data/full_repos/permissive/163494071/led/led.v
1: b'%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:37: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                 : ... In instance led\n  r_buf <= 255 - wheel_pos;\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:39: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'wheel_pos\' generates 16 bits.\n                                                                 : ... In instance led\n  b_buf <= wheel_pos;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:44: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                 : ... In instance led\n  g_buf <= (wheel_pos - 255);\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:45: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                 : ... In instance led\n  b_buf <= 255 - (wheel_pos - 255);\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:49: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                 : ... In instance led\n  r_buf <= (wheel_pos - 510);\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:50: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                 : ... In instance led\n  g_buf <= 255 - (wheel_pos - 510);\n        ^~\n%Error: Exiting due to 6 warning(s)\n'
module led(clk, rst_n, r, g, b);
input clk;
input rst_n;
output r, g, b;

reg [15:0] wheel_pos;
reg [7:0] r_buf,g_buf,b_buf;
reg [31:0] div_buffer;
wire clk;
reg div_clk;

pwm pwm_r(r, r_buf, clk);
pwm pwm_g(g, g_buf, clk);
pwm pwm_b(b, b_buf, clk);

always@(posedge clk)
begin
	if(div_buffer < 50000)
	begin
		div_buffer <= div_buffer + 1;
	end
	else
	begin
		div_clk <= ~div_clk;
		div_buffer <= 0;
	end
end

always@(posedge div_clk)
begin
	if(wheel_pos < 765)
		wheel_pos <= wheel_pos + 1;
	else
		wheel_pos <= 0;
	if(wheel_pos < 255)
	begin
		r_buf <= 255 - wheel_pos;
		g_buf <= 0;
		b_buf <= wheel_pos;
	end
	else if(wheel_pos < 510)
	begin
		r_buf <= 0;
		g_buf <= (wheel_pos - 255);
		b_buf <= 255 - (wheel_pos - 255);
	end
	else
	begin
		r_buf <= (wheel_pos - 510);
		g_buf <= 255 - (wheel_pos - 510);
		b_buf <= 0;
	end
end
endmodule
module led(clk, rst_n, r, g, b);

input clk;
input rst_n;
output r, g, b;

reg [15:0] wheel_pos;
reg [7:0] r_buf,g_buf,b_buf;
reg [31:0] div_buffer;
wire clk;
reg div_clk;

pwm pwm_r(r, r_buf, clk);
pwm pwm_g(g, g_buf, clk);
pwm pwm_b(b, b_buf, clk);

always@(posedge clk)
begin
	if(div_buffer < 50000)
	begin
		div_buffer <= div_buffer + 1;
	end
	else
	begin
		div_clk <= ~div_clk;
		div_buffer <= 0;
	end
end

always@(posedge div_clk)
begin
	if(wheel_pos < 765)
		wheel_pos <= wheel_pos + 1;
	else
		wheel_pos <= 0;
	if(wheel_pos < 255)
	begin
		r_buf <= 255 - wheel_pos;
		g_buf <= 0;
		b_buf <= wheel_pos;
	end
	else if(wheel_pos < 510)
	begin
		r_buf <= 0;
		g_buf <= (wheel_pos - 255);
		b_buf <= 255 - (wheel_pos - 255);
	end
	else
	begin
		r_buf <= (wheel_pos - 510);
		g_buf <= 255 - (wheel_pos - 510);
		b_buf <= 0;
	end
end
endmodule