data/full_repos/permissive/20688874/final/src/pipe3tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/20688874/final/src/pipe3tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk=0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/final/src/pipe3tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/final/src/pipe3tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/final/src/pipe3tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/final/src/pipe3tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/final/src/pipe3tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-LITENDIAN: data/full_repos/permissive/20688874/final/src/pipe3tb.v:9: Little bit endian vector: MSB < LSB of bit range: 0:127\n reg [0:127] dataOut_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/20688874/final/src/pipe3tb.v:10: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] wbyteen_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/20688874/final/src/pipe3tb.v:12: Little bit endian vector: MSB < LSB of bit range: 0:4\n reg [0:4] rwraddrd_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/20688874/final/src/pipe3tb.v:14: Little bit endian vector: MSB < LSB of bit range: 0:127\n reg [0:127] aluOut_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/20688874/final/src/pipe3tb.v:18: Little bit endian vector: MSB < LSB of bit range: 0:127\n wire [0:127] dataOut_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/20688874/final/src/pipe3tb.v:19: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] wbyteen_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/20688874/final/src/pipe3tb.v:21: Little bit endian vector: MSB < LSB of bit range: 0:4\n wire [0:4] rwraddrd_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/20688874/final/src/pipe3tb.v:23: Little bit endian vector: MSB < LSB of bit range: 0:127\n wire [0:127] aluOut_out;\n      ^\n%Error: data/full_repos/permissive/20688874/final/src/pipe3tb.v:26: Cannot find file containing module: \'pipe3\'\n pipe3 pipe3_1(dataOut_in, dataOut_out, wbyteen_in, wbyteen_out, \n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/final/src,data/full_repos/permissive/20688874/pipe3\n             data/full_repos/permissive/20688874/final/src,data/full_repos/permissive/20688874/pipe3.v\n             data/full_repos/permissive/20688874/final/src,data/full_repos/permissive/20688874/pipe3.sv\n             pipe3\n             pipe3.v\n             pipe3.sv\n             obj_dir/pipe3\n             obj_dir/pipe3.v\n             obj_dir/pipe3.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pipe3tb;
	

	reg [0:127] dataOut_in;
	reg [0:15] wbyteen_in;
	reg regwren_in;
	reg [0:4] rwraddrd_in;
	reg reginmuxop_in;
	reg [0:127] aluOut_in;
	reg clk, reset;
	

	wire [0:127] dataOut_out;
	wire [0:15] wbyteen_out;
	wire regwren_out;
	wire [0:4] rwraddrd_out;
	wire reginmuxop_out;
	wire [0:127] aluOut_out;
	

	pipe3 pipe3_1(dataOut_in, dataOut_out, wbyteen_in, wbyteen_out, 
		 regwren_in, regwren_out, rwraddrd_in, rwraddrd_out, 
		 reginmuxop_in, reginmuxop_out, aluOut_in, aluOut_out,
		 clk, reset);
	
	always
		begin
		#5 clk=0;
		#5 clk=1;
		end
		
	initial
		begin
		#5;
		reset=1'b1;
		#10;
		reset=1'b0;
		#10;
		dataOut_in<=128'hF0000000000000000000000000000000;
		wbyteen_in<=16'hF000;
		regwren_in<=1'b1;
		rwraddrd_in<=5'b10000;
		reginmuxop_in<=1'b1;
		aluOut_in<=128'hF0000000000000000000000000000000;
		#10;
		$finish;
		end
endmodule
module pipe3tb;

	

	reg [0:127] dataOut_in;
	reg [0:15] wbyteen_in;
	reg regwren_in;
	reg [0:4] rwraddrd_in;
	reg reginmuxop_in;
	reg [0:127] aluOut_in;
	reg clk, reset;
	

	wire [0:127] dataOut_out;
	wire [0:15] wbyteen_out;
	wire regwren_out;
	wire [0:4] rwraddrd_out;
	wire reginmuxop_out;
	wire [0:127] aluOut_out;
	

	pipe3 pipe3_1(dataOut_in, dataOut_out, wbyteen_in, wbyteen_out, 
		 regwren_in, regwren_out, rwraddrd_in, rwraddrd_out, 
		 reginmuxop_in, reginmuxop_out, aluOut_in, aluOut_out,
		 clk, reset);
	
	always
		begin
		#5 clk=0;
		#5 clk=1;
		end
		
	initial
		begin
		#5;
		reset=1'b1;
		#10;
		reset=1'b0;
		#10;
		dataOut_in<=128'hF0000000000000000000000000000000;
		wbyteen_in<=16'hF000;
		regwren_in<=1'b1;
		rwraddrd_in<=5'b10000;
		reginmuxop_in<=1'b1;
		aluOut_in<=128'hF0000000000000000000000000000000;
		#10;
		$finish;
		end
endmodule