data/full_repos/permissive/143278/ivltests/pr1925356.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1925356.v:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'ival\' generates 8 bits.\n                                                                        : ... In instance top\n    for(lp = ival; lp < 5; lp = lp + 1) begin\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top;
  reg pass = 1'b0;

  integer lp;
  reg [7:0] ival = 8'b0;

  initial begin

    for(lp = ival; lp < 5; lp = lp + 1) begin
      pass = 1'b1;
    end

    if(pass) $display("PASSED");
    else $display("FAILED");
  end
endmodule
module top;

  reg pass = 1'b0;

  integer lp;
  reg [7:0] ival = 8'b0;

  initial begin

    for(lp = ival; lp < 5; lp = lp + 1) begin
      pass = 1'b1;
    end

    if(pass) $display("PASSED");
    else $display("FAILED");
  end
endmodule