data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim/file_writer.v
 line:47: before: "integer"
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim/file_writer.v:24: Cannot find include file: stream_common.vh\n`include "stream_common.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh.sv\n             stream_common.vh\n             stream_common.vh.v\n             stream_common.vh.sv\n             obj_dir/stream_common.vh\n             obj_dir/stream_common.vh.v\n             obj_dir/stream_common.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module file_writer (clk, rst, wr_en, wr_data);
`include "stream_common.vh"

  parameter Filename     = "undefined";
  parameter NumSymbols  = 2;
  parameter SymbolBits  = {32'd8,32'd1};

  localparam TotalWidth = calc_total(NumSymbols, SymbolBits);

  input                   clk;
  input                   rst;
  input                   wr_en;
  input [TotalWidth-1:0] wr_data;





  integer fp;
  initial begin
    fp  = $fopen(Filename, "w");
    if (!fp) begin
      $display("Error: unable to create file %s", Filename);
      $display("***SIMULATION FAILED***");
      $finish;
    end
  end




  integer               col_val, col_width, i;
  reg [TotalWidth-1:0] data_i;

  always @(posedge clk) begin
    if (wr_en) begin
      data_i       = wr_data;
      for (i=NumSymbols-1; i >= 0; i=i-1) begin
        col_width  = get_symbol_width(NumSymbols, SymbolBits, i);
        col_val    = data_i >> (TotalWidth - col_width);
        data_i     = data_i << col_width;
        $fwrite(fp, "%0d", col_val);
        if (i > 0)
          $fwrite(fp, " ");
      end
      $fwrite(fp, "\n");
    end
  end

endmodule
module file_writer (clk, rst, wr_en, wr_data);

`include "stream_common.vh"

  parameter Filename     = "undefined";
  parameter NumSymbols  = 2;
  parameter SymbolBits  = {32'd8,32'd1};

  localparam TotalWidth = calc_total(NumSymbols, SymbolBits);

  input                   clk;
  input                   rst;
  input                   wr_en;
  input [TotalWidth-1:0] wr_data;





  integer fp;
  initial begin
    fp  = $fopen(Filename, "w");
    if (!fp) begin
      $display("Error: unable to create file %s", Filename);
      $display("***SIMULATION FAILED***");
      $finish;
    end
  end




  integer               col_val, col_width, i;
  reg [TotalWidth-1:0] data_i;

  always @(posedge clk) begin
    if (wr_en) begin
      data_i       = wr_data;
      for (i=NumSymbols-1; i >= 0; i=i-1) begin
        col_width  = get_symbol_width(NumSymbols, SymbolBits, i);
        col_val    = data_i >> (TotalWidth - col_width);
        data_i     = data_i << col_width;
        $fwrite(fp, "%0d", col_val);
        if (i > 0)
          $fwrite(fp, " ");
      end
      $fwrite(fp, "\n");
    end
  end

endmodule