data/full_repos/permissive/122924576/fifo.v
data/verilator_xmls/750f2c7d-e7eb-4daf-b983-3943d596dc95.xml
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);



parameter	DEPTH = 5,
		MAX_COUNT = 5'b11111,
		BUFFER_SIZE = 26;
		
input		clk;
input		rstp;
input [BUFFER_SIZE:0]	din;
input		readp;
input		writep;
output [BUFFER_SIZE:0]	dout;
output		emptyp;
output		fullp;


reg 		emptyp;
reg		fullp;






reg [(DEPTH-1):0]	tail;
reg [(DEPTH-1):0]	head;




reg [(DEPTH-1):0]	count;



reg [BUFFER_SIZE:0] fifomem[0:MAX_COUNT];




assign dout = (emptyp)?0:fifomem[tail];


always @(posedge clk) begin
   if (rstp == 1'b0 && writep == 1'b1 && fullp == 1'b0) begin
      fifomem[head] <= din;
   end
end
                  


always @(posedge clk) begin
   if (rstp == 1'b1) begin
      head <= 0;
   end
   else begin
      if (writep == 1'b1 && fullp == 1'b0) begin

         head <= head + 1;
      end
   end
end



always @(posedge clk) begin
   if (rstp == 1'b1) begin
      tail <= 0;
   end
   else begin
      if (readp == 1'b1 && emptyp == 1'b0) begin

         tail <= tail + 1;
      end
   end
end



always @(posedge clk) begin
   if (rstp == 1'b1) begin
      count <= 0;
   end
   else begin
      case ({readp, writep})
         2'b00: count <= count;
         2'b01: 

            if (count != MAX_COUNT) 
               count <= count + 1;
         2'b10: 

            if (count != 0)
               count <= count - 1;
         2'b11:

            count <= count;
      endcase
   end
end

         




always @(count) begin
   if (count == 0)
      emptyp <= 1'b1;
   else
      emptyp <= 1'b0;
end




always @(count) begin
   if (count == MAX_COUNT)
      fullp <= 1'b1;
   else
      fullp <= 1'b0;
end

endmodule
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);




parameter	DEPTH = 5,
		MAX_COUNT = 5'b11111,
		BUFFER_SIZE = 26;
		
input		clk;
input		rstp;
input [BUFFER_SIZE:0]	din;
input		readp;
input		writep;
output [BUFFER_SIZE:0]	dout;
output		emptyp;
output		fullp;


reg 		emptyp;
reg		fullp;






reg [(DEPTH-1):0]	tail;
reg [(DEPTH-1):0]	head;




reg [(DEPTH-1):0]	count;



reg [BUFFER_SIZE:0] fifomem[0:MAX_COUNT];




assign dout = (emptyp)?0:fifomem[tail];


always @(posedge clk) begin
   if (rstp == 1'b0 && writep == 1'b1 && fullp == 1'b0) begin
      fifomem[head] <= din;
   end
end
                  


always @(posedge clk) begin
   if (rstp == 1'b1) begin
      head <= 0;
   end
   else begin
      if (writep == 1'b1 && fullp == 1'b0) begin

         head <= head + 1;
      end
   end
end



always @(posedge clk) begin
   if (rstp == 1'b1) begin
      tail <= 0;
   end
   else begin
      if (readp == 1'b1 && emptyp == 1'b0) begin

         tail <= tail + 1;
      end
   end
end



always @(posedge clk) begin
   if (rstp == 1'b1) begin
      count <= 0;
   end
   else begin
      case ({readp, writep})
         2'b00: count <= count;
         2'b01: 

            if (count != MAX_COUNT) 
               count <= count + 1;
         2'b10: 

            if (count != 0)
               count <= count - 1;
         2'b11:

            count <= count;
      endcase
   end
end

         




always @(count) begin
   if (count == 0)
      emptyp <= 1'b1;
   else
      emptyp <= 1'b0;
end




always @(count) begin
   if (count == MAX_COUNT)
      fullp <= 1'b1;
   else
      fullp <= 1'b0;
end

endmodule