data/full_repos/permissive/107057345/7 Seg Display Synthesized/Design Task 2 synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v
1: b'%Error: Cannot find file containing module: Seg\n        ... Looked in:\n             data/full_repos/permissive/107057345/7/Seg\n             data/full_repos/permissive/107057345/7/Seg.v\n             data/full_repos/permissive/107057345/7/Seg.sv\n             Seg\n             Seg.v\n             Seg.sv\n             obj_dir/Seg\n             obj_dir/Seg.v\n             obj_dir/Seg.sv\n%Error: Cannot find file containing module: Display\n%Error: Cannot find file containing module: Synthesized/Design\n%Error: Cannot find file containing module: Task\n%Error: Cannot find file containing module: 2\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/7\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v\n%Error: Exiting due to 8 error(s)\n'
module dassign2 (




wdinA, wdinB, sub, wdout, ovunflow);



parameter wlen=15;
parameter dlen=3;
	



input   [wlen:0]   wdinA;
input   [wlen:0]   wdinB;





input   sub;
output  [wlen:0]  wdout;
output  ovunflow;




reg   [wlen:0]   out;
wire [dlen:0] d1inA, d2inA, d3inA, d4inA;
wire [dlen:0] d1inB, d2inB, d3inB, d4inB;
wire [dlen:0] d1out, d2out, d3out, d4out;
reg cin;
wire cout1,cout2,cout3,cout4;





assign {d4inA,d3inA,d2inA,d1inA} = wdinA;
assign {d4inB,d3inB,d2inB,d1inB} = wdinB;

assign wdout = {d4out,d3out,d2out,d1out};

deciadd dig1(d1inA, d1inB, sub, cin, d1out, cout1);
deciadd dig2(d2inA, d2inB, sub, cout1, d2out, cout2);
deciadd dig3(d3inA, d3inB, sub, cout2, d3out, cout3);
deciadd dig4(d4inA, d4inB, sub, cout3, d4out, cout4);

reg ovunflow;
reg firstpos, secpos, respos;
reg[3:0] signs;
  
  always @(sub or cin or cout4 or cout3 or d4inA or d4inB or d4out) begin
    begin
    	if(sub)
      cin = 1'b1;
  		else
    	 cin = 1'b0;
    end
  
      if(d4inA < 4'b0101)
        firstpos = 1'b1;
      else
        firstpos = 1'b0;
    
      if(d4inB < 4'b0101)
        secpos = 1'b1;
      else
        secpos = 1'b0;
    
      if(d4out < 4'b0101)
        respos = 1'b1;
      else
        respos = 1'b0;
    signs = {sub, firstpos, secpos, respos};
    
    case(signs)
      4'b0110:
        ovunflow = 1'b1;
      4'b0001:
        ovunflow = 1'b1;
      4'b1100:
        ovunflow = 1'b1;
      4'b1011:
        ovunflow = 1'b1;
      default: 
        ovunflow = 1'b0;
    endcase
      
  end
 
endmodule
module dassign2 (




wdinA, wdinB, sub, wdout, ovunflow);




parameter wlen=15;
parameter dlen=3;
	



input   [wlen:0]   wdinA;
input   [wlen:0]   wdinB;





input   sub;
output  [wlen:0]  wdout;
output  ovunflow;




reg   [wlen:0]   out;
wire [dlen:0] d1inA, d2inA, d3inA, d4inA;
wire [dlen:0] d1inB, d2inB, d3inB, d4inB;
wire [dlen:0] d1out, d2out, d3out, d4out;
reg cin;
wire cout1,cout2,cout3,cout4;





assign {d4inA,d3inA,d2inA,d1inA} = wdinA;
assign {d4inB,d3inB,d2inB,d1inB} = wdinB;

assign wdout = {d4out,d3out,d2out,d1out};

deciadd dig1(d1inA, d1inB, sub, cin, d1out, cout1);
deciadd dig2(d2inA, d2inB, sub, cout1, d2out, cout2);
deciadd dig3(d3inA, d3inB, sub, cout2, d3out, cout3);
deciadd dig4(d4inA, d4inB, sub, cout3, d4out, cout4);

reg ovunflow;
reg firstpos, secpos, respos;
reg[3:0] signs;
  
  always @(sub or cin or cout4 or cout3 or d4inA or d4inB or d4out) begin
    begin
    	if(sub)
      cin = 1'b1;
  		else
    	 cin = 1'b0;
    end
  
      if(d4inA < 4'b0101)
        firstpos = 1'b1;
      else
        firstpos = 1'b0;
    
      if(d4inB < 4'b0101)
        secpos = 1'b1;
      else
        secpos = 1'b0;
    
      if(d4out < 4'b0101)
        respos = 1'b1;
      else
        respos = 1'b0;
    signs = {sub, firstpos, secpos, respos};
    
    case(signs)
      4'b0110:
        ovunflow = 1'b1;
      4'b0001:
        ovunflow = 1'b1;
      4'b1100:
        ovunflow = 1'b1;
      4'b1011:
        ovunflow = 1'b1;
      default: 
        ovunflow = 1'b0;
    endcase
      
  end
 
endmodule