data/full_repos/permissive/102388603/uart_tx.v
 line:17: before: "integer"
1: b'%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:48: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'state\' generates 2 bits.\n                                                                 : ... In instance uart_tx\nassign ready = (state == idle) ? 1:0;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:56: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 3 bits.\n                                                                 : ... In instance uart_tx\n state <= idle;\n       ^~\n%Warning-SELRANGE: data/full_repos/permissive/102388603/uart_tx.v:73: Selection index out of range: 12:11 outside 10:0\n                                                                    : ... In instance uart_tx\n     dataUart[dataLen + 4:dataLen + 3] <= 2\'b11;\n             ^\n%Warning-SELRANGE: data/full_repos/permissive/102388603/uart_tx.v:80: Selection index out of range: 11:10 outside 10:0\n                                                                    : ... In instance uart_tx\n     dataUart[dataLen + 3:dataLen + 2] <= 2\'b11;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:82: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'send\' generates 3 bits.\n                                                                 : ... In instance uart_tx\n   state <= send;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:92: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 3 bits.\n                                                                 : ... In instance uart_tx\n   state <= idle;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:99: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'waitSnd\' generates 3 bits.\n                                                                 : ... In instance uart_tx\n   state <= waitSnd;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:108: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'send\' generates 3 bits.\n                                                                  : ... In instance uart_tx\n   state <= send;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:105: Operator GT expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'waitSndTimer\' generates 14 bits.\n                                                                  : ... In instance uart_tx\n  if(waitSndTimer > periodUart)\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:61: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n                                                                 : ... In instance uart_tx\n case(state)\n ^~~~\n%Error: Exiting due to 10 warning(s)\n'
module uart_tx #(
parameter T = 9600,
par = 0,
parType = 0,
stop = 1,
dataLen = 8)
(	input clk,
	input rst,
	input [dataLen-1:0]data,
	input start,
	output ready,
	output reg dataOut);

function integer log2;
input integer value;
begin
	for (log2=0; value>0; log2=log2+1)
		value = value>>1;
end
endfunction


parameter F_clk_Gz = 100_000_000;

parameter periodUart = F_clk_Gz/T;

parameter dataLenUart = dataLen + stop + 1 + par;

reg [log2(periodUart)-1:0]waitSndTimer;


reg [dataLenUart:0]dataUart;


reg [1:0]state;
parameter idle		= 3'b00;
parameter send		= 3'b01;
parameter waitSnd	= 3'b10;
parameter parity	= 3'b11;

reg [3:0]countBitSend;




assign ready = (state == idle) ? 1:0;

always @(posedge clk, posedge rst)
if(rst)
begin
	dataOut <= 1;
	dataUart <= 0;
	countBitSend <= 0;
	state <= idle;
	waitSndTimer <= 0;
end
else
begin
	case(state)
	idle:
	begin
		if(start)
		begin
			dataUart[dataLen:0] <= {data, 1'b0};
			if(par == 1)
			begin
				dataUart[dataLen + 1] <= ^data;
				if(stop == 1)
					dataUart[dataLen + 2] <= 1;
				else if(stop == 2)
					dataUart[dataLen + 4:dataLen + 3] <= 2'b11;
			end
			else if(par == 0)
			begin
				if(stop == 1)
					dataUart[dataLen + 1] <= 1;
				else if(stop == 2)
					dataUart[dataLen + 3:dataLen + 2] <= 2'b11;
			end
			state <= send;
		end
	end
	
	send:
	begin
		if(countBitSend > dataLenUart - 1)
		begin
			countBitSend <= 0;
			dataOut <= 1;
			state <= idle;
		end
		else
		begin
			dataUart <= dataUart >> 1;
			dataOut <= dataUart[0];
			countBitSend <= countBitSend + 1;
			state <= waitSnd;
		end
	end
	
	waitSnd:
	begin
		if(waitSndTimer > periodUart)
		begin
			waitSndTimer <= 0;
			state <= send;
		end
		else
			waitSndTimer <= waitSndTimer + 1;
	end
	endcase
end


endmodule
module uart_tx #(
parameter T = 9600,
par = 0,
parType = 0,
stop = 1,
dataLen = 8)
(	input clk,
	input rst,
	input [dataLen-1:0]data,
	input start,
	output ready,
	output reg dataOut);


function integer log2;
input integer value;
begin
	for (log2=0; value>0; log2=log2+1)
		value = value>>1;
end
endfunction


parameter F_clk_Gz = 100_000_000;

parameter periodUart = F_clk_Gz/T;

parameter dataLenUart = dataLen + stop + 1 + par;

reg [log2(periodUart)-1:0]waitSndTimer;


reg [dataLenUart:0]dataUart;


reg [1:0]state;
parameter idle		= 3'b00;
parameter send		= 3'b01;
parameter waitSnd	= 3'b10;
parameter parity	= 3'b11;

reg [3:0]countBitSend;




assign ready = (state == idle) ? 1:0;

always @(posedge clk, posedge rst)
if(rst)
begin
	dataOut <= 1;
	dataUart <= 0;
	countBitSend <= 0;
	state <= idle;
	waitSndTimer <= 0;
end
else
begin
	case(state)
	idle:
	begin
		if(start)
		begin
			dataUart[dataLen:0] <= {data, 1'b0};
			if(par == 1)
			begin
				dataUart[dataLen + 1] <= ^data;
				if(stop == 1)
					dataUart[dataLen + 2] <= 1;
				else if(stop == 2)
					dataUart[dataLen + 4:dataLen + 3] <= 2'b11;
			end
			else if(par == 0)
			begin
				if(stop == 1)
					dataUart[dataLen + 1] <= 1;
				else if(stop == 2)
					dataUart[dataLen + 3:dataLen + 2] <= 2'b11;
			end
			state <= send;
		end
	end
	
	send:
	begin
		if(countBitSend > dataLenUart - 1)
		begin
			countBitSend <= 0;
			dataOut <= 1;
			state <= idle;
		end
		else
		begin
			dataUart <= dataUart >> 1;
			dataOut <= dataUart[0];
			countBitSend <= countBitSend + 1;
			state <= waitSnd;
		end
	end
	
	waitSnd:
	begin
		if(waitSndTimer > periodUart)
		begin
			waitSndTimer <= 0;
			state <= send;
		end
		else
			waitSndTimer <= waitSndTimer + 1;
	end
	endcase
end


endmodule