data/full_repos/permissive/163115503/moving_light/top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/163115503/moving_light/top.v:16: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s MUL generates 32 or 14 bits.\n                                                                          : ... In instance top\n  ms_to_clockcycles = ms * 16000;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/163115503/moving_light/top.v:45: Bit extraction of var[4:0] requires 3 bit index, not 8 bits.\n                                                                          : ... In instance top\n    led_states[i] = led_states[i-1];\n              ^\n%Error: Exiting due to 2 warning(s)\n'
module top (
    input CLK,
	input PIN_1,
	output PIN_10,
	output PIN_11,
	output PIN_12,
	output PIN_13,
	output LED,
    output USBPU
);

    assign USBPU = 0;

	function ms_to_clockcycles;
		input ms;
		ms_to_clockcycles = ms * 16000;
	endfunction


	reg[4:0] led_states = 5'b00001;
	reg [7:0] i;


	reg [31:0] cycle_period = 16000000;
	
	reg [31:0] clk_count;
	reg button_flag;



	assign PIN_10 = led_states[0];
	assign PIN_11 = led_states[1];
	assign PIN_12 = led_states[2];
	assign PIN_13 = led_states[3];

	assign LED = PIN_1;

    always @(posedge CLK) begin
		clk_count = clk_count + 1;
		if (PIN_1) button_flag = 1;
		if (clk_count >= cycle_period) begin
			clk_count = 0;

			for (i = 4; i >= 1; i = i - 1) begin
				led_states[i] = led_states[i-1];
			end
			led_states[0] = button_flag;
			button_flag = 0;

		end
    end
endmodule
module top (
    input CLK,
	input PIN_1,
	output PIN_10,
	output PIN_11,
	output PIN_12,
	output PIN_13,
	output LED,
    output USBPU
);


    assign USBPU = 0;

	function ms_to_clockcycles;
		input ms;
		ms_to_clockcycles = ms * 16000;
	endfunction


	reg[4:0] led_states = 5'b00001;
	reg [7:0] i;


	reg [31:0] cycle_period = 16000000;
	
	reg [31:0] clk_count;
	reg button_flag;



	assign PIN_10 = led_states[0];
	assign PIN_11 = led_states[1];
	assign PIN_12 = led_states[2];
	assign PIN_13 = led_states[3];

	assign LED = PIN_1;

    always @(posedge CLK) begin
		clk_count = clk_count + 1;
		if (PIN_1) button_flag = 1;
		if (clk_count >= cycle_period) begin
			clk_count = 0;

			for (i = 4; i >= 1; i = i - 1) begin
				led_states[i] = led_states[i-1];
			end
			led_states[0] = button_flag;
			button_flag = 0;

		end
    end
endmodule