data/full_repos/permissive/165514176/Mat_mult.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/165514176/Mat_mult.v:43: Cannot find file containing module: 'div'\n div divider (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/165514176,data/full_repos/permissive/165514176/div\n             data/full_repos/permissive/165514176,data/full_repos/permissive/165514176/div.v\n             data/full_repos/permissive/165514176,data/full_repos/permissive/165514176/div.sv\n             div\n             div.v\n             div.sv\n             obj_dir/div\n             obj_dir/div.v\n             obj_dir/div.sv\n%Error: Exiting due to 1 error(s)\n"
module Mat_mult(A,B,clk,Res);
	parameter widthbig = 127; 
	parameter width = 31;


    input signed [127:0] A;
    input signed[127:0] B;
    output signed [127:0] Res;

    reg signed [127:0] Res;
    reg signed [31:0] A1 [0:1][0:1];
    reg signed [31:0] B1 [0:1][0:1];
    reg signed [31:0] Res1 [0:1][0:1];  
	 reg signed [31:0]temp1= 32'd25;
	 reg signed [31:0]temp2 = 32'd5;
	 	 reg signed go = 1'b1;
    integer i,j,k;
	 wire [63:0] divout;
	 wire valid;
    input clk;
	div divider (
  .aclk(clk),
  .s_axis_divisor_tvalid(go),
  .s_axis_divisor_tdata(temp2),
  .s_axis_dividend_tvalid(go),
  .s_axis_dividend_tdata(temp1),
  .m_axis_dout_tvalid(valid),
  .m_axis_dout_tdata(divout)
		);	 
    always@ (A or B)
    begin

        {A1[0][0],A1[0][1],A1[1][0],A1[1][1]} = A;
        {B1[0][0],B1[0][1],B1[1][0],B1[1][1]} = B;
        i = 0;
        j = 0;
        k = 0;
        {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]} = 128'd0;

        for(i=0;i < 2;i=i+1)
            for(j=0;j < 2;j=j+1)
                for(k=0;k < 2;k=k+1)
                    Res1[i][j] = Res1[i][j] + (A1[i][k] * B1[k][j]);

        Res = {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]};     
    end 

endmodule
module Mat_mult(A,B,clk,Res);

	parameter widthbig = 127; 
	parameter width = 31;


    input signed [127:0] A;
    input signed[127:0] B;
    output signed [127:0] Res;

    reg signed [127:0] Res;
    reg signed [31:0] A1 [0:1][0:1];
    reg signed [31:0] B1 [0:1][0:1];
    reg signed [31:0] Res1 [0:1][0:1];  
	 reg signed [31:0]temp1= 32'd25;
	 reg signed [31:0]temp2 = 32'd5;
	 	 reg signed go = 1'b1;
    integer i,j,k;
	 wire [63:0] divout;
	 wire valid;
    input clk;
	div divider (
  .aclk(clk),
  .s_axis_divisor_tvalid(go),
  .s_axis_divisor_tdata(temp2),
  .s_axis_dividend_tvalid(go),
  .s_axis_dividend_tdata(temp1),
  .m_axis_dout_tvalid(valid),
  .m_axis_dout_tdata(divout)
		);	 
    always@ (A or B)
    begin

        {A1[0][0],A1[0][1],A1[1][0],A1[1][1]} = A;
        {B1[0][0],B1[0][1],B1[1][0],B1[1][1]} = B;
        i = 0;
        j = 0;
        k = 0;
        {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]} = 128'd0;

        for(i=0;i < 2;i=i+1)
            for(j=0;j < 2;j=j+1)
                for(k=0;k < 2;k=k+1)
                    Res1[i][j] = Res1[i][j] + (A1[i][k] * B1[k][j]);

        Res = {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]};     
    end 

endmodule