data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v
1: b'%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:757: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h2a\' generates 6 bits.\n                                                                              : ... In instance pipeline_riscv.ALU\n    case (alu_code)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:526: Operator EQ expects 6 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                              : ... In instance pipeline_riscv.CTRL\n    if (rd[1]!=0 && ((J_type[1] && funct[1]==7\'h08) || S_type[1]==6\'h2B)) begin\n                                                                ^~\n%Error: Exiting due to 2 warning(s)\n'
module alu (
  input signed      [31:0]  opA,
  input signed      [31:0]  opB,
  output reg signed [31:0]  res,
  input             [6:0]   alu_code,
  output                    z
  );
  

  
  reg valid;
  assign z = (~|res)&valid;
  
  always@(*) begin
    valid = 1;
    case (alu_code)
      7'h20: begin
        res = opA + opB;
      end
      7'h22: begin
        res = opA - opB;
      end

      7'h0A, 6'h2A:
        if (opA < opB)
          res = 1;
        else
          res = 0;
      default: begin
        res = 0;
        valid = 0;
      end
    endcase
  end
endmodule
module alu (
  input signed      [31:0]  opA,
  input signed      [31:0]  opB,
  output reg signed [31:0]  res,
  input             [6:0]   alu_code,
  output                    z
  );

  

  
  reg valid;
  assign z = (~|res)&valid;
  
  always@(*) begin
    valid = 1;
    case (alu_code)
      7'h20: begin
        res = opA + opB;
      end
      7'h22: begin
        res = opA - opB;
      end

      7'h0A, 6'h2A:
        if (opA < opB)
          res = 1;
        else
          res = 0;
      default: begin
        res = 0;
        valid = 0;
      end
    endcase
  end
endmodule