data/full_repos/permissive/198139336/DDLab5_forStudent/cont_8bit_adder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/198139336/DDLab5_forStudent/cont_8bit_adder.v:11: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                           : ... In instance cont_8bit_adder\n    assign {cout,sum} = a+b+cin;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module cont_8bit_adder(sum, cout, a, b, cin);

    input [7:0] a, b;
    input cin;
    output [7:0] sum;
    output cout;
    

    assign {cout,sum} = a+b+cin;
    
endmodule
module cont_8bit_adder(sum, cout, a, b, cin);


    input [7:0] a, b;
    input cin;
    output [7:0] sum;
    output cout;
    

    assign {cout,sum} = a+b+cin;
    
endmodule