data/full_repos/permissive/120518070/main/source/outputToXor.sv
data/verilator_xmls/215fc2df-dc14-4d29-863f-31ac37066671.xml
module outputToXor(
	input wire clk,
	input wire [7:0] rdata_i,
	input wire end_i,
	output reg [7:0] outputToXor_o
);



always_ff @(posedge clk)
begin
	if (end_i == 1)
	begin
		outputToXor_o <= rdata_i;
	end
	else
	begin
		outputToXor_o <= outputToXor_o;
	end
end
endmodule
module outputToXor(
	input wire clk,
	input wire [7:0] rdata_i,
	input wire end_i,
	output reg [7:0] outputToXor_o
);




always_ff @(posedge clk)
begin
	if (end_i == 1)
	begin
		outputToXor_o <= rdata_i;
	end
	else
	begin
		outputToXor_o <= outputToXor_o;
	end
end
endmodule