data/full_repos/permissive/184916587/CPU.v
 line:37: before: "data"
1: b"%Error: data/full_repos/permissive/184916587/CPU.v:17: Cannot find file containing module: 'AGU'\n AGU agu(\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/184916587,data/full_repos/permissive/184916587/AGU\n             data/full_repos/permissive/184916587,data/full_repos/permissive/184916587/AGU.v\n             data/full_repos/permissive/184916587,data/full_repos/permissive/184916587/AGU.sv\n             AGU\n             AGU.v\n             AGU.sv\n             obj_dir/AGU\n             obj_dir/AGU.v\n             obj_dir/AGU.sv\n%Error: data/full_repos/permissive/184916587/CPU.v:23: Cannot find file containing module: 'IMemory'\n IMemory imemory(\n ^~~~~~~\n%Error: data/full_repos/permissive/184916587/CPU.v:28: Cannot find file containing module: 'decoder'\n decoder decoder(\n ^~~~~~~\n%Error: data/full_repos/permissive/184916587/CPU.v:36: Cannot find file containing module: 'Regfile'\n Regfile regfile_1(\n ^~~~~~~\n%Error: data/full_repos/permissive/184916587/CPU.v:44: Cannot find file containing module: 'ALU'\n ALU alu(\n ^~~\n%Error: data/full_repos/permissive/184916587/CPU.v:51: Cannot find file containing module: 'DMemory'\n DMemory dmemory(\n ^~~~~~~\n%Error: data/full_repos/permissive/184916587/CPU.v:58: Cannot find file containing module: 'Regfile'\n Regfile regfile_3(\n ^~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module CPU(
	input Reset,
	input PCWre
);
	wire[31:0] address;
	wire[31:0] instr;
	wire[9:0] alu_op;
	wire[4:0] rs1;
	wire[4:0] rs2;
	wire[4:0] rd;
	wire State_r=1;
	wire State_w=0;
	wire[31:0] rs1_data,rs2_data,rd_data;
	wire Delete=0;


	AGU agu(
		._Rest(Reset),
		.PCWre(PCWre),
		.address(address)
	);

	IMemory imemory(
		.address(address),
		.instr(instr)
	);

	decoder decoder(
		.instr(instr),
		.alu_op(alu_op),
		.rs1(rs1),
		.rs2(rs2),
		.rd(rd)
	);

	Regfile regfile_1(
		.State(State_r),
		.address_1(rs1),
		.address_2(rs2),
		.data_1(rs1_data),
		.data_2(rs2_data)
	);

	ALU alu(
		.rs1_num(rs1_data),
		.rs2_num(rs2_data),
		.alu_op(alu_op),
		.rd_num(rd_data)
	);

	DMemory dmemory(
		.Delete(Delete),
		.State(State_w),
		.data_w(rd_data),
		.address(rd)
	);

	Regfile regfile_3(
		.State(State_w),
		.address_1(rd),
		.data_w(rd_data)
	);
endmodule
module CPU(
	input Reset,
	input PCWre
);

	wire[31:0] address;
	wire[31:0] instr;
	wire[9:0] alu_op;
	wire[4:0] rs1;
	wire[4:0] rs2;
	wire[4:0] rd;
	wire State_r=1;
	wire State_w=0;
	wire[31:0] rs1_data,rs2_data,rd_data;
	wire Delete=0;


	AGU agu(
		._Rest(Reset),
		.PCWre(PCWre),
		.address(address)
	);

	IMemory imemory(
		.address(address),
		.instr(instr)
	);

	decoder decoder(
		.instr(instr),
		.alu_op(alu_op),
		.rs1(rs1),
		.rs2(rs2),
		.rd(rd)
	);

	Regfile regfile_1(
		.State(State_r),
		.address_1(rs1),
		.address_2(rs2),
		.data_1(rs1_data),
		.data_2(rs2_data)
	);

	ALU alu(
		.rs1_num(rs1_data),
		.rs2_num(rs2_data),
		.alu_op(alu_op),
		.rd_num(rd_data)
	);

	DMemory dmemory(
		.Delete(Delete),
		.State(State_w),
		.data_w(rd_data),
		.address(rd)
	);

	Regfile regfile_3(
		.State(State_w),
		.address_1(rd),
		.data_w(rd_data)
	);
endmodule