data/full_repos/permissive/137454634/count.v
None: at end of input
1: b'%Warning-MULTITOP: data/full_repos/permissive/137454634/count.v:40: Multiple top level modules\n                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                  : ... Top module \'counter_run\'\nmodule counter_run(endRun,CP,CP_H,StRun);\n       ^~~~~~~~~~~\n                                                                  : ... Top module \'counter_open\'\nmodule counter_open(endOpen,dispStage,CP,StOpen,pause,close);\n       ^~~~~~~~~~~~\n                                                                  : ... Top module \'delaybutton\'\nmodule delaybutton(pause,CP,delay);\n       ^~~~~~~~~~~\n                                                                  : ... Top module \'divideclk\'\nmodule divideclk(clk4hz,clk32hz,StRun,StOpen);\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module counter_open(endOpen,dispStage,CP,StOpen,pause,close);

	input CP,StOpen,pause,close;	
	output reg endOpen;
	output reg [1:0] dispStage=2'b00;
	reg [6:0] count;
	reg [6:0] endTime = 7'b0010101;

	always @ (posedge CP)
		if(!StOpen) begin count <= 7'b0000000;endOpen<=0;dispStage<=2'b00; end
		else
			begin
			if(count == endTime)
				begin count<=7'd0;endOpen<=1;dispStage<=2'b00; end
			else if (close)count = endTime-7'b0000011;
            else if (pause)endTime <= endTime;
			else
				begin 
				count<=count+1'd1;endOpen<=0;
				if (count == 7'd1)dispStage<=2'b01;
				else if (count == 7'd2)dispStage<=2'b10;
				else if (count == 7'd3)dispStage<=2'b11;
				else if (count == endTime-7'b0000010)dispStage<=2'b10;
				else if (count == endTime-7'b0000001)dispStage<=2'b01;
				end
			end

endmodule
module counter_open(endOpen,dispStage,CP,StOpen,pause,close);


	input CP,StOpen,pause,close;	
	output reg endOpen;
	output reg [1:0] dispStage=2'b00;
	reg [6:0] count;
	reg [6:0] endTime = 7'b0010101;

	always @ (posedge CP)
		if(!StOpen) begin count <= 7'b0000000;endOpen<=0;dispStage<=2'b00; end
		else
			begin
			if(count == endTime)
				begin count<=7'd0;endOpen<=1;dispStage<=2'b00; end
			else if (close)count = endTime-7'b0000011;
            else if (pause)endTime <= endTime;
			else
				begin 
				count<=count+1'd1;endOpen<=0;
				if (count == 7'd1)dispStage<=2'b01;
				else if (count == 7'd2)dispStage<=2'b10;
				else if (count == 7'd3)dispStage<=2'b11;
				else if (count == endTime-7'b0000010)dispStage<=2'b10;
				else if (count == endTime-7'b0000001)dispStage<=2'b01;
				end
			end

endmodule