data/full_repos/permissive/154371523/Code/rtl/xctrl.v
None: at end of input
1: b'%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:3: Cannot find include file: xdefs.vh\n`include "xdefs.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh.v\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh.sv\n             xdefs.vh\n             xdefs.vh.v\n             xdefs.vh.sv\n             obj_dir/xdefs.vh\n             obj_dir/xdefs.vh.v\n             obj_dir/xdefs.vh.sv\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:4: Cannot find include file: xctrldefs.vh\n`include "xctrldefs.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:5: Cannot find include file: xprogdefs.vh\n`include "xprogdefs.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:12: Define or directive not defined: \'`PROG_ADDR_W\'\n       output reg [`PROG_ADDR_W-1:0] pc,\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:13: Define or directive not defined: \'`INSTR_W\'\n       input [`INSTR_W-1:0]      instruction,\n              ^~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:18: Define or directive not defined: \'`ADDR_W\'\n       output reg [`ADDR_W-1:0]      data_addr,\n                   ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:19: Define or directive not defined: \'`DATA_W\'\n       input [`DATA_W-1:0]      data_to_rd,\n              ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:20: Define or directive not defined: \'`DATA_W\'\n       output [`DATA_W-1:0]      data_to_wr\n               ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:23: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0]      data_to_rd_int;\n        ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:25: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0]      regA;\n        ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:26: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0]      regA_nxt;\n        ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:27: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W:0]      temp_regA;\n        ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:27: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   reg [`DATA_W:0]      temp_regA;\n               ^\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:33: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0]      regB;\n        ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:34: Define or directive not defined: \'`DATA_W\'\n   wire [`DATA_W-1:0]      regB_nxt;\n         ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:35: Define or directive not defined: \'`ADDR_W\'\n   wire [`ADDR_W-1:0]      addr_from_regB;\n         ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:38: Define or directive not defined: \'`DATA_W\'\n   wire [`DATA_W-1:0]      regC;\n         ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:47: Define or directive not defined: \'`PROG_ADDR_W\'\n   reg [`PROG_ADDR_W-1:0]     pc_nxt;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:50: Define or directive not defined: \'`OPCODESZ\'\n   wire [`OPCODESZ-1 :0]     opcode;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:51: Define or directive not defined: \'`ADDR_W\'\n   wire [`ADDR_W-1:0]      addrint;\n         ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:52: Define or directive not defined: \'`DATA_W\'\n   wire signed [`DATA_W-1:0]     imm;\n                ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:57: Define or directive not defined: \'`INSTR_W\'\n   assign opcode  = instruction[`INSTR_W-1 -: `OPCODESZ];\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:57: Define or directive not defined: \'`OPCODESZ\'\n   assign opcode  = instruction[`INSTR_W-1 -: `OPCODESZ];\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign opcode  = instruction[`INSTR_W-1 -: `OPCODESZ];\n                                                       ^\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:58: Define or directive not defined: \'`ADDR_W\'\n   assign addrint = instruction[`ADDR_W-1:0];\n                                ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:59: Define or directive not defined: \'`DATA_W\'\n   assign imm     = {{(`DATA_W-`IMM_W){instruction[`IMM_W-1]}},instruction[`IMM_W-1:0]};\n                       ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:59: Define or directive not defined: \'`IMM_W\'\n   assign imm     = {{(`DATA_W-`IMM_W){instruction[`IMM_W-1]}},instruction[`IMM_W-1:0]};\n                               ^~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:59: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign imm     = {{(`DATA_W-`IMM_W){instruction[`IMM_W-1]}},instruction[`IMM_W-1:0]};\n                                     ^\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:59: Define or directive not defined: \'`IMM_W\'\n   assign imm     = {{(`DATA_W-`IMM_W){instruction[`IMM_W-1]}},instruction[`IMM_W-1:0]};\n                                                   ^~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:59: Define or directive not defined: \'`IMM_W\'\n   assign imm     = {{(`DATA_W-`IMM_W){instruction[`IMM_W-1]}},instruction[`IMM_W-1:0]};\n                                                                           ^~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:67: Define or directive not defined: \'`ADDR_W\'\n   assign addr_from_regB = regB[`ADDR_W-1:0];\n                                ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:70: Define or directive not defined: \'`DATA_W\'\n   assign regC = {negative, overflow,{(`DATA_W-3){1\'b0}},carry};\n                                       ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:75: Define or directive not defined: \'`RB\'\n      if (data_addr == `RB) begin\n                       ^~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:75: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (data_addr == `RB) begin\n                          ^\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:78: syntax error, unexpected else\n      end else if (data_addr == `RC)\n          ^~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:78: Define or directive not defined: \'`RC\'\n      end else if (data_addr == `RC)\n                                ^~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:87: Define or directive not defined: \'`DATA_W\'\n  regA <= `DATA_W\'d0;\n          ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:88: Define or directive not defined: \'`PROG_ROM\'\n  pc   <= `PROG_ROM;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:93: syntax error, unexpected <=, expecting IDENTIFIER\n    regB <= regB_nxt;     \n         ^~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:109: Define or directive not defined: \'`RDW\'\n `RDW: begin\n ^~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:109: syntax error, unexpected \':\', expecting endcase\n `RDW: begin\n     ^\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:112: Define or directive not defined: \'`RDWB\'\n `RDWB: begin\n ^~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:115: Define or directive not defined: \'`SHFT\'\n `SHFT: begin\n ^~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:116: Define or directive not defined: \'`DATA_W\'\n    if ( imm[`DATA_W-1] ) begin\n             ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:118: Define or directive not defined: \'`DATA_W\'\n       carry_nxt   = regA[`DATA_W-1];\n                          ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:124: Define or directive not defined: \'`BEQI\'\n `BEQI: begin\n ^~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:125: Define or directive not defined: \'`DATA_W\'\n    regA_nxt = regA - `DATA_W\'d1;\n                      ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:126: Define or directive not defined: \'`DATA_W\'\n    if ( regA == `DATA_W\'d0 )\n                 ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:127: syntax error, unexpected \'=\', expecting IDENTIFIER\n      pc_nxt = pc + imm[`PROG_ADDR_W:0];\n             ^\n%Error: data/full_repos/permissive/154371523/Code/rtl/xctrl.v:127: Define or directive not defined: \'`PROG_ADDR_W\'\n      pc_nxt = pc + imm[`PROG_ADDR_W:0];\n                        ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module xctrl (
	      input 			    clk,
	      input 			    rst,
	      

	      output reg [`PROG_ADDR_W-1:0] pc,
	      input [`INSTR_W-1:0] 	    instruction,
	      

	      output reg		    data_sel,
	      output reg 		    data_we,
	      output reg [`ADDR_W-1:0] 	    data_addr,
	      input [`DATA_W-1:0] 	    data_to_rd,
	      output [`DATA_W-1:0] 	    data_to_wr
	      );
   
   reg [`DATA_W-1:0] 			  data_to_rd_int;
   
   reg [`DATA_W-1:0] 			  regA;
   reg [`DATA_W-1:0] 			  regA_nxt;
   reg [`DATA_W:0] 			  temp_regA;



   reg 					  regB_sel;
   wire 				  regB_we;
   reg [`DATA_W-1:0] 			  regB;
   wire [`DATA_W-1:0] 			  regB_nxt;
   wire [`ADDR_W-1:0] 			  addr_from_regB;


   wire [`DATA_W-1:0] 			  regC;
   reg 					  carry;
   reg 					  carry_nxt;
   reg 					  overflow;
   reg 					  overflow_nxt;
   reg 					  negative;
   wire 				  negative_nxt;
 				  

   reg [`PROG_ADDR_W-1:0] 		  pc_nxt;
   

   wire [`OPCODESZ-1 :0] 		  opcode;
   wire [`ADDR_W-1:0] 			  addrint;
   wire signed [`DATA_W-1:0] 		  imm;

   
    

   assign opcode  = instruction[`INSTR_W-1 -: `OPCODESZ];
   assign addrint = instruction[`ADDR_W-1:0];
   assign imm     = {{(`DATA_W-`IMM_W){instruction[`IMM_W-1]}},instruction[`IMM_W-1:0]};


   assign data_to_wr = regA;


   assign regB_we = regB_sel & data_we;
   assign regB_nxt = regB_we ? data_to_wr : regB;
   assign addr_from_regB = regB[`ADDR_W-1:0];


   assign regC = {negative, overflow,{(`DATA_W-3){1'b0}},carry};
   

   always @ * begin
      regB_sel = 1'b0;
      if (data_addr == `RB) begin
	 regB_sel = 1'b1;
         data_to_rd_int = regB;
      end else if (data_addr == `RC)
	data_to_rd_int = regC;
      else
        data_to_rd_int = data_to_rd;
   end
   

   always @ (posedge clk) begin
      if (rst) begin
	 regA <= `DATA_W'd0;
	 pc   <= `PROG_ROM;
      end else begin
	 regA <= regA_nxt;
	 pc   <= pc_nxt;
	 if(regB_we)
	   regB <= regB_nxt;     
	 negative <= negative_nxt;
 	 overflow <= overflow_nxt;
	 carry   <= carry_nxt;
     end
   end



   always @ * begin

      regA_nxt = regA;
      carry_nxt   = carry;
      pc_nxt   = pc + 1'b1;
   
      case (opcode)
	`RDW: begin
	   regA_nxt = data_to_rd_int;
	end
	`RDWB: begin
	   regA_nxt = data_to_rd_int;
	end
	`SHFT: begin
	   if ( imm[`DATA_W-1] ) begin
	      regA_nxt = regA << 1'b1;
	      carry_nxt   = regA[`DATA_W-1];
	   end else begin
	      regA_nxt = regA >> 1'b1;
	      carry_nxt   = regA[0];
	   end
	end
	`BEQI: begin
	   regA_nxt = regA - `DATA_W'd1;
	   if ( regA == `DATA_W'd0 )
	     pc_nxt = pc + imm[`PROG_ADDR_W:0];
	end
	`BEQ: begin
	   regA_nxt = regA - `DATA_W'd1;
	   if ( regA == `DATA_W'd0 )
	     pc_nxt = regB[`PROG_ADDR_W:0];
	end
	`BNEQI: begin
	   regA_nxt = regA - `DATA_W'd1;
	   if ( regA != `DATA_W'd0 )
	     pc_nxt = pc + imm[`PROG_ADDR_W:0];
	end
	`BNEQ: begin
	   regA_nxt = regA - `DATA_W'd1;
	   if ( regA != `DATA_W'd0 )
	     pc_nxt = regB[`PROG_ADDR_W:0];
	end
	`LDI: begin
	   regA_nxt = imm;
	end
	`LDIH: begin
	   regA_nxt = {imm[`DATA_W-`IMM_W-1:0],regA[`IMM_W-1:0]};
	end
	`ADD: begin
	   regA_nxt  = temp_regA[`DATA_W-1:0];
	   carry_nxt    = temp_regA[`DATA_W];
	end
	`SUB: begin
	   regA_nxt  = temp_regA[`DATA_W-1:0];
	   carry_nxt    = temp_regA[`DATA_W];
	end
	`ADDI: begin
	   regA_nxt  = temp_regA[`DATA_W-1:0];
	   carry_nxt    = temp_regA[`DATA_W];
	end
	`AND: begin
	   regA_nxt = regA & data_to_rd_int;
	end
	`XOR: begin
	   regA_nxt = regA ^ data_to_rd_int;
	end
	default:
	  pc_nxt = pc + 1'b1;
      endcase
   end


   assign negative_nxt =  temp_regA[`DATA_W-1];
   

   always @* begin
      case (opcode)
	`ADD: begin
	   overflow_nxt = temp_regA[`DATA_W-1] & ~regA[`DATA_W-1] & ~data_to_rd_int[`DATA_W-1];
	end
	`SUB: begin
	   overflow_nxt = temp_regA[`DATA_W-1] & ~regA[`DATA_W-1] & ~data_to_rd_int[`DATA_W-1];
	end
	`ADDI: begin
	   overflow_nxt = temp_regA[`DATA_W-1] & ~regA[`DATA_W-1] & ~imm[`DATA_W-1];
	end
	default:  begin
	   overflow_nxt = 1'b0;
	end
      endcase
   end



   always @* begin
      case (opcode)
	`ADD: begin
	   temp_regA = regA + data_to_rd_int;
	end
	`SUB: begin
	   temp_regA = regA - data_to_rd_int;
	end
	`ADDI: begin
	   temp_regA = regA + imm;
	end
	default:  begin
	  temp_regA = regA + data_to_rd_int;
	end
      endcase
   end

   

   always @ * begin

      data_sel  = 1'b0;
      data_we  = 1'b0;
      data_addr = addrint;
      
      case (opcode)
	`RDW: begin 
	   data_sel  = (addrint >= `REGF_BASE);
	end
	`RDWB: begin
	   data_sel  = (addrint >= `REGF_BASE);
	   data_addr = addr_from_regB + imm;
	end
	`WRW: begin
	   data_sel  = (addrint >= `REGF_BASE);
	   data_we  = 1'b1;
	end
	`WRWB: begin
	   data_sel  = (addrint >= `REGF_BASE);
	   data_we = 1'b1;
	   data_addr = addr_from_regB + imm;
	end
	default:
	     data_we  = 1'b0;
      endcase
   end
   
endmodule
module xctrl (
	      input 			    clk,
	      input 			    rst,
	      

	      output reg [`PROG_ADDR_W-1:0] pc,
	      input [`INSTR_W-1:0] 	    instruction,
	      

	      output reg		    data_sel,
	      output reg 		    data_we,
	      output reg [`ADDR_W-1:0] 	    data_addr,
	      input [`DATA_W-1:0] 	    data_to_rd,
	      output [`DATA_W-1:0] 	    data_to_wr
	      );

   
   reg [`DATA_W-1:0] 			  data_to_rd_int;
   
   reg [`DATA_W-1:0] 			  regA;
   reg [`DATA_W-1:0] 			  regA_nxt;
   reg [`DATA_W:0] 			  temp_regA;



   reg 					  regB_sel;
   wire 				  regB_we;
   reg [`DATA_W-1:0] 			  regB;
   wire [`DATA_W-1:0] 			  regB_nxt;
   wire [`ADDR_W-1:0] 			  addr_from_regB;


   wire [`DATA_W-1:0] 			  regC;
   reg 					  carry;
   reg 					  carry_nxt;
   reg 					  overflow;
   reg 					  overflow_nxt;
   reg 					  negative;
   wire 				  negative_nxt;
 				  

   reg [`PROG_ADDR_W-1:0] 		  pc_nxt;
   

   wire [`OPCODESZ-1 :0] 		  opcode;
   wire [`ADDR_W-1:0] 			  addrint;
   wire signed [`DATA_W-1:0] 		  imm;

   
    

   assign opcode  = instruction[`INSTR_W-1 -: `OPCODESZ];
   assign addrint = instruction[`ADDR_W-1:0];
   assign imm     = {{(`DATA_W-`IMM_W){instruction[`IMM_W-1]}},instruction[`IMM_W-1:0]};


   assign data_to_wr = regA;


   assign regB_we = regB_sel & data_we;
   assign regB_nxt = regB_we ? data_to_wr : regB;
   assign addr_from_regB = regB[`ADDR_W-1:0];


   assign regC = {negative, overflow,{(`DATA_W-3){1'b0}},carry};
   

   always @ * begin
      regB_sel = 1'b0;
      if (data_addr == `RB) begin
	 regB_sel = 1'b1;
         data_to_rd_int = regB;
      end else if (data_addr == `RC)
	data_to_rd_int = regC;
      else
        data_to_rd_int = data_to_rd;
   end
   

   always @ (posedge clk) begin
      if (rst) begin
	 regA <= `DATA_W'd0;
	 pc   <= `PROG_ROM;
      end else begin
	 regA <= regA_nxt;
	 pc   <= pc_nxt;
	 if(regB_we)
	   regB <= regB_nxt;     
	 negative <= negative_nxt;
 	 overflow <= overflow_nxt;
	 carry   <= carry_nxt;
     end
   end



   always @ * begin

      regA_nxt = regA;
      carry_nxt   = carry;
      pc_nxt   = pc + 1'b1;
   
      case (opcode)
	`RDW: begin
	   regA_nxt = data_to_rd_int;
	end
	`RDWB: begin
	   regA_nxt = data_to_rd_int;
	end
	`SHFT: begin
	   if ( imm[`DATA_W-1] ) begin
	      regA_nxt = regA << 1'b1;
	      carry_nxt   = regA[`DATA_W-1];
	   end else begin
	      regA_nxt = regA >> 1'b1;
	      carry_nxt   = regA[0];
	   end
	end
	`BEQI: begin
	   regA_nxt = regA - `DATA_W'd1;
	   if ( regA == `DATA_W'd0 )
	     pc_nxt = pc + imm[`PROG_ADDR_W:0];
	end
	`BEQ: begin
	   regA_nxt = regA - `DATA_W'd1;
	   if ( regA == `DATA_W'd0 )
	     pc_nxt = regB[`PROG_ADDR_W:0];
	end
	`BNEQI: begin
	   regA_nxt = regA - `DATA_W'd1;
	   if ( regA != `DATA_W'd0 )
	     pc_nxt = pc + imm[`PROG_ADDR_W:0];
	end
	`BNEQ: begin
	   regA_nxt = regA - `DATA_W'd1;
	   if ( regA != `DATA_W'd0 )
	     pc_nxt = regB[`PROG_ADDR_W:0];
	end
	`LDI: begin
	   regA_nxt = imm;
	end
	`LDIH: begin
	   regA_nxt = {imm[`DATA_W-`IMM_W-1:0],regA[`IMM_W-1:0]};
	end
	`ADD: begin
	   regA_nxt  = temp_regA[`DATA_W-1:0];
	   carry_nxt    = temp_regA[`DATA_W];
	end
	`SUB: begin
	   regA_nxt  = temp_regA[`DATA_W-1:0];
	   carry_nxt    = temp_regA[`DATA_W];
	end
	`ADDI: begin
	   regA_nxt  = temp_regA[`DATA_W-1:0];
	   carry_nxt    = temp_regA[`DATA_W];
	end
	`AND: begin
	   regA_nxt = regA & data_to_rd_int;
	end
	`XOR: begin
	   regA_nxt = regA ^ data_to_rd_int;
	end
	default:
	  pc_nxt = pc + 1'b1;
      endcase
   end


   assign negative_nxt =  temp_regA[`DATA_W-1];
   

   always @* begin
      case (opcode)
	`ADD: begin
	   overflow_nxt = temp_regA[`DATA_W-1] & ~regA[`DATA_W-1] & ~data_to_rd_int[`DATA_W-1];
	end
	`SUB: begin
	   overflow_nxt = temp_regA[`DATA_W-1] & ~regA[`DATA_W-1] & ~data_to_rd_int[`DATA_W-1];
	end
	`ADDI: begin
	   overflow_nxt = temp_regA[`DATA_W-1] & ~regA[`DATA_W-1] & ~imm[`DATA_W-1];
	end
	default:  begin
	   overflow_nxt = 1'b0;
	end
      endcase
   end



   always @* begin
      case (opcode)
	`ADD: begin
	   temp_regA = regA + data_to_rd_int;
	end
	`SUB: begin
	   temp_regA = regA - data_to_rd_int;
	end
	`ADDI: begin
	   temp_regA = regA + imm;
	end
	default:  begin
	  temp_regA = regA + data_to_rd_int;
	end
      endcase
   end

   

   always @ * begin

      data_sel  = 1'b0;
      data_we  = 1'b0;
      data_addr = addrint;
      
      case (opcode)
	`RDW: begin 
	   data_sel  = (addrint >= `REGF_BASE);
	end
	`RDWB: begin
	   data_sel  = (addrint >= `REGF_BASE);
	   data_addr = addr_from_regB + imm;
	end
	`WRW: begin
	   data_sel  = (addrint >= `REGF_BASE);
	   data_we  = 1'b1;
	end
	`WRWB: begin
	   data_sel  = (addrint >= `REGF_BASE);
	   data_we = 1'b1;
	   data_addr = addr_from_regB + imm;
	end
	default:
	     data_we  = 1'b0;
      endcase
   end
   
endmodule