data/full_repos/permissive/214278225/1_LEDs/knightRiderV2/rider.v
 line:14: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/214278225/1_LEDs/knightRiderV2/rider.v:30: Operator SUB expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'COUNT\' generates 22 bits.\n                                                                                    : ... In instance rider\n else if(counter == COUNT -1)begin\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module rider(clk,sw,rst,dataOut,dir,counter,state);

parameter COUNT = 22'h3FFFFF;
input [23:0] counter;


input clk,rst,dir,state;
input [7:0] sw;


output reg [2:0] dataOut;
reg [2:0] dataOutNxt;
reg returning,returningNxt = 0;


always @(posedge clk)begin
	dataOut <= #1 dataOutNxt;
	returning <= #1 returningNxt;
end


always@(*)begin
	dataOutNxt = dataOut;
	returningNxt = returning;
	if(rst)begin
		dataOutNxt = (dir ? 0 : 7);
		returningNxt = 0;
	end
	else if(counter == COUNT -1)begin
		case(state)
			0: begin
				if(!returning)begin
					case(dataOut)
						7:returningNxt = dir || sw[7];
						6:returningNxt = sw[6];
						5:returningNxt = sw[5];
						4:returningNxt = sw[4];
						3:returningNxt = sw[3];
						2:returningNxt = sw[2];
						1:returningNxt = sw[1];
						0:returningNxt = !dir || sw[0];
					endcase
				end else if(dataOut == 0 && dir)
					returningNxt = 0;
				else if(dataOut == 7 && !dir)
					returningNxt = 0;
			end
			
			1: begin
				case(returning)
					0: dataOutNxt = (dir ? dataOut + 1 : dataOut - 1);
					1: dataOutNxt = (dir ? dataOut - 1 : dataOut + 1);
				endcase
			end
		endcase
	end
end

endmodule
module rider(clk,sw,rst,dataOut,dir,counter,state);


parameter COUNT = 22'h3FFFFF;
input [23:0] counter;


input clk,rst,dir,state;
input [7:0] sw;


output reg [2:0] dataOut;
reg [2:0] dataOutNxt;
reg returning,returningNxt = 0;


always @(posedge clk)begin
	dataOut <= #1 dataOutNxt;
	returning <= #1 returningNxt;
end


always@(*)begin
	dataOutNxt = dataOut;
	returningNxt = returning;
	if(rst)begin
		dataOutNxt = (dir ? 0 : 7);
		returningNxt = 0;
	end
	else if(counter == COUNT -1)begin
		case(state)
			0: begin
				if(!returning)begin
					case(dataOut)
						7:returningNxt = dir || sw[7];
						6:returningNxt = sw[6];
						5:returningNxt = sw[5];
						4:returningNxt = sw[4];
						3:returningNxt = sw[3];
						2:returningNxt = sw[2];
						1:returningNxt = sw[1];
						0:returningNxt = !dir || sw[0];
					endcase
				end else if(dataOut == 0 && dir)
					returningNxt = 0;
				else if(dataOut == 7 && !dir)
					returningNxt = 0;
			end
			
			1: begin
				case(returning)
					0: dataOutNxt = (dir ? dataOut + 1 : dataOut - 1);
					1: dataOutNxt = (dir ? dataOut - 1 : dataOut + 1);
				endcase
			end
		endcase
	end
end

endmodule