data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/ECP5_Raw10toParallel/source/clarity/image_fifo/image_fifo.v
1: b"%Error: data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/ECP5_Raw10toParallel/source/clarity/image_fifo/image_fifo.v:23: Cannot find file containing module: 'sc_fifo'\n    sc_fifo sc_fifo_inst (.Data({sc_fifo_Data}), .Q({sc_fifo_Q}), .Clock(sc_fifo_Clock), \n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/ECP5_Raw10toParallel/source/clarity/image_fifo,data/full_repos/permissive/138208056/sc_fifo\n             data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/ECP5_Raw10toParallel/source/clarity/image_fifo,data/full_repos/permissive/138208056/sc_fifo.v\n             data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/ECP5_Raw10toParallel/source/clarity/image_fifo,data/full_repos/permissive/138208056/sc_fifo.sv\n             sc_fifo\n             sc_fifo.v\n             sc_fifo.sv\n             obj_dir/sc_fifo\n             obj_dir/sc_fifo.v\n             obj_dir/sc_fifo.sv\n%Error: Exiting due to 1 error(s)\n"
module image_fifo (sc_fifo_Data, sc_fifo_Q, sc_fifo_Clock, sc_fifo_Empty, 
            sc_fifo_Full, sc_fifo_RdEn, sc_fifo_Reset, sc_fifo_WrEn);
    input [9:0]sc_fifo_Data;
    output [9:0]sc_fifo_Q;
    input sc_fifo_Clock;
    output sc_fifo_Empty;
    output sc_fifo_Full;
    input sc_fifo_RdEn;
    input sc_fifo_Reset;
    input sc_fifo_WrEn;
    
    
    sc_fifo sc_fifo_inst (.Data({sc_fifo_Data}), .Q({sc_fifo_Q}), .Clock(sc_fifo_Clock), 
            .Empty(sc_fifo_Empty), .Full(sc_fifo_Full), .RdEn(sc_fifo_RdEn), 
            .Reset(sc_fifo_Reset), .WrEn(sc_fifo_WrEn));
    
endmodule
module image_fifo (sc_fifo_Data, sc_fifo_Q, sc_fifo_Clock, sc_fifo_Empty, 
            sc_fifo_Full, sc_fifo_RdEn, sc_fifo_Reset, sc_fifo_WrEn);

    input [9:0]sc_fifo_Data;
    output [9:0]sc_fifo_Q;
    input sc_fifo_Clock;
    output sc_fifo_Empty;
    output sc_fifo_Full;
    input sc_fifo_RdEn;
    input sc_fifo_Reset;
    input sc_fifo_WrEn;
    
    
    sc_fifo sc_fifo_inst (.Data({sc_fifo_Data}), .Q({sc_fifo_Q}), .Clock(sc_fifo_Clock), 
            .Empty(sc_fifo_Empty), .Full(sc_fifo_Full), .RdEn(sc_fifo_RdEn), 
            .Reset(sc_fifo_Reset), .WrEn(sc_fifo_WrEn));
    
endmodule