data/full_repos/permissive/125742950/RegisterUnit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/125742950/RegisterUnit.v:114: Operator ADD expects 12 bits on the LHS, but LHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                       : ... In instance RegisterUnit.PA3\n            Phase <= Phase + {4\'b0000 + TuningWord};\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/125742950/RegisterUnit.v:114: Operator ADD expects 16 bits on the RHS, but RHS\'s REPLICATE generates 12 bits.\n                                                                       : ... In instance RegisterUnit.PA3\n            Phase <= Phase + {4\'b0000 + TuningWord};\n                           ^\n%Error: Exiting due to 2 warning(s)\n'
module RegisterUnit(CLK, RST, ToneValue, ToneWE, Status, StatusWE, ChannelStatus, WavetableIndices);
    input CLK, RST;
    input[11:0] ToneValue;
    input[3:0] ToneWE;
    input[7:0] Status;
    input[7:0] StatusWE;
    output[7:0] ChannelStatus;
    output[23:0] WavetableIndices;
    
    wire[11:0] DataOut[0:3];
    ToneRegister TR0(CLK, RST, ToneWE[0], ToneValue, DataOut[0]);
    ToneRegister TR1(CLK, RST, ToneWE[1], ToneValue, DataOut[1]);
    ToneRegister TR2(CLK, RST, ToneWE[2], ToneValue, DataOut[2]);
    ToneRegister TR3(CLK, RST, ToneWE[3], ToneValue, DataOut[3]);

    wire Overflow[0:3];
    PhaseAccumulator PA0(CLK, RST, DataOut[0], Overflow[0]);
    PhaseAccumulator PA1(CLK, RST, DataOut[1], Overflow[1]);
    PhaseAccumulator PA2(CLK, RST, DataOut[2], Overflow[2]);
    PhaseAccumulator PA3(CLK, RST, DataOut[3], Overflow[3]);
    
    wire[5:0] Index[0:3];
    IndexRegister IR0(CLK, RST, Overflow[0], Index[0]);
    IndexRegister IR1(CLK, RST, Overflow[1], Index[1]);
    IndexRegister IR2(CLK, RST, Overflow[2], Index[2]);
    IndexRegister IR3(CLK, RST, Overflow[3], Index[3]);
    
    assign WavetableIndices = {Index[3], Index[2], Index[1], Index[0]};
    
    StatusRegister SR0(CLK, RST, StatusWE[1:0], Status[1:0], ChannelStatus[1:0]);
    StatusRegister SR1(CLK, RST, StatusWE[3:2], Status[3:2], ChannelStatus[3:2]);
    StatusRegister SR2(CLK, RST, StatusWE[5:4], Status[5:4], ChannelStatus[5:4]);
    StatusRegister SR3(CLK, RST, StatusWE[7:6], Status[7:6], ChannelStatus[7:6]);
    
endmodule
module RegisterUnit(CLK, RST, ToneValue, ToneWE, Status, StatusWE, ChannelStatus, WavetableIndices);

    input CLK, RST;
    input[11:0] ToneValue;
    input[3:0] ToneWE;
    input[7:0] Status;
    input[7:0] StatusWE;
    output[7:0] ChannelStatus;
    output[23:0] WavetableIndices;
    
    wire[11:0] DataOut[0:3];
    ToneRegister TR0(CLK, RST, ToneWE[0], ToneValue, DataOut[0]);
    ToneRegister TR1(CLK, RST, ToneWE[1], ToneValue, DataOut[1]);
    ToneRegister TR2(CLK, RST, ToneWE[2], ToneValue, DataOut[2]);
    ToneRegister TR3(CLK, RST, ToneWE[3], ToneValue, DataOut[3]);

    wire Overflow[0:3];
    PhaseAccumulator PA0(CLK, RST, DataOut[0], Overflow[0]);
    PhaseAccumulator PA1(CLK, RST, DataOut[1], Overflow[1]);
    PhaseAccumulator PA2(CLK, RST, DataOut[2], Overflow[2]);
    PhaseAccumulator PA3(CLK, RST, DataOut[3], Overflow[3]);
    
    wire[5:0] Index[0:3];
    IndexRegister IR0(CLK, RST, Overflow[0], Index[0]);
    IndexRegister IR1(CLK, RST, Overflow[1], Index[1]);
    IndexRegister IR2(CLK, RST, Overflow[2], Index[2]);
    IndexRegister IR3(CLK, RST, Overflow[3], Index[3]);
    
    assign WavetableIndices = {Index[3], Index[2], Index[1], Index[0]};
    
    StatusRegister SR0(CLK, RST, StatusWE[1:0], Status[1:0], ChannelStatus[1:0]);
    StatusRegister SR1(CLK, RST, StatusWE[3:2], Status[3:2], ChannelStatus[3:2]);
    StatusRegister SR2(CLK, RST, StatusWE[5:4], Status[5:4], ChannelStatus[5:4]);
    StatusRegister SR3(CLK, RST, StatusWE[7:6], Status[7:6], ChannelStatus[7:6]);
    
endmodule