data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/jkFlipFlop.v
data/verilator_xmls/98e5d4ed-064a-444a-977b-3cbbd78b1a13.xml
module jkFlipFlop (J, K, CLK, Q);
  input J, K, CLK;
  output Q;
  
  reg Q;
  
  initial
    begin
      Q = 0;
  end
  
  always @ (posedge CLK)
  begin
    case ({J, K})
      {1'b0, 1'b0}:
      begin
        Q = Q;
      end
      
      {1'b0, 1'b1}:
      begin
        Q = 0;
      end
      
      {1'b1, 1'b0}:
      begin
        Q = 1;
      end
      
      {1'b1, 1'b1}:
      begin
        Q = ~Q;
      end
    endcase
  end
endmodule
module jkFlipFlop (J, K, CLK, Q);

  input J, K, CLK;
  output Q;
  
  reg Q;
  
  initial
    begin
      Q = 0;
  end
  
  always @ (posedge CLK)
  begin
    case ({J, K})
      {1'b0, 1'b0}:
      begin
        Q = Q;
      end
      
      {1'b0, 1'b1}:
      begin
        Q = 0;
      end
      
      {1'b1, 1'b0}:
      begin
        Q = 1;
      end
      
      {1'b1, 1'b1}:
      begin
        Q = ~Q;
      end
    endcase
  end
endmodule