data/full_repos/permissive/152271286/OTM17.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152271286/OTM17.v:87: Operator ADD expects 19 bits on the RHS, but RHS\'s CONST \'16\'h1\' generates 16 bits.\n                                                               : ... In instance BFI.c8\n opx=opx+16\'b1;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module resch(output reg [32:0]result,
				input [15:0]yt,
				input [18:0]prt,
				input ct,
				input clk);

reg [34:0]restmp;

always @(posedge clk)
begin
	restmp[15:0]=yt;
	restmp[34:16]=prt;
	result=restmp[32:0];
end
endmodule
module resch(output reg [32:0]result,
				input [15:0]yt,
				input [18:0]prt,
				input ct,
				input clk);


reg [34:0]restmp;

always @(posedge clk)
begin
	restmp[15:0]=yt;
	restmp[34:16]=prt;
	result=restmp[32:0];
end
endmodule