data/full_repos/permissive/181013988/src/prog_cntr.v
1: b'%Warning-WIDTH: data/full_repos/permissive/181013988/src/prog_cntr.v:32: Operator ADD expects 32 bits on the RHS, but RHS\'s REPLICATE generates 30 bits.\n                                                                       : ... In instance prog_cntr\n                2\'b10:   pc <= pc_incr + {{14{brnch_offs[15]}},brnch_offs[15:0]};\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module prog_cntr(
    input clk,
    input rst,
    input zero,
    input brnch,
    input jmp,
    input [25:0] jmp_addr,
    input [15:0] brnch_offs,
    input [31:0] reg_addr,
    output reg [31:0] pc
);

    wire [31:0] pc_incr;
    reg [1:0] pc_ctrl;

    initial pc <= 32'h00000000;

    assign pc_incr = pc + 1;

    always @(posedge clk) begin
        if(rst == 1)
            pc <= 32'h00000000;
        else begin
            pc_ctrl = brnch & zero == 1 ? 2'b10 : 2'b00;
            pc_ctrl = jmp ? 2'b11 : pc_ctrl;
            case(pc_ctrl)
                2'b00:   pc <= pc_incr;
                2'b11:   pc <= {pc_incr[31:26],jmp_addr};
                2'b01:   pc <= reg_addr;
                2'b10:   pc <= pc_incr + {{14{brnch_offs[15]}},brnch_offs[15:0]};
                default: pc <= pc_incr;
            endcase
        end
    end

endmodule
module prog_cntr(
    input clk,
    input rst,
    input zero,
    input brnch,
    input jmp,
    input [25:0] jmp_addr,
    input [15:0] brnch_offs,
    input [31:0] reg_addr,
    output reg [31:0] pc
);


    wire [31:0] pc_incr;
    reg [1:0] pc_ctrl;

    initial pc <= 32'h00000000;

    assign pc_incr = pc + 1;

    always @(posedge clk) begin
        if(rst == 1)
            pc <= 32'h00000000;
        else begin
            pc_ctrl = brnch & zero == 1 ? 2'b10 : 2'b00;
            pc_ctrl = jmp ? 2'b11 : pc_ctrl;
            case(pc_ctrl)
                2'b00:   pc <= pc_incr;
                2'b11:   pc <= {pc_incr[31:26],jmp_addr};
                2'b01:   pc <= reg_addr;
                2'b10:   pc <= pc_incr + {{14{brnch_offs[15]}},brnch_offs[15:0]};
                default: pc <= pc_incr;
            endcase
        end
    end

endmodule