data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv
 line:19: before: "class"
1: b"%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:19: Unsupported: classes\nclass tl_trans extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:19: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass tl_trans extends uvm_sequence_item;\n                       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:23: syntax error, unexpected rand\n    rand bit [2:0]         tx_plength;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:24: syntax error, unexpected rand\n    rand bit [1:0]         tx_dlength;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:25: syntax error, unexpected rand\n    rand bit [15:0]        tx_capp_tag;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:26: syntax error, unexpected rand\n    rand bit [63:0]        tx_byte_enable;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:27: syntax error, unexpected rand\n    rand bit [63:0]        tx_physical_addr;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:28: syntax error, unexpected rand\n    rand bit [3:0]         tx_cmd_flag;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:29: syntax error, unexpected rand\n    rand bit [63:0]        tx_object_handle;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:30: syntax error, unexpected rand\n    rand bit [7:0]         tx_mad;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:31: syntax error, unexpected rand\n    rand bit [63:0]        tx_data_carrier[32];\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:32: syntax error, unexpected rand\n    rand bit [2:0]         tx_data_error[32];           \n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:33: syntax error, unexpected rand\n    rand bit [71:0]        tx_xmeta[32];\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:34: syntax error, unexpected rand\n    rand bit [6:0]         tx_meta[32];\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:35: syntax error, unexpected rand\n    rand bit [5:0]         tx_data_template;    \n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:36: syntax error, unexpected rand\n    rand int               tx_data_carrier_type;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:38: syntax error, unexpected rand\n    rand tl_rx_trans::packet_type_enum rx_packet_type;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:40: syntax error, unexpected rand\n    rand bit [2:0]  rx_dP;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:41: syntax error, unexpected rand\n    rand bit [1:0]  rx_dL;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:42: syntax error, unexpected rand\n    rand bit [3:0]  rx_resp_code;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:43: syntax error, unexpected rand\n    rand bit        rx_R;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:44: syntax error, unexpected rand\n    rand bit [63:0] rx_data_carrier[32];   \n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:45: syntax error, unexpected rand\n    rand bit [2:0]  rx_data_error[32];\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:46: syntax error, unexpected rand\n    rand bit [71:0] rx_xmeta[32];\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:47: syntax error, unexpected rand\n    rand bit [6:0]  rx_meta[32];\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:48: syntax error, unexpected rand\n    rand bit [5:0]  rx_data_template;     \n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:49: syntax error, unexpected rand\n    rand int        rx_data_carrier_type;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:53: Define or directive not defined: '`uvm_object_utils_begin'\n    `uvm_object_utils_begin(tl_trans)\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:53: syntax error, unexpected '('\n    `uvm_object_utils_begin(tl_trans)\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:54: Define or directive not defined: '`uvm_field_enum'\n        `uvm_field_enum   (tl_tx_trans::packet_type_enum, tx_packet_type, UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:55: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int                    (tx_config_type,   UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:56: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int                    (tx_plength,       UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:57: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int                    (tx_dlength,       UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:58: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int                    (tx_capp_tag,      UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:59: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int                    (tx_byte_enable,   UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:60: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int                    (tx_physical_addr, UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:61: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int                    (tx_cmd_flag,      UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:62: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int                    (tx_object_handle, UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:63: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int                    (tx_mad,           UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:64: Define or directive not defined: '`uvm_field_sarray_int'\n        `uvm_field_sarray_int             (tx_data_carrier,  UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:65: Define or directive not defined: '`uvm_field_sarray_int'\n        `uvm_field_sarray_int             (tx_data_error,    UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:66: Define or directive not defined: '`uvm_field_sarray_int'\n        `uvm_field_sarray_int             (tx_xmeta,         UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:67: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int(tx_data_carrier_type,                 UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:68: Define or directive not defined: '`uvm_field_sarray_int'\n        `uvm_field_sarray_int             (tx_meta,          UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:69: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int                    (tx_data_template, UVM_ALL_ON)           \n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:71: Define or directive not defined: '`uvm_field_enum'\n        `uvm_field_enum   (tl_rx_trans::packet_type_enum, rx_packet_type, UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:72: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int(rx_CAPPTag,                           UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:73: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int(rx_dP,                                UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:74: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int(rx_dL,                                UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_trans.sv:75: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int(rx_resp_code,                         UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n"
function new(string name="tl_trans");
        super.new(name);
    endfunction
function new(string name="tl_trans");

        super.new(name);
    endfunction