data/full_repos/permissive/12739552/ControlFSM.v
data/verilator_xmls/462ba1cd-12fb-40a0-b6db-5e75a0e82dee.xml
module ControlFSM (clk, reset, irq, read, write, iack, ir, alu_flags,
    addr_sel, load_sel, count_sel, count_up, top_enable, alu_enable, alu_op);

input clk, reset;


input irq;
input [7:0] ir;
input [2:0] alu_flags;
reg   [3:0] ustate;


output read, write, iack;
output [1:0] addr_sel, load_sel, count_sel;
output count_up, top_enable, alu_enable;
output [5:0] alu_op;
wire   [3:0] nx_ustate;

reg [21:0] ucode [0:65535];

assign {read, write, iack, addr_sel, load_sel, count_sel, count_up, top_enable,
        alu_enable, alu_op, nx_ustate} = ucode[ {ir, ustate, irq, alu_flags} ];

initial begin
    $readmemh("microcode.hex", ucode);
end

always @(posedge reset) begin
    if (reset)
        ustate <= 0;
end

always @(posedge clk) begin
    ustate <= nx_ustate;
end

endmodule
module ControlFSM (clk, reset, irq, read, write, iack, ir, alu_flags,
    addr_sel, load_sel, count_sel, count_up, top_enable, alu_enable, alu_op);


input clk, reset;


input irq;
input [7:0] ir;
input [2:0] alu_flags;
reg   [3:0] ustate;


output read, write, iack;
output [1:0] addr_sel, load_sel, count_sel;
output count_up, top_enable, alu_enable;
output [5:0] alu_op;
wire   [3:0] nx_ustate;

reg [21:0] ucode [0:65535];

assign {read, write, iack, addr_sel, load_sel, count_sel, count_up, top_enable,
        alu_enable, alu_op, nx_ustate} = ucode[ {ir, ustate, irq, alu_flags} ];

initial begin
    $readmemh("microcode.hex", ucode);
end

always @(posedge reset) begin
    if (reset)
        ustate <= 0;
end

always @(posedge clk) begin
    ustate <= nx_ustate;
end

endmodule