data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v
 line:78: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v:66: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #(stimDelay)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #(stimDelay);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v:80: Unsupported: Ignoring delay on this delayed statement.\n   #(stimDelay) e_in = e_in + 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #100;  \n  ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PID
(output signed [31:0] u_out,
input signed [31:0] e_in,
input clk,
input reset,
input [7:0] k1,
input [7:0] k2,
input [7:0] k3);








	
	reg signed [31:0] u_prev;
	reg signed [31:0] e_prev[0:1];
	reg signed [31:0] e_in_buffered;
	
	assign u_out = u_prev + k1*e_in_buffered - k2*e_prev[0] + k3*e_prev[1];

	always @(posedge clk)
	begin
		e_in_buffered <= e_in;
		if (reset == 1) 
		begin
			u_prev <= 0;
			e_prev[0] <= 0;
			e_prev[1] <= 0;
		end
		else 
		begin 
			e_prev[1] <= e_prev[0];
			e_prev[0] <= e_in_buffered;
			u_prev <= u_out;
		end
	end
endmodule
module PID
(output signed [31:0] u_out,
input signed [31:0] e_in,
input clk,
input reset,
input [7:0] k1,
input [7:0] k2,
input [7:0] k3);









	
	reg signed [31:0] u_prev;
	reg signed [31:0] e_prev[0:1];
	reg signed [31:0] e_in_buffered;
	
	assign u_out = u_prev + k1*e_in_buffered - k2*e_prev[0] + k3*e_prev[1];

	always @(posedge clk)
	begin
		e_in_buffered <= e_in;
		if (reset == 1) 
		begin
			u_prev <= 0;
			e_prev[0] <= 0;
			e_prev[1] <= 0;
		end
		else 
		begin 
			e_prev[1] <= e_prev[0];
			e_prev[0] <= e_in_buffered;
			u_prev <= u_out;
		end
	end
endmodule