data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v
 line:335: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:409: Operator FUNCREF \'write_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_ctl_control\' generates 4 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                ADR_CTL_CONTROL:        reg_ctl_control      <= write_mask(reg_ctl_control,     s_wb_dat_i, s_wb_sel_i);\n                                                                ^~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:409: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'write_mask\' generates 32 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                ADR_CTL_CONTROL:        reg_ctl_control      <= write_mask(reg_ctl_control,     s_wb_dat_i, s_wb_sel_i);\n                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:410: Operator FUNCREF \'write_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_irq_enable\' generates 1 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                ADR_IRQ_ENABLE:         reg_irq_enable       <= write_mask(reg_irq_enable,      s_wb_dat_i, s_wb_sel_i);\n                                                                ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:410: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'write_mask\' generates 32 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                ADR_IRQ_ENABLE:         reg_irq_enable       <= write_mask(reg_irq_enable,      s_wb_dat_i, s_wb_sel_i);\n                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:411: Operator AND expects 32 bits on the LHS, but LHS\'s VARREF \'reg_irq_status\' generates 1 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                ADR_IRQ_CLR:            reg_irq_status       <= reg_irq_status & ~write_mask(0, s_wb_dat_i, s_wb_sel_i);\n                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:411: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                ADR_IRQ_CLR:            reg_irq_status       <= reg_irq_status & ~write_mask(0, s_wb_dat_i, s_wb_sel_i);\n                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:412: Operator OR expects 32 bits on the LHS, but LHS\'s VARREF \'reg_irq_status\' generates 1 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                ADR_IRQ_SET:            reg_irq_status       <= reg_irq_status |  write_mask(0, s_wb_dat_i, s_wb_sel_i);\n                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:412: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s OR generates 32 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                ADR_IRQ_SET:            reg_irq_status       <= reg_irq_status |  write_mask(0, s_wb_dat_i, s_wb_sel_i);\n                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:415: Operator FUNCREF \'write_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_arlen_max\' generates 8 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                ADR_PARAM_ARLEN_MAX:    reg_param_arlen_max  <= write_mask(reg_param_arlen_max, s_wb_dat_i, s_wb_sel_i);\n                                                                ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:415: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'write_mask\' generates 32 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                ADR_PARAM_ARLEN_MAX:    reg_param_arlen_max  <= write_mask(reg_param_arlen_max, s_wb_dat_i, s_wb_sel_i);\n                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:499: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_control\' generates 4 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                        (s_wb_adr_i == ADR_CTL_CONTROL)      ? reg_ctl_control      :\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:500: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_status\' generates 1 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                        (s_wb_adr_i == ADR_CTL_STATUS)       ? reg_ctl_status       :\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:501: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_index\' generates 1 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                        (s_wb_adr_i == ADR_CTL_INDEX)        ? reg_ctl_index        :\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:502: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_irq_enable\' generates 1 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                        (s_wb_adr_i == ADR_IRQ_ENABLE)       ? reg_irq_enable       :\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:503: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_irq_status\' generates 1 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                        (s_wb_adr_i == ADR_IRQ_STATUS)       ? reg_irq_status       :\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:506: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_arlen_max\' generates 8 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                        (s_wb_adr_i == ADR_PARAM_ARLEN_MAX)  ? reg_param_arlen_max  :\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:529: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_shadow_arlen_max\' generates 8 bits.\n                                                                                      : ... In instance jelly_dma_stream_read\n                        (s_wb_adr_i == ADR_SHADOW_ARLEN_MAX) ? reg_shadow_arlen_max :\n                                                             ^\n%Error: data/full_repos/permissive/2084115/rtl/dma/jelly_dma_stream_read.v:591: Cannot find file containing module: \'jelly_axi4_read_nd\'\n    jelly_axi4_read_nd\n    ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/dma,data/full_repos/permissive/2084115/jelly_axi4_read_nd\n             data/full_repos/permissive/2084115/rtl/dma,data/full_repos/permissive/2084115/jelly_axi4_read_nd.v\n             data/full_repos/permissive/2084115/rtl/dma,data/full_repos/permissive/2084115/jelly_axi4_read_nd.sv\n             jelly_axi4_read_nd\n             jelly_axi4_read_nd.v\n             jelly_axi4_read_nd.sv\n             obj_dir/jelly_axi4_read_nd\n             obj_dir/jelly_axi4_read_nd.v\n             obj_dir/jelly_axi4_read_nd.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n'
function [WB_DAT_WIDTH-1:0] write_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] dat,
                                        input [WB_SEL_WIDTH-1:0] sel
                                    );
    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            write_mask[i] = sel[i/8] ? dat[i] : org[i];
        end
    end
    endfunction
function [WB_DAT_WIDTH-1:0] write_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] dat,
                                        input [WB_SEL_WIDTH-1:0] sel
                                    );

    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            write_mask[i] = sel[i/8] ? dat[i] : org[i];
        end
    end
    endfunction