data/full_repos/permissive/190755935/src/comms/rtl/usb/usb_reset_det.v
1: b'%Warning-WIDTH: data/full_repos/permissive/190755935/src/comms/rtl/usb/usb_reset_det.v:24: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESET_COUNT\' generates 16 bits.\n                                                                                         : ... In instance usb_reset_det\n   reset_timer <= RESET_COUNT;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/190755935/src/comms/rtl/usb/usb_reset_det.v:28: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESET_COUNT\' generates 16 bits.\n                                                                                         : ... In instance usb_reset_det\n    reset_timer <= RESET_COUNT;\n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module usb_reset_det (
	  input clk,
	  input reset,

	  input usb_p_rx,  
	  input usb_n_rx,
	  
	   output usb_reset
	);

	localparam RESET_COUNT = 16'HFFFF;


	reg [17:0] reset_timer = 0;


	wire timer_expired = reset_timer[ 17 ];


	assign usb_reset = timer_expired;

	always @(posedge clk) begin
		if ( reset ) begin
			reset_timer <= RESET_COUNT;
		end else begin 

			if (usb_p_rx || usb_n_rx) begin
				reset_timer <= RESET_COUNT;
			end else begin 			
				reset_timer <= reset_timer - ((timer_expired)? 0 : 1);
			end	  
		end
	end
  
endmodule
module usb_reset_det (
	  input clk,
	  input reset,

	  input usb_p_rx,  
	  input usb_n_rx,
	  
	   output usb_reset
	);


	localparam RESET_COUNT = 16'HFFFF;


	reg [17:0] reset_timer = 0;


	wire timer_expired = reset_timer[ 17 ];


	assign usb_reset = timer_expired;

	always @(posedge clk) begin
		if ( reset ) begin
			reset_timer <= RESET_COUNT;
		end else begin 

			if (usb_p_rx || usb_n_rx) begin
				reset_timer <= RESET_COUNT;
			end else begin 			
				reset_timer <= reset_timer - ((timer_expired)? 0 : 1);
			end	  
		end
	end
  
endmodule