data/full_repos/permissive/108195533/instrMem.v
data/verilator_xmls/db1ea4b1-8875-41c0-a847-b0872dc13e6f.xml
module instrMem#(parameter MEM_WIDTH=8, parameter WIDTH=16)(addr, instr);
  input [MEM_WIDTH-1:0] addr;
  output reg[WIDTH-1:0] instr;
  
  reg [WIDTH-1:0] memory [2**MEM_WIDTH-1:0];
  
  initial $readmemb("instructions", memory);
    
  always@(*)
  begin
    instr = memory[addr];
  end
endmodule
module instrMem#(parameter MEM_WIDTH=8, parameter WIDTH=16)(addr, instr);

  input [MEM_WIDTH-1:0] addr;
  output reg[WIDTH-1:0] instr;
  
  reg [WIDTH-1:0] memory [2**MEM_WIDTH-1:0];
  
  initial $readmemb("instructions", memory);
    
  always@(*)
  begin
    instr = memory[addr];
  end
endmodule