data/full_repos/permissive/101237473/lab8/Source Code/reg16.v
1: b'%Error: Cannot find file containing module: Code,data/full_repos/permissive/101237473\n        ... Looked in:\n             data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473\n             data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.v\n             data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.sv\n             Code,data/full_repos/permissive/101237473\n             Code,data/full_repos/permissive/101237473.v\n             Code,data/full_repos/permissive/101237473.sv\n             obj_dir/Code,data/full_repos/permissive/101237473\n             obj_dir/Code,data/full_repos/permissive/101237473.v\n             obj_dir/Code,data/full_repos/permissive/101237473.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/101237473/lab8/Source\n%Error: Cannot find file containing module: Code/reg16.v\n%Error: Exiting due to 3 error(s)\n'
module reg16( clk, reset, ld, Din, DA, DB, oeA, oeB );

	input 	clk, reset, ld, oeA, oeB; 
	input 	[15:0] Din; 
	output 	[15:0] DA, DB; 
	reg 		[15:0] Dout; 
	

	always @ ( posedge clk or posedge reset ) 
		if (reset) 
			Dout <= 16'b0; 
		else 
			if (ld) 
					Dout <= Din; 
			else	Dout <= Dout; 
			

	assign DA = oeA ? Dout : 16'hz; 
	assign DB = oeB ? Dout : 16'hz; 

endmodule
module reg16( clk, reset, ld, Din, DA, DB, oeA, oeB );


	input 	clk, reset, ld, oeA, oeB; 
	input 	[15:0] Din; 
	output 	[15:0] DA, DB; 
	reg 		[15:0] Dout; 
	

	always @ ( posedge clk or posedge reset ) 
		if (reset) 
			Dout <= 16'b0; 
		else 
			if (ld) 
					Dout <= Din; 
			else	Dout <= Dout; 
			

	assign DA = oeA ? Dout : 16'hz; 
	assign DB = oeB ? Dout : 16'hz; 

endmodule