data/full_repos/permissive/18921956/books/tmp_mealy.v
data/verilator_xmls/1cf8234c-3047-4a44-ab56-f412266bb0ef.xml
module mealyFSM (
	output	reg	o_d,
	input 		i_d,
	input		clk,
	input		reset_n
);
parameter	IDLE	=	2'b00;
parameter	S0		=	2'b01;

reg [1:0] state, next_state;
reg o_d_next;

always @(posedge clk or negedge reset_n) begin
	if (!reset_n) begin
		state	<=	IDLE;
	end else begin
		state	<=	next_state;
	end
end

always @(*) begin
	o_d_next = 1'b0;
	case (state)
		IDLE: begin
			if (i_d == 1'b1) begin
				o_d_next = 1'b1;
			end
		end
	endcase
end

always @(*) begin
	next_state = IDLE;
	case (state)
		IDLE: begin
			if (i_d == 1'b1) begin
				next_state = S0;
			end
		end
		S0: begin
			if (i_d == 1'b1) begin
				next_state = S0;
			end
		end
	endcase
end

always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        o_d <= 1'b0;
    end else begin
        o_d <= o_d_next;
    end
end
endmodule
module mealyFSM (
	output	reg	o_d,
	input 		i_d,
	input		clk,
	input		reset_n
);

parameter	IDLE	=	2'b00;
parameter	S0		=	2'b01;

reg [1:0] state, next_state;
reg o_d_next;

always @(posedge clk or negedge reset_n) begin
	if (!reset_n) begin
		state	<=	IDLE;
	end else begin
		state	<=	next_state;
	end
end

always @(*) begin
	o_d_next = 1'b0;
	case (state)
		IDLE: begin
			if (i_d == 1'b1) begin
				o_d_next = 1'b1;
			end
		end
	endcase
end

always @(*) begin
	next_state = IDLE;
	case (state)
		IDLE: begin
			if (i_d == 1'b1) begin
				next_state = S0;
			end
		end
		S0: begin
			if (i_d == 1'b1) begin
				next_state = S0;
			end
		end
	endcase
end

always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        o_d <= 1'b0;
    end else begin
        o_d <= o_d_next;
    end
end
endmodule