data/full_repos/permissive/188795755/elec_design/beta1/src/pwm.v
'utf-8' codec can't decode byte 0xbf in position 248: invalid start byte
data/verilator_xmls/d5a20e83-8142-4326-9eef-60307349a2ca.xml
module  pwm(

        input                   sclk                    ,
        input                   s_rst_n                 ,

        input                   enable                  ,
        input                   direct                  ,

        output  [ 1:0]          MA
);




parameter               PERIOD  =       'd10_000        ;
parameter               SHIFT   =       'd100_000_000   ;

reg     [29:0]          cnt_spd                         ;
reg     [15:0]          cnt_r                           ;
reg     [15:0]          cntReg                          ;
reg     [15:0]          cnt                             ;
reg                     pulseout                        ;
reg     [ 1:0]          MA_r                            ;
reg     [ 1:0]          spd_sel                         ;



assign  MA      =       MA_r;   
      

always  @(posedge sclk or negedge s_rst_n) begin
        if(s_rst_n == 1'b0)
                cnt_spd <=      'd0;
        else if(cnt_spd >= SHIFT)
                cnt_spd <=      'd0;
        else
                cnt_spd <=      cnt_spd + 1'b1;
end  

always  @(posedge sclk or negedge s_rst_n) begin
        if (!s_rst_n)
                spd_sel <=      2'b11;
        else if(cnt_spd >= SHIFT)
                spd_sel <=      spd_sel - 1'b1;
end 


always  @( spd_sel ) begin 
        case (spd_sel)
                2'b00 :    cnt_r        <=      PERIOD - 'd3500; 
                2'b01 :    cnt_r        <=      PERIOD - 'd2500; 
                2'b10 :    cnt_r        <=      PERIOD - 'd1750; 
                2'b11 :    cnt_r        <=      PERIOD - 'd1000; 
        endcase 
end 

always  @(posedge sclk or negedge s_rst_n ) begin  
        if (!s_rst_n)
                cntReg  <=      16'b0;
        else if (direct == 1'b1)
                cntReg  <=      cnt_r;
        else if (direct == 1'b0)
                cntReg  <=      PERIOD - cnt_r;
end

always  @(posedge sclk or negedge s_rst_n ) begin  
        if (!s_rst_n)
                cnt     <=      16'b0;
        else if (cnt >= PERIOD)
                cnt     <=      'b0;
        else
                cnt     <=      cnt + 1;
end

always  @(posedge sclk or negedge s_rst_n ) begin  
        if (!s_rst_n)
                pulseout        <=      1'b0;
        else if (cnt >= cntReg)
                pulseout        <=      1'b1;
        else if (cnt >= PERIOD)
                pulseout        <=      1'b0;
end 

always  @(posedge sclk or negedge s_rst_n ) begin  
        if (!s_rst_n)
                MA_r    <=      2'b00;
        else if (enable == 1'b0)
                MA_r    <=      2'b00;
        else       
                MA_r    <=      {~pulseout,pulseout};
end
                
endmodule
module  pwm(

        input                   sclk                    ,
        input                   s_rst_n                 ,

        input                   enable                  ,
        input                   direct                  ,

        output  [ 1:0]          MA
);





parameter               PERIOD  =       'd10_000        ;
parameter               SHIFT   =       'd100_000_000   ;

reg     [29:0]          cnt_spd                         ;
reg     [15:0]          cnt_r                           ;
reg     [15:0]          cntReg                          ;
reg     [15:0]          cnt                             ;
reg                     pulseout                        ;
reg     [ 1:0]          MA_r                            ;
reg     [ 1:0]          spd_sel                         ;



assign  MA      =       MA_r;   
      

always  @(posedge sclk or negedge s_rst_n) begin
        if(s_rst_n == 1'b0)
                cnt_spd <=      'd0;
        else if(cnt_spd >= SHIFT)
                cnt_spd <=      'd0;
        else
                cnt_spd <=      cnt_spd + 1'b1;
end  

always  @(posedge sclk or negedge s_rst_n) begin
        if (!s_rst_n)
                spd_sel <=      2'b11;
        else if(cnt_spd >= SHIFT)
                spd_sel <=      spd_sel - 1'b1;
end 


always  @( spd_sel ) begin 
        case (spd_sel)
                2'b00 :    cnt_r        <=      PERIOD - 'd3500; 
                2'b01 :    cnt_r        <=      PERIOD - 'd2500; 
                2'b10 :    cnt_r        <=      PERIOD - 'd1750; 
                2'b11 :    cnt_r        <=      PERIOD - 'd1000; 
        endcase 
end 

always  @(posedge sclk or negedge s_rst_n ) begin  
        if (!s_rst_n)
                cntReg  <=      16'b0;
        else if (direct == 1'b1)
                cntReg  <=      cnt_r;
        else if (direct == 1'b0)
                cntReg  <=      PERIOD - cnt_r;
end

always  @(posedge sclk or negedge s_rst_n ) begin  
        if (!s_rst_n)
                cnt     <=      16'b0;
        else if (cnt >= PERIOD)
                cnt     <=      'b0;
        else
                cnt     <=      cnt + 1;
end

always  @(posedge sclk or negedge s_rst_n ) begin  
        if (!s_rst_n)
                pulseout        <=      1'b0;
        else if (cnt >= cntReg)
                pulseout        <=      1'b1;
        else if (cnt >= PERIOD)
                pulseout        <=      1'b0;
end 

always  @(posedge sclk or negedge s_rst_n ) begin  
        if (!s_rst_n)
                MA_r    <=      2'b00;
        else if (enable == 1'b0)
                MA_r    <=      2'b00;
        else       
                MA_r    <=      {~pulseout,pulseout};
end
                
endmodule