data/full_repos/permissive/168578692/Control.v
1: b"%Error: data/full_repos/permissive/168578692/Control.v:24: Can't find definition of variable: 'right_Pause'\n  button_Press[2] = (right_Pause | left_Pause);\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/168578692/Control.v:24: Can't find definition of variable: 'left_Pause'\n  button_Press[2] = (right_Pause | left_Pause);\n                                   ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Control(

  input clock100MHz,
  input clock_Divided,
  input start,
  input down_Button,
  input right_Button,
  input left_Button,
  clear,
  output reg count_Enable
);


reg [2:0] button_Press;


reg [1:0] state;


always @ (posedge clock100MHz) begin

  button_Press[0] = clear;
  button_Press[1] = start;
  button_Press[2] = (right_Pause | left_Pause);
end


always @ (posedge clock_Divided) begin

  casex(button_Press)
  3'bxx1: begin
    state = 2'b01;
    count_Enable = 1'b0; end
  3'bx10: begin
    state = 2'b11;
    count_Enable = 1'b1; end
  3'b100: begin
    state = 2'b10;
    count_Enable =  1'b0; end
  default: begin
    state = 2'b00;
    count_Enable = count_Enable; end
  endcase
end
endmodule
module Control(

  input clock100MHz,
  input clock_Divided,
  input start,
  input down_Button,
  input right_Button,
  input left_Button,
  clear,
  output reg count_Enable
);



reg [2:0] button_Press;


reg [1:0] state;


always @ (posedge clock100MHz) begin

  button_Press[0] = clear;
  button_Press[1] = start;
  button_Press[2] = (right_Pause | left_Pause);
end


always @ (posedge clock_Divided) begin

  casex(button_Press)
  3'bxx1: begin
    state = 2'b01;
    count_Enable = 1'b0; end
  3'bx10: begin
    state = 2'b11;
    count_Enable = 1'b1; end
  3'b100: begin
    state = 2'b10;
    count_Enable =  1'b0; end
  default: begin
    state = 2'b00;
    count_Enable = count_Enable; end
  endcase
end
endmodule