data/full_repos/permissive/143278/ivltests/pr2937417.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr2937417.v:5: Unsupported: Verilog 1995 strength specifiers\n  assign (weak1, weak0) x = (a === 1\'b1) ? 1\'b0 : 1\'b1;\n          ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr2937417.v:5: Unsupported: Verilog 1995 strength specifiers\n  assign (weak1, weak0) x = (a === 1\'b1) ? 1\'b0 : 1\'b1;\n                 ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr2937417.v:11: Unsupported: Verilog 1995 gate primitive: tran\n  tran (x, y);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2937417.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1 if ( x !== 1\'bx || y !== 1\'bx) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2937417.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1 a = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2937417.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1 if ( x !== 1\'b0 || y !== 1\'b0) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2937417.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1 a = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2937417.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1 if ( x !== 1\'b1 || y !== 1\'b1) begin\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/pr2937417.v:32: Unsupported: Verilog 1995 force\n    #1 force a = 1\'bx;\n       ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2937417.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #1 force a = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2937417.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #1 if ( x !== 1\'bx || y !== 1\'bx) begin\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/pr2937417.v:37: Unsupported: Verilog 1995 release\n    #1 release a;\n       ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2937417.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1 release a;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2937417.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #1 if ( x !== 1\'b0 || y !== 1\'b0) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2937417.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1 a = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2937417.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #1 if ( x !== 1\'b1 || y !== 1\'b1) begin\n    ^\n%Error: Exiting due to 5 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg a, pass;
  wire x, y, ab;

  assign (weak1, weak0) x = (a === 1'b1) ? 1'b0 : 1'b1;
  assign y = a;


  assign ab = ~a;

  tran (x, y);

  initial begin

    pass = 1'b1;

    #1 if ( x !== 1'bx || y !== 1'bx) begin
      $display("Failed initial value, expected 1'bx, 1'bx, got %b %b", x, y);
      pass = 1'b0;
    end
    #1 a = 1'b0;
    #1 if ( x !== 1'b0 || y !== 1'b0) begin
      $display("Failed same value, expected 1'b0, 1'b0, got %b %b", x, y);
      pass = 1'b0;
    end
    #1 a = 1'b1;
    #1 if ( x !== 1'b1 || y !== 1'b1) begin
      $display("Failed same value, expected 1'b1, 1'b1, got %b %b", x, y);
      pass = 1'b0;
    end

    #1 force a = 1'bx;
    #1 if ( x !== 1'bx || y !== 1'bx) begin
      $display("Failed driver value, expected 1'bx, 1'bx, got %b %b", x, y);
      pass = 1'b0;
    end
    #1 release a;
       a = 1'b0;
    #1 if ( x !== 1'b0 || y !== 1'b0) begin
      $display("Failed driver value, expected 1'b0, 1'b0, got %b %b", x, y);
      pass = 1'b0;
    end

    #1 a = 1'bz;
    #1 if ( x !== 1'b1 || y !== 1'b1) begin
      $display("Failed alt. value, expected 1'b1, 1'b1, got %b %b", x, y);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg a, pass;
  wire x, y, ab;

  assign (weak1, weak0) x = (a === 1'b1) ? 1'b0 : 1'b1;
  assign y = a;


  assign ab = ~a;

  tran (x, y);

  initial begin

    pass = 1'b1;

    #1 if ( x !== 1'bx || y !== 1'bx) begin
      $display("Failed initial value, expected 1'bx, 1'bx, got %b %b", x, y);
      pass = 1'b0;
    end
    #1 a = 1'b0;
    #1 if ( x !== 1'b0 || y !== 1'b0) begin
      $display("Failed same value, expected 1'b0, 1'b0, got %b %b", x, y);
      pass = 1'b0;
    end
    #1 a = 1'b1;
    #1 if ( x !== 1'b1 || y !== 1'b1) begin
      $display("Failed same value, expected 1'b1, 1'b1, got %b %b", x, y);
      pass = 1'b0;
    end

    #1 force a = 1'bx;
    #1 if ( x !== 1'bx || y !== 1'bx) begin
      $display("Failed driver value, expected 1'bx, 1'bx, got %b %b", x, y);
      pass = 1'b0;
    end
    #1 release a;
       a = 1'b0;
    #1 if ( x !== 1'b0 || y !== 1'b0) begin
      $display("Failed driver value, expected 1'b0, 1'b0, got %b %b", x, y);
      pass = 1'b0;
    end

    #1 a = 1'bz;
    #1 if ( x !== 1'b1 || y !== 1'b1) begin
      $display("Failed alt. value, expected 1'b1, 1'b1, got %b %b", x, y);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule