data/full_repos/permissive/211316121/lab8_1/RAM.v
data/verilator_xmls/5b6ce63a-5309-4219-a4c9-4264290deb83.xml
module top(
    input clk,
    input [14:0] sw,
    output [15:0] led
);
wire clk1_4hz;
wire [3:0]d1;
wire [3:0]q1;
wire [3:0]q2;
wire [3:0]q3;
wire [3:0]q4;
wire [3:0]yout;
clkdiv U0(clk,clk1_4hz);
_74LS377 U1(clk1_4hz,sw[7],d1,q1);
_74LS377 U2(clk1_4hz,sw[6],yout,q2);
_74LS377 U3(clk1_4hz,sw[5],yout,q3);
RAM U4(clk1_4hz,sw[0],yout,sw[4:1],q4);
MUX2_1 U5(sw[11:8],yout,sw[12],d1);
MUX4_1 U6(q1,q2,q3,q4,sw[14:13],yout);
assign led[3:0]=q2;
assign led[7:4]=q3;
assign led[11:8]=q1;
assign led[15:12]=q4;
endmodule
module top(
    input clk,
    input [14:0] sw,
    output [15:0] led
);

wire clk1_4hz;
wire [3:0]d1;
wire [3:0]q1;
wire [3:0]q2;
wire [3:0]q3;
wire [3:0]q4;
wire [3:0]yout;
clkdiv U0(clk,clk1_4hz);
_74LS377 U1(clk1_4hz,sw[7],d1,q1);
_74LS377 U2(clk1_4hz,sw[6],yout,q2);
_74LS377 U3(clk1_4hz,sw[5],yout,q3);
RAM U4(clk1_4hz,sw[0],yout,sw[4:1],q4);
MUX2_1 U5(sw[11:8],yout,sw[12],d1);
MUX4_1 U6(q1,q2,q3,q4,sw[14:13],yout);
assign led[3:0]=q2;
assign led[7:4]=q3;
assign led[11:8]=q1;
assign led[15:12]=q4;
endmodule