data/full_repos/permissive/160408009/components/jtag/corejtagdebug_ujtag_wrapper.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/160408009/components/jtag/corejtagdebug_ujtag_wrapper.v:74: Cannot find file containing module: 'UJTAG'\n  UJTAG UJTAG_inst(\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/160408009/components/jtag,data/full_repos/permissive/160408009/UJTAG\n             data/full_repos/permissive/160408009/components/jtag,data/full_repos/permissive/160408009/UJTAG.v\n             data/full_repos/permissive/160408009/components/jtag,data/full_repos/permissive/160408009/UJTAG.sv\n             UJTAG\n             UJTAG.v\n             UJTAG.sv\n             obj_dir/UJTAG\n             obj_dir/UJTAG.v\n             obj_dir/UJTAG.sv\n%Error: Exiting due to 1 error(s)\n"
module COREJTAGDEBUG_UJTAG_WRAPPER (

					  UTDO,
					  TDI,
					  TMS,
					  TCK,
					  TRSTB,

					  UDRCAP,
					  UDRSH,
					  UDRUPD,
					  UIREG,
					  URSTB,
					  UDRCK,
					  UTDI,
					  TDO
					  );
  
  input UTDO;
  input TDI;
  input TMS;
  input TCK;
  input TRSTB;
  output UDRCAP;
  output UDRSH;
  output UDRUPD;
  output [7:0] UIREG;
  output       URSTB;
  output 	   UDRCK;
  output       UTDI;
  output       TDO;

`ifndef IDENTIFY_DEBUG_IMPL


  UJTAG UJTAG_inst(

				.UTDO   ( UTDO ),
				.TDI    ( TDI ),
				.TMS    ( TMS ),
				.TCK    ( TCK ),
				.TRSTB  ( TRSTB ),

				.UDRCAP ( UDRCAP ),
				.UDRSH  ( UDRSH ),
				.UDRUPD ( UDRUPD ),
				.UIREG  ( UIREG ),
				.URSTB  ( URSTB ),
				.UDRCK  ( UDRCK ),
				.UTDI   ( UTDI ),
				.TDO    ( TDO )
        );

`else

  wire 	 utdo_wire;
  wire   tdi_wire;
  wire   tms_wire;
  wire   tck_wire;
  wire   trstb_wire;
  
  assign utdo_wire 	= UTDO ;
  assign tdi_wire 	= TDI;
  assign tms_wire 	= TMS;
  assign tck_wire 	= TCK;
  assign trstb_wire = TRSTB;
  

  syn_hyper_connect_internal hyperc_ujtag_wrapper_uireg(UIREG);
  defparam hyperc_ujtag_wrapper_uireg.w = 8;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_urstb(URSTB);
  defparam hyperc_ujtag_wrapper_urstb.w = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_udrupd(UDRUPD);
  defparam hyperc_ujtag_wrapper_udrupd.w = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_udrck(UDRCK);
  defparam hyperc_ujtag_wrapper_udrck.w = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_udrcap(UDRCAP);
  defparam hyperc_ujtag_wrapper_udrcap.w = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_udrsh(UDRSH);
  defparam hyperc_ujtag_wrapper_udrsh.w = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_utdi(UTDI);
  defparam hyperc_ujtag_wrapper_utdi.w = 1;

  syn_hyper_source_internal hypers_ujtag_wrapper_utdo(utdo_wire);
  defparam hypers_ujtag_wrapper_utdo.w 	  = 1;


  syn_hyper_source_internal hypers_ujtag_wrapper_tdi(tdi_wire);
  defparam hypers_ujtag_wrapper_tdi.w 	 = 1;

  syn_hyper_source_internal hypers_ujtag_wrapper_tms(tms_wire);
  defparam hypers_ujtag_wrapper_tms.w 	  = 1;
  
  syn_hyper_source_internal hypers_ujtag_wrapper_tck(tck_wire);
  defparam hypers_ujtag_wrapper_tck.w 	  = 1;

  syn_hyper_source_internal hypers_ujtag_wrapper_trstb(trstb_wire);
  defparam hypers_ujtag_wrapper_trstb.w 	  = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_tdo(TDO);
  defparam hyperc_ujtag_wrapper_tdo.w = 1;
  
`endif
  
endmodule
module COREJTAGDEBUG_UJTAG_WRAPPER (

					  UTDO,
					  TDI,
					  TMS,
					  TCK,
					  TRSTB,

					  UDRCAP,
					  UDRSH,
					  UDRUPD,
					  UIREG,
					  URSTB,
					  UDRCK,
					  UTDI,
					  TDO
					  );

  
  input UTDO;
  input TDI;
  input TMS;
  input TCK;
  input TRSTB;
  output UDRCAP;
  output UDRSH;
  output UDRUPD;
  output [7:0] UIREG;
  output       URSTB;
  output 	   UDRCK;
  output       UTDI;
  output       TDO;

`ifndef IDENTIFY_DEBUG_IMPL


  UJTAG UJTAG_inst(

				.UTDO   ( UTDO ),
				.TDI    ( TDI ),
				.TMS    ( TMS ),
				.TCK    ( TCK ),
				.TRSTB  ( TRSTB ),

				.UDRCAP ( UDRCAP ),
				.UDRSH  ( UDRSH ),
				.UDRUPD ( UDRUPD ),
				.UIREG  ( UIREG ),
				.URSTB  ( URSTB ),
				.UDRCK  ( UDRCK ),
				.UTDI   ( UTDI ),
				.TDO    ( TDO )
        );

`else

  wire 	 utdo_wire;
  wire   tdi_wire;
  wire   tms_wire;
  wire   tck_wire;
  wire   trstb_wire;
  
  assign utdo_wire 	= UTDO ;
  assign tdi_wire 	= TDI;
  assign tms_wire 	= TMS;
  assign tck_wire 	= TCK;
  assign trstb_wire = TRSTB;
  

  syn_hyper_connect_internal hyperc_ujtag_wrapper_uireg(UIREG);
  defparam hyperc_ujtag_wrapper_uireg.w = 8;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_urstb(URSTB);
  defparam hyperc_ujtag_wrapper_urstb.w = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_udrupd(UDRUPD);
  defparam hyperc_ujtag_wrapper_udrupd.w = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_udrck(UDRCK);
  defparam hyperc_ujtag_wrapper_udrck.w = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_udrcap(UDRCAP);
  defparam hyperc_ujtag_wrapper_udrcap.w = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_udrsh(UDRSH);
  defparam hyperc_ujtag_wrapper_udrsh.w = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_utdi(UTDI);
  defparam hyperc_ujtag_wrapper_utdi.w = 1;

  syn_hyper_source_internal hypers_ujtag_wrapper_utdo(utdo_wire);
  defparam hypers_ujtag_wrapper_utdo.w 	  = 1;


  syn_hyper_source_internal hypers_ujtag_wrapper_tdi(tdi_wire);
  defparam hypers_ujtag_wrapper_tdi.w 	 = 1;

  syn_hyper_source_internal hypers_ujtag_wrapper_tms(tms_wire);
  defparam hypers_ujtag_wrapper_tms.w 	  = 1;
  
  syn_hyper_source_internal hypers_ujtag_wrapper_tck(tck_wire);
  defparam hypers_ujtag_wrapper_tck.w 	  = 1;

  syn_hyper_source_internal hypers_ujtag_wrapper_trstb(trstb_wire);
  defparam hypers_ujtag_wrapper_trstb.w 	  = 1;

  syn_hyper_connect_internal hyperc_ujtag_wrapper_tdo(TDO);
  defparam hyperc_ujtag_wrapper_tdo.w = 1;
  
`endif
  
endmodule