data/full_repos/permissive/143278/ivltests/decl_assign1.v
 line:26: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/decl_assign1.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (i !== 8) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   integer i = 8;
   time    t = 0;


   initial begin
      #1 if (i !== 8) begin
         $display("FAILED -- i == %b", i);
         $finish;
      end

      if (t !== 0) begin
         $display("FAILED -- t == %b", t);
         $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   integer i = 8;
   time    t = 0;


   initial begin
      #1 if (i !== 8) begin
         $display("FAILED -- i == %b", i);
         $finish;
      end

      if (t !== 0) begin
         $display("FAILED -- t == %b", t);
         $finish;
      end

      $display("PASSED");
   end

endmodule