data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_converter.v
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_converter.v:1: Cannot find include file: line_decoder.v\n`include "line_decoder.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem5,data/full_repos/permissive/202237519/line_decoder.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem5,data/full_repos/permissive/202237519/line_decoder.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem5,data/full_repos/permissive/202237519/line_decoder.v.sv\n             line_decoder.v\n             line_decoder.v.v\n             line_decoder.v.sv\n             obj_dir/line_decoder.v\n             obj_dir/line_decoder.v.v\n             obj_dir/line_decoder.v.sv\n%Error: Exiting due to 1 error(s)\n'
module BCD_converter(B,P);

input [3:0]B;
output [9:0]P;
wire [10:0]T;

line_decoder C1 ({3'b000,B[3]},T[3:0]);
line_decoder C2 ({T[2:0],B[2]},T[7:4]);
line_decoder C3 ({3'b000,T[3]},{P[9],T[10:8]});
line_decoder C4 ({T[6:4],B1},P[4:1]);
line_decoder C5 (T[10:7],P[8:5]);


endmodule
module BCD_converter(B,P);


input [3:0]B;
output [9:0]P;
wire [10:0]T;

line_decoder C1 ({3'b000,B[3]},T[3:0]);
line_decoder C2 ({T[2:0],B[2]},T[7:4]);
line_decoder C3 ({3'b000,T[3]},{P[9],T[10:8]});
line_decoder C4 ({T[6:4],B1},P[4:1]);
line_decoder C5 (T[10:7],P[8:5]);


endmodule