data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc/bit_slip.sv
 line:60: before: ";"
1: b'%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc/bit_slip.sv:54: Operator SUB expects 32 or 6 bits on the RHS, but RHS\'s VARREF \'slip_amount\' generates 3 bits.\n                                                                                              : ... In instance bit_slip\n    assign slip_data   = data_window[WinBits-1-slip_amount -: DataBits];\n                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc/bit_slip.sv:70: Cannot find file containing module: \'stream_buf_v\'\n  stream_buf_v #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc,data/full_repos/permissive/181738725/stream_buf_v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc,data/full_repos/permissive/181738725/stream_buf_v.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc,data/full_repos/permissive/181738725/stream_buf_v.sv\n             stream_buf_v\n             stream_buf_v.v\n             stream_buf_v.sv\n             obj_dir/stream_buf_v\n             obj_dir/stream_buf_v.v\n             obj_dir/stream_buf_v.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module bit_slip #(
  parameter  DataBits     = 32,
  parameter  MaxSlip      = 7,
  parameter  LittleEndian = 1)
(
  input                         clk,
  input                         rst,

  input                         din_valid,
  output                        din_ready,
  input [DataBits-1:0]          din_data,

  output                        dout_valid,
  input                         dout_ready,
  output [DataBits-1:0]         dout_data,

  input [$clog2(MaxSlip+1)-1:0] slip_amount
);

  localparam MaxSlipBits = $clog2(MaxSlip + 1);
  localparam WinBits = DataBits + MaxSlip;

  logic [WinBits-1:0]  data_window;
  logic [DataBits-1:0] slip_data;
  logic [MaxSlip-1:0]  data_reg_n;
  logic [MaxSlip-1:0]  data_reg;


  generate if (LittleEndian) begin: little
    assign data_window = {din_data, data_reg};
    assign slip_data   = data_window[WinBits-1-slip_amount -: DataBits];
    assign data_reg_n  = din_data[DataBits-1 -: MaxSlip];
  end else begin: big
    assign data_window = {data_reg, din_data};
    assign slip_data   = data_window[slip_amount +: DataBits];
    assign data_reg_n  = din_data[0 +: MaxSlip];
  end endgenerate;


  always_ff @(posedge clk) begin
    if (din_valid & din_ready) begin
      data_reg <= data_reg_n;
    end
  end


  stream_buf_v #(
    .DataBits(DataBits))
  obuf (
    .clk      (clk),
    .rst      (rst),
    .in_valid (din_valid),
    .in_ready (din_ready),
    .in_data  (slip_data),
    .out_valid(dout_valid),
    .out_ready(dout_ready),
    .out_data (dout_data));

endmodule
module bit_slip #(
  parameter  DataBits     = 32,
  parameter  MaxSlip      = 7,
  parameter  LittleEndian = 1)
(
  input                         clk,
  input                         rst,

  input                         din_valid,
  output                        din_ready,
  input [DataBits-1:0]          din_data,

  output                        dout_valid,
  input                         dout_ready,
  output [DataBits-1:0]         dout_data,

  input [$clog2(MaxSlip+1)-1:0] slip_amount
);


  localparam MaxSlipBits = $clog2(MaxSlip + 1);
  localparam WinBits = DataBits + MaxSlip;

  logic [WinBits-1:0]  data_window;
  logic [DataBits-1:0] slip_data;
  logic [MaxSlip-1:0]  data_reg_n;
  logic [MaxSlip-1:0]  data_reg;


  generate if (LittleEndian) begin: little
    assign data_window = {din_data, data_reg};
    assign slip_data   = data_window[WinBits-1-slip_amount -: DataBits];
    assign data_reg_n  = din_data[DataBits-1 -: MaxSlip];
  end else begin: big
    assign data_window = {data_reg, din_data};
    assign slip_data   = data_window[slip_amount +: DataBits];
    assign data_reg_n  = din_data[0 +: MaxSlip];
  end endgenerate;


  always_ff @(posedge clk) begin
    if (din_valid & din_ready) begin
      data_reg <= data_reg_n;
    end
  end


  stream_buf_v #(
    .DataBits(DataBits))
  obuf (
    .clk      (clk),
    .rst      (rst),
    .in_valid (din_valid),
    .in_ready (din_ready),
    .in_data  (slip_data),
    .out_valid(dout_valid),
    .out_ready(dout_ready),
    .out_data (dout_data));

endmodule