data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:136: Operator GT expects 11 bits on the RHS, but RHS\'s SEL generates 10 bits.\n                                                                                        : ... In instance oscillo\n      if (Threshold3[i]>triggertot[ram_width-1:0]) begin  \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:125: Logical Operator IF expects 1 bit on the If, but If\'s ARRAYSEL generates 11 bits.\n                                                                                        : ... In instance oscillo\n     if (Threshold3[i]) begin\n     ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:123: Logical Operator IF expects 1 bit on the If, but If\'s SEL generates 10 bits.\n                                                                                        : ... In instance oscillo\n    if (triggertot[ram_width-1:0]) begin\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:162: Operator GT expects 11 bits on the RHS, but RHS\'s SEL generates 10 bits.\n                                                                                        : ... In instance oscillo\n      if (Threshold3[i]>triggertot[ram_width-1:0]) begin  \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:151: Logical Operator IF expects 1 bit on the If, but If\'s ARRAYSEL generates 11 bits.\n                                                                                        : ... In instance oscillo\n     if (Threshold3[i]) begin     \n     ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:149: Logical Operator IF expects 1 bit on the If, but If\'s SEL generates 10 bits.\n                                                                                        : ... In instance oscillo\n    if (triggertot[ram_width-1:0]) begin\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:221: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                                        : ... In instance oscillo\nassign downsamplego = downsamplecounter[downsample] || downsample==0;  \n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:267: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash1_reg\' generates 8 bits.\n                                                                                        : ... In instance oscillo\n  highres1=highres1+data_flash1_reg;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:268: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash2_reg\' generates 8 bits.\n                                                                                        : ... In instance oscillo\n  highres2=highres2+data_flash2_reg;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:269: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash3_reg\' generates 8 bits.\n                                                                                        : ... In instance oscillo\n  highres3=highres3+data_flash3_reg;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:270: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'data_flash4_reg\' generates 8 bits.\n                                                                                        : ... In instance oscillo\n  highres4=highres4+data_flash4_reg;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:274: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n                                                                                        : ... In instance oscillo\n    dout1=highres1>>maxhighres;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:275: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n                                                                                        : ... In instance oscillo\n    dout2=highres2>>maxhighres;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:276: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n                                                                                        : ... In instance oscillo\n    dout3=highres3>>maxhighres;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:277: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n                                                                                        : ... In instance oscillo\n    dout4=highres4>>maxhighres;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:280: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n                                                                                        : ... In instance oscillo\n    dout1=highres1>>downsample;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:281: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n                                                                                        : ... In instance oscillo\n    dout2=highres2>>downsample;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:282: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n                                                                                        : ... In instance oscillo\n    dout3=highres3>>downsample;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/oscillo.v:283: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n                                                                                        : ... In instance oscillo\n    dout4=highres4>>downsample;\n         ^\n%Error: Exiting due to 19 warning(s)\n'
module oscillo(clk, startTrigger, clk_flash, data_flash1, data_flash2, data_flash3, data_flash4, pwr1, pwr2, shdn_out, spen_out, trig_in, trig_out, rden, rdaddress, 
data_ready, wraddress_triggerpoint, imthelast, imthefirst,rollingtrigger,trigDebug,triggerpoint,downsample,
trigthresh,trigchannels,triggertype,triggertot,format_sdin_out,div_sclk_out,outsel_cs_out,clk_spi,SPIsend,SPIsenddata,
wraddress,Acquiring,SPIstate,clk_flash2,trigthresh2,dout1,dout2,dout3,dout4,highres,ext_trig_in,use_ext_trig, nsmp);
input clk,clk_spi;
input startTrigger;
input [1:0] trig_in;
output reg [1:0] trig_out;
output reg pwr1=0;
output reg pwr2=0;
output reg shdn_out=0;
output reg spen_out=0;
output reg format_sdin_out=0;
output reg div_sclk_out=0;
output reg outsel_cs_out=1;
input clk_flash, clk_flash2;
input [7:0] data_flash1, data_flash2, data_flash3, data_flash4;
output reg [7:0] dout1, dout2, dout3, dout4;
parameter ram_width=10;
output reg[ram_width-1:0] wraddress_triggerpoint;
input wire [ram_width-1:0] rdaddress;
input wire rden;
output reg data_ready=0;
input wire imthelast, imthefirst;
input wire rollingtrigger;
output reg trigDebug=1;
input [7:0] trigthresh, trigthresh2;
input [3:0] trigchannels;
input [ram_width-1:0] triggerpoint;
input [7:0] downsample;
input [3:0] triggertype;
input [ram_width:0] triggertot;
input highres;
parameter maxhighres=5;
reg [7+maxhighres:0] highres1, highres2, highres3, highres4;
input ext_trig_in, use_ext_trig;
input [ram_width-1:0] nsmp;

reg [31:0] SPIcounter=0;
input [15:0] SPIsenddata;
input SPIsend;
reg [3:0] SPIsendcounter;
localparam SPI0=0, SPI1=1, SPI2=2, SPI3=3;
output reg[3:0] SPIstate=SPI0;
always @(posedge clk_spi) begin
if (!spen_out) begin
SPIcounter=SPIcounter+1;
case (SPIstate)
	SPI0: begin
		if (SPIsend) begin
			SPIcounter=0;
			outsel_cs_out=1;
			div_sclk_out=1;
			SPIsendcounter=4'b1111;
			SPIstate=SPI1;
		end
	end
	SPI1: begin
		if (SPIcounter[2]) begin
			div_sclk_out=0;
			outsel_cs_out=0;
			format_sdin_out=SPIsenddata[SPIsendcounter];
			SPIsendcounter=SPIsendcounter-4'b001;
			SPIstate=SPI2;
		end
	end
	SPI2: begin
		if (!SPIcounter[2]) begin
			div_sclk_out=1;
			if (SPIsendcounter==4'b1111) SPIstate=SPI3;
			else SPIstate=SPI1;
		end
	end
	SPI3: begin
		if (SPIcounter[2]) begin
			outsel_cs_out=1;
			div_sclk_out=0;
			SPIstate=SPI0;
		end
	end
endcase
end
end

reg Threshold1[3:0], Threshold2[3:0];
reg [ram_width:0] Threshold3[3:0];
reg selftrigtemp[3:0];
reg Trigger;
reg AcquiringAndTriggered=0;
reg HaveFullData=0;
integer i;
initial begin
	Threshold3[0]=0;
	Threshold3[1]=0;
	Threshold3[2]=0;
	Threshold3[3]=0;
end
reg [ram_width-1:0] samplecount=0;
output reg [ram_width-1:0] wraddress;
output reg Acquiring;
reg PreOrPostAcquiring;

reg [7:0] data_flash1_reg; always @(posedge clk_flash) data_flash1_reg <= data_flash1;
reg [7:0] data_flash2_reg; always @(posedge clk_flash) data_flash2_reg <= data_flash2;


reg [7:0] data_flash3_reg; always @(posedge clk_flash2) data_flash3_reg <= data_flash3;
reg [7:0] data_flash4_reg; always @(posedge clk_flash2) data_flash4_reg <= data_flash4;


always @(posedge clk_flash) begin
	i=0;
	while (i<4) begin
		if (trigchannels[i]) begin

			if (i==0) Threshold1[i] <= (data_flash1_reg>=trigthresh && data_flash1_reg<=trigthresh2);
			if (i==1) Threshold1[i] <= (data_flash2_reg>=trigthresh && data_flash2_reg<=trigthresh2);
			if (i==2) Threshold1[i] <= (data_flash3_reg>=trigthresh && data_flash3_reg<=trigthresh2);
			if (i==3) Threshold1[i] <= (data_flash4_reg>=trigthresh && data_flash4_reg<=trigthresh2);
			Threshold2[i] <= Threshold1[i];
			
			if (triggertype[0]) begin
				if (triggertot[ram_width-1:0]) begin
					selftrigtemp[i] = 0;
					if (Threshold3[i]) begin
						if (triggertot[ram_width]) begin
							if (downsamplego) begin
								if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
								else Threshold3[i] <= 0;
							end
						end
						else begin
							if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
							else Threshold3[i] <= 0;
						end
						if (Threshold3[i]>triggertot[ram_width-1:0]) begin
							selftrigtemp[i] = 1;
							Threshold3[i] <= 0;
						end
					end
					else if (Threshold1[i] & ~Threshold2[i]) begin
						Threshold3[i] <= 1;
					end
				end
				else selftrigtemp[i] <= (Threshold1[i] & ~Threshold2[i]);
			end
			
			else begin
				if (triggertot[ram_width-1:0]) begin
					selftrigtemp[i] = 0;
					if (Threshold3[i]) begin					
						if (triggertot[ram_width]) begin
							if (downsamplego) begin
								if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
								else Threshold3[i] <= 0;
							end
						end
						else begin
							if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
							else Threshold3[i] <= 0;
						end						
						if (Threshold3[i]>triggertot[ram_width-1:0]) begin
							selftrigtemp[i] = 1;
							Threshold3[i] <= 0;
						end
					end
					else if (~Threshold1[i] & Threshold2[i]) begin
						Threshold3[i] <= 1;
					end
				end
				else selftrigtemp[i] <= (~Threshold1[i] & Threshold2[i]);
			end
			
		end
		i=i+1;
	end
end

reg[12:0] ext_trig_in_delay_bits=0;
reg ext_trig_in_delayed;
always @(posedge clk_flash) begin
	ext_trig_in_delayed <= ext_trig_in_delay_bits[12];
	ext_trig_in_delay_bits <= {ext_trig_in_delay_bits[12-1:0], ext_trig_in};
end

reg[31:0] thecounter;
always @(posedge clk_flash) if (Trigger) thecounter<=0; else thecounter<=thecounter+1;
wire selftrig;
assign selftrig = (trigchannels[0]&&selftrigtemp[0])||(trigchannels[1]&&selftrigtemp[1])||(trigchannels[2]&&selftrigtemp[2])||(trigchannels[3]&&selftrigtemp[3]) ||(rollingtrigger&thecounter>=25000000) || (use_ext_trig&ext_trig_in_delayed);

always @(posedge clk_flash)
if (imthefirst & imthelast) Trigger = selftrig;
else if (imthefirst) Trigger = selftrig||trig_in[1];
else if (imthelast) Trigger = selftrig||trig_in[0];
else Trigger = selftrig||trig_in[0]||trig_in[1];

always @(posedge clk_flash)
if (imthefirst) trig_out[0] = selftrig;
else trig_out[0] = trig_in[0]||selftrig;

always @(posedge clk_flash)
if (imthelast) trig_out[1] = selftrig;
else trig_out[1] = trig_in[1]||selftrig;



reg startAcquisition;
always @(posedge clk) begin
	if(~startAcquisition) startAcquisition <= startTrigger;
	else if(AcquiringAndTriggered2) startAcquisition <= 0;

end
reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;

localparam INIT=0, PREACQ=1, WAITING=2, POSTACQ=3;
integer state=INIT;
reg [31:0] downsamplecounter;
reg [maxhighres:0] highrescounter;
wire downsamplego;
assign downsamplego = downsamplecounter[downsample] || downsample==0;
always @(posedge clk_flash) begin
	case (state)
	INIT: begin
		if (startAcquisition2) begin
			samplecount <= 0;
			Acquiring <= 1;
			HaveFullData <= 0;
			PreOrPostAcquiring <= 1;
			downsamplecounter=1;
			highrescounter=0;
			highres1=0;
			highres2=0;
			highres3=0;
			highres4=0;
			state=PREACQ;
		end
	end
	PREACQ: begin
		if( (samplecount==triggerpoint) ) begin
			PreOrPostAcquiring <= 0;
			state=WAITING;
		end
	end
	WAITING: begin
		if(Trigger) begin
			AcquiringAndTriggered <= 1;
			PreOrPostAcquiring <= 1;
			wraddress_triggerpoint <= wraddress;
			state=POSTACQ;
		end
	end
	POSTACQ: begin
		if(samplecount==nsmp) begin
			Acquiring <= 0;
			AcquiringAndTriggered <= 0;
			HaveFullData <= 1;
			PreOrPostAcquiring <= 0;
			state=INIT;
		end
	end
	endcase
	
	downsamplecounter=downsamplecounter+1;
	if (highres && downsample>0) begin
		highrescounter=highrescounter+1;
		highres1=highres1+data_flash1_reg;
		highres2=highres2+data_flash2_reg;
		highres3=highres3+data_flash3_reg;
		highres4=highres4+data_flash4_reg;
		if (downsamplego || highrescounter[maxhighres]) begin
			highrescounter=0;
			if (downsample>maxhighres) begin			
				dout1=highres1>>maxhighres;
				dout2=highres2>>maxhighres;
				dout3=highres3>>maxhighres;
				dout4=highres4>>maxhighres;
			end
			else begin
				dout1=highres1>>downsample;
				dout2=highres2>>downsample;
				dout3=highres3>>downsample;
				dout4=highres4>>downsample;
			end
			highres1=0;
			highres2=0;
			highres3=0;
			highres4=0;
		end
	end
	else begin
		dout1=data_flash1_reg;
		dout2=data_flash2_reg;
		dout3=data_flash3_reg;
		dout4=data_flash4_reg;
	end
	if (downsamplego) begin
		downsamplecounter=1;
		if(Acquiring) wraddress <= wraddress + 1;
		if(PreOrPostAcquiring) samplecount <= samplecount + 1;
	end
end


reg AcquiringAndTriggered1; always @(posedge clk) AcquiringAndTriggered1 <= AcquiringAndTriggered;
reg AcquiringAndTriggered2; always @(posedge clk) AcquiringAndTriggered2 <= AcquiringAndTriggered1;
reg HaveFullData1; always @(posedge clk) HaveFullData1 <= HaveFullData;
reg HaveFullData2; always @(posedge clk) HaveFullData2 <= HaveFullData1;

always @(posedge clk) begin
	if (startAcquisition) data_ready=0;
	else if (HaveFullData2) data_ready=1;
end

endmodule
module oscillo(clk, startTrigger, clk_flash, data_flash1, data_flash2, data_flash3, data_flash4, pwr1, pwr2, shdn_out, spen_out, trig_in, trig_out, rden, rdaddress, 
data_ready, wraddress_triggerpoint, imthelast, imthefirst,rollingtrigger,trigDebug,triggerpoint,downsample,
trigthresh,trigchannels,triggertype,triggertot,format_sdin_out,div_sclk_out,outsel_cs_out,clk_spi,SPIsend,SPIsenddata,
wraddress,Acquiring,SPIstate,clk_flash2,trigthresh2,dout1,dout2,dout3,dout4,highres,ext_trig_in,use_ext_trig, nsmp);

input clk,clk_spi;
input startTrigger;
input [1:0] trig_in;
output reg [1:0] trig_out;
output reg pwr1=0;
output reg pwr2=0;
output reg shdn_out=0;
output reg spen_out=0;
output reg format_sdin_out=0;
output reg div_sclk_out=0;
output reg outsel_cs_out=1;
input clk_flash, clk_flash2;
input [7:0] data_flash1, data_flash2, data_flash3, data_flash4;
output reg [7:0] dout1, dout2, dout3, dout4;
parameter ram_width=10;
output reg[ram_width-1:0] wraddress_triggerpoint;
input wire [ram_width-1:0] rdaddress;
input wire rden;
output reg data_ready=0;
input wire imthelast, imthefirst;
input wire rollingtrigger;
output reg trigDebug=1;
input [7:0] trigthresh, trigthresh2;
input [3:0] trigchannels;
input [ram_width-1:0] triggerpoint;
input [7:0] downsample;
input [3:0] triggertype;
input [ram_width:0] triggertot;
input highres;
parameter maxhighres=5;
reg [7+maxhighres:0] highres1, highres2, highres3, highres4;
input ext_trig_in, use_ext_trig;
input [ram_width-1:0] nsmp;

reg [31:0] SPIcounter=0;
input [15:0] SPIsenddata;
input SPIsend;
reg [3:0] SPIsendcounter;
localparam SPI0=0, SPI1=1, SPI2=2, SPI3=3;
output reg[3:0] SPIstate=SPI0;
always @(posedge clk_spi) begin
if (!spen_out) begin
SPIcounter=SPIcounter+1;
case (SPIstate)
	SPI0: begin
		if (SPIsend) begin
			SPIcounter=0;
			outsel_cs_out=1;
			div_sclk_out=1;
			SPIsendcounter=4'b1111;
			SPIstate=SPI1;
		end
	end
	SPI1: begin
		if (SPIcounter[2]) begin
			div_sclk_out=0;
			outsel_cs_out=0;
			format_sdin_out=SPIsenddata[SPIsendcounter];
			SPIsendcounter=SPIsendcounter-4'b001;
			SPIstate=SPI2;
		end
	end
	SPI2: begin
		if (!SPIcounter[2]) begin
			div_sclk_out=1;
			if (SPIsendcounter==4'b1111) SPIstate=SPI3;
			else SPIstate=SPI1;
		end
	end
	SPI3: begin
		if (SPIcounter[2]) begin
			outsel_cs_out=1;
			div_sclk_out=0;
			SPIstate=SPI0;
		end
	end
endcase
end
end

reg Threshold1[3:0], Threshold2[3:0];
reg [ram_width:0] Threshold3[3:0];
reg selftrigtemp[3:0];
reg Trigger;
reg AcquiringAndTriggered=0;
reg HaveFullData=0;
integer i;
initial begin
	Threshold3[0]=0;
	Threshold3[1]=0;
	Threshold3[2]=0;
	Threshold3[3]=0;
end
reg [ram_width-1:0] samplecount=0;
output reg [ram_width-1:0] wraddress;
output reg Acquiring;
reg PreOrPostAcquiring;

reg [7:0] data_flash1_reg; always @(posedge clk_flash) data_flash1_reg <= data_flash1;
reg [7:0] data_flash2_reg; always @(posedge clk_flash) data_flash2_reg <= data_flash2;


reg [7:0] data_flash3_reg; always @(posedge clk_flash2) data_flash3_reg <= data_flash3;
reg [7:0] data_flash4_reg; always @(posedge clk_flash2) data_flash4_reg <= data_flash4;


always @(posedge clk_flash) begin
	i=0;
	while (i<4) begin
		if (trigchannels[i]) begin

			if (i==0) Threshold1[i] <= (data_flash1_reg>=trigthresh && data_flash1_reg<=trigthresh2);
			if (i==1) Threshold1[i] <= (data_flash2_reg>=trigthresh && data_flash2_reg<=trigthresh2);
			if (i==2) Threshold1[i] <= (data_flash3_reg>=trigthresh && data_flash3_reg<=trigthresh2);
			if (i==3) Threshold1[i] <= (data_flash4_reg>=trigthresh && data_flash4_reg<=trigthresh2);
			Threshold2[i] <= Threshold1[i];
			
			if (triggertype[0]) begin
				if (triggertot[ram_width-1:0]) begin
					selftrigtemp[i] = 0;
					if (Threshold3[i]) begin
						if (triggertot[ram_width]) begin
							if (downsamplego) begin
								if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
								else Threshold3[i] <= 0;
							end
						end
						else begin
							if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
							else Threshold3[i] <= 0;
						end
						if (Threshold3[i]>triggertot[ram_width-1:0]) begin
							selftrigtemp[i] = 1;
							Threshold3[i] <= 0;
						end
					end
					else if (Threshold1[i] & ~Threshold2[i]) begin
						Threshold3[i] <= 1;
					end
				end
				else selftrigtemp[i] <= (Threshold1[i] & ~Threshold2[i]);
			end
			
			else begin
				if (triggertot[ram_width-1:0]) begin
					selftrigtemp[i] = 0;
					if (Threshold3[i]) begin					
						if (triggertot[ram_width]) begin
							if (downsamplego) begin
								if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
								else Threshold3[i] <= 0;
							end
						end
						else begin
							if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1;
							else Threshold3[i] <= 0;
						end						
						if (Threshold3[i]>triggertot[ram_width-1:0]) begin
							selftrigtemp[i] = 1;
							Threshold3[i] <= 0;
						end
					end
					else if (~Threshold1[i] & Threshold2[i]) begin
						Threshold3[i] <= 1;
					end
				end
				else selftrigtemp[i] <= (~Threshold1[i] & Threshold2[i]);
			end
			
		end
		i=i+1;
	end
end

reg[12:0] ext_trig_in_delay_bits=0;
reg ext_trig_in_delayed;
always @(posedge clk_flash) begin
	ext_trig_in_delayed <= ext_trig_in_delay_bits[12];
	ext_trig_in_delay_bits <= {ext_trig_in_delay_bits[12-1:0], ext_trig_in};
end

reg[31:0] thecounter;
always @(posedge clk_flash) if (Trigger) thecounter<=0; else thecounter<=thecounter+1;
wire selftrig;
assign selftrig = (trigchannels[0]&&selftrigtemp[0])||(trigchannels[1]&&selftrigtemp[1])||(trigchannels[2]&&selftrigtemp[2])||(trigchannels[3]&&selftrigtemp[3]) ||(rollingtrigger&thecounter>=25000000) || (use_ext_trig&ext_trig_in_delayed);

always @(posedge clk_flash)
if (imthefirst & imthelast) Trigger = selftrig;
else if (imthefirst) Trigger = selftrig||trig_in[1];
else if (imthelast) Trigger = selftrig||trig_in[0];
else Trigger = selftrig||trig_in[0]||trig_in[1];

always @(posedge clk_flash)
if (imthefirst) trig_out[0] = selftrig;
else trig_out[0] = trig_in[0]||selftrig;

always @(posedge clk_flash)
if (imthelast) trig_out[1] = selftrig;
else trig_out[1] = trig_in[1]||selftrig;



reg startAcquisition;
always @(posedge clk) begin
	if(~startAcquisition) startAcquisition <= startTrigger;
	else if(AcquiringAndTriggered2) startAcquisition <= 0;

end
reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;

localparam INIT=0, PREACQ=1, WAITING=2, POSTACQ=3;
integer state=INIT;
reg [31:0] downsamplecounter;
reg [maxhighres:0] highrescounter;
wire downsamplego;
assign downsamplego = downsamplecounter[downsample] || downsample==0;
always @(posedge clk_flash) begin
	case (state)
	INIT: begin
		if (startAcquisition2) begin
			samplecount <= 0;
			Acquiring <= 1;
			HaveFullData <= 0;
			PreOrPostAcquiring <= 1;
			downsamplecounter=1;
			highrescounter=0;
			highres1=0;
			highres2=0;
			highres3=0;
			highres4=0;
			state=PREACQ;
		end
	end
	PREACQ: begin
		if( (samplecount==triggerpoint) ) begin
			PreOrPostAcquiring <= 0;
			state=WAITING;
		end
	end
	WAITING: begin
		if(Trigger) begin
			AcquiringAndTriggered <= 1;
			PreOrPostAcquiring <= 1;
			wraddress_triggerpoint <= wraddress;
			state=POSTACQ;
		end
	end
	POSTACQ: begin
		if(samplecount==nsmp) begin
			Acquiring <= 0;
			AcquiringAndTriggered <= 0;
			HaveFullData <= 1;
			PreOrPostAcquiring <= 0;
			state=INIT;
		end
	end
	endcase
	
	downsamplecounter=downsamplecounter+1;
	if (highres && downsample>0) begin
		highrescounter=highrescounter+1;
		highres1=highres1+data_flash1_reg;
		highres2=highres2+data_flash2_reg;
		highres3=highres3+data_flash3_reg;
		highres4=highres4+data_flash4_reg;
		if (downsamplego || highrescounter[maxhighres]) begin
			highrescounter=0;
			if (downsample>maxhighres) begin			
				dout1=highres1>>maxhighres;
				dout2=highres2>>maxhighres;
				dout3=highres3>>maxhighres;
				dout4=highres4>>maxhighres;
			end
			else begin
				dout1=highres1>>downsample;
				dout2=highres2>>downsample;
				dout3=highres3>>downsample;
				dout4=highres4>>downsample;
			end
			highres1=0;
			highres2=0;
			highres3=0;
			highres4=0;
		end
	end
	else begin
		dout1=data_flash1_reg;
		dout2=data_flash2_reg;
		dout3=data_flash3_reg;
		dout4=data_flash4_reg;
	end
	if (downsamplego) begin
		downsamplecounter=1;
		if(Acquiring) wraddress <= wraddress + 1;
		if(PreOrPostAcquiring) samplecount <= samplecount + 1;
	end
end


reg AcquiringAndTriggered1; always @(posedge clk) AcquiringAndTriggered1 <= AcquiringAndTriggered;
reg AcquiringAndTriggered2; always @(posedge clk) AcquiringAndTriggered2 <= AcquiringAndTriggered1;
reg HaveFullData1; always @(posedge clk) HaveFullData1 <= HaveFullData;
reg HaveFullData2; always @(posedge clk) HaveFullData2 <= HaveFullData1;

always @(posedge clk) begin
	if (startAcquisition) data_ready=0;
	else if (HaveFullData2) data_ready=1;
end

endmodule