data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v
1: b'%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:3: Cannot find include file: ../../define/global_def.v\n`include "../../define/global_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v.v\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v.sv\n             ../../define/global_def.v\n             ../../define/global_def.v.v\n             ../../define/global_def.v.sv\n             obj_dir/../../define/global_def.v\n             obj_dir/../../define/global_def.v.v\n             obj_dir/../../define/global_def.v.sv\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:4: Cannot find include file: ../../define/op_def.v\n`include "../../define/op_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:5: Cannot find include file: ../../define/funct_def.v\n`include "../../define/funct_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:6: Cannot find include file: ../../define/segpos_def.v\n`include "../../define/segpos_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:15: Define or directive not defined: \'`ADDR_BUS\'\n    input   wire[`ADDR_BUS]     pc,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`ADDR_BUS]     pc,\n                          ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:16: Define or directive not defined: \'`INST_BUS\'\n    input   wire[`INST_BUS]     inst,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:19: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     reg_val_mux_data_1,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:20: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     reg_val_mux_data_2,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:24: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg [`REG_ADDR_BUS] reg_addr_1,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:24: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  reg [`REG_ADDR_BUS] reg_addr_1,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg [`REG_ADDR_BUS] reg_addr_2,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:26: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  reg [`REG_ADDR_BUS] reg_addr_2,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                ram_write_en,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:33: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                ram_read_flag,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:34: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`DATA_BUS]     operand_1,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:34: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     operand_1,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:35: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     operand_2,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:37: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`REG_ADDR_BUS] write_reg_addr\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:37: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  wire[`REG_ADDR_BUS] write_reg_addr\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:40: Define or directive not defined: \'`INST_OP_BUS\'\n    wire[`INST_OP_BUS]  inst_op     = inst[`SEG_OPCODE];\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`INST_OP_BUS]  inst_op     = inst[`SEG_OPCODE];\n                     ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:40: Define or directive not defined: \'`SEG_OPCODE\'\n    wire[`INST_OP_BUS]  inst_op     = inst[`SEG_OPCODE];\n                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:41: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] inst_rs     = inst[`SEG_RS];\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] inst_rs     = inst[`SEG_RS];\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:41: Define or directive not defined: \'`SEG_RS\'\n    wire[`REG_ADDR_BUS] inst_rs     = inst[`SEG_RS];\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:42: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] inst_rt     = inst[`SEG_RT];\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] inst_rt     = inst[`SEG_RT];\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:42: Define or directive not defined: \'`SEG_RT\'\n    wire[`REG_ADDR_BUS] inst_rt     = inst[`SEG_RT];\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:43: Define or directive not defined: \'`OFFSET_BUS\'\n    wire[`OFFSET_BUS]   inst_offset = inst[`SEG_OFFSET];\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`OFFSET_BUS]   inst_offset = inst[`SEG_OFFSET];\n                    ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:43: Define or directive not defined: \'`SEG_OFFSET\'\n    wire[`OFFSET_BUS]   inst_offset = inst[`SEG_OFFSET];\n                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:45: Define or directive not defined: \'`DATA_BUS\'\n    wire[`DATA_BUS]     sign_extended_offset  = {{16{inst[15]}}, inst_offset};\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`DATA_BUS]     sign_extended_offset  = {{16{inst[15]}}, inst_offset};\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:47: Define or directive not defined: \'`RST_ENABLE\'\n    assign  operand_1 = (rst == `RST_ENABLE) ? `ZERO_WORD : \n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:47: Define or directive not defined: \'`ZERO_WORD\'\n    assign  operand_1 = (rst == `RST_ENABLE) ? `ZERO_WORD : \n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:48: Define or directive not defined: \'`READ_ENABLE\'\n                        (reg_read_en_1 == `READ_ENABLE) ? reg_val_mux_data_1:\n                                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:49: Define or directive not defined: \'`ZERO_WORD\'\n                        `ZERO_WORD;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:51: Define or directive not defined: \'`RST_ENABLE\'\n    assign  operand_2 = (rst == `RST_ENABLE) ? `ZERO_WORD : sign_extended_offset;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:51: Define or directive not defined: \'`ZERO_WORD\'\n    assign  operand_2 = (rst == `RST_ENABLE) ? `ZERO_WORD : sign_extended_offset;\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:54: Define or directive not defined: \'`OP_LB\'\n    assign  ram_read_flag   = ((inst_op == `OP_LB) || (inst_op == `OP_LBU) ||\n                                           ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:54: Define or directive not defined: \'`OP_LBU\'\n    assign  ram_read_flag   = ((inst_op == `OP_LB) || (inst_op == `OP_LBU) ||\n                                                                  ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:55: Define or directive not defined: \'`OP_LH\'\n                               (inst_op == `OP_LH) || (inst_op == `OP_LHU) ||\n                                           ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:55: Define or directive not defined: \'`OP_LHU\'\n                               (inst_op == `OP_LH) || (inst_op == `OP_LHU) ||\n                                                                  ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:56: Define or directive not defined: \'`OP_LW\'\n                               (inst_op == `OP_LW) || (inst_op == `OP_LWL) ||\n                                           ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:56: Define or directive not defined: \'`OP_LWL\'\n                               (inst_op == `OP_LW) || (inst_op == `OP_LWL) ||\n                                                                  ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:57: Define or directive not defined: \'`OP_LWR\'\n                               (inst_op == `OP_LWR)) ? `TRUE  : `FALSE; \n                                           ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:57: Define or directive not defined: \'`TRUE\'\n                               (inst_op == `OP_LWR)) ? `TRUE  : `FALSE; \n                                                       ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:57: Define or directive not defined: \'`FALSE\'\n                               (inst_op == `OP_LWR)) ? `TRUE  : `FALSE; \n                                                                ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_SL.v:60: Define or directive not defined: \'`OP_SB\'\n    wire    ram_write_flag  = ((inst_op == `OP_SB) || (inst_op == `OP_SH)  ||\n                                           ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module  ID_SL(
    input   wire                rst,


    output  wire                inst_sl,


    input   wire[`ADDR_BUS]     pc,
    input   wire[`INST_BUS]     inst,


    input   wire[`DATA_BUS]     reg_val_mux_data_1,
    input   wire[`DATA_BUS]     reg_val_mux_data_2,


    output  reg                 reg_read_en_1,
    output  reg [`REG_ADDR_BUS] reg_addr_1,
    output  reg                 reg_read_en_2,
    output  reg [`REG_ADDR_BUS] reg_addr_2,


    output  wire                ram_en,
    output  wire                ram_write_en,


    output  wire                ram_read_flag,
    output  wire[`DATA_BUS]     operand_1,
    output  wire[`DATA_BUS]     operand_2,
    output  wire                write_reg_en,
    output  wire[`REG_ADDR_BUS] write_reg_addr
);

    wire[`INST_OP_BUS]  inst_op     = inst[`SEG_OPCODE];
    wire[`REG_ADDR_BUS] inst_rs     = inst[`SEG_RS];
    wire[`REG_ADDR_BUS] inst_rt     = inst[`SEG_RT];
    wire[`OFFSET_BUS]   inst_offset = inst[`SEG_OFFSET];

    wire[`DATA_BUS]     sign_extended_offset  = {{16{inst[15]}}, inst_offset};

    assign  operand_1 = (rst == `RST_ENABLE) ? `ZERO_WORD : 
                        (reg_read_en_1 == `READ_ENABLE) ? reg_val_mux_data_1:
                        `ZERO_WORD;
    
    assign  operand_2 = (rst == `RST_ENABLE) ? `ZERO_WORD : sign_extended_offset;


    assign  ram_read_flag   = ((inst_op == `OP_LB) || (inst_op == `OP_LBU) ||
                               (inst_op == `OP_LH) || (inst_op == `OP_LHU) ||
                               (inst_op == `OP_LW) || (inst_op == `OP_LWL) ||
                               (inst_op == `OP_LWR)) ? `TRUE  : `FALSE; 
   

    wire    ram_write_flag  = ((inst_op == `OP_SB) || (inst_op == `OP_SH)  ||
                               (inst_op == `OP_SW) || (inst_op == `OP_SWL) ||
                               (inst_op == `OP_SWR)) ? `TRUE : `FALSE;


    assign  inst_sl = ram_read_flag || ram_write_flag;                      


    always @ (*)    begin
        if (rst == `RST_ENABLE) begin
            reg_read_en_1   <= `READ_DISABLE;
            reg_addr_1      <= `ZERO_REG_ADDR;
            reg_read_en_2   <= `READ_DISABLE;
            reg_addr_2      <= `ZERO_REG_ADDR;
        end else    begin
            case (inst_op)

                `OP_LB, `OP_LBU, `OP_LH, `OP_LHU, `OP_LW:   begin
                    reg_read_en_1   <= `READ_ENABLE;
                    reg_addr_1      <= inst_rs;
                    reg_read_en_2   <= `READ_DISABLE;
                    reg_addr_2      <= `ZERO_REG_ADDR;
                end

                `OP_LWL, `OP_LWR,
                `OP_SB, `OP_SH, `OP_SW, `OP_SWL, `OP_SWR:   begin
                    reg_read_en_1   <= `READ_ENABLE;
                    reg_addr_1      <= inst_rs;
                    reg_read_en_2   <= `READ_ENABLE;
                    reg_addr_2      <= inst_rt;
                end

                default:    begin
                    reg_read_en_1   <= `READ_DISABLE;
                    reg_addr_1      <= `ZERO_REG_ADDR;
                    reg_read_en_2   <= `READ_DISABLE;
                    reg_addr_2      <= `ZERO_REG_ADDR;
                end

            endcase
        end
    end


    assign  write_reg_en    = (rst == `RST_ENABLE) ? `WRITE_DISABLE : 
                              (ram_read_flag == `TRUE) ? `WRITE_ENABLE  : `WRITE_DISABLE;
    assign  write_reg_addr  = (rst == `RST_ENABLE) ? `ZERO_REG_ADDR : 
                              (ram_read_flag == `TRUE) ? inst_rt        : `ZERO_REG_ADDR;    


    assign  ram_en          = (rst == `RST_ENABLE) ? `CHIP_DISABLE :
                              (inst_sl == `TRUE) ? `CHIP_ENABLE : `CHIP_DISABLE;
    assign  ram_write_en    = (rst == `RST_ENABLE) ? `WRITE_DISABLE : 
                              (ram_write_flag == `TRUE) ? `WRITE_ENABLE : `WRITE_DISABLE;

endmodule
module  ID_SL(
    input   wire                rst,


    output  wire                inst_sl,


    input   wire[`ADDR_BUS]     pc,
    input   wire[`INST_BUS]     inst,


    input   wire[`DATA_BUS]     reg_val_mux_data_1,
    input   wire[`DATA_BUS]     reg_val_mux_data_2,


    output  reg                 reg_read_en_1,
    output  reg [`REG_ADDR_BUS] reg_addr_1,
    output  reg                 reg_read_en_2,
    output  reg [`REG_ADDR_BUS] reg_addr_2,


    output  wire                ram_en,
    output  wire                ram_write_en,


    output  wire                ram_read_flag,
    output  wire[`DATA_BUS]     operand_1,
    output  wire[`DATA_BUS]     operand_2,
    output  wire                write_reg_en,
    output  wire[`REG_ADDR_BUS] write_reg_addr
);


    wire[`INST_OP_BUS]  inst_op     = inst[`SEG_OPCODE];
    wire[`REG_ADDR_BUS] inst_rs     = inst[`SEG_RS];
    wire[`REG_ADDR_BUS] inst_rt     = inst[`SEG_RT];
    wire[`OFFSET_BUS]   inst_offset = inst[`SEG_OFFSET];

    wire[`DATA_BUS]     sign_extended_offset  = {{16{inst[15]}}, inst_offset};

    assign  operand_1 = (rst == `RST_ENABLE) ? `ZERO_WORD : 
                        (reg_read_en_1 == `READ_ENABLE) ? reg_val_mux_data_1:
                        `ZERO_WORD;
    
    assign  operand_2 = (rst == `RST_ENABLE) ? `ZERO_WORD : sign_extended_offset;


    assign  ram_read_flag   = ((inst_op == `OP_LB) || (inst_op == `OP_LBU) ||
                               (inst_op == `OP_LH) || (inst_op == `OP_LHU) ||
                               (inst_op == `OP_LW) || (inst_op == `OP_LWL) ||
                               (inst_op == `OP_LWR)) ? `TRUE  : `FALSE; 
   

    wire    ram_write_flag  = ((inst_op == `OP_SB) || (inst_op == `OP_SH)  ||
                               (inst_op == `OP_SW) || (inst_op == `OP_SWL) ||
                               (inst_op == `OP_SWR)) ? `TRUE : `FALSE;


    assign  inst_sl = ram_read_flag || ram_write_flag;                      


    always @ (*)    begin
        if (rst == `RST_ENABLE) begin
            reg_read_en_1   <= `READ_DISABLE;
            reg_addr_1      <= `ZERO_REG_ADDR;
            reg_read_en_2   <= `READ_DISABLE;
            reg_addr_2      <= `ZERO_REG_ADDR;
        end else    begin
            case (inst_op)

                `OP_LB, `OP_LBU, `OP_LH, `OP_LHU, `OP_LW:   begin
                    reg_read_en_1   <= `READ_ENABLE;
                    reg_addr_1      <= inst_rs;
                    reg_read_en_2   <= `READ_DISABLE;
                    reg_addr_2      <= `ZERO_REG_ADDR;
                end

                `OP_LWL, `OP_LWR,
                `OP_SB, `OP_SH, `OP_SW, `OP_SWL, `OP_SWR:   begin
                    reg_read_en_1   <= `READ_ENABLE;
                    reg_addr_1      <= inst_rs;
                    reg_read_en_2   <= `READ_ENABLE;
                    reg_addr_2      <= inst_rt;
                end

                default:    begin
                    reg_read_en_1   <= `READ_DISABLE;
                    reg_addr_1      <= `ZERO_REG_ADDR;
                    reg_read_en_2   <= `READ_DISABLE;
                    reg_addr_2      <= `ZERO_REG_ADDR;
                end

            endcase
        end
    end


    assign  write_reg_en    = (rst == `RST_ENABLE) ? `WRITE_DISABLE : 
                              (ram_read_flag == `TRUE) ? `WRITE_ENABLE  : `WRITE_DISABLE;
    assign  write_reg_addr  = (rst == `RST_ENABLE) ? `ZERO_REG_ADDR : 
                              (ram_read_flag == `TRUE) ? inst_rt        : `ZERO_REG_ADDR;    


    assign  ram_en          = (rst == `RST_ENABLE) ? `CHIP_DISABLE :
                              (inst_sl == `TRUE) ? `CHIP_ENABLE : `CHIP_DISABLE;
    assign  ram_write_en    = (rst == `RST_ENABLE) ? `WRITE_DISABLE : 
                              (ram_write_flag == `TRUE) ? `WRITE_ENABLE : `WRITE_DISABLE;

endmodule