data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sources_1/new/semaforo_FSM.sv
None: at end of input
data/verilator_xmls/faccfd9c-6e34-44a8-b3f6-e433ae4ee5b0.xml
module semaforo_FSM(
	input  logic       clock,
	input  logic       reset, TA, TB,
	output logic [1:0] LA, LB
    );
    
    enum logic[3:0] {STATE_0, STATE_1, STATE_2, STATE_3} state, next_state;
    

    localparam GREEN    = 2'b00;
    localparam YELLOW   = 2'b01;
    localparam RED      = 2'b10;
    


    always_comb begin


        next_state = state;
    	LA = RED;
    	LB = RED;
    	
    	case (state)
    		STATE_0: begin
    			     LA = GREEN;
    			     if(TA == 1'b0) begin
    			 	   next_state = STATE_1;
    		         end
    		    end

            STATE_1: begin
                    LA = YELLOW;
                    next_state = STATE_2;
                end
            
            STATE_2: begin
                    LB = GREEN;
                    if(TB == 1'b0) begin
                        next_state = STATE_3;
                    end
                end

            STATE_3: begin
                    LB = YELLOW;
                    next_state = STATE_0;
                end                
    	endcase
    end	


    always_ff@(posedge clock)
    	if(reset)
    		state <= STATE_0;
    	else
    		state <= next_state;
endmodule
module semaforo_FSM(
	input  logic       clock,
	input  logic       reset, TA, TB,
	output logic [1:0] LA, LB
    );

    
    enum logic[3:0] {STATE_0, STATE_1, STATE_2, STATE_3} state, next_state;
    

    localparam GREEN    = 2'b00;
    localparam YELLOW   = 2'b01;
    localparam RED      = 2'b10;
    


    always_comb begin


        next_state = state;
    	LA = RED;
    	LB = RED;
    	
    	case (state)
    		STATE_0: begin
    			     LA = GREEN;
    			     if(TA == 1'b0) begin
    			 	   next_state = STATE_1;
    		         end
    		    end

            STATE_1: begin
                    LA = YELLOW;
                    next_state = STATE_2;
                end
            
            STATE_2: begin
                    LB = GREEN;
                    if(TB == 1'b0) begin
                        next_state = STATE_3;
                    end
                end

            STATE_3: begin
                    LB = YELLOW;
                    next_state = STATE_0;
                end                
    	endcase
    end	


    always_ff@(posedge clock)
    	if(reset)
    		state <= STATE_0;
    	else
    		state <= next_state;
endmodule