data/full_repos/permissive/174643991/DCPU/DCPU.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/174643991/DCPU/DCPU.v:168: Signal definition not found, creating implicitly: \'HazardWBX\'\n                                                                       : ... Suggested alternative: \'HazardWB\'\n  assign HazardWBX  = WBIR[15]|(WBIR[14:11]==4\'b0010);\n         ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/174643991/DCPU/DCPU.v:153: Cannot find file containing module: \'ALU\'\n  ALU        ALUM(.OPC(EXOP),    \n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/174643991/DCPU,data/full_repos/permissive/174643991/ALU\n             data/full_repos/permissive/174643991/DCPU,data/full_repos/permissive/174643991/ALU.v\n             data/full_repos/permissive/174643991/DCPU,data/full_repos/permissive/174643991/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:237: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'5\'h2\' generates 5 bits.\n                                                                    : ... In instance DCPU\n          if((Inst==5\'b00010)&(~PCSt)) begin\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:278: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                    : ... In instance DCPU\n                      3\'b100:   EXOP <= 5\'b0000;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:279: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h7\' generates 5 bits.\n                                                                    : ... In instance DCPU\n                      3\'b110:   EXOP <= 5\'b0111;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:280: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h2\' generates 5 bits.\n                                                                    : ... In instance DCPU\n                      default:  EXOP <= 5\'b0010;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:284: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h2\' generates 5 bits.\n                                                                    : ... In instance DCPU\n                    EXOP <= 5\'b0010;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:288: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h2\' generates 5 bits.\n                                                                    : ... In instance DCPU\n                      EXOP <= 5\'b0010;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h5\' generates 5 bits.\n                                                                    : ... In instance DCPU\n                      EXOP <= 5\'b0101;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h7\' generates 5 bits.\n                                                                    : ... In instance DCPU\n                      EXOP <= 5\'b0111;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:326: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= IDIR[3:0];\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:334: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= IDIR[3:0];\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:342: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:350: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:358: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:366: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:374: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:382: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:390: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:398: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:406: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:414: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:422: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:430: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:438: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/DCPU.v:446: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance DCPU\n                    EXRB <= {IDIR[7:4],IDIR[3:0]};\n                         ^~\n%Error: Exiting due to 1 error(s), 25 warning(s)\n'
module DCPU(
  input  wire       CLK,
  input  wire       RST,
  input  wire       EN,
  input  wire       Start,
  output wire[7:0]  InstMemAddr,
  input  wire[15:0] Inst,
  output wire[7:0]  DataMemAddr,
  input  wire[15:0] DataIn,
  output wire       DataMemWE,
  output wire[15:0] DataOut
);
  

  `define SIdle 1'b0
  `define SExec 1'b1
  


  `define NOP   5'b00000
  `define HALT  5'b00001

  `define LOAD  5'b00010
  `define STORE 5'b00011

  `define CMP   5'b00100

  `define BE    5'b00101
  `define JUMP  5'b00110
  `define JMPR  5'b00111
  `define BZ    5'b01000
  `define BNZ   5'b01001
  `define BN    5'b01010
  `define BNN   5'b01011
  `define BC    5'b01100
  `define BNC   5'b01101
  `define BB    5'b01110
  `define BS    5'b01111

  `define ADD   5'b10000
  `define ADDI  5'b10001
  `define ADDC  5'b10010
  `define SUB   5'b10011
  `define SUBI  5'b10100
  `define SUBB  5'b10101
  `define INC   5'b10110

  `define LDIL  5'b10111
  `define LDIH  5'b11000

  `define XOR   5'b11001
  `define AND   5'b11010
  `define OR    5'b11011

  `define SLL   5'b11100
  `define SLA   5'b11101
  `define SRL   5'b11110
  `define SRA   5'b11111
  

  `define ALU_CMP   5'b0000
  `define ALU_ADDC  5'b0010
  `define ALU_SUBB  5'b0101
  `define ALU_INC   5'b0110
  `define ALU_LOAD  5'b0111
  `define ALU_XOR   5'b1001
  `define ALU_AND   5'b1010
  `define ALU_OR    5'b1011
  `define ALU_SLL   5'b1100
  `define ALU_SLA   5'b1101
  `define ALU_SRL   5'b1110
  `define ALU_SRA   5'b1111
  
  

  `define EXR1      GR[IDIR[10:8]]
  `define EXR2      GR[IDIR[6:4]]
  `define EXR3      GR[IDIR[2:0]]
  `define EXVAL2    IDIR[7:4]
  `define EXVAL3    IDIR[3:0]
  `define IDR1N     IDIR[10:8]
  `define EXR1N     EXIR[10:8]
  `define MRR1N     MRIR[10:8]
  `define WBR1N     WBIR[10:8]
  `define IDR2N     IDIR[6:4]
  `define IDR3N     IDIR[2:0]
  
  

  reg        state;
  reg        next_state;
  

  reg [7:0]  PC;
  reg [15:0] GR[0:7];
  

  reg [15:0] IDIR;
  reg [15:0] EXIR;
  reg [3:0]  EXOP;
  reg [15:0] MRIR;
  reg [15:0] WBIR;
  

  reg [15:0] EXRA;
  reg [15:0] EXRB;
  reg [15:0] EXSD;
  reg        EXCF;
  reg [15:0] MRRC;
  reg        MRCF;
  reg        MRZF;
  reg        MRNF;
  reg        MRDW;
  reg [15:0] MRSD;
  reg [15:0] WBRC;
  

  reg        PCSt;
  wire       HazardEX;
  wire       HazardEXL;
  wire       HazardMR;
  wire       HazardMRL;
  wire       HazardWB;
  wire       HazardWBL;
  reg [1:0]  BrSt;
  wire       HazardCtrl;
  

  wire[15:0] ALUOUT;
  wire       ALUOCF;
  wire       ALUOZF;
  wire       ALUONF;
  ALU        ALUM(.OPC(EXOP),
                  .IN1(EXRA),
                  .IN2(EXRB),
                  .ICF(EXCF),
                  .OUT(ALUOUT),
                  .OCF(ALUOCF),
                  .OZF(ALUOZF),
                  .ONF(ALUONF)
                  );
  
  

  assign HazardEX   = EXIR[15];
  assign HazardMR   = MRIR[15];
  assign HazardMRL  = (MRIR[14:11]==4'b0010);
  assign HazardWBX  = WBIR[15]|(WBIR[14:11]==4'b0010);
  assign HazardCtrl = (Inst[15:14]==2'b01)
                    | (Inst[15:11]==5'b00101||
                       Inst[15:11]==5'b00110||
                       Inst[15:11]==5'b00111);
  
  

  assign InstMemAddr = PC;
  assign DataMemAddr = MRRC[7:0];
  assign DataMemWE   = MRDW;
  assign DataOut     = MRSD;
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) state <= `SIdle;
    else    state <= next_state;
  end
  
  always @(*) begin
    case(state)
      `SIdle:
        if(EN & Start) next_state <= `SExec;
        else           next_state <= `SIdle;
      `SExec:
        if(!EN | WBIR[15:11]==`HALT) next_state <= `SIdle;
        else                         next_state <= `SExec;
    endcase
  end
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) begin
      IDIR <= 16'b0;
      PC   <= 8'b0;
      PCSt <= 1'b0;
      BrSt <= 2'b0;
    end
    else begin
      if(state==`SExec) begin

        if(BrSt==2'b00) IDIR <= Inst;
        else            IDIR <= 16'b0;

        case(BrSt)
          2'b00: BrSt <= ((HazardCtrl)?(2'b01):(2'b00));
          2'b01: BrSt <= 2'b10;
          2'b10: BrSt <= 2'b11;
          2'b11: BrSt <= 2'b00;
        endcase

        if((MRIR[15:11]==`JUMP)
        || (MRIR[15:11]==`JMPR)
        || (MRIR[15:11]==`BZ  &&  MRZF)
        || (MRIR[15:11]==`BNZ && ~MRZF)
        || (MRIR[15:11]==`BN  &&  MRNF)
        || (MRIR[15:11]==`BNN && ~MRNF)
        || (MRIR[15:11]==`BC  &&  MRCF)
        || (MRIR[15:11]==`BNC && ~MRCF)
        || (MRIR[15:11]==`BB  && ~MRNF)
        || (MRIR[15:11]==`BS  &&  MRNF)
        || (MRIR[15:11]==`BE  &&  MRZF))
        begin
          PC   <= MRRC[7:0];
          PCSt <= 1'b0;
        end
        else begin
          if((Inst==`LOAD)&(~PCSt)) begin
            PC   <= PC;
            PCSt <= 1'b1;
          end
          else begin
            if(BrSt==2'b00)
              PC <= PC + 1;
            else
              PC <= PC;
            PCSt <= 1'b0;
          end
        end
      end
      else begin
        IDIR <= IDIR;
        PC   <= PC;
        PCSt <= PCSt;
        BrSt <= BrSt;
      end
    end
  end
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) begin
      EXIR  <= 0;
      EXRA  <= 0;
      EXRB  <= 0;
      EXSD  <= 0;
      EXCF  <= 1'b0;
    end
    else begin
      if(state==`SExec) begin

        EXIR  <= IDIR;
        

        case(IDIR[15:14])
          2'b00:  begin
                    case(IDIR[13:11])
                      3'b100:   EXOP <= `ALU_CMP;
                      3'b110:   EXOP <= `ALU_LOAD;
                      default:  EXOP <= `ALU_ADDC;
                    endcase
                  end
          2'b01:  begin
                    EXOP <= `ALU_ADDC;
                  end
          2'b10:  begin
                    if(IDIR[13:11]==3'b000 || IDIR[13:11]==3'b001)
                      EXOP <= `ALU_ADDC;
                    else if(IDIR[13:11]==3'b011 || IDIR[13:11]==3'b100)
                      EXOP <= `ALU_SUBB;
                    else
                      EXOP <= IDIR[14:11];
                  end
          2'b11:  begin
                    if(IDIR[13:11]==3'b000)
                      EXOP <= `ALU_LOAD;
                    else
                      EXOP <= IDIR[14:11];
                  end
        endcase
        

        if(IDIR[15:11]==`SUBB||IDIR[15:11]==`ADDC)
          EXCF <= MRCF;
        else
          EXCF <= 0;
        

        if(IDIR[15:11]==`STORE)
          if      (HazardEX &(`IDR1N==`EXR1N)) EXSD <= ALUOUT;
          else if (HazardMR &(`IDR1N==`MRR1N)) EXSD <= MRRC;
          else if (HazardMRL&(`IDR1N==`MRR1N)) EXSD <= DataIn;
          else if (HazardWBX&(`IDR1N==`WBR1N)) EXSD <= WBRC;
          else                                 EXSD <= `EXR1;
        else
          EXSD <= 0;
        

        case(IDIR[15:11])
          `LOAD:  begin
                    if      (HazardEX &(`IDR2N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR2N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR2N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR2N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR2;
                    EXRB <= `EXVAL3;
                  end
          `STORE: begin
                    if      (HazardEX &(`IDR2N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR2N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR2N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR2N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR2;
                    EXRB <= `EXVAL3;
                  end
          `BE:    begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `JUMP:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `JMPR:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BZ:    begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BNZ:   begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BN:    begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BNN:   begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BC:    begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BNC:   begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BB:   begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BS:    begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `ADDI:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `SUBI:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `LDIL:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `LDIH:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3,8'b0};
                  end
          default:begin
                    if      (HazardEX &(`IDR2N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR2N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR2N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR2N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR2;
                    if      (HazardEX &(`IDR3N==`EXR1N)) EXRB <= ALUOUT;
                    else if (HazardMR &(`IDR3N==`MRR1N)) EXRB <= MRRC;
                    else if (HazardMRL&(`IDR3N==`MRR1N)) EXRB <= DataIn;
                    else if (HazardWBX&(`IDR3N==`WBR1N)) EXRB <= WBRC;
                    else                                 EXRB <= `EXR3;
                  end
        endcase
      end
      else begin
        EXIR  <= EXIR;
        EXRA  <= EXRA;
        EXRB  <= EXRB;
        EXSD  <= EXSD;
        EXCF  <= EXCF;
      end
    end
  end
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) begin
      MRIR  <= 0;
      MRRC  <= 0;
      MRCF  <= 1'b0;
      MRZF  <= 1'b0;
      MRNF  <= 1'b0;
      MRDW  <= 1'b0;
      MRSD  <= 0;
    end
    else begin
      if(state==`SExec) begin

        MRIR  <= EXIR;
        

        MRRC  <= ALUOUT;
        

        MRCF  <= ALUOCF;
        MRZF  <= ALUOZF;
        MRNF  <= ALUONF;
        

        MRDW  <= (EXIR[15:11]==`STORE);
        MRSD  <= EXSD;
      end
      else begin
        MRIR  <= MRIR;
        MRRC  <= MRRC;
        MRCF  <= MRCF;
        MRZF  <= MRZF;
        MRNF  <= MRNF;
        MRDW  <= MRDW;
        MRSD  <= MRSD;
      end
    end
  end
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) begin
      WBIR  <= 0;
      WBRC  <= 0;
    end
    else begin
      if(state==`SExec) begin

        WBIR  <= MRIR;
        

        if(MRIR[15:11]==`LOAD) WBRC <= DataIn;
        else                   WBRC <= MRRC;
      end
      else begin
        WBIR  <= 0;
        WBRC  <= 0;
      end
    end
  end
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) begin
      GR[0] <= 0;
      GR[1] <= 0;
      GR[2] <= 0;
      GR[3] <= 0;
      GR[4] <= 0;
      GR[5] <= 0;
      GR[6] <= 0;
      GR[7] <= 0;
    end
    else begin
      if((state==`SExec) && ((WBIR[15:11]==`LOAD)|WBIR[15]))
      begin

        GR[0] <= (`WBR1N==3'h0) ? (WBRC) : (GR[0]);
        GR[1] <= (`WBR1N==3'h1) ? (WBRC) : (GR[1]);
        GR[2] <= (`WBR1N==3'h2) ? (WBRC) : (GR[2]);
        GR[3] <= (`WBR1N==3'h3) ? (WBRC) : (GR[3]);
        GR[4] <= (`WBR1N==3'h4) ? (WBRC) : (GR[4]);
        GR[5] <= (`WBR1N==3'h5) ? (WBRC) : (GR[5]);
        GR[6] <= (`WBR1N==3'h6) ? (WBRC) : (GR[6]);
        GR[7] <= (`WBR1N==3'h7) ? (WBRC) : (GR[7]);
      end
      else begin
        GR[0] <= GR[0];
        GR[1] <= GR[1];
        GR[2] <= GR[2];
        GR[3] <= GR[3];
        GR[4] <= GR[4];
        GR[5] <= GR[5];
        GR[6] <= GR[6];
        GR[7] <= GR[7];
      end
    end
  end
  
endmodule
module DCPU(
  input  wire       CLK,
  input  wire       RST,
  input  wire       EN,
  input  wire       Start,
  output wire[7:0]  InstMemAddr,
  input  wire[15:0] Inst,
  output wire[7:0]  DataMemAddr,
  input  wire[15:0] DataIn,
  output wire       DataMemWE,
  output wire[15:0] DataOut
);

  

  `define SIdle 1'b0
  `define SExec 1'b1
  


  `define NOP   5'b00000
  `define HALT  5'b00001

  `define LOAD  5'b00010
  `define STORE 5'b00011

  `define CMP   5'b00100

  `define BE    5'b00101
  `define JUMP  5'b00110
  `define JMPR  5'b00111
  `define BZ    5'b01000
  `define BNZ   5'b01001
  `define BN    5'b01010
  `define BNN   5'b01011
  `define BC    5'b01100
  `define BNC   5'b01101
  `define BB    5'b01110
  `define BS    5'b01111

  `define ADD   5'b10000
  `define ADDI  5'b10001
  `define ADDC  5'b10010
  `define SUB   5'b10011
  `define SUBI  5'b10100
  `define SUBB  5'b10101
  `define INC   5'b10110

  `define LDIL  5'b10111
  `define LDIH  5'b11000

  `define XOR   5'b11001
  `define AND   5'b11010
  `define OR    5'b11011

  `define SLL   5'b11100
  `define SLA   5'b11101
  `define SRL   5'b11110
  `define SRA   5'b11111
  

  `define ALU_CMP   5'b0000
  `define ALU_ADDC  5'b0010
  `define ALU_SUBB  5'b0101
  `define ALU_INC   5'b0110
  `define ALU_LOAD  5'b0111
  `define ALU_XOR   5'b1001
  `define ALU_AND   5'b1010
  `define ALU_OR    5'b1011
  `define ALU_SLL   5'b1100
  `define ALU_SLA   5'b1101
  `define ALU_SRL   5'b1110
  `define ALU_SRA   5'b1111
  
  

  `define EXR1      GR[IDIR[10:8]]
  `define EXR2      GR[IDIR[6:4]]
  `define EXR3      GR[IDIR[2:0]]
  `define EXVAL2    IDIR[7:4]
  `define EXVAL3    IDIR[3:0]
  `define IDR1N     IDIR[10:8]
  `define EXR1N     EXIR[10:8]
  `define MRR1N     MRIR[10:8]
  `define WBR1N     WBIR[10:8]
  `define IDR2N     IDIR[6:4]
  `define IDR3N     IDIR[2:0]
  
  

  reg        state;
  reg        next_state;
  

  reg [7:0]  PC;
  reg [15:0] GR[0:7];
  

  reg [15:0] IDIR;
  reg [15:0] EXIR;
  reg [3:0]  EXOP;
  reg [15:0] MRIR;
  reg [15:0] WBIR;
  

  reg [15:0] EXRA;
  reg [15:0] EXRB;
  reg [15:0] EXSD;
  reg        EXCF;
  reg [15:0] MRRC;
  reg        MRCF;
  reg        MRZF;
  reg        MRNF;
  reg        MRDW;
  reg [15:0] MRSD;
  reg [15:0] WBRC;
  

  reg        PCSt;
  wire       HazardEX;
  wire       HazardEXL;
  wire       HazardMR;
  wire       HazardMRL;
  wire       HazardWB;
  wire       HazardWBL;
  reg [1:0]  BrSt;
  wire       HazardCtrl;
  

  wire[15:0] ALUOUT;
  wire       ALUOCF;
  wire       ALUOZF;
  wire       ALUONF;
  ALU        ALUM(.OPC(EXOP),
                  .IN1(EXRA),
                  .IN2(EXRB),
                  .ICF(EXCF),
                  .OUT(ALUOUT),
                  .OCF(ALUOCF),
                  .OZF(ALUOZF),
                  .ONF(ALUONF)
                  );
  
  

  assign HazardEX   = EXIR[15];
  assign HazardMR   = MRIR[15];
  assign HazardMRL  = (MRIR[14:11]==4'b0010);
  assign HazardWBX  = WBIR[15]|(WBIR[14:11]==4'b0010);
  assign HazardCtrl = (Inst[15:14]==2'b01)
                    | (Inst[15:11]==5'b00101||
                       Inst[15:11]==5'b00110||
                       Inst[15:11]==5'b00111);
  
  

  assign InstMemAddr = PC;
  assign DataMemAddr = MRRC[7:0];
  assign DataMemWE   = MRDW;
  assign DataOut     = MRSD;
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) state <= `SIdle;
    else    state <= next_state;
  end
  
  always @(*) begin
    case(state)
      `SIdle:
        if(EN & Start) next_state <= `SExec;
        else           next_state <= `SIdle;
      `SExec:
        if(!EN | WBIR[15:11]==`HALT) next_state <= `SIdle;
        else                         next_state <= `SExec;
    endcase
  end
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) begin
      IDIR <= 16'b0;
      PC   <= 8'b0;
      PCSt <= 1'b0;
      BrSt <= 2'b0;
    end
    else begin
      if(state==`SExec) begin

        if(BrSt==2'b00) IDIR <= Inst;
        else            IDIR <= 16'b0;

        case(BrSt)
          2'b00: BrSt <= ((HazardCtrl)?(2'b01):(2'b00));
          2'b01: BrSt <= 2'b10;
          2'b10: BrSt <= 2'b11;
          2'b11: BrSt <= 2'b00;
        endcase

        if((MRIR[15:11]==`JUMP)
        || (MRIR[15:11]==`JMPR)
        || (MRIR[15:11]==`BZ  &&  MRZF)
        || (MRIR[15:11]==`BNZ && ~MRZF)
        || (MRIR[15:11]==`BN  &&  MRNF)
        || (MRIR[15:11]==`BNN && ~MRNF)
        || (MRIR[15:11]==`BC  &&  MRCF)
        || (MRIR[15:11]==`BNC && ~MRCF)
        || (MRIR[15:11]==`BB  && ~MRNF)
        || (MRIR[15:11]==`BS  &&  MRNF)
        || (MRIR[15:11]==`BE  &&  MRZF))
        begin
          PC   <= MRRC[7:0];
          PCSt <= 1'b0;
        end
        else begin
          if((Inst==`LOAD)&(~PCSt)) begin
            PC   <= PC;
            PCSt <= 1'b1;
          end
          else begin
            if(BrSt==2'b00)
              PC <= PC + 1;
            else
              PC <= PC;
            PCSt <= 1'b0;
          end
        end
      end
      else begin
        IDIR <= IDIR;
        PC   <= PC;
        PCSt <= PCSt;
        BrSt <= BrSt;
      end
    end
  end
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) begin
      EXIR  <= 0;
      EXRA  <= 0;
      EXRB  <= 0;
      EXSD  <= 0;
      EXCF  <= 1'b0;
    end
    else begin
      if(state==`SExec) begin

        EXIR  <= IDIR;
        

        case(IDIR[15:14])
          2'b00:  begin
                    case(IDIR[13:11])
                      3'b100:   EXOP <= `ALU_CMP;
                      3'b110:   EXOP <= `ALU_LOAD;
                      default:  EXOP <= `ALU_ADDC;
                    endcase
                  end
          2'b01:  begin
                    EXOP <= `ALU_ADDC;
                  end
          2'b10:  begin
                    if(IDIR[13:11]==3'b000 || IDIR[13:11]==3'b001)
                      EXOP <= `ALU_ADDC;
                    else if(IDIR[13:11]==3'b011 || IDIR[13:11]==3'b100)
                      EXOP <= `ALU_SUBB;
                    else
                      EXOP <= IDIR[14:11];
                  end
          2'b11:  begin
                    if(IDIR[13:11]==3'b000)
                      EXOP <= `ALU_LOAD;
                    else
                      EXOP <= IDIR[14:11];
                  end
        endcase
        

        if(IDIR[15:11]==`SUBB||IDIR[15:11]==`ADDC)
          EXCF <= MRCF;
        else
          EXCF <= 0;
        

        if(IDIR[15:11]==`STORE)
          if      (HazardEX &(`IDR1N==`EXR1N)) EXSD <= ALUOUT;
          else if (HazardMR &(`IDR1N==`MRR1N)) EXSD <= MRRC;
          else if (HazardMRL&(`IDR1N==`MRR1N)) EXSD <= DataIn;
          else if (HazardWBX&(`IDR1N==`WBR1N)) EXSD <= WBRC;
          else                                 EXSD <= `EXR1;
        else
          EXSD <= 0;
        

        case(IDIR[15:11])
          `LOAD:  begin
                    if      (HazardEX &(`IDR2N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR2N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR2N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR2N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR2;
                    EXRB <= `EXVAL3;
                  end
          `STORE: begin
                    if      (HazardEX &(`IDR2N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR2N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR2N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR2N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR2;
                    EXRB <= `EXVAL3;
                  end
          `BE:    begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `JUMP:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `JMPR:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BZ:    begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BNZ:   begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BN:    begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BNN:   begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BC:    begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BNC:   begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BB:   begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `BS:    begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `ADDI:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `SUBI:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `LDIL:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3};
                  end
          `LDIH:  begin
                    if      (HazardEX &(`IDR1N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR1N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR1N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR1N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR1;
                    EXRB <= {`EXVAL2,`EXVAL3,8'b0};
                  end
          default:begin
                    if      (HazardEX &(`IDR2N==`EXR1N)) EXRA <= ALUOUT;
                    else if (HazardMR &(`IDR2N==`MRR1N)) EXRA <= MRRC;
                    else if (HazardMRL&(`IDR2N==`MRR1N)) EXRA <= DataIn;
                    else if (HazardWBX&(`IDR2N==`WBR1N)) EXRA <= WBRC;
                    else                                 EXRA <= `EXR2;
                    if      (HazardEX &(`IDR3N==`EXR1N)) EXRB <= ALUOUT;
                    else if (HazardMR &(`IDR3N==`MRR1N)) EXRB <= MRRC;
                    else if (HazardMRL&(`IDR3N==`MRR1N)) EXRB <= DataIn;
                    else if (HazardWBX&(`IDR3N==`WBR1N)) EXRB <= WBRC;
                    else                                 EXRB <= `EXR3;
                  end
        endcase
      end
      else begin
        EXIR  <= EXIR;
        EXRA  <= EXRA;
        EXRB  <= EXRB;
        EXSD  <= EXSD;
        EXCF  <= EXCF;
      end
    end
  end
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) begin
      MRIR  <= 0;
      MRRC  <= 0;
      MRCF  <= 1'b0;
      MRZF  <= 1'b0;
      MRNF  <= 1'b0;
      MRDW  <= 1'b0;
      MRSD  <= 0;
    end
    else begin
      if(state==`SExec) begin

        MRIR  <= EXIR;
        

        MRRC  <= ALUOUT;
        

        MRCF  <= ALUOCF;
        MRZF  <= ALUOZF;
        MRNF  <= ALUONF;
        

        MRDW  <= (EXIR[15:11]==`STORE);
        MRSD  <= EXSD;
      end
      else begin
        MRIR  <= MRIR;
        MRRC  <= MRRC;
        MRCF  <= MRCF;
        MRZF  <= MRZF;
        MRNF  <= MRNF;
        MRDW  <= MRDW;
        MRSD  <= MRSD;
      end
    end
  end
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) begin
      WBIR  <= 0;
      WBRC  <= 0;
    end
    else begin
      if(state==`SExec) begin

        WBIR  <= MRIR;
        

        if(MRIR[15:11]==`LOAD) WBRC <= DataIn;
        else                   WBRC <= MRRC;
      end
      else begin
        WBIR  <= 0;
        WBRC  <= 0;
      end
    end
  end
  
  

  always @(posedge CLK, posedge RST) begin
    if(RST) begin
      GR[0] <= 0;
      GR[1] <= 0;
      GR[2] <= 0;
      GR[3] <= 0;
      GR[4] <= 0;
      GR[5] <= 0;
      GR[6] <= 0;
      GR[7] <= 0;
    end
    else begin
      if((state==`SExec) && ((WBIR[15:11]==`LOAD)|WBIR[15]))
      begin

        GR[0] <= (`WBR1N==3'h0) ? (WBRC) : (GR[0]);
        GR[1] <= (`WBR1N==3'h1) ? (WBRC) : (GR[1]);
        GR[2] <= (`WBR1N==3'h2) ? (WBRC) : (GR[2]);
        GR[3] <= (`WBR1N==3'h3) ? (WBRC) : (GR[3]);
        GR[4] <= (`WBR1N==3'h4) ? (WBRC) : (GR[4]);
        GR[5] <= (`WBR1N==3'h5) ? (WBRC) : (GR[5]);
        GR[6] <= (`WBR1N==3'h6) ? (WBRC) : (GR[6]);
        GR[7] <= (`WBR1N==3'h7) ? (WBRC) : (GR[7]);
      end
      else begin
        GR[0] <= GR[0];
        GR[1] <= GR[1];
        GR[2] <= GR[2];
        GR[3] <= GR[3];
        GR[4] <= GR[4];
        GR[5] <= GR[5];
        GR[6] <= GR[6];
        GR[7] <= GR[7];
      end
    end
  end
  
endmodule