data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v
1: b'%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:757: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h2a\' generates 6 bits.\n                                                                              : ... In instance pipeline_riscv.ALU\n    case (alu_code)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:526: Operator EQ expects 6 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                              : ... In instance pipeline_riscv.CTRL\n    if (rd[1]!=0 && ((J_type[1] && funct[1]==7\'h08) || S_type[1]==6\'h2B)) begin\n                                                                ^~\n%Error: Exiting due to 2 warning(s)\n'
module id_exe_reg (
  input               clk,
  input               nrst,
  input               en,
  input               flush,
  input       [31:0]  cur_pc0,
  input       [31:0]  next_pc0,
  input       [31:0]  bra_off0,
  input       [31:0]  opA0,
  input       [31:0]  opB0,
  input       [31:0]  mem_data0,
  input       [4:0]   reg_addr0,
  output reg  [31:0]  cur_pc,
  output reg  [31:0]  next_pc,
  output reg  [31:0]  bra_off,
  output reg  [31:0]  opA,
  output reg  [31:0]  opB,
  output reg  [31:0]  mem_data,
  output reg  [4:0]   reg_addr
  );
  
  always@(posedge clk) begin
    if (!nrst | flush | !en) begin
      cur_pc   <= 0;
      next_pc  <= 0;
      bra_off  <= 0;
      opA      <= 0;
      opB      <= 0;
      mem_data <= 0;
      reg_addr <= 0;
    end else begin
      cur_pc   <= cur_pc0;
      next_pc  <= next_pc0;
      bra_off  <= bra_off0;
      opA      <= opA0;
      opB      <= opB0;
      mem_data <= mem_data0;
      reg_addr <= reg_addr0;
    end
  end
  
endmodule
module id_exe_reg (
  input               clk,
  input               nrst,
  input               en,
  input               flush,
  input       [31:0]  cur_pc0,
  input       [31:0]  next_pc0,
  input       [31:0]  bra_off0,
  input       [31:0]  opA0,
  input       [31:0]  opB0,
  input       [31:0]  mem_data0,
  input       [4:0]   reg_addr0,
  output reg  [31:0]  cur_pc,
  output reg  [31:0]  next_pc,
  output reg  [31:0]  bra_off,
  output reg  [31:0]  opA,
  output reg  [31:0]  opB,
  output reg  [31:0]  mem_data,
  output reg  [4:0]   reg_addr
  );

  
  always@(posedge clk) begin
    if (!nrst | flush | !en) begin
      cur_pc   <= 0;
      next_pc  <= 0;
      bra_off  <= 0;
      opA      <= 0;
      opB      <= 0;
      mem_data <= 0;
      reg_addr <= 0;
    end else begin
      cur_pc   <= cur_pc0;
      next_pc  <= next_pc0;
      bra_off  <= bra_off0;
      opA      <= opA0;
      opB      <= opB0;
      mem_data <= mem_data0;
      reg_addr <= reg_addr0;
    end
  end
  
endmodule