data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/iq_to_float.v
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/iq_to_float.v:36: Cannot find file containing module: \'binary_encoder\'\n   binary_encoder #(.SIZE(16))\n   ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200,data/full_repos/permissive/214858095/binary_encoder\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200,data/full_repos/permissive/214858095/binary_encoder.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200,data/full_repos/permissive/214858095/binary_encoder.sv\n             binary_encoder\n             binary_encoder.v\n             binary_encoder.sv\n             obj_dir/binary_encoder\n             obj_dir/binary_encoder.v\n             obj_dir/binary_encoder.sv\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/iq_to_float.v:49: Operator ADD expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'binary_out\' generates 4 bits.\n                                                                                                                                 : ... In instance iq_to_float\n   assign exponent = (in == 16\'b0)?(8\'b0):(binary_out +\'d127);\n                                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module iq_to_float

  #(parameter BITS_IN =16,
    parameter BITS_OUT = 32
    )
   (
    input [15:0] in,
    output [31:0] out
    );




   wire [15:0] unsigned_mag;
   wire [15:0] complement;


   wire [15:0] lead;
   wire [15:0] reversed_mag;


   wire [3:0] binary_out;

   wire [22:0] fraction;
   wire [7:0] exponent;

   wire [15:0] binary_in;

   binary_encoder #(.SIZE(16))
   encoding (.in(binary_in),.out(binary_out));


   assign unsigned_mag = (in[15] == 1)?((~in[15:0])+1'b1):in[15:0];


   assign complement = ((~reversed_mag[BITS_IN-1:0])+1'b1);
   assign lead = complement & reversed_mag;


   wire [15:0] pre_frac = unsigned_mag << ((15 - binary_out));
   assign fraction = {pre_frac[14:0],8'h0};
   assign exponent = (in == 16'b0)?(8'b0):(binary_out +'d127);


   assign out = {in[15], exponent, fraction};


   genvar r;

   generate
      for (r = 0; r < 16; r = r+1) begin:bit_reverse
	assign reversed_mag[r] = unsigned_mag[BITS_IN-r-1];
      end
   endgenerate


   genvar i;
   generate
     for (i= 0; i < 16; i = i+1) begin: i_rev
       assign binary_in[i] = lead[BITS_IN-i-1];
     end
   endgenerate
endmodule
module iq_to_float

  #(parameter BITS_IN =16,
    parameter BITS_OUT = 32
    )
   (
    input [15:0] in,
    output [31:0] out
    );





   wire [15:0] unsigned_mag;
   wire [15:0] complement;


   wire [15:0] lead;
   wire [15:0] reversed_mag;


   wire [3:0] binary_out;

   wire [22:0] fraction;
   wire [7:0] exponent;

   wire [15:0] binary_in;

   binary_encoder #(.SIZE(16))
   encoding (.in(binary_in),.out(binary_out));


   assign unsigned_mag = (in[15] == 1)?((~in[15:0])+1'b1):in[15:0];


   assign complement = ((~reversed_mag[BITS_IN-1:0])+1'b1);
   assign lead = complement & reversed_mag;


   wire [15:0] pre_frac = unsigned_mag << ((15 - binary_out));
   assign fraction = {pre_frac[14:0],8'h0};
   assign exponent = (in == 16'b0)?(8'b0):(binary_out +'d127);


   assign out = {in[15], exponent, fraction};


   genvar r;

   generate
      for (r = 0; r < 16; r = r+1) begin:bit_reverse
	assign reversed_mag[r] = unsigned_mag[BITS_IN-r-1];
      end
   endgenerate


   genvar i;
   generate
     for (i= 0; i < 16; i = i+1) begin: i_rev
       assign binary_in[i] = lead[BITS_IN-i-1];
     end
   endgenerate
endmodule