data/full_repos/permissive/114811571/test/samples/mips-cpu/rc_adder.v
 line:480: before: "("
1: b'%Error: data/full_repos/permissive/114811571/test/samples/mips-cpu/rc_adder.v:5: Cannot find include file: full_adder.v\n`include "full_adder.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114811571/test/samples/mips-cpu,data/full_repos/permissive/114811571/full_adder.v\n             data/full_repos/permissive/114811571/test/samples/mips-cpu,data/full_repos/permissive/114811571/full_adder.v.v\n             data/full_repos/permissive/114811571/test/samples/mips-cpu,data/full_repos/permissive/114811571/full_adder.v.sv\n             full_adder.v\n             full_adder.v.v\n             full_adder.v.sv\n             obj_dir/full_adder.v\n             obj_dir/full_adder.v.v\n             obj_dir/full_adder.v.sv\n%Error: data/full_repos/permissive/114811571/test/samples/mips-cpu/rc_adder.v:6: Cannot find include file: half_adder.v\n`include "half_adder.v" \n         ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module rc_adder(
		input wire	[N-1:0] a,
		input wire	[N-1:0] b,
		output wire [N-1:0] s,
		output wire			c);

	parameter N = 32;

	wire [N-1:0] _c;

	assign c = _c[N-1];

	half_adder add0(.a(a[0]), .b(b[0]), .s(s[0]),
					.c(_c[0]));

	genvar i;
	generate
		for (i = 1; i < N; i = i + 1) begin : gen_adder
			full_adder addN(.a(a[i]), .b(b[i]), .s(s[i]),
							.c_in(_c[i - 1]), .c(_c[i]));
		end
	endgenerate

endmodule
module rc_adder(
		input wire	[N-1:0] a,
		input wire	[N-1:0] b,
		output wire [N-1:0] s,
		output wire			c);


	parameter N = 32;

	wire [N-1:0] _c;

	assign c = _c[N-1];

	half_adder add0(.a(a[0]), .b(b[0]), .s(s[0]),
					.c(_c[0]));

	genvar i;
	generate
		for (i = 1; i < N; i = i + 1) begin : gen_adder
			full_adder addN(.a(a[i]), .b(b[i]), .s(s[i]),
							.c_in(_c[i - 1]), .c(_c[i]));
		end
	endgenerate

endmodule