data/full_repos/permissive/166661632/p8/srccode/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/166661632/p8/srccode/tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n   #600 reset=0;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/166661632/p8/srccode/tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n always #20 clk=~clk;\n        ^\n%Error: data/full_repos/permissive/166661632/p8/srccode/tb.v:52: Cannot find file containing module: \'mips\'\n mips uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/166661632/p8/srccode,data/full_repos/permissive/166661632/mips\n             data/full_repos/permissive/166661632/p8/srccode,data/full_repos/permissive/166661632/mips.v\n             data/full_repos/permissive/166661632/p8/srccode,data/full_repos/permissive/166661632/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;


	reg clk;
	reg reset;
	reg rx;
	reg [7:0] dip_switch0;
	reg [7:0] dip_switch1;
	reg [7:0] dip_switch2;
	reg [7:0] dip_switch3;
	reg [7:0] dip_switch4;
	reg [7:0] dip_switch5;
	reg [7:0] dip_switch6;
	reg [7:0] dip_switch7;
	reg [7:0] user_key;


	wire tx;
	wire [31:0] led_light;
	wire [7:0] digital_tube0;
	wire [7:0] digital_tube1;
	wire [7:0] digital_tube2;
	wire [3:0] sel0;
	wire [3:0] sel1;
	wire sel2;


	mips uut (
		.clk_in(clk), 
		.reset(reset), 
		.rx(tx), 
		.tx(tx), 
		.dip_switch0(dip_switch0), 
		.dip_switch1(dip_switch1), 
		.dip_switch2(dip_switch2), 
		.dip_switch3(dip_switch3), 
		.dip_switch4(dip_switch4), 
		.dip_switch5(dip_switch5), 
		.dip_switch6(dip_switch6), 
		.dip_switch7(dip_switch7), 
		.user_key(user_key), 
		.led_light(led_light), 
		.digital_tube0(digital_tube0), 
		.digital_tube1(digital_tube1), 
		.digital_tube2(digital_tube2), 
		.sel0(sel0), 
		.sel1(sel1), 
		.sel2(sel2)
	);

	initial begin

		clk = 0;
		reset = 1;
		rx = 0;
		dip_switch0 = 8'hff;
		dip_switch1 = 8'hff;
		dip_switch2 = 8'hff;
		dip_switch3 = 8'hff;
		dip_switch4 = 8'hff;
		dip_switch5 = 8'hff;
		dip_switch6 = 8'hff;
		dip_switch7 = 8'hff;
		user_key = 0;


			#600 reset=0;
		dip_switch0 = ~(8'h04);
		
		
			
	end
	
	always #20 clk=~clk;
      
endmodule
module tb;



	reg clk;
	reg reset;
	reg rx;
	reg [7:0] dip_switch0;
	reg [7:0] dip_switch1;
	reg [7:0] dip_switch2;
	reg [7:0] dip_switch3;
	reg [7:0] dip_switch4;
	reg [7:0] dip_switch5;
	reg [7:0] dip_switch6;
	reg [7:0] dip_switch7;
	reg [7:0] user_key;


	wire tx;
	wire [31:0] led_light;
	wire [7:0] digital_tube0;
	wire [7:0] digital_tube1;
	wire [7:0] digital_tube2;
	wire [3:0] sel0;
	wire [3:0] sel1;
	wire sel2;


	mips uut (
		.clk_in(clk), 
		.reset(reset), 
		.rx(tx), 
		.tx(tx), 
		.dip_switch0(dip_switch0), 
		.dip_switch1(dip_switch1), 
		.dip_switch2(dip_switch2), 
		.dip_switch3(dip_switch3), 
		.dip_switch4(dip_switch4), 
		.dip_switch5(dip_switch5), 
		.dip_switch6(dip_switch6), 
		.dip_switch7(dip_switch7), 
		.user_key(user_key), 
		.led_light(led_light), 
		.digital_tube0(digital_tube0), 
		.digital_tube1(digital_tube1), 
		.digital_tube2(digital_tube2), 
		.sel0(sel0), 
		.sel1(sel1), 
		.sel2(sel2)
	);

	initial begin

		clk = 0;
		reset = 1;
		rx = 0;
		dip_switch0 = 8'hff;
		dip_switch1 = 8'hff;
		dip_switch2 = 8'hff;
		dip_switch3 = 8'hff;
		dip_switch4 = 8'hff;
		dip_switch5 = 8'hff;
		dip_switch6 = 8'hff;
		dip_switch7 = 8'hff;
		user_key = 0;


			#600 reset=0;
		dip_switch0 = ~(8'h04);
		
		
			
	end
	
	always #20 clk=~clk;
      
endmodule