data/full_repos/permissive/159479522/tb_select_model.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/159479522/tb_select_model.v:38: Unsupported: Ignoring delay on this delayed statement.\n   #(5) module_select<=~module_select;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/159479522/tb_select_model.v:27: Cannot find file containing module: \'Select_module\'\n  Select_module DUT  (reset,power_led,start_pause,module_select,if_finish,model_now);\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/Select_module\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/Select_module.v\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/Select_module.sv\n             Select_module\n             Select_module.v\n             Select_module.sv\n             obj_dir/Select_module\n             obj_dir/Select_module.v\n             obj_dir/Select_module.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_select_model();
reg  reset,power_led,start_pause,module_select,if_finish;
   wire  [2:0]model_now;
   
  Select_module DUT  (reset,power_led,start_pause,module_select,if_finish,model_now);
  
   initial   begin  
   reset<=1;
   power_led<=1;
   start_pause<=0;
   module_select<=0;
   if_finish<=0;
   end
   
   always   begin
   #(5) module_select<=~module_select;
   end

endmodule
module tb_select_model();

reg  reset,power_led,start_pause,module_select,if_finish;
   wire  [2:0]model_now;
   
  Select_module DUT  (reset,power_led,start_pause,module_select,if_finish,model_now);
  
   initial   begin  
   reset<=1;
   power_led<=1;
   start_pause<=0;
   module_select<=0;
   if_finish<=0;
   end
   
   always   begin
   #(5) module_select<=~module_select;
   end

endmodule