data/full_repos/permissive/108216748/system/sha256.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha256.v:205: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'sha256_block\'\nmodule sha256_block (\n       ^~~~~~~~~~~~\n                                                                           : ... Top module \'sha256_H_0\'\nmodule sha256_H_0(\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:90: Cannot find file containing module: \'Ch\'\nCh #(.WORDSIZE(32)) Ch (\n^~\n        ... Looked in:\n             data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch\n             data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.v\n             data/full_repos/permissive/108216748/system,data/full_repos/permissive/108216748/Ch.sv\n             Ch\n             Ch.v\n             Ch.sv\n             obj_dir/Ch\n             obj_dir/Ch.v\n             obj_dir/Ch.sv\n%Error: data/full_repos/permissive/108216748/system/sha256.v:94: Cannot find file containing module: \'Maj\'\nMaj #(.WORDSIZE(32)) Maj (\n^~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:106: Cannot find file containing module: \'sha2_round\'\nsha2_round #(.WORDSIZE(32)) sha256_round_inner (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/108216748/system/sha256.v:65: Cannot find file containing module: \'W_machine\'\nW_machine #(.WORDSIZE(32)) W_machine (\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module sha256_block (
    input clk, rst,
    input [255:0] H_in,
    input [511:0] M_in,
    input input_valid,
    input en,
    output [255:0] H_out,
    output output_valid
    );

reg [6:0] round;
wire [31:0] a_in = H_in[255:224], b_in = H_in[223:192], c_in = H_in[191:160], d_in = H_in[159:128];
wire [31:0] e_in = H_in[127:96], f_in = H_in[95:64], g_in = H_in[63:32], h_in = H_in[31:0];
reg [31:0] a_q, b_q, c_q, d_q, e_q, f_q, g_q, h_q;
wire [31:0] a_d, b_d, c_d, d_d, e_d, f_d, g_d, h_d;
wire [31:0] W_tm2, W_tm15, s1_Wtm2, s0_Wtm15, Wj, Kj;
assign H_out = {
    a_in + a_q, b_in + b_q, c_in + c_q, d_in + d_q, e_in + e_q, f_in + f_q, g_in + g_q, h_in + h_q
};
assign output_valid = round == 64;

always @(posedge clk)
begin
    if (en == 0)
    begin
        a_q <= a_q; b_q <= b_q; c_q <= c_q; d_q <= d_q;
        e_q <= e_q; f_q <= f_q; g_q <= g_q; h_q <= h_q;
        round <= round;
    end
    else if (input_valid) begin
        a_q <= a_in; b_q <= b_in; c_q <= c_in; d_q <= d_in;
        e_q <= e_in; f_q <= f_in; g_q <= g_in; h_q <= h_in;
        round <= 0;
    end 
    else if (round == 64)
    begin
        a_q <= a_q; b_q <= b_q; c_q <= c_q; d_q <= d_q;
        e_q <= e_q; f_q <= f_q; g_q <= g_q; h_q <= h_q;
        round <= round;
    end
    else begin
        a_q <= a_d; b_q <= b_d; c_q <= c_d; d_q <= d_d;
        e_q <= e_d; f_q <= f_d; g_q <= g_d; h_q <= h_d;
        round <= round + 1;
    end
end

sha256_round sha256_round (
    .Kj(Kj), .Wj(Wj),
    .a_in(a_q), .b_in(b_q), .c_in(c_q), .d_in(d_q),
    .e_in(e_q), .f_in(f_q), .g_in(g_q), .h_in(h_q),
    .a_out(a_d), .b_out(b_d), .c_out(c_d), .d_out(d_d),
    .e_out(e_d), .f_out(f_d), .g_out(g_d), .h_out(h_d)
);

sha256_s0 sha256_s0 (.x(W_tm15), .s0(s0_Wtm15));
sha256_s1 sha256_s1 (.x(W_tm2), .s1(s1_Wtm2));

W_machine #(.WORDSIZE(32)) W_machine (
    .clk(clk),
    .en(en),
    .M(M_in), .M_valid(input_valid),
    .W_tm2(W_tm2), .W_tm15(W_tm15),
    .s1_Wtm2(s1_Wtm2), .s0_Wtm15(s0_Wtm15),
    .W(Wj)
);

sha256_K_machine sha256_K_machine (
    .clk(clk), .rst(input_valid), .en(en), .K(Kj)
);

endmodule
module sha256_block (
    input clk, rst,
    input [255:0] H_in,
    input [511:0] M_in,
    input input_valid,
    input en,
    output [255:0] H_out,
    output output_valid
    );


reg [6:0] round;
wire [31:0] a_in = H_in[255:224], b_in = H_in[223:192], c_in = H_in[191:160], d_in = H_in[159:128];
wire [31:0] e_in = H_in[127:96], f_in = H_in[95:64], g_in = H_in[63:32], h_in = H_in[31:0];
reg [31:0] a_q, b_q, c_q, d_q, e_q, f_q, g_q, h_q;
wire [31:0] a_d, b_d, c_d, d_d, e_d, f_d, g_d, h_d;
wire [31:0] W_tm2, W_tm15, s1_Wtm2, s0_Wtm15, Wj, Kj;
assign H_out = {
    a_in + a_q, b_in + b_q, c_in + c_q, d_in + d_q, e_in + e_q, f_in + f_q, g_in + g_q, h_in + h_q
};
assign output_valid = round == 64;

always @(posedge clk)
begin
    if (en == 0)
    begin
        a_q <= a_q; b_q <= b_q; c_q <= c_q; d_q <= d_q;
        e_q <= e_q; f_q <= f_q; g_q <= g_q; h_q <= h_q;
        round <= round;
    end
    else if (input_valid) begin
        a_q <= a_in; b_q <= b_in; c_q <= c_in; d_q <= d_in;
        e_q <= e_in; f_q <= f_in; g_q <= g_in; h_q <= h_in;
        round <= 0;
    end 
    else if (round == 64)
    begin
        a_q <= a_q; b_q <= b_q; c_q <= c_q; d_q <= d_q;
        e_q <= e_q; f_q <= f_q; g_q <= g_q; h_q <= h_q;
        round <= round;
    end
    else begin
        a_q <= a_d; b_q <= b_d; c_q <= c_d; d_q <= d_d;
        e_q <= e_d; f_q <= f_d; g_q <= g_d; h_q <= h_d;
        round <= round + 1;
    end
end

sha256_round sha256_round (
    .Kj(Kj), .Wj(Wj),
    .a_in(a_q), .b_in(b_q), .c_in(c_q), .d_in(d_q),
    .e_in(e_q), .f_in(f_q), .g_in(g_q), .h_in(h_q),
    .a_out(a_d), .b_out(b_d), .c_out(c_d), .d_out(d_d),
    .e_out(e_d), .f_out(f_d), .g_out(g_d), .h_out(h_d)
);

sha256_s0 sha256_s0 (.x(W_tm15), .s0(s0_Wtm15));
sha256_s1 sha256_s1 (.x(W_tm2), .s1(s1_Wtm2));

W_machine #(.WORDSIZE(32)) W_machine (
    .clk(clk),
    .en(en),
    .M(M_in), .M_valid(input_valid),
    .W_tm2(W_tm2), .W_tm15(W_tm15),
    .s1_Wtm2(s1_Wtm2), .s0_Wtm15(s0_Wtm15),
    .W(Wj)
);

sha256_K_machine sha256_K_machine (
    .clk(clk), .rst(input_valid), .en(en), .K(Kj)
);

endmodule