data/full_repos/permissive/120749710/metronome.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/120749710/metronome.v:89: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'metronome\'\nmodule metronome(\n       ^~~~~~~~~\n                                                                      : ... Top module \'band\'\nmodule band(\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120749710/metronome.v:37: Operator DIV expects 32 bits on the RHS, but RHS\'s VARREF \'speed\' generates 8 bits.\n                                                                   : ... In instance metronome\n   assign blank = 60 * freq / speed / 16;\n                            ^\n%Error: Exiting due to 2 warning(s)\n'
module metronome(
		input [7:0] speed,
		input	clk,
		input	rst_n,
		input [15:0] SW,
		output reg bell,
		output reg [15:0] LED
    );
		localparam freq = 2500;
		localparam beat = 25000000 / freq;
		localparam delta = 60 * freq / 256 / 16;


		wire[31:0] blank;
	 	assign blank = 60 * freq / speed / 16;
		integer i;
		integer j;
		reg [3:0] k;
		reg sign;

		always@(posedge clk or negedge rst_n)
		begin
			if (~rst_n)
			begin
				j <= 0;
				sign <= 0;
			end
			else if(SW == 16'h0000)
				j <= j;
			else if(j >= beat)
			begin
				sign <= ~sign;
				j <= 0;
			end
			else
				j <= j+1;
		end
		always@(posedge sign or negedge rst_n)
		begin
			if (~rst_n)
			begin
				i <= 0;
				bell <= 0;
				k <= 0;
				LED <= 0;
			end
			else if(i >= blank)
			begin
				i <= 0;
				LED[k] <= 1;
				LED[k == 0 ? 15 : k-1] <= 0;
				k <= k+1;
			end
			else if(SW[k] === 0)
				i <= i+1;
			else if(i >= blank - delta)
			begin
				bell <= ~bell;
				i <= i+1;
			end
			else
				i <= i+1;
		end
endmodule
module metronome(
		input [7:0] speed,
		input	clk,
		input	rst_n,
		input [15:0] SW,
		output reg bell,
		output reg [15:0] LED
    );

		localparam freq = 2500;
		localparam beat = 25000000 / freq;
		localparam delta = 60 * freq / 256 / 16;


		wire[31:0] blank;
	 	assign blank = 60 * freq / speed / 16;
		integer i;
		integer j;
		reg [3:0] k;
		reg sign;

		always@(posedge clk or negedge rst_n)
		begin
			if (~rst_n)
			begin
				j <= 0;
				sign <= 0;
			end
			else if(SW == 16'h0000)
				j <= j;
			else if(j >= beat)
			begin
				sign <= ~sign;
				j <= 0;
			end
			else
				j <= j+1;
		end
		always@(posedge sign or negedge rst_n)
		begin
			if (~rst_n)
			begin
				i <= 0;
				bell <= 0;
				k <= 0;
				LED <= 0;
			end
			else if(i >= blank)
			begin
				i <= 0;
				LED[k] <= 1;
				LED[k == 0 ? 15 : k-1] <= 0;
				k <= k+1;
			end
			else if(SW[k] === 0)
				i <= i+1;
			else if(i >= blank - delta)
			begin
				bell <= ~bell;
				i <= i+1;
			end
			else
				i <= i+1;
		end
endmodule