data/full_repos/permissive/212394344/Reg2.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/2df89282-7814-45fd-b001-153d9ea58c5e.xml
module Reg2(Hold_Address, Next_Address,Current_Address, IA, clk, reset);

input clk,reset;
input [7:0] Current_Address, IA; 
output reg [7:0] Hold_Address, Next_Address;
wire [7:0] temp1,temp2;

assign temp1=(reset==1'b0)? 8'b00000000 :Current_Address ;                     
assign temp2=(reset==1'b0)? 8'b00000000 :IA ;                     

always @(posedge clk)
begin
	Hold_Address<=temp1;
	Next_Address<=temp2;
end

endmodule
module Reg2(Hold_Address, Next_Address,Current_Address, IA, clk, reset);


input clk,reset;
input [7:0] Current_Address, IA; 
output reg [7:0] Hold_Address, Next_Address;
wire [7:0] temp1,temp2;

assign temp1=(reset==1'b0)? 8'b00000000 :Current_Address ;                     
assign temp2=(reset==1'b0)? 8'b00000000 :IA ;                     

always @(posedge clk)
begin
	Hold_Address<=temp1;
	Next_Address<=temp2;
end

endmodule