data/full_repos/permissive/158096953/data_bus.v
data/verilator_xmls/37f4f55f-366b-41ee-aa72-903a8a1718ac.xml
module data_bus(
	m1,
	mreq,
	rd,
	wr,
	cpu_data_input,
	cpu_data_output_output,
	cpu_data_os,

	pram_data,

	dram_input,
	dram_output,

	io_input,
	io_output
	);

input m1;
input mreq;
input rd;
input wr;
output reg [7:0] cpu_data_input;
input  [7:0] cpu_data_output_output;
input  [7:0] cpu_data_os;

input  [7:0] pram_data;

output [7:0] dram_input;
input  [7:0] dram_output;

output [7:0] io_input;
input  [7:0] io_output;

wire io_input_flag;

assign io_input_flag = m1 & (~wr) & rd & mreq;
assign io_input = io_input_flag ? cpu_data_output_output : 8'h00;




wire dram_input_flag;
assign dram_input_flag = m1 & (~wr) & rd & (~mreq);
assign dram_input = dram_input_flag ? cpu_data_os : 8'h00;

always @(m1 or wr or rd or mreq or pram_data or dram_output or io_output) begin
	case({m1, wr, rd, mreq})
		4'b0100: cpu_data_input = pram_data;
		4'b1100: cpu_data_input = dram_output;
		4'b1101: cpu_data_input = io_output;
		default: cpu_data_input = 8'h00;
	endcase
end

endmodule
module data_bus(
	m1,
	mreq,
	rd,
	wr,
	cpu_data_input,
	cpu_data_output_output,
	cpu_data_os,

	pram_data,

	dram_input,
	dram_output,

	io_input,
	io_output
	);


input m1;
input mreq;
input rd;
input wr;
output reg [7:0] cpu_data_input;
input  [7:0] cpu_data_output_output;
input  [7:0] cpu_data_os;

input  [7:0] pram_data;

output [7:0] dram_input;
input  [7:0] dram_output;

output [7:0] io_input;
input  [7:0] io_output;

wire io_input_flag;

assign io_input_flag = m1 & (~wr) & rd & mreq;
assign io_input = io_input_flag ? cpu_data_output_output : 8'h00;




wire dram_input_flag;
assign dram_input_flag = m1 & (~wr) & rd & (~mreq);
assign dram_input = dram_input_flag ? cpu_data_os : 8'h00;

always @(m1 or wr or rd or mreq or pram_data or dram_output or io_output) begin
	case({m1, wr, rd, mreq})
		4'b0100: cpu_data_input = pram_data;
		4'b1100: cpu_data_input = dram_output;
		4'b1101: cpu_data_input = io_output;
		default: cpu_data_input = 8'h00;
	endcase
end

endmodule