data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono2.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono2.v:50: Signal definition not found, creating implicitly: \'cnt\'\n    assign cnt = ~|dcount;\n           ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono2.v:44: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 26 bits.\n                                                                                                            : ... In instance chrono2\n            dcount <= FDIV - 1;\n                   ^~\n%Error: Exiting due to 2 warning(s)\n'
module chrono2 #(

    parameter FREQ = 50000000
    )(
    input wire ck,
    input wire cl,
    input wire start,
    output reg [3:0] c0,
    output reg [3:0] c1,
    output reg [3:0] s0,
    output reg [3:0] s1
    );


    localparam FDIV = FREQ/100;


    reg [23:0] dcount;



    always @(posedge ck) begin
        if (start == 0 || cl == 1 || dcount == 0)
            dcount <= FDIV - 1;
        else
            dcount <= dcount - 1;
    end


    assign cnt = ~|dcount;



    always @(posedge ck) begin
        if (cl) begin

            c0 <= 0;
            c1 <= 0;
            s0 <= 0;
            s1 <= 0;
        end else if (cnt) begin

            if (c0 < 9)
                c0 <= c0 + 1;
            else begin
                c0 <= 0;
                if (c1 < 9)
                    c1 <= c1 + 1;
                else begin
                    c1 <= 0;
                    if (s0 < 9)
                        s0 <= s0 + 1;
                    else begin
                        s0 <= 0;
                        if (s1 < 5)
                            s1 = s1 + 1;
                        else
                            s1 <= 0;
                    end
                end
            end
        end
    end

endmodule
module chrono2 #(

    parameter FREQ = 50000000
    )(
    input wire ck,
    input wire cl,
    input wire start,
    output reg [3:0] c0,
    output reg [3:0] c1,
    output reg [3:0] s0,
    output reg [3:0] s1
    );



    localparam FDIV = FREQ/100;


    reg [23:0] dcount;



    always @(posedge ck) begin
        if (start == 0 || cl == 1 || dcount == 0)
            dcount <= FDIV - 1;
        else
            dcount <= dcount - 1;
    end


    assign cnt = ~|dcount;



    always @(posedge ck) begin
        if (cl) begin

            c0 <= 0;
            c1 <= 0;
            s0 <= 0;
            s1 <= 0;
        end else if (cnt) begin

            if (c0 < 9)
                c0 <= c0 + 1;
            else begin
                c0 <= 0;
                if (c1 < 9)
                    c1 <= c1 + 1;
                else begin
                    c1 <= 0;
                    if (s0 < 9)
                        s0 <= s0 + 1;
                    else begin
                        s0 <= 0;
                        if (s1 < 5)
                            s1 = s1 + 1;
                        else
                            s1 <= 0;
                    end
                end
            end
        end
    end

endmodule