data/full_repos/permissive/161029703/src/uma/PriorityEncoder/PriorityEncoder_width8.v
data/verilator_xmls/57224a27-9422-4351-b33b-4180aa02a3b8.xml
module PriorityEncoder8(enable_n, data, result, result_valid);
	input 		      enable_n;
	input  [7:0]      data;
	output [2:0]      result;
	output		      result_valid;
	
	wire r2Raw = |data[3:0];
	wire r1Raw = |data[1:0] | 
					(|data[5:4]  & ~|{data[3:2]});
	wire r0Raw = data[0]  |
					(data[2]  & ~data[1]) | 
					(data[4]  & ~data[1] & ~data[3]) |
					(data[6]  & ~data[1] & ~data[3] & ~data[5]);
	wire [2:0]   result = {enable_n, enable_n, enable_n} | ~{r2Raw, r1Raw, r0Raw};					 
	wire         result_valid = |data & ~enable_n;
endmodule
module PriorityEncoder8(enable_n, data, result, result_valid);

	input 		      enable_n;
	input  [7:0]      data;
	output [2:0]      result;
	output		      result_valid;
	
	wire r2Raw = |data[3:0];
	wire r1Raw = |data[1:0] | 
					(|data[5:4]  & ~|{data[3:2]});
	wire r0Raw = data[0]  |
					(data[2]  & ~data[1]) | 
					(data[4]  & ~data[1] & ~data[3]) |
					(data[6]  & ~data[1] & ~data[3] & ~data[5]);
	wire [2:0]   result = {enable_n, enable_n, enable_n} | ~{r2Raw, r1Raw, r0Raw};					 
	wire         result_valid = |data & ~enable_n;
endmodule