data/full_repos/permissive/125927162/UART/UART_RX_tb.v
 line:65: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk = !clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:37: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("UART_RX.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:38: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #2\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #16\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n      #16\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #16\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #16\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #16\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #16\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n      #16\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n      #16\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #16\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_RX_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n      #32\n      ^\n%Error: Exiting due to 2 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_RX_tb();
   localparam BITS = 8;

   reg clk;
   reg rst;
   reg tx;
   wire [BITS-1:0] data;
   
   reg [BITS - 1:0] test_data = 8'b01011100;
   
   UART_RX #(.BITS(BITS))
   DUT(
       .clk(clk),
       .rst(rst),
       .rx(tx),
       .data(data)
       );

   always #1 clk = !clk;
   
   initial begin
      $dumpfile("UART_RX.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      rst = 1;
      tx = 1;
      #2
	rst = 0;
      #1
	tx = 0;
      #16
	tx = test_data[7]; 
      #16
	tx = test_data[6];
      #16
	tx = test_data[5];
      #16
	tx = test_data[4];
      #16
	tx = test_data[3]; 
      #16
	tx = test_data[2];
      #16
	tx = test_data[1];
      #16
	tx = test_data[0];
      #16
	tx = 1;
      #32
      $finish;   
   end

   
endmodule
module UART_RX_tb();

   localparam BITS = 8;

   reg clk;
   reg rst;
   reg tx;
   wire [BITS-1:0] data;
   
   reg [BITS - 1:0] test_data = 8'b01011100;
   
   UART_RX #(.BITS(BITS))
   DUT(
       .clk(clk),
       .rst(rst),
       .rx(tx),
       .data(data)
       );

   always #1 clk = !clk;
   
   initial begin
      $dumpfile("UART_RX.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      rst = 1;
      tx = 1;
      #2
	rst = 0;
      #1
	tx = 0;
      #16
	tx = test_data[7]; 
      #16
	tx = test_data[6];
      #16
	tx = test_data[5];
      #16
	tx = test_data[4];
      #16
	tx = test_data[3]; 
      #16
	tx = test_data[2];
      #16
	tx = test_data[1];
      #16
	tx = test_data[0];
      #16
	tx = 1;
      #32
      $finish;   
   end

   
endmodule