data/full_repos/permissive/177233467/instruction_decode.v
Syntax Error
1: b'%Error: data/full_repos/permissive/177233467/instruction_decode.v:35: Cannot find include file: armv7_set.v\n`include "armv7_set.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/177233467,data/full_repos/permissive/177233467/armv7_set.v\n             data/full_repos/permissive/177233467,data/full_repos/permissive/177233467/armv7_set.v.v\n             data/full_repos/permissive/177233467,data/full_repos/permissive/177233467/armv7_set.v.sv\n             armv7_set.v\n             armv7_set.v.v\n             armv7_set.v.sv\n             obj_dir/armv7_set.v\n             obj_dir/armv7_set.v.v\n             obj_dir/armv7_set.v.sv\n%Error: Exiting due to 1 error(s)\n'
module instruction_decode(
    input wire clk, resetn,
    input wire [code_width - 1:0] code_mem_rd,
    input wire [31:0] pc,

    output reg [3:0] cond_code,
    output reg [7:0] opcode, 
    output wire [7:0] muxflags,
    
    output reg [reg_addr_width - 1:0] Rn, Rm, Rd, 
    output reg [2:0] Rw,
    output reg [31:0] imm32, 


    output reg [7:0] debug_id
);

parameter code_width = 32;
parameter code_words = 512;

parameter reg_width = 32;
parameter reg_addr_width = 5;

parameter data_width = 32;
parameter data_addr_width = 5;

`include "armv7_set.v"


always @(posedge clk) begin
  cond_code <= code_mem_rd[31:28];
  opcode <= code_mem_rd[27:20];


  imm32 <= immVal;
end
assign muxflags = {BLS, BS, 1'b0, DPF, MWE, WBS, IS, RFWE};


reg [3:0] cond;
reg [2:0] op_type;

reg op;
reg [4:0] op1;
reg [3:0] op2;
reg [31:0] immVal;


reg [2:0] Rw;







reg BLS, BS, DPF, MWE, WBS, IS, RFWE; 


always @(*) begin

  Rd = 4'b0;
  Rm = 4'b0;
  Rn = 4'b0;
  Rw = 3'b0;


  BLS = 1'b0;
  BS = 1'b0;
  MWE = 1'b0;
  WBS = 1'b0;
  IS = 1'b0;
  RFWE = 1'b0;
  DPF = 1'b0;
  
  immVal = 0;

  debug_id = 1;



  if (code_mem_rd[31:28] != 4'h_f) begin
    debug_id = 2;
    casez(code_mem_rd[27:25])
      3'b_00?: process_data();
      3'b_010: load_store();
      3'b_011: load_store();
      3'b_10?: compute_branch();

    endcase
  end

end





task process_data;

  begin
    op = code_mem_rd[25];
    op1 = code_mem_rd[24:20];
    op2 = code_mem_rd[7:4];
    debug_id = 3;
    if(~op) begin



      if ( (op1 & 5'h19) != 5'h10) begin


        if( (op2 & 4'h1) === 4'h0) begin






          casez(op1)
            5'b0000?: AND_reg(code_mem_rd, Rw, Rd, Rn, Rm, RFWE);
            5'b0001?: EOR_reg(code_mem_rd, Rw, Rd, Rn, Rm, RFWE);
            5'b0010?: SUB_reg(code_mem_rd, Rw, Rd, Rn, Rm, RFWE);

            5'b0100?: ADD_reg(code_mem_rd, Rw, Rd, Rn, Rm, RFWE);



            5'b10001: TST_reg(code_mem_rd, Rw, Rn, Rm);
            5'b10011: TEQ_reg(code_mem_rd, Rw, Rn, Rm);
            5'b10101: CMP_reg(code_mem_rd, Rw, Rn, Rm);
            5'b10111: CMN_reg(code_mem_rd, Rw, Rn, Rm);
            5'b1100?: ORR_reg(code_mem_rd, Rw, Rd, Rn, Rm, RFWE);



          endcase
        end
      end else begin
        casez(op1) 
          5'b10??0: begin
            if( (op2 & 4'h8) == 4'h0 ) begin

              casez({code_mem_rd[6:4], code_mem_rd[22:21]})
                5'b00101: BX_reg(code_mem_rd, Rw, Rm, BS, BLS);
              endcase
            end

          end
        endcase
      end

    end else begin

        debug_id = 4;

         if ( (op1 & 5'h19) != 5'h10) begin


            debug_id = 6;
            casez(op1)
              5'b1101?: MOV_imm(code_mem_rd, Rw, Rd, immVal, RFWE, IS);
            endcase
         end
    end 
  end
endtask

task load_store;

  begin
    debug_id = 6;
    op1 = code_mem_rd[24:20];
    casez(op1)
      5'b??0?0: STR_imm(code_mem_rd, Rw, Rn, Rm, immVal, MWE, IS);
      5'b??0?1: LDR_imm(code_mem_rd, Rw, Rd, Rn, immVal, DPF, RFWE, WBS, IS);
    endcase
  end
endtask

task compute_branch;

  begin
    debug_id = 6;
    casez(code_mem_rd[25:20])
      6'b10????: B_imm(code_mem_rd, pc, Rw, Rn, immVal, IS, BS, BLS);
      6'b11????: BL_imm(code_mem_rd, pc, Rw, immVal, Rd, RFWE, IS, BS, BLS);
    endcase
  end
endtask

endmodule
module instruction_decode(
    input wire clk, resetn,
    input wire [code_width - 1:0] code_mem_rd,
    input wire [31:0] pc,

    output reg [3:0] cond_code,
    output reg [7:0] opcode, 
    output wire [7:0] muxflags,
    
    output reg [reg_addr_width - 1:0] Rn, Rm, Rd, 
    output reg [2:0] Rw,
    output reg [31:0] imm32, 


    output reg [7:0] debug_id
);


parameter code_width = 32;
parameter code_words = 512;

parameter reg_width = 32;
parameter reg_addr_width = 5;

parameter data_width = 32;
parameter data_addr_width = 5;

`include "armv7_set.v"


always @(posedge clk) begin
  cond_code <= code_mem_rd[31:28];
  opcode <= code_mem_rd[27:20];


  imm32 <= immVal;
end
assign muxflags = {BLS, BS, 1'b0, DPF, MWE, WBS, IS, RFWE};


reg [3:0] cond;
reg [2:0] op_type;

reg op;
reg [4:0] op1;
reg [3:0] op2;
reg [31:0] immVal;


reg [2:0] Rw;







reg BLS, BS, DPF, MWE, WBS, IS, RFWE; 


always @(*) begin

  Rd = 4'b0;
  Rm = 4'b0;
  Rn = 4'b0;
  Rw = 3'b0;


  BLS = 1'b0;
  BS = 1'b0;
  MWE = 1'b0;
  WBS = 1'b0;
  IS = 1'b0;
  RFWE = 1'b0;
  DPF = 1'b0;
  
  immVal = 0;

  debug_id = 1;



  if (code_mem_rd[31:28] != 4'h_f) begin
    debug_id = 2;
    casez(code_mem_rd[27:25])
      3'b_00?: process_data();
      3'b_010: load_store();
      3'b_011: load_store();
      3'b_10?: compute_branch();

    endcase
  end

end





task process_data;

  begin
    op = code_mem_rd[25];
    op1 = code_mem_rd[24:20];
    op2 = code_mem_rd[7:4];
    debug_id = 3;
    if(~op) begin



      if ( (op1 & 5'h19) != 5'h10) begin


        if( (op2 & 4'h1) === 4'h0) begin






          casez(op1)
            5'b0000?: AND_reg(code_mem_rd, Rw, Rd, Rn, Rm, RFWE);
            5'b0001?: EOR_reg(code_mem_rd, Rw, Rd, Rn, Rm, RFWE);
            5'b0010?: SUB_reg(code_mem_rd, Rw, Rd, Rn, Rm, RFWE);

            5'b0100?: ADD_reg(code_mem_rd, Rw, Rd, Rn, Rm, RFWE);



            5'b10001: TST_reg(code_mem_rd, Rw, Rn, Rm);
            5'b10011: TEQ_reg(code_mem_rd, Rw, Rn, Rm);
            5'b10101: CMP_reg(code_mem_rd, Rw, Rn, Rm);
            5'b10111: CMN_reg(code_mem_rd, Rw, Rn, Rm);
            5'b1100?: ORR_reg(code_mem_rd, Rw, Rd, Rn, Rm, RFWE);



          endcase
        end
      end else begin
        casez(op1) 
          5'b10??0: begin
            if( (op2 & 4'h8) == 4'h0 ) begin

              casez({code_mem_rd[6:4], code_mem_rd[22:21]})
                5'b00101: BX_reg(code_mem_rd, Rw, Rm, BS, BLS);
              endcase
            end

          end
        endcase
      end

    end else begin

        debug_id = 4;

         if ( (op1 & 5'h19) != 5'h10) begin


            debug_id = 6;
            casez(op1)
              5'b1101?: MOV_imm(code_mem_rd, Rw, Rd, immVal, RFWE, IS);
            endcase
         end
    end 
  end
endtask

task load_store;

  begin
    debug_id = 6;
    op1 = code_mem_rd[24:20];
    casez(op1)
      5'b??0?0: STR_imm(code_mem_rd, Rw, Rn, Rm, immVal, MWE, IS);
      5'b??0?1: LDR_imm(code_mem_rd, Rw, Rd, Rn, immVal, DPF, RFWE, WBS, IS);
    endcase
  end
endtask

task compute_branch;

  begin
    debug_id = 6;
    casez(code_mem_rd[25:20])
      6'b10????: B_imm(code_mem_rd, pc, Rw, Rn, immVal, IS, BS, BLS);
      6'b11????: BL_imm(code_mem_rd, pc, Rw, immVal, Rd, RFWE, IS, BS, BLS);
    endcase
  end
endtask

endmodule