data/full_repos/permissive/198223683/rtl/cd/lc8951.v
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data/verilator_xmls/88f01f1b-4cc2-4592-877e-6b59788bf5c7.xml
module lc8951(
	input nRESET,
	input CLK_12M,
	input nWR, nRD,
	input RS,
	input [7:0] DIN,
	output reg [7:0] DOUT,
	
	input [7:0] MSF_M,
	input [7:0] MSF_S,
	input [7:0] MSF_F,
	input MSF_LATCH,
	
	input SECTOR_READY,
	input DMA_RUNNING,
	output reg CDC_nIRQ
);

	reg [3:0] AR;
	reg [7:0] REGS_WRITE [16];
	
	reg [11:0] DBC;
	reg [15:0] DAC;


	reg [15:0] WA;
	reg nDTBSY, nSTBSY, nDTEN, nSTEN, nVALST;
	reg [7:0] HEAD [4];
	


	reg CMDI_FLAG, DTEI_FLAG, DECI_FLAG;
	reg CMDIEN, DTEIEN, DECIEN, nCMDBRK, nDTWAI, nSTWAI, DOUTEN, SOUTEN;
	reg DTTRG;
	reg DECEN, EDCRQ, E01RQ, AUTORQ, ERAMRQ, WRRQ, QRQ, PRQ;
	reg SYIEN, SYDEN, DSCREN, COWREN, MODRQ, FORMRQ, SHDREN;
	
	reg nWR_PREV, nRD_PREV;
	reg SECTOR_READY_PREV, DMA_RUNNING_PREV, MSF_LATCH_PREV;
	

	always @(negedge CLK_12M or negedge nRESET)
	begin
		if (!nRESET)
		begin
			AR <= 4'd0;
			nWR_PREV <= 1;
			nRD_PREV <= 1;
			
			CDC_nIRQ <= 1;
			
			DBC <= 12'h000;
			DAC <= 16'h0000;

			WA <= 16'h0000;
			
			CMDI_FLAG <= 0;
			DTEI_FLAG <= 0;
			DECI_FLAG <= 0;
			nDTBSY <= 1;
			nSTBSY <= 1;
			nDTEN <= 1;
			nSTEN <= 1;
			
			HEAD[0] <= 8'h00;
			HEAD[1] <= 8'h00;
			HEAD[2] <= 8'h00;
			HEAD[3] <= 8'h00;
			
			nVALST <= 1;
			
			{CMDIEN, DTEIEN, DECIEN, nCMDBRK, nDTWAI, nSTWAI, DOUTEN, SOUTEN} <= 8'b00000000;
			DTTRG <= 0;
			{DECEN, EDCRQ, E01RQ, AUTORQ, ERAMRQ, WRRQ, QRQ, PRQ} <= 8'b00000000;
			{SYIEN, SYDEN, DSCREN, COWREN, MODRQ, FORMRQ, SHDREN} <= 7'b0000000;
			
			SECTOR_READY_PREV <= 0;
			DMA_RUNNING_PREV <= 0;
		end
		else
		begin
			SECTOR_READY_PREV <= SECTOR_READY;
			DMA_RUNNING_PREV <= DMA_RUNNING;
			MSF_LATCH_PREV <= MSF_LATCH;
			

			if (~SECTOR_READY_PREV & SECTOR_READY)
			begin
				DECI_FLAG <= 1;
				nVALST <= 0;
			end
			

			if (DMA_RUNNING_PREV & ~DMA_RUNNING)
				DTEI_FLAG <= 1;
			

			if (~MSF_LATCH_PREV & MSF_LATCH)
			begin
				HEAD[0] <= MSF_M;
				HEAD[1] <= MSF_S;
				HEAD[2] <= MSF_F;

			end
			
			CDC_nIRQ <= ~|{(CMDI_FLAG & CMDIEN), (DTEI_FLAG & DTEIEN), (DECI_FLAG & DECIEN)};
		
			nWR_PREV <= nWR;
			nRD_PREV <= nRD;
			
			if (nWR_PREV & ~nWR)
			begin

				if (~RS)
					AR <= DIN[3:0];
				else
				begin
					case(AR)
						4'd0:;
						4'd1: {CMDIEN, DTEIEN, DECIEN, nCMDBRK, nDTWAI, nSTWAI, DOUTEN, SOUTEN} <= DIN;
						
						4'd2: DBC[7:0] <= DIN;
						4'd3: DBC[11:8] <= DIN[3:0];
						
						4'd4: DAC[7:0] <= DIN;
						4'd5: DAC[15:8] <= DIN;
						4'd6: DTTRG <= 1;
						4'd7: DTEI_FLAG <= 0;
						
						4'd8: WA[7:0] <= DIN;
						4'd9: WA[15:8] <= DIN;
			
						4'd10: {DECEN, EDCRQ, E01RQ, AUTORQ, ERAMRQ, WRRQ, QRQ, PRQ} <= DIN;
						4'd11: {SYIEN, SYDEN, DSCREN, COWREN, MODRQ, FORMRQ, SHDREN} <= {DIN[7:2], DIN[0]};
						
						4'd12:;
						4'd13:;
						4'd14:;
						4'd15:;
					endcase
					

					if (|{AR})
						AR <= AR + 1'b1;
				end
			end
			else if (nRD_PREV & ~nRD)
			begin

				if (~RS)
					DOUT <= {4'b0000, AR};
				else
				begin
					case(AR)
						4'd0: DOUT <= 8'b00000000;
						4'd1: DOUT <= {~CMDI_FLAG, ~DTEI_FLAG, ~DECI_FLAG, 1'b1, nDTBSY, nSTBSY, nDTEN, nSTEN};
						
						4'd2: DOUT <= DBC[7:0];
						4'd3: DOUT <= {{4{DTEI_FLAG}}, DBC[11:8]};
						
						4'd4: DOUT <= HEAD[0];
						4'd5: DOUT <= HEAD[1];
						4'd6: DOUT <= HEAD[2];
						4'd7: DOUT <= 8'h01;
						
						4'd8: DOUT <= 8'h04;
						4'd9: DOUT <= 8'h00;
			
						4'd10: DOUT <= WA[7:0];
						4'd11: DOUT <= WA[15:8];
						
						4'd12: DOUT <= 8'b10000000;
						4'd13: DOUT <= 8'b00000000;
						4'd14: DOUT <= 8'b00000000;
						4'd15:
						begin
							DOUT <= {nVALST, 7'b0000000};
							DECI_FLAG <= 0;
						end
					endcase
				

					if (|{AR})
						AR <= AR + 1'b1;
				end
			end
		end
	end
	
endmodule
module lc8951(
	input nRESET,
	input CLK_12M,
	input nWR, nRD,
	input RS,
	input [7:0] DIN,
	output reg [7:0] DOUT,
	
	input [7:0] MSF_M,
	input [7:0] MSF_S,
	input [7:0] MSF_F,
	input MSF_LATCH,
	
	input SECTOR_READY,
	input DMA_RUNNING,
	output reg CDC_nIRQ
);


	reg [3:0] AR;
	reg [7:0] REGS_WRITE [16];
	
	reg [11:0] DBC;
	reg [15:0] DAC;


	reg [15:0] WA;
	reg nDTBSY, nSTBSY, nDTEN, nSTEN, nVALST;
	reg [7:0] HEAD [4];
	


	reg CMDI_FLAG, DTEI_FLAG, DECI_FLAG;
	reg CMDIEN, DTEIEN, DECIEN, nCMDBRK, nDTWAI, nSTWAI, DOUTEN, SOUTEN;
	reg DTTRG;
	reg DECEN, EDCRQ, E01RQ, AUTORQ, ERAMRQ, WRRQ, QRQ, PRQ;
	reg SYIEN, SYDEN, DSCREN, COWREN, MODRQ, FORMRQ, SHDREN;
	
	reg nWR_PREV, nRD_PREV;
	reg SECTOR_READY_PREV, DMA_RUNNING_PREV, MSF_LATCH_PREV;
	

	always @(negedge CLK_12M or negedge nRESET)
	begin
		if (!nRESET)
		begin
			AR <= 4'd0;
			nWR_PREV <= 1;
			nRD_PREV <= 1;
			
			CDC_nIRQ <= 1;
			
			DBC <= 12'h000;
			DAC <= 16'h0000;

			WA <= 16'h0000;
			
			CMDI_FLAG <= 0;
			DTEI_FLAG <= 0;
			DECI_FLAG <= 0;
			nDTBSY <= 1;
			nSTBSY <= 1;
			nDTEN <= 1;
			nSTEN <= 1;
			
			HEAD[0] <= 8'h00;
			HEAD[1] <= 8'h00;
			HEAD[2] <= 8'h00;
			HEAD[3] <= 8'h00;
			
			nVALST <= 1;
			
			{CMDIEN, DTEIEN, DECIEN, nCMDBRK, nDTWAI, nSTWAI, DOUTEN, SOUTEN} <= 8'b00000000;
			DTTRG <= 0;
			{DECEN, EDCRQ, E01RQ, AUTORQ, ERAMRQ, WRRQ, QRQ, PRQ} <= 8'b00000000;
			{SYIEN, SYDEN, DSCREN, COWREN, MODRQ, FORMRQ, SHDREN} <= 7'b0000000;
			
			SECTOR_READY_PREV <= 0;
			DMA_RUNNING_PREV <= 0;
		end
		else
		begin
			SECTOR_READY_PREV <= SECTOR_READY;
			DMA_RUNNING_PREV <= DMA_RUNNING;
			MSF_LATCH_PREV <= MSF_LATCH;
			

			if (~SECTOR_READY_PREV & SECTOR_READY)
			begin
				DECI_FLAG <= 1;
				nVALST <= 0;
			end
			

			if (DMA_RUNNING_PREV & ~DMA_RUNNING)
				DTEI_FLAG <= 1;
			

			if (~MSF_LATCH_PREV & MSF_LATCH)
			begin
				HEAD[0] <= MSF_M;
				HEAD[1] <= MSF_S;
				HEAD[2] <= MSF_F;

			end
			
			CDC_nIRQ <= ~|{(CMDI_FLAG & CMDIEN), (DTEI_FLAG & DTEIEN), (DECI_FLAG & DECIEN)};
		
			nWR_PREV <= nWR;
			nRD_PREV <= nRD;
			
			if (nWR_PREV & ~nWR)
			begin

				if (~RS)
					AR <= DIN[3:0];
				else
				begin
					case(AR)
						4'd0:;
						4'd1: {CMDIEN, DTEIEN, DECIEN, nCMDBRK, nDTWAI, nSTWAI, DOUTEN, SOUTEN} <= DIN;
						
						4'd2: DBC[7:0] <= DIN;
						4'd3: DBC[11:8] <= DIN[3:0];
						
						4'd4: DAC[7:0] <= DIN;
						4'd5: DAC[15:8] <= DIN;
						4'd6: DTTRG <= 1;
						4'd7: DTEI_FLAG <= 0;
						
						4'd8: WA[7:0] <= DIN;
						4'd9: WA[15:8] <= DIN;
			
						4'd10: {DECEN, EDCRQ, E01RQ, AUTORQ, ERAMRQ, WRRQ, QRQ, PRQ} <= DIN;
						4'd11: {SYIEN, SYDEN, DSCREN, COWREN, MODRQ, FORMRQ, SHDREN} <= {DIN[7:2], DIN[0]};
						
						4'd12:;
						4'd13:;
						4'd14:;
						4'd15:;
					endcase
					

					if (|{AR})
						AR <= AR + 1'b1;
				end
			end
			else if (nRD_PREV & ~nRD)
			begin

				if (~RS)
					DOUT <= {4'b0000, AR};
				else
				begin
					case(AR)
						4'd0: DOUT <= 8'b00000000;
						4'd1: DOUT <= {~CMDI_FLAG, ~DTEI_FLAG, ~DECI_FLAG, 1'b1, nDTBSY, nSTBSY, nDTEN, nSTEN};
						
						4'd2: DOUT <= DBC[7:0];
						4'd3: DOUT <= {{4{DTEI_FLAG}}, DBC[11:8]};
						
						4'd4: DOUT <= HEAD[0];
						4'd5: DOUT <= HEAD[1];
						4'd6: DOUT <= HEAD[2];
						4'd7: DOUT <= 8'h01;
						
						4'd8: DOUT <= 8'h04;
						4'd9: DOUT <= 8'h00;
			
						4'd10: DOUT <= WA[7:0];
						4'd11: DOUT <= WA[15:8];
						
						4'd12: DOUT <= 8'b10000000;
						4'd13: DOUT <= 8'b00000000;
						4'd14: DOUT <= 8'b00000000;
						4'd15:
						begin
							DOUT <= {nVALST, 7'b0000000};
							DECI_FLAG <= 0;
						end
					endcase
				

					if (|{AR})
						AR <= AR + 1'b1;
				end
			end
		end
	end
	
endmodule