data/full_repos/permissive/196412397/UART_Loopback_module.v
1: b"%Error: data/full_repos/permissive/196412397/UART_Loopback_module.v:25: Cannot find file containing module: 'UART_RX'\nUART_RX #(.CLKS_PER_BIT(868)) UART_RX_Inst\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/UART_RX\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/UART_RX.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/UART_RX.sv\n             UART_RX\n             UART_RX.v\n             UART_RX.sv\n             obj_dir/UART_RX\n             obj_dir/UART_RX.v\n             obj_dir/UART_RX.sv\n%Error: data/full_repos/permissive/196412397/UART_Loopback_module.v:31: Cannot find file containing module: 'UART_TX'\nUART_TX #(.CLKS_PER_BIT(868)) UART_TX_Inst\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module UART_Loopback_module #( parameter 
    DATA_WIDTH = 8
)
(   input clk,
    input loopback,
    input RsRx,
    output RsTx,
    output [DATA_WIDTH-1:0]   dout,
    output o_TX_Done,
    output o_RX_DV
);

wire w_TX_Active, w_TX_Serial;

wire [DATA_WIDTH-1:0] w_RX_Byte;

UART_RX #(.CLKS_PER_BIT(868)) UART_RX_Inst
    (.clk(clk),
     .RsRx(RsRx),
     .o_RX_DV(o_RX_DV),
     .o_RX_Byte(w_RX_Byte));

UART_TX #(.CLKS_PER_BIT(868)) UART_TX_Inst
    (.clk(clk),
     .i_TX_DV(o_RX_DV),
     .i_TX_Byte(w_RX_Byte),
     .o_TX_Active(w_TX_Active),
     .o_TX_Serial(w_TX_Serial),
     .o_TX_Done(o_TX_Done)); 


assign RsTx = (w_TX_Active && loopback) ? w_TX_Serial : 1'b1;

assign dout = w_RX_Byte;

endmodule
module UART_Loopback_module #( parameter 
    DATA_WIDTH = 8
)
(   input clk,
    input loopback,
    input RsRx,
    output RsTx,
    output [DATA_WIDTH-1:0]   dout,
    output o_TX_Done,
    output o_RX_DV
);


wire w_TX_Active, w_TX_Serial;

wire [DATA_WIDTH-1:0] w_RX_Byte;

UART_RX #(.CLKS_PER_BIT(868)) UART_RX_Inst
    (.clk(clk),
     .RsRx(RsRx),
     .o_RX_DV(o_RX_DV),
     .o_RX_Byte(w_RX_Byte));

UART_TX #(.CLKS_PER_BIT(868)) UART_TX_Inst
    (.clk(clk),
     .i_TX_DV(o_RX_DV),
     .i_TX_Byte(w_RX_Byte),
     .o_TX_Active(w_TX_Active),
     .o_TX_Serial(w_TX_Serial),
     .o_TX_Done(o_TX_Done)); 


assign RsTx = (w_TX_Active && loopback) ? w_TX_Serial : 1'b1;

assign dout = w_RX_Byte;

endmodule