data/full_repos/permissive/143278/ivltests/signed_net_display.v
 line:8: before: "for"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/signed_net_display.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_net_display.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hffffffff\' generates 32 bits.\n                                                                                 : ... In instance signed_net_display\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_net_display.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffffe\' generates 32 bits.\n                                                                                 : ... In instance signed_net_display\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_net_display.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffffd\' generates 32 bits.\n                                                                                 : ... In instance signed_net_display\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_net_display.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffffc\' generates 32 bits.\n                                                                                 : ... In instance signed_net_display\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_net_display.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffffb\' generates 32 bits.\n                                                                                 : ... In instance signed_net_display\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_net_display.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffffa\' generates 32 bits.\n                                                                                 : ... In instance signed_net_display\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_net_display.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffff9\' generates 32 bits.\n                                                                                 : ... In instance signed_net_display\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_net_display.v:26: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                  : ... In instance signed_net_display\n        expect[0*8 +: 8] = "0" - j;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_net_display.v:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                  : ... In instance signed_net_display\n        expect[0*8 +: 8] = "0" + j;\n                         ^\n%Error: Exiting due to 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module signed_net_display;

wire signed [3:0] value[-7:7];

genvar i;

for (i = 7; i >= -7; i = i - 1) begin:genloop
  assign value[i] = i;
end

reg [2*8-1:0] result;
reg [2*8-1:0] expect;

integer j;

reg fail = 0;

initial begin
  #0;
  for (j = -7; j <= 7; j = j + 1) begin
    $swrite(result, "%d", value[j]);
    if (j < 0)
      begin
        expect[1*8 +: 8] = "-";
        expect[0*8 +: 8] = "0" - j;
      end
    else
      begin
        expect[1*8 +: 8] = " ";
        expect[0*8 +: 8] = "0" + j;
      end
    $display("%s : %s", expect, result);
    if (result !== expect) fail = 1;
  end

  if (fail)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module signed_net_display;


wire signed [3:0] value[-7:7];

genvar i;

for (i = 7; i >= -7; i = i - 1) begin:genloop
  assign value[i] = i;
end

reg [2*8-1:0] result;
reg [2*8-1:0] expect;

integer j;

reg fail = 0;

initial begin
  #0;
  for (j = -7; j <= 7; j = j + 1) begin
    $swrite(result, "%d", value[j]);
    if (j < 0)
      begin
        expect[1*8 +: 8] = "-";
        expect[0*8 +: 8] = "0" - j;
      end
    else
      begin
        expect[1*8 +: 8] = " ";
        expect[0*8 +: 8] = "0" + j;
      end
    $display("%s : %s", expect, result);
    if (result !== expect) fail = 1;
  end

  if (fail)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule