data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v
 line:1 column:1: Illegal character '\x00'
1: b'%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:50: Cannot find include file: trellis.vh\n`include "trellis.vh" // Defines the user-facing signal widths. \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh.v\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh.sv\n             trellis.vh\n             trellis.vh.v\n             trellis.vh.sv\n             obj_dir/trellis.vh\n             obj_dir/trellis.vh.v\n             obj_dir/trellis.vh.sv\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:51: Cannot find include file: tlp.vh\n`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP \n         ^~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:67: Define or directive not defined: \'`SIG_CPLID_W\'\n     input [`SIG_CPLID_W-1:0]                 CONFIG_COMPLETER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:88: Define or directive not defined: \'`SIG_FBE_W\'\n     input [`SIG_FBE_W-1:0]                   TXC_META_FDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:89: Define or directive not defined: \'`SIG_LBE_W\'\n     input [`SIG_LBE_W-1:0]                   TXC_META_LDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:90: Define or directive not defined: \'`SIG_LOWADDR_W\'\n     input [`SIG_LOWADDR_W-1:0]               TXC_META_ADDR,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:91: Define or directive not defined: \'`SIG_TYPE_W\'\n     input [`SIG_TYPE_W-1:0]                  TXC_META_TYPE,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:92: Define or directive not defined: \'`SIG_LEN_W\'\n     input [`SIG_LEN_W-1:0]                   TXC_META_LENGTH,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:93: Define or directive not defined: \'`SIG_BYTECNT_W\'\n     input [`SIG_BYTECNT_W-1:0]               TXC_META_BYTE_COUNT,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:94: Define or directive not defined: \'`SIG_TAG_W\'\n     input [`SIG_TAG_W-1:0]                   TXC_META_TAG,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:95: Define or directive not defined: \'`SIG_REQID_W\'\n     input [`SIG_REQID_W-1:0]                 TXC_META_REQUESTER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:96: Define or directive not defined: \'`SIG_TC_W\'\n     input [`SIG_TC_W-1:0]                    TXC_META_TC,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:97: Define or directive not defined: \'`SIG_ATTR_W\'\n     input [`SIG_ATTR_W-1:0]                  TXC_META_ATTR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:102: Define or directive not defined: \'`TLP_MAXHDR_W\'\n    localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:102: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;\n                                              ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:117: Define or directive not defined: \'`SIG_TYPE_W\'\n    wire [`SIG_TYPE_W-1:0]                    wTxType;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:118: Define or directive not defined: \'`SIG_NONPAY_W\'\n    wire [`SIG_NONPAY_W-1:0]                  wTxHdrNonpayLen;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:119: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n    wire [`SIG_PACKETLEN_W-1:0]               wTxHdrPacketLen;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:120: Define or directive not defined: \'`SIG_LEN_W\'\n    wire [`SIG_LEN_W-1:0]                     wTxHdrPayloadLen; \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:141: Define or directive not defined: \'`SIG_LEN_W\'\n         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:142: Define or directive not defined: \'`SIG_NONPAY_W\'\n         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:143: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:152: Define or directive not defined: \'`SIG_CPLID_W\'\n         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),\n                                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:154: Define or directive not defined: \'`SIG_FBE_W\'\n         .TXC_META_FDWBE                (TXC_META_FDWBE[`SIG_FBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:155: Define or directive not defined: \'`SIG_LBE_W\'\n         .TXC_META_LDWBE                (TXC_META_LDWBE[`SIG_LBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:156: Define or directive not defined: \'`SIG_LOWADDR_W\'\n         .TXC_META_ADDR                 (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),\n                                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:157: Define or directive not defined: \'`SIG_LEN_W\'\n         .TXC_META_LENGTH               (TXC_META_LENGTH[`SIG_LEN_W-1:0]),\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:158: Define or directive not defined: \'`SIG_BYTECNT_W\'\n         .TXC_META_BYTE_COUNT           (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),\n                                                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:159: Define or directive not defined: \'`SIG_TAG_W\'\n         .TXC_META_TAG                  (TXC_META_TAG[`SIG_TAG_W-1:0]),\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:160: Define or directive not defined: \'`SIG_TYPE_W\'\n         .TXC_META_TYPE                 (TXC_META_TYPE[`SIG_TYPE_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:161: Define or directive not defined: \'`SIG_REQID_W\'\n         .TXC_META_REQUESTER_ID         (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),\n                                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:162: Define or directive not defined: \'`SIG_TC_W\'\n         .TXC_META_TC                   (TXC_META_TC[`SIG_TC_W-1:0]),\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:163: Define or directive not defined: \'`SIG_ATTR_W\'\n         .TXC_META_ATTR                 (TXC_META_ATTR[`SIG_ATTR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:193: Define or directive not defined: \'`SIG_LEN_W\'\n         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:194: Define or directive not defined: \'`SIG_NONPAY_W\'\n         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:195: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:212: Define or directive not defined: \'`TLP_MAXHDR_W\'\n      parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,\n                                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:212: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,\n                                               ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:214: syntax error, unexpected parameter, expecting IDENTIFIER\n      parameter C_PIPELINE_INPUT = 1,\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:215: syntax error, unexpected parameter, expecting IDENTIFIER\n      parameter C_PIPELINE_OUTPUT = 1,\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:216: syntax error, unexpected parameter, expecting IDENTIFIER\n      parameter C_VENDOR = "ALTERA"\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:217: syntax error, unexpected \')\', expecting \';\'\n      )\n      ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:226: Define or directive not defined: \'`SIG_CPLID_W\'\n     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:230: Define or directive not defined: \'`SIG_FBE_W\'\n     input [`SIG_FBE_W-1:0]        TXC_META_FDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:231: Define or directive not defined: \'`SIG_LBE_W\'\n     input [`SIG_LBE_W-1:0]        TXC_META_LDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:232: Define or directive not defined: \'`SIG_LOWADDR_W\'\n     input [`SIG_LOWADDR_W-1:0]    TXC_META_ADDR,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:233: Define or directive not defined: \'`SIG_LEN_W\'\n     input [`SIG_LEN_W-1:0]        TXC_META_LENGTH,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:234: Define or directive not defined: \'`SIG_BYTECNT_W\'\n     input [`SIG_BYTECNT_W-1:0]    TXC_META_BYTE_COUNT,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:235: Define or directive not defined: \'`SIG_TAG_W\'\n     input [`SIG_TAG_W-1:0]        TXC_META_TAG,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txc_engine_classic.v:236: Define or directive not defined: \'`SIG_TYPE_W\'\n     input [`SIG_TYPE_W-1:0]       TXC_META_TYPE,\n            ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module txc_formatter_classic
    #(
      parameter C_PCI_DATA_WIDTH = 10'd128,
      parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
      parameter C_MAX_ALIGN_WIDTH = 32,
      parameter C_PIPELINE_INPUT = 1,
      parameter C_PIPELINE_OUTPUT = 1,
      parameter C_VENDOR = "ALTERA"
      )
    (

     input                         CLK,


     input                         RST_IN,


     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,


     input                         TXC_META_VALID,
     input [`SIG_FBE_W-1:0]        TXC_META_FDWBE,
     input [`SIG_LBE_W-1:0]        TXC_META_LDWBE,
     input [`SIG_LOWADDR_W-1:0]    TXC_META_ADDR,
     input [`SIG_LEN_W-1:0]        TXC_META_LENGTH,
     input [`SIG_BYTECNT_W-1:0]    TXC_META_BYTE_COUNT,
     input [`SIG_TAG_W-1:0]        TXC_META_TAG,
     input [`SIG_TYPE_W-1:0]       TXC_META_TYPE,
     input [`SIG_REQID_W-1:0]      TXC_META_REQUESTER_ID,
     input [`SIG_TC_W-1:0]         TXC_META_TC,
     input [`SIG_ATTR_W-1:0]       TXC_META_ATTR,
     input                         TXC_META_EP,
     output                        TXC_META_READY,


     output                        TX_HDR_VALID,
     output [C_MAX_HDR_WIDTH-1:0]  TX_HDR,
     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,
     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,
     output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
     output                        TX_HDR_NOPAYLOAD,
     input                         TX_HDR_READY
     );

    wire [C_MAX_HDR_WIDTH-1:0]     wCplHdr;


    wire                           wTxHdrReady;
    wire                           wTxHdrValid;
    wire [C_MAX_HDR_WIDTH-1:0]     wTxHdr;
    wire [`SIG_TYPE_W-1:0]         wTxType;
    wire [`SIG_NONPAY_W-1:0]       wTxHdrNonpayLen;
    wire [`SIG_PACKETLEN_W-1:0]    wTxHdrPacketLen;
    wire [`SIG_LEN_W-1:0]          wTxHdrPayloadLen; 
    wire                           wTxHdrNopayload;

    wire [`TLP_CPLADDR_W-1:0]      wTxLoAddr;



    assign wCplHdr[`TLP_RSVD0_R] = `TLP_RSVD0_V;
    assign wCplHdr[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
    assign wCplHdr[`TLP_TH_R] = `TLP_TH_W'b0;
    assign wCplHdr[`TLP_RSVD1_R] = `TLP_RSVD1_V;
    assign wCplHdr[`TLP_RSVD2_R] = `TLP_RSVD2_V;
    assign wCplHdr[`TLP_CPLBCM_R] = `TLP_CPLBCM_W'b0;
    assign wCplHdr[`TLP_CPLRSVD0_R] = `TLP_CPLRSVD0_W'b0;
    assign wCplHdr[127:96] = 32'b0;


    assign wCplHdr[`TLP_LEN_R] = TXC_META_LENGTH;
    assign wCplHdr[`TLP_EP_R] = TXC_META_EP;
    assign wCplHdr[`TLP_TD_R] = `TLP_NODIGEST_V;
    assign wCplHdr[`TLP_ATTR0_R] = TXC_META_ATTR[1:0];
    assign wCplHdr[`TLP_ATTR1_R] = TXC_META_ATTR[2];
    assign {wCplHdr[`TLP_FMT_R], wCplHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(TXC_META_TYPE,0);
    assign wCplHdr[`TLP_TC_R] = TXC_META_TC;


    assign wCplHdr[`TLP_CPLBYTECNT_R] = TXC_META_BYTE_COUNT;
    assign wCplHdr[`TLP_CPLSTAT_R] = 0;
    assign wCplHdr[`TLP_CPLCPLID_R] = CONFIG_COMPLETER_ID;
    assign wCplHdr[`TLP_CPLADDR_R] = TXC_META_ADDR;
    assign wCplHdr[`TLP_CPLTAG_R] = TXC_META_TAG;
    assign wCplHdr[`TLP_CPLREQID_R] = TXC_META_REQUESTER_ID;


    assign wTxLoAddr = wTxHdr[`TLP_CPLADDR_R];
    assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
    assign wTxHdrNonpayLen = 3 + ((C_VENDOR == "ALTERA")? {3'b0,(~wTxLoAddr[2] & ~wTxHdrNopayload)} : 4'b0);
    assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
    assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;    

    pipeline
        #(
          .C_DEPTH                         (C_PIPELINE_INPUT?1:0),
          .C_WIDTH                         (C_MAX_HDR_WIDTH),
          .C_USE_MEMORY                    (0)
)
    input_inst
        (
         .WR_DATA_READY                  (TXC_META_READY),
         .RD_DATA                        (wTxHdr),
         .RD_DATA_VALID                  (wTxHdrValid),

         .WR_DATA                        (wCplHdr),
         .WR_DATA_VALID                  (TXC_META_VALID),
         .RD_DATA_READY                  (wTxHdrReady),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    pipeline
        #(

          .C_DEPTH                         (C_PIPELINE_OUTPUT?1:0),
          .C_WIDTH                         (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
          .C_USE_MEMORY                    (0)
)
    output_inst
        (

         .WR_DATA_READY                  (wTxHdrReady),
         .RD_DATA                        ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
         .RD_DATA_VALID                  (TX_HDR_VALID),

         .WR_DATA                        ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
         .WR_DATA_VALID                  (wTxHdrValid),
         .RD_DATA_READY                  (TX_HDR_READY),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));
endmodule
module txc_formatter_classic
    #(
      parameter C_PCI_DATA_WIDTH = 10'd128,
      parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
      parameter C_MAX_ALIGN_WIDTH = 32,
      parameter C_PIPELINE_INPUT = 1,
      parameter C_PIPELINE_OUTPUT = 1,
      parameter C_VENDOR = "ALTERA"
      )
    (

     input                         CLK,


     input                         RST_IN,


     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,


     input                         TXC_META_VALID,
     input [`SIG_FBE_W-1:0]        TXC_META_FDWBE,
     input [`SIG_LBE_W-1:0]        TXC_META_LDWBE,
     input [`SIG_LOWADDR_W-1:0]    TXC_META_ADDR,
     input [`SIG_LEN_W-1:0]        TXC_META_LENGTH,
     input [`SIG_BYTECNT_W-1:0]    TXC_META_BYTE_COUNT,
     input [`SIG_TAG_W-1:0]        TXC_META_TAG,
     input [`SIG_TYPE_W-1:0]       TXC_META_TYPE,
     input [`SIG_REQID_W-1:0]      TXC_META_REQUESTER_ID,
     input [`SIG_TC_W-1:0]         TXC_META_TC,
     input [`SIG_ATTR_W-1:0]       TXC_META_ATTR,
     input                         TXC_META_EP,
     output                        TXC_META_READY,


     output                        TX_HDR_VALID,
     output [C_MAX_HDR_WIDTH-1:0]  TX_HDR,
     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,
     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,
     output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
     output                        TX_HDR_NOPAYLOAD,
     input                         TX_HDR_READY
     );


    wire [C_MAX_HDR_WIDTH-1:0]     wCplHdr;


    wire                           wTxHdrReady;
    wire                           wTxHdrValid;
    wire [C_MAX_HDR_WIDTH-1:0]     wTxHdr;
    wire [`SIG_TYPE_W-1:0]         wTxType;
    wire [`SIG_NONPAY_W-1:0]       wTxHdrNonpayLen;
    wire [`SIG_PACKETLEN_W-1:0]    wTxHdrPacketLen;
    wire [`SIG_LEN_W-1:0]          wTxHdrPayloadLen; 
    wire                           wTxHdrNopayload;

    wire [`TLP_CPLADDR_W-1:0]      wTxLoAddr;



    assign wCplHdr[`TLP_RSVD0_R] = `TLP_RSVD0_V;
    assign wCplHdr[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
    assign wCplHdr[`TLP_TH_R] = `TLP_TH_W'b0;
    assign wCplHdr[`TLP_RSVD1_R] = `TLP_RSVD1_V;
    assign wCplHdr[`TLP_RSVD2_R] = `TLP_RSVD2_V;
    assign wCplHdr[`TLP_CPLBCM_R] = `TLP_CPLBCM_W'b0;
    assign wCplHdr[`TLP_CPLRSVD0_R] = `TLP_CPLRSVD0_W'b0;
    assign wCplHdr[127:96] = 32'b0;


    assign wCplHdr[`TLP_LEN_R] = TXC_META_LENGTH;
    assign wCplHdr[`TLP_EP_R] = TXC_META_EP;
    assign wCplHdr[`TLP_TD_R] = `TLP_NODIGEST_V;
    assign wCplHdr[`TLP_ATTR0_R] = TXC_META_ATTR[1:0];
    assign wCplHdr[`TLP_ATTR1_R] = TXC_META_ATTR[2];
    assign {wCplHdr[`TLP_FMT_R], wCplHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(TXC_META_TYPE,0);
    assign wCplHdr[`TLP_TC_R] = TXC_META_TC;


    assign wCplHdr[`TLP_CPLBYTECNT_R] = TXC_META_BYTE_COUNT;
    assign wCplHdr[`TLP_CPLSTAT_R] = 0;
    assign wCplHdr[`TLP_CPLCPLID_R] = CONFIG_COMPLETER_ID;
    assign wCplHdr[`TLP_CPLADDR_R] = TXC_META_ADDR;
    assign wCplHdr[`TLP_CPLTAG_R] = TXC_META_TAG;
    assign wCplHdr[`TLP_CPLREQID_R] = TXC_META_REQUESTER_ID;


    assign wTxLoAddr = wTxHdr[`TLP_CPLADDR_R];
    assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
    assign wTxHdrNonpayLen = 3 + ((C_VENDOR == "ALTERA")? {3'b0,(~wTxLoAddr[2] & ~wTxHdrNopayload)} : 4'b0);
    assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
    assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;    

    pipeline
        #(
          .C_DEPTH                         (C_PIPELINE_INPUT?1:0),
          .C_WIDTH                         (C_MAX_HDR_WIDTH),
          .C_USE_MEMORY                    (0)
)
    input_inst
        (
         .WR_DATA_READY                  (TXC_META_READY),
         .RD_DATA                        (wTxHdr),
         .RD_DATA_VALID                  (wTxHdrValid),

         .WR_DATA                        (wCplHdr),
         .WR_DATA_VALID                  (TXC_META_VALID),
         .RD_DATA_READY                  (wTxHdrReady),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    pipeline
        #(

          .C_DEPTH                         (C_PIPELINE_OUTPUT?1:0),
          .C_WIDTH                         (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
          .C_USE_MEMORY                    (0)
)
    output_inst
        (

         .WR_DATA_READY                  (wTxHdrReady),
         .RD_DATA                        ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
         .RD_DATA_VALID                  (TX_HDR_VALID),

         .WR_DATA                        ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
         .WR_DATA_VALID                  (wTxHdrValid),
         .RD_DATA_READY                  (TX_HDR_READY),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));
endmodule