data/full_repos/permissive/215648344/multiplicador_v3.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/215648344/multiplicador_v3.v:112: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'multiplicador\'\nmodule multiplicador (input clk, input [31:0] A, B, output [31:0] resultado, salida,dum, output [4:0] cuenta, output lsb);\n       ^~~~~~~~~~~~~\n                                                                              : ... Top module \'shift_reg\'\nmodule shift_reg(input [31:0] entrada, input clk, S, output [31:0] Z);\n       ^~~~~~~~~\n                                                                              : ... Top module \'shift_reg_s\'\nmodule shift_reg_s(input [31:0] entrada, input clk, S, output [31:0] Z);\n       ^~~~~~~~~~~\n                                                                              : ... Top module \'mux_init\'\nmodule mux_init( input [4:0] contador, input [31:0] ent , output [31:0] sal );\n       ^~~~~~~~\n                                                                              : ... Top module \'control_multplier\'\nmodule control_multplier(input [31:0] A, B, input clk, output [31:0] Y, output [4:0] Cuenta);\n       ^~~~~~~~~~~~~~~~~\n                                                                              : ... Top module \'control_multiplicand\'\nmodule control_multiplicand (input clk, S, input [31:0] E, output [31:0] Y);\n       ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/215648344/multiplicador_v3.v:20: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n                                                                          : ... In instance multiplicador\n  shift_out <= {8\'b0, B[15:0]};\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/215648344/multiplicador_v3.v:24: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n                                                                          : ... In instance multiplicador\n  aux_in <= {8\'b0, B[15:0]};\n         ^~\n%Error: Exiting due to 3 warning(s)\n'
module multiplicador (input clk, input [31:0] A, B, output [31:0] resultado, salida,dum, output [4:0] cuenta, output lsb);

reg [31:0] mcand, mplier, aux_out, shift_out, shift_in, aux_in, final_reg;
reg [3:0] count2;
reg [4:0] count;
wire [31:0] dummy_wire;
wire b;
wire [31:0] Shift_reg;

reg ini = 1'b1;

always @ ( negedge clk) begin
  if (ini) begin

  shift_out <= {8'b0, B[15:0]};
  mcand <= A;
  count <= 5'b0000;
  count2 <= 4'b0000;
  aux_in <= {8'b0, B[15:0]};
  ini <= 1'b0;
  end else begin

  if (count2 == 4'b0000) begin
    count2 = count2 + 1;
  end else begin

  if (count < 5'd16) begin
  aux_in = Shift_reg;
  shift_out = Shift_reg;
  count = count + 1;
  end else if (count == 5'd16) begin
  aux_in = Shift_reg;
  shift_out = Shift_reg;
  final_reg = Shift_reg;
  ini = 1;
  end




    end
  end

end
controlador c(clk, count, aux_in, mcand, dummy_wire,dum, b);









assign Shift_reg[30:0] = dummy_wire[31:1];
assign Shift_reg[31] = 1'b0;

assign resultado = final_reg;
assign salida = dummy_wire;
assign cuenta = count;
assign lsb = b;

endmodule
module multiplicador (input clk, input [31:0] A, B, output [31:0] resultado, salida,dum, output [4:0] cuenta, output lsb);


reg [31:0] mcand, mplier, aux_out, shift_out, shift_in, aux_in, final_reg;
reg [3:0] count2;
reg [4:0] count;
wire [31:0] dummy_wire;
wire b;
wire [31:0] Shift_reg;

reg ini = 1'b1;

always @ ( negedge clk) begin
  if (ini) begin

  shift_out <= {8'b0, B[15:0]};
  mcand <= A;
  count <= 5'b0000;
  count2 <= 4'b0000;
  aux_in <= {8'b0, B[15:0]};
  ini <= 1'b0;
  end else begin

  if (count2 == 4'b0000) begin
    count2 = count2 + 1;
  end else begin

  if (count < 5'd16) begin
  aux_in = Shift_reg;
  shift_out = Shift_reg;
  count = count + 1;
  end else if (count == 5'd16) begin
  aux_in = Shift_reg;
  shift_out = Shift_reg;
  final_reg = Shift_reg;
  ini = 1;
  end




    end
  end

end
controlador c(clk, count, aux_in, mcand, dummy_wire,dum, b);









assign Shift_reg[30:0] = dummy_wire[31:1];
assign Shift_reg[31] = 1'b0;

assign resultado = final_reg;
assign salida = dummy_wire;
assign cuenta = count;
assign lsb = b;

endmodule