data/full_repos/permissive/135852214/Verilog/mux16_8.v
1: b'%Warning-WIDTH: data/full_repos/permissive/135852214/Verilog/mux16_8.v:27: Operator NOT expects 8 bits on the LHS, but LHS\'s VARREF \'s\' generates 1 bits.\n                                                                         : ... In instance mux16_8\nassign out = ~s & a | s & b;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/135852214/Verilog/mux16_8.v:27: Operator AND expects 8 bits on the LHS, but LHS\'s VARREF \'s\' generates 1 bits.\n                                                                         : ... In instance mux16_8\nassign out = ~s & a | s & b;\n                        ^\n%Error: Exiting due to 2 warning(s)\n'
module mux16_8(
    input [7:0] a,
    input [7:0] b,
    input s,
    output [7:0] out
    );
assign out = ~s & a | s & b;

endmodule
module mux16_8(
    input [7:0] a,
    input [7:0] b,
    input s,
    output [7:0] out
    );

assign out = ~s & a | s & b;

endmodule