data/full_repos/permissive/132220215/d_ff.v
1: b"%Error: data/full_repos/permissive/132220215/d_ff.v:8: Duplicate declaration of signal: 'Q'\n                                                     : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg Q;\n     ^\n        data/full_repos/permissive/132220215/d_ff.v:6: ... Location of original declaration\n output Q);\n        ^\n%Error: Exiting due to 1 error(s)\n"
module D_FF(
	input D,
	input clk,
	output Q);

 reg Q;

 always @(posedge clk) 
	 Q <= D;
endmodule
module D_FF(
	input D,
	input clk,
	output Q);


 reg Q;

 always @(posedge clk) 
	 Q <= D;
endmodule