data/full_repos/permissive/174643991/DCPU/DCPU_test01.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:126: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:128: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:130: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:133: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:134: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;\n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:134: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;\n                                                           ^\n%Error: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:139: Unsupported or unknown PLI call: $monitor\n    $monitor("%b  :%h         :%h:%h         :%h  :%b        :%h   ",\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:150: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00010,  3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:150: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00010,  3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:151: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10111,  3\'h1, 4\'h0, 4\'h2}; #10; CLK <= 1; #10; CLK <= 0;  \n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:151: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10111,  3\'h1, 4\'h0, 4\'h2}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:152: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10000,   3\'h5, 4\'h0, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:152: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10000,   3\'h5, 4\'h0, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:153: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00110,  3\'h0, 4\'h2, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:153: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00110,  3\'h0, 4\'h2, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:154: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10011,   3\'h0, 4\'h0, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:154: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10011,   3\'h0, 4\'h0, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:155: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10011,   3\'h0, 4\'h0, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:155: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10011,   3\'h0, 4\'h0, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:156: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10011,   3\'h0, 4\'h0, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:156: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10011,   3\'h0, 4\'h0, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:158: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10000,   3\'h0, 4\'h0, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:158: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b10000,   3\'h0, 4\'h0, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:159: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00011, 3\'h5, 4\'h2, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:159: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00011, 3\'h5, 4\'h2, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:160: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00011, 3\'h0, 4\'h2, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:160: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00011, 3\'h0, 4\'h2, 4\'h1}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:161: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:161: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:162: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:162: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:163: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:163: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:164: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:164: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:165: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:165: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00000,   3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:166: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00001,  3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174643991/DCPU/DCPU_test01.v:166: Unsupported: Ignoring delay on this delayed statement.\n    Inst <= {5\'b00001,  3\'h0, 4\'h0, 4\'h0}; #10; CLK <= 1; #10; CLK <= 0;  \n                                                          ^\n%Error: Exiting due to 1 error(s), 38 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DCPU_test01;



  `define NOP   5'b00000
  `define HALT  5'b00001

  `define LOAD  5'b00010
  `define STORE 5'b00011

  `define CMP   5'b00100

  `define BE    5'b00101
  `define JUMP  5'b00110
  `define JMPR  5'b00111
  `define BZ    5'b01000
  `define BNZ   5'b01001
  `define BN    5'b01010
  `define BNN   5'b01011
  `define BC    5'b01100
  `define BNC   5'b01101
  `define BB    5'b01110
  `define BS    5'b01111

  `define ADD   5'b10000
  `define ADDI  5'b10001
  `define ADDC  5'b10010
  `define SUB   5'b10011
  `define SUBI  5'b10100
  `define SUBB  5'b10101
  `define INC   5'b10110

  `define LDIL  5'b10111
  `define LDIH  5'b11000

  `define XOR   5'b11001
  `define AND   5'b11010
  `define OR    5'b11011

  `define SLL   5'b11100
  `define SLA   5'b11101
  `define SRL   5'b11110
  `define SRA   5'b11111
  

  `define AR0 3'h0
  `define BR0 4'h0
  `define AR1 3'h1
  `define BR1 4'h1
  `define AR2 3'h2
  `define BR2 4'h2
  `define AR3 3'h3
  `define BR3 4'h3
  `define AR4 3'h4
  `define BR4 4'h4
  `define AR5 3'h5
  `define BR5 4'h5
  `define AR6 3'h6
  `define BR6 4'h6
  `define AR7 3'h7
  `define BR7 4'h7
  


	reg CLK;
	reg RST;
	reg EN;
	reg Start;
	reg [15:0] Inst;
	reg [15:0] DataIn;


	wire [7:0] InstMemAddr;
	wire [7:0] DataMemAddr;
	wire DataMemWE;
	wire [15:0] DataOut;


	DCPU uut (
		.CLK(CLK), 
		.RST(RST), 
		.EN(EN), 
		.Start(Start), 
		.InstMemAddr(InstMemAddr), 
		.Inst(Inst), 
		.DataMemAddr(DataMemAddr), 
		.DataIn(DataIn), 
		.DataMemWE(DataMemWE), 
		.DataOut(DataOut)
	);

	initial begin

		CLK = 0;
		RST = 0;
		EN = 0;
		Start = 0;
		Inst = 0;
		DataIn = 0;


    #100;
    RST <= 1'b1;
    #100;
    RST <= 1'b0;
    #100;
    EN    <= 1'b1;
    Start <= 1'b1;
    #100;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;

    $display("CLK:InstMemAddr:Inst:DataMemAddr:DataIn:DataMemWE:DataOut");
    

    $monitor("%b  :%h         :%h:%h         :%h  :%b        :%h   ",
             uut.CLK,
             uut.InstMemAddr,
             uut.Inst,
             uut.DataMemAddr,
             uut.DataIn,
             uut.DataMemWE,
             uut.DataOut);
    

    DataIn <= 16'h9;
    Inst <= {`LOAD,  `AR0, `BR0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`LDIL,  `AR1, 4'h0, 4'h2}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`ADD,   `AR5, `BR0, `BR1}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`JUMP,  `AR0, 4'h2, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`SUB,   `AR0, `BR0, `BR1}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`SUB,   `AR0, `BR0, `BR1}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`SUB,   `AR0, `BR0, `BR1}; #10; CLK <= 1; #10; CLK <= 0;
    
    Inst <= {`ADD,   `AR0, `BR0, `BR1}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`STORE, `AR5, `BR2, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`STORE, `AR0, `BR2, 4'h1}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`HALT,  3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;

	end
      
endmodule
module DCPU_test01;




  `define NOP   5'b00000
  `define HALT  5'b00001

  `define LOAD  5'b00010
  `define STORE 5'b00011

  `define CMP   5'b00100

  `define BE    5'b00101
  `define JUMP  5'b00110
  `define JMPR  5'b00111
  `define BZ    5'b01000
  `define BNZ   5'b01001
  `define BN    5'b01010
  `define BNN   5'b01011
  `define BC    5'b01100
  `define BNC   5'b01101
  `define BB    5'b01110
  `define BS    5'b01111

  `define ADD   5'b10000
  `define ADDI  5'b10001
  `define ADDC  5'b10010
  `define SUB   5'b10011
  `define SUBI  5'b10100
  `define SUBB  5'b10101
  `define INC   5'b10110

  `define LDIL  5'b10111
  `define LDIH  5'b11000

  `define XOR   5'b11001
  `define AND   5'b11010
  `define OR    5'b11011

  `define SLL   5'b11100
  `define SLA   5'b11101
  `define SRL   5'b11110
  `define SRA   5'b11111
  

  `define AR0 3'h0
  `define BR0 4'h0
  `define AR1 3'h1
  `define BR1 4'h1
  `define AR2 3'h2
  `define BR2 4'h2
  `define AR3 3'h3
  `define BR3 4'h3
  `define AR4 3'h4
  `define BR4 4'h4
  `define AR5 3'h5
  `define BR5 4'h5
  `define AR6 3'h6
  `define BR6 4'h6
  `define AR7 3'h7
  `define BR7 4'h7
  


	reg CLK;
	reg RST;
	reg EN;
	reg Start;
	reg [15:0] Inst;
	reg [15:0] DataIn;


	wire [7:0] InstMemAddr;
	wire [7:0] DataMemAddr;
	wire DataMemWE;
	wire [15:0] DataOut;


	DCPU uut (
		.CLK(CLK), 
		.RST(RST), 
		.EN(EN), 
		.Start(Start), 
		.InstMemAddr(InstMemAddr), 
		.Inst(Inst), 
		.DataMemAddr(DataMemAddr), 
		.DataIn(DataIn), 
		.DataMemWE(DataMemWE), 
		.DataOut(DataOut)
	);

	initial begin

		CLK = 0;
		RST = 0;
		EN = 0;
		Start = 0;
		Inst = 0;
		DataIn = 0;


    #100;
    RST <= 1'b1;
    #100;
    RST <= 1'b0;
    #100;
    EN    <= 1'b1;
    Start <= 1'b1;
    #100;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;

    $display("CLK:InstMemAddr:Inst:DataMemAddr:DataIn:DataMemWE:DataOut");
    

    $monitor("%b  :%h         :%h:%h         :%h  :%b        :%h   ",
             uut.CLK,
             uut.InstMemAddr,
             uut.Inst,
             uut.DataMemAddr,
             uut.DataIn,
             uut.DataMemWE,
             uut.DataOut);
    

    DataIn <= 16'h9;
    Inst <= {`LOAD,  `AR0, `BR0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`LDIL,  `AR1, 4'h0, 4'h2}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`ADD,   `AR5, `BR0, `BR1}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`JUMP,  `AR0, 4'h2, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`SUB,   `AR0, `BR0, `BR1}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`SUB,   `AR0, `BR0, `BR1}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`SUB,   `AR0, `BR0, `BR1}; #10; CLK <= 1; #10; CLK <= 0;
    
    Inst <= {`ADD,   `AR0, `BR0, `BR1}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`STORE, `AR5, `BR2, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`STORE, `AR0, `BR2, 4'h1}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`NOP,   3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;
    Inst <= {`HALT,  3'h0, 4'h0, 4'h0}; #10; CLK <= 1; #10; CLK <= 0;

	end
      
endmodule