data/full_repos/permissive/143278/ivltests/br605a.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br605a.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b", dst);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br605a.v:7: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'src\' generates 2 bits.\n                                                                     : ... In instance test\n  assign dst = src;\n  ^~~~~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

reg [1:0] src;
reg [2:0] dst;

initial begin
  assign dst = src;
  src = 2'b01;
  #1 $display("%b", dst);
  if (dst === 3'b001)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module test();


reg [1:0] src;
reg [2:0] dst;

initial begin
  assign dst = src;
  src = 2'b01;
  #1 $display("%b", dst);
  if (dst === 3'b001)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule