data/full_repos/permissive/120142431/mux.v
data/verilator_xmls/703b5a42-1c16-43a0-8251-5c1a4e0d955d.xml
module mux(i0, i1, s, o);
input [15:0] i0;
input [15:0] i1;
input s;
output [15:0] o;
assign o = s ? i1 : i0;
endmodule
module mux(i0, i1, s, o);

input [15:0] i0;
input [15:0] i1;
input s;
output [15:0] o;
assign o = s ? i1 : i0;
endmodule