data/full_repos/permissive/155004694/sim/reg_file_sim.v
 line:24: before: "i"
1: b'%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:3: Cannot find include file: src/reg_file.v\n`include "src/reg_file.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155004694/sim,data/full_repos/permissive/155004694/src/reg_file.v\n             data/full_repos/permissive/155004694/sim,data/full_repos/permissive/155004694/src/reg_file.v.v\n             data/full_repos/permissive/155004694/sim,data/full_repos/permissive/155004694/src/reg_file.v.sv\n             src/reg_file.v\n             src/reg_file.v.v\n             src/reg_file.v.sv\n             obj_dir/src/reg_file.v\n             obj_dir/src/reg_file.v.v\n             obj_dir/src/reg_file.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/reg_file_sim.v:37: Unsupported: Ignoring delay on this delayed statement.\n        repeat(4) #10 clk = ~clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/reg_file_sim.v:39: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clk = ~clk;\n                ^\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:50: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:51: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:53: syntax error, unexpected \'@\'\n        @(posedge reset);\n        ^\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:72: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:79: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:91: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/reg_file_sim.v:92: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:97: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/reg_file_sim.v:98: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:108: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:115: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/reg_file_sim.v:117: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:127: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/reg_file_sim.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:136: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/reg_file_sim.v:137: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/reg_file_sim.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Error: data/full_repos/permissive/155004694/sim/reg_file_sim.v:149: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to 13 error(s), 8 warning(s)\n'
module reg_file_sim();

    reg clk = 'd0;
    reg reset = 'd1;

    reg [4:0] readA = 'd0;
    reg [4:0] readB = 'd0;

    reg writeEnC = 'd0;
    reg [4:0] writeC = 'd0;
    reg [31:0] writeDataC = 'd0;

    wire [31:0] A;
    wire [31:0] B;

    reg_file reg_file(
        .clk(clk),
        .reset(reset),
        .readA(readA),
        .readB(readB),
        .writeEnC(writeEnC),
        .writeC(writeC),
        .writeDataC(writeDataC),
        .A(A),
        .B(B)
    );

    initial begin
        clk = 1'b0;
        reset = 1'b0;
        repeat(4) #10 clk = ~clk;
        reset = 1'b1;
        forever #10 clk = ~clk;
    end

    initial begin

        int tests_passed;
        int tests_total;

        tests_passed = 0;
        tests_total = 0;

        $dumpfile("test.vcd");
        $dumpvars;

        @(posedge reset);

        readA = 'd0;
        readB = 'd0;

        `CHECK(A, 'd0);
        `CHECK(B, 'd0);

        for (int i = 1; i < 32; i++) begin
            readA = i;
            `CHECK(A, 'd0);
        end

        readA = 'd0;
        readB = 'd0;

        writeC = 'd1;
        writeDataC = 'hAC;

        @(posedge clk);

        readA = 'd1;
        `CHECK(A, 'd0);

        writeEnC = 'd1;

        @(posedge clk);

        readA = 'd1;
        `CHECK(A, 'hAC);


        for (int i = 2; i < 32; i++) begin
            writeEnC = 'd0;
            writeC = i;
            readA = i;
            readB = i;
            writeDataC = i + 7;
            @(posedge clk);
            #1
            `CHECK(A, 'd0);
            `CHECK(B, 'd0);
            
            writeEnC = 'd1;
            @(posedge clk);
            #1
            `CHECK(A, i + 7);
            `CHECK(B, i + 7);
        end

        writeEnC = 'd0;


        readA = 'd0;

        @(posedge clk);
        `CHECK(A, 'd0);

        writeDataC = 'h98;
        writeEnC = 'd1;
        writeC = 'd0;

        @(posedge clk);
        readA = 'd0;
        #1
        `CHECK(A, 'd0);

        readA = 'd0;
        readB = 'd0;

        writeDataC = 'h56;
        writeEnC = 'd1;
        writeC = 'd1;

        @(posedge clk);

        #1

        writeDataC = 'hC2;
        writeEnC = 'd1;
        writeC = 'd2;


        @(posedge clk);
        #1

        writeEnC = 'd0;

        readA = 'd1;
        readB = 'd2;
        
        #1

        `CHECK(A, 'h56);
        `CHECK(B, 'hC2);

        @(posedge clk);

        $display("%0d/%0d checks passed", tests_passed, tests_total);

        $finish;
    end

endmodule
module reg_file_sim();


    reg clk = 'd0;
    reg reset = 'd1;

    reg [4:0] readA = 'd0;
    reg [4:0] readB = 'd0;

    reg writeEnC = 'd0;
    reg [4:0] writeC = 'd0;
    reg [31:0] writeDataC = 'd0;

    wire [31:0] A;
    wire [31:0] B;

    reg_file reg_file(
        .clk(clk),
        .reset(reset),
        .readA(readA),
        .readB(readB),
        .writeEnC(writeEnC),
        .writeC(writeC),
        .writeDataC(writeDataC),
        .A(A),
        .B(B)
    );

    initial begin
        clk = 1'b0;
        reset = 1'b0;
        repeat(4) #10 clk = ~clk;
        reset = 1'b1;
        forever #10 clk = ~clk;
    end

    initial begin

        int tests_passed;
        int tests_total;

        tests_passed = 0;
        tests_total = 0;

        $dumpfile("test.vcd");
        $dumpvars;

        @(posedge reset);

        readA = 'd0;
        readB = 'd0;

        `CHECK(A, 'd0);
        `CHECK(B, 'd0);

        for (int i = 1; i < 32; i++) begin
            readA = i;
            `CHECK(A, 'd0);
        end

        readA = 'd0;
        readB = 'd0;

        writeC = 'd1;
        writeDataC = 'hAC;

        @(posedge clk);

        readA = 'd1;
        `CHECK(A, 'd0);

        writeEnC = 'd1;

        @(posedge clk);

        readA = 'd1;
        `CHECK(A, 'hAC);


        for (int i = 2; i < 32; i++) begin
            writeEnC = 'd0;
            writeC = i;
            readA = i;
            readB = i;
            writeDataC = i + 7;
            @(posedge clk);
            #1
            `CHECK(A, 'd0);
            `CHECK(B, 'd0);
            
            writeEnC = 'd1;
            @(posedge clk);
            #1
            `CHECK(A, i + 7);
            `CHECK(B, i + 7);
        end

        writeEnC = 'd0;


        readA = 'd0;

        @(posedge clk);
        `CHECK(A, 'd0);

        writeDataC = 'h98;
        writeEnC = 'd1;
        writeC = 'd0;

        @(posedge clk);
        readA = 'd0;
        #1
        `CHECK(A, 'd0);

        readA = 'd0;
        readB = 'd0;

        writeDataC = 'h56;
        writeEnC = 'd1;
        writeC = 'd1;

        @(posedge clk);

        #1

        writeDataC = 'hC2;
        writeEnC = 'd1;
        writeC = 'd2;


        @(posedge clk);
        #1

        writeEnC = 'd0;

        readA = 'd1;
        readB = 'd2;
        
        #1

        `CHECK(A, 'h56);
        `CHECK(B, 'hC2);

        @(posedge clk);

        $display("%0d/%0d checks passed", tests_passed, tests_total);

        $finish;
    end

endmodule