data/full_repos/permissive/193439230/sbox.v
data/verilator_xmls/9e770880-de7d-4db0-ab4b-be45e1c0d585.xml
module Top(g, m, d);
    input[7:0] g;
    input[9:0] m;
    output[3:0] d;
    wire t1,
        t2,
        t3,
        t4,
        t5,
        t6,
        t7,
        t8,
        t9,
        t10,
        t11,
        t12,
        t13,
        t14,
        t15,
        t16,
        t17,
        t18,
        t19,
        t20,
        t21,
        t22,
        t23,
        t24;
    NAND m1(t1, g[5], g[1]);
    NAND m2(t2, m[1], m[0]);
    NAND m3(t3, g[4], g[0]);
    NAND m4(t4, g[7], g[3]);
    NAND m5(t5, m[9], m[8]);
    NOR m6(t6, g[6], g[2]);
    NOR m7(t7, g[7], g[3]);
    NOR m8(t8, m[9], m[8]);
    NOR m9(t9, m[7], m[6]);
    NAND m10(t10, m[3], m[2]);
    NAND m11(t11, m[5], m[4]);
    NOR m12(t12, m[3], m[2]);
    XOR m13(t13, t1, t2);
    XOR m14(t14, t3, t2);
    XOR m15(t15, t4, t13);
    XOR m16(t16, t5, t14);
    XOR m17(t17, t9, t10);
    XOR m18(t18, t11, t12);
    XOR m19(t19, t6, t15);
    XOR m20(t20, t7, t16);
    XOR m21(t21, t19, t17);
    XOR m22(t22, t20, t18);
    XOR m23(t23, t8, t15);
    XOR m24(t24, t6, t16);
    assign d[3] = t21;
    assign d[2] = t22;
    assign d[1] = t23;
    assign d[0] = t24;
endmodule
module Top(g, m, d);

    input[7:0] g;
    input[9:0] m;
    output[3:0] d;
    wire t1,
        t2,
        t3,
        t4,
        t5,
        t6,
        t7,
        t8,
        t9,
        t10,
        t11,
        t12,
        t13,
        t14,
        t15,
        t16,
        t17,
        t18,
        t19,
        t20,
        t21,
        t22,
        t23,
        t24;
    NAND m1(t1, g[5], g[1]);
    NAND m2(t2, m[1], m[0]);
    NAND m3(t3, g[4], g[0]);
    NAND m4(t4, g[7], g[3]);
    NAND m5(t5, m[9], m[8]);
    NOR m6(t6, g[6], g[2]);
    NOR m7(t7, g[7], g[3]);
    NOR m8(t8, m[9], m[8]);
    NOR m9(t9, m[7], m[6]);
    NAND m10(t10, m[3], m[2]);
    NAND m11(t11, m[5], m[4]);
    NOR m12(t12, m[3], m[2]);
    XOR m13(t13, t1, t2);
    XOR m14(t14, t3, t2);
    XOR m15(t15, t4, t13);
    XOR m16(t16, t5, t14);
    XOR m17(t17, t9, t10);
    XOR m18(t18, t11, t12);
    XOR m19(t19, t6, t15);
    XOR m20(t20, t7, t16);
    XOR m21(t21, t19, t17);
    XOR m22(t22, t20, t18);
    XOR m23(t23, t8, t15);
    XOR m24(t24, t6, t16);
    assign d[3] = t21;
    assign d[2] = t22;
    assign d[1] = t23;
    assign d[0] = t24;
endmodule