data/full_repos/permissive/211471959/src/hdl/behavioural_example.v
data/verilator_xmls/915b4886-705e-4f40-9a1c-177fd7862f92.xml
module behavioural_example(
    input a,
    input b,
    input c,
    input d,
    output reg out
    );

    always @(a, b, c, d) begin
        out = ~(((a & b) | (~c)) & d);
    end
endmodule
module behavioural_example(
    input a,
    input b,
    input c,
    input d,
    output reg out
    );


    always @(a, b, c, d) begin
        out = ~(((a & b) | (~c)) & d);
    end
endmodule