data/full_repos/permissive/17894630/Single-Cycle/Core_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/17894630/Single-Cycle/Core_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #20  clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/17894630/Single-Cycle/Core_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n   #75\n   ^\n%Error: data/full_repos/permissive/17894630/Single-Cycle/Core_TB.v:28: Cannot find file containing module: \'Core\'\n  Core c (\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/17894630/Single-Cycle,data/full_repos/permissive/17894630/Core\n             data/full_repos/permissive/17894630/Single-Cycle,data/full_repos/permissive/17894630/Core.v\n             data/full_repos/permissive/17894630/Single-Cycle,data/full_repos/permissive/17894630/Core.sv\n             Core\n             Core.v\n             Core.sv\n             obj_dir/Core\n             obj_dir/Core.v\n             obj_dir/Core.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Core_TB(
    );
	 reg clk;
	 reg nrst;
	 reg[2:0] in;
	 wire[7:0] out;
	 Core c (
				clk,
				nrst,
				in,
				out
				);
		
		initial
		begin
			clk = 0;
			forever begin
				#20  clk = ~clk;
			end
		end
		
		initial
		begin
			in = 3'b010;
			nrst = 0;
			#75
			nrst = 1;
		end
	
endmodule
module Core_TB(
    );

	 reg clk;
	 reg nrst;
	 reg[2:0] in;
	 wire[7:0] out;
	 Core c (
				clk,
				nrst,
				in,
				out
				);
		
		initial
		begin
			clk = 0;
			forever begin
				#20  clk = ~clk;
			end
		end
		
		initial
		begin
			in = 3'b010;
			nrst = 0;
			#75
			nrst = 1;
		end
	
endmodule