data/full_repos/permissive/123984156/adder_tb.v
 line:70: before: "/"
1: b'%Warning-STMTDLY: data/full_repos/permissive/123984156/adder_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123984156/adder_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #32\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123984156/adder_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #32\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123984156/adder_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n#1 clk = ~clk;\n^\n%Error: data/full_repos/permissive/123984156/adder_tb.v:54: Cannot find file containing module: \'adder\'\nadder DUT (        \n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/123984156,data/full_repos/permissive/123984156/adder\n             data/full_repos/permissive/123984156,data/full_repos/permissive/123984156/adder.v\n             data/full_repos/permissive/123984156,data/full_repos/permissive/123984156/adder.sv\n             adder\n             adder.v\n             adder.sv\n             obj_dir/adder\n             obj_dir/adder.v\n             obj_dir/adder.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder_tb();

reg            clk;
reg            rst;
reg    [31:0]   input_a;
reg    [31:0]   input_b;
reg             input_a_stb;
reg             input_b_stb;
reg            output_z_ack;
wire            input_a_ack;
wire            input_b_ack;
wire            output_z_stb;
wire   [31:0]  output_z;
initial begin 
  clk = 1;
  rst = 1;
  input_a_stb = 0;  
  input_b_stb = 0;
  output_z_ack = 0;
  #10
  rst = 0;

  input_a_stb = 1;  
  input_b_stb = 1;
  output_z_ack = 1;

  input_a = 32'h3f800000;
  input_b = 32'h3f800000;
  #32














  input_a = 32'h3f000000;
  input_b = 32'h3f000000;
  #32
  input_a = 32'h3f000000;
  input_b = 32'hbf000000;
    
  
end

adder DUT (        
        input_a,
        input_b,
        input_a_stb,
        input_b_stb,
        output_z_ack,
        clk,
        rst,
        output_z,
        output_z_stb,
        input_a_ack,
        input_b_ack);

always 
#1 clk = ~clk;

endmodule
module adder_tb();


reg            clk;
reg            rst;
reg    [31:0]   input_a;
reg    [31:0]   input_b;
reg             input_a_stb;
reg             input_b_stb;
reg            output_z_ack;
wire            input_a_ack;
wire            input_b_ack;
wire            output_z_stb;
wire   [31:0]  output_z;
initial begin 
  clk = 1;
  rst = 1;
  input_a_stb = 0;  
  input_b_stb = 0;
  output_z_ack = 0;
  #10
  rst = 0;

  input_a_stb = 1;  
  input_b_stb = 1;
  output_z_ack = 1;

  input_a = 32'h3f800000;
  input_b = 32'h3f800000;
  #32














  input_a = 32'h3f000000;
  input_b = 32'h3f000000;
  #32
  input_a = 32'h3f000000;
  input_b = 32'hbf000000;
    
  
end

adder DUT (        
        input_a,
        input_b,
        input_a_stb,
        input_b_stb,
        output_z_ack,
        clk,
        rst,
        output_z,
        output_z_stb,
        input_a_ack,
        input_b_ack);

always 
#1 clk = ~clk;

endmodule