data/full_repos/permissive/169738435/Cells/fdm.v
data/verilator_xmls/4e02b387-91b4-4884-98de-503be025bde1.xml
module FDM(
	input CK,
	input D,
	output reg Q,
	output nQ
);

	initial
		Q <= 1'b0;

	always @(posedge CK)
		Q <= #2 D;
	
	assign nQ = ~Q;

endmodule
module FDM(
	input CK,
	input D,
	output reg Q,
	output nQ
);


	initial
		Q <= 1'b0;

	always @(posedge CK)
		Q <= #2 D;
	
	assign nQ = ~Q;

endmodule