data/full_repos/permissive/166023910/adders_8/source_v/add8_161.v
data/verilator_xmls/c6c98664-0fd1-4bae-bef3-fb28c54df6c3.xml
module PDKGENNAND3X1(input A, input B, input C, output Y );
     assign Y = ~((A & B) & C);
endmodule
module PDKGENNAND3X1(input A, input B, input C, output Y );

     assign Y = ~((A & B) & C);
endmodule