data/full_repos/permissive/175393019/rtl/xprog.v
1: b'%Error: data/full_repos/permissive/175393019/rtl/xprog.v:2: Cannot find include file: xdefs.vh\n`include "xdefs.vh"\n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175393019/rtl,data/full_repos/permissive/175393019/xdefs.vh\n             data/full_repos/permissive/175393019/rtl,data/full_repos/permissive/175393019/xdefs.vh.v\n             data/full_repos/permissive/175393019/rtl,data/full_repos/permissive/175393019/xdefs.vh.sv\n             xdefs.vh\n             xdefs.vh.v\n             xdefs.vh.sv\n             obj_dir/xdefs.vh\n             obj_dir/xdefs.vh.v\n             obj_dir/xdefs.vh.sv\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:3: Cannot find include file: xctrldefs.vh\n`include "xctrldefs.vh"\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:4: Cannot find include file: xprogdefs.vh\n`include "xprogdefs.vh"\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:12: Define or directive not defined: \'`PROG_RAM_ADDR_W\'\n       input [`PROG_RAM_ADDR_W-1:0] data_addr,\n              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:13: Define or directive not defined: \'`DATA_W\'\n       input [`DATA_W-1:0]     data_in,\n              ^~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:14: Define or directive not defined: \'`DATA_W\'\n       output [`DATA_W-1:0]     data_out,\n               ^~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:27: Define or directive not defined: \'`PROG_ADDR_W\'\n       input [`PROG_ADDR_W-1:0]     pc,\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:28: Define or directive not defined: \'`INSTR_W\'\n       output reg [`INSTR_W-1:0]    instruction\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:32: Define or directive not defined: \'`INSTR_W\'\n   wire [`INSTR_W-1:0]       data_from_rom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:35: Define or directive not defined: \'`INSTR_W\'\n   wire [`INSTR_W-1:0]       data_from_ram;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:45: Define or directive not defined: \'`PROG_ADDR_W\'\n      if ( ~pc[`PROG_ADDR_W-1] ) begin\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:57: Define or directive not defined: \'`PROG_ROM_ADDR_W\'\n   .pc(pc[`PROG_ROM_ADDR_W-1:0]),\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:64: Define or directive not defined: \'`PROG_RAM_ADDR_W\'\n   .pc(pc[`PROG_RAM_ADDR_W-1:0]),\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xprog.v:70: Define or directive not defined: \'`PROG_RAM_ADDR_W\'\n   .data_addr(data_addr[`PROG_RAM_ADDR_W-1:0]),\n                        ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module xprog (
	      input 			   clk,


	      input 			   data_sel,
	      input 			   data_we,
	      input [`PROG_RAM_ADDR_W-1:0] data_addr,
	      input [`DATA_W-1:0] 	   data_in,
	      output [`DATA_W-1:0] 	   data_out,
			output reg ram_led,
					
`ifdef DMA_USE

	      input 			   dma_sel,
	      input 			   dma_we,
	      input [`PROG_ADDR_W-1:0] 	   dma_addr,
	      input [`DATA_W-1:0] 	   dma_data_in,
	      output [`DATA_W-1:0] 	   dma_data_out
`endif


	      input [`PROG_ADDR_W-1:0] 	   pc,
	      output reg [`INSTR_W-1:0]    instruction
	      );
   

   wire [`INSTR_W-1:0] 			   data_from_rom;


   wire [`INSTR_W-1:0] 			   data_from_ram;

`ifdef DMA_USE
   wire 				   dma_we_int;
   assign dma_we_int = dma_sel & dma_we;
`endif

      

   always @ * 
      if ( ~pc[`PROG_ADDR_W-1] ) begin
	instruction= data_from_rom;
	ram_led <=0;
	end
      else
		begin
		ram_led<=1;
	instruction = data_from_ram;
		end

   xprog_rom rom(
		 .clk(clk),
		 .pc(pc[`PROG_ROM_ADDR_W-1:0]),
		 .instruction(data_from_rom)
		 );


   xprog_ram ram(

		 .pc(pc[`PROG_RAM_ADDR_W-1:0]),
		 .instruction(data_from_ram),
		 

		 .data_sel(data_sel),
		 .data_we(data_we),
		 .data_addr(data_addr[`PROG_RAM_ADDR_W-1:0]),
		 .data_in(data_in),
		 .data_out(data_out),
		 
`ifdef DMA_USE
		 .dma_addr(dma_addr),
		 .dma_data_in(dma_data_in),
		 .dma_data_out(dma_data_out)
`endif
		 .clk(clk)
		 );

endmodule
module xprog (
	      input 			   clk,


	      input 			   data_sel,
	      input 			   data_we,
	      input [`PROG_RAM_ADDR_W-1:0] data_addr,
	      input [`DATA_W-1:0] 	   data_in,
	      output [`DATA_W-1:0] 	   data_out,
			output reg ram_led,
					
`ifdef DMA_USE

	      input 			   dma_sel,
	      input 			   dma_we,
	      input [`PROG_ADDR_W-1:0] 	   dma_addr,
	      input [`DATA_W-1:0] 	   dma_data_in,
	      output [`DATA_W-1:0] 	   dma_data_out
`endif


	      input [`PROG_ADDR_W-1:0] 	   pc,
	      output reg [`INSTR_W-1:0]    instruction
	      );

   

   wire [`INSTR_W-1:0] 			   data_from_rom;


   wire [`INSTR_W-1:0] 			   data_from_ram;

`ifdef DMA_USE
   wire 				   dma_we_int;
   assign dma_we_int = dma_sel & dma_we;
`endif

      

   always @ * 
      if ( ~pc[`PROG_ADDR_W-1] ) begin
	instruction= data_from_rom;
	ram_led <=0;
	end
      else
		begin
		ram_led<=1;
	instruction = data_from_ram;
		end

   xprog_rom rom(
		 .clk(clk),
		 .pc(pc[`PROG_ROM_ADDR_W-1:0]),
		 .instruction(data_from_rom)
		 );


   xprog_ram ram(

		 .pc(pc[`PROG_RAM_ADDR_W-1:0]),
		 .instruction(data_from_ram),
		 

		 .data_sel(data_sel),
		 .data_we(data_we),
		 .data_addr(data_addr[`PROG_RAM_ADDR_W-1:0]),
		 .data_in(data_in),
		 .data_out(data_out),
		 
`ifdef DMA_USE
		 .dma_addr(dma_addr),
		 .dma_data_in(dma_data_in),
		 .dma_data_out(dma_data_out)
`endif
		 .clk(clk)
		 );

endmodule