data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v
 line:100: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n             ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n            ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n                ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n                                                                                              : ... In instance multicpu.alu\n   zero = ALUResult ? 0 : 1;\n                    ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pc(
     input clk, rst, PCWre,
	input [1:0] PCSrc,
	input [31:0] immediate, readData1, addr,
	output reg[31:0] pcout
    );
	initial begin
		pcout = 0;
	end
	always@(negedge clk or negedge rst) begin
		if (rst == 0) begin
			pcout = 0;
		end else if (PCWre) begin
			if (PCSrc == 2'b00) begin
				pcout = pcout + 4;
			end else if (PCSrc == 2'b01) begin
				pcout = pcout + 4 + immediate * 4;
			end else if (PCSrc == 2'b10) begin
				pcout = readData1;
			end else if (PCSrc == 2'b11) begin
				pcout = addr;
			end
		end
	end
endmodule
module pc(
     input clk, rst, PCWre,
	input [1:0] PCSrc,
	input [31:0] immediate, readData1, addr,
	output reg[31:0] pcout
    );

	initial begin
		pcout = 0;
	end
	always@(negedge clk or negedge rst) begin
		if (rst == 0) begin
			pcout = 0;
		end else if (PCWre) begin
			if (PCSrc == 2'b00) begin
				pcout = pcout + 4;
			end else if (PCSrc == 2'b01) begin
				pcout = pcout + 4 + immediate * 4;
			end else if (PCSrc == 2'b10) begin
				pcout = readData1;
			end else if (PCSrc == 2'b11) begin
				pcout = addr;
			end
		end
	end
endmodule