data/full_repos/permissive/128100618/SV/FP_operations_design.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/128100618/SV/FP_operations_design.v:280: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'DE2_Top\'\nmodule DE2_Top (\n       ^~~~~~~\n                                                                                     : ... Top module \'fpneg\'\nmodule fpneg(fout, f1) ;\n       ^~~~~\n                                                                                     : ... Top module \'int2fp\'\nmodule int2fp(fp_out, int_in, scale_in) ;\n       ^~~~~~\n                                                                                     : ... Top module \'fp2int\'\nmodule fp2int(int_out, fp_in, scale_in) ;\n       ^~~~~~\n                                                                                     : ... Top module \'fpinv\'\nmodule fpinv (fout, f1);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FP_operations_design.v:263: Input port connection \'num\' expects 4 bits on the pin connection, but pin connection\'s SEL generates 1 bits.\n                                                                                  : ... In instance DE2_Top\n HexDigit d2(HEX2, disp[8]);\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FP_operations_design.v:619: Operator SHIFTR expects 10 bits on the LHS, but LHS\'s VARREF \'m_in\' generates 9 bits.\n                                                                                  : ... In instance fp2int\n assign abs_int = (e_in>8\'h80)? (m_in >> (8\'h89 - e_in)) : 10\'d0 ;\n                                      ^~\n%Error: Exiting due to 3 warning(s)\n'
module fpadd (fout, f1, f2);

	input [17:0] f1, f2 ;
	output [17:0] fout ;
	
	wire  [17:0] fout ;
	wire sout ;
	reg [8:0] mout ;
	reg [7:0] eout ;
	reg [9:0] shift_small, denorm_mout ;
	
	wire s1, s2 ;
	reg  sb, ss ;
	wire [8:0] m1, m2 ;
	reg  [8:0] mb, ms ;
	wire [7:0] e1, e2 ;
	wire [7:0] ediff ;
	reg  [7:0] eb, es ;
	reg  [7:0] num_zeros ;
	

	assign s1 = f1[17];
	assign e1 = f1[16:9];
	assign m1 = f1[8:0] ;

	assign s2 = f2[17];
	assign e2 = f2[16:9];
	assign m2 = f2[8:0] ;
	

	always @(*)
	begin
		if (e1>e2)
		begin
			sb = s1 ;
			eb = e1 ;
			mb = m1 ;
			ss = s2 ;
			es = e2 ;
			ms = m2 ;
		end
		else if (e2>e1)
		begin
			sb = s2 ;
			eb = e2 ;
			mb = m2 ;
			ss = s1 ;
			es = e1 ;
			ms = m1 ;
		end
		else
		begin
			if (m1>m2)
			begin
				sb = s1 ;
				eb = e1 ;
				mb = m1 ;
				ss = s2 ;
				es = e2 ;
				ms = m2 ;
			end
			else
			begin
				sb = s2 ;
				eb = e2 ;
				mb = m2 ;
				ss = s1 ;
				es = e1 ;
				ms = m1 ;
			end
		end
	end
	

	assign sout = sb ;

	assign fout = {sout, eout, mout} ;	
	




	assign ediff = eb - es ;
	always @(*)
	begin
		if ((ms[8]==0) && (mb[8]==0))
		begin
			mout = 9'b0 ;
			eout = 8'b0 ; 
		end
		else if ((ms[8]==0) || ediff>8)
		begin
			mout = mb ;
			eout = eb ;
		end
		else
		begin


			shift_small = {1'b0, ms} >> ediff ;

			if (sb==ss)
			begin
				denorm_mout = {1'b0, mb} + shift_small ;


				if (denorm_mout[9]==1)
				begin
					mout = denorm_mout[9:1] ;
					eout = eb + 1 ;
				end
				else
				begin
					mout = denorm_mout[8:0] ;
					eout = eb ;
				end
			end
			else
			begin
				denorm_mout = {1'b0, mb} - shift_small ;




				if (denorm_mout[8:0]==9'd0)
				begin
					mout = 9'b0 ;
					eout = 8'b0 ;
				end
				else
				begin

					casex (denorm_mout[8:0])
						9'b1xxxxxxxx: num_zeros = 8'd0 ;
						9'b01xxxxxxx: num_zeros = 8'd1 ;
						9'b001xxxxxx: num_zeros = 8'd2 ;
						9'b0001xxxxx: num_zeros = 8'd3 ;
						9'b00001xxxx: num_zeros = 8'd4 ;
						9'b000001xxx: num_zeros = 8'd5 ;
						9'b0000001xx: num_zeros = 8'd6 ;
						9'b00000001x: num_zeros = 8'd7 ;
						9'b000000001: num_zeros = 8'd8 ;
						default:       num_zeros = 8'd9 ;
					endcase	


					eout = eb - num_zeros ;
					mout = denorm_mout[8:0] << num_zeros ;
				end
			end


		end
	end
endmodule
module fpadd (fout, f1, f2);


	input [17:0] f1, f2 ;
	output [17:0] fout ;
	
	wire  [17:0] fout ;
	wire sout ;
	reg [8:0] mout ;
	reg [7:0] eout ;
	reg [9:0] shift_small, denorm_mout ;
	
	wire s1, s2 ;
	reg  sb, ss ;
	wire [8:0] m1, m2 ;
	reg  [8:0] mb, ms ;
	wire [7:0] e1, e2 ;
	wire [7:0] ediff ;
	reg  [7:0] eb, es ;
	reg  [7:0] num_zeros ;
	

	assign s1 = f1[17];
	assign e1 = f1[16:9];
	assign m1 = f1[8:0] ;

	assign s2 = f2[17];
	assign e2 = f2[16:9];
	assign m2 = f2[8:0] ;
	

	always @(*)
	begin
		if (e1>e2)
		begin
			sb = s1 ;
			eb = e1 ;
			mb = m1 ;
			ss = s2 ;
			es = e2 ;
			ms = m2 ;
		end
		else if (e2>e1)
		begin
			sb = s2 ;
			eb = e2 ;
			mb = m2 ;
			ss = s1 ;
			es = e1 ;
			ms = m1 ;
		end
		else
		begin
			if (m1>m2)
			begin
				sb = s1 ;
				eb = e1 ;
				mb = m1 ;
				ss = s2 ;
				es = e2 ;
				ms = m2 ;
			end
			else
			begin
				sb = s2 ;
				eb = e2 ;
				mb = m2 ;
				ss = s1 ;
				es = e1 ;
				ms = m1 ;
			end
		end
	end
	

	assign sout = sb ;

	assign fout = {sout, eout, mout} ;	
	




	assign ediff = eb - es ;
	always @(*)
	begin
		if ((ms[8]==0) && (mb[8]==0))
		begin
			mout = 9'b0 ;
			eout = 8'b0 ; 
		end
		else if ((ms[8]==0) || ediff>8)
		begin
			mout = mb ;
			eout = eb ;
		end
		else
		begin


			shift_small = {1'b0, ms} >> ediff ;

			if (sb==ss)
			begin
				denorm_mout = {1'b0, mb} + shift_small ;


				if (denorm_mout[9]==1)
				begin
					mout = denorm_mout[9:1] ;
					eout = eb + 1 ;
				end
				else
				begin
					mout = denorm_mout[8:0] ;
					eout = eb ;
				end
			end
			else
			begin
				denorm_mout = {1'b0, mb} - shift_small ;




				if (denorm_mout[8:0]==9'd0)
				begin
					mout = 9'b0 ;
					eout = 8'b0 ;
				end
				else
				begin

					casex (denorm_mout[8:0])
						9'b1xxxxxxxx: num_zeros = 8'd0 ;
						9'b01xxxxxxx: num_zeros = 8'd1 ;
						9'b001xxxxxx: num_zeros = 8'd2 ;
						9'b0001xxxxx: num_zeros = 8'd3 ;
						9'b00001xxxx: num_zeros = 8'd4 ;
						9'b000001xxx: num_zeros = 8'd5 ;
						9'b0000001xx: num_zeros = 8'd6 ;
						9'b00000001x: num_zeros = 8'd7 ;
						9'b000000001: num_zeros = 8'd8 ;
						default:       num_zeros = 8'd9 ;
					endcase	


					eout = eb - num_zeros ;
					mout = denorm_mout[8:0] << num_zeros ;
				end
			end


		end
	end
endmodule