data/full_repos/permissive/20726090/hw/vlog/lib/xs6_sram_256x128_byte_en.v
 line:119: before: "lk"
1: b"%Error: data/full_repos/permissive/20726090/hw/vlog/lib/xs6_sram_256x128_byte_en.v:67: Cannot find file containing module: 'RAMB8BWER'\n        RAMB8BWER #(\n        ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20726090/hw/vlog/lib,data/full_repos/permissive/20726090/RAMB8BWER\n             data/full_repos/permissive/20726090/hw/vlog/lib,data/full_repos/permissive/20726090/RAMB8BWER.v\n             data/full_repos/permissive/20726090/hw/vlog/lib,data/full_repos/permissive/20726090/RAMB8BWER.sv\n             RAMB8BWER\n             RAMB8BWER.v\n             RAMB8BWER.sv\n             obj_dir/RAMB8BWER\n             obj_dir/RAMB8BWER.v\n             obj_dir/RAMB8BWER.sv\n%Error: Exiting due to 1 error(s)\n"
module xs6_sram_256x128_byte_en 

#(
parameter DATA_WIDTH    = 128,
parameter ADDRESS_WIDTH = 8
)

(
input                           i_clk,
input      [DATA_WIDTH-1:0]     i_write_data,
input                           i_write_enable,
input      [ADDRESS_WIDTH-1:0]  i_address,
input      [DATA_WIDTH/8-1:0]   i_byte_enable,
output     [DATA_WIDTH-1:0]     o_read_data

);

genvar      i;
wire [DATA_WIDTH/8-1:0] byte_write_enable;

assign byte_write_enable = {DATA_WIDTH/8{i_write_enable}} & i_byte_enable;


generate
    for (i=0;i<4;i=i+1) begin : u_gen
        RAMB8BWER #(
            .DATA_WIDTH_A        ( 36                        ),
            .DATA_WIDTH_B        ( 36                        ),
            .RAM_MODE            ( "SDP"                     ),
            .SIM_COLLISION_CHECK ( "GENERATE_X_ONLY"         ),
            .WRITE_MODE_A        ( "READ_FIRST"              ),
            .WRITE_MODE_B        ( "READ_FIRST"              )
         ) 
        u_ramb8bwer (
            .CLKAWRCLK      ( i_clk                          ),     
            .CLKBRDCLK      ( i_clk                          ),
            .ADDRAWRADDR    ( {i_address, 5'd0}              ),
            .ADDRBRDADDR    ( {i_address, 5'd0}              ),
            .ENAWREN        ( i_write_enable                 ),       
            .ENBRDEN        ( ~i_write_enable                ),
            

            .WEAWEL         ( byte_write_enable[4*i+1:4*i+0] ),  
            .DIADI          ( i_write_data[32*i+15:32*i+ 0]  ), 
            .DOADO          ( o_read_data [32*i+15:32*i+ 0]  ),
            

            .WEBWEU         ( byte_write_enable[4*i+3:4*i+2] ),
            .DIBDI          ( i_write_data[32*i+31:32*i+16]  ),
            .DOBDO          ( o_read_data [32*i+31:32*i+16]  ),



            .DIPBDIP        ( 2'd0                           ),
            .DIPADIP        ( 2'd0                           ),      
            .DOPADOP        (                                ),
            .DOPBDOP        (                                ),
          
            .REGCEA         ( 1'd0                           ),
            .REGCEBREGCE    ( 1'd0                           ),
            .RSTA           ( 1'd0                           ),
            .RSTBRST        ( 1'd0                           )
        );

    end
endgenerate


initial
    begin
    if ( DATA_WIDTH    != 128 ) $display("%M Warning: Incorrect parameter DATA_WIDTH");
    if ( ADDRESS_WIDTH != 8   ) $display("%M Warning: Incorrect parameter ADDRESS_WIDTH");
    end


endmodule
module xs6_sram_256x128_byte_en 

#(
parameter DATA_WIDTH    = 128,
parameter ADDRESS_WIDTH = 8
)

(
input                           i_clk,
input      [DATA_WIDTH-1:0]     i_write_data,
input                           i_write_enable,
input      [ADDRESS_WIDTH-1:0]  i_address,
input      [DATA_WIDTH/8-1:0]   i_byte_enable,
output     [DATA_WIDTH-1:0]     o_read_data

);


genvar      i;
wire [DATA_WIDTH/8-1:0] byte_write_enable;

assign byte_write_enable = {DATA_WIDTH/8{i_write_enable}} & i_byte_enable;


generate
    for (i=0;i<4;i=i+1) begin : u_gen
        RAMB8BWER #(
            .DATA_WIDTH_A        ( 36                        ),
            .DATA_WIDTH_B        ( 36                        ),
            .RAM_MODE            ( "SDP"                     ),
            .SIM_COLLISION_CHECK ( "GENERATE_X_ONLY"         ),
            .WRITE_MODE_A        ( "READ_FIRST"              ),
            .WRITE_MODE_B        ( "READ_FIRST"              )
         ) 
        u_ramb8bwer (
            .CLKAWRCLK      ( i_clk                          ),     
            .CLKBRDCLK      ( i_clk                          ),
            .ADDRAWRADDR    ( {i_address, 5'd0}              ),
            .ADDRBRDADDR    ( {i_address, 5'd0}              ),
            .ENAWREN        ( i_write_enable                 ),       
            .ENBRDEN        ( ~i_write_enable                ),
            

            .WEAWEL         ( byte_write_enable[4*i+1:4*i+0] ),  
            .DIADI          ( i_write_data[32*i+15:32*i+ 0]  ), 
            .DOADO          ( o_read_data [32*i+15:32*i+ 0]  ),
            

            .WEBWEU         ( byte_write_enable[4*i+3:4*i+2] ),
            .DIBDI          ( i_write_data[32*i+31:32*i+16]  ),
            .DOBDO          ( o_read_data [32*i+31:32*i+16]  ),



            .DIPBDIP        ( 2'd0                           ),
            .DIPADIP        ( 2'd0                           ),      
            .DOPADOP        (                                ),
            .DOPBDOP        (                                ),
          
            .REGCEA         ( 1'd0                           ),
            .REGCEBREGCE    ( 1'd0                           ),
            .RSTA           ( 1'd0                           ),
            .RSTBRST        ( 1'd0                           )
        );

    end
endgenerate


initial
    begin
    if ( DATA_WIDTH    != 128 ) $display("%M Warning: Incorrect parameter DATA_WIDTH");
    if ( ADDRESS_WIDTH != 8   ) $display("%M Warning: Incorrect parameter ADDRESS_WIDTH");
    end


endmodule