data/full_repos/permissive/159954591/rtl/deltaSigmaADC.v
1: b'%Warning-WIDTH: data/full_repos/permissive/159954591/rtl/deltaSigmaADC.v:49: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'delta\' generates 1 bits.\n                                                                           : ... In instance deltaSigmaADC\n              sigma <= sigma[9:0] + delta;\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module deltaSigmaADC (
    input           i_clk,
    input           i_rst_n,
    input           i_cmpans,
    output          o_cmpdac,
    output  [9:0]   o_adc_dt,
    output          o_adc_dt_en
    );
    
    reg             delta;
    reg     [9:0]   adc_dt;
    reg     [9:0]   sigma_cnt;
    reg     [9:0]   sigma;
    reg             data_en;
    

    always @(posedge i_clk or negedge i_rst_n) begin
        if (~i_rst_n) begin
            delta <= 1'b0;
        end else begin
            delta <= i_cmpans;
        end
    end
    assign o_cmpdac = delta;
    

    always @(posedge i_clk or negedge i_rst_n) begin
        if (~i_rst_n) begin
            adc_dt <= 10'd0;
            sigma_cnt <= 10'd0;
            sigma <= 10'd0;
            data_en <= 1'b0;
        end else begin
            sigma_cnt <= sigma_cnt + 10'd1;
            if (sigma_cnt == 10'd1023) begin
                adc_dt <= sigma;
                data_en <= 1'b1;
                sigma <= 10'd0;
            end else begin
              sigma <= sigma[9:0] + delta;
              data_en <= 1'b0;
            end
        end
    end
    assign o_adc_dt = adc_dt;
    assign o_adc_dt_en = data_en;

endmodule
module deltaSigmaADC (
    input           i_clk,
    input           i_rst_n,
    input           i_cmpans,
    output          o_cmpdac,
    output  [9:0]   o_adc_dt,
    output          o_adc_dt_en
    );

    
    reg             delta;
    reg     [9:0]   adc_dt;
    reg     [9:0]   sigma_cnt;
    reg     [9:0]   sigma;
    reg             data_en;
    

    always @(posedge i_clk or negedge i_rst_n) begin
        if (~i_rst_n) begin
            delta <= 1'b0;
        end else begin
            delta <= i_cmpans;
        end
    end
    assign o_cmpdac = delta;
    

    always @(posedge i_clk or negedge i_rst_n) begin
        if (~i_rst_n) begin
            adc_dt <= 10'd0;
            sigma_cnt <= 10'd0;
            sigma <= 10'd0;
            data_en <= 1'b0;
        end else begin
            sigma_cnt <= sigma_cnt + 10'd1;
            if (sigma_cnt == 10'd1023) begin
                adc_dt <= sigma;
                data_en <= 1'b1;
                sigma <= 10'd0;
            end else begin
              sigma <= sigma[9:0] + delta;
              data_en <= 1'b0;
            end
        end
    end
    assign o_adc_dt = adc_dt;
    assign o_adc_dt_en = data_en;

endmodule