data/full_repos/permissive/201025648/Verilog/3.12.v
 line:7: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/201025648/Verilog/3.12.v:5: Unsupported: Ignoring delay on this delayed statement.\n #10 clock=~clock;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/201025648/Verilog/3.12.v:7: Unsupported: Ignoring delay on this delayed statement.\n #1000 $finish;\n ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock_gen(output reg clock);
initial
	clock=1'b0;
always
	#10 clock=~clock;
initial
	#1000 $finish;
endmodule
module clock_gen(output reg clock);

initial
	clock=1'b0;
always
	#10 clock=~clock;
initial
	#1000 $finish;
endmodule