data/full_repos/permissive/136422019/src/booth32.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136422019/src/booth32.v:14: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                     : ... In instance booth32\n  product[64:33] = 4\'b0;  \n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module booth32(
	output wire [64:1] data_out,
	input wire [31:0] a, b
	);
	
	reg [64:0] product;
	initial product <= 0;
	assign data_out[64:1] = product[64:1];
	
	integer i;

	always @(*) begin
		product[0] = 0;
		product[64:33] = 4'b0;
		product[32:1] = a;

		for(i = 0; i < 32; i = i + 1) begin
			if (product[1] == 0 && product[0] == 1) begin
			product[64:33] = product[64:33] + b;
			end
			else if (product[1] == 1 && product[0] == 0) begin
					product[64:33] = product[64:33] - b;
			end
			product = product >> 1;
			product[64] = product[63];
		end
	end
endmodule
module booth32(
	output wire [64:1] data_out,
	input wire [31:0] a, b
	);

	
	reg [64:0] product;
	initial product <= 0;
	assign data_out[64:1] = product[64:1];
	
	integer i;

	always @(*) begin
		product[0] = 0;
		product[64:33] = 4'b0;
		product[32:1] = a;

		for(i = 0; i < 32; i = i + 1) begin
			if (product[1] == 0 && product[0] == 1) begin
			product[64:33] = product[64:33] + b;
			end
			else if (product[1] == 1 && product[0] == 0) begin
					product[64:33] = product[64:33] - b;
			end
			product = product >> 1;
			product[64] = product[63];
		end
	end
endmodule