data/full_repos/permissive/162924824/test2/comun/update.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/458b8955-320a-4b20-b189-cd0ca57e1249.xml
module update (
  input wire clk,
  input wire vsync,
  output reg [10:0] posx,
  output reg [10:0] posy
  );
  
  parameter
    XMAX = 11'd640,
    YMAX = 11'd480,
    TAM  = 11'd64;
    
  initial begin
    posx = 11'd320;
    posy = 11'd240;
  end
  
  reg vsync_prev = 1'b0;
  reg dx = 1'b0;
  reg dy = 1'b0;
  
  always @(posedge clk)
    vsync_prev <= vsync;    
  wire actualizar_ahora = vsync_prev & ~vsync;
  
  always @(posedge clk) begin
    if (actualizar_ahora == 1'b1) begin
      if (posx == XMAX-TAM && dx == 1'b0 || posx == 11'd1 && dx == 1'b1)
        dx <= ~dx;
      if (posy == YMAX-TAM && dy == 1'b0 || posy == 11'd1 && dy == 1'b1)
        dy <= ~dy;
      posx <= posx + {{10{dx}}, 1'b1};
      posy <= posy + {{10{dy}}, 1'b1};
    end
  end
endmodule
module update (
  input wire clk,
  input wire vsync,
  output reg [10:0] posx,
  output reg [10:0] posy
  );

  
  parameter
    XMAX = 11'd640,
    YMAX = 11'd480,
    TAM  = 11'd64;
    
  initial begin
    posx = 11'd320;
    posy = 11'd240;
  end
  
  reg vsync_prev = 1'b0;
  reg dx = 1'b0;
  reg dy = 1'b0;
  
  always @(posedge clk)
    vsync_prev <= vsync;    
  wire actualizar_ahora = vsync_prev & ~vsync;
  
  always @(posedge clk) begin
    if (actualizar_ahora == 1'b1) begin
      if (posx == XMAX-TAM && dx == 1'b0 || posx == 11'd1 && dx == 1'b1)
        dx <= ~dx;
      if (posy == YMAX-TAM && dy == 1'b0 || posy == 11'd1 && dy == 1'b1)
        dy <= ~dy;
      posx <= posx + {{10{dx}}, 1'b1};
      posy <= posy + {{10{dy}}, 1'b1};
    end
  end
endmodule