data/full_repos/permissive/118895561/Project 3/ledctrl.v
1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/3,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/3,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/3,data/full_repos/permissive/118895561.sv\n             3,data/full_repos/permissive/118895561\n             3,data/full_repos/permissive/118895561.v\n             3,data/full_repos/permissive/118895561.sv\n             obj_dir/3,data/full_repos/permissive/118895561\n             obj_dir/3,data/full_repos/permissive/118895561.v\n             obj_dir/3,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 3/ledctrl.v\n%Error: Exiting due to 3 error(s)\n'
module ledctrl2(
    input clk,
	 input reset,
    input [3:0] digit,
    output digital_tube_sel2,
    output [7:0] digital_tube2
    );
	
	wire [3:0] Data;
	

	
	assign Data = digit;
											 
	assign digital_tube_sel2 = 1;
	
	assign digital_tube2[7] = 1;
	
	assign digital_tube2[6:0] = (Data == 4'h0) ? 7'b0000001 :
										 (Data == 4'h1) ? 7'b1001111 :
										 (Data == 4'h2) ? 7'b0010010 :
										 (Data == 4'h3) ? 7'b0000110 :
										 (Data == 4'h4) ? 7'b1001100 :
										 (Data == 4'h5) ? 7'b0100100 :
										 (Data == 4'h6) ? 7'b0100000 :
										 (Data == 4'h7) ? 7'b0001111 :
										 (Data == 4'h8) ? 7'b0000000 :
										 (Data == 4'h9) ? 7'b0000100 :
										 (Data == 4'ha) ? 7'b0001000 :
										 (Data == 4'hb) ? 7'b1100000 :
										 (Data == 4'hc) ? 7'b0110001 :
										 (Data == 4'hd) ? 7'b1000010 :
										 (Data == 4'he) ? 7'b0110000 :
										 (Data == 4'hf) ? 7'b0111000 :
																 7'b1111110 ;

endmodule
module ledctrl2(
    input clk,
	 input reset,
    input [3:0] digit,
    output digital_tube_sel2,
    output [7:0] digital_tube2
    );

	
	wire [3:0] Data;
	

	
	assign Data = digit;
											 
	assign digital_tube_sel2 = 1;
	
	assign digital_tube2[7] = 1;
	
	assign digital_tube2[6:0] = (Data == 4'h0) ? 7'b0000001 :
										 (Data == 4'h1) ? 7'b1001111 :
										 (Data == 4'h2) ? 7'b0010010 :
										 (Data == 4'h3) ? 7'b0000110 :
										 (Data == 4'h4) ? 7'b1001100 :
										 (Data == 4'h5) ? 7'b0100100 :
										 (Data == 4'h6) ? 7'b0100000 :
										 (Data == 4'h7) ? 7'b0001111 :
										 (Data == 4'h8) ? 7'b0000000 :
										 (Data == 4'h9) ? 7'b0000100 :
										 (Data == 4'ha) ? 7'b0001000 :
										 (Data == 4'hb) ? 7'b1100000 :
										 (Data == 4'hc) ? 7'b0110001 :
										 (Data == 4'hd) ? 7'b1000010 :
										 (Data == 4'he) ? 7'b0110000 :
										 (Data == 4'hf) ? 7'b0111000 :
																 7'b1111110 ;

endmodule