data/full_repos/permissive/120024308/tests/leds/test_leds.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/120024308/tests/leds/test_leds.v:20: Unsupported: Ignoring delay on this delayed statement.\n #1  clk =  ! clk; \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/120024308/tests/leds/test_leds.v:24: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("test_leds.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/120024308/tests/leds/test_leds.v:25: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, test_leds);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/120024308/tests/leds/test_leds.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #2;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/120024308/tests/leds/test_leds.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #50;      \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/120024308/tests/leds/test_leds.v:36: Unsupported: Ignoring delay on this delayed statement.\n      # 5000000 reset = 1;\n      ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_leds;
   

   reg clk;
   reg reset;
   wire [7:0] led;
   
   
   
   Core uut(
	    .Clock(clk),
	    .Reset(reset),
	    .Led(led)
	    );
   
   always
     begin
	#1  clk =  ! clk;	
     end
   
   initial begin
      $dumpfile("test_leds.vcd");
      $dumpvars(0, test_leds);
      

      clk = 0;
      reset = 0;
      

      #2;
      reset = 1;
      #50;      
      reset = 0;
      # 5000000 reset = 1;
      $finish;
      
      
   end
   
endmodule
module test_leds;

   

   reg clk;
   reg reset;
   wire [7:0] led;
   
   
   
   Core uut(
	    .Clock(clk),
	    .Reset(reset),
	    .Led(led)
	    );
   
   always
     begin
	#1  clk =  ! clk;	
     end
   
   initial begin
      $dumpfile("test_leds.vcd");
      $dumpvars(0, test_leds);
      

      clk = 0;
      reset = 0;
      

      #2;
      reset = 1;
      #50;      
      reset = 0;
      # 5000000 reset = 1;
      $finish;
      
      
   end
   
endmodule