data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v:75: Multiple top level modules\n                                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                              : ... Top module \'key_debounce\'\nmodule key_debounce(  \n       ^~~~~~~~~~~~\n                                                                                                              : ... Top module \'switch_debounce\'\nmodule switch_debounce(     \n       ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v:155: Operator ASSIGNDLY expects 29 bits on the Assign RHS, but Assign RHS\'s CONST \'28\'h0\' generates 28 bits.\n                                                                                                            : ... In instance switch_debounce\n       count<=28\'d0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v:161: Operator ASSIGNDLY expects 29 bits on the Assign RHS, but Assign RHS\'s CONST \'28\'h0\' generates 28 bits.\n                                                                                                            : ... In instance switch_debounce\n        count<=28\'d0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v:158: Operator EQ expects 29 bits on the RHS, but RHS\'s CONST \'28\'h186a0\' generates 28 bits.\n                                                                                                            : ... In instance switch_debounce\n      if(count==28\'d100000)\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v:171: Operator ASSIGNDLY expects 29 bits on the Assign RHS, but Assign RHS\'s CONST \'28\'h0\' generates 28 bits.\n                                                                                                            : ... In instance switch_debounce\n       count<=28\'d0;\n            ^~\n%Error: Exiting due to 5 warning(s)\n'
module key_debounce(  
	input clk,
	input rst_n,
	input [4:0] key_in,
	output [4:0] button_out
	);

	reg [19:0] count;
	reg [4:0] key_scan;
	always@(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			count <=20'd0;
		else
	        begin
	            if(count == 20'd999_999)
	                begin
	                    count <= 20'd0;
	                    key_scan <= key_in;
	                end 
	            else 
	                count <= count + 20'd1;
	        end
	end
	reg[4:0]key_scan_r;
	always@(posedge clk)
		key_scan_r <= key_scan;
		
	wire [4:0]flag_key = key_scan_r[4:0]&(~key_scan[4:0]);
	reg [4:0]temp_led;
	always @ (posedge clk or negedge rst_n)
		begin
			if (!rst_n) 
				temp_led <= 5'b00000;
			else
				begin
					if ( flag_key[0] ) temp_led=5'b00001; 
					else if ( flag_key[1] ) temp_led=5'b00010; 
					else if ( flag_key[2] ) temp_led=5'b00100; 
					else if ( flag_key[3] ) temp_led=5'b01000; 
					else if ( flag_key[4] ) temp_led=5'b10000; 
					else temp_led=5'b00000; 
				end
		end
	assign button_out[0] = temp_led[0];
	assign button_out[1] = temp_led[1];
	assign button_out[2] = temp_led[2];
	assign button_out[3] = temp_led[3];
	assign button_out[4] = temp_led[4];
endmodule
module key_debounce(  
	input clk,
	input rst_n,
	input [4:0] key_in,
	output [4:0] button_out
	);


	reg [19:0] count;
	reg [4:0] key_scan;
	always@(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			count <=20'd0;
		else
	        begin
	            if(count == 20'd999_999)
	                begin
	                    count <= 20'd0;
	                    key_scan <= key_in;
	                end 
	            else 
	                count <= count + 20'd1;
	        end
	end
	reg[4:0]key_scan_r;
	always@(posedge clk)
		key_scan_r <= key_scan;
		
	wire [4:0]flag_key = key_scan_r[4:0]&(~key_scan[4:0]);
	reg [4:0]temp_led;
	always @ (posedge clk or negedge rst_n)
		begin
			if (!rst_n) 
				temp_led <= 5'b00000;
			else
				begin
					if ( flag_key[0] ) temp_led=5'b00001; 
					else if ( flag_key[1] ) temp_led=5'b00010; 
					else if ( flag_key[2] ) temp_led=5'b00100; 
					else if ( flag_key[3] ) temp_led=5'b01000; 
					else if ( flag_key[4] ) temp_led=5'b10000; 
					else temp_led=5'b00000; 
				end
		end
	assign button_out[0] = temp_led[0];
	assign button_out[1] = temp_led[1];
	assign button_out[2] = temp_led[2];
	assign button_out[3] = temp_led[3];
	assign button_out[4] = temp_led[4];
endmodule