data/full_repos/permissive/150881851/Completed/cache_and_ram.v
1: b"%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:14: Can't find definition of 'index_size' in dotted variable: 'cache.index_size'\nreg [cache.index_size - 1:0] index;  \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:15: Can't find definition of 'index_size' in dotted variable: 'cache.index_size'\nreg [11 - cache.index_size:0] tag;  \n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:34: Can't find definition of 'size' in dotted variable: 'ram.size'\n   prev_address = address % ram.size;\n                                ^~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:38: Can't find definition of 'index_size' in dotted variable: 'cache.index_size'\n   tag = prev_address >> cache.index_size;  \n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:39: Can't find definition of 'size' in dotted variable: 'cache.size'\n   index = address % cache.size;    \n                           ^~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:43: Can't find definition of 'ram' in dotted variable: 'ram.ram'\n     ram.ram[prev_address] = data;\n         ^~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:45: Can't find definition of 'valid_array' in dotted variable: 'cache.valid_array'\n     if (cache.valid_array[index] == 1 && cache.tag_array[index] == tag)\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:45: Can't find definition of 'tag_array' in dotted variable: 'cache.tag_array'\n     if (cache.valid_array[index] == 1 && cache.tag_array[index] == tag)\n                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:46: Can't find definition of 'cache' in dotted variable: 'cache.cache'\n      cache.cache[index] = data;\n            ^~~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:51: Can't find definition of 'valid_array' in dotted variable: 'cache.valid_array'\n     if (cache.valid_array[index] != 1 || cache.tag_array[index] != tag)\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:51: Can't find definition of 'tag_array' in dotted variable: 'cache.tag_array'\n     if (cache.valid_array[index] != 1 || cache.tag_array[index] != tag)\n                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:53: Can't find definition of 'valid_array' in dotted variable: 'cache.valid_array'\n       cache.valid_array[index] = 1;\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:54: Can't find definition of 'tag_array' in dotted variable: 'cache.tag_array'\n       cache.tag_array[index] = tag;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:55: Can't find definition of 'ram' in dotted variable: 'ram.ram'\n       cache.cache[index] = ram.ram[prev_address];\n                                ^~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:55: Can't find definition of 'cache' in dotted variable: 'cache.cache'\n       cache.cache[index] = ram.ram[prev_address];\n             ^~~~~\n%Error: data/full_repos/permissive/150881851/Completed/cache_and_ram.v:57: Can't find definition of 'cache' in dotted variable: 'cache.cache'\n     temp_out = cache.cache[index];\n                      ^~~~~\n%Error: Exiting due to 16 error(s)\n"
module cache_and_ram(
	input [31:0] address,
	input [31:0] data,
	input clk,
	input mode,
	output [31:0] out
);


reg [31:0] prev_address, prev_data;
reg prev_mode;
reg [31:0] temp_out;

reg [cache.index_size - 1:0] index;
reg [11 - cache.index_size:0] tag;

ram ram();
cache cache();

initial
	begin
		index = 0;
		tag = 0;
		prev_address = 0;
		prev_data = 0;
		prev_mode = 0;
	end

always @(posedge clk)
begin

	if (prev_address != address || prev_data != data || prev_mode != mode)
		begin
			prev_address = address % ram.size;
			prev_data = data;
			prev_mode = mode;
			
			tag = prev_address >> cache.index_size;
			index = address % cache.size;
				
			if (mode == 1)
				begin
					ram.ram[prev_address] = data;

					if (cache.valid_array[index] == 1 && cache.tag_array[index] == tag)
						cache.cache[index] = data;
				end
			else
				begin

					if (cache.valid_array[index] != 1 || cache.tag_array[index] != tag)
						begin
							cache.valid_array[index] = 1;
							cache.tag_array[index] = tag;
							cache.cache[index] = ram.ram[prev_address];
						end
					temp_out = cache.cache[index];
				end	
		end
end

assign out = temp_out;

endmodule
module cache_and_ram(
	input [31:0] address,
	input [31:0] data,
	input clk,
	input mode,
	output [31:0] out
);



reg [31:0] prev_address, prev_data;
reg prev_mode;
reg [31:0] temp_out;

reg [cache.index_size - 1:0] index;
reg [11 - cache.index_size:0] tag;

ram ram();
cache cache();

initial
	begin
		index = 0;
		tag = 0;
		prev_address = 0;
		prev_data = 0;
		prev_mode = 0;
	end

always @(posedge clk)
begin

	if (prev_address != address || prev_data != data || prev_mode != mode)
		begin
			prev_address = address % ram.size;
			prev_data = data;
			prev_mode = mode;
			
			tag = prev_address >> cache.index_size;
			index = address % cache.size;
				
			if (mode == 1)
				begin
					ram.ram[prev_address] = data;

					if (cache.valid_array[index] == 1 && cache.tag_array[index] == tag)
						cache.cache[index] = data;
				end
			else
				begin

					if (cache.valid_array[index] != 1 || cache.tag_array[index] != tag)
						begin
							cache.valid_array[index] = 1;
							cache.tag_array[index] = tag;
							cache.cache[index] = ram.ram[prev_address];
						end
					temp_out = cache.cache[index];
				end	
		end
end

assign out = temp_out;

endmodule