data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v:11: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/103842408/rtl/test,data/full_repos/permissive/103842408/rvm_constants.v\n             data/full_repos/permissive/103842408/rtl/test,data/full_repos/permissive/103842408/rvm_constants.v.v\n             data/full_repos/permissive/103842408/rtl/test,data/full_repos/permissive/103842408/rvm_constants.v.sv\n             rvm_constants.v\n             rvm_constants.v.v\n             rvm_constants.v.sv\n             obj_dir/rvm_constants.v\n             obj_dir/rvm_constants.v.v\n             obj_dir/rvm_constants.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #16 assign resetn = 1\'b1;   \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #5 assign clk = !clk;      \n    ^\n%Error: data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v:86: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("work/waves.vcd");     \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/test/rvm_core_tb.v:87: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,rvm_core_tb);\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module rvm_core_tb();

parameter SRAM_SIZE = 16384;

reg                 timeout;
integer             cycle_count;
integer             max_cycle_count;
reg     [100*8:0]   imem_file;
reg                 test_finished;
reg                 test_pass;
reg     [31:0]      halt_addr;
reg     [31:0]      pass_addr;
reg     [31:0]      fail_addr;
reg                 fail_hit ;


reg clk;
reg resetn =1'b0;
wire clk_req;

wire       [31:0] M_AXI_ARADDR;
wire              M_AXI_ARREADY;
wire       [ 2:0] M_AXI_ARSIZE;
wire              M_AXI_ARVALID;
wire       [31:0] M_AXI_AWADDR;
wire              M_AXI_AWREADY;
wire       [ 2:0] M_AXI_AWSIZE;
wire              M_AXI_AWVALID;
wire              M_AXI_BREADY;
wire       [ 1:0] M_AXI_BRESP;
wire              M_AXI_BVALID;
wire       [31:0] M_AXI_RDATA;
wire              M_AXI_RREADY;
wire       [ 1:0] M_AXI_RRESP;
wire              M_AXI_RVALID;
wire       [31:0] M_AXI_WDATA;
wire              M_AXI_WREADY;
wire       [ 3:0] M_AXI_WSTRB;
wire              M_AXI_WVALID;

initial begin
    #16 assign resetn = 1'b1;
end



always begin
    #5 assign clk = !clk;
end


initial begin
    clk             = 1'b0;
    resetn          = 1'b0;
    cycle_count     = 0;
    max_cycle_count = 500;
    halt_addr       = 32'b0;

    if($value$plusargs("IMEM=%s"            , imem_file)        )begin end
    if($value$plusargs("MAX_CYCLE_COUNT=%d" , max_cycle_count)  )begin end
    if($value$plusargs("HALT_ADDR=%h"       , halt_addr)        )begin end
    if($value$plusargs("PASS_ADDR=%h"       , pass_addr)        )begin end
    if($value$plusargs("FAIL_ADDR=%h"       , fail_addr)        )begin end

    $display("Simulation Parameters: ");
    $display("> MAX_CYCLE_COUNT: %d", max_cycle_count);
    $display("> IMEM           : %s", imem_file); 
    $display("> Halt Address   : %h", halt_addr); 
    $display("> Pass Address   : %h", pass_addr); 
    $display("> Fail Address   : %h", fail_addr); 
    
    $dumpfile("work/waves.vcd");     
    $dumpvars(0,rvm_core_tb);
end
    
integer i;


always @(posedge clk) begin
    cycle_count = cycle_count + 1;

    test_finished = 0;
    test_pass     = 0;
    timeout       = 0;
    fail_hit      = 0;

    if(M_AXI_ARADDR == halt_addr) begin
        test_finished = 1;
        test_pass     = 0;
        timeout       = 0;
    
    end else if(M_AXI_ARADDR == pass_addr) begin
        test_finished = 1;
        test_pass     = 1;
        timeout       = 0;
    
    end else if(M_AXI_ARADDR == fail_addr) begin
        test_finished = 1;
        test_pass     = 0;
        fail_hit      = 1;
        timeout       = 0;

    end else if(cycle_count > max_cycle_count) begin
        $display("Cycle timeout Reached: %d/%d", cycle_count,max_cycle_count);
        test_finished = 1;
        test_pass     = 0;
        timeout       = 1;
    end

    if(test_finished) begin
        
        $display("Register file values after %d cycles:", cycle_count);
        for (i = 0; i < 32; i = i + 1) begin
            $display("\t%d\t: 0x%h", i, `CORE_PATH.i_rvm_gprs.registers[i]);
        end

        $display("Program Counter:     %h", `CORE_PATH.s_pc);
        $display("Processor Cycles:    %d", cycle_count);

        if(test_pass) begin
            $display("TEST PASS                ");
        end else if (timeout) begin
            $display("TEST FAIL - TIMEOUT      ");
        end else if (fail_hit) begin
            $display("TEST FAIL - FAIL ADDRESS ");
        end else begin
            $display("TEST FAIL - UNKNOWN ERROR");
        end
        
        $finish(0);
    end

end






rvm_core_axi4 i_dut(
.ACLK          (clk           ) ,
.ARESETn       (resetn        ) ,
.M_AXI_ARADDR  (M_AXI_ARADDR  ) , 
.M_AXI_ARREADY (M_AXI_ARREADY ) , 
.M_AXI_ARSIZE  (M_AXI_ARSIZE  ) , 
.M_AXI_ARVALID (M_AXI_ARVALID ) , 
.M_AXI_AWADDR  (M_AXI_AWADDR  ) , 
.M_AXI_AWREADY (M_AXI_AWREADY ) , 
.M_AXI_AWSIZE  (M_AXI_AWSIZE  ) , 
.M_AXI_AWVALID (M_AXI_AWVALID ) , 
.M_AXI_BREADY  (M_AXI_BREADY  ) , 
.M_AXI_BRESP   (M_AXI_BRESP   ) , 
.M_AXI_BVALID  (M_AXI_BVALID  ) , 
.M_AXI_RDATA   (M_AXI_RDATA   ) , 
.M_AXI_RREADY  (M_AXI_RREADY  ) , 
.M_AXI_RRESP   (M_AXI_RRESP   ) , 
.M_AXI_RVALID  (M_AXI_RVALID  ) , 
.M_AXI_WDATA   (M_AXI_WDATA   ) , 
.M_AXI_WREADY  (M_AXI_WREADY  ) , 
.M_AXI_WSTRB   (M_AXI_WSTRB   ) , 
.M_AXI_WVALID  (M_AXI_WVALID  )   
);





axi_sram #(
 .addr_w(32),
 .data_w(32),
 .size(SRAM_SIZE)
) i_ram(
.memfile       (imem_file     ),
.ACLK          (clk           ) ,
.ARESETn       (resetn        ) ,
.M_AXI_ARADDR  (M_AXI_ARADDR  ) , 
.M_AXI_ARREADY (M_AXI_ARREADY ) , 
.M_AXI_ARSIZE  (M_AXI_ARSIZE  ) , 
.M_AXI_ARVALID (M_AXI_ARVALID ) , 
.M_AXI_AWADDR  (M_AXI_AWADDR  ) , 
.M_AXI_AWREADY (M_AXI_AWREADY ) , 
.M_AXI_AWSIZE  (M_AXI_AWSIZE  ) , 
.M_AXI_AWVALID (M_AXI_AWVALID ) , 
.M_AXI_BREADY  (M_AXI_BREADY  ) , 
.M_AXI_BRESP   (M_AXI_BRESP   ) , 
.M_AXI_BVALID  (M_AXI_BVALID  ) , 
.M_AXI_RDATA   (M_AXI_RDATA   ) , 
.M_AXI_RREADY  (M_AXI_RREADY  ) , 
.M_AXI_RRESP   (M_AXI_RRESP   ) , 
.M_AXI_RVALID  (M_AXI_RVALID  ) , 
.M_AXI_WDATA   (M_AXI_WDATA   ) , 
.M_AXI_WREADY  (M_AXI_WREADY  ) , 
.M_AXI_WSTRB   (M_AXI_WSTRB   ) , 
.M_AXI_WVALID  (M_AXI_WVALID  )   
);

endmodule
module rvm_core_tb();


parameter SRAM_SIZE = 16384;

reg                 timeout;
integer             cycle_count;
integer             max_cycle_count;
reg     [100*8:0]   imem_file;
reg                 test_finished;
reg                 test_pass;
reg     [31:0]      halt_addr;
reg     [31:0]      pass_addr;
reg     [31:0]      fail_addr;
reg                 fail_hit ;


reg clk;
reg resetn =1'b0;
wire clk_req;

wire       [31:0] M_AXI_ARADDR;
wire              M_AXI_ARREADY;
wire       [ 2:0] M_AXI_ARSIZE;
wire              M_AXI_ARVALID;
wire       [31:0] M_AXI_AWADDR;
wire              M_AXI_AWREADY;
wire       [ 2:0] M_AXI_AWSIZE;
wire              M_AXI_AWVALID;
wire              M_AXI_BREADY;
wire       [ 1:0] M_AXI_BRESP;
wire              M_AXI_BVALID;
wire       [31:0] M_AXI_RDATA;
wire              M_AXI_RREADY;
wire       [ 1:0] M_AXI_RRESP;
wire              M_AXI_RVALID;
wire       [31:0] M_AXI_WDATA;
wire              M_AXI_WREADY;
wire       [ 3:0] M_AXI_WSTRB;
wire              M_AXI_WVALID;

initial begin
    #16 assign resetn = 1'b1;
end



always begin
    #5 assign clk = !clk;
end


initial begin
    clk             = 1'b0;
    resetn          = 1'b0;
    cycle_count     = 0;
    max_cycle_count = 500;
    halt_addr       = 32'b0;

    if($value$plusargs("IMEM=%s"            , imem_file)        )begin end
    if($value$plusargs("MAX_CYCLE_COUNT=%d" , max_cycle_count)  )begin end
    if($value$plusargs("HALT_ADDR=%h"       , halt_addr)        )begin end
    if($value$plusargs("PASS_ADDR=%h"       , pass_addr)        )begin end
    if($value$plusargs("FAIL_ADDR=%h"       , fail_addr)        )begin end

    $display("Simulation Parameters: ");
    $display("> MAX_CYCLE_COUNT: %d", max_cycle_count);
    $display("> IMEM           : %s", imem_file); 
    $display("> Halt Address   : %h", halt_addr); 
    $display("> Pass Address   : %h", pass_addr); 
    $display("> Fail Address   : %h", fail_addr); 
    
    $dumpfile("work/waves.vcd");     
    $dumpvars(0,rvm_core_tb);
end
    
integer i;


always @(posedge clk) begin
    cycle_count = cycle_count + 1;

    test_finished = 0;
    test_pass     = 0;
    timeout       = 0;
    fail_hit      = 0;

    if(M_AXI_ARADDR == halt_addr) begin
        test_finished = 1;
        test_pass     = 0;
        timeout       = 0;
    
    end else if(M_AXI_ARADDR == pass_addr) begin
        test_finished = 1;
        test_pass     = 1;
        timeout       = 0;
    
    end else if(M_AXI_ARADDR == fail_addr) begin
        test_finished = 1;
        test_pass     = 0;
        fail_hit      = 1;
        timeout       = 0;

    end else if(cycle_count > max_cycle_count) begin
        $display("Cycle timeout Reached: %d/%d", cycle_count,max_cycle_count);
        test_finished = 1;
        test_pass     = 0;
        timeout       = 1;
    end

    if(test_finished) begin
        
        $display("Register file values after %d cycles:", cycle_count);
        for (i = 0; i < 32; i = i + 1) begin
            $display("\t%d\t: 0x%h", i, `CORE_PATH.i_rvm_gprs.registers[i]);
        end

        $display("Program Counter:     %h", `CORE_PATH.s_pc);
        $display("Processor Cycles:    %d", cycle_count);

        if(test_pass) begin
            $display("TEST PASS                ");
        end else if (timeout) begin
            $display("TEST FAIL - TIMEOUT      ");
        end else if (fail_hit) begin
            $display("TEST FAIL - FAIL ADDRESS ");
        end else begin
            $display("TEST FAIL - UNKNOWN ERROR");
        end
        
        $finish(0);
    end

end






rvm_core_axi4 i_dut(
.ACLK          (clk           ) ,
.ARESETn       (resetn        ) ,
.M_AXI_ARADDR  (M_AXI_ARADDR  ) , 
.M_AXI_ARREADY (M_AXI_ARREADY ) , 
.M_AXI_ARSIZE  (M_AXI_ARSIZE  ) , 
.M_AXI_ARVALID (M_AXI_ARVALID ) , 
.M_AXI_AWADDR  (M_AXI_AWADDR  ) , 
.M_AXI_AWREADY (M_AXI_AWREADY ) , 
.M_AXI_AWSIZE  (M_AXI_AWSIZE  ) , 
.M_AXI_AWVALID (M_AXI_AWVALID ) , 
.M_AXI_BREADY  (M_AXI_BREADY  ) , 
.M_AXI_BRESP   (M_AXI_BRESP   ) , 
.M_AXI_BVALID  (M_AXI_BVALID  ) , 
.M_AXI_RDATA   (M_AXI_RDATA   ) , 
.M_AXI_RREADY  (M_AXI_RREADY  ) , 
.M_AXI_RRESP   (M_AXI_RRESP   ) , 
.M_AXI_RVALID  (M_AXI_RVALID  ) , 
.M_AXI_WDATA   (M_AXI_WDATA   ) , 
.M_AXI_WREADY  (M_AXI_WREADY  ) , 
.M_AXI_WSTRB   (M_AXI_WSTRB   ) , 
.M_AXI_WVALID  (M_AXI_WVALID  )   
);





axi_sram #(
 .addr_w(32),
 .data_w(32),
 .size(SRAM_SIZE)
) i_ram(
.memfile       (imem_file     ),
.ACLK          (clk           ) ,
.ARESETn       (resetn        ) ,
.M_AXI_ARADDR  (M_AXI_ARADDR  ) , 
.M_AXI_ARREADY (M_AXI_ARREADY ) , 
.M_AXI_ARSIZE  (M_AXI_ARSIZE  ) , 
.M_AXI_ARVALID (M_AXI_ARVALID ) , 
.M_AXI_AWADDR  (M_AXI_AWADDR  ) , 
.M_AXI_AWREADY (M_AXI_AWREADY ) , 
.M_AXI_AWSIZE  (M_AXI_AWSIZE  ) , 
.M_AXI_AWVALID (M_AXI_AWVALID ) , 
.M_AXI_BREADY  (M_AXI_BREADY  ) , 
.M_AXI_BRESP   (M_AXI_BRESP   ) , 
.M_AXI_BVALID  (M_AXI_BVALID  ) , 
.M_AXI_RDATA   (M_AXI_RDATA   ) , 
.M_AXI_RREADY  (M_AXI_RREADY  ) , 
.M_AXI_RRESP   (M_AXI_RRESP   ) , 
.M_AXI_RVALID  (M_AXI_RVALID  ) , 
.M_AXI_WDATA   (M_AXI_WDATA   ) , 
.M_AXI_WREADY  (M_AXI_WREADY  ) , 
.M_AXI_WSTRB   (M_AXI_WSTRB   ) , 
.M_AXI_WVALID  (M_AXI_WVALID  )   
);

endmodule