data/full_repos/permissive/170365068/Splitted modules/Main modules/DataMemory.v
1: b'%Error: Cannot find file containing module: modules/Main\n        ... Looked in:\n             data/full_repos/permissive/170365068/Splitted/modules/Main\n             data/full_repos/permissive/170365068/Splitted/modules/Main.v\n             data/full_repos/permissive/170365068/Splitted/modules/Main.sv\n             modules/Main\n             modules/Main.v\n             modules/Main.sv\n             obj_dir/modules/Main\n             obj_dir/modules/Main.v\n             obj_dir/modules/Main.sv\n%Error: Cannot find file containing module: modules,data/full_repos/permissive/170365068\n%Error: Cannot find file containing module: data/full_repos/permissive/170365068/Splitted\n%Error: Cannot find file containing module: modules/DataMemory.v\n%Error: Exiting due to 4 error(s)\n'
module DataMemory(clk,Address,WriteData,ReadData,MemRead,MemWrite,reset);
	input[31:0] Address,WriteData;
	input MemRead,MemWrite,reset,clk;
	output reg [31:0] ReadData;
	
	integer i;  
    	reg [31:0] ram [31:0];
    	wire [4:0] ramAddress = Address[4:0];
	
	always@(posedge clk)
	begin
		if(reset)
		begin 
		   	for(i=0;i<31;i=i+1)
		        ram[i] <=0; 
		end
		else begin
			if(MemWrite)
				ram[ramAddress] <= WriteData;
		end
		ReadData = (MemRead==1'b1) ? ram[ramAddress]:0;
	end
				
endmodule
module DataMemory(clk,Address,WriteData,ReadData,MemRead,MemWrite,reset);

	input[31:0] Address,WriteData;
	input MemRead,MemWrite,reset,clk;
	output reg [31:0] ReadData;
	
	integer i;  
    	reg [31:0] ram [31:0];
    	wire [4:0] ramAddress = Address[4:0];
	
	always@(posedge clk)
	begin
		if(reset)
		begin 
		   	for(i=0;i<31;i=i+1)
		        ram[i] <=0; 
		end
		else begin
			if(MemWrite)
				ram[ramAddress] <= WriteData;
		end
		ReadData = (MemRead==1'b1) ? ram[ramAddress]:0;
	end
				
endmodule