data/full_repos/permissive/14432793/OLD/I2C/test/test1.v
 line:13: before: "reset"
1: b'%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #40\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:97: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #10 \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:103: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #10 \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:107: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #10 \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:111: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #10 \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:116: Unsupported: Ignoring delay on this delayed statement.\n    #2\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:118: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Error: Exiting due to 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test1(
input wire clk,
input wire reset,
input wire enabled,
input wire in,
input wire Start,
input wire Stop,
output wire sda
);

  reg start, done, data;

  always@( negedge Start or reset )
    begin
      if(~reset)
        begin
          start <= 1'b0;
        end
      else
        begin
          if( enabled == 1 )
            begin
              start <= 1'b1;
            end
          else
            begin
              start <= 1'b0;
            end
        end
    end
  
  always@( posedge Stop or reset )
    begin
      if(~reset)
        begin
          done <= 1'b0;
        end
      else
        begin
          if( enabled == 1 )
            begin
              done <= 1'b1;
            end
          else
            begin
              done <= 1'b0;
            end
        end
    end
   
  always@( posedge clk )
    begin
      data <= in;
    end

  assign sda = ( enabled == 1 ) ? ( start == 1) ? (done== 0) ? data : 1'bz : 1'bz : 1'bz;

endmodule
module test1(
input wire clk,
input wire reset,
input wire enabled,
input wire in,
input wire Start,
input wire Stop,
output wire sda
);


  reg start, done, data;

  always@( negedge Start or reset )
    begin
      if(~reset)
        begin
          start <= 1'b0;
        end
      else
        begin
          if( enabled == 1 )
            begin
              start <= 1'b1;
            end
          else
            begin
              start <= 1'b0;
            end
        end
    end
  
  always@( posedge Stop or reset )
    begin
      if(~reset)
        begin
          done <= 1'b0;
        end
      else
        begin
          if( enabled == 1 )
            begin
              done <= 1'b1;
            end
          else
            begin
              done <= 1'b0;
            end
        end
    end
   
  always@( posedge clk )
    begin
      data <= in;
    end

  assign sda = ( enabled == 1 ) ? ( start == 1) ? (done== 0) ? data : 1'bz : 1'bz : 1'bz;

endmodule