data/full_repos/permissive/127311496/src/v/Cache/DCache.v
 line:112: before: "="
1: b"%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:136: Cannot find file containing module: 'DCacheTag'\n DCacheTag cacheTag(.clka(clk), .wea(tagWe),\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/DCacheTag\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/DCacheTag.v\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/DCacheTag.sv\n             DCacheTag\n             DCacheTag.v\n             DCacheTag.sv\n             obj_dir/DCacheTag\n             obj_dir/DCacheTag.v\n             obj_dir/DCacheTag.sv\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:138: Cannot find file containing module: 'CacheLRUBit'\n CacheLRUBit cacheLRU(.clk(clk), .req(req_reg), .addr(tagAddr), .hit({hit1, hit0}), .flag(LRUBit));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:60: Cannot find file containing module: 'DCacheData'\n DCacheData way0Data(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:65: Cannot find file containing module: 'DCacheData'\n DCacheData way1Data(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:88: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceTypeCross (.clki(clkCPU), .clko(clkDDR), .i(replaceType_CPU), .o(replaceType_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:89: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceIndexCross[9:0](.clki(clkCPU), .clko(clkDDR), .i(replaceIndex_CPU), .o(replaceIndex_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:90: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) oldTagCross[16:0](.clki(clkCPU), .clko(clkDDR), .i(oldTag_CPU), .o(oldTag_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:91: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) newTagCross[16:0](.clki(clkCPU), .clko(clkDDR), .i(newTag_CPU), .o(newTag_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:93: Cannot find file containing module: 'AsyncHandshake'\n AsyncHandshake #(.STB_FREQ(1000 / CLKCPU_PERIOD), .ACK_FREQ(1000 / CLKDDR_PERIOD))\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:97: Cannot find file containing module: 'AsyncHandshake'\n AsyncHandshake #(.STB_FREQ(1000 / CLKDDR_PERIOD), .ACK_FREQ(1000 / CLKCPU_PERIOD))\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module DCache #(
	parameter CLKCPU_PERIOD = 10,
	parameter CLKDDR_PERIOD = 5
) (
	input clkCPU, input clkDDR, input rstCPU, input rstDDR,

	input [31:0] addrIn, input req, input [31:0] dataIn,
	input [3:0] dm, input we, output [31:0] dataOut, output dStall, input invalidate,

	output [31:0] ws_addr, output [511:0] ws_dout, output [63:0] ws_dm,
	output ws_we, output ws_cyc, output ws_stb, input ws_ack,
	input [511:0] ws_din
);
	wire [31:0] douta0, douta1;
	wire [1:0] writeReject;
	wire [9:0] addrb;
	wire [511:0] dinb, doutb;
	wire [63:0] dirtyb;
	wire dataOp;
	wire waySelA, waySelB;
	wire web;
	
	wire replaceStb_CPU, replaceStb_DDR;
	wire replaceType_CPU, replaceType_DDR;
	wire replaceAck_CPU, replaceAck_DDR;
	wire completeStb_CPU, completeStb_DDR;
	wire [9:0] replaceIndex_CPU, replaceIndex_DDR;
	wire [16:0] oldTag_CPU, oldTag_DDR;
	wire [16:0] newTag_CPU, newTag_DDR;
	
	DCacheData way0Data(
		.addra(addrIn[14:2]), .clka(clkCPU), .ena(~dStall), .wea(dm),
		.dina(dataIn), .douta(douta0), .readReq(req & ~we), .writeReject(writeReject[0]),
		.addrb({addrb[8:0], addrb[9]}), .clkb(clkDDR), .enb(1'b1), .web(web), .op(dataOp),
		.dinb(dinb[255:  0]), .doutb(doutb[255:  0]), .dirtyb(dirtyb[31: 0]));
	DCacheData way1Data(
		.addra(addrIn[14:2]), .clka(clkCPU), .ena(~dStall), .wea(dm),
		.dina(dataIn), .douta(douta1), .readReq(req & ~we), .writeReject(writeReject[1]),
		.addrb({addrb[8:0],~addrb[9]}), .clkb(clkDDR), .enb(1'b1), .web(web), .op(dataOp),
		.dinb(dinb[511:256]), .doutb(doutb[511:256]), .dirtyb(dirtyb[63:32]));

	DCacheFSM_CPU FSM0(.clk(clkCPU), .rst(rstCPU),
		.addrIn(addrIn), .req(req), .write(we),
		.dataOut(dataOut), .stall(dStall), .invalidateReq(invalidate),
		.writeReject(writeReject), .douta0(douta0), .douta1(douta1),
		.replaceStb(replaceStb_CPU), .replaceType(replaceType_CPU), .replaceAck(replaceAck_CPU),
		.completeStb(completeStb_CPU), .replaceIndex(replaceIndex_CPU),
		.oldTag(oldTag_CPU), .newTag(newTag_CPU));
	
	DCacheFSM_DDR FSM1(.clk(clkDDR), .rst(rstDDR),
		.ws_addr(ws_addr), .ws_dout(ws_dout), .ws_dm(ws_dm),
		.ws_din(ws_din), .ws_cyc(ws_cyc), .ws_stb(ws_stb), .ws_we(ws_we), .ws_ack(ws_ack),
		.addrb(addrb), .dinb(dinb), .dataOp(dataOp), .doutb(doutb),
		.web(web), .dirtyb(dirtyb),
		.replaceStb(replaceStb_DDR), .replaceType(replaceType_DDR), .replaceAck(replaceAck_DDR),
		.completeStb(completeStb_DDR), .replaceIndex(replaceIndex_DDR),
		.oldTag(oldTag_DDR), .newTag(newTag_DDR));
	
	ClockDomainCross #(0, 1) replaceTypeCross (.clki(clkCPU), .clko(clkDDR), .i(replaceType_CPU), .o(replaceType_DDR));
	ClockDomainCross #(0, 1) replaceIndexCross[9:0](.clki(clkCPU), .clko(clkDDR), .i(replaceIndex_CPU), .o(replaceIndex_DDR));
	ClockDomainCross #(0, 1) oldTagCross[16:0](.clki(clkCPU), .clko(clkDDR), .i(oldTag_CPU), .o(oldTag_DDR));
	ClockDomainCross #(0, 1) newTagCross[16:0](.clki(clkCPU), .clko(clkDDR), .i(newTag_CPU), .o(newTag_DDR));
	
	AsyncHandshake #(.STB_FREQ(1000 / CLKCPU_PERIOD), .ACK_FREQ(1000 / CLKDDR_PERIOD))
		replaceCross(.clkStb(clkCPU), .clkAck(clkDDR),
		.stbI(replaceStb_CPU), .stbO(replaceStb_DDR),
		.ackI(replaceAck_DDR), .ackO(replaceAck_CPU));
	AsyncHandshake #(.STB_FREQ(1000 / CLKDDR_PERIOD), .ACK_FREQ(1000 / CLKCPU_PERIOD))
		completeCross(.clkStb(clkDDR), .clkAck(clkCPU),
		.stbI(completeStb_DDR), .stbO(completeStb_CPU),
		.ackI(completeStb_CPU), .ackO());

endmodule
module DCache #(
	parameter CLKCPU_PERIOD = 10,
	parameter CLKDDR_PERIOD = 5
) (
	input clkCPU, input clkDDR, input rstCPU, input rstDDR,

	input [31:0] addrIn, input req, input [31:0] dataIn,
	input [3:0] dm, input we, output [31:0] dataOut, output dStall, input invalidate,

	output [31:0] ws_addr, output [511:0] ws_dout, output [63:0] ws_dm,
	output ws_we, output ws_cyc, output ws_stb, input ws_ack,
	input [511:0] ws_din
);

	wire [31:0] douta0, douta1;
	wire [1:0] writeReject;
	wire [9:0] addrb;
	wire [511:0] dinb, doutb;
	wire [63:0] dirtyb;
	wire dataOp;
	wire waySelA, waySelB;
	wire web;
	
	wire replaceStb_CPU, replaceStb_DDR;
	wire replaceType_CPU, replaceType_DDR;
	wire replaceAck_CPU, replaceAck_DDR;
	wire completeStb_CPU, completeStb_DDR;
	wire [9:0] replaceIndex_CPU, replaceIndex_DDR;
	wire [16:0] oldTag_CPU, oldTag_DDR;
	wire [16:0] newTag_CPU, newTag_DDR;
	
	DCacheData way0Data(
		.addra(addrIn[14:2]), .clka(clkCPU), .ena(~dStall), .wea(dm),
		.dina(dataIn), .douta(douta0), .readReq(req & ~we), .writeReject(writeReject[0]),
		.addrb({addrb[8:0], addrb[9]}), .clkb(clkDDR), .enb(1'b1), .web(web), .op(dataOp),
		.dinb(dinb[255:  0]), .doutb(doutb[255:  0]), .dirtyb(dirtyb[31: 0]));
	DCacheData way1Data(
		.addra(addrIn[14:2]), .clka(clkCPU), .ena(~dStall), .wea(dm),
		.dina(dataIn), .douta(douta1), .readReq(req & ~we), .writeReject(writeReject[1]),
		.addrb({addrb[8:0],~addrb[9]}), .clkb(clkDDR), .enb(1'b1), .web(web), .op(dataOp),
		.dinb(dinb[511:256]), .doutb(doutb[511:256]), .dirtyb(dirtyb[63:32]));

	DCacheFSM_CPU FSM0(.clk(clkCPU), .rst(rstCPU),
		.addrIn(addrIn), .req(req), .write(we),
		.dataOut(dataOut), .stall(dStall), .invalidateReq(invalidate),
		.writeReject(writeReject), .douta0(douta0), .douta1(douta1),
		.replaceStb(replaceStb_CPU), .replaceType(replaceType_CPU), .replaceAck(replaceAck_CPU),
		.completeStb(completeStb_CPU), .replaceIndex(replaceIndex_CPU),
		.oldTag(oldTag_CPU), .newTag(newTag_CPU));
	
	DCacheFSM_DDR FSM1(.clk(clkDDR), .rst(rstDDR),
		.ws_addr(ws_addr), .ws_dout(ws_dout), .ws_dm(ws_dm),
		.ws_din(ws_din), .ws_cyc(ws_cyc), .ws_stb(ws_stb), .ws_we(ws_we), .ws_ack(ws_ack),
		.addrb(addrb), .dinb(dinb), .dataOp(dataOp), .doutb(doutb),
		.web(web), .dirtyb(dirtyb),
		.replaceStb(replaceStb_DDR), .replaceType(replaceType_DDR), .replaceAck(replaceAck_DDR),
		.completeStb(completeStb_DDR), .replaceIndex(replaceIndex_DDR),
		.oldTag(oldTag_DDR), .newTag(newTag_DDR));
	
	ClockDomainCross #(0, 1) replaceTypeCross (.clki(clkCPU), .clko(clkDDR), .i(replaceType_CPU), .o(replaceType_DDR));
	ClockDomainCross #(0, 1) replaceIndexCross[9:0](.clki(clkCPU), .clko(clkDDR), .i(replaceIndex_CPU), .o(replaceIndex_DDR));
	ClockDomainCross #(0, 1) oldTagCross[16:0](.clki(clkCPU), .clko(clkDDR), .i(oldTag_CPU), .o(oldTag_DDR));
	ClockDomainCross #(0, 1) newTagCross[16:0](.clki(clkCPU), .clko(clkDDR), .i(newTag_CPU), .o(newTag_DDR));
	
	AsyncHandshake #(.STB_FREQ(1000 / CLKCPU_PERIOD), .ACK_FREQ(1000 / CLKDDR_PERIOD))
		replaceCross(.clkStb(clkCPU), .clkAck(clkDDR),
		.stbI(replaceStb_CPU), .stbO(replaceStb_DDR),
		.ackI(replaceAck_DDR), .ackO(replaceAck_CPU));
	AsyncHandshake #(.STB_FREQ(1000 / CLKDDR_PERIOD), .ACK_FREQ(1000 / CLKCPU_PERIOD))
		completeCross(.clkStb(clkDDR), .clkAck(clkCPU),
		.stbI(completeStb_DDR), .stbO(completeStb_CPU),
		.ackI(completeStb_CPU), .ackO());

endmodule