data/full_repos/permissive/136510272/projects/vga640x480/sdram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/vga640x480/sdram.v:60: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance sdram\nreg [11:0] init_counter = 1\'b0;\n                          ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/vga640x480/sdram.v:135: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                    : ... In instance sdram\n            data_rd <= we ? dq : 1\'b0;\n                          ^\n%Error: Exiting due to 2 warning(s)\n'
module sdram (


    input   wire        clock,
    output  wire        sdclk,
    output  reg  [11:0] addr,
    output  reg  [1:0]  bank,
    inout   wire [15:0] dq,
    output  reg         ldqm,
    output  reg         udqm,
    output  reg         ras,
    output  reg         cas,
    output  reg         we,
    





    input   wire        rden,
    input   wire        wren,
    input   wire [21:0] address,
    input   wire [15:0] data_wr,
    output  reg  [15:0] data_rd,
    output  reg         busy
);


`define STATE_INIT     4'b0000
`define STATE_WAIT     4'b0001
`define STATE_RW       4'b0010
`define STATE_RW_2     4'b0011
`define STATE_RW_3     4'b0100
`define STATE_RW_4     4'b0101


`define PRE_TIME       0

initial begin

    we   = 1'b1;
    cas  = 1'b1;
    ras  = 1'b1;
    ldqm = 1'b1;
    udqm = 1'b1;
    busy = 1'b1;
    
end


assign dq = we ? 16'bZ : data_wr;
assign sdclk = clock;


reg [3:0]  state = `STATE_INIT;
reg [11:0] init_counter = 1'b0;

reg [1:0] div25 = 2'b00;

always @(posedge clock) div25 <= div25 + 1'b1;


always @(posedge div25[0]) begin

    case (state)
    
        `STATE_INIT: begin
        

            if (init_counter == `PRE_TIME + 1) begin ras <= 1'b0; cas <= 1'b1; we <= 1'b0; addr[10] <= 1'b1; end 
            

            else if (init_counter == `PRE_TIME + 4) begin ras <= 1'b0; cas <= 1'b0; we <= 1'b1; end
        

            else if (init_counter == `PRE_TIME + 18) begin ras <= 1'b0; cas <= 1'b0; we <= 1'b0; addr[9:0] <= 10'b0000100111; end
            

            else if (init_counter == `PRE_TIME + 21) begin state <= `STATE_WAIT; end
            

            else begin ras <= 1'b1; cas <= 1'b1; we <= 1'b1; end
                                        
            init_counter <= init_counter + 1'b1;        
        end
    

        `STATE_WAIT: begin


            if (rden | wren) begin

                state <= `STATE_RW;
                bank  <= address[21:20];
                addr  <= address[19:8];
                ras   <= 1'b0;
                busy  <= 1'b1;
                ldqm  <= 1'b1;
                udqm  <= 1'b1;

            end

            else begin ras <= 1'b1; end

            cas <= 1'b1;
            we  <= 1'b1;

        end
        

        `STATE_RW: begin
        
            addr  <= {4'b0000, address[7:0]};

            ras   <= 1'b1;
            cas   <= 1'b0; 
            we    <= wren ^ 1'b1;
            
            ldqm  <= 1'b0; 
            udqm  <= 1'b0; 
            state <= `STATE_RW_2;

        end
        

        `STATE_RW_2: begin state <= `STATE_RW_3; end   
        

        `STATE_RW_3: begin
  
            data_rd <= we ? dq : 1'b0;
            
            ras     <= 1'b0;
            cas     <= 1'b1;
            we      <= 1'b0; 
            
            busy    <= 1'b0;
            ldqm    <= 1'b1; 
            udqm    <= 1'b1; 
            state   <= `STATE_WAIT;  
            
        end

    endcase

end

endmodule
module sdram (


    input   wire        clock,
    output  wire        sdclk,
    output  reg  [11:0] addr,
    output  reg  [1:0]  bank,
    inout   wire [15:0] dq,
    output  reg         ldqm,
    output  reg         udqm,
    output  reg         ras,
    output  reg         cas,
    output  reg         we,
    





    input   wire        rden,
    input   wire        wren,
    input   wire [21:0] address,
    input   wire [15:0] data_wr,
    output  reg  [15:0] data_rd,
    output  reg         busy
);



`define STATE_INIT     4'b0000
`define STATE_WAIT     4'b0001
`define STATE_RW       4'b0010
`define STATE_RW_2     4'b0011
`define STATE_RW_3     4'b0100
`define STATE_RW_4     4'b0101


`define PRE_TIME       0

initial begin

    we   = 1'b1;
    cas  = 1'b1;
    ras  = 1'b1;
    ldqm = 1'b1;
    udqm = 1'b1;
    busy = 1'b1;
    
end


assign dq = we ? 16'bZ : data_wr;
assign sdclk = clock;


reg [3:0]  state = `STATE_INIT;
reg [11:0] init_counter = 1'b0;

reg [1:0] div25 = 2'b00;

always @(posedge clock) div25 <= div25 + 1'b1;


always @(posedge div25[0]) begin

    case (state)
    
        `STATE_INIT: begin
        

            if (init_counter == `PRE_TIME + 1) begin ras <= 1'b0; cas <= 1'b1; we <= 1'b0; addr[10] <= 1'b1; end 
            

            else if (init_counter == `PRE_TIME + 4) begin ras <= 1'b0; cas <= 1'b0; we <= 1'b1; end
        

            else if (init_counter == `PRE_TIME + 18) begin ras <= 1'b0; cas <= 1'b0; we <= 1'b0; addr[9:0] <= 10'b0000100111; end
            

            else if (init_counter == `PRE_TIME + 21) begin state <= `STATE_WAIT; end
            

            else begin ras <= 1'b1; cas <= 1'b1; we <= 1'b1; end
                                        
            init_counter <= init_counter + 1'b1;        
        end
    

        `STATE_WAIT: begin


            if (rden | wren) begin

                state <= `STATE_RW;
                bank  <= address[21:20];
                addr  <= address[19:8];
                ras   <= 1'b0;
                busy  <= 1'b1;
                ldqm  <= 1'b1;
                udqm  <= 1'b1;

            end

            else begin ras <= 1'b1; end

            cas <= 1'b1;
            we  <= 1'b1;

        end
        

        `STATE_RW: begin
        
            addr  <= {4'b0000, address[7:0]};

            ras   <= 1'b1;
            cas   <= 1'b0; 
            we    <= wren ^ 1'b1;
            
            ldqm  <= 1'b0; 
            udqm  <= 1'b0; 
            state <= `STATE_RW_2;

        end
        

        `STATE_RW_2: begin state <= `STATE_RW_3; end   
        

        `STATE_RW_3: begin
  
            data_rd <= we ? dq : 1'b0;
            
            ras     <= 1'b0;
            cas     <= 1'b1;
            we      <= 1'b0; 
            
            busy    <= 1'b0;
            ldqm    <= 1'b1; 
            udqm    <= 1'b1; 
            state   <= `STATE_WAIT;  
            
        end

    endcase

end

endmodule