data/full_repos/permissive/132176809/vga.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/132176809/vga.v:56: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                             : ... In instance vga\n        red   <= 3\'b000;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/132176809/vga.v:57: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                             : ... In instance vga\n        green <= 3\'b000;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/132176809/vga.v:58: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                             : ... In instance vga\n        blue  <= 3\'b000;\n              ^~\n%Error: Exiting due to 3 warning(s)\n'
module vga (
	input wire clk,
    input wire reset,
    input wire [5:0] color_px,
    output reg [1:0] red,
    output reg [1:0] green,
    output reg [1:0] blue,
    output reg [10:0] hcounter,
    output reg [9:0] vcounter,
    output reg hsync,
    output reg vsync,
    output reg blank,
    output reg lower_blank
    );

    localparam border_w = 10;

	always@(hcounter or vcounter) begin

        red   <= 3'b000;
        green <= 3'b000;
        blue  <= 3'b000;


        hsync <= 1'b1;
        vsync <= 1'b1;
        blank <= 1'b0;
        lower_blank <= 1'b0;


        if(hcounter > 655 && hcounter < 751)
           hsync <= 1'b0;
        if(vcounter > 489 && vcounter < 491)
           vsync <= 1'b0;

        if(hcounter > 639 || vcounter > 479)
           blank <= 1'b1;
        if(vcounter > 479 )
           lower_blank <= 1'b1;

        if(vcounter < 480 && hcounter < 640) begin
            red <=   color_px[5:4];
            green <= color_px[3:2];
            blue <=  color_px[1:0];
        end else begin
            red <= 2'b0;
            green <= 2'b0;
            blue <= 2'b0;
        end 

    end


    always@(posedge clk) begin
        if(reset == 1) begin
            hcounter <= 0;
            vcounter <= 0;
        end else if(hcounter == 799) begin
            hcounter <= 0;
            if(vcounter == 524) begin
                vcounter <= 0;
            end else
                vcounter <= vcounter + 1;
            end
        else
            hcounter <= hcounter + 1;
    end
endmodule
module vga (
	input wire clk,
    input wire reset,
    input wire [5:0] color_px,
    output reg [1:0] red,
    output reg [1:0] green,
    output reg [1:0] blue,
    output reg [10:0] hcounter,
    output reg [9:0] vcounter,
    output reg hsync,
    output reg vsync,
    output reg blank,
    output reg lower_blank
    );


    localparam border_w = 10;

	always@(hcounter or vcounter) begin

        red   <= 3'b000;
        green <= 3'b000;
        blue  <= 3'b000;


        hsync <= 1'b1;
        vsync <= 1'b1;
        blank <= 1'b0;
        lower_blank <= 1'b0;


        if(hcounter > 655 && hcounter < 751)
           hsync <= 1'b0;
        if(vcounter > 489 && vcounter < 491)
           vsync <= 1'b0;

        if(hcounter > 639 || vcounter > 479)
           blank <= 1'b1;
        if(vcounter > 479 )
           lower_blank <= 1'b1;

        if(vcounter < 480 && hcounter < 640) begin
            red <=   color_px[5:4];
            green <= color_px[3:2];
            blue <=  color_px[1:0];
        end else begin
            red <= 2'b0;
            green <= 2'b0;
            blue <= 2'b0;
        end 

    end


    always@(posedge clk) begin
        if(reset == 1) begin
            hcounter <= 0;
            vcounter <= 0;
        end else if(hcounter == 799) begin
            hcounter <= 0;
            if(vcounter == 524) begin
                vcounter <= 0;
            end else
                vcounter <= vcounter + 1;
            end
        else
            hcounter <= hcounter + 1;
    end
endmodule