data/full_repos/permissive/133571498/adder/top.v
data/verilator_xmls/dc5ddae3-e29e-46fe-bc29-3886027e0c27.xml
module top #(
	parameter WIDTH = 4
) (

	input wire [WIDTH-1:0] A, B,

	output wire [WIDTH-1:0] Sum
);

	assign Sum = A + B;

endmodule
module top #(
	parameter WIDTH = 4
) (

	input wire [WIDTH-1:0] A, B,

	output wire [WIDTH-1:0] Sum
);


	assign Sum = A + B;

endmodule