data/full_repos/permissive/143278/ivltests/ldelay2.v
 line:28: before: "1"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay2.v:34: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/ldelay2.v:35: syntax error, unexpected \'@\'\n @(q);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay2.v:45: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay2.v:51: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   wire q;
   reg  a, b;
   xor #1 (q, a, b);

   reg	error;
   initial
     begin
	error = 0;
	#2;
	@(q);
	error = 1;
	$display("%0d: FAILED: q=%b", $time, q);
     end

   initial
     begin

	a = 0;
	b = 1;
	#3;
	a = 1;
	b = 0;
	#2;
	a = 0;
	b = 1;
	#3;
	if (!error)
	  $display("PASSED");
     end
endmodule
module test;


   wire q;
   reg  a, b;
   xor #1 (q, a, b);

   reg	error;
   initial
     begin
	error = 0;
	#2;
	@(q);
	error = 1;
	$display("%0d: FAILED: q=%b", $time, q);
     end

   initial
     begin

	a = 0;
	b = 1;
	#3;
	a = 1;
	b = 0;
	#2;
	a = 0;
	b = 1;
	#3;
	if (!error)
	  $display("PASSED");
     end
endmodule