data/full_repos/permissive/123043192/FPGA/USB/Sync245/Loopback-FPGA/fpga_usb_sync_245.srcs/sources_1/new/graycounter.v
data/verilator_xmls/95a69e84-0145-4ba6-bba2-cb6c8b6ab6f9.xml
module graycounter#(parameter counterwidth = 8)(
        output reg [counterwidth - 1:0] graycount,
        
        input wire enable,
        input wire clear,
        
        input wire clk
    );
    
    reg [counterwidth - 1:0] binary_count;
    
    always @(negedge clk) begin
        if (clear) begin
            binary_count <= {counterwidth{1'b0}} + 1;
            graycount <= {counterwidth{1'b0}};
        end
        else if(enable) begin
            binary_count <= binary_count + 1;
            graycount <= {binary_count[counterwidth - 1], binary_count[counterwidth-2:0] ^ binary_count[counterwidth -1:1]};
        end
    end
    
    
    
endmodule
module graycounter#(parameter counterwidth = 8)(
        output reg [counterwidth - 1:0] graycount,
        
        input wire enable,
        input wire clear,
        
        input wire clk
    );

    
    reg [counterwidth - 1:0] binary_count;
    
    always @(negedge clk) begin
        if (clear) begin
            binary_count <= {counterwidth{1'b0}} + 1;
            graycount <= {counterwidth{1'b0}};
        end
        else if(enable) begin
            binary_count <= binary_count + 1;
            graycount <= {binary_count[counterwidth - 1], binary_count[counterwidth-2:0] ^ binary_count[counterwidth -1:1]};
        end
    end
    
    
    
endmodule