data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PHT.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PHT.v:3: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/bus.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/bus.v.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/bus.v.sv\n             bus.v\n             bus.v.v\n             bus.v.sv\n             obj_dir/bus.v\n             obj_dir/bus.v.v\n             obj_dir/bus.v.sv\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PHT.v:4: Cannot find include file: branch.v\n`include "branch.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PHT.v:12: Define or directive not defined: \'`GHR_BUS\'\n  input   [`GHR_BUS]  last_index,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PHT.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input   [`GHR_BUS]  last_index,\n                   ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PHT.v:14: Define or directive not defined: \'`GHR_BUS\'\n  input   [`GHR_BUS]  index,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PHT.v:19: Define or directive not defined: \'`PHT_SIZE\'\n  reg[1:0] counters[`PHT_SIZE - 1:0];\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PHT.v:20: syntax error, unexpected assign\n  assign is_taken_out = |(counters[index] & 2\'b10);\n  ^~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PHT.v:26: syntax error, unexpected for\n      for (i = 0; i < `PHT_SIZE; i = i + 1) begin\n      ^~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PHT.v:26: Define or directive not defined: \'`PHT_SIZE\'\n      for (i = 0; i < `PHT_SIZE; i = i + 1) begin\n                      ^~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module PHT(
  input               clk,
  input               rst,

  input               is_last_branch,
  input               is_last_taken,
  input   [`GHR_BUS]  last_index,

  input   [`GHR_BUS]  index,

  output              is_taken_out
);

  reg[1:0] counters[`PHT_SIZE - 1:0];
  assign is_taken_out = |(counters[index] & 2'b10);

  always @(posedge clk) begin
    if (!rst) begin

      integer i;
      for (i = 0; i < `PHT_SIZE; i = i + 1) begin
        counters[i] <= 2'b10;
      end
    end
    else if (is_last_branch) begin
      if (&counters[last_index]) begin

        if (!is_last_taken) begin
          counters[last_index] <= counters[last_index] - 1;
        end
      end
      else if (!|counters[last_index]) begin

        if (is_last_taken) begin
          counters[last_index] <= counters[last_index] + 1;
        end
      end
      else begin

        if (!is_last_taken) begin
          counters[last_index] <= counters[last_index] - 1;
        end
        else begin
          counters[last_index] <= counters[last_index] + 1;
        end
      end
    end
  end

endmodule
module PHT(
  input               clk,
  input               rst,

  input               is_last_branch,
  input               is_last_taken,
  input   [`GHR_BUS]  last_index,

  input   [`GHR_BUS]  index,

  output              is_taken_out
);


  reg[1:0] counters[`PHT_SIZE - 1:0];
  assign is_taken_out = |(counters[index] & 2'b10);

  always @(posedge clk) begin
    if (!rst) begin

      integer i;
      for (i = 0; i < `PHT_SIZE; i = i + 1) begin
        counters[i] <= 2'b10;
      end
    end
    else if (is_last_branch) begin
      if (&counters[last_index]) begin

        if (!is_last_taken) begin
          counters[last_index] <= counters[last_index] - 1;
        end
      end
      else if (!|counters[last_index]) begin

        if (is_last_taken) begin
          counters[last_index] <= counters[last_index] + 1;
        end
      end
      else begin

        if (!is_last_taken) begin
          counters[last_index] <= counters[last_index] - 1;
        end
        else begin
          counters[last_index] <= counters[last_index] + 1;
        end
      end
    end
  end

endmodule