data/full_repos/permissive/214325244/hw1_ incomplete.v
 line:51: before: "input"
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/214325244/hw1_\n        ... Looked in:\n             data/full_repos/permissive/214325244,data/full_repos/permissive/214325244/data/full_repos/permissive/214325244/hw1_\n             data/full_repos/permissive/214325244,data/full_repos/permissive/214325244/data/full_repos/permissive/214325244/hw1_.v\n             data/full_repos/permissive/214325244,data/full_repos/permissive/214325244/data/full_repos/permissive/214325244/hw1_.sv\n             data/full_repos/permissive/214325244/hw1_\n             data/full_repos/permissive/214325244/hw1_.v\n             data/full_repos/permissive/214325244/hw1_.sv\n             obj_dir/data/full_repos/permissive/214325244/hw1_\n             obj_dir/data/full_repos/permissive/214325244/hw1_.v\n             obj_dir/data/full_repos/permissive/214325244/hw1_.sv\n%Error: Cannot find file containing module: incomplete.v\n%Error: Exiting due to 2 error(s)\n'
module trafficlightcntr(Clock, Reset, S1, S2, S3, L1, L2, L3, load, decr, value, timeup)

input Clock;
input Reset;
input
S1,
S2,
S3;

output reg [1:0]
L1,
L2,
L3;

output reg [7:0]  value;

	
wire load, decr;



parameter
	FS	= 6'b000001,
	REDL	= 6'b000010,
	NG	= 6'b000100,
	NY	= 6'b001000,
	EWG	= 6'b010000,
	EWY	= 6'b100000;



parameter
	FAIL	= 2'b00,
	GREEN	= 2'b01,
	YELLOW	= 2'b10,
	RED	= 2'b11;

reg [5:0] state;
reg [5:0] next_state;





always @(posedge Clock, posedge Reset)
begin
	if(Reset) 
	begin
		state = FS;
		value = 1'b1;
		load = 1'b1;
	end

	else
	begin
		load = 1'b0;
		if(timerup)
			decr <= 1'b0;
		state <= next_state;
	end
end

always @(state)
begin
	
	
	case(state)
		FS:	begin
			L1 = FAIL;
			L2 = FAIL;
			L3 = FAIL;
			end

		REDL:	begin
			L1 = RED;			
			L2 = RED;
			L3 = RED;
			end

		NG:	begin
			L1 = GREEN;			
			L2 = RED;
			L3 = RED;
			end


		NY:	begin
			L1 = YELLOW;			
			L2 = RED;
			L3 = RED;
			end


		EWG:	begin
			L1 = RED;			
			L2 = GREEN;
			L3 = GREEN;
			end

		EWY:	begin
			L1 = RED;			
			L2 = YELLOW;
			L3 = YELLOW;
			end
	endcase
end



always @(state or next_state)				
begin
	case(state)
					

		REDL:	begin
				if(timerup && S1)
				begin
					value = 8'b00101101;
					load = 1'b1;
					next_state = NG;
				end
				

			`	else
				begin
					decr <= 1'b1;
					next_state = REDL;
				end
			end
	 
		NG:	begin
				if(timerup && S1 && ~S2 && ~S3)
				begin	
					load = 1'b1;
					next_state = NG;
				end
			
				else if(timerup && ~S1 && (S2 || S3))
				begin
					value = 8'b00000101;
					load = 1'b1;
					next_state = NY;
			
				else
				begin
					decr <= 1b'1;
					next_state = NG;
				end
			end


		NY:	begin
				if(timer_yellow)
				begin
					value = 8'b00000001;
					load = 1'b1;
					next_state = REDL;
				end
	
				else
				begin
					decr <= 1'b1;
					next_state = NY;
				end
				end


		EWG:	begin
			if(timer_ewg)
			begin
				value = 8'b00000101;
				load = 1'b1;
				next_state = EWY;
			end
			
			else
			begin
				decr <= 1'b1;
				next_state = EWY;
			end

		EWY:	begin
			if(timer_yellow)
				next_state = REDL;

			else
				next_state = EWY;
			end 
		
	endcase
end

endmodule
module trafficlightcntr(Clock, Reset, S1, S2, S3, L1, L2, L3, load, decr, value, timeup)

input Clock;

input Reset;
input
S1,
S2,
S3;

output reg [1:0]
L1,
L2,
L3;

output reg [7:0]  value;

	
wire load, decr;



parameter
	FS	= 6'b000001,
	REDL	= 6'b000010,
	NG	= 6'b000100,
	NY	= 6'b001000,
	EWG	= 6'b010000,
	EWY	= 6'b100000;



parameter
	FAIL	= 2'b00,
	GREEN	= 2'b01,
	YELLOW	= 2'b10,
	RED	= 2'b11;

reg [5:0] state;
reg [5:0] next_state;





always @(posedge Clock, posedge Reset)
begin
	if(Reset) 
	begin
		state = FS;
		value = 1'b1;
		load = 1'b1;
	end

	else
	begin
		load = 1'b0;
		if(timerup)
			decr <= 1'b0;
		state <= next_state;
	end
end

always @(state)
begin
	
	
	case(state)
		FS:	begin
			L1 = FAIL;
			L2 = FAIL;
			L3 = FAIL;
			end

		REDL:	begin
			L1 = RED;			
			L2 = RED;
			L3 = RED;
			end

		NG:	begin
			L1 = GREEN;			
			L2 = RED;
			L3 = RED;
			end


		NY:	begin
			L1 = YELLOW;			
			L2 = RED;
			L3 = RED;
			end


		EWG:	begin
			L1 = RED;			
			L2 = GREEN;
			L3 = GREEN;
			end

		EWY:	begin
			L1 = RED;			
			L2 = YELLOW;
			L3 = YELLOW;
			end
	endcase
end



always @(state or next_state)				
begin
	case(state)
					

		REDL:	begin
				if(timerup && S1)
				begin
					value = 8'b00101101;
					load = 1'b1;
					next_state = NG;
				end
				

			`	else
				begin
					decr <= 1'b1;
					next_state = REDL;
				end
			end
	 
		NG:	begin
				if(timerup && S1 && ~S2 && ~S3)
				begin	
					load = 1'b1;
					next_state = NG;
				end
			
				else if(timerup && ~S1 && (S2 || S3))
				begin
					value = 8'b00000101;
					load = 1'b1;
					next_state = NY;
			
				else
				begin
					decr <= 1b'1;
					next_state = NG;
				end
			end


		NY:	begin
				if(timer_yellow)
				begin
					value = 8'b00000001;
					load = 1'b1;
					next_state = REDL;
				end
	
				else
				begin
					decr <= 1'b1;
					next_state = NY;
				end
				end


		EWG:	begin
			if(timer_ewg)
			begin
				value = 8'b00000101;
				load = 1'b1;
				next_state = EWY;
			end
			
			else
			begin
				decr <= 1'b1;
				next_state = EWY;
			end

		EWY:	begin
			if(timer_yellow)
				next_state = REDL;

			else
				next_state = EWY;
			end 
		
	endcase
end

endmodule