data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v
1: b'%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:3: Cannot find include file: ../define/bus.v\n`include "../define/bus.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149848590/src/cpu/core/registers,data/full_repos/permissive/149848590/../define/bus.v\n             data/full_repos/permissive/149848590/src/cpu/core/registers,data/full_repos/permissive/149848590/../define/bus.v.v\n             data/full_repos/permissive/149848590/src/cpu/core/registers,data/full_repos/permissive/149848590/../define/bus.v.sv\n             ../define/bus.v\n             ../define/bus.v.v\n             ../define/bus.v.sv\n             obj_dir/../define/bus.v\n             obj_dir/../define/bus.v.v\n             obj_dir/../define/bus.v.sv\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:4: Cannot find include file: ../define/cp0.v\n`include "../define/cp0.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:7: Define or directive not defined: \'`CP0_ADDR_BUS\'\n    input [`CP0_ADDR_BUS] cp0_read_addr,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`CP0_ADDR_BUS] cp0_read_addr,\n                        ^\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:9: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] cp0_status_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:10: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] cp0_cause_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:11: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] cp0_epc_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:12: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] cp0_ebase_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:13: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] cp0_read_data_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:16: Define or directive not defined: \'`CP0_ADDR_BUS\'\n    input [`CP0_ADDR_BUS] mem_cp0_write_addr,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:17: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] mem_cp0_data_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:20: Define or directive not defined: \'`CP0_ADDR_BUS\'\n    input [`CP0_ADDR_BUS] wb_cp0_write_addr,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:21: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] wb_cp0_data_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:23: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] cp0_status_out,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:24: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] cp0_cause_out,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:25: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] cp0_epc_out,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:26: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] cp0_ebase_out,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:27: Define or directive not defined: \'`DATA_BUS\'\n    output reg[`DATA_BUS] cp0_read_data_out\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:45: Define or directive not defined: \'`CP0_REG_STATUS\'\n            && wb_cp0_write_addr == `CP0_REG_STATUS ?\n                                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:48: Define or directive not defined: \'`CP0_REG_CAUSE\'\n            && wb_cp0_write_addr == `CP0_REG_CAUSE ?\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:51: Define or directive not defined: \'`CP0_REG_EPC\'\n            && wb_cp0_write_addr == `CP0_REG_EPC ?\n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/CP0ReadProxy.v:54: Define or directive not defined: \'`CP0_REG_EBASE\'\n            && wb_cp0_write_addr == `CP0_REG_EBASE ?\n                                    ^~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module CP0ReadProxy(
    input [`CP0_ADDR_BUS] cp0_read_addr,

    input [`DATA_BUS] cp0_status_in,
    input [`DATA_BUS] cp0_cause_in,
    input [`DATA_BUS] cp0_epc_in,
    input [`DATA_BUS] cp0_ebase_in,
    input [`DATA_BUS] cp0_read_data_in,

    input mem_cp0_write_flag,
    input [`CP0_ADDR_BUS] mem_cp0_write_addr,
    input [`DATA_BUS] mem_cp0_data_in,

    input wb_cp0_write_flag,
    input [`CP0_ADDR_BUS] wb_cp0_write_addr,
    input [`DATA_BUS] wb_cp0_data_in,

    output [`DATA_BUS] cp0_status_out,
    output [`DATA_BUS] cp0_cause_out,
    output [`DATA_BUS] cp0_epc_out,
    output [`DATA_BUS] cp0_ebase_out,
    output reg[`DATA_BUS] cp0_read_data_out
);


    always @(*) begin
        if (mem_cp0_write_flag && mem_cp0_write_addr == cp0_read_addr) begin
            cp0_read_data_out <= mem_cp0_data_in;
        end
        else if (wb_cp0_write_flag && wb_cp0_write_addr == cp0_read_addr) begin
            cp0_read_data_out <= wb_cp0_data_in;
        end
        else begin
            cp0_read_data_out <= cp0_read_data_in;
        end
    end


    assign cp0_status_out = wb_cp0_write_flag
            && wb_cp0_write_addr == `CP0_REG_STATUS ?
            wb_cp0_data_in : cp0_status_in;
    assign cp0_cause_out = wb_cp0_write_flag
            && wb_cp0_write_addr == `CP0_REG_CAUSE ?
            wb_cp0_data_in : cp0_cause_in;
    assign cp0_epc_out = wb_cp0_write_flag
            && wb_cp0_write_addr == `CP0_REG_EPC ?
            wb_cp0_data_in : cp0_epc_in;
    assign cp0_ebase_out = wb_cp0_write_flag
            && wb_cp0_write_addr == `CP0_REG_EBASE ?
            wb_cp0_data_in : cp0_ebase_in;

endmodule
module CP0ReadProxy(
    input [`CP0_ADDR_BUS] cp0_read_addr,

    input [`DATA_BUS] cp0_status_in,
    input [`DATA_BUS] cp0_cause_in,
    input [`DATA_BUS] cp0_epc_in,
    input [`DATA_BUS] cp0_ebase_in,
    input [`DATA_BUS] cp0_read_data_in,

    input mem_cp0_write_flag,
    input [`CP0_ADDR_BUS] mem_cp0_write_addr,
    input [`DATA_BUS] mem_cp0_data_in,

    input wb_cp0_write_flag,
    input [`CP0_ADDR_BUS] wb_cp0_write_addr,
    input [`DATA_BUS] wb_cp0_data_in,

    output [`DATA_BUS] cp0_status_out,
    output [`DATA_BUS] cp0_cause_out,
    output [`DATA_BUS] cp0_epc_out,
    output [`DATA_BUS] cp0_ebase_out,
    output reg[`DATA_BUS] cp0_read_data_out
);



    always @(*) begin
        if (mem_cp0_write_flag && mem_cp0_write_addr == cp0_read_addr) begin
            cp0_read_data_out <= mem_cp0_data_in;
        end
        else if (wb_cp0_write_flag && wb_cp0_write_addr == cp0_read_addr) begin
            cp0_read_data_out <= wb_cp0_data_in;
        end
        else begin
            cp0_read_data_out <= cp0_read_data_in;
        end
    end


    assign cp0_status_out = wb_cp0_write_flag
            && wb_cp0_write_addr == `CP0_REG_STATUS ?
            wb_cp0_data_in : cp0_status_in;
    assign cp0_cause_out = wb_cp0_write_flag
            && wb_cp0_write_addr == `CP0_REG_CAUSE ?
            wb_cp0_data_in : cp0_cause_in;
    assign cp0_epc_out = wb_cp0_write_flag
            && wb_cp0_write_addr == `CP0_REG_EPC ?
            wb_cp0_data_in : cp0_epc_in;
    assign cp0_ebase_out = wb_cp0_write_flag
            && wb_cp0_write_addr == `CP0_REG_EBASE ?
            wb_cp0_data_in : cp0_ebase_in;

endmodule