data/full_repos/permissive/212495825/src/gaplus_io.v
1: b'%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:356: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'INP\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h0: out <= INP;  \n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:357: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h1: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'hF;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:357: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h1: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'hF;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'he\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:359: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h3: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'h1;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:359: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'h1\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h3: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'h1;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:276: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_add\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp1\n    regs[4\'h0] <= credit_add;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:277: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_sub\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp1\n    regs[4\'h1] <= credit_sub;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:144: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_add\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp0\n    regs[4\'h2] <= credit_add;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:145: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_sub\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp0\n    regs[4\'h3] <= credit_sub;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:46: Output port connection \'rd\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'iocust_rd\' generates 4 bits.\n                                                                       : ... In instance GAPLUS_IO\nGAPLUS_IO_CUS2 iocust( reset, clk, iocust_cs, cpu_ad[3:0], iocust_rd, cpu_wd, cpu_wr,  pcm_kick, INP2 );\n                                                           ^~~~~~~~~\n%Error: Exiting due to 13 warning(s)\n'
module GAPLUS_IO_CUS1
(
	input			 reset,
	input			 clk,
	input			 VB,
	input			 cs,
	input  [3:0] adrs,
	output [3:0] rd,
	input  [3:0] wd,
	input			 we,

	input [31:0] INPORT
);

reg [3:0] regs [0:15];
reg [3:0] out;

reg		[7:0]	credits;
reg		[7:0]	credit_add, credit_sub;

reg	  [31:0]	pINPORT,fINPORT;
wire	  [31:0]	iINPORT = ( fINPORT ^ pINPORT ) & fINPORT;

wire		[3:0]	CREDIT_ONES, CREDIT_TENS;
BCDCONV	creditsBCD( credits, CREDIT_ONES, CREDIT_TENS );

reg pVB;

always @ ( posedge clk or posedge reset ) begin

	if ( reset ) begin
		out <= 4'hF;
		credits <= 0;

		pVB <= 1'b0;
	end
	else begin

		if (~VB) pVB <= 1'b0;
		else if (~pVB) begin

			if (regs[4'h8]==4'h3) begin
				credit_add = 0;
				credit_sub = 0;

				if ( iINPORT[0] & ( credits < 99 ) ) begin
					credit_add = 8'h01;
					credits = credits + 1;
				end

				if ( regs[4'h9] == 0 ) begin
					if ( ( credits >= 2 ) & iINPORT[15] ) begin
						credit_sub = 8'h02;
						credits = credits - 2;
					end else if ( ( credits >= 1 ) & iINPORT[14] ) begin
						credit_sub = 8'h01;
						credits = credits - 1;
					end
				end
			end

			pINPORT <= fINPORT;
			fINPORT <= INPORT;

			pVB <= 1'b1;
		end

		if (cs) begin
			if (we) regs[adrs] <= wd;
			else out <= regs[adrs];
		end

		case ( regs[4'h8] )

			4'h1: begin

				regs[4'h4] <= fINPORT[3:0];
				regs[4'h5] <= fINPORT[7:4];
				regs[4'h6] <= fINPORT[11:8];
				regs[4'h7] <= fINPORT[15:12];

			end



			4'h3: begin

				regs[4'h0] <= credit_add;
				regs[4'h1] <= credit_sub;
				regs[4'h2] <= CREDIT_TENS;
				regs[4'h3] <= CREDIT_ONES;

				regs[4'h4] <= fINPORT[7:4];
				regs[4'h5] <= { fINPORT[14], iINPORT[14], fINPORT[12], iINPORT[12] };
				regs[4'h6] <= INPORT[11:8];
				regs[4'h7] <= { fINPORT[15], iINPORT[15], fINPORT[13], iINPORT[13] };

			end

			4'h4: begin

				regs[4'h0] <= fINPORT[3:0];
				regs[4'h2] <= fINPORT[7:4];
				regs[4'h4] <= fINPORT[11:8];
				regs[4'h6] <= fINPORT[15:12];

				regs[4'h1] <= fINPORT[19:16];
				regs[4'h3] <= fINPORT[23:20];
				regs[4'h5] <= fINPORT[27:24];
				regs[4'h7] <= fINPORT[31:28];

			end

			4'h5: begin
				regs[4'h0] <= 4'hF;
				regs[4'h1] <= 4'hF;
			end

			default: ;

		endcase

	end

end

assign rd = out;

endmodule
module GAPLUS_IO_CUS1
(
	input			 reset,
	input			 clk,
	input			 VB,
	input			 cs,
	input  [3:0] adrs,
	output [3:0] rd,
	input  [3:0] wd,
	input			 we,

	input [31:0] INPORT
);


reg [3:0] regs [0:15];
reg [3:0] out;

reg		[7:0]	credits;
reg		[7:0]	credit_add, credit_sub;

reg	  [31:0]	pINPORT,fINPORT;
wire	  [31:0]	iINPORT = ( fINPORT ^ pINPORT ) & fINPORT;

wire		[3:0]	CREDIT_ONES, CREDIT_TENS;
BCDCONV	creditsBCD( credits, CREDIT_ONES, CREDIT_TENS );

reg pVB;

always @ ( posedge clk or posedge reset ) begin

	if ( reset ) begin
		out <= 4'hF;
		credits <= 0;

		pVB <= 1'b0;
	end
	else begin

		if (~VB) pVB <= 1'b0;
		else if (~pVB) begin

			if (regs[4'h8]==4'h3) begin
				credit_add = 0;
				credit_sub = 0;

				if ( iINPORT[0] & ( credits < 99 ) ) begin
					credit_add = 8'h01;
					credits = credits + 1;
				end

				if ( regs[4'h9] == 0 ) begin
					if ( ( credits >= 2 ) & iINPORT[15] ) begin
						credit_sub = 8'h02;
						credits = credits - 2;
					end else if ( ( credits >= 1 ) & iINPORT[14] ) begin
						credit_sub = 8'h01;
						credits = credits - 1;
					end
				end
			end

			pINPORT <= fINPORT;
			fINPORT <= INPORT;

			pVB <= 1'b1;
		end

		if (cs) begin
			if (we) regs[adrs] <= wd;
			else out <= regs[adrs];
		end

		case ( regs[4'h8] )

			4'h1: begin

				regs[4'h4] <= fINPORT[3:0];
				regs[4'h5] <= fINPORT[7:4];
				regs[4'h6] <= fINPORT[11:8];
				regs[4'h7] <= fINPORT[15:12];

			end



			4'h3: begin

				regs[4'h0] <= credit_add;
				regs[4'h1] <= credit_sub;
				regs[4'h2] <= CREDIT_TENS;
				regs[4'h3] <= CREDIT_ONES;

				regs[4'h4] <= fINPORT[7:4];
				regs[4'h5] <= { fINPORT[14], iINPORT[14], fINPORT[12], iINPORT[12] };
				regs[4'h6] <= INPORT[11:8];
				regs[4'h7] <= { fINPORT[15], iINPORT[15], fINPORT[13], iINPORT[13] };

			end

			4'h4: begin

				regs[4'h0] <= fINPORT[3:0];
				regs[4'h2] <= fINPORT[7:4];
				regs[4'h4] <= fINPORT[11:8];
				regs[4'h6] <= fINPORT[15:12];

				regs[4'h1] <= fINPORT[19:16];
				regs[4'h3] <= fINPORT[23:20];
				regs[4'h5] <= fINPORT[27:24];
				regs[4'h7] <= fINPORT[31:28];

			end

			4'h5: begin
				regs[4'h0] <= 4'hF;
				regs[4'h1] <= 4'hF;
			end

			default: ;

		endcase

	end

end

assign rd = out;

endmodule