data/full_repos/permissive/135077285/dataMemory.v
data/verilator_xmls/f7b44b48-feab-46ce-8373-b5b1f345b914.xml
module dataMemory (
  input wire [31:0] address,
  input wire [31:0] writeData,
  input wire memRead,
  input wire memWrite,
  output reg [31:0] readData
);

  reg [31:0] memory [0:15];

  initial begin
    readData <= 0;
  end

  always @(memRead or memWrite) begin
    if (memWrite)
      begin
        memory[address] <= readData;
      end

    if (memRead)
      begin
        readData <= memory[address];
      end
  end


endmodule
module dataMemory (
  input wire [31:0] address,
  input wire [31:0] writeData,
  input wire memRead,
  input wire memWrite,
  output reg [31:0] readData
);


  reg [31:0] memory [0:15];

  initial begin
    readData <= 0;
  end

  always @(memRead or memWrite) begin
    if (memWrite)
      begin
        memory[address] <= readData;
      end

    if (memRead)
      begin
        readData <= memory[address];
      end
  end


endmodule