data/full_repos/permissive/159029085/src/cpld_fifo.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/159029085/src/cpld_fifo.v:239: Signal definition not found, creating implicitly: \'slave_rd\'\n                                                                           : ... Suggested alternative: \'slave_rd_b\'\n                      .oeb(slave_rd),\n                           ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module lvc374(
              input clk,
              input oeb,
              input [7:0] d,
              output [7:0] q
              );

  reg[7:0]  q_q;
  
  always @ (posedge clk)
    q_q <= d;

  assign q = (!oeb) ? q_q : 8'bz;

endmodule
module lvc374(
              input clk,
              input oeb,
              input [7:0] d,
              output [7:0] q
              );


  reg[7:0]  q_q;
  
  always @ (posedge clk)
    q_q <= d;

  assign q = (!oeb) ? q_q : 8'bz;

endmodule