data/full_repos/permissive/210844779/lab4/4.3.2/d.v
data/verilator_xmls/17841a33-dda5-4373-87a7-b46ca1d98a03.xml
module dff(d,clk,en,q);
  
  input d,clk,en;
  output reg q;
  
  always@(posedge clk)
  begin
    if (en)
      q<=d;
      
  end
  
endmodule
module dff(d,clk,en,q);

  
  input d,clk,en;
  output reg q;
  
  always@(posedge clk)
  begin
    if (en)
      q<=d;
      
  end
  
endmodule