data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_stop_time)\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:137: Unsupported: Ignoring delay on this delayed statement.\n      #25241995.176\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:144: Unsupported: Ignoring delay on this delayed statement.\n      #20.176\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:146: Unsupported: Ignoring delay on this delayed statement.\n      #25098147\n      ^\n%Error: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:156: Too many digits for 32 bit number: 25241995176\n        ... As that number was unsized (\'d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n        ... Suggest adding a size to it.\n    #25241995176 $finish;\n     ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:156: Unsupported: Ignoring delay on this delayed statement.\n    #25241995176 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:193: Unsupported: Ignoring delay on this delayed statement.\n      #((jRise + maxLH - minLH));\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:203: Unsupported: Ignoring delay on this delayed statement.\n      #((jFall + maxHL - minHL));\n      ^\n%Error: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:210: syntax error, unexpected \'@\'\n    @(posedge tb_status[0])\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:233: Unsupported: Ignoring delay on this delayed statement.\n        #(offset + (minLH - jRise/2))\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:240: Unsupported: Ignoring delay on this delayed statement.\n        #((jRise/2 + maxLH) + (offset))\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:242: Unsupported: Ignoring delay on this delayed statement.\n        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2)))\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:245: Unsupported: Ignoring delay on this delayed statement.\n        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2)))\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:252: Unsupported: Ignoring delay on this delayed statement.\n        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2)))\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:255: Unsupported: Ignoring delay on this delayed statement.\n        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2)))\n        ^\n%Error: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:286: syntax error, unexpected $end, expecting \')\'\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_clock_minmax(tb_status, CLK, offset_bits, period_bits, duty_bits, minLH_bits, maxLH_bits, minHL_bits, maxHL_bits, jRise_bits, jFall_bits);
  parameter initialize = 0;

  input [1:0] tb_status;
  output CLK;
  input [63:0] offset_bits;
  input [63:0] period_bits;
  input [63:0] duty_bits;
  input [63:0] minLH_bits;
  input [63:0] maxLH_bits;
  input [63:0] minHL_bits;
  input [63:0] maxHL_bits;
  input [63:0] jRise_bits;
  input [63:0] jFall_bits;

  reg  CLK;
  real offset;
  real period;
  real duty;
  real minLH;
  real maxLH;
  real minHL;
  real maxHL;
  real jRise;
  real jFall;
  real CLK_high;
  real CLK_low;
 
  task DriveLHInvalidRegion;
    begin
    if ( (jRise + maxLH - minLH) > 0.0 )
      begin
      CLK <= 1'bx;
      #((jRise + maxLH - minLH));
      end
    end
  endtask

  task DriveHLInvalidRegion;
    begin
    if ( (jFall + maxHL - minHL) > 0.0 )
      begin
      CLK <= 1'bx;
      #((jFall + maxHL - minHL));
      end
    end
  endtask

  always
    begin
    @(posedge tb_status[0])
    offset = $bitstoreal( offset_bits );
    period = $bitstoreal( period_bits );
    duty  = $bitstoreal( duty_bits );
    minLH = $bitstoreal( minLH_bits );
    maxLH = $bitstoreal( maxLH_bits );
    minHL = $bitstoreal( minHL_bits );
    maxHL = $bitstoreal( maxHL_bits );
    jRise = $bitstoreal( jRise_bits );
    jFall = $bitstoreal( jFall_bits );
    if (period <= 0.0)
      $display("Error: Period for clock %m is invalid (period=%f).  Clock will not be driven", period);
    else if (duty <= 0.0)
      $display("Error: Duty for clock %m is invalid (duty=%f).  Clock will not be driven", duty);
    else
      begin
      CLK_low = period * duty / 100;
      CLK_high = period - CLK_low;
      
      if ( (offset + (minLH - jRise/2)) >= 0.0 )
        begin
        if (initialize)
          CLK <= 1'b0;
        #(offset + (minLH - jRise/2))
        ;
        end
      else
        begin
        if (initialize)
          CLK <= 1'bx;
        #((jRise/2 + maxLH) + (offset))
        CLK <= 1'b1;
        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2)))
        DriveHLInvalidRegion;
        CLK <= 1'b0;
        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2)))
        ;
        end
      while ( tb_status[0] == 1'b1 )
        begin : clock_loop
        DriveLHInvalidRegion;
        CLK <= 1'b1;
        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2)))
        DriveHLInvalidRegion;
        CLK <= 1'b0;
        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2)))
        ;
        end
      end
    end
endmodule
module tb_clock_minmax(tb_status, CLK, offset_bits, period_bits, duty_bits, minLH_bits, maxLH_bits, minHL_bits, maxHL_bits, jRise_bits, jFall_bits);

  parameter initialize = 0;

  input [1:0] tb_status;
  output CLK;
  input [63:0] offset_bits;
  input [63:0] period_bits;
  input [63:0] duty_bits;
  input [63:0] minLH_bits;
  input [63:0] maxLH_bits;
  input [63:0] minHL_bits;
  input [63:0] maxHL_bits;
  input [63:0] jRise_bits;
  input [63:0] jFall_bits;

  reg  CLK;
  real offset;
  real period;
  real duty;
  real minLH;
  real maxLH;
  real minHL;
  real maxHL;
  real jRise;
  real jFall;
  real CLK_high;
  real CLK_low;
 
  task DriveLHInvalidRegion;
    begin
    if ( (jRise + maxLH - minLH) > 0.0 )
      begin
      CLK <= 1'bx;
      #((jRise + maxLH - minLH));
      end
    end
  endtask

  task DriveHLInvalidRegion;
    begin
    if ( (jFall + maxHL - minHL) > 0.0 )
      begin
      CLK <= 1'bx;
      #((jFall + maxHL - minHL));
      end
    end
  endtask

  always
    begin
    @(posedge tb_status[0])
    offset = $bitstoreal( offset_bits );
    period = $bitstoreal( period_bits );
    duty  = $bitstoreal( duty_bits );
    minLH = $bitstoreal( minLH_bits );
    maxLH = $bitstoreal( maxLH_bits );
    minHL = $bitstoreal( minHL_bits );
    maxHL = $bitstoreal( maxHL_bits );
    jRise = $bitstoreal( jRise_bits );
    jFall = $bitstoreal( jFall_bits );
    if (period <= 0.0)
      $display("Error: Period for clock %m is invalid (period=%f).  Clock will not be driven", period);
    else if (duty <= 0.0)
      $display("Error: Duty for clock %m is invalid (duty=%f).  Clock will not be driven", duty);
    else
      begin
      CLK_low = period * duty / 100;
      CLK_high = period - CLK_low;
      
      if ( (offset + (minLH - jRise/2)) >= 0.0 )
        begin
        if (initialize)
          CLK <= 1'b0;
        #(offset + (minLH - jRise/2))
        ;
        end
      else
        begin
        if (initialize)
          CLK <= 1'bx;
        #((jRise/2 + maxLH) + (offset))
        CLK <= 1'b1;
        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2)))
        DriveHLInvalidRegion;
        CLK <= 1'b0;
        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2)))
        ;
        end
      while ( tb_status[0] == 1'b1 )
        begin : clock_loop
        DriveLHInvalidRegion;
        CLK <= 1'b1;
        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2)))
        DriveHLInvalidRegion;
        CLK <= 1'b0;
        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2)))
        ;
        end
      end
    end
endmodule