data/full_repos/permissive/143278/ivltests/pr2172606b.v
 line:20: before: "check"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #1 sel = 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #1 sel = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #1 sel = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'b0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'b1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:97: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'bz; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:102: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:103: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'bx; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:106: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:107: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #1 sel = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:110: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'b0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:111: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:112: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:114: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:115: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'b1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:116: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:117: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:118: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:119: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:120: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'bz; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:121: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:122: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:123: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:124: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:125: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_1 = 1\'bx; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:126: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:127: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:128: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:129: Unsupported: Ignoring delay on this delayed statement.\n    #1 in_0 = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2172606b.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (passed) $display("PASSED");\n    ^\n%Error: Exiting due to 53 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg passed = 1'b1;
  wire out, cout0, cout1;
  reg sel, in_1, in_0;
  reg pout;

`ifdef __ICARUS__


  localparam zz_blend = 1'bz;
`else
  localparam zz_blend = 1'bx;
`endif

  assign cout0 = sel ? 1'bz : in_0;
  assign cout1 = sel ? in_1: 1'bz;
  assign out = sel ? in_1: in_0;

  task automatic check;
    input bit, in_1, in_0;
    input [63:0] comment;
    begin
      if (sel === 1'b1) begin
        if (bit !== in_1) begin
          $display("FAILED: %0s sel = 1'b1, expected %b, got %b",
                   comment, in_1, bit);
          passed = 1'b0;
        end
      end else if (sel === 1'b0) begin
        if (bit !== in_0) begin
          $display("FAILED: %0s sel = 1'b0, expected %b, got %b",
                   comment, in_0, bit);
          passed = 1'b0;
        end
      end else begin
        if (in_0 === 1'bz && in_1 === 1'bz && bit !== zz_blend) begin
          $display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b",
                   comment, in_0, zz_blend, bit);
          passed = 1'b0;
        end else if (in_0 === in_1 && in_0 !== bit) begin
          $display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b",
                   comment, in_0, in_0, bit);
          passed = 1'b0;
        end else if (in_0 !== in_1 && bit !== 1'bx) begin
          $display("FAILED: %0s sel = 1'bx/z & %b %b, expected 1'bx, got %b",
                   comment, in_1, in_0, bit);
          passed = 1'b0;
        end
      end
    end
  endtask


  always @(cout0) begin
    check(cout0, 1'bz, in_0, "CZ 1");
  end


  always @(cout1) begin
    check(cout1, in_1, 1'bz, "CZ 0");
  end


  always @(out) begin
    check(out, in_1, in_0, "CA");
  end


  always @(sel, in_1, in_0) begin
    check(sel ? in_1 : in_0, in_1, in_0, "PR");
  end

  initial begin
    #1 sel = 1'b1;
    #1 in_1 = 1'b0;
    #1 in_1 = 1'b1;
    #1 in_1 = 1'bz;
    #1 in_1 = 1'bx;

    #1 sel = 1'b0;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;

    #1 sel = 1'bx;
    #1 in_1 = 1'b0;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'b1;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'bz;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'bx;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;

    #1 sel = 1'bz;
    #1 in_1 = 1'b0;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'b1;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'bz;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'bx;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;

    #1 if (passed) $display("PASSED");
  end
endmodule
module top;

  reg passed = 1'b1;
  wire out, cout0, cout1;
  reg sel, in_1, in_0;
  reg pout;

`ifdef __ICARUS__


  localparam zz_blend = 1'bz;
`else
  localparam zz_blend = 1'bx;
`endif

  assign cout0 = sel ? 1'bz : in_0;
  assign cout1 = sel ? in_1: 1'bz;
  assign out = sel ? in_1: in_0;

  task automatic check;
    input bit, in_1, in_0;
    input [63:0] comment;
    begin
      if (sel === 1'b1) begin
        if (bit !== in_1) begin
          $display("FAILED: %0s sel = 1'b1, expected %b, got %b",
                   comment, in_1, bit);
          passed = 1'b0;
        end
      end else if (sel === 1'b0) begin
        if (bit !== in_0) begin
          $display("FAILED: %0s sel = 1'b0, expected %b, got %b",
                   comment, in_0, bit);
          passed = 1'b0;
        end
      end else begin
        if (in_0 === 1'bz && in_1 === 1'bz && bit !== zz_blend) begin
          $display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b",
                   comment, in_0, zz_blend, bit);
          passed = 1'b0;
        end else if (in_0 === in_1 && in_0 !== bit) begin
          $display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b",
                   comment, in_0, in_0, bit);
          passed = 1'b0;
        end else if (in_0 !== in_1 && bit !== 1'bx) begin
          $display("FAILED: %0s sel = 1'bx/z & %b %b, expected 1'bx, got %b",
                   comment, in_1, in_0, bit);
          passed = 1'b0;
        end
      end
    end
  endtask


  always @(cout0) begin
    check(cout0, 1'bz, in_0, "CZ 1");
  end


  always @(cout1) begin
    check(cout1, in_1, 1'bz, "CZ 0");
  end


  always @(out) begin
    check(out, in_1, in_0, "CA");
  end


  always @(sel, in_1, in_0) begin
    check(sel ? in_1 : in_0, in_1, in_0, "PR");
  end

  initial begin
    #1 sel = 1'b1;
    #1 in_1 = 1'b0;
    #1 in_1 = 1'b1;
    #1 in_1 = 1'bz;
    #1 in_1 = 1'bx;

    #1 sel = 1'b0;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;

    #1 sel = 1'bx;
    #1 in_1 = 1'b0;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'b1;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'bz;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'bx;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;

    #1 sel = 1'bz;
    #1 in_1 = 1'b0;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'b1;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'bz;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;
    #1 in_1 = 1'bx;
    #1 in_0 = 1'b0;
    #1 in_0 = 1'b1;
    #1 in_0 = 1'bz;
    #1 in_0 = 1'bx;

    #1 if (passed) $display("PASSED");
  end
endmodule