data/full_repos/permissive/183345139/verilog_tutorial/5_PWM_Module/pwm1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/183345139/verilog_tutorial/5_PWM_Module/pwm1.v:51: Operator EQ expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'pwm_count\' generates 7 bits.\n                                                                                            : ... In instance pwm1\n    if (pwm_count == PERIOD_COUNT) begin\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pwm1
(
    input wire clk_16mhz,
    input wire button0,
    input wire button1,
    output wire [7:0] led,


    output reg pwm,
    output wire dir,
    output wire float_n
);


localparam CLK_FREQUENCY = 16_000_000;
localparam PWM_FREQUENCY = 160_000;
localparam PERIOD_COUNT = (CLK_FREQUENCY/PWM_FREQUENCY);
localparam COUNT_BITS = $clog2(PERIOD_COUNT);
localparam DUTY_CYCLE = 20;



assign dir = ~button0;
assign float_n = button1;
assign led = {6'h0,float_n,dir};


reg [COUNT_BITS-1:0] pwm_count;


initial begin

    pwm<=0; 
    pwm_count<=0;
    $display("DUTY_CYCLE: ",DUTY_CYCLE);
    $display("PERIOD_COUNT: ",PERIOD_COUNT);
    $display("COUNT_BITS: ",COUNT_BITS);
end
always @ (posedge clk_16mhz)
begin
    pwm_count <= pwm_count + 1;
    pwm <= 1;
    if (pwm_count >= DUTY_CYCLE) begin
        pwm <= 0;
    end
    if (pwm_count == PERIOD_COUNT) begin
        pwm_count <= 0;
    end
end

endmodule
module pwm1
(
    input wire clk_16mhz,
    input wire button0,
    input wire button1,
    output wire [7:0] led,


    output reg pwm,
    output wire dir,
    output wire float_n
);



localparam CLK_FREQUENCY = 16_000_000;
localparam PWM_FREQUENCY = 160_000;
localparam PERIOD_COUNT = (CLK_FREQUENCY/PWM_FREQUENCY);
localparam COUNT_BITS = $clog2(PERIOD_COUNT);
localparam DUTY_CYCLE = 20;



assign dir = ~button0;
assign float_n = button1;
assign led = {6'h0,float_n,dir};


reg [COUNT_BITS-1:0] pwm_count;


initial begin

    pwm<=0; 
    pwm_count<=0;
    $display("DUTY_CYCLE: ",DUTY_CYCLE);
    $display("PERIOD_COUNT: ",PERIOD_COUNT);
    $display("COUNT_BITS: ",COUNT_BITS);
end
always @ (posedge clk_16mhz)
begin
    pwm_count <= pwm_count + 1;
    pwm <= 1;
    if (pwm_count >= DUTY_CYCLE) begin
        pwm <= 0;
    end
    if (pwm_count == PERIOD_COUNT) begin
        pwm_count <= 0;
    end
end

endmodule