data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary/TestDiv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary/TestDiv.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary/TestDiv.v:64: Unsupported: Ignoring delay on this delayed statement.\n  forever #2 i_clk = ~i_clk;\n          ^\n%Error: data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary/TestDiv.v:39: Cannot find file containing module: \'qdiv\'\n qdiv uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary,data/full_repos/permissive/114714167/qdiv\n             data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary,data/full_repos/permissive/114714167/qdiv.v\n             data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary,data/full_repos/permissive/114714167/qdiv.sv\n             qdiv\n             qdiv.v\n             qdiv.sv\n             obj_dir/qdiv\n             obj_dir/qdiv.v\n             obj_dir/qdiv.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestDiv;


	reg [31:0] i_dividend;
	reg [31:0] i_divisor;
	reg i_start;
	reg i_clk;


	wire [31:0] o_quotient_out;
	wire o_complete;
	wire o_overflow;


	qdiv uut (
		.i_dividend(i_dividend), 
		.i_divisor(i_divisor), 
		.i_start(i_start), 
		.i_clk(i_clk), 
		.o_quotient_out(o_quotient_out), 
		.o_complete(o_complete), 
		.o_overflow(o_overflow)
	);

	reg [10:0]	count;

	initial begin

		i_dividend = 1;
		i_divisor = 1;
		i_start = 0;
		i_clk = 0;
		
		count <= 0;


		#100;


		forever #2 i_clk = ~i_clk;
	end
        
		always @(posedge i_clk) begin
			if (count == 47) begin
				count <= 0;
				i_start <= 1'b1;
				end
			else begin				
				count <= count + 1;
				i_start <= 1'b0;
				end
			end

		always @(count) begin
			if (count == 47) begin
				if ( i_divisor > 32'h1FFFFFFF ) begin
					i_divisor <= 1;
					i_dividend = (i_dividend << 1) + 3;
					end
				else
					i_divisor = (i_divisor << 1) + 1;
				end
			end
			
	always @(posedge o_complete)
		$display ("%b,%b,%b, %b", i_dividend, i_divisor, o_quotient_out, o_overflow);

endmodule
module TestDiv;



	reg [31:0] i_dividend;
	reg [31:0] i_divisor;
	reg i_start;
	reg i_clk;


	wire [31:0] o_quotient_out;
	wire o_complete;
	wire o_overflow;


	qdiv uut (
		.i_dividend(i_dividend), 
		.i_divisor(i_divisor), 
		.i_start(i_start), 
		.i_clk(i_clk), 
		.o_quotient_out(o_quotient_out), 
		.o_complete(o_complete), 
		.o_overflow(o_overflow)
	);

	reg [10:0]	count;

	initial begin

		i_dividend = 1;
		i_divisor = 1;
		i_start = 0;
		i_clk = 0;
		
		count <= 0;


		#100;


		forever #2 i_clk = ~i_clk;
	end
        
		always @(posedge i_clk) begin
			if (count == 47) begin
				count <= 0;
				i_start <= 1'b1;
				end
			else begin				
				count <= count + 1;
				i_start <= 1'b0;
				end
			end

		always @(count) begin
			if (count == 47) begin
				if ( i_divisor > 32'h1FFFFFFF ) begin
					i_divisor <= 1;
					i_dividend = (i_dividend << 1) + 3;
					end
				else
					i_divisor = (i_divisor << 1) + 1;
				end
			end
			
	always @(posedge o_complete)
		$display ("%b,%b,%b, %b", i_dividend, i_divisor, o_quotient_out, o_overflow);

endmodule