data/full_repos/permissive/205673649/MIPS/Source/banco_registros.v
1: b'%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/banco_registros.v:48: Operator ADD expects 32 bits on the LHS, but LHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                     : ... In instance banco_registros\n            registros[indice] <= {LEN{1\'b0+indice}};\n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/banco_registros.v:48: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1024 bits.\n                                                                                     : ... In instance banco_registros\n            registros[indice] <= {LEN{1\'b0+indice}};\n                              ^~\n%Error: Exiting due to 2 warning(s)\n'
module banco_registros
#(
    parameter LEN = 32,
    parameter CANTIDAD_REGISTROS=32,
    parameter NB_ADDRESS_REGISTROS=$clog2(CANTIDAD_REGISTROS)
)
(
    input i_clk,
    input i_rst,
    input [NB_ADDRESS_REGISTROS-1:0] i_read_reg_1,
    input [NB_ADDRESS_REGISTROS-1:0] i_read_reg_2,
    input [NB_ADDRESS_REGISTROS-1:0] i_write_reg,
    input i_reg_write_ctrl,
    input [LEN-1:0] i_write_data,
    output [LEN-1:0] o_wire_data1,
    output reg [LEN-1:0] o_read_data_1,
    output reg [LEN-1:0] o_read_data_2
);

reg [CANTIDAD_REGISTROS-1:0] registros [LEN-1:0];

generate
    integer indice;
    initial
        for (indice=0; indice < CANTIDAD_REGISTROS; indice =indice+1)
            registros[indice] <= {LEN{1'b0+indice}};
endgenerate

assign o_wire_data1 = registros[i_read_reg_1];

always @(negedge i_clk)
begin
    if(!i_rst)
    begin
        o_read_data_1 <= 0;
        o_read_data_2 <= 0;
    end
    
    else
    begin
        o_read_data_1 <= registros[i_read_reg_1];
        o_read_data_2 <= registros[i_read_reg_2];
    end
end

always @(posedge i_clk)
begin
    if(i_reg_write_ctrl)
        registros[i_write_reg] <= i_write_data;
    
    else
       registros[i_write_reg] <= registros[i_write_reg];
end
endmodule
module banco_registros
#(
    parameter LEN = 32,
    parameter CANTIDAD_REGISTROS=32,
    parameter NB_ADDRESS_REGISTROS=$clog2(CANTIDAD_REGISTROS)
)
(
    input i_clk,
    input i_rst,
    input [NB_ADDRESS_REGISTROS-1:0] i_read_reg_1,
    input [NB_ADDRESS_REGISTROS-1:0] i_read_reg_2,
    input [NB_ADDRESS_REGISTROS-1:0] i_write_reg,
    input i_reg_write_ctrl,
    input [LEN-1:0] i_write_data,
    output [LEN-1:0] o_wire_data1,
    output reg [LEN-1:0] o_read_data_1,
    output reg [LEN-1:0] o_read_data_2
);


reg [CANTIDAD_REGISTROS-1:0] registros [LEN-1:0];

generate
    integer indice;
    initial
        for (indice=0; indice < CANTIDAD_REGISTROS; indice =indice+1)
            registros[indice] <= {LEN{1'b0+indice}};
endgenerate

assign o_wire_data1 = registros[i_read_reg_1];

always @(negedge i_clk)
begin
    if(!i_rst)
    begin
        o_read_data_1 <= 0;
        o_read_data_2 <= 0;
    end
    
    else
    begin
        o_read_data_1 <= registros[i_read_reg_1];
        o_read_data_2 <= registros[i_read_reg_2];
    end
end

always @(posedge i_clk)
begin
    if(i_reg_write_ctrl)
        registros[i_write_reg] <= i_write_data;
    
    else
       registros[i_write_reg] <= registros[i_write_reg];
end
endmodule