data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v
1: b'%Error: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:174: Unsupported: wait statements\n  wait (tb_rst);    \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n  # COMB_DELAY;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:193: Unsupported: wait statements\n  wait (!tb_rst);   \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n  # COMB_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n  # COMB_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n  # COMB_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n      # COMB_DELAY;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n      # COMB_DELAY;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:241: Unsupported: Ignoring delay on this delayed statement.\n      # COMB_DELAY;\n      ^\n%Error: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:254: Unsupported: wait statements\n    wait (tb_old_ack != uut_ispl_ack);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n    # SPL_HSDLY;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:389: Unsupported: Ignoring delay on this delayed statement.\n  # INIT_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:393: Unsupported: Ignoring delay on this delayed statement.\n  # RST_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:395: Unsupported: Ignoring delay on this delayed statement.\n  # COMB_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:410: Unsupported: Ignoring delay on this delayed statement.\n    # UUT_CLK0_HPER;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:426: Unsupported: Ignoring delay on this delayed statement.\n    # UUT_CLK1_HPER;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:441: Unsupported: Ignoring delay on this delayed statement.\n  # INIT_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:445: Unsupported: Ignoring delay on this delayed statement.\n  # RST_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:447: Unsupported: Ignoring delay on this delayed statement.\n  # COMB_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_receiver_sync_fifo_tb.v:462: Unsupported: Ignoring delay on this delayed statement.\n    # TB_CLK_HPER;\n    ^\n%Error: Exiting due to 3 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spio_spinnaker_link_receiver_sync_fifo_tb ();



localparam UUT_CLK0_HPER = (6.666 / 2);
localparam UUT_CLK1_HPER = (13.333 / 2);
localparam TB_CLK_HPER   = (13.333 / 2);


localparam SPL_HSDLY = 23;

localparam INIT_DELAY = (10 * TB_CLK_HPER);
localparam RST_DELAY  = (51 * TB_CLK_HPER);

localparam COMB_DELAY = 2;





reg         tb_rst;
reg         tb_clk;

reg         uut_rst;
reg         uut_clk0;
reg         uut_clk1;

reg   [6:0] uut_ispl_data;
wire        uut_ispl_ack;

wire [71:0] uut_opkt_data;
wire        uut_opkt_vld;
reg         uut_opkt_rdy;

wire [71:0] uut0_uut1_opkt_data;
wire        uut0_uut1_opkt_vld;
wire        uut0_uut1_opkt_rdy;

wire [71:0] tb_ipkt;
wire  [7:0] tb_ipkt_hdr; 
reg   [1:0] tb_ipkt_type; 
wire        tb_ipkt_prty; 
reg  [31:0] tb_ipkt_key;
reg  [31:0] tb_ipkt_pld;
reg         tb_ipkt_send_pld;
wire        tb_ipkt_send_eop;

reg   [6:0] tb_old_data;
reg         tb_old_ack;

reg   [4:0] tb_flt_cnt;

wire  [7:0] tb_opkt_hdr; 
wire [31:0] tb_opkt_key;
wire [31:0] tb_opkt_pld;

reg         tb_bad_pkt;

reg  [71:0] tb_fifo_pkt [0:7];
reg   [2:0] tb_fifo_rdp;
reg   [2:0] tb_fifo_wrp;

reg [31:0] tb_pkt_cnt;
reg        tb_cnt_on;
reg [31:0] tb_cycle_cnt;
reg [31:0] tb_start_cnt;









function [6:0] encode_nrz_2of7 ;
  input [4:0] data;
  input [6:0] old_data;

  casex (data)
    5'b00000 : encode_nrz_2of7 = old_data ^ 7'b0010001;
    5'b00001 : encode_nrz_2of7 = old_data ^ 7'b0010010;
    5'b00010 : encode_nrz_2of7 = old_data ^ 7'b0010100;
    5'b00011 : encode_nrz_2of7 = old_data ^ 7'b0011000;
    5'b00100 : encode_nrz_2of7 = old_data ^ 7'b0100001;
    5'b00101 : encode_nrz_2of7 = old_data ^ 7'b0100010;
    5'b00110 : encode_nrz_2of7 = old_data ^ 7'b0100100;
    5'b00111 : encode_nrz_2of7 = old_data ^ 7'b0101000;
    5'b01000 : encode_nrz_2of7 = old_data ^ 7'b1000001;
    5'b01001 : encode_nrz_2of7 = old_data ^ 7'b1000010;
    5'b01010 : encode_nrz_2of7 = old_data ^ 7'b1000100;
    5'b01011 : encode_nrz_2of7 = old_data ^ 7'b1001000;
    5'b01100 : encode_nrz_2of7 = old_data ^ 7'b0000011;
    5'b01101 : encode_nrz_2of7 = old_data ^ 7'b0000110;
    5'b01110 : encode_nrz_2of7 = old_data ^ 7'b0001100;
    5'b01111 : encode_nrz_2of7 = old_data ^ 7'b0001001;
    5'b1xxxx : encode_nrz_2of7 = old_data ^ 7'b1100000;
    default  : encode_nrz_2of7 = 7'bxxxxxxx;
  endcase
endfunction





spio_spinnaker_link_receiver uut0
(
  .CLK_IN           (uut_clk0),
  .RESET_IN         (uut_rst),


  .SL_DATA_2OF7_IN  (uut_ispl_data),
  .SL_ACK_OUT       (uut_ispl_ack),


  .PKT_DATA_OUT     (uut0_uut1_opkt_data),
  .PKT_VLD_OUT      (uut0_uut1_opkt_vld),
  .PKT_RDY_IN       (uut0_uut1_opkt_rdy)
);


spio_hss_multiplexer_pkt_fifo_sync uut1
(
  .RESET_IN     (uut_rst),
  .WCLK_IN      (uut_clk0),
  .RCLK_IN      (uut_clk1),


  .SFI_DATA_IN  (uut0_uut1_opkt_data),
  .SFI_VLD_IN   (uut0_uut1_opkt_vld),
  .SFI_RDY_OUT  (uut0_uut1_opkt_rdy),


  .SFO_DATA_OUT (uut_opkt_data),
  .SFO_VLD_OUT  (uut_opkt_vld),
  .SFO_RDY_IN   (uut_opkt_rdy)
);






initial
begin
  wait (tb_rst);

  # COMB_DELAY;


  uut_ispl_data = 0;
  tb_old_data = 0;


  tb_ipkt_type = 0;
  tb_ipkt_key = 32'h0000_0001;
  tb_ipkt_pld = 32'ha5a5_a5a5;
  tb_ipkt_send_pld = 1'b0;


  tb_fifo_wrp = 0;

  tb_flt_cnt = 0;

  wait (!tb_rst);

  # COMB_DELAY;
   

  tb_fifo_pkt[tb_fifo_wrp] = tb_ipkt;

  # COMB_DELAY;


  tb_fifo_wrp = tb_fifo_wrp + 1;

  # COMB_DELAY;

  forever
  begin

    if (tb_ipkt_send_eop)
    begin

      uut_ispl_data = encode_nrz_2of7 (`EOP, tb_old_data);


      tb_ipkt_type = tb_ipkt_type + 1;
      tb_ipkt_key = tb_ipkt_key + 1;
      tb_ipkt_pld = tb_ipkt_pld + 1;
      if (tb_pkt_cnt > 13) tb_ipkt_send_pld = 1;

      # COMB_DELAY;


      tb_fifo_pkt[tb_fifo_wrp] = tb_ipkt;

      # COMB_DELAY;


      tb_fifo_wrp <= tb_fifo_wrp + 1;


      tb_flt_cnt = 0;
    end
    else
    begin

      uut_ispl_data = encode_nrz_2of7 (tb_ipkt[(tb_flt_cnt * 4) +: 4],
                                        tb_old_data
                                      );

      # COMB_DELAY;


      tb_flt_cnt = tb_flt_cnt + 1;
    end


    tb_old_data = uut_ispl_data;


    tb_old_ack = uut_ispl_ack;


    wait (tb_old_ack != uut_ispl_ack);

    # SPL_HSDLY;
  end
end





assign tb_ipkt = {tb_ipkt_pld, tb_ipkt_key, tb_ipkt_hdr};





assign tb_ipkt_hdr = {tb_ipkt_type, 4'b0000, tb_ipkt_send_pld, tb_ipkt_prty};





assign tb_ipkt_prty = tb_ipkt_send_pld
                        ? ^(tb_ipkt_hdr[7:1] ^ tb_ipkt_key ^ tb_ipkt_pld)
                        : ~(^(tb_ipkt_hdr[7:1] ^ tb_ipkt_key));





assign tb_ipkt_send_eop = (!tb_ipkt_hdr[1] && (tb_flt_cnt == 10))
                            || (tb_flt_cnt == 18);





always @ (posedge tb_clk or posedge tb_rst)
  if (tb_rst)
    uut_opkt_rdy <= # COMB_DELAY 1'b0;
  else
    if (uut_opkt_vld && uut_opkt_rdy && (tb_start_cnt != 0))
      uut_opkt_rdy <= # COMB_DELAY 1'b0;
    else if (tb_cycle_cnt == 0)
      uut_opkt_rdy <= # COMB_DELAY 1'b1;


always @ (posedge tb_clk or posedge tb_rst)
  if (tb_rst)
    tb_pkt_cnt <= 0;
  else
    if (uut_opkt_vld && uut_opkt_rdy)
      tb_pkt_cnt <= tb_pkt_cnt + 1;


always @ (posedge tb_clk or posedge tb_rst)
  if (tb_rst)
    tb_start_cnt <= 200;
  else
    if (tb_pkt_cnt <= 25)
    begin
      if (uut_opkt_vld && uut_opkt_rdy)
        if (tb_start_cnt <= 75)
          tb_start_cnt <= 200;
        else  
          tb_start_cnt <= tb_start_cnt - 15;
    end
    else
      tb_start_cnt <= 0;


always @ (*)
  if (uut_opkt_vld && uut_opkt_rdy && (tb_start_cnt != 0))
    tb_cnt_on = 1;
  else
    tb_cnt_on = 0;





assign tb_opkt_hdr = uut_opkt_data[`PKT_HDR_RNG];
assign tb_opkt_key = uut_opkt_data[`PKT_KEY_RNG];
assign tb_opkt_pld = uut_opkt_data[`PKT_PLD_RNG];






always @ (posedge tb_clk)
  if (uut_opkt_vld && uut_opkt_rdy)
    if ((tb_opkt_hdr !== tb_fifo_pkt[tb_fifo_rdp][`PKT_HDR_RNG])
         || (tb_opkt_key !== tb_fifo_pkt[tb_fifo_rdp][`PKT_KEY_RNG])
         || (tb_fifo_pkt[tb_fifo_rdp][1]
              && (tb_opkt_pld !== tb_fifo_pkt[tb_fifo_rdp][`PKT_PLD_RNG])
            )
       )
      tb_bad_pkt = 1;
    else
      tb_bad_pkt = 0;





always @ (posedge tb_clk or posedge tb_rst)
  if (tb_rst)
    tb_fifo_rdp <= 0;
  else
    if (uut_opkt_vld && uut_opkt_rdy)
      tb_fifo_rdp <= tb_fifo_rdp + 1;





always @ (posedge tb_clk or posedge tb_rst)
  if (tb_rst)
    tb_cycle_cnt <= 0;
  else
    if (tb_cnt_on)
      tb_cycle_cnt <= tb_start_cnt;
    else if (tb_cycle_cnt != 0)
      tb_cycle_cnt <= tb_cycle_cnt - 1;





initial
begin
  uut_rst = 1'b0;


  # INIT_DELAY;
   
  uut_rst = 1'b1;

  # RST_DELAY;

  # COMB_DELAY;
   
  uut_rst = 1'b0;
end





initial
begin
   uut_clk0 = 1'b0;

  forever
  begin
    # UUT_CLK0_HPER;
     
    uut_clk0 = ~uut_clk0;
   end
end





initial
begin
   uut_clk1 = 1'b0;

  forever
  begin
    # UUT_CLK1_HPER;
     
    uut_clk1 = ~uut_clk1;
   end
end





initial
begin
  tb_rst  = 1'b0;


  # INIT_DELAY;
   
  tb_rst  = 1'b1;

  # RST_DELAY;

  # COMB_DELAY;
   
  tb_rst  = 1'b0;
end





initial
begin
   tb_clk = 1'b0;

  forever
  begin
    # TB_CLK_HPER;
     
    tb_clk = ~tb_clk;
   end
end
endmodule
module spio_spinnaker_link_receiver_sync_fifo_tb ();




localparam UUT_CLK0_HPER = (6.666 / 2);
localparam UUT_CLK1_HPER = (13.333 / 2);
localparam TB_CLK_HPER   = (13.333 / 2);


localparam SPL_HSDLY = 23;

localparam INIT_DELAY = (10 * TB_CLK_HPER);
localparam RST_DELAY  = (51 * TB_CLK_HPER);

localparam COMB_DELAY = 2;





reg         tb_rst;
reg         tb_clk;

reg         uut_rst;
reg         uut_clk0;
reg         uut_clk1;

reg   [6:0] uut_ispl_data;
wire        uut_ispl_ack;

wire [71:0] uut_opkt_data;
wire        uut_opkt_vld;
reg         uut_opkt_rdy;

wire [71:0] uut0_uut1_opkt_data;
wire        uut0_uut1_opkt_vld;
wire        uut0_uut1_opkt_rdy;

wire [71:0] tb_ipkt;
wire  [7:0] tb_ipkt_hdr; 
reg   [1:0] tb_ipkt_type; 
wire        tb_ipkt_prty; 
reg  [31:0] tb_ipkt_key;
reg  [31:0] tb_ipkt_pld;
reg         tb_ipkt_send_pld;
wire        tb_ipkt_send_eop;

reg   [6:0] tb_old_data;
reg         tb_old_ack;

reg   [4:0] tb_flt_cnt;

wire  [7:0] tb_opkt_hdr; 
wire [31:0] tb_opkt_key;
wire [31:0] tb_opkt_pld;

reg         tb_bad_pkt;

reg  [71:0] tb_fifo_pkt [0:7];
reg   [2:0] tb_fifo_rdp;
reg   [2:0] tb_fifo_wrp;

reg [31:0] tb_pkt_cnt;
reg        tb_cnt_on;
reg [31:0] tb_cycle_cnt;
reg [31:0] tb_start_cnt;









function [6:0] encode_nrz_2of7 ;
  input [4:0] data;
  input [6:0] old_data;

  casex (data)
    5'b00000 : encode_nrz_2of7 = old_data ^ 7'b0010001;
    5'b00001 : encode_nrz_2of7 = old_data ^ 7'b0010010;
    5'b00010 : encode_nrz_2of7 = old_data ^ 7'b0010100;
    5'b00011 : encode_nrz_2of7 = old_data ^ 7'b0011000;
    5'b00100 : encode_nrz_2of7 = old_data ^ 7'b0100001;
    5'b00101 : encode_nrz_2of7 = old_data ^ 7'b0100010;
    5'b00110 : encode_nrz_2of7 = old_data ^ 7'b0100100;
    5'b00111 : encode_nrz_2of7 = old_data ^ 7'b0101000;
    5'b01000 : encode_nrz_2of7 = old_data ^ 7'b1000001;
    5'b01001 : encode_nrz_2of7 = old_data ^ 7'b1000010;
    5'b01010 : encode_nrz_2of7 = old_data ^ 7'b1000100;
    5'b01011 : encode_nrz_2of7 = old_data ^ 7'b1001000;
    5'b01100 : encode_nrz_2of7 = old_data ^ 7'b0000011;
    5'b01101 : encode_nrz_2of7 = old_data ^ 7'b0000110;
    5'b01110 : encode_nrz_2of7 = old_data ^ 7'b0001100;
    5'b01111 : encode_nrz_2of7 = old_data ^ 7'b0001001;
    5'b1xxxx : encode_nrz_2of7 = old_data ^ 7'b1100000;
    default  : encode_nrz_2of7 = 7'bxxxxxxx;
  endcase
endfunction





spio_spinnaker_link_receiver uut0
(
  .CLK_IN           (uut_clk0),
  .RESET_IN         (uut_rst),


  .SL_DATA_2OF7_IN  (uut_ispl_data),
  .SL_ACK_OUT       (uut_ispl_ack),


  .PKT_DATA_OUT     (uut0_uut1_opkt_data),
  .PKT_VLD_OUT      (uut0_uut1_opkt_vld),
  .PKT_RDY_IN       (uut0_uut1_opkt_rdy)
);


spio_hss_multiplexer_pkt_fifo_sync uut1
(
  .RESET_IN     (uut_rst),
  .WCLK_IN      (uut_clk0),
  .RCLK_IN      (uut_clk1),


  .SFI_DATA_IN  (uut0_uut1_opkt_data),
  .SFI_VLD_IN   (uut0_uut1_opkt_vld),
  .SFI_RDY_OUT  (uut0_uut1_opkt_rdy),


  .SFO_DATA_OUT (uut_opkt_data),
  .SFO_VLD_OUT  (uut_opkt_vld),
  .SFO_RDY_IN   (uut_opkt_rdy)
);






initial
begin
  wait (tb_rst);

  # COMB_DELAY;


  uut_ispl_data = 0;
  tb_old_data = 0;


  tb_ipkt_type = 0;
  tb_ipkt_key = 32'h0000_0001;
  tb_ipkt_pld = 32'ha5a5_a5a5;
  tb_ipkt_send_pld = 1'b0;


  tb_fifo_wrp = 0;

  tb_flt_cnt = 0;

  wait (!tb_rst);

  # COMB_DELAY;
   

  tb_fifo_pkt[tb_fifo_wrp] = tb_ipkt;

  # COMB_DELAY;


  tb_fifo_wrp = tb_fifo_wrp + 1;

  # COMB_DELAY;

  forever
  begin

    if (tb_ipkt_send_eop)
    begin

      uut_ispl_data = encode_nrz_2of7 (`EOP, tb_old_data);


      tb_ipkt_type = tb_ipkt_type + 1;
      tb_ipkt_key = tb_ipkt_key + 1;
      tb_ipkt_pld = tb_ipkt_pld + 1;
      if (tb_pkt_cnt > 13) tb_ipkt_send_pld = 1;

      # COMB_DELAY;


      tb_fifo_pkt[tb_fifo_wrp] = tb_ipkt;

      # COMB_DELAY;


      tb_fifo_wrp <= tb_fifo_wrp + 1;


      tb_flt_cnt = 0;
    end
    else
    begin

      uut_ispl_data = encode_nrz_2of7 (tb_ipkt[(tb_flt_cnt * 4) +: 4],
                                        tb_old_data
                                      );

      # COMB_DELAY;


      tb_flt_cnt = tb_flt_cnt + 1;
    end


    tb_old_data = uut_ispl_data;


    tb_old_ack = uut_ispl_ack;


    wait (tb_old_ack != uut_ispl_ack);

    # SPL_HSDLY;
  end
end





assign tb_ipkt = {tb_ipkt_pld, tb_ipkt_key, tb_ipkt_hdr};





assign tb_ipkt_hdr = {tb_ipkt_type, 4'b0000, tb_ipkt_send_pld, tb_ipkt_prty};





assign tb_ipkt_prty = tb_ipkt_send_pld
                        ? ^(tb_ipkt_hdr[7:1] ^ tb_ipkt_key ^ tb_ipkt_pld)
                        : ~(^(tb_ipkt_hdr[7:1] ^ tb_ipkt_key));





assign tb_ipkt_send_eop = (!tb_ipkt_hdr[1] && (tb_flt_cnt == 10))
                            || (tb_flt_cnt == 18);





always @ (posedge tb_clk or posedge tb_rst)
  if (tb_rst)
    uut_opkt_rdy <= # COMB_DELAY 1'b0;
  else
    if (uut_opkt_vld && uut_opkt_rdy && (tb_start_cnt != 0))
      uut_opkt_rdy <= # COMB_DELAY 1'b0;
    else if (tb_cycle_cnt == 0)
      uut_opkt_rdy <= # COMB_DELAY 1'b1;


always @ (posedge tb_clk or posedge tb_rst)
  if (tb_rst)
    tb_pkt_cnt <= 0;
  else
    if (uut_opkt_vld && uut_opkt_rdy)
      tb_pkt_cnt <= tb_pkt_cnt + 1;


always @ (posedge tb_clk or posedge tb_rst)
  if (tb_rst)
    tb_start_cnt <= 200;
  else
    if (tb_pkt_cnt <= 25)
    begin
      if (uut_opkt_vld && uut_opkt_rdy)
        if (tb_start_cnt <= 75)
          tb_start_cnt <= 200;
        else  
          tb_start_cnt <= tb_start_cnt - 15;
    end
    else
      tb_start_cnt <= 0;


always @ (*)
  if (uut_opkt_vld && uut_opkt_rdy && (tb_start_cnt != 0))
    tb_cnt_on = 1;
  else
    tb_cnt_on = 0;





assign tb_opkt_hdr = uut_opkt_data[`PKT_HDR_RNG];
assign tb_opkt_key = uut_opkt_data[`PKT_KEY_RNG];
assign tb_opkt_pld = uut_opkt_data[`PKT_PLD_RNG];






always @ (posedge tb_clk)
  if (uut_opkt_vld && uut_opkt_rdy)
    if ((tb_opkt_hdr !== tb_fifo_pkt[tb_fifo_rdp][`PKT_HDR_RNG])
         || (tb_opkt_key !== tb_fifo_pkt[tb_fifo_rdp][`PKT_KEY_RNG])
         || (tb_fifo_pkt[tb_fifo_rdp][1]
              && (tb_opkt_pld !== tb_fifo_pkt[tb_fifo_rdp][`PKT_PLD_RNG])
            )
       )
      tb_bad_pkt = 1;
    else
      tb_bad_pkt = 0;





always @ (posedge tb_clk or posedge tb_rst)
  if (tb_rst)
    tb_fifo_rdp <= 0;
  else
    if (uut_opkt_vld && uut_opkt_rdy)
      tb_fifo_rdp <= tb_fifo_rdp + 1;





always @ (posedge tb_clk or posedge tb_rst)
  if (tb_rst)
    tb_cycle_cnt <= 0;
  else
    if (tb_cnt_on)
      tb_cycle_cnt <= tb_start_cnt;
    else if (tb_cycle_cnt != 0)
      tb_cycle_cnt <= tb_cycle_cnt - 1;





initial
begin
  uut_rst = 1'b0;


  # INIT_DELAY;
   
  uut_rst = 1'b1;

  # RST_DELAY;

  # COMB_DELAY;
   
  uut_rst = 1'b0;
end





initial
begin
   uut_clk0 = 1'b0;

  forever
  begin
    # UUT_CLK0_HPER;
     
    uut_clk0 = ~uut_clk0;
   end
end





initial
begin
   uut_clk1 = 1'b0;

  forever
  begin
    # UUT_CLK1_HPER;
     
    uut_clk1 = ~uut_clk1;
   end
end





initial
begin
  tb_rst  = 1'b0;


  # INIT_DELAY;
   
  tb_rst  = 1'b1;

  # RST_DELAY;

  # COMB_DELAY;
   
  tb_rst  = 1'b0;
end





initial
begin
   tb_clk = 1'b0;

  forever
  begin
    # TB_CLK_HPER;
     
    tb_clk = ~tb_clk;
   end
end
endmodule