data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v
1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:2: Cannot find include file: def.v\n`include "def.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n             def.v\n             def.v.v\n             def.v.sv\n             obj_dir/def.v\n             obj_dir/def.v.v\n             obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n  if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n             ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n  if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n                   ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n  if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n  if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n                                                  ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:37: Define or directive not defined: \'`OP_IMM\'\n   opCode_o <= {25\'b0,`OP_IMM};\n                      ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:37: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n   opCode_o <= {25\'b0,`OP_IMM};\n                             ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:38: Define or directive not defined: \'`True\'\n  end else if(stall[1] != `True) begin\n                          ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n  if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n             ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n  if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n                   ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n  if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n  if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n                                                  ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:81: Define or directive not defined: \'`False\'\n                                                                                      : ... Suggested alternative: \'`else\'\n   wrIs_o   <= `False;\n               ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   wrIs_o   <= `False;\n                     ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:83: Define or directive not defined: \'`OP_IMM\'\n   opCode_o <= `OP_IMM;\n               ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   opCode_o <= `OP_IMM;\n                      ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:84: Define or directive not defined: \'`ADDI\'\n   opType_o <= `ADDI;\n               ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   opType_o <= `ADDI;\n                    ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:88: syntax error, unexpected else\n  end else if(!stall[2]) begin\n      ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:90: Define or directive not defined: \'`True\'\n   wrIs_o   <= `True;\n               ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n  if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n             ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n  if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n                   ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n  if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n  if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n                                                  ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:139: Define or directive not defined: \'`False\'\n                                                                                       : ... Suggested alternative: \'`else\'\n   wrIs_o   <= `False;\n               ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:139: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   wrIs_o   <= `False;\n                     ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:142: Define or directive not defined: \'`OP_IMM\'\n   opCode_o <= `OP_IMM;\n               ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:142: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   opCode_o <= `OP_IMM;\n                      ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:143: Define or directive not defined: \'`ADDI\'\n   opType_o <= `ADDI;\n               ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:143: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   opType_o <= `ADDI;\n                    ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:147: syntax error, unexpected else\n  end else if(!stall[3]) begin\n      ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: Define or directive not defined: \'`STORE\'\n   if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n                ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n   if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n                       ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: Define or directive not defined: \'`DEBUG\'\n   if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n                                                                 ^~~~~~\n%Error: Cannot continue\n'
module CPU_MEMTrans (
	clk, rst, stall,

	i_id, i_id_o,

	opCode, opType,
	wrIs, wr, wrData,
	rd0, rd1, imm,

	opCode_o, opType_o,
	wrIs_o, wr_o, wrData_o,
	rd0_o, rd1_o, imm_o
	);
	input wire 		    clk, rst;
	input wire [3  : 0] stall;

	input wire [ 31:0] i_id;
	output reg [ 31:0] i_id_o;

	input wire        wrIs;
	input wire [ 4:0] wr;
	input wire [31:0] wrData;
	input wire [ 6:0] opCode;
	output reg [ 6:0] opCode_o;
	input wire [ 2:0] opType;
	output reg [ 2:0] opType_o;
	input wire [31:0] rd0, rd1, imm;


	output reg 		  wrIs_o;
	output reg [ 4:0] wr_o;
	output reg [31:0] wrData_o;
	output reg [31:0] rd0_o, rd1_o, imm_o;

	always @ ( posedge clk ) begin
		if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin
			i_id_o   <= 5'b0;
			wrIs_o   <= `False;
			wr_o     <= 4'b0;
			wrData_o <= 32'b0;
			opCode_o <= `OP_IMM;
			opType_o <= `ADDI;
			rd0_o    <= 32'd0;
			rd1_o    <= 32'd0;
			imm_o    <= 32'd0;
		end else if(!stall[3]) begin
			i_id_o   <= i_id;
			wrIs_o   <= wrIs;
			wr_o     <= wr;
			wrData_o <= wrData;
			opCode_o <= opCode;
			opType_o <= opType;
			rd0_o    <= rd0;
			rd1_o    <= rd1;
			imm_o    <= imm;
			if(opCode == `STORE && opType == 3'b000 && wrData == 'h104 && `DEBUG == 1'b0)
				$write("%c",rd1);

		end
	end


endmodule
module CPU_MEMTrans (
	clk, rst, stall,

	i_id, i_id_o,

	opCode, opType,
	wrIs, wr, wrData,
	rd0, rd1, imm,

	opCode_o, opType_o,
	wrIs_o, wr_o, wrData_o,
	rd0_o, rd1_o, imm_o
	);

	input wire 		    clk, rst;
	input wire [3  : 0] stall;

	input wire [ 31:0] i_id;
	output reg [ 31:0] i_id_o;

	input wire        wrIs;
	input wire [ 4:0] wr;
	input wire [31:0] wrData;
	input wire [ 6:0] opCode;
	output reg [ 6:0] opCode_o;
	input wire [ 2:0] opType;
	output reg [ 2:0] opType_o;
	input wire [31:0] rd0, rd1, imm;


	output reg 		  wrIs_o;
	output reg [ 4:0] wr_o;
	output reg [31:0] wrData_o;
	output reg [31:0] rd0_o, rd1_o, imm_o;

	always @ ( posedge clk ) begin
		if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin
			i_id_o   <= 5'b0;
			wrIs_o   <= `False;
			wr_o     <= 4'b0;
			wrData_o <= 32'b0;
			opCode_o <= `OP_IMM;
			opType_o <= `ADDI;
			rd0_o    <= 32'd0;
			rd1_o    <= 32'd0;
			imm_o    <= 32'd0;
		end else if(!stall[3]) begin
			i_id_o   <= i_id;
			wrIs_o   <= wrIs;
			wr_o     <= wr;
			wrData_o <= wrData;
			opCode_o <= opCode;
			opType_o <= opType;
			rd0_o    <= rd0;
			rd1_o    <= rd1;
			imm_o    <= imm;
			if(opCode == `STORE && opType == 3'b000 && wrData == 'h104 && `DEBUG == 1'b0)
				$write("%c",rd1);

		end
	end


endmodule