data/full_repos/permissive/16751310/exampleproj/reconfig_hdl/reg_reconfig.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/16751310/exampleproj/reconfig_hdl/reg_reconfig.v:138: Signal definition not found, creating implicitly: \'fifo_empty\'\n                                                                                                  : ... Suggested alternative: \'fifo_rst\'\n  end else if ((icap_statusreg[4:0] == 5\'h1A) & (fifo_empty)) begin\n                                                 ^~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/16751310/exampleproj/reconfig_hdl/reg_reconfig.v:189: Cannot find file containing module: \'ICAP_SPARTAN6\'\n ICAP_SPARTAN6 #(\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/16751310/exampleproj/reconfig_hdl,data/full_repos/permissive/16751310/ICAP_SPARTAN6\n             data/full_repos/permissive/16751310/exampleproj/reconfig_hdl,data/full_repos/permissive/16751310/ICAP_SPARTAN6.v\n             data/full_repos/permissive/16751310/exampleproj/reconfig_hdl,data/full_repos/permissive/16751310/ICAP_SPARTAN6.sv\n             ICAP_SPARTAN6\n             ICAP_SPARTAN6.v\n             ICAP_SPARTAN6.sv\n             obj_dir/ICAP_SPARTAN6\n             obj_dir/ICAP_SPARTAN6.v\n             obj_dir/ICAP_SPARTAN6.sv\n%Error: data/full_repos/permissive/16751310/exampleproj/reconfig_hdl/reg_reconfig.v:207: Cannot find file containing module: \'icap_fifo\'\n icap_fifo icap_fifo (\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module reg_reconfig(
	input 			reset_i,
	input 			clk,
	input [5:0]    reg_address,
	input [15:0]   reg_bytecnt,
	input [7:0]    reg_datai,
	output [7:0]   reg_datao,
	input [15:0]   reg_size,
	input          reg_read,
	input  			reg_write,
	input          reg_addrvalid,
	output			reg_stream,	
	
	input [5:0]    reg_hypaddress,
	output [15:0]  reg_hyplen
    );

	wire icap_clk;
	wire icap_ce;
	wire icap_wr;
	wire [15:0] icap_in;
	
	reg fifo_wr_en;
	reg fifo_rd_en;
	wire [17:0] fifo_din;
	wire [17:0] fifo_dout;
	


	assign icap_in[15] = fifo_dout[8];
	assign icap_in[14] = fifo_dout[9];
	assign icap_in[13] = fifo_dout[10];
	assign icap_in[12] = fifo_dout[11];
	assign icap_in[11] = fifo_dout[12];
	assign icap_in[10] = fifo_dout[13];
	assign icap_in[9] = fifo_dout[14];
	assign icap_in[8] = fifo_dout[15];
	assign icap_in[7] = fifo_dout[0];
	assign icap_in[6] = fifo_dout[1];
	assign icap_in[5] = fifo_dout[2];
	assign icap_in[4] = fifo_dout[3];
	assign icap_in[3] = fifo_dout[4];
	assign icap_in[2] = fifo_dout[5];
	assign icap_in[1] = fifo_dout[6];
	assign icap_in[0] = fifo_dout[7];
	
	`define START_PATTERN 5'h1A
	`define RECONFIG_ADDR 52
	
	reg [7:0]  icap_statusreg;
	

	reg [15:0] reg_hyplen_reg;
	assign reg_hyplen = reg_hyplen_reg;
	
	always @(reg_hypaddress) begin
		case (reg_hypaddress)
            `RECONFIG_ADDR: reg_hyplen_reg <= 1;
				default: reg_hyplen_reg<= 0;
		endcase
	 end    	
	
	 wire fifo_rst;
	 reg [7:0] reg_datao_reg;
	 assign reg_datao = reg_datao_reg;
	
	assign fifo_rst = icap_statusreg[5];
	
	 always @(posedge clk) begin
		if (reg_read) begin
			case (reg_address)		
				`RECONFIG_ADDR: begin reg_datao_reg <= icap_statusreg; end
				default: begin reg_datao_reg <= 0; end
			endcase
		end
	 end	

	 reg [15:0] data_in;
	 reg dowr;
	 
	 always @(posedge clk)
		fifo_wr_en <= dowr; 

	 always @(posedge clk) begin
		if (reset_i) begin
			icap_statusreg <= 0;
		end else if ((icap_statusreg[4:0] == `START_PATTERN) & (fifo_empty)) begin
			icap_statusreg <= 0;
		end else if (reg_write) begin
			if (reg_bytecnt == 0) begin
				case (reg_address)
					`RECONFIG_ADDR: icap_statusreg <= reg_datai;	
					default: ;
				endcase
			end else begin
				if (reg_bytecnt[0] == 1'b1) begin
					data_in[15:8] <= reg_datai;
				end else begin
					data_in[7:0] <= reg_datai;				
				end
			end
		end
	 end	

	 always @(posedge clk) begin
		if (reset_i)
			dowr <= 0;
		else if ((reg_write) & (reg_bytecnt != 0) & (reg_bytecnt[0] == 1'b0) & (reg_address == `RECONFIG_ADDR))
			dowr <= 1;
		else
			dowr <= 0;
	 end	

	assign fifo_din[15:0] = data_in;
	assign fifo_din[17:16] = 2'b00;

	reg do_config;
	always @(posedge clk) begin
		 do_config <= (icap_statusreg[4:0] == `START_PATTERN) ? 1'b1 : 1'b0;
	end
	

	reg icap_cfg;
	reg icap_cfg2;
	always @(posedge icap_clk) begin
		icap_cfg2 <= do_config;
		icap_cfg <= icap_cfg2;
	end
	
	reg [2:0] cnt;	
	always @(posedge clk)
		cnt <= cnt + 3'b1;
		
	assign icap_clk = cnt[2];



	ICAP_SPARTAN6 #(
	.DEVICE_ID('h04004093),
	.SIM_CFG_FILE_NAME("NONE")

	)
	
	ICAP_SPARTAN6_inst (
		.BUSY(),
		.O(),
		.CE(~icap_cfg),
		.CLK(icap_clk),
		.I(icap_in),
		.WRITE(1'b0)
	);

	


	icap_fifo icap_fifo (
		.rst(reset_i | fifo_rst),
		.wr_clk(clk),
		.rd_clk(icap_clk),
		.din(fifo_din),
		.wr_en(fifo_wr_en),
		.rd_en(icap_cfg & ~fifo_empty),
		.dout(fifo_dout),
		.full(fifo_full),
		.empty(fifo_empty),
		.almost_empty()
		);

`ifdef CHIPSCOPE
   wire [127:0] cs_data;   
   wire [35:0]  chipscope_control;
  coregen_icon icon (
    .CONTROL0(chipscope_control)
   ); 

   coregen_ila ila (
    .CONTROL(chipscope_control),
    .CLK(icap_clk),
    .TRIG0(cs_data)
   );  
	
	assign cs_data[15:0] = icap_in;
	assign cs_data[16] = fifo_wr_en;
	assign cs_data[17] = icap_cfg;
	assign cs_data[18] = fifo_empty;	
	
`endif

endmodule
module reg_reconfig(
	input 			reset_i,
	input 			clk,
	input [5:0]    reg_address,
	input [15:0]   reg_bytecnt,
	input [7:0]    reg_datai,
	output [7:0]   reg_datao,
	input [15:0]   reg_size,
	input          reg_read,
	input  			reg_write,
	input          reg_addrvalid,
	output			reg_stream,	
	
	input [5:0]    reg_hypaddress,
	output [15:0]  reg_hyplen
    );


	wire icap_clk;
	wire icap_ce;
	wire icap_wr;
	wire [15:0] icap_in;
	
	reg fifo_wr_en;
	reg fifo_rd_en;
	wire [17:0] fifo_din;
	wire [17:0] fifo_dout;
	


	assign icap_in[15] = fifo_dout[8];
	assign icap_in[14] = fifo_dout[9];
	assign icap_in[13] = fifo_dout[10];
	assign icap_in[12] = fifo_dout[11];
	assign icap_in[11] = fifo_dout[12];
	assign icap_in[10] = fifo_dout[13];
	assign icap_in[9] = fifo_dout[14];
	assign icap_in[8] = fifo_dout[15];
	assign icap_in[7] = fifo_dout[0];
	assign icap_in[6] = fifo_dout[1];
	assign icap_in[5] = fifo_dout[2];
	assign icap_in[4] = fifo_dout[3];
	assign icap_in[3] = fifo_dout[4];
	assign icap_in[2] = fifo_dout[5];
	assign icap_in[1] = fifo_dout[6];
	assign icap_in[0] = fifo_dout[7];
	
	`define START_PATTERN 5'h1A
	`define RECONFIG_ADDR 52
	
	reg [7:0]  icap_statusreg;
	

	reg [15:0] reg_hyplen_reg;
	assign reg_hyplen = reg_hyplen_reg;
	
	always @(reg_hypaddress) begin
		case (reg_hypaddress)
            `RECONFIG_ADDR: reg_hyplen_reg <= 1;
				default: reg_hyplen_reg<= 0;
		endcase
	 end    	
	
	 wire fifo_rst;
	 reg [7:0] reg_datao_reg;
	 assign reg_datao = reg_datao_reg;
	
	assign fifo_rst = icap_statusreg[5];
	
	 always @(posedge clk) begin
		if (reg_read) begin
			case (reg_address)		
				`RECONFIG_ADDR: begin reg_datao_reg <= icap_statusreg; end
				default: begin reg_datao_reg <= 0; end
			endcase
		end
	 end	

	 reg [15:0] data_in;
	 reg dowr;
	 
	 always @(posedge clk)
		fifo_wr_en <= dowr; 

	 always @(posedge clk) begin
		if (reset_i) begin
			icap_statusreg <= 0;
		end else if ((icap_statusreg[4:0] == `START_PATTERN) & (fifo_empty)) begin
			icap_statusreg <= 0;
		end else if (reg_write) begin
			if (reg_bytecnt == 0) begin
				case (reg_address)
					`RECONFIG_ADDR: icap_statusreg <= reg_datai;	
					default: ;
				endcase
			end else begin
				if (reg_bytecnt[0] == 1'b1) begin
					data_in[15:8] <= reg_datai;
				end else begin
					data_in[7:0] <= reg_datai;				
				end
			end
		end
	 end	

	 always @(posedge clk) begin
		if (reset_i)
			dowr <= 0;
		else if ((reg_write) & (reg_bytecnt != 0) & (reg_bytecnt[0] == 1'b0) & (reg_address == `RECONFIG_ADDR))
			dowr <= 1;
		else
			dowr <= 0;
	 end	

	assign fifo_din[15:0] = data_in;
	assign fifo_din[17:16] = 2'b00;

	reg do_config;
	always @(posedge clk) begin
		 do_config <= (icap_statusreg[4:0] == `START_PATTERN) ? 1'b1 : 1'b0;
	end
	

	reg icap_cfg;
	reg icap_cfg2;
	always @(posedge icap_clk) begin
		icap_cfg2 <= do_config;
		icap_cfg <= icap_cfg2;
	end
	
	reg [2:0] cnt;	
	always @(posedge clk)
		cnt <= cnt + 3'b1;
		
	assign icap_clk = cnt[2];



	ICAP_SPARTAN6 #(
	.DEVICE_ID('h04004093),
	.SIM_CFG_FILE_NAME("NONE")

	)
	
	ICAP_SPARTAN6_inst (
		.BUSY(),
		.O(),
		.CE(~icap_cfg),
		.CLK(icap_clk),
		.I(icap_in),
		.WRITE(1'b0)
	);

	


	icap_fifo icap_fifo (
		.rst(reset_i | fifo_rst),
		.wr_clk(clk),
		.rd_clk(icap_clk),
		.din(fifo_din),
		.wr_en(fifo_wr_en),
		.rd_en(icap_cfg & ~fifo_empty),
		.dout(fifo_dout),
		.full(fifo_full),
		.empty(fifo_empty),
		.almost_empty()
		);

`ifdef CHIPSCOPE
   wire [127:0] cs_data;   
   wire [35:0]  chipscope_control;
  coregen_icon icon (
    .CONTROL0(chipscope_control)
   ); 

   coregen_ila ila (
    .CONTROL(chipscope_control),
    .CLK(icap_clk),
    .TRIG0(cs_data)
   );  
	
	assign cs_data[15:0] = icap_in;
	assign cs_data[16] = fifo_wr_en;
	assign cs_data[17] = icap_cfg;
	assign cs_data[18] = fifo_empty;	
	
`endif

endmodule