data/full_repos/permissive/154352170/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/154352170/test.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/154352170/test.v:49: Unsupported: Ignoring delay on this delayed statement.\n always #0.5 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/154352170/test.v:32: Cannot find file containing module: \'mips\'\n mips uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/154352170,data/full_repos/permissive/154352170/mips\n             data/full_repos/permissive/154352170,data/full_repos/permissive/154352170/mips.v\n             data/full_repos/permissive/154352170,data/full_repos/permissive/154352170/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;


	reg clk;
	reg reset;


	mips uut (
		.clk(clk), 
		.reset(reset)
	);

	initial begin

		clk = 0;
		reset = 0;


		#0;
        


	end
	
	always #0.5 clk = ~clk;
      
endmodule
module test;



	reg clk;
	reg reset;


	mips uut (
		.clk(clk), 
		.reset(reset)
	);

	initial begin

		clk = 0;
		reset = 0;


		#0;
        


	end
	
	always #0.5 clk = ~clk;
      
endmodule