data/full_repos/permissive/117439233/hdl/src/MUX2x1.v
data/verilator_xmls/bd7227ec-14ea-4604-93c6-8e20fb92ae52.xml
module MUX2x1(
	input A,
	input B,
	input sel,
	output res
	);
	assign res = B&sel | A&(~sel);
endmodule
module MUX2x1(
	input A,
	input B,
	input sel,
	output res
	);

	assign res = B&sel | A&(~sel);
endmodule