data/full_repos/permissive/218779832/pipeControl_old.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/218779832/pipeControl_old.v:42: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'CCG1\'\nmodule CCG1\n       ^~~~\n                                                                            : ... Top module \'CCG2\'\nmodule CCG2\n       ^~~~\n                                                                            : ... Top module \'CCG3\'\nmodule CCG3\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/218779832/pipeControl_old.v:67: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance CCG2\nwrite <= opcode_in_1[2:0];\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/pipeControl_old.v:71: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'flagCheck_1\' generates 1 bits.\n                                                                         : ... In instance CCG2\nflag1 <= flagCheck_1; \n      ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/pipeControl_old.v:75: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'flag1\' generates 8 bits.\n                                                                         : ... In instance CCG2\nassign flagCheck = flag1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/218779832/pipeControl_old.v:76: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'write\' generates 8 bits.\n                                                                         : ... In instance CCG2\nassign write_address = write;\n                     ^\n%Error: Exiting due to 5 warning(s)\n'
module CCG1
(
    input             clk,
    input   [15 : 0]  segment,
    input   [7:0]     PC_in,
    output  [7:0]     opcode_in_1,
    output  [7:0]     OR1,
    output  [7:0]     NPC_in_1
);



reg [7:0] NPC;
reg [7:0] OR;
reg [7:0] opcode;

always @  (posedge clk)
begin
NPC <= PC_in;
OR <= segment[7:0];
opcode <= segment[15:8];
end

assign opcode_in_1 = opcode;
assign OR1 = OR; 
assign NPC_in_1 = NPC;

endmodule
module CCG1
(
    input             clk,
    input   [15 : 0]  segment,
    input   [7:0]     PC_in,
    output  [7:0]     opcode_in_1,
    output  [7:0]     OR1,
    output  [7:0]     NPC_in_1
);




reg [7:0] NPC;
reg [7:0] OR;
reg [7:0] opcode;

always @  (posedge clk)
begin
NPC <= PC_in;
OR <= segment[7:0];
opcode <= segment[15:8];
end

assign opcode_in_1 = opcode;
assign OR1 = OR; 
assign NPC_in_1 = NPC;

endmodule