data/full_repos/permissive/183345139/hba_motor/pwm_dir.v
1: b'%Warning-WIDTH: data/full_repos/permissive/183345139/hba_motor/pwm_dir.v:88: Operator EQ expects 7 bits on the LHS, but LHS\'s VARREF \'duty_cycle_reg\' generates 1 bits.\n                                                                           : ... In instance pmw_dir\nwire duty_cycle_change = (duty_cycle_reg == ~duty_cycle) ? 1 : 0;\n                                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/183345139/hba_motor/pwm_dir.v:103: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'duty_cycle\' generates 7 bits.\n                                                                            : ... In instance pmw_dir\n        duty_cycle_reg <= duty_cycle;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/183345139/hba_motor/pwm_dir.v:135: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'pulse_100k_count\' generates 10 bits.\n                                                                            : ... In instance pmw_dir\n            if (pulse_100k_count == (PERIOD_COUNT-1)) begin\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/183345139/hba_motor/pwm_dir.v:184: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'pwm_count\' generates 8 bits.\n                                                                            : ... In instance pmw_dir\n                end else if (pwm_count == (DUTY_1_PERCENT-1)) begin\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/183345139/hba_motor/pwm_dir.v:182: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'duty_cycle\' generates 7 bits.\n                                                                            : ... In instance pmw_dir\n                if (duty_amount == duty_cycle) begin\n                                ^~\n%Error: Exiting due to 5 warning(s)\n'
module pmw_dir # 
(
    parameter integer CLK_FREQUENCY = 60_000_000,
    parameter integer PWM_FREQUENCY = 100_000,
    parameter integer PERIOD_COUNT = (CLK_FREQUENCY / PWM_FREQUENCY),
    parameter integer DUTY_1_PERCENT = (PERIOD_COUNT / 100)
)
(
    input wire clk,
    input wire reset,
    input wire en,
    input wire float,
    input wire [6:0] duty_cycle,
    input wire dir_in,
    input wire estop,

    output reg pwm,
    output reg dir_out,
    output wire float_n
);



assign float_n = ~float;








reg pwm_en;
reg en_reg;
reg float_reg;
reg duty_cycle_reg;
reg dir_in_reg;

wire en_change = (en_reg == ~en) ? 1 : 0;
wire float_change = (float_reg == ~float) ? 1 : 0;
wire duty_cycle_change = (duty_cycle_reg == ~duty_cycle) ? 1 : 0;
wire dir_in_change = (dir_in_reg == ~dir_in) ? 1 : 0;

always @ (posedge clk)
begin
    if (reset) begin
        pwm_en <= 0;
        en_reg <= 0;
        float_reg <= 0;
        duty_cycle_reg <= 0;
        dir_in_reg <= 0;
    end else begin

        en_reg <= en;
        float_reg <= float;
        duty_cycle_reg <= duty_cycle;
        dir_in_reg <= dir_in;
        
        if (estop) begin
            pwm_en <=0;
        end else begin
            if (pwm_en || en_change || float_change || duty_cycle_change || dir_in_change) begin
                pwm_en <= en;
            end
        end
    end
end






reg [9:0] pulse_100k_count;


reg pulse_100k;

always @ (posedge clk)
begin
    if (reset) begin
        pulse_100k_count <= 0;
        pulse_100k <= 0;
    end else begin
        pulse_100k <= 0;
        if (pwm_en) begin
            pulse_100k_count <= pulse_100k_count + 1;
            if (pulse_100k_count == (PERIOD_COUNT-1)) begin
                pulse_100k_count <= 0;
                pulse_100k <= 1;
            end
        end
    end
end



localparam FORWARD = 0;
localparam REVERSE = 1;



reg [7:0] pwm_count;



reg [7:0] duty_amount;

always @ (posedge clk)
begin
    if (reset) begin
        pwm <= 0;
        dir_out <= FORWARD;
        pwm_count <= 0;
        duty_amount <= 0;
    end else begin
        if (pwm_en) begin

            dir_out <= dir_in;


            if (pulse_100k) begin
                pwm_count <= 0;
                duty_amount <= 0;
                if (duty_cycle == 0) begin
                    pwm <= 0;
                end else begin
                    pwm <= 1;
                end
            end


            if (pwm && (duty_cycle<100)) begin
                pwm_count <= pwm_count + 1;
                if (duty_amount == duty_cycle) begin
                    pwm <= 0;
                end else if (pwm_count == (DUTY_1_PERCENT-1)) begin
                    pwm_count <= 0;
                    duty_amount <= duty_amount + 1;
                end
            end

        end else begin

            pwm <= 0;
            dir_out <= FORWARD;
            pwm_count <= 0;
            duty_amount <= 0;
        end
    end
end

endmodule
module pmw_dir # 
(
    parameter integer CLK_FREQUENCY = 60_000_000,
    parameter integer PWM_FREQUENCY = 100_000,
    parameter integer PERIOD_COUNT = (CLK_FREQUENCY / PWM_FREQUENCY),
    parameter integer DUTY_1_PERCENT = (PERIOD_COUNT / 100)
)
(
    input wire clk,
    input wire reset,
    input wire en,
    input wire float,
    input wire [6:0] duty_cycle,
    input wire dir_in,
    input wire estop,

    output reg pwm,
    output reg dir_out,
    output wire float_n
);




assign float_n = ~float;








reg pwm_en;
reg en_reg;
reg float_reg;
reg duty_cycle_reg;
reg dir_in_reg;

wire en_change = (en_reg == ~en) ? 1 : 0;
wire float_change = (float_reg == ~float) ? 1 : 0;
wire duty_cycle_change = (duty_cycle_reg == ~duty_cycle) ? 1 : 0;
wire dir_in_change = (dir_in_reg == ~dir_in) ? 1 : 0;

always @ (posedge clk)
begin
    if (reset) begin
        pwm_en <= 0;
        en_reg <= 0;
        float_reg <= 0;
        duty_cycle_reg <= 0;
        dir_in_reg <= 0;
    end else begin

        en_reg <= en;
        float_reg <= float;
        duty_cycle_reg <= duty_cycle;
        dir_in_reg <= dir_in;
        
        if (estop) begin
            pwm_en <=0;
        end else begin
            if (pwm_en || en_change || float_change || duty_cycle_change || dir_in_change) begin
                pwm_en <= en;
            end
        end
    end
end






reg [9:0] pulse_100k_count;


reg pulse_100k;

always @ (posedge clk)
begin
    if (reset) begin
        pulse_100k_count <= 0;
        pulse_100k <= 0;
    end else begin
        pulse_100k <= 0;
        if (pwm_en) begin
            pulse_100k_count <= pulse_100k_count + 1;
            if (pulse_100k_count == (PERIOD_COUNT-1)) begin
                pulse_100k_count <= 0;
                pulse_100k <= 1;
            end
        end
    end
end



localparam FORWARD = 0;
localparam REVERSE = 1;



reg [7:0] pwm_count;



reg [7:0] duty_amount;

always @ (posedge clk)
begin
    if (reset) begin
        pwm <= 0;
        dir_out <= FORWARD;
        pwm_count <= 0;
        duty_amount <= 0;
    end else begin
        if (pwm_en) begin

            dir_out <= dir_in;


            if (pulse_100k) begin
                pwm_count <= 0;
                duty_amount <= 0;
                if (duty_cycle == 0) begin
                    pwm <= 0;
                end else begin
                    pwm <= 1;
                end
            end


            if (pwm && (duty_cycle<100)) begin
                pwm_count <= pwm_count + 1;
                if (duty_amount == duty_cycle) begin
                    pwm <= 0;
                end else if (pwm_count == (DUTY_1_PERCENT-1)) begin
                    pwm_count <= 0;
                    duty_amount <= duty_amount + 1;
                end
            end

        end else begin

            pwm <= 0;
            dir_out <= FORWARD;
            pwm_count <= 0;
            duty_amount <= 0;
        end
    end
end

endmodule