data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v
None: at end of input
1: b'%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:23: Cannot find include file: top_defines.vh\n`include "top_defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159016511/src/rtl/tcm,data/full_repos/permissive/159016511/top_defines.vh\n             data/full_repos/permissive/159016511/src/rtl/tcm,data/full_repos/permissive/159016511/top_defines.vh.v\n             data/full_repos/permissive/159016511/src/rtl/tcm,data/full_repos/permissive/159016511/top_defines.vh.sv\n             top_defines.vh\n             top_defines.vh.v\n             top_defines.vh.sv\n             obj_dir/top_defines.vh\n             obj_dir/top_defines.vh.v\n             obj_dir/top_defines.vh.sv\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:24: Cannot find include file: core_defines.vh\n`include "core_defines.vh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:33: Define or directive not defined: \'`ADDR_WIDTH\'\n input [`ADDR_WIDTH - 1 : 0] instr_itcm_addr,   \n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:35: Define or directive not defined: \'`DATA_WIDTH\'\n output reg [`DATA_WIDTH - 1 : 0] instr_itcm_read_data,  \n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:42: Define or directive not defined: \'`ADDR_WIDTH\'\n input [`ADDR_WIDTH - 1 : 0] data_itcm_addr,   \n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:44: Define or directive not defined: \'`DATA_WIDTH\'\n input wire [`DATA_WIDTH - 1 : 0] data_itcm_write_data,  \n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:45: Define or directive not defined: \'`DATA_WIDTH\'\n output reg [`DATA_WIDTH - 1 : 0] data_itcm_read_data,  \n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:50: Define or directive not defined: \'`DATA_WIDTH\'\n input wire [`DATA_WIDTH - 1 : 0] IAHB_read_data,  \n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:53: Define or directive not defined: \'`ADDR_WIDTH\'\n output reg[`ADDR_WIDTH - 1 : 0 ] itcm_auto_load_addr  \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:62: Define or directive not defined: \'`ADDR_WIDTH\'\nwire [`ADDR_WIDTH - 1 : 0] itcm_size = `ITCM_SIZE;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:62: Define or directive not defined: \'`ITCM_SIZE\'\nwire [`ADDR_WIDTH - 1 : 0] itcm_size = `ITCM_SIZE;\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nwire [`ADDR_WIDTH - 1 : 0] itcm_size = `ITCM_SIZE;\n                                                 ^\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:75: Define or directive not defined: \'`ITCM_START_ADDR\'\n   if(itcm_auto_load_addr == `ITCM_START_ADDR + `ITCM_SIZE - 4)\n                             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:75: Define or directive not defined: \'`ITCM_SIZE\'\n   if(itcm_auto_load_addr == `ITCM_START_ADDR + `ITCM_SIZE - 4)\n                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:135: Define or directive not defined: \'`ITCM_START_ADDR\'\n  itcm_auto_load_addr <= `ITCM_START_ADDR;\n                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:135: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  itcm_auto_load_addr <= `ITCM_START_ADDR;\n                                         ^\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:139: Define or directive not defined: \'`ITCM_START_ADDR\'\n  if(itcm_auto_load_addr ==`ITCM_START_ADDR + `ITCM_SIZE - 4)\n                           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:139: Define or directive not defined: \'`ITCM_SIZE\'\n  if(itcm_auto_load_addr ==`ITCM_START_ADDR + `ITCM_SIZE - 4)\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:141: Define or directive not defined: \'`ITCM_START_ADDR\'\n   itcm_auto_load_addr <=`ITCM_START_ADDR + `ITCM_SIZE - 4; \n                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:141: Define or directive not defined: \'`ITCM_SIZE\'\n   itcm_auto_load_addr <=`ITCM_START_ADDR + `ITCM_SIZE - 4; \n                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:158: Define or directive not defined: \'`ADDR_WIDTH\'\nwire[`ADDR_WIDTH - 1 : 0 ] itcm_write_addr;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:159: Define or directive not defined: \'`ADDR_WIDTH\'\nwire[`ADDR_WIDTH - 1 : 0 ] itcm_write_addr_from_0;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:161: Define or directive not defined: \'`DATA_WIDTH\'\nwire [`DATA_WIDTH - 1 : 0] itcm_write_data;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:166: Define or directive not defined: \'`ADDR_WIDTH\'\nreg[`ADDR_WIDTH - 1 : 0 ] itcm_auto_write_addr;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:172: Define or directive not defined: \'`ITCM_START_ADDR\'\n  itcm_auto_write_addr <= `ITCM_START_ADDR;\n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:172: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  itcm_auto_write_addr <= `ITCM_START_ADDR;\n                                          ^\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:178: Define or directive not defined: \'`ITCM_START_ADDR\'\n   itcm_auto_write_addr <= `ITCM_START_ADDR;\n                           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:178: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   itcm_auto_write_addr <= `ITCM_START_ADDR;\n                                           ^\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:200: Define or directive not defined: \'`ITCM_START_ADDR\'\nassign itcm_write_addr_from_0 = itcm_write_addr - `ITCM_START_ADDR;\n                                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:200: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign itcm_write_addr_from_0 = itcm_write_addr - `ITCM_START_ADDR;\n                                                                  ^\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:206: Define or directive not defined: \'`ADDR_WIDTH\'\nwire [`ADDR_WIDTH - 1 : 0 ] instr_itcm_addr_rd_from_0 = instr_itcm_addr - `ITCM_START_ADDR;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:206: Define or directive not defined: \'`ITCM_START_ADDR\'\nwire [`ADDR_WIDTH - 1 : 0 ] instr_itcm_addr_rd_from_0 = instr_itcm_addr - `ITCM_START_ADDR;\n                                                                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:206: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nwire [`ADDR_WIDTH - 1 : 0 ] instr_itcm_addr_rd_from_0 = instr_itcm_addr - `ITCM_START_ADDR;\n                                                                                          ^\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:209: Define or directive not defined: \'`ADDR_WIDTH\'\nwire [`ADDR_WIDTH - 1 : 0 ] data_itcm_addr_rd_from_0 = data_itcm_addr - `ITCM_START_ADDR;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:209: Define or directive not defined: \'`ITCM_START_ADDR\'\nwire [`ADDR_WIDTH - 1 : 0 ] data_itcm_addr_rd_from_0 = data_itcm_addr - `ITCM_START_ADDR;\n                                                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/itcm.v:209: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nwire [`ADDR_WIDTH - 1 : 0 ] data_itcm_addr_rd_from_0 = data_itcm_addr - `ITCM_START_ADDR;\n                                                                                        ^\n%Error: Exiting due to 36 error(s)\n'
module itcm (


	input clk,
	input rstn,


	input [`ADDR_WIDTH - 1 : 0] instr_itcm_addr,
	input instr_itcm_access,
	output reg [`DATA_WIDTH - 1 : 0] instr_itcm_read_data,
	output reg instr_itcm_read_data_valid,


	output wire data_itcm_ready,
	input data_itcm_access,
	input data_itcm_rd0_wr1,
	input [`ADDR_WIDTH - 1 : 0] data_itcm_addr,
	input wire [3:0] data_itcm_byte_strobe,
	input wire [`DATA_WIDTH - 1 : 0] data_itcm_write_data,
	output reg [`DATA_WIDTH - 1 : 0] data_itcm_read_data,
	output reg data_itcm_read_data_valid,


	input wire IAHB_ready,
	input wire [`DATA_WIDTH - 1 : 0] IAHB_read_data,
	input wire IAHB_read_data_valid,
	output reg itcm_auto_load,
	output reg[`ADDR_WIDTH - 1 : 0 ] itcm_auto_load_addr

);






wire [`ADDR_WIDTH - 1 : 0] itcm_size = `ITCM_SIZE;
wire itcm_size_nz = (itcm_size!=0);

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		itcm_auto_load <= itcm_size_nz;
	end
	else
	begin
		if(itcm_size_nz)
		begin
			if(itcm_auto_load_addr == `ITCM_START_ADDR + `ITCM_SIZE - 4)
			begin
				itcm_auto_load <= 1'b0;
			end
			else
			begin
				itcm_auto_load <= 1'b1;
			end
		end
		else
		begin
			itcm_auto_load <= 1'b0;
		end
	end
end

reg itcm_auto_load_d1;
always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		itcm_auto_load_d1 <= 1'b0;
	end
	else
	begin
		itcm_auto_load_d1 <= itcm_auto_load;
	end

end



reg addr_s;
always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		addr_s <= 1'b0;
	end
	else
	begin
		if(~itcm_auto_load)
		begin
			addr_s <= 1'b0;
		end
		if(IAHB_ready)
		begin
			addr_s <= 1'b1;
		end
		else
		begin
			addr_s <= addr_s;
		end
	end
end

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		itcm_auto_load_addr <= `ITCM_START_ADDR;
	end
	else
	begin
		if(itcm_auto_load_addr ==`ITCM_START_ADDR + `ITCM_SIZE - 4)
		begin
			itcm_auto_load_addr <=`ITCM_START_ADDR + `ITCM_SIZE - 4; 
		end
		else if(addr_s)
		begin
			if(IAHB_ready)
			begin
				itcm_auto_load_addr <= itcm_auto_load_addr + 32'h4;
			end
			else
			begin
				itcm_auto_load_addr <= itcm_auto_load_addr;
			end
		end
	end
end

wire itcm_write_en;
wire[`ADDR_WIDTH - 1 : 0 ] itcm_write_addr;
wire[`ADDR_WIDTH - 1 : 0 ] itcm_write_addr_from_0;
wire [3:0] itcm_byte_strobe;
wire [`DATA_WIDTH - 1 : 0] itcm_write_data;

wire auto_load_wr = (IAHB_read_data_valid && (itcm_auto_load  || itcm_auto_load_d1));
wire [3:0] auto_load_byte_strobe = 4'hf;

reg[`ADDR_WIDTH - 1 : 0 ] itcm_auto_write_addr;

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		itcm_auto_write_addr <= `ITCM_START_ADDR;
	end
	else
	begin
		if(~itcm_auto_load)
		begin
			itcm_auto_write_addr <= `ITCM_START_ADDR;
		end
		else 
		begin
			if(IAHB_read_data_valid)
			begin
				itcm_auto_write_addr <= itcm_auto_write_addr + 32'h4;
			end
			else
			begin
				itcm_auto_write_addr <= itcm_auto_write_addr;
			end
		end
	end
end




assign itcm_write_en = auto_load_wr || (data_itcm_access && data_itcm_rd0_wr1);
assign itcm_write_data = auto_load_wr? IAHB_read_data : data_itcm_write_data;
assign itcm_write_addr = auto_load_wr? itcm_auto_write_addr : data_itcm_addr;
assign itcm_write_addr_from_0 = itcm_write_addr - `ITCM_START_ADDR;
assign itcm_byte_strobe = auto_load_wr? auto_load_byte_strobe : data_itcm_byte_strobe;


wire [14 : 2 ] itcm_word_addr_wr = itcm_write_addr_from_0[14 : 2 ];

wire [`ADDR_WIDTH - 1 : 0 ] instr_itcm_addr_rd_from_0 = instr_itcm_addr - `ITCM_START_ADDR;
wire [14 : 2 ] instr_itcm_word_addr_rd = instr_itcm_addr_rd_from_0[14 : 2 ];

wire [`ADDR_WIDTH - 1 : 0 ] data_itcm_addr_rd_from_0 = data_itcm_addr - `ITCM_START_ADDR;
wire [14 : 2 ] data_itcm_word_addr_rd = data_itcm_addr_rd_from_0[14 : 2 ];

`ifndef SIM
sram_4Kx32 itcm (
    .CLK	(clk),
    .RADDR1	(instr_itcm_word_addr_rd),
    .RADDR2	(data_itcm_word_addr_rd),
    .WADDR	(itcm_word_addr_wr),
    .WD		(itcm_write_data),
    .WEN	(itcm_write_en),
    .RD1	(instr_itcm_read_data),
    .RD2	(data_itcm_read_data)
);
`else
reg [`DATA_WIDTH - 1 : 0] itcm [`ITCM_SIZE - 1:0];
always @ (posedge clk)
begin
	if (itcm_write_en)
	begin
		if(itcm_byte_strobe[3])
		itcm[itcm_word_addr_wr][31:24] <= itcm_write_data[31:24];
		if(itcm_byte_strobe[2])
		itcm[itcm_word_addr_wr][23:16] <= itcm_write_data[23:16];
		if(itcm_byte_strobe[1])
		itcm[itcm_word_addr_wr][15:8] <= itcm_write_data[15:8];
		if(itcm_byte_strobe[0])
		itcm[itcm_word_addr_wr][7:0] <= itcm_write_data[7:0];
	end
end

reg itcm_read_data_valid;

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		instr_itcm_read_data <= 32'h0;
		data_itcm_read_data <= 32'h0;
	end
	else
	begin
		instr_itcm_read_data <= itcm[instr_itcm_word_addr_rd];
		data_itcm_read_data <= itcm[data_itcm_word_addr_rd];
	end

end
`endif

wire dw_same_loc_as_ir = data_itcm_access && data_itcm_rd0_wr1 && (itcm_word_addr_wr == instr_itcm_word_addr_rd);

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		instr_itcm_read_data_valid <= 1'b0;	
	end
	else 
	begin
		instr_itcm_read_data_valid <= instr_itcm_access && (~dw_same_loc_as_ir) && (~itcm_auto_load);
	end
end

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		data_itcm_read_data_valid <= 1'b0;	
	end
	else 
	begin
		data_itcm_read_data_valid <= data_itcm_access && (~data_itcm_rd0_wr1) && (~itcm_auto_load);
	end
end

assign data_itcm_ready = ~itcm_auto_load;

endmodule
module itcm (


	input clk,
	input rstn,


	input [`ADDR_WIDTH - 1 : 0] instr_itcm_addr,
	input instr_itcm_access,
	output reg [`DATA_WIDTH - 1 : 0] instr_itcm_read_data,
	output reg instr_itcm_read_data_valid,


	output wire data_itcm_ready,
	input data_itcm_access,
	input data_itcm_rd0_wr1,
	input [`ADDR_WIDTH - 1 : 0] data_itcm_addr,
	input wire [3:0] data_itcm_byte_strobe,
	input wire [`DATA_WIDTH - 1 : 0] data_itcm_write_data,
	output reg [`DATA_WIDTH - 1 : 0] data_itcm_read_data,
	output reg data_itcm_read_data_valid,


	input wire IAHB_ready,
	input wire [`DATA_WIDTH - 1 : 0] IAHB_read_data,
	input wire IAHB_read_data_valid,
	output reg itcm_auto_load,
	output reg[`ADDR_WIDTH - 1 : 0 ] itcm_auto_load_addr

);







wire [`ADDR_WIDTH - 1 : 0] itcm_size = `ITCM_SIZE;
wire itcm_size_nz = (itcm_size!=0);

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		itcm_auto_load <= itcm_size_nz;
	end
	else
	begin
		if(itcm_size_nz)
		begin
			if(itcm_auto_load_addr == `ITCM_START_ADDR + `ITCM_SIZE - 4)
			begin
				itcm_auto_load <= 1'b0;
			end
			else
			begin
				itcm_auto_load <= 1'b1;
			end
		end
		else
		begin
			itcm_auto_load <= 1'b0;
		end
	end
end

reg itcm_auto_load_d1;
always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		itcm_auto_load_d1 <= 1'b0;
	end
	else
	begin
		itcm_auto_load_d1 <= itcm_auto_load;
	end

end



reg addr_s;
always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		addr_s <= 1'b0;
	end
	else
	begin
		if(~itcm_auto_load)
		begin
			addr_s <= 1'b0;
		end
		if(IAHB_ready)
		begin
			addr_s <= 1'b1;
		end
		else
		begin
			addr_s <= addr_s;
		end
	end
end

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		itcm_auto_load_addr <= `ITCM_START_ADDR;
	end
	else
	begin
		if(itcm_auto_load_addr ==`ITCM_START_ADDR + `ITCM_SIZE - 4)
		begin
			itcm_auto_load_addr <=`ITCM_START_ADDR + `ITCM_SIZE - 4; 
		end
		else if(addr_s)
		begin
			if(IAHB_ready)
			begin
				itcm_auto_load_addr <= itcm_auto_load_addr + 32'h4;
			end
			else
			begin
				itcm_auto_load_addr <= itcm_auto_load_addr;
			end
		end
	end
end

wire itcm_write_en;
wire[`ADDR_WIDTH - 1 : 0 ] itcm_write_addr;
wire[`ADDR_WIDTH - 1 : 0 ] itcm_write_addr_from_0;
wire [3:0] itcm_byte_strobe;
wire [`DATA_WIDTH - 1 : 0] itcm_write_data;

wire auto_load_wr = (IAHB_read_data_valid && (itcm_auto_load  || itcm_auto_load_d1));
wire [3:0] auto_load_byte_strobe = 4'hf;

reg[`ADDR_WIDTH - 1 : 0 ] itcm_auto_write_addr;

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		itcm_auto_write_addr <= `ITCM_START_ADDR;
	end
	else
	begin
		if(~itcm_auto_load)
		begin
			itcm_auto_write_addr <= `ITCM_START_ADDR;
		end
		else 
		begin
			if(IAHB_read_data_valid)
			begin
				itcm_auto_write_addr <= itcm_auto_write_addr + 32'h4;
			end
			else
			begin
				itcm_auto_write_addr <= itcm_auto_write_addr;
			end
		end
	end
end




assign itcm_write_en = auto_load_wr || (data_itcm_access && data_itcm_rd0_wr1);
assign itcm_write_data = auto_load_wr? IAHB_read_data : data_itcm_write_data;
assign itcm_write_addr = auto_load_wr? itcm_auto_write_addr : data_itcm_addr;
assign itcm_write_addr_from_0 = itcm_write_addr - `ITCM_START_ADDR;
assign itcm_byte_strobe = auto_load_wr? auto_load_byte_strobe : data_itcm_byte_strobe;


wire [14 : 2 ] itcm_word_addr_wr = itcm_write_addr_from_0[14 : 2 ];

wire [`ADDR_WIDTH - 1 : 0 ] instr_itcm_addr_rd_from_0 = instr_itcm_addr - `ITCM_START_ADDR;
wire [14 : 2 ] instr_itcm_word_addr_rd = instr_itcm_addr_rd_from_0[14 : 2 ];

wire [`ADDR_WIDTH - 1 : 0 ] data_itcm_addr_rd_from_0 = data_itcm_addr - `ITCM_START_ADDR;
wire [14 : 2 ] data_itcm_word_addr_rd = data_itcm_addr_rd_from_0[14 : 2 ];

`ifndef SIM
sram_4Kx32 itcm (
    .CLK	(clk),
    .RADDR1	(instr_itcm_word_addr_rd),
    .RADDR2	(data_itcm_word_addr_rd),
    .WADDR	(itcm_word_addr_wr),
    .WD		(itcm_write_data),
    .WEN	(itcm_write_en),
    .RD1	(instr_itcm_read_data),
    .RD2	(data_itcm_read_data)
);
`else
reg [`DATA_WIDTH - 1 : 0] itcm [`ITCM_SIZE - 1:0];
always @ (posedge clk)
begin
	if (itcm_write_en)
	begin
		if(itcm_byte_strobe[3])
		itcm[itcm_word_addr_wr][31:24] <= itcm_write_data[31:24];
		if(itcm_byte_strobe[2])
		itcm[itcm_word_addr_wr][23:16] <= itcm_write_data[23:16];
		if(itcm_byte_strobe[1])
		itcm[itcm_word_addr_wr][15:8] <= itcm_write_data[15:8];
		if(itcm_byte_strobe[0])
		itcm[itcm_word_addr_wr][7:0] <= itcm_write_data[7:0];
	end
end

reg itcm_read_data_valid;

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		instr_itcm_read_data <= 32'h0;
		data_itcm_read_data <= 32'h0;
	end
	else
	begin
		instr_itcm_read_data <= itcm[instr_itcm_word_addr_rd];
		data_itcm_read_data <= itcm[data_itcm_word_addr_rd];
	end

end
`endif

wire dw_same_loc_as_ir = data_itcm_access && data_itcm_rd0_wr1 && (itcm_word_addr_wr == instr_itcm_word_addr_rd);

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		instr_itcm_read_data_valid <= 1'b0;	
	end
	else 
	begin
		instr_itcm_read_data_valid <= instr_itcm_access && (~dw_same_loc_as_ir) && (~itcm_auto_load);
	end
end

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		data_itcm_read_data_valid <= 1'b0;	
	end
	else 
	begin
		data_itcm_read_data_valid <= data_itcm_access && (~data_itcm_rd0_wr1) && (~itcm_auto_load);
	end
end

assign data_itcm_ready = ~itcm_auto_load;

endmodule