data/full_repos/permissive/162928820/main_con.v
1: b'%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:116: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'num0_reg\' generates 4 bits.\n                                                                   : ... In instance main_con\n frequency <= num0_reg + num1_reg*10 + num2_reg*100 + num3_reg*1000;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:148: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'yshang\' generates 32 bits.\n                                                                   : ... In instance main_con\n  temp = (addr + 1\'b1) * (yshang >> 8) + (((addr + 1\'b1) * (yshang && 8\'b11111111)) >> 8);\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:148: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                   : ... In instance main_con\n  temp = (addr + 1\'b1) * (yshang >> 8) + (((addr + 1\'b1) * (yshang && 8\'b11111111)) >> 8);\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:148: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addr\' generates 8 bits.\n                                                                   : ... In instance main_con\n  temp = (addr + 1\'b1) * (yshang >> 8) + (((addr + 1\'b1) * (yshang && 8\'b11111111)) >> 8);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:148: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addr\' generates 8 bits.\n                                                                   : ... In instance main_con\n  temp = (addr + 1\'b1) * (yshang >> 8) + (((addr + 1\'b1) * (yshang && 8\'b11111111)) >> 8);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:157: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                   : ... In instance main_con\n  yshang_temp <= 1\'b0;\n              ^~\n%Error: Exiting due to 6 warning(s)\n'
module div_rill(
	input[31:0] a, 
	input[15:0] b,
	
	output reg [31:0] yshang,
	output reg [15:0] yyushu
	);
 
reg[31:0] tempa;
reg[15:0] tempb;
reg[47:0] temp_a;
reg[47:0] temp_b;
 
integer i;
 
always @(a or b)
begin
    tempa <= a;
    tempb <= b;
end
 
always @(tempa or tempb)
begin
    temp_a = {16'h0000,tempa};
    temp_b = {tempb,32'h00000000}; 
    for(i = 0;i < 32;i = i + 1)
        begin
            temp_a = {temp_a[46:0],1'b0};
            if(temp_a[47:32] >= tempb)
                temp_a = temp_a - temp_b + 1'b1;
            else
				temp_a = temp_a;
        end
 
    yshang <= temp_a[31:0];
    yyushu <= temp_a[47:32];
end
 
endmodule
module div_rill(
	input[31:0] a, 
	input[15:0] b,
	
	output reg [31:0] yshang,
	output reg [15:0] yyushu
	);

 
reg[31:0] tempa;
reg[15:0] tempb;
reg[47:0] temp_a;
reg[47:0] temp_b;
 
integer i;
 
always @(a or b)
begin
    tempa <= a;
    tempb <= b;
end
 
always @(tempa or tempb)
begin
    temp_a = {16'h0000,tempa};
    temp_b = {tempb,32'h00000000}; 
    for(i = 0;i < 32;i = i + 1)
        begin
            temp_a = {temp_a[46:0],1'b0};
            if(temp_a[47:32] >= tempb)
                temp_a = temp_a - temp_b + 1'b1;
            else
				temp_a = temp_a;
        end
 
    yshang <= temp_a[31:0];
    yyushu <= temp_a[47:32];
end
 
endmodule