data/full_repos/permissive/20759093/CPU_TOP.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/20759093/CPU_TOP.v:241: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'Single_Cycle_CPU\'\nmodule Single_Cycle_CPU(\n       ^~~~~~~~~~~~~~~~\n                                                                    : ... Top module \'mux_2_to_1_5\'\nmodule mux_2_to_1_5(\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/20759093/CPU_TOP.v:496: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                 : ... In instance Single_Cycle_CPU.M4\n            4\'b1001 : result <= (A < B);\n                             ^~\n%Error: data/full_repos/permissive/20759093/CPU_TOP.v:104: Cannot find file containing module: \'RAM_A\'\n    RAM_A M8(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A.v\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A.sv\n             RAM_A\n             RAM_A.v\n             RAM_A.sv\n             obj_dir/RAM_A\n             obj_dir/RAM_A.v\n             obj_dir/RAM_A.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module Single_Cycle_CPU(
    input clk_in,
    input btn_t,
    input [7:0]sw,
    output [6:0]seg,
    output [3:0]an
);
    wire [31:0]pc_now, inst, read_data_1, read_data_2, debug_output, alu_output, pc_t1, pc_t2, imm, memory_out;
    wire [31:0]mux_out_2, mux_out_3, mux_out_5, mux_out_6, mux_out_7;
    wire [4:0] mux_out_1;
	wire [1:0] RegDst, Jump;
    wire btn, clk_100M, RegWrite, ALUSrc, MemRead, MemtoReg, MemWrite, JumpReg, Branch, Equal, JumpLink, zero, mux_out_4;
    wire [3:0]ALUCtrl;
    reg clk_50M;
	 wire clk_25M;
    reg [15:0] disp_num;
	 reg [31:0] display_num, counter;
	 
	 always @(posedge clk_in) counter = counter + 1'b1;

    assign clk_100M = clk_in;
    
    initial begin


    end
    



    



	
    assign clk_25M = counter[25];

    program_counter M0(
        .clk(clk_25M),
        .pc_next(mux_out_6),
        .pc_now(pc_now)
    );

    ROM_A M1(
        .addr({2'b00, pc_now[31:2]}),
        .inst(inst)
    );

    control M2(
        .op(inst[31:26]),
        .funct(inst[5:0]),
        .RegDst(RegDst),
        .RegWrite(RegWrite),
        .ALUSrc(ALUSrc),
        .MemRead(MemRead),
        .MemWrite(MemWrite),
        .MemtoReg(MemtoReg),
        .Jump(Jump),
        .Branch(Branch),
        .Equal(Equal),
        .JumpLink(JumpLink),
        .ALUCtrl(ALUCtrl)
    );

    register_file M3(
        .clk(clk_25M),
        .read_register_1(inst[25:21]),
        .read_register_2(inst[20:16]),
        .write_register(mux_out_1),
        .debug_input(sw[4:0]),
        .write_data(mux_out_7),
        .RegWrite(RegWrite),
        .read_data_1(read_data_1),
        .read_data_2(read_data_2),
        .debug_output(debug_output)
    );

    alu M4(
        .alu_ctl(ALUCtrl),
        .A(read_data_1),
        .B(mux_out_2),
        .zero(zero),
        .result(alu_output)
    );

    adder M5(
        .A(pc_now),
        .B(32'd4),
        .result(pc_t1)
    );

    adder M6(
        .A(pc_t1),
        .B({imm[29:0], 2'b00}),
        .result(pc_t2)
    );

    sign_extend M7(
        .imm_number(inst[15:0]),
        .extended_number(imm)
    );

    RAM_A M8(
        .clk(clk_100M),
        .a({2'b00, alu_output[31:2]}),
        .d(read_data_2),
        .we(MemWrite),
        .spo(memory_out)
     );
	  
	  always @(*) begin
			case (sw[7:6])
				2'b01: display_num <= pc_now;
				2'b10: display_num <= inst;
				2'b11: display_num <= 32'hFFFFFFFF;
				default: display_num <= debug_output;
			endcase
		end
     
     always @(*) begin
        if (sw[5]) begin
               disp_num <= display_num[31:16];
          end else begin
              disp_num <= display_num[15:0];
          end
     end
     
    display M9(
        .clk(clk_100M),
        .disp_num(disp_num),
        .seg(seg),
        .anode(an)
    );

     mux_4_to_1_5 U1(
         .A(inst[20:16]),
         .B(inst[15:11]),
         .C(5'd31),
         .D(5'b0),
         .enable(RegDst),
         .O(mux_out_1)
     );

     mux_2_to_1_32 U2(
         .A(read_data_2),
         .B(imm),
         .enable(ALUSrc),
         .O(mux_out_2)
     );

     mux_2_to_1_32 U3(
         .A(alu_output),
         .B(memory_out),
         .enable(MemtoReg),
         .O(mux_out_3)
     );

     mux_2_to_1_1 U4(
        .A(zero),
        .B(~zero),
        .enable(Equal),
        .O(mux_out_4)
    );

     mux_2_to_1_32 U5(
         .A(pc_t1),
         .B(pc_t2),
         .enable(Branch & mux_out_4),
         .O(mux_out_5)
     );
     
     mux_4_to_1_32 U6(
         .A(mux_out_5),
         .B({pc_t1[31:28],inst[25:0], 2'b00}),
         .C(read_data_1),
         .D(32'b0),
         .enable(Jump),
         .O(mux_out_6)
     );

     mux_2_to_1_32 U7(
        .A(mux_out_3),
        .B(pc_t1),
        .enable(JumpLink),
        .O(mux_out_7)
    );

     glitch_filter U8(
        .clk(clk_100M),
        .key_in(btn_t),
        .key_out(btn)
     );

endmodule
module Single_Cycle_CPU(
    input clk_in,
    input btn_t,
    input [7:0]sw,
    output [6:0]seg,
    output [3:0]an
);

    wire [31:0]pc_now, inst, read_data_1, read_data_2, debug_output, alu_output, pc_t1, pc_t2, imm, memory_out;
    wire [31:0]mux_out_2, mux_out_3, mux_out_5, mux_out_6, mux_out_7;
    wire [4:0] mux_out_1;
	wire [1:0] RegDst, Jump;
    wire btn, clk_100M, RegWrite, ALUSrc, MemRead, MemtoReg, MemWrite, JumpReg, Branch, Equal, JumpLink, zero, mux_out_4;
    wire [3:0]ALUCtrl;
    reg clk_50M;
	 wire clk_25M;
    reg [15:0] disp_num;
	 reg [31:0] display_num, counter;
	 
	 always @(posedge clk_in) counter = counter + 1'b1;

    assign clk_100M = clk_in;
    
    initial begin


    end
    



    



	
    assign clk_25M = counter[25];

    program_counter M0(
        .clk(clk_25M),
        .pc_next(mux_out_6),
        .pc_now(pc_now)
    );

    ROM_A M1(
        .addr({2'b00, pc_now[31:2]}),
        .inst(inst)
    );

    control M2(
        .op(inst[31:26]),
        .funct(inst[5:0]),
        .RegDst(RegDst),
        .RegWrite(RegWrite),
        .ALUSrc(ALUSrc),
        .MemRead(MemRead),
        .MemWrite(MemWrite),
        .MemtoReg(MemtoReg),
        .Jump(Jump),
        .Branch(Branch),
        .Equal(Equal),
        .JumpLink(JumpLink),
        .ALUCtrl(ALUCtrl)
    );

    register_file M3(
        .clk(clk_25M),
        .read_register_1(inst[25:21]),
        .read_register_2(inst[20:16]),
        .write_register(mux_out_1),
        .debug_input(sw[4:0]),
        .write_data(mux_out_7),
        .RegWrite(RegWrite),
        .read_data_1(read_data_1),
        .read_data_2(read_data_2),
        .debug_output(debug_output)
    );

    alu M4(
        .alu_ctl(ALUCtrl),
        .A(read_data_1),
        .B(mux_out_2),
        .zero(zero),
        .result(alu_output)
    );

    adder M5(
        .A(pc_now),
        .B(32'd4),
        .result(pc_t1)
    );

    adder M6(
        .A(pc_t1),
        .B({imm[29:0], 2'b00}),
        .result(pc_t2)
    );

    sign_extend M7(
        .imm_number(inst[15:0]),
        .extended_number(imm)
    );

    RAM_A M8(
        .clk(clk_100M),
        .a({2'b00, alu_output[31:2]}),
        .d(read_data_2),
        .we(MemWrite),
        .spo(memory_out)
     );
	  
	  always @(*) begin
			case (sw[7:6])
				2'b01: display_num <= pc_now;
				2'b10: display_num <= inst;
				2'b11: display_num <= 32'hFFFFFFFF;
				default: display_num <= debug_output;
			endcase
		end
     
     always @(*) begin
        if (sw[5]) begin
               disp_num <= display_num[31:16];
          end else begin
              disp_num <= display_num[15:0];
          end
     end
     
    display M9(
        .clk(clk_100M),
        .disp_num(disp_num),
        .seg(seg),
        .anode(an)
    );

     mux_4_to_1_5 U1(
         .A(inst[20:16]),
         .B(inst[15:11]),
         .C(5'd31),
         .D(5'b0),
         .enable(RegDst),
         .O(mux_out_1)
     );

     mux_2_to_1_32 U2(
         .A(read_data_2),
         .B(imm),
         .enable(ALUSrc),
         .O(mux_out_2)
     );

     mux_2_to_1_32 U3(
         .A(alu_output),
         .B(memory_out),
         .enable(MemtoReg),
         .O(mux_out_3)
     );

     mux_2_to_1_1 U4(
        .A(zero),
        .B(~zero),
        .enable(Equal),
        .O(mux_out_4)
    );

     mux_2_to_1_32 U5(
         .A(pc_t1),
         .B(pc_t2),
         .enable(Branch & mux_out_4),
         .O(mux_out_5)
     );
     
     mux_4_to_1_32 U6(
         .A(mux_out_5),
         .B({pc_t1[31:28],inst[25:0], 2'b00}),
         .C(read_data_1),
         .D(32'b0),
         .enable(Jump),
         .O(mux_out_6)
     );

     mux_2_to_1_32 U7(
        .A(mux_out_3),
        .B(pc_t1),
        .enable(JumpLink),
        .O(mux_out_7)
    );

     glitch_filter U8(
        .clk(clk_100M),
        .key_in(btn_t),
        .key_out(btn)
     );

endmodule