data/full_repos/permissive/156539908/include/led-pwm-gamma.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/156539908/include/led-pwm-gamma.v:192: Cell has missing pin: \'rising_edge\'\n            button_debouncer db (\n                             ^~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/156539908/include/led-pwm-gamma.v:192: Cell has missing pin: \'falling_edge\'\n            button_debouncer db (\n                             ^~\n%Error: data/full_repos/permissive/156539908/include/led-pwm-gamma.v:56: Duplicate declaration of signal: \'pll_clk\'\n                                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire        pll_clk;\n                ^~~~~~~\n        data/full_repos/permissive/156539908/include/led-pwm-gamma.v:23: ... Location of original declaration\n        output pll_clk,\n               ^~~~~~~\n%Error: data/full_repos/permissive/156539908/include/led-pwm-gamma.v:450: Duplicate declaration of signal: \'color8_g\'\n    reg [7:0] color8_g;\n              ^~~~~~~~\n        data/full_repos/permissive/156539908/include/led-pwm-gamma.v:445: ... Location of original declaration\n        output [7:0] color8_g);\n                     ^~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module gamma8 (
        input clk,
        input reset,
        input [7:0] color8,
        output [7:0] color8_g);

    reg [7:0] gamma8_table [0:255];
    initial $readmemh("gamma8x8z_table.hex", gamma8_table);

    reg [7:0] color8_g;

    always @(posedge clk)
        if (reset)
            color8_g <= 0;
        else
            color8_g <= gamma8_table[color8];

endmodule
module gamma8 (
        input clk,
        input reset,
        input [7:0] color8,
        output [7:0] color8_g);


    reg [7:0] gamma8_table [0:255];
    initial $readmemh("gamma8x8z_table.hex", gamma8_table);

    reg [7:0] color8_g;

    always @(posedge clk)
        if (reset)
            color8_g <= 0;
        else
            color8_g <= gamma8_table[color8];

endmodule