data/full_repos/permissive/210844779/lab1/1.a.1/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.a.1/test.v:14: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210844779/lab1/1.a.1/test.v:7: Cannot find file containing module: \'fa4bit\'\nfa4bit u0(A,B,C,Sum,Carry);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab1/1.a.1,data/full_repos/permissive/210844779/fa4bit\n             data/full_repos/permissive/210844779/lab1/1.a.1,data/full_repos/permissive/210844779/fa4bit.v\n             data/full_repos/permissive/210844779/lab1/1.a.1,data/full_repos/permissive/210844779/fa4bit.sv\n             fa4bit\n             fa4bit.v\n             fa4bit.sv\n             obj_dir/fa4bit\n             obj_dir/fa4bit.v\n             obj_dir/fa4bit.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab1/1.a.1/test.v:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                         : ... In instance tb\n   A=$random;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab1/1.a.1/test.v:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                         : ... In instance tb\n   B=$random;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab1/1.a.1/test.v:13: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                         : ... In instance tb\n   C=$random;\n    ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;

  reg [3:0]A,B;
  reg C;
  wire [3:0]Sum;
  wire Carry;
fa4bit u0(A,B,C,Sum,Carry);
always
begin

   A=$random;
   B=$random;
   C=$random;
   #10;
end

endmodule
module tb;


  reg [3:0]A,B;
  reg C;
  wire [3:0]Sum;
  wire Carry;
fa4bit u0(A,B,C,Sum,Carry);
always
begin

   A=$random;
   B=$random;
   C=$random;
   #10;
end

endmodule