data/full_repos/permissive/160788788/pc.v
data/verilator_xmls/bf8ca94d-1314-4858-8b22-69efb892f965.xml
module pc(clock, reset, in, out);
	input clock, reset;
	input [29:0] in;

	output [29:0] out;

	reg [29:0] pcnow;


	assign out = pcnow;


	initial
	begin
		pcnow <= 30'h00000c00;
	end

	always@(posedge clock, posedge reset)
	begin
		if (reset) pcnow <= 30'h00000c00;
		else pcnow <= in;
	end

endmodule
module pc(clock, reset, in, out);

	input clock, reset;
	input [29:0] in;

	output [29:0] out;

	reg [29:0] pcnow;


	assign out = pcnow;


	initial
	begin
		pcnow <= 30'h00000c00;
	end

	always@(posedge clock, posedge reset)
	begin
		if (reset) pcnow <= 30'h00000c00;
		else pcnow <= in;
	end

endmodule