data/full_repos/permissive/114324064/src/id.v
None: at end of input
1: b'%Error: data/full_repos/permissive/114324064/src/id.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.v\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/114324064/src/id.v:11: Define or directive not defined: \'`InstAddrBus\'\n    input wire[`InstAddrBus]      pc_i,\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`InstAddrBus]      pc_i,\n                           ^\n%Error: data/full_repos/permissive/114324064/src/id.v:12: Define or directive not defined: \'`InstBus\'\n    input wire[`InstBus]          inst_i,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:15: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus]           reg1_data_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:16: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus]           reg2_data_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`RegBus] ex_wdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:20: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus] ex_wdata_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:21: Define or directive not defined: \'`RegAddrBus\'\n    input wire[`RegAddrBus] ex_wd_i,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`RegBus] mem_wdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:25: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus] mem_wdata_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:26: Define or directive not defined: \'`RegAddrBus\'\n    input wire[`RegAddrBus] mem_wd_i,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:29: Define or directive not defined: \'`AluOpBus\'\n    input wire[`AluOpBus] ex_aluop_i,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                    reg2_read_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[`RegAddrBus]       reg1_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:34: Define or directive not defined: \'`RegAddrBus\'\n    output reg[`RegAddrBus]       reg1_addr_o,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:35: Define or directive not defined: \'`RegAddrBus\'\n    output reg[`RegAddrBus]       reg2_addr_o,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:38: Define or directive not defined: \'`AluOpBus\'\n    output reg[`AluOpBus]         aluop_o,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:39: Define or directive not defined: \'`AluSelBus\'\n    output reg[`AluSelBus]        alusel_o,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:40: Define or directive not defined: \'`RegBus\'\n    output reg[`RegBus]           reg1_o,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:41: Define or directive not defined: \'`RegBus\'\n    output reg[`RegBus]           reg2_o,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:42: Define or directive not defined: \'`RegAddrBus\'\n    output reg[`RegAddrBus]       wd_o,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:45: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire                   stallreq,\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:47: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                    branch_flag_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:48: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[`RegBus]           branch_target_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:48: Define or directive not defined: \'`RegBus\'\n    output reg[`RegBus]           branch_target_addr_o,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:49: Define or directive not defined: \'`RegBus\'\n    output reg[`RegBus]           link_addr_o,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:52: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[`RegBus]           offset_o\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:52: Define or directive not defined: \'`RegBus\'\n    output reg[`RegBus]           offset_o\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:63: Define or directive not defined: \'`RegBus\'\n    reg[`RegBus] imm;  \n        ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:63: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`RegBus] imm;  \n               ^\n%Error: data/full_repos/permissive/114324064/src/id.v:64: Define or directive not defined: \'`RegBus\'\n    reg[`RegBus] imm_unsigned;\n        ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:64: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`RegBus] imm_unsigned;\n               ^\n%Error: data/full_repos/permissive/114324064/src/id.v:65: Define or directive not defined: \'`RegBus\'\n    reg[`RegBus] offset_imm;  \n        ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`RegBus] offset_imm;  \n               ^\n%Error: data/full_repos/permissive/114324064/src/id.v:66: Define or directive not defined: \'`RegBus\'\n    reg[`RegBus] offset_imm_unsigned;\n        ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:66: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`RegBus] offset_imm_unsigned;\n               ^\n%Error: data/full_repos/permissive/114324064/src/id.v:70: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] pc_plus_4;\n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:70: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] pc_plus_4;\n                ^\n%Error: data/full_repos/permissive/114324064/src/id.v:74: syntax error, unexpected assign\n    assign pc_plus_4 = pc_i + 4;\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:76: Define or directive not defined: \'`EXE_LB_OP\'\n    assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:77: Define or directive not defined: \'`EXE_LBU_OP\'\n                               (ex_aluop_i == `EXE_LBU_OP) ||\n                                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:78: Define or directive not defined: \'`EXE_LH_OP\'\n                               (ex_aluop_i == `EXE_LH_OP) ||\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:79: Define or directive not defined: \'`EXE_LHU_OP\'\n                               (ex_aluop_i == `EXE_LHU_OP) ||\n                                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:80: Define or directive not defined: \'`EXE_LW_OP\'\n                               (ex_aluop_i == `EXE_LW_OP));\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:84: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:85: Define or directive not defined: \'`EXE_NOP_OP\'\n            aluop_o <= `EXE_NOP_OP;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:86: Define or directive not defined: \'`EXE_RES_NOP\'\n            alusel_o <= `EXE_RES_NOP;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:87: Define or directive not defined: \'`NOPRegAddr\'\n            wd_o <= `NOPRegAddr;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:88: Define or directive not defined: \'`WriteDisable\'\n            wreg_o <= `WriteDisable;\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module id(

    input wire                    rst,


    input wire                    inst_invalid_i,


    input wire[`InstAddrBus]      pc_i,
    input wire[`InstBus]          inst_i,


    input wire[`RegBus]           reg1_data_i,
    input wire[`RegBus]           reg2_data_i,


    input wire ex_wreg_i,
    input wire[`RegBus] ex_wdata_i,
    input wire[`RegAddrBus] ex_wd_i,


    input wire mem_wreg_i,
    input wire[`RegBus] mem_wdata_i,
    input wire[`RegAddrBus] mem_wd_i,


    input wire[`AluOpBus] ex_aluop_i,


    output reg                    reg1_read_o,
    output reg                    reg2_read_o,
    output reg[`RegAddrBus]       reg1_addr_o,
    output reg[`RegAddrBus]       reg2_addr_o,


    output reg[`AluOpBus]         aluop_o,
    output reg[`AluSelBus]        alusel_o,
    output reg[`RegBus]           reg1_o,
    output reg[`RegBus]           reg2_o,
    output reg[`RegAddrBus]       wd_o,
    output reg                    wreg_o,

    output wire                   stallreq,

    output reg                    branch_flag_o,
    output reg[`RegBus]           branch_target_addr_o,
    output reg[`RegBus]           link_addr_o,
    output reg                    next_inst_invalid_o,

    output reg[`RegBus]           offset_o
);

    wire[6:0] opcode = inst_i[6:0];
    wire[2:0] funct3 = inst_i[14:12];
    wire[6:0] funct7 = inst_i[31:25];

    wire[4:0] rd_addr = inst_i[11:7];
    wire[4:0] rs1_addr = inst_i[19:15];
    wire[4:0] rs2_addr = inst_i[24:20];

    reg[`RegBus] imm;
    reg[`RegBus] imm_unsigned;
    reg[`RegBus] offset_imm;
    reg[`RegBus] offset_imm_unsigned;
    reg instvalid;
    reg stallreq_for_reg1_loadrelate;
    reg stallreq_for_reg2_loadrelate;
    wire[`RegBus] pc_plus_4;
    wire pre_inst_is_load;


    assign pc_plus_4 = pc_i + 4;
    assign stallreq = stallreq_for_reg1_loadrelate | stallreq_for_reg2_loadrelate;
    assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||
                               (ex_aluop_i == `EXE_LBU_OP) ||
                               (ex_aluop_i == `EXE_LH_OP) ||
                               (ex_aluop_i == `EXE_LHU_OP) ||
                               (ex_aluop_i == `EXE_LW_OP));


    always @ (*) begin
        if (rst == `RstEnable) begin
            aluop_o <= `EXE_NOP_OP;
            alusel_o <= `EXE_RES_NOP;
            wd_o <= `NOPRegAddr;
            wreg_o <= `WriteDisable;
            instvalid <= `InstValid;
            reg1_read_o <= 1'b0;
            reg2_read_o <= 1'b0;
            reg1_addr_o <= `NOPRegAddr;
            reg2_addr_o <= `NOPRegAddr;
            imm <= 32'h0;
            link_addr_o <= `ZeroWord;
            branch_target_addr_o <= `ZeroWord;
            branch_flag_o <= `NotBranch;
            offset_o <= `ZeroWord;
            next_inst_invalid_o <= `InstValid;
        end else if (inst_invalid_i == `InstInvalid) begin
            aluop_o <= `EXE_NOP_OP;
            alusel_o <= `EXE_RES_NOP;
            wd_o <= `NOPRegAddr;
            wreg_o <= `WriteDisable;
            instvalid <= `InstInvalid;
            reg1_read_o <= 1'b0;
            reg2_read_o <= 1'b0;
            reg1_addr_o <= `NOPRegAddr;
            reg2_addr_o <= `NOPRegAddr;
            imm <= 32'h0;
            link_addr_o <= `ZeroWord;
            branch_target_addr_o <= `ZeroWord;
            branch_flag_o <= `NotBranch;
            offset_o <= `ZeroWord;
            next_inst_invalid_o <= `InstValid;
        end else begin
            aluop_o <= `EXE_NOP_OP;
            alusel_o <= `EXE_RES_NOP;
            wd_o <= rd_addr;
            wreg_o <= `WriteDisable;
            instvalid <= `InstInvalid;
            reg1_read_o <= 1'b0;
            reg2_read_o <= 1'b0;
            reg1_addr_o <= rs1_addr;
            reg2_addr_o <= rs2_addr;
            imm <= `ZeroWord;
            link_addr_o <= `ZeroWord;
            branch_target_addr_o <= `ZeroWord;
            branch_flag_o <= `NotBranch;
            offset_o <= `ZeroWord;
            next_inst_invalid_o <= `InstValid;

            case (opcode)
                `OPCODE_AUIPC: begin
                    aluop_o <= `EXE_OR_OP;
                    alusel_o <= `EXE_RES_LOGIC;
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    reg1_addr_o <= 5'b00000;
                    imm <= {inst_i[31:12], 12'h0} + pc_i;
                end
                `OPCODE_LUI: begin
                    aluop_o <= `EXE_OR_OP;
                    alusel_o <= `EXE_RES_LOGIC;
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    reg1_addr_o <= 5'b00000;
                    imm <= {inst_i[31:12], 12'h0};
                end
                `OPCODE_JAL: begin
                    aluop_o <= `EXE_JAL_OP;
                    alusel_o <= `EXE_RES_JUMP_BRANCH;
                    wreg_o <= `WriteEnable;
                    link_addr_o <= pc_plus_4;
                    branch_flag_o <= `Branch;
                    branch_target_addr_o <= pc_i + {{12{inst_i[31:31]}},
                        inst_i[19:12], inst_i[20:20], inst_i[30:21], 1'b0};
                    next_inst_invalid_o <= `InstInvalid;
                end
                `OPCODE_JALR: begin
                    aluop_o <= `EXE_JALR_OP;
                    alusel_o <= `EXE_RES_JUMP_BRANCH;
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    link_addr_o <= pc_plus_4;
                    branch_flag_o <= `Branch;
                    branch_target_addr_o <= (reg1_o + {{21{inst_i[31:31]}},
                        inst_i[30:20]}) & {31'b1, 1'b0};
                    next_inst_invalid_o <= `InstInvalid;
                end
                `OPCODE_BRANCH: begin
                    alusel_o <= `EXE_RES_JUMP_BRANCH;
                    reg1_read_o <= 1'b1;
                    reg2_read_o <= 1'b1;
                    offset_imm <= {{20{inst_i[31:31]}},
                        inst_i[7:7], inst_i[30:25], inst_i[11:8], 1'b0};
                    offset_imm_unsigned <= {19'b0, inst_i[31:31],
                        inst_i[7:7], inst_i[30:25], inst_i[11:8], 1'b0};
                    case (funct3)
                        `FUNCT3_BEQ: begin
                            aluop_o <= `EXE_BEQ_OP;
                            if (reg1_o == reg2_o) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        `FUNCT3_BNE: begin
                            aluop_o <= `EXE_BNE_OP;
                            if (reg1_o != reg2_o) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        `FUNCT3_BLT: begin
                            aluop_o <= `EXE_BLT_OP;
                            if ((reg1_o[31] == 1'b1 && reg2_o[31] == 1'b0) ||
                                (reg1_o[31] == reg2_o[31] && reg1_o[30:0] < reg2_o[30:0])) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        `FUNCT3_BGE: begin
                            aluop_o <= `EXE_BGE_OP;
                            if ((reg1_o[31] == 1'b0 && reg2_o[31] == 1'b1) ||
                                (reg1_o[31] == reg2_o[31] && reg1_o[30:0] >= reg2_o[30:0])) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        `FUNCT3_BLTU: begin
                            aluop_o <= `EXE_BLTU_OP;
                            imm <= imm_unsigned;
                            if (reg1_o < reg2_o) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        `FUNCT3_BGEU: begin
                            aluop_o <= `EXE_BGEU_OP;
                            imm <= imm_unsigned;
                            if (reg1_o >= reg2_o) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        default: begin
                        end
                    endcase
                end
                `OPCODE_LOAD: begin
                    alusel_o <= `EXE_RES_LOAD_STORE;
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    offset_o <= {{20{inst_i[31:31]}}, inst_i[31:20]};
                    case (funct3)
                        `FUNCT3_LB: begin
                            aluop_o <= `EXE_LB_OP;
                        end
                        `FUNCT3_LH: begin
                            aluop_o <= `EXE_LH_OP;
                        end
                        `FUNCT3_LW: begin
                            aluop_o <= `EXE_LW_OP;
                        end
                        `FUNCT3_LBU: begin
                            aluop_o <= `EXE_LBU_OP;
                        end
                        `FUNCT3_LHU: begin
                            aluop_o <= `EXE_LHU_OP;
                        end
                        default: begin
                        end
                    endcase
                end
                `OPCODE_STORE: begin
                    alusel_o <= `EXE_RES_LOAD_STORE;
                    reg1_read_o <= 1'b1;
                    reg2_read_o <= 1'b1;
                    offset_o <= {{21{inst_i[31:31]}}, inst_i[30:25], inst_i[11:7]};
                    case (funct3)
                        `FUNCT3_SB: begin
                            aluop_o <= `EXE_SB_OP;
                        end
                        `FUNCT3_SH: begin
                            aluop_o <= `EXE_SH_OP;
                        end
                        `FUNCT3_SW: begin
                            aluop_o <= `EXE_SW_OP;
                        end
                        default: begin
                        end
                    endcase
                end
                `OPCODE_OP_IMM: begin
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    reg2_read_o <= 1'b0;
                    imm <= {{20{inst_i[31:31]}}, inst_i[31:20]};
                    wd_o <= rd_addr;
                    instvalid <= `InstValid;
                    case (funct3)
                        `FUNCT3_XORI: begin
                            aluop_o <= `EXE_XOR_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_ORI: begin
                            aluop_o <= `EXE_OR_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_ANDI: begin
                            aluop_o <= `EXE_AND_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_SLLI: begin
                            aluop_o <= `EXE_SLL_OP;
                            alusel_o <= `EXE_RES_SHIFT;
                            imm[4:0] <= inst_i[24:20];
                        end
                        `FUNCT3_SRLI: begin
                            if (funct7 == `FUNCT7_SRL) begin
                                aluop_o <= `EXE_SRL_OP;
                                alusel_o <= `EXE_RES_SHIFT;
                                imm[4:0] <= inst_i[24:20];
                            end else if (funct7 == `FUNCT7_SRA) begin
                                aluop_o <= `EXE_SRA_OP;
                                alusel_o <= `EXE_RES_SHIFT;
                                imm[4:0] <= inst_i[24:20];
                            end
                        end
                        `FUNCT3_SLTI: begin
                            aluop_o <= `EXE_SLT_OP;
                            alusel_o <= `EXE_RES_ARITHMETIC;
                        end
                        `FUNCT3_SLTIU: begin
                            aluop_o <= `EXE_SLTU_OP;
                            alusel_o <= `EXE_RES_ARITHMETIC;
                        end
                        `FUNCT3_ADDI: begin
                            aluop_o <= `EXE_ADD_OP;
                            alusel_o <= `EXE_RES_ARITHMETIC;
                        end
                        default: begin
                        end
                    endcase
                end
                `OPCODE_OP: begin
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    reg2_read_o <= 1'b1;
                    wd_o <= rd_addr;
                    instvalid <= `InstValid;
                    case (funct3)
                        `FUNCT3_XOR: begin
                            aluop_o <= `EXE_XOR_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_OR: begin
                            aluop_o <= `EXE_OR_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_AND: begin
                            aluop_o <= `EXE_AND_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_SLL: begin
                            aluop_o <= `EXE_SLL_OP;
                            alusel_o <= `EXE_RES_SHIFT;
                        end
                        `FUNCT3_SRL: begin
                            if (funct7 == `FUNCT7_SRL) begin
                                aluop_o <= `EXE_SRL_OP;
                                alusel_o <= `EXE_RES_SHIFT;
                            end else if (funct7 == `FUNCT7_SRA) begin
                                aluop_o <= `EXE_SRA_OP;
                                alusel_o <= `EXE_RES_SHIFT;
                            end
                        end
                        `FUNCT3_SLT: begin
                            aluop_o <= `EXE_SLT_OP;
                            alusel_o <= `EXE_RES_ARITHMETIC;
                        end
                        `FUNCT3_SLTU: begin
                            aluop_o <= `EXE_SLTU_OP;
                            alusel_o <= `EXE_RES_ARITHMETIC;
                        end
                        `FUNCT3_ADD: begin
                            if (funct7 == `FUNCT7_ADD) begin
                                aluop_o <= `EXE_ADD_OP;
                                alusel_o <= `EXE_RES_ARITHMETIC;
                            end else if(funct7 == `FUNCT7_SUB) begin
                                aluop_o <= `EXE_SUB_OP;
                                alusel_o <= `EXE_RES_ARITHMETIC;
                            end
                        end
                        default: begin
                        end
                    endcase
                end
                default: begin
                end
            endcase

        end
    end


    always @ (*) begin
        stallreq_for_reg1_loadrelate <= `NoStop;
        if(rst == `RstEnable) begin
            reg1_o <= `ZeroWord;
        end else if (pre_inst_is_load == 1'b1 && ex_wd_i == reg1_addr_o
                                              && reg1_read_o == 1'b1) begin
            stallreq_for_reg1_loadrelate <= `Stop;
        end else if ((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
                                           && (ex_wd_i == reg1_addr_o)) begin
            reg1_o <= ex_wdata_i;
        end else if ((reg1_read_o == 1'b1) && (mem_wreg_i == 1'b1)
                                           && (mem_wd_i == reg1_addr_o)) begin
            reg1_o <= mem_wdata_i;
        end else if(reg1_read_o == 1'b1) begin
            reg1_o <= reg1_data_i;
        end else if(reg1_read_o == 1'b0) begin
            reg1_o <= imm;
        end else begin
            reg1_o <= `ZeroWord;
        end
    end
    always @ (*) begin
        stallreq_for_reg2_loadrelate <= `NoStop;
        if(rst == `RstEnable) begin
            reg2_o <= `ZeroWord;
        end else if (pre_inst_is_load == 1'b1 && ex_wd_i == reg2_addr_o
                                              && reg2_read_o == 1'b1) begin
            stallreq_for_reg2_loadrelate <= `Stop;
        end else if ((reg2_read_o == 1'b1) && (ex_wreg_i == 1'b1)
                                           && (ex_wd_i == reg2_addr_o)) begin
            reg2_o <= ex_wdata_i;
        end else if ((reg2_read_o == 1'b1) && (mem_wreg_i == 1'b1)
                                           && (mem_wd_i == reg2_addr_o)) begin
            reg2_o <= mem_wdata_i;
        end else if(reg2_read_o == 1'b1) begin
            reg2_o <= reg2_data_i;
        end else if(reg2_read_o == 1'b0) begin
            reg2_o <= imm;
        end else begin
            reg2_o <= `ZeroWord;
        end
    end

endmodule
module id(

    input wire                    rst,


    input wire                    inst_invalid_i,


    input wire[`InstAddrBus]      pc_i,
    input wire[`InstBus]          inst_i,


    input wire[`RegBus]           reg1_data_i,
    input wire[`RegBus]           reg2_data_i,


    input wire ex_wreg_i,
    input wire[`RegBus] ex_wdata_i,
    input wire[`RegAddrBus] ex_wd_i,


    input wire mem_wreg_i,
    input wire[`RegBus] mem_wdata_i,
    input wire[`RegAddrBus] mem_wd_i,


    input wire[`AluOpBus] ex_aluop_i,


    output reg                    reg1_read_o,
    output reg                    reg2_read_o,
    output reg[`RegAddrBus]       reg1_addr_o,
    output reg[`RegAddrBus]       reg2_addr_o,


    output reg[`AluOpBus]         aluop_o,
    output reg[`AluSelBus]        alusel_o,
    output reg[`RegBus]           reg1_o,
    output reg[`RegBus]           reg2_o,
    output reg[`RegAddrBus]       wd_o,
    output reg                    wreg_o,

    output wire                   stallreq,

    output reg                    branch_flag_o,
    output reg[`RegBus]           branch_target_addr_o,
    output reg[`RegBus]           link_addr_o,
    output reg                    next_inst_invalid_o,

    output reg[`RegBus]           offset_o
);


    wire[6:0] opcode = inst_i[6:0];
    wire[2:0] funct3 = inst_i[14:12];
    wire[6:0] funct7 = inst_i[31:25];

    wire[4:0] rd_addr = inst_i[11:7];
    wire[4:0] rs1_addr = inst_i[19:15];
    wire[4:0] rs2_addr = inst_i[24:20];

    reg[`RegBus] imm;
    reg[`RegBus] imm_unsigned;
    reg[`RegBus] offset_imm;
    reg[`RegBus] offset_imm_unsigned;
    reg instvalid;
    reg stallreq_for_reg1_loadrelate;
    reg stallreq_for_reg2_loadrelate;
    wire[`RegBus] pc_plus_4;
    wire pre_inst_is_load;


    assign pc_plus_4 = pc_i + 4;
    assign stallreq = stallreq_for_reg1_loadrelate | stallreq_for_reg2_loadrelate;
    assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||
                               (ex_aluop_i == `EXE_LBU_OP) ||
                               (ex_aluop_i == `EXE_LH_OP) ||
                               (ex_aluop_i == `EXE_LHU_OP) ||
                               (ex_aluop_i == `EXE_LW_OP));


    always @ (*) begin
        if (rst == `RstEnable) begin
            aluop_o <= `EXE_NOP_OP;
            alusel_o <= `EXE_RES_NOP;
            wd_o <= `NOPRegAddr;
            wreg_o <= `WriteDisable;
            instvalid <= `InstValid;
            reg1_read_o <= 1'b0;
            reg2_read_o <= 1'b0;
            reg1_addr_o <= `NOPRegAddr;
            reg2_addr_o <= `NOPRegAddr;
            imm <= 32'h0;
            link_addr_o <= `ZeroWord;
            branch_target_addr_o <= `ZeroWord;
            branch_flag_o <= `NotBranch;
            offset_o <= `ZeroWord;
            next_inst_invalid_o <= `InstValid;
        end else if (inst_invalid_i == `InstInvalid) begin
            aluop_o <= `EXE_NOP_OP;
            alusel_o <= `EXE_RES_NOP;
            wd_o <= `NOPRegAddr;
            wreg_o <= `WriteDisable;
            instvalid <= `InstInvalid;
            reg1_read_o <= 1'b0;
            reg2_read_o <= 1'b0;
            reg1_addr_o <= `NOPRegAddr;
            reg2_addr_o <= `NOPRegAddr;
            imm <= 32'h0;
            link_addr_o <= `ZeroWord;
            branch_target_addr_o <= `ZeroWord;
            branch_flag_o <= `NotBranch;
            offset_o <= `ZeroWord;
            next_inst_invalid_o <= `InstValid;
        end else begin
            aluop_o <= `EXE_NOP_OP;
            alusel_o <= `EXE_RES_NOP;
            wd_o <= rd_addr;
            wreg_o <= `WriteDisable;
            instvalid <= `InstInvalid;
            reg1_read_o <= 1'b0;
            reg2_read_o <= 1'b0;
            reg1_addr_o <= rs1_addr;
            reg2_addr_o <= rs2_addr;
            imm <= `ZeroWord;
            link_addr_o <= `ZeroWord;
            branch_target_addr_o <= `ZeroWord;
            branch_flag_o <= `NotBranch;
            offset_o <= `ZeroWord;
            next_inst_invalid_o <= `InstValid;

            case (opcode)
                `OPCODE_AUIPC: begin
                    aluop_o <= `EXE_OR_OP;
                    alusel_o <= `EXE_RES_LOGIC;
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    reg1_addr_o <= 5'b00000;
                    imm <= {inst_i[31:12], 12'h0} + pc_i;
                end
                `OPCODE_LUI: begin
                    aluop_o <= `EXE_OR_OP;
                    alusel_o <= `EXE_RES_LOGIC;
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    reg1_addr_o <= 5'b00000;
                    imm <= {inst_i[31:12], 12'h0};
                end
                `OPCODE_JAL: begin
                    aluop_o <= `EXE_JAL_OP;
                    alusel_o <= `EXE_RES_JUMP_BRANCH;
                    wreg_o <= `WriteEnable;
                    link_addr_o <= pc_plus_4;
                    branch_flag_o <= `Branch;
                    branch_target_addr_o <= pc_i + {{12{inst_i[31:31]}},
                        inst_i[19:12], inst_i[20:20], inst_i[30:21], 1'b0};
                    next_inst_invalid_o <= `InstInvalid;
                end
                `OPCODE_JALR: begin
                    aluop_o <= `EXE_JALR_OP;
                    alusel_o <= `EXE_RES_JUMP_BRANCH;
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    link_addr_o <= pc_plus_4;
                    branch_flag_o <= `Branch;
                    branch_target_addr_o <= (reg1_o + {{21{inst_i[31:31]}},
                        inst_i[30:20]}) & {31'b1, 1'b0};
                    next_inst_invalid_o <= `InstInvalid;
                end
                `OPCODE_BRANCH: begin
                    alusel_o <= `EXE_RES_JUMP_BRANCH;
                    reg1_read_o <= 1'b1;
                    reg2_read_o <= 1'b1;
                    offset_imm <= {{20{inst_i[31:31]}},
                        inst_i[7:7], inst_i[30:25], inst_i[11:8], 1'b0};
                    offset_imm_unsigned <= {19'b0, inst_i[31:31],
                        inst_i[7:7], inst_i[30:25], inst_i[11:8], 1'b0};
                    case (funct3)
                        `FUNCT3_BEQ: begin
                            aluop_o <= `EXE_BEQ_OP;
                            if (reg1_o == reg2_o) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        `FUNCT3_BNE: begin
                            aluop_o <= `EXE_BNE_OP;
                            if (reg1_o != reg2_o) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        `FUNCT3_BLT: begin
                            aluop_o <= `EXE_BLT_OP;
                            if ((reg1_o[31] == 1'b1 && reg2_o[31] == 1'b0) ||
                                (reg1_o[31] == reg2_o[31] && reg1_o[30:0] < reg2_o[30:0])) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        `FUNCT3_BGE: begin
                            aluop_o <= `EXE_BGE_OP;
                            if ((reg1_o[31] == 1'b0 && reg2_o[31] == 1'b1) ||
                                (reg1_o[31] == reg2_o[31] && reg1_o[30:0] >= reg2_o[30:0])) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        `FUNCT3_BLTU: begin
                            aluop_o <= `EXE_BLTU_OP;
                            imm <= imm_unsigned;
                            if (reg1_o < reg2_o) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        `FUNCT3_BGEU: begin
                            aluop_o <= `EXE_BGEU_OP;
                            imm <= imm_unsigned;
                            if (reg1_o >= reg2_o) begin
                                branch_target_addr_o <= pc_i + offset_imm;
                                branch_flag_o <= `Branch;
                                next_inst_invalid_o <= `InstInvalid;
                            end
                        end
                        default: begin
                        end
                    endcase
                end
                `OPCODE_LOAD: begin
                    alusel_o <= `EXE_RES_LOAD_STORE;
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    offset_o <= {{20{inst_i[31:31]}}, inst_i[31:20]};
                    case (funct3)
                        `FUNCT3_LB: begin
                            aluop_o <= `EXE_LB_OP;
                        end
                        `FUNCT3_LH: begin
                            aluop_o <= `EXE_LH_OP;
                        end
                        `FUNCT3_LW: begin
                            aluop_o <= `EXE_LW_OP;
                        end
                        `FUNCT3_LBU: begin
                            aluop_o <= `EXE_LBU_OP;
                        end
                        `FUNCT3_LHU: begin
                            aluop_o <= `EXE_LHU_OP;
                        end
                        default: begin
                        end
                    endcase
                end
                `OPCODE_STORE: begin
                    alusel_o <= `EXE_RES_LOAD_STORE;
                    reg1_read_o <= 1'b1;
                    reg2_read_o <= 1'b1;
                    offset_o <= {{21{inst_i[31:31]}}, inst_i[30:25], inst_i[11:7]};
                    case (funct3)
                        `FUNCT3_SB: begin
                            aluop_o <= `EXE_SB_OP;
                        end
                        `FUNCT3_SH: begin
                            aluop_o <= `EXE_SH_OP;
                        end
                        `FUNCT3_SW: begin
                            aluop_o <= `EXE_SW_OP;
                        end
                        default: begin
                        end
                    endcase
                end
                `OPCODE_OP_IMM: begin
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    reg2_read_o <= 1'b0;
                    imm <= {{20{inst_i[31:31]}}, inst_i[31:20]};
                    wd_o <= rd_addr;
                    instvalid <= `InstValid;
                    case (funct3)
                        `FUNCT3_XORI: begin
                            aluop_o <= `EXE_XOR_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_ORI: begin
                            aluop_o <= `EXE_OR_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_ANDI: begin
                            aluop_o <= `EXE_AND_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_SLLI: begin
                            aluop_o <= `EXE_SLL_OP;
                            alusel_o <= `EXE_RES_SHIFT;
                            imm[4:0] <= inst_i[24:20];
                        end
                        `FUNCT3_SRLI: begin
                            if (funct7 == `FUNCT7_SRL) begin
                                aluop_o <= `EXE_SRL_OP;
                                alusel_o <= `EXE_RES_SHIFT;
                                imm[4:0] <= inst_i[24:20];
                            end else if (funct7 == `FUNCT7_SRA) begin
                                aluop_o <= `EXE_SRA_OP;
                                alusel_o <= `EXE_RES_SHIFT;
                                imm[4:0] <= inst_i[24:20];
                            end
                        end
                        `FUNCT3_SLTI: begin
                            aluop_o <= `EXE_SLT_OP;
                            alusel_o <= `EXE_RES_ARITHMETIC;
                        end
                        `FUNCT3_SLTIU: begin
                            aluop_o <= `EXE_SLTU_OP;
                            alusel_o <= `EXE_RES_ARITHMETIC;
                        end
                        `FUNCT3_ADDI: begin
                            aluop_o <= `EXE_ADD_OP;
                            alusel_o <= `EXE_RES_ARITHMETIC;
                        end
                        default: begin
                        end
                    endcase
                end
                `OPCODE_OP: begin
                    wreg_o <= `WriteEnable;
                    reg1_read_o <= 1'b1;
                    reg2_read_o <= 1'b1;
                    wd_o <= rd_addr;
                    instvalid <= `InstValid;
                    case (funct3)
                        `FUNCT3_XOR: begin
                            aluop_o <= `EXE_XOR_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_OR: begin
                            aluop_o <= `EXE_OR_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_AND: begin
                            aluop_o <= `EXE_AND_OP;
                            alusel_o <= `EXE_RES_LOGIC;
                        end
                        `FUNCT3_SLL: begin
                            aluop_o <= `EXE_SLL_OP;
                            alusel_o <= `EXE_RES_SHIFT;
                        end
                        `FUNCT3_SRL: begin
                            if (funct7 == `FUNCT7_SRL) begin
                                aluop_o <= `EXE_SRL_OP;
                                alusel_o <= `EXE_RES_SHIFT;
                            end else if (funct7 == `FUNCT7_SRA) begin
                                aluop_o <= `EXE_SRA_OP;
                                alusel_o <= `EXE_RES_SHIFT;
                            end
                        end
                        `FUNCT3_SLT: begin
                            aluop_o <= `EXE_SLT_OP;
                            alusel_o <= `EXE_RES_ARITHMETIC;
                        end
                        `FUNCT3_SLTU: begin
                            aluop_o <= `EXE_SLTU_OP;
                            alusel_o <= `EXE_RES_ARITHMETIC;
                        end
                        `FUNCT3_ADD: begin
                            if (funct7 == `FUNCT7_ADD) begin
                                aluop_o <= `EXE_ADD_OP;
                                alusel_o <= `EXE_RES_ARITHMETIC;
                            end else if(funct7 == `FUNCT7_SUB) begin
                                aluop_o <= `EXE_SUB_OP;
                                alusel_o <= `EXE_RES_ARITHMETIC;
                            end
                        end
                        default: begin
                        end
                    endcase
                end
                default: begin
                end
            endcase

        end
    end


    always @ (*) begin
        stallreq_for_reg1_loadrelate <= `NoStop;
        if(rst == `RstEnable) begin
            reg1_o <= `ZeroWord;
        end else if (pre_inst_is_load == 1'b1 && ex_wd_i == reg1_addr_o
                                              && reg1_read_o == 1'b1) begin
            stallreq_for_reg1_loadrelate <= `Stop;
        end else if ((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
                                           && (ex_wd_i == reg1_addr_o)) begin
            reg1_o <= ex_wdata_i;
        end else if ((reg1_read_o == 1'b1) && (mem_wreg_i == 1'b1)
                                           && (mem_wd_i == reg1_addr_o)) begin
            reg1_o <= mem_wdata_i;
        end else if(reg1_read_o == 1'b1) begin
            reg1_o <= reg1_data_i;
        end else if(reg1_read_o == 1'b0) begin
            reg1_o <= imm;
        end else begin
            reg1_o <= `ZeroWord;
        end
    end
    always @ (*) begin
        stallreq_for_reg2_loadrelate <= `NoStop;
        if(rst == `RstEnable) begin
            reg2_o <= `ZeroWord;
        end else if (pre_inst_is_load == 1'b1 && ex_wd_i == reg2_addr_o
                                              && reg2_read_o == 1'b1) begin
            stallreq_for_reg2_loadrelate <= `Stop;
        end else if ((reg2_read_o == 1'b1) && (ex_wreg_i == 1'b1)
                                           && (ex_wd_i == reg2_addr_o)) begin
            reg2_o <= ex_wdata_i;
        end else if ((reg2_read_o == 1'b1) && (mem_wreg_i == 1'b1)
                                           && (mem_wd_i == reg2_addr_o)) begin
            reg2_o <= mem_wdata_i;
        end else if(reg2_read_o == 1'b1) begin
            reg2_o <= reg2_data_i;
        end else if(reg2_read_o == 1'b0) begin
            reg2_o <= imm;
        end else begin
            reg2_o <= `ZeroWord;
        end
    end

endmodule