data/full_repos/permissive/114324064/src/mem.v
1: b'%Error: data/full_repos/permissive/114324064/src/mem.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.v\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/114324064/src/mem.v:8: Define or directive not defined: \'`RegAddrBus\'\n    input wire[`RegAddrBus]       wd_i,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`RegAddrBus]       wd_i,\n                          ^\n%Error: data/full_repos/permissive/114324064/src/mem.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`RegBus]           wdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:10: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus]           wdata_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:12: Define or directive not defined: \'`AluOpBus\'\n    input wire[`AluOpBus]         aluop_i,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:13: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus]           mem_addr_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:14: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus]           reg2_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:17: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus]           mem_data_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:20: Define or directive not defined: \'`RegBus\'\n    output reg[`RegBus]           mem_addr_o,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:22: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[3:0]               mem_sel_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[`RegBus]           mem_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:23: Define or directive not defined: \'`RegBus\'\n    output reg[`RegBus]           mem_data_o,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[`RegAddrBus]       wd_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:27: Define or directive not defined: \'`RegAddrBus\'\n    output reg[`RegAddrBus]       wd_o,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[`RegBus]           wdata_o\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:29: Define or directive not defined: \'`RegBus\'\n    output reg[`RegBus]           wdata_o\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:33: Define or directive not defined: \'`RstEnable\'\n        if(rst == `RstEnable) begin\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:34: Define or directive not defined: \'`NOPRegAddr\'\n            wd_o <= `NOPRegAddr;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:35: Define or directive not defined: \'`WriteDisable\'\n            wreg_o <= `WriteDisable;\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:36: Define or directive not defined: \'`ZeroWord\'\n            wdata_o <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:37: Define or directive not defined: \'`ZeroWord\'\n            mem_addr_o <= `ZeroWord;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:38: Define or directive not defined: \'`WriteDisable\'\n            mem_we_o <= `WriteDisable;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:40: Define or directive not defined: \'`ZeroWord\'\n            mem_data_o <= `ZeroWord;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:41: Define or directive not defined: \'`ChipDisable\'\n            mem_ce_o <= `ChipDisable;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:46: Define or directive not defined: \'`ZeroWord\'\n            mem_addr_o <= `ZeroWord;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:47: Define or directive not defined: \'`WriteDisable\'\n            mem_we_o <= `WriteDisable;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:49: Define or directive not defined: \'`ZeroWord\'\n            mem_data_o <= `ZeroWord;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:50: Define or directive not defined: \'`ChipDisable\'\n            mem_ce_o <= `ChipDisable;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:52: Define or directive not defined: \'`EXE_LB_OP\'\n                `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:52: Define or directive not defined: \'`EXE_LH_OP\'\n                `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:52: Define or directive not defined: \'`EXE_LW_OP\'\n                `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:52: Define or directive not defined: \'`EXE_LBU_OP\'\n                `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin\n                                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:52: Define or directive not defined: \'`EXE_LHU_OP\'\n                `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin\n                                                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:54: Define or directive not defined: \'`ChipEnable\'\n                    mem_ce_o <= `ChipEnable;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:56: Define or directive not defined: \'`EXE_LB_OP\'\n                        `EXE_LB_OP: begin\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:75: Define or directive not defined: \'`ZeroWord\'\n                                    wdata_o <= `ZeroWord;\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:79: Define or directive not defined: \'`EXE_LH_OP\'\n                        `EXE_LH_OP: begin\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:90: Define or directive not defined: \'`ZeroWord\'\n                                    wdata_o <= `ZeroWord;\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:94: Define or directive not defined: \'`EXE_LW_OP\'\n                        `EXE_LW_OP: begin\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:98: Define or directive not defined: \'`EXE_LBU_OP\'\n                        `EXE_LBU_OP: begin\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:117: Define or directive not defined: \'`ZeroWord\'\n                                    wdata_o <= `ZeroWord;\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:121: Define or directive not defined: \'`EXE_LHU_OP\'\n                        `EXE_LHU_OP: begin\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:132: Define or directive not defined: \'`ZeroWord\'\n                                    wdata_o <= `ZeroWord;\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:138: Define or directive not defined: \'`EXE_SB_OP\'\n                `EXE_SB_OP, `EXE_SH_OP, `EXE_SW_OP: begin\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:138: Define or directive not defined: \'`EXE_SH_OP\'\n                `EXE_SB_OP, `EXE_SH_OP, `EXE_SW_OP: begin\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:138: Define or directive not defined: \'`EXE_SW_OP\'\n                `EXE_SB_OP, `EXE_SH_OP, `EXE_SW_OP: begin\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:140: Define or directive not defined: \'`WriteEnable\'\n                    mem_we_o <= `WriteEnable;\n                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:141: Define or directive not defined: \'`ChipEnable\'\n                    mem_ce_o <= `ChipEnable;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:143: Define or directive not defined: \'`EXE_SB_OP\'\n                        `EXE_SB_OP: begin\n                        ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mem(

    input wire                    rst,


    input wire[`RegAddrBus]       wd_i,
    input wire                    wreg_i,
    input wire[`RegBus]           wdata_i,

    input wire[`AluOpBus]         aluop_i,
    input wire[`RegBus]           mem_addr_i,
    input wire[`RegBus]           reg2_i,


    input wire[`RegBus]           mem_data_i,


    output reg[`RegBus]           mem_addr_o,
    output reg                    mem_we_o,
    output reg[3:0]               mem_sel_o,
    output reg[`RegBus]           mem_data_o,
    output reg                    mem_ce_o,


    output reg[`RegAddrBus]       wd_o,
    output reg                    wreg_o,
    output reg[`RegBus]           wdata_o
);

    always @ (*) begin
        if(rst == `RstEnable) begin
            wd_o <= `NOPRegAddr;
            wreg_o <= `WriteDisable;
            wdata_o <= `ZeroWord;
            mem_addr_o <= `ZeroWord;
            mem_we_o <= `WriteDisable;
            mem_sel_o <= 4'b0000;
            mem_data_o <= `ZeroWord;
            mem_ce_o <= `ChipDisable;
        end else begin
            wd_o <= wd_i;
            wreg_o <= wreg_i;
            wdata_o <= wdata_i;
            mem_addr_o <= `ZeroWord;
            mem_we_o <= `WriteDisable;
            mem_sel_o <= 4'b0000;
            mem_data_o <= `ZeroWord;
            mem_ce_o <= `ChipDisable;
            case (aluop_i)
                `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin
                    mem_addr_o <= mem_addr_i;
                    mem_ce_o <= `ChipEnable;
                    case (aluop_i)
                        `EXE_LB_OP: begin
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0001;
                                    wdata_o <= {{24{mem_data_i[7]}}, mem_data_i[7:0]};
                                end
                                2'b01: begin
                                    mem_sel_o <= 4'b0010;
                                    wdata_o <= {{24{mem_data_i[15]}}, mem_data_i[15:8]};
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b0100;
                                    wdata_o <= {{24{mem_data_i[23]}}, mem_data_i[23:16]};
                                end
                                2'b11: begin
                                    mem_sel_o <= 4'b1000;
                                    wdata_o <= {{24{mem_data_i[31]}}, mem_data_i[31:24]};
                                end
                                default: begin
                                    wdata_o <= `ZeroWord;
                                end
                            endcase
                        end
                        `EXE_LH_OP: begin
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0011;
                                    wdata_o <= {{16{mem_data_i[15]}}, mem_data_i[15:0]};
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b1100;
                                    wdata_o <= {{16{mem_data_i[31]}}, mem_data_i[31:16]};
                                end
                                default: begin
                                    wdata_o <= `ZeroWord;
                                end
                            endcase
                        end
                        `EXE_LW_OP: begin
                            mem_sel_o <= 4'b1111;
                            wdata_o <= mem_data_i;
                        end
                        `EXE_LBU_OP: begin
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0001;
                                    wdata_o <= {24'b0, mem_data_i[7:0]};
                                end
                                2'b01: begin
                                    mem_sel_o <= 4'b0010;
                                    wdata_o <= {24'b0, mem_data_i[15:8]};
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b0100;
                                    wdata_o <= {24'b0, mem_data_i[23:16]};
                                end
                                2'b11: begin
                                    mem_sel_o <= 4'b1000;
                                    wdata_o <= {24'b0, mem_data_i[31:24]};
                                end
                                default: begin
                                    wdata_o <= `ZeroWord;
                                end
                            endcase
                        end
                        `EXE_LHU_OP: begin
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0011;
                                    wdata_o <= {16'b0, mem_data_i[15:0]};
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b1100;
                                    wdata_o <= {16'b0, mem_data_i[31:16]};
                                end
                                default: begin
                                    wdata_o <= `ZeroWord;
                                end
                            endcase
                        end
                    endcase
                end
                `EXE_SB_OP, `EXE_SH_OP, `EXE_SW_OP: begin
                    mem_addr_o <= mem_addr_i;
                    mem_we_o <= `WriteEnable;
                    mem_ce_o <= `ChipEnable;
                    case (aluop_i)
                        `EXE_SB_OP: begin
                            mem_data_o <= {4{reg2_i[7:0]}};
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0001;
                                end
                                2'b01: begin
                                    mem_sel_o <= 4'b0010;
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b0100;
                                end
                                2'b11: begin
                                    mem_sel_o <= 4'b1000;
                                end
                                default: begin
                                    mem_sel_o <= 4'b0000;
                                end
                            endcase
                        end
                        `EXE_SH_OP: begin
                            mem_data_o <= {2{reg2_i[15:0]}};
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0011;
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b1100;
                                end
                                default: begin
                                    mem_sel_o <= 4'b0000;
                                end
                            endcase
                        end
                        `EXE_SW_OP: begin
                            mem_sel_o <= 4'b1111;
                            mem_data_o <= reg2_i;
                        end
                    endcase
                end
                default: begin
                end
            endcase
        end
    end


endmodule
module mem(

    input wire                    rst,


    input wire[`RegAddrBus]       wd_i,
    input wire                    wreg_i,
    input wire[`RegBus]           wdata_i,

    input wire[`AluOpBus]         aluop_i,
    input wire[`RegBus]           mem_addr_i,
    input wire[`RegBus]           reg2_i,


    input wire[`RegBus]           mem_data_i,


    output reg[`RegBus]           mem_addr_o,
    output reg                    mem_we_o,
    output reg[3:0]               mem_sel_o,
    output reg[`RegBus]           mem_data_o,
    output reg                    mem_ce_o,


    output reg[`RegAddrBus]       wd_o,
    output reg                    wreg_o,
    output reg[`RegBus]           wdata_o
);


    always @ (*) begin
        if(rst == `RstEnable) begin
            wd_o <= `NOPRegAddr;
            wreg_o <= `WriteDisable;
            wdata_o <= `ZeroWord;
            mem_addr_o <= `ZeroWord;
            mem_we_o <= `WriteDisable;
            mem_sel_o <= 4'b0000;
            mem_data_o <= `ZeroWord;
            mem_ce_o <= `ChipDisable;
        end else begin
            wd_o <= wd_i;
            wreg_o <= wreg_i;
            wdata_o <= wdata_i;
            mem_addr_o <= `ZeroWord;
            mem_we_o <= `WriteDisable;
            mem_sel_o <= 4'b0000;
            mem_data_o <= `ZeroWord;
            mem_ce_o <= `ChipDisable;
            case (aluop_i)
                `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin
                    mem_addr_o <= mem_addr_i;
                    mem_ce_o <= `ChipEnable;
                    case (aluop_i)
                        `EXE_LB_OP: begin
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0001;
                                    wdata_o <= {{24{mem_data_i[7]}}, mem_data_i[7:0]};
                                end
                                2'b01: begin
                                    mem_sel_o <= 4'b0010;
                                    wdata_o <= {{24{mem_data_i[15]}}, mem_data_i[15:8]};
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b0100;
                                    wdata_o <= {{24{mem_data_i[23]}}, mem_data_i[23:16]};
                                end
                                2'b11: begin
                                    mem_sel_o <= 4'b1000;
                                    wdata_o <= {{24{mem_data_i[31]}}, mem_data_i[31:24]};
                                end
                                default: begin
                                    wdata_o <= `ZeroWord;
                                end
                            endcase
                        end
                        `EXE_LH_OP: begin
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0011;
                                    wdata_o <= {{16{mem_data_i[15]}}, mem_data_i[15:0]};
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b1100;
                                    wdata_o <= {{16{mem_data_i[31]}}, mem_data_i[31:16]};
                                end
                                default: begin
                                    wdata_o <= `ZeroWord;
                                end
                            endcase
                        end
                        `EXE_LW_OP: begin
                            mem_sel_o <= 4'b1111;
                            wdata_o <= mem_data_i;
                        end
                        `EXE_LBU_OP: begin
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0001;
                                    wdata_o <= {24'b0, mem_data_i[7:0]};
                                end
                                2'b01: begin
                                    mem_sel_o <= 4'b0010;
                                    wdata_o <= {24'b0, mem_data_i[15:8]};
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b0100;
                                    wdata_o <= {24'b0, mem_data_i[23:16]};
                                end
                                2'b11: begin
                                    mem_sel_o <= 4'b1000;
                                    wdata_o <= {24'b0, mem_data_i[31:24]};
                                end
                                default: begin
                                    wdata_o <= `ZeroWord;
                                end
                            endcase
                        end
                        `EXE_LHU_OP: begin
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0011;
                                    wdata_o <= {16'b0, mem_data_i[15:0]};
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b1100;
                                    wdata_o <= {16'b0, mem_data_i[31:16]};
                                end
                                default: begin
                                    wdata_o <= `ZeroWord;
                                end
                            endcase
                        end
                    endcase
                end
                `EXE_SB_OP, `EXE_SH_OP, `EXE_SW_OP: begin
                    mem_addr_o <= mem_addr_i;
                    mem_we_o <= `WriteEnable;
                    mem_ce_o <= `ChipEnable;
                    case (aluop_i)
                        `EXE_SB_OP: begin
                            mem_data_o <= {4{reg2_i[7:0]}};
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0001;
                                end
                                2'b01: begin
                                    mem_sel_o <= 4'b0010;
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b0100;
                                end
                                2'b11: begin
                                    mem_sel_o <= 4'b1000;
                                end
                                default: begin
                                    mem_sel_o <= 4'b0000;
                                end
                            endcase
                        end
                        `EXE_SH_OP: begin
                            mem_data_o <= {2{reg2_i[15:0]}};
                            case (mem_addr_i[1:0])
                                2'b00: begin
                                    mem_sel_o <= 4'b0011;
                                end
                                2'b10: begin
                                    mem_sel_o <= 4'b1100;
                                end
                                default: begin
                                    mem_sel_o <= 4'b0000;
                                end
                            endcase
                        end
                        `EXE_SW_OP: begin
                            mem_sel_o <= 4'b1111;
                            mem_data_o <= reg2_i;
                        end
                    endcase
                end
                default: begin
                end
            endcase
        end
    end


endmodule