data/full_repos/permissive/175808891/verilog/prv32.v
 line:209: before: "("
1: b"%Error: data/full_repos/permissive/175808891/verilog/prv32.v:280: syntax error, unexpected type\n    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));\n                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:310: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    output reg [31:0] do\n                      ^~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:315: syntax error, unexpected '='\n        3'b100  : do = {24'b0,di[7:0]};\n                     ^\n%Error: Cannot continue\n"
module prv32_CPU(
	input clk, 
	input rst, 
	
	output 	[31:0] 	mAddr, 
	output 	[31:0] 	mDo, 
	input 	[31:0] 	mDi, 
	output  [1:0]   mSize,
	output 			mWr,

	output 	[4:0] 	rfRS1, 
	output 	[4:0] 	rfRS2, 
	output 	[4:0] 	rfRD, 
	input 	[31:0] 	rfD1, 
	input 	[31:0] 	rfD2,
	output	[31:0]	rfWD,
	output			rfWr

);


    wire            PCmux1_sel;
    wire            PCmux2_sel;
    wire            MAmux_sel;
    wire            Imux_sel;


    wire            Fmux_sel;
    wire [1:0]      WBmux_sel;
    wire            Cmux_sel;
    wire            SHmux_sel;
    wire            rf_Wr;
    wire            RAmux;
    wire            m_Wr;
    wire            store;
    wire            instr_w_rd;
    wire            instr_w_rs1;
    wire            instr_w_rs2;




	reg				ph;
    `sync_begin (ph)
        ph <= ~ph;
    `sync_end


    wire taken;
    wire [31:0] PCAdder;
     
    reg [31:0] PC;
    
    `sync_begin(PC)
	    if(ph) 
	        if(taken) 
	            PC <= (PCmux2_sel_1) ? ALUres : PCAdder;
	        else 
	            PC <= PC+4;
	`sync_end
	
	

	reg		[31:0]	IR;
	

	reg		[31:0]	PC_1;
	reg		[31:0]	R1_1, R2_1, I_1;
	reg		[4:0]	rd_1, rs1_1, rs2_1;
    reg     [4:0]   shamt_1;
    reg     [2:0]   func3_1;
    reg     [1:0]   ctrl_1;
    
    wire    [1:0]   ctrl;
    
    reg Imux_sel_1, Cmux_sel_1, SHmux_sel_1, RAmux_1, rf_Wr_1, m_Wr_1;
    reg PCmux2_sel_1;
    reg [1:0] WBmux_sel_1;
    reg [3:0] ALU_sel_1;
    reg store_1;
    reg instr_w_rd_1, instr_w_rs1_1, instr_w_rs2_1;
    

    
    assign rfRS1 = IR[`IR_rs1];
    assign rfRS2 = IR[`IR_rs2];

    wire [31:0] imm;
    wire [3:0] ALU_sel;
    
    prv32_ImmGen IG0    (
                            .IR(IR),
                            .Imm(imm)
                        );
                        
    prv32_ID ID0    (   .IR(IR),
                        .Imux_sel(Imux_sel),
                        .WBmux_sel(WBmux_sel),
                        .Cmux_sel(Cmux_sel),
                        .SHmux_sel(SHmux_sel),
                        .PCmux2_sel(PCmux2_sel),
                        .RAmux(RAmux),
                        .rfWr(rf_Wr),
                        .ALU_sel(ALU_sel), 
                        .ctrl(ctrl),
                        .mWr(m_Wr),
                        .store(store),
                        .instr_w_rd(instr_w_rd),
                        .instr_w_rs1(instr_w_rs1),
                        .instr_w_rs2(instr_w_rs2)

                    );
    
	`sync_begin(IR)
	    if(~ph) IR <= mDi;
	`sync_end
	
	`sync_begin(rd_1)
        if(ph) rd_1 <= IR[`IR_rd];		
	`sync_end
	
	`sync_begin(rs1_1)
        if(ph) rs1_1 <= IR[`IR_rs1];		
	`sync_end
	
	`sync_begin(rs2_1)
        if(ph) rs2_1 <= IR[`IR_rs2];		
	`sync_end
	
	`sync_begin(func3_1)
        if(ph) func3_1 <= IR[`IR_funct3];		
	`sync_end
	
	`sync_begin(shamt_1)
        if(ph) shamt_1 <= SHmux_sel ? IR[`IR_shamt] : rfD2[4:0];		
	`sync_end

	`sync_begin(ALU_sel_1)
	    if(ph)  ALU_sel_1 <= ALU_sel;
	`sync_end
	

	`sync_begin(Imux_sel_1)
	    if(ph) Imux_sel_1 <= Imux_sel;
	`sync_end
	
	`sync_begin(WBmux_sel_1)
	    if(ph)  WBmux_sel_1 <= WBmux_sel;
	`sync_end
	
	`sync_begin(Cmux_sel_1)
	    if(ph)  Cmux_sel_1 <= Cmux_sel;
	`sync_end
	
	`sync_begin(SHmux_sel_1)
	    if(ph)  SHmux_sel_1 <= SHmux_sel;
	`sync_end
	
	`sync_begin(RAmux_1)
	    if(ph)  RAmux_1 <= RAmux;
	`sync_end
	
	`sync_begin(store_1)
	    if(ph)  store_1 <= store;
	`sync_end
	
	`sync_begin(instr_w_rd_1)
	    if(ph)  instr_w_rd_1 <= instr_w_rd;
	`sync_end
	
	`sync_begin(instr_w_rs1_1)
	    if(ph)  instr_w_rs1_1 <= instr_w_rs1;
	`sync_end
	
	`sync_begin(instr_w_rs2_1)
	    if(ph)  instr_w_rs2_1 <= instr_w_rs2;
	`sync_end
	
	`sync_begin(PCmux2_sel_1)
	    if(ph)  PCmux2_sel_1 <= PCmux2_sel;
	`sync_end
	
	
	`sync_begin(rf_Wr_1)
	    if(ph)  rf_Wr_1 <= (rf_Wr & ~taken);
	`sync_end
    
    `sync_begin(m_Wr_1)
	    if(ph)  m_Wr_1 <= (m_Wr & ~taken);

	`sync_end
	



	
    `sync_begin(ctrl_1)
	    if(ph)  ctrl_1 <= (ctrl & {~taken, ~taken});
	`sync_end	
	

	
	`sync_begin(R1_1)
	    if(ph) R1_1 <= rfD1;
	`sync_end
	
    `sync_begin(R2_1)
	    if(ph) R2_1 <= rfD2;
	`sync_end
	
	`sync_begin(PC_1)
	    if(ph) PC_1 <= PC;
	`sync_end
	
	`sync_begin(I_1)
	    if(ph) I_1 <= imm;
	`sync_end
	
	


    wire [31:0] FWDmux1, FWDmux2, Imux;
    wire [31:0] ALUres;
    wire FWDmux1_sel, FWDmux2_sel;

    wire sf, vf, zf, cf;
    

    reg [31:0] R_2, MD_2;
    reg [1:0] WBmux_sel_2;
    reg [4:0] rd_2;
    reg rf_Wr_2;
    reg [31:0] RA_2;
    reg instr_w_rd_2;


    wire [31:0] mData;
    prv32_memData MD0 (
        .func3(func3_1),
        .di(mDi),
        .do(mData)
    );
    
    assign Imux = Imux_sel_1 ? I_1 : R2_1;
    

    prv32_ALU ALU0(.a(FWDmux1), .b(FWDmux2), .shamt(shamt_1),.r(ALUres), .cf(cf), .zf(zf), .vf(vf), .sf(sf), .alufn(ALU_sel_1));  
    

    assign PCAdder = PC_1 + I_1;
    

    prv32_HazardsUnit HZ0 ( .rs1(rs1_1), 
                            .rs2(rs2_1), 
                            .rd(rd_2), 
                            .rd_valid(instr_w_rd_2), 
                            .rs1_valid(instr_w_rs1_1), 
                            .rs2_valid(instr_w_rs2_1), 
                            .fwd1(FWDmux1_sel), 
                            .fwd2(FWDmux2_sel) );
    
    assign FWDmux1 = (FWDmux1_sel) ? WBmux : R1_1;
    assign FWDmux2 = (FWDmux2_sel & ~store_1) ? WBmux : Imux;
    

    prv32_ControlHazardUnit BU0(.cf(cf), .zf(zf), .vf(vf), .sf(sf), .func3(func3_1), .ctrl(ctrl_1), .taken(taken));
    
    `sync_begin(R_2)
	    if(ph) R_2 <= ALUres;
	`sync_end
	
	`sync_begin(MD_2)
	    if(ph) MD_2 <= mData;
	`sync_end
	

	`sync_begin(rd_2)
        if(ph) rd_2 <= rd_1;		
	`sync_end
	
	`sync_begin(instr_w_rd_2)
        if(ph) instr_w_rd_2 <= instr_w_rd_1;		
	`sync_end
	
	`sync_begin(rf_Wr_2)
        if(ph) rf_Wr_2 <= rf_Wr_1;		
	`sync_end
	
	`sync_begin(WBmux_sel_2)
        if(ph) WBmux_sel_2 <= WBmux_sel_1;		
	`sync_end
	
	`sync_begin(RA_2)
        if(ph) RA_2 <= RAmux_1 ? PCAdder : (PC_1+32'd4);		
	`sync_end
	

    wire [31:0] WBmux = (WBmux_sel_2==2'b11) ? MD_2 : 
                        (WBmux_sel_2==2'b01) ? RA_2 : R_2;
    assign rfWD =  WBmux;
    assign rfRD = rd_2;
    assign rfWr = rf_Wr_2 & ~ph;
    
    
    

	assign mAddr = ph ? ALUres : PC;
	assign mSize = ph ? func3_1[1:0] : 2'b10;
	assign mWr = m_Wr_1 & ph;
	assign mDo = (FWDmux2_sel & store_1) ? WBmux : R2_1;
	
endmodule
module prv32_CPU(
	input clk, 
	input rst, 
	
	output 	[31:0] 	mAddr, 
	output 	[31:0] 	mDo, 
	input 	[31:0] 	mDi, 
	output  [1:0]   mSize,
	output 			mWr,

	output 	[4:0] 	rfRS1, 
	output 	[4:0] 	rfRS2, 
	output 	[4:0] 	rfRD, 
	input 	[31:0] 	rfD1, 
	input 	[31:0] 	rfD2,
	output	[31:0]	rfWD,
	output			rfWr

);



    wire            PCmux1_sel;
    wire            PCmux2_sel;
    wire            MAmux_sel;
    wire            Imux_sel;


    wire            Fmux_sel;
    wire [1:0]      WBmux_sel;
    wire            Cmux_sel;
    wire            SHmux_sel;
    wire            rf_Wr;
    wire            RAmux;
    wire            m_Wr;
    wire            store;
    wire            instr_w_rd;
    wire            instr_w_rs1;
    wire            instr_w_rs2;




	reg				ph;
    `sync_begin (ph)
        ph <= ~ph;
    `sync_end


    wire taken;
    wire [31:0] PCAdder;
     
    reg [31:0] PC;
    
    `sync_begin(PC)
	    if(ph) 
	        if(taken) 
	            PC <= (PCmux2_sel_1) ? ALUres : PCAdder;
	        else 
	            PC <= PC+4;
	`sync_end
	
	

	reg		[31:0]	IR;
	

	reg		[31:0]	PC_1;
	reg		[31:0]	R1_1, R2_1, I_1;
	reg		[4:0]	rd_1, rs1_1, rs2_1;
    reg     [4:0]   shamt_1;
    reg     [2:0]   func3_1;
    reg     [1:0]   ctrl_1;
    
    wire    [1:0]   ctrl;
    
    reg Imux_sel_1, Cmux_sel_1, SHmux_sel_1, RAmux_1, rf_Wr_1, m_Wr_1;
    reg PCmux2_sel_1;
    reg [1:0] WBmux_sel_1;
    reg [3:0] ALU_sel_1;
    reg store_1;
    reg instr_w_rd_1, instr_w_rs1_1, instr_w_rs2_1;
    

    
    assign rfRS1 = IR[`IR_rs1];
    assign rfRS2 = IR[`IR_rs2];

    wire [31:0] imm;
    wire [3:0] ALU_sel;
    
    prv32_ImmGen IG0    (
                            .IR(IR),
                            .Imm(imm)
                        );
                        
    prv32_ID ID0    (   .IR(IR),
                        .Imux_sel(Imux_sel),
                        .WBmux_sel(WBmux_sel),
                        .Cmux_sel(Cmux_sel),
                        .SHmux_sel(SHmux_sel),
                        .PCmux2_sel(PCmux2_sel),
                        .RAmux(RAmux),
                        .rfWr(rf_Wr),
                        .ALU_sel(ALU_sel), 
                        .ctrl(ctrl),
                        .mWr(m_Wr),
                        .store(store),
                        .instr_w_rd(instr_w_rd),
                        .instr_w_rs1(instr_w_rs1),
                        .instr_w_rs2(instr_w_rs2)

                    );
    
	`sync_begin(IR)
	    if(~ph) IR <= mDi;
	`sync_end
	
	`sync_begin(rd_1)
        if(ph) rd_1 <= IR[`IR_rd];		
	`sync_end
	
	`sync_begin(rs1_1)
        if(ph) rs1_1 <= IR[`IR_rs1];		
	`sync_end
	
	`sync_begin(rs2_1)
        if(ph) rs2_1 <= IR[`IR_rs2];		
	`sync_end
	
	`sync_begin(func3_1)
        if(ph) func3_1 <= IR[`IR_funct3];		
	`sync_end
	
	`sync_begin(shamt_1)
        if(ph) shamt_1 <= SHmux_sel ? IR[`IR_shamt] : rfD2[4:0];		
	`sync_end

	`sync_begin(ALU_sel_1)
	    if(ph)  ALU_sel_1 <= ALU_sel;
	`sync_end
	

	`sync_begin(Imux_sel_1)
	    if(ph) Imux_sel_1 <= Imux_sel;
	`sync_end
	
	`sync_begin(WBmux_sel_1)
	    if(ph)  WBmux_sel_1 <= WBmux_sel;
	`sync_end
	
	`sync_begin(Cmux_sel_1)
	    if(ph)  Cmux_sel_1 <= Cmux_sel;
	`sync_end
	
	`sync_begin(SHmux_sel_1)
	    if(ph)  SHmux_sel_1 <= SHmux_sel;
	`sync_end
	
	`sync_begin(RAmux_1)
	    if(ph)  RAmux_1 <= RAmux;
	`sync_end
	
	`sync_begin(store_1)
	    if(ph)  store_1 <= store;
	`sync_end
	
	`sync_begin(instr_w_rd_1)
	    if(ph)  instr_w_rd_1 <= instr_w_rd;
	`sync_end
	
	`sync_begin(instr_w_rs1_1)
	    if(ph)  instr_w_rs1_1 <= instr_w_rs1;
	`sync_end
	
	`sync_begin(instr_w_rs2_1)
	    if(ph)  instr_w_rs2_1 <= instr_w_rs2;
	`sync_end
	
	`sync_begin(PCmux2_sel_1)
	    if(ph)  PCmux2_sel_1 <= PCmux2_sel;
	`sync_end
	
	
	`sync_begin(rf_Wr_1)
	    if(ph)  rf_Wr_1 <= (rf_Wr & ~taken);
	`sync_end
    
    `sync_begin(m_Wr_1)
	    if(ph)  m_Wr_1 <= (m_Wr & ~taken);

	`sync_end
	



	
    `sync_begin(ctrl_1)
	    if(ph)  ctrl_1 <= (ctrl & {~taken, ~taken});
	`sync_end	
	

	
	`sync_begin(R1_1)
	    if(ph) R1_1 <= rfD1;
	`sync_end
	
    `sync_begin(R2_1)
	    if(ph) R2_1 <= rfD2;
	`sync_end
	
	`sync_begin(PC_1)
	    if(ph) PC_1 <= PC;
	`sync_end
	
	`sync_begin(I_1)
	    if(ph) I_1 <= imm;
	`sync_end
	
	


    wire [31:0] FWDmux1, FWDmux2, Imux;
    wire [31:0] ALUres;
    wire FWDmux1_sel, FWDmux2_sel;

    wire sf, vf, zf, cf;
    

    reg [31:0] R_2, MD_2;
    reg [1:0] WBmux_sel_2;
    reg [4:0] rd_2;
    reg rf_Wr_2;
    reg [31:0] RA_2;
    reg instr_w_rd_2;


    wire [31:0] mData;
    prv32_memData MD0 (
        .func3(func3_1),
        .di(mDi),
        .do(mData)
    );
    
    assign Imux = Imux_sel_1 ? I_1 : R2_1;
    

    prv32_ALU ALU0(.a(FWDmux1), .b(FWDmux2), .shamt(shamt_1),.r(ALUres), .cf(cf), .zf(zf), .vf(vf), .sf(sf), .alufn(ALU_sel_1));  
    

    assign PCAdder = PC_1 + I_1;
    

    prv32_HazardsUnit HZ0 ( .rs1(rs1_1), 
                            .rs2(rs2_1), 
                            .rd(rd_2), 
                            .rd_valid(instr_w_rd_2), 
                            .rs1_valid(instr_w_rs1_1), 
                            .rs2_valid(instr_w_rs2_1), 
                            .fwd1(FWDmux1_sel), 
                            .fwd2(FWDmux2_sel) );
    
    assign FWDmux1 = (FWDmux1_sel) ? WBmux : R1_1;
    assign FWDmux2 = (FWDmux2_sel & ~store_1) ? WBmux : Imux;
    

    prv32_ControlHazardUnit BU0(.cf(cf), .zf(zf), .vf(vf), .sf(sf), .func3(func3_1), .ctrl(ctrl_1), .taken(taken));
    
    `sync_begin(R_2)
	    if(ph) R_2 <= ALUres;
	`sync_end
	
	`sync_begin(MD_2)
	    if(ph) MD_2 <= mData;
	`sync_end
	

	`sync_begin(rd_2)
        if(ph) rd_2 <= rd_1;		
	`sync_end
	
	`sync_begin(instr_w_rd_2)
        if(ph) instr_w_rd_2 <= instr_w_rd_1;		
	`sync_end
	
	`sync_begin(rf_Wr_2)
        if(ph) rf_Wr_2 <= rf_Wr_1;		
	`sync_end
	
	`sync_begin(WBmux_sel_2)
        if(ph) WBmux_sel_2 <= WBmux_sel_1;		
	`sync_end
	
	`sync_begin(RA_2)
        if(ph) RA_2 <= RAmux_1 ? PCAdder : (PC_1+32'd4);		
	`sync_end
	

    wire [31:0] WBmux = (WBmux_sel_2==2'b11) ? MD_2 : 
                        (WBmux_sel_2==2'b01) ? RA_2 : R_2;
    assign rfWD =  WBmux;
    assign rfRD = rd_2;
    assign rfWr = rf_Wr_2 & ~ph;
    
    
    

	assign mAddr = ph ? ALUres : PC;
	assign mSize = ph ? func3_1[1:0] : 2'b10;
	assign mWr = m_Wr_1 & ph;
	assign mDo = (FWDmux2_sel & store_1) ? WBmux : R2_1;
	
endmodule