data/full_repos/permissive/135701568/pc.v
data/verilator_xmls/3d1639fc-c32b-4f0b-8c6d-908d33557f2f.xml
module pc(clk, rst, loadEn, in, out);
  input[11:0] in;
  output reg [11:0] out;
  input clk, rst, loadEn;
  always @(posedge clk, posedge rst) begin
    if(rst) begin
      out <= 12'b0;
    end
    else begin
      if(loadEn) begin
        out <= in;
      end
    end
  end
endmodule
module pc(clk, rst, loadEn, in, out);

  input[11:0] in;
  output reg [11:0] out;
  input clk, rst, loadEn;
  always @(posedge clk, posedge rst) begin
    if(rst) begin
      out <= 12'b0;
    end
    else begin
      if(loadEn) begin
        out <= in;
      end
    end
  end
endmodule