data/full_repos/permissive/157667710/benchmark/AES-T1700/AES-T1700/src/TjIn/AES_tb.v
 line:64: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1700/AES-T1700/src/TjIn/AES_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1700/AES-T1700/src/TjIn/AES_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #15\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1700/AES-T1700/src/TjIn/AES_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #300 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1700/AES-T1700/src/TjIn/AES_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n   always #10.015 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/157667710/benchmark/AES-T1700/AES-T1700/src/TjIn/AES_tb.v:38: Cannot find file containing module: \'top\'\n top uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/157667710/benchmark/AES-T1700/AES-T1700/src/TjIn,data/full_repos/permissive/157667710/top\n             data/full_repos/permissive/157667710/benchmark/AES-T1700/AES-T1700/src/TjIn,data/full_repos/permissive/157667710/top.v\n             data/full_repos/permissive/157667710/benchmark/AES-T1700/AES-T1700/src/TjIn,data/full_repos/permissive/157667710/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module AES_tb;


	reg clk;
	reg rst;
	reg [127:0] state;
	reg [127:0] key;


	wire [127:0] out;
	wire Antena;


	top uut (
		.clk(clk), 
		.rst(rst), 
		.state(state), 
		.key(key), 
		.out(out), 
		.Antena(Antena)
	);

	initial begin

		clk = 0;
		rst = 0;
		state = 0;
		key = 0;


		#5;
      rst = 1;     
		state = 128'hFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF;

      key   = 128'haaaaaaaa_aaaaaaaa_aaaaaaaa_aaaaaaaa;

		#15
		rst = 0;

		#300 $finish;
	end
	
   always #10.015 clk = ~clk;
	
endmodule
module AES_tb;



	reg clk;
	reg rst;
	reg [127:0] state;
	reg [127:0] key;


	wire [127:0] out;
	wire Antena;


	top uut (
		.clk(clk), 
		.rst(rst), 
		.state(state), 
		.key(key), 
		.out(out), 
		.Antena(Antena)
	);

	initial begin

		clk = 0;
		rst = 0;
		state = 0;
		key = 0;


		#5;
      rst = 1;     
		state = 128'hFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF;

      key   = 128'haaaaaaaa_aaaaaaaa_aaaaaaaa_aaaaaaaa;

		#15
		rst = 0;

		#300 $finish;
	end
	
   always #10.015 clk = ~clk;
	
endmodule