data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/xilinx_lpddr/xilinx_ddr2_if.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/xilinx_lpddr/xilinx_ddr2_if.v:142: Cannot find include file: orpsoc-defines.v\n`include "orpsoc-defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/xilinx_lpddr,data/full_repos/permissive/19905110/orpsoc-defines.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/xilinx_lpddr,data/full_repos/permissive/19905110/orpsoc-defines.v.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/xilinx_lpddr,data/full_repos/permissive/19905110/orpsoc-defines.v.sv\n             orpsoc-defines.v\n             orpsoc-defines.v.v\n             orpsoc-defines.v.sv\n             obj_dir/orpsoc-defines.v\n             obj_dir/orpsoc-defines.v.v\n             obj_dir/orpsoc-defines.v.sv\n%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/xilinx_lpddr/xilinx_ddr2_if.v:143: Cannot find include file: xilinx_ddr2_params.v\n`include "xilinx_ddr2_params.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module xilinx_ddr2_if ( 
    input [31:0]       wb0_adr_i,
    input 	           wb0_stb_i,
    input 	           wb0_cyc_i,
    input  [2:0]       wb0_cti_i,
    input  [1:0]       wb0_bte_i,
    input 	           wb0_we_i,
    input  [3:0]       wb0_sel_i,
    input  [31:0]      wb0_dat_i,
    output [31:0]      wb0_dat_o,
    output             wb0_ack_o,

    input [31:0]       wb1_adr_i,
    input              wb1_stb_i,
    input              wb1_cyc_i,
    input  [2:0]       wb1_cti_i,
    input  [1:0]       wb1_bte_i,
    input              wb1_we_i,
    input  [3:0]       wb1_sel_i,
    input  [31:0]      wb1_dat_i,
    output [31:0]      wb1_dat_o,
    output             wb1_ack_o,

    input [31:0]       wb2_adr_i,
    input              wb2_stb_i,
    input              wb2_cyc_i,
    input  [2:0]       wb2_cti_i,
    input  [1:0]       wb2_bte_i,
    input              wb2_we_i,
    input  [3:0]       wb2_sel_i,
    input  [31:0]      wb2_dat_i,
    output [31:0]      wb2_dat_o,
    output             wb2_ack_o,

    input [31:0]       wb3_adr_i,
    input              wb3_stb_i,
    input              wb3_cyc_i,
    input  [2:0]       wb3_cti_i,
    input  [1:0]       wb3_bte_i,
    input              wb3_we_i,
    input  [3:0]       wb3_sel_i,
    input  [31:0]      wb3_dat_i,
    output [31:0]      wb3_dat_o,
    output             wb3_ack_o,

    input [31:0]       wb4_adr_i,
    input              wb4_stb_i,
    input              wb4_cyc_i,
    input  [2:0]       wb4_cti_i,
    input  [1:0]       wb4_bte_i,
    input              wb4_we_i,
    input  [3:0]       wb4_sel_i,
    input  [31:0]      wb4_dat_i,
    output [31:0]      wb4_dat_o,
    output             wb4_ack_o,

   input [31:0]       wb5_adr_i,
   input              wb5_stb_i,
   input              wb5_cyc_i,
   input  [2:0]       wb5_cti_i,
   input  [1:0]       wb5_bte_i,
   input              wb5_we_i,
   input  [3:0]       wb5_sel_i,
   input  [31:0]      wb5_dat_i,
   output [31:0]      wb5_dat_o,
   output             wb5_ack_o,
                                       

    output [12:0]      ddr2_a,
    output [2:0]       ddr2_ba,
    output 	           ddr2_ras_n,
    output 	           ddr2_cas_n,
    output 	           ddr2_we_n,
    output             ddr2_rzq,
    output             ddr2_zio,
    output             ddr2_odt,
    output             ddr2_cke,
    output             ddr2_dm,
    output             ddr2_udm,

    inout [15:0]       ddr2_dq,		  
    inout              ddr2_dqs,
    inout              ddr2_dqs_n,
    inout              ddr2_udqs,
    inout              ddr2_udqs_n,
    output             ddr2_ck,
    output             ddr2_ck_n,

    input 	           ddr2_if_clk,
    input 	           ddr2_if_rst,
    input 	           wb_clk,
    input 	           wb_rst
,
   output [31:0] 		     ddr2_trace_data0_o,
   output [31:0] 		     ddr2_trace_data1_o,
   output [31:0] 		     ddr2_trace_data2_o,
   output [31:0] 		     ddr2_trace_data3_o,
   output [31:0] 		     ddr2_trace_data4_o,
   output [31:0] 		     ddr2_trace_data5_o
);
   
`include "orpsoc-defines.v"
`include "xilinx_ddr2_params.v"
    parameter NUM_USERPORTS = 6;
    parameter P0_BURST_ADDR_WIDTH = 4;
    parameter P0_BURST_ADDR_ALIGN = P0_BURST_ADDR_WIDTH + 2;
	 parameter P0_WB_BURSTING      = "TRUE";
	 
    parameter P1_BURST_ADDR_WIDTH = 5;
    parameter P1_BURST_ADDR_ALIGN = P1_BURST_ADDR_WIDTH + 2;
	 parameter P1_WB_BURSTING      = "TRUE";
  
    parameter P2_BURST_ADDR_WIDTH = 6;
    parameter P2_BURST_ADDR_ALIGN = P2_BURST_ADDR_WIDTH + 2;
	 parameter P2_WB_BURSTING      = "TRUE";
  
    parameter P3_BURST_ADDR_WIDTH = 4;
    parameter P3_BURST_ADDR_ALIGN = P3_BURST_ADDR_WIDTH + 2;
	 parameter P3_WB_BURSTING      = "TRUE";

    parameter P4_BURST_ADDR_WIDTH = 4;
    parameter P4_BURST_ADDR_ALIGN = P4_BURST_ADDR_WIDTH + 2;
	 parameter P4_WB_BURSTING      = "TRUE";
   parameter P5_BURST_ADDR_WIDTH = 4;
       parameter P5_BURST_ADDR_ALIGN = P5_BURST_ADDR_WIDTH + 2;
        parameter P5_WB_BURSTING      = "TRUE";
       
       

    wire 	              ddr2_clk;
    wire 	              ddr2_rst;
 
    wire  [31:0]        wb_px_adr_i[NUM_USERPORTS-1:0];
    wire 	              wb_px_stb_i[NUM_USERPORTS-1:0];
    wire 	              wb_px_cyc_i[NUM_USERPORTS-1:0];
    wire  [2:0]         wb_px_cti_i[NUM_USERPORTS-1:0];
    wire  [1:0]         wb_px_bte_i[NUM_USERPORTS-1:0];
    wire 	              wb_px_we_i[NUM_USERPORTS-1:0];
    wire  [3:0]         wb_px_sel_i[NUM_USERPORTS-1:0];
    wire  [31:0]        wb_px_dat_i[NUM_USERPORTS-1:0];
    wire  [31:0]        wb_px_dat_o[NUM_USERPORTS-1:0];
    wire                wb_px_ack_o[NUM_USERPORTS-1:0];
 
    wire 	              wb_px_req[NUM_USERPORTS-1:0];
    reg 		            wb_px_req_r[NUM_USERPORTS-1:0];
    wire 	              wb_px_req_new[NUM_USERPORTS-1:0];
    wire                wb_px_wr_req[NUM_USERPORTS-1:0];
   

    wire                ddr2_px_cmd_full[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_full[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_en[NUM_USERPORTS-1:0];
    wire                ddr2_px_cmd_en[NUM_USERPORTS-1:0];
    wire [29:0]         ddr2_px_cmd_byte_addr[NUM_USERPORTS-1:0];
    wire [2:0]          ddr2_px_cmd_instr[NUM_USERPORTS-1:0];
    wire [31:0]         ddr2_px_wr_data[NUM_USERPORTS-1:0];
    wire [3:0]          ddr2_px_wr_mask[NUM_USERPORTS-1:0];
    wire [31:0]         ddr2_px_rd_data[NUM_USERPORTS-1:0];
    wire [5:0]          ddr2_px_cmd_bl[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_en[NUM_USERPORTS-1:0];
    wire                ddr2_px_cmd_empty[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_empty[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_count[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_underrun[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_error[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_full[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_empty[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_count[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_overflow[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_error[NUM_USERPORTS-1:0];
    wire 	              ddr2_calib_done;
    reg [1:0]           ddr2_calib_done_r;

    assign wb_px_adr_i[0] = wb0_adr_i;
    assign wb_px_stb_i[0] = wb0_stb_i;
    assign wb_px_cyc_i[0] = wb0_cyc_i;
    assign wb_px_cti_i[0] = wb0_cti_i;
    assign wb_px_bte_i[0] = wb0_bte_i;
    assign wb_px_we_i[0]  = wb0_we_i;
    assign wb_px_sel_i[0] = wb0_sel_i;
    assign wb_px_dat_i[0] = wb0_dat_i;
    assign wb0_dat_o = wb_px_dat_o[0];
    assign wb0_ack_o = wb_px_ack_o[0];

    assign wb_px_adr_i[1] = wb1_adr_i;
    assign wb_px_stb_i[1] = wb1_stb_i;
    assign wb_px_cyc_i[1] = wb1_cyc_i;
    assign wb_px_cti_i[1] = wb1_cti_i;
    assign wb_px_bte_i[1] = wb1_bte_i;
    assign wb_px_we_i[1]  = wb1_we_i;
    assign wb_px_sel_i[1] = wb1_sel_i;
    assign wb_px_dat_i[1] = wb1_dat_i;
    assign wb1_dat_o = wb_px_dat_o[1];
    assign wb1_ack_o = wb_px_ack_o[1];

    assign wb_px_adr_i[2] = wb2_adr_i;
    assign wb_px_stb_i[2] = wb2_stb_i;
    assign wb_px_cyc_i[2] = wb2_cyc_i;
    assign wb_px_cti_i[2] = wb2_cti_i;
    assign wb_px_bte_i[2] = wb2_bte_i;
    assign wb_px_we_i[2]  = wb2_we_i;
    assign wb_px_sel_i[2] = wb2_sel_i;
    assign wb_px_dat_i[2] = wb2_dat_i;
    assign wb2_dat_o = wb_px_dat_o[2];
    assign wb2_ack_o = wb_px_ack_o[2];

    assign wb_px_adr_i[3] = wb3_adr_i;
    assign wb_px_stb_i[3] = wb3_stb_i;
    assign wb_px_cyc_i[3] = wb3_cyc_i;
    assign wb_px_cti_i[3] = wb3_cti_i;
    assign wb_px_bte_i[3] = wb3_bte_i;
    assign wb_px_we_i[3]  = wb3_we_i;
    assign wb_px_sel_i[3] = wb3_sel_i;
    assign wb_px_dat_i[3] = wb3_dat_i;
    assign wb3_dat_o = wb_px_dat_o[3];
    assign wb3_ack_o = wb_px_ack_o[3];

    assign wb_px_adr_i[4] = wb4_adr_i;
    assign wb_px_stb_i[4] = wb4_stb_i;
    assign wb_px_cyc_i[4] = wb4_cyc_i;
    assign wb_px_cti_i[4] = wb4_cti_i;
    assign wb_px_bte_i[4] = wb4_bte_i;
    assign wb_px_we_i[4]  = wb4_we_i;
    assign wb_px_sel_i[4] = wb4_sel_i;
    assign wb_px_dat_i[4] = wb4_dat_i;
    assign wb4_dat_o = wb_px_dat_o[4];
    assign wb4_ack_o = wb_px_ack_o[4];
    
     assign wb_px_adr_i[5] = wb5_adr_i;
     assign wb_px_stb_i[5] = wb5_stb_i;
     assign wb_px_cyc_i[5] = wb5_cyc_i;
     assign wb_px_cti_i[5] = wb5_cti_i;
     assign wb_px_bte_i[5] = wb5_bte_i;
     assign wb_px_we_i[5]  = wb5_we_i;
     assign wb_px_sel_i[5] = wb5_sel_i;
     assign wb_px_dat_i[5] = wb5_dat_i;
     assign wb5_dat_o = wb_px_dat_o[5];
     assign wb5_ack_o = wb_px_ack_o[5];
                                         



    wire        px_addr_dirty[NUM_USERPORTS-1:0];
    wire [31:0] px_cache_addr[NUM_USERPORTS-1:0];



    assign px_addr_dirty[0] = ((wb0_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) |
                              ((wb1_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) | 
                              ((wb2_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                              ((wb3_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                              ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                              ((wb5_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);
                           
    assign px_addr_dirty[1] = ((wb0_adr_i[31:P1_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P1_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) | 
                              ((wb1_adr_i[31:P1_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P1_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) | 
                              ((wb2_adr_i[31:P1_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P1_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                              ((wb3_adr_i[31:P1_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P1_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                              ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                              ((wb5_adr_i[31:P1_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P1_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);
                           
    assign px_addr_dirty[2] = ((wb0_adr_i[31:P2_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P2_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) | 
                              ((wb1_adr_i[31:P2_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P2_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) |
                              ((wb2_adr_i[31:P2_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P2_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                              ((wb3_adr_i[31:P2_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P2_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                              ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                              ((wb5_adr_i[31:P2_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P2_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);
    
    assign px_addr_dirty[3] = ((wb0_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) | 
                              ((wb1_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) |
                              ((wb2_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                              ((wb3_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                              ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                              ((wb5_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);

    assign px_addr_dirty[4] = ((wb0_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) | 
                              ((wb1_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) |
                              ((wb2_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                              ((wb3_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                              ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                              ((wb5_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);

   assign px_addr_dirty[5] = ((wb0_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) |
                             ((wb1_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) |
                             ((wb2_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                             ((wb3_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                             ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                             ((wb5_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);
                                                                                                                           
                                                                                                                           
   always @ (posedge wb_clk)
     ddr2_calib_done_r[1:0] <= {ddr2_calib_done, ddr2_calib_done_r[1]};

   assign ddr2_trace_data3_o = wb_px_adr_i[1];
   assign ddr2_trace_data4_o = ddr2_px_rd_data[1];
   assign ddr2_trace_data5_o = {
				ddr2_px_cmd_full[1],
				ddr2_px_wr_full[1],
				ddr2_px_wr_en[1],
				ddr2_px_cmd_en[1],
				ddr2_px_cmd_instr[1],
				ddr2_px_rd_en[1],
				ddr2_px_cmd_empty[1],
				ddr2_px_wr_empty[1],
				ddr2_px_rd_full[1],
				ddr2_px_rd_empty[1],
				ddr2_px_rd_error[1],
				ddr2_px_wr_error[1],
				18'h0
				};

      assign wb_px_req[0]     = wb_px_stb_i[0] & wb_px_cyc_i[0] & ddr2_calib_done_r[0]; 
      assign wb_px_req_new[0] = wb_px_req[0] & !wb_px_req_r[0];
      assign wb_px_wr_req[0]  = wb_px_req_new[0] & wb_px_we_i[0];

      always @(posedge wb_clk)
        wb_px_req_r[0] <= wb_px_req[0] & !wb_px_ack_o[0];

       wb_to_userport #(
        .BURST_ADDR_WIDTH(P0_BURST_ADDR_WIDTH),
        .BURST_ADDR_ALIGN(P0_BURST_ADDR_ALIGN),
        .WB_BURSTING(P0_WB_BURSTING)
       )
       wb2up0 (
        .wb_clk                     (wb_clk),
        .wb_rst                     (wb_rst),
        .wb_adr_i                   (wb_px_adr_i[0]),
        .wb_stb_i                   (wb_px_stb_i[0]),
        .wb_cyc_i                   (wb_px_cyc_i[0]),
        .wb_cti_i                   (wb_px_cti_i[0]),
        .wb_bte_i                   (wb_px_bte_i[0]),
        .wb_we_i                    (wb_px_we_i[0]),
        .wb_sel_i                   (wb_px_sel_i[0]),
        .wb_dat_i                   (wb_px_dat_i[0]),
        .wb_dat_o                   (wb_px_dat_o[0]),
        .wb_ack_o                   (wb_px_ack_o[0]),

        .addr_dirty                 (px_addr_dirty[0]),
        .cache_addr                 (px_cache_addr[0]),

        .ddr2_px_cmd_full           (ddr2_px_cmd_full[0]),
        .ddr2_px_wr_full            (ddr2_px_wr_full[0]),
        .ddr2_px_wr_en              (ddr2_px_wr_en[0]),
        .ddr2_px_cmd_en             (ddr2_px_cmd_en[0]),
        .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[0]),
        .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[0]),
        .ddr2_px_wr_data            (ddr2_px_wr_data[0]),
        .ddr2_px_wr_mask            (ddr2_px_wr_mask[0]),
        .ddr2_px_rd_data            (ddr2_px_rd_data[0]),
        .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[0]),
        .ddr2_px_rd_en              (ddr2_px_rd_en[0]),
        .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[0]),
        .ddr2_px_wr_empty           (ddr2_px_wr_empty[0]),
        .ddr2_px_rd_full            (ddr2_px_rd_full[0]),
        .ddr2_px_rd_empty           (ddr2_px_rd_empty[0]),
        .ddr2_calib_done            (ddr2_calib_done)
        );

      assign wb_px_req[1]     = wb_px_stb_i[1] & wb_px_cyc_i[1] & ddr2_calib_done_r[0]; 
      assign wb_px_req_new[1] = wb_px_req[1] & !wb_px_req_r[1];
      assign wb_px_wr_req[1]  = wb_px_req_new[1] & wb_px_we_i[1];

      always @(posedge wb_clk)
        wb_px_req_r[1] <= wb_px_req[1] & !wb_px_ack_o[1];

       wb_to_userport #(
        .BURST_ADDR_WIDTH(P1_BURST_ADDR_WIDTH),
        .BURST_ADDR_ALIGN(P1_BURST_ADDR_ALIGN),
        .WB_BURSTING(P1_WB_BURSTING)
       )
       wb2up1 (
        .wb_clk                     (wb_clk),
        .wb_rst                     (wb_rst),
        .wb_adr_i                   (wb_px_adr_i[1]),
        .wb_stb_i                   (wb_px_stb_i[1]),
        .wb_cyc_i                   (wb_px_cyc_i[1]),
        .wb_cti_i                   (wb_px_cti_i[1]),
        .wb_bte_i                   (wb_px_bte_i[1]),
        .wb_we_i                    (wb_px_we_i[1]),
        .wb_sel_i                   (wb_px_sel_i[1]),
        .wb_dat_i                   (wb_px_dat_i[1]),
        .wb_dat_o                   (wb_px_dat_o[1]),
        .wb_ack_o                   (wb_px_ack_o[1]),

        .addr_dirty                 (px_addr_dirty[1]),
        .cache_addr                 (px_cache_addr[1]),

        .ddr2_px_cmd_full           (ddr2_px_cmd_full[1]),
        .ddr2_px_wr_full            (ddr2_px_wr_full[1]),
        .ddr2_px_wr_en              (ddr2_px_wr_en[1]),
        .ddr2_px_cmd_en             (ddr2_px_cmd_en[1]),
        .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[1]),
        .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[1]),
        .ddr2_px_wr_data            (ddr2_px_wr_data[1]),
        .ddr2_px_wr_mask            (ddr2_px_wr_mask[1]),
        .ddr2_px_rd_data            (ddr2_px_rd_data[1]),
        .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[1]),
        .ddr2_px_rd_en              (ddr2_px_rd_en[1]),
        .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[1]),
        .ddr2_px_wr_empty           (ddr2_px_wr_empty[1]),
        .ddr2_px_rd_full            (ddr2_px_rd_full[1]),
        .ddr2_px_rd_empty           (ddr2_px_rd_empty[1]),
        .ddr2_calib_done            (ddr2_calib_done)
        );

      assign wb_px_req[2]     = wb_px_stb_i[2] & wb_px_cyc_i[2] & ddr2_calib_done_r[0]; 
      assign wb_px_req_new[2] = wb_px_req[2] & !wb_px_req_r[2];
      assign wb_px_wr_req[2]  = wb_px_req_new[2] & wb_px_we_i[2];

      always @(posedge wb_clk)
        wb_px_req_r[2] <= wb_px_req[2] & !wb_px_ack_o[2];

       wb_to_userport #(
        .BURST_ADDR_WIDTH(P2_BURST_ADDR_WIDTH),
        .BURST_ADDR_ALIGN(P2_BURST_ADDR_ALIGN),
        .WB_BURSTING(P2_WB_BURSTING)
       )
       wb2up2 (
        .wb_clk                     (wb_clk),
        .wb_rst                     (wb_rst),
        .wb_adr_i                   (wb_px_adr_i[2]),
        .wb_stb_i                   (wb_px_stb_i[2]),
        .wb_cyc_i                   (wb_px_cyc_i[2]),
        .wb_cti_i                   (wb_px_cti_i[2]),
        .wb_bte_i                   (wb_px_bte_i[2]),
        .wb_we_i                    (wb_px_we_i[2]),
        .wb_sel_i                   (wb_px_sel_i[2]),
        .wb_dat_i                   (wb_px_dat_i[2]),
        .wb_dat_o                   (wb_px_dat_o[2]),
        .wb_ack_o                   (wb_px_ack_o[2]),

        .addr_dirty                 (px_addr_dirty[2]),
        .cache_addr                 (px_cache_addr[2]),

        .ddr2_px_cmd_full           (ddr2_px_cmd_full[2]),
        .ddr2_px_wr_full            (ddr2_px_wr_full[2]),
        .ddr2_px_wr_en              (ddr2_px_wr_en[2]),
        .ddr2_px_cmd_en             (ddr2_px_cmd_en[2]),
        .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[2]),
        .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[2]),
        .ddr2_px_wr_data            (ddr2_px_wr_data[2]),
        .ddr2_px_wr_mask            (ddr2_px_wr_mask[2]),
        .ddr2_px_rd_data            (ddr2_px_rd_data[2]),
        .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[2]),
        .ddr2_px_rd_en              (ddr2_px_rd_en[2]),
        .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[2]),
        .ddr2_px_wr_empty           (ddr2_px_wr_empty[2]),
        .ddr2_px_rd_full            (ddr2_px_rd_full[2]),
        .ddr2_px_rd_empty           (ddr2_px_rd_empty[2]),
        .ddr2_calib_done            (ddr2_calib_done)
        );

      assign wb_px_req[3]     = wb_px_stb_i[3] & wb_px_cyc_i[3] & ddr2_calib_done_r[0]; 
      assign wb_px_req_new[3] = wb_px_req[3] & !wb_px_req_r[3];
      assign wb_px_wr_req[3]  = wb_px_req_new[3] & wb_px_we_i[3];

      always @(posedge wb_clk)
        wb_px_req_r[3] <= wb_px_req[3] & !wb_px_ack_o[3];

       wb_to_userport #(
        .BURST_ADDR_WIDTH(P3_BURST_ADDR_WIDTH),
        .BURST_ADDR_ALIGN(P3_BURST_ADDR_ALIGN),
        .WB_BURSTING(P3_WB_BURSTING)
       )
       wb2up3 (
        .wb_clk                     (wb_clk),
        .wb_rst                     (wb_rst),
        .wb_adr_i                   (wb_px_adr_i[3]),
        .wb_stb_i                   (wb_px_stb_i[3]),
        .wb_cyc_i                   (wb_px_cyc_i[3]),
        .wb_cti_i                   (wb_px_cti_i[3]),
        .wb_bte_i                   (wb_px_bte_i[3]),
        .wb_we_i                    (wb_px_we_i[3]),
        .wb_sel_i                   (wb_px_sel_i[3]),
        .wb_dat_i                   (wb_px_dat_i[3]),
        .wb_dat_o                   (wb_px_dat_o[3]),
        .wb_ack_o                   (wb_px_ack_o[3]),

        .addr_dirty                 (px_addr_dirty[3]),
        .cache_addr                 (px_cache_addr[3]),

        .ddr2_px_cmd_full           (ddr2_px_cmd_full[3]),
        .ddr2_px_wr_full            (ddr2_px_wr_full[3]),
        .ddr2_px_wr_en              (ddr2_px_wr_en[3]),
        .ddr2_px_cmd_en             (ddr2_px_cmd_en[3]),
        .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[3]),
        .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[3]),
        .ddr2_px_wr_data            (ddr2_px_wr_data[3]),
        .ddr2_px_wr_mask            (ddr2_px_wr_mask[3]),
        .ddr2_px_rd_data            (ddr2_px_rd_data[3]),
        .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[3]),
        .ddr2_px_rd_en              (ddr2_px_rd_en[3]),
        .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[3]),
        .ddr2_px_wr_empty           (ddr2_px_wr_empty[3]),
        .ddr2_px_rd_full            (ddr2_px_rd_full[3]),
        .ddr2_px_rd_empty           (ddr2_px_rd_empty[3]),
        .ddr2_calib_done            (ddr2_calib_done)
        );

      assign wb_px_req[4]     = wb_px_stb_i[4] & wb_px_cyc_i[4] & ddr2_calib_done_r[0]; 
      assign wb_px_req_new[4] = wb_px_req[4] & !wb_px_req_r[4];
      assign wb_px_wr_req[4]  = wb_px_req_new[4] & wb_px_we_i[4];

      always @(posedge wb_clk)
        wb_px_req_r[4] <= wb_px_req[4] & !wb_px_ack_o[4];

       wb_to_userport #(
        .BURST_ADDR_WIDTH(P4_BURST_ADDR_WIDTH),
        .BURST_ADDR_ALIGN(P4_BURST_ADDR_ALIGN),
        .WB_BURSTING(P4_WB_BURSTING)
       )
       wb2up4 (
        .wb_clk                     (wb_clk),
        .wb_rst                     (wb_rst),
        .wb_adr_i                   (wb_px_adr_i[4]),
        .wb_stb_i                   (wb_px_stb_i[4]),
        .wb_cyc_i                   (wb_px_cyc_i[4]),
        .wb_cti_i                   (wb_px_cti_i[4]),
        .wb_bte_i                   (wb_px_bte_i[4]),
        .wb_we_i                    (wb_px_we_i[4]),
        .wb_sel_i                   (wb_px_sel_i[4]),
        .wb_dat_i                   (wb_px_dat_i[4]),
        .wb_dat_o                   (wb_px_dat_o[4]),
        .wb_ack_o                   (wb_px_ack_o[4]),

        .addr_dirty                 (px_addr_dirty[4]),
        .cache_addr                 (px_cache_addr[4]),

        .ddr2_px_cmd_full           (ddr2_px_cmd_full[4]),
        .ddr2_px_wr_full            (ddr2_px_wr_full[4]),
        .ddr2_px_wr_en              (ddr2_px_wr_en[4]),
        .ddr2_px_cmd_en             (ddr2_px_cmd_en[4]),
        .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[4]),
        .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[4]),
        .ddr2_px_wr_data            (ddr2_px_wr_data[4]),
        .ddr2_px_wr_mask            (ddr2_px_wr_mask[4]),
        .ddr2_px_rd_data            (ddr2_px_rd_data[4]),
        .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[4]),
        .ddr2_px_rd_en              (ddr2_px_rd_en[4]),
        .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[4]),
        .ddr2_px_wr_empty           (ddr2_px_wr_empty[4]),
        .ddr2_px_rd_full            (ddr2_px_rd_full[4]),
        .ddr2_px_rd_empty           (ddr2_px_rd_empty[4]),
        .ddr2_calib_done            (ddr2_calib_done)
        );
        
      assign wb_px_req[5]     = wb_px_stb_i[5] & wb_px_cyc_i[5] & ddr2_calib_done_r[0];
      assign wb_px_req_new[5] = wb_px_req[5] & !wb_px_req_r[5];
      assign wb_px_wr_req[5]  = wb_px_req_new[5] & wb_px_we_i[5];
                  
      always @(posedge wb_clk)
      wb_px_req_r[5] <= wb_px_req[5] & !wb_px_ack_o[5];
                                
      wb_to_userport #(
               .BURST_ADDR_WIDTH(P5_BURST_ADDR_WIDTH),
               .BURST_ADDR_ALIGN(P5_BURST_ADDR_ALIGN),
		   .WB_BURSTING(P5_WB_BURSTING)
                        )
         wb2up5 (
            .wb_clk                     (wb_clk),
            .wb_rst                     (wb_rst),
            .wb_adr_i                   (wb_px_adr_i[5]),
            .wb_stb_i                   (wb_px_stb_i[5]),
            .wb_cyc_i                   (wb_px_cyc_i[5]),
            .wb_cti_i                   (wb_px_cti_i[5]),
            .wb_bte_i                   (wb_px_bte_i[5]),
            .wb_we_i                    (wb_px_we_i[5]),
            .wb_sel_i                   (wb_px_sel_i[5]),
            .wb_dat_i                   (wb_px_dat_i[5]),
            .wb_dat_o                   (wb_px_dat_o[5]),
            .wb_ack_o                   (wb_px_ack_o[5]),
            .addr_dirty                 (px_addr_dirty[5]),
            .cache_addr                 (px_cache_addr[5]),
            .ddr2_px_cmd_full           (ddr2_px_cmd_full[5]),
            .ddr2_px_wr_full            (ddr2_px_wr_full[5]),
            .ddr2_px_wr_en              (ddr2_px_wr_en[5]),
            .ddr2_px_cmd_en             (ddr2_px_cmd_en[5]),
            .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[5]),
            .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[5]),
            .ddr2_px_wr_data            (ddr2_px_wr_data[5]),
            .ddr2_px_wr_mask            (ddr2_px_wr_mask[5]),
            .ddr2_px_rd_data            (ddr2_px_rd_data[5]),
            .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[5]),
            .ddr2_px_rd_en              (ddr2_px_rd_en[5]),
            .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[5]),
            .ddr2_px_wr_empty           (ddr2_px_wr_empty[5]),
            .ddr2_px_rd_full            (ddr2_px_rd_full[5]),
            .ddr2_px_rd_empty           (ddr2_px_rd_empty[5]),
            .ddr2_calib_done            (ddr2_calib_done)
            );








  mem32  #
  (
   .C3_P0_MASK_SIZE       (C3_P0_MASK_SIZE),
   .C3_P0_DATA_PORT_SIZE  (C3_P0_DATA_PORT_SIZE),
   .C3_P1_MASK_SIZE       (C3_P1_MASK_SIZE),
   .C3_P1_DATA_PORT_SIZE  (C3_P1_DATA_PORT_SIZE),
   .DEBUG_EN              (DEBUG_EN),       
   .C3_MEMCLK_PERIOD      (C3_MEMCLK_PERIOD),       
   .C3_CALIB_SOFT_IP      (C3_CALIB_SOFT_IP),       
   .C3_SIMULATION         (C3_SIMULATION),       
   .C3_RST_ACT_LOW        (C3_RST_ACT_LOW),       
   .C3_INPUT_CLK_TYPE     (C3_INPUT_CLK_TYPE),       
   .C3_MEM_ADDR_ORDER     (C3_MEM_ADDR_ORDER),       
   .C3_NUM_DQ_PINS        (C3_NUM_DQ_PINS),       
   .C3_MEM_ADDR_WIDTH     (C3_MEM_ADDR_WIDTH),       
   .C3_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH)       
   )
   mem32
   (
    .mcb3_dram_dq         (ddr2_dq),
    .mcb3_dram_a          (ddr2_a),
    .mcb3_dram_ba         (ddr2_ba),
    .mcb3_dram_ras_n      (ddr2_ras_n),
    .mcb3_dram_cas_n      (ddr2_cas_n),
    .mcb3_dram_we_n       (ddr2_we_n),

    .mcb3_dram_cke        (ddr2_cke),
    .mcb3_dram_dm         (ddr2_dm),
    .mcb3_dram_udqs       (ddr2_udqs),

    .mcb3_rzq             (ddr2_rzq),

    .mcb3_dram_udm        (ddr2_udm),
    .c3_sys_clk           (ddr2_if_clk),
    .c3_sys_rst_i         (ddr2_if_rst),
    .c3_calib_done        (ddr2_calib_done),
    .c3_clk0              (ddr2_clk),
    .c3_rst0              (ddr2_rst),
    .mcb3_dram_dqs        (ddr2_dqs),

    .mcb3_dram_ck         (ddr2_ck),          
    .mcb3_dram_ck_n       (ddr2_ck_n),
    .c3_p0_cmd_clk        (wb_clk),
    .c3_p0_cmd_en         (ddr2_px_cmd_en[0]),
    .c3_p0_cmd_instr      (ddr2_px_cmd_instr[0]),
    .c3_p0_cmd_bl         (ddr2_px_cmd_bl[0]),
    .c3_p0_cmd_byte_addr  (ddr2_px_cmd_byte_addr[0]),
    .c3_p0_cmd_empty      (ddr2_px_cmd_empty[0]),
    .c3_p0_cmd_full       (ddr2_px_cmd_full[0]),
    .c3_p0_wr_clk         (wb_clk),
    .c3_p0_wr_en          (ddr2_px_wr_en[0]),
    .c3_p0_wr_mask        (ddr2_px_wr_mask[0]),
    .c3_p0_wr_data        (ddr2_px_wr_data[0]),
    .c3_p0_wr_full        (ddr2_px_wr_full[0]),
    .c3_p0_wr_empty       (ddr2_px_wr_empty[0]),
    .c3_p0_wr_count       (ddr2_px_wr_count[0]),
    .c3_p0_wr_underrun    (ddr2_px_wr_underrun[0]),
    .c3_p0_wr_error       (ddr2_px_wr_error[0]),
    .c3_p0_rd_clk         (wb_clk),
    .c3_p0_rd_en          (ddr2_px_rd_en[0]),
    .c3_p0_rd_data        (ddr2_px_rd_data[0]),
    .c3_p0_rd_full        (ddr2_px_rd_full[0]),
    .c3_p0_rd_empty       (ddr2_px_rd_empty[0]),
    .c3_p0_rd_count       (ddr2_px_rd_count[0]),
    .c3_p0_rd_overflow    (ddr2_px_rd_overflow[0]),
    .c3_p0_rd_error       (ddr2_px_rd_error[0]),
    .c3_p1_cmd_clk        (wb_clk),
    .c3_p1_cmd_en         (ddr2_px_cmd_en[1]),
    .c3_p1_cmd_instr      (ddr2_px_cmd_instr[1]),
    .c3_p1_cmd_bl         (ddr2_px_cmd_bl[1]),
    .c3_p1_cmd_byte_addr  (ddr2_px_cmd_byte_addr[1]),
    .c3_p1_cmd_empty      (ddr2_px_cmd_empty[1]),
    .c3_p1_cmd_full       (ddr2_px_cmd_full[1]),
    .c3_p1_wr_clk         (wb_clk),
    .c3_p1_wr_en          (ddr2_px_wr_en[1]),
    .c3_p1_wr_mask        (ddr2_px_wr_mask[1]),
    .c3_p1_wr_data        (ddr2_px_wr_data[1]),
    .c3_p1_wr_full        (ddr2_px_wr_full[1]),
    .c3_p1_wr_empty       (ddr2_px_wr_empty[1]),
    .c3_p1_wr_count       (ddr2_px_wr_count[1]),
    .c3_p1_wr_underrun    (ddr2_px_wr_underrun[1]),
    .c3_p1_wr_error       (ddr2_px_wr_error[1]),
    .c3_p1_rd_clk         (wb_clk),
    .c3_p1_rd_en          (ddr2_px_rd_en[1]),
    .c3_p1_rd_data        (ddr2_px_rd_data[1]),
    .c3_p1_rd_full        (ddr2_px_rd_full[1]),
    .c3_p1_rd_empty       (ddr2_px_rd_empty[1]),
    .c3_p1_rd_count       (ddr2_px_rd_count[1]),
    .c3_p1_rd_overflow    (ddr2_px_rd_overflow[1]),
    .c3_p1_rd_error       (ddr2_px_rd_error[1]),
    .c3_p2_cmd_clk        (wb_clk),
    .c3_p2_cmd_en         (ddr2_px_cmd_en[2] & !wb_px_we_i[2]),
    .c3_p2_cmd_instr      (ddr2_px_cmd_instr[2]),
    .c3_p2_cmd_bl         (ddr2_px_cmd_bl[2]),
    .c3_p2_cmd_byte_addr  (ddr2_px_cmd_byte_addr[2]),
    .c3_p2_cmd_empty      (),
    .c3_p2_cmd_full       (),
    .c3_p2_rd_clk         (wb_clk),
    .c3_p2_rd_en          (ddr2_px_rd_en[2]),
    .c3_p2_rd_data        (ddr2_px_rd_data[2]),
    .c3_p2_rd_full        (ddr2_px_rd_full[2]),
    .c3_p2_rd_empty       (ddr2_px_rd_empty[2]),
    .c3_p2_rd_count       (ddr2_px_rd_count[2]),
    .c3_p2_rd_overflow    (ddr2_px_rd_overflow[2]),
    .c3_p2_rd_error       (ddr2_px_rd_error[2])

   );

endmodule
module xilinx_ddr2_if ( 
    input [31:0]       wb0_adr_i,
    input 	           wb0_stb_i,
    input 	           wb0_cyc_i,
    input  [2:0]       wb0_cti_i,
    input  [1:0]       wb0_bte_i,
    input 	           wb0_we_i,
    input  [3:0]       wb0_sel_i,
    input  [31:0]      wb0_dat_i,
    output [31:0]      wb0_dat_o,
    output             wb0_ack_o,

    input [31:0]       wb1_adr_i,
    input              wb1_stb_i,
    input              wb1_cyc_i,
    input  [2:0]       wb1_cti_i,
    input  [1:0]       wb1_bte_i,
    input              wb1_we_i,
    input  [3:0]       wb1_sel_i,
    input  [31:0]      wb1_dat_i,
    output [31:0]      wb1_dat_o,
    output             wb1_ack_o,

    input [31:0]       wb2_adr_i,
    input              wb2_stb_i,
    input              wb2_cyc_i,
    input  [2:0]       wb2_cti_i,
    input  [1:0]       wb2_bte_i,
    input              wb2_we_i,
    input  [3:0]       wb2_sel_i,
    input  [31:0]      wb2_dat_i,
    output [31:0]      wb2_dat_o,
    output             wb2_ack_o,

    input [31:0]       wb3_adr_i,
    input              wb3_stb_i,
    input              wb3_cyc_i,
    input  [2:0]       wb3_cti_i,
    input  [1:0]       wb3_bte_i,
    input              wb3_we_i,
    input  [3:0]       wb3_sel_i,
    input  [31:0]      wb3_dat_i,
    output [31:0]      wb3_dat_o,
    output             wb3_ack_o,

    input [31:0]       wb4_adr_i,
    input              wb4_stb_i,
    input              wb4_cyc_i,
    input  [2:0]       wb4_cti_i,
    input  [1:0]       wb4_bte_i,
    input              wb4_we_i,
    input  [3:0]       wb4_sel_i,
    input  [31:0]      wb4_dat_i,
    output [31:0]      wb4_dat_o,
    output             wb4_ack_o,

   input [31:0]       wb5_adr_i,
   input              wb5_stb_i,
   input              wb5_cyc_i,
   input  [2:0]       wb5_cti_i,
   input  [1:0]       wb5_bte_i,
   input              wb5_we_i,
   input  [3:0]       wb5_sel_i,
   input  [31:0]      wb5_dat_i,
   output [31:0]      wb5_dat_o,
   output             wb5_ack_o,
                                       

    output [12:0]      ddr2_a,
    output [2:0]       ddr2_ba,
    output 	           ddr2_ras_n,
    output 	           ddr2_cas_n,
    output 	           ddr2_we_n,
    output             ddr2_rzq,
    output             ddr2_zio,
    output             ddr2_odt,
    output             ddr2_cke,
    output             ddr2_dm,
    output             ddr2_udm,

    inout [15:0]       ddr2_dq,		  
    inout              ddr2_dqs,
    inout              ddr2_dqs_n,
    inout              ddr2_udqs,
    inout              ddr2_udqs_n,
    output             ddr2_ck,
    output             ddr2_ck_n,

    input 	           ddr2_if_clk,
    input 	           ddr2_if_rst,
    input 	           wb_clk,
    input 	           wb_rst
,
   output [31:0] 		     ddr2_trace_data0_o,
   output [31:0] 		     ddr2_trace_data1_o,
   output [31:0] 		     ddr2_trace_data2_o,
   output [31:0] 		     ddr2_trace_data3_o,
   output [31:0] 		     ddr2_trace_data4_o,
   output [31:0] 		     ddr2_trace_data5_o
);

   
`include "orpsoc-defines.v"
`include "xilinx_ddr2_params.v"
    parameter NUM_USERPORTS = 6;
    parameter P0_BURST_ADDR_WIDTH = 4;
    parameter P0_BURST_ADDR_ALIGN = P0_BURST_ADDR_WIDTH + 2;
	 parameter P0_WB_BURSTING      = "TRUE";
	 
    parameter P1_BURST_ADDR_WIDTH = 5;
    parameter P1_BURST_ADDR_ALIGN = P1_BURST_ADDR_WIDTH + 2;
	 parameter P1_WB_BURSTING      = "TRUE";
  
    parameter P2_BURST_ADDR_WIDTH = 6;
    parameter P2_BURST_ADDR_ALIGN = P2_BURST_ADDR_WIDTH + 2;
	 parameter P2_WB_BURSTING      = "TRUE";
  
    parameter P3_BURST_ADDR_WIDTH = 4;
    parameter P3_BURST_ADDR_ALIGN = P3_BURST_ADDR_WIDTH + 2;
	 parameter P3_WB_BURSTING      = "TRUE";

    parameter P4_BURST_ADDR_WIDTH = 4;
    parameter P4_BURST_ADDR_ALIGN = P4_BURST_ADDR_WIDTH + 2;
	 parameter P4_WB_BURSTING      = "TRUE";
   parameter P5_BURST_ADDR_WIDTH = 4;
       parameter P5_BURST_ADDR_ALIGN = P5_BURST_ADDR_WIDTH + 2;
        parameter P5_WB_BURSTING      = "TRUE";
       
       

    wire 	              ddr2_clk;
    wire 	              ddr2_rst;
 
    wire  [31:0]        wb_px_adr_i[NUM_USERPORTS-1:0];
    wire 	              wb_px_stb_i[NUM_USERPORTS-1:0];
    wire 	              wb_px_cyc_i[NUM_USERPORTS-1:0];
    wire  [2:0]         wb_px_cti_i[NUM_USERPORTS-1:0];
    wire  [1:0]         wb_px_bte_i[NUM_USERPORTS-1:0];
    wire 	              wb_px_we_i[NUM_USERPORTS-1:0];
    wire  [3:0]         wb_px_sel_i[NUM_USERPORTS-1:0];
    wire  [31:0]        wb_px_dat_i[NUM_USERPORTS-1:0];
    wire  [31:0]        wb_px_dat_o[NUM_USERPORTS-1:0];
    wire                wb_px_ack_o[NUM_USERPORTS-1:0];
 
    wire 	              wb_px_req[NUM_USERPORTS-1:0];
    reg 		            wb_px_req_r[NUM_USERPORTS-1:0];
    wire 	              wb_px_req_new[NUM_USERPORTS-1:0];
    wire                wb_px_wr_req[NUM_USERPORTS-1:0];
   

    wire                ddr2_px_cmd_full[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_full[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_en[NUM_USERPORTS-1:0];
    wire                ddr2_px_cmd_en[NUM_USERPORTS-1:0];
    wire [29:0]         ddr2_px_cmd_byte_addr[NUM_USERPORTS-1:0];
    wire [2:0]          ddr2_px_cmd_instr[NUM_USERPORTS-1:0];
    wire [31:0]         ddr2_px_wr_data[NUM_USERPORTS-1:0];
    wire [3:0]          ddr2_px_wr_mask[NUM_USERPORTS-1:0];
    wire [31:0]         ddr2_px_rd_data[NUM_USERPORTS-1:0];
    wire [5:0]          ddr2_px_cmd_bl[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_en[NUM_USERPORTS-1:0];
    wire                ddr2_px_cmd_empty[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_empty[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_count[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_underrun[NUM_USERPORTS-1:0];
    wire                ddr2_px_wr_error[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_full[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_empty[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_count[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_overflow[NUM_USERPORTS-1:0];
    wire                ddr2_px_rd_error[NUM_USERPORTS-1:0];
    wire 	              ddr2_calib_done;
    reg [1:0]           ddr2_calib_done_r;

    assign wb_px_adr_i[0] = wb0_adr_i;
    assign wb_px_stb_i[0] = wb0_stb_i;
    assign wb_px_cyc_i[0] = wb0_cyc_i;
    assign wb_px_cti_i[0] = wb0_cti_i;
    assign wb_px_bte_i[0] = wb0_bte_i;
    assign wb_px_we_i[0]  = wb0_we_i;
    assign wb_px_sel_i[0] = wb0_sel_i;
    assign wb_px_dat_i[0] = wb0_dat_i;
    assign wb0_dat_o = wb_px_dat_o[0];
    assign wb0_ack_o = wb_px_ack_o[0];

    assign wb_px_adr_i[1] = wb1_adr_i;
    assign wb_px_stb_i[1] = wb1_stb_i;
    assign wb_px_cyc_i[1] = wb1_cyc_i;
    assign wb_px_cti_i[1] = wb1_cti_i;
    assign wb_px_bte_i[1] = wb1_bte_i;
    assign wb_px_we_i[1]  = wb1_we_i;
    assign wb_px_sel_i[1] = wb1_sel_i;
    assign wb_px_dat_i[1] = wb1_dat_i;
    assign wb1_dat_o = wb_px_dat_o[1];
    assign wb1_ack_o = wb_px_ack_o[1];

    assign wb_px_adr_i[2] = wb2_adr_i;
    assign wb_px_stb_i[2] = wb2_stb_i;
    assign wb_px_cyc_i[2] = wb2_cyc_i;
    assign wb_px_cti_i[2] = wb2_cti_i;
    assign wb_px_bte_i[2] = wb2_bte_i;
    assign wb_px_we_i[2]  = wb2_we_i;
    assign wb_px_sel_i[2] = wb2_sel_i;
    assign wb_px_dat_i[2] = wb2_dat_i;
    assign wb2_dat_o = wb_px_dat_o[2];
    assign wb2_ack_o = wb_px_ack_o[2];

    assign wb_px_adr_i[3] = wb3_adr_i;
    assign wb_px_stb_i[3] = wb3_stb_i;
    assign wb_px_cyc_i[3] = wb3_cyc_i;
    assign wb_px_cti_i[3] = wb3_cti_i;
    assign wb_px_bte_i[3] = wb3_bte_i;
    assign wb_px_we_i[3]  = wb3_we_i;
    assign wb_px_sel_i[3] = wb3_sel_i;
    assign wb_px_dat_i[3] = wb3_dat_i;
    assign wb3_dat_o = wb_px_dat_o[3];
    assign wb3_ack_o = wb_px_ack_o[3];

    assign wb_px_adr_i[4] = wb4_adr_i;
    assign wb_px_stb_i[4] = wb4_stb_i;
    assign wb_px_cyc_i[4] = wb4_cyc_i;
    assign wb_px_cti_i[4] = wb4_cti_i;
    assign wb_px_bte_i[4] = wb4_bte_i;
    assign wb_px_we_i[4]  = wb4_we_i;
    assign wb_px_sel_i[4] = wb4_sel_i;
    assign wb_px_dat_i[4] = wb4_dat_i;
    assign wb4_dat_o = wb_px_dat_o[4];
    assign wb4_ack_o = wb_px_ack_o[4];
    
     assign wb_px_adr_i[5] = wb5_adr_i;
     assign wb_px_stb_i[5] = wb5_stb_i;
     assign wb_px_cyc_i[5] = wb5_cyc_i;
     assign wb_px_cti_i[5] = wb5_cti_i;
     assign wb_px_bte_i[5] = wb5_bte_i;
     assign wb_px_we_i[5]  = wb5_we_i;
     assign wb_px_sel_i[5] = wb5_sel_i;
     assign wb_px_dat_i[5] = wb5_dat_i;
     assign wb5_dat_o = wb_px_dat_o[5];
     assign wb5_ack_o = wb_px_ack_o[5];
                                         



    wire        px_addr_dirty[NUM_USERPORTS-1:0];
    wire [31:0] px_cache_addr[NUM_USERPORTS-1:0];



    assign px_addr_dirty[0] = ((wb0_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) |
                              ((wb1_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) | 
                              ((wb2_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                              ((wb3_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                              ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                              ((wb5_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[0][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);
                           
    assign px_addr_dirty[1] = ((wb0_adr_i[31:P1_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P1_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) | 
                              ((wb1_adr_i[31:P1_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P1_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) | 
                              ((wb2_adr_i[31:P1_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P1_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                              ((wb3_adr_i[31:P1_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P1_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                              ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                              ((wb5_adr_i[31:P1_BURST_ADDR_ALIGN] == px_cache_addr[1][31:P1_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);
                           
    assign px_addr_dirty[2] = ((wb0_adr_i[31:P2_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P2_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) | 
                              ((wb1_adr_i[31:P2_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P2_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) |
                              ((wb2_adr_i[31:P2_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P2_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                              ((wb3_adr_i[31:P2_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P2_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                              ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                              ((wb5_adr_i[31:P2_BURST_ADDR_ALIGN] == px_cache_addr[2][31:P2_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);
    
    assign px_addr_dirty[3] = ((wb0_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) | 
                              ((wb1_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) |
                              ((wb2_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                              ((wb3_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                              ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                              ((wb5_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[3][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);

    assign px_addr_dirty[4] = ((wb0_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) | 
                              ((wb1_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) |
                              ((wb2_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                              ((wb3_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                              ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                              ((wb5_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[4][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);

   assign px_addr_dirty[5] = ((wb0_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[0]) |
                             ((wb1_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[1]) |
                             ((wb2_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[2]) |
                             ((wb3_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[3]) |
                             ((wb4_adr_i[31:P0_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P0_BURST_ADDR_ALIGN]) & wb_px_wr_req[4]) |
                             ((wb5_adr_i[31:P3_BURST_ADDR_ALIGN] == px_cache_addr[5][31:P3_BURST_ADDR_ALIGN]) & wb_px_wr_req[5]);
                                                                                                                           
                                                                                                                           
   always @ (posedge wb_clk)
     ddr2_calib_done_r[1:0] <= {ddr2_calib_done, ddr2_calib_done_r[1]};

   assign ddr2_trace_data3_o = wb_px_adr_i[1];
   assign ddr2_trace_data4_o = ddr2_px_rd_data[1];
   assign ddr2_trace_data5_o = {
				ddr2_px_cmd_full[1],
				ddr2_px_wr_full[1],
				ddr2_px_wr_en[1],
				ddr2_px_cmd_en[1],
				ddr2_px_cmd_instr[1],
				ddr2_px_rd_en[1],
				ddr2_px_cmd_empty[1],
				ddr2_px_wr_empty[1],
				ddr2_px_rd_full[1],
				ddr2_px_rd_empty[1],
				ddr2_px_rd_error[1],
				ddr2_px_wr_error[1],
				18'h0
				};

      assign wb_px_req[0]     = wb_px_stb_i[0] & wb_px_cyc_i[0] & ddr2_calib_done_r[0]; 
      assign wb_px_req_new[0] = wb_px_req[0] & !wb_px_req_r[0];
      assign wb_px_wr_req[0]  = wb_px_req_new[0] & wb_px_we_i[0];

      always @(posedge wb_clk)
        wb_px_req_r[0] <= wb_px_req[0] & !wb_px_ack_o[0];

       wb_to_userport #(
        .BURST_ADDR_WIDTH(P0_BURST_ADDR_WIDTH),
        .BURST_ADDR_ALIGN(P0_BURST_ADDR_ALIGN),
        .WB_BURSTING(P0_WB_BURSTING)
       )
       wb2up0 (
        .wb_clk                     (wb_clk),
        .wb_rst                     (wb_rst),
        .wb_adr_i                   (wb_px_adr_i[0]),
        .wb_stb_i                   (wb_px_stb_i[0]),
        .wb_cyc_i                   (wb_px_cyc_i[0]),
        .wb_cti_i                   (wb_px_cti_i[0]),
        .wb_bte_i                   (wb_px_bte_i[0]),
        .wb_we_i                    (wb_px_we_i[0]),
        .wb_sel_i                   (wb_px_sel_i[0]),
        .wb_dat_i                   (wb_px_dat_i[0]),
        .wb_dat_o                   (wb_px_dat_o[0]),
        .wb_ack_o                   (wb_px_ack_o[0]),

        .addr_dirty                 (px_addr_dirty[0]),
        .cache_addr                 (px_cache_addr[0]),

        .ddr2_px_cmd_full           (ddr2_px_cmd_full[0]),
        .ddr2_px_wr_full            (ddr2_px_wr_full[0]),
        .ddr2_px_wr_en              (ddr2_px_wr_en[0]),
        .ddr2_px_cmd_en             (ddr2_px_cmd_en[0]),
        .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[0]),
        .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[0]),
        .ddr2_px_wr_data            (ddr2_px_wr_data[0]),
        .ddr2_px_wr_mask            (ddr2_px_wr_mask[0]),
        .ddr2_px_rd_data            (ddr2_px_rd_data[0]),
        .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[0]),
        .ddr2_px_rd_en              (ddr2_px_rd_en[0]),
        .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[0]),
        .ddr2_px_wr_empty           (ddr2_px_wr_empty[0]),
        .ddr2_px_rd_full            (ddr2_px_rd_full[0]),
        .ddr2_px_rd_empty           (ddr2_px_rd_empty[0]),
        .ddr2_calib_done            (ddr2_calib_done)
        );

      assign wb_px_req[1]     = wb_px_stb_i[1] & wb_px_cyc_i[1] & ddr2_calib_done_r[0]; 
      assign wb_px_req_new[1] = wb_px_req[1] & !wb_px_req_r[1];
      assign wb_px_wr_req[1]  = wb_px_req_new[1] & wb_px_we_i[1];

      always @(posedge wb_clk)
        wb_px_req_r[1] <= wb_px_req[1] & !wb_px_ack_o[1];

       wb_to_userport #(
        .BURST_ADDR_WIDTH(P1_BURST_ADDR_WIDTH),
        .BURST_ADDR_ALIGN(P1_BURST_ADDR_ALIGN),
        .WB_BURSTING(P1_WB_BURSTING)
       )
       wb2up1 (
        .wb_clk                     (wb_clk),
        .wb_rst                     (wb_rst),
        .wb_adr_i                   (wb_px_adr_i[1]),
        .wb_stb_i                   (wb_px_stb_i[1]),
        .wb_cyc_i                   (wb_px_cyc_i[1]),
        .wb_cti_i                   (wb_px_cti_i[1]),
        .wb_bte_i                   (wb_px_bte_i[1]),
        .wb_we_i                    (wb_px_we_i[1]),
        .wb_sel_i                   (wb_px_sel_i[1]),
        .wb_dat_i                   (wb_px_dat_i[1]),
        .wb_dat_o                   (wb_px_dat_o[1]),
        .wb_ack_o                   (wb_px_ack_o[1]),

        .addr_dirty                 (px_addr_dirty[1]),
        .cache_addr                 (px_cache_addr[1]),

        .ddr2_px_cmd_full           (ddr2_px_cmd_full[1]),
        .ddr2_px_wr_full            (ddr2_px_wr_full[1]),
        .ddr2_px_wr_en              (ddr2_px_wr_en[1]),
        .ddr2_px_cmd_en             (ddr2_px_cmd_en[1]),
        .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[1]),
        .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[1]),
        .ddr2_px_wr_data            (ddr2_px_wr_data[1]),
        .ddr2_px_wr_mask            (ddr2_px_wr_mask[1]),
        .ddr2_px_rd_data            (ddr2_px_rd_data[1]),
        .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[1]),
        .ddr2_px_rd_en              (ddr2_px_rd_en[1]),
        .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[1]),
        .ddr2_px_wr_empty           (ddr2_px_wr_empty[1]),
        .ddr2_px_rd_full            (ddr2_px_rd_full[1]),
        .ddr2_px_rd_empty           (ddr2_px_rd_empty[1]),
        .ddr2_calib_done            (ddr2_calib_done)
        );

      assign wb_px_req[2]     = wb_px_stb_i[2] & wb_px_cyc_i[2] & ddr2_calib_done_r[0]; 
      assign wb_px_req_new[2] = wb_px_req[2] & !wb_px_req_r[2];
      assign wb_px_wr_req[2]  = wb_px_req_new[2] & wb_px_we_i[2];

      always @(posedge wb_clk)
        wb_px_req_r[2] <= wb_px_req[2] & !wb_px_ack_o[2];

       wb_to_userport #(
        .BURST_ADDR_WIDTH(P2_BURST_ADDR_WIDTH),
        .BURST_ADDR_ALIGN(P2_BURST_ADDR_ALIGN),
        .WB_BURSTING(P2_WB_BURSTING)
       )
       wb2up2 (
        .wb_clk                     (wb_clk),
        .wb_rst                     (wb_rst),
        .wb_adr_i                   (wb_px_adr_i[2]),
        .wb_stb_i                   (wb_px_stb_i[2]),
        .wb_cyc_i                   (wb_px_cyc_i[2]),
        .wb_cti_i                   (wb_px_cti_i[2]),
        .wb_bte_i                   (wb_px_bte_i[2]),
        .wb_we_i                    (wb_px_we_i[2]),
        .wb_sel_i                   (wb_px_sel_i[2]),
        .wb_dat_i                   (wb_px_dat_i[2]),
        .wb_dat_o                   (wb_px_dat_o[2]),
        .wb_ack_o                   (wb_px_ack_o[2]),

        .addr_dirty                 (px_addr_dirty[2]),
        .cache_addr                 (px_cache_addr[2]),

        .ddr2_px_cmd_full           (ddr2_px_cmd_full[2]),
        .ddr2_px_wr_full            (ddr2_px_wr_full[2]),
        .ddr2_px_wr_en              (ddr2_px_wr_en[2]),
        .ddr2_px_cmd_en             (ddr2_px_cmd_en[2]),
        .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[2]),
        .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[2]),
        .ddr2_px_wr_data            (ddr2_px_wr_data[2]),
        .ddr2_px_wr_mask            (ddr2_px_wr_mask[2]),
        .ddr2_px_rd_data            (ddr2_px_rd_data[2]),
        .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[2]),
        .ddr2_px_rd_en              (ddr2_px_rd_en[2]),
        .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[2]),
        .ddr2_px_wr_empty           (ddr2_px_wr_empty[2]),
        .ddr2_px_rd_full            (ddr2_px_rd_full[2]),
        .ddr2_px_rd_empty           (ddr2_px_rd_empty[2]),
        .ddr2_calib_done            (ddr2_calib_done)
        );

      assign wb_px_req[3]     = wb_px_stb_i[3] & wb_px_cyc_i[3] & ddr2_calib_done_r[0]; 
      assign wb_px_req_new[3] = wb_px_req[3] & !wb_px_req_r[3];
      assign wb_px_wr_req[3]  = wb_px_req_new[3] & wb_px_we_i[3];

      always @(posedge wb_clk)
        wb_px_req_r[3] <= wb_px_req[3] & !wb_px_ack_o[3];

       wb_to_userport #(
        .BURST_ADDR_WIDTH(P3_BURST_ADDR_WIDTH),
        .BURST_ADDR_ALIGN(P3_BURST_ADDR_ALIGN),
        .WB_BURSTING(P3_WB_BURSTING)
       )
       wb2up3 (
        .wb_clk                     (wb_clk),
        .wb_rst                     (wb_rst),
        .wb_adr_i                   (wb_px_adr_i[3]),
        .wb_stb_i                   (wb_px_stb_i[3]),
        .wb_cyc_i                   (wb_px_cyc_i[3]),
        .wb_cti_i                   (wb_px_cti_i[3]),
        .wb_bte_i                   (wb_px_bte_i[3]),
        .wb_we_i                    (wb_px_we_i[3]),
        .wb_sel_i                   (wb_px_sel_i[3]),
        .wb_dat_i                   (wb_px_dat_i[3]),
        .wb_dat_o                   (wb_px_dat_o[3]),
        .wb_ack_o                   (wb_px_ack_o[3]),

        .addr_dirty                 (px_addr_dirty[3]),
        .cache_addr                 (px_cache_addr[3]),

        .ddr2_px_cmd_full           (ddr2_px_cmd_full[3]),
        .ddr2_px_wr_full            (ddr2_px_wr_full[3]),
        .ddr2_px_wr_en              (ddr2_px_wr_en[3]),
        .ddr2_px_cmd_en             (ddr2_px_cmd_en[3]),
        .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[3]),
        .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[3]),
        .ddr2_px_wr_data            (ddr2_px_wr_data[3]),
        .ddr2_px_wr_mask            (ddr2_px_wr_mask[3]),
        .ddr2_px_rd_data            (ddr2_px_rd_data[3]),
        .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[3]),
        .ddr2_px_rd_en              (ddr2_px_rd_en[3]),
        .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[3]),
        .ddr2_px_wr_empty           (ddr2_px_wr_empty[3]),
        .ddr2_px_rd_full            (ddr2_px_rd_full[3]),
        .ddr2_px_rd_empty           (ddr2_px_rd_empty[3]),
        .ddr2_calib_done            (ddr2_calib_done)
        );

      assign wb_px_req[4]     = wb_px_stb_i[4] & wb_px_cyc_i[4] & ddr2_calib_done_r[0]; 
      assign wb_px_req_new[4] = wb_px_req[4] & !wb_px_req_r[4];
      assign wb_px_wr_req[4]  = wb_px_req_new[4] & wb_px_we_i[4];

      always @(posedge wb_clk)
        wb_px_req_r[4] <= wb_px_req[4] & !wb_px_ack_o[4];

       wb_to_userport #(
        .BURST_ADDR_WIDTH(P4_BURST_ADDR_WIDTH),
        .BURST_ADDR_ALIGN(P4_BURST_ADDR_ALIGN),
        .WB_BURSTING(P4_WB_BURSTING)
       )
       wb2up4 (
        .wb_clk                     (wb_clk),
        .wb_rst                     (wb_rst),
        .wb_adr_i                   (wb_px_adr_i[4]),
        .wb_stb_i                   (wb_px_stb_i[4]),
        .wb_cyc_i                   (wb_px_cyc_i[4]),
        .wb_cti_i                   (wb_px_cti_i[4]),
        .wb_bte_i                   (wb_px_bte_i[4]),
        .wb_we_i                    (wb_px_we_i[4]),
        .wb_sel_i                   (wb_px_sel_i[4]),
        .wb_dat_i                   (wb_px_dat_i[4]),
        .wb_dat_o                   (wb_px_dat_o[4]),
        .wb_ack_o                   (wb_px_ack_o[4]),

        .addr_dirty                 (px_addr_dirty[4]),
        .cache_addr                 (px_cache_addr[4]),

        .ddr2_px_cmd_full           (ddr2_px_cmd_full[4]),
        .ddr2_px_wr_full            (ddr2_px_wr_full[4]),
        .ddr2_px_wr_en              (ddr2_px_wr_en[4]),
        .ddr2_px_cmd_en             (ddr2_px_cmd_en[4]),
        .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[4]),
        .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[4]),
        .ddr2_px_wr_data            (ddr2_px_wr_data[4]),
        .ddr2_px_wr_mask            (ddr2_px_wr_mask[4]),
        .ddr2_px_rd_data            (ddr2_px_rd_data[4]),
        .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[4]),
        .ddr2_px_rd_en              (ddr2_px_rd_en[4]),
        .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[4]),
        .ddr2_px_wr_empty           (ddr2_px_wr_empty[4]),
        .ddr2_px_rd_full            (ddr2_px_rd_full[4]),
        .ddr2_px_rd_empty           (ddr2_px_rd_empty[4]),
        .ddr2_calib_done            (ddr2_calib_done)
        );
        
      assign wb_px_req[5]     = wb_px_stb_i[5] & wb_px_cyc_i[5] & ddr2_calib_done_r[0];
      assign wb_px_req_new[5] = wb_px_req[5] & !wb_px_req_r[5];
      assign wb_px_wr_req[5]  = wb_px_req_new[5] & wb_px_we_i[5];
                  
      always @(posedge wb_clk)
      wb_px_req_r[5] <= wb_px_req[5] & !wb_px_ack_o[5];
                                
      wb_to_userport #(
               .BURST_ADDR_WIDTH(P5_BURST_ADDR_WIDTH),
               .BURST_ADDR_ALIGN(P5_BURST_ADDR_ALIGN),
		   .WB_BURSTING(P5_WB_BURSTING)
                        )
         wb2up5 (
            .wb_clk                     (wb_clk),
            .wb_rst                     (wb_rst),
            .wb_adr_i                   (wb_px_adr_i[5]),
            .wb_stb_i                   (wb_px_stb_i[5]),
            .wb_cyc_i                   (wb_px_cyc_i[5]),
            .wb_cti_i                   (wb_px_cti_i[5]),
            .wb_bte_i                   (wb_px_bte_i[5]),
            .wb_we_i                    (wb_px_we_i[5]),
            .wb_sel_i                   (wb_px_sel_i[5]),
            .wb_dat_i                   (wb_px_dat_i[5]),
            .wb_dat_o                   (wb_px_dat_o[5]),
            .wb_ack_o                   (wb_px_ack_o[5]),
            .addr_dirty                 (px_addr_dirty[5]),
            .cache_addr                 (px_cache_addr[5]),
            .ddr2_px_cmd_full           (ddr2_px_cmd_full[5]),
            .ddr2_px_wr_full            (ddr2_px_wr_full[5]),
            .ddr2_px_wr_en              (ddr2_px_wr_en[5]),
            .ddr2_px_cmd_en             (ddr2_px_cmd_en[5]),
            .ddr2_px_cmd_byte_addr      (ddr2_px_cmd_byte_addr[5]),
            .ddr2_px_cmd_instr          (ddr2_px_cmd_instr[5]),
            .ddr2_px_wr_data            (ddr2_px_wr_data[5]),
            .ddr2_px_wr_mask            (ddr2_px_wr_mask[5]),
            .ddr2_px_rd_data            (ddr2_px_rd_data[5]),
            .ddr2_px_cmd_bl             (ddr2_px_cmd_bl[5]),
            .ddr2_px_rd_en              (ddr2_px_rd_en[5]),
            .ddr2_px_cmd_empty          (ddr2_px_cmd_empty[5]),
            .ddr2_px_wr_empty           (ddr2_px_wr_empty[5]),
            .ddr2_px_rd_full            (ddr2_px_rd_full[5]),
            .ddr2_px_rd_empty           (ddr2_px_rd_empty[5]),
            .ddr2_calib_done            (ddr2_calib_done)
            );








  mem32  #
  (
   .C3_P0_MASK_SIZE       (C3_P0_MASK_SIZE),
   .C3_P0_DATA_PORT_SIZE  (C3_P0_DATA_PORT_SIZE),
   .C3_P1_MASK_SIZE       (C3_P1_MASK_SIZE),
   .C3_P1_DATA_PORT_SIZE  (C3_P1_DATA_PORT_SIZE),
   .DEBUG_EN              (DEBUG_EN),       
   .C3_MEMCLK_PERIOD      (C3_MEMCLK_PERIOD),       
   .C3_CALIB_SOFT_IP      (C3_CALIB_SOFT_IP),       
   .C3_SIMULATION         (C3_SIMULATION),       
   .C3_RST_ACT_LOW        (C3_RST_ACT_LOW),       
   .C3_INPUT_CLK_TYPE     (C3_INPUT_CLK_TYPE),       
   .C3_MEM_ADDR_ORDER     (C3_MEM_ADDR_ORDER),       
   .C3_NUM_DQ_PINS        (C3_NUM_DQ_PINS),       
   .C3_MEM_ADDR_WIDTH     (C3_MEM_ADDR_WIDTH),       
   .C3_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH)       
   )
   mem32
   (
    .mcb3_dram_dq         (ddr2_dq),
    .mcb3_dram_a          (ddr2_a),
    .mcb3_dram_ba         (ddr2_ba),
    .mcb3_dram_ras_n      (ddr2_ras_n),
    .mcb3_dram_cas_n      (ddr2_cas_n),
    .mcb3_dram_we_n       (ddr2_we_n),

    .mcb3_dram_cke        (ddr2_cke),
    .mcb3_dram_dm         (ddr2_dm),
    .mcb3_dram_udqs       (ddr2_udqs),

    .mcb3_rzq             (ddr2_rzq),

    .mcb3_dram_udm        (ddr2_udm),
    .c3_sys_clk           (ddr2_if_clk),
    .c3_sys_rst_i         (ddr2_if_rst),
    .c3_calib_done        (ddr2_calib_done),
    .c3_clk0              (ddr2_clk),
    .c3_rst0              (ddr2_rst),
    .mcb3_dram_dqs        (ddr2_dqs),

    .mcb3_dram_ck         (ddr2_ck),          
    .mcb3_dram_ck_n       (ddr2_ck_n),
    .c3_p0_cmd_clk        (wb_clk),
    .c3_p0_cmd_en         (ddr2_px_cmd_en[0]),
    .c3_p0_cmd_instr      (ddr2_px_cmd_instr[0]),
    .c3_p0_cmd_bl         (ddr2_px_cmd_bl[0]),
    .c3_p0_cmd_byte_addr  (ddr2_px_cmd_byte_addr[0]),
    .c3_p0_cmd_empty      (ddr2_px_cmd_empty[0]),
    .c3_p0_cmd_full       (ddr2_px_cmd_full[0]),
    .c3_p0_wr_clk         (wb_clk),
    .c3_p0_wr_en          (ddr2_px_wr_en[0]),
    .c3_p0_wr_mask        (ddr2_px_wr_mask[0]),
    .c3_p0_wr_data        (ddr2_px_wr_data[0]),
    .c3_p0_wr_full        (ddr2_px_wr_full[0]),
    .c3_p0_wr_empty       (ddr2_px_wr_empty[0]),
    .c3_p0_wr_count       (ddr2_px_wr_count[0]),
    .c3_p0_wr_underrun    (ddr2_px_wr_underrun[0]),
    .c3_p0_wr_error       (ddr2_px_wr_error[0]),
    .c3_p0_rd_clk         (wb_clk),
    .c3_p0_rd_en          (ddr2_px_rd_en[0]),
    .c3_p0_rd_data        (ddr2_px_rd_data[0]),
    .c3_p0_rd_full        (ddr2_px_rd_full[0]),
    .c3_p0_rd_empty       (ddr2_px_rd_empty[0]),
    .c3_p0_rd_count       (ddr2_px_rd_count[0]),
    .c3_p0_rd_overflow    (ddr2_px_rd_overflow[0]),
    .c3_p0_rd_error       (ddr2_px_rd_error[0]),
    .c3_p1_cmd_clk        (wb_clk),
    .c3_p1_cmd_en         (ddr2_px_cmd_en[1]),
    .c3_p1_cmd_instr      (ddr2_px_cmd_instr[1]),
    .c3_p1_cmd_bl         (ddr2_px_cmd_bl[1]),
    .c3_p1_cmd_byte_addr  (ddr2_px_cmd_byte_addr[1]),
    .c3_p1_cmd_empty      (ddr2_px_cmd_empty[1]),
    .c3_p1_cmd_full       (ddr2_px_cmd_full[1]),
    .c3_p1_wr_clk         (wb_clk),
    .c3_p1_wr_en          (ddr2_px_wr_en[1]),
    .c3_p1_wr_mask        (ddr2_px_wr_mask[1]),
    .c3_p1_wr_data        (ddr2_px_wr_data[1]),
    .c3_p1_wr_full        (ddr2_px_wr_full[1]),
    .c3_p1_wr_empty       (ddr2_px_wr_empty[1]),
    .c3_p1_wr_count       (ddr2_px_wr_count[1]),
    .c3_p1_wr_underrun    (ddr2_px_wr_underrun[1]),
    .c3_p1_wr_error       (ddr2_px_wr_error[1]),
    .c3_p1_rd_clk         (wb_clk),
    .c3_p1_rd_en          (ddr2_px_rd_en[1]),
    .c3_p1_rd_data        (ddr2_px_rd_data[1]),
    .c3_p1_rd_full        (ddr2_px_rd_full[1]),
    .c3_p1_rd_empty       (ddr2_px_rd_empty[1]),
    .c3_p1_rd_count       (ddr2_px_rd_count[1]),
    .c3_p1_rd_overflow    (ddr2_px_rd_overflow[1]),
    .c3_p1_rd_error       (ddr2_px_rd_error[1]),
    .c3_p2_cmd_clk        (wb_clk),
    .c3_p2_cmd_en         (ddr2_px_cmd_en[2] & !wb_px_we_i[2]),
    .c3_p2_cmd_instr      (ddr2_px_cmd_instr[2]),
    .c3_p2_cmd_bl         (ddr2_px_cmd_bl[2]),
    .c3_p2_cmd_byte_addr  (ddr2_px_cmd_byte_addr[2]),
    .c3_p2_cmd_empty      (),
    .c3_p2_cmd_full       (),
    .c3_p2_rd_clk         (wb_clk),
    .c3_p2_rd_en          (ddr2_px_rd_en[2]),
    .c3_p2_rd_data        (ddr2_px_rd_data[2]),
    .c3_p2_rd_full        (ddr2_px_rd_full[2]),
    .c3_p2_rd_empty       (ddr2_px_rd_empty[2]),
    .c3_p2_rd_count       (ddr2_px_rd_count[2]),
    .c3_p2_rd_overflow    (ddr2_px_rd_overflow[2]),
    .c3_p2_rd_error       (ddr2_px_rd_error[2])

   );

endmodule