data/full_repos/permissive/20270692/labs/lab2/sample/flip_me.v
data/verilator_xmls/649934ef-7921-4610-b0ae-da100fc8611d.xml
module flip_me (A,B);

  input A;
  output B;

  not G1(B,A);

endmodule
module flip_me (A,B);


  input A;
  output B;

  not G1(B,A);

endmodule