data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulacjion_VIDEO_PATH.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulacjion_VIDEO_PATH.v:24: Cannot find include file: video_in_v3.v\n`include "video_in_v3.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/video_in_v3.v\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/video_in_v3.v.v\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/video_in_v3.v.sv\n             video_in_v3.v\n             video_in_v3.v.v\n             video_in_v3.v.sv\n             obj_dir/video_in_v3.v\n             obj_dir/video_in_v3.v.v\n             obj_dir/video_in_v3.v.sv\n%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulacjion_VIDEO_PATH.v:25: Cannot find include file: video_out_v3.v\n`include "video_out_v3.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulacjion_VIDEO_PATH.v:26: Cannot find include file: blk_mem_gen5.v\n`include "blk_mem_gen5.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulacjion_VIDEO_PATH.v:27: Cannot find include file: CPS_v3.v\n`include "CPS_v3.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulacjion_VIDEO_PATH.v:28: Cannot find include file: dviPLL4.v\n`include "dviPLL4.v" \n         ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulacjion_VIDEO_PATH.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulacjion_VIDEO_PATH.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #1000 video_ACK=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulacjion_VIDEO_PATH.v:127: Unsupported: Ignoring delay on this delayed statement.\n always #1   Bus2IP_Clk=~Bus2IP_Clk;    \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulacjion_VIDEO_PATH.v:128: Unsupported: Ignoring delay on this delayed statement.\n always #2 ad_dataclk_i=~ad_dataclk_i;  \n        ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module symulacjion_VIDEO_PATH;


	reg ad_dataclk_i;
	reg ad_hsync_i;
	reg ad_vsync_i;
	reg [0:7] ad_red_i;
	reg [0:7] ad_green_i;
	reg [0:7] ad_blue_i;
	reg Bus2IP_Clk;
	reg Bus2IP_Reset;


	wire rst_Chrontel_o;
	wire [0:11] dvi_d_o;
	wire x_clk_p_o;
	wire x_clk_n_o;
	wire dvi_de_o;
	wire dvi_hsync_o;
	wire dvi_vsync_o;
	wire [10:0] column_max;
	wire [10:0] line_max;
	
	reg [9:0] H_FP;
	reg [9:0] H_BP;
	reg [9:0] H_sync;
	reg [9:0] H_VldDat;
	reg [9:0] COLUMNS;
	reg [9:0] V_FP;
	reg [9:0] V_BP;
	reg [9:0] V_sync;
	reg [9:0] V_VldDat;
	reg [9:0] LINES;
	reg H_active;
	reg V_active;
	

	reg [10:0] column;
	reg [10:0] line;
	reg DataEnable;
	reg [4:0] add_op;
	reg [23:0] pixs;
	reg temp_col;
	reg video_ACK;
	

	symulation_main uut (
		.rst_Chrontel_o(rst_Chrontel_o), 
		.dvi_d_o(dvi_d_o), 
		.x_clk_p_o(x_clk_p_o), 
		.x_clk_n_o(x_clk_n_o), 
		.dvi_de_o(dvi_de_o), 
		.dvi_hsync_o(dvi_hsync_o), 
		.dvi_vsync_o(dvi_vsync_o), 
		.ad_dataclk_i(ad_dataclk_i), 
		.ad_hsync_i(ad_hsync_i), 
		.ad_vsync_i(ad_vsync_i), 
		.ad_red_i(ad_red_i), 
		.ad_green_i(ad_green_i), 
		.ad_blue_i(ad_blue_i), 
		.Bus2IP_Clk(Bus2IP_Clk), 
		.Bus2IP_Reset(Bus2IP_Reset), 
		.column_max(column_max), 
		.line_max(line_max)
	);

	initial begin

		ad_dataclk_i = 0;
		ad_hsync_i = 0;
		ad_vsync_i = 0;
		ad_red_i = 0;
		ad_green_i = 0;
		ad_blue_i = 0;
		Bus2IP_Clk = 0;
		Bus2IP_Reset = 1;
		H_FP = 16;
		H_BP = 120;
		H_sync = 64;
		H_VldDat = 640;
		COLUMNS = H_FP+H_BP+H_sync+H_VldDat;
		V_FP = 1;
		V_BP = 16;
		V_sync = 3;
		V_VldDat = 480;
		LINES = V_FP+V_BP+V_sync+V_VldDat;
		H_active = 0;
		V_active = 0;
		DataEnable=0;
		video_ACK=0;
		
		#100;
      Bus2IP_Reset = 0;
		#1000 video_ACK=1;
		
	end
	
	always #1   Bus2IP_Clk=~Bus2IP_Clk;
	always #2	ad_dataclk_i=~ad_dataclk_i;
	
	always @(posedge ad_dataclk_i or posedge Bus2IP_Reset)
	begin
		if(Bus2IP_Reset)
		begin
			column<=0;
			line<=0;
			temp_col<=0;
		end
		else
		begin
			if(video_ACK)
			begin
				if(line<LINES)
				begin
					if(column<COLUMNS)
					begin
						column<=column+1'b1;
					end
					else
					begin
						line<=line+1'b1;
						column<=0;
					end	
				end
				else 
				begin
					line<=0;
					column<=0;	
				end	
			end		
		end
	end

	always @(negedge ad_dataclk_i or posedge Bus2IP_Reset)
	begin
		if(Bus2IP_Reset)
		begin
			ad_hsync_i<=1'b1;
			ad_vsync_i<=1'b1;
			DataEnable<=1'b0;
			ad_red_i<=0;
			ad_green_i<=0;
			ad_blue_i<=0;
			add_op<=1;
			pixs=0;
		end
		else
		begin
			if(video_ACK)
			begin
				if(DataEnable)
				begin
					pixs=24'hCF4F4F;
					ad_red_i<=pixs[23:16];
					ad_green_i<=pixs[15:8];
					ad_blue_i<=pixs[7:0];
				end
				else
				begin
					ad_red_i<=0;
					ad_green_i<=0;
					ad_blue_i<=0;
					pixs=0;
				end	
				
				if(line >(V_FP-1+ V_sync+V_BP))
				begin
					if(column>(H_FP+H_BP+H_sync))	DataEnable<=1'b1;
					else DataEnable<=1'b0;	
				end
				else DataEnable<=1'b0;
				
				if(column>(H_FP-1) && column<(H_FP+H_sync) ) 
				begin
					ad_hsync_i<=1'b0;
					
				end
				else ad_hsync_i<=1'b1;	
				
				if(line>(V_FP-1) && line<(V_FP+V_sync)) 
				begin
					ad_vsync_i<=1'b0; 
					add_op<=add_op+1'b1;
				end	
				else ad_vsync_i<=1'b1;
			end	
		end
	end
endmodule
module symulacjion_VIDEO_PATH;



	reg ad_dataclk_i;
	reg ad_hsync_i;
	reg ad_vsync_i;
	reg [0:7] ad_red_i;
	reg [0:7] ad_green_i;
	reg [0:7] ad_blue_i;
	reg Bus2IP_Clk;
	reg Bus2IP_Reset;


	wire rst_Chrontel_o;
	wire [0:11] dvi_d_o;
	wire x_clk_p_o;
	wire x_clk_n_o;
	wire dvi_de_o;
	wire dvi_hsync_o;
	wire dvi_vsync_o;
	wire [10:0] column_max;
	wire [10:0] line_max;
	
	reg [9:0] H_FP;
	reg [9:0] H_BP;
	reg [9:0] H_sync;
	reg [9:0] H_VldDat;
	reg [9:0] COLUMNS;
	reg [9:0] V_FP;
	reg [9:0] V_BP;
	reg [9:0] V_sync;
	reg [9:0] V_VldDat;
	reg [9:0] LINES;
	reg H_active;
	reg V_active;
	

	reg [10:0] column;
	reg [10:0] line;
	reg DataEnable;
	reg [4:0] add_op;
	reg [23:0] pixs;
	reg temp_col;
	reg video_ACK;
	

	symulation_main uut (
		.rst_Chrontel_o(rst_Chrontel_o), 
		.dvi_d_o(dvi_d_o), 
		.x_clk_p_o(x_clk_p_o), 
		.x_clk_n_o(x_clk_n_o), 
		.dvi_de_o(dvi_de_o), 
		.dvi_hsync_o(dvi_hsync_o), 
		.dvi_vsync_o(dvi_vsync_o), 
		.ad_dataclk_i(ad_dataclk_i), 
		.ad_hsync_i(ad_hsync_i), 
		.ad_vsync_i(ad_vsync_i), 
		.ad_red_i(ad_red_i), 
		.ad_green_i(ad_green_i), 
		.ad_blue_i(ad_blue_i), 
		.Bus2IP_Clk(Bus2IP_Clk), 
		.Bus2IP_Reset(Bus2IP_Reset), 
		.column_max(column_max), 
		.line_max(line_max)
	);

	initial begin

		ad_dataclk_i = 0;
		ad_hsync_i = 0;
		ad_vsync_i = 0;
		ad_red_i = 0;
		ad_green_i = 0;
		ad_blue_i = 0;
		Bus2IP_Clk = 0;
		Bus2IP_Reset = 1;
		H_FP = 16;
		H_BP = 120;
		H_sync = 64;
		H_VldDat = 640;
		COLUMNS = H_FP+H_BP+H_sync+H_VldDat;
		V_FP = 1;
		V_BP = 16;
		V_sync = 3;
		V_VldDat = 480;
		LINES = V_FP+V_BP+V_sync+V_VldDat;
		H_active = 0;
		V_active = 0;
		DataEnable=0;
		video_ACK=0;
		
		#100;
      Bus2IP_Reset = 0;
		#1000 video_ACK=1;
		
	end
	
	always #1   Bus2IP_Clk=~Bus2IP_Clk;
	always #2	ad_dataclk_i=~ad_dataclk_i;
	
	always @(posedge ad_dataclk_i or posedge Bus2IP_Reset)
	begin
		if(Bus2IP_Reset)
		begin
			column<=0;
			line<=0;
			temp_col<=0;
		end
		else
		begin
			if(video_ACK)
			begin
				if(line<LINES)
				begin
					if(column<COLUMNS)
					begin
						column<=column+1'b1;
					end
					else
					begin
						line<=line+1'b1;
						column<=0;
					end	
				end
				else 
				begin
					line<=0;
					column<=0;	
				end	
			end		
		end
	end

	always @(negedge ad_dataclk_i or posedge Bus2IP_Reset)
	begin
		if(Bus2IP_Reset)
		begin
			ad_hsync_i<=1'b1;
			ad_vsync_i<=1'b1;
			DataEnable<=1'b0;
			ad_red_i<=0;
			ad_green_i<=0;
			ad_blue_i<=0;
			add_op<=1;
			pixs=0;
		end
		else
		begin
			if(video_ACK)
			begin
				if(DataEnable)
				begin
					pixs=24'hCF4F4F;
					ad_red_i<=pixs[23:16];
					ad_green_i<=pixs[15:8];
					ad_blue_i<=pixs[7:0];
				end
				else
				begin
					ad_red_i<=0;
					ad_green_i<=0;
					ad_blue_i<=0;
					pixs=0;
				end	
				
				if(line >(V_FP-1+ V_sync+V_BP))
				begin
					if(column>(H_FP+H_BP+H_sync))	DataEnable<=1'b1;
					else DataEnable<=1'b0;	
				end
				else DataEnable<=1'b0;
				
				if(column>(H_FP-1) && column<(H_FP+H_sync) ) 
				begin
					ad_hsync_i<=1'b0;
					
				end
				else ad_hsync_i<=1'b1;	
				
				if(line>(V_FP-1) && line<(V_FP+V_sync)) 
				begin
					ad_vsync_i<=1'b0; 
					add_op<=add_op+1'b1;
				end	
				else ad_vsync_i<=1'b1;
			end	
		end
	end
endmodule