data/full_repos/permissive/143278/ivltests/shiftl.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/shiftl.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/shiftl.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/shiftl.v:32: Operator SHIFTL expects 2 bits on the LHS, but LHS\'s VARREF \'a\' generates 1 bits.\n                                                                      : ... In instance main.dut\n    c <= (a << 1) | b;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/shiftl.v:32: Operator OR expects 2 bits on the RHS, but RHS\'s VARREF \'b\' generates 1 bits.\n                                                                      : ... In instance main.dut\n    c <= (a << 1) | b;\n                  ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test (clk,c,a,b);
input clk;
input a, b;
output [1:0] c;
reg [1:0] c;

(* ivl_synthesis_on *)
always @(posedge clk)
    c <= (a << 1) | b;

endmodule
module test (clk,c,a,b);

input clk;
input a, b;
output [1:0] c;
reg [1:0] c;

(* ivl_synthesis_on *)
always @(posedge clk)
    c <= (a << 1) | b;

endmodule