data/full_repos/permissive/219943485/clk_div.v
data/verilator_xmls/02fb87b5-c43c-43b7-a3fe-f5b22701b72c.xml
module clk_div(rst_n, clk_100mhz, clk_25mhz, clk_100hz);
  input rst_n, clk_100mhz;
  output clk_25mhz, clk_100hz;
  
  parameter DIV_CNT_100Hz =  19'b1111010000100011111;
  
  reg clk_25mhz, clk_100hz;
  reg cnt_25mhz;  
  reg[18:0] cnt_100hz;






always @(posedge clk_100mhz or negedge rst_n)
  if(!rst_n)
    cnt_25mhz <= 1'b0;
  else if(cnt_25mhz == 1'b1)
    cnt_25mhz <= 1'b0;
  else
    cnt_25mhz <= cnt_25mhz + 1'b1;






always @(posedge clk_100mhz or negedge rst_n)
  if(!rst_n)
    clk_25mhz <= 0;
  else if(cnt_25mhz == 1'b1)
    clk_25mhz <= !clk_25mhz;
    





always @(posedge clk_100mhz or negedge rst_n) 
  if(!rst_n)
    cnt_100hz <= 19'b0;
  else if(cnt_100hz == DIV_CNT_100Hz)
    cnt_100hz <= 19'b0;
  else
    cnt_100hz <= cnt_100hz + 1'b1;






always @(posedge clk_100mhz or negedge rst_n)
  if(!rst_n)
    clk_100hz <= 0;
  else if(cnt_100hz == DIV_CNT_100Hz)
    clk_100hz <= !clk_100hz;

endmodule
module clk_div(rst_n, clk_100mhz, clk_25mhz, clk_100hz);

  input rst_n, clk_100mhz;
  output clk_25mhz, clk_100hz;
  
  parameter DIV_CNT_100Hz =  19'b1111010000100011111;
  
  reg clk_25mhz, clk_100hz;
  reg cnt_25mhz;  
  reg[18:0] cnt_100hz;






always @(posedge clk_100mhz or negedge rst_n)
  if(!rst_n)
    cnt_25mhz <= 1'b0;
  else if(cnt_25mhz == 1'b1)
    cnt_25mhz <= 1'b0;
  else
    cnt_25mhz <= cnt_25mhz + 1'b1;






always @(posedge clk_100mhz or negedge rst_n)
  if(!rst_n)
    clk_25mhz <= 0;
  else if(cnt_25mhz == 1'b1)
    clk_25mhz <= !clk_25mhz;
    





always @(posedge clk_100mhz or negedge rst_n) 
  if(!rst_n)
    cnt_100hz <= 19'b0;
  else if(cnt_100hz == DIV_CNT_100Hz)
    cnt_100hz <= 19'b0;
  else
    cnt_100hz <= cnt_100hz + 1'b1;






always @(posedge clk_100mhz or negedge rst_n)
  if(!rst_n)
    clk_100hz <= 0;
  else if(cnt_100hz == DIV_CNT_100Hz)
    clk_100hz <= !clk_100hz;

endmodule