data/full_repos/permissive/108908995/test_fnet.v
 line:29: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/108908995/test_fnet.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108908995/test_fnet.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 $display("%h", out);\n ^\n%Error: data/full_repos/permissive/108908995/test_fnet.v:16: Cannot find file containing module: \'fnet\'\nfnet fnet (\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fnet\n             data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fnet.v\n             data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fnet.sv\n             fnet\n             fnet.v\n             fnet.sv\n             obj_dir/fnet\n             obj_dir/fnet.v\n             obj_dir/fnet.sv\n%Error: data/full_repos/permissive/108908995/test_fnet.v:22: Cannot find file containing module: \'ifnet\'\nifnet ifnet (\n^~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

reg clk;

initial 
    clk = 1'b0;

always
    #1 clk = ~clk;

wire [63:0]in = 64'hDEADBEEFBAADF00D;
wire [255:0]key = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100;
wire [63:0]out;
wire [63:0]i_out;

fnet fnet (
    .IN(in),
    .KEY(key),
    .OUT(out)
);

ifnet ifnet (
    .IN(out),
    .KEY(key),
    .OUT(i_out)
);

initial begin
	#1 $display("%h", out);
	$display("%h", i_out);
    
    if (in == i_out)
        $display("[PASSED]");
    else 
        $display("[FAILED]");
    
    $finish;
end

endmodule
module top;


reg clk;

initial 
    clk = 1'b0;

always
    #1 clk = ~clk;

wire [63:0]in = 64'hDEADBEEFBAADF00D;
wire [255:0]key = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100;
wire [63:0]out;
wire [63:0]i_out;

fnet fnet (
    .IN(in),
    .KEY(key),
    .OUT(out)
);

ifnet ifnet (
    .IN(out),
    .KEY(key),
    .OUT(i_out)
);

initial begin
	#1 $display("%h", out);
	$display("%h", i_out);
    
    if (in == i_out)
        $display("[PASSED]");
    else 
        $display("[FAILED]");
    
    $finish;
end

endmodule