data/full_repos/permissive/168753118/rtl/misc/REG.v
data/verilator_xmls/96980e9a-acf4-40c1-b134-7632144ca55f.xml
module REG #(parameter DATA_WIDTH=32)(

    input clock_in,
    input reset_in,


    input set_in,


    input [DATA_WIDTH-1:0] data_in,


    output [DATA_WIDTH-1:0] data_out
  );


  reg [DATA_WIDTH-1:0] general_register_signal_reg;
  reg [DATA_WIDTH-1:0] general_register_data_reg;


  always @ ( * )
    begin
      if (set_in == 1'b1)
        general_register_signal_reg = data_in;
      else
        general_register_signal_reg = general_register_data_reg;
    end


  always @ (posedge clock_in, posedge reset_in)
    begin
      if (reset_in == 1'b1)
        general_register_data_reg <= 0;
      else
        general_register_data_reg <= general_register_signal_reg;
    end


  assign data_out = general_register_data_reg;

endmodule
module REG #(parameter DATA_WIDTH=32)(

    input clock_in,
    input reset_in,


    input set_in,


    input [DATA_WIDTH-1:0] data_in,


    output [DATA_WIDTH-1:0] data_out
  );



  reg [DATA_WIDTH-1:0] general_register_signal_reg;
  reg [DATA_WIDTH-1:0] general_register_data_reg;


  always @ ( * )
    begin
      if (set_in == 1'b1)
        general_register_signal_reg = data_in;
      else
        general_register_signal_reg = general_register_data_reg;
    end


  always @ (posedge clock_in, posedge reset_in)
    begin
      if (reset_in == 1'b1)
        general_register_data_reg <= 0;
      else
        general_register_data_reg <= general_register_signal_reg;
    end


  assign data_out = general_register_data_reg;

endmodule