data/full_repos/permissive/206670486/Modulos/PC.v
 line:15: before: "reset"
data/verilator_xmls/a11e2849-8ffd-4670-b9b3-9e2eebfb092a.xml
module Pipeline_PC (entrada,saida,clk,reset,PC_Freeze);
  input[31:0]entrada;
  input clk,reset,PC_Freeze;
  output reg[31:0] saida;

  always @ ( posedge clk or reset ) begin
    if(reset)begin
      saida <= 32'b0;
    end
    else begin
      saida = (PC_Freeze == 0) ? entrada : saida;
    end
  end

endmodule
module Pipeline_PC (entrada,saida,clk,reset,PC_Freeze);

  input[31:0]entrada;
  input clk,reset,PC_Freeze;
  output reg[31:0] saida;

  always @ ( posedge clk or reset ) begin
    if(reset)begin
      saida <= 32'b0;
    end
    else begin
      saida = (PC_Freeze == 0) ? entrada : saida;
    end
  end

endmodule