data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_len.v
1: b'%Error: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_len.v:83: Cannot find file containing module: \'jelly_pipeline_insert_ff\'\n        jelly_pipeline_insert_ff\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/legacy,data/full_repos/permissive/2084115/jelly_pipeline_insert_ff\n             data/full_repos/permissive/2084115/rtl/legacy,data/full_repos/permissive/2084115/jelly_pipeline_insert_ff.v\n             data/full_repos/permissive/2084115/rtl/legacy,data/full_repos/permissive/2084115/jelly_pipeline_insert_ff.sv\n             jelly_pipeline_insert_ff\n             jelly_pipeline_insert_ff.v\n             jelly_pipeline_insert_ff.sv\n             obj_dir/jelly_pipeline_insert_ff\n             obj_dir/jelly_pipeline_insert_ff.v\n             obj_dir/jelly_pipeline_insert_ff.sv\n%Error: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_len.v:107: Cannot find file containing module: \'jelly_pipeline_insert_ff\'\n        jelly_pipeline_insert_ff\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_len.v:160: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'ff_s_len\' generates 24 bits.\n                                                                                      : ... In instance jelly_axi_addr_len\n                    reg_len       <= ff_s_len;\n                                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_len.v:166: Operator SUB expects 24 bits on the RHS, but RHS\'s VARREF \'param_len_max\' generates 8 bits.\n                                                                                      : ... In instance jelly_axi_addr_len\n                        reg_len_count <= ff_s_len - param_len_max - 1\'b1;\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_len.v:163: Operator GT expects 24 bits on the RHS, but RHS\'s VARREF \'param_len_max\' generates 8 bits.\n                                                                                      : ... In instance jelly_axi_addr_len\n                    if ( ff_s_valid && (ff_s_len > param_len_max) ) begin\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_len.v:171: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'reg_len\' generates 8 bits.\n                                                                                      : ... In instance jelly_axi_addr_len\n                    reg_addr  <= reg_addr + ((reg_len + 1\'b1) << DATA_SIZE);\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_len.v:173: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg_len_count\' generates 24 bits.\n                                                                                      : ... In instance jelly_axi_addr_len\n                    reg_len   <= reg_len_count;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_len.v:178: Operator SUB expects 24 bits on the RHS, but RHS\'s VARREF \'param_len_max\' generates 8 bits.\n                                                                                      : ... In instance jelly_axi_addr_len\n                        reg_len_count <= reg_len_count - param_len_max - 1\'b1;\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_len.v:175: Operator GT expects 24 bits on the RHS, but RHS\'s VARREF \'param_len_max\' generates 8 bits.\n                                                                                      : ... In instance jelly_axi_addr_len\n                    if ( reg_len_count > param_len_max ) begin\n                                       ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n'
module jelly_axi_addr_len
        #(
            parameter   BYPASS        = 0,
            parameter   USER_WIDTH    = 0,
            parameter   DATA_SIZE     = 3,
            parameter   ADDR_WIDTH    = 32,
            parameter   S_LEN_WIDTH   = 24,
            parameter   M_LEN_WIDTH   = 8,
            parameter   S_SLAVE_REGS  = 1,
            parameter   S_MASTER_REGS = 1,
            parameter   M_SLAVE_REGS  = 1,
            parameter   M_MASTER_REGS = 1,
            

            parameter   USER_BITS     = USER_WIDTH > 0 ? USER_WIDTH : 1
        )
        (
            input   wire                        aresetn,
            input   wire                        aclk,
            input   wire                        aclken,
            
            output  wire                        busy,
            
            input   wire    [M_LEN_WIDTH-1:0]   param_len_max,
            
            input   wire    [USER_BITS-1:0]     s_user,
            input   wire    [ADDR_WIDTH-1:0]    s_addr,
            input   wire    [S_LEN_WIDTH-1:0]   s_len,
            input   wire                        s_valid,
            output  wire                        s_ready,
            
            output  wire    [USER_BITS-1:0]     m_user,
            output  wire    [ADDR_WIDTH-1:0]    m_addr,
            output  wire    [M_LEN_WIDTH-1:0]   m_len,
            output  wire                        m_valid,
            input   wire                        m_ready
        );
    
    
    generate
    if ( BYPASS ) begin : blk_bypass
        assign  m_user  = s_user;
        assign  m_addr  = s_addr;
        assign  m_len   = s_len;
        assign  m_valid = s_valid;
        assign  s_ready = m_ready;
        
        assign  busy    = 1'b0;
    end
    else begin : blk_split
        



        
        wire    [USER_BITS-1:0]     ff_s_user;
        wire    [ADDR_WIDTH-1:0]    ff_s_addr;
        wire    [S_LEN_WIDTH-1:0]   ff_s_len;
        wire                        ff_s_valid;
        wire                        ff_s_ready;
        
        wire    [USER_BITS-1:0]     ff_m_user;
        wire    [ADDR_WIDTH-1:0]    ff_m_addr;
        wire    [M_LEN_WIDTH-1:0]   ff_m_len;
        wire                        ff_m_valid;
        wire                        ff_m_ready;
        
        jelly_pipeline_insert_ff
                #(
                    .DATA_WIDTH         (USER_BITS+ADDR_WIDTH+S_LEN_WIDTH),
                    .SLAVE_REGS         (S_SLAVE_REGS),
                    .MASTER_REGS        (S_MASTER_REGS)
                )
            i_pipeline_insert_ff_s
                (
                    .reset              (~aresetn),
                    .clk                (aclk),
                    .cke                (aclken),
                    
                    .s_data             ({s_user, s_addr, s_len}),
                    .s_valid            (s_valid),
                    .s_ready            (s_ready),
                    
                    .m_data             ({ff_s_user, ff_s_addr, ff_s_len}),
                    .m_valid            (ff_s_valid),
                    .m_ready            (ff_s_ready),
                    
                    .buffered           (),
                    .s_ready_next       ()
                );
        
        jelly_pipeline_insert_ff
                #(
                    .DATA_WIDTH         (USER_BITS+ADDR_WIDTH+M_LEN_WIDTH),
                    .SLAVE_REGS         (M_SLAVE_REGS),
                    .MASTER_REGS        (0)
                )
            i_pipeline_insert_ff_m
                (
                    .reset              (~aresetn),
                    .clk                (aclk),
                    .cke                (aclken),
                    
                    .s_data             ({ff_m_user, ff_m_addr, ff_m_len}),
                    .s_valid            (ff_m_valid),
                    .s_ready            (ff_m_ready),
                    
                    .m_data             ({m_user, m_addr, m_len}),
                    .m_valid            (m_valid),
                    .m_ready            (m_ready),
                    
                    .buffered           (),
                    .s_ready_next       ()
                );
        
        
        



        
        wire                        cke        = aclken && (!ff_m_valid || ff_m_ready);
        
        reg                         reg_split;
        reg     [USER_BITS-1:0]     reg_user;
        reg     [ADDR_WIDTH-1:0]    reg_addr;
        reg     [M_LEN_WIDTH-1:0]   reg_len;
        reg     [S_LEN_WIDTH-1:0]   reg_len_count;
        reg                         reg_valid;
        
        always @(posedge aclk) begin
            if ( ~aresetn ) begin
                reg_split     <= 1'b0;
                reg_user      <= {USER_BITS{1'bx}};
                reg_addr      <= {ADDR_WIDTH{1'bx}};
                reg_len       <= {M_LEN_WIDTH{1'bx}};
                reg_len_count <= {S_LEN_WIDTH{1'bx}};
                reg_valid     <= 1'b0;
            end
            else if ( cke ) begin
                reg_valid <= 1'b0;
                if ( !reg_split ) begin
                    reg_user      <= ff_s_user;
                    reg_addr      <= ff_s_addr;
                    reg_len       <= ff_s_len;
                    reg_len_count <= {S_LEN_WIDTH{1'bx}};
                    reg_valid     <= ff_s_valid;
                    if ( ff_s_valid && (ff_s_len > param_len_max) ) begin
                        reg_split     <= 1'b1;
                        reg_len       <= param_len_max;
                        reg_len_count <= ff_s_len - param_len_max - 1'b1;
                    end
                end
                else begin
                    reg_split <= 1'b0;
                    reg_addr  <= reg_addr + ((reg_len + 1'b1) << DATA_SIZE);

                    reg_len   <= reg_len_count;
                    reg_valid <= 1'b1;
                    if ( reg_len_count > param_len_max ) begin
                        reg_split     <= 1'b1;
                        reg_len       <= param_len_max;
                        reg_len_count <= reg_len_count - param_len_max - 1'b1;
                        reg_valid     <= 1'b1;
                    end
                end
            end
        end
        
        assign ff_m_user  = reg_user;
        assign ff_m_addr  = reg_addr;
        assign ff_m_len   = reg_len;
        assign ff_m_valid = reg_valid;
        
        assign ff_s_ready = (cke && ~reg_split);
        
        assign busy       = (ff_s_valid || reg_valid);
    end
    endgenerate
    
    
endmodule
module jelly_axi_addr_len
        #(
            parameter   BYPASS        = 0,
            parameter   USER_WIDTH    = 0,
            parameter   DATA_SIZE     = 3,
            parameter   ADDR_WIDTH    = 32,
            parameter   S_LEN_WIDTH   = 24,
            parameter   M_LEN_WIDTH   = 8,
            parameter   S_SLAVE_REGS  = 1,
            parameter   S_MASTER_REGS = 1,
            parameter   M_SLAVE_REGS  = 1,
            parameter   M_MASTER_REGS = 1,
            

            parameter   USER_BITS     = USER_WIDTH > 0 ? USER_WIDTH : 1
        )
        (
            input   wire                        aresetn,
            input   wire                        aclk,
            input   wire                        aclken,
            
            output  wire                        busy,
            
            input   wire    [M_LEN_WIDTH-1:0]   param_len_max,
            
            input   wire    [USER_BITS-1:0]     s_user,
            input   wire    [ADDR_WIDTH-1:0]    s_addr,
            input   wire    [S_LEN_WIDTH-1:0]   s_len,
            input   wire                        s_valid,
            output  wire                        s_ready,
            
            output  wire    [USER_BITS-1:0]     m_user,
            output  wire    [ADDR_WIDTH-1:0]    m_addr,
            output  wire    [M_LEN_WIDTH-1:0]   m_len,
            output  wire                        m_valid,
            input   wire                        m_ready
        );

    
    
    generate
    if ( BYPASS ) begin : blk_bypass
        assign  m_user  = s_user;
        assign  m_addr  = s_addr;
        assign  m_len   = s_len;
        assign  m_valid = s_valid;
        assign  s_ready = m_ready;
        
        assign  busy    = 1'b0;
    end
    else begin : blk_split
        



        
        wire    [USER_BITS-1:0]     ff_s_user;
        wire    [ADDR_WIDTH-1:0]    ff_s_addr;
        wire    [S_LEN_WIDTH-1:0]   ff_s_len;
        wire                        ff_s_valid;
        wire                        ff_s_ready;
        
        wire    [USER_BITS-1:0]     ff_m_user;
        wire    [ADDR_WIDTH-1:0]    ff_m_addr;
        wire    [M_LEN_WIDTH-1:0]   ff_m_len;
        wire                        ff_m_valid;
        wire                        ff_m_ready;
        
        jelly_pipeline_insert_ff
                #(
                    .DATA_WIDTH         (USER_BITS+ADDR_WIDTH+S_LEN_WIDTH),
                    .SLAVE_REGS         (S_SLAVE_REGS),
                    .MASTER_REGS        (S_MASTER_REGS)
                )
            i_pipeline_insert_ff_s
                (
                    .reset              (~aresetn),
                    .clk                (aclk),
                    .cke                (aclken),
                    
                    .s_data             ({s_user, s_addr, s_len}),
                    .s_valid            (s_valid),
                    .s_ready            (s_ready),
                    
                    .m_data             ({ff_s_user, ff_s_addr, ff_s_len}),
                    .m_valid            (ff_s_valid),
                    .m_ready            (ff_s_ready),
                    
                    .buffered           (),
                    .s_ready_next       ()
                );
        
        jelly_pipeline_insert_ff
                #(
                    .DATA_WIDTH         (USER_BITS+ADDR_WIDTH+M_LEN_WIDTH),
                    .SLAVE_REGS         (M_SLAVE_REGS),
                    .MASTER_REGS        (0)
                )
            i_pipeline_insert_ff_m
                (
                    .reset              (~aresetn),
                    .clk                (aclk),
                    .cke                (aclken),
                    
                    .s_data             ({ff_m_user, ff_m_addr, ff_m_len}),
                    .s_valid            (ff_m_valid),
                    .s_ready            (ff_m_ready),
                    
                    .m_data             ({m_user, m_addr, m_len}),
                    .m_valid            (m_valid),
                    .m_ready            (m_ready),
                    
                    .buffered           (),
                    .s_ready_next       ()
                );
        
        
        



        
        wire                        cke        = aclken && (!ff_m_valid || ff_m_ready);
        
        reg                         reg_split;
        reg     [USER_BITS-1:0]     reg_user;
        reg     [ADDR_WIDTH-1:0]    reg_addr;
        reg     [M_LEN_WIDTH-1:0]   reg_len;
        reg     [S_LEN_WIDTH-1:0]   reg_len_count;
        reg                         reg_valid;
        
        always @(posedge aclk) begin
            if ( ~aresetn ) begin
                reg_split     <= 1'b0;
                reg_user      <= {USER_BITS{1'bx}};
                reg_addr      <= {ADDR_WIDTH{1'bx}};
                reg_len       <= {M_LEN_WIDTH{1'bx}};
                reg_len_count <= {S_LEN_WIDTH{1'bx}};
                reg_valid     <= 1'b0;
            end
            else if ( cke ) begin
                reg_valid <= 1'b0;
                if ( !reg_split ) begin
                    reg_user      <= ff_s_user;
                    reg_addr      <= ff_s_addr;
                    reg_len       <= ff_s_len;
                    reg_len_count <= {S_LEN_WIDTH{1'bx}};
                    reg_valid     <= ff_s_valid;
                    if ( ff_s_valid && (ff_s_len > param_len_max) ) begin
                        reg_split     <= 1'b1;
                        reg_len       <= param_len_max;
                        reg_len_count <= ff_s_len - param_len_max - 1'b1;
                    end
                end
                else begin
                    reg_split <= 1'b0;
                    reg_addr  <= reg_addr + ((reg_len + 1'b1) << DATA_SIZE);

                    reg_len   <= reg_len_count;
                    reg_valid <= 1'b1;
                    if ( reg_len_count > param_len_max ) begin
                        reg_split     <= 1'b1;
                        reg_len       <= param_len_max;
                        reg_len_count <= reg_len_count - param_len_max - 1'b1;
                        reg_valid     <= 1'b1;
                    end
                end
            end
        end
        
        assign ff_m_user  = reg_user;
        assign ff_m_addr  = reg_addr;
        assign ff_m_len   = reg_len;
        assign ff_m_valid = reg_valid;
        
        assign ff_s_ready = (cke && ~reg_split);
        
        assign busy       = (ff_s_valid || reg_valid);
    end
    endgenerate
    
    
endmodule