data/full_repos/permissive/132377858/transposed_convolution_test.srcs/sim_1/new/testbench.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/132377858/transposed_convolution_test.srcs/sim_1/new/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #(T/2);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/132377858/transposed_convolution_test.srcs/sim_1/new/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #(T/2);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/132377858/transposed_convolution_test.srcs/sim_1/new/testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n#(T/2);\n^\n%Error: data/full_repos/permissive/132377858/transposed_convolution_test.srcs/sim_1/new/testbench.v:56: syntax error, unexpected \'@\'\n    @(negedge  reset);\n    ^\n%Error: data/full_repos/permissive/132377858/transposed_convolution_test.srcs/sim_1/new/testbench.v:60: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: data/full_repos/permissive/132377858/transposed_convolution_test.srcs/sim_1/new/testbench.v:62: Unsupported: wait statements\n    wait(done_tick);\n    ^~~~\n%Error: data/full_repos/permissive/132377858/transposed_convolution_test.srcs/sim_1/new/testbench.v:64: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

localparam T = 10;

reg clk, reset;
wire we;
wire [15:0] addr_a, addr_b, addr_c;
reg [15:0] addr_result;
wire [7:0] a, b;
wire [31:0] c, cw, result;
wire done_tick;
reg btn_tick;

bram #(.ADDR_WIDTH(16), .DATA_WIDTH(8), .DATA_FILE("input_1_uint8.data")) bram_lhs
    (.clk(clk), .we(1'b0), .addr_a(addr_a), .addr_b(16'd0), .din_a(8'd0), .dout_a(a), .dout_b());

bram #(.ADDR_WIDTH(16), .DATA_WIDTH(8), .DATA_FILE("weight_1_uint8.data")) bram_rhs
    (.clk(clk), .we(1'b0), .addr_a(16'd0), .addr_b(addr_b), .din_a(8'd0), .dout_a(), .dout_b(b));

bram #(.ADDR_WIDTH(16), .DATA_WIDTH(32)) bram_res
        (.clk(clk), .we(we), .addr_a(addr_c), .addr_b(addr_result), .din_a(cw), .dout_a(c), .dout_b(result));

sparse_gemm mm_unit
    (.clk(clk), .reset(reset), .start_tick(btn_tick), .m(14'd9), .k(14'd2), .n(14'd4),
     .n_output_plane(10'd1), .output_h(7'd4), .output_w(7'd4), .input_h(7'd3), .input_w(7'd3),
     .kernel_h(3'd2), .kernel_w(3'd2), .pad_h(3'd1), .pad_w(3'd1),
     .stride_h(3'd2), .stride_w(3'd2), .dilation_h(3'd1), .dilation_w(3'd1), .a(a), .b(b), .c(c),
     .a_rd_addr(addr_a), .b_rd_addr(addr_b), .c_rw_addr(addr_c), .c_out(cw), .c_wr_en(we), .done_tick(done_tick));

always
begin
    clk = 1'b1;
    #(T/2);
    clk = 1'b0;
    #(T/2);
end


initial
begin
reset = 1'b1;
#(T/2);
reset = 1'b0;
end


integer i;
initial
begin

    addr_result = 16'hffff;
    btn_tick = 1'b0;

    @(negedge  reset);

    @(negedge clk);
    btn_tick = 1'b1;
    @(negedge clk);
    btn_tick = 1'b0;
    wait(done_tick);
    for (i = 0; i < 16; i = i+1) begin
        @(negedge clk);
        addr_result = addr_result + 1;
    end
end

endmodule
module testbench();


localparam T = 10;

reg clk, reset;
wire we;
wire [15:0] addr_a, addr_b, addr_c;
reg [15:0] addr_result;
wire [7:0] a, b;
wire [31:0] c, cw, result;
wire done_tick;
reg btn_tick;

bram #(.ADDR_WIDTH(16), .DATA_WIDTH(8), .DATA_FILE("input_1_uint8.data")) bram_lhs
    (.clk(clk), .we(1'b0), .addr_a(addr_a), .addr_b(16'd0), .din_a(8'd0), .dout_a(a), .dout_b());

bram #(.ADDR_WIDTH(16), .DATA_WIDTH(8), .DATA_FILE("weight_1_uint8.data")) bram_rhs
    (.clk(clk), .we(1'b0), .addr_a(16'd0), .addr_b(addr_b), .din_a(8'd0), .dout_a(), .dout_b(b));

bram #(.ADDR_WIDTH(16), .DATA_WIDTH(32)) bram_res
        (.clk(clk), .we(we), .addr_a(addr_c), .addr_b(addr_result), .din_a(cw), .dout_a(c), .dout_b(result));

sparse_gemm mm_unit
    (.clk(clk), .reset(reset), .start_tick(btn_tick), .m(14'd9), .k(14'd2), .n(14'd4),
     .n_output_plane(10'd1), .output_h(7'd4), .output_w(7'd4), .input_h(7'd3), .input_w(7'd3),
     .kernel_h(3'd2), .kernel_w(3'd2), .pad_h(3'd1), .pad_w(3'd1),
     .stride_h(3'd2), .stride_w(3'd2), .dilation_h(3'd1), .dilation_w(3'd1), .a(a), .b(b), .c(c),
     .a_rd_addr(addr_a), .b_rd_addr(addr_b), .c_rw_addr(addr_c), .c_out(cw), .c_wr_en(we), .done_tick(done_tick));

always
begin
    clk = 1'b1;
    #(T/2);
    clk = 1'b0;
    #(T/2);
end


initial
begin
reset = 1'b1;
#(T/2);
reset = 1'b0;
end


integer i;
initial
begin

    addr_result = 16'hffff;
    btn_tick = 1'b0;

    @(negedge  reset);

    @(negedge clk);
    btn_tick = 1'b1;
    @(negedge clk);
    btn_tick = 1'b0;
    wait(done_tick);
    for (i = 0; i < 16; i = i+1) begin
        @(negedge clk);
        addr_result = addr_result + 1;
    end
end

endmodule