data/full_repos/permissive/132304455/src/fivexn_bit_mux.v
1: b"%Error: data/full_repos/permissive/132304455/src/fivexn_bit_mux.v:19: Cannot find file containing module: 'mux4v'\n    mux4v #(.width(width)) first_four(intermediate, in0, in1, in2, in3, sel[1:0]);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/132304455/src,data/full_repos/permissive/132304455/mux4v\n             data/full_repos/permissive/132304455/src,data/full_repos/permissive/132304455/mux4v.v\n             data/full_repos/permissive/132304455/src,data/full_repos/permissive/132304455/mux4v.sv\n             mux4v\n             mux4v.v\n             mux4v.sv\n             obj_dir/mux4v\n             obj_dir/mux4v.v\n             obj_dir/mux4v.sv\n%Error: data/full_repos/permissive/132304455/src/fivexn_bit_mux.v:20: Cannot find file containing module: 'mux2v'\n    mux2v  #(.width(width)) final_val(out, intermediate, in4, sel[2]);\n    ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module fivexn_bit_mux(out,
                      in0,
                      in1,
                      in2,
                      in3,
                      in4,
                      sel);

    parameter
        width = 1;

    output [(width - 1):0] out;
    input  [(width - 1):0] in0, in1, in2, in3, in4;
    input  [2:0]           sel;

    wire   [(width - 1):0] intermediate;

    mux4v #(.width(width)) first_four(intermediate, in0, in1, in2, in3, sel[1:0]);
    mux2v  #(.width(width)) final_val(out, intermediate, in4, sel[2]);

endmodule
module fivexn_bit_mux(out,
                      in0,
                      in1,
                      in2,
                      in3,
                      in4,
                      sel);


    parameter
        width = 1;

    output [(width - 1):0] out;
    input  [(width - 1):0] in0, in1, in2, in3, in4;
    input  [2:0]           sel;

    wire   [(width - 1):0] intermediate;

    mux4v #(.width(width)) first_four(intermediate, in0, in1, in2, in3, sel[1:0]);
    mux2v  #(.width(width)) final_val(out, intermediate, in4, sel[2]);

endmodule