data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0403/lab0403.srcs/sim_1/new/signext_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0403/lab0403.srcs/sim_1/new/signext_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0403/lab0403.srcs/sim_1/new/signext_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0403/lab0403.srcs/sim_1/new/signext_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0403/lab0403.srcs/sim_1/new/signext_tb.v:28: Cannot find file containing module: \'signext\'\nsignext u0(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0403/lab0403.srcs/sim_1/new,data/full_repos/permissive/194376374/signext\n             data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0403/lab0403.srcs/sim_1/new,data/full_repos/permissive/194376374/signext.v\n             data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0403/lab0403.srcs/sim_1/new,data/full_repos/permissive/194376374/signext.sv\n             signext\n             signext.v\n             signext.sv\n             obj_dir/signext\n             obj_dir/signext.v\n             obj_dir/signext.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module signext_tb();

reg [15:0] inst;
wire [31:0] data;

signext u0(
    .inst(inst),
    .data(data)
);

initial begin
    inst=16'hffff;
    #100;
    inst=16'h0000;
    #100;
    inst=16'h0233;
    #100;
end

endmodule
module signext_tb();


reg [15:0] inst;
wire [31:0] data;

signext u0(
    .inst(inst),
    .data(data)
);

initial begin
    inst=16'hffff;
    #100;
    inst=16'h0000;
    #100;
    inst=16'h0233;
    #100;
end

endmodule