data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v
 line:124: before: "$"
1: b'%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:28: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tests/registro32bits/test1.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:29: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, test1);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:45: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #0 modo = 2\'b10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #0 dir = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #0 s_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #0 d = 32\'h0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #4;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hffffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hfffffff0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hffffff00;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hfffff000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hffff0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hfff00000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hff000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hf0000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'h00000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hf0000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hff000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hfff00000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hffff0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hfffff000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hffffff00;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hfffffff0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'hffffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'b0001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'b0010;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'b0100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 32\'b1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #4 d = 32\'hffaebc13;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #4 s_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #4 modo = 2\'b00;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #100 s_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #0 dir = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #120 modo = 2\'b10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #4 d = 32\'haf00f050;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #4 dir = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:97: Unsupported: Ignoring delay on this delayed statement.\n    #4;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #4 modo = 2\'b01;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #120 modo = 2\'b10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #0 d = 32\'h000aa000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:102: Unsupported: Ignoring delay on this delayed statement.\n    #4 dir = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:103: Unsupported: Ignoring delay on this delayed statement.\n    #4;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #4 modo = 2\'b01;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #20 dir = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:110: Unsupported: Ignoring delay on this delayed statement.\n    #30 dir = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:112: Unsupported: Ignoring delay on this delayed statement.\n    #20 dir = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #30 dir = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:115: Unsupported: Ignoring delay on this delayed statement.\n    #20 dir = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:116: Unsupported: Ignoring delay on this delayed statement.\n    #30 dir = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:118: Unsupported: Ignoring delay on this delayed statement.\n    #20 dir = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:119: Unsupported: Ignoring delay on this delayed statement.\n    #30 dir = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:121: Unsupported: Ignoring delay on this delayed statement.\n    #20 dir = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:122: Unsupported: Ignoring delay on this delayed statement.\n    #30 dir = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:124: Unsupported: Ignoring delay on this delayed statement.\n    #120 $finish;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro32bits/test1.v:129: Unsupported or unknown PLI call: $monitor\n    $monitor(\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s), 53 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test1;
  initial begin
    $display("Test Bench 1 registro32bits");
    $display("Prueba la funcionalidad de carga en serie a la izquierda");
    $display("********************************************************");
    $dumpfile("tests/registro32bits/test1.vcd");
    $dumpvars(0, test1);
  end

  reg clk = 0;
  reg enb = 1;
  reg dir;
  reg s_in;

  reg [1:0] modo  = 2'b0;
  reg [31:0] d    = 4'h0;

  wire [31:0] q;
  wire s_out;

  registro32bits registro1(clk, enb, dir, s_in, modo, d, q, s_out);

  always #1 clk = ~clk;

  initial begin

    #0 modo = 2'b10;
    #0 dir = 0;
    #0 s_in = 1;
    #0 d = 32'h0;
    #4;


    #2 d = 32'hffffffff;
    #2 d = 32'hfffffff0;
    #2 d = 32'hffffff00;
    #2 d = 32'hfffff000;
    #2 d = 32'hffff0000;
    #2 d = 32'hfff00000;
    #2 d = 32'hff000000;
    #2 d = 32'hf0000000;
    #2 d = 32'h00000000;

    #2 d = 32'hf0000000;
    #2 d = 32'hff000000;
    #2 d = 32'hfff00000;
    #2 d = 32'hffff0000;
    #2 d = 32'hfffff000;
    #2 d = 32'hffffff00;
    #2 d = 32'hfffffff0;
    #2 d = 32'hffffffff;


    #2 d = 32'b0001;
    #2 d = 32'b0010;
    #2 d = 32'b0100;
    #2 d = 32'b1000;


    #4 d = 32'hffaebc13;



    #4 s_in = 0;
    #4 modo = 2'b00;


    #100 s_in = 1;
    #0 dir = 1;


    #120 modo = 2'b10;
    #4 d = 32'haf00f050;
    #4 dir = 0;
    #4;
    #4 modo = 2'b01;

    #120 modo = 2'b10;
    #0 d = 32'h000aa000;
    #4 dir = 0;
    #4;
    #4 modo = 2'b01;




    #20 dir = 1;
    #30 dir = 0;

    #20 dir = 1;
    #30 dir = 0;

    #20 dir = 1;
    #30 dir = 0;

    #20 dir = 1;
    #30 dir = 0;

    #20 dir = 1;
    #30 dir = 0;

    #120 $finish;
  end

  initial begin
    $display("\t\ttiempo  dir s_in modo d \t\t\t\tq \t\t\t\t  s_out\n");
    $monitor(
      "%d", $time,
      "\t%b   ", dir,
      "%b    ", s_in,
      "%2b   ", modo,
      "%4b\t", d,
      "%4b  ", q,
      "%b", s_out
    );
  end
endmodule
module test1;

  initial begin
    $display("Test Bench 1 registro32bits");
    $display("Prueba la funcionalidad de carga en serie a la izquierda");
    $display("********************************************************");
    $dumpfile("tests/registro32bits/test1.vcd");
    $dumpvars(0, test1);
  end

  reg clk = 0;
  reg enb = 1;
  reg dir;
  reg s_in;

  reg [1:0] modo  = 2'b0;
  reg [31:0] d    = 4'h0;

  wire [31:0] q;
  wire s_out;

  registro32bits registro1(clk, enb, dir, s_in, modo, d, q, s_out);

  always #1 clk = ~clk;

  initial begin

    #0 modo = 2'b10;
    #0 dir = 0;
    #0 s_in = 1;
    #0 d = 32'h0;
    #4;


    #2 d = 32'hffffffff;
    #2 d = 32'hfffffff0;
    #2 d = 32'hffffff00;
    #2 d = 32'hfffff000;
    #2 d = 32'hffff0000;
    #2 d = 32'hfff00000;
    #2 d = 32'hff000000;
    #2 d = 32'hf0000000;
    #2 d = 32'h00000000;

    #2 d = 32'hf0000000;
    #2 d = 32'hff000000;
    #2 d = 32'hfff00000;
    #2 d = 32'hffff0000;
    #2 d = 32'hfffff000;
    #2 d = 32'hffffff00;
    #2 d = 32'hfffffff0;
    #2 d = 32'hffffffff;


    #2 d = 32'b0001;
    #2 d = 32'b0010;
    #2 d = 32'b0100;
    #2 d = 32'b1000;


    #4 d = 32'hffaebc13;



    #4 s_in = 0;
    #4 modo = 2'b00;


    #100 s_in = 1;
    #0 dir = 1;


    #120 modo = 2'b10;
    #4 d = 32'haf00f050;
    #4 dir = 0;
    #4;
    #4 modo = 2'b01;

    #120 modo = 2'b10;
    #0 d = 32'h000aa000;
    #4 dir = 0;
    #4;
    #4 modo = 2'b01;




    #20 dir = 1;
    #30 dir = 0;

    #20 dir = 1;
    #30 dir = 0;

    #20 dir = 1;
    #30 dir = 0;

    #20 dir = 1;
    #30 dir = 0;

    #20 dir = 1;
    #30 dir = 0;

    #120 $finish;
  end

  initial begin
    $display("\t\ttiempo  dir s_in modo d \t\t\t\tq \t\t\t\t  s_out\n");
    $monitor(
      "%d", $time,
      "\t%b   ", dir,
      "%b    ", s_in,
      "%2b   ", modo,
      "%4b\t", d,
      "%4b  ", q,
      "%b", s_out
    );
  end
endmodule