data/full_repos/permissive/113654920/hdl/TF_Stub.v
1: b'%Warning-WIDTH: data/full_repos/permissive/113654920/hdl/TF_Stub.v:70: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                     : ... In instance TF_Stub\n TF_COUNT  <= 2\'b00;   \n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module TF_Stub(
		input	RESET,
		input	CLK4,

		inout TFD0,
		inout TFD1,
		inout TFD2,
		inout TFD3,
		output TF_CMD,
		output TF_CLK,
		input TF_SENSE
    );








reg TF_CLKSO;
reg [7:0] TF_COUNT;
wire TFD0i,TFD1i,TFD2i,TFD3i;
reg [3:0] TFDD;
wire TerminateCount;
wire FAST;




	assign TFD0	= (TF_SENSE == 1'b1) ? TFDD[0] : 1'bZ;
	assign TFD0i	= TFD0;
	assign TFD1	= (TF_SENSE == 1'b1) ? TFDD[1] : 1'bZ;
	assign TFD1i	= TFD1;
	assign TFD2	= (TF_SENSE == 1'b1) ? TFDD[2] : 1'bZ;
	assign TFD2i	= TFD2;
	assign TFD3	= (TF_SENSE == 1'b1) ? TFDD[3] : 1'bZ;
	assign TFD3i	= TFD3;
	assign TF_CLK	= (TF_SENSE == 1'b1) ? TF_CLKSO : 1'b0;
	assign TF_CMD	= (TF_SENSE == 1'b1) ? TFD0i ^ TFD1i ^ TFD2i ^ TFD3i : 1'b0;



	assign	FAST = TFD0i;
	assign	TerminateCount =	(FAST & TF_COUNT[1] & ~TF_COUNT[0] ) | 
										(TF_COUNT[7] & TF_COUNT[5] & TF_COUNT[4] & TF_COUNT[2] & TF_COUNT[1]);
always @(posedge CLK4)begin
if (RESET == 1'b1) begin

	TF_COUNT		<= 2'b00;
	TF_CLKSO		<= 1'b0;
	TFDD			<= 4'b0000;

end else begin
	TFDD	<= TFDD + 1;





	if (TerminateCount == 1'b1) begin
		TF_COUNT[7:0] 	<= 8'b0000_0000;
		TF_CLKSO			<= ~TF_CLKSO;
	end else begin
		TF_COUNT			<= TF_COUNT + 1;
	end
end
end

endmodule
module TF_Stub(
		input	RESET,
		input	CLK4,

		inout TFD0,
		inout TFD1,
		inout TFD2,
		inout TFD3,
		output TF_CMD,
		output TF_CLK,
		input TF_SENSE
    );









reg TF_CLKSO;
reg [7:0] TF_COUNT;
wire TFD0i,TFD1i,TFD2i,TFD3i;
reg [3:0] TFDD;
wire TerminateCount;
wire FAST;




	assign TFD0	= (TF_SENSE == 1'b1) ? TFDD[0] : 1'bZ;
	assign TFD0i	= TFD0;
	assign TFD1	= (TF_SENSE == 1'b1) ? TFDD[1] : 1'bZ;
	assign TFD1i	= TFD1;
	assign TFD2	= (TF_SENSE == 1'b1) ? TFDD[2] : 1'bZ;
	assign TFD2i	= TFD2;
	assign TFD3	= (TF_SENSE == 1'b1) ? TFDD[3] : 1'bZ;
	assign TFD3i	= TFD3;
	assign TF_CLK	= (TF_SENSE == 1'b1) ? TF_CLKSO : 1'b0;
	assign TF_CMD	= (TF_SENSE == 1'b1) ? TFD0i ^ TFD1i ^ TFD2i ^ TFD3i : 1'b0;



	assign	FAST = TFD0i;
	assign	TerminateCount =	(FAST & TF_COUNT[1] & ~TF_COUNT[0] ) | 
										(TF_COUNT[7] & TF_COUNT[5] & TF_COUNT[4] & TF_COUNT[2] & TF_COUNT[1]);
always @(posedge CLK4)begin
if (RESET == 1'b1) begin

	TF_COUNT		<= 2'b00;
	TF_CLKSO		<= 1'b0;
	TFDD			<= 4'b0000;

end else begin
	TFDD	<= TFDD + 1;





	if (TerminateCount == 1'b1) begin
		TF_COUNT[7:0] 	<= 8'b0000_0000;
		TF_CLKSO			<= ~TF_CLKSO;
	end else begin
		TF_COUNT			<= TF_COUNT + 1;
	end
end
end

endmodule