data/full_repos/permissive/201488448/2_circuits/2_sequential/fsm/23_2cmp_mealy.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/7c1ce6db-07b1-48ea-877f-a9180adc450c.xml
module top_module (
    input clk,
    input areset,
    input x,
    output z
); 

    parameter A=2'b01, B=2'b10;
    reg	[1:0] state, next_state;

    always@(*) begin
        case({state,x})
            {A, 1'b0}:	next_state = A;
            {A, 1'b1}:	next_state = B;
            {B, 1'b0}:	next_state = B;
            {B, 1'b1}:	next_state = B;
            default:	next_state = A;
        endcase
    end
    
    always@(posedge clk or posedge areset) begin
        if(areset)
            state <= A;
        else
            state <= next_state;
    end
    
    assign	z = (state==A)&(x) || (state==B)&(~x);
    
endmodule
module top_module (
    input clk,
    input areset,
    input x,
    output z
);
 

    parameter A=2'b01, B=2'b10;
    reg	[1:0] state, next_state;

    always@(*) begin
        case({state,x})
            {A, 1'b0}:	next_state = A;
            {A, 1'b1}:	next_state = B;
            {B, 1'b0}:	next_state = B;
            {B, 1'b1}:	next_state = B;
            default:	next_state = A;
        endcase
    end
    
    always@(posedge clk or posedge areset) begin
        if(areset)
            state <= A;
        else
            state <= next_state;
    end
    
    assign	z = (state==A)&(x) || (state==B)&(~x);
    
endmodule