data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v
 line:5: before: "localparam"
1: b'%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v:65: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'substate\' generates 4 bits.\n                                                                                          : ... In instance MCU_CTRL\n                        substate <= (substate == SUB-1) ? {clog2(SUB-1){1\'b0}} : substate + 1;\n                                              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v:90: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                          : ... In instance MCU_CTRL\n                o_memSelect = {(clog2(N+1) - 1){1\'b0}};\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v:100: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                           : ... In instance MCU_CTRL\n                o_memSelect = {(clog2(N+1) - 1){1\'b0}};\n                            ^\n%Error: Exiting due to 3 warning(s)\n'
function integer clog2;
        input integer depth;
        for (clog2=0; depth>0; clog2=clog2+1)
            depth = depth >> 1;
    endfunction
function integer clog2;

        input integer depth;
        for (clog2=0; depth>0; clog2=clog2+1)
            depth = depth >> 1;
    endfunction