data/full_repos/permissive/120834015/mimas_a7/test/uart/rtl/Top.sv
 line:1 column:1: Illegal character '\x00'
1: b"%Error: data/full_repos/permissive/120834015/mimas_a7/test/uart/rtl/Top.sv:13: Cannot find file containing module: 'SyncChain'\n    SyncChain #(.DEFAULT(1'b0)) reset_sync_chain(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120834015/mimas_a7/test/uart/rtl,data/full_repos/permissive/120834015/SyncChain\n             data/full_repos/permissive/120834015/mimas_a7/test/uart/rtl,data/full_repos/permissive/120834015/SyncChain.v\n             data/full_repos/permissive/120834015/mimas_a7/test/uart/rtl,data/full_repos/permissive/120834015/SyncChain.sv\n             SyncChain\n             SyncChain.v\n             SyncChain.sv\n             obj_dir/SyncChain\n             obj_dir/SyncChain.v\n             obj_dir/SyncChain.sv\n%Error: data/full_repos/permissive/120834015/mimas_a7/test/uart/rtl/Top.sv:22: Cannot find file containing module: 'SyncChain'\n    SyncChain #(.DEFAULT(1'b1)) rx_sync_chain(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/120834015/mimas_a7/test/uart/rtl/Top.sv:30: Cannot find file containing module: 'Uart'\n    Uart uart(\n    ^~~~\n%Error: Exiting due to 3 error(s)\n"
module Top(
    input wire logic reset,
    input wire logic clk,

    output wire logic tx,
    input wire logic rx,

    output wire logic led);

    logic reset_n;
    SyncChain #(.DEFAULT(1'b0)) reset_sync_chain(
        .reset_n(~reset),
        .clk(clk),

        .x(1'b1),

        .x_sync(reset_n));

    logic rx_sync;
    SyncChain #(.DEFAULT(1'b1)) rx_sync_chain(
        .reset_n(reset_n),
        .clk(clk),

        .x(rx),

        .x_sync(rx_sync));

    Uart uart(
        .reset_n(reset_n),
        .clk(clk),

        .tx(tx),
        .rx(rx_sync),

        .has_errored(led));

endmodule
module Top(
    input wire logic reset,
    input wire logic clk,

    output wire logic tx,
    input wire logic rx,

    output wire logic led);


    logic reset_n;
    SyncChain #(.DEFAULT(1'b0)) reset_sync_chain(
        .reset_n(~reset),
        .clk(clk),

        .x(1'b1),

        .x_sync(reset_n));

    logic rx_sync;
    SyncChain #(.DEFAULT(1'b1)) rx_sync_chain(
        .reset_n(reset_n),
        .clk(clk),

        .x(rx),

        .x_sync(rx_sync));

    Uart uart(
        .reset_n(reset_n),
        .clk(clk),

        .tx(tx),
        .rx(rx_sync),

        .has_errored(led));

endmodule