data/full_repos/permissive/119126104/myCPU/regfile_2r1w.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/119126104/myCPU/regfile_2r1w.v:28: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                               : ... Top module \'regfile_2r1w\'\nmodule regfile_2r1w(\n       ^~~~~~~~~~~~\n                                                                               : ... Top module \'reg_HILO\'\nmodule reg_HILO(\n       ^~~~~~~~\n                                                                               : ... Top module \'reg_CP0\'\nmodule reg_CP0(\n       ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module regfile_2r1w(
    input         clk,

    input  [ 4:0] ra1,
    output [31:0] rd1,

    input  [ 4:0] ra2,
    output [31:0] rd2,

    input         we1,
    input  [ 4:0] wa1,
    input  [31:0] wd1
);

reg  [31:0] heap [31:0];

assign rd1 = (|ra1) ? heap[ra1] : 32'd0;
assign rd2 = (|ra2) ? heap[ra2] : 32'd0;

always @(posedge clk)
    if (we1)
        heap[wa1] <= wd1;

endmodule
module regfile_2r1w(
    input         clk,

    input  [ 4:0] ra1,
    output [31:0] rd1,

    input  [ 4:0] ra2,
    output [31:0] rd2,

    input         we1,
    input  [ 4:0] wa1,
    input  [31:0] wd1
);


reg  [31:0] heap [31:0];

assign rd1 = (|ra1) ? heap[ra1] : 32'd0;
assign rd2 = (|ra2) ? heap[ra2] : 32'd0;

always @(posedge clk)
    if (we1)
        heap[wa1] <= wd1;

endmodule