data/full_repos/permissive/219219909/Complex_Multiplier/align_1.v
data/verilator_xmls/830eabee-bf3f-4be0-b566-2accf9b625b0.xml
module align_1(
    input [7:0] BE,
    input [7:0] AE,
	 output reg [7:0] d
    );
	 
always @(AE,BE) begin
if (AE>BE) begin
d=AE-BE;
end
else if (AE<BE) begin
d=BE-AE;
end
else begin
d=8'b0;
end
end
endmodule
module align_1(
    input [7:0] BE,
    input [7:0] AE,
	 output reg [7:0] d
    );

	 
always @(AE,BE) begin
if (AE>BE) begin
d=AE-BE;
end
else if (AE<BE) begin
d=BE-AE;
end
else begin
d=8'b0;
end
end
endmodule