data/full_repos/permissive/16591284/fifo_design_collection/vivado/top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/16591284/fifo_design_collection/vivado/top.v:34: Cannot find file containing module: 'BFIFO'\n  BFIFO #(5, 32)\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/16591284/fifo_design_collection/vivado,data/full_repos/permissive/16591284/BFIFO\n             data/full_repos/permissive/16591284/fifo_design_collection/vivado,data/full_repos/permissive/16591284/BFIFO.v\n             data/full_repos/permissive/16591284/fifo_design_collection/vivado,data/full_repos/permissive/16591284/BFIFO.sv\n             BFIFO\n             BFIFO.v\n             BFIFO.sv\n             obj_dir/BFIFO\n             obj_dir/BFIFO.v\n             obj_dir/BFIFO.sv\n%Error: data/full_repos/permissive/16591284/fifo_design_collection/vivado/top.v:37: Cannot find file containing module: 'DFIFO'\n  DFIFO #(4, 32)\n  ^~~~~\n%Error: data/full_repos/permissive/16591284/fifo_design_collection/vivado/top.v:40: Cannot find file containing module: 'SRL_FIFO'\n  SRL_FIFO #(4, 32)\n  ^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top(input  wire       CLK,
           input  wire       RST_IN,
           output wire       OUT);

  reg RST; always @(posedge CLK) RST <= RST_IN;
     
  wire                   fifo_enq;
  wire                   fifo_deq;
  reg  [`FIFO_WIDTH-1:0] fifo_din;
  wire [`FIFO_WIDTH-1:0] bfifo_dot;
  wire [`FIFO_WIDTH-1:0] dfifo_dot;
  wire [`FIFO_WIDTH-1:0] srl_fifo_dot;
  wire                   fifo_emp;
  wire                   fifo_ful;
  wire [`FIFO_SIZE:0]    fifo_cnt;

  assign fifo_enq = ~fifo_ful;
  assign fifo_deq = ~fifo_emp;

  BFIFO #(5, `FIFO_WIDTH)
  bfifo(CLK, RST, fifo_enq, fifo_deq, fifo_din, 
        bfifo_dot, fifo_emp, fifo_ful, fifo_cnt);
  DFIFO #(`FIFO_SIZE, `FIFO_WIDTH)
  dfifo(CLK, RST, fifo_enq, fifo_deq, fifo_din, 
        dfifo_dot, 1'b0, 1'b0, 1'b0);
  SRL_FIFO #(`FIFO_SIZE, `FIFO_WIDTH)
  srl_fifo(CLK, RST, fifo_enq, fifo_deq, fifo_din, 
           srl_fifo_dot, 1'b0, 1'b0, 1'b0);

  always @(posedge CLK) begin
    if      (RST)      fifo_din <= 1;
    else if (fifo_enq) fifo_din <= fifo_din + 1;
  end
  
  assign OUT = ^{bfifo_dot, dfifo_dot, srl_fifo_dot};
  
endmodule
module top(input  wire       CLK,
           input  wire       RST_IN,
           output wire       OUT);


  reg RST; always @(posedge CLK) RST <= RST_IN;
     
  wire                   fifo_enq;
  wire                   fifo_deq;
  reg  [`FIFO_WIDTH-1:0] fifo_din;
  wire [`FIFO_WIDTH-1:0] bfifo_dot;
  wire [`FIFO_WIDTH-1:0] dfifo_dot;
  wire [`FIFO_WIDTH-1:0] srl_fifo_dot;
  wire                   fifo_emp;
  wire                   fifo_ful;
  wire [`FIFO_SIZE:0]    fifo_cnt;

  assign fifo_enq = ~fifo_ful;
  assign fifo_deq = ~fifo_emp;

  BFIFO #(5, `FIFO_WIDTH)
  bfifo(CLK, RST, fifo_enq, fifo_deq, fifo_din, 
        bfifo_dot, fifo_emp, fifo_ful, fifo_cnt);
  DFIFO #(`FIFO_SIZE, `FIFO_WIDTH)
  dfifo(CLK, RST, fifo_enq, fifo_deq, fifo_din, 
        dfifo_dot, 1'b0, 1'b0, 1'b0);
  SRL_FIFO #(`FIFO_SIZE, `FIFO_WIDTH)
  srl_fifo(CLK, RST, fifo_enq, fifo_deq, fifo_din, 
           srl_fifo_dot, 1'b0, 1'b0, 1'b0);

  always @(posedge CLK) begin
    if      (RST)      fifo_din <= 1;
    else if (fifo_enq) fifo_din <= fifo_din + 1;
  end
  
  assign OUT = ^{bfifo_dot, dfifo_dot, srl_fifo_dot};
  
endmodule