data/full_repos/permissive/108561032/Fetch.v
data/verilator_xmls/78f86279-ff70-4b88-bc70-3a911971df47.xml
module Fetch(clk,instru,instruD,sum2sumIF,sum2sumOF,FFetch);
       
       input clk;
       input [31:0] instru; 
       input [31:0] sum2sumIF;
       output reg [31:0] instruD;
       output reg [31:0] sum2sumOF;
       output wire FFetch;
  

assign FFetch = clk? 1'b1:1'b0; 

always @(posedge clk)
begin
    
    instruD   = instru;
    sum2sumOF = sum2sumIF;   
    
end
       
        
endmodule
module Fetch(clk,instru,instruD,sum2sumIF,sum2sumOF,FFetch);

       
       input clk;
       input [31:0] instru; 
       input [31:0] sum2sumIF;
       output reg [31:0] instruD;
       output reg [31:0] sum2sumOF;
       output wire FFetch;
  

assign FFetch = clk? 1'b1:1'b0; 

always @(posedge clk)
begin
    
    instruD   = instru;
    sum2sumOF = sum2sumIF;   
    
end
       
        
endmodule