data/full_repos/permissive/125927162/VGA/vga_tb.v
 line:45: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/VGA/vga_tb.v:38: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("vga.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/VGA/vga_tb.v:39: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/VGA/vga_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #4\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/VGA/vga_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #200000000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/VGA/vga_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n   always #4\n          ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vga_tb ();
   reg clk;
   reg rst;
   wire draw;
   wire hs;
   wire vs;
   wire [9:0] x;
   wire [9:0] y;

   vga DUT (
	    .clk(clk),
	    .rst(rst),
	    .draw(draw),
	    .hs(hs),
	    .vs(vs),
	    .x(x),
	    .y(y)
	    );

   initial begin
      $dumpfile("vga.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      rst = 1;
      #4
	rst = 0;
      #200000000
	$finish;
   end
   always #4
     clk = ~clk;

endmodule
module vga_tb ();

   reg clk;
   reg rst;
   wire draw;
   wire hs;
   wire vs;
   wire [9:0] x;
   wire [9:0] y;

   vga DUT (
	    .clk(clk),
	    .rst(rst),
	    .draw(draw),
	    .hs(hs),
	    .vs(vs),
	    .x(x),
	    .y(y)
	    );

   initial begin
      $dumpfile("vga.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      rst = 1;
      #4
	rst = 0;
      #200000000
	$finish;
   end
   always #4
     clk = ~clk;

endmodule