data/full_repos/permissive/157049472/Verilog Test Benches/Instruction_Fetch_TB.v
1: b'%Error: Cannot find file containing module: Test\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Test\n             data/full_repos/permissive/157049472/Verilog/Test.v\n             data/full_repos/permissive/157049472/Verilog/Test.sv\n             Test\n             Test.v\n             Test.sv\n             obj_dir/Test\n             obj_dir/Test.v\n             obj_dir/Test.sv\n%Error: Cannot find file containing module: Benches,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Benches/Instruction_Fetch_TB.v\n%Error: Exiting due to 4 error(s)\n'
module Instruction_Fetch_TB;


	reg [31:0] pc;
	reg clk;
	reg rst;


	wire [31:0] instruction;


	InstructionFetch uut (
		.pc(pc), 
		.instruction(instruction), 
		.clk(clk), 
		.rst(rst)
	);

	initial begin

		pc = 0;
		clk = 0;
		rst = 0;


		#100;
        

		rst = 1;
		#10 rst = 0;
		#10 pc = 1;
		#10 pc = 2;
		#10 pc = 3;
		#10 pc = 4;
	end
	always begin
		#5 clk = ~clk;
	end
      
endmodule
module Instruction_Fetch_TB;



	reg [31:0] pc;
	reg clk;
	reg rst;


	wire [31:0] instruction;


	InstructionFetch uut (
		.pc(pc), 
		.instruction(instruction), 
		.clk(clk), 
		.rst(rst)
	);

	initial begin

		pc = 0;
		clk = 0;
		rst = 0;


		#100;
        

		rst = 1;
		#10 rst = 0;
		#10 pc = 1;
		#10 pc = 2;
		#10 pc = 3;
		#10 pc = 4;
	end
	always begin
		#5 clk = ~clk;
	end
      
endmodule