data/full_repos/permissive/124591763/led/sevseg/sseg_drv.v
1: b'%Warning-WIDTH: data/full_repos/permissive/124591763/led/sevseg/sseg_drv.v:113: Operator OR expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                              : ... In instance sseg_drv\n        an_w <= (an_w << 1) | an_w[7];\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sseg_drv (
    input  wire        clk,

    input  wire        en,
    input  wire        mod,

    input  wire [31:0] dat,

    output wire [ 7:0] an,
    output reg  [ 7:0] seg
);


reg         blnk  = 1'b1;


reg  [ 3:0] d_sel;


wire [ 7:0] an_b;


wire [ 7:0] an_n;


reg  [ 7:0] an_w  = 8'h1;


reg  [`CNT_WIDTH - 1:0] cnt_a = `CNT_WIDTH'h0;


reg  [25:0] cnt_b = 26'h0;


wire        tck;


assign an   = (en == 1'b1) ? ~an_n : 8'hff;


assign an_n = (mod == 1'b1) ? an_b : an_w;


assign an_b = (blnk == 1'b1) ? an_w : 8'h00;


assign tck  = &cnt_a;


always @ (posedge clk) cnt_a <= cnt_a + `CNT_WIDTH'h1;


always @ (posedge clk) begin
    if (cnt_b == `HLF) begin
        cnt_b <= 26'h0;
    end else begin
        cnt_b <= cnt_b + 26'h1;
    end
end


always @ (posedge clk) begin
    if (cnt_b == `HLF) begin
        blnk <= ~blnk;
    end
end


always @ (*) begin
    case (d_sel)
        4'h0:    seg = 8'hc0;
        4'h1:    seg = 8'hf9;
        4'h2:    seg = 8'ha4;
        4'h3:    seg = 8'hb0;
        4'h4:    seg = 8'h99;
        4'h5:    seg = 8'h92;
        4'h6:    seg = 8'h82;
        4'h7:    seg = 8'hf8;
        4'h8:    seg = 8'h80;
        4'h9:    seg = 8'h98;
        4'ha:    seg = 8'h88;
        4'hb:    seg = 8'h83;
        4'hc:    seg = 8'hc6;
        4'hd:    seg = 8'ha1;
        4'he:    seg = 8'h86;
        4'hf:    seg = 8'h8e;
        default: seg = 8'hff;
    endcase
end


always @ (posedge clk) begin
    if (tck == 1'b1) begin
        an_w <= (an_w << 1) | an_w[7];
    end
end


always @ (*) begin
    case (an_w)
        8'h01:   d_sel = dat[ 3: 0];
        8'h02:   d_sel = dat[ 7: 4];
        8'h04:   d_sel = dat[11: 8];
        8'h08:   d_sel = dat[15:12];
        8'h10:   d_sel = dat[19:16];
        8'h20:   d_sel = dat[23:20];
        8'h40:   d_sel = dat[27:24];
        8'h80:   d_sel = dat[31:28];
        default: d_sel = 4'h0;
    endcase
end

endmodule
module sseg_drv (
    input  wire        clk,

    input  wire        en,
    input  wire        mod,

    input  wire [31:0] dat,

    output wire [ 7:0] an,
    output reg  [ 7:0] seg
);



reg         blnk  = 1'b1;


reg  [ 3:0] d_sel;


wire [ 7:0] an_b;


wire [ 7:0] an_n;


reg  [ 7:0] an_w  = 8'h1;


reg  [`CNT_WIDTH - 1:0] cnt_a = `CNT_WIDTH'h0;


reg  [25:0] cnt_b = 26'h0;


wire        tck;


assign an   = (en == 1'b1) ? ~an_n : 8'hff;


assign an_n = (mod == 1'b1) ? an_b : an_w;


assign an_b = (blnk == 1'b1) ? an_w : 8'h00;


assign tck  = &cnt_a;


always @ (posedge clk) cnt_a <= cnt_a + `CNT_WIDTH'h1;


always @ (posedge clk) begin
    if (cnt_b == `HLF) begin
        cnt_b <= 26'h0;
    end else begin
        cnt_b <= cnt_b + 26'h1;
    end
end


always @ (posedge clk) begin
    if (cnt_b == `HLF) begin
        blnk <= ~blnk;
    end
end


always @ (*) begin
    case (d_sel)
        4'h0:    seg = 8'hc0;
        4'h1:    seg = 8'hf9;
        4'h2:    seg = 8'ha4;
        4'h3:    seg = 8'hb0;
        4'h4:    seg = 8'h99;
        4'h5:    seg = 8'h92;
        4'h6:    seg = 8'h82;
        4'h7:    seg = 8'hf8;
        4'h8:    seg = 8'h80;
        4'h9:    seg = 8'h98;
        4'ha:    seg = 8'h88;
        4'hb:    seg = 8'h83;
        4'hc:    seg = 8'hc6;
        4'hd:    seg = 8'ha1;
        4'he:    seg = 8'h86;
        4'hf:    seg = 8'h8e;
        default: seg = 8'hff;
    endcase
end


always @ (posedge clk) begin
    if (tck == 1'b1) begin
        an_w <= (an_w << 1) | an_w[7];
    end
end


always @ (*) begin
    case (an_w)
        8'h01:   d_sel = dat[ 3: 0];
        8'h02:   d_sel = dat[ 7: 4];
        8'h04:   d_sel = dat[11: 8];
        8'h08:   d_sel = dat[15:12];
        8'h10:   d_sel = dat[19:16];
        8'h20:   d_sel = dat[23:20];
        8'h40:   d_sel = dat[27:24];
        8'h80:   d_sel = dat[31:28];
        default: d_sel = 4'h0;
    endcase
end

endmodule