data/full_repos/permissive/135077285/mem_wb.v
data/verilator_xmls/cce58baa-4907-49d4-b859-5ef822c587d8.xml
module memWb(
  input clock,



  input wire [1:0] wbControlInput,


  input wire [31:0] readDataMemoryInput,
  input wire [31:0] aluResultInput,
  input wire [4:0] writeRegisterInput,




  output reg regWrite,
  output reg memToReg,


  output reg [31:0] readDataMemory,
  output reg [31:0] aluResult,
  output reg [4:0] writeRegister
);

  initial begin

    regWrite <= 0;
    memToReg <= 0;


    readDataMemory <= 0;
    aluResult <= 0;
    writeRegister <= 0;
  end

  always @(posedge clock) begin

    regWrite <= wbControlInput[1];
    memToReg <= wbControlInput[0];


    readDataMemory <= readDataMemoryInput;
    aluResult <= aluResultInput;
    writeRegister <= writeRegisterInput;
  end

endmodule
module memWb(
  input clock,



  input wire [1:0] wbControlInput,


  input wire [31:0] readDataMemoryInput,
  input wire [31:0] aluResultInput,
  input wire [4:0] writeRegisterInput,




  output reg regWrite,
  output reg memToReg,


  output reg [31:0] readDataMemory,
  output reg [31:0] aluResult,
  output reg [4:0] writeRegister
);


  initial begin

    regWrite <= 0;
    memToReg <= 0;


    readDataMemory <= 0;
    aluResult <= 0;
    writeRegister <= 0;
  end

  always @(posedge clock) begin

    regWrite <= wbControlInput[1];
    memToReg <= wbControlInput[0];


    readDataMemory <= readDataMemoryInput;
    aluResult <= aluResultInput;
    writeRegister <= writeRegisterInput;
  end

endmodule