data/full_repos/permissive/21438680/DAQ_Firmware/src/ok/okWireIn_sync.v
1: b"%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ok/okWireIn_sync.v:49: Cannot find file containing module: 'fifo32_shallow'\nfifo32_shallow fifo32_shallow_inst (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ok,data/full_repos/permissive/21438680/fifo32_shallow\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ok,data/full_repos/permissive/21438680/fifo32_shallow.v\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ok,data/full_repos/permissive/21438680/fifo32_shallow.sv\n             fifo32_shallow\n             fifo32_shallow.v\n             fifo32_shallow.sv\n             obj_dir/fifo32_shallow\n             obj_dir/fifo32_shallow.v\n             obj_dir/fifo32_shallow.sv\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ok/okWireIn_sync.v:61: Cannot find file containing module: 'okWireIn'\nokWireIn control_wires(\n^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module okWireIn_sync (
  input  wire                     clk,
  input  wire                     okClk,
  input  wire [112:0]             okHE,
  input  wire [7:0]               ep_addr,
  output reg  [31:0]              ep_dataout
);

wire [31:0] control_bus;
wire [31:0] q_buff;
wire        rdempty;

reg         rdreq;

always @( posedge clk ) begin
  if ( rdreq ) begin
    ep_dataout <= q_buff;
  end
  rdreq <= ~rdempty;
end

fifo32_shallow fifo32_shallow_inst (
  .data ( control_bus ),
  .rdclk ( clk ),
  .rdreq ( rdreq ),
  .wrclk ( okClk ),
  .wrreq ( 1'b1 ),
  .q ( q_buff ),
  .rdempty ( rdempty ),
  .wrfull (  )
);


okWireIn control_wires(
  .okHE(okHE),
  .ep_addr(ep_addr),
  .ep_dataout(control_bus)
);
endmodule
module okWireIn_sync (
  input  wire                     clk,
  input  wire                     okClk,
  input  wire [112:0]             okHE,
  input  wire [7:0]               ep_addr,
  output reg  [31:0]              ep_dataout
);


wire [31:0] control_bus;
wire [31:0] q_buff;
wire        rdempty;

reg         rdreq;

always @( posedge clk ) begin
  if ( rdreq ) begin
    ep_dataout <= q_buff;
  end
  rdreq <= ~rdempty;
end

fifo32_shallow fifo32_shallow_inst (
  .data ( control_bus ),
  .rdclk ( clk ),
  .rdreq ( rdreq ),
  .wrclk ( okClk ),
  .wrreq ( 1'b1 ),
  .q ( q_buff ),
  .rdempty ( rdempty ),
  .wrfull (  )
);


okWireIn control_wires(
  .okHE(okHE),
  .ep_addr(ep_addr),
  .ep_dataout(control_bus)
);
endmodule