data/full_repos/permissive/157608247/testbench/candy_wb_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:1: Cannot find include file: candy_defines.v\n`include "candy_defines.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v.v\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v.sv\n             candy_defines.v\n             candy_defines.v.v\n             candy_defines.v.sv\n             obj_dir/candy_defines.v\n             obj_dir/candy_defines.v.v\n             obj_dir/candy_defines.v.sv\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:11: Define or directive not defined: \'`SRAMDataWidth\'\nreg [`SRAMDataWidth] result;\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`SRAMDataWidth] result;\n                   ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:12: Define or directive not defined: \'`SRAMAddrWidth\'\nreg [`SRAMAddrWidth] sram_result_addr;\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`SRAMAddrWidth] sram_result_addr;\n                   ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:13: Define or directive not defined: \'`RegAddrBus\'\nreg [`RegAddrBus] reg_addr;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`RegAddrBus] reg_addr;\n                ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:16: Define or directive not defined: \'`SRAMDataWidth\'\nwire [`SRAMDataWidth] sram_wdata;\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:16: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`SRAMDataWidth] sram_wdata;\n                    ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:17: Define or directive not defined: \'`SRAMAddrWidth\'\nwire [`SRAMAddrWidth] sram_waddr;\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`SRAMAddrWidth] sram_waddr;\n                    ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:20: Define or directive not defined: \'`RegAddrBus\'\nwire [`RegAddrBus] reg_waddr;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`RegAddrBus] reg_waddr;\n                 ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:21: Define or directive not defined: \'`RegBus\'\nwire [`RegBus] reg_wdata;\n      ^~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`RegBus] reg_wdata;\n             ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:49: Define or directive not defined: \'`RstEnable\'\n        rst <= `RstEnable;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst <= `RstEnable;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #0 begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:53: Define or directive not defined: \'`RstDisable\'\n        rst <= `RstDisable;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst <= `RstDisable;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #10 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #25 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #25 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_wb_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: Exiting due to 19 error(s), 5 warning(s)\n'
module candy_wb_tb;

reg clk;
reg rst;

reg is_mem;

reg wb_enable;
reg [`SRAMDataWidth] result;
reg [`SRAMAddrWidth] sram_result_addr;
reg [`RegAddrBus] reg_addr;

wire sram_write_enable;
wire [`SRAMDataWidth] sram_wdata;
wire [`SRAMAddrWidth] sram_waddr;

wire reg_write_enable;
wire [`RegAddrBus] reg_waddr;
wire [`RegBus] reg_wdata;



candy_wb wb(
    .clk(clk),
    .rst(rst),

    .is_mem(is_mem),
    .wb_enable(wb_enable),
    .result(result),
    .sram_result_addr(sram_result_addr),
    .reg_addr(reg_addr),


    .sram_write_enable(sram_write_enable),
    .sram_wdata(sram_wdata),
    .sram_waddr(sram_waddr),

    .reg_write_enable(reg_write_enable),
    .reg_waddr(reg_waddr),
    .reg_wdata(reg_wdata)
);


initial begin
    #0 begin
        clk <= 1'b0;
        rst <= `RstEnable;
        wb_enable <= 1'b0;
    end
    #10 begin
        rst <= `RstDisable;
        wb_enable <= 1'b1;
    end
    #25 begin
        is_mem <= 1'b1;
        result <= 24'h37c549;
        sram_result_addr <= 17'd11;
    end
    #25 begin
        is_mem <= 1'b0;
        result <= 24'h37c549;
        reg_addr <= 4'h4;
    end
end

always #5 clk <= ~clk;

endmodule
module candy_wb_tb;


reg clk;
reg rst;

reg is_mem;

reg wb_enable;
reg [`SRAMDataWidth] result;
reg [`SRAMAddrWidth] sram_result_addr;
reg [`RegAddrBus] reg_addr;

wire sram_write_enable;
wire [`SRAMDataWidth] sram_wdata;
wire [`SRAMAddrWidth] sram_waddr;

wire reg_write_enable;
wire [`RegAddrBus] reg_waddr;
wire [`RegBus] reg_wdata;



candy_wb wb(
    .clk(clk),
    .rst(rst),

    .is_mem(is_mem),
    .wb_enable(wb_enable),
    .result(result),
    .sram_result_addr(sram_result_addr),
    .reg_addr(reg_addr),


    .sram_write_enable(sram_write_enable),
    .sram_wdata(sram_wdata),
    .sram_waddr(sram_waddr),

    .reg_write_enable(reg_write_enable),
    .reg_waddr(reg_waddr),
    .reg_wdata(reg_wdata)
);


initial begin
    #0 begin
        clk <= 1'b0;
        rst <= `RstEnable;
        wb_enable <= 1'b0;
    end
    #10 begin
        rst <= `RstDisable;
        wb_enable <= 1'b1;
    end
    #25 begin
        is_mem <= 1'b1;
        result <= 24'h37c549;
        sram_result_addr <= 17'd11;
    end
    #25 begin
        is_mem <= 1'b0;
        result <= 24'h37c549;
        reg_addr <= 4'h4;
    end
end

always #5 clk <= ~clk;

endmodule