data/full_repos/permissive/135795492/project/async.v
 line:77: before: "="
1: b'%Warning-MULTITOP: data/full_repos/permissive/135795492/project/async.v:74: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                          : ... Top module \'async_transmitter\'\nmodule async_transmitter(\n       ^~~~~~~~~~~~~~~~~\n                                                                          : ... Top module \'async_receiver\'\nmodule async_receiver(\n       ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/135795492/project/async.v:192: Logical Operator WHILE expects 1 bit on the For Test Condition, but For Test Condition\'s SHIFTR generates 32 bits.\n                                                                        : ... In instance async_transmitter.tickgen\nfunction integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction\n                                                      ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/135795492/project/async.v:131: Logical Operator WHILE expects 1 bit on the For Test Condition, but For Test Condition\'s SHIFTR generates 32 bits.\n                                                                        : ... In instance async_receiver\nfunction integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction\n                                                      ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/135795492/project/async.v:134: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance async_receiver\nalways @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1\'d0 : OversamplingCnt + 1\'d1;\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/135795492/project/async.v:135: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'OversamplingCnt\' generates 3 bits.\n                                                                        : ... In instance async_receiver\nwire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);\n                                                     ^~\n%Error: Exiting due to 5 warning(s)\n'
module BaudTickGen(
	input clk, enable,
	output tick
);
parameter ClkFrequency = 24000000;
parameter Baud = 9600;
parameter Oversampling = 1;

function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8;
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth));
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
module BaudTickGen(
	input clk, enable,
	output tick
);

parameter ClkFrequency = 24000000;
parameter Baud = 9600;
parameter Oversampling = 1;

function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8;
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth));
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule