data/full_repos/permissive/138243369/button_debouncer.v
data/verilator_xmls/12549107-7b56-41b3-913c-a009b1239051.xml
module button_debouncer(
input wire inp,
input wire clk,
input wire clr,
output wire outp);


reg delay1;
reg delay2;
reg delay3;

reg [17:0] count;
reg beat;

wire slower_clk;

initial begin
    delay1 = 1'b0;
    delay2 = 1'b0;
    delay3 = 1'b0;
end

assign slower_clk = beat;
always @(posedge clk) begin

   if (clr) begin
		beat <= 1'b0;
		count <= 18'h0;
   end 
	else begin
		case(count)

			18'h1: begin

				beat <= 1'b1;
				count <= count + 1'b1;
			end

         default: begin
				beat <= 1'b0;
				count <= count + 1'b1;
			end
		endcase
	end
end

always @(posedge slower_clk or posedge clr) begin

	if (clr) begin

      delay1 <= 1'b0;
      delay2 <= 1'b0;
      delay3 <= 1'b0;
   end
   else begin

      delay1 <= inp;
      delay2 <= delay1;
      delay3 <= delay2;
   end
end

assign outp = delay1 & delay2 & delay3;

endmodule
module button_debouncer(
input wire inp,
input wire clk,
input wire clr,
output wire outp);



reg delay1;
reg delay2;
reg delay3;

reg [17:0] count;
reg beat;

wire slower_clk;

initial begin
    delay1 = 1'b0;
    delay2 = 1'b0;
    delay3 = 1'b0;
end

assign slower_clk = beat;
always @(posedge clk) begin

   if (clr) begin
		beat <= 1'b0;
		count <= 18'h0;
   end 
	else begin
		case(count)

			18'h1: begin

				beat <= 1'b1;
				count <= count + 1'b1;
			end

         default: begin
				beat <= 1'b0;
				count <= count + 1'b1;
			end
		endcase
	end
end

always @(posedge slower_clk or posedge clr) begin

	if (clr) begin

      delay1 <= 1'b0;
      delay2 <= 1'b0;
      delay3 <= 1'b0;
   end
   else begin

      delay1 <= inp;
      delay2 <= delay1;
      delay3 <= delay2;
   end
end

assign outp = delay1 & delay2 & delay3;

endmodule