data/full_repos/permissive/174323821/hdl/clocking/jtframe_cen48.v
 line:147: before: ","
1: b'%Warning-MULTITOP: data/full_repos/permissive/174323821/hdl/clocking/jtframe_cen48.v:76: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                       : ... Top module \'jtframe_cen48\'\nmodule jtframe_cen48(\n       ^~~~~~~~~~~~~\n                                                                                       : ... Top module \'jtframe_cen3p57\'\nmodule jtframe_cen3p57(\n       ^~~~~~~~~~~~~~~\n                                                                                       : ... Top module \'jtframe_cenp384\'\nmodule jtframe_cenp384(\n       ^~~~~~~~~~~~~~~\n                                                                                       : ... Top module \'jtframe_cen10\'\nmodule jtframe_cen10(\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/174323821/hdl/clocking/jtframe_cen48.v:105: Cannot find file containing module: \'jtframe_frac_cen\'\n    jtframe_frac_cen #(.W(2),.WC(16)) u_frac(\n    ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174323821/hdl/clocking,data/full_repos/permissive/174323821/jtframe_frac_cen\n             data/full_repos/permissive/174323821/hdl/clocking,data/full_repos/permissive/174323821/jtframe_frac_cen.v\n             data/full_repos/permissive/174323821/hdl/clocking,data/full_repos/permissive/174323821/jtframe_frac_cen.sv\n             jtframe_frac_cen\n             jtframe_frac_cen.v\n             jtframe_frac_cen.sv\n             obj_dir/jtframe_frac_cen\n             obj_dir/jtframe_frac_cen.v\n             obj_dir/jtframe_frac_cen.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module jtframe_cen48(
    input   clk,
    output  reg cen12,
    output  reg cen16,
    output  reg cen8,
    output  reg cen6,
    output  reg cen4,
    output  reg cen4_12,
    output  reg cen3,
    output  reg cen3q,
    output  reg cen1p5,

    output  reg cen16b,
    output  reg cen12b,
    output  reg cen6b,
    output  reg cen3b,
    output  reg cen3qb,
    output  reg cen1p5b
);

reg [4:0] cencnt=5'd0;
reg [2:0] cencnt6=3'd0;
reg       cencnt12=1'd0;
reg [2:0] cencnt4_12=3'd1;

always @(posedge clk) begin
    cencnt  <= cencnt+5'd1;
    cencnt6 <= cencnt6==3'd5 ? 3'd0 : (cencnt6+3'd1);
    cencnt12<= cencnt12 ^^ (cencnt6==3'd5);
end

always @(posedge clk) begin
    cen12  <= cencnt[1:0] == 2'd0;
    cen12b <= cencnt[1:0] == 2'd2;
    if(cencnt[1:0]==2'b0) cencnt4_12 <= { cencnt4_12[1:0], cencnt4_12[2]};
    cen4_12 <= cencnt[1:0]==2'd0 && cencnt4_12[2];
    cen16  <= cencnt6 == 3'd0 || cencnt6 == 3'd3;
    cen16b <= cencnt6 == 3'd2 || cencnt6 == 3'd5;
    cen8   <= cencnt6     == 3'd0;
    cen4   <= cencnt6     == 3'd0 && cencnt12;
    cen6   <= cencnt[2:0] == 3'd0;
    cen6b  <= cencnt[2:0] == 3'd4;
    cen3   <= cencnt[3:0] == 4'd0;
    cen3b  <= cencnt[3:0] == 4'h8;
    cen3q  <= cencnt[3:0] == 4'b1100;
    cen3qb <= cencnt[3:0] == 4'b0100;
    cen1p5 <= cencnt[4:0] == 5'd0;
    cen1p5b<= cencnt[4:0] == 5'h10;
end
endmodule
module jtframe_cen48(
    input   clk,
    output  reg cen12,
    output  reg cen16,
    output  reg cen8,
    output  reg cen6,
    output  reg cen4,
    output  reg cen4_12,
    output  reg cen3,
    output  reg cen3q,
    output  reg cen1p5,

    output  reg cen16b,
    output  reg cen12b,
    output  reg cen6b,
    output  reg cen3b,
    output  reg cen3qb,
    output  reg cen1p5b
);


reg [4:0] cencnt=5'd0;
reg [2:0] cencnt6=3'd0;
reg       cencnt12=1'd0;
reg [2:0] cencnt4_12=3'd1;

always @(posedge clk) begin
    cencnt  <= cencnt+5'd1;
    cencnt6 <= cencnt6==3'd5 ? 3'd0 : (cencnt6+3'd1);
    cencnt12<= cencnt12 ^^ (cencnt6==3'd5);
end

always @(posedge clk) begin
    cen12  <= cencnt[1:0] == 2'd0;
    cen12b <= cencnt[1:0] == 2'd2;
    if(cencnt[1:0]==2'b0) cencnt4_12 <= { cencnt4_12[1:0], cencnt4_12[2]};
    cen4_12 <= cencnt[1:0]==2'd0 && cencnt4_12[2];
    cen16  <= cencnt6 == 3'd0 || cencnt6 == 3'd3;
    cen16b <= cencnt6 == 3'd2 || cencnt6 == 3'd5;
    cen8   <= cencnt6     == 3'd0;
    cen4   <= cencnt6     == 3'd0 && cencnt12;
    cen6   <= cencnt[2:0] == 3'd0;
    cen6b  <= cencnt[2:0] == 3'd4;
    cen3   <= cencnt[3:0] == 4'd0;
    cen3b  <= cencnt[3:0] == 4'h8;
    cen3q  <= cencnt[3:0] == 4'b1100;
    cen3qb <= cencnt[3:0] == 4'b0100;
    cen1p5 <= cencnt[4:0] == 5'd0;
    cen1p5b<= cencnt[4:0] == 5'h10;
end
endmodule