data/full_repos/permissive/21408550/rtl/DE0_Comm.v
1: b'%Error: data/full_repos/permissive/21408550/rtl/DE0_Comm.v:26: Cannot find include file: system_include.v\n`include "system_include.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21408550/rtl,data/full_repos/permissive/21408550/system_include.v\n             data/full_repos/permissive/21408550/rtl,data/full_repos/permissive/21408550/system_include.v.v\n             data/full_repos/permissive/21408550/rtl,data/full_repos/permissive/21408550/system_include.v.sv\n             system_include.v\n             system_include.v.v\n             system_include.v.sv\n             obj_dir/system_include.v\n             obj_dir/system_include.v.v\n             obj_dir/system_include.v.sv\n%Error: Exiting due to 1 error(s)\n'
module DE0_Comm(


	input CLOCK_50,


	`ifdef UNDER_TEST

		input areset,
	`endif
	

	output [7:0] LED 
);






wire sysclk, reset_n;


wire heartbeat;






assign LED = {7'b0,heartbeat};






pll_clock	clock (
	.inclk0 ( CLOCK_50 ),
	.c0 ( sysclk ),
	

	`ifdef UNDER_TEST
		.areset( areset ),
	`else
		.areset(),
	`endif
	
	.locked ( )
	);


reset reset(
	.clk_i( sysclk ),
	.nreset_o( reset_n )
	);


heartbeat hb(
	.clk_i( sysclk ),
	.nreset_i( reset_n ),
	.heartbeat_o( heartbeat )
	);


fsm_app app(
	.clk_i(sysclk),
	.nreset_i(reset_n)
	);
	



	
endmodule
module DE0_Comm(


	input CLOCK_50,


	`ifdef UNDER_TEST

		input areset,
	`endif
	

	output [7:0] LED 
);







wire sysclk, reset_n;


wire heartbeat;






assign LED = {7'b0,heartbeat};






pll_clock	clock (
	.inclk0 ( CLOCK_50 ),
	.c0 ( sysclk ),
	

	`ifdef UNDER_TEST
		.areset( areset ),
	`else
		.areset(),
	`endif
	
	.locked ( )
	);


reset reset(
	.clk_i( sysclk ),
	.nreset_o( reset_n )
	);


heartbeat hb(
	.clk_i( sysclk ),
	.nreset_i( reset_n ),
	.heartbeat_o( heartbeat )
	);


fsm_app app(
	.clk_i(sysclk),
	.nreset_i(reset_n)
	);
	



	
endmodule