data/full_repos/permissive/143278/ivltests/pr1510724.v
 line:15: before: "."
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1510724.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1510724.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  parameter count = 2;

  reg pass = 1'b1;
  wire [count-1:0] y;
  reg [count-1:0] a, b;

  manyNands nandArray(y, a, b);
  defparam nandArray.count = count;

  initial begin
    a = 2'b00; b = 2'b00;
    #1;
    if (y !== 2'b11) begin
      $display("FAILED: ~(2'b00 & 2'b00) should be 2'b11, got %b", y);
      pass = 1'b0;
    end

    a = 2'b11; b = 2'b11;
    #1;
    if (y !== 2'b00) begin
      $display("FAILED: ~(2'b11 & 2'b11) should be 2'b00, got %b", y);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  parameter count = 2;

  reg pass = 1'b1;
  wire [count-1:0] y;
  reg [count-1:0] a, b;

  manyNands nandArray(y, a, b);
  defparam nandArray.count = count;

  initial begin
    a = 2'b00; b = 2'b00;
    #1;
    if (y !== 2'b11) begin
      $display("FAILED: ~(2'b00 & 2'b00) should be 2'b11, got %b", y);
      pass = 1'b0;
    end

    a = 2'b11; b = 2'b11;
    #1;
    if (y !== 2'b00) begin
      $display("FAILED: ~(2'b11 & 2'b11) should be 2'b00, got %b", y);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule