data/full_repos/permissive/129582718/project.v
 line:84: before: "."
1: b"%Error: data/full_repos/permissive/129582718/project.v:1152: syntax error, unexpected '(', expecting IDENTIFIER\n    hex0(.m0(signals[0]),\n         ^\n%Error: Exiting due to 1 error(s)\n"
module clock_8hz(clk, out);

  input clk;
  output reg out = 1'b0;

  reg [22:0] counter = 23'b0;
  always @(posedge clk) begin
    counter <= counter + 1'b1;
    if (counter[22:0] == 23'b10111110101111000010000) begin
      out <= 1'b1;
      counter <= 23'b0;
    end else begin
      out <= 1'b0;
    end
  end
endmodule
module clock_8hz(clk, out);


  input clk;
  output reg out = 1'b0;

  reg [22:0] counter = 23'b0;
  always @(posedge clk) begin
    counter <= counter + 1'b1;
    if (counter[22:0] == 23'b10111110101111000010000) begin
      out <= 1'b1;
      counter <= 23'b0;
    end else begin
      out <= 1'b0;
    end
  end
endmodule