data/full_repos/permissive/167274925/processor_tb.v
 line:28 column:11: Illegal character '\x00'
1: b'%Warning-STMTDLY: data/full_repos/permissive/167274925/processor_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167274925/processor_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/processor_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n#40;\n^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/processor_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n#2000;\n^\n%Error: data/full_repos/permissive/167274925/processor_tb.v:11: Cannot find file containing module: \'processor\'\nprocessor p1(.Clk(Clk),.Reset(Reset),.Zero(Zero),.IFPC(IFPC),.IDPC(IDPC),.EXPC(EXPC),.MEPC(MEPC),.WBPC(WBPC),.WDatalo(WDatalo),.HI(HI),.LO(LO));\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/processor\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/processor.v\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/processor.sv\n             processor\n             processor.v\n             processor.sv\n             obj_dir/processor\n             obj_dir/processor.v\n             obj_dir/processor.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module processor_tb();
reg Clk,Reset;
wire Zero;
wire [31:0]IFPC,IDPC,EXPC,MEPC,WBPC;
wire [31:0]WDatalo;
wire[31:0] HI,LO;
processor p1(.Clk(Clk),.Reset(Reset),.Zero(Zero),.IFPC(IFPC),.IDPC(IDPC),.EXPC(EXPC),.MEPC(MEPC),.WBPC(WBPC),.WDatalo(WDatalo),.HI(HI),.LO(LO));

always begin 
Clk<=1;
#100;
Clk<=0;
#100;
end 
initial begin 
Reset<=1;
#40;
Reset<=0;
#2000;

end 


endmodule
module processor_tb();

reg Clk,Reset;
wire Zero;
wire [31:0]IFPC,IDPC,EXPC,MEPC,WBPC;
wire [31:0]WDatalo;
wire[31:0] HI,LO;
processor p1(.Clk(Clk),.Reset(Reset),.Zero(Zero),.IFPC(IFPC),.IDPC(IDPC),.EXPC(EXPC),.MEPC(MEPC),.WBPC(WBPC),.WDatalo(WDatalo),.HI(HI),.LO(LO));

always begin 
Clk<=1;
#100;
Clk<=0;
#100;
end 
initial begin 
Reset<=1;
#40;
Reset<=0;
#2000;

end 


endmodule