data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v
1: b'%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:196: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'WRITE_DATA_IN\' generates 32 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n    SCRM_REG: SCRMBL_IDL_DAT <= WRITE_DATA_IN;\n                             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:198: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'WRITE_DATA_IN\' generates 32 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n    LEDO_REG: LED_OVERRIDE <= WRITE_DATA_IN;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:199: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'WRITE_DATA_IN\' generates 32 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n    RXEQ_REG: RXEQMIX <= WRITE_DATA_IN;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:200: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'WRITE_DATA_IN\' generates 32 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n    TXDS_REG: TXDIFFCTRL <= WRITE_DATA_IN;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:201: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'WRITE_DATA_IN\' generates 32 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n    TXPE_REG: TXPREEMPHASIS <= WRITE_DATA_IN;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:215: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'PINE_DEF\' generates 1 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n   PERIPH_IN_EN   <= PINE_DEF;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:229: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n     PIND_REG: PERIPH_IN_EN   <= 1\'b0;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:230: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n     PINE_REG: PERIPH_IN_EN   <= 1\'b1;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:243: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n     PIND_REG: PERIPH_IN_EN   <= 1\'b0;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:244: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n     PINE_REG: PERIPH_IN_EN   <= 1\'b1;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:235: Operator NEQ expects 14 bits on the RHS, but RHS\'s VARREF \'LC_ADDR_IN\' generates 8 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n   if (WRITE_IN && (!LC_WRITE_IN || (ADDR_IN != LC_ADDR_IN)))\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:252: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'FLAGS_IN\' generates 6 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n  FLAG_REG: READ_DATA_OUT = FLAGS_IN;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:255: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'SCRMBL_IDL_DAT\' generates 4 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n  SCRM_REG: READ_DATA_OUT = SCRMBL_IDL_DAT;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:257: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'LED_OVERRIDE\' generates 8 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n  LEDO_REG: READ_DATA_OUT = LED_OVERRIDE;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:258: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'RXEQMIX\' generates 8 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n  RXEQ_REG: READ_DATA_OUT = RXEQMIX;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:259: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'TXDIFFCTRL\' generates 16 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n  TXDS_REG: READ_DATA_OUT = TXDIFFCTRL;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:260: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'TXPREEMPHASIS\' generates 12 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n  TXPE_REG: READ_DATA_OUT = TXPREEMPHASIS;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:265: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PERIPH_IN_EN\' generates 2 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n  PIND_REG: READ_DATA_OUT = PERIPH_IN_EN;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_reg_bank.v:266: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'PERIPH_IN_EN\' generates 2 bits.\n                                                                                                          : ... In instance spinnaker_fpgas_reg_bank\n  PINE_REG: READ_DATA_OUT = PERIPH_IN_EN;\n                          ^\n%Error: Exiting due to 19 warning(s)\n'
module spinnaker_fpgas_reg_bank #(
                                   parameter REGA_BITS = 14

                                 , parameter REGD_BITS = 32
                                 )
                                 ( input  wire CLK_IN
                                 , input  wire RESET_IN

                                 ,   input  wire                 WRITE_IN
                                 ,   input  wire [REGA_BITS-1:0] ADDR_IN
                                 ,   input  wire [REGD_BITS-1:0] WRITE_DATA_IN
                                 ,   output reg  [REGD_BITS-1:0] READ_DATA_OUT

                                 ,   input  wire                 LC_WRITE_IN
                                 ,   input  wire           [7:0] LC_ADDR_IN
                                 ,   input  wire [REGD_BITS-1:0] LC_WR_DATA_IN

                                 , input  wire   [REGD_BITS-1:0] VERSION_IN






                                 , input  wire             [5:0] FLAGS_IN

                                 , output reg             [31:0] SPINNAKER_LINK_ENABLE

                                 , output reg             [31:0] PERIPH_MC_KEY
                                 , output reg             [31:0] PERIPH_MC_MASK
                                 , output reg              [3:0] SCRMBL_IDL_DAT











                                 , output reg              [7:0] LED_OVERRIDE






                                 , output reg              [7:0] RXEQMIX






                                 , output reg             [15:0] TXDIFFCTRL






                                 , output reg             [11:0] TXPREEMPHASIS

                                 , output reg              [1:0] PERIPH_IN_EN

                                 , output reg             [31:0] LC_KEY
                                 , output reg             [31:0] LC_MASK

                                 , output reg             [31:0] RC_KEY
                                 , output reg             [31:0] RC_MASK
                                 );


localparam PKEY_DEF   = 32'hffff_ffff;
localparam PMSK_DEF   = 32'h0000_0000;
localparam SCRMBL_DEF =  4'hf;
localparam LINKEN_DEF = 32'h0000_0000;
localparam LEDOVR_DEF =  8'h0f;


localparam PINE_DEF   = 1'b0;
localparam LKEY_DEF   = 32'hffff_fe00;
localparam LMSK_DEF   = 32'hffff_ff00;
localparam RKEY_DEF   = 32'hffff_ff00;
localparam RMSK_DEF   = 32'hffff_ff00;


localparam    B2B_RXEQMIX = 2'b10;
localparam PERIPH_RXEQMIX = 2'b10;
localparam   RING_RXEQMIX = 2'b00;


localparam    B2B_TXDIFFCTRL = 4'b0110;


localparam PERIPH_TXDIFFCTRL = 4'b0110;
localparam   RING_TXDIFFCTRL = 4'b0000;

localparam    B2B_TXPREEMPHASIS = 3'b010;
localparam PERIPH_TXPREEMPHASIS = 3'b010;
localparam   RING_TXPREEMPHASIS = 3'b000;



localparam VERS_REG = 0;
localparam FLAG_REG = 1;





localparam PKEY_REG = 2;
localparam PMSK_REG = 3;
localparam SCRM_REG = 4;
localparam SLEN_REG = 5;
localparam LEDO_REG = 6;








localparam RXEQ_REG = 7;




localparam TXDS_REG = 8;




localparam TXPE_REG = 9;






localparam LKEY_REG = 12;
localparam LMSK_REG = 13;
localparam RKEY_REG = 14;
localparam RMSK_REG = 15;
localparam PIND_REG = 16;
localparam PINE_REG = 17;





reg [31:0] LC_MASK_TMP;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		LC_MASK <= LMSK_DEF;
	else
		if ((LC_WRITE_IN && (LC_ADDR_IN == LKEY_REG))
			|| (WRITE_IN && (ADDR_IN == LKEY_REG)))
			LC_MASK <= LC_MASK_TMP;



always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			SCRMBL_IDL_DAT <= SCRMBL_DEF;
			SPINNAKER_LINK_ENABLE <= LINKEN_DEF;
			LED_OVERRIDE <= LEDOVR_DEF;
			RXEQMIX <= {RING_RXEQMIX
			           , PERIPH_RXEQMIX
			           , B2B_RXEQMIX
			           , B2B_RXEQMIX
			           };
			TXDIFFCTRL <= {RING_TXDIFFCTRL
			              , PERIPH_TXDIFFCTRL
			              , B2B_TXDIFFCTRL
			              , B2B_TXDIFFCTRL
			              };
			TXPREEMPHASIS <= {RING_TXPREEMPHASIS
			                 , PERIPH_TXPREEMPHASIS
			                 , B2B_TXPREEMPHASIS
			                 , B2B_TXPREEMPHASIS
			                 };
		end
	else
		if (WRITE_IN)
			case (ADDR_IN)
				SCRM_REG: SCRMBL_IDL_DAT <= WRITE_DATA_IN;
				SLEN_REG: SPINNAKER_LINK_ENABLE <= WRITE_DATA_IN;
				LEDO_REG: LED_OVERRIDE <= WRITE_DATA_IN;
				RXEQ_REG: RXEQMIX <= WRITE_DATA_IN;
				TXDS_REG: TXDIFFCTRL <= WRITE_DATA_IN;
				TXPE_REG: TXPREEMPHASIS <= WRITE_DATA_IN;
			endcase



always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			PERIPH_MC_KEY  <= PKEY_DEF;
			PERIPH_MC_MASK <= PMSK_DEF;
			LC_KEY         <= LKEY_DEF;
			LC_MASK_TMP    <= LMSK_DEF;
			RC_KEY         <= RKEY_DEF;
			RC_MASK        <= RMSK_DEF;
			PERIPH_IN_EN   <= PINE_DEF;
		end
	else
		begin


			if (LC_WRITE_IN)
				case (LC_ADDR_IN)
					PKEY_REG: PERIPH_MC_KEY  <= LC_WR_DATA_IN;
					PMSK_REG: PERIPH_MC_MASK <= LC_WR_DATA_IN;
					LKEY_REG: LC_KEY         <= LC_WR_DATA_IN;
					LMSK_REG: LC_MASK_TMP    <= LC_WR_DATA_IN;
					RKEY_REG: RC_KEY         <= LC_WR_DATA_IN;
					RMSK_REG: RC_MASK        <= LC_WR_DATA_IN;
					PIND_REG: PERIPH_IN_EN   <= 1'b0;
					PINE_REG: PERIPH_IN_EN   <= 1'b1;
				endcase



			if (WRITE_IN && (!LC_WRITE_IN || (ADDR_IN != LC_ADDR_IN)))
				case (ADDR_IN)
					PKEY_REG: PERIPH_MC_KEY  <= WRITE_DATA_IN;
					PMSK_REG: PERIPH_MC_MASK <= WRITE_DATA_IN;
					LKEY_REG: LC_KEY         <= WRITE_DATA_IN;
					LMSK_REG: LC_MASK_TMP    <= WRITE_DATA_IN;
					RKEY_REG: RC_KEY         <= WRITE_DATA_IN;
					RMSK_REG: RC_MASK        <= WRITE_DATA_IN;
					PIND_REG: PERIPH_IN_EN   <= 1'b0;
					PINE_REG: PERIPH_IN_EN   <= 1'b1;
				endcase
		end


always @ (*)
	case (ADDR_IN)
		VERS_REG: READ_DATA_OUT = VERSION_IN;
		FLAG_REG: READ_DATA_OUT = FLAGS_IN;
		PKEY_REG: READ_DATA_OUT = PERIPH_MC_KEY;
		PMSK_REG: READ_DATA_OUT = PERIPH_MC_MASK;
		SCRM_REG: READ_DATA_OUT = SCRMBL_IDL_DAT;
		SLEN_REG: READ_DATA_OUT = SPINNAKER_LINK_ENABLE;
		LEDO_REG: READ_DATA_OUT = LED_OVERRIDE;
		RXEQ_REG: READ_DATA_OUT = RXEQMIX;
		TXDS_REG: READ_DATA_OUT = TXDIFFCTRL;
		TXPE_REG: READ_DATA_OUT = TXPREEMPHASIS;
		LKEY_REG: READ_DATA_OUT = LC_KEY;
		LMSK_REG: READ_DATA_OUT = LC_MASK;
		RKEY_REG: READ_DATA_OUT = RC_KEY;
		RMSK_REG: READ_DATA_OUT = RC_MASK;
		PIND_REG: READ_DATA_OUT = PERIPH_IN_EN;
		PINE_REG: READ_DATA_OUT = PERIPH_IN_EN;
		default:  READ_DATA_OUT = {REGD_BITS{1'b1}};
	endcase


endmodule
module spinnaker_fpgas_reg_bank #(
                                   parameter REGA_BITS = 14

                                 , parameter REGD_BITS = 32
                                 )
                                 ( input  wire CLK_IN
                                 , input  wire RESET_IN

                                 ,   input  wire                 WRITE_IN
                                 ,   input  wire [REGA_BITS-1:0] ADDR_IN
                                 ,   input  wire [REGD_BITS-1:0] WRITE_DATA_IN
                                 ,   output reg  [REGD_BITS-1:0] READ_DATA_OUT

                                 ,   input  wire                 LC_WRITE_IN
                                 ,   input  wire           [7:0] LC_ADDR_IN
                                 ,   input  wire [REGD_BITS-1:0] LC_WR_DATA_IN

                                 , input  wire   [REGD_BITS-1:0] VERSION_IN






                                 , input  wire             [5:0] FLAGS_IN

                                 , output reg             [31:0] SPINNAKER_LINK_ENABLE

                                 , output reg             [31:0] PERIPH_MC_KEY
                                 , output reg             [31:0] PERIPH_MC_MASK
                                 , output reg              [3:0] SCRMBL_IDL_DAT











                                 , output reg              [7:0] LED_OVERRIDE






                                 , output reg              [7:0] RXEQMIX






                                 , output reg             [15:0] TXDIFFCTRL






                                 , output reg             [11:0] TXPREEMPHASIS

                                 , output reg              [1:0] PERIPH_IN_EN

                                 , output reg             [31:0] LC_KEY
                                 , output reg             [31:0] LC_MASK

                                 , output reg             [31:0] RC_KEY
                                 , output reg             [31:0] RC_MASK
                                 );



localparam PKEY_DEF   = 32'hffff_ffff;
localparam PMSK_DEF   = 32'h0000_0000;
localparam SCRMBL_DEF =  4'hf;
localparam LINKEN_DEF = 32'h0000_0000;
localparam LEDOVR_DEF =  8'h0f;


localparam PINE_DEF   = 1'b0;
localparam LKEY_DEF   = 32'hffff_fe00;
localparam LMSK_DEF   = 32'hffff_ff00;
localparam RKEY_DEF   = 32'hffff_ff00;
localparam RMSK_DEF   = 32'hffff_ff00;


localparam    B2B_RXEQMIX = 2'b10;
localparam PERIPH_RXEQMIX = 2'b10;
localparam   RING_RXEQMIX = 2'b00;


localparam    B2B_TXDIFFCTRL = 4'b0110;


localparam PERIPH_TXDIFFCTRL = 4'b0110;
localparam   RING_TXDIFFCTRL = 4'b0000;

localparam    B2B_TXPREEMPHASIS = 3'b010;
localparam PERIPH_TXPREEMPHASIS = 3'b010;
localparam   RING_TXPREEMPHASIS = 3'b000;



localparam VERS_REG = 0;
localparam FLAG_REG = 1;





localparam PKEY_REG = 2;
localparam PMSK_REG = 3;
localparam SCRM_REG = 4;
localparam SLEN_REG = 5;
localparam LEDO_REG = 6;








localparam RXEQ_REG = 7;




localparam TXDS_REG = 8;




localparam TXPE_REG = 9;






localparam LKEY_REG = 12;
localparam LMSK_REG = 13;
localparam RKEY_REG = 14;
localparam RMSK_REG = 15;
localparam PIND_REG = 16;
localparam PINE_REG = 17;





reg [31:0] LC_MASK_TMP;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		LC_MASK <= LMSK_DEF;
	else
		if ((LC_WRITE_IN && (LC_ADDR_IN == LKEY_REG))
			|| (WRITE_IN && (ADDR_IN == LKEY_REG)))
			LC_MASK <= LC_MASK_TMP;



always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			SCRMBL_IDL_DAT <= SCRMBL_DEF;
			SPINNAKER_LINK_ENABLE <= LINKEN_DEF;
			LED_OVERRIDE <= LEDOVR_DEF;
			RXEQMIX <= {RING_RXEQMIX
			           , PERIPH_RXEQMIX
			           , B2B_RXEQMIX
			           , B2B_RXEQMIX
			           };
			TXDIFFCTRL <= {RING_TXDIFFCTRL
			              , PERIPH_TXDIFFCTRL
			              , B2B_TXDIFFCTRL
			              , B2B_TXDIFFCTRL
			              };
			TXPREEMPHASIS <= {RING_TXPREEMPHASIS
			                 , PERIPH_TXPREEMPHASIS
			                 , B2B_TXPREEMPHASIS
			                 , B2B_TXPREEMPHASIS
			                 };
		end
	else
		if (WRITE_IN)
			case (ADDR_IN)
				SCRM_REG: SCRMBL_IDL_DAT <= WRITE_DATA_IN;
				SLEN_REG: SPINNAKER_LINK_ENABLE <= WRITE_DATA_IN;
				LEDO_REG: LED_OVERRIDE <= WRITE_DATA_IN;
				RXEQ_REG: RXEQMIX <= WRITE_DATA_IN;
				TXDS_REG: TXDIFFCTRL <= WRITE_DATA_IN;
				TXPE_REG: TXPREEMPHASIS <= WRITE_DATA_IN;
			endcase



always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			PERIPH_MC_KEY  <= PKEY_DEF;
			PERIPH_MC_MASK <= PMSK_DEF;
			LC_KEY         <= LKEY_DEF;
			LC_MASK_TMP    <= LMSK_DEF;
			RC_KEY         <= RKEY_DEF;
			RC_MASK        <= RMSK_DEF;
			PERIPH_IN_EN   <= PINE_DEF;
		end
	else
		begin


			if (LC_WRITE_IN)
				case (LC_ADDR_IN)
					PKEY_REG: PERIPH_MC_KEY  <= LC_WR_DATA_IN;
					PMSK_REG: PERIPH_MC_MASK <= LC_WR_DATA_IN;
					LKEY_REG: LC_KEY         <= LC_WR_DATA_IN;
					LMSK_REG: LC_MASK_TMP    <= LC_WR_DATA_IN;
					RKEY_REG: RC_KEY         <= LC_WR_DATA_IN;
					RMSK_REG: RC_MASK        <= LC_WR_DATA_IN;
					PIND_REG: PERIPH_IN_EN   <= 1'b0;
					PINE_REG: PERIPH_IN_EN   <= 1'b1;
				endcase



			if (WRITE_IN && (!LC_WRITE_IN || (ADDR_IN != LC_ADDR_IN)))
				case (ADDR_IN)
					PKEY_REG: PERIPH_MC_KEY  <= WRITE_DATA_IN;
					PMSK_REG: PERIPH_MC_MASK <= WRITE_DATA_IN;
					LKEY_REG: LC_KEY         <= WRITE_DATA_IN;
					LMSK_REG: LC_MASK_TMP    <= WRITE_DATA_IN;
					RKEY_REG: RC_KEY         <= WRITE_DATA_IN;
					RMSK_REG: RC_MASK        <= WRITE_DATA_IN;
					PIND_REG: PERIPH_IN_EN   <= 1'b0;
					PINE_REG: PERIPH_IN_EN   <= 1'b1;
				endcase
		end


always @ (*)
	case (ADDR_IN)
		VERS_REG: READ_DATA_OUT = VERSION_IN;
		FLAG_REG: READ_DATA_OUT = FLAGS_IN;
		PKEY_REG: READ_DATA_OUT = PERIPH_MC_KEY;
		PMSK_REG: READ_DATA_OUT = PERIPH_MC_MASK;
		SCRM_REG: READ_DATA_OUT = SCRMBL_IDL_DAT;
		SLEN_REG: READ_DATA_OUT = SPINNAKER_LINK_ENABLE;
		LEDO_REG: READ_DATA_OUT = LED_OVERRIDE;
		RXEQ_REG: READ_DATA_OUT = RXEQMIX;
		TXDS_REG: READ_DATA_OUT = TXDIFFCTRL;
		TXPE_REG: READ_DATA_OUT = TXPREEMPHASIS;
		LKEY_REG: READ_DATA_OUT = LC_KEY;
		LMSK_REG: READ_DATA_OUT = LC_MASK;
		RKEY_REG: READ_DATA_OUT = RC_KEY;
		RMSK_REG: READ_DATA_OUT = RC_MASK;
		PIND_REG: READ_DATA_OUT = PERIPH_IN_EN;
		PINE_REG: READ_DATA_OUT = PERIPH_IN_EN;
		default:  READ_DATA_OUT = {REGD_BITS{1'b1}};
	endcase


endmodule