data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/verilog_utils/verilog_utils.vh
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/aabd5c03-4a88-447b-b789-4cd0c249383c.xml
function integer ff1;
input integer in;
input integer width;
integer i;
begin
	ff1 = 0;
	for (i = width-1; i >= 0; i=i-1) begin
		if (in[i])
			ff1 = i;
	end
end
endfunction
function integer ff1;

input integer in;
input integer width;
integer i;
begin
	ff1 = 0;
	for (i = width-1; i >= 0; i=i-1) begin
		if (in[i])
			ff1 = i;
	end
end
endfunction