data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/mux_testbench.v
 line:26: before: "$"
1: b'%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/mux_testbench.v:14: Unsupported or unknown PLI call: $monitor\n    $monitor(sel, in1, in2, out);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/mux_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/mux_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_testbench;

reg sel;
reg [31:0] in1;
reg [31:0] in2;
wire [31:0] out;

mux uut(.sel(sel), .in1(in1), .in2(in2), .out(out));

initial begin
    
    $monitor(sel, in1, in2, out);
    

    in1=32'd64;
    in2=32'd32;
    

    sel=0;
    #5

    sel=1;
    #5
    $finish;
end
endmodule
module mux_testbench;


reg sel;
reg [31:0] in1;
reg [31:0] in2;
wire [31:0] out;

mux uut(.sel(sel), .in1(in1), .in2(in2), .out(out));

initial begin
    
    $monitor(sel, in1, in2, out);
    

    in1=32'd64;
    in2=32'd32;
    

    sel=0;
    #5

    sel=1;
    #5
    $finish;
end
endmodule