data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:54: Cannot find include file: vh/n64a_params.vh\n`include "vh/n64a_params.vh" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl,data/full_repos/permissive/118480210/vh/n64a_params.vh\n             data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl,data/full_repos/permissive/118480210/vh/n64a_params.vh.v\n             data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl,data/full_repos/permissive/118480210/vh/n64a_params.vh.sv\n             vh/n64a_params.vh\n             vh/n64a_params.vh.v\n             vh/n64a_params.vh.sv\n             obj_dir/vh/n64a_params.vh\n             obj_dir/vh/n64a_params.vh.v\n             obj_dir/vh/n64a_params.vh.sv\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:64: Define or directive not defined: \'`VDATA_I_FU_SLICE\'\ninput  [`VDATA_I_FU_SLICE] vdata_i;\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:64: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\ninput  [`VDATA_I_FU_SLICE] vdata_i;\n                         ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:65: Define or directive not defined: \'`VDATA_O_FU_SLICE\'\noutput [`VDATA_O_FU_SLICE] vdata_o;\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\noutput [`VDATA_O_FU_SLICE] vdata_o;\n                         ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:73: Define or directive not defined: \'`VDATA_I_RE_SLICE\'\nwire [color_width_i-1:0] R_i = vdata_i[`VDATA_I_RE_SLICE];\n                                       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:73: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [color_width_i-1:0] R_i = vdata_i[`VDATA_I_RE_SLICE];\n                                                        ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:74: Define or directive not defined: \'`VDATA_I_GR_SLICE\'\nwire [color_width_i-1:0] G_i = vdata_i[`VDATA_I_GR_SLICE];\n                                       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:74: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [color_width_i-1:0] G_i = vdata_i[`VDATA_I_GR_SLICE];\n                                                        ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:75: Define or directive not defined: \'`VDATA_I_BL_SLICE\'\nwire [color_width_i-1:0] B_i = vdata_i[`VDATA_I_BL_SLICE];\n                                       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:75: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [color_width_i-1:0] B_i = vdata_i[`VDATA_I_BL_SLICE];\n                                                        ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:105: Define or directive not defined: \'`HSTART_NTSC_480I\'\nreg [ram_depth-1:0] hstart = `HSTART_NTSC_480I;\n                             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nreg [ram_depth-1:0] hstart = `HSTART_NTSC_480I;\n                                              ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:106: Define or directive not defined: \'`HSTOP_NTSC\'\nreg [ram_depth-1:0] hstop  = `HSTOP_NTSC;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:106: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nreg [ram_depth-1:0] hstop  = `HSTOP_NTSC;\n                                        ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:108: Define or directive not defined: \'`HS_WIDTH_NTSC_480I\'\nreg [6:0] nHS_width = `HS_WIDTH_NTSC_480I;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nreg [6:0] nHS_width = `HS_WIDTH_NTSC_480I;\n                                         ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:148: Define or directive not defined: \'`HSTART_NTSC_240P\'\n            hstart    <= `HSTART_NTSC_240P;\n                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:148: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            hstart    <= `HSTART_NTSC_240P;\n                                          ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:149: Define or directive not defined: \'`HSTOP_NTSC\'\n            hstop     <= `HSTOP_NTSC;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:149: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            hstop     <= `HSTOP_NTSC;\n                                    ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:150: Define or directive not defined: \'`HS_WIDTH_NTSC_240P\'\n            nHS_width <= `HS_WIDTH_NTSC_240P;\n                         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:150: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            nHS_width <= `HS_WIDTH_NTSC_240P;\n                                            ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:153: Define or directive not defined: \'`HSTART_NTSC_480I\'\n            hstart    <= `HSTART_NTSC_480I;\n                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:153: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            hstart    <= `HSTART_NTSC_480I;\n                                          ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:154: Define or directive not defined: \'`HSTOP_NTSC\'\n            hstop     <= `HSTOP_NTSC;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:154: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            hstop     <= `HSTOP_NTSC;\n                                    ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:155: Define or directive not defined: \'`HS_WIDTH_NTSC_480I\'\n            nHS_width <= `HS_WIDTH_NTSC_480I;\n                         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:155: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            nHS_width <= `HS_WIDTH_NTSC_480I;\n                                            ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:158: Define or directive not defined: \'`HSTART_PAL_288P\'\n            hstart    <= `HSTART_PAL_288P;\n                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:158: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            hstart    <= `HSTART_PAL_288P;\n                                         ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:159: Define or directive not defined: \'`HSTOP_PAL\'\n            hstop     <= `HSTOP_PAL;\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:159: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            hstop     <= `HSTOP_PAL;\n                                   ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:160: Define or directive not defined: \'`HS_WIDTH_PAL_288P\'\n            nHS_width <= `HS_WIDTH_PAL_288P;\n                         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:160: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            nHS_width <= `HS_WIDTH_PAL_288P;\n                                           ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:163: Define or directive not defined: \'`HSTART_PAL_576I\'\n            hstart    <= `HSTART_PAL_576I;\n                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:163: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            hstart    <= `HSTART_PAL_576I;\n                                         ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:164: Define or directive not defined: \'`HSTOP_PAL\'\n            hstop     <= `HSTOP_PAL;\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:164: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            hstop     <= `HSTOP_PAL;\n                                   ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:165: Define or directive not defined: \'`HS_WIDTH_PAL_576I\'\n            nHS_width <= `HS_WIDTH_PAL_576I;\n                         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:165: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            nHS_width <= `HS_WIDTH_PAL_576I;\n                                           ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:302: Define or directive not defined: \'`VS_WIDTH\'\n      nVS_cnt  <= `VS_WIDTH;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:302: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      nVS_cnt  <= `VS_WIDTH;\n                           ^\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:365: Define or directive not defined: \'`VDATA_I_SY_SLICE\'\n    S_o <= vdata_i[`VDATA_I_SY_SLICE];\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118480210/advancedRGBmod/firmware/rtl/n64a_linedbl.v:365: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    S_o <= vdata_i[`VDATA_I_SY_SLICE];\n                                    ^\n%Error: Exiting due to 45 error(s)\n'
module n64a_linedbl(
  nCLK_in,
  CLK_out,
  nRST,

  vinfo_dbl,

  vdata_i,
  vdata_o
);

`include "vh/n64a_params.vh"

localparam ram_depth = 11;

input  nCLK_in;
output CLK_out;
input  nRST;

input [4:0] vinfo_dbl;

input  [`VDATA_I_FU_SLICE] vdata_i;
output [`VDATA_O_FU_SLICE] vdata_o;




wire nVS_i = vdata_i[3*color_width_i+3];
wire nHS_i = vdata_i[3*color_width_i+1];

wire [color_width_i-1:0] R_i = vdata_i[`VDATA_I_RE_SLICE];
wire [color_width_i-1:0] G_i = vdata_i[`VDATA_I_GR_SLICE];
wire [color_width_i-1:0] B_i = vdata_i[`VDATA_I_BL_SLICE];


wire nENABLE_linedbl = vinfo_dbl[4] | ~rdrun[1];
wire [1:0]    SL_str = vinfo_dbl[3:2];

wire pal_mode = vinfo_dbl[1];
wire n64_480i = vinfo_dbl[0];




reg div_2x = 1'b0;

always @(negedge nCLK_in) begin
  div_2x <= ~div_2x;
end


wire PX_CLK_4x, PLL_locked;
altpll_0 vid_pll(
  .inclk0(nCLK_in),
  .areset(~nRST),
  .locked(PLL_locked),
  .c0(PX_CLK_4x)
);

wire RST = ~(nRST && PLL_locked);


reg [ram_depth-1:0] hstart = `HSTART_NTSC_480I;
reg [ram_depth-1:0] hstop  = `HSTOP_NTSC;

reg [6:0] nHS_width = `HS_WIDTH_NTSC_480I;


reg                 wren   = 1'b0;
reg                 wrline = 1'b0;
reg [ram_depth-1:0] wrhcnt = {ram_depth{1'b1}};
reg [ram_depth-1:0] wraddr = {ram_depth{1'b0}};

wire line_overflow = &{wrhcnt[ram_depth-1],wrhcnt[ram_depth-2],wrhcnt[ram_depth-5]};
wire valid_line    = wrhcnt > hstop;


reg [ram_depth-1:0] line_width[0:1];
initial begin
   line_width[1] = {ram_depth{1'b0}};
   line_width[0] = {ram_depth{1'b0}};
end

reg  nVS_i_buf = 1'b0;
reg  nHS_i_buf = 1'b0;


reg [1:0]     newFrame = 2'b0;
reg [1:0] start_rdproc = 2'b00;
reg [1:0]  stop_rdproc = 2'b00;


always @(negedge nCLK_in) begin
  if (~div_2x) begin
    if (nVS_i_buf & ~nVS_i) begin

      newFrame[0] <= ~newFrame[1];


      if (&{nHS_i_buf,~nHS_i,~line_overflow,valid_line})
        start_rdproc[0] <= ~start_rdproc[1];


      case({pal_mode,n64_480i})
        2'b00: begin
            hstart    <= `HSTART_NTSC_240P;
            hstop     <= `HSTOP_NTSC;
            nHS_width <= `HS_WIDTH_NTSC_240P;
          end
        2'b01: begin
            hstart    <= `HSTART_NTSC_480I;
            hstop     <= `HSTOP_NTSC;
            nHS_width <= `HS_WIDTH_NTSC_480I;
          end
        2'b10: begin
            hstart    <= `HSTART_PAL_288P;
            hstop     <= `HSTOP_PAL;
            nHS_width <= `HS_WIDTH_PAL_288P;
          end
        2'b11: begin
            hstart    <= `HSTART_PAL_576I;
            hstop     <= `HSTOP_PAL;
            nHS_width <= `HS_WIDTH_PAL_576I;
          end
      endcase
    end

    if (nHS_i_buf & ~nHS_i) begin
      line_width[wrline] <= wrhcnt[ram_depth-1:0];

      wrhcnt <= {ram_depth{1'b0}};
      wrline <= ~wrline;
    end else if (~line_overflow) begin
      wrhcnt <= wrhcnt + 1'b1;
    end

    if (wrhcnt == hstart) begin
      wren   <= 1'b1;
      wraddr <= {ram_depth{1'b0}};
    end else if (wrhcnt > hstart && wrhcnt < hstop) begin
      wraddr <= wraddr + 1'b1;
    end else begin
      wren   <= 1'b0;
      wraddr <= {ram_depth{1'b0}};
    end

    nVS_i_buf <= nVS_i;
    nHS_i_buf <= nHS_i;
  end

  if (RST) begin
        newFrame[0] <= newFrame[1];
    start_rdproc[0] <= start_rdproc[1];
     stop_rdproc[0] <= ~stop_rdproc[1];

    wren   <= 1'b0;
    wrline <= 1'b0;
    wrhcnt <= {ram_depth{1'b1}};
  end
end


reg           [2:0] rden     = 3'b0;
reg           [1:0] rdrun    = 2'b00;
reg                 rdcnt    = 1'b0;
reg                 rdline   = 1'b0;
reg [ram_depth-1:0] rdhcnt   = {ram_depth{1'b1}};
reg [ram_depth-1:0] rdaddr   = {ram_depth{1'b0}};

always @(posedge PX_CLK_4x) begin
  if (rdrun[1]) begin
    if (rdhcnt == line_width[rdline]) begin
      rdhcnt   <= {ram_depth{1'b0}};
      if (rdcnt)
        rdline <= ~wrline;
      rdcnt <= ~rdcnt;
    end else begin
      rdhcnt <= rdhcnt + 1'b1;
    end
    if (line_overflow || &{nHS_i_buf,~nHS_i,~valid_line}) begin
      rdrun <= 2'b00;
    end

    if (rdhcnt == hstart) begin
      rden[0] <= 1'b1;
      rdaddr  <= {ram_depth{1'b0}};
    end else if (rdhcnt > hstart && rdhcnt < hstop) begin
      rdaddr <= rdaddr + 1'b1;
    end else begin
      rden[0] <= 1'b0;
      rdaddr  <= {ram_depth{1'b0}};
    end
  end else if (rdrun[0] && wrhcnt[3]) begin
    rdrun[1] <= 1'b1;
    rdcnt    <= 1'b0;
    rdline   <= ~wrline;
    rdhcnt   <= {ram_depth{1'b0}};
  end else if (^start_rdproc) begin
    rdrun[0] <= 1'b1;
  end
  
  rden[2:1] <= rden[1:0];

  if (^stop_rdproc) begin
    rden  <= 3'b0;
    rdrun <= 2'b0;
  end

  start_rdproc[1] <= start_rdproc[0];
   stop_rdproc[1] <=  stop_rdproc[0];
end


wire [color_width_i-1:0] R_buf[0:1], G_buf[0:1], B_buf[0:1];

ram2port_0 videobuffer_0(
  .data({R_i,G_i,B_i}),
  .rdaddress(rdaddr),
  .rdclock(PX_CLK_4x),
  .rden(&{rden[0],~rdline}),
  .wraddress(wraddr),
  .wrclock(~nCLK_in),
  .wren(&{wren,~wrline,~line_overflow,~div_2x}),
  .q({R_buf[0],G_buf[0],B_buf[0]})
);

ram2port_0 videobuffer_1(
  .data({R_i,G_i,B_i}),
  .rdaddress(rdaddr),
  .rdclock(PX_CLK_4x),
  .rden(&{rden[0],rdline}),
  .wraddress(wraddr),
  .wrclock(~nCLK_in),
  .wren(&{wren,wrline,~line_overflow,~div_2x}),
  .q({R_buf[1],G_buf[1],B_buf[1]})
);


reg     rdcnt_buf = 1'b0;
reg [7:0] nHS_cnt = 8'd0;
reg [1:0] nVS_cnt = 2'b0;

wire CSen_lineend = ((rdhcnt + 2'b11) > (line_width[rdline] - nHS_width));

reg               [3:0] S_o;
reg [color_width_o-1:0] R_o;
reg [color_width_o-1:0] G_o;
reg [color_width_o-1:0] B_o;

always @(posedge PX_CLK_4x) begin

  if (rdcnt_buf ^ rdcnt) begin
    S_o[0] <= 1'b0;
    S_o[1] <= 1'b0;
    S_o[2] <= 1'b1;

    nHS_cnt <= nHS_width;

    if (^newFrame) begin
      nVS_cnt  <= `VS_WIDTH;
      S_o[3]   <= 1'b0;
      newFrame[1] <= newFrame[0];
    end else if (|nVS_cnt) begin
      nVS_cnt <= nVS_cnt - 1'b1;
    end else begin
      S_o[3] <= 1'b1;
    end
  end else begin
    if (|nHS_cnt) begin
      nHS_cnt <= nHS_cnt - 1'b1;
    end else begin
      S_o[1] <= 1'b1;
      if (S_o[3])
        S_o[0] <= 1'b1;
    end
    
    if (CSen_lineend) begin
      S_o[0] <= 1'b1;
    end
  end

    rdcnt_buf <= rdcnt;

    if (rden[2]) begin
      if (rdcnt) begin
        case (SL_str)
          2'b11: begin
            R_o <= {R_buf[rdline],1'b0};
            G_o <= {G_buf[rdline],1'b0};
            B_o <= {B_buf[rdline],1'b0};
          end
          2'b10: begin
            R_o <= {1'b0 ,R_buf[rdline][color_width_i-1:0]} +
                   {2'b00,R_buf[rdline][color_width_i-1:1]};
            G_o <= {1'b0 ,G_buf[rdline][color_width_i-1:0]} +
                   {2'b00,G_buf[rdline][color_width_i-1:1]};
            B_o <= {1'b0 ,B_buf[rdline][color_width_i-1:0]} +
                   {2'b00,B_buf[rdline][color_width_i-1:1]};
          end
          2'b01: begin
            R_o <= {1'b0,R_buf[rdline][color_width_i-1:0]};
            G_o <= {1'b0,G_buf[rdline][color_width_i-1:0]};
            B_o <= {1'b0,B_buf[rdline][color_width_i-1:0]};
          end
          2'b00: begin
            R_o <= {color_width_o{1'b0}};
            G_o <= {color_width_o{1'b0}};
            B_o <= {color_width_o{1'b0}};
          end
        endcase
      end else begin
        R_o <= {R_buf[rdline],1'b0};
        G_o <= {G_buf[rdline],1'b0};
        B_o <= {B_buf[rdline],1'b0};
      end
    end else begin
      R_o <= {color_width_o{1'b0}};
      G_o <= {color_width_o{1'b0}};
      B_o <= {color_width_o{1'b0}};
    end

  if (nENABLE_linedbl) begin
    S_o <= vdata_i[`VDATA_I_SY_SLICE];
    R_o <= {R_i,1'b0};
    G_o <= {G_i,1'b0};
    B_o <= {B_i,1'b0};
  end
end




assign CLK_out = PX_CLK_4x;
assign vdata_o = {S_o,R_o,G_o,B_o};

endmodule
module n64a_linedbl(
  nCLK_in,
  CLK_out,
  nRST,

  vinfo_dbl,

  vdata_i,
  vdata_o
);


`include "vh/n64a_params.vh"

localparam ram_depth = 11;

input  nCLK_in;
output CLK_out;
input  nRST;

input [4:0] vinfo_dbl;

input  [`VDATA_I_FU_SLICE] vdata_i;
output [`VDATA_O_FU_SLICE] vdata_o;




wire nVS_i = vdata_i[3*color_width_i+3];
wire nHS_i = vdata_i[3*color_width_i+1];

wire [color_width_i-1:0] R_i = vdata_i[`VDATA_I_RE_SLICE];
wire [color_width_i-1:0] G_i = vdata_i[`VDATA_I_GR_SLICE];
wire [color_width_i-1:0] B_i = vdata_i[`VDATA_I_BL_SLICE];


wire nENABLE_linedbl = vinfo_dbl[4] | ~rdrun[1];
wire [1:0]    SL_str = vinfo_dbl[3:2];

wire pal_mode = vinfo_dbl[1];
wire n64_480i = vinfo_dbl[0];




reg div_2x = 1'b0;

always @(negedge nCLK_in) begin
  div_2x <= ~div_2x;
end


wire PX_CLK_4x, PLL_locked;
altpll_0 vid_pll(
  .inclk0(nCLK_in),
  .areset(~nRST),
  .locked(PLL_locked),
  .c0(PX_CLK_4x)
);

wire RST = ~(nRST && PLL_locked);


reg [ram_depth-1:0] hstart = `HSTART_NTSC_480I;
reg [ram_depth-1:0] hstop  = `HSTOP_NTSC;

reg [6:0] nHS_width = `HS_WIDTH_NTSC_480I;


reg                 wren   = 1'b0;
reg                 wrline = 1'b0;
reg [ram_depth-1:0] wrhcnt = {ram_depth{1'b1}};
reg [ram_depth-1:0] wraddr = {ram_depth{1'b0}};

wire line_overflow = &{wrhcnt[ram_depth-1],wrhcnt[ram_depth-2],wrhcnt[ram_depth-5]};
wire valid_line    = wrhcnt > hstop;


reg [ram_depth-1:0] line_width[0:1];
initial begin
   line_width[1] = {ram_depth{1'b0}};
   line_width[0] = {ram_depth{1'b0}};
end

reg  nVS_i_buf = 1'b0;
reg  nHS_i_buf = 1'b0;


reg [1:0]     newFrame = 2'b0;
reg [1:0] start_rdproc = 2'b00;
reg [1:0]  stop_rdproc = 2'b00;


always @(negedge nCLK_in) begin
  if (~div_2x) begin
    if (nVS_i_buf & ~nVS_i) begin

      newFrame[0] <= ~newFrame[1];


      if (&{nHS_i_buf,~nHS_i,~line_overflow,valid_line})
        start_rdproc[0] <= ~start_rdproc[1];


      case({pal_mode,n64_480i})
        2'b00: begin
            hstart    <= `HSTART_NTSC_240P;
            hstop     <= `HSTOP_NTSC;
            nHS_width <= `HS_WIDTH_NTSC_240P;
          end
        2'b01: begin
            hstart    <= `HSTART_NTSC_480I;
            hstop     <= `HSTOP_NTSC;
            nHS_width <= `HS_WIDTH_NTSC_480I;
          end
        2'b10: begin
            hstart    <= `HSTART_PAL_288P;
            hstop     <= `HSTOP_PAL;
            nHS_width <= `HS_WIDTH_PAL_288P;
          end
        2'b11: begin
            hstart    <= `HSTART_PAL_576I;
            hstop     <= `HSTOP_PAL;
            nHS_width <= `HS_WIDTH_PAL_576I;
          end
      endcase
    end

    if (nHS_i_buf & ~nHS_i) begin
      line_width[wrline] <= wrhcnt[ram_depth-1:0];

      wrhcnt <= {ram_depth{1'b0}};
      wrline <= ~wrline;
    end else if (~line_overflow) begin
      wrhcnt <= wrhcnt + 1'b1;
    end

    if (wrhcnt == hstart) begin
      wren   <= 1'b1;
      wraddr <= {ram_depth{1'b0}};
    end else if (wrhcnt > hstart && wrhcnt < hstop) begin
      wraddr <= wraddr + 1'b1;
    end else begin
      wren   <= 1'b0;
      wraddr <= {ram_depth{1'b0}};
    end

    nVS_i_buf <= nVS_i;
    nHS_i_buf <= nHS_i;
  end

  if (RST) begin
        newFrame[0] <= newFrame[1];
    start_rdproc[0] <= start_rdproc[1];
     stop_rdproc[0] <= ~stop_rdproc[1];

    wren   <= 1'b0;
    wrline <= 1'b0;
    wrhcnt <= {ram_depth{1'b1}};
  end
end


reg           [2:0] rden     = 3'b0;
reg           [1:0] rdrun    = 2'b00;
reg                 rdcnt    = 1'b0;
reg                 rdline   = 1'b0;
reg [ram_depth-1:0] rdhcnt   = {ram_depth{1'b1}};
reg [ram_depth-1:0] rdaddr   = {ram_depth{1'b0}};

always @(posedge PX_CLK_4x) begin
  if (rdrun[1]) begin
    if (rdhcnt == line_width[rdline]) begin
      rdhcnt   <= {ram_depth{1'b0}};
      if (rdcnt)
        rdline <= ~wrline;
      rdcnt <= ~rdcnt;
    end else begin
      rdhcnt <= rdhcnt + 1'b1;
    end
    if (line_overflow || &{nHS_i_buf,~nHS_i,~valid_line}) begin
      rdrun <= 2'b00;
    end

    if (rdhcnt == hstart) begin
      rden[0] <= 1'b1;
      rdaddr  <= {ram_depth{1'b0}};
    end else if (rdhcnt > hstart && rdhcnt < hstop) begin
      rdaddr <= rdaddr + 1'b1;
    end else begin
      rden[0] <= 1'b0;
      rdaddr  <= {ram_depth{1'b0}};
    end
  end else if (rdrun[0] && wrhcnt[3]) begin
    rdrun[1] <= 1'b1;
    rdcnt    <= 1'b0;
    rdline   <= ~wrline;
    rdhcnt   <= {ram_depth{1'b0}};
  end else if (^start_rdproc) begin
    rdrun[0] <= 1'b1;
  end
  
  rden[2:1] <= rden[1:0];

  if (^stop_rdproc) begin
    rden  <= 3'b0;
    rdrun <= 2'b0;
  end

  start_rdproc[1] <= start_rdproc[0];
   stop_rdproc[1] <=  stop_rdproc[0];
end


wire [color_width_i-1:0] R_buf[0:1], G_buf[0:1], B_buf[0:1];

ram2port_0 videobuffer_0(
  .data({R_i,G_i,B_i}),
  .rdaddress(rdaddr),
  .rdclock(PX_CLK_4x),
  .rden(&{rden[0],~rdline}),
  .wraddress(wraddr),
  .wrclock(~nCLK_in),
  .wren(&{wren,~wrline,~line_overflow,~div_2x}),
  .q({R_buf[0],G_buf[0],B_buf[0]})
);

ram2port_0 videobuffer_1(
  .data({R_i,G_i,B_i}),
  .rdaddress(rdaddr),
  .rdclock(PX_CLK_4x),
  .rden(&{rden[0],rdline}),
  .wraddress(wraddr),
  .wrclock(~nCLK_in),
  .wren(&{wren,wrline,~line_overflow,~div_2x}),
  .q({R_buf[1],G_buf[1],B_buf[1]})
);


reg     rdcnt_buf = 1'b0;
reg [7:0] nHS_cnt = 8'd0;
reg [1:0] nVS_cnt = 2'b0;

wire CSen_lineend = ((rdhcnt + 2'b11) > (line_width[rdline] - nHS_width));

reg               [3:0] S_o;
reg [color_width_o-1:0] R_o;
reg [color_width_o-1:0] G_o;
reg [color_width_o-1:0] B_o;

always @(posedge PX_CLK_4x) begin

  if (rdcnt_buf ^ rdcnt) begin
    S_o[0] <= 1'b0;
    S_o[1] <= 1'b0;
    S_o[2] <= 1'b1;

    nHS_cnt <= nHS_width;

    if (^newFrame) begin
      nVS_cnt  <= `VS_WIDTH;
      S_o[3]   <= 1'b0;
      newFrame[1] <= newFrame[0];
    end else if (|nVS_cnt) begin
      nVS_cnt <= nVS_cnt - 1'b1;
    end else begin
      S_o[3] <= 1'b1;
    end
  end else begin
    if (|nHS_cnt) begin
      nHS_cnt <= nHS_cnt - 1'b1;
    end else begin
      S_o[1] <= 1'b1;
      if (S_o[3])
        S_o[0] <= 1'b1;
    end
    
    if (CSen_lineend) begin
      S_o[0] <= 1'b1;
    end
  end

    rdcnt_buf <= rdcnt;

    if (rden[2]) begin
      if (rdcnt) begin
        case (SL_str)
          2'b11: begin
            R_o <= {R_buf[rdline],1'b0};
            G_o <= {G_buf[rdline],1'b0};
            B_o <= {B_buf[rdline],1'b0};
          end
          2'b10: begin
            R_o <= {1'b0 ,R_buf[rdline][color_width_i-1:0]} +
                   {2'b00,R_buf[rdline][color_width_i-1:1]};
            G_o <= {1'b0 ,G_buf[rdline][color_width_i-1:0]} +
                   {2'b00,G_buf[rdline][color_width_i-1:1]};
            B_o <= {1'b0 ,B_buf[rdline][color_width_i-1:0]} +
                   {2'b00,B_buf[rdline][color_width_i-1:1]};
          end
          2'b01: begin
            R_o <= {1'b0,R_buf[rdline][color_width_i-1:0]};
            G_o <= {1'b0,G_buf[rdline][color_width_i-1:0]};
            B_o <= {1'b0,B_buf[rdline][color_width_i-1:0]};
          end
          2'b00: begin
            R_o <= {color_width_o{1'b0}};
            G_o <= {color_width_o{1'b0}};
            B_o <= {color_width_o{1'b0}};
          end
        endcase
      end else begin
        R_o <= {R_buf[rdline],1'b0};
        G_o <= {G_buf[rdline],1'b0};
        B_o <= {B_buf[rdline],1'b0};
      end
    end else begin
      R_o <= {color_width_o{1'b0}};
      G_o <= {color_width_o{1'b0}};
      B_o <= {color_width_o{1'b0}};
    end

  if (nENABLE_linedbl) begin
    S_o <= vdata_i[`VDATA_I_SY_SLICE];
    R_o <= {R_i,1'b0};
    G_o <= {G_i,1'b0};
    B_o <= {B_i,1'b0};
  end
end




assign CLK_out = PX_CLK_4x;
assign vdata_o = {S_o,R_o,G_o,B_o};

endmodule