data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/PID_tb.v
 line:139: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/PID_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/PID_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10 rst=0;\n ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/PID_tb.v:185: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/PID_tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function of_check_16bit;
	input 	[15:0]a,b;
	begin
		s=a+b;
		of_check_16bit=(a[15]&b[15]&(~s[15]))|((~a[15])&(~b[15])&s[15]);
	end
endfunction
function of_check_16bit;

	input 	[15:0]a,b;
	begin
		s=a+b;
		of_check_16bit=(a[15]&b[15]&(~s[15]))|((~a[15])&(~b[15])&s[15]);
	end
endfunction