data/full_repos/permissive/135475029/lab_6/src/bad_ALU.v
data/verilator_xmls/c99067ca-32d1-4242-bf68-24755c1a529c.xml
module bad_ALU(
  input [3:0] aluop,
	input [31:0] a, b,
	output [31:0] result,
	output zero
	);

   reg [31:0]		slt;
   reg [31:0]		logicsel;

   reg [31:0]		alu_val;
   reg [31:0]		diff;
   wire				ss0;
   wire 				ss1;
   wire 				ss2;
   wire 				ss3;

	assign {ss0,ss1,ss2,ss3} = aluop;


	always @ ( * )
	begin
	   if (ss1 == 1)
	       if (ss2 == 0)
	           if (ss3 == 0)
	               logicsel = a & b;
	           else
	               logicsel = a | b;
	       else
	           if (ss3 == 1)
	               logicsel = ~(a | b);
	           else
	               logicsel = a ^ b;
     end

	always @ ( aluop , a, b )
		if (aluop == 4'b1010)
		begin
			diff = a - b;
			slt = 0;
			if (diff[31] == 1)
				slt = 1;
		end

	always @ ( * )
	begin
		case (aluop)
			4'b0000 : alu_val = a + b;
			4'b0010 : alu_val = a - b;
			4'b1010 : alu_val = slt;
			default : alu_val = logicsel;
		endcase
	end

	assign result = alu_val;
	assign zero = (alu_val == 32'b0) ? 1: 0;

endmodule
module bad_ALU(
  input [3:0] aluop,
	input [31:0] a, b,
	output [31:0] result,
	output zero
	);


   reg [31:0]		slt;
   reg [31:0]		logicsel;

   reg [31:0]		alu_val;
   reg [31:0]		diff;
   wire				ss0;
   wire 				ss1;
   wire 				ss2;
   wire 				ss3;

	assign {ss0,ss1,ss2,ss3} = aluop;


	always @ ( * )
	begin
	   if (ss1 == 1)
	       if (ss2 == 0)
	           if (ss3 == 0)
	               logicsel = a & b;
	           else
	               logicsel = a | b;
	       else
	           if (ss3 == 1)
	               logicsel = ~(a | b);
	           else
	               logicsel = a ^ b;
     end

	always @ ( aluop , a, b )
		if (aluop == 4'b1010)
		begin
			diff = a - b;
			slt = 0;
			if (diff[31] == 1)
				slt = 1;
		end

	always @ ( * )
	begin
		case (aluop)
			4'b0000 : alu_val = a + b;
			4'b0010 : alu_val = a - b;
			4'b1010 : alu_val = slt;
			default : alu_val = logicsel;
		endcase
	end

	assign result = alu_val;
	assign zero = (alu_val == 32'b0) ? 1: 0;

endmodule