data/full_repos/permissive/143278/ivltests/always3.1.3B2.v
 line:38: before: "assign"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.3B2.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #3 if(value1 != 4\'h1)\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.3B2.v:38: Unsupported: Ignoring delay on this delayed statement.\nalways #2 assign value1 = 1\'b1 && 1\'b1 ;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/always3.1.3B2.v:38: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s LOGAND generates 1 bits.\n                                                                             : ... In instance main\nalways #2 assign value1 = 1\'b1 && 1\'b1 ;\n          ^~~~~~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ;

reg [3:0] value1 ;

initial begin
    #3 if(value1 != 4'h1)
	$display("FAILED - 3.1.3B always assign reg_lvalue = boolean_expr");
    else
        $display("PASSED");
    $finish;
end

always #2 assign value1 = 1'b1 && 1'b1 ;

endmodule
module main ;


reg [3:0] value1 ;

initial begin
    #3 if(value1 != 4'h1)
	$display("FAILED - 3.1.3B always assign reg_lvalue = boolean_expr");
    else
        $display("PASSED");
    $finish;
end

always #2 assign value1 = 1'b1 && 1'b1 ;

endmodule