data/full_repos/permissive/117439233/hdl/src/CLA_4bit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/117439233/hdl/src/CLA_4bit.v:29: Operator OR expects 4 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                          : ... In instance CLA_4bit\n assign C[3:1] = G[3:1] | ( P[3:1] & C[3:0] );\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/117439233/hdl/src/CLA_4bit.v:29: Operator AND expects 4 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                          : ... In instance CLA_4bit\n assign C[3:1] = G[3:1] | ( P[3:1] & C[3:0] );\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/117439233/hdl/src/CLA_4bit.v:29: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s OR generates 4 bits.\n                                                                          : ... In instance CLA_4bit\n assign C[3:1] = G[3:1] | ( P[3:1] & C[3:0] );\n               ^\n%Warning-WIDTH: data/full_repos/permissive/117439233/hdl/src/CLA_4bit.v:31: Operator XOR expects 4 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                          : ... In instance CLA_4bit\n assign S[3:1] = P[3:1] ^ C[3:0];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/117439233/hdl/src/CLA_4bit.v:31: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s XOR generates 4 bits.\n                                                                          : ... In instance CLA_4bit\n assign S[3:1] = P[3:1] ^ C[3:0];\n               ^\n%Error: Exiting due to 5 warning(s)\n'
module CLA_4bit(
    input [3:0] A,
    input [3:0] B,
    input Cin,
    output [3:0]S,
    output PG,
    output GG,
    output Cout
    );
	wire [3:0] P;
	wire [3:0] G;
	wire [3:0] C;
	
	assign P[3:0] = A[3:0] ^ B[3:0];
	assign G[3:0] = A[3:0] & B[3:0];
	assign C[0] = G[0] | ( P[0] & Cin );
	assign C[3:1] = G[3:1] | ( P[3:1] & C[3:0] );
	assign S[0] = P[0] ^ Cin;
	assign S[3:1] = P[3:1] ^ C[3:0];
	assign Cout = C[3];
	
	assign PG = P[0] & P[1] & P[2] & P[3];
	assign GG = G[3] | ( G[2] & P[3] ) | ( G[1] & P[2] & P[3] ) | ( G[0] & P[1] & P[2] & P[3] );

endmodule
module CLA_4bit(
    input [3:0] A,
    input [3:0] B,
    input Cin,
    output [3:0]S,
    output PG,
    output GG,
    output Cout
    );

	wire [3:0] P;
	wire [3:0] G;
	wire [3:0] C;
	
	assign P[3:0] = A[3:0] ^ B[3:0];
	assign G[3:0] = A[3:0] & B[3:0];
	assign C[0] = G[0] | ( P[0] & Cin );
	assign C[3:1] = G[3:1] | ( P[3:1] & C[3:0] );
	assign S[0] = P[0] ^ Cin;
	assign S[3:1] = P[3:1] ^ C[3:0];
	assign Cout = C[3];
	
	assign PG = P[0] & P[1] & P[2] & P[3];
	assign GG = G[3] | ( G[2] & P[3] ) | ( G[1] & P[2] & P[3] ) | ( G[0] & P[1] & P[2] & P[3] );

endmodule