data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX V1.00/UART_TX/FINAL TOP MODULE.v
1: b'%Error: Cannot find file containing module: V1.00/UART_TX,data/full_repos/permissive/216654561\n        ... Looked in:\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n             V1.00/UART_TX,data/full_repos/permissive/216654561\n             V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX\n%Error: Cannot find file containing module: V1.00/UART_TX/FINAL\n%Error: Cannot find file containing module: TOP\n%Error: Cannot find file containing module: MODULE.v\n%Error: Exiting due to 5 error(s)\n'
module UART_Top_Module(

input clk,
input rst,
input [7:0] data_in,
input wr_en,rd_en,
input [2:0] address,

output  [7:0]data_o,
output  serial_data_out,
output  n_RTS,
output  tx_done,
input   n_CTS



);


wire b1;
wire [7:0]b2;
wire b3;
wire [7:0]ar0;
wire [7:0]ar1;
wire [7:0]ar3;
wire [7:0]ar4;

wire e1, e2;
wire [8:0]e3;
wire [1:0]e4;
wire [3:0]e5;
wire e6;

wire c1, c3;
wire [7:0]c2;

wire  d1;

assign tx_done = e6;

 UART_User_interface UI1 ( .clk(clk), .rst(rst),
  .wr_en(wr_en), .rd_en(rd_en), .data_in(data_in)
  , .addr(address), .fifo_full(b1),
  .data_fifo(b2), .fifo_wr_en(b3), .AXI_data_out(data_o),
  .reg_array0(ar0), .reg_array1(ar1), .reg_array3(ar3)
  , .reg_array4(ar4)
  );
  
  fifo F1( .clk(clk), .rst(rst),
  .we(b3), .data_in(b2), .re(c1),
  .full(b1), .data_o(c2), .empty(c3));


  
  c_div CD1( .rst(rst),
  .clk_cpu(clk), .tx(ar0), .rate(ar1), .control(ar3[7]),
  .baud_clock(d1));

  
  
  Process pr(
  .clk(clk), 
  .reset(rst),
  .data_in(c2), 
  .fifo_empty(c3), 
  .tx_ready(e1),
  .LCR0(ar3[0]), 
  .LCR1(ar3[1]),
  .LCR2(ar3[2]),
  .LCR3(ar3[3]),
  .LCR4(ar3[4]),
  .LCR5(ar3[5]),
  .fifo_read(c1), 
  .data_out_active(e2),
  .data_out(e3), 
  .num_stop_bit(e4),
  .data_length(e5));
  

  transmitter TX(  .reset(rst),
  .data_valid(e2), .data_in(e3), .num_stop_bit(e4), .data_length(e5), .MCR1(ar4[1]), .baud_clock(d1),
  .serial_data_out(serial_data_out), .n_RTS(n_RTS), .tx_done(e6),.tx_ready(e1),.n_CTS(n_CTS));
 endmodule
module UART_Top_Module(

input clk,
input rst,
input [7:0] data_in,
input wr_en,rd_en,
input [2:0] address,

output  [7:0]data_o,
output  serial_data_out,
output  n_RTS,
output  tx_done,
input   n_CTS



);



wire b1;
wire [7:0]b2;
wire b3;
wire [7:0]ar0;
wire [7:0]ar1;
wire [7:0]ar3;
wire [7:0]ar4;

wire e1, e2;
wire [8:0]e3;
wire [1:0]e4;
wire [3:0]e5;
wire e6;

wire c1, c3;
wire [7:0]c2;

wire  d1;

assign tx_done = e6;

 UART_User_interface UI1 ( .clk(clk), .rst(rst),
  .wr_en(wr_en), .rd_en(rd_en), .data_in(data_in)
  , .addr(address), .fifo_full(b1),
  .data_fifo(b2), .fifo_wr_en(b3), .AXI_data_out(data_o),
  .reg_array0(ar0), .reg_array1(ar1), .reg_array3(ar3)
  , .reg_array4(ar4)
  );
  
  fifo F1( .clk(clk), .rst(rst),
  .we(b3), .data_in(b2), .re(c1),
  .full(b1), .data_o(c2), .empty(c3));


  
  c_div CD1( .rst(rst),
  .clk_cpu(clk), .tx(ar0), .rate(ar1), .control(ar3[7]),
  .baud_clock(d1));

  
  
  Process pr(
  .clk(clk), 
  .reset(rst),
  .data_in(c2), 
  .fifo_empty(c3), 
  .tx_ready(e1),
  .LCR0(ar3[0]), 
  .LCR1(ar3[1]),
  .LCR2(ar3[2]),
  .LCR3(ar3[3]),
  .LCR4(ar3[4]),
  .LCR5(ar3[5]),
  .fifo_read(c1), 
  .data_out_active(e2),
  .data_out(e3), 
  .num_stop_bit(e4),
  .data_length(e5));
  

  transmitter TX(  .reset(rst),
  .data_valid(e2), .data_in(e3), .num_stop_bit(e4), .data_length(e5), .MCR1(ar4[1]), .baud_clock(d1),
  .serial_data_out(serial_data_out), .n_RTS(n_RTS), .tx_done(e6),.tx_ready(e1),.n_CTS(n_CTS));
 endmodule