data/full_repos/permissive/200314387/verilog/74245/hct74245.v
 line:56: before: "if"
1: b'%Warning-WIDTH: data/full_repos/permissive/200314387/verilog/74245/hct74245.v:33: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s CONST \'8\'bzzzzzzzz\' generates 8 bits.\n                                                                                : ... In instance hct74245\n    assign A= nOE_d ? 8\'bzzzzzzzz :dir_d==1?\'bzzzzzzzz:B_d;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/200314387/verilog/74245/hct74245.v:33: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'B_d\' generates 8 bits.\n                                                                                : ... In instance hct74245\n    assign A= nOE_d ? 8\'bzzzzzzzz :dir_d==1?\'bzzzzzzzz:B_d;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/200314387/verilog/74245/hct74245.v:33: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                : ... In instance hct74245\n    assign A= nOE_d ? 8\'bzzzzzzzz :dir_d==1?\'bzzzzzzzz:B_d;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/200314387/verilog/74245/hct74245.v:34: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s CONST \'8\'bzzzzzzzz\' generates 8 bits.\n                                                                                : ... In instance hct74245\n    assign B= nOE_d ? 8\'bzzzzzzzz :dir_d==0?\'bzzzzzzzz:A_d;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/200314387/verilog/74245/hct74245.v:34: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'A_d\' generates 8 bits.\n                                                                                : ... In instance hct74245\n    assign B= nOE_d ? 8\'bzzzzzzzz :dir_d==0?\'bzzzzzzzz:A_d;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/200314387/verilog/74245/hct74245.v:34: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                : ... In instance hct74245\n    assign B= nOE_d ? 8\'bzzzzzzzz :dir_d==0?\'bzzzzzzzz:A_d;\n            ^\n%Error: Exiting due to 6 warning(s)\n'
module hct74245( 
    input dir,
    input nOE,
    inout tri [7:0] A,
    inout tri [7:0] B
);
    parameter NAME="74245";
    parameter LOG=0;

    parameter PD_TRANS=10;
    parameter PD_DIR=16;
    parameter PD_OE=16;


    logic dir_d;
    logic nOE_d;
    
    logic [7:0] A_d;
    logic [7:0] B_d;

    assign A= nOE_d ? 8'bzzzzzzzz :dir_d==1?'bzzzzzzzz:B_d;
    assign B= nOE_d ? 8'bzzzzzzzz :dir_d==0?'bzzzzzzzz:A_d;
    
    always @* begin
        dir_d <= #(PD_DIR) dir;
        nOE_d <= #(PD_OE) nOE;
        A_d <= #(PD_TRANS) A;
        B_d <= #(PD_TRANS) B; 
    end













    
    if (LOG) 
        always @(*) 
        begin
            $display("%9t", $time,  " BUF %m (%s) : A=%8b ", NAME, A, "B=%8b ", B, "dir=%1b", dir, " nOE=%1b", nOE);
        end

endmodule
module hct74245( 
    input dir,
    input nOE,
    inout tri [7:0] A,
    inout tri [7:0] B
);

    parameter NAME="74245";
    parameter LOG=0;

    parameter PD_TRANS=10;
    parameter PD_DIR=16;
    parameter PD_OE=16;


    logic dir_d;
    logic nOE_d;
    
    logic [7:0] A_d;
    logic [7:0] B_d;

    assign A= nOE_d ? 8'bzzzzzzzz :dir_d==1?'bzzzzzzzz:B_d;
    assign B= nOE_d ? 8'bzzzzzzzz :dir_d==0?'bzzzzzzzz:A_d;
    
    always @* begin
        dir_d <= #(PD_DIR) dir;
        nOE_d <= #(PD_OE) nOE;
        A_d <= #(PD_TRANS) A;
        B_d <= #(PD_TRANS) B; 
    end













    
    if (LOG) 
        always @(*) 
        begin
            $display("%9t", $time,  " BUF %m (%s) : A=%8b ", NAME, A, "B=%8b ", B, "dir=%1b", dir, " nOE=%1b", nOE);
        end

endmodule