data/full_repos/permissive/143278/ivltests/pr1851310.v
 line:19: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1851310.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1851310.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI);\n  ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_monitor();

reg [7:0] Memory[0:15];

reg [3:0] Index;

wire Flag1;
wire FlagI;

assign Flag1 = (Memory[1] == 0);

assign FlagI = (Memory[Index] == 0);

initial begin
  Index = 1;
  Memory[Index] = 0;
  #1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI);
  Memory[Index] = 1;
  #1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI);
end

endmodule
module memory_monitor();


reg [7:0] Memory[0:15];

reg [3:0] Index;

wire Flag1;
wire FlagI;

assign Flag1 = (Memory[1] == 0);

assign FlagI = (Memory[Index] == 0);

initial begin
  Index = 1;
  Memory[Index] = 0;
  #1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI);
  Memory[Index] = 1;
  #1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI);
end

endmodule