data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v
None: at end of input
1: b'%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:56: Cannot find include file: wb_model_defines.v\n`include "wb_model_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog,data/full_repos/permissive/175070965/wb_model_defines.v\n             data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog,data/full_repos/permissive/175070965/wb_model_defines.v.v\n             data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog,data/full_repos/permissive/175070965/wb_model_defines.v.sv\n             wb_model_defines.v\n             wb_model_defines.v.v\n             wb_model_defines.v.sv\n             obj_dir/wb_model_defines.v\n             obj_dir/wb_model_defines.v.v\n             obj_dir/wb_model_defines.v.sv\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:57: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:79: Define or directive not defined: \'`WB_TAG_TYPE\'\n    input    `WB_TAG_TYPE    TAG_I;\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:80: Define or directive not defined: \'`WB_TAG_TYPE\'\n    output   `WB_TAG_TYPE    TAG_O;\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:82: Define or directive not defined: \'`WB_ADDR_TYPE\'\n    output   `WB_ADDR_TYPE   ADR_O;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:84: Define or directive not defined: \'`WB_DATA_TYPE\'\n    input    `WB_DATA_TYPE   DAT_I;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:85: Define or directive not defined: \'`WB_DATA_TYPE\'\n    output   `WB_DATA_TYPE   DAT_O;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:88: Define or directive not defined: \'`WB_SEL_TYPE\'\n    output   `WB_SEL_TYPE    SEL_O;\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:96: Define or directive not defined: \'`WB_ADDR_TYPE\'\n    reg    `WB_ADDR_TYPE   ADR_O;\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:97: Define or directive not defined: \'`WB_SEL_TYPE\'\n    reg    `WB_SEL_TYPE    SEL_O;\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:98: Define or directive not defined: \'`WB_TAG_TYPE\'\n    reg    `WB_TAG_TYPE    TAG_O;\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:101: Define or directive not defined: \'`WB_DATA_TYPE\'\n    reg    `WB_DATA_TYPE   DAT_O;\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:153: Define or directive not defined: \'`Tsetup\'\n        CYC_O <= #(Tp - `Tsetup) 1\'b1 ;\n                        ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:153: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        CYC_O <= #(Tp - `Tsetup) 1\'b1 ;\n                               ^\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:154: Define or directive not defined: \'`Tsetup\'\n        CAB_O <= #(Tp - `Tsetup) is_cab ;\n                        ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:154: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        CAB_O <= #(Tp - `Tsetup) is_cab ;\n                               ^\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:155: Define or directive not defined: \'`Tsetup\'\n        WE_O  <= #(Tp - `Tsetup) write ;\n                        ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:155: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        WE_O  <= #(Tp - `Tsetup) write ;\n                               ^\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:169: Define or directive not defined: \'`Thold\'\n        CYC_O <= #`Thold 1\'b0 ;\n                  ^~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:170: Define or directive not defined: \'`Thold\'\n        CAB_O <= #`Thold 1\'b0 ;\n                  ^~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:181: Define or directive not defined: \'`Tsetup\'\n        WE_O <= #(Tp - `Tsetup) we ;\n                       ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:181: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        WE_O <= #(Tp - `Tsetup) we ;\n                              ^\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:186: Define or directive not defined: \'`READ_STIM_TYPE\'\n        input  `READ_STIM_TYPE input_data ;\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:187: Define or directive not defined: \'`READ_RETURN_TYPE\'\n        inout `READ_RETURN_TYPE   output_data ;\n              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:188: Define or directive not defined: \'`WB_ADDR_TYPE\'\n        reg    `WB_ADDR_TYPE           address ;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:189: Define or directive not defined: \'`WB_DATA_TYPE\'\n        reg    `WB_DATA_TYPE           data ;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:190: Define or directive not defined: \'`WB_SEL_TYPE\'\n        reg    `WB_SEL_TYPE            sel ;\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:191: Define or directive not defined: \'`WB_TAG_TYPE\'\n        reg    `WB_TAG_TYPE            tag ;\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:194: Define or directive not defined: \'`TB_ERROR_BIT\'\n        output_data`TB_ERROR_BIT = 1\'b0 ;\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:200: Define or directive not defined: \'`TB_ERROR_BIT\'\n            output_data`TB_ERROR_BIT = 1\'b1 ;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:207: Define or directive not defined: \'`TB_ERROR_BIT\'\n            output_data`TB_ERROR_BIT = 1\'b1 ;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:214: Define or directive not defined: \'`TB_ERROR_BIT\'\n            output_data`TB_ERROR_BIT = 1\'b1 ;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:221: Define or directive not defined: \'`WAIT_FOR_RESPONSE\'\n        num_of_cyc = `WAIT_FOR_RESPONSE ;\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:221: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        num_of_cyc = `WAIT_FOR_RESPONSE ;\n                                        ^\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:224: Define or directive not defined: \'`Tsetup\'\n        ADR_O      <= #(Tp - `Tsetup) input_data`READ_ADDRESS ;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:224: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        ADR_O      <= #(Tp - `Tsetup) input_data`READ_ADDRESS ;\n                                    ^\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:224: Define or directive not defined: \'`READ_ADDRESS\'\n        ADR_O      <= #(Tp - `Tsetup) input_data`READ_ADDRESS ;\n                                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:225: Define or directive not defined: \'`Tsetup\'\n        SEL_O      <= #(Tp - `Tsetup) input_data`READ_SEL ;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:225: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        SEL_O      <= #(Tp - `Tsetup) input_data`READ_SEL ;\n                                    ^\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:225: Define or directive not defined: \'`READ_SEL\'\n        SEL_O      <= #(Tp - `Tsetup) input_data`READ_SEL ;\n                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:226: Define or directive not defined: \'`Tsetup\'\n        TAG_O      <= #(Tp - `Tsetup) input_data`READ_TAG_STIM ;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:226: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        TAG_O      <= #(Tp - `Tsetup) input_data`READ_TAG_STIM ;\n                                    ^\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:226: Define or directive not defined: \'`READ_TAG_STIM\'\n        TAG_O      <= #(Tp - `Tsetup) input_data`READ_TAG_STIM ;\n                                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:229: Define or directive not defined: \'`Tsetup\'\n        STB_O      <= #(Tp - `Tsetup) 1\'b1 ;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:229: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        STB_O      <= #(Tp - `Tsetup) 1\'b1 ;\n                                    ^\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:231: Define or directive not defined: \'`CYC_ACK\'\n        output_data`CYC_ACK = 0 ;\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:232: Define or directive not defined: \'`CYC_RTY\'\n        output_data`CYC_RTY = 0 ;\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:233: Define or directive not defined: \'`CYC_ERR\'\n        output_data`CYC_ERR = 0 ;\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:235: syntax error, unexpected \'@\'\n        @(posedge CLK_I) ;\n        ^\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/bench/verilog/wb_master32.v:236: Define or directive not defined: \'`CYC_ACK\'\n        output_data`CYC_ACK = ACK_I ;\n                   ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module WB_MASTER32
(
    CLK_I,
    RST_I,
    TAG_I,
    TAG_O,
    ACK_I,
    ADR_O,
    CYC_O,
    DAT_I,
    DAT_O,
    ERR_I,
    RTY_I,
    SEL_O,
    STB_O,
    WE_O,
    CAB_O
);

    input	             CLK_I;
    input                    RST_I;
    input    `WB_TAG_TYPE    TAG_I;
    output   `WB_TAG_TYPE    TAG_O;
    input                    ACK_I;
    output   `WB_ADDR_TYPE   ADR_O;
    output                   CYC_O;
    input    `WB_DATA_TYPE   DAT_I;
    output   `WB_DATA_TYPE   DAT_O;
    input                    ERR_I;
    input                    RTY_I;
    output   `WB_SEL_TYPE    SEL_O;
    output                   STB_O;
    output                   WE_O;
    output                   CAB_O ;


    real Tp ;

    reg    `WB_ADDR_TYPE   ADR_O;
    reg    `WB_SEL_TYPE    SEL_O;
    reg    `WB_TAG_TYPE    TAG_O;
    reg                    CYC_O;
    reg                    WE_O;
    reg    `WB_DATA_TYPE   DAT_O;
    reg                    CAB_O ;
    reg                    STB_O ;


    reg in_use ;


    reg cycle_in_progress ;


    reg cab ;

    reg we ;

    task start_cycle ;
        input is_cab ;
        input write  ;
        output ok ;
    begin:main

        ok  = 1 ;


        if ( (is_cab !== 1'b0) && (is_cab !== 1'b1) )
        begin
            $display("*E, invalid CAB value for cycle! Requested CAB_O value = %b, Time %t ", is_cab, $time) ;
            ok = 0 ;
            disable main ;
        end

        if ( (cycle_in_progress === 1) || (CYC_O === 1))
        begin

            $display("*W, cycle already in progress when start_cycle routine was called! Time %t ", $time) ;
            if ((CAB_O !== is_cab) || (WE_O !== write) )
            begin
                ok = 0 ;
                if ( is_cab === 1 )
                    $display("*E, cab cycle start attempted when non-cab cycle was in progress! Time %t", $time) ;
                else
                    $display("*E, non-cab cycle start attempted when cab cycle was in progress! Time %t", $time) ;

                if ( we === 1 )
                    $display("*E, write cycle start attempted when read cycle was in progress! Time %t", $time) ;
                else
                    $display("*E, read cycle start attempted when write cycle was in progress! Time %t", $time) ;

                disable main ;
            end
        end

        CYC_O <= #(Tp - `Tsetup) 1'b1 ;
        CAB_O <= #(Tp - `Tsetup) is_cab ;
        WE_O  <= #(Tp - `Tsetup) write ;


        cycle_in_progress = 1'b1 ;
        cab               = is_cab ;
        we                = write ;
    end
    endtask

    task end_cycle ;
    begin
        if ( CYC_O !== 1'b1 )
            $display("*W, end_cycle routine called when CYC_O value was %b! Time %t ", CYC_O, $time) ;

        CYC_O <= #`Thold 1'b0 ;
        CAB_O <= #`Thold 1'b0 ;
        cycle_in_progress = 1'b0 ;
    end
    endtask

    task modify_cycle ;
    begin
        if ( CYC_O !== 1'b1 )
            $display("*W, modify_cycle routine called when CYC_O value was %b! Time %t ", CYC_O, $time) ;

        we = ~we ;
        WE_O <= #(Tp - `Tsetup) we ;
    end
    endtask

    task wbm_read ;
        input  `READ_STIM_TYPE input_data ;
        inout `READ_RETURN_TYPE   output_data ;
        reg    `WB_ADDR_TYPE           address ;
        reg    `WB_DATA_TYPE           data ;
        reg    `WB_SEL_TYPE            sel ;
        reg    `WB_TAG_TYPE            tag ;
        integer                        num_of_cyc ;
    begin:main
        output_data`TB_ERROR_BIT = 1'b0 ;


        if ( in_use === 1 )
        begin
            $display("*E, wbm_read routine re-entered or called concurently with write routine! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end

        if ( cycle_in_progress !== 1 )
        begin
            $display("*E, wbm_read routine called without start_cycle routine being called first! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end

        if ( we !== 0 )
        begin
            $display("*E, wbm_read routine called after write cycle was started! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end


        in_use = 1 ;

        num_of_cyc = `WAIT_FOR_RESPONSE ;


        ADR_O      <= #(Tp - `Tsetup) input_data`READ_ADDRESS ;
        SEL_O      <= #(Tp - `Tsetup) input_data`READ_SEL ;
        TAG_O      <= #(Tp - `Tsetup) input_data`READ_TAG_STIM ;


        STB_O      <= #(Tp - `Tsetup) 1'b1 ;

        output_data`CYC_ACK = 0 ;
        output_data`CYC_RTY = 0 ;
        output_data`CYC_ERR = 0 ;

        @(posedge CLK_I) ;
        output_data`CYC_ACK = ACK_I ;
        output_data`CYC_RTY = RTY_I ;
        output_data`CYC_ERR = ERR_I ;

        while ( (num_of_cyc > 0) && (output_data`CYC_RESPONSE === 0) )
        begin
	    @(posedge CLK_I) ;
	    output_data`CYC_ACK = ACK_I ;
	    output_data`CYC_RTY = RTY_I ;
	    output_data`CYC_ERR = ERR_I ;
	    num_of_cyc = num_of_cyc - 1 ;
	end

	output_data`READ_DATA    = DAT_I ;
	output_data`READ_TAG_RET = TAG_I ;

        if ( output_data`CYC_RESPONSE === 0 )
	begin

            $display("*W, Terminating read cycle because no response was received in %d cycles! Time %t ", `WAIT_FOR_RESPONSE, $time) ;
        end

        if ( output_data`CYC_ACK === 1 && output_data`CYC_RTY === 0 && output_data`CYC_ERR === 0 )
            output_data`CYC_ACTUAL_TRANSFER = output_data`CYC_ACTUAL_TRANSFER + 1 ;

        STB_O <= #`Thold 1'b0 ;
        ADR_O <= #`Thold {`WB_ADDR_WIDTH{1'bx}} ;
        SEL_O <= #`Thold {`WB_SEL_WIDTH{1'bx}} ;
        TAG_O <= #`Thold {`WB_TAG_WIDTH{1'bx}} ;

        in_use = 0 ;
    end
    endtask

    task wbm_write ;
        input  `WRITE_STIM_TYPE input_data ;
        inout  `WRITE_RETURN_TYPE   output_data ;
        reg    `WB_ADDR_TYPE        address ;
        reg    `WB_DATA_TYPE        data ;
        reg    `WB_SEL_TYPE         sel ;
        reg    `WB_TAG_TYPE         tag ;
        integer                     num_of_cyc ;
    begin:main
        output_data`TB_ERROR_BIT = 1'b0 ;


        if ( in_use === 1 )
        begin
            $display("*E, wbm_write routine re-entered or called concurently with read routine! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end

        if ( cycle_in_progress !== 1 )
        begin
            $display("*E, wbm_write routine called without start_cycle routine being called first! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end

        if ( we !== 1 )
        begin
            $display("*E, wbm_write routine after read cycle was started! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end


        in_use = 1 ;

        num_of_cyc = `WAIT_FOR_RESPONSE ;

        ADR_O      <= #(Tp - `Tsetup) input_data`WRITE_ADDRESS ;
        DAT_O      <= #(Tp - `Tsetup) input_data`WRITE_DATA ;
        SEL_O      <= #(Tp - `Tsetup) input_data`WRITE_SEL ;
        TAG_O      <= #(Tp - `Tsetup) input_data`WRITE_TAG_STIM ;

        STB_O      <= #(Tp - `Tsetup) 1'b1 ;

        output_data`CYC_ACK = 0 ;
        output_data`CYC_RTY = 0 ;
        output_data`CYC_ERR = 0 ;

        @(posedge CLK_I) ;
        output_data`CYC_ACK = ACK_I ;
        output_data`CYC_RTY = RTY_I ;
        output_data`CYC_ERR = ERR_I ;

        while ( (num_of_cyc > 0) && (output_data`CYC_RESPONSE === 0) )
        begin
            @(posedge CLK_I) ;
            output_data`CYC_ACK = ACK_I ;
            output_data`CYC_RTY = RTY_I ;
            output_data`CYC_ERR = ERR_I ;
            num_of_cyc = num_of_cyc - 1 ;
        end

        output_data`WRITE_TAG_RET = TAG_I ;
        if ( output_data`CYC_RESPONSE === 0 )
        begin
            $display("*W, Terminating write cycle because no response was received in %d cycles! Time %t ", `WAIT_FOR_RESPONSE, $time) ;
        end

        if ( output_data`CYC_ACK === 1 && output_data`CYC_RTY === 0 && output_data`CYC_ERR === 0 )
            output_data`CYC_ACTUAL_TRANSFER = output_data`CYC_ACTUAL_TRANSFER + 1 ;

        ADR_O <= #`Thold {`WB_ADDR_WIDTH{1'bx}} ;
        DAT_O <= #`Thold {`WB_DATA_WIDTH{1'bx}} ;
        SEL_O <= #`Thold {`WB_SEL_WIDTH{1'bx}} ;
        TAG_O <= #`Thold {`WB_TAG_WIDTH{1'bx}} ;

        STB_O <= #`Thold 1'b0 ;

        in_use = 0 ;
    end
    endtask

    initial
    begin
        Tp = 1 / `WB_FREQ ;
        in_use = 0 ;
        cycle_in_progress = 0 ;
        cab = 0 ;
        ADR_O <= {`WB_ADDR_WIDTH{1'bx}} ;
        DAT_O <= {`WB_DATA_WIDTH{1'bx}} ;
        SEL_O <= {`WB_SEL_WIDTH{1'bx}} ;
        TAG_O <= {`WB_TAG_WIDTH{1'bx}} ;
        CYC_O <= 1'b0 ;
        STB_O <= 1'b0 ;
        CAB_O <= 1'b0 ;
        WE_O  <= 1'b0 ;
        if ( `Tsetup > Tp || `Thold >= Tp )
        begin
            $display("Either Tsetup or Thold values for WISHBONE BFMs are too large!") ;
            $stop ;
        end
    end

endmodule
module WB_MASTER32
(
    CLK_I,
    RST_I,
    TAG_I,
    TAG_O,
    ACK_I,
    ADR_O,
    CYC_O,
    DAT_I,
    DAT_O,
    ERR_I,
    RTY_I,
    SEL_O,
    STB_O,
    WE_O,
    CAB_O
);


    input	             CLK_I;
    input                    RST_I;
    input    `WB_TAG_TYPE    TAG_I;
    output   `WB_TAG_TYPE    TAG_O;
    input                    ACK_I;
    output   `WB_ADDR_TYPE   ADR_O;
    output                   CYC_O;
    input    `WB_DATA_TYPE   DAT_I;
    output   `WB_DATA_TYPE   DAT_O;
    input                    ERR_I;
    input                    RTY_I;
    output   `WB_SEL_TYPE    SEL_O;
    output                   STB_O;
    output                   WE_O;
    output                   CAB_O ;


    real Tp ;

    reg    `WB_ADDR_TYPE   ADR_O;
    reg    `WB_SEL_TYPE    SEL_O;
    reg    `WB_TAG_TYPE    TAG_O;
    reg                    CYC_O;
    reg                    WE_O;
    reg    `WB_DATA_TYPE   DAT_O;
    reg                    CAB_O ;
    reg                    STB_O ;


    reg in_use ;


    reg cycle_in_progress ;


    reg cab ;

    reg we ;

    task start_cycle ;
        input is_cab ;
        input write  ;
        output ok ;
    begin:main

        ok  = 1 ;


        if ( (is_cab !== 1'b0) && (is_cab !== 1'b1) )
        begin
            $display("*E, invalid CAB value for cycle! Requested CAB_O value = %b, Time %t ", is_cab, $time) ;
            ok = 0 ;
            disable main ;
        end

        if ( (cycle_in_progress === 1) || (CYC_O === 1))
        begin

            $display("*W, cycle already in progress when start_cycle routine was called! Time %t ", $time) ;
            if ((CAB_O !== is_cab) || (WE_O !== write) )
            begin
                ok = 0 ;
                if ( is_cab === 1 )
                    $display("*E, cab cycle start attempted when non-cab cycle was in progress! Time %t", $time) ;
                else
                    $display("*E, non-cab cycle start attempted when cab cycle was in progress! Time %t", $time) ;

                if ( we === 1 )
                    $display("*E, write cycle start attempted when read cycle was in progress! Time %t", $time) ;
                else
                    $display("*E, read cycle start attempted when write cycle was in progress! Time %t", $time) ;

                disable main ;
            end
        end

        CYC_O <= #(Tp - `Tsetup) 1'b1 ;
        CAB_O <= #(Tp - `Tsetup) is_cab ;
        WE_O  <= #(Tp - `Tsetup) write ;


        cycle_in_progress = 1'b1 ;
        cab               = is_cab ;
        we                = write ;
    end
    endtask

    task end_cycle ;
    begin
        if ( CYC_O !== 1'b1 )
            $display("*W, end_cycle routine called when CYC_O value was %b! Time %t ", CYC_O, $time) ;

        CYC_O <= #`Thold 1'b0 ;
        CAB_O <= #`Thold 1'b0 ;
        cycle_in_progress = 1'b0 ;
    end
    endtask

    task modify_cycle ;
    begin
        if ( CYC_O !== 1'b1 )
            $display("*W, modify_cycle routine called when CYC_O value was %b! Time %t ", CYC_O, $time) ;

        we = ~we ;
        WE_O <= #(Tp - `Tsetup) we ;
    end
    endtask

    task wbm_read ;
        input  `READ_STIM_TYPE input_data ;
        inout `READ_RETURN_TYPE   output_data ;
        reg    `WB_ADDR_TYPE           address ;
        reg    `WB_DATA_TYPE           data ;
        reg    `WB_SEL_TYPE            sel ;
        reg    `WB_TAG_TYPE            tag ;
        integer                        num_of_cyc ;
    begin:main
        output_data`TB_ERROR_BIT = 1'b0 ;


        if ( in_use === 1 )
        begin
            $display("*E, wbm_read routine re-entered or called concurently with write routine! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end

        if ( cycle_in_progress !== 1 )
        begin
            $display("*E, wbm_read routine called without start_cycle routine being called first! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end

        if ( we !== 0 )
        begin
            $display("*E, wbm_read routine called after write cycle was started! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end


        in_use = 1 ;

        num_of_cyc = `WAIT_FOR_RESPONSE ;


        ADR_O      <= #(Tp - `Tsetup) input_data`READ_ADDRESS ;
        SEL_O      <= #(Tp - `Tsetup) input_data`READ_SEL ;
        TAG_O      <= #(Tp - `Tsetup) input_data`READ_TAG_STIM ;


        STB_O      <= #(Tp - `Tsetup) 1'b1 ;

        output_data`CYC_ACK = 0 ;
        output_data`CYC_RTY = 0 ;
        output_data`CYC_ERR = 0 ;

        @(posedge CLK_I) ;
        output_data`CYC_ACK = ACK_I ;
        output_data`CYC_RTY = RTY_I ;
        output_data`CYC_ERR = ERR_I ;

        while ( (num_of_cyc > 0) && (output_data`CYC_RESPONSE === 0) )
        begin
	    @(posedge CLK_I) ;
	    output_data`CYC_ACK = ACK_I ;
	    output_data`CYC_RTY = RTY_I ;
	    output_data`CYC_ERR = ERR_I ;
	    num_of_cyc = num_of_cyc - 1 ;
	end

	output_data`READ_DATA    = DAT_I ;
	output_data`READ_TAG_RET = TAG_I ;

        if ( output_data`CYC_RESPONSE === 0 )
	begin

            $display("*W, Terminating read cycle because no response was received in %d cycles! Time %t ", `WAIT_FOR_RESPONSE, $time) ;
        end

        if ( output_data`CYC_ACK === 1 && output_data`CYC_RTY === 0 && output_data`CYC_ERR === 0 )
            output_data`CYC_ACTUAL_TRANSFER = output_data`CYC_ACTUAL_TRANSFER + 1 ;

        STB_O <= #`Thold 1'b0 ;
        ADR_O <= #`Thold {`WB_ADDR_WIDTH{1'bx}} ;
        SEL_O <= #`Thold {`WB_SEL_WIDTH{1'bx}} ;
        TAG_O <= #`Thold {`WB_TAG_WIDTH{1'bx}} ;

        in_use = 0 ;
    end
    endtask

    task wbm_write ;
        input  `WRITE_STIM_TYPE input_data ;
        inout  `WRITE_RETURN_TYPE   output_data ;
        reg    `WB_ADDR_TYPE        address ;
        reg    `WB_DATA_TYPE        data ;
        reg    `WB_SEL_TYPE         sel ;
        reg    `WB_TAG_TYPE         tag ;
        integer                     num_of_cyc ;
    begin:main
        output_data`TB_ERROR_BIT = 1'b0 ;


        if ( in_use === 1 )
        begin
            $display("*E, wbm_write routine re-entered or called concurently with read routine! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end

        if ( cycle_in_progress !== 1 )
        begin
            $display("*E, wbm_write routine called without start_cycle routine being called first! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end

        if ( we !== 1 )
        begin
            $display("*E, wbm_write routine after read cycle was started! Time %t ", $time) ;
            output_data`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end


        in_use = 1 ;

        num_of_cyc = `WAIT_FOR_RESPONSE ;

        ADR_O      <= #(Tp - `Tsetup) input_data`WRITE_ADDRESS ;
        DAT_O      <= #(Tp - `Tsetup) input_data`WRITE_DATA ;
        SEL_O      <= #(Tp - `Tsetup) input_data`WRITE_SEL ;
        TAG_O      <= #(Tp - `Tsetup) input_data`WRITE_TAG_STIM ;

        STB_O      <= #(Tp - `Tsetup) 1'b1 ;

        output_data`CYC_ACK = 0 ;
        output_data`CYC_RTY = 0 ;
        output_data`CYC_ERR = 0 ;

        @(posedge CLK_I) ;
        output_data`CYC_ACK = ACK_I ;
        output_data`CYC_RTY = RTY_I ;
        output_data`CYC_ERR = ERR_I ;

        while ( (num_of_cyc > 0) && (output_data`CYC_RESPONSE === 0) )
        begin
            @(posedge CLK_I) ;
            output_data`CYC_ACK = ACK_I ;
            output_data`CYC_RTY = RTY_I ;
            output_data`CYC_ERR = ERR_I ;
            num_of_cyc = num_of_cyc - 1 ;
        end

        output_data`WRITE_TAG_RET = TAG_I ;
        if ( output_data`CYC_RESPONSE === 0 )
        begin
            $display("*W, Terminating write cycle because no response was received in %d cycles! Time %t ", `WAIT_FOR_RESPONSE, $time) ;
        end

        if ( output_data`CYC_ACK === 1 && output_data`CYC_RTY === 0 && output_data`CYC_ERR === 0 )
            output_data`CYC_ACTUAL_TRANSFER = output_data`CYC_ACTUAL_TRANSFER + 1 ;

        ADR_O <= #`Thold {`WB_ADDR_WIDTH{1'bx}} ;
        DAT_O <= #`Thold {`WB_DATA_WIDTH{1'bx}} ;
        SEL_O <= #`Thold {`WB_SEL_WIDTH{1'bx}} ;
        TAG_O <= #`Thold {`WB_TAG_WIDTH{1'bx}} ;

        STB_O <= #`Thold 1'b0 ;

        in_use = 0 ;
    end
    endtask

    initial
    begin
        Tp = 1 / `WB_FREQ ;
        in_use = 0 ;
        cycle_in_progress = 0 ;
        cab = 0 ;
        ADR_O <= {`WB_ADDR_WIDTH{1'bx}} ;
        DAT_O <= {`WB_DATA_WIDTH{1'bx}} ;
        SEL_O <= {`WB_SEL_WIDTH{1'bx}} ;
        TAG_O <= {`WB_TAG_WIDTH{1'bx}} ;
        CYC_O <= 1'b0 ;
        STB_O <= 1'b0 ;
        CAB_O <= 1'b0 ;
        WE_O  <= 1'b0 ;
        if ( `Tsetup > Tp || `Thold >= Tp )
        begin
            $display("Either Tsetup or Thold values for WISHBONE BFMs are too large!") ;
            $stop ;
        end
    end

endmodule