data/full_repos/permissive/157436936/ex3/Uart_Top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/157436936/ex3/Uart_Top.v:155: Bit extraction of array[6:0] requires 3 bit index, not 4 bits.\n                                                                       : ... In instance Uart_Top\n           Data_Tx <= String[Light][Echo_Cnt];\n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/157436936/ex3/Uart_Top.v:179: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                       : ... In instance Uart_Top\n         State <= 2\'b0;\n               ^~\n%Error: data/full_repos/permissive/157436936/ex3/Uart_Top.v:330: Cannot find file containing module: \'Uart_ClkDiv\'\n Uart_ClkDiv uart_clkdiv(.Sys_CLK(Sys_CLK), .Sys_RST(Sys_RST), .Uart_CLK(Uart_CLK));\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157436936/ex3,data/full_repos/permissive/157436936/Uart_ClkDiv\n             data/full_repos/permissive/157436936/ex3,data/full_repos/permissive/157436936/Uart_ClkDiv.v\n             data/full_repos/permissive/157436936/ex3,data/full_repos/permissive/157436936/Uart_ClkDiv.sv\n             Uart_ClkDiv\n             Uart_ClkDiv.v\n             Uart_ClkDiv.sv\n             obj_dir/Uart_ClkDiv\n             obj_dir/Uart_ClkDiv.v\n             obj_dir/Uart_ClkDiv.sv\n%Error: data/full_repos/permissive/157436936/ex3/Uart_Top.v:331: Cannot find file containing module: \'Uart_Tx\'\n Uart_Tx uart_tx(.Uart_CLK(Uart_CLK), .Data_Tx(Data_Tx), .Wrsig(Wrsig), .Idle(Idle), .Signal_Tx(Signal_Tx));\n ^~~~~~~\n%Error: data/full_repos/permissive/157436936/ex3/Uart_Top.v:332: Cannot find file containing module: \'Uart_Rx\'\n Uart_Rx uart_rx(.Uart_CLK(Uart_CLK), .Uart_RST(Sys_RST), .Signal_Rx(Signal_Rx), .Data_Rx(Data_Rx), .Rdsig(Rdsig), .DataError_Flag(Rx_DataError_Flag), .FrameError_Flag(Rx_FrameError_Flag));\n ^~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module Uart_Top(Sys_CLK, Sys_RST, Signal_Tx, Signal_Rx, Light, Data, Length, Switch, Tx_Sig, Tx_Idle, Recv_index, Recv_data);
	input Sys_CLK;
	input Sys_RST;
	input Signal_Rx;
	output Signal_Tx;
	input [1:0] Light;
	input [7:0] Data;
	input [4:0] Length;
	input [1:0] Switch;
	input Tx_Sig;
	output reg Tx_Idle;
	output reg [4:0] Recv_index;
	output reg [7:0] Recv_data;
	

	wire Uart_CLK;
	reg [7:0] Data_Tx;
	wire [7:0] Data_Rx;
	reg Wrsig;
	wire Rdsig;
	wire Idle;
	wire Rx_DataError_Flag;
	wire Rx_FrameError_Flag;
	reg Error_Flag;
	reg [2:0] State;
	reg [7:0] cnt;

	reg [7:0] Print[0:8];
	reg [7:0] Recv_Reg;
	reg [3:0] Print_Cnt;
	reg [3:0] Recv_Cnt;
	reg [3:0] Echo_Cnt;
	reg [7:0] String[0:3][0:6];
	

	parameter Wait_Rdsig = 3'b000;
	parameter Check_Data = 3'b001;
	parameter Save_Data = 3'b010;
	parameter Trans_Data = 3'b011;
	parameter Echo_State = 3'b100;
	parameter State_Delay = 3'b101;
	
	always @(posedge Uart_CLK or negedge Sys_RST) begin
		if (!Sys_RST) begin
			Wrsig <= 1'b0;
			State <= 3'b0;
			cnt <= 8'b0;
			Tx_Idle <= 1'b1;
			Data_Tx <= 8'b0;
			Print_Cnt <= 4'b0;
			Recv_Reg <= 8'b0;
			Recv_Cnt <= 4'b0;
			Recv_index <= 5'b0;
			Recv_data <= 8'b0;
			Echo_Cnt <= 4'b0;
			String[0][0] <= 8'd79;
			String[0][1] <= 8'd102;
			String[0][2] <= 8'd102;
			String[0][3] <= 8'd32;
			String[0][4] <= 8'd32;
			String[0][5] <= 8'd32;
			String[0][6] <= 8'd13;
			String[1][0] <= 8'd87;
			String[1][1] <= 8'd104;
			String[1][2] <= 8'd105;
			String[1][3] <= 8'd116;
			String[1][4] <= 8'd101;
			String[1][5] <= 8'd32;
			String[1][6] <= 8'd13;
			String[2][0] <= 8'd83;
			String[2][1] <= 8'd117;
			String[2][2] <= 8'd110;
			String[2][3] <= 8'd32;
			String[2][4] <= 8'd32;
			String[2][5] <= 8'd32;
			String[2][6] <= 8'd13;
			String[3][0] <= 8'd89;
			String[3][1] <= 8'd101;
			String[3][2] <= 8'd108;
			String[3][3] <= 8'd108;
			String[3][4] <= 8'd111;
			String[3][5] <= 8'd119;
			String[3][6] <= 8'd13;
		end
		else begin
			if (!Switch[0])
				Recv_index <= 5'b0;
			case(State)
				Wait_Rdsig:	begin
									if (Tx_Sig) begin
										Tx_Idle <= 1'b0;
										if (Switch[1] == 1'b0)
											State <= Trans_Data;
										else
											State <= Echo_State;
									end
									else begin
										Tx_Idle <= 1'b1;
										if (Recv_Cnt == 4'd8) begin
											Recv_Cnt <= 4'd0;
											Recv_index <= Length + 1;
											Recv_data <= Recv_Reg;
										end
										if (!Rdsig)
											State <= Wait_Rdsig;
										else
											State <= Check_Data;
									end
								end
				Check_Data:	begin
									if (Rdsig)
										State <= Check_Data;
									else begin
										Error_Flag <= Rx_DataError_Flag || Rx_FrameError_Flag;
										State <= Save_Data;
									end
								end
				Save_Data:	begin
									if (!Error_Flag) begin
										case (Data_Rx)
											8'd48: Recv_Reg[7-Recv_Cnt] <= 1'b0;
											8'd49: Recv_Reg[7-Recv_Cnt] <= 1'b1;
										endcase
										Recv_Cnt <= Recv_Cnt + 1;
										State <= Wait_Rdsig;
									end
									else
										State <= Trans_Data;
								end
				Trans_Data:	begin
									if (Print_Cnt == 4'd9) begin
										Print_Cnt <= 4'd0;
										State <= State_Delay;
									end
									else begin
										if (cnt == 254) begin
											Data_Tx <= Print[Print_Cnt];
											Wrsig <= 1'b1;
											cnt <= 8'd0;
											Print_Cnt <= Print_Cnt + 1;
										end
										else begin
											Wrsig <= 1'b0;
											cnt <= cnt + 8'd1;
										end
									end
								end
				Echo_State:	begin
									if (Echo_Cnt == 4'd7) begin
										Echo_Cnt <= 4'd0;
										State <= State_Delay;
									end
									else begin
										if (cnt == 254) begin
											Data_Tx <= String[Light][Echo_Cnt];
											Wrsig <= 1'b1;
											cnt <= 8'd0;
											Echo_Cnt <= Echo_Cnt + 1;
										end
										else begin
											Wrsig <= 1'b0;
											cnt <= cnt + 8'd1;
										end
									end
								end
				State_Delay:begin
									if (cnt == 254) begin
										cnt <= 8'd0;
										State <= Wait_Rdsig;
									end
									else begin
										Wrsig <= 1'b0;
										cnt <= cnt + 8'd1;
									end
								end
				default:		begin
									Wrsig <= 1'b0;
									cnt <= 8'd0;
									State <= 2'b0;
								end
			endcase
		end
	end
	
	always @(Data) begin
		Print[1] <= 8'd46;
		Print[4] <= 8'd115;
		Print[5] <= 8'd58;
		if (Data[7]) begin
			Print[6] <= 8'd79;
			Print[7] <= 8'd110;
		end
		else begin
			Print[6] <= 8'd79;
			Print[7] <= 8'd102;
		end
		Print[8] <= 8'd13;
		case (Data[6:0])
			7'b0: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd48; end
			7'b1: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd49; end
			7'b10: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd50; end
			7'b11: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd51; end
			7'b100: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd52; end
			7'b101: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd53; end
			7'b110: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd54; end
			7'b111: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd55; end
			7'b1000: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd56; end
			7'b1001: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd57; end
			7'b1010: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd48; end
			7'b1011: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd49; end
			7'b1100: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd50; end
			7'b1101: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd51; end
			7'b1110: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd52; end
			7'b1111: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd53; end
			7'b10000: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd54; end
			7'b10001: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd55; end
			7'b10010: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd56; end
			7'b10011: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd57; end
			7'b10100: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd48; end
			7'b10101: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd49; end
			7'b10110: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd50; end
			7'b10111: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd51; end
			7'b11000: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd52; end
			7'b11001: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd53; end
			7'b11010: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd54; end
			7'b11011: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd55; end
			7'b11100: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd56; end
			7'b11101: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd57; end
			7'b11110: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd48; end
			7'b11111: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd49; end
			7'b100000: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd50; end
			7'b100001: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd51; end
			7'b100010: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd52; end
			7'b100011: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd53; end
			7'b100100: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd54; end
			7'b100101: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd55; end
			7'b100110: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd56; end
			7'b100111: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd57; end
			7'b101000: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd48; end
			7'b101001: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd49; end
			7'b101010: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd50; end
			7'b101011: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd51; end
			7'b101100: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd52; end
			7'b101101: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd53; end
			7'b101110: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd54; end
			7'b101111: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd55; end
			7'b110000: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd56; end
			7'b110001: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd57; end
			7'b110010: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd48; end
			7'b110011: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd49; end
			7'b110100: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd50; end
			7'b110101: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd51; end
			7'b110110: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd52; end
			7'b110111: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd53; end
			7'b111000: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd54; end
			7'b111001: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd55; end
			7'b111010: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd56; end
			7'b111011: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd57; end
			7'b111100: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd48; end
			7'b111101: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd49; end
			7'b111110: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd50; end
			7'b111111: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd51; end
			7'b1000000: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd52; end
			7'b1000001: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd53; end
			7'b1000010: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd54; end
			7'b1000011: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd55; end
			7'b1000100: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd56; end
			7'b1000101: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd57; end
			7'b1000110: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd48; end
			7'b1000111: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd49; end
			7'b1001000: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd50; end
			7'b1001001: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd51; end
			7'b1001010: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd52; end
			7'b1001011: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd53; end
			7'b1001100: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd54; end
			7'b1001101: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd55; end
			7'b1001110: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd56; end
			7'b1001111: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd57; end
			7'b1010000: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd48; end
			7'b1010001: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd49; end
			7'b1010010: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd50; end
			7'b1010011: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd51; end
			7'b1010100: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd52; end
			7'b1010101: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd53; end
			7'b1010110: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd54; end
			7'b1010111: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd55; end
			7'b1011000: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd56; end
			7'b1011001: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd57; end
			7'b1011010: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd48; end
			7'b1011011: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd49; end
			7'b1011100: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd50; end
			7'b1011101: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd51; end
			7'b1011110: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd52; end
			7'b1011111: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd53; end
			7'b1100000: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd54; end
			7'b1100001: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd55; end
			7'b1100010: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd56; end
			7'b1100011: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd57; end
			7'b1100100: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd48; end
			7'b1100101: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd49; end
			7'b1100110: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd50; end
			7'b1100111: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd51; end
			7'b1101000: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd52; end
			7'b1101001: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd53; end
			7'b1101010: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd54; end
			7'b1101011: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd55; end
			7'b1101100: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd56; end
			7'b1101101: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd57; end
			7'b1101110: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd48; end
			7'b1101111: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd49; end
			7'b1110000: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd50; end
			7'b1110001: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd51; end
			7'b1110010: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd52; end
			7'b1110011: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd53; end
			7'b1110100: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd54; end
			7'b1110101: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd55; end
			7'b1110110: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd56; end
			7'b1110111: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd57; end
			7'b1111000: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd48; end
			7'b1111001: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd49; end
			7'b1111010: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd50; end
			7'b1111011: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd51; end
			7'b1111100: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd52; end
			7'b1111101: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd53; end
			7'b1111110: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd54; end
			7'b1111111: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd55; end
		endcase
	end
	
	Uart_ClkDiv uart_clkdiv(.Sys_CLK(Sys_CLK), .Sys_RST(Sys_RST), .Uart_CLK(Uart_CLK));
	Uart_Tx uart_tx(.Uart_CLK(Uart_CLK), .Data_Tx(Data_Tx), .Wrsig(Wrsig), .Idle(Idle), .Signal_Tx(Signal_Tx));
	Uart_Rx uart_rx(.Uart_CLK(Uart_CLK), .Uart_RST(Sys_RST), .Signal_Rx(Signal_Rx), .Data_Rx(Data_Rx), .Rdsig(Rdsig), .DataError_Flag(Rx_DataError_Flag), .FrameError_Flag(Rx_FrameError_Flag));
	
endmodule
module Uart_Top(Sys_CLK, Sys_RST, Signal_Tx, Signal_Rx, Light, Data, Length, Switch, Tx_Sig, Tx_Idle, Recv_index, Recv_data);

	input Sys_CLK;
	input Sys_RST;
	input Signal_Rx;
	output Signal_Tx;
	input [1:0] Light;
	input [7:0] Data;
	input [4:0] Length;
	input [1:0] Switch;
	input Tx_Sig;
	output reg Tx_Idle;
	output reg [4:0] Recv_index;
	output reg [7:0] Recv_data;
	

	wire Uart_CLK;
	reg [7:0] Data_Tx;
	wire [7:0] Data_Rx;
	reg Wrsig;
	wire Rdsig;
	wire Idle;
	wire Rx_DataError_Flag;
	wire Rx_FrameError_Flag;
	reg Error_Flag;
	reg [2:0] State;
	reg [7:0] cnt;

	reg [7:0] Print[0:8];
	reg [7:0] Recv_Reg;
	reg [3:0] Print_Cnt;
	reg [3:0] Recv_Cnt;
	reg [3:0] Echo_Cnt;
	reg [7:0] String[0:3][0:6];
	

	parameter Wait_Rdsig = 3'b000;
	parameter Check_Data = 3'b001;
	parameter Save_Data = 3'b010;
	parameter Trans_Data = 3'b011;
	parameter Echo_State = 3'b100;
	parameter State_Delay = 3'b101;
	
	always @(posedge Uart_CLK or negedge Sys_RST) begin
		if (!Sys_RST) begin
			Wrsig <= 1'b0;
			State <= 3'b0;
			cnt <= 8'b0;
			Tx_Idle <= 1'b1;
			Data_Tx <= 8'b0;
			Print_Cnt <= 4'b0;
			Recv_Reg <= 8'b0;
			Recv_Cnt <= 4'b0;
			Recv_index <= 5'b0;
			Recv_data <= 8'b0;
			Echo_Cnt <= 4'b0;
			String[0][0] <= 8'd79;
			String[0][1] <= 8'd102;
			String[0][2] <= 8'd102;
			String[0][3] <= 8'd32;
			String[0][4] <= 8'd32;
			String[0][5] <= 8'd32;
			String[0][6] <= 8'd13;
			String[1][0] <= 8'd87;
			String[1][1] <= 8'd104;
			String[1][2] <= 8'd105;
			String[1][3] <= 8'd116;
			String[1][4] <= 8'd101;
			String[1][5] <= 8'd32;
			String[1][6] <= 8'd13;
			String[2][0] <= 8'd83;
			String[2][1] <= 8'd117;
			String[2][2] <= 8'd110;
			String[2][3] <= 8'd32;
			String[2][4] <= 8'd32;
			String[2][5] <= 8'd32;
			String[2][6] <= 8'd13;
			String[3][0] <= 8'd89;
			String[3][1] <= 8'd101;
			String[3][2] <= 8'd108;
			String[3][3] <= 8'd108;
			String[3][4] <= 8'd111;
			String[3][5] <= 8'd119;
			String[3][6] <= 8'd13;
		end
		else begin
			if (!Switch[0])
				Recv_index <= 5'b0;
			case(State)
				Wait_Rdsig:	begin
									if (Tx_Sig) begin
										Tx_Idle <= 1'b0;
										if (Switch[1] == 1'b0)
											State <= Trans_Data;
										else
											State <= Echo_State;
									end
									else begin
										Tx_Idle <= 1'b1;
										if (Recv_Cnt == 4'd8) begin
											Recv_Cnt <= 4'd0;
											Recv_index <= Length + 1;
											Recv_data <= Recv_Reg;
										end
										if (!Rdsig)
											State <= Wait_Rdsig;
										else
											State <= Check_Data;
									end
								end
				Check_Data:	begin
									if (Rdsig)
										State <= Check_Data;
									else begin
										Error_Flag <= Rx_DataError_Flag || Rx_FrameError_Flag;
										State <= Save_Data;
									end
								end
				Save_Data:	begin
									if (!Error_Flag) begin
										case (Data_Rx)
											8'd48: Recv_Reg[7-Recv_Cnt] <= 1'b0;
											8'd49: Recv_Reg[7-Recv_Cnt] <= 1'b1;
										endcase
										Recv_Cnt <= Recv_Cnt + 1;
										State <= Wait_Rdsig;
									end
									else
										State <= Trans_Data;
								end
				Trans_Data:	begin
									if (Print_Cnt == 4'd9) begin
										Print_Cnt <= 4'd0;
										State <= State_Delay;
									end
									else begin
										if (cnt == 254) begin
											Data_Tx <= Print[Print_Cnt];
											Wrsig <= 1'b1;
											cnt <= 8'd0;
											Print_Cnt <= Print_Cnt + 1;
										end
										else begin
											Wrsig <= 1'b0;
											cnt <= cnt + 8'd1;
										end
									end
								end
				Echo_State:	begin
									if (Echo_Cnt == 4'd7) begin
										Echo_Cnt <= 4'd0;
										State <= State_Delay;
									end
									else begin
										if (cnt == 254) begin
											Data_Tx <= String[Light][Echo_Cnt];
											Wrsig <= 1'b1;
											cnt <= 8'd0;
											Echo_Cnt <= Echo_Cnt + 1;
										end
										else begin
											Wrsig <= 1'b0;
											cnt <= cnt + 8'd1;
										end
									end
								end
				State_Delay:begin
									if (cnt == 254) begin
										cnt <= 8'd0;
										State <= Wait_Rdsig;
									end
									else begin
										Wrsig <= 1'b0;
										cnt <= cnt + 8'd1;
									end
								end
				default:		begin
									Wrsig <= 1'b0;
									cnt <= 8'd0;
									State <= 2'b0;
								end
			endcase
		end
	end
	
	always @(Data) begin
		Print[1] <= 8'd46;
		Print[4] <= 8'd115;
		Print[5] <= 8'd58;
		if (Data[7]) begin
			Print[6] <= 8'd79;
			Print[7] <= 8'd110;
		end
		else begin
			Print[6] <= 8'd79;
			Print[7] <= 8'd102;
		end
		Print[8] <= 8'd13;
		case (Data[6:0])
			7'b0: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd48; end
			7'b1: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd49; end
			7'b10: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd50; end
			7'b11: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd51; end
			7'b100: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd52; end
			7'b101: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd53; end
			7'b110: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd54; end
			7'b111: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd55; end
			7'b1000: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd56; end
			7'b1001: begin Print[0] <= 8'd48; Print[2] <= 8'd48; Print[3] <= 8'd57; end
			7'b1010: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd48; end
			7'b1011: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd49; end
			7'b1100: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd50; end
			7'b1101: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd51; end
			7'b1110: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd52; end
			7'b1111: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd53; end
			7'b10000: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd54; end
			7'b10001: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd55; end
			7'b10010: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd56; end
			7'b10011: begin Print[0] <= 8'd48; Print[2] <= 8'd49; Print[3] <= 8'd57; end
			7'b10100: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd48; end
			7'b10101: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd49; end
			7'b10110: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd50; end
			7'b10111: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd51; end
			7'b11000: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd52; end
			7'b11001: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd53; end
			7'b11010: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd54; end
			7'b11011: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd55; end
			7'b11100: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd56; end
			7'b11101: begin Print[0] <= 8'd48; Print[2] <= 8'd50; Print[3] <= 8'd57; end
			7'b11110: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd48; end
			7'b11111: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd49; end
			7'b100000: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd50; end
			7'b100001: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd51; end
			7'b100010: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd52; end
			7'b100011: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd53; end
			7'b100100: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd54; end
			7'b100101: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd55; end
			7'b100110: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd56; end
			7'b100111: begin Print[0] <= 8'd48; Print[2] <= 8'd51; Print[3] <= 8'd57; end
			7'b101000: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd48; end
			7'b101001: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd49; end
			7'b101010: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd50; end
			7'b101011: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd51; end
			7'b101100: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd52; end
			7'b101101: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd53; end
			7'b101110: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd54; end
			7'b101111: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd55; end
			7'b110000: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd56; end
			7'b110001: begin Print[0] <= 8'd48; Print[2] <= 8'd52; Print[3] <= 8'd57; end
			7'b110010: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd48; end
			7'b110011: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd49; end
			7'b110100: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd50; end
			7'b110101: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd51; end
			7'b110110: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd52; end
			7'b110111: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd53; end
			7'b111000: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd54; end
			7'b111001: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd55; end
			7'b111010: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd56; end
			7'b111011: begin Print[0] <= 8'd48; Print[2] <= 8'd53; Print[3] <= 8'd57; end
			7'b111100: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd48; end
			7'b111101: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd49; end
			7'b111110: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd50; end
			7'b111111: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd51; end
			7'b1000000: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd52; end
			7'b1000001: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd53; end
			7'b1000010: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd54; end
			7'b1000011: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd55; end
			7'b1000100: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd56; end
			7'b1000101: begin Print[0] <= 8'd48; Print[2] <= 8'd54; Print[3] <= 8'd57; end
			7'b1000110: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd48; end
			7'b1000111: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd49; end
			7'b1001000: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd50; end
			7'b1001001: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd51; end
			7'b1001010: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd52; end
			7'b1001011: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd53; end
			7'b1001100: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd54; end
			7'b1001101: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd55; end
			7'b1001110: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd56; end
			7'b1001111: begin Print[0] <= 8'd48; Print[2] <= 8'd55; Print[3] <= 8'd57; end
			7'b1010000: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd48; end
			7'b1010001: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd49; end
			7'b1010010: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd50; end
			7'b1010011: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd51; end
			7'b1010100: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd52; end
			7'b1010101: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd53; end
			7'b1010110: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd54; end
			7'b1010111: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd55; end
			7'b1011000: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd56; end
			7'b1011001: begin Print[0] <= 8'd48; Print[2] <= 8'd56; Print[3] <= 8'd57; end
			7'b1011010: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd48; end
			7'b1011011: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd49; end
			7'b1011100: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd50; end
			7'b1011101: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd51; end
			7'b1011110: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd52; end
			7'b1011111: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd53; end
			7'b1100000: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd54; end
			7'b1100001: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd55; end
			7'b1100010: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd56; end
			7'b1100011: begin Print[0] <= 8'd48; Print[2] <= 8'd57; Print[3] <= 8'd57; end
			7'b1100100: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd48; end
			7'b1100101: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd49; end
			7'b1100110: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd50; end
			7'b1100111: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd51; end
			7'b1101000: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd52; end
			7'b1101001: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd53; end
			7'b1101010: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd54; end
			7'b1101011: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd55; end
			7'b1101100: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd56; end
			7'b1101101: begin Print[0] <= 8'd49; Print[2] <= 8'd48; Print[3] <= 8'd57; end
			7'b1101110: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd48; end
			7'b1101111: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd49; end
			7'b1110000: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd50; end
			7'b1110001: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd51; end
			7'b1110010: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd52; end
			7'b1110011: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd53; end
			7'b1110100: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd54; end
			7'b1110101: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd55; end
			7'b1110110: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd56; end
			7'b1110111: begin Print[0] <= 8'd49; Print[2] <= 8'd49; Print[3] <= 8'd57; end
			7'b1111000: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd48; end
			7'b1111001: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd49; end
			7'b1111010: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd50; end
			7'b1111011: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd51; end
			7'b1111100: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd52; end
			7'b1111101: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd53; end
			7'b1111110: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd54; end
			7'b1111111: begin Print[0] <= 8'd49; Print[2] <= 8'd50; Print[3] <= 8'd55; end
		endcase
	end
	
	Uart_ClkDiv uart_clkdiv(.Sys_CLK(Sys_CLK), .Sys_RST(Sys_RST), .Uart_CLK(Uart_CLK));
	Uart_Tx uart_tx(.Uart_CLK(Uart_CLK), .Data_Tx(Data_Tx), .Wrsig(Wrsig), .Idle(Idle), .Signal_Tx(Signal_Tx));
	Uart_Rx uart_rx(.Uart_CLK(Uart_CLK), .Uart_RST(Sys_RST), .Signal_Rx(Signal_Rx), .Data_Rx(Data_Rx), .Rdsig(Rdsig), .DataError_Flag(Rx_DataError_Flag), .FrameError_Flag(Rx_FrameError_Flag));
	
endmodule