data/full_repos/permissive/186443491/model/game_info.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/186443491/model/game_info.v:72: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'timer\'\nmodule timer(\n       ^~~~~\n                                                                            : ... Top module \'rate_divider\'\nmodule rate_divider(resetn, clock, Enable);\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/186443491/model/game_info.v:69: Operator EQ expects 26 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance timer.r0\n assign Enable = (RateDivider == 1\'b0)?1:0;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/186443491/model/game_info.v:40: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'time_remaining\' generates 7 bits.\n                                                                         : ... In instance timer\n   time_remain <= time_remaining;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/186443491/model/game_info.v:86: Operator EQ expects 25 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance rate_divider\n assign Enable = (RateDivider == 1\'b0)?1:0;\n                              ^~\n%Error: Exiting due to 4 warning(s)\n'
module rate_divider(resetn, clock, Enable);
	input clock;
	input resetn;
	output Enable;
	parameter D = 25'd3333333;
	reg [24:0]RateDivider;
	always@(negedge resetn ,posedge clock)begin
		if(resetn == 0)
			RateDivider <= D;
		else if(RateDivider == 0)
			RateDivider <= D;
		else
			RateDivider <= RateDivider - 1'b1;
	end
	assign Enable = (RateDivider == 1'b0)?1:0;
endmodule
module rate_divider(resetn, clock, Enable);

	input clock;
	input resetn;
	output Enable;
	parameter D = 25'd3333333;
	reg [24:0]RateDivider;
	always@(negedge resetn ,posedge clock)begin
		if(resetn == 0)
			RateDivider <= D;
		else if(RateDivider == 0)
			RateDivider <= D;
		else
			RateDivider <= RateDivider - 1'b1;
	end
	assign Enable = (RateDivider == 1'b0)?1:0;
endmodule