data/full_repos/permissive/11571685/verilog/square_wave.v
data/verilator_xmls/0c22a973-1878-4bfb-ad72-96dfbfb9d243.xml
module square_wave(
    input clk,
    output reg sqwv_out
    );
	integer counter;
	initial counter=0;
	initial sqwv_out=0;

	always @(posedge clk) begin
		if(counter==399) begin
			sqwv_out<=~sqwv_out;
			counter <= 0;
		end else begin
			counter<=counter+1;
		end
	end

endmodule
module square_wave(
    input clk,
    output reg sqwv_out
    );

	integer counter;
	initial counter=0;
	initial sqwv_out=0;

	always @(posedge clk) begin
		if(counter==399) begin
			sqwv_out<=~sqwv_out;
			counter <= 0;
		end else begin
			counter<=counter+1;
		end
	end

endmodule