data/full_repos/permissive/146246005/Register- D Flip-Flop- SR Latch/reg_test.v
 line:40: before: "$"
1: b'%Error: Cannot find file containing module: D\n        ... Looked in:\n             data/full_repos/permissive/146246005/Register-/D\n             data/full_repos/permissive/146246005/Register-/D.v\n             data/full_repos/permissive/146246005/Register-/D.sv\n             D\n             D.v\n             D.sv\n             obj_dir/D\n             obj_dir/D.v\n             obj_dir/D.sv\n%Error: Cannot find file containing module: Flip-Flop-\n%Error: Cannot find file containing module: SR\n%Error: Cannot find file containing module: Latch,data/full_repos/permissive/146246005\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/Register-\n%Error: Cannot find file containing module: Latch/reg_test.v\n%Error: Exiting due to 6 error(s)\n'
module reg_test();
    reg CLK, ENA, RST;
    reg [7:0]DATA;
    wire [7:0]R;

    register UUT(R, CLK, DATA, ENA, RST);

    always #(`period*0.5) CLK=~CLK;

    initial begin
     $vcdpluson;
     $monitor("%d ns  DATA=%h  ENA=%b  RST=%b  R=%h",$time,DATA,ENA,RST,R);
     CLK=0;
    end

    initial begin
	ENA=0; RST=1; DATA=8'hAA;

	#(`period*2) ENA=1;
	#(`period*2) ENA=0;
	#`period DATA=8'h55;
	#(`period*2) RST=0;
     
     #`period $finish;

    end
endmodule
module reg_test();

    reg CLK, ENA, RST;
    reg [7:0]DATA;
    wire [7:0]R;

    register UUT(R, CLK, DATA, ENA, RST);

    always #(`period*0.5) CLK=~CLK;

    initial begin
     $vcdpluson;
     $monitor("%d ns  DATA=%h  ENA=%b  RST=%b  R=%h",$time,DATA,ENA,RST,R);
     CLK=0;
    end

    initial begin
	ENA=0; RST=1; DATA=8'hAA;

	#(`period*2) ENA=1;
	#(`period*2) ENA=0;
	#`period DATA=8'h55;
	#(`period*2) RST=0;
     
     #`period $finish;

    end
endmodule