data/full_repos/permissive/141038711/tb/apb_edgeirq_test.v
 line:51: before: "#"
1: b'%Error: data/full_repos/permissive/141038711/tb/apb_edgeirq_test.v:50: syntax error, unexpected \'@\'\n      @(posedge pclk)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_edgeirq_test.v:53: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD*5) ; \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_edgeirq_test.v:64: Unsupported: Ignoring delay on this delayed statement.\n            #1 $stop;\n            ^\n%Error: data/full_repos/permissive/141038711/tb/apb_edgeirq_test.v:67: syntax error, unexpected \'@\'\n         @(posedge pclk)  irq_posedge = 1<<i;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_edgeirq_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n            #1 $stop;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_edgeirq_test.v:86: Unsupported: Ignoring delay on this delayed statement.\n            #1 $stop;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_edgeirq_test.v:98: Unsupported: Ignoring delay on this delayed statement.\n            #1 $stop;\n            ^\n%Error: data/full_repos/permissive/141038711/tb/apb_edgeirq_test.v:111: syntax error, unexpected \'@\'\n         @(posedge pclk)  irq_posedge = i;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_edgeirq_test.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #500 $stop;       \n  ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n'
module apb_edgeirq_test;

`define ENBL_REG 16'h0
`define STAT_REG 16'h4

localparam CLK_PERIOD=100;




reg          reset_n;
reg          enable;


wire         pclk;
wire [ 15:0] paddr;
wire         pwrite;
wire         psel;
wire         penable;
wire [ 31:0] pwdata;
wire [ 31:0] prdata;
wire         pready;
wire         pslverr;

wire         irq;


reg  [ 3:0] irq_posedge;


integer i;

   initial
   begin


      reset_n    = 1'b0;
      enable     = 1'b1;


      irq_posedge   = 4'h0;
      
      @(posedge pclk)
         #(CLK_PERIOD*5) ; 
      reset_n = 1'b1;
      #(CLK_PERIOD*5) ; 
      

      for (i=0; i<4; i=i+1)
      begin

         apb_bus0.read(`STAT_REG,32'h00);
         apb_bus0.delay(1); 
         if (irq!==0)
         begin
            $display("%m@%0t: IRQ high (A) error",$time);
            #1 $stop;
         end            

         @(posedge pclk)  irq_posedge = 1<<i;
         @(posedge pclk)  irq_posedge = 0;

         @(posedge pclk); 

         apb_bus0.read(`STAT_REG,1<<i);

         if (irq!==1'b0)
         begin
            $display("%m@%0t: IRQ high (B) error",$time);
            #1 $stop;
         end            

         apb_bus0.write(`ENBL_REG,1<<i);
         apb_bus0.delay(2);

         if (irq!==1'b1)
         begin
            $display("%m@%0t: IRQ low (A) error",$time);
            #1 $stop;
         end            

         apb_bus0.read(`STAT_REG,32'h11<<i);
         apb_bus0.delay(2);

         apb_bus0.write(`STAT_REG,1<<i);
         apb_bus0.delay(2);

         if (irq!==1'b0)
         begin
            $display("%m@%0t: IRQ high (C) error",$time);
            #1 $stop;
         end            

         apb_bus0.read(`STAT_REG,32'h00);

         apb_bus0.write(`ENBL_REG,0);
      end
      

      apb_bus0.write(`ENBL_REG,32'hF);
      for (i=0; i<16; i=i+1)
      begin

         @(posedge pclk)  irq_posedge = i;
         @(posedge pclk)  irq_posedge = 0;

          @(posedge pclk); 
         apb_bus0.read(`STAT_REG,{24'h0,i[3:0],i[3:0]});
         apb_bus0.write(`STAT_REG,i);
         apb_bus0.delay(2);  
      end
         
      apb_bus0.delay(3);
      if (apb_bus0.errors==0)
         $display("apb_edgeirq test passed");
      else
         $display("apb_edgeirq test FAILED!");
		#500 $stop;       
   end


apb_edgeirq
apb_edgeirq_0 (

      .reset_n  (reset_n),
      .enable   (enable),


      .pclk     (pclk),
      .paddr    (paddr[2:0]),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr),
      
      .irq      (irq),


      .irq_posedge (irq_posedge)
   );
   
apb_bus 
#(.CLKPER(CLK_PERIOD)
 )
apb_bus0 (

      .pclk     (pclk),
      .paddr    (paddr),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr)
      ); 
   


endmodule
module apb_edgeirq_test;


`define ENBL_REG 16'h0
`define STAT_REG 16'h4

localparam CLK_PERIOD=100;




reg          reset_n;
reg          enable;


wire         pclk;
wire [ 15:0] paddr;
wire         pwrite;
wire         psel;
wire         penable;
wire [ 31:0] pwdata;
wire [ 31:0] prdata;
wire         pready;
wire         pslverr;

wire         irq;


reg  [ 3:0] irq_posedge;


integer i;

   initial
   begin


      reset_n    = 1'b0;
      enable     = 1'b1;


      irq_posedge   = 4'h0;
      
      @(posedge pclk)
         #(CLK_PERIOD*5) ; 
      reset_n = 1'b1;
      #(CLK_PERIOD*5) ; 
      

      for (i=0; i<4; i=i+1)
      begin

         apb_bus0.read(`STAT_REG,32'h00);
         apb_bus0.delay(1); 
         if (irq!==0)
         begin
            $display("%m@%0t: IRQ high (A) error",$time);
            #1 $stop;
         end            

         @(posedge pclk)  irq_posedge = 1<<i;
         @(posedge pclk)  irq_posedge = 0;

         @(posedge pclk); 

         apb_bus0.read(`STAT_REG,1<<i);

         if (irq!==1'b0)
         begin
            $display("%m@%0t: IRQ high (B) error",$time);
            #1 $stop;
         end            

         apb_bus0.write(`ENBL_REG,1<<i);
         apb_bus0.delay(2);

         if (irq!==1'b1)
         begin
            $display("%m@%0t: IRQ low (A) error",$time);
            #1 $stop;
         end            

         apb_bus0.read(`STAT_REG,32'h11<<i);
         apb_bus0.delay(2);

         apb_bus0.write(`STAT_REG,1<<i);
         apb_bus0.delay(2);

         if (irq!==1'b0)
         begin
            $display("%m@%0t: IRQ high (C) error",$time);
            #1 $stop;
         end            

         apb_bus0.read(`STAT_REG,32'h00);

         apb_bus0.write(`ENBL_REG,0);
      end
      

      apb_bus0.write(`ENBL_REG,32'hF);
      for (i=0; i<16; i=i+1)
      begin

         @(posedge pclk)  irq_posedge = i;
         @(posedge pclk)  irq_posedge = 0;

          @(posedge pclk); 
         apb_bus0.read(`STAT_REG,{24'h0,i[3:0],i[3:0]});
         apb_bus0.write(`STAT_REG,i);
         apb_bus0.delay(2);  
      end
         
      apb_bus0.delay(3);
      if (apb_bus0.errors==0)
         $display("apb_edgeirq test passed");
      else
         $display("apb_edgeirq test FAILED!");
		#500 $stop;       
   end


apb_edgeirq
apb_edgeirq_0 (

      .reset_n  (reset_n),
      .enable   (enable),


      .pclk     (pclk),
      .paddr    (paddr[2:0]),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr),
      
      .irq      (irq),


      .irq_posedge (irq_posedge)
   );
   
apb_bus 
#(.CLKPER(CLK_PERIOD)
 )
apb_bus0 (

      .pclk     (pclk),
      .paddr    (paddr),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr)
      ); 
   


endmodule