data/full_repos/permissive/100975158/MIPS32_Full/Processor/PC_Latch.v
data/verilator_xmls/349bdb90-bc3d-4f7f-a488-a544768b0f5f.xml
module PC_Latch (
    input clock,
    input reset,
    input enable,
    input [31:0] data,
    output reg [31:0] value
);

    initial begin
        value = 32'd0;
    end


    always @ (posedge clock) begin
        value <= (reset) ? 32'd0 : ((enable) ? data : value);
    end

endmodule
module PC_Latch (
    input clock,
    input reset,
    input enable,
    input [31:0] data,
    output reg [31:0] value
);


    initial begin
        value = 32'd0;
    end


    always @ (posedge clock) begin
        value <= (reset) ? 32'd0 : ((enable) ? data : value);
    end

endmodule