data/full_repos/permissive/143278/ivltests/clkgen_net.v
 line:11 column:15: Illegal character "'"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/clkgen_net.v:15: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/clkgen_net.v:23: Unsupported: fork statements\n    fork\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/clkgen_net.v:33: Unsupported: Ignoring delay on this delayed statement.\n     forever #10 iclk = ~iclk;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/clkgen_net.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clkgen(output clk);

logic iclk = 'x;
assign clk = iclk;

initial begin
   #100;
   disable checking;
   disable gen;
   $display ("PASSED");
   $finish;
end

initial begin
    fork
      checking;
	  gen;
    join
end


task gen;
  begin
     iclk = 0;
     forever #10 iclk = ~iclk;
  end
endtask

task checking;
   forever begin
      #1;
      if (clk === 1'bx ) begin
         $display ("FAILED!");
	     $finish;
      end
   end
endtask
endmodule
module clkgen(output clk);


logic iclk = 'x;
assign clk = iclk;

initial begin
   #100;
   disable checking;
   disable gen;
   $display ("PASSED");
   $finish;
end

initial begin
    fork
      checking;
	  gen;
    join
end


task gen;
  begin
     iclk = 0;
     forever #10 iclk = ~iclk;
  end
endtask

task checking;
   forever begin
      #1;
      if (clk === 1'bx ) begin
         $display ("FAILED!");
	     $finish;
      end
   end
endtask
endmodule