data/full_repos/permissive/101468463/mix_test.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/101468463/mix_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101468463/mix_test.v:44: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("output.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/101468463/mix_test.v:45: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/101468463/mix_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #10 $display("%x %x %x %x\\n", v_out[0*64+:64], v_out[4*64+:64], v_out[8*64+:64], v_out[12*64+:64]);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/101468463/mix_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mix_test();




reg clk=0;
reg [64*16-1:0] v;
reg [3:0]
  a = 4'd0,
  b = 4'd4,
  c = 4'd8,
  d = 4'd12;
reg [63:0]
  x = 64'h6f6c6c6568,
  y = 64'h0;

wire [64*16-1:0] v_out;

mix _mix(
  .clk(clk),
  .v(v),
  .a(a),
  .b(b),
  .c(c),
  .d(d),
  .x(x),
  .y(y),
  .v_out(v_out)
);

always
  begin
    #1 clk = ~clk;
  end

initial
  begin
    v[0*64+:64] = 64'h6a09e667f2bdc91c;
    v[4*64+:64] = 64'h510e527fade682d1;
    v[8*64+:64] = 64'h6a09e667f3bcc908;
    v[12*64+:64] = 64'h510e527fade682d4;

    $display("starting!");
    $dumpfile("output.vcd");
    $dumpvars;
    #10 $display("%x %x %x %x\n", v_out[0*64+:64], v_out[4*64+:64], v_out[8*64+:64], v_out[12*64+:64]);
    #10 $finish;
  end

endmodule
module mix_test();





reg clk=0;
reg [64*16-1:0] v;
reg [3:0]
  a = 4'd0,
  b = 4'd4,
  c = 4'd8,
  d = 4'd12;
reg [63:0]
  x = 64'h6f6c6c6568,
  y = 64'h0;

wire [64*16-1:0] v_out;

mix _mix(
  .clk(clk),
  .v(v),
  .a(a),
  .b(b),
  .c(c),
  .d(d),
  .x(x),
  .y(y),
  .v_out(v_out)
);

always
  begin
    #1 clk = ~clk;
  end

initial
  begin
    v[0*64+:64] = 64'h6a09e667f2bdc91c;
    v[4*64+:64] = 64'h510e527fade682d1;
    v[8*64+:64] = 64'h6a09e667f3bcc908;
    v[12*64+:64] = 64'h510e527fade682d4;

    $display("starting!");
    $dumpfile("output.vcd");
    $dumpvars;
    #10 $display("%x %x %x %x\n", v_out[0*64+:64], v_out[4*64+:64], v_out[8*64+:64], v_out[12*64+:64]);
    #10 $finish;
  end

endmodule