data/full_repos/permissive/160024456/exp/data_exporter.v
1: b"%Error: data/full_repos/permissive/160024456/exp/data_exporter.v:19: Cannot find file containing module: 'data_exporter'\ndata_exporter data_exporter1 (.clk(clk), .en(ready), .data({8'b0, overlaps}), .leds(leds));\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160024456/exp,data/full_repos/permissive/160024456/data_exporter\n             data/full_repos/permissive/160024456/exp,data/full_repos/permissive/160024456/data_exporter.v\n             data/full_repos/permissive/160024456/exp,data/full_repos/permissive/160024456/data_exporter.sv\n             data_exporter\n             data_exporter.v\n             data_exporter.sv\n             obj_dir/data_exporter\n             obj_dir/data_exporter.v\n             obj_dir/data_exporter.sv\n%Error: Exiting due to 1 error(s)\n"
module part1c (
  input wire clk,
  output reg LED5,
  output wire PMOD1,
  output wire PMOD2,
  output wire PMOD3,
  output wire PMOD4,
  output wire PMOD7,
  output wire PMOD8,
  output wire PMOD9,
  output wire PMOD10
);

reg ready = 0;

reg [19:0] overlaps;

wire [7:0] leds;
data_exporter data_exporter1 (.clk(clk), .en(ready), .data({8'b0, overlaps}), .leds(leds));

assign leds = {PMOD1, PMOD2, PMOD3, PMOD4, PMOD7, PMOD8, PMOD9, PMOD10};

always @(posedge clk) begin
  if (ready == 1) begin
    LED5 <= 1;
  end
  else begin
    ready <= 1;
    LED5 <= 0;
    overlaps <= 20'b0110_1001_0110_1001_0110;
  end
end

endmodule
module part1c (
  input wire clk,
  output reg LED5,
  output wire PMOD1,
  output wire PMOD2,
  output wire PMOD3,
  output wire PMOD4,
  output wire PMOD7,
  output wire PMOD8,
  output wire PMOD9,
  output wire PMOD10
);


reg ready = 0;

reg [19:0] overlaps;

wire [7:0] leds;
data_exporter data_exporter1 (.clk(clk), .en(ready), .data({8'b0, overlaps}), .leds(leds));

assign leds = {PMOD1, PMOD2, PMOD3, PMOD4, PMOD7, PMOD8, PMOD9, PMOD10};

always @(posedge clk) begin
  if (ready == 1) begin
    LED5 <= 1;
  end
  else begin
    ready <= 1;
    LED5 <= 0;
    overlaps <= 20'b0110_1001_0110_1001_0110;
  end
end

endmodule