data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/defines.vh\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/defines.vh.v\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:59: syntax error, unexpected \'(\', expecting \',\' or \';\'\n     .fn(fn),\n     ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:71: Define or directive not defined: \'`ALUFN_AND\'\n        in_vec[0] = { `ALUFN_AND, 8\'h00, 8\'h00 };\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:71: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        in_vec[0] = { `ALUFN_AND, 8\'h00, 8\'h00 };\n                                ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:75: Define or directive not defined: \'`ALUFN_AND\'\n        in_vec[1] = { `ALUFN_AND, 8\'hf0, 8\'ha5 };\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:75: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        in_vec[1] = { `ALUFN_AND, 8\'hf0, 8\'ha5 };\n                                ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:79: Define or directive not defined: \'`ALUFN_OR\'\n        in_vec[2] = { `ALUFN_OR, 8\'h00, 8\'h00 };\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:79: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        in_vec[2] = { `ALUFN_OR, 8\'h00, 8\'h00 };\n                               ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:83: Define or directive not defined: \'`ALUFN_OR\'\n        in_vec[3] = { `ALUFN_OR, 8\'h5a, 8\'ha5 };\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:83: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        in_vec[3] = { `ALUFN_OR, 8\'h5a, 8\'ha5 };\n                               ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:87: Define or directive not defined: \'`ALUFN_OR\'\n        in_vec[4] = { `ALUFN_OR, 8\'h07, 8\'h15 };\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:87: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        in_vec[4] = { `ALUFN_OR, 8\'h07, 8\'h15 };\n                               ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:91: Define or directive not defined: \'`ALUFN_XOR\'\n        in_vec[5] = { `ALUFN_XOR, 8\'h00, 8\'h00 };\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:91: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        in_vec[5] = { `ALUFN_XOR, 8\'h00, 8\'h00 };\n                                ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:95: Define or directive not defined: \'`ALUFN_XOR\'\n        in_vec[6] = { `ALUFN_XOR, 8\'h00, 8\'hff };\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:95: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        in_vec[6] = { `ALUFN_XOR, 8\'h00, 8\'hff };\n                                ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:99: Define or directive not defined: \'`ALUFN_XOR\'\n        in_vec[7] = { `ALUFN_XOR, 8\'hff, 8\'hff };\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:99: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        in_vec[7] = { `ALUFN_XOR, 8\'hff, 8\'hff };\n                                ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:103: Define or directive not defined: \'`ALUFN_PASSB\'\n        in_vec[8] = { `ALUFN_PASSB, 8\'ha5, 8\'h00 };\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:103: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        in_vec[8] = { `ALUFN_PASSB, 8\'ha5, 8\'h00 };\n                                  ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:107: Define or directive not defined: \'`ALUFN_PASSB\'\n        in_vec[9] = { `ALUFN_PASSB, 8\'h7e, 8\'ha5 };\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:107: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        in_vec[9] = { `ALUFN_PASSB, 8\'h7e, 8\'ha5 };\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n       #10;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n           #1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/logic_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n        #9;\n        ^\n%Error: Exiting due to 22 error(s), 3 warning(s)\n'
module logic_tb;

    parameter TESTS = 10;

    integer        errors;
    integer        test;




	reg     [17:0] in_vec [TESTS-1:0];


	reg     [11:0] out_vec [TESTS-1:0];

    

    reg     [1:0]  fn;
    reg     [7:0]  a;
    reg     [7:0]  b;


    wire    [7:0]  sum;
    wire    [3:0]  flags;

    reg            ok;


	logic uut (
	    .fn(fn),
		.a(a),
		.b(b),
		.sum(sum),
		.s(flags[3]),
		.v(flags[2]),
		.n(flags[1]),
		.z(flags[0])
	);

    initial begin

        in_vec[0] = { `ALUFN_AND, 8'h00, 8'h00 };
        out_vec[0] = { 4'b0001, 8'h00 };
        

        in_vec[1] = { `ALUFN_AND, 8'hf0, 8'ha5 };
        out_vec[1] = { 4'b1010, 8'ha0 };
        

        in_vec[2] = { `ALUFN_OR, 8'h00, 8'h00 };
        out_vec[2] = { 4'b0001, 8'h00 };
        

        in_vec[3] = { `ALUFN_OR, 8'h5a, 8'ha5 };
        out_vec[3] = { 4'b1010, 8'hff };
        

        in_vec[4] = { `ALUFN_OR, 8'h07, 8'h15 };
        out_vec[4] = { 4'b0000, 8'h17 };
        

        in_vec[5] = { `ALUFN_XOR, 8'h00, 8'h00 };
        out_vec[5] = { 4'b0001, 8'h00 };
        

        in_vec[6] = { `ALUFN_XOR, 8'h00, 8'hff };
        out_vec[6] = { 4'b1010, 8'hff };
        

        in_vec[7] = { `ALUFN_XOR, 8'hff, 8'hff };
        out_vec[7] = { 4'b0001, 8'h00 };
        

        in_vec[8] = { `ALUFN_PASSB, 8'ha5, 8'h00 };
        out_vec[8] = { 4'b0001, 8'h00 };
        

        in_vec[9] = { `ALUFN_PASSB, 8'h7e, 8'ha5 };
        out_vec[9] = { 4'b1010, 8'ha5 };
    end

	initial begin
	   errors = 0;
	   $display($time, " << Starting simulation >>");
       #10;

       for (test = 0; test < TESTS; test = test + 1) begin
           fn = in_vec[test][17:16];
           a = in_vec[test][15:8];
           b = in_vec[test][7:0];

           #1;
	       if ((out_vec[test][11:8] == flags) && (out_vec[test][7:0] == sum))
               ok = 1'b1;
           else
               ok = 1'bx;
 
	       #9;
	       if (ok == 1'b1) begin
               $display($time, " Test %d ok", test);
           end
           else begin
               errors = errors + 1;
               $display($time, " *** ERROR - Test %d failed *** - cout (e)%b (a)%b, sum (e)%b (a)%b", test, out_vec[test][11:8], flags, out_vec[test][7:0], sum);
           end    
       end
       
       if (errors == 0) begin
           $display($time, " All good, beer o'clock?");
       end
    end

endmodule
module logic_tb;


    parameter TESTS = 10;

    integer        errors;
    integer        test;




	reg     [17:0] in_vec [TESTS-1:0];


	reg     [11:0] out_vec [TESTS-1:0];

    

    reg     [1:0]  fn;
    reg     [7:0]  a;
    reg     [7:0]  b;


    wire    [7:0]  sum;
    wire    [3:0]  flags;

    reg            ok;


	logic uut (
	    .fn(fn),
		.a(a),
		.b(b),
		.sum(sum),
		.s(flags[3]),
		.v(flags[2]),
		.n(flags[1]),
		.z(flags[0])
	);

    initial begin

        in_vec[0] = { `ALUFN_AND, 8'h00, 8'h00 };
        out_vec[0] = { 4'b0001, 8'h00 };
        

        in_vec[1] = { `ALUFN_AND, 8'hf0, 8'ha5 };
        out_vec[1] = { 4'b1010, 8'ha0 };
        

        in_vec[2] = { `ALUFN_OR, 8'h00, 8'h00 };
        out_vec[2] = { 4'b0001, 8'h00 };
        

        in_vec[3] = { `ALUFN_OR, 8'h5a, 8'ha5 };
        out_vec[3] = { 4'b1010, 8'hff };
        

        in_vec[4] = { `ALUFN_OR, 8'h07, 8'h15 };
        out_vec[4] = { 4'b0000, 8'h17 };
        

        in_vec[5] = { `ALUFN_XOR, 8'h00, 8'h00 };
        out_vec[5] = { 4'b0001, 8'h00 };
        

        in_vec[6] = { `ALUFN_XOR, 8'h00, 8'hff };
        out_vec[6] = { 4'b1010, 8'hff };
        

        in_vec[7] = { `ALUFN_XOR, 8'hff, 8'hff };
        out_vec[7] = { 4'b0001, 8'h00 };
        

        in_vec[8] = { `ALUFN_PASSB, 8'ha5, 8'h00 };
        out_vec[8] = { 4'b0001, 8'h00 };
        

        in_vec[9] = { `ALUFN_PASSB, 8'h7e, 8'ha5 };
        out_vec[9] = { 4'b1010, 8'ha5 };
    end

	initial begin
	   errors = 0;
	   $display($time, " << Starting simulation >>");
       #10;

       for (test = 0; test < TESTS; test = test + 1) begin
           fn = in_vec[test][17:16];
           a = in_vec[test][15:8];
           b = in_vec[test][7:0];

           #1;
	       if ((out_vec[test][11:8] == flags) && (out_vec[test][7:0] == sum))
               ok = 1'b1;
           else
               ok = 1'bx;
 
	       #9;
	       if (ok == 1'b1) begin
               $display($time, " Test %d ok", test);
           end
           else begin
               errors = errors + 1;
               $display($time, " *** ERROR - Test %d failed *** - cout (e)%b (a)%b, sum (e)%b (a)%b", test, out_vec[test][11:8], flags, out_vec[test][7:0], sum);
           end    
       end
       
       if (errors == 0) begin
           $display($time, " All good, beer o'clock?");
       end
    end

endmodule