data/full_repos/permissive/187199324/stannel/Io_tb.v
 line:214: before: "begin"
1: b'%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:2: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:3: Cannot find include file: registers.vh\n`include "registers.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:4: Cannot find include file: status.vh\n`include "status.vh" \n         ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk <= ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:21: Define or directive not defined: \'`RAM_READ\'\n  wire                readWriteModeReal = `RAM_READ;\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:21: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  wire                readWriteModeReal = `RAM_READ;\n                                                   ^\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:80: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("Io_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:81: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, Io_tb);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:86: Define or directive not defined: \'`RAM_READ\'\n      readWriteAction = `RAM_READ;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      readWriteAction = `RAM_READ;\n                                 ^\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:88: Define or directive not defined: \'`REG_S1\'\n      destinationRegister = `REG_S1;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      destinationRegister = `REG_S1;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n      #4 reset = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n      #4 if (nextTopOfStack1 != ram0.ram[stackPointer + 0])\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:93: Define or directive not defined: \'`RAM_READ\'\n      if (readWriteMode != `RAM_READ)\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:93: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (readWriteMode != `RAM_READ)\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #4 begin\n    ^\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:112: Define or directive not defined: \'`RAM_READ\'\n      readWriteAction = `RAM_READ;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:112: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      readWriteAction = `RAM_READ;\n                                 ^\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:114: Define or directive not defined: \'`REG_S2\'\n      destinationRegister = `REG_S2;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:114: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      destinationRegister = `REG_S2;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n      #4 reset = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n      #4 if (nextTopOfStack2 != ram0.ram[stackPointer + 1])\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:119: Define or directive not defined: \'`RAM_READ\'\n      if (readWriteMode != `RAM_READ)\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:119: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (readWriteMode != `RAM_READ)\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n    #4 begin\n    ^\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:129: Define or directive not defined: \'`RAM_READ\'\n      readWriteAction = `RAM_READ;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:129: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      readWriteAction = `RAM_READ;\n                                 ^\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:131: Define or directive not defined: \'`REG_S3\'\n      destinationRegister = `REG_S3;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:131: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      destinationRegister = `REG_S3;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n      #4 reset = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n      #4 if (nextTopOfStack3 != ram0.ram[stackPointer + 2])\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:136: Define or directive not defined: \'`RAM_READ\'\n      if (readWriteMode != `RAM_READ)\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:136: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (readWriteMode != `RAM_READ)\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n    #4 begin\n    ^\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:144: Define or directive not defined: \'`RAM_WRITE\'\n      readWriteAction = `RAM_WRITE;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:144: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      readWriteAction = `RAM_WRITE;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n      #4 reset = 1;\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:149: Define or directive not defined: \'`RAM_WRITE\'\n      #4 if (readWriteMode != `RAM_WRITE)\n                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Io_tb.v:149: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      #4 if (readWriteMode != `RAM_WRITE)\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n      #4 if (readWriteMode != `RAM_WRITE)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n    #4 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Io_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n    #4 $finish;\n    ^\n%Error: Exiting due to 30 error(s), 14 warning(s)\n'
module Io_tb();
  localparam addrBits = 8;
  localparam dataBits = 16;

  reg clk = 1;
  always #1 clk <= ~clk;




  wire [addrBits-1:0] address;
  wire [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataInReal;
  wire [dataBits-1:0] dataOut;
  wire                readWriteMode;
  wire                readWriteModeReal = `RAM_READ;

  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile("execute_tb_data.hex")) ram0(
    .clk(clk),
    .address(address),
    .readWriteMode(readWriteModeReal),
    .dataIn(dataInReal),
    .dataOut(dataOut)
  );


  reg reset = 0;


  reg                readWriteAction;
  reg [addrBits-1:0] readOrWriteAddress;
  reg [dataBits-1:0] writeValue;
  reg [2:0]          destinationRegister;

  reg  [8:0]          programCounter   = 0;
  reg  [addrBits-1:0] stackPointer     = 13;
  reg  [addrBits-1:0] callStackPointer = 8;
  reg  [dataBits-1:0] topOfStack1;
  reg  [dataBits-1:0] topOfStack2;
  reg  [dataBits-1:0] topOfStack3;

  wire [8:0]          nextProgramCounter;
  wire [addrBits-1:0] nextStackPointer;
  wire [addrBits-1:0] nextCallStackPointer;
  wire [dataBits-1:0] nextTopOfStack1;
  wire [dataBits-1:0] nextTopOfStack2;
  wire [dataBits-1:0] nextTopOfStack3;

  Io #(.addrBits(addrBits), .dataBits(dataBits)) io0(
    .clk(clk),
    .reset(reset),
    .dataOut(dataOut),
    .addr(address),
    .dataIn(dataIn),
    .ramRW(readWriteMode),
    .readWriteAction(readWriteAction),
    .readOrWriteAddress(readOrWriteAddress),
    .writeValue(writeValue),
    .destinationRegister(destinationRegister),
    .programCounter(programCounter),
    .stackPointer(stackPointer),
    .callStackPointer(callStackPointer),
    .topOfStack1(topOfStack1),
    .topOfStack2(topOfStack2),
    .topOfStack3(topOfStack3),
    .nextProgramCounter(nextProgramCounter),
    .nextStackPointer(nextStackPointer),
    .nextCallStackPointer(nextCallStackPointer),
    .nextTopOfStack1(nextTopOfStack1),
    .nextTopOfStack2(nextTopOfStack2),
    .nextTopOfStack3(nextTopOfStack3)
  );

  initial begin
    $dumpfile("Io_tb.vcd");
    $dumpvars(0, Io_tb);

    #4 begin
      reset = 0;

      readWriteAction = `RAM_READ;
      readOrWriteAddress = stackPointer;
      destinationRegister = `REG_S1;
      #4 reset = 1;

      #4 if (nextTopOfStack1 != ram0.ram[stackPointer + 0])
        $error("readSp1: top of stack not updated as expected");
      if (readWriteMode != `RAM_READ)
        $error("readSp1: didn't perform read");
      if (address != stackPointer + 0)
        $error("readSp1: didn't perform read at expected address");

      if (nextProgramCounter != programCounter)
        $error("readSp1: PC changed");
      if (nextStackPointer != stackPointer)
        $error("readSp1: SP changed");
      if (nextCallStackPointer != callStackPointer)
        $error("readSp1: CSP changed");
      if (nextTopOfStack2 != topOfStack2)
        $error("readSp1: stack top 2 changed");
      if (nextTopOfStack3 != topOfStack3)
        $error("readSp1: stack top 3 changed");
    end

    #4 begin
      reset = 0;
      readWriteAction = `RAM_READ;
      readOrWriteAddress = stackPointer + 1;
      destinationRegister = `REG_S2;
      #4 reset = 1;

      #4 if (nextTopOfStack2 != ram0.ram[stackPointer + 1])
        $error("readSp2: top of stack 2 not updated as expected.");
      if (readWriteMode != `RAM_READ)
        $error("readSp2: didn't perform read");
      if (address != stackPointer + 1)
        $error("readSp2: read not from expected address");


    end

    #4 begin
      reset = 0;
      readWriteAction = `RAM_READ;
      readOrWriteAddress = stackPointer + 2;
      destinationRegister = `REG_S3;
      #4 reset = 1;

      #4 if (nextTopOfStack3 != ram0.ram[stackPointer + 2])
        $error("readSp3: top of stack 3 not updated as expected.");
      if (readWriteMode != `RAM_READ)
        $error("readSp3: didn't perform read");
      if (address != stackPointer + 2)
        $error("readSp3: read not from expected address");
    end

    #4 begin
      reset = 0;
      readWriteAction = `RAM_WRITE;
      readOrWriteAddress = stackPointer + 2;
      writeValue = topOfStack3;
      #4 reset = 1;

      #4 if (readWriteMode != `RAM_WRITE)
        $error("writeSp3: not writing as expected");
      if (dataIn != topOfStack3)
        $error("writeSp3: not writing top of stack 3 as expected.");
      if (address != stackPointer + 2)
        $error("writeSp3: not writing to stack pointer + 2 as expected.");
    end

    #4 $finish;
  end

endmodule
module Io_tb();

  localparam addrBits = 8;
  localparam dataBits = 16;

  reg clk = 1;
  always #1 clk <= ~clk;




  wire [addrBits-1:0] address;
  wire [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataInReal;
  wire [dataBits-1:0] dataOut;
  wire                readWriteMode;
  wire                readWriteModeReal = `RAM_READ;

  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile("execute_tb_data.hex")) ram0(
    .clk(clk),
    .address(address),
    .readWriteMode(readWriteModeReal),
    .dataIn(dataInReal),
    .dataOut(dataOut)
  );


  reg reset = 0;


  reg                readWriteAction;
  reg [addrBits-1:0] readOrWriteAddress;
  reg [dataBits-1:0] writeValue;
  reg [2:0]          destinationRegister;

  reg  [8:0]          programCounter   = 0;
  reg  [addrBits-1:0] stackPointer     = 13;
  reg  [addrBits-1:0] callStackPointer = 8;
  reg  [dataBits-1:0] topOfStack1;
  reg  [dataBits-1:0] topOfStack2;
  reg  [dataBits-1:0] topOfStack3;

  wire [8:0]          nextProgramCounter;
  wire [addrBits-1:0] nextStackPointer;
  wire [addrBits-1:0] nextCallStackPointer;
  wire [dataBits-1:0] nextTopOfStack1;
  wire [dataBits-1:0] nextTopOfStack2;
  wire [dataBits-1:0] nextTopOfStack3;

  Io #(.addrBits(addrBits), .dataBits(dataBits)) io0(
    .clk(clk),
    .reset(reset),
    .dataOut(dataOut),
    .addr(address),
    .dataIn(dataIn),
    .ramRW(readWriteMode),
    .readWriteAction(readWriteAction),
    .readOrWriteAddress(readOrWriteAddress),
    .writeValue(writeValue),
    .destinationRegister(destinationRegister),
    .programCounter(programCounter),
    .stackPointer(stackPointer),
    .callStackPointer(callStackPointer),
    .topOfStack1(topOfStack1),
    .topOfStack2(topOfStack2),
    .topOfStack3(topOfStack3),
    .nextProgramCounter(nextProgramCounter),
    .nextStackPointer(nextStackPointer),
    .nextCallStackPointer(nextCallStackPointer),
    .nextTopOfStack1(nextTopOfStack1),
    .nextTopOfStack2(nextTopOfStack2),
    .nextTopOfStack3(nextTopOfStack3)
  );

  initial begin
    $dumpfile("Io_tb.vcd");
    $dumpvars(0, Io_tb);

    #4 begin
      reset = 0;

      readWriteAction = `RAM_READ;
      readOrWriteAddress = stackPointer;
      destinationRegister = `REG_S1;
      #4 reset = 1;

      #4 if (nextTopOfStack1 != ram0.ram[stackPointer + 0])
        $error("readSp1: top of stack not updated as expected");
      if (readWriteMode != `RAM_READ)
        $error("readSp1: didn't perform read");
      if (address != stackPointer + 0)
        $error("readSp1: didn't perform read at expected address");

      if (nextProgramCounter != programCounter)
        $error("readSp1: PC changed");
      if (nextStackPointer != stackPointer)
        $error("readSp1: SP changed");
      if (nextCallStackPointer != callStackPointer)
        $error("readSp1: CSP changed");
      if (nextTopOfStack2 != topOfStack2)
        $error("readSp1: stack top 2 changed");
      if (nextTopOfStack3 != topOfStack3)
        $error("readSp1: stack top 3 changed");
    end

    #4 begin
      reset = 0;
      readWriteAction = `RAM_READ;
      readOrWriteAddress = stackPointer + 1;
      destinationRegister = `REG_S2;
      #4 reset = 1;

      #4 if (nextTopOfStack2 != ram0.ram[stackPointer + 1])
        $error("readSp2: top of stack 2 not updated as expected.");
      if (readWriteMode != `RAM_READ)
        $error("readSp2: didn't perform read");
      if (address != stackPointer + 1)
        $error("readSp2: read not from expected address");


    end

    #4 begin
      reset = 0;
      readWriteAction = `RAM_READ;
      readOrWriteAddress = stackPointer + 2;
      destinationRegister = `REG_S3;
      #4 reset = 1;

      #4 if (nextTopOfStack3 != ram0.ram[stackPointer + 2])
        $error("readSp3: top of stack 3 not updated as expected.");
      if (readWriteMode != `RAM_READ)
        $error("readSp3: didn't perform read");
      if (address != stackPointer + 2)
        $error("readSp3: read not from expected address");
    end

    #4 begin
      reset = 0;
      readWriteAction = `RAM_WRITE;
      readOrWriteAddress = stackPointer + 2;
      writeValue = topOfStack3;
      #4 reset = 1;

      #4 if (readWriteMode != `RAM_WRITE)
        $error("writeSp3: not writing as expected");
      if (dataIn != topOfStack3)
        $error("writeSp3: not writing top of stack 3 as expected.");
      if (address != stackPointer + 2)
        $error("writeSp3: not writing to stack pointer + 2 as expected.");
    end

    #4 $finish;
  end

endmodule