data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v
 line:70: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst= 1\'b1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #20 opcode = 5\'b01100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #20 opcode = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #500000000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:74: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clk=~clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:75: Unsupported: Ignoring delay on this delayed statement.\nalways #5 tick=~tick;\n       ^\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:79: Cannot find file containing module: \'interfaz\'\ninterfaz\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/BIP/Simulacion,data/full_repos/permissive/205673649/interfaz\n             data/full_repos/permissive/205673649/BIP/Simulacion,data/full_repos/permissive/205673649/interfaz.v\n             data/full_repos/permissive/205673649/BIP/Simulacion,data/full_repos/permissive/205673649/interfaz.sv\n             interfaz\n             interfaz.v\n             interfaz.sv\n             obj_dir/interfaz\n             obj_dir/interfaz.v\n             obj_dir/interfaz.sv\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:101: Cannot find file containing module: \'tx\'\ntx #(.NB_DATA(DATA), .SB_TICK(TICK))\n^~\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_interfaz.v:113: Cannot find file containing module: \'rx\'\nrx #(.NB_DATA(DATA), .SB_TICK(TICK))\n^~\n%Error: Exiting due to 3 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_interfaz();

localparam DATA = 8;
localparam ADDR =11;
localparam OPCODE =5;
localparam RAM =16;
localparam TICK= 16;

reg clk;
reg rst;
reg [OPCODE-1:0] opcode;
reg [RAM-1:0] acc;
reg [ADDR-1:0] pc;
wire bip_enable;
reg tick;
wire i_int_tx;
wire [DATA-1:0] i_interfaz_tx_data;
reg i_rx;
wire o_tx_interfaz_done_data;
wire o_tx;
wire o_rx_interfaz_done_data;
wire [DATA-1:0] o_rx_interfaz_data;

initial
begin
    clk = 1'b0;
    tick = 1'b0;
    rst = 1'b0;
    opcode= 5'b1;
    i_rx= 1'b1;
    #10 rst= 1'b1;
    #160 i_rx = 1'b0;
            
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b1;
    #160 i_rx = 1'b1;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    
    #160 i_rx = 1'b1;
    
    #20 opcode = 5'b01100;
    
    #20 opcode = 0;
    #500000000 $finish;
end


always #2.5 clk=~clk;
always #5 tick=~tick;



interfaz
#(
    .NB_DATA(DATA),
    .NB_OPCODE(OPCODE),
    .NB_ADDR(ADDR),
    .RAM_WIDTH(RAM)
)
u_agu
(
    .i_clk(clk),
    .i_rst(rst),
    .i_data(o_rx_interfaz_data),
    .i_done_data(o_rx_interfaz_done_data),
    .i_opcode(opcode),
    .i_acc(acc),
    .i_pc(pc),
    .i_done_tx(o_tx_interfaz_done_data),
    .o_int_tx(i_int_tx),
    .o_uart(i_interfaz_tx_data),
    .o_bip(bip_enable)
);

tx #(.NB_DATA(DATA), .SB_TICK(TICK))
u_agu1
(
    .i_clk(clk),
    .i_rst(rst),
    .i_tx_start(i_int_tx),
    .i_tick(tick),
    .i_data(i_interfaz_tx_data),       
    .o_done_tx(o_tx_interfaz_done_data),       
    .o_tx(o_tx) 
);

rx #(.NB_DATA(DATA), .SB_TICK(TICK))
u_agu2
(
    .i_clk(clk),
    .i_rst(rst),
    .i_bit(i_rx),                  
    .i_tick(tick),
    .o_done_data(o_rx_interfaz_done_data),  
    .o_data(o_rx_interfaz_data)      
);


endmodule
module tb_interfaz();


localparam DATA = 8;
localparam ADDR =11;
localparam OPCODE =5;
localparam RAM =16;
localparam TICK= 16;

reg clk;
reg rst;
reg [OPCODE-1:0] opcode;
reg [RAM-1:0] acc;
reg [ADDR-1:0] pc;
wire bip_enable;
reg tick;
wire i_int_tx;
wire [DATA-1:0] i_interfaz_tx_data;
reg i_rx;
wire o_tx_interfaz_done_data;
wire o_tx;
wire o_rx_interfaz_done_data;
wire [DATA-1:0] o_rx_interfaz_data;

initial
begin
    clk = 1'b0;
    tick = 1'b0;
    rst = 1'b0;
    opcode= 5'b1;
    i_rx= 1'b1;
    #10 rst= 1'b1;
    #160 i_rx = 1'b0;
            
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b1;
    #160 i_rx = 1'b1;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    
    #160 i_rx = 1'b1;
    
    #20 opcode = 5'b01100;
    
    #20 opcode = 0;
    #500000000 $finish;
end


always #2.5 clk=~clk;
always #5 tick=~tick;



interfaz
#(
    .NB_DATA(DATA),
    .NB_OPCODE(OPCODE),
    .NB_ADDR(ADDR),
    .RAM_WIDTH(RAM)
)
u_agu
(
    .i_clk(clk),
    .i_rst(rst),
    .i_data(o_rx_interfaz_data),
    .i_done_data(o_rx_interfaz_done_data),
    .i_opcode(opcode),
    .i_acc(acc),
    .i_pc(pc),
    .i_done_tx(o_tx_interfaz_done_data),
    .o_int_tx(i_int_tx),
    .o_uart(i_interfaz_tx_data),
    .o_bip(bip_enable)
);

tx #(.NB_DATA(DATA), .SB_TICK(TICK))
u_agu1
(
    .i_clk(clk),
    .i_rst(rst),
    .i_tx_start(i_int_tx),
    .i_tick(tick),
    .i_data(i_interfaz_tx_data),       
    .o_done_tx(o_tx_interfaz_done_data),       
    .o_tx(o_tx) 
);

rx #(.NB_DATA(DATA), .SB_TICK(TICK))
u_agu2
(
    .i_clk(clk),
    .i_rst(rst),
    .i_bit(i_rx),                  
    .i_tick(tick),
    .o_done_data(o_rx_interfaz_done_data),  
    .o_data(o_rx_interfaz_data)      
);


endmodule