data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_sim.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_sim);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:19: Unsupported: Ignoring delay on this delayed statement.\n    #1000000\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:24: Unsupported: Ignoring delay on this delayed statement.\n    initial #(RATE*10) reset <= 1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:27: Unsupported: Ignoring delay on this delayed statement.\n    always  #(RATE/2.0) clk  = ~clk;\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:65: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_adr_i = wb_adr_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:66: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_dat_i = wb_dat_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:67: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_we_i  = wb_we_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:68: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_sel_i = wb_sel_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:69: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_stb_i = wb_stb_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:91: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:97: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:99: syntax error, unexpected \'@\'\n                @(negedge wb_clk_i);\n                ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:113: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:119: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:121: syntax error, unexpected \'@\'\n                @(negedge wb_clk_i);\n                ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:139: syntax error, unexpected \'@\'\n    @(negedge wb_rst_i);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:141: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:145: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_semaphore/tb_sim.sv:147: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Error: Exiting due to 14 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sim();
    localparam RATE = 1000.0/200.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #1000000
        $finish;
    end
    
    logic     reset = 1'b1;
    initial #(RATE*10) reset <= 1'b0;

    logic     clk = 1'b1;
    always  #(RATE/2.0) clk  = ~clk;
    





    
    tb_sim_main
        i_sim_main
            (
                .*
            );
    
    





    
    localparam  WB_DAT_SIZE  = 3;
    localparam  WB_ADR_WIDTH = 40 - WB_DAT_SIZE;
    localparam  WB_DAT_WIDTH = (8 << WB_DAT_SIZE);
    localparam  WB_SEL_WIDTH = (1 << WB_DAT_SIZE);
    

    wire                            wb_rst_i = i_top.wb_peri_rst_i;
    wire                            wb_clk_i = i_top.wb_peri_clk_i;
    reg     [WB_ADR_WIDTH-1:0]      wb_adr_o;
    wire    [WB_DAT_WIDTH-1:0]      wb_dat_i = i_top.wb_peri_dat_o;
    reg     [WB_DAT_WIDTH-1:0]      wb_dat_o;
    reg                             wb_we_o;
    reg     [WB_SEL_WIDTH-1:0]      wb_sel_o;
    reg                             wb_stb_o = 0;
    wire                            wb_ack_i = i_top.wb_peri_ack_o;
    
    initial begin
        force i_top.wb_peri_adr_i = wb_adr_o;
        force i_top.wb_peri_dat_i = wb_dat_o;
        force i_top.wb_peri_we_i  = wb_we_o;
        force i_top.wb_peri_sel_i = wb_sel_o;
        force i_top.wb_peri_stb_i = wb_stb_o;
    end
    
    
    
    reg     [WB_DAT_WIDTH-1:0]      reg_wb_dat;
    reg                             reg_wb_ack;
    always @(posedge wb_clk_i) begin
        if ( ~wb_we_o & wb_stb_o & wb_ack_i ) begin
            reg_wb_dat <= wb_dat_i;
        end
        reg_wb_ack <= wb_ack_i;
    end
    
    
    task wb_write(
                input [WB_ADR_WIDTH-1:0]    adr,
                input [WB_DAT_WIDTH-1:0]    dat,
                input [WB_SEL_WIDTH-1:0]    sel
            );
    begin
        $display("WISHBONE_WRITE(adr:%h dat:%h sel:%b)", adr, dat, sel);
        @(negedge wb_clk_i);
            wb_adr_o = adr;
            wb_dat_o = dat;
            wb_sel_o = sel;
            wb_we_o  = 1'b1;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
    end
    endtask
    
    task wb_read(
                input [WB_ADR_WIDTH-1:0]    adr
            );
    begin
        @(negedge wb_clk_i);
            wb_adr_o = adr;
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'b1}};
            wb_we_o  = 1'b0;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
            $display("WISHBONE_READ(adr:%h dat:%h)", adr, reg_wb_dat);
    end
    endtask
    




     
    
    initial begin
    @(negedge wb_rst_i);
    
    #10000;
        $display(" --- test --- ");
        wb_read (0);
        wb_write(0, 64'h0123456789abcdef, 8'h0f);
    #10000;
    
    #10000;
        $finish();
        
    end
    
endmodule
module tb_sim();

    localparam RATE = 1000.0/200.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #1000000
        $finish;
    end
    
    logic     reset = 1'b1;
    initial #(RATE*10) reset <= 1'b0;

    logic     clk = 1'b1;
    always  #(RATE/2.0) clk  = ~clk;
    





    
    tb_sim_main
        i_sim_main
            (
                .*
            );
    
    





    
    localparam  WB_DAT_SIZE  = 3;
    localparam  WB_ADR_WIDTH = 40 - WB_DAT_SIZE;
    localparam  WB_DAT_WIDTH = (8 << WB_DAT_SIZE);
    localparam  WB_SEL_WIDTH = (1 << WB_DAT_SIZE);
    

    wire                            wb_rst_i = i_top.wb_peri_rst_i;
    wire                            wb_clk_i = i_top.wb_peri_clk_i;
    reg     [WB_ADR_WIDTH-1:0]      wb_adr_o;
    wire    [WB_DAT_WIDTH-1:0]      wb_dat_i = i_top.wb_peri_dat_o;
    reg     [WB_DAT_WIDTH-1:0]      wb_dat_o;
    reg                             wb_we_o;
    reg     [WB_SEL_WIDTH-1:0]      wb_sel_o;
    reg                             wb_stb_o = 0;
    wire                            wb_ack_i = i_top.wb_peri_ack_o;
    
    initial begin
        force i_top.wb_peri_adr_i = wb_adr_o;
        force i_top.wb_peri_dat_i = wb_dat_o;
        force i_top.wb_peri_we_i  = wb_we_o;
        force i_top.wb_peri_sel_i = wb_sel_o;
        force i_top.wb_peri_stb_i = wb_stb_o;
    end
    
    
    
    reg     [WB_DAT_WIDTH-1:0]      reg_wb_dat;
    reg                             reg_wb_ack;
    always @(posedge wb_clk_i) begin
        if ( ~wb_we_o & wb_stb_o & wb_ack_i ) begin
            reg_wb_dat <= wb_dat_i;
        end
        reg_wb_ack <= wb_ack_i;
    end
    
    
    task wb_write(
                input [WB_ADR_WIDTH-1:0]    adr,
                input [WB_DAT_WIDTH-1:0]    dat,
                input [WB_SEL_WIDTH-1:0]    sel
            );
    begin
        $display("WISHBONE_WRITE(adr:%h dat:%h sel:%b)", adr, dat, sel);
        @(negedge wb_clk_i);
            wb_adr_o = adr;
            wb_dat_o = dat;
            wb_sel_o = sel;
            wb_we_o  = 1'b1;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
    end
    endtask
    
    task wb_read(
                input [WB_ADR_WIDTH-1:0]    adr
            );
    begin
        @(negedge wb_clk_i);
            wb_adr_o = adr;
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'b1}};
            wb_we_o  = 1'b0;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
            $display("WISHBONE_READ(adr:%h dat:%h)", adr, reg_wb_dat);
    end
    endtask
    




     
    
    initial begin
    @(negedge wb_rst_i);
    
    #10000;
        $display(" --- test --- ");
        wb_read (0);
        wb_write(0, 64'h0123456789abcdef, 8'h0f);
    #10000;
    
    #10000;
        $finish();
        
    end
    
endmodule