data/full_repos/permissive/143278/ivltests/cprop.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/cprop.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #0 if (out0 !== 1\'b0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire a = 1'b0;
   wire b = 1'b1;
   wire c = 1'b1;
   wire d = 1'bx;

   wire out0, out1, out2, out3;

   and (out0, a, b);
   and (out1, b, c);
   and (out2, a, d);
   and (out3, b, d);

   initial begin
      #0 if (out0 !== 1'b0) begin
	 $display("FAILED -- out0 = %b", out0);
	 $finish;
      end

      if (out1 !== 1'b1) begin
	 $display("FAILED -- out1 = %b", out1);
	 $finish;
      end

      if (out2 !== 1'b0) begin
	 $display("FAILED -- out2 = %b", out2);
	 $finish;
      end

      if (out3 !== 1'bx) begin
	 $display("FAILED -- outx = %b", out3);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   wire a = 1'b0;
   wire b = 1'b1;
   wire c = 1'b1;
   wire d = 1'bx;

   wire out0, out1, out2, out3;

   and (out0, a, b);
   and (out1, b, c);
   and (out2, a, d);
   and (out3, b, d);

   initial begin
      #0 if (out0 !== 1'b0) begin
	 $display("FAILED -- out0 = %b", out0);
	 $finish;
      end

      if (out1 !== 1'b1) begin
	 $display("FAILED -- out1 = %b", out1);
	 $finish;
      end

      if (out2 !== 1'b0) begin
	 $display("FAILED -- out2 = %b", out2);
	 $finish;
      end

      if (out3 !== 1'bx) begin
	 $display("FAILED -- outx = %b", out3);
	 $finish;
      end

      $display("PASSED");
   end

endmodule