data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v
1: b'%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:1: Cannot find include file: ctrl_encode_def.v\n`include "ctrl_encode_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/ctrl_encode_def.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/ctrl_encode_def.v.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/ctrl_encode_def.v.sv\n             ctrl_encode_def.v\n             ctrl_encode_def.v.v\n             ctrl_encode_def.v.sv\n             obj_dir/ctrl_encode_def.v\n             obj_dir/ctrl_encode_def.v.v\n             obj_dir/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:2: Cannot find include file: instruction_def.v\n`include "instruction_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:79: Define or directive not defined: \'`INSTR_RTYPE_OP\'\n assign RType   = (Op == `INSTR_RTYPE_OP);\n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:79: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign RType   = (Op == `INSTR_RTYPE_OP);\n                                        ^\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:80: Define or directive not defined: \'`INSTR_ADDI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:80: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                        ^~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:80: Define or directive not defined: \'`INSTR_ADDIU_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:80: Define or directive not defined: \'`INSTR_ANDI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:80: Define or directive not defined: \'`INSTR_ORI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                                                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:80: Define or directive not defined: \'`INSTR_XORI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                                                                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:80: Define or directive not defined: \'`INSTR_LUI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                                                                                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:80: Define or directive not defined: \'`INSTR_SLTI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                                                                                                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:80: Define or directive not defined: \'`INSTR_SLTIU_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                                                                                                                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:81: Define or directive not defined: \'`INSTR_BEQ_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:81: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                       ^~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:81: Define or directive not defined: \'`INSTR_BNE_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:81: Define or directive not defined: \'`INSTR_BGEZ_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:81: Define or directive not defined: \'`INSTR_BGTZ_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                                                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:81: Define or directive not defined: \'`INSTR_BLEZ_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                                                                                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:81: Define or directive not defined: \'`INSTR_BLTZ_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                                                                                                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:82: Define or directive not defined: \'`INSTR_J_OP\'\n assign JType   = (Op == `INSTR_J_OP || Op == `INSTR_JAL_OP);\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:82: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign JType   = (Op == `INSTR_J_OP || Op == `INSTR_JAL_OP);\n                                     ^~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:82: Define or directive not defined: \'`INSTR_JAL_OP\'\n assign JType   = (Op == `INSTR_J_OP || Op == `INSTR_JAL_OP);\n                                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:83: Define or directive not defined: \'`INSTR_LW_OP\'\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:83: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                                      ^~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:83: Define or directive not defined: \'`INSTR_LB_OP\'\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:83: Define or directive not defined: \'`INSTR_LH_OP\'\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                                                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:83: Define or directive not defined: \'`INSTR_LBU_OP\'\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                                                                                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:83: Define or directive not defined: \'`INSTR_LHU_OP\'\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                                                                                                                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:84: Define or directive not defined: \'`INSTR_SW_OP\'\n assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:84: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);\n                                      ^~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:84: Define or directive not defined: \'`INSTR_SB_OP\'\n assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);\n                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:84: Define or directive not defined: \'`INSTR_SH_OP\'\n assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);\n                                                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:115: Define or directive not defined: \'`EXT_SIGNED\'\n  EXTOp = `EXT_SIGNED;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:115: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  EXTOp = `EXT_SIGNED;\n                     ^\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:125: Define or directive not defined: \'`BE_SW\'\n  be = `BE_SW;\n       ^~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:125: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  be = `BE_SW;\n             ^\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:140: Define or directive not defined: \'`EXT_SIGNED\'\n EXTOp = `EXT_SIGNED;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:140: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n EXTOp = `EXT_SIGNED;\n                    ^\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:143: Define or directive not defined: \'`EXT_UNSIGNED\'\n  EXTOp = `EXT_UNSIGNED;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:143: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  EXTOp = `EXT_UNSIGNED;\n                       ^\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:144: Define or directive not defined: \'`INSTR_JR_FUNCT\'\n if (RType && (Funct == `INSTR_JR_FUNCT || Funct == `INSTR_JALR_FUNCT))\n                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:144: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (RType && (Funct == `INSTR_JR_FUNCT || Funct == `INSTR_JALR_FUNCT))\n                                        ^~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:144: Define or directive not defined: \'`INSTR_JALR_FUNCT\'\n if (RType && (Funct == `INSTR_JR_FUNCT || Funct == `INSTR_JALR_FUNCT))\n                                                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:146: Define or directive not defined: \'`EXT_SIGNED\'\n  EXTOp = `EXT_SIGNED;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:150: syntax error, unexpected \'=\', expecting IDENTIFIER\n  EXTOp = `EXT_SIGNED;\n        ^\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:150: Define or directive not defined: \'`EXT_SIGNED\'\n  EXTOp = `EXT_SIGNED;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:153: syntax error, unexpected \'=\', expecting IDENTIFIER\n  EXTOp = `EXT_SIGNED;\n        ^\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:153: Define or directive not defined: \'`EXT_SIGNED\'\n  EXTOp = `EXT_SIGNED;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Ctrl.v:157: syntax error, unexpected \'=\', expecting IDENTIFIER\n  EXTOp = `EXT_SIGNED;\n        ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ctrl(clk, rst, instr, step,
		EXTOp, jmpSignal, jmpRSignal,
		control_EX_MemRead, ASel, BSel, ALUOp, WriteDstSel, EX_ctrl_regWr,
		MEM_ctrl_regWr, be, DMWr,
		WB_ctrl_regWr, WriteContentSel, WriteDstRegSel
	);
           





	input 			clk, rst;
	input	[1:0]	step;
	input	[31:0]	instr;



	output	[1:0]	EXTOp;
	output			jmpSignal;
	output			jmpRSignal;



	output			EX_ctrl_regWr;
	output			control_EX_MemRead;
	output	[1:0]	ASel;
	output			BSel;
	output	[4:0]	ALUOp;
	output			WriteDstSel;



	output			MEM_ctrl_regWr;
	output	[1:0]	be;
	output			DMWr;
	


	output			WB_ctrl_regWr;	
	output	[1:0]	WriteContentSel;
	output			WriteDstRegSel;

	
	




	wire	RType;
	wire	IType;
	wire	BrType;
	wire	JType;
	wire	LdType;
	wire	StType;
	wire	MemType;
	
	wire	[5:0]	Op;
	wire	[5:0]	Funct;
	wire	[4:0]	rs;
	wire	[4:0]	rt;
	wire	[4:0]	rd;
	wire	[15:0]	Imm16;
	wire	[25:0]	IMM;
	wire	[31:0]	shamt;
	
	assign	Op = instr[31:26];
	assign	Funct = instr[5:0];
	assign	rs = instr[25:21];
	assign	rt = instr[20:16];
	assign	rd = instr[15:11];
	assign	Imm16 = instr[15:0];
	assign	IMM = instr[25:0];
	assign	shamt = {32'b0, instr[10:6]};
	

	assign RType   = (Op == `INSTR_RTYPE_OP);
	assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);
	assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);
	assign JType   = (Op == `INSTR_J_OP || Op == `INSTR_JAL_OP);
	assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);
	assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);
	assign MemType = LdType || StType;


    



	reg	[1:0]	EXTOp;
	reg  jmpSignal;
	reg  jmpRSignal;

	reg			EX_ctrl_regWr;
	reg			control_EX_MemRead;
	reg	[1:0]	ASel;
	reg			BSel;
	reg	[4:0]	ALUOp;
	reg			WriteDstSel;

	reg			MEM_ctrl_regWr;
	reg	[1:0]	be;
	reg			DMWr;
	
	reg			WB_ctrl_regWr;
	reg	[1:0]	WriteContentSel;
	reg			WriteDstRegSel;
	
	initial
	begin
		jmpSignal = 0;
		jmpRSignal = 0;
		EXTOp = `EXT_SIGNED;
	 
		EX_ctrl_regWr = 0;
		control_EX_MemRead = 0;
		ASel = 2'b00;
		BSel = 1'b0;
		ALUOp = 0;
		WriteDstSel = 0;

		MEM_ctrl_regWr = 1'b0;
		be = `BE_SW;
		DMWr = 1'b0;

		WB_ctrl_regWr = 1'b0;
		WriteContentSel = 2'b00;
		WriteDstRegSel = 1'b0;
	end

 	always @(*) begin




	jmpSignal = 0;
	jmpRSignal = 0;
	EXTOp = `EXT_SIGNED;

	if (IType)
		EXTOp = `EXT_UNSIGNED;
	if (RType && (Funct == `INSTR_JR_FUNCT || Funct == `INSTR_JALR_FUNCT))
	begin
		EXTOp = `EXT_SIGNED;
		jmpRSignal = 1;
		end
	if (BrType)
		EXTOp = `EXT_SIGNED;
	if (JType)
	begin
		EXTOp = `EXT_SIGNED;
		jmpSignal = 1;
	end
	if (StType)
		EXTOp = `EXT_SIGNED;






	EX_ctrl_regWr = 0;
	control_EX_MemRead = 0;
	ASel = 2'b00;
	BSel = 1'b0;
	ALUOp = 0;
	WriteDstSel = 0;

	if (RType || IType || LdType)
		EX_ctrl_regWr = 1'b1;

	if (LdType || StType)
	begin
		ASel = 2'b00;
		BSel = 1'b1;
		control_EX_MemRead = 1;
		ALUOp = `ALUOp_ADD;
		WriteDstSel = 1'b0;
	end

	if (RType)
	begin
		ASel = 2'b00;
		BSel = 1'b0;
		WriteDstSel = 1'b1;
		case (Funct)
			`INSTR_ADD_FUNCT: ALUOp = `ALUOp_ADD;
            `INSTR_ADDU_FUNCT: ALUOp = `ALUOp_ADDU;
            `INSTR_SUB_FUNCT: ALUOp = `ALUOp_SUB;
            `INSTR_SUBU_FUNCT: ALUOp = `ALUOp_SUBU;
			`INSTR_AND_FUNCT: ALUOp = `ALUOp_AND;
            `INSTR_NOR_FUNCT: ALUOp = `ALUOp_NOR;
            `INSTR_OR_FUNCT: ALUOp = `ALUOp_OR;
            `INSTR_XOR_FUNCT: ALUOp = `ALUOp_XOR;
            `INSTR_SLT_FUNCT: ALUOp = `ALUOp_SLT;
            `INSTR_SLTU_FUNCT: ALUOp = `ALUOp_SLTU;
			`INSTR_SLL_FUNCT:
			begin
				ALUOp = `ALUOp_SLL;
				ASel = 2'b10;
			end
			`INSTR_SRL_FUNCT: 
            begin
                ALUOp = `ALUOp_SRL;
                ASel = 2'b10;
            end  
            `INSTR_SRA_FUNCT:
            begin
				ALUOp = `ALUOp_SRA;
				ASel = 2'b10;
            end
            `INSTR_SLLV_FUNCT:
            begin
                ALUOp = `ALUOp_SLL;
                ASel = 2'b10;
                BSel = 1'b0;
            end
			`INSTR_SRLV_FUNCT:
            begin
                ALUOp = `ALUOp_SRL;
                ASel = 2'b10;
			end
            `INSTR_SRAV_FUNCT:
            begin
                ALUOp = `ALUOp_SRA;
                ASel = 2'b10;
            end
			


		   default:;
	   endcase
	end

	if (IType)
	begin
		ASel = 2'b00;
		BSel = 1'b1;
		WriteDstSel = 1'b0;
		if (Op == `INSTR_ADDI_OP)
			ALUOp = `ALUOp_ADD;
		if (Op == `INSTR_ADDIU_OP)
			ALUOp = `ALUOp_ADD;
		if (Op == `INSTR_ANDI_OP)
			ALUOp = `ALUOp_AND;
		if (Op == `INSTR_ORI_OP)
			ALUOp = `ALUOp_OR;
		if (Op == `INSTR_XORI_OP)
			ALUOp = `ALUOp_XOR;
		if (Op == `INSTR_LUI_OP)
		begin
			ASel = 2'b01;
			ALUOp = `ALUOp_SLL;
		end
		if (Op == `INSTR_SLTI_OP)
			ALUOp = `ALUOp_SLT;
		if (Op == `INSTR_SLTIU_OP)
			ALUOp = `ALUOp_SLT;
	end






	MEM_ctrl_regWr = 1'b0;
	be = `BE_SW;
	DMWr = 1'b0;

	if (RType || IType || LdType)
		MEM_ctrl_regWr = 1'b1;
	if (MemType)
	begin
		if (Op == `INSTR_LW_OP || Op == `INSTR_SW_OP)
			be = `BE_SW;
		if (Op == `INSTR_LH_OP || Op == `INSTR_SH_OP)
			be = `BE_SH;
		if (Op == `INSTR_LB_OP || Op == `INSTR_SB_OP)
			be = `BE_SB;
	end
	if (StType)
		DMWr = 1'b1;
	else
		DMWr = 1'b0;






	WB_ctrl_regWr = 1'b0;
	WriteContentSel = 2'b00;
	WriteDstRegSel = 1'b0;

	if (RType || IType || LdType || (Op == `INSTR_JAL_OP))
		WB_ctrl_regWr = 1'b1;
	if (LdType)
		WriteContentSel = 2'b01;
	if (Op == `INSTR_JAL_OP)
	begin
		WriteContentSel = 2'b10;
		WriteDstRegSel = 1'b1;
	end

	end
endmodule
module ctrl(clk, rst, instr, step,
		EXTOp, jmpSignal, jmpRSignal,
		control_EX_MemRead, ASel, BSel, ALUOp, WriteDstSel, EX_ctrl_regWr,
		MEM_ctrl_regWr, be, DMWr,
		WB_ctrl_regWr, WriteContentSel, WriteDstRegSel
	);

           





	input 			clk, rst;
	input	[1:0]	step;
	input	[31:0]	instr;



	output	[1:0]	EXTOp;
	output			jmpSignal;
	output			jmpRSignal;



	output			EX_ctrl_regWr;
	output			control_EX_MemRead;
	output	[1:0]	ASel;
	output			BSel;
	output	[4:0]	ALUOp;
	output			WriteDstSel;



	output			MEM_ctrl_regWr;
	output	[1:0]	be;
	output			DMWr;
	


	output			WB_ctrl_regWr;	
	output	[1:0]	WriteContentSel;
	output			WriteDstRegSel;

	
	




	wire	RType;
	wire	IType;
	wire	BrType;
	wire	JType;
	wire	LdType;
	wire	StType;
	wire	MemType;
	
	wire	[5:0]	Op;
	wire	[5:0]	Funct;
	wire	[4:0]	rs;
	wire	[4:0]	rt;
	wire	[4:0]	rd;
	wire	[15:0]	Imm16;
	wire	[25:0]	IMM;
	wire	[31:0]	shamt;
	
	assign	Op = instr[31:26];
	assign	Funct = instr[5:0];
	assign	rs = instr[25:21];
	assign	rt = instr[20:16];
	assign	rd = instr[15:11];
	assign	Imm16 = instr[15:0];
	assign	IMM = instr[25:0];
	assign	shamt = {32'b0, instr[10:6]};
	

	assign RType   = (Op == `INSTR_RTYPE_OP);
	assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);
	assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);
	assign JType   = (Op == `INSTR_J_OP || Op == `INSTR_JAL_OP);
	assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);
	assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);
	assign MemType = LdType || StType;


    



	reg	[1:0]	EXTOp;
	reg  jmpSignal;
	reg  jmpRSignal;

	reg			EX_ctrl_regWr;
	reg			control_EX_MemRead;
	reg	[1:0]	ASel;
	reg			BSel;
	reg	[4:0]	ALUOp;
	reg			WriteDstSel;

	reg			MEM_ctrl_regWr;
	reg	[1:0]	be;
	reg			DMWr;
	
	reg			WB_ctrl_regWr;
	reg	[1:0]	WriteContentSel;
	reg			WriteDstRegSel;
	
	initial
	begin
		jmpSignal = 0;
		jmpRSignal = 0;
		EXTOp = `EXT_SIGNED;
	 
		EX_ctrl_regWr = 0;
		control_EX_MemRead = 0;
		ASel = 2'b00;
		BSel = 1'b0;
		ALUOp = 0;
		WriteDstSel = 0;

		MEM_ctrl_regWr = 1'b0;
		be = `BE_SW;
		DMWr = 1'b0;

		WB_ctrl_regWr = 1'b0;
		WriteContentSel = 2'b00;
		WriteDstRegSel = 1'b0;
	end

 	always @(*) begin




	jmpSignal = 0;
	jmpRSignal = 0;
	EXTOp = `EXT_SIGNED;

	if (IType)
		EXTOp = `EXT_UNSIGNED;
	if (RType && (Funct == `INSTR_JR_FUNCT || Funct == `INSTR_JALR_FUNCT))
	begin
		EXTOp = `EXT_SIGNED;
		jmpRSignal = 1;
		end
	if (BrType)
		EXTOp = `EXT_SIGNED;
	if (JType)
	begin
		EXTOp = `EXT_SIGNED;
		jmpSignal = 1;
	end
	if (StType)
		EXTOp = `EXT_SIGNED;






	EX_ctrl_regWr = 0;
	control_EX_MemRead = 0;
	ASel = 2'b00;
	BSel = 1'b0;
	ALUOp = 0;
	WriteDstSel = 0;

	if (RType || IType || LdType)
		EX_ctrl_regWr = 1'b1;

	if (LdType || StType)
	begin
		ASel = 2'b00;
		BSel = 1'b1;
		control_EX_MemRead = 1;
		ALUOp = `ALUOp_ADD;
		WriteDstSel = 1'b0;
	end

	if (RType)
	begin
		ASel = 2'b00;
		BSel = 1'b0;
		WriteDstSel = 1'b1;
		case (Funct)
			`INSTR_ADD_FUNCT: ALUOp = `ALUOp_ADD;
            `INSTR_ADDU_FUNCT: ALUOp = `ALUOp_ADDU;
            `INSTR_SUB_FUNCT: ALUOp = `ALUOp_SUB;
            `INSTR_SUBU_FUNCT: ALUOp = `ALUOp_SUBU;
			`INSTR_AND_FUNCT: ALUOp = `ALUOp_AND;
            `INSTR_NOR_FUNCT: ALUOp = `ALUOp_NOR;
            `INSTR_OR_FUNCT: ALUOp = `ALUOp_OR;
            `INSTR_XOR_FUNCT: ALUOp = `ALUOp_XOR;
            `INSTR_SLT_FUNCT: ALUOp = `ALUOp_SLT;
            `INSTR_SLTU_FUNCT: ALUOp = `ALUOp_SLTU;
			`INSTR_SLL_FUNCT:
			begin
				ALUOp = `ALUOp_SLL;
				ASel = 2'b10;
			end
			`INSTR_SRL_FUNCT: 
            begin
                ALUOp = `ALUOp_SRL;
                ASel = 2'b10;
            end  
            `INSTR_SRA_FUNCT:
            begin
				ALUOp = `ALUOp_SRA;
				ASel = 2'b10;
            end
            `INSTR_SLLV_FUNCT:
            begin
                ALUOp = `ALUOp_SLL;
                ASel = 2'b10;
                BSel = 1'b0;
            end
			`INSTR_SRLV_FUNCT:
            begin
                ALUOp = `ALUOp_SRL;
                ASel = 2'b10;
			end
            `INSTR_SRAV_FUNCT:
            begin
                ALUOp = `ALUOp_SRA;
                ASel = 2'b10;
            end
			


		   default:;
	   endcase
	end

	if (IType)
	begin
		ASel = 2'b00;
		BSel = 1'b1;
		WriteDstSel = 1'b0;
		if (Op == `INSTR_ADDI_OP)
			ALUOp = `ALUOp_ADD;
		if (Op == `INSTR_ADDIU_OP)
			ALUOp = `ALUOp_ADD;
		if (Op == `INSTR_ANDI_OP)
			ALUOp = `ALUOp_AND;
		if (Op == `INSTR_ORI_OP)
			ALUOp = `ALUOp_OR;
		if (Op == `INSTR_XORI_OP)
			ALUOp = `ALUOp_XOR;
		if (Op == `INSTR_LUI_OP)
		begin
			ASel = 2'b01;
			ALUOp = `ALUOp_SLL;
		end
		if (Op == `INSTR_SLTI_OP)
			ALUOp = `ALUOp_SLT;
		if (Op == `INSTR_SLTIU_OP)
			ALUOp = `ALUOp_SLT;
	end






	MEM_ctrl_regWr = 1'b0;
	be = `BE_SW;
	DMWr = 1'b0;

	if (RType || IType || LdType)
		MEM_ctrl_regWr = 1'b1;
	if (MemType)
	begin
		if (Op == `INSTR_LW_OP || Op == `INSTR_SW_OP)
			be = `BE_SW;
		if (Op == `INSTR_LH_OP || Op == `INSTR_SH_OP)
			be = `BE_SH;
		if (Op == `INSTR_LB_OP || Op == `INSTR_SB_OP)
			be = `BE_SB;
	end
	if (StType)
		DMWr = 1'b1;
	else
		DMWr = 1'b0;






	WB_ctrl_regWr = 1'b0;
	WriteContentSel = 2'b00;
	WriteDstRegSel = 1'b0;

	if (RType || IType || LdType || (Op == `INSTR_JAL_OP))
		WB_ctrl_regWr = 1'b1;
	if (LdType)
		WriteContentSel = 2'b01;
	if (Op == `INSTR_JAL_OP)
	begin
		WriteContentSel = 2'b10;
		WriteDstRegSel = 1'b1;
	end

	end
endmodule