data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sources_1/new/CLA_top.v
1: b"%Error: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sources_1/new/CLA_top.v:37: Cannot find file containing module: 'add_half'\nadd_half HA0 (A[0], B[0], g_from_ha[0], p_from_ha[0]);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sources_1/new,data/full_repos/permissive/124604849/add_half\n             data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sources_1/new,data/full_repos/permissive/124604849/add_half.v\n             data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sources_1/new,data/full_repos/permissive/124604849/add_half.sv\n             add_half\n             add_half.v\n             add_half.sv\n             obj_dir/add_half\n             obj_dir/add_half.v\n             obj_dir/add_half.sv\n%Error: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sources_1/new/CLA_top.v:38: Cannot find file containing module: 'add_half'\nadd_half HA1 (A[1], B[1], g_from_ha[1], p_from_ha[1]);\n^~~~~~~~\n%Error: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sources_1/new/CLA_top.v:39: Cannot find file containing module: 'add_half'\nadd_half HA2 (A[2], B[2], g_from_ha[2], p_from_ha[2]);\n^~~~~~~~\n%Error: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sources_1/new/CLA_top.v:40: Cannot find file containing module: 'add_half'\nadd_half HA3 (A[3], B[3], g_from_ha[3], p_from_ha[3]);\n^~~~~~~~\n%Error: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sources_1/new/CLA_top.v:48: Cannot find file containing module: 'CLAgen_4bit'\nCLAgen_4bit CLAGEN (g_from_ha, p_from_ha, c_in, c_from_CLA);\n^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module CLA_adder_4bit(
input [3:0] A,
input [3:0] B,
input c_in,
output reg [3:0] SUM,
output reg c_out
);

wire [3:0] p_from_ha;
wire [3:0] g_from_ha;
wire [4:1] c_from_CLA;
wire [3:0] SUM_from_HA;


add_half HA0 (A[0], B[0], g_from_ha[0], p_from_ha[0]);
add_half HA1 (A[1], B[1], g_from_ha[1], p_from_ha[1]);
add_half HA2 (A[2], B[2], g_from_ha[2], p_from_ha[2]);
add_half HA3 (A[3], B[3], g_from_ha[3], p_from_ha[3]);







CLAgen_4bit CLAGEN (g_from_ha, p_from_ha, c_in, c_from_CLA);

always@(*)
begin
    SUM[0] <= p_from_ha[0] ^ c_in;
    SUM[1] <= p_from_ha[1] ^ c_from_CLA[1];
    SUM[2] <= p_from_ha[2] ^ c_from_CLA[2];
    SUM[3] <= p_from_ha[3] ^ c_from_CLA[3];
    c_out <= c_from_CLA[4];
end







endmodule
module CLA_adder_4bit(
input [3:0] A,
input [3:0] B,
input c_in,
output reg [3:0] SUM,
output reg c_out
);


wire [3:0] p_from_ha;
wire [3:0] g_from_ha;
wire [4:1] c_from_CLA;
wire [3:0] SUM_from_HA;


add_half HA0 (A[0], B[0], g_from_ha[0], p_from_ha[0]);
add_half HA1 (A[1], B[1], g_from_ha[1], p_from_ha[1]);
add_half HA2 (A[2], B[2], g_from_ha[2], p_from_ha[2]);
add_half HA3 (A[3], B[3], g_from_ha[3], p_from_ha[3]);







CLAgen_4bit CLAGEN (g_from_ha, p_from_ha, c_in, c_from_CLA);

always@(*)
begin
    SUM[0] <= p_from_ha[0] ^ c_in;
    SUM[1] <= p_from_ha[1] ^ c_from_CLA[1];
    SUM[2] <= p_from_ha[2] ^ c_from_CLA[2];
    SUM[3] <= p_from_ha[3] ^ c_from_CLA[3];
    c_out <= c_from_CLA[4];
end







endmodule