data/full_repos/permissive/162400762/usg_top.v
 line:134: before: "."
1: b"%Error: data/full_repos/permissive/162400762/usg_top.v:123: Cannot find file containing module: 'L4_Parser'\nL4_Parser L4parser(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/L4_Parser\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/L4_Parser.v\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/L4_Parser.sv\n             L4_Parser\n             L4_Parser.v\n             L4_Parser.sv\n             obj_dir/L4_Parser\n             obj_dir/L4_Parser.v\n             obj_dir/L4_Parser.sv\n%Error: data/full_repos/permissive/162400762/usg_top.v:140: Cannot find file containing module: 'Pre_Processor'\nPre_Processor preProcessor(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162400762/usg_top.v:165: Cannot find file containing module: 'Stateful_Firewall'\nStateful_Firewall statefulFirewall(\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162400762/usg_top.v:189: Cannot find file containing module: 'Transmitter'\nTransmitter transmitter(\n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module usg_top(
	clk,
	reset,


	pktin_data_wr,
	pktin_data,
	pktin_data_valid_wr,
	pktin_data_valid,
	pktin_ready,
	pktout_data_wr,
	pktout_data,
	pktout_data_valid_wr,
	pktout_data_valid,
	pktout_ready,


	cin_data_wr,
	cin_data,
	cin_ready,
	cout_data_wr,
	cout_data,
	cout_ready
);

parameter 	w_pkt = 134,
			
			L4PAR = 0,
			PREPRO = 1,
			SFW = 2,
			TRANS = 3,
			MAX_MODULE = 2;		

input								clk;
input								reset;
(*mark_debug = "true"*)	input								pktin_data_wr;
(*mark_debug = "true"*)	input			[w_pkt-1:0]			pktin_data;
(*mark_debug = "true"*)	input								pktin_data_valid_wr;
(*mark_debug = "true"*)	input								pktin_data_valid;
(*mark_debug = "true"*)	output	wire						pktin_ready;
(*mark_debug = "true"*)	output	wire						pktout_data_wr;
(*mark_debug = "true"*)	output	wire	[w_pkt-1:0]			pktout_data;
(*mark_debug = "true"*)	output	wire						pktout_data_valid_wr;
(*mark_debug = "true"*)	output	wire						pktout_data_valid;
(*mark_debug = "true"*)	input								pktout_ready;

input								cin_data_wr;
input			[w_pkt-1:0]			cin_data;
output	wire						cin_ready;
output	wire						cout_data_wr;
output wire		[w_pkt-1:0]			cout_data;
input								cout_ready;




wire					pkt_data_wr[MAX_MODULE:0];
wire	[w_pkt-1:0]		pkt_data[MAX_MODULE:0];
wire 					pkt_ready[MAX_MODULE:0];
wire					cData_wr[MAX_MODULE:0];
wire	[w_pkt-1:0]		cData[MAX_MODULE:0];
wire					cData_ready[MAX_MODULE:0];




L4_Parser L4parser(
.clk(clk),
.reset(reset),
.pktin_data_wr(pktin_data_wr),
.pktin_data(pktin_data),
.pktin_ready(pktin_ready),
.pktout_data_wr(pkt_data_wr[L4PAR]),
.pktout_data(pkt_data[L4PAR]),
.pktout_ready(pkt_ready[L4PAR])
);
defparam
	L4parser.LMID = 1;



Pre_Processor preProcessor(
.clk(clk),
.reset(reset),
.pktin_data_wr(pkt_data_wr[PREPRO-1]),
.pktin_data(pkt_data[PREPRO-1]),
.pktin_ready(pkt_ready[PREPRO-1]),
.pktout_data_wr(pkt_data_wr[PREPRO]),
.pktout_data(pkt_data[PREPRO]),
.pktout_ready(pkt_ready[PREPRO]),

.cin_data(cin_data),
.cin_data_wr(cin_data_wr),
.cin_ready(cin_ready),
.cout_data(cData[PREPRO]),
.cout_data_wr(cData_wr[PREPRO]),
.cout_ready(cData_ready[PREPRO])
);
defparam
	preProcessor.LMID = 6;




Stateful_Firewall statefulFirewall(
.clk(clk),
.reset(reset),
.pktin_data_wr(pkt_data_wr[SFW-1]),
.pktin_data(pkt_data[SFW-1]),
.pktin_ready(pkt_ready[SFW-1]),
.pktout_data_wr(pkt_data_wr[SFW]),
.pktout_data(pkt_data[SFW]),
.pktout_ready(pkt_ready[SFW]),

.cin_data(cData[SFW-1]),
.cin_data_wr(cData_wr[SFW-1]),
.cin_ready(cData_ready[SFW-1]),
.cout_data(cData[SFW]),
.cout_data_wr(cData_wr[SFW]),
.cout_ready(cData_ready[SFW])
);
defparam
	statefulFirewall.LMID = 7;



Transmitter transmitter(
.clk(clk),
.reset(reset),
.pktin_data_wr(pkt_data_wr[TRANS-1]),
.pktin_data(pkt_data[TRANS-1]),
.pktin_ready(pkt_ready[TRANS-1]),
.pktout_data_wr(pktout_data_wr),
.pktout_data(pktout_data),
.pktout_data_valid(pktout_data_valid),
.pktout_data_valid_wr(pktout_data_valid_wr),
.pktout_ready(pktout_ready),

.cin_data(cData[TRANS-1]),
.cin_data_wr(cData_wr[TRANS-1]),
.cin_ready(cData_ready[TRANS-1]),
.cout_data(cout_data),
.cout_data_wr(cout_data_wr),
.cout_ready(cout_ready)
);
defparam
	transmitter.LMID = 8;


endmodule
module usg_top(
	clk,
	reset,


	pktin_data_wr,
	pktin_data,
	pktin_data_valid_wr,
	pktin_data_valid,
	pktin_ready,
	pktout_data_wr,
	pktout_data,
	pktout_data_valid_wr,
	pktout_data_valid,
	pktout_ready,


	cin_data_wr,
	cin_data,
	cin_ready,
	cout_data_wr,
	cout_data,
	cout_ready
);


parameter 	w_pkt = 134,
			
			L4PAR = 0,
			PREPRO = 1,
			SFW = 2,
			TRANS = 3,
			MAX_MODULE = 2;		

input								clk;
input								reset;
(*mark_debug = "true"*)	input								pktin_data_wr;
(*mark_debug = "true"*)	input			[w_pkt-1:0]			pktin_data;
(*mark_debug = "true"*)	input								pktin_data_valid_wr;
(*mark_debug = "true"*)	input								pktin_data_valid;
(*mark_debug = "true"*)	output	wire						pktin_ready;
(*mark_debug = "true"*)	output	wire						pktout_data_wr;
(*mark_debug = "true"*)	output	wire	[w_pkt-1:0]			pktout_data;
(*mark_debug = "true"*)	output	wire						pktout_data_valid_wr;
(*mark_debug = "true"*)	output	wire						pktout_data_valid;
(*mark_debug = "true"*)	input								pktout_ready;

input								cin_data_wr;
input			[w_pkt-1:0]			cin_data;
output	wire						cin_ready;
output	wire						cout_data_wr;
output wire		[w_pkt-1:0]			cout_data;
input								cout_ready;




wire					pkt_data_wr[MAX_MODULE:0];
wire	[w_pkt-1:0]		pkt_data[MAX_MODULE:0];
wire 					pkt_ready[MAX_MODULE:0];
wire					cData_wr[MAX_MODULE:0];
wire	[w_pkt-1:0]		cData[MAX_MODULE:0];
wire					cData_ready[MAX_MODULE:0];




L4_Parser L4parser(
.clk(clk),
.reset(reset),
.pktin_data_wr(pktin_data_wr),
.pktin_data(pktin_data),
.pktin_ready(pktin_ready),
.pktout_data_wr(pkt_data_wr[L4PAR]),
.pktout_data(pkt_data[L4PAR]),
.pktout_ready(pkt_ready[L4PAR])
);
defparam
	L4parser.LMID = 1;



Pre_Processor preProcessor(
.clk(clk),
.reset(reset),
.pktin_data_wr(pkt_data_wr[PREPRO-1]),
.pktin_data(pkt_data[PREPRO-1]),
.pktin_ready(pkt_ready[PREPRO-1]),
.pktout_data_wr(pkt_data_wr[PREPRO]),
.pktout_data(pkt_data[PREPRO]),
.pktout_ready(pkt_ready[PREPRO]),

.cin_data(cin_data),
.cin_data_wr(cin_data_wr),
.cin_ready(cin_ready),
.cout_data(cData[PREPRO]),
.cout_data_wr(cData_wr[PREPRO]),
.cout_ready(cData_ready[PREPRO])
);
defparam
	preProcessor.LMID = 6;




Stateful_Firewall statefulFirewall(
.clk(clk),
.reset(reset),
.pktin_data_wr(pkt_data_wr[SFW-1]),
.pktin_data(pkt_data[SFW-1]),
.pktin_ready(pkt_ready[SFW-1]),
.pktout_data_wr(pkt_data_wr[SFW]),
.pktout_data(pkt_data[SFW]),
.pktout_ready(pkt_ready[SFW]),

.cin_data(cData[SFW-1]),
.cin_data_wr(cData_wr[SFW-1]),
.cin_ready(cData_ready[SFW-1]),
.cout_data(cData[SFW]),
.cout_data_wr(cData_wr[SFW]),
.cout_ready(cData_ready[SFW])
);
defparam
	statefulFirewall.LMID = 7;



Transmitter transmitter(
.clk(clk),
.reset(reset),
.pktin_data_wr(pkt_data_wr[TRANS-1]),
.pktin_data(pkt_data[TRANS-1]),
.pktin_ready(pkt_ready[TRANS-1]),
.pktout_data_wr(pktout_data_wr),
.pktout_data(pktout_data),
.pktout_data_valid(pktout_data_valid),
.pktout_data_valid_wr(pktout_data_valid_wr),
.pktout_ready(pktout_ready),

.cin_data(cData[TRANS-1]),
.cin_data_wr(cData_wr[TRANS-1]),
.cin_ready(cData_ready[TRANS-1]),
.cout_data(cout_data),
.cout_data_wr(cout_data_wr),
.cout_ready(cout_ready)
);
defparam
	transmitter.LMID = 8;


endmodule