data/full_repos/permissive/192147978/cs161_datapath.v
 line:30: before: ")"
1: b"%Error: data/full_repos/permissive/192147978/cs161_datapath.v:30: syntax error, unexpected ')', expecting '['\n    );\n    ^\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:33: syntax error, unexpected input\n input wire  rst ;\n ^~~~~\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:35: syntax error, unexpected output\n output reg[5:0] instr_op ;\n ^~~~~~\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:36: syntax error, unexpected output\n output reg[5:0] funct  ;  \n ^~~~~~\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:38: syntax error, unexpected input\n input wire   reg_dst  ;\n ^~~~~\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:39: syntax error, unexpected input\n input wire   branch   ;\n ^~~~~\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:40: syntax error, unexpected input\n input wire   mem_read ;\n ^~~~~\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:41: syntax error, unexpected input\n input wire   mem_to_reg ;\n ^~~~~\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:42: syntax error, unexpected input\n input wire[3:0] alu_op  ;  \n ^~~~~\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:43: syntax error, unexpected input\n input wire   mem_write ;\n ^~~~~\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:44: syntax error, unexpected input\n input wire   alu_src   ; \n ^~~~~\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:45: syntax error, unexpected input\n input wire   reg_write  ;\n ^~~~~\n%Error: data/full_repos/permissive/192147978/cs161_datapath.v:73: syntax error, unexpected always\nalways @(posedge clk)\n^~~~~~\n%Error: Exiting due to 13 error(s)\n"
module cs161_datapath(
    clk ,     
    rst ,     
    instr_op ,
    funct   , 
    reg_dst , 
    branch  , 
    mem_read , 
    mem_to_reg ,
    alu_op    , 
    mem_write  ,
    alu_src  ,  
    reg_write ,    
	 


    );

 input wire  clk ; 
 input wire  rst ;
 
 output reg[5:0] instr_op ;
 output reg[5:0] funct  ;  
 
 input wire   reg_dst  ;
 input wire   branch   ;
 input wire   mem_read ;
 input wire   mem_to_reg ;
 input wire[3:0] alu_op  ;  
 input wire   mem_write ;
 input wire   alu_src   ; 
 input wire   reg_write  ;
 



 

 



always @(posedge clk)
begin: DATAPATH
	if ((reg_dst == 1'b1) && (alu_src == 1'b0) && (mem_to_reg == 1'b0) && (reg_write == 1'b1) && (mem_read == 1'b0) && (mem_write == 1'b0) && (branch == 1'b0)) begin
		instr_op = 6'b000000;
	end else if ((reg_dst == 1'b0) && (alu_src == 1'b1) && (mem_to_reg == 1'b1) && (reg_write == 1'b1) && (mem_read == 1'b1) && (mem_write == 1'b0) && (branch == 1'b0)) begin
		instr_op = 6'b100011;
	end else if ((reg_dst == 1'bx) && (alu_src == 1'b0) && (mem_to_reg == 1'b0) && (reg_write == 1'b1) && (mem_read == 1'b0) && (mem_write == 1'b0) && (branch == 1'b0)) begin
		instr_op = 6'b101011;
	end else if ((reg_dst == 1'bx) && (alu_src == 1'b0) && (mem_to_reg == 1'bx) && (reg_write == 1'b0) && (mem_read == 1'b0) && (mem_write == 1'b0) && (branch == 1'b1)) begin
		instr_op = 6'b000100;
	end else if ((reg_dst == 1'b0) && (alu_src == 1'b1) && (mem_to_reg == 1'b0) && (reg_write == 1'b1) && (mem_read == 1'b0) && (mem_write == 1'b0) && (branch == 1'b0)) begin
		instr_op = 6'b001000;
	end
	
	case(alu_op)
		4'b0010:
			begin
				if ((instr_op) == 6'b100011 || (instr_op) == 6'b101011)  
					funct = 6'bxxxxxx;
				else if ((instr_op) == 6'b100000)
					funct = 6'b100000;
				else
					funct = 6'b000000;
			end
		4'b0110:
		begin
			if ((instr_op) == 6'b000100)
				funct = 6'bxxxxxx;
			else
				funct = 6'b100010;
		end
		4'b0000:
		begin
			funct = 6'b100100;
		end
		4'b0001:
		begin
			funct = 6'b100101;
		end
		4'b1100:
		begin
			funct = 6'b100111;
		end
		4'b0111:
		begin
			funct = 6'b101010;
		end
		default: $display("default");
	endcase
end



endmodule
module cs161_datapath(
    clk ,     
    rst ,     
    instr_op ,
    funct   , 
    reg_dst , 
    branch  , 
    mem_read , 
    mem_to_reg ,
    alu_op    , 
    mem_write  ,
    alu_src  ,  
    reg_write ,    
	 


    );


 input wire  clk ; 
 input wire  rst ;
 
 output reg[5:0] instr_op ;
 output reg[5:0] funct  ;  
 
 input wire   reg_dst  ;
 input wire   branch   ;
 input wire   mem_read ;
 input wire   mem_to_reg ;
 input wire[3:0] alu_op  ;  
 input wire   mem_write ;
 input wire   alu_src   ; 
 input wire   reg_write  ;
 



 

 



always @(posedge clk)
begin: DATAPATH
	if ((reg_dst == 1'b1) && (alu_src == 1'b0) && (mem_to_reg == 1'b0) && (reg_write == 1'b1) && (mem_read == 1'b0) && (mem_write == 1'b0) && (branch == 1'b0)) begin
		instr_op = 6'b000000;
	end else if ((reg_dst == 1'b0) && (alu_src == 1'b1) && (mem_to_reg == 1'b1) && (reg_write == 1'b1) && (mem_read == 1'b1) && (mem_write == 1'b0) && (branch == 1'b0)) begin
		instr_op = 6'b100011;
	end else if ((reg_dst == 1'bx) && (alu_src == 1'b0) && (mem_to_reg == 1'b0) && (reg_write == 1'b1) && (mem_read == 1'b0) && (mem_write == 1'b0) && (branch == 1'b0)) begin
		instr_op = 6'b101011;
	end else if ((reg_dst == 1'bx) && (alu_src == 1'b0) && (mem_to_reg == 1'bx) && (reg_write == 1'b0) && (mem_read == 1'b0) && (mem_write == 1'b0) && (branch == 1'b1)) begin
		instr_op = 6'b000100;
	end else if ((reg_dst == 1'b0) && (alu_src == 1'b1) && (mem_to_reg == 1'b0) && (reg_write == 1'b1) && (mem_read == 1'b0) && (mem_write == 1'b0) && (branch == 1'b0)) begin
		instr_op = 6'b001000;
	end
	
	case(alu_op)
		4'b0010:
			begin
				if ((instr_op) == 6'b100011 || (instr_op) == 6'b101011)  
					funct = 6'bxxxxxx;
				else if ((instr_op) == 6'b100000)
					funct = 6'b100000;
				else
					funct = 6'b000000;
			end
		4'b0110:
		begin
			if ((instr_op) == 6'b000100)
				funct = 6'bxxxxxx;
			else
				funct = 6'b100010;
		end
		4'b0000:
		begin
			funct = 6'b100100;
		end
		4'b0001:
		begin
			funct = 6'b100101;
		end
		4'b1100:
		begin
			funct = 6'b100111;
		end
		4'b0111:
		begin
			funct = 6'b101010;
		end
		default: $display("default");
	endcase
end



endmodule