data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v
 line:79: before: ";"
1: b'%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:148: Cannot find include file: clogb2.vh\n`include "clogb2.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming,data/full_repos/permissive/197252258/clogb2.vh\n             data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming,data/full_repos/permissive/197252258/clogb2.vh.v\n             data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming,data/full_repos/permissive/197252258/clogb2.vh.sv\n             clogb2.vh\n             clogb2.vh.v\n             clogb2.vh.sv\n             obj_dir/clogb2.vh\n             obj_dir/clogb2.vh.v\n             obj_dir/clogb2.vh.sv\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:5: Define or directive not defined: \'`PKT_TYPE_W\'\n    input   [`PKT_TYPE_W-1:0]       pkt_type_in,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:6: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   cumulative_ack_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:7: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   selective_ack_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:8: Define or directive not defined: \'`TX_CNT_W\'\n    input   [`TX_CNT_W-1:0]         sack_tx_id_in,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:11: Define or directive not defined: \'`FLOW_WIN_SIZE\'\n    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:12: Define or directive not defined: \'`FLOW_WIN_IND_W\'\n    input   [`FLOW_WIN_IND_W-1:0]   wnd_start_ind_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:13: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:14: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\n    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:18: Define or directive not defined: \'`FLAG_W\'\n    output  [`FLAG_W-1:0]           valid_selective_ack,\n             ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:19: Define or directive not defined: \'`FLOW_WIN_IND_W\'\n    output  [`FLOW_WIN_IND_W-1:0]   new_c_acks_cnt,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:23: Define or directive not defined: \'`FLOW_WIN_SIZE\'\n    output  [`FLOW_WIN_SIZE-1:0]    acked_wnd_out,\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:24: Define or directive not defined: \'`FLOW_WIN_IND_W\'\n    output  [`FLOW_WIN_IND_W-1:0]   wnd_start_ind_out,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:25: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    output  [`FLOW_SEQ_NUM_W-1:0]   wnd_start_out\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:28: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nlocalparam  R_FLOW_WIN_IND_W = `FLOW_WIN_IND_W - 1;\n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:34: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\nwire    [`FLOW_SEQ_NUM_W-1:0]                       selective_ack_ind_tmp;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:35: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-2:0]                       selective_ack_ind;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:37: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       end_of_wnd_ind_tmp;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:38: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       end_of_wnd_ind;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:41: Define or directive not defined: \'`FLOW_WIN_SIZE\'\nwire    [`FLOW_WIN_SIZE-1:0]                        wnd_mask;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:43: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_start_1;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:44: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_end_1;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:47: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_start_2;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:48: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_end_2;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:51: Define or directive not defined: \'`FLOW_WIN_SIZE\'\nwire    [`FLOW_WIN_SIZE-1:0]                        nwack_wnd_mask;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:52: Define or directive not defined: \'`FLOW_WIN_SIZE\'\nwire    [`FLOW_WIN_SIZE-1:0]                        nwack_wnd;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:55: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_start_1;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:56: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_end_1;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:59: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_start_2;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:60: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_end_2;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:72: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\nwire   [`FLOW_SEQ_NUM_W-1:0]    wnd_start_ind_out_tmp;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:79: Define or directive not defined: \'`FLOW_WIN_SIZE\'\nassign wnd_range_end_1 = (end_of_wnd_ind >= wnd_start_ind_out) ? end_of_wnd_ind : `FLOW_WIN_SIZE;\n                                                                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign wnd_range_end_1 = (end_of_wnd_ind >= wnd_start_ind_out) ? end_of_wnd_ind : `FLOW_WIN_SIZE;\n                                                                                                ^\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:97: Define or directive not defined: \'`FLOW_WIN_SIZE\'\nfor (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_wnd_mask\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:97: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nfor (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_wnd_mask\n                              ^\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:105: Define or directive not defined: \'`FLOW_WIN_SIZE\'\nfor (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_ack\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:114: Define or directive not defined: \'`FLOW_WIN_SIZE\'\nassign nwack_wnd_range_end_1 = (wnd_start_ind_out >= wnd_start_ind_in) ? wnd_start_ind_out : `FLOW_WIN_SIZE;\n                                                                                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:114: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign nwack_wnd_range_end_1 = (wnd_start_ind_out >= wnd_start_ind_in) ? wnd_start_ind_out : `FLOW_WIN_SIZE;\n                                                                                                           ^\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:121: syntax error, unexpected generate\ngenerate\n^~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:122: Define or directive not defined: \'`FLOW_WIN_SIZE\'\nfor (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_nwack_wnd_mask\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:131: Define or directive not defined: \'`FLOW_WIN_SIZE\'\nfor (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_nwack_wnd\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:138: Define or directive not defined: \'`FLOW_WIN_SIZE\'\n    .VECT_WIDTH         (`FLOW_WIN_SIZE     ),\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_0.v:139: Define or directive not defined: \'`FLOW_WIN_IND_W\'\n    .VECT_IND_WIDTH     (`FLOW_WIN_IND_W    )\n                         ^~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module dd_incoming_0 (

    input   [`PKT_TYPE_W-1:0]       pkt_type_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   cumulative_ack_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   selective_ack_in,
    input   [`TX_CNT_W-1:0]         sack_tx_id_in,


    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,
    input   [`FLOW_WIN_IND_W-1:0]   wnd_start_ind_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,
    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,



    output  [`FLAG_W-1:0]           valid_selective_ack,
    output  [`FLOW_WIN_IND_W-1:0]   new_c_acks_cnt,


    
    output  [`FLOW_WIN_SIZE-1:0]    acked_wnd_out,
    output  [`FLOW_WIN_IND_W-1:0]   wnd_start_ind_out,
    output  [`FLOW_SEQ_NUM_W-1:0]   wnd_start_out
);

localparam  R_FLOW_WIN_IND_W = `FLOW_WIN_IND_W - 1;





wire    [`FLOW_SEQ_NUM_W-1:0]                       selective_ack_ind_tmp;
wire    [`FLOW_WIN_IND_W-2:0]                       selective_ack_ind;

wire    [`FLOW_WIN_IND_W-1:0]                       end_of_wnd_ind_tmp;
wire    [`FLOW_WIN_IND_W-1:0]                       end_of_wnd_ind;


wire    [`FLOW_WIN_SIZE-1:0]                        wnd_mask;
wire                                                wnd_range_val_1;
wire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_start_1;
wire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_end_1;

wire                                                wnd_range_val_2;
wire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_start_2;
wire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_end_2;


wire    [`FLOW_WIN_SIZE-1:0]                        nwack_wnd_mask;
wire    [`FLOW_WIN_SIZE-1:0]                        nwack_wnd;

wire                                                nwack_wnd_range_val_1;
wire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_start_1;
wire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_end_1;

wire                                                nwack_wnd_range_val_2;
wire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_start_2;
wire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_end_2;





assign end_of_wnd_ind_tmp = wnd_start_ind_out + wnd_size_in;
assign end_of_wnd_ind = {1'b0, end_of_wnd_ind_tmp[R_FLOW_WIN_IND_W-1:0]};


assign wnd_start_out = (cumulative_ack_in > wnd_start_in) ? cumulative_ack_in : wnd_start_in;

wire   [`FLOW_SEQ_NUM_W-1:0]    wnd_start_ind_out_tmp;
assign wnd_start_ind_out_tmp = wnd_start_ind_in + wnd_start_out - wnd_start_in;
assign wnd_start_ind_out = {1'b0, wnd_start_ind_out_tmp[R_FLOW_WIN_IND_W-1:0]};


assign wnd_range_val_1 = 1'b1;
assign wnd_range_start_1 = wnd_start_ind_out;
assign wnd_range_end_1 = (end_of_wnd_ind >= wnd_start_ind_out) ? end_of_wnd_ind : `FLOW_WIN_SIZE;

assign wnd_range_val_2 = end_of_wnd_ind < wnd_start_ind_out;
assign wnd_range_start_2 = {(R_FLOW_WIN_IND_W+1){1'b0}};
assign wnd_range_end_2 = end_of_wnd_ind;


assign selective_ack_ind_tmp = selective_ack_in - wnd_start_in + wnd_start_ind_in;
assign selective_ack_ind = selective_ack_ind_tmp[R_FLOW_WIN_IND_W-1:0];

assign valid_selective_ack = ~acked_wnd_in[selective_ack_ind] & 
                             selective_ack_in > wnd_start_out &
                             (selective_ack_in < wnd_start_out + wnd_size_in);

genvar i;


generate
for (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_wnd_mask
    assign wnd_mask[i] = (wnd_range_val_1 & (i >= wnd_range_start_1) & (i < wnd_range_end_1)) |
                             (wnd_range_val_2 & (i >= wnd_range_start_2) & (i < wnd_range_end_2)) ;
end
endgenerate


generate
for (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_ack
    assign acked_wnd_out[i] = wnd_mask[i] & ~nwack_wnd_mask[i] &
                              (((i == selective_ack_ind) & valid_selective_ack) ? 1'b1 : acked_wnd_in[i]);
end
endgenerate


assign nwack_wnd_range_val_1 = 1'b1;
assign nwack_wnd_range_start_1 = wnd_start_ind_in;
assign nwack_wnd_range_end_1 = (wnd_start_ind_out >= wnd_start_ind_in) ? wnd_start_ind_out : `FLOW_WIN_SIZE;

assign nwack_wnd_range_val_2 = wnd_start_ind_out < wnd_start_ind_in;
assign nwack_wnd_range_start_2 = {(R_FLOW_WIN_IND_W+1){1'b0}};
assign nwack_wnd_range_end_2 = wnd_start_ind_out;


generate
for (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_nwack_wnd_mask
    assign nwack_wnd_mask[i] = (nwack_wnd_range_val_1 & (i >= nwack_wnd_range_start_1) & (i < nwack_wnd_range_end_1)) |
                          (nwack_wnd_range_val_2 & (i >= nwack_wnd_range_start_2) & (i < nwack_wnd_range_end_2)); 
end
endgenerate



generate
for (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_nwack_wnd
    assign nwack_wnd[i] = ~acked_wnd_in[i] & nwack_wnd_mask[i];
end
endgenerate


cnt_wnd  #(
    .VECT_WIDTH         (`FLOW_WIN_SIZE     ),
    .VECT_IND_WIDTH     (`FLOW_WIN_IND_W    )
) 
cnt_wnd (
    .vect_in            (nwack_wnd          ),
    .select_set_in      (1'b1               ),
    .cnt_out            (new_c_acks_cnt     )
);


`include "clogb2.vh"
endmodule
module dd_incoming_0 (

    input   [`PKT_TYPE_W-1:0]       pkt_type_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   cumulative_ack_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   selective_ack_in,
    input   [`TX_CNT_W-1:0]         sack_tx_id_in,


    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,
    input   [`FLOW_WIN_IND_W-1:0]   wnd_start_ind_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,
    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,



    output  [`FLAG_W-1:0]           valid_selective_ack,
    output  [`FLOW_WIN_IND_W-1:0]   new_c_acks_cnt,


    
    output  [`FLOW_WIN_SIZE-1:0]    acked_wnd_out,
    output  [`FLOW_WIN_IND_W-1:0]   wnd_start_ind_out,
    output  [`FLOW_SEQ_NUM_W-1:0]   wnd_start_out
);


localparam  R_FLOW_WIN_IND_W = `FLOW_WIN_IND_W - 1;





wire    [`FLOW_SEQ_NUM_W-1:0]                       selective_ack_ind_tmp;
wire    [`FLOW_WIN_IND_W-2:0]                       selective_ack_ind;

wire    [`FLOW_WIN_IND_W-1:0]                       end_of_wnd_ind_tmp;
wire    [`FLOW_WIN_IND_W-1:0]                       end_of_wnd_ind;


wire    [`FLOW_WIN_SIZE-1:0]                        wnd_mask;
wire                                                wnd_range_val_1;
wire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_start_1;
wire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_end_1;

wire                                                wnd_range_val_2;
wire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_start_2;
wire    [`FLOW_WIN_IND_W-1:0]                       wnd_range_end_2;


wire    [`FLOW_WIN_SIZE-1:0]                        nwack_wnd_mask;
wire    [`FLOW_WIN_SIZE-1:0]                        nwack_wnd;

wire                                                nwack_wnd_range_val_1;
wire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_start_1;
wire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_end_1;

wire                                                nwack_wnd_range_val_2;
wire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_start_2;
wire    [`FLOW_WIN_IND_W-1:0]                       nwack_wnd_range_end_2;





assign end_of_wnd_ind_tmp = wnd_start_ind_out + wnd_size_in;
assign end_of_wnd_ind = {1'b0, end_of_wnd_ind_tmp[R_FLOW_WIN_IND_W-1:0]};


assign wnd_start_out = (cumulative_ack_in > wnd_start_in) ? cumulative_ack_in : wnd_start_in;

wire   [`FLOW_SEQ_NUM_W-1:0]    wnd_start_ind_out_tmp;
assign wnd_start_ind_out_tmp = wnd_start_ind_in + wnd_start_out - wnd_start_in;
assign wnd_start_ind_out = {1'b0, wnd_start_ind_out_tmp[R_FLOW_WIN_IND_W-1:0]};


assign wnd_range_val_1 = 1'b1;
assign wnd_range_start_1 = wnd_start_ind_out;
assign wnd_range_end_1 = (end_of_wnd_ind >= wnd_start_ind_out) ? end_of_wnd_ind : `FLOW_WIN_SIZE;

assign wnd_range_val_2 = end_of_wnd_ind < wnd_start_ind_out;
assign wnd_range_start_2 = {(R_FLOW_WIN_IND_W+1){1'b0}};
assign wnd_range_end_2 = end_of_wnd_ind;


assign selective_ack_ind_tmp = selective_ack_in - wnd_start_in + wnd_start_ind_in;
assign selective_ack_ind = selective_ack_ind_tmp[R_FLOW_WIN_IND_W-1:0];

assign valid_selective_ack = ~acked_wnd_in[selective_ack_ind] & 
                             selective_ack_in > wnd_start_out &
                             (selective_ack_in < wnd_start_out + wnd_size_in);

genvar i;


generate
for (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_wnd_mask
    assign wnd_mask[i] = (wnd_range_val_1 & (i >= wnd_range_start_1) & (i < wnd_range_end_1)) |
                             (wnd_range_val_2 & (i >= wnd_range_start_2) & (i < wnd_range_end_2)) ;
end
endgenerate


generate
for (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_ack
    assign acked_wnd_out[i] = wnd_mask[i] & ~nwack_wnd_mask[i] &
                              (((i == selective_ack_ind) & valid_selective_ack) ? 1'b1 : acked_wnd_in[i]);
end
endgenerate


assign nwack_wnd_range_val_1 = 1'b1;
assign nwack_wnd_range_start_1 = wnd_start_ind_in;
assign nwack_wnd_range_end_1 = (wnd_start_ind_out >= wnd_start_ind_in) ? wnd_start_ind_out : `FLOW_WIN_SIZE;

assign nwack_wnd_range_val_2 = wnd_start_ind_out < wnd_start_ind_in;
assign nwack_wnd_range_start_2 = {(R_FLOW_WIN_IND_W+1){1'b0}};
assign nwack_wnd_range_end_2 = wnd_start_ind_out;


generate
for (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_nwack_wnd_mask
    assign nwack_wnd_mask[i] = (nwack_wnd_range_val_1 & (i >= nwack_wnd_range_start_1) & (i < nwack_wnd_range_end_1)) |
                          (nwack_wnd_range_val_2 & (i >= nwack_wnd_range_start_2) & (i < nwack_wnd_range_end_2)); 
end
endgenerate



generate
for (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_nwack_wnd
    assign nwack_wnd[i] = ~acked_wnd_in[i] & nwack_wnd_mask[i];
end
endgenerate


cnt_wnd  #(
    .VECT_WIDTH         (`FLOW_WIN_SIZE     ),
    .VECT_IND_WIDTH     (`FLOW_WIN_IND_W    )
) 
cnt_wnd (
    .vect_in            (nwack_wnd          ),
    .select_set_in      (1'b1               ),
    .cnt_out            (new_c_acks_cnt     )
);


`include "clogb2.vh"
endmodule