data/full_repos/permissive/123984156/softmax_tb.v
 line:40: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/123984156/softmax_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123984156/softmax_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/123984156/softmax_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #2\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/123984156/softmax_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #2\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/123984156/softmax_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #2000 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/123984156/softmax_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n#1 Clock = ~Clock;\n^\n%Error: data/full_repos/permissive/123984156/softmax_tb.v:21: Cannot find file containing module: \'softmax\'\n softmax DUT (Clock, Reset, Start, Datain,N, Dataout);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123984156,data/full_repos/permissive/123984156/softmax\n             data/full_repos/permissive/123984156,data/full_repos/permissive/123984156/softmax.v\n             data/full_repos/permissive/123984156,data/full_repos/permissive/123984156/softmax.sv\n             softmax\n             softmax.v\n             softmax.sv\n             obj_dir/softmax\n             obj_dir/softmax.v\n             obj_dir/softmax.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module softmax_tb(
		);
reg 						Clock;
reg 						Reset;
reg 						Start;
reg [`DATALENGTH-1:0] 	Datain;
reg	[`INPUTMAX-1:0]		N;
wire [`DATALENGTH-1:0] Dataout;



	softmax DUT (Clock, Reset, Start, Datain,N, Dataout);
	
initial begin
	Clock = 1;
	Reset = 1;
	N   = 3;
	#10
	Start = 1;
	Reset = 0;
	Datain = 32'h3f800000;
	#2
	Datain = 32'h3f800000;
    #2
    Datain = 32'h3f800000;            
    #2
    Datain = 32'h3f800000;          
	
	Start = 0;
	#2000 
	$finish;
end

always 
#1 Clock = ~Clock;

endmodule
module softmax_tb(
		);

reg 						Clock;
reg 						Reset;
reg 						Start;
reg [`DATALENGTH-1:0] 	Datain;
reg	[`INPUTMAX-1:0]		N;
wire [`DATALENGTH-1:0] Dataout;



	softmax DUT (Clock, Reset, Start, Datain,N, Dataout);
	
initial begin
	Clock = 1;
	Reset = 1;
	N   = 3;
	#10
	Start = 1;
	Reset = 0;
	Datain = 32'h3f800000;
	#2
	Datain = 32'h3f800000;
    #2
    Datain = 32'h3f800000;            
    #2
    Datain = 32'h3f800000;          
	
	Start = 0;
	#2000 
	$finish;
end

always 
#1 Clock = ~Clock;

endmodule