data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv
 line:51: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:47: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk <= ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:51: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:53: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:56: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:61: syntax error, unexpected \'@\'\n  while (~d_write) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:62: syntax error, unexpected \'@\'\n  repeat (3) @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:64: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:75: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:78: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:83: syntax error, unexpected \'@\'\n  while (!mem_done) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:86: syntax error, unexpected \'@\'\n  repeat(2) @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:88: Too many digits for 32 bit number: \'hdaedbeefdeadbeef\n  mem_writedata <= \'hdaedbeefdeadbeef;\n                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117436613/testbench/bus_adapter_test.sv:91: syntax error, unexpected \'@\'\n  while (!mem_done) @(posedge clk);\n                    ^\n%Error: Exiting due to 12 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bus_adapter_test();

	reg    clk = 0;
	reg    reset_n;

	reg [63:0]	mem_address;
	reg [1:0]   mem_datasize;
	logic	mem_read;
	wire [63:0]	mem_readdata;
	logic	mem_write;
	logic [63:0]	mem_writedata;
	wire	mem_done;

	wire [27:0]	d_address;
	wire [7:0]	d_byteenable;
	wire	d_read;
	reg [63:0]	d_readdata;
	reg	d_waitrequest;
	wire	d_write;
	wire [63:0]	d_writedata;
	reg	d_readdatavalid;

	bus_adapter i0 (
		.clk		(clk),
		.reset_n	(reset_n),

		.mem_address	(mem_address),
		.mem_datasize	(mem_datasize),
		.mem_read	(mem_read),
		.mem_readdata	(mem_readdata),
		.mem_write	(mem_write),
		.mem_writedata	(mem_writedata),
		.mem_done	(mem_done),
	
		.d_address	(d_address),
		.d_byteenable	(d_byteenable),
		.d_read		(d_read),
		.d_readdata	(d_readdata),
		.d_waitrequest	(d_waitrequest),
		.d_write	(d_write),
		.d_writedata	(d_writedata),
		.d_readdatavalid	(d_readdatavalid)
	);

	always #10 clk <= ~clk;

	always @(posedge d_read) begin
		d_waitrequest <= 1;
		repeat (2) @(posedge clk);
		d_waitrequest <= 0;
		@(posedge clk);
		d_readdata <= 64'h0102030405060708;
		d_readdatavalid <= 1;
		@(posedge clk);
		d_readdata <= 64'bz;
		d_readdatavalid <= 0;
		d_waitrequest <= 1;
		
		while (~d_write) @(posedge clk);
		repeat (3) @(posedge clk);
		d_waitrequest <= 0;
		@(posedge clk);
		d_waitrequest <= 1;
		
	end
	
	initial begin
		reset_n <= 0;
		mem_read <= 0;
		mem_write <= 0;
		d_waitrequest <= 0;
		d_readdatavalid <= 0;
		repeat (2) @(posedge clk);
		reset_n <= 1;
		
		repeat (2) @(posedge clk);
		mem_address <= 64'h0123456789abcdef;
		mem_datasize <= 3;
		mem_read <= 1;
		
		while (!mem_done) @(posedge clk);
		mem_read <= 0;
		
		repeat(2) @(posedge clk);
		mem_datasize <= 2;
		mem_writedata <= 'hdaedbeefdeadbeef;
		mem_write <= 1;
		
		while (!mem_done) @(posedge clk);
		mem_write <= 0;
		
	end

endmodule
module bus_adapter_test();


	reg    clk = 0;
	reg    reset_n;

	reg [63:0]	mem_address;
	reg [1:0]   mem_datasize;
	logic	mem_read;
	wire [63:0]	mem_readdata;
	logic	mem_write;
	logic [63:0]	mem_writedata;
	wire	mem_done;

	wire [27:0]	d_address;
	wire [7:0]	d_byteenable;
	wire	d_read;
	reg [63:0]	d_readdata;
	reg	d_waitrequest;
	wire	d_write;
	wire [63:0]	d_writedata;
	reg	d_readdatavalid;

	bus_adapter i0 (
		.clk		(clk),
		.reset_n	(reset_n),

		.mem_address	(mem_address),
		.mem_datasize	(mem_datasize),
		.mem_read	(mem_read),
		.mem_readdata	(mem_readdata),
		.mem_write	(mem_write),
		.mem_writedata	(mem_writedata),
		.mem_done	(mem_done),
	
		.d_address	(d_address),
		.d_byteenable	(d_byteenable),
		.d_read		(d_read),
		.d_readdata	(d_readdata),
		.d_waitrequest	(d_waitrequest),
		.d_write	(d_write),
		.d_writedata	(d_writedata),
		.d_readdatavalid	(d_readdatavalid)
	);

	always #10 clk <= ~clk;

	always @(posedge d_read) begin
		d_waitrequest <= 1;
		repeat (2) @(posedge clk);
		d_waitrequest <= 0;
		@(posedge clk);
		d_readdata <= 64'h0102030405060708;
		d_readdatavalid <= 1;
		@(posedge clk);
		d_readdata <= 64'bz;
		d_readdatavalid <= 0;
		d_waitrequest <= 1;
		
		while (~d_write) @(posedge clk);
		repeat (3) @(posedge clk);
		d_waitrequest <= 0;
		@(posedge clk);
		d_waitrequest <= 1;
		
	end
	
	initial begin
		reset_n <= 0;
		mem_read <= 0;
		mem_write <= 0;
		d_waitrequest <= 0;
		d_readdatavalid <= 0;
		repeat (2) @(posedge clk);
		reset_n <= 1;
		
		repeat (2) @(posedge clk);
		mem_address <= 64'h0123456789abcdef;
		mem_datasize <= 3;
		mem_read <= 1;
		
		while (!mem_done) @(posedge clk);
		mem_read <= 0;
		
		repeat(2) @(posedge clk);
		mem_datasize <= 2;
		mem_writedata <= 'hdaedbeefdeadbeef;
		mem_write <= 1;
		
		while (!mem_done) @(posedge clk);
		mem_write <= 0;
		
	end

endmodule