data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/pat_gen.v
1: b"%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/pat_gen.v:124: Cannot find file containing module: 'pat_gen_ctrl'\npat_gen_ctrl #( \n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1,data/full_repos/permissive/165823960/pat_gen_ctrl\n             data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1,data/full_repos/permissive/165823960/pat_gen_ctrl.v\n             data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1,data/full_repos/permissive/165823960/pat_gen_ctrl.sv\n             pat_gen_ctrl\n             pat_gen_ctrl.v\n             pat_gen_ctrl.sv\n             obj_dir/pat_gen_ctrl\n             obj_dir/pat_gen_ctrl.v\n             obj_dir/pat_gen_ctrl.sv\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/pat_gen.v:196: Cannot find file containing module: 'pat_gen_ext'\npat_gen_ext  #( \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/pat_gen.v:233: Cannot find file containing module: 'pat_gen_int'\npat_gen_int  #( \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/pat_gen.v:264: Cannot find file containing module: 'ser_div'\nser_div      #( \n^~~~~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/pat_gen.v:281: Cannot find file containing module: 'ser_div'\nser_div      #( \n^~~~~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/pat_gen.v:299: Cannot find file containing module: 'ser_div'\nser_div      #( \n^~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module pat_gen(

   pat_gen_data, pat_gen_data_vld,

   clk, rst_n, det_vld, hs_en, vs_en, fnl_de_en, hs_pol, vs_pol,
   fnl_de_pol, actv_wd, actv_ht, pseudo_vs, pseudo_vs_actv_trig,
   hs_actv_trig, vs_actv_trig, de_actv_trig, de_idle_trig, lvds_data,
   sync_en, bist_en, pat_gen_en, map_sel, pat_gen_mode,
   pat_gen_col_bar_en, pat_gen_rvs_vcom_en, pat_gen_chkbd_sc,
   pat_gen_cus_col_en, pat_gen_18bit, pat_gen_ext_clk_src,
   pat_gen_int_tmg, pat_gen_rvs_col_en, pat_gen_auto_scrl_en,
   int_reg_data, bist_clk_src, pat_gen_int_clk_en
   );


parameter DSIZE = 28; 
parameter WD_SIZE = 12; 
parameter HT_SIZE = 12; 
localparam DIV_M = 16;
localparam DIV_N = 12;
localparam DIV_R = 0;
localparam DIV_S = 0;
localparam DIV_C = 5;
localparam Q_SIZE = (DIV_M+DIV_R-DIV_S);
localparam SYNC_N = 5;

input                        clk;
input                        rst_n;

input                        det_vld;
input                        hs_en;
input                        vs_en;
input                        fnl_de_en;
input                        hs_pol;
input                        vs_pol;
input                        fnl_de_pol;
input  [WD_SIZE-1:0]         actv_wd;
input  [HT_SIZE-1:0]         actv_ht;
input                        pseudo_vs;
input                        pseudo_vs_actv_trig;
input                        hs_actv_trig;
input                        vs_actv_trig;
input                        de_actv_trig;
input                        de_idle_trig;
input  [DSIZE-1:0]           lvds_data;

input                        sync_en;
input                        bist_en;
input                        pat_gen_en;
input                        map_sel;
input  [3:0]                 pat_gen_mode;
input                        pat_gen_col_bar_en;
input                        pat_gen_rvs_vcom_en;
input                        pat_gen_chkbd_sc;
input                        pat_gen_cus_col_en;
input                        pat_gen_18bit;
input                        pat_gen_ext_clk_src;
input                        pat_gen_int_tmg;
input                        pat_gen_rvs_col_en;
input                        pat_gen_auto_scrl_en;
input  [7:0]                 int_reg_data[24:0];
input  [1:0]                 bist_clk_src;
input                        pat_gen_int_clk_en;

output [DSIZE-1:0]           pat_gen_data;
output                       pat_gen_data_vld;








wire			cal_trig;
wire [WD_SIZE-1:0]	divisor_0;
wire [HT_SIZE-1:0]	divisor_1;
wire [WD_SIZE-1:0]	divisor_2;
wire [WD_SIZE-1:0]	ext_actv_x_pos;
wire [HT_SIZE-1:0]	ext_actv_y_pos;
wire			ext_cal_trig;
wire [3:0]		ext_scrl_mode;
wire			ext_work;
wire			ext_work_trig;
wire [1:0]		ext_x_zone;
wire [1:0]		ext_y_zone;
wire [WD_SIZE-1:0]	int_actv_x_pos;
wire [HT_SIZE-1:0]	int_actv_y_pos;
wire			int_cal_trig;
wire [3:0]		int_scrl_mode;
wire			int_work;
wire			int_work_trig;
wire [1:0]		int_x_zone;
wire [1:0]		int_y_zone;
wire [HT_SIZE-1:0]	pat_gen_actv_ht;
wire [WD_SIZE-1:0]	pat_gen_actv_wd;
wire [7:0]		pat_gen_frms_per_pat;
wire [7:0]		pat_gen_hbp_wd;
wire [7:0]		pat_gen_hs_wd;
wire [3:0]		pat_gen_slt_num;
wire [3:0]		pat_gen_slt_pat_num [15:0];
wire [HT_SIZE-1:0]	pat_gen_tot_ht;
wire [WD_SIZE-1:0]	pat_gen_tot_wd;
wire [7:0]		pat_gen_vbp_wd;
wire [7:0]		pat_gen_vs_wd;
wire [DIV_M+DIV_R-DIV_S-1:0] quotient_0;
wire [DIV_M+DIV_R-DIV_S-1:0] quotient_1;
wire [DIV_M+DIV_R-DIV_S-1:0] quotient_2;
wire			sync_pat_gen_auto_scrl_en;
wire			sync_pat_gen_en;
wire			sync_pat_gen_en_ack;
wire			sync_pat_gen_int_tmg;




pat_gen_ctrl #(

	       .DSIZE			(DSIZE),
	       .WD_SIZE			(WD_SIZE),
	       .HT_SIZE			(HT_SIZE),
	       .Q_SIZE			(Q_SIZE)) U_PAT_GEN_CTRL(

								 .pat_gen_data		(pat_gen_data[DSIZE-1:0]),
								 .pat_gen_data_vld	(pat_gen_data_vld),
								 .cal_trig		(cal_trig),
								 .divisor_0		(divisor_0[WD_SIZE-1:0]),
								 .divisor_1		(divisor_1[HT_SIZE-1:0]),
								 .divisor_2		(divisor_2[WD_SIZE-1:0]),
								 .sync_pat_gen_en	(sync_pat_gen_en),
								 .sync_pat_gen_en_ack	(sync_pat_gen_en_ack),
								 .sync_pat_gen_int_tmg	(sync_pat_gen_int_tmg),
								 .sync_pat_gen_auto_scrl_en(sync_pat_gen_auto_scrl_en),
								 .pat_gen_tot_wd	(pat_gen_tot_wd[WD_SIZE-1:0]),
								 .pat_gen_tot_ht	(pat_gen_tot_ht[HT_SIZE-1:0]),
								 .pat_gen_actv_wd	(pat_gen_actv_wd[WD_SIZE-1:0]),
								 .pat_gen_actv_ht	(pat_gen_actv_ht[HT_SIZE-1:0]),
								 .pat_gen_hs_wd		(pat_gen_hs_wd[7:0]),
								 .pat_gen_vs_wd		(pat_gen_vs_wd[7:0]),
								 .pat_gen_hbp_wd	(pat_gen_hbp_wd[7:0]),
								 .pat_gen_vbp_wd	(pat_gen_vbp_wd[7:0]),
								 .pat_gen_frms_per_pat	(pat_gen_frms_per_pat[7:0]),
								 .pat_gen_slt_num	(pat_gen_slt_num[3:0]),
								 .pat_gen_slt_pat_num	(pat_gen_slt_pat_num),

								 .clk			(clk),
								 .rst_n			(rst_n),
								 .hs_pol		(hs_pol),
								 .vs_pol		(vs_pol),
								 .fnl_de_pol		(fnl_de_pol),
								 .fnl_de_en		(fnl_de_en),
								 .actv_wd		(actv_wd[WD_SIZE-1:0]),
								 .actv_ht		(actv_ht[HT_SIZE-1:0]),
								 .lvds_data		(lvds_data[DSIZE-1:0]),
								 .ext_x_zone		(ext_x_zone[1:0]),
								 .ext_y_zone		(ext_y_zone[1:0]),
								 .ext_actv_x_pos	(ext_actv_x_pos[WD_SIZE-1:0]),
								 .ext_actv_y_pos	(ext_actv_y_pos[HT_SIZE-1:0]),
								 .ext_scrl_mode		(ext_scrl_mode[3:0]),
								 .ext_cal_trig		(ext_cal_trig),
								 .ext_work_trig		(ext_work_trig),
								 .ext_work		(ext_work),
								 .int_x_zone		(int_x_zone[1:0]),
								 .int_y_zone		(int_y_zone[1:0]),
								 .int_actv_x_pos	(int_actv_x_pos[WD_SIZE-1:0]),
								 .int_actv_y_pos	(int_actv_y_pos[HT_SIZE-1:0]),
								 .int_scrl_mode		(int_scrl_mode[3:0]),
								 .int_cal_trig		(int_cal_trig),
								 .int_work_trig		(int_work_trig),
								 .int_work		(int_work),
								 .quotient_0		(quotient_0[Q_SIZE-1:0]),
								 .quotient_1		(quotient_1[Q_SIZE-1:0]),
								 .quotient_2		(quotient_2[Q_SIZE-1:0]),
								 .sync_en		(sync_en),
								 .bist_en		(bist_en),
								 .pat_gen_en		(pat_gen_en),
								 .map_sel		(map_sel),
								 .pat_gen_mode		(pat_gen_mode[3:0]),
								 .pat_gen_col_bar_en	(pat_gen_col_bar_en),
								 .pat_gen_rvs_vcom_en	(pat_gen_rvs_vcom_en),
								 .pat_gen_chkbd_sc	(pat_gen_chkbd_sc),
								 .pat_gen_cus_col_en	(pat_gen_cus_col_en),
								 .pat_gen_18bit		(pat_gen_18bit),
								 .pat_gen_ext_clk_src	(pat_gen_ext_clk_src),
								 .pat_gen_int_tmg	(pat_gen_int_tmg),
								 .pat_gen_rvs_col_en	(pat_gen_rvs_col_en),
								 .pat_gen_auto_scrl_en	(pat_gen_auto_scrl_en),
								 .int_reg_data		(int_reg_data));
pat_gen_ext  #(

	       .WD_SIZE			(WD_SIZE),
	       .HT_SIZE			(HT_SIZE)) U_PAT_GEN_EXT(

								 .ext_x_zone		(ext_x_zone[1:0]),
								 .ext_y_zone		(ext_y_zone[1:0]),
								 .ext_actv_x_pos	(ext_actv_x_pos[WD_SIZE-1:0]),
								 .ext_actv_y_pos	(ext_actv_y_pos[HT_SIZE-1:0]),
								 .ext_cal_trig		(ext_cal_trig),
								 .ext_work_trig		(ext_work_trig),
								 .ext_work		(ext_work),
								 .ext_scrl_mode		(ext_scrl_mode[3:0]),

								 .clk			(clk),
								 .rst_n			(rst_n),
								 .det_vld		(det_vld),
								 .hs_pol		(hs_pol),
								 .hs_en			(hs_en),
								 .vs_pol		(vs_pol),
								 .vs_en			(vs_en),
								 .fnl_de_pol		(fnl_de_pol),
								 .fnl_de_en		(fnl_de_en),
								 .actv_wd		(actv_wd[WD_SIZE-1:0]),
								 .actv_ht		(actv_ht[HT_SIZE-1:0]),
								 .hs_actv_trig		(hs_actv_trig),
								 .vs_actv_trig		(vs_actv_trig),
								 .de_actv_trig		(de_actv_trig),
								 .de_idle_trig		(de_idle_trig),
								 .pseudo_vs_actv_trig	(pseudo_vs_actv_trig),
								 .sync_pat_gen_en	(sync_pat_gen_en),
								 .sync_pat_gen_en_ack	(sync_pat_gen_en_ack),
								 .sync_pat_gen_int_tmg	(sync_pat_gen_int_tmg),
								 .sync_pat_gen_auto_scrl_en(sync_pat_gen_auto_scrl_en),
								 .pat_gen_frms_per_pat	(pat_gen_frms_per_pat[7:0]),
								 .pat_gen_slt_num	(pat_gen_slt_num[3:0]),
								 .pat_gen_slt_pat_num	(pat_gen_slt_pat_num));
pat_gen_int  #(

	       .HT_SIZE			(HT_SIZE),
	       .WD_SIZE			(WD_SIZE)) U_PAT_GEN_INT(

								 .int_x_zone		(int_x_zone[1:0]),
								 .int_y_zone		(int_y_zone[1:0]),
								 .int_actv_x_pos	(int_actv_x_pos[WD_SIZE-1:0]),
								 .int_actv_y_pos	(int_actv_y_pos[HT_SIZE-1:0]),
								 .int_cal_trig		(int_cal_trig),
								 .int_work_trig		(int_work_trig),
								 .int_work		(int_work),
								 .int_scrl_mode		(int_scrl_mode[3:0]),

								 .clk			(clk),
								 .rst_n			(rst_n),
								 .sync_pat_gen_en	(sync_pat_gen_en),
								 .sync_pat_gen_en_ack	(sync_pat_gen_en_ack),
								 .sync_pat_gen_int_tmg	(sync_pat_gen_int_tmg),
								 .sync_pat_gen_auto_scrl_en(sync_pat_gen_auto_scrl_en),
								 .pat_gen_tot_wd	(pat_gen_tot_wd[WD_SIZE-1:0]),
								 .pat_gen_tot_ht	(pat_gen_tot_ht[HT_SIZE-1:0]),
								 .pat_gen_actv_wd	(pat_gen_actv_wd[WD_SIZE-1:0]),
								 .pat_gen_actv_ht	(pat_gen_actv_ht[HT_SIZE-1:0]),
								 .pat_gen_hs_wd		(pat_gen_hs_wd[7:0]),
								 .pat_gen_vs_wd		(pat_gen_vs_wd[7:0]),
								 .pat_gen_hbp_wd	(pat_gen_hbp_wd[7:0]),
								 .pat_gen_vbp_wd	(pat_gen_vbp_wd[7:0]),
								 .pat_gen_frms_per_pat	(pat_gen_frms_per_pat[7:0]),
								 .pat_gen_slt_num	(pat_gen_slt_num[3:0]),
								 .pat_gen_slt_pat_num	(pat_gen_slt_pat_num));
ser_div      #(

	       .DIV_M			(DIV_M),
	       .DIV_N			(DIV_N),
	       .DIV_R			(DIV_R),
	       .DIV_S			(DIV_S),
	       .DIV_C			(DIV_C)) U_DIV_0(
							.dividend (16'hFF00),


							 .quotient		(quotient_0[DIV_M+DIV_R-DIV_S-1:0]),
							 .div_done		({div_done_0}),

							 .clk			(clk),
							 .rst_n			(rst_n),
							 .cal_trig		(cal_trig),
							 .divisor		(divisor_0[DIV_N-1:0]));
ser_div      #(

	       .DIV_M			(DIV_M),
	       .DIV_N			(DIV_N),
	       .DIV_R			(DIV_R),
	       .DIV_S			(DIV_S),
	       .DIV_C			(DIV_C)) U_DIV_1(
							.dividend (16'hFF00),


							 .quotient		(quotient_1[DIV_M+DIV_R-DIV_S-1:0]),
							 .div_done		({div_done_1}),

							 .clk			(clk),
							 .rst_n			(rst_n),
							 .cal_trig		(cal_trig),
							 .divisor		(divisor_1[DIV_N-1:0]));

ser_div      #(

	       .DIV_M			(DIV_M),
	       .DIV_N			(DIV_N),
	       .DIV_R			(DIV_R),
	       .DIV_S			(DIV_S),
	       .DIV_C			(DIV_C)) U_DIV_2(
							.dividend (16'h7000),


							 .quotient		(quotient_2[DIV_M+DIV_R-DIV_S-1:0]),
							 .div_done		({div_done_2}),

							 .clk			(clk),
							 .rst_n			(rst_n),
							 .cal_trig		(cal_trig),
							 .divisor		(divisor_2[DIV_N-1:0]));

endmodule
module pat_gen(

   pat_gen_data, pat_gen_data_vld,

   clk, rst_n, det_vld, hs_en, vs_en, fnl_de_en, hs_pol, vs_pol,
   fnl_de_pol, actv_wd, actv_ht, pseudo_vs, pseudo_vs_actv_trig,
   hs_actv_trig, vs_actv_trig, de_actv_trig, de_idle_trig, lvds_data,
   sync_en, bist_en, pat_gen_en, map_sel, pat_gen_mode,
   pat_gen_col_bar_en, pat_gen_rvs_vcom_en, pat_gen_chkbd_sc,
   pat_gen_cus_col_en, pat_gen_18bit, pat_gen_ext_clk_src,
   pat_gen_int_tmg, pat_gen_rvs_col_en, pat_gen_auto_scrl_en,
   int_reg_data, bist_clk_src, pat_gen_int_clk_en
   );



parameter DSIZE = 28; 
parameter WD_SIZE = 12; 
parameter HT_SIZE = 12; 
localparam DIV_M = 16;
localparam DIV_N = 12;
localparam DIV_R = 0;
localparam DIV_S = 0;
localparam DIV_C = 5;
localparam Q_SIZE = (DIV_M+DIV_R-DIV_S);
localparam SYNC_N = 5;

input                        clk;
input                        rst_n;

input                        det_vld;
input                        hs_en;
input                        vs_en;
input                        fnl_de_en;
input                        hs_pol;
input                        vs_pol;
input                        fnl_de_pol;
input  [WD_SIZE-1:0]         actv_wd;
input  [HT_SIZE-1:0]         actv_ht;
input                        pseudo_vs;
input                        pseudo_vs_actv_trig;
input                        hs_actv_trig;
input                        vs_actv_trig;
input                        de_actv_trig;
input                        de_idle_trig;
input  [DSIZE-1:0]           lvds_data;

input                        sync_en;
input                        bist_en;
input                        pat_gen_en;
input                        map_sel;
input  [3:0]                 pat_gen_mode;
input                        pat_gen_col_bar_en;
input                        pat_gen_rvs_vcom_en;
input                        pat_gen_chkbd_sc;
input                        pat_gen_cus_col_en;
input                        pat_gen_18bit;
input                        pat_gen_ext_clk_src;
input                        pat_gen_int_tmg;
input                        pat_gen_rvs_col_en;
input                        pat_gen_auto_scrl_en;
input  [7:0]                 int_reg_data[24:0];
input  [1:0]                 bist_clk_src;
input                        pat_gen_int_clk_en;

output [DSIZE-1:0]           pat_gen_data;
output                       pat_gen_data_vld;








wire			cal_trig;
wire [WD_SIZE-1:0]	divisor_0;
wire [HT_SIZE-1:0]	divisor_1;
wire [WD_SIZE-1:0]	divisor_2;
wire [WD_SIZE-1:0]	ext_actv_x_pos;
wire [HT_SIZE-1:0]	ext_actv_y_pos;
wire			ext_cal_trig;
wire [3:0]		ext_scrl_mode;
wire			ext_work;
wire			ext_work_trig;
wire [1:0]		ext_x_zone;
wire [1:0]		ext_y_zone;
wire [WD_SIZE-1:0]	int_actv_x_pos;
wire [HT_SIZE-1:0]	int_actv_y_pos;
wire			int_cal_trig;
wire [3:0]		int_scrl_mode;
wire			int_work;
wire			int_work_trig;
wire [1:0]		int_x_zone;
wire [1:0]		int_y_zone;
wire [HT_SIZE-1:0]	pat_gen_actv_ht;
wire [WD_SIZE-1:0]	pat_gen_actv_wd;
wire [7:0]		pat_gen_frms_per_pat;
wire [7:0]		pat_gen_hbp_wd;
wire [7:0]		pat_gen_hs_wd;
wire [3:0]		pat_gen_slt_num;
wire [3:0]		pat_gen_slt_pat_num [15:0];
wire [HT_SIZE-1:0]	pat_gen_tot_ht;
wire [WD_SIZE-1:0]	pat_gen_tot_wd;
wire [7:0]		pat_gen_vbp_wd;
wire [7:0]		pat_gen_vs_wd;
wire [DIV_M+DIV_R-DIV_S-1:0] quotient_0;
wire [DIV_M+DIV_R-DIV_S-1:0] quotient_1;
wire [DIV_M+DIV_R-DIV_S-1:0] quotient_2;
wire			sync_pat_gen_auto_scrl_en;
wire			sync_pat_gen_en;
wire			sync_pat_gen_en_ack;
wire			sync_pat_gen_int_tmg;




pat_gen_ctrl #(

	       .DSIZE			(DSIZE),
	       .WD_SIZE			(WD_SIZE),
	       .HT_SIZE			(HT_SIZE),
	       .Q_SIZE			(Q_SIZE)) U_PAT_GEN_CTRL(

								 .pat_gen_data		(pat_gen_data[DSIZE-1:0]),
								 .pat_gen_data_vld	(pat_gen_data_vld),
								 .cal_trig		(cal_trig),
								 .divisor_0		(divisor_0[WD_SIZE-1:0]),
								 .divisor_1		(divisor_1[HT_SIZE-1:0]),
								 .divisor_2		(divisor_2[WD_SIZE-1:0]),
								 .sync_pat_gen_en	(sync_pat_gen_en),
								 .sync_pat_gen_en_ack	(sync_pat_gen_en_ack),
								 .sync_pat_gen_int_tmg	(sync_pat_gen_int_tmg),
								 .sync_pat_gen_auto_scrl_en(sync_pat_gen_auto_scrl_en),
								 .pat_gen_tot_wd	(pat_gen_tot_wd[WD_SIZE-1:0]),
								 .pat_gen_tot_ht	(pat_gen_tot_ht[HT_SIZE-1:0]),
								 .pat_gen_actv_wd	(pat_gen_actv_wd[WD_SIZE-1:0]),
								 .pat_gen_actv_ht	(pat_gen_actv_ht[HT_SIZE-1:0]),
								 .pat_gen_hs_wd		(pat_gen_hs_wd[7:0]),
								 .pat_gen_vs_wd		(pat_gen_vs_wd[7:0]),
								 .pat_gen_hbp_wd	(pat_gen_hbp_wd[7:0]),
								 .pat_gen_vbp_wd	(pat_gen_vbp_wd[7:0]),
								 .pat_gen_frms_per_pat	(pat_gen_frms_per_pat[7:0]),
								 .pat_gen_slt_num	(pat_gen_slt_num[3:0]),
								 .pat_gen_slt_pat_num	(pat_gen_slt_pat_num),

								 .clk			(clk),
								 .rst_n			(rst_n),
								 .hs_pol		(hs_pol),
								 .vs_pol		(vs_pol),
								 .fnl_de_pol		(fnl_de_pol),
								 .fnl_de_en		(fnl_de_en),
								 .actv_wd		(actv_wd[WD_SIZE-1:0]),
								 .actv_ht		(actv_ht[HT_SIZE-1:0]),
								 .lvds_data		(lvds_data[DSIZE-1:0]),
								 .ext_x_zone		(ext_x_zone[1:0]),
								 .ext_y_zone		(ext_y_zone[1:0]),
								 .ext_actv_x_pos	(ext_actv_x_pos[WD_SIZE-1:0]),
								 .ext_actv_y_pos	(ext_actv_y_pos[HT_SIZE-1:0]),
								 .ext_scrl_mode		(ext_scrl_mode[3:0]),
								 .ext_cal_trig		(ext_cal_trig),
								 .ext_work_trig		(ext_work_trig),
								 .ext_work		(ext_work),
								 .int_x_zone		(int_x_zone[1:0]),
								 .int_y_zone		(int_y_zone[1:0]),
								 .int_actv_x_pos	(int_actv_x_pos[WD_SIZE-1:0]),
								 .int_actv_y_pos	(int_actv_y_pos[HT_SIZE-1:0]),
								 .int_scrl_mode		(int_scrl_mode[3:0]),
								 .int_cal_trig		(int_cal_trig),
								 .int_work_trig		(int_work_trig),
								 .int_work		(int_work),
								 .quotient_0		(quotient_0[Q_SIZE-1:0]),
								 .quotient_1		(quotient_1[Q_SIZE-1:0]),
								 .quotient_2		(quotient_2[Q_SIZE-1:0]),
								 .sync_en		(sync_en),
								 .bist_en		(bist_en),
								 .pat_gen_en		(pat_gen_en),
								 .map_sel		(map_sel),
								 .pat_gen_mode		(pat_gen_mode[3:0]),
								 .pat_gen_col_bar_en	(pat_gen_col_bar_en),
								 .pat_gen_rvs_vcom_en	(pat_gen_rvs_vcom_en),
								 .pat_gen_chkbd_sc	(pat_gen_chkbd_sc),
								 .pat_gen_cus_col_en	(pat_gen_cus_col_en),
								 .pat_gen_18bit		(pat_gen_18bit),
								 .pat_gen_ext_clk_src	(pat_gen_ext_clk_src),
								 .pat_gen_int_tmg	(pat_gen_int_tmg),
								 .pat_gen_rvs_col_en	(pat_gen_rvs_col_en),
								 .pat_gen_auto_scrl_en	(pat_gen_auto_scrl_en),
								 .int_reg_data		(int_reg_data));
pat_gen_ext  #(

	       .WD_SIZE			(WD_SIZE),
	       .HT_SIZE			(HT_SIZE)) U_PAT_GEN_EXT(

								 .ext_x_zone		(ext_x_zone[1:0]),
								 .ext_y_zone		(ext_y_zone[1:0]),
								 .ext_actv_x_pos	(ext_actv_x_pos[WD_SIZE-1:0]),
								 .ext_actv_y_pos	(ext_actv_y_pos[HT_SIZE-1:0]),
								 .ext_cal_trig		(ext_cal_trig),
								 .ext_work_trig		(ext_work_trig),
								 .ext_work		(ext_work),
								 .ext_scrl_mode		(ext_scrl_mode[3:0]),

								 .clk			(clk),
								 .rst_n			(rst_n),
								 .det_vld		(det_vld),
								 .hs_pol		(hs_pol),
								 .hs_en			(hs_en),
								 .vs_pol		(vs_pol),
								 .vs_en			(vs_en),
								 .fnl_de_pol		(fnl_de_pol),
								 .fnl_de_en		(fnl_de_en),
								 .actv_wd		(actv_wd[WD_SIZE-1:0]),
								 .actv_ht		(actv_ht[HT_SIZE-1:0]),
								 .hs_actv_trig		(hs_actv_trig),
								 .vs_actv_trig		(vs_actv_trig),
								 .de_actv_trig		(de_actv_trig),
								 .de_idle_trig		(de_idle_trig),
								 .pseudo_vs_actv_trig	(pseudo_vs_actv_trig),
								 .sync_pat_gen_en	(sync_pat_gen_en),
								 .sync_pat_gen_en_ack	(sync_pat_gen_en_ack),
								 .sync_pat_gen_int_tmg	(sync_pat_gen_int_tmg),
								 .sync_pat_gen_auto_scrl_en(sync_pat_gen_auto_scrl_en),
								 .pat_gen_frms_per_pat	(pat_gen_frms_per_pat[7:0]),
								 .pat_gen_slt_num	(pat_gen_slt_num[3:0]),
								 .pat_gen_slt_pat_num	(pat_gen_slt_pat_num));
pat_gen_int  #(

	       .HT_SIZE			(HT_SIZE),
	       .WD_SIZE			(WD_SIZE)) U_PAT_GEN_INT(

								 .int_x_zone		(int_x_zone[1:0]),
								 .int_y_zone		(int_y_zone[1:0]),
								 .int_actv_x_pos	(int_actv_x_pos[WD_SIZE-1:0]),
								 .int_actv_y_pos	(int_actv_y_pos[HT_SIZE-1:0]),
								 .int_cal_trig		(int_cal_trig),
								 .int_work_trig		(int_work_trig),
								 .int_work		(int_work),
								 .int_scrl_mode		(int_scrl_mode[3:0]),

								 .clk			(clk),
								 .rst_n			(rst_n),
								 .sync_pat_gen_en	(sync_pat_gen_en),
								 .sync_pat_gen_en_ack	(sync_pat_gen_en_ack),
								 .sync_pat_gen_int_tmg	(sync_pat_gen_int_tmg),
								 .sync_pat_gen_auto_scrl_en(sync_pat_gen_auto_scrl_en),
								 .pat_gen_tot_wd	(pat_gen_tot_wd[WD_SIZE-1:0]),
								 .pat_gen_tot_ht	(pat_gen_tot_ht[HT_SIZE-1:0]),
								 .pat_gen_actv_wd	(pat_gen_actv_wd[WD_SIZE-1:0]),
								 .pat_gen_actv_ht	(pat_gen_actv_ht[HT_SIZE-1:0]),
								 .pat_gen_hs_wd		(pat_gen_hs_wd[7:0]),
								 .pat_gen_vs_wd		(pat_gen_vs_wd[7:0]),
								 .pat_gen_hbp_wd	(pat_gen_hbp_wd[7:0]),
								 .pat_gen_vbp_wd	(pat_gen_vbp_wd[7:0]),
								 .pat_gen_frms_per_pat	(pat_gen_frms_per_pat[7:0]),
								 .pat_gen_slt_num	(pat_gen_slt_num[3:0]),
								 .pat_gen_slt_pat_num	(pat_gen_slt_pat_num));
ser_div      #(

	       .DIV_M			(DIV_M),
	       .DIV_N			(DIV_N),
	       .DIV_R			(DIV_R),
	       .DIV_S			(DIV_S),
	       .DIV_C			(DIV_C)) U_DIV_0(
							.dividend (16'hFF00),


							 .quotient		(quotient_0[DIV_M+DIV_R-DIV_S-1:0]),
							 .div_done		({div_done_0}),

							 .clk			(clk),
							 .rst_n			(rst_n),
							 .cal_trig		(cal_trig),
							 .divisor		(divisor_0[DIV_N-1:0]));
ser_div      #(

	       .DIV_M			(DIV_M),
	       .DIV_N			(DIV_N),
	       .DIV_R			(DIV_R),
	       .DIV_S			(DIV_S),
	       .DIV_C			(DIV_C)) U_DIV_1(
							.dividend (16'hFF00),


							 .quotient		(quotient_1[DIV_M+DIV_R-DIV_S-1:0]),
							 .div_done		({div_done_1}),

							 .clk			(clk),
							 .rst_n			(rst_n),
							 .cal_trig		(cal_trig),
							 .divisor		(divisor_1[DIV_N-1:0]));

ser_div      #(

	       .DIV_M			(DIV_M),
	       .DIV_N			(DIV_N),
	       .DIV_R			(DIV_R),
	       .DIV_S			(DIV_S),
	       .DIV_C			(DIV_C)) U_DIV_2(
							.dividend (16'h7000),


							 .quotient		(quotient_2[DIV_M+DIV_R-DIV_S-1:0]),
							 .div_done		({div_done_2}),

							 .clk			(clk),
							 .rst_n			(rst_n),
							 .cal_trig		(cal_trig),
							 .divisor		(divisor_2[DIV_N-1:0]));

endmodule