data/full_repos/permissive/151958185/Mult16.v
'utf-8' codec can't decode byte 0xe5 in position 569: invalid continuation byte
1: b'%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:28: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s CONST \'15\'h0\' generates 15 bits.\n                                                                : ... In instance mult16\n   mult16x1=(sel)?(operand):15\'b0;  \n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:34: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp14=((mult16x1(a,b[1]))<<1); \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:35: Operator SHIFTL expects 18 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp13=((mult16x1(a,b[2]))<<2); \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:36: Operator SHIFTL expects 19 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp12=((mult16x1(a,b[3]))<<3); \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:37: Operator SHIFTL expects 20 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp11=((mult16x1(a,b[4]))<<4); \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:38: Operator SHIFTL expects 21 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp10=((mult16x1(a,b[5]))<<5); \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:39: Operator SHIFTL expects 22 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp9=((mult16x1(a,b[6]))<<6); \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:40: Operator SHIFTL expects 23 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp8=((mult16x1(a,b[7]))<<7); \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:41: Operator SHIFTL expects 24 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp7=((mult16x1(a,b[8]))<<8); \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:42: Operator SHIFTL expects 25 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp6=((mult16x1(a,b[9]))<<9); \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:43: Operator SHIFTL expects 26 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp5=((mult16x1(a,b[10]))<<10); \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:44: Operator SHIFTL expects 27 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp4=((mult16x1(a,b[11]))<<11); \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:45: Operator SHIFTL expects 28 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp3=((mult16x1(a,b[12]))<<12); \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:46: Operator SHIFTL expects 29 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp2=((mult16x1(a,b[13]))<<13); \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:47: Operator SHIFTL expects 30 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp1=((mult16x1(a,b[14]))<<14); \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:48: Operator SHIFTL expects 31 bits on the LHS, but LHS\'s FUNCREF \'mult16x1\' generates 16 bits.\n                                                                : ... In instance mult16\nassign temp0=((mult16x1(a,b[15]))<<15); \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp1\' generates 30 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                     ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp2\' generates 29 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp3\' generates 28 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 27 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp5\' generates 26 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp6\' generates 25 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp7\' generates 24 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp8\' generates 23 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp9\' generates 22 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp10\' generates 21 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp11\' generates 20 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp12\' generates 19 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp13\' generates 18 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp14\' generates 17 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/151958185/Mult16.v:50: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp15\' generates 16 bits.\n                                                                : ... In instance mult16\nassign outcome=(temp0+temp1+temp2+temp3+temp4+temp5+temp6+temp7+temp8+temp9+temp10+temp11+temp12+temp13+temp14+temp15)/256; \n                                                                                                              ^\n%Error: Exiting due to 31 warning(s)\n'
function [15:0] mult16x1; 
input [15:0] operand; 
input sel; 
begin  
   mult16x1=(sel)?(operand):15'b0;

end
endfunction
function [15:0] mult16x1;
 
input [15:0] operand; 
input sel; 
begin  
   mult16x1=(sel)?(operand):15'b0;

end
endfunction