data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v
 line:70: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #(CLOCK_PERIOD) clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #(100);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:32: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:68: syntax error, unexpected \'@\'\n    @(negedge reset);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:70: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #(10*CLOCK_PERIOD)\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:84: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:87: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:104: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:107: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:121: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:123: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:127: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:130: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:147: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:149: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:155: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:158: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:161: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:177: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:179: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:185: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:193: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:195: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:200: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:205: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:208: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:218: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:229: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:241: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:257: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:259: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:279: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:284: syntax error, unexpected \'@\'\n              @(posedge clk)\n              ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:289: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:299: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axi_fifo_tb.v:301: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: Exiting due to 34 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module axi_fifo_tb();


  localparam FIFO_SIZE = 1;
  localparam TEST_VECTOR_SIZE = 10;


  `define CLOCK_FREQ    200e6
  `define RESET_TIME    100

  reg clk;
  initial clk = 1'b0;
  localparam CLOCK_PERIOD = 1e9/`CLOCK_FREQ;
  always
    #(CLOCK_PERIOD) clk = ~clk;

  reg reset;
  initial begin
    reset = 1'b1;
    #(`RESET_TIME);
    @(posedge clk);
    reset = 1'b0;
  end


  reg [31:0] i_tdata;
  reg i_tvalid, o_tready;
  wire i_tready, o_tvalid;
  wire [31:0] o_tdata;
  reg clear;

  axi_fifo #(
    .SIZE(FIFO_SIZE),
    .WIDTH(32))
  dut_axi_fifo (
    .clk(clk), .reset(reset), .clear(clear),
    .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
    .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
    .space(), .occupied());


  reg [TEST_VECTOR_SIZE-1:0] i_tvalid_sequence;
  reg [TEST_VECTOR_SIZE-1:0] o_tready_sequence;
  integer i,k,n,i_tready_timeout;
  reg [31:0] o_tdata_check;

  initial begin
    i_tdata = {32{1'b1}};
    i_tvalid = 1'b0;
    o_tready = 1'b0;
    i_tready_timeout = 0;
    clear = 1'b0;
    @(negedge reset);
    #(10*CLOCK_PERIOD)
    @(posedge clk);
    $display("*****************************************************");
    $display("**              Begin Assertion Tests              **");
    $display("*****************************************************");
    $display("Test 1 -- Check filling FIFO");

    for (i = 0; i < 2**FIFO_SIZE; i = i + 1) begin
      if (~i_tready) begin
          $display("Test 1 FAILED!");
          $error("FIFO size should be %d entries, but detected %d!",2**FIFO_SIZE,i);
          $stop;
      end
      i_tvalid = 1'b1;
      i_tdata = i_tdata + 32'd1;
      @(posedge clk);
    end
    i_tvalid = 1'b0;
    @(posedge clk);
    if (i_tready) begin
      $display("Test 1 warning!");
      $warning("i_tready still asserted after filling FIFO with %d entries! Might be due to output registering.",i);

    end
    $display("Test 1 Passed!");


    $display("Test 2 -- Check emptying FIFO");
    for (i = 0; i < 2**FIFO_SIZE; i = i + 1) begin
      if (~o_tvalid) begin
          $display("Test 2 FAILED!");
          $error("FIFO o_tvalid not asserted! Occured at entry %d",2**FIFO_SIZE-i+1);
          $stop;
      end
      o_tready = 1'b1;
      @(posedge clk);
    end
    o_tready = 1'b0;
    @(posedge clk);
    if (o_tvalid) begin
      $display("Test 1 FAILED!");
      $error("o_tvalid still asserted after emptying FIFO!");
      $stop;
    end
    $display("Test 2 Passed!");


    $display("Test 3 -- Check for o_tready / i_tready dropping unexpectantly");
    clear = 1'b1;
    i_tdata = {32{1'b1}};
    i_tvalid = 1'b0;
    o_tready = 1'b0;
    @(posedge clk);
    clear = 1'b0;
    @(posedge clk);
    for (i = 0; i < 2**FIFO_SIZE-1; i = i + 1) begin
      i_tvalid = 1'b1;
      i_tdata = i_tdata + 32'd1;
      @(posedge clk);
      i_tvalid = 1'b0;

      @(posedge clk);
      @(posedge clk);
      @(posedge clk);
      if (~i_tready) begin
          $display("Test 3 FAILED!");
          $error("i_tready deasserted unexpectantly after writing %d entries!",i+1);
          $stop;
      end
      if (~o_tvalid) begin
          $display("Test 3 FAILED!");
          $error("o_tvalid deasserted unexpectantly after writing %d entries!",i+1);
          $stop;
      end
    end

    i_tvalid = 1'b1;
    i_tdata = i_tdata + 32'd1;
    @(posedge clk);
    i_tvalid = 1'b0;
    @(posedge clk);
    if (i_tready) begin
        $display("Test 3 warning!");
        $warning("i_tready still asserted after writing %d entries! Might be due to output registering.",i+1);

    end
    @(posedge clk);
    for (i = 0; i < 2**FIFO_SIZE-1; i = i + 1) begin
      o_tready = 1'b1;
      @(posedge clk);
      o_tready = 1'b0;

      @(posedge clk);
      @(posedge clk);
      @(posedge clk);
      if (~i_tready) begin
          $display("Test 3 FAILED!");
          $error("i_tready deasserted unexpectantly after reading %d entries!",i+1);
          $stop;
      end
      if (~o_tvalid) begin
          $display("Test 3 FAILED!");
          $error("o_tvalid deasserted unexpectantly after reading %d entries!",i+1);
          $stop;
      end
    end

    o_tready = 1'b1;
    @(posedge clk);
    o_tready = 1'b0;
    @(posedge clk);
    if (o_tvalid) begin
        $display("Test 3 FAILED!");
        $error("o_tvalid still asserted after reading %d entries!",i+1);
        $stop;
    end
    @(posedge clk);


    $display("Test 4 -- Check for bubble states");
    clear = 1'b1;
    i_tdata = {32{1'b1}};
    i_tvalid = 1'b0;
    o_tready = 1'b0;
    @(posedge clk);
    clear = 1'b0;
    @(posedge clk);

    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
      i_tvalid = 1'b1;
      i_tdata = i_tdata + 32'd1;
      @(posedge clk);
    end

    o_tready = 1'b1;
    i_tdata = i_tdata + 32'd1;
    @(posedge clk);

    i_tdata = i_tdata + 32'd1;
    @(posedge clk);

    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
      if (~i_tready) begin
          $display("Test 4 FAILED!");
          $error("FIFO bubble state detected when writing & reading at full rate!");
          $stop;
      end
      i_tvalid = 1'b1;
      i_tdata = i_tdata + 32'd1;
      @(posedge clk);
    end

    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
      if (~i_tready | ~o_tvalid) begin
          $display("Test 4 FAILED!");
          $error("FIFO bubble state detected when write at half rate, reading at full rate!");
          $stop;
      end
      i_tvalid = ~i_tvalid;
      if (i_tvalid) i_tdata = i_tdata + 32'd1;
      @(posedge clk);
    end

    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
      if (~i_tready | ~o_tvalid) begin
          $display("Test 4 FAILED!");
          $error("FIFO bubble state detected when write at half rate, reading at full rate!");
          $stop;
      end
      o_tready = ~o_tready;
      i_tvalid = 1'b1;
      i_tdata = i_tdata + 32'd1;
      @(posedge clk);
    end
    $display("Test 4 Passed!");





    $display("Test 5 -- Check combinations of i_tvalid / o_tready");
    clear = 1'b1;
    i_tdata = {32{1'b1}};
    i_tvalid = 1'b0;
    o_tready = 1'b0;
    i_tready_timeout = 0;
    i_tvalid_sequence = {TEST_VECTOR_SIZE{1'd0}};
    o_tready_sequence = {TEST_VECTOR_SIZE{1'd0}};
    @(posedge clk);
    clear = 1'b0;
    @(posedge clk);
    for (i = 0; i < 2**TEST_VECTOR_SIZE; i = i + 1) begin
      i_tvalid_sequence = i_tvalid_sequence + 1;
      for (k = 0; k < 2**TEST_VECTOR_SIZE; k = k + 1) begin
        o_tready_sequence = o_tready_sequence + 1;
        for (n = 0; n < TEST_VECTOR_SIZE; n = n + 1) begin
          if (o_tready_sequence[n]) begin
            o_tready = 1'b1;
          end else begin
            o_tready = 1'b0;
          end




          if (i_tvalid_sequence[n] | (i_tready_timeout == TEST_VECTOR_SIZE)) begin
            i_tvalid = 1'b1;
            if (i_tready_timeout < TEST_VECTOR_SIZE) begin
              i_tdata = i_tdata + 32'd1;
            end
            @(posedge clk);
            i_tready_timeout = 0;


            while(~i_tready & (i_tready_timeout < TEST_VECTOR_SIZE)) begin
              @(posedge clk)
              i_tready_timeout = i_tready_timeout + 1;
            end
          end else begin
            i_tvalid = 1'b0;
            @(posedge clk);
          end
        end
      end

      clear = 1'b1;
      i_tdata = {32{1'b1}};
      i_tvalid = 1'b0;
      o_tready = 1'b0;
      i_tready_timeout = 0;
      @(posedge clk);
      clear = 1'b0;
      @(posedge clk);
    end
    $display("Test 5 Passed!");
    $display("All tests PASSED!");
    $stop;
  end



  always @(posedge clk) begin
    if (reset) begin
      o_tdata_check <= 32'd0;
    end else begin
      if (clear) begin
        o_tdata_check <= 32'd0;
      end
      if (o_tready & o_tvalid) begin
        o_tdata_check <= o_tdata_check + 32'd1;
        if (o_tdata != o_tdata_check) begin
          $display("Test FAILED!");
          $error("Incorrect output!");
          $stop;
        end
      end
    end
  end

endmodule
module axi_fifo_tb();



  localparam FIFO_SIZE = 1;
  localparam TEST_VECTOR_SIZE = 10;


  `define CLOCK_FREQ    200e6
  `define RESET_TIME    100

  reg clk;
  initial clk = 1'b0;
  localparam CLOCK_PERIOD = 1e9/`CLOCK_FREQ;
  always
    #(CLOCK_PERIOD) clk = ~clk;

  reg reset;
  initial begin
    reset = 1'b1;
    #(`RESET_TIME);
    @(posedge clk);
    reset = 1'b0;
  end


  reg [31:0] i_tdata;
  reg i_tvalid, o_tready;
  wire i_tready, o_tvalid;
  wire [31:0] o_tdata;
  reg clear;

  axi_fifo #(
    .SIZE(FIFO_SIZE),
    .WIDTH(32))
  dut_axi_fifo (
    .clk(clk), .reset(reset), .clear(clear),
    .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
    .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
    .space(), .occupied());


  reg [TEST_VECTOR_SIZE-1:0] i_tvalid_sequence;
  reg [TEST_VECTOR_SIZE-1:0] o_tready_sequence;
  integer i,k,n,i_tready_timeout;
  reg [31:0] o_tdata_check;

  initial begin
    i_tdata = {32{1'b1}};
    i_tvalid = 1'b0;
    o_tready = 1'b0;
    i_tready_timeout = 0;
    clear = 1'b0;
    @(negedge reset);
    #(10*CLOCK_PERIOD)
    @(posedge clk);
    $display("*****************************************************");
    $display("**              Begin Assertion Tests              **");
    $display("*****************************************************");
    $display("Test 1 -- Check filling FIFO");

    for (i = 0; i < 2**FIFO_SIZE; i = i + 1) begin
      if (~i_tready) begin
          $display("Test 1 FAILED!");
          $error("FIFO size should be %d entries, but detected %d!",2**FIFO_SIZE,i);
          $stop;
      end
      i_tvalid = 1'b1;
      i_tdata = i_tdata + 32'd1;
      @(posedge clk);
    end
    i_tvalid = 1'b0;
    @(posedge clk);
    if (i_tready) begin
      $display("Test 1 warning!");
      $warning("i_tready still asserted after filling FIFO with %d entries! Might be due to output registering.",i);

    end
    $display("Test 1 Passed!");


    $display("Test 2 -- Check emptying FIFO");
    for (i = 0; i < 2**FIFO_SIZE; i = i + 1) begin
      if (~o_tvalid) begin
          $display("Test 2 FAILED!");
          $error("FIFO o_tvalid not asserted! Occured at entry %d",2**FIFO_SIZE-i+1);
          $stop;
      end
      o_tready = 1'b1;
      @(posedge clk);
    end
    o_tready = 1'b0;
    @(posedge clk);
    if (o_tvalid) begin
      $display("Test 1 FAILED!");
      $error("o_tvalid still asserted after emptying FIFO!");
      $stop;
    end
    $display("Test 2 Passed!");


    $display("Test 3 -- Check for o_tready / i_tready dropping unexpectantly");
    clear = 1'b1;
    i_tdata = {32{1'b1}};
    i_tvalid = 1'b0;
    o_tready = 1'b0;
    @(posedge clk);
    clear = 1'b0;
    @(posedge clk);
    for (i = 0; i < 2**FIFO_SIZE-1; i = i + 1) begin
      i_tvalid = 1'b1;
      i_tdata = i_tdata + 32'd1;
      @(posedge clk);
      i_tvalid = 1'b0;

      @(posedge clk);
      @(posedge clk);
      @(posedge clk);
      if (~i_tready) begin
          $display("Test 3 FAILED!");
          $error("i_tready deasserted unexpectantly after writing %d entries!",i+1);
          $stop;
      end
      if (~o_tvalid) begin
          $display("Test 3 FAILED!");
          $error("o_tvalid deasserted unexpectantly after writing %d entries!",i+1);
          $stop;
      end
    end

    i_tvalid = 1'b1;
    i_tdata = i_tdata + 32'd1;
    @(posedge clk);
    i_tvalid = 1'b0;
    @(posedge clk);
    if (i_tready) begin
        $display("Test 3 warning!");
        $warning("i_tready still asserted after writing %d entries! Might be due to output registering.",i+1);

    end
    @(posedge clk);
    for (i = 0; i < 2**FIFO_SIZE-1; i = i + 1) begin
      o_tready = 1'b1;
      @(posedge clk);
      o_tready = 1'b0;

      @(posedge clk);
      @(posedge clk);
      @(posedge clk);
      if (~i_tready) begin
          $display("Test 3 FAILED!");
          $error("i_tready deasserted unexpectantly after reading %d entries!",i+1);
          $stop;
      end
      if (~o_tvalid) begin
          $display("Test 3 FAILED!");
          $error("o_tvalid deasserted unexpectantly after reading %d entries!",i+1);
          $stop;
      end
    end

    o_tready = 1'b1;
    @(posedge clk);
    o_tready = 1'b0;
    @(posedge clk);
    if (o_tvalid) begin
        $display("Test 3 FAILED!");
        $error("o_tvalid still asserted after reading %d entries!",i+1);
        $stop;
    end
    @(posedge clk);


    $display("Test 4 -- Check for bubble states");
    clear = 1'b1;
    i_tdata = {32{1'b1}};
    i_tvalid = 1'b0;
    o_tready = 1'b0;
    @(posedge clk);
    clear = 1'b0;
    @(posedge clk);

    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
      i_tvalid = 1'b1;
      i_tdata = i_tdata + 32'd1;
      @(posedge clk);
    end

    o_tready = 1'b1;
    i_tdata = i_tdata + 32'd1;
    @(posedge clk);

    i_tdata = i_tdata + 32'd1;
    @(posedge clk);

    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
      if (~i_tready) begin
          $display("Test 4 FAILED!");
          $error("FIFO bubble state detected when writing & reading at full rate!");
          $stop;
      end
      i_tvalid = 1'b1;
      i_tdata = i_tdata + 32'd1;
      @(posedge clk);
    end

    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
      if (~i_tready | ~o_tvalid) begin
          $display("Test 4 FAILED!");
          $error("FIFO bubble state detected when write at half rate, reading at full rate!");
          $stop;
      end
      i_tvalid = ~i_tvalid;
      if (i_tvalid) i_tdata = i_tdata + 32'd1;
      @(posedge clk);
    end

    for (i = 0; i < (2**FIFO_SIZE + 1)/2; i = i + 1) begin
      if (~i_tready | ~o_tvalid) begin
          $display("Test 4 FAILED!");
          $error("FIFO bubble state detected when write at half rate, reading at full rate!");
          $stop;
      end
      o_tready = ~o_tready;
      i_tvalid = 1'b1;
      i_tdata = i_tdata + 32'd1;
      @(posedge clk);
    end
    $display("Test 4 Passed!");





    $display("Test 5 -- Check combinations of i_tvalid / o_tready");
    clear = 1'b1;
    i_tdata = {32{1'b1}};
    i_tvalid = 1'b0;
    o_tready = 1'b0;
    i_tready_timeout = 0;
    i_tvalid_sequence = {TEST_VECTOR_SIZE{1'd0}};
    o_tready_sequence = {TEST_VECTOR_SIZE{1'd0}};
    @(posedge clk);
    clear = 1'b0;
    @(posedge clk);
    for (i = 0; i < 2**TEST_VECTOR_SIZE; i = i + 1) begin
      i_tvalid_sequence = i_tvalid_sequence + 1;
      for (k = 0; k < 2**TEST_VECTOR_SIZE; k = k + 1) begin
        o_tready_sequence = o_tready_sequence + 1;
        for (n = 0; n < TEST_VECTOR_SIZE; n = n + 1) begin
          if (o_tready_sequence[n]) begin
            o_tready = 1'b1;
          end else begin
            o_tready = 1'b0;
          end




          if (i_tvalid_sequence[n] | (i_tready_timeout == TEST_VECTOR_SIZE)) begin
            i_tvalid = 1'b1;
            if (i_tready_timeout < TEST_VECTOR_SIZE) begin
              i_tdata = i_tdata + 32'd1;
            end
            @(posedge clk);
            i_tready_timeout = 0;


            while(~i_tready & (i_tready_timeout < TEST_VECTOR_SIZE)) begin
              @(posedge clk)
              i_tready_timeout = i_tready_timeout + 1;
            end
          end else begin
            i_tvalid = 1'b0;
            @(posedge clk);
          end
        end
      end

      clear = 1'b1;
      i_tdata = {32{1'b1}};
      i_tvalid = 1'b0;
      o_tready = 1'b0;
      i_tready_timeout = 0;
      @(posedge clk);
      clear = 1'b0;
      @(posedge clk);
    end
    $display("Test 5 Passed!");
    $display("All tests PASSED!");
    $stop;
  end



  always @(posedge clk) begin
    if (reset) begin
      o_tdata_check <= 32'd0;
    end else begin
      if (clear) begin
        o_tdata_check <= 32'd0;
      end
      if (o_tready & o_tvalid) begin
        o_tdata_check <= o_tdata_check + 32'd1;
        if (o_tdata != o_tdata_check) begin
          $display("Test FAILED!");
          $error("Incorrect output!");
          $stop;
        end
      end
    end
  end

endmodule