data/full_repos/permissive/131069375/ultimate-risc/verilog/system.v
1: b"%Error: data/full_repos/permissive/131069375/ultimate-risc/verilog/system.v:16: Cannot find file containing module: 'mem'\n   mem mem0 (.clk(clk),\n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/131069375/ultimate-risc/verilog,data/full_repos/permissive/131069375/mem\n             data/full_repos/permissive/131069375/ultimate-risc/verilog,data/full_repos/permissive/131069375/mem.v\n             data/full_repos/permissive/131069375/ultimate-risc/verilog,data/full_repos/permissive/131069375/mem.sv\n             mem\n             mem.v\n             mem.sv\n             obj_dir/mem\n             obj_dir/mem.v\n             obj_dir/mem.sv\n%Error: data/full_repos/permissive/131069375/ultimate-risc/verilog/system.v:19: Cannot find file containing module: 'urisc'\n   urisc urisc0 (.clk(clk),.reset(reset),\n   ^~~~~\n%Error: data/full_repos/permissive/131069375/ultimate-risc/verilog/system.v:26: Cannot find file containing module: 'word_to_7seg'\n   word_to_7seg display_decode (.word(disp), .digits(digits));\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131069375/ultimate-risc/verilog/system.v:28: Cannot find file containing module: 'strobe'\n   strobe strobe0 (.reset(reset), .clock(clk), .digits(digits), .seg(seg), .an(an));\n   ^~~~~~\n%Error: Exiting due to 4 error(s)\n"
module system(

 input 	       clk,
	 

 output [6:0]  seg,
 output [3:0]  an, 
 output        dp
);

   wire        reset;
   
   wire mem_wr;
   wire [7:0] mem_in, mem_out, mem_addr;
   
   mem mem0 (.clk(clk),
         .data_in(mem_in), .addr(mem_addr), .we(mem_wr),
         .data_out(mem_out));
   urisc urisc0 (.clk(clk),.reset(reset),
         .data_in(mem_out), .addr(mem_addr), .we(mem_wr),
         .data_out(mem_in));

   wire [15:0] disp;
   wire [27:0] digits;
   assign disp = {8'h00,mem_addr};
   word_to_7seg display_decode (.word(disp), .digits(digits));

   strobe strobe0 (.reset(reset), .clock(clk), .digits(digits), .seg(seg), .an(an));

   assign dp = 1'b1;
   
endmodule
module system(

 input 	       clk,
	 

 output [6:0]  seg,
 output [3:0]  an, 
 output        dp
);


   wire        reset;
   
   wire mem_wr;
   wire [7:0] mem_in, mem_out, mem_addr;
   
   mem mem0 (.clk(clk),
         .data_in(mem_in), .addr(mem_addr), .we(mem_wr),
         .data_out(mem_out));
   urisc urisc0 (.clk(clk),.reset(reset),
         .data_in(mem_out), .addr(mem_addr), .we(mem_wr),
         .data_out(mem_in));

   wire [15:0] disp;
   wire [27:0] digits;
   assign disp = {8'h00,mem_addr};
   word_to_7seg display_decode (.word(disp), .digits(digits));

   strobe strobe0 (.reset(reset), .clock(clk), .digits(digits), .seg(seg), .an(an));

   assign dp = 1'b1;
   
endmodule