data/full_repos/permissive/157049472/Verilog Test Benches/Control_unit_tb.v
1: b'%Error: Cannot find file containing module: Test\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Test\n             data/full_repos/permissive/157049472/Verilog/Test.v\n             data/full_repos/permissive/157049472/Verilog/Test.sv\n             Test\n             Test.v\n             Test.sv\n             obj_dir/Test\n             obj_dir/Test.v\n             obj_dir/Test.sv\n%Error: Cannot find file containing module: Benches,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Benches/Control_unit_tb.v\n%Error: Exiting due to 4 error(s)\n'
module Control_unit_tb;


	reg [5:0] opcode;
	reg [10:0] opcode_ext;
	reg clk;
	reg rst;


	wire [3:0] alu_control;
	wire Branch;
	wire regWrite;
	wire MemWrite;
	wire MemRead;
	wire ALU_src;
	wire reg_data;
	wire const_src;


	ControlUnit uut (
		.opcode(opcode), 
		.opcode_ext(opcode_ext), 
		.clk(clk), 
		.rst(rst), 
		.alu_control(alu_control), 
		.Branch(Branch), 
		.regWrite(regWrite), 
		.MemWrite(MemWrite), 
		.MemRead(MemRead), 
		.ALU_src(ALU_src), 
		.reg_data(reg_data), 
		.const_src(const_src)
	);

	initial begin

		opcode = 0;
		opcode_ext = 0;
		clk = 0;
		rst = 0;


		#100;
		#10 rst = 1;
		#10 rst = 0;
		
		#10;
		opcode = 0;
		opcode_ext = 0;
      
		#10;
		opcode = 0;
		opcode_ext = 4;
		
		#10;
		opcode = 3;
		opcode_ext = 0;
		
		#10;
		opcode = 4;
		opcode_ext = 0;
		
		#10;
		opcode = 15;
		opcode_ext = 0;


	end
	
	always begin
		#5 clk = ~clk;
	end      
endmodule
module Control_unit_tb;



	reg [5:0] opcode;
	reg [10:0] opcode_ext;
	reg clk;
	reg rst;


	wire [3:0] alu_control;
	wire Branch;
	wire regWrite;
	wire MemWrite;
	wire MemRead;
	wire ALU_src;
	wire reg_data;
	wire const_src;


	ControlUnit uut (
		.opcode(opcode), 
		.opcode_ext(opcode_ext), 
		.clk(clk), 
		.rst(rst), 
		.alu_control(alu_control), 
		.Branch(Branch), 
		.regWrite(regWrite), 
		.MemWrite(MemWrite), 
		.MemRead(MemRead), 
		.ALU_src(ALU_src), 
		.reg_data(reg_data), 
		.const_src(const_src)
	);

	initial begin

		opcode = 0;
		opcode_ext = 0;
		clk = 0;
		rst = 0;


		#100;
		#10 rst = 1;
		#10 rst = 0;
		
		#10;
		opcode = 0;
		opcode_ext = 0;
      
		#10;
		opcode = 0;
		opcode_ext = 4;
		
		#10;
		opcode = 3;
		opcode_ext = 0;
		
		#10;
		opcode = 4;
		opcode_ext = 0;
		
		#10;
		opcode = 15;
		opcode_ext = 0;


	end
	
	always begin
		#5 clk = ~clk;
	end      
endmodule