data/full_repos/permissive/169225814/modules/padring/rtl/padring.v
1: b"%Error: data/full_repos/permissive/169225814/modules/padring/rtl/padring.v:96: Cannot find file containing module: 'PWC_VD_PDO_33V'\n PWC_VD_PDO_33V u_poc_pad_inst (\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169225814/modules/padring/rtl,data/full_repos/permissive/169225814/PWC_VD_PDO_33V\n             data/full_repos/permissive/169225814/modules/padring/rtl,data/full_repos/permissive/169225814/PWC_VD_PDO_33V.v\n             data/full_repos/permissive/169225814/modules/padring/rtl,data/full_repos/permissive/169225814/PWC_VD_PDO_33V.sv\n             PWC_VD_PDO_33V\n             PWC_VD_PDO_33V.v\n             PWC_VD_PDO_33V.sv\n             obj_dir/PWC_VD_PDO_33V\n             obj_dir/PWC_VD_PDO_33V.v\n             obj_dir/PWC_VD_PDO_33V.sv\n%Error: data/full_repos/permissive/169225814/modules/padring/rtl/padring.v:109: Cannot find file containing module: 'STC_IN_001_33V_NC'\n STC_IN_001_33V_NC u_nPORESET_pad_inst (\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/padring/rtl/padring.v:121: Cannot find file containing module: 'STC_IN_001_33V_NC'\n STC_IN_001_33V_NC u_nRESET_pad_inst   (\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/padring/rtl/padring.v:133: Cannot find file containing module: 'STC_IN_001_33V_NC'\n STC_IN_001_33V_NC u_CLK_pad_inst (\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/padring/rtl/padring.v:147: Cannot find file containing module: 'SRC_BI_SDS_33V_STB'\n    SRC_BI_SDS_33V_STB u_pad_inst (\n    ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module padring #(
  parameter NUM_PADS  = 100,
  parameter PAD_CTL_W = 8
  )(
`ifndef FPGA_SYNTH
  input  wire                 VDD,
  input  wire                 DVDD,
  input  wire                 VSS,
  input  wire                 DVSS,
`endif
  inout  wire [NUM_PADS-1 :0] pad,
  input  wire [NUM_PADS-1 :3] pad_in,
  output wire [NUM_PADS-1 :0] pad_out,
  input  wire [PAD_CTL_W-1:0] pad_ctl[NUM_PADS-1:3]
);






genvar i;
`ifdef FPGA_SYNTH

IBUF #(
.IOSTANDARD("LVCMOS33")
) u_nPORESET_pad_inst (
    .O(pad_out[0]),
    .I(pad[0])
    );


IBUF #(
.IOSTANDARD("LVCMOS33")
) u_nRESET_pad_inst (
    .O(pad_out[1]),
    .I(pad[1])
    );










assign pad_out[2] = pad[2];


generate
  for (i=3; i<NUM_PADS; i=i+1) begin

    IOBUF #(
       .DRIVE(2),
       .IOSTANDARD("LVCMOS33"),
       .SLEW("SLOW")
    ) u_pad_inst (
        .O  (pad_out[i]),
        .IO (pad[i]),
        .I  (pad_in[i]),
        .T  (pad_ctl[i][0])
        );
  end
endgenerate


`else
 PWC_VD_PDO_33V u_poc_pad_inst (
   .SEL18 (1'b0),
   .POC   (POC_HV),
   .HVPS  (HVPS_HV),
   .BIAS  (BIAS_HV),
   .VDD   (VDD),
   .VSS   (VSS),
   .DVDD  (DVDD),
   .DVSS  (DVSS)
 );



 STC_IN_001_33V_NC u_nPORESET_pad_inst (
  .PAD  (pad[0]),
  .C    (pad_out[0]),
  .HVPS (HVPS_HV),
  .POC  (POC_HV),
  .BIAS (BIAS_HV),
  .VDD  (VDD),
  .VSS  (VSS),
  .DVDD (DVDD),
  .DVSS (DVSS)
 );

 STC_IN_001_33V_NC u_nRESET_pad_inst   (
  .PAD  (pad[1]),
  .C    (pad_out[1]),
  .HVPS (HVPS_HV),
  .POC  (POC_HV),
  .BIAS (BIAS_HV),
  .VDD  (VDD),
  .VSS  (VSS),
  .DVDD (DVDD),
  .DVSS (DVSS)
 );

 STC_IN_001_33V_NC u_CLK_pad_inst (
  .PAD  (pad[2]),
  .C    (pad_out[2]),
  .HVPS (HVPS_HV),
  .POC  (POC_HV),
  .BIAS (BIAS_HV),
  .VDD  (VDD),
  .VSS  (VSS),
  .DVDD (DVDD),
  .DVSS (DVSS)
 );

generate
  for (i=3; i<NUM_PADS; i=i+1) begin
    SRC_BI_SDS_33V_STB u_pad_inst (
      .I    (pad_in[i]),
      .C    (pad_out[i]),
      .PAD  (pad[i]),
      .OEN  (pad_ctl[i][0]),
      .REN  (pad_ctl[i][1]),
      .P1   (pad_ctl[i][2]),
      .P2   (pad_ctl[i][3]),
      .E1   (pad_ctl[i][4]),
      .E2   (pad_ctl[i][5]),
      .SMT  (pad_ctl[i][6]),
      .SR   (pad_ctl[i][7]),
      .POS  (pad_ctl[i][8]),
      .HVPS (HVPS_HV),
      .POC  (POC_HV),
      .BIAS (BIAS_HV),
      .VDD  (VDD),
      .VSS  (VSS),
      .DVDD (DVDD),
      .DVSS (DVSS)
    );
  end
endgenerate
`endif
 endmodule
module padring #(
  parameter NUM_PADS  = 100,
  parameter PAD_CTL_W = 8
  )(
`ifndef FPGA_SYNTH
  input  wire                 VDD,
  input  wire                 DVDD,
  input  wire                 VSS,
  input  wire                 DVSS,
`endif
  inout  wire [NUM_PADS-1 :0] pad,
  input  wire [NUM_PADS-1 :3] pad_in,
  output wire [NUM_PADS-1 :0] pad_out,
  input  wire [PAD_CTL_W-1:0] pad_ctl[NUM_PADS-1:3]
);







genvar i;
`ifdef FPGA_SYNTH

IBUF #(
.IOSTANDARD("LVCMOS33")
) u_nPORESET_pad_inst (
    .O(pad_out[0]),
    .I(pad[0])
    );


IBUF #(
.IOSTANDARD("LVCMOS33")
) u_nRESET_pad_inst (
    .O(pad_out[1]),
    .I(pad[1])
    );










assign pad_out[2] = pad[2];


generate
  for (i=3; i<NUM_PADS; i=i+1) begin

    IOBUF #(
       .DRIVE(2),
       .IOSTANDARD("LVCMOS33"),
       .SLEW("SLOW")
    ) u_pad_inst (
        .O  (pad_out[i]),
        .IO (pad[i]),
        .I  (pad_in[i]),
        .T  (pad_ctl[i][0])
        );
  end
endgenerate


`else
 PWC_VD_PDO_33V u_poc_pad_inst (
   .SEL18 (1'b0),
   .POC   (POC_HV),
   .HVPS  (HVPS_HV),
   .BIAS  (BIAS_HV),
   .VDD   (VDD),
   .VSS   (VSS),
   .DVDD  (DVDD),
   .DVSS  (DVSS)
 );



 STC_IN_001_33V_NC u_nPORESET_pad_inst (
  .PAD  (pad[0]),
  .C    (pad_out[0]),
  .HVPS (HVPS_HV),
  .POC  (POC_HV),
  .BIAS (BIAS_HV),
  .VDD  (VDD),
  .VSS  (VSS),
  .DVDD (DVDD),
  .DVSS (DVSS)
 );

 STC_IN_001_33V_NC u_nRESET_pad_inst   (
  .PAD  (pad[1]),
  .C    (pad_out[1]),
  .HVPS (HVPS_HV),
  .POC  (POC_HV),
  .BIAS (BIAS_HV),
  .VDD  (VDD),
  .VSS  (VSS),
  .DVDD (DVDD),
  .DVSS (DVSS)
 );

 STC_IN_001_33V_NC u_CLK_pad_inst (
  .PAD  (pad[2]),
  .C    (pad_out[2]),
  .HVPS (HVPS_HV),
  .POC  (POC_HV),
  .BIAS (BIAS_HV),
  .VDD  (VDD),
  .VSS  (VSS),
  .DVDD (DVDD),
  .DVSS (DVSS)
 );

generate
  for (i=3; i<NUM_PADS; i=i+1) begin
    SRC_BI_SDS_33V_STB u_pad_inst (
      .I    (pad_in[i]),
      .C    (pad_out[i]),
      .PAD  (pad[i]),
      .OEN  (pad_ctl[i][0]),
      .REN  (pad_ctl[i][1]),
      .P1   (pad_ctl[i][2]),
      .P2   (pad_ctl[i][3]),
      .E1   (pad_ctl[i][4]),
      .E2   (pad_ctl[i][5]),
      .SMT  (pad_ctl[i][6]),
      .SR   (pad_ctl[i][7]),
      .POS  (pad_ctl[i][8]),
      .HVPS (HVPS_HV),
      .POC  (POC_HV),
      .BIAS (BIAS_HV),
      .VDD  (VDD),
      .VSS  (VSS),
      .DVDD (DVDD),
      .DVSS (DVSS)
    );
  end
endgenerate
`endif
 endmodule