data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v
None: at end of input
1: b'%Error: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:1: Cannot find include file: riscv_defs.v\n`include "riscv_defs.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151207731/rv32i/verif/pfu,data/full_repos/permissive/151207731/riscv_defs.v\n             data/full_repos/permissive/151207731/rv32i/verif/pfu,data/full_repos/permissive/151207731/riscv_defs.v.v\n             data/full_repos/permissive/151207731/rv32i/verif/pfu,data/full_repos/permissive/151207731/riscv_defs.v.sv\n             riscv_defs.v\n             riscv_defs.v.v\n             riscv_defs.v.sv\n             obj_dir/riscv_defs.v\n             obj_dir/riscv_defs.v.v\n             obj_dir/riscv_defs.v.sv\n%Error: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:15: Define or directive not defined: \'`RV_XLEN\'\n    reg  [`RV_XLEN-1:0] irspdata;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:17: Define or directive not defined: \'`RV_XLEN\'\n    wire [`RV_XLEN-1:0] fifo_dout;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:23: Define or directive not defined: \'`RV_XLEN\'\n    reg  [`RV_XLEN-1:0] hvec_pc;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:27: Define or directive not defined: \'`RV_XLEN\'\n    wire [`RV_XLEN-1:0] ireqaddr;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:30: Define or directive not defined: \'`RV_XLEN\'\n    wire [`RV_XLEN-1:0] ids_ins;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:31: Define or directive not defined: \'`RV_XLEN\'\n    wire [`RV_XLEN-1:0] ids_pc;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:41: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.lxt");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:42: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_core);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #(200_000);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Error: data/full_repos/permissive/151207731/rv32i/verif/pfu/tb_pfu.v:93: Define or directive not defined: \'`RV_XLEN\'\n            .C_FIFO_WIDTH   (`RV_XLEN),\n                             ^~~~~~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n'
module tb_core;


    parameter C_IRQV_SZ = 32;

    reg                 clk    = 1'b1;
    reg                 resetb = 1'b0;

    wire                request;
    reg                 ireqready;
    reg                 irspvalid;
    wire                irsprerr;
    reg  [`RV_XLEN-1:0] irspdata;

    wire [`RV_XLEN-1:0] fifo_dout;

    wire                ids_ack;
    reg                 ids_ack_rand;

    wire                hvec_wr;
    reg  [`RV_XLEN-1:0] hvec_pc;
    reg                 hvec_rand;

    wire                ireqvalid;
    wire [`RV_XLEN-1:0] ireqaddr;
    wire                irspready;
    wire                ids_dav;
    wire [`RV_XLEN-1:0] ids_ins;
    wire [`RV_XLEN-1:0] ids_pc;
    wire                hvec_pc_ready;






    initial
    begin
        $dumpfile("wave.lxt");
        $dumpvars(0, tb_core);
        #(200_000);
        $finish();
    end




    always
    begin
        #50;
        clk = ~clk;
    end




    always @ (posedge clk)
    begin
        resetb <= 1'b1;
    end




    assign irsprerr = 1'b0;
    assign request  = ireqvalid & ireqready;

    always @ (posedge clk or negedge resetb)
    begin
        if (~resetb) begin
        end else begin
            if (ireqvalid) begin
                ireqready <= $random();
            end
        end

        if (request) begin
            if (ireqaddr[1:0] === 2'b0); else $error("Misaligned address.");
            irspvalid <= 1'b1;
            irspdata  <= ireqaddr;
        end else begin
            irspvalid <= 1'b0;
        end
    end




    fifo
        #(
            .C_FIFO_WIDTH   (`RV_XLEN),
            .C_FIFO_DEPTH_X (4)
        ) i_fifo (

            .clk_i          (clk),
            .clk_en_i       (1'b1),
            .resetb_i       (resetb),

            .flush_i        (1'b0),
            .empty_o        (),
            .full_o         (),

            .wr_i           (request),
            .din_i          (ireqaddr),

            .rd_i           (ids_ack),
            .dout_o         (fifo_dout)
        );




    assign ids_ack = (ids_dav ? ids_ack_rand : 1'b0);

    always @ (posedge clk)
    begin
        if (ids_ack) begin
            if (fifo_dout === ids_ins && fifo_dout === ids_pc) begin
            end else begin
                $error("Incorrect data returned by PFU");
                $fatal();
            end
        end

        ids_ack_rand <= $random();
    end




    assign hvec_wr = hvec_rand & hvec_pc_ready;
    always @ (posedge clk or negedge resetb)
    begin
        if (~resetb) begin
            hvec_rand <= 1'b0;
        end else begin
            hvec_pc <= { $random(), 2'b0 };
            if (hvec_pc_ready) begin
                if ($random() % 10 == 0) begin
                    hvec_rand <= 1'b1;
                end else begin
                    hvec_rand <= 1'b0;
                end
            end
        end
    end




    pfu
        #(
            .C_BUS_SZX      (5),
            .C_FIFO_DEPTH_X (2),
            .C_RESET_VECTOR (32'h00000000)
        ) i_pfu (

            .clk_i           (clk),
            .clk_en_i        (1'b1),
            .resetb_i        (resetb),

            .ireqready_i     (ireqready),
            .ireqvalid_o     (ireqvalid),
            .ireqhpl_o       (),
            .ireqaddr_o      (ireqaddr),
            .irspready_o     (irspready),
            .irspvalid_i     (irspvalid),
            .irsprerr_i      (irsprerr),
            .irspdata_i      (irspdata),

            .ids_dav_o       (ids_dav),
            .ids_ack_i       (ids_ack),
            .ids_sofid_o     (),
            .ids_ins_o       (ids_ins),
            .ids_ferr_o      (),
            .ids_pc_o        (ids_pc),

            .hvec_pc_ready_o (hvec_pc_ready),
            .hvec_pc_wr_i    (hvec_wr),
            .hvec_pc_din_i   (hvec_pc),

            .exs_hpl_i       (2'b0)
        );
endmodule
module tb_core;



    parameter C_IRQV_SZ = 32;

    reg                 clk    = 1'b1;
    reg                 resetb = 1'b0;

    wire                request;
    reg                 ireqready;
    reg                 irspvalid;
    wire                irsprerr;
    reg  [`RV_XLEN-1:0] irspdata;

    wire [`RV_XLEN-1:0] fifo_dout;

    wire                ids_ack;
    reg                 ids_ack_rand;

    wire                hvec_wr;
    reg  [`RV_XLEN-1:0] hvec_pc;
    reg                 hvec_rand;

    wire                ireqvalid;
    wire [`RV_XLEN-1:0] ireqaddr;
    wire                irspready;
    wire                ids_dav;
    wire [`RV_XLEN-1:0] ids_ins;
    wire [`RV_XLEN-1:0] ids_pc;
    wire                hvec_pc_ready;






    initial
    begin
        $dumpfile("wave.lxt");
        $dumpvars(0, tb_core);
        #(200_000);
        $finish();
    end




    always
    begin
        #50;
        clk = ~clk;
    end




    always @ (posedge clk)
    begin
        resetb <= 1'b1;
    end




    assign irsprerr = 1'b0;
    assign request  = ireqvalid & ireqready;

    always @ (posedge clk or negedge resetb)
    begin
        if (~resetb) begin
        end else begin
            if (ireqvalid) begin
                ireqready <= $random();
            end
        end

        if (request) begin
            if (ireqaddr[1:0] === 2'b0); else $error("Misaligned address.");
            irspvalid <= 1'b1;
            irspdata  <= ireqaddr;
        end else begin
            irspvalid <= 1'b0;
        end
    end




    fifo
        #(
            .C_FIFO_WIDTH   (`RV_XLEN),
            .C_FIFO_DEPTH_X (4)
        ) i_fifo (

            .clk_i          (clk),
            .clk_en_i       (1'b1),
            .resetb_i       (resetb),

            .flush_i        (1'b0),
            .empty_o        (),
            .full_o         (),

            .wr_i           (request),
            .din_i          (ireqaddr),

            .rd_i           (ids_ack),
            .dout_o         (fifo_dout)
        );




    assign ids_ack = (ids_dav ? ids_ack_rand : 1'b0);

    always @ (posedge clk)
    begin
        if (ids_ack) begin
            if (fifo_dout === ids_ins && fifo_dout === ids_pc) begin
            end else begin
                $error("Incorrect data returned by PFU");
                $fatal();
            end
        end

        ids_ack_rand <= $random();
    end




    assign hvec_wr = hvec_rand & hvec_pc_ready;
    always @ (posedge clk or negedge resetb)
    begin
        if (~resetb) begin
            hvec_rand <= 1'b0;
        end else begin
            hvec_pc <= { $random(), 2'b0 };
            if (hvec_pc_ready) begin
                if ($random() % 10 == 0) begin
                    hvec_rand <= 1'b1;
                end else begin
                    hvec_rand <= 1'b0;
                end
            end
        end
    end




    pfu
        #(
            .C_BUS_SZX      (5),
            .C_FIFO_DEPTH_X (2),
            .C_RESET_VECTOR (32'h00000000)
        ) i_pfu (

            .clk_i           (clk),
            .clk_en_i        (1'b1),
            .resetb_i        (resetb),

            .ireqready_i     (ireqready),
            .ireqvalid_o     (ireqvalid),
            .ireqhpl_o       (),
            .ireqaddr_o      (ireqaddr),
            .irspready_o     (irspready),
            .irspvalid_i     (irspvalid),
            .irsprerr_i      (irsprerr),
            .irspdata_i      (irspdata),

            .ids_dav_o       (ids_dav),
            .ids_ack_i       (ids_ack),
            .ids_sofid_o     (),
            .ids_ins_o       (ids_ins),
            .ids_ferr_o      (),
            .ids_pc_o        (ids_pc),

            .hvec_pc_ready_o (hvec_pc_ready),
            .hvec_pc_wr_i    (hvec_wr),
            .hvec_pc_din_i   (hvec_pc),

            .exs_hpl_i       (2'b0)
        );
endmodule