data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataMem.v
'utf-8' codec can't decode byte 0xb4 in position 715: invalid start byte
data/verilator_xmls/fd76fd9c-b359-4697-a614-dc19038e320c.xml
module DataMem(
 CLK, mWR,  mRD,  DataAddress,  DataIn, DataOut
);
        
    input mWR;
    input mRD;
    input CLK;
    input wire [31:0] DataAddress;
    input wire [31:0] DataIn;
    output reg [31:0] DataOut;
    reg [7:0] ram[0:63];
    
     initial begin
        DataOut = 0;
     end

       always@( negedge CLK ) begin
           if( mWR == 1 ) begin
               ram[DataAddress] <= DataIn[31:24];
               ram[DataAddress+1] <= DataIn[23:16];
               ram[DataAddress+2] <= DataIn[15:8];
               ram[DataAddress+3] <= DataIn[7:0];
          end
          else begin
           if(mRD == 1)begin
                  DataOut[31:24] = ram[DataAddress];
                  DataOut[23:16] = ram[DataAddress+1];
                  DataOut[15:8] = ram[DataAddress+2];
                  DataOut[7:0] = ram[DataAddress+3];
              end
              else if(mRD == 0)begin
                  DataOut[31:24] = 8'bz;
                  DataOut[23:16] = 8'bz;
                  DataOut[15:8] = 8'bz;
                  DataOut[7:0] = 8'bz;
              end
          end
        end
endmodule
module DataMem(
 CLK, mWR,  mRD,  DataAddress,  DataIn, DataOut
);

        
    input mWR;
    input mRD;
    input CLK;
    input wire [31:0] DataAddress;
    input wire [31:0] DataIn;
    output reg [31:0] DataOut;
    reg [7:0] ram[0:63];
    
     initial begin
        DataOut = 0;
     end

       always@( negedge CLK ) begin
           if( mWR == 1 ) begin
               ram[DataAddress] <= DataIn[31:24];
               ram[DataAddress+1] <= DataIn[23:16];
               ram[DataAddress+2] <= DataIn[15:8];
               ram[DataAddress+3] <= DataIn[7:0];
          end
          else begin
           if(mRD == 1)begin
                  DataOut[31:24] = ram[DataAddress];
                  DataOut[23:16] = ram[DataAddress+1];
                  DataOut[15:8] = ram[DataAddress+2];
                  DataOut[7:0] = ram[DataAddress+3];
              end
              else if(mRD == 0)begin
                  DataOut[31:24] = 8'bz;
                  DataOut[23:16] = 8'bz;
                  DataOut[15:8] = 8'bz;
                  DataOut[7:0] = 8'bz;
              end
          end
        end
endmodule