data/full_repos/permissive/190698744/6 - Combinational Logic/3 - Arithmatic Circuits/7 - Signed addition overflow.v
1: b'%Error: Invalid Option: -\n'
module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);












    
    assign s = a+b;
    assign overflow = a[7]&&b[7]&&(~s[7]) || (~a[7])&&(~b[7])&&(s[7]); 

endmodule
module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);













    
    assign s = a+b;
    assign overflow = a[7]&&b[7]&&(~s[7]) || (~a[7])&&(~b[7])&&(s[7]); 

endmodule