data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram.v:118: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/timescale.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram.v:120: Cannot find include file: minsoc_defines.v\n`include "minsoc_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module minsoc_onchip_ram(
`ifdef BIST

	mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif

	clk, rst, ce, we, oe, addr, di, doq
);




parameter aw = 11;
parameter dw = 8;

`ifdef BIST



input mbist_si_i;
input [`MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif




input			clk;
input			rst;
input			ce;
input			we;
input			oe;
input 	[aw-1:0]	addr;
input	[dw-1:0]	di;
output	[dw-1:0]	doq;




`ifdef SPARTAN2
	`define MINSOC_XILINX_RAMB4
`elsif VIRTEX
	`define MINSOC_XILINX_RAMB4
`endif

`ifdef SPARTAN3
	`define MINSOC_XILINX_RAMB16
`elsif SPARTAN6
	`define MINSOC_XILINX_RAMB16
`elsif SPARTAN3E
	`define MINSOC_XILINX_RAMB16
`elsif SPARTAN3A
	`define MINSOC_XILINX_RAMB16
`elsif VIRTEX2
	`define MINSOC_XILINX_RAMB16
`elsif VIRTEX4
	`define MINSOC_XILINX_RAMB16
`elsif VIRTEX5
	`define MINSOC_XILINX_RAMB16
`endif






`ifdef ARTISAN_SSP
`else
`ifdef VIRTUALSILICON_SSP
`else
`ifdef BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif


`ifdef GENERIC_MEMORY







reg	[dw-1:0]	mem [(1<<aw)-1:0];
reg	[aw-1:0]	addr_reg;




assign doq = (oe) ? mem[addr_reg] : {dw{1'bZ}};




always @(posedge clk or posedge rst)
	if (rst)
		addr_reg <= #1 {aw{1'b0}};
	else if (ce)
		addr_reg <= #1 addr;




always @(posedge clk)
	if (ce && we)
		mem[addr] <= #1 di;


`elsif ARTISAN_SSP





`ifdef UNUSED
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef BIST
art_hssp_2048x8_bist artisan_ssp(
`else
art_hssp_2048x8 artisan_ssp(
`endif
`endif
`ifdef BIST

	.mbist_si_i(mbist_si_i),
	.mbist_so_o(mbist_so_o),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.CLK(clk),
	.CEN(~ce),
	.WEN(~we),
	.A(addr),
	.D(di),
	.OEN(~oe),
	.Q(doq)
);


`elsif AVANT_ATP





avant_atp avant_atp(
	.web(~we),
	.reb(),
	.oeb(~oe),
	.rcsb(),
	.wcsb(),
	.ra(addr),
	.wa(addr),
	.di(di),
	.doq(doq)
);


`elsif VIRAGE_SSP





virage_ssp virage_ssp(
	.clk(clk),
	.adr(addr),
	.d(di),
	.we(we),
	.oe(oe),
	.me(ce),
	.q(doq)
);


`elsif VIRTUALSILICON_SSP





`ifdef UNUSED
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef BIST
vs_hdsp_2048x8_bist vs_ssp(
`else
vs_hdsp_2048x8 vs_ssp(
`endif
`endif
`ifdef BIST

	.mbist_si_i(mbist_si_i),
	.mbist_so_o(mbist_so_o),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.CK(clk),
	.ADR(addr),
	.DI(di),
	.WEN(~we),
	.CEN(~ce),
	.OEN(~oe),
	.DOUT(doq)
);


`elsif MINSOC_XILINX_RAMB4






wire	[dw-1:0]	doq_internal;




RAMB4_S2 ramb4_s2_0(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[1:0]),
	.EN(ce),
	.WE(we),
	.DO(doq_internal[1:0])
);




RAMB4_S2 ramb4_s2_1(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[3:2]),
	.EN(ce),
	.WE(we),
	.DO(doq_internal[3:2])
);




RAMB4_S2 ramb4_s2_2(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[5:4]),
	.EN(ce),
	.WE(we),
	.DO(doq_internal[5:4])
);




RAMB4_S2 ramb4_s2_3(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[7:6]),
	.EN(ce),
	.WE(we),
	.DO(doq_internal[7:6])
);

assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };


`elsif MINSOC_XILINX_RAMB16









wire	[dw-1:0]	doq_internal;

RAMB16_S9 ramb16_s9(
	.CLK(clk),
	.SSR(rst),
	.ADDR(addr),
	.DI(di),
	.DIP(1'b0),
	.EN(ce),
	.WE(we),
	.DO(doq_internal),
	.DOP()
);

assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };


`elsif ALTERA_FPGA








wire    wr;

assign  wr = ce & we;

wire	[dw-1:0]	doq_internal;

initial $display("Using Altera LPM.");

lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .data(di),
        .we(wr),
        .q(doq_internal)
);

assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };

defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";



`endif


endmodule
module minsoc_onchip_ram(
`ifdef BIST

	mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif

	clk, rst, ce, we, oe, addr, di, doq
);





parameter aw = 11;
parameter dw = 8;

`ifdef BIST



input mbist_si_i;
input [`MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif




input			clk;
input			rst;
input			ce;
input			we;
input			oe;
input 	[aw-1:0]	addr;
input	[dw-1:0]	di;
output	[dw-1:0]	doq;




`ifdef SPARTAN2
	`define MINSOC_XILINX_RAMB4
`elsif VIRTEX
	`define MINSOC_XILINX_RAMB4
`endif

`ifdef SPARTAN3
	`define MINSOC_XILINX_RAMB16
`elsif SPARTAN6
	`define MINSOC_XILINX_RAMB16
`elsif SPARTAN3E
	`define MINSOC_XILINX_RAMB16
`elsif SPARTAN3A
	`define MINSOC_XILINX_RAMB16
`elsif VIRTEX2
	`define MINSOC_XILINX_RAMB16
`elsif VIRTEX4
	`define MINSOC_XILINX_RAMB16
`elsif VIRTEX5
	`define MINSOC_XILINX_RAMB16
`endif






`ifdef ARTISAN_SSP
`else
`ifdef VIRTUALSILICON_SSP
`else
`ifdef BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif


`ifdef GENERIC_MEMORY







reg	[dw-1:0]	mem [(1<<aw)-1:0];
reg	[aw-1:0]	addr_reg;




assign doq = (oe) ? mem[addr_reg] : {dw{1'bZ}};




always @(posedge clk or posedge rst)
	if (rst)
		addr_reg <= #1 {aw{1'b0}};
	else if (ce)
		addr_reg <= #1 addr;




always @(posedge clk)
	if (ce && we)
		mem[addr] <= #1 di;


`elsif ARTISAN_SSP





`ifdef UNUSED
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef BIST
art_hssp_2048x8_bist artisan_ssp(
`else
art_hssp_2048x8 artisan_ssp(
`endif
`endif
`ifdef BIST

	.mbist_si_i(mbist_si_i),
	.mbist_so_o(mbist_so_o),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.CLK(clk),
	.CEN(~ce),
	.WEN(~we),
	.A(addr),
	.D(di),
	.OEN(~oe),
	.Q(doq)
);


`elsif AVANT_ATP





avant_atp avant_atp(
	.web(~we),
	.reb(),
	.oeb(~oe),
	.rcsb(),
	.wcsb(),
	.ra(addr),
	.wa(addr),
	.di(di),
	.doq(doq)
);


`elsif VIRAGE_SSP





virage_ssp virage_ssp(
	.clk(clk),
	.adr(addr),
	.d(di),
	.we(we),
	.oe(oe),
	.me(ce),
	.q(doq)
);


`elsif VIRTUALSILICON_SSP





`ifdef UNUSED
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef BIST
vs_hdsp_2048x8_bist vs_ssp(
`else
vs_hdsp_2048x8 vs_ssp(
`endif
`endif
`ifdef BIST

	.mbist_si_i(mbist_si_i),
	.mbist_so_o(mbist_so_o),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.CK(clk),
	.ADR(addr),
	.DI(di),
	.WEN(~we),
	.CEN(~ce),
	.OEN(~oe),
	.DOUT(doq)
);


`elsif MINSOC_XILINX_RAMB4






wire	[dw-1:0]	doq_internal;




RAMB4_S2 ramb4_s2_0(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[1:0]),
	.EN(ce),
	.WE(we),
	.DO(doq_internal[1:0])
);




RAMB4_S2 ramb4_s2_1(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[3:2]),
	.EN(ce),
	.WE(we),
	.DO(doq_internal[3:2])
);




RAMB4_S2 ramb4_s2_2(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[5:4]),
	.EN(ce),
	.WE(we),
	.DO(doq_internal[5:4])
);




RAMB4_S2 ramb4_s2_3(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[7:6]),
	.EN(ce),
	.WE(we),
	.DO(doq_internal[7:6])
);

assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };


`elsif MINSOC_XILINX_RAMB16









wire	[dw-1:0]	doq_internal;

RAMB16_S9 ramb16_s9(
	.CLK(clk),
	.SSR(rst),
	.ADDR(addr),
	.DI(di),
	.DIP(1'b0),
	.EN(ce),
	.WE(we),
	.DO(doq_internal),
	.DOP()
);

assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };


`elsif ALTERA_FPGA








wire    wr;

assign  wr = ce & we;

wire	[dw-1:0]	doq_internal;

initial $display("Using Altera LPM.");

lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .data(di),
        .we(wr),
        .q(doq_internal)
);

assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };

defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";



`endif


endmodule