data/full_repos/permissive/150499967/basic controller v2/sram_ctrl4.v
1: b'%Error: Cannot find file containing module: controller\n        ... Looked in:\n             data/full_repos/permissive/150499967/basic/controller\n             data/full_repos/permissive/150499967/basic/controller.v\n             data/full_repos/permissive/150499967/basic/controller.sv\n             controller\n             controller.v\n             controller.sv\n             obj_dir/controller\n             obj_dir/controller.v\n             obj_dir/controller.sv\n%Error: Cannot find file containing module: v2,data/full_repos/permissive/150499967\n%Error: Cannot find file containing module: data/full_repos/permissive/150499967/basic\n%Error: Cannot find file containing module: v2/sram_ctrl4.v\n%Error: Exiting due to 4 error(s)\n'
module sram_ctrl4(clk, start_operation, rw, address_input, data_f2s, data_s2f, address_to_sram_output, we_to_sram_output, oe_to_sram_output, ce_to_sram_output, data_from_to_sram_input_output, data_ready_signal_output, writing_finished_signal_output, busy_signal_output);

  input wire clk ;

  input wire start_operation;

  input wire rw;
  input wire [18:0] address_input;
  input wire [7:0] data_f2s;

  output wire [7:0] data_s2f;
  output reg [18:0] address_to_sram_output;

  output reg we_to_sram_output;
  output reg oe_to_sram_output;
  output reg ce_to_sram_output;

  inout wire [7:0] data_from_to_sram_input_output;

  output reg data_ready_signal_output;
  output reg writing_finished_signal_output;
  output reg busy_signal_output;




  localparam [4:0]
  rd0     =   3'd1,
  rd1     =   3'd2,
  wr0     =   3'd3,
  wr1     =   3'd4,
  idle    =   3'd5;


  reg [3:0] state_reg;

  reg [7:0] register_for_reading_data;
  reg [7:0] register_for_writing_data;

  reg register_for_splitting;

  initial
    begin

      ce_to_sram_output<=1'b1;
      oe_to_sram_output<=1'b1;
      we_to_sram_output<=1'b1;

      state_reg <= idle;

      register_for_reading_data[7:0]<=8'b0000_0000;
      register_for_writing_data[7:0]<=8'b0000_0000;

      register_for_splitting<=1'b0;

      data_ready_signal_output<=1'b0;
      writing_finished_signal_output<=1'b0;
      busy_signal_output<=1'b0;


    end


  always@(posedge clk)
    begin

      case(state_reg)
        idle: 
          begin

            register_for_splitting<=1'b0;
            writing_finished_signal_output<=1'b1;

            ce_to_sram_output<=1'b1;
            oe_to_sram_output<=1'b1;
            we_to_sram_output<=1'b1;

            busy_signal_output<=1'b0;

            data_ready_signal_output<=1'b0;

            if(~start_operation)
              state_reg <= idle;
            else begin
              if(rw)
                state_reg <= rd0;
              else  
                state_reg <= wr0;
            end
          end



        rd0:
          begin
            busy_signal_output<=1'b1;

            ce_to_sram_output<=1'b0;
            oe_to_sram_output<=1'b0;
            we_to_sram_output<=1'b1;


            address_to_sram_output[18:0]<=address_input[18:0];

            state_reg <= rd1;
          end   


        rd1:
          begin
            register_for_reading_data[7:0]<=data_from_to_sram_input_output[7:0];
            data_ready_signal_output<=1'b1;

            state_reg <= idle;
          end





        wr0:
          begin

            writing_finished_signal_output<=1'b0;

            busy_signal_output<=1'b1;

            address_to_sram_output[18:0]<=address_input[18:0];
            register_for_writing_data[7:0]<=data_f2s[7:0];

            state_reg <= wr1;
          end

        wr1:
          begin
            ce_to_sram_output<=1'b0;
            oe_to_sram_output<=1'b1;
            we_to_sram_output<=1'b0;

            register_for_splitting<=1'b1;

            state_reg <= idle;

          end


      endcase

    end

  assign data_s2f = register_for_reading_data;

  assign data_from_to_sram_input_output = (register_for_splitting) ? register_for_writing_data : 8'bz;

endmodule
module sram_ctrl4(clk, start_operation, rw, address_input, data_f2s, data_s2f, address_to_sram_output, we_to_sram_output, oe_to_sram_output, ce_to_sram_output, data_from_to_sram_input_output, data_ready_signal_output, writing_finished_signal_output, busy_signal_output);


  input wire clk ;

  input wire start_operation;

  input wire rw;
  input wire [18:0] address_input;
  input wire [7:0] data_f2s;

  output wire [7:0] data_s2f;
  output reg [18:0] address_to_sram_output;

  output reg we_to_sram_output;
  output reg oe_to_sram_output;
  output reg ce_to_sram_output;

  inout wire [7:0] data_from_to_sram_input_output;

  output reg data_ready_signal_output;
  output reg writing_finished_signal_output;
  output reg busy_signal_output;




  localparam [4:0]
  rd0     =   3'd1,
  rd1     =   3'd2,
  wr0     =   3'd3,
  wr1     =   3'd4,
  idle    =   3'd5;


  reg [3:0] state_reg;

  reg [7:0] register_for_reading_data;
  reg [7:0] register_for_writing_data;

  reg register_for_splitting;

  initial
    begin

      ce_to_sram_output<=1'b1;
      oe_to_sram_output<=1'b1;
      we_to_sram_output<=1'b1;

      state_reg <= idle;

      register_for_reading_data[7:0]<=8'b0000_0000;
      register_for_writing_data[7:0]<=8'b0000_0000;

      register_for_splitting<=1'b0;

      data_ready_signal_output<=1'b0;
      writing_finished_signal_output<=1'b0;
      busy_signal_output<=1'b0;


    end


  always@(posedge clk)
    begin

      case(state_reg)
        idle: 
          begin

            register_for_splitting<=1'b0;
            writing_finished_signal_output<=1'b1;

            ce_to_sram_output<=1'b1;
            oe_to_sram_output<=1'b1;
            we_to_sram_output<=1'b1;

            busy_signal_output<=1'b0;

            data_ready_signal_output<=1'b0;

            if(~start_operation)
              state_reg <= idle;
            else begin
              if(rw)
                state_reg <= rd0;
              else  
                state_reg <= wr0;
            end
          end



        rd0:
          begin
            busy_signal_output<=1'b1;

            ce_to_sram_output<=1'b0;
            oe_to_sram_output<=1'b0;
            we_to_sram_output<=1'b1;


            address_to_sram_output[18:0]<=address_input[18:0];

            state_reg <= rd1;
          end   


        rd1:
          begin
            register_for_reading_data[7:0]<=data_from_to_sram_input_output[7:0];
            data_ready_signal_output<=1'b1;

            state_reg <= idle;
          end





        wr0:
          begin

            writing_finished_signal_output<=1'b0;

            busy_signal_output<=1'b1;

            address_to_sram_output[18:0]<=address_input[18:0];
            register_for_writing_data[7:0]<=data_f2s[7:0];

            state_reg <= wr1;
          end

        wr1:
          begin
            ce_to_sram_output<=1'b0;
            oe_to_sram_output<=1'b1;
            we_to_sram_output<=1'b0;

            register_for_splitting<=1'b1;

            state_reg <= idle;

          end


      endcase

    end

  assign data_s2f = register_for_reading_data;

  assign data_from_to_sram_input_output = (register_for_splitting) ? register_for_writing_data : 8'bz;

endmodule