data/full_repos/permissive/118082957/main/proj1.v
 line:18: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:10: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20 rst=1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:17: Unsupported: Ignoring delay on this delayed statement.\n#435\n^\n%Warning-IMPLICIT: data/full_repos/permissive/118082957/main/proj1.v:648: Signal definition not found, creating implicitly: \'Zflag_reg\'\n   MAR_next, Zflag_reg, zflag_next);\n             ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/118082957/main/proj1.v:648: Signal definition not found, creating implicitly: \'zflag_next\'\n   MAR_next, Zflag_reg, zflag_next);\n                        ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/118082957/main/proj1.v:696: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'ACC_reg\' generates 16 bits.\n                                                                     : ... In instance tb_proj1.dut.datapath\n zflag = (!ACC_reg)? 1:0;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/118082957/main/proj1.v:19: Bit extraction of array[255:0] requires 8 bit index, not 16 bits.\n                                                                    : ... In instance tb_proj1\n$display("0x00d %d\\n",tb_proj1.dut.ram_ins.mem256x16[16\'h000d]);\n                                                    ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module datapath(
 clk,
 rst,
 muxPC,
 muxMAR,
 muxACC,
 loadMAR,
 loadPC,
 loadACC,
 loadMDR,
 loadIR,
 opALU,
 zflag,
 opcode,
 MemAddr,
 MemD,
 MemQ
 ); 

 input clk;
 input rst;
 input muxPC;
 input muxMAR;
 input muxACC;
 input loadMAR;
 input loadPC;
 input loadACC;
 input loadMDR;
 input loadIR;
 input [1:0]opALU;
 output zflag;
 output [7:0]opcode;
 output reg [7:0]MemAddr;
 output [15:0]MemD;
 input [15:0]MemQ;

reg [7:0]PC_next;

reg [15:0]IR_next;
reg [15:0]ACC_next;

reg [15:0]MDR_next;
reg [7:0]MAR_next;
wire [7:0]PC_reg;
wire [15:0]IR_reg;
wire [15:0]ACC_reg;
wire [15:0]MDR_reg;
wire [7:0]MAR_reg;
reg zflag;
wire [15:0]ALU_out;


alu alus(ACC_reg, MDR_reg, opALU, ALU_out);



	registers regs(	clk, rst, PC_reg, PC_next, IR_reg, IR_next,
 			ACC_reg, ACC_next, MDR_reg, MDR_next, MAR_reg,
			MAR_next, Zflag_reg, zflag_next);



always @(*) begin

	if (loadPC) begin
		if (muxPC) begin
			PC_next = IR_reg[15:8] ;
		end else begin
			PC_next = PC_reg + 1'b1;
		end
	end else begin
		PC_next = PC_reg;
	end
	
	if (loadIR) begin
		IR_next = MDR_reg;	
	end else begin
		IR_next = IR_reg;
	end
	
	if (loadACC) begin
		if (muxACC) begin
			ACC_next = MDR_reg;
		end else begin
			ACC_next = ALU_out;
		end	
	end else begin
		ACC_next = ACC_reg;
	end
	
	if (loadMDR) begin
		MDR_next = MemQ;
	end else begin
		MDR_next = MDR_reg;
	end
	
	if (loadMAR) begin
		if (muxMAR) begin
			MAR_next = IR_reg[15:8];
		end else begin
			MAR_next = PC_reg;
		end
	end else begin
		MAR_next = MAR_reg;
	end
	
	zflag = (!ACC_reg)? 1:0;
	
	MemAddr = MAR_next;
	
end

assign opcode = IR_reg[7:0];
assign MemD = ACC_reg;

endmodule
module datapath(
 clk,
 rst,
 muxPC,
 muxMAR,
 muxACC,
 loadMAR,
 loadPC,
 loadACC,
 loadMDR,
 loadIR,
 opALU,
 zflag,
 opcode,
 MemAddr,
 MemD,
 MemQ
 );
 

 input clk;
 input rst;
 input muxPC;
 input muxMAR;
 input muxACC;
 input loadMAR;
 input loadPC;
 input loadACC;
 input loadMDR;
 input loadIR;
 input [1:0]opALU;
 output zflag;
 output [7:0]opcode;
 output reg [7:0]MemAddr;
 output [15:0]MemD;
 input [15:0]MemQ;

reg [7:0]PC_next;

reg [15:0]IR_next;
reg [15:0]ACC_next;

reg [15:0]MDR_next;
reg [7:0]MAR_next;
wire [7:0]PC_reg;
wire [15:0]IR_reg;
wire [15:0]ACC_reg;
wire [15:0]MDR_reg;
wire [7:0]MAR_reg;
reg zflag;
wire [15:0]ALU_out;


alu alus(ACC_reg, MDR_reg, opALU, ALU_out);



	registers regs(	clk, rst, PC_reg, PC_next, IR_reg, IR_next,
 			ACC_reg, ACC_next, MDR_reg, MDR_next, MAR_reg,
			MAR_next, Zflag_reg, zflag_next);



always @(*) begin

	if (loadPC) begin
		if (muxPC) begin
			PC_next = IR_reg[15:8] ;
		end else begin
			PC_next = PC_reg + 1'b1;
		end
	end else begin
		PC_next = PC_reg;
	end
	
	if (loadIR) begin
		IR_next = MDR_reg;	
	end else begin
		IR_next = IR_reg;
	end
	
	if (loadACC) begin
		if (muxACC) begin
			ACC_next = MDR_reg;
		end else begin
			ACC_next = ALU_out;
		end	
	end else begin
		ACC_next = ACC_reg;
	end
	
	if (loadMDR) begin
		MDR_next = MemQ;
	end else begin
		MDR_next = MDR_reg;
	end
	
	if (loadMAR) begin
		if (muxMAR) begin
			MAR_next = IR_reg[15:8];
		end else begin
			MAR_next = PC_reg;
		end
	end else begin
		MAR_next = MAR_reg;
	end
	
	zflag = (!ACC_reg)? 1:0;
	
	MemAddr = MAR_next;
	
end

assign opcode = IR_reg[7:0];
assign MemD = ACC_reg;

endmodule