data/full_repos/permissive/150214807/lab4.v
 line:123: before: "$"
1: b'%Error: data/full_repos/permissive/150214807/lab4.v:114: Unsupported or unknown PLI call: $monitor\n$monitor(,$time,"a = %h, b =%h, bin = %b, op = %b, cin = %b, res = %h, cout = %b",a,b,Binvert,Operation,Carryin,Result,CarryOut);\n^~~~~~~~\n%Error: data/full_repos/permissive/150214807/lab4.v:114: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n$monitor(,$time,"a = %h, b =%h, bin = %b, op = %b, cin = %b, res = %h, cout = %b",a,b,Binvert,Operation,Carryin,Result,CarryOut);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:120: Unsupported: Ignoring delay on this delayed statement.\n#100 Operation=2\'b01;  \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:121: Unsupported: Ignoring delay on this delayed statement.\n#100 Operation=2\'b10;  \n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:122: Unsupported: Ignoring delay on this delayed statement.\n#100 Binvert=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:123: Unsupported: Ignoring delay on this delayed statement.\n#200 $finish;\n^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux21(out,sel,in1,in0);
	input in1,in0,sel;
	output out;
	wire nsel,w1,w0;
	not n1(nsel,sel);
	and a1(w0,nsel,in0);
	and a2(w1,sel,in1);
	or o1(out,w0,w1);
endmodule
module mux21(out,sel,in1,in0);

	input in1,in0,sel;
	output out;
	wire nsel,w1,w0;
	not n1(nsel,sel);
	and a1(w0,nsel,in0);
	and a2(w1,sel,in1);
	or o1(out,w0,w1);
endmodule