data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/packet_proc/arm_deframer.v
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data/verilator_xmls/8ce808f0-ef2b-4d1d-9819-26bd3d7c1411.xml
module arm_deframer (

  input wire clk,
  input wire reset,
  input wire clear,

  input wire [63:0] s_axis_tdata,
  input wire [3:0]  s_axis_tuser,
  input wire        s_axis_tlast,
  input wire        s_axis_tvalid,
  output reg        s_axis_tready,

  output reg [63:0] m_axis_tdata,
  output reg [3:0]  m_axis_tuser,
  output reg        m_axis_tlast,
  output reg        m_axis_tvalid,
  input wire        m_axis_tready
);

  localparam START = 2'b00;
  localparam BODY = 2'b01;
  localparam EXTRA = 2'b10;
  localparam PAD_BYTES = 3'b110;
  wire       new_line;
  wire       valid_beat;
  reg [1:0]  state = 2'b00, next_state=2'b00;
  reg [47:0] holding_reg;
  reg [2:0]  holding_user;


  assign new_line = (s_axis_tuser[2:0] > 3'b010) || (s_axis_tuser[2:0] == 3'b000);
  assign valid_beat = s_axis_tvalid & m_axis_tready;
  always @(posedge clk) begin
    if (reset | clear) begin
      state <= START;
    end else begin
      state <=next_state;
    end
  end

  always @(posedge clk)begin
    if (s_axis_tvalid & s_axis_tready) begin

      holding_reg  <= s_axis_tdata[63:16];


      holding_user <= s_axis_tuser[2:0];
    end
  end

  always @(*) begin
    m_axis_tdata  = 64'b0;
    m_axis_tvalid = 1'b0;
    m_axis_tlast  = 1'b0;
    m_axis_tuser  = 4'b0;
    s_axis_tready = 1'b1;
    case (state)
      START : begin


        m_axis_tdata  = {s_axis_tdata[15:0], 48'b0};
        m_axis_tvalid = s_axis_tvalid;
        m_axis_tlast  = s_axis_tlast;
        m_axis_tuser  = 4'b0;
        s_axis_tready = m_axis_tready;
        if(valid_beat) next_state = BODY;
        else next_state = START;
      end
      BODY : begin


        m_axis_tdata  = {s_axis_tdata[15:0], holding_reg};
        m_axis_tvalid = s_axis_tvalid;
        m_axis_tlast  = new_line? 1'b0: s_axis_tvalid & s_axis_tlast;

        m_axis_tuser  = (new_line & s_axis_tlast) ? 4'b0: {1'b0, s_axis_tuser[2:0] + PAD_BYTES};
        s_axis_tready = m_axis_tready;
        if (valid_beat & s_axis_tlast) next_state  =  new_line ? EXTRA : START;
        else next_state = BODY;
      end
      EXTRA : begin
        m_axis_tdata  = {16'b0, holding_reg};
        m_axis_tvalid = 1'b1;
        m_axis_tlast  = 1'b1;

        m_axis_tuser  = {1'b0, holding_user + PAD_BYTES};


        s_axis_tready = 1'b0;
        if (m_axis_tready) next_state = START;
        else next_state = EXTRA;
      end
      default : begin
        m_axis_tdata  = 64'b0;
        m_axis_tvalid = 1'b0;
        m_axis_tlast  = 1'b0;
        m_axis_tuser  = 4'b0;
        s_axis_tready = 1'b1;
        next_state = START;
      end
    endcase
  end
endmodule
module arm_deframer (

  input wire clk,
  input wire reset,
  input wire clear,

  input wire [63:0] s_axis_tdata,
  input wire [3:0]  s_axis_tuser,
  input wire        s_axis_tlast,
  input wire        s_axis_tvalid,
  output reg        s_axis_tready,

  output reg [63:0] m_axis_tdata,
  output reg [3:0]  m_axis_tuser,
  output reg        m_axis_tlast,
  output reg        m_axis_tvalid,
  input wire        m_axis_tready
);


  localparam START = 2'b00;
  localparam BODY = 2'b01;
  localparam EXTRA = 2'b10;
  localparam PAD_BYTES = 3'b110;
  wire       new_line;
  wire       valid_beat;
  reg [1:0]  state = 2'b00, next_state=2'b00;
  reg [47:0] holding_reg;
  reg [2:0]  holding_user;


  assign new_line = (s_axis_tuser[2:0] > 3'b010) || (s_axis_tuser[2:0] == 3'b000);
  assign valid_beat = s_axis_tvalid & m_axis_tready;
  always @(posedge clk) begin
    if (reset | clear) begin
      state <= START;
    end else begin
      state <=next_state;
    end
  end

  always @(posedge clk)begin
    if (s_axis_tvalid & s_axis_tready) begin

      holding_reg  <= s_axis_tdata[63:16];


      holding_user <= s_axis_tuser[2:0];
    end
  end

  always @(*) begin
    m_axis_tdata  = 64'b0;
    m_axis_tvalid = 1'b0;
    m_axis_tlast  = 1'b0;
    m_axis_tuser  = 4'b0;
    s_axis_tready = 1'b1;
    case (state)
      START : begin


        m_axis_tdata  = {s_axis_tdata[15:0], 48'b0};
        m_axis_tvalid = s_axis_tvalid;
        m_axis_tlast  = s_axis_tlast;
        m_axis_tuser  = 4'b0;
        s_axis_tready = m_axis_tready;
        if(valid_beat) next_state = BODY;
        else next_state = START;
      end
      BODY : begin


        m_axis_tdata  = {s_axis_tdata[15:0], holding_reg};
        m_axis_tvalid = s_axis_tvalid;
        m_axis_tlast  = new_line? 1'b0: s_axis_tvalid & s_axis_tlast;

        m_axis_tuser  = (new_line & s_axis_tlast) ? 4'b0: {1'b0, s_axis_tuser[2:0] + PAD_BYTES};
        s_axis_tready = m_axis_tready;
        if (valid_beat & s_axis_tlast) next_state  =  new_line ? EXTRA : START;
        else next_state = BODY;
      end
      EXTRA : begin
        m_axis_tdata  = {16'b0, holding_reg};
        m_axis_tvalid = 1'b1;
        m_axis_tlast  = 1'b1;

        m_axis_tuser  = {1'b0, holding_user + PAD_BYTES};


        s_axis_tready = 1'b0;
        if (m_axis_tready) next_state = START;
        else next_state = EXTRA;
      end
      default : begin
        m_axis_tdata  = 64'b0;
        m_axis_tvalid = 1'b0;
        m_axis_tlast  = 1'b0;
        m_axis_tuser  = 4'b0;
        s_axis_tready = 1'b1;
        next_state = START;
      end
    endcase
  end
endmodule