data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v
None: at end of input
1: b'%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:21: Cannot find include file: common.h\n`include "common.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.v\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.sv\n             common.h\n             common.h.v\n             common.h.sv\n             obj_dir/common.h\n             obj_dir/common.h.v\n             obj_dir/common.h.sv\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:55: Define or directive not defined: \'`NUM_BWD_STATE\'\nparameter NUM_BWD_STATE               = `NUM_BWD_STATE;\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:55: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter NUM_BWD_STATE               = `NUM_BWD_STATE;\n                                                      ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:56: Define or directive not defined: \'`STATE_BWD_IDLE\'\nparameter STATE_BWD_IDLE              = `STATE_BWD_IDLE;\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter STATE_BWD_IDLE              = `STATE_BWD_IDLE;\n                                                       ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:57: Define or directive not defined: \'`STATE_BWD_INIT\'\nparameter STATE_BWD_INIT              = `STATE_BWD_INIT;\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:57: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter STATE_BWD_INIT              = `STATE_BWD_INIT;\n                                                       ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:58: Define or directive not defined: \'`STATE_BWD_COST\'\nparameter STATE_BWD_COST              = `STATE_BWD_COST;\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:58: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter STATE_BWD_COST              = `STATE_BWD_COST;\n                                                       ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:59: Define or directive not defined: \'`STATE_BWD_FC_W_SM\'\nparameter STATE_BWD_FC_W_SM           = `STATE_BWD_FC_W_SM;\n                                        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:59: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter STATE_BWD_FC_W_SM           = `STATE_BWD_FC_W_SM;\n                                                          ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:60: Define or directive not defined: \'`STATE_BWD_WEIGHTED_SUM\'\nparameter STATE_BWD_WEIGHTED_SUM      = `STATE_BWD_WEIGHTED_SUM;\n                                        ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:60: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter STATE_BWD_WEIGHTED_SUM      = `STATE_BWD_WEIGHTED_SUM;\n                                                               ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:61: Define or directive not defined: \'`STATE_BWD_ATTENTION\'\nparameter STATE_BWD_ATTENTION         = `STATE_BWD_ATTENTION;\n                                        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:61: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter STATE_BWD_ATTENTION         = `STATE_BWD_ATTENTION;\n                                                            ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:62: Define or directive not defined: \'`STATE_BWD_EMB\'\nparameter STATE_BWD_EMB               = `STATE_BWD_EMB;\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter STATE_BWD_EMB               = `STATE_BWD_EMB;\n                                                      ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:63: Define or directive not defined: \'`STATE_BWD_W_UP\'\nparameter STATE_BWD_W_UP              = `STATE_BWD_W_UP;\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter STATE_BWD_W_UP              = `STATE_BWD_W_UP;\n                                                       ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:64: Define or directive not defined: \'`STATE_BWD_END_BWD\'\nparameter STATE_BWD_END_BWD           = `STATE_BWD_END_BWD;\n                                        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter STATE_BWD_END_BWD           = `STATE_BWD_END_BWD;\n                                                          ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:66: Define or directive not defined: \'`BW_BATCH_SIZE\'\nparameter BW_BATCH_SIZE = `BW_BATCH_SIZE;\n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_BATCH_SIZE = `BW_BATCH_SIZE;\n                                        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:67: Define or directive not defined: \'`BATCH_SIZE\'\nparameter BATCH_SIZE = `BATCH_SIZE;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_bwd_path_controller.v:67: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BATCH_SIZE = `BATCH_SIZE;\n                                  ^\n%Error: Exiting due to 25 error(s)\n'
module memory_network_bwd_path_controller
(

    clk,

    rst_n,

    en_bwd_path,
    
    done_bwd_path_cost,
    done_bwd_path_fc_w_sm,
    done_bwd_path_weighted_sum,
    done_bwd_path_attention,
    done_bwd_path_fc,
    done_bwd_path_emb,
    done_bwd_path_w_up,
    done_bwd_path_count_hop,
    

    en_bwd_path_cost,
    en_bwd_path_fc_w_sm,
    en_bwd_path_weighted_sum,
    en_bwd_path_attention,
    en_bwd_path_emb,
    en_bwd_path_w_up,
    en_bwd_path_end,
    en_bwd_path_count_hop

);



parameter NUM_BWD_STATE               = `NUM_BWD_STATE;
parameter STATE_BWD_IDLE              = `STATE_BWD_IDLE;
parameter STATE_BWD_INIT              = `STATE_BWD_INIT;
parameter STATE_BWD_COST              = `STATE_BWD_COST;
parameter STATE_BWD_FC_W_SM           = `STATE_BWD_FC_W_SM;
parameter STATE_BWD_WEIGHTED_SUM      = `STATE_BWD_WEIGHTED_SUM;
parameter STATE_BWD_ATTENTION         = `STATE_BWD_ATTENTION;
parameter STATE_BWD_EMB               = `STATE_BWD_EMB;
parameter STATE_BWD_W_UP              = `STATE_BWD_W_UP;
parameter STATE_BWD_END_BWD           = `STATE_BWD_END_BWD;

parameter BW_BATCH_SIZE = `BW_BATCH_SIZE;
parameter BATCH_SIZE = `BATCH_SIZE;





input wire clk;

input wire rst_n;

input wire en_bwd_path;

input wire done_bwd_path_cost;
input wire done_bwd_path_fc_w_sm;
input wire done_bwd_path_weighted_sum;
input wire done_bwd_path_attention;
input wire done_bwd_path_fc;
input wire done_bwd_path_emb;
input wire done_bwd_path_w_up;
input wire done_bwd_path_count_hop;


output reg en_bwd_path_cost;
output reg en_bwd_path_fc_w_sm;
output reg en_bwd_path_weighted_sum;
output reg en_bwd_path_attention;
output reg en_bwd_path_emb;
output reg en_bwd_path_w_up;
output reg en_bwd_path_end;
output reg en_bwd_path_count_hop;




reg [NUM_BWD_STATE-1:0] state;
reg [NUM_BWD_STATE-1:0] state_next;

reg _en_bwd_path_cost;
reg _en_bwd_path_fc_w_sm;
reg _en_bwd_path_weighted_sum;
reg _en_bwd_path_attention;
reg _en_bwd_path_emb;
reg _en_bwd_path_w_up;
reg _en_bwd_path_end;
reg _en_bwd_path_count_hop;

reg count;
reg _count;

reg flag_done_bwd_path_attention;
reg flag_done_bwd_path_fc;




always@(*)
begin
    state_next = state;
    _en_bwd_path_cost = 1'b0;
    _en_bwd_path_fc_w_sm = 1'b0;
    _en_bwd_path_weighted_sum = 1'b0;
    _en_bwd_path_attention = 1'b0;
    _en_bwd_path_emb = 1'b0;
    _en_bwd_path_w_up = 1'b0;
    _en_bwd_path_end = 1'b0;
    
    _rst_n_b_counter = 1'b1;
    en_b_counter = 1'b0;
    _count = 1'b1;

    _en_bwd_path_count_hop = 1'b0;
    
    case(state)
        STATE_BWD_IDLE :
        begin
            state_next = STATE_BWD_INIT;
            _count = 1'b0;
        end
        STATE_BWD_INIT :
        begin
            if(en_bwd_path==1'b1)
            begin
                state_next = STATE_BWD_COST;
                _count = 1'b0;
            end
        end
        STATE_BWD_COST :
        begin
            if(done_bwd_path_cost==1'b1)
            begin
                state_next = STATE_BWD_FC_W_SM;
                _count = 1'b0;
            end

            if(count==1'b0)
            begin
                _en_bwd_path_cost = 1'b1;
                _count = 1'b1;
            end
        end
        STATE_BWD_FC_W_SM :
        begin
            if(done_bwd_path_fc_w_sm==1'b1)
            begin
                state_next = STATE_BWD_WEIGHTED_SUM;
                _count = 1'b0;
            end

            if(count==1'b0)
            begin
                _en_bwd_path_fc_w_sm = 1'b1;
                _count = 1'b1;
            end
        end
        STATE_BWD_WEIGHTED_SUM :
        begin
            if(done_bwd_path_weighted_sum==1'b1)
            begin
                state_next = STATE_BWD_ATTENTION;
                _count = 1'b0;
            end

            if(count==1'b0)
            begin
                _en_bwd_path_weighted_sum = 1'b1;
                _count = 1'b1;
            end
        end
        STATE_BWD_ATTENTION :
        begin

            if(flag_done_bwd_path_attention==1'b1 && flag_done_bwd_path_fc==1'b1)
            begin
                state_next = STATE_BWD_EMB;
                _count = 1'b0;
            end

            if(count==1'b0)
            begin
                _en_bwd_path_attention= 1'b1;
                _count = 1'b1;
            end
        end
        STATE_BWD_EMB :
        begin
            if(done_bwd_path_emb==1'b1)
            begin
                if(done_bwd_path_count_hop==1'b1)
                begin
                    if(count_b_counter==BATCH_SIZE-1)
                    begin
                        state_next = STATE_BWD_W_UP;
                        _count = 1'b0;
                        
                    end
                    else
                    begin
                        state_next = STATE_BWD_END_BWD;
                        _count = 1'b0;
                    end

                    en_b_counter = 1'b1;
                end
                else
                begin
                    state_next = STATE_BWD_WEIGHTED_SUM;
                    _count = 1'b0;
                    _en_bwd_path_count_hop = 1'b1;
                end
            end

            if(count==1'b0)
            begin
                _en_bwd_path_emb = 1'b1;
                _count = 1'b1;


            end
        end
        STATE_BWD_W_UP :
        begin
            if(done_bwd_path_w_up==1'b1)
            begin
                state_next = STATE_BWD_END_BWD;
                _count = 1'b0;

                _rst_n_b_counter = 1'b0;
            end

            if(count==1'b0)
            begin
                _en_bwd_path_w_up = 1'b1;
                _count = 1'b1;
            end
        end
        STATE_BWD_END_BWD :
        begin
            state_next = STATE_BWD_IDLE;

            if(count==1'b0)
            begin
                _en_bwd_path_end = 1'b1;
                _count = 1'b1;
            end
        end
        default :
        begin
            state_next = STATE_BWD_IDLE;
        end
    endcase
end




always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        state <= STATE_BWD_IDLE;
    else
        if(en_bwd_path==1'b0)
            state <= STATE_BWD_IDLE;
        else 
            state <= state_next;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_cost <= 1'b0;
    else    
        en_bwd_path_cost <= _en_bwd_path_cost;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_fc_w_sm <= 1'b0;
    else    
        en_bwd_path_fc_w_sm <= _en_bwd_path_fc_w_sm;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_weighted_sum <= 1'b0;
    else    
        en_bwd_path_weighted_sum <= _en_bwd_path_weighted_sum;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_attention <= 1'b0;
    else    
        en_bwd_path_attention <= _en_bwd_path_attention;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_emb <= 1'b0;
    else    
        en_bwd_path_emb <= _en_bwd_path_emb;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_w_up <= 1'b0;
    else    
        en_bwd_path_w_up <= _en_bwd_path_w_up;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_end <= 1'b0;
    else    
        en_bwd_path_end <= _en_bwd_path_end;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        count <= 1'b0;
    else
        count <= _count;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_count_hop <= 1'b0;
    else
        en_bwd_path_count_hop <= _en_bwd_path_count_hop;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        flag_done_bwd_path_fc = 1'b0;
    else
        if(state==STATE_BWD_EMB)
            flag_done_bwd_path_fc = 1'b0;
        else
            if(flag_done_bwd_path_fc == 1'b0)
                flag_done_bwd_path_fc = done_bwd_path_fc;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        flag_done_bwd_path_attention = 1'b0;
    else
        if(state==STATE_BWD_EMB)
            flag_done_bwd_path_attention  = 1'b0;
        else
            if(flag_done_bwd_path_attention == 1'b0)
                flag_done_bwd_path_attention = done_bwd_path_attention;
end





wire rst_n_b_counter;
reg _rst_n_b_counter;
reg en_b_counter;
wire [BW_BATCH_SIZE-1:0] count_b_counter;



assign rst_n_b_counter = rst_n && _rst_n_b_counter;

counter
#(
    .BW(BW_BATCH_SIZE),
    .COUNT_VALUE(BATCH_SIZE)
)
batch_counter
(

    .clk(clk),

    .rst_n(rst_n_b_counter),

    .en(en_b_counter),
    .en_hold_max(1'b0),

    .count(count_b_counter),

    .done()
);

`ifdef DEBUG



`endif


endmodule
module memory_network_bwd_path_controller
(

    clk,

    rst_n,

    en_bwd_path,
    
    done_bwd_path_cost,
    done_bwd_path_fc_w_sm,
    done_bwd_path_weighted_sum,
    done_bwd_path_attention,
    done_bwd_path_fc,
    done_bwd_path_emb,
    done_bwd_path_w_up,
    done_bwd_path_count_hop,
    

    en_bwd_path_cost,
    en_bwd_path_fc_w_sm,
    en_bwd_path_weighted_sum,
    en_bwd_path_attention,
    en_bwd_path_emb,
    en_bwd_path_w_up,
    en_bwd_path_end,
    en_bwd_path_count_hop

);




parameter NUM_BWD_STATE               = `NUM_BWD_STATE;
parameter STATE_BWD_IDLE              = `STATE_BWD_IDLE;
parameter STATE_BWD_INIT              = `STATE_BWD_INIT;
parameter STATE_BWD_COST              = `STATE_BWD_COST;
parameter STATE_BWD_FC_W_SM           = `STATE_BWD_FC_W_SM;
parameter STATE_BWD_WEIGHTED_SUM      = `STATE_BWD_WEIGHTED_SUM;
parameter STATE_BWD_ATTENTION         = `STATE_BWD_ATTENTION;
parameter STATE_BWD_EMB               = `STATE_BWD_EMB;
parameter STATE_BWD_W_UP              = `STATE_BWD_W_UP;
parameter STATE_BWD_END_BWD           = `STATE_BWD_END_BWD;

parameter BW_BATCH_SIZE = `BW_BATCH_SIZE;
parameter BATCH_SIZE = `BATCH_SIZE;





input wire clk;

input wire rst_n;

input wire en_bwd_path;

input wire done_bwd_path_cost;
input wire done_bwd_path_fc_w_sm;
input wire done_bwd_path_weighted_sum;
input wire done_bwd_path_attention;
input wire done_bwd_path_fc;
input wire done_bwd_path_emb;
input wire done_bwd_path_w_up;
input wire done_bwd_path_count_hop;


output reg en_bwd_path_cost;
output reg en_bwd_path_fc_w_sm;
output reg en_bwd_path_weighted_sum;
output reg en_bwd_path_attention;
output reg en_bwd_path_emb;
output reg en_bwd_path_w_up;
output reg en_bwd_path_end;
output reg en_bwd_path_count_hop;




reg [NUM_BWD_STATE-1:0] state;
reg [NUM_BWD_STATE-1:0] state_next;

reg _en_bwd_path_cost;
reg _en_bwd_path_fc_w_sm;
reg _en_bwd_path_weighted_sum;
reg _en_bwd_path_attention;
reg _en_bwd_path_emb;
reg _en_bwd_path_w_up;
reg _en_bwd_path_end;
reg _en_bwd_path_count_hop;

reg count;
reg _count;

reg flag_done_bwd_path_attention;
reg flag_done_bwd_path_fc;




always@(*)
begin
    state_next = state;
    _en_bwd_path_cost = 1'b0;
    _en_bwd_path_fc_w_sm = 1'b0;
    _en_bwd_path_weighted_sum = 1'b0;
    _en_bwd_path_attention = 1'b0;
    _en_bwd_path_emb = 1'b0;
    _en_bwd_path_w_up = 1'b0;
    _en_bwd_path_end = 1'b0;
    
    _rst_n_b_counter = 1'b1;
    en_b_counter = 1'b0;
    _count = 1'b1;

    _en_bwd_path_count_hop = 1'b0;
    
    case(state)
        STATE_BWD_IDLE :
        begin
            state_next = STATE_BWD_INIT;
            _count = 1'b0;
        end
        STATE_BWD_INIT :
        begin
            if(en_bwd_path==1'b1)
            begin
                state_next = STATE_BWD_COST;
                _count = 1'b0;
            end
        end
        STATE_BWD_COST :
        begin
            if(done_bwd_path_cost==1'b1)
            begin
                state_next = STATE_BWD_FC_W_SM;
                _count = 1'b0;
            end

            if(count==1'b0)
            begin
                _en_bwd_path_cost = 1'b1;
                _count = 1'b1;
            end
        end
        STATE_BWD_FC_W_SM :
        begin
            if(done_bwd_path_fc_w_sm==1'b1)
            begin
                state_next = STATE_BWD_WEIGHTED_SUM;
                _count = 1'b0;
            end

            if(count==1'b0)
            begin
                _en_bwd_path_fc_w_sm = 1'b1;
                _count = 1'b1;
            end
        end
        STATE_BWD_WEIGHTED_SUM :
        begin
            if(done_bwd_path_weighted_sum==1'b1)
            begin
                state_next = STATE_BWD_ATTENTION;
                _count = 1'b0;
            end

            if(count==1'b0)
            begin
                _en_bwd_path_weighted_sum = 1'b1;
                _count = 1'b1;
            end
        end
        STATE_BWD_ATTENTION :
        begin

            if(flag_done_bwd_path_attention==1'b1 && flag_done_bwd_path_fc==1'b1)
            begin
                state_next = STATE_BWD_EMB;
                _count = 1'b0;
            end

            if(count==1'b0)
            begin
                _en_bwd_path_attention= 1'b1;
                _count = 1'b1;
            end
        end
        STATE_BWD_EMB :
        begin
            if(done_bwd_path_emb==1'b1)
            begin
                if(done_bwd_path_count_hop==1'b1)
                begin
                    if(count_b_counter==BATCH_SIZE-1)
                    begin
                        state_next = STATE_BWD_W_UP;
                        _count = 1'b0;
                        
                    end
                    else
                    begin
                        state_next = STATE_BWD_END_BWD;
                        _count = 1'b0;
                    end

                    en_b_counter = 1'b1;
                end
                else
                begin
                    state_next = STATE_BWD_WEIGHTED_SUM;
                    _count = 1'b0;
                    _en_bwd_path_count_hop = 1'b1;
                end
            end

            if(count==1'b0)
            begin
                _en_bwd_path_emb = 1'b1;
                _count = 1'b1;


            end
        end
        STATE_BWD_W_UP :
        begin
            if(done_bwd_path_w_up==1'b1)
            begin
                state_next = STATE_BWD_END_BWD;
                _count = 1'b0;

                _rst_n_b_counter = 1'b0;
            end

            if(count==1'b0)
            begin
                _en_bwd_path_w_up = 1'b1;
                _count = 1'b1;
            end
        end
        STATE_BWD_END_BWD :
        begin
            state_next = STATE_BWD_IDLE;

            if(count==1'b0)
            begin
                _en_bwd_path_end = 1'b1;
                _count = 1'b1;
            end
        end
        default :
        begin
            state_next = STATE_BWD_IDLE;
        end
    endcase
end




always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        state <= STATE_BWD_IDLE;
    else
        if(en_bwd_path==1'b0)
            state <= STATE_BWD_IDLE;
        else 
            state <= state_next;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_cost <= 1'b0;
    else    
        en_bwd_path_cost <= _en_bwd_path_cost;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_fc_w_sm <= 1'b0;
    else    
        en_bwd_path_fc_w_sm <= _en_bwd_path_fc_w_sm;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_weighted_sum <= 1'b0;
    else    
        en_bwd_path_weighted_sum <= _en_bwd_path_weighted_sum;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_attention <= 1'b0;
    else    
        en_bwd_path_attention <= _en_bwd_path_attention;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_emb <= 1'b0;
    else    
        en_bwd_path_emb <= _en_bwd_path_emb;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_w_up <= 1'b0;
    else    
        en_bwd_path_w_up <= _en_bwd_path_w_up;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_end <= 1'b0;
    else    
        en_bwd_path_end <= _en_bwd_path_end;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        count <= 1'b0;
    else
        count <= _count;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_bwd_path_count_hop <= 1'b0;
    else
        en_bwd_path_count_hop <= _en_bwd_path_count_hop;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        flag_done_bwd_path_fc = 1'b0;
    else
        if(state==STATE_BWD_EMB)
            flag_done_bwd_path_fc = 1'b0;
        else
            if(flag_done_bwd_path_fc == 1'b0)
                flag_done_bwd_path_fc = done_bwd_path_fc;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        flag_done_bwd_path_attention = 1'b0;
    else
        if(state==STATE_BWD_EMB)
            flag_done_bwd_path_attention  = 1'b0;
        else
            if(flag_done_bwd_path_attention == 1'b0)
                flag_done_bwd_path_attention = done_bwd_path_attention;
end





wire rst_n_b_counter;
reg _rst_n_b_counter;
reg en_b_counter;
wire [BW_BATCH_SIZE-1:0] count_b_counter;



assign rst_n_b_counter = rst_n && _rst_n_b_counter;

counter
#(
    .BW(BW_BATCH_SIZE),
    .COUNT_VALUE(BATCH_SIZE)
)
batch_counter
(

    .clk(clk),

    .rst_n(rst_n_b_counter),

    .en(en_b_counter),
    .en_hold_max(1'b0),

    .count(count_b_counter),

    .done()
);

`ifdef DEBUG



`endif


endmodule