data/full_repos/permissive/210844779/lab5/5.4/fa.v
1: b'%Warning-WIDTH: data/full_repos/permissive/210844779/lab5/5.4/fa.v:8: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'Cin\' generates 1 bits.\n                                                                    : ... In instance fa\nassign {Carry,Sum} = A+B+Cin;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module fa(A,B,Sum,Cin,Carry);
  
  input [15:0]A,B;
  input Cin;
  output [15:0]Sum;
  output Carry;

assign {Carry,Sum} = A+B+Cin;

endmodule
module fa(A,B,Sum,Cin,Carry);

  
  input [15:0]A,B;
  input Cin;
  output [15:0]Sum;
  output Carry;

assign {Carry,Sum} = A+B+Cin;

endmodule