data/full_repos/permissive/210844779/lab5/5.3/sequence.v
1: b"%Error: data/full_repos/permissive/210844779/lab5/5.3/sequence.v:1: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\nmodule sequence (ip,rst,load,en,clk,y);\n       ^~~~~~~~\n%Error: data/full_repos/permissive/210844779/lab5/5.3/sequence.v:1: syntax error, unexpected '(', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule sequence (ip,rst,load,en,clk,y);\n                 ^~\n%Error: data/full_repos/permissive/210844779/lab5/5.3/sequence.v:10: syntax error, unexpected always\n  always@(posedge clk,posedge rst)\n  ^~~~~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module sequence (ip,rst,load,en,clk,y);
  
  input [3:0]ip;
  input rst,clk,load,en;
  output reg [3:0]y;
  


  
  always@(posedge clk,posedge rst)
  if(rst)
    y<=4'b1000;
     else if (load)
			y<=ip;
   else
        if(en)
          begin
   case (y)
     
    4'b1000 : y<=4'b0111;
    4'b0111 : y<=4'b1011;
    4'b1011 : y<=4'b0100;
    4'b0100 : y<=4'b0010;
    4'b0010 : y<=4'b0101;
    4'b0101 : y<=4'b1100;
    4'b1100 : y<=4'b0110;
    4'b0110 : y<=4'b0011;
    4'b0011 : y<=4'b1111;
    4'b1111 : y<=4'b0001;
    4'b0001 : y<=4'b1110;
    4'b1110 : y<=4'b1101;
    4'b1101 : y<=4'b1000;
    default : y<=4'b1000;
    
  endcase

end

endmodule
module sequence (ip,rst,load,en,clk,y);

  
  input [3:0]ip;
  input rst,clk,load,en;
  output reg [3:0]y;
  


  
  always@(posedge clk,posedge rst)
  if(rst)
    y<=4'b1000;
     else if (load)
			y<=ip;
   else
        if(en)
          begin
   case (y)
     
    4'b1000 : y<=4'b0111;
    4'b0111 : y<=4'b1011;
    4'b1011 : y<=4'b0100;
    4'b0100 : y<=4'b0010;
    4'b0010 : y<=4'b0101;
    4'b0101 : y<=4'b1100;
    4'b1100 : y<=4'b0110;
    4'b0110 : y<=4'b0011;
    4'b0011 : y<=4'b1111;
    4'b1111 : y<=4'b0001;
    4'b0001 : y<=4'b1110;
    4'b1110 : y<=4'b1101;
    4'b1101 : y<=4'b1000;
    default : y<=4'b1000;
    
  endcase

end

endmodule