data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/RISC_core_mem_top.v
1: b"%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/RISC_core_mem_top.v:19: Cannot find file containing module: 'RISC_core_top'\nRISC_core_top core(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl,data/full_repos/permissive/137416811/RISC_core_top\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl,data/full_repos/permissive/137416811/RISC_core_top.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl,data/full_repos/permissive/137416811/RISC_core_top.sv\n             RISC_core_top\n             RISC_core_top.v\n             RISC_core_top.sv\n             obj_dir/RISC_core_top\n             obj_dir/RISC_core_top.v\n             obj_dir/RISC_core_top.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/RISC_core_mem_top.v:21: Cannot find file containing module: 'Memory'\nMemory MEM(MEMdataout,MEMAddress);\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module RISC_core_mem_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);

output	[7:0]bus_1_out;
input	clk,rst;
output	[7:0]Reg_R0_out;
output	[7:0]Reg_R1_out;
output	[7:0]Reg_R2_out;
output	[7:0]Reg_R3_out;

wire	[7:0]bus_1_out,MEMAddress;
wire	clk,rst;
wire	[7:0]MEMdataout;
wire	[7:0]Reg_R0_out;
wire	[7:0]Reg_R1_out;
wire	[7:0]Reg_R2_out;
wire	[7:0]Reg_R3_out;


RISC_core_top core(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);

Memory MEM(MEMdataout,MEMAddress);

endmodule
module RISC_core_mem_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);


output	[7:0]bus_1_out;
input	clk,rst;
output	[7:0]Reg_R0_out;
output	[7:0]Reg_R1_out;
output	[7:0]Reg_R2_out;
output	[7:0]Reg_R3_out;

wire	[7:0]bus_1_out,MEMAddress;
wire	clk,rst;
wire	[7:0]MEMdataout;
wire	[7:0]Reg_R0_out;
wire	[7:0]Reg_R1_out;
wire	[7:0]Reg_R2_out;
wire	[7:0]Reg_R3_out;


RISC_core_top core(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);

Memory MEM(MEMdataout,MEMAddress);

endmodule