data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus/textbench161.v
 line:19: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus/textbench161.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways#(clock_period/2)CP=~CP;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus/textbench161.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #20 MR=1;CEP=1;CET=1;PE=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus/textbench161.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #20 D=$random;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus/textbench161.v:24: Unsupported: Ignoring delay on this delayed statement.\n #400 $finish;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus/textbench161.v:4: Little bit endian vector: MSB < LSB of bit range: 0:3\nreg MR,CP,CEP,CET,PE;reg[0:3]D;\n                        ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus/textbench161.v:5: Little bit endian vector: MSB < LSB of bit range: 0:3\nwire[0:3]Q;wire TC;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus/textbench161.v:20: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                    : ... In instance testbench\n   #20 D=$random;\n        ^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus/textbench161.v:26: Cannot find file containing module: \'HC161\'\nHC161 u1(MR,CP,CEP,CET,PE,D,Q,TC);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus,data/full_repos/permissive/165160692/HC161\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus,data/full_repos/permissive/165160692/HC161.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/stimulus,data/full_repos/permissive/165160692/HC161.sv\n             HC161\n             HC161.v\n             HC161.sv\n             obj_dir/HC161\n             obj_dir/HC161.v\n             obj_dir/HC161.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
reg MR,CP,CEP,CET,PE;reg[0:3]D;
wire[0:3]Q;wire TC;

parameter clock_period=20;
always#(clock_period/2)CP=~CP;

initial
 begin
  MR=0;CEP=0;CET=0;PE=0;CP=0;
  #20 MR=1;CEP=1;CET=1;PE=1;
 end

initial
 begin
  D=0;
  repeat(20)
   #20 D=$random;
 end

initial
 #400 $finish;

HC161 u1(MR,CP,CEP,CET,PE,D,Q,TC);
endmodule
module testbench;

reg MR,CP,CEP,CET,PE;reg[0:3]D;
wire[0:3]Q;wire TC;

parameter clock_period=20;
always#(clock_period/2)CP=~CP;

initial
 begin
  MR=0;CEP=0;CET=0;PE=0;CP=0;
  #20 MR=1;CEP=1;CET=1;PE=1;
 end

initial
 begin
  D=0;
  repeat(20)
   #20 D=$random;
 end

initial
 #400 $finish;

HC161 u1(MR,CP,CEP,CET,PE,D,Q,TC);
endmodule