data/full_repos/permissive/143278/ivltests/vhdl_test7.v
 line:13: before: "j"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test7.v:16: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test7.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test7.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #12000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test7.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_test7.v:30: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                          : ... In instance main.stim\n        temp[3:0] = $random % 16;\n                  ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_test7.v:47: Cannot find file containing module: \'dummy\'\n    dummy dummy_vhdl(i,o);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/dummy\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/dummy.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/dummy.sv\n             dummy\n             dummy.v\n             dummy.sv\n             obj_dir/dummy\n             obj_dir/dummy.v\n             obj_dir/dummy.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
    wire [7:0] i,o;
    wire [7:0] veri;
    dummy dummy_vhdl(i,o);
    dummy_v dummy_verilog(i, veri);
    stimulus stim(i);


    always @(i) begin
    #1;
        if(o != veri) begin
            $display("ERROR!");
            $display("VERILOG: ", veri);
            $display("VHDL: ", o);
            $stop;
        end
    end
    initial begin
        #12000;
        #10;
            $display("PASSED");

    end
endmodule
module main;

    wire [7:0] i,o;
    wire [7:0] veri;
    dummy dummy_vhdl(i,o);
    dummy_v dummy_verilog(i, veri);
    stimulus stim(i);


    always @(i) begin
    #1;
        if(o != veri) begin
            $display("ERROR!");
            $display("VERILOG: ", veri);
            $display("VHDL: ", o);
            $stop;
        end
    end
    initial begin
        #12000;
        #10;
            $display("PASSED");

    end
endmodule