data/full_repos/permissive/183092987/LedMatrix.v
 line:131: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:119: Unsupported: Ignoring delay on this delayed statement.\nalways #90.909 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:130: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:133: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:136: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:140: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:142: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:148: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:150: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:152: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:154: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:156: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:158: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:160: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:162: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:164: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:166: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:168: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:170: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:172: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:174: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:176: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:178: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:180: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:182: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:184: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:186: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:188: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:190: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:192: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:194: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:196: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:198: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:200: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:202: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:204: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:206: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:211: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:210: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:215: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:217: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:219: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:221: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:223: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:225: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:227: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:229: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:231: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:233: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:235: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:237: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:239: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:241: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:243: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:245: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:247: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:249: Unsupported: Ignoring delay on this delayed statement.\n    #25\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:251: Unsupported: Ignoring delay on this delayed statement.\n    #25\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:253: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:256: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:258: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:260: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:262: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:264: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:266: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:268: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:270: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:272: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:274: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:276: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:278: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:280: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:282: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:284: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:288: Unsupported: Ignoring delay on this delayed statement.\n    #10000000;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/183092987/LedMatrix.v:51: Bit extraction of var[103:0] requires 7 bit index, not 8 bits.\n                                                                   : ... In instance LedMatrix_Test.DUT\n    pixels[row_idx][column_idx +: 8] = ~data;\n                   ^\n%Error: Exiting due to 80 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LedMatrix
(
  input  clk,
  input  cs,
  input  sclk,
  input  mosi,
  output reg [103:0] columns,
  output reg [15:0] rows
);

reg  [103:0]  pixels [0:15];
reg  [15:0]   spi_shift_register    = 16'd0;
reg  [12:0]   scan_rate_counter     = 13'd0;
reg  [7:0]    intensity             = 8'd0;
reg  [7:0]    column_idx            = 8'd0;
wire [3:0]    active_row            = scan_rate_counter[12:9];
wire [7:0]    pwm_counter           = scan_rate_counter[8:1];
wire [7:0]    address               = spi_shift_register[15:8];
wire [7:0]    data                  = spi_shift_register[7:0];
wire [3:0]    row_idx               = address[3:0];
wire [3:0]    column_byte_idx       = address[7:4];



always@(posedge sclk) begin
  if(!cs) begin
    spi_shift_register = spi_shift_register << 1;
    spi_shift_register[0] = mosi;
  end
end
  

always@(posedge cs) begin
  if(address == 8'hff) begin
    intensity = data;
  end
  else if( column_byte_idx <= `MAX_COL_IDX ) begin
    column_idx = 8'd0;
    column_idx[6:3] = column_byte_idx;
    pixels[row_idx][column_idx +: 8] = ~data;
  end
end


always@(posedge clk) begin
  if(pwm_counter <= intensity) begin
    columns = pixels[active_row];
    case (active_row)
      0:  rows = 16'b1111111111111110;
      1:  rows = 16'b1111111111111101;
      2:  rows = 16'b1111111111111011;
      3:  rows = 16'b1111111111110111;
      4:  rows = 16'b1111111111101111;
      5:  rows = 16'b1111111111011111;
      6:  rows = 16'b1111111110111111;
      7:  rows = 16'b1111111101111111;
      8:  rows = 16'b1111111011111111;
      9:  rows = 16'b1111110111111111;
      10: rows = 16'b1111101111111111;
      11: rows = 16'b1111011111111111;
      12: rows = 16'b1110111111111111;
      13: rows = 16'b1101111111111111;
      14: rows = 16'b1011111111111111;
      15: rows = 16'b0111111111111111;
      default: rows = ~(16'd0);
    endcase
  end
  else begin
    columns = ~(104'd0);
    rows = ~(16'd0);
  end
  scan_rate_counter = scan_rate_counter + 13'd1;
end

initial begin
  rows       = ~(16'd0);
  columns    = ~(104'd0);
  pixels[0]  = ~(104'd0);
  pixels[1]  = ~(104'd0);
  pixels[2]  = ~(104'd0);
  pixels[3]  = ~(104'd0);
  pixels[4]  = ~(104'd0);
  pixels[5]  = ~(104'd0);
  pixels[6]  = ~(104'd0);
  pixels[7]  = ~(104'd0);
  pixels[8]  = ~(104'd0);
  pixels[9]  = ~(104'd0);
  pixels[10] = ~(104'd0);
  pixels[11] = ~(104'd0);
  pixels[12] = ~(104'd0);
  pixels[13] = ~(104'd0);
  pixels[14] = ~(104'd0);
  pixels[15] = ~(104'd0);
end

endmodule
module LedMatrix
(
  input  clk,
  input  cs,
  input  sclk,
  input  mosi,
  output reg [103:0] columns,
  output reg [15:0] rows
);


reg  [103:0]  pixels [0:15];
reg  [15:0]   spi_shift_register    = 16'd0;
reg  [12:0]   scan_rate_counter     = 13'd0;
reg  [7:0]    intensity             = 8'd0;
reg  [7:0]    column_idx            = 8'd0;
wire [3:0]    active_row            = scan_rate_counter[12:9];
wire [7:0]    pwm_counter           = scan_rate_counter[8:1];
wire [7:0]    address               = spi_shift_register[15:8];
wire [7:0]    data                  = spi_shift_register[7:0];
wire [3:0]    row_idx               = address[3:0];
wire [3:0]    column_byte_idx       = address[7:4];



always@(posedge sclk) begin
  if(!cs) begin
    spi_shift_register = spi_shift_register << 1;
    spi_shift_register[0] = mosi;
  end
end
  

always@(posedge cs) begin
  if(address == 8'hff) begin
    intensity = data;
  end
  else if( column_byte_idx <= `MAX_COL_IDX ) begin
    column_idx = 8'd0;
    column_idx[6:3] = column_byte_idx;
    pixels[row_idx][column_idx +: 8] = ~data;
  end
end


always@(posedge clk) begin
  if(pwm_counter <= intensity) begin
    columns = pixels[active_row];
    case (active_row)
      0:  rows = 16'b1111111111111110;
      1:  rows = 16'b1111111111111101;
      2:  rows = 16'b1111111111111011;
      3:  rows = 16'b1111111111110111;
      4:  rows = 16'b1111111111101111;
      5:  rows = 16'b1111111111011111;
      6:  rows = 16'b1111111110111111;
      7:  rows = 16'b1111111101111111;
      8:  rows = 16'b1111111011111111;
      9:  rows = 16'b1111110111111111;
      10: rows = 16'b1111101111111111;
      11: rows = 16'b1111011111111111;
      12: rows = 16'b1110111111111111;
      13: rows = 16'b1101111111111111;
      14: rows = 16'b1011111111111111;
      15: rows = 16'b0111111111111111;
      default: rows = ~(16'd0);
    endcase
  end
  else begin
    columns = ~(104'd0);
    rows = ~(16'd0);
  end
  scan_rate_counter = scan_rate_counter + 13'd1;
end

initial begin
  rows       = ~(16'd0);
  columns    = ~(104'd0);
  pixels[0]  = ~(104'd0);
  pixels[1]  = ~(104'd0);
  pixels[2]  = ~(104'd0);
  pixels[3]  = ~(104'd0);
  pixels[4]  = ~(104'd0);
  pixels[5]  = ~(104'd0);
  pixels[6]  = ~(104'd0);
  pixels[7]  = ~(104'd0);
  pixels[8]  = ~(104'd0);
  pixels[9]  = ~(104'd0);
  pixels[10] = ~(104'd0);
  pixels[11] = ~(104'd0);
  pixels[12] = ~(104'd0);
  pixels[13] = ~(104'd0);
  pixels[14] = ~(104'd0);
  pixels[15] = ~(104'd0);
end

endmodule