data/full_repos/permissive/143278/ivltests/br955.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br955.v:92: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br955.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br955.v:89: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'lp\' generates 32 bits.\n                                                                     : ... In instance top\n      sel = lp;\n          ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_2_to_1
  (
    input sel_i,
    input [1:0] dat_i,
    output dat_o
  );

  assign dat_o = sel_i && dat_i[1] || ~sel_i && dat_i[0];

endmodule
module mux_2_to_1
  (
    input sel_i,
    input [1:0] dat_i,
    output dat_o
  );


  assign dat_o = sel_i && dat_i[1] || ~sel_i && dat_i[0];

endmodule