data/full_repos/permissive/159902111/PCPU_INT/ALU.v
1: b'%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:1: Cannot find include file: Instruction_def.v\n`include "Instruction_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159902111/PCPU_INT,data/full_repos/permissive/159902111/Instruction_def.v\n             data/full_repos/permissive/159902111/PCPU_INT,data/full_repos/permissive/159902111/Instruction_def.v.v\n             data/full_repos/permissive/159902111/PCPU_INT,data/full_repos/permissive/159902111/Instruction_def.v.sv\n             Instruction_def.v\n             Instruction_def.v.v\n             Instruction_def.v.sv\n             obj_dir/Instruction_def.v\n             obj_dir/Instruction_def.v.v\n             obj_dir/Instruction_def.v.sv\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:23: Define or directive not defined: \'`ALUOP_AND\'\n     `ALUOP_AND:\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:23: syntax error, unexpected \':\', expecting endcase\n     `ALUOP_AND:\n               ^\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:25: Define or directive not defined: \'`ALUOP_OR\'\n    `ALUOP_OR:\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:27: Define or directive not defined: \'`ALUOP_NOR\'\n    `ALUOP_NOR:\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:29: Define or directive not defined: \'`ALUOP_XOR\'\n    `ALUOP_XOR:                                         \n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:40: Define or directive not defined: \'`ALUOP_SLL\'\n      `ALUOP_SLL:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:42: Define or directive not defined: \'`ALUOP_SRL\'\n     `ALUOP_SRL:\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:44: Define or directive not defined: \'`ALUOP_SRA\'\n     `ALUOP_SRA:\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:57: Define or directive not defined: \'`ALUOP_ADD\'\n      `ALUOP_ADD:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:57: syntax error, unexpected \':\', expecting endcase\n      `ALUOP_ADD:\n                ^\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:63: Define or directive not defined: \'`ALUOP_SUB\'\n      `ALUOP_SUB:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:64: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        begin\n        ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:70: Define or directive not defined: \'`ALUOP_SLT\'\n      `ALUOP_SLT:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:71: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        begin\n        ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:79: Define or directive not defined: \'`ALUOP_SLTU\'\n      `ALUOP_SLTU:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:80: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        begin\n        ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:84: syntax error, unexpected \':\', expecting clocking\n      default:\n             ^\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:96: Define or directive not defined: \'`ALUOP_NOP\'\n      `ALUOP_NOP:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:101: Define or directive not defined: \'`ALUOP_ADD\'\n      `ALUOP_ADD,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:102: Define or directive not defined: \'`ALUOP_SUB\'\n      `ALUOP_SUB,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:103: Define or directive not defined: \'`ALUOP_SLT\'\n      `ALUOP_SLT,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:104: Define or directive not defined: \'`ALUOP_SLTU\'\n      `ALUOP_SLTU:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:109: Define or directive not defined: \'`ALUOP_AND\'\n      `ALUOP_AND,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:110: Define or directive not defined: \'`ALUOP_NOR\'\n      `ALUOP_NOR,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:111: Define or directive not defined: \'`ALUOP_OR\'\n      `ALUOP_OR,\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:112: Define or directive not defined: \'`ALUOP_XOR\'\n      `ALUOP_XOR:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:117: Define or directive not defined: \'`ALUOP_SLL\'\n      `ALUOP_SLL,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:118: Define or directive not defined: \'`ALUOP_SRL\'\n      `ALUOP_SRL,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/ALU.v:119: Define or directive not defined: \'`ALUOP_SRA\'\n      `ALUOP_SRA:\n      ^~~~~~~~~~\n%Error: Exiting due to 30 error(s)\n'
module ALU(
  input   [4:0] aluop_i,
  input   [31:0]src0_i,
  input   [31:0]src1_i,
  
  output  [63:0]aluout_o,
  output        zero_o,
  output        overflow_o
  );
  reg  [63:0]aluout;
  reg        zero;
  reg        overflow, arith_overflow;
  reg  [31:0]logic_rlt;
  reg  [31:0]shift_rlt;
  reg  [31:0]arith_rlt;


  always@(*)
  begin
    case (aluop_i)
     `ALUOP_AND:
          logic_rlt = src0_i & src1_i;
	   `ALUOP_OR:
		      logic_rlt = src0_i | src1_i;
	   `ALUOP_NOR:
		      logic_rlt = ~(src0_i | src1_i);
		  `ALUOP_XOR:
		      logic_rlt = src0_i ^ src1_i;
	   default:
		      logic_rlt = 32'b0;
    endcase
  end  


  always@(*)
  begin
    case (aluop_i)
      `ALUOP_SLL:
          shift_rlt = src1_i<<src0_i[4:0];
	    `ALUOP_SRL:
		      shift_rlt = src1_i>>src0_i[4:0];
	    `ALUOP_SRA:
		      shift_rlt = src1_i>>src0_i[4:0] | ({32{src1_i[31]}}<<(6'd32-{1'b0,src0_i[4:0]}));
	   default:
		      shift_rlt = 32'b0;
    endcase
  end


  reg [31:0]tmp_difference;
  always@(*)
  begin
    tmp_difference=src0_i-src1_i;
    case (aluop_i)
      `ALUOP_ADD:
        begin  
          arith_rlt = src0_i+src1_i;
          arith_overflow =  (~(src0_i>>31) & ~(src1_i>>31) & (arith_rlt>>31)) | ((src0_i>>31) & (src1_i>>31) & ~(arith_rlt>>31));

        end
      `ALUOP_SUB:
        begin
          arith_rlt = tmp_difference;
          arith_overflow = ((src0_i>>31) != (src1_i>>31)) && ((src1_i>>31) == arith_rlt>>31);


        end
      `ALUOP_SLT:
        begin
          arith_rlt = (
                        (src0_i[31] && !src1_i[31])
                    ||  (!src0_i[31] && !src1_i[31] && tmp_difference[31])
                    ||  (src0_i[31] && src1_i[31] && tmp_difference[31])
                    )? 32'd1:32'd0;
          arith_overflow = 1'b0;
        end
      `ALUOP_SLTU:
        begin
          arith_rlt = {31'd0,src0_i<src1_i};
          arith_overflow = 1'b0;
        end
      default:
        begin
          arith_rlt = 32'd0;
          arith_overflow = 1'b0;
        end
    endcase
  end


  always@(*)
  begin
    case(aluop_i)
      `ALUOP_NOP:
        begin
          aluout = 64'd0;
          overflow = 1'b0;
        end
      `ALUOP_ADD,
      `ALUOP_SUB,
      `ALUOP_SLT,
      `ALUOP_SLTU:
        begin
          aluout = {32'd0,arith_rlt};
          overflow = arith_overflow;
        end
      `ALUOP_AND,
      `ALUOP_NOR,
      `ALUOP_OR,
      `ALUOP_XOR:
        begin
          aluout = logic_rlt;
          overflow = 1'b0;
        end
      `ALUOP_SLL,
      `ALUOP_SRL,
      `ALUOP_SRA:
        begin
          aluout = shift_rlt;
          overflow = 1'b0;
        end
      default:
        begin
          aluout = 64'd0;
          overflow = 1'b0;
        end
    endcase
    zero = (aluout_o == 64'd0);
  end
  assign zero_o = zero;
  assign aluout_o = aluout;
  assign overflow_o = overflow;
endmodule
module ALU(
  input   [4:0] aluop_i,
  input   [31:0]src0_i,
  input   [31:0]src1_i,
  
  output  [63:0]aluout_o,
  output        zero_o,
  output        overflow_o
  );

  reg  [63:0]aluout;
  reg        zero;
  reg        overflow, arith_overflow;
  reg  [31:0]logic_rlt;
  reg  [31:0]shift_rlt;
  reg  [31:0]arith_rlt;


  always@(*)
  begin
    case (aluop_i)
     `ALUOP_AND:
          logic_rlt = src0_i & src1_i;
	   `ALUOP_OR:
		      logic_rlt = src0_i | src1_i;
	   `ALUOP_NOR:
		      logic_rlt = ~(src0_i | src1_i);
		  `ALUOP_XOR:
		      logic_rlt = src0_i ^ src1_i;
	   default:
		      logic_rlt = 32'b0;
    endcase
  end  


  always@(*)
  begin
    case (aluop_i)
      `ALUOP_SLL:
          shift_rlt = src1_i<<src0_i[4:0];
	    `ALUOP_SRL:
		      shift_rlt = src1_i>>src0_i[4:0];
	    `ALUOP_SRA:
		      shift_rlt = src1_i>>src0_i[4:0] | ({32{src1_i[31]}}<<(6'd32-{1'b0,src0_i[4:0]}));
	   default:
		      shift_rlt = 32'b0;
    endcase
  end


  reg [31:0]tmp_difference;
  always@(*)
  begin
    tmp_difference=src0_i-src1_i;
    case (aluop_i)
      `ALUOP_ADD:
        begin  
          arith_rlt = src0_i+src1_i;
          arith_overflow =  (~(src0_i>>31) & ~(src1_i>>31) & (arith_rlt>>31)) | ((src0_i>>31) & (src1_i>>31) & ~(arith_rlt>>31));

        end
      `ALUOP_SUB:
        begin
          arith_rlt = tmp_difference;
          arith_overflow = ((src0_i>>31) != (src1_i>>31)) && ((src1_i>>31) == arith_rlt>>31);


        end
      `ALUOP_SLT:
        begin
          arith_rlt = (
                        (src0_i[31] && !src1_i[31])
                    ||  (!src0_i[31] && !src1_i[31] && tmp_difference[31])
                    ||  (src0_i[31] && src1_i[31] && tmp_difference[31])
                    )? 32'd1:32'd0;
          arith_overflow = 1'b0;
        end
      `ALUOP_SLTU:
        begin
          arith_rlt = {31'd0,src0_i<src1_i};
          arith_overflow = 1'b0;
        end
      default:
        begin
          arith_rlt = 32'd0;
          arith_overflow = 1'b0;
        end
    endcase
  end


  always@(*)
  begin
    case(aluop_i)
      `ALUOP_NOP:
        begin
          aluout = 64'd0;
          overflow = 1'b0;
        end
      `ALUOP_ADD,
      `ALUOP_SUB,
      `ALUOP_SLT,
      `ALUOP_SLTU:
        begin
          aluout = {32'd0,arith_rlt};
          overflow = arith_overflow;
        end
      `ALUOP_AND,
      `ALUOP_NOR,
      `ALUOP_OR,
      `ALUOP_XOR:
        begin
          aluout = logic_rlt;
          overflow = 1'b0;
        end
      `ALUOP_SLL,
      `ALUOP_SRL,
      `ALUOP_SRA:
        begin
          aluout = shift_rlt;
          overflow = 1'b0;
        end
      default:
        begin
          aluout = 64'd0;
          overflow = 1'b0;
        end
    endcase
    zero = (aluout_o == 64'd0);
  end
  assign zero_o = zero;
  assign aluout_o = aluout;
  assign overflow_o = overflow;
endmodule