data/full_repos/permissive/121579170/spi_master_tb.v
 line:14: before: "$"
1: b'%Error: data/full_repos/permissive/121579170/spi_master_tb.v:8: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("spi_master.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/121579170/spi_master_tb.v:9: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0,spi_master_tb);\n   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/121579170/spi_master_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n   # 10  reset = 1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121579170/spi_master_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    # 10  reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/121579170/spi_master_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n   # 150 reset = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/121579170/spi_master_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    # 20  reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/121579170/spi_master_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    # 4000 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/121579170/spi_master_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    # 10  get_rdid = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/121579170/spi_master_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    # 400 get_rdid = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/121579170/spi_master_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = !clk;\n         ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spi_master_tb;

  reg reset,
      get_rdid;


  initial begin
	  $dumpfile("spi_master.vcd");
	  $dumpvars(0,spi_master_tb);
	  # 10  reset = 1;
    # 10  reset = 0;
	  # 150 reset = 1;
    # 20  reset = 0;
    # 4000 $stop;
  end


  initial begin
    # 10  get_rdid = 1;
    # 400 get_rdid = 0;
  end


  reg clk = 0;
  always #5 clk = !clk;


  spi_master m1 (clk,reset,get_rdid);






endmodule
module spi_master_tb;


  reg reset,
      get_rdid;


  initial begin
	  $dumpfile("spi_master.vcd");
	  $dumpvars(0,spi_master_tb);
	  # 10  reset = 1;
    # 10  reset = 0;
	  # 150 reset = 1;
    # 20  reset = 0;
    # 4000 $stop;
  end


  initial begin
    # 10  get_rdid = 1;
    # 400 get_rdid = 0;
  end


  reg clk = 0;
  always #5 clk = !clk;


  spi_master m1 (clk,reset,get_rdid);






endmodule