data/full_repos/permissive/19905110/minsoc/bench/verilog/vpi/dbg_comm_vpi.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/vpi/dbg_comm_vpi.v:77: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/bench/verilog/vpi,data/full_repos/permissive/19905110/timescale.v\n             data/full_repos/permissive/19905110/minsoc/bench/verilog/vpi,data/full_repos/permissive/19905110/timescale.v.v\n             data/full_repos/permissive/19905110/minsoc/bench/verilog/vpi,data/full_repos/permissive/19905110/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/vpi/dbg_comm_vpi.v:119: Unsupported or unknown PLI call: $jp_init\n $jp_init("4567");\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/bench/verilog/vpi/dbg_comm_vpi.v:120: Unsupported: Ignoring delay on this delayed statement.\n #5500;   \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/bench/verilog/vpi/dbg_comm_vpi.v:124: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/vpi/dbg_comm_vpi.v:125: Unsupported or unknown PLI call: $jp_in\n      $jp_in(memory);   \n      ^~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/vpi/dbg_comm_vpi.v:140: Unsupported or unknown PLI call: $jp_out\n $jp_out(P_TDO); \n ^~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/vpi/dbg_comm_vpi.v:155: Unsupported or unknown PLI call: $jp_wait_time\n    $jp_wait_time();\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module dbg_comm_vpi (
		       SYS_CLK,
		       P_TMS, 
		       P_TCK, 
		       P_TRST, 
		       P_TDI, 
		       P_TDO
		       );



   input     SYS_CLK;
   output    P_TMS;
   output    P_TCK;
   output    P_TRST;
   output    P_TDI;
   input     P_TDO;
   
   
   reg [4:0] memory;


   wire      P_TCK;
   wire      P_TRST;
   wire      P_TDI;
   wire      P_TMS;
   wire      P_TDO;
   
   reg [3:0] in_word_r;
   reg [5:0] clk_count;
   


   initial
     begin
	in_word_r = 5'b0;
	memory = 5'b0;
	$jp_init(`JP_PORT);
	#5500;
	
	while(1)
	  begin
	     #1;
	     $jp_in(memory);
	     if(memory[4])
	       begin
		  in_word_r = memory[3:0];
		  memory = memory & 4'b1111;
		  clk_count = 6'b000000;
	       end
	  end
     end




   always @ (P_TDO)
     begin
	$jp_out(P_TDO); 
     end


   assign P_TCK  = in_word_r[0];
   assign P_TRST = in_word_r[1];
   assign P_TDI  = in_word_r[2];
   assign P_TMS  = in_word_r[3];



   always @ (posedge SYS_CLK)
     begin
	if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1;
	else if(clk_count == `TIMEOUT_COUNT) begin
	   $jp_wait_time();
	   clk_count[5:0] = clk_count[5:0] + 1;
	end

     end 

endmodule
module dbg_comm_vpi (
		       SYS_CLK,
		       P_TMS, 
		       P_TCK, 
		       P_TRST, 
		       P_TDI, 
		       P_TDO
		       );




   input     SYS_CLK;
   output    P_TMS;
   output    P_TCK;
   output    P_TRST;
   output    P_TDI;
   input     P_TDO;
   
   
   reg [4:0] memory;


   wire      P_TCK;
   wire      P_TRST;
   wire      P_TDI;
   wire      P_TMS;
   wire      P_TDO;
   
   reg [3:0] in_word_r;
   reg [5:0] clk_count;
   


   initial
     begin
	in_word_r = 5'b0;
	memory = 5'b0;
	$jp_init(`JP_PORT);
	#5500;
	
	while(1)
	  begin
	     #1;
	     $jp_in(memory);
	     if(memory[4])
	       begin
		  in_word_r = memory[3:0];
		  memory = memory & 4'b1111;
		  clk_count = 6'b000000;
	       end
	  end
     end




   always @ (P_TDO)
     begin
	$jp_out(P_TDO); 
     end


   assign P_TCK  = in_word_r[0];
   assign P_TRST = in_word_r[1];
   assign P_TDI  = in_word_r[2];
   assign P_TMS  = in_word_r[3];



   always @ (posedge SYS_CLK)
     begin
	if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1;
	else if(clk_count == `TIMEOUT_COUNT) begin
	   $jp_wait_time();
	   clk_count[5:0] = clk_count[5:0] + 1;
	end

     end 

endmodule