data/full_repos/permissive/146246005/RISC-y Processor/RISCY_CPU.sv
 line:3: before: "package"
1: b'%Error: Cannot find file containing module: Processor,data/full_repos/permissive/146246005\n        ... Looked in:\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.v\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.sv\n             Processor,data/full_repos/permissive/146246005\n             Processor,data/full_repos/permissive/146246005.v\n             Processor,data/full_repos/permissive/146246005.sv\n             obj_dir/Processor,data/full_repos/permissive/146246005\n             obj_dir/Processor,data/full_repos/permissive/146246005.v\n             obj_dir/Processor,data/full_repos/permissive/146246005.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/RISC-y\n%Error: Cannot find file containing module: Processor/RISCY_CPU.sv\n%Error: Exiting due to 3 error(s)\n'
module RISCY(CLK,RST,IO);
	import cycle_package::*;
	input CLK, RST;
	inout [7:0] IO;

	wire IR_EN, A_EN, B_EN, PDR_EN, PORT_EN, PORT_RD, PC_EN, LOAD_EN, ALU_EN, ALU_OE, RAM_OE, RDR_EN, RAM_CS;
	
	CYCLE PHASE;
	wire PORT_DIR_OUT, AASD_RST;
	wire [3:0] OPCODE;
	wire [11:0] RESERVED;
	wire [6:0] ADDR;
	wire [4:0] PROG_ADDR;
	wire [7:0] DATA, ROM_DATA, RAM_DATA, PORT_DATA_OUT, A_OUT, B_OUT;
	wire [7:0] BiDi_Data;
	wire [31:0] ROM_OUT;
	wire I_FLAG, OF, SF, ZF, CF;
	

	RAM	RAM8(.DATA(BiDi_Data), .ADDR(ROM_DATA[4:0]), .OE(RAM_OE), .CS(RAM_CS), .WS(CLK));
	SCALE_REG #(8) REG8(.REG_OUT(RAM_DATA), .DATA_IN(BiDi_Data), .EN(RDR_EN), .CLOCK(CLK));
	
	ROM	ROM32(.DATA(ROM_OUT), .ADDR(PROG_ADDR), .OE(1'b1), .CS(1'b0));
	ProgCount #(5) PrgCnt(.Count(PROG_ADDR), .CLOCK(CLK), .RESET(AASD_RST), .Enable(PC_EN), .Load(LOAD_EN), .Data(ADDR[4:0])); 
	SCALE_REG #(32) REG32(.REG_OUT({OPCODE,I_FLAG, ADDR, RESERVED, ROM_DATA}), .DATA_IN(ROM_OUT), .EN(IR_EN), .CLOCK(CLK));
	


	PORT_DIR_REG PDR(.REG_OUT(PORT_DIR_OUT), .DATA_IN(DATA[0]), .PDR_EN(PDR_EN),.CLOCK(CLK), .RESET(AASD_RST));
	SCALE_REG #(8) IOREG(.REG_OUT(PORT_DATA_OUT), .DATA_IN(DATA), .EN(PORT_EN), .CLOCK(CLK));
	Tri_State_Buffer	Port_Data(.OUT(IO), .A(PORT_DATA_OUT), .SEL(PORT_DIR_OUT));
	Tri_State_Buffer	Port_Read(.OUT(BiDi_Data), .A(IO), .SEL(PORT_RD));

	

	SCALE_REG #(8) A_Reg(.REG_OUT(A_OUT), .DATA_IN(DATA), .EN(A_EN), .CLOCK(CLK));
	SCALE_REG #(8) B_Reg(.REG_OUT(B_OUT), .DATA_IN(DATA), .EN(B_EN), .CLOCK(CLK));
	ALU #(8) ALU0(.CLK(CLK), .EN(ALU_EN), .OE(ALU_OE), .OPCODE(OPCODE), .A(A_OUT), .B(B_OUT), .ALU_OUT(BiDi_Data), .CF(CF), .OF(OF), .SF(SF), .ZF(ZF));	
	
	

	scale_mux #(8) MUX(.A(ROM_DATA), .B(RAM_DATA), .SEL(RAM_OE), .OUT(DATA));

	

	AASD AASD0(.AASD_RST(AASD_RST), .CLOCK(CLK), .RESET(RST));
	phaser Phsr(.CLOCK(CLK), .RESET(AASD_RST), .EN(1'b0), .PHASE(PHASE));
	sequence_controller SeqCtrl(.ADDR(ADDR), .OPCODE(OPCODE), .PHASE(PHASE), .I_FLAG(I_FLAG), .ZF(ZF), .NF(SF), .OF(OF), .CF(CF), .IR_EN(IR_EN), .A_EN(A_EN), .B_EN(B_EN), .PDR_EN(PDR_EN), .PORT_EN(PORT_EN), .PORT_RD(PORT_RD), .PC_EN(PC_EN), .PC_LOAD(LOAD_EN), .ALU_EN(ALU_EN), .ALU_OE(ALU_OE), .RAM_OE(RAM_OE), .RDR_EN(RDR_EN), .RAM_CS(RAM_CS));
	
endmodule
module RISCY(CLK,RST,IO);

	import cycle_package::*;
	input CLK, RST;
	inout [7:0] IO;

	wire IR_EN, A_EN, B_EN, PDR_EN, PORT_EN, PORT_RD, PC_EN, LOAD_EN, ALU_EN, ALU_OE, RAM_OE, RDR_EN, RAM_CS;
	
	CYCLE PHASE;
	wire PORT_DIR_OUT, AASD_RST;
	wire [3:0] OPCODE;
	wire [11:0] RESERVED;
	wire [6:0] ADDR;
	wire [4:0] PROG_ADDR;
	wire [7:0] DATA, ROM_DATA, RAM_DATA, PORT_DATA_OUT, A_OUT, B_OUT;
	wire [7:0] BiDi_Data;
	wire [31:0] ROM_OUT;
	wire I_FLAG, OF, SF, ZF, CF;
	

	RAM	RAM8(.DATA(BiDi_Data), .ADDR(ROM_DATA[4:0]), .OE(RAM_OE), .CS(RAM_CS), .WS(CLK));
	SCALE_REG #(8) REG8(.REG_OUT(RAM_DATA), .DATA_IN(BiDi_Data), .EN(RDR_EN), .CLOCK(CLK));
	
	ROM	ROM32(.DATA(ROM_OUT), .ADDR(PROG_ADDR), .OE(1'b1), .CS(1'b0));
	ProgCount #(5) PrgCnt(.Count(PROG_ADDR), .CLOCK(CLK), .RESET(AASD_RST), .Enable(PC_EN), .Load(LOAD_EN), .Data(ADDR[4:0])); 
	SCALE_REG #(32) REG32(.REG_OUT({OPCODE,I_FLAG, ADDR, RESERVED, ROM_DATA}), .DATA_IN(ROM_OUT), .EN(IR_EN), .CLOCK(CLK));
	


	PORT_DIR_REG PDR(.REG_OUT(PORT_DIR_OUT), .DATA_IN(DATA[0]), .PDR_EN(PDR_EN),.CLOCK(CLK), .RESET(AASD_RST));
	SCALE_REG #(8) IOREG(.REG_OUT(PORT_DATA_OUT), .DATA_IN(DATA), .EN(PORT_EN), .CLOCK(CLK));
	Tri_State_Buffer	Port_Data(.OUT(IO), .A(PORT_DATA_OUT), .SEL(PORT_DIR_OUT));
	Tri_State_Buffer	Port_Read(.OUT(BiDi_Data), .A(IO), .SEL(PORT_RD));

	

	SCALE_REG #(8) A_Reg(.REG_OUT(A_OUT), .DATA_IN(DATA), .EN(A_EN), .CLOCK(CLK));
	SCALE_REG #(8) B_Reg(.REG_OUT(B_OUT), .DATA_IN(DATA), .EN(B_EN), .CLOCK(CLK));
	ALU #(8) ALU0(.CLK(CLK), .EN(ALU_EN), .OE(ALU_OE), .OPCODE(OPCODE), .A(A_OUT), .B(B_OUT), .ALU_OUT(BiDi_Data), .CF(CF), .OF(OF), .SF(SF), .ZF(ZF));	
	
	

	scale_mux #(8) MUX(.A(ROM_DATA), .B(RAM_DATA), .SEL(RAM_OE), .OUT(DATA));

	

	AASD AASD0(.AASD_RST(AASD_RST), .CLOCK(CLK), .RESET(RST));
	phaser Phsr(.CLOCK(CLK), .RESET(AASD_RST), .EN(1'b0), .PHASE(PHASE));
	sequence_controller SeqCtrl(.ADDR(ADDR), .OPCODE(OPCODE), .PHASE(PHASE), .I_FLAG(I_FLAG), .ZF(ZF), .NF(SF), .OF(OF), .CF(CF), .IR_EN(IR_EN), .A_EN(A_EN), .B_EN(B_EN), .PDR_EN(PDR_EN), .PORT_EN(PORT_EN), .PORT_RD(PORT_RD), .PC_EN(PC_EN), .PC_LOAD(LOAD_EN), .ALU_EN(ALU_EN), .ALU_OE(ALU_OE), .RAM_OE(RAM_OE), .RDR_EN(RDR_EN), .RAM_CS(RAM_CS));
	
endmodule