data/full_repos/permissive/19818566/hardware/base_system/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog/goc_wrapper.v
 line:7: before: ")"
1: b"%Error: data/full_repos/permissive/19818566/hardware/base_system/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog/goc_wrapper.v:7: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: Exiting due to 1 error(s)\n"
module golden_circuit (
clk,
rst,
testVector,
resultVector,
);
input clk;
input rst;
input[31:0] testVector;
output[53:0] resultVector;
b14 toplevel_instance (
.clock(clk),
.reset(rst),
.addr(resultVector [19:0]),
.datai(testVector [31:0]),
.datao(resultVector [51:20]),
.rd(resultVector[52]),
.wr(resultVector[53]));
endmodule
module golden_circuit (
clk,
rst,
testVector,
resultVector,
);

input clk;
input rst;
input[31:0] testVector;
output[53:0] resultVector;
b14 toplevel_instance (
.clock(clk),
.reset(rst),
.addr(resultVector [19:0]),
.datai(testVector [31:0]),
.datao(resultVector [51:20]),
.rd(resultVector[52]),
.wr(resultVector[53]));
endmodule