data/full_repos/permissive/100975158/MIPS32_Full/Util/FIFO_Structure_Ahead.v
1: b"%Error: data/full_repos/permissive/100975158/MIPS32_Full/Util/FIFO_Structure_Ahead.v:16: Cannot find file containing module: 'dcfifo'\n    dcfifo #(\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100975158/MIPS32_Full/Util,data/full_repos/permissive/100975158/dcfifo\n             data/full_repos/permissive/100975158/MIPS32_Full/Util,data/full_repos/permissive/100975158/dcfifo.v\n             data/full_repos/permissive/100975158/MIPS32_Full/Util,data/full_repos/permissive/100975158/dcfifo.sv\n             dcfifo\n             dcfifo.v\n             dcfifo.sv\n             obj_dir/dcfifo\n             obj_dir/dcfifo.v\n             obj_dir/dcfifo.sv\n%Error: Exiting due to 1 error(s)\n"
module FIFO_Structure_Ahead (
    input               clock,
    input               write,
    input               read,
    input [7:0]         in_data,
    input               reset,

    output              full,
    output              empty,
    output [7:0]        out_data
);


    dcfifo #(
        .intended_device_family ("Cyclone IV"),
        .lpm_type               ("dcfifo"),
        .lpm_width              (8),
        .lpm_numwords           (16),
        .lpm_showahead          ("ON"),
        .overflow_checking      ("ON"),
        .underflow_checking     ("ON"),
        .clocks_are_synchronized("TRUE")
    ) FIFO (
        .rdclk                  (clock),
        .wrclk                  (clock),
        .data                   (in_data),
        .wrreq                  (write),
        .rdreq                  (read),
        .q                      (out_data),
        .rdempty                (empty),
        .wrfull                 (full),
        .aclr                   (reset)
    );

endmodule
module FIFO_Structure_Ahead (
    input               clock,
    input               write,
    input               read,
    input [7:0]         in_data,
    input               reset,

    output              full,
    output              empty,
    output [7:0]        out_data
);



    dcfifo #(
        .intended_device_family ("Cyclone IV"),
        .lpm_type               ("dcfifo"),
        .lpm_width              (8),
        .lpm_numwords           (16),
        .lpm_showahead          ("ON"),
        .overflow_checking      ("ON"),
        .underflow_checking     ("ON"),
        .clocks_are_synchronized("TRUE")
    ) FIFO (
        .rdclk                  (clock),
        .wrclk                  (clock),
        .data                   (in_data),
        .wrreq                  (write),
        .rdreq                  (read),
        .q                      (out_data),
        .rdempty                (empty),
        .wrfull                 (full),
        .aclr                   (reset)
    );

endmodule