data/full_repos/permissive/143278/ivltests/partselsynth.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/partselsynth.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (val !== 1\'b1) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/partselsynth.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (val !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/partselsynth.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (val !== 1\'b1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/partselsynth.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (val !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/partselsynth.v:53: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (val !== 1\'b1) begin\n      ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg enable, bar_a, bar_b, val_in;
   reg [7:0] scon;

   reg val;

   always @(val_in or bar_a or bar_b or scon[7:6] or enable)
     begin
	if (scon[7:6]==2'b10) begin
	   val = 1'b1;
	end else if (enable) begin
	   val = val_in;
	end else begin
	   val = !bar_b & bar_a;
	end
     end

   (* ivl_synthesis_off *)
   initial begin
      val_in = 0;
      enable = 0;
      bar_b = 0;
      bar_a = 0;
      scon = 8'b10_000000;

      #1 if (val !== 1'b1) begin
	 $display("FAILED -- scon=%b, val=%b", scon, val);
	 $finish;
      end

      scon = 0;
      enable = 1;
      #1 if (val !== 1'b0) begin
	 $display("FAILED -- scon=%b, enable=%b, val=%b", scon, enable, val);
	 $finish;
      end

      val_in = 1;
      #1 if (val !== 1'b1) begin
	 $display("FAILED -- scon=%b, enable=%b, val_in=%b, val=%b",
		  scon, enable, val_in, val);
	 $finish;
      end

      enable = 0;
      #1 if (val !== 1'b0) begin
	 $display("FAILED -- scon=%b, enable=%b, val=%b", scon, enable, val);
	 $finish;
      end

      bar_a = 1;
      #1 if (val !== 1'b1) begin
	 $display("FAILED -- scon=%b, enable=%b, bar_a==%b, bar_b=%b, val=%b",
		  scon, enable, bar_a, bar_b, val);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg enable, bar_a, bar_b, val_in;
   reg [7:0] scon;

   reg val;

   always @(val_in or bar_a or bar_b or scon[7:6] or enable)
     begin
	if (scon[7:6]==2'b10) begin
	   val = 1'b1;
	end else if (enable) begin
	   val = val_in;
	end else begin
	   val = !bar_b & bar_a;
	end
     end

   (* ivl_synthesis_off *)
   initial begin
      val_in = 0;
      enable = 0;
      bar_b = 0;
      bar_a = 0;
      scon = 8'b10_000000;

      #1 if (val !== 1'b1) begin
	 $display("FAILED -- scon=%b, val=%b", scon, val);
	 $finish;
      end

      scon = 0;
      enable = 1;
      #1 if (val !== 1'b0) begin
	 $display("FAILED -- scon=%b, enable=%b, val=%b", scon, enable, val);
	 $finish;
      end

      val_in = 1;
      #1 if (val !== 1'b1) begin
	 $display("FAILED -- scon=%b, enable=%b, val_in=%b, val=%b",
		  scon, enable, val_in, val);
	 $finish;
      end

      enable = 0;
      #1 if (val !== 1'b0) begin
	 $display("FAILED -- scon=%b, enable=%b, val=%b", scon, enable, val);
	 $finish;
      end

      bar_a = 1;
      #1 if (val !== 1'b1) begin
	 $display("FAILED -- scon=%b, enable=%b, bar_a==%b, bar_b=%b, val=%b",
		  scon, enable, bar_a, bar_b, val);
	 $finish;
      end

      $display("PASSED");
   end

endmodule