data/full_repos/permissive/210844779/lab2/2.1.2/decoder4x16.v
1: b'%Warning-WIDTH: data/full_repos/permissive/210844779/lab2/2.1.2/decoder4x16.v:8: Operator AND expects 16 bits on the LHS, but LHS\'s CONST \'15\'h1\' generates 15 bits.\n                                                                               : ... In instance decoder4x16\n  assign temp1= 15\'b01 & En;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab2/2.1.2/decoder4x16.v:8: Operator AND expects 16 bits on the RHS, but RHS\'s VARREF \'En\' generates 1 bits.\n                                                                               : ... In instance decoder4x16\n  assign temp1= 15\'b01 & En;\n                       ^\n%Error: Exiting due to 2 warning(s)\n'
module decoder4x16(A,En,Y);
  
  input [3:0]A;
  input En;
  output [15:0]Y;
  wire [15:0]temp,temp1;
  
  assign temp1= 15'b01 & En;
  assign temp=temp1 << A;
  assign Y= temp;
  
endmodule
module decoder4x16(A,En,Y);

  
  input [3:0]A;
  input En;
  output [15:0]Y;
  wire [15:0]temp,temp1;
  
  assign temp1= 15'b01 & En;
  assign temp=temp1 << A;
  assign Y= temp;
  
endmodule