data/full_repos/permissive/137738911/src/Max.v
data/verilator_xmls/fc3e059c-0989-4e4c-a2e5-7a324dc2ec89.xml
module Max#(
    parameter BITWIDTH = 8,
    parameter LENGTH = 4
    )
    (
    input [BITWIDTH * LENGTH - 1 : 0] data,
    output reg signed [BITWIDTH - 1 : 0] result
    );
    
    wire signed [BITWIDTH - 1:0] dataArray[0:LENGTH - 1];
    genvar i;
    generate      
        for(i = 0; i < LENGTH; i = i + 1) begin
            assign dataArray[i] = data[i * BITWIDTH + BITWIDTH - 1: i * BITWIDTH];
        end
    endgenerate
    
    integer j;
    always @(*) begin
        result = -127;
        for(j = 0; j < LENGTH; j = j + 1) begin
            if(dataArray[j] > result) begin
                result = dataArray[j];
            end
        end
    end
    
endmodule
module Max#(
    parameter BITWIDTH = 8,
    parameter LENGTH = 4
    )
    (
    input [BITWIDTH * LENGTH - 1 : 0] data,
    output reg signed [BITWIDTH - 1 : 0] result
    );

    
    wire signed [BITWIDTH - 1:0] dataArray[0:LENGTH - 1];
    genvar i;
    generate      
        for(i = 0; i < LENGTH; i = i + 1) begin
            assign dataArray[i] = data[i * BITWIDTH + BITWIDTH - 1: i * BITWIDTH];
        end
    endgenerate
    
    integer j;
    always @(*) begin
        result = -127;
        for(j = 0; j < LENGTH; j = j + 1) begin
            if(dataArray[j] > result) begin
                result = dataArray[j];
            end
        end
    end
    
endmodule