data/full_repos/permissive/20688874/zhiyang_and_andrew/nanosim/Files/cencoder.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/20688874/zhiyang_and_andrew/nanosim/Files/cencoder.v:15: Duplicate declaration of signal: 'c'\n                                                                                          : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n   reg [1:0]  c;\n              ^\n        data/full_repos/permissive/20688874/zhiyang_and_andrew/nanosim/Files/cencoder.v:11: ... Location of original declaration\nmodule conv_encoder (output [1:0] c, input b, input clk, input reset);\n                                  ^\n%Error: Exiting due to 1 error(s)\n"
module conv_encoder (output [1:0] c, input b, input clk, input reset);



   reg [1:0] 	c;
   reg		D_0, D_1;

   always @ (posedge clk)
	 begin
		if (reset)
		  begin
		    D_0 <= 1'b0;
		    D_1 <= 1'b0;
		  end
		if (b)
		  begin
		    D_1 <= D_0;
		    D_0 <= b;
		  end
	 end

   always @ (D_0 or D_1 or b)
	 begin
		c[0]  <= b^D_0^D_1;
		c[1]  <= b^D_1;
	 end

endmodule
module conv_encoder (output [1:0] c, input b, input clk, input reset);




   reg [1:0] 	c;
   reg		D_0, D_1;

   always @ (posedge clk)
	 begin
		if (reset)
		  begin
		    D_0 <= 1'b0;
		    D_1 <= 1'b0;
		  end
		if (b)
		  begin
		    D_1 <= D_0;
		    D_0 <= b;
		  end
	 end

   always @ (D_0 or D_1 or b)
	 begin
		c[0]  <= b^D_0^D_1;
		c[1]  <= b^D_1;
	 end

endmodule