data/full_repos/permissive/21716763/uncle_gates/tb_stimulus_gen.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_stimulus_gen.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #(PERIOD/2) clk = 1\'b1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_stimulus_gen.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #(PERIOD/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_stimulus_gen.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_stimulus_gen.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_stimulus_gen.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/21716763/uncle_gates/tb_stimulus_gen.v:45: Cannot find file containing module: \'stimulus_gen\'\n stimulus_gen \n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21716763/uncle_gates,data/full_repos/permissive/21716763/stimulus_gen\n             data/full_repos/permissive/21716763/uncle_gates,data/full_repos/permissive/21716763/stimulus_gen.v\n             data/full_repos/permissive/21716763/uncle_gates,data/full_repos/permissive/21716763/stimulus_gen.sv\n             stimulus_gen\n             stimulus_gen.v\n             stimulus_gen.sv\n             obj_dir/stimulus_gen\n             obj_dir/stimulus_gen.v\n             obj_dir/stimulus_gen.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_stimulus_gen;
	
	parameter PERIOD = 10;

	parameter INPUT_PORTS = 3;
	parameter RESET_PORT = 1;
	parameter RESET_SENS = 0;



	reg clk;
	wire [INPUT_PORTS-1:0] stm_value;
	wire rsb;
	wire gnt;

	reg rst;
	reg req;


	stimulus_gen 
	#(.INPUT_PORTS(INPUT_PORTS),
	.RESET_PORT(RESET_PORT),
	.RESET_SENS(RESET_SENS)
	)
	stimulus_gen (
		.clk(clk), 
		.rst(rst), 
		.req(req), 
		.stm_value(stm_value), 
		.rsb(rsb),
		.gnt(gnt)
	);
	

	always begin
		clk = 1'b0;
		#(PERIOD/2) clk = 1'b1;
		#(PERIOD/2);
	end  

	initial begin

		rst = 1;
		req = 0;


		#100;
      
		rst = 0;
		req = 0;		

		#100;
		req = 1;
		$display("<< Starting the Simulation >>");
		
		#100;
		req = 0;	
		


	end

endmodule
module tb_stimulus_gen;

	
	parameter PERIOD = 10;

	parameter INPUT_PORTS = 3;
	parameter RESET_PORT = 1;
	parameter RESET_SENS = 0;



	reg clk;
	wire [INPUT_PORTS-1:0] stm_value;
	wire rsb;
	wire gnt;

	reg rst;
	reg req;


	stimulus_gen 
	#(.INPUT_PORTS(INPUT_PORTS),
	.RESET_PORT(RESET_PORT),
	.RESET_SENS(RESET_SENS)
	)
	stimulus_gen (
		.clk(clk), 
		.rst(rst), 
		.req(req), 
		.stm_value(stm_value), 
		.rsb(rsb),
		.gnt(gnt)
	);
	

	always begin
		clk = 1'b0;
		#(PERIOD/2) clk = 1'b1;
		#(PERIOD/2);
	end  

	initial begin

		rst = 1;
		req = 0;


		#100;
      
		rst = 0;
		req = 0;		

		#100;
		req = 1;
		$display("<< Starting the Simulation >>");
		
		#100;
		req = 0;	
		


	end

endmodule