data/full_repos/permissive/168753118/rtl/misc/MUX_F.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:64: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b00000: data_wire = x00_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:65: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b00001: data_wire = x01_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:66: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b00010: data_wire = x02_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:67: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b00011: data_wire = x03_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:68: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b00100: data_wire = x04_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:69: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b00101: data_wire = x05_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:70: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b00110: data_wire = x06_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:71: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b00111: data_wire = x07_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:72: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b01000: data_wire = x08_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:73: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b01001: data_wire = x09_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:74: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b01010: data_wire = x10_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:75: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b01011: data_wire = x11_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:76: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b01100: data_wire = x12_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:77: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b01101: data_wire = x13_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:78: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b01110: data_wire = x14_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:79: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b01111: data_wire = x15_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:80: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b10000: data_wire = x16_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:81: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b10001: data_wire = x17_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:82: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b10010: data_wire = x18_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:83: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b10011: data_wire = x19_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:84: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b10100: data_wire = x20_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:85: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b10101: data_wire = x21_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:86: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b10110: data_wire = x22_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:87: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b10111: data_wire = x23_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:88: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b11000: data_wire = x24_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:89: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b11001: data_wire = x25_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:90: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b11010: data_wire = x26_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:91: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b11011: data_wire = x27_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:92: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b11100: data_wire = x28_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:93: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b11101: data_wire = x29_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:94: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b11110: data_wire = x30_data_in;\n              ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_F.v:95: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_F\n    5'b11111: data_wire = x31_data_in;\n              ^~~~~~~~~\n%Error: Exiting due to 32 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module MUX_F (

  input [4:0] mux_sel_in,

  input [31:0] x00_data_in,
  input [31:0] x01_data_in,
  input [31:0] x02_data_in,
  input [31:0] x03_data_in,
  input [31:0] x04_data_in,
  input [31:0] x05_data_in,
  input [31:0] x06_data_in,
  input [31:0] x07_data_in,
  input [31:0] x08_data_in,
  input [31:0] x09_data_in,
  input [31:0] x10_data_in,
  input [31:0] x11_data_in,
  input [31:0] x12_data_in,
  input [31:0] x13_data_in,
  input [31:0] x14_data_in,
  input [31:0] x15_data_in,
  input [31:0] x16_data_in,
  input [31:0] x17_data_in,
  input [31:0] x18_data_in,
  input [31:0] x19_data_in,
  input [31:0] x20_data_in,
  input [31:0] x21_data_in,
  input [31:0] x22_data_in,
  input [31:0] x23_data_in,
  input [31:0] x24_data_in,
  input [31:0] x25_data_in,
  input [31:0] x26_data_in,
  input [31:0] x27_data_in,
  input [31:0] x28_data_in,
  input [31:0] x29_data_in,
  input [31:0] x30_data_in,
  input [31:0] x31_data_in,

  output [31:0] x_data_out

);


wire [31:0] data_wire;

always @(*) begin
  case (mux_sel_in)
    5'b00000: data_wire = x00_data_in;
    5'b00001: data_wire = x01_data_in;
    5'b00010: data_wire = x02_data_in;
    5'b00011: data_wire = x03_data_in;
    5'b00100: data_wire = x04_data_in;
    5'b00101: data_wire = x05_data_in;
    5'b00110: data_wire = x06_data_in;
    5'b00111: data_wire = x07_data_in;
    5'b01000: data_wire = x08_data_in;
    5'b01001: data_wire = x09_data_in;
    5'b01010: data_wire = x10_data_in;
    5'b01011: data_wire = x11_data_in;
    5'b01100: data_wire = x12_data_in;
    5'b01101: data_wire = x13_data_in;
    5'b01110: data_wire = x14_data_in;
    5'b01111: data_wire = x15_data_in;
    5'b10000: data_wire = x16_data_in;
    5'b10001: data_wire = x17_data_in;
    5'b10010: data_wire = x18_data_in;
    5'b10011: data_wire = x19_data_in;
    5'b10100: data_wire = x20_data_in;
    5'b10101: data_wire = x21_data_in;
    5'b10110: data_wire = x22_data_in;
    5'b10111: data_wire = x23_data_in;
    5'b11000: data_wire = x24_data_in;
    5'b11001: data_wire = x25_data_in;
    5'b11010: data_wire = x26_data_in;
    5'b11011: data_wire = x27_data_in;
    5'b11100: data_wire = x28_data_in;
    5'b11101: data_wire = x29_data_in;
    5'b11110: data_wire = x30_data_in;
    5'b11111: data_wire = x31_data_in;
  endcase
end

assign x_data_out = data_wire;

endmodule
module MUX_F (

  input [4:0] mux_sel_in,

  input [31:0] x00_data_in,
  input [31:0] x01_data_in,
  input [31:0] x02_data_in,
  input [31:0] x03_data_in,
  input [31:0] x04_data_in,
  input [31:0] x05_data_in,
  input [31:0] x06_data_in,
  input [31:0] x07_data_in,
  input [31:0] x08_data_in,
  input [31:0] x09_data_in,
  input [31:0] x10_data_in,
  input [31:0] x11_data_in,
  input [31:0] x12_data_in,
  input [31:0] x13_data_in,
  input [31:0] x14_data_in,
  input [31:0] x15_data_in,
  input [31:0] x16_data_in,
  input [31:0] x17_data_in,
  input [31:0] x18_data_in,
  input [31:0] x19_data_in,
  input [31:0] x20_data_in,
  input [31:0] x21_data_in,
  input [31:0] x22_data_in,
  input [31:0] x23_data_in,
  input [31:0] x24_data_in,
  input [31:0] x25_data_in,
  input [31:0] x26_data_in,
  input [31:0] x27_data_in,
  input [31:0] x28_data_in,
  input [31:0] x29_data_in,
  input [31:0] x30_data_in,
  input [31:0] x31_data_in,

  output [31:0] x_data_out

);



wire [31:0] data_wire;

always @(*) begin
  case (mux_sel_in)
    5'b00000: data_wire = x00_data_in;
    5'b00001: data_wire = x01_data_in;
    5'b00010: data_wire = x02_data_in;
    5'b00011: data_wire = x03_data_in;
    5'b00100: data_wire = x04_data_in;
    5'b00101: data_wire = x05_data_in;
    5'b00110: data_wire = x06_data_in;
    5'b00111: data_wire = x07_data_in;
    5'b01000: data_wire = x08_data_in;
    5'b01001: data_wire = x09_data_in;
    5'b01010: data_wire = x10_data_in;
    5'b01011: data_wire = x11_data_in;
    5'b01100: data_wire = x12_data_in;
    5'b01101: data_wire = x13_data_in;
    5'b01110: data_wire = x14_data_in;
    5'b01111: data_wire = x15_data_in;
    5'b10000: data_wire = x16_data_in;
    5'b10001: data_wire = x17_data_in;
    5'b10010: data_wire = x18_data_in;
    5'b10011: data_wire = x19_data_in;
    5'b10100: data_wire = x20_data_in;
    5'b10101: data_wire = x21_data_in;
    5'b10110: data_wire = x22_data_in;
    5'b10111: data_wire = x23_data_in;
    5'b11000: data_wire = x24_data_in;
    5'b11001: data_wire = x25_data_in;
    5'b11010: data_wire = x26_data_in;
    5'b11011: data_wire = x27_data_in;
    5'b11100: data_wire = x28_data_in;
    5'b11101: data_wire = x29_data_in;
    5'b11110: data_wire = x30_data_in;
    5'b11111: data_wire = x31_data_in;
  endcase
end

assign x_data_out = data_wire;

endmodule