data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp
 line:14: before: "input"
1: b"%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:8: Define or directive not defined: '`mname'\nmodule `mname` (\n       ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:8: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule `mname` (\n             ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:21: Unsupported or unknown PLI call: $DataWidth\ninput [`$DataWidth - 1`:0] data_in,         \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:23: Unsupported or unknown PLI call: $DataWidth\ninput [`$DataWidth - 1`:0] data_out_sel,    \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:29: Unsupported or unknown PLI call: $DataWidth\noutput [`$DataWidth -1`:0] data_out      \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:39: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\nlogic [`$DataWidth -1`:0] shift_registers [`$SHIFT_REG_LEN -1`:0];  \n       ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:39: Unsupported or unknown PLI call: $DataWidth\nlogic [`$DataWidth -1`:0] shift_registers [`$SHIFT_REG_LEN -1`:0];  \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:39: Unsupported or unknown PLI call: $SHIFT_REG_LEN\nlogic [`$DataWidth -1`:0] shift_registers [`$SHIFT_REG_LEN -1`:0];  \n                                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:40: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\nlogic [`$DataWidth- 1`:0] data_out_int;\n       ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:40: Unsupported or unknown PLI call: $DataWidth\nlogic [`$DataWidth- 1`:0] data_out_int;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:48: Unsupported or unknown PLI call: $SHIFT_REG_LEN\n  for (i = 1; i < `$SHIFT_REG_LEN`; i = i + 1) begin : GEN_SHIFT_REG\n                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:83: Number is missing value digits: 8'h\n        8'h`$i` : data_out_int = shift_registers[`$i-1`];\n        ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:83: Unsupported or unknown PLI call: $i\n        8'h`$i` : data_out_int = shift_registers[`$i-1`];\n            ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/memory_tile/mem_shift_reg.svp:83: Unsupported or unknown PLI call: $i\n        8'h`$i` : data_out_int = shift_registers[`$i-1`];\n                                                  ^~\n%Error: Exiting due to 14 error(s)\n"
module `mname` (





input clk,

input rst_n,




input [`$DataWidth - 1`:0] data_in,

input [`$DataWidth - 1`:0] data_out_sel,
input        shift,




output [`$DataWidth -1`:0] data_out

);


assign data_out = data_in;




logic [`$DataWidth -1`:0] shift_registers [`$SHIFT_REG_LEN -1`:0];
logic [`$DataWidth- 1`:0] data_out_int;





genvar i;
generate
  for (i = 1; i < `$SHIFT_REG_LEN`; i = i + 1) begin : GEN_SHIFT_REG
    always_ff @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
        shift_registers[i] <= 'h0;
      end else if(shift) begin
        shift_registers[i] <= shift_registers[i-1];
      end
    end
  end
endgenerate





always_ff @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
     shift_registers[0] <= 'h0;
  end else if(shift) begin
     shift_registers[0] <= data_in;
  end
end









always_comb begin: proc_mux
    case (sel)
        8'h0 : data_out_int = data_in;

        8'h`$i` : data_out_int = shift_registers[`$i-1`];

        default : data_out_int = data_in;
    endcase
end

assign data_out = data_out_int;



endmodule
module `mname` (





input clk,

input rst_n,




input [`$DataWidth - 1`:0] data_in,

input [`$DataWidth - 1`:0] data_out_sel,
input        shift,




output [`$DataWidth -1`:0] data_out

);



assign data_out = data_in;




logic [`$DataWidth -1`:0] shift_registers [`$SHIFT_REG_LEN -1`:0];
logic [`$DataWidth- 1`:0] data_out_int;





genvar i;
generate
  for (i = 1; i < `$SHIFT_REG_LEN`; i = i + 1) begin : GEN_SHIFT_REG
    always_ff @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
        shift_registers[i] <= 'h0;
      end else if(shift) begin
        shift_registers[i] <= shift_registers[i-1];
      end
    end
  end
endgenerate





always_ff @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
     shift_registers[0] <= 'h0;
  end else if(shift) begin
     shift_registers[0] <= data_in;
  end
end









always_comb begin: proc_mux
    case (sel)
        8'h0 : data_out_int = data_in;

        8'h`$i` : data_out_int = shift_registers[`$i-1`];

        default : data_out_int = data_in;
    endcase
end

assign data_out = data_out_int;



endmodule