data/full_repos/permissive/151904248/Triple Buffer/triple_controller.v
 line:116: before: "("
1: b'%Error: Cannot find file containing module: Buffer,data/full_repos/permissive/151904248\n        ... Looked in:\n             data/full_repos/permissive/151904248/Triple/Buffer,data/full_repos/permissive/151904248\n             data/full_repos/permissive/151904248/Triple/Buffer,data/full_repos/permissive/151904248.v\n             data/full_repos/permissive/151904248/Triple/Buffer,data/full_repos/permissive/151904248.sv\n             Buffer,data/full_repos/permissive/151904248\n             Buffer,data/full_repos/permissive/151904248.v\n             Buffer,data/full_repos/permissive/151904248.sv\n             obj_dir/Buffer,data/full_repos/permissive/151904248\n             obj_dir/Buffer,data/full_repos/permissive/151904248.v\n             obj_dir/Buffer,data/full_repos/permissive/151904248.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/151904248/Triple\n%Error: Cannot find file containing module: Buffer/triple_controller.v\n%Error: Exiting due to 3 error(s)\n'
module tri_control
#(
parameter wait_cycles = 0,
parameter TRANS_ACTIVE = 0,
parameter CAP_ACTIVE = 1
)
(
input wire clk,
input wire reset,
input wire capture_trigger,
input wire transmission_trigger,
output reg [2:0] sram_select,
output reg error
);


wire [2:0] sram_int_select;

localparam [1:0] state_first_wait = 2'b00,
			  state_switch = 2'b01,
			  state_second_wait = 2'b10;


localparam [1:0] X = 2'b00, 
					  Y = 2'b01,
					  Z = 2'b10;
					  

localparam [2:0] A = 3'b000,
					  B = 3'b001,
					  C = 3'b010,
					  D = 3'b011,
					  E = 3'b100,
					  F = 3'b101;
					  
reg [1:0] camera_buff;
reg [1:0] vga_buff;




reg [1:0] x_cnt;
reg [1:0] y_cnt;
reg [1:0] z_cnt;


reg [1:0] cap_state;
reg [1:0] trans_state;

reg [5:0] cap_count;
reg [5:0] trans_count;


			  
initial begin
	camera_buff <= X;
	vga_buff <= Y;
	sram_select <= A;
	error <= 1'b0;
	
	x_cnt <= 2'b0;
	y_cnt <= 2'b0;
	z_cnt <= 2'b0;
	
	cap_state = state_first_wait;
	trans_state = state_first_wait;
	
	cap_count = 0;
	trans_count = 0;

end


always @ (posedge clk) begin

	case(cap_state)
		
		state_first_wait: begin

			if(capture_trigger == CAP_ACTIVE) begin
				if(cap_count >= wait_cycles) begin
					cap_count <= 0;
					cap_state <= state_switch;
				end
				else begin
					cap_count <= cap_count + 1'b1;
				end
			end

			else begin
				cap_count <= 0;
			end
		
		end
	
		state_switch: begin

			cap_switch();

			cap_state <= state_second_wait;
		end
		
		state_second_wait: begin

			if(capture_trigger != CAP_ACTIVE) begin
				cap_state <= state_first_wait;
			end
		end
		
		default: begin
			cap_state <= state_first_wait;
		end
		
	endcase
end



always @ (posedge clk) begin

	case(trans_state)
		
		state_first_wait: begin

			if(transmission_trigger == TRANS_ACTIVE) begin
				if(trans_count >= wait_cycles) begin
					trans_count <= 0;
					trans_state <= state_switch;
				end
				else begin
					trans_count <= trans_count + 1'b1;
				end
			end

			else begin
				trans_count <= 0;
			end
		
		end
	
		state_switch: begin

			trans_switch();

			trans_state <= state_second_wait;
		end
		
		state_second_wait: begin

			if(transmission_trigger != TRANS_ACTIVE) begin
				
				trans_state <= state_first_wait;
			end
		end
		
		default: begin
			trans_state <= state_first_wait;
		end
		
	endcase
end


task cap_switch;
begin

case(vga_buff)
		
			X: begin
				if(camera_buff == Y) begin
					camera_buff <= Z;
					z_cnt <= 2'b0;
					x_cnt <= x_cnt + 1'b1;
					y_cnt <= y_cnt + 1'b1;
				end
				else begin
					camera_buff <= Y;
					y_cnt <= 2'b0;
					x_cnt <= x_cnt + 1'b1;
					z_cnt <= z_cnt + 1'b1;
				end
			end
			
			Y: begin
				if(camera_buff == Z) begin
					camera_buff <= X;
					x_cnt <= 2'b0;
					z_cnt <= z_cnt + 1'b1;
					y_cnt <= y_cnt + 1'b1;
				end
				else begin
					camera_buff <= Z;
					z_cnt <= 2'b0;
					x_cnt <= x_cnt + 1'b1;
					y_cnt <= y_cnt + 1'b1;
				end
			end
			
			Z: begin
				if(camera_buff == X) begin
					camera_buff <= Y;
					y_cnt <= 2'b0;
					x_cnt <= x_cnt + 1'b1;
					z_cnt <= z_cnt + 1'b1;
				end
				else begin
					camera_buff <= X;
					x_cnt <= 2'b0;
					z_cnt <= z_cnt + 1'b1;
					y_cnt <= y_cnt + 1'b1;
				end
			end
			
			default begin
				camera_buff <= X;
				x_cnt <= 2'b0;
				z_cnt <= z_cnt + 1'b1;
				y_cnt <= y_cnt + 1'b1;
			end
			
		endcase

end
endtask


task trans_switch;
begin

	case(camera_buff)
	
		X: begin
			if(vga_buff == Y && z_cnt < 2) begin
				vga_buff <= Z;
			end
			else if(y_cnt < 2) begin
				vga_buff <= Y;
			end
		end
		
		Y: begin
			if(vga_buff == Z && x_cnt < 2) begin
				vga_buff <= X;
			end
			else if(z_cnt < 2) begin
				vga_buff <= Z;
			end
		end
		
		Z: begin
			if(vga_buff == X && y_cnt < 2) begin
				vga_buff <= Y;
			end
			else if(x_cnt < 2) begin
				vga_buff <= X;
			end
		end
		
		default begin
			vga_buff <= Y;
		end
		
	endcase

end
endtask



always @ (posedge clk) begin


	if(capture_trigger == CAP_ACTIVE || transmission_trigger == TRANS_ACTIVE) begin
		sram_select <= sram_int_select;
	end

end

assign sram_int_select = (camera_buff == X && vga_buff == Y) ? A : 
						((camera_buff == X && vga_buff == Z) ? B :
						((camera_buff == Y && vga_buff == X) ? C :
						((camera_buff == Y && vga_buff == Z) ? D :
						((camera_buff == Z && vga_buff == X) ? E : F))));


endmodule
module tri_control
#(
parameter wait_cycles = 0,
parameter TRANS_ACTIVE = 0,
parameter CAP_ACTIVE = 1
)
(
input wire clk,
input wire reset,
input wire capture_trigger,
input wire transmission_trigger,
output reg [2:0] sram_select,
output reg error
);



wire [2:0] sram_int_select;

localparam [1:0] state_first_wait = 2'b00,
			  state_switch = 2'b01,
			  state_second_wait = 2'b10;


localparam [1:0] X = 2'b00, 
					  Y = 2'b01,
					  Z = 2'b10;
					  

localparam [2:0] A = 3'b000,
					  B = 3'b001,
					  C = 3'b010,
					  D = 3'b011,
					  E = 3'b100,
					  F = 3'b101;
					  
reg [1:0] camera_buff;
reg [1:0] vga_buff;




reg [1:0] x_cnt;
reg [1:0] y_cnt;
reg [1:0] z_cnt;


reg [1:0] cap_state;
reg [1:0] trans_state;

reg [5:0] cap_count;
reg [5:0] trans_count;


			  
initial begin
	camera_buff <= X;
	vga_buff <= Y;
	sram_select <= A;
	error <= 1'b0;
	
	x_cnt <= 2'b0;
	y_cnt <= 2'b0;
	z_cnt <= 2'b0;
	
	cap_state = state_first_wait;
	trans_state = state_first_wait;
	
	cap_count = 0;
	trans_count = 0;

end


always @ (posedge clk) begin

	case(cap_state)
		
		state_first_wait: begin

			if(capture_trigger == CAP_ACTIVE) begin
				if(cap_count >= wait_cycles) begin
					cap_count <= 0;
					cap_state <= state_switch;
				end
				else begin
					cap_count <= cap_count + 1'b1;
				end
			end

			else begin
				cap_count <= 0;
			end
		
		end
	
		state_switch: begin

			cap_switch();

			cap_state <= state_second_wait;
		end
		
		state_second_wait: begin

			if(capture_trigger != CAP_ACTIVE) begin
				cap_state <= state_first_wait;
			end
		end
		
		default: begin
			cap_state <= state_first_wait;
		end
		
	endcase
end



always @ (posedge clk) begin

	case(trans_state)
		
		state_first_wait: begin

			if(transmission_trigger == TRANS_ACTIVE) begin
				if(trans_count >= wait_cycles) begin
					trans_count <= 0;
					trans_state <= state_switch;
				end
				else begin
					trans_count <= trans_count + 1'b1;
				end
			end

			else begin
				trans_count <= 0;
			end
		
		end
	
		state_switch: begin

			trans_switch();

			trans_state <= state_second_wait;
		end
		
		state_second_wait: begin

			if(transmission_trigger != TRANS_ACTIVE) begin
				
				trans_state <= state_first_wait;
			end
		end
		
		default: begin
			trans_state <= state_first_wait;
		end
		
	endcase
end


task cap_switch;
begin

case(vga_buff)
		
			X: begin
				if(camera_buff == Y) begin
					camera_buff <= Z;
					z_cnt <= 2'b0;
					x_cnt <= x_cnt + 1'b1;
					y_cnt <= y_cnt + 1'b1;
				end
				else begin
					camera_buff <= Y;
					y_cnt <= 2'b0;
					x_cnt <= x_cnt + 1'b1;
					z_cnt <= z_cnt + 1'b1;
				end
			end
			
			Y: begin
				if(camera_buff == Z) begin
					camera_buff <= X;
					x_cnt <= 2'b0;
					z_cnt <= z_cnt + 1'b1;
					y_cnt <= y_cnt + 1'b1;
				end
				else begin
					camera_buff <= Z;
					z_cnt <= 2'b0;
					x_cnt <= x_cnt + 1'b1;
					y_cnt <= y_cnt + 1'b1;
				end
			end
			
			Z: begin
				if(camera_buff == X) begin
					camera_buff <= Y;
					y_cnt <= 2'b0;
					x_cnt <= x_cnt + 1'b1;
					z_cnt <= z_cnt + 1'b1;
				end
				else begin
					camera_buff <= X;
					x_cnt <= 2'b0;
					z_cnt <= z_cnt + 1'b1;
					y_cnt <= y_cnt + 1'b1;
				end
			end
			
			default begin
				camera_buff <= X;
				x_cnt <= 2'b0;
				z_cnt <= z_cnt + 1'b1;
				y_cnt <= y_cnt + 1'b1;
			end
			
		endcase

end
endtask


task trans_switch;
begin

	case(camera_buff)
	
		X: begin
			if(vga_buff == Y && z_cnt < 2) begin
				vga_buff <= Z;
			end
			else if(y_cnt < 2) begin
				vga_buff <= Y;
			end
		end
		
		Y: begin
			if(vga_buff == Z && x_cnt < 2) begin
				vga_buff <= X;
			end
			else if(z_cnt < 2) begin
				vga_buff <= Z;
			end
		end
		
		Z: begin
			if(vga_buff == X && y_cnt < 2) begin
				vga_buff <= Y;
			end
			else if(x_cnt < 2) begin
				vga_buff <= X;
			end
		end
		
		default begin
			vga_buff <= Y;
		end
		
	endcase

end
endtask



always @ (posedge clk) begin


	if(capture_trigger == CAP_ACTIVE || transmission_trigger == TRANS_ACTIVE) begin
		sram_select <= sram_int_select;
	end

end

assign sram_int_select = (camera_buff == X && vga_buff == Y) ? A : 
						((camera_buff == X && vga_buff == Z) ? B :
						((camera_buff == Y && vga_buff == X) ? C :
						((camera_buff == Y && vga_buff == Z) ? D :
						((camera_buff == Z && vga_buff == X) ? E : F))));


endmodule