data/full_repos/permissive/157135695/lab4_test.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:93: Unsupported: Ignoring delay on this delayed statement.\n      #50\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #50000 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:120: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:122: Unsupported: Ignoring delay on this delayed statement.\n    #400\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:124: Unsupported: Ignoring delay on this delayed statement.\n    #1400\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:126: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:128: Unsupported: Ignoring delay on this delayed statement.\n    #1800\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:130: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #1800\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:136: Unsupported: Ignoring delay on this delayed statement.\n    #1800\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:138: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:140: Unsupported: Ignoring delay on this delayed statement.\n    #1800\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:142: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #1800\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:148: Unsupported: Ignoring delay on this delayed statement.\n    #1800\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:150: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:152: Unsupported: Ignoring delay on this delayed statement.\n    #1800\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157135695/lab4_test.v:154: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Error: data/full_repos/permissive/157135695/lab4_test.v:228: Unsupported or unknown PLI call: $monitor\n    $monitor("MSIM> --> PC_EN = %1d at time = %1d (ignore until Part C)\\nMSIM> ", PC_EN, $time);\n    ^~~~~~~~\n%Error: Exiting due to 1 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function [7:0] read_mem(input [7:0] DataD);
    begin
      if(DataD === 8'd249) begin
        read_mem = IOA;
        $display("MSIM> --> INPUT on IOA of %2h", IOA);
      end
      else if(DataD === 8'd250) begin
        read_mem = IOB;
        $display("MSIM> --> INPUT on IOB of %2h", IOB);
      end
      else if(DataD === 8'd251) begin
        read_mem = IOC;
        $display("MSIM> --> INPUT on IOC of %2h", IOC);
      end
      else begin
        read_mem = sdmem[DataD];
        $display("MSIM> --> Reading %2h from data RAM address %3d", read_mem, DataD);
      end
    end
  endfunction
function [7:0] read_mem(input [7:0] DataD);

    begin
      if(DataD === 8'd249) begin
        read_mem = IOA;
        $display("MSIM> --> INPUT on IOA of %2h", IOA);
      end
      else if(DataD === 8'd250) begin
        read_mem = IOB;
        $display("MSIM> --> INPUT on IOB of %2h", IOB);
      end
      else if(DataD === 8'd251) begin
        read_mem = IOC;
        $display("MSIM> --> INPUT on IOC of %2h", IOC);
      end
      else begin
        read_mem = sdmem[DataD];
        $display("MSIM> --> Reading %2h from data RAM address %3d", read_mem, DataD);
      end
    end
  endfunction