data/full_repos/permissive/188434311/verilog/qsch/sch/sp_fixed_arbiter.v
 line:7: before: ";"
1: b'%Error: data/full_repos/permissive/188434311/verilog/qsch/sch/sp_fixed_arbiter.v:1: Cannot find include file: sp_fixed_arbiter_defs.vh\n`include "sp_fixed_arbiter_defs.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188434311/verilog/qsch/sch,data/full_repos/permissive/188434311/sp_fixed_arbiter_defs.vh\n             data/full_repos/permissive/188434311/verilog/qsch/sch,data/full_repos/permissive/188434311/sp_fixed_arbiter_defs.vh.v\n             data/full_repos/permissive/188434311/verilog/qsch/sch,data/full_repos/permissive/188434311/sp_fixed_arbiter_defs.vh.sv\n             sp_fixed_arbiter_defs.vh\n             sp_fixed_arbiter_defs.vh.v\n             sp_fixed_arbiter_defs.vh.sv\n             obj_dir/sp_fixed_arbiter_defs.vh\n             obj_dir/sp_fixed_arbiter_defs.vh.v\n             obj_dir/sp_fixed_arbiter_defs.vh.sv\n%Error: data/full_repos/permissive/188434311/verilog/qsch/sch/sp_fixed_arbiter.v:4: syntax error, unexpected \';\', expecting \')\' or \',\'\n    parameter REQ_NUMB      = 4;\n                               ^\n%Error: data/full_repos/permissive/188434311/verilog/qsch/sch/sp_fixed_arbiter.v:7: Define or directive not defined: \'`RS_REGD\'\n    parameter REQ_MODE      = `RS_REGD;\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/188434311/verilog/qsch/sch/sp_fixed_arbiter.v:7: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    parameter REQ_MODE      = `RS_REGD;\n                                      ^\n%Error: Exiting due to 4 error(s)\n'
module sp_fixed_arbiter
#(
    parameter REQ_NUMB      = 4;
    parameter ID_BITWIDTH   = 2;
    parameter DATA_BITWIDTH = 10;
    parameter REQ_MODE      = `RS_REGD;
)
(
    input                           sys_clk,
    input                           rst_n,
    input  [REQ_NUMB - 1 : 0]       RxVld,
    input  [DATA_BITWIDTH - 1 : 0]  RxData[REQ_NUMB - 1 : 0],
    output [REQ_NUMB - 1 : 0]       RxRdy,

    output                          TxVld,
    output [DATA_BITWIDTH - 1 : 0]  TxData,
    output [ID_BITWIDTH - 1 : 0]    TxPortId,
    input                           TxRdy
);



endmodule
module sp_fixed_arbiter
#(
    parameter REQ_NUMB      = 4;

    parameter ID_BITWIDTH   = 2;
    parameter DATA_BITWIDTH = 10;
    parameter REQ_MODE      = `RS_REGD;
)
(
    input                           sys_clk,
    input                           rst_n,
    input  [REQ_NUMB - 1 : 0]       RxVld,
    input  [DATA_BITWIDTH - 1 : 0]  RxData[REQ_NUMB - 1 : 0],
    output [REQ_NUMB - 1 : 0]       RxRdy,

    output                          TxVld,
    output [DATA_BITWIDTH - 1 : 0]  TxData,
    output [ID_BITWIDTH - 1 : 0]    TxPortId,
    input                           TxRdy
);



endmodule