data/full_repos/permissive/14635275/src/lvds_clockgen.v
None: at end of input
1: b'%Warning-IMPLICIT: data/full_repos/permissive/14635275/src/lvds_clockgen.v:55: Signal definition not found, creating implicitly: \'not_clk_lckd\'\n                                                                             : ... Suggested alternative: \'clk_lckd\'\nassign not_clk_lckd = ~clk_lckd ;\n       ^~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/14635275/src/lvds_clockgen.v:69: Signal definition not found, creating implicitly: \'rst_clk\'\n                                                                             : ... Suggested alternative: \'rstclk\'\nassign rstclk = rst_clk;\n                ^~~~~~~\n%Error: data/full_repos/permissive/14635275/src/lvds_clockgen.v:28: Cannot find file containing module: \'DCM_SP\'\nDCM_SP #(.CLKIN_PERIOD ("15.625"),\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14635275/src,data/full_repos/permissive/14635275/DCM_SP\n             data/full_repos/permissive/14635275/src,data/full_repos/permissive/14635275/DCM_SP.v\n             data/full_repos/permissive/14635275/src,data/full_repos/permissive/14635275/DCM_SP.sv\n             DCM_SP\n             DCM_SP.v\n             DCM_SP.sv\n             obj_dir/DCM_SP\n             obj_dir/DCM_SP.v\n             obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/14635275/src/lvds_clockgen.v:53: Cannot find file containing module: \'BUFG\'\nBUFG  clk_bufg (.I(clkdcm),   .O(clo) ) ;\n^~~~\n%Error: data/full_repos/permissive/14635275/src/lvds_clockgen.v:57: Cannot find file containing module: \'FDP\'\nFDP fd_rst_clk (.D(not_clk_lckd), .C(clo), .Q(rst_clk)) ;\n^~~\n%Error: data/full_repos/permissive/14635275/src/lvds_clockgen.v:60: Cannot find file containing module: \'serializer\'\nserializer lvdsclkman (\n^~~~~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module lvds_clockgen(
    input clk,
    output clk35,
    output nclk35,
	 output rstclk,
	 output dataclock,
    output lvdsclk
    );
	 



wire clk_lckd;
wire clkdcm;
wire clo;

DCM_SP #(.CLKIN_PERIOD	("15.625"),
	.DESKEW_ADJUST	("0"),	
	.CLKFX_MULTIPLY	(7),
	.CLKFX_DIVIDE	(2))	
dcm_clk (
	.CLKIN   	(clk),
	.CLKFB   	(clo),
	.RST     	(1'b0),
	.CLK0    	(clkdcm),
	.CLKFX   	(clk35),
	.CLKFX180	(nclk35),
	.CLK180		(),
	.CLK270		(),
	.CLK2X		(),
	.CLK2X180	(),
	.CLK90		(),
	.CLKDV		(),
	.PSDONE		(),
	.STATUS		(),
	.DSSEN 		(1'b0),
	.PSINCDEC	(1'b0),
	.PSEN 		(1'b0),
	.PSCLK 		(1'b0),
	.LOCKED  	(clk_lckd)) ;
	
BUFG 	clk_bufg	(.I(clkdcm), 		.O(clo) ) ;

assign not_clk_lckd = ~clk_lckd ;

FDP fd_rst_clk (.D(not_clk_lckd), .C(clo), .Q(rst_clk)) ;


serializer lvdsclkman (
    .clk(clo), 
    .clk35(clk35), 
    .notclk35(nclk35), 
    .data(7'b1100011),
	 .rst(rst_clk),
	 .out(lvdsclk)
    ); 

assign rstclk = rst_clk;
assign dataclock = clo;
endmodule
module lvds_clockgen(
    input clk,
    output clk35,
    output nclk35,
	 output rstclk,
	 output dataclock,
    output lvdsclk
    );

	 



wire clk_lckd;
wire clkdcm;
wire clo;

DCM_SP #(.CLKIN_PERIOD	("15.625"),
	.DESKEW_ADJUST	("0"),	
	.CLKFX_MULTIPLY	(7),
	.CLKFX_DIVIDE	(2))	
dcm_clk (
	.CLKIN   	(clk),
	.CLKFB   	(clo),
	.RST     	(1'b0),
	.CLK0    	(clkdcm),
	.CLKFX   	(clk35),
	.CLKFX180	(nclk35),
	.CLK180		(),
	.CLK270		(),
	.CLK2X		(),
	.CLK2X180	(),
	.CLK90		(),
	.CLKDV		(),
	.PSDONE		(),
	.STATUS		(),
	.DSSEN 		(1'b0),
	.PSINCDEC	(1'b0),
	.PSEN 		(1'b0),
	.PSCLK 		(1'b0),
	.LOCKED  	(clk_lckd)) ;
	
BUFG 	clk_bufg	(.I(clkdcm), 		.O(clo) ) ;

assign not_clk_lckd = ~clk_lckd ;

FDP fd_rst_clk (.D(not_clk_lckd), .C(clo), .Q(rst_clk)) ;


serializer lvdsclkman (
    .clk(clo), 
    .clk35(clk35), 
    .notclk35(nclk35), 
    .data(7'b1100011),
	 .rst(rst_clk),
	 .out(lvdsclk)
    ); 

assign rstclk = rst_clk;
assign dataclock = clo;
endmodule