data/full_repos/permissive/206670486/Modulos/ALU.v
data/verilator_xmls/71a183f1-8436-4868-8686-0357f33d5b6a.xml
module ALU (controle,ALUIN_A,ALUIN_B,zero,saida);
  input wire [3:0]controle;
  input wire [31:0]ALUIN_A;
  input wire [31:0]ALUIN_B;
  output reg [31:0]saida;
  output zero;
  
  always @ (*) begin
    case (controle)
      `ALU_ADD: saida <= ALUIN_A + ALUIN_B;
      `ALU_SUB: saida <= ALUIN_A - ALUIN_B;
      `ALU_AND: saida <= ALUIN_A & ALUIN_B;
      `ALU_OR:  saida <= ALUIN_A | ALUIN_B;
      `ALU_NOR: saida <= ~(ALUIN_A | ALUIN_B);
      `ALU_XOR: saida <= ALUIN_A ^ ALUIN_B;
      `ALU_SLT: saida <= ALUIN_A < ALUIN_B ? 1 : 0;
      default: saida <= 0;
    endcase
  end
  assign zero = (saida == 0);
endmodule
module ALU (controle,ALUIN_A,ALUIN_B,zero,saida);

  input wire [3:0]controle;
  input wire [31:0]ALUIN_A;
  input wire [31:0]ALUIN_B;
  output reg [31:0]saida;
  output zero;
  
  always @ (*) begin
    case (controle)
      `ALU_ADD: saida <= ALUIN_A + ALUIN_B;
      `ALU_SUB: saida <= ALUIN_A - ALUIN_B;
      `ALU_AND: saida <= ALUIN_A & ALUIN_B;
      `ALU_OR:  saida <= ALUIN_A | ALUIN_B;
      `ALU_NOR: saida <= ~(ALUIN_A | ALUIN_B);
      `ALU_XOR: saida <= ALUIN_A ^ ALUIN_B;
      `ALU_SLT: saida <= ALUIN_A < ALUIN_B ? 1 : 0;
      default: saida <= 0;
    endcase
  end
  assign zero = (saida == 0);
endmodule