data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Reciprocal/Reciprocal_Pipelined.v
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1: b'%Error: Cannot find file containing module: Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Reciprocal/Reciprocal_Pipelined.v\n%Error: Exiting due to 3 error(s)\n'
module Reciprocal_Pipelined_NR

		#(parameter 	

						WL = 24,
						LUT_bits = 15,
						LUT_addWidth = 12,
						dWL = 26,
						WLO = 24
		 ) 		

		(
			input CLK,
			input nRST,
			input CE,
			
			input [WL-1:0] din,

			output [WLO-1:0] dout
		);
			

		reg  [LUT_bits-1 : 0]     LUT [2**LUT_addWidth-1 : 0];
		reg  [LUT_bits-1 : 0]	  iniValue;
		wire [LUT_addWidth-1:0]   reg_cmp;
		reg  [WL-1:0] 				  din_delay;
		reg  [LUT_bits-1 : 0] 	  iniValue_delay;
		reg  [LUT_bits-1 : 0] 	  iniValue_delay2;
		reg  [LUT_bits-1 : 0] 	  iniValue_delay3;

		wire [dWL-1 :0]   		  mul1_net;
		reg  [dWL-1 :0]   		  mul_1_r;
		wire [dWL+LUT_bits-1:0]	  mul2_net;







		assign reg_cmp = din[WL-2 : WL-1-LUT_addWidth];
		always @(posedge CLK) begin
			if(~nRST) begin
					iniValue <= 0;
					mul_1_r <= 0;
					din_delay <= 0;
					iniValue_delay3 <= 0;
					iniValue_delay2 <= 0;
					iniValue_delay <= 0;

			end
			else begin
				if (CE) begin

					din_delay <= din;
					iniValue_delay <= iniValue;
					iniValue_delay2 <= iniValue_delay;
					iniValue_delay3 <= iniValue_delay2;
					iniValue <= LUT[reg_cmp];
					mul_1_r <= ~mul1_net;
				end
			end
		end


mult_unsigned_pipe #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(LUT_bits-1), .WIO(1), .WFO(dWL-1)) multiplier_1 
						  (.CLK(CLK), .RST(nRST), .in1(din_delay), .in2(iniValue), .out(mul1_net));
						  

mult_unsigned_pipe #(.WI1(1), .WF1(dWL-1), .WI2(1), .WF2(LUT_bits-1), .WIO(1), .WFO(dWL+LUT_bits-1)) multiplier_2 
						  (.CLK(CLK), .RST(nRST), .in1(mul_1_r), .in2(iniValue_delay3), .out(mul2_net));


		ux_round2nearest
			#(
				.WordLength(dWL+LUT_bits),
				.RoundLength(dWL+LUT_bits-WLO)
			 )
		round_0 
			(
				.CLK(CLK),
				.RESET(nRST),
				.CE(CE),
				.x(mul2_net),
				.y(dout)
			 );
endmodule
module Reciprocal_Pipelined_NR

		#(parameter 	

						WL = 24,
						LUT_bits = 15,
						LUT_addWidth = 12,
						dWL = 26,
						WLO = 24
		 ) 		

		(
			input CLK,
			input nRST,
			input CE,
			
			input [WL-1:0] din,

			output [WLO-1:0] dout
		);

			

		reg  [LUT_bits-1 : 0]     LUT [2**LUT_addWidth-1 : 0];
		reg  [LUT_bits-1 : 0]	  iniValue;
		wire [LUT_addWidth-1:0]   reg_cmp;
		reg  [WL-1:0] 				  din_delay;
		reg  [LUT_bits-1 : 0] 	  iniValue_delay;
		reg  [LUT_bits-1 : 0] 	  iniValue_delay2;
		reg  [LUT_bits-1 : 0] 	  iniValue_delay3;

		wire [dWL-1 :0]   		  mul1_net;
		reg  [dWL-1 :0]   		  mul_1_r;
		wire [dWL+LUT_bits-1:0]	  mul2_net;







		assign reg_cmp = din[WL-2 : WL-1-LUT_addWidth];
		always @(posedge CLK) begin
			if(~nRST) begin
					iniValue <= 0;
					mul_1_r <= 0;
					din_delay <= 0;
					iniValue_delay3 <= 0;
					iniValue_delay2 <= 0;
					iniValue_delay <= 0;

			end
			else begin
				if (CE) begin

					din_delay <= din;
					iniValue_delay <= iniValue;
					iniValue_delay2 <= iniValue_delay;
					iniValue_delay3 <= iniValue_delay2;
					iniValue <= LUT[reg_cmp];
					mul_1_r <= ~mul1_net;
				end
			end
		end


mult_unsigned_pipe #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(LUT_bits-1), .WIO(1), .WFO(dWL-1)) multiplier_1 
						  (.CLK(CLK), .RST(nRST), .in1(din_delay), .in2(iniValue), .out(mul1_net));
						  

mult_unsigned_pipe #(.WI1(1), .WF1(dWL-1), .WI2(1), .WF2(LUT_bits-1), .WIO(1), .WFO(dWL+LUT_bits-1)) multiplier_2 
						  (.CLK(CLK), .RST(nRST), .in1(mul_1_r), .in2(iniValue_delay3), .out(mul2_net));


		ux_round2nearest
			#(
				.WordLength(dWL+LUT_bits),
				.RoundLength(dWL+LUT_bits-WLO)
			 )
		round_0 
			(
				.CLK(CLK),
				.RESET(nRST),
				.CE(CE),
				.x(mul2_net),
				.y(dout)
			 );
endmodule