data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/BitGen.v
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/BitGen.v\n%Error: Exiting due to 4 error(s)\n'
module BitGen(
input [3:0]		glyphCol, 
input [11:0] 	glyphR,
input [11:0] 	glyphG,
input [11:0] 	glyphB,
input [10:0] 	hCount,
input 			bright,
output reg 		red,
output reg 		green,
output reg 		blue
);

always@(*)
begin
	red 	<= 0;
	green <= 0;
	blue 	<= 0;
	if(bright)
		if(636 <= hCount)
		begin
			red 	<= 0;
			green <= 0;
			blue 	<= 0;
		end
		else
		begin

			red 	<= glyphR[11 - glyphCol];
			green <= glyphG[11 - glyphCol];
			blue 	<= glyphB[11 - glyphCol];
		end
end
endmodule
module BitGen(
input [3:0]		glyphCol, 
input [11:0] 	glyphR,
input [11:0] 	glyphG,
input [11:0] 	glyphB,
input [10:0] 	hCount,
input 			bright,
output reg 		red,
output reg 		green,
output reg 		blue
);


always@(*)
begin
	red 	<= 0;
	green <= 0;
	blue 	<= 0;
	if(bright)
		if(636 <= hCount)
		begin
			red 	<= 0;
			green <= 0;
			blue 	<= 0;
		end
		else
		begin

			red 	<= glyphR[11 - glyphCol];
			green <= glyphG[11 - glyphCol];
			blue 	<= glyphB[11 - glyphCol];
		end
end
endmodule