data/full_repos/permissive/177289247/Extender.v
data/verilator_xmls/9434bdd0-55c3-46e7-8ac5-b1680c9cf605.xml
module Extender(
input  [15:0]       DataIn,
input               ExtOp,
output reg[31:0]    ExtOut
);


always @( DataIn or ExtOp ) begin
    ExtOut[31:0] <=  { ExtOp?{16{DataIn[15]}}:16'b0, DataIn[15:0] };
end


endmodule
module Extender(
input  [15:0]       DataIn,
input               ExtOp,
output reg[31:0]    ExtOut
);



always @( DataIn or ExtOp ) begin
    ExtOut[31:0] <=  { ExtOp?{16{DataIn[15]}}:16'b0, DataIn[15:0] };
end


endmodule