data/full_repos/permissive/211316121/lab5_3_nexys4/74LS173.v
1: b'%Warning-WIDTH: data/full_repos/permissive/211316121/lab5_3_nexys4/74LS173.v:35: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n                                                                               : ... In instance Top_74LS173.top_173\n        Q<=\'bzzzz;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Top_74LS173(
    input [8:0] sw,
    input clkstd,
    output [3:0] led
);

wire clk;

CLKDIV top_div(clkstd,clk);

LS173 top_173(.D(sw[3:0]),.CP(clk),.CR(sw[4]),.G1(sw[5]),.G2(sw[6]),.M(sw[7]),.N(sw[8]),.Q(led[3:0]));

endmodule
module Top_74LS173(
    input [8:0] sw,
    input clkstd,
    output [3:0] led
);


wire clk;

CLKDIV top_div(clkstd,clk);

LS173 top_173(.D(sw[3:0]),.CP(clk),.CR(sw[4]),.G1(sw[5]),.G2(sw[6]),.M(sw[7]),.N(sw[8]),.Q(led[3:0]));

endmodule