data/full_repos/permissive/110151336/lab_04/src/6_lab4_hdl_nbit_8in1_selector/lab4.v
data/verilator_xmls/08b4fca5-1df5-4b4e-8dcd-120a9f5c56e7.xml
module lab4
(
    input   [ 1:0]  KEY,
    input   [ 9:0]  SW,
    output  [ 9:0]  LEDR
);

	bn_select_8_1_case #(3) bn_select_8_1_case (.d0(SW[2:0]), .d1(SW[3:1]), .d2(SW[4:2]), 
	                                            .d3(SW[5:3]), .d4(SW[6:4]), .d5(SW[7:5]), 
												.d6(SW[8:6]), .d7(SW[9:7]), .sel(SW[7:0]), .y(LEDR[2:0]));


endmodule
module lab4
(
    input   [ 1:0]  KEY,
    input   [ 9:0]  SW,
    output  [ 9:0]  LEDR
);


	bn_select_8_1_case #(3) bn_select_8_1_case (.d0(SW[2:0]), .d1(SW[3:1]), .d2(SW[4:2]), 
	                                            .d3(SW[5:3]), .d4(SW[6:4]), .d5(SW[7:5]), 
												.d6(SW[8:6]), .d7(SW[9:7]), .sel(SW[7:0]), .y(LEDR[2:0]));


endmodule