data/full_repos/permissive/204736068/SoM/RTL/common/ice40_spram_128kx8.sv
 line:72: before: "genvar"
1: b"%Error: data/full_repos/permissive/204736068/SoM/RTL/common/ice40_spram_128kx8.sv:79: Cannot find file containing module: 'SP256K'\n            SP256K i_spram16k_16 (\n            ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/204736068/SoM/RTL/common,data/full_repos/permissive/204736068/SP256K\n             data/full_repos/permissive/204736068/SoM/RTL/common,data/full_repos/permissive/204736068/SP256K.v\n             data/full_repos/permissive/204736068/SoM/RTL/common,data/full_repos/permissive/204736068/SP256K.sv\n             SP256K\n             SP256K.v\n             SP256K.sv\n             obj_dir/SP256K\n             obj_dir/SP256K.v\n             obj_dir/SP256K.sv\n%Error: Exiting due to 1 error(s)\n"
module ice40_spram_128kx8 (
    input  wire       clk    ,
    input  wire        rst    ,
    input  wire        cs     ,
    input  wire [16:0] addr   ,
    input  wire        wr_en  ,
    input  wire [ 7:0] wr_data,
    output wire [ 7:0] rd_data
);



    logic [ 3:0] mask          ;
    logic [ 3:0] we            ;
    logic [ 3:0] ram_cs        ;
    logic [15:0] dout     [0:3];
    logic [15:0] bank_dout     ;
    logic addr0_d;



    

    always_ff @(posedge clk)
        if (cs & ~wr_en)
            addr0_d <= addr[0];


    assign mask = addr[0] ? 4'b1100 : 4'b0011;

    generate
        for (genvar i=0; i<4; i++) begin


            assign we[i]     = wr_en && (addr[16:15] == i);
            assign ram_cs[i] = cs && (addr[16:15] == i);


            SP256K i_spram16k_16 (
                .CK      (clk               ),
                .CS      (ram_cs[i]         ),
                .AD      (addr[14:1]        ),
                .DI      ({wr_data, wr_data}),
                .MASKWE  (mask              ),
                .WE      (we[i]             ),
                .DO      (dout[i]           ),
                .STDBY   (1'b0              ),
                .SLEEP   (1'b0              ),
                .PWROFF_N(1'b1              )
            );
        end
    endgenerate


    assign bank_dout =
        (addr[16:15] == 2'b00) ? dout[0] :
        (addr[16:15] == 2'b01) ? dout[1] :
        (addr[16:15] == 2'b10) ? dout[2] :
        dout[3];


    assign rd_data = addr0_d ? bank_dout[15:8] : bank_dout[7:0];

endmodule
module ice40_spram_128kx8 (
    input  wire       clk    ,
    input  wire        rst    ,
    input  wire        cs     ,
    input  wire [16:0] addr   ,
    input  wire        wr_en  ,
    input  wire [ 7:0] wr_data,
    output wire [ 7:0] rd_data
);




    logic [ 3:0] mask          ;
    logic [ 3:0] we            ;
    logic [ 3:0] ram_cs        ;
    logic [15:0] dout     [0:3];
    logic [15:0] bank_dout     ;
    logic addr0_d;



    

    always_ff @(posedge clk)
        if (cs & ~wr_en)
            addr0_d <= addr[0];


    assign mask = addr[0] ? 4'b1100 : 4'b0011;

    generate
        for (genvar i=0; i<4; i++) begin


            assign we[i]     = wr_en && (addr[16:15] == i);
            assign ram_cs[i] = cs && (addr[16:15] == i);


            SP256K i_spram16k_16 (
                .CK      (clk               ),
                .CS      (ram_cs[i]         ),
                .AD      (addr[14:1]        ),
                .DI      ({wr_data, wr_data}),
                .MASKWE  (mask              ),
                .WE      (we[i]             ),
                .DO      (dout[i]           ),
                .STDBY   (1'b0              ),
                .SLEEP   (1'b0              ),
                .PWROFF_N(1'b1              )
            );
        end
    endgenerate


    assign bank_dout =
        (addr[16:15] == 2'b00) ? dout[0] :
        (addr[16:15] == 2'b01) ? dout[1] :
        (addr[16:15] == 2'b10) ? dout[2] :
        dout[3];


    assign rd_data = addr0_d ? bank_dout[15:8] : bank_dout[7:0];

endmodule