data/full_repos/permissive/178355189/reset_conditioner.v
data/verilator_xmls/3658f6c2-ff04-4825-98ea-88cedec8b860.xml
module reset_conditioner (
    input clk,
    input in,
    output reg out
  );

  parameter STAGES = 4;


  reg [STAGES - 1:0] stage;

  always @(posedge clk) begin
    if(in) begin
      stage <= {STAGES{1'b1}};
      out <= 1;
    end else begin
      stage <= {stage[STAGES-2:0],1'b0};
      out <= stage[STAGES-1];
    end
  end

endmodule
module reset_conditioner (
    input clk,
    input in,
    output reg out
  );


  parameter STAGES = 4;


  reg [STAGES - 1:0] stage;

  always @(posedge clk) begin
    if(in) begin
      stage <= {STAGES{1'b1}};
      out <= 1;
    end else begin
      stage <= {stage[STAGES-2:0],1'b0};
      out <= stage[STAGES-1];
    end
  end

endmodule