data/full_repos/permissive/146399661/src/rsa/test_rsa.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_rsa.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_rsa.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_rsa.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_rsa.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_rsa.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_rsa.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: data/full_repos/permissive/146399661/src/rsa/test_rsa.v:6: Cannot find file containing module: \'rsa\'\nrsa rsa(x,a,b,y,clock,enable,reset,ready);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/146399661/src/rsa,data/full_repos/permissive/146399661/rsa\n             data/full_repos/permissive/146399661/src/rsa,data/full_repos/permissive/146399661/rsa.v\n             data/full_repos/permissive/146399661/src/rsa,data/full_repos/permissive/146399661/rsa.sv\n             rsa\n             rsa.v\n             rsa.sv\n             obj_dir/rsa\n             obj_dir/rsa.v\n             obj_dir/rsa.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
reg [7:0] a,b,y;
reg clock,reset,enable;
wire [7:0] x;
wire ready;
rsa rsa(x,a,b,y,clock,enable,reset,ready);
initial begin 
    $display("test >> Resetting the rsa module");
    reset = 1;
    enable = 0;
    #10;
    reset = 0;

    if (~ready) begin
        $display("test >> rsa is ready");
    end
    else begin
        $display("test >> rsa is not ready");
    end
    a = 7;
    b = 3;
    y = 99;
    enable = 1;

    $display("test >> Waiting till rsa has its data ready");
    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> rsa has its data ready!");
    enable = 0;
    $display("test >> a was %d, b was %d, y is %d,axb = %d",a,b,y,x);

    $display("test >> Resetting the rsa module for the next computation");

    enable = 0;
    reset = 1;
    while (ready != 1'b0) begin
        #1;
    end
    reset = 0;

    $display("test >> emul_sql is ready");

    a = 5;
    b = 5;
    y = 5;
    enable = 1;
    while (ready == 1'b0) begin
        #1;
    end
    enable = 0;
end
always begin
    clock = 0; 
    #5;
    clock = 1;
    #5;
end
endmodule
module main;

reg [7:0] a,b,y;
reg clock,reset,enable;
wire [7:0] x;
wire ready;
rsa rsa(x,a,b,y,clock,enable,reset,ready);
initial begin 
    $display("test >> Resetting the rsa module");
    reset = 1;
    enable = 0;
    #10;
    reset = 0;

    if (~ready) begin
        $display("test >> rsa is ready");
    end
    else begin
        $display("test >> rsa is not ready");
    end
    a = 7;
    b = 3;
    y = 99;
    enable = 1;

    $display("test >> Waiting till rsa has its data ready");
    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> rsa has its data ready!");
    enable = 0;
    $display("test >> a was %d, b was %d, y is %d,axb = %d",a,b,y,x);

    $display("test >> Resetting the rsa module for the next computation");

    enable = 0;
    reset = 1;
    while (ready != 1'b0) begin
        #1;
    end
    reset = 0;

    $display("test >> emul_sql is ready");

    a = 5;
    b = 5;
    y = 5;
    enable = 1;
    while (ready == 1'b0) begin
        #1;
    end
    enable = 0;
end
always begin
    clock = 0; 
    #5;
    clock = 1;
    #5;
end
endmodule