data/full_repos/permissive/164482394/Verilog/MIDI_vel.v
data/verilator_xmls/1a731aa7-9f71-4b7a-8afb-ddbb253103f2.xml
module MIDI_vel(velocity, FM_in, ChA, ChB, ChC, ChD, Clk);
	input [7:0] velocity;
	input Clk, FM_in;
	output ChA, ChB, ChC, ChD;
	reg EnA, EnB, EnC, EnD;

	
	assign ChA = FM_in & EnA;
	assign ChB = FM_in & EnB;
	assign ChC = FM_in & EnC;
	assign ChD = FM_in & EnD;
	
	always @ (posedge Clk)
	begin
		if (velocity == 0)
		begin
			EnA <= 1'b0;
			EnB <= 1'b0;
			EnC <= 1'b0;
			EnD <= 1'b0;
		end
		else if ((velocity >= 1) & (velocity <= 31))
		begin
			EnA <= FM_in;
			EnB <= 1'b0;
			EnC <= 1'b0;
			EnD <= 1'b0;
		end
		else if ((velocity >= 32) & (velocity <= 63))
		begin
			EnA <= FM_in;
			EnB <= FM_in;
			EnC <= 1'b0;
			EnD <= 1'b0;
		end
		else if ((velocity >= 64) & (velocity <= 95))
		begin
			EnA <= FM_in;
			EnB <= FM_in;
			EnC <= FM_in;
			EnD <= 1'b0;
		end
		else if ((velocity >= 96) & (velocity <= 127))
		begin
			EnA <= FM_in;
			EnB <= FM_in;
			EnC <= FM_in;
			EnD <= FM_in;
		end

	end
	
endmodule
module MIDI_vel(velocity, FM_in, ChA, ChB, ChC, ChD, Clk);

	input [7:0] velocity;
	input Clk, FM_in;
	output ChA, ChB, ChC, ChD;
	reg EnA, EnB, EnC, EnD;

	
	assign ChA = FM_in & EnA;
	assign ChB = FM_in & EnB;
	assign ChC = FM_in & EnC;
	assign ChD = FM_in & EnD;
	
	always @ (posedge Clk)
	begin
		if (velocity == 0)
		begin
			EnA <= 1'b0;
			EnB <= 1'b0;
			EnC <= 1'b0;
			EnD <= 1'b0;
		end
		else if ((velocity >= 1) & (velocity <= 31))
		begin
			EnA <= FM_in;
			EnB <= 1'b0;
			EnC <= 1'b0;
			EnD <= 1'b0;
		end
		else if ((velocity >= 32) & (velocity <= 63))
		begin
			EnA <= FM_in;
			EnB <= FM_in;
			EnC <= 1'b0;
			EnD <= 1'b0;
		end
		else if ((velocity >= 64) & (velocity <= 95))
		begin
			EnA <= FM_in;
			EnB <= FM_in;
			EnC <= FM_in;
			EnD <= 1'b0;
		end
		else if ((velocity >= 96) & (velocity <= 127))
		begin
			EnA <= FM_in;
			EnB <= FM_in;
			EnC <= FM_in;
			EnD <= FM_in;
		end

	end
	
endmodule