data/full_repos/permissive/170013753/src/pc.v
 line:11: before: "input"
data/verilator_xmls/4f1cbf93-4cb1-4b37-82ba-f34bdb209090.xml
module pc(
  input clk,
  input rst,
  input en,
  input inc,
  input [15:0] d,
  output reg [15:0] o
);

always @(posedge clk) begin
  if(rst)      o <= 16'b0;
  else if(en)  o <= d;
  else if(inc) o <= o + 2;
  else         o <= o;
end

endmodule
module pc(
  input clk,
  input rst,
  input en,
  input inc,
  input [15:0] d,
  output reg [15:0] o
);


always @(posedge clk) begin
  if(rst)      o <= 16'b0;
  else if(en)  o <= d;
  else if(inc) o <= o + 2;
  else         o <= o;
end

endmodule