data/full_repos/permissive/154223629/opsg_noise.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/3b15bf2e-f398-45b4-a81b-b9215b0a6cd0.xml
module opsg_noise #(
	parameter TAPPED_BIT0 = 0,
	parameter TAPPED_BIT1 = 3,
	parameter SHIFT_WIDTH = 15,
	parameter TONE_WIDTH = 10
)(
	input clk,
	input reload,
	input fb,
	input [1:0] nf,
	input [TONE_WIDTH-1:0] freq,
	output reg [TONE_WIDTH-1:0] count,
	output reg [SHIFT_WIDTH-1:0] shiftReg,
	output reg noiseBit
);
  

	reg [TONE_WIDTH-1:0] counter = 1;
	reg [SHIFT_WIDTH-1:0] shift = { 1'b1, { SHIFT_WIDTH-1 {1'b0} } };
	reg nbit = 1'b1;
	reg feedback;
  
	always @(posedge clk) begin
		if ( counter == 1 ) begin
			case(nf)
				2'b00 : counter <= 16;
				2'b01 : counter <= 32;
				2'b10 : counter <= 64;

				default : counter <= freq;
			endcase
			nbit <= !nbit;
		end else begin
			counter <= counter - 1;
		end
		count = counter;
	end
  


	always @(posedge nbit, negedge reload) begin
		if (!reload) begin
			shift <= { 1'b1, { SHIFT_WIDTH-1 {1'b0} } };
		end else begin
			if (fb) begin
				shift <= { (shift[TAPPED_BIT0] ^ shift[TAPPED_BIT1]), shift[SHIFT_WIDTH-1:1] };
			end else begin
				shift <= { shift[0], shift[SHIFT_WIDTH-1:1] };
			end
			shiftReg = shift;
			noiseBit = shift[0];
		end
	end
  
endmodule
module opsg_noise #(
	parameter TAPPED_BIT0 = 0,
	parameter TAPPED_BIT1 = 3,
	parameter SHIFT_WIDTH = 15,
	parameter TONE_WIDTH = 10
)(
	input clk,
	input reload,
	input fb,
	input [1:0] nf,
	input [TONE_WIDTH-1:0] freq,
	output reg [TONE_WIDTH-1:0] count,
	output reg [SHIFT_WIDTH-1:0] shiftReg,
	output reg noiseBit
);

  

	reg [TONE_WIDTH-1:0] counter = 1;
	reg [SHIFT_WIDTH-1:0] shift = { 1'b1, { SHIFT_WIDTH-1 {1'b0} } };
	reg nbit = 1'b1;
	reg feedback;
  
	always @(posedge clk) begin
		if ( counter == 1 ) begin
			case(nf)
				2'b00 : counter <= 16;
				2'b01 : counter <= 32;
				2'b10 : counter <= 64;

				default : counter <= freq;
			endcase
			nbit <= !nbit;
		end else begin
			counter <= counter - 1;
		end
		count = counter;
	end
  


	always @(posedge nbit, negedge reload) begin
		if (!reload) begin
			shift <= { 1'b1, { SHIFT_WIDTH-1 {1'b0} } };
		end else begin
			if (fb) begin
				shift <= { (shift[TAPPED_BIT0] ^ shift[TAPPED_BIT1]), shift[SHIFT_WIDTH-1:1] };
			end else begin
				shift <= { shift[0], shift[SHIFT_WIDTH-1:1] };
			end
			shiftReg = shift;
			noiseBit = shift[0];
		end
	end
  
endmodule