data/full_repos/permissive/167856740/cpu/privilege.v
None: at end of input
1: b'%Error: data/full_repos/permissive/167856740/cpu/privilege.v:4: Cannot find include file: alu_definitions.vh\n`include "alu_definitions.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167856740/cpu,data/full_repos/permissive/167856740/alu_definitions.vh\n             data/full_repos/permissive/167856740/cpu,data/full_repos/permissive/167856740/alu_definitions.vh.v\n             data/full_repos/permissive/167856740/cpu,data/full_repos/permissive/167856740/alu_definitions.vh.sv\n             alu_definitions.vh\n             alu_definitions.vh.v\n             alu_definitions.vh.sv\n             obj_dir/alu_definitions.vh\n             obj_dir/alu_definitions.vh.v\n             obj_dir/alu_definitions.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module privilege #(parameter VECTOR=32'h00000000) (
    input wire I_clk,
    input wire I_rst,


    input wire I_ecall,
    input wire I_ebreak,
    input wire I_illegalinst,


    input wire I_extinterrupt,
    

    input wire I_mret,
    

    input wire [31:0] I_pc,
    input wire I_msrwen,
    input wire signed [11:0] I_csraddr,
    input wire signed [3:0] I_rs1addr,
    input wire signed [31:0] I_rs1data,
	output reg signed [31:0] O_csrdata,
	

	output reg O_exception,
	output wire [31:0] O_epcreturn,
	output wire [31:0] O_evect
);

    reg [2:0] mstatus;
    reg [4:0] mcause;
    reg [31:0] mepc;
    reg [31:0] mevect;


    wire exception = I_ecall | I_ebreak | I_illegalinst;


    assign O_epcreturn = (mcause[4] == 0) ? mepc + 4 : mepc;
    assign O_evect = mevect;


    initial begin
        mstatus <= 3'b000;
        mcause <= 5'b00000;
        mepc <= 32'h00000000;
        mevect <= VECTOR;
        O_exception <= 0;
    end





           















        



                   


                   


                   



            



            


        



            


            


            



        







    

    always @(posedge I_clk) begin

        if(I_rst) begin
            mstatus <= 3'b000;
            mcause <= 5'b00000;
            mepc <= 32'h00000000;
            mevect <= VECTOR;
        end
        
        else begin

            O_exception <= 0;
            
            if(exception) begin

                if(I_illegalinst) begin
                    $display("PRIV: An illegal instruction exception has occured");
                    mcause <= 5'b00010;
                end
                else if (I_ebreak) begin
                    $display("PRIV: An ebreak exception has occured");
                    mcause <= 5'b00011;
                end
                else begin
                    $display("PRIV: An ecall exception has occured");
                    mcause <= 5'b01011;
                end
            


                mepc <= I_pc;
                       

                mstatus[1] <= mstatus[0];
                       

                mstatus[0] <= 0;
                       

                O_exception <= 1;
            end
            

            else if(I_extinterrupt && (mstatus[0] == 1)) begin
                $display("PRIV: An external interrupt has occured");
                        

                mcause <= 5'b11011;        
                    


                mepc <= I_pc;
                        

                mstatus[1] <= mstatus[0];
                        

                mstatus[0] <= 0;
                        

                O_exception <= 1;
            end
            
            else if(I_mret) begin

                mstatus[0] <= mstatus[1];
                $display("MRET: The MRET instruction was called");
            end
            


            else if (I_msrwen == 1 && (I_rs1addr != 4'b0000)) begin
                case(I_csraddr)              

                    12'h7C0: mstatus <= I_rs1data[2:0];
                    12'h7C1: mcause <= {I_rs1data[31], I_rs1data[3:0]};
                    12'h7C2: mepc <= I_rs1data;
                    12'h7C3: mevect <= I_rs1data;
                endcase
                $display("The value %h was stored in msr %h", I_rs1data, I_csraddr);
            end
        end
    end
    

    always @(*) begin

        case(I_csraddr)
            12'hFC0: O_csrdata = {29'b00000000000000000000000000000,mstatus};
            12'h7C0: O_csrdata = {29'b00000000000000000000000000000,mstatus};
            12'hFC1: O_csrdata = {mcause[4],27'b00000000000000000000000000000,mcause[3:0]};
            12'h7C1: O_csrdata = {mcause[4],27'b00000000000000000000000000000,mcause[3:0]};
            12'hFC2: O_csrdata = mepc;
            12'h7C2: O_csrdata = mepc;
            12'hFC3: O_csrdata = mevect;
            12'h7C3: O_csrdata = mevect;
            default: O_csrdata = 32'hFFFFFFFF;
        endcase
    end
endmodule
module privilege #(parameter VECTOR=32'h00000000) (
    input wire I_clk,
    input wire I_rst,


    input wire I_ecall,
    input wire I_ebreak,
    input wire I_illegalinst,


    input wire I_extinterrupt,
    

    input wire I_mret,
    

    input wire [31:0] I_pc,
    input wire I_msrwen,
    input wire signed [11:0] I_csraddr,
    input wire signed [3:0] I_rs1addr,
    input wire signed [31:0] I_rs1data,
	output reg signed [31:0] O_csrdata,
	

	output reg O_exception,
	output wire [31:0] O_epcreturn,
	output wire [31:0] O_evect
);


    reg [2:0] mstatus;
    reg [4:0] mcause;
    reg [31:0] mepc;
    reg [31:0] mevect;


    wire exception = I_ecall | I_ebreak | I_illegalinst;


    assign O_epcreturn = (mcause[4] == 0) ? mepc + 4 : mepc;
    assign O_evect = mevect;


    initial begin
        mstatus <= 3'b000;
        mcause <= 5'b00000;
        mepc <= 32'h00000000;
        mevect <= VECTOR;
        O_exception <= 0;
    end





           















        



                   


                   


                   



            



            


        



            


            


            



        







    

    always @(posedge I_clk) begin

        if(I_rst) begin
            mstatus <= 3'b000;
            mcause <= 5'b00000;
            mepc <= 32'h00000000;
            mevect <= VECTOR;
        end
        
        else begin

            O_exception <= 0;
            
            if(exception) begin

                if(I_illegalinst) begin
                    $display("PRIV: An illegal instruction exception has occured");
                    mcause <= 5'b00010;
                end
                else if (I_ebreak) begin
                    $display("PRIV: An ebreak exception has occured");
                    mcause <= 5'b00011;
                end
                else begin
                    $display("PRIV: An ecall exception has occured");
                    mcause <= 5'b01011;
                end
            


                mepc <= I_pc;
                       

                mstatus[1] <= mstatus[0];
                       

                mstatus[0] <= 0;
                       

                O_exception <= 1;
            end
            

            else if(I_extinterrupt && (mstatus[0] == 1)) begin
                $display("PRIV: An external interrupt has occured");
                        

                mcause <= 5'b11011;        
                    


                mepc <= I_pc;
                        

                mstatus[1] <= mstatus[0];
                        

                mstatus[0] <= 0;
                        

                O_exception <= 1;
            end
            
            else if(I_mret) begin

                mstatus[0] <= mstatus[1];
                $display("MRET: The MRET instruction was called");
            end
            


            else if (I_msrwen == 1 && (I_rs1addr != 4'b0000)) begin
                case(I_csraddr)              

                    12'h7C0: mstatus <= I_rs1data[2:0];
                    12'h7C1: mcause <= {I_rs1data[31], I_rs1data[3:0]};
                    12'h7C2: mepc <= I_rs1data;
                    12'h7C3: mevect <= I_rs1data;
                endcase
                $display("The value %h was stored in msr %h", I_rs1data, I_csraddr);
            end
        end
    end
    

    always @(*) begin

        case(I_csraddr)
            12'hFC0: O_csrdata = {29'b00000000000000000000000000000,mstatus};
            12'h7C0: O_csrdata = {29'b00000000000000000000000000000,mstatus};
            12'hFC1: O_csrdata = {mcause[4],27'b00000000000000000000000000000,mcause[3:0]};
            12'h7C1: O_csrdata = {mcause[4],27'b00000000000000000000000000000,mcause[3:0]};
            12'hFC2: O_csrdata = mepc;
            12'h7C2: O_csrdata = mepc;
            12'hFC3: O_csrdata = mevect;
            12'h7C3: O_csrdata = mevect;
            default: O_csrdata = 32'hFFFFFFFF;
        endcase
    end
endmodule