data/full_repos/permissive/156609923/memoria/probador.v
 line:38: before: "("
1: b'%Error: data/full_repos/permissive/156609923/memoria/probador.v:29: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("dump.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/memoria/probador.v:30: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/memoria/probador.v:31: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/memoria/probador.v:37: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/memoria/probador.v:42: syntax error, unexpected \'@\'\n    @(posedge clk); \n    ^\n%Error: data/full_repos/permissive/156609923/memoria/probador.v:48: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/memoria/probador.v:54: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/156609923/memoria/probador.v:64: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/156609923/memoria/probador.v:69: syntax error, unexpected \'@\'\n   @(posedge clk);@(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/memoria/probador.v:74: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk <= ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 9 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador #(
parameter ADDR_WIDTH = 4,
parameter BUS_SIZE = 4,

parameter MEM_LENGTH = 1 << ADDR_WIDTH)(












 output reg 		     clk,
 output reg 		     read,write,
 output reg [BUS_SIZE-1:0]   data_in,
 output reg [ADDR_WIDTH-1:0] addressR,
 output reg [ADDR_WIDTH-1:0] addressW,
 input wire [BUS_SIZE-1:0]   data_out_synth,
 input wire [BUS_SIZE-1:0]   data_out_cond);
   
   

   initial begin
   $dumpfile("dump.vcd");
	$dumpvars();
   @(posedge clk);
   read <= 0;
   write <= 0;
   data_in <= 0;
   addressR <= 0;
	addressW <= 0;
   @(posedge clk);
   repeat (MEM_LENGTH) begin
	   data_in <= $random;
	   write <= 1;
	   read <=1;
	   @(posedge clk);	
	   addressW <= addressW + 1;
	   addressR <= addressR + 1;
	end
   
   addressR <= 0;
   @(posedge clk);
   @(posedge clk);
   addressW <= -1;
   repeat (MEM_LENGTH) begin
	   read <= 1;
	   data_in<=$random;
	   @(posedge clk);
	   addressR <= addressR + 1;
	   addressW <= addressW + 1;
	   
	end

   write <= 0;
   repeat (MEM_LENGTH) begin
      read <= 1;

      @(posedge clk);
      addressR <= addressR + 1;

      
   end
   @(posedge clk);@(posedge clk);
   $finish;
end  
   
   initial clk <= 0;
   always #1 clk <= ~clk;
   

endmodule
module probador #(
parameter ADDR_WIDTH = 4,
parameter BUS_SIZE = 4,

parameter MEM_LENGTH = 1 << ADDR_WIDTH)(












 output reg 		     clk,
 output reg 		     read,write,
 output reg [BUS_SIZE-1:0]   data_in,
 output reg [ADDR_WIDTH-1:0] addressR,
 output reg [ADDR_WIDTH-1:0] addressW,
 input wire [BUS_SIZE-1:0]   data_out_synth,
 input wire [BUS_SIZE-1:0]   data_out_cond);

   
   

   initial begin
   $dumpfile("dump.vcd");
	$dumpvars();
   @(posedge clk);
   read <= 0;
   write <= 0;
   data_in <= 0;
   addressR <= 0;
	addressW <= 0;
   @(posedge clk);
   repeat (MEM_LENGTH) begin
	   data_in <= $random;
	   write <= 1;
	   read <=1;
	   @(posedge clk);	
	   addressW <= addressW + 1;
	   addressR <= addressR + 1;
	end
   
   addressR <= 0;
   @(posedge clk);
   @(posedge clk);
   addressW <= -1;
   repeat (MEM_LENGTH) begin
	   read <= 1;
	   data_in<=$random;
	   @(posedge clk);
	   addressR <= addressR + 1;
	   addressW <= addressW + 1;
	   
	end

   write <= 0;
   repeat (MEM_LENGTH) begin
      read <= 1;

      @(posedge clk);
      addressR <= addressR + 1;

      
   end
   @(posedge clk);@(posedge clk);
   $finish;
end  
   
   initial clk <= 0;
   always #1 clk <= ~clk;
   

endmodule