data/full_repos/permissive/167746421/pe_core/genesis/test_mult_add_vec.svp
 line:15: before: "parameter"
1: b"%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_mult_add_vec.svp:14: Define or directive not defined: '`mname'\nmodule  `mname` #(\n        ^~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_mult_add_vec.svp:14: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule  `mname` #(\n              ^\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_mult_add_vec.svp:16: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter MaxVecSz = 4,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_mult_add_vec.svp:17: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter VecWidth = 4  \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_mult_add_vec.svp:18: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_mult_add_vec.svp:28: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic  [MaxVecSz-1:0]   c_out\n  ^~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_mult_add_vec.svp:29: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_mult_add_vec.svp:50: syntax error, unexpected assign\n  assign a_sign = is_signed & a[DataWidth-1];\n  ^~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_mult_add_vec.svp:73: syntax error, unexpected IDENTIFIER\n    c_addend = vec_mode == 2'b10 ? {{vecStride{c[15]&is_signed}},c[15:12],{vecStride{c[11]&is_signed}},c[11:8],{vecStride{c[7]&is_signed}},c[7:4],{vecStride{c[3]&is_signed}},c[3:0]} : \n    ^~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module  `mname` #(
  parameter DataWidth = 16,
  parameter MaxVecSz = 4,
  parameter VecWidth = 4
) (
  input                  is_signed,
  input  [DataWidth-1:0] a,
  input  [DataWidth-1:0] b,


  input  [DataWidth-1:0] c,

  input  [1:0]           vec_mode,
  output logic [2*DataWidth-1:0] res,
  output logic  [MaxVecSz-1:0]   c_out
);



localparam npp  = ((DataWidth/2) + 2);
localparam xdim = (DataWidth+DataWidth+1);
localparam asxt = (DataWidth+1);
localparam outStride = (DataWidth*2/MaxVecSz);
localparam vecStride= (DataWidth/MaxVecSz);

reg   [xdim-1 : 0]  pp_array [0 : npp-1];
reg   [xdim-1 : 0]	tmp_OUT0, tmp_OUT1;
reg   [xdim-1:0] int_sum,out_sum;
reg   [MaxVecSz-1:0] carries_out;
wire  [DataWidth+2 : 0]	b_padded;
wire  [xdim-1 : 0]	a_padded;
wire  [xdim-DataWidth-1 : 0]	temp_padded;
wire  			a_sign, b_sign, out_sign;
wire  signed [DataWidth : 0]      a_signed;
wire  signed [DataWidth : 0]      b_signed;

  assign a_sign = is_signed & a[DataWidth-1];
  assign b_sign = is_signed & b[DataWidth-1];
  assign b_padded = {b_sign, b_sign, b, 1'b0};
  assign temp_padded = {asxt{a_sign}};
  assign a_padded = {temp_padded, a};

  always @ (a_padded or b_padded or vec_mode or c)

  always @ (a_padded or b_padded or vec_mode)

  begin : mk_pp_array
    reg [xdim-1 : 0] temp_pp_array [0 : npp-1];
    reg [xdim-1 : 0] next_pp_array [0 : npp-1];
    reg [xdim+3 : 0] temp_pp;
    reg [xdim-1 : 0] new_pp;
    reg [xdim-1 : 0] tmp_pp_carry, temp_sum;
    reg [DataWidth+2 : 0] temp_b_padded;
    reg [2 : 0] temp_bitgroup;
    reg [xdim-1:0]  pp_mask,mult_mask,vec_multiplicand; 
    reg [MaxVecSz-1:0] carries_in,c_out_full;
	integer vec_ind,maski,vec_stride,bit_pair, pp_count, i,velem,ppi,ppvi;

    reg [2*DataWidth-1:0] c_addend;
    c_addend = vec_mode == 2'b10 ? {{vecStride{c[15]&is_signed}},c[15:12],{vecStride{c[11]&is_signed}},c[11:8],{vecStride{c[7]&is_signed}},c[7:4],{vecStride{c[3]&is_signed}},c[3:0]} : 
    vec_mode == 2'b01 ? {{2*vecStride{c[15]&is_signed}},c[15:8],{2*vecStride{c[7]&is_signed}},c[7:0]} : {{DataWidth{c[15]&is_signed}},c};
    temp_pp_array[0] = {xdim{1'b0}};


    for (bit_pair=0 ; bit_pair < npp-2 ; bit_pair = bit_pair+1)
    begin
      vec_ind = bit_pair >> (DataWidth/MaxVecSz >> vec_mode);

      vec_stride  = (DataWidth >> vec_mode);

      pp_mask[xdim-1:DataWidth] = 0;
      mult_mask[xdim-1:DataWidth]= 0;
      for(maski = 0; maski < MaxVecSz; maski = maski +1) begin
        mult_mask[maski*vecStride+:vecStride] = vec_ind == (maski >> (MaxVecSz >> vec_mode)-1) ? -1 : 0; 
        pp_mask[maski*vecStride*2+:vecStride*2] = vec_ind == (maski >> (MaxVecSz >> vec_mode)-1) ? -1 : 0; 
      end
      


      vec_multiplicand = a_padded & mult_mask;
      vec_multiplicand[(vec_ind+1)*vec_stride+:DataWidth] = is_signed & vec_multiplicand[((vec_ind+1)*vec_stride)-1]?-1:0;

      temp_b_padded = (b_padded >> (bit_pair*2));
      temp_bitgroup[2:1] = temp_b_padded[2:1];


	  case (vec_mode)
      	2'b10:
          temp_bitgroup[0] = temp_b_padded[0] & ~(bit_pair[0] == 1'd0);
        2'b01:
          temp_bitgroup[0] = temp_b_padded[0] & ~(bit_pair[1:0] == 2'd0);
		default:
          temp_bitgroup[0] = temp_b_padded[0];
	  endcase


      case (temp_bitgroup)
        3'b000, 3'b111 :
          temp_pp = {xdim{1'b0}};
        3'b001, 3'b010 :
          temp_pp = (vec_multiplicand);
        3'b011 :
          temp_pp = (vec_multiplicand) << 1;
        3'b100 :
          temp_pp = (~((vec_multiplicand) << 1) + 1);
        3'b101, 3'b110 :
          temp_pp =  ~(vec_multiplicand) + 1;
        default : temp_pp = {xdim{1'b0}};
      endcase

      temp_pp = (temp_pp) << (2 * bit_pair);
      new_pp = temp_pp[xdim-1 : 0] & pp_mask;

      temp_pp_array[bit_pair+1] = new_pp;
    end


    temp_pp_array[npp-1] = is_signed ? 0 : 
    (vec_mode == 2'b00) ? b[DataWidth-1] ? a_padded << DataWidth:0 : 
    vec_mode == 2'b01 ? {b[DataWidth-1] ? a_padded[DataWidth-1-:DataWidth/2]:{2*VecWidth{1'b0}},	 	{2*VecWidth{1'b0}}, b[DataWidth/2-1] ? a_padded[DataWidth/2-1-:DataWidth/2]:{2*VecWidth{1'b0}} ,{2*VecWidth{1'b0}}} : 
    {b[DataWidth-1] ? a_padded[DataWidth-1-:VecWidth] :{VecWidth{1'b0}},{VecWidth{1'b0}},b[DataWidth-1-VecWidth] ? a_padded[DataWidth-1-VecWidth-:VecWidth]: {VecWidth{1'b0}},{VecWidth{1'b0}},b[DataWidth-1-2*(VecWidth)] ? a_padded[DataWidth-1-2*(VecWidth)-:VecWidth]:{VecWidth{1'b0}}, {VecWidth{1'b0}},b[(VecWidth)-1] ? a_padded[(VecWidth)-1-:VecWidth]: {VecWidth{1'b0}}, {VecWidth{1'b0}}};



    pp_count = npp;
    while (pp_count > 2)
    begin
      for (i=0 ; i < (pp_count/3) ; i = i+1)
      begin
        next_pp_array[i*2] = temp_pp_array[i*3] ^ temp_pp_array[i*3+1] ^ temp_pp_array[i*3+2];

        tmp_pp_carry = (temp_pp_array[i*3] & temp_pp_array[i*3+1]) |
                       (temp_pp_array[i*3+1] & temp_pp_array[i*3+2]) |
                       (temp_pp_array[i*3] & temp_pp_array[i*3+2]);

        tmp_pp_carry[2*VecWidth-1] = tmp_pp_carry[2*VecWidth-1] & ~(vec_mode == 2'b10);
        tmp_pp_carry[4*VecWidth-1] = tmp_pp_carry[4*VecWidth-1] & ~((vec_mode == 2'b10) | (vec_mode == 2'b01));
        tmp_pp_carry[6*VecWidth-1] = tmp_pp_carry[6*VecWidth-1] & ~(vec_mode == 2'b10);

        next_pp_array[i*2+1] = tmp_pp_carry << 1;
      end

      if ((pp_count % 3) > 0)
      begin
        for (i=0 ; i < (pp_count % 3) ; i = i + 1)
        next_pp_array[2 * (pp_count/3) + i] = temp_pp_array[3 * (pp_count/3) + i];
      end

      for (i=0 ; i < npp ; i = i + 1) 
        temp_pp_array[i] = next_pp_array[i];

      pp_count = pp_count - (pp_count/3);
    end
        tmp_OUT0 = temp_pp_array[0];

    if (pp_count > 1)
      tmp_OUT1 = temp_pp_array[1];
    else
      tmp_OUT1 = {xdim{1'b0}};


    carries_in[0] = 1'b0;

    temp_sum = 0;
    for(velem=0; velem<MaxVecSz; velem=velem + 1) begin
      {c_out_full[velem], temp_sum[(velem+1)*2*vecStride -1 -:2*vecStride]} = 
      tmp_OUT1[(velem+1)*2*vecStride-1 -:2*vecStride] +  tmp_OUT0[(velem+1)*2*vecStride-1 -:2*vecStride] + (vec_mode == 2'b10 ? 1'b0 : vec_mode == 2'b01 ? (velem[0] & carries_in[velem]) : carries_in[velem]);
      if(velem != MaxVecSz) begin
         carries_in[velem + 1] =  c_out_full[velem];
      end

    end
    int_sum = temp_sum;

    carries_in = 0;
    c_out_full = 0;
    for(velem=0; velem<MaxVecSz; velem=velem + 1) begin
 
      {c_out_full[velem], int_sum[(velem+1)*2*vecStride -1 -:2*vecStride]} = int_sum[(velem+1)*2*vecStride -1 -:2*vecStride] + c_addend[(velem+1)*2*vecStride -1 -:2*vecStride] + (vec_mode == 2'b10 ? 1'b0 : vec_mode == 2'b01 ? (velem[0] & carries_in[velem]) : carries_in[velem]);    
      if(velem != MaxVecSz) begin
         carries_in[velem + 1] =  c_out_full[velem];
      end

    end

    carries_out = c_out_full;
    out_sum = int_sum;
  end
  
    assign res = out_sum;
	assign c_out = carries_out;
endmodule
module  `mname` #(
  parameter DataWidth = 16,
  parameter MaxVecSz = 4,
  parameter VecWidth = 4
) (
  input                  is_signed,
  input  [DataWidth-1:0] a,
  input  [DataWidth-1:0] b,


  input  [DataWidth-1:0] c,

  input  [1:0]           vec_mode,
  output logic [2*DataWidth-1:0] res,
  output logic  [MaxVecSz-1:0]   c_out
);




localparam npp  = ((DataWidth/2) + 2);
localparam xdim = (DataWidth+DataWidth+1);
localparam asxt = (DataWidth+1);
localparam outStride = (DataWidth*2/MaxVecSz);
localparam vecStride= (DataWidth/MaxVecSz);

reg   [xdim-1 : 0]  pp_array [0 : npp-1];
reg   [xdim-1 : 0]	tmp_OUT0, tmp_OUT1;
reg   [xdim-1:0] int_sum,out_sum;
reg   [MaxVecSz-1:0] carries_out;
wire  [DataWidth+2 : 0]	b_padded;
wire  [xdim-1 : 0]	a_padded;
wire  [xdim-DataWidth-1 : 0]	temp_padded;
wire  			a_sign, b_sign, out_sign;
wire  signed [DataWidth : 0]      a_signed;
wire  signed [DataWidth : 0]      b_signed;

  assign a_sign = is_signed & a[DataWidth-1];
  assign b_sign = is_signed & b[DataWidth-1];
  assign b_padded = {b_sign, b_sign, b, 1'b0};
  assign temp_padded = {asxt{a_sign}};
  assign a_padded = {temp_padded, a};

  always @ (a_padded or b_padded or vec_mode or c)

  always @ (a_padded or b_padded or vec_mode)

  begin : mk_pp_array
    reg [xdim-1 : 0] temp_pp_array [0 : npp-1];
    reg [xdim-1 : 0] next_pp_array [0 : npp-1];
    reg [xdim+3 : 0] temp_pp;
    reg [xdim-1 : 0] new_pp;
    reg [xdim-1 : 0] tmp_pp_carry, temp_sum;
    reg [DataWidth+2 : 0] temp_b_padded;
    reg [2 : 0] temp_bitgroup;
    reg [xdim-1:0]  pp_mask,mult_mask,vec_multiplicand; 
    reg [MaxVecSz-1:0] carries_in,c_out_full;
	integer vec_ind,maski,vec_stride,bit_pair, pp_count, i,velem,ppi,ppvi;

    reg [2*DataWidth-1:0] c_addend;
    c_addend = vec_mode == 2'b10 ? {{vecStride{c[15]&is_signed}},c[15:12],{vecStride{c[11]&is_signed}},c[11:8],{vecStride{c[7]&is_signed}},c[7:4],{vecStride{c[3]&is_signed}},c[3:0]} : 
    vec_mode == 2'b01 ? {{2*vecStride{c[15]&is_signed}},c[15:8],{2*vecStride{c[7]&is_signed}},c[7:0]} : {{DataWidth{c[15]&is_signed}},c};
    temp_pp_array[0] = {xdim{1'b0}};


    for (bit_pair=0 ; bit_pair < npp-2 ; bit_pair = bit_pair+1)
    begin
      vec_ind = bit_pair >> (DataWidth/MaxVecSz >> vec_mode);

      vec_stride  = (DataWidth >> vec_mode);

      pp_mask[xdim-1:DataWidth] = 0;
      mult_mask[xdim-1:DataWidth]= 0;
      for(maski = 0; maski < MaxVecSz; maski = maski +1) begin
        mult_mask[maski*vecStride+:vecStride] = vec_ind == (maski >> (MaxVecSz >> vec_mode)-1) ? -1 : 0; 
        pp_mask[maski*vecStride*2+:vecStride*2] = vec_ind == (maski >> (MaxVecSz >> vec_mode)-1) ? -1 : 0; 
      end
      


      vec_multiplicand = a_padded & mult_mask;
      vec_multiplicand[(vec_ind+1)*vec_stride+:DataWidth] = is_signed & vec_multiplicand[((vec_ind+1)*vec_stride)-1]?-1:0;

      temp_b_padded = (b_padded >> (bit_pair*2));
      temp_bitgroup[2:1] = temp_b_padded[2:1];


	  case (vec_mode)
      	2'b10:
          temp_bitgroup[0] = temp_b_padded[0] & ~(bit_pair[0] == 1'd0);
        2'b01:
          temp_bitgroup[0] = temp_b_padded[0] & ~(bit_pair[1:0] == 2'd0);
		default:
          temp_bitgroup[0] = temp_b_padded[0];
	  endcase


      case (temp_bitgroup)
        3'b000, 3'b111 :
          temp_pp = {xdim{1'b0}};
        3'b001, 3'b010 :
          temp_pp = (vec_multiplicand);
        3'b011 :
          temp_pp = (vec_multiplicand) << 1;
        3'b100 :
          temp_pp = (~((vec_multiplicand) << 1) + 1);
        3'b101, 3'b110 :
          temp_pp =  ~(vec_multiplicand) + 1;
        default : temp_pp = {xdim{1'b0}};
      endcase

      temp_pp = (temp_pp) << (2 * bit_pair);
      new_pp = temp_pp[xdim-1 : 0] & pp_mask;

      temp_pp_array[bit_pair+1] = new_pp;
    end


    temp_pp_array[npp-1] = is_signed ? 0 : 
    (vec_mode == 2'b00) ? b[DataWidth-1] ? a_padded << DataWidth:0 : 
    vec_mode == 2'b01 ? {b[DataWidth-1] ? a_padded[DataWidth-1-:DataWidth/2]:{2*VecWidth{1'b0}},	 	{2*VecWidth{1'b0}}, b[DataWidth/2-1] ? a_padded[DataWidth/2-1-:DataWidth/2]:{2*VecWidth{1'b0}} ,{2*VecWidth{1'b0}}} : 
    {b[DataWidth-1] ? a_padded[DataWidth-1-:VecWidth] :{VecWidth{1'b0}},{VecWidth{1'b0}},b[DataWidth-1-VecWidth] ? a_padded[DataWidth-1-VecWidth-:VecWidth]: {VecWidth{1'b0}},{VecWidth{1'b0}},b[DataWidth-1-2*(VecWidth)] ? a_padded[DataWidth-1-2*(VecWidth)-:VecWidth]:{VecWidth{1'b0}}, {VecWidth{1'b0}},b[(VecWidth)-1] ? a_padded[(VecWidth)-1-:VecWidth]: {VecWidth{1'b0}}, {VecWidth{1'b0}}};



    pp_count = npp;
    while (pp_count > 2)
    begin
      for (i=0 ; i < (pp_count/3) ; i = i+1)
      begin
        next_pp_array[i*2] = temp_pp_array[i*3] ^ temp_pp_array[i*3+1] ^ temp_pp_array[i*3+2];

        tmp_pp_carry = (temp_pp_array[i*3] & temp_pp_array[i*3+1]) |
                       (temp_pp_array[i*3+1] & temp_pp_array[i*3+2]) |
                       (temp_pp_array[i*3] & temp_pp_array[i*3+2]);

        tmp_pp_carry[2*VecWidth-1] = tmp_pp_carry[2*VecWidth-1] & ~(vec_mode == 2'b10);
        tmp_pp_carry[4*VecWidth-1] = tmp_pp_carry[4*VecWidth-1] & ~((vec_mode == 2'b10) | (vec_mode == 2'b01));
        tmp_pp_carry[6*VecWidth-1] = tmp_pp_carry[6*VecWidth-1] & ~(vec_mode == 2'b10);

        next_pp_array[i*2+1] = tmp_pp_carry << 1;
      end

      if ((pp_count % 3) > 0)
      begin
        for (i=0 ; i < (pp_count % 3) ; i = i + 1)
        next_pp_array[2 * (pp_count/3) + i] = temp_pp_array[3 * (pp_count/3) + i];
      end

      for (i=0 ; i < npp ; i = i + 1) 
        temp_pp_array[i] = next_pp_array[i];

      pp_count = pp_count - (pp_count/3);
    end
        tmp_OUT0 = temp_pp_array[0];

    if (pp_count > 1)
      tmp_OUT1 = temp_pp_array[1];
    else
      tmp_OUT1 = {xdim{1'b0}};


    carries_in[0] = 1'b0;

    temp_sum = 0;
    for(velem=0; velem<MaxVecSz; velem=velem + 1) begin
      {c_out_full[velem], temp_sum[(velem+1)*2*vecStride -1 -:2*vecStride]} = 
      tmp_OUT1[(velem+1)*2*vecStride-1 -:2*vecStride] +  tmp_OUT0[(velem+1)*2*vecStride-1 -:2*vecStride] + (vec_mode == 2'b10 ? 1'b0 : vec_mode == 2'b01 ? (velem[0] & carries_in[velem]) : carries_in[velem]);
      if(velem != MaxVecSz) begin
         carries_in[velem + 1] =  c_out_full[velem];
      end

    end
    int_sum = temp_sum;

    carries_in = 0;
    c_out_full = 0;
    for(velem=0; velem<MaxVecSz; velem=velem + 1) begin
 
      {c_out_full[velem], int_sum[(velem+1)*2*vecStride -1 -:2*vecStride]} = int_sum[(velem+1)*2*vecStride -1 -:2*vecStride] + c_addend[(velem+1)*2*vecStride -1 -:2*vecStride] + (vec_mode == 2'b10 ? 1'b0 : vec_mode == 2'b01 ? (velem[0] & carries_in[velem]) : carries_in[velem]);    
      if(velem != MaxVecSz) begin
         carries_in[velem + 1] =  c_out_full[velem];
      end

    end

    carries_out = c_out_full;
    out_sum = int_sum;
  end
  
    assign res = out_sum;
	assign c_out = carries_out;
endmodule