data/full_repos/permissive/146689564/whac_a_mole_v3.v
 line:77: before: "."
1: b'%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:708: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'frame\' generates 4 bits.\n                                                                         : ... In instance whac_a_mole_v3.u1\nassign en = ((q == frame) & enable) ? 1:0;  \n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:716: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'frame\' generates 4 bits.\n                                                                         : ... In instance whac_a_mole_v3.u1\n    if(q == frame)  \n         ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:440: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d0: y_posi = mole_1;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:441: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_2\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d1: y_posi = mole_2;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:442: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_3\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d2: y_posi = mole_3;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:443: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_4\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d3: y_posi = mole_4;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:444: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n    default: y_posi = mole_1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:447: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  else y_posi = mole_1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:466: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n       mole_1 <= M_Y_S;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:467: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      mole_2 <= M_Y_S;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     mole_3 <= M_Y_S;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:469: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     mole_4 <= M_Y_S;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:475: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S1\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence1 <= S1;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:476: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S2\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence2 <= S2;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:477: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S3\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence3 <= S3;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:478: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S4\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence4 <= S4;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:501: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:496: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_1 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:509: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:504: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_2 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:517: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:512: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_3 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:525: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:520: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_4 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:531: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:535: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:539: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:543: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:547: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:551: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:555: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:559: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:568: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h33\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 == 7\'d51) \n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:573: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h33\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 == 7\'d51)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:578: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h34\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 < 7\'d52)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:583: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h34\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 < 7\'d52)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:640: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[5:3];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:641: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter [2:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:653: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[3:2];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:654: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter [1:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:669: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[2:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:670: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter[7:3];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:230: Operator CASE expects 2 bits on the Case expression, but Case expression\'s VARREF \'difficulty\' generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.c0\n  case(difficulty)\n  ^~~~\n%Error: data/full_repos/permissive/146689564/whac_a_mole_v3.v:60: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter.v\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter.sv\n             vga_adapter\n             vga_adapter.v\n             vga_adapter.sv\n             obj_dir/vga_adapter\n             obj_dir/vga_adapter.v\n             obj_dir/vga_adapter.sv\n%Error: data/full_repos/permissive/146689564/whac_a_mole_v3.v:88: Cannot find file containing module: \'keyboard_press_driver\'\n keyboard_press_driver KEYBOARD(\n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:139: Input port connection \'difficulty\' expects 1 bits on the pin connection, but pin connection\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3\n   .difficulty(SW[9:8]),\n    ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 48 warning(s)\n'
module control(
    input clk,
    input resetn,
    input go,
    input move, f,
	 input difficulty,
    output reg  draw_mole,draw_hammer, clear, erase, update, count, m,
	 output reg [3:0]frame,
    output reg [1:0]mole_id,
    output reg [5:0]current_state
    );

    reg [5:0]  next_state; 
    
    localparam  CLEAR = 6'd0,
		D_MOLE_1 = 6'd1,
		D_MOLE_2 = 6'd2,
		D_MOLE_3 = 6'd3,
		D_MOLE_4 = 6'd4,
		D_HAMMER_1 = 6'd5,
		D_HAMMER_2 = 6'd6,
		D_HAMMER_3 = 6'd7,
		D_HAMMER_4 = 6'd8,
		ERASE_1 = 6'd9,
		ERASE_2 = 6'd10,
		ERASE_3 = 6'd11,
		ERASE_4 = 6'd12,
		WAIT = 6'd13,
		UPDATE = 6'd14,
		COUNT_TIME = 6'd15,
		WAIT1 = 6'd16,
		WAIT2 = 6'd17,
		WAIT3 = 6'd18,
		WAIT4= 6'd19,
		EWAIT1= 6'd20,
		EWAIT2= 6'd21,
		EWAIT3= 6'd22,
		EWAIT4= 6'd23,
		HWAIT1= 6'd24,
		HWAIT2= 6'd25,
		HWAIT3= 6'd26,
		HWAIT4= 6'd27,
		COUNT_WAIT= 6'd28;
		
	always@(*)
	begin
	 case(difficulty)
	   2'd0: frame = 4'd14;
		2'd1: frame = 4'd9;
		2'd2: frame = 4'd4;
		default: frame = 4'd14;
	endcase
	end
		


    always@(*)
    begin: state_table 
            case (current_state)
		CLEAR: next_state = move ? WAIT : CLEAR; 
		WAIT: next_state = go ? D_MOLE_1 : WAIT;
		D_MOLE_1: next_state = move ? WAIT1 : D_MOLE_1;
		WAIT1: next_state = D_MOLE_2;
		D_MOLE_2: next_state = move ? WAIT2 : D_MOLE_2;
		WAIT2: next_state = D_MOLE_3;
		D_MOLE_3: next_state = move ? WAIT3 : D_MOLE_3;
		WAIT3: next_state = D_MOLE_4;
		D_MOLE_4: next_state = move ? WAIT4 : D_MOLE_4;
		WAIT4:next_state = COUNT_TIME;
		COUNT_TIME :  next_state = f ? COUNT_WAIT : COUNT_TIME;
		COUNT_WAIT: next_state = ERASE_1;
		ERASE_1: next_state = move? EWAIT1 : ERASE_1;
		EWAIT1: next_state = ERASE_2;
		ERASE_2: next_state = move? EWAIT2 : ERASE_2;
		EWAIT2: next_state = ERASE_3;
		ERASE_3: next_state = move? EWAIT3 : ERASE_3;
		EWAIT3: next_state = ERASE_4;
		ERASE_4: next_state = move? EWAIT4 : ERASE_4;
		EWAIT4: next_state = UPDATE;
		UPDATE: next_state = D_HAMMER_1;
		D_HAMMER_1 : next_state = move ? HWAIT1 : D_HAMMER_1;
		HWAIT1: next_state = D_HAMMER_2;
		D_HAMMER_2 : next_state = move ? HWAIT2 : D_HAMMER_2;
		HWAIT2: next_state = D_HAMMER_3;
		D_HAMMER_3 : next_state = move ? HWAIT3 : D_HAMMER_3;
		HWAIT3: next_state = D_HAMMER_4;
		D_HAMMER_4 : next_state = move ? HWAIT4 : D_HAMMER_4;
		HWAIT4: next_state = D_MOLE_1;
		
      default:     next_state = CLEAR;
      endcase
    end
   


    always @(*)
    begin: enable_signals

	erase = 1'b0;
   draw_mole = 1'b0;
	draw_hammer = 1'b0;
	clear = 1'b0;
	mole_id = 2'd0;
	update = 1'b0;
	count = 1'b0;
	m = 1'b1;

        case (current_state)
            CLEAR: begin
		clear = 1'b1;
		m = 1'b0;
                end
            D_MOLE_1: begin
		draw_mole = 1'b1;
				m = 1'b0;
                end
            D_MOLE_2: begin
		draw_mole = 1'b1;
		mole_id = 2'd1;
				m = 1'b0;
                end
            D_MOLE_3: begin
		draw_mole = 1'b1;
		mole_id = 2'd2;
				m = 1'b0;
                end
            D_MOLE_4: begin
		draw_mole = 1'b1;
		mole_id = 2'd3;
				m = 1'b0;
                end
	    D_HAMMER_1: begin
		draw_hammer = 1'b1;
				m = 1'b0;
                end
            D_HAMMER_2: begin
		draw_hammer = 1'b1;
		mole_id = 2'd1;
				m = 1'b0;
                end
            D_HAMMER_3: begin
		draw_hammer = 1'b1;
		mole_id = 2'd2;
				m = 1'b0;
                end
            D_HAMMER_4: begin
		draw_hammer = 1'b1;
		mole_id = 2'd3;
				m = 1'b0;
                end
	    ERASE_1: begin
		erase = 1'b1;
				m = 1'b0;
		end
	    ERASE_2: begin
		erase = 1'b1;
		mole_id = 2'd1;
				m = 1'b0;
                end
            ERASE_3: begin
		erase = 1'b1;
		mole_id = 2'd2;
				m = 1'b0;
                end
            ERASE_4: begin
		erase = 1'b1;
		mole_id = 2'd3;
				m = 1'b0;
                end
	    UPDATE: begin
		update = 1'b1;
				m = 1'b0;

		end
	    COUNT_TIME: begin
		count = 1'b1;
				m = 1'b0;
		end


        endcase
    end

 
   always@(posedge clk)
    begin:state_FFs 
        if(resetn == 0)
            current_state <= CLEAR;
        else
            current_state <= next_state;
    end


endmodule
module control(
    input clk,
    input resetn,
    input go,
    input move, f,
	 input difficulty,
    output reg  draw_mole,draw_hammer, clear, erase, update, count, m,
	 output reg [3:0]frame,
    output reg [1:0]mole_id,
    output reg [5:0]current_state
    );


    reg [5:0]  next_state; 
    
    localparam  CLEAR = 6'd0,
		D_MOLE_1 = 6'd1,
		D_MOLE_2 = 6'd2,
		D_MOLE_3 = 6'd3,
		D_MOLE_4 = 6'd4,
		D_HAMMER_1 = 6'd5,
		D_HAMMER_2 = 6'd6,
		D_HAMMER_3 = 6'd7,
		D_HAMMER_4 = 6'd8,
		ERASE_1 = 6'd9,
		ERASE_2 = 6'd10,
		ERASE_3 = 6'd11,
		ERASE_4 = 6'd12,
		WAIT = 6'd13,
		UPDATE = 6'd14,
		COUNT_TIME = 6'd15,
		WAIT1 = 6'd16,
		WAIT2 = 6'd17,
		WAIT3 = 6'd18,
		WAIT4= 6'd19,
		EWAIT1= 6'd20,
		EWAIT2= 6'd21,
		EWAIT3= 6'd22,
		EWAIT4= 6'd23,
		HWAIT1= 6'd24,
		HWAIT2= 6'd25,
		HWAIT3= 6'd26,
		HWAIT4= 6'd27,
		COUNT_WAIT= 6'd28;
		
	always@(*)
	begin
	 case(difficulty)
	   2'd0: frame = 4'd14;
		2'd1: frame = 4'd9;
		2'd2: frame = 4'd4;
		default: frame = 4'd14;
	endcase
	end
		


    always@(*)
    begin: state_table 
            case (current_state)
		CLEAR: next_state = move ? WAIT : CLEAR; 
		WAIT: next_state = go ? D_MOLE_1 : WAIT;
		D_MOLE_1: next_state = move ? WAIT1 : D_MOLE_1;
		WAIT1: next_state = D_MOLE_2;
		D_MOLE_2: next_state = move ? WAIT2 : D_MOLE_2;
		WAIT2: next_state = D_MOLE_3;
		D_MOLE_3: next_state = move ? WAIT3 : D_MOLE_3;
		WAIT3: next_state = D_MOLE_4;
		D_MOLE_4: next_state = move ? WAIT4 : D_MOLE_4;
		WAIT4:next_state = COUNT_TIME;
		COUNT_TIME :  next_state = f ? COUNT_WAIT : COUNT_TIME;
		COUNT_WAIT: next_state = ERASE_1;
		ERASE_1: next_state = move? EWAIT1 : ERASE_1;
		EWAIT1: next_state = ERASE_2;
		ERASE_2: next_state = move? EWAIT2 : ERASE_2;
		EWAIT2: next_state = ERASE_3;
		ERASE_3: next_state = move? EWAIT3 : ERASE_3;
		EWAIT3: next_state = ERASE_4;
		ERASE_4: next_state = move? EWAIT4 : ERASE_4;
		EWAIT4: next_state = UPDATE;
		UPDATE: next_state = D_HAMMER_1;
		D_HAMMER_1 : next_state = move ? HWAIT1 : D_HAMMER_1;
		HWAIT1: next_state = D_HAMMER_2;
		D_HAMMER_2 : next_state = move ? HWAIT2 : D_HAMMER_2;
		HWAIT2: next_state = D_HAMMER_3;
		D_HAMMER_3 : next_state = move ? HWAIT3 : D_HAMMER_3;
		HWAIT3: next_state = D_HAMMER_4;
		D_HAMMER_4 : next_state = move ? HWAIT4 : D_HAMMER_4;
		HWAIT4: next_state = D_MOLE_1;
		
      default:     next_state = CLEAR;
      endcase
    end
   


    always @(*)
    begin: enable_signals

	erase = 1'b0;
   draw_mole = 1'b0;
	draw_hammer = 1'b0;
	clear = 1'b0;
	mole_id = 2'd0;
	update = 1'b0;
	count = 1'b0;
	m = 1'b1;

        case (current_state)
            CLEAR: begin
		clear = 1'b1;
		m = 1'b0;
                end
            D_MOLE_1: begin
		draw_mole = 1'b1;
				m = 1'b0;
                end
            D_MOLE_2: begin
		draw_mole = 1'b1;
		mole_id = 2'd1;
				m = 1'b0;
                end
            D_MOLE_3: begin
		draw_mole = 1'b1;
		mole_id = 2'd2;
				m = 1'b0;
                end
            D_MOLE_4: begin
		draw_mole = 1'b1;
		mole_id = 2'd3;
				m = 1'b0;
                end
	    D_HAMMER_1: begin
		draw_hammer = 1'b1;
				m = 1'b0;
                end
            D_HAMMER_2: begin
		draw_hammer = 1'b1;
		mole_id = 2'd1;
				m = 1'b0;
                end
            D_HAMMER_3: begin
		draw_hammer = 1'b1;
		mole_id = 2'd2;
				m = 1'b0;
                end
            D_HAMMER_4: begin
		draw_hammer = 1'b1;
		mole_id = 2'd3;
				m = 1'b0;
                end
	    ERASE_1: begin
		erase = 1'b1;
				m = 1'b0;
		end
	    ERASE_2: begin
		erase = 1'b1;
		mole_id = 2'd1;
				m = 1'b0;
                end
            ERASE_3: begin
		erase = 1'b1;
		mole_id = 2'd2;
				m = 1'b0;
                end
            ERASE_4: begin
		erase = 1'b1;
		mole_id = 2'd3;
				m = 1'b0;
                end
	    UPDATE: begin
		update = 1'b1;
				m = 1'b0;

		end
	    COUNT_TIME: begin
		count = 1'b1;
				m = 1'b0;
		end


        endcase
    end

 
   always@(posedge clk)
    begin:state_FFs 
        if(resetn == 0)
            current_state <= CLEAR;
        else
            current_state <= next_state;
    end


endmodule