data/full_repos/permissive/156539908/first-demo/first-demo.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/156539908/first-demo/first-demo.v:189: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'top\'\nmodule top (\n       ^~~\n                                                                                   : ... Top module \'button_debouncer\'\nmodule button_debouncer (\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156539908/first-demo/first-demo.v:279: Cannot find file containing module: \'SB_IO\'\n    SB_IO #(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/156539908/first-demo,data/full_repos/permissive/156539908/SB_IO\n             data/full_repos/permissive/156539908/first-demo,data/full_repos/permissive/156539908/SB_IO.v\n             data/full_repos/permissive/156539908/first-demo,data/full_repos/permissive/156539908/SB_IO.sv\n             SB_IO\n             SB_IO.v\n             SB_IO.sv\n             obj_dir/SB_IO\n             obj_dir/SB_IO.v\n             obj_dir/SB_IO.sv\n%Error: data/full_repos/permissive/156539908/first-demo/first-demo.v:267: Cannot find file containing module: \'SB_GB\'\n    SB_GB rst_gb (\n    ^~~~~\n%Error: data/full_repos/permissive/156539908/first-demo/first-demo.v:234: Cannot find file containing module: \'SB_PLL40_PAD\'\n    SB_PLL40_PAD #(\n    ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:66: Operator ASSIGNW expects 21 bits on the Assign RHS, but Assign RHS\'s VARREF \'frame_counter\' generates 20 bits.\n                                                                               : ... In instance top\n    assign {frame, subframe} = frame_counter;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:88: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 6 bits.\n                                                                               : ... In instance top\n    assign xx = x + frame[5:0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:89: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'y0\' generates 6 bits.\n                                                                               : ... In instance top\n    assign yy0 = y0 + frame[5:2];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:89: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                               : ... In instance top\n    assign yy0 = y0 + frame[5:2];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:90: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'y1\' generates 6 bits.\n                                                                               : ... In instance top\n    assign yy1 = y1 + frame[5:2];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:90: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                               : ... In instance top\n    assign yy1 = y1 + frame[5:2];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:91: Operator XOR expects 8 bits on the LHS, but LHS\'s VARREF \'x\' generates 7 bits.\n                                                                               : ... In instance top\n    assign xort = x ^ frame[9:2];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:91: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s XOR generates 8 bits.\n                                                                               : ... In instance top\n    assign xort = x ^ frame[9:2];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:99: Operator ASSIGNW expects 24 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                               : ... In instance top\n    assign rgb0 = {red0 > cmp, grn0 > cmp, blu0 > cmp};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:100: Operator ASSIGNW expects 24 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                                : ... In instance top\n    assign rgb1 = {red1 > cmp, grn1 > cmp, blu1 > cmp};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:161: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'rgb0\' generates 24 bits.\n                                                                                : ... In instance top\n                        led_rgb0  <= rgb0;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:162: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'rgb1\' generates 24 bits.\n                                                                                : ... In instance top\n                        led_rgb1  <= rgb1;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:209: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'counter\' generates 13 bits.\n                                                                                : ... In instance button_debouncer\n        if (counter) begin\n        ^~\n%Error: Exiting due to 3 error(s), 14 warning(s)\n'
module top (
        input  CLK,
        input  BTN_N,
        output LED1,
        output LED2,
        output LED3,
        output LED4,
        output LED5,
        output LEDR_N,
        output LEDG_N,
        output P1A1,
        output P1A2,
        output P1A3,
        output P1A7,
        output P1A8,
        output P1A9,
        output P1B1,
        output P1B2,
        output P1B3,
        output P1B4,
        output P1B7,
        output P1B8,
        output P1B9,
        output P1B10);

    localparam  S_START   = 8'b00000001;
    localparam  S_BLANK   = 8'b00000010;
    localparam  S_LATCH   = 8'b00000100;
    localparam  S_UNLATCH = 8'b00001000;
    localparam  S_UNBLANK = 8'b00010000;
    localparam  S_SHIFT   = 8'b00100000;

    wire        clk30_locked;
    wire        clk30;
    wire        reset;

    wire  [7:0] subframe;
    wire [12:0] frame;
    wire  [5:0] y0, y1;
    wire [23:0] rgb0, rgb1;
    wire  [7:0] cmp;

    reg   [2:0] led_rgb0;
    reg   [2:0] led_rgb1;
    reg   [4:0] led_addr;
    reg         led_blank;
    reg         led_latch;
    wire        led_sclk;

    reg   [6:0] x;
    reg   [4:0] addr;
    reg  [19:0] frame_counter;
    reg   [7:0] state;
    reg         sclk_ena;


    assign {P1A3, P1A2, P1A1}              = led_rgb0;
    assign {P1A9, P1A8, P1A7}              = led_rgb1;
    assign {P1B10, P1B4, P1B3, P1B2, P1B1} = led_addr;
    assign P1B7                            = led_blank;
    assign P1B8                            = led_latch;
    assign P1B9                            = led_sclk;

    assign {frame, subframe} = frame_counter;
    assign y0 = {1'b0, addr};
    assign y1 = {1'b1, addr};

    assign cmp = {subframe[0], subframe[1], subframe[2], subframe[3],
                  subframe[4], subframe[5], subframe[6], subframe[7]};













    wire [7:0] xx, yy0, yy1;
    wire [5:0] xort;
    wire [7:0] red0, red1, grn0, grn1, blu0, blu1;
    assign xx = x + frame[5:0];
    assign yy0 = y0 + frame[5:2];
    assign yy1 = y1 + frame[5:2];
    assign xort = x ^ frame[9:2];
    assign red0 = (xx[3] & yy0[3]) ? xx & 8'h07 : 0;
    assign grn0 = (xx[3] & yy0[3]) ? yy0 & 8'h07 : 0;
    assign blu0 = (xort == y0) ? 8'hBB : 8'h00;
    assign red1 = (xx[3] & yy1[3]) ? xx & 8'h07 : 0;
    assign grn1 = (xx[3] & yy1[3]) ? yy1 & 8'h07 : 0;
    assign blu1 = (xort == y1) ? 8'hBB : 8'h00;

    assign rgb0 = {red0 > cmp, grn0 > cmp, blu0 > cmp};
    assign rgb1 = {red1 > cmp, grn1 > cmp, blu1 > cmp};






    always @(posedge clk30)
        if (reset) begin
            led_rgb0              <= 0;
            led_rgb1              <= 0;
            led_addr              <= 0;
            led_blank             <= 0;
            led_latch             <= 0;
            addr                  <= 0;
            frame_counter         <= 0;
            x                     <= 0;
            state                 <= S_START;
            sclk_ena              <= 0;
        end
        else
            case (state)

                S_START:
                    state         <= S_BLANK;

                S_BLANK:
                    begin
                        led_blank <= 1;
                        led_addr  <= addr;
                        state     <= S_LATCH;
                    end

                S_LATCH:
                    begin
                        led_latch <= 1;
                        state     <= S_UNLATCH;
                    end

                S_UNLATCH:
                    begin
                        led_latch <= 0;
                        state     <= S_UNBLANK;
                    end

                S_UNBLANK:
                    begin
                        led_blank <= 0;
                        x         <= 0;
                        addr      <= addr + 1;
                        if (addr == 31)
                            frame_counter <= frame_counter + 1;
                        state     <= S_SHIFT;
                    end

                S_SHIFT:
                    if (x[6]) begin
                        sclk_ena  <= 0;
                        state     <= S_BLANK;
                    end
                    else begin
                        led_rgb0  <= rgb0;
                        led_rgb1  <= rgb1;
                        x         <= x + 1;
                        sclk_ena  <= 1;
                        state     <= S_SHIFT;
                    end

            endcase

    pll_30mhz pll(
        .clk_pin(CLK),
        .reset_pin(~BTN_N),
        .locked(clk30_locked),
        .clk30(clk30));

    reset_logic rl(
        .pll_clk(clk30),
        .pll_locked(clk30_locked),
        .reset(reset));

    ddr led_sclk_ddr(
        .clk(clk30),
        .ena(sclk_ena),
        .sclk(led_sclk));

endmodule
module top (
        input  CLK,
        input  BTN_N,
        output LED1,
        output LED2,
        output LED3,
        output LED4,
        output LED5,
        output LEDR_N,
        output LEDG_N,
        output P1A1,
        output P1A2,
        output P1A3,
        output P1A7,
        output P1A8,
        output P1A9,
        output P1B1,
        output P1B2,
        output P1B3,
        output P1B4,
        output P1B7,
        output P1B8,
        output P1B9,
        output P1B10);


    localparam  S_START   = 8'b00000001;
    localparam  S_BLANK   = 8'b00000010;
    localparam  S_LATCH   = 8'b00000100;
    localparam  S_UNLATCH = 8'b00001000;
    localparam  S_UNBLANK = 8'b00010000;
    localparam  S_SHIFT   = 8'b00100000;

    wire        clk30_locked;
    wire        clk30;
    wire        reset;

    wire  [7:0] subframe;
    wire [12:0] frame;
    wire  [5:0] y0, y1;
    wire [23:0] rgb0, rgb1;
    wire  [7:0] cmp;

    reg   [2:0] led_rgb0;
    reg   [2:0] led_rgb1;
    reg   [4:0] led_addr;
    reg         led_blank;
    reg         led_latch;
    wire        led_sclk;

    reg   [6:0] x;
    reg   [4:0] addr;
    reg  [19:0] frame_counter;
    reg   [7:0] state;
    reg         sclk_ena;


    assign {P1A3, P1A2, P1A1}              = led_rgb0;
    assign {P1A9, P1A8, P1A7}              = led_rgb1;
    assign {P1B10, P1B4, P1B3, P1B2, P1B1} = led_addr;
    assign P1B7                            = led_blank;
    assign P1B8                            = led_latch;
    assign P1B9                            = led_sclk;

    assign {frame, subframe} = frame_counter;
    assign y0 = {1'b0, addr};
    assign y1 = {1'b1, addr};

    assign cmp = {subframe[0], subframe[1], subframe[2], subframe[3],
                  subframe[4], subframe[5], subframe[6], subframe[7]};













    wire [7:0] xx, yy0, yy1;
    wire [5:0] xort;
    wire [7:0] red0, red1, grn0, grn1, blu0, blu1;
    assign xx = x + frame[5:0];
    assign yy0 = y0 + frame[5:2];
    assign yy1 = y1 + frame[5:2];
    assign xort = x ^ frame[9:2];
    assign red0 = (xx[3] & yy0[3]) ? xx & 8'h07 : 0;
    assign grn0 = (xx[3] & yy0[3]) ? yy0 & 8'h07 : 0;
    assign blu0 = (xort == y0) ? 8'hBB : 8'h00;
    assign red1 = (xx[3] & yy1[3]) ? xx & 8'h07 : 0;
    assign grn1 = (xx[3] & yy1[3]) ? yy1 & 8'h07 : 0;
    assign blu1 = (xort == y1) ? 8'hBB : 8'h00;

    assign rgb0 = {red0 > cmp, grn0 > cmp, blu0 > cmp};
    assign rgb1 = {red1 > cmp, grn1 > cmp, blu1 > cmp};






    always @(posedge clk30)
        if (reset) begin
            led_rgb0              <= 0;
            led_rgb1              <= 0;
            led_addr              <= 0;
            led_blank             <= 0;
            led_latch             <= 0;
            addr                  <= 0;
            frame_counter         <= 0;
            x                     <= 0;
            state                 <= S_START;
            sclk_ena              <= 0;
        end
        else
            case (state)

                S_START:
                    state         <= S_BLANK;

                S_BLANK:
                    begin
                        led_blank <= 1;
                        led_addr  <= addr;
                        state     <= S_LATCH;
                    end

                S_LATCH:
                    begin
                        led_latch <= 1;
                        state     <= S_UNLATCH;
                    end

                S_UNLATCH:
                    begin
                        led_latch <= 0;
                        state     <= S_UNBLANK;
                    end

                S_UNBLANK:
                    begin
                        led_blank <= 0;
                        x         <= 0;
                        addr      <= addr + 1;
                        if (addr == 31)
                            frame_counter <= frame_counter + 1;
                        state     <= S_SHIFT;
                    end

                S_SHIFT:
                    if (x[6]) begin
                        sclk_ena  <= 0;
                        state     <= S_BLANK;
                    end
                    else begin
                        led_rgb0  <= rgb0;
                        led_rgb1  <= rgb1;
                        x         <= x + 1;
                        sclk_ena  <= 1;
                        state     <= S_SHIFT;
                    end

            endcase

    pll_30mhz pll(
        .clk_pin(CLK),
        .reset_pin(~BTN_N),
        .locked(clk30_locked),
        .clk30(clk30));

    reset_logic rl(
        .pll_clk(clk30),
        .pll_locked(clk30_locked),
        .reset(reset));

    ddr led_sclk_ddr(
        .clk(clk30),
        .ena(sclk_ena),
        .sclk(led_sclk));

endmodule