data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog/seg_execute_alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog/seg_execute_alu.v:44: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                                               : ... In instance seg_execute_alu\n            4\'b0111: o_ALUOut = signed_data_a < signed_data_b;   \n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module seg_execute_alu
    #( parameter 
        LEN         = 32,
        NB_ALUCTL   = 4
    )
    (
        input wire  [NB_ALUCTL - 1: 0]  i_ALUctl,
        input wire  [LEN - 1: 0]    i_data_a,
        input wire  [LEN - 1: 0]    i_data_b,
        output reg  [LEN - 1: 0]    o_ALUOut,
        output wire                 o_zero
    );
    
    reg signed  [LEN-1: 0]      signed_data_a;
    reg signed  [LEN-1: 0]      signed_data_b;
    wire        [LEN - 1: 0]    sub_ab;
	wire        [LEN - 1: 0]    add_ab;
	wire                        oflow_sub;


    assign o_zero = (o_ALUOut == 0) ? 1'b1 : 1'b0;

	assign sub_ab = i_data_a - i_data_b;

	assign oflow_sub = (i_data_a[LEN - 1] == i_data_b[LEN - 1] && sub_ab[LEN - 1] != i_data_a[LEN - 1]) ? 1 : 0;


    always@(*)
    begin
        signed_data_a = i_data_a;
        signed_data_b = i_data_b;
    end

    always @(*) begin
        case (i_ALUctl)
            4'b0000: o_ALUOut = i_data_a & i_data_b;
            4'b0001: o_ALUOut = i_data_a | i_data_b;
            4'b0010: o_ALUOut = i_data_a + i_data_b;
            4'b0011: o_ALUOut = signed_data_a + signed_data_b;
            4'b0110: o_ALUOut = i_data_a - i_data_b;

            4'b0111: o_ALUOut = signed_data_a < signed_data_b;
            4'b1000: o_ALUOut = i_data_b << 16;
            4'b1001: o_ALUOut = i_data_a ^ i_data_b;
            4'b1010: o_ALUOut = ~(i_data_a | i_data_b);
            4'b1011: o_ALUOut = i_data_a << i_data_b;
            4'b1100: o_ALUOut = i_data_a >> i_data_b;
            4'b1101: o_ALUOut = signed_data_a >>> i_data_b;


            default: o_ALUOut = i_data_a + i_data_b;
        endcase
    end
  
endmodule
module seg_execute_alu
    #( parameter 
        LEN         = 32,
        NB_ALUCTL   = 4
    )
    (
        input wire  [NB_ALUCTL - 1: 0]  i_ALUctl,
        input wire  [LEN - 1: 0]    i_data_a,
        input wire  [LEN - 1: 0]    i_data_b,
        output reg  [LEN - 1: 0]    o_ALUOut,
        output wire                 o_zero
    );

    
    reg signed  [LEN-1: 0]      signed_data_a;
    reg signed  [LEN-1: 0]      signed_data_b;
    wire        [LEN - 1: 0]    sub_ab;
	wire        [LEN - 1: 0]    add_ab;
	wire                        oflow_sub;


    assign o_zero = (o_ALUOut == 0) ? 1'b1 : 1'b0;

	assign sub_ab = i_data_a - i_data_b;

	assign oflow_sub = (i_data_a[LEN - 1] == i_data_b[LEN - 1] && sub_ab[LEN - 1] != i_data_a[LEN - 1]) ? 1 : 0;


    always@(*)
    begin
        signed_data_a = i_data_a;
        signed_data_b = i_data_b;
    end

    always @(*) begin
        case (i_ALUctl)
            4'b0000: o_ALUOut = i_data_a & i_data_b;
            4'b0001: o_ALUOut = i_data_a | i_data_b;
            4'b0010: o_ALUOut = i_data_a + i_data_b;
            4'b0011: o_ALUOut = signed_data_a + signed_data_b;
            4'b0110: o_ALUOut = i_data_a - i_data_b;

            4'b0111: o_ALUOut = signed_data_a < signed_data_b;
            4'b1000: o_ALUOut = i_data_b << 16;
            4'b1001: o_ALUOut = i_data_a ^ i_data_b;
            4'b1010: o_ALUOut = ~(i_data_a | i_data_b);
            4'b1011: o_ALUOut = i_data_a << i_data_b;
            4'b1100: o_ALUOut = i_data_a >> i_data_b;
            4'b1101: o_ALUOut = signed_data_a >>> i_data_b;


            default: o_ALUOut = i_data_a + i_data_b;
        endcase
    end
  
endmodule