data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/REG_MUXER.v
data/verilator_xmls/c94e0a0a-7f04-4165-8e96-7cbf2cc23254.xml
module REG_MUXER(
	input [4:0] reg1,
	input [4:0] reg2,
	input [4:0] reg3,

	input Wr,
	input [1:0] optype,
	
	output reg [4:0] regaddr1,
	output reg [4:0] regaddr2,
	output reg [4:0] regaddr3
);

always@(*)
begin
	if(optype==2'h0)
	begin
		regaddr1=reg1;
		regaddr2=reg2;
		regaddr3=reg3;
	end
	else if(optype==2'h1)
	begin
		if(Wr)
		begin
			regaddr1=reg1;
			regaddr2=reg2;
		end
		else
		begin
			regaddr1=reg1;
			regaddr3=reg2;
		end
	end

end

endmodule
module REG_MUXER(
	input [4:0] reg1,
	input [4:0] reg2,
	input [4:0] reg3,

	input Wr,
	input [1:0] optype,
	
	output reg [4:0] regaddr1,
	output reg [4:0] regaddr2,
	output reg [4:0] regaddr3
);


always@(*)
begin
	if(optype==2'h0)
	begin
		regaddr1=reg1;
		regaddr2=reg2;
		regaddr3=reg3;
	end
	else if(optype==2'h1)
	begin
		if(Wr)
		begin
			regaddr1=reg1;
			regaddr2=reg2;
		end
		else
		begin
			regaddr1=reg1;
			regaddr3=reg2;
		end
	end

end

endmodule