data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataReg.v
data/verilator_xmls/1ed52a17-f077-4bf7-baff-ae8153d5ec75.xml
module DataReg(
DataIn, DataOut, CLK
);
   input wire [31:0] DataIn;
   output reg [31:0] DataOut;
   input  CLK;
   
   always @(posedge CLK)begin
          DataOut = DataIn;  
   end

endmodule
module DataReg(
DataIn, DataOut, CLK
);

   input wire [31:0] DataIn;
   output reg [31:0] DataOut;
   input  CLK;
   
   always @(posedge CLK)begin
          DataOut = DataIn;  
   end

endmodule