data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton.v
 line:35: before: "("
1: b"%Error: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton.v:60: Cannot find file containing module: 'block'\n      block Bi( { in[ (i==0) ? WIDTH-1 : (i-1) ], in[i], in[ ( i == (WIDTH-1) ) ? 0 : i+1 ] }, rule, out[i] );\n      ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/128117771/Automaton-Verilog-Nbits,data/full_repos/permissive/128117771/block\n             data/full_repos/permissive/128117771/Automaton-Verilog-Nbits,data/full_repos/permissive/128117771/block.v\n             data/full_repos/permissive/128117771/Automaton-Verilog-Nbits,data/full_repos/permissive/128117771/block.sv\n             block\n             block.v\n             block.sv\n             obj_dir/block\n             obj_dir/block.v\n             obj_dir/block.sv\n%Error: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton.v:17: Cannot find file containing module: 'prescaler'\n  prescaler #(.N(N)) PRES ( .clk_in(clk), .clk_out(clk_base) );\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton.v:21: Cannot find file containing module: 'init'\n  init INIT ( clk_base, sel );\n  ^~~~\n%Error: Exiting due to 3 error(s)\n"
module automaton #(parameter WIDTH = 8) 
  ( input wire clk,
    output wire [WIDTH-1:0] data
  );


  parameter N = 23;
  parameter SEED = 8'b00000001;
  parameter RULE = 129;
  
  wire [7:0] rule = RULE;


  wire clk_base;


  prescaler #(.N(N)) PRES ( .clk_in(clk), .clk_out(clk_base) );


  wire sel;
  init INIT ( clk_base, sel );




  wire [WIDTH-1:0] rin;


  assign data = (sel == 0) ? SEED : rout;

  cellAutomaton #(.WIDTH(WIDTH)) CA ( .in(data), .rule(rule), .out(rin));


  reg [WIDTH-1:0] rout;
  always @(posedge(clk_base))
    rout <= rin;

endmodule
module automaton #(parameter WIDTH = 8) 
  ( input wire clk,
    output wire [WIDTH-1:0] data
  );



  parameter N = 23;
  parameter SEED = 8'b00000001;
  parameter RULE = 129;
  
  wire [7:0] rule = RULE;


  wire clk_base;


  prescaler #(.N(N)) PRES ( .clk_in(clk), .clk_out(clk_base) );


  wire sel;
  init INIT ( clk_base, sel );




  wire [WIDTH-1:0] rin;


  assign data = (sel == 0) ? SEED : rout;

  cellAutomaton #(.WIDTH(WIDTH)) CA ( .in(data), .rule(rule), .out(rin));


  reg [WIDTH-1:0] rout;
  always @(posedge(clk_base))
    rout <= rin;

endmodule