data/full_repos/permissive/184721104/test/test_main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_main.v:30: Unsupported: Ignoring delay on this delayed statement.\n    CLK =0; #(STEP/2);\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_main.v:31: Unsupported: Ignoring delay on this delayed statement.\n    CLK =1; #(STEP/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_main.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP*10);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_main.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP*10);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_main.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #(STEP);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_main.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP*150);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_main.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #(STEP);\n        ^\n%Error: data/full_repos/permissive/184721104/test/test_main.v:17: Cannot find file containing module: \'main\'\nmain main(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/184721104/test,data/full_repos/permissive/184721104/main\n             data/full_repos/permissive/184721104/test,data/full_repos/permissive/184721104/main.v\n             data/full_repos/permissive/184721104/test,data/full_repos/permissive/184721104/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Warning-WIDTH: data/full_repos/permissive/184721104/test/test_main.v:51: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'R\' generates 6 bits.\n                                                                        : ... In instance test_main\n            $fwrite(fp,"%c", 8\'d00 | (R<<2));\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/184721104/test/test_main.v:52: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'G\' generates 6 bits.\n                                                                        : ... In instance test_main\n            $fwrite(fp,"%c", 8\'h00 | (G<<2));\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/184721104/test/test_main.v:53: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'B\' generates 6 bits.\n                                                                        : ... In instance test_main\n            $fwrite(fp,"%c", 8\'h00 | (B<<2));\n                                       ^~\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_main;

localparam STEP = 8;
localparam CLKNUM = 4200000;

reg CLK;
reg RST;
reg PCK_before;

wire PCK;
wire HS;
wire VS;
wire [5:0]R;
wire [5:0]G;
wire [5:0]B;

main main(
    .CLK(CLK),
    .RST(RST),

    .PCK(PCK),
    .HS(HS),
    .VS(VS),
    .R(R),
    .G(G),
    .B(B)
);

always begin
    CLK =0; #(STEP/2);
    CLK =1; #(STEP/2);
end

integer fp;

initial begin
    fp = $fopen("main_img.raw","wb");

    RST=1;
    #(STEP*10);
    RST=0;
    #(STEP*10);

    PCK_before =0;
    while (VS == 0)begin
        #(STEP);
    end
    #(STEP*150);
    while (VS == 0)begin
        if(PCK != PCK_before && PCK==1)begin
            $fwrite(fp,"%c", 8'd00 | (R<<2));
            $fwrite(fp,"%c", 8'h00 | (G<<2));
            $fwrite(fp,"%c", 8'h00 | (B<<2));
        end
        PCK_before = PCK;
        #(STEP);
    end

    $fclose(fp);
    $finish;
end

initial begin
end

endmodule
module test_main;


localparam STEP = 8;
localparam CLKNUM = 4200000;

reg CLK;
reg RST;
reg PCK_before;

wire PCK;
wire HS;
wire VS;
wire [5:0]R;
wire [5:0]G;
wire [5:0]B;

main main(
    .CLK(CLK),
    .RST(RST),

    .PCK(PCK),
    .HS(HS),
    .VS(VS),
    .R(R),
    .G(G),
    .B(B)
);

always begin
    CLK =0; #(STEP/2);
    CLK =1; #(STEP/2);
end

integer fp;

initial begin
    fp = $fopen("main_img.raw","wb");

    RST=1;
    #(STEP*10);
    RST=0;
    #(STEP*10);

    PCK_before =0;
    while (VS == 0)begin
        #(STEP);
    end
    #(STEP*150);
    while (VS == 0)begin
        if(PCK != PCK_before && PCK==1)begin
            $fwrite(fp,"%c", 8'd00 | (R<<2));
            $fwrite(fp,"%c", 8'h00 | (G<<2));
            $fwrite(fp,"%c", 8'h00 | (B<<2));
        end
        PCK_before = PCK;
        #(STEP);
    end

    $fclose(fp);
    $finish;
end

initial begin
end

endmodule