data/full_repos/permissive/157101210/adder.v
data/verilator_xmls/e7c95d2e-5b90-4fdb-b3e3-16c92e499139.xml
module didOverflow1
(
    output overflow,
    input a, 
    input b, 
    input s
); 



    wire notA;
    wire notB;
    wire notS;
    wire aAndB;
    wire notaAndNotb;
    wire negToPos;
    wire posToNeg;

    not aNot(notA, a);
    not bNot(notB, b);
    not sNot(notS, s);

    and andab(aAndB, a, b);
    and andabNot(notaAndNotb, notA, notB);

    and andSwitch1(negToPos, aAndB, notS);
    and andSwitch2(posToNeg, notaAndNotb, s);

    or orGate(overflow, negToPos, posToNeg); 

endmodule
module didOverflow1
(
    output overflow,
    input a, 
    input b, 
    input s
);
 



    wire notA;
    wire notB;
    wire notS;
    wire aAndB;
    wire notaAndNotb;
    wire negToPos;
    wire posToNeg;

    not aNot(notA, a);
    not bNot(notB, b);
    not sNot(notS, s);

    and andab(aAndB, a, b);
    and andabNot(notaAndNotb, notA, notB);

    and andSwitch1(negToPos, aAndB, notS);
    and andSwitch2(posToNeg, notaAndNotb, s);

    or orGate(overflow, negToPos, posToNeg); 

endmodule