data/full_repos/permissive/172538466/hw/src/sim0/stim_uart.v
None: at end of input
1: b'%Error: data/full_repos/permissive/172538466/hw/src/sim0/stim_uart.v:1: Cannot find include file: defs.vh\n`include "defs.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172538466/hw/src/sim0,data/full_repos/permissive/172538466/defs.vh\n             data/full_repos/permissive/172538466/hw/src/sim0,data/full_repos/permissive/172538466/defs.vh.v\n             data/full_repos/permissive/172538466/hw/src/sim0,data/full_repos/permissive/172538466/defs.vh.sv\n             defs.vh\n             defs.vh.v\n             defs.vh.sv\n             obj_dir/defs.vh\n             obj_dir/defs.vh.v\n             obj_dir/defs.vh.sv\n%Error: data/full_repos/permissive/172538466/hw/src/sim0/stim_uart.v:2: Cannot find include file: sim0.vh\n`include "sim0.vh" \n         ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/172538466/hw/src/sim0/stim_uart.v:25: Unsupported: Ignoring delay on this delayed statement.\n       # (T);\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/172538466/hw/src/sim0/stim_uart.v:34: Unsupported: Ignoring delay on this delayed statement.\n         # (T);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/172538466/hw/src/sim0/stim_uart.v:38: Unsupported: Ignoring delay on this delayed statement.\n       # (T * 4);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/172538466/hw/src/sim0/stim_uart.v:20: Unsupported: Ignoring delay on this delayed statement.\n     # (T * 20)\n     ^\n%Error: data/full_repos/permissive/172538466/hw/src/sim0/stim_uart.v:52: syntax error, unexpected \'@\'\n       @(negedge RX_I);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/172538466/hw/src/sim0/stim_uart.v:53: Unsupported: Ignoring delay on this delayed statement.\n       #(T / 2);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/172538466/hw/src/sim0/stim_uart.v:57: Unsupported: Ignoring delay on this delayed statement.\n         #(T);\n         ^\n%Error: data/full_repos/permissive/172538466/hw/src/sim0/stim_uart.v:62: syntax error, unexpected \'@\'\n       @(posedge RX_I);\n       ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n'
module stim_uart
  (
   input  CLK_I,
   input  RST_I,
   input  RX_I,
   output TX_O
   );

   localparam BITRATE = 115200;
   localparam T = 1000000000 / BITRATE;


   reg    TX_O;
   integer i, n;
   initial begin
     TX_O = 1;
     # (T * 20)

     for(n = 48; n < 58 ; n = n + 1) begin

       TX_O = 0;
       # (T);


       for(i = 0; i < 8; i = i + 1) begin
         if(n & (1 << i))
           TX_O = 1;
         else
           TX_O = 0;

         # (T);
       end

       TX_O = 1;
       # (T * 4);

     end
   end



   reg [7:0] rx_data;


   initial begin
     forever begin


       @(negedge RX_I);
       #(T / 2);


       repeat(8) begin
         #(T);
         rx_data = {RX_I, rx_data[7:1]};
       end


       @(posedge RX_I);


       $write("%c", rx_data);

     end
   end


endmodule
module stim_uart
  (
   input  CLK_I,
   input  RST_I,
   input  RX_I,
   output TX_O
   );


   localparam BITRATE = 115200;
   localparam T = 1000000000 / BITRATE;


   reg    TX_O;
   integer i, n;
   initial begin
     TX_O = 1;
     # (T * 20)

     for(n = 48; n < 58 ; n = n + 1) begin

       TX_O = 0;
       # (T);


       for(i = 0; i < 8; i = i + 1) begin
         if(n & (1 << i))
           TX_O = 1;
         else
           TX_O = 0;

         # (T);
       end

       TX_O = 1;
       # (T * 4);

     end
   end



   reg [7:0] rx_data;


   initial begin
     forever begin


       @(negedge RX_I);
       #(T / 2);


       repeat(8) begin
         #(T);
         rx_data = {RX_I, rx_data[7:1]};
       end


       @(posedge RX_I);


       $write("%c", rx_data);

     end
   end


endmodule