data/full_repos/permissive/168753118/rtl/misc/ENCODE_B.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/ENCODE_B.v:28: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                               : ... In instance ENCODE_B\n    4'b0001: data_wire = 2'b00;\n             ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/ENCODE_B.v:29: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                               : ... In instance ENCODE_B\n    4'b0010: data_wire = 2'b01;\n             ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/ENCODE_B.v:30: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                               : ... In instance ENCODE_B\n    4'b0100: data_wire = 2'b10;\n             ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/ENCODE_B.v:31: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                               : ... In instance ENCODE_B\n    4'b1000: data_wire = 2'b11;\n             ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/ENCODE_B.v:32: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                               : ... In instance ENCODE_B\n    default: data_wire = 2'b00;\n             ^~~~~~~~~\n%Error: Exiting due to 5 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module ENCODE_B (
  input [3:0] data_in,
  output [1:0] data_out
);

wire [1:0] data_wire;


always @ ( * ) begin
  case (data_in)
    4'b0001: data_wire = 2'b00;
    4'b0010: data_wire = 2'b01;
    4'b0100: data_wire = 2'b10;
    4'b1000: data_wire = 2'b11;
    default: data_wire = 2'b00;
  endcase
end


assign data_out = data_wire;

endmodule
module ENCODE_B (
  input [3:0] data_in,
  output [1:0] data_out
);


wire [1:0] data_wire;


always @ ( * ) begin
  case (data_in)
    4'b0001: data_wire = 2'b00;
    4'b0010: data_wire = 2'b01;
    4'b0100: data_wire = 2'b10;
    4'b1000: data_wire = 2'b11;
    default: data_wire = 2'b00;
  endcase
end


assign data_out = data_wire;

endmodule