data/full_repos/permissive/143278/ivltests/test_system.v
 line:17: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_system.v:24: Unsupported: Ignoring delay on this delayed statement.\ninitial forever #(T) clk = !clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/test_system.v:27: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/test_system.v:29: syntax error, unexpected \'@\'\n    repeat(6) @(negedge clk);\n              ^\n%Error: data/full_repos/permissive/143278/ivltests/test_system.v:34: syntax error, unexpected \'@\'\n  @(posedge reset);\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/test_system.v:38: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_system.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
parameter integer T = 25;
parameter integer P = 1000;
parameter integer M = 200;

int i;

bit clk = 0, reset = 0;

byte unsigned x;
wire [10:0] y;

initial forever #(T) clk = !clk;

initial begin
    @(negedge clk);
    reset = 1'b1;
    repeat(6) @(negedge clk);
    reset = 1'b0;
end

initial begin
  @(posedge reset);
  @(negedge reset);
  for (i = 0; i < M; i=i+1) begin
    x = {$random} % 255;
    @(negedge clk);
    if (y !== P-1) begin
      $display ("ERROR");
      $finish;
    end
  end
  #100;
  $display ("PASSED");
  $finish;
end

const_system #(P) duv (.clk(clk), .reset(reset), .x(x), .y(y) );



endmodule
module test;

parameter integer T = 25;
parameter integer P = 1000;
parameter integer M = 200;

int i;

bit clk = 0, reset = 0;

byte unsigned x;
wire [10:0] y;

initial forever #(T) clk = !clk;

initial begin
    @(negedge clk);
    reset = 1'b1;
    repeat(6) @(negedge clk);
    reset = 1'b0;
end

initial begin
  @(posedge reset);
  @(negedge reset);
  for (i = 0; i < M; i=i+1) begin
    x = {$random} % 255;
    @(negedge clk);
    if (y !== P-1) begin
      $display ("ERROR");
      $finish;
    end
  end
  #100;
  $display ("PASSED");
  $finish;
end

const_system #(P) duv (.clk(clk), .reset(reset), .x(x), .y(y) );



endmodule