data/full_repos/permissive/180624253/control_module.v
1: b'%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:524: Value too large for 6 bit number: 100\n       ({random_x,2\'b00, random_y,2\'b00} == {7\'d100,6\'d100}) ||\n                                                    ^~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:526: Value too large for 6 bit number: 100\n       ({random_x,2\'b00, random_y,2\'b00} == {7\'d20,6\'d100}))\n                                                   ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:86: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIALIZE\' generates 20 bits.\n                                                                        : ... In instance control_module\n    current_state <= INITIALIZE;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:101: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                         : ... In instance control_module\n    score = 7\'d0;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:104: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                         : ... In instance control_module\n    draw_erase_counter = 5\'b0;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:178: Operator COND expects 20 bits on the Conditional False, but Conditional False\'s VARREF \'restart_game\' generates 1 bits.\n                                                                         : ... In instance control_module\n        next_state = (restart_counter == 20\'d833334) ? INITIALIZE: restart_game;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:178: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s COND generates 20 bits.\n                                                                         : ... In instance control_module\n        next_state = (restart_counter == 20\'d833334) ? INITIALIZE: restart_game;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case expression, but Case expression\'s VARREF \'current_state\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'INIT_HEAD\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'INIT_BODY_1\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'INIT_BODY_2\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'INIT_TAIL\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'INIT_FOOD\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'OBSTACLE1\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'OBSTACLE2\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'TUNNEL_ENTRANCE\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'TUNNEL_EXIT\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'HOLD\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'ERASE_TAIL\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'SHIFT_ARRAY\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'UPDATE_POSITION1\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'UPDATE_POSITION2\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'CHECK\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'DRAW_NEW1\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'DRAW_NEW2\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'DRAW_NEW3\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'DRAW_NEW4\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'UPDATE_HEAD\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'UPDATE_FOOD\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'DELAY\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:114: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'RESTART\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:280: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                         : ... In instance control_module\n        score <= 7\'d0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case expression, but Case expression\'s VARREF \'current_state\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'INIT_HEAD\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'INIT_BODY_1\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'INIT_BODY_2\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'INIT_TAIL\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'INIT_FOOD\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'OBSTACLE1\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'OBSTACLE2\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'TUNNEL_ENTRANCE\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'TUNNEL_EXIT\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'ERASE_TAIL\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'DRAW_NEW1\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'DRAW_NEW2\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'DRAW_NEW3\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'DRAW_NEW4\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'UPDATE_HEAD\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'UPDATE_FOOD\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:287: Operator CASE expects 20 bits on the Case Item, but Case Item\'s VARREF \'RESTART\' generates 5 bits.\n                                                                         : ... In instance control_module\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:503: Operator NEQ expects 20 bits on the LHS, but LHS\'s VARREF \'current_state\' generates 5 bits.\n                                                                         : ... In instance control_module\n     else if (current_state != INITIALIZE && current_state != HOLD && current_state != UPDATE_POSITION1 && \n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:501: Operator EQ expects 20 bits on the LHS, but LHS\'s VARREF \'current_state\' generates 5 bits.\n                                                                         : ... In instance control_module\n     if (current_state == INITIALIZE)\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:516: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance control_module\n     for (index = 1\'b0; index < length; index = index + 1\'b1) \n                ^\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:523: Operator EQ expects 15 bits on the RHS, but RHS\'s REPLICATE generates 13 bits.\n                                                                         : ... In instance control_module\n     if (({random_x,2\'b00, random_y,2\'b00} == {7\'d20,6\'d20}) ||\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:524: Operator EQ expects 15 bits on the RHS, but RHS\'s REPLICATE generates 13 bits.\n                                                                         : ... In instance control_module\n       ({random_x,2\'b00, random_y,2\'b00} == {7\'d100,6\'d100}) ||\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:525: Operator EQ expects 15 bits on the RHS, but RHS\'s REPLICATE generates 13 bits.\n                                                                         : ... In instance control_module\n       ({random_x,2\'b00, random_y,2\'b00} == {7\'d120,6\'d20}) ||\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:526: Operator EQ expects 15 bits on the RHS, but RHS\'s REPLICATE generates 13 bits.\n                                                                         : ... In instance control_module\n       ({random_x,2\'b00, random_y,2\'b00} == {7\'d20,6\'d100}))\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/180624253/control_module.v:533: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                         : ... In instance control_module\n      r_y <= {random_x,2\'b00};\n          ^~\n%Error: Exiting due to 58 warning(s)\n'
module random_x_counter(CLOCK_50, resetn, random_x);
	input CLOCK_50;
	input resetn;
	output [5:0] random_x;
	reg [5:0] count;
	initial begin
		count = 6'd0;
		end
	always@(posedge CLOCK_50)
		begin
		if (!resetn)
			count <= 6'd0;
		else 
			begin
				if (count == 6'd39)
					count <= 6'd0;
			else
				count <= count + 1'd1;
			end
		end
	assign random_x = count;
endmodule
module random_x_counter(CLOCK_50, resetn, random_x);

	input CLOCK_50;
	input resetn;
	output [5:0] random_x;
	reg [5:0] count;
	initial begin
		count = 6'd0;
		end
	always@(posedge CLOCK_50)
		begin
		if (!resetn)
			count <= 6'd0;
		else 
			begin
				if (count == 6'd39)
					count <= 6'd0;
			else
				count <= count + 1'd1;
			end
		end
	assign random_x = count;
endmodule