data/full_repos/permissive/146399661/src/memory/test_mem2.v
None: at end of input
1: b'%Error: data/full_repos/permissive/146399661/src/memory/test_mem2.v:2: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146399661/src/memory,data/full_repos/permissive/146399661/constants.vh\n             data/full_repos/permissive/146399661/src/memory,data/full_repos/permissive/146399661/constants.vh.v\n             data/full_repos/permissive/146399661/src/memory,data/full_repos/permissive/146399661/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/memory/test_mem2.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10; \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/memory/test_mem2.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/memory/test_mem2.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/memory/test_mem2.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/memory/test_mem2.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/memory/test_mem2.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/memory/test_mem2.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/memory/test_mem2.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/memory/test_mem2.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/memory/test_mem2.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n'
module main;
`include "constants.vh"

reg clk,en,op,reset;
reg [WORDSIZE-1:0]addr;
reg [MEMORY_ADDR_WIDTH-1:0] datain;
wire [MEMORY_ADDR_WIDTH-1:0] dataout;
wire [1:0]status;

memory mem(clk,en,reset,op,addr,datain,dataout,status,ready);

initial begin

    $display("test >> Resetting the chip");
    reset = 1'b1;
    #10; 
    reset = 1'b0;

    $display("test >> Setting input to chip & enabling it");
    op = 1'b1;
    addr = 8'b00001000;
    datain = 8'b11110000;
    en = 1'b1;

    $display("test >> Waiting for the chip to signal ready...");
    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> Ready signaled !");
    en = 1'b0;

    $display("test >> Ready is %d",ready);

    $display("test >> Status of write operation was : %d",status);

    reset = 1'b1;
    while (ready) begin
        #1;
    end
    reset = 1'b0;

    op = 1'b0;
    addr = 8'b00001000;
    en = 1'b1;

    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> Data read from memory was : %d",dataout);
    $display("test >> Status of read operation was : %d",status);

    en = 1'b0;

    reset = 1'b1;
    while (ready) begin
        #1;
    end
    reset = 1'b0;

    op = 1;
    addr = 8'b00001001;
    datain = 8'b11110001;
    en = 1;

    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> Status of write operation was : %d",status);
    en = 0;

    reset = 1'b1;
    while (ready) begin
        #1;
    end
    reset = 1'b0;

    op = 0;
    en = 1;

    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> Data read from memory was : %d",dataout);
    $display("test >> Status of read operation was : %d",status);

end

always begin
    clk = 1'b0;
    #5;
    clk = 1'b1;
    #5;
end

endmodule
module main;

`include "constants.vh"

reg clk,en,op,reset;
reg [WORDSIZE-1:0]addr;
reg [MEMORY_ADDR_WIDTH-1:0] datain;
wire [MEMORY_ADDR_WIDTH-1:0] dataout;
wire [1:0]status;

memory mem(clk,en,reset,op,addr,datain,dataout,status,ready);

initial begin

    $display("test >> Resetting the chip");
    reset = 1'b1;
    #10; 
    reset = 1'b0;

    $display("test >> Setting input to chip & enabling it");
    op = 1'b1;
    addr = 8'b00001000;
    datain = 8'b11110000;
    en = 1'b1;

    $display("test >> Waiting for the chip to signal ready...");
    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> Ready signaled !");
    en = 1'b0;

    $display("test >> Ready is %d",ready);

    $display("test >> Status of write operation was : %d",status);

    reset = 1'b1;
    while (ready) begin
        #1;
    end
    reset = 1'b0;

    op = 1'b0;
    addr = 8'b00001000;
    en = 1'b1;

    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> Data read from memory was : %d",dataout);
    $display("test >> Status of read operation was : %d",status);

    en = 1'b0;

    reset = 1'b1;
    while (ready) begin
        #1;
    end
    reset = 1'b0;

    op = 1;
    addr = 8'b00001001;
    datain = 8'b11110001;
    en = 1;

    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> Status of write operation was : %d",status);
    en = 0;

    reset = 1'b1;
    while (ready) begin
        #1;
    end
    reset = 1'b0;

    op = 0;
    en = 1;

    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> Data read from memory was : %d",dataout);
    $display("test >> Status of read operation was : %d",status);

end

always begin
    clk = 1'b0;
    #5;
    clk = 1'b1;
    #5;
end

endmodule