data/full_repos/permissive/181665138/verilog/capitolo_v/FlipFlop_JK.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/FlipFlop_JK.v:27: syntax error, unexpected ==, expecting \')\' or \',\' or or\n    always @(reset_ == 0) #1 STAR <= S0;\n                    ^~\n%Warning-STMTDLY: data/full_repos/permissive/181665138/verilog/capitolo_v/FlipFlop_JK.v:29: Unsupported: Ignoring delay on this delayed statement.\n    always @(posedge clock) if (reset_ == 1) #3\n                                             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module FlipFlop_JK(q, j, k, clock, reset_);
    input clock, reset_;
    input j, k;
    output q;

    reg STAR;
    parameter S0 = 'B0, S1 = 'B1;

    assign q = (STAR == S0)?0:1;

    always @(reset_ == 0) #1 STAR <= S0;

    always @(posedge clock) if (reset_ == 1) #3
        casex(STAR)
            S0: STAR <= (j == 0)? S0:S1;
            S1: STAR <= (k == 0)? S1:S0;
        endcase
endmodule
module FlipFlop_JK(q, j, k, clock, reset_);

    input clock, reset_;
    input j, k;
    output q;

    reg STAR;
    parameter S0 = 'B0, S1 = 'B1;

    assign q = (STAR == S0)?0:1;

    always @(reset_ == 0) #1 STAR <= S0;

    always @(posedge clock) if (reset_ == 1) #3
        casex(STAR)
            S0: STAR <= (j == 0)? S0:S1;
            S1: STAR <= (k == 0)? S1:S0;
        endcase
endmodule