data/full_repos/permissive/11455462/90522229_5_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_5_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_5_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/11455462/90522229_5_tb.v:9: Cannot find file containing module: \'elv_sim\'\nelv_sim test(u1,u2,pos1,pos2,source,st);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/elv_sim\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/elv_sim.v\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/elv_sim.sv\n             elv_sim\n             elv_sim.v\n             elv_sim.sv\n             obj_dir/elv_sim\n             obj_dir/elv_sim.v\n             obj_dir/elv_sim.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module elv_test();

reg [1:0]source;
reg st;
reg [1:0]pos1;
reg [1:0]pos2;
wire u1,u2;

elv_sim test(u1,u2,pos1,pos2,source,st);

	initial
	begin
		pos1 = 2'b11;
		pos2 = 2'b00;

		
	#40
		st =1;
		source = 2'b10;

		
	#10
		st = 1;
		source = 2'b01;
		
	
	end


endmodule
module elv_test();


reg [1:0]source;
reg st;
reg [1:0]pos1;
reg [1:0]pos2;
wire u1,u2;

elv_sim test(u1,u2,pos1,pos2,source,st);

	initial
	begin
		pos1 = 2'b11;
		pos2 = 2'b00;

		
	#40
		st =1;
		source = 2'b10;

		
	#10
		st = 1;
		source = 2'b01;
		
	
	end


endmodule