data/full_repos/permissive/19572582/Lab3/lab3_part3.v
data/verilator_xmls/119c4759-008c-4b78-aee7-ea6db3e9d0ad.xml
module MSDF(Clk, D, Q);
	
	input Clk, D;
	output Q;

	wire Qm;

	Dflop D0 (~Clk, D, Qm);
	Dflop D1 (Clk, Qm, Q);

endmodule
module MSDF(Clk, D, Q);

	
	input Clk, D;
	output Q;

	wire Qm;

	Dflop D0 (~Clk, D, Qm);
	Dflop D1 (Clk, Qm, Q);

endmodule