data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v
 line:29: before: ","
1: b'%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:96: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'WOFS\' generates 4 bits.\n                                                                             : ... In instance NINJAKUN_SP.eng\nassign     WPAD = {1\'b0,XPOS}-{XPOSH,8\'h0}+WOFS-1\'d1;\n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:96: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 9 bits.\n                                                                             : ... In instance NINJAKUN_SP.eng\nassign     WPAD = {1\'b0,XPOS}-{XPOSH,8\'h0}+WOFS-1\'d1;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:142: Operator ADD expects 9 bits on the RHS, but RHS\'s CONST \'5\'h11\' generates 5 bits.\n                                                                              : ... In instance NINJAKUN_SP.eng\n    NV <= PV+5\'d17;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:142: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                              : ... In instance NINJAKUN_SP.eng\n    NV <= PV+5\'d17;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:176: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s VARREF \'SPADT\' generates 8 bits.\n                                                                              : ... In instance NINJAKUN_SP.eng\n   PTNO  <= RAIDERS5 ? { PTNO[8:6], SPADT[7:2] } : SPADT;\n                     ^\n%Error: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:32: Cannot find file containing module: \'dpram\'\ndpram #(8,10) ldbuf(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/217518118/rtl,data/full_repos/permissive/217518118/dpram\n             data/full_repos/permissive/217518118/rtl,data/full_repos/permissive/217518118/dpram.v\n             data/full_repos/permissive/217518118/rtl,data/full_repos/permissive/217518118/dpram.sv\n             dpram\n             dpram.v\n             dpram.sv\n             obj_dir/dpram\n             obj_dir/dpram.v\n             obj_dir/dpram.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module NINJAKUN_SP
(
	input         VCLKx4,
	input         VCLK,
	input         RESET,
	input         RAIDERS5,

	input   [8:0] PH,
	input   [8:0] PV,

	output [10:0] SPAAD,
	input   [7:0] SPADT,

	output [13:0] SPCAD,
	input  [31:0] SPCDT,
	input         SPCFT,

	output  [8:0] SPOUT
);
wire       WPEN;
wire [7:0] WPAD;
wire [7:0] WPIX;

reg  [7:0] POUT;
wire [3:0] OTHP = (POUT[3:0]==1) ? POUT[7:4] : POUT[3:0];

reg  [9:0] radr0=0,radr1=1;
wire [7:0] POUTi;

dpram #(8,10) ldbuf(
	VCLKx4, WPEN, {PV[0], 1'b0, WPAD}, WPIX, 8'd0,
	VCLKx4, (radr0==radr1), radr0, 8'd0, POUTi);

always @(posedge VCLKx4) begin 
	radr0 <= {~PV[0],PH};
	if (VCLK) begin
		if (radr0!=radr1) POUT <= POUTi;
		radr1 <= radr0;
	end
end

NINJAKUN_SPENG eng (
	VCLKx4, RESET, RAIDERS5, PH, PV,
	SPAAD, SPADT,
	SPCAD, SPCDT, SPCFT,
	 WPAD,  WPIX, WPEN
);

assign SPOUT = { 5'h0, OTHP };

endmodule
module NINJAKUN_SP
(
	input         VCLKx4,
	input         VCLK,
	input         RESET,
	input         RAIDERS5,

	input   [8:0] PH,
	input   [8:0] PV,

	output [10:0] SPAAD,
	input   [7:0] SPADT,

	output [13:0] SPCAD,
	input  [31:0] SPCDT,
	input         SPCFT,

	output  [8:0] SPOUT
);

wire       WPEN;
wire [7:0] WPAD;
wire [7:0] WPIX;

reg  [7:0] POUT;
wire [3:0] OTHP = (POUT[3:0]==1) ? POUT[7:4] : POUT[3:0];

reg  [9:0] radr0=0,radr1=1;
wire [7:0] POUTi;

dpram #(8,10) ldbuf(
	VCLKx4, WPEN, {PV[0], 1'b0, WPAD}, WPIX, 8'd0,
	VCLKx4, (radr0==radr1), radr0, 8'd0, POUTi);

always @(posedge VCLKx4) begin 
	radr0 <= {~PV[0],PH};
	if (VCLK) begin
		if (radr0!=radr1) POUT <= POUTi;
		radr1 <= radr0;
	end
end

NINJAKUN_SPENG eng (
	VCLKx4, RESET, RAIDERS5, PH, PV,
	SPAAD, SPADT,
	SPCAD, SPCDT, SPCFT,
	 WPAD,  WPIX, WPEN
);

assign SPOUT = { 5'h0, OTHP };

endmodule