data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/camellia_wrapper.v
 line:88: before: "["
1: b'%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/camellia_wrapper.v:93: Cannot find file containing module: \'buslayer_slave\'\nbuslayer_slave slave_interface (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/buslayer_slave\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/buslayer_slave.v\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/buslayer_slave.sv\n             buslayer_slave\n             buslayer_slave.v\n             buslayer_slave.sv\n             obj_dir/buslayer_slave\n             obj_dir/buslayer_slave.v\n             obj_dir/buslayer_slave.sv\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/camellia_wrapper.v:136: Cannot find file containing module: \'camellia\'\ncamellia camallia_u (\n^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/camellia_wrapper.v:165: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 30 bits.\n                                                                                                              : ... In instance camellia_wrapper\n    wordOut_sel = {{28\'b0}, {wordIn_sel[1:0]}};\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/camellia_wrapper.v:181: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                                              : ... In instance camellia_wrapper\n            data2cam[i] <= 8\'b0;\n                        ^~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module camellia_wrapper(

    input  logic        wb_clk,
    input  logic        wb_rst,
    input  logic        wb_cyc,
    input  logic        wb_stb,
    input  logic        wb_we,
    input  logic  [3:0] wb_sel,
    input  logic [31:0] wb_dat_i,
    input  logic [31:0] wb_adr,
    output logic        wb_ack,
    output logic        wb_err,
    output logic        wb_stall,
    output logic [31:0] wb_dat_o

);


logic request, write, reset, err, done;

logic [31:0] address;

logic  [3:0] byte_sel;

logic [3:0][7:0] data_from_bus;

logic [31:0] data_to_bus;


buslayer_slave slave_interface (

    .wb_clk(wb_clk),
    .wb_rst(wb_rst),
    .wb_cyc(wb_cyc),
    .wb_stb(wb_stb),
    .wb_we(wb_we),
    .wb_sel(wb_sel),
    .wb_dat_i(wb_dat_i),
    .wb_adr(wb_adr),
    .wb_ack(wb_ack),
    .wb_err(wb_err),
    .wb_stall(wb_stall),
    .wb_dat_o(wb_dat_o),

    

    .request(request),
    .write(write),
    .reset(reset),
    .address(address),
    .data_from_bus(data_from_bus),
    .byte_sel(byte_sel),
    .data_to_bus(data_to_bus),
    .done(done),
    .err(err)

);


logic bsy;

logic [31:0] mudule_addres;

logic [31:0] wordIn_sel;

logic [1:0] wordOut_sel;

logic [3:0][7:0] data2cam [8:0];

logic [3:0][7:0] data4cam [3:0];


camellia camallia_u (
    .CLK    (wb_clk),
    .RSTn   (!reset),

    .EN     (data2cam[8][0][0]), 
    .EncDec (data2cam[8][1][0]),
    .Drdy   (data2cam[8][2][0]), 
    .Krdy   (data2cam[8][3][0]),

    .Din    ({{data2cam[7]}, {data2cam[6]}, 
             {data2cam[5]}, {data2cam[4]}}),              

    .Kin    ({{data2cam[3]}, {data2cam[2]}, 
             {data2cam[1]},  {data2cam[0]}}),     

    .Dout   ({{data4cam[0]}, {data4cam[3]}, 
              {data4cam[2]},  {data4cam[1]}}),

    .BSY    (bsy), 
    .Kvld   (), 
    .Dvld   ()
);


always_comb begin
    mudule_addres = (address - `CAMELLIA_BASE);

    wordIn_sel = {{28'b0}, {mudule_addres[5:2]}};

    wordOut_sel = {{28'b0}, {wordIn_sel[1:0]}};

    done = request;




    err = request && 
          ( mudule_addres[1:0] != 2'b0 || 
            mudule_addres > 32'h34     || (write && mudule_addres >= 32'h24));
end


always_ff @(posedge wb_clk or posedge reset) begin
    if (reset) begin
        for (integer i = 0; i < 9; i++) 
            data2cam[i] <= 8'b0;
    end
    else begin
        if ((request && write && !err) == 1'b1) begin                                        
            for (integer k = 0;k < 4; k++) begin
                if (byte_sel[k]) 
                    data2cam[wordIn_sel][k] <= (wordIn_sel == 8)? data_from_bus[0]
                                                                : data_from_bus[k];
            end
        end
       


        if (bsy) begin
            data2cam[8][1] <= 8'b0;
            data2cam[8][2] <= 8'b0;
            data2cam[8][3] <= 8'b0;
        end
   end
end


always_comb begin
    if ((request && !write && !err) == 1'b1) begin
       data_to_bus[7:0] = (!byte_sel[0])? 8'b0
                        : (wordIn_sel < 9)?   data2cam[wordIn_sel][0] 
                        : (wordIn_sel < 13)? data4cam[wordOut_sel][0] 
                        : {{7'b0}, {bsy}};
                        
       data_to_bus[15:8] = (!byte_sel[1])? 8'b0
                        : (wordIn_sel < 9)? data2cam[wordIn_sel][1] 
                        : data4cam[wordOut_sel][1]; 
                         
       data_to_bus[23:16] = (!byte_sel[2])? 8'b0
                        : (wordIn_sel < 9)? data2cam[wordIn_sel][2] 
                        : data4cam[wordOut_sel][2];   
                                    
      data_to_bus[31:24] = (!byte_sel[3])? 8'b0
                        : (wordIn_sel < 9)? data2cam[wordIn_sel][3] 
                        : data4cam[wordOut_sel][3]; 
    end   
    else begin
        data_to_bus = 32'hffffffff;
    end
end

endmodule
module camellia_wrapper(

    input  logic        wb_clk,
    input  logic        wb_rst,
    input  logic        wb_cyc,
    input  logic        wb_stb,
    input  logic        wb_we,
    input  logic  [3:0] wb_sel,
    input  logic [31:0] wb_dat_i,
    input  logic [31:0] wb_adr,
    output logic        wb_ack,
    output logic        wb_err,
    output logic        wb_stall,
    output logic [31:0] wb_dat_o

);



logic request, write, reset, err, done;

logic [31:0] address;

logic  [3:0] byte_sel;

logic [3:0][7:0] data_from_bus;

logic [31:0] data_to_bus;


buslayer_slave slave_interface (

    .wb_clk(wb_clk),
    .wb_rst(wb_rst),
    .wb_cyc(wb_cyc),
    .wb_stb(wb_stb),
    .wb_we(wb_we),
    .wb_sel(wb_sel),
    .wb_dat_i(wb_dat_i),
    .wb_adr(wb_adr),
    .wb_ack(wb_ack),
    .wb_err(wb_err),
    .wb_stall(wb_stall),
    .wb_dat_o(wb_dat_o),

    

    .request(request),
    .write(write),
    .reset(reset),
    .address(address),
    .data_from_bus(data_from_bus),
    .byte_sel(byte_sel),
    .data_to_bus(data_to_bus),
    .done(done),
    .err(err)

);


logic bsy;

logic [31:0] mudule_addres;

logic [31:0] wordIn_sel;

logic [1:0] wordOut_sel;

logic [3:0][7:0] data2cam [8:0];

logic [3:0][7:0] data4cam [3:0];


camellia camallia_u (
    .CLK    (wb_clk),
    .RSTn   (!reset),

    .EN     (data2cam[8][0][0]), 
    .EncDec (data2cam[8][1][0]),
    .Drdy   (data2cam[8][2][0]), 
    .Krdy   (data2cam[8][3][0]),

    .Din    ({{data2cam[7]}, {data2cam[6]}, 
             {data2cam[5]}, {data2cam[4]}}),              

    .Kin    ({{data2cam[3]}, {data2cam[2]}, 
             {data2cam[1]},  {data2cam[0]}}),     

    .Dout   ({{data4cam[0]}, {data4cam[3]}, 
              {data4cam[2]},  {data4cam[1]}}),

    .BSY    (bsy), 
    .Kvld   (), 
    .Dvld   ()
);


always_comb begin
    mudule_addres = (address - `CAMELLIA_BASE);

    wordIn_sel = {{28'b0}, {mudule_addres[5:2]}};

    wordOut_sel = {{28'b0}, {wordIn_sel[1:0]}};

    done = request;




    err = request && 
          ( mudule_addres[1:0] != 2'b0 || 
            mudule_addres > 32'h34     || (write && mudule_addres >= 32'h24));
end


always_ff @(posedge wb_clk or posedge reset) begin
    if (reset) begin
        for (integer i = 0; i < 9; i++) 
            data2cam[i] <= 8'b0;
    end
    else begin
        if ((request && write && !err) == 1'b1) begin                                        
            for (integer k = 0;k < 4; k++) begin
                if (byte_sel[k]) 
                    data2cam[wordIn_sel][k] <= (wordIn_sel == 8)? data_from_bus[0]
                                                                : data_from_bus[k];
            end
        end
       


        if (bsy) begin
            data2cam[8][1] <= 8'b0;
            data2cam[8][2] <= 8'b0;
            data2cam[8][3] <= 8'b0;
        end
   end
end


always_comb begin
    if ((request && !write && !err) == 1'b1) begin
       data_to_bus[7:0] = (!byte_sel[0])? 8'b0
                        : (wordIn_sel < 9)?   data2cam[wordIn_sel][0] 
                        : (wordIn_sel < 13)? data4cam[wordOut_sel][0] 
                        : {{7'b0}, {bsy}};
                        
       data_to_bus[15:8] = (!byte_sel[1])? 8'b0
                        : (wordIn_sel < 9)? data2cam[wordIn_sel][1] 
                        : data4cam[wordOut_sel][1]; 
                         
       data_to_bus[23:16] = (!byte_sel[2])? 8'b0
                        : (wordIn_sel < 9)? data2cam[wordIn_sel][2] 
                        : data4cam[wordOut_sel][2];   
                                    
      data_to_bus[31:24] = (!byte_sel[3])? 8'b0
                        : (wordIn_sel < 9)? data2cam[wordIn_sel][3] 
                        : data4cam[wordOut_sel][3]; 
    end   
    else begin
        data_to_bus = 32'hffffffff;
    end
end

endmodule