data/full_repos/permissive/169930446/alu/alu.srcs/sources_1/new/ctrl.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169930446/alu/alu.srcs/sources_1/new/ctrl.v:72: Operator AND expects 7 bits on the LHS, but LHS\'s VARREF \'A\' generates 6 bits.\n                                                                                         : ... In instance ctrl\n                led = (A & B);\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169930446/alu/alu.srcs/sources_1/new/ctrl.v:72: Operator AND expects 7 bits on the RHS, but RHS\'s VARREF \'B\' generates 6 bits.\n                                                                                         : ... In instance ctrl\n                led = (A & B);\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/169930446/alu/alu.srcs/sources_1/new/ctrl.v:75: Operator OR expects 7 bits on the LHS, but LHS\'s VARREF \'A\' generates 6 bits.\n                                                                                         : ... In instance ctrl\n                led = (A | B);                \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/169930446/alu/alu.srcs/sources_1/new/ctrl.v:75: Operator OR expects 7 bits on the RHS, but RHS\'s VARREF \'B\' generates 6 bits.\n                                                                                         : ... In instance ctrl\n                led = (A | B);                \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/169930446/alu/alu.srcs/sources_1/new/ctrl.v:78: Operator XOR expects 7 bits on the LHS, but LHS\'s VARREF \'A\' generates 6 bits.\n                                                                                         : ... In instance ctrl\n                led = (A ^ B);\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/169930446/alu/alu.srcs/sources_1/new/ctrl.v:78: Operator XOR expects 7 bits on the RHS, but RHS\'s VARREF \'B\' generates 6 bits.\n                                                                                         : ... In instance ctrl\n                led = (A ^ B);\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/169930446/alu/alu.srcs/sources_1/new/ctrl.v:88: Operator SHIFTL expects 7 bits on the LHS, but LHS\'s VARREF \'A\' generates 6 bits.\n                                                                                         : ... In instance ctrl\n                led = A << B;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/169930446/alu/alu.srcs/sources_1/new/ctrl.v:91: Operator SHIFTL expects 7 bits on the LHS, but LHS\'s VARREF \'B\' generates 6 bits.\n                                                                                         : ... In instance ctrl\n                led = B << A;\n                        ^~\n%Error: Exiting due to 8 warning(s)\n'
module ctrl(
    input clk,
    input [5:0] A,
    input [5:0] B,
    input [3:0] C,
    output reg [6:0] led
    ); 

   
    always @(posedge clk)
    begin
        case(C)
            4'b0000:

                led <= A + B;
            4'b0001:

                led <= A - B;
            4'b0010:

                led <= A + 1'b1;
            4'b0011:

                led <= A - 1'b1;
            4'b0100:

                led <= B + 1'b1;
            4'b0101:

                led <= B - 1'b1;
            4'b0110:

                led = (A & B);
            4'b0111:

                led = (A | B);                
            4'b1000:

                led = (A ^ B);
            4'b1001:

                led = {1'b0,~A[5:0]};

            4'b1010:

                led = {1'b0,~B[5:0]};
            4'b1011:

                led = A << B;
            4'b1100:

                led = B << A;
                
            4'b1101:

                if(A > B)
                    led = 7'b0000001;
                else
                    led = 7'b0000000;
            4'b1110:

                if(A < B)
                    led = 7'b00000001;
                else
                    led = 7'b0000000;
                    
            4'b1111:

                if(A == B)
                    led = 7'b0000001;
                else
                    led = 7'b0000000;          
            default: 

                led <= 7'b1111111;
        endcase
    end
    

endmodule
module ctrl(
    input clk,
    input [5:0] A,
    input [5:0] B,
    input [3:0] C,
    output reg [6:0] led
    );
 

   
    always @(posedge clk)
    begin
        case(C)
            4'b0000:

                led <= A + B;
            4'b0001:

                led <= A - B;
            4'b0010:

                led <= A + 1'b1;
            4'b0011:

                led <= A - 1'b1;
            4'b0100:

                led <= B + 1'b1;
            4'b0101:

                led <= B - 1'b1;
            4'b0110:

                led = (A & B);
            4'b0111:

                led = (A | B);                
            4'b1000:

                led = (A ^ B);
            4'b1001:

                led = {1'b0,~A[5:0]};

            4'b1010:

                led = {1'b0,~B[5:0]};
            4'b1011:

                led = A << B;
            4'b1100:

                led = B << A;
                
            4'b1101:

                if(A > B)
                    led = 7'b0000001;
                else
                    led = 7'b0000000;
            4'b1110:

                if(A < B)
                    led = 7'b00000001;
                else
                    led = 7'b0000000;
                    
            4'b1111:

                if(A == B)
                    led = 7'b0000001;
                else
                    led = 7'b0000000;          
            default: 

                led <= 7'b1111111;
        endcase
    end
    

endmodule