data/full_repos/permissive/147086086/Lab6/hw/barrel_shifter_rtl/barrel_shifter_right_tb.v
 line:22: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/147086086/Lab6/hw/barrel_shifter_rtl/barrel_shifter_right_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #DELAY;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147086086/Lab6/hw/barrel_shifter_rtl/barrel_shifter_right_tb.v:15: Cannot find file containing module: \'barrel_shifter_right\'\nbarrel_shifter_right #(.DATA_WIDTH (DATA_WIDTH)) bsr_inst(.i_data (i_data), \n^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147086086/Lab6/hw/barrel_shifter_rtl,data/full_repos/permissive/147086086/barrel_shifter_right\n             data/full_repos/permissive/147086086/Lab6/hw/barrel_shifter_rtl,data/full_repos/permissive/147086086/barrel_shifter_right.v\n             data/full_repos/permissive/147086086/Lab6/hw/barrel_shifter_rtl,data/full_repos/permissive/147086086/barrel_shifter_right.sv\n             barrel_shifter_right\n             barrel_shifter_right.v\n             barrel_shifter_right.sv\n             obj_dir/barrel_shifter_right\n             obj_dir/barrel_shifter_right.v\n             obj_dir/barrel_shifter_right.sv\n%Warning-WIDTH: data/full_repos/permissive/147086086/Lab6/hw/barrel_shifter_rtl/barrel_shifter_right_tb.v:23: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                            : ... In instance testbench\n        i_st    = $random;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/147086086/Lab6/hw/barrel_shifter_rtl/barrel_shifter_right_tb.v:24: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                            : ... In instance testbench\n        i_sa    = $random;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/147086086/Lab6/hw/barrel_shifter_rtl/barrel_shifter_right_tb.v:25: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                            : ... In instance testbench\n        i_data  = $random;\n                ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

parameter DATA_WIDTH = 16;
parameter SA_WIDTH = $clog2(DATA_WIDTH);
parameter DELAY = 20;
parameter N = 10_000;

reg                     i_st;
reg   [DATA_WIDTH-1:0]  i_data;
reg   [SA_WIDTH-1:0]    i_sa;
wire  [DATA_WIDTH-1:0]  o_data;

barrel_shifter_right #(.DATA_WIDTH (DATA_WIDTH)) bsr_inst(.i_data (i_data), 
                                                           .i_sa (i_sa), 
                                                           .i_st (i_st), 
                                                           .o_data (o_data)
                                                           );
initial begin

    repeat (N) begin
        i_st    = $random;
        i_sa    = $random;
        i_data  = $random;
        #DELAY;
    end

    $finish;

end

endmodule
module testbench;


parameter DATA_WIDTH = 16;
parameter SA_WIDTH = $clog2(DATA_WIDTH);
parameter DELAY = 20;
parameter N = 10_000;

reg                     i_st;
reg   [DATA_WIDTH-1:0]  i_data;
reg   [SA_WIDTH-1:0]    i_sa;
wire  [DATA_WIDTH-1:0]  o_data;

barrel_shifter_right #(.DATA_WIDTH (DATA_WIDTH)) bsr_inst(.i_data (i_data), 
                                                           .i_sa (i_sa), 
                                                           .i_st (i_st), 
                                                           .o_data (o_data)
                                                           );
initial begin

    repeat (N) begin
        i_st    = $random;
        i_sa    = $random;
        i_data  = $random;
        #DELAY;
    end

    $finish;

end

endmodule