data/full_repos/permissive/134925232/src/dmx.v
 line:39: before: "assign"
data/verilator_xmls/cecbd553-342c-4d04-9d73-57a0a75afe00.xml
module dmx(
    input wire dmxclk,
    output wire signal
);

    




    

    













    reg [19:0] counter = 0;
    reg signal_out = 0;
    assign signal = signal_out;

    always @(posedge dmxclk) begin
        if (counter == 82500) begin 
            counter = 0;
        end else begin
            counter = counter + 1;
        end

        if (counter < 78393) begin
            assign signal_out = 1;
        end else if (counter >= 78393 && counter < 78395) begin
            assign signal_out = 0;
        end else if (counter >= 78395 && counter < 78396) begin
            assign signal_out = 1;
        end else if (counter >= 78396 && counter < 78404) begin
            assign signal_out = 0;
        end else if (counter >= 78404 && counter < 82500) begin
            assign signal_out = ~signal_out;
        end else begin
            assign signal_out = 0;
        end
    end
endmodule
module dmx(
    input wire dmxclk,
    output wire signal
);


    




    

    













    reg [19:0] counter = 0;
    reg signal_out = 0;
    assign signal = signal_out;

    always @(posedge dmxclk) begin
        if (counter == 82500) begin 
            counter = 0;
        end else begin
            counter = counter + 1;
        end

        if (counter < 78393) begin
            assign signal_out = 1;
        end else if (counter >= 78393 && counter < 78395) begin
            assign signal_out = 0;
        end else if (counter >= 78395 && counter < 78396) begin
            assign signal_out = 1;
        end else if (counter >= 78396 && counter < 78404) begin
            assign signal_out = 0;
        end else if (counter >= 78404 && counter < 82500) begin
            assign signal_out = ~signal_out;
        end else begin
            assign signal_out = 0;
        end
    end
endmodule