data/full_repos/permissive/173943530/jt_gng/modules/jtgng_cen.v
 line:49: before: "/"
data/verilator_xmls/b5e8b66a-7fb9-456d-8a30-1adfe489a0ba.xml
module jtgng_cen(
    input   clk,
    output  reg cen12,
    output  reg cen6,
    output  reg cen3,
    output  reg cen1p5
);

parameter CLK_SPEED = 12;
reg [3:0] cencnt=4'd0;

always @(posedge clk)
    cencnt <= cencnt+4'd1;

always @(negedge clk) begin

    if( CLK_SPEED==24 ) begin
        cen12  <= cencnt[0]   == 1'd0;
        cen6   <= cencnt[1:0] == 2'd0;
        cen3   <= cencnt[2:0] == 3'd0;
        cen1p5 <= cencnt[3:0] == 4'd0;
    end
    else if( CLK_SPEED==12 ) begin
        cen12  <= 1'b1;
        cen6   <= cencnt[0]   == 1'd0;
        cen3   <= cencnt[1:0] == 2'd0;
        cen1p5 <= cencnt[2:0] == 3'd0;
    end
end

endmodule
module jtgng_cen(
    input   clk,
    output  reg cen12,
    output  reg cen6,
    output  reg cen3,
    output  reg cen1p5
);


parameter CLK_SPEED = 12;
reg [3:0] cencnt=4'd0;

always @(posedge clk)
    cencnt <= cencnt+4'd1;

always @(negedge clk) begin

    if( CLK_SPEED==24 ) begin
        cen12  <= cencnt[0]   == 1'd0;
        cen6   <= cencnt[1:0] == 2'd0;
        cen3   <= cencnt[2:0] == 3'd0;
        cen1p5 <= cencnt[3:0] == 4'd0;
    end
    else if( CLK_SPEED==12 ) begin
        cen12  <= 1'b1;
        cen6   <= cencnt[0]   == 1'd0;
        cen3   <= cencnt[1:0] == 2'd0;
        cen1p5 <= cencnt[2:0] == 3'd0;
    end
end

endmodule