data/full_repos/permissive/129127690/ALU.v
1: b"%Error: data/full_repos/permissive/129127690/ALU.v:35: Cannot find file containing module: 'parameterizable_nand'\n parameterizable_nand #(bus) and_c2(b,c2_in,b_c2);\n ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/parameterizable_nand\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/parameterizable_nand.v\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/parameterizable_nand.sv\n             parameterizable_nand\n             parameterizable_nand.v\n             parameterizable_nand.sv\n             obj_dir/parameterizable_nand\n             obj_dir/parameterizable_nand.v\n             obj_dir/parameterizable_nand.sv\n%Error: data/full_repos/permissive/129127690/ALU.v:40: Cannot find file containing module: 'parameterizable_and'\n parameterizable_and #(bus) and_dut(a,b,andout);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129127690/ALU.v:45: Cannot find file containing module: 'sumador_parametrizable'\n sumador_parametrizable #(bus) sumador(a,b_c2,cin, sumout, local_carry);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129127690/ALU.v:49: Cannot find file containing module: 'parameterizable_or'\n parameterizable_or #(bus) or_dut(a,b,orout);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129127690/ALU.v:53: Cannot find file containing module: 'parametrizable_not'\n parametrizable_not #(bus) nor_dut(orout,norout);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129127690/ALU.v:58: Cannot find file containing module: 'parameterizable_shift_left'\n parameterizable_shift_left #(bus) sll_dut(a,b,sllout);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129127690/ALU.v:59: Cannot find file containing module: 'parameterizable_shift_right'\n parameterizable_shift_right #(bus) srl_dut(a,b,srlout);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129127690/ALU.v:63: Cannot find file containing module: 'parametrizable_slt'\n parametrizable_slt #(bus) slt_dut(a,b,sltout);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129127690/ALU.v:75: Cannot find file containing module: 'mux_8_3'\n mux_8_3 #(bus) operation_sel(sllout,srlout,orout,norout,sumout,sumout,andout,sltout,opselect[2:0],sout);\n ^~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module ALU #(parameter bus = 8)
	(a,b,opselect,sout,zero,cout,overflow,negative);

	input [bus-1:0] a;
	input [bus-1:0] b;
	input [3:0] opselect;
	output[bus-1:0] sout;
	output zero;
	output cout;
	output overflow;
	output negative;
	
	wire u_operation;
	assign u_operation = opselect[3];
	

	
	wire [bus-1:0] c2_in,bc2;
	wire c2_function;
	

	assign c2_function = opselect[0] & opselect[2];
	
	
	genvar i;
	generate 
		for (i = 0; i < bus; i = i+1) begin:forloop
			assign c2_in[i] = c2_function;
		end
	
	endgenerate
	
	parameterizable_nand #(bus) and_c2(b,c2_in,b_c2);
	
	

	wire [bus-1:0] andout;
	parameterizable_and #(bus) and_dut(a,b,andout);
	

	wire [bus-1:0] sumout;	
	wire local_carry;
	sumador_parametrizable #(bus) sumador(a,b_c2,cin, sumout, local_carry);
	

	wire [bus-1:0] orout;
	parameterizable_or #(bus) or_dut(a,b,orout);
	

	wire [bus-1:0] norout;
	parametrizable_not #(bus) nor_dut(orout,norout);



	wire [bus-1:0] sllout,srlout;
	parameterizable_shift_left #(bus) sll_dut(a,b,sllout);
	parameterizable_shift_right #(bus) srl_dut(a,b,srlout);
	
	wire [bus-1:0] sltout;
	
	parametrizable_slt #(bus) slt_dut(a,b,sltout);
	









	
	mux_8_3 #(bus) operation_sel(sllout,srlout,orout,norout,sumout,sumout,andout,sltout,opselect[2:0],sout);
	
	

	
	assign zero = ~| sumout;



	wire sub_add_op;
	assign sub_add_op = opselect[0] & ~opselect[1];
	assign negative = sout[bus-1] & ~u_operation & sub_add_op; 

	assign cout = local_carry & sub_add_op & ~opselect[2]; 





	assign overflow = ~(opselect[2] ^ a[bus-1] ^ b[bus-1]) & (a[bus-1] ^ sumout[bus-1]) & sub_add_op;
	

endmodule
module ALU #(parameter bus = 8)
	(a,b,opselect,sout,zero,cout,overflow,negative);


	input [bus-1:0] a;
	input [bus-1:0] b;
	input [3:0] opselect;
	output[bus-1:0] sout;
	output zero;
	output cout;
	output overflow;
	output negative;
	
	wire u_operation;
	assign u_operation = opselect[3];
	

	
	wire [bus-1:0] c2_in,bc2;
	wire c2_function;
	

	assign c2_function = opselect[0] & opselect[2];
	
	
	genvar i;
	generate 
		for (i = 0; i < bus; i = i+1) begin:forloop
			assign c2_in[i] = c2_function;
		end
	
	endgenerate
	
	parameterizable_nand #(bus) and_c2(b,c2_in,b_c2);
	
	

	wire [bus-1:0] andout;
	parameterizable_and #(bus) and_dut(a,b,andout);
	

	wire [bus-1:0] sumout;	
	wire local_carry;
	sumador_parametrizable #(bus) sumador(a,b_c2,cin, sumout, local_carry);
	

	wire [bus-1:0] orout;
	parameterizable_or #(bus) or_dut(a,b,orout);
	

	wire [bus-1:0] norout;
	parametrizable_not #(bus) nor_dut(orout,norout);



	wire [bus-1:0] sllout,srlout;
	parameterizable_shift_left #(bus) sll_dut(a,b,sllout);
	parameterizable_shift_right #(bus) srl_dut(a,b,srlout);
	
	wire [bus-1:0] sltout;
	
	parametrizable_slt #(bus) slt_dut(a,b,sltout);
	









	
	mux_8_3 #(bus) operation_sel(sllout,srlout,orout,norout,sumout,sumout,andout,sltout,opselect[2:0],sout);
	
	

	
	assign zero = ~| sumout;



	wire sub_add_op;
	assign sub_add_op = opselect[0] & ~opselect[1];
	assign negative = sout[bus-1] & ~u_operation & sub_add_op; 

	assign cout = local_carry & sub_add_op & ~opselect[2]; 





	assign overflow = ~(opselect[2] ^ a[bus-1] ^ b[bus-1]) & (a[bus-1] ^ sumout[bus-1]) & sub_add_op;
	

endmodule