data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Basics.v
1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Basics.v:8: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Basics.v:2: ... Location of original declaration\nmodule top_module( input in, output out );\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Basics.v:16: Duplicate declaration of module: \'top_module\'\nmodule top_module( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Basics.v:2: ... Location of original declaration\nmodule top_module( input in, output out );\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Basics.v:24: Duplicate declaration of module: \'top_module\'\nmodule top_module( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Basics.v:2: ... Location of original declaration\nmodule top_module( input in, output out );\n       ^~~~~~~~~~\n%Error: Exiting due to 3 warning(s)\n'
module top_module( 
    input a, 
    input b, 
    output out );
    assign out = a&b;
endmodule
module top_module( 
    input a, 
    input b, 
    output out );

    assign out = a&b;
endmodule