data/full_repos/permissive/143278/vhdl_tests/pr2555813b.v
data/verilator_xmls/ca9c6fc8-9d15-4c0e-ad43-86d09f6911fc.xml
module test();
  wire x, y;
a__a a_(
.b_buf(y),
.b (x)
);
endmodule
module test();

  wire x, y;
a__a a_(
.b_buf(y),
.b (x)
);
endmodule