data/full_repos/permissive/12014746/hw/fpga/source/memory_if/track_buff.v
data/verilator_xmls/ab1077b8-4c05-4dcc-9b5b-d90047aeeb73.xml
module track_buff(
input i_clk,
input i_data,
input [7:0] i_wr_ptr,
input [7:0] i_rd_ptr,
input i_wr_en,
output o_data
);

reg [0:0] mem[255:0];

always @(posedge i_clk)
begin
  if(i_wr_en)
      mem[i_wr_ptr] <= i_data;
end


assign o_data = mem[i_rd_ptr];

endmodule
module track_buff(
input i_clk,
input i_data,
input [7:0] i_wr_ptr,
input [7:0] i_rd_ptr,
input i_wr_en,
output o_data
);


reg [0:0] mem[255:0];

always @(posedge i_clk)
begin
  if(i_wr_en)
      mem[i_wr_ptr] <= i_data;
end


assign o_data = mem[i_rd_ptr];

endmodule