data/full_repos/permissive/109594910/example_tb.v
 line:11: before: "$"
1: b'%Error: data/full_repos/permissive/109594910/example_tb.v:6: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile("example_tb.vcd");\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/example_tb.v:7: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0,top_tb);\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n     # 10000 sel = 1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n     # 10000 sel = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n     # 900000 $finish;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = !clk;\n         ^\n%Error: data/full_repos/permissive/109594910/example_tb.v:20: syntax error, unexpected \'=\', expecting \')\'\n  top uut (clk, sel, LED[7], LED[6], LED[5], LED[4], LED[3], LED[2], LED[1], LED[0], LOG2DELAY=8);\n                                                                                              ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb;

  reg sel = 0;
  initial begin
     $dumpfile("example_tb.vcd");
     $dumpvars(0,top_tb);

     # 10000 sel = 1;
     # 10000 sel = 0;
     # 900000 $finish;
  end


  reg clk = 0;
  always #1 clk = !clk;


  wire [7:0] LED;
  top uut (clk, sel, LED[7], LED[6], LED[5], LED[4], LED[3], LED[2], LED[1], LED[0], LOG2DELAY=8);

endmodule
module top_tb;


  reg sel = 0;
  initial begin
     $dumpfile("example_tb.vcd");
     $dumpvars(0,top_tb);

     # 10000 sel = 1;
     # 10000 sel = 0;
     # 900000 $finish;
  end


  reg clk = 0;
  always #1 clk = !clk;


  wire [7:0] LED;
  top uut (clk, sel, LED[7], LED[6], LED[5], LED[4], LED[3], LED[2], LED[1], LED[0], LOG2DELAY=8);

endmodule