data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl/sync_dual_port_ram.v
data/verilator_xmls/e5daca97-4c80-478b-a623-bcc2fec19c84.xml
module sync_dual_port_ram
		#( parameter ADDRESS_WIDTH = 4,
                     DATA_WIDTH    =  4
	 )
	

	(
		input wire clk,
		input wire write_en,
		input wire [ADDRESS_WIDTH-1:0] read_address, write_address,
		input wire [DATA_WIDTH-1:0] write_data_in,
		output wire [DATA_WIDTH-1:0] read_data_out, write_data_out
	);
	

	reg [DATA_WIDTH-1:0] ram [2**ADDRESS_WIDTH-1:0];
	reg [ADDRESS_WIDTH-1:0] read_address_reg, write_address_reg;
	

	always @(posedge clk)
		begin
		if (write_en)
		   ram[write_address] <= write_data_in;
		    
                read_address_reg  <= read_address;
	        write_address_reg <= write_address;
	        end
	

	assign read_data_out  = ram[read_address_reg];
	assign write_data_out = ram[write_address_reg];
endmodule
module sync_dual_port_ram
		#( parameter ADDRESS_WIDTH = 4,
                     DATA_WIDTH    =  4
	 )
	

	(
		input wire clk,
		input wire write_en,
		input wire [ADDRESS_WIDTH-1:0] read_address, write_address,
		input wire [DATA_WIDTH-1:0] write_data_in,
		output wire [DATA_WIDTH-1:0] read_data_out, write_data_out
	);

	

	reg [DATA_WIDTH-1:0] ram [2**ADDRESS_WIDTH-1:0];
	reg [ADDRESS_WIDTH-1:0] read_address_reg, write_address_reg;
	

	always @(posedge clk)
		begin
		if (write_en)
		   ram[write_address] <= write_data_in;
		    
                read_address_reg  <= read_address;
	        write_address_reg <= write_address;
	        end
	

	assign read_data_out  = ram[read_address_reg];
	assign write_data_out = ram[write_address_reg];
endmodule