data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:403: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.in_fifo.unhardened_fifo.mem_1r1w.synth\n                                  (N5)? { 1\'b0, 1\'b0, 1\'b0, 1\'b0 } : 1\'b0;\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:144: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.in_fifo.unhardened_fifo.ft.wptr\n                      (N1)? n_o : 1\'b0;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:148: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.in_fifo.unhardened_fifo.ft.wptr\n               (N3)? o : 1\'b0;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:665: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.out_fifo.mem_1r1w.synth\n                      (N2)? { 1\'b0, 1\'b0 } : 1\'b0;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:103: Operator ADD expects 3 bits on the RHS, but RHS\'s VARREF \'up_i\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.dma_counter\n  assign { N8, N7, N6 } = { N14, N13, N12 } + up_i;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:105: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.dma_counter\n                            (N1)? { N8, N7, N6 } : 1\'b0;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:1206: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                                : ... In instance top.wrapper\n                       (N8)? { 1\'b0, 1\'b0 } : 1\'b0;\n                           ^\n%Error: Exiting due to 7 warning(s)\n'
module bsg_fifo_tracker_els_p4
(
  clk_i,
  reset_i,
  enq_i,
  deq_i,
  wptr_r_o,
  rptr_r_o,
  rptr_n_o,
  full_o,
  empty_o
);

  output [1:0] wptr_r_o;
  output [1:0] rptr_r_o;
  output [1:0] rptr_n_o;
  input clk_i;
  input reset_i;
  input enq_i;
  input deq_i;
  output full_o;
  output empty_o;
  wire [1:0] wptr_r_o,rptr_r_o,rptr_n_o;
  wire full_o,empty_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,equal_ptrs,SYNOPSYS_UNCONNECTED_1,
  SYNOPSYS_UNCONNECTED_2;
  reg deq_r,enq_r;

  bsg_circular_ptr_slots_p4_max_add_p1
  rptr
  (
    .clk(clk_i),
    .reset_i(reset_i),
    .add_i(deq_i),
    .o(rptr_r_o),
    .n_o(rptr_n_o)
  );


  bsg_circular_ptr_slots_p4_max_add_p1
  wptr
  (
    .clk(clk_i),
    .reset_i(reset_i),
    .add_i(enq_i),
    .o(wptr_r_o),
    .n_o({ SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2 })
  );

  assign equal_ptrs = rptr_r_o == wptr_r_o;
  assign N5 = (N0)? 1'b1 : 
              (N9)? 1'b1 : 
              (N4)? 1'b0 : 1'b0;
  assign N0 = N2;
  assign N6 = (N0)? 1'b0 : 
              (N9)? enq_i : 1'b0;
  assign N7 = (N0)? 1'b1 : 
              (N9)? deq_i : 1'b0;
  assign N1 = enq_i | deq_i;
  assign N2 = reset_i;
  assign N3 = N1 | N2;
  assign N4 = ~N3;
  assign N8 = ~N2;
  assign N9 = N1 & N8;
  assign empty_o = equal_ptrs & deq_r;
  assign full_o = equal_ptrs & enq_r;

  always @(posedge clk_i) begin
    if(N5) begin
      deq_r <= N7;
      enq_r <= N6;
    end 
  end


endmodule
module bsg_fifo_tracker_els_p4
(
  clk_i,
  reset_i,
  enq_i,
  deq_i,
  wptr_r_o,
  rptr_r_o,
  rptr_n_o,
  full_o,
  empty_o
);


  output [1:0] wptr_r_o;
  output [1:0] rptr_r_o;
  output [1:0] rptr_n_o;
  input clk_i;
  input reset_i;
  input enq_i;
  input deq_i;
  output full_o;
  output empty_o;
  wire [1:0] wptr_r_o,rptr_r_o,rptr_n_o;
  wire full_o,empty_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,equal_ptrs,SYNOPSYS_UNCONNECTED_1,
  SYNOPSYS_UNCONNECTED_2;
  reg deq_r,enq_r;

  bsg_circular_ptr_slots_p4_max_add_p1
  rptr
  (
    .clk(clk_i),
    .reset_i(reset_i),
    .add_i(deq_i),
    .o(rptr_r_o),
    .n_o(rptr_n_o)
  );


  bsg_circular_ptr_slots_p4_max_add_p1
  wptr
  (
    .clk(clk_i),
    .reset_i(reset_i),
    .add_i(enq_i),
    .o(wptr_r_o),
    .n_o({ SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2 })
  );

  assign equal_ptrs = rptr_r_o == wptr_r_o;
  assign N5 = (N0)? 1'b1 : 
              (N9)? 1'b1 : 
              (N4)? 1'b0 : 1'b0;
  assign N0 = N2;
  assign N6 = (N0)? 1'b0 : 
              (N9)? enq_i : 1'b0;
  assign N7 = (N0)? 1'b1 : 
              (N9)? deq_i : 1'b0;
  assign N1 = enq_i | deq_i;
  assign N2 = reset_i;
  assign N3 = N1 | N2;
  assign N4 = ~N3;
  assign N8 = ~N2;
  assign N9 = N1 & N8;
  assign empty_o = equal_ptrs & deq_r;
  assign full_o = equal_ptrs & enq_r;

  always @(posedge clk_i) begin
    if(N5) begin
      deq_r <= N7;
      enq_r <= N6;
    end 
  end


endmodule