data/full_repos/permissive/178917770/design.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/178917770/design.v:237: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'flopenr\'\nmodule flopenr #(parameter WIDTH = 4)\n       ^~~~~~~\n                                                                    : ... Top module \'processor\'\nmodule processor(input clk, reset,\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/178917770/design.v:250: Duplicate declaration of signal: \'MemWrite\'\n                                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire MemToReg, MemWrite, RegWrite, ALUSrc, J, initRd;\n                   ^~~~~~~~\n        data/full_repos/permissive/178917770/design.v:240: ... Location of original declaration\n                 output MemWrite,BeqFlag,\n                        ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module datapath(   input clk,reset,
  				   output BeqFlag,
                   input  [1:0] AdrRd,
                   input  [1:0] AdrRa,
                   input  [1:0] AdrRb,
                   input  [3:0] imm,
                   input [6:0] Adr,
                   input [1:0] ALUControl,
                   input MemToReg, MemWrite, RegWrite, ALUSrc, J,
                   input Beq,
                output [7:0] PC, 
                output [3:0] ALUResult, WriteData,
                input [3:0] ReadData,
               input initRd);
  
  wire BeqFlag_preclk;
  wire [7:0] PCplusImm,Adrx2,PCplus1,PCpre,imm8;
  wire [1:0] BJ;
  wire [3:0] Result,Ra;
  wire [3:0] SrcB;
  wire [3:0] Result_;
  assign BJ={Beq,J};
  

  pcmux Pcmux (.PCplusImm(PCplusImm),.Adrx2(Adrx2),.PCplus1(PCplus1),.BJ(BJ),.PC(PCpre));
  flopr #(8) PCreg (.clk(clk),.reset(reset), .d(PCpre),.q(PC) );
  adder adder1(.a(PC),.b(imm8),.y(PCplusImm));
  adder adder2(.a(PC), .b(8'b1),.y(PCplus1));
  extendImm extendImm(.imm(imm), .imm8(imm8));
  extendJ extendJ(.Adr(Adr), .Adrx2(Adrx2));
  

  regfile regfile( .clk(clk),.RegWrite(RegWrite),.Rd(Result),.Ra(Ra), .Rb(WriteData), .AdrRd(AdrRd),.AdrRa(AdrRa), .AdrRb(AdrRb) );
 

  assign SrcB=(ALUSrc==1'b1) ? imm :WriteData;
  

  ALU  ALU(.SrcA(Ra), .SrcB(SrcB), .ALUControl(ALUControl), .ALUResult (ALUResult),.BeqFlag(BeqFlag_preclk) );
  
  flopr #(1) flagreg(.clk(clk), .reset(reset), .d(BeqFlag_preclk), .q(BeqFlag) );
   

  assign Result_ = (MemToReg==1'b1) ? ReadData : ALUResult;
  

  assign Result = (initRd==1'b1) ? imm : Result_;
  
endmodule
module datapath(   input clk,reset,
  				   output BeqFlag,
                   input  [1:0] AdrRd,
                   input  [1:0] AdrRa,
                   input  [1:0] AdrRb,
                   input  [3:0] imm,
                   input [6:0] Adr,
                   input [1:0] ALUControl,
                   input MemToReg, MemWrite, RegWrite, ALUSrc, J,
                   input Beq,
                output [7:0] PC, 
                output [3:0] ALUResult, WriteData,
                input [3:0] ReadData,
               input initRd);

  
  wire BeqFlag_preclk;
  wire [7:0] PCplusImm,Adrx2,PCplus1,PCpre,imm8;
  wire [1:0] BJ;
  wire [3:0] Result,Ra;
  wire [3:0] SrcB;
  wire [3:0] Result_;
  assign BJ={Beq,J};
  

  pcmux Pcmux (.PCplusImm(PCplusImm),.Adrx2(Adrx2),.PCplus1(PCplus1),.BJ(BJ),.PC(PCpre));
  flopr #(8) PCreg (.clk(clk),.reset(reset), .d(PCpre),.q(PC) );
  adder adder1(.a(PC),.b(imm8),.y(PCplusImm));
  adder adder2(.a(PC), .b(8'b1),.y(PCplus1));
  extendImm extendImm(.imm(imm), .imm8(imm8));
  extendJ extendJ(.Adr(Adr), .Adrx2(Adrx2));
  

  regfile regfile( .clk(clk),.RegWrite(RegWrite),.Rd(Result),.Ra(Ra), .Rb(WriteData), .AdrRd(AdrRd),.AdrRa(AdrRa), .AdrRb(AdrRb) );
 

  assign SrcB=(ALUSrc==1'b1) ? imm :WriteData;
  

  ALU  ALU(.SrcA(Ra), .SrcB(SrcB), .ALUControl(ALUControl), .ALUResult (ALUResult),.BeqFlag(BeqFlag_preclk) );
  
  flopr #(1) flagreg(.clk(clk), .reset(reset), .d(BeqFlag_preclk), .q(BeqFlag) );
   

  assign Result_ = (MemToReg==1'b1) ? ReadData : ALUResult;
  

  assign Result = (initRd==1'b1) ? imm : Result_;
  
endmodule