data/full_repos/permissive/210844779/lab1/1.a.2/fa8bit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/210844779/lab1/1.a.2/fa8bit.v:8: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'C\' generates 1 bits.\n                                                                          : ... In instance fa8bit\n   assign{Carry,Sum}= A + B + C;\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module fa8bit(A,B,C,Sum,Carry);

   input [7:0]A,B;
   input      C;
   output [7:0] Sum;
   output 	Carry;

   assign{Carry,Sum}= A + B + C;
endmodule
module fa8bit(A,B,C,Sum,Carry);


   input [7:0]A,B;
   input      C;
   output [7:0] Sum;
   output 	Carry;

   assign{Carry,Sum}= A + B + C;
endmodule