data/full_repos/permissive/112219256/execute_stage.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/112219256/execute_stage.v:305: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'execute_stage\'\nmodule execute_stage(\n       ^~~~~~~~~~~~~\n                                                                           : ... Top module \'MUX_3_5\'\nmodule MUX_3_5(\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112219256/execute_stage.v:409: Operator NOT expects 3 bits on the LHS, but LHS\'s VARREF \'vaddr\' generates 2 bits.\n                                                                        : ... In instance execute_stage.Store\n  assign size_r = &(~vaddr) ? 3\'b010 : ~vaddr;  \n                                       ^\n%Error: data/full_repos/permissive/112219256/execute_stage.v:241: Cannot find file containing module: \'MUX_4_32\'\n    MUX_4_32 ALUA_MUX(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.v\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.sv\n             MUX_4_32\n             MUX_4_32.v\n             MUX_4_32.sv\n             obj_dir/MUX_4_32\n             obj_dir/MUX_4_32.v\n             obj_dir/MUX_4_32.sv\n%Error: data/full_repos/permissive/112219256/execute_stage.v:250: Cannot find file containing module: \'MUX_4_32\'\n    MUX_4_32 ALUB_MUX(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/execute_stage.v:259: Cannot find file containing module: \'ALU\'\n    ALU ALU(\n    ^~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module MemWrite_Sel(
    input  [3:0] MemWrite_ID_EXE,
    input  [1:0]       SW_ID_EXE,
    input              SB_ID_EXE,
    input              SH_ID_EXE,
    input  [1:0]           vaddr,
    output [3:0]        MemWrite
);
    wire [3:0] MemW_L, MemW_R, MemW_SB, MemW_SH;
    wire [3:0] v;

    assign MemW_L[3] = &vaddr;
    assign MemW_L[2] = vaddr[1];
    assign MemW_L[1] = |vaddr;
    assign MemW_L[0] = 1'b1;

    assign MemW_R[3] = 1'b1;
    assign MemW_R[2] = ~(&vaddr);
    assign MemW_R[1] = ~vaddr[1];
    assign MemW_R[0] = ~(|vaddr);

    assign v[3] =  vaddr[1] &  vaddr[0];
    assign v[2] =  vaddr[1] & ~vaddr[0];
    assign v[1] = ~vaddr[1] &  vaddr[0];
    assign v[0] = ~vaddr[1] & ~vaddr[0];

    assign MemW_SB = ({4{v[0]}} & 4'b0001 | {4{v[1]}} & 4'b0010) |
                     ({4{v[2]}} & 4'b0100 | {4{v[3]}} & 4'b1000) ;

    assign MemW_SH = ({4{v[0]}} & 4'b0011) | ({4{v[2]}} & 4'b1100);


    assign MemWrite = ( SW_ID_EXE[1] &~SW_ID_EXE[0]) ? MemW_L :
                      (~SW_ID_EXE[1] & SW_ID_EXE[0]) ? MemW_R :
                      ( SW_ID_EXE[1] & SW_ID_EXE[0]) ? MemWrite_ID_EXE :
                       SB_ID_EXE           ? MemW_SB :
                       SH_ID_EXE           ? MemW_SH : MemWrite_ID_EXE;
endmodule
module MemWrite_Sel(
    input  [3:0] MemWrite_ID_EXE,
    input  [1:0]       SW_ID_EXE,
    input              SB_ID_EXE,
    input              SH_ID_EXE,
    input  [1:0]           vaddr,
    output [3:0]        MemWrite
);

    wire [3:0] MemW_L, MemW_R, MemW_SB, MemW_SH;
    wire [3:0] v;

    assign MemW_L[3] = &vaddr;
    assign MemW_L[2] = vaddr[1];
    assign MemW_L[1] = |vaddr;
    assign MemW_L[0] = 1'b1;

    assign MemW_R[3] = 1'b1;
    assign MemW_R[2] = ~(&vaddr);
    assign MemW_R[1] = ~vaddr[1];
    assign MemW_R[0] = ~(|vaddr);

    assign v[3] =  vaddr[1] &  vaddr[0];
    assign v[2] =  vaddr[1] & ~vaddr[0];
    assign v[1] = ~vaddr[1] &  vaddr[0];
    assign v[0] = ~vaddr[1] & ~vaddr[0];

    assign MemW_SB = ({4{v[0]}} & 4'b0001 | {4{v[1]}} & 4'b0010) |
                     ({4{v[2]}} & 4'b0100 | {4{v[3]}} & 4'b1000) ;

    assign MemW_SH = ({4{v[0]}} & 4'b0011) | ({4{v[2]}} & 4'b1100);


    assign MemWrite = ( SW_ID_EXE[1] &~SW_ID_EXE[0]) ? MemW_L :
                      (~SW_ID_EXE[1] & SW_ID_EXE[0]) ? MemW_R :
                      ( SW_ID_EXE[1] & SW_ID_EXE[0]) ? MemWrite_ID_EXE :
                       SB_ID_EXE           ? MemW_SB :
                       SH_ID_EXE           ? MemW_SH : MemWrite_ID_EXE;
endmodule