data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_fast_sim_top.sv
1: b'%Error: data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_fast_sim_top.sv:160: Cannot find file containing module: \'sonic_hard_ip_custom\'\n   sonic_hard_ip_custom rp_tx_st (.clk_in(pld_clk),\n   ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep,data/full_repos/permissive/18477150/sonic_hard_ip_custom\n             data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep,data/full_repos/permissive/18477150/sonic_hard_ip_custom.v\n             data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep,data/full_repos/permissive/18477150/sonic_hard_ip_custom.sv\n             sonic_hard_ip_custom\n             sonic_hard_ip_custom.v\n             sonic_hard_ip_custom.sv\n             obj_dir/sonic_hard_ip_custom\n             obj_dir/sonic_hard_ip_custom.v\n             obj_dir/sonic_hard_ip_custom.sv\n%Error: data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_fast_sim_top.sv:179: Cannot find file containing module: \'sonic_rp_top\'\n   sonic_rp_top rp_top (\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_fast_sim_top.sv:214: Cannot find file containing module: \'sonic_application_top\'\n   sonic_application_top ep_top (\n   ^~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_fast_sim_top.sv:275: Operator ASSIGNW expects 13 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h21\' generates 12 bits.\n                                                                                                          : ... In instance sonic_fast_sim_top\n   assign cfg_busdev = 12\'h21;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_fast_sim_top.sv:280: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'ha5\' generates 32 bits.\n                                                                                                          : ... In instance sonic_fast_sim_top\n   assign cfg_msicsr = 32\'ha5;\n                     ^\n%Error: data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_fast_sim_top.sv:286: Cannot find file containing module: \'sonic_monitor\'\n   sonic_monitor sonic_mon (\n   ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module sonic_fast_sim_top (

   xcvr_tx_datain,

   pld_clk, rstn, xcvr_rx_clkout, xcvr_tx_clkout, xcvr_rx_dataout
   ) ;
   parameter USE_MON = 1;
      
   input pld_clk;
   input rstn;
   input 	  xcvr_rx_clkout;
   input 	  xcvr_tx_clkout;
   input [39:0]   xcvr_rx_dataout;
   output [39:0]  xcvr_tx_datain;

   logic [19:0] cfg_io_bas;
   logic [11:0] cfg_np_bas;
   logic [43:0] cfg_pr_bas;
   logic [12:0] cfg_busdev;
   logic [31:0] cfg_devcsr;
   logic [31:0] cfg_prmcsr;
   logic [23:0] cfg_tcvcmap;
   logic [31:0] cfg_linkcsr;
   logic [15:0] cfg_msicsr;
   logic 	cpl_pending;
   logic [6:0] 	cpl_err;
   logic [127:0] err_desc;


   logic 	rp_rx_st_sop;
   logic 	rp_rx_st_eop;
   logic [127:0] rp_rx_st_data;
   logic 	 rp_rx_st_valid;
   logic 	 rp_rx_st_ready;
   logic 	 rp_rx_st_empty;
   logic 	 rp_rx_st_err;
   
   logic 	 rp_rx_st_sop_mon;
   logic 	 rp_rx_st_eop_mon;
   logic [127:0] rp_rx_st_data_mon;
   logic 	 rp_rx_st_valid_mon;
   logic 	 rp_rx_st_ready_mon;
   logic 	 rp_rx_st_empty_mon;
   logic 	 rp_rx_st_err_mon;

   logic 	 rp_rx_st_sop_mux;
   logic 	 rp_rx_st_eop_mux;
   logic [127:0] rp_rx_st_data_mux;
   logic 	 rp_rx_st_valid_mux;
   logic 	 rp_rx_st_ready_mux;
   logic 	 rp_rx_st_empty_mux;
   logic 	 rp_rx_st_err_mux;

   assign rp_rx_st_sop_mux = (USE_MON == 1) ? rp_rx_st_sop_mon : rp_rx_st_sop ;
   assign rp_rx_st_eop_mux = (USE_MON == 1) ? rp_rx_st_eop_mon : rp_rx_st_eop ;
   assign rp_rx_st_data_mux = (USE_MON == 1) ? rp_rx_st_data_mon : rp_rx_st_data ;
   assign rp_rx_st_valid_mux = (USE_MON == 1) ? rp_rx_st_valid_mon : rp_rx_st_valid ;
   assign rp_rx_st_ready_mux = (USE_MON == 1) ? rp_rx_st_ready_mon : rp_rx_st_ready ;
   assign rp_rx_st_empty_mux = (USE_MON == 1) ? rp_rx_st_empty_mon : rp_rx_st_empty ;
   assign rp_rx_st_err_mux = (USE_MON == 1) ? rp_rx_st_err_mon : rp_rx_st_err ;
      
   logic [15:0]  rp_rx_st_be;
   logic [7:0] 	 rp_rx_st_bardec;
   logic 	 rp_rx_st_mask;


   logic 	 ep_rx_st_sop;
   logic 	 ep_rx_st_eop;
   logic [127:0] ep_rx_st_data;
   logic 	 ep_rx_st_err;
   logic 	 ep_rx_st_ready;
   logic 	 ep_rx_st_empty;
   logic 	 ep_rx_st_valid;
   
   logic 	 ep_rx_st_sop_mon;
   logic 	 ep_rx_st_eop_mon;
   logic [127:0] ep_rx_st_data_mon;
   logic 	 ep_rx_st_err_mon;
   logic 	 ep_rx_st_ready_mon;
   logic 	 ep_rx_st_empty_mon;
   logic 	 ep_rx_st_valid_mon;

   logic 	 ep_rx_st_sop_mux;
   logic 	 ep_rx_st_eop_mux;
   logic [127:0] ep_rx_st_data_mux;
   logic 	 ep_rx_st_err_mux;
   logic 	 ep_rx_st_ready_mux;
   logic 	 ep_rx_st_empty_mux;
   logic 	 ep_rx_st_valid_mux;
   
   assign ep_rx_st_sop_mux = (USE_MON == 1) ? ep_rx_st_sop_mon : ep_rx_st_sop ;
   assign ep_rx_st_eop_mux = (USE_MON == 1) ? ep_rx_st_eop_mon : ep_rx_st_eop ;
   assign ep_rx_st_data_mux = (USE_MON == 1) ? ep_rx_st_data_mon : ep_rx_st_data ;
   assign ep_rx_st_err_mux = (USE_MON == 1) ? ep_rx_st_err_mon : ep_rx_st_err ;
   assign ep_rx_st_ready_mux = (USE_MON == 1) ? ep_rx_st_ready_mon : ep_rx_st_ready ;
   assign ep_rx_st_empty_mux = (USE_MON == 1) ? ep_rx_st_empty_mon : ep_rx_st_empty ;
   assign ep_rx_st_valid_mux = (USE_MON == 1) ? ep_rx_st_valid_mon : ep_rx_st_valid ;
   
   logic 	 ep_rx_st_sop_r;
   logic 	 ep_rx_st_eop_r;
   logic [127:0] ep_rx_st_data_r;
   logic 	 ep_rx_st_err_r;
   logic 	 ep_rx_st_empty_r;
   logic 	 ep_rx_st_valid_r;
   
   logic [15:0]   ep_rx_st_be;
   logic [7:0] 	  ep_rx_st_bardec;
   logic 	  tx_fifo_empty;
   
   logic [4:0] 	  pex_msi_num;
   logic 	  app_msi_req;
   logic [2:0] 	  app_msi_tc;
   logic [4:0] 	  app_msi_num;
   logic 	  app_int_sts;
   
   logic 	  pma_tx_ready;
   logic 	  pma_rx_ready;
   
   logic tx_stream_mask;


   sonic_hard_ip_custom rp_tx_st (.clk_in(pld_clk),
				  .rstn(rstn),
				  .tx_st_data(ep_rx_st_data_mux),
				  .tx_st_sop(ep_rx_st_sop_mux),
				  .tx_st_eop(ep_rx_st_eop_mux),
				  .tx_st_valid(ep_rx_st_valid_mux),
				  .tx_st_err(ep_rx_st_err_mux),
				  .tx_st_empty(ep_rx_st_empty_mux),

				  .tx_st_data_r(ep_rx_st_data_r),
				  .tx_st_sop_r(ep_rx_st_sop_r),
				  .tx_st_eop_r(ep_rx_st_eop_r),
				  .tx_st_valid_r(ep_rx_st_valid_r),
				  .tx_st_err_r(ep_rx_st_err_r),
				  .tx_st_empty_r(ep_rx_st_empty_r),
				  .tx_st_be(ep_rx_st_be),
				  .tx_st_bardec(ep_rx_st_bardec)
				  );
      
   sonic_rp_top rp_top (
			       .pld_clk(pld_clk),
			       .rstn(rstn),
			       .cfg_io_bas(cfg_io_bas),
			       .cfg_np_bas(cfg_np_bas),
			       .cfg_pr_bas(cfg_pr_bas),
			       .rx_st_sop(rp_rx_st_sop_mux),
			       .rx_st_eop(rp_rx_st_eop_mux),
			       .rx_st_data(rp_rx_st_data_mux),
			       .rx_st_valid(rp_rx_st_valid_mux),
			       .rx_st_ready(rp_rx_st_ready),
			       .rx_st_empty(rp_rx_st_empty_mux),
			       .rx_st_be(rp_rx_st_be),
			       .rx_st_mask(rp_rx_st_mask),
			       .tx_st_sop(ep_rx_st_sop),
			       .tx_st_eop(ep_rx_st_eop),
			       .tx_st_data(ep_rx_st_data),
			       .tx_st_ready(ep_rx_st_ready_mux),
			       .tx_st_empty(ep_rx_st_empty),
			       .tx_st_valid(ep_rx_st_valid),
			       .tx_fifo_empty(tx_fifo_empty)
			       );

   assign cfg_io_bas = 20'h0;
   assign cfg_np_bas = 12'h0;
   assign cfg_pr_bas = 44'h0;
   assign rp_rx_st_empty = 0;
   

   assign ep_rx_st_err = 0;
         
   sonic_application_top ep_top (

				 .rx_st_sop0(ep_rx_st_sop_r),
				 .rx_st_eop0(ep_rx_st_eop_r),
				 .rx_st_data0(ep_rx_st_data_r),
				 .rx_st_valid0(ep_rx_st_valid_r),
				 .rx_st_ready0(ep_rx_st_ready),
				 .rx_st_empty0(ep_rx_st_empty_r),
				 .rx_st_err0(ep_rx_st_err_r),
				 .rx_st_be0(ep_rx_st_be),
				 .rx_st_bardec0(ep_rx_st_bardec),


				 .tx_st_sop0(rp_rx_st_sop),
				 .tx_st_eop0(rp_rx_st_eop),
				 .tx_st_data0(rp_rx_st_data),

				 .tx_st_valid0(rp_rx_st_valid),
				 .tx_st_ready0(rp_rx_st_ready_mux),


				 .pex_msi_num(pex_msi_num),
				 .app_msi_req(app_msi_req),
				 .app_msi_ack(1'b1),
				 .app_msi_tc(app_msi_tc),
				 .app_msi_num(app_msi_num),

				 .app_int_sts(app_int_sts),
				 .app_int_ack(1'b1),

				 .rx_stream_mask0(tx_stream_mask),
				 .tx_stream_cred0(36'hFFFFFFFFF),
				 .tx_stream_fifo_empty0(1'b1),


				 .cfg_busdev(cfg_busdev),
				 .cfg_devcsr(cfg_devcsr),
				 .cfg_prmcsr(cfg_prmcsr),
				 .cfg_tcvcmap(cfg_tcvcmap),
				 .cfg_linkcsr(cfg_linkcsr),
				 .cfg_msicsr(cfg_msicsr),

				 .cpl_pending(cpl_pending), 
				 .cpl_err(cpl_err),
				 .err_desc(err_desc),


				 .xcvr_rx_clkout(xcvr_rx_clkout),
				 .xcvr_tx_clkout(xcvr_tx_clkout),
				 .xcvr_rx_dataout(xcvr_rx_dataout),
				 .xcvr_tx_datain(xcvr_tx_datain),
				 .pma_tx_ready(pma_tx_ready),
				 .pma_rx_ready(pma_rx_ready),
				 .gen2_speed(),

				 .clk_in(pld_clk),
				 .rstn(rstn)
				 );

   assign pma_tx_ready = 1'b1;
   assign pma_rx_ready = 1'b1;
   assign cfg_busdev = 12'h21;
   assign cfg_devcsr = 32'h1030;
   assign cfg_prmcsr = 32'h6;
   assign cfg_tcvcmap = 24'h0;
   assign cfg_linkcsr = 32'h10820040;
   assign cfg_msicsr = 32'ha5;



   sonic_monitor sonic_mon (
			    .clk_in_clk(pld_clk),
			    .reset_reset_n(rstn),


			    .sonic_tx_monitor_sink_data(rp_rx_st_data),
			    .sonic_tx_monitor_sink_valid(rp_rx_st_valid),
			    .sonic_tx_monitor_sink_ready(rp_rx_st_ready_mon),
			    .sonic_tx_monitor_sink_startofpacket(rp_rx_st_sop),
			    .sonic_tx_monitor_sink_endofpacket(rp_rx_st_eop),
			    .sonic_tx_monitor_sink_empty(rp_rx_st_empty),
			    .sonic_tx_monitor_sink_error(rp_rx_st_err),

			    .sonic_tx_monitor_src_data(rp_rx_st_data_mon),
			    .sonic_tx_monitor_src_valid(rp_rx_st_valid_mon),
			    .sonic_tx_monitor_src_ready(rp_rx_st_ready),
			    .sonic_tx_monitor_src_startofpacket(rp_rx_st_sop_mon),
			    .sonic_tx_monitor_src_endofpacket(rp_rx_st_eop_mon),
			    .sonic_tx_monitor_src_empty(rp_rx_st_empty_mon),
			    .sonic_tx_monitor_src_error(rp_rx_st_err_mon),
      

			    .sonic_rx_monitor_src_data(ep_rx_st_data_mon),
			    .sonic_rx_monitor_src_valid(ep_rx_st_valid_mon),
			    .sonic_rx_monitor_src_ready(ep_rx_st_ready),
			    .sonic_rx_monitor_src_startofpacket(ep_rx_st_sop_mon),
			    .sonic_rx_monitor_src_endofpacket(ep_rx_st_eop_mon),
			    .sonic_rx_monitor_src_empty(ep_rx_st_empty_mon),
			    .sonic_rx_monitor_src_error(ep_rx_st_err_mon),
      
			    .sonic_rx_monitor_sink_data(ep_rx_st_data),
			    .sonic_rx_monitor_sink_valid(ep_rx_st_valid),
			    .sonic_rx_monitor_sink_ready(ep_rx_st_ready_mon),
			    .sonic_rx_monitor_sink_startofpacket(ep_rx_st_sop),
			    .sonic_rx_monitor_sink_endofpacket(ep_rx_st_eop),
			    .sonic_rx_monitor_sink_empty(ep_rx_st_empty),
			    .sonic_rx_monitor_sink_error(ep_rx_st_err)
			    );
      
endmodule
module sonic_fast_sim_top (

   xcvr_tx_datain,

   pld_clk, rstn, xcvr_rx_clkout, xcvr_tx_clkout, xcvr_rx_dataout
   ) ;

   parameter USE_MON = 1;
      
   input pld_clk;
   input rstn;
   input 	  xcvr_rx_clkout;
   input 	  xcvr_tx_clkout;
   input [39:0]   xcvr_rx_dataout;
   output [39:0]  xcvr_tx_datain;

   logic [19:0] cfg_io_bas;
   logic [11:0] cfg_np_bas;
   logic [43:0] cfg_pr_bas;
   logic [12:0] cfg_busdev;
   logic [31:0] cfg_devcsr;
   logic [31:0] cfg_prmcsr;
   logic [23:0] cfg_tcvcmap;
   logic [31:0] cfg_linkcsr;
   logic [15:0] cfg_msicsr;
   logic 	cpl_pending;
   logic [6:0] 	cpl_err;
   logic [127:0] err_desc;


   logic 	rp_rx_st_sop;
   logic 	rp_rx_st_eop;
   logic [127:0] rp_rx_st_data;
   logic 	 rp_rx_st_valid;
   logic 	 rp_rx_st_ready;
   logic 	 rp_rx_st_empty;
   logic 	 rp_rx_st_err;
   
   logic 	 rp_rx_st_sop_mon;
   logic 	 rp_rx_st_eop_mon;
   logic [127:0] rp_rx_st_data_mon;
   logic 	 rp_rx_st_valid_mon;
   logic 	 rp_rx_st_ready_mon;
   logic 	 rp_rx_st_empty_mon;
   logic 	 rp_rx_st_err_mon;

   logic 	 rp_rx_st_sop_mux;
   logic 	 rp_rx_st_eop_mux;
   logic [127:0] rp_rx_st_data_mux;
   logic 	 rp_rx_st_valid_mux;
   logic 	 rp_rx_st_ready_mux;
   logic 	 rp_rx_st_empty_mux;
   logic 	 rp_rx_st_err_mux;

   assign rp_rx_st_sop_mux = (USE_MON == 1) ? rp_rx_st_sop_mon : rp_rx_st_sop ;
   assign rp_rx_st_eop_mux = (USE_MON == 1) ? rp_rx_st_eop_mon : rp_rx_st_eop ;
   assign rp_rx_st_data_mux = (USE_MON == 1) ? rp_rx_st_data_mon : rp_rx_st_data ;
   assign rp_rx_st_valid_mux = (USE_MON == 1) ? rp_rx_st_valid_mon : rp_rx_st_valid ;
   assign rp_rx_st_ready_mux = (USE_MON == 1) ? rp_rx_st_ready_mon : rp_rx_st_ready ;
   assign rp_rx_st_empty_mux = (USE_MON == 1) ? rp_rx_st_empty_mon : rp_rx_st_empty ;
   assign rp_rx_st_err_mux = (USE_MON == 1) ? rp_rx_st_err_mon : rp_rx_st_err ;
      
   logic [15:0]  rp_rx_st_be;
   logic [7:0] 	 rp_rx_st_bardec;
   logic 	 rp_rx_st_mask;


   logic 	 ep_rx_st_sop;
   logic 	 ep_rx_st_eop;
   logic [127:0] ep_rx_st_data;
   logic 	 ep_rx_st_err;
   logic 	 ep_rx_st_ready;
   logic 	 ep_rx_st_empty;
   logic 	 ep_rx_st_valid;
   
   logic 	 ep_rx_st_sop_mon;
   logic 	 ep_rx_st_eop_mon;
   logic [127:0] ep_rx_st_data_mon;
   logic 	 ep_rx_st_err_mon;
   logic 	 ep_rx_st_ready_mon;
   logic 	 ep_rx_st_empty_mon;
   logic 	 ep_rx_st_valid_mon;

   logic 	 ep_rx_st_sop_mux;
   logic 	 ep_rx_st_eop_mux;
   logic [127:0] ep_rx_st_data_mux;
   logic 	 ep_rx_st_err_mux;
   logic 	 ep_rx_st_ready_mux;
   logic 	 ep_rx_st_empty_mux;
   logic 	 ep_rx_st_valid_mux;
   
   assign ep_rx_st_sop_mux = (USE_MON == 1) ? ep_rx_st_sop_mon : ep_rx_st_sop ;
   assign ep_rx_st_eop_mux = (USE_MON == 1) ? ep_rx_st_eop_mon : ep_rx_st_eop ;
   assign ep_rx_st_data_mux = (USE_MON == 1) ? ep_rx_st_data_mon : ep_rx_st_data ;
   assign ep_rx_st_err_mux = (USE_MON == 1) ? ep_rx_st_err_mon : ep_rx_st_err ;
   assign ep_rx_st_ready_mux = (USE_MON == 1) ? ep_rx_st_ready_mon : ep_rx_st_ready ;
   assign ep_rx_st_empty_mux = (USE_MON == 1) ? ep_rx_st_empty_mon : ep_rx_st_empty ;
   assign ep_rx_st_valid_mux = (USE_MON == 1) ? ep_rx_st_valid_mon : ep_rx_st_valid ;
   
   logic 	 ep_rx_st_sop_r;
   logic 	 ep_rx_st_eop_r;
   logic [127:0] ep_rx_st_data_r;
   logic 	 ep_rx_st_err_r;
   logic 	 ep_rx_st_empty_r;
   logic 	 ep_rx_st_valid_r;
   
   logic [15:0]   ep_rx_st_be;
   logic [7:0] 	  ep_rx_st_bardec;
   logic 	  tx_fifo_empty;
   
   logic [4:0] 	  pex_msi_num;
   logic 	  app_msi_req;
   logic [2:0] 	  app_msi_tc;
   logic [4:0] 	  app_msi_num;
   logic 	  app_int_sts;
   
   logic 	  pma_tx_ready;
   logic 	  pma_rx_ready;
   
   logic tx_stream_mask;


   sonic_hard_ip_custom rp_tx_st (.clk_in(pld_clk),
				  .rstn(rstn),
				  .tx_st_data(ep_rx_st_data_mux),
				  .tx_st_sop(ep_rx_st_sop_mux),
				  .tx_st_eop(ep_rx_st_eop_mux),
				  .tx_st_valid(ep_rx_st_valid_mux),
				  .tx_st_err(ep_rx_st_err_mux),
				  .tx_st_empty(ep_rx_st_empty_mux),

				  .tx_st_data_r(ep_rx_st_data_r),
				  .tx_st_sop_r(ep_rx_st_sop_r),
				  .tx_st_eop_r(ep_rx_st_eop_r),
				  .tx_st_valid_r(ep_rx_st_valid_r),
				  .tx_st_err_r(ep_rx_st_err_r),
				  .tx_st_empty_r(ep_rx_st_empty_r),
				  .tx_st_be(ep_rx_st_be),
				  .tx_st_bardec(ep_rx_st_bardec)
				  );
      
   sonic_rp_top rp_top (
			       .pld_clk(pld_clk),
			       .rstn(rstn),
			       .cfg_io_bas(cfg_io_bas),
			       .cfg_np_bas(cfg_np_bas),
			       .cfg_pr_bas(cfg_pr_bas),
			       .rx_st_sop(rp_rx_st_sop_mux),
			       .rx_st_eop(rp_rx_st_eop_mux),
			       .rx_st_data(rp_rx_st_data_mux),
			       .rx_st_valid(rp_rx_st_valid_mux),
			       .rx_st_ready(rp_rx_st_ready),
			       .rx_st_empty(rp_rx_st_empty_mux),
			       .rx_st_be(rp_rx_st_be),
			       .rx_st_mask(rp_rx_st_mask),
			       .tx_st_sop(ep_rx_st_sop),
			       .tx_st_eop(ep_rx_st_eop),
			       .tx_st_data(ep_rx_st_data),
			       .tx_st_ready(ep_rx_st_ready_mux),
			       .tx_st_empty(ep_rx_st_empty),
			       .tx_st_valid(ep_rx_st_valid),
			       .tx_fifo_empty(tx_fifo_empty)
			       );

   assign cfg_io_bas = 20'h0;
   assign cfg_np_bas = 12'h0;
   assign cfg_pr_bas = 44'h0;
   assign rp_rx_st_empty = 0;
   

   assign ep_rx_st_err = 0;
         
   sonic_application_top ep_top (

				 .rx_st_sop0(ep_rx_st_sop_r),
				 .rx_st_eop0(ep_rx_st_eop_r),
				 .rx_st_data0(ep_rx_st_data_r),
				 .rx_st_valid0(ep_rx_st_valid_r),
				 .rx_st_ready0(ep_rx_st_ready),
				 .rx_st_empty0(ep_rx_st_empty_r),
				 .rx_st_err0(ep_rx_st_err_r),
				 .rx_st_be0(ep_rx_st_be),
				 .rx_st_bardec0(ep_rx_st_bardec),


				 .tx_st_sop0(rp_rx_st_sop),
				 .tx_st_eop0(rp_rx_st_eop),
				 .tx_st_data0(rp_rx_st_data),

				 .tx_st_valid0(rp_rx_st_valid),
				 .tx_st_ready0(rp_rx_st_ready_mux),


				 .pex_msi_num(pex_msi_num),
				 .app_msi_req(app_msi_req),
				 .app_msi_ack(1'b1),
				 .app_msi_tc(app_msi_tc),
				 .app_msi_num(app_msi_num),

				 .app_int_sts(app_int_sts),
				 .app_int_ack(1'b1),

				 .rx_stream_mask0(tx_stream_mask),
				 .tx_stream_cred0(36'hFFFFFFFFF),
				 .tx_stream_fifo_empty0(1'b1),


				 .cfg_busdev(cfg_busdev),
				 .cfg_devcsr(cfg_devcsr),
				 .cfg_prmcsr(cfg_prmcsr),
				 .cfg_tcvcmap(cfg_tcvcmap),
				 .cfg_linkcsr(cfg_linkcsr),
				 .cfg_msicsr(cfg_msicsr),

				 .cpl_pending(cpl_pending), 
				 .cpl_err(cpl_err),
				 .err_desc(err_desc),


				 .xcvr_rx_clkout(xcvr_rx_clkout),
				 .xcvr_tx_clkout(xcvr_tx_clkout),
				 .xcvr_rx_dataout(xcvr_rx_dataout),
				 .xcvr_tx_datain(xcvr_tx_datain),
				 .pma_tx_ready(pma_tx_ready),
				 .pma_rx_ready(pma_rx_ready),
				 .gen2_speed(),

				 .clk_in(pld_clk),
				 .rstn(rstn)
				 );

   assign pma_tx_ready = 1'b1;
   assign pma_rx_ready = 1'b1;
   assign cfg_busdev = 12'h21;
   assign cfg_devcsr = 32'h1030;
   assign cfg_prmcsr = 32'h6;
   assign cfg_tcvcmap = 24'h0;
   assign cfg_linkcsr = 32'h10820040;
   assign cfg_msicsr = 32'ha5;



   sonic_monitor sonic_mon (
			    .clk_in_clk(pld_clk),
			    .reset_reset_n(rstn),


			    .sonic_tx_monitor_sink_data(rp_rx_st_data),
			    .sonic_tx_monitor_sink_valid(rp_rx_st_valid),
			    .sonic_tx_monitor_sink_ready(rp_rx_st_ready_mon),
			    .sonic_tx_monitor_sink_startofpacket(rp_rx_st_sop),
			    .sonic_tx_monitor_sink_endofpacket(rp_rx_st_eop),
			    .sonic_tx_monitor_sink_empty(rp_rx_st_empty),
			    .sonic_tx_monitor_sink_error(rp_rx_st_err),

			    .sonic_tx_monitor_src_data(rp_rx_st_data_mon),
			    .sonic_tx_monitor_src_valid(rp_rx_st_valid_mon),
			    .sonic_tx_monitor_src_ready(rp_rx_st_ready),
			    .sonic_tx_monitor_src_startofpacket(rp_rx_st_sop_mon),
			    .sonic_tx_monitor_src_endofpacket(rp_rx_st_eop_mon),
			    .sonic_tx_monitor_src_empty(rp_rx_st_empty_mon),
			    .sonic_tx_monitor_src_error(rp_rx_st_err_mon),
      

			    .sonic_rx_monitor_src_data(ep_rx_st_data_mon),
			    .sonic_rx_monitor_src_valid(ep_rx_st_valid_mon),
			    .sonic_rx_monitor_src_ready(ep_rx_st_ready),
			    .sonic_rx_monitor_src_startofpacket(ep_rx_st_sop_mon),
			    .sonic_rx_monitor_src_endofpacket(ep_rx_st_eop_mon),
			    .sonic_rx_monitor_src_empty(ep_rx_st_empty_mon),
			    .sonic_rx_monitor_src_error(ep_rx_st_err_mon),
      
			    .sonic_rx_monitor_sink_data(ep_rx_st_data),
			    .sonic_rx_monitor_sink_valid(ep_rx_st_valid),
			    .sonic_rx_monitor_sink_ready(ep_rx_st_ready_mon),
			    .sonic_rx_monitor_sink_startofpacket(ep_rx_st_sop),
			    .sonic_rx_monitor_sink_endofpacket(ep_rx_st_eop),
			    .sonic_rx_monitor_sink_empty(ep_rx_st_empty),
			    .sonic_rx_monitor_sink_error(ep_rx_st_err)
			    );
      
endmodule