data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v
None: at end of input
1: b'%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:28: Cannot find include file: spio_spinnaker_link.h\n`include "spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.v\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.sv\n             spio_spinnaker_link.h\n             spio_spinnaker_link.h.v\n             spio_spinnaker_link.h.sv\n             obj_dir/spio_spinnaker_link.h\n             obj_dir/spio_spinnaker_link.h.v\n             obj_dir/spio_spinnaker_link.h.sv\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:49: Define or directive not defined: \'`PKT_BITS\'\n  output wire [`PKT_BITS - 1:0] PKT_DATA_OUT,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:510: Define or directive not defined: \'`PKT_BITS\'\n  output reg  [`PKT_BITS - 1:0] PKT_DATA_OUT,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:538: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] bad_pkt;        \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:550: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] pkt_buf;    \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:650: Define or directive not defined: \'`PKT_BITS\'\n      pkt_buf <= {flt_data_bin, pkt_buf[`PKT_BITS - 1:4]};\n                                        ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module spio_spinnaker_link_synchronous_receiver
(
  input                         CLK_IN,
  input                         RESET_IN,


  output wire                   FLT_ERR_OUT,
  output wire                   FRM_ERR_OUT,
  output wire                   GCH_ERR_OUT,


  input                   [6:0] SL_DATA_2OF7_IN,
  output wire                   SL_ACK_OUT,


  output wire [`PKT_BITS - 1:0] PKT_DATA_OUT,
  output wire                   PKT_VLD_OUT,
  input                         PKT_RDY_IN
);




  wire [6:0] synced_sl_data_2of7;




  wire [6:0] flt_data_bad;
  wire [3:0] flt_data_bin;
  wire       flt_dat;
  wire       flt_bad;
  wire       flt_eop;
  wire       flt_cts;


  spio_spinnaker_link_sync #(.SIZE(7)) sync
  ( .CLK_IN (CLK_IN),
    .IN     (SL_DATA_2OF7_IN),
    .OUT    (synced_sl_data_2of7)
  );
		
  flit_input_if fi
  (
    .CLK_IN          (CLK_IN),
    .RESET_IN        (RESET_IN),
    .GCH_ERR_OUT     (GCH_ERR_OUT),
    .SL_DATA_2OF7_IN (synced_sl_data_2of7),
    .SL_ACK_OUT      (SL_ACK_OUT),
    .flt_data_bad    (flt_data_bad),
    .flt_data_bin    (flt_data_bin),
    .flt_dat         (flt_dat),
    .flt_bad         (flt_bad),
    .flt_eop         (flt_eop),
    .flt_cts         (flt_cts)
  );

  pkt_deserializer pd
  (
    .CLK_IN          (CLK_IN),
    .RESET_IN        (RESET_IN),
    .FLT_ERR_OUT     (FLT_ERR_OUT),
    .FRM_ERR_OUT     (FRM_ERR_OUT),
    .flt_data_bad    (flt_data_bad),
    .flt_data_bin    (flt_data_bin),
    .flt_dat         (flt_dat),
    .flt_bad         (flt_bad),
    .flt_eop         (flt_eop),
    .flt_cts         (flt_cts),
    .PKT_DATA_OUT    (PKT_DATA_OUT),
    .PKT_VLD_OUT     (PKT_VLD_OUT),
    .PKT_RDY_IN      (PKT_RDY_IN)
  );
endmodule
module spio_spinnaker_link_synchronous_receiver
(
  input                         CLK_IN,
  input                         RESET_IN,


  output wire                   FLT_ERR_OUT,
  output wire                   FRM_ERR_OUT,
  output wire                   GCH_ERR_OUT,


  input                   [6:0] SL_DATA_2OF7_IN,
  output wire                   SL_ACK_OUT,


  output wire [`PKT_BITS - 1:0] PKT_DATA_OUT,
  output wire                   PKT_VLD_OUT,
  input                         PKT_RDY_IN
);





  wire [6:0] synced_sl_data_2of7;




  wire [6:0] flt_data_bad;
  wire [3:0] flt_data_bin;
  wire       flt_dat;
  wire       flt_bad;
  wire       flt_eop;
  wire       flt_cts;


  spio_spinnaker_link_sync #(.SIZE(7)) sync
  ( .CLK_IN (CLK_IN),
    .IN     (SL_DATA_2OF7_IN),
    .OUT    (synced_sl_data_2of7)
  );
		
  flit_input_if fi
  (
    .CLK_IN          (CLK_IN),
    .RESET_IN        (RESET_IN),
    .GCH_ERR_OUT     (GCH_ERR_OUT),
    .SL_DATA_2OF7_IN (synced_sl_data_2of7),
    .SL_ACK_OUT      (SL_ACK_OUT),
    .flt_data_bad    (flt_data_bad),
    .flt_data_bin    (flt_data_bin),
    .flt_dat         (flt_dat),
    .flt_bad         (flt_bad),
    .flt_eop         (flt_eop),
    .flt_cts         (flt_cts)
  );

  pkt_deserializer pd
  (
    .CLK_IN          (CLK_IN),
    .RESET_IN        (RESET_IN),
    .FLT_ERR_OUT     (FLT_ERR_OUT),
    .FRM_ERR_OUT     (FRM_ERR_OUT),
    .flt_data_bad    (flt_data_bad),
    .flt_data_bin    (flt_data_bin),
    .flt_dat         (flt_dat),
    .flt_bad         (flt_bad),
    .flt_eop         (flt_eop),
    .flt_cts         (flt_cts),
    .PKT_DATA_OUT    (PKT_DATA_OUT),
    .PKT_VLD_OUT     (PKT_VLD_OUT),
    .PKT_RDY_IN      (PKT_RDY_IN)
  );
endmodule