data/full_repos/permissive/19572582/Lab4/lab4_part4.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/19572582/Lab4/lab4_part4.v:72: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'lab4_part4\'\nmodule lab4_part4 (CLOCK_50, HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LEDR, KEY);\n       ^~~~~~~~~~\n                                                                           : ... Top module \'hex_ssd\'\nmodule hex_ssd (BIN, SSD);\n       ^~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part4.v:54: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output reg [0:6] SSD;\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part4.v:22: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;\n         ^\n%Error: data/full_repos/permissive/19572582/Lab4/lab4_part4.v:28: Cannot find file containing module: \'counter_26bit\'\n  counter_26bit C0 (1, CLOCK_50, Clr, Q);\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19572582/Lab4,data/full_repos/permissive/19572582/counter_26bit\n             data/full_repos/permissive/19572582/Lab4,data/full_repos/permissive/19572582/counter_26bit.v\n             data/full_repos/permissive/19572582/Lab4,data/full_repos/permissive/19572582/counter_26bit.sv\n             counter_26bit\n             counter_26bit.v\n             counter_26bit.sv\n             obj_dir/counter_26bit\n             obj_dir/counter_26bit.v\n             obj_dir/counter_26bit.sv\n%Error: data/full_repos/permissive/19572582/Lab4/lab4_part4.v:29: Cannot find file containing module: \'counter_16bit\'\n  counter_16bit DISPLAY (1, Clr, Clr2, Q2);\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19572582/Lab4/lab4_part4.v:47: Cannot find file containing module: \'t_flipflop\'\n  t_flipflop T0 (1, Clr, 0, LEDR[4]);\n  ^~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part4.v:74: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output reg [0:6] SSD;\n             ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module b2d_ssd (X, SSD);
  input [3:0] X;
  output reg [0:6] SSD;

  always begin
    case(X)
      0:SSD=7'b0000001;
      1:SSD=7'b1001111;
      2:SSD=7'b0010010;
      3:SSD=7'b0000110;
      4:SSD=7'b1001100;
      5:SSD=7'b0100100;
      6:SSD=7'b0100000;
      7:SSD=7'b0001111;
      8:SSD=7'b0000000;
      9:SSD=7'b0001100;
    endcase
  end
endmodule
module b2d_ssd (X, SSD);

  input [3:0] X;
  output reg [0:6] SSD;

  always begin
    case(X)
      0:SSD=7'b0000001;
      1:SSD=7'b1001111;
      2:SSD=7'b0010010;
      3:SSD=7'b0000110;
      4:SSD=7'b1001100;
      5:SSD=7'b0100100;
      6:SSD=7'b0100000;
      7:SSD=7'b0001111;
      8:SSD=7'b0000000;
      9:SSD=7'b0001100;
    endcase
  end
endmodule