data/full_repos/permissive/161029703/src/periph/parallel_ifce.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/161029703/src/periph/parallel_ifce.v:43: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                  : ... In instance parallel_ifce\n    dev_address <= 22\'b0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161029703/src/periph/parallel_ifce.v:44: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                  : ... In instance parallel_ifce\n    dev_wrdata <= 16\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/161029703/src/periph/parallel_ifce.v:51: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'hold_cycle\' generates 4 bits.\n                                                                                  : ... In instance parallel_ifce\n    hold_cycle <= (hold_cycle && hold_cycle < (RW_BUS_CYCLE+1)) ?(hold_cycle+4\'b1): 4\'b0;\n                              ^~\n%Error: Exiting due to 3 warning(s)\n'
module parallel_ifce (

          dev_data,

          bus_data_o,
          bus_stall,
          dev_address,
          dev_we_n,
          dev_oe_n,
          dev_ce_n,

          clk_bus,
          rst_n,
          bus_address,
          bus_data_i,
          bus_read,
          bus_write);

parameter RW_BUS_CYCLE = 4;

input wire clk_bus;
input wire rst_n;

input wire[23:0] bus_address;
input wire[31:0] bus_data_i;
output reg[31:0] bus_data_o;
input wire bus_read;
input wire bus_write;
output wire bus_stall;

output reg[23:0] dev_address;
inout wire[31:0] dev_data;
output reg dev_we_n;
output reg dev_oe_n;
output reg dev_ce_n;

reg[31:0]dev_wrdata;
reg[3:0] hold_cycle;

always @(posedge clk_bus or negedge rst_n) begin
  if (!rst_n) begin
    dev_address <= 22'b0;
    dev_wrdata <= 16'b0;
    dev_we_n <= 1'b1;
    dev_oe_n <= 1'b1;
    dev_ce_n <= 1'b1;
    hold_cycle <= 4'b0;
    bus_data_o <= 32'h0;
  end else begin
    hold_cycle <= (hold_cycle && hold_cycle < (RW_BUS_CYCLE+1)) ?(hold_cycle+4'b1): 4'b0;
    if ((bus_read || bus_write) && hold_cycle == 4'b0) begin
      dev_address <= bus_address;
      dev_wrdata <= bus_data_i;
      dev_we_n <= ~bus_write;
      dev_oe_n <= ~bus_read;
      dev_ce_n <= 1'b0;
      hold_cycle <= 4'b1;
    end else if(hold_cycle == RW_BUS_CYCLE) begin
      dev_we_n <= 1'b1;
      dev_oe_n <= 1'b1;
      dev_ce_n <= 1'b1;
    end
    if(!dev_oe_n)
      bus_data_o <= dev_data;
  end
end

assign dev_data = (~dev_we_n) ? dev_wrdata : {32{1'bz}};
assign bus_stall = (bus_read || bus_write) && (hold_cycle < (RW_BUS_CYCLE+1));

endmodule
module parallel_ifce (

          dev_data,

          bus_data_o,
          bus_stall,
          dev_address,
          dev_we_n,
          dev_oe_n,
          dev_ce_n,

          clk_bus,
          rst_n,
          bus_address,
          bus_data_i,
          bus_read,
          bus_write);


parameter RW_BUS_CYCLE = 4;

input wire clk_bus;
input wire rst_n;

input wire[23:0] bus_address;
input wire[31:0] bus_data_i;
output reg[31:0] bus_data_o;
input wire bus_read;
input wire bus_write;
output wire bus_stall;

output reg[23:0] dev_address;
inout wire[31:0] dev_data;
output reg dev_we_n;
output reg dev_oe_n;
output reg dev_ce_n;

reg[31:0]dev_wrdata;
reg[3:0] hold_cycle;

always @(posedge clk_bus or negedge rst_n) begin
  if (!rst_n) begin
    dev_address <= 22'b0;
    dev_wrdata <= 16'b0;
    dev_we_n <= 1'b1;
    dev_oe_n <= 1'b1;
    dev_ce_n <= 1'b1;
    hold_cycle <= 4'b0;
    bus_data_o <= 32'h0;
  end else begin
    hold_cycle <= (hold_cycle && hold_cycle < (RW_BUS_CYCLE+1)) ?(hold_cycle+4'b1): 4'b0;
    if ((bus_read || bus_write) && hold_cycle == 4'b0) begin
      dev_address <= bus_address;
      dev_wrdata <= bus_data_i;
      dev_we_n <= ~bus_write;
      dev_oe_n <= ~bus_read;
      dev_ce_n <= 1'b0;
      hold_cycle <= 4'b1;
    end else if(hold_cycle == RW_BUS_CYCLE) begin
      dev_we_n <= 1'b1;
      dev_oe_n <= 1'b1;
      dev_ce_n <= 1'b1;
    end
    if(!dev_oe_n)
      bus_data_o <= dev_data;
  end
end

assign dev_data = (~dev_we_n) ? dev_wrdata : {32{1'bz}};
assign bus_stall = (bus_read || bus_write) && (hold_cycle < (RW_BUS_CYCLE+1));

endmodule