data/full_repos/permissive/174783592/IFU/inc16bitTB.v
 line:35: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/174783592/IFU/inc16bitTB.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #30 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174783592/IFU/inc16bitTB.v:38: Unsupported: Ignoring delay on this delayed statement.\n    always #2 clk <= ~clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/174783592/IFU/inc16bitTB.v:39: Unsupported: Ignoring delay on this delayed statement.\n    always #2 pc <= pc +1;\n           ^\n%Error: data/full_repos/permissive/174783592/IFU/inc16bitTB.v:43: Unsupported or unknown PLI call: $monitor\n    initial $monitor($time," clk=%d  pc=%b j=%d pcwire=%b",clk,pc,inc1.j,pcwire);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module inc16bitTB();

    reg [15:0] pc;
    reg clk;
    wire [15:0]pcwire;

    inc16bit inc1(pc,pcwire,clk);

    initial
    begin
      pc <= {{4{2'b10}},{2{4'b0000}}};
      clk<=0;
        #30 $finish;
    end

    always #2 clk <= ~clk;
    always #2 pc <= pc +1;


    
    initial $monitor($time," clk=%d  pc=%b j=%d pcwire=%b",clk,pc,inc1.j,pcwire);
endmodule
module inc16bitTB();


    reg [15:0] pc;
    reg clk;
    wire [15:0]pcwire;

    inc16bit inc1(pc,pcwire,clk);

    initial
    begin
      pc <= {{4{2'b10}},{2{4'b0000}}};
      clk<=0;
        #30 $finish;
    end

    always #2 clk <= ~clk;
    always #2 pc <= pc +1;


    
    initial $monitor($time," clk=%d  pc=%b j=%d pcwire=%b",clk,pc,inc1.j,pcwire);
endmodule