data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v
1: b'%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:22: Cannot find include file: urv_defs.v\n`include "urv_defs.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v.sv\n             urv_defs.v\n             urv_defs.v.v\n             urv_defs.v.sv\n             obj_dir/urv_defs.v\n             obj_dir/urv_defs.v.v\n             obj_dir/urv_defs.v.sv\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:68: Define or directive not defined: \'`CSR_ID_CYCLESL\'\n       `CSR_ID_CYCLESL: csr_in1 <= csr_cycles_i[31:0];\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:68: syntax error, unexpected \':\', expecting endcase\n       `CSR_ID_CYCLESL: csr_in1 <= csr_cycles_i[31:0];\n                      ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:69: Define or directive not defined: \'`CSR_ID_CYCLESH\'\n       `CSR_ID_CYCLESH: csr_in1 <= { 24\'h0, csr_cycles_i[39:32] };\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:70: Define or directive not defined: \'`CSR_ID_TIMEL\'\n       `CSR_ID_TIMEL: csr_in1 <= csr_time_i[31:0];\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:71: Define or directive not defined: \'`CSR_ID_TIMEH\'\n       `CSR_ID_TIMEH: csr_in1 <= { 24\'h0, csr_time_i[39:32] };\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:72: Define or directive not defined: \'`CSR_ID_MSCRATCH\'\n       `CSR_ID_MSCRATCH: csr_in1 <= csr_mscratch;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:73: Define or directive not defined: \'`CSR_ID_MEPC\'\n       `CSR_ID_MEPC: csr_in1 <= csr_mepc_i;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:74: Define or directive not defined: \'`CSR_ID_MSTATUS\'\n       `CSR_ID_MSTATUS: csr_in1 <= csr_mstatus_i;\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:75: Define or directive not defined: \'`CSR_ID_MCAUSE\'\n       `CSR_ID_MCAUSE: csr_in1 <= csr_mcause_i;\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:76: Define or directive not defined: \'`CSR_ID_MIP\'\n       `CSR_ID_MIP: csr_in1 <= csr_mip_i;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:77: Define or directive not defined: \'`CSR_ID_MIE\'\n       `CSR_ID_MIE: csr_in1 <= csr_mie_i;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:89: Define or directive not defined: \'`CSR_OP_CSRRWI\'\n       `CSR_OP_CSRRWI,\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:89: syntax error, unexpected \',\', expecting endcase\n       `CSR_OP_CSRRWI,\n                     ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:90: Define or directive not defined: \'`CSR_OP_CSRRSI\'\n       `CSR_OP_CSRRSI,\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:91: Define or directive not defined: \'`CSR_OP_CSRRCI\'\n       `CSR_OP_CSRRCI:\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:105: Define or directive not defined: \'`CSR_OP_CSRRWI\'\n        `CSR_OP_CSRRWI, \n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:106: Define or directive not defined: \'`CSR_OP_CSRRW\'\n        `CSR_OP_CSRRW:\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:108: Define or directive not defined: \'`CSR_OP_CSRRCI\'\n        `CSR_OP_CSRRCI,\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:109: Define or directive not defined: \'`CSR_OP_CSRRC\'\n        `CSR_OP_CSRRC:\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:111: Define or directive not defined: \'`CSR_OP_CSRRSI\'\n        `CSR_OP_CSRRSI,\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:112: Define or directive not defined: \'`CSR_OP_CSRRS\'\n        `CSR_OP_CSRRS:\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_csr.v:127: Define or directive not defined: \'`CSR_ID_MSCRATCH\'\n  `CSR_ID_MSCRATCH: \n  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 23 error(s)\n'
module urv_csr
  (
   input 	     clk_i,
   input 	     rst_i,

   input 	     x_stall_i,
   input 	     x_kill_i,
   
   input 	     d_is_csr_i,
   input [2:0] 	     d_fun_i,
   input [4:0] 	     d_csr_imm_i,
   input [11:0]      d_csr_sel_i,
   
   
   input [31:0]      d_rs1_i,
   
   output reg [31:0] x_rd_o,
   
   input [39:0]      csr_time_i,
   input [39:0]      csr_cycles_i,



   output [31:0]     x_csr_write_value_o,

   input [31:0]      csr_mstatus_i,
   input [31:0]      csr_mip_i,
   input [31:0]      csr_mie_i,
   input [31:0]      csr_mepc_i,
   input [31:0]      csr_mcause_i

   );
   
   reg [31:0] 	csr_mscratch; 
   
   reg [31:0] 	csr_in1;
   reg [31:0] 	csr_in2;
   reg [31:0] 	csr_out;

  
   always@*
     case(d_csr_sel_i)
       `CSR_ID_CYCLESL: csr_in1 <= csr_cycles_i[31:0];
       `CSR_ID_CYCLESH: csr_in1 <= { 24'h0, csr_cycles_i[39:32] };
       `CSR_ID_TIMEL: csr_in1 <= csr_time_i[31:0];
       `CSR_ID_TIMEH: csr_in1 <= { 24'h0, csr_time_i[39:32] };
       `CSR_ID_MSCRATCH: csr_in1 <= csr_mscratch;
       `CSR_ID_MEPC: csr_in1 <= csr_mepc_i;
       `CSR_ID_MSTATUS: csr_in1 <= csr_mstatus_i;
       `CSR_ID_MCAUSE: csr_in1 <= csr_mcause_i;
       `CSR_ID_MIP: csr_in1 <= csr_mip_i;
       `CSR_ID_MIE: csr_in1 <= csr_mie_i;
       default: csr_in1 <= 32'hx;
     endcase

   always@*
     x_rd_o <= csr_in1;

   genvar 	i;

   
   always@*
     case (d_fun_i)
       `CSR_OP_CSRRWI,
       `CSR_OP_CSRRSI,
       `CSR_OP_CSRRCI:
	 csr_in2 <= {27'b0, d_csr_imm_i };
       default:
	 csr_in2 <= d_rs1_i;
     endcase

   generate

      
      for (i=0;i<32;i=i+1) 
	begin : gen_csr_bits

	   always@*
	     case(d_fun_i)
	       `CSR_OP_CSRRWI, 
	       `CSR_OP_CSRRW:
		 csr_out[i] <= csr_in2[i];
	       `CSR_OP_CSRRCI,
	       `CSR_OP_CSRRC:
		 csr_out[i] <= csr_in2[i] ? 1'b0 : csr_in1[i];
	       `CSR_OP_CSRRSI,
	       `CSR_OP_CSRRS:
		 csr_out[i] <= csr_in2[i] ? 1'b1 : csr_in1[i];
	       default:
		 csr_out[i] <= 32'hx;
	     endcase
	end
      
      endgenerate
   
   
   always@(posedge clk_i)
     if(rst_i) 
       csr_mscratch <= 0;
     else if(!x_stall_i && !x_kill_i && d_is_csr_i) 
       case (d_csr_sel_i)
	 `CSR_ID_MSCRATCH: 
	   csr_mscratch <= csr_out;
       endcase
   

   assign x_csr_write_value_o = csr_out;

   
endmodule
module urv_csr
  (
   input 	     clk_i,
   input 	     rst_i,

   input 	     x_stall_i,
   input 	     x_kill_i,
   
   input 	     d_is_csr_i,
   input [2:0] 	     d_fun_i,
   input [4:0] 	     d_csr_imm_i,
   input [11:0]      d_csr_sel_i,
   
   
   input [31:0]      d_rs1_i,
   
   output reg [31:0] x_rd_o,
   
   input [39:0]      csr_time_i,
   input [39:0]      csr_cycles_i,



   output [31:0]     x_csr_write_value_o,

   input [31:0]      csr_mstatus_i,
   input [31:0]      csr_mip_i,
   input [31:0]      csr_mie_i,
   input [31:0]      csr_mepc_i,
   input [31:0]      csr_mcause_i

   );

   
   reg [31:0] 	csr_mscratch; 
   
   reg [31:0] 	csr_in1;
   reg [31:0] 	csr_in2;
   reg [31:0] 	csr_out;

  
   always@*
     case(d_csr_sel_i)
       `CSR_ID_CYCLESL: csr_in1 <= csr_cycles_i[31:0];
       `CSR_ID_CYCLESH: csr_in1 <= { 24'h0, csr_cycles_i[39:32] };
       `CSR_ID_TIMEL: csr_in1 <= csr_time_i[31:0];
       `CSR_ID_TIMEH: csr_in1 <= { 24'h0, csr_time_i[39:32] };
       `CSR_ID_MSCRATCH: csr_in1 <= csr_mscratch;
       `CSR_ID_MEPC: csr_in1 <= csr_mepc_i;
       `CSR_ID_MSTATUS: csr_in1 <= csr_mstatus_i;
       `CSR_ID_MCAUSE: csr_in1 <= csr_mcause_i;
       `CSR_ID_MIP: csr_in1 <= csr_mip_i;
       `CSR_ID_MIE: csr_in1 <= csr_mie_i;
       default: csr_in1 <= 32'hx;
     endcase

   always@*
     x_rd_o <= csr_in1;

   genvar 	i;

   
   always@*
     case (d_fun_i)
       `CSR_OP_CSRRWI,
       `CSR_OP_CSRRSI,
       `CSR_OP_CSRRCI:
	 csr_in2 <= {27'b0, d_csr_imm_i };
       default:
	 csr_in2 <= d_rs1_i;
     endcase

   generate

      
      for (i=0;i<32;i=i+1) 
	begin : gen_csr_bits

	   always@*
	     case(d_fun_i)
	       `CSR_OP_CSRRWI, 
	       `CSR_OP_CSRRW:
		 csr_out[i] <= csr_in2[i];
	       `CSR_OP_CSRRCI,
	       `CSR_OP_CSRRC:
		 csr_out[i] <= csr_in2[i] ? 1'b0 : csr_in1[i];
	       `CSR_OP_CSRRSI,
	       `CSR_OP_CSRRS:
		 csr_out[i] <= csr_in2[i] ? 1'b1 : csr_in1[i];
	       default:
		 csr_out[i] <= 32'hx;
	     endcase
	end
      
      endgenerate
   
   
   always@(posedge clk_i)
     if(rst_i) 
       csr_mscratch <= 0;
     else if(!x_stall_i && !x_kill_i && d_is_csr_i) 
       case (d_csr_sel_i)
	 `CSR_ID_MSCRATCH: 
	   csr_mscratch <= csr_out;
       endcase
   

   assign x_csr_write_value_o = csr_out;

   
endmodule