data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n                #5; clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n                #5; clk = ~clk;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        Ta = 0; Tb = 0; #12;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        Tb = 1; #10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        Tb = 0; #20;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        Ta = 1; #15;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        Ta = 0; #5;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        Ta = 1; Tb = 0; #10;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        Tb = 0; #20;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        Tb = 1; #25;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        reset = 0; #5; \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        reset = 1; #10;\n                   ^\n%Error: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:35: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("data/dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:36: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/197806087/fsm-practice/traffic_control/tb.v:37: Unsupported or unknown PLI call: $monitor\n        $monitor("At time=%2t, clk=%d, reset=%d, Ta=%d, Tb=%d, La=%d, Lb=%d",\n        ^~~~~~~~\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
    reg clk, reset, Ta, Tb;
    wire [1:0] La;
    wire [1:0] Lb;
    trafficfsm t1(.clk(clk), .reset(reset), .Ta(Ta), .Tb(Tb), .La(La), .Lb(Lb));
    integer i;
    initial begin
        clk = 0;
        reset = 0;
        Ta = 0;
        Tb = 0;
        if(1) begin
            for(i = 0; i <= 1000; i = i+1) begin
                #5; clk = ~clk;
                #5; clk = ~clk;
            end
        end
    end
    initial begin
        reset = 1;
        Ta = 0; Tb = 0; #12;
        Tb = 1; #10;
        Tb = 0; #20;
        Ta = 1; #15;
        Ta = 0; #5;
        Ta = 1; Tb = 0; #10;
        Tb = 0; #20;
        Tb = 1; #25;
        reset = 0; #5; 
        reset = 1; #10;

    end
    initial begin
        $dumpfile("data/dumpfile.vcd");
        $dumpvars(0, tb);
        $monitor("At time=%2t, clk=%d, reset=%d, Ta=%d, Tb=%d, La=%d, Lb=%d",
                $time, clk, reset, Ta, Tb, La, Lb);
    end
endmodule
module tb;

    reg clk, reset, Ta, Tb;
    wire [1:0] La;
    wire [1:0] Lb;
    trafficfsm t1(.clk(clk), .reset(reset), .Ta(Ta), .Tb(Tb), .La(La), .Lb(Lb));
    integer i;
    initial begin
        clk = 0;
        reset = 0;
        Ta = 0;
        Tb = 0;
        if(1) begin
            for(i = 0; i <= 1000; i = i+1) begin
                #5; clk = ~clk;
                #5; clk = ~clk;
            end
        end
    end
    initial begin
        reset = 1;
        Ta = 0; Tb = 0; #12;
        Tb = 1; #10;
        Tb = 0; #20;
        Ta = 1; #15;
        Ta = 0; #5;
        Ta = 1; Tb = 0; #10;
        Tb = 0; #20;
        Tb = 1; #25;
        reset = 0; #5; 
        reset = 1; #10;

    end
    initial begin
        $dumpfile("data/dumpfile.vcd");
        $dumpvars(0, tb);
        $monitor("At time=%2t, clk=%d, reset=%d, Ta=%d, Tb=%d, La=%d, Lb=%d",
                $time, clk, reset, Ta, Tb, La, Lb);
    end
endmodule