data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n     forever #5 clk_source = !clk_source;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n     forever #5 clk = !clk;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n     forever #1280 modulation_wave = !modulation_wave;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n     #5\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n     #5\n     ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:78: Define or directive not defined: \'`ADDR_AMP_MIN\'\n     avalon_write(`ADDR_AMP_MIN,14\'h0); \n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:80: Define or directive not defined: \'`ADDR_POINT\'\n     avalon_write(`ADDR_POINT,16\'d256); \n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:81: Define or directive not defined: \'`ADDR_CONTROL\'\n     avalon_write(`ADDR_CONTROL,8\'h1); \n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:83: Define or directive not defined: \'`ADDR_CONTROL\'\n      avalon_write(`ADDR_CONTROL,8\'h0);\n                   ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n     #30000\n     ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:85: Define or directive not defined: \'`ADDR_CONTROL\'\n      avalon_write(`ADDR_CONTROL,8\'h3);\n                   ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n     #1000\n     ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:87: Define or directive not defined: \'`ADDR_CONTROL\'\n      avalon_write(`ADDR_CONTROL,8\'h5);\n                   ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n     #50000\n     ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:89: Define or directive not defined: \'`ADDR_AMP_MAX\'\n      avalon_write(`ADDR_AMP_MAX,14\'h1fff);\n                   ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n     #50000\n     ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:91: Define or directive not defined: \'`ADDR_AMP_MIN\'\n      avalon_write(`ADDR_AMP_MIN,14\'h1000);\n                   ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n     #50000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n     #50000\n     ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:95: Define or directive not defined: \'`ADDR_CONTROL\'\n      avalon_write(`ADDR_CONTROL,8\'h7);\n                   ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n     #50000\n     ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:96: Define or directive not defined: \'`ADDR_DAC\'\n                                                                                                   : ... Suggested alternative: \'`ADDR_AD\'\n      avalon_write(`ADDR_DAC,14\'h3fff);\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:98: Define or directive not defined: \'`ADDR_DAC\'\n                                                                                                   : ... Suggested alternative: \'`ADDR_AD\'\n      avalon_write(`ADDR_DAC,14\'h2fff); \n                   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n     #1000 \n     ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:100: Define or directive not defined: \'`ADDR_DAC\'\n                                                                                                    : ... Suggested alternative: \'`ADDR_AD\'\n      avalon_write(`ADDR_DAC,14\'h1fff);\n                   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n     #1000 \n     ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:102: Define or directive not defined: \'`ADDR_DAC\'\n                                                                                                    : ... Suggested alternative: \'`ADDR_AD\'\n      avalon_write(`ADDR_DAC,14\'h0);            \n                   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n     #1000 \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/demodulation/hdl/demodulation_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n      #1000 $stop;\n      ^\n%Error: Exiting due to 13 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module demodulation_tb;

 	reg clk,reset_n,avs_s0_chipselect,avs_s0_read,avs_s0_write;
 	reg [31:0] avs_s0_writedata;
 	wire [31:0] avs_s0_readdata;
 	reg [2:0] avs_s0_address;
 	reg clk_source;
 	reg modulation_wave;
 	reg [13:0] ad;
 	wire [13:0] dac;			
 			
 demodulation tb(clk,reset_n,avs_s0_chipselect,avs_s0_write,avs_s0_read,avs_s0_writedata,avs_s0_readdata,avs_s0_address,clk_source,modulation_wave,ad,dac);
		
	defparam tb.Sample1Start=16'd32;
	defparam tb.Sample2Start=16'd128;
	defparam tb.Sample1Num=16'd32;
	defparam tb.Sample2Num=16'd32;
	defparam tb.FreqDiv=32'h1;
	

 initial                         
   begin
     clk_source = 0;
     forever #`delay clk_source = !clk_source;
   end
 initial                         
   begin
     clk=0;
     forever #`delay clk = !clk;
   end
 initial                         
   begin
     modulation_wave=0;
     forever #`delay_lage modulation_wave = !modulation_wave;
   end   
   
task  avalon_write;
  input [2:0] addr;
  input [31:0] data;
  begin
  #`delay;
	avs_s0_address=addr;
	avs_s0_writedata=data;
	avs_s0_chipselect=1;
	avs_s0_write=1;
	#`delay;
	avs_s0_chipselect=0;
	avs_s0_write=0;
	end
endtask
   
 initial                         
   begin
     reset_n = 1;
     #`delay
     reset_n = 0;
     #`delay
     reset_n = 1;
     
     avalon_write(`ADDR_SAMPLE1_START,14'h3fff);
     avalon_write(`ADDR_AMP_MIN,14'h0); 
     avalon_write(`ADDR_FREQ_DIV,32'd3); 
     avalon_write(`ADDR_POINT,16'd256); 
     avalon_write(`ADDR_CONTROL,8'h1); 
     #30000
      avalon_write(`ADDR_CONTROL,8'h0);
     #1000
      avalon_write(`ADDR_CONTROL,8'h3);
     #50000
      avalon_write(`ADDR_CONTROL,8'h5);
     #50000
      avalon_write(`ADDR_AMP_MAX,14'h1fff);
     #50000
      avalon_write(`ADDR_AMP_MIN,14'h1000);
     #50000
      avalon_write(`ADDR_FREQ_DIV,32'h5);
     #50000
      avalon_write(`ADDR_CONTROL,8'h7);
      avalon_write(`ADDR_DAC,14'h3fff);
     #1000 
      avalon_write(`ADDR_DAC,14'h2fff); 
     #1000 
      avalon_write(`ADDR_DAC,14'h1fff);
     #1000 
      avalon_write(`ADDR_DAC,14'h0);            
      #1000 $stop;
     
   end

 endmodule
module demodulation_tb;


 	reg clk,reset_n,avs_s0_chipselect,avs_s0_read,avs_s0_write;
 	reg [31:0] avs_s0_writedata;
 	wire [31:0] avs_s0_readdata;
 	reg [2:0] avs_s0_address;
 	reg clk_source;
 	reg modulation_wave;
 	reg [13:0] ad;
 	wire [13:0] dac;			
 			
 demodulation tb(clk,reset_n,avs_s0_chipselect,avs_s0_write,avs_s0_read,avs_s0_writedata,avs_s0_readdata,avs_s0_address,clk_source,modulation_wave,ad,dac);
		
	defparam tb.Sample1Start=16'd32;
	defparam tb.Sample2Start=16'd128;
	defparam tb.Sample1Num=16'd32;
	defparam tb.Sample2Num=16'd32;
	defparam tb.FreqDiv=32'h1;
	

 initial                         
   begin
     clk_source = 0;
     forever #`delay clk_source = !clk_source;
   end
 initial                         
   begin
     clk=0;
     forever #`delay clk = !clk;
   end
 initial                         
   begin
     modulation_wave=0;
     forever #`delay_lage modulation_wave = !modulation_wave;
   end   
   
task  avalon_write;
  input [2:0] addr;
  input [31:0] data;
  begin
  #`delay;
	avs_s0_address=addr;
	avs_s0_writedata=data;
	avs_s0_chipselect=1;
	avs_s0_write=1;
	#`delay;
	avs_s0_chipselect=0;
	avs_s0_write=0;
	end
endtask
   
 initial                         
   begin
     reset_n = 1;
     #`delay
     reset_n = 0;
     #`delay
     reset_n = 1;
     
     avalon_write(`ADDR_SAMPLE1_START,14'h3fff);
     avalon_write(`ADDR_AMP_MIN,14'h0); 
     avalon_write(`ADDR_FREQ_DIV,32'd3); 
     avalon_write(`ADDR_POINT,16'd256); 
     avalon_write(`ADDR_CONTROL,8'h1); 
     #30000
      avalon_write(`ADDR_CONTROL,8'h0);
     #1000
      avalon_write(`ADDR_CONTROL,8'h3);
     #50000
      avalon_write(`ADDR_CONTROL,8'h5);
     #50000
      avalon_write(`ADDR_AMP_MAX,14'h1fff);
     #50000
      avalon_write(`ADDR_AMP_MIN,14'h1000);
     #50000
      avalon_write(`ADDR_FREQ_DIV,32'h5);
     #50000
      avalon_write(`ADDR_CONTROL,8'h7);
      avalon_write(`ADDR_DAC,14'h3fff);
     #1000 
      avalon_write(`ADDR_DAC,14'h2fff); 
     #1000 
      avalon_write(`ADDR_DAC,14'h1fff);
     #1000 
      avalon_write(`ADDR_DAC,14'h0);            
      #1000 $stop;
     
   end

 endmodule