data/full_repos/permissive/170365068/Single verilog file/mipsFull.v
1: b'%Error: Cannot find file containing module: verilog\n        ... Looked in:\n             data/full_repos/permissive/170365068/Single/verilog\n             data/full_repos/permissive/170365068/Single/verilog.v\n             data/full_repos/permissive/170365068/Single/verilog.sv\n             verilog\n             verilog.v\n             verilog.sv\n             obj_dir/verilog\n             obj_dir/verilog.v\n             obj_dir/verilog.sv\n%Error: Cannot find file containing module: file,data/full_repos/permissive/170365068\n%Error: Cannot find file containing module: data/full_repos/permissive/170365068/Single\n%Error: Cannot find file containing module: file/mipsFull.v\n%Error: Exiting due to 4 error(s)\n'
module ALUControl(instruction1,ALUop,ALUCon);

	input [5:0] instruction1;
	input [1:0]ALUop;
	
	output reg [3:0] ALUCon;
	
	wire [7:0] ALUControlIn;  
	assign ALUControlIn = {ALUop,instruction1};
	
	always@(*)
	begin
		casex(ALUControlIn)
			8'b10100000: ALUCon=4'b0010;
			8'b10100010: ALUCon=4'b0110;
			8'b10100100: ALUCon=4'b0000;
			8'b10100101: ALUCon=4'b0001;
			8'b10101010: ALUCon=4'b0111;
			8'b10101111: ALUCon=4'b0011;
			8'b01xxxxxx: ALUCon=4'b0110;
			8'b00xxxxxx: ALUCon=4'b0010;
			default: ALUCon=4'b0010;
		endcase
	end
	
endmodule
module ALUControl(instruction1,ALUop,ALUCon);


	input [5:0] instruction1;
	input [1:0]ALUop;
	
	output reg [3:0] ALUCon;
	
	wire [7:0] ALUControlIn;  
	assign ALUControlIn = {ALUop,instruction1};
	
	always@(*)
	begin
		casex(ALUControlIn)
			8'b10100000: ALUCon=4'b0010;
			8'b10100010: ALUCon=4'b0110;
			8'b10100100: ALUCon=4'b0000;
			8'b10100101: ALUCon=4'b0001;
			8'b10101010: ALUCon=4'b0111;
			8'b10101111: ALUCon=4'b0011;
			8'b01xxxxxx: ALUCon=4'b0110;
			8'b00xxxxxx: ALUCon=4'b0010;
			default: ALUCon=4'b0010;
		endcase
	end
	
endmodule