data/full_repos/permissive/136422019/src/computerP3_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP3_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n #101\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/136422019/src/computerP3_tb.v:7: Cannot find file containing module: \'computer\'\ncomputer cp(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/computer\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/computer.v\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/computer.sv\n             computer\n             computer.v\n             computer.sv\n             obj_dir/computer\n             obj_dir/computer.v\n             obj_dir/computer.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module computerP3_tb;


reg [31:0] busDataIn;
reg reset;
computer cp(
	reset,
	busDataIn
);

initial begin
	reset <= 1;
	#101
	reset <= 0;
end
	
endmodule
module computerP3_tb;



reg [31:0] busDataIn;
reg reset;
computer cp(
	reset,
	busDataIn
);

initial begin
	reset <= 1;
	#101
	reset <= 0;
end
	
endmodule