data/full_repos/permissive/218779832/mem_data.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/cdc468b5-5217-4411-bdd3-bf3385fbcea6.xml
module DataMemory
(
    input           clk,
    input           WR,
    input           S20,
    input           S50,
    input   [7:0]   SP_in,
    input   [7:0]   R0_in,
    input   [7:0]   NPC_in,
    input   [7:0]   RN_in,
    output  [7:0]   dataOut

);

    reg [7:0] dataMem[255:0];
    wire [7:0] address;
    wire [7:0] dataIn;

    assign address = S20 ? SP_in : R0_in;
    assign dataIn = S50 ? RN_in : NPC_in;
    assign dataOut = dataMem[address];

    always @(posedge clk)
    begin
    if (WR)
        dataMem[address] <= dataIn;
    end
    

endmodule
module DataMemory
(
    input           clk,
    input           WR,
    input           S20,
    input           S50,
    input   [7:0]   SP_in,
    input   [7:0]   R0_in,
    input   [7:0]   NPC_in,
    input   [7:0]   RN_in,
    output  [7:0]   dataOut

);


    reg [7:0] dataMem[255:0];
    wire [7:0] address;
    wire [7:0] dataIn;

    assign address = S20 ? SP_in : R0_in;
    assign dataIn = S50 ? RN_in : NPC_in;
    assign dataOut = dataMem[address];

    always @(posedge clk)
    begin
    if (WR)
        dataMem[address] <= dataIn;
    end
    

endmodule