data/full_repos/permissive/201753306/src_v/dbg_bridge_uart.v
data/verilator_xmls/03df915f-7649-40dd-ae94-31435301b35e.xml
module dbg_bridge_uart




#(
    parameter UART_DIVISOR_W   = 9
)




(

    input         clk_i,
    input         rst_i,


    input [UART_DIVISOR_W-1:0] bit_div_i,
    input         stop_bits_i,


    input         wr_i,
    input  [7:0]  data_i,
    output        tx_busy_o,


    input         rd_i,
    output [7:0]  data_o,
    output        rx_ready_o,

    output        rx_err_o,


    input         rxd_i,
    output        txd_o
);




localparam   START_BIT = 4'd0;
localparam   STOP_BIT0 = 4'd9;
localparam   STOP_BIT1 = 4'd10;





reg                       tx_busy_q;
reg [3:0]                 tx_bits_q;
reg [UART_DIVISOR_W-1:0]  tx_count_q;
reg [7:0]                 tx_shift_reg_q;
reg                       txd_q;


reg                       rxd_q;
reg [7:0]                 rx_data_q;
reg [3:0]                 rx_bits_q;
reg [UART_DIVISOR_W-1:0]  rx_count_q;
reg [7:0]                 rx_shift_reg_q;
reg                       rx_ready_q;
reg                       rx_busy_q;

reg                       rx_err_q;




reg rxd_ms_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
   rxd_ms_q <= 1'b1;
   rxd_q    <= 1'b1;
end
else
begin
   rxd_ms_q <= rxd_i;
   rxd_q    <= rxd_ms_q;
end




wire rx_sample_w = (rx_count_q == {(UART_DIVISOR_W){1'b0}});

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    rx_count_q     <= {(UART_DIVISOR_W){1'b0}};
else
begin

    if (!rx_busy_q)
        rx_count_q    <= {1'b0, bit_div_i[UART_DIVISOR_W-1:1]};

    else if (rx_count_q != 0)
        rx_count_q    <= (rx_count_q - 1);

    else if (rx_sample_w)
    begin

        if ((rx_bits_q == STOP_BIT0 && !stop_bits_i) || (rx_bits_q == STOP_BIT1 && stop_bits_i))
            rx_count_q    <= {(UART_DIVISOR_W){1'b0}};
        else
            rx_count_q    <= bit_div_i;
    end
end




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    rx_shift_reg_q <= 8'h00;
    rx_busy_q      <= 1'b0;
end

else if (rx_busy_q && rx_sample_w)
begin

    if (rx_bits_q == STOP_BIT0 && !stop_bits_i)
        rx_busy_q <= 1'b0;
    else if (rx_bits_q == STOP_BIT1 && stop_bits_i)
        rx_busy_q <= 1'b0;
    else if (rx_bits_q == START_BIT)
    begin


        if (rxd_q)
            rx_busy_q <= 1'b0;
    end

    else 
        rx_shift_reg_q <= {rxd_q, rx_shift_reg_q[7:1]};
end

else if (!rx_busy_q && rxd_q == 1'b0)
begin
    rx_shift_reg_q <= 8'h00;
    rx_busy_q      <= 1'b1;
end

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    rx_bits_q  <= START_BIT;
else if (rx_sample_w && rx_busy_q)
begin
    if ((rx_bits_q == STOP_BIT1 && stop_bits_i) || (rx_bits_q == STOP_BIT0 && !stop_bits_i))
        rx_bits_q <= START_BIT;
    else
        rx_bits_q <= rx_bits_q + 4'd1;
end
else if (!rx_busy_q && (bit_div_i == {(UART_DIVISOR_W){1'b0}}))
    rx_bits_q  <= START_BIT + 4'd1;
else if (!rx_busy_q)
    rx_bits_q  <= START_BIT;




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
   rx_ready_q      <= 1'b0;
   rx_data_q       <= 8'h00;
   rx_err_q        <= 1'b0;
end
else
begin

   if (rd_i == 1'b1)
   begin
       rx_ready_q <= 1'b0;
       rx_err_q   <= 1'b0;
   end

   if (rx_busy_q && rx_sample_w)
   begin

       if ((rx_bits_q == STOP_BIT1 && stop_bits_i) || (rx_bits_q == STOP_BIT0 && !stop_bits_i))
       begin

           if (rxd_q)
           begin
               rx_data_q      <= rx_shift_reg_q;
               rx_ready_q     <= 1'b1;
           end


           else
           begin
               rx_ready_q      <= 1'b0;
               rx_data_q       <= 8'h00;
               rx_err_q        <= 1'b1;
           end
       end

       else if (rx_bits_q == START_BIT && rxd_q)
           rx_err_q        <= 1'b1;
   end
end




wire tx_sample_w = (tx_count_q == {(UART_DIVISOR_W){1'b0}});

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    tx_count_q      <= {(UART_DIVISOR_W){1'b0}};
else
begin

    if (!tx_busy_q)
        tx_count_q  <= bit_div_i;

    else if (tx_count_q != 0)
        tx_count_q  <= (tx_count_q - 1);
    else if (tx_sample_w)
        tx_count_q  <= bit_div_i;
end




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    tx_shift_reg_q <= 8'h00;
    tx_busy_q      <= 1'b0;
end

else if (tx_busy_q)
begin

    if (tx_bits_q != START_BIT && tx_sample_w)
        tx_shift_reg_q <= {1'b0, tx_shift_reg_q[7:1]};


    if (tx_bits_q == STOP_BIT0 && tx_sample_w && !stop_bits_i)
        tx_busy_q <= 1'b0;
    else if (tx_bits_q == STOP_BIT1 && tx_sample_w && stop_bits_i)
        tx_busy_q <= 1'b0;
end

else if (wr_i)
begin
    tx_shift_reg_q <= data_i;
    tx_busy_q      <= 1'b1;
end

always @ (posedge clk_i or posedge rst_i )
if (rst_i)
    tx_bits_q  <= 4'd0;
else if (tx_sample_w && tx_busy_q)
begin
    if ((tx_bits_q == STOP_BIT1 && stop_bits_i) || (tx_bits_q == STOP_BIT0 && !stop_bits_i))
        tx_bits_q <= START_BIT;
    else
        tx_bits_q <= tx_bits_q + 4'd1;
end




reg txd_r;

always @ *
begin
    txd_r = 1'b1;

    if (tx_busy_q)
    begin

        if (tx_bits_q == START_BIT)
            txd_r = 1'b0;

        else if (tx_bits_q == STOP_BIT0 || tx_bits_q == STOP_BIT1)
            txd_r = 1'b1;

        else
            txd_r = tx_shift_reg_q[0];
    end
end

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    txd_q <= 1'b1;
else
    txd_q <= txd_r;




assign tx_busy_o  = tx_busy_q;
assign rx_ready_o = rx_ready_q;
assign txd_o      = txd_q;
assign data_o     = rx_data_q;
assign rx_err_o   = rx_err_q;

endmodule
module dbg_bridge_uart




#(
    parameter UART_DIVISOR_W   = 9
)




(

    input         clk_i,
    input         rst_i,


    input [UART_DIVISOR_W-1:0] bit_div_i,
    input         stop_bits_i,


    input         wr_i,
    input  [7:0]  data_i,
    output        tx_busy_o,


    input         rd_i,
    output [7:0]  data_o,
    output        rx_ready_o,

    output        rx_err_o,


    input         rxd_i,
    output        txd_o
);





localparam   START_BIT = 4'd0;
localparam   STOP_BIT0 = 4'd9;
localparam   STOP_BIT1 = 4'd10;





reg                       tx_busy_q;
reg [3:0]                 tx_bits_q;
reg [UART_DIVISOR_W-1:0]  tx_count_q;
reg [7:0]                 tx_shift_reg_q;
reg                       txd_q;


reg                       rxd_q;
reg [7:0]                 rx_data_q;
reg [3:0]                 rx_bits_q;
reg [UART_DIVISOR_W-1:0]  rx_count_q;
reg [7:0]                 rx_shift_reg_q;
reg                       rx_ready_q;
reg                       rx_busy_q;

reg                       rx_err_q;




reg rxd_ms_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
   rxd_ms_q <= 1'b1;
   rxd_q    <= 1'b1;
end
else
begin
   rxd_ms_q <= rxd_i;
   rxd_q    <= rxd_ms_q;
end




wire rx_sample_w = (rx_count_q == {(UART_DIVISOR_W){1'b0}});

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    rx_count_q     <= {(UART_DIVISOR_W){1'b0}};
else
begin

    if (!rx_busy_q)
        rx_count_q    <= {1'b0, bit_div_i[UART_DIVISOR_W-1:1]};

    else if (rx_count_q != 0)
        rx_count_q    <= (rx_count_q - 1);

    else if (rx_sample_w)
    begin

        if ((rx_bits_q == STOP_BIT0 && !stop_bits_i) || (rx_bits_q == STOP_BIT1 && stop_bits_i))
            rx_count_q    <= {(UART_DIVISOR_W){1'b0}};
        else
            rx_count_q    <= bit_div_i;
    end
end




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    rx_shift_reg_q <= 8'h00;
    rx_busy_q      <= 1'b0;
end

else if (rx_busy_q && rx_sample_w)
begin

    if (rx_bits_q == STOP_BIT0 && !stop_bits_i)
        rx_busy_q <= 1'b0;
    else if (rx_bits_q == STOP_BIT1 && stop_bits_i)
        rx_busy_q <= 1'b0;
    else if (rx_bits_q == START_BIT)
    begin


        if (rxd_q)
            rx_busy_q <= 1'b0;
    end

    else 
        rx_shift_reg_q <= {rxd_q, rx_shift_reg_q[7:1]};
end

else if (!rx_busy_q && rxd_q == 1'b0)
begin
    rx_shift_reg_q <= 8'h00;
    rx_busy_q      <= 1'b1;
end

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    rx_bits_q  <= START_BIT;
else if (rx_sample_w && rx_busy_q)
begin
    if ((rx_bits_q == STOP_BIT1 && stop_bits_i) || (rx_bits_q == STOP_BIT0 && !stop_bits_i))
        rx_bits_q <= START_BIT;
    else
        rx_bits_q <= rx_bits_q + 4'd1;
end
else if (!rx_busy_q && (bit_div_i == {(UART_DIVISOR_W){1'b0}}))
    rx_bits_q  <= START_BIT + 4'd1;
else if (!rx_busy_q)
    rx_bits_q  <= START_BIT;




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
   rx_ready_q      <= 1'b0;
   rx_data_q       <= 8'h00;
   rx_err_q        <= 1'b0;
end
else
begin

   if (rd_i == 1'b1)
   begin
       rx_ready_q <= 1'b0;
       rx_err_q   <= 1'b0;
   end

   if (rx_busy_q && rx_sample_w)
   begin

       if ((rx_bits_q == STOP_BIT1 && stop_bits_i) || (rx_bits_q == STOP_BIT0 && !stop_bits_i))
       begin

           if (rxd_q)
           begin
               rx_data_q      <= rx_shift_reg_q;
               rx_ready_q     <= 1'b1;
           end


           else
           begin
               rx_ready_q      <= 1'b0;
               rx_data_q       <= 8'h00;
               rx_err_q        <= 1'b1;
           end
       end

       else if (rx_bits_q == START_BIT && rxd_q)
           rx_err_q        <= 1'b1;
   end
end




wire tx_sample_w = (tx_count_q == {(UART_DIVISOR_W){1'b0}});

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    tx_count_q      <= {(UART_DIVISOR_W){1'b0}};
else
begin

    if (!tx_busy_q)
        tx_count_q  <= bit_div_i;

    else if (tx_count_q != 0)
        tx_count_q  <= (tx_count_q - 1);
    else if (tx_sample_w)
        tx_count_q  <= bit_div_i;
end




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    tx_shift_reg_q <= 8'h00;
    tx_busy_q      <= 1'b0;
end

else if (tx_busy_q)
begin

    if (tx_bits_q != START_BIT && tx_sample_w)
        tx_shift_reg_q <= {1'b0, tx_shift_reg_q[7:1]};


    if (tx_bits_q == STOP_BIT0 && tx_sample_w && !stop_bits_i)
        tx_busy_q <= 1'b0;
    else if (tx_bits_q == STOP_BIT1 && tx_sample_w && stop_bits_i)
        tx_busy_q <= 1'b0;
end

else if (wr_i)
begin
    tx_shift_reg_q <= data_i;
    tx_busy_q      <= 1'b1;
end

always @ (posedge clk_i or posedge rst_i )
if (rst_i)
    tx_bits_q  <= 4'd0;
else if (tx_sample_w && tx_busy_q)
begin
    if ((tx_bits_q == STOP_BIT1 && stop_bits_i) || (tx_bits_q == STOP_BIT0 && !stop_bits_i))
        tx_bits_q <= START_BIT;
    else
        tx_bits_q <= tx_bits_q + 4'd1;
end




reg txd_r;

always @ *
begin
    txd_r = 1'b1;

    if (tx_busy_q)
    begin

        if (tx_bits_q == START_BIT)
            txd_r = 1'b0;

        else if (tx_bits_q == STOP_BIT0 || tx_bits_q == STOP_BIT1)
            txd_r = 1'b1;

        else
            txd_r = tx_shift_reg_q[0];
    end
end

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    txd_q <= 1'b1;
else
    txd_q <= txd_r;




assign tx_busy_o  = tx_busy_q;
assign rx_ready_o = rx_ready_q;
assign txd_o      = txd_q;
assign data_o     = rx_data_q;
assign rx_err_o   = rx_err_q;

endmodule