data/full_repos/permissive/140357212/Tomasulo/som_sub.v
data/verilator_xmls/c0624678-5823-419a-a107-aeac64765990.xml
module FU_add_sub(clk,RUN,RegX,RegY,OpCode,Result,Done,InputX_AddSub,InputLabel_AddSub,AddressX,Label);
	input [8:0]RegX,RegY;
	input [2:0]OpCode,InputX_AddSub,InputLabel_AddSub;
	input clk,RUN;
	output reg Done;
	output [2:0]AddressX,Label;
	output reg [8:0]Result;
	wire [2:0]count;
	
	assign AddressX = InputX_AddSub;
	assign Label = InputLabel_AddSub;
	
	always@(clk,RegX,RegY,OpCode,RUN) begin
		Done = 0;
		if(count == 2 && OpCode == 3'b000) begin
			Result = RegX + RegY;
			Done = 1;
		end
		else if(count == 2 && OpCode == 3'b001) begin
			Result = RegX - RegY;
			Done = 1;
		end
	end
	Count c(clk,RUN,Done,count);
endmodule
module FU_add_sub(clk,RUN,RegX,RegY,OpCode,Result,Done,InputX_AddSub,InputLabel_AddSub,AddressX,Label);

	input [8:0]RegX,RegY;
	input [2:0]OpCode,InputX_AddSub,InputLabel_AddSub;
	input clk,RUN;
	output reg Done;
	output [2:0]AddressX,Label;
	output reg [8:0]Result;
	wire [2:0]count;
	
	assign AddressX = InputX_AddSub;
	assign Label = InputLabel_AddSub;
	
	always@(clk,RegX,RegY,OpCode,RUN) begin
		Done = 0;
		if(count == 2 && OpCode == 3'b000) begin
			Result = RegX + RegY;
			Done = 1;
		end
		else if(count == 2 && OpCode == 3'b001) begin
			Result = RegX - RegY;
			Done = 1;
		end
	end
	Count c(clk,RUN,Done,count);
endmodule