data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
1: b'%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v:62: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v:64: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module or1200_dpram_256x32(

	clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
	clk_b, rst_b, ce_b, we_b, addr_b, di_b
);




parameter aw = 8;
parameter dw = 32;




input			clk_a;
input			rst_a;
input			ce_a;
input			oe_a;
input 	[aw-1:0]	addr_a;
output	[dw-1:0]	do_a;
input			clk_b;
input			rst_b;
input			ce_b;
input			we_b;
input 	[aw-1:0]	addr_b;
input	[dw-1:0]	di_b;


`ifdef OR1200_XILINX_RAMB4










RAMB4_S16_S16 ramb4_s16_0(
	.CLKA(clk_a),
	.RSTA(rst_a),
	.ADDRA(addr_a),
	.DIA(16'h0000),
	.ENA(ce_a),
	.WEA(1'b0),
	.DOA(do_a[15:0]),

	.CLKB(clk_b),
	.RSTB(rst_b),
	.ADDRB(addr_b),
	.DIB(di_b[15:0]),
	.ENB(ce_b),
	.WEB(we_b),
	.DOB()
);




RAMB4_S16_S16 ramb4_s16_1(
	.CLKA(clk_a),
	.RSTA(rst_a),
	.ADDRA(addr_a),
	.DIA(16'h0000),
	.ENA(ce_a),
	.WEA(1'b0),
	.DOA(do_a[31:16]),

	.CLKB(clk_b),
	.RSTB(rst_b),
	.ADDRB(addr_b),
	.DIB(di_b[31:16]),
	.ENB(ce_b),
	.WEB(we_b),
	.DOB()
);

`else

`ifdef OR1200_XILINX_RAMB16









RAMB16_S36_S36 ramb16_s36_s36(
	.CLKA(clk_a),
	.SSRA(rst_a),
	.ADDRA({1'b0, addr_a}),
	.DIA(32'h00000000),
	.DIPA(4'h0),
 	.ENA(ce_a),
	.WEA(1'b0),
	.DOA(do_a),
	.DOPA(),

	.CLKB(clk_b),
	.SSRB(rst_b),
	.ADDRB({1'b0, addr_b}),
	.DIB(di_b),
	.DIPB(4'h0),
	.ENB(ce_b),
	.WEB(we_b),
	.DOB(),
	.DOPB()
);

`else








reg	[dw-1:0]	mem [(1<<aw)-1:0];
reg	[aw-1:0]	addr_a_reg;




assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};




always @(posedge clk_a or posedge rst_a)
	if (rst_a)
		addr_a_reg <= #1 {aw{1'b0}};
	else if (ce_a)
		addr_a_reg <= #1 addr_a;




always @(posedge clk_b)
	if (ce_b && we_b)
		mem[addr_b] <= #1 di_b;

`endif
`endif
endmodule
module or1200_dpram_256x32(

	clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
	clk_b, rst_b, ce_b, we_b, addr_b, di_b
);





parameter aw = 8;
parameter dw = 32;




input			clk_a;
input			rst_a;
input			ce_a;
input			oe_a;
input 	[aw-1:0]	addr_a;
output	[dw-1:0]	do_a;
input			clk_b;
input			rst_b;
input			ce_b;
input			we_b;
input 	[aw-1:0]	addr_b;
input	[dw-1:0]	di_b;


`ifdef OR1200_XILINX_RAMB4










RAMB4_S16_S16 ramb4_s16_0(
	.CLKA(clk_a),
	.RSTA(rst_a),
	.ADDRA(addr_a),
	.DIA(16'h0000),
	.ENA(ce_a),
	.WEA(1'b0),
	.DOA(do_a[15:0]),

	.CLKB(clk_b),
	.RSTB(rst_b),
	.ADDRB(addr_b),
	.DIB(di_b[15:0]),
	.ENB(ce_b),
	.WEB(we_b),
	.DOB()
);




RAMB4_S16_S16 ramb4_s16_1(
	.CLKA(clk_a),
	.RSTA(rst_a),
	.ADDRA(addr_a),
	.DIA(16'h0000),
	.ENA(ce_a),
	.WEA(1'b0),
	.DOA(do_a[31:16]),

	.CLKB(clk_b),
	.RSTB(rst_b),
	.ADDRB(addr_b),
	.DIB(di_b[31:16]),
	.ENB(ce_b),
	.WEB(we_b),
	.DOB()
);

`else

`ifdef OR1200_XILINX_RAMB16









RAMB16_S36_S36 ramb16_s36_s36(
	.CLKA(clk_a),
	.SSRA(rst_a),
	.ADDRA({1'b0, addr_a}),
	.DIA(32'h00000000),
	.DIPA(4'h0),
 	.ENA(ce_a),
	.WEA(1'b0),
	.DOA(do_a),
	.DOPA(),

	.CLKB(clk_b),
	.SSRB(rst_b),
	.ADDRB({1'b0, addr_b}),
	.DIB(di_b),
	.DIPB(4'h0),
	.ENB(ce_b),
	.WEB(we_b),
	.DOB(),
	.DOPB()
);

`else








reg	[dw-1:0]	mem [(1<<aw)-1:0];
reg	[aw-1:0]	addr_a_reg;




assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};




always @(posedge clk_a or posedge rst_a)
	if (rst_a)
		addr_a_reg <= #1 {aw{1'b0}};
	else if (ce_a)
		addr_a_reg <= #1 addr_a;




always @(posedge clk_b)
	if (ce_b && we_b)
		mem[addr_b] <= #1 di_b;

`endif
`endif
endmodule