data/full_repos/permissive/19572582/Lab3/lab3_part3.v
data/verilator_xmls/119c4759-008c-4b78-aee7-ea6db3e9d0ad.xml
module Dflop (Clk, D, Q);
  input Clk, D;
  output Q;

  wire S, R;
  
  assign S = D;
  assign R = ~D;
  
  wire R_g, S_g, Qa, Qb; 
  


	assign S_g = S & Clk;



	assign R_g = R & Clk;
	
	assign Qa = ~(R_g | Qb);
	assign Qb = ~(S_g | Qa);
	
	assign Q = Qa;

endmodule
module Dflop (Clk, D, Q);

  input Clk, D;
  output Q;

  wire S, R;
  
  assign S = D;
  assign R = ~D;
  
  wire R_g, S_g, Qa, Qb; 
  


	assign S_g = S & Clk;



	assign R_g = R & Clk;
	
	assign Qa = ~(R_g | Qb);
	assign Qb = ~(S_g | Qa);
	
	assign Q = Qa;

endmodule