data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v
 line:44: before: "("
1: b'%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v:22: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("mux_41.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v:23: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v:40: syntax error, unexpected \'@\'\n      @ (posedge clk);\n      ^\n%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v:45: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v:47: Unsupported: Ignoring delay on this delayed statement.\n         #10;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v:62: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v:74: Unsupported: Ignoring delay on this delayed statement.\n   always #40 clk <= ~clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v:76: Unsupported: Ignoring delay on this delayed statement.\n   always #121 valid_0 <= ~valid_0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v:77: Unsupported: Ignoring delay on this delayed statement.\n   always #121 valid_1 <= ~valid_1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v:78: Unsupported: Ignoring delay on this delayed statement.\n   always #121 valid_2 <= ~valid_2;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tester.v:79: Unsupported: Ignoring delay on this delayed statement.\n   always #121 valid_3 <= ~valid_3;\n          ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_41_tester (
                   output reg       clk,
                   output reg       reset_L,
                   output reg [3:0] data_0,
                   output reg [3:0] data_1,
                   output reg [3:0] data_2,
                   output reg [3:0] data_3,
                   output reg       valid_0,
                   output reg       valid_1,
                   output reg       valid_2,
                   output reg       valid_3,
                   input [3:0]      data_out_cond,
                   input [3:0]      data_out_est,
                   input            valid_out_cond,
                   input            valid_out_est
                   );

   reg [2:0]                   counter;

   initial begin
      $dumpfile("mux_41.vcd");
      $dumpvars;
      data_0 <= 4'b0000;
      data_1 <= 4'b1010;
      data_2 <= 4'b0101;
      data_3 <= 4'b1111;
      reset_L <= 1'b0;


      valid_0 <= 'b1;
      valid_1 <= 'b1;
      valid_2 <= 'b1;
      valid_3 <= 'b1;


      counter <= 'b0;


      @ (posedge clk);
      reset_L <= 1'b1;


      repeat (16) begin
         @(posedge clk);

         #10;

         counter <= counter + 1;

         if (counter > 'b1) begin
            data_0 <= data_0 + 1;
            data_1 <= data_1 - 1;
            data_2 <= data_2 + 1;
            data_3 <= data_3 - 1;
            counter <= 'b0;
         end

      end


      @(posedge clk);
      data_0 = 4'b0;
      data_1 = 4'b0;
      data_2 = 4'b0;
      data_3 = 4'b0;

      $finish;

   end

   initial clk <= 0;

   always #40 clk <= ~clk;

   always #121 valid_0 <= ~valid_0;
   always #121 valid_1 <= ~valid_1;
   always #121 valid_2 <= ~valid_2;
   always #121 valid_3 <= ~valid_3;

endmodule
module mux_41_tester (
                   output reg       clk,
                   output reg       reset_L,
                   output reg [3:0] data_0,
                   output reg [3:0] data_1,
                   output reg [3:0] data_2,
                   output reg [3:0] data_3,
                   output reg       valid_0,
                   output reg       valid_1,
                   output reg       valid_2,
                   output reg       valid_3,
                   input [3:0]      data_out_cond,
                   input [3:0]      data_out_est,
                   input            valid_out_cond,
                   input            valid_out_est
                   );


   reg [2:0]                   counter;

   initial begin
      $dumpfile("mux_41.vcd");
      $dumpvars;
      data_0 <= 4'b0000;
      data_1 <= 4'b1010;
      data_2 <= 4'b0101;
      data_3 <= 4'b1111;
      reset_L <= 1'b0;


      valid_0 <= 'b1;
      valid_1 <= 'b1;
      valid_2 <= 'b1;
      valid_3 <= 'b1;


      counter <= 'b0;


      @ (posedge clk);
      reset_L <= 1'b1;


      repeat (16) begin
         @(posedge clk);

         #10;

         counter <= counter + 1;

         if (counter > 'b1) begin
            data_0 <= data_0 + 1;
            data_1 <= data_1 - 1;
            data_2 <= data_2 + 1;
            data_3 <= data_3 - 1;
            counter <= 'b0;
         end

      end


      @(posedge clk);
      data_0 = 4'b0;
      data_1 = 4'b0;
      data_2 = 4'b0;
      data_3 = 4'b0;

      $finish;

   end

   initial clk <= 0;

   always #40 clk <= ~clk;

   always #121 valid_0 <= ~valid_0;
   always #121 valid_1 <= ~valid_1;
   always #121 valid_2 <= ~valid_2;
   always #121 valid_3 <= ~valid_3;

endmodule