data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:72: Operator ASSIGNDLY expects 512 bits on the Assign RHS, but Assign RHS\'s CONST \'511\'h0\' generates 511 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n default:selReg[511:0] <= 511\'d0;\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:65: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'sel1\' generates 2 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel1)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h5\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h6\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h7\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hb\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hd\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'he\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:81: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hf\' generates 4 bits.\n                                                                                                : ... In instance prm_chk_v1_0\n case(sel2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/prm_chk_v1_0.v:109: Operator ASSIGNDLY expects 2048 bits on the Assign RHS, but Assign RHS\'s CONST \'2047\'h0\' generates 2047 bits.\n                                                                                                 : ... In instance prm_chk_v1_0\n   edgeResult <= 2047\'b0;\n              ^~\n%Error: Exiting due to 19 warning(s)\n'
module prm_chk_v1_0 
	(

		input CLK,
		input RST_n,

		input [1:0] sel1,
		input [7:0] sel2,

		input [11:0] xyzInput,

		output [3:0] x,
		output [3:0] y,
		output [3:0] z,
		input [2047:0] edge_mask,

		output [31:0] result_imp


	);

	wire [2047:0] outputMask_Wire;

	reg [2047:0] edgeResult;
	reg [511:0] selReg;
	reg [11:0] slv_reg0;

always @(posedge CLK)begin
if (!RST_n) begin
    slv_reg0 <= {(12){1'd0}};
end
else begin
    slv_reg0 <= xyzInput;
end
end



always @(*) begin
	case(sel1)

		3'd0: selReg[511:0] <= edgeResult[511:0];
		3'd1: selReg[511:0] <= edgeResult[1023:512];
		3'd2: selReg[511:0] <= edgeResult[1535:1024];
		3'd3: selReg[511:0] <= edgeResult[2047:1536];

	default:selReg[511:0] <= 511'd0;
	endcase
end

reg [31:0] result_imp_reg;
assign result_imp = result_imp_reg;


always @(*) begin
	case(sel2)

		4'd0: result_imp_reg[31:0] <= selReg[31:0];
		4'd1: result_imp_reg[31:0] <= selReg[63:32];
		4'd2: result_imp_reg[31:0] <= selReg[95:64];
		4'd3: result_imp_reg[31:0] <= selReg[127:96];
		4'd4: result_imp_reg[31:0] <= selReg[159:128];
		4'd5: result_imp_reg[31:0] <= selReg[191:160];
		4'd6: result_imp_reg[31:0] <= selReg[223:192];
		4'd7: result_imp_reg[31:0] <= selReg[255:224];
		4'd8: result_imp_reg[31:0] <= selReg[287:256];
		4'd9: result_imp_reg[31:0] <= selReg[319:288];
		4'd10: result_imp_reg[31:0] <= selReg[351:320];
		4'd11: result_imp_reg[31:0] <= selReg[383:352];
		4'd12: result_imp_reg[31:0] <= selReg[415:384];
		4'd13: result_imp_reg[31:0] <= selReg[447:416];
		4'd14: result_imp_reg[31:0] <= selReg[479:448];
		4'd15: result_imp_reg[31:0] <= selReg[511:480];

	default:result_imp_reg[31:0] <= 32'd0;
	endcase
end



	always @ ( posedge CLK ) begin

		if ( !RST_n ) begin
			edgeResult <= 2047'b0;
		end

		else begin
			edgeResult <= edgeResult | outputMask_Wire;

		end
	end


assign outputMask_Wire = edge_mask;
assign {x,y,z} = slv_reg0;





	endmodule
module prm_chk_v1_0 
	(

		input CLK,
		input RST_n,

		input [1:0] sel1,
		input [7:0] sel2,

		input [11:0] xyzInput,

		output [3:0] x,
		output [3:0] y,
		output [3:0] z,
		input [2047:0] edge_mask,

		output [31:0] result_imp


	);


	wire [2047:0] outputMask_Wire;

	reg [2047:0] edgeResult;
	reg [511:0] selReg;
	reg [11:0] slv_reg0;

always @(posedge CLK)begin
if (!RST_n) begin
    slv_reg0 <= {(12){1'd0}};
end
else begin
    slv_reg0 <= xyzInput;
end
end



always @(*) begin
	case(sel1)

		3'd0: selReg[511:0] <= edgeResult[511:0];
		3'd1: selReg[511:0] <= edgeResult[1023:512];
		3'd2: selReg[511:0] <= edgeResult[1535:1024];
		3'd3: selReg[511:0] <= edgeResult[2047:1536];

	default:selReg[511:0] <= 511'd0;
	endcase
end

reg [31:0] result_imp_reg;
assign result_imp = result_imp_reg;


always @(*) begin
	case(sel2)

		4'd0: result_imp_reg[31:0] <= selReg[31:0];
		4'd1: result_imp_reg[31:0] <= selReg[63:32];
		4'd2: result_imp_reg[31:0] <= selReg[95:64];
		4'd3: result_imp_reg[31:0] <= selReg[127:96];
		4'd4: result_imp_reg[31:0] <= selReg[159:128];
		4'd5: result_imp_reg[31:0] <= selReg[191:160];
		4'd6: result_imp_reg[31:0] <= selReg[223:192];
		4'd7: result_imp_reg[31:0] <= selReg[255:224];
		4'd8: result_imp_reg[31:0] <= selReg[287:256];
		4'd9: result_imp_reg[31:0] <= selReg[319:288];
		4'd10: result_imp_reg[31:0] <= selReg[351:320];
		4'd11: result_imp_reg[31:0] <= selReg[383:352];
		4'd12: result_imp_reg[31:0] <= selReg[415:384];
		4'd13: result_imp_reg[31:0] <= selReg[447:416];
		4'd14: result_imp_reg[31:0] <= selReg[479:448];
		4'd15: result_imp_reg[31:0] <= selReg[511:480];

	default:result_imp_reg[31:0] <= 32'd0;
	endcase
end



	always @ ( posedge CLK ) begin

		if ( !RST_n ) begin
			edgeResult <= 2047'b0;
		end

		else begin
			edgeResult <= edgeResult | outputMask_Wire;

		end
	end


assign outputMask_Wire = edge_mask;
assign {x,y,z} = slv_reg0;





	endmodule