data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog/wb_ram_xilinx.v
 line:43: before: "waddr"
1: b"%Error: data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog/wb_ram_xilinx.v:40: Cannot find file containing module: 'wb_ram_xilinx_bank'\n   wb_ram_xilinx_bank bank0(\n   ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog,data/full_repos/permissive/175132042/wb_ram_xilinx_bank\n             data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog,data/full_repos/permissive/175132042/wb_ram_xilinx_bank.v\n             data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog,data/full_repos/permissive/175132042/wb_ram_xilinx_bank.sv\n             wb_ram_xilinx_bank\n             wb_ram_xilinx_bank.v\n             wb_ram_xilinx_bank.sv\n             obj_dir/wb_ram_xilinx_bank\n             obj_dir/wb_ram_xilinx_bank.v\n             obj_dir/wb_ram_xilinx_bank.sv\n%Error: data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog/wb_ram_xilinx.v:53: Cannot find file containing module: 'wb_ram_xilinx_bank'\n   wb_ram_xilinx_bank bank1(\n   ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module wb_ram_xilinx (

   dout,

   clk, rst, we, din, waddr, raddr
   ) ;

   
   input clk;
   input rst;   
   input [3:0] we;
   input [31:0] din;
   input [14:0] waddr;
   input [14:0] raddr;
   output wire [31:0] dout;

   initial begin
      $display("WB XILINX RAM");
      
   end
   
   wire bank_select = waddr[13] | raddr[13];
   
   wire [31:0] dout_bank0;
   wire [31:0] dout_bank1;

   assign dout = bank_select ? dout_bank1 : dout_bank0;
   
   
   wb_ram_xilinx_bank bank0(

                            .dout               (dout_bank0[31:0]),

                            .clk                (clk),
                            .rst                (rst),
                            .bank_select        (~bank_select),
                            .we                 (we[3:0]),
                            .din                (din[31:0]),
                            .waddr              (waddr[12:0]),
                            .raddr              (raddr[12:0]));
   

   wb_ram_xilinx_bank bank1(

                            .dout               (dout_bank1[31:0]),

                            .clk                (clk),
                            .rst                (rst),
                            .bank_select        (bank_select),
                            .we                 (we[3:0]),
                            .din                (din[31:0]),
                            .waddr              (waddr[12:0]),
                            .raddr              (raddr[12:0]));   
endmodule
module wb_ram_xilinx (

   dout,

   clk, rst, we, din, waddr, raddr
   ) ;


   
   input clk;
   input rst;   
   input [3:0] we;
   input [31:0] din;
   input [14:0] waddr;
   input [14:0] raddr;
   output wire [31:0] dout;

   initial begin
      $display("WB XILINX RAM");
      
   end
   
   wire bank_select = waddr[13] | raddr[13];
   
   wire [31:0] dout_bank0;
   wire [31:0] dout_bank1;

   assign dout = bank_select ? dout_bank1 : dout_bank0;
   
   
   wb_ram_xilinx_bank bank0(

                            .dout               (dout_bank0[31:0]),

                            .clk                (clk),
                            .rst                (rst),
                            .bank_select        (~bank_select),
                            .we                 (we[3:0]),
                            .din                (din[31:0]),
                            .waddr              (waddr[12:0]),
                            .raddr              (raddr[12:0]));
   

   wb_ram_xilinx_bank bank1(

                            .dout               (dout_bank1[31:0]),

                            .clk                (clk),
                            .rst                (rst),
                            .bank_select        (bank_select),
                            .we                 (we[3:0]),
                            .din                (din[31:0]),
                            .waddr              (waddr[12:0]),
                            .raddr              (raddr[12:0]));   
endmodule