data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_mem_write_fifo_wrapper.v
1: b"%Error: data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_mem_write_fifo_wrapper.v:157: Cannot find file containing module: 'nt_recv_capture_mem_write_fifo'\n  nt_recv_capture_mem_write_fifo nt_recv_capture_mem_write_fifo_inst (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl,data/full_repos/permissive/136197078/nt_recv_capture_mem_write_fifo\n             data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl,data/full_repos/permissive/136197078/nt_recv_capture_mem_write_fifo.v\n             data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl,data/full_repos/permissive/136197078/nt_recv_capture_mem_write_fifo.sv\n             nt_recv_capture_mem_write_fifo\n             nt_recv_capture_mem_write_fifo.v\n             nt_recv_capture_mem_write_fifo.sv\n             obj_dir/nt_recv_capture_mem_write_fifo\n             obj_dir/nt_recv_capture_mem_write_fifo.v\n             obj_dir/nt_recv_capture_mem_write_fifo.sv\n%Error: Exiting due to 1 error(s)\n"
module nt_recv_capture_mem_write_fifo_wrapper
(

  input wire          clk,
  input wire          rstn,
  input wire          rst_sw,


  input wire [63:0]   din_i,
  input wire          wr_en_i,
  output wire         full_o,


  output wire [511:0] dout_o,
  input wire          rd_en_i,
  output wire         empty_o,
  output wire         prog_empty_o,
  output wire [10:0]  rd_data_count_o,


  input wire align_i,
  output wire align_done_o
);


  localparam  RST           = 2'b00,
              PASS_THROUGH  = 2'b01,
              ALIGN         = 2'b10;

  reg [1:0] state, nxt_state;


  reg [2:0] fifo_wr_word_cntr, nxt_fifo_wr_word_cntr;


  reg align_done, nxt_align_done;
  assign align_done_o = align_done;


  wire [63:0] fifo_din;



  assign fifo_din = state == PASS_THROUGH ? din_i : 64'hFFFFFFFFFFFFFFFF;




  wire fifo_wr_en;
  assign fifo_wr_en = state == PASS_THROUGH ? wr_en_i :
    (state == ALIGN) & (fifo_wr_word_cntr != 0);


  always @(posedge clk) begin
    if (~rstn | rst_sw) begin
      state <= RST;
    end else begin
      state <= nxt_state;
    end

    fifo_wr_word_cntr <= nxt_fifo_wr_word_cntr;
    align_done <= nxt_align_done;
  end


  always @(*) begin

    nxt_state = state;
    nxt_fifo_wr_word_cntr = fifo_wr_word_cntr;
    nxt_align_done = 1'b0;

    case (state)

      RST: begin


        nxt_state = PASS_THROUGH;
        nxt_fifo_wr_word_cntr = 3'b0;
      end

      PASS_THROUGH: begin

        if (align_i) begin

          nxt_state = ALIGN;
        end

        if (wr_en_i) begin


          nxt_fifo_wr_word_cntr
            = (fifo_wr_word_cntr == 7) ? 3'b0 : fifo_wr_word_cntr + 3'b1;
        end
      end

      ALIGN: begin

        if (fifo_wr_word_cntr == 0) begin

          nxt_state = PASS_THROUGH;
          nxt_align_done = 1'b1;
        end else begin


          nxt_fifo_wr_word_cntr
            = (fifo_wr_word_cntr == 7) ? 3'b0 : fifo_wr_word_cntr + 3'b1;
        end
      end

    endcase
  end


  nt_recv_capture_mem_write_fifo nt_recv_capture_mem_write_fifo_inst (
    .clk(clk),
    .srst(~rstn | rst_sw),
    .din(fifo_din),
    .wr_en(fifo_wr_en),
    .rd_en(rd_en_i),
    .dout(dout_o),
    .full(full_o),
    .empty(empty_o),
    .rd_data_count(rd_data_count_o),
    .prog_empty(prog_empty_o)
  );

endmodule
module nt_recv_capture_mem_write_fifo_wrapper
(

  input wire          clk,
  input wire          rstn,
  input wire          rst_sw,


  input wire [63:0]   din_i,
  input wire          wr_en_i,
  output wire         full_o,


  output wire [511:0] dout_o,
  input wire          rd_en_i,
  output wire         empty_o,
  output wire         prog_empty_o,
  output wire [10:0]  rd_data_count_o,


  input wire align_i,
  output wire align_done_o
);



  localparam  RST           = 2'b00,
              PASS_THROUGH  = 2'b01,
              ALIGN         = 2'b10;

  reg [1:0] state, nxt_state;


  reg [2:0] fifo_wr_word_cntr, nxt_fifo_wr_word_cntr;


  reg align_done, nxt_align_done;
  assign align_done_o = align_done;


  wire [63:0] fifo_din;



  assign fifo_din = state == PASS_THROUGH ? din_i : 64'hFFFFFFFFFFFFFFFF;




  wire fifo_wr_en;
  assign fifo_wr_en = state == PASS_THROUGH ? wr_en_i :
    (state == ALIGN) & (fifo_wr_word_cntr != 0);


  always @(posedge clk) begin
    if (~rstn | rst_sw) begin
      state <= RST;
    end else begin
      state <= nxt_state;
    end

    fifo_wr_word_cntr <= nxt_fifo_wr_word_cntr;
    align_done <= nxt_align_done;
  end


  always @(*) begin

    nxt_state = state;
    nxt_fifo_wr_word_cntr = fifo_wr_word_cntr;
    nxt_align_done = 1'b0;

    case (state)

      RST: begin


        nxt_state = PASS_THROUGH;
        nxt_fifo_wr_word_cntr = 3'b0;
      end

      PASS_THROUGH: begin

        if (align_i) begin

          nxt_state = ALIGN;
        end

        if (wr_en_i) begin


          nxt_fifo_wr_word_cntr
            = (fifo_wr_word_cntr == 7) ? 3'b0 : fifo_wr_word_cntr + 3'b1;
        end
      end

      ALIGN: begin

        if (fifo_wr_word_cntr == 0) begin

          nxt_state = PASS_THROUGH;
          nxt_align_done = 1'b1;
        end else begin


          nxt_fifo_wr_word_cntr
            = (fifo_wr_word_cntr == 7) ? 3'b0 : fifo_wr_word_cntr + 3'b1;
        end
      end

    endcase
  end


  nt_recv_capture_mem_write_fifo nt_recv_capture_mem_write_fifo_inst (
    .clk(clk),
    .srst(~rstn | rst_sw),
    .din(fifo_din),
    .wr_en(fifo_wr_en),
    .rd_en(rd_en_i),
    .dout(dout_o),
    .full(full_o),
    .empty(empty_o),
    .rd_data_count(rd_data_count_o),
    .prog_empty(prog_empty_o)
  );

endmodule