data/full_repos/permissive/157608247/src/alu/div_tb.v
 line:34: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/157608247/src/alu/div_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #0 begin\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157608247/src/alu/div_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #20 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/src/alu/div_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk <= ~clk;\n           ^\n%Error: data/full_repos/permissive/157608247/src/alu/div_tb.v:20: Cannot find file containing module: \'div\'\n    div div0(.clk(clk),\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/157608247/src/alu,data/full_repos/permissive/157608247/div\n             data/full_repos/permissive/157608247/src/alu,data/full_repos/permissive/157608247/div.v\n             data/full_repos/permissive/157608247/src/alu,data/full_repos/permissive/157608247/div.sv\n             div\n             div.v\n             div.sv\n             obj_dir/div\n             obj_dir/div.v\n             obj_dir/div.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module div_tb;
    
    reg clk;
    reg rst;

    reg signed_div_i;
        

	reg[23:0] opdata1_i;
	reg[23:0] opdata2_i;
	reg start_i;
	reg annul_i;


    wire [23:0]		quotient_o;
	wire [23:0]		remainder_o;
    wire ready_o;

   
    div div0(.clk(clk),
            .rst(rst),
            .signed_div_i(signed_div_i),
            .opdata1_i(opdata1_i),
            .opdata2_i(opdata2_i),
            .start_i(start_i),
            .annul_i(annul_i),
            .remainder_o(remainder_o),
            .quotient_o(quotient_o),
            .ready_o(ready_o));

    
    
    initial begin
        #0 begin
            clk <= 1'b0;
            rst <= 1'b1;
            signed_div_i <= 1'b0;
            opdata1_i <= 24'd704;
            opdata2_i <= 24'd36;
            start_i <= 1'b1;
            annul_i <= 1'b0;
        end
        #20 begin
            rst <= 1'b0;
        end
    end


    always #5 clk <= ~clk;
    

endmodule
module div_tb;

    
    reg clk;
    reg rst;

    reg signed_div_i;
        

	reg[23:0] opdata1_i;
	reg[23:0] opdata2_i;
	reg start_i;
	reg annul_i;


    wire [23:0]		quotient_o;
	wire [23:0]		remainder_o;
    wire ready_o;

   
    div div0(.clk(clk),
            .rst(rst),
            .signed_div_i(signed_div_i),
            .opdata1_i(opdata1_i),
            .opdata2_i(opdata2_i),
            .start_i(start_i),
            .annul_i(annul_i),
            .remainder_o(remainder_o),
            .quotient_o(quotient_o),
            .ready_o(ready_o));

    
    
    initial begin
        #0 begin
            clk <= 1'b0;
            rst <= 1'b1;
            signed_div_i <= 1'b0;
            opdata1_i <= 24'd704;
            opdata2_i <= 24'd36;
            start_i <= 1'b1;
            annul_i <= 1'b0;
        end
        #20 begin
            rst <= 1'b0;
        end
    end


    always #5 clk <= ~clk;
    

endmodule