data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/d_ff.v
data/verilator_xmls/863e13b5-df3b-41bf-8227-4e42bfe4bf44.xml
module d_ff (q,clk,reset,out);

input [4:0] q;
input clk;
input reset;
output reg [4:0] out;

always@ (posedge clk)
begin
if(~reset)
    begin
        out<= 5'b00000;
    end
else
    begin
        out <= q;
    end
end

endmodule
module d_ff (q,clk,reset,out);


input [4:0] q;
input clk;
input reset;
output reg [4:0] out;

always@ (posedge clk)
begin
if(~reset)
    begin
        out<= 5'b00000;
    end
else
    begin
        out <= q;
    end
end

endmodule