data/full_repos/permissive/14432793/rfid-verilog/reader/rfid_reader_packet_rxtx.v
 line:221 column:42: Illegal character "'"
1: b'%Error: data/full_repos/permissive/14432793/rfid-verilog/reader/rfid_reader_packet_rxtx.v:102: Cannot find file containing module: \'rfid_reader_tx\'\nrfid_reader_tx U_TX (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14432793/rfid-verilog/reader,data/full_repos/permissive/14432793/rfid_reader_tx\n             data/full_repos/permissive/14432793/rfid-verilog/reader,data/full_repos/permissive/14432793/rfid_reader_tx.v\n             data/full_repos/permissive/14432793/rfid-verilog/reader,data/full_repos/permissive/14432793/rfid_reader_tx.sv\n             rfid_reader_tx\n             rfid_reader_tx.v\n             rfid_reader_tx.sv\n             obj_dir/rfid_reader_tx\n             obj_dir/rfid_reader_tx.v\n             obj_dir/rfid_reader_tx.sv\n%Error: data/full_repos/permissive/14432793/rfid-verilog/reader/rfid_reader_packet_rxtx.v:113: Cannot find file containing module: \'rfid_reader_rx\'\nrfid_reader_rx U_RX (\n^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/14432793/rfid-verilog/reader/rfid_reader_packet_rxtx.v:236: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 14 bits.\n                                                                                                     : ... In instance rfid_reader_packet_rxtx\n              tx_packet_data[17:5]   <= {divide_ratio,miller,trext,select,session,target,slot_q};\n                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/14432793/rfid-verilog/reader/rfid_reader_packet_rxtx.v:267: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                                     : ... In instance rfid_reader_packet_rxtx\n              tx_packet_data[15:0]  <= 15\'d0;  \n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/14432793/rfid-verilog/reader/rfid_reader_packet_rxtx.v:278: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                                     : ... In instance rfid_reader_packet_rxtx\n              tx_packet_data[15:0]  <= 15\'d0;   \n                                    ^~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module endianflip16(flipin, flipout);
  input  [15:0] flipin;
  output [15:0] flipout;
  assign flipout[15] = flipin[0];
  assign flipout[14] = flipin[1];
  assign flipout[13] = flipin[2];
  assign flipout[12] = flipin[3];
  assign flipout[11] = flipin[4];
  assign flipout[10] = flipin[5];
  assign flipout[9] = flipin[6];
  assign flipout[8] = flipin[7];
  assign flipout[7] = flipin[8];
  assign flipout[6] = flipin[9];
  assign flipout[5] = flipin[10];
  assign flipout[4] = flipin[11];
  assign flipout[3] = flipin[12];
  assign flipout[2] = flipin[13];
  assign flipout[1] = flipin[14];
  assign flipout[0] = flipin[15];
endmodule
module endianflip16(flipin, flipout);

  input  [15:0] flipin;
  output [15:0] flipout;
  assign flipout[15] = flipin[0];
  assign flipout[14] = flipin[1];
  assign flipout[13] = flipin[2];
  assign flipout[12] = flipin[3];
  assign flipout[11] = flipin[4];
  assign flipout[10] = flipin[5];
  assign flipout[9] = flipin[6];
  assign flipout[8] = flipin[7];
  assign flipout[7] = flipin[8];
  assign flipout[6] = flipin[9];
  assign flipout[5] = flipin[10];
  assign flipout[4] = flipin[11];
  assign flipout[3] = flipin[12];
  assign flipout[2] = flipin[13];
  assign flipout[1] = flipin[14];
  assign flipout[0] = flipin[15];
endmodule