data/full_repos/permissive/143278/ivltests/pr1474318.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1474318.v:8: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a !== 6\'bzzzz10) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1474318.v:4: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 6 bits.\n                                                                        : ... In instance test\n   assign     a[1:0] = {{2\'b0},b};\n                     ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
   wire [5:0] a;
   reg [3:0]  b;
   assign     a[1:0] = {{2'b0},b};

   initial begin
      b = 4'b0110;
      #1 if (a !== 6'bzzzz10) begin
	 $display("FAILED -- a=%b", a);
	 $finish;
      end
      $display("PASSED");
   end

endmodule
module test;

   wire [5:0] a;
   reg [3:0]  b;
   assign     a[1:0] = {{2'b0},b};

   initial begin
      b = 4'b0110;
      #1 if (a !== 6'bzzzz10) begin
	 $display("FAILED -- a=%b", a);
	 $finish;
      end
      $display("PASSED");
   end

endmodule