data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #3000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #2000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #2000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #2000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #2000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #3000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #2000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #3000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #2000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #3000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2) phi2 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2);\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:35: Little bit endian vector: MSB < LSB of bit range: 1:3\n    wire [1:3] delay;\n         ^\n%Error: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/ss_core_tb.v:37: Cannot find file containing module: \'ss_core\'\n    ss_core uut(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/134057391/cpld/m6502_db/testbench,data/full_repos/permissive/134057391/ss_core\n             data/full_repos/permissive/134057391/cpld/m6502_db/testbench,data/full_repos/permissive/134057391/ss_core.v\n             data/full_repos/permissive/134057391/cpld/m6502_db/testbench,data/full_repos/permissive/134057391/ss_core.sv\n             ss_core\n             ss_core.v\n             ss_core.sv\n             obj_dir/ss_core\n             obj_dir/ss_core.v\n             obj_dir/ss_core.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ss_core_tb;

    parameter PERIOD = 1000;

    reg phi2;
    reg sync;
    reg rd;
    reg ss;
    reg si_n;
    reg sc;

    wire rdy_cycle, rdy_inst;
    wire wc_clk;
    wire wc;
    wire [1:3] delay;

    ss_core uut(
        .phi2(phi2),
        .sync(sync),
        .rd(rd),
        .ss(ss),
        .si_n(si_n),
        .rdy_inst(rdy_inst),
        .rdy_cycle(rdy_cycle),
        .wcycle_clk(wc_clk),
        .wcycle(wc),
        .delay(delay)
    );
    
    initial begin

        rd = 1;
        sc = 1;
        ss = 0;
        si_n = 1;
        sync = 0;


        #1000;


        sc = 0;
        ss = 1;
        #3000;
        sc = 1;
        ss = 0;
        #2000;


        sc = 0;
        ss = 1;
        #1000;
        sync = 1;
        #2000;
        sc = 1;
        ss = 0;
        #2000;


        si_n = 0;
        ss = 1;
        #1000;
        sync = 0;

        #2000;
        sync = 1;
        #1000;
        si_n = 1;
        ss = 0;
        #3000;






        sc = 0;
        ss = 1;
        #1000;
        sync = 0;
        #2000;
        sc = 1;
        ss = 0;
        #3000;

        sc = 0;
        ss = 1;
        #1000;
        rd = 0;
        #2000;
        sc = 1;
        ss = 0;
        #3000;


        sc = 0;
        ss = 1;
        #1000;

    end

    always begin
        phi2 = 1'b0;
        #(PERIOD/2) phi2 = 1'b1;
        #(PERIOD/2);
    end  
     
endmodule
module ss_core_tb;


    parameter PERIOD = 1000;

    reg phi2;
    reg sync;
    reg rd;
    reg ss;
    reg si_n;
    reg sc;

    wire rdy_cycle, rdy_inst;
    wire wc_clk;
    wire wc;
    wire [1:3] delay;

    ss_core uut(
        .phi2(phi2),
        .sync(sync),
        .rd(rd),
        .ss(ss),
        .si_n(si_n),
        .rdy_inst(rdy_inst),
        .rdy_cycle(rdy_cycle),
        .wcycle_clk(wc_clk),
        .wcycle(wc),
        .delay(delay)
    );
    
    initial begin

        rd = 1;
        sc = 1;
        ss = 0;
        si_n = 1;
        sync = 0;


        #1000;


        sc = 0;
        ss = 1;
        #3000;
        sc = 1;
        ss = 0;
        #2000;


        sc = 0;
        ss = 1;
        #1000;
        sync = 1;
        #2000;
        sc = 1;
        ss = 0;
        #2000;


        si_n = 0;
        ss = 1;
        #1000;
        sync = 0;

        #2000;
        sync = 1;
        #1000;
        si_n = 1;
        ss = 0;
        #3000;






        sc = 0;
        ss = 1;
        #1000;
        sync = 0;
        #2000;
        sc = 1;
        ss = 0;
        #3000;

        sc = 0;
        ss = 1;
        #1000;
        rd = 0;
        #2000;
        sc = 1;
        ss = 0;
        #3000;


        sc = 0;
        ss = 1;
        #1000;

    end

    always begin
        phi2 = 1'b0;
        #(PERIOD/2) phi2 = 1'b1;
        #(PERIOD/2);
    end  
     
endmodule