data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim/frame_source_tb.v
1: b"%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim/frame_source_tb.v:29: Cannot find file containing module: 'clock_gen'\n  clock_gen clkgen(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim,data/full_repos/permissive/181738725/clock_gen\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim,data/full_repos/permissive/181738725/clock_gen.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim,data/full_repos/permissive/181738725/clock_gen.sv\n             clock_gen\n             clock_gen.v\n             clock_gen.sv\n             obj_dir/clock_gen\n             obj_dir/clock_gen.v\n             obj_dir/clock_gen.sv\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim/frame_source_tb.v:38: Cannot find file containing module: 'frame_source'\n  frame_source #(\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim/frame_source_tb.v:63: Cannot find file containing module: 'rate_ctrl'\n  rate_ctrl #(\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim/frame_source_tb.v:79: Cannot find file containing module: 'insert_errors'\n  insert_errors\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim/frame_source_tb.v:106: Cannot find file containing module: 'frame_sink'\n  frame_sink\n  ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module frame_source_tb;




  wire clk, rst;
  clock_gen clkgen(
    .clk (clk),
    .rst (rst));




  wire src_valid, src_ready, src_eof;
  wire [7:0] src_data;
  frame_source #(
    .GoDefault(1))
  src(
    .clk        (clk),
    .rst        (rst),

    .cfg_paddr  (5'b0),
    .cfg_pwrite (1'b0),
    .cfg_pwdata (32'b0),
    .cfg_psel   (1'b0),
    .cfg_penable(1'b0),
    .cfg_pready (),
    .cfg_prdata (),
    .cfg_pslverr(),
    .cfg_irq    (),

    .dout_ready (src_ready),
    .dout_valid (src_valid),
    .dout_eof   (src_eof),
    .dout_data  (src_data));




  wire       rate_valid, rate_ready, rate_active;
  rate_ctrl #(
    .THROUGHPUT (50))
  rate(
    .clk    (clk),
    .rst    (rst),
    .active (rate_active),
    .ack    (src_valid & src_ready));

  assign rate_valid = (rate_active) ? src_valid  : 1'b0;
  assign src_ready  = (rate_active) ? rate_ready : 1'b0;




  wire       ins_valid, ins_ready, ins_eof;
  wire [7:0] ins_data;
  insert_errors
  ins_err(
    .clk        (clk),
    .rst        (rst),

    .cfg_paddr  (5'b0),
    .cfg_pwrite (1'b0),
    .cfg_pwdata (32'b0),
    .cfg_psel   (1'b0),
    .cfg_penable(1'b0),
    .cfg_pready (),
    .cfg_prdata (),
    .cfg_pslverr(),

    .din_ready  (rate_ready),
    .din_valid  (rate_valid),
    .din_eof    (src_eof),
    .din_data   (src_data),

    .dout_ready (ins_ready),
    .dout_valid (ins_valid),
    .dout_eof   (ins_eof),
    .dout_data  (ins_data));




  frame_sink
  snk(
    .clk        (clk),
    .rst        (rst),

    .cfg_paddr  (5'b0),
    .cfg_pwrite (1'b0),
    .cfg_pwdata (32'b0),
    .cfg_psel   (1'b0),
    .cfg_penable(1'b0),
    .cfg_pready (),
    .cfg_prdata (),
    .cfg_pslverr(),
    .cfg_irq    (),

    .din_ready  (ins_ready),
    .din_valid  (ins_valid),
    .din_eof    (ins_eof),
    .din_data   (ins_data));

endmodule
module frame_source_tb;





  wire clk, rst;
  clock_gen clkgen(
    .clk (clk),
    .rst (rst));




  wire src_valid, src_ready, src_eof;
  wire [7:0] src_data;
  frame_source #(
    .GoDefault(1))
  src(
    .clk        (clk),
    .rst        (rst),

    .cfg_paddr  (5'b0),
    .cfg_pwrite (1'b0),
    .cfg_pwdata (32'b0),
    .cfg_psel   (1'b0),
    .cfg_penable(1'b0),
    .cfg_pready (),
    .cfg_prdata (),
    .cfg_pslverr(),
    .cfg_irq    (),

    .dout_ready (src_ready),
    .dout_valid (src_valid),
    .dout_eof   (src_eof),
    .dout_data  (src_data));




  wire       rate_valid, rate_ready, rate_active;
  rate_ctrl #(
    .THROUGHPUT (50))
  rate(
    .clk    (clk),
    .rst    (rst),
    .active (rate_active),
    .ack    (src_valid & src_ready));

  assign rate_valid = (rate_active) ? src_valid  : 1'b0;
  assign src_ready  = (rate_active) ? rate_ready : 1'b0;




  wire       ins_valid, ins_ready, ins_eof;
  wire [7:0] ins_data;
  insert_errors
  ins_err(
    .clk        (clk),
    .rst        (rst),

    .cfg_paddr  (5'b0),
    .cfg_pwrite (1'b0),
    .cfg_pwdata (32'b0),
    .cfg_psel   (1'b0),
    .cfg_penable(1'b0),
    .cfg_pready (),
    .cfg_prdata (),
    .cfg_pslverr(),

    .din_ready  (rate_ready),
    .din_valid  (rate_valid),
    .din_eof    (src_eof),
    .din_data   (src_data),

    .dout_ready (ins_ready),
    .dout_valid (ins_valid),
    .dout_eof   (ins_eof),
    .dout_data  (ins_data));




  frame_sink
  snk(
    .clk        (clk),
    .rst        (rst),

    .cfg_paddr  (5'b0),
    .cfg_pwrite (1'b0),
    .cfg_pwdata (32'b0),
    .cfg_psel   (1'b0),
    .cfg_penable(1'b0),
    .cfg_pready (),
    .cfg_prdata (),
    .cfg_pslverr(),
    .cfg_irq    (),

    .din_ready  (ins_ready),
    .din_valid  (ins_valid),
    .din_eof    (ins_eof),
    .din_data   (ins_data));

endmodule