data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161049548/project_1.srcs/sources_1/new,data/full_repos/permissive/161049548/defines.v\n             data/full_repos/permissive/161049548/project_1.srcs/sources_1/new,data/full_repos/permissive/161049548/defines.v.v\n             data/full_repos/permissive/161049548/project_1.srcs/sources_1/new,data/full_repos/permissive/161049548/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:27: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] pc,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] pc,\n                    ^\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:28: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] raw_inst,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:29: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] alu_rs,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:30: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] imm,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:34: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] branch_target\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:37: Define or directive not defined: \'`DATA_BUS\'\n    wire [`DATA_BUS] pc4 = pc + 4;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`DATA_BUS] pc4 = pc + 4;\n                   ^\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:41: Define or directive not defined: \'`JUMP\'\n        if (jump == `JUMP)  \n                    ^~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:42: Define or directive not defined: \'`RAW_INST_ADDR_BUS\'\n            branch_target = { pc4[DATA_WIDTH-1:28], raw_inst[`RAW_INST_ADDR_BUS], 2\'b00 };\n                                                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:43: Define or directive not defined: \'`JUMP_REG\'\n        else if (jump == `JUMP_REG)  \n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pc_targeter.v:45: Define or directive not defined: \'`JUMP_COND\'\n        else if (jump == `JUMP_COND)  \n                         ^~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module pc_targeter#(
    parameter DATA_WIDTH = 32
)(
    input [`DATA_BUS] pc,
    input [`DATA_BUS] raw_inst,
    input [`DATA_BUS] alu_rs,
    input [`DATA_BUS] imm,
    
    input [1:0] jump,
        
    output reg [`DATA_BUS] branch_target
    );

    wire [`DATA_BUS] pc4 = pc + 4;

    always @*
    begin
        if (jump == `JUMP)
            branch_target = { pc4[DATA_WIDTH-1:28], raw_inst[`RAW_INST_ADDR_BUS], 2'b00 };
        else if (jump == `JUMP_REG)
            branch_target = alu_rs;
        else if (jump == `JUMP_COND)
            branch_target = pc4 + {imm[DATA_WIDTH-3:0], 2'b00};
        else
            branch_target = 0;
    end
endmodule
module pc_targeter#(
    parameter DATA_WIDTH = 32
)(
    input [`DATA_BUS] pc,
    input [`DATA_BUS] raw_inst,
    input [`DATA_BUS] alu_rs,
    input [`DATA_BUS] imm,
    
    input [1:0] jump,
        
    output reg [`DATA_BUS] branch_target
    );


    wire [`DATA_BUS] pc4 = pc + 4;

    always @*
    begin
        if (jump == `JUMP)
            branch_target = { pc4[DATA_WIDTH-1:28], raw_inst[`RAW_INST_ADDR_BUS], 2'b00 };
        else if (jump == `JUMP_REG)
            branch_target = alu_rs;
        else if (jump == `JUMP_COND)
            branch_target = pc4 + {imm[DATA_WIDTH-3:0], 2'b00};
        else
            branch_target = 0;
    end
endmodule