data/full_repos/permissive/157101210/regfile.t.v
1: b'%Error: data/full_repos/permissive/157101210/regfile.t.v:6: Cannot find include file: regfile.v\n`include "regfile.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/regfile.v\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/regfile.v.v\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/regfile.v.sv\n             regfile.v\n             regfile.v.v\n             regfile.v.sv\n             obj_dir/regfile.v\n             obj_dir/regfile.v.v\n             obj_dir/regfile.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:177: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:177: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:217: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Error: Exiting due to 1 error(s), 21 warning(s)\n'
module hw4testbench
(

input	   		begintest,
output reg 		endtest,
output reg 		dutpassed,


input[31:0]		ReadData1,
input[31:0]		ReadData2,
output reg[31:0]	WriteData,
output reg[4:0]		ReadRegister1,
output reg[4:0]		ReadRegister2,
output reg[4:0]		WriteRegister,
output reg		RegWrite,
output reg		Clk
);


  initial begin
    WriteData=32'd0;
    ReadRegister1=5'd0;
    ReadRegister2=5'd0;
    WriteRegister=5'd0;
    RegWrite=0;
    Clk=1;
  end


  always @(negedge begintest) begin
    endtest = 0;
    dutpassed = 1;
    #10



  WriteRegister = 5'd2;
  WriteData = 32'd42;
  RegWrite = 1;
  ReadRegister1 = 5'd2;
  ReadRegister2 = 5'd2;
  #5 Clk=0; #5 Clk=1;


  if((ReadData1 !== 42) || (ReadData2 !== 42)) begin
    dutpassed = 0;
    $display("Regfile Test Case 1 Failed: Didn't write value and read back - %d %d", ReadData1, ReadData2);
  end



  WriteRegister = 5'd2;
  WriteData = 32'd15;
  RegWrite = 1;
  ReadRegister1 = 5'd2;
  ReadRegister2 = 5'd2;
  #5 Clk=0; #5 Clk=1;

  if((ReadData1 !== 15) || (ReadData2 !== 15)) begin
    dutpassed = 0;
    $display("Regfile Test Case 2 Failed: Didn't write value and read back");
  end





  WriteRegister = 5'd12;
  WriteData = 32'd42;
  RegWrite = 1;
  ReadRegister1 = 5'd12;
  ReadRegister2 = 5'd12;
  #5 Clk=0; #5 Clk=1;
  RegWrite = 0;
  WriteData = 32'd12;
  #5 Clk=0; #5 Clk=1;

  if((ReadData1 !== 42) || (ReadData2 !== 42)) begin
    dutpassed = 0;
    $display("Regfile Test Case 3 Failed: Low RegWrite didn't disable write");
  end







  WriteRegister = 5'd12;
  WriteData = 32'd42;
  RegWrite=1;
  ReadRegister1 = 5'd12;
  ReadRegister2 = 5'd11;
  #5 Clk=0; #5 Clk=1;
  WriteData = 32'd40;
  WriteRegister = 5'd11;
  #5 Clk=0; #5 Clk=1;

  if((ReadData1 !== 42) || (ReadData2 !== 40)) begin
    dutpassed = 0;
    $display("Regfile Test Case 4 Failed: Separate registers not written to and read from.");
  end




  WriteRegister = 5'd0;
  WriteData = 32'd42;
  RegWrite=1;
  ReadRegister1 = 5'd0;
  ReadRegister2 = 5'd0;
  #5 Clk=0; #5 Clk=1;

  if((ReadData1 !== 0) || (ReadData2 !== 0)) begin
    dutpassed = 0;
    $display("Regfile Test Case 5 Failed: Zero register not always 0.");
  end





  WriteRegister = 5'd12;
  WriteData = 32'd42;
  RegWrite=1;
  ReadRegister1 = 5'd12;
  ReadRegister2 = 5'd12;
  #5 Clk=0; #5 Clk=1;

  if((ReadData1 !== 42) || (ReadData2 !== 42)) begin
    dutpassed = 0;
    $display("Regfile Test Case 6 Failed: Didn't write value and read back.");
  end

  ReadRegister1 = 5'd0;
  ReadRegister2 = 5'd0;
  #5;

  if((ReadData1 !== 0) || (ReadData2 !== 0)) begin
    dutpassed = 0;
    $display("Regfile Test Case 6 Failed: Register has to clock to update outputs.");
  end

  #5
  endtest = 1;

end

endmodule
module hw4testbench
(

input	   		begintest,
output reg 		endtest,
output reg 		dutpassed,


input[31:0]		ReadData1,
input[31:0]		ReadData2,
output reg[31:0]	WriteData,
output reg[4:0]		ReadRegister1,
output reg[4:0]		ReadRegister2,
output reg[4:0]		WriteRegister,
output reg		RegWrite,
output reg		Clk
);



  initial begin
    WriteData=32'd0;
    ReadRegister1=5'd0;
    ReadRegister2=5'd0;
    WriteRegister=5'd0;
    RegWrite=0;
    Clk=1;
  end


  always @(negedge begintest) begin
    endtest = 0;
    dutpassed = 1;
    #10



  WriteRegister = 5'd2;
  WriteData = 32'd42;
  RegWrite = 1;
  ReadRegister1 = 5'd2;
  ReadRegister2 = 5'd2;
  #5 Clk=0; #5 Clk=1;


  if((ReadData1 !== 42) || (ReadData2 !== 42)) begin
    dutpassed = 0;
    $display("Regfile Test Case 1 Failed: Didn't write value and read back - %d %d", ReadData1, ReadData2);
  end



  WriteRegister = 5'd2;
  WriteData = 32'd15;
  RegWrite = 1;
  ReadRegister1 = 5'd2;
  ReadRegister2 = 5'd2;
  #5 Clk=0; #5 Clk=1;

  if((ReadData1 !== 15) || (ReadData2 !== 15)) begin
    dutpassed = 0;
    $display("Regfile Test Case 2 Failed: Didn't write value and read back");
  end





  WriteRegister = 5'd12;
  WriteData = 32'd42;
  RegWrite = 1;
  ReadRegister1 = 5'd12;
  ReadRegister2 = 5'd12;
  #5 Clk=0; #5 Clk=1;
  RegWrite = 0;
  WriteData = 32'd12;
  #5 Clk=0; #5 Clk=1;

  if((ReadData1 !== 42) || (ReadData2 !== 42)) begin
    dutpassed = 0;
    $display("Regfile Test Case 3 Failed: Low RegWrite didn't disable write");
  end







  WriteRegister = 5'd12;
  WriteData = 32'd42;
  RegWrite=1;
  ReadRegister1 = 5'd12;
  ReadRegister2 = 5'd11;
  #5 Clk=0; #5 Clk=1;
  WriteData = 32'd40;
  WriteRegister = 5'd11;
  #5 Clk=0; #5 Clk=1;

  if((ReadData1 !== 42) || (ReadData2 !== 40)) begin
    dutpassed = 0;
    $display("Regfile Test Case 4 Failed: Separate registers not written to and read from.");
  end




  WriteRegister = 5'd0;
  WriteData = 32'd42;
  RegWrite=1;
  ReadRegister1 = 5'd0;
  ReadRegister2 = 5'd0;
  #5 Clk=0; #5 Clk=1;

  if((ReadData1 !== 0) || (ReadData2 !== 0)) begin
    dutpassed = 0;
    $display("Regfile Test Case 5 Failed: Zero register not always 0.");
  end





  WriteRegister = 5'd12;
  WriteData = 32'd42;
  RegWrite=1;
  ReadRegister1 = 5'd12;
  ReadRegister2 = 5'd12;
  #5 Clk=0; #5 Clk=1;

  if((ReadData1 !== 42) || (ReadData2 !== 42)) begin
    dutpassed = 0;
    $display("Regfile Test Case 6 Failed: Didn't write value and read back.");
  end

  ReadRegister1 = 5'd0;
  ReadRegister2 = 5'd0;
  #5;

  if((ReadData1 !== 0) || (ReadData2 !== 0)) begin
    dutpassed = 0;
    $display("Regfile Test Case 6 Failed: Register has to clock to update outputs.");
  end

  #5
  endtest = 1;

end

endmodule