data/full_repos/permissive/17877624/src/hardware/audio_codec.sv
data/verilator_xmls/7bcf3672-4a0a-4bb7-9850-0838cbfbf366.xml
module audio_codec (
    input  clk,
    input  reset,
    output [1:0]  sample_end,
    output [1:0]  sample_req,
    input  [15:0] audio_output,
    input  [1:0] channel_sel,
    output AUD_ADCLRCK,
    input AUD_ADCDAT,
    output AUD_DACLRCK,
    output AUD_DACDAT,  
    output AUD_BCLK
);


reg [7:0] lrck_divider;


reg [1:0] bclk_divider;

reg [15:0] shift_out;
reg [15:0] shift_temp;

wire lrck = !lrck_divider[7];


assign AUD_ADCLRCK = lrck;
assign AUD_DACLRCK = lrck;
assign AUD_BCLK = bclk_divider[1];


assign AUD_DACDAT = shift_out[15];


always @(posedge clk) begin
    if (reset) begin
        lrck_divider <= 8'hff;
        bclk_divider <= 2'b11;
    end else begin
        lrck_divider <= lrck_divider + 1'b1;
        bclk_divider <= bclk_divider + 1'b1;
    end
end


assign sample_end[1] = (lrck_divider == 8'h40);

assign sample_end[0] = (lrck_divider == 8'hc0);


assign sample_req[1] = (lrck_divider == 8'hfe);

assign sample_req[0] = (lrck_divider == 8'h7e);

wire clr_lrck = (lrck_divider == 8'h7f);
wire set_lrck = (lrck_divider == 8'hff);

wire set_bclk = (bclk_divider == 2'b10 && !lrck_divider[6]);

wire clr_bclk = (bclk_divider == 2'b11 && !lrck_divider[6]);


always @(posedge clk) begin
    if (reset) begin
        shift_out <= 16'h0;
        shift_temp <= 16'h0;
  	 end
	 else if (set_lrck) begin
            shift_out <= audio_output;
            shift_temp <= audio_output;
    end
	 else if (clr_lrck) begin
			shift_out <= shift_temp;
    end else if (clr_bclk == 1) begin
        shift_out <= {shift_out[14:0], 1'b0};
    end
end

endmodule
module audio_codec (
    input  clk,
    input  reset,
    output [1:0]  sample_end,
    output [1:0]  sample_req,
    input  [15:0] audio_output,
    input  [1:0] channel_sel,
    output AUD_ADCLRCK,
    input AUD_ADCDAT,
    output AUD_DACLRCK,
    output AUD_DACDAT,  
    output AUD_BCLK
);



reg [7:0] lrck_divider;


reg [1:0] bclk_divider;

reg [15:0] shift_out;
reg [15:0] shift_temp;

wire lrck = !lrck_divider[7];


assign AUD_ADCLRCK = lrck;
assign AUD_DACLRCK = lrck;
assign AUD_BCLK = bclk_divider[1];


assign AUD_DACDAT = shift_out[15];


always @(posedge clk) begin
    if (reset) begin
        lrck_divider <= 8'hff;
        bclk_divider <= 2'b11;
    end else begin
        lrck_divider <= lrck_divider + 1'b1;
        bclk_divider <= bclk_divider + 1'b1;
    end
end


assign sample_end[1] = (lrck_divider == 8'h40);

assign sample_end[0] = (lrck_divider == 8'hc0);


assign sample_req[1] = (lrck_divider == 8'hfe);

assign sample_req[0] = (lrck_divider == 8'h7e);

wire clr_lrck = (lrck_divider == 8'h7f);
wire set_lrck = (lrck_divider == 8'hff);

wire set_bclk = (bclk_divider == 2'b10 && !lrck_divider[6]);

wire clr_bclk = (bclk_divider == 2'b11 && !lrck_divider[6]);


always @(posedge clk) begin
    if (reset) begin
        shift_out <= 16'h0;
        shift_temp <= 16'h0;
  	 end
	 else if (set_lrck) begin
            shift_out <= audio_output;
            shift_temp <= audio_output;
    end
	 else if (clr_lrck) begin
			shift_out <= shift_temp;
    end else if (clr_bclk == 1) begin
        shift_out <= {shift_out[14:0], 1'b0};
    end
end

endmodule