data/full_repos/permissive/125742950/WavetableRAM.v
data/verilator_xmls/6cbcac0e-4d89-4b88-a0e0-c7a3adc7de7f.xml
module MemoryBank(CLK, WE, Address, DataIn, Index, DataOut);
    input CLK;
    input WE;
    input[5:0] Address;
    input[5:0] DataIn;
    input[5:0] Index;
    output[5:0] DataOut;
    
    reg[5:0] RAM[0:63];
    
    always @ (posedge CLK) begin
        if(WE) begin
            RAM[Address] <= DataIn;
        end 
    end
    
    assign DataOut = RAM[Index];
endmodule
module MemoryBank(CLK, WE, Address, DataIn, Index, DataOut);

    input CLK;
    input WE;
    input[5:0] Address;
    input[5:0] DataIn;
    input[5:0] Index;
    output[5:0] DataOut;
    
    reg[5:0] RAM[0:63];
    
    always @ (posedge CLK) begin
        if(WE) begin
            RAM[Address] <= DataIn;
        end 
    end
    
    assign DataOut = RAM[Index];
endmodule