data/full_repos/permissive/144785545/alu.v
data/verilator_xmls/7c6c9c77-f3ec-4f6d-a111-1cef8663258c.xml
module ALU(
		input CLK,
		input [3:0]	REGDATA,
		input [3:0] IMMDATA,
		output reg [3:0] OUT
);

always @( posedge CLK ) begin
		OUT <= REGDATA + IMMDATA;
end

endmodule
module ALU(
		input CLK,
		input [3:0]	REGDATA,
		input [3:0] IMMDATA,
		output reg [3:0] OUT
);


always @( posedge CLK ) begin
		OUT <= REGDATA + IMMDATA;
end

endmodule