data/full_repos/permissive/143278/ivltests/vams_abs2.v
 line:26: before: "real"
1: b'%Error: data/full_repos/permissive/143278/ivltests/vams_abs2.v:26: syntax error, unexpected real, expecting IDENTIFIER or \'=\' or do or final\n   reg       real  b;\n             ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vams_abs2.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (vala !== 0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vams_abs2.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (valb != 0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vams_abs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (vala !== 1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vams_abs2.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (valb != 1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vams_abs2.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (vala !== 1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vams_abs2.v:61: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (valb != 1) begin\n      ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module main;

   reg signed [7:0]  a;
   wire signed [7:0] vala = abs(a);

   reg	      real  b;
   wire       real  valb = abs(b);

   initial begin
      a = 0;
      b = 0;
      #1 if (vala !== 0) begin
	 $display("FAILED -- a=%b, vala=%b", a, vala);
	 $finish;
      end

      #1 if (valb != 0) begin
	 $display("FAILED -- b=%g valb=%g", b, valb);
	 $finish;
      end

      a = 1;
      b = 1;
      #1 if (vala !== 1) begin
	 $display("FAILED -- a=%b, vala=%b", a, vala);
	 $finish;
      end

      #1 if (valb != 1) begin
	 $display("FAILED -- b=%g valb=%g", b, valb);
	 $finish;
      end

      a = -1;
      b = -1;
      #1 if (vala !== 1) begin
	 $display("FAILED -- a=%b, vala=%b", a, vala);
	 $finish;
      end

      #1 if (valb != 1) begin
	 $display("FAILED -- b=%g valb=%g", b, valb);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg signed [7:0]  a;
   wire signed [7:0] vala = abs(a);

   reg	      real  b;
   wire       real  valb = abs(b);

   initial begin
      a = 0;
      b = 0;
      #1 if (vala !== 0) begin
	 $display("FAILED -- a=%b, vala=%b", a, vala);
	 $finish;
      end

      #1 if (valb != 0) begin
	 $display("FAILED -- b=%g valb=%g", b, valb);
	 $finish;
      end

      a = 1;
      b = 1;
      #1 if (vala !== 1) begin
	 $display("FAILED -- a=%b, vala=%b", a, vala);
	 $finish;
      end

      #1 if (valb != 1) begin
	 $display("FAILED -- b=%g valb=%g", b, valb);
	 $finish;
      end

      a = -1;
      b = -1;
      #1 if (vala !== 1) begin
	 $display("FAILED -- a=%b, vala=%b", a, vala);
	 $finish;
      end

      #1 if (valb != 1) begin
	 $display("FAILED -- b=%g valb=%g", b, valb);
	 $finish;
      end

      $display("PASSED");
   end

endmodule