data/full_repos/permissive/156417892/hdl/Execute/Execute_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/Execute_test.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/Execute_test.v:51: Unsupported: Ignoring delay on this delayed statement.\n #25 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/156417892/hdl/Execute/Execute_test.v:56: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("./main_test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/156417892/hdl/Execute/Execute_test.v:57: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;


   reg iSig_RegDst;
   reg [1:0] iSig_ALUOp;
   reg iSig_ALUSrc;
   reg [31:0] iadder_branch_result;
   reg [31:0] iregfile_read_1, iregfile_read_2;
   reg [31:0] iimm;
   reg [4:0] iins2016, iins1511;

   wire [31:0] o_adder_branch_result;
   wire oALU_zero;
   wire [31:0] oALU_result, oregfile_read_2;
   wire [4:0] oreg_write_reg;


   integer    i;


   Execute uut(
         iSig_RegDst,
         iSig_ALUOp,
         iSig_ALUSrc,
         iadder_branch_result,
         iregfile_read_1,
         iregfile_read_2,
         iimm,
         iins2016,
         iins1511,
         o_adder_branch_result,
         oALU_zero,
         oALU_result,
         oregfile_read_2,
         oreg_write_reg
         );

   initial begin

      resetn = 0;
      #10;


   end

   initial begin
      clk = 0;
      for (i = 0; i < 2000; i = i + 1)
	#25 clk = ~clk;
   end


   initial begin
      $dumpfile("./main_test.vcd");
      $dumpvars;
   end

endmodule
module main_test;



   reg iSig_RegDst;
   reg [1:0] iSig_ALUOp;
   reg iSig_ALUSrc;
   reg [31:0] iadder_branch_result;
   reg [31:0] iregfile_read_1, iregfile_read_2;
   reg [31:0] iimm;
   reg [4:0] iins2016, iins1511;

   wire [31:0] o_adder_branch_result;
   wire oALU_zero;
   wire [31:0] oALU_result, oregfile_read_2;
   wire [4:0] oreg_write_reg;


   integer    i;


   Execute uut(
         iSig_RegDst,
         iSig_ALUOp,
         iSig_ALUSrc,
         iadder_branch_result,
         iregfile_read_1,
         iregfile_read_2,
         iimm,
         iins2016,
         iins1511,
         o_adder_branch_result,
         oALU_zero,
         oALU_result,
         oregfile_read_2,
         oreg_write_reg
         );

   initial begin

      resetn = 0;
      #10;


   end

   initial begin
      clk = 0;
      for (i = 0; i < 2000; i = i + 1)
	#25 clk = ~clk;
   end


   initial begin
      $dumpfile("./main_test.vcd");
      $dumpvars;
   end

endmodule