data/full_repos/permissive/158606829/sys/ip/avalon_combiner.v
data/verilator_xmls/7b4e3b53-c35f-4229-bdca-2d9dad853270.xml
module avalon_combiner
(
	input  wire        clk,
	input  wire        rst,

	output wire [6:0]  mixer_address,
	output wire [3:0]  mixer_byteenable,
	output wire        mixer_write,
	output wire [31:0] mixer_writedata,
	input  wire        mixer_waitrequest,

	output wire [6:0]  scaler_address,
	output wire [3:0]  scaler_byteenable,
	input  wire        scaler_waitrequest,
	output wire        scaler_write,
	output wire [31:0] scaler_writedata,

	output wire [7:0]  video_address,
	output wire [3:0]  video_byteenable,
	input  wire        video_waitrequest,
	output wire        video_write,
	output wire [31:0] video_writedata,

	output wire        clock,
	output wire        reset,
	input  wire [8:0]  address,
	input  wire        write,
	input  wire [31:0] writedata,
	output wire        waitrequest
);

assign clock = clk;
assign reset = rst;

assign mixer_address  = address[6:0];
assign scaler_address = address[6:0];
assign video_address  = address[7:0];

assign mixer_byteenable  = 4'b1111;
assign scaler_byteenable = 4'b1111;
assign video_byteenable  = 4'b1111;

wire   en_scaler = (address[8:7] == 0);
wire   en_mixer  = (address[8:7] == 1);
wire   en_video  =  address[8];

assign mixer_write  = en_mixer  & write;
assign scaler_write = en_scaler & write;
assign video_write  = en_video  & write;

assign mixer_writedata  = writedata;
assign scaler_writedata = writedata;
assign video_writedata  = writedata;

assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest);

endmodule
module avalon_combiner
(
	input  wire        clk,
	input  wire        rst,

	output wire [6:0]  mixer_address,
	output wire [3:0]  mixer_byteenable,
	output wire        mixer_write,
	output wire [31:0] mixer_writedata,
	input  wire        mixer_waitrequest,

	output wire [6:0]  scaler_address,
	output wire [3:0]  scaler_byteenable,
	input  wire        scaler_waitrequest,
	output wire        scaler_write,
	output wire [31:0] scaler_writedata,

	output wire [7:0]  video_address,
	output wire [3:0]  video_byteenable,
	input  wire        video_waitrequest,
	output wire        video_write,
	output wire [31:0] video_writedata,

	output wire        clock,
	output wire        reset,
	input  wire [8:0]  address,
	input  wire        write,
	input  wire [31:0] writedata,
	output wire        waitrequest
);


assign clock = clk;
assign reset = rst;

assign mixer_address  = address[6:0];
assign scaler_address = address[6:0];
assign video_address  = address[7:0];

assign mixer_byteenable  = 4'b1111;
assign scaler_byteenable = 4'b1111;
assign video_byteenable  = 4'b1111;

wire   en_scaler = (address[8:7] == 0);
wire   en_mixer  = (address[8:7] == 1);
wire   en_video  =  address[8];

assign mixer_write  = en_mixer  & write;
assign scaler_write = en_scaler & write;
assign video_write  = en_video  & write;

assign mixer_writedata  = writedata;
assign scaler_writedata = writedata;
assign video_writedata  = writedata;

assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest);

endmodule