data/full_repos/permissive/143278/ivltests/pr2036953.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2036953.v:13: Operator OR expects 3 bits on the LHS, but LHS\'s ARRAYSEL generates 2 bits.\n                                                                         : ... In instance test\n width1_2 = width1[0] | width2[0];\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2036953.v:13: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s OR generates 3 bits.\n                                                                         : ... In instance test\n width1_2 = width1[0] | width2[0];\n          ^\n%Error: Exiting due to 2 warning(s)\n'
module test;

reg [1:0] width1[1:0];
reg [2:0] width2[1:0];

reg [1:0] width1_2;

initial
begin
	width1[0] = 1;
	width2[0] = 2;

	width1_2 = width1[0] | width2[0];

	if(width1_2 !== 3)
		$display("FAILED");
	else
		$display("PASSED");
end

endmodule
module test;


reg [1:0] width1[1:0];
reg [2:0] width2[1:0];

reg [1:0] width1_2;

initial
begin
	width1[0] = 1;
	width2[0] = 2;

	width1_2 = width1[0] | width2[0];

	if(width1_2 !== 3)
		$display("FAILED");
	else
		$display("PASSED");
end

endmodule