data/full_repos/permissive/16142629/rtl/v1_3_1/zet_fulladd16.v
1: b'%Warning-WIDTH: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_fulladd16.v:30: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'ci\' generates 1 bits.\n                                                                                 : ... In instance zet_fulladd16\n  assign {co,z} = {1\'b0, x} + {s, y} + ci;\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module zet_fulladd16 (
    input  [15:0] x,
    input  [15:0] y,
    input         ci,
    output        co,
    output [15:0] z,
    input         s
  );


  assign {co,z} = {1'b0, x} + {s, y} + ci;
endmodule
module zet_fulladd16 (
    input  [15:0] x,
    input  [15:0] y,
    input         ci,
    output        co,
    output [15:0] z,
    input         s
  );



  assign {co,z} = {1'b0, x} + {s, y} + ci;
endmodule