data/full_repos/permissive/212020337/control_input_module.v
1: b"%Error: data/full_repos/permissive/212020337/control_input_module.v:36: Cannot find file containing module: 'debouncing_module'\n    debouncing_module C0(signal_floor_1, bt_floor_1, clk);\n    ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212020337,data/full_repos/permissive/212020337/debouncing_module\n             data/full_repos/permissive/212020337,data/full_repos/permissive/212020337/debouncing_module.v\n             data/full_repos/permissive/212020337,data/full_repos/permissive/212020337/debouncing_module.sv\n             debouncing_module\n             debouncing_module.v\n             debouncing_module.sv\n             obj_dir/debouncing_module\n             obj_dir/debouncing_module.v\n             obj_dir/debouncing_module.sv\n%Error: data/full_repos/permissive/212020337/control_input_module.v:37: Cannot find file containing module: 'debouncing_module'\n    debouncing_module C1(signal_floor_2, bt_floor_2, clk);\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/212020337/control_input_module.v:38: Cannot find file containing module: 'debouncing_module'\n    debouncing_module C2(signal_floor_3, bt_floor_3, clk);\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/212020337/control_input_module.v:39: Cannot find file containing module: 'debouncing_module'\n    debouncing_module C3(signal_floor_4, bt_floor_4, clk);\n    ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module control_input_unit(
    output reg [3:0] memory_address_buffer,
    output reg [3:0] ctrl_load,
    input      [3:0] ctrl_seq,
    input            bt_floor_1,
    input            bt_floor_2,
    input            bt_floor_3,
    input            bt_floor_4,
    input            clk
    );


    reg  [3:0] ctrl_seq_register;


    wire [3:0] ctrl_seq_temp;
    wire       signal_floor_1;
    wire       signal_floor_2;
    wire       signal_floor_3;
    wire       signal_floor_4;


    debouncing_module C0(signal_floor_1, bt_floor_1, clk);
    debouncing_module C1(signal_floor_2, bt_floor_2, clk);
    debouncing_module C2(signal_floor_3, bt_floor_3, clk);
    debouncing_module C3(signal_floor_4, bt_floor_4, clk);


    assign ctrl_seq_temp =
   {
        signal_floor_4,
        signal_floor_3,
        signal_floor_2,
        signal_floor_1
    };


    always @(*) begin
        case (ctrl_seq_temp)
            4'h1:    ctrl_seq_register = ctrl_seq_temp;
            4'h2:    ctrl_seq_register = ctrl_seq_temp;
            4'h4:    ctrl_seq_register = ctrl_seq_temp;
            4'h8:    ctrl_seq_register = ctrl_seq_temp;
            default: ctrl_seq_register = 4'h0;
        endcase
    end


    always @(posedge clk)
    begin
        memory_address_buffer = ctrl_seq_register;
        if (ctrl_seq == 0)
            ctrl_load = ctrl_seq_register;
        else
            ctrl_load = ctrl_seq;
    end
endmodule
module control_input_unit(
    output reg [3:0] memory_address_buffer,
    output reg [3:0] ctrl_load,
    input      [3:0] ctrl_seq,
    input            bt_floor_1,
    input            bt_floor_2,
    input            bt_floor_3,
    input            bt_floor_4,
    input            clk
    );



    reg  [3:0] ctrl_seq_register;


    wire [3:0] ctrl_seq_temp;
    wire       signal_floor_1;
    wire       signal_floor_2;
    wire       signal_floor_3;
    wire       signal_floor_4;


    debouncing_module C0(signal_floor_1, bt_floor_1, clk);
    debouncing_module C1(signal_floor_2, bt_floor_2, clk);
    debouncing_module C2(signal_floor_3, bt_floor_3, clk);
    debouncing_module C3(signal_floor_4, bt_floor_4, clk);


    assign ctrl_seq_temp =
   {
        signal_floor_4,
        signal_floor_3,
        signal_floor_2,
        signal_floor_1
    };


    always @(*) begin
        case (ctrl_seq_temp)
            4'h1:    ctrl_seq_register = ctrl_seq_temp;
            4'h2:    ctrl_seq_register = ctrl_seq_temp;
            4'h4:    ctrl_seq_register = ctrl_seq_temp;
            4'h8:    ctrl_seq_register = ctrl_seq_temp;
            default: ctrl_seq_register = 4'h0;
        endcase
    end


    always @(posedge clk)
    begin
        memory_address_buffer = ctrl_seq_register;
        if (ctrl_seq == 0)
            ctrl_load = ctrl_seq_register;
        else
            ctrl_load = ctrl_seq;
    end
endmodule