data/full_repos/permissive/125742950/NoiseGenerator.v
data/verilator_xmls/cd190de3-144b-4fc6-9193-22e58073ab70.xml
module NoiseGenerator(CLK, RST, Output);
    input CLK, RST;
    output reg[5:0] Output;
    
    reg[15:0] ShiftRegister;
    wire Feedback = ShiftRegister[0] ^ ShiftRegister[3];
    
    always @ (posedge CLK or negedge RST) begin
        if(!RST) begin
            Output <= 6'd0;
            ShiftRegister <= 16'hF00F;
        end else begin
            ShiftRegister <= {Feedback, ShiftRegister[15:1]};
            Output <= (ShiftRegister[0] ? 6'd63 : 6'd0);
        end
    end
endmodule
module NoiseGenerator(CLK, RST, Output);

    input CLK, RST;
    output reg[5:0] Output;
    
    reg[15:0] ShiftRegister;
    wire Feedback = ShiftRegister[0] ^ ShiftRegister[3];
    
    always @ (posedge CLK or negedge RST) begin
        if(!RST) begin
            Output <= 6'd0;
            ShiftRegister <= 16'hF00F;
        end else begin
            ShiftRegister <= {Feedback, ShiftRegister[15:1]};
            Output <= (ShiftRegister[0] ? 6'd63 : 6'd0);
        end
    end
endmodule