data/full_repos/permissive/108561032/pc.v
data/verilator_xmls/d5e4cbe2-7199-4b84-b0c5-cc25c707994e.xml
module pc(
    input  SaltoCond,
	input Saltoincond,
	input [31:0] extSigno, 
	input oZero,
    input clk,
    input reset,
	input [31:0]instru,
	input [31:0] sum2sumin,
	output [31:0] sum2sumout,
    output reg [31:0] direinstru,
	output  [31:0] salSum2out,
	input [31:0] salSum2in
    );
    
    
	wire [31:0] sum2sum;
    wire [31:0] salSum2;
	wire FuentePC;
	wire [31:0] sal2PC;
	wire [31:0] mux2mux;
	wire oZeroD;
	


    
    

  
    assign salSum2out =  extSigno + sum2sumin;
    assign sum2sumout = direinstru +1;

    assign sal2PC = mux2mux;
    assign FuentePC = SaltoCond & oZeroD;
	assign mux2mux = FuentePC ? salSum2in : sum2sumout;



    /



   
    always @(negedge reset )
    begin
        direinstru = 32'b0000_0000_0000_0000_0000_0000_0000_0000;

                    
    end
    
 assign oZeroD = oZero ? 1'b1 :  1'b0;   
    always @(posedge clk)
        begin
        




                    

           if (reset==1)
              direinstru = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
                
           else

                    direinstru = sal2PC;
       
                


    


        end
            
    endmodule
module pc(
    input  SaltoCond,
	input Saltoincond,
	input [31:0] extSigno, 
	input oZero,
    input clk,
    input reset,
	input [31:0]instru,
	input [31:0] sum2sumin,
	output [31:0] sum2sumout,
    output reg [31:0] direinstru,
	output  [31:0] salSum2out,
	input [31:0] salSum2in
    );

    
    
	wire [31:0] sum2sum;
    wire [31:0] salSum2;
	wire FuentePC;
	wire [31:0] sal2PC;
	wire [31:0] mux2mux;
	wire oZeroD;
	


    
    

  
    assign salSum2out =  extSigno + sum2sumin;
    assign sum2sumout = direinstru +1;

    assign sal2PC = mux2mux;
    assign FuentePC = SaltoCond & oZeroD;
	assign mux2mux = FuentePC ? salSum2in : sum2sumout;



    /



   
    always @(negedge reset )
    begin
        direinstru = 32'b0000_0000_0000_0000_0000_0000_0000_0000;

                    
    end
    
 assign oZeroD = oZero ? 1'b1 :  1'b0;   
    always @(posedge clk)
        begin
        




                    

           if (reset==1)
              direinstru = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
                
           else

                    direinstru = sal2PC;
       
                


    


        end
            
    endmodule