data/full_repos/permissive/166008742/src/ctrl_logic.v
1: b'%Error: data/full_repos/permissive/166008742/src/ctrl_logic.v:43: Cannot find include file: globals.vh\n    `include "globals.vh" \n             ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh.v\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh.sv\n             globals.vh\n             globals.vh.v\n             globals.vh.sv\n             obj_dir/globals.vh\n             obj_dir/globals.vh.v\n             obj_dir/globals.vh.sv\n%Error: data/full_repos/permissive/166008742/src/ctrl_logic.v:152: Define or directive not defined: \'`BUF_MANAGER_BASE_ADDR\'\n    assign wbm_address   = `BUF_MANAGER_BASE_ADDR;\n                           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/166008742/src/ctrl_logic.v:152: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    assign wbm_address   = `BUF_MANAGER_BASE_ADDR;\n                                                 ^\n%Error: Exiting due to 3 error(s)\n'
module ctrl_logic #(parameter ADDR_WIDTH = 32, parameter DATA_WIDTH = 32)
(
    input                   reset,
    input                   clk,


    output [ADDR_WIDTH-1:0] wbm_address,
    output [DATA_WIDTH-1:0] wbm_writedata,
    input  [DATA_WIDTH-1:0] wbm_readdata,
    output                  wbm_strobe,
    output                  wbm_cycle,
    output                  wbm_write,
    input                   wbm_ack,
    

    output [DATA_WIDTH-1:0] update_buf_id,
    output                  update_buf,
    input                   buf_updated,


    output [DATA_WIDTH-1:0] image_buf_id,
    output                  display_image,
    input                   display_image_done
);

    `include "globals.vh"

    localparam LED_SEND_DLY  = 10000000; 
    localparam INIT_DLY      = 100; 

    localparam ST_IDLE       = 0;
    localparam ST_INIT       = 1;
    localparam ST_ALLOC_B1   = 2;
    localparam ST_UPD_B1     = 3;

    localparam ST_ALLOC_B2   = 4;
    localparam ST_DISP1_UPD2 = 5;
    localparam ST_DELAY      = 6;
    localparam ST_RELEASE_B1 = 7;
    localparam ST_LD_B1_B2   = 8;


    reg [3:0] state, next_state;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= ST_IDLE;
        end
        else begin
            state <= next_state;
        end
    end


    always @(*) begin
        next_state = state;
        case (state)
            ST_IDLE: begin
                next_state = ST_INIT;
            end
            ST_INIT: begin
                if (delay_done) begin
                    next_state = ST_ALLOC_B1;
                end
            end
            ST_ALLOC_B1: begin
                if (wbm_ack) begin
                    next_state = ST_UPD_B1;
                end
            end
            ST_UPD_B1: begin
                if (buf_updated) begin
                    next_state = ST_ALLOC_B2;
                end
            end
            ST_ALLOC_B2: begin
                if (wbm_ack) begin
                    next_state = ST_DISP1_UPD2;
                end
            end
            ST_DISP1_UPD2: begin
                if (display_image_done) begin
                    next_state = ST_DELAY;
                end
            end
            ST_DELAY: begin
                if (delay_done) begin
                    next_state = ST_RELEASE_B1;
                end
            end
            ST_RELEASE_B1: begin
                if (wbm_ack) begin
                    next_state = ST_LD_B1_B2;
                end
            end
            ST_LD_B1_B2: begin
                next_state = ST_ALLOC_B2;
            end
            default: begin
                next_state = ST_IDLE;
            end
        endcase
    end


    reg [DATA_WIDTH-1:0] buf_id_1;
    reg [DATA_WIDTH-1:0] buf_id_2;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            buf_id_1 <= 0;
            buf_id_2 <= 0;
        end
        else begin
            if (state == ST_ALLOC_B1 && wbm_ack) begin
                buf_id_1 <= wbm_readdata;
            end
            else if (state == ST_ALLOC_B2 && wbm_ack) begin
                buf_id_2 <= wbm_readdata;
            end
            else if (state == ST_LD_B1_B2) begin
                buf_id_1 <= buf_id_2;
            end
        end
    end

    assign update_buf    = (state == ST_UPD_B1) | (state == ST_DISP1_UPD2);
    assign update_buf_id = (state == ST_UPD_B1) ? buf_id_1 : buf_id_2;


    assign image_buf_id  = buf_id_1;
    assign display_image = (state == ST_DISP1_UPD2);


    assign wbm_address   = `BUF_MANAGER_BASE_ADDR;
    assign wbm_write     = (state == ST_RELEASE_B1);
    assign wbm_writedata = buf_id_1;
    assign wbm_cycle     = (state == ST_ALLOC_B1) | (state == ST_ALLOC_B2) | (state == ST_RELEASE_B1);
    assign wbm_strobe    = (state == ST_ALLOC_B1) | (state == ST_ALLOC_B2) | (state == ST_RELEASE_B1);
    


    reg [DATA_WIDTH-1:0] dly_timer;
    wire delay_done = ((state == ST_DELAY) & (dly_timer == LED_SEND_DLY)) |
                      ((state == ST_INIT)  & (dly_timer == INIT_DLY));

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            dly_timer <= 0;
        end
        else begin
            if ((state == ST_INIT) | (state == ST_DELAY)) begin
                dly_timer <= dly_timer + 1;
            end
            else begin
                dly_timer <= 0;
            end
        end
    end

endmodule
module ctrl_logic #(parameter ADDR_WIDTH = 32, parameter DATA_WIDTH = 32)
(
    input                   reset,
    input                   clk,


    output [ADDR_WIDTH-1:0] wbm_address,
    output [DATA_WIDTH-1:0] wbm_writedata,
    input  [DATA_WIDTH-1:0] wbm_readdata,
    output                  wbm_strobe,
    output                  wbm_cycle,
    output                  wbm_write,
    input                   wbm_ack,
    

    output [DATA_WIDTH-1:0] update_buf_id,
    output                  update_buf,
    input                   buf_updated,


    output [DATA_WIDTH-1:0] image_buf_id,
    output                  display_image,
    input                   display_image_done
);


    `include "globals.vh"

    localparam LED_SEND_DLY  = 10000000; 
    localparam INIT_DLY      = 100; 

    localparam ST_IDLE       = 0;
    localparam ST_INIT       = 1;
    localparam ST_ALLOC_B1   = 2;
    localparam ST_UPD_B1     = 3;

    localparam ST_ALLOC_B2   = 4;
    localparam ST_DISP1_UPD2 = 5;
    localparam ST_DELAY      = 6;
    localparam ST_RELEASE_B1 = 7;
    localparam ST_LD_B1_B2   = 8;


    reg [3:0] state, next_state;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            state <= ST_IDLE;
        end
        else begin
            state <= next_state;
        end
    end


    always @(*) begin
        next_state = state;
        case (state)
            ST_IDLE: begin
                next_state = ST_INIT;
            end
            ST_INIT: begin
                if (delay_done) begin
                    next_state = ST_ALLOC_B1;
                end
            end
            ST_ALLOC_B1: begin
                if (wbm_ack) begin
                    next_state = ST_UPD_B1;
                end
            end
            ST_UPD_B1: begin
                if (buf_updated) begin
                    next_state = ST_ALLOC_B2;
                end
            end
            ST_ALLOC_B2: begin
                if (wbm_ack) begin
                    next_state = ST_DISP1_UPD2;
                end
            end
            ST_DISP1_UPD2: begin
                if (display_image_done) begin
                    next_state = ST_DELAY;
                end
            end
            ST_DELAY: begin
                if (delay_done) begin
                    next_state = ST_RELEASE_B1;
                end
            end
            ST_RELEASE_B1: begin
                if (wbm_ack) begin
                    next_state = ST_LD_B1_B2;
                end
            end
            ST_LD_B1_B2: begin
                next_state = ST_ALLOC_B2;
            end
            default: begin
                next_state = ST_IDLE;
            end
        endcase
    end


    reg [DATA_WIDTH-1:0] buf_id_1;
    reg [DATA_WIDTH-1:0] buf_id_2;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            buf_id_1 <= 0;
            buf_id_2 <= 0;
        end
        else begin
            if (state == ST_ALLOC_B1 && wbm_ack) begin
                buf_id_1 <= wbm_readdata;
            end
            else if (state == ST_ALLOC_B2 && wbm_ack) begin
                buf_id_2 <= wbm_readdata;
            end
            else if (state == ST_LD_B1_B2) begin
                buf_id_1 <= buf_id_2;
            end
        end
    end

    assign update_buf    = (state == ST_UPD_B1) | (state == ST_DISP1_UPD2);
    assign update_buf_id = (state == ST_UPD_B1) ? buf_id_1 : buf_id_2;


    assign image_buf_id  = buf_id_1;
    assign display_image = (state == ST_DISP1_UPD2);


    assign wbm_address   = `BUF_MANAGER_BASE_ADDR;
    assign wbm_write     = (state == ST_RELEASE_B1);
    assign wbm_writedata = buf_id_1;
    assign wbm_cycle     = (state == ST_ALLOC_B1) | (state == ST_ALLOC_B2) | (state == ST_RELEASE_B1);
    assign wbm_strobe    = (state == ST_ALLOC_B1) | (state == ST_ALLOC_B2) | (state == ST_RELEASE_B1);
    


    reg [DATA_WIDTH-1:0] dly_timer;
    wire delay_done = ((state == ST_DELAY) & (dly_timer == LED_SEND_DLY)) |
                      ((state == ST_INIT)  & (dly_timer == INIT_DLY));

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            dly_timer <= 0;
        end
        else begin
            if ((state == ST_INIT) | (state == ST_DELAY)) begin
                dly_timer <= dly_timer + 1;
            end
            else begin
                dly_timer <= 0;
            end
        end
    end

endmodule