data/full_repos/permissive/114459345/srcOrigin/rom_ram.v
1: b'%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:7: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] addr,\n                        ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:13: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`InstBus] inst,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:13: Define or directive not defined: \'`InstBus\'\n output reg[`InstBus] inst,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire we,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`ValidBitBus] wvalid_bit,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:20: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] wvalid_bit,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:21: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] waddr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:22: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] data_i,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`ValidBitBus] rvalid_bit,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:26: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] rvalid_bit,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:27: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] raddr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:28: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus] data_o \n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:33: Define or directive not defined: \'`DataMemNum\'\n reg[7:0] data_mem[0:`DataMemNum-1];\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:35: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:44: Define or directive not defined: \'`ChipDisable\'\n  if(rom_ce == `ChipDisable)  begin\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:45: Define or directive not defined: \'`NopInst\'\n   inst <= `NopInst;\n           ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:46: Define or directive not defined: \'`Continue\'\n   stall_req <= `Continue;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:49: Define or directive not defined: \'`WriteEnable\'\n   if(we == `WriteEnable) begin  \n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:50: Define or directive not defined: \'`Stop\'\n    stall_req <= `Stop;\n                 ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:53: Define or directive not defined: \'`Continue\'\n    stall_req <= `Continue;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:61: Define or directive not defined: \'`ChipDisable\'\n  if(ram_ce == `ChipDisable) begin\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:64: Define or directive not defined: \'`WriteEnable\'\n  else if(we == `WriteEnable) begin  \n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:66: Define or directive not defined: \'`Byte\'\n    `Byte : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:69: Define or directive not defined: \'`Half\'\n    `Half : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:73: Define or directive not defined: \'`Word\'\n    `Word : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:89: Define or directive not defined: \'`ChipDisable\'\n  if(ram_ce == `ChipDisable) begin\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:90: Define or directive not defined: \'`ZeroWord\'\n   data_o <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:92: Define or directive not defined: \'`WriteEnable\'\n  else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:92: Define or directive not defined: \'`ReadEnable\'\n  else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:95: Define or directive not defined: \'`ReadEnable\'\n  else if(re == `ReadEnable) begin  \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:97: Define or directive not defined: \'`Byte\'\n    `Byte : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:100: Define or directive not defined: \'`Half\'\n    `Half : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:103: Define or directive not defined: \'`Word\'\n    `Word : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:109: Define or directive not defined: \'`ZeroWord\'\n   data_o <= `ZeroWord;\n             ^~~~~~~~~\n%Error: Exiting due to 36 error(s)\n'
module rom_ram(

	input wire rom_ce,
	input wire[`InstAddrBus] addr,
	

	output reg stall_req,
	

	output reg[`InstBus] inst,


	input wire ram_ce,
	

	input wire we,
	input wire[`ValidBitBus] wvalid_bit,
	input wire[`DataAddrBus] waddr,
	input wire[`DataBus] data_i,
	

	input wire re,
	input wire[`ValidBitBus] rvalid_bit,
	input wire[`DataAddrBus] raddr,
	output reg[`DataBus] data_o	
	


);
	reg[7:0] data_mem[0:`DataMemNum-1];

	initial begin




		$readmemh("D:\\Coding\\cpu-risc-v\\inst_test\\helloworld.s", data_mem);	
	end
	
	always @ (*) begin
		if(rom_ce == `ChipDisable)  begin
			inst <= `NopInst;
			stall_req <= `Continue;
		end
		else begin
			if(we == `WriteEnable) begin
				stall_req <= `Stop;
			end
			else begin
				stall_req <= `Continue;
				inst <= {data_mem[addr + 3], data_mem[addr + 2], data_mem[addr + 1], data_mem[addr]};
			end
		end
	end


	always @ (*) begin
		if(ram_ce == `ChipDisable) begin

		end
		else if(we == `WriteEnable) begin
			case(wvalid_bit)
				`Byte : begin
					data_mem[waddr] <= data_i[7:0];
				end
				`Half : begin
					data_mem[waddr] <= data_i[7:0];
					data_mem[waddr+1] <= data_i[15:8];
				end
				`Word : begin
					data_mem[waddr] <= data_i[7:0];
					data_mem[waddr+1] <= data_i[15:8];
					data_mem[waddr+2] <= data_i[23:16];
					data_mem[waddr+3] <= data_i[31:24];
				end
				default : begin

				end
			endcase
			$display("mem_wdata -> %c", data_i[7:0]);
		end
	end


	always @ (*) begin
		if(ram_ce == `ChipDisable) begin
			data_o <= `ZeroWord;
		end
		else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
			data_o <= data_i;
		end
		else if(re == `ReadEnable) begin
			case(rvalid_bit)
				`Byte : begin
					data_o <= {{24{1'b0}}, data_mem[raddr]};
				end
				`Half : begin
					data_o <= {{16{1'b0}}, data_mem[raddr+1],data_mem[raddr]};
				end
				`Word : begin
					data_o <= {data_mem[raddr+3],data_mem[raddr+2],data_mem[raddr+1],data_mem[raddr]};
				end
			endcase
		end
		else begin
			data_o <= `ZeroWord;
		end
	end	

endmodule
module rom_ram(

	input wire rom_ce,
	input wire[`InstAddrBus] addr,
	

	output reg stall_req,
	

	output reg[`InstBus] inst,


	input wire ram_ce,
	

	input wire we,
	input wire[`ValidBitBus] wvalid_bit,
	input wire[`DataAddrBus] waddr,
	input wire[`DataBus] data_i,
	

	input wire re,
	input wire[`ValidBitBus] rvalid_bit,
	input wire[`DataAddrBus] raddr,
	output reg[`DataBus] data_o	
	


);

	reg[7:0] data_mem[0:`DataMemNum-1];

	initial begin




		$readmemh("D:\\Coding\\cpu-risc-v\\inst_test\\helloworld.s", data_mem);	
	end
	
	always @ (*) begin
		if(rom_ce == `ChipDisable)  begin
			inst <= `NopInst;
			stall_req <= `Continue;
		end
		else begin
			if(we == `WriteEnable) begin
				stall_req <= `Stop;
			end
			else begin
				stall_req <= `Continue;
				inst <= {data_mem[addr + 3], data_mem[addr + 2], data_mem[addr + 1], data_mem[addr]};
			end
		end
	end


	always @ (*) begin
		if(ram_ce == `ChipDisable) begin

		end
		else if(we == `WriteEnable) begin
			case(wvalid_bit)
				`Byte : begin
					data_mem[waddr] <= data_i[7:0];
				end
				`Half : begin
					data_mem[waddr] <= data_i[7:0];
					data_mem[waddr+1] <= data_i[15:8];
				end
				`Word : begin
					data_mem[waddr] <= data_i[7:0];
					data_mem[waddr+1] <= data_i[15:8];
					data_mem[waddr+2] <= data_i[23:16];
					data_mem[waddr+3] <= data_i[31:24];
				end
				default : begin

				end
			endcase
			$display("mem_wdata -> %c", data_i[7:0]);
		end
	end


	always @ (*) begin
		if(ram_ce == `ChipDisable) begin
			data_o <= `ZeroWord;
		end
		else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
			data_o <= data_i;
		end
		else if(re == `ReadEnable) begin
			case(rvalid_bit)
				`Byte : begin
					data_o <= {{24{1'b0}}, data_mem[raddr]};
				end
				`Half : begin
					data_o <= {{16{1'b0}}, data_mem[raddr+1],data_mem[raddr]};
				end
				`Word : begin
					data_o <= {data_mem[raddr+3],data_mem[raddr+2],data_mem[raddr+1],data_mem[raddr]};
				end
			endcase
		end
		else begin
			data_o <= `ZeroWord;
		end
	end	

endmodule