data/full_repos/permissive/202237519/verilog/digitalsystem4/Mux.v
1: b'%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem4/Mux.v:9: Operator CASE expects 2 bits on the Case expression, but Case expression\'s VARREF \'Sel\' generates 1 bits.\n                                                                                   : ... In instance Mux\n    case (Sel)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Mux (In,Sel,Out);

input [1:0] In;
output reg Out;
input Sel;

always @(In,Sel)
begin
    case (Sel)
        2'b00: Out = In[0];
        2'b01: Out = In[1];
    endcase
end
endmodule
module Mux (In,Sel,Out);


input [1:0] In;
output reg Out;
input Sel;

always @(In,Sel)
begin
    case (Sel)
        2'b00: Out = In[0];
        2'b01: Out = In[1];
    endcase
end
endmodule