data/full_repos/permissive/169258653/components/ALU/ALU.srcs/sources_1/new/ALU.v
 line:28: before: "input"
1: b'%Warning-WIDTH: data/full_repos/permissive/169258653/components/ALU/ALU.srcs/sources_1/new/ALU.v:40: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s LT generates 1 bits.\n                                                                                                   : ... In instance ALU\n        3\'b111:result=a[31]==b[31]?a<b:a>b;\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169258653/components/ALU/ALU.srcs/sources_1/new/ALU.v:40: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s GT generates 1 bits.\n                                                                                                   : ... In instance ALU\n        3\'b111:result=a[31]==b[31]?a<b:a>b;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/169258653/components/ALU/ALU.srcs/sources_1/new/ALU.v:42: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'result\' generates 32 bits.\n                                                                                                   : ... In instance ALU\n        zero=!result;\n             ^\n%Error: Exiting due to 3 warning(s)\n'
module ALU(
    input [31:0] a,b,
    input [2:0] alucont,
    output reg [31:0] result,
    output reg zero
    );
    
    always@(*)
    begin
        case(alucont)
        3'b000:result=a&b;
        3'b001:result=a|b;
        3'b010:result=a+b;
        3'b011:result=result;
        3'b100:result=a&~b;
        3'b101:result=a|~b;
        3'b110:result=a-b;
        3'b111:result=a[31]==b[31]?a<b:a>b;
        endcase
        zero=!result;
    end
    
endmodule
module ALU(
    input [31:0] a,b,
    input [2:0] alucont,
    output reg [31:0] result,
    output reg zero
    );

    
    always@(*)
    begin
        case(alucont)
        3'b000:result=a&b;
        3'b001:result=a|b;
        3'b010:result=a+b;
        3'b011:result=result;
        3'b100:result=a&~b;
        3'b101:result=a|~b;
        3'b110:result=a-b;
        3'b111:result=a[31]==b[31]?a<b:a>b;
        endcase
        zero=!result;
    end
    
endmodule