data/full_repos/permissive/210737016/wam_dis.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/210737016/wam_dis.v:41: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'wam_led\'\nmodule wam_led (             \n       ^~~~~~~\n                                                                    : ... Top module \'wam_lst\'\nmodule wam_lst (             \n       ^~~~~~~\n                                                                    : ... Top module \'wam_dis\'\nmodule wam_dis(              \n       ^~~~~~~\n%Error: data/full_repos/permissive/210737016/wam_dis.v:54: Cannot find file containing module: \'wam_tch\'\n    wam_tch tchc( .clk_19(clk_19), .btn(cout0), .tch(cout0s));\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_tch\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_tch.v\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_tch.sv\n             wam_tch\n             wam_tch.v\n             wam_tch.sv\n             obj_dir/wam_tch\n             obj_dir/wam_tch.v\n             obj_dir/wam_tch.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module wam_obd(
    input wire [3:0] num,
    output reg [6:0] a2g
    );

    always @(*) begin
        case(num)
            'h0: a2g=7'b0000001;
            'h1: a2g=7'b1001111;
            'h2: a2g=7'b0010010;
            'h3: a2g=7'b0000110;
            'h4: a2g=7'b1001100;
            'h5: a2g=7'b0100100;
            'h6: a2g=7'b0100000;
            'h7: a2g=7'b0001111;
            'h8: a2g=7'b0000000;
            'h9: a2g=7'b0000100;
            'hA: a2g=7'b1001000;
            'hB: a2g=7'b0011100;
            'hC: a2g=7'b0110001;
            'hD: a2g=7'b1000010;
            'hE: a2g=7'b0110000;
            'hF: a2g=7'b1111111;
            default: a2g=7'b1111111;
        endcase
    end
endmodule
module wam_obd(
    input wire [3:0] num,
    output reg [6:0] a2g
    );


    always @(*) begin
        case(num)
            'h0: a2g=7'b0000001;
            'h1: a2g=7'b1001111;
            'h2: a2g=7'b0010010;
            'h3: a2g=7'b0000110;
            'h4: a2g=7'b1001100;
            'h5: a2g=7'b0100100;
            'h6: a2g=7'b0100000;
            'h7: a2g=7'b0001111;
            'h8: a2g=7'b0000000;
            'h9: a2g=7'b0000100;
            'hA: a2g=7'b1001000;
            'hB: a2g=7'b0011100;
            'hC: a2g=7'b0110001;
            'hD: a2g=7'b1000010;
            'hE: a2g=7'b0110000;
            'hF: a2g=7'b1111111;
            default: a2g=7'b1111111;
        endcase
    end
endmodule