data/full_repos/permissive/131831582/COUNTER/myCounter.v
data/verilator_xmls/fe6b2744-1c44-4967-8abb-9cc5bc208939.xml
module myCounter(clk, reset, out);
input wire clk, reset;
output [3:0] out;

reg [3:0] count = 0;

always @ (posedge clk)
begin
	if (reset) begin
		count <= 4'd0;
	end else begin
		count <= count + 4'd1;
	end
end
assign out = count;
endmodule
module myCounter(clk, reset, out);

input wire clk, reset;
output [3:0] out;

reg [3:0] count = 0;

always @ (posedge clk)
begin
	if (reset) begin
		count <= 4'd0;
	end else begin
		count <= count + 4'd1;
	end
end
assign out = count;
endmodule