data/full_repos/permissive/206783267/SPI/CNTLR/W25Q32JV_fastread.v
1: b"%Error: data/full_repos/permissive/206783267/SPI/CNTLR/W25Q32JV_fastread.v:23: Cannot find file containing module: 'spi_master'\nspi_master\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206783267/SPI/CNTLR,data/full_repos/permissive/206783267/spi_master\n             data/full_repos/permissive/206783267/SPI/CNTLR,data/full_repos/permissive/206783267/spi_master.v\n             data/full_repos/permissive/206783267/SPI/CNTLR,data/full_repos/permissive/206783267/spi_master.sv\n             spi_master\n             spi_master.v\n             spi_master.sv\n             obj_dir/spi_master\n             obj_dir/spi_master.v\n             obj_dir/spi_master.sv\n%Error: Exiting due to 1 error(s)\n"
module W25Q32JV_fastread(
	input	clk, arstn,
	input	fastread_start,
	input	[23:0]	addr,
	output	sclk, csn, mosi,
	input	miso,
	output	fastread_done,
	output	[7:0]	data_out_1, data_out_2
	);

wire	[8+24+8+16-1:0]	data_send, data_recv;
wire	spi_start, spi_done;

assign spi_start = fastread_start;
assign data_send = {8'h0b, addr, 8'h00, 8'h00, 8'h00};

assign fastread_done = spi_done;
assign data_out_1 = fastread_done ? data_recv[15:8] : 'd0;
assign data_out_2 = fastread_done ? data_recv[7:0] : 'd0;

spi_master
#(
	.CLK_FREQ(50_000_000),
	.SPI_FREQ(5_000_000),
	.DATA_WIDTH(8+24+8+16),
	.CPOL(0),
	.CPHA(0)
)
spi_ctrl(
	.clk(clk),
	.arstn(arstn),
	.data_send(data_send),
	.spi_start(spi_start),
	.sclk(sclk),
	.csn(csn),
	.mosi(mosi),
	.miso(miso),
	.spi_done(spi_done),
	.data_recv(data_recv)
);

endmodule
module W25Q32JV_fastread(
	input	clk, arstn,
	input	fastread_start,
	input	[23:0]	addr,
	output	sclk, csn, mosi,
	input	miso,
	output	fastread_done,
	output	[7:0]	data_out_1, data_out_2
	);


wire	[8+24+8+16-1:0]	data_send, data_recv;
wire	spi_start, spi_done;

assign spi_start = fastread_start;
assign data_send = {8'h0b, addr, 8'h00, 8'h00, 8'h00};

assign fastread_done = spi_done;
assign data_out_1 = fastread_done ? data_recv[15:8] : 'd0;
assign data_out_2 = fastread_done ? data_recv[7:0] : 'd0;

spi_master
#(
	.CLK_FREQ(50_000_000),
	.SPI_FREQ(5_000_000),
	.DATA_WIDTH(8+24+8+16),
	.CPOL(0),
	.CPHA(0)
)
spi_ctrl(
	.clk(clk),
	.arstn(arstn),
	.data_send(data_send),
	.spi_start(spi_start),
	.sclk(sclk),
	.csn(csn),
	.mosi(mosi),
	.miso(miso),
	.spi_done(spi_done),
	.data_recv(data_recv)
);

endmodule