data/full_repos/permissive/220330507/rtl/pmem_sim.v
 line:1: before: "WORD_WIDTH"
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/220330507/rtl/pmem_sim.v:34: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_word'\n                                                                          : ... In instance pmem_sim\n        out_word = mem_array[sampled_addr];\n        ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module pmem_sim #(WORD_WIDTH = 16, ADDR_WIDTH = 12, NUM_WORDS = 2048, PMEM_FILE="")
         (input                   clock,
		  input  [ADDR_WIDTH-1:0] in_addr,
		  output [WORD_WIDTH-1:0] out_word);


    localparam ADDR_LSB = ((WORD_WIDTH / 8)-1);
    
    reg [WORD_WIDTH-1:0]          mem_array [ NUM_WORDS-1 : 0 ];
    reg [ADDR_WIDTH-ADDR_LSB-1:0] sampled_addr;


    integer cfgFileHandle;
    reg  [256*8-1:0] memFileName;


    initial begin
        cfgFileHandle = $fopen(PMEM_FILE, "r");

        if (cfgFileHandle == 0) begin
           $display("ERROR: Could not open memory config file %s\n", PMEM_FILE);
           $finish;
        end

        $fscanf  (cfgFileHandle, "%s", memFileName);
        $readmemh(memFileName, mem_array);
    end

    always @(posedge clock) begin
        sampled_addr <= in_addr[ADDR_WIDTH-1:ADDR_LSB];
    end

    always @(sampled_addr) begin
        out_word = mem_array[sampled_addr];
    end 

endmodule
module pmem_sim #(WORD_WIDTH = 16, ADDR_WIDTH = 12, NUM_WORDS = 2048, PMEM_FILE="")
         (input                   clock,
		  input  [ADDR_WIDTH-1:0] in_addr,
		  output [WORD_WIDTH-1:0] out_word);



    localparam ADDR_LSB = ((WORD_WIDTH / 8)-1);
    
    reg [WORD_WIDTH-1:0]          mem_array [ NUM_WORDS-1 : 0 ];
    reg [ADDR_WIDTH-ADDR_LSB-1:0] sampled_addr;


    integer cfgFileHandle;
    reg  [256*8-1:0] memFileName;


    initial begin
        cfgFileHandle = $fopen(PMEM_FILE, "r");

        if (cfgFileHandle == 0) begin
           $display("ERROR: Could not open memory config file %s\n", PMEM_FILE);
           $finish;
        end

        $fscanf  (cfgFileHandle, "%s", memFileName);
        $readmemh(memFileName, mem_array);
    end

    always @(posedge clock) begin
        sampled_addr <= in_addr[ADDR_WIDTH-1:ADDR_LSB];
    end

    always @(sampled_addr) begin
        out_word = mem_array[sampled_addr];
    end 

endmodule