data/full_repos/permissive/125927162/SPI/SPI_SLAVE.v
data/verilator_xmls/d9a0299e-e5df-4164-8b0f-297742402346.xml
module SPI_SLAVE(
		 input 			 ss_n,
		 input 			 sclk,
		 input 			 mosi,
		 output 		 miso,
		 input [BITS - 1:0] 	 inData,
		 input 			 latch,
 		 output reg [BITS - 1:0] outData
		 );
   
   parameter BITS = 8;


   reg 			outBit;
   reg 			inBit;

   always @ (latch)
      outData <= inData;
      
   always @ (posedge sclk)
     if (!ss_n)
       inBit <= mosi;
   
   always @ (negedge sclk)
      if (!ss_n) begin
	 outBit <= outData[BITS - 1];
	 outData[BITS - 1: 1] <= outData[BITS - 2: 0];
	 outData[0] <= inBit;
      end
   
   assign miso = ss_n ? 1'bZ : outBit;
endmodule
module SPI_SLAVE(
		 input 			 ss_n,
		 input 			 sclk,
		 input 			 mosi,
		 output 		 miso,
		 input [BITS - 1:0] 	 inData,
		 input 			 latch,
 		 output reg [BITS - 1:0] outData
		 );

   
   parameter BITS = 8;


   reg 			outBit;
   reg 			inBit;

   always @ (latch)
      outData <= inData;
      
   always @ (posedge sclk)
     if (!ss_n)
       inBit <= mosi;
   
   always @ (negedge sclk)
      if (!ss_n) begin
	 outBit <= outData[BITS - 1];
	 outData[BITS - 1: 1] <= outData[BITS - 2: 0];
	 outData[0] <= inBit;
      end
   
   assign miso = ss_n ? 1'bZ : outBit;
endmodule