data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v:164: Bit extraction of var[5:0] requires 3 bit index, not 2 bits.\n                                                                                     : ... In instance Z80Reg.WSelectR\n    if(rstatus[{1\'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3\'b010};   \n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v:167: Bit extraction of var[5:0] requires 3 bit index, not 2 bits.\n                                                                                     : ... In instance Z80Reg.WSelectR\n    case({rstatus[5:4], rstatus[{1\'b1, rstatus[1]}]})\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v:106: Operator ADD expects 16 bits on the RHS, but RHS\'s LOGNOT generates 1 bits.\n                                                                                     : ... In instance Z80Reg\n wire [15:0]ADDR1 = ADDR + !ALU16OP[2];  \n                         ^\n%Error: Exiting due to 3 warning(s)\n'
module RegSelect(
	input [2:0]SEL,
	output reg [3:0]RAMSEL,
	input [5:0]rstatus
	);
	
	always @* begin
		RAMSEL = 4'bxxxx;
		case(SEL)
			0: RAMSEL = {rstatus[1], 3'b000};
			1:
				if(rstatus[{1'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3'b010};
				else RAMSEL = {rstatus[1], 3'b001};
			2:
				case({rstatus[5:4], rstatus[{1'b1, rstatus[1]}]})
					0,4: 	RAMSEL = {rstatus[1], 3'b010};
					1,5: 	RAMSEL = {rstatus[1], 3'b001};
					2,3:	RAMSEL = 4'b0101;
					6,7:	RAMSEL = 4'b0110;
				endcase
			3: RAMSEL = {rstatus[0], 3'b011};
			4:	RAMSEL = 4;
			5: RAMSEL = 12;
			6: RAMSEL = 13;
			7: RAMSEL = 7;
		endcase
	end
endmodule
module RegSelect(
	input [2:0]SEL,
	output reg [3:0]RAMSEL,
	input [5:0]rstatus
	);

	
	always @* begin
		RAMSEL = 4'bxxxx;
		case(SEL)
			0: RAMSEL = {rstatus[1], 3'b000};
			1:
				if(rstatus[{1'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3'b010};
				else RAMSEL = {rstatus[1], 3'b001};
			2:
				case({rstatus[5:4], rstatus[{1'b1, rstatus[1]}]})
					0,4: 	RAMSEL = {rstatus[1], 3'b010};
					1,5: 	RAMSEL = {rstatus[1], 3'b001};
					2,3:	RAMSEL = 4'b0101;
					6,7:	RAMSEL = 4'b0110;
				endcase
			3: RAMSEL = {rstatus[0], 3'b011};
			4:	RAMSEL = 4;
			5: RAMSEL = 12;
			6: RAMSEL = 13;
			7: RAMSEL = 7;
		endcase
	end
endmodule