data/full_repos/permissive/191834901/VerilogHDL/mainMemory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/191834901/VerilogHDL/mainMemory.v:20: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'instMemory\'\nmodule instMemory #(parameter instructionW=32, parameter addrW=16) (\n       ^~~~~~~~~~\n                                                                                  : ... Top module \'dataMemory\'\nmodule dataMemory #(parameter dataW=32, parameter addrW=16) (\n       ^~~~~~~~~~\n                                                                                  : ... Top module \'controlPathDriver\'\nmodule controlPathDriver #(parameter controlWordWidth=16, parameter caddrW=16) (\n       ^~~~~~~~~~~~~~~~~\n                                                                                  : ... Top module \'registerFile\'\nmodule registerFile #(parameter dataWidth=32, parameter addrWidth=5) (\n       ^~~~~~~~~~~~\n                                                                                  : ... Top module \'registerNx\'\nmodule registerNx #(parameter regWidth=8)(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module controlPathDriver #(parameter controlWordWidth=16, parameter caddrW=16) (
    output PCSel,
    output [2:0] ImmSel,
    output BrUn, ASel, BSel,
    output [3:0] ALUSel,
    output MemRW, RegWEn,
    output [1:0] WBSel,
    input  [31:0] inst32,
    input  BrEq, BrLt,
    input  sysCLK
);

	wire [14:0] rawControlWord;
	wire [11:0] rawInstCodes;
	assign rawInstCodes[10:0] = {inst32[30], inst32[14:12], inst32[6:2], BrEq, BrLt};

	ControlPath32v2 callCP(rawControlWord[14:0], rawInstCodes[10:0], sysCLK);


    assign PCSel        = rawControlWord[14];
    assign ImmSel[2:0]  = rawControlWord[13:11];
    assign BrUn         = rawControlWord[10];
    assign ASel         = rawControlWord[9];
    assign BSel         = rawControlWord[8];
    assign ALUSel[3:0]  = rawControlWord[7:4];
    assign MemRW        = rawControlWord[3];
    assign RegWEn       = rawControlWord[2];
    assign WBSel[1:0]   = rawControlWord[1:0];

endmodule
module controlPathDriver #(parameter controlWordWidth=16, parameter caddrW=16) (
    output PCSel,
    output [2:0] ImmSel,
    output BrUn, ASel, BSel,
    output [3:0] ALUSel,
    output MemRW, RegWEn,
    output [1:0] WBSel,
    input  [31:0] inst32,
    input  BrEq, BrLt,
    input  sysCLK
);


	wire [14:0] rawControlWord;
	wire [11:0] rawInstCodes;
	assign rawInstCodes[10:0] = {inst32[30], inst32[14:12], inst32[6:2], BrEq, BrLt};

	ControlPath32v2 callCP(rawControlWord[14:0], rawInstCodes[10:0], sysCLK);


    assign PCSel        = rawControlWord[14];
    assign ImmSel[2:0]  = rawControlWord[13:11];
    assign BrUn         = rawControlWord[10];
    assign ASel         = rawControlWord[9];
    assign BSel         = rawControlWord[8];
    assign ALUSel[3:0]  = rawControlWord[7:4];
    assign MemRW        = rawControlWord[3];
    assign RegWEn       = rawControlWord[2];
    assign WBSel[1:0]   = rawControlWord[1:0];

endmodule