data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v
 line:187: before: ":"
1: b'%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:1: Cannot find include file: ctrl_encode_def.v\n`include "ctrl_encode_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131249673/MIPS_Single_Line,data/full_repos/permissive/131249673/ctrl_encode_def.v\n             data/full_repos/permissive/131249673/MIPS_Single_Line,data/full_repos/permissive/131249673/ctrl_encode_def.v.v\n             data/full_repos/permissive/131249673/MIPS_Single_Line,data/full_repos/permissive/131249673/ctrl_encode_def.v.sv\n             ctrl_encode_def.v\n             ctrl_encode_def.v.v\n             ctrl_encode_def.v.sv\n             obj_dir/ctrl_encode_def.v\n             obj_dir/ctrl_encode_def.v.v\n             obj_dir/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:2: Cannot find include file: instruction_def.v\n`include "instruction_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:45: Define or directive not defined: \'`INSTR_RTYPE_OP\'\n assign RType   = (Op == `INSTR_RTYPE_OP);\n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign RType   = (Op == `INSTR_RTYPE_OP);\n                                        ^\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:46: Define or directive not defined: \'`INSTR_ADDI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:46: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                        ^~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:46: Define or directive not defined: \'`INSTR_ADDIU_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:46: Define or directive not defined: \'`INSTR_ANDI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:46: Define or directive not defined: \'`INSTR_ORI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                                                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:46: Define or directive not defined: \'`INSTR_XORI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                                                                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:46: Define or directive not defined: \'`INSTR_LUI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                                                                                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:46: Define or directive not defined: \'`INSTR_SLTI_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                                                                                                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:46: Define or directive not defined: \'`INSTR_SLTIU_OP\'\n assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);\n                                                                                                                                                                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:47: Define or directive not defined: \'`INSTR_BEQ_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:47: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                       ^~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:47: Define or directive not defined: \'`INSTR_BNE_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:47: Define or directive not defined: \'`INSTR_BGEZ_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:47: Define or directive not defined: \'`INSTR_BGTZ_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                                                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:47: Define or directive not defined: \'`INSTR_BLEZ_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                                                                                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:47: Define or directive not defined: \'`INSTR_BLTZ_OP\'\n assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);\n                                                                                                                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:48: Define or directive not defined: \'`INSTR_J_OP\'\n assign JType   = (Op == `INSTR_J_OP || Op == `INSTR_JAL_OP);\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:48: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign JType   = (Op == `INSTR_J_OP || Op == `INSTR_JAL_OP);\n                                     ^~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:48: Define or directive not defined: \'`INSTR_JAL_OP\'\n assign JType   = (Op == `INSTR_J_OP || Op == `INSTR_JAL_OP);\n                                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:49: Define or directive not defined: \'`INSTR_LW_OP\'\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:49: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                                      ^~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:49: Define or directive not defined: \'`INSTR_LB_OP\'\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:49: Define or directive not defined: \'`INSTR_LH_OP\'\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                                                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:49: Define or directive not defined: \'`INSTR_LBU_OP\'\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                                                                                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:49: Define or directive not defined: \'`INSTR_LHU_OP\'\n assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);\n                                                                                                                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:50: Define or directive not defined: \'`INSTR_SW_OP\'\n assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:50: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);\n                                      ^~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:50: Define or directive not defined: \'`INSTR_SB_OP\'\n assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);\n                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:50: Define or directive not defined: \'`INSTR_SH_OP\'\n assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);\n                                                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:128: Define or directive not defined: \'`NPC_PLUS4\'\n            NPCOp  = `NPC_PLUS4; \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:128: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            NPCOp  = `NPC_PLUS4; \n                               ^\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:165: Define or directive not defined: \'`EXT_UNSIGNED\'\n               EXTOp = `EXT_UNSIGNED;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:165: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n               EXTOp = `EXT_UNSIGNED;\n                                    ^\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:181: Define or directive not defined: \'`INSTR_ADDI_OP\'\n              if (Op == `INSTR_ADDI_OP) ALUOp = `ALUOp_ADD;\n                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:181: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n              if (Op == `INSTR_ADDI_OP) ALUOp = `ALUOp_ADD;\n                                      ^\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:181: Define or directive not defined: \'`ALUOp_ADD\'\n              if (Op == `INSTR_ADDI_OP) ALUOp = `ALUOp_ADD;\n                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:182: Define or directive not defined: \'`INSTR_ADDIU_OP\'\n              else if(Op == `INSTR_ADDIU_OP) ALUOp = `ALUOp_ADD;\n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:182: Define or directive not defined: \'`ALUOp_ADD\'\n              else if(Op == `INSTR_ADDIU_OP) ALUOp = `ALUOp_ADD;\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:183: Define or directive not defined: \'`INSTR_ANDI_OP\'\n              else if(Op == `INSTR_ANDI_OP) ALUOp = `ALUOp_AND;\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:183: Define or directive not defined: \'`ALUOp_AND\'\n              else if(Op == `INSTR_ANDI_OP) ALUOp = `ALUOp_AND;\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:184: Define or directive not defined: \'`INSTR_ORI_OP\'\n              else if(Op == `INSTR_ORI_OP) ALUOp = `ALUOp_OR;\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:184: Define or directive not defined: \'`ALUOp_OR\'\n              else if(Op == `INSTR_ORI_OP) ALUOp = `ALUOp_OR;\n                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:185: Define or directive not defined: \'`INSTR_XORI_OP\'\n              else if(Op == `INSTR_XORI_OP) ALUOp = `ALUOp_XOR;\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:185: Define or directive not defined: \'`ALUOp_XOR\'\n              else if(Op == `INSTR_XORI_OP) ALUOp = `ALUOp_XOR;\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:186: Define or directive not defined: \'`INSTR_LUI_OP\'\n              else if(Op == `INSTR_LUI_OP)\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_Single_Line/ctrl.v:188: Define or directive not defined: \'`ALUOp_SLL\'\n                  ALUOp = `ALUOp_SLL;\n                          ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ctrl(clk, rst, Zero, Op, Funct,
            RFWr, DMWr, PCWr, IRWr,
            EXTOp, ALUOp, NPCOp, GPRSel,
            WDSel, ASel, BSel);
    

	input 			clk, rst, Zero;       
	input  [5:0] 	Op;
	input  [5:0] 	Funct;
	output       	RFWr;
	output       	DMWr;
	output       	PCWr;
	output       	IRWr;
	output [1:0] 	EXTOp;
	output [4:0] 	ALUOp;
	output [1:0] 	NPCOp;
	output [1:0] 	GPRSel;
	output [1:0] 	WDSel;
	output [1:0] 	ASel;
	output [1:0]    BSel;
    
	parameter 	Fetch  = 4'b0000,
				DCD    = 4'b0001,
				Exe    = 4'b0010,
				MA     = 4'b0011,
				Branch = 4'b0100,
				Jmp    = 4'b0101,
				MR     = 4'b0110,
				MW     = 4'b0111,
				WB     = 4'b1000,
				MemWB  = 4'b1001;
    

	wire RType;
	wire IType;
	wire BrType;
	wire JType;
	wire LdType;
	wire StType;
	wire MemType;
	

	assign RType   = (Op == `INSTR_RTYPE_OP);
	assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);
	assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);
	assign JType   = (Op == `INSTR_J_OP || Op == `INSTR_JAL_OP);
	assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);
	assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);
	assign MemType = LdType || StType;
    



	reg [3:0] nextstate;
	reg [3:0] state;
   
	always @(posedge clk or posedge rst) begin
		if ( rst )
			state <= Fetch;
		else
			state <= nextstate;
	end
             

	always @(*) begin
		case (state)

        Fetch: nextstate = DCD;
         

        DCD: nextstate = Exe;
		

        Exe:  
        
         

         Jmp: 	nextstate = Fetch;
         

         MA: begin 
            if ( LdType )
				   nextstate = MR;
            else if ( StType )
					 nextstate = MW;
			   end
	        

         MR:   nextstate = MemWB;
         

         MW:   nextstate = Fetch;
         

         WB: 	 nextstate = Fetch;
         

         MemWB: nextstate = Fetch;      
			 default: ;
       endcase
   end

	
	
	


	 reg       RFWr;
   reg       DMWr;
   reg       PCWr;
   reg       IRWr;
   reg [1:0] EXTOp;
   reg [4:0] ALUOp;
   reg [1:0] NPCOp;
   reg [1:0] GPRSel;
   reg [1:0] WDSel;
   reg [1:0] ASel;
   reg       BSel;
	

	always @( * ) begin
	   case ( state ) 

		   Fetch: begin
            PCWr   = 1'b1;
            NPCOp  = `NPC_PLUS4; 
            IRWr   = 1'b1;
            RFWr  = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = 0;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			 end
			

       DCD: begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = 0;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			 end
			

       Exe: 	begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b0;
            DMWr   = 1'b0;
            ASel = 2'b00;
            
            if (IType)
               EXTOp = `EXT_UNSIGNED;
            else
               EXTOp = 0;
               
            GPRSel = 0;
            WDSel  = 0;
            DMWr   = 0;
            
            if (IType)
               BSel   = 1'b1;
            else
               BSel   = 1'b0;
            

            if (IType)
            begin
              if (Op == `INSTR_ADDI_OP) ALUOp = `ALUOp_ADD;
              else if(Op == `INSTR_ADDIU_OP) ALUOp = `ALUOp_ADD;
              else if(Op == `INSTR_ANDI_OP) ALUOp = `ALUOp_AND;
              else if(Op == `INSTR_ORI_OP) ALUOp = `ALUOp_OR;
              else if(Op == `INSTR_XORI_OP) ALUOp = `ALUOp_XOR;
              else if(Op == `INSTR_LUI_OP)
                begin
                  ALUOp = `ALUOp_SLL;
                  ASel = 2'b01;
                end
              else if(Op == `INSTR_SLTI_OP) ALUOp = `ALUOp_SLT;
              else if(Op == `INSTR_SLTIU_OP) ALUOp = `ALUOp_SLT;
            end
            

            else if (Op == `INSTR_RTYPE_OP) 
            begin
               case (Funct)
                   `INSTR_ADD_FUNCT: ALUOp = `ALUOp_ADD;
                   `INSTR_ADDU_FUNCT: ALUOp = `ALUOp_ADDU;
                   `INSTR_SUB_FUNCT: ALUOp = `ALUOp_SUB;
                   `INSTR_SUBU_FUNCT: ALUOp = `ALUOp_SUBU;
                   `INSTR_AND_FUNCT: ALUOp = `ALUOp_AND;
                   `INSTR_NOR_FUNCT: ALUOp = `ALUOp_NOR;
                   `INSTR_OR_FUNCT: ALUOp = `ALUOp_OR;
                   `INSTR_XOR_FUNCT: ALUOp = `ALUOp_XOR;
                   `INSTR_SLT_FUNCT: ALUOp = `ALUOp_SLT;
                   `INSTR_SLTU_FUNCT: ALUOp = `ALUOp_SLTU;
                   
                   `INSTR_SLL_FUNCT: 
                     begin
                      ALUOp = `ALUOp_SLL;
                      ASel = 2'b10;
                     end
                     
                   `INSTR_SRL_FUNCT: 
                     begin
                      ALUOp = `ALUOp_SRL;
                      ASel = 2'b10;
                     end
                     
                   `INSTR_SRA_FUNCT:
                     begin
                      ALUOp = `ALUOp_SRA;
                      ASel = 2'b10;
                     end
                     
                   `INSTR_SLLV_FUNCT:
                     begin
                      ALUOp = `ALUOp_SLL;
                      ASel = 2'b10;
                      BSel = 1'b0;
                     end
                     
                   `INSTR_SRLV_FUNCT:
                     begin
                      ALUOp = `ALUOp_SRL;
                      ASel = 2'b10;
                     end
                     
                   `INSTR_SRAV_FUNCT:
                     begin
                      ALUOp = `ALUOp_SRA;
                      ASel = 2'b10;
                     end
                     
                   `INSTR_JR_FUNCT:
                     begin
                      PCWr   = 1'b1;
                      NPCOp  = `NPC_JMPR;
                      IRWr   = 1'b0;
                      DMWr   = 1'b0;
                      EXTOp  = `EXT_SIGNED;
                      ASel   = 0;
                      BSel   = 0;
                      ALUOp  = 0;  
                     end
                     







                   default: ;
               endcase
            end
			   end
			   

         Branch: begin
            if (Zero)
               PCWr = 1'b1;
            else
               PCWr = 1'b0;
            NPCOp  = `NPC_BRANCH;
            IRWr   = 1'b0;
            RFWr   = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = `EXT_SIGNED;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 2'b0;
            BSel   = 1'b0;
            ALUOp  = `ALUOp_EQL;
			   end
			

         Jmp: 	begin
            PCWr   = 1'b1;
            NPCOp  = `NPC_JUMP;
            IRWr   = 1'b0;
            if (Op == `INSTR_J_OP)
              RFWr = 1'b0;
            else
              RFWr  = 1'b1;
            DMWr   = 1'b0;
            EXTOp  = `EXT_SIGNED;
            GPRSel = `GPRSel_31;
            WDSel  = `WDSel_FromPC;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			   end
			   

         MA: begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr   = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = `EXT_SIGNED;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 1'b1;
            ALUOp  = `ALUOp_ADDU;
			   end
			   

         MR:  begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = 0;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			   end
			   

         MW:  begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b0;
            DMWr   = 1'b1;
            EXTOp  = 0;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			   end
         

         WB: 	begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b1;
            DMWr   = 1'b0;
            EXTOp  = 0;
            if (IType)
               GPRSel = `GPRSel_RT;
            else
               GPRSel = `GPRSel_RD;
            WDSel  = `WDSel_FromALU;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			   end
         

         MemWB: begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b1;
            DMWr   = 1'b0;
            EXTOp  = 0;
            GPRSel = `GPRSel_RT;
            WDSel  = `WDSel_FromMEM;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			   end
			   
			default: begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = 0;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			end
	   endcase
   end
    
endmodule
module ctrl(clk, rst, Zero, Op, Funct,
            RFWr, DMWr, PCWr, IRWr,
            EXTOp, ALUOp, NPCOp, GPRSel,
            WDSel, ASel, BSel);

    

	input 			clk, rst, Zero;       
	input  [5:0] 	Op;
	input  [5:0] 	Funct;
	output       	RFWr;
	output       	DMWr;
	output       	PCWr;
	output       	IRWr;
	output [1:0] 	EXTOp;
	output [4:0] 	ALUOp;
	output [1:0] 	NPCOp;
	output [1:0] 	GPRSel;
	output [1:0] 	WDSel;
	output [1:0] 	ASel;
	output [1:0]    BSel;
    
	parameter 	Fetch  = 4'b0000,
				DCD    = 4'b0001,
				Exe    = 4'b0010,
				MA     = 4'b0011,
				Branch = 4'b0100,
				Jmp    = 4'b0101,
				MR     = 4'b0110,
				MW     = 4'b0111,
				WB     = 4'b1000,
				MemWB  = 4'b1001;
    

	wire RType;
	wire IType;
	wire BrType;
	wire JType;
	wire LdType;
	wire StType;
	wire MemType;
	

	assign RType   = (Op == `INSTR_RTYPE_OP);
	assign IType   = (Op == `INSTR_ADDI_OP || Op == `INSTR_ADDIU_OP || Op == `INSTR_ANDI_OP || Op == `INSTR_ORI_OP || Op == `INSTR_XORI_OP || Op == `INSTR_LUI_OP || Op == `INSTR_SLTI_OP || Op == `INSTR_SLTIU_OP);
	assign BrType  = (Op == `INSTR_BEQ_OP || Op == `INSTR_BNE_OP || Op == `INSTR_BGEZ_OP || Op == `INSTR_BGTZ_OP || Op == `INSTR_BLEZ_OP || Op == `INSTR_BLTZ_OP);
	assign JType   = (Op == `INSTR_J_OP || Op == `INSTR_JAL_OP);
	assign LdType  = (Op == `INSTR_LW_OP || Op == `INSTR_LB_OP || Op == `INSTR_LH_OP || Op == `INSTR_LBU_OP || Op == `INSTR_LHU_OP);
	assign StType  = (Op == `INSTR_SW_OP || Op == `INSTR_SB_OP || Op == `INSTR_SH_OP);
	assign MemType = LdType || StType;
    



	reg [3:0] nextstate;
	reg [3:0] state;
   
	always @(posedge clk or posedge rst) begin
		if ( rst )
			state <= Fetch;
		else
			state <= nextstate;
	end
             

	always @(*) begin
		case (state)

        Fetch: nextstate = DCD;
         

        DCD: nextstate = Exe;
		

        Exe:  
        
         

         Jmp: 	nextstate = Fetch;
         

         MA: begin 
            if ( LdType )
				   nextstate = MR;
            else if ( StType )
					 nextstate = MW;
			   end
	        

         MR:   nextstate = MemWB;
         

         MW:   nextstate = Fetch;
         

         WB: 	 nextstate = Fetch;
         

         MemWB: nextstate = Fetch;      
			 default: ;
       endcase
   end

	
	
	


	 reg       RFWr;
   reg       DMWr;
   reg       PCWr;
   reg       IRWr;
   reg [1:0] EXTOp;
   reg [4:0] ALUOp;
   reg [1:0] NPCOp;
   reg [1:0] GPRSel;
   reg [1:0] WDSel;
   reg [1:0] ASel;
   reg       BSel;
	

	always @( * ) begin
	   case ( state ) 

		   Fetch: begin
            PCWr   = 1'b1;
            NPCOp  = `NPC_PLUS4; 
            IRWr   = 1'b1;
            RFWr  = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = 0;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			 end
			

       DCD: begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = 0;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			 end
			

       Exe: 	begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b0;
            DMWr   = 1'b0;
            ASel = 2'b00;
            
            if (IType)
               EXTOp = `EXT_UNSIGNED;
            else
               EXTOp = 0;
               
            GPRSel = 0;
            WDSel  = 0;
            DMWr   = 0;
            
            if (IType)
               BSel   = 1'b1;
            else
               BSel   = 1'b0;
            

            if (IType)
            begin
              if (Op == `INSTR_ADDI_OP) ALUOp = `ALUOp_ADD;
              else if(Op == `INSTR_ADDIU_OP) ALUOp = `ALUOp_ADD;
              else if(Op == `INSTR_ANDI_OP) ALUOp = `ALUOp_AND;
              else if(Op == `INSTR_ORI_OP) ALUOp = `ALUOp_OR;
              else if(Op == `INSTR_XORI_OP) ALUOp = `ALUOp_XOR;
              else if(Op == `INSTR_LUI_OP)
                begin
                  ALUOp = `ALUOp_SLL;
                  ASel = 2'b01;
                end
              else if(Op == `INSTR_SLTI_OP) ALUOp = `ALUOp_SLT;
              else if(Op == `INSTR_SLTIU_OP) ALUOp = `ALUOp_SLT;
            end
            

            else if (Op == `INSTR_RTYPE_OP) 
            begin
               case (Funct)
                   `INSTR_ADD_FUNCT: ALUOp = `ALUOp_ADD;
                   `INSTR_ADDU_FUNCT: ALUOp = `ALUOp_ADDU;
                   `INSTR_SUB_FUNCT: ALUOp = `ALUOp_SUB;
                   `INSTR_SUBU_FUNCT: ALUOp = `ALUOp_SUBU;
                   `INSTR_AND_FUNCT: ALUOp = `ALUOp_AND;
                   `INSTR_NOR_FUNCT: ALUOp = `ALUOp_NOR;
                   `INSTR_OR_FUNCT: ALUOp = `ALUOp_OR;
                   `INSTR_XOR_FUNCT: ALUOp = `ALUOp_XOR;
                   `INSTR_SLT_FUNCT: ALUOp = `ALUOp_SLT;
                   `INSTR_SLTU_FUNCT: ALUOp = `ALUOp_SLTU;
                   
                   `INSTR_SLL_FUNCT: 
                     begin
                      ALUOp = `ALUOp_SLL;
                      ASel = 2'b10;
                     end
                     
                   `INSTR_SRL_FUNCT: 
                     begin
                      ALUOp = `ALUOp_SRL;
                      ASel = 2'b10;
                     end
                     
                   `INSTR_SRA_FUNCT:
                     begin
                      ALUOp = `ALUOp_SRA;
                      ASel = 2'b10;
                     end
                     
                   `INSTR_SLLV_FUNCT:
                     begin
                      ALUOp = `ALUOp_SLL;
                      ASel = 2'b10;
                      BSel = 1'b0;
                     end
                     
                   `INSTR_SRLV_FUNCT:
                     begin
                      ALUOp = `ALUOp_SRL;
                      ASel = 2'b10;
                     end
                     
                   `INSTR_SRAV_FUNCT:
                     begin
                      ALUOp = `ALUOp_SRA;
                      ASel = 2'b10;
                     end
                     
                   `INSTR_JR_FUNCT:
                     begin
                      PCWr   = 1'b1;
                      NPCOp  = `NPC_JMPR;
                      IRWr   = 1'b0;
                      DMWr   = 1'b0;
                      EXTOp  = `EXT_SIGNED;
                      ASel   = 0;
                      BSel   = 0;
                      ALUOp  = 0;  
                     end
                     







                   default: ;
               endcase
            end
			   end
			   

         Branch: begin
            if (Zero)
               PCWr = 1'b1;
            else
               PCWr = 1'b0;
            NPCOp  = `NPC_BRANCH;
            IRWr   = 1'b0;
            RFWr   = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = `EXT_SIGNED;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 2'b0;
            BSel   = 1'b0;
            ALUOp  = `ALUOp_EQL;
			   end
			

         Jmp: 	begin
            PCWr   = 1'b1;
            NPCOp  = `NPC_JUMP;
            IRWr   = 1'b0;
            if (Op == `INSTR_J_OP)
              RFWr = 1'b0;
            else
              RFWr  = 1'b1;
            DMWr   = 1'b0;
            EXTOp  = `EXT_SIGNED;
            GPRSel = `GPRSel_31;
            WDSel  = `WDSel_FromPC;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			   end
			   

         MA: begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr   = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = `EXT_SIGNED;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 1'b1;
            ALUOp  = `ALUOp_ADDU;
			   end
			   

         MR:  begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = 0;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			   end
			   

         MW:  begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b0;
            DMWr   = 1'b1;
            EXTOp  = 0;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			   end
         

         WB: 	begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b1;
            DMWr   = 1'b0;
            EXTOp  = 0;
            if (IType)
               GPRSel = `GPRSel_RT;
            else
               GPRSel = `GPRSel_RD;
            WDSel  = `WDSel_FromALU;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			   end
         

         MemWB: begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b1;
            DMWr   = 1'b0;
            EXTOp  = 0;
            GPRSel = `GPRSel_RT;
            WDSel  = `WDSel_FromMEM;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			   end
			   
			default: begin
            PCWr   = 1'b0;
            NPCOp  = 0;
            IRWr   = 1'b0;
            RFWr  = 1'b0;
            DMWr   = 1'b0;
            EXTOp  = 0;
            GPRSel = 0;
            WDSel  = 0;
            ASel   = 0;
            BSel   = 0;
            ALUOp  = 0;
			end
	   endcase
   end
    
endmodule