data/full_repos/permissive/205673649/BIP/Source/control.v
1: b"%Error: data/full_repos/permissive/205673649/BIP/Source/control.v:44: Cannot find file containing module: 'pc'\n    pc\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/205673649/BIP/Source,data/full_repos/permissive/205673649/pc\n             data/full_repos/permissive/205673649/BIP/Source,data/full_repos/permissive/205673649/pc.v\n             data/full_repos/permissive/205673649/BIP/Source,data/full_repos/permissive/205673649/pc.sv\n             pc\n             pc.v\n             pc.sv\n             obj_dir/pc\n             obj_dir/pc.v\n             obj_dir/pc.sv\n%Error: data/full_repos/permissive/205673649/BIP/Source/control.v:56: Cannot find file containing module: 'instruction_decoder'\n    instruction_decoder\n    ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module control
#(
    parameter NB_OPCODE = 5,
    parameter NB_ADDR = 11,
    parameter NB_DECODER_SEL_A = 2
)
(
    input i_clk,
    input i_rst,
    input [NB_OPCODE-1:0] i_opcode,
    output [NB_ADDR-1:0] o_addr,
    output [NB_DECODER_SEL_A-1:0] o_selA,
    output o_selB,
    output o_wrAcc,
    output [NB_OPCODE-1:0] o_op,
    output o_wrRam,
    output o_rdRam
);

wire wrPc;

    pc
#(
    .NB_PC(NB_ADDR)
)
    u_pc
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_enable(wrPc),
    .o_addr(o_addr)
);

    instruction_decoder
#(
    .NB_OPCODE(NB_OPCODE),
    .NB_DECODER_SEL_A(NB_DECODER_SEL_A)
)
    u_instruction_decoder
(
    .i_opcode(i_opcode),
    .o_wrPc(wrPc),
    .o_selA(o_selA),
    .o_selB(o_selB),
    .o_wrAcc(o_wrAcc),
    .o_op(o_op),
    .o_wrRam(o_wrRam),
    .o_rdRam(o_rdRam)
);
endmodule
module control
#(
    parameter NB_OPCODE = 5,
    parameter NB_ADDR = 11,
    parameter NB_DECODER_SEL_A = 2
)
(
    input i_clk,
    input i_rst,
    input [NB_OPCODE-1:0] i_opcode,
    output [NB_ADDR-1:0] o_addr,
    output [NB_DECODER_SEL_A-1:0] o_selA,
    output o_selB,
    output o_wrAcc,
    output [NB_OPCODE-1:0] o_op,
    output o_wrRam,
    output o_rdRam
);


wire wrPc;

    pc
#(
    .NB_PC(NB_ADDR)
)
    u_pc
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_enable(wrPc),
    .o_addr(o_addr)
);

    instruction_decoder
#(
    .NB_OPCODE(NB_OPCODE),
    .NB_DECODER_SEL_A(NB_DECODER_SEL_A)
)
    u_instruction_decoder
(
    .i_opcode(i_opcode),
    .o_wrPc(wrPc),
    .o_selA(o_selA),
    .o_selB(o_selB),
    .o_wrAcc(o_wrAcc),
    .o_op(o_op),
    .o_wrRam(o_wrRam),
    .o_rdRam(o_rdRam)
);
endmodule