data/full_repos/permissive/179980995/FPU/before roll.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/179980995/FPU/before\n        ... Looked in:\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/data/full_repos/permissive/179980995/FPU/before\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/data/full_repos/permissive/179980995/FPU/before.v\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/data/full_repos/permissive/179980995/FPU/before.sv\n             data/full_repos/permissive/179980995/FPU/before\n             data/full_repos/permissive/179980995/FPU/before.v\n             data/full_repos/permissive/179980995/FPU/before.sv\n             obj_dir/data/full_repos/permissive/179980995/FPU/before\n             obj_dir/data/full_repos/permissive/179980995/FPU/before.v\n             obj_dir/data/full_repos/permissive/179980995/FPU/before.sv\n%Error: Cannot find file containing module: roll.v\n%Error: Exiting due to 2 error(s)\n'
module mux2X1(in0, in1, sel, out);
input in0, in1, sel;
output out;
wire in0, in1, sel;
reg out;
always@(*) begin
out = sel?in1:in0;
end
endmodule
module mux2X1(in0, in1, sel, out);

input in0, in1, sel;
output out;
wire in0, in1, sel;
reg out;
always@(*) begin
out = sel?in1:in0;
end
endmodule