data/full_repos/permissive/205919221/ip/ip_fifo.v
1: b"%Error: data/full_repos/permissive/205919221/ip/ip_fifo.v:17: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n do, clkr, re,\n ^~\n%Error: data/full_repos/permissive/205919221/ip/ip_fifo.v:27: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n output [31:0] do;\n               ^~\n%Error: data/full_repos/permissive/205919221/ip/ip_fifo.v:49: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n .do(do),\n  ^~\n%Error: data/full_repos/permissive/205919221/ip/ip_fifo.v:49: syntax error, unexpected '(', expecting ')'\n .do(do),\n     ^~\n%Error: Exiting due to 4 error(s)\n"
module ip_fifo (
	rst,
	di, clkw, we,
	do, clkr, re,
	empty_flag, aempty_flag,
	full_flag, afull_flag 
);

	input rst;
	input [31:0] di;
	input clkw, we;
	input clkr,re;

	output [31:0] do;
	output empty_flag, aempty_flag;
	output full_flag, afull_flag;

EG_LOGIC_FIFO #(
 	.DATA_WIDTH_W(32),
	.DATA_WIDTH_R(32),
	.DATA_DEPTH_W(512),
	.DATA_DEPTH_R(512),
	.ENDIAN("BIG"),
	.RESETMODE("ASYNC"),
	.E(0),
	.F(512),
	.ASYNC_RESET_RELEASE("SYNC"),
	.AE(4),
	.AF(508))
logic_fifo(
	.rst(rst),
	.di(di),
	.clkw(clkw),
	.we(we),
	.csw(3'b111),
	.do(do),
	.clkr(clkr),
	.re(re),
	.csr(3'b111),
	.ore(1'b0),
	.empty_flag(empty_flag),
	.aempty_flag(aempty_flag),
	.full_flag(full_flag),
	.afull_flag(afull_flag)

);

endmodule
module ip_fifo (
	rst,
	di, clkw, we,
	do, clkr, re,
	empty_flag, aempty_flag,
	full_flag, afull_flag 
);


	input rst;
	input [31:0] di;
	input clkw, we;
	input clkr,re;

	output [31:0] do;
	output empty_flag, aempty_flag;
	output full_flag, afull_flag;

EG_LOGIC_FIFO #(
 	.DATA_WIDTH_W(32),
	.DATA_WIDTH_R(32),
	.DATA_DEPTH_W(512),
	.DATA_DEPTH_R(512),
	.ENDIAN("BIG"),
	.RESETMODE("ASYNC"),
	.E(0),
	.F(512),
	.ASYNC_RESET_RELEASE("SYNC"),
	.AE(4),
	.AF(508))
logic_fifo(
	.rst(rst),
	.di(di),
	.clkw(clkw),
	.we(we),
	.csw(3'b111),
	.do(do),
	.clkr(clkr),
	.re(re),
	.csr(3'b111),
	.ore(1'b0),
	.empty_flag(empty_flag),
	.aempty_flag(aempty_flag),
	.full_flag(full_flag),
	.afull_flag(afull_flag)

);

endmodule