data/full_repos/permissive/143278/ivltests/bitsel10.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/bitsel10.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #1 CLK = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/bitsel10.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (bus !== 8\'bzzzzzzz1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/bitsel10.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (bus !== 8\'bzzzzzzz1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/bitsel10.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #1 CLK = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/bitsel10.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #1 D = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/bitsel10.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (bus !== 8\'bzzzzzzz1) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/bitsel10.v:64: Operator COND expects 2 bits on the Conditional True, but Conditional True\'s VARREF \'save\' generates 1 bits.\n                                                                        : ... In instance main.drv\n   assign TO = E? save : 2\'bz;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/bitsel10.v:64: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 2 bits.\n                                                                        : ... In instance main.drv\n   assign TO = E? save : 2\'bz;\n             ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module BUFT(inout wire TO, input wire D, input wire E, input wire CLK);

   reg save;
   assign TO = E? save : 2'bz;

   always @(posedge CLK)
     save <= D;

endmodule
module BUFT(inout wire TO, input wire D, input wire E, input wire CLK);


   reg save;
   assign TO = E? save : 2'bz;

   always @(posedge CLK)
     save <= D;

endmodule