data/full_repos/permissive/139213403/FPGA/pwm_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:32: syntax error, unexpected \'@\'\n  @(negedge reset);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:36: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:40: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:44: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:48: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:52: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/pwm_testbench.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: Exiting due to 6 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pwm_testbench;
	reg clk, reset;
	reg [0:0] test_in;
	reg [3:0] test_ds;
	wire [0:0] test_out;
	
	localparam T=20;
	
	pwm uut(clk, reset, test_in, test_ds, test_out);
	
	always
	begin
		clk = 1'b1;
		#(T / 2);
		clk = 1'b0;
		#(T / 2);
	end
	
	initial
	begin
		reset = 1'b1;
		#(T / 2);
		reset = 1'b0;
	end
	
	initial
	begin
		test_in = 1'b1;
		test_ds = 4'b1111;
		@(negedge reset);
		@(negedge clk);
		
		#1000;
		@(negedge clk);
		test_ds = 4'b1000;
		
		#1000;
		@(negedge clk);
		test_ds = 4'b0100;
		
		#1000;
		@(negedge clk);
		test_ds = 4'b0010;
		
		#1000;
		@(negedge clk);
		test_ds = 4'b0001;
		
		#1000;
		@(negedge clk);
		test_ds = 4'b0000;
		
		#1000;
		$stop;
	end
	
endmodule
module pwm_testbench;

	reg clk, reset;
	reg [0:0] test_in;
	reg [3:0] test_ds;
	wire [0:0] test_out;
	
	localparam T=20;
	
	pwm uut(clk, reset, test_in, test_ds, test_out);
	
	always
	begin
		clk = 1'b1;
		#(T / 2);
		clk = 1'b0;
		#(T / 2);
	end
	
	initial
	begin
		reset = 1'b1;
		#(T / 2);
		reset = 1'b0;
	end
	
	initial
	begin
		test_in = 1'b1;
		test_ds = 4'b1111;
		@(negedge reset);
		@(negedge clk);
		
		#1000;
		@(negedge clk);
		test_ds = 4'b1000;
		
		#1000;
		@(negedge clk);
		test_ds = 4'b0100;
		
		#1000;
		@(negedge clk);
		test_ds = 4'b0010;
		
		#1000;
		@(negedge clk);
		test_ds = 4'b0001;
		
		#1000;
		@(negedge clk);
		test_ds = 4'b0000;
		
		#1000;
		$stop;
	end
	
endmodule