data/full_repos/permissive/175197601/hdl/jtpopeye_cen.v
 line:49: before: "/"
data/verilator_xmls/d9e114df-3ec6-4428-899e-f061ae6b1c38.xml
module jtpopeye_cen(
    input           clk,

    output reg      H0_cen,
    output reg      cpu_cen,
    output reg      ay_cen,
    output reg      pxl_cen,
    output reg      pxl2_cen,
    output reg      pxl4_cen
);

reg [3:0] cnt2='d0;
reg [4:0] cnt20='d0;


always @(negedge clk) begin
    cnt2  <= cnt2 + 4'd1;
    cnt20 <= cnt20 == 5'd19 ? 5'd0 : (cnt20+5'd1);
    
    pxl4_cen <= cnt2[ 0 ]==1'b0;
    pxl2_cen <= cnt2[1:0]==2'b00;
    pxl_cen  <= cnt2[2:0]==3'b000;
    H0_cen   <= cnt2[3:0]==4'b1000;

    cpu_cen  <= cnt20==5'd0 || cnt20==5'd10;
    ay_cen   <= cnt20==5'd0;
end

endmodule
module jtpopeye_cen(
    input           clk,

    output reg      H0_cen,
    output reg      cpu_cen,
    output reg      ay_cen,
    output reg      pxl_cen,
    output reg      pxl2_cen,
    output reg      pxl4_cen
);


reg [3:0] cnt2='d0;
reg [4:0] cnt20='d0;


always @(negedge clk) begin
    cnt2  <= cnt2 + 4'd1;
    cnt20 <= cnt20 == 5'd19 ? 5'd0 : (cnt20+5'd1);
    
    pxl4_cen <= cnt2[ 0 ]==1'b0;
    pxl2_cen <= cnt2[1:0]==2'b00;
    pxl_cen  <= cnt2[2:0]==3'b000;
    H0_cen   <= cnt2[3:0]==4'b1000;

    cpu_cen  <= cnt20==5'd0 || cnt20==5'd10;
    ay_cen   <= cnt20==5'd0;
end

endmodule