data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v
 line:58: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:57: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:65: syntax error, unexpected \'@\'\n    @(posedge clk)\n    ^\n%Error: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:69: syntax error, unexpected \'@\'\n    @(negedge p_valid)\n    ^\n%Error: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:80: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104443190/complex_mult/tb_complex_mult.v:103: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~clk;\n       ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_complex_mult;

parameter N = 2;



reg     clk;

reg ab_valid;
reg signed [N-1:0] ar,ai,br,bi;

wire p_valid;
wire signed [N+N:0] pr,pi;


reg [4*N-1:0] i,j;
reg signed [N-1:0] exp_ar,exp_ai,exp_br,exp_bi;
reg signed [N+N:0] real_part_dsp,imag_part_dsp;


complex_mult
#(
	.WIDTH(N),
	.INPUT_BUF("ON"),
	.OUTPUT_BUF("ON")
)UUT(
	.clk(clk),
	.ab_valid(ab_valid),
	.ar(ar), .ai(ai),
	.br(br), .bi(bi),
	.p_valid(p_valid),
	.pr(pr), .pi(pi)

    );

initial begin





    clk = 0;
    i = 0;
    j = 0;
    ab_valid = 0;
    ar = 0; ai = 0; br = 0; bi = 0;

    #200;


    $display("Simulation begin!");

    for(i = 0; i < 2**(4*N)-1; i = i + 1) begin
        @(posedge clk)
        #1;
        ab_valid = 1;
        ar = i[N-1:0];
        ai = i[2*N-1:N];
        br = i[3*N-1:2*N];
        bi = i[4*N-1:3*N];
    end
    @(posedge clk)
    ab_valid = 0;
    ar = 0; ai = 0; br = 0; bi = 0;

    @(negedge p_valid)
    #100;

    $display("All tests are passed!");

    $finish;

end

initial begin
	while(1)begin
		@(posedge clk);
		if(p_valid)begin
			exp_ar = j[N-1:0];
	        exp_ai = j[2*N-1:N];
	        exp_br = j[3*N-1:2*N];
	        exp_bi = j[4*N-1:3*N];

	        real_part_dsp = exp_ar*exp_br - exp_ai*exp_bi;
	        imag_part_dsp = exp_ai*exp_br + exp_ar*exp_bi;
	        if( (pr != real_part_dsp)&&(pi != imag_part_dsp) ) begin
	            $display(" Fail - Module output does not equal expected value\n");
	            $display("%d,%d,%d,%d",pr,pi,real_part_dsp,imag_part_dsp);
	            $stop;
	        end

			j = j + 1;
		end
	end
end




always #10 clk = ~clk;



endmodule
module tb_complex_mult;


parameter N = 2;



reg     clk;

reg ab_valid;
reg signed [N-1:0] ar,ai,br,bi;

wire p_valid;
wire signed [N+N:0] pr,pi;


reg [4*N-1:0] i,j;
reg signed [N-1:0] exp_ar,exp_ai,exp_br,exp_bi;
reg signed [N+N:0] real_part_dsp,imag_part_dsp;


complex_mult
#(
	.WIDTH(N),
	.INPUT_BUF("ON"),
	.OUTPUT_BUF("ON")
)UUT(
	.clk(clk),
	.ab_valid(ab_valid),
	.ar(ar), .ai(ai),
	.br(br), .bi(bi),
	.p_valid(p_valid),
	.pr(pr), .pi(pi)

    );

initial begin





    clk = 0;
    i = 0;
    j = 0;
    ab_valid = 0;
    ar = 0; ai = 0; br = 0; bi = 0;

    #200;


    $display("Simulation begin!");

    for(i = 0; i < 2**(4*N)-1; i = i + 1) begin
        @(posedge clk)
        #1;
        ab_valid = 1;
        ar = i[N-1:0];
        ai = i[2*N-1:N];
        br = i[3*N-1:2*N];
        bi = i[4*N-1:3*N];
    end
    @(posedge clk)
    ab_valid = 0;
    ar = 0; ai = 0; br = 0; bi = 0;

    @(negedge p_valid)
    #100;

    $display("All tests are passed!");

    $finish;

end

initial begin
	while(1)begin
		@(posedge clk);
		if(p_valid)begin
			exp_ar = j[N-1:0];
	        exp_ai = j[2*N-1:N];
	        exp_br = j[3*N-1:2*N];
	        exp_bi = j[4*N-1:3*N];

	        real_part_dsp = exp_ar*exp_br - exp_ai*exp_bi;
	        imag_part_dsp = exp_ai*exp_br + exp_ar*exp_bi;
	        if( (pr != real_part_dsp)&&(pi != imag_part_dsp) ) begin
	            $display(" Fail - Module output does not equal expected value\n");
	            $display("%d,%d,%d,%d",pr,pi,real_part_dsp,imag_part_dsp);
	            $stop;
	        end

			j = j + 1;
		end
	end
end




always #10 clk = ~clk;



endmodule