data/full_repos/permissive/160895047/Register_File.v
 line:33: before: "posedge"
data/verilator_xmls/4bc5ee14-2ab9-4d90-aaca-d4ce5cc708d9.xml
module Register_File(
	CLOCK,
	A1,
	A2,
	A3,
	RD1,
	RD2,
	WE,
	WD
);
input CLOCK;
input [4:0] A1;
input [4:0] A2;
input [4:0] A3;
output [31:0] RD1;
output [31:0] RD2;
input WE;
input [31:0] WD;

wire CLOCK;
wire [4:0] A1;
wire [4:0] A2;
wire [4:0] A3;
reg [31:0] RD1;
reg [31:0] RD2;
wire WE;
wire [31:0] WD;

reg [31:0] REGS[31:0];

always @ (A1, A2, posedge CLOCK)
begin
	RD1 <= REGS[A1];
	RD2 <= REGS[A2];
end

always @ (negedge CLOCK)
begin
	if (WE)
	begin
		$display("Reg[%g] = %g", A3, WD);
		REGS[A3] <= WD;
	end
end
endmodule
module Register_File(
	CLOCK,
	A1,
	A2,
	A3,
	RD1,
	RD2,
	WE,
	WD
);

input CLOCK;
input [4:0] A1;
input [4:0] A2;
input [4:0] A3;
output [31:0] RD1;
output [31:0] RD2;
input WE;
input [31:0] WD;

wire CLOCK;
wire [4:0] A1;
wire [4:0] A2;
wire [4:0] A3;
reg [31:0] RD1;
reg [31:0] RD2;
wire WE;
wire [31:0] WD;

reg [31:0] REGS[31:0];

always @ (A1, A2, posedge CLOCK)
begin
	RD1 <= REGS[A1];
	RD2 <= REGS[A2];
end

always @ (negedge CLOCK)
begin
	if (WE)
	begin
		$display("Reg[%g] = %g", A3, WD);
		REGS[A3] <= WD;
	end
end
endmodule