data/full_repos/permissive/163728837/src/cast_ray_tb.v
 line:43: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/163728837/src/cast_ray_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    forever #10 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/163728837/src/cast_ray_tb.v:43: syntax error, unexpected \'@\'\n        repeat(6) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/163728837/src/cast_ray_tb.v:45: syntax error, unexpected \'@\'\n        repeat(2) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/163728837/src/cast_ray_tb.v:59: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/163728837/src/cast_ray_tb.v:61: syntax error, unexpected \'@\'\n        repeat(100) @(posedge clk);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/163728837/src/cast_ray_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #5000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/163728837/src/cast_ray_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #500000000\n        ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cast_ray_tb(
    );

reg clk;
reg rst;

reg [8:0] x;
reg [6:0] turn;

reg [15:0] map_pos_x;
reg [15:0] map_pos_y;

reg start;
wire busy;
wire [23:0] line_height;
wire [7:0] line_color;
wire [6:0] line_tex_x;

cast_ray DUT (
    .clk(clk),
    .rst(rst),
    .x(x),
    .turn(turn),
    .map_pos_x(map_pos_x),
    .map_pos_y(map_pos_y),
    .start(start),
    .busy(busy),
    .line_height(line_height),
    .line_color(line_color),
    .line_tex_x(line_tex_x)
);


	 initial begin
	     clk = 0;
		  forever #10 clk = ~clk;
	 end

    initial begin
        rst = 1'b1;
        repeat(6) @(posedge clk);
        rst = 1'b0;
   	    repeat(2) @(posedge clk);





        x = 9'd30;
        turn = 7'd16;
        map_pos_x = 16'h13_0c;
        map_pos_y = 16'h14_90;
        start = 1'b1;
        @(posedge clk);
        start = 1'b0;
        repeat(100) @(posedge clk);

        #5000
        $finish;
    end

    initial begin
        #500000000
        $finish;
    end
endmodule
module cast_ray_tb(
    );


reg clk;
reg rst;

reg [8:0] x;
reg [6:0] turn;

reg [15:0] map_pos_x;
reg [15:0] map_pos_y;

reg start;
wire busy;
wire [23:0] line_height;
wire [7:0] line_color;
wire [6:0] line_tex_x;

cast_ray DUT (
    .clk(clk),
    .rst(rst),
    .x(x),
    .turn(turn),
    .map_pos_x(map_pos_x),
    .map_pos_y(map_pos_y),
    .start(start),
    .busy(busy),
    .line_height(line_height),
    .line_color(line_color),
    .line_tex_x(line_tex_x)
);


	 initial begin
	     clk = 0;
		  forever #10 clk = ~clk;
	 end

    initial begin
        rst = 1'b1;
        repeat(6) @(posedge clk);
        rst = 1'b0;
   	    repeat(2) @(posedge clk);





        x = 9'd30;
        turn = 7'd16;
        map_pos_x = 16'h13_0c;
        map_pos_y = 16'h14_90;
        start = 1'b1;
        @(posedge clk);
        start = 1'b0;
        repeat(100) @(posedge clk);

        #5000
        $finish;
    end

    initial begin
        #500000000
        $finish;
    end
endmodule