data/full_repos/permissive/122497324/final_project/final_project_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/122497324/final_project/final_project_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/122497324/final_project/final_project_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n      #5;\n      ^\n%Error: data/full_repos/permissive/122497324/final_project/final_project_tb.v:56: Cannot find file containing module: \'cache\'\n  cache make_it_rain\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/122497324/final_project,data/full_repos/permissive/122497324/cache\n             data/full_repos/permissive/122497324/final_project,data/full_repos/permissive/122497324/cache.v\n             data/full_repos/permissive/122497324/final_project,data/full_repos/permissive/122497324/cache.sv\n             cache\n             cache.v\n             cache.sv\n             obj_dir/cache\n             obj_dir/cache.v\n             obj_dir/cache.sv\n%Error: data/full_repos/permissive/122497324/final_project/final_project_tb.v:66: Cannot find file containing module: \'final_project\'\n  final_project #(.CPU_ID(1\'b0)) dut\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/122497324/final_project/final_project_tb.v:74: Cannot find file containing module: \'final_project\'\n  final_project #(.CPU_ID(1\'b1)) dut2\n  ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module final_project_tb();

  reg clk;

  integer num_cycles, i;

  


  wire cache_busy;

  wire [21:0] p0_request, p1_request;

  wire [29:0] data_out;

  




  




  
  cache make_it_rain
  (
    .clk(clk),
    .p0_request(p0_request),
    .p1_request(p1_request),
    .data_out(data_out),
    .is_busy(cache_busy)
  );
  

  final_project #(.CPU_ID(1'b0)) dut
  (
    .clk(clk),
    .cache_request(p0_request),
    .cache_data(data_out),
    .cache_busy(cache_busy)
  );
  
  final_project #(.CPU_ID(1'b1)) dut2
  (
    .clk(clk),
    .cache_request(p1_request),
    .cache_data(data_out),
    .cache_busy(cache_busy)
  );
  
  
  initial begin









    $display("REFRENCE: reservation station IDs:  001=MULT, 010=ADD, 011=ST, 100=LD");
    $display("REFRENCE: execution unit IDs:       001=MULT, 010=ADD, 011=LD/ST");
    $display("REFRENCE: current instruction list: 000=NOP,  001=LD,  010=ST, 011=ADD, 100=MULT, 101=SUBT");
    $display("REFRENCE: the request line:\n processor id (1 bit)\n load-store flag (1 bit) (0=load, 1=store)\n the tag (11 bits)\n the block offset (1 bits)\n the data (8 bits)");
    $display("REFRENCE: the data_out line:\n the processor id (1 bit)\n the request type (load/store) (1 bit)\n the tag (11 bits)\n the block offset (1 bits)\n the data (if a load) (16 bits)");
    

    
    num_cycles = 90;
    for(i=0;i < num_cycles; i= i+1) begin
      clk=0;
      $display ("\nTime=%t,  clk=%b", $realtime, clk);
      #5


      clk=1;
      $display ("\nTime=%t,  clk=%b, cycle=%d", $realtime, clk, i+1);
      #5;
    end
  end
endmodule
module final_project_tb();


  reg clk;

  integer num_cycles, i;

  


  wire cache_busy;

  wire [21:0] p0_request, p1_request;

  wire [29:0] data_out;

  




  




  
  cache make_it_rain
  (
    .clk(clk),
    .p0_request(p0_request),
    .p1_request(p1_request),
    .data_out(data_out),
    .is_busy(cache_busy)
  );
  

  final_project #(.CPU_ID(1'b0)) dut
  (
    .clk(clk),
    .cache_request(p0_request),
    .cache_data(data_out),
    .cache_busy(cache_busy)
  );
  
  final_project #(.CPU_ID(1'b1)) dut2
  (
    .clk(clk),
    .cache_request(p1_request),
    .cache_data(data_out),
    .cache_busy(cache_busy)
  );
  
  
  initial begin









    $display("REFRENCE: reservation station IDs:  001=MULT, 010=ADD, 011=ST, 100=LD");
    $display("REFRENCE: execution unit IDs:       001=MULT, 010=ADD, 011=LD/ST");
    $display("REFRENCE: current instruction list: 000=NOP,  001=LD,  010=ST, 011=ADD, 100=MULT, 101=SUBT");
    $display("REFRENCE: the request line:\n processor id (1 bit)\n load-store flag (1 bit) (0=load, 1=store)\n the tag (11 bits)\n the block offset (1 bits)\n the data (8 bits)");
    $display("REFRENCE: the data_out line:\n the processor id (1 bit)\n the request type (load/store) (1 bit)\n the tag (11 bits)\n the block offset (1 bits)\n the data (if a load) (16 bits)");
    

    
    num_cycles = 90;
    for(i=0;i < num_cycles; i= i+1) begin
      clk=0;
      $display ("\nTime=%t,  clk=%b", $realtime, clk);
      #5


      clk=1;
      $display ("\nTime=%t,  clk=%b, cycle=%d", $realtime, clk, i+1);
      #5;
    end
  end
endmodule