data/full_repos/permissive/173099254/lab4/cod.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/173099254/lab4/cod.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10 A=1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab4/cod.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 B=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab4/cod.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10 Cin0=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab4/cod.v:38: Unsupported: Ignoring delay on this delayed statement.\n #10 A=15; B=12;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab4/cod.v:80: Unsupported: Ignoring delay on this delayed statement.\n #10 A=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab4/cod.v:81: Unsupported: Ignoring delay on this delayed statement.\n #10 B=3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab4/cod.v:127: Unsupported: Ignoring delay on this delayed statement.\n#10 E = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab4/cod.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #10 S= i;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab4/cod.v:163: Unsupported: Ignoring delay on this delayed statement.\n   #10 A = i;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab4/cod.v:169: Unsupported: Ignoring delay on this delayed statement.\n   #10 A = i;\n   ^\n%Warning-MULTITOP: data/full_repos/permissive/173099254/lab4/cod.v:72: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                     : ... Top module \'sumator4_test\'\nmodule sumator4_test();\n       ^~~~~~~~~~~~~\n                                                                     : ... Top module \'comparator_test\'\nmodule comparator_test();\n       ^~~~~~~~~~~~~~~\n                                                                     : ... Top module \'mux4_1_test\'\nmodule mux4_1_test();\n       ^~~~~~~~~~~\n                                                                     : ... Top module \'decodificator_test\'\nmodule decodificator_test();\n       ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab4/cod.v:14: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'Cin0\' generates 1 bits.\n                                                                  : ... In instance sumator4_test.sumator\n  S = A+B+Cin0;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab4/cod.v:19: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'Cin0\' generates 1 bits.\n                                                                  : ... In instance sumator4_test.sumator\n  S=A+B+Cin0;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab4/cod.v:11: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'Cin0\' generates 1 bits.\n                                                                  : ... In instance sumator4_test.sumator\n if(A+B+Cin0 <= 15)\n       ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab4/cod.v:163: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                   : ... In instance decodificator_test\n   #10 A = i;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab4/cod.v:169: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                   : ... In instance decodificator_test\n   #10 A = i;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab4/cod.v:130: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                   : ... In instance mux4_1_test\n  #10 S= i;\n       ^\n%Error: Exiting due to 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decodificator_3(A, E,Y);
output reg [7:0]Y;
input [2:0] A;
input E;

always @(E or A) begin
 if( E == 0)
   Y = 0;
  else
   Y = 2**A;
end
endmodule
module decodificator_3(A, E,Y);

output reg [7:0]Y;
input [2:0] A;
input E;

always @(E or A) begin
 if( E == 0)
   Y = 0;
  else
   Y = 2**A;
end
endmodule