data/full_repos/permissive/115035459/verilog/src/lib/RAM.sv
 line:18: before: "="
1: b'%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/RAM.sv:37: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                 : ... Top module \'RAM_inferred_with_register_outputs\'\nmodule RAM_inferred_with_register_outputs #(\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'RAM_inferred_with_register_inputs\'\nmodule RAM_inferred_with_register_inputs #(\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module RAM_inferred_with_register_inputs #(
	parameter ADDR_WIDTH = 4,
	parameter NUMBER_OF_ADDRESSES = 1<<ADDR_WIDTH,
	parameter DATA_WIDTH = 32
) (
	input reset,
	input [ADDR_WIDTH-1:0] waddr, raddr,
	input [DATA_WIDTH-1:0] din,
	input write_en, wclk, rclk,
	output reg [DATA_WIDTH-1:0] dout = 0,
	input [DATA_WIDTH-1:0] mem_in [NUMBER_OF_ADDRESSES-1:0]
);
	reg [DATA_WIDTH-1:0] mem [NUMBER_OF_ADDRESSES-1:0];
	genvar i;
	always @(posedge wclk) begin
		if (~reset) begin
			if (write_en) begin
				mem[waddr] <= din;
			end else begin
				for (i=0; i<NUMBER_OF_ADDRESSES; i=i+1) begin : write_block
					mem[i] <= mem_in[i];
				end
			end
		end
	end
	always @(posedge rclk) begin
		if (~reset) begin
			dout <= mem[raddr];
		end
	end
endmodule
module RAM_inferred_with_register_inputs #(
	parameter ADDR_WIDTH = 4,
	parameter NUMBER_OF_ADDRESSES = 1<<ADDR_WIDTH,
	parameter DATA_WIDTH = 32
) (
	input reset,
	input [ADDR_WIDTH-1:0] waddr, raddr,
	input [DATA_WIDTH-1:0] din,
	input write_en, wclk, rclk,
	output reg [DATA_WIDTH-1:0] dout = 0,
	input [DATA_WIDTH-1:0] mem_in [NUMBER_OF_ADDRESSES-1:0]
);

	reg [DATA_WIDTH-1:0] mem [NUMBER_OF_ADDRESSES-1:0];
	genvar i;
	always @(posedge wclk) begin
		if (~reset) begin
			if (write_en) begin
				mem[waddr] <= din;
			end else begin
				for (i=0; i<NUMBER_OF_ADDRESSES; i=i+1) begin : write_block
					mem[i] <= mem_in[i];
				end
			end
		end
	end
	always @(posedge rclk) begin
		if (~reset) begin
			dout <= mem[raddr];
		end
	end
endmodule