data/full_repos/permissive/143278/ivltests/pr1115.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1115.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (match0 !== 1\'b1) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   reg[7:0] addr [0:2], pixel;

   wire     match0 = addr[0] == pixel;

   initial begin
      pixel = 1;
      addr[0] = 1;
      addr[1] = 2;
      addr[2] = 3;
      #1 if (match0 !== 1'b1) begin
	 $display("FAILED -- match0 is %b", match0);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module test;


   reg[7:0] addr [0:2], pixel;

   wire     match0 = addr[0] == pixel;

   initial begin
      pixel = 1;
      addr[0] = 1;
      addr[1] = 2;
      addr[2] = 3;
      #1 if (match0 !== 1'b1) begin
	 $display("FAILED -- match0 is %b", match0);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule