data/full_repos/permissive/140358757/snoop_completo/processador.v
None: at end of input
1: b"%Error: data/full_repos/permissive/140358757/snoop_completo/processador.v:47: syntax error, unexpected return, expecting '['\n  parameter return = 2'b11;\n            ^~~~~~\n%Error: data/full_repos/permissive/140358757/snoop_completo/processador.v:113: syntax error, unexpected return, expecting TYPE-IDENTIFIER\n      barout[5:4] = return;\n                    ^~~~~~\n%Error: data/full_repos/permissive/140358757/snoop_completo/processador.v:118: syntax error, unexpected return, expecting TYPE-IDENTIFIER\n    else if(barin[5:4] == return && barout[9:8] == escolhe_processador) begin\n                          ^~~~~~\n%Error: data/full_repos/permissive/140358757/snoop_completo/processador.v:126: syntax error, unexpected end\n   end\n   ^~~\n%Error: Exiting due to 4 error(s)\n"
module processador (inst,barin,clk,escolhe_processador,barout,Cache);
		input [6:0]inst;
		input clk;
		input [1:0]escolhe_processador;
		input [10:0]barin;
		output reg [10:0]barout;

		
		output reg [5:0]Cache = 6'b000000;

		reg writeback;	
		reg alternabus;
		reg alternacpu;
		reg [1:0]ocorrencias;

		
		
		wire [1:0]estado;
		
		parameter exclusive = 2'b10;
		parameter shared  = 2'b01;
		parameter invalid = 2'b00;
		
		parameter read  = 1'b0; 
		parameter write = 1'b1;
		
		parameter readMiss = 2'b01;
		parameter invalidate = 2'b10;
		parameter return = 2'b11;
		
		always @(posedge clk) begin
			alternabus = 0;
			alternacpu = 0;
			barout = 11'b00000000000;
			Cache[5:4] = estado;
			if(inst[6:5] == escolhe_processador) begin
				alternacpu = 1;
				ocorrencias[1] = inst[4];
				if(inst[4] == read && inst[3] == Cache[3] && Cache[5:4] != invalid) begin

					barout[3] = Cache[3];
					barout[2:0] = Cache[2:0];
					ocorrencias[0] = 1;
				end
				else if(inst[4] == read) begin

					barout[9:8] = escolhe_processador;
					barout[5:4] = readMiss;
					barout[3] = inst[3];
					alternacpu = 0;
					if(Cache[5:4] == exclusive) begin
						barout[6] = Cache[3];
						barout[7] = 1;
						barout[2:0] = Cache[2:0];
					end
				end
				else if(inst[4] == write && inst[3] == Cache[3] && Cache[5:4] != invalid) begin 

					Cache[2:0] = inst[2:0];
					ocorrencias[0] = 1;
					if(Cache[5:4] == shared) begin
						barout[9:8] = escolhe_processador;
						barout[5:4] = invalidate;
						barout[3] = Cache[3];
					end
				end
				else if(inst[4] == write) begin 

					if(Cache[5:4] == exclusive) begin
						barout[7] = 1;
						barout[6] = Cache[3];
						barout[2:0] = Cache[2:0];
					end

					ocorrencias[0] = 0;
					barout[9:8] = escolhe_processador;
					barout[5:4] = invalidate;
					barout[3] = inst[3];

					Cache[3] = inst[3];
					Cache[2:0] = inst[2:0];
				end
			end
			else if(barin[5:4]!= 2'b00) begin
if(barin[5:4] == readMiss && barin[3] == Cache[3] && Cache[5:4] != invalid) begin
					if(Cache[5:4] == exclusive) begin
						barout[7] = 1;
						barout[6] = Cache[3];
					end
						barout[10] = 1;
						barout[9:8] = barin[9:8];
						barout[5:4] = return;
						barout[3] = Cache[3];
						barout[2:0] = Cache[2:0];
						Cache[5:4] = shared;
			   end
				else if(barin[5:4] == return && barout[9:8] == escolhe_processador) begin

					if(barout[10] == 1) begin
						Cache[5:4] = shared;
					end
					Cache[3] = barin[3];
					Cache[2:0] = barin[2:0];
				end
			end
		end
	emissor e1(alternacpu,Cache[5:4],ocorrencias[1],ocorrencias[0],clk,estado);
endmodule
module processador (inst,barin,clk,escolhe_processador,barout,Cache);

		input [6:0]inst;
		input clk;
		input [1:0]escolhe_processador;
		input [10:0]barin;
		output reg [10:0]barout;

		
		output reg [5:0]Cache = 6'b000000;

		reg writeback;	
		reg alternabus;
		reg alternacpu;
		reg [1:0]ocorrencias;

		
		
		wire [1:0]estado;
		
		parameter exclusive = 2'b10;
		parameter shared  = 2'b01;
		parameter invalid = 2'b00;
		
		parameter read  = 1'b0; 
		parameter write = 1'b1;
		
		parameter readMiss = 2'b01;
		parameter invalidate = 2'b10;
		parameter return = 2'b11;
		
		always @(posedge clk) begin
			alternabus = 0;
			alternacpu = 0;
			barout = 11'b00000000000;
			Cache[5:4] = estado;
			if(inst[6:5] == escolhe_processador) begin
				alternacpu = 1;
				ocorrencias[1] = inst[4];
				if(inst[4] == read && inst[3] == Cache[3] && Cache[5:4] != invalid) begin

					barout[3] = Cache[3];
					barout[2:0] = Cache[2:0];
					ocorrencias[0] = 1;
				end
				else if(inst[4] == read) begin

					barout[9:8] = escolhe_processador;
					barout[5:4] = readMiss;
					barout[3] = inst[3];
					alternacpu = 0;
					if(Cache[5:4] == exclusive) begin
						barout[6] = Cache[3];
						barout[7] = 1;
						barout[2:0] = Cache[2:0];
					end
				end
				else if(inst[4] == write && inst[3] == Cache[3] && Cache[5:4] != invalid) begin 

					Cache[2:0] = inst[2:0];
					ocorrencias[0] = 1;
					if(Cache[5:4] == shared) begin
						barout[9:8] = escolhe_processador;
						barout[5:4] = invalidate;
						barout[3] = Cache[3];
					end
				end
				else if(inst[4] == write) begin 

					if(Cache[5:4] == exclusive) begin
						barout[7] = 1;
						barout[6] = Cache[3];
						barout[2:0] = Cache[2:0];
					end

					ocorrencias[0] = 0;
					barout[9:8] = escolhe_processador;
					barout[5:4] = invalidate;
					barout[3] = inst[3];

					Cache[3] = inst[3];
					Cache[2:0] = inst[2:0];
				end
			end
			else if(barin[5:4]!= 2'b00) begin
if(barin[5:4] == readMiss && barin[3] == Cache[3] && Cache[5:4] != invalid) begin
					if(Cache[5:4] == exclusive) begin
						barout[7] = 1;
						barout[6] = Cache[3];
					end
						barout[10] = 1;
						barout[9:8] = barin[9:8];
						barout[5:4] = return;
						barout[3] = Cache[3];
						barout[2:0] = Cache[2:0];
						Cache[5:4] = shared;
			   end
				else if(barin[5:4] == return && barout[9:8] == escolhe_processador) begin

					if(barout[10] == 1) begin
						Cache[5:4] = shared;
					end
					Cache[3] = barin[3];
					Cache[2:0] = barin[2:0];
				end
			end
		end
	emissor e1(alternacpu,Cache[5:4],ocorrencias[1],ocorrencias[0],clk,estado);
endmodule