data/full_repos/permissive/135852214/Verilog/mpc_verilog_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/mpc_verilog_sim.v:60: Unsupported: Ignoring delay on this delayed statement.\n always #10 CLK = ~CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/mpc_verilog_sim.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/mpc_verilog_sim.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/mpc_verilog_sim.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: data/full_repos/permissive/135852214/Verilog/mpc_verilog_sim.v:45: Cannot find file containing module: \'mpc_verilog\'\n mpc_verilog uut (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/mpc_verilog\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/mpc_verilog.v\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/mpc_verilog.sv\n             mpc_verilog\n             mpc_verilog.v\n             mpc_verilog.sv\n             obj_dir/mpc_verilog\n             obj_dir/mpc_verilog.v\n             obj_dir/mpc_verilog.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mpc_verilog_sim;


	reg CIN;
	reg CLK;
	reg CTRL_A;
	reg CTRL_ADDR;
	reg CTRL_PC;
	reg [11:0] DATA_IN;
	reg RESET;
	reg WE_A;
	reg WE_B;
	reg WE_PC;


	wire [11:0] ADDR_OUT;
	wire [11:0] DATA_OUT;
	wire OVF;


	mpc_verilog uut (
		.CIN(CIN), 
		.CLK(CLK), 
		.CTRL_A(CTRL_A), 
		.CTRL_ADDR(CTRL_ADDR), 
		.CTRL_PC(CTRL_PC), 
		.DATA_IN(DATA_IN), 
		.RESET(RESET), 
		.WE_A(WE_A), 
		.WE_B(WE_B), 
		.WE_PC(WE_PC), 
		.ADDR_OUT(ADDR_OUT), 
		.DATA_OUT(DATA_OUT), 
		.OVF(OVF)
	);
	always #10 CLK = ~CLK;
	initial begin

		CIN = 0;
		CLK = 0;
		CTRL_A = 0;
		CTRL_ADDR = 0;
		CTRL_PC = 0;
		DATA_IN = 0;
		RESET = 1;
		WE_A = 0;
		WE_B = 0;
		WE_PC = 0;
		

		#100;
      RESET = 0;
		CTRL_A = 1	;
		WE_A = 1;
		DATA_IN = 12'b000000000111;
		#20;
		CTRL_A = 0;
		WE_A = 0;
		WE_B = 1;
		DATA_IN = 12'b000000011001;
		#20;
		CTRL_A = 0;
		WE_A = 1;
		WE_B = 0;
		DATA_IN = 12'b000000011001;
		


	end
      
endmodule
module mpc_verilog_sim;



	reg CIN;
	reg CLK;
	reg CTRL_A;
	reg CTRL_ADDR;
	reg CTRL_PC;
	reg [11:0] DATA_IN;
	reg RESET;
	reg WE_A;
	reg WE_B;
	reg WE_PC;


	wire [11:0] ADDR_OUT;
	wire [11:0] DATA_OUT;
	wire OVF;


	mpc_verilog uut (
		.CIN(CIN), 
		.CLK(CLK), 
		.CTRL_A(CTRL_A), 
		.CTRL_ADDR(CTRL_ADDR), 
		.CTRL_PC(CTRL_PC), 
		.DATA_IN(DATA_IN), 
		.RESET(RESET), 
		.WE_A(WE_A), 
		.WE_B(WE_B), 
		.WE_PC(WE_PC), 
		.ADDR_OUT(ADDR_OUT), 
		.DATA_OUT(DATA_OUT), 
		.OVF(OVF)
	);
	always #10 CLK = ~CLK;
	initial begin

		CIN = 0;
		CLK = 0;
		CTRL_A = 0;
		CTRL_ADDR = 0;
		CTRL_PC = 0;
		DATA_IN = 0;
		RESET = 1;
		WE_A = 0;
		WE_B = 0;
		WE_PC = 0;
		

		#100;
      RESET = 0;
		CTRL_A = 1	;
		WE_A = 1;
		DATA_IN = 12'b000000000111;
		#20;
		CTRL_A = 0;
		WE_A = 0;
		WE_B = 1;
		DATA_IN = 12'b000000011001;
		#20;
		CTRL_A = 0;
		WE_A = 1;
		WE_B = 0;
		DATA_IN = 12'b000000011001;
		


	end
      
endmodule