data/full_repos/permissive/167518838/sources/MBIST_comparator_WF.v
 line:67: before: "assign"
1: b'%Error: data/full_repos/permissive/167518838/sources/MBIST_comparator_WF.v:73: Unsupported: Verilog 1995 deassign\n   deassign comp_data;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/167518838/sources/MBIST_comparator_WF.v:74: Unsupported: Verilog 1995 deassign\n   deassign done;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/167518838/sources/MBIST_comparator_WF.v:75: Unsupported: Verilog 1995 deassign\n   deassign fail;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/167518838/sources/MBIST_comparator_WF.v:76: Unsupported: Verilog 1995 deassign\n   deassign fail_diag;\n   ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MBIST_comparator_write_first (
    reset, comp_en, comp_clk, check, capture, comp_alg_end, data_in, data_out, fail, done
    );
	
	parameter DW = 1;
	
    input reset;
    input comp_en;
	input comp_clk;
	input check;
    input capture;
	input comp_alg_end;
    input [DW:0] data_in;
    input [DW:0] data_out;
	output fail;
	output done;
	
	reg fail_diag;
	reg [DW:0] comp_data;
	reg done;
	reg fail;
	

	always @(reset) begin
		if (reset) begin
			assign comp_data = 0;
			assign done = 0;
			assign fail = 0;
			assign fail_diag = 0;
		end	
		else begin
			deassign comp_data;
			deassign done;
			deassign fail;
			deassign fail_diag;
		end
	end
	

	always @(posedge fail_diag) begin
		if (comp_en) begin
			fail <= 1;
			end
		else begin
			fail <= fail;
		end
	end
	

	always @(posedge comp_alg_end) begin
		if (comp_en) begin
			done <= 1;
			end
		else begin
			done <= done;
		end
	end
	

	always @(posedge comp_clk) begin
		if (comp_en) begin
			if (capture) begin
				comp_data <= data_in;
			end			
		end		
	end
	

	always @(negedge check) begin
		if(comp_en) begin
			if (comp_data == data_out) begin
				fail_diag <= 0;
				end
			else begin
				fail_diag <= 1;
			end
		end
	end				
	
endmodule
module MBIST_comparator_write_first (
    reset, comp_en, comp_clk, check, capture, comp_alg_end, data_in, data_out, fail, done
    );

	
	parameter DW = 1;
	
    input reset;
    input comp_en;
	input comp_clk;
	input check;
    input capture;
	input comp_alg_end;
    input [DW:0] data_in;
    input [DW:0] data_out;
	output fail;
	output done;
	
	reg fail_diag;
	reg [DW:0] comp_data;
	reg done;
	reg fail;
	

	always @(reset) begin
		if (reset) begin
			assign comp_data = 0;
			assign done = 0;
			assign fail = 0;
			assign fail_diag = 0;
		end	
		else begin
			deassign comp_data;
			deassign done;
			deassign fail;
			deassign fail_diag;
		end
	end
	

	always @(posedge fail_diag) begin
		if (comp_en) begin
			fail <= 1;
			end
		else begin
			fail <= fail;
		end
	end
	

	always @(posedge comp_alg_end) begin
		if (comp_en) begin
			done <= 1;
			end
		else begin
			done <= done;
		end
	end
	

	always @(posedge comp_clk) begin
		if (comp_en) begin
			if (capture) begin
				comp_data <= data_in;
			end			
		end		
	end
	

	always @(negedge check) begin
		if(comp_en) begin
			if (comp_data == data_out) begin
				fail_diag <= 0;
				end
			else begin
				fail_diag <= 1;
			end
		end
	end				
	
endmodule