data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v
1: b'%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:1: Cannot find include file: common.vh\n`include "common.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core,data/full_repos/permissive/200650987/common.vh\n             data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core,data/full_repos/permissive/200650987/common.vh.v\n             data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core,data/full_repos/permissive/200650987/common.vh.sv\n             common.vh\n             common.vh.v\n             common.vh.sv\n             obj_dir/common.vh\n             obj_dir/common.vh.v\n             obj_dir/common.vh.sv\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:7: syntax error, unexpected int, expecting IDENTIFIER or \'[\' or do or final\n    input   [5 :0]      int,\n                        ^~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  [31:0]      entryhi,\n    ^~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:44: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [2:0]    config_k0,\n    ^~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:45: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [31:0]   taglo\n    ^~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:46: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:51: syntax error, unexpected assign\n    assign hw_int[5] = int[5] || timer_int;\n    ^~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:56: Define or directive not defined: \'`EXC_MOD\'\n    wire exception_mem = commit_code == `EXC_MOD\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:57: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                      || commit_code == `EXC_TLBL\n                      ^~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:57: Define or directive not defined: \'`EXC_TLBL\'\n                      || commit_code == `EXC_TLBL\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:58: Define or directive not defined: \'`EXC_TLBS\'\n                      || commit_code == `EXC_TLBS\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:59: Define or directive not defined: \'`EXC_ADEL\'\n                      || commit_code == `EXC_ADEL\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:60: Define or directive not defined: \'`EXC_ADES\'\n                      || commit_code == `EXC_ADES;\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:64: Define or directive not defined: \'`TLB_IDXBITS\'\n    reg [`TLB_IDXBITS-1:0] index_index;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:65: syntax error, unexpected assign\n    assign index = (index_p << 31) | index_index;\n    ^~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:67: Define or directive not defined: \'`CP0_INDEX\'\n    wire index_write = mtc0 && addr == `CP0_INDEX;\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:67: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    wire index_write = mtc0 && addr == `CP0_INDEX;\n                                                 ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:71: Define or directive not defined: \'`INDEX_P\'\n        if (tlbp) index_p <= tlbp_index[`INDEX_P];\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:73: Define or directive not defined: \'`INDEX_INDEX\'\n        if (tlbp) index_index <= tlbp_index[`INDEX_INDEX];\n                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:74: Define or directive not defined: \'`INDEX_INDEX\'\n        else if (index_write) index_index <= mtc0_data[`INDEX_INDEX];\n                                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:78: Define or directive not defined: \'`TLB_IDXBITS\'\n    reg [`TLB_IDXBITS-1:0] wired_wired;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:81: Define or directive not defined: \'`CP0_WIRED\'\n    wire wired_write = mtc0 && addr == `CP0_WIRED;\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    wire wired_write = mtc0 && addr == `CP0_WIRED;\n                                                 ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:85: Define or directive not defined: \'`WIRED_WIRED\'\n        else if (wired_write) wired_wired <= mtc0_data[`WIRED_WIRED];\n                                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:89: Define or directive not defined: \'`TLB_IDXBITS\'\n    reg [`TLB_IDXBITS-1:0] random_random;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:90: syntax error, unexpected assign\n    assign random = random_random;\n    ^~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:92: Define or directive not defined: \'`TLB_IDXBITS\'\n    wire [`TLB_IDXBITS-1:0] next_random = random_random + 1\'b1;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:93: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:95: Define or directive not defined: \'`TLB_ENTRIES\'\n        if (!resetn || wired_write) random_random <= `TLB_ENTRIES - 1;\n                                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:106: syntax error, unexpected assign\n    assign entrylo0 = {\n    ^~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:123: Define or directive not defined: \'`CP0_ENTRYLO0\'\n    wire entrylo0_write = mtc0 && addr == `CP0_ENTRYLO0;\n                                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:123: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    wire entrylo0_write = mtc0 && addr == `CP0_ENTRYLO0;\n                                                       ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:124: Define or directive not defined: \'`CP0_ENTRYLO1\'\n    wire entrylo1_write = mtc0 && addr == `CP0_ENTRYLO1;\n                                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:124: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    wire entrylo1_write = mtc0 && addr == `CP0_ENTRYLO1;\n                                                       ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:129: Define or directive not defined: \'`ENTRYLO_PFN\'\n            entrylo0_pfn <= tlbr_lo0[`ENTRYLO_PFN];\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:130: Define or directive not defined: \'`ENTRYLO_C\'\n            entrylo0_c <= tlbr_lo0[`ENTRYLO_C];\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:131: Define or directive not defined: \'`ENTRYLO_D\'\n            entrylo0_d <= tlbr_lo0[`ENTRYLO_D];\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:132: Define or directive not defined: \'`ENTRYLO_V\'\n            entrylo0_v <= tlbr_lo0[`ENTRYLO_V];\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:133: Define or directive not defined: \'`ENTRYLO_G\'\n            entrylo0_g <= tlbr_lo0[`ENTRYLO_G];\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:136: Define or directive not defined: \'`ENTRYLO_PFN\'\n            entrylo0_pfn <= mtc0_data[`ENTRYLO_PFN];\n                                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:137: Define or directive not defined: \'`ENTRYLO_C\'\n            entrylo0_c <= mtc0_data[`ENTRYLO_C];\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:138: Define or directive not defined: \'`ENTRYLO_D\'\n            entrylo0_d <= mtc0_data[`ENTRYLO_D];\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:139: Define or directive not defined: \'`ENTRYLO_V\'\n            entrylo0_v <= mtc0_data[`ENTRYLO_V];\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:140: Define or directive not defined: \'`ENTRYLO_G\'\n            entrylo0_g <= mtc0_data[`ENTRYLO_G];\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:144: Define or directive not defined: \'`ENTRYLO_PFN\'\n            entrylo1_pfn <= tlbr_lo1[`ENTRYLO_PFN];\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:145: Define or directive not defined: \'`ENTRYLO_C\'\n            entrylo1_c <= tlbr_lo1[`ENTRYLO_C];\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:146: Define or directive not defined: \'`ENTRYLO_D\'\n            entrylo1_d <= tlbr_lo1[`ENTRYLO_D];\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:147: Define or directive not defined: \'`ENTRYLO_V\'\n            entrylo1_v <= tlbr_lo1[`ENTRYLO_V];\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:148: Define or directive not defined: \'`ENTRYLO_G\'\n            entrylo1_g <= tlbr_lo1[`ENTRYLO_G];\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/cp0regs.v:151: Define or directive not defined: \'`ENTRYLO_PFN\'\n            entrylo1_pfn <= mtc0_data[`ENTRYLO_PFN];\n                                      ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module cp0regs(
    input               clk,
    input               resetn,
    
    input   [5 :0]      int,
    output              int_sig,
    

    input               mtc0,
    input   [31:0]      mtc0_data,
    output  [31:0]      mfc0_data,
    input   [7 :0]      addr,
    

    input               tlbr,
    input   [31:0]      tlbr_lo0,
    input   [31:0]      tlbr_lo1,
    input   [31:0]      tlbr_hi,
    input   [11:0]      tlbr_mask,
    input               tlbwr,
    input               tlbp,
    input   [31:0]      tlbp_index,
    

    input               commit_exc,
    input   [4 :0]      commit_code,
    input               commit_bd,
    input   [1 :0]      commit_ce,
    input   [31:0]      commit_epc,
    input   [31:0]      commit_bvaddr,
    input               commit_eret,
    
    output  [31:0]      index,
    output  [31:0]      random,
    output  [31:0]      entrylo0,
    output  [31:0]      entrylo1,
    output reg [11:0]   mask,
    output  [31:0]      entryhi,
    output  [31:0]      status,
    output  [31:0]      cause,
    output reg [31:0]   epc,
    output reg [2:0]    config_k0,
    output reg [31:0]   taglo
);

    wire [5:0] hw_int;
    reg timer_int;
    
    assign hw_int[5] = int[5] || timer_int;
    assign hw_int[4:0] = int[4:0];


    wire exception_commit = commit_exc && !commit_eret;
    wire exception_mem = commit_code == `EXC_MOD
                      || commit_code == `EXC_TLBL
                      || commit_code == `EXC_TLBS
                      || commit_code == `EXC_ADEL
                      || commit_code == `EXC_ADES;
    

    reg index_p;
    reg [`TLB_IDXBITS-1:0] index_index;
    assign index = (index_p << 31) | index_index;
    
    wire index_write = mtc0 && addr == `CP0_INDEX;
    always @(posedge clk) begin

        if (!resetn) index_p <= 1'b0;
        if (tlbp) index_p <= tlbp_index[`INDEX_P];

        if (tlbp) index_index <= tlbp_index[`INDEX_INDEX];
        else if (index_write) index_index <= mtc0_data[`INDEX_INDEX];
    end
    

    reg [`TLB_IDXBITS-1:0] wired_wired;
    wire [31:0] wired = wired_wired;
    
    wire wired_write = mtc0 && addr == `CP0_WIRED;
    always @(posedge clk) begin

        if (!resetn) wired_wired <= 0;
        else if (wired_write) wired_wired <= mtc0_data[`WIRED_WIRED];
    end
    

    reg [`TLB_IDXBITS-1:0] random_random;
    assign random = random_random;
    
    wire [`TLB_IDXBITS-1:0] next_random = random_random + 1'b1;
    always @(posedge clk) begin

        if (!resetn || wired_write) random_random <= `TLB_ENTRIES - 1;
        else if (tlbwr) random_random <= next_random < wired_wired ? wired_wired : next_random;
    end
    

    
    reg [19:0] entrylo0_pfn, entrylo1_pfn;
    reg [2:0] entrylo0_c, entrylo1_c;
    reg entrylo0_d, entrylo1_d;
    reg entrylo0_v, entrylo1_v;
    reg entrylo0_g, entrylo1_g;
    assign entrylo0 = {
        6'd0,
        entrylo0_pfn,
        entrylo0_c,
        entrylo0_d,
        entrylo0_v,
        entrylo0_g
    };
    assign entrylo1 = {
        6'd0,
        entrylo1_pfn,
        entrylo1_c,
        entrylo1_d,
        entrylo1_v,
        entrylo1_g
    };
    
    wire entrylo0_write = mtc0 && addr == `CP0_ENTRYLO0;
    wire entrylo1_write = mtc0 && addr == `CP0_ENTRYLO1;
    
    always @(posedge clk) begin

        if (tlbr) begin
            entrylo0_pfn <= tlbr_lo0[`ENTRYLO_PFN];
            entrylo0_c <= tlbr_lo0[`ENTRYLO_C];
            entrylo0_d <= tlbr_lo0[`ENTRYLO_D];
            entrylo0_v <= tlbr_lo0[`ENTRYLO_V];
            entrylo0_g <= tlbr_lo0[`ENTRYLO_G];
        end
        else if (entrylo0_write) begin
            entrylo0_pfn <= mtc0_data[`ENTRYLO_PFN];
            entrylo0_c <= mtc0_data[`ENTRYLO_C];
            entrylo0_d <= mtc0_data[`ENTRYLO_D];
            entrylo0_v <= mtc0_data[`ENTRYLO_V];
            entrylo0_g <= mtc0_data[`ENTRYLO_G];
        end

        if (tlbr) begin
            entrylo1_pfn <= tlbr_lo1[`ENTRYLO_PFN];
            entrylo1_c <= tlbr_lo1[`ENTRYLO_C];
            entrylo1_d <= tlbr_lo1[`ENTRYLO_D];
            entrylo1_v <= tlbr_lo1[`ENTRYLO_V];
            entrylo1_g <= tlbr_lo1[`ENTRYLO_G];
        end
        else if (entrylo1_write) begin
            entrylo1_pfn <= mtc0_data[`ENTRYLO_PFN];
            entrylo1_c <= mtc0_data[`ENTRYLO_C];
            entrylo1_d <= mtc0_data[`ENTRYLO_D];
            entrylo1_v <= mtc0_data[`ENTRYLO_V];
            entrylo1_g <= mtc0_data[`ENTRYLO_G];
        end
    end
    

    
    reg [8:0] context_ptebase;
    reg [18:0] context_badvpn2;
    
    wire [31:0] context = {
        context_ptebase,
        context_badvpn2,
        4'd0
    };
    
    wire context_write = mtc0 && addr == `CP0_CONTEXT;
    
    always @(posedge clk) begin

        if (context_write) context_ptebase <= mtc0_data[`CONTEXT_PTEBASE];

        if (exception_commit && exception_mem) context_badvpn2 <= commit_bvaddr[31:13];
    end
    

    wire [31:0] pagemask = {
        8'd0,
        mask,
        13'd0
    };
    
    wire pagemask_write = mtc0 && addr == `CP0_PAGEMASK;
    always @(posedge clk) begin
        if (tlbr) mask <= tlbr_mask;
        else if (pagemask_write) mask <= mtc0_data[`PAGEMASK_MASK];
    end
    

    reg [31:0] badvaddr;
    always @(posedge clk) begin
        if (exception_commit && exception_mem) badvaddr <= commit_bvaddr;
    end
    

    reg [31:0] count;
    reg tick;
    
    wire count_write = mtc0 && addr == `CP0_COUNT;
    always @(posedge clk) begin
        if (!resetn) tick <= 1'b0;
        else tick <= ~tick;

        if (count_write) count <= mtc0_data;
        else if (tick) count <= count + 32'd1;
    end
    

    reg [18:0] entryhi_vpn2;
    reg [7:0] entryhi_asid;
    assign entryhi = {
        entryhi_vpn2,
        5'd0,
        entryhi_asid
    };
    
    wire entryhi_write = mtc0 && addr == `CP0_ENTRYHI;
    always @(posedge clk) begin

        if (exception_commit && exception_mem) entryhi_vpn2 <= commit_bvaddr[`ENTRYHI_VPN2];
        else if (tlbr) entryhi_vpn2 <= tlbr_hi[`ENTRYHI_VPN2];
        else if (entryhi_write) entryhi_vpn2 <= mtc0_data[`ENTRYHI_VPN2];

        if (!resetn) entryhi_asid <= 0;
        if (tlbr) entryhi_asid <= tlbr_hi[`ENTRYHI_ASID];
        else if (entryhi_write) entryhi_asid <= mtc0_data[`ENTRYHI_ASID];
    end
    

    reg [31:0] compare;
    
    wire compare_write = mtc0 && addr == `CP0_COMPARE;
    always @(posedge clk) begin
        if (compare_write) compare <= mtc0_data;
    end
    

    reg status_cu0;
    reg status_bev;
    reg [7:0] status_im;
    reg status_um;
    reg status_exl;
    reg status_ie;
    assign status = {
        3'd0,
        status_cu0,
        5'd0,
        status_bev,
        6'd0,
        status_im,
        3'd0,
        status_um,
        1'b0,
        1'b0,
        status_exl,
        status_ie
    };
    
    wire status_write = mtc0 && addr == `CP0_STATUS;
    always @(posedge clk) begin

        if (!resetn) status_cu0 <= 1'b0;
        else if (status_write) status_cu0 <= mtc0_data[`STATUS_CU0];

        if (!resetn) status_bev <= 1'b1;
        else if (status_write) status_bev <= mtc0_data[`STATUS_BEV];

        if (!resetn) status_im <= 8'd0;
        else if (status_write) status_im <= mtc0_data[`STATUS_IM];

        if (!resetn) status_um <= 1'b0;
        else if (status_write) status_um <= mtc0_data[`STATUS_UM];

        if (!resetn) status_exl <= 1'b0;
        else if (commit_exc) status_exl <= !commit_eret;
        else if (status_write) status_exl <= mtc0_data[`STATUS_EXL];

        if (!resetn) status_ie <= 1'b0;
        else if (status_write) status_ie <= mtc0_data[`STATUS_IE];
    end
    

    reg cause_bd;
    reg cause_ti;
    reg [1:0] cause_ce;
    reg cause_iv;
    reg [5:0] cause_ip7_2;
    reg [1:0] cause_ip1_0;
    reg [4:0] cause_exccode;
    assign cause = {
        cause_bd,
        cause_ti,
        cause_ce,
        4'd0,
        cause_iv,
        7'd0,
        cause_ip7_2,
        cause_ip1_0,
        1'd0,
        cause_exccode,
        2'd0
    };
    
    wire cause_write = mtc0 && addr == `CP0_CAUSE;
    always @(posedge clk) begin

        if (!resetn) cause_bd <= 1'b0;
        else if (exception_commit && !status_exl) cause_bd <= commit_bd;

        if (!resetn) cause_ti <= 1'b0;
        else cause_ti <= timer_int;

        if (!resetn) cause_ce <= 2'd0;
        else if (exception_commit) cause_ce <= commit_ce;

        if (!resetn) cause_iv <= 1'b0;
        else if (cause_write) cause_iv <= mtc0_data[`CAUSE_IV];

        cause_ip7_2 <= hw_int;
        if (!resetn) cause_ip1_0 <= 2'd0;
        else if (cause_write) cause_ip1_0 <= mtc0_data[`CAUSE_IP1_0];

        if (!resetn) cause_exccode <= 5'd0;
        else if (exception_commit) cause_exccode <= commit_code;
    end
    

    wire epc_write = mtc0 && addr == `CP0_EPC;
    always @(posedge clk) begin
        if (epc_write) epc <= mtc0_data;
        else if (exception_commit && !status_exl) epc <= commit_epc;
    end
    

    wire [31:0] prid = 32'h00004220;
    

    wire [31:0] config0 = {
        1'b1,
        3'd0,
        3'd0,
        9'd0,
        1'b0,
        2'd0,
        3'd0,
        3'd1,
        3'd0,
        1'b0,
        config_k0
    };
    
    wire config_write = mtc0 && addr == `CP0_CONFIG;
    always @(posedge clk) begin
        if (!resetn) config_k0 <= 3'd3;
        else if (config_write) config_k0 <= mtc0_data[`CONFIG_K0];
    end
    

    wire [31:0] config1 = {
        1'b0,
        6'd31,
        3'd1,
        3'd4,
        3'd3,
        3'd1,
        3'd4,
        3'd1,
        1'b0,
        1'b0,
        1'b0,
        1'b0,
        1'b0,
        1'b0,
        1'b0
    };
    

    wire taglo_write = mtc0 && addr == `CP0_TAGLO;
    always @(posedge clk) begin
        if (taglo_write) taglo <= mtc0_data;
    end
    

    always @(posedge clk) begin
        if (!resetn) timer_int <= 1'b0;
        else if (compare_write) timer_int <= 1'b0;
        else if (count == compare) timer_int <= 1'b1;
    end
    
    assign int_sig = {cause_ip7_2, cause_ip1_0} & status_im && !status_exl && status_ie;
    
    assign mfc0_data =
        {32{addr == `CP0_INDEX      }} & index      |
        {32{addr == `CP0_RANDOM     }} & random     |
        {32{addr == `CP0_ENTRYLO0   }} & entrylo0   |
        {32{addr == `CP0_ENTRYLO1   }} & entrylo1   |
        {32{addr == `CP0_CONTEXT    }} & context    |
        {32{addr == `CP0_PAGEMASK   }} & pagemask   |
        {32{addr == `CP0_WIRED      }} & wired      |
        {32{addr == `CP0_BADVADDR   }} & badvaddr   |
        {32{addr == `CP0_COUNT      }} & count      |
        {32{addr == `CP0_ENTRYHI    }} & entryhi    |
        {32{addr == `CP0_COMPARE    }} & compare    |
        {32{addr == `CP0_STATUS     }} & status     |
        {32{addr == `CP0_CAUSE      }} & cause      |
        {32{addr == `CP0_EPC        }} & epc        |
        {32{addr == `CP0_PRID       }} & prid       |
        {32{addr == `CP0_CONFIG     }} & config0    |
        {32{addr == `CP0_CONFIG1    }} & config1    |
        {32{addr == `CP0_TAGLO      }} & taglo      ;
    
endmodule
module cp0regs(
    input               clk,
    input               resetn,
    
    input   [5 :0]      int,
    output              int_sig,
    

    input               mtc0,
    input   [31:0]      mtc0_data,
    output  [31:0]      mfc0_data,
    input   [7 :0]      addr,
    

    input               tlbr,
    input   [31:0]      tlbr_lo0,
    input   [31:0]      tlbr_lo1,
    input   [31:0]      tlbr_hi,
    input   [11:0]      tlbr_mask,
    input               tlbwr,
    input               tlbp,
    input   [31:0]      tlbp_index,
    

    input               commit_exc,
    input   [4 :0]      commit_code,
    input               commit_bd,
    input   [1 :0]      commit_ce,
    input   [31:0]      commit_epc,
    input   [31:0]      commit_bvaddr,
    input               commit_eret,
    
    output  [31:0]      index,
    output  [31:0]      random,
    output  [31:0]      entrylo0,
    output  [31:0]      entrylo1,
    output reg [11:0]   mask,
    output  [31:0]      entryhi,
    output  [31:0]      status,
    output  [31:0]      cause,
    output reg [31:0]   epc,
    output reg [2:0]    config_k0,
    output reg [31:0]   taglo
);


    wire [5:0] hw_int;
    reg timer_int;
    
    assign hw_int[5] = int[5] || timer_int;
    assign hw_int[4:0] = int[4:0];


    wire exception_commit = commit_exc && !commit_eret;
    wire exception_mem = commit_code == `EXC_MOD
                      || commit_code == `EXC_TLBL
                      || commit_code == `EXC_TLBS
                      || commit_code == `EXC_ADEL
                      || commit_code == `EXC_ADES;
    

    reg index_p;
    reg [`TLB_IDXBITS-1:0] index_index;
    assign index = (index_p << 31) | index_index;
    
    wire index_write = mtc0 && addr == `CP0_INDEX;
    always @(posedge clk) begin

        if (!resetn) index_p <= 1'b0;
        if (tlbp) index_p <= tlbp_index[`INDEX_P];

        if (tlbp) index_index <= tlbp_index[`INDEX_INDEX];
        else if (index_write) index_index <= mtc0_data[`INDEX_INDEX];
    end
    

    reg [`TLB_IDXBITS-1:0] wired_wired;
    wire [31:0] wired = wired_wired;
    
    wire wired_write = mtc0 && addr == `CP0_WIRED;
    always @(posedge clk) begin

        if (!resetn) wired_wired <= 0;
        else if (wired_write) wired_wired <= mtc0_data[`WIRED_WIRED];
    end
    

    reg [`TLB_IDXBITS-1:0] random_random;
    assign random = random_random;
    
    wire [`TLB_IDXBITS-1:0] next_random = random_random + 1'b1;
    always @(posedge clk) begin

        if (!resetn || wired_write) random_random <= `TLB_ENTRIES - 1;
        else if (tlbwr) random_random <= next_random < wired_wired ? wired_wired : next_random;
    end
    

    
    reg [19:0] entrylo0_pfn, entrylo1_pfn;
    reg [2:0] entrylo0_c, entrylo1_c;
    reg entrylo0_d, entrylo1_d;
    reg entrylo0_v, entrylo1_v;
    reg entrylo0_g, entrylo1_g;
    assign entrylo0 = {
        6'd0,
        entrylo0_pfn,
        entrylo0_c,
        entrylo0_d,
        entrylo0_v,
        entrylo0_g
    };
    assign entrylo1 = {
        6'd0,
        entrylo1_pfn,
        entrylo1_c,
        entrylo1_d,
        entrylo1_v,
        entrylo1_g
    };
    
    wire entrylo0_write = mtc0 && addr == `CP0_ENTRYLO0;
    wire entrylo1_write = mtc0 && addr == `CP0_ENTRYLO1;
    
    always @(posedge clk) begin

        if (tlbr) begin
            entrylo0_pfn <= tlbr_lo0[`ENTRYLO_PFN];
            entrylo0_c <= tlbr_lo0[`ENTRYLO_C];
            entrylo0_d <= tlbr_lo0[`ENTRYLO_D];
            entrylo0_v <= tlbr_lo0[`ENTRYLO_V];
            entrylo0_g <= tlbr_lo0[`ENTRYLO_G];
        end
        else if (entrylo0_write) begin
            entrylo0_pfn <= mtc0_data[`ENTRYLO_PFN];
            entrylo0_c <= mtc0_data[`ENTRYLO_C];
            entrylo0_d <= mtc0_data[`ENTRYLO_D];
            entrylo0_v <= mtc0_data[`ENTRYLO_V];
            entrylo0_g <= mtc0_data[`ENTRYLO_G];
        end

        if (tlbr) begin
            entrylo1_pfn <= tlbr_lo1[`ENTRYLO_PFN];
            entrylo1_c <= tlbr_lo1[`ENTRYLO_C];
            entrylo1_d <= tlbr_lo1[`ENTRYLO_D];
            entrylo1_v <= tlbr_lo1[`ENTRYLO_V];
            entrylo1_g <= tlbr_lo1[`ENTRYLO_G];
        end
        else if (entrylo1_write) begin
            entrylo1_pfn <= mtc0_data[`ENTRYLO_PFN];
            entrylo1_c <= mtc0_data[`ENTRYLO_C];
            entrylo1_d <= mtc0_data[`ENTRYLO_D];
            entrylo1_v <= mtc0_data[`ENTRYLO_V];
            entrylo1_g <= mtc0_data[`ENTRYLO_G];
        end
    end
    

    
    reg [8:0] context_ptebase;
    reg [18:0] context_badvpn2;
    
    wire [31:0] context = {
        context_ptebase,
        context_badvpn2,
        4'd0
    };
    
    wire context_write = mtc0 && addr == `CP0_CONTEXT;
    
    always @(posedge clk) begin

        if (context_write) context_ptebase <= mtc0_data[`CONTEXT_PTEBASE];

        if (exception_commit && exception_mem) context_badvpn2 <= commit_bvaddr[31:13];
    end
    

    wire [31:0] pagemask = {
        8'd0,
        mask,
        13'd0
    };
    
    wire pagemask_write = mtc0 && addr == `CP0_PAGEMASK;
    always @(posedge clk) begin
        if (tlbr) mask <= tlbr_mask;
        else if (pagemask_write) mask <= mtc0_data[`PAGEMASK_MASK];
    end
    

    reg [31:0] badvaddr;
    always @(posedge clk) begin
        if (exception_commit && exception_mem) badvaddr <= commit_bvaddr;
    end
    

    reg [31:0] count;
    reg tick;
    
    wire count_write = mtc0 && addr == `CP0_COUNT;
    always @(posedge clk) begin
        if (!resetn) tick <= 1'b0;
        else tick <= ~tick;

        if (count_write) count <= mtc0_data;
        else if (tick) count <= count + 32'd1;
    end
    

    reg [18:0] entryhi_vpn2;
    reg [7:0] entryhi_asid;
    assign entryhi = {
        entryhi_vpn2,
        5'd0,
        entryhi_asid
    };
    
    wire entryhi_write = mtc0 && addr == `CP0_ENTRYHI;
    always @(posedge clk) begin

        if (exception_commit && exception_mem) entryhi_vpn2 <= commit_bvaddr[`ENTRYHI_VPN2];
        else if (tlbr) entryhi_vpn2 <= tlbr_hi[`ENTRYHI_VPN2];
        else if (entryhi_write) entryhi_vpn2 <= mtc0_data[`ENTRYHI_VPN2];

        if (!resetn) entryhi_asid <= 0;
        if (tlbr) entryhi_asid <= tlbr_hi[`ENTRYHI_ASID];
        else if (entryhi_write) entryhi_asid <= mtc0_data[`ENTRYHI_ASID];
    end
    

    reg [31:0] compare;
    
    wire compare_write = mtc0 && addr == `CP0_COMPARE;
    always @(posedge clk) begin
        if (compare_write) compare <= mtc0_data;
    end
    

    reg status_cu0;
    reg status_bev;
    reg [7:0] status_im;
    reg status_um;
    reg status_exl;
    reg status_ie;
    assign status = {
        3'd0,
        status_cu0,
        5'd0,
        status_bev,
        6'd0,
        status_im,
        3'd0,
        status_um,
        1'b0,
        1'b0,
        status_exl,
        status_ie
    };
    
    wire status_write = mtc0 && addr == `CP0_STATUS;
    always @(posedge clk) begin

        if (!resetn) status_cu0 <= 1'b0;
        else if (status_write) status_cu0 <= mtc0_data[`STATUS_CU0];

        if (!resetn) status_bev <= 1'b1;
        else if (status_write) status_bev <= mtc0_data[`STATUS_BEV];

        if (!resetn) status_im <= 8'd0;
        else if (status_write) status_im <= mtc0_data[`STATUS_IM];

        if (!resetn) status_um <= 1'b0;
        else if (status_write) status_um <= mtc0_data[`STATUS_UM];

        if (!resetn) status_exl <= 1'b0;
        else if (commit_exc) status_exl <= !commit_eret;
        else if (status_write) status_exl <= mtc0_data[`STATUS_EXL];

        if (!resetn) status_ie <= 1'b0;
        else if (status_write) status_ie <= mtc0_data[`STATUS_IE];
    end
    

    reg cause_bd;
    reg cause_ti;
    reg [1:0] cause_ce;
    reg cause_iv;
    reg [5:0] cause_ip7_2;
    reg [1:0] cause_ip1_0;
    reg [4:0] cause_exccode;
    assign cause = {
        cause_bd,
        cause_ti,
        cause_ce,
        4'd0,
        cause_iv,
        7'd0,
        cause_ip7_2,
        cause_ip1_0,
        1'd0,
        cause_exccode,
        2'd0
    };
    
    wire cause_write = mtc0 && addr == `CP0_CAUSE;
    always @(posedge clk) begin

        if (!resetn) cause_bd <= 1'b0;
        else if (exception_commit && !status_exl) cause_bd <= commit_bd;

        if (!resetn) cause_ti <= 1'b0;
        else cause_ti <= timer_int;

        if (!resetn) cause_ce <= 2'd0;
        else if (exception_commit) cause_ce <= commit_ce;

        if (!resetn) cause_iv <= 1'b0;
        else if (cause_write) cause_iv <= mtc0_data[`CAUSE_IV];

        cause_ip7_2 <= hw_int;
        if (!resetn) cause_ip1_0 <= 2'd0;
        else if (cause_write) cause_ip1_0 <= mtc0_data[`CAUSE_IP1_0];

        if (!resetn) cause_exccode <= 5'd0;
        else if (exception_commit) cause_exccode <= commit_code;
    end
    

    wire epc_write = mtc0 && addr == `CP0_EPC;
    always @(posedge clk) begin
        if (epc_write) epc <= mtc0_data;
        else if (exception_commit && !status_exl) epc <= commit_epc;
    end
    

    wire [31:0] prid = 32'h00004220;
    

    wire [31:0] config0 = {
        1'b1,
        3'd0,
        3'd0,
        9'd0,
        1'b0,
        2'd0,
        3'd0,
        3'd1,
        3'd0,
        1'b0,
        config_k0
    };
    
    wire config_write = mtc0 && addr == `CP0_CONFIG;
    always @(posedge clk) begin
        if (!resetn) config_k0 <= 3'd3;
        else if (config_write) config_k0 <= mtc0_data[`CONFIG_K0];
    end
    

    wire [31:0] config1 = {
        1'b0,
        6'd31,
        3'd1,
        3'd4,
        3'd3,
        3'd1,
        3'd4,
        3'd1,
        1'b0,
        1'b0,
        1'b0,
        1'b0,
        1'b0,
        1'b0,
        1'b0
    };
    

    wire taglo_write = mtc0 && addr == `CP0_TAGLO;
    always @(posedge clk) begin
        if (taglo_write) taglo <= mtc0_data;
    end
    

    always @(posedge clk) begin
        if (!resetn) timer_int <= 1'b0;
        else if (compare_write) timer_int <= 1'b0;
        else if (count == compare) timer_int <= 1'b1;
    end
    
    assign int_sig = {cause_ip7_2, cause_ip1_0} & status_im && !status_exl && status_ie;
    
    assign mfc0_data =
        {32{addr == `CP0_INDEX      }} & index      |
        {32{addr == `CP0_RANDOM     }} & random     |
        {32{addr == `CP0_ENTRYLO0   }} & entrylo0   |
        {32{addr == `CP0_ENTRYLO1   }} & entrylo1   |
        {32{addr == `CP0_CONTEXT    }} & context    |
        {32{addr == `CP0_PAGEMASK   }} & pagemask   |
        {32{addr == `CP0_WIRED      }} & wired      |
        {32{addr == `CP0_BADVADDR   }} & badvaddr   |
        {32{addr == `CP0_COUNT      }} & count      |
        {32{addr == `CP0_ENTRYHI    }} & entryhi    |
        {32{addr == `CP0_COMPARE    }} & compare    |
        {32{addr == `CP0_STATUS     }} & status     |
        {32{addr == `CP0_CAUSE      }} & cause      |
        {32{addr == `CP0_EPC        }} & epc        |
        {32{addr == `CP0_PRID       }} & prid       |
        {32{addr == `CP0_CONFIG     }} & config0    |
        {32{addr == `CP0_CONFIG1    }} & config1    |
        {32{addr == `CP0_TAGLO      }} & taglo      ;
    
endmodule