data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_out_v3.v
1: b'%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_out_v3.v:92: Cannot find file containing module: \'dviPLL4\'\n dviPLL4 PLL(clk_i,    \n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/dviPLL4\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/dviPLL4.v\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/dviPLL4.sv\n             dviPLL4\n             dviPLL4.v\n             dviPLL4.sv\n             obj_dir/dviPLL4\n             obj_dir/dviPLL4.v\n             obj_dir/dviPLL4.sv\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_out_v3.v:187: Operator NEQ expects 11 bits on the RHS, but RHS\'s VARREF \'COLUMNS\' generates 10 bits.\n                                                                                                                    : ... In instance VIDEO_OUT3\n     if( column != COLUMNS )\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_out_v3.v:185: Operator NEQ expects 11 bits on the RHS, but RHS\'s VARREF \'LINES\' generates 10 bits.\n                                                                                                                    : ... In instance VIDEO_OUT3\n    if( line != LINES )\n             ^~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module VIDEO_OUT3
(	
	input	wire clk_i,
	input wire rst_i,

	input wire [383:0] doutb_bram3_i,
	output reg [6:0] addrb_bram3_o,
	output wire clkb_bram3_o,

	input wire full_i,
	input wire video_ACK_i,
	input wire VLD_VIDEO_i,
	input wire vld_mem_i,
	output reg empty_o,

	output reg [11:0] vga_d_o,
	output reg vga_de_o,
	output reg vga_hsync_o,
	output reg vga_vsync_o,
	output wire x_clk_p_o,
	output wire x_clk_n_o,

	input wire [9 :0] H_FP,H_BP,H_sync,H_VldDat,COLUMNS,
	input wire [9 :0] V_FP,V_BP,V_sync,V_VldDat,LINES,
	input wire H_active,V_active,
	input wire [23:0] Color,
	input wire [9:0] HighLine,LowLine,HighCol,LowCol,
	input wire VideoInputActive);
	

	localparam 	color_background	= 12'hFFF;
	localparam 	LowLineProc			= 11'd195,
					HighLineProc		= 11'd323,
					LowColProc			= 11'd455,
					HighColProc			= 11'd583;
	

	reg 			temp_col;
	reg [10:0] 	column, line;
	reg [383:0] row2display, shift_reg;
	reg 			readLineProc, readColProc; 
	

	wire 			ALL_VLD, LOCKED_OUT;
	wire 			clk2_ph0_i, clk2_ph2_i, data_clk;
	

	dviPLL4 PLL(clk_i,
					rst_i, 
					clk2_ph0_i,
					data_clk,
					clk2_ph2_i,
					LOCKED_OUT);
	


	assign x_clk_p_o			= clk2_ph0_i;		
	assign x_clk_n_o 			= clk2_ph2_i;
	assign ALL_VLD 			= (VideoInputActive)?LOCKED_OUT & VLD_VIDEO_i & video_ACK_i & vld_mem_i : LOCKED_OUT & video_ACK_i;
	assign clkb_bram3_o 		= ~vga_hsync_o; 



	always @(negedge clkb_bram3_o or posedge rst_i) 
	begin
		if(rst_i)
		begin
			addrb_bram3_o	<= 0;
			empty_o			<= 1;
		end
		else
		begin
			if( ALL_VLD )
			begin
				if( full_i )
				begin
					empty_o	<= 0;
				end
				else
				begin
					if( readLineProc )
					begin
						if( addrb_bram3_o != 7'd126 )
						begin
							empty_o			<= 1'b0;
							addrb_bram3_o	<= addrb_bram3_o+1'b1;
						end
						else
						begin
							empty_o	<= 1'b1;
						end
					end
					else
					begin
						if( ~vga_vsync_o && addrb_bram3_o == 7'd126)
						begin
							empty_o			<= 1'b1;
							addrb_bram3_o	<= 0;
						end
					end
				end
			end
		end
	end
	

	always @(negedge clkb_bram3_o or posedge rst_i)
	begin
		if(rst_i)
		begin
			row2display	<= 0;
		end
		else
		begin
			if( ALL_VLD )
			begin
				if( empty_o == 1'b0 && readLineProc )
				begin
					row2display	<= doutb_bram3_i;
				end			
				else row2display	<= 0;			
			end	
		end
	end


	always @(posedge x_clk_p_o or posedge rst_i)
	begin
		if(rst_i)
		begin
			temp_col			<= 1'b0;
			column			<= 0;
			line				<= 0;
			readLineProc	<= 1'b0;
			readColProc		<= 1'b0;
		end
		else
		begin
			if( ALL_VLD )
			begin
				if( line != LINES )
				begin
					if( column != COLUMNS )
					begin
						temp_col	<= temp_col + 1;
						if( temp_col == 1'b1 )
						begin
							column	<= column + 1'b1;
							temp_col	<= 1'b0;
						end
					end
					else
					begin
						line		<= line + 1'b1;
						column	<= 0;
					end	
				end
				else 
				begin
					line		<= 0;
					column	<= 0;	
				end

				if( line == LowLineProc ) readLineProc	<= 1'b1;
				else if( line == HighLineProc ) readLineProc	<= 1'b0;
				
				if( column == LowColProc ) readColProc	<= 1'b1;
				else if( column == HighColProc ) readColProc	<= 1'b0;
				
			end		
		end
	end
	

	always @(negedge data_clk or posedge rst_i)
	begin
		if(rst_i)
		begin
			vga_hsync_o		<= ~H_active;
			vga_vsync_o		<= ~V_active;
			vga_de_o			<= 1'b0;
			vga_d_o			<= 12'h000;
			shift_reg		=  0;
		end
		else
		begin
			if(ALL_VLD)
			begin

				if( vga_de_o )
				begin
					if( VideoInputActive )
					begin
						if( readLineProc ) 
						begin
							if( readColProc ) 
								begin
								if( temp_col ) 
								begin
									vga_d_o[11:7]		<= { shift_reg[383],4'b1001 };
									vga_d_o[6:4]		<= { shift_reg[382],2'b10 };
									vga_d_o[3:1]		<= 3'b111;
									vga_d_o[0]			<= 1'b1;
								end
								else
								begin
									vga_d_o[11:9]		<= 3'b011;
									vga_d_o[8:4]		<= {shift_reg[381],4'b1001};
									vga_d_o[3]			<= 1'b1;
									vga_d_o[2:0]		<= 3'b111;
									
									shift_reg[383:3]	 =  shift_reg[380:0];
									shift_reg[2:0]		 =  3'b000;	
								end
							end
							else vga_d_o<=color_background;
						end
						else vga_d_o<=color_background;
					end
					else
					begin
						if( line>(V_FP+V_BP+V_sync+LowLine-1) && line <= (V_FP+V_BP+V_sync+HighLine) )
						begin
							if( column>(H_FP+H_BP+H_sync+LowCol) && column<= (H_FP+H_BP+H_sync+HighCol) )
							begin
								if( temp_col ) vga_d_o<=Color[11:0]; 
								else  vga_d_o<=Color[23:12];
							end
							else vga_d_o<=color_background;
						end
						else
						begin
							vga_d_o<=color_background;
						end
					end	
				end
				else
				begin
					vga_d_o<=12'h000;
				end
			

				if(~vga_hsync_o)
				begin
					shift_reg=row2display;
				end
				

				if(line >(V_FP-1+ V_sync+V_BP))
				begin
					if(column>(H_FP+H_BP+H_sync))	vga_de_o<=1'b1; 					
					else vga_de_o<=1'b0;	
				end
				else vga_de_o<=1'b0;
				

				if(column>(H_FP-1) && column<(H_FP+H_sync) ) vga_hsync_o<=H_active; 
				else vga_hsync_o<=~H_active;	
				

				if(line>(V_FP-1) && line<(V_FP+V_sync))
				begin 
					vga_vsync_o<=V_active; 
				end
				else vga_vsync_o<=~V_active;
			end
			else
			begin
				vga_hsync_o<=~H_active;
				vga_vsync_o<=~V_active;
				vga_de_o<=1'b0;
				vga_d_o<=12'h000;
				shift_reg=0;
			end
		end
	end
endmodule
module VIDEO_OUT3
(	
	input	wire clk_i,
	input wire rst_i,

	input wire [383:0] doutb_bram3_i,
	output reg [6:0] addrb_bram3_o,
	output wire clkb_bram3_o,

	input wire full_i,
	input wire video_ACK_i,
	input wire VLD_VIDEO_i,
	input wire vld_mem_i,
	output reg empty_o,

	output reg [11:0] vga_d_o,
	output reg vga_de_o,
	output reg vga_hsync_o,
	output reg vga_vsync_o,
	output wire x_clk_p_o,
	output wire x_clk_n_o,

	input wire [9 :0] H_FP,H_BP,H_sync,H_VldDat,COLUMNS,
	input wire [9 :0] V_FP,V_BP,V_sync,V_VldDat,LINES,
	input wire H_active,V_active,
	input wire [23:0] Color,
	input wire [9:0] HighLine,LowLine,HighCol,LowCol,
	input wire VideoInputActive);

	

	localparam 	color_background	= 12'hFFF;
	localparam 	LowLineProc			= 11'd195,
					HighLineProc		= 11'd323,
					LowColProc			= 11'd455,
					HighColProc			= 11'd583;
	

	reg 			temp_col;
	reg [10:0] 	column, line;
	reg [383:0] row2display, shift_reg;
	reg 			readLineProc, readColProc; 
	

	wire 			ALL_VLD, LOCKED_OUT;
	wire 			clk2_ph0_i, clk2_ph2_i, data_clk;
	

	dviPLL4 PLL(clk_i,
					rst_i, 
					clk2_ph0_i,
					data_clk,
					clk2_ph2_i,
					LOCKED_OUT);
	


	assign x_clk_p_o			= clk2_ph0_i;		
	assign x_clk_n_o 			= clk2_ph2_i;
	assign ALL_VLD 			= (VideoInputActive)?LOCKED_OUT & VLD_VIDEO_i & video_ACK_i & vld_mem_i : LOCKED_OUT & video_ACK_i;
	assign clkb_bram3_o 		= ~vga_hsync_o; 



	always @(negedge clkb_bram3_o or posedge rst_i) 
	begin
		if(rst_i)
		begin
			addrb_bram3_o	<= 0;
			empty_o			<= 1;
		end
		else
		begin
			if( ALL_VLD )
			begin
				if( full_i )
				begin
					empty_o	<= 0;
				end
				else
				begin
					if( readLineProc )
					begin
						if( addrb_bram3_o != 7'd126 )
						begin
							empty_o			<= 1'b0;
							addrb_bram3_o	<= addrb_bram3_o+1'b1;
						end
						else
						begin
							empty_o	<= 1'b1;
						end
					end
					else
					begin
						if( ~vga_vsync_o && addrb_bram3_o == 7'd126)
						begin
							empty_o			<= 1'b1;
							addrb_bram3_o	<= 0;
						end
					end
				end
			end
		end
	end
	

	always @(negedge clkb_bram3_o or posedge rst_i)
	begin
		if(rst_i)
		begin
			row2display	<= 0;
		end
		else
		begin
			if( ALL_VLD )
			begin
				if( empty_o == 1'b0 && readLineProc )
				begin
					row2display	<= doutb_bram3_i;
				end			
				else row2display	<= 0;			
			end	
		end
	end


	always @(posedge x_clk_p_o or posedge rst_i)
	begin
		if(rst_i)
		begin
			temp_col			<= 1'b0;
			column			<= 0;
			line				<= 0;
			readLineProc	<= 1'b0;
			readColProc		<= 1'b0;
		end
		else
		begin
			if( ALL_VLD )
			begin
				if( line != LINES )
				begin
					if( column != COLUMNS )
					begin
						temp_col	<= temp_col + 1;
						if( temp_col == 1'b1 )
						begin
							column	<= column + 1'b1;
							temp_col	<= 1'b0;
						end
					end
					else
					begin
						line		<= line + 1'b1;
						column	<= 0;
					end	
				end
				else 
				begin
					line		<= 0;
					column	<= 0;	
				end

				if( line == LowLineProc ) readLineProc	<= 1'b1;
				else if( line == HighLineProc ) readLineProc	<= 1'b0;
				
				if( column == LowColProc ) readColProc	<= 1'b1;
				else if( column == HighColProc ) readColProc	<= 1'b0;
				
			end		
		end
	end
	

	always @(negedge data_clk or posedge rst_i)
	begin
		if(rst_i)
		begin
			vga_hsync_o		<= ~H_active;
			vga_vsync_o		<= ~V_active;
			vga_de_o			<= 1'b0;
			vga_d_o			<= 12'h000;
			shift_reg		=  0;
		end
		else
		begin
			if(ALL_VLD)
			begin

				if( vga_de_o )
				begin
					if( VideoInputActive )
					begin
						if( readLineProc ) 
						begin
							if( readColProc ) 
								begin
								if( temp_col ) 
								begin
									vga_d_o[11:7]		<= { shift_reg[383],4'b1001 };
									vga_d_o[6:4]		<= { shift_reg[382],2'b10 };
									vga_d_o[3:1]		<= 3'b111;
									vga_d_o[0]			<= 1'b1;
								end
								else
								begin
									vga_d_o[11:9]		<= 3'b011;
									vga_d_o[8:4]		<= {shift_reg[381],4'b1001};
									vga_d_o[3]			<= 1'b1;
									vga_d_o[2:0]		<= 3'b111;
									
									shift_reg[383:3]	 =  shift_reg[380:0];
									shift_reg[2:0]		 =  3'b000;	
								end
							end
							else vga_d_o<=color_background;
						end
						else vga_d_o<=color_background;
					end
					else
					begin
						if( line>(V_FP+V_BP+V_sync+LowLine-1) && line <= (V_FP+V_BP+V_sync+HighLine) )
						begin
							if( column>(H_FP+H_BP+H_sync+LowCol) && column<= (H_FP+H_BP+H_sync+HighCol) )
							begin
								if( temp_col ) vga_d_o<=Color[11:0]; 
								else  vga_d_o<=Color[23:12];
							end
							else vga_d_o<=color_background;
						end
						else
						begin
							vga_d_o<=color_background;
						end
					end	
				end
				else
				begin
					vga_d_o<=12'h000;
				end
			

				if(~vga_hsync_o)
				begin
					shift_reg=row2display;
				end
				

				if(line >(V_FP-1+ V_sync+V_BP))
				begin
					if(column>(H_FP+H_BP+H_sync))	vga_de_o<=1'b1; 					
					else vga_de_o<=1'b0;	
				end
				else vga_de_o<=1'b0;
				

				if(column>(H_FP-1) && column<(H_FP+H_sync) ) vga_hsync_o<=H_active; 
				else vga_hsync_o<=~H_active;	
				

				if(line>(V_FP-1) && line<(V_FP+V_sync))
				begin 
					vga_vsync_o<=V_active; 
				end
				else vga_vsync_o<=~V_active;
			end
			else
			begin
				vga_hsync_o<=~H_active;
				vga_vsync_o<=~V_active;
				vga_de_o<=1'b0;
				vga_d_o<=12'h000;
				shift_reg=0;
			end
		end
	end
endmodule