data/full_repos/permissive/181415525/danmaku_de2/global_ctl/led.v
 line:68: before: "SLOT4_DOUBLE"
1: b'%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/global_ctl/led.v:19: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                    : ... In instance led\n        cnt <= 1\'d0;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/global_ctl/led.v:23: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                    : ... In instance led\n        cnt <= 1\'d0;\n            ^~\n%Error: Exiting due to 2 warning(s)\n'
module led(
input wire clk,
input wire rst,
output reg status_led
);

reg [25:0] cnt;

always @(posedge clk or negedge rst) begin
    if (!rst) begin

        status_led <= 1'd0;
        cnt <= 1'd0;
    end
    else if (cnt==12500000) begin
        status_led <= ~status_led;
        cnt <= 1'd0;
    end
    else
        cnt <= cnt+1'd1;
end

endmodule
module led(
input wire clk,
input wire rst,
output reg status_led
);


reg [25:0] cnt;

always @(posedge clk or negedge rst) begin
    if (!rst) begin

        status_led <= 1'd0;
        cnt <= 1'd0;
    end
    else if (cnt==12500000) begin
        status_led <= ~status_led;
        cnt <= 1'd0;
    end
    else
        cnt <= cnt+1'd1;
end

endmodule