data/full_repos/permissive/190595283/Modulos/Ext_Sinal.v
data/verilator_xmls/5a46750d-21b1-4663-a764-40292b50f5b4.xml
module Ext_Sinal (entrada,saida);
  input [15:0]entrada;
  output [31:0]saida;
  assign saida = (entrada[15] == 0) ? {16'b0000000000000000, entrada} : {16'b1111111111111111, entrada};
endmodule
module Ext_Sinal (entrada,saida);

  input [15:0]entrada;
  output [31:0]saida;
  assign saida = (entrada[15] == 0) ? {16'b0000000000000000, entrada} : {16'b1111111111111111, entrada};
endmodule