data/full_repos/permissive/108561032/Memory.v
data/verilator_xmls/73011a10-05a3-4537-bcc3-fae2d667fad9.xml
module Memory(clk,outE,outE_M,Dataout,DataoutM,RegEscr1E,RegEscr1E_M,FMemory);

    input clk;
    input [31:0] outE;
    input [31:0] Dataout;
    input [4:0] RegEscr1E;
    
    output reg [31:0] outE_M;
    output reg [31:0] DataoutM;
    output reg [4:0] RegEscr1E_M;
    output wire FMemory;
    
assign FMemory = clk ? 1'b1:1'b0;
    
 always @ (posedge clk)
    begin
        
        outE_M = outE;
        DataoutM = Dataout;
        RegEscr1E_M = RegEscr1E;
        
    end

endmodule
module Memory(clk,outE,outE_M,Dataout,DataoutM,RegEscr1E,RegEscr1E_M,FMemory);


    input clk;
    input [31:0] outE;
    input [31:0] Dataout;
    input [4:0] RegEscr1E;
    
    output reg [31:0] outE_M;
    output reg [31:0] DataoutM;
    output reg [4:0] RegEscr1E_M;
    output wire FMemory;
    
assign FMemory = clk ? 1'b1:1'b0;
    
 always @ (posedge clk)
    begin
        
        outE_M = outE;
        DataoutM = Dataout;
        RegEscr1E_M = RegEscr1E;
        
    end

endmodule