data/full_repos/permissive/118928497/Quadratic_Equation.v
1: b'%Warning-WIDTH: data/full_repos/permissive/118928497/Quadratic_Equation.v:24: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'in_b\' generates 8 bits.\n                                                                            : ... In instance Quadratic_Equation\n            R <= (in_a * in_x) + in_b;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/118928497/Quadratic_Equation.v:31: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'C\' generates 8 bits.\n                                                                            : ... In instance Quadratic_Equation\n        result <= (R * rX) + C;\n                           ^\n%Error: Exiting due to 2 warning(s)\n'
module Quadratic_Equation (clk, reset, enable,in_a, in_x, in_b, in_c, result);

input wire clk, reset, enable;
input wire [7:0]in_a;
input wire [7:0]in_x;
input wire [7:0]in_b;
input wire [7:0]in_c;
output reg [15:0]result;

reg [7:0]C;
reg [7:0]rX;
reg [15:0]R;

always @ ( posedge clk or posedge reset ) begin
    if (reset == 1) begin
        R <= 16'b0;
        C <= 8'b0;
        result <= 16'b0;
    end
    else begin
        if (enable == 1) begin
            rX <= in_x;
            C <= in_c;
            R <= (in_a * in_x) + in_b;
        end
        else begin
            rX <= 0;
            C <= 0;
            R <= 0;
        end
        result <= (R * rX) + C;
    end
end
endmodule
module Quadratic_Equation (clk, reset, enable,in_a, in_x, in_b, in_c, result);


input wire clk, reset, enable;
input wire [7:0]in_a;
input wire [7:0]in_x;
input wire [7:0]in_b;
input wire [7:0]in_c;
output reg [15:0]result;

reg [7:0]C;
reg [7:0]rX;
reg [15:0]R;

always @ ( posedge clk or posedge reset ) begin
    if (reset == 1) begin
        R <= 16'b0;
        C <= 8'b0;
        result <= 16'b0;
    end
    else begin
        if (enable == 1) begin
            rX <= in_x;
            C <= in_c;
            R <= (in_a * in_x) + in_b;
        end
        else begin
            rX <= 0;
            C <= 0;
            R <= 0;
        end
        result <= (R * rX) + C;
    end
end
endmodule