data/full_repos/permissive/141038711/hdl/apb_regs1.v
data/verilator_xmls/a17b9f83-9e5a-4267-81b0-c69db30d258f.xml
module apb_regs1 (

   input             reset_n,
   input             enable,


   input             pclk,            
   input      [ 3:0] paddr,
   input             pwrite,
   input             psel,
   input             penable,
   input      [31:0] pwdata,
   output reg [31:0] prdata,
   output            pready,
   output            pslverr,


   input      [31:0] status32,
   input      [15:0] status16,
   input      [ 7:0] status8,
   output reg [31:0] control32,
   output reg [15:0] control16,
   output reg [ 7:0] control8
);

wire apb_write = psel & penable & pwrite;
wire apb_read  = psel & ~pwrite;

   assign pready  = 1'b1;
   assign pslverr = 1'b0;
   
   always @(posedge pclk or negedge reset_n)
   begin
      if (!reset_n)
      begin
         control32 <= 32'h0;
         control16 <= 16'h1234;
         control8  <=  8'h0;
         prdata    <= 32'h0;
      end
      else if (enable)
      begin
         
         if (apb_write)
         begin
            case (paddr)

            4'h4 : control32 <= pwdata;
            4'h8 : control16 <= pwdata[15:0];
            4'hC : control8  <= pwdata[7:0];
            endcase
         end
         
         if (apb_read)
         begin
            case (paddr)
            4'h0 : prdata <= status32;
            4'h4 : prdata <= control32; 
            4'h8 : prdata <= {status16,control16};
            4'hC : prdata <= {8'h0,status8,8'h0,control8};
            endcase
         end
         else
            prdata <= 32'h0;
      end
   end
   
endmodule
module apb_regs1 (

   input             reset_n,
   input             enable,


   input             pclk,            
   input      [ 3:0] paddr,
   input             pwrite,
   input             psel,
   input             penable,
   input      [31:0] pwdata,
   output reg [31:0] prdata,
   output            pready,
   output            pslverr,


   input      [31:0] status32,
   input      [15:0] status16,
   input      [ 7:0] status8,
   output reg [31:0] control32,
   output reg [15:0] control16,
   output reg [ 7:0] control8
);


wire apb_write = psel & penable & pwrite;
wire apb_read  = psel & ~pwrite;

   assign pready  = 1'b1;
   assign pslverr = 1'b0;
   
   always @(posedge pclk or negedge reset_n)
   begin
      if (!reset_n)
      begin
         control32 <= 32'h0;
         control16 <= 16'h1234;
         control8  <=  8'h0;
         prdata    <= 32'h0;
      end
      else if (enable)
      begin
         
         if (apb_write)
         begin
            case (paddr)

            4'h4 : control32 <= pwdata;
            4'h8 : control16 <= pwdata[15:0];
            4'hC : control8  <= pwdata[7:0];
            endcase
         end
         
         if (apb_read)
         begin
            case (paddr)
            4'h0 : prdata <= status32;
            4'h4 : prdata <= control32; 
            4'h8 : prdata <= {status16,control16};
            4'hC : prdata <= {8'h0,status8,8'h0,control8};
            endcase
         end
         else
            prdata <= 32'h0;
      end
   end
   
endmodule