data/full_repos/permissive/143278/contrib/add32.v
 line:14: before: "assign"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/add32.v:31: Unsupported: Ignoring delay on this delayed statement.\n    always #1 CLOCK = ~ CLOCK;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/contrib/add32.v:35: Unsupported or unknown PLI call: $monitor\n      $monitor($time,, " CLOCK=%d, A=%x, B=%x, C_IN=%d -- SUM=%x, C_OUT=%d",\n      ^~~~~~~~\n%Error: data/full_repos/permissive/143278/contrib/add32.v:35: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      $monitor($time,, " CLOCK=%d, A=%x, B=%x, C_IN=%d -- SUM=%x, C_OUT=%d",\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/add32.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #20 $finish;\n      ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module add32(sum, cOut, clock, a, b, cIn);

  input clock;
  input a, b, cIn;
  output sum, cOut;

  reg [31:0] a, b;
  reg cIn;
  wire [31:0] sum;
  wire cOut;

  always @(posedge clock)

    assign sum = a + b + cIn;

endmodule
module add32(sum, cOut, clock, a, b, cIn);


  input clock;
  input a, b, cIn;
  output sum, cOut;

  reg [31:0] a, b;
  reg cIn;
  wire [31:0] sum;
  wire cOut;

  always @(posedge clock)

    assign sum = a + b + cIn;

endmodule