data/full_repos/permissive/157608247/src/candy_alu.v
1: b'%Error: data/full_repos/permissive/157608247/src/candy_alu.v:1: Cannot find include file: candy_defines.v\n`include "candy_defines.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157608247/src,data/full_repos/permissive/157608247/candy_defines.v\n             data/full_repos/permissive/157608247/src,data/full_repos/permissive/157608247/candy_defines.v.v\n             data/full_repos/permissive/157608247/src,data/full_repos/permissive/157608247/candy_defines.v.sv\n             candy_defines.v\n             candy_defines.v.v\n             candy_defines.v.sv\n             obj_dir/candy_defines.v\n             obj_dir/candy_defines.v.v\n             obj_dir/candy_defines.v.sv\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:7: Define or directive not defined: \'`AluOpBus\'\n    input wire [`AluOpBus] aluop_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`AluOpBus] aluop_i,\n                         ^\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:8: Define or directive not defined: \'`RegBus\'\n    input wire [`RegBus] reg1_i,\n                ^~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:9: Define or directive not defined: \'`RegBus\'\n    input wire [`RegBus] reg2_i,\n                ^~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:11: Define or directive not defined: \'`RegBus\'\n    output reg [`RegBus] res_o\n                ^~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:14: Define or directive not defined: \'`RegBus\'\nwire [`RegBus] mul_op1;\n      ^~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`RegBus] mul_op1;\n             ^\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:15: Define or directive not defined: \'`RegBus\'\nwire [`RegBus] mul_op2;\n      ^~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`RegBus] mul_op2;\n             ^\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:18: Define or directive not defined: \'`RegBus\'\nreg [`RegBus] add_op1;\n     ^~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:18: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`RegBus] add_op1;\n            ^\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:19: Define or directive not defined: \'`RegBus\'\nreg [`RegBus] add_op2;\n     ^~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`RegBus] add_op2;\n            ^\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:22: syntax error, unexpected assign\nassign mul_op1 = reg1_i;\n^~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:27: syntax error, unexpected IDENTIFIER\nwalltree_mul wm(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:40: Define or directive not defined: \'`RstEnable\'\n    if (rst == `RstEnable) begin\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:41: Define or directive not defined: \'`ZeroWord\'\n        wdata_o <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:45: Define or directive not defined: \'`EXE_NOT\'\n            `EXE_NOT:   begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:48: Define or directive not defined: \'`EXE_NEG\'\n            `EXE_NEG:   begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:51: Define or directive not defined: \'`EXE_AND\'\n            `EXE_AND:   begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:54: Define or directive not defined: \'`EXE_OR\'\n            `EXE_OR:    begin\n            ^~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:57: Define or directive not defined: \'`EXE_XOR\'\n            `EXE_XOR:   begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:65: Define or directive not defined: \'`RstEnable\'\n    if (rst == `RstEnable) begin\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:66: Define or directive not defined: \'`ZeroWord\'\n        wdata_o <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:70: Define or directive not defined: \'`EXE_SLL\'\n            `EXE_SLL:   begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:73: Define or directive not defined: \'`EXE_SRA\'\n            `EXE_SRA:   begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:77: Define or directive not defined: \'`EXE_SRL\'\n            `EXE_SRL:   begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:85: Define or directive not defined: \'`RstEnable\'\n    if(rst == `RstEnable) begin\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:86: Define or directive not defined: \'`ZeroWord\'\n        wdata_o <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:90: Define or directive not defined: \'`EXE_ADD\'\n            `EXE_ADD: begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:95: Define or directive not defined: \'`EXE_SUB\'\n            `EXE_SUB: begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_alu.v:100: Define or directive not defined: \'`EXE_MUL\'\n            `EXE_MUL: begin\n            ^~~~~~~~\n%Error: Exiting due to 33 error(s)\n'
module candy_alu(
    input wire clk,
    input wire rst,

    input wire [`AluOpBus] aluop_i,
    input wire [`RegBus] reg1_i,
    input wire [`RegBus] reg2_i,
  
    output reg [`RegBus] res_o
);

wire [`RegBus] mul_op1;
wire [`RegBus] mul_op2;
wire [48:0] mul_result;

reg [`RegBus] add_op1;
reg [`RegBus] add_op2;
wire [24:0] sum_result;

assign mul_op1 = reg1_i;
assign mul_op2 = reg2_i;

reg [23:0] wdata_o;

walltree_mul wm(
    .op1(mul_op1),
    .op2(mul_op2),
    .result(mul_result)
);

csa24 csa0O(
    .op1(add_op1),
    .op2(add_op2),
    .result(sum_result)
);

always @ (*) begin
    if (rst == `RstEnable) begin
        wdata_o <= `ZeroWord;
    end
    else begin
        case (aluop_i)
            `EXE_NOT:   begin
                wdata_o <= ~(reg1_i);
            end
            `EXE_NEG:   begin
                wdata_o <= ~(reg1_i) + 1;
            end
            `EXE_AND:   begin
                wdata_o <= (reg1_i & reg2_i);
            end
            `EXE_OR:    begin
                wdata_o <= (reg1_i | reg2_i);
            end
            `EXE_XOR:   begin
                wdata_o <= (reg1_i ^ reg2_i);
            end
        endcase
    end
end

always @ (*) begin
    if (rst == `RstEnable) begin
        wdata_o <= `ZeroWord;
    end
    else begin
        case (aluop_i) 
            `EXE_SLL:   begin
                wdata_o <= reg1_i << reg2_i;
            end
            `EXE_SRA:   begin

                wdata_o <= reg1_i >>> reg2_i ;
            end
            `EXE_SRL:   begin
                wdata_o <= reg1_i >> reg2_i;
            end
        endcase
    end
end

always @ (*) begin
    if(rst == `RstEnable) begin
        wdata_o <= `ZeroWord;
    end
    else begin
        case (aluop_i)        
            `EXE_ADD: begin
                add_op1 <= reg1_i;
                add_op2 <= reg2_i;
                wdata_o <= sum_result[23:0];
            end
            `EXE_SUB: begin
                add_op1 <= reg1_i;
                add_op2 <= ~reg2_i + 1;
                wdata_o <= sum_result[23:0];
            end
            `EXE_MUL: begin
                wdata_o <= mul_result[23:0];
            end
        endcase
    end
end

always @ (posedge clk) begin
    res_o <= wdata_o;
end


endmodule
module candy_alu(
    input wire clk,
    input wire rst,

    input wire [`AluOpBus] aluop_i,
    input wire [`RegBus] reg1_i,
    input wire [`RegBus] reg2_i,
  
    output reg [`RegBus] res_o
);


wire [`RegBus] mul_op1;
wire [`RegBus] mul_op2;
wire [48:0] mul_result;

reg [`RegBus] add_op1;
reg [`RegBus] add_op2;
wire [24:0] sum_result;

assign mul_op1 = reg1_i;
assign mul_op2 = reg2_i;

reg [23:0] wdata_o;

walltree_mul wm(
    .op1(mul_op1),
    .op2(mul_op2),
    .result(mul_result)
);

csa24 csa0O(
    .op1(add_op1),
    .op2(add_op2),
    .result(sum_result)
);

always @ (*) begin
    if (rst == `RstEnable) begin
        wdata_o <= `ZeroWord;
    end
    else begin
        case (aluop_i)
            `EXE_NOT:   begin
                wdata_o <= ~(reg1_i);
            end
            `EXE_NEG:   begin
                wdata_o <= ~(reg1_i) + 1;
            end
            `EXE_AND:   begin
                wdata_o <= (reg1_i & reg2_i);
            end
            `EXE_OR:    begin
                wdata_o <= (reg1_i | reg2_i);
            end
            `EXE_XOR:   begin
                wdata_o <= (reg1_i ^ reg2_i);
            end
        endcase
    end
end

always @ (*) begin
    if (rst == `RstEnable) begin
        wdata_o <= `ZeroWord;
    end
    else begin
        case (aluop_i) 
            `EXE_SLL:   begin
                wdata_o <= reg1_i << reg2_i;
            end
            `EXE_SRA:   begin

                wdata_o <= reg1_i >>> reg2_i ;
            end
            `EXE_SRL:   begin
                wdata_o <= reg1_i >> reg2_i;
            end
        endcase
    end
end

always @ (*) begin
    if(rst == `RstEnable) begin
        wdata_o <= `ZeroWord;
    end
    else begin
        case (aluop_i)        
            `EXE_ADD: begin
                add_op1 <= reg1_i;
                add_op2 <= reg2_i;
                wdata_o <= sum_result[23:0];
            end
            `EXE_SUB: begin
                add_op1 <= reg1_i;
                add_op2 <= ~reg2_i + 1;
                wdata_o <= sum_result[23:0];
            end
            `EXE_MUL: begin
                wdata_o <= mul_result[23:0];
            end
        endcase
    end
end

always @ (posedge clk) begin
    res_o <= wdata_o;
end


endmodule