data/full_repos/permissive/155070420/thinpad_top.srcs/sim_1/new/clock.v
 line:8: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/155070420/thinpad_top.srcs/sim_1/new/clock.v:10: Unsupported: Ignoring delay on this delayed statement.\nalways #(90422/2) clk_11M0592 = ~clk_11M0592;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/155070420/thinpad_top.srcs/sim_1/new/clock.v:11: Unsupported: Ignoring delay on this delayed statement.\nalways #(20000/2) clk_50M = ~clk_50M;\n       ^\n%Error: data/full_repos/permissive/155070420/thinpad_top.srcs/sim_1/new/clock.v:8: Duplicate declaration of signal: \'clk_50M\'\n                                                                                 : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg clk_50M = 0, clk_11M0592 = 0;\n    ^~~~~~~\n        data/full_repos/permissive/155070420/thinpad_top.srcs/sim_1/new/clock.v:4: ... Location of original declaration\n    output clk_50M,\n           ^~~~~~~\n%Error: data/full_repos/permissive/155070420/thinpad_top.srcs/sim_1/new/clock.v:8: Duplicate declaration of signal: \'clk_11M0592\'\nreg clk_50M = 0, clk_11M0592 = 0;\n                 ^~~~~~~~~~~\n        data/full_repos/permissive/155070420/thinpad_top.srcs/sim_1/new/clock.v:5: ... Location of original declaration\n    output clk_11M0592\n           ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock (
    output clk_50M,
    output clk_11M0592
);

reg clk_50M = 0, clk_11M0592 = 0;

always #(90422/2) clk_11M0592 = ~clk_11M0592;
always #(20000/2) clk_50M = ~clk_50M;

endmodule
module clock (
    output clk_50M,
    output clk_11M0592
);


reg clk_50M = 0, clk_11M0592 = 0;

always #(90422/2) clk_11M0592 = ~clk_11M0592;
always #(20000/2) clk_50M = ~clk_50M;

endmodule