data/full_repos/permissive/174783592/IFU/IFU_TB.v
 line:47: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/174783592/IFU/IFU_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #50 $finish;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174783592/IFU/IFU_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk <= ~clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/174783592/IFU/IFU_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n    initial #5 reset <= 0;\n            ^\n%Error: data/full_repos/permissive/174783592/IFU/IFU_TB.v:53: Unsupported or unknown PLI call: $monitor\n    initial $monitor($time, " clk=%d,rest=%d,en=%d, pc=%d  pcwire=%d, isr=%d",clk,reset,en,ifu.pc,ifu.pcwire,isr);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module IFU_TB();

    reg reset;
    reg clk;
    reg en;

    wire [15:0] isr;

    IFU ifu(reset,clk,en,isr);

    assign ifu.imem[0]=3;
      assign ifu.imem[1]=7;
      assign ifu.imem[2]=15;
      assign ifu.imem[3]=31;
      assign ifu.imem[4]=64;
      assign ifu.imem[5]=128;
      assign ifu.imem[6]=255;

    initial
    begin
      reset <= 1;
      clk <=0;
      en <=1;
      
      #50 $finish;
    end

    always #5 clk <= ~clk;
    initial #5 reset <= 0;

    initial $monitor($time, " clk=%d,rest=%d,en=%d, pc=%d  pcwire=%d, isr=%d",clk,reset,en,ifu.pc,ifu.pcwire,isr);
endmodule
module IFU_TB();


    reg reset;
    reg clk;
    reg en;

    wire [15:0] isr;

    IFU ifu(reset,clk,en,isr);

    assign ifu.imem[0]=3;
      assign ifu.imem[1]=7;
      assign ifu.imem[2]=15;
      assign ifu.imem[3]=31;
      assign ifu.imem[4]=64;
      assign ifu.imem[5]=128;
      assign ifu.imem[6]=255;

    initial
    begin
      reset <= 1;
      clk <=0;
      en <=1;
      
      #50 $finish;
    end

    always #5 clk <= ~clk;
    initial #5 reset <= 0;

    initial $monitor($time, " clk=%d,rest=%d,en=%d, pc=%d  pcwire=%d, isr=%d",clk,reset,en,ifu.pc,ifu.pcwire,isr);
endmodule