data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton.v
 line:35: before: "("
1: b"%Error: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton.v:60: Cannot find file containing module: 'block'\n      block Bi( { in[ (i==0) ? WIDTH-1 : (i-1) ], in[i], in[ ( i == (WIDTH-1) ) ? 0 : i+1 ] }, rule, out[i] );\n      ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/128117771/Automaton-Verilog-Nbits,data/full_repos/permissive/128117771/block\n             data/full_repos/permissive/128117771/Automaton-Verilog-Nbits,data/full_repos/permissive/128117771/block.v\n             data/full_repos/permissive/128117771/Automaton-Verilog-Nbits,data/full_repos/permissive/128117771/block.sv\n             block\n             block.v\n             block.sv\n             obj_dir/block\n             obj_dir/block.v\n             obj_dir/block.sv\n%Error: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton.v:17: Cannot find file containing module: 'prescaler'\n  prescaler #(.N(N)) PRES ( .clk_in(clk), .clk_out(clk_base) );\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton.v:21: Cannot find file containing module: 'init'\n  init INIT ( clk_base, sel );\n  ^~~~\n%Error: Exiting due to 3 error(s)\n"
module cellAutomaton #(parameter WIDTH = 8) 
  ( input wire [WIDTH-1:0] in,
    input wire [7:0] rule,
    output wire [WIDTH-1:0] out
  );











  genvar i;
  generate
    for (i=0; i<WIDTH; i=i+1)
    begin : automaton_cell
      block Bi( { in[ (i==0) ? WIDTH-1 : (i-1) ], in[i], in[ ( i == (WIDTH-1) ) ? 0 : i+1 ] }, rule, out[i] );








    end 
  endgenerate

endmodule
module cellAutomaton #(parameter WIDTH = 8) 
  ( input wire [WIDTH-1:0] in,
    input wire [7:0] rule,
    output wire [WIDTH-1:0] out
  );












  genvar i;
  generate
    for (i=0; i<WIDTH; i=i+1)
    begin : automaton_cell
      block Bi( { in[ (i==0) ? WIDTH-1 : (i-1) ], in[i], in[ ( i == (WIDTH-1) ) ? 0 : i+1 ] }, rule, out[i] );








    end 
  endgenerate

endmodule