data/full_repos/permissive/133653839/step_1_TB.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/133653839/step_1_TB.v:35: Unsupported: Ignoring delay on this delayed statement.\n   #5 clk = !clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133653839/step_1_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #50000 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/step_1_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #50000 rst = 0;\n  ^\n%Error: data/full_repos/permissive/133653839/step_1_TB.v:16: Cannot find file containing module: \'i2c_clk_divider\'\n i2c_clk_divider uut_1 (\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133653839,data/full_repos/permissive/133653839/i2c_clk_divider\n             data/full_repos/permissive/133653839,data/full_repos/permissive/133653839/i2c_clk_divider.v\n             data/full_repos/permissive/133653839,data/full_repos/permissive/133653839/i2c_clk_divider.sv\n             i2c_clk_divider\n             i2c_clk_divider.v\n             i2c_clk_divider.sv\n             obj_dir/i2c_clk_divider\n             obj_dir/i2c_clk_divider.v\n             obj_dir/i2c_clk_divider.sv\n%Error: data/full_repos/permissive/133653839/step_1_TB.v:22: Cannot find file containing module: \'step_1\'\n step_1 uut_2 (\n ^~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module step_1_TB;


	reg clk;
	reg rst;
	reg ref_clk;

	wire sda;
	wire scl;
	wire i2c_clk;
	
	i2c_clk_divider uut_1 (
		.ref_clk(clk), 
		.rst(rst),  
		.i2c_clk(i2c_clk)
	);

	step_1 uut_2 (
		.clk(i2c_clk), 
		.rst(rst), 
		.sda(sda), 
		.scl(scl)
	);

	
	initial begin

		clk = 0;
		rst = 0;
		forever begin
			#5 clk = !clk;
		end
	end

	initial
		begin
		#50000 rst = 1;
		#50000 rst = 0;
        


	end
      
endmodule
module step_1_TB;



	reg clk;
	reg rst;
	reg ref_clk;

	wire sda;
	wire scl;
	wire i2c_clk;
	
	i2c_clk_divider uut_1 (
		.ref_clk(clk), 
		.rst(rst),  
		.i2c_clk(i2c_clk)
	);

	step_1 uut_2 (
		.clk(i2c_clk), 
		.rst(rst), 
		.sda(sda), 
		.scl(scl)
	);

	
	initial begin

		clk = 0;
		rst = 0;
		forever begin
			#5 clk = !clk;
		end
	end

	initial
		begin
		#50000 rst = 1;
		#50000 rst = 0;
        


	end
      
endmodule