data/full_repos/permissive/143278/ivltests/test_varray1.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:11: syntax error, unexpected \'@\'\n  @(negedge reset);\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:13: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_varray1.v:43: Unsupported: Ignoring delay on this delayed statement.\n  initial forever #T clk = ~clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:55: syntax error, unexpected \'@\'\n  @(negedge reset);\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:57: syntax error, unexpected \'@\'\n  repeat (D) @(negedge clk);\n             ^\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:59: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_varray1.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_varray1.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #S;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:90: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:92: syntax error, unexpected \'@\'\n repeat (5) @(negedge clk);\n            ^\n%Error: Exiting due to 7 error(s), 3 warning(s)\n'
module test;
  parameter M = 200;
  parameter W = 8;
  parameter T = 10;
  parameter D = 8;
  parameter K = 10;
  parameter S = 2*M*T + 12*D;
  parameter MAX = D*K;

  bit clk =0, reset = 0;

  wire [W-1:0] xin;
  wire [W-1:0] din = K;

  wire [W-1:0] dout, bout, xout;

  wire [2:0] lin = 3'b111;
  wire [2:0] lout;

  int x_gold;

  initial forever #T clk = ~clk;



  stimulus   #(W, M, MAX)   stim  (.clk(clk), .reset(reset), .x(xin));
  diq_array  #(W, D)         duv   (.clk(clk), .reset(reset),
                                    .din(din), .bin(8'd0), .xin(xin), .lin(lin),
                                    .dout(dout), .bout(bout), .xout(xout),
                                   .lout(lout) );


initial begin: checking
  @(negedge reset);
  @(posedge clk);
  repeat (D) @(negedge clk);
  forever begin
    @(posedge clk);
    #1;

    if (dout !== din) begin
      $display("ERROR");
      $finish;
    end

    if (bout !== MAX) begin
      $display("ERROR");
      $finish;
    end

    x_gold = xout-1;
    if (lout !== x_gold/K) begin
      $display("ERROR");
      $finish;
    end

  end
end

  initial begin
    doreset();
    #S;
    $display("PASSED");
    $finish;
  end

  task doreset;
     begin
	@(negedge clk);
	reset = 1;
	repeat (5) @(negedge clk);
	reset = 0;
     end
  endtask

endmodule
module test;

  parameter M = 200;
  parameter W = 8;
  parameter T = 10;
  parameter D = 8;
  parameter K = 10;
  parameter S = 2*M*T + 12*D;
  parameter MAX = D*K;

  bit clk =0, reset = 0;

  wire [W-1:0] xin;
  wire [W-1:0] din = K;

  wire [W-1:0] dout, bout, xout;

  wire [2:0] lin = 3'b111;
  wire [2:0] lout;

  int x_gold;

  initial forever #T clk = ~clk;



  stimulus   #(W, M, MAX)   stim  (.clk(clk), .reset(reset), .x(xin));
  diq_array  #(W, D)         duv   (.clk(clk), .reset(reset),
                                    .din(din), .bin(8'd0), .xin(xin), .lin(lin),
                                    .dout(dout), .bout(bout), .xout(xout),
                                   .lout(lout) );


initial begin: checking
  @(negedge reset);
  @(posedge clk);
  repeat (D) @(negedge clk);
  forever begin
    @(posedge clk);
    #1;

    if (dout !== din) begin
      $display("ERROR");
      $finish;
    end

    if (bout !== MAX) begin
      $display("ERROR");
      $finish;
    end

    x_gold = xout-1;
    if (lout !== x_gold/K) begin
      $display("ERROR");
      $finish;
    end

  end
end

  initial begin
    doreset();
    #S;
    $display("PASSED");
    $finish;
  end

  task doreset;
     begin
	@(negedge clk);
	reset = 1;
	repeat (5) @(negedge clk);
	reset = 0;
     end
  endtask

endmodule