data/full_repos/permissive/172538466/hw/src/uart.v
None: at end of input
1: b'%Error: data/full_repos/permissive/172538466/hw/src/uart.v:1: Cannot find include file: defs.vh\n`include "defs.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.v\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.sv\n             defs.vh\n             defs.vh.v\n             defs.vh.sv\n             obj_dir/defs.vh\n             obj_dir/defs.vh.v\n             obj_dir/defs.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module uart
  (
   input        CLK_I,
   input        RESET_N_I,

   input [10:0] ADD_I,

   input        RX_I,
   output [7:0] RX_DATA_O,
   output reg   RX_VALID_O,
   output reg   RX_ERROR_O,

   output       TX_O,
   output       TX_BUSY_O,
   input [7:0]  TX_DATA_I,
   input        TX_VALID_I
   );







   reg [12:0]   acc1;
   wire         tick16 = acc1[12];
   always @(posedge CLK_I)
     if(!RESET_N_I) begin
       acc1 <= 0;
     end else begin
       acc1 <= acc1[11:0] + {1'b0, ADD_I};
     end


   reg [3:0]  acc2;
   reg        tx_tick;
   always @(posedge CLK_I) begin
     tx_tick <= 0;
     if(!tx_working)
       acc2 <= 0;
     else if(tick16) begin
       {tx_tick, acc2} <= acc2 + 1;
     end
   end


   reg [3:0]  acc3;
   reg        rx_tick;
   always @(posedge CLK_I) begin
     rx_tick <= tick16 & ~|acc3;
     if(tick16) begin
       if(rx_state != 0) begin
         acc3 <= acc3 + 1;
       end else
         acc3 <= 9;
     end
   end







   reg [8:0]  tx_data;
   reg        tx_working;
   reg [3:0]  tx_cnt;
   assign       TX_BUSY_O = tx_working;
   assign       TX_O = tx_data[0];

   always @(posedge CLK_I)
     if(!RESET_N_I) begin
       tx_working <= 0;
       tx_cnt <= 0;
       tx_data <= -1;
     end else begin
       if(!tx_working) begin
         tx_cnt <= 0;
         tx_data[0] <= 1;
         if(TX_VALID_I) begin
           tx_working <= 1;
           tx_data <= {TX_DATA_I, 1'b0 };
         end
       end else if(tx_tick) begin
         tx_cnt <= tx_cnt + 1;
         tx_data <= {1'b1, tx_data[8:1]};
         if(tx_cnt == 9)
           tx_working <= 0;
       end
     end







   reg [3:0]  rxs;
   always @(posedge CLK_I)
     rxs <= {RX_I, rxs[3:1]};


   reg        rx;
   always@(posedge CLK_I) begin
     if(!RESET_N_I)
       rx <= 1;
     else begin
       if(rxs[2:0] == 3'b000)
         rx <= 0;
       else if(rxs[2:0] == 3'b111)
         rx <= 1;
     end
   end


   reg [3:0]  rx_state;
   reg [7:0]  rx_data;
   assign RX_DATA_O = rx_data;

   always @(posedge CLK_I)
     if(!RESET_N_I) begin
       rx_state <= 0;
       RX_VALID_O <= 0;
       RX_ERROR_O <= 0;
     end else begin
       RX_VALID_O <= 0;
       RX_ERROR_O <= 0;

       case (rx_state)

         0:
           if(tick16 & !rx)
             rx_state <= 1;


         1:
           if(tick16 & rx) begin
             rx_state <= 0;
             RX_ERROR_O <= 1;
           end else if(rx_tick)
             rx_state <= rx_state + 1;


         2, 3, 4, 5, 6, 7, 8, 9:
           if(rx_tick) begin
             rx_data <= {rx, rx_data[7:1] };
             rx_state <= rx_state + 1;
             if(rx_state == 9)
               RX_VALID_O <= 1;
           end


         10:
           if(rx_tick) begin
             if(!rx)
               RX_ERROR_O <= 1;
             else
               rx_state <= 0;
           end

         default:
           rx_state <= 0;
       endcase
     end
endmodule
module uart
  (
   input        CLK_I,
   input        RESET_N_I,

   input [10:0] ADD_I,

   input        RX_I,
   output [7:0] RX_DATA_O,
   output reg   RX_VALID_O,
   output reg   RX_ERROR_O,

   output       TX_O,
   output       TX_BUSY_O,
   input [7:0]  TX_DATA_I,
   input        TX_VALID_I
   );








   reg [12:0]   acc1;
   wire         tick16 = acc1[12];
   always @(posedge CLK_I)
     if(!RESET_N_I) begin
       acc1 <= 0;
     end else begin
       acc1 <= acc1[11:0] + {1'b0, ADD_I};
     end


   reg [3:0]  acc2;
   reg        tx_tick;
   always @(posedge CLK_I) begin
     tx_tick <= 0;
     if(!tx_working)
       acc2 <= 0;
     else if(tick16) begin
       {tx_tick, acc2} <= acc2 + 1;
     end
   end


   reg [3:0]  acc3;
   reg        rx_tick;
   always @(posedge CLK_I) begin
     rx_tick <= tick16 & ~|acc3;
     if(tick16) begin
       if(rx_state != 0) begin
         acc3 <= acc3 + 1;
       end else
         acc3 <= 9;
     end
   end







   reg [8:0]  tx_data;
   reg        tx_working;
   reg [3:0]  tx_cnt;
   assign       TX_BUSY_O = tx_working;
   assign       TX_O = tx_data[0];

   always @(posedge CLK_I)
     if(!RESET_N_I) begin
       tx_working <= 0;
       tx_cnt <= 0;
       tx_data <= -1;
     end else begin
       if(!tx_working) begin
         tx_cnt <= 0;
         tx_data[0] <= 1;
         if(TX_VALID_I) begin
           tx_working <= 1;
           tx_data <= {TX_DATA_I, 1'b0 };
         end
       end else if(tx_tick) begin
         tx_cnt <= tx_cnt + 1;
         tx_data <= {1'b1, tx_data[8:1]};
         if(tx_cnt == 9)
           tx_working <= 0;
       end
     end







   reg [3:0]  rxs;
   always @(posedge CLK_I)
     rxs <= {RX_I, rxs[3:1]};


   reg        rx;
   always@(posedge CLK_I) begin
     if(!RESET_N_I)
       rx <= 1;
     else begin
       if(rxs[2:0] == 3'b000)
         rx <= 0;
       else if(rxs[2:0] == 3'b111)
         rx <= 1;
     end
   end


   reg [3:0]  rx_state;
   reg [7:0]  rx_data;
   assign RX_DATA_O = rx_data;

   always @(posedge CLK_I)
     if(!RESET_N_I) begin
       rx_state <= 0;
       RX_VALID_O <= 0;
       RX_ERROR_O <= 0;
     end else begin
       RX_VALID_O <= 0;
       RX_ERROR_O <= 0;

       case (rx_state)

         0:
           if(tick16 & !rx)
             rx_state <= 1;


         1:
           if(tick16 & rx) begin
             rx_state <= 0;
             RX_ERROR_O <= 1;
           end else if(rx_tick)
             rx_state <= rx_state + 1;


         2, 3, 4, 5, 6, 7, 8, 9:
           if(rx_tick) begin
             rx_data <= {rx, rx_data[7:1] };
             rx_state <= rx_state + 1;
             if(rx_state == 9)
               RX_VALID_O <= 1;
           end


         10:
           if(rx_tick) begin
             if(!rx)
               RX_ERROR_O <= 1;
             else
               rx_state <= 0;
           end

         default:
           rx_state <= 0;
       endcase
     end
endmodule