data/full_repos/permissive/190595283/Modulos/Registradores.v
 line:56: before: "RegWrite"
data/verilator_xmls/982750b3-696a-44a7-9a68-d2b5ab65232a.xml
module Registradores (clk,RegWrite,ReadReg1,ReadReg2,WriteReg,WriteData,ReadData1,ReadData2);
  input RegWrite;
  input wire clk;
  input [ 4:0]ReadReg1;
  input [ 4:0]ReadReg2;
  input [ 4:0] WriteReg;
  input [31:0] WriteData;
  output reg [31:0]ReadData1;
  output reg [31:0]ReadData2;
  reg [31:0]Regs[0:31];

  initial begin
    Regs[0] = 0;
    Regs[1] = 0;
    Regs[2] = 0;
    Regs[3] = 0;
    Regs[4] = 0;
    Regs[5] = 0;
    Regs[6] = 0;
    Regs[7] = 0;
    Regs[8] = 10;
    Regs[9] = 20;
    Regs[10] = 22;
    Regs[11] = 40;
    Regs[12] = 50;
    Regs[13] = 60;
    Regs[14] = 70;
    Regs[15] = 80;
    Regs[16] = 1;
    Regs[17] = 2;
    Regs[18] = 0;
    Regs[19] = 4;
    Regs[20] = 5;
    Regs[21] = 6;
    Regs[22] = 7;
    Regs[23] = 8;
    Regs[24] = 0;
    Regs[25] = 0;
    Regs[26] = 0;
    Regs[27] = 0;
    Regs[28] = 0;
    Regs[29] = 0;
    Regs[30] = 0;
    Regs[31] = 0;
  end



  always @ ( ReadReg1 or ReadReg2 ) begin
    ReadData1 <= Regs[ReadReg1];
    ReadData2 <= Regs[ReadReg2];
  end

  always @ (posedge clk, RegWrite) begin
      case (RegWrite)
        0: begin
          end
        1: begin
             Regs[WriteReg] = WriteData;
          end
      endcase
  end
endmodule
module Registradores (clk,RegWrite,ReadReg1,ReadReg2,WriteReg,WriteData,ReadData1,ReadData2);

  input RegWrite;
  input wire clk;
  input [ 4:0]ReadReg1;
  input [ 4:0]ReadReg2;
  input [ 4:0] WriteReg;
  input [31:0] WriteData;
  output reg [31:0]ReadData1;
  output reg [31:0]ReadData2;
  reg [31:0]Regs[0:31];

  initial begin
    Regs[0] = 0;
    Regs[1] = 0;
    Regs[2] = 0;
    Regs[3] = 0;
    Regs[4] = 0;
    Regs[5] = 0;
    Regs[6] = 0;
    Regs[7] = 0;
    Regs[8] = 10;
    Regs[9] = 20;
    Regs[10] = 22;
    Regs[11] = 40;
    Regs[12] = 50;
    Regs[13] = 60;
    Regs[14] = 70;
    Regs[15] = 80;
    Regs[16] = 1;
    Regs[17] = 2;
    Regs[18] = 0;
    Regs[19] = 4;
    Regs[20] = 5;
    Regs[21] = 6;
    Regs[22] = 7;
    Regs[23] = 8;
    Regs[24] = 0;
    Regs[25] = 0;
    Regs[26] = 0;
    Regs[27] = 0;
    Regs[28] = 0;
    Regs[29] = 0;
    Regs[30] = 0;
    Regs[31] = 0;
  end



  always @ ( ReadReg1 or ReadReg2 ) begin
    ReadData1 <= Regs[ReadReg1];
    ReadData2 <= Regs[ReadReg2];
  end

  always @ (posedge clk, RegWrite) begin
      case (RegWrite)
        0: begin
          end
        1: begin
             Regs[WriteReg] = WriteData;
          end
      endcase
  end
endmodule