data/full_repos/permissive/176378198/src/pc.v
data/verilator_xmls/b360a4a3-eedb-42c4-8612-503a249ef1c3.xml
module pc (
    inout [7:0] bus,
    input clk,
    input CE,
    input J,
    input CO,
    input rst
);
    reg [3:0] PC;
    initial PC = 0;
    assign bus[3:0] = CO ? PC : 4'bzzzz;

    always @(posedge clk) begin
        if (rst)
            PC <= 0;
        else if (J)
            PC <= bus[3 : 0];
        else if (CE)
            PC <= PC + 1;
    end

`ifdef FORMAL
    always @* begin

        if (J)
            assume(!CO && !CE);
        else if (CO)
            assume(!CE);

        if (!CO)
            assert(bus[3:0] == 4'bzzzz);
        else
            assert(bus[3:0] == PC);
    end

    reg past_valid;
    initial past_valid = 0;
    always @(posedge clk) begin
        past_valid <= 1;

       if ($past(rst))
            assert(bus[3:0] == 0);
        else if ($past(CE) && past_valid)
            assert(PC == $past(PC) + 4'b1);
    end
`endif
endmodule
module pc (
    inout [7:0] bus,
    input clk,
    input CE,
    input J,
    input CO,
    input rst
);

    reg [3:0] PC;
    initial PC = 0;
    assign bus[3:0] = CO ? PC : 4'bzzzz;

    always @(posedge clk) begin
        if (rst)
            PC <= 0;
        else if (J)
            PC <= bus[3 : 0];
        else if (CE)
            PC <= PC + 1;
    end

`ifdef FORMAL
    always @* begin

        if (J)
            assume(!CO && !CE);
        else if (CO)
            assume(!CE);

        if (!CO)
            assert(bus[3:0] == 4'bzzzz);
        else
            assert(bus[3:0] == PC);
    end

    reg past_valid;
    initial past_valid = 0;
    always @(posedge clk) begin
        past_valid <= 1;

       if ($past(rst))
            assert(bus[3:0] == 0);
        else if ($past(CE) && past_valid)
            assert(PC == $past(PC) + 4'b1);
    end
`endif
endmodule