data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v
1: b'%Error: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:23: Cannot find include file: regfile.syn.v\n`include "regfile.syn.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor/syn/netlist,data/full_repos/permissive/21051978/regfile.syn.v\n             data/full_repos/permissive/21051978/processor/syn/netlist,data/full_repos/permissive/21051978/regfile.syn.v.v\n             data/full_repos/permissive/21051978/processor/syn/netlist,data/full_repos/permissive/21051978/regfile.syn.v.sv\n             regfile.syn.v\n             regfile.syn.v.v\n             regfile.syn.v.sv\n             obj_dir/regfile.syn.v\n             obj_dir/regfile.syn.v.v\n             obj_dir/regfile.syn.v.sv\n%Error: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:24: Cannot find include file: /auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v\n`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:113: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:114: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 1;\n     ^\n%Error: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:160: Unsupported or unknown PLI call: $sdf_annotate\n  $sdf_annotate("../sdf/seq_detect.sdf",rg,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");\n  ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:193: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:200: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:207: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:214: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:221: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:228: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:235: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:242: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/regfiletb.v:259: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Error: Exiting due to 3 error(s), 14 warning(s)\n'
module tb_regfile();

	parameter DEPTH = 8;

	parameter WIDTH = 8;
	
	
	
	
	
	
	


	


	wire [WIDTH-1:0] d_out;
	
	
	
	
	
	
	

	


	reg clock,wr_en;

	reg [WIDTH-1:0] d_in;

	reg [DEPTH-1:0] w_addr,r_addr ;
	
	
	
	
	
	
	
	



	
	
	
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end	
	
	
	
	
	
	
	
	
	

	

	regfile rg (


		d_out,d_in,w_addr,r_addr,wr_en,clock);
	
	
	
	

	

	initial
	begin
		$sdf_annotate("../sdf/seq_detect.sdf",rg,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
		
	

		$display($time, " << Starting the simulation >>");

		d_in=8'd6;
		w_addr=3'd0;
		r_addr=3'd0;
		wr_en=1;
		
		
		#10
		d_in=8'd7;
		w_addr=3'd0;
		r_addr=3'd0;
		wr_en=0;
		

		#10
		d_in=8'd6;
		w_addr=3'd2;
		r_addr=3'd0;
		wr_en=1;
		
		
		#10
		d_in=8'd5;
		w_addr=3'd3;
		r_addr=3'd1;
		wr_en=1;
		
		
		#10
		d_in=8'd100;
		w_addr=3'd4;
		r_addr=3'd7;
		wr_en=1;
		
		
		#10
		d_in=8'd200;
		w_addr=3'd5;
		r_addr=3'd6;
		wr_en=1;
		

		#10
		d_in=8'd3;
		w_addr=3'd4;
		r_addr=3'd2;
		wr_en=0;
		
		
		#10
		d_in=8'd2;
		w_addr=3'd5;
		r_addr=3'd3;
		wr_en=0;
		
		
		#10
		d_in=8'd1;
		w_addr=3'd6;
		r_addr=3'd4;
		wr_en=0;
		
		
		#10
		d_in=8'd0;
		w_addr=3'd7;
		r_addr=3'd5;
		wr_en=0;
		
		
		#10
		d_in=8'd5;
		w_addr=3'd7;
		r_addr=3'd1;
		wr_en=1;
		
		
		#10
		d_in=8'd0;
		w_addr=3'd2;
		r_addr=3'd7;
		wr_en=0;
		
		
		
		
		
		
		
		
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_regfile();


	parameter DEPTH = 8;

	parameter WIDTH = 8;
	
	
	
	
	
	
	


	


	wire [WIDTH-1:0] d_out;
	
	
	
	
	
	
	

	


	reg clock,wr_en;

	reg [WIDTH-1:0] d_in;

	reg [DEPTH-1:0] w_addr,r_addr ;
	
	
	
	
	
	
	
	



	
	
	
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end	
	
	
	
	
	
	
	
	
	

	

	regfile rg (


		d_out,d_in,w_addr,r_addr,wr_en,clock);
	
	
	
	

	

	initial
	begin
		$sdf_annotate("../sdf/seq_detect.sdf",rg,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
		
	

		$display($time, " << Starting the simulation >>");

		d_in=8'd6;
		w_addr=3'd0;
		r_addr=3'd0;
		wr_en=1;
		
		
		#10
		d_in=8'd7;
		w_addr=3'd0;
		r_addr=3'd0;
		wr_en=0;
		

		#10
		d_in=8'd6;
		w_addr=3'd2;
		r_addr=3'd0;
		wr_en=1;
		
		
		#10
		d_in=8'd5;
		w_addr=3'd3;
		r_addr=3'd1;
		wr_en=1;
		
		
		#10
		d_in=8'd100;
		w_addr=3'd4;
		r_addr=3'd7;
		wr_en=1;
		
		
		#10
		d_in=8'd200;
		w_addr=3'd5;
		r_addr=3'd6;
		wr_en=1;
		

		#10
		d_in=8'd3;
		w_addr=3'd4;
		r_addr=3'd2;
		wr_en=0;
		
		
		#10
		d_in=8'd2;
		w_addr=3'd5;
		r_addr=3'd3;
		wr_en=0;
		
		
		#10
		d_in=8'd1;
		w_addr=3'd6;
		r_addr=3'd4;
		wr_en=0;
		
		
		#10
		d_in=8'd0;
		w_addr=3'd7;
		r_addr=3'd5;
		wr_en=0;
		
		
		#10
		d_in=8'd5;
		w_addr=3'd7;
		r_addr=3'd1;
		wr_en=1;
		
		
		#10
		d_in=8'd0;
		w_addr=3'd2;
		r_addr=3'd7;
		wr_en=0;
		
		
		
		
		
		
		
		
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule