data/full_repos/permissive/106029354/verilog_source/multiplexador.v
 line:12: before: "out"
data/verilator_xmls/e1dab13e-2a85-4cfa-b86d-7cd3083b3bac.xml
module mux_4x1(in_1, in_2, in_3, in_4, sel_1, sel_2, out);
output reg out;
input in_1, in_2, in_3, in_4, sel_1, sel_2;

always @(sel_1, sel_2)
begin
	case({sel_1, sel_2})
		0: out = in_1;
		1: out = in_2;
		2: out = in_3;
		3: out = in_4;
	default out = 1'bx;
	endcase
end
endmodule
module mux_4x1(in_1, in_2, in_3, in_4, sel_1, sel_2, out);

output reg out;
input in_1, in_2, in_3, in_4, sel_1, sel_2;

always @(sel_1, sel_2)
begin
	case({sel_1, sel_2})
		0: out = in_1;
		1: out = in_2;
		2: out = in_3;
		3: out = in_4;
	default out = 1'bx;
	endcase
end
endmodule