data/full_repos/permissive/146399661/src/vedic/vedic8.v
1: b'%Warning-WIDTH: data/full_repos/permissive/146399661/src/vedic/vedic8.v:31: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                          : ... In instance vedic8\nvedic4 z1(a[3:0],b[3:0],q0[15:0]);\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/146399661/src/vedic/vedic8.v:32: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                          : ... In instance vedic8\nvedic4 z2(a[7:4],b[3:0],q1[15:0]);\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/146399661/src/vedic/vedic8.v:33: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                          : ... In instance vedic8\nvedic4 z3(a[3:0],b[7:4],q2[15:0]);\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/146399661/src/vedic/vedic8.v:34: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                          : ... In instance vedic8\nvedic4 z4(a[7:4],b[7:4],q3[15:0]);\n                          ^\n%Error: Exiting due to 4 warning(s)\n'
module vedic8(a,b,c);   
input [7:0]a;
input [7:0]b;
output [15:0]c;
wire d,e,f;
wire [15:0]q0;	
wire [15:0]q1;	
wire [15:0]q2;
wire [15:0]q3;	
wire [15:0]c;
wire [7:0]temp1;
wire [11:0]temp2;
wire [11:0]temp3;
wire [11:0]temp4;
wire [7:0]q4;
wire [11:0]q5;
wire [11:0]q6;

vedic4 z1(a[3:0],b[3:0],q0[15:0]);
vedic4 z2(a[7:4],b[3:0],q1[15:0]);
vedic4 z3(a[3:0],b[7:4],q2[15:0]);
vedic4 z4(a[7:4],b[7:4],q3[15:0]);

assign temp1 ={4'b0000,q0[7:4]};
add8bit z5(q1[7:0],temp1,q4,d);
assign temp2 ={4'b0000,q2[7:0]};
assign temp3 ={q3[7:0],4'b0000};
add12bit z6(temp2,temp3,q5,e);
assign temp4={4'b0000,q4[7:0]};
add12bit z7(temp4,q5,q6,f);
assign c[3:0]=q0[3:0];
assign c[15:4]=q6[11:0];
endmodule
module vedic8(a,b,c);
   
input [7:0]a;
input [7:0]b;
output [15:0]c;
wire d,e,f;
wire [15:0]q0;	
wire [15:0]q1;	
wire [15:0]q2;
wire [15:0]q3;	
wire [15:0]c;
wire [7:0]temp1;
wire [11:0]temp2;
wire [11:0]temp3;
wire [11:0]temp4;
wire [7:0]q4;
wire [11:0]q5;
wire [11:0]q6;

vedic4 z1(a[3:0],b[3:0],q0[15:0]);
vedic4 z2(a[7:4],b[3:0],q1[15:0]);
vedic4 z3(a[3:0],b[7:4],q2[15:0]);
vedic4 z4(a[7:4],b[7:4],q3[15:0]);

assign temp1 ={4'b0000,q0[7:4]};
add8bit z5(q1[7:0],temp1,q4,d);
assign temp2 ={4'b0000,q2[7:0]};
assign temp3 ={q3[7:0],4'b0000};
add12bit z6(temp2,temp3,q5,e);
assign temp4={4'b0000,q4[7:0]};
add12bit z7(temp4,q5,q6,f);
assign c[3:0]=q0[3:0];
assign c[15:4]=q6[11:0];
endmodule