data/full_repos/permissive/147265957/src/register.v
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data/verilator_xmls/674128c7-1bde-49f7-9458-7153b5fe22a0.xml
module register(
    in,cont,reset,clock,load
    );
    parameter WIDTH = 8;
    input [WIDTH-1:0] in;
    input reset,clock,load;
    output reg [WIDTH-1:0] cont;
    initial cont = 0;
    always @(posedge clock) begin
      if (reset) cont = 0;
      else if (clock & load) cont = in;
    end
endmodule
module register(
    in,cont,reset,clock,load
    );

    parameter WIDTH = 8;
    input [WIDTH-1:0] in;
    input reset,clock,load;
    output reg [WIDTH-1:0] cont;
    initial cont = 0;
    always @(posedge clock) begin
      if (reset) cont = 0;
      else if (clock & load) cont = in;
    end
endmodule