data/full_repos/permissive/130536678/Single-Cycle/CPU_TEST.v
 line:89: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/130536678/Single-Cycle/CPU_TEST.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #30 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/130536678/Single-Cycle/CPU_TEST.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #1 CLOCK = ~CLOCK;\n    ^\n%Error: data/full_repos/permissive/130536678/Single-Cycle/CPU_TEST.v:37: Cannot find file containing module: \'Instruction_Memory\'\n  Instruction_Memory mem1\n  ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/130536678/Single-Cycle,data/full_repos/permissive/130536678/Instruction_Memory\n             data/full_repos/permissive/130536678/Single-Cycle,data/full_repos/permissive/130536678/Instruction_Memory.v\n             data/full_repos/permissive/130536678/Single-Cycle,data/full_repos/permissive/130536678/Instruction_Memory.sv\n             Instruction_Memory\n             Instruction_Memory.v\n             Instruction_Memory.sv\n             obj_dir/Instruction_Memory\n             obj_dir/Instruction_Memory.v\n             obj_dir/Instruction_Memory.sv\n%Error: data/full_repos/permissive/130536678/Single-Cycle/CPU_TEST.v:44: Cannot find file containing module: \'Registers\'\n  Registers mem2\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/130536678/Single-Cycle/CPU_TEST.v:56: Cannot find file containing module: \'Data_Memory\'\n  Data_Memory mem3\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130536678/Single-Cycle/CPU_TEST.v:66: Cannot find file containing module: \'ARM_CPU\'\n  ARM_CPU core\n  ^~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPU_TEST;


  reg CLOCK;


  wire [63:0] instructionPC;
  wire [31:0] instructionOut;


  wire [4:0] READ_REG_1;
  wire [4:0] READ_REG_2;
  wire [4:0] WRITE_REG;
  wire [63:0] WRITE_DATA;
  wire [63:0] DATA_OUT_1;
  wire [63:0] DATA_OUT_2;


  wire [63:0] data_memory_out;
  wire [63:0] ALU_Result_Out;


  wire CONTROL_REG2LOC;
  wire CONTROL_REGWRITE;
  wire CONTROL_MEMREAD;
  wire CONTROL_MEMWRITE;
  wire CONTROL_BRANCH;


  Instruction_Memory mem1
  (
    instructionPC,
    instructionOut
  );


  Registers mem2
  (
    READ_REG_1,
    READ_REG_2,
    WRITE_REG,
    WRITE_DATA,
    CONTROL_REGWRITE,
    DATA_OUT_1,
    DATA_OUT_2
  );


  Data_Memory mem3
  (
    ALU_Result_Out,
    DATA_OUT_2,
    CONTROL_MEMREAD,
    CONTROL_MEMWRITE,
    data_memory_out
  );


  ARM_CPU core
  (
    .CLOCK(CLOCK),
    .INSTRUCTION(instructionOut),
    .PC(instructionPC),
    .CONTROL_REG2LOC(CONTROL_REG2LOC),
    .CONTROL_REGWRITE(CONTROL_REGWRITE),
    .CONTROL_MEMREAD(CONTROL_MEMREAD),
    .CONTROL_MEMWRITE(CONTROL_MEMWRITE),
    .CONTROL_BRANCH(CONTROL_BRANCH),
    .READ_REG_1(READ_REG_1),
    .READ_REG_2(READ_REG_2),
    .WRITE_REG(WRITE_REG),
    .REG_DATA1(DATA_OUT_1),
    .REG_DATA2(DATA_OUT_2),
    .ALU_Result_Out(ALU_Result_Out),
    .data_memory_out(data_memory_out),
    .WRITE_REG_DATA(WRITE_DATA)
  );


  initial begin
    CLOCK = 1'b0;
    #30 $finish;
  end


  always begin
    #1 CLOCK = ~CLOCK;
  end
endmodule
module CPU_TEST;



  reg CLOCK;


  wire [63:0] instructionPC;
  wire [31:0] instructionOut;


  wire [4:0] READ_REG_1;
  wire [4:0] READ_REG_2;
  wire [4:0] WRITE_REG;
  wire [63:0] WRITE_DATA;
  wire [63:0] DATA_OUT_1;
  wire [63:0] DATA_OUT_2;


  wire [63:0] data_memory_out;
  wire [63:0] ALU_Result_Out;


  wire CONTROL_REG2LOC;
  wire CONTROL_REGWRITE;
  wire CONTROL_MEMREAD;
  wire CONTROL_MEMWRITE;
  wire CONTROL_BRANCH;


  Instruction_Memory mem1
  (
    instructionPC,
    instructionOut
  );


  Registers mem2
  (
    READ_REG_1,
    READ_REG_2,
    WRITE_REG,
    WRITE_DATA,
    CONTROL_REGWRITE,
    DATA_OUT_1,
    DATA_OUT_2
  );


  Data_Memory mem3
  (
    ALU_Result_Out,
    DATA_OUT_2,
    CONTROL_MEMREAD,
    CONTROL_MEMWRITE,
    data_memory_out
  );


  ARM_CPU core
  (
    .CLOCK(CLOCK),
    .INSTRUCTION(instructionOut),
    .PC(instructionPC),
    .CONTROL_REG2LOC(CONTROL_REG2LOC),
    .CONTROL_REGWRITE(CONTROL_REGWRITE),
    .CONTROL_MEMREAD(CONTROL_MEMREAD),
    .CONTROL_MEMWRITE(CONTROL_MEMWRITE),
    .CONTROL_BRANCH(CONTROL_BRANCH),
    .READ_REG_1(READ_REG_1),
    .READ_REG_2(READ_REG_2),
    .WRITE_REG(WRITE_REG),
    .REG_DATA1(DATA_OUT_1),
    .REG_DATA2(DATA_OUT_2),
    .ALU_Result_Out(ALU_Result_Out),
    .data_memory_out(data_memory_out),
    .WRITE_REG_DATA(WRITE_DATA)
  );


  initial begin
    CLOCK = 1'b0;
    #30 $finish;
  end


  always begin
    #1 CLOCK = ~CLOCK;
  end
endmodule