data/full_repos/permissive/117179686/src/openmips.v
1: b'%Error: data/full_repos/permissive/117179686/src/openmips.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v.v\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/117179686/src/openmips.v:8: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] rom_data_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegBus] rom_data_i,\n                   ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:9: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus] rom_addr_o,\n             ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus]    ram_data_i,\n ^~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:13: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    ram_data_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:14: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus]   ram_addr_o,\n             ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:15: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus]   ram_data_o,\n             ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:17: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[3:0]    ram_sel_o,\n ^~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:18: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire      ram_ce_o,\n ^~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire artificial_go_out\n ^~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:23: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] pc;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] pc;\n                  ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:24: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] id_pc_i;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] id_pc_i;\n                  ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:25: Define or directive not defined: \'`InstBus\'\n wire[`InstBus] id_inst_i;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstBus] id_inst_i;\n              ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:27: Define or directive not defined: \'`AluOpBus\'\n wire[`AluOpBus] id_aluop_o;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluOpBus] id_aluop_o;\n               ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:28: Define or directive not defined: \'`AluSelBus\'\n wire[`AluSelBus] id_alusel_o;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluSelBus] id_alusel_o;\n                ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:29: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] id_reg1_o;\n      ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] id_reg1_o;\n             ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:30: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] id_reg2_o;\n      ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] id_reg2_o;\n             ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:32: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] id_wd_o;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] id_wd_o;\n                 ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:34: Define or directive not defined: \'`AluOpBus\'\n wire[`AluOpBus] ex_aluop_i;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluOpBus] ex_aluop_i;\n               ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:35: Define or directive not defined: \'`AluSelBus\'\n wire[`AluSelBus] ex_alusel_i;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluSelBus] ex_alusel_i;\n                ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:36: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] ex_reg1_i;\n      ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] ex_reg1_i;\n             ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:37: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] ex_reg2_i;\n      ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] ex_reg2_i;\n             ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:38: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] ex_reg2_o; \n      ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] ex_reg2_o; \n             ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:39: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] ex_mem_addr_o;\n      ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] ex_mem_addr_o;\n             ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:41: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] ex_wd_i;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] ex_wd_i;\n                 ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:44: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] ex_wd_o;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] ex_wd_o;\n                 ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:45: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] ex_wdata_o;\n      ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] ex_wdata_o;\n             ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:48: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] mem_wd_i;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] mem_wd_i;\n                 ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:49: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] mem_wdata_i;\n      ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/openmips.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] mem_wdata_i;\n             ^\n%Error: data/full_repos/permissive/117179686/src/openmips.v:52: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] mem_wd_o;\n      ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module openmips(

	input wire clk,
	input wire rst,

	input wire[`RegBus] rom_data_i,
	output wire[`RegBus] rom_addr_o,
	output wire rom_ce_o,
	

	input wire[`RegBus]				ram_data_i,
	output wire[`RegBus]			ram_addr_o,
	output wire[`RegBus]			ram_data_o,
	output wire						ram_we_o,
	output wire[3:0]				ram_sel_o,
	output wire						ram_ce_o,
	output wire artificial_go_out

);

	wire[`InstAddrBus] pc;
	wire[`InstAddrBus] id_pc_i;
	wire[`InstBus] id_inst_i;
	
	wire[`AluOpBus] id_aluop_o;
	wire[`AluSelBus] id_alusel_o;
	wire[`RegBus] id_reg1_o;
	wire[`RegBus] id_reg2_o;
	wire id_wreg_o;
	wire[`RegAddrBus] id_wd_o;
	
	wire[`AluOpBus] ex_aluop_i;
	wire[`AluSelBus] ex_alusel_i;
	wire[`RegBus] ex_reg1_i;
	wire[`RegBus] ex_reg2_i;
	wire[`RegBus] ex_reg2_o;	
	wire[`RegBus] ex_mem_addr_o;
	wire ex_wreg_i;
	wire[`RegAddrBus] ex_wd_i;
	
	wire ex_wreg_o;
	wire[`RegAddrBus] ex_wd_o;
	wire[`RegBus] ex_wdata_o;

	wire mem_wreg_i;
	wire[`RegAddrBus] mem_wd_i;
	wire[`RegBus] mem_wdata_i;

	wire mem_wreg_o;
	wire[`RegAddrBus] mem_wd_o;
	wire[`RegBus] mem_wdata_o;
	
	wire wb_wreg_i;
	wire[`RegAddrBus] wb_wd_i;
	wire[`RegBus] wb_wdata_i;

	wire reg1_read;
	wire reg2_read;
	wire[`RegBus] reg1_data;
	wire[`RegBus] reg2_data;
	wire[`RegAddrBus] reg1_addr;
	wire[`RegAddrBus] reg2_addr;
   	wire [5:0] stall;
   	wire stallreq_from_id;
   	wire stallreq_from_ex;
   	
	wire[`RegBus] id_link_address_o;
	wire[`RegBus] ex_link_address_i;
	wire id_branch_flag_o;
	wire[`RegBus] branch_target_address;
	wire[`RegBus] offset_from_id_ex;
	wire[`RegBus] offset_from_id;
	wire[`AluOpBus] mem_aluop_i;
	wire[`AluOpBus] ex_aluop_o;
	wire[`AluOpBus] mem_aluop_o;
	wire[`RegBus] mem_mem_addr_i;
	wire[`RegBus] mem_reg2_i;
	wire artificial_or_not;
	
	assign artificial_go_out = artificial_or_not;
  
	pc_reg pc_reg0(
		.clk(clk),
		.rst(rst),
		.stall(stall),
		.branch_flag_i(id_branch_flag_o),
		.branch_target_address_i(branch_target_address),
		.pc(pc),
		.ce(rom_ce_o),
		.artificial(artificial_or_not)
	);
	
	assign rom_addr_o = pc;

	if_id if_id0(
		.clk(clk),
		.rst(rst),
		.stall(stall),
		.if_branch(id_branch_flag_o),
		.artificial(artificial_or_not),
		.if_pc(pc),	
		.if_inst(rom_data_i),
		.id_pc(id_pc_i),
		.id_inst(id_inst_i)
	);
	
	id id0(
		.rst(rst),
		.pc_i(id_pc_i),
		.inst_i(id_inst_i),
		.ex_aluop_i(ex_aluop_o),
		.mem_aluop_i(mem_aluop_o),
		.reg1_data_i(reg1_data),
		.reg2_data_i(reg2_data),
		
		.ex_wreg_i(ex_wreg_o),
		.ex_wdata_i(ex_wdata_o),
		.ex_wd_i(ex_wd_o),

		.mem_wreg_i(mem_wreg_o),
		.mem_wdata_i(mem_wdata_o),
		.mem_wd_i(mem_wd_o),

		.reg1_read_o(reg1_read),
		.reg2_read_o(reg2_read), 	  

		.reg1_addr_o(reg1_addr),
		.reg2_addr_o(reg2_addr),
	  
		.aluop_o(id_aluop_o),
		.alusel_o(id_alusel_o),
		.reg1_o(id_reg1_o),
		.reg2_o(id_reg2_o),
		.wd_o(id_wd_o),
		.wreg_o(id_wreg_o),
		
		.branch_flag_o(id_branch_flag_o),
		.branch_target_address_o(branch_target_address),       
		.link_addr_o(id_link_address_o),

		
		.stallreq(stallreq_from_id),
		.offset_o(offset_from_id)
	);

	regfile regfile1(
		.clk (clk),
		.rst (rst),
		.we	(wb_wreg_i),
		.waddr (wb_wd_i),
		.wdata (wb_wdata_i),
		.re1 (reg1_read),
		.raddr1 (reg1_addr),
		.rdata1 (reg1_data),
		.re2 (reg2_read),
		.raddr2 (reg2_addr),
		.rdata2 (reg2_data)
	);

	id_ex id_ex0(
		.clk(clk),
		.rst(rst),
		
		.stall(stall),
		
		.id_aluop(id_aluop_o),
		.id_alusel(id_alusel_o),
		.id_reg1(id_reg1_o),
		.id_reg2(id_reg2_o),
		.id_wd(id_wd_o),
		.id_wreg(id_wreg_o),
		.id_link_address(id_link_address_o),
		.offset_i(offset_from_id),
	
		.ex_aluop(ex_aluop_i),
		.ex_alusel(ex_alusel_i),
		.ex_reg1(ex_reg1_i),
		.ex_reg2(ex_reg2_i),
		.ex_wd(ex_wd_i),
		.ex_wreg(ex_wreg_i),
		.ex_link_address(ex_link_address_i),
		.offset_o(offset_from_id_ex)
	);		
	
	ex ex0(
		.rst(rst),
	
		.aluop_i(ex_aluop_i),
		.alusel_i(ex_alusel_i),
		.reg1_i(ex_reg1_i),
		.reg2_i(ex_reg2_i),
		.wd_i(ex_wd_i),
		.wreg_i(ex_wreg_i),
		.link_address_i(ex_link_address_i),
		.offset_i(offset_from_id_ex),
	  
		.wd_o(ex_wd_o),
		.wreg_o(ex_wreg_o),
		.wdata_o(ex_wdata_o),
		.aluop_o(ex_aluop_o),
		.mem_addr_o(ex_mem_addr_o),
		.reg2_o(ex_reg2_o),
		.stallreq(stallreq_from_ex)
	);

  ex_mem ex_mem0(
		.clk(clk),
		.rst(rst),
	  
		.stall(stall),
		.ex_wd(ex_wd_o),
		.ex_wreg(ex_wreg_o),
		.ex_wdata(ex_wdata_o),
  		.ex_aluop(ex_aluop_o),
		.ex_mem_addr(ex_mem_addr_o),
		.ex_reg2(ex_reg2_o),
	
		.mem_wd(mem_wd_i),
		.mem_wreg(mem_wreg_i),
		.mem_wdata(mem_wdata_i),
	  	.mem_aluop(mem_aluop_i),
	  	.mem_mem_addr(mem_mem_addr_i),
		.mem_reg2(mem_reg2_i)
	);
	
	mem mem0(
		.rst(rst),
	
		.wd_i(mem_wd_i),
		.wreg_i(mem_wreg_i),
		.wdata_i(mem_wdata_i),
		.aluop_i(mem_aluop_i),
		.mem_addr_i(mem_mem_addr_i),
		.reg2_i(mem_reg2_i),
		.mem_data_i(ram_data_i),
	  
		.wd_o(mem_wd_o),
		.wreg_o(mem_wreg_o),
		.wdata_o(mem_wdata_o),
		.mem_addr_o(ram_addr_o),
		.mem_we_o(ram_we_o),
		.mem_sel_o(ram_sel_o),
		.mem_data_o(ram_data_o),
		.mem_ce_o(ram_ce_o),
		.aluop_o(mem_aluop_o)
	);

	mem_wb mem_wb0(
		.clk(clk),
		.rst(rst),

		.stall(stall),
		.mem_wd(mem_wd_o),
		.mem_wreg(mem_wreg_o),
		.mem_wdata(mem_wdata_o),
	
		.wb_wd(wb_wd_i),
		.wb_wreg(wb_wreg_i),
		.wb_wdata(wb_wdata_i)
	);
	
	ctrl ctrl0(
		.rst(rst),
		.stallreq_from_id(stallreq_from_id),
		.stallreq_from_ex(stallreq_from_ex),
		.stall(stall)
	);

endmodule
module openmips(

	input wire clk,
	input wire rst,

	input wire[`RegBus] rom_data_i,
	output wire[`RegBus] rom_addr_o,
	output wire rom_ce_o,
	

	input wire[`RegBus]				ram_data_i,
	output wire[`RegBus]			ram_addr_o,
	output wire[`RegBus]			ram_data_o,
	output wire						ram_we_o,
	output wire[3:0]				ram_sel_o,
	output wire						ram_ce_o,
	output wire artificial_go_out

);


	wire[`InstAddrBus] pc;
	wire[`InstAddrBus] id_pc_i;
	wire[`InstBus] id_inst_i;
	
	wire[`AluOpBus] id_aluop_o;
	wire[`AluSelBus] id_alusel_o;
	wire[`RegBus] id_reg1_o;
	wire[`RegBus] id_reg2_o;
	wire id_wreg_o;
	wire[`RegAddrBus] id_wd_o;
	
	wire[`AluOpBus] ex_aluop_i;
	wire[`AluSelBus] ex_alusel_i;
	wire[`RegBus] ex_reg1_i;
	wire[`RegBus] ex_reg2_i;
	wire[`RegBus] ex_reg2_o;	
	wire[`RegBus] ex_mem_addr_o;
	wire ex_wreg_i;
	wire[`RegAddrBus] ex_wd_i;
	
	wire ex_wreg_o;
	wire[`RegAddrBus] ex_wd_o;
	wire[`RegBus] ex_wdata_o;

	wire mem_wreg_i;
	wire[`RegAddrBus] mem_wd_i;
	wire[`RegBus] mem_wdata_i;

	wire mem_wreg_o;
	wire[`RegAddrBus] mem_wd_o;
	wire[`RegBus] mem_wdata_o;
	
	wire wb_wreg_i;
	wire[`RegAddrBus] wb_wd_i;
	wire[`RegBus] wb_wdata_i;

	wire reg1_read;
	wire reg2_read;
	wire[`RegBus] reg1_data;
	wire[`RegBus] reg2_data;
	wire[`RegAddrBus] reg1_addr;
	wire[`RegAddrBus] reg2_addr;
   	wire [5:0] stall;
   	wire stallreq_from_id;
   	wire stallreq_from_ex;
   	
	wire[`RegBus] id_link_address_o;
	wire[`RegBus] ex_link_address_i;
	wire id_branch_flag_o;
	wire[`RegBus] branch_target_address;
	wire[`RegBus] offset_from_id_ex;
	wire[`RegBus] offset_from_id;
	wire[`AluOpBus] mem_aluop_i;
	wire[`AluOpBus] ex_aluop_o;
	wire[`AluOpBus] mem_aluop_o;
	wire[`RegBus] mem_mem_addr_i;
	wire[`RegBus] mem_reg2_i;
	wire artificial_or_not;
	
	assign artificial_go_out = artificial_or_not;
  
	pc_reg pc_reg0(
		.clk(clk),
		.rst(rst),
		.stall(stall),
		.branch_flag_i(id_branch_flag_o),
		.branch_target_address_i(branch_target_address),
		.pc(pc),
		.ce(rom_ce_o),
		.artificial(artificial_or_not)
	);
	
	assign rom_addr_o = pc;

	if_id if_id0(
		.clk(clk),
		.rst(rst),
		.stall(stall),
		.if_branch(id_branch_flag_o),
		.artificial(artificial_or_not),
		.if_pc(pc),	
		.if_inst(rom_data_i),
		.id_pc(id_pc_i),
		.id_inst(id_inst_i)
	);
	
	id id0(
		.rst(rst),
		.pc_i(id_pc_i),
		.inst_i(id_inst_i),
		.ex_aluop_i(ex_aluop_o),
		.mem_aluop_i(mem_aluop_o),
		.reg1_data_i(reg1_data),
		.reg2_data_i(reg2_data),
		
		.ex_wreg_i(ex_wreg_o),
		.ex_wdata_i(ex_wdata_o),
		.ex_wd_i(ex_wd_o),

		.mem_wreg_i(mem_wreg_o),
		.mem_wdata_i(mem_wdata_o),
		.mem_wd_i(mem_wd_o),

		.reg1_read_o(reg1_read),
		.reg2_read_o(reg2_read), 	  

		.reg1_addr_o(reg1_addr),
		.reg2_addr_o(reg2_addr),
	  
		.aluop_o(id_aluop_o),
		.alusel_o(id_alusel_o),
		.reg1_o(id_reg1_o),
		.reg2_o(id_reg2_o),
		.wd_o(id_wd_o),
		.wreg_o(id_wreg_o),
		
		.branch_flag_o(id_branch_flag_o),
		.branch_target_address_o(branch_target_address),       
		.link_addr_o(id_link_address_o),

		
		.stallreq(stallreq_from_id),
		.offset_o(offset_from_id)
	);

	regfile regfile1(
		.clk (clk),
		.rst (rst),
		.we	(wb_wreg_i),
		.waddr (wb_wd_i),
		.wdata (wb_wdata_i),
		.re1 (reg1_read),
		.raddr1 (reg1_addr),
		.rdata1 (reg1_data),
		.re2 (reg2_read),
		.raddr2 (reg2_addr),
		.rdata2 (reg2_data)
	);

	id_ex id_ex0(
		.clk(clk),
		.rst(rst),
		
		.stall(stall),
		
		.id_aluop(id_aluop_o),
		.id_alusel(id_alusel_o),
		.id_reg1(id_reg1_o),
		.id_reg2(id_reg2_o),
		.id_wd(id_wd_o),
		.id_wreg(id_wreg_o),
		.id_link_address(id_link_address_o),
		.offset_i(offset_from_id),
	
		.ex_aluop(ex_aluop_i),
		.ex_alusel(ex_alusel_i),
		.ex_reg1(ex_reg1_i),
		.ex_reg2(ex_reg2_i),
		.ex_wd(ex_wd_i),
		.ex_wreg(ex_wreg_i),
		.ex_link_address(ex_link_address_i),
		.offset_o(offset_from_id_ex)
	);		
	
	ex ex0(
		.rst(rst),
	
		.aluop_i(ex_aluop_i),
		.alusel_i(ex_alusel_i),
		.reg1_i(ex_reg1_i),
		.reg2_i(ex_reg2_i),
		.wd_i(ex_wd_i),
		.wreg_i(ex_wreg_i),
		.link_address_i(ex_link_address_i),
		.offset_i(offset_from_id_ex),
	  
		.wd_o(ex_wd_o),
		.wreg_o(ex_wreg_o),
		.wdata_o(ex_wdata_o),
		.aluop_o(ex_aluop_o),
		.mem_addr_o(ex_mem_addr_o),
		.reg2_o(ex_reg2_o),
		.stallreq(stallreq_from_ex)
	);

  ex_mem ex_mem0(
		.clk(clk),
		.rst(rst),
	  
		.stall(stall),
		.ex_wd(ex_wd_o),
		.ex_wreg(ex_wreg_o),
		.ex_wdata(ex_wdata_o),
  		.ex_aluop(ex_aluop_o),
		.ex_mem_addr(ex_mem_addr_o),
		.ex_reg2(ex_reg2_o),
	
		.mem_wd(mem_wd_i),
		.mem_wreg(mem_wreg_i),
		.mem_wdata(mem_wdata_i),
	  	.mem_aluop(mem_aluop_i),
	  	.mem_mem_addr(mem_mem_addr_i),
		.mem_reg2(mem_reg2_i)
	);
	
	mem mem0(
		.rst(rst),
	
		.wd_i(mem_wd_i),
		.wreg_i(mem_wreg_i),
		.wdata_i(mem_wdata_i),
		.aluop_i(mem_aluop_i),
		.mem_addr_i(mem_mem_addr_i),
		.reg2_i(mem_reg2_i),
		.mem_data_i(ram_data_i),
	  
		.wd_o(mem_wd_o),
		.wreg_o(mem_wreg_o),
		.wdata_o(mem_wdata_o),
		.mem_addr_o(ram_addr_o),
		.mem_we_o(ram_we_o),
		.mem_sel_o(ram_sel_o),
		.mem_data_o(ram_data_o),
		.mem_ce_o(ram_ce_o),
		.aluop_o(mem_aluop_o)
	);

	mem_wb mem_wb0(
		.clk(clk),
		.rst(rst),

		.stall(stall),
		.mem_wd(mem_wd_o),
		.mem_wreg(mem_wreg_o),
		.mem_wdata(mem_wdata_o),
	
		.wb_wd(wb_wd_i),
		.wb_wreg(wb_wreg_i),
		.wb_wdata(wb_wdata_i)
	);
	
	ctrl ctrl0(
		.rst(rst),
		.stallreq_from_id(stallreq_from_id),
		.stallreq_from_ex(stallreq_from_ex),
		.stall(stall)
	);

endmodule