data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v
 line:29: before: ","
1: b'%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:96: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'WOFS\' generates 4 bits.\n                                                                             : ... In instance NINJAKUN_SP.eng\nassign     WPAD = {1\'b0,XPOS}-{XPOSH,8\'h0}+WOFS-1\'d1;\n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:96: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 9 bits.\n                                                                             : ... In instance NINJAKUN_SP.eng\nassign     WPAD = {1\'b0,XPOS}-{XPOSH,8\'h0}+WOFS-1\'d1;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:142: Operator ADD expects 9 bits on the RHS, but RHS\'s CONST \'5\'h11\' generates 5 bits.\n                                                                              : ... In instance NINJAKUN_SP.eng\n    NV <= PV+5\'d17;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:142: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                              : ... In instance NINJAKUN_SP.eng\n    NV <= PV+5\'d17;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:176: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s VARREF \'SPADT\' generates 8 bits.\n                                                                              : ... In instance NINJAKUN_SP.eng\n   PTNO  <= RAIDERS5 ? { PTNO[8:6], SPADT[7:2] } : SPADT;\n                     ^\n%Error: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:32: Cannot find file containing module: \'dpram\'\ndpram #(8,10) ldbuf(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/217518118/rtl,data/full_repos/permissive/217518118/dpram\n             data/full_repos/permissive/217518118/rtl,data/full_repos/permissive/217518118/dpram.v\n             data/full_repos/permissive/217518118/rtl,data/full_repos/permissive/217518118/dpram.sv\n             dpram\n             dpram.v\n             dpram.sv\n             obj_dir/dpram\n             obj_dir/dpram.v\n             obj_dir/dpram.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module NINJAKUN_SPENG
(
	input         VCLKx4,
	input         RESET,
	input         RAIDERS5,

	input   [8:0] PH,
	input   [8:0] PV,

	output [10:0] SPAAD,
	input   [7:0] SPADT,

	output reg [13:0] SPCAD,
	input  [31:0] SPCDT,
	input         SPCFT,

	output [7:0]  WPAD,
	output [7:0]  WPIX,
	output        WPEN
);

reg  [5:0] SPRNO;
reg  [1:0] SPRIX;
assign     SPAAD = {SPRNO, 3'h0, SPRIX};

reg  [3:0] PALNO;
reg        FLIPH;
reg        FLIPV;
reg        XPOSH;
reg        DSABL;

reg  [7:0] YPOS;
reg  [7:0] NV;
wire [7:0] HV   = NV-YPOS;
wire [3:0] LV   = {4{FLIPV}}^(HV[3:0]);
wire       YHIT = (HV[7:4]==4'b1111) & (~DSABL);

reg  [7:0] XPOS;
reg  [4:0] WP;
wire [3:0] WOFS = {4{FLIPH}}^(WP[3:0]);
assign     WPAD = {1'b0,XPOS}-{XPOSH,8'h0}+WOFS-1'd1;
assign     WPEN = ~(WP[4]|(WPIX[3:0]==0));

reg  [8:0] PTNO;
reg        CRS;

function [3:0] XOUT;
input  [2:0] N;
input [31:0] CDT;
	case(N)
	 0: XOUT = CDT[7:4];
	 1: XOUT = CDT[3:0];
	 2: XOUT = CDT[15:12];
	 3: XOUT = CDT[11:8];
	 4: XOUT = CDT[23:20];
	 5: XOUT = CDT[19:16];
	 6: XOUT = CDT[31:28];
	 7: XOUT = CDT[27:24];
	endcase
endfunction
reg [31:0] CDT0, CDT1;
assign	  WPIX = {PALNO, XOUT(WP[2:0],WP[3] ? CDT1 : CDT0)};


`define WAIT	0
`define FETCH0	1
`define FETCH1	2
`define FETCH2	3
`define FETCH3	4
`define FETCH4	5
`define DRAW	6
`define NEXT	7

reg  [2:0] STATE;
reg        PH8_D;
always @( posedge VCLKx4 ) begin
	if (RESET) begin
		STATE <= `WAIT;
		SPCAD <= 14'h3fff;
	end else
	case (STATE)

	 `WAIT: begin
			PH8_D <= PH[8];
			WP <= 16;
			if (PH8_D & ~PH[8]) begin
				NV <= PV+5'd17;
				SPRNO <= 0;
				SPRIX <= 2;
				STATE <= `FETCH0;
			end
		end

	 `FETCH0: begin
			YPOS  <= SPADT;
			SPRIX <= 3;
			STATE <= `FETCH1;
		end
	 `FETCH1: begin
			if (!RAIDERS5) begin
				PALNO <= SPADT[3:0];
				FLIPH <= SPADT[4];
				FLIPV <= SPADT[5];
				XPOSH <= SPADT[6];
				DSABL <= SPADT[7];
			end else begin
				PALNO <= SPADT[7:4];
				DSABL <= SPADT[3];
				XPOSH <= 0;
				PTNO[8:6] <= SPADT[2:0];
			end
			SPRIX <= 0;
			STATE <= YHIT ? `FETCH2 : `NEXT;
		end

	 `FETCH2: begin
			if (RAIDERS5) begin
				FLIPH <= SPADT[0];
				FLIPV <= SPADT[1];
			end
			PTNO  <= RAIDERS5 ? { PTNO[8:6], SPADT[7:2] } : SPADT;
			SPRIX <= 1;
			STATE <= `FETCH3;
		end
	 `FETCH3: begin
		   if (SPCFT) begin
				XPOS  <= SPADT;
				CRS   <= 0;
				STATE <= `FETCH4;
				SPCAD <= {PTNO, LV[3], 1'b0, LV[2:0]};
			end
		end
	 `FETCH4: begin
			if (SPCFT) begin
				if (~CRS) begin
					CDT0  <= SPCDT;
					CRS   <= 1;
					SPCAD <= {PTNO, LV[3], 1'b1, LV[2:0]};
				end
				else begin
					CDT1  <= SPCDT;
					WP    <= 0;
					STATE <= `DRAW;
				end
			end
		end

	 `DRAW: begin
			WP <= WP+1'd1;
			if (&WP[3:0]) STATE <= `NEXT;
 	   end

	 `NEXT: begin
			CDT0  <= 0; CDT1 <= 0;
			SPRNO <= SPRNO+1'd1;
			SPRIX <= 2;
			STATE <= (SPRNO==63) ? `WAIT : `FETCH0;
	   end

	endcase
end

endmodule
module NINJAKUN_SPENG
(
	input         VCLKx4,
	input         RESET,
	input         RAIDERS5,

	input   [8:0] PH,
	input   [8:0] PV,

	output [10:0] SPAAD,
	input   [7:0] SPADT,

	output reg [13:0] SPCAD,
	input  [31:0] SPCDT,
	input         SPCFT,

	output [7:0]  WPAD,
	output [7:0]  WPIX,
	output        WPEN
);


reg  [5:0] SPRNO;
reg  [1:0] SPRIX;
assign     SPAAD = {SPRNO, 3'h0, SPRIX};

reg  [3:0] PALNO;
reg        FLIPH;
reg        FLIPV;
reg        XPOSH;
reg        DSABL;

reg  [7:0] YPOS;
reg  [7:0] NV;
wire [7:0] HV   = NV-YPOS;
wire [3:0] LV   = {4{FLIPV}}^(HV[3:0]);
wire       YHIT = (HV[7:4]==4'b1111) & (~DSABL);

reg  [7:0] XPOS;
reg  [4:0] WP;
wire [3:0] WOFS = {4{FLIPH}}^(WP[3:0]);
assign     WPAD = {1'b0,XPOS}-{XPOSH,8'h0}+WOFS-1'd1;
assign     WPEN = ~(WP[4]|(WPIX[3:0]==0));

reg  [8:0] PTNO;
reg        CRS;

function [3:0] XOUT;
input  [2:0] N;
input [31:0] CDT;
	case(N)
	 0: XOUT = CDT[7:4];
	 1: XOUT = CDT[3:0];
	 2: XOUT = CDT[15:12];
	 3: XOUT = CDT[11:8];
	 4: XOUT = CDT[23:20];
	 5: XOUT = CDT[19:16];
	 6: XOUT = CDT[31:28];
	 7: XOUT = CDT[27:24];
	endcase
endfunction
reg [31:0] CDT0, CDT1;
assign	  WPIX = {PALNO, XOUT(WP[2:0],WP[3] ? CDT1 : CDT0)};


`define WAIT	0
`define FETCH0	1
`define FETCH1	2
`define FETCH2	3
`define FETCH3	4
`define FETCH4	5
`define DRAW	6
`define NEXT	7

reg  [2:0] STATE;
reg        PH8_D;
always @( posedge VCLKx4 ) begin
	if (RESET) begin
		STATE <= `WAIT;
		SPCAD <= 14'h3fff;
	end else
	case (STATE)

	 `WAIT: begin
			PH8_D <= PH[8];
			WP <= 16;
			if (PH8_D & ~PH[8]) begin
				NV <= PV+5'd17;
				SPRNO <= 0;
				SPRIX <= 2;
				STATE <= `FETCH0;
			end
		end

	 `FETCH0: begin
			YPOS  <= SPADT;
			SPRIX <= 3;
			STATE <= `FETCH1;
		end
	 `FETCH1: begin
			if (!RAIDERS5) begin
				PALNO <= SPADT[3:0];
				FLIPH <= SPADT[4];
				FLIPV <= SPADT[5];
				XPOSH <= SPADT[6];
				DSABL <= SPADT[7];
			end else begin
				PALNO <= SPADT[7:4];
				DSABL <= SPADT[3];
				XPOSH <= 0;
				PTNO[8:6] <= SPADT[2:0];
			end
			SPRIX <= 0;
			STATE <= YHIT ? `FETCH2 : `NEXT;
		end

	 `FETCH2: begin
			if (RAIDERS5) begin
				FLIPH <= SPADT[0];
				FLIPV <= SPADT[1];
			end
			PTNO  <= RAIDERS5 ? { PTNO[8:6], SPADT[7:2] } : SPADT;
			SPRIX <= 1;
			STATE <= `FETCH3;
		end
	 `FETCH3: begin
		   if (SPCFT) begin
				XPOS  <= SPADT;
				CRS   <= 0;
				STATE <= `FETCH4;
				SPCAD <= {PTNO, LV[3], 1'b0, LV[2:0]};
			end
		end
	 `FETCH4: begin
			if (SPCFT) begin
				if (~CRS) begin
					CDT0  <= SPCDT;
					CRS   <= 1;
					SPCAD <= {PTNO, LV[3], 1'b1, LV[2:0]};
				end
				else begin
					CDT1  <= SPCDT;
					WP    <= 0;
					STATE <= `DRAW;
				end
			end
		end

	 `DRAW: begin
			WP <= WP+1'd1;
			if (&WP[3:0]) STATE <= `NEXT;
 	   end

	 `NEXT: begin
			CDT0  <= 0; CDT1 <= 0;
			SPRNO <= SPRNO+1'd1;
			SPRIX <= 2;
			STATE <= (SPRNO==63) ? `WAIT : `FETCH0;
	   end

	endcase
end

endmodule