data/full_repos/permissive/202233324/rtl/ascii_input.v
Syntax Error
data/verilator_xmls/6234d5ac-8747-43a2-aa91-ea24cc52e9f4.xml
module Clock_divider_ascii(clock_in,clock_out
    );
input clock_in;
output clock_out;
reg[27:0] counter=28'd0;
parameter DIVISOR = 28'd2;





always @(posedge clock_in)
begin
 counter <= counter + 28'd1;
 if(counter>=(DIVISOR-1))
  counter <= 28'd0;
end
assign clock_out = (counter<DIVISOR/2)?1'b0:1'b1;
endmodule
module Clock_divider_ascii(clock_in,clock_out
    );

input clock_in;
output clock_out;
reg[27:0] counter=28'd0;
parameter DIVISOR = 28'd2;





always @(posedge clock_in)
begin
 counter <= counter + 28'd1;
 if(counter>=(DIVISOR-1))
  counter <= 28'd0;
end
assign clock_out = (counter<DIVISOR/2)?1'b0:1'b1;
endmodule