data/full_repos/permissive/188868339/src/register/REG_8bit.v
data/verilator_xmls/61eb5dc9-7324-4ebb-803a-bb3967a4b137.xml
module REG_8bit(
    input clk,
    input rst,
    input [7:0]D,
    output reg [7:0] Q
);


    always @ (posedge clk or negedge rst) begin
        if(~rst) Q = 8'b00000000;
        else Q <= D;
    end

endmodule
module REG_8bit(
    input clk,
    input rst,
    input [7:0]D,
    output reg [7:0] Q
);



    always @ (posedge clk or negedge rst) begin
        if(~rst) Q = 8'b00000000;
        else Q <= D;
    end

endmodule