data/full_repos/permissive/139213403/FPGA/stack_testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/stack_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/stack_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/stack_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/stack_testbench.v:37: syntax error, unexpected \'@\'\n  @(negedge reset);\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/stack_testbench.v:44: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/stack_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Error: data/full_repos/permissive/139213403/FPGA/stack_testbench.v:51: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/stack_testbench.v:56: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/stack_testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Error: data/full_repos/permissive/139213403/FPGA/stack_testbench.v:62: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: Exiting due to 5 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stack_testbench;

	localparam WORD_LEN = 8, WORD_SIZE = 4, NUM_WORDS=16;
	localparam T = 20;

	reg clk, reset, rd, wr;
	reg [WORD_LEN-1:0] w_data;
	wire of, uf;
	wire [WORD_LEN-1:0] r_data;
	integer i;
	
	stack #(WORD_LEN, WORD_SIZE) uut (clk, reset, rd, wr, w_data, r_data, of, uf);
	

	always
	begin
		clk = 1'b1;
		#(T / 2);
		clk = 1'b0;
		#(T / 2);
	end


	initial
	begin
		reset = 1'b1;
		#(T / 2);
		reset = 1'b0;
	end
	
	initial
	begin
		w_data = 8'h1;
		rd = 1'b0;
		@(negedge reset);
		@(negedge clk);
		
		for (i = 2; i <= NUM_WORDS; i = i + 1)
			begin
				w_data = i;
				wr = 1'b1;
				@(negedge clk);
				@(posedge clk);
				wr = 1'b0;
				#200;
			end
		
		wr = 1'b0;
		@(negedge clk);
		
		for (i = 2; i <= NUM_WORDS; i = i + 1)
			begin
				rd = 1'b1;
				@(negedge clk);
				@(posedge clk);
				rd = 1'b0;
				#200;
			end
		
		@(negedge clk);
		$stop;
	end
	
endmodule
module stack_testbench;


	localparam WORD_LEN = 8, WORD_SIZE = 4, NUM_WORDS=16;
	localparam T = 20;

	reg clk, reset, rd, wr;
	reg [WORD_LEN-1:0] w_data;
	wire of, uf;
	wire [WORD_LEN-1:0] r_data;
	integer i;
	
	stack #(WORD_LEN, WORD_SIZE) uut (clk, reset, rd, wr, w_data, r_data, of, uf);
	

	always
	begin
		clk = 1'b1;
		#(T / 2);
		clk = 1'b0;
		#(T / 2);
	end


	initial
	begin
		reset = 1'b1;
		#(T / 2);
		reset = 1'b0;
	end
	
	initial
	begin
		w_data = 8'h1;
		rd = 1'b0;
		@(negedge reset);
		@(negedge clk);
		
		for (i = 2; i <= NUM_WORDS; i = i + 1)
			begin
				w_data = i;
				wr = 1'b1;
				@(negedge clk);
				@(posedge clk);
				wr = 1'b0;
				#200;
			end
		
		wr = 1'b0;
		@(negedge clk);
		
		for (i = 2; i <= NUM_WORDS; i = i + 1)
			begin
				rd = 1'b1;
				@(negedge clk);
				@(posedge clk);
				rd = 1'b0;
				#200;
			end
		
		@(negedge clk);
		$stop;
	end
	
endmodule