data/full_repos/permissive/146073027/Simple 32bit integer ALU.v
 line:28: before: "assign"
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/146073027/Simple\n        ... Looked in:\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.sv\n             data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027/Simple.sv\n             obj_dir/data/full_repos/permissive/146073027/Simple\n             obj_dir/data/full_repos/permissive/146073027/Simple.v\n             obj_dir/data/full_repos/permissive/146073027/Simple.sv\n%Error: Cannot find file containing module: 32bit\n%Error: Cannot find file containing module: integer\n%Error: Cannot find file containing module: ALU.v\n%Error: Exiting due to 4 error(s)\n'
module one_bit_fa(c_out,sum,c_in,x,y);
  input c_in,x,y;
  output c_out,sum;
  wire s1,s2,s3;
  
  xor(s1,x,y);
  xor(sum,s1,c_in);
  and(s2,s1,c_in);
  and(s3,x,y);
  or(c_out,s3,s2);
endmodule
module one_bit_fa(c_out,sum,c_in,x,y);

  input c_in,x,y;
  output c_out,sum;
  wire s1,s2,s3;
  
  xor(s1,x,y);
  xor(sum,s1,c_in);
  and(s2,s1,c_in);
  and(s3,x,y);
  or(c_out,s3,s2);
endmodule