data/full_repos/permissive/107757225/testbench.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:38: Unsupported: Ignoring delay on this delayed statement.\n        #1 CLOCK_50 = ~CLOCK_50;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:48: Unsupported: Ignoring delay on this delayed statement.\n        #2 DUT.reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:51: Unsupported: Ignoring delay on this delayed statement.\n        #2 DUT.cont = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:52: Unsupported: Ignoring delay on this delayed statement.\n        #2 DUT.cont = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:53: Unsupported: Ignoring delay on this delayed statement.\n        #2 DUT.cont = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:54: Unsupported: Ignoring delay on this delayed statement.\n        #2 DUT.cont = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:55: Unsupported: Ignoring delay on this delayed statement.\n        #2 DUT.cont = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:56: Unsupported: Ignoring delay on this delayed statement.\n        #2 DUT.cont = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:57: Unsupported: Ignoring delay on this delayed statement.\n        #2 DUT.cont = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:58: Unsupported: Ignoring delay on this delayed statement.\n        #2 DUT.cont = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:59: Unsupported: Ignoring delay on this delayed statement.\n        #2 DUT.cont = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/107757225/testbench.sv:60: Unsupported: Ignoring delay on this delayed statement.\n        #2 DUT.cont = 1;\n        ^\n%Error: data/full_repos/permissive/107757225/testbench.sv:46: Can\'t find definition of \'reset\' in dotted variable: \'DUT.reset\'\n        DUT.reset = 1;\n            ^~~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:47: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        DUT.cont = 1;\n            ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:48: Can\'t find definition of \'reset\' in dotted variable: \'DUT.reset\'\n        #2 DUT.reset = 0;\n               ^~~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:50: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        DUT.cont = 1;\n            ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:51: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        #2 DUT.cont = 0;\n               ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:52: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        #2 DUT.cont = 1;\n               ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:53: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        #2 DUT.cont = 0;\n               ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:54: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        #2 DUT.cont = 1;\n               ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:55: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        #2 DUT.cont = 0;\n               ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:56: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        #2 DUT.cont = 1;\n               ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:57: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        #2 DUT.cont = 0;\n               ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:58: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        #2 DUT.cont = 1;\n               ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:59: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        #2 DUT.cont = 0;\n               ^~~~\n%Error: data/full_repos/permissive/107757225/testbench.sv:60: Can\'t find definition of \'cont\' in dotted variable: \'DUT.cont\'\n        #2 DUT.cont = 1;\n               ^~~~\n%Error: Exiting due to 14 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench ( input a );

    timeunit 10ns;
    timeprecision 1ns;


	logic [3:0] KEY;
	logic CLOCK_50;
	logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
	

	wire [15:0] SRAM_DQ;
	logic SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_OE_N, SRAM_WE_N;
	logic [19:0] SRAM_ADDR;

	toplevel DUT(
		.KEY        (KEY),
		.CLOCK_50   (CLOCK_50),
		.HEX0       (HEX0),
		.HEX1       (HEX1),
		.HEX2       (HEX2),
		.HEX3       (HEX3),
		.HEX4       (HEX4),
		.HEX5       (HEX5),
		.HEX6       (HEX6),
		.HEX7       (HEX7),
        .SRAM_DQ    (SRAM_DQ),
        .SRAM_ADDR  (SRAM_ADDR),
        .SRAM_CE_N  (SRAM_CE_N),
        .SRAM_UB_N  (SRAM_UB_N),
        .SRAM_LB_N  (SRAM_LB_N),
        .SRAM_OE_N  (SRAM_OE_N),
        .SRAM_WE_N  (SRAM_WE_N)

	);

    always begin : CLOCK_GENERATION
        #1 CLOCK_50 = ~CLOCK_50;
    end

    initial begin: CLOCK_INITIALIZATION
        CLOCK_50 = 0;
    end 

    initial begin: TEST_VECTORS
        DUT.reset = 1;
        DUT.cont = 1;
        #2 DUT.reset = 0;

        DUT.cont = 1;
        #2 DUT.cont = 0;
        #2 DUT.cont = 1;
        #2 DUT.cont = 0;
        #2 DUT.cont = 1;
        #2 DUT.cont = 0;
        #2 DUT.cont = 1;
        #2 DUT.cont = 0;
        #2 DUT.cont = 1;
        #2 DUT.cont = 0;
        #2 DUT.cont = 1;

    end

endmodule
module testbench ( input a );


    timeunit 10ns;
    timeprecision 1ns;


	logic [3:0] KEY;
	logic CLOCK_50;
	logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
	

	wire [15:0] SRAM_DQ;
	logic SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_OE_N, SRAM_WE_N;
	logic [19:0] SRAM_ADDR;

	toplevel DUT(
		.KEY        (KEY),
		.CLOCK_50   (CLOCK_50),
		.HEX0       (HEX0),
		.HEX1       (HEX1),
		.HEX2       (HEX2),
		.HEX3       (HEX3),
		.HEX4       (HEX4),
		.HEX5       (HEX5),
		.HEX6       (HEX6),
		.HEX7       (HEX7),
        .SRAM_DQ    (SRAM_DQ),
        .SRAM_ADDR  (SRAM_ADDR),
        .SRAM_CE_N  (SRAM_CE_N),
        .SRAM_UB_N  (SRAM_UB_N),
        .SRAM_LB_N  (SRAM_LB_N),
        .SRAM_OE_N  (SRAM_OE_N),
        .SRAM_WE_N  (SRAM_WE_N)

	);

    always begin : CLOCK_GENERATION
        #1 CLOCK_50 = ~CLOCK_50;
    end

    initial begin: CLOCK_INITIALIZATION
        CLOCK_50 = 0;
    end 

    initial begin: TEST_VECTORS
        DUT.reset = 1;
        DUT.cont = 1;
        #2 DUT.reset = 0;

        DUT.cont = 1;
        #2 DUT.cont = 0;
        #2 DUT.cont = 1;
        #2 DUT.cont = 0;
        #2 DUT.cont = 1;
        #2 DUT.cont = 0;
        #2 DUT.cont = 1;
        #2 DUT.cont = 0;
        #2 DUT.cont = 1;
        #2 DUT.cont = 0;
        #2 DUT.cont = 1;

    end

endmodule