data/full_repos/permissive/193790231/lab06/lab06part06.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193790231/lab06/lab06part06.v:25: Unsupported: Ignoring delay on this delayed statement.\n        res = 1\'b0; #100; res=1\'b1; #100;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab06/lab06part06.v:25: Unsupported: Ignoring delay on this delayed statement.\n        res = 1\'b0; #100; res=1\'b1; #100;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab06/lab06part06.v:26: Unsupported: Ignoring delay on this delayed statement.\n        forever #50 clk=~clk;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab06/lab06part06.v:35: Unsupported: Ignoring delay on this delayed statement.\n                a=i; b=j; #100; \n                          ^\n%Error: data/full_repos/permissive/193790231/lab06/lab06part06.v:9: Cannot find file containing module: \'syncMultiplierNx\'\n    syncMultiplierNx #(4) multhem(ans, SW[7:4], SW[3:0], SW[8], KEY[3]);\n    ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193790231/lab06,data/full_repos/permissive/193790231/syncMultiplierNx\n             data/full_repos/permissive/193790231/lab06,data/full_repos/permissive/193790231/syncMultiplierNx.v\n             data/full_repos/permissive/193790231/lab06,data/full_repos/permissive/193790231/syncMultiplierNx.sv\n             syncMultiplierNx\n             syncMultiplierNx.v\n             syncMultiplierNx.sv\n             obj_dir/syncMultiplierNx\n             obj_dir/syncMultiplierNx.v\n             obj_dir/syncMultiplierNx.sv\n%Error: data/full_repos/permissive/193790231/lab06/lab06part06.v:10: Cannot find file containing module: \'hexDecoder7Seg\'\n    hexDecoder7Seg disp1(HEX1, ans[7:4]);\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193790231/lab06/lab06part06.v:11: Cannot find file containing module: \'hexDecoder7Seg\'\n    hexDecoder7Seg disp0(HEX0, ans[3:0]);\n    ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab06/lab06part06.v:35: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance tbtestl6p6\n                a=i; b=j; #100; \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab06/lab06part06.v:35: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                           : ... In instance tbtestl6p6\n                a=i; b=j; #100; \n                      ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tbtestl6p6;
    wire [6:0]h1,h0;
    reg  [3:0]a,b;
    wire [7:0]ans;
    reg clk, res;
    lab06part06 testl6p6(h1,h0,ans, {clk, a, b}, res);
    
    initial begin
        clk = 1'b0;
        res = 1'b0; #100; res=1'b1; #100;
        forever #50 clk=~clk;
    end

    integer i, j;
    initial begin
        

        for(i=0; i<16; i=i+1) begin
            for(j=0; j<16; j=j+1) begin
                a=i; b=j; #100; 
            end
        end
    end
endmodule
module tbtestl6p6;

    wire [6:0]h1,h0;
    reg  [3:0]a,b;
    wire [7:0]ans;
    reg clk, res;
    lab06part06 testl6p6(h1,h0,ans, {clk, a, b}, res);
    
    initial begin
        clk = 1'b0;
        res = 1'b0; #100; res=1'b1; #100;
        forever #50 clk=~clk;
    end

    integer i, j;
    initial begin
        

        for(i=0; i<16; i=i+1) begin
            for(j=0; j<16; j=j+1) begin
                a=i; b=j; #100; 
            end
        end
    end
endmodule