data/full_repos/permissive/175197601/hdl/jtpopeye_dip.v
data/verilator_xmls/98c3c8e9-ceee-4f52-874b-029bb057401d.xml
module jtpopeye_dip(
    input             clk,
    input      [31:0] status,
    output reg [ 1:0] dip_level,
    output     [ 1:0] dip_lives,
    output     [ 1:0] dip_bonus,
    output            dip_upright,
    output            dip_demosnd,
    output     [ 3:0] dip_price,
    output            skyskipper
);

assign dip_upright = 1'b0;
assign dip_demosnd = status[22];
assign dip_price   = 4'hf;
assign dip_lives   = status[19:18];
assign dip_bonus   = status[21:20];
assign skyskipper  = status[23];



always @(posedge clk) begin
    case( status[17:16] )
        2'b00: dip_level <= 2'b10;
        2'b01: dip_level <= 2'b11;
        2'b10: dip_level <= 2'b01;
        2'b11: dip_level <= 2'b00;
    endcase
end

endmodule
module jtpopeye_dip(
    input             clk,
    input      [31:0] status,
    output reg [ 1:0] dip_level,
    output     [ 1:0] dip_lives,
    output     [ 1:0] dip_bonus,
    output            dip_upright,
    output            dip_demosnd,
    output     [ 3:0] dip_price,
    output            skyskipper
);


assign dip_upright = 1'b0;
assign dip_demosnd = status[22];
assign dip_price   = 4'hf;
assign dip_lives   = status[19:18];
assign dip_bonus   = status[21:20];
assign skyskipper  = status[23];



always @(posedge clk) begin
    case( status[17:16] )
        2'b00: dip_level <= 2'b10;
        2'b01: dip_level <= 2'b11;
        2'b10: dip_level <= 2'b01;
        2'b11: dip_level <= 2'b00;
    endcase
end

endmodule