data/full_repos/permissive/143278/ivltests/br_ml20180309b.v
 line:3: before: "="
data/verilator_xmls/d71e81c8-2384-458d-bda8-f32d1e31204a.xml
module test();

  string str1 = "abcd";
  string str2 = "efgh";

  typedef bit [31:0] vector;

  vector data[1:0];

  initial begin
    data[0] = vector'(str1);
    data[1] = vector'(str2);
    $display("%s %s", data[0], data[1]);
    if (data[0] === "abcd" && data[1] === "efgh")
      $display("PASSED");
    else
      $display("FAILED");
  end

endmodule
module test();


  string str1 = "abcd";
  string str2 = "efgh";

  typedef bit [31:0] vector;

  vector data[1:0];

  initial begin
    data[0] = vector'(str1);
    data[1] = vector'(str2);
    $display("%s %s", data[0], data[1]);
    if (data[0] === "abcd" && data[1] === "efgh")
      $display("PASSED");
    else
      $display("FAILED");
  end

endmodule