data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_opt_reg.svp
 line:2: before: "parameter"
1: b"%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_opt_reg.svp:1: Define or directive not defined: '`mname'\nmodule  `mname`  #(\n        ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_opt_reg.svp:1: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule  `mname`  #(\n              ^\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_opt_reg.svp:3: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_opt_reg.svp:14: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_opt_reg.svp:18: syntax error, unexpected always_ff\nalways_ff @(posedge clk or negedge rst_n) begin\n^~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module  `mname`  #(
  parameter DataWidth = 16
) (
  input                  clk,
  input                  rst_n,

  input                  load,
  input  [DataWidth-1:0] val,

  input                  sel,

  input        [DataWidth-1:0] data_in,
  output logic [DataWidth-1:0] res
);

logic [DataWidth-1:0] data_in_reg;

always_ff @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    data_in_reg <= 'h0;
  end else if(load) begin
    data_in_reg <= val;
  end else if(~sel) begin
    data_in_reg <= data_in;
  end
end

assign res = sel ? data_in : data_in_reg;

endmodule
module  `mname`  #(
  parameter DataWidth = 16
) (
  input                  clk,
  input                  rst_n,

  input                  load,
  input  [DataWidth-1:0] val,

  input                  sel,

  input        [DataWidth-1:0] data_in,
  output logic [DataWidth-1:0] res
);


logic [DataWidth-1:0] data_in_reg;

always_ff @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    data_in_reg <= 'h0;
  end else if(load) begin
    data_in_reg <= val;
  end else if(~sel) begin
    data_in_reg <= data_in;
  end
end

assign res = sel ? data_in : data_in_reg;

endmodule