data/full_repos/permissive/165160692/04.FPGA/5932_00_153_194/component/work/XYF/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_00_153_194/component/work/XYF/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #(SYSCLK_PERIOD * 10 )\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_00_153_194/component/work/XYF/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;\n    ^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_00_153_194/component/work/XYF/testbench.v:45: Cannot find file containing module: \'XYF\'\nXYF XYF_0 (\n^~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_00_153_194/component/work/XYF,data/full_repos/permissive/165160692/XYF\n             data/full_repos/permissive/165160692/04.FPGA/5932_00_153_194/component/work/XYF,data/full_repos/permissive/165160692/XYF.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_00_153_194/component/work/XYF,data/full_repos/permissive/165160692/XYF.sv\n             XYF\n             XYF.v\n             XYF.sv\n             obj_dir/XYF\n             obj_dir/XYF.v\n             obj_dir/XYF.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

parameter SYSCLK_PERIOD = 100;

reg SYSCLK;
reg NSYSRESET;

initial
begin
    SYSCLK = 1'b0;
    NSYSRESET = 1'b0;
end




initial
begin
    #(SYSCLK_PERIOD * 10 )
        NSYSRESET = 1'b1;
end





always @(SYSCLK)
    #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;





XYF XYF_0 (

    .A({4{1'b0}}),
    .B({4{1'b0}}),
    .I1({4{1'b0}}),
    .I2({4{1'b0}}),
    .S1({1{1'b0}}),
    .S2({1{1'b0}}),
    .E1N({1{1'b0}}),
    .E2N({1{1'b0}}),
    .MR({1{1'b0}}),
    .D({4{1'b0}}),
    .DSR({1{1'b0}}),
    .S({2{1'b0}}),
    .DSL({1{1'b0}}),
    .CP({1{1'b0}}),


    .Q( ),
    .Y( ),
    .Y1( ),
    .Y2( )



);

endmodule
module testbench;


parameter SYSCLK_PERIOD = 100;

reg SYSCLK;
reg NSYSRESET;

initial
begin
    SYSCLK = 1'b0;
    NSYSRESET = 1'b0;
end




initial
begin
    #(SYSCLK_PERIOD * 10 )
        NSYSRESET = 1'b1;
end





always @(SYSCLK)
    #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;





XYF XYF_0 (

    .A({4{1'b0}}),
    .B({4{1'b0}}),
    .I1({4{1'b0}}),
    .I2({4{1'b0}}),
    .S1({1{1'b0}}),
    .S2({1{1'b0}}),
    .E1N({1{1'b0}}),
    .E2N({1{1'b0}}),
    .MR({1{1'b0}}),
    .D({4{1'b0}}),
    .DSR({1{1'b0}}),
    .S({2{1'b0}}),
    .DSL({1{1'b0}}),
    .CP({1{1'b0}}),


    .Q( ),
    .Y( ),
    .Y1( ),
    .Y2( )



);

endmodule