data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/cal1d_fp16_pool_sum.v
1: b"%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/cal1d_fp16_pool_sum.v:63: Cannot find file containing module: 'HLS_fp17_add'\nHLS_fp17_add u_cal1d_pool_sum_0 (\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/HLS_fp17_add\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/HLS_fp17_add.v\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/HLS_fp17_add.sv\n             HLS_fp17_add\n             HLS_fp17_add.v\n             HLS_fp17_add.sv\n             obj_dir/HLS_fp17_add\n             obj_dir/HLS_fp17_add.v\n             obj_dir/HLS_fp17_add.sv\n%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/cal1d_fp16_pool_sum.v:76: Cannot find file containing module: 'HLS_fp17_add'\nHLS_fp17_add u_cal1d_pool_sum_1 (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/cal1d_fp16_pool_sum.v:89: Cannot find file containing module: 'HLS_fp17_add'\nHLS_fp17_add u_cal1d_pool_sum_2 (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/cal1d_fp16_pool_sum.v:102: Cannot find file containing module: 'HLS_fp17_add'\nHLS_fp17_add u_cal1d_pool_sum_3 (\n^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module cal1d_fp16_pool_sum (
   inp_a_0
  ,inp_a_1
  ,inp_a_2
  ,inp_a_3
  ,inp_b_0
  ,inp_b_1
  ,inp_b_2
  ,inp_b_3
  ,inp_in_pvld
  ,inp_out_prdy
  ,nvdla_core_rstn
  ,nvdla_op_gated_clk_fp16
  ,inp_in_prdy
  ,inp_out_pvld
  ,out_z_0
  ,out_z_1
  ,out_z_2
  ,out_z_3
  );
input [16:0] inp_a_0;
input [16:0] inp_a_1;
input [16:0] inp_a_2;
input [16:0] inp_a_3;
input [16:0] inp_b_0;
input [16:0] inp_b_1;
input [16:0] inp_b_2;
input [16:0] inp_b_3;
input inp_in_pvld;
input inp_out_prdy;
input nvdla_core_rstn;
input nvdla_op_gated_clk_fp16;
output inp_in_prdy;
output inp_out_pvld;
output [16:0] out_z_0;
output [16:0] out_z_1;
output [16:0] out_z_2;
output [16:0] out_z_3;
wire [3:0] inp_a_rdy;
wire [3:0] inp_a_vld;
wire [3:0] inp_b_rdy;
wire [3:0] inp_b_vld;
wire [3:0] out_z_rdy;
wire [3:0] out_z_vld;

assign inp_in_prdy = (&inp_a_rdy) & (&inp_b_rdy);
assign inp_a_vld[0] = inp_in_pvld & (&inp_a_rdy[3:1]) & (&inp_b_rdy[3:0]);
assign inp_a_vld[1] = inp_in_pvld & (&{inp_a_rdy[3:2],inp_a_rdy[0]}) & (&inp_b_rdy[3:0]);
assign inp_a_vld[2] = inp_in_pvld & (&{inp_a_rdy[3],inp_a_rdy[1:0]}) & (&inp_b_rdy[3:0]);
assign inp_a_vld[3] = inp_in_pvld & (&inp_a_rdy[2:0]) & (&inp_b_rdy[3:0]);
assign inp_b_vld[0] = inp_in_pvld & (&inp_b_rdy[3:1]) & (&inp_a_rdy[3:0]);
assign inp_b_vld[1] = inp_in_pvld & (&{inp_b_rdy[3:2],inp_b_rdy[0]}) & (&inp_a_rdy[3:0]);
assign inp_b_vld[2] = inp_in_pvld & (&{inp_b_rdy[3],inp_b_rdy[1:0]}) & (&inp_a_rdy[3:0]);
assign inp_b_vld[3] = inp_in_pvld & (&inp_b_rdy[2:0]) & (&inp_a_rdy[3:0]);
HLS_fp17_add u_cal1d_pool_sum_0 (
   .nvdla_core_clk (nvdla_op_gated_clk_fp16)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.chn_a_rsc_z (inp_a_0[16:0])
  ,.chn_a_rsc_vz (inp_a_vld[0])
  ,.chn_a_rsc_lz (inp_a_rdy[0])
  ,.chn_b_rsc_z (inp_b_0[16:0])
  ,.chn_b_rsc_vz (inp_b_vld[0])
  ,.chn_b_rsc_lz (inp_b_rdy[0])
  ,.chn_o_rsc_z (out_z_0[16:0])
  ,.chn_o_rsc_vz (out_z_rdy[0])
  ,.chn_o_rsc_lz (out_z_vld[0])
  );
HLS_fp17_add u_cal1d_pool_sum_1 (
   .nvdla_core_clk (nvdla_op_gated_clk_fp16)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.chn_a_rsc_z (inp_a_1[16:0])
  ,.chn_a_rsc_vz (inp_a_vld[1])
  ,.chn_a_rsc_lz (inp_a_rdy[1])
  ,.chn_b_rsc_z (inp_b_1[16:0])
  ,.chn_b_rsc_vz (inp_b_vld[1])
  ,.chn_b_rsc_lz (inp_b_rdy[1])
  ,.chn_o_rsc_z (out_z_1[16:0])
  ,.chn_o_rsc_vz (out_z_rdy[1])
  ,.chn_o_rsc_lz (out_z_vld[1])
  );
HLS_fp17_add u_cal1d_pool_sum_2 (
   .nvdla_core_clk (nvdla_op_gated_clk_fp16)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.chn_a_rsc_z (inp_a_2[16:0])
  ,.chn_a_rsc_vz (inp_a_vld[2])
  ,.chn_a_rsc_lz (inp_a_rdy[2])
  ,.chn_b_rsc_z (inp_b_2[16:0])
  ,.chn_b_rsc_vz (inp_b_vld[2])
  ,.chn_b_rsc_lz (inp_b_rdy[2])
  ,.chn_o_rsc_z (out_z_2[16:0])
  ,.chn_o_rsc_vz (out_z_rdy[2])
  ,.chn_o_rsc_lz (out_z_vld[2])
  );
HLS_fp17_add u_cal1d_pool_sum_3 (
   .nvdla_core_clk (nvdla_op_gated_clk_fp16)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.chn_a_rsc_z (inp_a_3[16:0])
  ,.chn_a_rsc_vz (inp_a_vld[3])
  ,.chn_a_rsc_lz (inp_a_rdy[3])
  ,.chn_b_rsc_z (inp_b_3[16:0])
  ,.chn_b_rsc_vz (inp_b_vld[3])
  ,.chn_b_rsc_lz (inp_b_rdy[3])
  ,.chn_o_rsc_z (out_z_3[16:0])
  ,.chn_o_rsc_vz (out_z_rdy[3])
  ,.chn_o_rsc_lz (out_z_vld[3])
  );
assign inp_out_pvld = &out_z_vld;
assign out_z_rdy[0] = inp_out_prdy & (&out_z_vld[3:1]);
assign out_z_rdy[1] = inp_out_prdy & (&out_z_vld[3:2] & out_z_vld[0]);
assign out_z_rdy[2] = inp_out_prdy & (out_z_vld[3] & (&out_z_vld[1:0]));
assign out_z_rdy[3] = inp_out_prdy & (&out_z_vld[2:0]);























endmodule
module cal1d_fp16_pool_sum (
   inp_a_0
  ,inp_a_1
  ,inp_a_2
  ,inp_a_3
  ,inp_b_0
  ,inp_b_1
  ,inp_b_2
  ,inp_b_3
  ,inp_in_pvld
  ,inp_out_prdy
  ,nvdla_core_rstn
  ,nvdla_op_gated_clk_fp16
  ,inp_in_prdy
  ,inp_out_pvld
  ,out_z_0
  ,out_z_1
  ,out_z_2
  ,out_z_3
  );

input [16:0] inp_a_0;
input [16:0] inp_a_1;
input [16:0] inp_a_2;
input [16:0] inp_a_3;
input [16:0] inp_b_0;
input [16:0] inp_b_1;
input [16:0] inp_b_2;
input [16:0] inp_b_3;
input inp_in_pvld;
input inp_out_prdy;
input nvdla_core_rstn;
input nvdla_op_gated_clk_fp16;
output inp_in_prdy;
output inp_out_pvld;
output [16:0] out_z_0;
output [16:0] out_z_1;
output [16:0] out_z_2;
output [16:0] out_z_3;
wire [3:0] inp_a_rdy;
wire [3:0] inp_a_vld;
wire [3:0] inp_b_rdy;
wire [3:0] inp_b_vld;
wire [3:0] out_z_rdy;
wire [3:0] out_z_vld;

assign inp_in_prdy = (&inp_a_rdy) & (&inp_b_rdy);
assign inp_a_vld[0] = inp_in_pvld & (&inp_a_rdy[3:1]) & (&inp_b_rdy[3:0]);
assign inp_a_vld[1] = inp_in_pvld & (&{inp_a_rdy[3:2],inp_a_rdy[0]}) & (&inp_b_rdy[3:0]);
assign inp_a_vld[2] = inp_in_pvld & (&{inp_a_rdy[3],inp_a_rdy[1:0]}) & (&inp_b_rdy[3:0]);
assign inp_a_vld[3] = inp_in_pvld & (&inp_a_rdy[2:0]) & (&inp_b_rdy[3:0]);
assign inp_b_vld[0] = inp_in_pvld & (&inp_b_rdy[3:1]) & (&inp_a_rdy[3:0]);
assign inp_b_vld[1] = inp_in_pvld & (&{inp_b_rdy[3:2],inp_b_rdy[0]}) & (&inp_a_rdy[3:0]);
assign inp_b_vld[2] = inp_in_pvld & (&{inp_b_rdy[3],inp_b_rdy[1:0]}) & (&inp_a_rdy[3:0]);
assign inp_b_vld[3] = inp_in_pvld & (&inp_b_rdy[2:0]) & (&inp_a_rdy[3:0]);
HLS_fp17_add u_cal1d_pool_sum_0 (
   .nvdla_core_clk (nvdla_op_gated_clk_fp16)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.chn_a_rsc_z (inp_a_0[16:0])
  ,.chn_a_rsc_vz (inp_a_vld[0])
  ,.chn_a_rsc_lz (inp_a_rdy[0])
  ,.chn_b_rsc_z (inp_b_0[16:0])
  ,.chn_b_rsc_vz (inp_b_vld[0])
  ,.chn_b_rsc_lz (inp_b_rdy[0])
  ,.chn_o_rsc_z (out_z_0[16:0])
  ,.chn_o_rsc_vz (out_z_rdy[0])
  ,.chn_o_rsc_lz (out_z_vld[0])
  );
HLS_fp17_add u_cal1d_pool_sum_1 (
   .nvdla_core_clk (nvdla_op_gated_clk_fp16)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.chn_a_rsc_z (inp_a_1[16:0])
  ,.chn_a_rsc_vz (inp_a_vld[1])
  ,.chn_a_rsc_lz (inp_a_rdy[1])
  ,.chn_b_rsc_z (inp_b_1[16:0])
  ,.chn_b_rsc_vz (inp_b_vld[1])
  ,.chn_b_rsc_lz (inp_b_rdy[1])
  ,.chn_o_rsc_z (out_z_1[16:0])
  ,.chn_o_rsc_vz (out_z_rdy[1])
  ,.chn_o_rsc_lz (out_z_vld[1])
  );
HLS_fp17_add u_cal1d_pool_sum_2 (
   .nvdla_core_clk (nvdla_op_gated_clk_fp16)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.chn_a_rsc_z (inp_a_2[16:0])
  ,.chn_a_rsc_vz (inp_a_vld[2])
  ,.chn_a_rsc_lz (inp_a_rdy[2])
  ,.chn_b_rsc_z (inp_b_2[16:0])
  ,.chn_b_rsc_vz (inp_b_vld[2])
  ,.chn_b_rsc_lz (inp_b_rdy[2])
  ,.chn_o_rsc_z (out_z_2[16:0])
  ,.chn_o_rsc_vz (out_z_rdy[2])
  ,.chn_o_rsc_lz (out_z_vld[2])
  );
HLS_fp17_add u_cal1d_pool_sum_3 (
   .nvdla_core_clk (nvdla_op_gated_clk_fp16)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.chn_a_rsc_z (inp_a_3[16:0])
  ,.chn_a_rsc_vz (inp_a_vld[3])
  ,.chn_a_rsc_lz (inp_a_rdy[3])
  ,.chn_b_rsc_z (inp_b_3[16:0])
  ,.chn_b_rsc_vz (inp_b_vld[3])
  ,.chn_b_rsc_lz (inp_b_rdy[3])
  ,.chn_o_rsc_z (out_z_3[16:0])
  ,.chn_o_rsc_vz (out_z_rdy[3])
  ,.chn_o_rsc_lz (out_z_vld[3])
  );
assign inp_out_pvld = &out_z_vld;
assign out_z_rdy[0] = inp_out_prdy & (&out_z_vld[3:1]);
assign out_z_rdy[1] = inp_out_prdy & (&out_z_vld[3:2] & out_z_vld[0]);
assign out_z_rdy[2] = inp_out_prdy & (out_z_vld[3] & (&out_z_vld[1:0]));
assign out_z_rdy[3] = inp_out_prdy & (&out_z_vld[2:0]);























endmodule