data/full_repos/permissive/117026779/src/MIPS.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/117026779/src/MIPS.v:898: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'MIPS\'\nmodule MIPS(\n       ^~~~\n                                                                      : ... Top module \'MULT\'\nmodule MULT #(parameter WIDTH = 32)(\n       ^~~~\n                                                                      : ... Top module \'DIV\'\nmodule DIV #(parameter WIDTH = 32)(\n       ^~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:754: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n                                                                   : ... In instance MIPS.regfile\nassign read_data_1 = (read_address_1 != 0) ? register_file[read_address_1] : 0;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:755: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n                                                                   : ... In instance MIPS.regfile\nassign read_data_2 = (read_address_2 != 0) ? register_file[read_address_2] : 0;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:774: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n                                                                   : ... In instance MIPS.regfile\n        register_file[write_address] <= write_data;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegWriteDst <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegInSelect <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            PCSrc       <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            MemWrite    <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            ALUOp       <= 1\'bx;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegWriteDst <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegInSelect <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            PCSrc       <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            MemWrite    <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            ALUOp       <= 1\'bx;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegWriteDst <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegInSelect <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            PCSrc       <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            MemWrite    <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            ALUOp       <= 1\'bx;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:194: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'write_address\' generates 5 bits.\n                                                                   : ... In instance MIPS\nassign RegWriteAddress              = write_address;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:241: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                   : ... In instance MIPS\nwire [32-1:0] DataBusByte = DataBusByteShifted & 8\'hFF;\n                                               ^\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:266: Cannot find file containing module: \'REGISTER\'\nREGISTER #(.WIDTH(32)) pc_register (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/REGISTER\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/REGISTER.v\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/REGISTER.sv\n             REGISTER\n             REGISTER.v\n             REGISTER.sv\n             obj_dir/REGISTER\n             obj_dir/REGISTER.v\n             obj_dir/REGISTER.sv\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:280: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:325: Input port connection \'a\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'branch_pc_offset\' generates 32 bits.\n                                                                   : ... In instance MIPS\n .a(branch_pc_offset),\n  ^\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:335: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:344: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:366: Cannot find file containing module: \'OR\'\nOR #(.WIDTH(4)\n^~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:372: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:385: Cannot find file containing module: \'TRIBUFFER\'\nTRIBUFFER #(.WIDTH(32)\n^~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:403: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: Exiting due to 8 error(s), 22 warning(s)\n'
module MIPS(
    input wire clk,
    input wire rst,
    output wire BusCycle,
    output wire [3:0] MemWrite,
    output wire MemRead,
    output wire [`REGISTER_WIDTH-1:0] AddressBus,
    output wire [`REGISTER_WIDTH-1:0] DataBus,
    output wire [`REGISTER_WIDTH-1:0] ProgramCounter,
    output wire [`REGISTER_WIDTH-1:0] ALUResult,
    output wire [`REGISTER_WIDTH-1:0] RegOut1,
    output wire [`REGISTER_WIDTH-1:0] RegOut2,
    output wire [`REGISTER_WIDTH-1:0] RegWriteData,
    output wire [`REGISTER_WIDTH-1:0] RegWriteAddress,
    input wire  [`REGISTER_WIDTH-1:0] Instruction
);



parameter BYTE = 2'd2;
parameter HALF = 2'd1;
parameter WORD = 2'd0;



assign AddressBus                   = (BusCycle) ? alu_result : `REGISTER_WIDTH'b0;
assign ALUResult                    = alu_result;
assign ProgramCounter               = pc;
assign mips_instruction             = Instruction;
assign RegOut1                      = read_data_1;
assign RegOut2                      = read_data_2;
assign RegWriteData                 = write_data;
assign RegWriteAddress              = write_address;
assign data_out_bus_select          = (MemWrite == 4'b1111) ? WORD : (MemWrite == 4'b0011 || MemWrite == 4'b1100) ? HALF : BYTE;




wire [`INSTRUCTION_WIDTH-1:0] mips_instruction;

wire [ 5:0] opcode                 = mips_instruction[`INSTR_OPCODE];
wire [ 4:0] register_source        = mips_instruction[`INSTR_RS];
wire [ 4:0] register_target        = mips_instruction[`INSTR_RT];
wire [ 4:0] register_destination   = mips_instruction[`INSTR_RD];
wire [ 4:0] shift_amount           = mips_instruction[`INSTR_SHAMT];
wire [ 5:0] funct                  = mips_instruction[`INSTR_FUNCT];

wire [15:0] immediate              = mips_instruction[`INSTR_IMM16];

wire [25:0] jump_address           = mips_instruction[`INSTR_IMM26];

wire [`REGISTER_WIDTH-1:0] final_pc;
wire [`REGISTER_WIDTH-1:0] next_pc;
wire [`REGISTER_WIDTH-1:0] branch_pc_offset;
wire [`REGISTER_WIDTH-1:0] branch_pc_offset_sign_extended;
wire [`REGISTER_WIDTH-1:0] branch_pc;
wire [`REGISTER_WIDTH-1:0] pc;

wire [`ALU_OP_CODE_WIDTH-1:0] ALUOp;
wire [1:0] RegInSelect;
wire [1:0] RegWriteDst;
wire [1:0] PCSrc;
wire ALUSrc;
wire RegWrite;
wire SignExtImm;

wire [`REGISTER_WIDTH-1:0] alu_b;
wire [`REGISTER_WIDTH-1:0] alu_result;
wire [`REGISTER_WIDTH-1:0] memory_to_reg_data;
wire zero;
wire tribuffer_enable;
wire less_than_eq;
wire greater_than;

wire [`REGISTER_WIDTH-1:0] read_data_1;
wire [`REGISTER_WIDTH-1:0] read_data_2;
wire [$clog2(`NUMBER_OF_REGISTERS)-1:0] write_address;
wire [`REGISTER_WIDTH-1:0] immediate_extended;
wire [`REGISTER_WIDTH-1:0] DataBusByteShifted;
wire [`REGISTER_WIDTH-1:0] DataBusByte = DataBusByteShifted & 8'hFF;
wire [`REGISTER_WIDTH-1:0] write_data;

wire [1:0] data_out_bus_select;
wire [`REGISTER_WIDTH-1:0] data_out;

PROCESSOR_DECODER decoder(
    .opcode(opcode),
    .funct(funct),
    .alu_result(alu_result),
    .zero(zero),
    .less_than_eq(less_than_eq),
    .greater_than(greater_than),
    .BusCycle(BusCycle),
    .RegWriteDst(RegWriteDst),
    .RegInSelect(RegInSelect),
    .PCSrc(PCSrc),
    .ALUSrc(ALUSrc),
    .SignExtImm(SignExtImm),
    .RegWrite(RegWrite),
    .MemWrite(MemWrite),
    .MemRead(MemRead),
    .ALUOp(ALUOp)
);

REGISTER #(.WIDTH(`REGISTER_WIDTH)) pc_register (
	.rst(rst),
	.clk(clk),
	.load(1'b1),
	.D(final_pc),
	.Q(pc)
);

ADDER #(.WIDTH(`REGISTER_WIDTH)) adder (
	.a(pc),
    .b(32'h4),
	.y(next_pc)
);

MUX #(
    .WIDTH($clog2(`NUMBER_OF_REGISTERS)),
    .INPUTS(3)
) register_destination_mux (
    .select(RegWriteDst),
    .in({ `RETURN_ADDRESS_REGISTER, register_target, register_destination }),
    .out(write_address)
);

REGFILE regfile(
	.clk(clk),
	.read_address_1(register_source),
    .read_address_2(register_target),
    .write_address(write_address),
	.write_enable(RegWrite),
	.write_data(write_data),
	.read_data_1(read_data_1),
    .read_data_2(read_data_2)
);


VALUE_EXTEND #(
    .INPUT_WIDTH(16),
    .OUTPUT_WIDTH(`REGISTER_WIDTH)
) sign_extend_immediate (
    .sign_extend(SignExtImm),
	.a(immediate),
	.y(immediate_extended)

);

SHIFT_LEFT #(.AMOUNT(2))
branch_shift_immediate
(
	.a(immediate_extended),

    .y(branch_pc_offset)
);

VALUE_EXTEND #(
    .INPUT_WIDTH(16),
    .OUTPUT_WIDTH(`REGISTER_WIDTH)
) branch_pc_offset_sign_extend
(
    .sign_extend(1),
	.a(branch_pc_offset),
	.y(branch_pc_offset_sign_extended)
);

ADDER #(.WIDTH(`REGISTER_WIDTH)) branch_pc_adder (
	.a(branch_pc_offset_sign_extended),
    .b(next_pc),
	.y(branch_pc)
);

MUX #(
    .WIDTH(`REGISTER_WIDTH),
    .INPUTS(4)
) final_pc_mux (
    .select(PCSrc),
    .in({ alu_result, branch_pc_offset, branch_pc, next_pc }),
    .out(final_pc)
);

MUX #(
    .WIDTH(`REGISTER_WIDTH),
    .INPUTS(2)
) alu_source_mux (
    .select(ALUSrc),
    .in({immediate_extended, read_data_2}),

    .out(alu_b)
);

ALU alu(
    .clk(clk),
    .a(read_data_1),
    .b(alu_b),
    .ALUOp(ALUOp),
    .shift_amount(shift_amount),
    .result(alu_result),
    .zero(zero),
    .less_than_eq(less_than_eq),
    .greater_than(greater_than)
);

OR #(.WIDTH(4)
) mem_write_or (
    .in(MemWrite),
    .out(tribuffer_enable)
);

MUX #(
    .WIDTH(`REGISTER_WIDTH),
    .INPUTS(3)
) data_out_bus_mux (
    .select(data_out_bus_select),
    .in({
        { read_data_2[ 7:0], read_data_2[7:0], read_data_2[ 7:0], read_data_2[7:0] },
        { read_data_2[15:8], read_data_2[7:0], read_data_2[15:8], read_data_2[7:0] },
        read_data_2
    }),
    .out(data_out)
);

TRIBUFFER #(.WIDTH(`REGISTER_WIDTH)
) buffer_databus (
	.oe(tribuffer_enable),
	.in(data_out),
	.out(DataBus)
);





SHIFT_RIGHT #(.WIDTH(`REGISTER_WIDTH)
) shift_data_memory_by_address_offset (
	.a(DataBus),
    .b({ {(`REGISTER_WIDTH-5){1'b0}}, AddressBus[1:0], 3'b0 }),
	.y(DataBusByteShifted)
);

MUX #(
    .WIDTH(`REGISTER_WIDTH),
    .INPUTS(4)
) final_stage_write_data (
    .select(RegInSelect),
    .in({
        DataBusByte,
        next_pc,
        DataBus,
        alu_result
    }),
    .out(write_data)
);








endmodule
module MIPS(
    input wire clk,
    input wire rst,
    output wire BusCycle,
    output wire [3:0] MemWrite,
    output wire MemRead,
    output wire [`REGISTER_WIDTH-1:0] AddressBus,
    output wire [`REGISTER_WIDTH-1:0] DataBus,
    output wire [`REGISTER_WIDTH-1:0] ProgramCounter,
    output wire [`REGISTER_WIDTH-1:0] ALUResult,
    output wire [`REGISTER_WIDTH-1:0] RegOut1,
    output wire [`REGISTER_WIDTH-1:0] RegOut2,
    output wire [`REGISTER_WIDTH-1:0] RegWriteData,
    output wire [`REGISTER_WIDTH-1:0] RegWriteAddress,
    input wire  [`REGISTER_WIDTH-1:0] Instruction
);




parameter BYTE = 2'd2;
parameter HALF = 2'd1;
parameter WORD = 2'd0;



assign AddressBus                   = (BusCycle) ? alu_result : `REGISTER_WIDTH'b0;
assign ALUResult                    = alu_result;
assign ProgramCounter               = pc;
assign mips_instruction             = Instruction;
assign RegOut1                      = read_data_1;
assign RegOut2                      = read_data_2;
assign RegWriteData                 = write_data;
assign RegWriteAddress              = write_address;
assign data_out_bus_select          = (MemWrite == 4'b1111) ? WORD : (MemWrite == 4'b0011 || MemWrite == 4'b1100) ? HALF : BYTE;




wire [`INSTRUCTION_WIDTH-1:0] mips_instruction;

wire [ 5:0] opcode                 = mips_instruction[`INSTR_OPCODE];
wire [ 4:0] register_source        = mips_instruction[`INSTR_RS];
wire [ 4:0] register_target        = mips_instruction[`INSTR_RT];
wire [ 4:0] register_destination   = mips_instruction[`INSTR_RD];
wire [ 4:0] shift_amount           = mips_instruction[`INSTR_SHAMT];
wire [ 5:0] funct                  = mips_instruction[`INSTR_FUNCT];

wire [15:0] immediate              = mips_instruction[`INSTR_IMM16];

wire [25:0] jump_address           = mips_instruction[`INSTR_IMM26];

wire [`REGISTER_WIDTH-1:0] final_pc;
wire [`REGISTER_WIDTH-1:0] next_pc;
wire [`REGISTER_WIDTH-1:0] branch_pc_offset;
wire [`REGISTER_WIDTH-1:0] branch_pc_offset_sign_extended;
wire [`REGISTER_WIDTH-1:0] branch_pc;
wire [`REGISTER_WIDTH-1:0] pc;

wire [`ALU_OP_CODE_WIDTH-1:0] ALUOp;
wire [1:0] RegInSelect;
wire [1:0] RegWriteDst;
wire [1:0] PCSrc;
wire ALUSrc;
wire RegWrite;
wire SignExtImm;

wire [`REGISTER_WIDTH-1:0] alu_b;
wire [`REGISTER_WIDTH-1:0] alu_result;
wire [`REGISTER_WIDTH-1:0] memory_to_reg_data;
wire zero;
wire tribuffer_enable;
wire less_than_eq;
wire greater_than;

wire [`REGISTER_WIDTH-1:0] read_data_1;
wire [`REGISTER_WIDTH-1:0] read_data_2;
wire [$clog2(`NUMBER_OF_REGISTERS)-1:0] write_address;
wire [`REGISTER_WIDTH-1:0] immediate_extended;
wire [`REGISTER_WIDTH-1:0] DataBusByteShifted;
wire [`REGISTER_WIDTH-1:0] DataBusByte = DataBusByteShifted & 8'hFF;
wire [`REGISTER_WIDTH-1:0] write_data;

wire [1:0] data_out_bus_select;
wire [`REGISTER_WIDTH-1:0] data_out;

PROCESSOR_DECODER decoder(
    .opcode(opcode),
    .funct(funct),
    .alu_result(alu_result),
    .zero(zero),
    .less_than_eq(less_than_eq),
    .greater_than(greater_than),
    .BusCycle(BusCycle),
    .RegWriteDst(RegWriteDst),
    .RegInSelect(RegInSelect),
    .PCSrc(PCSrc),
    .ALUSrc(ALUSrc),
    .SignExtImm(SignExtImm),
    .RegWrite(RegWrite),
    .MemWrite(MemWrite),
    .MemRead(MemRead),
    .ALUOp(ALUOp)
);

REGISTER #(.WIDTH(`REGISTER_WIDTH)) pc_register (
	.rst(rst),
	.clk(clk),
	.load(1'b1),
	.D(final_pc),
	.Q(pc)
);

ADDER #(.WIDTH(`REGISTER_WIDTH)) adder (
	.a(pc),
    .b(32'h4),
	.y(next_pc)
);

MUX #(
    .WIDTH($clog2(`NUMBER_OF_REGISTERS)),
    .INPUTS(3)
) register_destination_mux (
    .select(RegWriteDst),
    .in({ `RETURN_ADDRESS_REGISTER, register_target, register_destination }),
    .out(write_address)
);

REGFILE regfile(
	.clk(clk),
	.read_address_1(register_source),
    .read_address_2(register_target),
    .write_address(write_address),
	.write_enable(RegWrite),
	.write_data(write_data),
	.read_data_1(read_data_1),
    .read_data_2(read_data_2)
);


VALUE_EXTEND #(
    .INPUT_WIDTH(16),
    .OUTPUT_WIDTH(`REGISTER_WIDTH)
) sign_extend_immediate (
    .sign_extend(SignExtImm),
	.a(immediate),
	.y(immediate_extended)

);

SHIFT_LEFT #(.AMOUNT(2))
branch_shift_immediate
(
	.a(immediate_extended),

    .y(branch_pc_offset)
);

VALUE_EXTEND #(
    .INPUT_WIDTH(16),
    .OUTPUT_WIDTH(`REGISTER_WIDTH)
) branch_pc_offset_sign_extend
(
    .sign_extend(1),
	.a(branch_pc_offset),
	.y(branch_pc_offset_sign_extended)
);

ADDER #(.WIDTH(`REGISTER_WIDTH)) branch_pc_adder (
	.a(branch_pc_offset_sign_extended),
    .b(next_pc),
	.y(branch_pc)
);

MUX #(
    .WIDTH(`REGISTER_WIDTH),
    .INPUTS(4)
) final_pc_mux (
    .select(PCSrc),
    .in({ alu_result, branch_pc_offset, branch_pc, next_pc }),
    .out(final_pc)
);

MUX #(
    .WIDTH(`REGISTER_WIDTH),
    .INPUTS(2)
) alu_source_mux (
    .select(ALUSrc),
    .in({immediate_extended, read_data_2}),

    .out(alu_b)
);

ALU alu(
    .clk(clk),
    .a(read_data_1),
    .b(alu_b),
    .ALUOp(ALUOp),
    .shift_amount(shift_amount),
    .result(alu_result),
    .zero(zero),
    .less_than_eq(less_than_eq),
    .greater_than(greater_than)
);

OR #(.WIDTH(4)
) mem_write_or (
    .in(MemWrite),
    .out(tribuffer_enable)
);

MUX #(
    .WIDTH(`REGISTER_WIDTH),
    .INPUTS(3)
) data_out_bus_mux (
    .select(data_out_bus_select),
    .in({
        { read_data_2[ 7:0], read_data_2[7:0], read_data_2[ 7:0], read_data_2[7:0] },
        { read_data_2[15:8], read_data_2[7:0], read_data_2[15:8], read_data_2[7:0] },
        read_data_2
    }),
    .out(data_out)
);

TRIBUFFER #(.WIDTH(`REGISTER_WIDTH)
) buffer_databus (
	.oe(tribuffer_enable),
	.in(data_out),
	.out(DataBus)
);





SHIFT_RIGHT #(.WIDTH(`REGISTER_WIDTH)
) shift_data_memory_by_address_offset (
	.a(DataBus),
    .b({ {(`REGISTER_WIDTH-5){1'b0}}, AddressBus[1:0], 3'b0 }),
	.y(DataBusByteShifted)
);

MUX #(
    .WIDTH(`REGISTER_WIDTH),
    .INPUTS(4)
) final_stage_write_data (
    .select(RegInSelect),
    .in({
        DataBusByte,
        next_pc,
        DataBus,
        alu_result
    }),
    .out(write_data)
);








endmodule