data/full_repos/permissive/160024456/day02/part1_test.v
 line:18: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/160024456/day02/part1_test.v:11: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = !clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/160024456/day02/part1_test.v:15: Unsupported or unknown PLI call: $monitor\n    $monitor("time=", $time, ", clk=", clk, ", en=", en, ", pairs=", pairs, ", triplets=", triplets, ", product=", product);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/160024456/day02/part1_test.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #10 en = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/day02/part1_test.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10000 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module part1_test;

  reg clk = 0;
  reg en = 0;
  wire [7:0] pairs;
  wire [7:0] triplets;
  wire [15:0] product;

  part1 dut (.clk(clk), .en(en), .pairs(pairs), .triplets(triplets), .product(product));

  always #5 clk = !clk;

  initial begin
    $display("start");
    $monitor("time=", $time, ", clk=", clk, ", en=", en, ", pairs=", pairs, ", triplets=", triplets, ", product=", product);

    #10 en = 1;
    #10000 $finish;
  end

endmodule
module part1_test;


  reg clk = 0;
  reg en = 0;
  wire [7:0] pairs;
  wire [7:0] triplets;
  wire [15:0] product;

  part1 dut (.clk(clk), .en(en), .pairs(pairs), .triplets(triplets), .product(product));

  always #5 clk = !clk;

  initial begin
    $display("start");
    $monitor("time=", $time, ", clk=", clk, ", en=", en, ", pairs=", pairs, ", triplets=", triplets, ", product=", product);

    #10 en = 1;
    #10000 $finish;
  end

endmodule