data/full_repos/permissive/179884651/library/WF_RGB_if.v
1: b"%Error: data/full_repos/permissive/179884651/library/WF_RGB_if.v:37: Duplicate declaration of signal: 'scan_done'\n                                                                   : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire scan_done = dotclk_done;\n       ^~~~~~~~~\n        data/full_repos/permissive/179884651/library/WF_RGB_if.v:27: ... Location of original declaration\n          output scan_done,  \n                 ^~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module WF_RGB_if(
          input  clk,
          input  scan_en,
          output scan_done,

          output [5:0]  ram_rd_addr,
          input  [15:0] ram_rd_pixels,

          output reg  CLK_OUT,
          output wire LOAD,
          output wire DOUT
  );

  wire scan_done = dotclk_done;


  reg        phase_col;
  reg        phase_rd;
  reg [5:0]  dotclk_index;
  reg [2:0]  dotclk_index_d;
  reg        dotclk_en;
  reg        dotclk_en_d;
  wire       dotclk_done;
  reg        dotclk_done_d;
  reg        phase_row;
  reg [7:0]  row;
  reg [2:0]  row_addr;
  reg [23:0] data_next;
  reg [23:0] data_out;





     always @ (posedge clk)
       begin
         if (row == 8'h0)
           row <= 8'hfe;

         if (dotclk_done )
           row <= {row[6:0],row[7]};
       end









    always@ (posedge clk)
      if (scan_en)

        phase_rd <= 1'b1;
      else
        begin
          if (dotclk_index == 15 && phase_rd)
            begin
              phase_rd     <= 1'b0;
              phase_col    <= 1'b1;
              dotclk_index <= 0;
              dotclk_en    <= 1'b1;
            end
          else
            if (phase_rd || phase_col || phase_row)
              dotclk_index <= dotclk_index + 'b1;

          if (dotclk_index == 47)
            begin
              phase_col    <= 1'b0;
              phase_row    <= 1'b1;
            end
          if (dotclk_index == 6'd63)
            begin
              dotclk_en    <= 1'b0;
              phase_row    <= 1'b0;
            end
        end






   always @(*)
         case (row)
             8'b1111_1110 : row_addr <= 3'h0;
             8'b1111_1101 : row_addr <= 3'h1;
             8'b1111_1011 : row_addr <= 3'h2;
             8'b1111_0111 : row_addr <= 3'h3;
             8'b1110_1111 : row_addr <= 3'h4;
             8'b1101_1111 : row_addr <= 3'h5;
             8'b1011_1111 : row_addr <= 3'h6;
             8'b0111_1111 : row_addr <= 3'h7;
         endcase



    assign ram_rd_addr =  {row_addr,dotclk_index[2:0]};


    always@ (posedge clk)
      if (phase_row)
         begin
           dotclk_index_d <= dotclk_index[2:0];

           data_next[dotclk_index_d[2:0]]    <= ram_rd_pixels[0];
           data_next[dotclk_index_d[2:0]+16] <= ram_rd_pixels[5];
           data_next[dotclk_index_d[2:0]+8]  <= ram_rd_pixels[10];
       end





     always @ (posedge clk)
       if (dotclk_en)
         CLK_OUT <= ~CLK_OUT;
       else
         CLK_OUT <= 1'b0;






     always @ (posedge clk)
       if (dotclk_en )
         begin
           if (dotclk_index == 47)
             data_out <= {row, 16'b0};
           else
             if (dotclk_index[0])
             data_out <= {data_out[22:0],1'b0};
         end
       else
         data_out <= data_next;

     always @ (posedge clk)
       begin
         dotclk_en_d   <= dotclk_en;
         dotclk_done_d <= dotclk_done;
       end


     assign LOAD = ~dotclk_en;
     assign DOUT = data_out[23];

     assign dotclk_done = ~dotclk_en && dotclk_en_d;

endmodule
module WF_RGB_if(
          input  clk,
          input  scan_en,
          output scan_done,

          output [5:0]  ram_rd_addr,
          input  [15:0] ram_rd_pixels,

          output reg  CLK_OUT,
          output wire LOAD,
          output wire DOUT
  );


  wire scan_done = dotclk_done;


  reg        phase_col;
  reg        phase_rd;
  reg [5:0]  dotclk_index;
  reg [2:0]  dotclk_index_d;
  reg        dotclk_en;
  reg        dotclk_en_d;
  wire       dotclk_done;
  reg        dotclk_done_d;
  reg        phase_row;
  reg [7:0]  row;
  reg [2:0]  row_addr;
  reg [23:0] data_next;
  reg [23:0] data_out;





     always @ (posedge clk)
       begin
         if (row == 8'h0)
           row <= 8'hfe;

         if (dotclk_done )
           row <= {row[6:0],row[7]};
       end









    always@ (posedge clk)
      if (scan_en)

        phase_rd <= 1'b1;
      else
        begin
          if (dotclk_index == 15 && phase_rd)
            begin
              phase_rd     <= 1'b0;
              phase_col    <= 1'b1;
              dotclk_index <= 0;
              dotclk_en    <= 1'b1;
            end
          else
            if (phase_rd || phase_col || phase_row)
              dotclk_index <= dotclk_index + 'b1;

          if (dotclk_index == 47)
            begin
              phase_col    <= 1'b0;
              phase_row    <= 1'b1;
            end
          if (dotclk_index == 6'd63)
            begin
              dotclk_en    <= 1'b0;
              phase_row    <= 1'b0;
            end
        end






   always @(*)
         case (row)
             8'b1111_1110 : row_addr <= 3'h0;
             8'b1111_1101 : row_addr <= 3'h1;
             8'b1111_1011 : row_addr <= 3'h2;
             8'b1111_0111 : row_addr <= 3'h3;
             8'b1110_1111 : row_addr <= 3'h4;
             8'b1101_1111 : row_addr <= 3'h5;
             8'b1011_1111 : row_addr <= 3'h6;
             8'b0111_1111 : row_addr <= 3'h7;
         endcase



    assign ram_rd_addr =  {row_addr,dotclk_index[2:0]};


    always@ (posedge clk)
      if (phase_row)
         begin
           dotclk_index_d <= dotclk_index[2:0];

           data_next[dotclk_index_d[2:0]]    <= ram_rd_pixels[0];
           data_next[dotclk_index_d[2:0]+16] <= ram_rd_pixels[5];
           data_next[dotclk_index_d[2:0]+8]  <= ram_rd_pixels[10];
       end





     always @ (posedge clk)
       if (dotclk_en)
         CLK_OUT <= ~CLK_OUT;
       else
         CLK_OUT <= 1'b0;






     always @ (posedge clk)
       if (dotclk_en )
         begin
           if (dotclk_index == 47)
             data_out <= {row, 16'b0};
           else
             if (dotclk_index[0])
             data_out <= {data_out[22:0],1'b0};
         end
       else
         data_out <= data_next;

     always @ (posedge clk)
       begin
         dotclk_en_d   <= dotclk_en;
         dotclk_done_d <= dotclk_done;
       end


     assign LOAD = ~dotclk_en;
     assign DOUT = data_out[23];

     assign dotclk_done = ~dotclk_en && dotclk_en_d;

endmodule