data/full_repos/permissive/217060808/bsg_async/bsg_async_ptr_gray/bsg_async_ptr_gray_lg_size_p_8_use_negedge_for_launch_p_1_use_async_reset_p_0/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_ptr_gray/bsg_async_ptr_gray_lg_size_p_8_use_negedge_for_launch_p_1_use_async_reset_p_0/top.v:58: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                        : ... In instance top.wrapper.ptr_sync.sync_n_maxb_0___05Fblss\n                                                (N1)? iclk_data_i : 1\'b0;\n                                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_ptr_gray/bsg_async_ptr_gray_lg_size_p_8_use_negedge_for_launch_p_1_use_async_reset_p_0/top.v:152: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                         : ... In instance top.wrapper\n                        (N1)? w_ptr_gray_r_o : 1\'b0;\n                            ^\n%Error: Exiting due to 2 warning(s)\n'
module bsg_async_ptr_gray
(
  w_clk_i,
  w_reset_i,
  w_inc_i,
  r_clk_i,
  w_ptr_binary_r_o,
  w_ptr_gray_r_o,
  w_ptr_gray_r_rsync_o
);

  output [7:0] w_ptr_binary_r_o;
  output [7:0] w_ptr_gray_r_o;
  output [7:0] w_ptr_gray_r_rsync_o;
  input w_clk_i;
  input w_reset_i;
  input w_inc_i;
  input r_clk_i;
  wire [7:0] w_ptr_gray_r_o,w_ptr_gray_r_rsync_o,w_ptr_p2,w_ptr_gray_n;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10;
  reg [7:0] w_ptr_p1_r,w_ptr_binary_r_o;

  bsg_launch_sync_sync_width_p8_use_negedge_for_launch_p1_use_async_reset_p0
  ptr_sync
  (
    .iclk_i(w_clk_i),
    .iclk_reset_i(w_reset_i),
    .oclk_i(r_clk_i),
    .iclk_data_i(w_ptr_gray_n),
    .iclk_data_o(w_ptr_gray_r_o),
    .oclk_data_o(w_ptr_gray_r_rsync_o)
  );

  assign w_ptr_p2 = w_ptr_p1_r + 1'b1;
  assign w_ptr_gray_n = (N0)? { w_ptr_p1_r[7:7], N3, N4, N5, N6, N7, N8, N9 } : 
                        (N1)? w_ptr_gray_r_o : 1'b0;
  assign N0 = w_inc_i;
  assign N1 = N2;
  assign N2 = ~w_inc_i;
  assign N3 = w_ptr_p1_r[7] ^ w_ptr_p1_r[6];
  assign N4 = w_ptr_p1_r[6] ^ w_ptr_p1_r[5];
  assign N5 = w_ptr_p1_r[5] ^ w_ptr_p1_r[4];
  assign N6 = w_ptr_p1_r[4] ^ w_ptr_p1_r[3];
  assign N7 = w_ptr_p1_r[3] ^ w_ptr_p1_r[2];
  assign N8 = w_ptr_p1_r[2] ^ w_ptr_p1_r[1];
  assign N9 = w_ptr_p1_r[1] ^ w_ptr_p1_r[0];
  assign N10 = ~w_clk_i;

  always @(posedge N10) begin
    if(w_reset_i) begin
      { w_ptr_p1_r[7:0] } <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 };
      { w_ptr_binary_r_o[7:0] } <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
    end else if(w_inc_i) begin
      { w_ptr_p1_r[7:0] } <= { w_ptr_p2[7:0] };
      { w_ptr_binary_r_o[7:0] } <= { w_ptr_p1_r[7:0] };
    end 
  end


endmodule
module bsg_async_ptr_gray
(
  w_clk_i,
  w_reset_i,
  w_inc_i,
  r_clk_i,
  w_ptr_binary_r_o,
  w_ptr_gray_r_o,
  w_ptr_gray_r_rsync_o
);


  output [7:0] w_ptr_binary_r_o;
  output [7:0] w_ptr_gray_r_o;
  output [7:0] w_ptr_gray_r_rsync_o;
  input w_clk_i;
  input w_reset_i;
  input w_inc_i;
  input r_clk_i;
  wire [7:0] w_ptr_gray_r_o,w_ptr_gray_r_rsync_o,w_ptr_p2,w_ptr_gray_n;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10;
  reg [7:0] w_ptr_p1_r,w_ptr_binary_r_o;

  bsg_launch_sync_sync_width_p8_use_negedge_for_launch_p1_use_async_reset_p0
  ptr_sync
  (
    .iclk_i(w_clk_i),
    .iclk_reset_i(w_reset_i),
    .oclk_i(r_clk_i),
    .iclk_data_i(w_ptr_gray_n),
    .iclk_data_o(w_ptr_gray_r_o),
    .oclk_data_o(w_ptr_gray_r_rsync_o)
  );

  assign w_ptr_p2 = w_ptr_p1_r + 1'b1;
  assign w_ptr_gray_n = (N0)? { w_ptr_p1_r[7:7], N3, N4, N5, N6, N7, N8, N9 } : 
                        (N1)? w_ptr_gray_r_o : 1'b0;
  assign N0 = w_inc_i;
  assign N1 = N2;
  assign N2 = ~w_inc_i;
  assign N3 = w_ptr_p1_r[7] ^ w_ptr_p1_r[6];
  assign N4 = w_ptr_p1_r[6] ^ w_ptr_p1_r[5];
  assign N5 = w_ptr_p1_r[5] ^ w_ptr_p1_r[4];
  assign N6 = w_ptr_p1_r[4] ^ w_ptr_p1_r[3];
  assign N7 = w_ptr_p1_r[3] ^ w_ptr_p1_r[2];
  assign N8 = w_ptr_p1_r[2] ^ w_ptr_p1_r[1];
  assign N9 = w_ptr_p1_r[1] ^ w_ptr_p1_r[0];
  assign N10 = ~w_clk_i;

  always @(posedge N10) begin
    if(w_reset_i) begin
      { w_ptr_p1_r[7:0] } <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 };
      { w_ptr_binary_r_o[7:0] } <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
    end else if(w_inc_i) begin
      { w_ptr_p1_r[7:0] } <= { w_ptr_p2[7:0] };
      { w_ptr_binary_r_o[7:0] } <= { w_ptr_p1_r[7:0] };
    end 
  end


endmodule