data/full_repos/permissive/175132042/testbench/fw_interface/fw_interface_logic.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/175132042/testbench/fw_interface/fw_interface_logic.v:11: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/testbench/fw_interface,data/full_repos/permissive/175132042/timescale.v\n             data/full_repos/permissive/175132042/testbench/fw_interface,data/full_repos/permissive/175132042/timescale.v.v\n             data/full_repos/permissive/175132042/testbench/fw_interface,data/full_repos/permissive/175132042/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n'
module fw_interface_logic (

                           wb_clk_i, wb_rst_i, new_report, new_warning, new_error,
                           new_compare, report_reg, warning_reg, error_reg, expected_reg,
                           measured_reg, index, data, write_mem
                           ) ;

   input wire wb_clk_i;
   input wire wb_rst_i;


   input wire new_report;
   input wire new_warning;
   input wire new_error;
   input wire new_compare;

   input wire [31:0] report_reg;
   input wire [31:0] warning_reg;
   input wire [31:0] error_reg;
   input wire [31:0] expected_reg;
   input wire [31:0] measured_reg;   
   input wire [5:0]  index;
   input wire [7:0]  data;
   input wire        write_mem;
   
`ifdef SIMULATION   
   reg [7:0]         string_mem[31:0];
   
   always @(posedge wb_clk_i)
     if (write_mem) begin
        string_mem[index] <= data;
        string_mem[index+1] <= 0;

     end
   
   wire new_report_rising;   
   edge_detection new_report_edge(

                                  .rising(new_report_rising), 
                                  .failling(),

                                  .clk_i(wb_clk_i), 
                                  .rst_i(wb_rst_i), 
                                  .signal(new_report)
                                  );

   integer i;
   reg [(8*32)-1:0] test_string;   
   always @ (posedge new_report_rising) begin
      i = 0;        
      test_string = 0;
      while (string_mem[i] != 8'h0) begin
	     #1 test_string = {test_string[8*29:0], string_mem[i]};
         #1 string_mem[i] = 0;
         #1 i = i + 1;
      end

      `TEST_COMPARE(test_string,0,0);
   end


   wire new_compare_rising;
   edge_detection new_compare_edge(

                                   .rising(new_compare_rising),
                                   .failling(),

                                   .clk_i(wb_clk_i),
                                   .rst_i(wb_rst_i),
                                   .signal(new_compare)
                                   );
   

   
`endif
   
endmodule
module fw_interface_logic (

                           wb_clk_i, wb_rst_i, new_report, new_warning, new_error,
                           new_compare, report_reg, warning_reg, error_reg, expected_reg,
                           measured_reg, index, data, write_mem
                           ) ;


   input wire wb_clk_i;
   input wire wb_rst_i;


   input wire new_report;
   input wire new_warning;
   input wire new_error;
   input wire new_compare;

   input wire [31:0] report_reg;
   input wire [31:0] warning_reg;
   input wire [31:0] error_reg;
   input wire [31:0] expected_reg;
   input wire [31:0] measured_reg;   
   input wire [5:0]  index;
   input wire [7:0]  data;
   input wire        write_mem;
   
`ifdef SIMULATION   
   reg [7:0]         string_mem[31:0];
   
   always @(posedge wb_clk_i)
     if (write_mem) begin
        string_mem[index] <= data;
        string_mem[index+1] <= 0;

     end
   
   wire new_report_rising;   
   edge_detection new_report_edge(

                                  .rising(new_report_rising), 
                                  .failling(),

                                  .clk_i(wb_clk_i), 
                                  .rst_i(wb_rst_i), 
                                  .signal(new_report)
                                  );

   integer i;
   reg [(8*32)-1:0] test_string;   
   always @ (posedge new_report_rising) begin
      i = 0;        
      test_string = 0;
      while (string_mem[i] != 8'h0) begin
	     #1 test_string = {test_string[8*29:0], string_mem[i]};
         #1 string_mem[i] = 0;
         #1 i = i + 1;
      end

      `TEST_COMPARE(test_string,0,0);
   end


   wire new_compare_rising;
   edge_detection new_compare_edge(

                                   .rising(new_compare_rising),
                                   .failling(),

                                   .clk_i(wb_clk_i),
                                   .rst_i(wb_rst_i),
                                   .signal(new_compare)
                                   );
   

   
`endif
   
endmodule