data/full_repos/permissive/152142712/v1/framegen.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/152142712/v1/framegen.v:80: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                        : ... Top module \'framegen\'\nmodule framegen (\n       ^~~~~~~~\n                                                                        : ... Top module \'framebuffer\'\nmodule framebuffer (\n       ^~~~~~~~~~~\n                                                                        : ... Top module \'audiogen\'\nmodule audiogen (\n       ^~~~~~~~\n%Warning-UNSIGNED: data/full_repos/permissive/152142712/v1/framegen.v:47: Comparison is constant due to unsigned arithmetic\n                                                                        : ... In instance framegen\n      if (hc >= 9\'d0 && hc < 9\'d384 && vc >= 9\'d0 && vc < 9\'d288) begin   \n             ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152142712/v1/framegen.v:47: Comparison is constant due to unsigned arithmetic\n                                                                        : ... In instance framegen\n      if (hc >= 9\'d0 && hc < 9\'d384 && vc >= 9\'d0 && vc < 9\'d288) begin   \n                                          ^~\n%Error: Exiting due to 3 warning(s)\n'
module framebuffer (
  input wire clk,
  input wire [13:0] addrr,
  input wire [13:0] addrw,
  input wire we,
  input wire [7:0] din,
  output reg [7:0] dout
  );
  
  reg [7:0] mem[0:16383];
  integer i;
  initial begin
    for (i=0;i<16384;i=i+1) begin
      mem[i] = 8'h00;
    end

    $readmemh ("cat.hex", mem);
  end
  
  always @(posedge clk) begin
    dout <= mem[addrr];
    if (we == 1'b1)
      mem[addrw] <= din;
  end
endmodule
module framebuffer (
  input wire clk,
  input wire [13:0] addrr,
  input wire [13:0] addrw,
  input wire we,
  input wire [7:0] din,
  output reg [7:0] dout
  );

  
  reg [7:0] mem[0:16383];
  integer i;
  initial begin
    for (i=0;i<16384;i=i+1) begin
      mem[i] = 8'h00;
    end

    $readmemh ("cat.hex", mem);
  end
  
  always @(posedge clk) begin
    dout <= mem[addrr];
    if (we == 1'b1)
      mem[addrw] <= din;
  end
endmodule