data/full_repos/permissive/121864698/ControlUnit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/121864698/ControlUnit.v:19: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                     : ... In instance control\nMux2<=1\'b1;\n    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/121864698/ControlUnit.v:39: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                     : ... In instance control\nMux2<=1\'b0;\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/121864698/ControlUnit.v:279: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                      : ... In instance control\nMux2<=1\'b0;\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/121864698/ControlUnit.v:293: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                      : ... In instance control\nMux2<=1\'b1;\n    ^~\n%Error: Exiting due to 4 warning(s)\n'
module control(alu_op,opcode,clk,carry,reset,reg_wrt,re,wr,Mux1,Mux2,Mux3,MuxAlu,Mux5,branch,pc_sel,im_select);
input clk,carry,reset;
input [3:0] opcode;
output reg[3:0]alu_op;
output reg reg_wrt,re,wr,Mux1,Mux3,MuxAlu,Mux5,branch,pc_sel,im_select;
output reg[1:0]Mux2;
reg [3:0]pstate,nstate;
parameter s0 = 4'b0000,s1 = 4'b0001, s2=4'b0010, s3=4'b0011, s4=4'b0100, s5=4'b0101, s6=4'b0110, s7=4'b0111, s11=4'b1000;
initial
pstate = s0;
always @(posedge clk)begin
case(pstate)
/
alu_op<=4'b0001;    
reg_wrt<=1'b1;
re<=1'b0;
wr<=1'b0;
Mux1<=1'b1;
Mux2<=2'b0;
Mux3<=1'b0;
Mux5<=1'b1;
MuxAlu<=1'b0;
branch<=1'b0;
pc_sel<=1'b0;
im_select<=1'b1;
pstate<=s0;
end
/
/
alu_op<=4'b0;
reg_wrt<=1'b1;
re<=1'b1;
wr<=1'b0;
Mux1<=1'b0;
Mux2<=2'b01;
Mux3<=1'b1;
Mux5<=1'b1;
MuxAlu<=1'b0;
branch<=1'b0;
pc_sel<=1'b0;
im_select<=1'b1;
pstate<=s0;
end
/
alu_op<=4'b0;
reg_wrt<=1'b0;
re<=1'b0;
wr<=1'b1;
Mux1<=1'b1;
Mux2<=2'b01;
Mux3<=1'b1;
Mux5<=1'b1;
MuxAlu<=1'b0;
branch<=1'b0;
pc_sel<=1'b0;
im_select<=1'b1;
pstate<=s0;
end
/
alu_op<=4'b0001;
reg_wrt<=1'b0;
re<=1'b0;
wr<=1'b0;
Mux1<=1'b1;
Mux2<=2'b0;
Mux3<=1'b0;
Mux5<=1'b1;
MuxAlu<=1'b0;
branch<=1'b1;
pc_sel<=1'b0;
im_select<=1'b1;
pstate<=s0;
end
/
alu_op<=4'b1110;
reg_wrt<=1'b0;
re<=1'b0;
wr<=1'b0;
Mux1<=1'b1;
Mux2<=2'b10;
Mux3<=1'b0;
Mux5<=1'b0;
MuxAlu<=1'b0;
branch<=1'b0;
pc_sel<=1'b0;
im_select<=1'b1;
pstate<=s0;
end   
endcase
end
s2:begin
reg_wrt<=1'b0;
re<=1'b0;
wr<=1'b0;
Mux1<=1'b0;
Mux2<=1'b0;
Mux3<=1'b0;
alu_op<=4'bxxxx;
MuxAlu<=1'b0;
branch<=1'b1;
pc_sel<=1'b0;
im_select<=1'b0;
pstate<=s0;
end
s3:begin
reg_wrt<=1'b1;
re<=1'bx;
wr<=1'b0;
Mux1<=1'b1;
Mux2<=1'b1;
Mux3<=1'b1;
alu_op<=4'bxxxx;
MuxAlu<=1'b0;
branch<=1'b0;
pc_sel<=1'b0;
im_select<=1'b0;
pstate<=s0;
end
endcase
end
endmodule
module control(alu_op,opcode,clk,carry,reset,reg_wrt,re,wr,Mux1,Mux2,Mux3,MuxAlu,Mux5,branch,pc_sel,im_select);

input clk,carry,reset;
input [3:0] opcode;
output reg[3:0]alu_op;
output reg reg_wrt,re,wr,Mux1,Mux3,MuxAlu,Mux5,branch,pc_sel,im_select;
output reg[1:0]Mux2;
reg [3:0]pstate,nstate;
parameter s0 = 4'b0000,s1 = 4'b0001, s2=4'b0010, s3=4'b0011, s4=4'b0100, s5=4'b0101, s6=4'b0110, s7=4'b0111, s11=4'b1000;
initial
pstate = s0;
always @(posedge clk)begin
case(pstate)
/
alu_op<=4'b0001;    
reg_wrt<=1'b1;
re<=1'b0;
wr<=1'b0;
Mux1<=1'b1;
Mux2<=2'b0;
Mux3<=1'b0;
Mux5<=1'b1;
MuxAlu<=1'b0;
branch<=1'b0;
pc_sel<=1'b0;
im_select<=1'b1;
pstate<=s0;
end
/
/
alu_op<=4'b0;
reg_wrt<=1'b1;
re<=1'b1;
wr<=1'b0;
Mux1<=1'b0;
Mux2<=2'b01;
Mux3<=1'b1;
Mux5<=1'b1;
MuxAlu<=1'b0;
branch<=1'b0;
pc_sel<=1'b0;
im_select<=1'b1;
pstate<=s0;
end
/
alu_op<=4'b0;
reg_wrt<=1'b0;
re<=1'b0;
wr<=1'b1;
Mux1<=1'b1;
Mux2<=2'b01;
Mux3<=1'b1;
Mux5<=1'b1;
MuxAlu<=1'b0;
branch<=1'b0;
pc_sel<=1'b0;
im_select<=1'b1;
pstate<=s0;
end
/
alu_op<=4'b0001;
reg_wrt<=1'b0;
re<=1'b0;
wr<=1'b0;
Mux1<=1'b1;
Mux2<=2'b0;
Mux3<=1'b0;
Mux5<=1'b1;
MuxAlu<=1'b0;
branch<=1'b1;
pc_sel<=1'b0;
im_select<=1'b1;
pstate<=s0;
end
/
alu_op<=4'b1110;
reg_wrt<=1'b0;
re<=1'b0;
wr<=1'b0;
Mux1<=1'b1;
Mux2<=2'b10;
Mux3<=1'b0;
Mux5<=1'b0;
MuxAlu<=1'b0;
branch<=1'b0;
pc_sel<=1'b0;
im_select<=1'b1;
pstate<=s0;
end   
endcase
end
s2:begin
reg_wrt<=1'b0;
re<=1'b0;
wr<=1'b0;
Mux1<=1'b0;
Mux2<=1'b0;
Mux3<=1'b0;
alu_op<=4'bxxxx;
MuxAlu<=1'b0;
branch<=1'b1;
pc_sel<=1'b0;
im_select<=1'b0;
pstate<=s0;
end
s3:begin
reg_wrt<=1'b1;
re<=1'bx;
wr<=1'b0;
Mux1<=1'b1;
Mux2<=1'b1;
Mux3<=1'b1;
alu_op<=4'bxxxx;
MuxAlu<=1'b0;
branch<=1'b0;
pc_sel<=1'b0;
im_select<=1'b0;
pstate<=s0;
end
endcase
end
endmodule