data/full_repos/permissive/113780415/src/ACounter.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/113780415/src/ACounter.v:17: Too many digits for 7 bit number: 7'b10011111\n       HEXright = 7'b10011111;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:61: Too many digits for 7 bit number: 7'b10011111\n       HEXleft = 7'b10011111;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:66: Too many digits for 7 bit number: 7'b10011111\n       HEXleft = 7'b10011111;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:67: Too many digits for 7 bit number: 7'b10011111\n       HEXright = 7'b10011111;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:71: Too many digits for 7 bit number: 7'b10011111\n       HEXleft = 7'b10011111;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:76: Too many digits for 7 bit number: 7'b10011111\n       HEXleft = 7'b10011111;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:81: Too many digits for 7 bit number: 7'b10011111\n       HEXleft = 7'b10011111;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:86: Too many digits for 7 bit number: 7'b10011111\n       HEXleft = 7'b10011111;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:91: Too many digits for 7 bit number: 7'b10011111\n       HEXleft = 7'b10011111;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:96: Too many digits for 7 bit number: 7'b10011111\n       HEXleft = 7'b10011111;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113780415/src/ACounter.v:106: Too many digits for 7 bit number: 7'b10011111\n       HEXleft = 7'b10011111;\n                 ^~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n"
module displaycounter(clk, clear_b, out);
    input clk;
    input clear_b;
    output [5:0] out;
    reg [5:0] q = 0;

    assign out = q;
    
    always @(posedge clk)
    begin
        if (clear_b == 1'b0)
            q <= 0;
        else if (q == 5'b10100)
            q <= 0;
        else if (clk == 1'b1)
            q <= q + 1'b1;
    end

endmodule
module displaycounter(clk, clear_b, out);

    input clk;
    input clear_b;
    output [5:0] out;
    reg [5:0] q = 0;

    assign out = q;
    
    always @(posedge clk)
    begin
        if (clear_b == 1'b0)
            q <= 0;
        else if (q == 5'b10100)
            q <= 0;
        else if (clk == 1'b1)
            q <= q + 1'b1;
    end

endmodule