data/full_repos/permissive/170267528/state1/TODO/graph/graph/graph2-0.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170267528/state1/TODO/graph/graph/graph2-0.v:74: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                                          : ... In instance graph\n  ramAddress <= 10\'d0;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/TODO/graph/graph/graph2-0.v:100: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                                           : ... In instance graph\n  ramAddress <= 10\'d0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/TODO/graph/graph/graph2-0.v:118: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                                           : ... In instance graph\n  ramAddress <= 10\'d0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/TODO/graph/graph/graph2-0.v:220: Operator AND expects 66 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance graph\n  if( (activePose >> endPose) & 66\'b1 == 66\'b1 ) begin\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/TODO/graph/graph/graph2-0.v:220: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 66 bits.\n                                                                                           : ... In instance graph\n  if( (activePose >> endPose) & 66\'b1 == 66\'b1 ) begin\n  ^~\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/TODO/graph/graph/graph2-0.v:247: Operator AND expects 66 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance graph\n  if ( (activePose >> startPose) & 66\'b1 == 66\'b1 ) begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/TODO/graph/graph/graph2-0.v:247: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 66 bits.\n                                                                                           : ... In instance graph\n  if ( (activePose >> startPose) & 66\'b1 == 66\'b1 ) begin\n  ^~\n%Error: Exiting due to 7 warning(s)\n'
module graph
(
	input CLK,
	input RST_n,
	input [1033:0] edgeMask,
	input [2:0] control,
	input [7:0] startPose,
	input [7:0] endPose,


	output reg [10:0] ramAddress,
	input [15:0] RAMData,

	output reg [1033:0] edgeMask_Reg,
	output reg [109:0] selectEdge,


	output reg [2:0] state

);

parameter FORWARD_INIT = 3'd0;
parameter FORWARD_WORK = 3'd1;
parameter BACKWARD_INIT = 3'd2;
parameter BACKWARD_WORK = 3'd3;
parameter FAIL = 3'd4;
parameter FINISH = 3'd5;


wire [7:0] firstPose = RAMData[15:8];
wire [7:0] secondPose = RAMData[7:0];
wire [65:0] routeLine = (66'b1 << firstPose) | (66'b1 << secondPose);


reg [65:0] activePose;
reg [1033:0] activeEdge[0:9];



reg [3:0] maxLever;
reg [3:0] leverCnt;



always @(posedge CLK ) begin
	if (!RST_n) begin
		ramAddress <= 10'd0;
		leverCnt <= 4'd0;

		activeEdge[0] <= 1034'b0;
		activeEdge[1] <= 1034'b0;
		activeEdge[2] <= 1034'b0;
		activeEdge[3] <= 1034'b0;
		activeEdge[4] <= 1034'b0;
		activeEdge[5] <= 1034'b0;
		activeEdge[6] <= 1034'b0;
		activeEdge[7] <= 1034'b0;
		activeEdge[8] <= 1034'b0;
		activeEdge[9] <= 1034'b0;

		activePose <= 66'b0;

		selectEdge <= 110'd0;
	end

	else

	case(state)

	FORWARD_INIT: begin


		ramAddress <= 10'd0;
		leverCnt <= 4'd0;
		activeEdge[0] <= 1034'b0;
		activeEdge[1] <= 1034'b0;
		activeEdge[2] <= 1034'b0;
		activeEdge[3] <= 1034'b0;
		activeEdge[4] <= 1034'b0;
		activeEdge[5] <= 1034'b0;
		activeEdge[6] <= 1034'b0;
		activeEdge[7] <= 1034'b0;
		activeEdge[8] <= 1034'b0;
		activeEdge[9] <= 1034'b0;

		activePose <= (66'b1 << startPose);
	end

	 BACKWARD_INIT: begin

		ramAddress <= 10'd0;
		leverCnt <= 4'd0;
		activeEdge[0] <= 1034'b0;
		activeEdge[1] <= 1034'b0;
		activeEdge[2] <= 1034'b0;
		activeEdge[3] <= 1034'b0;
		activeEdge[4] <= 1034'b0;
		activeEdge[5] <= 1034'b0;
		activeEdge[6] <= 1034'b0;
		activeEdge[7] <= 1034'b0;
		activeEdge[8] <= 1034'b0;
		activeEdge[9] <= 1034'b0;

		activePose <= (66'b1 << endPose);
	end

	FORWARD_WORK: begin

		if ( ramAddress < 11'd1034 ) begin

			leverCnt <= leverCnt;
			ramAddress <= ramAddress + 11'd1;

			if ( edgeMask_Reg[ramAddress] != 1'b1 ) begin

				if ( (^(activePose & routeLine)) == 1'b1 ) begin
					
					activePose <= activePose | routeLine;
					activeEdge[leverCnt] <= activeEdge[leverCnt] | (1034'b1 << ramAddress);
				end
				else begin
				end
			end
			else begin
			end
		end
		else begin
			leverCnt <= leverCnt + 1'd1;
			ramAddress <= 0;
		end
	end

	BACKWARD_WORK:  begin
		
		if ( ramAddress < 11'd1034 ) begin

			leverCnt <= leverCnt;
			ramAddress <= ramAddress + 11'd1;

			if ( edgeMask_Reg[ramAddress] != 1'b1 ) begin

				if ( (^(activePose & routeLine)) == 1'b1 ) begin
					
					activePose <= activePose | routeLine;
	
					leverCnt <= leverCnt + 1'd1;

					ramAddress <= 11'd0;
					selectEdge[leverCnt*11+:11] <= ramAddress;

				end

				else begin
				end
			end
			else begin
			end
		end
		else begin
		end
	end

	default: begin
	end

	endcase

end




always @(negedge CLK) begin
	if (!RST_n) begin
		maxLever <= 4'd10;
		state <= FORWARD_INIT;
		
	end

	case (state)
	FORWARD_INIT: begin
		maxLever <= 4'd10;

		edgeMask_Reg[1033:0] <= edgeMask[1033:0];

		if ( control == 3'b010  ) begin
			state <= FORWARD_WORK;
		end

	end

	FORWARD_WORK: begin
		if( (activePose >> endPose) & 66'b1 == 66'b1 ) begin
			state <= BACKWARD_INIT;
			edgeMask_Reg <= edgeMask_Reg | 
							~( activeEdge[0] | activeEdge[1] | activeEdge[2] | activeEdge[3]
							| activeEdge[4] | activeEdge[5] | activeEdge[6] | activeEdge[7]
							| activeEdge[8] | activeEdge[9] );
			maxLever <= leverCnt;
			
		end
		else begin
			state <= FORWARD_WORK;
		end

		if ( leverCnt == maxLever ) begin

			state <= FAIL;

		end
	end

	BACKWARD_INIT: begin
		if ( control == 3'b100 ) begin
			state <= BACKWARD_WORK;
		end
	end

	BACKWARD_WORK: begin
		if ( (activePose >> startPose) & 66'b1 == 66'b1 ) begin

			state <= FINISH;
		end
	end

	default: begin
	end

	endcase


end

endmodule
module graph
(
	input CLK,
	input RST_n,
	input [1033:0] edgeMask,
	input [2:0] control,
	input [7:0] startPose,
	input [7:0] endPose,


	output reg [10:0] ramAddress,
	input [15:0] RAMData,

	output reg [1033:0] edgeMask_Reg,
	output reg [109:0] selectEdge,


	output reg [2:0] state

);


parameter FORWARD_INIT = 3'd0;
parameter FORWARD_WORK = 3'd1;
parameter BACKWARD_INIT = 3'd2;
parameter BACKWARD_WORK = 3'd3;
parameter FAIL = 3'd4;
parameter FINISH = 3'd5;


wire [7:0] firstPose = RAMData[15:8];
wire [7:0] secondPose = RAMData[7:0];
wire [65:0] routeLine = (66'b1 << firstPose) | (66'b1 << secondPose);


reg [65:0] activePose;
reg [1033:0] activeEdge[0:9];



reg [3:0] maxLever;
reg [3:0] leverCnt;



always @(posedge CLK ) begin
	if (!RST_n) begin
		ramAddress <= 10'd0;
		leverCnt <= 4'd0;

		activeEdge[0] <= 1034'b0;
		activeEdge[1] <= 1034'b0;
		activeEdge[2] <= 1034'b0;
		activeEdge[3] <= 1034'b0;
		activeEdge[4] <= 1034'b0;
		activeEdge[5] <= 1034'b0;
		activeEdge[6] <= 1034'b0;
		activeEdge[7] <= 1034'b0;
		activeEdge[8] <= 1034'b0;
		activeEdge[9] <= 1034'b0;

		activePose <= 66'b0;

		selectEdge <= 110'd0;
	end

	else

	case(state)

	FORWARD_INIT: begin


		ramAddress <= 10'd0;
		leverCnt <= 4'd0;
		activeEdge[0] <= 1034'b0;
		activeEdge[1] <= 1034'b0;
		activeEdge[2] <= 1034'b0;
		activeEdge[3] <= 1034'b0;
		activeEdge[4] <= 1034'b0;
		activeEdge[5] <= 1034'b0;
		activeEdge[6] <= 1034'b0;
		activeEdge[7] <= 1034'b0;
		activeEdge[8] <= 1034'b0;
		activeEdge[9] <= 1034'b0;

		activePose <= (66'b1 << startPose);
	end

	 BACKWARD_INIT: begin

		ramAddress <= 10'd0;
		leverCnt <= 4'd0;
		activeEdge[0] <= 1034'b0;
		activeEdge[1] <= 1034'b0;
		activeEdge[2] <= 1034'b0;
		activeEdge[3] <= 1034'b0;
		activeEdge[4] <= 1034'b0;
		activeEdge[5] <= 1034'b0;
		activeEdge[6] <= 1034'b0;
		activeEdge[7] <= 1034'b0;
		activeEdge[8] <= 1034'b0;
		activeEdge[9] <= 1034'b0;

		activePose <= (66'b1 << endPose);
	end

	FORWARD_WORK: begin

		if ( ramAddress < 11'd1034 ) begin

			leverCnt <= leverCnt;
			ramAddress <= ramAddress + 11'd1;

			if ( edgeMask_Reg[ramAddress] != 1'b1 ) begin

				if ( (^(activePose & routeLine)) == 1'b1 ) begin
					
					activePose <= activePose | routeLine;
					activeEdge[leverCnt] <= activeEdge[leverCnt] | (1034'b1 << ramAddress);
				end
				else begin
				end
			end
			else begin
			end
		end
		else begin
			leverCnt <= leverCnt + 1'd1;
			ramAddress <= 0;
		end
	end

	BACKWARD_WORK:  begin
		
		if ( ramAddress < 11'd1034 ) begin

			leverCnt <= leverCnt;
			ramAddress <= ramAddress + 11'd1;

			if ( edgeMask_Reg[ramAddress] != 1'b1 ) begin

				if ( (^(activePose & routeLine)) == 1'b1 ) begin
					
					activePose <= activePose | routeLine;
	
					leverCnt <= leverCnt + 1'd1;

					ramAddress <= 11'd0;
					selectEdge[leverCnt*11+:11] <= ramAddress;

				end

				else begin
				end
			end
			else begin
			end
		end
		else begin
		end
	end

	default: begin
	end

	endcase

end




always @(negedge CLK) begin
	if (!RST_n) begin
		maxLever <= 4'd10;
		state <= FORWARD_INIT;
		
	end

	case (state)
	FORWARD_INIT: begin
		maxLever <= 4'd10;

		edgeMask_Reg[1033:0] <= edgeMask[1033:0];

		if ( control == 3'b010  ) begin
			state <= FORWARD_WORK;
		end

	end

	FORWARD_WORK: begin
		if( (activePose >> endPose) & 66'b1 == 66'b1 ) begin
			state <= BACKWARD_INIT;
			edgeMask_Reg <= edgeMask_Reg | 
							~( activeEdge[0] | activeEdge[1] | activeEdge[2] | activeEdge[3]
							| activeEdge[4] | activeEdge[5] | activeEdge[6] | activeEdge[7]
							| activeEdge[8] | activeEdge[9] );
			maxLever <= leverCnt;
			
		end
		else begin
			state <= FORWARD_WORK;
		end

		if ( leverCnt == maxLever ) begin

			state <= FAIL;

		end
	end

	BACKWARD_INIT: begin
		if ( control == 3'b100 ) begin
			state <= BACKWARD_WORK;
		end
	end

	BACKWARD_WORK: begin
		if ( (activePose >> startPose) & 66'b1 == 66'b1 ) begin

			state <= FINISH;
		end
	end

	default: begin
	end

	endcase


end

endmodule