data/full_repos/permissive/132439949/sources_1/new/A_delay_echo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/132439949/sources_1/new/A_delay_echo.v:35: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                    : ... In instance A_delay_echo\n        data_out = 12\'b0;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/132439949/sources_1/new/A_delay_echo.v:39: Bit extraction of array[19999:0] requires 15 bit index, not 25 bits.\n                                                                                    : ... In instance A_delay_echo\n         memory[i] <= data_in1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/132439949/sources_1/new/A_delay_echo.v:39: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_in1\' generates 1 bits.\n                                                                                    : ... In instance A_delay_echo\n         memory[i] <= data_in1;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/132439949/sources_1/new/A_delay_echo.v:42: Bit extraction of array[19999:0] requires 15 bit index, not 25 bits.\n                                                                                    : ... In instance A_delay_echo\n         memory[ii] <= data_in2;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/132439949/sources_1/new/A_delay_echo.v:42: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_in2\' generates 1 bits.\n                                                                                    : ... In instance A_delay_echo\n         memory[ii] <= data_in2;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/132439949/sources_1/new/A_delay_echo.v:51: Bit extraction of array[19999:0] requires 15 bit index, not 14 bits.\n                                                                                    : ... In instance A_delay_echo\n        data_out <= memory[j];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/132439949/sources_1/new/A_delay_echo.v:51: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 12 bits.\n                                                                                    : ... In instance A_delay_echo\n        data_out <= memory[j];\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/132439949/sources_1/new/A_delay_echo.v:52: Operator EQ expects 32 or 15 bits on the LHS, but LHS\'s VARREF \'j\' generates 14 bits.\n                                                                                    : ... In instance A_delay_echo\n        j <= (j==19999) ? 0 : j+1;\n               ^~\n%Error: Exiting due to 8 warning(s)\n'
module A_delay_echo(
    input data_in1,
    input data_in2,
    input clk_write,
    output reg data_out
    );
    
    reg [11:0] memory [0:19999];
    reg [24:0] i = 0;
    reg [24:0] ii = 12;
    
    initial begin
        data_out = 12'b0;
    end
    
    always @ (posedge clk_write) begin
         memory[i] <= data_in1;
         i <= (i==19999) ? 0 : i+1;
         
         memory[ii] <= data_in2;
         ii <= (ii==19999) ? 0 : ii+1;
    end



    reg [13:0] j = 10;
 
    always @ (posedge clk_write) begin
        data_out <= memory[j];
        j <= (j==19999) ? 0 : j+1;
    end
    
endmodule
module A_delay_echo(
    input data_in1,
    input data_in2,
    input clk_write,
    output reg data_out
    );

    
    reg [11:0] memory [0:19999];
    reg [24:0] i = 0;
    reg [24:0] ii = 12;
    
    initial begin
        data_out = 12'b0;
    end
    
    always @ (posedge clk_write) begin
         memory[i] <= data_in1;
         i <= (i==19999) ? 0 : i+1;
         
         memory[ii] <= data_in2;
         ii <= (ii==19999) ? 0 : ii+1;
    end



    reg [13:0] j = 10;
 
    always @ (posedge clk_write) begin
        data_out <= memory[j];
        j <= (j==19999) ? 0 : j+1;
    end
    
endmodule