data/full_repos/permissive/147645128/source/mm_slave/pwr_ctrl.v
1: b'%Warning-WIDTH: data/full_repos/permissive/147645128/source/mm_slave/pwr_ctrl.v:295: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h7f\' generates 7 bits.\n                                                                                   : ... In instance pwr_ctrl\n  if(pwr_good_stage == 7\'b111_1111)\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pwr_ctrl(




clk_sys_i,
rst_n_i,


mm_s_addr_i,
mm_s_wdata_i,
mm_s_rdata_o,
mm_s_we_i,


psu_prsnt_i,
pwr_good_i,
pwr_en_o,
pwr_err_o,
pwr_allgood_o
);


parameter MM_ADDR_WIDTH = 8;
parameter MM_DATA_WIDTH = 16;

parameter REG_ADDR_PWR_CTRL = 'h10;
parameter REG_ADDR_PSU_STA  = 'h12;
parameter REG_ADDR_PWR_STA  = 'h14;
parameter REG_ADDR_PWR_ERR  = 'h16;


parameter STATE_OFF	= 4'b0001;
parameter STATE_UP	= 4'b0010;
parameter STATE_ON	= 4'b0100;
parameter STATE_ERR	= 4'b1000;


parameter FREQ_SYSCLK = 25_000_000;
parameter TIME_SYSCLK = 1_000_000_000 / FREQ_SYSCLK;


parameter TIME_PWR_WDT = 1_000_000_000;



input clk_sys_i, rst_n_i;



input[MM_ADDR_WIDTH-1:0] mm_s_addr_i;
input[MM_DATA_WIDTH-1:0] mm_s_wdata_i;
output[MM_DATA_WIDTH-1:0] mm_s_rdata_o;

input mm_s_we_i;


input[1:0] psu_prsnt_i;
input[14:0] pwr_good_i;
output[11:0] pwr_en_o;
output pwr_err_o;
output pwr_allgood_o;




reg[11:0] pwr_en_o;
reg[7:0] pwr_good_stage;





































	


reg[1:0] pwr_ctrl_reg;
reg[14:0] pwr_err_reg;
reg[MM_DATA_WIDTH-1:0] mm_s_rdata_o; 

reg[31:0] pwr_delay_cnt;
reg[31:0] pwr_wdt_cnt;
reg pwr_delay_en, pwr_wdt_en, pwr_delay_ot, pwr_wdt_ot;

reg pwr_auto_start;
reg pwr_err_o;
reg pwr_allgood_o;

reg[3:0] pwr_ctrl_fsm;




always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_ctrl_reg <= 0;
	end
	else begin
		if(mm_s_we_i) begin
			case(mm_s_addr_i)
				REG_ADDR_PWR_CTRL:
				begin
					pwr_ctrl_reg <= mm_s_wdata_i[1:0];
				end
				
				default:
				begin
					pwr_ctrl_reg <= 0;
				end
			endcase
		end
		else begin
			pwr_ctrl_reg <= 0;
		end
	end
end


always @(mm_s_addr_i, pwr_ctrl_reg, pwr_good_i, psu_prsnt_i, pwr_allgood_o, pwr_err_reg, rst_n_i)
begin
	if(!rst_n_i) begin
		mm_s_rdata_o <= 0;
	end
	else begin
		case(mm_s_addr_i)
			REG_ADDR_PWR_CTRL:
				mm_s_rdata_o <= {14'h0, pwr_ctrl_reg[1:0]};
				
			REG_ADDR_PSU_STA:
				mm_s_rdata_o <= {12'h0, pwr_good_i[14:13], ~psu_prsnt_i[1:0]};
			
			REG_ADDR_PWR_STA:
				mm_s_rdata_o <= {pwr_allgood_o, 2'h0, pwr_good_i[12:0]};
				
			REG_ADDR_PWR_ERR:
				mm_s_rdata_o <= {1'h0, pwr_err_reg};
		
			default:
				mm_s_rdata_o <= 0;
		endcase
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_ctrl_fsm <= STATE_OFF;
	end
	else begin
		case(pwr_ctrl_fsm)
			STATE_OFF:
			begin


				if(pwr_ctrl_reg == 2'b01 | pwr_auto_start == 1'b1) begin
					pwr_ctrl_fsm <= STATE_UP;
				end
			end
			
			STATE_UP:
			begin
				if(pwr_allgood_o == 1'b1) begin
					pwr_ctrl_fsm <= STATE_ON;
				end
				else if(pwr_wdt_ot == 1'b1) begin
					pwr_ctrl_fsm <= STATE_ERR;
				end
			end
			
			STATE_ON:
			begin				
				if(pwr_allgood_o == 1'b0) begin
					pwr_ctrl_fsm <= STATE_ERR;
				end


				else if(pwr_ctrl_reg == 2'b10) begin
					pwr_ctrl_fsm <= STATE_OFF;
				end
			end
			
			STATE_ERR:
			begin
				pwr_ctrl_fsm <= STATE_OFF;
			end

			default:
			begin
				pwr_ctrl_fsm <= STATE_OFF;
			end
		endcase
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_good_stage <= 0;
	end
	else begin



		pwr_good_stage[0] <= 1'b1;
		



		pwr_good_stage[1] <= (pwr_good_i[14] | pwr_good_i[13]) & pwr_good_i[1] & pwr_good_i[0];
				

		pwr_good_stage[2] <= pwr_good_i[4] & pwr_good_i[3] & pwr_good_i[2];
		

		pwr_good_stage[3] <= pwr_good_i[6] & pwr_good_i[5];
		

		pwr_good_stage[4] <= pwr_good_i[9] & pwr_good_i[8] & pwr_good_i[7];
		

		pwr_good_stage[5] <= pwr_good_i[11] & pwr_good_i[10];


		pwr_good_stage[6] <= pwr_good_i[12];
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_allgood_o <= 1'b0;
	end
	else begin		
		if(pwr_good_stage == 7'b111_1111)
			pwr_allgood_o <= 1'b1;
		else
			pwr_allgood_o <= 1'b0;
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_en_o <= 12'b1100_0000_0000;
		
	end
	else begin
		if(pwr_ctrl_fsm == STATE_UP) begin

			pwr_en_o[11] <= ~pwr_good_stage[0];
			pwr_en_o[10] <= ~pwr_good_stage[0];
			

			pwr_en_o[1] <= pwr_good_stage[1];
			pwr_en_o[0] <= pwr_good_stage[1];
			

			pwr_en_o[3] <= pwr_good_stage[2];
			pwr_en_o[2] <= pwr_good_stage[2];
			

			pwr_en_o[6] <= pwr_good_stage[3];
			pwr_en_o[5] <= pwr_good_stage[3];
			pwr_en_o[4] <= pwr_good_stage[3];
			

			pwr_en_o[8] <= pwr_good_stage[4];
			pwr_en_o[7] <= pwr_good_stage[4];
			

			pwr_en_o[9] <= pwr_good_stage[5];
		end
		
		else if(pwr_ctrl_fsm == STATE_OFF) begin
			pwr_en_o <= 12'b1100_0000_0000;
		end
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_err_reg <= 0;
		pwr_err_o <= 0;
	end
	else begin
		if(pwr_ctrl_fsm == STATE_ERR) begin		
			pwr_err_reg <= pwr_good_i;
			pwr_err_o <= 1'b1;
		end
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_auto_start <= 1'b1;
	end
	else begin
		if(pwr_ctrl_fsm == STATE_UP)
			pwr_auto_start <= 1'b0;
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_wdt_cnt <= 0;
		pwr_wdt_ot <= 0;
	end
	else begin
		if(pwr_ctrl_fsm == STATE_OFF) begin
			pwr_wdt_cnt <= 0;
			pwr_wdt_ot <= 0;
		end		
		else if(pwr_ctrl_fsm == STATE_UP) begin
			pwr_wdt_cnt <= pwr_wdt_cnt + 1'b1;
			
			if(pwr_wdt_cnt >= TIME_PWR_WDT / (1_000_000_000 / FREQ_SYSCLK))
				pwr_wdt_ot <= 1;
		end
			
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin

	end
	else begin
		
	end
end


endmodule
module pwr_ctrl(




clk_sys_i,
rst_n_i,


mm_s_addr_i,
mm_s_wdata_i,
mm_s_rdata_o,
mm_s_we_i,


psu_prsnt_i,
pwr_good_i,
pwr_en_o,
pwr_err_o,
pwr_allgood_o
);



parameter MM_ADDR_WIDTH = 8;
parameter MM_DATA_WIDTH = 16;

parameter REG_ADDR_PWR_CTRL = 'h10;
parameter REG_ADDR_PSU_STA  = 'h12;
parameter REG_ADDR_PWR_STA  = 'h14;
parameter REG_ADDR_PWR_ERR  = 'h16;


parameter STATE_OFF	= 4'b0001;
parameter STATE_UP	= 4'b0010;
parameter STATE_ON	= 4'b0100;
parameter STATE_ERR	= 4'b1000;


parameter FREQ_SYSCLK = 25_000_000;
parameter TIME_SYSCLK = 1_000_000_000 / FREQ_SYSCLK;


parameter TIME_PWR_WDT = 1_000_000_000;



input clk_sys_i, rst_n_i;



input[MM_ADDR_WIDTH-1:0] mm_s_addr_i;
input[MM_DATA_WIDTH-1:0] mm_s_wdata_i;
output[MM_DATA_WIDTH-1:0] mm_s_rdata_o;

input mm_s_we_i;


input[1:0] psu_prsnt_i;
input[14:0] pwr_good_i;
output[11:0] pwr_en_o;
output pwr_err_o;
output pwr_allgood_o;




reg[11:0] pwr_en_o;
reg[7:0] pwr_good_stage;





































	


reg[1:0] pwr_ctrl_reg;
reg[14:0] pwr_err_reg;
reg[MM_DATA_WIDTH-1:0] mm_s_rdata_o; 

reg[31:0] pwr_delay_cnt;
reg[31:0] pwr_wdt_cnt;
reg pwr_delay_en, pwr_wdt_en, pwr_delay_ot, pwr_wdt_ot;

reg pwr_auto_start;
reg pwr_err_o;
reg pwr_allgood_o;

reg[3:0] pwr_ctrl_fsm;




always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_ctrl_reg <= 0;
	end
	else begin
		if(mm_s_we_i) begin
			case(mm_s_addr_i)
				REG_ADDR_PWR_CTRL:
				begin
					pwr_ctrl_reg <= mm_s_wdata_i[1:0];
				end
				
				default:
				begin
					pwr_ctrl_reg <= 0;
				end
			endcase
		end
		else begin
			pwr_ctrl_reg <= 0;
		end
	end
end


always @(mm_s_addr_i, pwr_ctrl_reg, pwr_good_i, psu_prsnt_i, pwr_allgood_o, pwr_err_reg, rst_n_i)
begin
	if(!rst_n_i) begin
		mm_s_rdata_o <= 0;
	end
	else begin
		case(mm_s_addr_i)
			REG_ADDR_PWR_CTRL:
				mm_s_rdata_o <= {14'h0, pwr_ctrl_reg[1:0]};
				
			REG_ADDR_PSU_STA:
				mm_s_rdata_o <= {12'h0, pwr_good_i[14:13], ~psu_prsnt_i[1:0]};
			
			REG_ADDR_PWR_STA:
				mm_s_rdata_o <= {pwr_allgood_o, 2'h0, pwr_good_i[12:0]};
				
			REG_ADDR_PWR_ERR:
				mm_s_rdata_o <= {1'h0, pwr_err_reg};
		
			default:
				mm_s_rdata_o <= 0;
		endcase
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_ctrl_fsm <= STATE_OFF;
	end
	else begin
		case(pwr_ctrl_fsm)
			STATE_OFF:
			begin


				if(pwr_ctrl_reg == 2'b01 | pwr_auto_start == 1'b1) begin
					pwr_ctrl_fsm <= STATE_UP;
				end
			end
			
			STATE_UP:
			begin
				if(pwr_allgood_o == 1'b1) begin
					pwr_ctrl_fsm <= STATE_ON;
				end
				else if(pwr_wdt_ot == 1'b1) begin
					pwr_ctrl_fsm <= STATE_ERR;
				end
			end
			
			STATE_ON:
			begin				
				if(pwr_allgood_o == 1'b0) begin
					pwr_ctrl_fsm <= STATE_ERR;
				end


				else if(pwr_ctrl_reg == 2'b10) begin
					pwr_ctrl_fsm <= STATE_OFF;
				end
			end
			
			STATE_ERR:
			begin
				pwr_ctrl_fsm <= STATE_OFF;
			end

			default:
			begin
				pwr_ctrl_fsm <= STATE_OFF;
			end
		endcase
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_good_stage <= 0;
	end
	else begin



		pwr_good_stage[0] <= 1'b1;
		



		pwr_good_stage[1] <= (pwr_good_i[14] | pwr_good_i[13]) & pwr_good_i[1] & pwr_good_i[0];
				

		pwr_good_stage[2] <= pwr_good_i[4] & pwr_good_i[3] & pwr_good_i[2];
		

		pwr_good_stage[3] <= pwr_good_i[6] & pwr_good_i[5];
		

		pwr_good_stage[4] <= pwr_good_i[9] & pwr_good_i[8] & pwr_good_i[7];
		

		pwr_good_stage[5] <= pwr_good_i[11] & pwr_good_i[10];


		pwr_good_stage[6] <= pwr_good_i[12];
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_allgood_o <= 1'b0;
	end
	else begin		
		if(pwr_good_stage == 7'b111_1111)
			pwr_allgood_o <= 1'b1;
		else
			pwr_allgood_o <= 1'b0;
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_en_o <= 12'b1100_0000_0000;
		
	end
	else begin
		if(pwr_ctrl_fsm == STATE_UP) begin

			pwr_en_o[11] <= ~pwr_good_stage[0];
			pwr_en_o[10] <= ~pwr_good_stage[0];
			

			pwr_en_o[1] <= pwr_good_stage[1];
			pwr_en_o[0] <= pwr_good_stage[1];
			

			pwr_en_o[3] <= pwr_good_stage[2];
			pwr_en_o[2] <= pwr_good_stage[2];
			

			pwr_en_o[6] <= pwr_good_stage[3];
			pwr_en_o[5] <= pwr_good_stage[3];
			pwr_en_o[4] <= pwr_good_stage[3];
			

			pwr_en_o[8] <= pwr_good_stage[4];
			pwr_en_o[7] <= pwr_good_stage[4];
			

			pwr_en_o[9] <= pwr_good_stage[5];
		end
		
		else if(pwr_ctrl_fsm == STATE_OFF) begin
			pwr_en_o <= 12'b1100_0000_0000;
		end
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_err_reg <= 0;
		pwr_err_o <= 0;
	end
	else begin
		if(pwr_ctrl_fsm == STATE_ERR) begin		
			pwr_err_reg <= pwr_good_i;
			pwr_err_o <= 1'b1;
		end
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_auto_start <= 1'b1;
	end
	else begin
		if(pwr_ctrl_fsm == STATE_UP)
			pwr_auto_start <= 1'b0;
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		pwr_wdt_cnt <= 0;
		pwr_wdt_ot <= 0;
	end
	else begin
		if(pwr_ctrl_fsm == STATE_OFF) begin
			pwr_wdt_cnt <= 0;
			pwr_wdt_ot <= 0;
		end		
		else if(pwr_ctrl_fsm == STATE_UP) begin
			pwr_wdt_cnt <= pwr_wdt_cnt + 1'b1;
			
			if(pwr_wdt_cnt >= TIME_PWR_WDT / (1_000_000_000 / FREQ_SYSCLK))
				pwr_wdt_ot <= 1;
		end
			
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin

	end
	else begin
		
	end
end


endmodule