data/full_repos/permissive/20688874/viterbi/syncommschannel.v
1: b'%Error: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:43: Cannot find include file: syntheziedviterbi.v\n`include "syntheziedviterbi.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/syntheziedviterbi.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/syntheziedviterbi.v.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/syntheziedviterbi.v.sv\n             syntheziedviterbi.v\n             syntheziedviterbi.v.v\n             syntheziedviterbi.v.sv\n             obj_dir/syntheziedviterbi.v\n             obj_dir/syntheziedviterbi.v.v\n             obj_dir/syntheziedviterbi.v.sv\n%Error: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:45: Cannot find include file: cencoder.v\n`include "cencoder.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:46: Cannot find include file: noisegen.v\n`include "noisegen.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:47: Cannot find include file: xor2.v\n`include "xor2.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:48: Cannot find include file: pipe.v\n`include "pipe.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:49: Cannot find include file: pipe2.v\n`include "pipe2.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:50: Cannot find include file: /auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v\n`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:330: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:331: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 1;\n     ^\n%Error: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:424: Unsupported or unknown PLI call: $sdf_annotate\n  $sdf_annotate("../sdf/viterbi_decoder.sdf",v_d,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");\n  ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:434: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:454: Unsupported: Ignoring delay on this delayed statement.\n   #10\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/syncommschannel.v:484: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: Exiting due to 8 error(s), 5 warning(s)\n'
module tb_communication_channel();

	 

	

	
	
	
		


	


	wire d;
	wire [1:0] c;
	wire [1:0] cx;
wire b;


	wire [1:0] r_c;
	



	
	
	






	reg  r[0:255];

reg rr;

	reg [7:0] e;
	reg clock;



	reg r_b;



	reg [7:0] r_e;



	reg [1:0] rr_c;

	reg [7:0] r_e1;

wire [1:0] r_e2;

wire [1:0] r_cx;

	reg r_b1;

	reg [7:0] error_level;



	reg [1:0] rr_c1;

	reg [1:0] r_cx1;

	reg r_b2;

	reg rset;
	
	
	
	
	
	
	
	
	
	


	integer count;
	
	
	
	
	
	
	

	

	parameter size_of_input = 9'd256;
	
	
	
	
	


	

	viterbi_decoder v_d (


		d,r_cx1,clock,rset);
	

	

	conv_encoder enc (


		r_c,r_b,clock,rset);
	

	

	noise_generator ng (


		r_e1,r_e2,error_level);
	

	

	xor2_2bit xor22 (


		rr_c,r_e2,r_cx);
	
	

	

	pipeline_buffer_2bit pipe_c (


		rr_c1,c,clock,rset);
	

	

	pipeline_buffer_2bit pipe_cx (


		r_cx1,cx,clock,rset);
	

	

	pipeline_buffer pipe_b (


		r_b2,b,clock,rset);
	
	
	
	
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;

    end		
	
	
	
	
	



	always@(posedge clock)
	begin
		if(rset)
		begin
			r_b<=0;
			r_e<=0;
		end
		else
		begin
			r_e<=e;
			r_b<=rr;
		end
	end
	


	always@(posedge clock)
	begin
		if(rset)
		begin
			rr_c<=0;
			r_e1<=0;
			r_b1<=0;
		end
		else
		begin
			rr_c<=r_c;
			r_e1<=r_e;
			r_b1<=r_b;
		end
	end
	


	always@(posedge clock)
	begin
		if(rset)
		begin
			rr_c1<=0;
			r_cx1<=0;
			r_b2<=0;
		end
		else
		begin
			rr_c1<=rr_c;
			r_cx1<=r_cx;
			r_b2<=r_b1;
		end
	end
	

	
	
	
	
	
	
	
	
	
	
	

	

	initial
	begin
		$sdf_annotate("../sdf/viterbi_decoder.sdf",v_d,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
	
		
		

		$display(" << Starting the simulation >>");

		error_level=8'd5;
		rset=1;

		#20
		rset=0;
		
		
		

		$readmemb("testfile.bit",r);

		

		
		for(count=0;count<size_of_input;count=count+1)
		begin
			#10
			$display("Next");
			e=$random;
			rr=r[count];
			
			
			if(rr_c != r_cx) 
			begin
				$display($time,"rr_c NOT EQUAL to r_cx");
			end
			
if(count==150)
begin
	rset=1;
end
else if(count==151)
begin
	rset=0;
end
			
		end
		
		
		
		

		
		
		
		
		#20;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_communication_channel();


	 

	

	
	
	
		


	


	wire d;
	wire [1:0] c;
	wire [1:0] cx;
wire b;


	wire [1:0] r_c;
	



	
	
	






	reg  r[0:255];

reg rr;

	reg [7:0] e;
	reg clock;



	reg r_b;



	reg [7:0] r_e;



	reg [1:0] rr_c;

	reg [7:0] r_e1;

wire [1:0] r_e2;

wire [1:0] r_cx;

	reg r_b1;

	reg [7:0] error_level;



	reg [1:0] rr_c1;

	reg [1:0] r_cx1;

	reg r_b2;

	reg rset;
	
	
	
	
	
	
	
	
	
	


	integer count;
	
	
	
	
	
	
	

	

	parameter size_of_input = 9'd256;
	
	
	
	
	


	

	viterbi_decoder v_d (


		d,r_cx1,clock,rset);
	

	

	conv_encoder enc (


		r_c,r_b,clock,rset);
	

	

	noise_generator ng (


		r_e1,r_e2,error_level);
	

	

	xor2_2bit xor22 (


		rr_c,r_e2,r_cx);
	
	

	

	pipeline_buffer_2bit pipe_c (


		rr_c1,c,clock,rset);
	

	

	pipeline_buffer_2bit pipe_cx (


		r_cx1,cx,clock,rset);
	

	

	pipeline_buffer pipe_b (


		r_b2,b,clock,rset);
	
	
	
	
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;

    end		
	
	
	
	
	



	always@(posedge clock)
	begin
		if(rset)
		begin
			r_b<=0;
			r_e<=0;
		end
		else
		begin
			r_e<=e;
			r_b<=rr;
		end
	end
	


	always@(posedge clock)
	begin
		if(rset)
		begin
			rr_c<=0;
			r_e1<=0;
			r_b1<=0;
		end
		else
		begin
			rr_c<=r_c;
			r_e1<=r_e;
			r_b1<=r_b;
		end
	end
	


	always@(posedge clock)
	begin
		if(rset)
		begin
			rr_c1<=0;
			r_cx1<=0;
			r_b2<=0;
		end
		else
		begin
			rr_c1<=rr_c;
			r_cx1<=r_cx;
			r_b2<=r_b1;
		end
	end
	

	
	
	
	
	
	
	
	
	
	
	

	

	initial
	begin
		$sdf_annotate("../sdf/viterbi_decoder.sdf",v_d,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
	
		
		

		$display(" << Starting the simulation >>");

		error_level=8'd5;
		rset=1;

		#20
		rset=0;
		
		
		

		$readmemb("testfile.bit",r);

		

		
		for(count=0;count<size_of_input;count=count+1)
		begin
			#10
			$display("Next");
			e=$random;
			rr=r[count];
			
			
			if(rr_c != r_cx) 
			begin
				$display($time,"rr_c NOT EQUAL to r_cx");
			end
			
if(count==150)
begin
	rset=1;
end
else if(count==151)
begin
	rset=0;
end
			
		end
		
		
		
		

		
		
		
		
		#20;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule