data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;        \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;        \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #20; clk = ~clk; #20;       \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #20;        \n  ^\n%Error: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:40: Unsupported or unknown PLI call: $writememb\n  $writememb("registers.mem", RTypeMips32.Reg.registers);  \n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips32_testbench.v:45: Unsupported or unknown PLI call: $monitor\n  $monitor("              opcode/__rs_/__rt_/__rd_/shamt/_funct\\ninstruction : %6b %5b %5b %5b %5b %6h\\nresult      : %32b\\n", instruction_set[31:26], instruction_set[25:21], instruction_set[20:16], instruction_set[15:11], instruction_set[10:6], instruction_set[5:0], result);\n  ^~~~~~~~\n%Error: Exiting due to 2 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips32_testbench ();
	reg [31:0] instruction_set;
	wire [31:0] result;
	reg clk;
	
	mips32 RTypeMips32(instruction_set, result, clk);
	
	initial
	begin
		clk = 1;
	end
	
	initial
	begin
		$readmemb("registers.mem", RTypeMips32.Reg.registers);



		instruction_set = 32'b000000_10000_10001_10010_00000_100000;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_10011_00000_100001;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_10100_00000_100010;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_10101_00000_100011;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_10110_00000_100100;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_10111_00000_100101;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_11000_00000_100111;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_11001_00001_000000;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_11010_00001_000010;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_11011_00000_101011;
		#20;
		
		$writememb("registers.mem", RTypeMips32.Reg.registers);
	end
	
	initial
	begin
		$monitor("              opcode/__rs_/__rt_/__rd_/shamt/_funct\ninstruction : %6b %5b %5b %5b %5b %6h\nresult      : %32b\n", instruction_set[31:26], instruction_set[25:21], instruction_set[20:16], instruction_set[15:11], instruction_set[10:6], instruction_set[5:0], result);
	end

endmodule
module mips32_testbench ();

	reg [31:0] instruction_set;
	wire [31:0] result;
	reg clk;
	
	mips32 RTypeMips32(instruction_set, result, clk);
	
	initial
	begin
		clk = 1;
	end
	
	initial
	begin
		$readmemb("registers.mem", RTypeMips32.Reg.registers);



		instruction_set = 32'b000000_10000_10001_10010_00000_100000;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_10011_00000_100001;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_10100_00000_100010;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_10101_00000_100011;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_10110_00000_100100;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_10111_00000_100101;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_11000_00000_100111;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_11001_00001_000000;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_11010_00001_000010;
		#20; clk = ~clk; #20;
		clk = ~clk; instruction_set = 32'b000000_10000_10001_11011_00000_101011;
		#20;
		
		$writememb("registers.mem", RTypeMips32.Reg.registers);
	end
	
	initial
	begin
		$monitor("              opcode/__rs_/__rt_/__rd_/shamt/_funct\ninstruction : %6b %5b %5b %5b %5b %6h\nresult      : %32b\n", instruction_set[31:26], instruction_set[25:21], instruction_set[20:16], instruction_set[15:11], instruction_set[10:6], instruction_set[5:0], result);
	end

endmodule