data/full_repos/permissive/166661632/p8/srccode/IFU.v
1: b"%Error: data/full_repos/permissive/166661632/p8/srccode/IFU.v:9: Cannot find file containing module: 'DM4K'\nDM4K dm4k (\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/166661632/p8/srccode,data/full_repos/permissive/166661632/DM4K\n             data/full_repos/permissive/166661632/p8/srccode,data/full_repos/permissive/166661632/DM4K.v\n             data/full_repos/permissive/166661632/p8/srccode,data/full_repos/permissive/166661632/DM4K.sv\n             DM4K\n             DM4K.v\n             DM4K.sv\n             obj_dir/DM4K\n             obj_dir/DM4K.v\n             obj_dir/DM4K.sv\n%Error: Exiting due to 1 error(s)\n"
module IFU (clk,clk2,clr,stall,branch,intreq,npcout,instr,pc8);
input clk,clk2,clr,stall,branch,intreq;
input [31:0] npcout;
output [31:0] instr,pc8;

reg [31:0]pc;
wire [31:0] add=pc-32'h00003000;
DM4K dm4k (
  .clka(clk2),
   .wea(4'b0000),
  .addra(add[14:2]),
   .dina(32'h00000000),
  .douta(instr)
);

always @(posedge clk)
begin
	if (clr)
		pc<=32'h00003000;
	else if (intreq)
		pc<=npcout;
	else if(stall)
		pc<=pc;
	else if(branch)
		pc<=npcout;

	else
		pc<=pc+4;
end


assign pc8=pc+8;
endmodule
module IFU (clk,clk2,clr,stall,branch,intreq,npcout,instr,pc8);

input clk,clk2,clr,stall,branch,intreq;
input [31:0] npcout;
output [31:0] instr,pc8;

reg [31:0]pc;
wire [31:0] add=pc-32'h00003000;
DM4K dm4k (
  .clka(clk2),
   .wea(4'b0000),
  .addra(add[14:2]),
   .dina(32'h00000000),
  .douta(instr)
);

always @(posedge clk)
begin
	if (clr)
		pc<=32'h00003000;
	else if (intreq)
		pc<=npcout;
	else if(stall)
		pc<=pc;
	else if(branch)
		pc<=npcout;

	else
		pc<=pc+4;
end


assign pc8=pc+8;
endmodule