data/full_repos/permissive/184916587/Test_Regfile.v
 line:28: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Regfile.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #0 State=1;reg_address=00000;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Regfile.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #5 State=0;reg_address=00001;reg_data_w=32\'b11110000000000000000000000001111;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Regfile.v:25: Unsupported: Ignoring delay on this delayed statement.\n   #5 State=1;reg_address=00001;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Regfile.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #5 State=0;reg_address=00000;reg_data_w=32\'b11111111111111111111111111111111;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Regfile.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #5 State=1;reg_address=00000;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Regfile.v:28: Unsupported: Ignoring delay on this delayed statement.\n   #5 $finish;\n   ^\n%Error: data/full_repos/permissive/184916587/Test_Regfile.v:33: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("Regfile.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/184916587/Test_Regfile.v:34: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0,Regfile_test);\n   ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Regfile_test;
	reg State;
	reg[4:0] reg_address;
	reg[31:0] reg_data_w;
	wire[31:0] reg_data;

	Regfile regfile_test(
		.State(State),
		.address(reg_address),
		.data_w(reg_data_w),
		.data(reg_data)
	);

	initial
		begin
			#0 State=1;reg_address=00000;
			#5 State=0;reg_address=00001;reg_data_w=32'b11110000000000000000000000001111;
			#5 State=1;reg_address=00001;
			#5 State=0;reg_address=00000;reg_data_w=32'b11111111111111111111111111111111;
			#5 State=1;reg_address=00000;
			#5 $finish;
		end

	initial
		begin
			$dumpfile("Regfile.vcd");
			$dumpvars(0,Regfile_test);
		end
endmodule
module Regfile_test;

	reg State;
	reg[4:0] reg_address;
	reg[31:0] reg_data_w;
	wire[31:0] reg_data;

	Regfile regfile_test(
		.State(State),
		.address(reg_address),
		.data_w(reg_data_w),
		.data(reg_data)
	);

	initial
		begin
			#0 State=1;reg_address=00000;
			#5 State=0;reg_address=00001;reg_data_w=32'b11110000000000000000000000001111;
			#5 State=1;reg_address=00001;
			#5 State=0;reg_address=00000;reg_data_w=32'b11111111111111111111111111111111;
			#5 State=1;reg_address=00000;
			#5 $finish;
		end

	initial
		begin
			$dumpfile("Regfile.vcd");
			$dumpvars(0,Regfile_test);
		end
endmodule