data/full_repos/permissive/174783592/WallacePL/Wallace16BitPLTB.v
 line:41: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Wallace16BitPLTB.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #50 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Wallace16BitPLTB.v:44: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk <= ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Wallace16BitPLTB.v:45: Unsupported: Ignoring delay on this delayed statement.\n always #5 a <= a +1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Wallace16BitPLTB.v:46: Unsupported: Ignoring delay on this delayed statement.\n always #5 b <= b +1;\n        ^\n%Error: data/full_repos/permissive/174783592/WallacePL/Wallace16BitPLTB.v:48: Unsupported or unknown PLI call: $monitor\n initial $monitor($time,"clk=%b a=%b\\nb=%b\\nLL=%b\\nLH=%b\\nHL=%b\\nHH=%b\\noutu=%b\\np=%b",clk,a,b,w.prodLowLow_reg,w.prodLowHigh_reg,w.prodHighLow_reg,w.prodHighHigh_reg,w.outu,p);\n         ^~~~~~~~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Wallace16BitTB();


	reg [15:0] a;
	reg [15:0] b;
	reg clk;
	wire [32:0] p;


	Wallace16BitPL  w(a,b,p,clk);
	initial 
	begin
		a <= {4{4'b1111}};
		b <= {4{4'b1111}};
		clk <= 1'b0;
		#50 $finish;
	end

	always #5 clk <= ~clk;
	always #5 a <= a +1;
	always #5 b <= b +1;

	initial $monitor($time,"clk=%b a=%b\nb=%b\nLL=%b\nLH=%b\nHL=%b\nHH=%b\noutu=%b\np=%b",clk,a,b,w.prodLowLow_reg,w.prodLowHigh_reg,w.prodHighLow_reg,w.prodHighHigh_reg,w.outu,p);
	endmodule
module Wallace16BitTB();



	reg [15:0] a;
	reg [15:0] b;
	reg clk;
	wire [32:0] p;


	Wallace16BitPL  w(a,b,p,clk);
	initial 
	begin
		a <= {4{4'b1111}};
		b <= {4{4'b1111}};
		clk <= 1'b0;
		#50 $finish;
	end

	always #5 clk <= ~clk;
	always #5 a <= a +1;
	always #5 b <= b +1;

	initial $monitor($time,"clk=%b a=%b\nb=%b\nLL=%b\nLH=%b\nHL=%b\nHH=%b\noutu=%b\np=%b",clk,a,b,w.prodLowLow_reg,w.prodLowHigh_reg,w.prodHighLow_reg,w.prodHighHigh_reg,w.outu,p);
	endmodule