data/full_repos/permissive/109608368/memory/Enable_select.v
data/verilator_xmls/8b39c1d4-5f0b-4858-9204-d13c90b479db.xml
module Enable_select(enable, select, out);
    input [3:0] select;
    input enable;
    output [15:0] out;
    reg [15:0] reg_out;

    initial  begin
        reg_out[15:0] = 16'd0;
    end

    always @ (*)
    begin
        case (select[3:0])
            4'd0: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0001 : 16'd0;
            4'd1: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0010 : 16'd0;
            4'd2: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0100 : 16'd0;
            4'd3: reg_out[15:0] <= enable ? 16'b0000_0000_0000_1000 : 16'd0;
            4'd4: reg_out[15:0] <= enable ? 16'b0000_0000_0001_0000 : 16'd0;
            4'd5: reg_out[15:0] <= enable ? 16'b0000_0000_0010_0000 : 16'd0;
            4'd6: reg_out[15:0] <= enable ? 16'b0000_0000_0100_0000 : 16'd0;
            4'd7: reg_out[15:0] <= enable ? 16'b0000_0000_1000_0000 : 16'd0;
            4'd8: reg_out[15:0] <= enable ? 16'b0000_0001_0000_0000 : 16'd0;
            4'd9: reg_out[15:0] <= enable ? 16'b0000_0010_0000_0000 : 16'd0;
            4'd10: reg_out[15:0] <= enable ? 16'b0000_0100_0000_0000 : 16'd0;
            4'd11: reg_out[15:0] <= enable ? 16'b0000_1000_0000_0000 : 16'd0;
            4'd12: reg_out[15:0] <= enable ? 16'b0001_0000_0000_0000 : 16'd0;
            4'd13: reg_out[15:0] <= enable ? 16'b0010_0000_0000_0000 : 16'd0;
            4'd14: reg_out[15:0] <= enable ? 16'b0100_0000_0000_0000 : 16'd0;
            4'd15: reg_out[15:0] <= enable ? 16'b1000_0000_0000_0000 : 16'd0;

       endcase
    end
	 
    assign out[15:0] = reg_out[15:0];
    
endmodule
module Enable_select(enable, select, out);

    input [3:0] select;
    input enable;
    output [15:0] out;
    reg [15:0] reg_out;

    initial  begin
        reg_out[15:0] = 16'd0;
    end

    always @ (*)
    begin
        case (select[3:0])
            4'd0: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0001 : 16'd0;
            4'd1: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0010 : 16'd0;
            4'd2: reg_out[15:0] <= enable ? 16'b0000_0000_0000_0100 : 16'd0;
            4'd3: reg_out[15:0] <= enable ? 16'b0000_0000_0000_1000 : 16'd0;
            4'd4: reg_out[15:0] <= enable ? 16'b0000_0000_0001_0000 : 16'd0;
            4'd5: reg_out[15:0] <= enable ? 16'b0000_0000_0010_0000 : 16'd0;
            4'd6: reg_out[15:0] <= enable ? 16'b0000_0000_0100_0000 : 16'd0;
            4'd7: reg_out[15:0] <= enable ? 16'b0000_0000_1000_0000 : 16'd0;
            4'd8: reg_out[15:0] <= enable ? 16'b0000_0001_0000_0000 : 16'd0;
            4'd9: reg_out[15:0] <= enable ? 16'b0000_0010_0000_0000 : 16'd0;
            4'd10: reg_out[15:0] <= enable ? 16'b0000_0100_0000_0000 : 16'd0;
            4'd11: reg_out[15:0] <= enable ? 16'b0000_1000_0000_0000 : 16'd0;
            4'd12: reg_out[15:0] <= enable ? 16'b0001_0000_0000_0000 : 16'd0;
            4'd13: reg_out[15:0] <= enable ? 16'b0010_0000_0000_0000 : 16'd0;
            4'd14: reg_out[15:0] <= enable ? 16'b0100_0000_0000_0000 : 16'd0;
            4'd15: reg_out[15:0] <= enable ? 16'b1000_0000_0000_0000 : 16'd0;

       endcase
    end
	 
    assign out[15:0] = reg_out[15:0];
    
endmodule