data/full_repos/permissive/113471686/virtualtree/freq/freq.v
1: b"%Error: data/full_repos/permissive/113471686/virtualtree/freq/freq.v:46: Cannot find file containing module: 'vMERGE_SORTER_TREE'\n  vMERGE_SORTER_TREE #(10, 3, 2, 2, 64, 32)\n  ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113471686/virtualtree/freq,data/full_repos/permissive/113471686/vMERGE_SORTER_TREE\n             data/full_repos/permissive/113471686/virtualtree/freq,data/full_repos/permissive/113471686/vMERGE_SORTER_TREE.v\n             data/full_repos/permissive/113471686/virtualtree/freq,data/full_repos/permissive/113471686/vMERGE_SORTER_TREE.sv\n             vMERGE_SORTER_TREE\n             vMERGE_SORTER_TREE.v\n             vMERGE_SORTER_TREE.sv\n             obj_dir/vMERGE_SORTER_TREE\n             obj_dir/vMERGE_SORTER_TREE.v\n             obj_dir/vMERGE_SORTER_TREE.sv\n%Error: Exiting due to 1 error(s)\n"
module freq(input  wire CLK,
            input  wire RST_IN,
            output wire OUT);
  
  reg RST; always @(posedge CLK) RST <= RST_IN;
  
  reg  [(`DATW<<`P_LOG)-1:0] vmerge_sorter_tree_din;
  reg                        vmerge_sorter_tree_dinen;
  reg  [`W_LOG-1:0]          vmerge_sorter_tree_din_idx;
  wire [`DATW-1:0]           vmerge_sorter_tree_dot;
  wire                       vmerge_sorter_tree_doten;
  wire [(1<<`W_LOG)-1:0]     vmerge_sorter_tree_emp;

  always @(posedge CLK) begin
    if (RST) begin
      vmerge_sorter_tree_din     <= 1;
      vmerge_sorter_tree_dinen   <= 0;
      vmerge_sorter_tree_din_idx <= 0;
    end else begin
      vmerge_sorter_tree_din       <= vmerge_sorter_tree_din << 1;
      vmerge_sorter_tree_dinen     <= ~vmerge_sorter_tree_dinen;
      if (vmerge_sorter_tree_dinen) begin
        vmerge_sorter_tree_din_idx <= vmerge_sorter_tree_din_idx + 1;
      end
    end
  end
  
  vMERGE_SORTER_TREE #(`W_LOG, `P_LOG, `Q_SIZE, `FIFO_SIZE, `DATW, `KEYW)
  vmerge_sorter_tree(CLK, RST, 1'b0, vmerge_sorter_tree_din, vmerge_sorter_tree_dinen, vmerge_sorter_tree_din_idx, 
                     vmerge_sorter_tree_dot, vmerge_sorter_tree_doten, vmerge_sorter_tree_emp);
  
  reg [`DATW-1:0] dot_buf; 
  always @(posedge CLK) begin
    if (vmerge_sorter_tree_doten) dot_buf <= vmerge_sorter_tree_dot;
  end

  assign OUT = ^dot_buf;

endmodule
module freq(input  wire CLK,
            input  wire RST_IN,
            output wire OUT);

  
  reg RST; always @(posedge CLK) RST <= RST_IN;
  
  reg  [(`DATW<<`P_LOG)-1:0] vmerge_sorter_tree_din;
  reg                        vmerge_sorter_tree_dinen;
  reg  [`W_LOG-1:0]          vmerge_sorter_tree_din_idx;
  wire [`DATW-1:0]           vmerge_sorter_tree_dot;
  wire                       vmerge_sorter_tree_doten;
  wire [(1<<`W_LOG)-1:0]     vmerge_sorter_tree_emp;

  always @(posedge CLK) begin
    if (RST) begin
      vmerge_sorter_tree_din     <= 1;
      vmerge_sorter_tree_dinen   <= 0;
      vmerge_sorter_tree_din_idx <= 0;
    end else begin
      vmerge_sorter_tree_din       <= vmerge_sorter_tree_din << 1;
      vmerge_sorter_tree_dinen     <= ~vmerge_sorter_tree_dinen;
      if (vmerge_sorter_tree_dinen) begin
        vmerge_sorter_tree_din_idx <= vmerge_sorter_tree_din_idx + 1;
      end
    end
  end
  
  vMERGE_SORTER_TREE #(`W_LOG, `P_LOG, `Q_SIZE, `FIFO_SIZE, `DATW, `KEYW)
  vmerge_sorter_tree(CLK, RST, 1'b0, vmerge_sorter_tree_din, vmerge_sorter_tree_dinen, vmerge_sorter_tree_din_idx, 
                     vmerge_sorter_tree_dot, vmerge_sorter_tree_doten, vmerge_sorter_tree_emp);
  
  reg [`DATW-1:0] dot_buf; 
  always @(posedge CLK) begin
    if (vmerge_sorter_tree_doten) dot_buf <= vmerge_sorter_tree_dot;
  end

  assign OUT = ^dot_buf;

endmodule