data/full_repos/permissive/161473991/source/clock.v
data/verilator_xmls/0a7b17a1-ed93-46e3-9123-60eac9a88d01.xml
module counter_tube(input clk, rst, output clk_bps_tube);
    reg [13:0] cnt_first, cnt_second;
    always @(posedge clk or posedge rst)
        if(rst)
            cnt_first <= 14'd0;
        else if(cnt_first == 14'd10000)
            cnt_first <= 14'd0;
        else
            cnt_first <= cnt_first+1'b1;
    always @(posedge clk or posedge rst)
        if(rst)
            cnt_second <= 14'd0;
        else if(cnt_second == 14'd2500)
            cnt_second <= 14'd0;
        else if(cnt_first == 14'd10000)
            cnt_second <= cnt_second+1'b1;
    assign clk_bps_tube = cnt_second == 14'd2500 ? 1'b1:1'b0;
endmodule
module counter_tube(input clk, rst, output clk_bps_tube);

    reg [13:0] cnt_first, cnt_second;
    always @(posedge clk or posedge rst)
        if(rst)
            cnt_first <= 14'd0;
        else if(cnt_first == 14'd10000)
            cnt_first <= 14'd0;
        else
            cnt_first <= cnt_first+1'b1;
    always @(posedge clk or posedge rst)
        if(rst)
            cnt_second <= 14'd0;
        else if(cnt_second == 14'd2500)
            cnt_second <= 14'd0;
        else if(cnt_first == 14'd10000)
            cnt_second <= cnt_second+1'b1;
    assign clk_bps_tube = cnt_second == 14'd2500 ? 1'b1:1'b0;
endmodule