data/full_repos/permissive/170013753/test/regfile_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/170013753/test/regfile_tb.v:2: Cannot find include file: src/regfile.v\n`include "src/regfile.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170013753/test,data/full_repos/permissive/170013753/src/regfile.v\n             data/full_repos/permissive/170013753/test,data/full_repos/permissive/170013753/src/regfile.v.v\n             data/full_repos/permissive/170013753/test,data/full_repos/permissive/170013753/src/regfile.v.sv\n             src/regfile.v\n             src/regfile.v.v\n             src/regfile.v.sv\n             obj_dir/src/regfile.v\n             obj_dir/src/regfile.v.v\n             obj_dir/src/regfile.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/regfile_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    clk = ~clk; #5;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/170013753/test/regfile_tb.v:27: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("out/regfile.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/170013753/test/regfile_tb.v:28: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, regfile_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/regfile_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/regfile_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/regfile_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module regfile_tb;

  reg clk = 1'b0;
  reg rst = 1'b0;
  reg wen = 1'b0;

  reg [3:0]  selRd = 4'b0;
  reg [3:0]  selRs = 4'b0;
  reg [3:0]  selRt = 4'b0;
  reg [15:0] rd    = 16'b0;

  wire [15:0] rs;
  wire [15:0] rt;

  integer testIndex = 0;

  regfile UUT(clk, rst, wen, selRd, selRs, selRt, rd, rs, rt);

  always begin
    clk = ~clk; #5;
  end

  initial begin
    $dumpfile("out/regfile.vcd");
    $dumpvars(0, regfile_tb);

    wen = 1'b1;
    rst = 1'b1;
    #20;
    rst = 1'b0;
    rd = 16'b0;
    #20;

    for(testIndex = 0; testIndex < 15; testIndex++) begin
      rd = testIndex;
      selRd = testIndex;
      selRs = testIndex; 
      selRt = testIndex;
      #20;
    end

    $finish;
    $display("Testbench completed");
  end

endmodule
module regfile_tb;


  reg clk = 1'b0;
  reg rst = 1'b0;
  reg wen = 1'b0;

  reg [3:0]  selRd = 4'b0;
  reg [3:0]  selRs = 4'b0;
  reg [3:0]  selRt = 4'b0;
  reg [15:0] rd    = 16'b0;

  wire [15:0] rs;
  wire [15:0] rt;

  integer testIndex = 0;

  regfile UUT(clk, rst, wen, selRd, selRs, selRt, rd, rs, rt);

  always begin
    clk = ~clk; #5;
  end

  initial begin
    $dumpfile("out/regfile.vcd");
    $dumpvars(0, regfile_tb);

    wen = 1'b1;
    rst = 1'b1;
    #20;
    rst = 1'b0;
    rd = 16'b0;
    #20;

    for(testIndex = 0; testIndex < 15; testIndex++) begin
      rd = testIndex;
      selRd = testIndex;
      selRs = testIndex; 
      selRt = testIndex;
      #20;
    end

    $finish;
    $display("Testbench completed");
  end

endmodule