data/full_repos/permissive/190755935/src/comms/rtl/uart_out.v
 line:467: before: "("
1: b'%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_out.v:52: Cannot find include file: ../../pipe/rtl/pipe_defs.v\n`include "../../pipe/rtl/pipe_defs.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v.v\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v.sv\n             ../../pipe/rtl/pipe_defs.v\n             ../../pipe/rtl/pipe_defs.v.v\n             ../../pipe/rtl/pipe_defs.v.sv\n             obj_dir/../../pipe/rtl/pipe_defs.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.sv\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_out.v:54: Define or directive not defined: \'`PS_DATA\'\nmodule uart_out  #( parameter PipeSpec = `PS_DATA( 8 ), parameter ClockFrequency = 12000000, parameter BaudRate = 9600 ) (\n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_out.v:58: Define or directive not defined: \'`P_w\'\n        inout [`P_w(PipeSpec)-1:0] pipe_in,\n               ^~~~\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_out.v:63: Define or directive not defined: \'`P_Data_w\'\n    wire [`P_Data_w(PipeSpec)-1:0] in_data;\n          ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module uart_out_np #( parameter ClockFrequency = 12000000, parameter BaudRate = 9600 )(
        input clock,
        input reset,

        input [7:0] out_data,
        input       out_valid,
        output      out_ready,

        output uart_tx
    );




    generate
        if( ClockFrequency < BaudRate * 8 && ( ClockFrequency % BaudRate != 0 ) ) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested BaudRate rate");
    endgenerate

    `ifdef SIMULATION
        wire BitTick = 1'b1;
    `else
        wire BitTick;
        uart_out_baudrate_gen #( ClockFrequency, BaudRate ) tickgen( .clock( clock ), .enable( ~out_ready ), .tick( BitTick ) );
    `endif

    reg [3:0] uart_state = 0;
    wire uart_ready = (uart_state==0);
    assign out_ready = uart_ready;

    reg [7:0] uart_shift = 0;
    always @(posedge clock)
    begin
        if ( reset ) begin
            uart_state <= 0;
        end else begin
            if( uart_ready & out_valid )
                uart_shift <= out_data;
            else
                if(uart_state[3] & BitTick)
                    uart_shift <= (uart_shift >> 1);

            case(uart_state)
                4'b0000: if(out_valid) uart_state <= 4'b0100;
                4'b0100: if(BitTick) uart_state <= 4'b1000;
                4'b1000: if(BitTick) uart_state <= 4'b1001;
                4'b1001: if(BitTick) uart_state <= 4'b1010;
                4'b1010: if(BitTick) uart_state <= 4'b1011;
                4'b1011: if(BitTick) uart_state <= 4'b1100;
                4'b1100: if(BitTick) uart_state <= 4'b1101;
                4'b1101: if(BitTick) uart_state <= 4'b1110;
                4'b1110: if(BitTick) uart_state <= 4'b1111;
                4'b1111: if(BitTick) uart_state <= 4'b0010;
                4'b0010: if(BitTick) uart_state <= 4'b0000;
                4'b0011: if(BitTick) uart_state <= 4'b0000;
                default: if(BitTick) uart_state <= 4'b0000;
            endcase
        end
    end

    assign uart_tx = (uart_state<4) | (uart_state[3] & uart_shift[0]);

endmodule
module uart_out_np #( parameter ClockFrequency = 12000000, parameter BaudRate = 9600 )(
        input clock,
        input reset,

        input [7:0] out_data,
        input       out_valid,
        output      out_ready,

        output uart_tx
    );





    generate
        if( ClockFrequency < BaudRate * 8 && ( ClockFrequency % BaudRate != 0 ) ) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested BaudRate rate");
    endgenerate

    `ifdef SIMULATION
        wire BitTick = 1'b1;
    `else
        wire BitTick;
        uart_out_baudrate_gen #( ClockFrequency, BaudRate ) tickgen( .clock( clock ), .enable( ~out_ready ), .tick( BitTick ) );
    `endif

    reg [3:0] uart_state = 0;
    wire uart_ready = (uart_state==0);
    assign out_ready = uart_ready;

    reg [7:0] uart_shift = 0;
    always @(posedge clock)
    begin
        if ( reset ) begin
            uart_state <= 0;
        end else begin
            if( uart_ready & out_valid )
                uart_shift <= out_data;
            else
                if(uart_state[3] & BitTick)
                    uart_shift <= (uart_shift >> 1);

            case(uart_state)
                4'b0000: if(out_valid) uart_state <= 4'b0100;
                4'b0100: if(BitTick) uart_state <= 4'b1000;
                4'b1000: if(BitTick) uart_state <= 4'b1001;
                4'b1001: if(BitTick) uart_state <= 4'b1010;
                4'b1010: if(BitTick) uart_state <= 4'b1011;
                4'b1011: if(BitTick) uart_state <= 4'b1100;
                4'b1100: if(BitTick) uart_state <= 4'b1101;
                4'b1101: if(BitTick) uart_state <= 4'b1110;
                4'b1110: if(BitTick) uart_state <= 4'b1111;
                4'b1111: if(BitTick) uart_state <= 4'b0010;
                4'b0010: if(BitTick) uart_state <= 4'b0000;
                4'b0011: if(BitTick) uart_state <= 4'b0000;
                default: if(BitTick) uart_state <= 4'b0000;
            endcase
        end
    end

    assign uart_tx = (uart_state<4) | (uart_state[3] & uart_shift[0]);

endmodule