data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_seven_seg_5.v
1: b'%Error: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_seven_seg_5.v:27: Cannot find file containing module: \'counter_9\'\n  counter_9 ctr (\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/counter_9\n             data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/counter_9.v\n             data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/counter_9.sv\n             counter_9\n             counter_9.v\n             counter_9.sv\n             obj_dir/counter_9\n             obj_dir/counter_9.v\n             obj_dir/counter_9.sv\n%Error: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_seven_seg_5.v:35: Cannot find file containing module: \'seven_seg_10\'\n  seven_seg_10 seg_dec (\n  ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_seven_seg_5.v:43: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_ctr_value\' generates 3 bits.\n                                                                                                       : ... In instance multi_seven_seg_5\n    sel = M_ctr_value;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module multi_seven_seg_5 (
    input clk,
    input rst,
    input [39:0] values,
    output reg [6:0] seg,
    output reg [7:0] sel
  );
  
  localparam DIGITS = 4'h8;
  localparam DIV = 1'h1;
  
  
  localparam DIGIT_BITS = 2'h3;
  
  wire [3-1:0] M_ctr_value;
  counter_9 ctr (
    .clk(clk),
    .rst(rst),
    .value(M_ctr_value)
  );
  
  wire [7-1:0] M_seg_dec_segs;
  reg [5-1:0] M_seg_dec_char;
  seven_seg_10 seg_dec (
    .char(M_seg_dec_char),
    .segs(M_seg_dec_segs)
  );
  
  always @* begin
    M_seg_dec_char = values[(M_ctr_value)*5+4-:5];
    seg = M_seg_dec_segs;
    sel = M_ctr_value;
  end
endmodule
module multi_seven_seg_5 (
    input clk,
    input rst,
    input [39:0] values,
    output reg [6:0] seg,
    output reg [7:0] sel
  );

  
  localparam DIGITS = 4'h8;
  localparam DIV = 1'h1;
  
  
  localparam DIGIT_BITS = 2'h3;
  
  wire [3-1:0] M_ctr_value;
  counter_9 ctr (
    .clk(clk),
    .rst(rst),
    .value(M_ctr_value)
  );
  
  wire [7-1:0] M_seg_dec_segs;
  reg [5-1:0] M_seg_dec_char;
  seven_seg_10 seg_dec (
    .char(M_seg_dec_char),
    .segs(M_seg_dec_segs)
  );
  
  always @* begin
    M_seg_dec_char = values[(M_ctr_value)*5+4-:5];
    seg = M_seg_dec_segs;
    sel = M_ctr_value;
  end
endmodule