data/full_repos/permissive/161517951/controle.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161517951/controle.v:24: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                  : ... In instance controle\n tula = 1\'b0;\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161517951/controle.v:31: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                  : ... In instance controle\n tula = 1\'b0;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/161517951/controle.v:38: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                  : ... In instance controle\n tula = 1\'b0;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/161517951/controle.v:44: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                  : ... In instance controle\n tula = 1\'b0;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/161517951/controle.v:51: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                  : ... In instance controle\n tula = 1\'b0;\n      ^\n%Error: Exiting due to 5 warning(s)\n'
module controle (clock, Op, tx, ty, tz, tula);

input wire [2:0]Op; 
input wire clock;

output reg[3:0]tx;
output reg[3:0]ty;
output reg[3:0]tz;
output reg[3:0]tula;







 always @(posedge clock)begin
case(Op)

  3'b000:begin
	tx = 4'b0001;
	ty = 4'b0000;
	tz = 4'b0000;
	tula = 1'b0;
 end
 
   3'b001:begin
	tx = 4'b0001;
	ty = 4'b0001;
	tz = 4'b0010;
	tula = 1'b0;
 end
 
   3'b010:begin
	tx = 4'b0000;
	ty = 4'b0001;
	tz = 4'b0010;
	tula = 1'b0;
 end
 3'b011:begin
	tx = 4'b0010;
	ty = 4'b0011;
	tz = 4'b0010;
	tula = 1'b0;
 end
 
  3'b100:begin
	tx = 4'b0010;
	ty = 4'b0000;
	tz = 4'b0001;
	tula = 1'b0;
 end
endcase 
end

endmodule
module controle (clock, Op, tx, ty, tz, tula);


input wire [2:0]Op; 
input wire clock;

output reg[3:0]tx;
output reg[3:0]ty;
output reg[3:0]tz;
output reg[3:0]tula;







 always @(posedge clock)begin
case(Op)

  3'b000:begin
	tx = 4'b0001;
	ty = 4'b0000;
	tz = 4'b0000;
	tula = 1'b0;
 end
 
   3'b001:begin
	tx = 4'b0001;
	ty = 4'b0001;
	tz = 4'b0010;
	tula = 1'b0;
 end
 
   3'b010:begin
	tx = 4'b0000;
	ty = 4'b0001;
	tz = 4'b0010;
	tula = 1'b0;
 end
 3'b011:begin
	tx = 4'b0010;
	ty = 4'b0011;
	tz = 4'b0010;
	tula = 1'b0;
 end
 
  3'b100:begin
	tx = 4'b0010;
	ty = 4'b0000;
	tz = 4'b0001;
	tula = 1'b0;
 end
endcase 
end

endmodule