data/full_repos/permissive/189415563/TestBench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/189415563/TestBench.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #10 rst_n = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/189415563/TestBench.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/189415563/TestBench.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/189415563/TestBench.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189415563/TestBench.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #50 ena = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189415563/TestBench.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189415563/TestBench.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189415563/TestBench.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189415563/TestBench.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189415563/TestBench.v:142: Unsupported: Ignoring delay on this delayed statement.\n   #10 clk <= !clk;                                                 \n   ^\n%Error: data/full_repos/permissive/189415563/TestBench.v:152: syntax error, unexpected \'@\'\n@eachvec;                                              \n^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DCT_vlg_tst();


reg eachvec;

reg clk;
reg [8:0] data_in0;
reg [8:0] data_in1;
reg [8:0] data_in2;
reg [8:0] data_in3;
reg [8:0] data_in4;
reg [8:0] data_in5;
reg [8:0] data_in6;
reg [8:0] data_in7;
reg ena;
reg rst_n;

wire [9:0]  M0;
wire [9:0]  M1;
wire [9:0]  M2;
wire [9:0]  M3;
wire [10:0]  M03;
wire [11:0]  M4;
wire [10:0]  M12;
wire [9:0]  P0;
wire [9:0]  P1;
wire [9:0]  P2;
wire [9:0]  P3;
wire [10:0]  P03;
wire [11:0]  P4;
wire [10:0]  P12;
wire [18:0]  data_out0;
wire [18:0]  data_out1;
wire [18:0]  data_out2;
wire [18:0]  data_out3;
wire [18:0]  data_out4;
wire [18:0]  data_out5;
wire [18:0]  data_out6;
wire [18:0]  data_out7;
wire done;
wire pipe0;
wire pipe1;
wire pipe2;
wire pipe3;
wire pipe4;


DCT i1 (

	.M0(M0),
	.M1(M1),
	.M2(M2),
	.M3(M3),
	.M03(M03),
	.M4(M4),
	.M12(M12),
	.P0(P0),
	.P1(P1),
	.P2(P2),
	.P3(P3),
	.P03(P03),
	.P4(P4),
	.P12(P12),
	.clk(clk),
	.data_in0(data_in0),
	.data_in1(data_in1),
	.data_in2(data_in2),
	.data_in3(data_in3),
	.data_in4(data_in4),
	.data_in5(data_in5),
	.data_in6(data_in6),
	.data_in7(data_in7),
	.data_out0(data_out0),
	.data_out1(data_out1),
	.data_out2(data_out2),
	.data_out3(data_out3),
	.data_out4(data_out4),
	.data_out5(data_out5),
	.data_out6(data_out6),
	.data_out7(data_out7),
	.done(done),
	.ena(ena),
	.pipe0(pipe0),
	.pipe1(pipe1),
	.pipe2(pipe2),
	.pipe3(pipe3),
	.pipe4(pipe4),
	.rst_n(rst_n)
);
initial                                                
begin                                                  
  #10 rst_n = 0;
    #10 rst_n = 1;
    #10 clk = 0;	
	 #100;
	 data_in0 = 8'd255;
    data_in1 = 8'd0;
    data_in2 = 8'd0;
    data_in3 = 8'd255;
    data_in4 = 8'd255;
    data_in5 = 8'd0;
    data_in6 = 8'd0;
    data_in7 = 8'd255;
	 #50 ena = 1;
	 #40;
	 data_in0 = 8'd155;
    data_in1 = 8'd0;
    data_in2 = 8'd0;
    data_in3 = 8'd155;
    data_in4 = 8'd155;
    data_in5 = 8'd0;
    data_in6 = 8'd0;
    data_in7 = 8'd155;
	 #40;
	 data_in0 = 8'd10;
    data_in1 = 8'd50;
    data_in2 = 8'd100;
    data_in3 = 8'd150;
    data_in4 = 8'd200;
    data_in5 = 8'd250;
    data_in6 = 8'd100;
    data_in7 = 8'd0;
	 #20;
	 data_in0 = 8'd155;
    data_in1 = 8'd154;
    data_in2 = 8'd153;
    data_in3 = 8'd152;
    data_in4 = 8'd151;
    data_in5 = 8'd150;
    data_in6 = 8'd149;
    data_in7 = 8'd148;
	 #500;
	 $stop;                                          
$display("Running testbench");                       
end   
initial                                                
begin  
forever 
	  begin
		 #10 clk <= !clk;                                                 
	  end
end                                                 
always                                                 


begin                                                  


                                                       
@eachvec;                                              

end                                                  
endmodule
module DCT_vlg_tst();



reg eachvec;

reg clk;
reg [8:0] data_in0;
reg [8:0] data_in1;
reg [8:0] data_in2;
reg [8:0] data_in3;
reg [8:0] data_in4;
reg [8:0] data_in5;
reg [8:0] data_in6;
reg [8:0] data_in7;
reg ena;
reg rst_n;

wire [9:0]  M0;
wire [9:0]  M1;
wire [9:0]  M2;
wire [9:0]  M3;
wire [10:0]  M03;
wire [11:0]  M4;
wire [10:0]  M12;
wire [9:0]  P0;
wire [9:0]  P1;
wire [9:0]  P2;
wire [9:0]  P3;
wire [10:0]  P03;
wire [11:0]  P4;
wire [10:0]  P12;
wire [18:0]  data_out0;
wire [18:0]  data_out1;
wire [18:0]  data_out2;
wire [18:0]  data_out3;
wire [18:0]  data_out4;
wire [18:0]  data_out5;
wire [18:0]  data_out6;
wire [18:0]  data_out7;
wire done;
wire pipe0;
wire pipe1;
wire pipe2;
wire pipe3;
wire pipe4;


DCT i1 (

	.M0(M0),
	.M1(M1),
	.M2(M2),
	.M3(M3),
	.M03(M03),
	.M4(M4),
	.M12(M12),
	.P0(P0),
	.P1(P1),
	.P2(P2),
	.P3(P3),
	.P03(P03),
	.P4(P4),
	.P12(P12),
	.clk(clk),
	.data_in0(data_in0),
	.data_in1(data_in1),
	.data_in2(data_in2),
	.data_in3(data_in3),
	.data_in4(data_in4),
	.data_in5(data_in5),
	.data_in6(data_in6),
	.data_in7(data_in7),
	.data_out0(data_out0),
	.data_out1(data_out1),
	.data_out2(data_out2),
	.data_out3(data_out3),
	.data_out4(data_out4),
	.data_out5(data_out5),
	.data_out6(data_out6),
	.data_out7(data_out7),
	.done(done),
	.ena(ena),
	.pipe0(pipe0),
	.pipe1(pipe1),
	.pipe2(pipe2),
	.pipe3(pipe3),
	.pipe4(pipe4),
	.rst_n(rst_n)
);
initial                                                
begin                                                  
  #10 rst_n = 0;
    #10 rst_n = 1;
    #10 clk = 0;	
	 #100;
	 data_in0 = 8'd255;
    data_in1 = 8'd0;
    data_in2 = 8'd0;
    data_in3 = 8'd255;
    data_in4 = 8'd255;
    data_in5 = 8'd0;
    data_in6 = 8'd0;
    data_in7 = 8'd255;
	 #50 ena = 1;
	 #40;
	 data_in0 = 8'd155;
    data_in1 = 8'd0;
    data_in2 = 8'd0;
    data_in3 = 8'd155;
    data_in4 = 8'd155;
    data_in5 = 8'd0;
    data_in6 = 8'd0;
    data_in7 = 8'd155;
	 #40;
	 data_in0 = 8'd10;
    data_in1 = 8'd50;
    data_in2 = 8'd100;
    data_in3 = 8'd150;
    data_in4 = 8'd200;
    data_in5 = 8'd250;
    data_in6 = 8'd100;
    data_in7 = 8'd0;
	 #20;
	 data_in0 = 8'd155;
    data_in1 = 8'd154;
    data_in2 = 8'd153;
    data_in3 = 8'd152;
    data_in4 = 8'd151;
    data_in5 = 8'd150;
    data_in6 = 8'd149;
    data_in7 = 8'd148;
	 #500;
	 $stop;                                          
$display("Running testbench");                       
end   
initial                                                
begin  
forever 
	  begin
		 #10 clk <= !clk;                                                 
	  end
end                                                 
always                                                 


begin                                                  


                                                       
@eachvec;                                              

end                                                  
endmodule