data/full_repos/permissive/219219909/Complex_Multiplier/buf35.v
data/verilator_xmls/836c9d71-99e0-4ff7-9554-4bdefaea8548.xml
module buf35(
    input [23:0] c_m,
    input [7:0] c_e,
    input c_s,
    input clk,
    output reg [31:0] c
    );
always @(posedge clk) begin

c<={c_s,c_e,c_m[22:0]};

end

endmodule
module buf35(
    input [23:0] c_m,
    input [7:0] c_e,
    input c_s,
    input clk,
    output reg [31:0] c
    );

always @(posedge clk) begin

c<={c_s,c_e,c_m[22:0]};

end

endmodule