data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v
 line:21: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:12: Unsupported: Ignoring delay on this delayed statement.\n  RTR_SRR_tb = 1\'b0; IDE_tb = 1\'b0;   RTR_r1_tb = 1\'b0; #5\n                                                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:13: Unsupported: Ignoring delay on this delayed statement.\n  RTR_SRR_tb = 1\'b0; IDE_tb = 1\'b0;   RTR_r1_tb = 1\'b1; #5\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:14: Unsupported: Ignoring delay on this delayed statement.\n  RTR_SRR_tb = 1\'b0; IDE_tb = 1\'b1;   RTR_r1_tb = 1\'b0; #5\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:15: Unsupported: Ignoring delay on this delayed statement.\n  RTR_SRR_tb = 1\'b0; IDE_tb = 1\'b1;   RTR_r1_tb = 1\'b1; #5\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:16: Unsupported: Ignoring delay on this delayed statement.\n  RTR_SRR_tb = 1\'b1; IDE_tb = 1\'b0;   RTR_r1_tb = 1\'b0; #5\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:17: Unsupported: Ignoring delay on this delayed statement.\n  RTR_SRR_tb = 1\'b1; IDE_tb = 1\'b0;   RTR_r1_tb = 1\'b1; #5\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n  RTR_SRR_tb = 1\'b1; IDE_tb = 1\'b1;   RTR_r1_tb = 1\'b0; #5\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:19: Unsupported: Ignoring delay on this delayed statement.\n  RTR_SRR_tb = 1\'b1; IDE_tb = 1\'b1;   RTR_r1_tb = 1\'b1; #5\n                                                        ^\n%Error: data/full_repos/permissive/107735152/src/framemaker/DatavsRemote_TB.v:7: Cannot find file containing module: \'DatavsRemote\'\n DatavsRemote dut(RTR_SRR_tb, IDE_tb, RTR_r1_tb, isRemote_tb);\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/DatavsRemote\n             data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/DatavsRemote.v\n             data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/DatavsRemote.sv\n             DatavsRemote\n             DatavsRemote.v\n             DatavsRemote.sv\n             obj_dir/DatavsRemote\n             obj_dir/DatavsRemote.v\n             obj_dir/DatavsRemote.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DatavsRemote_TB;
	
	reg 	RTR_SRR_tb, IDE_tb, RTR_r1_tb;
	wire  isRemote_tb;

	DatavsRemote dut(RTR_SRR_tb, IDE_tb, RTR_r1_tb, isRemote_tb);
	
	initial
	begin
		
		RTR_SRR_tb = 1'b0;	IDE_tb = 1'b0;  	RTR_r1_tb = 1'b0; #5
		RTR_SRR_tb = 1'b0;	IDE_tb = 1'b0;  	RTR_r1_tb = 1'b1; #5
		RTR_SRR_tb = 1'b0;	IDE_tb = 1'b1;  	RTR_r1_tb = 1'b0; #5
		RTR_SRR_tb = 1'b0;	IDE_tb = 1'b1;  	RTR_r1_tb = 1'b1; #5
		RTR_SRR_tb = 1'b1;	IDE_tb = 1'b0;  	RTR_r1_tb = 1'b0; #5
		RTR_SRR_tb = 1'b1;	IDE_tb = 1'b0;  	RTR_r1_tb = 1'b1; #5
		RTR_SRR_tb = 1'b1;	IDE_tb = 1'b1;  	RTR_r1_tb = 1'b0;	#5
		RTR_SRR_tb = 1'b1;	IDE_tb = 1'b1;  	RTR_r1_tb = 1'b1;	#5

		$stop;
	end
endmodule
module DatavsRemote_TB;

	
	reg 	RTR_SRR_tb, IDE_tb, RTR_r1_tb;
	wire  isRemote_tb;

	DatavsRemote dut(RTR_SRR_tb, IDE_tb, RTR_r1_tb, isRemote_tb);
	
	initial
	begin
		
		RTR_SRR_tb = 1'b0;	IDE_tb = 1'b0;  	RTR_r1_tb = 1'b0; #5
		RTR_SRR_tb = 1'b0;	IDE_tb = 1'b0;  	RTR_r1_tb = 1'b1; #5
		RTR_SRR_tb = 1'b0;	IDE_tb = 1'b1;  	RTR_r1_tb = 1'b0; #5
		RTR_SRR_tb = 1'b0;	IDE_tb = 1'b1;  	RTR_r1_tb = 1'b1; #5
		RTR_SRR_tb = 1'b1;	IDE_tb = 1'b0;  	RTR_r1_tb = 1'b0; #5
		RTR_SRR_tb = 1'b1;	IDE_tb = 1'b0;  	RTR_r1_tb = 1'b1; #5
		RTR_SRR_tb = 1'b1;	IDE_tb = 1'b1;  	RTR_r1_tb = 1'b0;	#5
		RTR_SRR_tb = 1'b1;	IDE_tb = 1'b1;  	RTR_r1_tb = 1'b1;	#5

		$stop;
	end
endmodule