data/full_repos/permissive/143278/ivltests/br_ml20150606.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_ml20150606.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/br_ml20150606.v:3: Duplicate declaration of signal: \'DataI\'\n                                                                    : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire [3:0] DataI;\n           ^~~~~\n        data/full_repos/permissive/143278/ivltests/br_ml20150606.v:1: ... Location of original declaration\nmodule dut(input [3:0] DataI, output [3:0] DataO);\n                       ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/br_ml20150606.v:4: Duplicate declaration of signal: \'DataO\'\nreg  [3:0] DataO;\n           ^~~~~\n        data/full_repos/permissive/143278/ivltests/br_ml20150606.v:1: ... Location of original declaration\nmodule dut(input [3:0] DataI, output [3:0] DataO);\n                                           ^~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top();

reg  [3:0] DataI;
wire [3:0] DataO;

dut dut(DataI, DataO);

initial begin
  DataI = 5;
  #1;
  if (DataO === 5)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module top();


reg  [3:0] DataI;
wire [3:0] DataO;

dut dut(DataI, DataO);

initial begin
  DataI = 5;
  #1;
  if (DataO === 5)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule