data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b9.v
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1: b'%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b9.v:18: Cannot find file containing module: \'jt74194\'\n jt74194 u_4A(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74194\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74194.v\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74194.sv\n             jt74194\n             jt74194.v\n             jt74194.sv\n             obj_dir/jt74194\n             obj_dir/jt74194.v\n             obj_dir/jt74194.sv\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b9.v:28: Cannot find file containing module: \'jt74194\'\n jt74194 u_4B(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b9.v:82: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 15 bits.\n                                                                                 : ... In instance jt_gng_b9\n addr = { AS, addr_lsb };\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module jt_gng_b9(
	input [9:0]		AS,
	input			SH8,
	input			SHFLIP,
	input			SHFLIP_q,
	input			V8S,
	input			V4S,
	input			V2S,
	input			V1S,
	input			SVFLIP,
	input			S6M,
	input			FLIP_buf,
	output			SCRX,
	output			SCRY,
	output			SCRZ,
	input			S7H_b
);

reg [7:0] 	mem_3b [0:16383];
reg [7:0]	mem_3c [0:16383];
reg [7:0]	mem_3e [0:16383];
reg [7:0]	mem_1b [0:16383];
reg [7:0]	mem_1c [0:16383];
reg [7:0]	mem_1e [0:16383];

initial begin
	$readmemh("../../rom/3b.hex", mem_3b);
	$readmemh("../../rom/3c.hex", mem_3c);
	$readmemh("../../rom/3e.hex", mem_3e);
	$readmemh("../../rom/1b.hex", mem_1b);
	$readmemh("../../rom/1c.hex", mem_1c);
	$readmemh("../../rom/1e.hex", mem_1e);
end

reg [4:0] addr_lsb;

always @(*)
	addr_lsb = { SHFLIP^SH8, {4{SVFLIP}}^{V8S,V4S,V2S,V1S} };

reg [13:0] addr;

always @(*)
	addr = { AS, addr_lsb };

reg [7:0] X,Y,Z;

always @(addr,AS[9])
	if( AS[9] ) begin
		X = mem_3b[addr];
		Y = mem_3c[addr];
		Z = mem_3e[addr];
	end
	else begin
		X = mem_1b[addr];
		Y = mem_1c[addr];
		Z = mem_1e[addr];
	end

wire XL, YL, ZL;
reg [1:0] S;
wire [3:0] Q4A, Q4B;
wire SEL = FLIP_buf ^ SHFLIP_q;

always @(*) begin
	S[0] = ~S7H_b |  SEL;
	S[1] = ~S7H_b | ~SEL;
end

shift8 U4AB( .D(X), .clk(S6M), .S(S), .Y(SCRX), .SEL(SEL) );
shift8 U4CD( .D(Y), .clk(S6M), .S(S), .Y(SCRY), .SEL(SEL) );
shift8 U4EF( .D(Z), .clk(S6M), .S(S), .Y(SCRZ), .SEL(SEL) );

endmodule
module jt_gng_b9(
	input [9:0]		AS,
	input			SH8,
	input			SHFLIP,
	input			SHFLIP_q,
	input			V8S,
	input			V4S,
	input			V2S,
	input			V1S,
	input			SVFLIP,
	input			S6M,
	input			FLIP_buf,
	output			SCRX,
	output			SCRY,
	output			SCRZ,
	input			S7H_b
);


reg [7:0] 	mem_3b [0:16383];
reg [7:0]	mem_3c [0:16383];
reg [7:0]	mem_3e [0:16383];
reg [7:0]	mem_1b [0:16383];
reg [7:0]	mem_1c [0:16383];
reg [7:0]	mem_1e [0:16383];

initial begin
	$readmemh("../../rom/3b.hex", mem_3b);
	$readmemh("../../rom/3c.hex", mem_3c);
	$readmemh("../../rom/3e.hex", mem_3e);
	$readmemh("../../rom/1b.hex", mem_1b);
	$readmemh("../../rom/1c.hex", mem_1c);
	$readmemh("../../rom/1e.hex", mem_1e);
end

reg [4:0] addr_lsb;

always @(*)
	addr_lsb = { SHFLIP^SH8, {4{SVFLIP}}^{V8S,V4S,V2S,V1S} };

reg [13:0] addr;

always @(*)
	addr = { AS, addr_lsb };

reg [7:0] X,Y,Z;

always @(addr,AS[9])
	if( AS[9] ) begin
		X = mem_3b[addr];
		Y = mem_3c[addr];
		Z = mem_3e[addr];
	end
	else begin
		X = mem_1b[addr];
		Y = mem_1c[addr];
		Z = mem_1e[addr];
	end

wire XL, YL, ZL;
reg [1:0] S;
wire [3:0] Q4A, Q4B;
wire SEL = FLIP_buf ^ SHFLIP_q;

always @(*) begin
	S[0] = ~S7H_b |  SEL;
	S[1] = ~S7H_b | ~SEL;
end

shift8 U4AB( .D(X), .clk(S6M), .S(S), .Y(SCRX), .SEL(SEL) );
shift8 U4CD( .D(Y), .clk(S6M), .S(S), .Y(SCRY), .SEL(SEL) );
shift8 U4EF( .D(Z), .clk(S6M), .S(S), .Y(SCRZ), .SEL(SEL) );

endmodule