data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram.v:33: Bit extraction of array[65535:0] requires 16 bit index, not 14 bits.\n                                                                                            : ... In instance ram\nassign d_read_data = ram[d_address[ADDR_WIDTH-1:2]];\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram.v:34: Bit extraction of array[65535:0] requires 16 bit index, not 14 bits.\n                                                                                            : ... In instance ram\nassign i_read_data = ram[i_address[ADDR_WIDTH-1:2]]; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram.v:40: Bit extraction of array[65535:0] requires 16 bit index, not 14 bits.\n                                                                                            : ... In instance ram\n  ram[d_address[ADDR_WIDTH-1:2]]<=d_write_data;\n     ^\n%Error: Exiting due to 3 warning(s)\n'
module ram #(
  parameter DATA_WIDTH = 32,
  parameter ADDR_WIDTH = 16
) (
  input  clock,


  input  [ADDR_WIDTH-1:0] i_address,
  output [DATA_WIDTH-1:0] i_read_data, 


  input  wEn,
  input  [ADDR_WIDTH-1:0] d_address, 
  input  [DATA_WIDTH-1:0] d_write_data,
  output [DATA_WIDTH-1:0] d_read_data

);

localparam RAM_DEPTH = 1 << ADDR_WIDTH; 

reg [DATA_WIDTH-1:0] ram [0:RAM_DEPTH-1];







assign d_read_data = ram[d_address[ADDR_WIDTH-1:2]];
assign i_read_data = ram[i_address[ADDR_WIDTH-1:2]]; 



always @(posedge clock) begin
	if (wEn==1) begin
		ram[d_address[ADDR_WIDTH-1:2]]<=d_write_data;
	end
end

endmodule
module ram #(
  parameter DATA_WIDTH = 32,
  parameter ADDR_WIDTH = 16
) (
  input  clock,


  input  [ADDR_WIDTH-1:0] i_address,
  output [DATA_WIDTH-1:0] i_read_data, 


  input  wEn,
  input  [ADDR_WIDTH-1:0] d_address, 
  input  [DATA_WIDTH-1:0] d_write_data,
  output [DATA_WIDTH-1:0] d_read_data

);


localparam RAM_DEPTH = 1 << ADDR_WIDTH; 

reg [DATA_WIDTH-1:0] ram [0:RAM_DEPTH-1];







assign d_read_data = ram[d_address[ADDR_WIDTH-1:2]];
assign i_read_data = ram[i_address[ADDR_WIDTH-1:2]]; 



always @(posedge clock) begin
	if (wEn==1) begin
		ram[d_address[ADDR_WIDTH-1:2]]<=d_write_data;
	end
end

endmodule