data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v:5: Cannot find include file: spio_uart_common.h\n`include "spio_uart_common.h" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/modules/uart,data/full_repos/permissive/19591557/spio_uart_common.h\n             data/full_repos/permissive/19591557/modules/uart,data/full_repos/permissive/19591557/spio_uart_common.h.v\n             data/full_repos/permissive/19591557/modules/uart,data/full_repos/permissive/19591557/spio_uart_common.h.sv\n             spio_uart_common.h\n             spio_uart_common.h.v\n             spio_uart_common.h.sv\n             obj_dir/spio_uart_common.h\n             obj_dir/spio_uart_common.h.v\n             obj_dir/spio_uart_common.h.sv\n%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v:124: Define or directive not defined: \'`LINE_IDLE\'\n  TX_OUT = `LINE_IDLE;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v:124: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  TX_OUT = `LINE_IDLE;\n                     ^\n%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v:128: Define or directive not defined: \'`LINE_IDLE\'\n    TX_OUT = `LINE_IDLE;\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v:128: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    TX_OUT = `LINE_IDLE;\n                       ^\n%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v:132: Define or directive not defined: \'`LINE_IDLE\'\n    TX_OUT = `LINE_IDLE;\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v:132: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    TX_OUT = `LINE_IDLE;\n                       ^\n%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v:135: Define or directive not defined: \'`START_BIT\'\n    TX_OUT = `START_BIT;\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v:135: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    TX_OUT = `START_BIT;\n                       ^\n%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v:142: Define or directive not defined: \'`STOP_BIT\'\n    TX_OUT = `STOP_BIT;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_tx.v:142: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    TX_OUT = `STOP_BIT;\n                      ^\n%Error: Exiting due to 11 error(s)\n'
module spio_uart_tx (
                      input wire CLK_IN

                    , input wire RESET_IN


                    ,   input  wire [7:0] DATA_IN
                    ,   input  wire       VLD_IN
                    ,   output reg        RDY_OUT

                    ,   input wire BAUD_PULSE_IN

                    , output reg TX_OUT
                    );


localparam STATE_RESET = 8;


localparam STATE_IDLE = 9;


localparam STATE_START = 10;


localparam STATE_STOP = 11;


localparam STATE_BIT0 = 0;
localparam STATE_BIT1 = 1;
localparam STATE_BIT2 = 2;
localparam STATE_BIT3 = 3;
localparam STATE_BIT4 = 4;
localparam STATE_BIT5 = 5;
localparam STATE_BIT6 = 6;
localparam STATE_BIT7 = 7;


reg [3:0] state_i;


reg [7:0] data_i;





always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		state_i <= STATE_RESET;
	else
		if (state_i == STATE_RESET)
			state_i <= STATE_IDLE;
		else if (BAUD_PULSE_IN)
			case (state_i)
				STATE_IDLE: if (!RDY_OUT||VLD_IN) state_i <= STATE_START;
				STATE_START:                      state_i <= STATE_BIT0;
				STATE_BIT0:                       state_i <= STATE_BIT1;
				STATE_BIT1:                       state_i <= STATE_BIT2;
				STATE_BIT2:                       state_i <= STATE_BIT3;
				STATE_BIT3:                       state_i <= STATE_BIT4;
				STATE_BIT4:                       state_i <= STATE_BIT5;
				STATE_BIT5:                       state_i <= STATE_BIT6;
				STATE_BIT6:                       state_i <= STATE_BIT7;
				STATE_BIT7:                       state_i <= STATE_STOP;
				STATE_STOP: if (!RDY_OUT||VLD_IN) state_i <= STATE_START;
				            else                  state_i <= STATE_IDLE;
				
				default:
					state_i <= STATE_RESET;
			endcase








always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		RDY_OUT <= 1'b0;
	else
		if (RDY_OUT && VLD_IN)
			RDY_OUT <= 1'b0;
		else if (state_i == STATE_RESET)
			RDY_OUT <= 1'b1;
		else if (state_i == STATE_BIT7 && BAUD_PULSE_IN)
			RDY_OUT <= 1'b1;






always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		data_i <= 8'hXX;
	else
		if (RDY_OUT && VLD_IN)
			data_i <= DATA_IN;
		else if (BAUD_PULSE_IN
		        && (  state_i == STATE_BIT0 || state_i == STATE_BIT1
		           || state_i == STATE_BIT2 || state_i == STATE_BIT3
		           || state_i == STATE_BIT4 || state_i == STATE_BIT5
		           || state_i == STATE_BIT6 || state_i == STATE_BIT7
		           )
		        )
			data_i <= {1'bX, data_i[7:1]};






always @ (*)
	if (RESET_IN)
		TX_OUT = `LINE_IDLE;
	else
		case (state_i)
			default:
				TX_OUT = `LINE_IDLE;
			
			STATE_RESET,
			STATE_IDLE:
				TX_OUT = `LINE_IDLE;
			
			STATE_START:
				TX_OUT = `START_BIT;
			
			STATE_BIT0, STATE_BIT1, STATE_BIT2, STATE_BIT3,
			STATE_BIT4, STATE_BIT5, STATE_BIT6, STATE_BIT7:
				TX_OUT = data_i[0];
			
			STATE_STOP:
				TX_OUT = `STOP_BIT;
		endcase


endmodule
module spio_uart_tx (
                      input wire CLK_IN

                    , input wire RESET_IN


                    ,   input  wire [7:0] DATA_IN
                    ,   input  wire       VLD_IN
                    ,   output reg        RDY_OUT

                    ,   input wire BAUD_PULSE_IN

                    , output reg TX_OUT
                    );



localparam STATE_RESET = 8;


localparam STATE_IDLE = 9;


localparam STATE_START = 10;


localparam STATE_STOP = 11;


localparam STATE_BIT0 = 0;
localparam STATE_BIT1 = 1;
localparam STATE_BIT2 = 2;
localparam STATE_BIT3 = 3;
localparam STATE_BIT4 = 4;
localparam STATE_BIT5 = 5;
localparam STATE_BIT6 = 6;
localparam STATE_BIT7 = 7;


reg [3:0] state_i;


reg [7:0] data_i;





always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		state_i <= STATE_RESET;
	else
		if (state_i == STATE_RESET)
			state_i <= STATE_IDLE;
		else if (BAUD_PULSE_IN)
			case (state_i)
				STATE_IDLE: if (!RDY_OUT||VLD_IN) state_i <= STATE_START;
				STATE_START:                      state_i <= STATE_BIT0;
				STATE_BIT0:                       state_i <= STATE_BIT1;
				STATE_BIT1:                       state_i <= STATE_BIT2;
				STATE_BIT2:                       state_i <= STATE_BIT3;
				STATE_BIT3:                       state_i <= STATE_BIT4;
				STATE_BIT4:                       state_i <= STATE_BIT5;
				STATE_BIT5:                       state_i <= STATE_BIT6;
				STATE_BIT6:                       state_i <= STATE_BIT7;
				STATE_BIT7:                       state_i <= STATE_STOP;
				STATE_STOP: if (!RDY_OUT||VLD_IN) state_i <= STATE_START;
				            else                  state_i <= STATE_IDLE;
				
				default:
					state_i <= STATE_RESET;
			endcase








always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		RDY_OUT <= 1'b0;
	else
		if (RDY_OUT && VLD_IN)
			RDY_OUT <= 1'b0;
		else if (state_i == STATE_RESET)
			RDY_OUT <= 1'b1;
		else if (state_i == STATE_BIT7 && BAUD_PULSE_IN)
			RDY_OUT <= 1'b1;






always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		data_i <= 8'hXX;
	else
		if (RDY_OUT && VLD_IN)
			data_i <= DATA_IN;
		else if (BAUD_PULSE_IN
		        && (  state_i == STATE_BIT0 || state_i == STATE_BIT1
		           || state_i == STATE_BIT2 || state_i == STATE_BIT3
		           || state_i == STATE_BIT4 || state_i == STATE_BIT5
		           || state_i == STATE_BIT6 || state_i == STATE_BIT7
		           )
		        )
			data_i <= {1'bX, data_i[7:1]};






always @ (*)
	if (RESET_IN)
		TX_OUT = `LINE_IDLE;
	else
		case (state_i)
			default:
				TX_OUT = `LINE_IDLE;
			
			STATE_RESET,
			STATE_IDLE:
				TX_OUT = `LINE_IDLE;
			
			STATE_START:
				TX_OUT = `START_BIT;
			
			STATE_BIT0, STATE_BIT1, STATE_BIT2, STATE_BIT3,
			STATE_BIT4, STATE_BIT5, STATE_BIT6, STATE_BIT7:
				TX_OUT = data_i[0];
			
			STATE_STOP:
				TX_OUT = `STOP_BIT;
		endcase


endmodule