data/full_repos/permissive/160895047/Memory.v
data/verilator_xmls/3b962b59-d7c0-4b6e-8538-ece4440fab48.xml
module Memory(
	CLOCK,
	A,
	D,
	WE,
	WD
);
input CLOCK;
input [31:0] A;
output [31:0] D;
input WE;
input [31:0] WD;

wire CLOCK;
wire [31:0] A;
reg [31:0] D;
wire WE;
wire [31:0] WD;

reg [31:0] MEM[65535:0];

always @ (negedge CLOCK) 
begin
	if (WE)
		MEM[A] <= WD;
	D <= MEM[A];
end
endmodule
module Memory(
	CLOCK,
	A,
	D,
	WE,
	WD
);

input CLOCK;
input [31:0] A;
output [31:0] D;
input WE;
input [31:0] WD;

wire CLOCK;
wire [31:0] A;
reg [31:0] D;
wire WE;
wire [31:0] WD;

reg [31:0] MEM[65535:0];

always @ (negedge CLOCK) 
begin
	if (WE)
		MEM[A] <= WD;
	D <= MEM[A];
end
endmodule