data/full_repos/permissive/157005262/verilog/counter_tb.v
 line:32: before: "$"
1: b'%Error: data/full_repos/permissive/157005262/verilog/counter_tb.v:1: Cannot find include file: counter.v\n`include "counter.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/counter.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/counter.v.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/counter.v.sv\n             counter.v\n             counter.v.v\n             counter.v.sv\n             obj_dir/counter.v\n             obj_dir/counter.v.v\n             obj_dir/counter.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/counter_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    forever #1 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/157005262/verilog/counter_tb.v:16: Unsupported or unknown PLI call: $monitor\n      $monitor($time, " clk = %b, en = %b, rst = %b, count = %b",\n      ^~~~~~~~\n%Error: data/full_repos/permissive/157005262/verilog/counter_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile(`VCD_FILE);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/157005262/verilog/counter_tb.v:18: Define or directive not defined: \'`VCD_FILE\'\n      $dumpfile(`VCD_FILE);\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/157005262/verilog/counter_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/counter_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #2 en <= 0; rst <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/counter_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #2 en <= 0; rst <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/counter_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #2 en <= 1; rst <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/counter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #4 en <= 1; rst <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/counter_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #2 en <= 1; rst <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/counter_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #10 en <= 0; rst <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/counter_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #4 $finish;\n      ^\n%Error: Exiting due to 5 error(s), 8 warning(s)\n'
module Top;
  reg clk = 1;
  reg en = 0;
  reg rst = 0;
  wire [3:0] count;

  counter c(clk, en, rst, count);

  initial
    forever #1 clk = ~clk;

  initial
    begin
      $monitor($time, " clk = %b, en = %b, rst = %b, count = %b",
               clk, en, rst, count);
      $dumpfile(`VCD_FILE);
      $dumpvars;

      #2 en <= 0; rst <= 1;
      #2 en <= 0; rst <= 0;
      #2 en <= 1; rst <= 0;
      #4 en <= 1; rst <= 1;
      #2 en <= 1; rst <= 0;
      #10 en <= 0; rst <= 0;
      #4 $finish;
    end
endmodule
module Top;

  reg clk = 1;
  reg en = 0;
  reg rst = 0;
  wire [3:0] count;

  counter c(clk, en, rst, count);

  initial
    forever #1 clk = ~clk;

  initial
    begin
      $monitor($time, " clk = %b, en = %b, rst = %b, count = %b",
               clk, en, rst, count);
      $dumpfile(`VCD_FILE);
      $dumpvars;

      #2 en <= 0; rst <= 1;
      #2 en <= 0; rst <= 0;
      #2 en <= 1; rst <= 0;
      #4 en <= 1; rst <= 1;
      #2 en <= 1; rst <= 0;
      #10 en <= 0; rst <= 0;
      #4 $finish;
    end
endmodule