data/full_repos/permissive/129127690/parametrizable_slt.v
data/verilator_xmls/9a3b75ae-3aba-4abf-9ecf-75b6be4a93dd.xml
module parametrizable_slt #(parameter bus_size = 32) (
	input [bus_size-1:0] 	a,b,
	output [bus_size-1:0] out);

	assign out[0] = a<b;

	genvar i;
	generate 
		for (i = 1; i < bus_size; i = i+1) begin:forloop
			assign out[i] = 0;
		end
	
	endgenerate

endmodule
module parametrizable_slt #(parameter bus_size = 32) (
	input [bus_size-1:0] 	a,b,
	output [bus_size-1:0] out);


	assign out[0] = a<b;

	genvar i;
	generate 
		for (i = 1; i < bus_size; i = i+1) begin:forloop
			assign out[i] = 0;
		end
	
	endgenerate

endmodule