data/full_repos/permissive/174263347/scanconv/designer/scanconv.v
1: b"%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:328: Cannot find file containing module: 'DFC1B'\n    DFC1B riseZ0Z_1 (.D(rise[0]), .CLK(clk_c), .CLR(nReset_c), .Q(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/174263347/scanconv/designer,data/full_repos/permissive/174263347/DFC1B\n             data/full_repos/permissive/174263347/scanconv/designer,data/full_repos/permissive/174263347/DFC1B.v\n             data/full_repos/permissive/174263347/scanconv/designer,data/full_repos/permissive/174263347/DFC1B.sv\n             DFC1B\n             DFC1B.v\n             DFC1B.sv\n             obj_dir/DFC1B\n             obj_dir/DFC1B.v\n             obj_dir/DFC1B.sv\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:330: Cannot find file containing module: 'DFC1B'\n    DFC1B riseZ0Z_0 (.D(vsync_c), .CLK(clk_c), .CLR(nReset_c), .Q(\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:313: Cannot find file containing module: 'OR2A'\n    OR2A out_0 (.A(riseZ0Z_1), .B(riseZ0Z_0), .Y(hsync_0));\n    ^~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:314: Cannot find file containing module: 'DFC1B'\n    DFC1B rise_1 (.D(riseZ0Z_0), .CLK(clk_c), .CLR(nReset_c), .Q(\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:316: Cannot find file containing module: 'DFC1B'\n    DFC1B rise_0 (.D(hsync_c), .CLK(clk_c), .CLR(nReset_c), .Q(\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:318: Cannot find file containing module: 'OR2A'\n    OR2A out (.A(riseZ0Z_1), .B(riseZ0Z_0), .Y(hsync));\n    ^~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:367: Cannot find file containing module: 'DFE3C'\n    DFE3C v_5 (.D(y_33), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:369: Cannot find file containing module: 'DFE3C'\n    DFE3C nline_2 (.D(y_47), .CLK(clk_c), .CLR(nReset_c), .E(\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:371: Cannot find file containing module: 'DFE1B'\n    DFE1B h_2 (.D(y_35), .CLK(clk_c), .E(y_42), .Q(aVga[2]));\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:374: Cannot find file containing module: 'CM8INV'\n    CM8INV G_308_cm8i (.A(aVga[11]), .Y(G_308_cm8iZ0));\n    ^~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:375: Cannot find file containing module: 'CM8'\n    CM8 G_16_i_0 (.D0(GNDZ0), .D1(VCCZ0), .D2(GNDZ0), .D3(N_372_1), \n    ^~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:378: Cannot find file containing module: 'CM8'\n    CM8 pixel_n3_0_xor2 (.D0(GNDZ0), .D1(pixelZ0Z_0), .D2(VCCZ0), .D3(\n    ^~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:381: Cannot find file containing module: 'DFC1B'\n    DFC1B pixel_3 (.D(pixel_n3), .CLK(clk_c), .CLR(hsync), .Q(\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:383: Cannot find file containing module: 'CM8INV'\n    CM8INV v_n5_0_xor2_i_cm8i (.A(aVga[11]), .Y(v_n5_0_xor2_i_cm8iZ0));\n    ^~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:384: Cannot find file containing module: 'DFE4F'\n    DFE4F hdelay_2 (.D(N_377), .CLK(clk_c), .PRE(nReset_c), .E(y_38), \n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:386: Cannot find file containing module: 'AND2'\n    AND2 un1_hsync_3_i_0_and2_209 (.A(aVga[13]), .B(aVga[10]), .Y(y_5));\n    ^~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:387: Cannot find file containing module: 'CM8'\n    CM8 h_l5_i_0 (.D0(hsync), .D1(GNDZ0), .D2(GNDZ0), .D3(hsync), .S00(\n    ^~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:390: Cannot find file containing module: 'CM8'\n    CM8 G_55_i_and2_0_and2 (.D0(VCCZ0), .D1(N_221_n), .D2(VCCZ0), .D3(\n    ^~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:393: Cannot find file containing module: 'CM8INV'\n    CM8INV un1_un1_un1_hsync_1_i_0_0_cm8i (.A(vdelayZ0Z_3), .Y(\n    ^~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:395: Cannot find file containing module: 'DFC1B'\n    DFC1B pixel8 (.D(pixel8_3), .CLK(clk_c), .CLR(hsync), .Q(pixelZ0Z8)\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:397: Cannot find file containing module: 'CM8INV'\n    CM8INV pixel_n2_0_xor2_cm8i (.A(pixelZ0Z_1), .Y(\n    ^~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:399: Cannot find file containing module: 'XNOR2'\n    XNOR2 G_200_0 (.A(y_51), .B(aVga[11]), .Y(y_36));\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:400: Cannot find file containing module: 'AND3'\n    AND3 wrVga_0_and2_0_and2 (.A(pixelZ0Z8), .B(lineZ0), .C(frameZ0), \n    ^~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:402: Cannot find file containing module: 'CM8INV'\n    CM8INV v_n2_0_xor2_i_cm8i (.A(aVga[8]), .Y(v_n2_0_xor2_i_cm8iZ0));\n    ^~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:403: Cannot find file containing module: 'DFE1B'\n    DFE1B h_6 (.D(N_165), .CLK(clk_c), .E(y_42), .Q(aVga[6]));\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:404: Cannot find file containing module: 'CM8'\n    CM8 G_10_i_0 (.D0(N_114_0), .D1(un1_hsync_2_i), .D2(un1_hsync_2_i), \n    ^~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:407: Cannot find file containing module: 'CM8'\n    CM8 vdelay_l1_0_and2_0_and2 (.D0(N_114_0), .D1(GNDZ0), .D2(GNDZ0), \n    ^~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:410: Cannot find file containing module: 'OR2A'\n    OR2A G_95_0 (.A(rise_1), .B(rise_0), .Y(N_114_0));\n    ^~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:411: Cannot find file containing module: 'OR2A'\n    OR2A G_95 (.A(rise_1), .B(rise_0), .Y(y_45));\n    ^~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:412: Cannot find file containing module: 'OR2B'\n    OR2B G_55_i_and2_0_and2_192_n (.A(aVga[12]), .B(aVga[13]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:414: Cannot find file containing module: 'XOR2'\n    XOR2 G_114 (.A(pixelZ0Z_0), .B(pixelZ0Z_1), .Y(y_44));\n    ^~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:417: Cannot find file containing module: 'DFE3C'\n    DFE3C v_3 (.D(y_30), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:419: Cannot find file containing module: 'AND2'\n    AND2 line_8_0_and2_i (.A(hsync_0), .B(nlineZ0Z_0), .Y(y_31));\n    ^~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:420: Cannot find file containing module: 'CM8INV'\n    CM8INV hdelay_l2_i_and2_0_and2_cm8i (.A(hsync_0), .Y(\n    ^~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:422: Cannot find file containing module: 'OR2B'\n    OR2B vdelay_l0_i_and2_0_and2 (.A(vdelayZ0Z_0), .B(N_114_0), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:424: Cannot find file containing module: 'CM8INV'\n    CM8INV nline_9_i_0_cm8i_1 (.A(nlineZ0Z_1), .Y(\n    ^~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:426: Cannot find file containing module: 'CM8INV'\n    CM8INV h_l5_i_0_cm8i (.A(aVga[4]), .Y(h_l5_i_0_cm8iZ0));\n    ^~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:427: Cannot find file containing module: 'CM8INV'\n    CM8INV G_310_cm8i (.A(y_51), .Y(G_310_cm8iZ0));\n    ^~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:428: Cannot find file containing module: 'DFE3C'\n    DFE3C v_1 (.D(y_37), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(aVga[8])\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:430: Cannot find file containing module: 'VCC'\n    VCC VCC (.Y(VCCZ0));\n    ^~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:431: Cannot find file containing module: 'CM8'\n    CM8 h_l4_0_and3_0_and2 (.D0(hsync_0), .D1(GNDZ0), .D2(GNDZ0), .D3(\n    ^~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:434: Cannot find file containing module: 'CM8'\n    CM8 v_n5_0_xor2_i (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(VCCZ0), \n    ^~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:437: Cannot find file containing module: 'CM8'\n    CM8 hdelay_l2_i_and2_0_and2 (.D0(VCCZ0), .D1(\n    ^~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:441: Cannot find file containing module: 'DFE4F'\n    DFE4F nline_0 (.D(y_27), .CLK(clk_c), .PRE(nReset_c), .E(\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:443: Cannot find file containing module: 'DFE1B'\n    DFE1B h_3 (.D(h_l3), .CLK(clk_c), .E(y_42), .Q(aVga[3]));\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:444: Cannot find file containing module: 'DFE3C'\n    DFE3C v_6 (.D(y_34), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:446: Cannot find file containing module: 'DFE3C'\n    DFE3C v_2 (.D(y_32), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(aVga[9])\n    ^~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:448: Cannot find file containing module: 'CM8'\n    CM8 pixel_n2_0_xor2 (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(VCCZ0)\n    ^~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:451: Cannot find file containing module: 'CM8INV'\n    CM8INV nline_9_i_0_cm8i_2 (.A(nlineZ0Z_2), .Y(\n    ^~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/designer/scanconv.v:453: Cannot find file containing module: 'AND3C'\n    AND3C G_16_i_0_and2_0_1 (.A(hdelayZ0Z_0), .B(hdelayZ0Z_1), .C(\n    ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module vga(dVga, aVga, hsync_c, vsync_c, iVideo_c, nReset_c, relay_c, 
        clk_c, dirout_0, access, wrVga, wrVga_i);
output  [7:0] dVga;
output  [15:0] aVga;
input  hsync_c, vsync_c, iVideo_c, nReset_c;
output  relay_c;
input  clk_c, dirout_0, access;
output  wrVga, wrVga_i;

    wire N_372_1, N_347, N_114_0, N_327, N_326, N_221_n, N_330_n, 
        N_337, y_5, y_4, y, y_9, y_8, pixel8_3, pixelZ0Z8, y_43, y_26, 
        linesZ0Z350, y_31, y_40, lineZ0, y_49, frameZ0, pixel_n3, 
        pixelZ0Z_3, pixel_n2, pixelZ0Z_2, y_44, pixelZ0Z_1, 
        pixel_iZ0Z_0, pixelZ0Z_0, y_30, y_32, y_37, aVga_iZ0Z_7, y_33, 
        y_36, N_355, vdelayZ0Z_0, y_28, y_29, y_34, y_39, y_45, 
        vdelay_l2, vdelayZ0Z_2, vdelay_l1, vdelayZ0Z_1, N_293, N_357, 
        vdelayZ0Z_4, N_356, y_48, vdelayZ0Z_3, h_l3, y_35, h_l1, N_165, 
        y_41, h_l4, y_42, N_377, hdelayZ0Z_2, hdelay_l1, hdelayZ0Z_1, 
        N_376, y_38, hdelayZ0Z_0, y_47, nlineZ0Z_2, y_46, nlineZ0Z_1, 
        y_27, un1_hsync_2_i, nlineZ0Z_0, y_50, y_51, rise_0, rise_1, 
        hsync_0, hsync, VCCZ0, GNDZ0, G_67_i_0_cm8iZ0, 
        un1_hsync_3_i_0_cm8iZ0, G_55_i_and2_0_and2_cm8iZ0, 
        h_l5_i_0_cm8iZ0, un1_un1_un1_hsync_1_i_0_0_cm8iZ0, 
        nline_9_i_0_cm8iZ0Z_2, nline_9_i_0_cm8iZ0Z_1, G_13_i_0_cm8iZ0, 
        v_n6_0_xor2_i_cm8iZ0, v_n5_0_xor2_i_cm8iZ0, 
        v_n2_0_xor2_i_cm8iZ0, G_308_cm8iZ0, G_310_cm8iZ0, 
        nline_9_1_i_and2_cm8iZ0Z_0, hdelay_l2_i_and2_0_and2_cm8iZ0, 
        h_l3_0_and3_0_and2_cm8iZ0, G_311_cm8iZ0, 
        vdelay_l4_i_and2_0_and2_cm8iZ0, vdelay_l3_i_and2_0_and2_cm8iZ0, 
        pixel_n2_0_xor2_cm8iZ0;
    
    DFE3C v_5 (.D(y_33), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[12]));
    DFE3C nline_2 (.D(y_47), .CLK(clk_c), .CLR(nReset_c), .E(
        un1_hsync_2_i), .Q(nlineZ0Z_2));
    DFE1B h_2 (.D(y_35), .CLK(clk_c), .E(y_42), .Q(aVga[2]));
    myFAILINGEX_1 hFrontExt (.hsync_c(hsync_c), .nReset_c(nReset_c), 
        .clk_c(clk_c), .hsync_0(hsync_0), .hsync(hsync));
    CM8INV G_308_cm8i (.A(aVga[11]), .Y(G_308_cm8iZ0));
    CM8 G_16_i_0 (.D0(GNDZ0), .D1(VCCZ0), .D2(GNDZ0), .D3(N_372_1), 
        .S00(hsync_0), .S01(VCCZ0), .S10(pixelZ0Z8), .S11(GNDZ0), .Y(
        y_38));
    CM8 pixel_n3_0_xor2 (.D0(GNDZ0), .D1(pixelZ0Z_0), .D2(VCCZ0), .D3(
        pixel_iZ0Z_0), .S00(pixelZ0Z_1), .S01(pixelZ0Z_2), .S10(
        pixelZ0Z_3), .S11(GNDZ0), .Y(pixel_n3));
    DFC1B pixel_3 (.D(pixel_n3), .CLK(clk_c), .CLR(hsync), .Q(
        pixelZ0Z_3));
    CM8INV v_n5_0_xor2_i_cm8i (.A(aVga[11]), .Y(v_n5_0_xor2_i_cm8iZ0));
    DFE4F hdelay_2 (.D(N_377), .CLK(clk_c), .PRE(nReset_c), .E(y_38), 
        .Q(hdelayZ0Z_2));
    AND2 un1_hsync_3_i_0_and2_209 (.A(aVga[13]), .B(aVga[10]), .Y(y_5));
    CM8 h_l5_i_0 (.D0(hsync), .D1(GNDZ0), .D2(GNDZ0), .D3(hsync), .S00(
        aVga[5]), .S01(VCCZ0), .S10(h_l5_i_0_cm8iZ0), .S11(N_326), .Y(
        y_41));
    CM8 G_55_i_and2_0_and2 (.D0(VCCZ0), .D1(N_221_n), .D2(VCCZ0), .D3(
        VCCZ0), .S00(aVga[14]), .S01(aVga[11]), .S10(
        G_55_i_and2_0_and2_cm8iZ0), .S11(N_330_n), .Y(y_26));
    CM8INV un1_un1_un1_hsync_1_i_0_0_cm8i (.A(vdelayZ0Z_3), .Y(
        un1_un1_un1_hsync_1_i_0_0_cm8iZ0));
    DFC1B pixel8 (.D(pixel8_3), .CLK(clk_c), .CLR(hsync), .Q(pixelZ0Z8)
        );
    CM8INV pixel_n2_0_xor2_cm8i (.A(pixelZ0Z_1), .Y(
        pixel_n2_0_xor2_cm8iZ0));
    XNOR2 G_200_0 (.A(y_51), .B(aVga[11]), .Y(y_36));
    AND3 wrVga_0_and2_0_and2 (.A(pixelZ0Z8), .B(lineZ0), .C(frameZ0), 
        .Y(wrVga));
    CM8INV v_n2_0_xor2_i_cm8i (.A(aVga[8]), .Y(v_n2_0_xor2_i_cm8iZ0));
    DFE1B h_6 (.D(N_165), .CLK(clk_c), .E(y_42), .Q(aVga[6]));
    CM8 G_10_i_0 (.D0(N_114_0), .D1(un1_hsync_2_i), .D2(un1_hsync_2_i), 
        .D3(un1_hsync_2_i), .S00(N_327), .S01(VCCZ0), .S10(vdelayZ0Z_3)
        , .S11(vdelayZ0Z_4), .Y(y_48));
    CM8 vdelay_l1_0_and2_0_and2 (.D0(N_114_0), .D1(GNDZ0), .D2(GNDZ0), 
        .D3(N_114_0), .S00(vdelayZ0Z_0), .S01(VCCZ0), .S10(vdelayZ0Z_1)
        , .S11(GNDZ0), .Y(vdelay_l1));
    OR2A G_95_0 (.A(rise_1), .B(rise_0), .Y(N_114_0));
    OR2A G_95 (.A(rise_1), .B(rise_0), .Y(y_45));
    OR2B G_55_i_and2_0_and2_192_n (.A(aVga[12]), .B(aVga[13]), .Y(
        N_221_n));
    XOR2 G_114 (.A(pixelZ0Z_0), .B(pixelZ0Z_1), .Y(y_44));
    myFAILINGEX vFrontExt (.rise({rise_1, rise_0}), .vsync_c(vsync_c), 
        .nReset_c(nReset_c), .clk_c(clk_c));
    DFE3C v_3 (.D(y_30), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[10]));
    AND2 line_8_0_and2_i (.A(hsync_0), .B(nlineZ0Z_0), .Y(y_31));
    CM8INV hdelay_l2_i_and2_0_and2_cm8i (.A(hsync_0), .Y(
        hdelay_l2_i_and2_0_and2_cm8iZ0));
    OR2B vdelay_l0_i_and2_0_and2 (.A(vdelayZ0Z_0), .B(N_114_0), .Y(
        N_355));
    CM8INV nline_9_i_0_cm8i_1 (.A(nlineZ0Z_1), .Y(
        nline_9_i_0_cm8iZ0Z_1));
    CM8INV h_l5_i_0_cm8i (.A(aVga[4]), .Y(h_l5_i_0_cm8iZ0));
    CM8INV G_310_cm8i (.A(y_51), .Y(G_310_cm8iZ0));
    DFE3C v_1 (.D(y_37), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(aVga[8])
        );
    VCC VCC (.Y(VCCZ0));
    CM8 h_l4_0_and3_0_and2 (.D0(hsync_0), .D1(GNDZ0), .D2(GNDZ0), .D3(
        hsync_0), .S00(N_326), .S01(VCCZ0), .S10(aVga[4]), .S11(GNDZ0), 
        .Y(h_l4));
    CM8 v_n5_0_xor2_i (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(VCCZ0), 
        .S00(aVga[12]), .S01(VCCZ0), .S10(v_n5_0_xor2_i_cm8iZ0), .S11(
        y_51), .Y(y_33));
    CM8 hdelay_l2_i_and2_0_and2 (.D0(VCCZ0), .D1(
        hdelay_l2_i_and2_0_and2_cm8iZ0), .D2(
        hdelay_l2_i_and2_0_and2_cm8iZ0), .D3(VCCZ0), .S00(hdelayZ0Z_2), 
        .S01(VCCZ0), .S10(hdelayZ0Z_1), .S11(hdelayZ0Z_0), .Y(N_377));
    DFE4F nline_0 (.D(y_27), .CLK(clk_c), .PRE(nReset_c), .E(
        un1_hsync_2_i), .Q(nlineZ0Z_0));
    DFE1B h_3 (.D(h_l3), .CLK(clk_c), .E(y_42), .Q(aVga[3]));
    DFE3C v_6 (.D(y_34), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[13]));
    DFE3C v_2 (.D(y_32), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(aVga[9])
        );
    CM8 pixel_n2_0_xor2 (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(VCCZ0)
        , .S00(pixelZ0Z_2), .S01(VCCZ0), .S10(pixel_n2_0_xor2_cm8iZ0), 
        .S11(pixel_iZ0Z_0), .Y(pixel_n2));
    CM8INV nline_9_i_0_cm8i_2 (.A(nlineZ0Z_2), .Y(
        nline_9_i_0_cm8iZ0Z_2));
    AND3C G_16_i_0_and2_0_1 (.A(hdelayZ0Z_0), .B(hdelayZ0Z_1), .C(
        hdelayZ0Z_2), .Y(N_372_1));
    CM8 pixel_i_0 (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(GNDZ0), 
        .S00(pixelZ0Z_0), .S01(VCCZ0), .S10(GNDZ0), .S11(GNDZ0), .Y(
        pixel_iZ0Z_0));
    CM8 v_n2_0_xor2_i (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(VCCZ0), 
        .S00(aVga[9]), .S01(VCCZ0), .S10(v_n2_0_xor2_i_cm8iZ0), .S11(
        aVga_iZ0Z_7), .Y(y_32));
    CM8INV vdelay_l4_i_and2_0_and2_cm8i (.A(N_114_0), .Y(
        vdelay_l4_i_and2_0_and2_cm8iZ0));
    CM8 nline_9_i_0_1 (.D0(GNDZ0), .D1(nline_9_i_0_cm8iZ0Z_1), .D2(
        GNDZ0), .D3(nlineZ0Z_0), .S00(N_114_0), .S01(VCCZ0), .S10(
        linesZ0Z350), .S11(GNDZ0), .Y(y_46));
    CM8 vdelay_l4_i_and2_0_and2 (.D0(VCCZ0), .D1(
        vdelay_l4_i_and2_0_and2_cm8iZ0), .D2(
        vdelay_l4_i_and2_0_and2_cm8iZ0), .D3(VCCZ0), .S00(vdelayZ0Z_4), 
        .S01(VCCZ0), .S10(vdelayZ0Z_3), .S11(N_327), .Y(N_357));
    DFE4F hdelay_0 (.D(N_376), .CLK(clk_c), .PRE(nReset_c), .E(y_38), 
        .Q(hdelayZ0Z_0));
    CM8 G_67_i_0_195 (.D0(VCCZ0), .D1(VCCZ0), .D2(VCCZ0), .D3(GNDZ0), 
        .S00(aVga[6]), .S01(VCCZ0), .S10(aVga[4]), .S11(aVga[5]), .Y(
        y_8));
    CM8 nline_9_1_i_and2_0 (.D0(VCCZ0), .D1(nline_9_1_i_and2_cm8iZ0Z_0)
        , .D2(VCCZ0), .D3(nlineZ0Z_2), .S00(N_114_0), .S01(VCCZ0), 
        .S10(linesZ0Z350), .S11(GNDZ0), .Y(y_27));
    AND2B G_67_i_0_and2_0_188 (.A(aVga[2]), .B(aVga[3]), .Y(y_9));
    AND4A pixel8_3_0_and2 (.A(pixelZ0Z_3), .B(pixelZ0Z_2), .C(
        pixel_iZ0Z_0), .D(pixelZ0Z_1), .Y(pixel8_3));
    DF1 dVgaZ0Z_7 (.D(dVga[6]), .CLK(clk_c), .Q(dVga[7]));
    DFE4F vdelay_3 (.D(N_356), .CLK(clk_c), .PRE(nReset_c), .E(y_48), 
        .Q(vdelayZ0Z_3));
    CM8 G_308 (.D0(aVga[11]), .D1(G_308_cm8iZ0), .D2(GNDZ0), .D3(VCCZ0)
        , .S00(aVga[14]), .S01(VCCZ0), .S10(N_221_n), .S11(y_51), .Y(
        y_29));
    DF1 dVgaZ0Z_4 (.D(dVga[3]), .CLK(clk_c), .Q(dVga[4]));
    DFE3C vdelay_2 (.D(vdelay_l2), .CLK(clk_c), .CLR(nReset_c), .E(
        y_48), .Q(vdelayZ0Z_2));
    CM8 h_l2_0_and3_i (.D0(GNDZ0), .D1(hsync), .D2(hsync), .D3(GNDZ0), 
        .S00(aVga[1]), .S01(aVga[0]), .S10(aVga[2]), .S11(GNDZ0), .Y(
        y_35));
    CM8INV G_311_cm8i (.A(N_326), .Y(G_311_cm8iZ0));
    CM8 G_67_i_0 (.D0(y_8), .D1(VCCZ0), .D2(y_8), .D3(y_8), .S00(
        G_67_i_0_cm8iZ0), .S01(y_9), .S10(aVga[0]), .S11(aVga[5]), .Y(
        y_43));
    DFE3C hdelay_1 (.D(hdelay_l1), .CLK(clk_c), .CLR(nReset_c), .E(
        y_38), .Q(hdelayZ0Z_1));
    DFC1B pixel_1 (.D(y_44), .CLK(clk_c), .CLR(hsync), .Q(pixelZ0Z_1));
    DFC1B pixel_0 (.D(pixel_iZ0Z_0), .CLK(clk_c), .CLR(hsync), .Q(
        pixelZ0Z_0));
    OR3B G_301 (.A(aVga[8]), .B(aVga[9]), .C(aVga_iZ0Z_7), .Y(N_337));
    GND GND (.Y(GNDZ0));
    CM8 v_n6_0_xor2_i (.D0(aVga[12]), .D1(N_221_n), .D2(GNDZ0), .D3(
        VCCZ0), .S00(aVga[13]), .S01(VCCZ0), .S10(v_n6_0_xor2_i_cm8iZ0)
        , .S11(y_51), .Y(y_34));
    CM8 un1_hsync_3_i_0 (.D0(GNDZ0), .D1(un1_hsync_3_i_0_cm8iZ0), .D2(
        VCCZ0), .D3(VCCZ0), .S00(y_5), .S01(y_4), .S10(y), .S11(hsync), 
        .Y(y_39));
    OR3C wrVga_iZ0 (.A(lineZ0), .B(frameZ0), .C(pixelZ0Z8), .Y(wrVga_i)
        );
    CM8 G_13_i_0 (.D0(hsync_0), .D1(hsync_0), .D2(hsync_0), .D3(GNDZ0), 
        .S00(access), .S01(dirout_0), .S10(G_13_i_0_cm8iZ0), .S11(
        N_347), .Y(y_42));
    DF1 dVgaZ0Z_3 (.D(dVga[2]), .CLK(clk_c), .Q(dVga[3]));
    DFE1B h_4 (.D(h_l4), .CLK(clk_c), .E(y_42), .Q(aVga[4]));
    CM8 hdelay_l1_0_and2_0_and2 (.D0(hsync_0), .D1(GNDZ0), .D2(GNDZ0), 
        .D3(hsync_0), .S00(hdelayZ0Z_0), .S01(VCCZ0), .S10(hdelayZ0Z_1)
        , .S11(GNDZ0), .Y(hdelay_l1));
    CM8INV un1_hsync_3_i_0_cm8i (.A(N_337), .Y(un1_hsync_3_i_0_cm8iZ0));
    CM8 G_305 (.D0(GNDZ0), .D1(aVga[7]), .D2(VCCZ0), .D3(aVga_iZ0Z_7), 
        .S00(aVga[8]), .S01(aVga[9]), .S10(aVga[10]), .S11(GNDZ0), .Y(
        y_30));
    OR4D G_290 (.A(aVga[1]), .B(aVga[3]), .C(aVga[0]), .D(aVga[2]), .Y(
        N_326));
    DFC1B pixel_2 (.D(pixel_n2), .CLK(clk_c), .CLR(hsync), .Q(
        pixelZ0Z_2));
    DF1 dVgaZ0Z_5 (.D(dVga[4]), .CLK(clk_c), .Q(dVga[5]));
    AND2 G_10_i_0_and2 (.A(hsync_0), .B(N_114_0), .Y(un1_hsync_2_i));
    AND4 v_ca7 (.A(aVga[11]), .B(aVga[12]), .C(aVga[13]), .D(aVga[14]), 
        .Y(y_50));
    OR2A un1_hsync_3_i_0_236 (.A(frameZ0), .B(nlineZ0Z_0), .Y(y));
    DFE3C nline_1 (.D(y_46), .CLK(clk_c), .CLR(nReset_c), .E(
        un1_hsync_2_i), .Q(nlineZ0Z_1));
    CM8INV nline_9_1_i_and2_cm8i_0 (.A(nlineZ0Z_0), .Y(
        nline_9_1_i_and2_cm8iZ0Z_0));
    DF1 dVgaZ0Z_2 (.D(dVga[1]), .CLK(clk_c), .Q(dVga[2]));
    DFE1B h_1 (.D(h_l1), .CLK(clk_c), .E(y_42), .Q(aVga[1]));
    DFE3C frame (.D(y_45), .CLK(clk_c), .CLR(nReset_c), .E(y_49), .Q(
        frameZ0));
    DFE3C v_0 (.D(aVga_iZ0Z_7), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[7]));
    CM8 nline_9_i_0_2 (.D0(GNDZ0), .D1(nline_9_i_0_cm8iZ0Z_2), .D2(
        GNDZ0), .D3(nlineZ0Z_1), .S00(N_114_0), .S01(VCCZ0), .S10(
        linesZ0Z350), .S11(GNDZ0), .Y(y_47));
    DFE3C line (.D(y_31), .CLK(clk_c), .CLR(nReset_c), .E(y_40), .Q(
        lineZ0));
    XA1 h_l1_0_and3_0_and2 (.A(aVga[0]), .B(aVga[1]), .C(hsync_0), .Y(
        h_l1));
    CM8 G_311 (.D0(GNDZ0), .D1(G_311_cm8iZ0), .D2(VCCZ0), .D3(N_326), 
        .S00(aVga[4]), .S01(aVga[5]), .S10(aVga[6]), .S11(GNDZ0), .Y(
        N_347));
    AND2A h_l0_0_and3_i (.A(aVga[0]), .B(hsync_0), .Y(N_293));
    DF1 dVgaZ0Z_1 (.D(dVga[0]), .CLK(clk_c), .Q(dVga[1]));
    DFE3C v_4 (.D(y_36), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[11]));
    CM8INV h_l3_0_and3_0_and2_cm8i (.A(hsync_0), .Y(
        h_l3_0_and3_0_and2_cm8iZ0));
    CM8 G_310 (.D0(GNDZ0), .D1(VCCZ0), .D2(VCCZ0), .D3(GNDZ0), .S00(
        G_310_cm8iZ0), .S01(y_50), .S10(aVga[15]), .S11(GNDZ0), .Y(
        y_28));
    DFE4F vdelay_0 (.D(N_355), .CLK(clk_c), .PRE(nReset_c), .E(y_48), 
        .Q(vdelayZ0Z_0));
    AND2 h_l6_i_0 (.A(hsync_0), .B(N_347), .Y(N_165));
    OR3 G_291 (.A(vdelayZ0Z_0), .B(vdelayZ0Z_2), .C(vdelayZ0Z_1), .Y(
        N_327));
    CM8INV G_13_i_0_cm8i (.A(aVga[6]), .Y(G_13_i_0_cm8iZ0));
    CM8INV v_n6_0_xor2_i_cm8i (.A(aVga[11]), .Y(v_n6_0_xor2_i_cm8iZ0));
    CM8INV G_55_i_and2_0_and2_cm8i (.A(aVga[15]), .Y(
        G_55_i_and2_0_and2_cm8iZ0));
    DFE3C v_7 (.D(y_29), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[14]));
    DFE1B notVga (.D(y_43), .CLK(clk_c), .E(hsync), .Q(relay_c));
    DFE1B lines350 (.D(y_26), .CLK(clk_c), .E(hsync), .Q(linesZ0Z350));
    DF1 dVgaZ0Z_0 (.D(iVideo_c), .CLK(clk_c), .Q(dVga[0]));
    DFE3C vdelay_1 (.D(vdelay_l1), .CLK(clk_c), .CLR(nReset_c), .E(
        y_48), .Q(vdelayZ0Z_1));
    AND2B G_294_n (.A(aVga[9]), .B(aVga[10]), .Y(N_330_n));
    DFE4F vdelay_4 (.D(N_357), .CLK(clk_c), .PRE(nReset_c), .E(y_48), 
        .Q(vdelayZ0Z_4));
    CM8INV vdelay_l3_i_and2_0_and2_cm8i (.A(N_114_0), .Y(
        vdelay_l3_i_and2_0_and2_cm8iZ0));
    XNOR2 G_199_0 (.A(aVga_iZ0Z_7), .B(aVga[8]), .Y(y_37));
    DFE3C v_8 (.D(y_28), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[15]));
    CM8 h_l3_0_and3_0_and2 (.D0(aVga[3]), .D1(N_326), .D2(GNDZ0), .D3(
        GNDZ0), .S00(aVga[1]), .S01(aVga[0]), .S10(y_9), .S11(
        h_l3_0_and3_0_and2_cm8iZ0), .Y(h_l3));
    OR2B hdelay_l0_i_and2_0_and2 (.A(hdelayZ0Z_0), .B(hsync_0), .Y(
        N_376));
    DF1 dVgaZ0Z_6 (.D(dVga[5]), .CLK(clk_c), .Q(dVga[6]));
    CM8 aVga_i_7 (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(GNDZ0), .S00(
        aVga[7]), .S01(VCCZ0), .S10(GNDZ0), .S11(GNDZ0), .Y(
        aVga_iZ0Z_7));
    NAND4 v_ca3 (.A(aVga[7]), .B(aVga[8]), .C(aVga[9]), .D(aVga[10]), 
        .Y(y_51));
    DFE1B h_0 (.D(N_293), .CLK(clk_c), .E(y_42), .Q(aVga[0]));
    DFE1B h_5 (.D(y_41), .CLK(clk_c), .E(y_42), .Q(aVga[5]));
    CM8 un1_un1_un1_hsync_i_0_0 (.D0(hsync_0), .D1(GNDZ0), .D2(GNDZ0), 
        .D3(GNDZ0), .S00(pixelZ0Z8), .S01(N_372_1), .S10(GNDZ0), .S11(
        GNDZ0), .Y(y_40));
    CM8INV G_67_i_0_cm8i (.A(aVga[1]), .Y(G_67_i_0_cm8iZ0));
    CM8 un1_un1_un1_hsync_1_i_0_0 (.D0(N_114_0), .D1(hsync), .D2(
        N_114_0), .D3(VCCZ0), .S00(un1_un1_un1_hsync_1_i_0_0_cm8iZ0), 
        .S01(N_114_0), .S10(vdelayZ0Z_4), .S11(N_327), .Y(y_49));
    AND4 un1_hsync_3_i_0_and2_211 (.A(aVga[11]), .B(aVga[14]), .C(
        aVga[12]), .D(aVga[15]), .Y(y_4));
    CM8 vdelay_l2_0_and2_0_and2 (.D0(N_114_0), .D1(GNDZ0), .D2(GNDZ0), 
        .D3(N_114_0), .S00(vdelayZ0Z_2), .S01(VCCZ0), .S10(vdelayZ0Z_1)
        , .S11(vdelayZ0Z_0), .Y(vdelay_l2));
    CM8 vdelay_l3_i_and2_0_and2 (.D0(VCCZ0), .D1(
        vdelay_l3_i_and2_0_and2_cm8iZ0), .D2(
        vdelay_l3_i_and2_0_and2_cm8iZ0), .D3(VCCZ0), .S00(N_327), .S01(
        VCCZ0), .S10(vdelayZ0Z_3), .S11(GNDZ0), .Y(N_356));
    
endmodule
module vga(dVga, aVga, hsync_c, vsync_c, iVideo_c, nReset_c, relay_c, 
        clk_c, dirout_0, access, wrVga, wrVga_i);

output  [7:0] dVga;
output  [15:0] aVga;
input  hsync_c, vsync_c, iVideo_c, nReset_c;
output  relay_c;
input  clk_c, dirout_0, access;
output  wrVga, wrVga_i;

    wire N_372_1, N_347, N_114_0, N_327, N_326, N_221_n, N_330_n, 
        N_337, y_5, y_4, y, y_9, y_8, pixel8_3, pixelZ0Z8, y_43, y_26, 
        linesZ0Z350, y_31, y_40, lineZ0, y_49, frameZ0, pixel_n3, 
        pixelZ0Z_3, pixel_n2, pixelZ0Z_2, y_44, pixelZ0Z_1, 
        pixel_iZ0Z_0, pixelZ0Z_0, y_30, y_32, y_37, aVga_iZ0Z_7, y_33, 
        y_36, N_355, vdelayZ0Z_0, y_28, y_29, y_34, y_39, y_45, 
        vdelay_l2, vdelayZ0Z_2, vdelay_l1, vdelayZ0Z_1, N_293, N_357, 
        vdelayZ0Z_4, N_356, y_48, vdelayZ0Z_3, h_l3, y_35, h_l1, N_165, 
        y_41, h_l4, y_42, N_377, hdelayZ0Z_2, hdelay_l1, hdelayZ0Z_1, 
        N_376, y_38, hdelayZ0Z_0, y_47, nlineZ0Z_2, y_46, nlineZ0Z_1, 
        y_27, un1_hsync_2_i, nlineZ0Z_0, y_50, y_51, rise_0, rise_1, 
        hsync_0, hsync, VCCZ0, GNDZ0, G_67_i_0_cm8iZ0, 
        un1_hsync_3_i_0_cm8iZ0, G_55_i_and2_0_and2_cm8iZ0, 
        h_l5_i_0_cm8iZ0, un1_un1_un1_hsync_1_i_0_0_cm8iZ0, 
        nline_9_i_0_cm8iZ0Z_2, nline_9_i_0_cm8iZ0Z_1, G_13_i_0_cm8iZ0, 
        v_n6_0_xor2_i_cm8iZ0, v_n5_0_xor2_i_cm8iZ0, 
        v_n2_0_xor2_i_cm8iZ0, G_308_cm8iZ0, G_310_cm8iZ0, 
        nline_9_1_i_and2_cm8iZ0Z_0, hdelay_l2_i_and2_0_and2_cm8iZ0, 
        h_l3_0_and3_0_and2_cm8iZ0, G_311_cm8iZ0, 
        vdelay_l4_i_and2_0_and2_cm8iZ0, vdelay_l3_i_and2_0_and2_cm8iZ0, 
        pixel_n2_0_xor2_cm8iZ0;
    
    DFE3C v_5 (.D(y_33), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[12]));
    DFE3C nline_2 (.D(y_47), .CLK(clk_c), .CLR(nReset_c), .E(
        un1_hsync_2_i), .Q(nlineZ0Z_2));
    DFE1B h_2 (.D(y_35), .CLK(clk_c), .E(y_42), .Q(aVga[2]));
    myFAILINGEX_1 hFrontExt (.hsync_c(hsync_c), .nReset_c(nReset_c), 
        .clk_c(clk_c), .hsync_0(hsync_0), .hsync(hsync));
    CM8INV G_308_cm8i (.A(aVga[11]), .Y(G_308_cm8iZ0));
    CM8 G_16_i_0 (.D0(GNDZ0), .D1(VCCZ0), .D2(GNDZ0), .D3(N_372_1), 
        .S00(hsync_0), .S01(VCCZ0), .S10(pixelZ0Z8), .S11(GNDZ0), .Y(
        y_38));
    CM8 pixel_n3_0_xor2 (.D0(GNDZ0), .D1(pixelZ0Z_0), .D2(VCCZ0), .D3(
        pixel_iZ0Z_0), .S00(pixelZ0Z_1), .S01(pixelZ0Z_2), .S10(
        pixelZ0Z_3), .S11(GNDZ0), .Y(pixel_n3));
    DFC1B pixel_3 (.D(pixel_n3), .CLK(clk_c), .CLR(hsync), .Q(
        pixelZ0Z_3));
    CM8INV v_n5_0_xor2_i_cm8i (.A(aVga[11]), .Y(v_n5_0_xor2_i_cm8iZ0));
    DFE4F hdelay_2 (.D(N_377), .CLK(clk_c), .PRE(nReset_c), .E(y_38), 
        .Q(hdelayZ0Z_2));
    AND2 un1_hsync_3_i_0_and2_209 (.A(aVga[13]), .B(aVga[10]), .Y(y_5));
    CM8 h_l5_i_0 (.D0(hsync), .D1(GNDZ0), .D2(GNDZ0), .D3(hsync), .S00(
        aVga[5]), .S01(VCCZ0), .S10(h_l5_i_0_cm8iZ0), .S11(N_326), .Y(
        y_41));
    CM8 G_55_i_and2_0_and2 (.D0(VCCZ0), .D1(N_221_n), .D2(VCCZ0), .D3(
        VCCZ0), .S00(aVga[14]), .S01(aVga[11]), .S10(
        G_55_i_and2_0_and2_cm8iZ0), .S11(N_330_n), .Y(y_26));
    CM8INV un1_un1_un1_hsync_1_i_0_0_cm8i (.A(vdelayZ0Z_3), .Y(
        un1_un1_un1_hsync_1_i_0_0_cm8iZ0));
    DFC1B pixel8 (.D(pixel8_3), .CLK(clk_c), .CLR(hsync), .Q(pixelZ0Z8)
        );
    CM8INV pixel_n2_0_xor2_cm8i (.A(pixelZ0Z_1), .Y(
        pixel_n2_0_xor2_cm8iZ0));
    XNOR2 G_200_0 (.A(y_51), .B(aVga[11]), .Y(y_36));
    AND3 wrVga_0_and2_0_and2 (.A(pixelZ0Z8), .B(lineZ0), .C(frameZ0), 
        .Y(wrVga));
    CM8INV v_n2_0_xor2_i_cm8i (.A(aVga[8]), .Y(v_n2_0_xor2_i_cm8iZ0));
    DFE1B h_6 (.D(N_165), .CLK(clk_c), .E(y_42), .Q(aVga[6]));
    CM8 G_10_i_0 (.D0(N_114_0), .D1(un1_hsync_2_i), .D2(un1_hsync_2_i), 
        .D3(un1_hsync_2_i), .S00(N_327), .S01(VCCZ0), .S10(vdelayZ0Z_3)
        , .S11(vdelayZ0Z_4), .Y(y_48));
    CM8 vdelay_l1_0_and2_0_and2 (.D0(N_114_0), .D1(GNDZ0), .D2(GNDZ0), 
        .D3(N_114_0), .S00(vdelayZ0Z_0), .S01(VCCZ0), .S10(vdelayZ0Z_1)
        , .S11(GNDZ0), .Y(vdelay_l1));
    OR2A G_95_0 (.A(rise_1), .B(rise_0), .Y(N_114_0));
    OR2A G_95 (.A(rise_1), .B(rise_0), .Y(y_45));
    OR2B G_55_i_and2_0_and2_192_n (.A(aVga[12]), .B(aVga[13]), .Y(
        N_221_n));
    XOR2 G_114 (.A(pixelZ0Z_0), .B(pixelZ0Z_1), .Y(y_44));
    myFAILINGEX vFrontExt (.rise({rise_1, rise_0}), .vsync_c(vsync_c), 
        .nReset_c(nReset_c), .clk_c(clk_c));
    DFE3C v_3 (.D(y_30), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[10]));
    AND2 line_8_0_and2_i (.A(hsync_0), .B(nlineZ0Z_0), .Y(y_31));
    CM8INV hdelay_l2_i_and2_0_and2_cm8i (.A(hsync_0), .Y(
        hdelay_l2_i_and2_0_and2_cm8iZ0));
    OR2B vdelay_l0_i_and2_0_and2 (.A(vdelayZ0Z_0), .B(N_114_0), .Y(
        N_355));
    CM8INV nline_9_i_0_cm8i_1 (.A(nlineZ0Z_1), .Y(
        nline_9_i_0_cm8iZ0Z_1));
    CM8INV h_l5_i_0_cm8i (.A(aVga[4]), .Y(h_l5_i_0_cm8iZ0));
    CM8INV G_310_cm8i (.A(y_51), .Y(G_310_cm8iZ0));
    DFE3C v_1 (.D(y_37), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(aVga[8])
        );
    VCC VCC (.Y(VCCZ0));
    CM8 h_l4_0_and3_0_and2 (.D0(hsync_0), .D1(GNDZ0), .D2(GNDZ0), .D3(
        hsync_0), .S00(N_326), .S01(VCCZ0), .S10(aVga[4]), .S11(GNDZ0), 
        .Y(h_l4));
    CM8 v_n5_0_xor2_i (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(VCCZ0), 
        .S00(aVga[12]), .S01(VCCZ0), .S10(v_n5_0_xor2_i_cm8iZ0), .S11(
        y_51), .Y(y_33));
    CM8 hdelay_l2_i_and2_0_and2 (.D0(VCCZ0), .D1(
        hdelay_l2_i_and2_0_and2_cm8iZ0), .D2(
        hdelay_l2_i_and2_0_and2_cm8iZ0), .D3(VCCZ0), .S00(hdelayZ0Z_2), 
        .S01(VCCZ0), .S10(hdelayZ0Z_1), .S11(hdelayZ0Z_0), .Y(N_377));
    DFE4F nline_0 (.D(y_27), .CLK(clk_c), .PRE(nReset_c), .E(
        un1_hsync_2_i), .Q(nlineZ0Z_0));
    DFE1B h_3 (.D(h_l3), .CLK(clk_c), .E(y_42), .Q(aVga[3]));
    DFE3C v_6 (.D(y_34), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[13]));
    DFE3C v_2 (.D(y_32), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(aVga[9])
        );
    CM8 pixel_n2_0_xor2 (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(VCCZ0)
        , .S00(pixelZ0Z_2), .S01(VCCZ0), .S10(pixel_n2_0_xor2_cm8iZ0), 
        .S11(pixel_iZ0Z_0), .Y(pixel_n2));
    CM8INV nline_9_i_0_cm8i_2 (.A(nlineZ0Z_2), .Y(
        nline_9_i_0_cm8iZ0Z_2));
    AND3C G_16_i_0_and2_0_1 (.A(hdelayZ0Z_0), .B(hdelayZ0Z_1), .C(
        hdelayZ0Z_2), .Y(N_372_1));
    CM8 pixel_i_0 (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(GNDZ0), 
        .S00(pixelZ0Z_0), .S01(VCCZ0), .S10(GNDZ0), .S11(GNDZ0), .Y(
        pixel_iZ0Z_0));
    CM8 v_n2_0_xor2_i (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(VCCZ0), 
        .S00(aVga[9]), .S01(VCCZ0), .S10(v_n2_0_xor2_i_cm8iZ0), .S11(
        aVga_iZ0Z_7), .Y(y_32));
    CM8INV vdelay_l4_i_and2_0_and2_cm8i (.A(N_114_0), .Y(
        vdelay_l4_i_and2_0_and2_cm8iZ0));
    CM8 nline_9_i_0_1 (.D0(GNDZ0), .D1(nline_9_i_0_cm8iZ0Z_1), .D2(
        GNDZ0), .D3(nlineZ0Z_0), .S00(N_114_0), .S01(VCCZ0), .S10(
        linesZ0Z350), .S11(GNDZ0), .Y(y_46));
    CM8 vdelay_l4_i_and2_0_and2 (.D0(VCCZ0), .D1(
        vdelay_l4_i_and2_0_and2_cm8iZ0), .D2(
        vdelay_l4_i_and2_0_and2_cm8iZ0), .D3(VCCZ0), .S00(vdelayZ0Z_4), 
        .S01(VCCZ0), .S10(vdelayZ0Z_3), .S11(N_327), .Y(N_357));
    DFE4F hdelay_0 (.D(N_376), .CLK(clk_c), .PRE(nReset_c), .E(y_38), 
        .Q(hdelayZ0Z_0));
    CM8 G_67_i_0_195 (.D0(VCCZ0), .D1(VCCZ0), .D2(VCCZ0), .D3(GNDZ0), 
        .S00(aVga[6]), .S01(VCCZ0), .S10(aVga[4]), .S11(aVga[5]), .Y(
        y_8));
    CM8 nline_9_1_i_and2_0 (.D0(VCCZ0), .D1(nline_9_1_i_and2_cm8iZ0Z_0)
        , .D2(VCCZ0), .D3(nlineZ0Z_2), .S00(N_114_0), .S01(VCCZ0), 
        .S10(linesZ0Z350), .S11(GNDZ0), .Y(y_27));
    AND2B G_67_i_0_and2_0_188 (.A(aVga[2]), .B(aVga[3]), .Y(y_9));
    AND4A pixel8_3_0_and2 (.A(pixelZ0Z_3), .B(pixelZ0Z_2), .C(
        pixel_iZ0Z_0), .D(pixelZ0Z_1), .Y(pixel8_3));
    DF1 dVgaZ0Z_7 (.D(dVga[6]), .CLK(clk_c), .Q(dVga[7]));
    DFE4F vdelay_3 (.D(N_356), .CLK(clk_c), .PRE(nReset_c), .E(y_48), 
        .Q(vdelayZ0Z_3));
    CM8 G_308 (.D0(aVga[11]), .D1(G_308_cm8iZ0), .D2(GNDZ0), .D3(VCCZ0)
        , .S00(aVga[14]), .S01(VCCZ0), .S10(N_221_n), .S11(y_51), .Y(
        y_29));
    DF1 dVgaZ0Z_4 (.D(dVga[3]), .CLK(clk_c), .Q(dVga[4]));
    DFE3C vdelay_2 (.D(vdelay_l2), .CLK(clk_c), .CLR(nReset_c), .E(
        y_48), .Q(vdelayZ0Z_2));
    CM8 h_l2_0_and3_i (.D0(GNDZ0), .D1(hsync), .D2(hsync), .D3(GNDZ0), 
        .S00(aVga[1]), .S01(aVga[0]), .S10(aVga[2]), .S11(GNDZ0), .Y(
        y_35));
    CM8INV G_311_cm8i (.A(N_326), .Y(G_311_cm8iZ0));
    CM8 G_67_i_0 (.D0(y_8), .D1(VCCZ0), .D2(y_8), .D3(y_8), .S00(
        G_67_i_0_cm8iZ0), .S01(y_9), .S10(aVga[0]), .S11(aVga[5]), .Y(
        y_43));
    DFE3C hdelay_1 (.D(hdelay_l1), .CLK(clk_c), .CLR(nReset_c), .E(
        y_38), .Q(hdelayZ0Z_1));
    DFC1B pixel_1 (.D(y_44), .CLK(clk_c), .CLR(hsync), .Q(pixelZ0Z_1));
    DFC1B pixel_0 (.D(pixel_iZ0Z_0), .CLK(clk_c), .CLR(hsync), .Q(
        pixelZ0Z_0));
    OR3B G_301 (.A(aVga[8]), .B(aVga[9]), .C(aVga_iZ0Z_7), .Y(N_337));
    GND GND (.Y(GNDZ0));
    CM8 v_n6_0_xor2_i (.D0(aVga[12]), .D1(N_221_n), .D2(GNDZ0), .D3(
        VCCZ0), .S00(aVga[13]), .S01(VCCZ0), .S10(v_n6_0_xor2_i_cm8iZ0)
        , .S11(y_51), .Y(y_34));
    CM8 un1_hsync_3_i_0 (.D0(GNDZ0), .D1(un1_hsync_3_i_0_cm8iZ0), .D2(
        VCCZ0), .D3(VCCZ0), .S00(y_5), .S01(y_4), .S10(y), .S11(hsync), 
        .Y(y_39));
    OR3C wrVga_iZ0 (.A(lineZ0), .B(frameZ0), .C(pixelZ0Z8), .Y(wrVga_i)
        );
    CM8 G_13_i_0 (.D0(hsync_0), .D1(hsync_0), .D2(hsync_0), .D3(GNDZ0), 
        .S00(access), .S01(dirout_0), .S10(G_13_i_0_cm8iZ0), .S11(
        N_347), .Y(y_42));
    DF1 dVgaZ0Z_3 (.D(dVga[2]), .CLK(clk_c), .Q(dVga[3]));
    DFE1B h_4 (.D(h_l4), .CLK(clk_c), .E(y_42), .Q(aVga[4]));
    CM8 hdelay_l1_0_and2_0_and2 (.D0(hsync_0), .D1(GNDZ0), .D2(GNDZ0), 
        .D3(hsync_0), .S00(hdelayZ0Z_0), .S01(VCCZ0), .S10(hdelayZ0Z_1)
        , .S11(GNDZ0), .Y(hdelay_l1));
    CM8INV un1_hsync_3_i_0_cm8i (.A(N_337), .Y(un1_hsync_3_i_0_cm8iZ0));
    CM8 G_305 (.D0(GNDZ0), .D1(aVga[7]), .D2(VCCZ0), .D3(aVga_iZ0Z_7), 
        .S00(aVga[8]), .S01(aVga[9]), .S10(aVga[10]), .S11(GNDZ0), .Y(
        y_30));
    OR4D G_290 (.A(aVga[1]), .B(aVga[3]), .C(aVga[0]), .D(aVga[2]), .Y(
        N_326));
    DFC1B pixel_2 (.D(pixel_n2), .CLK(clk_c), .CLR(hsync), .Q(
        pixelZ0Z_2));
    DF1 dVgaZ0Z_5 (.D(dVga[4]), .CLK(clk_c), .Q(dVga[5]));
    AND2 G_10_i_0_and2 (.A(hsync_0), .B(N_114_0), .Y(un1_hsync_2_i));
    AND4 v_ca7 (.A(aVga[11]), .B(aVga[12]), .C(aVga[13]), .D(aVga[14]), 
        .Y(y_50));
    OR2A un1_hsync_3_i_0_236 (.A(frameZ0), .B(nlineZ0Z_0), .Y(y));
    DFE3C nline_1 (.D(y_46), .CLK(clk_c), .CLR(nReset_c), .E(
        un1_hsync_2_i), .Q(nlineZ0Z_1));
    CM8INV nline_9_1_i_and2_cm8i_0 (.A(nlineZ0Z_0), .Y(
        nline_9_1_i_and2_cm8iZ0Z_0));
    DF1 dVgaZ0Z_2 (.D(dVga[1]), .CLK(clk_c), .Q(dVga[2]));
    DFE1B h_1 (.D(h_l1), .CLK(clk_c), .E(y_42), .Q(aVga[1]));
    DFE3C frame (.D(y_45), .CLK(clk_c), .CLR(nReset_c), .E(y_49), .Q(
        frameZ0));
    DFE3C v_0 (.D(aVga_iZ0Z_7), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[7]));
    CM8 nline_9_i_0_2 (.D0(GNDZ0), .D1(nline_9_i_0_cm8iZ0Z_2), .D2(
        GNDZ0), .D3(nlineZ0Z_1), .S00(N_114_0), .S01(VCCZ0), .S10(
        linesZ0Z350), .S11(GNDZ0), .Y(y_47));
    DFE3C line (.D(y_31), .CLK(clk_c), .CLR(nReset_c), .E(y_40), .Q(
        lineZ0));
    XA1 h_l1_0_and3_0_and2 (.A(aVga[0]), .B(aVga[1]), .C(hsync_0), .Y(
        h_l1));
    CM8 G_311 (.D0(GNDZ0), .D1(G_311_cm8iZ0), .D2(VCCZ0), .D3(N_326), 
        .S00(aVga[4]), .S01(aVga[5]), .S10(aVga[6]), .S11(GNDZ0), .Y(
        N_347));
    AND2A h_l0_0_and3_i (.A(aVga[0]), .B(hsync_0), .Y(N_293));
    DF1 dVgaZ0Z_1 (.D(dVga[0]), .CLK(clk_c), .Q(dVga[1]));
    DFE3C v_4 (.D(y_36), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[11]));
    CM8INV h_l3_0_and3_0_and2_cm8i (.A(hsync_0), .Y(
        h_l3_0_and3_0_and2_cm8iZ0));
    CM8 G_310 (.D0(GNDZ0), .D1(VCCZ0), .D2(VCCZ0), .D3(GNDZ0), .S00(
        G_310_cm8iZ0), .S01(y_50), .S10(aVga[15]), .S11(GNDZ0), .Y(
        y_28));
    DFE4F vdelay_0 (.D(N_355), .CLK(clk_c), .PRE(nReset_c), .E(y_48), 
        .Q(vdelayZ0Z_0));
    AND2 h_l6_i_0 (.A(hsync_0), .B(N_347), .Y(N_165));
    OR3 G_291 (.A(vdelayZ0Z_0), .B(vdelayZ0Z_2), .C(vdelayZ0Z_1), .Y(
        N_327));
    CM8INV G_13_i_0_cm8i (.A(aVga[6]), .Y(G_13_i_0_cm8iZ0));
    CM8INV v_n6_0_xor2_i_cm8i (.A(aVga[11]), .Y(v_n6_0_xor2_i_cm8iZ0));
    CM8INV G_55_i_and2_0_and2_cm8i (.A(aVga[15]), .Y(
        G_55_i_and2_0_and2_cm8iZ0));
    DFE3C v_7 (.D(y_29), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[14]));
    DFE1B notVga (.D(y_43), .CLK(clk_c), .E(hsync), .Q(relay_c));
    DFE1B lines350 (.D(y_26), .CLK(clk_c), .E(hsync), .Q(linesZ0Z350));
    DF1 dVgaZ0Z_0 (.D(iVideo_c), .CLK(clk_c), .Q(dVga[0]));
    DFE3C vdelay_1 (.D(vdelay_l1), .CLK(clk_c), .CLR(nReset_c), .E(
        y_48), .Q(vdelayZ0Z_1));
    AND2B G_294_n (.A(aVga[9]), .B(aVga[10]), .Y(N_330_n));
    DFE4F vdelay_4 (.D(N_357), .CLK(clk_c), .PRE(nReset_c), .E(y_48), 
        .Q(vdelayZ0Z_4));
    CM8INV vdelay_l3_i_and2_0_and2_cm8i (.A(N_114_0), .Y(
        vdelay_l3_i_and2_0_and2_cm8iZ0));
    XNOR2 G_199_0 (.A(aVga_iZ0Z_7), .B(aVga[8]), .Y(y_37));
    DFE3C v_8 (.D(y_28), .CLK(clk_c), .CLR(y_45), .E(y_39), .Q(
        aVga[15]));
    CM8 h_l3_0_and3_0_and2 (.D0(aVga[3]), .D1(N_326), .D2(GNDZ0), .D3(
        GNDZ0), .S00(aVga[1]), .S01(aVga[0]), .S10(y_9), .S11(
        h_l3_0_and3_0_and2_cm8iZ0), .Y(h_l3));
    OR2B hdelay_l0_i_and2_0_and2 (.A(hdelayZ0Z_0), .B(hsync_0), .Y(
        N_376));
    DF1 dVgaZ0Z_6 (.D(dVga[5]), .CLK(clk_c), .Q(dVga[6]));
    CM8 aVga_i_7 (.D0(VCCZ0), .D1(GNDZ0), .D2(GNDZ0), .D3(GNDZ0), .S00(
        aVga[7]), .S01(VCCZ0), .S10(GNDZ0), .S11(GNDZ0), .Y(
        aVga_iZ0Z_7));
    NAND4 v_ca3 (.A(aVga[7]), .B(aVga[8]), .C(aVga[9]), .D(aVga[10]), 
        .Y(y_51));
    DFE1B h_0 (.D(N_293), .CLK(clk_c), .E(y_42), .Q(aVga[0]));
    DFE1B h_5 (.D(y_41), .CLK(clk_c), .E(y_42), .Q(aVga[5]));
    CM8 un1_un1_un1_hsync_i_0_0 (.D0(hsync_0), .D1(GNDZ0), .D2(GNDZ0), 
        .D3(GNDZ0), .S00(pixelZ0Z8), .S01(N_372_1), .S10(GNDZ0), .S11(
        GNDZ0), .Y(y_40));
    CM8INV G_67_i_0_cm8i (.A(aVga[1]), .Y(G_67_i_0_cm8iZ0));
    CM8 un1_un1_un1_hsync_1_i_0_0 (.D0(N_114_0), .D1(hsync), .D2(
        N_114_0), .D3(VCCZ0), .S00(un1_un1_un1_hsync_1_i_0_0_cm8iZ0), 
        .S01(N_114_0), .S10(vdelayZ0Z_4), .S11(N_327), .Y(y_49));
    AND4 un1_hsync_3_i_0_and2_211 (.A(aVga[11]), .B(aVga[14]), .C(
        aVga[12]), .D(aVga[15]), .Y(y_4));
    CM8 vdelay_l2_0_and2_0_and2 (.D0(N_114_0), .D1(GNDZ0), .D2(GNDZ0), 
        .D3(N_114_0), .S00(vdelayZ0Z_2), .S01(VCCZ0), .S10(vdelayZ0Z_1)
        , .S11(vdelayZ0Z_0), .Y(vdelay_l2));
    CM8 vdelay_l3_i_and2_0_and2 (.D0(VCCZ0), .D1(
        vdelay_l3_i_and2_0_and2_cm8iZ0), .D2(
        vdelay_l3_i_and2_0_and2_cm8iZ0), .D3(VCCZ0), .S00(N_327), .S01(
        VCCZ0), .S10(vdelayZ0Z_3), .S11(GNDZ0), .Y(N_356));
    
endmodule