data/full_repos/permissive/157608247/testbench/candy_pc_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/157608247/testbench/candy_pc_tb.v:1: Cannot find include file: candy_defines.v\n`include "candy_defines.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v.v\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v.sv\n             candy_defines.v\n             candy_defines.v.v\n             candy_defines.v.sv\n             obj_dir/candy_defines.v\n             obj_dir/candy_defines.v.v\n             obj_dir/candy_defines.v.sv\n%Error: data/full_repos/permissive/157608247/testbench/candy_pc_tb.v:9: Define or directive not defined: \'`SRAMAddrWidth\'\nwire [`SRAMAddrWidth] pc;\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_pc_tb.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`SRAMAddrWidth] pc;\n                    ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_pc_tb.v:23: Define or directive not defined: \'`RstEnable\'\n        rst <= `RstEnable;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_pc_tb.v:23: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst <= `RstEnable;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_pc_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #0 begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/157608247/testbench/candy_pc_tb.v:27: Define or directive not defined: \'`RstDisable\'\n        rst <= `RstDisable;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_pc_tb.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst <= `RstDisable;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_pc_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #25 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_pc_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: Exiting due to 7 error(s), 3 warning(s)\n'
module candy_pc_tb;

reg clk;
reg rst;
reg pc_en;

wire [`SRAMAddrWidth] pc;


candy_pc pc0(
    .clk(clk),
    .rst(rst),
    .pc_enable(pc_en),
    .pc(pc)
);


initial begin
    #0 begin
        clk <= 1'b0;
        rst <= `RstEnable;
        pc_en <= 1'b1;
    end
    #25 begin
        rst <= `RstDisable;
    end

end

always #5 clk <= ~clk;

endmodule
module candy_pc_tb;


reg clk;
reg rst;
reg pc_en;

wire [`SRAMAddrWidth] pc;


candy_pc pc0(
    .clk(clk),
    .rst(rst),
    .pc_enable(pc_en),
    .pc(pc)
);


initial begin
    #0 begin
        clk <= 1'b0;
        rst <= `RstEnable;
        pc_en <= 1'b1;
    end
    #25 begin
        rst <= `RstDisable;
    end

end

always #5 clk <= ~clk;

endmodule