data/full_repos/permissive/195227969/work/hwtst/div/illegalOp/multill.v
 line:309: before: "valid"
data/verilator_xmls/d0e3ef4d-9262-418b-aa4c-33b9dc14532b.xml
module multill
  (
   input [31:0] Op,
   output reg   ill
   );

   always @(Op)
     casez ( {Op[6:2],Op[14:12]} )


       8'b00000_00? : ill = 1'b0;
       8'b00000_010 : ill = 1'b0;
       8'b00000_011 : ill = 1'b1;
       8'b00000_10? : ill = 1'b0;
       8'b00000_11? : ill = 1'b1;

       8'b00001_??? : ill = 1'b?;

       8'b00010_000 : ill = 1'b0;
       8'b00010_001 : ill = 1'b1;
       8'b00010_01? : ill = 1'b1;
       8'b00010_1?? : ill = 1'b1;

       8'b00011_00? : ill = 1'b0;
       8'b00011_01? : ill = 1'b1;
       8'b00011_1?? : ill = 1'b1;

       8'b0010?_??? : ill = 1'b0;
       8'b0011?_??? : ill = 1'b?;

       8'b01000_00? : ill = 1'b0;
       8'b01000_010 : ill = 1'b0;
       8'b01000_011 : ill = 1'b1;
       8'b01000_1?? : ill = 1'b1;

       8'b01001_??? : ill = 1'b?;
       8'b0101?_??? : ill = 1'b?;
       8'b0110?_??? : ill = 1'b0;
       8'b0111?_??? : ill = 1'b?;
       8'b10???_??? : ill = 1'b?;

       8'b11000_00? : ill = 1'b0;
       8'b11000_01? : ill = 1'b1;
       8'b11000_1?? : ill = 1'b0;

       8'b11011_000 : ill = 1'b0;
       8'b11001_001 : ill = 1'b1;
       8'b11001_01? : ill = 1'b1;
       8'b11001_1?? : ill = 1'b1;

       8'b11010_??? : ill = 1'b?;
       8'b11011_??? : ill = 1'b0;

       8'b11100_0?? : ill = 1'b0;
       8'b11100_100 : ill = 1'b1;
       8'b11100_101 : ill = 1'b0;
       8'b11100_11? : ill = 1'b0;
       
       8'b11101_??? : ill = 1'b?;
       8'b1111?_??? : ill = 1'b?;
     endcase
endmodule
module multill
  (
   input [31:0] Op,
   output reg   ill
   );


   always @(Op)
     casez ( {Op[6:2],Op[14:12]} )


       8'b00000_00? : ill = 1'b0;
       8'b00000_010 : ill = 1'b0;
       8'b00000_011 : ill = 1'b1;
       8'b00000_10? : ill = 1'b0;
       8'b00000_11? : ill = 1'b1;

       8'b00001_??? : ill = 1'b?;

       8'b00010_000 : ill = 1'b0;
       8'b00010_001 : ill = 1'b1;
       8'b00010_01? : ill = 1'b1;
       8'b00010_1?? : ill = 1'b1;

       8'b00011_00? : ill = 1'b0;
       8'b00011_01? : ill = 1'b1;
       8'b00011_1?? : ill = 1'b1;

       8'b0010?_??? : ill = 1'b0;
       8'b0011?_??? : ill = 1'b?;

       8'b01000_00? : ill = 1'b0;
       8'b01000_010 : ill = 1'b0;
       8'b01000_011 : ill = 1'b1;
       8'b01000_1?? : ill = 1'b1;

       8'b01001_??? : ill = 1'b?;
       8'b0101?_??? : ill = 1'b?;
       8'b0110?_??? : ill = 1'b0;
       8'b0111?_??? : ill = 1'b?;
       8'b10???_??? : ill = 1'b?;

       8'b11000_00? : ill = 1'b0;
       8'b11000_01? : ill = 1'b1;
       8'b11000_1?? : ill = 1'b0;

       8'b11011_000 : ill = 1'b0;
       8'b11001_001 : ill = 1'b1;
       8'b11001_01? : ill = 1'b1;
       8'b11001_1?? : ill = 1'b1;

       8'b11010_??? : ill = 1'b?;
       8'b11011_??? : ill = 1'b0;

       8'b11100_0?? : ill = 1'b0;
       8'b11100_100 : ill = 1'b1;
       8'b11100_101 : ill = 1'b0;
       8'b11100_11? : ill = 1'b0;
       
       8'b11101_??? : ill = 1'b?;
       8'b1111?_??? : ill = 1'b?;
     endcase
endmodule