data/full_repos/permissive/162338081/DebounceDivideCLK.v
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data/verilator_xmls/17530ccd-78ea-4ab1-b254-b5a1e00ca3c5.xml
module DebounceDivideCLK(CLK, Clock);
    input CLK;
    output reg Clock;
    reg [26:0]counter = 0;
    always @(posedge CLK)
    begin
        counter <= (counter >= 249999)?0:counter+1;
        Clock <= (counter < 125000)?1'b0:1'b1;
    end
endmodule
module DebounceDivideCLK(CLK, Clock);

    input CLK;
    output reg Clock;
    reg [26:0]counter = 0;
    always @(posedge CLK)
    begin
        counter <= (counter >= 249999)?0:counter+1;
        Clock <= (counter < 125000)?1'b0:1'b1;
    end
endmodule