data/full_repos/permissive/143278/ivltests/assign_neq.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/assign_neq.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #5 ;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/assign_neq.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/assign_neq.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #5 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/assign_neq.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #5 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/assign_neq.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #5 ;\n    ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

integer a;
integer b;
wire  result;
integer error;

assign result = (a != b);

initial
  begin
    a =  0;
    b = 0;
    error = 0;
    #5 ;
    if( result === 1'b1)
       error =1;
    a = 1;
    #5;
    if( result === 1'b0)
       error =1;

    b = 1;
    #5 ;
    if( result === 1'b1)
       error =1;

    a = 1002;
    b = 1001;
    #5 ;
    if( result === 1'b0)
       error =1;
    a = 1001;
    #5 ;
    if( result === 1'b1)
       error =1;

    if(error === 0)
	    $display("PASSED");
    else
	    $display("FAILED");
  end

endmodule
module test;


integer a;
integer b;
wire  result;
integer error;

assign result = (a != b);

initial
  begin
    a =  0;
    b = 0;
    error = 0;
    #5 ;
    if( result === 1'b1)
       error =1;
    a = 1;
    #5;
    if( result === 1'b0)
       error =1;

    b = 1;
    #5 ;
    if( result === 1'b1)
       error =1;

    a = 1002;
    b = 1001;
    #5 ;
    if( result === 1'b0)
       error =1;
    a = 1001;
    #5 ;
    if( result === 1'b1)
       error =1;

    if(error === 0)
	    $display("PASSED");
    else
	    $display("FAILED");
  end

endmodule