data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_module.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_module.v:41: Cannot find include file: adbg_defines.v\n`include "adbg_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog,data/full_repos/permissive/17099167/adbg_defines.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog,data/full_repos/permissive/17099167/adbg_defines.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog,data/full_repos/permissive/17099167/adbg_defines.v.sv\n             adbg_defines.v\n             adbg_defines.v.v\n             adbg_defines.v.sv\n             obj_dir/adbg_defines.v\n             obj_dir/adbg_defines.v.v\n             obj_dir/adbg_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module adbg_jsp_module (

			 tck_i,
			 module_tdo_o,
			 tdi_i,


			 capture_dr_i,
			 shift_dr_i,
			 update_dr_i,

			 data_register_i,
			 module_select_i,
			 top_inhibit_o,
			 rst_i,


			 wb_clk_i, wb_rst_i,


			 wb_adr_i, wb_dat_o, wb_dat_i, wb_cyc_i, wb_stb_i, wb_sel_i,
			 wb_we_i, wb_ack_o, wb_cab_i, wb_err_o, wb_cti_i, wb_bte_i, int_o 
			 );


   input         tck_i;
   output        module_tdo_o;
   input         tdi_i;


   input         capture_dr_i;
   input         shift_dr_i;
   input         update_dr_i;

   input [52:0]  data_register_i;
   input         module_select_i;
   output        top_inhibit_o;
   input         rst_i;
   

   input         wb_clk_i;
   input         wb_rst_i;
   input  [31:0] wb_adr_i;
   output [31:0] wb_dat_o;
   input  [31:0] wb_dat_i;
   input         wb_cyc_i;
   input         wb_stb_i;
   input   [3:0] wb_sel_i;
   input         wb_we_i;
   output        wb_ack_o;
   input         wb_cab_i;
   output        wb_err_o;
   input   [2:0] wb_cti_i;
   input   [1:0] wb_bte_i;
   output 	 int_o;
  

   wire 	 module_tdo_o;
   wire 	 top_inhibit_o;




   





   reg [3:0] 	 read_bit_count;
   reg [3:0]   write_bit_count;
   reg [3:0] 	 input_word_count;
   reg [3:0]     output_word_count;
   reg [3:0] 	 user_word_count;
   reg [7:0] 	 data_out_shift_reg;



   reg 		 rd_bit_ct_en;
   reg 		 rd_bit_ct_rst;
   reg 		 wr_bit_ct_en;
   reg 		 wr_bit_ct_rst;
   reg 		 in_word_ct_sel;
   reg 		 out_word_ct_sel;
   reg 		 in_word_ct_en;
   reg           out_word_ct_en;
   reg           user_word_ct_en;
   reg           user_word_ct_sel;
   reg 		 out_reg_ld_en;
   reg 		 out_reg_shift_en;
   reg 		 out_reg_data_sel;
   reg 		 biu_rd_strobe;
   reg 		 biu_wr_strobe;



   wire 	 in_word_count_zero;
   wire 	 out_word_count_zero;
   wire          user_word_count_zero;
   wire 	 rd_bit_count_max;
   wire 	 wr_bit_count_max;
      

   wire [3:0] 	 data_to_in_word_counter;
   wire [3:0] 	 data_to_out_word_counter;
   wire [3:0] 	 data_to_user_word_counter;
   wire [3:0] 	 decremented_in_word_count;
   wire [3:0] 	 decremented_out_word_count;
   wire [3:0] 	 decremented_user_word_count;
   wire [3:0] 	 count_data_in;
   wire [7:0] 	 data_to_biu;
   wire [7:0] 	 data_from_biu;
   wire [3:0] 	 biu_space_available;
   wire [3:0] 	 biu_bytes_available;
   wire [7:0] 	 count_data_from_biu;
   wire [7:0] 	 out_reg_data;





   assign count_data_from_biu = {biu_bytes_available, biu_space_available};
   assign count_data_in = {tdi_i, data_register_i[52:50]};
   assign data_to_biu = {tdi_i,data_register_i[52:46]};
   assign top_inhibit_o = 1'b0;




   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)             write_bit_count <= 4'h0;
	else if(wr_bit_ct_rst)   write_bit_count <= 4'h0;
	else if(wr_bit_ct_en)    write_bit_count <= write_bit_count + 4'h1;
     end

   assign wr_bit_count_max = (write_bit_count == 4'h7) ? 1'b1 : 1'b0;




   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)             read_bit_count <= 4'h0;
	else if(rd_bit_ct_rst)   read_bit_count <= 4'h0;
	else if(rd_bit_ct_en)    read_bit_count <= read_bit_count + 4'h1;
     end

   assign rd_bit_count_max = (read_bit_count == 4'h7) ? 1'b1 : 1'b0;




   assign data_to_in_word_counter = (in_word_ct_sel) ?  decremented_in_word_count : biu_space_available;
   assign decremented_in_word_count = input_word_count - 4'h1;

   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  input_word_count <= 4'h0;
	else if(in_word_ct_en)
	  input_word_count <= data_to_in_word_counter;
     end

   assign in_word_count_zero = (input_word_count == 4'h0);
   



   assign data_to_out_word_counter = (out_word_ct_sel) ?  decremented_out_word_count : biu_bytes_available;
   assign decremented_out_word_count = output_word_count - 4'h1;

   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  output_word_count <= 4'h0;
	else if(out_word_ct_en)
	  output_word_count <= data_to_out_word_counter;
     end

   assign out_word_count_zero = (output_word_count == 4'h0);




   assign data_to_user_word_counter = (user_word_ct_sel) ?  decremented_user_word_count : count_data_in;
   assign decremented_user_word_count = user_word_count - 4'h1;

   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)                 user_word_count <= 4'h0;
	else if(user_word_ct_en)  user_word_count <= data_to_user_word_counter;
     end

   assign user_word_count_zero = (user_word_count == 4'h0);
    



   assign out_reg_data = (out_reg_data_sel) ? count_data_from_biu : data_from_biu;

   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) data_out_shift_reg <= 8'h0;
	else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data;
	else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[7:1]};
     end

   assign module_tdo_o = data_out_shift_reg[0];
   






   adbg_jsp_biu jsp_biu_i (

			   .tck_i           (tck_i),
			   .rst_i           (rst_i),
			   .data_i          (data_to_biu),
			   .data_o          (data_from_biu),
			   .bytes_available_o (biu_bytes_available),
			   .bytes_free_o    (biu_space_available),
			   .rd_strobe_i     (biu_rd_strobe),
			   .wr_strobe_i     (biu_wr_strobe),
			   

			   .wb_clk_i        (wb_clk_i),
			   .wb_rst_i        (wb_rst_i),
			   .wb_adr_i        (wb_adr_i),
			   .wb_dat_o        (wb_dat_o),
			   .wb_dat_i        (wb_dat_i),
			   .wb_cyc_i        (wb_cyc_i),
			   .wb_stb_i        (wb_stb_i),
			   .wb_sel_i        (wb_sel_i),
			   .wb_we_i         (wb_we_i),
			   .wb_ack_o        (wb_ack_o),
			   .wb_cab_i        (wb_cab_i),
			   .wb_err_o        (wb_err_o),
			   .wb_cti_i        (wb_cti_i),
			   .wb_bte_i        (wb_bte_i),
			   .int_o           (int_o)
			   );









`define STATE_wr_idle     3'h0
`define STATE_wr_wait     3'h1
`define STATE_wr_counts   3'h2
`define STATE_wr_xfer     3'h3

   reg [2:0] wr_module_state;
   reg [2:0] wr_module_next_state;



   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  wr_module_state <= `STATE_wr_idle;
	else
	  wr_module_state <= wr_module_next_state;
     end



   always @ (wr_module_state or module_select_i or update_dr_i or capture_dr_i 
	     or shift_dr_i or wr_bit_count_max or tdi_i)
     begin
	case(wr_module_state)
	  `STATE_wr_idle:
	    begin
`ifdef ADBG_JSP_SUPPORT_MULTI
	       if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_wait;
`else
	       if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_counts;
`endif
	       else wr_module_next_state <= `STATE_wr_idle;
	    end
	   `STATE_wr_wait:
	   begin 
	     	 if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
	    	  else if(module_select_i && tdi_i) wr_module_next_state <= `STATE_wr_counts;
	       else wr_module_next_state <= `STATE_wr_wait;
	   end
	  `STATE_wr_counts:
	    begin
	       if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
	       else if(wr_bit_count_max) wr_module_next_state <= `STATE_wr_xfer;
	       else wr_module_next_state <= `STATE_wr_counts;
	    end

	  `STATE_wr_xfer:
	    begin
	       if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
	       else wr_module_next_state <= `STATE_wr_xfer;
	    end
	  
	  default: wr_module_next_state <= `STATE_wr_idle;
	endcase
     end
   


   always @ (wr_module_state or wr_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
	     or in_word_count_zero or out_word_count_zero or wr_bit_count_max or decremented_in_word_count
	     or decremented_out_word_count or user_word_count_zero)
     begin

	wr_bit_ct_en <= 1'b0;
	wr_bit_ct_rst <= 1'b0;
	in_word_ct_sel <= 1'b0;
	user_word_ct_sel <= 1'b0;
	in_word_ct_en <= 1'b0;
	user_word_ct_en <= 1'b0;
	biu_wr_strobe <= 1'b0;
	
	case(wr_module_state)
	  `STATE_wr_idle:
	    begin
	       in_word_ct_sel <= 1'b0;
	       

	       if(wr_module_next_state != `STATE_wr_idle) begin
		  wr_bit_ct_rst <= 1'b1;
		  in_word_ct_en <= 1'b1;
	       end
	    end


	  `STATE_wr_wait:
	    begin
	       wr_bit_ct_en <= 1'b0;
	    end

	  `STATE_wr_counts:
	    begin
	       if(shift_dr_i) begin
		  wr_bit_ct_en <= 1'b1;
		  user_word_ct_sel <= 1'b0;
		  
		  if(wr_bit_count_max) begin
		     wr_bit_ct_rst <= 1'b1;
		     user_word_ct_en <= 1'b1;
		  end
	       end
	    end
    
	  `STATE_wr_xfer:
	    begin
	       if(shift_dr_i) begin
		  wr_bit_ct_en <= 1'b1;
		  in_word_ct_sel <= 1'b1;
		  user_word_ct_sel <= 1'b1;
	       
		  if(wr_bit_count_max) begin
		     wr_bit_ct_rst <= 1'b1;
		  
		     if(!(in_word_count_zero || user_word_count_zero)) begin
			biu_wr_strobe <= 1'b1;
			in_word_ct_en <= 1'b1;
			user_word_ct_en <= 1'b1;
		     end

		  end
	       end
	    end

	  default: ;
	endcase
     end








`define STATE_rd_idle     4'h0
`define STATE_rd_counts   4'h1
`define STATE_rd_rdack   4'h2
`define STATE_rd_xfer  4'h3





   reg [2:0] rd_module_state;
   reg [2:0] rd_module_next_state;



   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  rd_module_state <= `STATE_rd_idle;
	else
	  rd_module_state <= rd_module_next_state;
     end



   always @ (rd_module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or rd_bit_count_max)
     begin
	case(rd_module_state)
	  `STATE_rd_idle:
	    begin
	       if(module_select_i && capture_dr_i) rd_module_next_state <= `STATE_rd_counts;
	       else rd_module_next_state <= `STATE_rd_idle;
	    end
	  `STATE_rd_counts:
	    begin
	       if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
	       else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
	       else rd_module_next_state <= `STATE_rd_counts;
	    end
	  `STATE_rd_rdack:
	    begin
               if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
               else rd_module_next_state <= `STATE_rd_xfer;
	    end
	  `STATE_rd_xfer:
	    begin
	       if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
	       else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
	       else rd_module_next_state <= `STATE_rd_xfer;
	    end
	  
	  default: rd_module_next_state <= `STATE_rd_idle;
	endcase
     end
   


   always @ (rd_module_state or rd_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
	     or in_word_count_zero or out_word_count_zero or rd_bit_count_max or decremented_in_word_count
	     or decremented_out_word_count)
     begin

	rd_bit_ct_en <= 1'b0;
	rd_bit_ct_rst <= 1'b0;
	out_word_ct_sel <= 1'b0;
	out_word_ct_en <= 1'b0;
	out_reg_ld_en <= 1'b0;
	out_reg_shift_en <= 1'b0;
	out_reg_data_sel <= 1'b0;
	biu_rd_strobe <= 1'b0;
	
	case(rd_module_state)
	  `STATE_rd_idle:
	    begin
	       out_reg_data_sel <= 1'b1;
	       out_word_ct_sel <= 1'b0;
	       

	       if(rd_module_next_state != `STATE_rd_idle) begin
		  out_reg_ld_en <= 1'b1;
		  rd_bit_ct_rst <= 1'b1;
		  out_word_ct_en <= 1'b1;
	       end
	    end

	  `STATE_rd_counts:
	    begin
	       if(shift_dr_i) begin
		  rd_bit_ct_en <= 1'b1;
		  out_reg_shift_en <= 1'b1;
		  
		  if(rd_bit_count_max) begin
		     rd_bit_ct_rst <= 1'b1;
		     

		     if(!out_word_count_zero) begin
			out_reg_ld_en <= 1'b1;
			out_reg_shift_en <= 1'b0;
		     end
		  end
	       end
	    end
 
	  `STATE_rd_rdack:
	    begin
	       if(shift_dr_i) begin
		  rd_bit_ct_en <= 1'b1;
		  out_reg_shift_en <= 1'b1;
		  out_reg_data_sel <= 1'b0;
      

      
		  if(!out_word_count_zero) begin
		     biu_rd_strobe <= 1'b1;
		  end
	       end
	    end
    
	  `STATE_rd_xfer:
	    begin
	       if(shift_dr_i) begin
		  rd_bit_ct_en <= 1'b1;
		  out_word_ct_sel <= 1'b1;
		  out_reg_shift_en <= 1'b1;
		  out_reg_data_sel <= 1'b0;
	       
		  if(rd_bit_count_max) begin
		     rd_bit_ct_rst <= 1'b1;


		     if(!out_word_count_zero) begin
			out_reg_ld_en <= 1'b1;
			out_reg_shift_en <= 1'b0;
			out_word_ct_en <= 1'b1;
		     end
		  end
	       end
	    end

	  default: ;
	endcase
     end


endmodule
module adbg_jsp_module (

			 tck_i,
			 module_tdo_o,
			 tdi_i,


			 capture_dr_i,
			 shift_dr_i,
			 update_dr_i,

			 data_register_i,
			 module_select_i,
			 top_inhibit_o,
			 rst_i,


			 wb_clk_i, wb_rst_i,


			 wb_adr_i, wb_dat_o, wb_dat_i, wb_cyc_i, wb_stb_i, wb_sel_i,
			 wb_we_i, wb_ack_o, wb_cab_i, wb_err_o, wb_cti_i, wb_bte_i, int_o 
			 );



   input         tck_i;
   output        module_tdo_o;
   input         tdi_i;


   input         capture_dr_i;
   input         shift_dr_i;
   input         update_dr_i;

   input [52:0]  data_register_i;
   input         module_select_i;
   output        top_inhibit_o;
   input         rst_i;
   

   input         wb_clk_i;
   input         wb_rst_i;
   input  [31:0] wb_adr_i;
   output [31:0] wb_dat_o;
   input  [31:0] wb_dat_i;
   input         wb_cyc_i;
   input         wb_stb_i;
   input   [3:0] wb_sel_i;
   input         wb_we_i;
   output        wb_ack_o;
   input         wb_cab_i;
   output        wb_err_o;
   input   [2:0] wb_cti_i;
   input   [1:0] wb_bte_i;
   output 	 int_o;
  

   wire 	 module_tdo_o;
   wire 	 top_inhibit_o;




   





   reg [3:0] 	 read_bit_count;
   reg [3:0]   write_bit_count;
   reg [3:0] 	 input_word_count;
   reg [3:0]     output_word_count;
   reg [3:0] 	 user_word_count;
   reg [7:0] 	 data_out_shift_reg;



   reg 		 rd_bit_ct_en;
   reg 		 rd_bit_ct_rst;
   reg 		 wr_bit_ct_en;
   reg 		 wr_bit_ct_rst;
   reg 		 in_word_ct_sel;
   reg 		 out_word_ct_sel;
   reg 		 in_word_ct_en;
   reg           out_word_ct_en;
   reg           user_word_ct_en;
   reg           user_word_ct_sel;
   reg 		 out_reg_ld_en;
   reg 		 out_reg_shift_en;
   reg 		 out_reg_data_sel;
   reg 		 biu_rd_strobe;
   reg 		 biu_wr_strobe;



   wire 	 in_word_count_zero;
   wire 	 out_word_count_zero;
   wire          user_word_count_zero;
   wire 	 rd_bit_count_max;
   wire 	 wr_bit_count_max;
      

   wire [3:0] 	 data_to_in_word_counter;
   wire [3:0] 	 data_to_out_word_counter;
   wire [3:0] 	 data_to_user_word_counter;
   wire [3:0] 	 decremented_in_word_count;
   wire [3:0] 	 decremented_out_word_count;
   wire [3:0] 	 decremented_user_word_count;
   wire [3:0] 	 count_data_in;
   wire [7:0] 	 data_to_biu;
   wire [7:0] 	 data_from_biu;
   wire [3:0] 	 biu_space_available;
   wire [3:0] 	 biu_bytes_available;
   wire [7:0] 	 count_data_from_biu;
   wire [7:0] 	 out_reg_data;





   assign count_data_from_biu = {biu_bytes_available, biu_space_available};
   assign count_data_in = {tdi_i, data_register_i[52:50]};
   assign data_to_biu = {tdi_i,data_register_i[52:46]};
   assign top_inhibit_o = 1'b0;




   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)             write_bit_count <= 4'h0;
	else if(wr_bit_ct_rst)   write_bit_count <= 4'h0;
	else if(wr_bit_ct_en)    write_bit_count <= write_bit_count + 4'h1;
     end

   assign wr_bit_count_max = (write_bit_count == 4'h7) ? 1'b1 : 1'b0;




   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)             read_bit_count <= 4'h0;
	else if(rd_bit_ct_rst)   read_bit_count <= 4'h0;
	else if(rd_bit_ct_en)    read_bit_count <= read_bit_count + 4'h1;
     end

   assign rd_bit_count_max = (read_bit_count == 4'h7) ? 1'b1 : 1'b0;




   assign data_to_in_word_counter = (in_word_ct_sel) ?  decremented_in_word_count : biu_space_available;
   assign decremented_in_word_count = input_word_count - 4'h1;

   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  input_word_count <= 4'h0;
	else if(in_word_ct_en)
	  input_word_count <= data_to_in_word_counter;
     end

   assign in_word_count_zero = (input_word_count == 4'h0);
   



   assign data_to_out_word_counter = (out_word_ct_sel) ?  decremented_out_word_count : biu_bytes_available;
   assign decremented_out_word_count = output_word_count - 4'h1;

   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  output_word_count <= 4'h0;
	else if(out_word_ct_en)
	  output_word_count <= data_to_out_word_counter;
     end

   assign out_word_count_zero = (output_word_count == 4'h0);




   assign data_to_user_word_counter = (user_word_ct_sel) ?  decremented_user_word_count : count_data_in;
   assign decremented_user_word_count = user_word_count - 4'h1;

   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)                 user_word_count <= 4'h0;
	else if(user_word_ct_en)  user_word_count <= data_to_user_word_counter;
     end

   assign user_word_count_zero = (user_word_count == 4'h0);
    



   assign out_reg_data = (out_reg_data_sel) ? count_data_from_biu : data_from_biu;

   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) data_out_shift_reg <= 8'h0;
	else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data;
	else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[7:1]};
     end

   assign module_tdo_o = data_out_shift_reg[0];
   






   adbg_jsp_biu jsp_biu_i (

			   .tck_i           (tck_i),
			   .rst_i           (rst_i),
			   .data_i          (data_to_biu),
			   .data_o          (data_from_biu),
			   .bytes_available_o (biu_bytes_available),
			   .bytes_free_o    (biu_space_available),
			   .rd_strobe_i     (biu_rd_strobe),
			   .wr_strobe_i     (biu_wr_strobe),
			   

			   .wb_clk_i        (wb_clk_i),
			   .wb_rst_i        (wb_rst_i),
			   .wb_adr_i        (wb_adr_i),
			   .wb_dat_o        (wb_dat_o),
			   .wb_dat_i        (wb_dat_i),
			   .wb_cyc_i        (wb_cyc_i),
			   .wb_stb_i        (wb_stb_i),
			   .wb_sel_i        (wb_sel_i),
			   .wb_we_i         (wb_we_i),
			   .wb_ack_o        (wb_ack_o),
			   .wb_cab_i        (wb_cab_i),
			   .wb_err_o        (wb_err_o),
			   .wb_cti_i        (wb_cti_i),
			   .wb_bte_i        (wb_bte_i),
			   .int_o           (int_o)
			   );









`define STATE_wr_idle     3'h0
`define STATE_wr_wait     3'h1
`define STATE_wr_counts   3'h2
`define STATE_wr_xfer     3'h3

   reg [2:0] wr_module_state;
   reg [2:0] wr_module_next_state;



   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  wr_module_state <= `STATE_wr_idle;
	else
	  wr_module_state <= wr_module_next_state;
     end



   always @ (wr_module_state or module_select_i or update_dr_i or capture_dr_i 
	     or shift_dr_i or wr_bit_count_max or tdi_i)
     begin
	case(wr_module_state)
	  `STATE_wr_idle:
	    begin
`ifdef ADBG_JSP_SUPPORT_MULTI
	       if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_wait;
`else
	       if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_counts;
`endif
	       else wr_module_next_state <= `STATE_wr_idle;
	    end
	   `STATE_wr_wait:
	   begin 
	     	 if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
	    	  else if(module_select_i && tdi_i) wr_module_next_state <= `STATE_wr_counts;
	       else wr_module_next_state <= `STATE_wr_wait;
	   end
	  `STATE_wr_counts:
	    begin
	       if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
	       else if(wr_bit_count_max) wr_module_next_state <= `STATE_wr_xfer;
	       else wr_module_next_state <= `STATE_wr_counts;
	    end

	  `STATE_wr_xfer:
	    begin
	       if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
	       else wr_module_next_state <= `STATE_wr_xfer;
	    end
	  
	  default: wr_module_next_state <= `STATE_wr_idle;
	endcase
     end
   


   always @ (wr_module_state or wr_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
	     or in_word_count_zero or out_word_count_zero or wr_bit_count_max or decremented_in_word_count
	     or decremented_out_word_count or user_word_count_zero)
     begin

	wr_bit_ct_en <= 1'b0;
	wr_bit_ct_rst <= 1'b0;
	in_word_ct_sel <= 1'b0;
	user_word_ct_sel <= 1'b0;
	in_word_ct_en <= 1'b0;
	user_word_ct_en <= 1'b0;
	biu_wr_strobe <= 1'b0;
	
	case(wr_module_state)
	  `STATE_wr_idle:
	    begin
	       in_word_ct_sel <= 1'b0;
	       

	       if(wr_module_next_state != `STATE_wr_idle) begin
		  wr_bit_ct_rst <= 1'b1;
		  in_word_ct_en <= 1'b1;
	       end
	    end


	  `STATE_wr_wait:
	    begin
	       wr_bit_ct_en <= 1'b0;
	    end

	  `STATE_wr_counts:
	    begin
	       if(shift_dr_i) begin
		  wr_bit_ct_en <= 1'b1;
		  user_word_ct_sel <= 1'b0;
		  
		  if(wr_bit_count_max) begin
		     wr_bit_ct_rst <= 1'b1;
		     user_word_ct_en <= 1'b1;
		  end
	       end
	    end
    
	  `STATE_wr_xfer:
	    begin
	       if(shift_dr_i) begin
		  wr_bit_ct_en <= 1'b1;
		  in_word_ct_sel <= 1'b1;
		  user_word_ct_sel <= 1'b1;
	       
		  if(wr_bit_count_max) begin
		     wr_bit_ct_rst <= 1'b1;
		  
		     if(!(in_word_count_zero || user_word_count_zero)) begin
			biu_wr_strobe <= 1'b1;
			in_word_ct_en <= 1'b1;
			user_word_ct_en <= 1'b1;
		     end

		  end
	       end
	    end

	  default: ;
	endcase
     end








`define STATE_rd_idle     4'h0
`define STATE_rd_counts   4'h1
`define STATE_rd_rdack   4'h2
`define STATE_rd_xfer  4'h3





   reg [2:0] rd_module_state;
   reg [2:0] rd_module_next_state;



   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  rd_module_state <= `STATE_rd_idle;
	else
	  rd_module_state <= rd_module_next_state;
     end



   always @ (rd_module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or rd_bit_count_max)
     begin
	case(rd_module_state)
	  `STATE_rd_idle:
	    begin
	       if(module_select_i && capture_dr_i) rd_module_next_state <= `STATE_rd_counts;
	       else rd_module_next_state <= `STATE_rd_idle;
	    end
	  `STATE_rd_counts:
	    begin
	       if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
	       else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
	       else rd_module_next_state <= `STATE_rd_counts;
	    end
	  `STATE_rd_rdack:
	    begin
               if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
               else rd_module_next_state <= `STATE_rd_xfer;
	    end
	  `STATE_rd_xfer:
	    begin
	       if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
	       else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
	       else rd_module_next_state <= `STATE_rd_xfer;
	    end
	  
	  default: rd_module_next_state <= `STATE_rd_idle;
	endcase
     end
   


   always @ (rd_module_state or rd_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
	     or in_word_count_zero or out_word_count_zero or rd_bit_count_max or decremented_in_word_count
	     or decremented_out_word_count)
     begin

	rd_bit_ct_en <= 1'b0;
	rd_bit_ct_rst <= 1'b0;
	out_word_ct_sel <= 1'b0;
	out_word_ct_en <= 1'b0;
	out_reg_ld_en <= 1'b0;
	out_reg_shift_en <= 1'b0;
	out_reg_data_sel <= 1'b0;
	biu_rd_strobe <= 1'b0;
	
	case(rd_module_state)
	  `STATE_rd_idle:
	    begin
	       out_reg_data_sel <= 1'b1;
	       out_word_ct_sel <= 1'b0;
	       

	       if(rd_module_next_state != `STATE_rd_idle) begin
		  out_reg_ld_en <= 1'b1;
		  rd_bit_ct_rst <= 1'b1;
		  out_word_ct_en <= 1'b1;
	       end
	    end

	  `STATE_rd_counts:
	    begin
	       if(shift_dr_i) begin
		  rd_bit_ct_en <= 1'b1;
		  out_reg_shift_en <= 1'b1;
		  
		  if(rd_bit_count_max) begin
		     rd_bit_ct_rst <= 1'b1;
		     

		     if(!out_word_count_zero) begin
			out_reg_ld_en <= 1'b1;
			out_reg_shift_en <= 1'b0;
		     end
		  end
	       end
	    end
 
	  `STATE_rd_rdack:
	    begin
	       if(shift_dr_i) begin
		  rd_bit_ct_en <= 1'b1;
		  out_reg_shift_en <= 1'b1;
		  out_reg_data_sel <= 1'b0;
      

      
		  if(!out_word_count_zero) begin
		     biu_rd_strobe <= 1'b1;
		  end
	       end
	    end
    
	  `STATE_rd_xfer:
	    begin
	       if(shift_dr_i) begin
		  rd_bit_ct_en <= 1'b1;
		  out_word_ct_sel <= 1'b1;
		  out_reg_shift_en <= 1'b1;
		  out_reg_data_sel <= 1'b0;
	       
		  if(rd_bit_count_max) begin
		     rd_bit_ct_rst <= 1'b1;


		     if(!out_word_count_zero) begin
			out_reg_ld_en <= 1'b1;
			out_reg_shift_en <= 1'b0;
			out_word_ct_en <= 1'b1;
		     end
		  end
	       end
	    end

	  default: ;
	endcase
     end


endmodule