data/full_repos/permissive/165697764/red_pitaya_dsp.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/165697764/red_pitaya_dsp.v:347: Signal definition not found, creating implicitly: \'dat_b_saturated\'\n                                                                            : ... Suggested alternative: \'dac_b_saturated\'\n   20\'h08 : begin sys_ack <= sys_en;          sys_rdata <= {{32- 2{1\'b0}},dat_b_saturated,dac_a_saturated}; end\n                                                                          ^~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/165697764/red_pitaya_dsp.v:279: Cannot find file containing module: \'red_pitaya_saturate\'\nred_pitaya_saturate #(\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165697764,data/full_repos/permissive/165697764/red_pitaya_saturate\n             data/full_repos/permissive/165697764,data/full_repos/permissive/165697764/red_pitaya_saturate.v\n             data/full_repos/permissive/165697764,data/full_repos/permissive/165697764/red_pitaya_saturate.sv\n             red_pitaya_saturate\n             red_pitaya_saturate.v\n             red_pitaya_saturate.sv\n             obj_dir/red_pitaya_saturate\n             obj_dir/red_pitaya_saturate.v\n             obj_dir/red_pitaya_saturate.sv\n%Warning-WIDTH: data/full_repos/permissive/165697764/red_pitaya_dsp.v:351: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                         : ... In instance red_pitaya_dsp\n     default : begin sys_ack <= module_ack[sys_addr[16+LOG_MODULES-1:16]];    sys_rdata <=  module_rdata[sys_addr[16+LOG_MODULES-1:16]]  ; end\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/165697764/red_pitaya_dsp.v:351: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                         : ... In instance red_pitaya_dsp\n     default : begin sys_ack <= module_ack[sys_addr[16+LOG_MODULES-1:16]];    sys_rdata <=  module_rdata[sys_addr[16+LOG_MODULES-1:16]]  ; end\n                                                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/165697764/red_pitaya_dsp.v:344: Operator CASE expects 20 bits on the Case expression, but Case expression\'s SEL generates 16 bits.\n                                                                         : ... In instance red_pitaya_dsp\n   casez (sys_addr[16-1:0])\n   ^~~~~\n%Error: data/full_repos/permissive/165697764/red_pitaya_dsp.v:371: Cannot find file containing module: \'red_pitaya_pid_block\'\n   red_pitaya_pid_block i_pid (\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/165697764/red_pitaya_dsp.v:396: Cannot find file containing module: \'red_pitaya_trigger_block\'\n   red_pitaya_trigger_block i_trigger (\n   ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/165697764/red_pitaya_dsp.v:420: Cannot find file containing module: \'red_pitaya_iir_block\'\n    red_pitaya_iir_block iir (\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/165697764/red_pitaya_dsp.v:441: Cannot find file containing module: \'red_pitaya_iq_block\'\n    red_pitaya_iq_block\n    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/165697764/red_pitaya_dsp.v:468: Cannot find file containing module: \'red_pitaya_iq_block\'\n    red_pitaya_iq_block   #( .QUADRATUREFILTERSTAGES(4) )\n    ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 4 warning(s)\n'
module red_pitaya_dsp #(
	parameter MODULES = 8
)
(

   input                 clk_i           ,
   input                 rstn_i          ,
   input      [ 14-1: 0] dat_a_i         ,
   input      [ 14-1: 0] dat_b_i         ,
   output     [ 14-1: 0] dat_a_o         ,
   output     [ 14-1: 0] dat_b_o         ,

   output     [ 14-1: 0] scope1_o,
   output     [ 14-1: 0] scope2_o,
   input      [ 14-1: 0] asg1_i,
   input      [ 14-1: 0] asg2_i,
   input      [ 14-1: 0] asg1phase_i,


   output     [ 14-1: 0] pwm0,
   output     [ 14-1: 0] pwm1,
   output     [ 14-1: 0] pwm2,
   output     [ 14-1: 0] pwm3,


   output                trig_o,





	 output 		[14-1: 0]	iq0_sineout,
	 output 		[14-1: 0]	iq1_sineout,
	 output 		[14-1: 0]	iq2_sineout,






   input      [ 32-1: 0] sys_addr        ,
   input      [ 32-1: 0] sys_wdata       ,
   input      [  4-1: 0] sys_sel         ,
   input                 sys_wen         ,
   input                 sys_ren         ,
   output reg [ 32-1: 0] sys_rdata   ,
   output reg            sys_err         ,
   output reg            sys_ack
);

localparam EXTRAMODULES = 2;
localparam EXTRAINPUTS = 4;
localparam EXTRAOUTPUTS = 2;
localparam LOG_MODULES = 4;


localparam PID0  = 'd0;
localparam PID1  = 'd1;
localparam PID2  = 'd2;
localparam PID3  = 'd3;
localparam TRIG  = 'd3;
localparam IIR   = 'd4;
localparam IQ0   = 'd5;
localparam IQ1   = 'd6;
localparam IQ2   = 'd7;

localparam NONE = 2**LOG_MODULES-1;


localparam ASG1   = MODULES;
localparam ASG2   = MODULES+1;
localparam SCOPE1 = MODULES;
localparam SCOPE2 = MODULES+1;

localparam ADC1  = MODULES+2;
localparam ADC2  = MODULES+3;
localparam DAC1  = MODULES+4;
localparam DAC2  = MODULES+5;

localparam PWM0  = MODULES+2;
localparam PWM1  = MODULES+3;
localparam PWM3  = MODULES+4;
localparam PWM4  = MODULES+5;


localparam BOTH = 2'b11;
localparam OUT1 = 2'b01;
localparam OUT2 = 2'b10;
localparam OFF  = 2'b00;




wire [14-1:0] input_signal [MODULES+EXTRAMODULES+EXTRAOUTPUTS-1:0];

reg [LOG_MODULES-1:0] input_select [MODULES+EXTRAMODULES+EXTRAOUTPUTS-1:0];


wire [14-1:0] output_signal [MODULES+EXTRAMODULES+EXTRAINPUTS-1+1:0];


wire [14-1:0] output_direct [MODULES+EXTRAMODULES-1:0];

reg [2-1:0] output_select [MODULES+EXTRAMODULES-1:0];


reg [MODULES-1:0] sync;


wire [ 32-1: 0] module_rdata [MODULES-1:0];
wire            module_ack   [MODULES-1:0];





assign iq0_sineout = output_direct[5];
assign iq1_sineout = output_direct[6];
assign iq2_sineout = output_direct[7];


wire signed		[14-1:0]		iq0_output;
wire signed		[14-1:0]		iq1_output;

assign iq0_output = output_signal[5];
assign iq1_output = output_signal[6];


reg signed 		[15-1:0]	tempoutp;
reg signed		[15-1:0]	tempoutm;

always @(posedge clk_i) begin
		if (rstn_i == 1'b0) begin
				tempoutp <= 15'b0;
				tempoutm <= 15'b0;
		end
		else begin
				tempoutp <= iq0_output + iq1_output;
				tempoutm <= iq0_output - iq1_output;
		end
end

assign output_signal[7]  = tempoutp[15-1:1];
assign output_signal[14] = tempoutm[15-1:1];







assign scope1_o = input_signal[SCOPE1];
assign scope2_o = input_signal[SCOPE2];


assign output_signal[ASG1] = asg1_i;
assign output_signal[ASG2] = asg2_i;
assign output_direct[ASG1] = asg1_i;
assign output_direct[ASG2] = asg2_i;


assign output_signal[ADC1] = dat_a_i;
assign output_signal[ADC2] = dat_b_i;
assign output_signal[DAC1] = dat_a_o;
assign output_signal[DAC2] = dat_b_o;


assign pwm0 = (input_select[PWM0] == NONE) ? 14'h0 : output_signal[input_select[PWM0]];
assign pwm1 = (input_select[PWM1] == NONE) ? 14'h0 : output_signal[input_select[PWM1]];
assign pwm2 = 14'b0;
assign pwm3 = 14'b0;

reg  signed [   14+LOG_MODULES-1: 0] sum1;
reg  signed [   14+LOG_MODULES-1: 0] sum2;

wire dac_a_saturated;
wire dac_b_saturated;

integer i;
genvar j;


generate for (j = 0; j < MODULES+EXTRAMODULES; j = j+1)
   assign input_signal[j] = (input_select[j]==NONE) ? 14'b0 : output_signal[input_select[j]];
endgenerate









localparam CHANNELS = 2**LOG_MODULES;
reg  signed [   14+LOG_MODULES-1: 0] presum1 [CHANNELS-1-1:0];
reg  signed [   14+LOG_MODULES-1: 0] presum2 [CHANNELS-1-1:0];

always @(posedge clk_i) begin
   if (rstn_i == 1'b0) begin
     for (i=0;i<CHANNELS;i=i+1) begin
        presum1[i] <= {14+LOG_MODULES{1'b0}};
        presum2[i] <= {14+LOG_MODULES{1'b0}};
     end
     sum1 <= {14+LOG_MODULES{1'b0}};
     sum2 <= {14+LOG_MODULES{1'b0}};
   end
   else begin

     for (i=0;i<(MODULES+EXTRAMODULES)/2;i=i+1) begin
        presum1[i] <= ({14+LOG_MODULES{(|(output_select[2*i]&OUT1))}} & {{LOG_MODULES{output_direct[2*i][14-1]}},output_direct[2*i]}) + ({14+LOG_MODULES{(|(output_select[2*i+1]&OUT1))}} & {{LOG_MODULES{output_direct[2*i+1][14-1]}},output_direct[2*i+1]});
        presum2[i] <= ({14+LOG_MODULES{(|(output_select[2*i]&OUT2))}} & {{LOG_MODULES{output_direct[2*i][14-1]}},output_direct[2*i]}) + ({14+LOG_MODULES{(|(output_select[2*i+1]&OUT2))}} & {{LOG_MODULES{output_direct[2*i+1][14-1]}},output_direct[2*i+1]});
     end

     for (i=0;i<CHANNELS/2-1;i=i+1) begin
        presum1[8+i] <= presum1[2*i]+presum1[2*i+1];
        presum2[8+i] <= presum2[2*i]+presum2[2*i+1];
     end

     sum1 <= presum1[CHANNELS-1-1];
     sum2 <= presum2[CHANNELS-1-1];
   end
end


red_pitaya_saturate #(
    .BITS_IN (14+LOG_MODULES),
    .SHIFT(0),
    .BITS_OUT(14)
    ) dac_saturate [1:0] (
   .input_i({sum2,sum1}),
   .output_o({dat_b_o,dat_a_o}),
   .overflow ({dat_b_saturated,dac_a_saturated})
   );


always @(posedge clk_i) begin
   if (rstn_i == 1'b0) begin

      input_select [PID0] <= ADC1;
      output_select[PID0] <= OFF;

      input_select [PID1] <= ADC1;
      output_select[PID1] <= OFF;

      input_select [PID2] <= ADC1;
      output_select[PID2] <= OFF;

      input_select [PID3] <= ADC1;
      output_select[PID3] <= OFF;

      input_select [IIR] <= ADC1;
      output_select[IIR] <= OFF;

      input_select [IQ0] <= ADC1;
      output_select[IQ0] <= OFF;

      input_select [IQ1] <= ADC1;
      output_select[IQ1] <= OFF;

      input_select [IQ2] <= ADC1;
      output_select[IQ2] <= OFF;

      input_select [SCOPE1] <= ADC1;
      input_select [SCOPE2] <= ADC2;
      output_select[ASG1] <= OFF;
      output_select[ASG2] <= OFF;

      input_select [PWM0] <= NONE;
      input_select [PWM1] <= NONE;

      sync <= {MODULES{1'b1}} ;
   end
   else begin
      if (sys_wen) begin
         if (sys_addr[16-1:0]==16'h00)     input_select[sys_addr[16+LOG_MODULES-1:16]] <= sys_wdata[ LOG_MODULES-1:0];
         if (sys_addr[16-1:0]==16'h04)    output_select[sys_addr[16+LOG_MODULES-1:16]] <= sys_wdata[ 2-1:0];
         if (sys_addr[16-1:0]==16'h0C)                                            sync <= sys_wdata[MODULES-1:0];
      end
   end
end

wire sys_en;
assign sys_en = sys_wen | sys_ren;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
   sys_err <= 1'b0 ;
   sys_ack <= 1'b0 ;
end else begin
   sys_err <= 1'b0 ;
   casez (sys_addr[16-1:0])
      20'h00 : begin sys_ack <= sys_en;          sys_rdata <= {{32- LOG_MODULES{1'b0}},input_select[sys_addr[16+LOG_MODULES-1:16]]}; end
	  20'h04 : begin sys_ack <= sys_en;          sys_rdata <= {{32- 2{1'b0}},output_select[sys_addr[16+LOG_MODULES-1:16]]}; end
	  20'h08 : begin sys_ack <= sys_en;          sys_rdata <= {{32- 2{1'b0}},dat_b_saturated,dac_a_saturated}; end
	  20'h0C : begin sys_ack <= sys_en;          sys_rdata <= {{32-MODULES{1'b0}},sync} ; end
      20'h10 : begin sys_ack <= sys_en;          sys_rdata <= {{32- 14{1'b0}},output_signal[sys_addr[16+LOG_MODULES-1:16]]} ; end

     default : begin sys_ack <= module_ack[sys_addr[16+LOG_MODULES-1:16]];    sys_rdata <=  module_rdata[sys_addr[16+LOG_MODULES-1:16]]  ; end
   endcase
end






wire [14-1:0] diff_input_signal [3-1:0];
wire [14-1:0] diff_output_signal [3-1:0];


assign diff_input_signal[0] = diff_output_signal[1];
assign diff_input_signal[1] = diff_output_signal[0];
assign diff_input_signal[2] = {14{1'b0}};

generate for (j = 0; j < 3; j = j+1) begin
   red_pitaya_pid_block i_pid (

     .clk_i        (  clk_i          ),
     .rstn_i       (  rstn_i         ),
     .sync_i       (  sync[j]        ),
     .dat_i        (  input_signal [j] ),
     .dat_o        (  output_direct[j]),
	 .diff_dat_i   (  diff_input_signal[j] ),
	 .diff_dat_o   (  diff_output_signal[j] ),


	 .addr ( sys_addr[16-1:0] ),
	 .wen  ( sys_wen & (sys_addr[20-1:16]==j) ),
	 .ren  ( sys_ren & (sys_addr[20-1:16]==j) ),
	 .ack  ( module_ack[j] ),
	 .rdata (module_rdata[j]),
     .wdata (sys_wdata)
   );
   assign output_signal[j] = output_direct[j];
end
endgenerate

wire trig_signal;

generate for (j = 3; j < 4; j = j+1) begin
   red_pitaya_trigger_block i_trigger (

     .clk_i        (  clk_i          ),
     .rstn_i       (  rstn_i         ),
     .dat_i        (  input_signal [j] ),
     .dat_o        (  output_direct[j]),
     .signal_o     (  output_signal[j]),
     .phase1_i     (  asg1phase_i ),
     .trig_o       (  trig_signal ),


	 .addr ( sys_addr[16-1:0] ),
	 .wen  ( sys_wen & (sys_addr[20-1:16]==j) ),
	 .ren  ( sys_ren & (sys_addr[20-1:16]==j) ),
	 .ack  ( module_ack[j] ),
	 .rdata (module_rdata[j]),
     .wdata (sys_wdata)
   );
end
endgenerate
assign trig_o = trig_signal;


generate for (j = 4; j < 5; j = j+1) begin
    red_pitaya_iir_block iir (

	     .clk_i        (  clk_i          ),
	     .rstn_i       (  rstn_i         ),
	     .dat_i        (  input_signal [j] ),
	     .dat_o        (  output_direct[j]),


		 .addr ( sys_addr[16-1:0] ),
		 .wen  ( sys_wen & (sys_addr[20-1:16]==j) ),
		 .ren  ( sys_ren & (sys_addr[20-1:16]==j) ),
		 .ack  ( module_ack[j] ),
		 .rdata (module_rdata[j]),
	     .wdata (sys_wdata)
      );
	  assign output_signal[j] = output_direct[j];
end endgenerate



generate for (j = 5; j < 7; j = j+1) begin
    red_pitaya_iq_block
      iq
      (

	     .clk_i        (  clk_i          ),
	     .rstn_i       (  rstn_i         ),
         .sync_i       (  sync[j]        ),
	     .dat_i        (  input_signal [j] ),
	     .dat_o        (  output_direct[j]),
		 .signal_o     (  output_signal[j]),






		 .addr ( sys_addr[16-1:0] ),
		 .wen  ( sys_wen & (sys_addr[20-1:16]==j) ),
		 .ren  ( sys_ren & (sys_addr[20-1:16]==j) ),
		 .ack  ( module_ack[j] ),
		 .rdata (module_rdata[j]),
	     .wdata (sys_wdata)
      );
end endgenerate


generate for (j = 7; j < 8; j = j+1) begin
    red_pitaya_iq_block   #( .QUADRATUREFILTERSTAGES(4) )
      iq_2_outputs
      (

         .clk_i        (  clk_i          ),
         .rstn_i       (  rstn_i         ),
         .sync_i       (  sync[j]        ),
         .dat_i        (  input_signal [j] ),
         .dat_o        (  output_direct[j]),





         .signal_o     (  								),
         .signal2_o    (  								),






         .addr ( sys_addr[16-1:0] ),
         .wen  ( sys_wen & (sys_addr[20-1:16]==j) ),
         .ren  ( sys_ren & (sys_addr[20-1:16]==j) ),
         .ack  ( module_ack[j] ),
         .rdata (module_rdata[j]),
         .wdata (sys_wdata)
      );
end endgenerate

endmodule
module red_pitaya_dsp #(
	parameter MODULES = 8
)
(

   input                 clk_i           ,
   input                 rstn_i          ,
   input      [ 14-1: 0] dat_a_i         ,
   input      [ 14-1: 0] dat_b_i         ,
   output     [ 14-1: 0] dat_a_o         ,
   output     [ 14-1: 0] dat_b_o         ,

   output     [ 14-1: 0] scope1_o,
   output     [ 14-1: 0] scope2_o,
   input      [ 14-1: 0] asg1_i,
   input      [ 14-1: 0] asg2_i,
   input      [ 14-1: 0] asg1phase_i,


   output     [ 14-1: 0] pwm0,
   output     [ 14-1: 0] pwm1,
   output     [ 14-1: 0] pwm2,
   output     [ 14-1: 0] pwm3,


   output                trig_o,





	 output 		[14-1: 0]	iq0_sineout,
	 output 		[14-1: 0]	iq1_sineout,
	 output 		[14-1: 0]	iq2_sineout,






   input      [ 32-1: 0] sys_addr        ,
   input      [ 32-1: 0] sys_wdata       ,
   input      [  4-1: 0] sys_sel         ,
   input                 sys_wen         ,
   input                 sys_ren         ,
   output reg [ 32-1: 0] sys_rdata   ,
   output reg            sys_err         ,
   output reg            sys_ack
);


localparam EXTRAMODULES = 2;
localparam EXTRAINPUTS = 4;
localparam EXTRAOUTPUTS = 2;
localparam LOG_MODULES = 4;


localparam PID0  = 'd0;
localparam PID1  = 'd1;
localparam PID2  = 'd2;
localparam PID3  = 'd3;
localparam TRIG  = 'd3;
localparam IIR   = 'd4;
localparam IQ0   = 'd5;
localparam IQ1   = 'd6;
localparam IQ2   = 'd7;

localparam NONE = 2**LOG_MODULES-1;


localparam ASG1   = MODULES;
localparam ASG2   = MODULES+1;
localparam SCOPE1 = MODULES;
localparam SCOPE2 = MODULES+1;

localparam ADC1  = MODULES+2;
localparam ADC2  = MODULES+3;
localparam DAC1  = MODULES+4;
localparam DAC2  = MODULES+5;

localparam PWM0  = MODULES+2;
localparam PWM1  = MODULES+3;
localparam PWM3  = MODULES+4;
localparam PWM4  = MODULES+5;


localparam BOTH = 2'b11;
localparam OUT1 = 2'b01;
localparam OUT2 = 2'b10;
localparam OFF  = 2'b00;




wire [14-1:0] input_signal [MODULES+EXTRAMODULES+EXTRAOUTPUTS-1:0];

reg [LOG_MODULES-1:0] input_select [MODULES+EXTRAMODULES+EXTRAOUTPUTS-1:0];


wire [14-1:0] output_signal [MODULES+EXTRAMODULES+EXTRAINPUTS-1+1:0];


wire [14-1:0] output_direct [MODULES+EXTRAMODULES-1:0];

reg [2-1:0] output_select [MODULES+EXTRAMODULES-1:0];


reg [MODULES-1:0] sync;


wire [ 32-1: 0] module_rdata [MODULES-1:0];
wire            module_ack   [MODULES-1:0];





assign iq0_sineout = output_direct[5];
assign iq1_sineout = output_direct[6];
assign iq2_sineout = output_direct[7];


wire signed		[14-1:0]		iq0_output;
wire signed		[14-1:0]		iq1_output;

assign iq0_output = output_signal[5];
assign iq1_output = output_signal[6];


reg signed 		[15-1:0]	tempoutp;
reg signed		[15-1:0]	tempoutm;

always @(posedge clk_i) begin
		if (rstn_i == 1'b0) begin
				tempoutp <= 15'b0;
				tempoutm <= 15'b0;
		end
		else begin
				tempoutp <= iq0_output + iq1_output;
				tempoutm <= iq0_output - iq1_output;
		end
end

assign output_signal[7]  = tempoutp[15-1:1];
assign output_signal[14] = tempoutm[15-1:1];







assign scope1_o = input_signal[SCOPE1];
assign scope2_o = input_signal[SCOPE2];


assign output_signal[ASG1] = asg1_i;
assign output_signal[ASG2] = asg2_i;
assign output_direct[ASG1] = asg1_i;
assign output_direct[ASG2] = asg2_i;


assign output_signal[ADC1] = dat_a_i;
assign output_signal[ADC2] = dat_b_i;
assign output_signal[DAC1] = dat_a_o;
assign output_signal[DAC2] = dat_b_o;


assign pwm0 = (input_select[PWM0] == NONE) ? 14'h0 : output_signal[input_select[PWM0]];
assign pwm1 = (input_select[PWM1] == NONE) ? 14'h0 : output_signal[input_select[PWM1]];
assign pwm2 = 14'b0;
assign pwm3 = 14'b0;

reg  signed [   14+LOG_MODULES-1: 0] sum1;
reg  signed [   14+LOG_MODULES-1: 0] sum2;

wire dac_a_saturated;
wire dac_b_saturated;

integer i;
genvar j;


generate for (j = 0; j < MODULES+EXTRAMODULES; j = j+1)
   assign input_signal[j] = (input_select[j]==NONE) ? 14'b0 : output_signal[input_select[j]];
endgenerate









localparam CHANNELS = 2**LOG_MODULES;
reg  signed [   14+LOG_MODULES-1: 0] presum1 [CHANNELS-1-1:0];
reg  signed [   14+LOG_MODULES-1: 0] presum2 [CHANNELS-1-1:0];

always @(posedge clk_i) begin
   if (rstn_i == 1'b0) begin
     for (i=0;i<CHANNELS;i=i+1) begin
        presum1[i] <= {14+LOG_MODULES{1'b0}};
        presum2[i] <= {14+LOG_MODULES{1'b0}};
     end
     sum1 <= {14+LOG_MODULES{1'b0}};
     sum2 <= {14+LOG_MODULES{1'b0}};
   end
   else begin

     for (i=0;i<(MODULES+EXTRAMODULES)/2;i=i+1) begin
        presum1[i] <= ({14+LOG_MODULES{(|(output_select[2*i]&OUT1))}} & {{LOG_MODULES{output_direct[2*i][14-1]}},output_direct[2*i]}) + ({14+LOG_MODULES{(|(output_select[2*i+1]&OUT1))}} & {{LOG_MODULES{output_direct[2*i+1][14-1]}},output_direct[2*i+1]});
        presum2[i] <= ({14+LOG_MODULES{(|(output_select[2*i]&OUT2))}} & {{LOG_MODULES{output_direct[2*i][14-1]}},output_direct[2*i]}) + ({14+LOG_MODULES{(|(output_select[2*i+1]&OUT2))}} & {{LOG_MODULES{output_direct[2*i+1][14-1]}},output_direct[2*i+1]});
     end

     for (i=0;i<CHANNELS/2-1;i=i+1) begin
        presum1[8+i] <= presum1[2*i]+presum1[2*i+1];
        presum2[8+i] <= presum2[2*i]+presum2[2*i+1];
     end

     sum1 <= presum1[CHANNELS-1-1];
     sum2 <= presum2[CHANNELS-1-1];
   end
end


red_pitaya_saturate #(
    .BITS_IN (14+LOG_MODULES),
    .SHIFT(0),
    .BITS_OUT(14)
    ) dac_saturate [1:0] (
   .input_i({sum2,sum1}),
   .output_o({dat_b_o,dat_a_o}),
   .overflow ({dat_b_saturated,dac_a_saturated})
   );


always @(posedge clk_i) begin
   if (rstn_i == 1'b0) begin

      input_select [PID0] <= ADC1;
      output_select[PID0] <= OFF;

      input_select [PID1] <= ADC1;
      output_select[PID1] <= OFF;

      input_select [PID2] <= ADC1;
      output_select[PID2] <= OFF;

      input_select [PID3] <= ADC1;
      output_select[PID3] <= OFF;

      input_select [IIR] <= ADC1;
      output_select[IIR] <= OFF;

      input_select [IQ0] <= ADC1;
      output_select[IQ0] <= OFF;

      input_select [IQ1] <= ADC1;
      output_select[IQ1] <= OFF;

      input_select [IQ2] <= ADC1;
      output_select[IQ2] <= OFF;

      input_select [SCOPE1] <= ADC1;
      input_select [SCOPE2] <= ADC2;
      output_select[ASG1] <= OFF;
      output_select[ASG2] <= OFF;

      input_select [PWM0] <= NONE;
      input_select [PWM1] <= NONE;

      sync <= {MODULES{1'b1}} ;
   end
   else begin
      if (sys_wen) begin
         if (sys_addr[16-1:0]==16'h00)     input_select[sys_addr[16+LOG_MODULES-1:16]] <= sys_wdata[ LOG_MODULES-1:0];
         if (sys_addr[16-1:0]==16'h04)    output_select[sys_addr[16+LOG_MODULES-1:16]] <= sys_wdata[ 2-1:0];
         if (sys_addr[16-1:0]==16'h0C)                                            sync <= sys_wdata[MODULES-1:0];
      end
   end
end

wire sys_en;
assign sys_en = sys_wen | sys_ren;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
   sys_err <= 1'b0 ;
   sys_ack <= 1'b0 ;
end else begin
   sys_err <= 1'b0 ;
   casez (sys_addr[16-1:0])
      20'h00 : begin sys_ack <= sys_en;          sys_rdata <= {{32- LOG_MODULES{1'b0}},input_select[sys_addr[16+LOG_MODULES-1:16]]}; end
	  20'h04 : begin sys_ack <= sys_en;          sys_rdata <= {{32- 2{1'b0}},output_select[sys_addr[16+LOG_MODULES-1:16]]}; end
	  20'h08 : begin sys_ack <= sys_en;          sys_rdata <= {{32- 2{1'b0}},dat_b_saturated,dac_a_saturated}; end
	  20'h0C : begin sys_ack <= sys_en;          sys_rdata <= {{32-MODULES{1'b0}},sync} ; end
      20'h10 : begin sys_ack <= sys_en;          sys_rdata <= {{32- 14{1'b0}},output_signal[sys_addr[16+LOG_MODULES-1:16]]} ; end

     default : begin sys_ack <= module_ack[sys_addr[16+LOG_MODULES-1:16]];    sys_rdata <=  module_rdata[sys_addr[16+LOG_MODULES-1:16]]  ; end
   endcase
end






wire [14-1:0] diff_input_signal [3-1:0];
wire [14-1:0] diff_output_signal [3-1:0];


assign diff_input_signal[0] = diff_output_signal[1];
assign diff_input_signal[1] = diff_output_signal[0];
assign diff_input_signal[2] = {14{1'b0}};

generate for (j = 0; j < 3; j = j+1) begin
   red_pitaya_pid_block i_pid (

     .clk_i        (  clk_i          ),
     .rstn_i       (  rstn_i         ),
     .sync_i       (  sync[j]        ),
     .dat_i        (  input_signal [j] ),
     .dat_o        (  output_direct[j]),
	 .diff_dat_i   (  diff_input_signal[j] ),
	 .diff_dat_o   (  diff_output_signal[j] ),


	 .addr ( sys_addr[16-1:0] ),
	 .wen  ( sys_wen & (sys_addr[20-1:16]==j) ),
	 .ren  ( sys_ren & (sys_addr[20-1:16]==j) ),
	 .ack  ( module_ack[j] ),
	 .rdata (module_rdata[j]),
     .wdata (sys_wdata)
   );
   assign output_signal[j] = output_direct[j];
end
endgenerate

wire trig_signal;

generate for (j = 3; j < 4; j = j+1) begin
   red_pitaya_trigger_block i_trigger (

     .clk_i        (  clk_i          ),
     .rstn_i       (  rstn_i         ),
     .dat_i        (  input_signal [j] ),
     .dat_o        (  output_direct[j]),
     .signal_o     (  output_signal[j]),
     .phase1_i     (  asg1phase_i ),
     .trig_o       (  trig_signal ),


	 .addr ( sys_addr[16-1:0] ),
	 .wen  ( sys_wen & (sys_addr[20-1:16]==j) ),
	 .ren  ( sys_ren & (sys_addr[20-1:16]==j) ),
	 .ack  ( module_ack[j] ),
	 .rdata (module_rdata[j]),
     .wdata (sys_wdata)
   );
end
endgenerate
assign trig_o = trig_signal;


generate for (j = 4; j < 5; j = j+1) begin
    red_pitaya_iir_block iir (

	     .clk_i        (  clk_i          ),
	     .rstn_i       (  rstn_i         ),
	     .dat_i        (  input_signal [j] ),
	     .dat_o        (  output_direct[j]),


		 .addr ( sys_addr[16-1:0] ),
		 .wen  ( sys_wen & (sys_addr[20-1:16]==j) ),
		 .ren  ( sys_ren & (sys_addr[20-1:16]==j) ),
		 .ack  ( module_ack[j] ),
		 .rdata (module_rdata[j]),
	     .wdata (sys_wdata)
      );
	  assign output_signal[j] = output_direct[j];
end endgenerate



generate for (j = 5; j < 7; j = j+1) begin
    red_pitaya_iq_block
      iq
      (

	     .clk_i        (  clk_i          ),
	     .rstn_i       (  rstn_i         ),
         .sync_i       (  sync[j]        ),
	     .dat_i        (  input_signal [j] ),
	     .dat_o        (  output_direct[j]),
		 .signal_o     (  output_signal[j]),






		 .addr ( sys_addr[16-1:0] ),
		 .wen  ( sys_wen & (sys_addr[20-1:16]==j) ),
		 .ren  ( sys_ren & (sys_addr[20-1:16]==j) ),
		 .ack  ( module_ack[j] ),
		 .rdata (module_rdata[j]),
	     .wdata (sys_wdata)
      );
end endgenerate


generate for (j = 7; j < 8; j = j+1) begin
    red_pitaya_iq_block   #( .QUADRATUREFILTERSTAGES(4) )
      iq_2_outputs
      (

         .clk_i        (  clk_i          ),
         .rstn_i       (  rstn_i         ),
         .sync_i       (  sync[j]        ),
         .dat_i        (  input_signal [j] ),
         .dat_o        (  output_direct[j]),





         .signal_o     (  								),
         .signal2_o    (  								),






         .addr ( sys_addr[16-1:0] ),
         .wen  ( sys_wen & (sys_addr[20-1:16]==j) ),
         .ren  ( sys_ren & (sys_addr[20-1:16]==j) ),
         .ack  ( module_ack[j] ),
         .rdata (module_rdata[j]),
         .wdata (sys_wdata)
      );
end endgenerate

endmodule