data/full_repos/permissive/188595972/src/module.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/188595972/src/module.v:22: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'SerialSender\'\nmodule SerialSender(data,e,clk,rst_n,out,aviliable);\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'SerialReceiver\'\nmodule SerialReceiver(in,rst,clk,rst_n,data,inputValid,receiving_n);\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/188595972/src/module.v:50: Cannot find file containing module: \'NegedgeDetector\'\n    NegedgeDetector nd(in,clk,rst_n,neg);\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188595972/src,data/full_repos/permissive/188595972/NegedgeDetector\n             data/full_repos/permissive/188595972/src,data/full_repos/permissive/188595972/NegedgeDetector.v\n             data/full_repos/permissive/188595972/src,data/full_repos/permissive/188595972/NegedgeDetector.sv\n             NegedgeDetector\n             NegedgeDetector.v\n             NegedgeDetector.sv\n             obj_dir/NegedgeDetector\n             obj_dir/NegedgeDetector.v\n             obj_dir/NegedgeDetector.sv\n%Error: data/full_repos/permissive/188595972/src/module.v:51: Cannot find file containing module: \'JK_FF\'\n    JK_FF jk(reliableInput,aviRst,clk,rst_n,inputValid);\n    ^~~~~\n%Error: data/full_repos/permissive/188595972/src/module.v:52: Cannot find file containing module: \'JK_FF\'\n    JK_FF jk2(neg,received,clk,rst_n,receiving);\n    ^~~~~\n%Error: data/full_repos/permissive/188595972/src/module.v:53: Cannot find file containing module: \'ShiftReg\'\n    ShiftReg sr(in,13\'hffff,half,receiving_n,clk,rst_n,Q,13\'hffff);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/188595972/src/module.v:54: Cannot find file containing module: \'SerialClockModule\'\n    SerialClockModule scm(receiving,clk,rst_n,,half);\n    ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188595972/src/module.v:13: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                    : ... In instance SerialSender\n    assign over=!Q[12:1];\n                ^\n%Error: data/full_repos/permissive/188595972/src/module.v:17: Cannot find file containing module: \'JK_FF\'\n    JK_FF jk(e,over,clk,rst_n,E);\n    ^~~~~\n%Error: data/full_repos/permissive/188595972/src/module.v:18: Cannot find file containing module: \'SerialClockModule\'\n    SerialClockModule scm(.e(E),.clk(clk),.rst_n(rst_n),.out(next));\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/188595972/src/module.v:19: Cannot find file containing module: \'ShiftReg\'\n    ShiftReg sr(1\'b0,frames,next,aviliable,clk,rst_n,Q,13\'h1);\n    ^~~~~~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n'
module SerialSender(data,e,clk,rst_n,out,aviliable);
    input [7:0]data;
    input e,clk,rst_n;
    output aviliable;
    output out;
    
    wire next;
    wire [12:0]frames;
    wire over,E;
    wire [12:0]Q;
    
    assign frames={2'b11,^data,data,2'b01};
    assign over=!Q[12:1];
    assign out=Q[0];
    assign aviliable=!E;
    
    JK_FF jk(e,over,clk,rst_n,E);
    SerialClockModule scm(.e(E),.clk(clk),.rst_n(rst_n),.out(next));
    ShiftReg sr(1'b0,frames,next,aviliable,clk,rst_n,Q,13'h1);
    endmodule
module SerialSender(data,e,clk,rst_n,out,aviliable);

    input [7:0]data;
    input e,clk,rst_n;
    output aviliable;
    output out;
    
    wire next;
    wire [12:0]frames;
    wire over,E;
    wire [12:0]Q;
    
    assign frames={2'b11,^data,data,2'b01};
    assign over=!Q[12:1];
    assign out=Q[0];
    assign aviliable=!E;
    
    JK_FF jk(e,over,clk,rst_n,E);
    SerialClockModule scm(.e(E),.clk(clk),.rst_n(rst_n),.out(next));
    ShiftReg sr(1'b0,frames,next,aviliable,clk,rst_n,Q,13'h1);
    endmodule