data/full_repos/permissive/172538466/hw/src/ahb_mux.v
None: at end of input
1: b'%Error: data/full_repos/permissive/172538466/hw/src/ahb_mux.v:1: Cannot find include file: defs.vh\n`include "defs.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.v\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.sv\n             defs.vh\n             defs.vh.v\n             defs.vh.sv\n             obj_dir/defs.vh\n             obj_dir/defs.vh.v\n             obj_dir/defs.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module ahb_mux
(
 input         HCLK_I,
 input         HRESET_N_I,


 input [2:0]   M_SEL_I,
 input [1:0]   M_HTRANS_I,
 input         M_HREADY_I,

 output        M_HREADY_O,
 output        M_HRESP_O,
 output [31:0] M_HRDATA_O,


 output [7:1]   S_SEL_O,
 input [7:1]   S_HREADY_I,
 input [7:1]   S_HRESP_I,

 input [31:0]  S1_HRDATA_I,
 input [31:0]  S2_HRDATA_I,
 input [31:0]  S3_HRDATA_I,
 input [31:0]  S4_HRDATA_I,
 input [31:0]  S5_HRDATA_I,
 input [31:0]  S6_HRDATA_I,
 input [31:0]  S7_HRDATA_I
 );


   reg         state;
   always @(posedge HCLK_I)
     if(!HRESET_N_I)
       state <= 0;
     else
       state <= M_HREADY_I & M_HTRANS_I[1];



   reg [2:0] sel_d;
   always @(posedge HCLK_I)
     if(!HRESET_N_I)
       sel_d <= 3'b000;
     else if(M_HREADY_I & M_HTRANS_I[1])
       sel_d <= M_SEL_I;



   assign M_HRDATA_O = (sel_d == 3'd1) ? S1_HRDATA_I :
                       (sel_d == 3'd2) ? S2_HRDATA_I :
                       (sel_d == 3'd3) ? S3_HRDATA_I :
                       (sel_d == 3'd4) ? S4_HRDATA_I :
                       (sel_d == 3'd5) ? S5_HRDATA_I :
                       (sel_d == 3'd6) ? S6_HRDATA_I :
                       (sel_d == 3'd7) ? S7_HRDATA_I :
                       32'dx;



   wire [7:0] mask = 8'h01 << M_SEL_I;
   wire [7:0] mask_d = 8'h01 << sel_d;

   assign S_SEL_O = mask[7:1];
   assign M_HREADY_O = ~state | |(mask_d[7:1] & S_HREADY_I);
   assign M_HRESP_O = |(~mask_d[7:1] & S_HRESP_I);
endmodule
module ahb_mux
(
 input         HCLK_I,
 input         HRESET_N_I,


 input [2:0]   M_SEL_I,
 input [1:0]   M_HTRANS_I,
 input         M_HREADY_I,

 output        M_HREADY_O,
 output        M_HRESP_O,
 output [31:0] M_HRDATA_O,


 output [7:1]   S_SEL_O,
 input [7:1]   S_HREADY_I,
 input [7:1]   S_HRESP_I,

 input [31:0]  S1_HRDATA_I,
 input [31:0]  S2_HRDATA_I,
 input [31:0]  S3_HRDATA_I,
 input [31:0]  S4_HRDATA_I,
 input [31:0]  S5_HRDATA_I,
 input [31:0]  S6_HRDATA_I,
 input [31:0]  S7_HRDATA_I
 );



   reg         state;
   always @(posedge HCLK_I)
     if(!HRESET_N_I)
       state <= 0;
     else
       state <= M_HREADY_I & M_HTRANS_I[1];



   reg [2:0] sel_d;
   always @(posedge HCLK_I)
     if(!HRESET_N_I)
       sel_d <= 3'b000;
     else if(M_HREADY_I & M_HTRANS_I[1])
       sel_d <= M_SEL_I;



   assign M_HRDATA_O = (sel_d == 3'd1) ? S1_HRDATA_I :
                       (sel_d == 3'd2) ? S2_HRDATA_I :
                       (sel_d == 3'd3) ? S3_HRDATA_I :
                       (sel_d == 3'd4) ? S4_HRDATA_I :
                       (sel_d == 3'd5) ? S5_HRDATA_I :
                       (sel_d == 3'd6) ? S6_HRDATA_I :
                       (sel_d == 3'd7) ? S7_HRDATA_I :
                       32'dx;



   wire [7:0] mask = 8'h01 << M_SEL_I;
   wire [7:0] mask_d = 8'h01 << sel_d;

   assign S_SEL_O = mask[7:1];
   assign M_HREADY_O = ~state | |(mask_d[7:1] & S_HREADY_I);
   assign M_HRESP_O = |(~mask_d[7:1] & S_HRESP_I);
endmodule