data/full_repos/permissive/187199324/stannel/Scheduler.v
1: b'%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:2: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:3: Cannot find include file: status.vh\n`include "status.vh" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:4: Cannot find include file: messages.vh\n`include "messages.vh" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:6: Define or directive not defined: \'`ADDRESS_BITS\'\nmodule Scheduler #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:6: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nmodule Scheduler #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                     ^\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:6: Define or directive not defined: \'`DATA_BITS\'\nmodule Scheduler #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:6: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule Scheduler #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                                                      ^\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                reset,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                enabled,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:11: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                 finished,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:13: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire                core0ReadyForDeschedule,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                core1ReadyForDeschedule,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                hasDeschedule,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [addrBits-1:0] deschedulePid,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                hasSchedule,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [addrBits-1:0] schedulePid,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                 core0Active,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg  [addrBits-1:0] core0Pid,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:24: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                 core1Active,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg  [addrBits-1:0] core1Pid,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                 core0NeedsResumeAwake,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                 core1NeedsResumeAwake,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:30: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire                canHalt\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:44: syntax error, unexpected IDENTIFIER\n  IceRam #(.addrBits(addrBits), .dataBits(dataBits)) schedulerListMemory(\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:54: Define or directive not defined: \'`CELL_COUNT\'\n  reg [`CELL_COUNT:0] rScheduleState;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:54: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  reg [`CELL_COUNT:0] rScheduleState;\n                  ^\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:77: syntax error, unexpected assign\n  assign canHalt = rScheduleState == 0;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:79: Define or directive not defined: \'`CELL_COUNT\'\n  reg [`CELL_COUNT:0] wNextScheduleState;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:79: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  reg [`CELL_COUNT:0] wNextScheduleState;\n                  ^\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:92: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:147: Define or directive not defined: \'`RAM_READ\'\n      wReadWriteMode      = `RAM_READ;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:179: Define or directive not defined: \'`CELL_COUNT\'\n            wNextScheduleState = rScheduleState & ({{`CELL_COUNT{1\'b1}}, 1\'b1} ^ (`CELL_COUNT_CONST_1 << deschedulePid[4:0]));\n                                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:179: Define or directive not defined: \'`CELL_COUNT_CONST_1\'\n            wNextScheduleState = rScheduleState & ({{`CELL_COUNT{1\'b1}}, 1\'b1} ^ (`CELL_COUNT_CONST_1 << deschedulePid[4:0]));\n                                                                                  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:196: Define or directive not defined: \'`RAM_WRITE\'\n            wReadWriteMode = `RAM_WRITE;\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:204: Define or directive not defined: \'`RAM_WRITE\'\n            wReadWriteMode    = `RAM_WRITE;\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Scheduler.v:228: Define or directive not defined: \'`CELL_COUNT_CONST_1\'\n            wNextScheduleState  = rScheduleState | (`CELL_COUNT_CONST_1 << dataOut[4:0]);\n                                                    ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 37 error(s)\n'
module Scheduler #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    input  wire                enabled,
    output reg                 finished,

    input  wire                core0ReadyForDeschedule,
    input  wire                core1ReadyForDeschedule,

    input  wire                hasDeschedule,
    input  wire [addrBits-1:0] deschedulePid,
    input  wire                hasSchedule,
    input  wire [addrBits-1:0] schedulePid,


    output reg                 core0Active,
    output reg  [addrBits-1:0] core0Pid,
    output reg                 core1Active,
    output reg  [addrBits-1:0] core1Pid,
    output reg                 core0NeedsResumeAwake,
    output reg                 core1NeedsResumeAwake,


    output wire                canHalt
  );



  reg  [addrBits-1:0] wAddress;
  reg  [dataBits-1:0] wDataIn;

  wire [dataBits-1:0] dataOut;

  reg                 wReadWriteMode;



  IceRam #(.addrBits(addrBits), .dataBits(dataBits)) schedulerListMemory(
    .clk           (clk),
    .address       (wAddress),
    .dataIn        (wDataIn),
    .dataOut       (dataOut),
    .readWriteMode (wReadWriteMode)
  );



  reg [`CELL_COUNT:0] rScheduleState;






  reg [addrBits-1:0] rFrontOfIndexList;
  reg [addrBits-1:0] rEndOfIndexList;

  reg [3:0] rState;

  localparam STATE_INIT                            = 4'd0;
  localparam STATE_DESCHEDULE_START                = 4'd1;
  localparam STATE_DESCHEDULE_WAIT                 = 4'd2;
  localparam STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_0 = 4'd3;
  localparam STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_1 = 4'd4;
  localparam STATE_SCHEDULE_INIT                   = 4'd5;
  localparam STATE_SCHEDULE_READ_NEXT              = 4'd6;




  assign canHalt = rScheduleState == 0;

  reg [`CELL_COUNT:0] wNextScheduleState;

  reg [3:0]          wNextState;
  reg                wFinished;
  reg                wDeactivateCore0;
  reg                wDeactivateCore1;
  reg                wIncrementListFront;
  reg                wIncrementListEnd;
  reg                wActivateCore0;
  reg [addrBits-1:0] wCore0NewPid;
  reg                wActivateCore1;
  reg [addrBits-1:0] wCore1NewPid;

  always @(posedge clk)
    begin
      if (!reset)
        begin
          rState            <= STATE_INIT;
          rScheduleState    <= 0;
          finished          <= 0;
          rFrontOfIndexList <= 0;
          rEndOfIndexList   <= 0;
          core0Active       <= 0;
          core0Pid          <= 0;
          core1Active       <= 0;
          core1Pid          <= 0;
        end
      else if (!enabled)
        begin
          rState                <= STATE_INIT;
          finished              <= 0;
          core0NeedsResumeAwake <= 0;
          core1NeedsResumeAwake <= 0;
        end
      else
        begin
          rState   <= wNextState;
          finished <= wFinished;
          rScheduleState <= wNextScheduleState;

          if (wDeactivateCore0)
            core0Active <= 0;
          else if (wActivateCore0)
            begin
              core0Active           <= 1;
              core0NeedsResumeAwake <= 1;
              core0Pid              <= wCore0NewPid;
            end

          if (wDeactivateCore1)
            core1Active <= 0;
          else if (wActivateCore1)
            begin
              core1Active           <= 1;
              core1NeedsResumeAwake <= 1;
              core1Pid              <= wCore1NewPid;
            end

          if (wIncrementListFront)
            rFrontOfIndexList <= rFrontOfIndexList + 1;
          if (wIncrementListEnd)
            rEndOfIndexList <= rEndOfIndexList + 1;
        end
    end


  always @(*)
    begin
      wReadWriteMode      = `RAM_READ;
      wAddress            = {addrBits{1'bx}};
      wDataIn             = {dataBits{1'bx}};
      wNextState          = rState;
      wFinished           = 0;
      wDeactivateCore0    = 0;
      wDeactivateCore1    = 0;
      wIncrementListFront = 0;
      wIncrementListEnd   = 0;
      wNextScheduleState  = rScheduleState;
      wActivateCore0      = 0;
      wActivateCore1      = 0;
      wCore0NewPid        = 0;
      wCore1NewPid        = 0;

      case (rState)
        STATE_INIT:
          begin
            if (hasDeschedule)
              wNextState = STATE_DESCHEDULE_START;
            else if (hasSchedule)
              wNextState = STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_0;
            else
              wNextState = STATE_SCHEDULE_INIT;
          end
        STATE_DESCHEDULE_START:
          begin
            if (core0Pid == deschedulePid)
              wDeactivateCore0 = 1;
            if (core1Pid == deschedulePid)
              wDeactivateCore1 = 1;
            wNextState = STATE_DESCHEDULE_WAIT;
            wNextScheduleState = rScheduleState & ({{`CELL_COUNT{1'b1}}, 1'b1} ^ (`CELL_COUNT_CONST_1 << deschedulePid[4:0]));
          end
        STATE_DESCHEDULE_WAIT:
          begin
            if (core0Pid == deschedulePid && !core0ReadyForDeschedule)
              wNextState = STATE_DESCHEDULE_WAIT;
            else if (core1Pid == deschedulePid && !core1ReadyForDeschedule)
              wNextState = STATE_DESCHEDULE_WAIT;
            else if (hasSchedule)
              wNextState = STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_0;
            else
              wNextState = STATE_SCHEDULE_INIT;
          end
        STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_0:
          begin
            wAddress       = rEndOfIndexList;
            wDataIn        = {8'b0, schedulePid};
            wReadWriteMode = `RAM_WRITE;
            wNextState     = STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_1;
          end
        STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_1:
          begin
            wIncrementListEnd = 1;
            wAddress          = rEndOfIndexList;
            wDataIn           = {8'b0, schedulePid};
            wReadWriteMode    = `RAM_WRITE;
            wNextState        = STATE_SCHEDULE_INIT;
          end
        STATE_SCHEDULE_INIT:
          begin
            wAddress = rFrontOfIndexList;
            if (rFrontOfIndexList == rEndOfIndexList)
              wFinished = 1;
            else if (!core0Active && !core0ReadyForDeschedule)
              wNextState = STATE_SCHEDULE_INIT;
            else if (!core1Active && !core1ReadyForDeschedule)
              wNextState = STATE_SCHEDULE_INIT;
            else if (!core0Active)
              wNextState = STATE_SCHEDULE_READ_NEXT;
            else if (!core1Active)
              wNextState = STATE_SCHEDULE_READ_NEXT;
            else
              wFinished = 1;
          end
        STATE_SCHEDULE_READ_NEXT:
          begin
            wAddress            = rFrontOfIndexList;
            wIncrementListFront = 1;
            wNextState          = STATE_SCHEDULE_INIT;
            wNextScheduleState  = rScheduleState | (`CELL_COUNT_CONST_1 << dataOut[4:0]);
            if (!core0Active)
              begin
                wActivateCore0 = 1;
                wCore0NewPid   = dataOut[7:0];
                wFinished      = core1Active;
              end
            else
              begin
                wActivateCore1 = 1;
                wCore1NewPid   = dataOut[7:0];
                wFinished      = 1;
              end
          end
        default:
          begin
          end
      endcase
    end

endmodule
module Scheduler #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    input  wire                enabled,
    output reg                 finished,

    input  wire                core0ReadyForDeschedule,
    input  wire                core1ReadyForDeschedule,

    input  wire                hasDeschedule,
    input  wire [addrBits-1:0] deschedulePid,
    input  wire                hasSchedule,
    input  wire [addrBits-1:0] schedulePid,


    output reg                 core0Active,
    output reg  [addrBits-1:0] core0Pid,
    output reg                 core1Active,
    output reg  [addrBits-1:0] core1Pid,
    output reg                 core0NeedsResumeAwake,
    output reg                 core1NeedsResumeAwake,


    output wire                canHalt
  );




  reg  [addrBits-1:0] wAddress;
  reg  [dataBits-1:0] wDataIn;

  wire [dataBits-1:0] dataOut;

  reg                 wReadWriteMode;



  IceRam #(.addrBits(addrBits), .dataBits(dataBits)) schedulerListMemory(
    .clk           (clk),
    .address       (wAddress),
    .dataIn        (wDataIn),
    .dataOut       (dataOut),
    .readWriteMode (wReadWriteMode)
  );



  reg [`CELL_COUNT:0] rScheduleState;






  reg [addrBits-1:0] rFrontOfIndexList;
  reg [addrBits-1:0] rEndOfIndexList;

  reg [3:0] rState;

  localparam STATE_INIT                            = 4'd0;
  localparam STATE_DESCHEDULE_START                = 4'd1;
  localparam STATE_DESCHEDULE_WAIT                 = 4'd2;
  localparam STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_0 = 4'd3;
  localparam STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_1 = 4'd4;
  localparam STATE_SCHEDULE_INIT                   = 4'd5;
  localparam STATE_SCHEDULE_READ_NEXT              = 4'd6;




  assign canHalt = rScheduleState == 0;

  reg [`CELL_COUNT:0] wNextScheduleState;

  reg [3:0]          wNextState;
  reg                wFinished;
  reg                wDeactivateCore0;
  reg                wDeactivateCore1;
  reg                wIncrementListFront;
  reg                wIncrementListEnd;
  reg                wActivateCore0;
  reg [addrBits-1:0] wCore0NewPid;
  reg                wActivateCore1;
  reg [addrBits-1:0] wCore1NewPid;

  always @(posedge clk)
    begin
      if (!reset)
        begin
          rState            <= STATE_INIT;
          rScheduleState    <= 0;
          finished          <= 0;
          rFrontOfIndexList <= 0;
          rEndOfIndexList   <= 0;
          core0Active       <= 0;
          core0Pid          <= 0;
          core1Active       <= 0;
          core1Pid          <= 0;
        end
      else if (!enabled)
        begin
          rState                <= STATE_INIT;
          finished              <= 0;
          core0NeedsResumeAwake <= 0;
          core1NeedsResumeAwake <= 0;
        end
      else
        begin
          rState   <= wNextState;
          finished <= wFinished;
          rScheduleState <= wNextScheduleState;

          if (wDeactivateCore0)
            core0Active <= 0;
          else if (wActivateCore0)
            begin
              core0Active           <= 1;
              core0NeedsResumeAwake <= 1;
              core0Pid              <= wCore0NewPid;
            end

          if (wDeactivateCore1)
            core1Active <= 0;
          else if (wActivateCore1)
            begin
              core1Active           <= 1;
              core1NeedsResumeAwake <= 1;
              core1Pid              <= wCore1NewPid;
            end

          if (wIncrementListFront)
            rFrontOfIndexList <= rFrontOfIndexList + 1;
          if (wIncrementListEnd)
            rEndOfIndexList <= rEndOfIndexList + 1;
        end
    end


  always @(*)
    begin
      wReadWriteMode      = `RAM_READ;
      wAddress            = {addrBits{1'bx}};
      wDataIn             = {dataBits{1'bx}};
      wNextState          = rState;
      wFinished           = 0;
      wDeactivateCore0    = 0;
      wDeactivateCore1    = 0;
      wIncrementListFront = 0;
      wIncrementListEnd   = 0;
      wNextScheduleState  = rScheduleState;
      wActivateCore0      = 0;
      wActivateCore1      = 0;
      wCore0NewPid        = 0;
      wCore1NewPid        = 0;

      case (rState)
        STATE_INIT:
          begin
            if (hasDeschedule)
              wNextState = STATE_DESCHEDULE_START;
            else if (hasSchedule)
              wNextState = STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_0;
            else
              wNextState = STATE_SCHEDULE_INIT;
          end
        STATE_DESCHEDULE_START:
          begin
            if (core0Pid == deschedulePid)
              wDeactivateCore0 = 1;
            if (core1Pid == deschedulePid)
              wDeactivateCore1 = 1;
            wNextState = STATE_DESCHEDULE_WAIT;
            wNextScheduleState = rScheduleState & ({{`CELL_COUNT{1'b1}}, 1'b1} ^ (`CELL_COUNT_CONST_1 << deschedulePid[4:0]));
          end
        STATE_DESCHEDULE_WAIT:
          begin
            if (core0Pid == deschedulePid && !core0ReadyForDeschedule)
              wNextState = STATE_DESCHEDULE_WAIT;
            else if (core1Pid == deschedulePid && !core1ReadyForDeschedule)
              wNextState = STATE_DESCHEDULE_WAIT;
            else if (hasSchedule)
              wNextState = STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_0;
            else
              wNextState = STATE_SCHEDULE_INIT;
          end
        STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_0:
          begin
            wAddress       = rEndOfIndexList;
            wDataIn        = {8'b0, schedulePid};
            wReadWriteMode = `RAM_WRITE;
            wNextState     = STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_1;
          end
        STATE_SCHEDULE_ADD_TO_SCHEDULE_LIST_1:
          begin
            wIncrementListEnd = 1;
            wAddress          = rEndOfIndexList;
            wDataIn           = {8'b0, schedulePid};
            wReadWriteMode    = `RAM_WRITE;
            wNextState        = STATE_SCHEDULE_INIT;
          end
        STATE_SCHEDULE_INIT:
          begin
            wAddress = rFrontOfIndexList;
            if (rFrontOfIndexList == rEndOfIndexList)
              wFinished = 1;
            else if (!core0Active && !core0ReadyForDeschedule)
              wNextState = STATE_SCHEDULE_INIT;
            else if (!core1Active && !core1ReadyForDeschedule)
              wNextState = STATE_SCHEDULE_INIT;
            else if (!core0Active)
              wNextState = STATE_SCHEDULE_READ_NEXT;
            else if (!core1Active)
              wNextState = STATE_SCHEDULE_READ_NEXT;
            else
              wFinished = 1;
          end
        STATE_SCHEDULE_READ_NEXT:
          begin
            wAddress            = rFrontOfIndexList;
            wIncrementListFront = 1;
            wNextState          = STATE_SCHEDULE_INIT;
            wNextScheduleState  = rScheduleState | (`CELL_COUNT_CONST_1 << dataOut[4:0]);
            if (!core0Active)
              begin
                wActivateCore0 = 1;
                wCore0NewPid   = dataOut[7:0];
                wFinished      = core1Active;
              end
            else
              begin
                wActivateCore1 = 1;
                wCore1NewPid   = dataOut[7:0];
                wFinished      = 1;
              end
          end
        default:
          begin
          end
      endcase
    end

endmodule