data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:6: Cannot find include file: spio_hss_multiplexer_common.h\n`include "spio_hss_multiplexer_common.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h.v\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h.sv\n             spio_hss_multiplexer_common.h\n             spio_hss_multiplexer_common.h.v\n             spio_hss_multiplexer_common.h.sv\n             obj_dir/spio_hss_multiplexer_common.h\n             obj_dir/spio_hss_multiplexer_common.h.v\n             obj_dir/spio_hss_multiplexer_common.h.sv\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:7: Cannot find include file: spio_hss_multiplexer_reg_bank.h\n`include "spio_hss_multiplexer_reg_bank.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:53: Define or directive not defined: \'`PKT_BITS\'\n                             ,   input  wire [`PKT_BITS-1:0] TX_PKT0_DATA_IN\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:56: Define or directive not defined: \'`PKT_BITS\'\n                             ,   input  wire [`PKT_BITS-1:0] TX_PKT1_DATA_IN\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:59: Define or directive not defined: \'`PKT_BITS\'\n                             ,   input  wire [`PKT_BITS-1:0] TX_PKT2_DATA_IN\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:62: Define or directive not defined: \'`PKT_BITS\'\n                             ,   input  wire [`PKT_BITS-1:0] TX_PKT3_DATA_IN\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:65: Define or directive not defined: \'`PKT_BITS\'\n                             ,   input  wire [`PKT_BITS-1:0] TX_PKT4_DATA_IN\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:68: Define or directive not defined: \'`PKT_BITS\'\n                             ,   input  wire [`PKT_BITS-1:0] TX_PKT5_DATA_IN\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:71: Define or directive not defined: \'`PKT_BITS\'\n                             ,   input  wire [`PKT_BITS-1:0] TX_PKT6_DATA_IN\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:74: Define or directive not defined: \'`PKT_BITS\'\n                             ,   input  wire [`PKT_BITS-1:0] TX_PKT7_DATA_IN\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:79: Define or directive not defined: \'`PKT_BITS\'\n                             ,   output wire [`PKT_BITS-1:0] RX_PKT0_DATA_OUT\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:82: Define or directive not defined: \'`PKT_BITS\'\n                             ,   output wire [`PKT_BITS-1:0] RX_PKT1_DATA_OUT\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:85: Define or directive not defined: \'`PKT_BITS\'\n                             ,   output wire [`PKT_BITS-1:0] RX_PKT2_DATA_OUT\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:88: Define or directive not defined: \'`PKT_BITS\'\n                             ,   output wire [`PKT_BITS-1:0] RX_PKT3_DATA_OUT\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:91: Define or directive not defined: \'`PKT_BITS\'\n                             ,   output wire [`PKT_BITS-1:0] RX_PKT4_DATA_OUT\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:94: Define or directive not defined: \'`PKT_BITS\'\n                             ,   output wire [`PKT_BITS-1:0] RX_PKT5_DATA_OUT\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:97: Define or directive not defined: \'`PKT_BITS\'\n                             ,   output wire [`PKT_BITS-1:0] RX_PKT6_DATA_OUT\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:100: Define or directive not defined: \'`PKT_BITS\'\n                             ,   output wire [`PKT_BITS-1:0] RX_PKT7_DATA_OUT\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:114: Define or directive not defined: \'`REGA_BITS\'\n                             ,   input  wire [`REGA_BITS - 1:0] REG_ADDR_IN\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:116: Define or directive not defined: \'`REGD_BITS\'\n                             ,   output wire [`REGD_BITS - 1:0] REG_READ_DATA_OUT\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:117: Define or directive not defined: \'`REGD_BITS\'\n                             ,   input  wire [`REGD_BITS - 1:0] REG_WRITE_DATA_IN\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:138: Define or directive not defined: \'`CRDT_BITS\'\nwire [`CRDT_BITS - 1:0] reg_crdt_i;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:139: Define or directive not defined: \'`NUM_CHANS\'\nwire [`NUM_CHANS - 1:0] reg_empt_i;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:140: Define or directive not defined: \'`NUM_CHANS\'\nwire [`NUM_CHANS - 1:0] reg_full_i;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:144: Define or directive not defined: \'`IDLE_BITS\'\nwire [`IDLE_BITS - 1:0] reg_idso_i;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:154: Define or directive not defined: \'`NUM_CHANS\'\nwire [`NUM_CHANS - 1:0] reg_cfcr_i;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:155: Define or directive not defined: \'`IDLE_BITS\'\nwire [`IDLE_BITS - 1:0] reg_idsi_i;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer.v:162: Define or directive not defined: \'`NUM_CHANS\'\nwire [`NUM_CHANS - 1:0] reg_cfcl_i;\n      ^~~~~~~~~~\n%Error: Exiting due to 28 error(s)\n'
module spio_hss_multiplexer #(
                               parameter NUM_INPUT_CHANS = 8


                             , parameter CLOCK_CORRECTION_INTERVAL = 1000

                             , parameter CLOCK_CORRECTION_INTERVAL_BITS = 10


                             , parameter NUM_HANDSHAKES = 100

                             , parameter NUM_HANDSHAKES_BITS = 7
                             )
                             (

                               input wire  CLK_IN



                             , input wire  RESET_IN
                               



                             ,   output wire HANDSHAKE_COMPLETE_OUT


                             ,   output wire VERSION_MISMATCH_OUT
                             


                             ,   input wire [31:0] RXDATA_IN
                             ,   input wire  [3:0] RXCHARISCOMMA_IN
                             ,   input wire  [3:0] RXCHARISK_IN
                             ,   input wire  [1:0] RXLOSSOFSYNC_IN
                             

                             ,   output wire [31:0] TXDATA_OUT
                             ,   output wire  [3:0] TXCHARISK_OUT
                             




                             ,   input  wire [`PKT_BITS-1:0] TX_PKT0_DATA_IN
                             ,   input  wire                 TX_PKT0_VLD_IN
                             ,   output wire                 TX_PKT0_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT1_DATA_IN
                             ,   input  wire                 TX_PKT1_VLD_IN
                             ,   output wire                 TX_PKT1_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT2_DATA_IN
                             ,   input  wire                 TX_PKT2_VLD_IN
                             ,   output wire                 TX_PKT2_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT3_DATA_IN
                             ,   input  wire                 TX_PKT3_VLD_IN
                             ,   output wire                 TX_PKT3_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT4_DATA_IN
                             ,   input  wire                 TX_PKT4_VLD_IN
                             ,   output wire                 TX_PKT4_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT5_DATA_IN
                             ,   input  wire                 TX_PKT5_VLD_IN
                             ,   output wire                 TX_PKT5_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT6_DATA_IN
                             ,   input  wire                 TX_PKT6_VLD_IN
                             ,   output wire                 TX_PKT6_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT7_DATA_IN
                             ,   input  wire                 TX_PKT7_VLD_IN
                             ,   output wire                 TX_PKT7_RDY_OUT


                             ,   output wire [`PKT_BITS-1:0] RX_PKT0_DATA_OUT
                             ,   output wire                 RX_PKT0_VLD_OUT
                             ,   input  wire                 RX_PKT0_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT1_DATA_OUT
                             ,   output wire                 RX_PKT1_VLD_OUT
                             ,   input  wire                 RX_PKT1_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT2_DATA_OUT
                             ,   output wire                 RX_PKT2_VLD_OUT
                             ,   input  wire                 RX_PKT2_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT3_DATA_OUT
                             ,   output wire                 RX_PKT3_VLD_OUT
                             ,   input  wire                 RX_PKT3_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT4_DATA_OUT
                             ,   output wire                 RX_PKT4_VLD_OUT
                             ,   input  wire                 RX_PKT4_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT5_DATA_OUT
                             ,   output wire                 RX_PKT5_VLD_OUT
                             ,   input  wire                 RX_PKT5_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT6_DATA_OUT
                             ,   output wire                 RX_PKT6_VLD_OUT
                             ,   input  wire                 RX_PKT6_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT7_DATA_OUT
                             ,   output wire                 RX_PKT7_VLD_OUT
                             ,   input  wire                 RX_PKT7_RDY_IN
                             

                             ,   input  wire                 SCRMBL_IDL_DAT






                             ,   input  wire                    REG_WRITE_IN

                             ,   input  wire [`REGA_BITS - 1:0] REG_ADDR_IN

                             ,   output wire [`REGD_BITS - 1:0] REG_READ_DATA_OUT
                             ,   input  wire [`REGD_BITS - 1:0] REG_WRITE_DATA_IN
                             );







wire [31:0] txdata_i;
wire  [3:0] txcharisk_i;
wire        txvld_i;
wire        txrdy_i;

wire [31:0] rxdata_i;
wire  [3:0] rxcharisk_i;
wire        rxvld_i;


wire                    reg_sfrm_i;
wire                    reg_looc_i;
wire [`CRDT_BITS - 1:0] reg_crdt_i;
wire [`NUM_CHANS - 1:0] reg_empt_i;
wire [`NUM_CHANS - 1:0] reg_full_i;


wire                    reg_tfrm_i;
wire [`IDLE_BITS - 1:0] reg_idso_i;
wire                    reg_stop_i;


wire                    reg_dfrm_i;
wire                    reg_crce_i;
wire                    reg_frme_i;
wire                    reg_rnak_i;
wire                    reg_rack_i;
wire                    reg_rooc_i;
wire [`NUM_CHANS - 1:0] reg_cfcr_i;
wire [`IDLE_BITS - 1:0] reg_idsi_i;


wire                    reg_rfrm_i;
wire                    reg_busy_i;
wire                    reg_lnak_i;
wire                    reg_lack_i;
wire [`NUM_CHANS - 1:0] reg_cfcl_i;


wire [1:0]              reg_hand_i;





spio_hss_multiplexer_reg_bank
spio_hss_multiplexer_reg_bank_i( .clk (CLK_IN)
                               , .rst (RESET_IN)
                               

                               , .reg_sfrm (reg_sfrm_i)
                               , .reg_looc (reg_looc_i)
                               , .reg_crdt (reg_crdt_i)
                               , .reg_empt (reg_empt_i)
                               , .reg_full (reg_full_i)
                               

                               , .reg_tfrm (reg_tfrm_i)
                               , .reg_idso (reg_idso_i)
                               , .reg_stop (reg_stop_i)
                               

                               , .reg_dfrm (reg_dfrm_i)
                               , .reg_crce (reg_crce_i)
                               , .reg_frme (reg_frme_i)
                               , .reg_rnak (reg_rnak_i)
                               , .reg_rack (reg_rack_i)
                               , .reg_rooc (reg_rooc_i)
                               , .reg_cfcr (reg_cfcr_i)
                               , .reg_idsi (reg_idsi_i)
                               

                               , .reg_rfrm (reg_rfrm_i)
                               , .reg_busy (reg_busy_i)
                               , .reg_lnak (reg_lnak_i)
                               , .reg_lack (reg_lack_i)
                               , .reg_cfcl (reg_cfcl_i)
                               

                               , .reg_hand (reg_hand_i)
                               

                               , .reg_write      (REG_WRITE_IN)
                               , .reg_addr       (REG_ADDR_IN)
                               , .reg_read_data  (REG_READ_DATA_OUT)
                               , .reg_write_data (REG_WRITE_DATA_IN)
                               );






wire handshake_phase_i;

spio_hss_multiplexer_tx_control
spio_hss_multiplexer_tx_control_i( .CLK_IN                 (CLK_IN)
                                 , .RESET_IN               (RESET_IN)
                                 , .SCRMBL_IDL_DAT         (SCRMBL_IDL_DAT)
                                 , .REG_IDSO_IN            (reg_idso_i)
                                 , .HANDSHAKE_COMPLETE_IN  (HANDSHAKE_COMPLETE_OUT)
                                 , .HANDSHAKE_PHASE_IN     (handshake_phase_i)
                                 , .TXDATA_OUT             (TXDATA_OUT)
                                 , .TXCHARISK_OUT          (TXCHARISK_OUT)
                                 , .TXDATA_IN              (txdata_i)
                                 , .TXCHARISK_IN           (txcharisk_i)
                                 , .TXVLD_IN               (txvld_i)
                                 , .TXRDY_OUT              (txrdy_i)
                                 );


spio_hss_multiplexer_rx_control #( .NUM_HANDSHAKES(NUM_HANDSHAKES)
                                 , .NUM_HANDSHAKES_BITS(NUM_HANDSHAKES_BITS)
                                 )
spio_hss_multiplexer_rx_control_i( .CLK_IN                 (CLK_IN)
                                 , .RESET_IN               (RESET_IN)
                                 , .REG_IDSI_OUT           (reg_idsi_i)
                                 , .HANDSHAKE_COMPLETE_OUT (HANDSHAKE_COMPLETE_OUT)
                                 , .HANDSHAKE_PHASE_OUT    (handshake_phase_i)
                                 , .VERSION_MISMATCH_OUT   (VERSION_MISMATCH_OUT)
                                 , .RXDATA_IN              (RXDATA_IN)
                                 , .RXCHARISCOMMA_IN       (RXCHARISCOMMA_IN)
                                 , .RXLOSSOFSYNC_IN        (RXLOSSOFSYNC_IN)
                                 , .RXCHARISK_IN           (RXCHARISK_IN)
                                 , .RXDATA_OUT             (rxdata_i)
                                 , .RXCHARISK_OUT          (rxcharisk_i)
                                 , .RXVLD_OUT              (rxvld_i)
                                 );

assign reg_hand_i = {VERSION_MISMATCH_OUT, HANDSHAKE_COMPLETE_OUT};







spio_hss_multiplexer_spinnlink #( .NUM_INPUT_CHANS  (NUM_INPUT_CHANS)
                                )
spio_hss_multiplexer_spinnlink_i( .clk       (CLK_IN)
                                , .rst       (RESET_IN)
                                

                                , .reg_sfrm  (reg_sfrm_i)
                                , .reg_looc  (reg_looc_i)
                                , .reg_crdt  (reg_crdt_i)
                                , .reg_empt  (reg_empt_i)
                                , .reg_full  (reg_full_i)
                                  

                                , .reg_tfrm  (reg_tfrm_i)
                                , .reg_stop  (reg_stop_i)
                                  

                                , .reg_dfrm  (reg_dfrm_i)
                                , .reg_crce  (reg_crce_i)
                                , .reg_frme  (reg_frme_i)
                                , .reg_rnak  (reg_rnak_i)
                                , .reg_rack  (reg_rack_i)
                                , .reg_rooc  (reg_rooc_i)
                                , .reg_cfcr  (reg_cfcr_i)
                                  

                                , .reg_rfrm  (reg_rfrm_i)
                                , .reg_busy  (reg_busy_i)
                                , .reg_lnak  (reg_lnak_i)
                                , .reg_lack  (reg_lack_i)
                                , .reg_cfcl  (reg_cfcl_i)
                                

                                , .hsl_data  (txdata_i)
                                , .hsl_kchr  (txcharisk_i)
                                , .hsl_vld   (txvld_i)
                                , .hsl_rdy   (txrdy_i)
                                

                                , .ihsl_data  (rxdata_i)
                                , .ihsl_kchr  (rxcharisk_i)
                                , .ihsl_vld   (rxvld_i)
                                

                                , .pkt_data0 (TX_PKT0_DATA_IN)
                                , .pkt_vld0  (TX_PKT0_VLD_IN)
                                , .pkt_rdy0  (TX_PKT0_RDY_OUT)
                                
                                , .pkt_data1 (TX_PKT1_DATA_IN)
                                , .pkt_vld1  (TX_PKT1_VLD_IN)
                                , .pkt_rdy1  (TX_PKT1_RDY_OUT)
                                
                                , .pkt_data2 (TX_PKT2_DATA_IN)
                                , .pkt_vld2  (TX_PKT2_VLD_IN)
                                , .pkt_rdy2  (TX_PKT2_RDY_OUT)
                                
                                , .pkt_data3 (TX_PKT3_DATA_IN)
                                , .pkt_vld3  (TX_PKT3_VLD_IN)
                                , .pkt_rdy3  (TX_PKT3_RDY_OUT)
                                
                                , .pkt_data4 (TX_PKT4_DATA_IN)
                                , .pkt_vld4  (TX_PKT4_VLD_IN)
                                , .pkt_rdy4  (TX_PKT4_RDY_OUT)
                                
                                , .pkt_data5 (TX_PKT5_DATA_IN)
                                , .pkt_vld5  (TX_PKT5_VLD_IN)
                                , .pkt_rdy5  (TX_PKT5_RDY_OUT)
                                
                                , .pkt_data6 (TX_PKT6_DATA_IN)
                                , .pkt_vld6  (TX_PKT6_VLD_IN)
                                , .pkt_rdy6  (TX_PKT6_RDY_OUT)
                                
                                , .pkt_data7 (TX_PKT7_DATA_IN)
                                , .pkt_vld7  (TX_PKT7_VLD_IN)
                                , .pkt_rdy7  (TX_PKT7_RDY_OUT)
                                

                                , .opkt_data0(RX_PKT0_DATA_OUT)
                                , .opkt_vld0 (RX_PKT0_VLD_OUT)
                                , .opkt_rdy0 (RX_PKT0_RDY_IN)
                                
                                , .opkt_data1(RX_PKT1_DATA_OUT)
                                , .opkt_vld1 (RX_PKT1_VLD_OUT)
                                , .opkt_rdy1 (RX_PKT1_RDY_IN)
                                
                                , .opkt_data2(RX_PKT2_DATA_OUT)
                                , .opkt_vld2 (RX_PKT2_VLD_OUT)
                                , .opkt_rdy2 (RX_PKT2_RDY_IN)
                                
                                , .opkt_data3(RX_PKT3_DATA_OUT)
                                , .opkt_vld3 (RX_PKT3_VLD_OUT)
                                , .opkt_rdy3 (RX_PKT3_RDY_IN)
                                
                                , .opkt_data4(RX_PKT4_DATA_OUT)
                                , .opkt_vld4 (RX_PKT4_VLD_OUT)
                                , .opkt_rdy4 (RX_PKT4_RDY_IN)
                                
                                , .opkt_data5(RX_PKT5_DATA_OUT)
                                , .opkt_vld5 (RX_PKT5_VLD_OUT)
                                , .opkt_rdy5 (RX_PKT5_RDY_IN)
                                
                                , .opkt_data6(RX_PKT6_DATA_OUT)
                                , .opkt_vld6 (RX_PKT6_VLD_OUT)
                                , .opkt_rdy6 (RX_PKT6_RDY_IN)
                                
                                , .opkt_data7(RX_PKT7_DATA_OUT)
                                , .opkt_vld7 (RX_PKT7_VLD_OUT)
                                , .opkt_rdy7 (RX_PKT7_RDY_IN)
                                );

endmodule
module spio_hss_multiplexer #(
                               parameter NUM_INPUT_CHANS = 8


                             , parameter CLOCK_CORRECTION_INTERVAL = 1000

                             , parameter CLOCK_CORRECTION_INTERVAL_BITS = 10


                             , parameter NUM_HANDSHAKES = 100

                             , parameter NUM_HANDSHAKES_BITS = 7
                             )
                             (

                               input wire  CLK_IN



                             , input wire  RESET_IN
                               



                             ,   output wire HANDSHAKE_COMPLETE_OUT


                             ,   output wire VERSION_MISMATCH_OUT
                             


                             ,   input wire [31:0] RXDATA_IN
                             ,   input wire  [3:0] RXCHARISCOMMA_IN
                             ,   input wire  [3:0] RXCHARISK_IN
                             ,   input wire  [1:0] RXLOSSOFSYNC_IN
                             

                             ,   output wire [31:0] TXDATA_OUT
                             ,   output wire  [3:0] TXCHARISK_OUT
                             




                             ,   input  wire [`PKT_BITS-1:0] TX_PKT0_DATA_IN
                             ,   input  wire                 TX_PKT0_VLD_IN
                             ,   output wire                 TX_PKT0_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT1_DATA_IN
                             ,   input  wire                 TX_PKT1_VLD_IN
                             ,   output wire                 TX_PKT1_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT2_DATA_IN
                             ,   input  wire                 TX_PKT2_VLD_IN
                             ,   output wire                 TX_PKT2_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT3_DATA_IN
                             ,   input  wire                 TX_PKT3_VLD_IN
                             ,   output wire                 TX_PKT3_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT4_DATA_IN
                             ,   input  wire                 TX_PKT4_VLD_IN
                             ,   output wire                 TX_PKT4_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT5_DATA_IN
                             ,   input  wire                 TX_PKT5_VLD_IN
                             ,   output wire                 TX_PKT5_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT6_DATA_IN
                             ,   input  wire                 TX_PKT6_VLD_IN
                             ,   output wire                 TX_PKT6_RDY_OUT
                             ,   input  wire [`PKT_BITS-1:0] TX_PKT7_DATA_IN
                             ,   input  wire                 TX_PKT7_VLD_IN
                             ,   output wire                 TX_PKT7_RDY_OUT


                             ,   output wire [`PKT_BITS-1:0] RX_PKT0_DATA_OUT
                             ,   output wire                 RX_PKT0_VLD_OUT
                             ,   input  wire                 RX_PKT0_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT1_DATA_OUT
                             ,   output wire                 RX_PKT1_VLD_OUT
                             ,   input  wire                 RX_PKT1_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT2_DATA_OUT
                             ,   output wire                 RX_PKT2_VLD_OUT
                             ,   input  wire                 RX_PKT2_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT3_DATA_OUT
                             ,   output wire                 RX_PKT3_VLD_OUT
                             ,   input  wire                 RX_PKT3_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT4_DATA_OUT
                             ,   output wire                 RX_PKT4_VLD_OUT
                             ,   input  wire                 RX_PKT4_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT5_DATA_OUT
                             ,   output wire                 RX_PKT5_VLD_OUT
                             ,   input  wire                 RX_PKT5_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT6_DATA_OUT
                             ,   output wire                 RX_PKT6_VLD_OUT
                             ,   input  wire                 RX_PKT6_RDY_IN
                             ,   output wire [`PKT_BITS-1:0] RX_PKT7_DATA_OUT
                             ,   output wire                 RX_PKT7_VLD_OUT
                             ,   input  wire                 RX_PKT7_RDY_IN
                             

                             ,   input  wire                 SCRMBL_IDL_DAT






                             ,   input  wire                    REG_WRITE_IN

                             ,   input  wire [`REGA_BITS - 1:0] REG_ADDR_IN

                             ,   output wire [`REGD_BITS - 1:0] REG_READ_DATA_OUT
                             ,   input  wire [`REGD_BITS - 1:0] REG_WRITE_DATA_IN
                             );








wire [31:0] txdata_i;
wire  [3:0] txcharisk_i;
wire        txvld_i;
wire        txrdy_i;

wire [31:0] rxdata_i;
wire  [3:0] rxcharisk_i;
wire        rxvld_i;


wire                    reg_sfrm_i;
wire                    reg_looc_i;
wire [`CRDT_BITS - 1:0] reg_crdt_i;
wire [`NUM_CHANS - 1:0] reg_empt_i;
wire [`NUM_CHANS - 1:0] reg_full_i;


wire                    reg_tfrm_i;
wire [`IDLE_BITS - 1:0] reg_idso_i;
wire                    reg_stop_i;


wire                    reg_dfrm_i;
wire                    reg_crce_i;
wire                    reg_frme_i;
wire                    reg_rnak_i;
wire                    reg_rack_i;
wire                    reg_rooc_i;
wire [`NUM_CHANS - 1:0] reg_cfcr_i;
wire [`IDLE_BITS - 1:0] reg_idsi_i;


wire                    reg_rfrm_i;
wire                    reg_busy_i;
wire                    reg_lnak_i;
wire                    reg_lack_i;
wire [`NUM_CHANS - 1:0] reg_cfcl_i;


wire [1:0]              reg_hand_i;





spio_hss_multiplexer_reg_bank
spio_hss_multiplexer_reg_bank_i( .clk (CLK_IN)
                               , .rst (RESET_IN)
                               

                               , .reg_sfrm (reg_sfrm_i)
                               , .reg_looc (reg_looc_i)
                               , .reg_crdt (reg_crdt_i)
                               , .reg_empt (reg_empt_i)
                               , .reg_full (reg_full_i)
                               

                               , .reg_tfrm (reg_tfrm_i)
                               , .reg_idso (reg_idso_i)
                               , .reg_stop (reg_stop_i)
                               

                               , .reg_dfrm (reg_dfrm_i)
                               , .reg_crce (reg_crce_i)
                               , .reg_frme (reg_frme_i)
                               , .reg_rnak (reg_rnak_i)
                               , .reg_rack (reg_rack_i)
                               , .reg_rooc (reg_rooc_i)
                               , .reg_cfcr (reg_cfcr_i)
                               , .reg_idsi (reg_idsi_i)
                               

                               , .reg_rfrm (reg_rfrm_i)
                               , .reg_busy (reg_busy_i)
                               , .reg_lnak (reg_lnak_i)
                               , .reg_lack (reg_lack_i)
                               , .reg_cfcl (reg_cfcl_i)
                               

                               , .reg_hand (reg_hand_i)
                               

                               , .reg_write      (REG_WRITE_IN)
                               , .reg_addr       (REG_ADDR_IN)
                               , .reg_read_data  (REG_READ_DATA_OUT)
                               , .reg_write_data (REG_WRITE_DATA_IN)
                               );






wire handshake_phase_i;

spio_hss_multiplexer_tx_control
spio_hss_multiplexer_tx_control_i( .CLK_IN                 (CLK_IN)
                                 , .RESET_IN               (RESET_IN)
                                 , .SCRMBL_IDL_DAT         (SCRMBL_IDL_DAT)
                                 , .REG_IDSO_IN            (reg_idso_i)
                                 , .HANDSHAKE_COMPLETE_IN  (HANDSHAKE_COMPLETE_OUT)
                                 , .HANDSHAKE_PHASE_IN     (handshake_phase_i)
                                 , .TXDATA_OUT             (TXDATA_OUT)
                                 , .TXCHARISK_OUT          (TXCHARISK_OUT)
                                 , .TXDATA_IN              (txdata_i)
                                 , .TXCHARISK_IN           (txcharisk_i)
                                 , .TXVLD_IN               (txvld_i)
                                 , .TXRDY_OUT              (txrdy_i)
                                 );


spio_hss_multiplexer_rx_control #( .NUM_HANDSHAKES(NUM_HANDSHAKES)
                                 , .NUM_HANDSHAKES_BITS(NUM_HANDSHAKES_BITS)
                                 )
spio_hss_multiplexer_rx_control_i( .CLK_IN                 (CLK_IN)
                                 , .RESET_IN               (RESET_IN)
                                 , .REG_IDSI_OUT           (reg_idsi_i)
                                 , .HANDSHAKE_COMPLETE_OUT (HANDSHAKE_COMPLETE_OUT)
                                 , .HANDSHAKE_PHASE_OUT    (handshake_phase_i)
                                 , .VERSION_MISMATCH_OUT   (VERSION_MISMATCH_OUT)
                                 , .RXDATA_IN              (RXDATA_IN)
                                 , .RXCHARISCOMMA_IN       (RXCHARISCOMMA_IN)
                                 , .RXLOSSOFSYNC_IN        (RXLOSSOFSYNC_IN)
                                 , .RXCHARISK_IN           (RXCHARISK_IN)
                                 , .RXDATA_OUT             (rxdata_i)
                                 , .RXCHARISK_OUT          (rxcharisk_i)
                                 , .RXVLD_OUT              (rxvld_i)
                                 );

assign reg_hand_i = {VERSION_MISMATCH_OUT, HANDSHAKE_COMPLETE_OUT};







spio_hss_multiplexer_spinnlink #( .NUM_INPUT_CHANS  (NUM_INPUT_CHANS)
                                )
spio_hss_multiplexer_spinnlink_i( .clk       (CLK_IN)
                                , .rst       (RESET_IN)
                                

                                , .reg_sfrm  (reg_sfrm_i)
                                , .reg_looc  (reg_looc_i)
                                , .reg_crdt  (reg_crdt_i)
                                , .reg_empt  (reg_empt_i)
                                , .reg_full  (reg_full_i)
                                  

                                , .reg_tfrm  (reg_tfrm_i)
                                , .reg_stop  (reg_stop_i)
                                  

                                , .reg_dfrm  (reg_dfrm_i)
                                , .reg_crce  (reg_crce_i)
                                , .reg_frme  (reg_frme_i)
                                , .reg_rnak  (reg_rnak_i)
                                , .reg_rack  (reg_rack_i)
                                , .reg_rooc  (reg_rooc_i)
                                , .reg_cfcr  (reg_cfcr_i)
                                  

                                , .reg_rfrm  (reg_rfrm_i)
                                , .reg_busy  (reg_busy_i)
                                , .reg_lnak  (reg_lnak_i)
                                , .reg_lack  (reg_lack_i)
                                , .reg_cfcl  (reg_cfcl_i)
                                

                                , .hsl_data  (txdata_i)
                                , .hsl_kchr  (txcharisk_i)
                                , .hsl_vld   (txvld_i)
                                , .hsl_rdy   (txrdy_i)
                                

                                , .ihsl_data  (rxdata_i)
                                , .ihsl_kchr  (rxcharisk_i)
                                , .ihsl_vld   (rxvld_i)
                                

                                , .pkt_data0 (TX_PKT0_DATA_IN)
                                , .pkt_vld0  (TX_PKT0_VLD_IN)
                                , .pkt_rdy0  (TX_PKT0_RDY_OUT)
                                
                                , .pkt_data1 (TX_PKT1_DATA_IN)
                                , .pkt_vld1  (TX_PKT1_VLD_IN)
                                , .pkt_rdy1  (TX_PKT1_RDY_OUT)
                                
                                , .pkt_data2 (TX_PKT2_DATA_IN)
                                , .pkt_vld2  (TX_PKT2_VLD_IN)
                                , .pkt_rdy2  (TX_PKT2_RDY_OUT)
                                
                                , .pkt_data3 (TX_PKT3_DATA_IN)
                                , .pkt_vld3  (TX_PKT3_VLD_IN)
                                , .pkt_rdy3  (TX_PKT3_RDY_OUT)
                                
                                , .pkt_data4 (TX_PKT4_DATA_IN)
                                , .pkt_vld4  (TX_PKT4_VLD_IN)
                                , .pkt_rdy4  (TX_PKT4_RDY_OUT)
                                
                                , .pkt_data5 (TX_PKT5_DATA_IN)
                                , .pkt_vld5  (TX_PKT5_VLD_IN)
                                , .pkt_rdy5  (TX_PKT5_RDY_OUT)
                                
                                , .pkt_data6 (TX_PKT6_DATA_IN)
                                , .pkt_vld6  (TX_PKT6_VLD_IN)
                                , .pkt_rdy6  (TX_PKT6_RDY_OUT)
                                
                                , .pkt_data7 (TX_PKT7_DATA_IN)
                                , .pkt_vld7  (TX_PKT7_VLD_IN)
                                , .pkt_rdy7  (TX_PKT7_RDY_OUT)
                                

                                , .opkt_data0(RX_PKT0_DATA_OUT)
                                , .opkt_vld0 (RX_PKT0_VLD_OUT)
                                , .opkt_rdy0 (RX_PKT0_RDY_IN)
                                
                                , .opkt_data1(RX_PKT1_DATA_OUT)
                                , .opkt_vld1 (RX_PKT1_VLD_OUT)
                                , .opkt_rdy1 (RX_PKT1_RDY_IN)
                                
                                , .opkt_data2(RX_PKT2_DATA_OUT)
                                , .opkt_vld2 (RX_PKT2_VLD_OUT)
                                , .opkt_rdy2 (RX_PKT2_RDY_IN)
                                
                                , .opkt_data3(RX_PKT3_DATA_OUT)
                                , .opkt_vld3 (RX_PKT3_VLD_OUT)
                                , .opkt_rdy3 (RX_PKT3_RDY_IN)
                                
                                , .opkt_data4(RX_PKT4_DATA_OUT)
                                , .opkt_vld4 (RX_PKT4_VLD_OUT)
                                , .opkt_rdy4 (RX_PKT4_RDY_IN)
                                
                                , .opkt_data5(RX_PKT5_DATA_OUT)
                                , .opkt_vld5 (RX_PKT5_VLD_OUT)
                                , .opkt_rdy5 (RX_PKT5_RDY_IN)
                                
                                , .opkt_data6(RX_PKT6_DATA_OUT)
                                , .opkt_vld6 (RX_PKT6_VLD_OUT)
                                , .opkt_rdy6 (RX_PKT6_RDY_IN)
                                
                                , .opkt_data7(RX_PKT7_DATA_OUT)
                                , .opkt_vld7 (RX_PKT7_VLD_OUT)
                                , .opkt_rdy7 (RX_PKT7_RDY_IN)
                                );

endmodule