data/full_repos/permissive/119715647/sim/AccessControl/AccessControl.v
1: b'%Warning-WIDTH: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl.v:25: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s XOR generates 16 bits.\n                                                                                         : ... In instance AccessControl\n assign Memory_data_wire = (ROM_data_wire ^ RAM_data_wire)?\n                                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl.v:29: Cannot find file containing module: \'ROMPassword\'\n ROMPassword ROM(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119715647/sim/AccessControl,data/full_repos/permissive/119715647/ROMPassword\n             data/full_repos/permissive/119715647/sim/AccessControl,data/full_repos/permissive/119715647/ROMPassword.v\n             data/full_repos/permissive/119715647/sim/AccessControl,data/full_repos/permissive/119715647/ROMPassword.sv\n             ROMPassword\n             ROMPassword.v\n             ROMPassword.sv\n             obj_dir/ROMPassword\n             obj_dir/ROMPassword.v\n             obj_dir/ROMPassword.sv\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl.v:34: Cannot find file containing module: \'RAMPassword\'\n RAMPassword RAM(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl.v:41: Cannot find file containing module: \'AccessControlFsm\'\n AccessControlFsm FSM(\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module AccessControl(
	input clk, 
	input rst, 
	input [17:0] _Data_In, 
	input [0:0]  _Data_In_Load,
	output [0:0] _Access_grant,
	output [15:0] user_ID); 


	
	wire [15:0] ROM_data_wire; 
	wire [15:0] RAM_data_wire;
	wire [15:0] FSM_data_wire; 
	wire [15:0] Address_Wire; 
	wire [0:0] Access_Grant_wire, wren_wire; 
	wire [15:0] Memory_data_wire; 

	assign Memory_data_wire = (ROM_data_wire ^ RAM_data_wire)?
								RAM_data_wire:
								ROM_data_wire;
	 
	ROMPassword ROM(
		._Address(Address_Wire), 
		.clk(clk), 
		._Data(ROM_data_wire));

	RAMPassword RAM(
		.clk(clk),
		._Address(Address_Wire), 
		._Data_In(FSM_data_wire), 
		.wren(wren_wire), 
		._Data_Out(RAM_data_wire));
	
	AccessControlFsm FSM(
		.clk(clk),
		.rst(rst), 
		._Data_In(_Data_In), 
		._Data_In_Load(_Data_In_Load), 
		._Memory_In(Memory_data_wire), 
		.Access_Grant(Access_Grant_wire),
		.Address(Address_Wire), 
		.wren(wren_wire),
		.Data_Out(FSM_data_wire));  

	assign _Access_grant = Access_Grant_wire;
	assign user_ID = Address_Wire;
	
endmodule
module AccessControl(
	input clk, 
	input rst, 
	input [17:0] _Data_In, 
	input [0:0]  _Data_In_Load,
	output [0:0] _Access_grant,
	output [15:0] user_ID);
 


	
	wire [15:0] ROM_data_wire; 
	wire [15:0] RAM_data_wire;
	wire [15:0] FSM_data_wire; 
	wire [15:0] Address_Wire; 
	wire [0:0] Access_Grant_wire, wren_wire; 
	wire [15:0] Memory_data_wire; 

	assign Memory_data_wire = (ROM_data_wire ^ RAM_data_wire)?
								RAM_data_wire:
								ROM_data_wire;
	 
	ROMPassword ROM(
		._Address(Address_Wire), 
		.clk(clk), 
		._Data(ROM_data_wire));

	RAMPassword RAM(
		.clk(clk),
		._Address(Address_Wire), 
		._Data_In(FSM_data_wire), 
		.wren(wren_wire), 
		._Data_Out(RAM_data_wire));
	
	AccessControlFsm FSM(
		.clk(clk),
		.rst(rst), 
		._Data_In(_Data_In), 
		._Data_In_Load(_Data_In_Load), 
		._Memory_In(Memory_data_wire), 
		.Access_Grant(Access_Grant_wire),
		.Address(Address_Wire), 
		.wren(wren_wire),
		.Data_Out(FSM_data_wire));  

	assign _Access_grant = Access_Grant_wire;
	assign user_ID = Address_Wire;
	
endmodule