data/full_repos/permissive/207610706/sim/testbench.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/207610706/sim/testbench.sv:3: Cannot find include file: wrapper_defines.vh\n`include "wrapper_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207610706/sim,data/full_repos/permissive/207610706/wrapper_defines.vh\n             data/full_repos/permissive/207610706/sim,data/full_repos/permissive/207610706/wrapper_defines.vh.v\n             data/full_repos/permissive/207610706/sim,data/full_repos/permissive/207610706/wrapper_defines.vh.sv\n             wrapper_defines.vh\n             wrapper_defines.vh.v\n             wrapper_defines.vh.sv\n             obj_dir/wrapper_defines.vh\n             obj_dir/wrapper_defines.vh.v\n             obj_dir/wrapper_defines.vh.sv\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:4: Cannot find include file: aeses_defines.vh\n`include "aeses_defines.vh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:5: Cannot find include file: uart/uart_defines.v\n`include "uart/uart_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:9: Define or directive not defined: \'`SIM_HALF_CLK_PERIOD_DEF\'\nparameter HALF_CLK_PERIOD     =`SIM_HALF_CLK_PERIOD_DEF;\n                               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:9: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter HALF_CLK_PERIOD     =`SIM_HALF_CLK_PERIOD_DEF;\n                                                       ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:11: Define or directive not defined: \'`SIM_UART_NUM_CLK_TICKS_BIT\'\nparameter UART_NUM_CLK_TICKS_BIT   =`SIM_UART_NUM_CLK_TICKS_BIT;  \n                                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:11: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter UART_NUM_CLK_TICKS_BIT   =`SIM_UART_NUM_CLK_TICKS_BIT;  \n                                                               ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:43: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:46: syntax error, unexpected \'@\'\n  repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);\n                                 ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:52: syntax error, unexpected \'@\'\n   repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);\n                                  ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:58: syntax error, unexpected \'@\'\n   repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);\n                                  ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:72: syntax error, unexpected \'@\'\n  @(negedge pad_rx_uart_tb);\n  ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:76: syntax error, unexpected \'@\'\n repeat(UART_NUM_CLK_TICKS_BIT/2) @(posedge clk);\n                                  ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:81: syntax error, unexpected \'@\'\n   repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);\n                                  ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:88: syntax error, unexpected \'@\'\n   repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);\n                                  ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:101: Define or directive not defined: \'`KEY_192\'\nwire [1:0] mode = `KEY_192;  \n                  ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:101: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nwire [1:0] mode = `KEY_192;  \n                          ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:126: Define or directive not defined: \'`KEY_128\'\n        `KEY_128:\n        ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:126: syntax error, unexpected \':\', expecting endcase\n        `KEY_128:\n                ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:133: Define or directive not defined: \'`KEY_192\'\n        `KEY_192:\n        ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:134: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            begin\n            ^~~~~\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:140: Define or directive not defined: \'`KEY_256\'\n        `KEY_256:\n        ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:141: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            begin\n            ^~~~~\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:147: syntax error, unexpected \':\', expecting clocking\n        default:\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/207610706/sim/testbench.sv:178: Unsupported: Ignoring delay on this delayed statement.\nalways #HALF_CLK_PERIOD clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:200: syntax error, unexpected \'@\'\n repeat(2) @(posedge clk);\n           ^\n%Error: data/full_repos/permissive/207610706/sim/testbench.sv:203: syntax error, unexpected \'@\'\n repeat(2) @(posedge clk);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/207610706/sim/testbench.sv:243: Unsupported: Ignoring delay on this delayed statement.\n #20 $finish;\n ^\n%Error: Exiting due to 26 error(s), 2 warning(s)\n'
module fpga_top_tb ();

parameter HALF_CLK_PERIOD 				=`SIM_HALF_CLK_PERIOD_DEF;
parameter CLK_PERIOD 					=HALF_CLK_PERIOD * 2;
parameter UART_NUM_CLK_TICKS_BIT 		=`SIM_UART_NUM_CLK_TICKS_BIT;
parameter UART_NUM_DWORD_BITS			= 8;
parameter UART_NUM_STOP_BITS			= 1;

reg		clk;
reg		rst;
reg		pad_tx_tb_uart;
wire	pad_rx_uart_tb;

reg [UART_NUM_DWORD_BITS-1:0] recv_data;


wire 	[9:0] LED;

fpga_top
top0(	
	.CLK_PIN(clk),
	.RST_PIN(rst),
	.RX_PIN(pad_tx_tb_uart),
	.TX_PIN(pad_rx_uart_tb),
	.M_LED(LED)
	);




task sendByteUart;
		input [7:0] wdata;
		integer i;
	begin
		$display("@%0t: START tb.sendByteUart(%b)",$time,wdata);

		@(posedge clk);
		pad_tx_tb_uart <= 0;
		i<=0;
		repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);

		repeat(UART_NUM_DWORD_BITS)
		begin
			i<=i+1;
			pad_tx_tb_uart <= wdata[i];
			repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);
		end

		repeat(UART_NUM_STOP_BITS)
		begin
			pad_tx_tb_uart <= 1;
			repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);
		end
		$display("@%0t: END tb.sendByteUart(%b)",$time,wdata);
	end
endtask


task recvByteUart;
	output reg [7:0] rdata;
		begin
		$display("@%0t: START tb.recvByteUart()",$time);


	while(pad_rx_uart_tb!=0)
		@(negedge pad_rx_uart_tb);
		
	$display("@%0t: uart.recv() startbit: %b",$time,pad_rx_uart_tb);

	repeat(UART_NUM_CLK_TICKS_BIT/2) @(posedge clk);


		repeat(UART_NUM_DWORD_BITS)
		begin
			repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);
			rdata <= {pad_rx_uart_tb , rdata[UART_NUM_DWORD_BITS-1:1]};
		end


		repeat(UART_NUM_STOP_BITS)
		begin
			repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);
			if(pad_rx_uart_tb!=1)
				$display("@%0t: ERROR tb.recvByteUart() WRONG STOP BIT",$time);

		end

	$display("@%0t: END tb.recvByteUart(%b)",$time,rdata);
end
endtask




wire [1:0] mode = `KEY_192;
wire encryption = 1'b1;
 
wire [0:255] key_128_bit = 256'h000102030405060708090a0b0c0d0e0f00000000000000000000000000000000;
wire [0:255] key_192_bit = 256'h000102030405060708090a0b0c0d0e0f10111213141516170000000000000000;
wire [0:255] key_256_bit = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;

wire [0:127] test_ptx = 128'h00112233445566778899aabbccddeeff;

wire [0:127] ctx_128 = 128'h69c4e0d86a7b0430d8cdb78070b4c55a;
wire [0:127] ctx_192 = 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
wire [0:127] ctx_256 = 128'h8ea2b7ca516745bfeafc49904b496089;

reg [0:255] input_key;
wire [7:0] input_key_bytes[0:31];

reg [0:127] start_value;
wire [7:0] start_value_bytes[0:15];

reg [0:127] final_reference;
reg [7:0] result[0:15];

always@(*)
begin
    case(mode)
        `KEY_128:
            begin
            input_key = key_128_bit;
            start_value = ctx_128;

            final_reference = ctx_128;
            end
        `KEY_192:
            begin
            input_key = key_192_bit;
            start_value = ctx_192;

            final_reference = ctx_192;
            end
        `KEY_256:
            begin
            input_key = key_256_bit;
            start_value = ctx_256;

            final_reference = ctx_256;
            end
        default:
            begin
            input_key = 256'h0;
            start_value = {64{2'b10}};

            final_reference = {64{2'b10}};
            end
    endcase
    
    if(encryption)
        start_value = test_ptx;
    else
        final_reference = test_ptx;
end

genvar k;
generate
    for(k=0; k<32; k=k+1)
    begin: split_key_bytes
        assign input_key_bytes[k] = input_key[8*k:8*(k+1)-1]; 
    end
    
    for(k=0; k<16; k=k+1)
    begin: split_ptx_ctx_i
        assign start_value_bytes[k] = start_value[8*k:8*(k+1)-1];
    end
endgenerate




always #HALF_CLK_PERIOD clk = ~clk;




initial
begin:initial_tb
    automatic integer i;
    integer cnt;

	
	clk <= 0;
  	rst = 0;
	pad_tx_tb_uart = 1;
	recv_data =0;
	repeat(2) @(posedge clk);
  	rst = 1;
	
	repeat(2) @(posedge clk);
	

	sendByteUart({1'b1, mode, 5'd0});

	cnt = 0;
	repeat(32)
	begin
	   sendByteUart(input_key_bytes[cnt]);
	   cnt=cnt+1;
    end
    
    repeat(3)
    begin

        sendByteUart({1'b0, mode, 1'b1, encryption, 3'd0});

        cnt = 0;
        repeat(16)
        begin
            sendByteUart(start_value_bytes[cnt]);
            cnt=cnt+1;
        end
        

        cnt = 0;
        repeat(16)	
        begin
            recvByteUart(recv_data);
            result[cnt]=recv_data;
            cnt=cnt+1;
        end
        
        $write("#################\n");
        for(i=0;i<16;i=i+1)
           $write("%h",result[i]);
        $write("\n%h\n", final_reference);
        $write("#################\n");
    end
	
	#20 $finish;
end

endmodule
module fpga_top_tb ();


parameter HALF_CLK_PERIOD 				=`SIM_HALF_CLK_PERIOD_DEF;
parameter CLK_PERIOD 					=HALF_CLK_PERIOD * 2;
parameter UART_NUM_CLK_TICKS_BIT 		=`SIM_UART_NUM_CLK_TICKS_BIT;
parameter UART_NUM_DWORD_BITS			= 8;
parameter UART_NUM_STOP_BITS			= 1;

reg		clk;
reg		rst;
reg		pad_tx_tb_uart;
wire	pad_rx_uart_tb;

reg [UART_NUM_DWORD_BITS-1:0] recv_data;


wire 	[9:0] LED;

fpga_top
top0(	
	.CLK_PIN(clk),
	.RST_PIN(rst),
	.RX_PIN(pad_tx_tb_uart),
	.TX_PIN(pad_rx_uart_tb),
	.M_LED(LED)
	);




task sendByteUart;
		input [7:0] wdata;
		integer i;
	begin
		$display("@%0t: START tb.sendByteUart(%b)",$time,wdata);

		@(posedge clk);
		pad_tx_tb_uart <= 0;
		i<=0;
		repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);

		repeat(UART_NUM_DWORD_BITS)
		begin
			i<=i+1;
			pad_tx_tb_uart <= wdata[i];
			repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);
		end

		repeat(UART_NUM_STOP_BITS)
		begin
			pad_tx_tb_uart <= 1;
			repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);
		end
		$display("@%0t: END tb.sendByteUart(%b)",$time,wdata);
	end
endtask


task recvByteUart;
	output reg [7:0] rdata;
		begin
		$display("@%0t: START tb.recvByteUart()",$time);


	while(pad_rx_uart_tb!=0)
		@(negedge pad_rx_uart_tb);
		
	$display("@%0t: uart.recv() startbit: %b",$time,pad_rx_uart_tb);

	repeat(UART_NUM_CLK_TICKS_BIT/2) @(posedge clk);


		repeat(UART_NUM_DWORD_BITS)
		begin
			repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);
			rdata <= {pad_rx_uart_tb , rdata[UART_NUM_DWORD_BITS-1:1]};
		end


		repeat(UART_NUM_STOP_BITS)
		begin
			repeat(UART_NUM_CLK_TICKS_BIT) @(posedge clk);
			if(pad_rx_uart_tb!=1)
				$display("@%0t: ERROR tb.recvByteUart() WRONG STOP BIT",$time);

		end

	$display("@%0t: END tb.recvByteUart(%b)",$time,rdata);
end
endtask




wire [1:0] mode = `KEY_192;
wire encryption = 1'b1;
 
wire [0:255] key_128_bit = 256'h000102030405060708090a0b0c0d0e0f00000000000000000000000000000000;
wire [0:255] key_192_bit = 256'h000102030405060708090a0b0c0d0e0f10111213141516170000000000000000;
wire [0:255] key_256_bit = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;

wire [0:127] test_ptx = 128'h00112233445566778899aabbccddeeff;

wire [0:127] ctx_128 = 128'h69c4e0d86a7b0430d8cdb78070b4c55a;
wire [0:127] ctx_192 = 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
wire [0:127] ctx_256 = 128'h8ea2b7ca516745bfeafc49904b496089;

reg [0:255] input_key;
wire [7:0] input_key_bytes[0:31];

reg [0:127] start_value;
wire [7:0] start_value_bytes[0:15];

reg [0:127] final_reference;
reg [7:0] result[0:15];

always@(*)
begin
    case(mode)
        `KEY_128:
            begin
            input_key = key_128_bit;
            start_value = ctx_128;

            final_reference = ctx_128;
            end
        `KEY_192:
            begin
            input_key = key_192_bit;
            start_value = ctx_192;

            final_reference = ctx_192;
            end
        `KEY_256:
            begin
            input_key = key_256_bit;
            start_value = ctx_256;

            final_reference = ctx_256;
            end
        default:
            begin
            input_key = 256'h0;
            start_value = {64{2'b10}};

            final_reference = {64{2'b10}};
            end
    endcase
    
    if(encryption)
        start_value = test_ptx;
    else
        final_reference = test_ptx;
end

genvar k;
generate
    for(k=0; k<32; k=k+1)
    begin: split_key_bytes
        assign input_key_bytes[k] = input_key[8*k:8*(k+1)-1]; 
    end
    
    for(k=0; k<16; k=k+1)
    begin: split_ptx_ctx_i
        assign start_value_bytes[k] = start_value[8*k:8*(k+1)-1];
    end
endgenerate




always #HALF_CLK_PERIOD clk = ~clk;




initial
begin:initial_tb
    automatic integer i;
    integer cnt;

	
	clk <= 0;
  	rst = 0;
	pad_tx_tb_uart = 1;
	recv_data =0;
	repeat(2) @(posedge clk);
  	rst = 1;
	
	repeat(2) @(posedge clk);
	

	sendByteUart({1'b1, mode, 5'd0});

	cnt = 0;
	repeat(32)
	begin
	   sendByteUart(input_key_bytes[cnt]);
	   cnt=cnt+1;
    end
    
    repeat(3)
    begin

        sendByteUart({1'b0, mode, 1'b1, encryption, 3'd0});

        cnt = 0;
        repeat(16)
        begin
            sendByteUart(start_value_bytes[cnt]);
            cnt=cnt+1;
        end
        

        cnt = 0;
        repeat(16)	
        begin
            recvByteUart(recv_data);
            result[cnt]=recv_data;
            cnt=cnt+1;
        end
        
        $write("#################\n");
        for(i=0;i<16;i=i+1)
           $write("%h",result[i]);
        $write("\n%h\n", final_reference);
        $write("#################\n");
    end
	
	#20 $finish;
end

endmodule