data/full_repos/permissive/192147978/control_unit.v
 line:1 column:1: Illegal character '\x00'
data/verilator_xmls/6efaade2-8ae4-456c-896a-127caf060425.xml
module control_unit  (
   	 clk,
   	 reset,
   	 instr_op,
   	 reg_dst,
   	 branch,
   	 mem_read,
   	 mem_to_reg,
   	 alu_op,
   	 mem_write,
   	 alu_src,
   	 reg_write
	);
    

    input [5:0] instr_op;
    input clk;
    input reset;

    output reg_dst;
    output branch;
    output mem_read;
    output mem_to_reg;
    output [1:0] alu_op;
    output mem_write;
    output alu_src;
    output reg_write;

    wire clk;
    wire reset;
    wire [5:0] instr_op;

    reg reg_dst;
    reg branch;
    reg mem_read;
    reg mem_to_reg;
    reg [1:0] alu_op;
    reg mem_write;
    reg alu_src;
    reg reg_write;
    
always @ (posedge clk)
begin: LAB03
    case (instr_op)
   	 6'b000000:
   		 begin
   			 reg_dst = 1'b1;
   			 alu_src = 1'b0;
   			 mem_to_reg = 1'b0;
   			 reg_write = 1'b1;
   			 mem_read = 1'b0;
   			 mem_write = 1'b0;
   			 branch = 1'b0;
   			 alu_op = 2'b10;
   		 end
   	 6'b100011:
   		 begin
   			 reg_dst = 1'b0;
   			 alu_src = 1'b1;
   			 mem_to_reg = 1'b1;
   			 reg_write = 1'b1;
   			 mem_read = 1'b1;
   			 mem_write = 1'b0;
   			 branch = 1'b0;
   			 alu_op = 2'b00;
   		 end
   	 6'b101011:
   		 begin
   			 reg_dst = 1'bx;
   			 alu_src = 1'b1;
   			 mem_to_reg = 1'bx;
   			 reg_write = 1'b0;
   			 mem_read = 1'b0;
   			 mem_write = 1'b1;
   			 branch = 1'b0;
   			 alu_op = 2'b00;
   		 end
   	 6'b000100:
   		 begin
   			 reg_dst = 1'bx;
   			 alu_src = 1'b0;
   			 mem_to_reg = 1'bx;
   			 reg_write = 1'b0;
   			 mem_read = 1'b0;
   			 mem_write = 1'b0;
   			 branch = 1'b1;
   			 alu_op = 2'b01;
   		 end
   	 6'b001000:
   		 begin
   			 reg_dst = 1'b0;
   			 alu_src = 1'b1;
   			 mem_to_reg = 1'b0;
   			 reg_write = 1'b1;
   			 mem_read = 1'b0;
   			 mem_write = 1'b0;
   			 branch = 1'b0;
   			 alu_op = 2'b00;
   		 end
   	 default: begin
   		 reg_dst = 1'b0;
   		 alu_src = 1'b0;
   		 mem_to_reg = 1'b0;
   		 reg_write = 1'b0;
   		 mem_read = 1'b0;
   		 mem_write = 1'b0;
   		 branch = 1'b0;
   		 alu_op = 2'b00;
   	 end
    endcase
end
    
endmodule
module control_unit  (
   	 clk,
   	 reset,
   	 instr_op,
   	 reg_dst,
   	 branch,
   	 mem_read,
   	 mem_to_reg,
   	 alu_op,
   	 mem_write,
   	 alu_src,
   	 reg_write
	);

    

    input [5:0] instr_op;
    input clk;
    input reset;

    output reg_dst;
    output branch;
    output mem_read;
    output mem_to_reg;
    output [1:0] alu_op;
    output mem_write;
    output alu_src;
    output reg_write;

    wire clk;
    wire reset;
    wire [5:0] instr_op;

    reg reg_dst;
    reg branch;
    reg mem_read;
    reg mem_to_reg;
    reg [1:0] alu_op;
    reg mem_write;
    reg alu_src;
    reg reg_write;
    
always @ (posedge clk)
begin: LAB03
    case (instr_op)
   	 6'b000000:
   		 begin
   			 reg_dst = 1'b1;
   			 alu_src = 1'b0;
   			 mem_to_reg = 1'b0;
   			 reg_write = 1'b1;
   			 mem_read = 1'b0;
   			 mem_write = 1'b0;
   			 branch = 1'b0;
   			 alu_op = 2'b10;
   		 end
   	 6'b100011:
   		 begin
   			 reg_dst = 1'b0;
   			 alu_src = 1'b1;
   			 mem_to_reg = 1'b1;
   			 reg_write = 1'b1;
   			 mem_read = 1'b1;
   			 mem_write = 1'b0;
   			 branch = 1'b0;
   			 alu_op = 2'b00;
   		 end
   	 6'b101011:
   		 begin
   			 reg_dst = 1'bx;
   			 alu_src = 1'b1;
   			 mem_to_reg = 1'bx;
   			 reg_write = 1'b0;
   			 mem_read = 1'b0;
   			 mem_write = 1'b1;
   			 branch = 1'b0;
   			 alu_op = 2'b00;
   		 end
   	 6'b000100:
   		 begin
   			 reg_dst = 1'bx;
   			 alu_src = 1'b0;
   			 mem_to_reg = 1'bx;
   			 reg_write = 1'b0;
   			 mem_read = 1'b0;
   			 mem_write = 1'b0;
   			 branch = 1'b1;
   			 alu_op = 2'b01;
   		 end
   	 6'b001000:
   		 begin
   			 reg_dst = 1'b0;
   			 alu_src = 1'b1;
   			 mem_to_reg = 1'b0;
   			 reg_write = 1'b1;
   			 mem_read = 1'b0;
   			 mem_write = 1'b0;
   			 branch = 1'b0;
   			 alu_op = 2'b00;
   		 end
   	 default: begin
   		 reg_dst = 1'b0;
   		 alu_src = 1'b0;
   		 mem_to_reg = 1'b0;
   		 reg_write = 1'b0;
   		 mem_read = 1'b0;
   		 mem_write = 1'b0;
   		 branch = 1'b0;
   		 alu_op = 2'b00;
   	 end
    endcase
end
    
endmodule