data/full_repos/permissive/162571337/multiplers/8x7_unsigned/pareto_pwr_mre/mul8x7u_6PC.v
data/verilator_xmls/f579bb20-ce1a-4723-9501-dad8eb0cd5a8.xml
module mul8x7u_6PC (
    A,
    B,
    O
);

input [7:0] A;
input [6:0] B;
output [14:0] O;

wire sig_151,sig_162,sig_195,sig_196,sig_205,sig_207,sig_240,sig_241,sig_242,sig_243,sig_244,sig_249,sig_250,sig_251,sig_252,sig_280,sig_281,sig_282,sig_283,sig_284;
wire sig_285,sig_286,sig_287,sig_288,sig_289;

assign sig_151 = A[7] & B[3];
assign sig_162 = A[7] & B[4];
assign sig_195 = sig_151 ^ sig_162;
assign sig_196 = sig_151 & B[4];
assign sig_205 = A[6] & B[5];
assign sig_207 = A[7] & B[5];
assign sig_240 = sig_196 ^ sig_207;
assign sig_241 = sig_196 & B[5];
assign sig_242 = sig_207 & A[6];
assign sig_243 = sig_240 ^ sig_205;
assign sig_244 = sig_241 | sig_242;
assign sig_249 = A[3] & B[4];
assign sig_250 = A[5] & B[6];
assign sig_251 = A[6] & B[6];
assign sig_252 = A[7] & B[6];
assign sig_280 = sig_243 ^ sig_251;
assign sig_281 = sig_243 & sig_251;
assign sig_282 = sig_280 & sig_250;
assign sig_283 = sig_280 ^ sig_250;
assign sig_284 = sig_281 | sig_282;
assign sig_285 = sig_244 ^ sig_252;
assign sig_286 = sig_244 & sig_252;
assign sig_287 = A[7] & sig_284;
assign sig_288 = sig_285 ^ sig_284;
assign sig_289 = sig_286 | sig_287;

assign O[14] = sig_289;
assign O[13] = sig_288;
assign O[12] = sig_283;
assign O[11] = sig_195;
assign O[10] = sig_249;
assign O[9] = sig_283;
assign O[8] = sig_286;
assign O[7] = sig_242;
assign O[6] = 1'b0;
assign O[5] = 1'b0;
assign O[4] = sig_195;
assign O[3] = 1'b0;
assign O[2] = sig_252;
assign O[1] = sig_283;
assign O[0] = 1'b0;

endmodule
module mul8x7u_6PC (
    A,
    B,
    O
);


input [7:0] A;
input [6:0] B;
output [14:0] O;

wire sig_151,sig_162,sig_195,sig_196,sig_205,sig_207,sig_240,sig_241,sig_242,sig_243,sig_244,sig_249,sig_250,sig_251,sig_252,sig_280,sig_281,sig_282,sig_283,sig_284;
wire sig_285,sig_286,sig_287,sig_288,sig_289;

assign sig_151 = A[7] & B[3];
assign sig_162 = A[7] & B[4];
assign sig_195 = sig_151 ^ sig_162;
assign sig_196 = sig_151 & B[4];
assign sig_205 = A[6] & B[5];
assign sig_207 = A[7] & B[5];
assign sig_240 = sig_196 ^ sig_207;
assign sig_241 = sig_196 & B[5];
assign sig_242 = sig_207 & A[6];
assign sig_243 = sig_240 ^ sig_205;
assign sig_244 = sig_241 | sig_242;
assign sig_249 = A[3] & B[4];
assign sig_250 = A[5] & B[6];
assign sig_251 = A[6] & B[6];
assign sig_252 = A[7] & B[6];
assign sig_280 = sig_243 ^ sig_251;
assign sig_281 = sig_243 & sig_251;
assign sig_282 = sig_280 & sig_250;
assign sig_283 = sig_280 ^ sig_250;
assign sig_284 = sig_281 | sig_282;
assign sig_285 = sig_244 ^ sig_252;
assign sig_286 = sig_244 & sig_252;
assign sig_287 = A[7] & sig_284;
assign sig_288 = sig_285 ^ sig_284;
assign sig_289 = sig_286 | sig_287;

assign O[14] = sig_289;
assign O[13] = sig_288;
assign O[12] = sig_283;
assign O[11] = sig_195;
assign O[10] = sig_249;
assign O[9] = sig_283;
assign O[8] = sig_286;
assign O[7] = sig_242;
assign O[6] = 1'b0;
assign O[5] = 1'b0;
assign O[4] = sig_195;
assign O[3] = 1'b0;
assign O[2] = sig_252;
assign O[1] = sig_283;
assign O[0] = 1'b0;

endmodule