data/full_repos/permissive/175132042/rtl/system_controller/system_controller_altera.v
None: at end of input
1: b'%Error: data/full_repos/permissive/175132042/rtl/system_controller/system_controller_altera.v:24: Cannot find file containing module: \'altera_syscon_pll\'\n   altera_syscon_pll pll(\n   ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/rtl/system_controller,data/full_repos/permissive/175132042/altera_syscon_pll\n             data/full_repos/permissive/175132042/rtl/system_controller,data/full_repos/permissive/175132042/altera_syscon_pll.v\n             data/full_repos/permissive/175132042/rtl/system_controller,data/full_repos/permissive/175132042/altera_syscon_pll.sv\n             altera_syscon_pll\n             altera_syscon_pll.v\n             altera_syscon_pll.sv\n             obj_dir/altera_syscon_pll\n             obj_dir/altera_syscon_pll.v\n             obj_dir/altera_syscon_pll.sv\n%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/system_controller/system_controller_altera.v:53: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'rst_count\' generates 4 bits.\n                                                                                                        : ... In instance system_controller_altera\n           if (rst_count) begin\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module system_controller_altera (

   clk_i, rst_i, nrst_i,

   clk_sys_i, rst_sys_i
   ) ;
   input wire clk_sys_i;
   input wire rst_sys_i;
   
   output wire clk_i;
   output reg  rst_i;
   output wire nrst_i;
   wire        LOCKED;
   
   altera_syscon_pll pll(
                         .areset(rst_sys_i),
	                     .inclk0(clk_sys_i),
	                     .c0(clk_i),
	                     .locked(LOCKED)
                         );




   reg [3:0]  rst_count;   




   assign nrst_i = ~rst_i;







   always @(posedge clk_sys_i)
     if (rst_sys_i | ~LOCKED) begin
        rst_i <= 1;       
        rst_count <= 4'hF;        
     end else begin
        if (LOCKED) begin
           if (rst_count) begin
              rst_count <= rst_count - 1;              
           end else begin
              rst_i <= 0;              
           end           
        end        
     end
     
endmodule
module system_controller_altera (

   clk_i, rst_i, nrst_i,

   clk_sys_i, rst_sys_i
   ) ;

   input wire clk_sys_i;
   input wire rst_sys_i;
   
   output wire clk_i;
   output reg  rst_i;
   output wire nrst_i;
   wire        LOCKED;
   
   altera_syscon_pll pll(
                         .areset(rst_sys_i),
	                     .inclk0(clk_sys_i),
	                     .c0(clk_i),
	                     .locked(LOCKED)
                         );




   reg [3:0]  rst_count;   




   assign nrst_i = ~rst_i;







   always @(posedge clk_sys_i)
     if (rst_sys_i | ~LOCKED) begin
        rst_i <= 1;       
        rst_count <= 4'hF;        
     end else begin
        if (LOCKED) begin
           if (rst_count) begin
              rst_count <= rst_count - 1;              
           end else begin
              rst_i <= 0;              
           end           
        end        
     end
     
endmodule