data/full_repos/permissive/123796236/mips_pipeline.v
 line:100: before: "PC_reset"
1: b'%Error: data/full_repos/permissive/123796236/mips_pipeline.v:99: syntax error, unexpected \'@\'\n@(posedge clk)\n^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/mips_pipeline.v:277: Unsupported: Ignoring delay on this delayed statement.\n #100 clk <= ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module test_mips_pipeline();
reg clk;
mips_pipeline mp(clk);

initial begin
	clk = 0;
end
always
	begin
	#100 clk <= ~clk;
	end
endmodule
module test_mips_pipeline();

reg clk;
mips_pipeline mp(clk);

initial begin
	clk = 0;
end
always
	begin
	#100 clk <= ~clk;
	end
endmodule