data/full_repos/permissive/178917770/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/178917770/testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n reset <= 1; # 22; reset <= 0;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/178917770/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n clk <= 1; # 10; clk <= 0; # 10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/178917770/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n clk <= 1; # 10; clk <= 0; # 10;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/178917770/testbench.v:106: Bit extraction of array[127:0] requires 7 bit index, not 8 bits.\n                                                                    : ... In instance testbench.dut.imem\n  assign rd = RAM[a];  \n                 ^\n%Error: data/full_repos/permissive/178917770/testbench.v:75: Cannot find file containing module: \'processor\'\n  processor proc( .clk(clk), .reset(reset), .PC(PC), .Instr(Instr), .MemWrite(MemWrite), .ALUResult(DataAdr), .WriteData(WriteData), .ReadData(ReadData), .ALUControl(ALUControl), .AdrRd(AdrRd), .AdrRa(AdrRa), .AdrRb(AdrRb) ,.BeqFlag(BeqFlag) , .Beq(Beq) );\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/178917770,data/full_repos/permissive/178917770/processor\n             data/full_repos/permissive/178917770,data/full_repos/permissive/178917770/processor.v\n             data/full_repos/permissive/178917770,data/full_repos/permissive/178917770/processor.sv\n             processor\n             processor.v\n             processor.sv\n             obj_dir/processor\n             obj_dir/processor.v\n             obj_dir/processor.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top(input clk, reset, 
           output [3:0] WriteData, DataAdr,
           output [7:0] PC, 
output MemWrite,BeqFlag,Beq,
           output [1:0] ALUControl,
            output  [1:0] AdrRd,
                 output [1:0] AdrRa,
                 output  [1:0] AdrRb);

  
  wire  [3:0] ReadData;
  wire [10:0] Instr;

  processor proc( .clk(clk), .reset(reset), .PC(PC), .Instr(Instr), .MemWrite(MemWrite), .ALUResult(DataAdr), .WriteData(WriteData), .ReadData(ReadData), .ALUControl(ALUControl), .AdrRd(AdrRd), .AdrRa(AdrRa), .AdrRb(AdrRb) ,.BeqFlag(BeqFlag) , .Beq(Beq) );
  imem imem( .a(PC), .rd(Instr) );
  dmem dmem( .clk(clk), .we(MemWrite), .a(DataAdr), .wd(WriteData), .rd(ReadData) );

endmodule
module top(input clk, reset, 
           output [3:0] WriteData, DataAdr,
           output [7:0] PC, 
output MemWrite,BeqFlag,Beq,
           output [1:0] ALUControl,
            output  [1:0] AdrRd,
                 output [1:0] AdrRa,
                 output  [1:0] AdrRb);


  
  wire  [3:0] ReadData;
  wire [10:0] Instr;

  processor proc( .clk(clk), .reset(reset), .PC(PC), .Instr(Instr), .MemWrite(MemWrite), .ALUResult(DataAdr), .WriteData(WriteData), .ReadData(ReadData), .ALUControl(ALUControl), .AdrRd(AdrRd), .AdrRa(AdrRa), .AdrRb(AdrRb) ,.BeqFlag(BeqFlag) , .Beq(Beq) );
  imem imem( .a(PC), .rd(Instr) );
  dmem dmem( .clk(clk), .we(MemWrite), .a(DataAdr), .wd(WriteData), .rd(ReadData) );

endmodule