data/full_repos/permissive/117439233/hdl/src/hazzard_detection_unit.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/117439233/hdl/src/hazzard_detection_unit.v:28: Signal definition not found, creating implicitly: \'EN\'\n assign EN = (Registers[RD_Address_A] || Registers[RD_Address_B] || Registers[RD_Address_C]);\n        ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module hazzard_detection_unit(
	input CLK,
	input RST,
	input WR,
	input WB_WR,
	input [3:0] RD_Address_A,
	input [3:0] RD_Address_B,
	input [3:0] RD_Address_C,
	input [3:0] WR_Address,
	input [3:0] WB_Address,
	output STALL
    );
    reg STALL_EN;
	reg [15:0] Registers;

	assign EN = (Registers[RD_Address_A] || Registers[RD_Address_B] || Registers[RD_Address_C]);
	assign STALL = ~STALL_EN && EN;

    always @ (posedge CLK) begin
        if(RST)
            STALL_EN <= 1'b0;
        else if(~STALL_EN && EN)
            STALL_EN <= 1'b1;
        else
            STALL_EN <= 1'b0;
    end

	always @ (posedge CLK) begin
        if (RST)
            Registers <= 16'b0;
        else begin
            Registers[WR_Address] = (WR_Address == 0) ? 1'b0 : WR;
            Registers[WB_Address] = (WB_Address == 0) ? 1'b0 : ~WB_WR;
        end
    end
endmodule
module hazzard_detection_unit(
	input CLK,
	input RST,
	input WR,
	input WB_WR,
	input [3:0] RD_Address_A,
	input [3:0] RD_Address_B,
	input [3:0] RD_Address_C,
	input [3:0] WR_Address,
	input [3:0] WB_Address,
	output STALL
    );

    reg STALL_EN;
	reg [15:0] Registers;

	assign EN = (Registers[RD_Address_A] || Registers[RD_Address_B] || Registers[RD_Address_C]);
	assign STALL = ~STALL_EN && EN;

    always @ (posedge CLK) begin
        if(RST)
            STALL_EN <= 1'b0;
        else if(~STALL_EN && EN)
            STALL_EN <= 1'b1;
        else
            STALL_EN <= 1'b0;
    end

	always @ (posedge CLK) begin
        if (RST)
            Registers <= 16'b0;
        else begin
            Registers[WR_Address] = (WR_Address == 0) ? 1'b0 : WR;
            Registers[WB_Address] = (WB_Address == 0) ? 1'b0 : ~WB_WR;
        end
    end
endmodule