data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_serializer.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/0845ed62-8bf9-4616-94c8-13b35f58a934.xml
module stream_serializer #(
  parameter DataBits = 8,
  parameter Ratio = 2)
(
  input                       clk,
  input                       rst,

  input                       in_valid,
  output                      in_ready,
  input [Ratio*DataBits-1:0]  in_data,

  output                      out_valid,
  input                       out_ready,
  output [DataBits-1:0]       out_data
);

  reg [Ratio-1:0]              count;
  reg [(Ratio-1)*DataBits-1:0] data_r;

  always @(posedge clk) begin


    if (out_valid & out_ready) begin
      count <= (count[Ratio-1]) ? 1 : count << 1;
    end


    if (out_ready) begin
      if (count[0] & in_valid) begin

        data_r <= in_data[Ratio*DataBits-1:DataBits];
      end else begin

        data_r <= data_r >> DataBits;
      end
    end

    if (rst) begin
      count <= 1;
    end
  end

  assign in_ready  = count[0] ? out_ready : 1'b0;
  assign out_valid = count[0] ? in_valid  : 1'b1;
  assign out_data  = count[0] ? in_data[DataBits-1:0] : data_r[DataBits-1:0];

endmodule
module stream_serializer #(
  parameter DataBits = 8,
  parameter Ratio = 2)
(
  input                       clk,
  input                       rst,

  input                       in_valid,
  output                      in_ready,
  input [Ratio*DataBits-1:0]  in_data,

  output                      out_valid,
  input                       out_ready,
  output [DataBits-1:0]       out_data
);


  reg [Ratio-1:0]              count;
  reg [(Ratio-1)*DataBits-1:0] data_r;

  always @(posedge clk) begin


    if (out_valid & out_ready) begin
      count <= (count[Ratio-1]) ? 1 : count << 1;
    end


    if (out_ready) begin
      if (count[0] & in_valid) begin

        data_r <= in_data[Ratio*DataBits-1:DataBits];
      end else begin

        data_r <= data_r >> DataBits;
      end
    end

    if (rst) begin
      count <= 1;
    end
  end

  assign in_ready  = count[0] ? out_ready : 1'b0;
  assign out_valid = count[0] ? in_valid  : 1'b1;
  assign out_data  = count[0] ? in_data[DataBits-1:0] : data_r[DataBits-1:0];

endmodule