data/full_repos/permissive/107735152/src/datarate.v
data/verilator_xmls/6abe8c69-657a-465e-929f-8a59dc008073.xml
module datarate (samplePoint, samplePointFD, edl, brs, brsStop, samplePointOUT);

input wire samplePoint, samplePointFD, edl, brs, brsStop;
output wire samplePointOUT;

wire switch; 

assign switch = edl & brs & brsStop;

assign samplePointOUT = (switch == 0) ? samplePoint : samplePointFD;

endmodule
module datarate (samplePoint, samplePointFD, edl, brs, brsStop, samplePointOUT);


input wire samplePoint, samplePointFD, edl, brs, brsStop;
output wire samplePointOUT;

wire switch; 

assign switch = edl & brs & brsStop;

assign samplePointOUT = (switch == 0) ? samplePoint : samplePointFD;

endmodule