data/full_repos/permissive/136992793/hdl/streamcounter.v
data/verilator_xmls/351678bc-00f8-4b09-b050-2e0c7678868f.xml
module streamcounter #
  (
    parameter integer C_AXIS_BYTEWIDTH = 4
  )
  (

    input clk,
    input resetn,
  

    input wire  input_s_axis_tvalid,
    input wire [(C_AXIS_BYTEWIDTH*8)-1: 0] input_s_axis_tdata,
    input wire [C_AXIS_BYTEWIDTH-1: 0] input_s_axis_tstrb,
    input wire  input_s_axis_tlast,
    output wire  input_s_axis_tready,
  

    output wire  output_m_axis_tvalid,
    output wire [(C_AXIS_BYTEWIDTH*8)-1: 0] output_m_axis_tdata,
    output wire [C_AXIS_BYTEWIDTH-1: 0] output_m_axis_tstrb,
    output wire  output_m_axis_tlast,
    input wire  output_m_axis_tready,
  

    output reg [31:0] byte_count,
    output reg [31:0] tlast_count,
    output reg [31:0] last_tlast
  );

  always @(posedge clk) begin
    if (~resetn) begin
      byte_count <= 0;
      tlast_count <= 0;
      last_tlast <= 0;
    end


    if(input_s_axis_tvalid & output_m_axis_tready) begin
      byte_count <= byte_count + C_AXIS_BYTEWIDTH;
    end


    if(input_s_axis_tlast & input_s_axis_tvalid & output_m_axis_tready) begin
      tlast_count <= tlast_count + 1;
      last_tlast <= byte_count + C_AXIS_BYTEWIDTH;
    end
  end



  assign output_m_axis_tvalid = input_s_axis_tvalid;
  assign input_s_axis_tready = output_m_axis_tready;
  assign output_m_axis_tdata = input_s_axis_tdata;
  assign output_m_axis_tstrb = input_s_axis_tstrb;
  assign output_m_axis_tlast = input_s_axis_tlast;

endmodule
module streamcounter #
  (
    parameter integer C_AXIS_BYTEWIDTH = 4
  )
  (

    input clk,
    input resetn,
  

    input wire  input_s_axis_tvalid,
    input wire [(C_AXIS_BYTEWIDTH*8)-1: 0] input_s_axis_tdata,
    input wire [C_AXIS_BYTEWIDTH-1: 0] input_s_axis_tstrb,
    input wire  input_s_axis_tlast,
    output wire  input_s_axis_tready,
  

    output wire  output_m_axis_tvalid,
    output wire [(C_AXIS_BYTEWIDTH*8)-1: 0] output_m_axis_tdata,
    output wire [C_AXIS_BYTEWIDTH-1: 0] output_m_axis_tstrb,
    output wire  output_m_axis_tlast,
    input wire  output_m_axis_tready,
  

    output reg [31:0] byte_count,
    output reg [31:0] tlast_count,
    output reg [31:0] last_tlast
  );


  always @(posedge clk) begin
    if (~resetn) begin
      byte_count <= 0;
      tlast_count <= 0;
      last_tlast <= 0;
    end


    if(input_s_axis_tvalid & output_m_axis_tready) begin
      byte_count <= byte_count + C_AXIS_BYTEWIDTH;
    end


    if(input_s_axis_tlast & input_s_axis_tvalid & output_m_axis_tready) begin
      tlast_count <= tlast_count + 1;
      last_tlast <= byte_count + C_AXIS_BYTEWIDTH;
    end
  end



  assign output_m_axis_tvalid = input_s_axis_tvalid;
  assign input_s_axis_tready = output_m_axis_tready;
  assign output_m_axis_tdata = input_s_axis_tdata;
  assign output_m_axis_tstrb = input_s_axis_tstrb;
  assign output_m_axis_tlast = input_s_axis_tlast;

endmodule