data/full_repos/permissive/208325333/Files/control_uart.v
 line:260: before: "-"
1: b'%Error: data/full_repos/permissive/208325333/Files/control_uart.v:8: Cannot find include file: baudgen.vh\n`include "baudgen.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208325333/Files,data/full_repos/permissive/208325333/baudgen.vh\n             data/full_repos/permissive/208325333/Files,data/full_repos/permissive/208325333/baudgen.vh.v\n             data/full_repos/permissive/208325333/Files,data/full_repos/permissive/208325333/baudgen.vh.sv\n             baudgen.vh\n             baudgen.vh.v\n             baudgen.vh.sv\n             obj_dir/baudgen.vh\n             obj_dir/baudgen.vh.v\n             obj_dir/baudgen.vh.sv\n%Error: data/full_repos/permissive/208325333/Files/control_uart.v:21: Define or directive not defined: \'`B12Mbauds\'\nparameter BAUD = `B12Mbauds;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/208325333/Files/control_uart.v:21: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BAUD = `B12Mbauds;\n                           ^\n%Error: Exiting due to 3 error(s)\n'
module control_uart (input wire clk,
                input wire rst,
                input wire dtr,
                input wire VSYNC,
                input wire [7:0] data,
                output wire ready,
                output wire tx
               );


parameter BAUD = `B12Mbauds;



reg [7:0] data_r;



reg transmit;


reg start;


reg uart_flag=0;     






uart_tx #(.BAUD(BAUD))
  uart_tx (
    .clk(clk),
    .rst(rst),
    .data(data_r),
    .start(start),
    .ready(ready),
    .tx(tx)
  );
 reg new_img=1;
 reg cena=0;
 reg VSYNC_ant=0;


always @(posedge clk) begin
  if(rst==1) begin
	transmit <= 0;
	new_img <= 0;
	VSYNC_ant<=0;
  end
  
  else begin
	VSYNC_ant<=VSYNC;
  
	  if(VSYNC && VSYNC_ant==0) begin
		transmit <= 1;
		new_img <= 1;
	  end
	  
	  else if(car_count==11 && new_img && cena) begin
		transmit <= 0;
		new_img <= 0;
	  end 
	  
	  else if(new_img) begin
		transmit <= 1;
	  end 
	  
	  else begin
		transmit <= dtr;
	  end
  end
  
end




localparam IDLE = 0;
localparam TXCAR = 2'd1;
localparam WAITING = 2'd2;
localparam SENDING = 2'd3;
localparam END = 4;


reg [2:0] state;


always @(posedge clk) begin

  if (rst == 1)

    state <= IDLE;

  else begin
    uart_flag <= 0;
    cena <= 0;
  	
    case (state)
    
      IDLE: 
        if (transmit == 1) state <= TXCAR;
        else state <= IDLE;
        
        
      TXCAR: 
        if (ready == 1) state <= WAITING;
        else state <= TXCAR;
        
        
      WAITING: 
        if (ready == 0) state <= SENDING;
        else state <= WAITING;
        
        
      SENDING: 
        if (ready == 1) begin
        	state <= END;
          if (new_img) cena <= 1;	
      	  else
      		  uart_flag <= 1;
		end
		
        else state <= SENDING;
        
        
      END: begin
        if (uart_flag || cena) begin
        	state <= IDLE;
      		uart_flag <= 0;
      		cena <= 0;
        end
        
        else state <= END;
	   end
	  

      default:
         state <= IDLE;
        

    endcase
  end
end

always @(posedge clk) begin
  
  case (state)
    IDLE: begin
      start <= 0;
    end

    TXCAR: begin
      start <= 1;
    end

    WAITING: begin
      start <= 0;	
    end

    SENDING: begin
      start <= 0;	
    end

    END: begin
      start <= 0;
    end

    default: begin
      start <= 0;
    end
  endcase
end



always @(posedge clk) begin
 if(new_img) begin
  case (car_count)
    0: data_r <= "\n";
    1: data_r <= "\n";
    2: data_r <= "N";
    3: data_r <= "e";
    4: data_r <= "w";
    5: data_r <= " ";
    6: data_r <= "I";
    7: data_r <= "m";
    8: data_r <= "g";
    9: data_r <= "\r";
    10: data_r <= "\n";
    11: data_r <= "\n";
    default: data_r <= ".";
  endcase
 end
  else
    data_r <= data;
  
end  


reg [4:0] car_count;

always @(posedge clk) begin
  if (rst == 1)
    car_count = 0;
  else if (car_count<11 && new_img && cena)
    car_count = car_count + 1;
  else if (car_count==11 && !new_img) begin
    car_count = 0;
  end
end

endmodule
module control_uart (input wire clk,
                input wire rst,
                input wire dtr,
                input wire VSYNC,
                input wire [7:0] data,
                output wire ready,
                output wire tx
               );



parameter BAUD = `B12Mbauds;



reg [7:0] data_r;



reg transmit;


reg start;


reg uart_flag=0;     






uart_tx #(.BAUD(BAUD))
  uart_tx (
    .clk(clk),
    .rst(rst),
    .data(data_r),
    .start(start),
    .ready(ready),
    .tx(tx)
  );
 reg new_img=1;
 reg cena=0;
 reg VSYNC_ant=0;


always @(posedge clk) begin
  if(rst==1) begin
	transmit <= 0;
	new_img <= 0;
	VSYNC_ant<=0;
  end
  
  else begin
	VSYNC_ant<=VSYNC;
  
	  if(VSYNC && VSYNC_ant==0) begin
		transmit <= 1;
		new_img <= 1;
	  end
	  
	  else if(car_count==11 && new_img && cena) begin
		transmit <= 0;
		new_img <= 0;
	  end 
	  
	  else if(new_img) begin
		transmit <= 1;
	  end 
	  
	  else begin
		transmit <= dtr;
	  end
  end
  
end




localparam IDLE = 0;
localparam TXCAR = 2'd1;
localparam WAITING = 2'd2;
localparam SENDING = 2'd3;
localparam END = 4;


reg [2:0] state;


always @(posedge clk) begin

  if (rst == 1)

    state <= IDLE;

  else begin
    uart_flag <= 0;
    cena <= 0;
  	
    case (state)
    
      IDLE: 
        if (transmit == 1) state <= TXCAR;
        else state <= IDLE;
        
        
      TXCAR: 
        if (ready == 1) state <= WAITING;
        else state <= TXCAR;
        
        
      WAITING: 
        if (ready == 0) state <= SENDING;
        else state <= WAITING;
        
        
      SENDING: 
        if (ready == 1) begin
        	state <= END;
          if (new_img) cena <= 1;	
      	  else
      		  uart_flag <= 1;
		end
		
        else state <= SENDING;
        
        
      END: begin
        if (uart_flag || cena) begin
        	state <= IDLE;
      		uart_flag <= 0;
      		cena <= 0;
        end
        
        else state <= END;
	   end
	  

      default:
         state <= IDLE;
        

    endcase
  end
end

always @(posedge clk) begin
  
  case (state)
    IDLE: begin
      start <= 0;
    end

    TXCAR: begin
      start <= 1;
    end

    WAITING: begin
      start <= 0;	
    end

    SENDING: begin
      start <= 0;	
    end

    END: begin
      start <= 0;
    end

    default: begin
      start <= 0;
    end
  endcase
end



always @(posedge clk) begin
 if(new_img) begin
  case (car_count)
    0: data_r <= "\n";
    1: data_r <= "\n";
    2: data_r <= "N";
    3: data_r <= "e";
    4: data_r <= "w";
    5: data_r <= " ";
    6: data_r <= "I";
    7: data_r <= "m";
    8: data_r <= "g";
    9: data_r <= "\r";
    10: data_r <= "\n";
    11: data_r <= "\n";
    default: data_r <= ".";
  endcase
 end
  else
    data_r <= data;
  
end  


reg [4:0] car_count;

always @(posedge clk) begin
  if (rst == 1)
    car_count = 0;
  else if (car_count<11 && new_img && cena)
    car_count = car_count + 1;
  else if (car_count==11 && !new_img) begin
    car_count = 0;
  end
end

endmodule