data/full_repos/permissive/101171422/de2-115/pllsim/pllsim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/pllsim/pllsim.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101171422/de2-115/pllsim/pllsim.v:8: Cannot find file containing module: \'atpll\'\n atpll a(rst, clk, c0, c1, c2, c3, c4);\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/101171422/de2-115/pllsim,data/full_repos/permissive/101171422/atpll\n             data/full_repos/permissive/101171422/de2-115/pllsim,data/full_repos/permissive/101171422/atpll.v\n             data/full_repos/permissive/101171422/de2-115/pllsim,data/full_repos/permissive/101171422/atpll.sv\n             atpll\n             atpll.v\n             atpll.sv\n             obj_dir/atpll\n             obj_dir/atpll.v\n             obj_dir/atpll.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pllsim_test();
	reg clk, rst;
	
	initial begin
		clk = 0;
		rst = 1;
	end
	
	always begin
		#10 clk = ~clk;
		    rst = 0;
	end
	
	pllsim p(rst, clk);
endmodule
module pllsim_test();

	reg clk, rst;
	
	initial begin
		clk = 0;
		rst = 1;
	end
	
	always begin
		#10 clk = ~clk;
		    rst = 0;
	end
	
	pllsim p(rst, clk);
endmodule