data/full_repos/permissive/209534045/src/wsg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:197: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:204: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:212: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n%Error: Exiting due to 3 warning(s)\n'
module WSGCORE
(
	input				RESET,
	input				WSGCLKx4,

	output			WROMCLK,
	output [7:0]	WROMADR,
	input  [3:0]	WROMDAT,

	input  [2:0]	W0,
	input  [2:0]	W1,
	input  [2:0]	W2,

	input  [3:0]	V0,
	input  [3:0]	V1,
	input  [3:0]	V2,

	input [19:0]	F0,
	input [15:0]	F1,
	input [15:0]	F2,

	output reg			outclk,
	output reg [7:0]	sndout
);

reg   [7:0] waveadr, cc1, cc2;

reg  [19:0] c0;
reg  [15:0] c1, c2;

reg   [3:0] wavevol;
wire  [7:0] waveout = wavevol * WROMDAT;

reg   [9:0] sndmix;
wire [10:0] sndmixdown = { 1'b0, sndmix };

reg   [1:0] phase;
always @ ( posedge WSGCLKx4 or posedge RESET ) begin

   if ( RESET ) begin
      phase  <= 0;
      sndout <= 0;
		outclk <= 0;
		cc1    <= 0;
		cc2    <= 0;
   end
   else begin

      case ( phase )

      0: begin
            sndout  <= ( sndmixdown[9:2] | {8{sndmixdown[10]}} );

				cc1     <= {W1,c1[15:11]};
				cc2     <= {W2,c2[15:11]};

            sndmix  <= 0;
            waveadr <= {W0,c0[19:15]};
            wavevol <= (F0!=0) ? V0 : 0;
         end

      1: begin
				outclk  <= 1'b1;
            sndmix  <= sndmix + waveout;

            waveadr <= cc1;
            wavevol <= (F1!=0) ? V1 : 0;
         end

      2: begin
            sndmix  <= sndmix + waveout;

            waveadr <= cc2;
            wavevol <= (F2!=0) ? V2 : 0;
         end

      3: begin
				outclk  <= 0;
            sndmix  <= sndmix + waveout;
         end

			default:;

      endcase

      phase <= phase+1;

      c0 <= c0 + F0;
      c1 <= c1 + F1;
      c2 <= c2 + F2;

   end

end

assign WROMCLK = ~WSGCLKx4;
assign WROMADR = waveadr;

endmodule
module WSGCORE
(
	input				RESET,
	input				WSGCLKx4,

	output			WROMCLK,
	output [7:0]	WROMADR,
	input  [3:0]	WROMDAT,

	input  [2:0]	W0,
	input  [2:0]	W1,
	input  [2:0]	W2,

	input  [3:0]	V0,
	input  [3:0]	V1,
	input  [3:0]	V2,

	input [19:0]	F0,
	input [15:0]	F1,
	input [15:0]	F2,

	output reg			outclk,
	output reg [7:0]	sndout
);


reg   [7:0] waveadr, cc1, cc2;

reg  [19:0] c0;
reg  [15:0] c1, c2;

reg   [3:0] wavevol;
wire  [7:0] waveout = wavevol * WROMDAT;

reg   [9:0] sndmix;
wire [10:0] sndmixdown = { 1'b0, sndmix };

reg   [1:0] phase;
always @ ( posedge WSGCLKx4 or posedge RESET ) begin

   if ( RESET ) begin
      phase  <= 0;
      sndout <= 0;
		outclk <= 0;
		cc1    <= 0;
		cc2    <= 0;
   end
   else begin

      case ( phase )

      0: begin
            sndout  <= ( sndmixdown[9:2] | {8{sndmixdown[10]}} );

				cc1     <= {W1,c1[15:11]};
				cc2     <= {W2,c2[15:11]};

            sndmix  <= 0;
            waveadr <= {W0,c0[19:15]};
            wavevol <= (F0!=0) ? V0 : 0;
         end

      1: begin
				outclk  <= 1'b1;
            sndmix  <= sndmix + waveout;

            waveadr <= cc1;
            wavevol <= (F1!=0) ? V1 : 0;
         end

      2: begin
            sndmix  <= sndmix + waveout;

            waveadr <= cc2;
            wavevol <= (F2!=0) ? V2 : 0;
         end

      3: begin
				outclk  <= 0;
            sndmix  <= sndmix + waveout;
         end

			default:;

      endcase

      phase <= phase+1;

      c0 <= c0 + F0;
      c1 <= c1 + F1;
      c2 <= c2 + F2;

   end

end

assign WROMCLK = ~WSGCLKx4;
assign WROMADR = waveadr;

endmodule