data/full_repos/permissive/184332405/control_tb.v
 line:28: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/184332405/control_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n #10 clk =! clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/184332405/control_tb.v:17: Unsupported or unknown PLI call: $monitor\n $monitor("%b, %b, %b", clk, Q, D);\n ^~~~~~~~\n%Error: data/full_repos/permissive/184332405/control_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("control.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/184332405/control_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/184332405/control_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #5 D = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/control_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #30 D = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/control_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #40 D = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/control_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10 D = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/control_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #20 D = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/control_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10 D = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/control_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #10 D = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/control_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #10 D = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/control_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: Exiting due to 3 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_tb;

reg D;
reg clk;
wire Q;

initial begin
	D   = 0;
	clk = 0;
end
	
always begin
	#10 clk =! clk;
end
	
initial begin
	$monitor("%b, %b, %b", clk, Q, D);
	$dumpfile("control.vcd");
	$dumpvars;
	#5	D = 1'b0;
	#30 D = 1'b1;
	#40 D = 1'b0;
	#10 D = 1'b1;
	#20 D = 1'b0;
	#10 D = 1'b1;
	#10 D = 1'b0;
	#10 D = 1'b1;
	#10 $finish;
end
control DUT( D, clk, Q );
endmodule
module control_tb;


reg D;
reg clk;
wire Q;

initial begin
	D   = 0;
	clk = 0;
end
	
always begin
	#10 clk =! clk;
end
	
initial begin
	$monitor("%b, %b, %b", clk, Q, D);
	$dumpfile("control.vcd");
	$dumpvars;
	#5	D = 1'b0;
	#30 D = 1'b1;
	#40 D = 1'b0;
	#10 D = 1'b1;
	#20 D = 1'b0;
	#10 D = 1'b1;
	#10 D = 1'b0;
	#10 D = 1'b1;
	#10 $finish;
end
control DUT( D, clk, Q );
endmodule