data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/regFile.v
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/regFile.v\n%Error: Exiting due to 4 error(s)\n'
module regfile #(parameter WIDTH = 16, REGBITS = 4)
                (input                clk, 
                 input                regwrite, 
                 input  [REGBITS-1:0] ra1, ra2, wa, 
                 input  [WIDTH-1:0]   wd, 
                 output [WIDTH-1:0]   rd1, rd2);

   reg  [WIDTH-1:0] RAM [(1<<REGBITS)-1:0]; 







   always @(posedge clk)
      if (regwrite) RAM[wa] <= wd;	

   assign rd1 = RAM[ra1];
   assign rd2 = RAM[ra2];
endmodule
module regfile #(parameter WIDTH = 16, REGBITS = 4)
                (input                clk, 
                 input                regwrite, 
                 input  [REGBITS-1:0] ra1, ra2, wa, 
                 input  [WIDTH-1:0]   wd, 
                 output [WIDTH-1:0]   rd1, rd2);


   reg  [WIDTH-1:0] RAM [(1<<REGBITS)-1:0]; 







   always @(posedge clk)
      if (regwrite) RAM[wa] <= wd;	

   assign rd1 = RAM[ra1];
   assign rd2 = RAM[ra2];
endmodule