data/full_repos/permissive/121203026/virtex6/bf16x16/matlab/verilog_files/TheController.v
1: b'%Warning-WIDTH: data/full_repos/permissive/121203026/virtex6/bf16x16/matlab/verilog_files/TheController.v:41: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                                                            : ... In instance TheController\nwire [3:0] input_signal = {iteration_done, finish, start};\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module TheController(input iteration_done_agu, finish, start, rst_global,
							clk,
							output reg write_enable, read_enable);

wire iteration_done =iteration_done_agu ;

parameter IDLE_STATE = 2'b00,
			 INIT_STATE = 2'b01,
			 PROC_STATE = 2'b11,
			 WAIT_STATE = 2'b10;

reg[1:0]    Next_State; 			 
reg[1:0] Current_State; 			 
wire [3:0] input_signal = {iteration_done, finish, start};


always@(*)
begin
	case(Current_State)
	IDLE_STATE:
		begin
			if(!start)
				begin
				Next_State   = IDLE_STATE;
				write_enable = 0;
				read_enable  = 0;
				end
			else
				begin
				Next_State   = INIT_STATE;
				write_enable = 0;
				read_enable  = 1;
				end
		end
	INIT_STATE:
		begin
				Next_State 	 = WAIT_STATE;
				write_enable = 0;
				read_enable  = 1;
		end
	WAIT_STATE:
		begin
				Next_State 	 = PROC_STATE;
				write_enable = 0;
				read_enable  = 0;
		end	
		
	PROC_STATE:
		begin
			if(finish)
				begin
				Next_State   = IDLE_STATE;
				write_enable = 0;
				read_enable  = 0;
				end
			else
				begin
				if(iteration_done)
					begin
					Next_State   = WAIT_STATE;
					write_enable = 1;
					read_enable  = 1;	
					end
				else
					begin
					Next_State   = PROC_STATE;
					write_enable = 0;
					read_enable  = 0;	
					end
				end
		end
	default:
		begin
				Next_State   = IDLE_STATE;
				write_enable = 0;
				read_enable  = 0;
		end
	endcase
end


always@(posedge clk)
begin
	if(rst_global)
		Current_State <= IDLE_STATE;
	else
		Current_State <= Next_State;
end
endmodule
module TheController(input iteration_done_agu, finish, start, rst_global,
							clk,
							output reg write_enable, read_enable);


wire iteration_done =iteration_done_agu ;

parameter IDLE_STATE = 2'b00,
			 INIT_STATE = 2'b01,
			 PROC_STATE = 2'b11,
			 WAIT_STATE = 2'b10;

reg[1:0]    Next_State; 			 
reg[1:0] Current_State; 			 
wire [3:0] input_signal = {iteration_done, finish, start};


always@(*)
begin
	case(Current_State)
	IDLE_STATE:
		begin
			if(!start)
				begin
				Next_State   = IDLE_STATE;
				write_enable = 0;
				read_enable  = 0;
				end
			else
				begin
				Next_State   = INIT_STATE;
				write_enable = 0;
				read_enable  = 1;
				end
		end
	INIT_STATE:
		begin
				Next_State 	 = WAIT_STATE;
				write_enable = 0;
				read_enable  = 1;
		end
	WAIT_STATE:
		begin
				Next_State 	 = PROC_STATE;
				write_enable = 0;
				read_enable  = 0;
		end	
		
	PROC_STATE:
		begin
			if(finish)
				begin
				Next_State   = IDLE_STATE;
				write_enable = 0;
				read_enable  = 0;
				end
			else
				begin
				if(iteration_done)
					begin
					Next_State   = WAIT_STATE;
					write_enable = 1;
					read_enable  = 1;	
					end
				else
					begin
					Next_State   = PROC_STATE;
					write_enable = 0;
					read_enable  = 0;	
					end
				end
		end
	default:
		begin
				Next_State   = IDLE_STATE;
				write_enable = 0;
				read_enable  = 0;
		end
	endcase
end


always@(posedge clk)
begin
	if(rst_global)
		Current_State <= IDLE_STATE;
	else
		Current_State <= Next_State;
end
endmodule