data/full_repos/permissive/132176809/vga_tb.v
1: b'%Error: data/full_repos/permissive/132176809/vga_tb.v:11: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile("test.vcd");\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/132176809/vga_tb.v:12: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0, test);\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/132176809/vga_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n     # 1 reset <= 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/132176809/vga_tb.v:14: Unsupported: wait statements\n     wait(vga_test.vcounter == 30);  \n     ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/132176809/vga_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n     # 1000;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/132176809/vga_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = !clk;\n         ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

  reg clk = 0;
  wire hsync;
  wire vsync;
  reg [7:0] pixels = 8'b00111100;
  reg reset = 1;


  initial begin
     $dumpfile("test.vcd");
     $dumpvars(0, test);
     # 1 reset <= 0;
     wait(vga_test.vcounter == 30);
     # 1000;
     $finish;
  end

  vga vga_test(.reset(reset), .pixels(pixels), .clk(clk));


  always #1 clk = !clk;

endmodule
module test;


  reg clk = 0;
  wire hsync;
  wire vsync;
  reg [7:0] pixels = 8'b00111100;
  reg reset = 1;


  initial begin
     $dumpfile("test.vcd");
     $dumpvars(0, test);
     # 1 reset <= 0;
     wait(vga_test.vcounter == 30);
     # 1000;
     $finish;
  end

  vga vga_test(.reset(reset), .pixels(pixels), .clk(clk));


  always #1 clk = !clk;

endmodule