data/full_repos/permissive/19572582/Lab3/lab3_part3.v
data/verilator_xmls/119c4759-008c-4b78-aee7-ea6db3e9d0ad.xml
module lab3_part3 (SW, LEDR, LEDG);

	input [1:0] SW;
	output [1:0] LEDR, LEDG;
	assign LEDR = SW;
	
	wire Q;

	MSDF F0(SW[1],SW[0],LEDG[0]);

endmodule
module lab3_part3 (SW, LEDR, LEDG);


	input [1:0] SW;
	output [1:0] LEDR, LEDG;
	assign LEDR = SW;
	
	wire Q;

	MSDF F0(SW[1],SW[0],LEDG[0]);

endmodule