data/full_repos/permissive/163494071/addition1/addtion1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/163494071/addition1/addtion1.v:254: Value too large for 5 bit number: 32\n   5\'d32:\n   ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/163494071/addition1/addtion1.v:20: Signal definition not found, creating implicitly: \'top\'\n  add f4(.a(cina[3]),.b(cinb[3]),.fro(term[2]),.Cout(top),.sum(cout[3]));\n                                                     ^~~\n%Error: Exiting due to 2 warning(s)\n'
module add(a,b,fro,Cout,sum);
	input a;
	input b;
	input fro;
	output Cout;
	output sum;
	
	assign {Cout,sum}=a+b+fro;
endmodule
module add(a,b,fro,Cout,sum);

	input a;
	input b;
	input fro;
	output Cout;
	output sum;
	
	assign {Cout,sum}=a+b+fro;
endmodule