data/full_repos/permissive/214823094/lab_7/project_1/project_1.srcs/sources_1/new/bus.v
data/verilator_xmls/7f7dd0f0-285f-46b7-bf12-d5571dcce98b.xml
module bus(
    input clk,
    input [14:0] SW,
    output [15:0] LED
    );
    
    wire myclk;
    wire [3:0] d1;
    wire [3:0] y;
    wire [15:0] light;
    clkdiv U0(clk,myclk);
    
    register U1(myclk,SW[7],d1[3:0],light[11:8]);
    assign LED[11:8]=light[11:8];
    register U2(myclk,SW[6],y[3:0],light[3:0]);
    assign LED[3:0]=light[3:0];
    register U3(myclk,SW[5],y[3:0],light[7:4]);
    assign LED[7:4]=light[7:4];
    ram2 U4(myclk,SW[0],SW[4:1],y[3:0],light[15:12]);
    assign LED[15:12]=light[15:12];
    
    MUX_2_1 U5(SW[12],SW[11:8],y[3:0],d1[3:0]);
    MUX_4_1 U6(SW[14:13],light[11:8],light[3:0],light[7:4],light[15:12],y[3:0]);
    
endmodule
module bus(
    input clk,
    input [14:0] SW,
    output [15:0] LED
    );

    
    wire myclk;
    wire [3:0] d1;
    wire [3:0] y;
    wire [15:0] light;
    clkdiv U0(clk,myclk);
    
    register U1(myclk,SW[7],d1[3:0],light[11:8]);
    assign LED[11:8]=light[11:8];
    register U2(myclk,SW[6],y[3:0],light[3:0]);
    assign LED[3:0]=light[3:0];
    register U3(myclk,SW[5],y[3:0],light[7:4]);
    assign LED[7:4]=light[7:4];
    ram2 U4(myclk,SW[0],SW[4:1],y[3:0],light[15:12]);
    assign LED[15:12]=light[15:12];
    
    MUX_2_1 U5(SW[12],SW[11:8],y[3:0],d1[3:0]);
    MUX_4_1 U6(SW[14:13],light[11:8],light[3:0],light[7:4],light[15:12],y[3:0]);
    
endmodule