data/full_repos/permissive/157101210/memReg.t.v
 line:116: before: "/"
1: b'%Error: data/full_repos/permissive/157101210/memReg.t.v:1: Cannot find include file: memReg.v\n`include "memReg.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/memReg.v\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/memReg.v.v\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/memReg.v.sv\n             memReg.v\n             memReg.v.v\n             memReg.v.sv\n             obj_dir/memReg.v\n             obj_dir/memReg.v.v\n             obj_dir/memReg.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:33: Unsupported: Ignoring delay on this delayed statement.\n clk=0; #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:34: Unsupported: Ignoring delay on this delayed statement.\n clk=1; #10  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:37: Unsupported: Ignoring delay on this delayed statement.\n clk=0; #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:38: Unsupported: Ignoring delay on this delayed statement.\n clk=1; #10  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:42: Unsupported: Ignoring delay on this delayed statement.\n addressRW=9\'b1111111; #10\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:44: Unsupported: Ignoring delay on this delayed statement.\n addressRW=9\'b0000000; #10\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:51: Unsupported: Ignoring delay on this delayed statement.\n clk=0; #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:52: Unsupported: Ignoring delay on this delayed statement.\n clk=1; #10  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:55: Unsupported: Ignoring delay on this delayed statement.\n clk=0; #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:56: Unsupported: Ignoring delay on this delayed statement.\n clk=1; #10  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:60: Unsupported: Ignoring delay on this delayed statement.\n addressRW=9\'b1111111; #10\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:62: Unsupported: Ignoring delay on this delayed statement.\n addressRW=9\'b0000000; #10\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:73: Unsupported: Ignoring delay on this delayed statement.\n clk = 0; #10\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:74: Unsupported: Ignoring delay on this delayed statement.\n clk = 1; #10  \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/memReg.t.v:80: Unsupported: Ignoring delay on this delayed statement.\n addressRead = 9\'b1100000; #10\n                           ^\n%Error: Exiting due to 1 error(s), 15 warning(s)\n'
module testmemReg ();
	reg clk;
	reg[11:0] addressRW, addressRead, addressWrite;
	reg[31:0] dataInRW, dataInWrite;
	reg writeEnableRW, writeEnableWrite;
	wire[31:0] dataOutRW, dataOutRead;

	memoryReg memReg(.clk(clk), 
		.dataOutRW(dataOutRW), 
		.dataOutRead(dataOutRead), 
		.addressRW(addressRW), 
		.addressRead(addressRead), 
		.addressWrite(addressWrite), 
		.writeEnableRW(writeEnableRW), 
		.writeEnableWrite(writeEnableWrite), 
		.dataInRW(dataInRW), 
		.dataInWrite(dataInWrite));

	initial begin
	$display("Starting memReg tests.");


	writeEnableWrite = 0;
	addressRead = 9'b0000000;
	dataInWrite = 31'b0;

	writeEnableRW=1;
	addressRW=9'b1111111;
	dataInRW=32'b11110000;
	clk=0; #10
	clk=1; #10
	addressRW=9'b0000000;
	dataInRW=32'b00001111;
	clk=0; #10
	clk=1; #10


	writeEnableRW=0;
	addressRW=9'b1111111; #10
	if (dataOutRW !== 32'b11110000) $display("Read test 1a failed - %b", dataOutRW);
	addressRW=9'b0000000; #10
	if (dataOutRW !== 32'b00001111) $display("Read test 2a failed - %b", dataOutRW);


	writeEnableRW=0;
	addressRW=9'b1111111;
	dataInRW=32'b00001111;
	clk=0; #10
	clk=1; #10
	addressRW=9'b0000000;
	dataInRW=32'b11110000;
	clk=0; #10
	clk=1; #10


	writeEnableRW=0;
	addressRW=9'b1111111; #10
	if (dataOutRW !== 32'b11110000) $display("Read test 1b failed - %b", dataOutRW);
	addressRW=9'b0000000; #10
	if (dataOutRW !== 32'b00001111) $display("Read test 2b failed - %b", dataOutRW);



	writeEnableRW = 1;
	writeEnableWrite = 1;
	dataInRW = 32'b1;
	dataInWrite = 32'b10;
	addressRW = 9'b1100000;
	addressWrite = 9'b0011111;
	clk = 0; #10
	clk = 1; #10


	writeEnableRW = 0;
	writeEnableWrite = 0;
	addressRW = 9'b0011111;
	addressRead = 9'b1100000; #10
	if (dataOutRW !== 32'b10) $display("Read from two at once test 1 failed - %b", dataOutRW);
	if (dataOutRead !== 32'b1) $display("Read from two at once test 2 failed - %b", dataOutRead);

	$display("memReg Testing Finished");

	end

endmodule
module testmemReg ();

	reg clk;
	reg[11:0] addressRW, addressRead, addressWrite;
	reg[31:0] dataInRW, dataInWrite;
	reg writeEnableRW, writeEnableWrite;
	wire[31:0] dataOutRW, dataOutRead;

	memoryReg memReg(.clk(clk), 
		.dataOutRW(dataOutRW), 
		.dataOutRead(dataOutRead), 
		.addressRW(addressRW), 
		.addressRead(addressRead), 
		.addressWrite(addressWrite), 
		.writeEnableRW(writeEnableRW), 
		.writeEnableWrite(writeEnableWrite), 
		.dataInRW(dataInRW), 
		.dataInWrite(dataInWrite));

	initial begin
	$display("Starting memReg tests.");


	writeEnableWrite = 0;
	addressRead = 9'b0000000;
	dataInWrite = 31'b0;

	writeEnableRW=1;
	addressRW=9'b1111111;
	dataInRW=32'b11110000;
	clk=0; #10
	clk=1; #10
	addressRW=9'b0000000;
	dataInRW=32'b00001111;
	clk=0; #10
	clk=1; #10


	writeEnableRW=0;
	addressRW=9'b1111111; #10
	if (dataOutRW !== 32'b11110000) $display("Read test 1a failed - %b", dataOutRW);
	addressRW=9'b0000000; #10
	if (dataOutRW !== 32'b00001111) $display("Read test 2a failed - %b", dataOutRW);


	writeEnableRW=0;
	addressRW=9'b1111111;
	dataInRW=32'b00001111;
	clk=0; #10
	clk=1; #10
	addressRW=9'b0000000;
	dataInRW=32'b11110000;
	clk=0; #10
	clk=1; #10


	writeEnableRW=0;
	addressRW=9'b1111111; #10
	if (dataOutRW !== 32'b11110000) $display("Read test 1b failed - %b", dataOutRW);
	addressRW=9'b0000000; #10
	if (dataOutRW !== 32'b00001111) $display("Read test 2b failed - %b", dataOutRW);



	writeEnableRW = 1;
	writeEnableWrite = 1;
	dataInRW = 32'b1;
	dataInWrite = 32'b10;
	addressRW = 9'b1100000;
	addressWrite = 9'b0011111;
	clk = 0; #10
	clk = 1; #10


	writeEnableRW = 0;
	writeEnableWrite = 0;
	addressRW = 9'b0011111;
	addressRead = 9'b1100000; #10
	if (dataOutRW !== 32'b10) $display("Read from two at once test 1 failed - %b", dataOutRW);
	if (dataOutRead !== 32'b1) $display("Read from two at once test 2 failed - %b", dataOutRead);

	$display("memReg Testing Finished");

	end

endmodule