data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:8: Define or directive not defined: \'`STAT_BUS\'\n    input wire [`STAT_BUS] E_stat_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`STAT_BUS] E_stat_i,\n                         ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:9: Define or directive not defined: \'`ICODE_BUS\'\n    input wire [`ICODE_BUS] E_icode_i,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:10: Define or directive not defined: \'`DATA_BUS\'\n    input wire [`DATA_BUS] e_valE_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:11: Define or directive not defined: \'`DATA_BUS\'\n    input wire [`DATA_BUS] E_valA_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:12: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input wire [`REG_ADDR_BUS] e_dstE_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:13: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input wire [`REG_ADDR_BUS] E_dstM_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:16: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`STAT_BUS] M_stat_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:16: Define or directive not defined: \'`STAT_BUS\'\n    output reg [`STAT_BUS] M_stat_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:17: Define or directive not defined: \'`ICODE_BUS\'\n    output reg [`ICODE_BUS] M_icode_o,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:18: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] M_valE_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:19: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] M_valA_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:20: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output reg [`REG_ADDR_BUS] M_dstE_o,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:21: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output reg [`REG_ADDR_BUS] M_dstM_o\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:26: Define or directive not defined: \'`TRUE\'\n            M_Cnd_o  <= `TRUE;\n                        ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:27: Define or directive not defined: \'`SAOK\'\n            M_stat_o <= `SAOK;\n                        ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:28: Define or directive not defined: \'`ICODE_ZERO\'\n            M_icode_o <= `ICODE_ZERO;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:29: Define or directive not defined: \'`DATA_ZERO\'\n            M_valE_o <= `DATA_ZERO;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:30: Define or directive not defined: \'`DATA_ZERO\'\n            M_valA_o <= `DATA_ZERO;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:31: Define or directive not defined: \'`NREG\'\n            M_dstE_o <= `NREG;\n                        ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:32: Define or directive not defined: \'`NREG\'\n            M_dstM_o <= `NREG;\n                        ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:37: Define or directive not defined: \'`RST_EN\'\n            if(rst == `RST_EN)\n                      ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:39: Define or directive not defined: \'`TRUE\'\n                M_Cnd_o  <= `TRUE;\n                            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:40: Define or directive not defined: \'`SAOK\'\n                M_stat_o <= `SAOK;\n                            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:41: Define or directive not defined: \'`ICODE_ZERO\'\n                M_icode_o <= `ICODE_ZERO;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:42: Define or directive not defined: \'`DATA_ZERO\'\n                M_valE_o <= `DATA_ZERO;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:43: Define or directive not defined: \'`DATA_ZERO\'\n                M_valA_o <= `DATA_ZERO;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:44: Define or directive not defined: \'`NREG\'\n                M_dstE_o <= `NREG;\n                            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:45: Define or directive not defined: \'`NREG\'\n                M_dstM_o <= `NREG;\n                            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:47: Define or directive not defined: \'`TRUE\'\n            else if(M_bubble_i == `TRUE)\n                                  ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:50: Define or directive not defined: \'`SAOK\'\n                M_stat_o <= `SAOK;\n                            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:51: Define or directive not defined: \'`NOP\'\n                M_icode_o <= `NOP;\n                             ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:52: Define or directive not defined: \'`DATA_ZERO\'\n                M_valE_o <= `DATA_ZERO;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:53: Define or directive not defined: \'`DATA_ZERO\'\n                M_valA_o <= `DATA_ZERO;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:54: Define or directive not defined: \'`NREG\'\n                M_dstE_o <= `NREG;\n                            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem_reg.v:55: Define or directive not defined: \'`NREG\'\n                M_dstM_o <= `NREG;\n                            ^~~~~\n%Error: Exiting due to 37 error(s)\n'
module mem_reg(
    input wire clk,
    input wire rst,
    input wire e_Cnd_i,
    input wire M_bubble_i,
    input wire [`STAT_BUS] E_stat_i,
    input wire [`ICODE_BUS] E_icode_i,
    input wire [`DATA_BUS] e_valE_i,
    input wire [`DATA_BUS] E_valA_i,
    input wire [`REG_ADDR_BUS] e_dstE_i,
    input wire [`REG_ADDR_BUS] E_dstM_i,
    
    output reg M_Cnd_o,
    output reg [`STAT_BUS] M_stat_o,
    output reg [`ICODE_BUS] M_icode_o,
    output reg [`DATA_BUS] M_valE_o,
    output reg [`DATA_BUS] M_valA_o,
    output reg [`REG_ADDR_BUS] M_dstE_o,
    output reg [`REG_ADDR_BUS] M_dstM_o
    );

    initial
        begin
            M_Cnd_o  <= `TRUE;
            M_stat_o <= `SAOK;
            M_icode_o <= `ICODE_ZERO;
            M_valE_o <= `DATA_ZERO;
            M_valA_o <= `DATA_ZERO;
            M_dstE_o <= `NREG;
            M_dstM_o <= `NREG;
        end
    
    always @(posedge clk)
        begin
            if(rst == `RST_EN)
            begin
                M_Cnd_o  <= `TRUE;
                M_stat_o <= `SAOK;
                M_icode_o <= `ICODE_ZERO;
                M_valE_o <= `DATA_ZERO;
                M_valA_o <= `DATA_ZERO;
                M_dstE_o <= `NREG;
                M_dstM_o <= `NREG;
            end
            else if(M_bubble_i == `TRUE)
            begin
                M_Cnd_o  <= e_Cnd_i;
                M_stat_o <= `SAOK;
                M_icode_o <= `NOP;
                M_valE_o <= `DATA_ZERO;
                M_valA_o <= `DATA_ZERO;
                M_dstE_o <= `NREG;
                M_dstM_o <= `NREG;
            end
            else
            begin
                M_Cnd_o  <= e_Cnd_i;
                M_stat_o <= E_stat_i;
                M_icode_o <= E_icode_i;
                M_valE_o <= e_valE_i;
                M_valA_o <= E_valA_i;
                M_dstE_o <= e_dstE_i;
                M_dstM_o <= E_dstM_i;
            end
        end
endmodule
module mem_reg(
    input wire clk,
    input wire rst,
    input wire e_Cnd_i,
    input wire M_bubble_i,
    input wire [`STAT_BUS] E_stat_i,
    input wire [`ICODE_BUS] E_icode_i,
    input wire [`DATA_BUS] e_valE_i,
    input wire [`DATA_BUS] E_valA_i,
    input wire [`REG_ADDR_BUS] e_dstE_i,
    input wire [`REG_ADDR_BUS] E_dstM_i,
    
    output reg M_Cnd_o,
    output reg [`STAT_BUS] M_stat_o,
    output reg [`ICODE_BUS] M_icode_o,
    output reg [`DATA_BUS] M_valE_o,
    output reg [`DATA_BUS] M_valA_o,
    output reg [`REG_ADDR_BUS] M_dstE_o,
    output reg [`REG_ADDR_BUS] M_dstM_o
    );


    initial
        begin
            M_Cnd_o  <= `TRUE;
            M_stat_o <= `SAOK;
            M_icode_o <= `ICODE_ZERO;
            M_valE_o <= `DATA_ZERO;
            M_valA_o <= `DATA_ZERO;
            M_dstE_o <= `NREG;
            M_dstM_o <= `NREG;
        end
    
    always @(posedge clk)
        begin
            if(rst == `RST_EN)
            begin
                M_Cnd_o  <= `TRUE;
                M_stat_o <= `SAOK;
                M_icode_o <= `ICODE_ZERO;
                M_valE_o <= `DATA_ZERO;
                M_valA_o <= `DATA_ZERO;
                M_dstE_o <= `NREG;
                M_dstM_o <= `NREG;
            end
            else if(M_bubble_i == `TRUE)
            begin
                M_Cnd_o  <= e_Cnd_i;
                M_stat_o <= `SAOK;
                M_icode_o <= `NOP;
                M_valE_o <= `DATA_ZERO;
                M_valA_o <= `DATA_ZERO;
                M_dstE_o <= `NREG;
                M_dstM_o <= `NREG;
            end
            else
            begin
                M_Cnd_o  <= e_Cnd_i;
                M_stat_o <= E_stat_i;
                M_icode_o <= E_icode_i;
                M_valE_o <= e_valE_i;
                M_valA_o <= E_valA_i;
                M_dstE_o <= e_dstE_i;
                M_dstM_o <= E_dstM_i;
            end
        end
endmodule