data/full_repos/permissive/119913252/proj1.v
data/verilator_xmls/9f0450ee-4dfe-4ca6-8508-2db0a28ff3b6.xml
module proj1(x1,x2,x3,f);
	input x1,x2,x3;
	output f;
 
	wire m0, m3, m5, m6;

	assign m0 = ~x1 & ~x2 & ~x3; 
	assign m3 = ~x1 & x2 & x3;
	assign m5 = x1 & ~x2 & x3;
	assign m6 = x1 & x2 & ~x3;	
	 	
	assign f = m0 | m3 | m5 | m6;

endmodule
module proj1(x1,x2,x3,f);

	input x1,x2,x3;
	output f;
 
	wire m0, m3, m5, m6;

	assign m0 = ~x1 & ~x2 & ~x3; 
	assign m3 = ~x1 & x2 & x3;
	assign m5 = x1 & ~x2 & x3;
	assign m6 = x1 & x2 & ~x3;	
	 	
	assign f = m0 | m3 | m5 | m6;

endmodule