data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
data/verilator_xmls/a1ca12a6-8a1f-4c19-9a3c-b8bf8f194833.xml
module jtag_tap(
  output tck,
  output tdi,
  input tdo,
  output capture,
  output shift,
  output e1dr,
  output update,
  output reset
);

	assign tck = 1;
	assign tdi = 1;
	assign capture = 0;
	assign shift = 0;
	assign e1dr = 0;
	assign update = 0;
	assign reset = 0;

endmodule
module jtag_tap(
  output tck,
  output tdi,
  input tdo,
  output capture,
  output shift,
  output e1dr,
  output update,
  output reset
);


	assign tck = 1;
	assign tdi = 1;
	assign capture = 0;
	assign shift = 0;
	assign e1dr = 0;
	assign update = 0;
	assign reset = 0;

endmodule