data/full_repos/permissive/119758565/nandGate.v
data/verilator_xmls/8510fe19-5dc5-4fb0-be3a-566e1a351d8b.xml
module nandGate(
    input x,
    input y,
    output out
    );
	 
	 assign out = ~(x & y);

endmodule
module nandGate(
    input x,
    input y,
    output out
    );

	 
	 assign out = ~(x & y);

endmodule