data/full_repos/permissive/143278/ivltests/sv_uwire3.v
 line:5: before: "typedef"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_uwire3.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #1  ;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DUT(output sample_t out,
	   input logic [1:0] x, y);

   always @* begin
      out.a = x;
      out.b = y;
   end

endmodule
module DUT(output sample_t out,
	   input logic [1:0] x, y);


   always @* begin
      out.a = x;
      out.b = y;
   end

endmodule