data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v
'utf-8' codec can't decode byte 0xbe in position 220: invalid start byte
1: b'%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:72: Cannot find include file: rom8x1024_DE2.v\n `include "rom8x1024_DE2.v"  // ROM        DE2      , quartus,              \n          ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/rom8x1024_DE2.v\n             data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/rom8x1024_DE2.v.v\n             data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/rom8x1024_DE2.v.sv\n             rom8x1024_DE2.v\n             rom8x1024_DE2.v.v\n             rom8x1024_DE2.v.sv\n             obj_dir/rom8x1024_DE2.v\n             obj_dir/rom8x1024_DE2.v.v\n             obj_dir/rom8x1024_DE2.v.sv\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:73: Cannot find include file: ram8x2048_DE2.v\n `include "ram8x2048_DE2.v"  // RAM        DE2      , quartus,              \n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:75: Cannot find include file: alu.v\n`include "alu.v"           // ALU       \n         ^~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:76: Cannot find include file: pc.v\n`include "pc.v"            // PC       \n         ^~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:77: Cannot find include file: registers.v\n`include "registers.v"     //                        \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:78: Cannot find include file: plus4.v\n`include "plus4.v"         // PC                         \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:79: Cannot find include file: adder32.v\n`include "adder32.v"       // PC               \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:80: Cannot find include file: mux32_32_32.v\n`include "mux32_32_32.v"   // 32-bit, 32-bit    , \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:82: Cannot find include file: mux5_5_5.v\n`include "mux5_5_5.v"      // 5-bit, 5-bit    , \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:84: Cannot find include file: main_ctrl.v\n`include "main_ctrl.v"     //                      \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:85: Cannot find include file: alu_ctrler.v\n`include "alu_ctrler.v"    // ALU                \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:86: Cannot find include file: shifter32_32_l2.v\n`include "shifter32_32_l2.v"   // 32-bit    , 32-bit      2                         \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:87: Cannot find include file: signext16_32.v\n`include "signext16_32.v"      // 16-bit    , 32-bit                         \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/cpu.v:88: Cannot find include file: is_branch.v\n`include "is_branch.v"         //                    \n         ^~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module cpu (clk, reset,
            clk_ctrl0, clk_ctrl1, clk_ctrl_clk,
            o_clock, o_pc, o_alu_y, o_alu_a, o_alu_b, o_alu_ctrl, o_alu_comp,
            o_reg_data1, o_reg_idx1, o_reg_data2, o_reg_idx2, o_reg_wdata, o_reg_widx, o_reg_wen,
            o_ram_addr, o_ram_rdata, o_ram_wdata, o_ram_wen,
            i_ram_addr, i_ram_wdata, i_ram_wen
);


  input clk;
  input reset;

  input clk_ctrl0;
  input clk_ctrl1;
  input clk_ctrl_clk;

  input [12:0]  i_ram_addr;
  input [31:0] i_ram_wdata;
  input          i_ram_wen;


  output            o_clock;
  output [11:0]        o_pc;
  output [31:0]     o_alu_y;
  output [31:0]     o_alu_a;
  output [31:0]     o_alu_b;
  output [3:0]   o_alu_ctrl;
  output [1:0]   o_alu_comp;
  output [31:0] o_reg_data1;
  output [4:0]   o_reg_idx1;
  output [31:0] o_reg_data2;
  output [4:0]   o_reg_idx2;
  output [31:0] o_reg_wdata;
  output [4:0]   o_reg_widx;
  output          o_reg_wen;
  output [12:0]  o_ram_addr;
  output [31:0] o_ram_rdata;
  output [31:0] o_ram_wdata;
  output          o_ram_wen;





  wire [23:0] max_bunsyuu_reg_val;

  reg            clock_reg;
  reg  [23:0]  bunsyuu_reg;


  wire               clock;
  wire           clock_rom;
  wire           clock_ram;



  assign clock         = ((clk_ctrl1 == 1'b1) && (clk_ctrl0 == 1'b1)) ? clk_ctrl_clk : clock_reg;
  assign clock_rom     =   bunsyuu_reg[3];
  assign clock_ram     =   bunsyuu_reg[4];









  assign max_bunsyuu_reg_val = ((clk_ctrl1 == 1'b0) && (clk_ctrl0 == 1'b0)) ? `max_bunsyuu_reg_val_2Hz
                               : (((clk_ctrl1 == 1'b0) && (clk_ctrl0 == 1'b1)) ? `max_bunsyuu_reg_val_200Hz
                                 : (((clk_ctrl1 == 1'b1) && (clk_ctrl0 == 1'b0)) ? `max_bunsyuu_reg_val_1kHz
                                   : `max_bunsyuu_reg_val_2Hz));


  always @(posedge clk or negedge reset) begin
     if (reset == 1'b0) begin
	 bunsyuu_reg <= 24'b000000000000000000000000;
	 clock_reg   <=                         1'b0;
     end else begin
	 if (bunsyuu_reg >= max_bunsyuu_reg_val) begin
	     bunsyuu_reg <= 24'b000000000000000000000000;

             clock_reg   <= ~clock_reg;
	 end else begin
             bunsyuu_reg <= bunsyuu_reg + 1;
	 end
     end
  end





  wire  [11:0]       rom_addr;
  wire  [31:0]       rom_data;

  wire  [12:0]       ram_addr;
  wire       ram_write_enable;
  wire  [31:0] ram_write_data;
  wire  [31:0]  ram_read_data;
  wire  [12:0]  key_ram_addr;
  wire  [31:0] key_ram_wdata;
  wire          key_ram_wen;

  wire  [31:0]   alu_a, alu_b;
  wire   [3:0] 	     alu_ctrl;
  wire  [31:0]          alu_y;
  wire   [1:0]       alu_comp;

  wire   [31:0]       pc_next;
  wire   [31:0]            pc;

  wire   [4:0]  reg_read_idx1;
  wire   [4:0]  reg_read_idx2;
  wire   [4:0]  reg_write_idx;
  wire  [31:0] reg_write_data;
  wire  [31:0] reg_read_data1;
  wire  [31:0] reg_read_data2;

  wire   [31:0]         inc_a;
  wire   [31:0]         inc_y;

  wire   [31:0]         add_a;
  wire   [31:0]         add_b;
  wire   [31:0]         add_y;

  wire  [31:0]   alu_b_sel1_d0;
  wire  [31:0]   alu_b_sel1_d1;
  wire            alu_b_sel1_s;
  wire  [31:0]    alu_b_sel1_y;

  wire  [31:0]   alu_b_sel2_d0;
  wire  [31:0]   alu_b_sel2_d1;
  wire            alu_b_sel2_s;
  wire  [31:0]    alu_b_sel2_y;

  wire  [31:0]   alu_ram_sel_d0;
  wire  [31:0]   alu_ram_sel_d1;
  wire            alu_ram_sel_s;
  wire  [31:0]    alu_ram_sel_y;

  wire  [31:0]      link_sel_d0;
  wire  [31:0]      link_sel_d1;
  wire               link_sel_s;
  wire  [31:0]       link_sel_y;

  wire  [4:0]   reg_widx_sel1_d0;
  wire  [4:0]   reg_widx_sel1_d1;
  wire           reg_widx_sel1_s;
  wire  [4:0]    reg_widx_sel1_y;

  wire  [4:0]     reg_widx_sel2_d0;
  wire  [4:0]     reg_widx_sel2_d1;
  wire             reg_widx_sel2_s;
  wire  [4:0]      reg_widx_sel2_y;

  wire  [31:0]       pc_sel_d0;
  wire  [31:0]       pc_sel_d1;
  wire                pc_sel_s;
  wire  [31:0]        pc_sel_y;




  wire  [31:0]     jp_sel_d0;
  wire  [31:0]     jp_sel_d1;
  wire              jp_sel_s;
  wire  [31:0]      jp_sel_y;




  wire  [31:0]     jpr_sel_d0;
  wire  [31:0]     jpr_sel_d1;
  wire             jpr_sel_s;
  wire  [31:0]     jpr_sel_y;


  wire   [31:0]    instruction;
  wire              alu_b_sel1;
  wire              alu_b_sel2;
  wire   [2:0]          alu_op;
  wire   [2:0]  is_branch_ctrl;
  wire        reg_write_enable;
  wire                      jp;
  wire                    link;
  wire                     jpr;
  wire                  shiftv;
  wire             do_sign_ext;

  wire   [5:0]            func;

  wire   [31:0]           sh_a;
  wire   [31:0]           sh_y;

  wire   [31:0]         sh_j_a;
  wire   [31:0]         sh_j_y;

  wire   [15:0]            a16;
  wire   [31:0]            y32;

  wire    [2:0]   is_branch_d0;
  wire    [1:0]   is_branch_d1;
  wire             is_branch_y;

  wire  [31:0]   alu_a_sel1_d0;
  wire  [31:0]   alu_a_sel1_d1;
  wire            alu_a_sel1_s;
  wire  [31:0]    alu_a_sel1_y;

















  rom8x1024_DE2  rom8x1024a(clock_rom, rom_addr, rom_data);



















  ram8x2048_DE2  ram8x2048a(clock_ram, ram_addr, ram_write_enable,
                            ram_write_data, ram_read_data,
                            key_ram_addr, key_ram_wdata, key_ram_wen);









  alu  alua(alu_a, alu_b, alu_ctrl, alu_y, alu_comp);







  pc  pca (clock, reset, pc_next, pc); 











  registers register_file(clock, reset,
		  reg_read_idx1, reg_read_idx2,
		  reg_write_idx, reg_write_enable, reg_write_data,
		  reg_read_data1, reg_read_data2);





  plus4 pc_plus4 (inc_a, inc_y);   







  adder32 pc_add(add_a, add_b, add_y);







  mux32_32_32  alu_b_sel_1(alu_b_sel1_d0, alu_b_sel1_d1, alu_b_sel1_s, alu_b_sel1_y);
  mux32_32_32  alu_b_sel_2(alu_b_sel2_d0, alu_b_sel2_d1, alu_b_sel2_s, alu_b_sel2_y);
  mux32_32_32  alu_ram_sel(alu_ram_sel_d0, alu_ram_sel_d1, alu_ram_sel_s, alu_ram_sel_y);
  mux32_32_32  link_sel(link_sel_d0, link_sel_d1, link_sel_s, link_sel_y);
  mux32_32_32  alu_a_sel_1(alu_a_sel1_d0, alu_a_sel1_d1, alu_a_sel1_s, alu_a_sel1_y);




  mux32_32_32  jpr_sel(jpr_sel_d0, jpr_sel_d1, jpr_sel_s, jpr_sel_y);



  mux32_32_32  jp_sel(jp_sel_d0, jp_sel_d1, jp_sel_s, jp_sel_y);

  mux32_32_32  pc_sel(pc_sel_d0, pc_sel_d1, pc_sel_s, pc_sel_y);







  mux5_5_5  reg_widx_sel1(reg_widx_sel1_d0, reg_widx_sel1_d1,
                            reg_widx_sel1_s, reg_widx_sel1_y);
  mux5_5_5  reg_widx_sel2(reg_widx_sel2_d0, reg_widx_sel2_d1,
                        reg_widx_sel2_s, reg_widx_sel2_y);

















  main_ctrl main_ctrla(instruction, ram_write_enable, alu_b_sel1, alu_b_sel2, alu_op,
                       is_branch_ctrl, reg_write_enable, 
                       alu_ram_sel_s, reg_widx_sel1_s, jp, link, jpr,
                       shiftv, do_sign_ext);






  alu_ctrler alu_ctrlera(alu_op, func, alu_ctrl);





  shifter32_32_l2 shifter32_32_l2a(sh_a, sh_y);
  shifter32_32_l2 shifter32_32_l2b(sh_j_a, sh_j_y);






  signext16_32 signext16_32a(do_sign_ext, a16, y32);






  is_branch is_brancha(is_branch_d0, is_branch_d1, is_branch_y);

  assign rom_addr = (pc[31:0] > 32'h00400fff) ? 12'hfff : pc[11:0];

  assign ram_addr = alu_y[12:0];
  assign ram_write_data = reg_read_data2;
  assign key_ram_addr   = i_ram_addr;
  assign key_ram_wdata  = i_ram_wdata;
  assign key_ram_wen    = i_ram_wen;
  assign alu_a = alu_a_sel1_y;
  assign alu_b = alu_b_sel2_y;




  assign pc_next = jpr_sel_y;






  assign reg_read_idx1 = instruction[25:21];
  assign reg_read_idx2 = instruction[20:16];
  assign reg_write_idx = reg_widx_sel2_y;
  assign reg_write_data = link_sel_y;
  assign inc_a = pc;
  assign add_a = inc_y;
  assign add_b = sh_y;
  assign alu_b_sel1_d0 = reg_read_data2;
  assign alu_b_sel1_d1 = y32;
  assign alu_b_sel1_s = alu_b_sel1;
  assign alu_b_sel2_d0 = alu_b_sel1_y;
  assign alu_b_sel2_d1 = 0;
  assign alu_b_sel2_s = alu_b_sel2;
  assign alu_ram_sel_d0 = alu_y;
  assign alu_ram_sel_d1 = ram_read_data;
  assign reg_widx_sel1_d0 = instruction[20:16];
  assign reg_widx_sel1_d1 = instruction[15:11];
  assign reg_widx_sel2_d0 = reg_widx_sel1_y;
  assign reg_widx_sel2_d1 = 5'b11111;
  assign reg_widx_sel2_s = link;
  assign link_sel_d0 = alu_ram_sel_y;
  assign link_sel_d1 = inc_y;
  assign link_sel_s = link;
  assign pc_sel_d0 = inc_y;
  assign pc_sel_d1 = add_y;
  assign pc_sel_s = is_branch_y;




  assign jp_sel_d0 = pc_sel_y;
  assign jp_sel_d1 = sh_j_y;
  assign jp_sel_s = jp;





  assign jpr_sel_d0 = jp_sel_y;
  assign jpr_sel_d1 = alu_ram_sel_y;
  assign jpr_sel_s = jpr;

  assign instruction = rom_data;
  assign func = y32[5:0];
  assign sh_a = y32;
  assign sh_j_a = {6'b000000, instruction[25:0]};
  assign a16 = instruction[15:0];
  assign is_branch_d0 = is_branch_ctrl;
  assign is_branch_d1 = alu_comp;

  assign alu_a_sel1_d0 = reg_read_data1;
  assign alu_a_sel1_d1 = {27'b000000000000000000000000000, y32[10:6]};
  assign alu_a_sel1_s = shiftv;

  assign o_pc        = pc[11:0];
  assign o_clock     = clock;
  assign o_alu_y     = alu_y;
  assign o_alu_a     = alu_a;
  assign o_alu_b     = alu_b;
  assign o_alu_ctrl  = alu_ctrl;
  assign o_alu_comp  = alu_comp;
  assign o_reg_data1 = reg_read_data1;
  assign o_reg_idx1  = reg_read_idx1;
  assign o_reg_data2 = reg_read_data2;
  assign o_reg_idx2  = reg_read_idx2;
  assign o_reg_wdata = reg_write_data;
  assign o_reg_widx  = reg_write_idx;
  assign o_reg_wen   = reg_write_enable;
  assign o_ram_addr  = ram_addr;
  assign o_ram_rdata = ram_read_data;
  assign o_ram_wdata = ram_write_data;
  assign o_ram_wen   = ram_write_enable;
   
endmodule
module cpu (clk, reset,
            clk_ctrl0, clk_ctrl1, clk_ctrl_clk,
            o_clock, o_pc, o_alu_y, o_alu_a, o_alu_b, o_alu_ctrl, o_alu_comp,
            o_reg_data1, o_reg_idx1, o_reg_data2, o_reg_idx2, o_reg_wdata, o_reg_widx, o_reg_wen,
            o_ram_addr, o_ram_rdata, o_ram_wdata, o_ram_wen,
            i_ram_addr, i_ram_wdata, i_ram_wen
);



  input clk;
  input reset;

  input clk_ctrl0;
  input clk_ctrl1;
  input clk_ctrl_clk;

  input [12:0]  i_ram_addr;
  input [31:0] i_ram_wdata;
  input          i_ram_wen;


  output            o_clock;
  output [11:0]        o_pc;
  output [31:0]     o_alu_y;
  output [31:0]     o_alu_a;
  output [31:0]     o_alu_b;
  output [3:0]   o_alu_ctrl;
  output [1:0]   o_alu_comp;
  output [31:0] o_reg_data1;
  output [4:0]   o_reg_idx1;
  output [31:0] o_reg_data2;
  output [4:0]   o_reg_idx2;
  output [31:0] o_reg_wdata;
  output [4:0]   o_reg_widx;
  output          o_reg_wen;
  output [12:0]  o_ram_addr;
  output [31:0] o_ram_rdata;
  output [31:0] o_ram_wdata;
  output          o_ram_wen;





  wire [23:0] max_bunsyuu_reg_val;

  reg            clock_reg;
  reg  [23:0]  bunsyuu_reg;


  wire               clock;
  wire           clock_rom;
  wire           clock_ram;



  assign clock         = ((clk_ctrl1 == 1'b1) && (clk_ctrl0 == 1'b1)) ? clk_ctrl_clk : clock_reg;
  assign clock_rom     =   bunsyuu_reg[3];
  assign clock_ram     =   bunsyuu_reg[4];









  assign max_bunsyuu_reg_val = ((clk_ctrl1 == 1'b0) && (clk_ctrl0 == 1'b0)) ? `max_bunsyuu_reg_val_2Hz
                               : (((clk_ctrl1 == 1'b0) && (clk_ctrl0 == 1'b1)) ? `max_bunsyuu_reg_val_200Hz
                                 : (((clk_ctrl1 == 1'b1) && (clk_ctrl0 == 1'b0)) ? `max_bunsyuu_reg_val_1kHz
                                   : `max_bunsyuu_reg_val_2Hz));


  always @(posedge clk or negedge reset) begin
     if (reset == 1'b0) begin
	 bunsyuu_reg <= 24'b000000000000000000000000;
	 clock_reg   <=                         1'b0;
     end else begin
	 if (bunsyuu_reg >= max_bunsyuu_reg_val) begin
	     bunsyuu_reg <= 24'b000000000000000000000000;

             clock_reg   <= ~clock_reg;
	 end else begin
             bunsyuu_reg <= bunsyuu_reg + 1;
	 end
     end
  end





  wire  [11:0]       rom_addr;
  wire  [31:0]       rom_data;

  wire  [12:0]       ram_addr;
  wire       ram_write_enable;
  wire  [31:0] ram_write_data;
  wire  [31:0]  ram_read_data;
  wire  [12:0]  key_ram_addr;
  wire  [31:0] key_ram_wdata;
  wire          key_ram_wen;

  wire  [31:0]   alu_a, alu_b;
  wire   [3:0] 	     alu_ctrl;
  wire  [31:0]          alu_y;
  wire   [1:0]       alu_comp;

  wire   [31:0]       pc_next;
  wire   [31:0]            pc;

  wire   [4:0]  reg_read_idx1;
  wire   [4:0]  reg_read_idx2;
  wire   [4:0]  reg_write_idx;
  wire  [31:0] reg_write_data;
  wire  [31:0] reg_read_data1;
  wire  [31:0] reg_read_data2;

  wire   [31:0]         inc_a;
  wire   [31:0]         inc_y;

  wire   [31:0]         add_a;
  wire   [31:0]         add_b;
  wire   [31:0]         add_y;

  wire  [31:0]   alu_b_sel1_d0;
  wire  [31:0]   alu_b_sel1_d1;
  wire            alu_b_sel1_s;
  wire  [31:0]    alu_b_sel1_y;

  wire  [31:0]   alu_b_sel2_d0;
  wire  [31:0]   alu_b_sel2_d1;
  wire            alu_b_sel2_s;
  wire  [31:0]    alu_b_sel2_y;

  wire  [31:0]   alu_ram_sel_d0;
  wire  [31:0]   alu_ram_sel_d1;
  wire            alu_ram_sel_s;
  wire  [31:0]    alu_ram_sel_y;

  wire  [31:0]      link_sel_d0;
  wire  [31:0]      link_sel_d1;
  wire               link_sel_s;
  wire  [31:0]       link_sel_y;

  wire  [4:0]   reg_widx_sel1_d0;
  wire  [4:0]   reg_widx_sel1_d1;
  wire           reg_widx_sel1_s;
  wire  [4:0]    reg_widx_sel1_y;

  wire  [4:0]     reg_widx_sel2_d0;
  wire  [4:0]     reg_widx_sel2_d1;
  wire             reg_widx_sel2_s;
  wire  [4:0]      reg_widx_sel2_y;

  wire  [31:0]       pc_sel_d0;
  wire  [31:0]       pc_sel_d1;
  wire                pc_sel_s;
  wire  [31:0]        pc_sel_y;




  wire  [31:0]     jp_sel_d0;
  wire  [31:0]     jp_sel_d1;
  wire              jp_sel_s;
  wire  [31:0]      jp_sel_y;




  wire  [31:0]     jpr_sel_d0;
  wire  [31:0]     jpr_sel_d1;
  wire             jpr_sel_s;
  wire  [31:0]     jpr_sel_y;


  wire   [31:0]    instruction;
  wire              alu_b_sel1;
  wire              alu_b_sel2;
  wire   [2:0]          alu_op;
  wire   [2:0]  is_branch_ctrl;
  wire        reg_write_enable;
  wire                      jp;
  wire                    link;
  wire                     jpr;
  wire                  shiftv;
  wire             do_sign_ext;

  wire   [5:0]            func;

  wire   [31:0]           sh_a;
  wire   [31:0]           sh_y;

  wire   [31:0]         sh_j_a;
  wire   [31:0]         sh_j_y;

  wire   [15:0]            a16;
  wire   [31:0]            y32;

  wire    [2:0]   is_branch_d0;
  wire    [1:0]   is_branch_d1;
  wire             is_branch_y;

  wire  [31:0]   alu_a_sel1_d0;
  wire  [31:0]   alu_a_sel1_d1;
  wire            alu_a_sel1_s;
  wire  [31:0]    alu_a_sel1_y;

















  rom8x1024_DE2  rom8x1024a(clock_rom, rom_addr, rom_data);



















  ram8x2048_DE2  ram8x2048a(clock_ram, ram_addr, ram_write_enable,
                            ram_write_data, ram_read_data,
                            key_ram_addr, key_ram_wdata, key_ram_wen);









  alu  alua(alu_a, alu_b, alu_ctrl, alu_y, alu_comp);







  pc  pca (clock, reset, pc_next, pc); 











  registers register_file(clock, reset,
		  reg_read_idx1, reg_read_idx2,
		  reg_write_idx, reg_write_enable, reg_write_data,
		  reg_read_data1, reg_read_data2);





  plus4 pc_plus4 (inc_a, inc_y);   







  adder32 pc_add(add_a, add_b, add_y);







  mux32_32_32  alu_b_sel_1(alu_b_sel1_d0, alu_b_sel1_d1, alu_b_sel1_s, alu_b_sel1_y);
  mux32_32_32  alu_b_sel_2(alu_b_sel2_d0, alu_b_sel2_d1, alu_b_sel2_s, alu_b_sel2_y);
  mux32_32_32  alu_ram_sel(alu_ram_sel_d0, alu_ram_sel_d1, alu_ram_sel_s, alu_ram_sel_y);
  mux32_32_32  link_sel(link_sel_d0, link_sel_d1, link_sel_s, link_sel_y);
  mux32_32_32  alu_a_sel_1(alu_a_sel1_d0, alu_a_sel1_d1, alu_a_sel1_s, alu_a_sel1_y);




  mux32_32_32  jpr_sel(jpr_sel_d0, jpr_sel_d1, jpr_sel_s, jpr_sel_y);



  mux32_32_32  jp_sel(jp_sel_d0, jp_sel_d1, jp_sel_s, jp_sel_y);

  mux32_32_32  pc_sel(pc_sel_d0, pc_sel_d1, pc_sel_s, pc_sel_y);







  mux5_5_5  reg_widx_sel1(reg_widx_sel1_d0, reg_widx_sel1_d1,
                            reg_widx_sel1_s, reg_widx_sel1_y);
  mux5_5_5  reg_widx_sel2(reg_widx_sel2_d0, reg_widx_sel2_d1,
                        reg_widx_sel2_s, reg_widx_sel2_y);

















  main_ctrl main_ctrla(instruction, ram_write_enable, alu_b_sel1, alu_b_sel2, alu_op,
                       is_branch_ctrl, reg_write_enable, 
                       alu_ram_sel_s, reg_widx_sel1_s, jp, link, jpr,
                       shiftv, do_sign_ext);






  alu_ctrler alu_ctrlera(alu_op, func, alu_ctrl);





  shifter32_32_l2 shifter32_32_l2a(sh_a, sh_y);
  shifter32_32_l2 shifter32_32_l2b(sh_j_a, sh_j_y);






  signext16_32 signext16_32a(do_sign_ext, a16, y32);






  is_branch is_brancha(is_branch_d0, is_branch_d1, is_branch_y);

  assign rom_addr = (pc[31:0] > 32'h00400fff) ? 12'hfff : pc[11:0];

  assign ram_addr = alu_y[12:0];
  assign ram_write_data = reg_read_data2;
  assign key_ram_addr   = i_ram_addr;
  assign key_ram_wdata  = i_ram_wdata;
  assign key_ram_wen    = i_ram_wen;
  assign alu_a = alu_a_sel1_y;
  assign alu_b = alu_b_sel2_y;




  assign pc_next = jpr_sel_y;






  assign reg_read_idx1 = instruction[25:21];
  assign reg_read_idx2 = instruction[20:16];
  assign reg_write_idx = reg_widx_sel2_y;
  assign reg_write_data = link_sel_y;
  assign inc_a = pc;
  assign add_a = inc_y;
  assign add_b = sh_y;
  assign alu_b_sel1_d0 = reg_read_data2;
  assign alu_b_sel1_d1 = y32;
  assign alu_b_sel1_s = alu_b_sel1;
  assign alu_b_sel2_d0 = alu_b_sel1_y;
  assign alu_b_sel2_d1 = 0;
  assign alu_b_sel2_s = alu_b_sel2;
  assign alu_ram_sel_d0 = alu_y;
  assign alu_ram_sel_d1 = ram_read_data;
  assign reg_widx_sel1_d0 = instruction[20:16];
  assign reg_widx_sel1_d1 = instruction[15:11];
  assign reg_widx_sel2_d0 = reg_widx_sel1_y;
  assign reg_widx_sel2_d1 = 5'b11111;
  assign reg_widx_sel2_s = link;
  assign link_sel_d0 = alu_ram_sel_y;
  assign link_sel_d1 = inc_y;
  assign link_sel_s = link;
  assign pc_sel_d0 = inc_y;
  assign pc_sel_d1 = add_y;
  assign pc_sel_s = is_branch_y;




  assign jp_sel_d0 = pc_sel_y;
  assign jp_sel_d1 = sh_j_y;
  assign jp_sel_s = jp;





  assign jpr_sel_d0 = jp_sel_y;
  assign jpr_sel_d1 = alu_ram_sel_y;
  assign jpr_sel_s = jpr;

  assign instruction = rom_data;
  assign func = y32[5:0];
  assign sh_a = y32;
  assign sh_j_a = {6'b000000, instruction[25:0]};
  assign a16 = instruction[15:0];
  assign is_branch_d0 = is_branch_ctrl;
  assign is_branch_d1 = alu_comp;

  assign alu_a_sel1_d0 = reg_read_data1;
  assign alu_a_sel1_d1 = {27'b000000000000000000000000000, y32[10:6]};
  assign alu_a_sel1_s = shiftv;

  assign o_pc        = pc[11:0];
  assign o_clock     = clock;
  assign o_alu_y     = alu_y;
  assign o_alu_a     = alu_a;
  assign o_alu_b     = alu_b;
  assign o_alu_ctrl  = alu_ctrl;
  assign o_alu_comp  = alu_comp;
  assign o_reg_data1 = reg_read_data1;
  assign o_reg_idx1  = reg_read_idx1;
  assign o_reg_data2 = reg_read_data2;
  assign o_reg_idx2  = reg_read_idx2;
  assign o_reg_wdata = reg_write_data;
  assign o_reg_widx  = reg_write_idx;
  assign o_reg_wen   = reg_write_enable;
  assign o_ram_addr  = ram_addr;
  assign o_ram_rdata = ram_read_data;
  assign o_ram_wdata = ram_write_data;
  assign o_ram_wen   = ram_write_enable;
   
endmodule