data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:25: Cannot find include file: jpdt.v\n`include "jpdt.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor/spare/build2,data/full_repos/permissive/21051978/jpdt.v\n             data/full_repos/permissive/21051978/processor/spare/build2,data/full_repos/permissive/21051978/jpdt.v.v\n             data/full_repos/permissive/21051978/processor/spare/build2,data/full_repos/permissive/21051978/jpdt.v.sv\n             jpdt.v\n             jpdt.v.v\n             jpdt.v.sv\n             obj_dir/jpdt.v\n             obj_dir/jpdt.v.v\n             obj_dir/jpdt.v.sv\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:26: Cannot find include file: control.h\n`include "control.h" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:137: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:137: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:138: Define or directive not defined: \'`aluwmuleu\'\n  a_op=`aluwmuleu;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:138: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmuleu;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:141: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:146: Define or directive not defined: \'`w16\'\n  c_ww=`w16;\n       ^~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:146: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w16;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:147: Define or directive not defined: \'`aluwmuleu\'\n  a_op=`aluwmuleu;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:147: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmuleu;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:161: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:161: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:162: Define or directive not defined: \'`aluwmulou\'\n  a_op=`aluwmulou;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:162: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmulou;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:170: Define or directive not defined: \'`w16\'\n  c_ww=`w16;\n       ^~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:170: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w16;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:171: Define or directive not defined: \'`aluwmulou\'\n  a_op=`aluwmulou;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:171: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmulou;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:188: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:188: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:189: Define or directive not defined: \'`aluwmulos\'\n  a_op=`aluwmulos;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:189: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmulos;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:193: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:199: Define or directive not defined: \'`w16\'\n  c_ww=`w16;\n       ^~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:199: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w16;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:200: Define or directive not defined: \'`aluwmulos\'\n  a_op=`aluwmulos;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:200: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmulos;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:212: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:221: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:221: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:222: Define or directive not defined: \'`aluwmules\'\n  a_op=`aluwmules;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:222: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmules;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:226: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:235: Define or directive not defined: \'`w16\'\n  c_ww=`w16;\n       ^~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:235: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w16;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:236: Define or directive not defined: \'`aluwmules\'\n  a_op=`aluwmules;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:236: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmules;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/spare/build2/jpdttb.v:240: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Error: Exiting due to 34 error(s), 8 warning(s)\n'
module tb_alu();


	


wire [0:127] res;
	
	
	
	
	
	
	

	


reg [0:127] r_A;

reg [0:127] r_B;

	reg [0:1] c_ww;

	reg [0:4] a_op;

reg [0:127] e_r;
	
	
	
	
	
	

	


	
	

	
	

	

	alu a_l_u (



		r_A,r_B,c_ww,a_op,res);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");	
		
		


		r_A=128'h0402030405060708f00a0b0cff0eff00;
		r_B=128'h03010202030303031004f505ff09fe10;
		e_r=128'h000c0006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		#10

		r_A=128'h000100020000ffff000f10bff103ffff;
		r_B=128'h000200040006ffff000c100000120014;
		e_r=128'h0000000200000000000000b40010f236;
		c_ww=`w16;
		a_op=`aluwmuleu;
		
		
		
		

		
		
		
		#10

		r_A=128'h0102030405060708090aff0c0dff0fff;
		r_B=128'h01010202030303031004040508000fff;
		e_r=128'h00020008001200180028003c0000fe01;
		c_ww=`w8;
		a_op=`aluwmulou;
		
		
		#10

		r_A=128'h0001000200000008000f10bff103ffff;
		r_B=128'h0002000400060008000c001000120014;
		e_r=128'h000000080000004000010bf00013ffec;
		c_ww=`w16;
		a_op=`aluwmulou;
		
		
		

		
		
		
		#10


		r_A=128'h0180010501f9015301040100013c0100;
		r_B=128'h017f010901fa010001fd01f101b80100;
		e_r=128'hc080002d002a0000fff40000ef200000;
		c_ww=`w8;
		a_op=`aluwmulos;
		
		
		
		#10


		r_A=128'h1111000211118000111120541111fff9;
		r_B=128'hffff0004ffff7fffffff0000fffffffd;
		e_r=128'h00000008c00080000000000000000015;
		c_ww=`w16;
		a_op=`aluwmulos;
	
		
		
		
		
		
		

		
		
		
		#10


		r_A=128'h80010501f9015301040100013c010001;
		r_B=128'h7f010901fa010001fd01f101b8010001;
		e_r=128'hc080002d002a0000fff40000ef200000;
		c_ww=`w8;
		a_op=`aluwmules;
		
		
		
		#10


		r_A=128'h000211118000111120541111fff91111;
		r_B=128'h0004ffff7fffffff0000fffffffdffff;
		e_r=128'h00000008c00080000000000000000015;
		c_ww=`w16;
		a_op=`aluwmules;
	
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_alu();



	


wire [0:127] res;
	
	
	
	
	
	
	

	


reg [0:127] r_A;

reg [0:127] r_B;

	reg [0:1] c_ww;

	reg [0:4] a_op;

reg [0:127] e_r;
	
	
	
	
	
	

	


	
	

	
	

	

	alu a_l_u (



		r_A,r_B,c_ww,a_op,res);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");	
		
		


		r_A=128'h0402030405060708f00a0b0cff0eff00;
		r_B=128'h03010202030303031004f505ff09fe10;
		e_r=128'h000c0006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		#10

		r_A=128'h000100020000ffff000f10bff103ffff;
		r_B=128'h000200040006ffff000c100000120014;
		e_r=128'h0000000200000000000000b40010f236;
		c_ww=`w16;
		a_op=`aluwmuleu;
		
		
		
		

		
		
		
		#10

		r_A=128'h0102030405060708090aff0c0dff0fff;
		r_B=128'h01010202030303031004040508000fff;
		e_r=128'h00020008001200180028003c0000fe01;
		c_ww=`w8;
		a_op=`aluwmulou;
		
		
		#10

		r_A=128'h0001000200000008000f10bff103ffff;
		r_B=128'h0002000400060008000c001000120014;
		e_r=128'h000000080000004000010bf00013ffec;
		c_ww=`w16;
		a_op=`aluwmulou;
		
		
		

		
		
		
		#10


		r_A=128'h0180010501f9015301040100013c0100;
		r_B=128'h017f010901fa010001fd01f101b80100;
		e_r=128'hc080002d002a0000fff40000ef200000;
		c_ww=`w8;
		a_op=`aluwmulos;
		
		
		
		#10


		r_A=128'h1111000211118000111120541111fff9;
		r_B=128'hffff0004ffff7fffffff0000fffffffd;
		e_r=128'h00000008c00080000000000000000015;
		c_ww=`w16;
		a_op=`aluwmulos;
	
		
		
		
		
		
		

		
		
		
		#10


		r_A=128'h80010501f9015301040100013c010001;
		r_B=128'h7f010901fa010001fd01f101b8010001;
		e_r=128'hc080002d002a0000fff40000ef200000;
		c_ww=`w8;
		a_op=`aluwmules;
		
		
		
		#10


		r_A=128'h000211118000111120541111fff91111;
		r_B=128'h0004ffff7fffffff0000fffffffdffff;
		e_r=128'h00000008c00080000000000000000015;
		c_ww=`w16;
		a_op=`aluwmules;
	
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule