data/full_repos/permissive/113036182/DataMemory.v
 line:4 column:14: Illegal character "'"
1: b"%Error: data/full_repos/permissive/113036182/DataMemory.v:71: Cannot find file containing module: 'CSA_32bit'\nCSA_32bit f1 (Address1,32'b00000000000000000000000000000001,1'b0,address11,co,ov),\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit\n             data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit.v\n             data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/CSA_32bit.sv\n             CSA_32bit\n             CSA_32bit.v\n             CSA_32bit.sv\n             obj_dir/CSA_32bit\n             obj_dir/CSA_32bit.v\n             obj_dir/CSA_32bit.sv\n%Error: data/full_repos/permissive/113036182/DataMemory.v:102: Cannot find file containing module: 'mux_2x32'\nmux_2x32 m1 (WriteData2,rData1,select,WrData2),\n^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Project_test1 (input [31:0]Address1,Address2,WriteData1,WriteData2,input select,MemRead,MemWrite,inout [31:0]Data1,Data2);
reg [31:0] rData1,rData2;
wire [31:0] WrData1,WrData2;
mux_2x32 m1 (WriteData2,rData1,select,WrData2),
         m2 (WriteData1,rData2,select,WrData1);  
DataMem DM1 (Address1,Address2,WrData1,WrData2,MemRead,MemWrite,Data1,Data2);
always@( Address1,Address2 ) begin
rData1 <= Data1;
rData2 <= Data2;
end
endmodule
module Project_test1 (input [31:0]Address1,Address2,WriteData1,WriteData2,input select,MemRead,MemWrite,inout [31:0]Data1,Data2);

reg [31:0] rData1,rData2;
wire [31:0] WrData1,WrData2;
mux_2x32 m1 (WriteData2,rData1,select,WrData2),
         m2 (WriteData1,rData2,select,WrData1);  
DataMem DM1 (Address1,Address2,WrData1,WrData2,MemRead,MemWrite,Data1,Data2);
always@( Address1,Address2 ) begin
rData1 <= Data1;
rData2 <= Data2;
end
endmodule