data/full_repos/permissive/143278/ivltests/unary_xnor2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/unary_xnor2.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/unary_xnor2.v:43: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/unary_xnor2.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/unary_xnor2.v:53: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/unary_xnor2.v:56: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-UNSIGNED: data/full_repos/permissive/143278/ivltests/unary_xnor2.v:34: Comparison is constant due to unsigned arithmetic\n                                                                              : ... In instance main\n   for(vect=4\'b0001;vect<4\'b0000;vect = vect << 1)\n                        ^\n%Warning-UNSIGNED: data/full_repos/permissive/143278/ivltests/unary_xnor2.v:44: Comparison is constant due to unsigned arithmetic\n                                                                              : ... In instance main\n   for(vect=4\'b0011;vect<4\'b0000;vect = vect << 1)\n                        ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

reg [3:0] vect;
reg	error;
wire	result;

assign result = ^~(vect);

initial
 begin
   error = 0;
   for(vect=4'b0001;vect<4'b0000;vect = vect << 1)
    begin
      #1;
      if(result !== 1'b0)
        begin
           $display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
           error = 1'b1;
        end
    end
   #1;
   for(vect=4'b0011;vect<4'b0000;vect = vect << 1)
    begin
      #1;
      if(result !== 1'b0)
        begin
           $display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
           error = 1'b1;
        end
    end
   #1;

   vect = 4'b0000;
   #1;
   if(result !== 1'b1)
     begin
       $display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
       error = 1'b1;
     end
   if(error === 0 )
     $display("PASSED");
 end

endmodule
module main;


reg [3:0] vect;
reg	error;
wire	result;

assign result = ^~(vect);

initial
 begin
   error = 0;
   for(vect=4'b0001;vect<4'b0000;vect = vect << 1)
    begin
      #1;
      if(result !== 1'b0)
        begin
           $display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
           error = 1'b1;
        end
    end
   #1;
   for(vect=4'b0011;vect<4'b0000;vect = vect << 1)
    begin
      #1;
      if(result !== 1'b0)
        begin
           $display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
           error = 1'b1;
        end
    end
   #1;

   vect = 4'b0000;
   #1;
   if(result !== 1'b1)
     begin
       $display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
       error = 1'b1;
     end
   if(error === 0 )
     $display("PASSED");
 end

endmodule