data/full_repos/permissive/180217218/fpga/src/uart.v
 line:25: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/180217218/fpga/src/uart.v:68: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'rxDiv\' generates 3 bits.\n                                                                       : ... In instance Uart\n  if(rxDiv == (div/2-1)) begin\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/180217218/fpga/src/uart.v:90: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 4 bits.\n                                                                       : ... In instance Uart\n     rxDiv <= div/4;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/180217218/fpga/src/uart.v:159: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'txDiv\' generates 3 bits.\n                                                                        : ... In instance Uart\n  if(txDiv == (div/2-1)) begin\n           ^~\n%Error: Exiting due to 3 warning(s)\n'
module Uart #(
	parameter div = 12
)(
	input clk,
	
	input rx,
	output reg cts = 0,
	
	output reg tx = 1,
	input rts,
	
	input [7:0] dataSend,
	input dataSendCmd,
	input dataSendValid,
	output reg dataSendAck = 1,
	
	output reg [7:0] dataRecv = 0,
	output reg dataRecvCmd = 0,
	output reg dataRecvValid = 0,
	input dataRecvAck,
	input dataRecvThrottle
);

	localparam S_Idle = 0;
	localparam S_Start = 1;
	localparam S_Data = 2;
	localparam S_Stop = 3;
	

	
	reg [1:0] rxBuf = 2'b11;
	reg [7:0] rxData = 0;
	reg [2:0] rxBitCnt = 0;
	reg [2:0] rxDiv = 0;
	reg [1:0] rxState = S_Idle;
	reg rxNext = 0;
	reg rxCmd = 0;
	
	reg dataRecvAckLast = 0;
	
	always @(posedge clk)
	begin

		dataRecvValid <= 0;
		

		rxBuf <= {rxBuf[0],rx};
		

		if(rxDiv == (div/2-1)) begin
			rxDiv <= 0;
			rxNext <= 1;
		end else begin
			rxDiv <= rxDiv + 1;
			rxNext <= 0;
		end
		
		if(dataRecvThrottle) begin
			cts <= 1;
		end else begin
			cts <= 0;
		end


		dataRecvAckLast <= dataRecvAck;
		case(rxState)
			S_Idle: begin



				if(rxBuf == 2'b10) begin
					rxDiv <= div/4;
					rxNext <= 0;
					rxState <= S_Start;
				end
			end
			
			S_Start: begin
				if(rxNext) begin
					rxState <= rxBuf[0] ? S_Idle : S_Data;
				end
			end
			
			S_Data: begin
				if(rxNext) begin
					rxData[rxBitCnt] <= rxBuf[0];
					if(rxBitCnt == 7) begin
						rxBitCnt <= 0;
						rxState <= S_Stop;
					end else begin
						rxBitCnt <= rxBitCnt + 1;
					end
				end
			end
			
			S_Stop: begin
				if(rxNext) begin
					if((rxBuf[0] == 1) && dataRecvAck) begin
						if(rxCmd) begin
							if(rxData == 8'h00) begin
								dataRecv <= 8'h2a;
								dataRecvValid <= 1;
								dataRecvCmd <= 0;
							end else begin
								dataRecv <= rxData;
								dataRecvValid <= 1;
								dataRecvCmd <= 1;
							end
							rxCmd <= 0;
						end else begin
							if(rxData == 8'h2a) begin
								rxCmd <= 1;
							end else begin
								dataRecv <= rxData;
								dataRecvValid <= 1;
								dataRecvCmd <= 0;
							end					
						end

					end
					rxState <= S_Idle;
				end
			end
		endcase
	end
	

	
	reg [7:0] txData = 0;
	reg [2:0] txBitCnt = 0;
	reg [2:0] txDiv = 0;
	reg [1:0] txState = S_Idle;
	reg txNext = 0;
	
	always @(posedge clk)
	begin

		dataSendAck <= 0;
		

		if(txDiv == (div/2-1)) begin
			txDiv <= 0;
			txNext <= 1;
		end else begin
			txDiv <= txDiv + 1;
			txNext <= 0;
		end
		

		case(txState)
			S_Idle: begin
				tx <= 1;
				if(dataSendValid && !rts) begin
					txState <= S_Start;
					txData <= dataSend;
					dataSendAck <= 1;
				end
			end
			
			S_Start: begin
				if(txNext) begin
					tx <= 0;
					txState <= S_Data;
				end
			end
			
			S_Data: begin
				if(txNext) begin
					tx <= txData[txBitCnt];
					if(txBitCnt == 7) begin
						txBitCnt <= 0;
						txState <= S_Stop;
					end else begin
						txBitCnt <= txBitCnt + 1;
					end
				end
			end
			
			S_Stop: begin
				if(txNext) begin
					tx <= 1;
					txState <= S_Idle;
				end
			end
			
		endcase
	end

endmodule
module Uart #(
	parameter div = 12
)(
	input clk,
	
	input rx,
	output reg cts = 0,
	
	output reg tx = 1,
	input rts,
	
	input [7:0] dataSend,
	input dataSendCmd,
	input dataSendValid,
	output reg dataSendAck = 1,
	
	output reg [7:0] dataRecv = 0,
	output reg dataRecvCmd = 0,
	output reg dataRecvValid = 0,
	input dataRecvAck,
	input dataRecvThrottle
);


	localparam S_Idle = 0;
	localparam S_Start = 1;
	localparam S_Data = 2;
	localparam S_Stop = 3;
	

	
	reg [1:0] rxBuf = 2'b11;
	reg [7:0] rxData = 0;
	reg [2:0] rxBitCnt = 0;
	reg [2:0] rxDiv = 0;
	reg [1:0] rxState = S_Idle;
	reg rxNext = 0;
	reg rxCmd = 0;
	
	reg dataRecvAckLast = 0;
	
	always @(posedge clk)
	begin

		dataRecvValid <= 0;
		

		rxBuf <= {rxBuf[0],rx};
		

		if(rxDiv == (div/2-1)) begin
			rxDiv <= 0;
			rxNext <= 1;
		end else begin
			rxDiv <= rxDiv + 1;
			rxNext <= 0;
		end
		
		if(dataRecvThrottle) begin
			cts <= 1;
		end else begin
			cts <= 0;
		end


		dataRecvAckLast <= dataRecvAck;
		case(rxState)
			S_Idle: begin



				if(rxBuf == 2'b10) begin
					rxDiv <= div/4;
					rxNext <= 0;
					rxState <= S_Start;
				end
			end
			
			S_Start: begin
				if(rxNext) begin
					rxState <= rxBuf[0] ? S_Idle : S_Data;
				end
			end
			
			S_Data: begin
				if(rxNext) begin
					rxData[rxBitCnt] <= rxBuf[0];
					if(rxBitCnt == 7) begin
						rxBitCnt <= 0;
						rxState <= S_Stop;
					end else begin
						rxBitCnt <= rxBitCnt + 1;
					end
				end
			end
			
			S_Stop: begin
				if(rxNext) begin
					if((rxBuf[0] == 1) && dataRecvAck) begin
						if(rxCmd) begin
							if(rxData == 8'h00) begin
								dataRecv <= 8'h2a;
								dataRecvValid <= 1;
								dataRecvCmd <= 0;
							end else begin
								dataRecv <= rxData;
								dataRecvValid <= 1;
								dataRecvCmd <= 1;
							end
							rxCmd <= 0;
						end else begin
							if(rxData == 8'h2a) begin
								rxCmd <= 1;
							end else begin
								dataRecv <= rxData;
								dataRecvValid <= 1;
								dataRecvCmd <= 0;
							end					
						end

					end
					rxState <= S_Idle;
				end
			end
		endcase
	end
	

	
	reg [7:0] txData = 0;
	reg [2:0] txBitCnt = 0;
	reg [2:0] txDiv = 0;
	reg [1:0] txState = S_Idle;
	reg txNext = 0;
	
	always @(posedge clk)
	begin

		dataSendAck <= 0;
		

		if(txDiv == (div/2-1)) begin
			txDiv <= 0;
			txNext <= 1;
		end else begin
			txDiv <= txDiv + 1;
			txNext <= 0;
		end
		

		case(txState)
			S_Idle: begin
				tx <= 1;
				if(dataSendValid && !rts) begin
					txState <= S_Start;
					txData <= dataSend;
					dataSendAck <= 1;
				end
			end
			
			S_Start: begin
				if(txNext) begin
					tx <= 0;
					txState <= S_Data;
				end
			end
			
			S_Data: begin
				if(txNext) begin
					tx <= txData[txBitCnt];
					if(txBitCnt == 7) begin
						txBitCnt <= 0;
						txState <= S_Stop;
					end else begin
						txBitCnt <= txBitCnt + 1;
					end
				end
			end
			
			S_Stop: begin
				if(txNext) begin
					tx <= 1;
					txState <= S_Idle;
				end
			end
			
		endcase
	end

endmodule