data/full_repos/permissive/125927162/SPI/SPI_MASTER_tb.v
 line:32: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/SPI/SPI_MASTER_tb.v:23: Unsupported or unknown PLI call: $dumpfie\n      $dumpfie("SPI_MASTER.vcd");\n      ^~~~~~~~\n%Error: data/full_repos/permissive/125927162/SPI/SPI_MASTER_tb.v:24: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_MASTER_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_MASTER_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #2\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_MASTER_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #32\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_MASTER_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk = ~clk;\n          ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SPI_MASTER_tb();
   reg clk;
   wire sclk;
   wire mosi;
   wire ss_n;
   reg 	miso;
   wire data_sent;
   reg 	data_ready;
   reg 	data;
   
   SPI_MASTER #(.BITS(8))
   DUT(
       .clk(clk),
       .sclk(sclk),
       .mosi(mosi),
       .miso(miso),
       .ss_n(ss_n),
       .data_sent(data_sent),
       .data_ready(data_ready),
       .data(data));
   
   initial begin
      $dumpfie("SPI_MASTER.vcd");
      $dumpvars(0, DUT);
      miso <= 1'b0;
      data = 8'b00110101;
      #1
	data_ready = 1;
      #2
	data_ready = 0;
      #32
      $finish;
   end
   
   always #1 clk = ~clk;
   
endmodule
module SPI_MASTER_tb();

   reg clk;
   wire sclk;
   wire mosi;
   wire ss_n;
   reg 	miso;
   wire data_sent;
   reg 	data_ready;
   reg 	data;
   
   SPI_MASTER #(.BITS(8))
   DUT(
       .clk(clk),
       .sclk(sclk),
       .mosi(mosi),
       .miso(miso),
       .ss_n(ss_n),
       .data_sent(data_sent),
       .data_ready(data_ready),
       .data(data));
   
   initial begin
      $dumpfie("SPI_MASTER.vcd");
      $dumpvars(0, DUT);
      miso <= 1'b0;
      data = 8'b00110101;
      #1
	data_ready = 1;
      #2
	data_ready = 0;
      #32
      $finish;
   end
   
   always #1 clk = ~clk;
   
endmodule