data/full_repos/permissive/176378198/src/emulate_pull_down.v
1: b'%Warning-WIDTH: data/full_repos/permissive/176378198/src/emulate_pull_down.v:12: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance emulate_pull_down\n    assign in = {SIZE {(flip_q == 1\'h0) ? 1\'b0 : 1\'bz}};\n                               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/176378198/src/emulate_pull_down.v:22: Operator GT expects 4 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                               : ... In instance emulate_pull_down\n        if (flip_q > 2\'h2) begin  \n                   ^\n%Error: Exiting due to 2 warning(s)\n'
module emulate_pull_down #(parameter SIZE = 1) (
    input                 clk,
    inout      [SIZE-1:0] in,
    output reg [SIZE-1:0] out);

    assign in = {SIZE {(flip_q == 1'h0) ? 1'b0 : 1'bz}};
    
    reg [3:0] flip_d, flip_q;
    reg [SIZE-1:0] saved_d, saved_q;
    
    always @* begin
        saved_d = saved_q;
        flip_d = flip_q;
        
        flip_d = flip_q + 1'h1;
        if (flip_q > 2'h2) begin
            saved_d = in;
        end
        out = saved_q;
    end
    
    always @(posedge clk) begin
        flip_q <= flip_d;
        saved_q <= saved_d;
    end
endmodule
module emulate_pull_down #(parameter SIZE = 1) (
    input                 clk,
    inout      [SIZE-1:0] in,
    output reg [SIZE-1:0] out);


    assign in = {SIZE {(flip_q == 1'h0) ? 1'b0 : 1'bz}};
    
    reg [3:0] flip_d, flip_q;
    reg [SIZE-1:0] saved_d, saved_q;
    
    always @* begin
        saved_d = saved_q;
        flip_d = flip_q;
        
        flip_d = flip_q + 1'h1;
        if (flip_q > 2'h2) begin
            saved_d = in;
        end
        out = saved_q;
    end
    
    always @(posedge clk) begin
        flip_q <= flip_d;
        saved_q <= saved_d;
    end
endmodule