data/full_repos/permissive/147466718/LC3_ALU.v
data/verilator_xmls/6515ba50-7605-4c90-b37b-568e1b64eedd.xml
module LC3_ALU(
    input [15:0] B,
    input [15:0] A,
    input [1:0] ALUK,
    output reg [15:0] ALU
    );
	 

    always @(*) begin
        case (ALUK)
	    2'd0: ALU = A + B;
	    2'd1: ALU = A & B;
	    2'd2: ALU = ~A;
	    2'd3: ALU = A | B;
	    default: $display("ERROR: INVALID ALUK SIGNAL"); 

	endcase
    end
endmodule
module LC3_ALU(
    input [15:0] B,
    input [15:0] A,
    input [1:0] ALUK,
    output reg [15:0] ALU
    );

	 

    always @(*) begin
        case (ALUK)
	    2'd0: ALU = A + B;
	    2'd1: ALU = A & B;
	    2'd2: ALU = ~A;
	    2'd3: ALU = A | B;
	    default: $display("ERROR: INVALID ALUK SIGNAL"); 

	endcase
    end
endmodule