data/full_repos/permissive/20203077/robsparts.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/20203077/robsparts.v:19: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'register\'\nmodule register # (parameter N = 8)\n       ^~~~~~~~\n                                                                     : ... Top module \'register_hl\'\nmodule register_hl # (parameter N = 16)\n       ^~~~~~~~~~~\n                                                                     : ... Top module \'upcreg\'\nmodule upcreg(\n       ^~~~~~\n                                                                     : ... Top module \'mux5\'\nmodule mux5 (input      d0, d1, d2, d3, d4,\n       ^~~~\n                                                                     : ... Top module \'addsub\'\nmodule addsub\n       ^~~~~~\n                                                                     : ... Top module \'counter_down\'\nmodule counter_down\n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module upcreg(
    input clk,
    input reset,
    input load_incr,
    input [4:0] upc_next,
    output reg [4:0] upc);

    always @ (posedge clk, posedge reset)
        if (reset)  upc <= 5'b00000;
        else if (load_incr) upc <= upc_next;
        else if (~load_incr) upc <= upc + 1;
        else upc <= 5'b00000;

endmodule
module upcreg(
    input clk,
    input reset,
    input load_incr,
    input [4:0] upc_next,
    output reg [4:0] upc);


    always @ (posedge clk, posedge reset)
        if (reset)  upc <= 5'b00000;
        else if (load_incr) upc <= upc_next;
        else if (~load_incr) upc <= upc + 1;
        else upc <= 5'b00000;

endmodule