data/full_repos/permissive/201025648/Verilog/3.38.v
 line:11: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/201025648/Verilog/3.38.v:9: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clock=~clock; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/201025648/Verilog/3.38.v:11: syntax error, unexpected begin\nbegin\n^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb92;

reg Clock, reset, d; 
wire q2, q3;

initial clock=0;
always #5 clock=~clock; 
initial d= 1;
begin

reset= 1

# 12 reset =0; 
#11 reset=1;
# 17 $stop;

end

dff2 dff2(clock, reset, d, q2);


endmodule
module tb92;


reg Clock, reset, d; 
wire q2, q3;

initial clock=0;
always #5 clock=~clock; 
initial d= 1;
begin

reset= 1

# 12 reset =0; 
#11 reset=1;
# 17 $stop;

end

dff2 dff2(clock, reset, d, q2);


endmodule