data/full_repos/permissive/116468596/rectangleSM.v
1: b"%Error: data/full_repos/permissive/116468596/rectangleSM.v:48: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n             FDRE\n             FDRE.v\n             FDRE.sv\n             obj_dir/FDRE\n             obj_dir/FDRE.v\n             obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/rectangleSM.v:49: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));\n    ^~~~\n%Error: data/full_repos/permissive/116468596/rectangleSM.v:50: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));\n    ^~~~\n%Error: data/full_repos/permissive/116468596/rectangleSM.v:51: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0)) ff_instance_3 (.C(clk), .CE(1'b1), .D(inD[3]), .Q(outQ[3]));\n    ^~~~\n%Error: Exiting due to 4 error(s)\n"
module rectangleSM(
    input hit, allHit, timeOut,
    input clk, btnC,
    output startState,loadTime,
    output returnHit, resetState,
    output flash, go, activeRed
    );
    wire [9:0] con;
    wire [3:0] inD;
    wire [3:0] outQ;
    assign con[0] = ~btnC & outQ[0];
    assign con[1] = btnC & outQ[0];
    assign con[2] = ~hit & outQ[1];
    assign con[3] = hit & outQ[1] & ~timeOut;
    assign con[4] = ~allHit & outQ[2] & ~timeOut;
    assign con[5] = allHit & outQ[2];
    assign con[6] = ~btnC & outQ[3];
    assign con[7] = (btnC & outQ[3])|timeOut;
    assign con[8] = timeOut & outQ[2];
    assign con[9] = timeOut & outQ[1];
    assign inD[0] = con[0];
    assign inD[1] = con[1] | con[2] | con[7] | con[8];
    assign inD[2] = con[3] | con[4];
    assign inD[3] = con[5] | con[6];
    
    FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));
    FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));
    FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));
    FDRE #(.INIT(1'b0)) ff_instance_3 (.C(clk), .CE(1'b1), .D(inD[3]), .Q(outQ[3]));
    
    assign loadTime = con[8] | con[9];
    assign startState = outQ[0];
    assign resetState = con[7] | timeOut;
    assign returnHit = outQ[2] | outQ[3] ;
    assign go = outQ[1];
    assign flash = outQ[2] | outQ[3];
    assign activeRed = outQ[1];

endmodule
module rectangleSM(
    input hit, allHit, timeOut,
    input clk, btnC,
    output startState,loadTime,
    output returnHit, resetState,
    output flash, go, activeRed
    );

    wire [9:0] con;
    wire [3:0] inD;
    wire [3:0] outQ;
    assign con[0] = ~btnC & outQ[0];
    assign con[1] = btnC & outQ[0];
    assign con[2] = ~hit & outQ[1];
    assign con[3] = hit & outQ[1] & ~timeOut;
    assign con[4] = ~allHit & outQ[2] & ~timeOut;
    assign con[5] = allHit & outQ[2];
    assign con[6] = ~btnC & outQ[3];
    assign con[7] = (btnC & outQ[3])|timeOut;
    assign con[8] = timeOut & outQ[2];
    assign con[9] = timeOut & outQ[1];
    assign inD[0] = con[0];
    assign inD[1] = con[1] | con[2] | con[7] | con[8];
    assign inD[2] = con[3] | con[4];
    assign inD[3] = con[5] | con[6];
    
    FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));
    FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));
    FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));
    FDRE #(.INIT(1'b0)) ff_instance_3 (.C(clk), .CE(1'b1), .D(inD[3]), .Q(outQ[3]));
    
    assign loadTime = con[8] | con[9];
    assign startState = outQ[0];
    assign resetState = con[7] | timeOut;
    assign returnHit = outQ[2] | outQ[3] ;
    assign go = outQ[1];
    assign flash = outQ[2] | outQ[3];
    assign activeRed = outQ[1];

endmodule