data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/xge/rtl/verilog/rx_checker.v
data/verilator_xmls/7213ae06-5717-4597-900e-6e80c6bb8288.xml
module rx_checker
  (
   input clk156,
   input rst,
   input enable,
   output reg done,
   output reg correct,
   output reg [1:0] error,

   input pkt_rx_avail,
   input pkt_rx_val,
   input pkt_rx_sop,
   input pkt_rx_eop,
   input [2:0] pkt_rx_mod,
   input [63:0] pkt_rx_data,
   input pkt_rx_err,
   output reg pkt_rx_ren
   );


   reg [10:0] 	 payload;
   reg [10:0] 	 count;
   reg [7:0] 	 state;

   
always @(posedge clk156)
  if (rst)
    begin

       state <= `IDLE;
       done <= 0;
       correct <= 0;
       error <= 0;
       pkt_rx_ren <= 0;
       count <= 0;
       payload <= 45;
    end
  else
    begin

       state <= state;
       done <= 0;
       correct <= 0;
       error <= 0;
       pkt_rx_ren <= 0;
       count <= count;
       payload <= payload;
       
            
       case(state)


	 `IDLE: begin
	    if (enable)  
	      state <= `SEARCH;
	 end






	 `SEARCH: begin
	      if (pkt_rx_val)
	      state <= `ERROR1;
	    else if (payload == 1500)
	      state <= `DONE;
	    else if (pkt_rx_avail)
	      begin
		 payload <= payload + 1; 
		 pkt_rx_ren <= 1;
		 state <= `RECEIVE1;
	      end
	 end





	 `RECEIVE1: begin
	    pkt_rx_ren <= 1;
	    
	    if (pkt_rx_err)
	      state <= `ERROR3;
	    else if (pkt_rx_val && pkt_rx_sop && ~pkt_rx_eop)
	      begin
		 if ((pkt_rx_data[63:16] == 48'h0001020304) && (pkt_rx_data[15:0] == 16'h0000) && (pkt_rx_mod == 3'h0))
		   state <= `RECEIVE2;
		 else
		   state <= `ERROR2;
	      end	    
	    else if (pkt_rx_val || pkt_rx_sop || pkt_rx_eop)
	      begin
		 state <= `ERROR1;
	      end
	 end




	 `RECEIVE2: begin
	    pkt_rx_ren <= 1;
	    
	    if (pkt_rx_err)
	      state <= `ERROR3;
	    else if (pkt_rx_val && ~pkt_rx_sop && ~pkt_rx_eop)
	      begin
		 if ((pkt_rx_data[63:32] == 32'h05060708) && 
		     (pkt_rx_data[31:16] == 16'h88b5) && 
		     (pkt_rx_data[15:0] == 16'hBEEF) && 
		     (pkt_rx_mod == 3'h0))
		   begin
		      count <= payload - 2;
		      state <= `RECEIVE3;
		   end
		 else
		   state <= `ERROR2;
	      end	    
	    else if (~pkt_rx_val || pkt_rx_sop || pkt_rx_eop)
	      begin
		 state <= `ERROR1;
	      end
	 end






	 `RECEIVE3: begin
	    count <= count - 8;
	    
	    if (pkt_rx_err)
	      state <= `ERROR3;
	    else if (pkt_rx_val && ~pkt_rx_sop) 
	      begin
		 case({pkt_rx_eop,pkt_rx_mod})
		   4'b0000: begin
		      if (pkt_rx_data[63:0] == {8{count[10:3]}})
			begin
			   pkt_rx_ren <= 1;
			   state <= `RECEIVE3;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1000: begin
		      if (pkt_rx_data[63:0] == {8{count[10:3]}})
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1001: begin
		      if (pkt_rx_data[63:56] == {1{count[10:3]}})	      
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end	     
		      else
			state <= `ERROR2;
		   end
		   4'b1010: begin
		      if (pkt_rx_data[63:48] == {2{count[10:3]}})		
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1011: begin
		      if (pkt_rx_data[63:40] == {3{count[10:3]}})		
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1100: begin
		      if (pkt_rx_data[63:32] == {4{count[10:3]}})
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1101: begin
		      if (pkt_rx_data[63:24] == {5{count[10:3]}})
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1110: begin
		      if (pkt_rx_data[63:16] == {6{count[10:3]}})
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1111: begin
		      if (pkt_rx_data[63:8] == {7{count[10:3]}})
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   default: state <= `ERROR1;
		 endcase
	      end	   
	 end




	 `DONE: begin
	    done <= 1;
	    correct <= 1;
	 end




	 `ERROR1: begin
	    done <= 1;
	    error <= 1;
	 end




	 `ERROR2: begin
	    done <= 1;
	    error <= 2;
	 end




	 `ERROR3: begin
	    done <= 1;
	    error <= 3;
	 end
       endcase
    end

endmodule
module rx_checker
  (
   input clk156,
   input rst,
   input enable,
   output reg done,
   output reg correct,
   output reg [1:0] error,

   input pkt_rx_avail,
   input pkt_rx_val,
   input pkt_rx_sop,
   input pkt_rx_eop,
   input [2:0] pkt_rx_mod,
   input [63:0] pkt_rx_data,
   input pkt_rx_err,
   output reg pkt_rx_ren
   );



   reg [10:0] 	 payload;
   reg [10:0] 	 count;
   reg [7:0] 	 state;

   
always @(posedge clk156)
  if (rst)
    begin

       state <= `IDLE;
       done <= 0;
       correct <= 0;
       error <= 0;
       pkt_rx_ren <= 0;
       count <= 0;
       payload <= 45;
    end
  else
    begin

       state <= state;
       done <= 0;
       correct <= 0;
       error <= 0;
       pkt_rx_ren <= 0;
       count <= count;
       payload <= payload;
       
            
       case(state)


	 `IDLE: begin
	    if (enable)  
	      state <= `SEARCH;
	 end






	 `SEARCH: begin
	      if (pkt_rx_val)
	      state <= `ERROR1;
	    else if (payload == 1500)
	      state <= `DONE;
	    else if (pkt_rx_avail)
	      begin
		 payload <= payload + 1; 
		 pkt_rx_ren <= 1;
		 state <= `RECEIVE1;
	      end
	 end





	 `RECEIVE1: begin
	    pkt_rx_ren <= 1;
	    
	    if (pkt_rx_err)
	      state <= `ERROR3;
	    else if (pkt_rx_val && pkt_rx_sop && ~pkt_rx_eop)
	      begin
		 if ((pkt_rx_data[63:16] == 48'h0001020304) && (pkt_rx_data[15:0] == 16'h0000) && (pkt_rx_mod == 3'h0))
		   state <= `RECEIVE2;
		 else
		   state <= `ERROR2;
	      end	    
	    else if (pkt_rx_val || pkt_rx_sop || pkt_rx_eop)
	      begin
		 state <= `ERROR1;
	      end
	 end




	 `RECEIVE2: begin
	    pkt_rx_ren <= 1;
	    
	    if (pkt_rx_err)
	      state <= `ERROR3;
	    else if (pkt_rx_val && ~pkt_rx_sop && ~pkt_rx_eop)
	      begin
		 if ((pkt_rx_data[63:32] == 32'h05060708) && 
		     (pkt_rx_data[31:16] == 16'h88b5) && 
		     (pkt_rx_data[15:0] == 16'hBEEF) && 
		     (pkt_rx_mod == 3'h0))
		   begin
		      count <= payload - 2;
		      state <= `RECEIVE3;
		   end
		 else
		   state <= `ERROR2;
	      end	    
	    else if (~pkt_rx_val || pkt_rx_sop || pkt_rx_eop)
	      begin
		 state <= `ERROR1;
	      end
	 end






	 `RECEIVE3: begin
	    count <= count - 8;
	    
	    if (pkt_rx_err)
	      state <= `ERROR3;
	    else if (pkt_rx_val && ~pkt_rx_sop) 
	      begin
		 case({pkt_rx_eop,pkt_rx_mod})
		   4'b0000: begin
		      if (pkt_rx_data[63:0] == {8{count[10:3]}})
			begin
			   pkt_rx_ren <= 1;
			   state <= `RECEIVE3;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1000: begin
		      if (pkt_rx_data[63:0] == {8{count[10:3]}})
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1001: begin
		      if (pkt_rx_data[63:56] == {1{count[10:3]}})	      
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end	     
		      else
			state <= `ERROR2;
		   end
		   4'b1010: begin
		      if (pkt_rx_data[63:48] == {2{count[10:3]}})		
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1011: begin
		      if (pkt_rx_data[63:40] == {3{count[10:3]}})		
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1100: begin
		      if (pkt_rx_data[63:32] == {4{count[10:3]}})
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1101: begin
		      if (pkt_rx_data[63:24] == {5{count[10:3]}})
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1110: begin
		      if (pkt_rx_data[63:16] == {6{count[10:3]}})
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   4'b1111: begin
		      if (pkt_rx_data[63:8] == {7{count[10:3]}})
			begin
			   pkt_rx_ren <= 0;	     
			   state <= `SEARCH;
			end
		      else
			state <= `ERROR2;
		   end
		   default: state <= `ERROR1;
		 endcase
	      end	   
	 end




	 `DONE: begin
	    done <= 1;
	    correct <= 1;
	 end




	 `ERROR1: begin
	    done <= 1;
	    error <= 1;
	 end




	 `ERROR2: begin
	    done <= 1;
	    error <= 2;
	 end




	 `ERROR3: begin
	    done <= 1;
	    error <= 3;
	 end
       endcase
    end

endmodule