data/full_repos/permissive/141525667/Source/hdl/directDigitalSynthesizer.v
data/verilator_xmls/1612deda-0e7d-4298-8f0d-feace1de6d3d.xml
module squareGenerator
(
    input clk,
    input rst,
    input[31:0] phase,
    input[31:0] frequency,

    output[7:0] dacLevel
);
    reg[31:0] phaseAccumulator;

    assign dacLevel = {8{phaseAccumulator[31]}};

    always@(posedge clk, posedge rst)
    begin
        if(rst == 1'b1)
        begin
            phaseAccumulator <= 32'b0;
        end

        else
        begin
            phaseAccumulator <= phaseAccumulator + frequency + phase;
        end
    end
endmodule
module squareGenerator
(
    input clk,
    input rst,
    input[31:0] phase,
    input[31:0] frequency,

    output[7:0] dacLevel
);

    reg[31:0] phaseAccumulator;

    assign dacLevel = {8{phaseAccumulator[31]}};

    always@(posedge clk, posedge rst)
    begin
        if(rst == 1'b1)
        begin
            phaseAccumulator <= 32'b0;
        end

        else
        begin
            phaseAccumulator <= phaseAccumulator + frequency + phase;
        end
    end
endmodule