data/full_repos/permissive/141525667/Source/hdl/testBenches/testBench_clockDivider.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/141525667/Source/hdl/testBenches/testBench_clockDivider.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/141525667/Source/hdl/testBenches/testBench_clockDivider.v:30: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/141525667/Source/hdl/testBenches/testBench_clockDivider.v:20: Cannot find file containing module: \'clockDivider\'\n    clockDivider #(5000)dut(clk, rst, slowerClock);\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141525667/Source/hdl/testBenches,data/full_repos/permissive/141525667/clockDivider\n             data/full_repos/permissive/141525667/Source/hdl/testBenches,data/full_repos/permissive/141525667/clockDivider.v\n             data/full_repos/permissive/141525667/Source/hdl/testBenches,data/full_repos/permissive/141525667/clockDivider.sv\n             clockDivider\n             clockDivider.v\n             clockDivider.sv\n             obj_dir/clockDivider\n             obj_dir/clockDivider.v\n             obj_dir/clockDivider.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testBench_clockDivider;


    reg clk;
    reg rst;



    wire slowerClock;

    clockDivider #(5000)dut(clk, rst, slowerClock);

    initial
    begin
        clk <= 0;
        rst <= 1;
        #20
        rst <= 0;
    end

    always #10 clk = ~clk;

 endmodule
module testBench_clockDivider;



    reg clk;
    reg rst;



    wire slowerClock;

    clockDivider #(5000)dut(clk, rst, slowerClock);

    initial
    begin
        clk <= 0;
        rst <= 1;
        #20
        rst <= 0;
    end

    always #10 clk = ~clk;

 endmodule