data/full_repos/permissive/101862289/baud_gen.v
data/verilator_xmls/52781b4a-712f-4252-901d-51e6e0a57ede.xml
module baud_gen(
    input clk,
    input rst,
    output cy
    );

reg[15:0] Q;

assign cy=(Q==16'd3);

always@(posedge clk)
begin
	if(rst|cy) Q<=16'd0;
	else Q<=Q+1;
end



endmodule
module baud_gen(
    input clk,
    input rst,
    output cy
    );


reg[15:0] Q;

assign cy=(Q==16'd3);

always@(posedge clk)
begin
	if(rst|cy) Q<=16'd0;
	else Q<=Q+1;
end



endmodule