data/full_repos/permissive/166661632/p4/P4/EXT.v
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data/verilator_xmls/8e7d02f2-c57e-4c98-94f8-787a23b582c0.xml
module EXT(imm,extop,extout);
input [15:0]imm;
input [1:0] extop;
output [31:0] extout;

wire [31:0]tmp[3:0];
assign tmp[0]={16'b0,imm};
assign tmp[1]={{16{imm[15]}},imm};
assign tmp[2]={imm,16'b0};
assign extout=tmp[extop];

endmodule
module EXT(imm,extop,extout);

input [15:0]imm;
input [1:0] extop;
output [31:0] extout;

wire [31:0]tmp[3:0];
assign tmp[0]={16'b0,imm};
assign tmp[1]={{16{imm[15]}},imm};
assign tmp[2]={imm,16'b0};
assign extout=tmp[extop];

endmodule