data/full_repos/permissive/173670949/uart_mirror/uart_mirror.v
1: b"%Error: data/full_repos/permissive/173670949/uart_mirror/uart_mirror.v:22: Cannot find file containing module: 'uart_rx'\n    uart_rx #(.UART_BAUD(9600)) rx (\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173670949/uart_mirror,data/full_repos/permissive/173670949/uart_rx\n             data/full_repos/permissive/173670949/uart_mirror,data/full_repos/permissive/173670949/uart_rx.v\n             data/full_repos/permissive/173670949/uart_mirror,data/full_repos/permissive/173670949/uart_rx.sv\n             uart_rx\n             uart_rx.v\n             uart_rx.sv\n             obj_dir/uart_rx\n             obj_dir/uart_rx.v\n             obj_dir/uart_rx.sv\n%Error: data/full_repos/permissive/173670949/uart_mirror/uart_mirror.v:39: Cannot find file containing module: 'ram'\n    ram ram_inst (\n    ^~~\n%Error: data/full_repos/permissive/173670949/uart_mirror/uart_mirror.v:56: Cannot find file containing module: 'uart_tx2'\n    uart_tx2 #(.UART_BAUD(9600)) tx (\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module UART_Mirror (
    input  ICE_CLK,
    input  UART_RX,
    output UART_TX,
    output J3_10,
    output J3_9,
    output J3_8,
    output GLED5,
    output RLED1,
    output RLED2,
    output RLED3,
    output RLED4
);


    wire       rx_dv;
    wire [7:0] rx_byte;

    uart_rx #(.UART_BAUD(9600)) rx (
        ICE_CLK,
        UART_RX,
        rx_dv,
        rx_byte
    );


    wire [7:0] ram_din;
    reg  [8:0] ram_write_addr = 0;
    wire       ram_write_en;
    reg  [8:0] ram_read_addr  = 0;
    wire [7:0] ram_dout;

    assign ram_din      = rx_byte;
    assign ram_write_en = rx_dv;

    ram ram_inst (
        ICE_CLK,
        ram_write_addr,
        ram_din,
        ram_write_en,
        ram_read_addr,
        ram_dout
    );


    reg        tx_dv;
    wire [7:0] tx_byte;
    wire       tx_data;
    wire       tx_done;

    assign tx_byte = ram_dout;

    uart_tx2 #(.UART_BAUD(9600)) tx (
        ICE_CLK,
        tx_dv,
        tx_byte,
        tx_data,
        tx_done
    );


    always @(posedge rx_dv) begin
        ram_write_addr <= ram_write_addr + 1;
    end


    always @(posedge ICE_CLK) begin
        if ((ram_write_addr > ram_read_addr) && tx_done) begin
            ram_read_addr <= ram_read_addr + 1;
            tx_dv <= 1;
        end else begin
            tx_dv <= 0;
        end


        if (ram_write_addr == 0) begin
            ram_read_addr <= 0;
        end
    end

    assign UART_TX = tx_data;
    assign J3_10   = tx_dv;
    assign J3_9    = UART_TX;
    assign J3_8    = UART_RX;

    assign GLED5 = ~UART_TX;




endmodule
module UART_Mirror (
    input  ICE_CLK,
    input  UART_RX,
    output UART_TX,
    output J3_10,
    output J3_9,
    output J3_8,
    output GLED5,
    output RLED1,
    output RLED2,
    output RLED3,
    output RLED4
);



    wire       rx_dv;
    wire [7:0] rx_byte;

    uart_rx #(.UART_BAUD(9600)) rx (
        ICE_CLK,
        UART_RX,
        rx_dv,
        rx_byte
    );


    wire [7:0] ram_din;
    reg  [8:0] ram_write_addr = 0;
    wire       ram_write_en;
    reg  [8:0] ram_read_addr  = 0;
    wire [7:0] ram_dout;

    assign ram_din      = rx_byte;
    assign ram_write_en = rx_dv;

    ram ram_inst (
        ICE_CLK,
        ram_write_addr,
        ram_din,
        ram_write_en,
        ram_read_addr,
        ram_dout
    );


    reg        tx_dv;
    wire [7:0] tx_byte;
    wire       tx_data;
    wire       tx_done;

    assign tx_byte = ram_dout;

    uart_tx2 #(.UART_BAUD(9600)) tx (
        ICE_CLK,
        tx_dv,
        tx_byte,
        tx_data,
        tx_done
    );


    always @(posedge rx_dv) begin
        ram_write_addr <= ram_write_addr + 1;
    end


    always @(posedge ICE_CLK) begin
        if ((ram_write_addr > ram_read_addr) && tx_done) begin
            ram_read_addr <= ram_read_addr + 1;
            tx_dv <= 1;
        end else begin
            tx_dv <= 0;
        end


        if (ram_write_addr == 0) begin
            ram_read_addr <= 0;
        end
    end

    assign UART_TX = tx_data;
    assign J3_10   = tx_dv;
    assign J3_9    = UART_TX;
    assign J3_8    = UART_RX;

    assign GLED5 = ~UART_TX;




endmodule