data/full_repos/permissive/157101210/alu.v
data/verilator_xmls/37bfacbe-b9ac-4c25-bf23-ddd091e41228.xml
module didOverflow
(
    output overflow,
    input a, 
    input b, 
    input s,
    input sub
);
    wire BxorSub;
    wire notA;
    wire notB;
    wire notS;
    wire aAndB;
    wire notaAndNotb;
    wire negToPos;
    wire posToNeg;
    xor xorgate(BxorSub, b, sub);
    not aNot(notA, a);
    not bNot(notB, BxorSub);
    not sNot(notS, s);
    and andab(aAndB, a, BxorSub);
    and andabNot(notaAndNotb, notA, notB);
    and andSwitch1(negToPos, aAndB, notS);
    and andSwitch2(posToNeg, notaAndNotb, s);
    or orGate(overflow, negToPos, posToNeg);
endmodule
module didOverflow
(
    output overflow,
    input a, 
    input b, 
    input s,
    input sub
);

    wire BxorSub;
    wire notA;
    wire notB;
    wire notS;
    wire aAndB;
    wire notaAndNotb;
    wire negToPos;
    wire posToNeg;
    xor xorgate(BxorSub, b, sub);
    not aNot(notA, a);
    not bNot(notB, BxorSub);
    not sNot(notS, s);
    and andab(aAndB, a, BxorSub);
    and andabNot(notaAndNotb, notA, notB);
    and andSwitch1(negToPos, aAndB, notS);
    and andSwitch2(posToNeg, notaAndNotb, s);
    or orGate(overflow, negToPos, posToNeg);
endmodule