data/full_repos/permissive/159016511/src/rtl/core/imm_gen.v
None: at end of input
1: b'%Error: data/full_repos/permissive/159016511/src/rtl/core/imm_gen.v:25: Cannot find include file: core_defines.vh\n`include "core_defines.vh" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159016511/src/rtl/core,data/full_repos/permissive/159016511/core_defines.vh\n             data/full_repos/permissive/159016511/src/rtl/core,data/full_repos/permissive/159016511/core_defines.vh.v\n             data/full_repos/permissive/159016511/src/rtl/core,data/full_repos/permissive/159016511/core_defines.vh.sv\n             core_defines.vh\n             core_defines.vh.v\n             core_defines.vh.sv\n             obj_dir/core_defines.vh\n             obj_dir/core_defines.vh.v\n             obj_dir/core_defines.vh.sv\n%Error: data/full_repos/permissive/159016511/src/rtl/core/imm_gen.v:28: Define or directive not defined: \'`INSTR_WIDTH\'\ninput wire [`INSTR_WIDTH - 1 : 0] instr,  \n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/imm_gen.v:34: Define or directive not defined: \'`DATA_WIDTH\'\noutput reg [`DATA_WIDTH - 1 : 0] imm   \n            ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module imm_gen (
input wire [`INSTR_WIDTH - 1 : 0] instr,
input wire imm_is_I_type,
input wire imm_is_S_type,
input wire imm_is_B_type,
input wire imm_is_J_type,
input wire imm_is_U_type,
output reg [`DATA_WIDTH - 1 : 0] imm
);





wire [4:0] imm_type;
assign imm_type = {imm_is_I_type,imm_is_S_type,imm_is_B_type,imm_is_J_type,imm_is_U_type};

always @ *
begin
	case (imm_type)
	5'b00001: imm = {instr[31:12],12'b0};
	5'b00010: imm =	{{12{instr[31]}},instr[19:12],instr[20],instr[30:21],1'b0};
	5'b00100: imm = {{20{instr[31]}},instr[7],instr[30:25],instr[11:8],1'b0};
	5'b01000: imm = {{21{instr[31]}},instr[30:25],instr[11:7]};
	5'b10000: imm = {{21{instr[31]}},instr[30:20]};
	default : imm = 32'b0;
	endcase
end

endmodule
module imm_gen (
input wire [`INSTR_WIDTH - 1 : 0] instr,
input wire imm_is_I_type,
input wire imm_is_S_type,
input wire imm_is_B_type,
input wire imm_is_J_type,
input wire imm_is_U_type,
output reg [`DATA_WIDTH - 1 : 0] imm
);






wire [4:0] imm_type;
assign imm_type = {imm_is_I_type,imm_is_S_type,imm_is_B_type,imm_is_J_type,imm_is_U_type};

always @ *
begin
	case (imm_type)
	5'b00001: imm = {instr[31:12],12'b0};
	5'b00010: imm =	{{12{instr[31]}},instr[19:12],instr[20],instr[30:21],1'b0};
	5'b00100: imm = {{20{instr[31]}},instr[7],instr[30:25],instr[11:8],1'b0};
	5'b01000: imm = {{21{instr[31]}},instr[30:25],instr[11:7]};
	5'b10000: imm = {{21{instr[31]}},instr[30:20]};
	default : imm = 32'b0;
	endcase
end

endmodule