data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new/shift_register.v
data/verilator_xmls/041c65e2-53c9-4084-8049-a06a7fe4c361.xml
module shift_register #(parameter dataIN_width=4)(
    input clk, rst, sl, sr, ld, leftIn, rightIn,
    input [dataIN_width - 1 : 0] D,
    output reg [dataIN_width - 1 : 0] Q
    );

always @ (posedge clk)
begin
    if (rst)
        Q = 0;
    else if (ld)
        Q = D;
    else if (sl)
        begin
            Q[dataIN_width - 1 : 1] = Q[dataIN_width - 2 : 0];
            Q[0] = rightIn;
        end
    else if (sr)
        begin
            Q[dataIN_width - 2 : 0] = Q[dataIN_width - 1 : 1];
            Q[dataIN_width - 1] = leftIn; 
        end
    else
        Q[dataIN_width - 1 : 0] = Q[dataIN_width - 1 : 0];
end
endmodule
module shift_register #(parameter dataIN_width=4)(
    input clk, rst, sl, sr, ld, leftIn, rightIn,
    input [dataIN_width - 1 : 0] D,
    output reg [dataIN_width - 1 : 0] Q
    );


always @ (posedge clk)
begin
    if (rst)
        Q = 0;
    else if (ld)
        Q = D;
    else if (sl)
        begin
            Q[dataIN_width - 1 : 1] = Q[dataIN_width - 2 : 0];
            Q[0] = rightIn;
        end
    else if (sr)
        begin
            Q[dataIN_width - 2 : 0] = Q[dataIN_width - 1 : 1];
            Q[dataIN_width - 1] = leftIn; 
        end
    else
        Q[dataIN_width - 1 : 0] = Q[dataIN_width - 1 : 0];
end
endmodule