data/full_repos/permissive/157979234/Semester III/Digital Design and Computer Organization/Session 06/pc.v
1: b'%Error: Cannot find file containing module: III/Digital\n        ... Looked in:\n             data/full_repos/permissive/157979234/Semester/III/Digital\n             data/full_repos/permissive/157979234/Semester/III/Digital.v\n             data/full_repos/permissive/157979234/Semester/III/Digital.sv\n             III/Digital\n             III/Digital.v\n             III/Digital.sv\n             obj_dir/III/Digital\n             obj_dir/III/Digital.v\n             obj_dir/III/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Organization/Session\n%Error: Cannot find file containing module: 06,data/full_repos/permissive/157979234\n%Error: Cannot find file containing module: data/full_repos/permissive/157979234/Semester\n%Error: Cannot find file containing module: 06/pc.v\n%Error: Exiting due to 8 error(s)\n'
module reg_unit(input wire [15:0]in,input load,reset,clk,output wire [15:0]o);

dfrl reg0(clk, reset, load, in[0],o[0]);
dfrl reg1(clk, reset, load, in[1],o[1]);
dfrl reg2(clk, reset, load, in[2],o[2]);
dfrl reg3(clk, reset, load, in[3],o[3]);
dfrl reg4(clk, reset, load, in[4],o[4]);
dfrl reg5(clk, reset, load, in[5],o[5]);
dfrl reg6(clk, reset, load, in[6],o[6]);
dfrl reg7(clk, reset, load, in[7],o[7]);
dfrl reg8(clk, reset, load, in[8],o[8]);
dfrl reg9(clk, reset, load, in[9],o[9]);
dfrl reg10(clk, reset, load, in[10],o[10]);
dfrl reg11(clk, reset, load, in[11],o[11]);
dfrl reg12(clk, reset, load, in[12],o[12]);
dfrl reg13(clk, reset, load, in[13],o[13]);
dfrl reg14(clk, reset, load, in[14],o[14]);
dfrl reg15(clk, reset, load, in[15],o[15]);

endmodule
module reg_unit(input wire [15:0]in,input load,reset,clk,output wire [15:0]o);


dfrl reg0(clk, reset, load, in[0],o[0]);
dfrl reg1(clk, reset, load, in[1],o[1]);
dfrl reg2(clk, reset, load, in[2],o[2]);
dfrl reg3(clk, reset, load, in[3],o[3]);
dfrl reg4(clk, reset, load, in[4],o[4]);
dfrl reg5(clk, reset, load, in[5],o[5]);
dfrl reg6(clk, reset, load, in[6],o[6]);
dfrl reg7(clk, reset, load, in[7],o[7]);
dfrl reg8(clk, reset, load, in[8],o[8]);
dfrl reg9(clk, reset, load, in[9],o[9]);
dfrl reg10(clk, reset, load, in[10],o[10]);
dfrl reg11(clk, reset, load, in[11],o[11]);
dfrl reg12(clk, reset, load, in[12],o[12]);
dfrl reg13(clk, reset, load, in[13],o[13]);
dfrl reg14(clk, reset, load, in[14],o[14]);
dfrl reg15(clk, reset, load, in[15],o[15]);

endmodule