data/full_repos/permissive/156539908/queue/top_tb.v
 line:18: before: "+"
1: b'%Error: data/full_repos/permissive/156539908/queue/top_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("queue.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/156539908/queue/top_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, top_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/156539908/queue/top_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n            #1 CLK = ~CLK;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb();

    reg  CLK;
    wire LEDR_N, LEDG_N;
    integer i;

    top uut(CLK, LEDR_N, LEDG_N);

    initial begin
        $dumpfile("queue.vcd");
        $dumpvars(0, top_tb);
    end

    initial begin
        CLK = 0;
        for (i = 0; i < 5000; i++)
            #1 CLK = ~CLK;
    end

endmodule
module top_tb();


    reg  CLK;
    wire LEDR_N, LEDG_N;
    integer i;

    top uut(CLK, LEDR_N, LEDG_N);

    initial begin
        $dumpfile("queue.vcd");
        $dumpvars(0, top_tb);
    end

    initial begin
        CLK = 0;
        for (i = 0; i < 5000; i++)
            #1 CLK = ~CLK;
    end

endmodule