data/full_repos/permissive/211866113/Register.v
data/verilator_xmls/f7d812cb-e5da-4922-8582-a6fd9d527597.xml
module three_bit_reg( input clk,
		      input 	   reset,
		      input [2:0]  in,
		      output [2:0] out
		      );

	wire [2:0]  _in;

    D_FlipFlop DFF0(in[0], clk, reset, out[0]);
    D_FlipFlop DFF1(in[1], clk, reset, out[1]);
    D_FlipFlop DFF2(in[2], clk, reset, out[2]);

endmodule
module three_bit_reg( input clk,
		      input 	   reset,
		      input [2:0]  in,
		      output [2:0] out
		      );


	wire [2:0]  _in;

    D_FlipFlop DFF0(in[0], clk, reset, out[0]);
    D_FlipFlop DFF1(in[1], clk, reset, out[1]);
    D_FlipFlop DFF2(in[2], clk, reset, out[2]);

endmodule