data/full_repos/permissive/174642777/Experiments/Lab X3/Lab 09 ADD_4bit/FullAdder_test.v
1: b'%Error: Cannot find file containing module: X3/Lab\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X3/Lab\n             data/full_repos/permissive/174642777/Experiments/Lab/X3/Lab.v\n             data/full_repos/permissive/174642777/Experiments/Lab/X3/Lab.sv\n             X3/Lab\n             X3/Lab.v\n             X3/Lab.sv\n             obj_dir/X3/Lab\n             obj_dir/X3/Lab.v\n             obj_dir/X3/Lab.sv\n%Error: Cannot find file containing module: 09\n%Error: Cannot find file containing module: ADD_4bit,data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: ADD_4bit/FullAdder_test.v\n%Error: Exiting due to 5 error(s)\n'
module FullAdder_test;


	reg A;
	reg B;
	reg Cin;


	wire S;
	wire Cout;


	FullAdder uut (
		.A(A), 
		.B(B), 
		.Cin(Cin), 
		.S(S), 
		.Cout(Cout)
	);

	initial begin

		A = 0;
		B = 0;
		Cin = 0;


		#100;
    

    #100
    A <= 0;
    B <= 0;
    Cin <= 0;
    
    #100
    A <= 1;
    B <= 0;
    Cin <= 0;
    
    #100
    A <= 0;
    B <= 1;
    Cin <= 0;
    
    #100
    A <= 1;
    B <= 1;
    Cin <= 0;
    
    #100
    A <= 0;
    B <= 0;
    Cin <= 1;
    
    #100
    A <= 1;
    B <= 0;
    Cin <= 1;
    
    #100
    A <= 0;
    B <= 1;
    Cin <= 1;
    
    #100
    A <= 1;
    B <= 1;
    Cin <= 1;

	end
  
endmodule
module FullAdder_test;



	reg A;
	reg B;
	reg Cin;


	wire S;
	wire Cout;


	FullAdder uut (
		.A(A), 
		.B(B), 
		.Cin(Cin), 
		.S(S), 
		.Cout(Cout)
	);

	initial begin

		A = 0;
		B = 0;
		Cin = 0;


		#100;
    

    #100
    A <= 0;
    B <= 0;
    Cin <= 0;
    
    #100
    A <= 1;
    B <= 0;
    Cin <= 0;
    
    #100
    A <= 0;
    B <= 1;
    Cin <= 0;
    
    #100
    A <= 1;
    B <= 1;
    Cin <= 0;
    
    #100
    A <= 0;
    B <= 0;
    Cin <= 1;
    
    #100
    A <= 1;
    B <= 0;
    Cin <= 1;
    
    #100
    A <= 0;
    B <= 1;
    Cin <= 1;
    
    #100
    A <= 1;
    B <= 1;
    Cin <= 1;

	end
  
endmodule