data/full_repos/permissive/167962127/noise.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/167962127/noise.v:14: Little bit endian vector: MSB < LSB of bit range: 0:15\n  reg [0:15] r_shift16 = 16\'hdead;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module noise(
  input i_clk,
  output reg signed [15:0] o_data
);

  reg [0:15] r_shift16 = 16'hdead;

  always @ (posedge i_clk) begin
    r_shift16[0] <= (((r_shift16[15]^r_shift16[14])^r_shift16[12])^r_shift16[3]);
    r_shift16[1:15] <= r_shift16[0:14];
  end

  always @ (posedge i_clk) begin

    case (r_shift16)
      16'b1000_0000_0000_0000: o_data <= 16'b1000_0000_0000_0001;
                      default: o_data <= r_shift16;
    endcase
  end

endmodule
module noise(
  input i_clk,
  output reg signed [15:0] o_data
);


  reg [0:15] r_shift16 = 16'hdead;

  always @ (posedge i_clk) begin
    r_shift16[0] <= (((r_shift16[15]^r_shift16[14])^r_shift16[12])^r_shift16[3]);
    r_shift16[1:15] <= r_shift16[0:14];
  end

  always @ (posedge i_clk) begin

    case (r_shift16)
      16'b1000_0000_0000_0000: o_data <= 16'b1000_0000_0000_0001;
                      default: o_data <= r_shift16;
    endcase
  end

endmodule