data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/ctrlport_to_regport.v
 line:38: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/ctrlport_to_regport.v:42: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                                                        : ... In instance ctrlport_to_regport\n  output reg  [REG_AWIDTH-1:0] reg_wr_addr  = \'bX,\n                                              ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/ctrlport_to_regport.v:45: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                                                        : ... In instance ctrlport_to_regport\n  output reg  [REG_AWIDTH-1:0] reg_rd_addr  = \'bX,\n                                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/ctrlport_to_regport.v:55: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                                                        : ... In instance ctrlport_to_regport\n      reg_wr_addr          <= \'bX;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/ctrlport_to_regport.v:58: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                                                        : ... In instance ctrlport_to_regport\n      reg_rd_addr          <= \'bX;\n                           ^~\n%Error: Exiting due to 4 warning(s)\n'
module ctrlport_to_regport #(
  parameter REG_AWIDTH = 20,
  parameter REG_DWIDTH = 32
) (
  input clk,
  input rst,

  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,
  output reg         s_ctrlport_resp_ack   = 1'b0,
  output reg  [31:0] s_ctrlport_resp_data  = 'bX,

  output reg                   reg_wr_req   = 1'b0,
  output reg  [REG_AWIDTH-1:0] reg_wr_addr  = 'bX,
  output reg  [REG_DWIDTH-1:0] reg_wr_data  = 'bX,
  output reg                   reg_rd_req   = 1'b0,
  output reg  [REG_AWIDTH-1:0] reg_rd_addr  = 'bX,
  input  wire                  reg_rd_resp,
  input  wire [REG_DWIDTH-1:0] reg_rd_data
);

  always @(posedge clk) begin
    if (rst) begin
      s_ctrlport_resp_ack  <= 1'b0;
      s_ctrlport_resp_data <= 'bx;
      reg_wr_req           <= 1'b0;
      reg_wr_addr          <= 'bX;
      reg_wr_data          <= 'bX;
      reg_rd_req           <= 1'b0;
      reg_rd_addr          <= 'bX;
    end else begin

      s_ctrlport_resp_ack <= 1'b0;
      reg_wr_req          <= 1'b0;
      reg_rd_req          <= 1'b0;


      if (s_ctrlport_req_wr) begin
        reg_wr_req  <= 1'b1;
        reg_wr_addr <= s_ctrlport_req_addr;
        reg_wr_data <= s_ctrlport_req_data;


        s_ctrlport_resp_ack <= 1'b1;
      end


      if (s_ctrlport_req_rd) begin
        reg_rd_req  <= 1'b1;
        reg_rd_addr <= s_ctrlport_req_addr;
      end


      if (reg_rd_resp) begin
        s_ctrlport_resp_ack  <= 1'b1;
        s_ctrlport_resp_data <= reg_rd_data;
      end

    end
  end

endmodule
module ctrlport_to_regport #(
  parameter REG_AWIDTH = 20,
  parameter REG_DWIDTH = 32
) (
  input clk,
  input rst,

  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,
  output reg         s_ctrlport_resp_ack   = 1'b0,
  output reg  [31:0] s_ctrlport_resp_data  = 'bX,

  output reg                   reg_wr_req   = 1'b0,
  output reg  [REG_AWIDTH-1:0] reg_wr_addr  = 'bX,
  output reg  [REG_DWIDTH-1:0] reg_wr_data  = 'bX,
  output reg                   reg_rd_req   = 1'b0,
  output reg  [REG_AWIDTH-1:0] reg_rd_addr  = 'bX,
  input  wire                  reg_rd_resp,
  input  wire [REG_DWIDTH-1:0] reg_rd_data
);


  always @(posedge clk) begin
    if (rst) begin
      s_ctrlport_resp_ack  <= 1'b0;
      s_ctrlport_resp_data <= 'bx;
      reg_wr_req           <= 1'b0;
      reg_wr_addr          <= 'bX;
      reg_wr_data          <= 'bX;
      reg_rd_req           <= 1'b0;
      reg_rd_addr          <= 'bX;
    end else begin

      s_ctrlport_resp_ack <= 1'b0;
      reg_wr_req          <= 1'b0;
      reg_rd_req          <= 1'b0;


      if (s_ctrlport_req_wr) begin
        reg_wr_req  <= 1'b1;
        reg_wr_addr <= s_ctrlport_req_addr;
        reg_wr_data <= s_ctrlport_req_data;


        s_ctrlport_resp_ack <= 1'b1;
      end


      if (s_ctrlport_req_rd) begin
        reg_rd_req  <= 1'b1;
        reg_rd_addr <= s_ctrlport_req_addr;
      end


      if (reg_rd_resp) begin
        s_ctrlport_resp_ack  <= 1'b1;
        s_ctrlport_resp_data <= reg_rd_data;
      end

    end
  end

endmodule