data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #20 clk50 = ~clk50;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:12: Operator ASSIGN expects 113 bits on the Assign RHS, but Assign RHS\'s CONST \'112\'h48656c6c6f20576f726c64210d0a\' generates 112 bits.\n                                                                                       : ... In instance uart_hello_test.u0\n reg [8*14:0] text = "Hello World!\\r\\n";\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:32: Cannot find file containing module: \'reset_delay\'\n reset_delay r0(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/101171422/de2-115/uart_hello,data/full_repos/permissive/101171422/reset_delay\n             data/full_repos/permissive/101171422/de2-115/uart_hello,data/full_repos/permissive/101171422/reset_delay.v\n             data/full_repos/permissive/101171422/de2-115/uart_hello,data/full_repos/permissive/101171422/reset_delay.sv\n             reset_delay\n             reset_delay.v\n             reset_delay.sv\n             obj_dir/reset_delay\n             obj_dir/reset_delay.v\n             obj_dir/reset_delay.sv\n%Error: data/full_repos/permissive/101171422/de2-115/uart_hello/uart_hello.v:37: Cannot find file containing module: \'uart_transmitter\'\n uart_transmitter t0(\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_hello_test();
	reg  clk50;
	wire uart_rts;
	wire uart_rxd;
	wire uart_cts;
	wire uart_txd;
	
	initial begin
		clk50 = 0;
	end
	
	always begin
		#20 clk50 = ~clk50;
	end
	
	uart_hello u0(
		.clk50(clk50),
		.uart_rts(uart_rts),
		.uart_rxd(uart_rxd),
		.uart_cts(uart_cts),
		.uart_txd(uart_txd)
	);
endmodule
module uart_hello_test();

	reg  clk50;
	wire uart_rts;
	wire uart_rxd;
	wire uart_cts;
	wire uart_txd;
	
	initial begin
		clk50 = 0;
	end
	
	always begin
		#20 clk50 = ~clk50;
	end
	
	uart_hello u0(
		.clk50(clk50),
		.uart_rts(uart_rts),
		.uart_rxd(uart_rxd),
		.uart_cts(uart_cts),
		.uart_txd(uart_txd)
	);
endmodule