data/full_repos/permissive/199632300/HDLBits_doc/picture/fsm2s.v
data/verilator_xmls/3b08a8b5-907f-497d-88c8-0bc49ccfdd24.xml
module top_module(
    input clk,
    input reset,
    input j,
    input k,
    output out);

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin

        case (state) 
            OFF: next_state <= j ? ON : OFF;
            ON: next_state <= k ? OFF : ON;
        endcase
    end

    always @(posedge clk) begin

        if(reset) begin
            state <= OFF;
        end else begin
            state <= next_state;
        end
    end
    assign out = (state == ON);
endmodule
module top_module(
    input clk,
    input reset,
    input j,
    input k,
    output out);


    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin

        case (state) 
            OFF: next_state <= j ? ON : OFF;
            ON: next_state <= k ? OFF : ON;
        endcase
    end

    always @(posedge clk) begin

        if(reset) begin
            state <= OFF;
        end else begin
            state <= next_state;
        end
    end
    assign out = (state == ON);
endmodule