data/full_repos/permissive/184916587/DMemory.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/184916587/DMemory.v:15: Duplicate declaration of signal: 'data_r'\n                                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg[31:0] data_r;\n           ^~~~~~\n        data/full_repos/permissive/184916587/DMemory.v:12: ... Location of original declaration\n output[31:0] data_r  \n              ^~~~~~\n%Error: Exiting due to 1 error(s)\n"
module DMemory(
	input Delete,
	input State,
	input[31:0] data_w,
	input[4:0] address,
	output[31:0] data_r
);
	reg[31:0] data_in[31:0];
	reg[31:0] data_r;

	always @(*)
	begin
		if(State===0&&Delete!=1&&address!=0)
			data_in[address]=data_w;
	end

	always @(*)
	begin
		if(State===1&&Delete!=1)
			data_r=data_in[address];
	end

	always @(*)
	begin
		if(Delete===1)
			data_in[address]=0;
	end
endmodule
module DMemory(
	input Delete,
	input State,
	input[31:0] data_w,
	input[4:0] address,
	output[31:0] data_r
);

	reg[31:0] data_in[31:0];
	reg[31:0] data_r;

	always @(*)
	begin
		if(State===0&&Delete!=1&&address!=0)
			data_in[address]=data_w;
	end

	always @(*)
	begin
		if(State===1&&Delete!=1)
			data_r=data_in[address];
	end

	always @(*)
	begin
		if(Delete===1)
			data_in[address]=0;
	end
endmodule