data/full_repos/permissive/206301883/tx_count.v
None: at end of input
data/verilator_xmls/a17c779f-36ab-443e-a0b8-2a14f693c4f5.xml
module tx_count(
input wire new_tx,
output wire [31:0]tx_counter
);
    
reg [31:0]counter = 0;   

assign tx_counter = counter;

always @(posedge new_tx)
    begin
        counter <= counter+1;
    end
endmodule
module tx_count(
input wire new_tx,
output wire [31:0]tx_counter
);

    
reg [31:0]counter = 0;   

assign tx_counter = counter;

always @(posedge new_tx)
    begin
        counter <= counter+1;
    end
endmodule