data/full_repos/permissive/167489907/Examples/RegisterNbit.v
data/verilator_xmls/2b97e876-cc26-42bd-91e6-b5ec0f5446c3.xml
module RegisterNbit(Q, D, L, R, clock);
	parameter N = 8;
	output reg [N-1:0]Q;
	input [N-1:0]D;
	input L;
	input R;
	input clock;
	

always @(posedge clock or posedge R) begin
	if(R)
		Q <= {N{1'b0}};
	else if(L)
		Q <= D;
	else
		Q <= Q;
end
endmodule
module RegisterNbit(Q, D, L, R, clock);

	parameter N = 8;
	output reg [N-1:0]Q;
	input [N-1:0]D;
	input L;
	input R;
	input clock;
	

always @(posedge clock or posedge R) begin
	if(R)
		Q <= {N{1'b0}};
	else if(L)
		Q <= D;
	else
		Q <= Q;
end
endmodule