data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_obct.v
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_obct.v:102: Cannot find include file: mc_defines.v\n`include "mc_defines.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl,data/full_repos/permissive/137416811/mc_defines.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl,data/full_repos/permissive/137416811/mc_defines.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl,data/full_repos/permissive/137416811/mc_defines.v.sv\n             mc_defines.v\n             mc_defines.v.v\n             mc_defines.v.sv\n             obj_dir/mc_defines.v\n             obj_dir/mc_defines.v.v\n             obj_dir/mc_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module mc_obct_dummy(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
		bank_open, any_bank_open, row_same);
input		clk, rst;
input	[12:0]	row_adr;
input	[1:0]	bank_adr;
input		bank_set;
input		bank_clr;
input		bank_clr_all;
output		bank_open;
output		any_bank_open;
output		row_same;

assign bank_open = 1'b0;
assign any_bank_open = 1'b0;
assign row_same = 1'b0;

endmodule
module mc_obct_dummy(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
		bank_open, any_bank_open, row_same);

input		clk, rst;
input	[12:0]	row_adr;
input	[1:0]	bank_adr;
input		bank_set;
input		bank_clr;
input		bank_clr_all;
output		bank_open;
output		any_bank_open;
output		row_same;

assign bank_open = 1'b0;
assign any_bank_open = 1'b0;
assign row_same = 1'b0;

endmodule