data/full_repos/permissive/200478172/source/TempPC.v
data/verilator_xmls/413661bd-4bf8-44b7-b60a-ea44c6ecf23e.xml
module TempPC(
    input clk,
    input reset,
    input ctr,
    input [31:0] pc,
    
    output reg [31:0] z
    );
    always@(posedge clk or posedge reset)begin
        if(reset==1)z<=32'h00400000;
        else begin
            if(ctr==1)z<=pc;
        end
    end
endmodule
module TempPC(
    input clk,
    input reset,
    input ctr,
    input [31:0] pc,
    
    output reg [31:0] z
    );

    always@(posedge clk or posedge reset)begin
        if(reset==1)z<=32'h00400000;
        else begin
            if(ctr==1)z<=pc;
        end
    end
endmodule