data/full_repos/permissive/20688874/viterbi/synviterbidectb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:43: Cannot find include file: syntheziedviterbi.v\n`include "syntheziedviterbi.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/syntheziedviterbi.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/syntheziedviterbi.v.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/syntheziedviterbi.v.sv\n             syntheziedviterbi.v\n             syntheziedviterbi.v.v\n             syntheziedviterbi.v.sv\n             obj_dir/syntheziedviterbi.v\n             obj_dir/syntheziedviterbi.v.v\n             obj_dir/syntheziedviterbi.v.sv\n%Error: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:45: Cannot find include file: /auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v\n`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:95: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:96: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 1;\n     ^\n%Error: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:123: Unsupported or unknown PLI call: $sdf_annotate\n  $sdf_annotate("../sdf/viterbi_decoder.sdf",v_d,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");\n  ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:151: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:157: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:163: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:169: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:181: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:187: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:193: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:199: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:205: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:211: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:217: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:223: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:229: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:235: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:241: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:247: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:253: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:259: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:265: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:271: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:277: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:283: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:289: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:295: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:301: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:307: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:313: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:319: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:325: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:331: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:337: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:343: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:349: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:355: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:361: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:367: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:373: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:379: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/synviterbidectb.v:384: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: Exiting due to 3 error(s), 45 warning(s)\n'
module tb_viterbi_decoder();

	

	wire data;
	
	

	reg [1:0] encoded_input;
	reg clock;
	reg reset_sig;
	
	
	

	viterbi_decoder v_d (


		data,encoded_input,clock,reset_sig);
	
	
	
	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end		
	
	
	
	
	

	

	initial
	begin
		$sdf_annotate("../sdf/viterbi_decoder.sdf",v_d,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
	

		$display(" << Starting the simulation >>");

		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd1;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd3;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd2;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd2;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd3;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd2;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd3;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd2;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 1;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		
		#20;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_viterbi_decoder();


	

	wire data;
	
	

	reg [1:0] encoded_input;
	reg clock;
	reg reset_sig;
	
	
	

	viterbi_decoder v_d (


		data,encoded_input,clock,reset_sig);
	
	
	
	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end		
	
	
	
	
	

	

	initial
	begin
		$sdf_annotate("../sdf/viterbi_decoder.sdf",v_d,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
	

		$display(" << Starting the simulation >>");

		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd1;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd3;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd2;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd2;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd3;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd2;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd3;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd0;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd1;
		
		

		#10
		reset_sig = 1'd0;
		encoded_input = 2'd2;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 1;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		

		#10
		reset_sig = 0;
		encoded_input = $random;
		
		
		#20;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule