data/full_repos/permissive/162928820/main_con_new.v
 line:247: before: "/"
1: b'%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:115: Operator ADD expects 32 or 14 bits on the LHS, but LHS\'s VARREF \'num0_reg\' generates 4 bits.\n                                                                       : ... In instance main_con_new\n frequency <= num0_reg + num1_reg*10 + num2_reg*100 + num3_reg*1000;  \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:123: Operator ADD expects 30 bits on the LHS, but LHS\'s REPLICATE generates 9 bits.\n                                                                       : ... In instance main_con_new\n  temp <= ({1\'b0,addr} + 1\'b1) * (yshang[28:8]) + ((({1\'b0,addr} + 1\'b1) * (yshang[7:0])) >> 8);\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:123: Operator ADD expects 30 bits on the LHS, but LHS\'s REPLICATE generates 9 bits.\n                                                                       : ... In instance main_con_new\n  temp <= ({1\'b0,addr} + 1\'b1) * (yshang[28:8]) + ((({1\'b0,addr} + 1\'b1) * (yshang[7:0])) >> 8);\n                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:137: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance main_con_new\n   addr <= 1\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:127: Operator EQ expects 30 bits on the LHS, but LHS\'s VARREF \'yshang_temp\' generates 29 bits.\n                                                                       : ... In instance main_con_new\n  if(yshang_temp == temp) begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:159: Operator ASSIGNW expects 29 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                       : ... In instance main_con_new\nassign default_frq = x[2]==1 ? (x[3]==1 ? 32\'h0007A120 : 32\'h1DCD6500) : (x[3]==1 ? 32\'h004C4B40 : 32\'h02FAF080);\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:164: Output port connection \'yshang\' expects 43 bits on the pin connection, but pin connection\'s VARREF \'yshang\' generates 29 bits.\n                                                                       : ... In instance main_con_new\ndiv_rill div(default_frq, frequency, yshang);\n                                     ^~~~~~\n%Error: Exiting due to 7 warning(s)\n'
module div_rill(
	input[28:0] a,
	input[13:0] b,
	
	output wire [42:0] yshang

	);
 
reg[28:0] tempa;
reg[13:0] tempb;
reg[42:0] temp_a;

 
integer i;
 
always @(a or b)
begin
    tempa <= a;
    tempb <= b;
end
 
always @(tempa or tempb) begin
    temp_a = {14'b00000000000000,tempa};

    for(i = 0;i < 29;i = i + 1) begin
            temp_a = {temp_a[41:0],1'b0};
            if(temp_a[42:29] >= tempb)
                temp_a = temp_a - {tempb,29'b00000000000000000000000000000} + 1'b1;
            else
				temp_a = temp_a;
        end


end

assign yshang = temp_a;
 
endmodule
module div_rill(
	input[28:0] a,
	input[13:0] b,
	
	output wire [42:0] yshang

	);

 
reg[28:0] tempa;
reg[13:0] tempb;
reg[42:0] temp_a;

 
integer i;
 
always @(a or b)
begin
    tempa <= a;
    tempb <= b;
end
 
always @(tempa or tempb) begin
    temp_a = {14'b00000000000000,tempa};

    for(i = 0;i < 29;i = i + 1) begin
            temp_a = {temp_a[41:0],1'b0};
            if(temp_a[42:29] >= tempb)
                temp_a = temp_a - {tempb,29'b00000000000000000000000000000} + 1'b1;
            else
				temp_a = temp_a;
        end


end

assign yshang = temp_a;
 
endmodule