data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v
None: at end of input
1: b'%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:3: Cannot find include file: define.h\n`include "define.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/define.h\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/define.h.v\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/define.h.sv\n             define.h\n             define.h.v\n             define.h.sv\n             obj_dir/define.h\n             obj_dir/define.h.v\n             obj_dir/define.h.sv\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:15: Define or directive not defined: \'`AND\'\n assign ALUctl[0]  = (zero & (funct==`AND)) | ALUop[0];                  \n                                     ^~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:15: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[0]  = (zero & (funct==`AND)) | ALUop[0];                  \n                                         ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:16: Define or directive not defined: \'`OR\'\n assign ALUctl[1]  = (zero & (funct==`OR)) | ALUop[1];                   \n                                     ^~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:16: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[1]  = (zero & (funct==`OR)) | ALUop[1];                   \n                                        ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:17: Define or directive not defined: \'`XOR\'\n assign ALUctl[2]  = (zero & (funct==`XOR)) | ALUop[2];                  \n                                     ^~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:17: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[2]  = (zero & (funct==`XOR)) | ALUop[2];                  \n                                         ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:18: Define or directive not defined: \'`NOR\'\n assign ALUctl[3]  = zero & (funct==`NOR);                               \n                                    ^~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:18: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[3]  = zero & (funct==`NOR);                               \n                                        ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:19: Define or directive not defined: \'`ADD\'\n assign ALUctl[4]  = (zero & (funct==`ADD|funct==`ADDU)) | ALUop[3];     \n                                     ^~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:19: Define or directive not defined: \'`ADDU\'\n assign ALUctl[4]  = (zero & (funct==`ADD|funct==`ADDU)) | ALUop[3];     \n                                                 ^~~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:19: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[4]  = (zero & (funct==`ADD|funct==`ADDU)) | ALUop[3];     \n                                                      ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:20: Define or directive not defined: \'`SUB\'\n assign ALUctl[5]  = (zero & (funct==`SUB|funct==`SUBU)) | ALUop[4];     \n                                     ^~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:20: Define or directive not defined: \'`SUBU\'\n assign ALUctl[5]  = (zero & (funct==`SUB|funct==`SUBU)) | ALUop[4];     \n                                                 ^~~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:20: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[5]  = (zero & (funct==`SUB|funct==`SUBU)) | ALUop[4];     \n                                                      ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:21: Define or directive not defined: \'`SLT\'\n assign ALUctl[6]  = (zero & (funct==`SLT)) | ALUop[5];                  \n                                     ^~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:21: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[6]  = (zero & (funct==`SLT)) | ALUop[5];                  \n                                         ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:22: Define or directive not defined: \'`SLL\'\n assign ALUctl[7]  = zero & (funct==`SLL);                               \n                                    ^~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:22: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[7]  = zero & (funct==`SLL);                               \n                                        ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:23: Define or directive not defined: \'`SRL\'\n assign ALUctl[8]  = zero & (funct==`SRL);                               \n                                    ^~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:23: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[8]  = zero & (funct==`SRL);                               \n                                        ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:24: Define or directive not defined: \'`SLLV\'\n assign ALUctl[9]  = zero & (funct==`SLLV);                              \n                                    ^~~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[9]  = zero & (funct==`SLLV);                              \n                                         ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:25: Define or directive not defined: \'`SRLV\'\n assign ALUctl[10] = zero & (funct==`SRLV);                              \n                                    ^~~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:25: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[10] = zero & (funct==`SRLV);                              \n                                         ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:26: Define or directive not defined: \'`SLTU\'\n assign ALUctl[11] = (zero & (funct==`SLTU)) | ALUop[7];                 \n                                     ^~~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:26: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[11] = (zero & (funct==`SLTU)) | ALUop[7];                 \n                                          ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:28: Define or directive not defined: \'`SRA\'\n assign ALUctl[13] = zero & (funct==`SRA);                               \n                                    ^~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:28: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[13] = zero & (funct==`SRA);                               \n                                        ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:29: Define or directive not defined: \'`SRAV\'\n assign ALUctl[14] = zero & (funct==`SRAV);                              \n                                    ^~~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/ALU_control.v:29: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign ALUctl[14] = zero & (funct==`SRAV);                              \n                                         ^\n%Error: Exiting due to 31 error(s)\n'
module ALU_control(
	input  [7:0]  ALUop,
	input  [5:0]  funct,
	output [14:0] ALUctl
	);
	
	wire zero;

	assign zero = ~|ALUop;

	assign ALUctl[0]  = (zero & (funct==`AND)) | ALUop[0];
	assign ALUctl[1]  = (zero & (funct==`OR)) | ALUop[1];
	assign ALUctl[2]  = (zero & (funct==`XOR)) | ALUop[2];
	assign ALUctl[3]  = zero & (funct==`NOR);
	assign ALUctl[4]  = (zero & (funct==`ADD|funct==`ADDU)) | ALUop[3];
	assign ALUctl[5]  = (zero & (funct==`SUB|funct==`SUBU)) | ALUop[4];
	assign ALUctl[6]  = (zero & (funct==`SLT)) | ALUop[5];
	assign ALUctl[7]  = zero & (funct==`SLL);
	assign ALUctl[8]  = zero & (funct==`SRL);
	assign ALUctl[9]  = zero & (funct==`SLLV);
	assign ALUctl[10] = zero & (funct==`SRLV);
	assign ALUctl[11] = (zero & (funct==`SLTU)) | ALUop[7];
	assign ALUctl[12] = ALUop[6];
	assign ALUctl[13] = zero & (funct==`SRA);
	assign ALUctl[14] = zero & (funct==`SRAV);

	

endmodule
module ALU_control(
	input  [7:0]  ALUop,
	input  [5:0]  funct,
	output [14:0] ALUctl
	);

	
	wire zero;

	assign zero = ~|ALUop;

	assign ALUctl[0]  = (zero & (funct==`AND)) | ALUop[0];
	assign ALUctl[1]  = (zero & (funct==`OR)) | ALUop[1];
	assign ALUctl[2]  = (zero & (funct==`XOR)) | ALUop[2];
	assign ALUctl[3]  = zero & (funct==`NOR);
	assign ALUctl[4]  = (zero & (funct==`ADD|funct==`ADDU)) | ALUop[3];
	assign ALUctl[5]  = (zero & (funct==`SUB|funct==`SUBU)) | ALUop[4];
	assign ALUctl[6]  = (zero & (funct==`SLT)) | ALUop[5];
	assign ALUctl[7]  = zero & (funct==`SLL);
	assign ALUctl[8]  = zero & (funct==`SRL);
	assign ALUctl[9]  = zero & (funct==`SLLV);
	assign ALUctl[10] = zero & (funct==`SRLV);
	assign ALUctl[11] = (zero & (funct==`SLTU)) | ALUop[7];
	assign ALUctl[12] = ALUop[6];
	assign ALUctl[13] = zero & (funct==`SRA);
	assign ALUctl[14] = zero & (funct==`SRAV);

	

endmodule