data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_shuffler.v
 line:47: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_shuffler.v:47: Unsupported: Ignoring delay on this delayed statement.\n#10000000 $stop;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_shuffler.v:50: Unsupported: Ignoring delay on this delayed statement.\n#(2*n) sel=~sel;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_shuffler.v:54: Unsupported: Ignoring delay on this delayed statement.\n#10000000 $stop;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_shuffler.v:57: Unsupported: Ignoring delay on this delayed statement.\n#n clk=~clk;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_shuffler.v:62: Unsupported: Ignoring delay on this delayed statement.\n#(2*n)\n^\n%Warning-STMTDLY: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_shuffler.v:65: Unsupported: Ignoring delay on this delayed statement.\n#(2*n)\n^\n%Error: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_shuffler.v:37: Cannot find file containing module: \'basic_shuffler\'\n basic_shuffler uut (\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219219909/3-parallel_Data_Shuffler,data/full_repos/permissive/219219909/basic_shuffler\n             data/full_repos/permissive/219219909/3-parallel_Data_Shuffler,data/full_repos/permissive/219219909/basic_shuffler.v\n             data/full_repos/permissive/219219909/3-parallel_Data_Shuffler,data/full_repos/permissive/219219909/basic_shuffler.sv\n             basic_shuffler\n             basic_shuffler.v\n             basic_shuffler.sv\n             obj_dir/basic_shuffler\n             obj_dir/basic_shuffler.v\n             obj_dir/basic_shuffler.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_shuffler;
parameter n=5;

	reg [31:0] a;
	reg [31:0] b;
	reg sel,clk;


	wire [31:0] a1;
	wire [31:0] b1;


	basic_shuffler uut (
		.a(a), 
		.b(b), 
		.sel(sel), 
		.clk(clk),
		.a1(a1), 
		.b1(b1)
	);
initial begin
      sel=0;
#10000000 $stop;
end
always begin
#(2*n) sel=~sel;
end
initial begin
      clk=0;
#10000000 $stop;
end
always begin
#n clk=~clk;
end
	initial begin
		a=32'h00000001;
b=32'h00000002;		
#(2*n)
a=32'h00000003;
b=32'h00000004;
#(2*n)
a=32'h00000005;
b=32'h00000006;
end
      
endmodule
module test_shuffler;

parameter n=5;

	reg [31:0] a;
	reg [31:0] b;
	reg sel,clk;


	wire [31:0] a1;
	wire [31:0] b1;


	basic_shuffler uut (
		.a(a), 
		.b(b), 
		.sel(sel), 
		.clk(clk),
		.a1(a1), 
		.b1(b1)
	);
initial begin
      sel=0;
#10000000 $stop;
end
always begin
#(2*n) sel=~sel;
end
initial begin
      clk=0;
#10000000 $stop;
end
always begin
#n clk=~clk;
end
	initial begin
		a=32'h00000001;
b=32'h00000002;		
#(2*n)
a=32'h00000003;
b=32'h00000004;
#(2*n)
a=32'h00000005;
b=32'h00000006;
end
      
endmodule