data/full_repos/permissive/197224897/Controller/clkDivider.v
data/verilator_xmls/262389cd-66a6-4fb5-b1c9-f8979173e5d4.xml
module clkDivider(inClk, globalReset, outClk);
   input inClk, globalReset;
	reg reset = 1;
	output reg outClk =1 ;
	reg [27:0] counter = 0;
	
	always @ (posedge inClk) begin
		if (globalReset == 1)
			begin
				reset   <= 1;
				counter <= 0;
				outClk  <= 1;
			end

		else if (reset == 1) 
		reset  <= 0;

		else if (counter == 4) 
			begin
				counter  <= 0;
				outClk   <= ~outClk;
			end 
		else 
			begin
				counter <= counter + 1;
			end
	end
endmodule
module clkDivider(inClk, globalReset, outClk);

   input inClk, globalReset;
	reg reset = 1;
	output reg outClk =1 ;
	reg [27:0] counter = 0;
	
	always @ (posedge inClk) begin
		if (globalReset == 1)
			begin
				reset   <= 1;
				counter <= 0;
				outClk  <= 1;
			end

		else if (reset == 1) 
		reset  <= 0;

		else if (counter == 4) 
			begin
				counter  <= 0;
				outClk   <= ~outClk;
			end 
		else 
			begin
				counter <= counter + 1;
			end
	end
endmodule