data/full_repos/permissive/109209652/verilog/fifo_deserial.v
 line:22: before: "<="
data/verilator_xmls/22c7a12f-95aa-4636-b173-3fd7a381fe37.xml
module fifo_deserial(
	input				clk,
	input				reset,
	input		[31:0]	data_in,
	input				fifo_empty,
	input				outfifo_full,
	output				fifo_rdreq,

	output	reg	[9:0]	img_in_x,
	output	reg	[9:0]	img_in_y,
	output	reg	[7:0]	img_in_left,	
	output	reg	[7:0]	img_in_right,
	output				img_is_val,

	input		[9:0]	debug_in,
	output		[5:0]	debug_out
);


	assign fifo_rdreq = ~fifo_empty & ~outfifo_full;

	reg					in_is_val;
	always @(posedge clk) begin
		if (fifo_rdreq) begin
			in_is_val <= 1;
		end
		else begin
			in_is_val <= 0;
		end
	end


	reg					coord_is_val;
	reg					pix_is_val;
	reg					read_next_packet;
	always @(posedge clk) begin
		if (reset) begin
			coord_is_val <= 0;
			pix_is_val <= 0;
			read_next_packet <= 1;
		end
		else begin
			if (read_next_packet) begin





				pix_is_val <= 0;
				if (!data_in[31] && in_is_val) begin

					img_in_x <= data_in[9:0];
					img_in_y <= data_in[25:16];
					coord_is_val <= 1;



					read_next_packet <= 0;
				end
				else begin
					coord_is_val <= 0;
					read_next_packet <= 1;
				end
			end
			else begin

				if (data_in[31] && in_is_val) begin

					img_in_left <= data_in[15:8];
					img_in_right <= data_in[7:0];
					pix_is_val <= 1;



					read_next_packet <= 1;
				end
				else begin
					pix_is_val <= 0;
					read_next_packet <= 0;
				end
			end
		end
	end



	assign img_is_val = coord_is_val & pix_is_val;

	assign debug_out[0] = pix_is_val;
	assign debug_out[1] = coord_is_val;
	assign debug_out[2] = fifo_rdreq;
	assign debug_out[3] = in_is_val;
	assign debug_out[4] = read_next_packet;
	assign debug_out[5] = data_in[31];
endmodule
module fifo_deserial(
	input				clk,
	input				reset,
	input		[31:0]	data_in,
	input				fifo_empty,
	input				outfifo_full,
	output				fifo_rdreq,

	output	reg	[9:0]	img_in_x,
	output	reg	[9:0]	img_in_y,
	output	reg	[7:0]	img_in_left,	
	output	reg	[7:0]	img_in_right,
	output				img_is_val,

	input		[9:0]	debug_in,
	output		[5:0]	debug_out
);



	assign fifo_rdreq = ~fifo_empty & ~outfifo_full;

	reg					in_is_val;
	always @(posedge clk) begin
		if (fifo_rdreq) begin
			in_is_val <= 1;
		end
		else begin
			in_is_val <= 0;
		end
	end


	reg					coord_is_val;
	reg					pix_is_val;
	reg					read_next_packet;
	always @(posedge clk) begin
		if (reset) begin
			coord_is_val <= 0;
			pix_is_val <= 0;
			read_next_packet <= 1;
		end
		else begin
			if (read_next_packet) begin





				pix_is_val <= 0;
				if (!data_in[31] && in_is_val) begin

					img_in_x <= data_in[9:0];
					img_in_y <= data_in[25:16];
					coord_is_val <= 1;



					read_next_packet <= 0;
				end
				else begin
					coord_is_val <= 0;
					read_next_packet <= 1;
				end
			end
			else begin

				if (data_in[31] && in_is_val) begin

					img_in_left <= data_in[15:8];
					img_in_right <= data_in[7:0];
					pix_is_val <= 1;



					read_next_packet <= 1;
				end
				else begin
					pix_is_val <= 0;
					read_next_packet <= 0;
				end
			end
		end
	end



	assign img_is_val = coord_is_val & pix_is_val;

	assign debug_out[0] = pix_is_val;
	assign debug_out[1] = coord_is_val;
	assign debug_out[2] = fifo_rdreq;
	assign debug_out[3] = in_is_val;
	assign debug_out[4] = read_next_packet;
	assign debug_out[5] = data_in[31];
endmodule