data/full_repos/permissive/161329976/split_data.v
data/verilator_xmls/8eec04bc-3bad-46a7-9419-653e8c6e646d.xml
module split_data #(

    parameter AXIS_TDATA_WIDTH = 32)(

    input   [AXIS_TDATA_WIDTH-1:0]      S_AXIS_tdata,
    input                               S_AXIS_tvalid,
    
    output  [AXIS_TDATA_WIDTH/2-1:0]    M_AXIS_OUT1_tdata,
    output                              M_AXIS_OUT1_tvalid,
    
    output  [AXIS_TDATA_WIDTH/2-1:0]    M_AXIS_OUT2_tdata,
    output                              M_AXIS_OUT2_tvalid
    );
    
    assign M_AXIS_OUT1_tdata = S_AXIS_tdata[AXIS_TDATA_WIDTH/2-1:0];
    assign M_AXIS_OUT2_tdata = S_AXIS_tdata[AXIS_TDATA_WIDTH-1:AXIS_TDATA_WIDTH/2];
    assign M_AXIS_OUT1_tvalid = S_AXIS_tvalid;
    assign M_AXIS_OUT2_tvalid = S_AXIS_tvalid;
    
endmodule
module split_data #(

    parameter AXIS_TDATA_WIDTH = 32)(

    input   [AXIS_TDATA_WIDTH-1:0]      S_AXIS_tdata,
    input                               S_AXIS_tvalid,
    
    output  [AXIS_TDATA_WIDTH/2-1:0]    M_AXIS_OUT1_tdata,
    output                              M_AXIS_OUT1_tvalid,
    
    output  [AXIS_TDATA_WIDTH/2-1:0]    M_AXIS_OUT2_tdata,
    output                              M_AXIS_OUT2_tvalid
    );

    
    assign M_AXIS_OUT1_tdata = S_AXIS_tdata[AXIS_TDATA_WIDTH/2-1:0];
    assign M_AXIS_OUT2_tdata = S_AXIS_tdata[AXIS_TDATA_WIDTH-1:AXIS_TDATA_WIDTH/2];
    assign M_AXIS_OUT1_tvalid = S_AXIS_tvalid;
    assign M_AXIS_OUT2_tvalid = S_AXIS_tvalid;
    
endmodule