data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Error: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:59: Unsupported or unknown PLI call: $shm_open\n $shm_open("demux2to4.shm");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/20688874/andy/tb/demux2to4tb.v:60: Unsupported or unknown PLI call: $shm_probe\n $shm_probe("AC"); \n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module demux2to4tb;
    reg 	in0, in1, in2, in3, d0, d1;
    wire 	out;

    demux demux1 (in0, in1, in2, in3, d0, d1, out);


    initial
        begin
            in0=1'b0; in1=1'b1; in2=1'b1; in3=1'b1; 
            d0=1'b0; d1=1'b0; 
            #10;
            d0=1'b1; d1=1'b0;
            #10;
            d0=1'b0; d1=1'b1;
            #10;
            d0=1'b1; d1=1'b1;
            #10;

            in0=1'b1; in1=1'b0; in2=1'b1; in3=1'b1; 
            d0=1'b0; d1=1'b0; 
            #10;
            d0=1'b1; d1=1'b0;
            #10;
            d0=1'b0; d1=1'b1;
            #10;
            d0=1'b1; d1=1'b1;
            #10;

            in0=1'b1; in1=1'b1; in2=1'b0; in3=1'b1; 
            d0=1'b0; d1=1'b0; 
            #10;
            d0=1'b1; d1=1'b0;
            #10;
            d0=1'b0; d1=1'b1;
            #10;
            d0=1'b1; d1=1'b1;
            #10;

            in0=1'b1; in1=1'b1; in2=1'b1; in3=1'b0; 
            d0=1'b0; d1=1'b0; 
            #10;
            d0=1'b1; d1=1'b0;
            #10;
            d0=1'b0; d1=1'b1;
            #10;
            d0=1'b1; d1=1'b1;
            #10;


        end
        
   initial
     begin
	$shm_open("demux2to4.shm");
	$shm_probe("AC");	
     end
endmodule
module demux2to4tb;

    reg 	in0, in1, in2, in3, d0, d1;
    wire 	out;

    demux demux1 (in0, in1, in2, in3, d0, d1, out);


    initial
        begin
            in0=1'b0; in1=1'b1; in2=1'b1; in3=1'b1; 
            d0=1'b0; d1=1'b0; 
            #10;
            d0=1'b1; d1=1'b0;
            #10;
            d0=1'b0; d1=1'b1;
            #10;
            d0=1'b1; d1=1'b1;
            #10;

            in0=1'b1; in1=1'b0; in2=1'b1; in3=1'b1; 
            d0=1'b0; d1=1'b0; 
            #10;
            d0=1'b1; d1=1'b0;
            #10;
            d0=1'b0; d1=1'b1;
            #10;
            d0=1'b1; d1=1'b1;
            #10;

            in0=1'b1; in1=1'b1; in2=1'b0; in3=1'b1; 
            d0=1'b0; d1=1'b0; 
            #10;
            d0=1'b1; d1=1'b0;
            #10;
            d0=1'b0; d1=1'b1;
            #10;
            d0=1'b1; d1=1'b1;
            #10;

            in0=1'b1; in1=1'b1; in2=1'b1; in3=1'b0; 
            d0=1'b0; d1=1'b0; 
            #10;
            d0=1'b1; d1=1'b0;
            #10;
            d0=1'b0; d1=1'b1;
            #10;
            d0=1'b1; d1=1'b1;
            #10;


        end
        
   initial
     begin
	$shm_open("demux2to4.shm");
	$shm_probe("AC");	
     end
endmodule