data/full_repos/permissive/123364505/risc32_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123364505/risc32_test.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123364505/risc32_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #3000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123364505/risc32_test.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #(T/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123364505/risc32_test.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #(T/2);\n  ^\n%Error: data/full_repos/permissive/123364505/risc32_test.v:54: Cannot find file containing module: \'risc32_core\'\n risc32_core uut (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123364505,data/full_repos/permissive/123364505/risc32_core\n             data/full_repos/permissive/123364505,data/full_repos/permissive/123364505/risc32_core.v\n             data/full_repos/permissive/123364505,data/full_repos/permissive/123364505/risc32_core.sv\n             risc32_core\n             risc32_core.v\n             risc32_core.sv\n             obj_dir/risc32_core\n             obj_dir/risc32_core.v\n             obj_dir/risc32_core.sv\n%Error: data/full_repos/permissive/123364505/risc32_test.v:68: Cannot find file containing module: \'risc_rom\'\n risc_rom rom(.address(address), .data(instruction));\n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module risc32_test;


	reg clk;
	reg reset;
	reg interrupt;
	wire interrupt_ack;
	reg [7:0] inport;
	wire [ 31 : 0 ] instruction;


	wire [31:0] outport;
	wire halt;
	wire [ 31 : 0 ] address;
	

	localparam T = 20;


	risc32_core uut (
		.clk(clk), 
		.reset(reset), 
		.interrupt(interrupt),
		.interrupt_ack(interrupt_ack),
		.address(address),
		.instruction(instruction),
		.inport(inport), 
		.outport(outport), 
		.halt(halt)
	);



	risc_rom rom(.address(address), .data(instruction));
	
	initial begin

		clk = 0;
		reset = 1;
		interrupt = 0;
		inport = 0;


		#100;
        

		reset = 0;

		#3000;
		reset = 1;
		$stop;
	end
  

	always
	begin
		clk = 1'b1;
		#(T/2);
		
		clk = 1'b0;
		#(T/2);
	end
	
endmodule
module risc32_test;



	reg clk;
	reg reset;
	reg interrupt;
	wire interrupt_ack;
	reg [7:0] inport;
	wire [ 31 : 0 ] instruction;


	wire [31:0] outport;
	wire halt;
	wire [ 31 : 0 ] address;
	

	localparam T = 20;


	risc32_core uut (
		.clk(clk), 
		.reset(reset), 
		.interrupt(interrupt),
		.interrupt_ack(interrupt_ack),
		.address(address),
		.instruction(instruction),
		.inport(inport), 
		.outport(outport), 
		.halt(halt)
	);



	risc_rom rom(.address(address), .data(instruction));
	
	initial begin

		clk = 0;
		reset = 1;
		interrupt = 0;
		inport = 0;


		#100;
        

		reset = 0;

		#3000;
		reset = 1;
		$stop;
	end
  

	always
	begin
		clk = 1'b1;
		#(T/2);
		
		clk = 1'b0;
		#(T/2);
	end
	
endmodule