data/full_repos/permissive/195227969/work/code/simcode/m_ice40sim_SRAM.v
None: at end of input
1: b'%Error: data/full_repos/permissive/195227969/work/code/simcode/m_ice40sim_SRAM.v:11: Cannot find include file: ../../generated/midgetv_ucodeoptions.hv\n`include "../../generated/midgetv_ucodeoptions.hv" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/195227969/work/code/simcode,data/full_repos/permissive/195227969/../../generated/midgetv_ucodeoptions.hv\n             data/full_repos/permissive/195227969/work/code/simcode,data/full_repos/permissive/195227969/../../generated/midgetv_ucodeoptions.hv.v\n             data/full_repos/permissive/195227969/work/code/simcode,data/full_repos/permissive/195227969/../../generated/midgetv_ucodeoptions.hv.sv\n             ../../generated/midgetv_ucodeoptions.hv\n             ../../generated/midgetv_ucodeoptions.hv.v\n             ../../generated/midgetv_ucodeoptions.hv.sv\n             obj_dir/../../generated/midgetv_ucodeoptions.hv\n             obj_dir/../../generated/midgetv_ucodeoptions.hv.v\n             obj_dir/../../generated/midgetv_ucodeoptions.hv.sv\n%Error: Exiting due to 1 error(s)\n'
module m_ice40sim_SRAM
  # ( parameter
      SRAMADRWIDTH       = 16,  
      SIMEBRAWIDTH       = 10
      )
   (
    input CLK_I,
    input RST_I,
    input meip
    );
   
   
   m_ice40sim_EBRonly
     #(
       .SRAMADRWIDTH       ( SRAMADRWIDTH        ),
       .SIMEBRAWIDTH       ( SIMEBRAWIDTH        )
       )
   inst_ice40sim_EBRonly
     (

      .CLK_I                            (CLK_I),
      .RST_I                            (RST_I),
      .meip                             (meip));
endmodule
module m_ice40sim_SRAM
  # ( parameter
      SRAMADRWIDTH       = 16,  
      SIMEBRAWIDTH       = 10
      )
   (
    input CLK_I,
    input RST_I,
    input meip
    );

   
   
   m_ice40sim_EBRonly
     #(
       .SRAMADRWIDTH       ( SRAMADRWIDTH        ),
       .SIMEBRAWIDTH       ( SIMEBRAWIDTH        )
       )
   inst_ice40sim_EBRonly
     (

      .CLK_I                            (CLK_I),
      .RST_I                            (RST_I),
      .meip                             (meip));
endmodule