data/full_repos/permissive/174369527/simpleCPU/src/reset_sync.v
 line:10: before: "="
data/verilator_xmls/607b0a3b-b814-4b15-8f4e-4b370a5833e0.xml
module reset_sync
	(
	 input wire [0:0] i_clk,
	 input wire [0:0] i_rst,
	


	 output reg [0:0] o_rst_1 = 1'b0,

	 output reg [0:0] o_rst_2 = 1'b0
	);


	reg [1:0] r_rst = 2'b00;

	wire w_rst_1;
	reg r_rst_1 = 1'b0;
	
	always @ (posedge i_clk)
	begin
		r_rst[0] <= i_rst;
		r_rst[1] <= r_rst[0];
	end

	assign w_rst_1 = (o_rst_1 & (i_rst | r_rst[1] | r_rst[0])) | (i_rst & r_rst[0] & r_rst[1]);

	always @ (posedge i_clk)
	begin
		o_rst_1 <= w_rst_1;
		r_rst_1 <= o_rst_1;
		o_rst_2 <= r_rst_1;
	end

endmodule
module reset_sync
	(
	 input wire [0:0] i_clk,
	 input wire [0:0] i_rst,
	


	 output reg [0:0] o_rst_1 = 1'b0,

	 output reg [0:0] o_rst_2 = 1'b0
	);



	reg [1:0] r_rst = 2'b00;

	wire w_rst_1;
	reg r_rst_1 = 1'b0;
	
	always @ (posedge i_clk)
	begin
		r_rst[0] <= i_rst;
		r_rst[1] <= r_rst[0];
	end

	assign w_rst_1 = (o_rst_1 & (i_rst | r_rst[1] | r_rst[0])) | (i_rst & r_rst[0] & r_rst[1]);

	always @ (posedge i_clk)
	begin
		o_rst_1 <= w_rst_1;
		r_rst_1 <= o_rst_1;
		o_rst_2 <= r_rst_1;
	end

endmodule