data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:3: Cannot find include file: simdrv_defs.svh\n`include "simdrv_defs.svh" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader,data/full_repos/permissive/161356276/simdrv_defs.svh\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader,data/full_repos/permissive/161356276/simdrv_defs.svh.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader,data/full_repos/permissive/161356276/simdrv_defs.svh.sv\n             simdrv_defs.svh\n             simdrv_defs.svh.v\n             simdrv_defs.svh.sv\n             obj_dir/simdrv_defs.svh\n             obj_dir/simdrv_defs.svh.v\n             obj_dir/simdrv_defs.svh.sv\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:4: Cannot find include file: if_wb_master.svh\n`include "if_wb_master.svh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:6: Cannot find include file: regs/xloader_regs.vh\n`include "regs/xloader_regs.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:13: Unsupported: Ignoring delay on this delayed statement.\n     #5ns clk_sys <= ~clk_sys;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:16: syntax error, unexpected \'@\'\n      repeat(5) @(posedge clk_sys);\n                ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:71: syntax error, unexpected IDENTIFIER, expecting \')\'\n   task load_bitstream(CBusAccessor acc, string filename);\n                                    ^~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:76: Define or directive not defined: \'`ADDR_XLDR_CSR\'\n      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_SWRST );\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_SWRST );\n                               ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:76: Define or directive not defined: \'`XLDR_CSR_SWRST\'\n      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_SWRST );\n                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:77: Define or directive not defined: \'`ADDR_XLDR_CSR\'\n      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_START | `XLDR_CSR_MSBF);\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:77: syntax error, unexpected \'(\', expecting IDENTIFIER\n      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_START | `XLDR_CSR_MSBF);\n                               ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:77: Define or directive not defined: \'`XLDR_CSR_START\'\n      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_START | `XLDR_CSR_MSBF);\n                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:77: Define or directive not defined: \'`XLDR_CSR_MSBF\'\n      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_START | `XLDR_CSR_MSBF);\n                                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:83: Define or directive not defined: \'`ADDR_XLDR_FIFO_CSR\'\n           acc.read(`ADDR_XLDR_FIFO_CSR, rval);\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:83: syntax error, unexpected \'(\', expecting IDENTIFIER\n           acc.read(`ADDR_XLDR_FIFO_CSR, rval);\n                                       ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:85: Define or directive not defined: \'`XLDR_FIFO_CSR_FULL\'\n           if(!(rval&`XLDR_FIFO_CSR_FULL)) begin\n                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:85: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n           if(!(rval&`XLDR_FIFO_CSR_FULL)) begin\n                                        ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:89: syntax error, unexpected \'=\', expecting IDENTIFIER\n              n  = $fread(word, f);\n                 ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:90: Define or directive not defined: \'`ADDR_XLDR_FIFO_R0\'\n              acc.write(`ADDR_XLDR_FIFO_R0, (n - 1) | ($feof(f) ? `XLDR_FIFO_R0_XLAST : 0));\n                        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:90: syntax error, unexpected \'(\', expecting IDENTIFIER\n              acc.write(`ADDR_XLDR_FIFO_R0, (n - 1) | ($feof(f) ? `XLDR_FIFO_R0_XLAST : 0));\n                                          ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:90: Define or directive not defined: \'`XLDR_FIFO_R0_XLAST\'\n              acc.write(`ADDR_XLDR_FIFO_R0, (n - 1) | ($feof(f) ? `XLDR_FIFO_R0_XLAST : 0));\n                                                                  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:91: Define or directive not defined: \'`ADDR_XLDR_FIFO_R1\'\n              acc.write(`ADDR_XLDR_FIFO_R1, word);\n                        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:91: syntax error, unexpected \'(\', expecting IDENTIFIER\n              acc.write(`ADDR_XLDR_FIFO_R1, word);\n                                          ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:98: Define or directive not defined: \'`ADDR_XLDR_CSR\'\n         acc.read( `ADDR_XLDR_CSR, csr);\n                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:99: Define or directive not defined: \'`XLDR_CSR_DONE\'\n         if(csr & `XLDR_CSR_DONE) begin\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:99: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n         if(csr & `XLDR_CSR_DONE) begin\n                                ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:100: Define or directive not defined: \'`XLDR_CSR_ERROR\'\n            $display("Bitstream loaded, status: %s", (csr & `XLDR_CSR_ERROR ? "ERROR" : "OK"));\n                                                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_xilinx_fpga_loader/main.sv:111: syntax error, unexpected \'#\'\n      #1000ns;\n      ^\n%Error: Cannot continue\n'
module main;

   reg clk_sys=1, rst_n=0;

   always
     #5ns clk_sys <= ~clk_sys;

   initial begin 
      repeat(5) @(posedge clk_sys);
      rst_n <= 1;
   end
   

   IWishboneMaster #(32, 32) U_WB
     (
      .clk_i(clk_sys),
      .rst_n_i(rst_n)
      );


   wire cclk, din, program_b, init_b, done, suspend;
   wire [1:0] m;
   
   wb_xilinx_fpga_loader DUT 
     (
      .clk_sys_i (clk_sys),
      .rst_n_i   (rst_n),

      .boot_en_i(1'b1),
      
      .wb_adr_i (U_WB.master.adr),
      .wb_dat_i (U_WB.master.dat_o),
      .wb_dat_o (U_WB.master.dat_i),
      .wb_cyc_i (U_WB.master.cyc),
      .wb_stb_i (U_WB.master.stb),
      .wb_we_i  (U_WB.master.we),
      .wb_ack_o (U_WB.master.ack),
      .wb_sel_i (U_WB.master.sel),

      .xlx_cclk_o      (cclk),
      .xlx_din_o       (din),
      .xlx_program_b_o (program_b),
      .xlx_init_b_i     (init_b),
      .xlx_done_i       (done),
      .xlx_suspend_o (suspend),
     
      .xlx_m_o (m)
      );
   
   
   SIM_CONFIG_S6_SERIAL2
  #(
    .DEVICE_ID(32'h34000093)
    ) U_serial_sim 
    (
     .DONE(done),
     .CCLK(cclk),
     .DIN(din),
     .INITB(init_b), 
     .M(m),
     .PROGB(program_b)
     );

   task load_bitstream(CBusAccessor acc, string filename);
      int f,i;
      uint64_t csr;
      
     
      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_SWRST );
      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_START | `XLDR_CSR_MSBF);
      f  = $fopen(filename, "r");
      
      while(!$feof(f))
        begin
           uint64_t rval;
           acc.read(`ADDR_XLDR_FIFO_CSR, rval);
           
           if(!(rval&`XLDR_FIFO_CSR_FULL)) begin
              int n;
              bit [31:0] word;
              
              n  = $fread(word, f);
              acc.write(`ADDR_XLDR_FIFO_R0, (n - 1) | ($feof(f) ? `XLDR_FIFO_R0_XLAST : 0));
              acc.write(`ADDR_XLDR_FIFO_R1, word);
              end
        end

      $fclose(f);

      while(1) begin
         acc.read( `ADDR_XLDR_CSR, csr);
         if(csr & `XLDR_CSR_DONE) begin
            $display("Bitstream loaded, status: %s", (csr & `XLDR_CSR_ERROR ? "ERROR" : "OK"));
            break;
         end
      end
   endtask
   
   
   initial begin
      CBusAccessor acc;
      int i;
      
      #1000ns;
      acc = U_WB.get_accessor();



      load_bitstream(acc, "sample_bitstream/crc_gen.bin");
      $stop;
     
   end
   
endmodule
module main;


   reg clk_sys=1, rst_n=0;

   always
     #5ns clk_sys <= ~clk_sys;

   initial begin 
      repeat(5) @(posedge clk_sys);
      rst_n <= 1;
   end
   

   IWishboneMaster #(32, 32) U_WB
     (
      .clk_i(clk_sys),
      .rst_n_i(rst_n)
      );


   wire cclk, din, program_b, init_b, done, suspend;
   wire [1:0] m;
   
   wb_xilinx_fpga_loader DUT 
     (
      .clk_sys_i (clk_sys),
      .rst_n_i   (rst_n),

      .boot_en_i(1'b1),
      
      .wb_adr_i (U_WB.master.adr),
      .wb_dat_i (U_WB.master.dat_o),
      .wb_dat_o (U_WB.master.dat_i),
      .wb_cyc_i (U_WB.master.cyc),
      .wb_stb_i (U_WB.master.stb),
      .wb_we_i  (U_WB.master.we),
      .wb_ack_o (U_WB.master.ack),
      .wb_sel_i (U_WB.master.sel),

      .xlx_cclk_o      (cclk),
      .xlx_din_o       (din),
      .xlx_program_b_o (program_b),
      .xlx_init_b_i     (init_b),
      .xlx_done_i       (done),
      .xlx_suspend_o (suspend),
     
      .xlx_m_o (m)
      );
   
   
   SIM_CONFIG_S6_SERIAL2
  #(
    .DEVICE_ID(32'h34000093)
    ) U_serial_sim 
    (
     .DONE(done),
     .CCLK(cclk),
     .DIN(din),
     .INITB(init_b), 
     .M(m),
     .PROGB(program_b)
     );

   task load_bitstream(CBusAccessor acc, string filename);
      int f,i;
      uint64_t csr;
      
     
      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_SWRST );
      acc.write( `ADDR_XLDR_CSR, `XLDR_CSR_START | `XLDR_CSR_MSBF);
      f  = $fopen(filename, "r");
      
      while(!$feof(f))
        begin
           uint64_t rval;
           acc.read(`ADDR_XLDR_FIFO_CSR, rval);
           
           if(!(rval&`XLDR_FIFO_CSR_FULL)) begin
              int n;
              bit [31:0] word;
              
              n  = $fread(word, f);
              acc.write(`ADDR_XLDR_FIFO_R0, (n - 1) | ($feof(f) ? `XLDR_FIFO_R0_XLAST : 0));
              acc.write(`ADDR_XLDR_FIFO_R1, word);
              end
        end

      $fclose(f);

      while(1) begin
         acc.read( `ADDR_XLDR_CSR, csr);
         if(csr & `XLDR_CSR_DONE) begin
            $display("Bitstream loaded, status: %s", (csr & `XLDR_CSR_ERROR ? "ERROR" : "OK"));
            break;
         end
      end
   endtask
   
   
   initial begin
      CBusAccessor acc;
      int i;
      
      #1000ns;
      acc = U_WB.get_accessor();



      load_bitstream(acc, "sample_bitstream/crc_gen.bin");
      $stop;
     
   end
   
endmodule