data/full_repos/permissive/156129873/verilog/id_ex.v
1: b'%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:38: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable || pause == `Enable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:38: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n        if (rst == `RstEnable || pause == `Enable) begin\n                              ^~\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:38: Define or directive not defined: \'`Enable\'\n        if (rst == `RstEnable || pause == `Enable) begin\n                                          ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:41: Define or directive not defined: \'`ZERO\'\n                operand1_o <= `ZERO;\n                              ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:42: Define or directive not defined: \'`ZERO\'\n                operand2_o <= `ZERO;\n                              ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                operand2_o <= `ZERO;\n                                   ^\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:43: Define or directive not defined: \'`ALU_NOP_OP\'\n                aluOp_o <= `ALU_NOP_OP;\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                aluOp_o <= `ALU_NOP_OP;\n                                      ^\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:46: Define or directive not defined: \'`MEM_NOP_OP\'\n                memOp_o <= `MEM_NOP_OP;\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                memOp_o <= `MEM_NOP_OP;\n                                      ^\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:49: Define or directive not defined: \'`Disable\'\n                writeReg_o <= `Disable;\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                writeReg_o <= `Disable;\n                                      ^\n%Error: data/full_repos/permissive/156129873/verilog/id_ex.v:51: syntax error, unexpected else\n        end else begin\n            ^~~~\n%Error: Cannot continue\n'
module id_ex(
    input wire clk,
    input wire rst,
    input wire pause,


    

    input wire[15:0] operand1_i,
    input wire[15:0] operand2_i,
    input wire[4:0] aluOp_i,


    input wire[1:0] memOp_i,


    input wire writeReg_i,
    input wire[3:0] writeRegAddr_i,
   

    

    output reg[15:0] operand1_o,
    output reg[15:0] operand2_o,
    output reg[4:0] aluOp_o,


    output reg[1:0] memOp_o,


    output reg writeReg_o,
    output reg[3:0] writeRegAddr_o
    );

    always @(posedge clk) begin
        if (rst == `RstEnable || pause == `Enable) begin
        

                operand1_o <= `ZERO;
                operand2_o <= `ZERO;
                aluOp_o <= `ALU_NOP_OP;
                

                memOp_o <= `MEM_NOP_OP;


                writeReg_o <= `Disable;
                writeRegAddr_o <= 5'h0;
        end else begin
                

                operand1_o <= operand1_i;
                operand2_o <= operand2_i;
                aluOp_o <= aluOp_i;
                

                memOp_o <= memOp_i;


                writeReg_o <= writeReg_i;
                writeRegAddr_o <= writeRegAddr_i;
        end
    end

endmodule
module id_ex(
    input wire clk,
    input wire rst,
    input wire pause,


    

    input wire[15:0] operand1_i,
    input wire[15:0] operand2_i,
    input wire[4:0] aluOp_i,


    input wire[1:0] memOp_i,


    input wire writeReg_i,
    input wire[3:0] writeRegAddr_i,
   

    

    output reg[15:0] operand1_o,
    output reg[15:0] operand2_o,
    output reg[4:0] aluOp_o,


    output reg[1:0] memOp_o,


    output reg writeReg_o,
    output reg[3:0] writeRegAddr_o
    );


    always @(posedge clk) begin
        if (rst == `RstEnable || pause == `Enable) begin
        

                operand1_o <= `ZERO;
                operand2_o <= `ZERO;
                aluOp_o <= `ALU_NOP_OP;
                

                memOp_o <= `MEM_NOP_OP;


                writeReg_o <= `Disable;
                writeRegAddr_o <= 5'h0;
        end else begin
                

                operand1_o <= operand1_i;
                operand2_o <= operand2_i;
                aluOp_o <= aluOp_i;
                

                memOp_o <= memOp_i;


                writeReg_o <= writeReg_i;
                writeRegAddr_o <= writeRegAddr_i;
        end
    end

endmodule