data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/memory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/memory.v:21: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'addra\' generates 6 bits.\n                                                                                     : ... In instance mem\n            addr_reg <= addra;\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mem(addra, clka, dina, douta, ena, wea);
	
	input clka, ena, wea;
	input [5:0] addra;
	input [31:0] dina;
	output [31:0] douta;

	reg [31:0] mem[0:63];
	reg [31:0] addr_reg;
	
	assign douta = mem[addr_reg];
	
	always @(posedge clka)
	begin
		if(wea)		
            mem[addra] <= dina;
		
		if(ena)	
            addr_reg <= addra;
	end

endmodule
module mem(addra, clka, dina, douta, ena, wea);

	
	input clka, ena, wea;
	input [5:0] addra;
	input [31:0] dina;
	output [31:0] douta;

	reg [31:0] mem[0:63];
	reg [31:0] addr_reg;
	
	assign douta = mem[addr_reg];
	
	always @(posedge clka)
	begin
		if(wea)		
            mem[addra] <= dina;
		
		if(ena)	
            addr_reg <= addra;
	end

endmodule