data/full_repos/permissive/197356760/UpDownCounter/seven_seg.v
data/verilator_xmls/ca8198b4-e481-4535-9768-60ae7f081655.xml
module seven_seg(in,out);
input [3:0] in;
output reg [6:0] out;

always@(in)begin
	case(in)
	0: out=~7'b0111111;
	1: out=~7'b0000110;
	2: out=~7'b1011011;
	3: out=~7'b1001111;
	4:	out=~7'b1100110;
	5:	out=~7'b1101101;
	6:	out=~7'b1111101;
	7:	out=~7'b0000111;
	default:
		out=~7'b0000000;
	endcase
end
endmodule
module seven_seg(in,out);

input [3:0] in;
output reg [6:0] out;

always@(in)begin
	case(in)
	0: out=~7'b0111111;
	1: out=~7'b0000110;
	2: out=~7'b1011011;
	3: out=~7'b1001111;
	4:	out=~7'b1100110;
	5:	out=~7'b1101101;
	6:	out=~7'b1111101;
	7:	out=~7'b0000111;
	default:
		out=~7'b0000000;
	endcase
end
endmodule