data/full_repos/permissive/211316121/lab7_1_nexys4/Traffic.v
data/verilator_xmls/ca577149-9261-4fa3-876c-03fa47d393ac.xml
module clkdiv(
input clk,
input reset,
output clk5,
output clk10
);

    reg [5:0] value;
    always@(posedge clk,posedge reset)
        if(reset) value<=0;
        else if(value<10) value<=value+1;
             else              value<=10;
             
    assign clk5 = (value>=4);
    assign clk10 = (value>=9);
endmodule
module clkdiv(
input clk,
input reset,
output clk5,
output clk10
);


    reg [5:0] value;
    always@(posedge clk,posedge reset)
        if(reset) value<=0;
        else if(value<10) value<=value+1;
             else              value<=10;
             
    assign clk5 = (value>=4);
    assign clk10 = (value>=9);
endmodule