data/full_repos/permissive/110151336/lab_02/src/04_d_flip_flop/d_flip_flop.v
data/verilator_xmls/d4daeb67-097c-4ad0-b56a-1ef403c24212.xml
module d_flip_flop
(
    input   clk,
    input   d,
    output  reg q
);

    always @ (posedge clk)
        q <= d;
 
endmodule
module d_flip_flop
(
    input   clk,
    input   d,
    output  reg q
);


    always @ (posedge clk)
        q <= d;
 
endmodule