data/full_repos/permissive/211878730/atlys/practice/two_four_decoder.v
data/verilator_xmls/24056f78-76e8-4521-b427-3ac6621f66b2.xml
module two_four_decoder(
	input  wire [1:0] data,
	output reg [3:0] y
    );

	always @(*) begin
		case (data)
			2'b00: y = 4'b0001;
			2'b01: y = 4'b0010;
			2'b10: y = 4'b0100;
			2'b11: y = 4'b1000;
		endcase
	end
endmodule
module two_four_decoder(
	input  wire [1:0] data,
	output reg [3:0] y
    );


	always @(*) begin
		case (data)
			2'b00: y = 4'b0001;
			2'b01: y = 4'b0010;
			2'b10: y = 4'b0100;
			2'b11: y = 4'b1000;
		endcase
	end
endmodule