data/full_repos/permissive/189834092/src/pl/count_data_gen.v
 line:32: before: "="
data/verilator_xmls/33460698-4e47-45f4-8fbf-8eb535b4c159.xml
module count_data_gen#(
        parameter integer C_M_AXIS_DATA_WIDTH = 32
    )(

        input wire                              ACLK,
        input wire                              ARESETN,

        input wire                              sample_clk,
        input wire                              enable,               

        output reg [C_M_AXIS_DATA_WIDTH-1:0]    sample_data = 'd0,
        output reg                              data_valid = 1'b0
    );
    
    reg trigger_sample_write = 1'b1;
    
always @(posedge ACLK) begin

    if(~ARESETN) begin
        sample_data <= 'd0;
        data_valid <= 1'b0;
        trigger_sample_write <= 1'b1; 
    end
    else begin

        if(data_valid) begin
            data_valid <= 1'b0;
        end

        if(enable) begin



            if(sample_clk && trigger_sample_write) begin
                sample_data <= sample_data + 'd1;
                data_valid <= 1'b1;

                trigger_sample_write <= 1'b0;
            end
            else if(~sample_clk) begin


                trigger_sample_write <= 1'b1;
            end
        end
    end
end
endmodule
module count_data_gen#(
        parameter integer C_M_AXIS_DATA_WIDTH = 32
    )(

        input wire                              ACLK,
        input wire                              ARESETN,

        input wire                              sample_clk,
        input wire                              enable,               

        output reg [C_M_AXIS_DATA_WIDTH-1:0]    sample_data = 'd0,
        output reg                              data_valid = 1'b0
    );

    
    reg trigger_sample_write = 1'b1;
    
always @(posedge ACLK) begin

    if(~ARESETN) begin
        sample_data <= 'd0;
        data_valid <= 1'b0;
        trigger_sample_write <= 1'b1; 
    end
    else begin

        if(data_valid) begin
            data_valid <= 1'b0;
        end

        if(enable) begin



            if(sample_clk && trigger_sample_write) begin
                sample_data <= sample_data + 'd1;
                data_valid <= 1'b1;

                trigger_sample_write <= 1'b0;
            end
            else if(~sample_clk) begin


                trigger_sample_write <= 1'b1;
            end
        end
    end
end
endmodule