data/full_repos/permissive/175808891/verilog/rle.v
1: b'%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/rle.v:31: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'bit_count\' generates 23 bits.\n                                                                     : ... In instance rle\n   else if(end_of_stream  && bit_count) next_state = COUNT_DONE;\n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module rle (clk, rst, rd_req , recv_ready ,send_ready, in_data , out_data, end_of_stream ,wr_req);
input clk,rst;
input recv_ready,send_ready;
input [7:0] in_data;
input end_of_stream ;
output [23:0] out_data;
output rd_req,wr_req;

reg rd_reg,wr_reg;
reg [22:0] bit_count;
reg [3:0] shift_count;
reg value_type;
reg [7:0] shift_buf;

reg [3:0] state;
reg [3:0] next_state;

reg new_bitstream;


parameter INIT  = 4'b0000,REQUEST_INPUT = 4'b0001,WAIT_INPUT = 4'b0010,COUNT_BITS = 4'b0011,
SHIFT_BITS = 4'b0100,COUNT_DONE = 4'b0101,WAIT_OUTPUT = 4'b0110, RESET_COUNT = 4'b0111, READ_INPUT  = 4'b1000;

always @(state or recv_ready or send_ready or end_of_stream or bit_count or new_bitstream or shift_count) begin
	case(state)
		INIT: begin
			next_state = REQUEST_INPUT;
		end
		REQUEST_INPUT: begin
			if(recv_ready) next_state = WAIT_INPUT;
			else if(end_of_stream  && bit_count) next_state = COUNT_DONE;
			else next_state = REQUEST_INPUT;
		end
		WAIT_INPUT: next_state = READ_INPUT ;
		READ_INPUT : next_state = COUNT_BITS;
		COUNT_BITS: next_state = SHIFT_BITS;
		SHIFT_BITS:
		begin
			if(new_bitstream) next_state = COUNT_DONE;
			else begin
				if(shift_count == 7) next_state = REQUEST_INPUT;
				else next_state = COUNT_BITS;
			end
		end
		COUNT_DONE:
		begin
			if(send_ready) next_state = WAIT_OUTPUT ;
			else next_state = COUNT_DONE;
		end
		WAIT_OUTPUT : next_state = RESET_COUNT ;
		RESET_COUNT : begin
			if(end_of_stream ) next_state = INIT;
			else next_state = COUNT_BITS;
		end
		default: next_state = INIT;
	endcase
end

always @(posedge clk) begin
	if(rst) state <= INIT;
	else state <= next_state;

	case(state)
	INIT: begin

		bit_count <= 0;

		shift_buf <= 0;
		rd_reg <= 0;
		wr_reg <= 0;
		new_bitstream <= 1;
	end
	REQUEST_INPUT: begin

		rd_reg<=1;
		shift_count<=0;

	end
	WAIT_INPUT: begin

		rd_reg<=0;
	end
	READ_INPUT : begin


		shift_buf<=in_data;
	end
	COUNT_BITS: begin



		if(new_bitstream) begin
			value_type<=shift_buf[0];
			bit_count<=bit_count+1;
			new_bitstream<=0;
		end
		else begin
			if(shift_buf[0] == value_type) begin
				bit_count<=bit_count+1;
			end
			else begin

				new_bitstream<=1;
			end
		end
	end
	SHIFT_BITS: begin


		if(!new_bitstream) begin
			shift_buf<=(shift_buf>>1);			
			shift_count<=shift_count+1;
		end
	end
	COUNT_DONE: begin


		wr_reg<=1;
	end
	WAIT_OUTPUT : begin

		wr_reg<=0;
	end
	RESET_COUNT : begin

		bit_count<=0;
	end
	endcase
end

assign rd_req = rd_reg;
assign wr_req = wr_reg;
assign out_data[23] = value_type;
assign out_data[22:0] = bit_count[22:0];
endmodule
module rle (clk, rst, rd_req , recv_ready ,send_ready, in_data , out_data, end_of_stream ,wr_req);

input clk,rst;
input recv_ready,send_ready;
input [7:0] in_data;
input end_of_stream ;
output [23:0] out_data;
output rd_req,wr_req;

reg rd_reg,wr_reg;
reg [22:0] bit_count;
reg [3:0] shift_count;
reg value_type;
reg [7:0] shift_buf;

reg [3:0] state;
reg [3:0] next_state;

reg new_bitstream;


parameter INIT  = 4'b0000,REQUEST_INPUT = 4'b0001,WAIT_INPUT = 4'b0010,COUNT_BITS = 4'b0011,
SHIFT_BITS = 4'b0100,COUNT_DONE = 4'b0101,WAIT_OUTPUT = 4'b0110, RESET_COUNT = 4'b0111, READ_INPUT  = 4'b1000;

always @(state or recv_ready or send_ready or end_of_stream or bit_count or new_bitstream or shift_count) begin
	case(state)
		INIT: begin
			next_state = REQUEST_INPUT;
		end
		REQUEST_INPUT: begin
			if(recv_ready) next_state = WAIT_INPUT;
			else if(end_of_stream  && bit_count) next_state = COUNT_DONE;
			else next_state = REQUEST_INPUT;
		end
		WAIT_INPUT: next_state = READ_INPUT ;
		READ_INPUT : next_state = COUNT_BITS;
		COUNT_BITS: next_state = SHIFT_BITS;
		SHIFT_BITS:
		begin
			if(new_bitstream) next_state = COUNT_DONE;
			else begin
				if(shift_count == 7) next_state = REQUEST_INPUT;
				else next_state = COUNT_BITS;
			end
		end
		COUNT_DONE:
		begin
			if(send_ready) next_state = WAIT_OUTPUT ;
			else next_state = COUNT_DONE;
		end
		WAIT_OUTPUT : next_state = RESET_COUNT ;
		RESET_COUNT : begin
			if(end_of_stream ) next_state = INIT;
			else next_state = COUNT_BITS;
		end
		default: next_state = INIT;
	endcase
end

always @(posedge clk) begin
	if(rst) state <= INIT;
	else state <= next_state;

	case(state)
	INIT: begin

		bit_count <= 0;

		shift_buf <= 0;
		rd_reg <= 0;
		wr_reg <= 0;
		new_bitstream <= 1;
	end
	REQUEST_INPUT: begin

		rd_reg<=1;
		shift_count<=0;

	end
	WAIT_INPUT: begin

		rd_reg<=0;
	end
	READ_INPUT : begin


		shift_buf<=in_data;
	end
	COUNT_BITS: begin



		if(new_bitstream) begin
			value_type<=shift_buf[0];
			bit_count<=bit_count+1;
			new_bitstream<=0;
		end
		else begin
			if(shift_buf[0] == value_type) begin
				bit_count<=bit_count+1;
			end
			else begin

				new_bitstream<=1;
			end
		end
	end
	SHIFT_BITS: begin


		if(!new_bitstream) begin
			shift_buf<=(shift_buf>>1);			
			shift_count<=shift_count+1;
		end
	end
	COUNT_DONE: begin


		wr_reg<=1;
	end
	WAIT_OUTPUT : begin

		wr_reg<=0;
	end
	RESET_COUNT : begin

		bit_count<=0;
	end
	endcase
end

assign rd_req = rd_reg;
assign wr_req = wr_reg;
assign out_data[23] = value_type;
assign out_data[22:0] = bit_count[22:0];
endmodule