data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/SN74LS366A_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/SN74LS366A_testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/SN74LS366A_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #100;      \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/SN74LS366A_testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/SN74LS366A_testbench.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #100 data <= data + 1;\n        ^\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/SN74LS366A_testbench.v:36: Cannot find file containing module: \'SN74LS365\'\n    SN74LS365 # (.INVERTED_OUTPUT(1)) uut (\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/SN74LS365\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/SN74LS365.v\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/SN74LS365.sv\n             SN74LS365\n             SN74LS365.v\n             SN74LS365.sv\n             obj_dir/SN74LS365\n             obj_dir/SN74LS365.v\n             obj_dir/SN74LS365.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SN74LS366A_testbench;


    reg e1;
    reg e2;
    reg [5:0] data;


    wire [5:0] out;


    SN74LS365 # (.INVERTED_OUTPUT(1)) uut (
        .e1(e1), 
        .e2(e2), 
        .data(data), 
        .out(out)
    );

    initial begin

        e1 = 1;
        e2 = 0;
        data = 0;
        
        #100;
        e2 = 1;


        #100;      

        e1 = 0;
        
        #100;
        e2 = 0;
    end
      
    always
    begin
        #100 data <= data + 1;
    end
      
endmodule
module SN74LS366A_testbench;



    reg e1;
    reg e2;
    reg [5:0] data;


    wire [5:0] out;


    SN74LS365 # (.INVERTED_OUTPUT(1)) uut (
        .e1(e1), 
        .e2(e2), 
        .data(data), 
        .out(out)
    );

    initial begin

        e1 = 1;
        e2 = 0;
        data = 0;
        
        #100;
        e2 = 1;


        #100;      

        e1 = 0;
        
        #100;
        e2 = 0;
    end
      
    always
    begin
        #100 data <= data + 1;
    end
      
endmodule