data/full_repos/permissive/132220215/full_adder.v
data/verilator_xmls/45845dc8-69f8-4955-beab-e95f8060fb84.xml
module full_add(
       input a_sig,
       input b_sig,
       input cin_sig,
       output sum_sig,
       output cout_sig);

 assign sum_sig = a_sig ^ b_sig ^ cin_sig; 
 assign cout_sig = (a_sig&b_sig) | (cin_sig&(a_sig ^ b_sig));

endmodule
module full_add(
       input a_sig,
       input b_sig,
       input cin_sig,
       output sum_sig,
       output cout_sig);


 assign sum_sig = a_sig ^ b_sig ^ cin_sig; 
 assign cout_sig = (a_sig&b_sig) | (cin_sig&(a_sig ^ b_sig));

endmodule