data/full_repos/permissive/106408053/verilog/filter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/filter.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module filter (clock, indata, indata180, outdata);
input clock;
input [31:0] indata;
input [31:0] indata180;
output [31:0] outdata;

reg [31:0] dly_indata, next_dly_indata; 
reg [31:0] dly_indata180, next_dly_indata180; 
reg [31:0] outdata, next_outdata;

always @(posedge clock) 
begin
  outdata = next_outdata;
  dly_indata = next_dly_indata;
  dly_indata180 = next_dly_indata180;
end

always @*
begin
  #1;
  next_outdata = (outdata | dly_indata | indata) & dly_indata180;
  next_dly_indata = indata;
  next_dly_indata180 = indata180;
end
endmodule
module filter (clock, indata, indata180, outdata);

input clock;
input [31:0] indata;
input [31:0] indata180;
output [31:0] outdata;

reg [31:0] dly_indata, next_dly_indata; 
reg [31:0] dly_indata180, next_dly_indata180; 
reg [31:0] outdata, next_outdata;

always @(posedge clock) 
begin
  outdata = next_outdata;
  dly_indata = next_dly_indata;
  dly_indata180 = next_dly_indata180;
end

always @*
begin
  #1;
  next_outdata = (outdata | dly_indata | indata) & dly_indata180;
  next_dly_indata = indata;
  next_dly_indata180 = indata180;
end
endmodule