data/full_repos/permissive/179980995/Lab2/main.v
data/verilator_xmls/ffe682a8-a3d9-41a3-a9f9-e88c87fa4fb3.xml
module arithmetic_unit(
input a,
input b,
input cin,
input [1:0] s,
output reg g,
output reg cout
);
reg c1, c2, s1;
always@(*) begin
case(s)
2'b00:
begin
g = a ^ cin;
cout = a & cin;
end

2'b01:
begin
s1 = a ^ b;
c1 = a & b;
g = s1 ^ cin;
c2 = s1 & cin;
cout = c1 | c2;
end

2'b10:
begin
s1 = a ^ (~b);
c1 = a & (~b);
g = s1 ^ cin;
c2 = s1 & cin;
cout = c1 | c2;
end

2'b11:
begin
s1 = (~a) ^ b;
c1 = (~a) & b;
g = s1 ^ cin;
c2 = s1 & cin;
cout = c1 | c2;
end
endcase
end
endmodule
module arithmetic_unit(
input a,
input b,
input cin,
input [1:0] s,
output reg g,
output reg cout
);

reg c1, c2, s1;
always@(*) begin
case(s)
2'b00:
begin
g = a ^ cin;
cout = a & cin;
end

2'b01:
begin
s1 = a ^ b;
c1 = a & b;
g = s1 ^ cin;
c2 = s1 & cin;
cout = c1 | c2;
end

2'b10:
begin
s1 = a ^ (~b);
c1 = a & (~b);
g = s1 ^ cin;
c2 = s1 & cin;
cout = c1 | c2;
end

2'b11:
begin
s1 = (~a) ^ b;
c1 = (~a) & b;
g = s1 ^ cin;
c2 = s1 & cin;
cout = c1 | c2;
end
endcase
end
endmodule