data/full_repos/permissive/143278/ivltests/always3.1.11A.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.11A.v:28: Unsupported: Ignoring delay on this delayed statement.\n          #5 ;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.11A.v:41: Unsupported: Ignoring delay on this delayed statement.\n     #6;\n     ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ;

reg [3:0] value1,value2,value3;

always begin
          #5 ;
          value1 = 1;
       end

initial
  begin
     value1 = 0;
     value2 = 0;
     if(value1 != 0)
        begin
          $display("FAILED - 3.1.11A always begin statement end");
           value2 = 1;
        end
     #6;
     if(value1 != 1)
        begin
          $display("FAILED - 3.1.11A always begin statement end");
           value2 = 1;
        end
     if(value2 == 0)
           $display("PASSED");
     $finish ;
  end

endmodule
module main ;


reg [3:0] value1,value2,value3;

always begin
          #5 ;
          value1 = 1;
       end

initial
  begin
     value1 = 0;
     value2 = 0;
     if(value1 != 0)
        begin
          $display("FAILED - 3.1.11A always begin statement end");
           value2 = 1;
        end
     #6;
     if(value1 != 1)
        begin
          $display("FAILED - 3.1.11A always begin statement end");
           value2 = 1;
        end
     if(value2 == 0)
           $display("PASSED");
     $finish ;
  end

endmodule