data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_io_lvds_dual_mode.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_io_lvds_dual_mode.v:334: Signal definition not found, creating implicitly: \'radio_rst_2x\'\n                                                                                                                                                 : ... Suggested alternative: \'radio_rst\'\n    if (radio_rst_2x) begin\n        ^~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_io_lvds_dual_mode.v:100: Cannot find file containing module: \'synchronizer\'\n  synchronizer mimo_sync (\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen,data/full_repos/permissive/214858095/synchronizer\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen,data/full_repos/permissive/214858095/synchronizer.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen,data/full_repos/permissive/214858095/synchronizer.sv\n             synchronizer\n             synchronizer.v\n             synchronizer.sv\n             obj_dir/synchronizer\n             obj_dir/synchronizer.v\n             obj_dir/synchronizer.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_io_lvds_dual_mode.v:107: Cannot find file containing module: \'synchronizer\'\n  synchronizer tx_ch_sync (\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_io_lvds_dual_mode.v:120: Cannot find file containing module: \'BUFGCTRL\'\n  BUFGCTRL BUFGCTRL_radio_clk (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_io_lvds_dual_mode.v:256: Cannot find file containing module: \'fifo_short_2clk\'\n  fifo_short_2clk fifo_short_2clk_rx (\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_io_lvds_dual_mode.v:299: Cannot find file containing module: \'synchronizer\'\n  synchronizer #(\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_io_lvds_dual_mode.v:317: Cannot find file containing module: \'fifo_short_2clk\'\n  fifo_short_2clk fifo_short_2clk_tx (\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_io_lvds_dual_mode.v:409: Cannot find file containing module: \'cat_io_lvds\'\n  cat_io_lvds #(\n  ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n'
module cat_io_lvds_dual_mode #(
  parameter INVERT_FRAME_RX    = 0,
  parameter INVERT_DATA_RX     = 6'b00_0000,
  parameter INVERT_FRAME_TX    = 0,
  parameter INVERT_DATA_TX     = 6'b00_0000,
  parameter USE_CLOCK_IDELAY   = 1,
  parameter USE_DATA_IDELAY    = 1,
  parameter DATA_IDELAY_MODE   = "FIXED",
  parameter CLOCK_IDELAY_MODE  = "FIXED",
  parameter INPUT_CLOCK_DELAY  = 16,
  parameter INPUT_DATA_DELAY   = 0,
  parameter USE_CLOCK_ODELAY   = 0,
  parameter USE_DATA_ODELAY    = 0,
  parameter DATA_ODELAY_MODE   = "FIXED",
  parameter CLOCK_ODELAY_MODE  = "FIXED",
  parameter OUTPUT_CLOCK_DELAY = 16,
  parameter OUTPUT_DATA_DELAY  = 0
) (
  input clk200,


  input a_mimo,
  input a_tx_ch,


  input       ctrl_clk,
  input [4:0] ctrl_in_data_delay,
  input [4:0] ctrl_in_clk_delay,
  input       ctrl_ld_in_data_delay,
  input       ctrl_ld_in_clk_delay,
  input [4:0] ctrl_out_data_delay,
  input [4:0] ctrl_out_clk_delay,
  input       ctrl_ld_out_data_delay,
  input       ctrl_ld_out_clk_delay,


  input  radio_rst,
  output radio_clk,

  output reg    rx_aligned,
  output [11:0] rx_i0,
  output [11:0] rx_q0,
  output [11:0] rx_i1,
  output [11:0] rx_q1,

  input  [11:0] tx_i0,
  input  [11:0] tx_q0,
  input  [11:0] tx_i1,
  input  [11:0] tx_q1,


  input        rx_clk_p,
  input        rx_clk_n,
  input        rx_frame_p,
  input        rx_frame_n,
  input  [5:0] rx_d_p,
  input  [5:0] rx_d_n,

  output       tx_clk_p,
  output       tx_clk_n,
  output       tx_frame_p,
  output       tx_frame_n,
  output [5:0] tx_d_p,
  output [5:0] tx_d_n
);

  wire radio_clk_1x;
  wire radio_clk_2x;






  wire r_mimo;
  wire r_tx_ch;


  synchronizer mimo_sync (
    .clk(radio_clk_1x),
    .rst(1'b0),
    .in(a_mimo),
    .out(r_mimo));


  synchronizer tx_ch_sync (
    .clk(radio_clk_1x),
    .rst(1'b0),
    .in(a_tx_ch),
    .out(r_tx_ch));








  BUFGCTRL BUFGCTRL_radio_clk (
    .I0      (radio_clk_1x),
    .I1      (radio_clk_2x),
    .S0      (r_mimo),
    .S1      (~r_mimo),
    .CE0     (1),
    .CE1     (1),
    .O       (radio_clk),
    .IGNORE0 (0),
    .IGNORE1 (0)
  );
























  reg align_1x = 0;
  reg align_2x = 0;

  always @(posedge radio_clk_1x)
  begin
    align_1x <= ~align_1x;
  end

  always @(posedge radio_clk_2x)
  begin


    align_2x <= align_1x;
  end












  wire rx_aligned_t;
  reg rx_aligned_reg;

  wire [11:0] rx_i0_t;
  wire [11:0] rx_q0_t;
  wire [11:0] rx_i1_t;
  wire [11:0] rx_q1_t;

  reg [11:0] rx_i0_ser;
  reg [11:0] rx_q0_ser;
  reg [11:0] rx_i1_ser;
  reg [11:0] rx_q1_ser;

  reg [11:0] rx_i0_out;
  reg [11:0] rx_q0_out;
  reg [11:0] rx_i1_out;
  reg [11:0] rx_q1_out;

  reg rx_out_val;

  always @(posedge radio_clk_2x)
  begin
    rx_aligned_reg <= rx_aligned_t;

    if (align_1x ^ align_2x) begin


      rx_i0_ser <= rx_i0_t;
      rx_q0_ser <= rx_q0_t;
      rx_i1_ser <= rx_i0_t;
      rx_q1_ser <= rx_q0_t;
    end else begin


      rx_i0_ser <= rx_i1_t;
      rx_q0_ser <= rx_q1_t;
      rx_i1_ser <= rx_i1_t;
      rx_q1_ser <= rx_q1_t;
    end


    if (r_mimo) begin


      rx_out_val <= ~rx_out_val;
      rx_i0_out <= rx_i0_t;
      rx_q0_out <= rx_q0_t;
      rx_i1_out <= rx_i1_t;
      rx_q1_out <= rx_q1_t;
    end else begin


      rx_out_val <= 1'b1;
      rx_i0_out <= rx_i0_ser;
      rx_q0_out <= rx_q0_ser;
      rx_i1_out <= rx_i1_ser;
      rx_q1_out <= rx_q1_ser;
    end
  end












  wire rx_fifo_full;
  wire rx_fifo_empty;
  reg  rx_fifo_rd_en;

  fifo_short_2clk fifo_short_2clk_rx (
    .rst           (radio_rst),
    .wr_clk        (radio_clk_2x),
    .rd_clk        (radio_clk),
    .din           ({rx_i1_out, rx_q1_out, rx_i0_out, rx_q0_out}),
    .wr_en         (rx_out_val & ~rx_fifo_full & rx_aligned_reg),
    .rd_en         (rx_fifo_rd_en & ~rx_fifo_empty),
    .dout          ({rx_i1, rx_q1, rx_i0, rx_q0 }),
    .full          (rx_fifo_full),
    .empty         (rx_fifo_empty),
    .rd_data_count (),
    .wr_data_count ()
  );



  always @(posedge radio_clk) begin
    if (radio_rst) begin
      rx_fifo_rd_en <= 1'b0;
      rx_aligned    <= 1'b0;
    end else begin
      if (!rx_fifo_empty) begin
        rx_fifo_rd_en <= 1'b1;
        rx_aligned    <= 1'b1;
      end else if (rx_fifo_empty) begin
        rx_fifo_rd_en <= 1'b0;
        rx_aligned    <= 1'b0;
      end
    end
  end













  synchronizer #(
    .INITIAL_VAL (1'b1)
  ) synchronizer_radio_rst_2x (
    .clk (radio_clk_2x),
    .rst (1'b0),
    .in  (radio_rst),
    .out (radio_rst_2x)
  );

  wire [11:0] tx_i0_del0;
  wire [11:0] tx_q0_del0;
  wire [11:0] tx_i1_del0;
  wire [11:0] tx_q1_del0;

  wire tx_fifo_full;
  wire tx_fifo_empty;
  reg  tx_fifo_rd_en;

  fifo_short_2clk fifo_short_2clk_tx (
    .rst           (radio_rst),
    .wr_clk        (radio_clk),
    .rd_clk        (radio_clk_2x),
    .din           ({tx_i1, tx_q1, tx_i0, tx_q0}),
    .wr_en         (~tx_fifo_full),
    .rd_en         (tx_fifo_rd_en & ~tx_fifo_empty),
    .dout          ({tx_i1_del0, tx_q1_del0, tx_i0_del0, tx_q0_del0}),
    .full          (tx_fifo_full),
    .empty         (tx_fifo_empty),
    .rd_data_count (),
    .wr_data_count ()
  );



  always @(posedge radio_clk_2x) begin
    if (radio_rst_2x) begin
      tx_fifo_rd_en <= 1'b0;
    end else begin
      if (!tx_fifo_empty) begin
        tx_fifo_rd_en <= 1'b1;
      end else if (tx_fifo_empty) begin
        tx_fifo_rd_en <= 1'b0;
      end
    end
  end













  reg [11:0] tx_i0_del1;
  reg [11:0] tx_q0_del1;
  reg [11:0] tx_i1_del1;
  reg [11:0] tx_q1_del1;

  reg [11:0] tx_i0_t;
  reg [11:0] tx_q0_t;
  reg [11:0] tx_i1_t;
  reg [11:0] tx_q1_t;

  always @(posedge radio_clk_2x)
  begin

    tx_i0_del1 <= tx_i0_del0;
    tx_q0_del1 <= tx_q0_del0;
    tx_i1_del1 <= tx_i1_del0;
    tx_q1_del1 <= tx_q1_del0;
  end

  always @(posedge radio_clk_1x)
  begin
    if (r_mimo) begin


      tx_i0_t <= tx_i0_del0;
      tx_q0_t <= tx_q0_del0;
      tx_i1_t <= tx_i1_del0;
      tx_q1_t <= tx_q1_del0;
    end else begin




      if (r_tx_ch == 0) begin
        tx_i0_t <= tx_i0_del1;
        tx_q0_t <= tx_q0_del1;
        tx_i1_t <= tx_i0_del0;
        tx_q1_t <= tx_q0_del0;
      end else begin
        tx_i0_t <= tx_i1_del1;
        tx_q0_t <= tx_q1_del1;
        tx_i1_t <= tx_i1_del0;
        tx_q1_t <= tx_q1_del0;
      end
    end
  end






  cat_io_lvds #(
    .INVERT_FRAME_RX    (0),
    .INVERT_DATA_RX     (6'b00_0000),
    .INVERT_FRAME_TX    (0),
    .INVERT_DATA_TX     (6'b00_0000),
    .USE_CLOCK_IDELAY   (USE_CLOCK_IDELAY),
    .USE_DATA_IDELAY    (USE_DATA_IDELAY),
    .DATA_IDELAY_MODE   (DATA_IDELAY_MODE),
    .CLOCK_IDELAY_MODE  (CLOCK_IDELAY_MODE),
    .INPUT_CLOCK_DELAY  (INPUT_CLOCK_DELAY),
    .INPUT_DATA_DELAY   (INPUT_DATA_DELAY),
    .USE_CLOCK_ODELAY   (USE_CLOCK_ODELAY),
    .USE_DATA_ODELAY    (USE_DATA_ODELAY),
    .DATA_ODELAY_MODE   (DATA_ODELAY_MODE),
    .CLOCK_ODELAY_MODE  (CLOCK_ODELAY_MODE),
    .OUTPUT_CLOCK_DELAY (OUTPUT_CLOCK_DELAY),
    .OUTPUT_DATA_DELAY  (OUTPUT_DATA_DELAY),
    .USE_BUFG           (0)
  ) cat_io_lvds_i0 (
    .rst    (radio_rst),
    .clk200 (clk200),


    .mimo         (1),
    .frame_sample (~r_mimo),


    .ctrl_clk               (ctrl_clk),

    .ctrl_in_data_delay     (ctrl_in_data_delay),
    .ctrl_in_clk_delay      (ctrl_in_clk_delay),
    .ctrl_ld_in_data_delay  (ctrl_ld_in_data_delay),
    .ctrl_ld_in_clk_delay   (ctrl_ld_in_clk_delay),

    .ctrl_out_data_delay    (ctrl_out_data_delay),
    .ctrl_out_clk_delay     (ctrl_out_clk_delay),
    .ctrl_ld_out_data_delay (ctrl_ld_out_data_delay),
    .ctrl_ld_out_clk_delay  (ctrl_ld_out_clk_delay),


    .radio_clk    (radio_clk_1x),
    .radio_clk_2x (radio_clk_2x),
    .rx_aligned   (rx_aligned_t),

    .rx_i0        (rx_i0_t),
    .rx_q0        (rx_q0_t),
    .rx_i1        (rx_i1_t),
    .rx_q1        (rx_q1_t),

    .tx_i0        (tx_i0_t),
    .tx_q0        (tx_q0_t),
    .tx_i1        (tx_i1_t),
    .tx_q1        (tx_q1_t),


    .rx_clk_p   (rx_clk_p),
    .rx_clk_n   (rx_clk_n),
    .rx_frame_p (rx_frame_p),
    .rx_frame_n (rx_frame_n),
    .rx_d_p     (rx_d_p),
    .rx_d_n     (rx_d_n),

    .tx_clk_p   (tx_clk_p),
    .tx_clk_n   (tx_clk_n),
    .tx_frame_p (tx_frame_p),
    .tx_frame_n (tx_frame_n),
    .tx_d_p     (tx_d_p),
    .tx_d_n     (tx_d_n)
  );

endmodule
module cat_io_lvds_dual_mode #(
  parameter INVERT_FRAME_RX    = 0,
  parameter INVERT_DATA_RX     = 6'b00_0000,
  parameter INVERT_FRAME_TX    = 0,
  parameter INVERT_DATA_TX     = 6'b00_0000,
  parameter USE_CLOCK_IDELAY   = 1,
  parameter USE_DATA_IDELAY    = 1,
  parameter DATA_IDELAY_MODE   = "FIXED",
  parameter CLOCK_IDELAY_MODE  = "FIXED",
  parameter INPUT_CLOCK_DELAY  = 16,
  parameter INPUT_DATA_DELAY   = 0,
  parameter USE_CLOCK_ODELAY   = 0,
  parameter USE_DATA_ODELAY    = 0,
  parameter DATA_ODELAY_MODE   = "FIXED",
  parameter CLOCK_ODELAY_MODE  = "FIXED",
  parameter OUTPUT_CLOCK_DELAY = 16,
  parameter OUTPUT_DATA_DELAY  = 0
) (
  input clk200,


  input a_mimo,
  input a_tx_ch,


  input       ctrl_clk,
  input [4:0] ctrl_in_data_delay,
  input [4:0] ctrl_in_clk_delay,
  input       ctrl_ld_in_data_delay,
  input       ctrl_ld_in_clk_delay,
  input [4:0] ctrl_out_data_delay,
  input [4:0] ctrl_out_clk_delay,
  input       ctrl_ld_out_data_delay,
  input       ctrl_ld_out_clk_delay,


  input  radio_rst,
  output radio_clk,

  output reg    rx_aligned,
  output [11:0] rx_i0,
  output [11:0] rx_q0,
  output [11:0] rx_i1,
  output [11:0] rx_q1,

  input  [11:0] tx_i0,
  input  [11:0] tx_q0,
  input  [11:0] tx_i1,
  input  [11:0] tx_q1,


  input        rx_clk_p,
  input        rx_clk_n,
  input        rx_frame_p,
  input        rx_frame_n,
  input  [5:0] rx_d_p,
  input  [5:0] rx_d_n,

  output       tx_clk_p,
  output       tx_clk_n,
  output       tx_frame_p,
  output       tx_frame_n,
  output [5:0] tx_d_p,
  output [5:0] tx_d_n
);


  wire radio_clk_1x;
  wire radio_clk_2x;






  wire r_mimo;
  wire r_tx_ch;


  synchronizer mimo_sync (
    .clk(radio_clk_1x),
    .rst(1'b0),
    .in(a_mimo),
    .out(r_mimo));


  synchronizer tx_ch_sync (
    .clk(radio_clk_1x),
    .rst(1'b0),
    .in(a_tx_ch),
    .out(r_tx_ch));








  BUFGCTRL BUFGCTRL_radio_clk (
    .I0      (radio_clk_1x),
    .I1      (radio_clk_2x),
    .S0      (r_mimo),
    .S1      (~r_mimo),
    .CE0     (1),
    .CE1     (1),
    .O       (radio_clk),
    .IGNORE0 (0),
    .IGNORE1 (0)
  );
























  reg align_1x = 0;
  reg align_2x = 0;

  always @(posedge radio_clk_1x)
  begin
    align_1x <= ~align_1x;
  end

  always @(posedge radio_clk_2x)
  begin


    align_2x <= align_1x;
  end












  wire rx_aligned_t;
  reg rx_aligned_reg;

  wire [11:0] rx_i0_t;
  wire [11:0] rx_q0_t;
  wire [11:0] rx_i1_t;
  wire [11:0] rx_q1_t;

  reg [11:0] rx_i0_ser;
  reg [11:0] rx_q0_ser;
  reg [11:0] rx_i1_ser;
  reg [11:0] rx_q1_ser;

  reg [11:0] rx_i0_out;
  reg [11:0] rx_q0_out;
  reg [11:0] rx_i1_out;
  reg [11:0] rx_q1_out;

  reg rx_out_val;

  always @(posedge radio_clk_2x)
  begin
    rx_aligned_reg <= rx_aligned_t;

    if (align_1x ^ align_2x) begin


      rx_i0_ser <= rx_i0_t;
      rx_q0_ser <= rx_q0_t;
      rx_i1_ser <= rx_i0_t;
      rx_q1_ser <= rx_q0_t;
    end else begin


      rx_i0_ser <= rx_i1_t;
      rx_q0_ser <= rx_q1_t;
      rx_i1_ser <= rx_i1_t;
      rx_q1_ser <= rx_q1_t;
    end


    if (r_mimo) begin


      rx_out_val <= ~rx_out_val;
      rx_i0_out <= rx_i0_t;
      rx_q0_out <= rx_q0_t;
      rx_i1_out <= rx_i1_t;
      rx_q1_out <= rx_q1_t;
    end else begin


      rx_out_val <= 1'b1;
      rx_i0_out <= rx_i0_ser;
      rx_q0_out <= rx_q0_ser;
      rx_i1_out <= rx_i1_ser;
      rx_q1_out <= rx_q1_ser;
    end
  end












  wire rx_fifo_full;
  wire rx_fifo_empty;
  reg  rx_fifo_rd_en;

  fifo_short_2clk fifo_short_2clk_rx (
    .rst           (radio_rst),
    .wr_clk        (radio_clk_2x),
    .rd_clk        (radio_clk),
    .din           ({rx_i1_out, rx_q1_out, rx_i0_out, rx_q0_out}),
    .wr_en         (rx_out_val & ~rx_fifo_full & rx_aligned_reg),
    .rd_en         (rx_fifo_rd_en & ~rx_fifo_empty),
    .dout          ({rx_i1, rx_q1, rx_i0, rx_q0 }),
    .full          (rx_fifo_full),
    .empty         (rx_fifo_empty),
    .rd_data_count (),
    .wr_data_count ()
  );



  always @(posedge radio_clk) begin
    if (radio_rst) begin
      rx_fifo_rd_en <= 1'b0;
      rx_aligned    <= 1'b0;
    end else begin
      if (!rx_fifo_empty) begin
        rx_fifo_rd_en <= 1'b1;
        rx_aligned    <= 1'b1;
      end else if (rx_fifo_empty) begin
        rx_fifo_rd_en <= 1'b0;
        rx_aligned    <= 1'b0;
      end
    end
  end













  synchronizer #(
    .INITIAL_VAL (1'b1)
  ) synchronizer_radio_rst_2x (
    .clk (radio_clk_2x),
    .rst (1'b0),
    .in  (radio_rst),
    .out (radio_rst_2x)
  );

  wire [11:0] tx_i0_del0;
  wire [11:0] tx_q0_del0;
  wire [11:0] tx_i1_del0;
  wire [11:0] tx_q1_del0;

  wire tx_fifo_full;
  wire tx_fifo_empty;
  reg  tx_fifo_rd_en;

  fifo_short_2clk fifo_short_2clk_tx (
    .rst           (radio_rst),
    .wr_clk        (radio_clk),
    .rd_clk        (radio_clk_2x),
    .din           ({tx_i1, tx_q1, tx_i0, tx_q0}),
    .wr_en         (~tx_fifo_full),
    .rd_en         (tx_fifo_rd_en & ~tx_fifo_empty),
    .dout          ({tx_i1_del0, tx_q1_del0, tx_i0_del0, tx_q0_del0}),
    .full          (tx_fifo_full),
    .empty         (tx_fifo_empty),
    .rd_data_count (),
    .wr_data_count ()
  );



  always @(posedge radio_clk_2x) begin
    if (radio_rst_2x) begin
      tx_fifo_rd_en <= 1'b0;
    end else begin
      if (!tx_fifo_empty) begin
        tx_fifo_rd_en <= 1'b1;
      end else if (tx_fifo_empty) begin
        tx_fifo_rd_en <= 1'b0;
      end
    end
  end













  reg [11:0] tx_i0_del1;
  reg [11:0] tx_q0_del1;
  reg [11:0] tx_i1_del1;
  reg [11:0] tx_q1_del1;

  reg [11:0] tx_i0_t;
  reg [11:0] tx_q0_t;
  reg [11:0] tx_i1_t;
  reg [11:0] tx_q1_t;

  always @(posedge radio_clk_2x)
  begin

    tx_i0_del1 <= tx_i0_del0;
    tx_q0_del1 <= tx_q0_del0;
    tx_i1_del1 <= tx_i1_del0;
    tx_q1_del1 <= tx_q1_del0;
  end

  always @(posedge radio_clk_1x)
  begin
    if (r_mimo) begin


      tx_i0_t <= tx_i0_del0;
      tx_q0_t <= tx_q0_del0;
      tx_i1_t <= tx_i1_del0;
      tx_q1_t <= tx_q1_del0;
    end else begin




      if (r_tx_ch == 0) begin
        tx_i0_t <= tx_i0_del1;
        tx_q0_t <= tx_q0_del1;
        tx_i1_t <= tx_i0_del0;
        tx_q1_t <= tx_q0_del0;
      end else begin
        tx_i0_t <= tx_i1_del1;
        tx_q0_t <= tx_q1_del1;
        tx_i1_t <= tx_i1_del0;
        tx_q1_t <= tx_q1_del0;
      end
    end
  end






  cat_io_lvds #(
    .INVERT_FRAME_RX    (0),
    .INVERT_DATA_RX     (6'b00_0000),
    .INVERT_FRAME_TX    (0),
    .INVERT_DATA_TX     (6'b00_0000),
    .USE_CLOCK_IDELAY   (USE_CLOCK_IDELAY),
    .USE_DATA_IDELAY    (USE_DATA_IDELAY),
    .DATA_IDELAY_MODE   (DATA_IDELAY_MODE),
    .CLOCK_IDELAY_MODE  (CLOCK_IDELAY_MODE),
    .INPUT_CLOCK_DELAY  (INPUT_CLOCK_DELAY),
    .INPUT_DATA_DELAY   (INPUT_DATA_DELAY),
    .USE_CLOCK_ODELAY   (USE_CLOCK_ODELAY),
    .USE_DATA_ODELAY    (USE_DATA_ODELAY),
    .DATA_ODELAY_MODE   (DATA_ODELAY_MODE),
    .CLOCK_ODELAY_MODE  (CLOCK_ODELAY_MODE),
    .OUTPUT_CLOCK_DELAY (OUTPUT_CLOCK_DELAY),
    .OUTPUT_DATA_DELAY  (OUTPUT_DATA_DELAY),
    .USE_BUFG           (0)
  ) cat_io_lvds_i0 (
    .rst    (radio_rst),
    .clk200 (clk200),


    .mimo         (1),
    .frame_sample (~r_mimo),


    .ctrl_clk               (ctrl_clk),

    .ctrl_in_data_delay     (ctrl_in_data_delay),
    .ctrl_in_clk_delay      (ctrl_in_clk_delay),
    .ctrl_ld_in_data_delay  (ctrl_ld_in_data_delay),
    .ctrl_ld_in_clk_delay   (ctrl_ld_in_clk_delay),

    .ctrl_out_data_delay    (ctrl_out_data_delay),
    .ctrl_out_clk_delay     (ctrl_out_clk_delay),
    .ctrl_ld_out_data_delay (ctrl_ld_out_data_delay),
    .ctrl_ld_out_clk_delay  (ctrl_ld_out_clk_delay),


    .radio_clk    (radio_clk_1x),
    .radio_clk_2x (radio_clk_2x),
    .rx_aligned   (rx_aligned_t),

    .rx_i0        (rx_i0_t),
    .rx_q0        (rx_q0_t),
    .rx_i1        (rx_i1_t),
    .rx_q1        (rx_q1_t),

    .tx_i0        (tx_i0_t),
    .tx_q0        (tx_q0_t),
    .tx_i1        (tx_i1_t),
    .tx_q1        (tx_q1_t),


    .rx_clk_p   (rx_clk_p),
    .rx_clk_n   (rx_clk_n),
    .rx_frame_p (rx_frame_p),
    .rx_frame_n (rx_frame_n),
    .rx_d_p     (rx_d_p),
    .rx_d_n     (rx_d_n),

    .tx_clk_p   (tx_clk_p),
    .tx_clk_n   (tx_clk_n),
    .tx_frame_p (tx_frame_p),
    .tx_frame_n (tx_frame_n),
    .tx_d_p     (tx_d_p),
    .tx_d_n     (tx_d_n)
  );

endmodule