data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:2: Cannot find include file: ./comparator.v\n`include "./comparator.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219917900/rx_rtl_files/sim,data/full_repos/permissive/219917900/./comparator.v\n             data/full_repos/permissive/219917900/rx_rtl_files/sim,data/full_repos/permissive/219917900/./comparator.v.v\n             data/full_repos/permissive/219917900/rx_rtl_files/sim,data/full_repos/permissive/219917900/./comparator.v.sv\n             ./comparator.v\n             ./comparator.v.v\n             ./comparator.v.sv\n             obj_dir/./comparator.v\n             obj_dir/./comparator.v.v\n             obj_dir/./comparator.v.sv\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:7: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("comparator.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:8: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,comp);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:33: Unsupported: Ignoring delay on this delayed statement.\n clk = !clk;#5;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:43: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:47: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:50: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:53: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:58: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:63: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:64: Unsupported: Ignoring delay on this delayed statement.\nen=1\'b0;#120;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_comparator.v:68: Unsupported: Ignoring delay on this delayed statement.\n#500;\n^\n%Error: Exiting due to 3 error(s), 9 warning(s)\n'
module tb_comparator;

initial begin
	$dumpfile("comparator.vcd");
	$dumpvars(0,comp);

end

reg clk = 0;
reg [7:0] rxdata;

reg en=0;
reg [7:0] bramout;
wire valid,result;
wire shift4_result;

comparator comp(
	.clk(clk),
	.rxdata(rxdata),


	.en(en),
	.bramout(bramout),
	.valid(valid),
	.result(result),
	.shift4_result(shift4_result)
);

always begin
	clk = !clk;#5;
end

integer i;
integer j;
integer k;
initial begin
for (k=0; k<2; k = k+1) begin
for (j=0; j<7; j = j+1) begin
for (i=0; i < 7; i = i + 1) begin
#10;
en=1'b1;
rxdata = 8'hde;
bramout = 8'hde;
#10;
rxdata = 8'had;
bramout = 8'had;
#10;
rxdata = 8'hbe;
bramout = 8'hbe;
#10;
rxdata = 8'hef;
bramout = 8'hef;
end
for (i=0; i<4+k; i = i+1) begin
#10;
rxdata = 8'haa;
bramout = i%2'b10;

end
#10;
en=1'b0;#120;
end
end

#500;
$finish;
end



endmodule
module tb_comparator;


initial begin
	$dumpfile("comparator.vcd");
	$dumpvars(0,comp);

end

reg clk = 0;
reg [7:0] rxdata;

reg en=0;
reg [7:0] bramout;
wire valid,result;
wire shift4_result;

comparator comp(
	.clk(clk),
	.rxdata(rxdata),


	.en(en),
	.bramout(bramout),
	.valid(valid),
	.result(result),
	.shift4_result(shift4_result)
);

always begin
	clk = !clk;#5;
end

integer i;
integer j;
integer k;
initial begin
for (k=0; k<2; k = k+1) begin
for (j=0; j<7; j = j+1) begin
for (i=0; i < 7; i = i + 1) begin
#10;
en=1'b1;
rxdata = 8'hde;
bramout = 8'hde;
#10;
rxdata = 8'had;
bramout = 8'had;
#10;
rxdata = 8'hbe;
bramout = 8'hbe;
#10;
rxdata = 8'hef;
bramout = 8'hef;
end
for (i=0; i<4+k; i = i+1) begin
#10;
rxdata = 8'haa;
bramout = i%2'b10;

end
#10;
en=1'b0;#120;
end
end

#500;
$finish;
end



endmodule