data/full_repos/permissive/127519632/lfsr.v
1: b'%Warning-WIDTH: data/full_repos/permissive/127519632/lfsr.v:39: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                              : ... In instance lfsr\n  carry <= 4\'b0000;\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module lfsr(
	carry,
	random_out,
	reset_in,
	enable_n,
	rst_n,
	clk);

output reg carry;
output [3:0]random_out;
input [3:0]reset_in;
input rst_n, clk, enable_n;

reg [3:0]tmp;
reg [3:0]tmp_of_carry;

assign random_out = tmp;

always @(posedge clk) begin
	if(rst_n) begin
		if(enable_n) begin
			tmp[0] <= tmp[2] ^ tmp[3];
			tmp[1] <= tmp[0];
			tmp[2] <= tmp[1];
			tmp[3] <= tmp[2];
			if(tmp_of_carry == tmp) begin
				carry <= 0'b1;
			end
			else begin
				carry <= 0'b0;
			end
		end
		else begin
			carry <= 0;
		end
	end
	else begin
		tmp <= reset_in;
		carry <= 4'b0000;
		tmp_of_carry <= reset_in; 
	end
end

endmodule
module lfsr(
	carry,
	random_out,
	reset_in,
	enable_n,
	rst_n,
	clk);


output reg carry;
output [3:0]random_out;
input [3:0]reset_in;
input rst_n, clk, enable_n;

reg [3:0]tmp;
reg [3:0]tmp_of_carry;

assign random_out = tmp;

always @(posedge clk) begin
	if(rst_n) begin
		if(enable_n) begin
			tmp[0] <= tmp[2] ^ tmp[3];
			tmp[1] <= tmp[0];
			tmp[2] <= tmp[1];
			tmp[3] <= tmp[2];
			if(tmp_of_carry == tmp) begin
				carry <= 0'b1;
			end
			else begin
				carry <= 0'b0;
			end
		end
		else begin
			carry <= 0;
		end
	end
	else begin
		tmp <= reset_in;
		carry <= 4'b0000;
		tmp_of_carry <= reset_in; 
	end
end

endmodule