data/full_repos/permissive/170902741/hw3_2/rca_4b.v
1: b"%Error: data/full_repos/permissive/170902741/hw3_2/rca_4b.v:20: Cannot find file containing module: 'fullAdder_1b'\n fullAdder_1b adder_1b_0(.A(A[0]), .B(B[0]), .C_in(C_in), .S(S[0]), .C_out(c_out[0]));\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170902741/hw3_2,data/full_repos/permissive/170902741/fullAdder_1b\n             data/full_repos/permissive/170902741/hw3_2,data/full_repos/permissive/170902741/fullAdder_1b.v\n             data/full_repos/permissive/170902741/hw3_2,data/full_repos/permissive/170902741/fullAdder_1b.sv\n             fullAdder_1b\n             fullAdder_1b.v\n             fullAdder_1b.sv\n             obj_dir/fullAdder_1b\n             obj_dir/fullAdder_1b.v\n             obj_dir/fullAdder_1b.sv\n%Error: data/full_repos/permissive/170902741/hw3_2/rca_4b.v:21: Cannot find file containing module: 'fullAdder_1b'\n fullAdder_1b adder_1b_1(.A(A[1]), .B(B[1]), .C_in(c_out[0]), .S(S[1]), .C_out(c_out[1]));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/170902741/hw3_2/rca_4b.v:22: Cannot find file containing module: 'fullAdder_1b'\n fullAdder_1b adder_1b_2(.A(A[2]), .B(B[2]), .C_in(c_out[1]), .S(S[2]), .C_out(c_out[2]));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/170902741/hw3_2/rca_4b.v:23: Cannot find file containing module: 'fullAdder_1b'\n fullAdder_1b adder_1b_3(.A(A[N - 1]), .B(B[N - 1]), .C_in(c_out[N - 2]), .S(S[N - 1]), .C_out(C_out));\n ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module rca_4b(A, B, C_in, S, C_out);


    parameter   N = 4;

    input [N-1: 0] A, B;
    input          C_in;
    output [N-1:0] S;
    output         C_out;

	wire c_out[N-2:0];


	fullAdder_1b adder_1b_0(.A(A[0]), .B(B[0]), .C_in(C_in), .S(S[0]), .C_out(c_out[0]));
	fullAdder_1b adder_1b_1(.A(A[1]), .B(B[1]), .C_in(c_out[0]), .S(S[1]), .C_out(c_out[1]));
	fullAdder_1b adder_1b_2(.A(A[2]), .B(B[2]), .C_in(c_out[1]), .S(S[2]), .C_out(c_out[2]));
	fullAdder_1b adder_1b_3(.A(A[N - 1]), .B(B[N - 1]), .C_in(c_out[N - 2]), .S(S[N - 1]), .C_out(C_out));

endmodule
module rca_4b(A, B, C_in, S, C_out);



    parameter   N = 4;

    input [N-1: 0] A, B;
    input          C_in;
    output [N-1:0] S;
    output         C_out;

	wire c_out[N-2:0];


	fullAdder_1b adder_1b_0(.A(A[0]), .B(B[0]), .C_in(C_in), .S(S[0]), .C_out(c_out[0]));
	fullAdder_1b adder_1b_1(.A(A[1]), .B(B[1]), .C_in(c_out[0]), .S(S[1]), .C_out(c_out[1]));
	fullAdder_1b adder_1b_2(.A(A[2]), .B(B[2]), .C_in(c_out[1]), .S(S[2]), .C_out(c_out[2]));
	fullAdder_1b adder_1b_3(.A(A[N - 1]), .B(B[N - 1]), .C_in(c_out[N - 2]), .S(S[N - 1]), .C_out(C_out));

endmodule