data/full_repos/permissive/123339956/Lab3_Structural_Modelling/ripple_adder.v
 line:17: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab3_Structural_Modelling/ripple_adder.v:13: Unsupported: Ignoring delay on this delayed statement.\n #00 a=4\'d10; b=4\'d2;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab3_Structural_Modelling/ripple_adder.v:14: Unsupported: Ignoring delay on this delayed statement.\n #20 a=4\'d10; b=4\'d10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab3_Structural_Modelling/ripple_adder.v:15: Unsupported: Ignoring delay on this delayed statement.\n #20 a=4\'d3; b=4\'d5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab3_Structural_Modelling/ripple_adder.v:16: Unsupported: Ignoring delay on this delayed statement.\n #20 a=4\'d15; b=4\'d15;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab3_Structural_Modelling/ripple_adder.v:17: Unsupported: Ignoring delay on this delayed statement.\n #20 $stop;\n ^\n%Error: data/full_repos/permissive/123339956/Lab3_Structural_Modelling/ripple_adder.v:22: Unsupported or unknown PLI call: $monitor\n $monitor("time=%3d, a=%4b, b=%4b, d=%4b, cout=%1b",$time,a,b,d,cout);\n ^~~~~~~~\n%Error: data/full_repos/permissive/123339956/Lab3_Structural_Modelling/ripple_adder.v:27: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ripple_adder.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/123339956/Lab3_Structural_Modelling/ripple_adder.v:28: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ripple_adder(d,cout,a,b);
	output [3:0] d;
	output cout;
	input [3:0] a,b;
	wire c0,c1,c2;
	full_adder f0(d[0],c0,a[0],b[0],1'b0);
	full_adder f1(d[1],c1,a[1],b[1],c0);
	full_adder f2(d[2],c2,a[2],b[2],c1);
	full_adder f3(d[3],cout,a[3],b[3],c2);
endmodule
module ripple_adder(d,cout,a,b);

	output [3:0] d;
	output cout;
	input [3:0] a,b;
	wire c0,c1,c2;
	full_adder f0(d[0],c0,a[0],b[0],1'b0);
	full_adder f1(d[1],c1,a[1],b[1],c0);
	full_adder f2(d[2],c2,a[2],b[2],c1);
	full_adder f3(d[3],cout,a[3],b[3],c2);
endmodule