data/full_repos/permissive/146246005/Sequence Controller/SeqConTL.sv
 line:18: before: "package"
1: b'%Error: Cannot find file containing module: Controller,data/full_repos/permissive/146246005\n        ... Looked in:\n             data/full_repos/permissive/146246005/Sequence/Controller,data/full_repos/permissive/146246005\n             data/full_repos/permissive/146246005/Sequence/Controller,data/full_repos/permissive/146246005.v\n             data/full_repos/permissive/146246005/Sequence/Controller,data/full_repos/permissive/146246005.sv\n             Controller,data/full_repos/permissive/146246005\n             Controller,data/full_repos/permissive/146246005.v\n             Controller,data/full_repos/permissive/146246005.sv\n             obj_dir/Controller,data/full_repos/permissive/146246005\n             obj_dir/Controller,data/full_repos/permissive/146246005.v\n             obj_dir/Controller,data/full_repos/permissive/146246005.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/Sequence\n%Error: Cannot find file containing module: Controller/SeqConTL.sv\n%Error: Exiting due to 3 error(s)\n'
module toplevel(ADDR,OPCODE,I_FLAG,ZF,NF,OF,CF,IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS,CLK,RST,EN);

import cycle_package::*;
	input [6:0] ADDR;
	input [3:0] OPCODE;
	input I_FLAG,ZF,NF,OF,CF,RST,CLK,EN;
	output reg IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS;

    CYCLE PHASE;
	wire AASD_RST;
	
  sequence_controller seq_cont(ADDR,OPCODE,PHASE,I_FLAG,ZF,NF,OF,CF,IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS);
	
  AASD aasd_seq(AASD_RST,CLK,RST);
	
  phaser phase_gen(CLK,AASD_RST,EN,PHASE);
endmodule
module toplevel(ADDR,OPCODE,I_FLAG,ZF,NF,OF,CF,IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS,CLK,RST,EN);


import cycle_package::*;
	input [6:0] ADDR;
	input [3:0] OPCODE;
	input I_FLAG,ZF,NF,OF,CF,RST,CLK,EN;
	output reg IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS;

    CYCLE PHASE;
	wire AASD_RST;
	
  sequence_controller seq_cont(ADDR,OPCODE,PHASE,I_FLAG,ZF,NF,OF,CF,IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS);
	
  AASD aasd_seq(AASD_RST,CLK,RST);
	
  phaser phase_gen(CLK,AASD_RST,EN,PHASE);
endmodule