data/full_repos/permissive/102515926/Modules/MAIN_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk <= ~clk;     \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #20 rst <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #15 o <= 3; rst <= 1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #15 o <= 3; rst <= 1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #15 o <= 2; rst <= 0;  \n        ^\n%Error: data/full_repos/permissive/102515926/Modules/MAIN_TB.v:39: Cannot find file containing module: \'MAIN\'\n    MAIN #(DATAWIDTH) MAIN_1(a, b, c, d, e, f, g, h, i, j, k, l, m, n, a8_sel, o, clk, rst, p, p_amt, q, q_amt, r, s, a1, a2_gt, a2_lt, a2_eq, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12);\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/MAIN\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/MAIN.v\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/MAIN.sv\n             MAIN\n             MAIN.v\n             MAIN.sv\n             obj_dir/MAIN\n             obj_dir/MAIN.v\n             obj_dir/MAIN.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MAIN_TB();
    parameter DATAWIDTH = 8;

    reg [DATAWIDTH - 1:0] a, b; wire [DATAWIDTH - 1:0] a1;
    reg [DATAWIDTH - 1:0] c, d; wire a2_gt, a2_lt, a2_eq;
    reg [DATAWIDTH - 1:0] e; wire [DATAWIDTH - 1:0] a3;
    reg [DATAWIDTH - 1:0] f, g; wire [DATAWIDTH - 1:0] a4;
    reg [DATAWIDTH - 1:0] h; wire [DATAWIDTH - 1:0] a5;
    reg [DATAWIDTH - 1:0] i, j; wire [DATAWIDTH - 1:0] a6;
    reg [DATAWIDTH - 1:0] k, l; wire [DATAWIDTH - 1:0] a7;
    reg [DATAWIDTH - 1:0] m, n; reg a8_sel; wire [DATAWIDTH - 1:0] a8;
    reg [DATAWIDTH - 1:0] o; reg clk, rst; wire [DATAWIDTH - 1:0] a9;
    reg [DATAWIDTH - 1:0] p; reg [$clog2(DATAWIDTH) - 1:0] p_amt; wire [DATAWIDTH - 1:0] a10;
    reg [DATAWIDTH - 1:0] q; reg [$clog2(DATAWIDTH) - 1:0] q_amt; wire [DATAWIDTH - 1:0] a11;
    reg [DATAWIDTH - 1:0] r, s; wire [DATAWIDTH - 1:0] a12;

    MAIN #(DATAWIDTH) MAIN_1(a, b, c, d, e, f, g, h, i, j, k, l, m, n, a8_sel, o, clk, rst, p, p_amt, q, q_amt, r, s, a1, a2_gt, a2_lt, a2_eq, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12);

    always
        #10 clk <= ~clk;
   
    initial begin
        clk <= 0;
        rst <= 1;
        #20 rst <= 0;
        #10;
        a <= 1; b <= 2;
        c <= 4; d <= 3;
        e <= 4;
        f <= 6; g <= 3;
        h <= 5;
        i <= 7; j <= 3;
        k <= 4; l <= 2;
        m <= 2; n <= 3; a8_sel <= 1;
        o <= 4;
        #15 o <= 3; rst <= 1;
        #15 o <= 3; rst <= 1;
        #15 o <= 2; rst <= 0;
        p <= 1; p_amt <= 1;
        q <= 8; q_amt <= 2;
        r <= 5; s <= 4;
    end
endmodule
module MAIN_TB();

    parameter DATAWIDTH = 8;

    reg [DATAWIDTH - 1:0] a, b; wire [DATAWIDTH - 1:0] a1;
    reg [DATAWIDTH - 1:0] c, d; wire a2_gt, a2_lt, a2_eq;
    reg [DATAWIDTH - 1:0] e; wire [DATAWIDTH - 1:0] a3;
    reg [DATAWIDTH - 1:0] f, g; wire [DATAWIDTH - 1:0] a4;
    reg [DATAWIDTH - 1:0] h; wire [DATAWIDTH - 1:0] a5;
    reg [DATAWIDTH - 1:0] i, j; wire [DATAWIDTH - 1:0] a6;
    reg [DATAWIDTH - 1:0] k, l; wire [DATAWIDTH - 1:0] a7;
    reg [DATAWIDTH - 1:0] m, n; reg a8_sel; wire [DATAWIDTH - 1:0] a8;
    reg [DATAWIDTH - 1:0] o; reg clk, rst; wire [DATAWIDTH - 1:0] a9;
    reg [DATAWIDTH - 1:0] p; reg [$clog2(DATAWIDTH) - 1:0] p_amt; wire [DATAWIDTH - 1:0] a10;
    reg [DATAWIDTH - 1:0] q; reg [$clog2(DATAWIDTH) - 1:0] q_amt; wire [DATAWIDTH - 1:0] a11;
    reg [DATAWIDTH - 1:0] r, s; wire [DATAWIDTH - 1:0] a12;

    MAIN #(DATAWIDTH) MAIN_1(a, b, c, d, e, f, g, h, i, j, k, l, m, n, a8_sel, o, clk, rst, p, p_amt, q, q_amt, r, s, a1, a2_gt, a2_lt, a2_eq, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12);

    always
        #10 clk <= ~clk;
   
    initial begin
        clk <= 0;
        rst <= 1;
        #20 rst <= 0;
        #10;
        a <= 1; b <= 2;
        c <= 4; d <= 3;
        e <= 4;
        f <= 6; g <= 3;
        h <= 5;
        i <= 7; j <= 3;
        k <= 4; l <= 2;
        m <= 2; n <= 3; a8_sel <= 1;
        o <= 4;
        #15 o <= 3; rst <= 1;
        #15 o <= 3; rst <= 1;
        #15 o <= 2; rst <= 0;
        p <= 1; p_amt <= 1;
        q <= 8; q_amt <= 2;
        r <= 5; s <= 4;
    end
endmodule