data/full_repos/permissive/174323821/hdl/sdram/jtframe_gatecen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/174323821/hdl/sdram/jtframe_gatecen.v:63: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'miss_cnt\' generates 3 bits.\n                                                                                   : ... In instance jtframe_gatecen\n    if( miss_cnt && !cen && rec_en && !rom_cs )\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/174323821/hdl/sdram/jtframe_gatecen.v:77: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'miss_cnt\' generates 3 bits.\n                                                                                   : ... In instance jtframe_gatecen\n                if( miss_cnt ) miss_cnt <= miss_cnt - 3\'d1;\n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module jtframe_gatecen #(parameter ROMW=12 )(
    input             clk,
    input             rst,
    input             cen,
    input             rec_en,


    input  [ROMW-1:0] rom_addr,
    input             rom_cs,
    input             rom_ok,
    output            wait_cen
);

reg  [     1:0] last_cs;
reg  [ROMW-1:0] last_addr;
reg             waitn, rec, start;
reg  [     2:0] miss_cnt;
wire            new_addr = last_addr != rom_addr;

assign          wait_cen = cen & waitn | rec;

always @(*) begin
    rec = 0;
    if( miss_cnt && !cen && rec_en && !rom_cs )
        rec = 1;
end

always @(posedge clk, posedge rst) begin
    if( rst ) begin
        miss_cnt <= 3'd0;
    end else begin
        if( !start ) begin
            miss_cnt <= 3'd0;
        end else begin
            if( cen && !waitn ) begin
                if( ~&miss_cnt ) miss_cnt <= miss_cnt+3'd1;
            end else if( rec ) begin
                if( miss_cnt ) miss_cnt <= miss_cnt - 3'd1;
            end
        end
    end
end


always @(posedge clk) begin
    if( rst ) begin
        waitn     <= 1;
        last_cs   <= 0;
        last_addr <= {ROMW{1'b0}};
    end else begin
        last_cs   <= { last_cs[0] & ~new_addr, rom_cs };
        last_addr <= rom_addr;
        if( rom_cs && (!last_cs[0] || new_addr) ) waitn <= 0;
        else if( rom_ok && last_cs[1] ) begin
          waitn <= 1;
          start <= 1;
        end
    end
end

endmodule
module jtframe_gatecen #(parameter ROMW=12 )(
    input             clk,
    input             rst,
    input             cen,
    input             rec_en,


    input  [ROMW-1:0] rom_addr,
    input             rom_cs,
    input             rom_ok,
    output            wait_cen
);


reg  [     1:0] last_cs;
reg  [ROMW-1:0] last_addr;
reg             waitn, rec, start;
reg  [     2:0] miss_cnt;
wire            new_addr = last_addr != rom_addr;

assign          wait_cen = cen & waitn | rec;

always @(*) begin
    rec = 0;
    if( miss_cnt && !cen && rec_en && !rom_cs )
        rec = 1;
end

always @(posedge clk, posedge rst) begin
    if( rst ) begin
        miss_cnt <= 3'd0;
    end else begin
        if( !start ) begin
            miss_cnt <= 3'd0;
        end else begin
            if( cen && !waitn ) begin
                if( ~&miss_cnt ) miss_cnt <= miss_cnt+3'd1;
            end else if( rec ) begin
                if( miss_cnt ) miss_cnt <= miss_cnt - 3'd1;
            end
        end
    end
end


always @(posedge clk) begin
    if( rst ) begin
        waitn     <= 1;
        last_cs   <= 0;
        last_addr <= {ROMW{1'b0}};
    end else begin
        last_cs   <= { last_cs[0] & ~new_addr, rom_cs };
        last_addr <= rom_addr;
        if( rom_cs && (!last_cs[0] || new_addr) ) waitn <= 0;
        else if( rom_ok && last_cs[1] ) begin
          waitn <= 1;
          start <= 1;
        end
    end
end

endmodule