data/full_repos/permissive/160156109/mips-work/analysis.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160156109/mips-work/analysis.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #5 reset = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160156109/mips-work/analysis.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #5 reset = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160156109/mips-work/analysis.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #20 clk =~ clk;\n  ^\n%Error: data/full_repos/permissive/160156109/mips-work/analysis.v:12: Cannot find file containing module: \'regfile\'\n  regfile regfile1(clk, reset, busw, RegWr, ra, rb, rw, busa, busb, RegDst, rd);\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160156109/mips-work,data/full_repos/permissive/160156109/regfile\n             data/full_repos/permissive/160156109/mips-work,data/full_repos/permissive/160156109/regfile.v\n             data/full_repos/permissive/160156109/mips-work,data/full_repos/permissive/160156109/regfile.sv\n             regfile\n             regfile.v\n             regfile.sv\n             obj_dir/regfile\n             obj_dir/regfile.v\n             obj_dir/regfile.sv\n%Error: data/full_repos/permissive/160156109/mips-work/analysis.v:13: Cannot find file containing module: \'extender\'\n  extender extender1(imm, dout1, ExtOp);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/160156109/mips-work/analysis.v:14: Cannot find file containing module: \'mux\'\n  mux mux1(dout1, busb, dout2, ALUSrc);\n  ^~~\n%Error: data/full_repos/permissive/160156109/mips-work/analysis.v:16: Cannot find file containing module: \'alu\'\n  alu alu1(ALUctr, busa, dout2, zero, dout3);\n  ^~~\n%Error: data/full_repos/permissive/160156109/mips-work/analysis.v:17: Cannot find file containing module: \'dm\'\n  dm dm1(clk, reset, dout3, busb, dout4, WrEn);\n  ^~\n%Error: data/full_repos/permissive/160156109/mips-work/analysis.v:18: Cannot find file containing module: \'mux\'\n  mux mux2(dout4, dout3, busw, MemtoReg);\n  ^~~\n%Error: Exiting due to 6 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module analysis;

  reg clk, reset, RegDst, RegWr, ExtOp, ALUSrc, MemWr, MemtoReg, WrEn;
  reg [3:0] ALUctr;
  reg [15:0] imm;
  reg [4:0] ra, rb, rw, rd;
  
  wire zero;
  wire [31:0] busw, busa, busb, dout1, dout2, dout3, dout4, dout5;


  regfile regfile1(clk, reset, busw, RegWr, ra, rb, rw, busa, busb, RegDst, rd);
  extender extender1(imm, dout1, ExtOp);
  mux mux1(dout1, busb, dout2, ALUSrc);

  alu alu1(ALUctr, busa, dout2, zero, dout3);
  dm dm1(clk, reset, dout3, busb, dout4, WrEn);
  mux mux2(dout4, dout3, busw, MemtoReg);

  initial
  begin
    clk = 0; reset = 0; RegDst = 0; RegWr = 0; ExtOp = 0; ALUSrc = 0; MemWr = 0; MemtoReg = 0; WrEn = 0; ALUctr <= 4'b0000;

    #5 reset = 1;
     RegDst = 0;
      RegWr = 1;
       ExtOp = 1;
        ALUSrc = 1;
         ALUctr = 4'b0010;
          MemWr = 1;
           MemtoReg = 0;
            ra <= 5'b1;
             rb <= 5'b10;
              imm <= 16'h12;
    #5 reset = 0; 

  end

  always
  #20 clk =~ clk;

endmodule
module analysis;


  reg clk, reset, RegDst, RegWr, ExtOp, ALUSrc, MemWr, MemtoReg, WrEn;
  reg [3:0] ALUctr;
  reg [15:0] imm;
  reg [4:0] ra, rb, rw, rd;
  
  wire zero;
  wire [31:0] busw, busa, busb, dout1, dout2, dout3, dout4, dout5;


  regfile regfile1(clk, reset, busw, RegWr, ra, rb, rw, busa, busb, RegDst, rd);
  extender extender1(imm, dout1, ExtOp);
  mux mux1(dout1, busb, dout2, ALUSrc);

  alu alu1(ALUctr, busa, dout2, zero, dout3);
  dm dm1(clk, reset, dout3, busb, dout4, WrEn);
  mux mux2(dout4, dout3, busw, MemtoReg);

  initial
  begin
    clk = 0; reset = 0; RegDst = 0; RegWr = 0; ExtOp = 0; ALUSrc = 0; MemWr = 0; MemtoReg = 0; WrEn = 0; ALUctr <= 4'b0000;

    #5 reset = 1;
     RegDst = 0;
      RegWr = 1;
       ExtOp = 1;
        ALUSrc = 1;
         ALUctr = 4'b0010;
          MemWr = 1;
           MemtoReg = 0;
            ra <= 5'b1;
             rb <= 5'b10;
              imm <= 16'h12;
    #5 reset = 0; 

  end

  always
  #20 clk =~ clk;

endmodule