data/full_repos/permissive/167161024/four_bit_spi_tb.v
 line:67: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167161024/four_bit_spi_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #10   clock = ~clock;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/167161024/four_bit_spi_tb.v:39: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("four_bit_spi_tb.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/four_bit_spi_tb.v:40: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0, four_bit_spi_tb);\n   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/167161024/four_bit_spi_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n   #100 reset_n <= 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/four_bit_spi_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n   #10 bits_to_send <= 40;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/four_bit_spi_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n   #10 trigger <= 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/four_bit_spi_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n   #20 trigger <= 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/four_bit_spi_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n   # 1000 trigger <= 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/four_bit_spi_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n   # 20 trigger <= 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/four_bit_spi_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n   #10000\n   ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module four_bit_spi_tb;
   wire busy;
   wire cs;
   wire sclk;
   wire [3:0] sdio;

   reg 		 clock;
   reg 		 reset_n;
   reg 		 trigger;
   reg [5:0] bits_to_send;
   reg [63:0] data_input;

   reg 		  four_bit;
   
   
   four_bit_spi dut(

					.busy				(busy),
					.cs					(cs),
					.sclk				(sclk),
					.sdio				(sdio[3:0]),

					.clock				(clock),
					.reset_n			(reset_n),
					.trigger			(trigger),
					.four_bit			(four_bit),
					.bits_to_send		(bits_to_send[5:0]),
					.data_input			(data_input[63:0]));

   always begin
	  #10 	 clock = ~clock;
   end
   integer 	   i;


   initial begin
	  $dumpfile("four_bit_spi_tb.vcd");
	  $dumpvars(0, four_bit_spi_tb);
	  data_input = 0;
	  for(i = 0;i < 10; i = i+1)begin

		 data_input = data_input | (i & 4'hF) << (i << 2);
	  end


	  
	  $display("START");
	  clock <= 0;
	  reset_n <= 0;
	  four_bit <= 0;
	  #100 reset_n <= 1;

	  #10 bits_to_send <= 40;

	  #10 trigger <= 1;

	  #20 trigger <= 0;

	  # 1000 trigger <= 1;
	  bits_to_send <= 40;
	  four_bit <= 1;
	  # 20 trigger <= 0;
	  
	  #10000
		$display("END");
	  $finish;
	  
   end
   
   
endmodule
module four_bit_spi_tb;

   wire busy;
   wire cs;
   wire sclk;
   wire [3:0] sdio;

   reg 		 clock;
   reg 		 reset_n;
   reg 		 trigger;
   reg [5:0] bits_to_send;
   reg [63:0] data_input;

   reg 		  four_bit;
   
   
   four_bit_spi dut(

					.busy				(busy),
					.cs					(cs),
					.sclk				(sclk),
					.sdio				(sdio[3:0]),

					.clock				(clock),
					.reset_n			(reset_n),
					.trigger			(trigger),
					.four_bit			(four_bit),
					.bits_to_send		(bits_to_send[5:0]),
					.data_input			(data_input[63:0]));

   always begin
	  #10 	 clock = ~clock;
   end
   integer 	   i;


   initial begin
	  $dumpfile("four_bit_spi_tb.vcd");
	  $dumpvars(0, four_bit_spi_tb);
	  data_input = 0;
	  for(i = 0;i < 10; i = i+1)begin

		 data_input = data_input | (i & 4'hF) << (i << 2);
	  end


	  
	  $display("START");
	  clock <= 0;
	  reset_n <= 0;
	  four_bit <= 0;
	  #100 reset_n <= 1;

	  #10 bits_to_send <= 40;

	  #10 trigger <= 1;

	  #20 trigger <= 0;

	  # 1000 trigger <= 1;
	  bits_to_send <= 40;
	  four_bit <= 1;
	  # 20 trigger <= 0;
	  
	  #10000
		$display("END");
	  $finish;
	  
   end
   
   
endmodule