data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock_tb.v
 line:221: before: "#"
1: b'%Error: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock_tb.v:11: Cannot find include file: crossclock.v\n`include "crossclock.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab11/crossclock,data/full_repos/permissive/20270692/crossclock.v\n             data/full_repos/permissive/20270692/labs/lab11/crossclock,data/full_repos/permissive/20270692/crossclock.v.v\n             data/full_repos/permissive/20270692/labs/lab11/crossclock,data/full_repos/permissive/20270692/crossclock.v.sv\n             crossclock.v\n             crossclock.v.v\n             crossclock.v.sv\n             obj_dir/crossclock.v\n             obj_dir/crossclock.v.v\n             obj_dir/crossclock.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    forever #5 clkA=~clkA;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    forever #7 clkB=~clkB;\n            ^\n%Error: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock_tb.v:57: syntax error, unexpected \'@\'\n      @(posedge clkA or posedge clkB); begin  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #20 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #20 writeEnable = 1; writeMode = 1; inputPacket = {length{1\'b1}};\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #40\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #80 writeEnable = 0; writeMode = 0; readMode = 1; inputPacket = {bits{1\'b0}};\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #80 readMode = 0;\n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n'
module crossclock_tb(
    readMode,
    writeMode,
    inputPacket
);

  parameter bits = 8;

  output readMode, writeMode;
  reg readMode, writeMode;

  output [bits-1:0] inputPacket;
  reg [bits-1:0] inputPacket;

  reg clkA, clkB, rst;

  output [bits-1:0] outputPacket;
  wire [bits-1:0] outputPacket;

  reg writeEnable;

  crossclock FIFO(.wrEnable(writeEnable),
                  .inputData(inputPacket),
                  .outputData(outputPacket),
                  .clkA(clkA),
                  .clkB(clkB),
                  .rst(rst)
                  );

  initial
  begin
    clkA=0;
    forever #5 clkA=~clkA;
  end

  initial
  begin
    clkB=0;
    forever #7 clkB=~clkB;
  end

  initial
  begin
    forever begin
      @(posedge clkA or posedge clkB); begin
        $display("time=%04d RWE=%b%b%b I=%h O=%h clkA=%b clkB=%b", $time,
            readMode, writeMode, writeEnable, inputPacket, outputPacket, clkA, clkB);
      end
    end
  end

  initial
  begin

    $display("Resetting cross clock FIFO");
    rst = 1;
    writeEnable = 0;
    readMode = 0;
    writeMode = 0;
    inputPacket = {length{1'b0}};
    #20 rst = 0;
    #40
    #20 writeEnable = 1; writeMode = 1; inputPacket = {length{1'b1}};
    $display("Writing");
    #80 writeEnable = 0; writeMode = 0; readMode = 1; inputPacket = {bits{1'b0}};
    $display("Reading");
    #80 readMode = 0;
    if (outputPacket === {bits{1'b1}}) begin
      $display("Pass");
    end else begin
      $display("Fail");
    end
    $finish;
  end

endmodule
module crossclock_tb(
    readMode,
    writeMode,
    inputPacket
);


  parameter bits = 8;

  output readMode, writeMode;
  reg readMode, writeMode;

  output [bits-1:0] inputPacket;
  reg [bits-1:0] inputPacket;

  reg clkA, clkB, rst;

  output [bits-1:0] outputPacket;
  wire [bits-1:0] outputPacket;

  reg writeEnable;

  crossclock FIFO(.wrEnable(writeEnable),
                  .inputData(inputPacket),
                  .outputData(outputPacket),
                  .clkA(clkA),
                  .clkB(clkB),
                  .rst(rst)
                  );

  initial
  begin
    clkA=0;
    forever #5 clkA=~clkA;
  end

  initial
  begin
    clkB=0;
    forever #7 clkB=~clkB;
  end

  initial
  begin
    forever begin
      @(posedge clkA or posedge clkB); begin
        $display("time=%04d RWE=%b%b%b I=%h O=%h clkA=%b clkB=%b", $time,
            readMode, writeMode, writeEnable, inputPacket, outputPacket, clkA, clkB);
      end
    end
  end

  initial
  begin

    $display("Resetting cross clock FIFO");
    rst = 1;
    writeEnable = 0;
    readMode = 0;
    writeMode = 0;
    inputPacket = {length{1'b0}};
    #20 rst = 0;
    #40
    #20 writeEnable = 1; writeMode = 1; inputPacket = {length{1'b1}};
    $display("Writing");
    #80 writeEnable = 0; writeMode = 0; readMode = 1; inputPacket = {bits{1'b0}};
    $display("Reading");
    #80 readMode = 0;
    if (outputPacket === {bits{1'b1}}) begin
      $display("Pass");
    end else begin
      $display("Fail");
    end
    $finish;
  end

endmodule