data/full_repos/permissive/215648344/multiplicador_v3.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/215648344/multiplicador_v3.v:112: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'multiplicador\'\nmodule multiplicador (input clk, input [31:0] A, B, output [31:0] resultado, salida,dum, output [4:0] cuenta, output lsb);\n       ^~~~~~~~~~~~~\n                                                                              : ... Top module \'shift_reg\'\nmodule shift_reg(input [31:0] entrada, input clk, S, output [31:0] Z);\n       ^~~~~~~~~\n                                                                              : ... Top module \'shift_reg_s\'\nmodule shift_reg_s(input [31:0] entrada, input clk, S, output [31:0] Z);\n       ^~~~~~~~~~~\n                                                                              : ... Top module \'mux_init\'\nmodule mux_init( input [4:0] contador, input [31:0] ent , output [31:0] sal );\n       ^~~~~~~~\n                                                                              : ... Top module \'control_multplier\'\nmodule control_multplier(input [31:0] A, B, input clk, output [31:0] Y, output [4:0] Cuenta);\n       ^~~~~~~~~~~~~~~~~\n                                                                              : ... Top module \'control_multiplicand\'\nmodule control_multiplicand (input clk, S, input [31:0] E, output [31:0] Y);\n       ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/215648344/multiplicador_v3.v:20: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n                                                                          : ... In instance multiplicador\n  shift_out <= {8\'b0, B[15:0]};\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/215648344/multiplicador_v3.v:24: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n                                                                          : ... In instance multiplicador\n  aux_in <= {8\'b0, B[15:0]};\n         ^~\n%Error: Exiting due to 3 warning(s)\n'
module mux_init( input [4:0] contador, input [31:0] ent , output [31:0] sal );
reg[31:0] X;
  always @(contador, ent)
    begin
      case(contador)
        5'b00000: X = 32'd0;
        default: X = ent;
      endcase
    end
    assign sal = X;
endmodule
module mux_init( input [4:0] contador, input [31:0] ent , output [31:0] sal );

reg[31:0] X;
  always @(contador, ent)
    begin
      case(contador)
        5'b00000: X = 32'd0;
        default: X = ent;
      endcase
    end
    assign sal = X;
endmodule