data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/hard_macros_ql/Aurora/primitive_macros.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/hard_macros_ql/Aurora/primitive_macros.v:31: Multiple top level modules\n                                                                                                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                                                  : ... Top module \'ck_buff\'\nmodule ck_buff ( A , Q ) ;\n       ^~~~~~~\n                                                                                                                                                                  : ... Top module \'GCLKBUFF\'\nmodule GCLKBUFF ( A , Z ) ;\n       ^~~~~~~~\n                                                                                                                                                                  : ... Top module \'in_buff\'\nmodule in_buff ( A , Q ) ;\n       ^~~~~~~\n                                                                                                                                                                  : ... Top module \'out_buff\'\nmodule out_buff ( A , Q ) ;\n       ^~~~~~~~\n                                                                                                                                                                  : ... Top module \'inv\'\nmodule inv ( A , Q ) ;\n       ^~~\n                                                                                                                                                                  : ... Top module \'buff\'\nmodule buff ( A , Q ) ;\n       ^~~~\n                                                                                                                                                                  : ... Top module \'mux2x0\'\nmodule mux2x0 ( A , B, S, Q ) ;\n       ^~~~~~\n                                                                                                                                                                  : ... Top module \'LOGIC_Cell\'\nmodule LOGIC_Cell (T0I0, T0I1, T0I2, T0I3, B0I0, B0I1, B0I2, B0I3, \n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module in_buff ( A , Q );
input A;
output Q;


endmodule
module in_buff ( A , Q );

input A;
output Q;


endmodule