data/full_repos/permissive/127311496/src/v/SD/SDC_CRC.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/127311496/src/v/SD/SDC_CRC.v:19: Multiple top level modules\n                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                             : ... Top module \'SDC_CRC16\'\nmodule SDC_CRC16(\n       ^~~~~~~~~\n                                                                             : ... Top module \'SDC_CRC7\'\nmodule SDC_CRC7(\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module SDC_CRC16(
	input clk, input ce, input din,
	input clr, output crc_out
);
	reg [15:0] crc;
	wire crc_in = clr? 1'b0: crc_out ^ din;
	assign crc_out = crc[3] ^ crc[10] ^ crc[15];
	always @ (posedge clk)
	if(ce || clr) crc <= {crc[14:0], crc_in};
	
endmodule
module SDC_CRC16(
	input clk, input ce, input din,
	input clr, output crc_out
);

	reg [15:0] crc;
	wire crc_in = clr? 1'b0: crc_out ^ din;
	assign crc_out = crc[3] ^ crc[10] ^ crc[15];
	always @ (posedge clk)
	if(ce || clr) crc <= {crc[14:0], crc_in};
	
endmodule