data/full_repos/permissive/14193640/fpga/register_without_reset.v
data/verilator_xmls/47a9e127-4dfa-414f-9911-6d682e086de9.xml
module register_without_reset
  #(parameter WIDTH = 1)
   (
    input                  clk,
    input [WIDTH-1:0]      d,
    output reg [WIDTH-1:0] q
    );

   always @(posedge clk)
     q <= d;

endmodule
module register_without_reset
  #(parameter WIDTH = 1)
   (
    input                  clk,
    input [WIDTH-1:0]      d,
    output reg [WIDTH-1:0] q
    );


   always @(posedge clk)
     q <= d;

endmodule