data/full_repos/permissive/210250459/src/pc.v
data/verilator_xmls/718831ed-8f74-4f68-8e6f-d86edd6ba705.xml
module PC(out, in, clk);

output [31:0] out;
input [31:0] in;
input clk;

reg [31:0] pc;

initial
begin
    pc = 0;
end

assign out = pc;

always @(posedge clk) begin
    pc = in;
    $display($time, " [1 PC] Update = %d -----------------------------", in);
end

endmodule
module PC(out, in, clk);


output [31:0] out;
input [31:0] in;
input clk;

reg [31:0] pc;

initial
begin
    pc = 0;
end

assign out = pc;

always @(posedge clk) begin
    pc = in;
    $display($time, " [1 PC] Update = %d -----------------------------", in);
end

endmodule