data/full_repos/permissive/127217549/rtl/ramController.v
 line:57: before: "("
1: b"%Error: data/full_repos/permissive/127217549/rtl/ramController.v:45: Cannot find file containing module: 'flipFlopNbit'\n   flipFlopNbit #(\n   ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127217549/rtl,data/full_repos/permissive/127217549/flipFlopNbit\n             data/full_repos/permissive/127217549/rtl,data/full_repos/permissive/127217549/flipFlopNbit.v\n             data/full_repos/permissive/127217549/rtl,data/full_repos/permissive/127217549/flipFlopNbit.sv\n             flipFlopNbit\n             flipFlopNbit.v\n             flipFlopNbit.sv\n             obj_dir/flipFlopNbit\n             obj_dir/flipFlopNbit.v\n             obj_dir/flipFlopNbit.sv\n%Error: Exiting due to 1 error(s)\n"
module ramController (
		      input [8:0]   Ain,
		      input 	    OEin_n,
		      input 	    CASU_n,
		      input 	    CASL_n,
		      input 	    WE_n,
		      input 	    RAS_n,
		      output [17:0] Aout,
		      output 	    OEout_n,
		      output 	    UB_n,
		      output 	    LB_n,
		      output 	    CE_n
		      );
   

   reg ce_n;
   assign CE_n = ce_n;
   
   reg lb_n;
   reg ub_n;
   assign LB_n = lb_n;
   assign UB_n = ub_n;

   reg [17:0] addressOut = 18'd0;
   assign Aout = addressOut;
      



   assign OEout_n = OEin_n;
   

   parameter busWidth = 9;



   wire [(busWidth - 1):0] rowAddress;
     


    
   flipFlopNbit #(
		  busWidth
		  )
   rowLatch (
	     .D (Ain),
	     .clk (~RAS_n),
	     .reset_n (1'b1),
	     .Q (rowAddress)
	     );



   always @(negedge(RAS_n)) begin
      if(RAS_n == 1'b0) begin
	 ce_n <= 1'b0;
      end
      else begin
	 ce_n <= 1'b1;
      end
   end




   always @(negedge(CASU_n), negedge(CASL_n)) begin
      if(CASU_n == 1'b0) begin
	 ub_n = 1'b0;
      end
      else begin
	 ub_n = 1'b1;
      end

      if(CASL_n == 1'b0) begin
	 lb_n = 1'b0;
      end
      else begin
	 lb_n = 1'b1;
      end
   end
   
   always @(negedge(CASU_n), negedge(CASL_n)) begin
      addressOut [8:0] = rowAddress;
      addressOut [17:9] = Ain;
   end
   
   
 endmodule
module ramController (
		      input [8:0]   Ain,
		      input 	    OEin_n,
		      input 	    CASU_n,
		      input 	    CASL_n,
		      input 	    WE_n,
		      input 	    RAS_n,
		      output [17:0] Aout,
		      output 	    OEout_n,
		      output 	    UB_n,
		      output 	    LB_n,
		      output 	    CE_n
		      );

   

   reg ce_n;
   assign CE_n = ce_n;
   
   reg lb_n;
   reg ub_n;
   assign LB_n = lb_n;
   assign UB_n = ub_n;

   reg [17:0] addressOut = 18'd0;
   assign Aout = addressOut;
      



   assign OEout_n = OEin_n;
   

   parameter busWidth = 9;



   wire [(busWidth - 1):0] rowAddress;
     


    
   flipFlopNbit #(
		  busWidth
		  )
   rowLatch (
	     .D (Ain),
	     .clk (~RAS_n),
	     .reset_n (1'b1),
	     .Q (rowAddress)
	     );



   always @(negedge(RAS_n)) begin
      if(RAS_n == 1'b0) begin
	 ce_n <= 1'b0;
      end
      else begin
	 ce_n <= 1'b1;
      end
   end




   always @(negedge(CASU_n), negedge(CASL_n)) begin
      if(CASU_n == 1'b0) begin
	 ub_n = 1'b0;
      end
      else begin
	 ub_n = 1'b1;
      end

      if(CASL_n == 1'b0) begin
	 lb_n = 1'b0;
      end
      else begin
	 lb_n = 1'b1;
      end
   end
   
   always @(negedge(CASU_n), negedge(CASL_n)) begin
      addressOut [8:0] = rowAddress;
      addressOut [17:9] = Ain;
   end
   
   
 endmodule