data/full_repos/permissive/177233467/hazard_detect.v
1: b'%Warning-WIDTH: data/full_repos/permissive/177233467/hazard_detect.v:149: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 16 bits.\n                                                                        : ... In instance hazard_detect\n  if (rf_def_mem & rf_use_ex) begin\n  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/177233467/hazard_detect.v:156: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 16 bits.\n                                                                        : ... In instance hazard_detect\n  if (rf_def_wb & rf_use_ex) begin\n  ^~\n%Warning-WIDTH: data/full_repos/permissive/177233467/hazard_detect.v:163: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 16 bits.\n                                                                        : ... In instance hazard_detect\n  if (rf_def_wb & rf_use_mem) begin\n  ^~\n%Error: Exiting due to 3 warning(s)\n'
module hazard_detect(
    input wire [7:0] mf_ex, mf_mem, mf_wb,
    input wire [(3*reg_addr_width+3)-1:0] rf_ex, rf_mem, rf_wb,
    input wire vf_mem, vf_wb,

    output wire [5:0] fwd_flags,
    output reg [nreg-1:0] rf_use_ex, rf_use_mem,
    output reg [nreg-1:0] rf_def_mem, rf_def_wb 
);
parameter nreg = 16;
parameter reg_addr_width = 4;





always @(*) begin

  rf_use_ex = 16'b0;
  rf_use_mem = 16'b0;

  rf_def_mem = 16'b0;
  rf_def_wb = 16'b0;



  rf_use_ex[rf_ex[3:0]] = rf_ex[12] ? 1'b1 : 1'b0;
  rf_use_ex[rf_ex[7:4]] = rf_ex[13] ? 1'b1 : 1'b0;
  rf_use_mem[rf_mem[3:0]] = rf_mem[12] ? 1'b1 : 1'b0;
  rf_use_mem[rf_mem[7:4]] = rf_mem[13] ? 1'b1: 1'b0;




  rf_def_mem[rf_mem[11:8]] = rf_mem[14] ? 1'b1 : 1'b0;
  rf_def_wb[rf_wb[11:8]] = rf_wb[14] ? 1'b1 : 1'b0;


end

  reg [1:0] fwd_mem_ex, fwd_wb_ex, fwd_wb_mem;
always @(*) begin
  fwd_mem_ex = 2'b0;
  fwd_wb_ex = 2'b0;
  fwd_wb_mem = 2'b0;






  if (rf_def_mem & rf_use_ex) begin
    fwd_mem_ex = vf_mem & mf_mem[0] ?
              {rf_mem[11:8] == rf_ex[7:4], rf_mem[11:8] == rf_ex[3:0]} : 
              2'b0;
  end
  

  if (rf_def_wb & rf_use_ex) begin
    fwd_wb_ex = vf_wb & mf_wb[0] ?
              {rf_wb[11:8] == rf_ex[7:4], rf_wb[11:8] == rf_ex[3:0]} : 
              2'b0;
  end


  if (rf_def_wb & rf_use_mem) begin
    fwd_wb_mem = vf_wb & mf_wb[0] ?
              {rf_wb[11:8] == rf_mem[7:4], rf_wb[11:8] == rf_mem[3:0]} : 
              2'b0;
  end

end

assign fwd_flags = {fwd_wb_mem, fwd_wb_ex, fwd_mem_ex};
endmodule
module hazard_detect(
    input wire [7:0] mf_ex, mf_mem, mf_wb,
    input wire [(3*reg_addr_width+3)-1:0] rf_ex, rf_mem, rf_wb,
    input wire vf_mem, vf_wb,

    output wire [5:0] fwd_flags,
    output reg [nreg-1:0] rf_use_ex, rf_use_mem,
    output reg [nreg-1:0] rf_def_mem, rf_def_wb 
);

parameter nreg = 16;
parameter reg_addr_width = 4;





always @(*) begin

  rf_use_ex = 16'b0;
  rf_use_mem = 16'b0;

  rf_def_mem = 16'b0;
  rf_def_wb = 16'b0;



  rf_use_ex[rf_ex[3:0]] = rf_ex[12] ? 1'b1 : 1'b0;
  rf_use_ex[rf_ex[7:4]] = rf_ex[13] ? 1'b1 : 1'b0;
  rf_use_mem[rf_mem[3:0]] = rf_mem[12] ? 1'b1 : 1'b0;
  rf_use_mem[rf_mem[7:4]] = rf_mem[13] ? 1'b1: 1'b0;




  rf_def_mem[rf_mem[11:8]] = rf_mem[14] ? 1'b1 : 1'b0;
  rf_def_wb[rf_wb[11:8]] = rf_wb[14] ? 1'b1 : 1'b0;


end

  reg [1:0] fwd_mem_ex, fwd_wb_ex, fwd_wb_mem;
always @(*) begin
  fwd_mem_ex = 2'b0;
  fwd_wb_ex = 2'b0;
  fwd_wb_mem = 2'b0;






  if (rf_def_mem & rf_use_ex) begin
    fwd_mem_ex = vf_mem & mf_mem[0] ?
              {rf_mem[11:8] == rf_ex[7:4], rf_mem[11:8] == rf_ex[3:0]} : 
              2'b0;
  end
  

  if (rf_def_wb & rf_use_ex) begin
    fwd_wb_ex = vf_wb & mf_wb[0] ?
              {rf_wb[11:8] == rf_ex[7:4], rf_wb[11:8] == rf_ex[3:0]} : 
              2'b0;
  end


  if (rf_def_wb & rf_use_mem) begin
    fwd_wb_mem = vf_wb & mf_wb[0] ?
              {rf_wb[11:8] == rf_mem[7:4], rf_wb[11:8] == rf_mem[3:0]} : 
              2'b0;
  end

end

assign fwd_flags = {fwd_wb_mem, fwd_wb_ex, fwd_mem_ex};
endmodule