data/full_repos/permissive/150947952/scratch/fpga-md5/swedishhat/hardware/cross_domain_buffer.v
 line:5: before: "="
data/verilator_xmls/dc05e824-54a3-4418-b489-e011f4e46604.xml
module cross_domain_buffer(
   input wire clk,
	input wire [31:0] in,
	input wire save,	
	output reg [31:0] out = 0,
   output wire saved
);

always @(posedge save) 
   begin
      out <= in;      
   end

reg [1:0] syncSaved;
   
always @(posedge clk)
   begin
      syncSaved[0] <= save;
      syncSaved[1] <= syncSaved[0];
   end
 
 assign saved = syncSaved[1];

endmodule
module cross_domain_buffer(
   input wire clk,
	input wire [31:0] in,
	input wire save,	
	output reg [31:0] out = 0,
   output wire saved
);


always @(posedge save) 
   begin
      out <= in;      
   end

reg [1:0] syncSaved;
   
always @(posedge clk)
   begin
      syncSaved[0] <= save;
      syncSaved[1] <= syncSaved[0];
   end
 
 assign saved = syncSaved[1];

endmodule