data/full_repos/permissive/102564818/UART.v
1: b"%Error: data/full_repos/permissive/102564818/UART.v:22: Cannot find file containing module: 'Transmitter'\n    Transmitter T1( .CLK(CLK), \n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/Transmitter\n             data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/Transmitter.v\n             data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/Transmitter.sv\n             Transmitter\n             Transmitter.v\n             Transmitter.sv\n             obj_dir/Transmitter\n             obj_dir/Transmitter.v\n             obj_dir/Transmitter.sv\n%Error: data/full_repos/permissive/102564818/UART.v:32: Cannot find file containing module: 'Receiver'\n    Receiver R1(    .CLK(CLK),\n    ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module UART(CLK, RST, BaudRate, ParityMode, StopBits, Tx, Rx, Error);
    input CLK;
    input RST;
    input[1:0] BaudRate;
    input[1:0] ParityMode;
    input StopBits;
    output Tx;
    input Rx;
    output Error;
    
    wire TxBusy;
    
    wire[7:0] RxData;
    wire RxDataReady;
    
    Transmitter T1( .CLK(CLK), 
                    .RST(RST), 
                    .BaudRate(BaudRate), 
                    .ParityMode(ParityMode), 
                    .StopBits(StopBits),
                    .TxBegin(RxDataReady),
                    .TxData(RxData),
                    .TxBusy(TxBusy),
                    .Tx(Tx));
                    
    Receiver R1(    .CLK(CLK),
                    .RST(RST),
                    .BaudRate(BaudRate),
                    .ParityMode(ParityMode),
                    .StopBits(StopBits),
                    .Rx(Rx),
                    .RxData(RxData),
                    .RxDataReady(RxDataReady),
                    .Error(Error));
                    
endmodule
module UART(CLK, RST, BaudRate, ParityMode, StopBits, Tx, Rx, Error);

    input CLK;
    input RST;
    input[1:0] BaudRate;
    input[1:0] ParityMode;
    input StopBits;
    output Tx;
    input Rx;
    output Error;
    
    wire TxBusy;
    
    wire[7:0] RxData;
    wire RxDataReady;
    
    Transmitter T1( .CLK(CLK), 
                    .RST(RST), 
                    .BaudRate(BaudRate), 
                    .ParityMode(ParityMode), 
                    .StopBits(StopBits),
                    .TxBegin(RxDataReady),
                    .TxData(RxData),
                    .TxBusy(TxBusy),
                    .Tx(Tx));
                    
    Receiver R1(    .CLK(CLK),
                    .RST(RST),
                    .BaudRate(BaudRate),
                    .ParityMode(ParityMode),
                    .StopBits(StopBits),
                    .Rx(Rx),
                    .RxData(RxData),
                    .RxDataReady(RxDataReady),
                    .Error(Error));
                    
endmodule