data/full_repos/permissive/172705897/verilog/adder.v
data/verilator_xmls/44e29cbe-4ca7-4ac1-a31d-5975c6559083.xml
module adder(input1, input2, out);
	input [31:0]	input1;
	input [31:0]	input2;
	output [31:0]	out;

	assign		out = input1 + input2;
endmodule
module adder(input1, input2, out);

	input [31:0]	input1;
	input [31:0]	input2;
	output [31:0]	out;

	assign		out = input1 + input2;
endmodule