data/full_repos/permissive/143278/ivltests/mixed_type_div_mod.v
data/verilator_xmls/bcd4e64d-99f1-45c8-ba6d-2c1508b416bc.xml
module top;
  reg pass;
  real result;
  initial begin
    pass = 1'b1;


    result = 1/2.0;
    if (result != 0.5) begin
      $display("Failed: int/real, expected 0.5, got %g", result);
      pass = 1'b0;
    end


    result = 1.0/2;
    if (result != 0.5) begin
      $display("Failed: real/int, expected 0.5, got %g", result);
      pass = 1'b0;
    end

`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST

    result = 1%2.0;
    if (result != 1.0) begin
      $display("Failed: int%%real, expected 1.0, got %g", result);
      pass = 1'b0;
    end


    result = 1.0%2;
    if (result != 1.0) begin
      $display("Failed: real%%int, expected 1.0, got %g", result);
      pass = 1'b0;
    end
`endif

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  real result;
  initial begin
    pass = 1'b1;


    result = 1/2.0;
    if (result != 0.5) begin
      $display("Failed: int/real, expected 0.5, got %g", result);
      pass = 1'b0;
    end


    result = 1.0/2;
    if (result != 0.5) begin
      $display("Failed: real/int, expected 0.5, got %g", result);
      pass = 1'b0;
    end

`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST

    result = 1%2.0;
    if (result != 1.0) begin
      $display("Failed: int%%real, expected 1.0, got %g", result);
      pass = 1'b0;
    end


    result = 1.0%2;
    if (result != 1.0) begin
      $display("Failed: real%%int, expected 1.0, got %g", result);
      pass = 1'b0;
    end
`endif

    if (pass) $display("PASSED");
  end
endmodule