data/full_repos/permissive/173003307/src/timer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/173003307/src/timer.v:108: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'InterruptRate\' generates 8 bits.\n                                                                    : ... In instance timer\n        else if((LastTime + InterruptRate) == Timer) \n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module timer(

    input CLK,
    input RESET,

    inout [7:0] BUS_DATA,
    input [7:0] BUS_ADDR,
    input BUS_WE,
    output BUS_INTERRUPT_RAISE,
    input BUS_INTERRUPT_ACK
     );
    parameter [7:0] TimerBaseAddr = 8'hF0;
    parameter InitialIterruptRate = 100;
    parameter InitialIterruptEnable = 1'b1;











    reg [7:0] InterruptRate;
    
    always@(posedge CLK) begin
        if(RESET)
            InterruptRate <= InitialIterruptRate;
        else if((BUS_ADDR == TimerBaseAddr + 8'h01) & BUS_WE)
            InterruptRate <= BUS_DATA;
    end


    
    reg InterruptEnable;
    always@(posedge CLK) begin
        if(RESET)
            InterruptEnable <= InitialIterruptEnable;
        else if((BUS_ADDR == TimerBaseAddr + 8'h03) & BUS_WE) 
            InterruptEnable <= BUS_DATA[0];
    end

    
    reg [31:0] DownCounter;
    always@(posedge CLK) begin
        if(RESET)
            DownCounter <= 0;
        else 
        begin
            if(DownCounter == 32'd99999)
                DownCounter <= 0;
            else
                DownCounter <= DownCounter + 1'b1;
        end
    end



    
    reg [31:0] Timer;
    
    always@(posedge CLK) begin
        if(RESET | (BUS_ADDR == TimerBaseAddr + 8'h02))
            Timer <= 0;
        else 
        begin
            if((DownCounter == 0))
                Timer <= Timer + 1'b1;
            else
                Timer <= Timer;
        end
    end

    
    reg TargetReached;
    reg [31:0] LastTime;
    
    always@(posedge CLK) begin
        if(RESET) 
        begin
            TargetReached <= 1'b0;
            LastTime <= 0;
        end 
        else if((LastTime + InterruptRate) == Timer) 
        begin
            if(InterruptEnable)
                TargetReached <= 1'b1;
            
            LastTime <= Timer;
        end 
        else
            TargetReached <= 1'b0;
        end

    reg Interrupt;
    
    always@(posedge CLK) begin
        if(RESET)
            Interrupt <= 1'b0;
        else if(TargetReached)
            Interrupt <= 1'b1;
        else if(BUS_INTERRUPT_ACK)
            Interrupt <= 1'b0;
    end
    
    assign BUS_INTERRUPT_RAISE = Interrupt;

    
    reg TransmitTimerValue;
    
    always@(posedge CLK) begin
        if(BUS_ADDR == TimerBaseAddr)
            TransmitTimerValue <= 1'b1;
        else
            TransmitTimerValue <= 1'b0;
        end
    
    assign BUS_DATA = (TransmitTimerValue) ? Timer[7:0] : 8'hZZ;
    
    
    endmodule
module timer(

    input CLK,
    input RESET,

    inout [7:0] BUS_DATA,
    input [7:0] BUS_ADDR,
    input BUS_WE,
    output BUS_INTERRUPT_RAISE,
    input BUS_INTERRUPT_ACK
     );

    parameter [7:0] TimerBaseAddr = 8'hF0;
    parameter InitialIterruptRate = 100;
    parameter InitialIterruptEnable = 1'b1;











    reg [7:0] InterruptRate;
    
    always@(posedge CLK) begin
        if(RESET)
            InterruptRate <= InitialIterruptRate;
        else if((BUS_ADDR == TimerBaseAddr + 8'h01) & BUS_WE)
            InterruptRate <= BUS_DATA;
    end


    
    reg InterruptEnable;
    always@(posedge CLK) begin
        if(RESET)
            InterruptEnable <= InitialIterruptEnable;
        else if((BUS_ADDR == TimerBaseAddr + 8'h03) & BUS_WE) 
            InterruptEnable <= BUS_DATA[0];
    end

    
    reg [31:0] DownCounter;
    always@(posedge CLK) begin
        if(RESET)
            DownCounter <= 0;
        else 
        begin
            if(DownCounter == 32'd99999)
                DownCounter <= 0;
            else
                DownCounter <= DownCounter + 1'b1;
        end
    end



    
    reg [31:0] Timer;
    
    always@(posedge CLK) begin
        if(RESET | (BUS_ADDR == TimerBaseAddr + 8'h02))
            Timer <= 0;
        else 
        begin
            if((DownCounter == 0))
                Timer <= Timer + 1'b1;
            else
                Timer <= Timer;
        end
    end

    
    reg TargetReached;
    reg [31:0] LastTime;
    
    always@(posedge CLK) begin
        if(RESET) 
        begin
            TargetReached <= 1'b0;
            LastTime <= 0;
        end 
        else if((LastTime + InterruptRate) == Timer) 
        begin
            if(InterruptEnable)
                TargetReached <= 1'b1;
            
            LastTime <= Timer;
        end 
        else
            TargetReached <= 1'b0;
        end

    reg Interrupt;
    
    always@(posedge CLK) begin
        if(RESET)
            Interrupt <= 1'b0;
        else if(TargetReached)
            Interrupt <= 1'b1;
        else if(BUS_INTERRUPT_ACK)
            Interrupt <= 1'b0;
    end
    
    assign BUS_INTERRUPT_RAISE = Interrupt;

    
    reg TransmitTimerValue;
    
    always@(posedge CLK) begin
        if(BUS_ADDR == TimerBaseAddr)
            TransmitTimerValue <= 1'b1;
        else
            TransmitTimerValue <= 1'b0;
        end
    
    assign BUS_DATA = (TransmitTimerValue) ? Timer[7:0] : 8'hZZ;
    
    
    endmodule