data/full_repos/permissive/202237519/verilog/digitalsystem6/d_ff_tb.v
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/d_ff_tb.v:1: Cannot find include file: d_ff.v\n`include "d_ff.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/d_ff.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/d_ff.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/d_ff.v.sv\n             d_ff.v\n             d_ff.v.v\n             d_ff.v.sv\n             obj_dir/d_ff.v\n             obj_dir/d_ff.v.v\n             obj_dir/d_ff.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/d_ff_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/d_ff_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("d_ff_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/d_ff_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,d_ff_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/d_ff_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    D <= 0; #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/d_ff_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    D <= 0; #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/d_ff_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    D <= 1; #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/d_ff_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    D <= 1; #10;\n            ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module d_ff_tb;

reg clk, D, set;
wire Q, nQ;

always #2.5 clk <= ~clk;

D_FF d_ff(clk,D,set,Q,nQ);

initial begin
    $dumpfile("d_ff_tb.vcd");
    $dumpvars(0,d_ff_tb);
    clk <= 1; set <= 0;
    D <= 0; #10;
    D <= 0; #10;
    D <= 1; #10;
    D <= 1; #10;
    $finish;
    end


endmodule
module d_ff_tb;


reg clk, D, set;
wire Q, nQ;

always #2.5 clk <= ~clk;

D_FF d_ff(clk,D,set,Q,nQ);

initial begin
    $dumpfile("d_ff_tb.vcd");
    $dumpvars(0,d_ff_tb);
    clk <= 1; set <= 0;
    D <= 0; #10;
    D <= 0; #10;
    D <= 1; #10;
    D <= 1; #10;
    $finish;
    end


endmodule