data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v
1: b'%Warning-WIDTH: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:42: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 37 bits.\n                                                                                : ... In instance mips\n   assign shamt = {32\'b0, instr[10:6]};  \n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:44: Cannot find file containing module: \'ctrl\'\n   ctrl U_CTRL(\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/131249673/MIPS_L_MultiCycle,data/full_repos/permissive/131249673/ctrl\n             data/full_repos/permissive/131249673/MIPS_L_MultiCycle,data/full_repos/permissive/131249673/ctrl.v\n             data/full_repos/permissive/131249673/MIPS_L_MultiCycle,data/full_repos/permissive/131249673/ctrl.sv\n             ctrl\n             ctrl.v\n             ctrl.sv\n             obj_dir/ctrl\n             obj_dir/ctrl.v\n             obj_dir/ctrl.sv\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:49: Cannot find file containing module: \'PC\'\n   PC U_PC (\n   ^~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:54: Cannot find file containing module: \'im_4k\'\n   im_4k U_IM ( \n   ^~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:59: Cannot find file containing module: \'IR\'\n   IR U_IR ( \n   ^~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:64: Cannot find file containing module: \'mux4\'\n   mux4 #(.WIDTH(5)) RF_MUX (\n   ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:69: Cannot find file containing module: \'RF\'\n   RF U_RF (\n   ^~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:75: Cannot find file containing module: \'EXT\'\n   EXT U_EXT ( \n   ^~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:80: Cannot find file containing module: \'flopr\'\n   flopr #(.WIDTH(32)) U_RD1_r (\n   ^~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:85: Cannot find file containing module: \'flopr\'\n   flopr #(.WIDTH(32)) U_RD2_r (\n   ^~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:91: Cannot find file containing module: \'NPC\'\n   NPC U_NPC (\n   ^~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:96: Cannot find file containing module: \'mux4\'\n   mux4 #(.WIDTH(32)) A_MUX (\n   ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:102: Cannot find file containing module: \'mux2\'\n   mux2 #(.WIDTH(32)) B_MUX (\n   ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:107: Cannot find file containing module: \'alu\'\n   alu U_ALU ( \n   ^~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:112: Cannot find file containing module: \'flopr\'\n   flopr #(.WIDTH(32)) U_C_r (\n   ^~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:118: Cannot find file containing module: \'dm_4k\'\n   dm_4k U_DM ( \n   ^~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:123: Cannot find file containing module: \'flopr\'\n   flopr #(.WIDTH(32)) U_DM_r (\n   ^~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/mips.v:129: Cannot find file containing module: \'mux4\'\n   mux4 #(.WIDTH(32)) WD_MUX (\n   ^~~~\n%Error: Exiting due to 17 error(s), 1 warning(s)\n'
module mips( clk, rst );
   input   clk;
   input   rst;
   
   wire 		     RFWr;
   wire 		     DMWr;
   wire 		     PCWr;
   wire 		     IRWr;
   wire [1:0]  EXTOp;
   wire [4:0]  ALUOp;
   wire [1:0]  NPCOp;
   wire [1:0]  GPRSel;
   wire [1:0]  WDSel;
   wire [1:0]  ASel;
   wire 		     BSel;
   wire 		     Zero;
   wire [29:0] PC, NPC;
   wire [31:0] im_dout, dm_dout, dm_dout_r;
   wire [31:0] DR_out;
   wire [31:0] instr;
   wire [4:0]  rs;
   wire [4:0]  rt;
   wire [4:0]  rd;
   wire [4:0]  shamt;
   wire [5:0]  Op;
   wire [5:0]  Funct;
   wire [15:0] Imm16; 
   wire [31:0] Imm32;
   wire [25:0] IMM;
   wire [4:0]  A3;
   wire [31:0] WD;
   wire [31:0] RD1, RD1_r, RD2, RD2_r;
   wire [31:0] A, B, C, C_r;
   
   assign Op = instr[31:26];
   assign Funct = instr[5:0];
   assign rs = instr[25:21];
   assign rt = instr[20:16];
   assign rd = instr[15:11];
   assign Imm16 = instr[15:0];
   assign IMM = instr[25:0];
   assign shamt = {32'b0, instr[10:6]};

   ctrl U_CTRL(
      .clk(clk),	.rst(rst), .Zero(Zero), .Op(Op), .Funct(Funct), .RFWr(RFWr), .DMWr(DMWr), .PCWr(PCWr), .IRWr(IRWr), .EXTOp(EXTOp), .ALUOp(ALUOp), .NPCOp(NPCOp), .GPRSel(GPRSel), .WDSel(WDSel), .ASel(ASel), .BSel(BSel)
   );
   

   PC U_PC (
      .clk(clk), .rst(rst), .PCWr(PCWr), .NPC(NPC), .PC(PC)
   ); 
   

   im_4k U_IM ( 
      .addr(PC[9:0]) , .dout(im_dout)
   );
   

   IR U_IR ( 
      .clk(clk), .rst(rst), .IRWr(IRWr), .im_dout(im_dout), .instr(instr)
   );
   

   mux4 #(.WIDTH(5)) RF_MUX (
      .d0(rd), .d1(rt), .d2(5'd31), .s(GPRSel), .y(A3)
   );
   

   RF U_RF (
      .A1(rs), .A2(rt), .A3(A3), .WD(WD), .clk(clk), 
      .RFWr(RFWr), .RD1(RD1), .RD2(RD2)
   );
   

   EXT U_EXT ( 
      .Imm16(Imm16), .EXTOp(EXTOp), .Imm32(Imm32) 
   );
   

   flopr #(.WIDTH(32)) U_RD1_r (
      .clk(clk), .rst(rst), .d(RD1), .q(RD1_r)
   );
   

   flopr #(.WIDTH(32)) U_RD2_r (
      .clk(clk), .rst(rst), .d(RD2), .q(RD2_r)
   );
   


   NPC U_NPC (
      .PC(PC), .NPCOp(NPCOp), .IMM(IMM), .NPC(NPC), .JMPR(RD1_r >> 2'b10)
   );
   

   mux4 #(.WIDTH(32)) A_MUX (
      .d0(RD1_r), .d1(5'b10000), .d2(shamt), .d3(1'b0), .s(ASel), .y(A)
   );
   
      

   mux2 #(.WIDTH(32)) B_MUX (
      .d0(RD2_r), .d1(Imm32), .s(BSel), .y(B)
   );
   

   alu U_ALU ( 
      .A(A), .B(B), .ALUOp(ALUOp), .C(C), .Compare(Zero)
   );
   

   flopr #(.WIDTH(32)) U_C_r (
      .clk(clk), .rst(rst), .d(C), .q(C_r)
   );
   


   dm_4k U_DM ( 
      .addr(C_r[11:2]), .din(RD2_r), .be(4'b1111), .DMWr(DMWr), .clk(clk), .dout(dm_dout)
   );
   

   flopr #(.WIDTH(32)) U_DM_r (
      .clk(clk), .rst(rst), .d(dm_dout), .q(DR_out)
   );
   


   mux4 #(.WIDTH(32)) WD_MUX (
      .d0(C_r), .d1(DR_out), .d2({PC, 2'b00}), .d3(0), .s(WDSel), .y(WD)
   );
endmodule
module mips( clk, rst );

   input   clk;
   input   rst;
   
   wire 		     RFWr;
   wire 		     DMWr;
   wire 		     PCWr;
   wire 		     IRWr;
   wire [1:0]  EXTOp;
   wire [4:0]  ALUOp;
   wire [1:0]  NPCOp;
   wire [1:0]  GPRSel;
   wire [1:0]  WDSel;
   wire [1:0]  ASel;
   wire 		     BSel;
   wire 		     Zero;
   wire [29:0] PC, NPC;
   wire [31:0] im_dout, dm_dout, dm_dout_r;
   wire [31:0] DR_out;
   wire [31:0] instr;
   wire [4:0]  rs;
   wire [4:0]  rt;
   wire [4:0]  rd;
   wire [4:0]  shamt;
   wire [5:0]  Op;
   wire [5:0]  Funct;
   wire [15:0] Imm16; 
   wire [31:0] Imm32;
   wire [25:0] IMM;
   wire [4:0]  A3;
   wire [31:0] WD;
   wire [31:0] RD1, RD1_r, RD2, RD2_r;
   wire [31:0] A, B, C, C_r;
   
   assign Op = instr[31:26];
   assign Funct = instr[5:0];
   assign rs = instr[25:21];
   assign rt = instr[20:16];
   assign rd = instr[15:11];
   assign Imm16 = instr[15:0];
   assign IMM = instr[25:0];
   assign shamt = {32'b0, instr[10:6]};

   ctrl U_CTRL(
      .clk(clk),	.rst(rst), .Zero(Zero), .Op(Op), .Funct(Funct), .RFWr(RFWr), .DMWr(DMWr), .PCWr(PCWr), .IRWr(IRWr), .EXTOp(EXTOp), .ALUOp(ALUOp), .NPCOp(NPCOp), .GPRSel(GPRSel), .WDSel(WDSel), .ASel(ASel), .BSel(BSel)
   );
   

   PC U_PC (
      .clk(clk), .rst(rst), .PCWr(PCWr), .NPC(NPC), .PC(PC)
   ); 
   

   im_4k U_IM ( 
      .addr(PC[9:0]) , .dout(im_dout)
   );
   

   IR U_IR ( 
      .clk(clk), .rst(rst), .IRWr(IRWr), .im_dout(im_dout), .instr(instr)
   );
   

   mux4 #(.WIDTH(5)) RF_MUX (
      .d0(rd), .d1(rt), .d2(5'd31), .s(GPRSel), .y(A3)
   );
   

   RF U_RF (
      .A1(rs), .A2(rt), .A3(A3), .WD(WD), .clk(clk), 
      .RFWr(RFWr), .RD1(RD1), .RD2(RD2)
   );
   

   EXT U_EXT ( 
      .Imm16(Imm16), .EXTOp(EXTOp), .Imm32(Imm32) 
   );
   

   flopr #(.WIDTH(32)) U_RD1_r (
      .clk(clk), .rst(rst), .d(RD1), .q(RD1_r)
   );
   

   flopr #(.WIDTH(32)) U_RD2_r (
      .clk(clk), .rst(rst), .d(RD2), .q(RD2_r)
   );
   


   NPC U_NPC (
      .PC(PC), .NPCOp(NPCOp), .IMM(IMM), .NPC(NPC), .JMPR(RD1_r >> 2'b10)
   );
   

   mux4 #(.WIDTH(32)) A_MUX (
      .d0(RD1_r), .d1(5'b10000), .d2(shamt), .d3(1'b0), .s(ASel), .y(A)
   );
   
      

   mux2 #(.WIDTH(32)) B_MUX (
      .d0(RD2_r), .d1(Imm32), .s(BSel), .y(B)
   );
   

   alu U_ALU ( 
      .A(A), .B(B), .ALUOp(ALUOp), .C(C), .Compare(Zero)
   );
   

   flopr #(.WIDTH(32)) U_C_r (
      .clk(clk), .rst(rst), .d(C), .q(C_r)
   );
   


   dm_4k U_DM ( 
      .addr(C_r[11:2]), .din(RD2_r), .be(4'b1111), .DMWr(DMWr), .clk(clk), .dout(dm_dout)
   );
   

   flopr #(.WIDTH(32)) U_DM_r (
      .clk(clk), .rst(rst), .d(dm_dout), .q(DR_out)
   );
   


   mux4 #(.WIDTH(32)) WD_MUX (
      .d0(C_r), .d1(DR_out), .d2({PC, 2'b00}), .d3(0), .s(WDSel), .y(WD)
   );
endmodule