data/full_repos/permissive/159902111/PCPU_INT/MIPS_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/159902111/PCPU_INT/MIPS_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #1    rst =  1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159902111/PCPU_INT/MIPS_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #2    rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/159902111/PCPU_INT/MIPS_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk <= !clk;\n    ^\n%Error: data/full_repos/permissive/159902111/PCPU_INT/MIPS_tb.v:5: Cannot find file containing module: \'MIPS\'\n  MIPS mips(clk, rst,INT);\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/159902111/PCPU_INT,data/full_repos/permissive/159902111/MIPS\n             data/full_repos/permissive/159902111/PCPU_INT,data/full_repos/permissive/159902111/MIPS.v\n             data/full_repos/permissive/159902111/PCPU_INT,data/full_repos/permissive/159902111/MIPS.sv\n             MIPS\n             MIPS.v\n             MIPS.sv\n             obj_dir/MIPS\n             obj_dir/MIPS.v\n             obj_dir/MIPS.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MIPS_tb(
  );
  `timescale 1ns/1ps
  reg clk, rst, INT;
  MIPS mips(clk, rst,INT);
  initial begin

    clk = 0;
    rst = 0;
    INT = 1;
    #1    rst =  1;
    #2    rst = 0;



  end
  
  always
    #5 clk <= !clk;
endmodule
module MIPS_tb(
  );

  `timescale 1ns/1ps
  reg clk, rst, INT;
  MIPS mips(clk, rst,INT);
  initial begin

    clk = 0;
    rst = 0;
    INT = 1;
    #1    rst =  1;
    #2    rst = 0;



  end
  
  always
    #5 clk <= !clk;
endmodule