data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv
 line:238: before: "("
1: b'%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:238: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:243: Unsupported: Ignoring delay on this delayed statement.\nalways #5 axi_aclk = !axi_aclk ;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:252: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.wr_single(32\'h20, 32\'h33445566, 12\'h0, 3\'h2, 2\'h0, 3\'b010,       resp);   \n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:250: Unsupported: wait statements\n   wait (axi_arstn)\n   ^~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:253: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.wr_single(32\'h00, 32\'h66666666, 12\'h0, 3\'h2, 2\'h0, 3\'b010,       resp);\n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:254: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.rd_single(32\'h04,               12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp);\n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:255: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.rd_single(32\'h00,               12\'h0, 3\'h1, 2\'h0, 3\'b010, rdat, resp);   \n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:256: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.rd_single(32\'h14,               12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp);   \n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:258: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.rd_single(32\'h04,               12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp);\n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:259: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.rd_single(32\'h00,               12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp);\n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:260: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.wr_single(32\'h04, 32\'h00000000, 12\'h0, 3\'h1, 2\'h0, 3\'b010,       resp);   \n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:261: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.wr_single(32\'h04, 32\'h00000444, 12\'h0, 3\'h2, 2\'h0, 3\'b010,       resp);\n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:262: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.rd_single(32\'h04,               12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp);\n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:264: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.rd_single(32\'h08,               12\'h0, 3\'h2, 2\'h0, 3\'b010, rdat, resp);\n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:265: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.wr_single(32\'h00, 32\'h33445566, 12\'h0, 3\'h2, 2\'h0, 3\'b010,       resp);\n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:266: syntax error, unexpected \'@\'\n   repeat(10) @(posedge axi_aclk);  master.wr_single(32\'h08, 32\'h00000606, 12\'h0, 3\'h2, 2\'h0, 3\'b010,       resp);\n              ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/axi_slave_tb.sv:268: syntax error, unexpected \'@\'\n   repeat(20000) @(posedge axi_aclk);\n                 ^\n%Error: Exiting due to 16 error(s), 1 warning(s)\n'
module axi_slave_tb ();

wire             axi_arvalid     ;
wire             axi_awvalid     ;
wire             axi_bready      ;
wire             axi_rready      ;
wire             axi_wlast       ;
wire             axi_wvalid      ;
wire  [ 12-1: 0] axi_arid        ;
wire  [ 12-1: 0] axi_awid        ;
wire  [ 12-1: 0] axi_wid         ;
wire  [  2-1: 0] axi_arburst     ;
wire  [  2-1: 0] axi_arlock      ;
wire  [  3-1: 0] axi_arsize      ;
wire  [  2-1: 0] axi_awburst     ;
wire  [  2-1: 0] axi_awlock      ;
wire  [  3-1: 0] axi_awsize      ;
wire  [  3-1: 0] axi_arprot      ;
wire  [  3-1: 0] axi_awprot      ;
wire  [ 32-1: 0] axi_araddr      ;
wire  [ 32-1: 0] axi_awaddr      ;
wire  [ 32-1: 0] axi_wdata       ;
wire  [  4-1: 0] axi_arcache     ;
wire  [  4-1: 0] axi_arlen       ;
wire  [  4-1: 0] axi_arqos       ;
wire  [  4-1: 0] axi_awcache     ;
wire  [  4-1: 0] axi_awlen       ;
wire  [  4-1: 0] axi_awqos       ;
wire  [  4-1: 0] axi_wstrb       ;
reg              axi_aclk        ;
wire             axi_arready     ;
wire             axi_awready     ;
wire             axi_bvalid      ;
wire             axi_rlast       ;
wire             axi_rvalid      ;
wire             axi_wready      ;
wire  [ 12-1: 0] axi_bid         ;
wire  [ 12-1: 0] axi_rid         ;
wire  [  2-1: 0] axi_bresp       ;
wire  [  2-1: 0] axi_rresp       ;
wire  [ 32-1: 0] axi_rdata       ;
reg              axi_arstn       ;

wire             sys_clk         ;
wire             sys_rstn        ;
wire  [ 32-1: 0] sys_addr        ;
wire  [ 32-1: 0] sys_wdata       ;
wire  [  4-1: 0] sys_sel         ;
wire             sys_wen         ;
wire             sys_ren         ;
reg   [ 32-1: 0] sys_rdata       ;
reg              sys_err         ;
reg              sys_ack         ;

axi_master_model #(
  .AW    ( 32    ),
  .DW    ( 32    ),
  .IW    ( 12    ),
  .LW    (  4    )
) master (

  .aclk_i         (  axi_aclk        ),
  .arstn_i        (  axi_arstn       ),

  .awid_o         (  axi_awid        ),
  .awlen_o        (  axi_awlen       ),
  .awsize_o       (  axi_awsize      ),
  .awburst_o      (  axi_awburst     ),
  .awcache_o      (  axi_awcache     ),
  .awaddr_o       (  axi_awaddr      ),
  .awprot_o       (  axi_awprot      ),
  .awvalid_o      (  axi_awvalid     ),
  .awready_i      (  axi_awready     ),
  .awlock_o       (  axi_awlock      ),

  .wdata_o        (  axi_wdata       ),
  .wstrb_o        (  axi_wstrb       ),
  .wlast_o        (  axi_wlast       ),
  .wvalid_o       (  axi_wvalid      ),
  .wready_i       (  axi_wready      ),  

  .bid_i          (  axi_bid         ),
  .bresp_i        (  axi_bresp       ),
  .bvalid_i       (  axi_bvalid      ),
  .bready_o       (  axi_bready      ),

  .arid_o         (  axi_arid        ),
  .arlen_o        (  axi_arlen       ),
  .arsize_o       (  axi_arsize      ),
  .arburst_o      (  axi_arburst     ),
  .arprot_o       (  axi_arprot      ),
  .arcache_o      (  axi_arcache     ),
  .arvalid_o      (  axi_arvalid     ),
  .araddr_o       (  axi_araddr      ),
  .arlock_o       (  axi_arlock      ),
  .arready_i      (  axi_arready     ),

  .rid_i          (  axi_rid         ),
  .rdata_i        (  axi_rdata       ),
  .rresp_i        (  axi_rresp       ),
  .rvalid_i       (  axi_rvalid      ),
  .rlast_i        (  axi_rlast       ),
  .rready_o       (  axi_rready      ) 
);

axi_slave #(
  .AXI_DW     (  32     ),
  .AXI_AW     (  32     ),
  .AXI_IW     (  12     )
) slave (

  .axi_clk_i        (  axi_aclk           ),
  .axi_rstn_i       (  axi_arstn          ),

  .axi_awid_i       (  axi_awid           ),
  .axi_awaddr_i     (  axi_awaddr         ),
  .axi_awlen_i      (  axi_awlen          ),
  .axi_awsize_i     (  axi_awsize         ),
  .axi_awburst_i    (  axi_awburst        ),
  .axi_awlock_i     (  axi_awlock         ),
  .axi_awcache_i    (  axi_awcache        ),
  .axi_awprot_i     (  axi_awprot         ),
  .axi_awvalid_i    (  axi_awvalid        ),
  .axi_awready_o    (  axi_awready        ),

  .axi_wid_i        (  axi_wid            ),
  .axi_wdata_i      (  axi_wdata          ),
  .axi_wstrb_i      (  axi_wstrb          ),
  .axi_wlast_i      (  axi_wlast          ),
  .axi_wvalid_i     (  axi_wvalid         ),
  .axi_wready_o     (  axi_wready         ),

  .axi_bid_o        (  axi_bid            ),
  .axi_bresp_o      (  axi_bresp          ),
  .axi_bvalid_o     (  axi_bvalid         ),
  .axi_bready_i     (  axi_bready         ),

  .axi_arid_i       (  axi_arid           ),
  .axi_araddr_i     (  axi_araddr         ),
  .axi_arlen_i      (  axi_arlen          ),
  .axi_arsize_i     (  axi_arsize         ),
  .axi_arburst_i    (  axi_arburst        ),
  .axi_arlock_i     (  axi_arlock         ),
  .axi_arcache_i    (  axi_arcache        ),
  .axi_arprot_i     (  axi_arprot         ),
  .axi_arvalid_i    (  axi_arvalid        ),
  .axi_arready_o    (  axi_arready        ),

  .axi_rid_o        (  axi_rid            ),
  .axi_rdata_o      (  axi_rdata          ),
  .axi_rresp_o      (  axi_rresp          ),
  .axi_rlast_o      (  axi_rlast          ),
  .axi_rvalid_o     (  axi_rvalid         ),
  .axi_rready_i     (  axi_rready         ),

  .sys_addr_o       (  sys_addr           ),
  .sys_wdata_o      (  sys_wdata          ),
  .sys_sel_o        (  sys_sel            ),
  .sys_wen_o        (  sys_wen            ),
  .sys_ren_o        (  sys_ren            ),
  .sys_rdata_i      (  sys_rdata          ),
  .sys_err_i        (  sys_err            ),
  .sys_ack_i        (  sys_ack            )
);





assign sys_clk  = axi_aclk    ;
assign sys_rstn = axi_arstn   ;

logic [  4-1: 0] rd_ack   ;
logic [ 32-1: 0] reg_a    ;
logic [ 32-1: 0] reg_b    ;
logic [ 32-1: 0] reg_c    ;

always @(posedge sys_clk)
   if (sys_rstn == 1'b0) begin
      rd_ack <= 4'h0 ;
      reg_a  <= 32'h0         ;
      reg_b  <= 32'h12345678  ;
      reg_c  <= 32'h505       ;
   end else begin
      rd_ack <= {rd_ack[2:0], (sys_ren || sys_wen)};

      if (sys_wen && (sys_addr[9:0]==10'h0))    reg_a <= sys_wdata ;
      if (sys_wen && (sys_addr[9:0]==10'h4))    reg_b <= sys_wdata ;
      if (sys_wen && (sys_addr[9:0]==10'h8))    reg_c <= sys_wdata ;
   end

always_comb
begin
   sys_err = 1'b0 ;
   casez (sys_addr[9:0])
         10'h0 : begin sys_ack = 1'b1;          sys_rdata = reg_a      ; end 
         10'h4 : begin sys_ack = rd_ack[3];     sys_rdata = reg_b      ; end
         10'h8 : begin sys_ack = 1'b1;          sys_rdata = reg_c      ; end 
       default : begin sys_ack = 1'b0;          sys_rdata = 32'h0      ; end
   endcase
end





initial
begin
   axi_arstn = 1'b0;
   repeat(10) @(posedge axi_aclk);
   axi_arstn = 1'b1;
end

initial   axi_aclk = 1'b0;
always #5 axi_aclk = !axi_aclk ;

reg [32-1: 0] rdat ;
reg [ 2-1: 0] resp ;

initial
begin
   wait (axi_arstn)

   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h20, 32'h33445566, 12'h0, 3'h2, 2'h0, 3'b010,       resp);
   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h00, 32'h66666666, 12'h0, 3'h2, 2'h0, 3'b010,       resp);
   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h04,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h00,               12'h0, 3'h1, 2'h0, 3'b010, rdat, resp);
   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h14,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);

   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h04,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h00,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h04, 32'h00000000, 12'h0, 3'h1, 2'h0, 3'b010,       resp);
   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h04, 32'h00000444, 12'h0, 3'h2, 2'h0, 3'b010,       resp);
   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h04,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);

   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h08,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h00, 32'h33445566, 12'h0, 3'h2, 2'h0, 3'b010,       resp);
   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h08, 32'h00000606, 12'h0, 3'h2, 2'h0, 3'b010,       resp);

   repeat(20000) @(posedge axi_aclk);
end

endmodule
module axi_slave_tb ();


wire             axi_arvalid     ;
wire             axi_awvalid     ;
wire             axi_bready      ;
wire             axi_rready      ;
wire             axi_wlast       ;
wire             axi_wvalid      ;
wire  [ 12-1: 0] axi_arid        ;
wire  [ 12-1: 0] axi_awid        ;
wire  [ 12-1: 0] axi_wid         ;
wire  [  2-1: 0] axi_arburst     ;
wire  [  2-1: 0] axi_arlock      ;
wire  [  3-1: 0] axi_arsize      ;
wire  [  2-1: 0] axi_awburst     ;
wire  [  2-1: 0] axi_awlock      ;
wire  [  3-1: 0] axi_awsize      ;
wire  [  3-1: 0] axi_arprot      ;
wire  [  3-1: 0] axi_awprot      ;
wire  [ 32-1: 0] axi_araddr      ;
wire  [ 32-1: 0] axi_awaddr      ;
wire  [ 32-1: 0] axi_wdata       ;
wire  [  4-1: 0] axi_arcache     ;
wire  [  4-1: 0] axi_arlen       ;
wire  [  4-1: 0] axi_arqos       ;
wire  [  4-1: 0] axi_awcache     ;
wire  [  4-1: 0] axi_awlen       ;
wire  [  4-1: 0] axi_awqos       ;
wire  [  4-1: 0] axi_wstrb       ;
reg              axi_aclk        ;
wire             axi_arready     ;
wire             axi_awready     ;
wire             axi_bvalid      ;
wire             axi_rlast       ;
wire             axi_rvalid      ;
wire             axi_wready      ;
wire  [ 12-1: 0] axi_bid         ;
wire  [ 12-1: 0] axi_rid         ;
wire  [  2-1: 0] axi_bresp       ;
wire  [  2-1: 0] axi_rresp       ;
wire  [ 32-1: 0] axi_rdata       ;
reg              axi_arstn       ;

wire             sys_clk         ;
wire             sys_rstn        ;
wire  [ 32-1: 0] sys_addr        ;
wire  [ 32-1: 0] sys_wdata       ;
wire  [  4-1: 0] sys_sel         ;
wire             sys_wen         ;
wire             sys_ren         ;
reg   [ 32-1: 0] sys_rdata       ;
reg              sys_err         ;
reg              sys_ack         ;

axi_master_model #(
  .AW    ( 32    ),
  .DW    ( 32    ),
  .IW    ( 12    ),
  .LW    (  4    )
) master (

  .aclk_i         (  axi_aclk        ),
  .arstn_i        (  axi_arstn       ),

  .awid_o         (  axi_awid        ),
  .awlen_o        (  axi_awlen       ),
  .awsize_o       (  axi_awsize      ),
  .awburst_o      (  axi_awburst     ),
  .awcache_o      (  axi_awcache     ),
  .awaddr_o       (  axi_awaddr      ),
  .awprot_o       (  axi_awprot      ),
  .awvalid_o      (  axi_awvalid     ),
  .awready_i      (  axi_awready     ),
  .awlock_o       (  axi_awlock      ),

  .wdata_o        (  axi_wdata       ),
  .wstrb_o        (  axi_wstrb       ),
  .wlast_o        (  axi_wlast       ),
  .wvalid_o       (  axi_wvalid      ),
  .wready_i       (  axi_wready      ),  

  .bid_i          (  axi_bid         ),
  .bresp_i        (  axi_bresp       ),
  .bvalid_i       (  axi_bvalid      ),
  .bready_o       (  axi_bready      ),

  .arid_o         (  axi_arid        ),
  .arlen_o        (  axi_arlen       ),
  .arsize_o       (  axi_arsize      ),
  .arburst_o      (  axi_arburst     ),
  .arprot_o       (  axi_arprot      ),
  .arcache_o      (  axi_arcache     ),
  .arvalid_o      (  axi_arvalid     ),
  .araddr_o       (  axi_araddr      ),
  .arlock_o       (  axi_arlock      ),
  .arready_i      (  axi_arready     ),

  .rid_i          (  axi_rid         ),
  .rdata_i        (  axi_rdata       ),
  .rresp_i        (  axi_rresp       ),
  .rvalid_i       (  axi_rvalid      ),
  .rlast_i        (  axi_rlast       ),
  .rready_o       (  axi_rready      ) 
);

axi_slave #(
  .AXI_DW     (  32     ),
  .AXI_AW     (  32     ),
  .AXI_IW     (  12     )
) slave (

  .axi_clk_i        (  axi_aclk           ),
  .axi_rstn_i       (  axi_arstn          ),

  .axi_awid_i       (  axi_awid           ),
  .axi_awaddr_i     (  axi_awaddr         ),
  .axi_awlen_i      (  axi_awlen          ),
  .axi_awsize_i     (  axi_awsize         ),
  .axi_awburst_i    (  axi_awburst        ),
  .axi_awlock_i     (  axi_awlock         ),
  .axi_awcache_i    (  axi_awcache        ),
  .axi_awprot_i     (  axi_awprot         ),
  .axi_awvalid_i    (  axi_awvalid        ),
  .axi_awready_o    (  axi_awready        ),

  .axi_wid_i        (  axi_wid            ),
  .axi_wdata_i      (  axi_wdata          ),
  .axi_wstrb_i      (  axi_wstrb          ),
  .axi_wlast_i      (  axi_wlast          ),
  .axi_wvalid_i     (  axi_wvalid         ),
  .axi_wready_o     (  axi_wready         ),

  .axi_bid_o        (  axi_bid            ),
  .axi_bresp_o      (  axi_bresp          ),
  .axi_bvalid_o     (  axi_bvalid         ),
  .axi_bready_i     (  axi_bready         ),

  .axi_arid_i       (  axi_arid           ),
  .axi_araddr_i     (  axi_araddr         ),
  .axi_arlen_i      (  axi_arlen          ),
  .axi_arsize_i     (  axi_arsize         ),
  .axi_arburst_i    (  axi_arburst        ),
  .axi_arlock_i     (  axi_arlock         ),
  .axi_arcache_i    (  axi_arcache        ),
  .axi_arprot_i     (  axi_arprot         ),
  .axi_arvalid_i    (  axi_arvalid        ),
  .axi_arready_o    (  axi_arready        ),

  .axi_rid_o        (  axi_rid            ),
  .axi_rdata_o      (  axi_rdata          ),
  .axi_rresp_o      (  axi_rresp          ),
  .axi_rlast_o      (  axi_rlast          ),
  .axi_rvalid_o     (  axi_rvalid         ),
  .axi_rready_i     (  axi_rready         ),

  .sys_addr_o       (  sys_addr           ),
  .sys_wdata_o      (  sys_wdata          ),
  .sys_sel_o        (  sys_sel            ),
  .sys_wen_o        (  sys_wen            ),
  .sys_ren_o        (  sys_ren            ),
  .sys_rdata_i      (  sys_rdata          ),
  .sys_err_i        (  sys_err            ),
  .sys_ack_i        (  sys_ack            )
);





assign sys_clk  = axi_aclk    ;
assign sys_rstn = axi_arstn   ;

logic [  4-1: 0] rd_ack   ;
logic [ 32-1: 0] reg_a    ;
logic [ 32-1: 0] reg_b    ;
logic [ 32-1: 0] reg_c    ;

always @(posedge sys_clk)
   if (sys_rstn == 1'b0) begin
      rd_ack <= 4'h0 ;
      reg_a  <= 32'h0         ;
      reg_b  <= 32'h12345678  ;
      reg_c  <= 32'h505       ;
   end else begin
      rd_ack <= {rd_ack[2:0], (sys_ren || sys_wen)};

      if (sys_wen && (sys_addr[9:0]==10'h0))    reg_a <= sys_wdata ;
      if (sys_wen && (sys_addr[9:0]==10'h4))    reg_b <= sys_wdata ;
      if (sys_wen && (sys_addr[9:0]==10'h8))    reg_c <= sys_wdata ;
   end

always_comb
begin
   sys_err = 1'b0 ;
   casez (sys_addr[9:0])
         10'h0 : begin sys_ack = 1'b1;          sys_rdata = reg_a      ; end 
         10'h4 : begin sys_ack = rd_ack[3];     sys_rdata = reg_b      ; end
         10'h8 : begin sys_ack = 1'b1;          sys_rdata = reg_c      ; end 
       default : begin sys_ack = 1'b0;          sys_rdata = 32'h0      ; end
   endcase
end





initial
begin
   axi_arstn = 1'b0;
   repeat(10) @(posedge axi_aclk);
   axi_arstn = 1'b1;
end

initial   axi_aclk = 1'b0;
always #5 axi_aclk = !axi_aclk ;

reg [32-1: 0] rdat ;
reg [ 2-1: 0] resp ;

initial
begin
   wait (axi_arstn)

   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h20, 32'h33445566, 12'h0, 3'h2, 2'h0, 3'b010,       resp);
   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h00, 32'h66666666, 12'h0, 3'h2, 2'h0, 3'b010,       resp);
   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h04,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h00,               12'h0, 3'h1, 2'h0, 3'b010, rdat, resp);
   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h14,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);

   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h04,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h00,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h04, 32'h00000000, 12'h0, 3'h1, 2'h0, 3'b010,       resp);
   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h04, 32'h00000444, 12'h0, 3'h2, 2'h0, 3'b010,       resp);
   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h04,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);

   repeat(10) @(posedge axi_aclk);  master.rd_single(32'h08,               12'h0, 3'h2, 2'h0, 3'b010, rdat, resp);
   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h00, 32'h33445566, 12'h0, 3'h2, 2'h0, 3'b010,       resp);
   repeat(10) @(posedge axi_aclk);  master.wr_single(32'h08, 32'h00000606, 12'h0, 3'h2, 2'h0, 3'b010,       resp);

   repeat(20000) @(posedge axi_aclk);
end

endmodule