data/full_repos/permissive/159016511/src/rtl/common/debug_cnt.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/f49dad55-2c28-4a83-ab36-c706ef1c66e7.xml
module debug_cnt (
input wire clk,
input wire rstn,
input wire cnt_en,
output LED1,
output LED2
);
parameter CNT_WIDTH = 25;
reg [CNT_WIDTH-1:0] cnt;
reg event_detect;

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		cnt <= 0;
		event_detect <= 1'b0;
	end
	else
	begin 
		if(cnt_en)
		begin
			cnt <= cnt + 1;
			event_detect <= 1'b1;
		end
	end
end


assign LED1   = cnt[CNT_WIDTH-1];
assign LED2   = event_detect;

endmodule
module debug_cnt (
input wire clk,
input wire rstn,
input wire cnt_en,
output LED1,
output LED2
);

parameter CNT_WIDTH = 25;
reg [CNT_WIDTH-1:0] cnt;
reg event_detect;

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		cnt <= 0;
		event_detect <= 1'b0;
	end
	else
	begin 
		if(cnt_en)
		begin
			cnt <= cnt + 1;
			event_detect <= 1'b1;
		end
	end
end


assign LED1   = cnt[CNT_WIDTH-1];
assign LED2   = event_detect;

endmodule