data/full_repos/permissive/143278/fpga_tests/bufifab_tb.v
 line:15: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/bufifab_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("I=%b, E=%b, Out0=%b, Out1=%b", i[0], i[1], out0, out1);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/fpga_tests/bufifab_tb.v:7: Cannot find file containing module: \'bufifab\'\n   bufifab dut(.Out0(out0), .Out1(out1), .I(i[0]), .E(i[1]));\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/bufifab\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/bufifab.v\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/bufifab.sv\n             bufifab\n             bufifab.v\n             bufifab.sv\n             obj_dir/bufifab\n             obj_dir/bufifab.v\n             obj_dir/bufifab.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [2:0] i;
   wire      out0, out1;
   wire      ref0, ref1;

   bufifab dut(.Out0(out0), .Out1(out1), .I(i[0]), .E(i[1]));

   bufif0 (ref0, i[0], i[1]);
   bufif1 (ref1, i[0], i[1]);
   initial begin
      i = 0;

      for (i = 0 ;  i[2] == 0 ;  i = i+1) begin
	 #1 $display("I=%b, E=%b, Out0=%b, Out1=%b", i[0], i[1], out0, out1);

	 if (out0 !== ref0) begin
	    $display("FAILED -- ref0=%b, out0=%b", ref0, out0);
	    $finish;
	 end

	 if (out1 !== ref1) begin
	    $display("FAILED -- ref1=%b, out1=%b", ref1, out1);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule
module main;


   reg [2:0] i;
   wire      out0, out1;
   wire      ref0, ref1;

   bufifab dut(.Out0(out0), .Out1(out1), .I(i[0]), .E(i[1]));

   bufif0 (ref0, i[0], i[1]);
   bufif1 (ref1, i[0], i[1]);
   initial begin
      i = 0;

      for (i = 0 ;  i[2] == 0 ;  i = i+1) begin
	 #1 $display("I=%b, E=%b, Out0=%b, Out1=%b", i[0], i[1], out0, out1);

	 if (out0 !== ref0) begin
	    $display("FAILED -- ref0=%b, out0=%b", ref0, out0);
	    $finish;
	 end

	 if (out1 !== ref1) begin
	    $display("FAILED -- ref1=%b, out1=%b", ref1, out1);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule