data/full_repos/permissive/135852214/Verilog/dafa_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/135852214/Verilog/dafa_sim.v:18: Cannot find file containing module: \'DAFA\'\n DAFA uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/DAFA\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/DAFA.v\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/DAFA.sv\n             DAFA\n             DAFA.v\n             DAFA.sv\n             obj_dir/DAFA\n             obj_dir/DAFA.v\n             obj_dir/DAFA.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dafa_sim;


	reg [11:0] s_in;
	reg [11:0] x_in;
	reg [11:0] y_in;
	reg ovf_in;


	wire [11:0] s_out;
	wire [11:0] x_out; 
	wire [11:0] y_out;
	wire ovf_out;


	DAFA uut (
		.s_in(s_in), 
		.x_in(x_in), 
		.y_in(y_in), 
		.s_out(s_out), 
		.x_out(x_out), 
		.y_out(y_out), 
		.ovf_in(ovf_in), 
		.ovf_out(ovf_out)
	);

	initial begin

		s_in = 0;
		x_in = 0;
		y_in = 0;
		ovf_in = 0;
		#100;
		y_in = 12'b000000000111;
		x_in = 12'b000000011001;
		#10;
		if(s_out != 12'b000000011110)
			$display("Error: s_out is %b while it should be 000000011110", s_out);
		#10;
		y_in = 12'b000000011110;
		x_in = 12'b000000101010;
		#10;
		if(s_out != 12'b000000110100)
			$display("Error: s_out is %b while it should be 000000110100", s_out);
		#10;
		y_in = 12'b000000101101;
		x_in = 12'b000000110011;
		#10;
		if(s_out != 12'b000001010101)
			$display("Error: s_out is %b while it should be 000001010101", s_out);
		#10;
		y_in = 12'b000000110100;
		x_in = 12'b000001001011;
		#10; 
		if(s_out != 12'b000001111111)
			$display("Error: s_out is %b while it should be 000001111111", s_out);
		#10;
		y_in = 12'b000001001100;
		x_in = 12'b000001010010;
		#10;
		if(s_out != 12'b000110011111) 
			$display("Error: s_out is %b while it should be 000110011111", s_out);
		#10;
		y_in = 12'b000001010101;
		x_in = 12'b000001100001;
		#10;
		if(s_out != 12'b000110110101)
			$display("Error: s_out is %b while it should be 000110110101", s_out);
		#10;
		y_in = 12'b000001100110;
		x_in = 12'b000001111000;
		#10;
		if(s_out != 12'b000111010100)
			$display("Error: s_out is %b while it should be 000111010100", s_out);
		#10;
		x_in = 12'b111101110000;
		y_in = 12'b000000000111;
		#10;
		if(s_out != 12'b111101110111)
			$display("Error: s_out is %b while it should be 111101110111", s_out);
		#10;
		x_in = 12'b000000000111;
		y_in = 12'b000000011110;
		#10;
		if(s_out != 12'b000000101010)
			$display("Error: s_out is %b while it should be 111101110111", s_out);
		#10;
		

	end
      
endmodule
module dafa_sim;



	reg [11:0] s_in;
	reg [11:0] x_in;
	reg [11:0] y_in;
	reg ovf_in;


	wire [11:0] s_out;
	wire [11:0] x_out; 
	wire [11:0] y_out;
	wire ovf_out;


	DAFA uut (
		.s_in(s_in), 
		.x_in(x_in), 
		.y_in(y_in), 
		.s_out(s_out), 
		.x_out(x_out), 
		.y_out(y_out), 
		.ovf_in(ovf_in), 
		.ovf_out(ovf_out)
	);

	initial begin

		s_in = 0;
		x_in = 0;
		y_in = 0;
		ovf_in = 0;
		#100;
		y_in = 12'b000000000111;
		x_in = 12'b000000011001;
		#10;
		if(s_out != 12'b000000011110)
			$display("Error: s_out is %b while it should be 000000011110", s_out);
		#10;
		y_in = 12'b000000011110;
		x_in = 12'b000000101010;
		#10;
		if(s_out != 12'b000000110100)
			$display("Error: s_out is %b while it should be 000000110100", s_out);
		#10;
		y_in = 12'b000000101101;
		x_in = 12'b000000110011;
		#10;
		if(s_out != 12'b000001010101)
			$display("Error: s_out is %b while it should be 000001010101", s_out);
		#10;
		y_in = 12'b000000110100;
		x_in = 12'b000001001011;
		#10; 
		if(s_out != 12'b000001111111)
			$display("Error: s_out is %b while it should be 000001111111", s_out);
		#10;
		y_in = 12'b000001001100;
		x_in = 12'b000001010010;
		#10;
		if(s_out != 12'b000110011111) 
			$display("Error: s_out is %b while it should be 000110011111", s_out);
		#10;
		y_in = 12'b000001010101;
		x_in = 12'b000001100001;
		#10;
		if(s_out != 12'b000110110101)
			$display("Error: s_out is %b while it should be 000110110101", s_out);
		#10;
		y_in = 12'b000001100110;
		x_in = 12'b000001111000;
		#10;
		if(s_out != 12'b000111010100)
			$display("Error: s_out is %b while it should be 000111010100", s_out);
		#10;
		x_in = 12'b111101110000;
		y_in = 12'b000000000111;
		#10;
		if(s_out != 12'b111101110111)
			$display("Error: s_out is %b while it should be 111101110111", s_out);
		#10;
		x_in = 12'b000000000111;
		y_in = 12'b000000011110;
		#10;
		if(s_out != 12'b000000101010)
			$display("Error: s_out is %b while it should be 111101110111", s_out);
		#10;
		

	end
      
endmodule