data/full_repos/permissive/116866011/BSP/c5soc/hardware/c5soc/system/synthesis/submodules/pll_lock_avs.v
 line:26: before: "v"
data/verilator_xmls/c81a7a24-ceb8-498e-be2d-585a1e7f8230.xml
module pll_lock_avs 
#( 
  parameter WIDTH=32
)
(
   input clk,
   input resetn,


   input slave_read,
   output slave_readdata,

   input  lock,
   output lock_export
);

reg locked;
always@(posedge clk)
  locked <= lock;

assign slave_readdata = locked;
assign lock_export = lock;

endmodule
module pll_lock_avs 
#( 
  parameter WIDTH=32
)
(
   input clk,
   input resetn,


   input slave_read,
   output slave_readdata,

   input  lock,
   output lock_export
);


reg locked;
always@(posedge clk)
  locked <= lock;

assign slave_readdata = locked;
assign lock_export = lock;

endmodule