data/full_repos/permissive/210844779/lab1/1.3.2/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.3.2/test.v:13: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210844779/lab1/1.3.2/test.v:6: Cannot find file containing module: \'D_sr_nor\'\nD_sr_nor u0(D,En,Q,not_Q);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab1/1.3.2,data/full_repos/permissive/210844779/D_sr_nor\n             data/full_repos/permissive/210844779/lab1/1.3.2,data/full_repos/permissive/210844779/D_sr_nor.v\n             data/full_repos/permissive/210844779/lab1/1.3.2,data/full_repos/permissive/210844779/D_sr_nor.sv\n             D_sr_nor\n             D_sr_nor.v\n             D_sr_nor.sv\n             obj_dir/D_sr_nor\n             obj_dir/D_sr_nor.v\n             obj_dir/D_sr_nor.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab1/1.3.2/test.v:11: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                         : ... In instance tb\nD= $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab1/1.3.2/test.v:12: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                         : ... In instance tb\nEn= $random;\n  ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

reg D,En;
wire Q,not_Q;

D_sr_nor u0(D,En,Q,not_Q);

always
begin

D= $random;
En= $random;
#10;

end

endmodule
module tb();


reg D,En;
wire Q,not_Q;

D_sr_nor u0(D,En,Q,not_Q);

always
begin

D= $random;
En= $random;
#10;

end

endmodule