data/full_repos/permissive/174155074/systems/microprocessors/programable-8-bit-microprocessor/core-parts/register-ab8.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/174155074/systems/microprocessors/programable-8-bit-microprocessor/core-parts/register-ab8.v:17: Signal definition not found, creating implicitly: \'LOW\'\nassign LOW              = 1\'b0;\n       ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/174155074/systems/microprocessors/programable-8-bit-microprocessor/core-parts/register-ab8.v:21: Cannot find file containing module: \'or2\'\nor2 OR1 (\n^~~\n        ... Looked in:\n             data/full_repos/permissive/174155074/systems/microprocessors/programable-8-bit-microprocessor/core-parts,data/full_repos/permissive/174155074/or2\n             data/full_repos/permissive/174155074/systems/microprocessors/programable-8-bit-microprocessor/core-parts,data/full_repos/permissive/174155074/or2.v\n             data/full_repos/permissive/174155074/systems/microprocessors/programable-8-bit-microprocessor/core-parts,data/full_repos/permissive/174155074/or2.sv\n             or2\n             or2.v\n             or2.sv\n             obj_dir/or2\n             obj_dir/or2.v\n             obj_dir/or2.sv\n%Error: data/full_repos/permissive/174155074/systems/microprocessors/programable-8-bit-microprocessor/core-parts/register-ab8.v:28: Cannot find file containing module: \'ta377_bar\'\nta377_bar DFFS (\n^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module register_ab8(
    input [7:0]     DATA_IN,
    input           SYSTEM_CLK,
    input           ENABLE_CLK,
    output [7:0]    DATA_OUT
);


wire         W1;


assign LOW              = 1'b0;



or2 OR1 (
    .a(SYSTEM_CLK),
    .b(ENABLE_CLK),
    .y(W1)
);


ta377_bar DFFS (
    .EN_BAR(LOW),
    .CLK(W1),
    .D(DATA_IN),
    .Q(DATA_OUT)
);

endmodule
module register_ab8(
    input [7:0]     DATA_IN,
    input           SYSTEM_CLK,
    input           ENABLE_CLK,
    output [7:0]    DATA_OUT
);



wire         W1;


assign LOW              = 1'b0;



or2 OR1 (
    .a(SYSTEM_CLK),
    .b(ENABLE_CLK),
    .y(W1)
);


ta377_bar DFFS (
    .EN_BAR(LOW),
    .CLK(W1),
    .D(DATA_IN),
    .Q(DATA_OUT)
);

endmodule