data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp
 line:8: before: "parameter"
1: b"%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:7: Define or directive not defined: '`mname'\nmodule  `mname`  #(\n        ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:7: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule  `mname`  #(\n              ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:9: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:20: Unsupported or unknown PLI call: $c_in_decl\n  input  `$c_in_decl`        op_c_in,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:23: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [DataWidth-1:0] res\n  ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:24: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:30: Define or directive not defined: '`2'\n    logic [`2**$lut_inps-1`:0] lut;\n           ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:30: Unsupported or unknown PLI call: $lut_inps\n    logic [`2**$lut_inps-1`:0] lut;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:34: Define or directive not defined: '`2'\n        lut   <= `2**$lut_inps`'h0;\n                 ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:34: Unsupported or unknown PLI call: $lut_inps\n        lut   <= `2**$lut_inps`'h0;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:39: Unsupported or unknown PLI call: $lut_inps\n        lut   <= {`(2**$lut_inps)/32`{cfg_d[`$cfg_index-1`: 0]}};\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:39: Unsupported or unknown PLI call: $cfg_index\n        lut   <= {`(2**$lut_inps)/32`{cfg_d[`$cfg_index-1`: 0]}};\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:41: Unsupported or unknown PLI call: $cfg_index\n        lut   <= cfg_d[`$cfg_index-1`: 0];\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:51: Define or directive not defined: '`32'\n    assign read_data = {`32-(2**$lut_inps)`'b0, lut};\n                        ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_lut.svp:51: Unsupported or unknown PLI call: $lut_inps\n    assign read_data = {`32-(2**$lut_inps)`'b0, lut};\n                                ^~~~~~~~~\n%Error: Exiting due to 15 error(s)\n"
module  `mname`  #(
  parameter DataWidth = 16
) (
  input                  cfg_clk,
  input                  cfg_rst_n,
  input  [31:0]          cfg_d,
  input  [7:0]           cfg_a,
  input                  cfg_en,

  input  [DataWidth-1:0] op_a_in,
  input  [DataWidth-1:0] op_b_in,


  input  `$c_in_decl`        op_c_in,

  output logic [31:0] read_data,
  output logic [DataWidth-1:0] res
);

genvar ggg;
generate
  for (ggg = 0; ggg < DataWidth; ggg = ggg +1) begin : GEN_LUT

    logic [`2**$lut_inps-1`:0] lut;

    always_ff @(posedge cfg_clk or negedge cfg_rst_n) begin
      if(~cfg_rst_n) begin
        lut   <= `2**$lut_inps`'h0;
      end else if(cfg_en && (cfg_a == $unsigned(ggg/4)) ) begin



        lut   <= {`(2**$lut_inps)/32`{cfg_d[`$cfg_index-1`: 0]}};

        lut   <= cfg_d[`$cfg_index-1`: 0];

      end
    end


    assign res[ggg] = lut[{op_c_in, op_b_in[ggg], op_a_in[ggg]}];

    assign res[ggg] = lut[{op_b_in[ggg], op_a_in[ggg]}];

    assign read_data = {`32-(2**$lut_inps)`'b0, lut};
  end
endgenerate

endmodule
module  `mname`  #(
  parameter DataWidth = 16
) (
  input                  cfg_clk,
  input                  cfg_rst_n,
  input  [31:0]          cfg_d,
  input  [7:0]           cfg_a,
  input                  cfg_en,

  input  [DataWidth-1:0] op_a_in,
  input  [DataWidth-1:0] op_b_in,


  input  `$c_in_decl`        op_c_in,

  output logic [31:0] read_data,
  output logic [DataWidth-1:0] res
);


genvar ggg;
generate
  for (ggg = 0; ggg < DataWidth; ggg = ggg +1) begin : GEN_LUT

    logic [`2**$lut_inps-1`:0] lut;

    always_ff @(posedge cfg_clk or negedge cfg_rst_n) begin
      if(~cfg_rst_n) begin
        lut   <= `2**$lut_inps`'h0;
      end else if(cfg_en && (cfg_a == $unsigned(ggg/4)) ) begin



        lut   <= {`(2**$lut_inps)/32`{cfg_d[`$cfg_index-1`: 0]}};

        lut   <= cfg_d[`$cfg_index-1`: 0];

      end
    end


    assign res[ggg] = lut[{op_c_in, op_b_in[ggg], op_a_in[ggg]}];

    assign res[ggg] = lut[{op_b_in[ggg], op_a_in[ggg]}];

    assign read_data = {`32-(2**$lut_inps)`'b0, lut};
  end
endgenerate

endmodule