data/full_repos/permissive/155656868/src/sp_reg.v
data/verilator_xmls/ecd12d8c-0c8d-44ec-b6b9-57d4d0f37b3b.xml
module program_counter #(parameter WORD_SIZE=32, OPCODE_WIDTH=3, REG_WIDTH=5)
                        (input clk, rst, beq, zero, j,
                         input [WORD_SIZE-1 : 0] offset,
                         output [WORD_SIZE-1:0] pc_out);


    reg [WORD_SIZE-1:0]  pc_reg;
    wire [WORD_SIZE-1:0] pc_i, pc_new;




    always @(posedge clk) begin
        if (rst) pc_reg <= 0;
        else pc_reg <= pc_new;
    end

    assign pc_i = pc_reg + 1;
    assign pc_new = (j || (beq && zero)) ? (offset + pc_i) : pc_i;

    assign pc_out = pc_reg;
endmodule
module program_counter #(parameter WORD_SIZE=32, OPCODE_WIDTH=3, REG_WIDTH=5)
                        (input clk, rst, beq, zero, j,
                         input [WORD_SIZE-1 : 0] offset,
                         output [WORD_SIZE-1:0] pc_out);



    reg [WORD_SIZE-1:0]  pc_reg;
    wire [WORD_SIZE-1:0] pc_i, pc_new;




    always @(posedge clk) begin
        if (rst) pc_reg <= 0;
        else pc_reg <= pc_new;
    end

    assign pc_i = pc_reg + 1;
    assign pc_new = (j || (beq && zero)) ? (offset + pc_i) : pc_i;

    assign pc_out = pc_reg;
endmodule