data/full_repos/permissive/129155059/proyecto-02/all/mux4_1_cond.v
data/verilator_xmls/cc2460be-a313-47c3-ab17-5bba1912306c.xml
module mux4_1_cond( input [1:0]   VC_id,
                    input [3:0]   Data_Word,
                    input         reset,
                    output reg    data_out
                    );









  always @ (*) begin
    if (reset) begin
      case (VC_id)
        2'b00: data_out = Data_Word[0];
        2'b01: data_out = Data_Word[1];
        2'b10: data_out = Data_Word[2];
        2'b11: data_out = Data_Word[3];
        default: data_out = 1'b0;
      endcase

    end else begin
      data_out = 1'b0;
    end
  end
endmodule
module mux4_1_cond( input [1:0]   VC_id,
                    input [3:0]   Data_Word,
                    input         reset,
                    output reg    data_out
                    );










  always @ (*) begin
    if (reset) begin
      case (VC_id)
        2'b00: data_out = Data_Word[0];
        2'b01: data_out = Data_Word[1];
        2'b10: data_out = Data_Word[2];
        2'b11: data_out = Data_Word[3];
        default: data_out = 1'b0;
      endcase

    end else begin
      data_out = 1'b0;
    end
  end
endmodule