data/full_repos/permissive/201488448/3_verification/1_sim/12_seq1.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/3_verification/1_sim/12_seq1.v:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                         : ... In instance top_module\n       q <= ~a; \n       ^\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input a,
    output q );

    always@(posedge clk) begin
       q <= ~a; 
    end
    
endmodule
module top_module (
    input clk,
    input a,
    output q );


    always@(posedge clk) begin
       q <= ~a; 
    end
    
endmodule