data/full_repos/permissive/20097350/score_count_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  forever #50 CLK = ~CLK; \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #200 RESET = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #500 RESET = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #1000 REACHED_TARGET = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #1 REACHED_TARGET = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #1000 REACHED_TARGET = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #1 REACHED_TARGET = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #1000 REACHED_TARGET = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #1 REACHED_TARGET = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #200 RESET = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20097350/score_count_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #500 RESET = 0;\n  ^\n%Error: data/full_repos/permissive/20097350/score_count_tb.v:36: Cannot find file containing module: \'ScoreCounter\'\n ScoreCounter uut (\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20097350,data/full_repos/permissive/20097350/ScoreCounter\n             data/full_repos/permissive/20097350,data/full_repos/permissive/20097350/ScoreCounter.v\n             data/full_repos/permissive/20097350,data/full_repos/permissive/20097350/ScoreCounter.sv\n             ScoreCounter\n             ScoreCounter.v\n             ScoreCounter.sv\n             obj_dir/ScoreCounter\n             obj_dir/ScoreCounter.v\n             obj_dir/ScoreCounter.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module score_count_tb;


	reg CLK;
	reg RESET;
	reg REACHED_TARGET;


	wire [3:0] CURRENT_SCORE;


	ScoreCounter uut (
		.CLK(CLK), 
		.RESET(RESET), 
		.REACHED_TARGET(REACHED_TARGET), 
		.CURRENT_SCORE(CURRENT_SCORE)
	);
	
	

	initial begin

		CLK = 0;
		RESET = 0;
		REACHED_TARGET = 0;


		#100;
		
		forever #50 CLK = ~CLK; 
	end
	
	initial begin
		#200 RESET = 1;
		#500 RESET = 0;
		
		#1000 REACHED_TARGET = 1;
		#1 REACHED_TARGET = 0;
	
		
		#1000 REACHED_TARGET = 1;
		#1 REACHED_TARGET = 0;
		
		#1000 REACHED_TARGET = 1;
		#1 REACHED_TARGET = 0;
		
		
		#200 RESET = 1;
		#500 RESET = 0;
	end
		
      
endmodule
module score_count_tb;



	reg CLK;
	reg RESET;
	reg REACHED_TARGET;


	wire [3:0] CURRENT_SCORE;


	ScoreCounter uut (
		.CLK(CLK), 
		.RESET(RESET), 
		.REACHED_TARGET(REACHED_TARGET), 
		.CURRENT_SCORE(CURRENT_SCORE)
	);
	
	

	initial begin

		CLK = 0;
		RESET = 0;
		REACHED_TARGET = 0;


		#100;
		
		forever #50 CLK = ~CLK; 
	end
	
	initial begin
		#200 RESET = 1;
		#500 RESET = 0;
		
		#1000 REACHED_TARGET = 1;
		#1 REACHED_TARGET = 0;
	
		
		#1000 REACHED_TARGET = 1;
		#1 REACHED_TARGET = 0;
		
		#1000 REACHED_TARGET = 1;
		#1 REACHED_TARGET = 0;
		
		
		#200 RESET = 1;
		#500 RESET = 0;
	end
		
      
endmodule