data/full_repos/permissive/147690299/lab/26_seq_counter/tb/testbench.sv
 line:20: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/26_seq_counter/tb/testbench.sv:15: Unsupported: Ignoring delay on this delayed statement.\n            #(t/2) clk <= ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147690299/lab/26_seq_counter/tb/testbench.sv:20: syntax error, unexpected \'@\'\n        repeat(3) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/147690299/lab/26_seq_counter/tb/testbench.sv:31: syntax error, unexpected \'@\'\n        repeat(Tmax) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/147690299/lab/26_seq_counter/tb/testbench.sv:35: Unsupported or unknown PLI call: $monitor\n    initial $monitor ("%5t value=%3d %8b", $time, value, value);\n            ^~~~~~~~\n%Error: data/full_repos/permissive/147690299/lab/26_seq_counter/tb/testbench.sv:36: Unsupported or unknown PLI call: $dumpvars\n    initial $dumpvars;\n            ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

    localparam t    = 20;
    localparam Tmax = 300;
    localparam WIDTH = 8;


    reg  clk, rst_n;

    initial begin
        clk <= 0;
        forever
            #(t/2) clk <= ~clk;
    end

    initial begin
        rst_n <= 'b0;
        repeat(3) @(posedge clk);
        rst_n <= 'b1;
    end

    wire [WIDTH-1:0] value;


    counter #(WIDTH) counter (clk, rst_n, value);


    initial begin
        repeat(Tmax) @(posedge clk);
        $finish;
    end

    initial $monitor ("%5t value=%3d %8b", $time, value, value);
    initial $dumpvars;

endmodule
module testbench;


    localparam t    = 20;
    localparam Tmax = 300;
    localparam WIDTH = 8;


    reg  clk, rst_n;

    initial begin
        clk <= 0;
        forever
            #(t/2) clk <= ~clk;
    end

    initial begin
        rst_n <= 'b0;
        repeat(3) @(posedge clk);
        rst_n <= 'b1;
    end

    wire [WIDTH-1:0] value;


    counter #(WIDTH) counter (clk, rst_n, value);


    initial begin
        repeat(Tmax) @(posedge clk);
        $finish;
    end

    initial $monitor ("%5t value=%3d %8b", $time, value, value);
    initial $dumpvars;

endmodule