data/full_repos/permissive/120518070/main/source/sarr.sv
 line:22: before: "["
data/verilator_xmls/f089ccec-672e-4271-bf20-fde66c69b9c8.xml
module sarr (
	input wire clk,
	input wire [7:0] waddr_i,
	input wire [7:0] wdata_i,
	input wire [7:0] raddr_i,
	input wire swap_i,
	input wire renable_i,
	input wire wenable_i,
	output wire [7:0] rdata_o
);

reg [255:0] [7:0] stateArray;


integer i;

always_ff @ (posedge clk)
begin








	if(wenable_i == 1)
	begin
		stateArray[waddr_i] <= wdata_i;
	end


















	else if(swap_i == 1)
	begin
		stateArray[raddr_i] <= stateArray[waddr_i];
		stateArray[waddr_i] <= stateArray[raddr_i];
	end







end

assign rdata_o = (renable_i == 1) ? stateArray[raddr_i] : 0;
endmodule
module sarr (
	input wire clk,
	input wire [7:0] waddr_i,
	input wire [7:0] wdata_i,
	input wire [7:0] raddr_i,
	input wire swap_i,
	input wire renable_i,
	input wire wenable_i,
	output wire [7:0] rdata_o
);


reg [255:0] [7:0] stateArray;


integer i;

always_ff @ (posedge clk)
begin








	if(wenable_i == 1)
	begin
		stateArray[waddr_i] <= wdata_i;
	end


















	else if(swap_i == 1)
	begin
		stateArray[raddr_i] <= stateArray[waddr_i];
		stateArray[waddr_i] <= stateArray[raddr_i];
	end







end

assign rdata_o = (renable_i == 1) ? stateArray[raddr_i] : 0;
endmodule