data/full_repos/permissive/116563702/register/regSyncReset.v
data/verilator_xmls/2410d103-728a-4454-982a-366b04d3c271.xml
module register(input clk,
		input 		 reset,
		input 		 en,
		input [3:0] 	 data,
		output reg [3:0] q);

   always @(posedge clk)
     begin
	if (reset)
	  q <= 4'b0;
	else if (en)
	  q <= data;
     end
endmodule
module register(input clk,
		input 		 reset,
		input 		 en,
		input [3:0] 	 data,
		output reg [3:0] q);


   always @(posedge clk)
     begin
	if (reset)
	  q <= 4'b0;
	else if (en)
	  q <= data;
     end
endmodule