data/full_repos/permissive/126791278/assets/registerFile_backup.v
1: b'%Warning-WIDTH: data/full_repos/permissive/126791278/assets/registerFile_backup.v:97: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'bzzzz\' generates 4 bits.\n                                                                                    : ... In instance registerFile.mux2\n   default: out<=4\'bzzzz;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/126791278/assets/registerFile_backup.v:64: Output port connection \'out\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'read_data1\' generates 16 bits.\n                                                                                    : ... In instance registerFile\n mux16to1 mux1 (read_data1, reg_out, read_reg1);\n                ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/126791278/assets/registerFile_backup.v:65: Output port connection \'out\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'read_data2\' generates 16 bits.\n                                                                                    : ... In instance registerFile\n mux16to1 mux2 (read_data2, reg_out, read_reg2);\n                ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/126791278/assets/registerFile_backup.v:143: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'out\'\n                                                                                         : ... In instance registerFile.deco\n   default: out<=16\'b0000_0000_0000_0000;\n            ^~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module registerFile (read_data1, read_data2, clk, rst, ctrl_reg_write, read_reg1, read_reg2, write_reg, write_data);
	
	output [15:0] read_data1, read_data2;
	input [3:0] read_reg1, read_reg2, write_reg;
	input [15:0] write_data;
	input clk, rst, ctrl_reg_write;
	wire [15:0] deco_out, reg_in;
	reg [15:0] reg_out [15:0];
	
	decoder4to16 deco (deco_out, write_reg);
	
	and and0 (reg_in[0], ctrl_reg_write, deco_out[0], clk);
	and and1 (reg_in[1], ctrl_reg_write, deco_out[1], clk);
	and and2 (reg_in[2], ctrl_reg_write, deco_out[2], clk);
	and and3 (reg_in[3], ctrl_reg_write, deco_out[3], clk);
	and and4 (reg_in[4], ctrl_reg_write, deco_out[4], clk);
	and and5 (reg_in[5], ctrl_reg_write, deco_out[5], clk);
	and and6 (reg_in[6], ctrl_reg_write, deco_out[6], clk);
	and and7 (reg_in[7], ctrl_reg_write, deco_out[7], clk);
	and and8 (reg_in[8], ctrl_reg_write, deco_out[8], clk);
	and and9 (reg_in[9], ctrl_reg_write, deco_out[9], clk);
	and and10 (reg_in[10], ctrl_reg_write, deco_out[10], clk);
	and and11 (reg_in[11], ctrl_reg_write, deco_out[11], clk);
	and and12 (reg_in[12], ctrl_reg_write, deco_out[12], clk);
	and and13 (reg_in[13], ctrl_reg_write, deco_out[13], clk);
	and and14 (reg_in[14], ctrl_reg_write, deco_out[14], clk);
	and and15 (reg_in[15], ctrl_reg_write, deco_out[15], clk);
	
	register_16bit r0 (reg_out[0], write_data, reg_in[0], clk, rst);
	register_16bit r1 (reg_out[1], write_data, reg_in[1], clk, rst);
	register_16bit r2 (reg_out[2], write_data, reg_in[2], clk, rst);
	register_16bit r3 (reg_out[3], write_data, reg_in[3], clk, rst);
	register_16bit r4 (reg_out[4], write_data, reg_in[4], clk, rst);
	register_16bit r5 (reg_out[5], write_data, reg_in[5], clk, rst);
	register_16bit r6 (reg_out[6], write_data, reg_in[6], clk, rst);
	register_16bit r7 (reg_out[7], write_data, reg_in[7], clk, rst);
	register_16bit r8 (reg_out[8], write_data, reg_in[8], clk, rst);
	register_16bit r9 (reg_out[9], write_data, reg_in[9], clk, rst);
	register_16bit r10 (reg_out[10], write_data, reg_in[10], clk, rst);
	register_16bit r11 (reg_out[11], write_data, reg_in[11], clk, rst);
	register_16bit r12 (reg_out[12], write_data, reg_in[12], clk, rst);
	register_16bit r13 (reg_out[13], write_data, reg_in[13], clk, rst);
	register_16bit r14 (reg_out[14], write_data, reg_in[14], clk, rst);
	register_16bit r15 (reg_out[15], write_data, reg_in[15], clk, rst);

	mux16to1 mux1 (read_data1, reg_out, read_reg1);
	mux16to1 mux2 (read_data2, reg_out, read_reg2);

endmodule
module registerFile (read_data1, read_data2, clk, rst, ctrl_reg_write, read_reg1, read_reg2, write_reg, write_data);

	
	output [15:0] read_data1, read_data2;
	input [3:0] read_reg1, read_reg2, write_reg;
	input [15:0] write_data;
	input clk, rst, ctrl_reg_write;
	wire [15:0] deco_out, reg_in;
	reg [15:0] reg_out [15:0];
	
	decoder4to16 deco (deco_out, write_reg);
	
	and and0 (reg_in[0], ctrl_reg_write, deco_out[0], clk);
	and and1 (reg_in[1], ctrl_reg_write, deco_out[1], clk);
	and and2 (reg_in[2], ctrl_reg_write, deco_out[2], clk);
	and and3 (reg_in[3], ctrl_reg_write, deco_out[3], clk);
	and and4 (reg_in[4], ctrl_reg_write, deco_out[4], clk);
	and and5 (reg_in[5], ctrl_reg_write, deco_out[5], clk);
	and and6 (reg_in[6], ctrl_reg_write, deco_out[6], clk);
	and and7 (reg_in[7], ctrl_reg_write, deco_out[7], clk);
	and and8 (reg_in[8], ctrl_reg_write, deco_out[8], clk);
	and and9 (reg_in[9], ctrl_reg_write, deco_out[9], clk);
	and and10 (reg_in[10], ctrl_reg_write, deco_out[10], clk);
	and and11 (reg_in[11], ctrl_reg_write, deco_out[11], clk);
	and and12 (reg_in[12], ctrl_reg_write, deco_out[12], clk);
	and and13 (reg_in[13], ctrl_reg_write, deco_out[13], clk);
	and and14 (reg_in[14], ctrl_reg_write, deco_out[14], clk);
	and and15 (reg_in[15], ctrl_reg_write, deco_out[15], clk);
	
	register_16bit r0 (reg_out[0], write_data, reg_in[0], clk, rst);
	register_16bit r1 (reg_out[1], write_data, reg_in[1], clk, rst);
	register_16bit r2 (reg_out[2], write_data, reg_in[2], clk, rst);
	register_16bit r3 (reg_out[3], write_data, reg_in[3], clk, rst);
	register_16bit r4 (reg_out[4], write_data, reg_in[4], clk, rst);
	register_16bit r5 (reg_out[5], write_data, reg_in[5], clk, rst);
	register_16bit r6 (reg_out[6], write_data, reg_in[6], clk, rst);
	register_16bit r7 (reg_out[7], write_data, reg_in[7], clk, rst);
	register_16bit r8 (reg_out[8], write_data, reg_in[8], clk, rst);
	register_16bit r9 (reg_out[9], write_data, reg_in[9], clk, rst);
	register_16bit r10 (reg_out[10], write_data, reg_in[10], clk, rst);
	register_16bit r11 (reg_out[11], write_data, reg_in[11], clk, rst);
	register_16bit r12 (reg_out[12], write_data, reg_in[12], clk, rst);
	register_16bit r13 (reg_out[13], write_data, reg_in[13], clk, rst);
	register_16bit r14 (reg_out[14], write_data, reg_in[14], clk, rst);
	register_16bit r15 (reg_out[15], write_data, reg_in[15], clk, rst);

	mux16to1 mux1 (read_data1, reg_out, read_reg1);
	mux16to1 mux2 (read_data2, reg_out, read_reg2);

endmodule