data/full_repos/permissive/15579276/Final_Lock.v
1: b"%Error: data/full_repos/permissive/15579276/Final_Lock.v:10: Cannot find file containing module: 'Final_Lock_sm'\n Final_Lock_sm State_Machine(clock, SoftReset, Program, B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, GREEN, RED);\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/15579276,data/full_repos/permissive/15579276/Final_Lock_sm\n             data/full_repos/permissive/15579276,data/full_repos/permissive/15579276/Final_Lock_sm.v\n             data/full_repos/permissive/15579276,data/full_repos/permissive/15579276/Final_Lock_sm.sv\n             Final_Lock_sm\n             Final_Lock_sm.v\n             Final_Lock_sm.sv\n             obj_dir/Final_Lock_sm\n             obj_dir/Final_Lock_sm.v\n             obj_dir/Final_Lock_sm.sv\n%Error: data/full_repos/permissive/15579276/Final_Lock.v:11: Cannot find file containing module: 'Clock_Divider'\n Clock_Divider Clock_Divider_1(CLOCK_50, clock);\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Final_Lock(CLOCK_50, SoftReset, Program, B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, GREEN, RED);

	input CLOCK_50;
	input SoftReset, Program;
	input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9;
	output GREEN, RED;
	
	wire clock;
	
	Final_Lock_sm State_Machine(clock, SoftReset, Program, B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, GREEN, RED);
	Clock_Divider Clock_Divider_1(CLOCK_50, clock);
endmodule
module Final_Lock(CLOCK_50, SoftReset, Program, B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, GREEN, RED);


	input CLOCK_50;
	input SoftReset, Program;
	input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9;
	output GREEN, RED;
	
	wire clock;
	
	Final_Lock_sm State_Machine(clock, SoftReset, Program, B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, GREEN, RED);
	Clock_Divider Clock_Divider_1(CLOCK_50, clock);
endmodule