data/full_repos/permissive/122184933/FPGA/delay.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/122184933/FPGA/delay.v:21: Cannot find file containing module: 'LUT4'\n   LUT4 # (.init(16'h0002)) I1 (.A(a), .B(1'b0), .C(1'b0), .D(1'b0), .Z(z));\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/LUT4\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/LUT4.v\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/LUT4.sv\n             LUT4\n             LUT4.v\n             LUT4.sv\n             obj_dir/LUT4\n             obj_dir/LUT4.v\n             obj_dir/LUT4.sv\n%Error: Exiting due to 1 error(s)\n"
module delay # (

	parameter LENGTH = 1
)
(

	input wire a,

	output wire o
);


genvar i;

generate
	for (i = 0; i < LENGTH; i = i + 1) begin : DELAY_ELEMS
		wire z;

		if (i == 0) begin
			LUT4 # (.init(16'h0002)) I1 (.A(a), .B(1'b0), .C(1'b0), .D(1'b0), .Z(z));

		end else begin
			LUT4 # (.init(16'h0002)) I1 (.A(DELAY_ELEMS[i-1].z), .B(1'b0), .C(1'b0), .D(1'b0), .Z(z));
		end
	end
endgenerate


assign o = DELAY_ELEMS[LENGTH - 1].z;

endmodule
module delay # (

	parameter LENGTH = 1
)
(

	input wire a,

	output wire o
);



genvar i;

generate
	for (i = 0; i < LENGTH; i = i + 1) begin : DELAY_ELEMS
		wire z;

		if (i == 0) begin
			LUT4 # (.init(16'h0002)) I1 (.A(a), .B(1'b0), .C(1'b0), .D(1'b0), .Z(z));

		end else begin
			LUT4 # (.init(16'h0002)) I1 (.A(DELAY_ELEMS[i-1].z), .B(1'b0), .C(1'b0), .D(1'b0), .Z(z));
		end
	end
endgenerate


assign o = DELAY_ELEMS[LENGTH - 1].z;

endmodule