data/full_repos/permissive/146073027/Simple 32bit integer ALU.v
 line:28: before: "assign"
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/146073027/Simple\n        ... Looked in:\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.sv\n             data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027/Simple.sv\n             obj_dir/data/full_repos/permissive/146073027/Simple\n             obj_dir/data/full_repos/permissive/146073027/Simple.v\n             obj_dir/data/full_repos/permissive/146073027/Simple.sv\n%Error: Cannot find file containing module: 32bit\n%Error: Cannot find file containing module: integer\n%Error: Cannot find file containing module: ALU.v\n%Error: Exiting due to 4 error(s)\n'
module four_bit_multiplicator(out,in1,in2);
  output [31:0]out;
  input [15:0]in1,in2;
  wire [15:0]t1,t2,t3,t4,t5,t6,t7,u2,u3,u4;
  wire c1,c2,c3;
  assign t1=in1 & {4{in2[0]}};
  assign t2=in1 & {4{in2[1]}};
  assign t3=in1 & {4{in2[2]}};
  assign t4=in1 & {4{in2[3]}};
  assign u2=t2<<1;
  assign u3=t3<<2;
  assign u4=t4<<3;
  
  sixteen_bit_fa sbf0(c1,t5,0,t1,u2);
  sixteen_bit_fa sbf1(c2,t6,c1,t5,u3);
  sixteen_bit_fa sbf2(c3,t7,c2,t6,u4);
  assign out={c3,t7};
endmodule
module four_bit_multiplicator(out,in1,in2);

  output [31:0]out;
  input [15:0]in1,in2;
  wire [15:0]t1,t2,t3,t4,t5,t6,t7,u2,u3,u4;
  wire c1,c2,c3;
  assign t1=in1 & {4{in2[0]}};
  assign t2=in1 & {4{in2[1]}};
  assign t3=in1 & {4{in2[2]}};
  assign t4=in1 & {4{in2[3]}};
  assign u2=t2<<1;
  assign u3=t3<<2;
  assign u4=t4<<3;
  
  sixteen_bit_fa sbf0(c1,t5,0,t1,u2);
  sixteen_bit_fa sbf1(c2,t6,c1,t5,u3);
  sixteen_bit_fa sbf2(c3,t7,c2,t6,u4);
  assign out={c3,t7};
endmodule