data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v
1: b'%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v:22: Cannot find include file: urv_defs.v\n`include "urv_defs.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v.sv\n             urv_defs.v\n             urv_defs.v.v\n             urv_defs.v.sv\n             obj_dir/urv_defs.v\n             obj_dir/urv_defs.v.v\n             obj_dir/urv_defs.v.sv\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v:64: Define or directive not defined: \'`LDST_B\'\n   `LDST_B:\n   ^~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v:64: syntax error, unexpected \':\', expecting endcase\n   `LDST_B:\n          ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v:73: Define or directive not defined: \'`LDST_BU\'\n   `LDST_BU:\n   ^~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v:82: Define or directive not defined: \'`LDST_H\'\n   `LDST_H:\n   ^~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v:89: Define or directive not defined: \'`LDST_HU\'\n   `LDST_HU:\n   ^~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v:96: Define or directive not defined: \'`LDST_L\'\n   `LDST_L: load_value <= dm_data_l_i;\n   ^~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v:103: syntax error, unexpected IDENTIFIER, expecting "\'{"\n   reg [31:0] rf_rd_value;\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v:108: Define or directive not defined: \'`RD_SOURCE_SHIFTER\'\n     else if ( x_rd_source_i == `RD_SOURCE_SHIFTER )\n                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v:110: Define or directive not defined: \'`RD_SOURCE_MULTIPLY\'\n     else if ( x_rd_source_i == `RD_SOURCE_MULTIPLY )\n                                ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_writeback.v:129: syntax error, unexpected endmodule\nendmodule  \n^~~~~~~~~\n%Error: Cannot continue\n'
module urv_writeback
  (
   input 	     clk_i,
   input 	     rst_i,

   input 	     w_stall_i,
   output 	     w_stall_req_o,
   
   input [2:0] 	     x_fun_i,
   input 	     x_load_i,
   input 	     x_store_i,
   
   input [31:0]      x_dm_addr_i,
   input [4:0] 	     x_rd_i,
   input [31:0]      x_rd_value_i,
   input 	     x_rd_write_i,
   input 	     x_valid_i,
   

   input [31:0]      x_shifter_rd_value_i,
   input [31:0]      x_multiply_rd_value_i,
   input [1:0] 	     x_rd_source_i,

   input [31:0]      dm_data_l_i,
   input 	     dm_load_done_i,
   input 	     dm_store_done_i,
   
   output [31:0]     rf_rd_value_o,
   output [4:0]      rf_rd_o,
   output 	     rf_rd_write_o
   );

   reg [31:0] 	 load_value;


   always@*
     begin
	case (x_fun_i)
	  `LDST_B:
	    case ( x_dm_addr_i [1:0] )
	      2'b00:  load_value <= {{24{dm_data_l_i[7]}}, dm_data_l_i[7:0] };
	      2'b01:  load_value <= {{24{dm_data_l_i[15]}}, dm_data_l_i[15:8] };
	      2'b10:  load_value <= {{24{dm_data_l_i[23]}}, dm_data_l_i[23:16] };
	      2'b11:  load_value <= {{24{dm_data_l_i[31]}}, dm_data_l_i[31:24] };
	      default: load_value <= 32'hx;
	    endcase
	  
	  `LDST_BU:
	    case ( x_dm_addr_i [1:0] )
	      2'b00:  load_value <= {24'h0, dm_data_l_i[7:0] };
	      2'b01:  load_value <= {24'h0, dm_data_l_i[15:8] };
	      2'b10:  load_value <= {24'h0, dm_data_l_i[23:16] };
	      2'b11:  load_value <= {24'h0, dm_data_l_i[31:24] };
	      default: load_value <= 32'hx;
	    endcase
	  
	  `LDST_H:
	    case ( x_dm_addr_i [1:0] )
	      2'b00, 2'b01: load_value <= {{16{dm_data_l_i[15]}}, dm_data_l_i[15:0] };
	      2'b10, 2'b11: load_value <= {{16{dm_data_l_i[31]}}, dm_data_l_i[31:16] };
	      default: load_value <= 32'hx;
	    endcase

	  `LDST_HU:
	    case ( x_dm_addr_i [1:0] )
	      2'b00, 2'b01:  load_value <= {16'h0, dm_data_l_i[15:0] };
	      2'b10, 2'b11:  load_value <= {16'h0, dm_data_l_i[31:16] };
	      default: load_value <= 32'hx;
	    endcase
	    
	  `LDST_L: load_value <= dm_data_l_i;

	  default: load_value <= 32'hx;
	endcase
     end

   reg rf_rd_write;
   reg [31:0] rf_rd_value;
      
   always@*
     if( x_load_i )
       rf_rd_value <= load_value;
     else if ( x_rd_source_i == `RD_SOURCE_SHIFTER )
       rf_rd_value <= x_shifter_rd_value_i;
     else if ( x_rd_source_i == `RD_SOURCE_MULTIPLY )
       rf_rd_value <= x_multiply_rd_value_i;
     else
       rf_rd_value <= x_rd_value_i;

   always@*
     if (w_stall_i)
       rf_rd_write <= 0;
     else if (x_load_i && dm_load_done_i)
       rf_rd_write <= x_valid_i;
     else
       rf_rd_write <= x_rd_write_i & x_valid_i;


   assign rf_rd_write_o = rf_rd_write;
   assign rf_rd_value_o = rf_rd_value;
   assign rf_rd_o = x_rd_i;
   assign w_stall_req_o = x_valid_i && ((x_load_i && !dm_load_done_i) || (x_store_i && !dm_store_done_i));

endmodule
module urv_writeback
  (
   input 	     clk_i,
   input 	     rst_i,

   input 	     w_stall_i,
   output 	     w_stall_req_o,
   
   input [2:0] 	     x_fun_i,
   input 	     x_load_i,
   input 	     x_store_i,
   
   input [31:0]      x_dm_addr_i,
   input [4:0] 	     x_rd_i,
   input [31:0]      x_rd_value_i,
   input 	     x_rd_write_i,
   input 	     x_valid_i,
   

   input [31:0]      x_shifter_rd_value_i,
   input [31:0]      x_multiply_rd_value_i,
   input [1:0] 	     x_rd_source_i,

   input [31:0]      dm_data_l_i,
   input 	     dm_load_done_i,
   input 	     dm_store_done_i,
   
   output [31:0]     rf_rd_value_o,
   output [4:0]      rf_rd_o,
   output 	     rf_rd_write_o
   );


   reg [31:0] 	 load_value;


   always@*
     begin
	case (x_fun_i)
	  `LDST_B:
	    case ( x_dm_addr_i [1:0] )
	      2'b00:  load_value <= {{24{dm_data_l_i[7]}}, dm_data_l_i[7:0] };
	      2'b01:  load_value <= {{24{dm_data_l_i[15]}}, dm_data_l_i[15:8] };
	      2'b10:  load_value <= {{24{dm_data_l_i[23]}}, dm_data_l_i[23:16] };
	      2'b11:  load_value <= {{24{dm_data_l_i[31]}}, dm_data_l_i[31:24] };
	      default: load_value <= 32'hx;
	    endcase
	  
	  `LDST_BU:
	    case ( x_dm_addr_i [1:0] )
	      2'b00:  load_value <= {24'h0, dm_data_l_i[7:0] };
	      2'b01:  load_value <= {24'h0, dm_data_l_i[15:8] };
	      2'b10:  load_value <= {24'h0, dm_data_l_i[23:16] };
	      2'b11:  load_value <= {24'h0, dm_data_l_i[31:24] };
	      default: load_value <= 32'hx;
	    endcase
	  
	  `LDST_H:
	    case ( x_dm_addr_i [1:0] )
	      2'b00, 2'b01: load_value <= {{16{dm_data_l_i[15]}}, dm_data_l_i[15:0] };
	      2'b10, 2'b11: load_value <= {{16{dm_data_l_i[31]}}, dm_data_l_i[31:16] };
	      default: load_value <= 32'hx;
	    endcase

	  `LDST_HU:
	    case ( x_dm_addr_i [1:0] )
	      2'b00, 2'b01:  load_value <= {16'h0, dm_data_l_i[15:0] };
	      2'b10, 2'b11:  load_value <= {16'h0, dm_data_l_i[31:16] };
	      default: load_value <= 32'hx;
	    endcase
	    
	  `LDST_L: load_value <= dm_data_l_i;

	  default: load_value <= 32'hx;
	endcase
     end

   reg rf_rd_write;
   reg [31:0] rf_rd_value;
      
   always@*
     if( x_load_i )
       rf_rd_value <= load_value;
     else if ( x_rd_source_i == `RD_SOURCE_SHIFTER )
       rf_rd_value <= x_shifter_rd_value_i;
     else if ( x_rd_source_i == `RD_SOURCE_MULTIPLY )
       rf_rd_value <= x_multiply_rd_value_i;
     else
       rf_rd_value <= x_rd_value_i;

   always@*
     if (w_stall_i)
       rf_rd_write <= 0;
     else if (x_load_i && dm_load_done_i)
       rf_rd_write <= x_valid_i;
     else
       rf_rd_write <= x_rd_write_i & x_valid_i;


   assign rf_rd_write_o = rf_rd_write;
   assign rf_rd_value_o = rf_rd_value;
   assign rf_rd_o = x_rd_i;
   assign w_stall_req_o = x_valid_i && ((x_load_i && !dm_load_done_i) || (x_store_i && !dm_store_done_i));

endmodule