data/full_repos/permissive/194626900/src/tb/tb_aes_mask_core.v
 line:115: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/194626900/src/tb/tb_aes_mask_core.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_HALF_PERIOD;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/194626900/src/tb/tb_aes_mask_core.v:112: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/194626900/src/tb/tb_aes_mask_core.v:143: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_PERIOD);\n      ^\n%Error: data/full_repos/permissive/194626900/src/tb/tb_aes_mask_core.v:75: Cannot find file containing module: \'aes_mask_core\'\n  aes_mask_core dut(\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194626900/src/tb,data/full_repos/permissive/194626900/aes_mask_core\n             data/full_repos/permissive/194626900/src/tb,data/full_repos/permissive/194626900/aes_mask_core.v\n             data/full_repos/permissive/194626900/src/tb,data/full_repos/permissive/194626900/aes_mask_core.sv\n             aes_mask_core\n             aes_mask_core.v\n             aes_mask_core.sv\n             obj_dir/aes_mask_core\n             obj_dir/aes_mask_core.v\n             obj_dir/aes_mask_core.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_aes_mask_core();




  parameter DEBUG     = 0;
  parameter DUMP_WAIT = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;





  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;

  reg            tb_monitor;
  reg            tb_clk;
  reg            tb_reset_n;
  reg            tb_init;
  reg            tb_next;
  reg            tb_finalize;
  reg [127 : 0]  tb_key;
  reg            tb_keylen;
  reg [127 : 0]  tb_block;
  wire [127 : 0] tb_result;





  aes_mask_core dut(
                    .clk(tb_clk),
                    .reset_n(tb_reset_n),

                    .init(tb_init),
                    .next(tb_next),
                    .finalize(tb_finalize),

                    .key(tb_key),
                    .keylen(tb_keylen),

                    .block(tb_block),
                    .result(tb_result)
                   );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD;
      tb_clk = !tb_clk;
    end








  always
    begin : sys_monitor
      cycle_ctr = cycle_ctr + 1;
      #(CLK_PERIOD);
      if (tb_monitor)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state;
    begin
      $display("State of DUT");
      $display("------------");
      $display("");
    end
  endtask







  task reset_dut;
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(2 * CLK_PERIOD);
      tb_reset_n = 1;
    end
  endtask







  task display_test_result;
    begin
      if (error_ctr == 0)
        begin
          $display("*** All %02d test cases completed successfully", tc_ctr);
        end
      else
        begin
          $display("*** %02d tests completed - %02d test cases did not complete successfully.",
                   tc_ctr, error_ctr);
        end
    end
  endtask








  task init_sim;
    begin
      cycle_ctr  = 0;
      error_ctr  = 0;
      tc_ctr     = 0;
      tb_monitor = 0;

      tb_clk      = 1'h0;
      tb_reset_n  = 1'h1;
      tb_keylen   = 1'h0;
      tb_init     = 1'h0;
      tb_next     = 1'h0;
      tb_finalize = 1'h0;
      tb_key      = 128'h0;
      tb_block    = 128'h0;
    end
  endtask





  task tc1;
    begin
      $display("*** TC1 started.");
      $display("*** TC1 completed.");
      $display("");
    end
  endtask







  initial
    begin : aes_mask_core_test
      $display("   -= Testbench for AES mask core started =-");
      $display("     =====================================");
      $display("");

      init_sim();
      reset_dut();

      tc1();

      display_test_result();
      $display("");
      $display("*** AES mask core simulation done. ***");
      $finish;
    end
endmodule
module tb_aes_mask_core();





  parameter DEBUG     = 0;
  parameter DUMP_WAIT = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;





  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;

  reg            tb_monitor;
  reg            tb_clk;
  reg            tb_reset_n;
  reg            tb_init;
  reg            tb_next;
  reg            tb_finalize;
  reg [127 : 0]  tb_key;
  reg            tb_keylen;
  reg [127 : 0]  tb_block;
  wire [127 : 0] tb_result;





  aes_mask_core dut(
                    .clk(tb_clk),
                    .reset_n(tb_reset_n),

                    .init(tb_init),
                    .next(tb_next),
                    .finalize(tb_finalize),

                    .key(tb_key),
                    .keylen(tb_keylen),

                    .block(tb_block),
                    .result(tb_result)
                   );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD;
      tb_clk = !tb_clk;
    end








  always
    begin : sys_monitor
      cycle_ctr = cycle_ctr + 1;
      #(CLK_PERIOD);
      if (tb_monitor)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state;
    begin
      $display("State of DUT");
      $display("------------");
      $display("");
    end
  endtask







  task reset_dut;
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(2 * CLK_PERIOD);
      tb_reset_n = 1;
    end
  endtask







  task display_test_result;
    begin
      if (error_ctr == 0)
        begin
          $display("*** All %02d test cases completed successfully", tc_ctr);
        end
      else
        begin
          $display("*** %02d tests completed - %02d test cases did not complete successfully.",
                   tc_ctr, error_ctr);
        end
    end
  endtask








  task init_sim;
    begin
      cycle_ctr  = 0;
      error_ctr  = 0;
      tc_ctr     = 0;
      tb_monitor = 0;

      tb_clk      = 1'h0;
      tb_reset_n  = 1'h1;
      tb_keylen   = 1'h0;
      tb_init     = 1'h0;
      tb_next     = 1'h0;
      tb_finalize = 1'h0;
      tb_key      = 128'h0;
      tb_block    = 128'h0;
    end
  endtask





  task tc1;
    begin
      $display("*** TC1 started.");
      $display("*** TC1 completed.");
      $display("");
    end
  endtask







  initial
    begin : aes_mask_core_test
      $display("   -= Testbench for AES mask core started =-");
      $display("     =====================================");
      $display("");

      init_sim();
      reset_dut();

      tc1();

      display_test_result();
      $display("");
      $display("*** AES mask core simulation done. ***");
      $finish;
    end
endmodule