data/full_repos/permissive/122303998/Verilog/hdlsrc/dut.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/122303998/Verilog/hdlsrc/dut.v:22: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                               : ... Top module \'s_add\'\nmodule s_add(\n       ^~~~~\n                                                                               : ... Top module \'s_mult\'\nmodule s_mult(\n       ^~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module s_mult(
  IN1 ,
  IN2 ,
  OUT );

parameter IN1WL  = 8       ;
parameter IN2WL  = 8       ;
parameter OUTWL  = IN1WL + IN2WL;


input signed [IN1WL -1:0] IN1;
input signed [IN2WL -1:0] IN2;
output signed [OUTWL-1:0] OUT;

reg   signed [OUTWL-1:0]  W_p;

always @ (IN1 or IN2) begin
  W_p = IN1 * IN2;
end

assign OUT = W_p;

endmodule
module s_mult(
  IN1 ,
  IN2 ,
  OUT );


parameter IN1WL  = 8       ;
parameter IN2WL  = 8       ;
parameter OUTWL  = IN1WL + IN2WL;


input signed [IN1WL -1:0] IN1;
input signed [IN2WL -1:0] IN2;
output signed [OUTWL-1:0] OUT;

reg   signed [OUTWL-1:0]  W_p;

always @ (IN1 or IN2) begin
  W_p = IN1 * IN2;
end

assign OUT = W_p;

endmodule