data/full_repos/permissive/199632300/HDLBits/Verification/sim/sim/circuit4.v
data/verilator_xmls/c2630367-5d1e-4536-8111-73020e7565c6.xml
module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );

    assign q = b|c; 

endmodule
module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );


    assign q = b|c; 

endmodule