data/full_repos/permissive/177038316/project.v
1: b'%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:457: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'HUNDREDS\' generates 2 bits.\n                                                                  : ... In instance top.m3\n    case(HUNDREDS)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Error: Exiting due to 5 warning(s)\n'
module keyboard(
input wire clk,
input wire data,
output reg [2:0] led,
output reg inst,
input wire ready

);
reg [7:0] data_curr;
reg [7:0] data_pre;
reg [3:0] b;
reg flag;
integer contador;
initial
begin
b<=4'h1;
flag<=1'b0;
data_curr<=8'hf0;
data_pre<=8'hf0;
led<=3'b000;
inst <= 1'b0;
contador<=0;
end
always @(negedge clk)
begin
case(b)
1:;
2:data_curr[0]<=data;
3:data_curr[1]<=data;
4:data_curr[2]<=data;
5:data_curr[3]<=data;
6:data_curr[4]<=data;
7:data_curr[5]<=data;
8:data_curr[6]<=data;
9:data_curr[7]<=data;
10:flag<=1'b1;
11:flag<=1'b0;
endcase
 if(b<=10)
 b<=b+1;
 else if(b==11)
 b<=1;
end
always@(posedge flag)
begin
	if(data_curr==8'hf0)
	begin
			if(ready) begin
				inst <= 1'b1;
				case(data_pre)
					8'h70: led<=3'b000;
					8'h69: led<=3'b001;
					8'h72: led<=3'b010;
					8'h7a: led<=3'b011;
					8'h6b: led<=3'b100;
					8'hf0: led<=3'b101;
				endcase
			end
	end

	 else
	 begin
		 inst <= 1'b0;
		 data_pre<=data_curr;
	 end
end 
endmodule
module keyboard(
input wire clk,
input wire data,
output reg [2:0] led,
output reg inst,
input wire ready

);

reg [7:0] data_curr;
reg [7:0] data_pre;
reg [3:0] b;
reg flag;
integer contador;
initial
begin
b<=4'h1;
flag<=1'b0;
data_curr<=8'hf0;
data_pre<=8'hf0;
led<=3'b000;
inst <= 1'b0;
contador<=0;
end
always @(negedge clk)
begin
case(b)
1:;
2:data_curr[0]<=data;
3:data_curr[1]<=data;
4:data_curr[2]<=data;
5:data_curr[3]<=data;
6:data_curr[4]<=data;
7:data_curr[5]<=data;
8:data_curr[6]<=data;
9:data_curr[7]<=data;
10:flag<=1'b1;
11:flag<=1'b0;
endcase
 if(b<=10)
 b<=b+1;
 else if(b==11)
 b<=1;
end
always@(posedge flag)
begin
	if(data_curr==8'hf0)
	begin
			if(ready) begin
				inst <= 1'b1;
				case(data_pre)
					8'h70: led<=3'b000;
					8'h69: led<=3'b001;
					8'h72: led<=3'b010;
					8'h7a: led<=3'b011;
					8'h6b: led<=3'b100;
					8'hf0: led<=3'b101;
				endcase
			end
	end

	 else
	 begin
		 inst <= 1'b0;
		 data_pre<=data_curr;
	 end
end 
endmodule