data/full_repos/permissive/21051978/final/src/datamemtb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:29: Cannot find include file: datamem.v\n`include "datamem.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/final/src,data/full_repos/permissive/21051978/datamem.v\n             data/full_repos/permissive/21051978/final/src,data/full_repos/permissive/21051978/datamem.v.v\n             data/full_repos/permissive/21051978/final/src,data/full_repos/permissive/21051978/datamem.v.sv\n             datamem.v\n             datamem.v.v\n             datamem.v.sv\n             obj_dir/datamem.v\n             obj_dir/datamem.v.v\n             obj_dir/datamem.v.sv\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:31: Cannot find include file: control.h\n`include "control.h" \n         ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/datamemtb.v:115: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/datamemtb.v:116: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 1;\n     ^\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:170: Define or directive not defined: \'`memnop\'\n  data_memory_control_signal=`memnop;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:170: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  data_memory_control_signal=`memnop;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/datamemtb.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #29\n  ^\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:176: Define or directive not defined: \'`memwst\'\n  data_memory_control_signal=`memwst;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:176: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  data_memory_control_signal=`memwst;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/datamemtb.v:191: Unsupported: Ignoring delay on this delayed statement.\n   #10\n   ^\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:195: Define or directive not defined: \'`memwst\'\n   data_memory_control_signal=`memwst;\n                              ^~~~~~~\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:195: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   data_memory_control_signal=`memwst;\n                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/datamemtb.v:206: Unsupported: Ignoring delay on this delayed statement.\n   #10\n   ^\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:209: Define or directive not defined: \'`memwld\'\n   data_memory_control_signal=`memwld;\n                              ^~~~~~~\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:209: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   data_memory_control_signal=`memwld;\n                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/datamemtb.v:216: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:219: Define or directive not defined: \'`memnop\'\n  data_memory_control_signal=`memnop;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:219: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  data_memory_control_signal=`memnop;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/datamemtb.v:223: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:226: Define or directive not defined: \'`memwld\'\n  data_memory_control_signal=`memwld;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/21051978/final/src/datamemtb.v:226: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  data_memory_control_signal=`memwld;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/datamemtb.v:231: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Error: Exiting due to 14 error(s), 8 warning(s)\n'
module tb_datamem ();


	


	wire [0:127] data_output;
	
	
	
	
	
	
	
	

	


	reg [0:1] data_memory_control_signal;

	reg [0:31] memory_control_address;

	reg [0:127] data_input;
	reg clock;
	reg [0:31] counter;
	
	
	
	
	
	


	integer count;
	
	
	
	
	
	
	

	

	parameter size_of_input = 6'd32;
	parameter size_of_input2 = 4'd8;
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end	
	
	
	
	
	
	
	
	
	

	

	data_mem dm (



		data_output,data_input,memory_control_address,
		clock,data_memory_control_signal);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");
		
		

		data_input=128'h71;
		memory_control_address=32'd0;
		data_memory_control_signal=`memnop;
		counter=32'd1;
		#29

		data_input=128'h72;
		memory_control_address=counter;
		data_memory_control_signal=`memwst;
		counter=counter+32'd1;


		
		
		

		

		for(count=0;count<=size_of_input2;count=count+1)
		begin
			#10

			data_input=data_input+128'd1;
			memory_control_address=counter;
			data_memory_control_signal=`memwst;

			counter=counter+32'd1;
		end

		counter=32'd1;
		


		for(count=0;count<=size_of_input2;count=count+1)
		begin
			#10
			data_input=$random;
			memory_control_address=counter;
			data_memory_control_signal=`memwld;

			counter=counter+32'd1;
		end
		
		

		#10
		data_input=$random;
		memory_control_address=counter;
		data_memory_control_signal=`memnop;


		
		#10
		data_input=$random;
		memory_control_address=counter;
		data_memory_control_signal=`memwld;

		counter=counter+32'd1;
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end
	


endmodule
module tb_datamem ();



	


	wire [0:127] data_output;
	
	
	
	
	
	
	
	

	


	reg [0:1] data_memory_control_signal;

	reg [0:31] memory_control_address;

	reg [0:127] data_input;
	reg clock;
	reg [0:31] counter;
	
	
	
	
	
	


	integer count;
	
	
	
	
	
	
	

	

	parameter size_of_input = 6'd32;
	parameter size_of_input2 = 4'd8;
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end	
	
	
	
	
	
	
	
	
	

	

	data_mem dm (



		data_output,data_input,memory_control_address,
		clock,data_memory_control_signal);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");
		
		

		data_input=128'h71;
		memory_control_address=32'd0;
		data_memory_control_signal=`memnop;
		counter=32'd1;
		#29

		data_input=128'h72;
		memory_control_address=counter;
		data_memory_control_signal=`memwst;
		counter=counter+32'd1;


		
		
		

		

		for(count=0;count<=size_of_input2;count=count+1)
		begin
			#10

			data_input=data_input+128'd1;
			memory_control_address=counter;
			data_memory_control_signal=`memwst;

			counter=counter+32'd1;
		end

		counter=32'd1;
		


		for(count=0;count<=size_of_input2;count=count+1)
		begin
			#10
			data_input=$random;
			memory_control_address=counter;
			data_memory_control_signal=`memwld;

			counter=counter+32'd1;
		end
		
		

		#10
		data_input=$random;
		memory_control_address=counter;
		data_memory_control_signal=`memnop;


		
		#10
		data_input=$random;
		memory_control_address=counter;
		data_memory_control_signal=`memwld;

		counter=counter+32'd1;
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end
	


endmodule