data/full_repos/permissive/211878730/atlys/practice/onehotconter_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/onehotconter_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n  forever #1 clk = !clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/onehotconter_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #4;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/onehotconter_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/onehotconter_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Error: data/full_repos/permissive/211878730/atlys/practice/onehotconter_test.v:14: Cannot find file containing module: \'onehotcounter\'\n onehotcounter uut (\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/onehotcounter\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/onehotcounter.v\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/onehotcounter.sv\n             onehotcounter\n             onehotcounter.v\n             onehotcounter.sv\n             obj_dir/onehotcounter\n             obj_dir/onehotcounter.v\n             obj_dir/onehotcounter.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module onehotconter_test;


	reg clk;
	reg reset;


	wire [3:0] q;


	onehotcounter uut (
		.clk(clk), 
		.reset(reset), 
		.q(q)
	);

	initial begin

		clk = 0;
		forever #1 clk = !clk;
	end

	initial begin
		reset = 0;
		#4;
		reset = 1;
		#2;
		reset = 0;
		#2;
	end
endmodule
module onehotconter_test;



	reg clk;
	reg reset;


	wire [3:0] q;


	onehotcounter uut (
		.clk(clk), 
		.reset(reset), 
		.q(q)
	);

	initial begin

		clk = 0;
		forever #1 clk = !clk;
	end

	initial begin
		reset = 0;
		#4;
		reset = 1;
		#2;
		reset = 0;
		#2;
	end
endmodule