data/full_repos/permissive/170402453/PhaseDetectorTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/170402453/PhaseDetectorTest.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/170402453/PhaseDetectorTest.v:65: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Error: data/full_repos/permissive/170402453/PhaseDetectorTest.v:41: Cannot find file containing module: \'PhaseDetector\'\n PhaseDetector uut (\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/PhaseDetector\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/PhaseDetector.v\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/PhaseDetector.sv\n             PhaseDetector\n             PhaseDetector.v\n             PhaseDetector.sv\n             obj_dir/PhaseDetector\n             obj_dir/PhaseDetector.v\n             obj_dir/PhaseDetector.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PhaseDetectorTest;


	reg CLK;
	reg Phase1;
	reg Phase2;
	reg initialSLEEP;
	
	integer CC, CC2, CC3;


	wire [15:0] PhaseOUT;
	wire LeftFirst;
	wire SignalDetect;


	PhaseDetector uut (
		.CLK(CLK), 
		.Phase1(Phase1), 
		.Phase2(Phase2), 
		.PhaseOUT(PhaseOUT), 
		.LeftFirst(LeftFirst), 
		.SignalDetect(SignalDetect)
	);

	initial begin

		CLK = 0;
		Phase1 = 0;
		Phase2 = 0;
		CC = 0;
		CC2 = 0;
		initialSLEEP = 1;
		CC3 = 0;


		#100;
		
		while(1) begin
			CLK = ~CLK;
			#10;
			

			if(CC >= 2632) begin
				CC = 0;
				Phase1 = ~Phase1;
			end
			
			if(CC3 >= 2632) begin
				initialSLEEP = 0;
			end
			
			if(CC2 >= 2632) begin
				CC2 = 0;
				Phase2 = ~Phase2;
			end
			
			CC = CC+1;
			CC3 = CC3+1;
			if(~initialSLEEP) begin
				CC2 = CC2+1;
			end
		end
        


	end
      
endmodule
module PhaseDetectorTest;



	reg CLK;
	reg Phase1;
	reg Phase2;
	reg initialSLEEP;
	
	integer CC, CC2, CC3;


	wire [15:0] PhaseOUT;
	wire LeftFirst;
	wire SignalDetect;


	PhaseDetector uut (
		.CLK(CLK), 
		.Phase1(Phase1), 
		.Phase2(Phase2), 
		.PhaseOUT(PhaseOUT), 
		.LeftFirst(LeftFirst), 
		.SignalDetect(SignalDetect)
	);

	initial begin

		CLK = 0;
		Phase1 = 0;
		Phase2 = 0;
		CC = 0;
		CC2 = 0;
		initialSLEEP = 1;
		CC3 = 0;


		#100;
		
		while(1) begin
			CLK = ~CLK;
			#10;
			

			if(CC >= 2632) begin
				CC = 0;
				Phase1 = ~Phase1;
			end
			
			if(CC3 >= 2632) begin
				initialSLEEP = 0;
			end
			
			if(CC2 >= 2632) begin
				CC2 = 0;
				Phase2 = ~Phase2;
			end
			
			CC = CC+1;
			CC3 = CC3+1;
			if(~initialSLEEP) begin
				CC2 = CC2+1;
			end
		end
        


	end
      
endmodule