data/full_repos/permissive/168395472/labs/07_uart/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/168395472/labs/07_uart/top.v:7: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                         : ... In instance top\nreg [15:0]cnt = 24\'b0;\n                ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/168395472/labs/07_uart/top.v:12: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 16 bits.\n                                                                          : ... In instance top\n    if (cnt == 24\'b0) begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/168395472/labs/07_uart/top.v:19: Operator ADD expects 24 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 16 bits.\n                                                                          : ... In instance top\n    cnt <= cnt + 24\'b1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/168395472/labs/07_uart/top.v:19: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 24 bits.\n                                                                          : ... In instance top\n    cnt <= cnt + 24\'b1;\n        ^~\n%Error: data/full_repos/permissive/168395472/labs/07_uart/top.v:24: Cannot find file containing module: \'rom\'\nrom rom(rom_addr, CLK, uart_data);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/168395472/labs/07_uart,data/full_repos/permissive/168395472/rom\n             data/full_repos/permissive/168395472/labs/07_uart,data/full_repos/permissive/168395472/rom.v\n             data/full_repos/permissive/168395472/labs/07_uart,data/full_repos/permissive/168395472/rom.sv\n             rom\n             rom.v\n             rom.sv\n             obj_dir/rom\n             obj_dir/rom.v\n             obj_dir/rom.sv\n%Error: data/full_repos/permissive/168395472/labs/07_uart/top.v:26: Cannot find file containing module: \'uart_tx\'\nuart_tx uart_tx(CLK, uart_start, uart_data, TXD);\n^~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module top(
    input CLK,

    output TXD
);

reg [15:0]cnt = 24'b0;
reg [2:0]rom_addr = 3'b111;
reg uart_start = 1'b0;

always @(posedge CLK) begin
    if (cnt == 24'b0) begin
        rom_addr <= rom_addr + 3'b1;
        uart_start <= 1'b1;
    end
    else
        uart_start <= 1'b0;

    cnt <= cnt + 24'b1;
end

wire [7:0]uart_data;

rom rom(rom_addr, CLK, uart_data);

uart_tx uart_tx(CLK, uart_start, uart_data, TXD);

endmodule
module top(
    input CLK,

    output TXD
);


reg [15:0]cnt = 24'b0;
reg [2:0]rom_addr = 3'b111;
reg uart_start = 1'b0;

always @(posedge CLK) begin
    if (cnt == 24'b0) begin
        rom_addr <= rom_addr + 3'b1;
        uart_start <= 1'b1;
    end
    else
        uart_start <= 1'b0;

    cnt <= cnt + 24'b1;
end

wire [7:0]uart_data;

rom rom(rom_addr, CLK, uart_data);

uart_tx uart_tx(CLK, uart_start, uart_data, TXD);

endmodule