data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v
 line:53: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clock = ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:23: Cannot find file containing module: \'ram\'\nram #(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/ram\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/ram.v\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/ram.sv\n             ram\n             ram.v\n             ram.sv\n             obj_dir/ram\n             obj_dir/ram.v\n             obj_dir/ram.sv\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ram_tb.v:47: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                               : ... In instance ram_tb\n  d_write_data = 16\'d0;\n               ^\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram_tb();

parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;

reg  clock;


reg  [ADDR_WIDTH-1:0] i_address;
wire [DATA_WIDTH-1:0] i_read_data;


reg  wEn;
reg  [ADDR_WIDTH-1:0] d_address;
reg  [DATA_WIDTH-1:0] d_write_data;
wire [DATA_WIDTH-1:0] d_read_data;


ram #(
  .DATA_WIDTH(DATA_WIDTH),
  .ADDR_WIDTH(ADDR_WIDTH)
) uut (
  .clock(clock),


  .i_address(i_address),
  .i_read_data(i_read_data),


  .wEn(wEn),
  .d_address(d_address),
  .d_write_data(d_write_data),
  .d_read_data(d_read_data)

);

always #5 clock = ~clock;


initial begin
  clock = 1'b1;
  d_address = 16'd0;
  d_write_data = 16'd0;
  wEn = 1'b0;

  #10
  wEn = 1'b1;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  d_write_data = 1;
  d_address = 4;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  d_write_data = 2;
  d_address = 8;
  #10
  $display("Data Address %d: %h", d_address, d_read_data); 



  d_write_data = 6;
  d_address = 9;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  wEn=0;
  d_write_data = 4;
  d_address = 8;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  d_write_data = 4;
  d_address = 4;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  d_address = 8;
  i_address = 4;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  $display("Data Address %d: %h", i_address, i_read_data);
  d_address = 2**16-1;
  i_address = 2**16-1;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  $display("Data Address %d: %h", i_address, i_read_data); 
  wEn=1;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  $display("Data Address %d: %h", i_address, i_read_data);
  d_address = 2**16;
  i_address = 2**16;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  $display("Data Address %d: %h", i_address, i_read_data); 
  #100
  $stop();

end

endmodule
module ram_tb();


parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;

reg  clock;


reg  [ADDR_WIDTH-1:0] i_address;
wire [DATA_WIDTH-1:0] i_read_data;


reg  wEn;
reg  [ADDR_WIDTH-1:0] d_address;
reg  [DATA_WIDTH-1:0] d_write_data;
wire [DATA_WIDTH-1:0] d_read_data;


ram #(
  .DATA_WIDTH(DATA_WIDTH),
  .ADDR_WIDTH(ADDR_WIDTH)
) uut (
  .clock(clock),


  .i_address(i_address),
  .i_read_data(i_read_data),


  .wEn(wEn),
  .d_address(d_address),
  .d_write_data(d_write_data),
  .d_read_data(d_read_data)

);

always #5 clock = ~clock;


initial begin
  clock = 1'b1;
  d_address = 16'd0;
  d_write_data = 16'd0;
  wEn = 1'b0;

  #10
  wEn = 1'b1;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  d_write_data = 1;
  d_address = 4;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  d_write_data = 2;
  d_address = 8;
  #10
  $display("Data Address %d: %h", d_address, d_read_data); 



  d_write_data = 6;
  d_address = 9;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  wEn=0;
  d_write_data = 4;
  d_address = 8;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  d_write_data = 4;
  d_address = 4;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  d_address = 8;
  i_address = 4;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  $display("Data Address %d: %h", i_address, i_read_data);
  d_address = 2**16-1;
  i_address = 2**16-1;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  $display("Data Address %d: %h", i_address, i_read_data); 
  wEn=1;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  $display("Data Address %d: %h", i_address, i_read_data);
  d_address = 2**16;
  i_address = 2**16;
  #10
  $display("Data Address %d: %h", d_address, d_read_data);
  $display("Data Address %d: %h", i_address, i_read_data); 
  #100
  $stop();

end

endmodule