data/full_repos/permissive/122777989/test/uart_tx/uart_tx_reset_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_reset_test.v:27: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clock_i <= ~clock_i;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_reset_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #1 reset_i = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_reset_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_reset_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #24 if (!busy_o)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_reset_test.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #2 if (busy_o)\n  ^\n%Error: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_reset_test.v:14: Cannot find file containing module: \'UartTx\'\nUartTx uart_tx (\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122777989/test/uart_tx,data/full_repos/permissive/122777989/UartTx\n             data/full_repos/permissive/122777989/test/uart_tx,data/full_repos/permissive/122777989/UartTx.v\n             data/full_repos/permissive/122777989/test/uart_tx,data/full_repos/permissive/122777989/UartTx.sv\n             UartTx\n             UartTx.v\n             UartTx.sv\n             obj_dir/UartTx\n             obj_dir/UartTx.v\n             obj_dir/UartTx.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UartTxResetTest ();

reg reset_i = 1'b0;
reg clock_i = 1'b0;
reg write_i = 1'b0;
reg two_stop_bits_i = 1'b0;
reg parity_bit_i = 1'b0;
reg parity_even_i = 1'b0;
reg [15:0] clock_divider_i = 0;
reg [7:0] data_i = 8'h00;
wire serial_o;
wire busy_o;

UartTx uart_tx (
  .reset_i(reset_i),
  .clock_i(clock_i),
  .write_i(write_i),
  .two_stop_bits_i(two_stop_bits_i),
  .parity_bit_i(parity_bit_i),
  .parity_even_i(parity_even_i),
  .clock_divider_i(clock_divider_i),
  .data_i(data_i),
  .serial_o(serial_o),
  .busy_o(busy_o)
);

always #1 clock_i <= ~clock_i;

always @ (*) begin
  if (reset_i) begin
    if (!busy_o)
      $display("FAILED - busy_o should be high when reset_i is high");

    if (!serial_o)
      $display("FAILED - serial_o should be high when reset_i is high");
  end
end

initial begin
  #1 reset_i = 1'b1;

  #1
  if (!busy_o)
    $display("FAILED - Should be busy during reset_i");

  reset_i = 1'b0;

  #24 if (!busy_o)
    $display("FAILED - Should wait one packet length after reset");

  #2 if (busy_o)
    $display("FAILED - busy_o should go low after reset wait time");
end

endmodule
module UartTxResetTest ();


reg reset_i = 1'b0;
reg clock_i = 1'b0;
reg write_i = 1'b0;
reg two_stop_bits_i = 1'b0;
reg parity_bit_i = 1'b0;
reg parity_even_i = 1'b0;
reg [15:0] clock_divider_i = 0;
reg [7:0] data_i = 8'h00;
wire serial_o;
wire busy_o;

UartTx uart_tx (
  .reset_i(reset_i),
  .clock_i(clock_i),
  .write_i(write_i),
  .two_stop_bits_i(two_stop_bits_i),
  .parity_bit_i(parity_bit_i),
  .parity_even_i(parity_even_i),
  .clock_divider_i(clock_divider_i),
  .data_i(data_i),
  .serial_o(serial_o),
  .busy_o(busy_o)
);

always #1 clock_i <= ~clock_i;

always @ (*) begin
  if (reset_i) begin
    if (!busy_o)
      $display("FAILED - busy_o should be high when reset_i is high");

    if (!serial_o)
      $display("FAILED - serial_o should be high when reset_i is high");
  end
end

initial begin
  #1 reset_i = 1'b1;

  #1
  if (!busy_o)
    $display("FAILED - Should be busy during reset_i");

  reset_i = 1'b0;

  #24 if (!busy_o)
    $display("FAILED - Should wait one packet length after reset");

  #2 if (busy_o)
    $display("FAILED - busy_o should go low after reset wait time");
end

endmodule