data/full_repos/permissive/104269513/ALU_final_smaller.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:416: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:422: Unsupported: Ignoring delay on this delayed statement.\n#99\n^\n%Error: data/full_repos/permissive/104269513/ALU_final_smaller.v:424: Too many digits for 32 bit number: \'hFFFF_FFFF_FFFF_FFFF\nA=\'hFFFF_FFFF_FFFF_FFFF;\n  ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:428: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:431: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:434: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:437: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:440: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:443: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:446: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_ctrl(input [63:0] A,
				input [63:0] B,
				input [3:0] cmd,
				output [31:0] psw,
				output reg [63:0] Data_out);






wire [63:0] Data_out6;
wire [63:0] Data_out7;
wire [63:0] Data_out8;					  


			

						
			shift_L_register alu7(.data_in(A), .shamt(B), .data_out(Data_out6));

			shift_R_register alu8(.data_in(A), .shamt(B), .data_out(Data_out7));
			
			shift_RA_register alu9(.data_in(A), .shamt(B), .data_out(Data_out8));
					
			
always @ (*)
begin

	case (cmd)
		
		`ADD:
		Data_out = A + B;
		
		`SUB:
		Data_out = A - B;
		
		`AND:
		Data_out = A & B;
		
		`OR:
		Data_out = A | B;
		
		`NOT:
		Data_out = ~A;
		
		`SHIFT_L:
		Data_out = Data_out6;
		
		`SHIFT_R:
		Data_out = Data_out7;
		
		`SHIFT_RA:
		Data_out = Data_out8;						 

		default:
		Data_out = 64'h0;
	
	endcase

end			
			

endmodule
module ALU_ctrl(input [63:0] A,
				input [63:0] B,
				input [3:0] cmd,
				output [31:0] psw,
				output reg [63:0] Data_out);







wire [63:0] Data_out6;
wire [63:0] Data_out7;
wire [63:0] Data_out8;					  


			

						
			shift_L_register alu7(.data_in(A), .shamt(B), .data_out(Data_out6));

			shift_R_register alu8(.data_in(A), .shamt(B), .data_out(Data_out7));
			
			shift_RA_register alu9(.data_in(A), .shamt(B), .data_out(Data_out8));
					
			
always @ (*)
begin

	case (cmd)
		
		`ADD:
		Data_out = A + B;
		
		`SUB:
		Data_out = A - B;
		
		`AND:
		Data_out = A & B;
		
		`OR:
		Data_out = A | B;
		
		`NOT:
		Data_out = ~A;
		
		`SHIFT_L:
		Data_out = Data_out6;
		
		`SHIFT_R:
		Data_out = Data_out7;
		
		`SHIFT_RA:
		Data_out = Data_out8;						 

		default:
		Data_out = 64'h0;
	
	endcase

end			
			

endmodule