data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v
None: at end of input
1: b'%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:4: Cannot find include file: sm_cpu.vh\n`include "sm_cpu.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/lab_11/src/testbench,data/full_repos/permissive/110151336/sm_cpu.vh\n             data/full_repos/permissive/110151336/lab_11/src/testbench,data/full_repos/permissive/110151336/sm_cpu.vh.v\n             data/full_repos/permissive/110151336/lab_11/src/testbench,data/full_repos/permissive/110151336/sm_cpu.vh.sv\n             sm_cpu.vh\n             sm_cpu.vh.v\n             sm_cpu.vh.sv\n             obj_dir/sm_cpu.vh\n             obj_dir/sm_cpu.vh.v\n             obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:34: syntax error, unexpected \'.\', expecting \'=\'\n    defparam sm_top.sm_clk_divider.bypass = 1;\n                                  ^\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:55: syntax error, unexpected \'@\'\n        repeat (4)  @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:97: Define or directive not defined: \'`C_SPEC\'\n                { `C_SPEC,  `F_ADDU } : $write ("addu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n                  ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:97: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                { `C_SPEC,  `F_ADDU } : $write ("addu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n                         ^\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:97: Define or directive not defined: \'`F_ADDU\'\n                { `C_SPEC,  `F_ADDU } : $write ("addu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n                            ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:98: Define or directive not defined: \'`C_SPEC\'\n                { `C_SPEC,  `F_OR   } : $write ("or    $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n                  ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:98: Define or directive not defined: \'`F_OR\'\n                { `C_SPEC,  `F_OR   } : $write ("or    $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n                            ^~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:99: Define or directive not defined: \'`C_SPEC\'\n                { `C_SPEC,  `F_SRL  } : $write ("srl   $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n                  ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:99: Define or directive not defined: \'`F_SRL\'\n                { `C_SPEC,  `F_SRL  } : $write ("srl   $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n                            ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:100: Define or directive not defined: \'`C_SPEC\'\n                { `C_SPEC,  `F_SLTU } : $write ("sltu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n                  ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:100: Define or directive not defined: \'`F_SLTU\'\n                { `C_SPEC,  `F_SLTU } : $write ("sltu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n                            ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:101: Define or directive not defined: \'`C_SPEC\'\n                { `C_SPEC,  `F_SUBU } : $write ("subu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n                  ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:101: Define or directive not defined: \'`F_SUBU\'\n                { `C_SPEC,  `F_SUBU } : $write ("subu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);\n                            ^~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:103: Define or directive not defined: \'`C_ADDIU\'\n                { `C_ADDIU, `F_ANY  } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:103: Define or directive not defined: \'`F_ANY\'\n                { `C_ADDIU, `F_ANY  } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);\n                            ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:104: Define or directive not defined: \'`C_LUI\'\n                { `C_LUI,   `F_ANY  } : $write ("lui   $%1d, %1d",       cmdRt, cmdImm);\n                  ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:104: Define or directive not defined: \'`F_ANY\'\n                { `C_LUI,   `F_ANY  } : $write ("lui   $%1d, %1d",       cmdRt, cmdImm);\n                            ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:106: Define or directive not defined: \'`C_BEQ\'\n                { `C_BEQ,   `F_ANY  } : $write ("beq   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);\n                  ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:106: Define or directive not defined: \'`F_ANY\'\n                { `C_BEQ,   `F_ANY  } : $write ("beq   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);\n                            ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:107: Define or directive not defined: \'`C_BNE\'\n                { `C_BNE,   `F_ANY  } : $write ("bne   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);\n                  ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:107: Define or directive not defined: \'`F_ANY\'\n                { `C_BNE,   `F_ANY  } : $write ("bne   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);\n                            ^~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/testbench/testbench.v:137: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module sm_testbench;


    parameter Tt     = 20;

    reg         clk;
    reg         rst_n;
    reg  [ 4:0] regAddr;
    wire [31:0] regData;
    wire        cpuClk;



    sm_top sm_top
    (
        .clkIn     ( clk     ),
        .rst_n     ( rst_n   ),
        .clkDevide ( 4'b0    ),
        .clkEnable ( 1'b1    ),
        .clk       ( cpuClk  ),
        .regAddr   ( regAddr ),
        .regData   ( regData )
    );

    defparam sm_top.sm_clk_divider.bypass = 1;



`ifdef ICARUS

    initial $dumpvars;
    genvar k;
    for (k = 0; k < 32; k = k + 1) begin
        initial $dumpvars(0, sm_top.sm_cpu.rf.rf[k]);
    end
`endif


    initial begin
        clk = 0;
        forever clk = #(Tt/2) ~clk;
    end

    initial begin
        rst_n   = 0;
        repeat (4)  @(posedge clk);
        rst_n   = 1;
    end


    integer i;
    initial begin
        for (i = 0; i < 32; i = i + 1)
            sm_top.sm_cpu.rf.rf[i] = 0;
    end

    task disasmInstr
    (
        input [31:0] instr
    );
        reg        [ 5:0] cmdOper;
        reg        [ 5:0] cmdFunk;
        reg        [ 4:0] cmdRs;
        reg        [ 4:0] cmdRt;
        reg        [ 4:0] cmdRd;
        reg        [ 4:0] cmdSa;
        reg        [15:0] cmdImm;
        reg signed [15:0] cmdImmS;

        begin
            cmdOper = instr[31:26];
            cmdFunk = instr[ 5:0 ];
            cmdRs   = instr[25:21];
            cmdRt   = instr[20:16];
            cmdRd   = instr[15:11];
            cmdSa   = instr[10:6 ];
            cmdImm  = instr[15:0 ];
            cmdImmS = instr[15:0 ];

            $write("   ");

            casez( {cmdOper,cmdFunk} )
                default               : if (instr == 32'b0) 
                                            $write ("nop");
                                        else
                                            $write ("new/unknown");

                { `C_SPEC,  `F_ADDU } : $write ("addu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
                { `C_SPEC,  `F_OR   } : $write ("or    $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
                { `C_SPEC,  `F_SRL  } : $write ("srl   $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
                { `C_SPEC,  `F_SLTU } : $write ("sltu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
                { `C_SPEC,  `F_SUBU } : $write ("subu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);

                { `C_ADDIU, `F_ANY  } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);
                { `C_LUI,   `F_ANY  } : $write ("lui   $%1d, %1d",       cmdRt, cmdImm);

                { `C_BEQ,   `F_ANY  } : $write ("beq   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
                { `C_BNE,   `F_ANY  } : $write ("bne   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
            endcase
        end

    endtask



    integer cycle; initial cycle = 0;

    initial regAddr = 0;

    always @ (posedge clk)
    begin
        $write ("%5d  pc = %2d  pcaddr = %h  instr = %h   v0 = %1d", 
                  cycle, regData, (regData << 2), sm_top.sm_cpu.instr, sm_top.sm_cpu.rf.rf[2]);

        disasmInstr(sm_top.sm_cpu.instr);

        $write("\n");

        cycle = cycle + 1;

        if (cycle > `SIMULATION_CYCLES)
        begin
            $display ("Timeout");
            $stop;
        end
    end

endmodule
module sm_testbench;



    parameter Tt     = 20;

    reg         clk;
    reg         rst_n;
    reg  [ 4:0] regAddr;
    wire [31:0] regData;
    wire        cpuClk;



    sm_top sm_top
    (
        .clkIn     ( clk     ),
        .rst_n     ( rst_n   ),
        .clkDevide ( 4'b0    ),
        .clkEnable ( 1'b1    ),
        .clk       ( cpuClk  ),
        .regAddr   ( regAddr ),
        .regData   ( regData )
    );

    defparam sm_top.sm_clk_divider.bypass = 1;



`ifdef ICARUS

    initial $dumpvars;
    genvar k;
    for (k = 0; k < 32; k = k + 1) begin
        initial $dumpvars(0, sm_top.sm_cpu.rf.rf[k]);
    end
`endif


    initial begin
        clk = 0;
        forever clk = #(Tt/2) ~clk;
    end

    initial begin
        rst_n   = 0;
        repeat (4)  @(posedge clk);
        rst_n   = 1;
    end


    integer i;
    initial begin
        for (i = 0; i < 32; i = i + 1)
            sm_top.sm_cpu.rf.rf[i] = 0;
    end

    task disasmInstr
    (
        input [31:0] instr
    );
        reg        [ 5:0] cmdOper;
        reg        [ 5:0] cmdFunk;
        reg        [ 4:0] cmdRs;
        reg        [ 4:0] cmdRt;
        reg        [ 4:0] cmdRd;
        reg        [ 4:0] cmdSa;
        reg        [15:0] cmdImm;
        reg signed [15:0] cmdImmS;

        begin
            cmdOper = instr[31:26];
            cmdFunk = instr[ 5:0 ];
            cmdRs   = instr[25:21];
            cmdRt   = instr[20:16];
            cmdRd   = instr[15:11];
            cmdSa   = instr[10:6 ];
            cmdImm  = instr[15:0 ];
            cmdImmS = instr[15:0 ];

            $write("   ");

            casez( {cmdOper,cmdFunk} )
                default               : if (instr == 32'b0) 
                                            $write ("nop");
                                        else
                                            $write ("new/unknown");

                { `C_SPEC,  `F_ADDU } : $write ("addu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
                { `C_SPEC,  `F_OR   } : $write ("or    $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
                { `C_SPEC,  `F_SRL  } : $write ("srl   $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
                { `C_SPEC,  `F_SLTU } : $write ("sltu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
                { `C_SPEC,  `F_SUBU } : $write ("subu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);

                { `C_ADDIU, `F_ANY  } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);
                { `C_LUI,   `F_ANY  } : $write ("lui   $%1d, %1d",       cmdRt, cmdImm);

                { `C_BEQ,   `F_ANY  } : $write ("beq   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
                { `C_BNE,   `F_ANY  } : $write ("bne   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
            endcase
        end

    endtask



    integer cycle; initial cycle = 0;

    initial regAddr = 0;

    always @ (posedge clk)
    begin
        $write ("%5d  pc = %2d  pcaddr = %h  instr = %h   v0 = %1d", 
                  cycle, regData, (regData << 2), sm_top.sm_cpu.instr, sm_top.sm_cpu.rf.rf[2]);

        disasmInstr(sm_top.sm_cpu.instr);

        $write("\n");

        cycle = cycle + 1;

        if (cycle > `SIMULATION_CYCLES)
        begin
            $display ("Timeout");
            $stop;
        end
    end

endmodule