data/full_repos/permissive/189158922/verilog_src/signals.v
 line:61: before: "*"
1: b'%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/signals.v:62: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                             : ... In instance top\n  assign \\$12  = width_temp == (* src = "signals.py:73" *) 2\'h2;\n                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/signals.v:64: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                             : ... In instance top\n  assign \\$17  = width_temp == (* src = "signals.py:73" *) 2\'h2;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/signals.v:65: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                             : ... In instance top\n  assign \\$19  = height_temp == (* src = "signals.py:84" *) 1\'h0;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/signals.v:66: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                             : ... In instance top\n  assign \\$21  = width_temp == (* src = "signals.py:84" *) 3\'h4;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/signals.v:68: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                             : ... In instance top\n  assign \\$25  = height_temp == (* src = "signals.py:84" *) 1\'h0;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/signals.v:69: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                             : ... In instance top\n  assign \\$27  = width_temp == (* src = "signals.py:84" *) 3\'h4;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/signals.v:70: Operator SUB expects 17 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                             : ... In instance top\n  assign \\$2  = width - (* src = "signals.py:65" *) 2\'h2;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/signals.v:72: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                             : ... In instance top\n  assign \\$4  = width_temp == (* src = "signals.py:73" *) 2\'h2;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/signals.v:73: Operator SUB expects 17 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                             : ... In instance top\n  assign \\$7  = width_temp - (* src = "signals.py:81" *) 2\'h2;\n                           ^\n%Error: Exiting due to 9 warning(s)\n'
module top(width, height, rst, clk, end_of_frame, new_row, new_input);
  wire [16:0] \$1 ;
  wire [16:0] \$10 ;
  wire \$12 ;
  wire [16:0] \$14 ;
  wire [16:0] \$15 ;
  wire \$17 ;
  wire \$19 ;
  wire [16:0] \$2 ;
  wire \$21 ;
  wire \$23 ;
  wire \$25 ;
  wire \$27 ;
  wire \$29 ;
  wire \$4 ;
  wire [16:0] \$6 ;
  wire [16:0] \$7 ;
  wire [16:0] \$9 ;
  (* src = "signals.py:45" *)
  reg \$next\end_of_frame ;
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] \$next\fsm_state ;
  (* src = "signals.py:57" *)
  reg [15:0] \$next\height_temp ;
  (* src = "signals.py:46" *)
  reg \$next\new_row ;
  (* src = "signals.py:56" *)
  reg [15:0] \$next\width_temp ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* init = 1'h0 *)
  (* src = "signals.py:45" *)
  output end_of_frame;
  reg end_of_frame = 1'h0;
  (* init = 2'h0 *)
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] fsm_state = 2'h0;
  (* src = "signals.py:41" *)
  input [15:0] height;
  (* init = 16'h0000 *)
  (* src = "signals.py:57" *)
  reg [15:0] height_temp = 16'h0000;
  (* src = "signals.py:43" *)
  input new_input;
  (* init = 1'h1 *)
  (* src = "signals.py:46" *)
  output new_row;
  reg new_row = 1'h1;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "signals.py:42" *)
  input [15:0] width;
  (* init = 16'h0000 *)
  (* src = "signals.py:56" *)
  reg [15:0] width_temp = 16'h0000;
  assign \$10  = height - (* src = "signals.py:66" *) 1'h1;
  assign \$12  = width_temp == (* src = "signals.py:73" *) 2'h2;
  assign \$15  = height_temp - (* src = "signals.py:76" *) 1'h1;
  assign \$17  = width_temp == (* src = "signals.py:73" *) 2'h2;
  assign \$19  = height_temp == (* src = "signals.py:84" *) 1'h0;
  assign \$21  = width_temp == (* src = "signals.py:84" *) 3'h4;
  assign \$23  = \$19  & (* src = "signals.py:84" *) \$21 ;
  assign \$25  = height_temp == (* src = "signals.py:84" *) 1'h0;
  assign \$27  = width_temp == (* src = "signals.py:84" *) 3'h4;
  assign \$2  = width - (* src = "signals.py:65" *) 2'h2;
  assign \$29  = \$25  & (* src = "signals.py:84" *) \$27 ;
  assign \$4  = width_temp == (* src = "signals.py:73" *) 2'h2;
  assign \$7  = width_temp - (* src = "signals.py:81" *) 2'h2;
  always @(posedge clk)
      end_of_frame <= \$next\end_of_frame ;
  always @(posedge clk)
      fsm_state <= \$next\fsm_state ;
  always @(posedge clk)
      new_row <= \$next\new_row ;
  always @(posedge clk)
      height_temp <= \$next\height_temp ;
  always @(posedge clk)
      width_temp <= \$next\width_temp ;
  always @* begin
    \$next\width_temp  = width_temp;
    casez (fsm_state)
      2'h0:
          casez (new_input)
            1'h1:
                \$next\width_temp  = \$1 [15:0];
          endcase
      2'h1:
          casez (new_input)
            1'h1:
                casez (\$4 )
                  1'h1:
                      \$next\width_temp  = width;
                  1'hz:
                      \$next\width_temp  = \$6 [15:0];
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\width_temp  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\height_temp  = height_temp;
    casez (fsm_state)
      2'h0:
          casez (new_input)
            1'h1:
                \$next\height_temp  = \$9 [15:0];
          endcase
      2'h1:
          casez (new_input)
            1'h1:
                casez (\$12 )
                  1'h1:
                      \$next\height_temp  = \$14 [15:0];
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\height_temp  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\new_row  = new_row;
    casez (fsm_state)
      2'h0:
          casez (new_input)
            1'h1:
                \$next\new_row  = 1'h0;
          endcase
      2'h1:
          casez (new_input)
            1'h1:
                casez (\$17 )
                  1'h1:
                      \$next\new_row  = 1'h1;
                  1'hz:
                      \$next\new_row  = 1'h0;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\new_row  = 1'h1;
    endcase
  end
  always @* begin
    \$next\fsm_state  = fsm_state;
    casez (fsm_state)
      2'h0:
          casez (new_input)
            1'h1:
                \$next\fsm_state  = 2'h1;
          endcase
      2'h1:
          casez (new_input)
            1'h1:
                casez (\$23 )
                  1'h1:
                      \$next\fsm_state  = 2'h2;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fsm_state  = 2'h0;
    endcase
  end
  always @* begin
    \$next\end_of_frame  = end_of_frame;
    casez (fsm_state)
      2'h1:
          casez (new_input)
            1'h1:
                casez (\$29 )
                  1'h1:
                      \$next\end_of_frame  = 1'h1;
                endcase
          endcase
      2'h2:
          \$next\end_of_frame  = 1'h1;
    endcase
    casez (rst)
      1'h1:
          \$next\end_of_frame  = 1'h0;
    endcase
  end
  assign \$1  = \$2 ;
  assign \$6  = \$7 ;
  assign \$9  = \$10 ;
  assign \$14  = \$15 ;
endmodule
module top(width, height, rst, clk, end_of_frame, new_row, new_input);

  wire [16:0] \$1 ;
  wire [16:0] \$10 ;
  wire \$12 ;
  wire [16:0] \$14 ;
  wire [16:0] \$15 ;
  wire \$17 ;
  wire \$19 ;
  wire [16:0] \$2 ;
  wire \$21 ;
  wire \$23 ;
  wire \$25 ;
  wire \$27 ;
  wire \$29 ;
  wire \$4 ;
  wire [16:0] \$6 ;
  wire [16:0] \$7 ;
  wire [16:0] \$9 ;
  (* src = "signals.py:45" *)
  reg \$next\end_of_frame ;
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] \$next\fsm_state ;
  (* src = "signals.py:57" *)
  reg [15:0] \$next\height_temp ;
  (* src = "signals.py:46" *)
  reg \$next\new_row ;
  (* src = "signals.py:56" *)
  reg [15:0] \$next\width_temp ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* init = 1'h0 *)
  (* src = "signals.py:45" *)
  output end_of_frame;
  reg end_of_frame = 1'h0;
  (* init = 2'h0 *)
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] fsm_state = 2'h0;
  (* src = "signals.py:41" *)
  input [15:0] height;
  (* init = 16'h0000 *)
  (* src = "signals.py:57" *)
  reg [15:0] height_temp = 16'h0000;
  (* src = "signals.py:43" *)
  input new_input;
  (* init = 1'h1 *)
  (* src = "signals.py:46" *)
  output new_row;
  reg new_row = 1'h1;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "signals.py:42" *)
  input [15:0] width;
  (* init = 16'h0000 *)
  (* src = "signals.py:56" *)
  reg [15:0] width_temp = 16'h0000;
  assign \$10  = height - (* src = "signals.py:66" *) 1'h1;
  assign \$12  = width_temp == (* src = "signals.py:73" *) 2'h2;
  assign \$15  = height_temp - (* src = "signals.py:76" *) 1'h1;
  assign \$17  = width_temp == (* src = "signals.py:73" *) 2'h2;
  assign \$19  = height_temp == (* src = "signals.py:84" *) 1'h0;
  assign \$21  = width_temp == (* src = "signals.py:84" *) 3'h4;
  assign \$23  = \$19  & (* src = "signals.py:84" *) \$21 ;
  assign \$25  = height_temp == (* src = "signals.py:84" *) 1'h0;
  assign \$27  = width_temp == (* src = "signals.py:84" *) 3'h4;
  assign \$2  = width - (* src = "signals.py:65" *) 2'h2;
  assign \$29  = \$25  & (* src = "signals.py:84" *) \$27 ;
  assign \$4  = width_temp == (* src = "signals.py:73" *) 2'h2;
  assign \$7  = width_temp - (* src = "signals.py:81" *) 2'h2;
  always @(posedge clk)
      end_of_frame <= \$next\end_of_frame ;
  always @(posedge clk)
      fsm_state <= \$next\fsm_state ;
  always @(posedge clk)
      new_row <= \$next\new_row ;
  always @(posedge clk)
      height_temp <= \$next\height_temp ;
  always @(posedge clk)
      width_temp <= \$next\width_temp ;
  always @* begin
    \$next\width_temp  = width_temp;
    casez (fsm_state)
      2'h0:
          casez (new_input)
            1'h1:
                \$next\width_temp  = \$1 [15:0];
          endcase
      2'h1:
          casez (new_input)
            1'h1:
                casez (\$4 )
                  1'h1:
                      \$next\width_temp  = width;
                  1'hz:
                      \$next\width_temp  = \$6 [15:0];
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\width_temp  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\height_temp  = height_temp;
    casez (fsm_state)
      2'h0:
          casez (new_input)
            1'h1:
                \$next\height_temp  = \$9 [15:0];
          endcase
      2'h1:
          casez (new_input)
            1'h1:
                casez (\$12 )
                  1'h1:
                      \$next\height_temp  = \$14 [15:0];
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\height_temp  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\new_row  = new_row;
    casez (fsm_state)
      2'h0:
          casez (new_input)
            1'h1:
                \$next\new_row  = 1'h0;
          endcase
      2'h1:
          casez (new_input)
            1'h1:
                casez (\$17 )
                  1'h1:
                      \$next\new_row  = 1'h1;
                  1'hz:
                      \$next\new_row  = 1'h0;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\new_row  = 1'h1;
    endcase
  end
  always @* begin
    \$next\fsm_state  = fsm_state;
    casez (fsm_state)
      2'h0:
          casez (new_input)
            1'h1:
                \$next\fsm_state  = 2'h1;
          endcase
      2'h1:
          casez (new_input)
            1'h1:
                casez (\$23 )
                  1'h1:
                      \$next\fsm_state  = 2'h2;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fsm_state  = 2'h0;
    endcase
  end
  always @* begin
    \$next\end_of_frame  = end_of_frame;
    casez (fsm_state)
      2'h1:
          casez (new_input)
            1'h1:
                casez (\$29 )
                  1'h1:
                      \$next\end_of_frame  = 1'h1;
                endcase
          endcase
      2'h2:
          \$next\end_of_frame  = 1'h1;
    endcase
    casez (rst)
      1'h1:
          \$next\end_of_frame  = 1'h0;
    endcase
  end
  assign \$1  = \$2 ;
  assign \$6  = \$7 ;
  assign \$9  = \$10 ;
  assign \$14  = \$15 ;
endmodule