data/full_repos/permissive/114643454/src/inst_rom_data_ram.v
 line:5: before: "]"
1: b'%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:5: Define or directive not defined: \'`InstAddrBus\'\n    input   wire[`InstAddrBus]  rom_addr,\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:5: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`InstAddrBus]  rom_addr,\n                             ^\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:6: Define or directive not defined: \'`InstBus\'\n    output  reg[`InstBus]       rom_inst,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire                ram_we,\n    ^~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`DataAddrBus]  ram_addr,\n    ^~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:10: Define or directive not defined: \'`DataAddrBus\'\n    input   wire[`DataAddrBus]  ram_addr,\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`DataBus]      ram_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:12: Define or directive not defined: \'`DataBus\'\n    input   wire[`DataBus]      ram_data_i,\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:13: Define or directive not defined: \'`DataBus\'\n    output  reg[`DataBus]       ram_data_o\n                ^~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:17: Define or directive not defined: \'`InstBus\'\n    reg[`InstBus]               inst_mem[0 : `InstMemNum - 1];\n        ^~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`InstBus]               inst_mem[0 : `InstMemNum - 1];\n                ^\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:17: Define or directive not defined: \'`InstMemNum\'\n    reg[`InstBus]               inst_mem[0 : `InstMemNum - 1];\n                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:19: Define or directive not defined: \'`ByteWidth\'\n    reg[`ByteWidth]             data_mem0[0 : `DataMemNum - 1];\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`ByteWidth]             data_mem0[0 : `DataMemNum - 1];\n                  ^\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:19: Define or directive not defined: \'`DataMemNum\'\n    reg[`ByteWidth]             data_mem0[0 : `DataMemNum - 1];\n                                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:20: Define or directive not defined: \'`ByteWidth\'\n    reg[`ByteWidth]             data_mem1[0 : `DataMemNum - 1];\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`ByteWidth]             data_mem1[0 : `DataMemNum - 1];\n                  ^\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:20: Define or directive not defined: \'`DataMemNum\'\n    reg[`ByteWidth]             data_mem1[0 : `DataMemNum - 1];\n                                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:21: Define or directive not defined: \'`ByteWidth\'\n    reg[`ByteWidth]             data_mem2[0 : `DataMemNum - 1];\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`ByteWidth]             data_mem2[0 : `DataMemNum - 1];\n                  ^\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:21: Define or directive not defined: \'`DataMemNum\'\n    reg[`ByteWidth]             data_mem2[0 : `DataMemNum - 1];\n                                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:22: Define or directive not defined: \'`ByteWidth\'\n    reg[`ByteWidth]             data_mem3[0 : `DataMemNum - 1];\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`ByteWidth]             data_mem3[0 : `DataMemNum - 1];\n                  ^\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:22: Define or directive not defined: \'`DataMemNum\'\n    reg[`ByteWidth]             data_mem3[0 : `DataMemNum - 1];\n                                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:26: syntax error, unexpected initial\n    initial begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:28: Define or directive not defined: \'`InstMemNum\'\n        for (i = 0; i < `InstMemNum; i = i + 1) begin\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:37: Define or directive not defined: \'`ChipDisable\'\n        if (rom_ce == `ChipDisable) begin\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:38: Define or directive not defined: \'`ZeroWord\'\n            rom_inst <= `ZeroWord;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:50: Define or directive not defined: \'`ChipDisable\'\n        if (ram_ce == `ChipDisable) begin\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:51: Define or directive not defined: \'`ZeroWord\'\n            ram_data_o  <=  `ZeroWord;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:52: Define or directive not defined: \'`WriteDisable\'\n        end else if (ram_we == `WriteDisable) begin\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:56: Define or directive not defined: \'`ZeroWord\'\n            ram_data_o  <=  `ZeroWord;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:61: Define or directive not defined: \'`ChipDisable\'\n        if (ram_ce == `ChipDisable) begin\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:62: Define or directive not defined: \'`ZeroWord\'\n            ram_data_o  <=  `ZeroWord;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:63: Define or directive not defined: \'`WriteEnable\'\n        end else if (ram_we == `WriteEnable) begin\n                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:64: Define or directive not defined: \'`Selected\'\n            if (ram_sel[3] == `Selected) data_mem3[ram_addr >> 2] <= ram_data_i[31 : 24];\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:65: Define or directive not defined: \'`Selected\'\n            if (ram_sel[2] == `Selected) data_mem2[ram_addr >> 2] <= ram_data_i[23 : 16];\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:66: Define or directive not defined: \'`Selected\'\n            if (ram_sel[1] == `Selected) data_mem1[ram_addr >> 2] <= ram_data_i[15 : 8];\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:67: Define or directive not defined: \'`Selected\'\n            if (ram_sel[0] == `Selected) data_mem0[ram_addr >> 2] <= ram_data_i[7 : 0];\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:69: Define or directive not defined: \'`Selected\'\n                if (ram_sel[3] == `Selected) $display("%c", ram_data_i[31 : 24]);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:70: Define or directive not defined: \'`Selected\'\n                if (ram_sel[2] == `Selected) $display("%c", ram_data_i[23 : 16]);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:71: Define or directive not defined: \'`Selected\'\n                if (ram_sel[1] == `Selected) $display("%c", ram_data_i[15 : 8]);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:72: Define or directive not defined: \'`Selected\'\n                if (ram_sel[0] == `Selected) $display("%c", ram_data_i[7 : 0]);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:74: Define or directive not defined: \'`Selected\'\n            $display("Store memory[%h] = %h", ram_addr, {{(ram_sel[3] == `Selected) ? ram_data_i[31 : 24] : 8\'b0}, {(ram_sel[2] == `Selected) ? ram_data_i[23 : 16] : 8\'b0}, {(ram_sel[1] == `Selected) ? ram_data_i[15 : 8] : 8\'b0}, {(ram_sel[0] == `Selected) ? ram_data_i[7 : 0] : 8\'b0}});\n                                                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:74: Define or directive not defined: \'`Selected\'\n            $display("Store memory[%h] = %h", ram_addr, {{(ram_sel[3] == `Selected) ? ram_data_i[31 : 24] : 8\'b0}, {(ram_sel[2] == `Selected) ? ram_data_i[23 : 16] : 8\'b0}, {(ram_sel[1] == `Selected) ? ram_data_i[15 : 8] : 8\'b0}, {(ram_sel[0] == `Selected) ? ram_data_i[7 : 0] : 8\'b0}});\n                                                                                                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:74: Define or directive not defined: \'`Selected\'\n            $display("Store memory[%h] = %h", ram_addr, {{(ram_sel[3] == `Selected) ? ram_data_i[31 : 24] : 8\'b0}, {(ram_sel[2] == `Selected) ? ram_data_i[23 : 16] : 8\'b0}, {(ram_sel[1] == `Selected) ? ram_data_i[15 : 8] : 8\'b0}, {(ram_sel[0] == `Selected) ? ram_data_i[7 : 0] : 8\'b0}});\n                                                                                                                                                                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:74: Define or directive not defined: \'`Selected\'\n            $display("Store memory[%h] = %h", ram_addr, {{(ram_sel[3] == `Selected) ? ram_data_i[31 : 24] : 8\'b0}, {(ram_sel[2] == `Selected) ? ram_data_i[23 : 16] : 8\'b0}, {(ram_sel[1] == `Selected) ? ram_data_i[15 : 8] : 8\'b0}, {(ram_sel[0] == `Selected) ? ram_data_i[7 : 0] : 8\'b0}});\n                                                                                                                                                                                                                                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/inst_rom_data_ram.v:76: Define or directive not defined: \'`ZeroWord\'\n            ram_data_o  <=  `ZeroWord;\n                            ^~~~~~~~~\n%Error: Exiting due to 48 error(s)\n'
module inst_rom_data_ram (
    input   wire                clk,

    input   wire                rom_ce,
    input   wire[`InstAddrBus]  rom_addr,
    output  reg[`InstBus]       rom_inst,

    input   wire                ram_ce,
    input   wire                ram_we,
    input   wire[`DataAddrBus]  ram_addr,
    input   wire[3 : 0]         ram_sel,
    input   wire[`DataBus]      ram_data_i,
    output  reg[`DataBus]       ram_data_o

);

    reg[`InstBus]               inst_mem[0 : `InstMemNum - 1];

    reg[`ByteWidth]             data_mem0[0 : `DataMemNum - 1];
    reg[`ByteWidth]             data_mem1[0 : `DataMemNum - 1];
    reg[`ByteWidth]             data_mem2[0 : `DataMemNum - 1];
    reg[`ByteWidth]             data_mem3[0 : `DataMemNum - 1];

    integer i;

    initial begin
        $readmemh ( "inst_rom.data" , inst_mem );
        for (i = 0; i < `InstMemNum; i = i + 1) begin
            data_mem0[i] <= inst_mem[i][31 : 24];
            data_mem1[i] <= inst_mem[i][23 : 16];
            data_mem2[i] <= inst_mem[i][15 : 8];
            data_mem3[i] <= inst_mem[i][7 : 0];
        end
    end

    always @ ( rom_ce or rom_addr ) begin
        if (rom_ce == `ChipDisable) begin
            rom_inst <= `ZeroWord;
        end else begin
            rom_inst <= {inst_mem[rom_addr >> 2][7 : 0], inst_mem[rom_addr >> 2][15 : 8],
                    inst_mem[rom_addr >> 2][23 : 16], inst_mem[rom_addr >> 2][31 : 24]};

    end
end



    always @ ( * ) begin
        if (ram_ce == `ChipDisable) begin
            ram_data_o  <=  `ZeroWord;
        end else if (ram_we == `WriteDisable) begin
            ram_data_o  <=  {data_mem3[ram_addr >> 2], data_mem2[ram_addr >> 2], data_mem1[ram_addr >> 2], data_mem0[ram_addr >> 2]};
            $display("Load memory[%h] = %h", ram_addr, {data_mem3[ram_addr >> 2], data_mem2[ram_addr >> 2], data_mem1[ram_addr >> 2], data_mem0[ram_addr >> 2]});
        end else begin
            ram_data_o  <=  `ZeroWord;
        end
    end

    always @ ( posedge clk ) begin
        if (ram_ce == `ChipDisable) begin
            ram_data_o  <=  `ZeroWord;
        end else if (ram_we == `WriteEnable) begin
            if (ram_sel[3] == `Selected) data_mem3[ram_addr >> 2] <= ram_data_i[31 : 24];
            if (ram_sel[2] == `Selected) data_mem2[ram_addr >> 2] <= ram_data_i[23 : 16];
            if (ram_sel[1] == `Selected) data_mem1[ram_addr >> 2] <= ram_data_i[15 : 8];
            if (ram_sel[0] == `Selected) data_mem0[ram_addr >> 2] <= ram_data_i[7 : 0];
            if (ram_addr == 32'h104) begin
                if (ram_sel[3] == `Selected) $display("%c", ram_data_i[31 : 24]);
                if (ram_sel[2] == `Selected) $display("%c", ram_data_i[23 : 16]);
                if (ram_sel[1] == `Selected) $display("%c", ram_data_i[15 : 8]);
                if (ram_sel[0] == `Selected) $display("%c", ram_data_i[7 : 0]);
            end
            $display("Store memory[%h] = %h", ram_addr, {{(ram_sel[3] == `Selected) ? ram_data_i[31 : 24] : 8'b0}, {(ram_sel[2] == `Selected) ? ram_data_i[23 : 16] : 8'b0}, {(ram_sel[1] == `Selected) ? ram_data_i[15 : 8] : 8'b0}, {(ram_sel[0] == `Selected) ? ram_data_i[7 : 0] : 8'b0}});
        end else begin
            ram_data_o  <=  `ZeroWord;
        end
    end

endmodule
module inst_rom_data_ram (
    input   wire                clk,

    input   wire                rom_ce,
    input   wire[`InstAddrBus]  rom_addr,
    output  reg[`InstBus]       rom_inst,

    input   wire                ram_ce,
    input   wire                ram_we,
    input   wire[`DataAddrBus]  ram_addr,
    input   wire[3 : 0]         ram_sel,
    input   wire[`DataBus]      ram_data_i,
    output  reg[`DataBus]       ram_data_o

);


    reg[`InstBus]               inst_mem[0 : `InstMemNum - 1];

    reg[`ByteWidth]             data_mem0[0 : `DataMemNum - 1];
    reg[`ByteWidth]             data_mem1[0 : `DataMemNum - 1];
    reg[`ByteWidth]             data_mem2[0 : `DataMemNum - 1];
    reg[`ByteWidth]             data_mem3[0 : `DataMemNum - 1];

    integer i;

    initial begin
        $readmemh ( "inst_rom.data" , inst_mem );
        for (i = 0; i < `InstMemNum; i = i + 1) begin
            data_mem0[i] <= inst_mem[i][31 : 24];
            data_mem1[i] <= inst_mem[i][23 : 16];
            data_mem2[i] <= inst_mem[i][15 : 8];
            data_mem3[i] <= inst_mem[i][7 : 0];
        end
    end

    always @ ( rom_ce or rom_addr ) begin
        if (rom_ce == `ChipDisable) begin
            rom_inst <= `ZeroWord;
        end else begin
            rom_inst <= {inst_mem[rom_addr >> 2][7 : 0], inst_mem[rom_addr >> 2][15 : 8],
                    inst_mem[rom_addr >> 2][23 : 16], inst_mem[rom_addr >> 2][31 : 24]};

    end
end



    always @ ( * ) begin
        if (ram_ce == `ChipDisable) begin
            ram_data_o  <=  `ZeroWord;
        end else if (ram_we == `WriteDisable) begin
            ram_data_o  <=  {data_mem3[ram_addr >> 2], data_mem2[ram_addr >> 2], data_mem1[ram_addr >> 2], data_mem0[ram_addr >> 2]};
            $display("Load memory[%h] = %h", ram_addr, {data_mem3[ram_addr >> 2], data_mem2[ram_addr >> 2], data_mem1[ram_addr >> 2], data_mem0[ram_addr >> 2]});
        end else begin
            ram_data_o  <=  `ZeroWord;
        end
    end

    always @ ( posedge clk ) begin
        if (ram_ce == `ChipDisable) begin
            ram_data_o  <=  `ZeroWord;
        end else if (ram_we == `WriteEnable) begin
            if (ram_sel[3] == `Selected) data_mem3[ram_addr >> 2] <= ram_data_i[31 : 24];
            if (ram_sel[2] == `Selected) data_mem2[ram_addr >> 2] <= ram_data_i[23 : 16];
            if (ram_sel[1] == `Selected) data_mem1[ram_addr >> 2] <= ram_data_i[15 : 8];
            if (ram_sel[0] == `Selected) data_mem0[ram_addr >> 2] <= ram_data_i[7 : 0];
            if (ram_addr == 32'h104) begin
                if (ram_sel[3] == `Selected) $display("%c", ram_data_i[31 : 24]);
                if (ram_sel[2] == `Selected) $display("%c", ram_data_i[23 : 16]);
                if (ram_sel[1] == `Selected) $display("%c", ram_data_i[15 : 8]);
                if (ram_sel[0] == `Selected) $display("%c", ram_data_i[7 : 0]);
            end
            $display("Store memory[%h] = %h", ram_addr, {{(ram_sel[3] == `Selected) ? ram_data_i[31 : 24] : 8'b0}, {(ram_sel[2] == `Selected) ? ram_data_i[23 : 16] : 8'b0}, {(ram_sel[1] == `Selected) ? ram_data_i[15 : 8] : 8'b0}, {(ram_sel[0] == `Selected) ? ram_data_i[7 : 0] : 8'b0}});
        end else begin
            ram_data_o  <=  `ZeroWord;
        end
    end

endmodule