data/full_repos/permissive/136584400/digital_logic_labs/lab04/3/sources/comparator1.v
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data/verilator_xmls/370c1078-15b6-4324-86d5-c26f6b29f622.xml
module comparator1(A, B, f1, f2, f3);
	parameter WIDTH = 1;

	input [WIDTH-1:0] A, B;
	output f1, f2, f3;

	assign f1 = (A > B) ? 1'b1 : 1'b0;
	assign f2 = (A == B) ? 1'b1 : 1'b0;
	assign f3 = (A < B) ? 1'b1 : 1'b0;
endmodule
module comparator1(A, B, f1, f2, f3);

	parameter WIDTH = 1;

	input [WIDTH-1:0] A, B;
	output f1, f2, f3;

	assign f1 = (A > B) ? 1'b1 : 1'b0;
	assign f2 = (A == B) ? 1'b1 : 1'b0;
	assign f3 = (A < B) ? 1'b1 : 1'b0;
endmodule