data/full_repos/permissive/123800017/clk.v
data/verilator_xmls/4fc34eb5-b3c3-4604-a25e-02236563788a.xml
module clkredu(
 input clk,
 output reg salida
 ); 
 reg [25:0]conteo; 
always @(posedge clk) 
	begin 
		conteo <= conteo + 1; 
		if(conteo==2605)  
			begin 
				conteo <= 0; 
				salida <= salida+1; 
			end 
	end 
endmodule
module clkredu(
 input clk,
 output reg salida
 );
 
 reg [25:0]conteo; 
always @(posedge clk) 
	begin 
		conteo <= conteo + 1; 
		if(conteo==2605)  
			begin 
				conteo <= 0; 
				salida <= salida+1; 
			end 
	end 
endmodule