data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v
1: b'%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:49: Cannot find file containing module: \'pmod_als\'\n    pmod_als \n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis,data/full_repos/permissive/110151336/pmod_als\n             data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis,data/full_repos/permissive/110151336/pmod_als.v\n             data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis,data/full_repos/permissive/110151336/pmod_als.sv\n             pmod_als\n             pmod_als.v\n             pmod_als.sv\n             obj_dir/pmod_als\n             obj_dir/pmod_als.v\n             obj_dir/pmod_als.sv\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:63: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                                    : ... In instance de10_lite\n    assign LEDR[9:1] = 8\'b0;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n                                                                                                    : ... In instance de10_lite\n    wire [ 31:0 ] h7segment = { 16\'b0, value };\n                            ^\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:74: Cannot find file containing module: \'hex_display\'\n    hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:75: Cannot find file containing module: \'hex_display\'\n    hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:76: Cannot find file containing module: \'hex_display\'\n    hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:77: Cannot find file containing module: \'hex_display\'\n    hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:78: Cannot find file containing module: \'hex_display\'\n    hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/01_badstyle/synthesis/de10_lite.v:79: Cannot find file containing module: \'hex_display\'\n    hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );\n    ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 2 warning(s)\n'
module de10_lite
(
    input               ADC_CLK_10,
    input               MAX10_CLK1_50,
    input               MAX10_CLK2_50,

    output  [  7:0 ]    HEX0,
    output  [  7:0 ]    HEX1,
    output  [  7:0 ]    HEX2,
    output  [  7:0 ]    HEX3,
    output  [  7:0 ]    HEX4,
    output  [  7:0 ]    HEX5,

    input   [  1:0 ]    KEY,
    output  [  9:0 ]    LEDR,
    input   [  9:0 ]    SW,
    inout   [ 35:0 ]    GPIO
);


    wire        cs;
    wire        sck;
    wire        sdo;











    assign GPIO[26] = 1'b0;
    assign GPIO[28] = sck;
    assign sdo      = GPIO[30];
    assign GPIO[32] = 1'bz;
    assign GPIO[34] = cs;


    wire clk   = MAX10_CLK1_50;
    wire rst_n = KEY[0];


    wire  [7:0] value;


    pmod_als 
        #( .QUERY_DELAY(1 << 21) )
    als
    (
        .clk    ( clk   ),
        .rst_n  ( rst_n ),
        .cs     ( cs    ),
        .sck    ( sck   ),
        .sdo    ( sdo   ),
        .value  ( value )
    );


    assign LEDR[0]   = ~cs;
    assign LEDR[9:1] = 8'b0;

    wire [ 31:0 ] h7segment = { 16'b0, value };

    assign HEX0 [7] = 1'b1;
    assign HEX1 [7] = 1'b1;
    assign HEX2 [7] = 1'b1;
    assign HEX3 [7] = 1'b1;
    assign HEX4 [7] = 1'b1;
    assign HEX5 [7] = 1'b1;

    hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
    hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
    hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
    hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
    hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
    hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );

endmodule
module de10_lite
(
    input               ADC_CLK_10,
    input               MAX10_CLK1_50,
    input               MAX10_CLK2_50,

    output  [  7:0 ]    HEX0,
    output  [  7:0 ]    HEX1,
    output  [  7:0 ]    HEX2,
    output  [  7:0 ]    HEX3,
    output  [  7:0 ]    HEX4,
    output  [  7:0 ]    HEX5,

    input   [  1:0 ]    KEY,
    output  [  9:0 ]    LEDR,
    input   [  9:0 ]    SW,
    inout   [ 35:0 ]    GPIO
);



    wire        cs;
    wire        sck;
    wire        sdo;











    assign GPIO[26] = 1'b0;
    assign GPIO[28] = sck;
    assign sdo      = GPIO[30];
    assign GPIO[32] = 1'bz;
    assign GPIO[34] = cs;


    wire clk   = MAX10_CLK1_50;
    wire rst_n = KEY[0];


    wire  [7:0] value;


    pmod_als 
        #( .QUERY_DELAY(1 << 21) )
    als
    (
        .clk    ( clk   ),
        .rst_n  ( rst_n ),
        .cs     ( cs    ),
        .sck    ( sck   ),
        .sdo    ( sdo   ),
        .value  ( value )
    );


    assign LEDR[0]   = ~cs;
    assign LEDR[9:1] = 8'b0;

    wire [ 31:0 ] h7segment = { 16'b0, value };

    assign HEX0 [7] = 1'b1;
    assign HEX1 [7] = 1'b1;
    assign HEX2 [7] = 1'b1;
    assign HEX3 [7] = 1'b1;
    assign HEX4 [7] = 1'b1;
    assign HEX5 [7] = 1'b1;

    hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
    hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
    hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
    hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
    hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
    hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );

endmodule