data/full_repos/permissive/21716763/uncle_gates/netlist/pfet_b.v
1: b'%Error: data/full_repos/permissive/21716763/uncle_gates/netlist/pfet_b.v:10: Unsupported: Verilog 1995 gate primitive: tranif0\n    tranif0 (d, s, g);\n            ^\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pfet_b ( d, g, s, b );

  inout s;
  inout b;
  inout d;
  input g;

    tranif0 (d, s, g);

endmodule
module pfet_b ( d, g, s, b );


  inout s;
  inout b;
  inout d;
  input g;

    tranif0 (d, s, g);

endmodule