data/full_repos/permissive/124844461/Lab1/simple_register.v
 line:59: before: "/"
data/verilator_xmls/3c39850e-0cbd-47a1-8e09-9854e8b39674.xml
module simple_register(
in,
out,
clk,
enable,
reset
);

parameter DATA_WIDTH = 32;

input   in;
input   reset;
input   clk;
input   enable;
output  out;

wire [DATA_WIDTH - 1: 0]    in;
wire                        reset;
wire                        clk;
wire                        enable;
reg  [DATA_WIDTH - 1: 0]    out;

reg  [DATA_WIDTH - 1: 0]    reg_store;

initial begin
    reg_store = {DATA_WIDTH{1'b0}};
end

always @(posedge clk)begin
    if (reset == 1'b1) begin
      reg_store = {DATA_WIDTH{1'b0}};
    end else if (enable == 1'b1) begin
        reg_store = in;
    end

     out = reg_store;
end

endmodule
module simple_register(
in,
out,
clk,
enable,
reset
);


parameter DATA_WIDTH = 32;

input   in;
input   reset;
input   clk;
input   enable;
output  out;

wire [DATA_WIDTH - 1: 0]    in;
wire                        reset;
wire                        clk;
wire                        enable;
reg  [DATA_WIDTH - 1: 0]    out;

reg  [DATA_WIDTH - 1: 0]    reg_store;

initial begin
    reg_store = {DATA_WIDTH{1'b0}};
end

always @(posedge clk)begin
    if (reset == 1'b1) begin
      reg_store = {DATA_WIDTH{1'b0}};
    end else if (enable == 1'b1) begin
        reg_store = in;
    end

     out = reg_store;
end

endmodule