data/full_repos/permissive/184916587/Test_ALU_RECV.v
 line:43: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_ALU_RECV.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #0 alu_op=1000000001;ls_op={5{1\'b1}};j_op={5{1\'b1}};b_op={5{1\'b1}};pc_in={32{1\'b0}};rs1={{31{1\'b0}},{1{1\'b1}}};rs2={32{1\'b0}};address_imm={{31{1\'b0}},{1{1\'b1}}};  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_ALU_RECV.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #5 alu_op={10{1\'b1}};ls_op=5\'b00011;j_op={5{1\'b1}};b_op={5{1\'b1}};pc_in={32{1\'b0}};rs1={{28{1\'b0}},4\'b1101};rs2={32{1\'b0}};address_imm={{31{1\'b0}},{1{1\'b1}}};  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_ALU_RECV.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #5 alu_op={10{1\'b1}};ls_op={5{1\'b1}};j_op=5\'b00010;b_op={5{1\'b1}};pc_in={{30{1\'b0}},2\'b11};rs1={32{1\'b0}};rs2={32{1\'b0}};address_imm={{31{1\'b0}},{1{1\'b1}}};  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_ALU_RECV.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #5 alu_op={10{1\'b1}};ls_op={5{1\'b1}};j_op={5{1\'b1}};b_op=5\'b00101;pc_in={{25{1\'b0}},7\'b1101100};rs1={{30{1\'b0}},2\'b11};rs2={{31{1\'b0}},1\'b1};address_imm={{26{1\'b0}},6\'b001001};  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_ALU_RECV.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #5 alu_op={10{1\'b1}};ls_op={5{1\'b1}};j_op={5{1\'b1}};b_op=5\'b00101;pc_in={{25{1\'b0}},7\'b1101100};rs2={{30{1\'b0}},2\'b11};rs1={{31{1\'b0}},1\'b1};address_imm={{26{1\'b0}},6\'b001001};  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_ALU_RECV.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #5 $finish;\n  ^\n%Error: data/full_repos/permissive/184916587/Test_ALU_RECV.v:47: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("ALU_RECV.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/184916587/Test_ALU_RECV.v:48: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,Test_ALU_RECV);\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_ALU_RECV;


	reg[9:0] alu_op;
	reg[4:0] ls_op;
	reg[4:0] j_op;
	reg[4:0] b_op;
	reg[31:0] pc_in;
	reg[31:0] rs1;
	reg[31:0] rs2;
	reg[31:0] address_imm;
	wire[31:0] rd;
	wire[31:0] pc_out;
	wire[31:0] address;

	ALU_RECV test_alu_recv(
		.alu_op(alu_op),
		.ls_op(ls_op),
		.j_op(j_op),
		.b_op(b_op),
		.pc_in(pc_in),
		.pc_out(pc_out),
		.address(address),
		.rs1(rs1),
		.rs2(rs2),
		.address_imm(address_imm),
		.rd(rd)
		);

	initial begin
		#0 alu_op=1000000001;ls_op={5{1'b1}};j_op={5{1'b1}};b_op={5{1'b1}};pc_in={32{1'b0}};rs1={{31{1'b0}},{1{1'b1}}};rs2={32{1'b0}};address_imm={{31{1'b0}},{1{1'b1}}};
		#5 alu_op={10{1'b1}};ls_op=5'b00011;j_op={5{1'b1}};b_op={5{1'b1}};pc_in={32{1'b0}};rs1={{28{1'b0}},4'b1101};rs2={32{1'b0}};address_imm={{31{1'b0}},{1{1'b1}}};
		#5 alu_op={10{1'b1}};ls_op={5{1'b1}};j_op=5'b00010;b_op={5{1'b1}};pc_in={{30{1'b0}},2'b11};rs1={32{1'b0}};rs2={32{1'b0}};address_imm={{31{1'b0}},{1{1'b1}}};
		#5 alu_op={10{1'b1}};ls_op={5{1'b1}};j_op={5{1'b1}};b_op=5'b00101;pc_in={{25{1'b0}},7'b1101100};rs1={{30{1'b0}},2'b11};rs2={{31{1'b0}},1'b1};address_imm={{26{1'b0}},6'b001001};
		#5 alu_op={10{1'b1}};ls_op={5{1'b1}};j_op={5{1'b1}};b_op=5'b00101;pc_in={{25{1'b0}},7'b1101100};rs2={{30{1'b0}},2'b11};rs1={{31{1'b0}},1'b1};address_imm={{26{1'b0}},6'b001001};
		#5 $finish;
	end

	initial begin
		$dumpfile("ALU_RECV.vcd");
		$dumpvars(0,Test_ALU_RECV);
	end

endmodule
module Test_ALU_RECV;



	reg[9:0] alu_op;
	reg[4:0] ls_op;
	reg[4:0] j_op;
	reg[4:0] b_op;
	reg[31:0] pc_in;
	reg[31:0] rs1;
	reg[31:0] rs2;
	reg[31:0] address_imm;
	wire[31:0] rd;
	wire[31:0] pc_out;
	wire[31:0] address;

	ALU_RECV test_alu_recv(
		.alu_op(alu_op),
		.ls_op(ls_op),
		.j_op(j_op),
		.b_op(b_op),
		.pc_in(pc_in),
		.pc_out(pc_out),
		.address(address),
		.rs1(rs1),
		.rs2(rs2),
		.address_imm(address_imm),
		.rd(rd)
		);

	initial begin
		#0 alu_op=1000000001;ls_op={5{1'b1}};j_op={5{1'b1}};b_op={5{1'b1}};pc_in={32{1'b0}};rs1={{31{1'b0}},{1{1'b1}}};rs2={32{1'b0}};address_imm={{31{1'b0}},{1{1'b1}}};
		#5 alu_op={10{1'b1}};ls_op=5'b00011;j_op={5{1'b1}};b_op={5{1'b1}};pc_in={32{1'b0}};rs1={{28{1'b0}},4'b1101};rs2={32{1'b0}};address_imm={{31{1'b0}},{1{1'b1}}};
		#5 alu_op={10{1'b1}};ls_op={5{1'b1}};j_op=5'b00010;b_op={5{1'b1}};pc_in={{30{1'b0}},2'b11};rs1={32{1'b0}};rs2={32{1'b0}};address_imm={{31{1'b0}},{1{1'b1}}};
		#5 alu_op={10{1'b1}};ls_op={5{1'b1}};j_op={5{1'b1}};b_op=5'b00101;pc_in={{25{1'b0}},7'b1101100};rs1={{30{1'b0}},2'b11};rs2={{31{1'b0}},1'b1};address_imm={{26{1'b0}},6'b001001};
		#5 alu_op={10{1'b1}};ls_op={5{1'b1}};j_op={5{1'b1}};b_op=5'b00101;pc_in={{25{1'b0}},7'b1101100};rs2={{30{1'b0}},2'b11};rs1={{31{1'b0}},1'b1};address_imm={{26{1'b0}},6'b001001};
		#5 $finish;
	end

	initial begin
		$dumpfile("ALU_RECV.vcd");
		$dumpvars(0,Test_ALU_RECV);
	end

endmodule