data/full_repos/permissive/135077285/fowarding.v
data/verilator_xmls/b14035eb-bde4-4dd8-b62b-e12ce1f25c12.xml
module fowarding(
  input wire clock,


  input wire [4:0] rs,
  input wire [4:0] rt,


  input wire [4:0] writeRegister,
  input wire regWrite,


  input wire [4:0] writeRegisterMemWb,
  input wire regWriteMemWb,


  output reg [1:0] fowardA,
  output reg [1:0] fowardB
);

  initial begin
    fowardA <= 0;
    fowardB <= 0;
  end

  always @(posedge clock) begin


    if (regWrite && (writeRegister != 0) && (writeRegister == rs))
      fowardA <= 2'b10;
    else if (regWriteMemWb && (writeRegisterMemWb != 0) && !(regWrite && (writeRegister != 0)) && (writeRegister != rs) && (writeRegisterMemWb == rs))
      fowardA <= 2'b01;
    else
      fowardA <= 2'b00;



    if (regWrite && (writeRegister != 0) && (writeRegister == rt))
      fowardB <= 2'b10;
    else if (regWriteMemWb && (writeRegisterMemWb != 0) && !(regWrite && (writeRegister != 0)) && (writeRegister != rt) && (writeRegisterMemWb == rt))
      fowardB <= 2'b01;
    else
      fowardB <= 2'b00;
  end

endmodule
module fowarding(
  input wire clock,


  input wire [4:0] rs,
  input wire [4:0] rt,


  input wire [4:0] writeRegister,
  input wire regWrite,


  input wire [4:0] writeRegisterMemWb,
  input wire regWriteMemWb,


  output reg [1:0] fowardA,
  output reg [1:0] fowardB
);


  initial begin
    fowardA <= 0;
    fowardB <= 0;
  end

  always @(posedge clock) begin


    if (regWrite && (writeRegister != 0) && (writeRegister == rs))
      fowardA <= 2'b10;
    else if (regWriteMemWb && (writeRegisterMemWb != 0) && !(regWrite && (writeRegister != 0)) && (writeRegister != rs) && (writeRegisterMemWb == rs))
      fowardA <= 2'b01;
    else
      fowardA <= 2'b00;



    if (regWrite && (writeRegister != 0) && (writeRegister == rt))
      fowardB <= 2'b10;
    else if (regWriteMemWb && (writeRegisterMemWb != 0) && !(regWrite && (writeRegister != 0)) && (writeRegister != rt) && (writeRegisterMemWb == rt))
      fowardB <= 2'b01;
    else
      fowardB <= 2'b00;
  end

endmodule