data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v
 line:47: before: "integer"
1: b"%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:24: Define or directive not defined: '`UDP_REG_ADDR_WIDTH'\n      input  [`UDP_REG_ADDR_WIDTH-1:0]       reg_addr_in,\n              ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:25: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n      input  [`CPCI_NF2_DATA_WIDTH-1:0]      reg_data_in,\n              ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:31: Define or directive not defined: '`UDP_REG_ADDR_WIDTH'\n      output reg [`UDP_REG_ADDR_WIDTH-1:0]   reg_addr_out,\n                  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:32: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n      output reg [`CPCI_NF2_DATA_WIDTH-1:0]  reg_data_out,\n                  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:63: Define or directive not defined: '`IN_ARB_REG_ADDR_WIDTH'\n   wire [`IN_ARB_REG_ADDR_WIDTH - 1:0]                reg_addr;\n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:64: Define or directive not defined: '`UDP_REG_ADDR_WIDTH'\n   wire [((`UDP_REG_ADDR_WIDTH-`IN_ARB_REG_ADDR_WIDTH) - 1):0] tag_addr;\n           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:64: Define or directive not defined: '`IN_ARB_REG_ADDR_WIDTH'\n   wire [((`UDP_REG_ADDR_WIDTH-`IN_ARB_REG_ADDR_WIDTH) - 1):0] tag_addr;\n                               ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:64: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n   wire [((`UDP_REG_ADDR_WIDTH-`IN_ARB_REG_ADDR_WIDTH) - 1):0] tag_addr;\n                                                     ^\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:81: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n   reg [`CPCI_NF2_DATA_WIDTH-1:0]                     eop_cnt;\n        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:83: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n   reg [`CPCI_NF2_DATA_WIDTH-1:0]                     reg_data;\n        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:90: Define or directive not defined: '`IN_ARB_REG_ADDR_WIDTH'\n   assign reg_addr = reg_addr_in[`IN_ARB_REG_ADDR_WIDTH-1:0];\n                                 ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:91: Define or directive not defined: '`UDP_REG_ADDR_WIDTH'\n   assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:`IN_ARB_REG_ADDR_WIDTH];\n                                 ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:91: Define or directive not defined: '`IN_ARB_REG_ADDR_WIDTH'\n   assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:`IN_ARB_REG_ADDR_WIDTH];\n                                                         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:91: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n   assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:`IN_ARB_REG_ADDR_WIDTH];\n                                                                               ^\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:93: Define or directive not defined: '`IN_ARB_REG_ADDR_WIDTH'\n   assign addr_good = reg_addr[`IN_ARB_REG_ADDR_WIDTH-1:ADDR_WIDTH] == 'h0 &&\n                               ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:95: Define or directive not defined: '`IN_ARB_BLOCK_ADDR'\n   assign tag_hit = tag_addr == `IN_ARB_BLOCK_ADDR;\n                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:95: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n   assign tag_hit = tag_addr == `IN_ARB_BLOCK_ADDR;\n                                                  ^\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:101: Define or directive not defined: '`IN_ARB_NUM_PKTS_SENT'\n      if (reset || (reg_req_in && tag_hit && addr == `IN_ARB_NUM_PKTS_SENT))\n                                                     ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:101: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n      if (reset || (reg_req_in && tag_hit && addr == `IN_ARB_NUM_PKTS_SENT))\n                                                                          ^\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:165: Define or directive not defined: '`IN_ARB_NUM_PKTS_SENT'\n            `IN_ARB_NUM_PKTS_SENT:        reg_data = eop_cnt;\n            ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:165: syntax error, unexpected ':', expecting endcase\n            `IN_ARB_NUM_PKTS_SENT:        reg_data = eop_cnt;\n                                 ^\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:166: Define or directive not defined: '`IN_ARB_STATE'\n            `IN_ARB_STATE:                reg_data = {{(`CPCI_NF2_DATA_WIDTH-2){1'b0}}, out_rdy_latched, state_latched};\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:166: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n            `IN_ARB_STATE:                reg_data = {{(`CPCI_NF2_DATA_WIDTH-2){1'b0}}, out_rdy_latched, state_latched};\n                                                        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:167: Define or directive not defined: '`IN_ARB_LAST_PKT_WORD_0_LO'\n            `IN_ARB_LAST_PKT_WORD_0_LO:   reg_data = last_pkt_data_0[31:0];\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:168: Define or directive not defined: '`IN_ARB_LAST_PKT_WORD_0_HI'\n            `IN_ARB_LAST_PKT_WORD_0_HI:   reg_data = last_pkt_data_0[63:32];\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:169: Define or directive not defined: '`IN_ARB_LAST_PKT_CTRL_0'\n            `IN_ARB_LAST_PKT_CTRL_0:      reg_data = last_pkt_ctrl_0;\n            ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:170: Define or directive not defined: '`IN_ARB_LAST_PKT_WORD_1_LO'\n            `IN_ARB_LAST_PKT_WORD_1_LO:   reg_data = last_pkt_data_1[31:0];\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:171: Define or directive not defined: '`IN_ARB_LAST_PKT_WORD_1_HI'\n            `IN_ARB_LAST_PKT_WORD_1_HI:   reg_data = last_pkt_data_1[63:32];\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:172: Define or directive not defined: '`IN_ARB_LAST_PKT_CTRL_1'\n            `IN_ARB_LAST_PKT_CTRL_1:      reg_data = last_pkt_ctrl_1;\n            ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/in_arb_regs.v:209: syntax error, unexpected endmodule\nendmodule  \n^~~~~~~~~\n%Error: Cannot continue\n"
module in_arb_regs
    #( parameter DATA_WIDTH = 64,
       parameter CTRL_WIDTH = DATA_WIDTH/8,
       parameter UDP_REG_SRC_WIDTH = 2
       )
   
   ( 
      input                                  reg_req_in,
      input                                  reg_ack_in,
      input                                  reg_rd_wr_L_in,
      input  [`UDP_REG_ADDR_WIDTH-1:0]       reg_addr_in,
      input  [`CPCI_NF2_DATA_WIDTH-1:0]      reg_data_in,
      input  [UDP_REG_SRC_WIDTH-1:0]         reg_src_in,

      output reg                             reg_req_out,
      output reg                             reg_ack_out,
      output reg                             reg_rd_wr_L_out,
      output reg [`UDP_REG_ADDR_WIDTH-1:0]   reg_addr_out,
      output reg [`CPCI_NF2_DATA_WIDTH-1:0]  reg_data_out,
      output reg [UDP_REG_SRC_WIDTH-1:0]     reg_src_out,

      input                                  state,
      input                                  out_wr,
      input [CTRL_WIDTH-1:0]                 out_ctrl,
      input [DATA_WIDTH-1:0]                 out_data,
      input                                  out_rdy,
      input                                  eop,

      input                                  clk,
      input                                  reset
     );

   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction


   localparam NUM_REGS_USED = 8;
   localparam ADDR_WIDTH = log2(NUM_REGS_USED);



   wire [ADDR_WIDTH-1:0]                              addr;
   wire [`IN_ARB_REG_ADDR_WIDTH - 1:0]                reg_addr;
   wire [((`UDP_REG_ADDR_WIDTH-`IN_ARB_REG_ADDR_WIDTH) - 1):0] tag_addr;

   wire                                               addr_good;
   wire                                               tag_hit;

   reg                                                in_pkt;
   reg                                                second_word;

   reg                                                state_latched;
   reg                                                out_rdy_latched;

   reg [CTRL_WIDTH-1:0]                               last_pkt_ctrl_0;
   reg [DATA_WIDTH-1:0]                               last_pkt_data_0;

   reg [CTRL_WIDTH-1:0]                               last_pkt_ctrl_1;
   reg [DATA_WIDTH-1:0]                               last_pkt_data_1;

   reg [`CPCI_NF2_DATA_WIDTH-1:0]                     eop_cnt;

   reg [`CPCI_NF2_DATA_WIDTH-1:0]                     reg_data;

   wire                                               first_word;



   assign addr = reg_addr_in[ADDR_WIDTH-1:0];
   assign reg_addr = reg_addr_in[`IN_ARB_REG_ADDR_WIDTH-1:0];
   assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:`IN_ARB_REG_ADDR_WIDTH];

   assign addr_good = reg_addr[`IN_ARB_REG_ADDR_WIDTH-1:ADDR_WIDTH] == 'h0 &&
      addr < NUM_REGS_USED;
   assign tag_hit = tag_addr == `IN_ARB_BLOCK_ADDR;


   always @(posedge clk)
   begin

      if (reset || (reg_req_in && tag_hit && addr == `IN_ARB_NUM_PKTS_SENT))
         eop_cnt <= 'h0;
      else if (eop)
         eop_cnt <= eop_cnt + 'h1;

      if (reset) begin
         state_latched <= 0;
	 out_rdy_latched <= 0;

         last_pkt_ctrl_0 <= 'h0;
         last_pkt_data_0 <= 'h0;

         last_pkt_ctrl_1 <= 'h0;
         last_pkt_data_1 <= 'h0;
      end
      else begin
         state_latched <= state;
	 out_rdy_latched <= out_rdy;

         if (first_word && out_wr) begin
            last_pkt_ctrl_0 <= out_ctrl;
            last_pkt_data_0 <= out_data;
         end
         
         if (second_word && out_wr) begin
            last_pkt_ctrl_1 <= out_ctrl;
            last_pkt_data_1 <= out_data;
         end
      end
   end



   assign first_word = !in_pkt && !(|out_ctrl);
   always @(posedge clk)
   begin
      if (reset) begin
         in_pkt <= 0;
         second_word <= 0;
      end
      else begin
         if (first_word && out_wr)
            in_pkt <= 1'b1;
         else if (in_pkt && |out_ctrl && out_wr)
            in_pkt <= 1'b0;

         if(first_word && out_wr) begin
            second_word <= 1;
         end
         else if(second_word==1 && out_wr) begin
            second_word <= 0;
         end
      end
   end



   always @*
   begin
      if (reset) begin
         reg_data = 'h0;
      end
      else begin
         case (addr)
            `IN_ARB_NUM_PKTS_SENT:        reg_data = eop_cnt;
            `IN_ARB_STATE:                reg_data = {{(`CPCI_NF2_DATA_WIDTH-2){1'b0}}, out_rdy_latched, state_latched};
            `IN_ARB_LAST_PKT_WORD_0_LO:   reg_data = last_pkt_data_0[31:0];
            `IN_ARB_LAST_PKT_WORD_0_HI:   reg_data = last_pkt_data_0[63:32];
            `IN_ARB_LAST_PKT_CTRL_0:      reg_data = last_pkt_ctrl_0;
            `IN_ARB_LAST_PKT_WORD_1_LO:   reg_data = last_pkt_data_1[31:0];
            `IN_ARB_LAST_PKT_WORD_1_HI:   reg_data = last_pkt_data_1[63:32];
            `IN_ARB_LAST_PKT_CTRL_1:      reg_data = last_pkt_ctrl_1;
         endcase
      end
   end


   always @(posedge clk) begin

      reg_rd_wr_L_out <= reg_rd_wr_L_in;
      reg_addr_out <= reg_addr_in;
      reg_src_out <= reg_src_in;

      if( reset ) begin
         reg_req_out <= 1'b0;
         reg_ack_out <= 1'b0;
         reg_data_out <= 'h0;
      end
      else begin
         if(reg_req_in && tag_hit) begin
            if(addr_good) begin
               reg_data_out <= reg_data;
            end
            else begin
               reg_data_out <= 32'hdead_beef;
            end


            reg_ack_out <= 1'b1;
         end
         else begin
            reg_ack_out <= reg_ack_in;
            reg_data_out <= reg_data_in;
         end
         reg_req_out <= reg_req_in;
      end
   end

endmodule
module in_arb_regs
    #( parameter DATA_WIDTH = 64,
       parameter CTRL_WIDTH = DATA_WIDTH/8,
       parameter UDP_REG_SRC_WIDTH = 2
       )
   
   ( 
      input                                  reg_req_in,
      input                                  reg_ack_in,
      input                                  reg_rd_wr_L_in,
      input  [`UDP_REG_ADDR_WIDTH-1:0]       reg_addr_in,
      input  [`CPCI_NF2_DATA_WIDTH-1:0]      reg_data_in,
      input  [UDP_REG_SRC_WIDTH-1:0]         reg_src_in,

      output reg                             reg_req_out,
      output reg                             reg_ack_out,
      output reg                             reg_rd_wr_L_out,
      output reg [`UDP_REG_ADDR_WIDTH-1:0]   reg_addr_out,
      output reg [`CPCI_NF2_DATA_WIDTH-1:0]  reg_data_out,
      output reg [UDP_REG_SRC_WIDTH-1:0]     reg_src_out,

      input                                  state,
      input                                  out_wr,
      input [CTRL_WIDTH-1:0]                 out_ctrl,
      input [DATA_WIDTH-1:0]                 out_data,
      input                                  out_rdy,
      input                                  eop,

      input                                  clk,
      input                                  reset
     );


   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction


   localparam NUM_REGS_USED = 8;
   localparam ADDR_WIDTH = log2(NUM_REGS_USED);



   wire [ADDR_WIDTH-1:0]                              addr;
   wire [`IN_ARB_REG_ADDR_WIDTH - 1:0]                reg_addr;
   wire [((`UDP_REG_ADDR_WIDTH-`IN_ARB_REG_ADDR_WIDTH) - 1):0] tag_addr;

   wire                                               addr_good;
   wire                                               tag_hit;

   reg                                                in_pkt;
   reg                                                second_word;

   reg                                                state_latched;
   reg                                                out_rdy_latched;

   reg [CTRL_WIDTH-1:0]                               last_pkt_ctrl_0;
   reg [DATA_WIDTH-1:0]                               last_pkt_data_0;

   reg [CTRL_WIDTH-1:0]                               last_pkt_ctrl_1;
   reg [DATA_WIDTH-1:0]                               last_pkt_data_1;

   reg [`CPCI_NF2_DATA_WIDTH-1:0]                     eop_cnt;

   reg [`CPCI_NF2_DATA_WIDTH-1:0]                     reg_data;

   wire                                               first_word;



   assign addr = reg_addr_in[ADDR_WIDTH-1:0];
   assign reg_addr = reg_addr_in[`IN_ARB_REG_ADDR_WIDTH-1:0];
   assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:`IN_ARB_REG_ADDR_WIDTH];

   assign addr_good = reg_addr[`IN_ARB_REG_ADDR_WIDTH-1:ADDR_WIDTH] == 'h0 &&
      addr < NUM_REGS_USED;
   assign tag_hit = tag_addr == `IN_ARB_BLOCK_ADDR;


   always @(posedge clk)
   begin

      if (reset || (reg_req_in && tag_hit && addr == `IN_ARB_NUM_PKTS_SENT))
         eop_cnt <= 'h0;
      else if (eop)
         eop_cnt <= eop_cnt + 'h1;

      if (reset) begin
         state_latched <= 0;
	 out_rdy_latched <= 0;

         last_pkt_ctrl_0 <= 'h0;
         last_pkt_data_0 <= 'h0;

         last_pkt_ctrl_1 <= 'h0;
         last_pkt_data_1 <= 'h0;
      end
      else begin
         state_latched <= state;
	 out_rdy_latched <= out_rdy;

         if (first_word && out_wr) begin
            last_pkt_ctrl_0 <= out_ctrl;
            last_pkt_data_0 <= out_data;
         end
         
         if (second_word && out_wr) begin
            last_pkt_ctrl_1 <= out_ctrl;
            last_pkt_data_1 <= out_data;
         end
      end
   end



   assign first_word = !in_pkt && !(|out_ctrl);
   always @(posedge clk)
   begin
      if (reset) begin
         in_pkt <= 0;
         second_word <= 0;
      end
      else begin
         if (first_word && out_wr)
            in_pkt <= 1'b1;
         else if (in_pkt && |out_ctrl && out_wr)
            in_pkt <= 1'b0;

         if(first_word && out_wr) begin
            second_word <= 1;
         end
         else if(second_word==1 && out_wr) begin
            second_word <= 0;
         end
      end
   end



   always @*
   begin
      if (reset) begin
         reg_data = 'h0;
      end
      else begin
         case (addr)
            `IN_ARB_NUM_PKTS_SENT:        reg_data = eop_cnt;
            `IN_ARB_STATE:                reg_data = {{(`CPCI_NF2_DATA_WIDTH-2){1'b0}}, out_rdy_latched, state_latched};
            `IN_ARB_LAST_PKT_WORD_0_LO:   reg_data = last_pkt_data_0[31:0];
            `IN_ARB_LAST_PKT_WORD_0_HI:   reg_data = last_pkt_data_0[63:32];
            `IN_ARB_LAST_PKT_CTRL_0:      reg_data = last_pkt_ctrl_0;
            `IN_ARB_LAST_PKT_WORD_1_LO:   reg_data = last_pkt_data_1[31:0];
            `IN_ARB_LAST_PKT_WORD_1_HI:   reg_data = last_pkt_data_1[63:32];
            `IN_ARB_LAST_PKT_CTRL_1:      reg_data = last_pkt_ctrl_1;
         endcase
      end
   end


   always @(posedge clk) begin

      reg_rd_wr_L_out <= reg_rd_wr_L_in;
      reg_addr_out <= reg_addr_in;
      reg_src_out <= reg_src_in;

      if( reset ) begin
         reg_req_out <= 1'b0;
         reg_ack_out <= 1'b0;
         reg_data_out <= 'h0;
      end
      else begin
         if(reg_req_in && tag_hit) begin
            if(addr_good) begin
               reg_data_out <= reg_data;
            end
            else begin
               reg_data_out <= 32'hdead_beef;
            end


            reg_ack_out <= 1'b1;
         end
         else begin
            reg_ack_out <= reg_ack_in;
            reg_data_out <= reg_data_in;
         end
         reg_req_out <= reg_req_in;
      end
   end

endmodule