data/full_repos/permissive/106330868/verilog/source/source.v
data/verilator_xmls/08ef7ed6-dfba-44a1-b35c-13fafa225a1d.xml
module SOURCE (
        clk, 
        rst_an, 
        period,
        amplitude,
        strobe,
        period_done,
        source_out
    );


	input clk;


    input rst_an;


	output reg signed [15:0] source_out;
    output reg period_done;


    input [14:0] amplitude;
    input [7:0]  period;
    input        strobe;


    reg signed [7:0] periodcnt;
    reg        [16:0] lfsr;
    reg        last_strobe;

    always @(posedge clk, negedge rst_an)
    begin
        if (rst_an == 0)
        begin

            periodcnt <= 0;
            period_done <= 1;
            source_out <= 0;
            last_strobe <= 0;
            lfsr <= 17'h1;
        end
        else
        begin

            period_done <= 0;

            if ((strobe == 1) && (last_strobe == 0))
            begin


                if (period == 0)
                begin



                    if (periodcnt >= 64)                        
                    begin
                        periodcnt <= 0;
                        period_done <= 1;
                    end
                    else
                        periodcnt <= periodcnt + 1;
                    

                    lfsr <= {lfsr[15:0], lfsr[16] ^ lfsr[2]};
                    source_out <= lfsr[0] ? {1'b0, amplitude} : {1'b1, ~amplitude};
                end
                else
                begin




                    if (periodcnt >= period)
                    begin
                        periodcnt <= 0;
                        period_done <= 1;
                    end
                    else
                        periodcnt <= periodcnt + 1;

                    if (periodcnt < 8)
                        source_out <= {1'b0, amplitude};
                    else
                        source_out <= 16'h0000;  




                    lfsr <= 17'h1;
                end
            end
            last_strobe <= strobe;
        end
    end

endmodule
module SOURCE (
        clk, 
        rst_an, 
        period,
        amplitude,
        strobe,
        period_done,
        source_out
    );



	input clk;


    input rst_an;


	output reg signed [15:0] source_out;
    output reg period_done;


    input [14:0] amplitude;
    input [7:0]  period;
    input        strobe;


    reg signed [7:0] periodcnt;
    reg        [16:0] lfsr;
    reg        last_strobe;

    always @(posedge clk, negedge rst_an)
    begin
        if (rst_an == 0)
        begin

            periodcnt <= 0;
            period_done <= 1;
            source_out <= 0;
            last_strobe <= 0;
            lfsr <= 17'h1;
        end
        else
        begin

            period_done <= 0;

            if ((strobe == 1) && (last_strobe == 0))
            begin


                if (period == 0)
                begin



                    if (periodcnt >= 64)                        
                    begin
                        periodcnt <= 0;
                        period_done <= 1;
                    end
                    else
                        periodcnt <= periodcnt + 1;
                    

                    lfsr <= {lfsr[15:0], lfsr[16] ^ lfsr[2]};
                    source_out <= lfsr[0] ? {1'b0, amplitude} : {1'b1, ~amplitude};
                end
                else
                begin




                    if (periodcnt >= period)
                    begin
                        periodcnt <= 0;
                        period_done <= 1;
                    end
                    else
                        periodcnt <= periodcnt + 1;

                    if (periodcnt < 8)
                        source_out <= {1'b0, amplitude};
                    else
                        source_out <= 16'h0000;  




                    lfsr <= 17'h1;
                end
            end
            last_strobe <= strobe;
        end
    end

endmodule