data/full_repos/permissive/189567834/DD_FIR/DD_FIR.srcs/sources_1/imports/vivado_demo/code/fp16_norm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/189567834/DD_FIR/DD_FIR.srcs/sources_1/imports/vivado_demo/code/fp16_norm.v:39: Operator SUB expects 6 bits on the RHS, but RHS\'s VARREF \'zeros\' generates 4 bits.\n                                                                                                                         : ... In instance fadd_norm\n   exp0 = temp_exp - zeros;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189567834/DD_FIR/DD_FIR.srcs/sources_1/imports/vivado_demo/code/fp16_norm.v:51: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'frac_plus_1\' generates 1 bits.\n                                                                                                                         : ... In instance fadd_norm\n wire[11:0] frac_round = {1\'b0, frac0[13:3]} + frac_plus_1;\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/189567834/DD_FIR/DD_FIR.srcs/sources_1/imports/vivado_demo/code/fp16_norm.v:52: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s COND generates 6 bits.\n                                                                                                                         : ... In instance fadd_norm\n wire[4:0] exponent = frac_round[11] ?\n                    ^\n%Error: Exiting due to 3 warning(s)\n'
module fadd_norm (sign,temp_exp,cal_frac,s);
	input sign;
	input[4:0] temp_exp;
	input[14:0] cal_frac;
	output[15:0] s;

    wire [13:0] f3, f2, f1, f0;


	wire [3:0] zeros;
	assign zeros[3] = ~|cal_frac[13:6];
	assign f3 = zeros[3]? {cal_frac[5:0],8'b0} : cal_frac[13:0];
	assign zeros[2] = ~|f3[13:10];
	assign f2 = zeros[2]? {f3[9:0], 4'b0} : f3;
	assign zeros[1] = ~|f2[13:12];
	assign f1 = zeros[1]? {f2[11:0], 2'b0} : f2;
	assign zeros[0] = ~|f1[13];
	assign f0 = zeros[0]? {f1[12:0], 1'b0} : f1;
	reg [13:0] frac0;
	reg [5:0] exp0;


	always @ * begin

		if (cal_frac==0) begin
			frac0 = 0;
			exp0 = 0;
		end

		else if (cal_frac[14]) begin
			frac0 = cal_frac[14:1];
			exp0 = temp_exp + 5'h1;
		end

		else begin
			exp0 = temp_exp - zeros;
			frac0 = f0;
			
		end

	end


	wire frac_plus_1 =
	frac0[2] & (frac0[1] | frac0[0]) |
	frac0[2] & ~frac0[1] & ~frac0[0] & frac0[3];

	wire[11:0] frac_round = {1'b0, frac0[13:3]} + frac_plus_1;
	wire[4:0] exponent = frac_round[11] ?
							exp0 + 5'h1 :
							exp0;

	assign s = {sign, exponent, frac_round[9:0]};

endmodule
module fadd_norm (sign,temp_exp,cal_frac,s);

	input sign;
	input[4:0] temp_exp;
	input[14:0] cal_frac;
	output[15:0] s;

    wire [13:0] f3, f2, f1, f0;


	wire [3:0] zeros;
	assign zeros[3] = ~|cal_frac[13:6];
	assign f3 = zeros[3]? {cal_frac[5:0],8'b0} : cal_frac[13:0];
	assign zeros[2] = ~|f3[13:10];
	assign f2 = zeros[2]? {f3[9:0], 4'b0} : f3;
	assign zeros[1] = ~|f2[13:12];
	assign f1 = zeros[1]? {f2[11:0], 2'b0} : f2;
	assign zeros[0] = ~|f1[13];
	assign f0 = zeros[0]? {f1[12:0], 1'b0} : f1;
	reg [13:0] frac0;
	reg [5:0] exp0;


	always @ * begin

		if (cal_frac==0) begin
			frac0 = 0;
			exp0 = 0;
		end

		else if (cal_frac[14]) begin
			frac0 = cal_frac[14:1];
			exp0 = temp_exp + 5'h1;
		end

		else begin
			exp0 = temp_exp - zeros;
			frac0 = f0;
			
		end

	end


	wire frac_plus_1 =
	frac0[2] & (frac0[1] | frac0[0]) |
	frac0[2] & ~frac0[1] & ~frac0[0] & frac0[3];

	wire[11:0] frac_round = {1'b0, frac0[13:3]} + frac_plus_1;
	wire[4:0] exponent = frac_round[11] ?
							exp0 + 5'h1 :
							exp0;

	assign s = {sign, exponent, frac_round[9:0]};

endmodule