data/full_repos/permissive/19340845/test/MemoryTest.v
 line:44: before: "$"
1: b'%Error: data/full_repos/permissive/19340845/test/MemoryTest.v:9: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("Memory.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19340845/test/MemoryTest.v:10: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, MEMORYTEST);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19340845/test/MemoryTest.v:11: Unsupported or unknown PLI call: $monitor\n      $monitor("%t: write:%d, address:%d, data:%d, out = %d",\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 1; a = 4; d = 6;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 1; a = 3; d = 7;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 1; a = 8; d = 8;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 0; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 1; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 2; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 3; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 4; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 5; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 6; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 7; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 8; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 9; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 1; a = 4; d = 9;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 1; a = 5; d = 9;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 0; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 1; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 2; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 3; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 4; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 5; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 6; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 7; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 8; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #10 w = 0; a = 9; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MemoryTest.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #10 $finish;\n      ^\n%Error: Exiting due to 3 error(s), 26 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MEMORYTEST;

   reg [15:0] w, a, d;
   wire [15:0] out;

   Memory m (w, a, d, out);

   initial begin
      $dumpfile("Memory.vcd");
      $dumpvars(0, MEMORYTEST);
      $monitor("%t: write:%d, address:%d, data:%d, out = %d",
               $time, w, a, d, out);

      w = 1; a = 0; d = 5;
      #10 w = 1; a = 4; d = 6;
      #10 w = 1; a = 3; d = 7;
      #10 w = 1; a = 8; d = 8;

      #10 w = 0; a = 0; d = 0;
      #10 w = 0; a = 1; d = 0;
      #10 w = 0; a = 2; d = 0;
      #10 w = 0; a = 3; d = 0;
      #10 w = 0; a = 4; d = 0;
      #10 w = 0; a = 5; d = 0;
      #10 w = 0; a = 6; d = 0;
      #10 w = 0; a = 7; d = 0;
      #10 w = 0; a = 8; d = 0;
      #10 w = 0; a = 9; d = 0;

      #10 w = 1; a = 4; d = 9;
      #10 w = 1; a = 5; d = 9;

      #10 w = 0; a = 0; d = 0;
      #10 w = 0; a = 1; d = 0;
      #10 w = 0; a = 2; d = 0;
      #10 w = 0; a = 3; d = 0;
      #10 w = 0; a = 4; d = 0;
      #10 w = 0; a = 5; d = 0;
      #10 w = 0; a = 6; d = 0;
      #10 w = 0; a = 7; d = 0;
      #10 w = 0; a = 8; d = 0;
      #10 w = 0; a = 9; d = 0;

      #10 $finish;
   end

endmodule
module MEMORYTEST;


   reg [15:0] w, a, d;
   wire [15:0] out;

   Memory m (w, a, d, out);

   initial begin
      $dumpfile("Memory.vcd");
      $dumpvars(0, MEMORYTEST);
      $monitor("%t: write:%d, address:%d, data:%d, out = %d",
               $time, w, a, d, out);

      w = 1; a = 0; d = 5;
      #10 w = 1; a = 4; d = 6;
      #10 w = 1; a = 3; d = 7;
      #10 w = 1; a = 8; d = 8;

      #10 w = 0; a = 0; d = 0;
      #10 w = 0; a = 1; d = 0;
      #10 w = 0; a = 2; d = 0;
      #10 w = 0; a = 3; d = 0;
      #10 w = 0; a = 4; d = 0;
      #10 w = 0; a = 5; d = 0;
      #10 w = 0; a = 6; d = 0;
      #10 w = 0; a = 7; d = 0;
      #10 w = 0; a = 8; d = 0;
      #10 w = 0; a = 9; d = 0;

      #10 w = 1; a = 4; d = 9;
      #10 w = 1; a = 5; d = 9;

      #10 w = 0; a = 0; d = 0;
      #10 w = 0; a = 1; d = 0;
      #10 w = 0; a = 2; d = 0;
      #10 w = 0; a = 3; d = 0;
      #10 w = 0; a = 4; d = 0;
      #10 w = 0; a = 5; d = 0;
      #10 w = 0; a = 6; d = 0;
      #10 w = 0; a = 7; d = 0;
      #10 w = 0; a = 8; d = 0;
      #10 w = 0; a = 9; d = 0;

      #10 $finish;
   end

endmodule