data/full_repos/permissive/194847941/demo/12_game/sources/rtl/vga/vga_box.v
data/verilator_xmls/97bdbf25-9ac8-40e3-b888-8df911029144.xml
module vga_box
#(
	parameter X = 640,
	parameter Y = 480
)
(
	input	wire		clk,
	

	input	wire		hs_i,
	input	wire		vs_i,
	input	wire		axis_en,
	input	wire [10:0]	axis_x,
	input	wire [10:0] axis_y,
	

	output	reg			hs_o,
	output	reg			vs_o,
	output	reg [15:0]	rgb_o
);


always@(posedge clk)
begin
	if(axis_en)
	begin
		if(axis_x == 0)
			rgb_o <= {5'b11111,6'b000000,5'b00000};
		else if(axis_x == X - 1)
			rgb_o <= {5'b00000,6'b000000,5'b11111};
		else if(axis_y == 0)
			rgb_o <= {5'b00000,6'b111111,5'b00000};
		else if(axis_y == Y - 1)
			rgb_o <= {5'b11111,6'b111111,5'b11111};
		else
			rgb_o <= {5'b00000,6'b00000,5'b00000};
	end
	else
		rgb_o <= {5'b00000,6'b00000,5'b00000};
end

always@(posedge clk)
begin
	hs_o <= hs_i;
	vs_o <= vs_i;
end

endmodule
module vga_box
#(
	parameter X = 640,
	parameter Y = 480
)
(
	input	wire		clk,
	

	input	wire		hs_i,
	input	wire		vs_i,
	input	wire		axis_en,
	input	wire [10:0]	axis_x,
	input	wire [10:0] axis_y,
	

	output	reg			hs_o,
	output	reg			vs_o,
	output	reg [15:0]	rgb_o
);



always@(posedge clk)
begin
	if(axis_en)
	begin
		if(axis_x == 0)
			rgb_o <= {5'b11111,6'b000000,5'b00000};
		else if(axis_x == X - 1)
			rgb_o <= {5'b00000,6'b000000,5'b11111};
		else if(axis_y == 0)
			rgb_o <= {5'b00000,6'b111111,5'b00000};
		else if(axis_y == Y - 1)
			rgb_o <= {5'b11111,6'b111111,5'b11111};
		else
			rgb_o <= {5'b00000,6'b00000,5'b00000};
	end
	else
		rgb_o <= {5'b00000,6'b00000,5'b00000};
end

always@(posedge clk)
begin
	hs_o <= hs_i;
	vs_o <= vs_i;
end

endmodule