data/full_repos/permissive/143278/ivltests/case_priority.v
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case_priority.v:7: Unsupported: Ignoring delay on this delayed statement.\n   initial forever #1 clk <= ~clk;\n                   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-INFINITELOOP: data/full_repos/permissive/143278/ivltests/case_priority.v:7: Infinite loop (condition always true)\n                                                                                   : ... In instance main\n   initial forever #1 clk <= ~clk;\n           ^~~~~~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
   logic [1:0] counter = 2'b00;
   logic       clk = 1'b0;

   initial forever #1 clk <= ~clk;

   always @(posedge clk) begin
      counter <= counter + 2'd1;

      priority case (counter)
      2'd0: $display("case 0");
      2'd1: $display("case 1");
      2'd3: $display("case 3");
      endcase

      if (counter == 2'd3) begin
         $display("PASSED");
         $finish(0);
      end
   end
endmodule
module main;

   logic [1:0] counter = 2'b00;
   logic       clk = 1'b0;

   initial forever #1 clk <= ~clk;

   always @(posedge clk) begin
      counter <= counter + 2'd1;

      priority case (counter)
      2'd0: $display("case 0");
      2'd1: $display("case 1");
      2'd3: $display("case 3");
      endcase

      if (counter == 2'd3) begin
         $display("PASSED");
         $finish(0);
      end
   end
endmodule