data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v
1: b'%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:23: Cannot find include file: encoder.v\n`include "encoder.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/coding_theory/syn/src,data/full_repos/permissive/20688874/encoder.v\n             data/full_repos/permissive/20688874/coding_theory/syn/src,data/full_repos/permissive/20688874/encoder.v.v\n             data/full_repos/permissive/20688874/coding_theory/syn/src,data/full_repos/permissive/20688874/encoder.v.sv\n             encoder.v\n             encoder.v.v\n             encoder.v.sv\n             obj_dir/encoder.v\n             obj_dir/encoder.v.v\n             obj_dir/encoder.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n     #5 clk = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n     #5 clk = 1;\n     ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:100: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:107: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:114: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:121: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:128: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:135: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:142: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:149: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:156: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:163: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:170: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:177: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/src/ee577bHw2q2tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: Exiting due to 13 error(s), 15 warning(s)\n'
module tb_arbiter();

	

	wire [3:0] grant_vector;
	

	reg [3:0] req_vector;
	reg clk,reset,enable;
	
	
	

	always begin

    	#5 clk = 0;
    	#5 clk = 1;
    end	
	
	

	arbiter_LRU4 arb (


		grant_vector,req_vector,enable,clk,reset);
	

	

	initial
	begin

		$display($time, " << Starting the simulation >>");
		reset = 1;
		enable = 0;
		req_vector = 4'b1010;
		

		@(posedge clk);
		#1;
		reset = 0;
		enable = 0;
		req_vector = 4'b1110;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1111;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1000;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1011;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b0111;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 0;
		req_vector = 4'b1110;
		
		
		@(posedge clk);
		#1;
		reset = 1;
		enable = 0;
		req_vector = 4'b1011;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1100;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1101;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1010;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1111;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1110;
		
		

		#20;
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_arbiter();


	

	wire [3:0] grant_vector;
	

	reg [3:0] req_vector;
	reg clk,reset,enable;
	
	
	

	always begin

    	#5 clk = 0;
    	#5 clk = 1;
    end	
	
	

	arbiter_LRU4 arb (


		grant_vector,req_vector,enable,clk,reset);
	

	

	initial
	begin

		$display($time, " << Starting the simulation >>");
		reset = 1;
		enable = 0;
		req_vector = 4'b1010;
		

		@(posedge clk);
		#1;
		reset = 0;
		enable = 0;
		req_vector = 4'b1110;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1111;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1000;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1011;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b0111;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 0;
		req_vector = 4'b1110;
		
		
		@(posedge clk);
		#1;
		reset = 1;
		enable = 0;
		req_vector = 4'b1011;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1100;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1101;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1010;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1111;
		
		
		@(posedge clk);
		#1;
		reset = 0;
		enable = 1;
		req_vector = 4'b1110;
		
		

		#20;
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule