data/full_repos/permissive/200314387/verilog/cpu/ports.v
 line:9: before: "package"
data/verilator_xmls/4908362f-7892-424e-b126-d37170b1c07d.xml
function PortName portNameWR; input [3:0] portno;
        PortName tmp;
        begin
            case(portno)
                 3 : portNameWR =    "TIMER1";
                 4 : portNameWR =    "TIMER2";
                 7 : portNameWR =    "PARALLEL";

                default: begin
                    $sformat(tmp,"??(%d)",portno);
                    portNameWR = tmp;
                end
            endcase
        end
    endfunction
function PortName portNameWR;
 input [3:0] portno;
        PortName tmp;
        begin
            case(portno)
                 3 : portNameWR =    "TIMER1";
                 4 : portNameWR =    "TIMER2";
                 7 : portNameWR =    "PARALLEL";

                default: begin
                    $sformat(tmp,"??(%d)",portno);
                    portNameWR = tmp;
                end
            endcase
        end
    endfunction