data/full_repos/permissive/207835546/Switches/switch_test.v
1: b'%Error: data/full_repos/permissive/207835546/Switches/switch_test.v:2: Cannot find include file: Switch.v\n`include "Switch.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207835546/Switches,data/full_repos/permissive/207835546/Switch.v\n             data/full_repos/permissive/207835546/Switches,data/full_repos/permissive/207835546/Switch.v.v\n             data/full_repos/permissive/207835546/Switches,data/full_repos/permissive/207835546/Switch.v.sv\n             Switch.v\n             Switch.v.v\n             Switch.v.sv\n             obj_dir/Switch.v\n             obj_dir/Switch.v.v\n             obj_dir/Switch.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/207835546/Switches/switch_test.v:15: Unsupported: Ignoring delay on this delayed statement.\n   #5 {s0,s1,i0,i1,i2,i3}=k;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/207835546/Switches/switch_test.v:22: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("switch_wave.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/207835546/Switches/switch_test.v:23: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module mux41_test;

reg s0,s1,i0,i1,i2,i3;
wire out;
integer k;

mux_4to1 DUT (out,s0,s1,i0,i1,i2,i3);

initial begin 
	for (k=0; k<64;k=k+1)
		begin 
			#5 {s0,s1,i0,i1,i2,i3}=k;
			$display ("Sel: %2b, IN: %4b, Out: %b",{s0,s1},{i0,i1,i2,i3},out);
		end
end

initial 
begin 
 $dumpfile ("switch_wave.vcd");
 $dumpvars;

 end
endmodule
module mux41_test;


reg s0,s1,i0,i1,i2,i3;
wire out;
integer k;

mux_4to1 DUT (out,s0,s1,i0,i1,i2,i3);

initial begin 
	for (k=0; k<64;k=k+1)
		begin 
			#5 {s0,s1,i0,i1,i2,i3}=k;
			$display ("Sel: %2b, IN: %4b, Out: %b",{s0,s1},{i0,i1,i2,i3},out);
		end
end

initial 
begin 
 $dumpfile ("switch_wave.vcd");
 $dumpvars;

 end
endmodule