data/full_repos/permissive/118082957/testbench/indiv_tb.v
 line:17: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #10 $display ("A = %b B = %b opALU = %b || Rout = %b", A, B, opALU, Rout);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #10 $display ("A = %b B = %b opALU = %b || Rout = %b", A, B, opALU, Rout);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10 rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #10 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("Q = %h", q);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#435\n^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n%Error: data/full_repos/permissive/118082957/testbench/indiv_tb.v:100: Unsupported or unknown PLI call: $monitor\n$monitor("ADDR 0002: %d \\n",$time,CPUTEST.dut.ram_ins.mem256x16[16\'h0002]);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n#20 rst=1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n#10000\n^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RAMTEST;
reg we;
reg [15:0]  d;
wire [15:0] q;
reg [7:0] addr;

	ram ram_ins(we, d, q, addr);

initial begin
$readmemh("memory.list", ram_ins.mem256x16);

	#10 we = 1;
		addr = 8'hc;
		d = 16'hf;
	#10 we = 0;
	#10 $display ("Q = %h", q);

#435
$display("ADDR 0000: %h\n",ram_ins.mem256x16[16'h0000]);
$display("ADDR 0001: %h\n",ram_ins.mem256x16[16'h0001]);
$display("ADDR 0002: %h\n",ram_ins.mem256x16[16'h0002]);
$display("ADDR 0003: %h\n",ram_ins.mem256x16[16'h0003]);
$display("ADDR 0004: %h\n",ram_ins.mem256x16[16'h0004]);
$display("ADDR 0005: %h\n",ram_ins.mem256x16[16'h0005]);
$display("ADDR 0006: %h\n",ram_ins.mem256x16[16'h0006]);
$display("ADDR 0007: %h\n",ram_ins.mem256x16[16'h0007]);
$display("ADDR 0008: %h\n",ram_ins.mem256x16[16'h0008]);
$display("ADDR 0009: %h\n",ram_ins.mem256x16[16'h0009]);
$display("ADDR 000a: %h\n",ram_ins.mem256x16[16'h000a]);
$display("ADDR 000b: %h\n",ram_ins.mem256x16[16'h000b]);
$display("ADDR 000c: %h\n",ram_ins.mem256x16[16'h000c]);
$display("ADDR 000d: %h\n",ram_ins.mem256x16[16'h000d]);
$display("ADDR 000e: %h\n",ram_ins.mem256x16[16'h000e]);
$finish;
end

endmodule
module RAMTEST;

reg we;
reg [15:0]  d;
wire [15:0] q;
reg [7:0] addr;

	ram ram_ins(we, d, q, addr);

initial begin
$readmemh("memory.list", ram_ins.mem256x16);

	#10 we = 1;
		addr = 8'hc;
		d = 16'hf;
	#10 we = 0;
	#10 $display ("Q = %h", q);

#435
$display("ADDR 0000: %h\n",ram_ins.mem256x16[16'h0000]);
$display("ADDR 0001: %h\n",ram_ins.mem256x16[16'h0001]);
$display("ADDR 0002: %h\n",ram_ins.mem256x16[16'h0002]);
$display("ADDR 0003: %h\n",ram_ins.mem256x16[16'h0003]);
$display("ADDR 0004: %h\n",ram_ins.mem256x16[16'h0004]);
$display("ADDR 0005: %h\n",ram_ins.mem256x16[16'h0005]);
$display("ADDR 0006: %h\n",ram_ins.mem256x16[16'h0006]);
$display("ADDR 0007: %h\n",ram_ins.mem256x16[16'h0007]);
$display("ADDR 0008: %h\n",ram_ins.mem256x16[16'h0008]);
$display("ADDR 0009: %h\n",ram_ins.mem256x16[16'h0009]);
$display("ADDR 000a: %h\n",ram_ins.mem256x16[16'h000a]);
$display("ADDR 000b: %h\n",ram_ins.mem256x16[16'h000b]);
$display("ADDR 000c: %h\n",ram_ins.mem256x16[16'h000c]);
$display("ADDR 000d: %h\n",ram_ins.mem256x16[16'h000d]);
$display("ADDR 000e: %h\n",ram_ins.mem256x16[16'h000e]);
$finish;
end

endmodule