data/full_repos/permissive/157049472/Verilog Source Files/Data_memory.v
1: b'%Error: Cannot find file containing module: Source\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Source\n             data/full_repos/permissive/157049472/Verilog/Source.v\n             data/full_repos/permissive/157049472/Verilog/Source.sv\n             Source\n             Source.v\n             Source.sv\n             obj_dir/Source\n             obj_dir/Source.v\n             obj_dir/Source.sv\n%Error: Cannot find file containing module: Files,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Files/Data_memory.v\n%Error: Exiting due to 4 error(s)\n'
module Data_memory(input wire clk, input wire rst, input wire [9:0] address,
						 input wire [31:0] data_in, input wire MemRead, input wire MemWrite,
						 output wire [31:0] data_out);

reg [31:0] Memory[1023:0];
integer i;
always @(posedge clk or posedge rst)
begin
	if(rst)
	begin
		for(i=0;i<1024;i=i+1)
			Memory[i] = 32'd0;

		Memory[0] = 32'd2;
		Memory[1] = 32'd3;
		Memory[2] = 32'd1;
		Memory[3] = 32'd4;
		Memory[4] = 32'd8;
		Memory[5] = 32'd5;
		Memory[6] = 32'd7;
		Memory[7] = 32'd6;
	end
	else
	begin
		if(MemWrite)
			Memory[address] = data_in;
	end
end

		assign data_out = (MemRead)?Memory[address[3:0]]:32'b0;
		
endmodule
module Data_memory(input wire clk, input wire rst, input wire [9:0] address,
						 input wire [31:0] data_in, input wire MemRead, input wire MemWrite,
						 output wire [31:0] data_out);


reg [31:0] Memory[1023:0];
integer i;
always @(posedge clk or posedge rst)
begin
	if(rst)
	begin
		for(i=0;i<1024;i=i+1)
			Memory[i] = 32'd0;

		Memory[0] = 32'd2;
		Memory[1] = 32'd3;
		Memory[2] = 32'd1;
		Memory[3] = 32'd4;
		Memory[4] = 32'd8;
		Memory[5] = 32'd5;
		Memory[6] = 32'd7;
		Memory[7] = 32'd6;
	end
	else
	begin
		if(MemWrite)
			Memory[address] = data_in;
	end
end

		assign data_out = (MemRead)?Memory[address[3:0]]:32'b0;
		
endmodule