data/full_repos/permissive/205673649/BIP/Source/pc.v
data/verilator_xmls/01554648-483e-41fb-a58a-3158f1ca1755.xml
module pc
#(
    parameter NB_PC = 11
)
(
    input i_clk,
    input i_rst,
    input i_enable,
    output reg [NB_PC-1:0] o_addr
);

always @(negedge i_clk) 
begin
    if(!i_rst)
        o_addr <= 0;
    else
    begin
        if(i_enable)
            o_addr <= o_addr + 1'b1;
        else
            o_addr <= o_addr;
    end
end
endmodule
module pc
#(
    parameter NB_PC = 11
)
(
    input i_clk,
    input i_rst,
    input i_enable,
    output reg [NB_PC-1:0] o_addr
);


always @(negedge i_clk) 
begin
    if(!i_rst)
        o_addr <= 0;
    else
    begin
        if(i_enable)
            o_addr <= o_addr + 1'b1;
        else
            o_addr <= o_addr;
    end
end
endmodule