data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:42: Cannot find include file: spi_defines.v\n`include "spi_defines.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup,data/full_repos/permissive/19905110/spi_defines.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup,data/full_repos/permissive/19905110/spi_defines.v.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup,data/full_repos/permissive/19905110/spi_defines.v.sv\n             spi_defines.v\n             spi_defines.v.v\n             spi_defines.v.sv\n             obj_dir/spi_defines.v\n             obj_dir/spi_defines.v.v\n             obj_dir/spi_defines.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:43: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:72: Define or directive not defined: \'`SPI_SS_NB\'\n   output [`SPI_SS_NB-1:0]      ss_pad_o;          \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:82: Define or directive not defined: \'`SPI_CTRL_BIT_NB\'\n   wire [`SPI_CTRL_BIT_NB-1:0]      ctrl;              \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:83: Define or directive not defined: \'`SPI_SS_NB\'\n   reg [`SPI_SS_NB-1:0]      ss;                \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:84: Define or directive not defined: \'`SPI_MAX_CHAR\'\n   wire [`SPI_MAX_CHAR-1:0]      rx;                \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:104: Define or directive not defined: \'`SPI_OFS_BITS\'\n   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);\n                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:104: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);\n                                                                         ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:104: Define or directive not defined: \'`SPI_CTRL\'\n   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);\n                                                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:105: Define or directive not defined: \'`SPI_OFS_BITS\'\n   assign spi_tx_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);\n                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:105: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign spi_tx_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);\n                                                                         ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:105: Define or directive not defined: \'`SPI_TX_0\'\n   assign spi_tx_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);\n                                                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:106: Define or directive not defined: \'`SPI_OFS_BITS\'\n   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);\n                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:106: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);\n                                                                         ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:106: Define or directive not defined: \'`SPI_SS\'\n   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);\n                                                                              ^~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:115: Define or directive not defined: \'`SPI_OFS_BITS\'\n       case (wb_adr_i[`SPI_OFS_BITS])\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:115: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n       case (wb_adr_i[`SPI_OFS_BITS])\n                                   ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:116: Define or directive not defined: \'`SPI_RX_0\'\n  `SPI_RX_0:    wb_dat_o <= rx;  \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:117: Define or directive not defined: \'`SPI_CTRL\'\n  `SPI_CTRL:    wb_dat_o <= {18\'d0, ctrl};\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:118: Define or directive not defined: \'`SPI_DEVIDE\'\n  `SPI_DEVIDE:  wb_dat_o <= divider;\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:119: Define or directive not defined: \'`SPI_SS\'\n  `SPI_SS:      wb_dat_o <= {{32-`SPI_SS_NB{1\'b0}}, ss};\n  ^~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:119: Define or directive not defined: \'`SPI_SS_NB\'\n  `SPI_SS:      wb_dat_o <= {{32-`SPI_SS_NB{1\'b0}}, ss};\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:176: Define or directive not defined: \'`SPI_SS_NB\'\n       ss <= #Tp {`SPI_SS_NB{1\'b0}};\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:179: Define or directive not defined: \'`SPI_SS_NB\'\n         ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:181: Define or directive not defined: \'`SPI_SS_NB\'\n   assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));\n                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:181: Define or directive not defined: \'`SPI_SS_NB\'\n   assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));\n                                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_top.v:205: Define or directive not defined: \'`SPI_CHAR_LEN_BITS\'\n      .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),\n                    ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 27 error(s)\n'
module spi_flash_top
  (

   wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
   wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, 

   ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
   );
   
   parameter divider_len = 2;
   parameter divider = 0;
   
   parameter Tp = 1;
   

   input                            wb_clk_i;
   input                            wb_rst_i;
   input [4:2] 			    wb_adr_i;
   input [31:0] 		    wb_dat_i;
   output [31:0] 		    wb_dat_o;
   input [3:0] 			    wb_sel_i;
   input                            wb_we_i;
   input                            wb_stb_i;
   input                            wb_cyc_i;
   output                           wb_ack_o;
   

   output [`SPI_SS_NB-1:0] 	    ss_pad_o;
   output                           sclk_pad_o;
   output                           mosi_pad_o;
   input                            miso_pad_i;
   
   reg [31:0] 			    wb_dat_o;
   reg                              wb_ack_o;
   


   wire [`SPI_CTRL_BIT_NB-1:0] 	    ctrl;
   reg [`SPI_SS_NB-1:0] 	    ss;
   wire [`SPI_MAX_CHAR-1:0] 	    rx;

   wire [5:0] 			    char_len;
   reg 				    char_len_ctrl;
   reg 				    go;
   
   wire 			    spi_ctrl_sel;
   wire 			    spi_tx_sel;
   wire 			    spi_ss_sel;
   wire                             tip;
   wire                             pos_edge;
   wire                             neg_edge;
   wire                             last_bit;

  wire                             rx_negedge;
  wire                             tx_negedge;
  wire                             lsb;
  wire                             ass;
   

   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
   assign spi_tx_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);
  


   always @(posedge wb_clk_i or posedge wb_rst_i)
  begin
     if (wb_rst_i)
       wb_dat_o <= #Tp 32'b0;
     else
       case (wb_adr_i[`SPI_OFS_BITS])
	 `SPI_RX_0:    wb_dat_o <= rx;	 
	 `SPI_CTRL:    wb_dat_o <= {18'd0, ctrl};
	 `SPI_DEVIDE:  wb_dat_o <= divider;
	 `SPI_SS:      wb_dat_o <= {{32-`SPI_SS_NB{1'b0}}, ss};
	default:      wb_dat_o  <= rx;
       endcase
  end
  

   always @(posedge wb_clk_i or posedge wb_rst_i)
     begin
	if (wb_rst_i)
	  wb_ack_o <= #Tp 1'b0;
    else
      wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
     end
   

   always @(posedge wb_clk_i or posedge wb_rst_i)
     begin
	if (wb_rst_i)
	  {go,char_len_ctrl} <= #Tp 2'b01;
	else if(spi_ctrl_sel && wb_we_i && !tip)
	  begin
             if (wb_sel_i[0])
               char_len_ctrl <= #Tp wb_dat_i[5];
             if (wb_sel_i[1])
	       go <= #Tp wb_dat_i[8];
	  end
	else if(tip && last_bit && pos_edge)
	  go <= #Tp 1'b0;
     end

   assign char_len = char_len_ctrl ? 6'd32 : 6'd8;   
`ifdef SPI_CTRL_ASS
   assign ass = 1'b1;
`else
   assign ass = 1'b0;
`endif
`ifdef SPI_CTRL_LSB
   assign lsb = 1'b1;
`else
   assign lsb = 1'b0;
`endif
`ifdef SPI_CTRL_RX_NEGEDGE
   assign rx_negedge = 1'b1;
`else
   assign rx_negedge = 1'b0;
`endif
`ifdef SPI_CTRL_TX_NEGEDGE
   assign tx_negedge = 1'b1;
`else
   assign tx_negedge = 1'b0;
`endif

   assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len};
   

   always @(posedge wb_clk_i or posedge wb_rst_i)
     if (wb_rst_i)
       ss <= #Tp {`SPI_SS_NB{1'b0}};
     else if(spi_ss_sel && wb_we_i && !tip)
       if (wb_sel_i[0])
         ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
   
   assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
 
   spi_flash_clgen
     #
     (
      .divider_len(divider_len),
      .divider(divider)
      )
     clgen 
       (
	.clk_in(wb_clk_i), 
	.rst(wb_rst_i), 
	.go(go), 
	.enable(tip), 
	.last_clk(last_bit),
	.clk_out(sclk_pad_o), 
	.pos_edge(pos_edge), 
        .neg_edge(neg_edge)
	);
  
   spi_flash_shift  shift 
     (
      .clk(wb_clk_i), 
      .rst(wb_rst_i), 
      .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
      .latch(spi_tx_sel & wb_we_i), 
      .byte_sel(wb_sel_i),
      .go(go), 
      .pos_edge(pos_edge), 
      .neg_edge(neg_edge),
      .lsb(lsb),
      .rx_negedge(rx_negedge), 
      .tx_negedge(tx_negedge), 
      .tip(tip), 
      .last(last_bit), 
      .p_in(wb_dat_i), 
      .p_out(rx), 
      .s_clk(sclk_pad_o), 
      .s_in(miso_pad_i), 
      .s_out(mosi_pad_o)
      );
   
endmodule
module spi_flash_top
  (

   wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
   wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, 

   ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
   );

   
   parameter divider_len = 2;
   parameter divider = 0;
   
   parameter Tp = 1;
   

   input                            wb_clk_i;
   input                            wb_rst_i;
   input [4:2] 			    wb_adr_i;
   input [31:0] 		    wb_dat_i;
   output [31:0] 		    wb_dat_o;
   input [3:0] 			    wb_sel_i;
   input                            wb_we_i;
   input                            wb_stb_i;
   input                            wb_cyc_i;
   output                           wb_ack_o;
   

   output [`SPI_SS_NB-1:0] 	    ss_pad_o;
   output                           sclk_pad_o;
   output                           mosi_pad_o;
   input                            miso_pad_i;
   
   reg [31:0] 			    wb_dat_o;
   reg                              wb_ack_o;
   


   wire [`SPI_CTRL_BIT_NB-1:0] 	    ctrl;
   reg [`SPI_SS_NB-1:0] 	    ss;
   wire [`SPI_MAX_CHAR-1:0] 	    rx;

   wire [5:0] 			    char_len;
   reg 				    char_len_ctrl;
   reg 				    go;
   
   wire 			    spi_ctrl_sel;
   wire 			    spi_tx_sel;
   wire 			    spi_ss_sel;
   wire                             tip;
   wire                             pos_edge;
   wire                             neg_edge;
   wire                             last_bit;

  wire                             rx_negedge;
  wire                             tx_negedge;
  wire                             lsb;
  wire                             ass;
   

   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
   assign spi_tx_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);
  


   always @(posedge wb_clk_i or posedge wb_rst_i)
  begin
     if (wb_rst_i)
       wb_dat_o <= #Tp 32'b0;
     else
       case (wb_adr_i[`SPI_OFS_BITS])
	 `SPI_RX_0:    wb_dat_o <= rx;	 
	 `SPI_CTRL:    wb_dat_o <= {18'd0, ctrl};
	 `SPI_DEVIDE:  wb_dat_o <= divider;
	 `SPI_SS:      wb_dat_o <= {{32-`SPI_SS_NB{1'b0}}, ss};
	default:      wb_dat_o  <= rx;
       endcase
  end
  

   always @(posedge wb_clk_i or posedge wb_rst_i)
     begin
	if (wb_rst_i)
	  wb_ack_o <= #Tp 1'b0;
    else
      wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
     end
   

   always @(posedge wb_clk_i or posedge wb_rst_i)
     begin
	if (wb_rst_i)
	  {go,char_len_ctrl} <= #Tp 2'b01;
	else if(spi_ctrl_sel && wb_we_i && !tip)
	  begin
             if (wb_sel_i[0])
               char_len_ctrl <= #Tp wb_dat_i[5];
             if (wb_sel_i[1])
	       go <= #Tp wb_dat_i[8];
	  end
	else if(tip && last_bit && pos_edge)
	  go <= #Tp 1'b0;
     end

   assign char_len = char_len_ctrl ? 6'd32 : 6'd8;   
`ifdef SPI_CTRL_ASS
   assign ass = 1'b1;
`else
   assign ass = 1'b0;
`endif
`ifdef SPI_CTRL_LSB
   assign lsb = 1'b1;
`else
   assign lsb = 1'b0;
`endif
`ifdef SPI_CTRL_RX_NEGEDGE
   assign rx_negedge = 1'b1;
`else
   assign rx_negedge = 1'b0;
`endif
`ifdef SPI_CTRL_TX_NEGEDGE
   assign tx_negedge = 1'b1;
`else
   assign tx_negedge = 1'b0;
`endif

   assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len};
   

   always @(posedge wb_clk_i or posedge wb_rst_i)
     if (wb_rst_i)
       ss <= #Tp {`SPI_SS_NB{1'b0}};
     else if(spi_ss_sel && wb_we_i && !tip)
       if (wb_sel_i[0])
         ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
   
   assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
 
   spi_flash_clgen
     #
     (
      .divider_len(divider_len),
      .divider(divider)
      )
     clgen 
       (
	.clk_in(wb_clk_i), 
	.rst(wb_rst_i), 
	.go(go), 
	.enable(tip), 
	.last_clk(last_bit),
	.clk_out(sclk_pad_o), 
	.pos_edge(pos_edge), 
        .neg_edge(neg_edge)
	);
  
   spi_flash_shift  shift 
     (
      .clk(wb_clk_i), 
      .rst(wb_rst_i), 
      .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
      .latch(spi_tx_sel & wb_we_i), 
      .byte_sel(wb_sel_i),
      .go(go), 
      .pos_edge(pos_edge), 
      .neg_edge(neg_edge),
      .lsb(lsb),
      .rx_negedge(rx_negedge), 
      .tx_negedge(tx_negedge), 
      .tip(tip), 
      .last(last_bit), 
      .p_in(wb_dat_i), 
      .p_out(rx), 
      .s_clk(sclk_pad_o), 
      .s_in(miso_pad_i), 
      .s_out(mosi_pad_o)
      );
   
endmodule