data/full_repos/permissive/194847941/demo/15_ov5640_sdram/src/sccb/I2C_Controller.v
 line:1 column:1: Illegal character '\x00'
data/verilator_xmls/fb361ea7-8925-492f-9236-7f9ea0a8a438.xml
module I2C_Controller 
(

	input			clk,		
	input			rst_n,		
	

	input			i2c_clk,
	input			i2c_en,
	input	[39:0]	i2c_wdata,
	output			i2c_sclk,
 	inout			i2c_sdat,
	input			wr,
	input			trans,
	output			ack,
	output	reg		i2c_end,
	output	reg	[7:0]	i2c_rdata
);



reg			i2c_bit;
reg 		sclk;
reg	[6:0]	sd_counter;


wire 	i2c_sclk1 = 	(trans == 1 &&
						((sd_counter >= 5 && sd_counter <=12 || sd_counter == 14) ||	
						(sd_counter >= 16 && sd_counter <=23 || sd_counter == 25) ||
						(sd_counter >= 27 && sd_counter <=34 || sd_counter == 36) ||
						(sd_counter >= 38 && sd_counter <=45 || sd_counter == 47))) ? i2c_clk : sclk;


wire 	i2c_sclk2 = 	(trans == 1 &&
						((sd_counter >= 5 && sd_counter <=12 || sd_counter == 14) ||
						(sd_counter >= 16 && sd_counter <=23 || sd_counter == 25) ||
						(sd_counter >= 27 && sd_counter <=34 || sd_counter == 36) ||
						(sd_counter >= 44 && sd_counter <=52 || sd_counter == 54) ||
						(sd_counter >= 56 && sd_counter <=63 || sd_counter == 65))) ? i2c_clk : sclk;		
						
assign	i2c_sclk = wr ? i2c_sclk1 : i2c_sclk2;	

wire	sdo1	=		((sd_counter == 13 || sd_counter == 14) || 
						 (sd_counter == 24 || sd_counter == 25) || 
						 (sd_counter == 35 || sd_counter == 36) ||
						 (sd_counter == 46 || sd_counter == 47)) ? 1'b0 : 1'b1;
						
wire	sdo2	=		((sd_counter == 13 || sd_counter == 14)|| 
						(sd_counter == 24 || sd_counter == 25) || 
						(sd_counter == 35 || sd_counter == 36) ||
						(sd_counter == 53 || sd_counter == 54) ||
						(sd_counter >= 55 && sd_counter <= 63)) ? 1'b0 : 1'b1;
						
wire	SDO = wr ? sdo1 : sdo2;

assign	i2c_sdat = SDO ? i2c_bit : 1'bz;





reg	ackw1, ackw2, ackw3,ackw4;
reg 	ackr1, ackr2, ackr3,ackr4;
assign	ack = wr ? (ackw1 | ackw2 | ackw3 | ackw4) : (ackr1 | ackr2 | ackr3 | ackr4);




always @(posedge clk or negedge rst_n) 
begin
	if (!rst_n) 
		sd_counter <= 7'b0;
	else if(i2c_en)
		begin
		if (trans == 0 || i2c_end == 1) 
			sd_counter <= 7'b0;
		else if (sd_counter < 7'd70) 
			sd_counter <= sd_counter + 7'd1;	
		end
	else
		sd_counter <= sd_counter;
end



always @(posedge clk or negedge rst_n) 
begin
    if(!rst_n) 
		begin 
		sclk <= 1;
		i2c_bit <= 1; 
		ackw1 <= 1; ackw2 <= 1; ackw3 <= 1;ackw4 <= 1; 
		ackr1 <= 1; ackr2 <= 1; ackr3 <= 1;ackr4 <= 1;
		i2c_end <= 0;
		i2c_rdata <= 8'h0;	
		end
	else if(i2c_en)
		begin
		if(trans)
			begin
			if(wr)
				begin
				case(sd_counter)

				7'd0 :begin
						sclk <= 1;
						i2c_bit <= 1;
						ackw1 <= 1; ackw2 <= 1; ackw3 <= 1; ackw4 <= 1;
						ackr1 <= 1; ackr2 <= 1; ackr3 <= 1; ackr4 <= 1;
						i2c_end <= 0;
						end

				7'd1 :	begin 
						sclk <= 1;
						i2c_bit <= 1;
						ackw1 <= 1; ackw2 <= 1; ackw3 <= 1;ackw4<=1;
						i2c_end <= 0;
						end
				7'd2  : i2c_bit <= 0;
				7'd3  : sclk <= 0;
				

				7'd4  : i2c_bit <= i2c_wdata[31];
				7'd5  : i2c_bit <= i2c_wdata[30];
				7'd6  : i2c_bit <= i2c_wdata[29];
				7'd7  : i2c_bit <= i2c_wdata[28];
				7'd8  : i2c_bit <= i2c_wdata[27];
				7'd9  : i2c_bit <= i2c_wdata[26];
				7'd10 : i2c_bit <= i2c_wdata[25];
				7'd11 : i2c_bit <= i2c_wdata[24];
				7'd12 : i2c_bit <= 0;
				7'd13 : ackw1 	<= i2c_sdat;
				7'd14 : i2c_bit <= 0;
				

				7'd15 : i2c_bit <= i2c_wdata[23];
				7'd16 : i2c_bit <= i2c_wdata[22];
				7'd17 : i2c_bit <= i2c_wdata[21];
				7'd18 : i2c_bit <= i2c_wdata[20];
				7'd19 : i2c_bit <= i2c_wdata[19];
				7'd20 : i2c_bit <= i2c_wdata[18];
				7'd21 : i2c_bit <= i2c_wdata[17];
				7'd22 : i2c_bit <= i2c_wdata[16];
				7'd23 : i2c_bit <= 0;
				7'd24 : ackw2 	<= i2c_sdat;
				7'd25 : i2c_bit <= 0;
				
				7'd26 : i2c_bit <= i2c_wdata[15];
				7'd27 : i2c_bit <= i2c_wdata[14];
				7'd28 : i2c_bit <= i2c_wdata[13];
				7'd29 : i2c_bit <= i2c_wdata[12];
				7'd30 : i2c_bit <= i2c_wdata[11];
				7'd31 : i2c_bit <= i2c_wdata[10];
				7'd32 : i2c_bit <= i2c_wdata[9];
				7'd33 : i2c_bit <= i2c_wdata[8];
				7'd34 : i2c_bit <= 0;
				7'd35 : ackw3 	<= i2c_sdat;
				7'd36 : i2c_bit <= 0;
				

				7'd37 : i2c_bit <= i2c_wdata[7];
				7'd38 : i2c_bit <= i2c_wdata[6];
				7'd39 : i2c_bit <= i2c_wdata[5];
				7'd40 : i2c_bit <= i2c_wdata[4];
				7'd41 : i2c_bit <= i2c_wdata[3];
				7'd42 : i2c_bit <= i2c_wdata[2];
				7'd43 : i2c_bit <= i2c_wdata[1];
				7'd44 : i2c_bit <= i2c_wdata[0];
				7'd45 : i2c_bit <= 0;
				7'd46 : ackw4 	<= i2c_sdat;
				7'd47 : i2c_bit <= 0;


				7'd48 : begin	sclk <= 0; i2c_bit <= 0; end
				7'd49 : sclk <= 1;	
				7'd50 : begin i2c_bit <= 1; i2c_end <= 1; end 
				default : begin i2c_bit <= 1; sclk <= 1; end
				endcase
				end
			else
				begin
				case(sd_counter)

				7'd0 :begin
						sclk <= 1;
						i2c_bit <= 1;
						ackw1 <= 1; ackw2 <= 1; ackw3 <= 1; ackw4 <= 1;
						ackr1 <= 1; ackr2 <= 1; ackr3 <= 1; ackr4 <= 1; 
						i2c_end <= 0;
						end


				7'd1 :begin 
						sclk <= 1;
						i2c_bit <= 1;
						ackr1 <= 1; ackr2 <= 1; ackr3 <= 1; ackr4 <= 1;
						i2c_end <= 0;
						end
				7'd2  : i2c_bit <= 0;
				7'd3  : sclk <= 0;
				

				7'd4  : i2c_bit <= i2c_wdata[31];
				7'd5  : i2c_bit <= i2c_wdata[30];
				7'd6  : i2c_bit <= i2c_wdata[29];
				7'd7  : i2c_bit <= i2c_wdata[28];
				7'd8  : i2c_bit <= i2c_wdata[27];
				7'd9  : i2c_bit <= i2c_wdata[26];
				7'd10 : i2c_bit <= i2c_wdata[25];
				7'd11 : i2c_bit <= i2c_wdata[24];
				7'd12 : i2c_bit <= 0;
				7'd13 : ackr1 	<= i2c_sdat;
				7'd14 : i2c_bit <= 0;
				

				7'd15 : i2c_bit <= i2c_wdata[23];
				7'd16 : i2c_bit <= i2c_wdata[22];
				7'd17 : i2c_bit <= i2c_wdata[21];
				7'd18 : i2c_bit <= i2c_wdata[20];
				7'd19 : i2c_bit <= i2c_wdata[19];
				7'd20 : i2c_bit <= i2c_wdata[18];
				7'd21 : i2c_bit <= i2c_wdata[17];
				7'd22 : i2c_bit <= i2c_wdata[16];
				7'd23 : i2c_bit <= 0;
				7'd24 : ackr2 	<= i2c_sdat;
				7'd25 : i2c_bit <= 0;

				7'd26 : i2c_bit <= i2c_wdata[15];
				7'd27 : i2c_bit <= i2c_wdata[14];
				7'd28 : i2c_bit <= i2c_wdata[13];
				7'd29 : i2c_bit <= i2c_wdata[12];
				7'd30 : i2c_bit <= i2c_wdata[11];
				7'd31 : i2c_bit <= i2c_wdata[10];
				7'd32 : i2c_bit <= i2c_wdata[9];
				7'd33 : i2c_bit <= i2c_wdata[8];
				7'd34 : i2c_bit <= 0;
				7'd35 : ackr3 	<= i2c_sdat;
				7'd36 : i2c_bit <= 0;
				

				7'd37 : begin	sclk <= 0; i2c_bit <= 0; end
				7'd38 : sclk <= 1;	
				7'd39 : begin i2c_bit <= 1;end 



				7'd40 :	begin 
						sclk <= 1;
						i2c_bit <= 1;
						end
				7'd41 : i2c_bit <= 0;
				7'd42 : sclk <= 0;
				

				7'd43 : i2c_bit <= i2c_wdata[39];
				7'd44 : i2c_bit <= i2c_wdata[38];
				7'd45 : i2c_bit <= i2c_wdata[37];
				7'd46 : i2c_bit <= i2c_wdata[36];
				7'd47 : i2c_bit <= i2c_wdata[35];
				7'd48 : i2c_bit <= i2c_wdata[34];
				7'd49 : i2c_bit <= i2c_wdata[33];
				7'd50 : i2c_bit <= i2c_wdata[32];
				7'd51 : i2c_bit <= 1'b1;
				7'd52 : i2c_bit <= 0;
				7'd53 : ackr4 	<= i2c_sdat;
				7'd54 : i2c_bit <= 0;
				

				7'd55 : i2c_bit 	  <= 0;
				7'd56 : i2c_rdata[7] <= i2c_sdat;
				7'd57 : i2c_rdata[6] <= i2c_sdat;
				7'd58 : i2c_rdata[5] <= i2c_sdat;
				7'd59 : i2c_rdata[4] <= i2c_sdat;
				7'd60 : i2c_rdata[3] <= i2c_sdat;
				7'd61 : i2c_rdata[2] <= i2c_sdat;
				7'd62 : i2c_rdata[1] <= i2c_sdat;
				7'd63 : i2c_rdata[0] <= i2c_sdat;
				7'd64 : i2c_bit 	  <= 1;
				7'd65 : i2c_bit 	  <= 0;
				

				7'd66 : begin	sclk <= 0; i2c_bit <= 0; end
				7'd67 : sclk <= 1;	
				7'd68 : begin i2c_bit <= 1; i2c_end <= 1; end 
				endcase
				end
			end
		else
			begin
			sclk <= 1;
			i2c_bit <= 1; 
			ackw1 <= 1; ackw2 <= 1; ackw3 <= 1; ackw4<=1;
			ackr1 <= 1; ackr2 <= 1; ackr3 <= 1; ackr4<=1;
			i2c_end <= 0;
			i2c_rdata <= i2c_rdata;
			end
		end
end
		
endmodule
module I2C_Controller 
(

	input			clk,		
	input			rst_n,		
	

	input			i2c_clk,
	input			i2c_en,
	input	[39:0]	i2c_wdata,
	output			i2c_sclk,
 	inout			i2c_sdat,
	input			wr,
	input			trans,
	output			ack,
	output	reg		i2c_end,
	output	reg	[7:0]	i2c_rdata
);




reg			i2c_bit;
reg 		sclk;
reg	[6:0]	sd_counter;


wire 	i2c_sclk1 = 	(trans == 1 &&
						((sd_counter >= 5 && sd_counter <=12 || sd_counter == 14) ||	
						(sd_counter >= 16 && sd_counter <=23 || sd_counter == 25) ||
						(sd_counter >= 27 && sd_counter <=34 || sd_counter == 36) ||
						(sd_counter >= 38 && sd_counter <=45 || sd_counter == 47))) ? i2c_clk : sclk;


wire 	i2c_sclk2 = 	(trans == 1 &&
						((sd_counter >= 5 && sd_counter <=12 || sd_counter == 14) ||
						(sd_counter >= 16 && sd_counter <=23 || sd_counter == 25) ||
						(sd_counter >= 27 && sd_counter <=34 || sd_counter == 36) ||
						(sd_counter >= 44 && sd_counter <=52 || sd_counter == 54) ||
						(sd_counter >= 56 && sd_counter <=63 || sd_counter == 65))) ? i2c_clk : sclk;		
						
assign	i2c_sclk = wr ? i2c_sclk1 : i2c_sclk2;	

wire	sdo1	=		((sd_counter == 13 || sd_counter == 14) || 
						 (sd_counter == 24 || sd_counter == 25) || 
						 (sd_counter == 35 || sd_counter == 36) ||
						 (sd_counter == 46 || sd_counter == 47)) ? 1'b0 : 1'b1;
						
wire	sdo2	=		((sd_counter == 13 || sd_counter == 14)|| 
						(sd_counter == 24 || sd_counter == 25) || 
						(sd_counter == 35 || sd_counter == 36) ||
						(sd_counter == 53 || sd_counter == 54) ||
						(sd_counter >= 55 && sd_counter <= 63)) ? 1'b0 : 1'b1;
						
wire	SDO = wr ? sdo1 : sdo2;

assign	i2c_sdat = SDO ? i2c_bit : 1'bz;





reg	ackw1, ackw2, ackw3,ackw4;
reg 	ackr1, ackr2, ackr3,ackr4;
assign	ack = wr ? (ackw1 | ackw2 | ackw3 | ackw4) : (ackr1 | ackr2 | ackr3 | ackr4);




always @(posedge clk or negedge rst_n) 
begin
	if (!rst_n) 
		sd_counter <= 7'b0;
	else if(i2c_en)
		begin
		if (trans == 0 || i2c_end == 1) 
			sd_counter <= 7'b0;
		else if (sd_counter < 7'd70) 
			sd_counter <= sd_counter + 7'd1;	
		end
	else
		sd_counter <= sd_counter;
end



always @(posedge clk or negedge rst_n) 
begin
    if(!rst_n) 
		begin 
		sclk <= 1;
		i2c_bit <= 1; 
		ackw1 <= 1; ackw2 <= 1; ackw3 <= 1;ackw4 <= 1; 
		ackr1 <= 1; ackr2 <= 1; ackr3 <= 1;ackr4 <= 1;
		i2c_end <= 0;
		i2c_rdata <= 8'h0;	
		end
	else if(i2c_en)
		begin
		if(trans)
			begin
			if(wr)
				begin
				case(sd_counter)

				7'd0 :begin
						sclk <= 1;
						i2c_bit <= 1;
						ackw1 <= 1; ackw2 <= 1; ackw3 <= 1; ackw4 <= 1;
						ackr1 <= 1; ackr2 <= 1; ackr3 <= 1; ackr4 <= 1;
						i2c_end <= 0;
						end

				7'd1 :	begin 
						sclk <= 1;
						i2c_bit <= 1;
						ackw1 <= 1; ackw2 <= 1; ackw3 <= 1;ackw4<=1;
						i2c_end <= 0;
						end
				7'd2  : i2c_bit <= 0;
				7'd3  : sclk <= 0;
				

				7'd4  : i2c_bit <= i2c_wdata[31];
				7'd5  : i2c_bit <= i2c_wdata[30];
				7'd6  : i2c_bit <= i2c_wdata[29];
				7'd7  : i2c_bit <= i2c_wdata[28];
				7'd8  : i2c_bit <= i2c_wdata[27];
				7'd9  : i2c_bit <= i2c_wdata[26];
				7'd10 : i2c_bit <= i2c_wdata[25];
				7'd11 : i2c_bit <= i2c_wdata[24];
				7'd12 : i2c_bit <= 0;
				7'd13 : ackw1 	<= i2c_sdat;
				7'd14 : i2c_bit <= 0;
				

				7'd15 : i2c_bit <= i2c_wdata[23];
				7'd16 : i2c_bit <= i2c_wdata[22];
				7'd17 : i2c_bit <= i2c_wdata[21];
				7'd18 : i2c_bit <= i2c_wdata[20];
				7'd19 : i2c_bit <= i2c_wdata[19];
				7'd20 : i2c_bit <= i2c_wdata[18];
				7'd21 : i2c_bit <= i2c_wdata[17];
				7'd22 : i2c_bit <= i2c_wdata[16];
				7'd23 : i2c_bit <= 0;
				7'd24 : ackw2 	<= i2c_sdat;
				7'd25 : i2c_bit <= 0;
				
				7'd26 : i2c_bit <= i2c_wdata[15];
				7'd27 : i2c_bit <= i2c_wdata[14];
				7'd28 : i2c_bit <= i2c_wdata[13];
				7'd29 : i2c_bit <= i2c_wdata[12];
				7'd30 : i2c_bit <= i2c_wdata[11];
				7'd31 : i2c_bit <= i2c_wdata[10];
				7'd32 : i2c_bit <= i2c_wdata[9];
				7'd33 : i2c_bit <= i2c_wdata[8];
				7'd34 : i2c_bit <= 0;
				7'd35 : ackw3 	<= i2c_sdat;
				7'd36 : i2c_bit <= 0;
				

				7'd37 : i2c_bit <= i2c_wdata[7];
				7'd38 : i2c_bit <= i2c_wdata[6];
				7'd39 : i2c_bit <= i2c_wdata[5];
				7'd40 : i2c_bit <= i2c_wdata[4];
				7'd41 : i2c_bit <= i2c_wdata[3];
				7'd42 : i2c_bit <= i2c_wdata[2];
				7'd43 : i2c_bit <= i2c_wdata[1];
				7'd44 : i2c_bit <= i2c_wdata[0];
				7'd45 : i2c_bit <= 0;
				7'd46 : ackw4 	<= i2c_sdat;
				7'd47 : i2c_bit <= 0;


				7'd48 : begin	sclk <= 0; i2c_bit <= 0; end
				7'd49 : sclk <= 1;	
				7'd50 : begin i2c_bit <= 1; i2c_end <= 1; end 
				default : begin i2c_bit <= 1; sclk <= 1; end
				endcase
				end
			else
				begin
				case(sd_counter)

				7'd0 :begin
						sclk <= 1;
						i2c_bit <= 1;
						ackw1 <= 1; ackw2 <= 1; ackw3 <= 1; ackw4 <= 1;
						ackr1 <= 1; ackr2 <= 1; ackr3 <= 1; ackr4 <= 1; 
						i2c_end <= 0;
						end


				7'd1 :begin 
						sclk <= 1;
						i2c_bit <= 1;
						ackr1 <= 1; ackr2 <= 1; ackr3 <= 1; ackr4 <= 1;
						i2c_end <= 0;
						end
				7'd2  : i2c_bit <= 0;
				7'd3  : sclk <= 0;
				

				7'd4  : i2c_bit <= i2c_wdata[31];
				7'd5  : i2c_bit <= i2c_wdata[30];
				7'd6  : i2c_bit <= i2c_wdata[29];
				7'd7  : i2c_bit <= i2c_wdata[28];
				7'd8  : i2c_bit <= i2c_wdata[27];
				7'd9  : i2c_bit <= i2c_wdata[26];
				7'd10 : i2c_bit <= i2c_wdata[25];
				7'd11 : i2c_bit <= i2c_wdata[24];
				7'd12 : i2c_bit <= 0;
				7'd13 : ackr1 	<= i2c_sdat;
				7'd14 : i2c_bit <= 0;
				

				7'd15 : i2c_bit <= i2c_wdata[23];
				7'd16 : i2c_bit <= i2c_wdata[22];
				7'd17 : i2c_bit <= i2c_wdata[21];
				7'd18 : i2c_bit <= i2c_wdata[20];
				7'd19 : i2c_bit <= i2c_wdata[19];
				7'd20 : i2c_bit <= i2c_wdata[18];
				7'd21 : i2c_bit <= i2c_wdata[17];
				7'd22 : i2c_bit <= i2c_wdata[16];
				7'd23 : i2c_bit <= 0;
				7'd24 : ackr2 	<= i2c_sdat;
				7'd25 : i2c_bit <= 0;

				7'd26 : i2c_bit <= i2c_wdata[15];
				7'd27 : i2c_bit <= i2c_wdata[14];
				7'd28 : i2c_bit <= i2c_wdata[13];
				7'd29 : i2c_bit <= i2c_wdata[12];
				7'd30 : i2c_bit <= i2c_wdata[11];
				7'd31 : i2c_bit <= i2c_wdata[10];
				7'd32 : i2c_bit <= i2c_wdata[9];
				7'd33 : i2c_bit <= i2c_wdata[8];
				7'd34 : i2c_bit <= 0;
				7'd35 : ackr3 	<= i2c_sdat;
				7'd36 : i2c_bit <= 0;
				

				7'd37 : begin	sclk <= 0; i2c_bit <= 0; end
				7'd38 : sclk <= 1;	
				7'd39 : begin i2c_bit <= 1;end 



				7'd40 :	begin 
						sclk <= 1;
						i2c_bit <= 1;
						end
				7'd41 : i2c_bit <= 0;
				7'd42 : sclk <= 0;
				

				7'd43 : i2c_bit <= i2c_wdata[39];
				7'd44 : i2c_bit <= i2c_wdata[38];
				7'd45 : i2c_bit <= i2c_wdata[37];
				7'd46 : i2c_bit <= i2c_wdata[36];
				7'd47 : i2c_bit <= i2c_wdata[35];
				7'd48 : i2c_bit <= i2c_wdata[34];
				7'd49 : i2c_bit <= i2c_wdata[33];
				7'd50 : i2c_bit <= i2c_wdata[32];
				7'd51 : i2c_bit <= 1'b1;
				7'd52 : i2c_bit <= 0;
				7'd53 : ackr4 	<= i2c_sdat;
				7'd54 : i2c_bit <= 0;
				

				7'd55 : i2c_bit 	  <= 0;
				7'd56 : i2c_rdata[7] <= i2c_sdat;
				7'd57 : i2c_rdata[6] <= i2c_sdat;
				7'd58 : i2c_rdata[5] <= i2c_sdat;
				7'd59 : i2c_rdata[4] <= i2c_sdat;
				7'd60 : i2c_rdata[3] <= i2c_sdat;
				7'd61 : i2c_rdata[2] <= i2c_sdat;
				7'd62 : i2c_rdata[1] <= i2c_sdat;
				7'd63 : i2c_rdata[0] <= i2c_sdat;
				7'd64 : i2c_bit 	  <= 1;
				7'd65 : i2c_bit 	  <= 0;
				

				7'd66 : begin	sclk <= 0; i2c_bit <= 0; end
				7'd67 : sclk <= 1;	
				7'd68 : begin i2c_bit <= 1; i2c_end <= 1; end 
				endcase
				end
			end
		else
			begin
			sclk <= 1;
			i2c_bit <= 1; 
			ackw1 <= 1; ackw2 <= 1; ackw3 <= 1; ackw4<=1;
			ackr1 <= 1; ackr2 <= 1; ackr3 <= 1; ackr4<=1;
			i2c_end <= 0;
			i2c_rdata <= i2c_rdata;
			end
		end
end
		
endmodule