data/full_repos/permissive/218779832/stackptr.v
data/verilator_xmls/931224b3-f144-465a-8dab-c7b9127da99c.xml
module stack 
(
    input wire clk,    
    input wire [7:0] r0,
    input wire [1:0] rw,
    output wire [7:0] address
);
    reg [7:0] stackptr = 8'hff; 


    assign address = rw[1] ? stackptr+1 : stackptr;

    always @ (posedge clk)
    begin 



    case (rw)
    2'b00 :stackptr <= stackptr;
    2'b01 :stackptr <= stackptr - 1;
    2'b10 :stackptr <= stackptr + 1;
    2'b11 :stackptr <= r0;
    endcase
    end
endmodule
module stack 
(
    input wire clk,    
    input wire [7:0] r0,
    input wire [1:0] rw,
    output wire [7:0] address
);

    reg [7:0] stackptr = 8'hff; 


    assign address = rw[1] ? stackptr+1 : stackptr;

    always @ (posedge clk)
    begin 



    case (rw)
    2'b00 :stackptr <= stackptr;
    2'b01 :stackptr <= stackptr - 1;
    2'b10 :stackptr <= stackptr + 1;
    2'b11 :stackptr <= r0;
    endcase
    end
endmodule