data/full_repos/permissive/143278/ivltests/pr1830834.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1830834.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr1830834.v:19: Unsupported or unknown PLI call: $strobe\n    $strobe("out: %b, in[%0d] %b:", out, j, in[j]);\n    ^~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1830834.v:22: Unsupported or unknown PLI call: $strobe\n    $strobe("out[3:0]: %b, in[%0d] %b:", out[j*1-1 +: 4], j, in[j]);\n    ^~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  reg[4:0] j;
  reg [5:0] in [1:0];
  wire [5:0] out;

  assign out = in[j];

  initial begin
    in[1] = 6'b110001;

    j = 1;
    #1;
    $display("out: %b, in[%0d] %b:", out, j, in[j]);
    $display("out[3:0]: %b, in[%0d] %b:", out[j*1-1 +: 4], j, in[j]);


    $strobe("out: %b, in[%0d] %b:", out, j, in[j]);


    $strobe("out[3:0]: %b, in[%0d] %b:", out[j*1-1 +: 4], j, in[j]);

  end

endmodule
module test;

  reg[4:0] j;
  reg [5:0] in [1:0];
  wire [5:0] out;

  assign out = in[j];

  initial begin
    in[1] = 6'b110001;

    j = 1;
    #1;
    $display("out: %b, in[%0d] %b:", out, j, in[j]);
    $display("out[3:0]: %b, in[%0d] %b:", out[j*1-1 +: 4], j, in[j]);


    $strobe("out: %b, in[%0d] %b:", out, j, in[j]);


    $strobe("out[3:0]: %b, in[%0d] %b:", out[j*1-1 +: 4], j, in[j]);

  end

endmodule