data/full_repos/permissive/135852214/Verilog/top_ver_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/top_ver_sim.v:42: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/top_ver_sim.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #3\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/top_ver_sim.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #52;\n  ^\n%Error: data/full_repos/permissive/135852214/Verilog/top_ver_sim.v:36: Cannot find file containing module: \'TOP_verilog\'\n TOP_verilog uut (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/TOP_verilog\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/TOP_verilog.v\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/TOP_verilog.sv\n             TOP_verilog\n             TOP_verilog.v\n             TOP_verilog.sv\n             obj_dir/TOP_verilog\n             obj_dir/TOP_verilog.v\n             obj_dir/TOP_verilog.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_ver_sim;


	reg clk;
	reg reset;


	wire defect_address;
	wire defect_data;


	TOP_verilog uut (
		.clk(clk), 
		.reset(reset), 
		.defect_address(defect_address), 
		.defect_data(defect_data)
	);
	always #10 clk = ~clk;
	initial begin

		clk = 0;
		reset = 0;
		#3
		reset = 1;
		#52;
		reset = 0;    
	end
endmodule
module top_ver_sim;



	reg clk;
	reg reset;


	wire defect_address;
	wire defect_data;


	TOP_verilog uut (
		.clk(clk), 
		.reset(reset), 
		.defect_address(defect_address), 
		.defect_data(defect_data)
	);
	always #10 clk = ~clk;
	initial begin

		clk = 0;
		reset = 0;
		#3
		reset = 1;
		#52;
		reset = 0;    
	end
endmodule