data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v:164: Bit extraction of var[5:0] requires 3 bit index, not 2 bits.\n                                                                                     : ... In instance Z80Reg.WSelectR\n    if(rstatus[{1\'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3\'b010};   \n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v:167: Bit extraction of var[5:0] requires 3 bit index, not 2 bits.\n                                                                                     : ... In instance Z80Reg.WSelectR\n    case({rstatus[5:4], rstatus[{1\'b1, rstatus[1]}]})\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v:106: Operator ADD expects 16 bits on the RHS, but RHS\'s LOGNOT generates 1 bits.\n                                                                                     : ... In instance Z80Reg\n wire [15:0]ADDR1 = ADDR + !ALU16OP[2];  \n                         ^\n%Error: Exiting due to 3 warning(s)\n'
module RAM16X8D_regs(
      output [7:0]DPO,
      output [7:0]SPO,
      input [3:0]A,
      input [7:0]D,
      input [3:0]DPRA,
      input WCLK,
      input WE
   );
	
	reg [7:0]data[15:0];
	assign DPO = data[DPRA];
	assign SPO = data[A];
	
	always @(posedge WCLK)
		if(WE) data[A] <= D;
		
`ifdef SIMULATE
integer	i;
initial
	begin
		for(i=0;i<15;i++)data[i]=0;
	end
`endif

endmodule
module RAM16X8D_regs(
      output [7:0]DPO,
      output [7:0]SPO,
      input [3:0]A,
      input [7:0]D,
      input [3:0]DPRA,
      input WCLK,
      input WE
   );

	
	reg [7:0]data[15:0];
	assign DPO = data[DPRA];
	assign SPO = data[A];
	
	always @(posedge WCLK)
		if(WE) data[A] <= D;
		
`ifdef SIMULATE
integer	i;
initial
	begin
		for(i=0;i<15;i++)data[i]=0;
	end
`endif

endmodule