data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v
None: at end of input
1: b'%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:9: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171607226/rtl/e203/redundant_core,data/full_repos/permissive/171607226/e203_defines.v\n             data/full_repos/permissive/171607226/rtl/e203/redundant_core,data/full_repos/permissive/171607226/e203_defines.v.v\n             data/full_repos/permissive/171607226/rtl/e203/redundant_core,data/full_repos/permissive/171607226/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:12: Define or directive not defined: \'`E203_PC_SIZE\'\n  output[`E203_PC_SIZE-1:0] inspect_pc,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:66: Define or directive not defined: \'`E203_INSTR_SIZE\'\n  output [`E203_INSTR_SIZE-1:0] ifu_o_ir, \n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:67: Define or directive not defined: \'`E203_PC_SIZE\'\n  output [`E203_PC_SIZE-1:0] ifu_o_pc,    \n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:71: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,\n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:72: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,\n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:112: Define or directive not defined: \'`E203_PC_SIZE\'\n  input[`E203_PC_SIZE-1:0] in_inspect_pc,\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:127: Define or directive not defined: \'`E203_INSTR_SIZE\'\n  input [`E203_INSTR_SIZE-1:0] in_ifu_o_ir, \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:128: Define or directive not defined: \'`E203_PC_SIZE\'\n  input [`E203_PC_SIZE-1:0] in_ifu_o_pc,    \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:132: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  input [`E203_RFIDX_WIDTH-1:0] in_ifu_o_rs1idx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:133: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  input [`E203_RFIDX_WIDTH-1:0] in_ifu_o_rs2idx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:145: Define or directive not defined: \'`E203_PC_SIZE\'\n   sirv_gnrl_dffl #(`E203_PC_SIZE)  inspect_pc_dffl (lden, in_inspect_pc, inspect_pc, clk);\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:169: Define or directive not defined: \'`E203_INSTR_SIZE\'\n  sirv_gnrl_dffl #(`E203_INSTR_SIZE)  ifu_o_ir_dffl (lden, in_ifu_o_ir, ifu_o_ir, clk);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:171: Define or directive not defined: \'`E203_PC_SIZE\'\n  sirv_gnrl_dffl #(`E203_PC_SIZE)  ifu_o_pc_dffl (lden, in_ifu_o_pc, ifu_o_pc, clk);\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:179: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  sirv_gnrl_dffl #(`E203_RFIDX_WIDTH)  ifu_o_rs1idx_dffl (lden, in_ifu_o_rs1idx, ifu_o_rs1idx, clk);\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/ifu_buffer.v:181: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  sirv_gnrl_dffl #(`E203_RFIDX_WIDTH)  ifu_o_rs2idx_dffl (lden, in_ifu_o_rs2idx, ifu_o_rs2idx, clk);\n                   ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 16 error(s)\n'
module ifu_buffer(
  output[`E203_PC_SIZE-1:0] inspect_pc,
  output ifu_active,



  `ifdef E203_HAS_ITCM










  output ifu2itcm_icb_cmd_valid,



  output [`E203_ITCM_ADDR_WIDTH-1:0]   ifu2itcm_icb_cmd_addr,



  output ifu2itcm_icb_rsp_ready,



  `endif

  `ifdef E203_HAS_MEM_ITF




  output ifu2biu_icb_cmd_valid,



  output [`E203_ADDR_SIZE-1:0]   ifu2biu_icb_cmd_addr,



  output ifu2biu_icb_rsp_ready,





  `endif




  output [`E203_INSTR_SIZE-1:0] ifu_o_ir,
  output [`E203_PC_SIZE-1:0] ifu_o_pc,
  output ifu_o_pc_vld,
  output ifu_o_misalgn,
  output ifu_o_buserr,
  output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
  output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
  output ifu_o_prdt_taken,
  output ifu_o_muldiv_b2b,               
  output ifu_o_valid,


  output  pipe_flush_ack,



  `ifdef E203_TIMING_BOOST

  `endif

      






  output ifu_halt_ack,













  input  clk,
  input lden,

  
  
  input[`E203_PC_SIZE-1:0] in_inspect_pc,
  input in_ifu_active,

  `ifdef E203_HAS_ITCM
  input in_ifu2itcm_icb_cmd_valid,
  input [`E203_ITCM_ADDR_WIDTH-1:0]   in_ifu2itcm_icb_cmd_addr,
  input in_ifu2itcm_icb_rsp_ready,
  `endif

  `ifdef E203_HAS_MEM_ITF
  input in_ifu2biu_icb_cmd_valid,
  input [`E203_ADDR_SIZE-1:0]   in_ifu2biu_icb_cmd_addr,
  input in_ifu2biu_icb_rsp_ready,

  `endif
  input [`E203_INSTR_SIZE-1:0] in_ifu_o_ir,
  input [`E203_PC_SIZE-1:0] in_ifu_o_pc,
  input in_ifu_o_pc_vld,
  input in_ifu_o_misalgn,
  input in_ifu_o_buserr,
  input [`E203_RFIDX_WIDTH-1:0] in_ifu_o_rs1idx,
  input [`E203_RFIDX_WIDTH-1:0] in_ifu_o_rs2idx,
  input in_ifu_o_prdt_taken,
  input in_ifu_o_muldiv_b2b,               
  input in_ifu_o_valid,
  input  in_pipe_flush_ack,
  `ifdef E203_TIMING_BOOST
  `endif

  input in_ifu_halt_ack
  );
  
  
   sirv_gnrl_dffl #(`E203_PC_SIZE)  inspect_pc_dffl (lden, in_inspect_pc, inspect_pc, clk);

   sirv_gnrl_dffl #(1)  ifu_active_dffl (lden, in_ifu_active, ifu_active, clk);


  `ifdef E203_HAS_ITCM

  sirv_gnrl_dffl #(1)  ifu2itcm_icb_cmd_valid_dffl (lden, in_ifu2itcm_icb_cmd_valid, ifu2itcm_icb_cmd_valid, clk);

  sirv_gnrl_dffl #(`E203_ITCM_ADDR_WIDTH)  ifu2itcm_icb_cmd_addr_dffl (lden, in_ifu2itcm_icb_cmd_addr, ifu2itcm_icb_cmd_addr, clk);

  sirv_gnrl_dffl #(1)  ifu2itcm_icb_rsp_ready_dffl (lden, in_ifu2itcm_icb_rsp_ready, ifu2itcm_icb_rsp_ready, clk);
  `endif

  `ifdef E203_HAS_MEM_ITF

  sirv_gnrl_dffl #(1)  ifu2biu_icb_cmd_valid_dffl (lden, in_ifu2biu_icb_cmd_valid, ifu2biu_icb_cmd_valid, clk);

  sirv_gnrl_dffl #(`E203_ADDR_SIZE)  ifu2biu_icb_cmd_addr_dffl (lden, in_ifu2biu_icb_cmd_addr, ifu2biu_icb_cmd_addr, clk); 

  sirv_gnrl_dffl #(1)  ifu2biu_icb_rsp_ready_dffl (lden, in_ifu2biu_icb_rsp_ready, ifu2biu_icb_rsp_ready, clk);

  `endif

  sirv_gnrl_dffl #(`E203_INSTR_SIZE)  ifu_o_ir_dffl (lden, in_ifu_o_ir, ifu_o_ir, clk);

  sirv_gnrl_dffl #(`E203_PC_SIZE)  ifu_o_pc_dffl (lden, in_ifu_o_pc, ifu_o_pc, clk);

  sirv_gnrl_dffl #(1)  ifu_o_pc_vld_dffl (lden, in_ifu_o_pc_vld, ifu_o_pc_vld, clk);

  sirv_gnrl_dffl #(1)  ifu_o_misalgn_dffl (lden, in_ifu_o_misalgn, ifu_o_misalgn, clk); 

  sirv_gnrl_dffl #(1)  ifu_o_buserr_dffl (lden, in_ifu_o_buserr, ifu_o_buserr, clk);

  sirv_gnrl_dffl #(`E203_RFIDX_WIDTH)  ifu_o_rs1idx_dffl (lden, in_ifu_o_rs1idx, ifu_o_rs1idx, clk);

  sirv_gnrl_dffl #(`E203_RFIDX_WIDTH)  ifu_o_rs2idx_dffl (lden, in_ifu_o_rs2idx, ifu_o_rs2idx, clk);

  sirv_gnrl_dffl #(1)  ifu_o_prdt_taken_dffl (lden, in_ifu_o_prdt_taken, ifu_o_prdt_taken, clk);

  sirv_gnrl_dffl #(1)  ifu_o_muldiv_b2b_dffl (lden, in_ifu_o_muldiv_b2b, ifu_o_muldiv_b2b, clk);

  sirv_gnrl_dffl #(1)  ifu_o_valid_dffl (lden, in_ifu_o_valid, ifu_o_valid, clk);

  sirv_gnrl_dffl #(1)  pipe_flush_ack_dffl (lden, in_pipe_flush_ack, pipe_flush_ack, clk);
  `ifdef E203_TIMING_BOOST
  `endif


  sirv_gnrl_dffl #(1)  ifu_halt_ack_dffl (lden, in_ifu_halt_ack, ifu_halt_ack, clk);
endmodule
module ifu_buffer(
  output[`E203_PC_SIZE-1:0] inspect_pc,
  output ifu_active,



  `ifdef E203_HAS_ITCM










  output ifu2itcm_icb_cmd_valid,



  output [`E203_ITCM_ADDR_WIDTH-1:0]   ifu2itcm_icb_cmd_addr,



  output ifu2itcm_icb_rsp_ready,



  `endif

  `ifdef E203_HAS_MEM_ITF




  output ifu2biu_icb_cmd_valid,



  output [`E203_ADDR_SIZE-1:0]   ifu2biu_icb_cmd_addr,



  output ifu2biu_icb_rsp_ready,





  `endif




  output [`E203_INSTR_SIZE-1:0] ifu_o_ir,
  output [`E203_PC_SIZE-1:0] ifu_o_pc,
  output ifu_o_pc_vld,
  output ifu_o_misalgn,
  output ifu_o_buserr,
  output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
  output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
  output ifu_o_prdt_taken,
  output ifu_o_muldiv_b2b,               
  output ifu_o_valid,


  output  pipe_flush_ack,



  `ifdef E203_TIMING_BOOST

  `endif

      






  output ifu_halt_ack,













  input  clk,
  input lden,

  
  
  input[`E203_PC_SIZE-1:0] in_inspect_pc,
  input in_ifu_active,

  `ifdef E203_HAS_ITCM
  input in_ifu2itcm_icb_cmd_valid,
  input [`E203_ITCM_ADDR_WIDTH-1:0]   in_ifu2itcm_icb_cmd_addr,
  input in_ifu2itcm_icb_rsp_ready,
  `endif

  `ifdef E203_HAS_MEM_ITF
  input in_ifu2biu_icb_cmd_valid,
  input [`E203_ADDR_SIZE-1:0]   in_ifu2biu_icb_cmd_addr,
  input in_ifu2biu_icb_rsp_ready,

  `endif
  input [`E203_INSTR_SIZE-1:0] in_ifu_o_ir,
  input [`E203_PC_SIZE-1:0] in_ifu_o_pc,
  input in_ifu_o_pc_vld,
  input in_ifu_o_misalgn,
  input in_ifu_o_buserr,
  input [`E203_RFIDX_WIDTH-1:0] in_ifu_o_rs1idx,
  input [`E203_RFIDX_WIDTH-1:0] in_ifu_o_rs2idx,
  input in_ifu_o_prdt_taken,
  input in_ifu_o_muldiv_b2b,               
  input in_ifu_o_valid,
  input  in_pipe_flush_ack,
  `ifdef E203_TIMING_BOOST
  `endif

  input in_ifu_halt_ack
  );

  
  
   sirv_gnrl_dffl #(`E203_PC_SIZE)  inspect_pc_dffl (lden, in_inspect_pc, inspect_pc, clk);

   sirv_gnrl_dffl #(1)  ifu_active_dffl (lden, in_ifu_active, ifu_active, clk);


  `ifdef E203_HAS_ITCM

  sirv_gnrl_dffl #(1)  ifu2itcm_icb_cmd_valid_dffl (lden, in_ifu2itcm_icb_cmd_valid, ifu2itcm_icb_cmd_valid, clk);

  sirv_gnrl_dffl #(`E203_ITCM_ADDR_WIDTH)  ifu2itcm_icb_cmd_addr_dffl (lden, in_ifu2itcm_icb_cmd_addr, ifu2itcm_icb_cmd_addr, clk);

  sirv_gnrl_dffl #(1)  ifu2itcm_icb_rsp_ready_dffl (lden, in_ifu2itcm_icb_rsp_ready, ifu2itcm_icb_rsp_ready, clk);
  `endif

  `ifdef E203_HAS_MEM_ITF

  sirv_gnrl_dffl #(1)  ifu2biu_icb_cmd_valid_dffl (lden, in_ifu2biu_icb_cmd_valid, ifu2biu_icb_cmd_valid, clk);

  sirv_gnrl_dffl #(`E203_ADDR_SIZE)  ifu2biu_icb_cmd_addr_dffl (lden, in_ifu2biu_icb_cmd_addr, ifu2biu_icb_cmd_addr, clk); 

  sirv_gnrl_dffl #(1)  ifu2biu_icb_rsp_ready_dffl (lden, in_ifu2biu_icb_rsp_ready, ifu2biu_icb_rsp_ready, clk);

  `endif

  sirv_gnrl_dffl #(`E203_INSTR_SIZE)  ifu_o_ir_dffl (lden, in_ifu_o_ir, ifu_o_ir, clk);

  sirv_gnrl_dffl #(`E203_PC_SIZE)  ifu_o_pc_dffl (lden, in_ifu_o_pc, ifu_o_pc, clk);

  sirv_gnrl_dffl #(1)  ifu_o_pc_vld_dffl (lden, in_ifu_o_pc_vld, ifu_o_pc_vld, clk);

  sirv_gnrl_dffl #(1)  ifu_o_misalgn_dffl (lden, in_ifu_o_misalgn, ifu_o_misalgn, clk); 

  sirv_gnrl_dffl #(1)  ifu_o_buserr_dffl (lden, in_ifu_o_buserr, ifu_o_buserr, clk);

  sirv_gnrl_dffl #(`E203_RFIDX_WIDTH)  ifu_o_rs1idx_dffl (lden, in_ifu_o_rs1idx, ifu_o_rs1idx, clk);

  sirv_gnrl_dffl #(`E203_RFIDX_WIDTH)  ifu_o_rs2idx_dffl (lden, in_ifu_o_rs2idx, ifu_o_rs2idx, clk);

  sirv_gnrl_dffl #(1)  ifu_o_prdt_taken_dffl (lden, in_ifu_o_prdt_taken, ifu_o_prdt_taken, clk);

  sirv_gnrl_dffl #(1)  ifu_o_muldiv_b2b_dffl (lden, in_ifu_o_muldiv_b2b, ifu_o_muldiv_b2b, clk);

  sirv_gnrl_dffl #(1)  ifu_o_valid_dffl (lden, in_ifu_o_valid, ifu_o_valid, clk);

  sirv_gnrl_dffl #(1)  pipe_flush_ack_dffl (lden, in_pipe_flush_ack, pipe_flush_ack, clk);
  `ifdef E203_TIMING_BOOST
  `endif


  sirv_gnrl_dffl #(1)  ifu_halt_ack_dffl (lden, in_ifu_halt_ack, ifu_halt_ack, clk);
endmodule