data/full_repos/permissive/136056083/src/Controller.v
data/verilator_xmls/5a86c240-d32d-456d-b48d-c99f76e4cf1d.xml
module Controller(instruction, unconditionalBranch, branch, memRead, memToReg,
    aluControlCode, memWrite, aluSRC, regWriteFlag, readRegister1,
    readRegister2,  writeRegister, clock , invertZeroFlag, opType) ;

   `define LD_TYPE 0
   `define CB_TYPE 1
   `define R_TYPE  2
   `define ST_TYPE 3
   `define I_TYPE  4
   `define B_TYPE  5
   `define M_TYPE  6


    input clock;
    input [31:0] instruction;

    output wire unconditionalBranch;
    output wire branch;
    output wire memRead;
    output wire memToReg;
    output reg [3:0] aluControlCode;
    output wire memWrite;
    output wire aluSRC;
    output wire regWriteFlag;
    output wire invertZeroFlag;

    output reg [4:0] readRegister1;
    output reg [4:0] readRegister2;
    output reg [4:0] writeRegister;


    wire reg2Loc;
    output reg [2:0] opType;
    wire [1:0] aluOP;


    assign reg2Loc = opType == `CB_TYPE || opType == `ST_TYPE ? 1 : 0;
    assign aluSRC = opType == `R_TYPE || opType == `CB_TYPE || opType == `M_TYPE ? 0 : 1;
    assign memToReg = opType == `LD_TYPE ? 1 : 0;
    assign regWriteFlag = opType == `R_TYPE || opType == `LD_TYPE || opType == `M_TYPE || opType == `I_TYPE ? 1 : 0;
    assign memRead = opType == `LD_TYPE ? 1 : 0;
    assign memWrite = opType == `ST_TYPE ? 1 : 0;
    assign branch = opType == `CB_TYPE ? 1 : 0;
    assign unconditionalBranch = opType == `B_TYPE ? 1 : 0;

    assign aluOP = opType == `R_TYPE  ? 2 :
                   opType == `CB_TYPE ? 1 :
                   0;
    assign invertZeroFlag = opType == `CB_TYPE ? instruction[24] == 1 
                                                ? 1 :0
                                                :0;


    always @* begin

      if (instruction[26] == 1) begin
        if (instruction[29] == 1) begin opType <= `CB_TYPE; end
        else begin opType <= `B_TYPE;  end
      end
      else if (instruction[28] == 0) begin opType <= `R_TYPE; end
      else if (instruction[23] == 1) begin opType <= `M_TYPE; end
      else if (instruction[22] == 1) begin opType <= `LD_TYPE; end
      else if (instruction[27] == 1) begin opType <= `ST_TYPE; end
      else begin opType <= `I_TYPE; end



      readRegister1 <= instruction[9:5];
      if (reg2Loc == 0) begin readRegister2 <= instruction[20:16]; end
      else begin readRegister2 <= instruction[4:0]; end
      writeRegister <= instruction[4:0];


      if (opType == `LD_TYPE || opType == `ST_TYPE) begin aluControlCode <= 4'b0010; end
      else if (aluOP == 1) begin aluControlCode <= 4'b0111; end
      else if (opType == `M_TYPE) begin aluControlCode <= 4'b1101; end
      else if (aluOP == 2) begin
        if (instruction[24] == 1) begin
          if (instruction[30] == 0) begin aluControlCode <= 4'b0010; end
          else begin aluControlCode <= 4'b1010; end
        end
        else if (instruction[29] == 0) begin aluControlCode <= 4'b0110; end
        else if (instruction[30] == 0) begin aluControlCode <= 4'b0100; end
        else begin aluControlCode <= 4'b1001; end
      end
      else if (opType == `I_TYPE) begin
        if (instruction[29] == 1) begin aluControlCode <= 4'b0100; end
        else if (instruction[30] == 1) begin
          if (instruction[25] == 1) begin aluControlCode <= 4'b1001; end
          else begin aluControlCode <= 4'b1010; end
        end
        else if (instruction[25] == 1) begin aluControlCode <= 4'b0110; end
        else begin aluControlCode <=  4'b0010; end
      end
      else begin
        aluControlCode <= 0;
      end
    end

endmodule
module Controller(instruction, unconditionalBranch, branch, memRead, memToReg,
    aluControlCode, memWrite, aluSRC, regWriteFlag, readRegister1,
    readRegister2,  writeRegister, clock , invertZeroFlag, opType) ;


   `define LD_TYPE 0
   `define CB_TYPE 1
   `define R_TYPE  2
   `define ST_TYPE 3
   `define I_TYPE  4
   `define B_TYPE  5
   `define M_TYPE  6


    input clock;
    input [31:0] instruction;

    output wire unconditionalBranch;
    output wire branch;
    output wire memRead;
    output wire memToReg;
    output reg [3:0] aluControlCode;
    output wire memWrite;
    output wire aluSRC;
    output wire regWriteFlag;
    output wire invertZeroFlag;

    output reg [4:0] readRegister1;
    output reg [4:0] readRegister2;
    output reg [4:0] writeRegister;


    wire reg2Loc;
    output reg [2:0] opType;
    wire [1:0] aluOP;


    assign reg2Loc = opType == `CB_TYPE || opType == `ST_TYPE ? 1 : 0;
    assign aluSRC = opType == `R_TYPE || opType == `CB_TYPE || opType == `M_TYPE ? 0 : 1;
    assign memToReg = opType == `LD_TYPE ? 1 : 0;
    assign regWriteFlag = opType == `R_TYPE || opType == `LD_TYPE || opType == `M_TYPE || opType == `I_TYPE ? 1 : 0;
    assign memRead = opType == `LD_TYPE ? 1 : 0;
    assign memWrite = opType == `ST_TYPE ? 1 : 0;
    assign branch = opType == `CB_TYPE ? 1 : 0;
    assign unconditionalBranch = opType == `B_TYPE ? 1 : 0;

    assign aluOP = opType == `R_TYPE  ? 2 :
                   opType == `CB_TYPE ? 1 :
                   0;
    assign invertZeroFlag = opType == `CB_TYPE ? instruction[24] == 1 
                                                ? 1 :0
                                                :0;


    always @* begin

      if (instruction[26] == 1) begin
        if (instruction[29] == 1) begin opType <= `CB_TYPE; end
        else begin opType <= `B_TYPE;  end
      end
      else if (instruction[28] == 0) begin opType <= `R_TYPE; end
      else if (instruction[23] == 1) begin opType <= `M_TYPE; end
      else if (instruction[22] == 1) begin opType <= `LD_TYPE; end
      else if (instruction[27] == 1) begin opType <= `ST_TYPE; end
      else begin opType <= `I_TYPE; end



      readRegister1 <= instruction[9:5];
      if (reg2Loc == 0) begin readRegister2 <= instruction[20:16]; end
      else begin readRegister2 <= instruction[4:0]; end
      writeRegister <= instruction[4:0];


      if (opType == `LD_TYPE || opType == `ST_TYPE) begin aluControlCode <= 4'b0010; end
      else if (aluOP == 1) begin aluControlCode <= 4'b0111; end
      else if (opType == `M_TYPE) begin aluControlCode <= 4'b1101; end
      else if (aluOP == 2) begin
        if (instruction[24] == 1) begin
          if (instruction[30] == 0) begin aluControlCode <= 4'b0010; end
          else begin aluControlCode <= 4'b1010; end
        end
        else if (instruction[29] == 0) begin aluControlCode <= 4'b0110; end
        else if (instruction[30] == 0) begin aluControlCode <= 4'b0100; end
        else begin aluControlCode <= 4'b1001; end
      end
      else if (opType == `I_TYPE) begin
        if (instruction[29] == 1) begin aluControlCode <= 4'b0100; end
        else if (instruction[30] == 1) begin
          if (instruction[25] == 1) begin aluControlCode <= 4'b1001; end
          else begin aluControlCode <= 4'b1010; end
        end
        else if (instruction[25] == 1) begin aluControlCode <= 4'b0110; end
        else begin aluControlCode <=  4'b0010; end
      end
      else begin
        aluControlCode <= 0;
      end
    end

endmodule