data/full_repos/permissive/102515926/Modules/DIV.v
data/verilator_xmls/beeae784-af35-417c-94a6-cb55e97d80a6.xml
module DIV(a, b, quot);

    parameter DATAWIDTH = 2;

    input [DATAWIDTH - 1:0] a, b;
    output reg [DATAWIDTH - 1:0] quot;
    
    always @(*) begin
    
        quot <= a / b;
    
    end
    
endmodule
module DIV(a, b, quot);


    parameter DATAWIDTH = 2;

    input [DATAWIDTH - 1:0] a, b;
    output reg [DATAWIDTH - 1:0] quot;
    
    always @(*) begin
    
        quot <= a / b;
    
    end
    
endmodule