data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v
 line:126: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d6;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d7;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #4 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d19;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d14;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d15;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d8;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d9;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d8;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #2 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d8;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #2 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d8;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #2 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d8;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #2 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d8;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #2 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d8;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:116: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d8;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:117: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d8;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_ALU_result = 32\'d8;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:126: Unsupported: Ignoring delay on this delayed statement.\n        #2 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:129: Unsupported: Ignoring delay on this delayed statement.\n    always #1 i_clk = ~i_clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:131: Unsupported: Ignoring delay on this delayed statement.\n    always #2 i_PC_branch = o_PC_branch + 1;\n           ^\n%Error: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_memory_access.v:133: Cannot find file containing module: \'seg_memory_access\'\n    seg_memory_access \n    ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_memory_access\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_memory_access.v\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_memory_access.sv\n             seg_memory_access\n             seg_memory_access.v\n             seg_memory_access.sv\n             obj_dir/seg_memory_access\n             obj_dir/seg_memory_access.v\n             obj_dir/seg_memory_access.sv\n%Error: Exiting due to 1 error(s), 38 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_seg_memory_access();
    localparam LEN             = 32;
    localparam NB_ADDR         = 5;
    localparam NB_CTRL_WB      = 2;
    localparam NB_CTRL_M       = 9;

    localparam RAM_WIDTH_DATA          = 32;
    localparam RAM_DEPTH_DATA          = 21; 
    localparam RAM_PERFORMANCE_DATA    = "LOW_LATENCY";
    localparam INIT_FILE_DATA          = "C:\\Users\\astar\\git\\Arquitectura_de_Computadoras_2019\\TP4-MIPS-2019\\Test\\init_mem_memory_access.mem";



    reg                      i_clk;
    reg                      i_rst;
    reg  [LEN - 1 : 0]       i_PC_branch;
    reg  [LEN - 1 : 0]       i_ALU_result;
    reg  [LEN - 1 : 0]       i_write_data;
    reg  [NB_ADDR-1:0]       i_write_register;
    wire                     i_ALU_zero;

    reg  [NB_CTRL_WB-1:0]    i_ctrl_wb_bus;
    reg  [NB_CTRL_M-1:0]     i_ctrl_mem_bus;

    wire                     o_PCSrc;
    wire [LEN - 1 : 0]       o_PC_branch;
    wire [LEN - 1 : 0]       o_read_data;
    wire [LEN - 1 : 0]       o_address;
    wire [NB_ADDR-1:0]       o_write_register;

    wire [NB_CTRL_WB-1:0]    o_ctrl_wb_bus;

    assign i_ALU_zero = (i_ALU_result == 0) ? 1'b1 : 1'b0;

    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;
        i_PC_branch = {LEN{1'b0}};
        i_ALU_result = {LEN{1'b0}};
        i_write_data = {LEN{1'b0}};
        i_write_register = {NB_ADDR{1'b0}};
        i_ctrl_wb_bus = {NB_CTRL_WB{1'b0}};
        i_ctrl_mem_bus = {NB_CTRL_M{1'b0}};
        
        #4
        i_rst = 1'b1;
        i_write_register = 5'b10101;
        i_ctrl_wb_bus = 2'b11;

        i_ALU_result = 32'd1;
        i_write_data = 32'hF6F6F6F6;
        i_ctrl_mem_bus = 9'b000000001;

        #2 i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd5;
        #2 i_ALU_result = 32'd6;
        #2 i_ALU_result = 32'd7;
        #2 i_ALU_result = 32'd20;

        #4 

        i_ALU_result = 32'd0;
        i_ctrl_mem_bus = 9'b000000110;
        i_ctrl_wb_bus = 2'b11;
        
        #2 i_ALU_result = 32'd1;
        #2 i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd3;
        #2 i_ALU_result = 32'd19;
        #2 i_ALU_result = 32'd20;
        
        #4

        i_ALU_result = 32'd13;
        i_ctrl_mem_bus = 9'b000001011;
        i_write_data = 32'hA5DFA5DF;
        
        #2 i_ALU_result = 32'd14;
        #2 i_ALU_result = 32'd15;
        #2 i_ALU_result = 32'd8;
        #2 i_ALU_result = 32'd9;


        #10
        i_ctrl_mem_bus = 9'b001000010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2 
        i_ctrl_mem_bus = 9'b000100010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2 
        i_ctrl_mem_bus = 9'b000000010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2 
        i_ctrl_mem_bus = 9'b001010010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2 
        i_ctrl_mem_bus = 9'b000110010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2 
        i_ctrl_mem_bus = 9'b000000010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;


        #4
        i_write_data = 32'h53535353;
        i_ctrl_mem_bus = 9'b100000001;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2
        i_ctrl_mem_bus = 9'b010000001;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2
        i_ctrl_mem_bus = 9'b000000001;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        
        #2 $finish;
    end

    always #1 i_clk = ~i_clk;

    always #2 i_PC_branch = o_PC_branch + 1;

    seg_memory_access 
    #(
        .LEN                  (LEN                  ),
        .NB_ADDR              (NB_ADDR              ),
        .NB_CTRL_WB           (NB_CTRL_WB           ),
        .NB_CTRL_M            (NB_CTRL_M            ),
        .RAM_WIDTH_DATA       (RAM_WIDTH_DATA       ),
        .RAM_DEPTH_DATA       (RAM_DEPTH_DATA       ),
        .RAM_PERFORMANCE_DATA (RAM_PERFORMANCE_DATA ),
        .INIT_FILE_DATA       (INIT_FILE_DATA       )
    )
    u_seg_memory_access(
    	.i_clk            (i_clk            ),
        .i_rst            (i_rst            ),
        .i_PC_branch      (i_PC_branch      ),
        .i_ALU_result     (i_ALU_result     ),
        .i_write_data     (i_write_data     ),
        .i_write_register (i_write_register ),
        .i_ALU_zero       (i_ALU_zero       ),
        .i_ctrl_wb_bus    (i_ctrl_wb_bus    ),
        .i_ctrl_mem_bus   (i_ctrl_mem_bus   ),
        .o_PCSrc          (o_PCSrc          ),
        .o_PC_branch      (o_PC_branch      ),
        .o_read_data      (o_read_data      ),
        .o_address        (o_address        ),
        .o_write_register (o_write_register ),
        .o_ctrl_wb_bus    (o_ctrl_wb_bus    )
    );
    

endmodule
module tb_seg_memory_access();

    localparam LEN             = 32;
    localparam NB_ADDR         = 5;
    localparam NB_CTRL_WB      = 2;
    localparam NB_CTRL_M       = 9;

    localparam RAM_WIDTH_DATA          = 32;
    localparam RAM_DEPTH_DATA          = 21; 
    localparam RAM_PERFORMANCE_DATA    = "LOW_LATENCY";
    localparam INIT_FILE_DATA          = "C:\\Users\\astar\\git\\Arquitectura_de_Computadoras_2019\\TP4-MIPS-2019\\Test\\init_mem_memory_access.mem";



    reg                      i_clk;
    reg                      i_rst;
    reg  [LEN - 1 : 0]       i_PC_branch;
    reg  [LEN - 1 : 0]       i_ALU_result;
    reg  [LEN - 1 : 0]       i_write_data;
    reg  [NB_ADDR-1:0]       i_write_register;
    wire                     i_ALU_zero;

    reg  [NB_CTRL_WB-1:0]    i_ctrl_wb_bus;
    reg  [NB_CTRL_M-1:0]     i_ctrl_mem_bus;

    wire                     o_PCSrc;
    wire [LEN - 1 : 0]       o_PC_branch;
    wire [LEN - 1 : 0]       o_read_data;
    wire [LEN - 1 : 0]       o_address;
    wire [NB_ADDR-1:0]       o_write_register;

    wire [NB_CTRL_WB-1:0]    o_ctrl_wb_bus;

    assign i_ALU_zero = (i_ALU_result == 0) ? 1'b1 : 1'b0;

    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;
        i_PC_branch = {LEN{1'b0}};
        i_ALU_result = {LEN{1'b0}};
        i_write_data = {LEN{1'b0}};
        i_write_register = {NB_ADDR{1'b0}};
        i_ctrl_wb_bus = {NB_CTRL_WB{1'b0}};
        i_ctrl_mem_bus = {NB_CTRL_M{1'b0}};
        
        #4
        i_rst = 1'b1;
        i_write_register = 5'b10101;
        i_ctrl_wb_bus = 2'b11;

        i_ALU_result = 32'd1;
        i_write_data = 32'hF6F6F6F6;
        i_ctrl_mem_bus = 9'b000000001;

        #2 i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd5;
        #2 i_ALU_result = 32'd6;
        #2 i_ALU_result = 32'd7;
        #2 i_ALU_result = 32'd20;

        #4 

        i_ALU_result = 32'd0;
        i_ctrl_mem_bus = 9'b000000110;
        i_ctrl_wb_bus = 2'b11;
        
        #2 i_ALU_result = 32'd1;
        #2 i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd3;
        #2 i_ALU_result = 32'd19;
        #2 i_ALU_result = 32'd20;
        
        #4

        i_ALU_result = 32'd13;
        i_ctrl_mem_bus = 9'b000001011;
        i_write_data = 32'hA5DFA5DF;
        
        #2 i_ALU_result = 32'd14;
        #2 i_ALU_result = 32'd15;
        #2 i_ALU_result = 32'd8;
        #2 i_ALU_result = 32'd9;


        #10
        i_ctrl_mem_bus = 9'b001000010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2 
        i_ctrl_mem_bus = 9'b000100010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2 
        i_ctrl_mem_bus = 9'b000000010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2 
        i_ctrl_mem_bus = 9'b001010010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2 
        i_ctrl_mem_bus = 9'b000110010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2 
        i_ctrl_mem_bus = 9'b000000010;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;


        #4
        i_write_data = 32'h53535353;
        i_ctrl_mem_bus = 9'b100000001;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2
        i_ctrl_mem_bus = 9'b010000001;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        #2
        i_ctrl_mem_bus = 9'b000000001;
        i_ALU_result = 32'd2;
        #2 i_ALU_result = 32'd8;
        
        #2 $finish;
    end

    always #1 i_clk = ~i_clk;

    always #2 i_PC_branch = o_PC_branch + 1;

    seg_memory_access 
    #(
        .LEN                  (LEN                  ),
        .NB_ADDR              (NB_ADDR              ),
        .NB_CTRL_WB           (NB_CTRL_WB           ),
        .NB_CTRL_M            (NB_CTRL_M            ),
        .RAM_WIDTH_DATA       (RAM_WIDTH_DATA       ),
        .RAM_DEPTH_DATA       (RAM_DEPTH_DATA       ),
        .RAM_PERFORMANCE_DATA (RAM_PERFORMANCE_DATA ),
        .INIT_FILE_DATA       (INIT_FILE_DATA       )
    )
    u_seg_memory_access(
    	.i_clk            (i_clk            ),
        .i_rst            (i_rst            ),
        .i_PC_branch      (i_PC_branch      ),
        .i_ALU_result     (i_ALU_result     ),
        .i_write_data     (i_write_data     ),
        .i_write_register (i_write_register ),
        .i_ALU_zero       (i_ALU_zero       ),
        .i_ctrl_wb_bus    (i_ctrl_wb_bus    ),
        .i_ctrl_mem_bus   (i_ctrl_mem_bus   ),
        .o_PCSrc          (o_PCSrc          ),
        .o_PC_branch      (o_PC_branch      ),
        .o_read_data      (o_read_data      ),
        .o_address        (o_address        ),
        .o_write_register (o_write_register ),
        .o_ctrl_wb_bus    (o_ctrl_wb_bus    )
    );
    

endmodule