data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv
 line:7: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:61: Unsupported: Ignoring delay on this delayed statement.\nalways #10 i_hclk++;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:76: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("ahb_master.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:77: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:89: syntax error, unexpected \'@\'\n        repeat(10) @(posedge i_hclk);\n                   ^\n%Error: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:128: syntax error, unexpected \'@\'\n        repeat(10) @(posedge i_hclk);\n                   ^\n%Error: data/full_repos/permissive/100152754/ahb_master/bench/ahb_master_test.sv:143: syntax error, unexpected \'@\'\n        @(posedge i_hclk);\n        ^\n%Error: Exiting due to 5 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ahb_master_test;

parameter DATA_WDT = 32;
parameter BEAT_WDT = 32;


        bit                    i_hclk;
        bit                    i_hreset_n;


        logic [31:0]           o_haddr;
        logic [2:0]            o_hburst;
        logic [1:0]            o_htrans;
        logic[DATA_WDT-1:0]    o_hwdata;
        logic                  o_hwrite;
        logic [2:0]            o_hsize;
        logic [DATA_WDT-1:0]   i_hrdata;
        logic                  i_hready;
        logic [1:0]            i_hresp;
        logic                  i_hgrant;
        logic                  o_hbusreq;


        logic                 o_next;
        logic   [DATA_WDT-1:0]i_data;
        bit                   i_dav;
        bit      [31:0]       i_addr;
        bit      [2:0]        i_size;
        bit                   i_wr;
        bit                   i_rd;
        bit     [BEAT_WDT-1:0]i_min_len;
        bit                   i_cont;
        logic[DATA_WDT-1:0]   o_data;
        logic[31:0]           o_addr;
        logic                 o_dav;

logic [DATA_WDT-1:0] hwdata0, hwdata1;

assign hwdata0 = U_AHB_MASTER.o_hwdata[0];
assign hwdata1 = U_AHB_MASTER.o_hwdata[1];

ahb_master      #(.DATA_WDT(DATA_WDT), .BEAT_WDT(BEAT_WDT)) U_AHB_MASTER    (.*); 

ahb_slave_sim   #(.DATA_WDT(DATA_WDT))                      U_AHB_SLAVE_SIM_1 (

.i_hclk         (i_hclk),
.i_hreset_n     (i_hreset_n),
.i_hburst       (o_hburst),
.i_htrans       (o_htrans),
.i_hwdata       (o_hwdata),
.i_hsel         (1'd1),
.i_haddr        (o_haddr),
.i_hwrite       (o_hwrite),
.i_hready       (1'd1),
.o_hrdata       (i_hrdata),
.o_hready       (i_hready),
.o_hresp        (i_hresp)

);

always #10 i_hclk++;

always @ (posedge i_hclk)
begin
        if ( o_hbusreq )
                i_hgrant <= 1'd1;
        else
                i_hgrant <= 1'd0;
end

bit dav;
bit [31:0] dat;

initial
begin
        $dumpfile("ahb_master.vcd");
        $dumpvars;

        i_hgrant <= 1;

        i_hreset_n <= 1'd0;
        d(1);
        i_hreset_n <= 1'd1;


        i_rd <= 0;
        i_wr <= 0;

        repeat(10) @(posedge i_hclk);



        i_min_len <= 42;
        i_wr      <= 1'd1;
        i_cont    <= 1'd0;
        i_dav     <= 1'd1;
        i_data    <= 0;


        wait_for_next;       



        repeat(100)
        begin: bk
                dav = $random;
                dat = dat + dav;

                i_cont    <= 1'd1;
                i_dav     <= dav;


                i_data    <= dav ? dat : 
                `ifdef X_INJECTION
                        32'dx;
                `else
                        0;
                `endif

                wait_for_next;
        end


        i_rd   <= 1'd0;
        i_wr   <= 1'd0;
        i_cont <= 1'd0;

        repeat(10) @(posedge i_hclk);

        $finish;
end

task wait_for_next;
        d(1);
        while(o_next !== 1)
        begin
                d(1);
        end
endtask

task d(int x);
        repeat(x) 
        @(posedge i_hclk);
endtask

endmodule
module ahb_master_test;


parameter DATA_WDT = 32;
parameter BEAT_WDT = 32;


        bit                    i_hclk;
        bit                    i_hreset_n;


        logic [31:0]           o_haddr;
        logic [2:0]            o_hburst;
        logic [1:0]            o_htrans;
        logic[DATA_WDT-1:0]    o_hwdata;
        logic                  o_hwrite;
        logic [2:0]            o_hsize;
        logic [DATA_WDT-1:0]   i_hrdata;
        logic                  i_hready;
        logic [1:0]            i_hresp;
        logic                  i_hgrant;
        logic                  o_hbusreq;


        logic                 o_next;
        logic   [DATA_WDT-1:0]i_data;
        bit                   i_dav;
        bit      [31:0]       i_addr;
        bit      [2:0]        i_size;
        bit                   i_wr;
        bit                   i_rd;
        bit     [BEAT_WDT-1:0]i_min_len;
        bit                   i_cont;
        logic[DATA_WDT-1:0]   o_data;
        logic[31:0]           o_addr;
        logic                 o_dav;

logic [DATA_WDT-1:0] hwdata0, hwdata1;

assign hwdata0 = U_AHB_MASTER.o_hwdata[0];
assign hwdata1 = U_AHB_MASTER.o_hwdata[1];

ahb_master      #(.DATA_WDT(DATA_WDT), .BEAT_WDT(BEAT_WDT)) U_AHB_MASTER    (.*); 

ahb_slave_sim   #(.DATA_WDT(DATA_WDT))                      U_AHB_SLAVE_SIM_1 (

.i_hclk         (i_hclk),
.i_hreset_n     (i_hreset_n),
.i_hburst       (o_hburst),
.i_htrans       (o_htrans),
.i_hwdata       (o_hwdata),
.i_hsel         (1'd1),
.i_haddr        (o_haddr),
.i_hwrite       (o_hwrite),
.i_hready       (1'd1),
.o_hrdata       (i_hrdata),
.o_hready       (i_hready),
.o_hresp        (i_hresp)

);

always #10 i_hclk++;

always @ (posedge i_hclk)
begin
        if ( o_hbusreq )
                i_hgrant <= 1'd1;
        else
                i_hgrant <= 1'd0;
end

bit dav;
bit [31:0] dat;

initial
begin
        $dumpfile("ahb_master.vcd");
        $dumpvars;

        i_hgrant <= 1;

        i_hreset_n <= 1'd0;
        d(1);
        i_hreset_n <= 1'd1;


        i_rd <= 0;
        i_wr <= 0;

        repeat(10) @(posedge i_hclk);



        i_min_len <= 42;
        i_wr      <= 1'd1;
        i_cont    <= 1'd0;
        i_dav     <= 1'd1;
        i_data    <= 0;


        wait_for_next;       



        repeat(100)
        begin: bk
                dav = $random;
                dat = dat + dav;

                i_cont    <= 1'd1;
                i_dav     <= dav;


                i_data    <= dav ? dat : 
                `ifdef X_INJECTION
                        32'dx;
                `else
                        0;
                `endif

                wait_for_next;
        end


        i_rd   <= 1'd0;
        i_wr   <= 1'd0;
        i_cont <= 1'd0;

        repeat(10) @(posedge i_hclk);

        $finish;
end

task wait_for_next;
        d(1);
        while(o_next !== 1)
        begin
                d(1);
        end
endtask

task d(int x);
        repeat(x) 
        @(posedge i_hclk);
endtask

endmodule