data/full_repos/permissive/101171422/de2-115/ledsw/ledsw.v
data/verilator_xmls/b2e5f1df-eb54-440e-a880-fcf9fbd090e5.xml
module ledsw
(
    input  wire [17:0] sw,
    output reg  [17:0] ledr
);
	generate
		genvar i;
		for (i = 0; i <= 17; i=i+1)
		begin: loop
			always @* begin
				ledr[i] <= sw[i];
			end
		end
	endgenerate
	 
endmodule
module ledsw
(
    input  wire [17:0] sw,
    output reg  [17:0] ledr
);

	generate
		genvar i;
		for (i = 0; i <= 17; i=i+1)
		begin: loop
			always @* begin
				ledr[i] <= sw[i];
			end
		end
	endgenerate
	 
endmodule