data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new/ALU_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new/ALU_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new/ALU_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new/ALU_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new/ALU_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new/ALU_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new/ALU_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new/ALU_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new/ALU_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new/ALU_tb.v:33: Cannot find file containing module: \'ALU\'\n    ALU u0(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new,data/full_repos/permissive/194376374/ALU\n             data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new,data/full_repos/permissive/194376374/ALU.v\n             data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0303/lab0303.srcs/sim_1/new,data/full_repos/permissive/194376374/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_tb(

    );
    
    reg [31:0] input1;
    reg [31:0] input2;
    reg [3:0] aluCtr;
    wire [31:0] aluRes;
    wire zero;
    
    ALU u0(
        .input1(input1),
        .input2(input2),
        .aluCtr(aluCtr),
        .aluRes(aluRes),
        .zero(zero)
    );
    
    initial begin
    


    
    input1=15;
    input2=10; 
    

    aluCtr=4'b0000;
    #100;
    

    aluCtr=4'b0001;
    #100;
    

    aluCtr=4'b0010;
    #100;


    aluCtr=4'b0110;
    #100;
    

    aluCtr=4'b0111;
    #100;
    

    aluCtr=4'b1100;
    #100;
 
    input1=10;
    input2=10;     

    aluCtr=4'b0110;
    #100;
    

    aluCtr=4'b0010;
    #100;
        
    end
endmodule
module ALU_tb(

    );

    
    reg [31:0] input1;
    reg [31:0] input2;
    reg [3:0] aluCtr;
    wire [31:0] aluRes;
    wire zero;
    
    ALU u0(
        .input1(input1),
        .input2(input2),
        .aluCtr(aluCtr),
        .aluRes(aluRes),
        .zero(zero)
    );
    
    initial begin
    


    
    input1=15;
    input2=10; 
    

    aluCtr=4'b0000;
    #100;
    

    aluCtr=4'b0001;
    #100;
    

    aluCtr=4'b0010;
    #100;


    aluCtr=4'b0110;
    #100;
    

    aluCtr=4'b0111;
    #100;
    

    aluCtr=4'b1100;
    #100;
 
    input1=10;
    input2=10;     

    aluCtr=4'b0110;
    #100;
    

    aluCtr=4'b0010;
    #100;
        
    end
endmodule