data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v
 line:100: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n             ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n            ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n                ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n                                                                                              : ... In instance multicpu.alu\n   zero = ALUResult ? 0 : 1;\n                    ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu(
    input [31:0] AData, BData, immediate,
	input [4:0] sa,
	input [2:0] ALUOp,
	input ALUSrcA,ALUSrcB,
	output reg zero,
	output reg [31:0] ALUResult
    );
	initial 
		begin
			ALUResult=0;
			zero=1;
		end
	wire [31:0] A,B;
	assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;
	assign B=ALUSrcB ? immediate : BData;
	
	always@(ALUOp or AData or BData or A or B)
		begin
			case(ALUOp)
				3'b000 : ALUResult = A+B;
				3'b001 : ALUResult = A-B;
				3'b010 : ALUResult = (A<B)? 1:0;
				3'b011 : 
				begin
				        if(A<B&&((A[31]==0&&B[31]==0)||(A[31]==1&&B[31]==1))) ALUResult =1;
				        else if(A[31]==0&&B[31]==1) ALUResult=0;
				        else if (A[31]==1 &&B[31]==0) ALUResult=1;
				        else ALUResult=0;
				end
				3'b100 : ALUResult = B << A;
				3'b101 : ALUResult = A | B;
				3'b110 : ALUResult = A & B;
				3'b111 : ALUResult = (-A & B) | (A & -B);
				default : ALUResult = 0;
			endcase
			zero = ALUResult ? 0 : 1;
		end
endmodule
module alu(
    input [31:0] AData, BData, immediate,
	input [4:0] sa,
	input [2:0] ALUOp,
	input ALUSrcA,ALUSrcB,
	output reg zero,
	output reg [31:0] ALUResult
    );

	initial 
		begin
			ALUResult=0;
			zero=1;
		end
	wire [31:0] A,B;
	assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;
	assign B=ALUSrcB ? immediate : BData;
	
	always@(ALUOp or AData or BData or A or B)
		begin
			case(ALUOp)
				3'b000 : ALUResult = A+B;
				3'b001 : ALUResult = A-B;
				3'b010 : ALUResult = (A<B)? 1:0;
				3'b011 : 
				begin
				        if(A<B&&((A[31]==0&&B[31]==0)||(A[31]==1&&B[31]==1))) ALUResult =1;
				        else if(A[31]==0&&B[31]==1) ALUResult=0;
				        else if (A[31]==1 &&B[31]==0) ALUResult=1;
				        else ALUResult=0;
				end
				3'b100 : ALUResult = B << A;
				3'b101 : ALUResult = A | B;
				3'b110 : ALUResult = A & B;
				3'b111 : ALUResult = (-A & B) | (A & -B);
				default : ALUResult = 0;
			endcase
			zero = ALUResult ? 0 : 1;
		end
endmodule