data/full_repos/permissive/160794640/example/interface1.v
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data/verilator_xmls/6105db1a-e950-46e5-9c6b-787b6e764037.xml
module interface1 (input clk, input rst, output [31:0] test1);


   simple simon0(), simon1[1:0]();

   submodule x1(.conn(simon0));
   
   assign test1 = simon1[0].simple2 ^ simon1[1].simple2;
   
endmodule
module interface1 (input clk, input rst, output [31:0] test1);



   simple simon0(), simon1[1:0]();

   submodule x1(.conn(simon0));
   
   assign test1 = simon1[0].simple2 ^ simon1[1].simple2;
   
endmodule