data/full_repos/permissive/175958895/mips32_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/175958895/mips32_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/175958895/mips32_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n #15 clk2 = ~clk2;\n ^\n%Error: data/full_repos/permissive/175958895/mips32_testbench.v:11: Cannot find file containing module: \'mips32\'\nmips32 mp (instruction, clk, R);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175958895,data/full_repos/permissive/175958895/mips32\n             data/full_repos/permissive/175958895,data/full_repos/permissive/175958895/mips32.v\n             data/full_repos/permissive/175958895,data/full_repos/permissive/175958895/mips32.sv\n             mips32\n             mips32.v\n             mips32.sv\n             obj_dir/mips32\n             obj_dir/mips32.v\n             obj_dir/mips32.sv\n%Warning-WIDTH: data/full_repos/permissive/175958895/mips32_testbench.v:59: Bit extraction of array[10:0] requires 4 bit index, not 8 bits.\n                                                                          : ... In instance mips32_testbench\ninstruction<=testVectors[index];\n                        ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips32_testbench();

reg [31:0] instruction;
wire [31:0] R;

reg clk, clk2;
reg [7:0] index;
reg [31:0] testVectors[0:10];

mips32 mp (instruction, clk, R);



always begin
	#5 clk = ~clk;
end

always begin
	#15 clk2 = ~clk2;
end

initial 
begin
	clk = 1'b0;
	clk2 = 1'b0;	
	$readmemb("C:/altera/13.1/hcb_projects/RMIPS2/simulation/modelsim/inst.txt",testVectors);
	instruction = 32'd0; 
	index = -1;
end
























 
 
always @(posedge clk2)
begin
instruction<=testVectors[index];
end
 
always @(negedge clk2)
begin
	$display("opcode = %6b, rs = %5b, rt = %5b, rd = %5b, shamt = %5b, funct = %6b, result = %32b", 
	instruction[31:26], instruction[25:21], instruction[20:16], instruction[15:11], instruction[10:6], instruction[5:0], R);
	index = index + 1;
	if (index == 8'd10)
	begin
		$finish;
	end
end	
 
endmodule
module mips32_testbench();


reg [31:0] instruction;
wire [31:0] R;

reg clk, clk2;
reg [7:0] index;
reg [31:0] testVectors[0:10];

mips32 mp (instruction, clk, R);



always begin
	#5 clk = ~clk;
end

always begin
	#15 clk2 = ~clk2;
end

initial 
begin
	clk = 1'b0;
	clk2 = 1'b0;	
	$readmemb("C:/altera/13.1/hcb_projects/RMIPS2/simulation/modelsim/inst.txt",testVectors);
	instruction = 32'd0; 
	index = -1;
end
























 
 
always @(posedge clk2)
begin
instruction<=testVectors[index];
end
 
always @(negedge clk2)
begin
	$display("opcode = %6b, rs = %5b, rt = %5b, rd = %5b, shamt = %5b, funct = %6b, result = %32b", 
	instruction[31:26], instruction[25:21], instruction[20:16], instruction[15:11], instruction[10:6], instruction[5:0], R);
	index = index + 1;
	if (index == 8'd10)
	begin
		$finish;
	end
end	
 
endmodule