data/full_repos/permissive/138443719/08-counter/src/main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/138443719/08-counter/src/main.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/138443719/08-counter/src/main.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/138443719/08-counter/src/main.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: data/full_repos/permissive/138443719/08-counter/src/main.v:35: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile(dumpfile_path);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/138443719/08-counter/src/main.v:36: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,hello_world);\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hello_world;


  wire clk;
  clock_gen clk_gen(clk);
  reg reset = 0;

  wire[3:0] count;
  counter #(.WIDTH(4)) my_counter (count, clk, reset);

  initial begin

    #1
    reset = 1;
    #1
    reset = 0;
    #10;
    $finish;

  end








  reg dummy;
  reg[8*64:0] dumpfile_path = "output.vcd";

  initial begin
    dummy = $value$plusargs("VCD_PATH=%s", dumpfile_path);
    $dumpfile(dumpfile_path);
    $dumpvars(0,hello_world);
  end

endmodule
module hello_world;



  wire clk;
  clock_gen clk_gen(clk);
  reg reset = 0;

  wire[3:0] count;
  counter #(.WIDTH(4)) my_counter (count, clk, reset);

  initial begin

    #1
    reset = 1;
    #1
    reset = 0;
    #10;
    $finish;

  end








  reg dummy;
  reg[8*64:0] dumpfile_path = "output.vcd";

  initial begin
    dummy = $value$plusargs("VCD_PATH=%s", dumpfile_path);
    $dumpfile(dumpfile_path);
    $dumpvars(0,hello_world);
  end

endmodule