data/full_repos/permissive/118303050/src/lab_4/controller.v
1: b"%Error: data/full_repos/permissive/118303050/src/lab_4/controller.v:52: Cannot find file containing module: 'maindec'\n maindec md(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/118303050/src/lab_4,data/full_repos/permissive/118303050/maindec\n             data/full_repos/permissive/118303050/src/lab_4,data/full_repos/permissive/118303050/maindec.v\n             data/full_repos/permissive/118303050/src/lab_4,data/full_repos/permissive/118303050/maindec.sv\n             maindec\n             maindec.v\n             maindec.sv\n             obj_dir/maindec\n             obj_dir/maindec.v\n             obj_dir/maindec.sv\n%Error: data/full_repos/permissive/118303050/src/lab_4/controller.v:60: Cannot find file containing module: 'aludec'\n aludec ad(functD,aluopD,alucontrolD);\n ^~~~~~\n%Error: data/full_repos/permissive/118303050/src/lab_4/controller.v:65: Cannot find file containing module: 'floprc'\n floprc #(8) regE(\n ^~~~~~\n%Error: data/full_repos/permissive/118303050/src/lab_4/controller.v:72: Cannot find file containing module: 'flopr'\n flopr #(8) regM(\n ^~~~~\n%Error: data/full_repos/permissive/118303050/src/lab_4/controller.v:77: Cannot find file containing module: 'flopr'\n flopr #(8) regW(\n ^~~~~\n%Error: Exiting due to 5 error(s)\n"
module controller(
	input wire clk,rst,

	input wire[5:0] opD,functD,
	output wire pcsrcD,branchD,equalD,jumpD,
	

	input wire flushE,
	output wire memtoregE,alusrcE,
	output wire regdstE,regwriteE,	
	output wire[2:0] alucontrolE,


	output wire memtoregM,memwriteM,
				regwriteM,

	output wire memtoregW,regwriteW

    );
	

	wire[1:0] aluopD;
	wire memtoregD,memwriteD,alusrcD,
		regdstD,regwriteD;
	wire[2:0] alucontrolD;


	wire memwriteE;

	maindec md(
		opD,
		memtoregD,memwriteD,
		branchD,alusrcD,
		regdstD,regwriteD,
		jumpD,
		aluopD
		);
	aludec ad(functD,aluopD,alucontrolD);

	assign pcsrcD = branchD & equalD;


	floprc #(8) regE(
		clk,
		rst,
		flushE,
		{memtoregD,memwriteD,alusrcD,regdstD,regwriteD,alucontrolD},
		{memtoregE,memwriteE,alusrcE,regdstE,regwriteE,alucontrolE}
		);
	flopr #(8) regM(
		clk,rst,
		{memtoregE,memwriteE,regwriteE},
		{memtoregM,memwriteM,regwriteM}
		);
	flopr #(8) regW(
		clk,rst,
		{memtoregM,regwriteM},
		{memtoregW,regwriteW}
		);
endmodule
module controller(
	input wire clk,rst,

	input wire[5:0] opD,functD,
	output wire pcsrcD,branchD,equalD,jumpD,
	

	input wire flushE,
	output wire memtoregE,alusrcE,
	output wire regdstE,regwriteE,	
	output wire[2:0] alucontrolE,


	output wire memtoregM,memwriteM,
				regwriteM,

	output wire memtoregW,regwriteW

    );

	

	wire[1:0] aluopD;
	wire memtoregD,memwriteD,alusrcD,
		regdstD,regwriteD;
	wire[2:0] alucontrolD;


	wire memwriteE;

	maindec md(
		opD,
		memtoregD,memwriteD,
		branchD,alusrcD,
		regdstD,regwriteD,
		jumpD,
		aluopD
		);
	aludec ad(functD,aluopD,alucontrolD);

	assign pcsrcD = branchD & equalD;


	floprc #(8) regE(
		clk,
		rst,
		flushE,
		{memtoregD,memwriteD,alusrcD,regdstD,regwriteD,alucontrolD},
		{memtoregE,memwriteE,alusrcE,regdstE,regwriteE,alucontrolE}
		);
	flopr #(8) regM(
		clk,rst,
		{memtoregE,memwriteE,regwriteE},
		{memtoregM,memwriteM,regwriteM}
		);
	flopr #(8) regW(
		clk,rst,
		{memtoregM,regwriteM},
		{memtoregW,regwriteW}
		);
endmodule