data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/tb.v:2: Cannot find include file: vga_config.inc\n`include "vga_config.inc" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic,data/full_repos/permissive/130996185/vga_config.inc\n             data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic,data/full_repos/permissive/130996185/vga_config.inc.v\n             data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic,data/full_repos/permissive/130996185/vga_config.inc.sv\n             vga_config.inc\n             vga_config.inc.v\n             vga_config.inc.sv\n             obj_dir/vga_config.inc\n             obj_dir/vga_config.inc.v\n             obj_dir/vga_config.inc.sv\n%Warning-STMTDLY: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/tb.v:6: Unsupported: Ignoring delay on this delayed statement.\n always #10 FPGA_CLK1_50 <= ~FPGA_CLK1_50;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/tb.v:7: Unsupported: Ignoring delay on this delayed statement.\n always #10 FPGA_CLK2_50 <= ~FPGA_CLK2_50;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n always #10 FPGA_CLK3_50 <= ~FPGA_CLK3_50;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #0  KEY = 2\'B10; FPGA_CLK1_50 = 0; FPGA_CLK2_50 = 0; FPGA_CLK3_50 = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #1000 KEY = 2\'B11;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #200000 KEY = 2\'B11;  \n  ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module tb;
	
	reg			FPGA_CLK1_50, FPGA_CLK2_50, FPGA_CLK3_50;
	always #10	FPGA_CLK1_50 <= ~FPGA_CLK1_50;
	always #10	FPGA_CLK2_50 <= ~FPGA_CLK2_50;
	always #10	FPGA_CLK3_50 <= ~FPGA_CLK3_50;
	
	reg			[1:0]	KEY;


	ghrd				ghrd_inst(
							.FPGA_CLK1_50(FPGA_CLK1_50),
							.FPGA_CLK2_50(FPGA_CLK2_50),
							.FPGA_CLK3_50(FPGA_CLK3_50),
							.KEY(KEY)
						);
	
	initial
	begin
	
		#0		KEY = 2'B10; FPGA_CLK1_50 = 0; FPGA_CLK2_50 = 0; FPGA_CLK3_50 = 0;
		#1000	KEY = 2'B11;
		#200000	KEY = 2'B11;
		

		
	end
	

endmodule
module tb;

	
	reg			FPGA_CLK1_50, FPGA_CLK2_50, FPGA_CLK3_50;
	always #10	FPGA_CLK1_50 <= ~FPGA_CLK1_50;
	always #10	FPGA_CLK2_50 <= ~FPGA_CLK2_50;
	always #10	FPGA_CLK3_50 <= ~FPGA_CLK3_50;
	
	reg			[1:0]	KEY;


	ghrd				ghrd_inst(
							.FPGA_CLK1_50(FPGA_CLK1_50),
							.FPGA_CLK2_50(FPGA_CLK2_50),
							.FPGA_CLK3_50(FPGA_CLK3_50),
							.KEY(KEY)
						);
	
	initial
	begin
	
		#0		KEY = 2'B10; FPGA_CLK1_50 = 0; FPGA_CLK2_50 = 0; FPGA_CLK3_50 = 0;
		#1000	KEY = 2'B11;
		#200000	KEY = 2'B11;
		

		
	end
	

endmodule