data/full_repos/permissive/187712539/modules/programCounter.v
data/verilator_xmls/5d6b65c3-f19b-4919-9578-f2558a100c3a.xml
module programCounter(clk,in_address,out_address,rst);
input clk, rst;
input [31:0] in_address;
output [31:0] out_address;

reg [31:0] reg_address;

always @(posedge clk)
begin
	if(rst)
		reg_address = 32'h00000000;
	else
		reg_address = in_address;
	

end

assign out_address = reg_address;

endmodule
module programCounter(clk,in_address,out_address,rst);

input clk, rst;
input [31:0] in_address;
output [31:0] out_address;

reg [31:0] reg_address;

always @(posedge clk)
begin
	if(rst)
		reg_address = 32'h00000000;
	else
		reg_address = in_address;
	

end

assign out_address = reg_address;

endmodule