data/full_repos/permissive/131921633/tv/Util/Delay/single.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Util/Delay/single.v:1: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Util/Delay,data/full_repos/permissive/131921633/Data/Control/Control.v\n             data/full_repos/permissive/131921633/tv/Util/Delay,data/full_repos/permissive/131921633/Data/Control/Control.v.v\n             data/full_repos/permissive/131921633/tv/Util/Delay,data/full_repos/permissive/131921633/Data/Control/Control.v.sv\n             Data/Control/Control.v\n             Data/Control/Control.v.v\n             Data/Control/Control.v.sv\n             obj_dir/Data/Control/Control.v\n             obj_dir/Data/Control/Control.v.v\n             obj_dir/Data/Control/Control.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Util/Delay/single.v:7: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T(input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Delay/single.v:7: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Control_Control_T(input) ctrl\n                           ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Delay/single.v:18: syntax error, unexpected always\n  always @(posedge `Data_Control_Control_Clock(ctrl))\n  ^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Delay/single.v:18: Define or directive not defined: \'`Data_Control_Control_Clock\'\n  always @(posedge `Data_Control_Control_Clock(ctrl))\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Delay/single.v:19: Define or directive not defined: \'`Data_Control_Control_Reset\'\n   if(!`Data_Control_Control_Reset(ctrl)) begin\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module Util_Delay_single #
	( parameter DELAY = 0
	, parameter RESET = 1'b0
	)
	( `Data_Control_Control_T(input) ctrl
	, input  in
	, output out
	);

generate
	if(DELAY <= 0)
		assign out = in;
	else begin
		reg q[DELAY-1:0];
		integer i;
		always @(posedge `Data_Control_Control_Clock(ctrl))
			if(!`Data_Control_Control_Reset(ctrl)) begin
				q[0] <= in;
				for(i = 1; i < DELAY; i = i + 1)
					q[i] <= q[i-1];
			end else
				for(i = 0; i < DELAY; i = i + 1)
					q[i] <= RESET;
		assign out = q[DELAY-1];
	end
endgenerate

endmodule
module Util_Delay_single #
	( parameter DELAY = 0
	, parameter RESET = 1'b0
	)
	( `Data_Control_Control_T(input) ctrl
	, input  in
	, output out
	);


generate
	if(DELAY <= 0)
		assign out = in;
	else begin
		reg q[DELAY-1:0];
		integer i;
		always @(posedge `Data_Control_Control_Clock(ctrl))
			if(!`Data_Control_Control_Reset(ctrl)) begin
				q[0] <= in;
				for(i = 1; i < DELAY; i = i + 1)
					q[i] <= q[i-1];
			end else
				for(i = 0; i < DELAY; i = i + 1)
					q[i] <= RESET;
		assign out = q[DELAY-1];
	end
endgenerate

endmodule