data/full_repos/permissive/192010622/src/blinky.v
data/verilator_xmls/4df80f00-6c82-4c70-99f5-7a8e8c2adcea.xml
module fpga_top(input wire clk, output reg WF_LED);
    reg [24:0] counter;


    always @ (posedge clk) begin


        if (counter == 8000000) begin
            WF_LED   <= ~WF_LED;
            counter  <= 'b0;
        end else begin
            counter  <= counter + 'b1;
        end
    end













endmodule
module fpga_top(input wire clk, output reg WF_LED);

    reg [24:0] counter;


    always @ (posedge clk) begin


        if (counter == 8000000) begin
            WF_LED   <= ~WF_LED;
            counter  <= 'b0;
        end else begin
            counter  <= counter + 'b1;
        end
    end













endmodule