data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/verilog_utils/verilog_utils.vh
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/aabd5c03-4a88-447b-b789-4cd0c249383c.xml
function integer clog2;
input integer in;
begin
	in = in - 1;
	for (clog2 = 0; in > 0; clog2=clog2+1)
		in = in >> 1;
end
endfunction
function integer clog2;

input integer in;
begin
	in = in - 1;
	for (clog2 = 0; in > 0; clog2=clog2+1)
		in = in >> 1;
end
endfunction