data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v
1: b'%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:1: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:11: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   rs1_1tag,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:12: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   rs2_1tag,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:13: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   rs1_2tag,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:14: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   rs2_2tag,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:15: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   com1tag,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:16: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   com2tag,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:21: Define or directive not defined: \'`DATA_LEN\'\n    output wire [`DATA_LEN-1:0] rs1_1data,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:22: Define or directive not defined: \'`DATA_LEN\'\n    output wire [`DATA_LEN-1:0] rs2_1data,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:23: Define or directive not defined: \'`DATA_LEN\'\n    output wire [`DATA_LEN-1:0] rs1_2data,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:24: Define or directive not defined: \'`DATA_LEN\'\n    output wire [`DATA_LEN-1:0] rs2_2data,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:25: Define or directive not defined: \'`DATA_LEN\'\n    output wire [`DATA_LEN-1:0] com1data,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:26: Define or directive not defined: \'`DATA_LEN\'\n    output wire [`DATA_LEN-1:0] com2data,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:27: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   wrrfaddr1,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:28: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   wrrfaddr2,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:29: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   wrrfaddr3,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:30: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   wrrfaddr4,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:31: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   wrrfaddr5,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:32: Define or directive not defined: \'`DATA_LEN\'\n    input wire [`DATA_LEN-1:0]  wrrfdata1,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:33: Define or directive not defined: \'`DATA_LEN\'\n    input wire [`DATA_LEN-1:0]  wrrfdata2,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:34: Define or directive not defined: \'`DATA_LEN\'\n    input wire [`DATA_LEN-1:0]  wrrfdata3,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:35: Define or directive not defined: \'`DATA_LEN\'\n    input wire [`DATA_LEN-1:0]  wrrfdata4,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:36: Define or directive not defined: \'`DATA_LEN\'\n    input wire [`DATA_LEN-1:0]  wrrfdata5,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:42: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   dpaddr1,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:43: Define or directive not defined: \'`RRF_SEL\'\n    input wire [`RRF_SEL-1:0]   dpaddr2,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:48: Define or directive not defined: \'`RRF_NUM\'\n   reg [`RRF_NUM-1:0]          valid;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:49: Define or directive not defined: \'`DATA_LEN\'\n   reg [`DATA_LEN-1:0]          datarr [0:`RRF_NUM-1];\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:49: Define or directive not defined: \'`RRF_NUM\'\n   reg [`DATA_LEN-1:0]          datarr [0:`RRF_NUM-1];\n                                          ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:63: Define or directive not defined: \'`RRF_NUM\'\n   wire [`RRF_NUM-1:0]          or_valid = \n         ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:64: Define or directive not defined: \'`RRF_NUM\'\n           (~wrrfen1 ? `RRF_NUM\'b0 : \n                       ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:65: Define or directive not defined: \'`RRF_NUM\'\n     (`RRF_NUM\'b1 << wrrfaddr1)) |\n      ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:66: Define or directive not defined: \'`RRF_NUM\'\n           (~wrrfen2 ? `RRF_NUM\'b0 : \n                       ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:67: Define or directive not defined: \'`RRF_NUM\'\n     (`RRF_NUM\'b1 << wrrfaddr2)) |\n      ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:68: Define or directive not defined: \'`RRF_NUM\'\n            (~wrrfen3 ? `RRF_NUM\'b0 : \n                        ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:69: Define or directive not defined: \'`RRF_NUM\'\n     (`RRF_NUM\'b1 << wrrfaddr3)) |\n      ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:70: Define or directive not defined: \'`RRF_NUM\'\n           (~wrrfen4 ? `RRF_NUM\'b0 : \n                       ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:71: Define or directive not defined: \'`RRF_NUM\'\n     (`RRF_NUM\'b1 << wrrfaddr4)) |\n      ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:72: Define or directive not defined: \'`RRF_NUM\'\n           (~wrrfen5 ? `RRF_NUM\'b0 : \n                       ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:73: Define or directive not defined: \'`RRF_NUM\'\n     (`RRF_NUM\'b1 << wrrfaddr5));\n      ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:75: Define or directive not defined: \'`RRF_NUM\'\n   wire [`RRF_NUM-1:0]          and_valid = \n         ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:76: Define or directive not defined: \'`RRF_NUM\'\n           (~dpen1 ? ~(`RRF_NUM\'b0) : \n                       ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:77: Define or directive not defined: \'`RRF_NUM\'\n     ~(`RRF_NUM\'b1 << dpaddr1)) & \n       ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:78: Define or directive not defined: \'`RRF_NUM\'\n           (~dpen2 ? ~(`RRF_NUM\'b0) : \n                       ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rrf.v:79: Define or directive not defined: \'`RRF_NUM\'\n     ~(`RRF_NUM\'b1 << dpaddr2));\n       ^~~~~~~~\n%Error: Exiting due to 44 error(s)\n'
module rrf(
	   input wire 		       clk,
	   input wire 		       reset,
	   input wire [`RRF_SEL-1:0]   rs1_1tag,
	   input wire [`RRF_SEL-1:0]   rs2_1tag,
	   input wire [`RRF_SEL-1:0]   rs1_2tag,
	   input wire [`RRF_SEL-1:0]   rs2_2tag,
	   input wire [`RRF_SEL-1:0]   com1tag,
	   input wire [`RRF_SEL-1:0]   com2tag,
	   output wire 		       rs1_1valid,
	   output wire 		       rs2_1valid,
	   output wire 		       rs1_2valid,
	   output wire 		       rs2_2valid,
	   output wire [`DATA_LEN-1:0] rs1_1data,
	   output wire [`DATA_LEN-1:0] rs2_1data,
	   output wire [`DATA_LEN-1:0] rs1_2data,
	   output wire [`DATA_LEN-1:0] rs2_2data,
	   output wire [`DATA_LEN-1:0] com1data,
	   output wire [`DATA_LEN-1:0] com2data,
	   input wire [`RRF_SEL-1:0]   wrrfaddr1,
	   input wire [`RRF_SEL-1:0]   wrrfaddr2,
	   input wire [`RRF_SEL-1:0]   wrrfaddr3,
	   input wire [`RRF_SEL-1:0]   wrrfaddr4,
	   input wire [`RRF_SEL-1:0]   wrrfaddr5,
	   input wire [`DATA_LEN-1:0]  wrrfdata1,
	   input wire [`DATA_LEN-1:0]  wrrfdata2,
	   input wire [`DATA_LEN-1:0]  wrrfdata3,
	   input wire [`DATA_LEN-1:0]  wrrfdata4,
	   input wire [`DATA_LEN-1:0]  wrrfdata5,
	   input wire 		       wrrfen1,
	   input wire 		       wrrfen2,
	   input wire 		       wrrfen3,
	   input wire 		       wrrfen4,
	   input wire 		       wrrfen5,
	   input wire [`RRF_SEL-1:0]   dpaddr1,
	   input wire [`RRF_SEL-1:0]   dpaddr2,
	   input wire 		       dpen1,
	   input wire 		       dpen2
	   );

   reg [`RRF_NUM-1:0] 		       valid;
   reg [`DATA_LEN-1:0] 		       datarr [0:`RRF_NUM-1];

   assign rs1_1data = datarr[rs1_1tag];
   assign rs2_1data = datarr[rs2_1tag];
   assign rs1_2data = datarr[rs1_2tag];
   assign rs2_2data = datarr[rs2_2tag];
   assign com1data = datarr[com1tag];
   assign com2data = datarr[com2tag];

   assign rs1_1valid = valid[rs1_1tag];
   assign rs2_1valid = valid[rs2_1tag];
   assign rs1_2valid = valid[rs1_2tag];
   assign rs2_2valid = valid[rs2_2tag];

   wire [`RRF_NUM-1:0] 		       or_valid = 
				       (~wrrfen1 ? `RRF_NUM'b0 : 
					(`RRF_NUM'b1 << wrrfaddr1)) |
				       (~wrrfen2 ? `RRF_NUM'b0 : 
					(`RRF_NUM'b1 << wrrfaddr2)) |
 				       (~wrrfen3 ? `RRF_NUM'b0 : 
					(`RRF_NUM'b1 << wrrfaddr3)) |
				       (~wrrfen4 ? `RRF_NUM'b0 : 
					(`RRF_NUM'b1 << wrrfaddr4)) |
				       (~wrrfen5 ? `RRF_NUM'b0 : 
					(`RRF_NUM'b1 << wrrfaddr5));
   
   wire [`RRF_NUM-1:0] 		       and_valid = 
				       (~dpen1 ? ~(`RRF_NUM'b0) : 
					~(`RRF_NUM'b1 << dpaddr1)) & 
				       (~dpen2 ? ~(`RRF_NUM'b0) : 
					~(`RRF_NUM'b1 << dpaddr2));

   always @ (posedge clk) begin
      if (reset) begin
	 valid <= 0;
      end else begin
	 valid <= (valid | or_valid) & and_valid;
      end
   end

   always @ (posedge clk) begin
      if (~reset) begin
	 if (wrrfen1)
	   datarr[wrrfaddr1] <= wrrfdata1;
	 if (wrrfen2)
	   datarr[wrrfaddr2] <= wrrfdata2;
	 if (wrrfen3)
	   datarr[wrrfaddr3] <= wrrfdata3;
	 if (wrrfen4)
	   datarr[wrrfaddr4] <= wrrfdata4;
	 if (wrrfen5)
	   datarr[wrrfaddr5] <= wrrfdata5;
      end
   end
endmodule
module rrf(
	   input wire 		       clk,
	   input wire 		       reset,
	   input wire [`RRF_SEL-1:0]   rs1_1tag,
	   input wire [`RRF_SEL-1:0]   rs2_1tag,
	   input wire [`RRF_SEL-1:0]   rs1_2tag,
	   input wire [`RRF_SEL-1:0]   rs2_2tag,
	   input wire [`RRF_SEL-1:0]   com1tag,
	   input wire [`RRF_SEL-1:0]   com2tag,
	   output wire 		       rs1_1valid,
	   output wire 		       rs2_1valid,
	   output wire 		       rs1_2valid,
	   output wire 		       rs2_2valid,
	   output wire [`DATA_LEN-1:0] rs1_1data,
	   output wire [`DATA_LEN-1:0] rs2_1data,
	   output wire [`DATA_LEN-1:0] rs1_2data,
	   output wire [`DATA_LEN-1:0] rs2_2data,
	   output wire [`DATA_LEN-1:0] com1data,
	   output wire [`DATA_LEN-1:0] com2data,
	   input wire [`RRF_SEL-1:0]   wrrfaddr1,
	   input wire [`RRF_SEL-1:0]   wrrfaddr2,
	   input wire [`RRF_SEL-1:0]   wrrfaddr3,
	   input wire [`RRF_SEL-1:0]   wrrfaddr4,
	   input wire [`RRF_SEL-1:0]   wrrfaddr5,
	   input wire [`DATA_LEN-1:0]  wrrfdata1,
	   input wire [`DATA_LEN-1:0]  wrrfdata2,
	   input wire [`DATA_LEN-1:0]  wrrfdata3,
	   input wire [`DATA_LEN-1:0]  wrrfdata4,
	   input wire [`DATA_LEN-1:0]  wrrfdata5,
	   input wire 		       wrrfen1,
	   input wire 		       wrrfen2,
	   input wire 		       wrrfen3,
	   input wire 		       wrrfen4,
	   input wire 		       wrrfen5,
	   input wire [`RRF_SEL-1:0]   dpaddr1,
	   input wire [`RRF_SEL-1:0]   dpaddr2,
	   input wire 		       dpen1,
	   input wire 		       dpen2
	   );


   reg [`RRF_NUM-1:0] 		       valid;
   reg [`DATA_LEN-1:0] 		       datarr [0:`RRF_NUM-1];

   assign rs1_1data = datarr[rs1_1tag];
   assign rs2_1data = datarr[rs2_1tag];
   assign rs1_2data = datarr[rs1_2tag];
   assign rs2_2data = datarr[rs2_2tag];
   assign com1data = datarr[com1tag];
   assign com2data = datarr[com2tag];

   assign rs1_1valid = valid[rs1_1tag];
   assign rs2_1valid = valid[rs2_1tag];
   assign rs1_2valid = valid[rs1_2tag];
   assign rs2_2valid = valid[rs2_2tag];

   wire [`RRF_NUM-1:0] 		       or_valid = 
				       (~wrrfen1 ? `RRF_NUM'b0 : 
					(`RRF_NUM'b1 << wrrfaddr1)) |
				       (~wrrfen2 ? `RRF_NUM'b0 : 
					(`RRF_NUM'b1 << wrrfaddr2)) |
 				       (~wrrfen3 ? `RRF_NUM'b0 : 
					(`RRF_NUM'b1 << wrrfaddr3)) |
				       (~wrrfen4 ? `RRF_NUM'b0 : 
					(`RRF_NUM'b1 << wrrfaddr4)) |
				       (~wrrfen5 ? `RRF_NUM'b0 : 
					(`RRF_NUM'b1 << wrrfaddr5));
   
   wire [`RRF_NUM-1:0] 		       and_valid = 
				       (~dpen1 ? ~(`RRF_NUM'b0) : 
					~(`RRF_NUM'b1 << dpaddr1)) & 
				       (~dpen2 ? ~(`RRF_NUM'b0) : 
					~(`RRF_NUM'b1 << dpaddr2));

   always @ (posedge clk) begin
      if (reset) begin
	 valid <= 0;
      end else begin
	 valid <= (valid | or_valid) & and_valid;
      end
   end

   always @ (posedge clk) begin
      if (~reset) begin
	 if (wrrfen1)
	   datarr[wrrfaddr1] <= wrrfdata1;
	 if (wrrfen2)
	   datarr[wrrfaddr2] <= wrrfdata2;
	 if (wrrfen3)
	   datarr[wrrfaddr3] <= wrrfdata3;
	 if (wrrfen4)
	   datarr[wrrfaddr4] <= wrrfdata4;
	 if (wrrfen5)
	   datarr[wrrfaddr5] <= wrrfdata5;
      end
   end
endmodule