data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_xilinx_internal_jtag.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_xilinx_internal_jtag.v:73: Cannot find include file: minsoc_defines.v\n`include "minsoc_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/minsoc_defines.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/minsoc_defines.v.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/minsoc_defines.v.sv\n             minsoc_defines.v\n             minsoc_defines.v.v\n             minsoc_defines.v.sv\n             obj_dir/minsoc_defines.v\n             obj_dir/minsoc_defines.v.v\n             obj_dir/minsoc_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module minsoc_xilinx_internal_jtag (
	tck_o,
	debug_tdo_i,
	tdi_o,
	test_logic_reset_o,
	run_test_idle_o,
	shift_dr_o,
	capture_dr_o,
	pause_dr_o,
	update_dr_o,
	debug_select_o
);



parameter virtex_jtag_chain = 1;

input debug_tdo_i;
output tck_o;
output tdi_o;
output test_logic_reset_o;
output run_test_idle_o;
output shift_dr_o;
output capture_dr_o;
output pause_dr_o;
output update_dr_o;
output debug_select_o;

wire debug_tdo_i;
wire tck_o;
wire drck;
wire tdi_o;
wire test_logic_reset_o;
wire run_test_idle_o;
wire shift_dr_o;
wire pause_dr_o;
wire update_dr_o;
wire debug_select_o;

`ifdef SPARTAN3E
	`define SPARTAN3
`endif

`ifdef SPARTAN2






reg capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst (
.DRCK1(drck),
.DRCK2(),
.RESET(test_logic_reset_o),
.SEL1(debug_select_o),
.SEL2(),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO1(debug_tdo_i),
.TDO2( 1'b0 )
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




always @ (negedge tck_o)
begin
	if(debug_select_o && !shift_dr_o)
		capture_dr_o <= 1'b1;
	else
		capture_dr_o <= 1'b0;
end




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;

`else
`ifdef SPARTAN3



wire capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
.CAPTURE(capture_dr_o),
.DRCK1(drck),
.DRCK2(),
.RESET(test_logic_reset_o),
.SEL1(debug_select_o),
.SEL2(),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO1(debug_tdo_i),
.TDO2(1'b0)
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;

`ifdef SPARTAN3E
	`undef SPARTAN3
`endif

`else
`ifdef SPARTAN3A



wire capture_dr_o;

BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst (
.CAPTURE(capture_dr_o),
.DRCK1(),
.DRCK2(),
.RESET(test_logic_reset_o),
.SEL1(debug_select_o),
.SEL2(),
.SHIFT(shift_dr_o),
.TCK(tck_o),
.TDI(tdi_o),
.TMS(),
.UPDATE(update_dr_o),
.TDO1(debug_tdo_i),
.TDO2( 1'b0)
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;

`else
 `ifdef SPARTAN6
    wire capture_dr_o;
    BSCAN_SPARTAN6 #(
    .JTAG_CHAIN(1)
)
BSCAN_SPARTAN6_inst (
.CAPTURE(capture_dr_o),
.DRCK(drck),
.RESET(test_logic_reset_o),
.RUNTEST(),
.SEL(debug_select_o),
.SHIFT(shift_dr_o),
.TCK(tck_o),
.TDI(tdi_o),
.TMS(),
.UPDATE(update_dr_o),
.TDO(debug_tdo_i)
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
    
`else
`ifdef VIRTEX




reg capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_VIRTEX BSCAN_VIRTEX_inst (
.DRCK1(drck),
.DRCK2(),
.RESET(test_logic_reset_o),
.SEL1(debug_select_o),
.SEL2(),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO1(debug_tdo_i),
.TDO2( 1'b0)
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




always @ (negedge tck_o)
begin
	if(debug_select_o && !shift_dr_o)
		capture_dr_o <= 1'b1;
	else
		capture_dr_o <= 1'b0;
end




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;

`else
`ifdef VIRTEX2




wire capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst (
.CAPTURE(capture_dr_o),
.DRCK1(drck),
.DRCK2(),
.RESET(test_logic_reset_o),
.SEL1(debug_select_o),
.SEL2(),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO1(debug_tdo_i),
.TDO2( 1'b0 )
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;

`else
`ifdef VIRTEX4



wire capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_VIRTEX4 #(
.JTAG_CHAIN(virtex_jtag_chain) 
) BSCAN_VIRTEX4_inst (
.CAPTURE(capture_dr_o),
.DRCK(drck),
.RESET(test_logic_reset_o),
.SEL(debug_select_o),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO( debug_tdo_i )
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;

`else
`ifdef VIRTEX5



wire capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_VIRTEX5 #(
.JTAG_CHAIN(virtex_jtag_chain) 
) BSCAN_VIRTEX5_inst (
.CAPTURE(capture_dr_o),
.DRCK(drck),
.RESET(test_logic_reset),
.SEL(debug_select_o),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO(debug_tdo_i)
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;


`endif
`endif
`endif
`endif
`endif
`endif
`endif
`endif

endmodule
module minsoc_xilinx_internal_jtag (
	tck_o,
	debug_tdo_i,
	tdi_o,
	test_logic_reset_o,
	run_test_idle_o,
	shift_dr_o,
	capture_dr_o,
	pause_dr_o,
	update_dr_o,
	debug_select_o
);




parameter virtex_jtag_chain = 1;

input debug_tdo_i;
output tck_o;
output tdi_o;
output test_logic_reset_o;
output run_test_idle_o;
output shift_dr_o;
output capture_dr_o;
output pause_dr_o;
output update_dr_o;
output debug_select_o;

wire debug_tdo_i;
wire tck_o;
wire drck;
wire tdi_o;
wire test_logic_reset_o;
wire run_test_idle_o;
wire shift_dr_o;
wire pause_dr_o;
wire update_dr_o;
wire debug_select_o;

`ifdef SPARTAN3E
	`define SPARTAN3
`endif

`ifdef SPARTAN2






reg capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst (
.DRCK1(drck),
.DRCK2(),
.RESET(test_logic_reset_o),
.SEL1(debug_select_o),
.SEL2(),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO1(debug_tdo_i),
.TDO2( 1'b0 )
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




always @ (negedge tck_o)
begin
	if(debug_select_o && !shift_dr_o)
		capture_dr_o <= 1'b1;
	else
		capture_dr_o <= 1'b0;
end




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;

`else
`ifdef SPARTAN3



wire capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
.CAPTURE(capture_dr_o),
.DRCK1(drck),
.DRCK2(),
.RESET(test_logic_reset_o),
.SEL1(debug_select_o),
.SEL2(),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO1(debug_tdo_i),
.TDO2(1'b0)
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;

`ifdef SPARTAN3E
	`undef SPARTAN3
`endif

`else
`ifdef SPARTAN3A



wire capture_dr_o;

BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst (
.CAPTURE(capture_dr_o),
.DRCK1(),
.DRCK2(),
.RESET(test_logic_reset_o),
.SEL1(debug_select_o),
.SEL2(),
.SHIFT(shift_dr_o),
.TCK(tck_o),
.TDI(tdi_o),
.TMS(),
.UPDATE(update_dr_o),
.TDO1(debug_tdo_i),
.TDO2( 1'b0)
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;

`else
 `ifdef SPARTAN6
    wire capture_dr_o;
    BSCAN_SPARTAN6 #(
    .JTAG_CHAIN(1)
)
BSCAN_SPARTAN6_inst (
.CAPTURE(capture_dr_o),
.DRCK(drck),
.RESET(test_logic_reset_o),
.RUNTEST(),
.SEL(debug_select_o),
.SHIFT(shift_dr_o),
.TCK(tck_o),
.TDI(tdi_o),
.TMS(),
.UPDATE(update_dr_o),
.TDO(debug_tdo_i)
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;
    
`else
`ifdef VIRTEX




reg capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_VIRTEX BSCAN_VIRTEX_inst (
.DRCK1(drck),
.DRCK2(),
.RESET(test_logic_reset_o),
.SEL1(debug_select_o),
.SEL2(),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO1(debug_tdo_i),
.TDO2( 1'b0)
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




always @ (negedge tck_o)
begin
	if(debug_select_o && !shift_dr_o)
		capture_dr_o <= 1'b1;
	else
		capture_dr_o <= 1'b0;
end




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;

`else
`ifdef VIRTEX2




wire capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst (
.CAPTURE(capture_dr_o),
.DRCK1(drck),
.DRCK2(),
.RESET(test_logic_reset_o),
.SEL1(debug_select_o),
.SEL2(),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO1(debug_tdo_i),
.TDO2( 1'b0 )
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;

`else
`ifdef VIRTEX4



wire capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_VIRTEX4 #(
.JTAG_CHAIN(virtex_jtag_chain) 
) BSCAN_VIRTEX4_inst (
.CAPTURE(capture_dr_o),
.DRCK(drck),
.RESET(test_logic_reset_o),
.SEL(debug_select_o),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO( debug_tdo_i )
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;

`else
`ifdef VIRTEX5



wire capture_dr_o;
wire update_bscan;
reg update_out;

BSCAN_VIRTEX5 #(
.JTAG_CHAIN(virtex_jtag_chain) 
) BSCAN_VIRTEX5_inst (
.CAPTURE(capture_dr_o),
.DRCK(drck),
.RESET(test_logic_reset),
.SEL(debug_select_o),
.SHIFT(shift_dr_o),
.TDI(tdi_o),
.UPDATE(update_bscan),
.TDO(debug_tdo_i)
);

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;




assign tck_o = (drck & debug_select_o & !update_bscan);



always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
begin
	if(update_bscan) update_out <= 1'b1;
	else if(capture_dr_o) update_out <= 1'b0;
	else if(!debug_select_o) update_out <= 1'b0;
end

assign update_dr_o = update_out;


`endif
`endif
`endif
`endif
`endif
`endif
`endif
`endif

endmodule