data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk <= ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v:53: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile ("hilb_tb.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v:54: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #23 rst <= 1; #20 rst <= 0; #20 en <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #23 rst <= 1; #20 rst <= 0; #20 en <= 1;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #23 rst <= 1; #20 rst <= 0; #20 en <= 1;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n      #200 en <= 0; #40 en <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n      #200 en <= 0; #40 en <= 1;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n      #200 en <= 0; #40 en <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n      #200 en <= 0; #40 en <= 1;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/fake_hilbert_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #200 $finish;\n      ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fake_hilbert_tb;

   parameter MSB = 0;

   wire [MSB:0] re, im;
   reg          clk = 0, rst = 0, en = 0, stb = 0;
   reg [MSB:0]  d;
   wire         valid;

   always #5 clk <= ~clk;


   initial begin : HILB_TB
      $dumpfile ("hilb_tb.vcd");
      $dumpvars;

      #23 rst <= 1; #20 rst <= 0; #20 en <= 1;


      #200 en <= 0; #40 en <= 1;
      #200 en <= 0; #40 en <= 1;
      
      #200 $finish;
   end


   always @(posedge clk)
     if (!rst && stb)
       d <= #3 $random;
     else
       d <= #3 d;

   always @(posedge clk)
     if (rst)
       stb <= #3 0;
     else
       stb <= #3 ~stb;


   fake_hilbert #( .WIDTH(MSB+1) ) HILBIE[MSB:0]
     (  .clock_i (clk),
        .reset_i (rst),

        .enable_i(en),
        .strobe_i(stb),
        .signal_i(d),

        .locked_o(locked),
        .strobe_o(strobe),
        .framed_o(framed),
        .sig_re_o(re),
        .sig_im_o(im)
        );


endmodule
module fake_hilbert_tb;


   parameter MSB = 0;

   wire [MSB:0] re, im;
   reg          clk = 0, rst = 0, en = 0, stb = 0;
   reg [MSB:0]  d;
   wire         valid;

   always #5 clk <= ~clk;


   initial begin : HILB_TB
      $dumpfile ("hilb_tb.vcd");
      $dumpvars;

      #23 rst <= 1; #20 rst <= 0; #20 en <= 1;


      #200 en <= 0; #40 en <= 1;
      #200 en <= 0; #40 en <= 1;
      
      #200 $finish;
   end


   always @(posedge clk)
     if (!rst && stb)
       d <= #3 $random;
     else
       d <= #3 d;

   always @(posedge clk)
     if (rst)
       stb <= #3 0;
     else
       stb <= #3 ~stb;


   fake_hilbert #( .WIDTH(MSB+1) ) HILBIE[MSB:0]
     (  .clock_i (clk),
        .reset_i (rst),

        .enable_i(en),
        .strobe_i(stb),
        .signal_i(d),

        .locked_o(locked),
        .strobe_o(strobe),
        .framed_o(framed),
        .sig_re_o(re),
        .sig_im_o(im)
        );


endmodule