data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:12: Define or directive not defined: \'`MemAddrWidth\'\n  input wire[`MemAddrWidth-1:0] ex_addr,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:15: Define or directive not defined: \'`MemAddrWidth\'\n        output reg[`MemAddrWidth-1:0] pc,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:21: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable) \n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:21: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (rst == `RstEnable) \n                             ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:23: Define or directive not defined: \'`ChipDisable\'\n            ce <= `ChipDisable;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:25: syntax error, unexpected else\n  end else if (!stall[0]) begin\n      ^~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:26: Define or directive not defined: \'`JumpUncdt\'\n   if (idex_jump_type == `JumpUncdt \n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:27: Define or directive not defined: \'`JumpBranch\'\n    || (idex_jump_type == `JumpBranch && ex_jump)) begin\n                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:28: Define or directive not defined: \'`ChipEnable\'\n    ce <= `ChipEnable;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:31: Define or directive not defined: \'`ChipEnable\'\n    ce <= `ChipEnable;\n          ^~~~~~~~~~~\n%Error: Cannot continue\n'
module pc_reg(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,


		input wire ex_jump,
		input wire[1:0] idex_jump_type,
		input wire[`MemAddrWidth-1:0] ex_addr,


        output reg[`MemAddrWidth-1:0] pc,
        output reg ce
    );
    
    always @ (posedge clk) 
    begin
        if (rst == `RstEnable) 
        begin
            ce <= `ChipDisable;
            pc <= 32'hFFFFFFFC;
		end else if (!stall[0]) begin
			if (idex_jump_type == `JumpUncdt 
				|| (idex_jump_type == `JumpBranch && ex_jump)) begin
				ce <= `ChipEnable;
				pc <= ex_addr;
			end else begin
				ce <= `ChipEnable;
				pc <= pc + 4'h4;
			end
        end 
    end
    
endmodule
module pc_reg(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,


		input wire ex_jump,
		input wire[1:0] idex_jump_type,
		input wire[`MemAddrWidth-1:0] ex_addr,


        output reg[`MemAddrWidth-1:0] pc,
        output reg ce
    );

    
    always @ (posedge clk) 
    begin
        if (rst == `RstEnable) 
        begin
            ce <= `ChipDisable;
            pc <= 32'hFFFFFFFC;
		end else if (!stall[0]) begin
			if (idex_jump_type == `JumpUncdt 
				|| (idex_jump_type == `JumpBranch && ex_jump)) begin
				ce <= `ChipEnable;
				pc <= ex_addr;
			end else begin
				ce <= `ChipEnable;
				pc <= pc + 4'h4;
			end
        end 
    end
    
endmodule