data/full_repos/permissive/172912857/project_bin_bcd_7dig/bin_bcd_7dig.v
 line:194: before: "("
data/verilator_xmls/b300b048-3dde-488a-a93e-90374b50244d.xml
module counter(
    input reset,
    input clk,
    output reg [1:0] out
    );



    always @(posedge clk, posedge reset)
        if (reset) begin
        out <= 2'b00 ;
        end 
        else begin
        out <= out + 1;
        end
endmodule
module counter(
    input reset,
    input clk,
    output reg [1:0] out
    );




    always @(posedge clk, posedge reset)
        if (reset) begin
        out <= 2'b00 ;
        end 
        else begin
        out <= out + 1;
        end
endmodule