data/full_repos/permissive/157005262/verilog/spoilers/keypad.v
 line:16: before: "+"
1: b"%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:23: syntax error, unexpected pullup, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule pullup(output wire pin, output wire d_in);\n       ^~~~~~\n%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\nmodule pullup(output wire pin, output wire d_in);\n                               ^~~~~~\n%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:49: syntax error, unexpected ',', expecting ')'\n  pullup io1(PIO1_02, row_pins[0]);\n                    ^\n%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:50: syntax error, unexpected ',', expecting ')'\n  pullup io2(PIO1_03, row_pins[1]);\n                    ^\n%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:51: syntax error, unexpected ',', expecting ')'\n  pullup io3(PIO1_04, row_pins[2]);\n                    ^\n%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:52: syntax error, unexpected ',', expecting ')'\n  pullup io4(PIO1_05, row_pins[3]);\n                    ^\n%Error: Exiting due to 6 error(s)\n"
module keypad(input wire clk,
              output reg [3:0]  column_pins,
              input wire [3:0]   row_pins,
              output reg [15:0] keys);

  reg [1:0] column = 0;

  initial begin
    column_pins = 4'b1110;
    keys = 0;
  end

  integer i;

  always @(posedge clk) begin
    for (i = 0; i < 4; i++)
      keys[i*4 + column] <= (row_pins[i] == 0);
    column <= (column + 1) % 4;
    column_pins <= (column_pins << 1) + (column_pins >> 3);
  end
endmodule
module keypad(input wire clk,
              output reg [3:0]  column_pins,
              input wire [3:0]   row_pins,
              output reg [15:0] keys);


  reg [1:0] column = 0;

  initial begin
    column_pins = 4'b1110;
    keys = 0;
  end

  integer i;

  always @(posedge clk) begin
    for (i = 0; i < 4; i++)
      keys[i*4 + column] <= (row_pins[i] == 0);
    column <= (column + 1) % 4;
    column_pins <= (column_pins << 1) + (column_pins >> 3);
  end
endmodule