data/full_repos/permissive/147086086/Lab5/hw/simple_pwm/simple_pwm_tb.v
 line:31: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/147086086/Lab5/hw/simple_pwm/simple_pwm_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    forever #(PERIOD/2) i_clk = ~i_clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147086086/Lab5/hw/simple_pwm/simple_pwm_tb.v:31: syntax error, unexpected \'@\'\n    repeat(10) @(negedge i_clk);\n               ^\n%Error: data/full_repos/permissive/147086086/Lab5/hw/simple_pwm/simple_pwm_tb.v:36: syntax error, unexpected \'@\'\n        repeat (5*1024) @(negedge i_clk);\n                        ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

parameter PERIOD = 20;

wire [35:0] gpio;
wire        o_pwm;
reg         i_clk;
reg         i_pwm_en;
reg [9:0]   i_pwm_dc;

integer i = 0;

simple_pwm simple_pwm_inst (.MAX10_CLK1_50 (i_clk), 
                            .KEY ({1'b0, i_pwm_en}), 
                            .SW (i_pwm_dc), 
                            .GPIO (gpio)
                           );

assign o_pwm = gpio[0];

initial begin
    i_clk = 0;
    forever #(PERIOD/2) i_clk = ~i_clk;
end

initial begin
    i_pwm_dc = 0;

    repeat(10) @(negedge i_clk);

    for (i=0; i<1024; i=i+1) begin   
        i_pwm_dc = i;   
        i_pwm_en = $random();      
        repeat (5*1024) @(negedge i_clk);
    end

    $finish;  
end
  
endmodule
module testbench;


parameter PERIOD = 20;

wire [35:0] gpio;
wire        o_pwm;
reg         i_clk;
reg         i_pwm_en;
reg [9:0]   i_pwm_dc;

integer i = 0;

simple_pwm simple_pwm_inst (.MAX10_CLK1_50 (i_clk), 
                            .KEY ({1'b0, i_pwm_en}), 
                            .SW (i_pwm_dc), 
                            .GPIO (gpio)
                           );

assign o_pwm = gpio[0];

initial begin
    i_clk = 0;
    forever #(PERIOD/2) i_clk = ~i_clk;
end

initial begin
    i_pwm_dc = 0;

    repeat(10) @(negedge i_clk);

    for (i=0; i<1024; i=i+1) begin   
        i_pwm_dc = i;   
        i_pwm_en = $random();      
        repeat (5*1024) @(negedge i_clk);
    end

    $finish;  
end
  
endmodule