data/full_repos/permissive/164251444/analog/cdk_oa/P2PARN1X1/netlsit/pre_netlist/verilog.v
 line:16: before: "CDS_LIBNAME"
1: b"%Error: data/full_repos/permissive/164251444/analog/cdk_oa/P2PARN1X1/netlsit/pre_netlist/verilog.v:21: Cannot find file containing module: 'nfet_b'\nnfet_b  N0 ( .b(VPW), .s(VSS), .g(C), .d(Z));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164251444/analog/cdk_oa/P2PARN1X1/netlsit/pre_netlist,data/full_repos/permissive/164251444/nfet_b\n             data/full_repos/permissive/164251444/analog/cdk_oa/P2PARN1X1/netlsit/pre_netlist,data/full_repos/permissive/164251444/nfet_b.v\n             data/full_repos/permissive/164251444/analog/cdk_oa/P2PARN1X1/netlsit/pre_netlist,data/full_repos/permissive/164251444/nfet_b.sv\n             nfet_b\n             nfet_b.v\n             nfet_b.sv\n             obj_dir/nfet_b\n             obj_dir/nfet_b.v\n             obj_dir/nfet_b.sv\n%Error: data/full_repos/permissive/164251444/analog/cdk_oa/P2PARN1X1/netlsit/pre_netlist/verilog.v:22: Cannot find file containing module: 'pfet_b'\npfet_b  P1 ( .b(VNW), .s(VDD), .g(B), .d(Z));\n^~~~~~\n%Error: data/full_repos/permissive/164251444/analog/cdk_oa/P2PARN1X1/netlsit/pre_netlist/verilog.v:23: Cannot find file containing module: 'pfet_b'\npfet_b  P0 ( .b(VNW), .s(VDD), .g(A), .d(Z));\n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module P2PARN1X1 ( Z, VDD, VNW, VPW, VSS, A, B, C );

output  Z;

inout  VDD, VNW, VPW, VSS;

input  A, B, C;


specify 
    specparam CDS_LIBNAME  = "rail12lp";
    specparam CDS_CELLNAME = "P2PARN1X1";
    specparam CDS_VIEWNAME = "schematic";
endspecify

nfet_b  N0 ( .b(VPW), .s(VSS), .g(C), .d(Z));
pfet_b  P1 ( .b(VNW), .s(VDD), .g(B), .d(Z));
pfet_b  P0 ( .b(VNW), .s(VDD), .g(A), .d(Z));

endmodule
module P2PARN1X1 ( Z, VDD, VNW, VPW, VSS, A, B, C );


output  Z;

inout  VDD, VNW, VPW, VSS;

input  A, B, C;


specify 
    specparam CDS_LIBNAME  = "rail12lp";
    specparam CDS_CELLNAME = "P2PARN1X1";
    specparam CDS_VIEWNAME = "schematic";
endspecify

nfet_b  N0 ( .b(VPW), .s(VSS), .g(C), .d(Z));
pfet_b  P1 ( .b(VNW), .s(VDD), .g(B), .d(Z));
pfet_b  P0 ( .b(VNW), .s(VDD), .g(A), .d(Z));

endmodule