data/full_repos/permissive/165217789/FusionAccel/deprecated/dma_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/deprecated/dma_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/deprecated/dma_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/deprecated/dma_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #100 reads_en = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/deprecated/dma_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #40 ib_valid = 1;\n    ^\n%Error: data/full_repos/permissive/165217789/FusionAccel/deprecated/dma_tb.v:25: Cannot find file containing module: \'dma\'\ndma dma_\n^~~\n        ... Looked in:\n             data/full_repos/permissive/165217789/FusionAccel/deprecated,data/full_repos/permissive/165217789/dma\n             data/full_repos/permissive/165217789/FusionAccel/deprecated,data/full_repos/permissive/165217789/dma.v\n             data/full_repos/permissive/165217789/FusionAccel/deprecated,data/full_repos/permissive/165217789/dma.sv\n             dma\n             dma.v\n             dma.sv\n             obj_dir/dma\n             obj_dir/dma.v\n             obj_dir/dma.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dma_tb;

reg clk;
reg reset;
reg writes_en;
reg reads_en;
reg calib_done;

reg [31:0] ib_data;
reg [9:0] ib_count;
reg ib_valid;
reg ib_empty;

reg [9:0] ob_count;

reg rd_empty;
reg [31:0] rd_data;

reg cmd_full;
reg wr_full;


dma dma_
	(
	.clk(clk),
	.reset(reset),
	.writes_en(writes_en),
	.reads_en(reads_en),
	.calib_done(calib_done), 

	.ib_re(ib_re),
	.ib_data(ib_data),
	.ib_count(ib_count),
	.ib_valid(ib_valid),
	.ib_empty(ib_empty),

	.ob_we(ob_we),
	.ob_data(ob_data),
	.ob_count(ob_count),
	
	.rd_en(rd_en), 
	.rd_empty(rd_empty),
	.rd_data(rd_data),
	
	.cmd_full(cmd_full),
	.cmd_en(cmd_en),
	.cmd_instr(cmd_instr),
	.cmd_byte_addr(cmd_byte_addr),
	.cmd_bl(cmd_bl), 

	.wr_full(wr_full),
	.wr_en(wr_en),
	.wr_data(wr_data),
	.wr_mask(wr_mask)
	);

always #5 clk = ~clk;

initial begin
    reset = 1;
    clk = 0;
    writes_en = 0;
	reads_en = 0;
    calib_done = 0;
    ib_count = 0;
	ob_count = 0;
    ib_valid = 0;
	rd_empty = 0;
    #10 reset = 0;
    #100 reads_en = 1;
    calib_done = 1;
    ob_count = 64;
    #40 ib_valid = 1;

end
endmodule
module dma_tb;


reg clk;
reg reset;
reg writes_en;
reg reads_en;
reg calib_done;

reg [31:0] ib_data;
reg [9:0] ib_count;
reg ib_valid;
reg ib_empty;

reg [9:0] ob_count;

reg rd_empty;
reg [31:0] rd_data;

reg cmd_full;
reg wr_full;


dma dma_
	(
	.clk(clk),
	.reset(reset),
	.writes_en(writes_en),
	.reads_en(reads_en),
	.calib_done(calib_done), 

	.ib_re(ib_re),
	.ib_data(ib_data),
	.ib_count(ib_count),
	.ib_valid(ib_valid),
	.ib_empty(ib_empty),

	.ob_we(ob_we),
	.ob_data(ob_data),
	.ob_count(ob_count),
	
	.rd_en(rd_en), 
	.rd_empty(rd_empty),
	.rd_data(rd_data),
	
	.cmd_full(cmd_full),
	.cmd_en(cmd_en),
	.cmd_instr(cmd_instr),
	.cmd_byte_addr(cmd_byte_addr),
	.cmd_bl(cmd_bl), 

	.wr_full(wr_full),
	.wr_en(wr_en),
	.wr_data(wr_data),
	.wr_mask(wr_mask)
	);

always #5 clk = ~clk;

initial begin
    reset = 1;
    clk = 0;
    writes_en = 0;
	reads_en = 0;
    calib_done = 0;
    ib_count = 0;
	ob_count = 0;
    ib_valid = 0;
	rd_empty = 0;
    #10 reset = 0;
    #100 reads_en = 1;
    calib_done = 1;
    ob_count = 64;
    #40 ib_valid = 1;

end
endmodule