data/full_repos/permissive/114811571/test/samples/mips-cpu/cla_full_adder.v
data/verilator_xmls/1cb48a13-e1a6-4896-97fc-64c1c7367281.xml
module cla_full_adder(
		input	a,
		input	b,
		input	c,
		output	g,
		output	p,
		output	s);

	assign g = a & b;
	assign p = a ^ b;
	assign s = a ^ (b ^ c);

endmodule
module cla_full_adder(
		input	a,
		input	b,
		input	c,
		output	g,
		output	p,
		output	s);


	assign g = a & b;
	assign p = a ^ b;
	assign s = a ^ (b ^ c);

endmodule