data/full_repos/permissive/111433415/verilog/08_memorias/08-1_rom/rom_mul.v
data/verilator_xmls/20787d07-9cb2-4655-a2ba-222e9741989f.xml
module rommul_bcd (
    input wire [3:0] x,
    input wire [3:0] y,
    output wire [7:0] z
    );



    rom256x8 rom (.a({x, y}), .d(z));

endmodule
module rommul_bcd (
    input wire [3:0] x,
    input wire [3:0] y,
    output wire [7:0] z
    );




    rom256x8 rom (.a({x, y}), .d(z));

endmodule