data/full_repos/permissive/108382235/SingleCycle.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                         : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n       ^~~~~~~~~~~\n                                                                         : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n       ^~~~~~~~\n                                                                         : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n       ^~~~~~~~~~~~\n                                                                         : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n       ^~~~~~~~~~\n                                                                         : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n       ^~~~~~~~~~\n                                                                         : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                      : ... In instance SingleCycle.M_DataMemory\n  if (MemRead) ReadData=Dmemory[Address[31:2]];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                      : ... In instance SingleCycle.M_DataMemory\n  else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                      : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n                                                                        ^\n%Error: Exiting due to 4 warning(s)\n'
module Alucontrol(Aluctrl,Aluop,funct);
	input [5:0] funct;
	input [1:0] Aluop;
	output [3:0] Aluctrl;

	reg [3:0] Aluctrl;

	always @ (Aluop or funct)
	begin
		if(Aluop==2'b00) Aluctrl=4'b0010;
		else if(Aluop==2'b01) Aluctrl=4'b0110;
		else if(Aluop==2'b11) Aluctrl=4'b0000;
		else if(Aluop==2'b10 && funct==6'b100000) Aluctrl=4'b0010;
		else if(Aluop==2'b10 && funct==6'b100010) Aluctrl=4'b0110;
		else if(Aluop==2'b10 && funct==6'b100100) Aluctrl=4'b0000;
		else if(Aluop==2'b10 && funct==6'b100101) Aluctrl=4'b0001;
		else if(Aluop==2'b10 && funct==6'b101010) Aluctrl=4'b0111;
	end
endmodule
module Alucontrol(Aluctrl,Aluop,funct);

	input [5:0] funct;
	input [1:0] Aluop;
	output [3:0] Aluctrl;

	reg [3:0] Aluctrl;

	always @ (Aluop or funct)
	begin
		if(Aluop==2'b00) Aluctrl=4'b0010;
		else if(Aluop==2'b01) Aluctrl=4'b0110;
		else if(Aluop==2'b11) Aluctrl=4'b0000;
		else if(Aluop==2'b10 && funct==6'b100000) Aluctrl=4'b0010;
		else if(Aluop==2'b10 && funct==6'b100010) Aluctrl=4'b0110;
		else if(Aluop==2'b10 && funct==6'b100100) Aluctrl=4'b0000;
		else if(Aluop==2'b10 && funct==6'b100101) Aluctrl=4'b0001;
		else if(Aluop==2'b10 && funct==6'b101010) Aluctrl=4'b0111;
	end
endmodule