data/full_repos/permissive/123690745/CP0.v
'utf-8' codec can't decode byte 0xa5 in position 835: invalid start byte
1: b"%Error: data/full_repos/permissive/123690745/CP0.v:80: Cannot find file containing module: 'MUX324'\n  MUX324 MUX324(.In0(SR),.In1(Cause),.In2(EPC),.In3(PRId),.Select(AddressLow),.Out(DataOut));\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/MUX324\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/MUX324.v\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/MUX324.sv\n             MUX324\n             MUX324.v\n             MUX324.sv\n             obj_dir/MUX324\n             obj_dir/MUX324.v\n             obj_dir/MUX324.sv\n%Error: Exiting due to 1 error(s)\n"
module CP0 (
	 input [4:0] Address,
    input [31:0] DataIn,
    input [31:0] ExcPC,
    input ErrorRlM,
    input ErrorOvM,
    input [7:2] HWInterruptRequest,
    input CP0WriteM,
	 input MemWriteM,
	 input StartM,
    input EXLSet,
    input EXLClearM,
    input clk,
    input reset,
	 input [31:0] PCM,
	 input AtDelaySlotM,
    output InterruptRequest,
    output reg [31:0] EPC = 0,
    output [31:0] DataOut
    );
	 wire [1:0] AddressLow;
	 wire [7:2] IM;
	 wire IE;
	 wire EXL;

	 assign AddressLow = Address[1:0];
	 
	 reg [31:0] SR = 0;
	 reg [31:0] Cause = 0;

	 reg [31:0] PRId = 32'hdead2333;
	 
	 MUX324 MUX324(.In0(SR),.In1(Cause),.In2(EPC),.In3(PRId),.Select(AddressLow),.Out(DataOut));
	 
	 assign  IM = SR[15:10];
	 assign  IE = SR[0];
	 assign  EXL = SR[1];
	 assign 	InterruptRequest = |(HWInterruptRequest[7:2] & IM) & IE & !EXL;

	 always @(posedge clk) begin
		Cause[15:10] <= HWInterruptRequest[7:2]; 
		if (reset) begin
			SR <= 0;
			Cause <= 0;
			EPC <= 0;
			PRId <= 32'hdead2333;
		end
		else if (InterruptRequest) begin
			EPC <= AtDelaySlotM ? (PCM-4) :
					 (MemWriteM ||StartM)? (PCM+4) :
					 PCM;
			SR[1] <= 1;
			Cause[6:2] <= 0;
		end
		else begin
			if (CP0WriteM) begin
				if (AddressLow == 0) begin
					{SR[15:10],SR[1],SR[0]} <= {DataIn[15:10],DataIn[1],DataIn[0]};


				end
				if (AddressLow == 2) begin	
					EPC <= DataIn;

				end
			end
			if (EXLClearM) begin
				SR[1] <= 0;
			end
		end
	 end
	 
endmodule
module CP0 (
	 input [4:0] Address,
    input [31:0] DataIn,
    input [31:0] ExcPC,
    input ErrorRlM,
    input ErrorOvM,
    input [7:2] HWInterruptRequest,
    input CP0WriteM,
	 input MemWriteM,
	 input StartM,
    input EXLSet,
    input EXLClearM,
    input clk,
    input reset,
	 input [31:0] PCM,
	 input AtDelaySlotM,
    output InterruptRequest,
    output reg [31:0] EPC = 0,
    output [31:0] DataOut
    );

	 wire [1:0] AddressLow;
	 wire [7:2] IM;
	 wire IE;
	 wire EXL;

	 assign AddressLow = Address[1:0];
	 
	 reg [31:0] SR = 0;
	 reg [31:0] Cause = 0;

	 reg [31:0] PRId = 32'hdead2333;
	 
	 MUX324 MUX324(.In0(SR),.In1(Cause),.In2(EPC),.In3(PRId),.Select(AddressLow),.Out(DataOut));
	 
	 assign  IM = SR[15:10];
	 assign  IE = SR[0];
	 assign  EXL = SR[1];
	 assign 	InterruptRequest = |(HWInterruptRequest[7:2] & IM) & IE & !EXL;

	 always @(posedge clk) begin
		Cause[15:10] <= HWInterruptRequest[7:2]; 
		if (reset) begin
			SR <= 0;
			Cause <= 0;
			EPC <= 0;
			PRId <= 32'hdead2333;
		end
		else if (InterruptRequest) begin
			EPC <= AtDelaySlotM ? (PCM-4) :
					 (MemWriteM ||StartM)? (PCM+4) :
					 PCM;
			SR[1] <= 1;
			Cause[6:2] <= 0;
		end
		else begin
			if (CP0WriteM) begin
				if (AddressLow == 0) begin
					{SR[15:10],SR[1],SR[0]} <= {DataIn[15:10],DataIn[1],DataIn[0]};


				end
				if (AddressLow == 2) begin	
					EPC <= DataIn;

				end
			end
			if (EXLClearM) begin
				SR[1] <= 0;
			end
		end
	 end
	 
endmodule