data/full_repos/permissive/176606610/ip_repo/dsm_order6/src/fac.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/176606610/ip_repo/dsm_order6/src/fac.v:41: Cannot find file containing module: 'xa'\n    xa #(.CGAINA(CGAINA)) xai\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/176606610/ip_repo/dsm_order6/src,data/full_repos/permissive/176606610/xa\n             data/full_repos/permissive/176606610/ip_repo/dsm_order6/src,data/full_repos/permissive/176606610/xa.v\n             data/full_repos/permissive/176606610/ip_repo/dsm_order6/src,data/full_repos/permissive/176606610/xa.sv\n             xa\n             xa.v\n             xa.sv\n             obj_dir/xa\n             obj_dir/xa.v\n             obj_dir/xa.sv\n%Error: data/full_repos/permissive/176606610/ip_repo/dsm_order6/src/fac.v:53: Cannot find file containing module: 'xb'\n     xb #(.CGAINB(CGAINB),.CGAING(CGAING)) xbi\n     ^~\n%Error: Exiting due to 2 error(s)\n"
module fac
    #(parameter CGAINA = 0,
    parameter CGAINB = 0,
    parameter CGAING = 0)(
    input clk,
    input rst_n,
    input fs_enb,
    input [35:0] csump,
    input [35:0] inpba,
    input [35:0] inpbb,
    input [35:0] outaa,
    input [35:0] outab,
    output [35:0] xout
    );
    
    wire [35:0] gsum;
    wire [35:0] csum;
    
    xa #(.CGAINA(CGAINA)) xai
        (
        .clk(clk),
        .rst_n(rst_n),
        .fs_enb(fs_enb),
        .inpb(inpba),
        .outa(outaa),
        .csump(csump),
        .gsum(gsum),
        .csum(csum)
        );
        
     xb #(.CGAINB(CGAINB),.CGAING(CGAING)) xbi
     (
       .clk(clk),
       .rst_n(rst_n),
       .fs_enb(fs_enb),
       .inpb(inpbb),
       .outa(outab),
       .csump(csum),
       .gsum(gsum),
       .csum(xout)
       );
           
endmodule
module fac
    #(parameter CGAINA = 0,
    parameter CGAINB = 0,
    parameter CGAING = 0)(
    input clk,
    input rst_n,
    input fs_enb,
    input [35:0] csump,
    input [35:0] inpba,
    input [35:0] inpbb,
    input [35:0] outaa,
    input [35:0] outab,
    output [35:0] xout
    );

    
    wire [35:0] gsum;
    wire [35:0] csum;
    
    xa #(.CGAINA(CGAINA)) xai
        (
        .clk(clk),
        .rst_n(rst_n),
        .fs_enb(fs_enb),
        .inpb(inpba),
        .outa(outaa),
        .csump(csump),
        .gsum(gsum),
        .csum(csum)
        );
        
     xb #(.CGAINB(CGAINB),.CGAING(CGAING)) xbi
     (
       .clk(clk),
       .rst_n(rst_n),
       .fs_enb(fs_enb),
       .inpb(inpbb),
       .outa(outab),
       .csump(csum),
       .gsum(gsum),
       .csum(xout)
       );
           
endmodule