data/full_repos/permissive/177233467/alu.v
data/verilator_xmls/3b5ce786-8c7c-4a5b-b8e9-0cf6b370ea11.xml
function check_cond;
    input [3:0] cc;
    input [3:0] cpsr;

    reg result;

    begin
        result = 0;
        case(cc[3:1])
            3'b000: result = (cpsr[2] == 1);
            3'b001: result = (cpsr[1] == 1);
            3'b010: result = (cpsr[3] == 1);
            3'b011: result = (cpsr[0] == 1);
            3'b100: result = (cpsr[1] == 1) & (cpsr[2] == 0);
            3'b101: result = (cpsr[3] == cpsr[0]);
            3'b110: result = (cpsr[3] == cpsr[0]) & (cpsr[2] == 0);
            3'b111: result = 1'b1;
        endcase
        if (cc[0])
            result = !result;
        check_cond = result;
    end
endfunction
function check_cond;

    input [3:0] cc;
    input [3:0] cpsr;

    reg result;

    begin
        result = 0;
        case(cc[3:1])
            3'b000: result = (cpsr[2] == 1);
            3'b001: result = (cpsr[1] == 1);
            3'b010: result = (cpsr[3] == 1);
            3'b011: result = (cpsr[0] == 1);
            3'b100: result = (cpsr[1] == 1) & (cpsr[2] == 0);
            3'b101: result = (cpsr[3] == cpsr[0]);
            3'b110: result = (cpsr[3] == cpsr[0]) & (cpsr[2] == 0);
            3'b111: result = 1'b1;
        endcase
        if (cc[0])
            result = !result;
        check_cond = result;
    end
endfunction