data/full_repos/permissive/170402453/PWM10.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170402453/PWM10.v:46: Operator LT expects 5 bits on the RHS, but RHS\'s VARREF \'duty\' generates 4 bits.\n                                                               : ... In instance PWM10\n  pwm <= (cycle < duty) ? 1 : 0;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module PWM10(
    input clk,
    input [3:0] duty,
    output pwm_out
    );
	 

	 reg [4:0] cycle;
	 
	 reg pwm;
	 assign pwm_out = pwm;
	 initial begin
		cycle = 0;
		pwm = 0;
	 end
	 
	 parameter CYCLE_SIZE = 10;
	 

	 always @(posedge clk) begin

		cycle <= (cycle >= CYCLE_SIZE) ? 0 : cycle+1;
		


		pwm <= (cycle < duty) ? 1 : 0;

	 end

endmodule
module PWM10(
    input clk,
    input [3:0] duty,
    output pwm_out
    );

	 

	 reg [4:0] cycle;
	 
	 reg pwm;
	 assign pwm_out = pwm;
	 initial begin
		cycle = 0;
		pwm = 0;
	 end
	 
	 parameter CYCLE_SIZE = 10;
	 

	 always @(posedge clk) begin

		cycle <= (cycle >= CYCLE_SIZE) ? 0 : cycle+1;
		


		pwm <= (cycle < duty) ? 1 : 0;

	 end

endmodule