data/full_repos/permissive/183345139/projects/loopback/top_loopback.v
1: b"%Error: data/full_repos/permissive/183345139/projects/loopback/top_loopback.v:98: Cannot find file containing module: 'pll_60mhz'\npll_60mhz pll_60mhz_inst (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/183345139/projects/loopback,data/full_repos/permissive/183345139/pll_60mhz\n             data/full_repos/permissive/183345139/projects/loopback,data/full_repos/permissive/183345139/pll_60mhz.v\n             data/full_repos/permissive/183345139/projects/loopback,data/full_repos/permissive/183345139/pll_60mhz.sv\n             pll_60mhz\n             pll_60mhz.v\n             pll_60mhz.sv\n             obj_dir/pll_60mhz\n             obj_dir/pll_60mhz.v\n             obj_dir/pll_60mhz.sv\n%Error: data/full_repos/permissive/183345139/projects/loopback/top_loopback.v:104: Cannot find file containing module: 'buart'\nbuart # (\n^~~~~\n%Error: Exiting due to 2 error(s)\n"
module top_loopback
(
    input wire  CLK_16MHZ,


    input wire  PIN_9,
    output wire PIN_10,


    output wire PIN_5,
    output wire PIN_8,


    output wire PIN_18,
    output wire PIN_19,
    output wire PIN_26,

    output wire PIN_20,
    output wire PIN_29,
    output wire PIN_21,
    output wire PIN_30,
    output wire PIN_22

);


parameter integer CLK_FREQUENCY = 60_000_000;
parameter integer BAUD = 32'd115_200;



wire clk_60mhz;
wire locked;
wire rxd;
wire txd;

reg reset = 0;
reg [7:0] count = 0;

reg uart_rd;
reg uart_wr;
wire rx_valid;
wire tx_busy;

wire [7:0] rx_data;
reg [7:0] tx_data;

assign rxd = PIN_9;
assign PIN_10 = txd;


assign PIN_18 = loop_state;
assign PIN_19 = ~txd;
assign PIN_26 = ~rxd;


assign PIN_5 = 0;
assign PIN_8 = 0;



assign PIN_20 = 0;
assign PIN_29 = 0;
assign PIN_21 = 0;
assign PIN_30 = 0;
assign PIN_22 = 0;




pll_60mhz pll_60mhz_inst (
    .clock_in(CLK_16MHZ),
    .clock_out(clk_60mhz),
    .locked(locked)
);

buart # (
    .CLKFREQ(CLK_FREQUENCY)
) uart_inst (
   .clk(clk_60mhz),
   .resetq(~reset),
   .baud(BAUD),
   .rx(rxd),
   .tx(txd),
   .rd(uart_rd),
   .wr(uart_wr),
   .valid(rx_valid),
   .busy(tx_busy),
   .tx_data(tx_data),
   .rx_data(rx_data)
);






always @ (posedge clk_60mhz)
begin
    if (count < 10) begin
        reset <= 1;
        count <= count + 1;
    end else begin
        reset <= 0;
    end
end


reg loop_state;
localparam RECV_CHAR = 0;
localparam SEND_CHAR = 1;
always @ (posedge clk_60mhz)
begin
    if (reset) begin
        uart_rd <= 0;
        uart_wr <= 0;
        tx_data <= 0;
        loop_state <= 0;
    end else begin
        case (loop_state)
            RECV_CHAR : begin
                uart_rd <= 0;
                uart_wr <= 0;
                if (rx_valid) begin
                    uart_rd <= 1;
                    tx_data <= rx_data;
                    loop_state <= SEND_CHAR;
                end
            end
            SEND_CHAR : begin
                uart_rd <= 0;
                if (~tx_busy) begin
                    uart_wr <= 1;
                    loop_state <= RECV_CHAR;
                end
            end
            default : begin
            end
        endcase
    end
end

endmodule
module top_loopback
(
    input wire  CLK_16MHZ,


    input wire  PIN_9,
    output wire PIN_10,


    output wire PIN_5,
    output wire PIN_8,


    output wire PIN_18,
    output wire PIN_19,
    output wire PIN_26,

    output wire PIN_20,
    output wire PIN_29,
    output wire PIN_21,
    output wire PIN_30,
    output wire PIN_22

);



parameter integer CLK_FREQUENCY = 60_000_000;
parameter integer BAUD = 32'd115_200;



wire clk_60mhz;
wire locked;
wire rxd;
wire txd;

reg reset = 0;
reg [7:0] count = 0;

reg uart_rd;
reg uart_wr;
wire rx_valid;
wire tx_busy;

wire [7:0] rx_data;
reg [7:0] tx_data;

assign rxd = PIN_9;
assign PIN_10 = txd;


assign PIN_18 = loop_state;
assign PIN_19 = ~txd;
assign PIN_26 = ~rxd;


assign PIN_5 = 0;
assign PIN_8 = 0;



assign PIN_20 = 0;
assign PIN_29 = 0;
assign PIN_21 = 0;
assign PIN_30 = 0;
assign PIN_22 = 0;




pll_60mhz pll_60mhz_inst (
    .clock_in(CLK_16MHZ),
    .clock_out(clk_60mhz),
    .locked(locked)
);

buart # (
    .CLKFREQ(CLK_FREQUENCY)
) uart_inst (
   .clk(clk_60mhz),
   .resetq(~reset),
   .baud(BAUD),
   .rx(rxd),
   .tx(txd),
   .rd(uart_rd),
   .wr(uart_wr),
   .valid(rx_valid),
   .busy(tx_busy),
   .tx_data(tx_data),
   .rx_data(rx_data)
);






always @ (posedge clk_60mhz)
begin
    if (count < 10) begin
        reset <= 1;
        count <= count + 1;
    end else begin
        reset <= 0;
    end
end


reg loop_state;
localparam RECV_CHAR = 0;
localparam SEND_CHAR = 1;
always @ (posedge clk_60mhz)
begin
    if (reset) begin
        uart_rd <= 0;
        uart_wr <= 0;
        tx_data <= 0;
        loop_state <= 0;
    end else begin
        case (loop_state)
            RECV_CHAR : begin
                uart_rd <= 0;
                uart_wr <= 0;
                if (rx_valid) begin
                    uart_rd <= 1;
                    tx_data <= rx_data;
                    loop_state <= SEND_CHAR;
                end
            end
            SEND_CHAR : begin
                uart_rd <= 0;
                if (~tx_busy) begin
                    uart_wr <= 1;
                    loop_state <= RECV_CHAR;
                end
            end
            default : begin
            end
        endcase
    end
end

endmodule