data/full_repos/permissive/18770871/andgate.v
None: at end of input
data/verilator_xmls/043e10c9-3b83-40d7-a48f-8be1f6cc809f.xml
module andgate(
  mem_branch,
  zero,
  pcsrc
);
input mem_branch;
input zero;
output pcsrc;

assign pcsrc = mem_branch & zero;

endmodule
module andgate(
  mem_branch,
  zero,
  pcsrc
);

input mem_branch;
input zero;
output pcsrc;

assign pcsrc = mem_branch & zero;

endmodule