data/full_repos/permissive/172054326/rtl/xdivinsa.v
 line:61: before: "@"
1: b"%Error: data/full_repos/permissive/172054326/rtl/xdivinsa.v:60: syntax error, unexpected '@'\n                @(posedge cop_clk)\n                ^\n%Error: Exiting due to 1 error(s)\n"
module lfsr32 #(
parameter RESET_VALUE = 32'h6789ABCD
)(
input  wire        clk        ,
input  wire        rst        ,
input  wire        update     ,
input  wire        extra_tap  ,
output reg  [31:0] prng
);

wire        n_prng_lsb =  prng[31] ~^ prng[21] ~^ prng[ 1] ~^ prng[ 0] ^
                          extra_tap ;

wire [31:0] n_prng     = {prng[31-1:0], n_prng_lsb};

always @(posedge clk) begin
    if     (rst)       prng <= RESET_VALUE;
    else if( update  ) prng <= n_prng;
end

endmodule
module lfsr32 #(
parameter RESET_VALUE = 32'h6789ABCD
)(
input  wire        clk        ,
input  wire        rst        ,
input  wire        update     ,
input  wire        extra_tap  ,
output reg  [31:0] prng
);


wire        n_prng_lsb =  prng[31] ~^ prng[21] ~^ prng[ 1] ~^ prng[ 0] ^
                          extra_tap ;

wire [31:0] n_prng     = {prng[31-1:0], n_prng_lsb};

always @(posedge clk) begin
    if     (rst)       prng <= RESET_VALUE;
    else if( update  ) prng <= n_prng;
end

endmodule