data/full_repos/permissive/143278/ivltests/br_gh443.v
 line:3: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh443.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  task tsk;
    $display("In task %m()");
  endtask

  function void fnc();
    $display("In function %m()");
  endfunction

  initial begin
    $display("In %m.initial");
    tsk();
    fnc();
    #10;
    $display("Done with simulation at %0d", $time);
  end

  final begin

    fnc();
    $display("In %m.final");
    $display("PASSED");
  end
endmodule
module top;

  task tsk;
    $display("In task %m()");
  endtask

  function void fnc();
    $display("In function %m()");
  endfunction

  initial begin
    $display("In %m.initial");
    tsk();
    fnc();
    #10;
    $display("Done with simulation at %0d", $time);
  end

  final begin

    fnc();
    $display("In %m.final");
    $display("PASSED");
  end
endmodule