data/full_repos/permissive/20759093/test_pc.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/20759093/test_pc.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_pc.v:55: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/20759093/test_pc.v:35: Cannot find file containing module: \'program_counter\'\n program_counter uut (\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/program_counter\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/program_counter.v\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/program_counter.sv\n             program_counter\n             program_counter.v\n             program_counter.sv\n             obj_dir/program_counter\n             obj_dir/program_counter.v\n             obj_dir/program_counter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_pc;


	reg clk;
	reg [31:0] pc_next;


	wire [31:0] pc_now;


	program_counter uut (
		.clk(clk), 
		.pc_next(pc_next), 
		.pc_now(pc_now)
	);

	initial begin

		clk = 0;
		pc_next = 0;


		#100;
        

		
	end
     
	always @* pc_next <= pc_now + 4;
	
	always #10 clk = ~clk;
endmodule
module test_pc;



	reg clk;
	reg [31:0] pc_next;


	wire [31:0] pc_now;


	program_counter uut (
		.clk(clk), 
		.pc_next(pc_next), 
		.pc_now(pc_now)
	);

	initial begin

		clk = 0;
		pc_next = 0;


		#100;
        

		
	end
     
	always @* pc_next <= pc_now + 4;
	
	always #10 clk = ~clk;
endmodule