data/full_repos/permissive/211316121/lab6_2/sources_1/new/Timer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Timer.v:58: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                       : ... Top module \'digitalClock_top\'\nmodule digitalClock_top(\n       ^~~~~~~~~~~~~~~~\n                                                                                       : ... Top module \'_74LS163\'\nmodule _74LS163(\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module digitalClock_top(
    input CLK100MHZ,
    input [13:0] SW,
    output CA,
    output CB,
    output CC,
    output CD,
    output CE,
    output CF,
    output CG,
    output [7:0] AN
    );
endmodule
module digitalClock_top(
    input CLK100MHZ,
    input [13:0] SW,
    output CA,
    output CB,
    output CC,
    output CD,
    output CE,
    output CF,
    output CG,
    output [7:0] AN
    );

endmodule