data/full_repos/permissive/137416864/benchmarks/techmapping/tigfet/sclib_tigfet10_hpnw4_tt_0p70v_25c.v
None: at end of input
data/verilator_xmls/66fbbc70-176b-43e7-9514-2e141670a68b.xml
module MUXI2_HPNW4 (Y, A, B, S0);
	output Y;
	input A, B, S0;


	buf (Y, 1'b0);


	specify
		if (B)
			(A => Y) = 0;
		if (~B)
			(A => Y) = 0;
		ifnone (A => Y) = 0;
		if (A)
			(B => Y) = 0;
		if (~A)
			(B => Y) = 0;
		ifnone (B => Y) = 0;
		(posedge S0 => (Y:S0)) = 0;
		(negedge S0 => (Y:S0)) = 0;
	endspecify
endmodule
module MUXI2_HPNW4 (Y, A, B, S0);

	output Y;
	input A, B, S0;


	buf (Y, 1'b0);


	specify
		if (B)
			(A => Y) = 0;
		if (~B)
			(A => Y) = 0;
		ifnone (A => Y) = 0;
		if (A)
			(B => Y) = 0;
		if (~A)
			(B => Y) = 0;
		ifnone (B => Y) = 0;
		(posedge S0 => (Y:S0)) = 0;
		(negedge S0 => (Y:S0)) = 0;
	endspecify
endmodule