data/full_repos/permissive/119387855/mips_core_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_core_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #30 clock=~clock;\n  ^\n%Error: data/full_repos/permissive/119387855/mips_core_testbench.v:49: Unsupported or unknown PLI call: $writememb\n  $writememb("../../res_registers.mem", test.registers.registers);\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/119387855/mips_core_testbench.v:50: Unsupported or unknown PLI call: $writememb\n  $writememb("../../res_data.mem", test.memory.data_mem);\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 30 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_core_testbench ();
	reg clock;
	wire result;

	mips_core test(clock);

	initial clock = 0;



	initial begin
		#30 clock=~clock; 
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock; 
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock; 
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		

	end



	initial begin
		$writememb("../../res_registers.mem", test.registers.registers);
		$writememb("../../res_data.mem", test.memory.data_mem);
	end

endmodule
module mips_core_testbench ();

	reg clock;
	wire result;

	mips_core test(clock);

	initial clock = 0;



	initial begin
		#30 clock=~clock; 
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock; 
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock; 
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		#30 clock=~clock;
		

	end



	initial begin
		$writememb("../../res_registers.mem", test.registers.registers);
		$writememb("../../res_data.mem", test.memory.data_mem);
	end

endmodule