data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/butt.v
data/verilator_xmls/377b2d4d-c8c3-4cfa-9f58-4b54d7248e7a.xml
module butt(
	input clk,
	input rst_n,
	input buttonpress,
	
	output button
);

assign button = buttonpress;


reg [31:0] cycle_count;

reg valid;
reg sgcycle;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		valid<=0;
		cycle_count<=0;
		sgcycle<=0;
	end
	else
	begin
		if(buttonpress)
		begin
			if(cycle_count==32'd999)
			begin
				if(!sgcycle)
				begin
					valid<=1;
					sgcycle<=1;
				end
				else
				begin
					valid<=0;
				end
			end
			else
			begin
				cycle_count<=cycle_count+32'h1;
			end
		end
		else
		begin
			cycle_count<=32'h0;
			valid<=0;
			sgcycle<=0;
		end
	end

end


endmodule
module butt(
	input clk,
	input rst_n,
	input buttonpress,
	
	output button
);


assign button = buttonpress;


reg [31:0] cycle_count;

reg valid;
reg sgcycle;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		valid<=0;
		cycle_count<=0;
		sgcycle<=0;
	end
	else
	begin
		if(buttonpress)
		begin
			if(cycle_count==32'd999)
			begin
				if(!sgcycle)
				begin
					valid<=1;
					sgcycle<=1;
				end
				else
				begin
					valid<=0;
				end
			end
			else
			begin
				cycle_count<=cycle_count+32'h1;
			end
		end
		else
		begin
			cycle_count<=32'h0;
			valid<=0;
			sgcycle<=0;
		end
	end

end


endmodule