data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sources_1/new/TempImgCreator.v
data/verilator_xmls/0aa77866-6d0e-4cea-8caf-01a83ba4ed28.xml
module TempImgCreator(
    input CLK,
    output CLKOUT,
    output reg [7:0] dataOut,
    
    input reset
    );
    
    reg[7:0] scaler;
    
    assign CLKOUT = CLK;
    
    always@(posedge CLK) begin
        if(reset) begin
            scaler <= 8'h00;
            dataOut <= scaler;
        end
        else begin
            scaler <= scaler + 1;
            dataOut <= scaler;
        end 
    end
endmodule
module TempImgCreator(
    input CLK,
    output CLKOUT,
    output reg [7:0] dataOut,
    
    input reset
    );

    
    reg[7:0] scaler;
    
    assign CLKOUT = CLK;
    
    always@(posedge CLK) begin
        if(reset) begin
            scaler <= 8'h00;
            dataOut <= scaler;
        end
        else begin
            scaler <= scaler + 1;
            dataOut <= scaler;
        end 
    end
endmodule