data/full_repos/permissive/137547257/ALU_Nbit.v
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1: b"%Error: data/full_repos/permissive/137547257/ALU_Nbit.v:64: syntax error, unexpected '#', expecting ',' or ';'\n Mux4to1Nbit  mux_logic #(N=N)(Binternal, FS[2:1], FS[0], FS[1], FS[2], FS[3]);  \n                        ^\n%Error: Exiting due to 1 error(s)\n"
module ALU_Nbit #(parameter N=16)
(	input  wire Cin, 
	input  wire [N-1:0] A, 
	input  wire [N-1:0] B, 
	input  wire   [4:0] FS,
	output wire Cout, 
	output wire   [3:0] status,
	output wire [N-1:0] Fout
	);





	wire             oVerflow, CarryOut, NegativeNum, Zero ;
	assign status = {oVerflow, CarryOut, NegativeNum, Zero};
	
	assign oVerflow = ~(Ainternal[N-1] ^ Binternal[N-1])  &  (F[N-1] ^ Ainternal[N-1]) ;

	assign NegativeNum = F[N-1];
	assign Zero = ~| Fout ;




	wire [N-1:0] Ainternal, Binternal;

	assign Ainternal = FS[0] ? ~A : A;


	Mux4to1Nbit  mux_logic #(N=N)(Binternal, FS[2:1], FS[0], FS[1], FS[2], FS[3]);






	always @ (posedge clk, posedge reset) begin
		case ( FS[4:0] )

			5'd1 : Fout = A + B;
			5'd2 : Fout = A + ~B + 1'b1;
			5'd3 : Fout = A - 1'b1;
			5'd4 : Fout =~A + 1'b1;
			5'd5 : Fout = A ^ B;
			5'd6 : Fout = A + B + C0;
			5'd7 : Fout = A + 1'b1;



			5'd0  : Fout = 'b0;
			5'd8  : Fout = 'hFFFF;
			5'd9  : Fout = ~A ;
			5'd10 : Fout =  A & B ;
			5'd11 : Fout =  A | B ;
			5'd12 : Fout =  A ;
			5'd16 : Fout =  B ;


			5'd13 : Fout = A >> 1 ;
			5'd14 : Fout = A << 1 ;
			5'd15 : Fout = A >>> 1;

			default: Fout = 16'b1000_0000_0000_0000;
		endcase
	end

	


	
endmodule
module ALU_Nbit #(parameter N=16)
(	input  wire Cin, 
	input  wire [N-1:0] A, 
	input  wire [N-1:0] B, 
	input  wire   [4:0] FS,
	output wire Cout, 
	output wire   [3:0] status,
	output wire [N-1:0] Fout
	);






	wire             oVerflow, CarryOut, NegativeNum, Zero ;
	assign status = {oVerflow, CarryOut, NegativeNum, Zero};
	
	assign oVerflow = ~(Ainternal[N-1] ^ Binternal[N-1])  &  (F[N-1] ^ Ainternal[N-1]) ;

	assign NegativeNum = F[N-1];
	assign Zero = ~| Fout ;




	wire [N-1:0] Ainternal, Binternal;

	assign Ainternal = FS[0] ? ~A : A;


	Mux4to1Nbit  mux_logic #(N=N)(Binternal, FS[2:1], FS[0], FS[1], FS[2], FS[3]);






	always @ (posedge clk, posedge reset) begin
		case ( FS[4:0] )

			5'd1 : Fout = A + B;
			5'd2 : Fout = A + ~B + 1'b1;
			5'd3 : Fout = A - 1'b1;
			5'd4 : Fout =~A + 1'b1;
			5'd5 : Fout = A ^ B;
			5'd6 : Fout = A + B + C0;
			5'd7 : Fout = A + 1'b1;



			5'd0  : Fout = 'b0;
			5'd8  : Fout = 'hFFFF;
			5'd9  : Fout = ~A ;
			5'd10 : Fout =  A & B ;
			5'd11 : Fout =  A | B ;
			5'd12 : Fout =  A ;
			5'd16 : Fout =  B ;


			5'd13 : Fout = A >> 1 ;
			5'd14 : Fout = A << 1 ;
			5'd15 : Fout = A >>> 1;

			default: Fout = 16'b1000_0000_0000_0000;
		endcase
	end

	


	
endmodule