data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:25: Define or directive not defined: \'`ADDR_W\'\n  input [`ADDR_W - 1:0] i_req_addr;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:26: Define or directive not defined: \'`INSTR_W\'\n  output reg [`INSTR_W - 1:0] o_res_data;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:29: Define or directive not defined: \'`INSTR_W\'\n  reg [`INSTR_W - 1:0] read_instr;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:33: Define or directive not defined: \'`INSTR_W\'\n  reg [`INSTR_W - 1:0] r_mem [0:INSTR_MAX - 1];\n       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:40: Define or directive not defined: \'`INSTR_W\'\n  wire [`INSTR_W - 3:0] word_addr = i_req_addr[`INSTR_W - 1:2];\n        ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:40: Define or directive not defined: \'`INSTR_W\'\n  wire [`INSTR_W - 3:0] word_addr = i_req_addr[`INSTR_W - 1:2];\n                                               ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:46: Define or directive not defined: \'`FUNCT3_ADD\'\n      o_res_data <= {12\'h000, 5\'d0, `FUNCT3_ADD, 5\'d0, `OPCODE_ITYPE};\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:46: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      o_res_data <= {12\'h000, 5\'d0, `FUNCT3_ADD, 5\'d0, `OPCODE_ITYPE};\n                                               ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/instruction_memory.v:46: Define or directive not defined: \'`OPCODE_ITYPE\'\n      o_res_data <= {12\'h000, 5\'d0, `FUNCT3_ADD, 5\'d0, `OPCODE_ITYPE};\n                                                       ^~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module instruction_memory(
  clk,

  i_req_addr,
  
  o_res_data
);

  parameter INSTR_MAX = 256;
  parameter INSTR_FILE = "instr.txt";
  parameter DUMP_INSTR = 0;
  parameter DUMP_FILE = "a.vcd";

  input clk;

  input [`ADDR_W - 1:0] i_req_addr;
  output reg [`INSTR_W - 1:0] o_res_data;

  integer instr_file;
  reg [`INSTR_W - 1:0] read_instr;
  integer i;
  integer fscanf_ret;

  reg [`INSTR_W - 1:0] r_mem [0:INSTR_MAX - 1];

  initial begin: load_instr
    $readmemh(INSTR_FILE, r_mem, 0, INSTR_MAX - 1);
  end


  wire [`INSTR_W - 3:0] word_addr = i_req_addr[`INSTR_W - 1:2];

  always@(posedge clk) begin
    if(word_addr < INSTR_MAX) begin
      o_res_data <= r_mem[word_addr];
    end else begin
      o_res_data <= `NOP;
    end
  end

endmodule
module instruction_memory(
  clk,

  i_req_addr,
  
  o_res_data
);


  parameter INSTR_MAX = 256;
  parameter INSTR_FILE = "instr.txt";
  parameter DUMP_INSTR = 0;
  parameter DUMP_FILE = "a.vcd";

  input clk;

  input [`ADDR_W - 1:0] i_req_addr;
  output reg [`INSTR_W - 1:0] o_res_data;

  integer instr_file;
  reg [`INSTR_W - 1:0] read_instr;
  integer i;
  integer fscanf_ret;

  reg [`INSTR_W - 1:0] r_mem [0:INSTR_MAX - 1];

  initial begin: load_instr
    $readmemh(INSTR_FILE, r_mem, 0, INSTR_MAX - 1);
  end


  wire [`INSTR_W - 3:0] word_addr = i_req_addr[`INSTR_W - 1:2];

  always@(posedge clk) begin
    if(word_addr < INSTR_MAX) begin
      o_res_data <= r_mem[word_addr];
    end else begin
      o_res_data <= `NOP;
    end
  end

endmodule