data/full_repos/permissive/143278/ivltests/pr1581580.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1581580.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q !== 2\'b00) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1581580.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q !== 2\'b01) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1581580.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 d = 2\'b10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1581580.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q !== 2\'b01) begin\n      ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module unit_latch(output reg Q, input wire D, input wire G);

   always @*
     if (G) Q = D;

endmodule
module unit_latch(output reg Q, input wire D, input wire G);


   always @*
     if (G) Q = D;

endmodule