data/full_repos/permissive/207835546/DFF/sync_test.v
 line:49: before: "$"
1: b'%Error: data/full_repos/permissive/207835546/DFF/sync_test.v:2: Cannot find include file: sync.v\n`include"sync.v" \n        ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207835546/DFF,data/full_repos/permissive/207835546/sync.v\n             data/full_repos/permissive/207835546/DFF,data/full_repos/permissive/207835546/sync.v.v\n             data/full_repos/permissive/207835546/DFF,data/full_repos/permissive/207835546/sync.v.sv\n             sync.v\n             sync.v.v\n             sync.v.sv\n             obj_dir/sync.v\n             obj_dir/sync.v.v\n             obj_dir/sync.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/207835546/DFF/sync_test.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #100 clk=~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/207835546/DFF/sync_test.v:25: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("sync_DFF.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/207835546/DFF/sync_test.v:26: Unsupported or unknown PLI call: $dumpvars\n$dumpvars;\n^~~~~~~~~\n%Error: data/full_repos/permissive/207835546/DFF/sync_test.v:28: Unsupported or unknown PLI call: $monitor\n$monitor("Clock=%d, D=%d, Q=%d", clk,D,Q);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/207835546/DFF/sync_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n#200 D<=0;reset=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/207835546/DFF/sync_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n#200 D<=0; reset=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/207835546/DFF/sync_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n#200 D<=1; reset=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/207835546/DFF/sync_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n#40 $finish;\n^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n'
module tb_dff();

reg D,clk,reset;
wire Q;

integer i;

dff dut (D,clk,reset,Q);

initial


clk=0;

always 
    #100 clk=~clk;



initial begin 

$dumpfile("sync_DFF.vcd");
$dumpvars;

$monitor("Clock=%d, D=%d, Q=%d", clk,D,Q);

D<=1;reset=1;
#200 D<=0;reset=1;
#200 D<=0; reset=0;
#200 D<=1; reset=0;
#40 $finish;
end 

endmodule
module tb_dff();


reg D,clk,reset;
wire Q;

integer i;

dff dut (D,clk,reset,Q);

initial


clk=0;

always 
    #100 clk=~clk;



initial begin 

$dumpfile("sync_DFF.vcd");
$dumpvars;

$monitor("Clock=%d, D=%d, Q=%d", clk,D,Q);

D<=1;reset=1;
#200 D<=0;reset=1;
#200 D<=0; reset=0;
#200 D<=1; reset=0;
#40 $finish;
end 

endmodule