data/full_repos/permissive/173670949/dds-synth/uart_rx.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/1a47a82c-184e-47e0-9114-8c992e33b430.xml
module uart_rx 
(
    input        SER_CLK,
    input        RX_SERIAL,
    output       RX_DV,
    output [7:0] RX_BYTE
);

    parameter F_CLK = 12_000_000;
    parameter UART_BAUD    = 9600;


    parameter CLKS_PER_BIT = (F_CLK / UART_BAUD);

    parameter IDLE    = 3'b000;
    parameter START   = 3'b001;
    parameter DATA    = 3'b010;
    parameter STOP    = 3'b011;
    parameter CLEANUP = 3'b100;



    reg [31:0] Clock_Count = 0; 
    reg [2:0]  Bit_Idx     = 0;
    reg [7:0]  Rx_Byte     = 0;
    reg        Rx_Dv       = 0;
    reg [2:0]  State       = 0;
    reg        Rx_Data     = 1;

    always @(posedge SER_CLK) begin
        Rx_Data <= RX_SERIAL;
    end

    always @(posedge SER_CLK) begin
        case (State)
            IDLE: begin
                Rx_Dv       <= 1'b0;
                Clock_Count <= 0;
                Bit_Idx     <= 0;


                if (Rx_Data == 0)
                    State <= START;
                else
                    State <= IDLE;
            end

            START: begin
                if (Clock_Count == (CLKS_PER_BIT-1)/2) begin
                    if (Rx_Data == 0) begin
                        Clock_Count <= 0;
                        State       <= DATA;
                        Rx_Byte     <= 0;
                    end
                end
                else begin
                    Clock_Count <= Clock_Count + 1;
                    State       <= START;
                end
            end

            DATA: begin
                if (Clock_Count < CLKS_PER_BIT - 1) begin
                    Clock_Count <= Clock_Count + 1;
                    State       <= DATA;
                end
                else begin
                    Clock_Count      <= 0;
                    Rx_Byte[Bit_Idx] <= Rx_Data;

                    if (Bit_Idx < 7) begin
                        Bit_Idx <= Bit_Idx + 1;
                        State   <= DATA;
                    end
                    else begin
                        Bit_Idx <= 0;
                        State   <= STOP;
                    end
                end
            end

            STOP: begin
                if (Clock_Count < CLKS_PER_BIT - 1) begin
                    Clock_Count <= Clock_Count + 1;
                    State       <= STOP;
                end
                else begin
                    Rx_Dv       <= 1'b1;
                    Clock_Count <= 0;
                    State       <= CLEANUP;
                end
            end

            CLEANUP: begin
                State <= IDLE;
                Rx_Dv <= 1'b0;
            end

            default:
                State <= IDLE;
        endcase
    end
 
    assign RX_DV   = Rx_Dv;
    assign RX_BYTE = Rx_Byte;

endmodule
module uart_rx 
(
    input        SER_CLK,
    input        RX_SERIAL,
    output       RX_DV,
    output [7:0] RX_BYTE
);


    parameter F_CLK = 12_000_000;
    parameter UART_BAUD    = 9600;


    parameter CLKS_PER_BIT = (F_CLK / UART_BAUD);

    parameter IDLE    = 3'b000;
    parameter START   = 3'b001;
    parameter DATA    = 3'b010;
    parameter STOP    = 3'b011;
    parameter CLEANUP = 3'b100;



    reg [31:0] Clock_Count = 0; 
    reg [2:0]  Bit_Idx     = 0;
    reg [7:0]  Rx_Byte     = 0;
    reg        Rx_Dv       = 0;
    reg [2:0]  State       = 0;
    reg        Rx_Data     = 1;

    always @(posedge SER_CLK) begin
        Rx_Data <= RX_SERIAL;
    end

    always @(posedge SER_CLK) begin
        case (State)
            IDLE: begin
                Rx_Dv       <= 1'b0;
                Clock_Count <= 0;
                Bit_Idx     <= 0;


                if (Rx_Data == 0)
                    State <= START;
                else
                    State <= IDLE;
            end

            START: begin
                if (Clock_Count == (CLKS_PER_BIT-1)/2) begin
                    if (Rx_Data == 0) begin
                        Clock_Count <= 0;
                        State       <= DATA;
                        Rx_Byte     <= 0;
                    end
                end
                else begin
                    Clock_Count <= Clock_Count + 1;
                    State       <= START;
                end
            end

            DATA: begin
                if (Clock_Count < CLKS_PER_BIT - 1) begin
                    Clock_Count <= Clock_Count + 1;
                    State       <= DATA;
                end
                else begin
                    Clock_Count      <= 0;
                    Rx_Byte[Bit_Idx] <= Rx_Data;

                    if (Bit_Idx < 7) begin
                        Bit_Idx <= Bit_Idx + 1;
                        State   <= DATA;
                    end
                    else begin
                        Bit_Idx <= 0;
                        State   <= STOP;
                    end
                end
            end

            STOP: begin
                if (Clock_Count < CLKS_PER_BIT - 1) begin
                    Clock_Count <= Clock_Count + 1;
                    State       <= STOP;
                end
                else begin
                    Rx_Dv       <= 1'b1;
                    Clock_Count <= 0;
                    State       <= CLEANUP;
                end
            end

            CLEANUP: begin
                State <= IDLE;
                Rx_Dv <= 1'b0;
            end

            default:
                State <= IDLE;
        endcase
    end
 
    assign RX_DV   = Rx_Dv;
    assign RX_BYTE = Rx_Byte;

endmodule