data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo16n.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo16n.v:104: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'rd_en_i\' generates 1 bits.\n                                                                                    : ... In instance fifo16n\nassign next_rd_ptr = !rempty_o ? bin_rd_ptr + rd_en_i : bin_rd_ptr;\n                                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo16n.v:123: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'wr_en_i\' generates 1 bits.\n                                                                                    : ... In instance fifo16n\nassign next_wr_ptr = !wfull_o ? bin_wr_ptr + wr_en_i : bin_wr_ptr;\n                                           ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo16n.v:177: Cannot find file containing module: \'bin2gray\'\nbin2gray B2G0 (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo,data/full_repos/permissive/20430511/bin2gray\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo,data/full_repos/permissive/20430511/bin2gray.v\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo,data/full_repos/permissive/20430511/bin2gray.sv\n             bin2gray\n             bin2gray.v\n             bin2gray.sv\n             obj_dir/bin2gray\n             obj_dir/bin2gray.v\n             obj_dir/bin2gray.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo16n.v:184: Cannot find file containing module: \'bin2gray\'\nbin2gray B2G1 (\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module fifo16n (
	reset_ni,
	
	rd_clk_i,
	rd_en_i,
	rd_data_o,
	
	wr_clk_i,
	wr_en_i,
	wr_data_i,
	
	rempty_o,
	wfull_o
);

parameter	WIDTH	= 8;

input	reset_ni;

input	rd_clk_i;
input	rd_en_i;
output	[WIDTH-1:0]	rd_data_o;

input	wr_clk_i;
input	wr_en_i;
input	[WIDTH-1:0]	wr_data_i;

output	rempty_o;
output	wfull_o;


reg	[`ADMSB:0]	bin_rd_ptr	= 0;
reg	[`ADMSB:0]	bin_wr_ptr	= 0;

wire	[`ADMSB:0]	next_rd_ptr;
wire	[`ADMSB:0]	next_wr_ptr;

wire	[`ADMSB:0]	gray_rd_ptr_w;
wire	[`ADMSB:0]	gray_wr_ptr_w;

reg	[`ADMSB:0]	gray_rd_ptr_r	= 0;
reg	[`ADMSB:0]	gray_wr_ptr_r	= 0;

wire	aempty_n;
wire	afull_n;
reg	rempty2	= 0;
reg	wfull2	= 0;
reg	rempty_o	= 1;
reg	wfull_o		= 0;









reg    [WIDTH-1:0]  mem [0:15];



always @ (posedge wr_clk_i)
begin
	if (wr_en_i && reset_ni)
		mem [gray_wr_ptr_r [`ADMSB:0]]	<= wr_data_i;
end

assign	rd_data_o	= mem [gray_rd_ptr_r [`ADMSB:0]];






assign	next_rd_ptr	= !rempty_o ? bin_rd_ptr + rd_en_i : bin_rd_ptr;
always @(posedge rd_clk_i or negedge reset_ni)
begin
	if (!reset_ni)
	begin
		bin_rd_ptr	<= 0;
		gray_rd_ptr_r	<= 0;
	end
	else
	begin



		gray_rd_ptr_r	<= gray_rd_ptr_w;
		bin_rd_ptr	<= next_rd_ptr;
	end
end


assign	next_wr_ptr	= !wfull_o ? bin_wr_ptr + wr_en_i : bin_wr_ptr;
always @(posedge wr_clk_i or negedge reset_ni)
begin
	if (!reset_ni)
	begin
		bin_wr_ptr	<= 0;
		gray_wr_ptr_r	<= 0;
	end
	else
	begin
		gray_wr_ptr_r	<= gray_wr_ptr_w;
		bin_wr_ptr	<= next_wr_ptr;
	end
end













reg	direction	= 0;
wire	dirset_n	= ~((gray_wr_ptr_r [`ADMSB] ^ gray_rd_ptr_r [`ADMSB-1]) & ~(gray_wr_ptr_r [`ADMSB-1] ^ gray_rd_ptr_r [`ADMSB]));
wire	dirclr_n	= ~((~(gray_wr_ptr_r [`ADMSB] ^ gray_rd_ptr_r [`ADMSB-1]) & (gray_wr_ptr_r [`ADMSB-1] ^ gray_rd_ptr_r [`ADMSB])) | ~reset_ni);

always @(negedge dirset_n or negedge dirclr_n)
	if	(!dirclr_n)	direction <= 1'b0;
	else			direction <= 1'b1;

assign	aempty_n	= ~((gray_wr_ptr_r == gray_rd_ptr_r) && !direction);
assign	afull_n		= ~((gray_wr_ptr_r == gray_rd_ptr_r) && direction);



always @(posedge rd_clk_i or negedge aempty_n)
	if (!aempty_n)	{rempty_o, rempty2}	<= 2'b11;
	else		{rempty_o, rempty2}	<= {rempty2, ~aempty_n};



always @(posedge wr_clk_i or negedge reset_ni or negedge afull_n)
	if	(!reset_ni)	{wfull_o, wfull2}	<= 2'b00;
	else if	(!afull_n)	{wfull_o, wfull2}	<= 2'b11;
	else			{wfull_o, wfull2}	<= {wfull2, ~afull_n};



defparam	B2G0.WIDTH	= `ADBITS;
bin2gray B2G0 (
	.bin_i	(next_rd_ptr),
	.gray_o	(gray_rd_ptr_w)
);


defparam	B2G1.WIDTH	= `ADBITS;
bin2gray B2G1 (
	.bin_i	(next_wr_ptr),
	.gray_o	(gray_wr_ptr_w)
);


endmodule
module fifo16n (
	reset_ni,
	
	rd_clk_i,
	rd_en_i,
	rd_data_o,
	
	wr_clk_i,
	wr_en_i,
	wr_data_i,
	
	rempty_o,
	wfull_o
);


parameter	WIDTH	= 8;

input	reset_ni;

input	rd_clk_i;
input	rd_en_i;
output	[WIDTH-1:0]	rd_data_o;

input	wr_clk_i;
input	wr_en_i;
input	[WIDTH-1:0]	wr_data_i;

output	rempty_o;
output	wfull_o;


reg	[`ADMSB:0]	bin_rd_ptr	= 0;
reg	[`ADMSB:0]	bin_wr_ptr	= 0;

wire	[`ADMSB:0]	next_rd_ptr;
wire	[`ADMSB:0]	next_wr_ptr;

wire	[`ADMSB:0]	gray_rd_ptr_w;
wire	[`ADMSB:0]	gray_wr_ptr_w;

reg	[`ADMSB:0]	gray_rd_ptr_r	= 0;
reg	[`ADMSB:0]	gray_wr_ptr_r	= 0;

wire	aempty_n;
wire	afull_n;
reg	rempty2	= 0;
reg	wfull2	= 0;
reg	rempty_o	= 1;
reg	wfull_o		= 0;









reg    [WIDTH-1:0]  mem [0:15];



always @ (posedge wr_clk_i)
begin
	if (wr_en_i && reset_ni)
		mem [gray_wr_ptr_r [`ADMSB:0]]	<= wr_data_i;
end

assign	rd_data_o	= mem [gray_rd_ptr_r [`ADMSB:0]];






assign	next_rd_ptr	= !rempty_o ? bin_rd_ptr + rd_en_i : bin_rd_ptr;
always @(posedge rd_clk_i or negedge reset_ni)
begin
	if (!reset_ni)
	begin
		bin_rd_ptr	<= 0;
		gray_rd_ptr_r	<= 0;
	end
	else
	begin



		gray_rd_ptr_r	<= gray_rd_ptr_w;
		bin_rd_ptr	<= next_rd_ptr;
	end
end


assign	next_wr_ptr	= !wfull_o ? bin_wr_ptr + wr_en_i : bin_wr_ptr;
always @(posedge wr_clk_i or negedge reset_ni)
begin
	if (!reset_ni)
	begin
		bin_wr_ptr	<= 0;
		gray_wr_ptr_r	<= 0;
	end
	else
	begin
		gray_wr_ptr_r	<= gray_wr_ptr_w;
		bin_wr_ptr	<= next_wr_ptr;
	end
end













reg	direction	= 0;
wire	dirset_n	= ~((gray_wr_ptr_r [`ADMSB] ^ gray_rd_ptr_r [`ADMSB-1]) & ~(gray_wr_ptr_r [`ADMSB-1] ^ gray_rd_ptr_r [`ADMSB]));
wire	dirclr_n	= ~((~(gray_wr_ptr_r [`ADMSB] ^ gray_rd_ptr_r [`ADMSB-1]) & (gray_wr_ptr_r [`ADMSB-1] ^ gray_rd_ptr_r [`ADMSB])) | ~reset_ni);

always @(negedge dirset_n or negedge dirclr_n)
	if	(!dirclr_n)	direction <= 1'b0;
	else			direction <= 1'b1;

assign	aempty_n	= ~((gray_wr_ptr_r == gray_rd_ptr_r) && !direction);
assign	afull_n		= ~((gray_wr_ptr_r == gray_rd_ptr_r) && direction);



always @(posedge rd_clk_i or negedge aempty_n)
	if (!aempty_n)	{rempty_o, rempty2}	<= 2'b11;
	else		{rempty_o, rempty2}	<= {rempty2, ~aempty_n};



always @(posedge wr_clk_i or negedge reset_ni or negedge afull_n)
	if	(!reset_ni)	{wfull_o, wfull2}	<= 2'b00;
	else if	(!afull_n)	{wfull_o, wfull2}	<= 2'b11;
	else			{wfull_o, wfull2}	<= {wfull2, ~afull_n};



defparam	B2G0.WIDTH	= `ADBITS;
bin2gray B2G0 (
	.bin_i	(next_rd_ptr),
	.gray_o	(gray_rd_ptr_w)
);


defparam	B2G1.WIDTH	= `ADBITS;
bin2gray B2G1 (
	.bin_i	(next_wr_ptr),
	.gray_o	(gray_wr_ptr_w)
);


endmodule