data/full_repos/permissive/211878730/atlys/practice/counter4.v
data/verilator_xmls/2bafb2b6-e603-43f7-8584-96c33bca4aa4.xml
module counter4(
    input  wire clk,
    output wire [1:0] count
    );

    reg [1:0] count_down;

    always @(posedge clk) begin
        if (count_down >= 2'b11) begin
            count_down <= 2'b00;
        end else begin
            count_down <= count_down + 1'b1;
        end
    end

    assign count = count_down;
endmodule
module counter4(
    input  wire clk,
    output wire [1:0] count
    );


    reg [1:0] count_down;

    always @(posedge clk) begin
        if (count_down >= 2'b11) begin
            count_down <= 2'b00;
        end else begin
            count_down <= count_down + 1'b1;
        end
    end

    assign count = count_down;
endmodule