data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/settings_bus_timed_2clk.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/settings_bus_timed_2clk.v:91: Cannot find file containing module: 'axi_fifo_2clk'\n  axi_fifo_2clk #(\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/axi_fifo_2clk\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/axi_fifo_2clk.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/axi_fifo_2clk.sv\n             axi_fifo_2clk\n             axi_fifo_2clk.v\n             axi_fifo_2clk.sv\n             obj_dir/axi_fifo_2clk\n             obj_dir/axi_fifo_2clk.v\n             obj_dir/axi_fifo_2clk.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/settings_bus_timed_2clk.v:110: Cannot find file containing module: 'time_compare'\n  time_compare time_compare (\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/settings_bus_timed_2clk.v:118: Cannot find file containing module: 'axi_fifo_2clk'\n  axi_fifo_2clk #(\n  ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module settings_bus_timed_2clk #(
  parameter SR_AWIDTH     = 8,
  parameter SR_DWIDTH     = 32,
  parameter RB_AWIDTH     = 8,
  parameter RB_DWIDTH     = 64,
  parameter TIMED_CMDS_EN = 0
) (
  input                  sb_clk,
  input                  sb_rst,
  input                  tb_clk,
  input                  tb_rst,

  input  [63:0]          vita_time,
                         
  input                  s_set_stb,
  input  [SR_AWIDTH-1:0] s_set_addr,
  input  [SR_DWIDTH-1:0] s_set_data,
  input                  s_set_has_time,
  input  [63:0]          s_set_time,
  output                 s_set_pending,
  input  [RB_AWIDTH-1:0] s_rb_addr,
  output                 s_rb_stb,
  output [RB_DWIDTH-1:0] s_rb_data,

  output                 m_set_stb,
  output [SR_AWIDTH-1:0] m_set_addr,
  output [SR_DWIDTH-1:0] m_set_data,
  output                 m_set_has_time,
  output [63:0]          m_set_time,
  input                  m_set_pending,
  output [RB_AWIDTH-1:0] m_rb_addr,
  input                  m_rb_stb,
  input  [RB_DWIDTH-1:0] m_rb_data
);


  localparam [2:0] ST_IDLE        = 3'd0;
  localparam [2:0] ST_SET_ISSUED  = 3'd1;
  localparam [2:0] ST_SET_PENDING = 3'd2;
  localparam [2:0] ST_RB_PENDING  = 3'd3;
  localparam [2:0] ST_RB_DONE     = 3'd4;
  
  wire rb_valid;


  reg [2:0] in_state = ST_IDLE;
  always @(posedge sb_clk) begin
    if (sb_rst) begin
      in_state <= ST_IDLE;
    end else begin
      case (in_state)
        ST_IDLE: begin
          if (s_set_stb) begin
            in_state <= ST_SET_PENDING;
          end
        end
        ST_SET_PENDING: begin
          if (rb_valid) begin
            in_state <= ST_RB_DONE;
          end
        end
        ST_RB_DONE: begin
          in_state <= ST_IDLE;
        end
        default: begin
          in_state <= ST_IDLE;
        end
      endcase
    end
  end
  assign s_set_pending = (in_state == ST_SET_PENDING);
  assign s_rb_stb = (in_state == ST_RB_DONE);




  wire set_pending, set_finished;
  axi_fifo_2clk #(
    .WIDTH(SR_AWIDTH+SR_DWIDTH+1+64+RB_AWIDTH), .SIZE(0)
  ) sb_2clk_fifo_i (
    .i_aclk(sb_clk), .reset(sb_rst),
    .i_tdata({s_set_addr, s_set_data, s_set_has_time, s_set_time, s_rb_addr}),
    .i_tvalid(s_set_stb), .i_tready(),
    .o_aclk(tb_clk),
    .o_tdata({m_set_addr, m_set_data, m_set_has_time, m_set_time, m_rb_addr}),
    .o_tvalid(set_pending), .o_tready(set_finished)
  );




  wire now, late;
  wire go = ((TIMED_CMDS_EN == 1) && m_set_has_time) ? (now | late) : 1'b1;



  time_compare time_compare (
    .clk(tb_clk), .reset(tb_rst),
    .time_now(vita_time), .trigger_time(m_set_time),
    .now(now), .early(), .late(late), .too_early()
  );


  reg [RB_DWIDTH-1:0] cached_rb_data;
  axi_fifo_2clk #(
    .WIDTH(RB_DWIDTH), .SIZE(0)
  ) rbdata_2clk_fifo_i (
    .reset(tb_rst),
    .i_aclk(tb_clk), .i_tdata(cached_rb_data), .i_tvalid(set_finished), .i_tready(),
    .o_aclk(sb_clk), .o_tdata(s_rb_data), .o_tvalid(rb_valid), .o_tready(s_rb_stb)
  );


  reg [2:0] out_state = ST_IDLE;
  always @(posedge tb_clk) begin
    if (tb_rst) begin
      out_state <= ST_IDLE;
    end else begin
      case (out_state)
        ST_IDLE: begin
          if (go & set_pending) begin
            out_state <= ST_SET_ISSUED;
          end
        end
        ST_SET_ISSUED: begin
          out_state <= ST_SET_PENDING;
        end
        ST_SET_PENDING: begin
          if (~m_set_pending) begin
            if (m_rb_stb) begin
              out_state <= ST_RB_DONE;
              cached_rb_data <= m_rb_data;
            end else begin
              out_state <= ST_RB_PENDING;
            end
          end
        end
        ST_RB_PENDING: begin
          if (m_rb_stb) begin
            out_state <= ST_RB_DONE;
            cached_rb_data <= m_rb_data;
          end
        end
        ST_RB_DONE: begin
          out_state <= ST_IDLE;
        end
        default: begin
          out_state <= ST_IDLE;
        end
      endcase
    end
  end

  assign m_set_stb = (out_state == ST_SET_ISSUED);
  assign set_finished = (out_state == ST_RB_DONE);

endmodule
module settings_bus_timed_2clk #(
  parameter SR_AWIDTH     = 8,
  parameter SR_DWIDTH     = 32,
  parameter RB_AWIDTH     = 8,
  parameter RB_DWIDTH     = 64,
  parameter TIMED_CMDS_EN = 0
) (
  input                  sb_clk,
  input                  sb_rst,
  input                  tb_clk,
  input                  tb_rst,

  input  [63:0]          vita_time,
                         
  input                  s_set_stb,
  input  [SR_AWIDTH-1:0] s_set_addr,
  input  [SR_DWIDTH-1:0] s_set_data,
  input                  s_set_has_time,
  input  [63:0]          s_set_time,
  output                 s_set_pending,
  input  [RB_AWIDTH-1:0] s_rb_addr,
  output                 s_rb_stb,
  output [RB_DWIDTH-1:0] s_rb_data,

  output                 m_set_stb,
  output [SR_AWIDTH-1:0] m_set_addr,
  output [SR_DWIDTH-1:0] m_set_data,
  output                 m_set_has_time,
  output [63:0]          m_set_time,
  input                  m_set_pending,
  output [RB_AWIDTH-1:0] m_rb_addr,
  input                  m_rb_stb,
  input  [RB_DWIDTH-1:0] m_rb_data
);



  localparam [2:0] ST_IDLE        = 3'd0;
  localparam [2:0] ST_SET_ISSUED  = 3'd1;
  localparam [2:0] ST_SET_PENDING = 3'd2;
  localparam [2:0] ST_RB_PENDING  = 3'd3;
  localparam [2:0] ST_RB_DONE     = 3'd4;
  
  wire rb_valid;


  reg [2:0] in_state = ST_IDLE;
  always @(posedge sb_clk) begin
    if (sb_rst) begin
      in_state <= ST_IDLE;
    end else begin
      case (in_state)
        ST_IDLE: begin
          if (s_set_stb) begin
            in_state <= ST_SET_PENDING;
          end
        end
        ST_SET_PENDING: begin
          if (rb_valid) begin
            in_state <= ST_RB_DONE;
          end
        end
        ST_RB_DONE: begin
          in_state <= ST_IDLE;
        end
        default: begin
          in_state <= ST_IDLE;
        end
      endcase
    end
  end
  assign s_set_pending = (in_state == ST_SET_PENDING);
  assign s_rb_stb = (in_state == ST_RB_DONE);




  wire set_pending, set_finished;
  axi_fifo_2clk #(
    .WIDTH(SR_AWIDTH+SR_DWIDTH+1+64+RB_AWIDTH), .SIZE(0)
  ) sb_2clk_fifo_i (
    .i_aclk(sb_clk), .reset(sb_rst),
    .i_tdata({s_set_addr, s_set_data, s_set_has_time, s_set_time, s_rb_addr}),
    .i_tvalid(s_set_stb), .i_tready(),
    .o_aclk(tb_clk),
    .o_tdata({m_set_addr, m_set_data, m_set_has_time, m_set_time, m_rb_addr}),
    .o_tvalid(set_pending), .o_tready(set_finished)
  );




  wire now, late;
  wire go = ((TIMED_CMDS_EN == 1) && m_set_has_time) ? (now | late) : 1'b1;



  time_compare time_compare (
    .clk(tb_clk), .reset(tb_rst),
    .time_now(vita_time), .trigger_time(m_set_time),
    .now(now), .early(), .late(late), .too_early()
  );


  reg [RB_DWIDTH-1:0] cached_rb_data;
  axi_fifo_2clk #(
    .WIDTH(RB_DWIDTH), .SIZE(0)
  ) rbdata_2clk_fifo_i (
    .reset(tb_rst),
    .i_aclk(tb_clk), .i_tdata(cached_rb_data), .i_tvalid(set_finished), .i_tready(),
    .o_aclk(sb_clk), .o_tdata(s_rb_data), .o_tvalid(rb_valid), .o_tready(s_rb_stb)
  );


  reg [2:0] out_state = ST_IDLE;
  always @(posedge tb_clk) begin
    if (tb_rst) begin
      out_state <= ST_IDLE;
    end else begin
      case (out_state)
        ST_IDLE: begin
          if (go & set_pending) begin
            out_state <= ST_SET_ISSUED;
          end
        end
        ST_SET_ISSUED: begin
          out_state <= ST_SET_PENDING;
        end
        ST_SET_PENDING: begin
          if (~m_set_pending) begin
            if (m_rb_stb) begin
              out_state <= ST_RB_DONE;
              cached_rb_data <= m_rb_data;
            end else begin
              out_state <= ST_RB_PENDING;
            end
          end
        end
        ST_RB_PENDING: begin
          if (m_rb_stb) begin
            out_state <= ST_RB_DONE;
            cached_rb_data <= m_rb_data;
          end
        end
        ST_RB_DONE: begin
          out_state <= ST_IDLE;
        end
        default: begin
          out_state <= ST_IDLE;
        end
      endcase
    end
  end

  assign m_set_stb = (out_state == ST_SET_ISSUED);
  assign set_finished = (out_state == ST_RB_DONE);

endmodule