data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/MEMSegReg.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/MEMSegReg.v:34: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance MEMSegReg\n            RegWriteM<=1\'b0;\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/MEMSegReg.v:36: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance MEMSegReg\n            MemWriteM<=1\'b0;\n                     ^~\n%Error: Exiting due to 2 warning(s)\n'
module MEMSegReg(
    input wire clk,
    input wire rst,
    input wire en,

    input wire [31:0] AluOutE,
    output reg [31:0] AluOutM, 
    input wire [31:0] ForwardData2,
    output reg [31:0] StoreDataM, 
    input wire [4:0] RdE,
    output reg [4:0] RdM,
    input wire [31:0] PCE,
    output reg [31:0] PCM,

    input wire [2:0] RegWriteE,
    output reg [2:0] RegWriteM,
    input wire MemToRegE,
    output reg MemToRegM,
    input wire [3:0] MemWriteE,
    output reg [3:0] MemWriteM,
    input wire LoadNpcE,
    output reg LoadNpcM
    );

    always@(posedge clk or posedge rst)
    begin
        if(rst)
        begin
            AluOutM<=32'b0;
            StoreDataM<=32'b0;
            RdM<=5'b0;
            PCM<=32'b0;
            RegWriteM<=1'b0;
            MemToRegM<=1'b0;
            MemWriteM<=1'b0;
            LoadNpcM<=1'b0;   
        end
        else if(en)
        begin

            AluOutM<=AluOutE;
            StoreDataM<=ForwardData2;
            RdM<=RdE;
            PCM<=PCE;
            RegWriteM<=RegWriteE;
            MemToRegM<=MemToRegE;
            MemWriteM<=MemWriteE;
            LoadNpcM<=LoadNpcE;
        end
    end
    
endmodule
module MEMSegReg(
    input wire clk,
    input wire rst,
    input wire en,

    input wire [31:0] AluOutE,
    output reg [31:0] AluOutM, 
    input wire [31:0] ForwardData2,
    output reg [31:0] StoreDataM, 
    input wire [4:0] RdE,
    output reg [4:0] RdM,
    input wire [31:0] PCE,
    output reg [31:0] PCM,

    input wire [2:0] RegWriteE,
    output reg [2:0] RegWriteM,
    input wire MemToRegE,
    output reg MemToRegM,
    input wire [3:0] MemWriteE,
    output reg [3:0] MemWriteM,
    input wire LoadNpcE,
    output reg LoadNpcM
    );


    always@(posedge clk or posedge rst)
    begin
        if(rst)
        begin
            AluOutM<=32'b0;
            StoreDataM<=32'b0;
            RdM<=5'b0;
            PCM<=32'b0;
            RegWriteM<=1'b0;
            MemToRegM<=1'b0;
            MemWriteM<=1'b0;
            LoadNpcM<=1'b0;   
        end
        else if(en)
        begin

            AluOutM<=AluOutE;
            StoreDataM<=ForwardData2;
            RdM<=RdE;
            PCM<=PCE;
            RegWriteM<=RegWriteE;
            MemToRegM<=MemToRegE;
            MemWriteM<=MemWriteE;
            LoadNpcM<=LoadNpcE;
        end
    end
    
endmodule