data/full_repos/permissive/20270692/labs/lab1/fig3p37.v
data/verilator_xmls/cfb63ae2-3422-4b7c-9359-21a347f8229c.xml
module fig3p37 (A,B,C,D,E);
  output D,E;
  input A,B,C;
  wire w1;

  and G1(w1,A,B);
  not G2(E,C);
  xor G3(D,w1,E);

endmodule
module fig3p37 (A,B,C,D,E);

  output D,E;
  input A,B,C;
  wire w1;

  and G1(w1,A,B);
  not G2(E,C);
  xor G3(D,w1,E);

endmodule