data/full_repos/permissive/181013988/src/sign_extn.v
None: at end of input
data/verilator_xmls/0c29b2c2-e60d-49d2-be4c-fb1c44ef4ccc.xml
module sign_extn(
    input [15:0] in,
    output [31:0] out
);

    assign out = {{16{in[15]}},in[15:0]};

endmodule
module sign_extn(
    input [15:0] in,
    output [31:0] out
);


    assign out = {{16{in[15]}},in[15:0]};

endmodule