data/full_repos/permissive/109209652/verilog/convolve_census/convolve_mult.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/f6fba0fd-a186-4b1f-81a0-b802f7631124.xml
module convolve_mult (out, a, b);
	output	signed	[15:0]	out;
	input 			[7:0] 	a;
	input 	signed	[7:0] 	b;
	
	wire	signed	[15:0]	out;
	wire 	signed	[17:0]	mult_out;
	wire	signed	[8:0]	a_se;
	wire	signed	[8:0]	b_se;


	assign a_se = {1'b0, a};
	assign b_se = {b[7], b};

	assign mult_out = a_se * b_se;
	assign out = {mult_out[17], mult_out[14:0]};
endmodule
module convolve_mult (out, a, b);

	output	signed	[15:0]	out;
	input 			[7:0] 	a;
	input 	signed	[7:0] 	b;
	
	wire	signed	[15:0]	out;
	wire 	signed	[17:0]	mult_out;
	wire	signed	[8:0]	a_se;
	wire	signed	[8:0]	b_se;


	assign a_se = {1'b0, a};
	assign b_se = {b[7], b};

	assign mult_out = a_se * b_se;
	assign out = {mult_out[17], mult_out[14:0]};
endmodule