data/full_repos/permissive/197356760/UpDownCounter/UD_Counter.v
1: b"%Error: data/full_repos/permissive/197356760/UpDownCounter/UD_Counter.v:35: Cannot find file containing module: 'seven_seg'\nseven_seg inst(counter,out);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197356760/UpDownCounter,data/full_repos/permissive/197356760/seven_seg\n             data/full_repos/permissive/197356760/UpDownCounter,data/full_repos/permissive/197356760/seven_seg.v\n             data/full_repos/permissive/197356760/UpDownCounter,data/full_repos/permissive/197356760/seven_seg.sv\n             seven_seg\n             seven_seg.v\n             seven_seg.sv\n             obj_dir/seven_seg\n             obj_dir/seven_seg.v\n             obj_dir/seven_seg.sv\n%Error: Exiting due to 1 error(s)\n"
module UD_Counter(clk,rst,load,ud,init,out);
input clk,rst,ud,load;
input [3:0] init;
output [6:0]out;

reg [3:0] counter;


reg [23:0] div;
always@(posedge clk)
	div = div +1;



always@(posedge div[23] or posedge rst)begin
	if (rst==1'b1)
		counter = 4'b0;
	else
	begin
		if (load==1'b1)
			counter = init;
		else
			if (ud==1'b1)
				counter = counter+4'b0001;
			else
				counter = counter -4'b0001;
	end
end

seven_seg inst(counter,out);
endmodule
module UD_Counter(clk,rst,load,ud,init,out);

input clk,rst,ud,load;
input [3:0] init;
output [6:0]out;

reg [3:0] counter;


reg [23:0] div;
always@(posedge clk)
	div = div +1;



always@(posedge div[23] or posedge rst)begin
	if (rst==1'b1)
		counter = 4'b0;
	else
	begin
		if (load==1'b1)
			counter = init;
		else
			if (ud==1'b1)
				counter = counter+4'b0001;
			else
				counter = counter -4'b0001;
	end
end

seven_seg inst(counter,out);
endmodule