data/full_repos/permissive/136422019/src/cla16.v
data/verilator_xmls/f61e63cf-cf4e-4f32-ba2c-cc286496c306.xml
module cla4 (
	output [3:0] S,
	output Cout, PG, GG,
	input [3:0] X,Y,
	input Cin
	);
	
	wire[3:0] G,P,C;
			
		assign G = X & Y;
		assign P = X ^ Y;
		assign C[0] = Cin;
		assign C[1] = G[0] | (P[0] & C[0]);
		assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
		assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);
		assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) | (P[3] & P[2] & P[1] & P[0] & C[0]);
	 
		assign S = P ^ C;
		
		assign PG = P[3] & P[2] & P[1] & P[0];
		assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
endmodule
module cla4 (
	output [3:0] S,
	output Cout, PG, GG,
	input [3:0] X,Y,
	input Cin
	);

	
	wire[3:0] G,P,C;
			
		assign G = X & Y;
		assign P = X ^ Y;
		assign C[0] = Cin;
		assign C[1] = G[0] | (P[0] & C[0]);
		assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
		assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);
		assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) | (P[3] & P[2] & P[1] & P[0] & C[0]);
	 
		assign S = P ^ C;
		
		assign PG = P[3] & P[2] & P[1] & P[0];
		assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
endmodule