data/full_repos/permissive/168395472/labs/03_counter/testbench.v
 line:26: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/168395472/labs/03_counter/testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/168395472/labs/03_counter/testbench.v:24: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;       \n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/168395472/labs/03_counter/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #50 $finish;     \n    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

reg clk = 1'b0;

always begin
    #1 clk = ~clk;
end

wire clk2;

counter counter(.clk(clk), .clk2(clk2));

initial begin
    $dumpvars;
    $display("Test started...");
    #50 $finish;
end

endmodule
module testbench();


reg clk = 1'b0;

always begin
    #1 clk = ~clk;
end

wire clk2;

counter counter(.clk(clk), .clk2(clk2));

initial begin
    $dumpvars;
    $display("Test started...");
    #50 $finish;
end

endmodule