data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 1; K = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 1; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 0; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 0; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 1; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 1; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 0; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 0; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 1; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 1; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 1; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 1; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 0; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 0; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 0; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 0; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 1; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 1; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 1; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 1; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 1; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 1; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 0; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 0; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 1; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 1; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 0; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 0; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 1; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 1; K = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; J = 1; K = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; J = 1; K = 1;\n    ^\n%Error: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/testJK.v:6: Cannot find file containing module: \'jkFlipFlop\'\n  jkFlipFlop jk(J, K, CLK, Q, Qbar);\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop,data/full_repos/permissive/172602559/jkFlipFlop\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop,data/full_repos/permissive/172602559/jkFlipFlop.v\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop,data/full_repos/permissive/172602559/jkFlipFlop.sv\n             jkFlipFlop\n             jkFlipFlop.v\n             jkFlipFlop.sv\n             obj_dir/jkFlipFlop\n             obj_dir/jkFlipFlop.v\n             obj_dir/jkFlipFlop.sv\n%Error: Exiting due to 1 error(s), 32 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testJK();
  
  wire Q, Qbar;
  reg J, K, CLK;
  
  jkFlipFlop jk(J, K, CLK, Q, Qbar);
  
  initial
  begin
    #10 CLK = 0; J = 1; K = 1;
    #10 CLK = 1; J = 1; K = 1;
    #10 CLK = 0; J = 0; K = 0;
    #10 CLK = 1; J = 0; K = 0;
    #10 CLK = 0; J = 1; K = 0;
    #10 CLK = 1; J = 1; K = 0;
    #10 CLK = 0; J = 0; K = 1;
    #10 CLK = 1; J = 0; K = 1;
    #10 CLK = 0; J = 1; K = 0;
    #10 CLK = 1; J = 1; K = 0;
    #10 CLK = 0; J = 1; K = 1;
    #10 CLK = 1; J = 1; K = 1;
    
    #10 CLK = 0; J = 0; K = 0;
    #10 CLK = 1; J = 0; K = 0;
    #10 CLK = 0; J = 0; K = 1;
    #10 CLK = 1; J = 0; K = 1;
    #10 CLK = 0; J = 1; K = 0;
    #10 CLK = 1; J = 1; K = 0;
    #10 CLK = 0; J = 1; K = 0;
    #10 CLK = 1; J = 1; K = 0;
    #10 CLK = 0; J = 1; K = 1;
    #10 CLK = 1; J = 1; K = 1;
    
    #10 CLK = 0; J = 0; K = 0;
    #10 CLK = 1; J = 0; K = 0;
    #10 CLK = 0; J = 1; K = 1;
    #10 CLK = 1; J = 1; K = 1;
    #10 CLK = 0; J = 0; K = 1;
    #10 CLK = 1; J = 0; K = 1;
    #10 CLK = 0; J = 1; K = 0;
    #10 CLK = 1; J = 1; K = 0;
    #10 CLK = 0; J = 1; K = 1;
    #10 CLK = 1; J = 1; K = 1;
  end
endmodule
module testJK();

  
  wire Q, Qbar;
  reg J, K, CLK;
  
  jkFlipFlop jk(J, K, CLK, Q, Qbar);
  
  initial
  begin
    #10 CLK = 0; J = 1; K = 1;
    #10 CLK = 1; J = 1; K = 1;
    #10 CLK = 0; J = 0; K = 0;
    #10 CLK = 1; J = 0; K = 0;
    #10 CLK = 0; J = 1; K = 0;
    #10 CLK = 1; J = 1; K = 0;
    #10 CLK = 0; J = 0; K = 1;
    #10 CLK = 1; J = 0; K = 1;
    #10 CLK = 0; J = 1; K = 0;
    #10 CLK = 1; J = 1; K = 0;
    #10 CLK = 0; J = 1; K = 1;
    #10 CLK = 1; J = 1; K = 1;
    
    #10 CLK = 0; J = 0; K = 0;
    #10 CLK = 1; J = 0; K = 0;
    #10 CLK = 0; J = 0; K = 1;
    #10 CLK = 1; J = 0; K = 1;
    #10 CLK = 0; J = 1; K = 0;
    #10 CLK = 1; J = 1; K = 0;
    #10 CLK = 0; J = 1; K = 0;
    #10 CLK = 1; J = 1; K = 0;
    #10 CLK = 0; J = 1; K = 1;
    #10 CLK = 1; J = 1; K = 1;
    
    #10 CLK = 0; J = 0; K = 0;
    #10 CLK = 1; J = 0; K = 0;
    #10 CLK = 0; J = 1; K = 1;
    #10 CLK = 1; J = 1; K = 1;
    #10 CLK = 0; J = 0; K = 1;
    #10 CLK = 1; J = 0; K = 1;
    #10 CLK = 0; J = 1; K = 0;
    #10 CLK = 1; J = 1; K = 0;
    #10 CLK = 0; J = 1; K = 1;
    #10 CLK = 1; J = 1; K = 1;
  end
endmodule