data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv
 line:40 column:21: Illegal character '"'
1: b'%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv:41: Unterminated string\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv:42: Unterminated string\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv:18: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv:18: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv:40: syntax error, unexpected \'%\', expecting \')\'\n          $display(          S %h (%h expected)          errors = errors + 1;\n                                   ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module testbenchFTCfunct();
    logic clk;
    logic Cin, I1, I2, I3, I4, C, Cout, S;
    logic [7:0] vectors[31:0], currentvec;
    logic [6:0] vectornum, errors;
    

    FTC dut(Cin, I1, I2, I3, I4, C, Cout, S);
    

    initial begin
       $readmemb("FTC-vectors.txt", vectors);
       vectornum = 0; errors = 0;
    end

    always begin
       clk = 1; #10; clk = 0; #10;
    end

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
       Cin = currentvec[7];
       I1 = currentvec[6];
       I2 = currentvec[5];
       I3 = currentvec[4];
       I4 = currentvec[3];
       
       if (vectornum === 31) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
         $stop;
       end
    end
    

    always @(negedge clk) begin
       if ((S !== currentvec[0]) || (Cout !== currentvec[1]) || ( C !== currentvec[2])) begin
          $display("Error: inputs were Cin=%h I1=%h I2=%h I3=%h I4=%h", Cin, I1, I2, I3, I4);
          $display("Check C : %h (%h expected), Cout %h (%h expected), 
          S %h (%h expected)", C , currentvec[2], Cout, currentvec[1], S, currentvec[0]);
          errors = errors + 1;
       end
       vectornum = vectornum + 1;
    end
endmodule
module testbenchFTCfunct();

    logic clk;
    logic Cin, I1, I2, I3, I4, C, Cout, S;
    logic [7:0] vectors[31:0], currentvec;
    logic [6:0] vectornum, errors;
    

    FTC dut(Cin, I1, I2, I3, I4, C, Cout, S);
    

    initial begin
       $readmemb("FTC-vectors.txt", vectors);
       vectornum = 0; errors = 0;
    end

    always begin
       clk = 1; #10; clk = 0; #10;
    end

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
       Cin = currentvec[7];
       I1 = currentvec[6];
       I2 = currentvec[5];
       I3 = currentvec[4];
       I4 = currentvec[3];
       
       if (vectornum === 31) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
         $stop;
       end
    end
    

    always @(negedge clk) begin
       if ((S !== currentvec[0]) || (Cout !== currentvec[1]) || ( C !== currentvec[2])) begin
          $display("Error: inputs were Cin=%h I1=%h I2=%h I3=%h I4=%h", Cin, I1, I2, I3, I4);
          $display("Check C : %h (%h expected), Cout %h (%h expected), 
          S %h (%h expected)", C , currentvec[2], Cout, currentvec[1], S, currentvec[0]);
          errors = errors + 1;
       end
       vectornum = vectornum + 1;
    end
endmodule