data/full_repos/permissive/20430511/hardware/FPGA/wishbone/rtl/wb_chunk.v
 line:58: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/wishbone/rtl/wb_chunk.v:70: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'count\' generates 3 bits.\n                                                                                            : ... In instance wb_chunk\n   wire            wrap_count = count == COUNT;\n                                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/wishbone/rtl/wb_chunk.v:71: Operator COND expects 32 or 4 bits on the Conditional True, but Conditional True\'s REPLICATE generates 3 bits.\n                                                                                            : ... In instance wb_chunk\n   wire [CBITS:0]  next_count = wrap_count ? {CBITS{1\'b0}} : count + 1;\n                                           ^\n%Error: Exiting due to 2 warning(s)\n'
module wb_chunk
  #(parameter WIDTH = 48,
    parameter WSB   = WIDTH-1,
    parameter CHUNK = 8,
    parameter MSB   = CHUNK-1,
    parameter COUNT = (WIDTH+CHUNK-1) / CHUNK - 1,
    parameter CBITS = 3,
    parameter CSB   = CBITS-1,
    parameter DELAY = 3)
   (

    input          clk_i,
    input          rst_i,
    input          cyc_i,
    input          stb_i,
    input          we_i,
    output reg     ack_o = 0,
    input [MSB:0]  dat_i,
    output [MSB:0] dat_o,

    output reg     fetch_o = 0,
    input          ready_i,
    input [WSB:0]  value_i
    );

   reg             empty = 1'b1;
   reg [WSB:0]     word = {WIDTH{1'bx}};
   reg [CSB:0]     count = {CBITS{1'b0}};
   wire            wrap_count = count == COUNT;
   wire [CBITS:0]  next_count = wrap_count ? {CBITS{1'b0}} : count + 1;

   assign dat_o = word[MSB:0];



   always @(posedge clk_i)
     if (rst_i || ack_o)
       ack_o <= #DELAY 1'b0;
     else if (cyc_i && stb_i && !empty)
       ack_o <= #DELAY 1'b1;

   always @(posedge clk_i)
     if (rst_i || fetch_o && ready_i)
       count <= #DELAY {CBITS{1'b0}};
     else if (cyc_i && stb_i && !ack_o && !empty)
       count <= #DELAY next_count[CSB:0];



   always @(posedge clk_i)
     if (rst_i || fetch_o && ready_i)
       fetch_o <= #DELAY 1'b0;
     else if (cyc_i && stb_i && empty)
       fetch_o <= #DELAY 1'b1;

   always @(posedge clk_i)
     if (rst_i)
       empty <= #DELAY 1'b1;
     else if (fetch_o && ready_i)
       empty <= #DELAY 1'b0;
     else if (wrap_count && cyc_i && stb_i && !ack_o)
       empty <= #DELAY 1'b1;



   always @(posedge clk_i)
     if (fetch_o && ready_i)
       word <= #DELAY value_i;
     else if (cyc_i && stb_i && ack_o)
       word <= #DELAY {{CHUNK{1'b0}}, word[WSB:CHUNK]};


endmodule
module wb_chunk
  #(parameter WIDTH = 48,
    parameter WSB   = WIDTH-1,
    parameter CHUNK = 8,
    parameter MSB   = CHUNK-1,
    parameter COUNT = (WIDTH+CHUNK-1) / CHUNK - 1,
    parameter CBITS = 3,
    parameter CSB   = CBITS-1,
    parameter DELAY = 3)
   (

    input          clk_i,
    input          rst_i,
    input          cyc_i,
    input          stb_i,
    input          we_i,
    output reg     ack_o = 0,
    input [MSB:0]  dat_i,
    output [MSB:0] dat_o,

    output reg     fetch_o = 0,
    input          ready_i,
    input [WSB:0]  value_i
    );


   reg             empty = 1'b1;
   reg [WSB:0]     word = {WIDTH{1'bx}};
   reg [CSB:0]     count = {CBITS{1'b0}};
   wire            wrap_count = count == COUNT;
   wire [CBITS:0]  next_count = wrap_count ? {CBITS{1'b0}} : count + 1;

   assign dat_o = word[MSB:0];



   always @(posedge clk_i)
     if (rst_i || ack_o)
       ack_o <= #DELAY 1'b0;
     else if (cyc_i && stb_i && !empty)
       ack_o <= #DELAY 1'b1;

   always @(posedge clk_i)
     if (rst_i || fetch_o && ready_i)
       count <= #DELAY {CBITS{1'b0}};
     else if (cyc_i && stb_i && !ack_o && !empty)
       count <= #DELAY next_count[CSB:0];



   always @(posedge clk_i)
     if (rst_i || fetch_o && ready_i)
       fetch_o <= #DELAY 1'b0;
     else if (cyc_i && stb_i && empty)
       fetch_o <= #DELAY 1'b1;

   always @(posedge clk_i)
     if (rst_i)
       empty <= #DELAY 1'b1;
     else if (fetch_o && ready_i)
       empty <= #DELAY 1'b0;
     else if (wrap_count && cyc_i && stb_i && !ack_o)
       empty <= #DELAY 1'b1;



   always @(posedge clk_i)
     if (fetch_o && ready_i)
       word <= #DELAY value_i;
     else if (cyc_i && stb_i && ack_o)
       word <= #DELAY {{CHUNK{1'b0}}, word[WSB:CHUNK]};


endmodule