data/full_repos/permissive/184916587/AGU.v
1: b"%Error: data/full_repos/permissive/184916587/AGU.v:13: Duplicate declaration of signal: 'address'\n                                                     : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg[31:0] address;\n           ^~~~~~~\n        data/full_repos/permissive/184916587/AGU.v:10: ... Location of original declaration\n output[31:0] address\n              ^~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module AGU(
	input _Rest,
	input PCWre,
	output[31:0] address
);

	reg[31:0] address;
	always @(*)
	begin
		if(_Rest===1)
			address=0;
		else if(PCWre) begin
			address=address+4;
		end
	end
endmodule
module AGU(
	input _Rest,
	input PCWre,
	output[31:0] address
);


	reg[31:0] address;
	always @(*)
	begin
		if(_Rest===1)
			address=0;
		else if(PCWre) begin
			address=address+4;
		end
	end
endmodule