data/full_repos/permissive/103842408/rtl/main/rvm_core.v
1: b'%Error: data/full_repos/permissive/103842408/rtl/main/rvm_core.v:11: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.v\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.sv\n             rvm_constants.v\n             rvm_constants.v.v\n             rvm_constants.v.sv\n             obj_dir/rvm_constants.v\n             obj_dir/rvm_constants.v.v\n             obj_dir/rvm_constants.v.sv\n%Error: Exiting due to 1 error(s)\n'
module rvm_core(
input  wire         clk,
input  wire         resetn,

output wire [31:0]  mem_addr,
input  wire [31:0]  mem_rdata,
output wire [31:0]  mem_wdata,
output wire         mem_c_en,
output wire         mem_w_en,
output wire [ 3:0]  mem_b_en,
input  wire         mem_error,
input  wire         mem_stall

);





wire        scu_instr_retired;
wire        scu_goto_mtvec   ;
wire [ 3:0] f_scu_op         ;
wire [31:0] f_scu_result     ;
wire [31:0] s_epc            ;
wire [31:2] s_mtvec          ;





wire [31:0] f_add_lhs   ;
wire [31:0] f_add_rhs   ;
wire [ 2:0] f_add_op    ;
wire        f_add_valid ;
wire [31:0] f_add_result;
wire        f_add_overflow;

wire [31:0] f_bit_lhs   ;
wire [31:0] f_bit_rhs   ;
wire [ 1:0] f_bit_op    ;
wire        f_bit_valid ;
wire [31:0] f_bit_result;

wire [31:0] f_shf_lhs   ;
wire [ 4:0] f_shf_rhs   ;
wire [ 1:0] f_shf_op    ;
wire        f_shf_valid ;
wire [31:0] f_shf_result;





wire        s_rs1_en     ;
wire [4 :0] s_rs1_addr   ;
wire [31:0] s_rs1_rdata  ;

wire        s_rs2_en     ;
wire [4 :0] s_rs2_addr   ;
wire [31:0] s_rs2_rdata  ;

wire        d_rd_wen     ;
wire [4 :0] d_rd_addr    ;
wire [31:0] d_rd_wdata   ;





wire        d_pc_w_en;
wire [31:0] d_pc_wdata;
wire [31:0] s_pc;





wire        ctrl_illegal_instr;
wire        ctrl_fdu_mem_valid;

wire [ 4:0] i_rs1_addr  ;
wire [ 4:0] i_rs2_addr  ;
wire [ 4:0] i_rd_addr   ;
wire [31:0] i_immediate ;
wire [ 5:0] i_instr     ;


rvm_fdu i_rvm_fdu(
.clk          (clk               ),
.resetn       (resetn            ),
.mem_rdata    (mem_rdata         ),
.mem_valid    (ctrl_fdu_mem_valid),
.illegal_instr(ctrl_illegal_instr),
.rs1          (i_rs1_addr        ),
.rs2          (i_rs2_addr        ),
.dest         (i_rd_addr         ),
.imm          (i_immediate       ),
.instr        (i_instr           )
);





rvm_pcu i_rvm_pcu (
.clk     (clk       ),
.resetn  (resetn    ),
.pc_w_en (d_pc_w_en ),
.pc_wdata(d_pc_wdata),
.pc      (s_pc      )
);

rvm_gprs i_rvm_gprs (
.clk       (clk        ),
.resetn    (resetn     ),
.rs1_en    (s_rs1_en   ),
.rs1_addr  (s_rs1_addr ),
.rs1_rdata (s_rs1_rdata),
.rs2_en    (s_rs2_en   ),
.rs2_addr  (s_rs2_addr ),
.rs2_rdata (s_rs2_rdata),
.rd_wen    (d_rd_wen   ),
.rd_addr   (d_rd_addr  ),
.rd_wdata  (d_rd_wdata )
);





rvm_adder i_rvm_add(
.lhs   (f_add_lhs   ),
.rhs   (f_add_rhs   ),
.op    (f_add_op    ),
.valid (f_add_valid ),
.result(f_add_result),
.overflow(f_add_overflow)
);

rvm_bitwise i_rvm_bitwise(
.lhs   (f_bit_lhs   ),
.rhs   (f_bit_rhs   ),
.op    (f_bit_op    ),
.valid (f_bit_valid ),
.result(f_bit_result)
);

rvm_shift i_rvm_shift(
.lhs   (f_shf_lhs   ),
.rhs   (f_shf_rhs   ),
.op    (f_shf_op    ),
.valid (f_shf_valid ),
.result(f_shf_result)
);






rvm_control i_rvm_control(
.clk          (clk         ),
.resetn       (resetn      ),
.f_scu_op         (f_scu_op           ),
.f_scu_result     (f_scu_result       ),
.f_scu_mtvec  (s_mtvec      ),
.f_scu_mepc   (s_epc        ),
.scu_instr_retired(scu_instr_retired  ),
.f_add_lhs    (f_add_lhs   ),
.f_add_rhs    (f_add_rhs   ),
.f_add_op     (f_add_op    ),
.f_add_valid  (f_add_valid ),
.f_add_result (f_add_result),
.f_bit_lhs    (f_bit_lhs   ),
.f_bit_rhs    (f_bit_rhs   ),
.f_bit_op     (f_bit_op    ),
.f_bit_valid  (f_bit_valid ),
.f_bit_result (f_bit_result),
.f_shf_lhs    (f_shf_lhs   ),
.f_shf_rhs    (f_shf_rhs   ),
.f_shf_op     (f_shf_op    ),
.f_shf_valid  (f_shf_valid ),
.f_shf_result (f_shf_result),
.ctrl_illegal_instr(ctrl_illegal_instr),
.ctrl_fdu_mem_valid(ctrl_fdu_mem_valid),
.i_rs1_addr   (i_rs1_addr  ),
.i_rs2_addr   (i_rs2_addr  ),
.i_rd_addr    (i_rd_addr   ),
.i_immediate  (i_immediate ),
.i_instr      (i_instr     ),
.s_rs1_en     (s_rs1_en    ),
.s_rs1_addr   (s_rs1_addr  ),
.s_rs1_rdata  (s_rs1_rdata ),
.s_rs2_en     (s_rs2_en    ),
.s_rs2_addr   (s_rs2_addr  ),
.s_rs2_rdata  (s_rs2_rdata ),
.d_rd_wen     (d_rd_wen    ),
.d_rd_addr    (d_rd_addr   ),
.d_rd_wdata   (d_rd_wdata  ),
.d_pc_w_en    (d_pc_w_en   ),
.d_pc_wdata   (d_pc_wdata  ),
.s_pc         (s_pc        ),
.mem_addr     (mem_addr    ),
.mem_rdata    (mem_rdata   ),
.mem_wdata    (mem_wdata   ),
.mem_c_en     (mem_c_en    ),
.mem_w_en     (mem_w_en    ),
.mem_b_en     (mem_b_en    ),
.mem_error    (mem_error   ),
.mem_stall    (mem_stall   )
);


rvm_scu i_scu(
.clk                (clk),
.resetn             (resetn),
.core_stall         (1'b0),
.pc                 (s_pc),
.instr_retired      (scu_instr_retired),
.goto_mtvec         (scu_goto_mtvec   ),
.scu_op             (f_scu_op         ),
.arg_rs1_addr       (i_rs1_addr),
.arg_rs1            (s_rs1_rdata),
.arg_rs2            (s_rs2_rdata),
.arg_imm            (i_immediate),
.wb_val             (f_scu_result),
.ld_bad_addr        (1'b0),
.bad_addr_val       (mem_addr),
.trap_msi           (1'b0),
.trap_mei           (1'b0),
.trap_iaddr_misalign(1'b0),
.trap_iaddr_fault   (1'b0),
.trap_illegal_instr (1'b0),
.trap_breakpoint    (1'b0),
.trap_laddr_misalign(1'b0),
.trap_laddr_fault   (1'b0),
.trap_saddr_misalign(1'b0),
.trap_saddr_fault   (1'b0),
.mepc               (s_epc),
.mtvec              (s_mtvec)
);

endmodule
module rvm_core(
input  wire         clk,
input  wire         resetn,

output wire [31:0]  mem_addr,
input  wire [31:0]  mem_rdata,
output wire [31:0]  mem_wdata,
output wire         mem_c_en,
output wire         mem_w_en,
output wire [ 3:0]  mem_b_en,
input  wire         mem_error,
input  wire         mem_stall

);






wire        scu_instr_retired;
wire        scu_goto_mtvec   ;
wire [ 3:0] f_scu_op         ;
wire [31:0] f_scu_result     ;
wire [31:0] s_epc            ;
wire [31:2] s_mtvec          ;





wire [31:0] f_add_lhs   ;
wire [31:0] f_add_rhs   ;
wire [ 2:0] f_add_op    ;
wire        f_add_valid ;
wire [31:0] f_add_result;
wire        f_add_overflow;

wire [31:0] f_bit_lhs   ;
wire [31:0] f_bit_rhs   ;
wire [ 1:0] f_bit_op    ;
wire        f_bit_valid ;
wire [31:0] f_bit_result;

wire [31:0] f_shf_lhs   ;
wire [ 4:0] f_shf_rhs   ;
wire [ 1:0] f_shf_op    ;
wire        f_shf_valid ;
wire [31:0] f_shf_result;





wire        s_rs1_en     ;
wire [4 :0] s_rs1_addr   ;
wire [31:0] s_rs1_rdata  ;

wire        s_rs2_en     ;
wire [4 :0] s_rs2_addr   ;
wire [31:0] s_rs2_rdata  ;

wire        d_rd_wen     ;
wire [4 :0] d_rd_addr    ;
wire [31:0] d_rd_wdata   ;





wire        d_pc_w_en;
wire [31:0] d_pc_wdata;
wire [31:0] s_pc;





wire        ctrl_illegal_instr;
wire        ctrl_fdu_mem_valid;

wire [ 4:0] i_rs1_addr  ;
wire [ 4:0] i_rs2_addr  ;
wire [ 4:0] i_rd_addr   ;
wire [31:0] i_immediate ;
wire [ 5:0] i_instr     ;


rvm_fdu i_rvm_fdu(
.clk          (clk               ),
.resetn       (resetn            ),
.mem_rdata    (mem_rdata         ),
.mem_valid    (ctrl_fdu_mem_valid),
.illegal_instr(ctrl_illegal_instr),
.rs1          (i_rs1_addr        ),
.rs2          (i_rs2_addr        ),
.dest         (i_rd_addr         ),
.imm          (i_immediate       ),
.instr        (i_instr           )
);





rvm_pcu i_rvm_pcu (
.clk     (clk       ),
.resetn  (resetn    ),
.pc_w_en (d_pc_w_en ),
.pc_wdata(d_pc_wdata),
.pc      (s_pc      )
);

rvm_gprs i_rvm_gprs (
.clk       (clk        ),
.resetn    (resetn     ),
.rs1_en    (s_rs1_en   ),
.rs1_addr  (s_rs1_addr ),
.rs1_rdata (s_rs1_rdata),
.rs2_en    (s_rs2_en   ),
.rs2_addr  (s_rs2_addr ),
.rs2_rdata (s_rs2_rdata),
.rd_wen    (d_rd_wen   ),
.rd_addr   (d_rd_addr  ),
.rd_wdata  (d_rd_wdata )
);





rvm_adder i_rvm_add(
.lhs   (f_add_lhs   ),
.rhs   (f_add_rhs   ),
.op    (f_add_op    ),
.valid (f_add_valid ),
.result(f_add_result),
.overflow(f_add_overflow)
);

rvm_bitwise i_rvm_bitwise(
.lhs   (f_bit_lhs   ),
.rhs   (f_bit_rhs   ),
.op    (f_bit_op    ),
.valid (f_bit_valid ),
.result(f_bit_result)
);

rvm_shift i_rvm_shift(
.lhs   (f_shf_lhs   ),
.rhs   (f_shf_rhs   ),
.op    (f_shf_op    ),
.valid (f_shf_valid ),
.result(f_shf_result)
);






rvm_control i_rvm_control(
.clk          (clk         ),
.resetn       (resetn      ),
.f_scu_op         (f_scu_op           ),
.f_scu_result     (f_scu_result       ),
.f_scu_mtvec  (s_mtvec      ),
.f_scu_mepc   (s_epc        ),
.scu_instr_retired(scu_instr_retired  ),
.f_add_lhs    (f_add_lhs   ),
.f_add_rhs    (f_add_rhs   ),
.f_add_op     (f_add_op    ),
.f_add_valid  (f_add_valid ),
.f_add_result (f_add_result),
.f_bit_lhs    (f_bit_lhs   ),
.f_bit_rhs    (f_bit_rhs   ),
.f_bit_op     (f_bit_op    ),
.f_bit_valid  (f_bit_valid ),
.f_bit_result (f_bit_result),
.f_shf_lhs    (f_shf_lhs   ),
.f_shf_rhs    (f_shf_rhs   ),
.f_shf_op     (f_shf_op    ),
.f_shf_valid  (f_shf_valid ),
.f_shf_result (f_shf_result),
.ctrl_illegal_instr(ctrl_illegal_instr),
.ctrl_fdu_mem_valid(ctrl_fdu_mem_valid),
.i_rs1_addr   (i_rs1_addr  ),
.i_rs2_addr   (i_rs2_addr  ),
.i_rd_addr    (i_rd_addr   ),
.i_immediate  (i_immediate ),
.i_instr      (i_instr     ),
.s_rs1_en     (s_rs1_en    ),
.s_rs1_addr   (s_rs1_addr  ),
.s_rs1_rdata  (s_rs1_rdata ),
.s_rs2_en     (s_rs2_en    ),
.s_rs2_addr   (s_rs2_addr  ),
.s_rs2_rdata  (s_rs2_rdata ),
.d_rd_wen     (d_rd_wen    ),
.d_rd_addr    (d_rd_addr   ),
.d_rd_wdata   (d_rd_wdata  ),
.d_pc_w_en    (d_pc_w_en   ),
.d_pc_wdata   (d_pc_wdata  ),
.s_pc         (s_pc        ),
.mem_addr     (mem_addr    ),
.mem_rdata    (mem_rdata   ),
.mem_wdata    (mem_wdata   ),
.mem_c_en     (mem_c_en    ),
.mem_w_en     (mem_w_en    ),
.mem_b_en     (mem_b_en    ),
.mem_error    (mem_error   ),
.mem_stall    (mem_stall   )
);


rvm_scu i_scu(
.clk                (clk),
.resetn             (resetn),
.core_stall         (1'b0),
.pc                 (s_pc),
.instr_retired      (scu_instr_retired),
.goto_mtvec         (scu_goto_mtvec   ),
.scu_op             (f_scu_op         ),
.arg_rs1_addr       (i_rs1_addr),
.arg_rs1            (s_rs1_rdata),
.arg_rs2            (s_rs2_rdata),
.arg_imm            (i_immediate),
.wb_val             (f_scu_result),
.ld_bad_addr        (1'b0),
.bad_addr_val       (mem_addr),
.trap_msi           (1'b0),
.trap_mei           (1'b0),
.trap_iaddr_misalign(1'b0),
.trap_iaddr_fault   (1'b0),
.trap_illegal_instr (1'b0),
.trap_breakpoint    (1'b0),
.trap_laddr_misalign(1'b0),
.trap_laddr_fault   (1'b0),
.trap_saddr_misalign(1'b0),
.trap_saddr_fault   (1'b0),
.mepc               (s_epc),
.mtvec              (s_mtvec)
);

endmodule