data/full_repos/permissive/148324174/HDLBits/Circuits/KarnaughMap.v
1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/KarnaughMap.v:10: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/KarnaughMap.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/KarnaughMap.v:20: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/KarnaughMap.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/KarnaughMap.v:32: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/KarnaughMap.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Error: Exiting due to 3 warning(s)\n'
module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
); 
    assign out_sop = (~a&~b&c&~d) | (b&c&d);
    assign out_pos = b&(~b+d);
endmodule
module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
);
 
    assign out_sop = (~a&~b&c&~d) | (b&c&d);
    assign out_pos = b&(~b+d);
endmodule