data/full_repos/permissive/143278/ivltests/vhdl_expr1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_expr1.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (out != a-b) begin\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_expr1.v:6: Cannot find file containing module: \'subtract\'\n   subtract dut (.a(a), .b(b), .out_sig(out));\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/subtract\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/subtract.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/subtract.sv\n             subtract\n             subtract.v\n             subtract.sv\n             obj_dir/subtract\n             obj_dir/subtract.v\n             obj_dir/subtract.sv\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_expr1.v:9: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'test_vector\' generates 9 bits.\n                                                                         : ... In instance main\n   assign {a, b} = test_vector;\n                 ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire [3:0] a, b;
   wire [3:0] out;

   subtract dut (.a(a), .b(b), .out_sig(out));

   reg [8:0]  test_vector;
   assign {a, b} = test_vector;

   initial begin
      for (test_vector=0 ; test_vector[8]==0 ; test_vector=test_vector+1) begin
	 #1 if (out != a-b) begin
	    $display("FAILED -- out=%b, expecting %b-%b=%b", out, a, b, a-b);
	    $finish;
	 end
      end

      $display("PASSED");
      $finish;
   end
endmodule
module main;


   wire [3:0] a, b;
   wire [3:0] out;

   subtract dut (.a(a), .b(b), .out_sig(out));

   reg [8:0]  test_vector;
   assign {a, b} = test_vector;

   initial begin
      for (test_vector=0 ; test_vector[8]==0 ; test_vector=test_vector+1) begin
	 #1 if (out != a-b) begin
	    $display("FAILED -- out=%b, expecting %b-%b=%b", out, a, b, a-b);
	    $finish;
	 end
      end

      $display("PASSED");
      $finish;
   end
endmodule