data/full_repos/permissive/169496369/rounding.v
data/verilator_xmls/7c75f70e-0db4-43f4-8985-aa53daa08be8.xml
module rounding(m, e, om, oe, control);
    input [24:0]m;
    input [7:0]e;
    input control;
    
    output logic [24:0]om;
    output logic [7:0]oe;
    
    always_comb
    begin
        if(control)
        begin    
            if(m[0] == 1'b1)
            begin
                om = (m + 1);
             end
             else
                om = m;
        end
        else
        begin
            om = m;
        end
        oe = e;
    end
endmodule
module rounding(m, e, om, oe, control);

    input [24:0]m;
    input [7:0]e;
    input control;
    
    output logic [24:0]om;
    output logic [7:0]oe;
    
    always_comb
    begin
        if(control)
        begin    
            if(m[0] == 1'b1)
            begin
                om = (m + 1);
             end
             else
                om = m;
        end
        else
        begin
            om = m;
        end
        oe = e;
    end
endmodule