data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_CMAC_REG_dual.v
1: b'%Warning-WIDTH: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_CMAC_REG_dual.v:68: Operator CASE expects 32 bits on the Case expression, but Case expression\'s VARREF \'reg_offset_rd_int\' generates 12 bits.\n                                                                                                      : ... In instance NV_NVDLA_CMAC_REG_dual\n  case (reg_offset_rd_int)\n  ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_CMAC_REG_dual.v:101: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s TESTPLUSARGS \'arreggen_dump_wr\' generates 32 bits.\n                                                                                                       : ... In instance NV_NVDLA_CMAC_REG_dual\n  arreggen_dump = $test$plusargs("arreggen_dump_wr");\n                ^\n%Warning-WIDTH: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_CMAC_REG_dual.v:102: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s TESTPLUSARGS \'arreggen_abort_on_rowr\' generates 32 bits.\n                                                                                                       : ... In instance NV_NVDLA_CMAC_REG_dual\n  arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr");\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_CMAC_REG_dual.v:103: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s TESTPLUSARGS \'arreggen_abort_on_invalid_wr\' generates 32 bits.\n                                                                                                       : ... In instance NV_NVDLA_CMAC_REG_dual\n  arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr");\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_CMAC_REG_dual.v:111: Operator CASE expects 32 bits on the Case expression, but Case expression\'s VARREF \'reg_offset\' generates 12 bits.\n                                                                                                       : ... In instance NV_NVDLA_CMAC_REG_dual\n    case(reg_offset)\n    ^~~~\n%Error: Exiting due to 5 warning(s)\n'
module NV_NVDLA_CMAC_REG_dual (
   reg_rd_data
  ,reg_offset


  ,reg_wr_data


  ,reg_wr_en
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,conv_mode
  ,proc_precision
  ,op_en_trigger
  ,op_en
  );
wire [31:0] nvdla_cmac_a_d_misc_cfg_0_out;
wire [31:0] nvdla_cmac_a_d_op_enable_0_out;
wire [11:0] reg_offset_rd_int;
wire [31:0] reg_offset_wr;

output [31:0] reg_rd_data;
input [11:0] reg_offset;
input [31:0] reg_wr_data;
input reg_wr_en;
input nvdla_core_clk;
input nvdla_core_rstn;

output conv_mode;
output [1:0] proc_precision;
output op_en_trigger;

input op_en;



reg arreggen_abort_on_invalid_wr;
reg arreggen_abort_on_rowr;
reg arreggen_dump;

reg conv_mode;
reg [1:0] proc_precision;
reg [31:0] reg_rd_data;
assign reg_offset_wr = {20'b0 , reg_offset};


wire nvdla_cmac_a_d_misc_cfg_0_wren = (reg_offset_wr == (32'h700c & 32'h00000fff)) & reg_wr_en ;
wire nvdla_cmac_a_d_op_enable_0_wren = (reg_offset_wr == (32'h7008 & 32'h00000fff)) & reg_wr_en ;
assign nvdla_cmac_a_d_misc_cfg_0_out[31:0] = { 18'b0, proc_precision, 11'b0, conv_mode };
assign nvdla_cmac_a_d_op_enable_0_out[31:0] = { 31'b0, op_en };
assign op_en_trigger = nvdla_cmac_a_d_op_enable_0_wren;
assign reg_offset_rd_int = reg_offset;


always @(
  reg_offset_rd_int
  or nvdla_cmac_a_d_misc_cfg_0_out
  or nvdla_cmac_a_d_op_enable_0_out
  ) begin
  case (reg_offset_rd_int)
     (32'h700c & 32'h00000fff): begin
                            reg_rd_data = nvdla_cmac_a_d_misc_cfg_0_out ;
                            end
     (32'h7008 & 32'h00000fff): begin
                            reg_rd_data = nvdla_cmac_a_d_op_enable_0_out ;
                            end
    default: reg_rd_data = {32{1'b0}};
  endcase
end



always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    conv_mode <= 1'b0;
    proc_precision[1:0] <= 2'b01;
  end else begin

  if (nvdla_cmac_a_d_misc_cfg_0_wren) begin
    conv_mode <= reg_wr_data[0];
  end

  if (nvdla_cmac_a_d_misc_cfg_0_wren) begin
    proc_precision[1:0] <= reg_wr_data[13:12];
  end

  end
end



initial begin
  arreggen_dump = $test$plusargs("arreggen_dump_wr");
  arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr");
  arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr");
`ifdef VERILATOR
`else
  $timeformat(-9, 2, "ns", 15);
`endif
end
always @(posedge nvdla_core_clk) begin
  if (reg_wr_en) begin
    case(reg_offset)
      (32'h700c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CMAC_A_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cmac_a_d_misc_cfg_0_out, nvdla_cmac_a_d_misc_cfg_0_out);
      (32'h7008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CMAC_A_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cmac_a_d_op_enable_0_out, nvdla_cmac_a_d_op_enable_0_out);
      default: begin
          if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data);
          if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end
        end
    endcase
  end
end


endmodule
module NV_NVDLA_CMAC_REG_dual (
   reg_rd_data
  ,reg_offset


  ,reg_wr_data


  ,reg_wr_en
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,conv_mode
  ,proc_precision
  ,op_en_trigger
  ,op_en
  );

wire [31:0] nvdla_cmac_a_d_misc_cfg_0_out;
wire [31:0] nvdla_cmac_a_d_op_enable_0_out;
wire [11:0] reg_offset_rd_int;
wire [31:0] reg_offset_wr;

output [31:0] reg_rd_data;
input [11:0] reg_offset;
input [31:0] reg_wr_data;
input reg_wr_en;
input nvdla_core_clk;
input nvdla_core_rstn;

output conv_mode;
output [1:0] proc_precision;
output op_en_trigger;

input op_en;



reg arreggen_abort_on_invalid_wr;
reg arreggen_abort_on_rowr;
reg arreggen_dump;

reg conv_mode;
reg [1:0] proc_precision;
reg [31:0] reg_rd_data;
assign reg_offset_wr = {20'b0 , reg_offset};


wire nvdla_cmac_a_d_misc_cfg_0_wren = (reg_offset_wr == (32'h700c & 32'h00000fff)) & reg_wr_en ;
wire nvdla_cmac_a_d_op_enable_0_wren = (reg_offset_wr == (32'h7008 & 32'h00000fff)) & reg_wr_en ;
assign nvdla_cmac_a_d_misc_cfg_0_out[31:0] = { 18'b0, proc_precision, 11'b0, conv_mode };
assign nvdla_cmac_a_d_op_enable_0_out[31:0] = { 31'b0, op_en };
assign op_en_trigger = nvdla_cmac_a_d_op_enable_0_wren;
assign reg_offset_rd_int = reg_offset;


always @(
  reg_offset_rd_int
  or nvdla_cmac_a_d_misc_cfg_0_out
  or nvdla_cmac_a_d_op_enable_0_out
  ) begin
  case (reg_offset_rd_int)
     (32'h700c & 32'h00000fff): begin
                            reg_rd_data = nvdla_cmac_a_d_misc_cfg_0_out ;
                            end
     (32'h7008 & 32'h00000fff): begin
                            reg_rd_data = nvdla_cmac_a_d_op_enable_0_out ;
                            end
    default: reg_rd_data = {32{1'b0}};
  endcase
end



always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    conv_mode <= 1'b0;
    proc_precision[1:0] <= 2'b01;
  end else begin

  if (nvdla_cmac_a_d_misc_cfg_0_wren) begin
    conv_mode <= reg_wr_data[0];
  end

  if (nvdla_cmac_a_d_misc_cfg_0_wren) begin
    proc_precision[1:0] <= reg_wr_data[13:12];
  end

  end
end



initial begin
  arreggen_dump = $test$plusargs("arreggen_dump_wr");
  arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr");
  arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr");
`ifdef VERILATOR
`else
  $timeformat(-9, 2, "ns", 15);
`endif
end
always @(posedge nvdla_core_clk) begin
  if (reg_wr_en) begin
    case(reg_offset)
      (32'h700c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CMAC_A_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cmac_a_d_misc_cfg_0_out, nvdla_cmac_a_d_misc_cfg_0_out);
      (32'h7008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CMAC_A_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cmac_a_d_op_enable_0_out, nvdla_cmac_a_d_op_enable_0_out);
      default: begin
          if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data);
          if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end
        end
    endcase
  end
end


endmodule