data/full_repos/permissive/216615048/src/data_mem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/216615048/src/data_mem.v:29: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 9 bits.\n                                                                      : ... In instance DataMem\n                mem[addr+2]<=data_in[24:16];\n                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module DataMem (input clk, input MemRead, input MemWrite, input [31:0] addr,input [2:0]func3, input [31:0] data_in, output reg [31:0]  data_out);
    reg [7:0] mem [(200):0]; 
    
    always @(posedge clk) 
    begin
        if (MemWrite & ~MemRead)
            if (func3 == 3'b010)
            begin
                mem[addr] <= data_in[7:0];
                mem[addr+1]<=data_in[15:8];
                mem[addr+2]<=data_in[24:16];
                mem[addr+3]<=data_in[31:24];
            end

            else if (func3 == 3'b001)
            begin
                mem[addr] <= data_in[7:0];
                mem[addr+1] <= data_in[15:8];
            end
            else if (func3==3'b000)
            mem[addr] <= data_in[7:0];
    end


always @(*)    begin
        if (MemRead & ~MemWrite) begin
            if (func3 == 3'b010)
                data_out={mem[addr+3],mem[addr+2],mem[addr+1],mem[addr]};

            else if (func3 == 3'b001)
                data_out={{16{mem[addr+1][7]}},mem[addr+1],mem[addr]};

            else if (func3 == 3'b101)
                data_out= {16'b0,mem[addr],mem[addr+1]};

            else if (func3 == 3'b100)
                data_out= {24'b0,mem[addr]};

            else if(func3==3'b000)
                data_out={{24{mem[addr][7]}},mem[addr]};
         end
    end
    
    initial begin $readmemh("rars.mem", mem); end  
    
        
      
endmodule
module DataMem (input clk, input MemRead, input MemWrite, input [31:0] addr,input [2:0]func3, input [31:0] data_in, output reg [31:0]  data_out);

    reg [7:0] mem [(200):0]; 
    
    always @(posedge clk) 
    begin
        if (MemWrite & ~MemRead)
            if (func3 == 3'b010)
            begin
                mem[addr] <= data_in[7:0];
                mem[addr+1]<=data_in[15:8];
                mem[addr+2]<=data_in[24:16];
                mem[addr+3]<=data_in[31:24];
            end

            else if (func3 == 3'b001)
            begin
                mem[addr] <= data_in[7:0];
                mem[addr+1] <= data_in[15:8];
            end
            else if (func3==3'b000)
            mem[addr] <= data_in[7:0];
    end


always @(*)    begin
        if (MemRead & ~MemWrite) begin
            if (func3 == 3'b010)
                data_out={mem[addr+3],mem[addr+2],mem[addr+1],mem[addr]};

            else if (func3 == 3'b001)
                data_out={{16{mem[addr+1][7]}},mem[addr+1],mem[addr]};

            else if (func3 == 3'b101)
                data_out= {16'b0,mem[addr],mem[addr+1]};

            else if (func3 == 3'b100)
                data_out= {24'b0,mem[addr]};

            else if(func3==3'b000)
                data_out={{24{mem[addr][7]}},mem[addr]};
         end
    end
    
    initial begin $readmemh("rars.mem", mem); end  
    
        
      
endmodule