data/full_repos/permissive/131358616/test/perceptron_tb.v
 line:57: before: "("
1: b'%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:46: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, perceptron);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\nalways #(clk_pulse_width/2) clk = !clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:54: Unsupported or unknown PLI call: $monitor\n $monitor("Time %d", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:57: syntax error, unexpected \'@\'\n repeat (5) @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:70: Unsupported: wait statements\n wait( rst_n );\n ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:71: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:72: Unsupported or unknown PLI call: $monitor\n $monitor("[Time %d]: Started testbench", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:78: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:85: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:94: syntax error, unexpected \'@\'\n repeat (clk_pulse_width*50) @(negedge clk);\n                             ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:101: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:108: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_tb.v:113: syntax error, unexpected \'@\'\n repeat (clk_pulse_width*200) @(negedge clk);\n                              ^\n%Error: Exiting due to 12 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module perceptron_tb;


localparam clock_frequency	= 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

localparam usart_baud_rate	= 9600;

reg clk, rst_n;


reg [15:0] neur_IN1, neur_IN2;
reg [15:0] neur_weight1_new, neur_weight2_new;
reg neur_weight1_ld, neur_weight2_ld;
wire [15:0] neur_weight1_curr, neur_weight2_curr;
wire [15:0] neur_result;

perceptron perceptron (
	.rst_n(rst_n),
	.clk(clk),
	.IN1(neur_IN1),
	.IN2(neur_IN2),
	.weight1_new(neur_weight1_new),
	.weight2_new(neur_weight2_new),
	.weight1_ld(neur_weight1_ld),
	.weight2_ld(neur_weight2_ld),
	.weight1(neur_weight1_curr),
	.weight2(neur_weight2_curr),
	.result(neur_result)
);



initial begin
    $dumpvars(0, perceptron);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	neur_IN1 = 0;
	neur_IN2 = 0;
	neur_weight1_new = 0; 
	neur_weight2_new = 0;
	neur_weight1_ld = 0; 
	neur_weight2_ld = 0;

	wait( rst_n );
	@(negedge clk);
	$monitor("[Time %d]: Started testbench", $time);
	neur_weight1_new = 8806;
	neur_weight2_new = 3072;
	neur_weight1_ld = 1;
	neur_weight2_ld = 1;

	@(negedge clk);

	neur_weight1_new = 0;
	neur_weight2_new = 0;
	neur_weight1_ld = 0;
	neur_weight2_ld = 0;

	@(negedge clk);

	neur_IN1 = 3522;
	neur_IN2 = 5734;

	



	repeat (clk_pulse_width*50) @(negedge clk);

	neur_weight1_new = 57344;
	neur_weight2_new = 3072;
	neur_weight1_ld = 1;
	neur_weight2_ld = 1;

	@(negedge clk);

	neur_weight1_new = 0;
	neur_weight2_new = 0;
	neur_weight1_ld = 0;
	neur_weight2_ld = 0;

	@(negedge clk);

	neur_IN1 = 8192;
	neur_IN2 = 1024;

	repeat (clk_pulse_width*200) @(negedge clk);

	$finish;
end

endmodule
module perceptron_tb;



localparam clock_frequency	= 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

localparam usart_baud_rate	= 9600;

reg clk, rst_n;


reg [15:0] neur_IN1, neur_IN2;
reg [15:0] neur_weight1_new, neur_weight2_new;
reg neur_weight1_ld, neur_weight2_ld;
wire [15:0] neur_weight1_curr, neur_weight2_curr;
wire [15:0] neur_result;

perceptron perceptron (
	.rst_n(rst_n),
	.clk(clk),
	.IN1(neur_IN1),
	.IN2(neur_IN2),
	.weight1_new(neur_weight1_new),
	.weight2_new(neur_weight2_new),
	.weight1_ld(neur_weight1_ld),
	.weight2_ld(neur_weight2_ld),
	.weight1(neur_weight1_curr),
	.weight2(neur_weight2_curr),
	.result(neur_result)
);



initial begin
    $dumpvars(0, perceptron);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	neur_IN1 = 0;
	neur_IN2 = 0;
	neur_weight1_new = 0; 
	neur_weight2_new = 0;
	neur_weight1_ld = 0; 
	neur_weight2_ld = 0;

	wait( rst_n );
	@(negedge clk);
	$monitor("[Time %d]: Started testbench", $time);
	neur_weight1_new = 8806;
	neur_weight2_new = 3072;
	neur_weight1_ld = 1;
	neur_weight2_ld = 1;

	@(negedge clk);

	neur_weight1_new = 0;
	neur_weight2_new = 0;
	neur_weight1_ld = 0;
	neur_weight2_ld = 0;

	@(negedge clk);

	neur_IN1 = 3522;
	neur_IN2 = 5734;

	



	repeat (clk_pulse_width*50) @(negedge clk);

	neur_weight1_new = 57344;
	neur_weight2_new = 3072;
	neur_weight1_ld = 1;
	neur_weight2_ld = 1;

	@(negedge clk);

	neur_weight1_new = 0;
	neur_weight2_new = 0;
	neur_weight1_ld = 0;
	neur_weight2_ld = 0;

	@(negedge clk);

	neur_IN1 = 8192;
	neur_IN2 = 1024;

	repeat (clk_pulse_width*200) @(negedge clk);

	$finish;
end

endmodule