data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_ams.v
1: b'%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_ams.v:73: Operator EQ expects 20 bits on the RHS, but RHS\'s CONST \'16\'h20\' generates 16 bits.\n                                                                                             : ... In instance red_pitaya_ams\n      if (sys_addr[19:0]==16\'h20)   dac_a_o <= sys_wdata[24-1: 0] ;\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_ams.v:74: Operator EQ expects 20 bits on the RHS, but RHS\'s CONST \'16\'h24\' generates 16 bits.\n                                                                                             : ... In instance red_pitaya_ams\n      if (sys_addr[19:0]==16\'h24)   dac_b_o <= sys_wdata[24-1: 0] ;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_ams.v:75: Operator EQ expects 20 bits on the RHS, but RHS\'s CONST \'16\'h28\' generates 16 bits.\n                                                                                             : ... In instance red_pitaya_ams\n      if (sys_addr[19:0]==16\'h28)   dac_c_o <= sys_wdata[24-1: 0] ;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_ams.v:76: Operator EQ expects 20 bits on the RHS, but RHS\'s CONST \'16\'h2c\' generates 16 bits.\n                                                                                             : ... In instance red_pitaya_ams\n      if (sys_addr[19:0]==16\'h2C)   dac_d_o <= sys_wdata[24-1: 0] ;\n                        ^~\n%Error: Exiting due to 4 warning(s)\n'
module red_pitaya_ams (

   input                 clk_i           ,
   input                 rstn_i          ,

   output reg [ 24-1: 0] dac_a_o         ,
   output reg [ 24-1: 0] dac_b_o         ,
   output reg [ 24-1: 0] dac_c_o         ,
   output reg [ 24-1: 0] dac_d_o         ,

   input      [ 32-1: 0] sys_addr        ,
   input      [ 32-1: 0] sys_wdata       ,
   input      [  4-1: 0] sys_sel         ,
   input                 sys_wen         ,
   input                 sys_ren         ,
   output reg [ 32-1: 0] sys_rdata       ,
   output reg            sys_err         ,
   output reg            sys_ack
);





always @(posedge clk_i)
if (rstn_i == 1'b0) begin
   dac_a_o     <= 24'h0F_0000 ;
   dac_b_o     <= 24'h4E_0000 ;
   dac_c_o     <= 24'h75_0000 ;
   dac_d_o     <= 24'h9C_0000 ;
end else begin
   if (sys_wen) begin
      if (sys_addr[19:0]==16'h20)   dac_a_o <= sys_wdata[24-1: 0] ;
      if (sys_addr[19:0]==16'h24)   dac_b_o <= sys_wdata[24-1: 0] ;
      if (sys_addr[19:0]==16'h28)   dac_c_o <= sys_wdata[24-1: 0] ;
      if (sys_addr[19:0]==16'h2C)   dac_d_o <= sys_wdata[24-1: 0] ;
   end
end

wire sys_en;
assign sys_en = sys_wen | sys_ren;

always @(posedge clk_i)
if (rstn_i == 1'b0) begin
   sys_err <= 1'b0 ;
   sys_ack <= 1'b0 ;
end else begin
   sys_err <= 1'b0 ;
   casez (sys_addr[19:0])
     20'h00020 : begin sys_ack <= sys_en;         sys_rdata <= {{32-24{1'b0}}, dac_a_o}          ; end
     20'h00024 : begin sys_ack <= sys_en;         sys_rdata <= {{32-24{1'b0}}, dac_b_o}          ; end
     20'h00028 : begin sys_ack <= sys_en;         sys_rdata <= {{32-24{1'b0}}, dac_c_o}          ; end
     20'h0002C : begin sys_ack <= sys_en;         sys_rdata <= {{32-24{1'b0}}, dac_d_o}          ; end
       default : begin sys_ack <= sys_en;         sys_rdata <=   32'h0                           ; end
   endcase
end

endmodule
module red_pitaya_ams (

   input                 clk_i           ,
   input                 rstn_i          ,

   output reg [ 24-1: 0] dac_a_o         ,
   output reg [ 24-1: 0] dac_b_o         ,
   output reg [ 24-1: 0] dac_c_o         ,
   output reg [ 24-1: 0] dac_d_o         ,

   input      [ 32-1: 0] sys_addr        ,
   input      [ 32-1: 0] sys_wdata       ,
   input      [  4-1: 0] sys_sel         ,
   input                 sys_wen         ,
   input                 sys_ren         ,
   output reg [ 32-1: 0] sys_rdata       ,
   output reg            sys_err         ,
   output reg            sys_ack
);






always @(posedge clk_i)
if (rstn_i == 1'b0) begin
   dac_a_o     <= 24'h0F_0000 ;
   dac_b_o     <= 24'h4E_0000 ;
   dac_c_o     <= 24'h75_0000 ;
   dac_d_o     <= 24'h9C_0000 ;
end else begin
   if (sys_wen) begin
      if (sys_addr[19:0]==16'h20)   dac_a_o <= sys_wdata[24-1: 0] ;
      if (sys_addr[19:0]==16'h24)   dac_b_o <= sys_wdata[24-1: 0] ;
      if (sys_addr[19:0]==16'h28)   dac_c_o <= sys_wdata[24-1: 0] ;
      if (sys_addr[19:0]==16'h2C)   dac_d_o <= sys_wdata[24-1: 0] ;
   end
end

wire sys_en;
assign sys_en = sys_wen | sys_ren;

always @(posedge clk_i)
if (rstn_i == 1'b0) begin
   sys_err <= 1'b0 ;
   sys_ack <= 1'b0 ;
end else begin
   sys_err <= 1'b0 ;
   casez (sys_addr[19:0])
     20'h00020 : begin sys_ack <= sys_en;         sys_rdata <= {{32-24{1'b0}}, dac_a_o}          ; end
     20'h00024 : begin sys_ack <= sys_en;         sys_rdata <= {{32-24{1'b0}}, dac_b_o}          ; end
     20'h00028 : begin sys_ack <= sys_en;         sys_rdata <= {{32-24{1'b0}}, dac_c_o}          ; end
     20'h0002C : begin sys_ack <= sys_en;         sys_rdata <= {{32-24{1'b0}}, dac_d_o}          ; end
       default : begin sys_ack <= sys_en;         sys_rdata <=   32'h0                           ; end
   endcase
end

endmodule