data/full_repos/permissive/209997170/6. time counter/work/planAhead/decimal selector/decimal selector.srcs/sources_1/imports/verilog/multi_dec_ctr_4.v
1: b'%Error: Cannot find file containing module: time\n        ... Looked in:\n             data/full_repos/permissive/209997170/6./time\n             data/full_repos/permissive/209997170/6./time.v\n             data/full_repos/permissive/209997170/6./time.sv\n             time\n             time.v\n             time.sv\n             obj_dir/time\n             obj_dir/time.v\n             obj_dir/time.sv\n%Error: Cannot find file containing module: counter/work/planAhead/decimal\n%Error: Cannot find file containing module: selector/decimal\n%Error: Cannot find file containing module: selector.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170\n%Error: Cannot find file containing module: data/full_repos/permissive/209997170/6.\n%Error: Cannot find file containing module: selector.srcs/sources_1/imports/verilog/multi_dec_ctr_4.v\n%Error: Exiting due to 6 error(s)\n'
module multi_dec_ctr_4 (
    input clk,
    input rst,
    input inc,
    output reg [15:0] digits
  );
  
  localparam DIGITS = 3'h4;
  
  
  wire [(3'h4+0)-1:0] M_dctr_ovf;
  wire [(3'h4+0)*4-1:0] M_dctr_value;
  reg [(3'h4+0)-1:0] M_dctr_inc;
  
  genvar GEN_dctr0;
  generate
  for (GEN_dctr0=0;GEN_dctr0<3'h4;GEN_dctr0=GEN_dctr0+1) begin: dctr_gen_0
    decimal_counter_9 dctr (
      .clk(clk),
      .rst(rst),
      .inc(M_dctr_inc[GEN_dctr0*(1)+(1)-1-:(1)]),
      .ovf(M_dctr_ovf[GEN_dctr0*(1)+(1)-1-:(1)]),
      .value(M_dctr_value[GEN_dctr0*(3'h4)+(3'h4)-1-:(3'h4)])
    );
  end
  endgenerate
  
  always @* begin
    M_dctr_inc[0+0-:1] = inc;
    digits = M_dctr_value;
    M_dctr_inc[1+2-:3] = M_dctr_ovf[0+2-:3];
  end
endmodule
module multi_dec_ctr_4 (
    input clk,
    input rst,
    input inc,
    output reg [15:0] digits
  );

  
  localparam DIGITS = 3'h4;
  
  
  wire [(3'h4+0)-1:0] M_dctr_ovf;
  wire [(3'h4+0)*4-1:0] M_dctr_value;
  reg [(3'h4+0)-1:0] M_dctr_inc;
  
  genvar GEN_dctr0;
  generate
  for (GEN_dctr0=0;GEN_dctr0<3'h4;GEN_dctr0=GEN_dctr0+1) begin: dctr_gen_0
    decimal_counter_9 dctr (
      .clk(clk),
      .rst(rst),
      .inc(M_dctr_inc[GEN_dctr0*(1)+(1)-1-:(1)]),
      .ovf(M_dctr_ovf[GEN_dctr0*(1)+(1)-1-:(1)]),
      .value(M_dctr_value[GEN_dctr0*(3'h4)+(3'h4)-1-:(3'h4)])
    );
  end
  endgenerate
  
  always @* begin
    M_dctr_inc[0+0-:1] = inc;
    digits = M_dctr_value;
    M_dctr_inc[1+2-:3] = M_dctr_ovf[0+2-:3];
  end
endmodule