data/full_repos/permissive/119557600/cas.v
data/verilator_xmls/54a1ec93-5a12-4f36-95fa-b2f9cd4e6bc6.xml
module cas (divisor, dividend, quotient, cin, cout, remainder);
input wire divisor, dividend, quotient, cin;
output wire cout, remainder;

assign remainder = (quotient ^ divisor) ^ dividend ^ cin;

assign cout = ((quotient ^ divisor)&dividend) | ((quotient ^ divisor)&cin) | (cin&dividend);

endmodule
module cas (divisor, dividend, quotient, cin, cout, remainder);

input wire divisor, dividend, quotient, cin;
output wire cout, remainder;

assign remainder = (quotient ^ divisor) ^ dividend ^ cin;

assign cout = ((quotient ^ divisor)&dividend) | ((quotient ^ divisor)&cin) | (cin&dividend);

endmodule