data/full_repos/permissive/167274925/PCAdder_tb.v
 line:8: before: "mkYZ"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167274925/PCAdder_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167274925/PCAdder_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/PCAdder_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #400;\n ^\n%Error: data/full_repos/permissive/167274925/PCAdder_tb.v:16: Cannot find file containing module: \'PCAdder\'\n    PCAdder u0(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/PCAdder\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/PCAdder.v\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/PCAdder.sv\n             PCAdder\n             PCAdder.v\n             PCAdder.sv\n             obj_dir/PCAdder\n             obj_dir/PCAdder.v\n             obj_dir/PCAdder.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PCAdder_tb();

    reg [31:0] PCResult;

    wire [31:0] PCAddResult;

    PCAdder u0(
        .PCResult(PCResult), 
        .PCAddResult(PCAddResult)
    );

	initial begin
	PCResult<=32'd34;
	#10;
	PCResult<=32'd45;
	#10;
	PCResult<=32'd70;
	#400;
	
         
	
	end

endmodule
module PCAdder_tb();


    reg [31:0] PCResult;

    wire [31:0] PCAddResult;

    PCAdder u0(
        .PCResult(PCResult), 
        .PCAddResult(PCAddResult)
    );

	initial begin
	PCResult<=32'd34;
	#10;
	PCResult<=32'd45;
	#10;
	PCResult<=32'd70;
	#400;
	
         
	
	end

endmodule