data/full_repos/permissive/160035208/hd44780_tb.v
 line:29: before: "+"
1: b'%Error: data/full_repos/permissive/160035208/hd44780_tb.v:20: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("hd44780_wave.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/160035208/hd44780_tb.v:21: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, hd44780_drv);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/160035208/hd44780_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #500;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160035208/hd44780_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #500;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/160035208/hd44780_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #500;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/160035208/hd44780_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/160035208/hd44780_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hd44780_tb;
   reg clk;
   reg rst_n;
   wire lcd_rs;
   wire lcd_rw;
   wire lcd_clk;
   wire [7:0] lcd_data;

   integer    i;

   hd44780 hd44780_drv (.clk(clk),
                        .rst_n(rst_n),
                        .lcd_rs(lcd_rs),
                        .lcd_rw(lcd_rw),
                        .lcd_clk(lcd_clk),
                        .lcd_data(lcd_data));
   initial begin
      $dumpfile("hd44780_wave.vcd");
      $dumpvars(0, hd44780_drv);
      clk <= 0;
      rst_n <= 1;
      #500;
      rst_n <= 0;
      #500;
      rst_n <= 1;
      #500;
      for (i = 0; i < 60000; i++)
        begin
           clk <= 1;
           #500;
           clk <= 0;
           #500;
        end
      $finish;
   end
endmodule
module hd44780_tb;

   reg clk;
   reg rst_n;
   wire lcd_rs;
   wire lcd_rw;
   wire lcd_clk;
   wire [7:0] lcd_data;

   integer    i;

   hd44780 hd44780_drv (.clk(clk),
                        .rst_n(rst_n),
                        .lcd_rs(lcd_rs),
                        .lcd_rw(lcd_rw),
                        .lcd_clk(lcd_clk),
                        .lcd_data(lcd_data));
   initial begin
      $dumpfile("hd44780_wave.vcd");
      $dumpvars(0, hd44780_drv);
      clk <= 0;
      rst_n <= 1;
      #500;
      rst_n <= 0;
      #500;
      rst_n <= 1;
      #500;
      for (i = 0; i < 60000; i++)
        begin
           clk <= 1;
           #500;
           clk <= 0;
           #500;
        end
      $finish;
   end
endmodule