data/full_repos/permissive/128497744/fsm_calculator_part3/Full_Calculator/Full_Calculator.srcs/sources_1/new/Full_Calculator_CU.v
 line:167 column:30: Illegal character "'"
data/verilator_xmls/e8ce7b58-01d2-49d4-8b6d-21c5772676ed.xml
module Full_Calculator_CU(
    input Go, clk, rst,
    input [2:0] F,
    output done,
    
    input Done_Calc, Done_Div,
    output En_F, En_X, En_Y,
    output Go_Calc, Go_Div,
    output [1:0] Op_Calc,
    output Sel_H,
    output [1:0] Sel_L,
    output Calc_Mux_Sel, Mul_Mux_Sel,
    output En_Out_H, En_Out_L,
    output RST_OUT_H, RST_OUT_L,
    output [3:0] cs,
    output Module_Reset
    );
    

    parameter S0 = 4'd0,
              S1 = 4'd1,
              S2 = 4'd2,
              S3 = 4'd3,
              S4 = 4'd4,
              S4p = 4'd5,
              S5 = 4'd6,
              S6 = 4'd7,
              S6p = 4'd8,
              S7 = 4'd9,
              S7p = 4'd10,
              S8 = 4'd11,
              S9 = 4'd12,
              S10 = 4'd13;
              

    reg [3:0] CS, NS;
    


    reg [14:0] cw;

    reg Calc_Mux_Sel_internal, Mul_Mux_Sel_internal;
    reg Sel_H_internal;
    reg [1:0] Sel_L_internal;
    reg [1:0] Calc_Op_internal;
    wire dummy1;
    wire [1:0] dummy2, dummy3;
    reg Module_Reset_Internal;
    
    reg calc;
    

    always @ (CS, Go)
    begin
        case (CS)
            S0: NS <= (Go) ? S1 : S0;
            S1: NS <= S2;
            S2:
                begin
                if (F[2])
                    begin
                        Calc_Mux_Sel_internal <= 1'b1;
                        Mul_Mux_Sel_internal <= 1'b1;   
                    end
                else
                    begin
                        Calc_Mux_Sel_internal <= 1'b0;
                        Mul_Mux_Sel_internal <= 1'b0;
                    end
                
                if (F[2] && F[1] && F[0])
                    begin
                    NS <= S0;
                    end
                else
                    begin
                        if (F[1])
                            begin
                                if (F[0])
                                    begin
                                        NS <= S5;
                                        Sel_L_internal <= 2'b00;
                                        Sel_H_internal <= 1'b0;
                                    end
                                else
                                    begin
                                        NS <= S4;
                                        Sel_L_internal <= 2'b01;
                                        Sel_H_internal <= 1'b1;
                                    end
                            end
                        else
                            begin
                            if (F[0])
                                Calc_Op_internal <= 2'b01;
                            else
                                Calc_Op_internal <= 2'b00;
                            NS <= S3;
                            Sel_L_internal <= 2'b10;
                            Sel_H_internal <= 1'b0;
                            end
                    end
                end
            S3: NS <= S6;
            S4: NS <= S4p;
            S4p: NS <= S8; 
            S5: NS <= S7;
            S6: NS <= (Done_Calc) ? S9 : S6p;
            S6p: NS <= (Done_Calc) ? S9 : S6;
            S7: NS <= (Done_Div) ? S9 : S7p;
            S7p: NS <= (Done_Div) ? S9 : S7;
            S8: NS <= S9;
            S9: NS <= S10;
            S10: NS <= S0;
            
            default: NS <= S0;
        endcase
    end
    

    always @ (posedge clk, posedge rst)
        
        if (rst)
            begin
            CS = S0;

            end







        else
            CS = NS;
            

       always @ (CS)
       begin
           case(CS)               
               S0:
                    begin

                    cw <= 15'b__1_____0_____0_____0________0_______00________0_____00_______0_________0________1__________1________0;
                    calc <= 1'b0;
                    Module_Reset_Internal <= 1'b1; 
                    end
               S1:
                    begin

                    cw <= 15'b__1_____1_____1_____0________0_______00________0_____00_______0_________0________0__________0________0;
                    Module_Reset_Internal <= 1'b1; 
                    
                    end
               S2:
                    begin

                    cw <= 15'b__1_____0_____0_____0________0_______00________0_____00_______0_________0________0__________0________0;
                    Module_Reset_Internal <= 1'b0; 
                    end
               S3:
                    begin
                    if (F[0])
                    begin

                    cw <= 15'b__0_____0_____0_____1________0_______01________0_____00_______0_________0________0___________0________0;
                    end
                    else
                    begin

                    cw <= 15'b__0_____0_____0_____1________0_______00________0_____00_______0_________0________0___________0________0;                    
                    end                         
                    end
               S4:
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0___________0________0;                    
                    end
               S4p:
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0___________0________0;                    
                    end
               S5:
                    begin

                    cw <= 15'b__0_____0_____0_____0________1_______00________0_____00_______0_________0________0___________0________0;                    
                    end
               S6:
                    begin
                    if (NS == S9)
                    begin
                        if (F[0])
                        begin

                            cw <= 15'b__0_____0_____0_____0________0_______01________0_____10_______0_________0________0__________0_________0;
                        end
                        else
                        begin

                            cw <= 15'b__0_____0_____0_____0________0_______00________0_____10_______0_________0________0__________0_________0;
                        end                    
                    end
                    else
                    begin
                        if (F[0])
                        begin

                            cw <= 15'b__0_____0_____0_____0________0_______01________0_____10_______0_________0________0__________0_________0;                    
                        end
                        else
                        begin

                            cw <= 15'b__0_____0_____0_____0________0_______00________0_____10_______0_________0________0__________0_________0;
                        end
                    end                    
                    end
               S6p: begin
                    if (NS == S9)
                       begin
                           if (F[0])
                           begin

                               cw <= 15'b__0_____0_____0_____0________0_______01________0_____10_______0_________0________0__________0_________0;
                           end
                           else
                           begin

                               cw <= 15'b__0_____0_____0_____0________0_______00________0_____10_______0_________0________0__________0_________0;
                           end                    
                       end
                       else
                       begin
                           if (F[0])
                           begin

                               cw <= 15'b__0_____0_____0_____0________0_______01________0_____10_______0_________0________0__________0_________0;                    
                           end
                           else
                           begin

                               cw <= 15'b__0_____0_____0_____0________0_______00________0_____10_______0_________0________0__________0_________0;
                           end
                       end                    
                       end
               S7:
                    begin
                     if (Done_Div)
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0__________0_________0;                    
                    end
                    else
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0__________0_________0;                    
                    end                                       
                    end
                S7p:
                   begin
                    if (Done_Div)
                   begin

                   cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0__________0_________0;                    
                   end
                   else
                   begin

                   cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0__________0_________0;                    
                   end                                       
                   end
               S8:
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________1_____01_______0_________0________0__________0_________0;                    
                    end
               S9:
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______1_________1_______0___________0_________0;                    
                    end
              S10:
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______1_________1_______0___________0_________1;
                    Module_Reset_Internal <= 1'b1;                    
                    end
            endcase
        end
        
        assign {En_F, En_X, En_Y, Go_Calc, Go_Div, dummy3, dummy1, dummy2, En_Out_H, En_Out_L, RST_OUT_H, RST_OUT_L, done} = cw;
        assign Calc_Mux_Sel = Calc_Mux_Sel_internal;
        assign Mul_Mux_Sel = Mul_Mux_Sel_internal;
        assign Sel_H = Sel_H_internal;
        assign Sel_L = Sel_L_internal;
        assign Op_Calc = Calc_Op_internal;
        assign Module_Reset = Module_Reset_Internal;
        assign cs = CS;
                

                

endmodule
module Full_Calculator_CU(
    input Go, clk, rst,
    input [2:0] F,
    output done,
    
    input Done_Calc, Done_Div,
    output En_F, En_X, En_Y,
    output Go_Calc, Go_Div,
    output [1:0] Op_Calc,
    output Sel_H,
    output [1:0] Sel_L,
    output Calc_Mux_Sel, Mul_Mux_Sel,
    output En_Out_H, En_Out_L,
    output RST_OUT_H, RST_OUT_L,
    output [3:0] cs,
    output Module_Reset
    );

    

    parameter S0 = 4'd0,
              S1 = 4'd1,
              S2 = 4'd2,
              S3 = 4'd3,
              S4 = 4'd4,
              S4p = 4'd5,
              S5 = 4'd6,
              S6 = 4'd7,
              S6p = 4'd8,
              S7 = 4'd9,
              S7p = 4'd10,
              S8 = 4'd11,
              S9 = 4'd12,
              S10 = 4'd13;
              

    reg [3:0] CS, NS;
    


    reg [14:0] cw;

    reg Calc_Mux_Sel_internal, Mul_Mux_Sel_internal;
    reg Sel_H_internal;
    reg [1:0] Sel_L_internal;
    reg [1:0] Calc_Op_internal;
    wire dummy1;
    wire [1:0] dummy2, dummy3;
    reg Module_Reset_Internal;
    
    reg calc;
    

    always @ (CS, Go)
    begin
        case (CS)
            S0: NS <= (Go) ? S1 : S0;
            S1: NS <= S2;
            S2:
                begin
                if (F[2])
                    begin
                        Calc_Mux_Sel_internal <= 1'b1;
                        Mul_Mux_Sel_internal <= 1'b1;   
                    end
                else
                    begin
                        Calc_Mux_Sel_internal <= 1'b0;
                        Mul_Mux_Sel_internal <= 1'b0;
                    end
                
                if (F[2] && F[1] && F[0])
                    begin
                    NS <= S0;
                    end
                else
                    begin
                        if (F[1])
                            begin
                                if (F[0])
                                    begin
                                        NS <= S5;
                                        Sel_L_internal <= 2'b00;
                                        Sel_H_internal <= 1'b0;
                                    end
                                else
                                    begin
                                        NS <= S4;
                                        Sel_L_internal <= 2'b01;
                                        Sel_H_internal <= 1'b1;
                                    end
                            end
                        else
                            begin
                            if (F[0])
                                Calc_Op_internal <= 2'b01;
                            else
                                Calc_Op_internal <= 2'b00;
                            NS <= S3;
                            Sel_L_internal <= 2'b10;
                            Sel_H_internal <= 1'b0;
                            end
                    end
                end
            S3: NS <= S6;
            S4: NS <= S4p;
            S4p: NS <= S8; 
            S5: NS <= S7;
            S6: NS <= (Done_Calc) ? S9 : S6p;
            S6p: NS <= (Done_Calc) ? S9 : S6;
            S7: NS <= (Done_Div) ? S9 : S7p;
            S7p: NS <= (Done_Div) ? S9 : S7;
            S8: NS <= S9;
            S9: NS <= S10;
            S10: NS <= S0;
            
            default: NS <= S0;
        endcase
    end
    

    always @ (posedge clk, posedge rst)
        
        if (rst)
            begin
            CS = S0;

            end







        else
            CS = NS;
            

       always @ (CS)
       begin
           case(CS)               
               S0:
                    begin

                    cw <= 15'b__1_____0_____0_____0________0_______00________0_____00_______0_________0________1__________1________0;
                    calc <= 1'b0;
                    Module_Reset_Internal <= 1'b1; 
                    end
               S1:
                    begin

                    cw <= 15'b__1_____1_____1_____0________0_______00________0_____00_______0_________0________0__________0________0;
                    Module_Reset_Internal <= 1'b1; 
                    
                    end
               S2:
                    begin

                    cw <= 15'b__1_____0_____0_____0________0_______00________0_____00_______0_________0________0__________0________0;
                    Module_Reset_Internal <= 1'b0; 
                    end
               S3:
                    begin
                    if (F[0])
                    begin

                    cw <= 15'b__0_____0_____0_____1________0_______01________0_____00_______0_________0________0___________0________0;
                    end
                    else
                    begin

                    cw <= 15'b__0_____0_____0_____1________0_______00________0_____00_______0_________0________0___________0________0;                    
                    end                         
                    end
               S4:
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0___________0________0;                    
                    end
               S4p:
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0___________0________0;                    
                    end
               S5:
                    begin

                    cw <= 15'b__0_____0_____0_____0________1_______00________0_____00_______0_________0________0___________0________0;                    
                    end
               S6:
                    begin
                    if (NS == S9)
                    begin
                        if (F[0])
                        begin

                            cw <= 15'b__0_____0_____0_____0________0_______01________0_____10_______0_________0________0__________0_________0;
                        end
                        else
                        begin

                            cw <= 15'b__0_____0_____0_____0________0_______00________0_____10_______0_________0________0__________0_________0;
                        end                    
                    end
                    else
                    begin
                        if (F[0])
                        begin

                            cw <= 15'b__0_____0_____0_____0________0_______01________0_____10_______0_________0________0__________0_________0;                    
                        end
                        else
                        begin

                            cw <= 15'b__0_____0_____0_____0________0_______00________0_____10_______0_________0________0__________0_________0;
                        end
                    end                    
                    end
               S6p: begin
                    if (NS == S9)
                       begin
                           if (F[0])
                           begin

                               cw <= 15'b__0_____0_____0_____0________0_______01________0_____10_______0_________0________0__________0_________0;
                           end
                           else
                           begin

                               cw <= 15'b__0_____0_____0_____0________0_______00________0_____10_______0_________0________0__________0_________0;
                           end                    
                       end
                       else
                       begin
                           if (F[0])
                           begin

                               cw <= 15'b__0_____0_____0_____0________0_______01________0_____10_______0_________0________0__________0_________0;                    
                           end
                           else
                           begin

                               cw <= 15'b__0_____0_____0_____0________0_______00________0_____10_______0_________0________0__________0_________0;
                           end
                       end                    
                       end
               S7:
                    begin
                     if (Done_Div)
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0__________0_________0;                    
                    end
                    else
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0__________0_________0;                    
                    end                                       
                    end
                S7p:
                   begin
                    if (Done_Div)
                   begin

                   cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0__________0_________0;                    
                   end
                   else
                   begin

                   cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______0_________0________0__________0_________0;                    
                   end                                       
                   end
               S8:
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________1_____01_______0_________0________0__________0_________0;                    
                    end
               S9:
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______1_________1_______0___________0_________0;                    
                    end
              S10:
                    begin

                    cw <= 15'b__0_____0_____0_____0________0_______00________0_____00_______1_________1_______0___________0_________1;
                    Module_Reset_Internal <= 1'b1;                    
                    end
            endcase
        end
        
        assign {En_F, En_X, En_Y, Go_Calc, Go_Div, dummy3, dummy1, dummy2, En_Out_H, En_Out_L, RST_OUT_H, RST_OUT_L, done} = cw;
        assign Calc_Mux_Sel = Calc_Mux_Sel_internal;
        assign Mul_Mux_Sel = Mul_Mux_Sel_internal;
        assign Sel_H = Sel_H_internal;
        assign Sel_L = Sel_L_internal;
        assign Op_Calc = Calc_Op_internal;
        assign Module_Reset = Module_Reset_Internal;
        assign cs = CS;
                

                

endmodule