data/full_repos/permissive/143278/ivltests/pr528.v
 line:14: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr528.v:11: Unsupported: Ignoring delay on this delayed statement.\n    always  #5000 clk = ~ clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr528.v:13: Unsupported or unknown PLI call: $monitor\n    initial $monitor( "%T %b %b %b", $time, clk, clko1, clko2 );\n            ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr528.v:14: Unsupported: Ignoring delay on this delayed statement.\n    initial #50001 $finish(0);\n            ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester;
    wire  clko1, clko2;
    reg   clk;

    assign #50 clko1 = clk & 1'b1;
    assign #50 clko2 = clk;

    initial       clk = 1'b0;
    always  #5000 clk = ~ clk;

    initial $monitor( "%T %b %b %b", $time, clk, clko1, clko2 );
    initial #50001 $finish(0);
endmodule
module tester;

    wire  clko1, clko2;
    reg   clk;

    assign #50 clko1 = clk & 1'b1;
    assign #50 clko2 = clk;

    initial       clk = 1'b0;
    always  #5000 clk = ~ clk;

    initial $monitor( "%T %b %b %b", $time, clk, clko1, clko2 );
    initial #50001 $finish(0);
endmodule