data/full_repos/permissive/166115772/old_attempt/verilog/program_counter.v
 line:47: before: "/"
1: b'%Warning-LITENDIAN: data/full_repos/permissive/166115772/old_attempt/verilog/program_counter.v:2: Little bit endian vector: MSB < LSB of bit range: 0:15\n    input [0:15] data,\n          ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/old_attempt/verilog/program_counter.v:4: Little bit endian vector: MSB < LSB of bit range: 0:15\n    output [0:15] count\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/old_attempt/verilog/program_counter.v:6: Little bit endian vector: MSB < LSB of bit range: 0:15\n    reg [0:15] counterReg;\n        ^\n%Error: Exiting due to 3 warning(s)\n'
module programCounter (
    input [0:15] data,
    input load, clk, reset,
    output [0:15] count
);
    reg [0:15] counterReg;
    assign count = counterReg;

    initial
        counterReg <= 0;

    always @(posedge clk or posedge reset) begin
        if(reset)
            counterReg <= 16'd0;
        else
            if (load)
                counterReg <= data;
            else
                counterReg <= counterReg + 16'd1;
    end
endmodule
module programCounter (
    input [0:15] data,
    input load, clk, reset,
    output [0:15] count
);

    reg [0:15] counterReg;
    assign count = counterReg;

    initial
        counterReg <= 0;

    always @(posedge clk or posedge reset) begin
        if(reset)
            counterReg <= 16'd0;
        else
            if (load)
                counterReg <= data;
            else
                counterReg <= counterReg + 16'd1;
    end
endmodule