data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:29: Cannot find include file: cypress.v\n`include "cypress.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0,data/full_repos/permissive/105824537/cypress.v\n             data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0,data/full_repos/permissive/105824537/cypress.v.v\n             data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0,data/full_repos/permissive/105824537/cypress.v.sv\n             cypress.v\n             cypress.v.v\n             cypress.v.sv\n             obj_dir/cypress.v\n             obj_dir/cypress.v.v\n             obj_dir/cypress.v.sv\n%Warning-WIDTH: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:70: Value too large for 2 bit number: 10\n  localparam CTRL_BUS     = 2\'d10;   \n                            ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:163: Define or directive not defined: \'`FALSE\'\n    cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE))    \n                                                ^~~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:176: Define or directive not defined: \'`TRUE\'\n        cy_psoc3_control #(.cy_force_order(`TRUE))           \n                                           ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:269: Define or directive not defined: \'`TRUE\'\n            cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE))   \n                                                                       ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:273: Define or directive not defined: \'`TRUE\'\n            cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE))   \n                                                                       ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:277: Define or directive not defined: \'`TRUE\'\n            cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE))   \n                                                                       ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:282: Define or directive not defined: \'`TRUE\'\n            cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE))   \n                                                                       ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:289: Define or directive not defined: \'`TRUE\'\n            cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8\'h00), .cy_ctrl_mode_0(8\'hFF))  \n                                                                       ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:294: Define or directive not defined: \'`TRUE\'\n            cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8\'h00), .cy_ctrl_mode_0(8\'hFF))  \n                                                                       ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:299: Define or directive not defined: \'`TRUE\'\n            cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8\'h00), .cy_ctrl_mode_0(8\'hFF))  \n                                                                       ^~~~~\n%Error: data/full_repos/permissive/105824537/DDS24_lib.cylib/DDS24_Core_v0_0/DDS24_Core_v0_0.v:305: Define or directive not defined: \'`TRUE\'\n            cy_psoc3_control #(.cy_init_value (8\'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8\'h00), .cy_ctrl_mode_0(8\'hFF))  \n                                                                       ^~~~~\n%Error: Exiting due to 11 error(s), 1 warning(s)\n'
module DDS24_Core_v0_0( load, en, ctrl, phase, clock, out1, out2, rdy1, rdy2, rfd );


  
  parameter   out1_width = 8'd8;
  parameter   out2_width = 8'd8;
  localparam  Hi1 = out1_width-1;
  localparam  Hi2 = out2_width-1;



  input  wire           load;
  input  wire           en;
  input  wire [22:0]    ctrl;
  input  wire [7:0]     phase;
  input  wire           clock;
  output wire [Hi1:0]   out1;
  output wire [Hi2:0]   out2;
  output wire           rdy1;
  output wire           rdy2;
  output wire           rfd;
  
  
  

  
  parameter out2_enable   = 1'b0;
  parameter hw_load       = 1'b0;
  parameter tune_word_h   = 23'd1;
  parameter out2_phase_h  = 8'd0;
  
  localparam CTRL_API     = 2'b00;
  localparam CTRL_HARDC   = 2'b01;
  localparam CTRL_BUS     = 2'd10;
  parameter [1:0] ControlFreq  = CTRL_API;
  parameter [1:0] ControlPhase = CTRL_API;
  
  localparam ENMODE_AUTO   = 2'b00;
  localparam ENMODE_CRONLY = 2'b01;
  localparam ENMODE_HWONLY = 2'b10;
  localparam ENMODE_CR_HW  = 2'b11;
  parameter [1:0] EnableMode = ENMODE_CRONLY;
  
  
  

  
  wire [22:0] tune_word;
  wire [7:0]  controlD;
  wire        ClockOutFromEnBlock;








 
    reg  [23:0]   Acc;
    reg  [23:16]  Ac1;
    reg  [23:16]  Ac2;
   
    generate
    if(out2_enable==1'b1)
    begin 
        always @(posedge ClockOutFromEnBlock) begin	
            Acc <= Acc+tune_word;
            Ac1 <= Acc[23:16];
            Ac2 <= Acc[23:16]+controlD;
        end 

        assign out1 = Ac1[23:(23-Hi1)];
        assign out2 = Ac2[23:(23-Hi2)];
    end
    else begin
        always @(posedge ClockOutFromEnBlock) begin	
            Acc <= Acc+tune_word;
        end  
        assign out1 = Acc[23:(23-Hi1)];
    end
    endgenerate

     
     






    reg [Hi1:0] out1_old;
    reg [Hi2:0] out2_old;
    
    generate
    if(out2_enable==1'b1)
    begin 
        always @(posedge ClockOutFromEnBlock) 	   
        begin
           out1_old <= out1;
           out2_old <= out2;
        end
        assign rdy1 = |(out1 ^ out1_old) & ~clock;
        assign rdy2 = |(out2 ^ out2_old) & ~clock;
    end
    else begin
        always @(posedge ClockOutFromEnBlock) 	    
        begin
           out1_old <= out1;
        end
        assign rdy1 = |(out1 ^ out1_old) & ~clock;
    end
    endgenerate
    







    
    
    wire clock_en;
    

    cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE))
    clock_enable_block (
                        .clock_out(ClockOutFromEnBlock),
                        .clock_in(clock),
                        .enable(clock_en)
    );
    
                                                     
    localparam CLOCK_ENABLE_BIT   = 1'd0;
    wire [7:0] ctrl8;
    
    generate
    if( (EnableMode == ENMODE_CRONLY) || (EnableMode == ENMODE_CR_HW) ) begin : sCTRLReg 
        cy_psoc3_control #(.cy_force_order(`TRUE))
            ctrlreg( .control(ctrl8) );
    end
    endgenerate
    
    wire control_enable; assign control_enable = ctrl8[CLOCK_ENABLE_BIT];

    assign clock_en = (EnableMode == ENMODE_AUTO)?   1'b1:
                      (EnableMode == ENMODE_CRONLY)? control_enable:
                      (EnableMode == ENMODE_CR_HW)? (control_enable & en):
                                                     en;
    
    
    





   
    

    generate
    if (hw_load==1'b1) begin
        wire s_load;
        cy_psoc3_sync HWLoadSync (
                .clock	(ClockOutFromEnBlock),
    			.sc_in	(load),
	    		.sc_out	(s_load));
                         
        assign rfd = s_load;
    end
    endgenerate

    


                                    
                                   
                                    






    
    wire [23:0]  control_cr;
    wire [7:0]   controlD_cr;



    generate  
    if (ControlFreq==CTRL_API)   assign tune_word = control_cr[22:0];  else
    if (ControlFreq==CTRL_HARDC) assign tune_word = tune_word_h;       else

        if (hw_load==1'd0)
            assign tune_word = ctrl[22:0];
        else begin
            reg[22:0] r_ctrl; always @(posedge load) r_ctrl <= ctrl[22:0];
            assign tune_word = r_ctrl;
        end
    endgenerate 
    


    generate  
    if (ControlPhase==CTRL_API)   assign controlD = controlD_cr;       else
    if (ControlPhase==CTRL_HARDC) assign controlD = out2_phase_h;      else

        if (hw_load==1'd0)
            assign controlD = phase;
        else begin
            reg[7:0] r_phase; always @(posedge load) r_phase <= phase;
            assign controlD = r_phase;
        end
    endgenerate 
    
    











    generate                                
    if (hw_load==1'b0) begin: sControl
 
            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
            ControlPhaseA(
                .control(control_cr[7:0]));

            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
            ControlPhaseB(
                .control(control_cr[15:8]));
    
            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
            ControlPhaseC(
                .control(control_cr[23:16]));
               

            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
            ControlPhaseD(
                .control(controlD_cr));
        
    end
    else begin: sControl

            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
            ControlPhaseA(
                .control(control_cr[7:0]),
                .clock(load)            );
            
            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
            ControlPhaseB(
                .control(control_cr[15:8]),
                .clock(load)             );
    
            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
            ControlPhaseC(
                .control(control_cr[23:16]),
                .clock(load)              );
               

            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
            ControlPhaseD(
                .control(controlD_cr),
                .clock(load)        );

    end
    endgenerate
   






endmodule
module DDS24_Core_v0_0( load, en, ctrl, phase, clock, out1, out2, rdy1, rdy2, rfd );



  
  parameter   out1_width = 8'd8;
  parameter   out2_width = 8'd8;
  localparam  Hi1 = out1_width-1;
  localparam  Hi2 = out2_width-1;



  input  wire           load;
  input  wire           en;
  input  wire [22:0]    ctrl;
  input  wire [7:0]     phase;
  input  wire           clock;
  output wire [Hi1:0]   out1;
  output wire [Hi2:0]   out2;
  output wire           rdy1;
  output wire           rdy2;
  output wire           rfd;
  
  
  

  
  parameter out2_enable   = 1'b0;
  parameter hw_load       = 1'b0;
  parameter tune_word_h   = 23'd1;
  parameter out2_phase_h  = 8'd0;
  
  localparam CTRL_API     = 2'b00;
  localparam CTRL_HARDC   = 2'b01;
  localparam CTRL_BUS     = 2'd10;
  parameter [1:0] ControlFreq  = CTRL_API;
  parameter [1:0] ControlPhase = CTRL_API;
  
  localparam ENMODE_AUTO   = 2'b00;
  localparam ENMODE_CRONLY = 2'b01;
  localparam ENMODE_HWONLY = 2'b10;
  localparam ENMODE_CR_HW  = 2'b11;
  parameter [1:0] EnableMode = ENMODE_CRONLY;
  
  
  

  
  wire [22:0] tune_word;
  wire [7:0]  controlD;
  wire        ClockOutFromEnBlock;








 
    reg  [23:0]   Acc;
    reg  [23:16]  Ac1;
    reg  [23:16]  Ac2;
   
    generate
    if(out2_enable==1'b1)
    begin 
        always @(posedge ClockOutFromEnBlock) begin	
            Acc <= Acc+tune_word;
            Ac1 <= Acc[23:16];
            Ac2 <= Acc[23:16]+controlD;
        end 

        assign out1 = Ac1[23:(23-Hi1)];
        assign out2 = Ac2[23:(23-Hi2)];
    end
    else begin
        always @(posedge ClockOutFromEnBlock) begin	
            Acc <= Acc+tune_word;
        end  
        assign out1 = Acc[23:(23-Hi1)];
    end
    endgenerate

     
     






    reg [Hi1:0] out1_old;
    reg [Hi2:0] out2_old;
    
    generate
    if(out2_enable==1'b1)
    begin 
        always @(posedge ClockOutFromEnBlock) 	   
        begin
           out1_old <= out1;
           out2_old <= out2;
        end
        assign rdy1 = |(out1 ^ out1_old) & ~clock;
        assign rdy2 = |(out2 ^ out2_old) & ~clock;
    end
    else begin
        always @(posedge ClockOutFromEnBlock) 	    
        begin
           out1_old <= out1;
        end
        assign rdy1 = |(out1 ^ out1_old) & ~clock;
    end
    endgenerate
    







    
    
    wire clock_en;
    

    cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE))
    clock_enable_block (
                        .clock_out(ClockOutFromEnBlock),
                        .clock_in(clock),
                        .enable(clock_en)
    );
    
                                                     
    localparam CLOCK_ENABLE_BIT   = 1'd0;
    wire [7:0] ctrl8;
    
    generate
    if( (EnableMode == ENMODE_CRONLY) || (EnableMode == ENMODE_CR_HW) ) begin : sCTRLReg 
        cy_psoc3_control #(.cy_force_order(`TRUE))
            ctrlreg( .control(ctrl8) );
    end
    endgenerate
    
    wire control_enable; assign control_enable = ctrl8[CLOCK_ENABLE_BIT];

    assign clock_en = (EnableMode == ENMODE_AUTO)?   1'b1:
                      (EnableMode == ENMODE_CRONLY)? control_enable:
                      (EnableMode == ENMODE_CR_HW)? (control_enable & en):
                                                     en;
    
    
    





   
    

    generate
    if (hw_load==1'b1) begin
        wire s_load;
        cy_psoc3_sync HWLoadSync (
                .clock	(ClockOutFromEnBlock),
    			.sc_in	(load),
	    		.sc_out	(s_load));
                         
        assign rfd = s_load;
    end
    endgenerate

    


                                    
                                   
                                    






    
    wire [23:0]  control_cr;
    wire [7:0]   controlD_cr;



    generate  
    if (ControlFreq==CTRL_API)   assign tune_word = control_cr[22:0];  else
    if (ControlFreq==CTRL_HARDC) assign tune_word = tune_word_h;       else

        if (hw_load==1'd0)
            assign tune_word = ctrl[22:0];
        else begin
            reg[22:0] r_ctrl; always @(posedge load) r_ctrl <= ctrl[22:0];
            assign tune_word = r_ctrl;
        end
    endgenerate 
    


    generate  
    if (ControlPhase==CTRL_API)   assign controlD = controlD_cr;       else
    if (ControlPhase==CTRL_HARDC) assign controlD = out2_phase_h;      else

        if (hw_load==1'd0)
            assign controlD = phase;
        else begin
            reg[7:0] r_phase; always @(posedge load) r_phase <= phase;
            assign controlD = r_phase;
        end
    endgenerate 
    
    











    generate                                
    if (hw_load==1'b0) begin: sControl
 
            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
            ControlPhaseA(
                .control(control_cr[7:0]));

            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
            ControlPhaseB(
                .control(control_cr[15:8]));
    
            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
            ControlPhaseC(
                .control(control_cr[23:16]));
               

            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE))
            ControlPhaseD(
                .control(controlD_cr));
        
    end
    else begin: sControl

            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
            ControlPhaseA(
                .control(control_cr[7:0]),
                .clock(load)            );
            
            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
            ControlPhaseB(
                .control(control_cr[15:8]),
                .clock(load)             );
    
            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
            ControlPhaseC(
                .control(control_cr[23:16]),
                .clock(load)              );
               

            cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
            ControlPhaseD(
                .control(controlD_cr),
                .clock(load)        );

    end
    endgenerate
   






endmodule