data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/exmem.v
 line:42: before: "input"
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/exmem.v\n%Error: Exiting due to 4 error(s)\n'
module exmem #(parameter WIDTH = 16, RAM_ADDR_BITS = 14)
   (input clk, en,
    input memwrite,
    input [RAM_ADDR_BITS-1:0] adr,
    input [WIDTH-1:0] writedata,
    output reg [WIDTH-1:0] memdata,
	 input pxlClk,
	 input [13:0] glyphAdd,
	 output reg [15:0] glyphData
    );

   reg [WIDTH-1:0] mips_ram [(2**RAM_ADDR_BITS)-1:0];










 
initial
$readmemb("testInitLevel.bin", mips_ram);





   always @(posedge clk)
      if (en) begin
         if (memwrite)
            mips_ram[adr] <= writedata;
         memdata <= mips_ram[adr];
      end
		
   always @(posedge pxlClk)
      if (en) begin
         glyphData <= mips_ram[glyphAdd];
      end
							
						
endmodule
module exmem #(parameter WIDTH = 16, RAM_ADDR_BITS = 14)
   (input clk, en,
    input memwrite,
    input [RAM_ADDR_BITS-1:0] adr,
    input [WIDTH-1:0] writedata,
    output reg [WIDTH-1:0] memdata,
	 input pxlClk,
	 input [13:0] glyphAdd,
	 output reg [15:0] glyphData
    );


   reg [WIDTH-1:0] mips_ram [(2**RAM_ADDR_BITS)-1:0];










 
initial
$readmemb("testInitLevel.bin", mips_ram);





   always @(posedge clk)
      if (en) begin
         if (memwrite)
            mips_ram[adr] <= writedata;
         memdata <= mips_ram[adr];
      end
		
   always @(posedge pxlClk)
      if (en) begin
         glyphData <= mips_ram[glyphAdd];
      end
							
						
endmodule