data/full_repos/permissive/121864698/TestBench.v
 line:52: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/121864698/TestBench.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #40$finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121864698/TestBench.v:57: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = !clk;\n        ^\n%Error: data/full_repos/permissive/121864698/TestBench.v:41: Cannot find file containing module: \'risc\'\n risc uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/121864698,data/full_repos/permissive/121864698/risc\n             data/full_repos/permissive/121864698,data/full_repos/permissive/121864698/risc.v\n             data/full_repos/permissive/121864698,data/full_repos/permissive/121864698/risc.sv\n             risc\n             risc.v\n             risc.sv\n             obj_dir/risc\n             obj_dir/risc.v\n             obj_dir/risc.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module JIZ;


 reg clk;
 reg reset;


 risc uut (
  .clk(clk), 
  .reset(reset)
 );

 initial begin

  clk = 0;
  reset = 0;


  #40$finish;
        


 end
 always #1 clk = !clk;
      
endmodule
module JIZ;



 reg clk;
 reg reset;


 risc uut (
  .clk(clk), 
  .reset(reset)
 );

 initial begin

  clk = 0;
  reset = 0;


  #40$finish;
        


 end
 always #1 clk = !clk;
      
endmodule