data/full_repos/permissive/109846502/ctndek.v
data/verilator_xmls/b3b9bfcd-560f-4394-bc68-4146c2bc31e9.xml
module ctndek(
			input clk,
			input rst,
			input en,
			output reg ovl,
			output reg [3:0] out
    );
always @(posedge clk, posedge rst)
begin
	if(rst)
		out <= 4'd0;
	else if(en)
		if(out == 4'd9)
			out <= 4'd0;
		else
			out <= out + 1;
end
	 
always @(posedge clk, posedge rst)
begin
	if(rst)
		ovl <= 1'b0;
	else
		if (out == 4'd9)
			ovl <= 1'b1;
		else
			ovl <= 1'b0;
end


endmodule
module ctndek(
			input clk,
			input rst,
			input en,
			output reg ovl,
			output reg [3:0] out
    );

always @(posedge clk, posedge rst)
begin
	if(rst)
		out <= 4'd0;
	else if(en)
		if(out == 4'd9)
			out <= 4'd0;
		else
			out <= out + 1;
end
	 
always @(posedge clk, posedge rst)
begin
	if(rst)
		ovl <= 1'b0;
	else
		if (out == 4'd9)
			ovl <= 1'b1;
		else
			ovl <= 1'b0;
end


endmodule