data/full_repos/permissive/158922207/Verilog Design/modules/SimpleRegister.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/SimpleRegister.v\n%Error: Exiting due to 3 error(s)\n'
module simplereg(dataOut, dataIn, W_en, reset, clock);
parameter N = 32;
input W_en, reset, clock;
input [N-1:0] dataIn;
output [N-1:0] dataOut;
reg [N-1:0] mem;

assign dataOut = mem;
always @(posedge clock or posedge reset) begin
if (reset)
    mem <= 0;
else begin
    if(W_en)
       mem <= dataIn;
end
end
endmodule
module simplereg(dataOut, dataIn, W_en, reset, clock);

parameter N = 32;
input W_en, reset, clock;
input [N-1:0] dataIn;
output [N-1:0] dataOut;
reg [N-1:0] mem;

assign dataOut = mem;
always @(posedge clock or posedge reset) begin
if (reset)
    mem <= 0;
else begin
    if(W_en)
       mem <= dataIn;
end
end
endmodule