data/full_repos/permissive/128566293/Sources/verilog/VfD_prescaler.v
1: b'%Warning-WIDTH: data/full_repos/permissive/128566293/Sources/verilog/VfD_prescaler.v:18: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'divider\' generates 32 bits.\n                                                                                       : ... In instance VfD_prescaler\n    assign w_zero = (divider)? 0: 1;\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module VfD_prescaler (

    output          o_clk,

    input           clk
);


    parameter       f_clkin = 12_000_000;
    parameter       f_clkout = 2;



    integer         divider = 0;

    wire            w_zero;

    assign w_zero = (divider)? 0: 1;

always @ (posedge clk)
begin
    if (w_zero)
        begin

        divider <= (f_clkin / f_clkout)/2;
        end
    else
        divider <= divider - 1;
end



    reg             r_toggle = ~0;

always @ (posedge clk)
begin
        r_toggle <= (w_zero)? !r_toggle: r_toggle;
end


assign o_clk = r_toggle;

endmodule
module VfD_prescaler (

    output          o_clk,

    input           clk
);



    parameter       f_clkin = 12_000_000;
    parameter       f_clkout = 2;



    integer         divider = 0;

    wire            w_zero;

    assign w_zero = (divider)? 0: 1;

always @ (posedge clk)
begin
    if (w_zero)
        begin

        divider <= (f_clkin / f_clkout)/2;
        end
    else
        divider <= divider - 1;
end



    reg             r_toggle = ~0;

always @ (posedge clk)
begin
        r_toggle <= (w_zero)? !r_toggle: r_toggle;
end


assign o_clk = r_toggle;

endmodule