data/full_repos/permissive/166661632/p4/P4/DATAPATH.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:2: Cannot find include file: head.v\n`include "head.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166661632/p4/P4,data/full_repos/permissive/166661632/head.v\n             data/full_repos/permissive/166661632/p4/P4,data/full_repos/permissive/166661632/head.v.v\n             data/full_repos/permissive/166661632/p4/P4,data/full_repos/permissive/166661632/head.v.sv\n             head.v\n             head.v.v\n             head.v.sv\n             obj_dir/head.v\n             obj_dir/head.v.v\n             obj_dir/head.v.sv\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:45: Define or directive not defined: \'`alusrc_rd2\'\nassign alubdata=(alusrc==`alusrc_rd2)?rd2:extout;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign alubdata=(alusrc==`alusrc_rd2)?rd2:extout;\n                                    ^\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:49: Define or directive not defined: \'`regdst_rd\'\nassign regaddr= (regdst==`regdst_rd)?rd:\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign regaddr= (regdst==`regdst_rd)?rd:\n                                   ^\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:50: Define or directive not defined: \'`regdst_rt\'\n       (regdst==`regdst_rt)?rt:\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:55: Define or directive not defined: \'`mtr_slti\'\nassign regdata=   (memtoreg==`mtr_slti)?($signed(rd1)<$signed(extout))?32\'b1:32\'b0:\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:55: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign regdata=   (memtoreg==`mtr_slti)?($signed(rd1)<$signed(extout))?32\'b1:32\'b0:\n                                      ^\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:56: Define or directive not defined: \'`mtr_shift\'\n      (memtoreg==`mtr_shift)?shiftout:\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:57: Define or directive not defined: \'`mtr_slt\'\n      (memtoreg==`mtr_slt)?(($signed(rd1)<$signed(rd2))?32\'b1:32\'b0):\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:58: Define or directive not defined: \'`mtr_alu\'\n      (memtoreg==`mtr_alu)?aluout:\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:59: Define or directive not defined: \'`mtr_dm\'\n      (memtoreg==`mtr_dm)?dmout:\n                 ^~~~~~~\n%Error: data/full_repos/permissive/166661632/p4/P4/DATAPATH.v:60: Define or directive not defined: \'`mtr_ext\'\n      (memtoreg==`mtr_ext)?extout:\n                 ^~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module DATAPATH(clk,clr,
branch,regwrite,memwrite,npcop,extop,aluop,alusrc,hf,bt,
regdst,memtoreg,
isbeq,isbgtz,isbgez,isbltz,isblez,
issll,issra,issrl,v,
instr);
input clk,clr,branch,regwrite,memwrite,isbeq,alusrc,hf,bt,isbgtz,isbgez,isbltz,isblez,issra,issrl,issll,v;
input [1:0] npcop,extop,aluop,regdst;
input [2:0] memtoreg;
output[31:0] instr;

wire [4:0]regaddr;
wire [31:0] regdata,alubdata;

wire [31:0]pc4;
wire [31:0] rd1,rd2,extout,zero32,npcout,gtz32,gez32,ltz32,lez32,shiftout;
wire [31:0] aluout;
wire [31:0] dmout;
wire branchlogic;

IM im(.clk(clk),.clr(clr),.branch(branchlogic),.npc(npcout),.instr(instr),.pc4(pc4));
assign branchlogic=(branch&isbeq&zero32[0])|(branch&isbgtz&gtz32[0])|(branch&isbgez&gez32[0])|(branch&isbltz&ltz32[0])
							|(branch&isblez&lez32[0])|(branch&~isbeq&~isbgtz&~isbgtz&~isbgez&~isbltz&~isblez);

wire [4:0] rs,rd,rt,shamt;
wire [5:0] op,funct;
wire [15:0] imm;
assign op=instr[31:26];
assign funct=instr[5:0];
assign shamt=instr[10:6];
assign rd=instr[15:11];
assign rt=instr[20:16];
assign rs=instr[25:21];
assign imm=instr[15:0];
GPR gpr(.clk(clk),.clr(clr),.we(regwrite),.a1(rs),.a2(rt),.a3(regaddr),.wd(regdata),.rd1(rd1),.rd2(rd2));
EXT ext(.imm(imm),.extop(extop),.extout(extout));
CMP cmp(.a(rd1),.b(rd2),.zero32(zero32),.gtz32(gtz32),.gez32(gez32),.ltz32(ltz32),.lez32(lez32));
NPC npc(.pc4(pc4),.extout(extout),.instr(instr),.rd1(rd1),.npcop(npcop),.npcout(npcout));
shift sft(rd2,rd1,shamt,issll,issrl,issra,v,shiftout);


ALU alu(.a(rd1),.b(alubdata),.aluop(aluop),.aluout(aluout));
assign alubdata=(alusrc==`alusrc_rd2)?rd2:extout;

DM dm(.clk(clk),.clr(clr),.we(memwrite),.addr(aluout),.wd(rd2),.dmout(dmout),.hf(hf),.bt(bt));

assign regaddr= (regdst==`regdst_rd)?rd:
					  (regdst==`regdst_rt)?rt:
					  5'd31;
					  
					  
					  
assign regdata=   (memtoreg==`mtr_slti)?($signed(rd1)<$signed(extout))?32'b1:32'b0:
						(memtoreg==`mtr_shift)?shiftout:
						(memtoreg==`mtr_slt)?(($signed(rd1)<$signed(rd2))?32'b1:32'b0):
						(memtoreg==`mtr_alu)?aluout:
						(memtoreg==`mtr_dm)?dmout:
						(memtoreg==`mtr_ext)?extout:
						pc4;






endmodule
module DATAPATH(clk,clr,
branch,regwrite,memwrite,npcop,extop,aluop,alusrc,hf,bt,
regdst,memtoreg,
isbeq,isbgtz,isbgez,isbltz,isblez,
issll,issra,issrl,v,
instr);

input clk,clr,branch,regwrite,memwrite,isbeq,alusrc,hf,bt,isbgtz,isbgez,isbltz,isblez,issra,issrl,issll,v;
input [1:0] npcop,extop,aluop,regdst;
input [2:0] memtoreg;
output[31:0] instr;

wire [4:0]regaddr;
wire [31:0] regdata,alubdata;

wire [31:0]pc4;
wire [31:0] rd1,rd2,extout,zero32,npcout,gtz32,gez32,ltz32,lez32,shiftout;
wire [31:0] aluout;
wire [31:0] dmout;
wire branchlogic;

IM im(.clk(clk),.clr(clr),.branch(branchlogic),.npc(npcout),.instr(instr),.pc4(pc4));
assign branchlogic=(branch&isbeq&zero32[0])|(branch&isbgtz&gtz32[0])|(branch&isbgez&gez32[0])|(branch&isbltz&ltz32[0])
							|(branch&isblez&lez32[0])|(branch&~isbeq&~isbgtz&~isbgtz&~isbgez&~isbltz&~isblez);

wire [4:0] rs,rd,rt,shamt;
wire [5:0] op,funct;
wire [15:0] imm;
assign op=instr[31:26];
assign funct=instr[5:0];
assign shamt=instr[10:6];
assign rd=instr[15:11];
assign rt=instr[20:16];
assign rs=instr[25:21];
assign imm=instr[15:0];
GPR gpr(.clk(clk),.clr(clr),.we(regwrite),.a1(rs),.a2(rt),.a3(regaddr),.wd(regdata),.rd1(rd1),.rd2(rd2));
EXT ext(.imm(imm),.extop(extop),.extout(extout));
CMP cmp(.a(rd1),.b(rd2),.zero32(zero32),.gtz32(gtz32),.gez32(gez32),.ltz32(ltz32),.lez32(lez32));
NPC npc(.pc4(pc4),.extout(extout),.instr(instr),.rd1(rd1),.npcop(npcop),.npcout(npcout));
shift sft(rd2,rd1,shamt,issll,issrl,issra,v,shiftout);


ALU alu(.a(rd1),.b(alubdata),.aluop(aluop),.aluout(aluout));
assign alubdata=(alusrc==`alusrc_rd2)?rd2:extout;

DM dm(.clk(clk),.clr(clr),.we(memwrite),.addr(aluout),.wd(rd2),.dmout(dmout),.hf(hf),.bt(bt));

assign regaddr= (regdst==`regdst_rd)?rd:
					  (regdst==`regdst_rt)?rt:
					  5'd31;
					  
					  
					  
assign regdata=   (memtoreg==`mtr_slti)?($signed(rd1)<$signed(extout))?32'b1:32'b0:
						(memtoreg==`mtr_shift)?shiftout:
						(memtoreg==`mtr_slt)?(($signed(rd1)<$signed(rd2))?32'b1:32'b0):
						(memtoreg==`mtr_alu)?aluout:
						(memtoreg==`mtr_dm)?dmout:
						(memtoreg==`mtr_ext)?extout:
						pc4;






endmodule