data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_CORE.v
 line:10: before: "("
1: b"%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_CORE.v:37: Cannot find file containing module: 'HD63701_SEQ'\nHD63701_SEQ #(MCWIDTH) SEQ(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174323821/hdl/cpu/63701,data/full_repos/permissive/174323821/HD63701_SEQ\n             data/full_repos/permissive/174323821/hdl/cpu/63701,data/full_repos/permissive/174323821/HD63701_SEQ.v\n             data/full_repos/permissive/174323821/hdl/cpu/63701,data/full_repos/permissive/174323821/HD63701_SEQ.sv\n             HD63701_SEQ\n             HD63701_SEQ.v\n             HD63701_SEQ.sv\n             obj_dir/HD63701_SEQ\n             obj_dir/HD63701_SEQ.v\n             obj_dir/HD63701_SEQ.sv\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_CORE.v:58: Cannot find file containing module: 'HD63701_EXEC'\nHD63701_EXEC #(MCWIDTH) EXEC(\n^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module HD63701_Core #(parameter MCWIDTH=24) (
    input           rst,
    input           clk,
    (*direct_enable *) input cen_rise,
    (*direct_enable *) input cen_fall,
    input           NMI,
    input           IRQ,
    input           IRQ2,
    input    [3:0]  IRQ2V,

    output          RW,
    output  [15:0]  AD,
    output  [ 7:0]  DO,
    input   [ 7:0]  DI,


    output    [5:0] PH,
    output [MCWIDTH-1:0] MC,
    output   [15:0] REG_D,
    output   [15:0] REG_X,
    output  [15:0]  REG_S,
    output   [5:0]  REG_C
);

wire [MCWIDTH-1:0] mcode;
wire [7:0]         vect;
wire               inte, fncu;

assign MC = mcode;

HD63701_SEQ #(MCWIDTH) SEQ(
    .clk        ( clk      ),
    .rst        ( rst      ),
    .cen_rise   ( cen_rise ),
    .cen_fall   ( cen_fall ),
                        
    .NMI(NMI),
    .IRQ(IRQ),
    .IRQ2(IRQ2),
    .IRQ2V(IRQ2V),
                        
    .DI(DI),
                        
    .mcout(mcode),
    .vect(vect),
    .inte(inte),
    .fncu(fncu),
                        
    .PH(PH) 
);

HD63701_EXEC #(MCWIDTH) EXEC(
    .clk        ( clk      ),
    .rst        ( rst      ),
    .cen_rise   ( cen_rise ),
    .cen_fall   ( cen_fall ),

    .DI(DI),
    .AD(AD),
    .RW(RW),
    .DO(DO),
                        
    .mcode(mcode),
    .vect(vect),
    .inte(inte),
    .fncu(fncu),
                        
    .REG_D(REG_D),
    .REG_X(REG_X),
    .REG_S(REG_S),
    .REG_C(REG_C)
);

endmodule
module HD63701_Core #(parameter MCWIDTH=24) (
    input           rst,
    input           clk,
    (*direct_enable *) input cen_rise,
    (*direct_enable *) input cen_fall,
    input           NMI,
    input           IRQ,
    input           IRQ2,
    input    [3:0]  IRQ2V,

    output          RW,
    output  [15:0]  AD,
    output  [ 7:0]  DO,
    input   [ 7:0]  DI,


    output    [5:0] PH,
    output [MCWIDTH-1:0] MC,
    output   [15:0] REG_D,
    output   [15:0] REG_X,
    output  [15:0]  REG_S,
    output   [5:0]  REG_C
);


wire [MCWIDTH-1:0] mcode;
wire [7:0]         vect;
wire               inte, fncu;

assign MC = mcode;

HD63701_SEQ #(MCWIDTH) SEQ(
    .clk        ( clk      ),
    .rst        ( rst      ),
    .cen_rise   ( cen_rise ),
    .cen_fall   ( cen_fall ),
                        
    .NMI(NMI),
    .IRQ(IRQ),
    .IRQ2(IRQ2),
    .IRQ2V(IRQ2V),
                        
    .DI(DI),
                        
    .mcout(mcode),
    .vect(vect),
    .inte(inte),
    .fncu(fncu),
                        
    .PH(PH) 
);

HD63701_EXEC #(MCWIDTH) EXEC(
    .clk        ( clk      ),
    .rst        ( rst      ),
    .cen_rise   ( cen_rise ),
    .cen_fall   ( cen_fall ),

    .DI(DI),
    .AD(AD),
    .RW(RW),
    .DO(DO),
                        
    .mcode(mcode),
    .vect(vect),
    .inte(inte),
    .fncu(fncu),
                        
    .REG_D(REG_D),
    .REG_X(REG_X),
    .REG_S(REG_S),
    .REG_C(REG_C)
);

endmodule