data/full_repos/permissive/136510272/projects/mkalc/processor.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:98: Operator ADD expects 9 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                  : ... In instance processor\nwire [8:0] r_adc = a + i_data + p[0];\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:99: Operator SUB expects 9 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                  : ... In instance processor\nwire [8:0] r_sbc = a - i_data - p[0] ^ 1\'b1;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:99: Operator XOR expects 9 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                  : ... In instance processor\nwire [8:0] r_sbc = a - i_data - p[0] ^ 1\'b1;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:110: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'t\' generates 4 bits.\n                                                                                   : ... In instance processor\nwire [7:0] opcode = t ? op_cache : i_data;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:113: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\nwire [7:0] zpx = i_data + (t == 4\'h6 ? y : (t == 4\'h7 ? x : 1\'b0));\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:128: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n            am <= 1\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:169: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n                8\'b100_110_00: begin a <= y; p <= {y[7], p[6:2], y == 1\'b0, p[0]}; end  \n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:193: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n            3\'h0: begin am <= 3\'h1; addr <= {8\'h00, i_data + (t == 4\'h1 ? x : 1\'b0)}; pc <= pc + 1\'b1; alt <= 1\'b1; end  \n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:195: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'y\' generates 8 bits.\n                                                                                   : ... In instance processor\n            3\'h2: begin t  <= 4\'hC; addr <= {i_data, tmp8} + (t == 4\'h8 ? y : 1\'b0); end  \n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:195: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n            3\'h2: begin t  <= 4\'hC; addr <= {i_data, tmp8} + (t == 4\'h8 ? y : 1\'b0); end  \n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:202: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'zpx\' generates 8 bits.\n                                                                                   : ... In instance processor\n        4\'h2, 4\'h6, 4\'h7: begin alt <= 1\'b1; addr <= zpx; t <= 4\'hC; pc <= pc + 1\'b1; end  \n                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:210: Operator COND expects 32 or 16 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 8 bits.\n                                                                                   : ... In instance processor\n            3\'h1: begin t  <= 4\'hC; addr <= {i_data, tmp8} + (t == 4\'h4 ? x : (t == 4\'h5 ? y : 0)); pc <= pc + 1\'b1; alt <= 1\'b1; end  \n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:210: Operator COND expects 32 or 16 bits on the Conditional True, but Conditional True\'s VARREF \'y\' generates 8 bits.\n                                                                                   : ... In instance processor\n            3\'h1: begin t  <= 4\'hC; addr <= {i_data, tmp8} + (t == 4\'h4 ? x : (t == 4\'h5 ? y : 0)); pc <= pc + 1\'b1; alt <= 1\'b1; end  \n                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:226: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n            t <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:231: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n        4\'hA: begin o_wr <= 1\'b0; alt <= 1\'b0; t <= 1\'b0; end\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:244: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n                    p   <= {r_ora[7], p[6:2], r_ora == 1\'b0, p[0]};\n                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:252: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n                    p   <= {r_and[7], p[6:2], r_and == 1\'b0, p[0]};\n                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:260: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n                    p   <= {r_eor[7], p[6:2], r_eor == 1\'b0, p[0]};\n                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:268: Operator EQ expects 9 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n                    p   <= {r_adc[7], r_adc_v, p[5:2], r_adc == 1\'b0, r_adc[8]};\n                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:276: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n                    p   <= {i_data[7], p[6:2], i_data == 1\'b0, p[0]};\n                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:283: Operator EQ expects 9 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n                    p   <= {i_data[7], r_sbc_v, p[5:2], r_sbc == 1\'b0, p[0] ^ 1\'b1};\n                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:284: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_sbc\' generates 9 bits.\n                                                                                   : ... In instance processor\n                    if (opcode[5]) a <= r_sbc;  \n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/mkalc/processor.v:308: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance processor\n                t   <= 1\'b0; \n                    ^~\n%Error: Exiting due to 23 warning(s)\n'
module processor(


    input   wire        clock_25,
    

    input   wire [7:0]  i_data,
    output  wire [15:0] o_addr,
    output  reg  [7:0]  o_data,
    output  reg         o_wr

);



assign o_addr = alt ? addr : pc;


 
reg [7:0]  a;
reg [7:0]  x;
reg [7:0]  y;
reg [7:0]  p;
reg [7:0]  s;
reg [15:0] pc;





reg [3:0]  t;
reg [2:0]  am;
reg [7:0]  op_cache;
reg        alt;
reg [15:0] addr;
reg [7:0]  tmp8;




initial begin

    a = 8'h17;
    x = 8'h00; 
    y = 8'h00;
    p = 8'h00; 
    s = 8'h00;
    
    t   = 4'h0;
    am  = 3'h0;
    alt = 1'b0;
    

    pc     = 16'h0000;
    addr   = 16'h0000;
    
    op_cache = 8'h00;
    o_data  = 8'h00;
    o_wr    = 1'b0;

end


 
wire [7:0] r_ora = a | i_data;
wire [7:0] r_and = a & i_data;
wire [7:0] r_eor = a ^ i_data;
wire [8:0] r_adc = a + i_data + p[0];
wire [8:0] r_sbc = a - i_data - p[0] ^ 1'b1;
wire       r_adc_v = (a[7] ^ i_data[7] ^ 1'b1) & (a[7] ^ r_adc[7]);
wire       r_sbc_v = (a[7] ^ i_data[7]       ) & (a[7] ^ r_adc[7]);

wire [15:0] pc_rel = pc + {{8{i_data[7]}}, i_data[6:0]} + 1'b1;




wire [7:0] opcode = t ? op_cache : i_data;


wire [7:0] zpx = i_data + (t == 4'h6 ? y : (t == 4'h7 ? x : 1'b0));



always @(posedge clock_25) begin

    case (t)
    

        4'h0: begin

            op_cache <= i_data;
            pc <= pc + 1'b1;
            am <= 1'b0;
        

            casex (opcode)
            

                8'bxxx_000_x1: t <= 4'h1;                
                

                8'b10x_101_1x: t <= 4'h6;


                8'bxxx_101_xx: t <= 4'h7;
                

                8'bxxx_001_xx, 
                8'b1xx_00x_00: t <= 4'h2;


                8'b001_000_00,
                8'bxxx_011_xx: t <= 4'h3;
                

                8'bxxx_100_x1: t <= 4'h8;


                8'bxxx_110_x1, 
                8'b10x_111_1x: t <= 4'h4;


                8'bxxx_111_xx: t <= 4'h5;
                

                8'bxxx_100_00: t <= 4'h9; 
                

                8'bxxx_010_x1: t <= 4'hC;
                

                8'b00x_110_00: p[0] <= opcode[5];
                8'b01x_110_00: p[2] <= opcode[5];
                8'b100_110_00: begin a <= y; p <= {y[7], p[6:2], y == 1'b0, p[0]}; end
                8'b101_110_00: p[6] <= 1'b0;
                8'b11x_110_00: p[3] <= opcode[5];
                

                default: begin 
                               

                    t <= 4'hC;

                end

            endcase
        
        end
        

        


        4'h1, 4'h8: case (am)

            3'h0: begin am <= 3'h1; addr <= {8'h00, i_data + (t == 4'h1 ? x : 1'b0)}; pc <= pc + 1'b1; alt <= 1'b1; end
            3'h1: begin am <= 3'h2; tmp8 <= i_data; addr[7:0] <= addr[7:0] + 1'b1; end
            3'h2: begin t  <= 4'hC; addr <= {i_data, tmp8} + (t == 4'h8 ? y : 1'b0); end

        endcase




        4'h2, 4'h6, 4'h7: begin alt <= 1'b1; addr <= zpx; t <= 4'hC; pc <= pc + 1'b1; end
        



        4'h3, 4'h4, 4'h5: case (am)

            3'h0: begin am <= 3'h1; tmp8 <= i_data; pc <= pc + 1'b1; end
            3'h1: begin t  <= 4'hC; addr <= {i_data, tmp8} + (t == 4'h4 ? x : (t == 4'h5 ? y : 0)); pc <= pc + 1'b1; alt <= 1'b1; end

        endcase  


        4'h9: begin
        
            casex (opcode[4:2])
            
                3'b00x: if (p[7] == opcode[0]) pc <= pc_rel; else pc <= pc + 1'b1;
                3'b01x: if (p[6] == opcode[0]) pc <= pc_rel; else pc <= pc + 1'b1;
                3'b10x: if (p[0] == opcode[0]) pc <= pc_rel; else pc <= pc + 1'b1;
                3'b11x: if (p[1] == opcode[0]) pc <= pc_rel; else pc <= pc + 1'b1;
            
            endcase
            
            t <= 1'b0;

        end
        

        4'hA: begin o_wr <= 1'b0; alt <= 1'b0; t <= 1'b0; end


        4'hC: begin 
        


            casex (opcode) 


                8'b000_xxx_01: begin 

                    a   <= r_ora; 
                    p   <= {r_ora[7], p[6:2], r_ora == 1'b0, p[0]};
                    
                end


                8'b001_xxx_01: begin 

                    a   <= r_and; 
                    p   <= {r_and[7], p[6:2], r_and == 1'b0, p[0]};

                end


                8'b010_xxx_01: begin 
                
                    a   <= r_eor; 
                    p   <= {r_eor[7], p[6:2], r_eor == 1'b0, p[0]};
                
                end


                8'b011_xxx_01: begin 
                
                    a   <= r_adc[7:0]; 
                    p   <= {r_adc[7], r_adc_v, p[5:2], r_adc == 1'b0, r_adc[8]};

                end


                8'b101_xxx_01: begin
                
                    a   <= i_data;
                    p   <= {i_data[7], p[6:2], i_data == 1'b0, p[0]};
                
                end
                

                8'b11x_xxx_01: begin
                    
                    p   <= {i_data[7], r_sbc_v, p[5:2], r_sbc == 1'b0, p[0] ^ 1'b1};
                    if (opcode[5]) a <= r_sbc;
                
                end


            
            endcase




            if ({opcode[7:5], opcode[1:0]} == 5'b10001) begin
            
                t      <= 4'hA;
                o_data <= a;
                o_wr   <= 1'b1;
                
                if (~alt) pc <= pc + 1'b1;

            end 

            else if (opcode[1:0] == 2'b01) begin 
                            
                alt <= 1'b0; 
                t   <= 1'b0; 

                if (~alt) pc <= pc + 1'b1;

            end
        
        end

    endcase

end

endmodule
module processor(


    input   wire        clock_25,
    

    input   wire [7:0]  i_data,
    output  wire [15:0] o_addr,
    output  reg  [7:0]  o_data,
    output  reg         o_wr

);




assign o_addr = alt ? addr : pc;


 
reg [7:0]  a;
reg [7:0]  x;
reg [7:0]  y;
reg [7:0]  p;
reg [7:0]  s;
reg [15:0] pc;





reg [3:0]  t;
reg [2:0]  am;
reg [7:0]  op_cache;
reg        alt;
reg [15:0] addr;
reg [7:0]  tmp8;




initial begin

    a = 8'h17;
    x = 8'h00; 
    y = 8'h00;
    p = 8'h00; 
    s = 8'h00;
    
    t   = 4'h0;
    am  = 3'h0;
    alt = 1'b0;
    

    pc     = 16'h0000;
    addr   = 16'h0000;
    
    op_cache = 8'h00;
    o_data  = 8'h00;
    o_wr    = 1'b0;

end


 
wire [7:0] r_ora = a | i_data;
wire [7:0] r_and = a & i_data;
wire [7:0] r_eor = a ^ i_data;
wire [8:0] r_adc = a + i_data + p[0];
wire [8:0] r_sbc = a - i_data - p[0] ^ 1'b1;
wire       r_adc_v = (a[7] ^ i_data[7] ^ 1'b1) & (a[7] ^ r_adc[7]);
wire       r_sbc_v = (a[7] ^ i_data[7]       ) & (a[7] ^ r_adc[7]);

wire [15:0] pc_rel = pc + {{8{i_data[7]}}, i_data[6:0]} + 1'b1;




wire [7:0] opcode = t ? op_cache : i_data;


wire [7:0] zpx = i_data + (t == 4'h6 ? y : (t == 4'h7 ? x : 1'b0));



always @(posedge clock_25) begin

    case (t)
    

        4'h0: begin

            op_cache <= i_data;
            pc <= pc + 1'b1;
            am <= 1'b0;
        

            casex (opcode)
            

                8'bxxx_000_x1: t <= 4'h1;                
                

                8'b10x_101_1x: t <= 4'h6;


                8'bxxx_101_xx: t <= 4'h7;
                

                8'bxxx_001_xx, 
                8'b1xx_00x_00: t <= 4'h2;


                8'b001_000_00,
                8'bxxx_011_xx: t <= 4'h3;
                

                8'bxxx_100_x1: t <= 4'h8;


                8'bxxx_110_x1, 
                8'b10x_111_1x: t <= 4'h4;


                8'bxxx_111_xx: t <= 4'h5;
                

                8'bxxx_100_00: t <= 4'h9; 
                

                8'bxxx_010_x1: t <= 4'hC;
                

                8'b00x_110_00: p[0] <= opcode[5];
                8'b01x_110_00: p[2] <= opcode[5];
                8'b100_110_00: begin a <= y; p <= {y[7], p[6:2], y == 1'b0, p[0]}; end
                8'b101_110_00: p[6] <= 1'b0;
                8'b11x_110_00: p[3] <= opcode[5];
                

                default: begin 
                               

                    t <= 4'hC;

                end

            endcase
        
        end
        

        


        4'h1, 4'h8: case (am)

            3'h0: begin am <= 3'h1; addr <= {8'h00, i_data + (t == 4'h1 ? x : 1'b0)}; pc <= pc + 1'b1; alt <= 1'b1; end
            3'h1: begin am <= 3'h2; tmp8 <= i_data; addr[7:0] <= addr[7:0] + 1'b1; end
            3'h2: begin t  <= 4'hC; addr <= {i_data, tmp8} + (t == 4'h8 ? y : 1'b0); end

        endcase




        4'h2, 4'h6, 4'h7: begin alt <= 1'b1; addr <= zpx; t <= 4'hC; pc <= pc + 1'b1; end
        



        4'h3, 4'h4, 4'h5: case (am)

            3'h0: begin am <= 3'h1; tmp8 <= i_data; pc <= pc + 1'b1; end
            3'h1: begin t  <= 4'hC; addr <= {i_data, tmp8} + (t == 4'h4 ? x : (t == 4'h5 ? y : 0)); pc <= pc + 1'b1; alt <= 1'b1; end

        endcase  


        4'h9: begin
        
            casex (opcode[4:2])
            
                3'b00x: if (p[7] == opcode[0]) pc <= pc_rel; else pc <= pc + 1'b1;
                3'b01x: if (p[6] == opcode[0]) pc <= pc_rel; else pc <= pc + 1'b1;
                3'b10x: if (p[0] == opcode[0]) pc <= pc_rel; else pc <= pc + 1'b1;
                3'b11x: if (p[1] == opcode[0]) pc <= pc_rel; else pc <= pc + 1'b1;
            
            endcase
            
            t <= 1'b0;

        end
        

        4'hA: begin o_wr <= 1'b0; alt <= 1'b0; t <= 1'b0; end


        4'hC: begin 
        


            casex (opcode) 


                8'b000_xxx_01: begin 

                    a   <= r_ora; 
                    p   <= {r_ora[7], p[6:2], r_ora == 1'b0, p[0]};
                    
                end


                8'b001_xxx_01: begin 

                    a   <= r_and; 
                    p   <= {r_and[7], p[6:2], r_and == 1'b0, p[0]};

                end


                8'b010_xxx_01: begin 
                
                    a   <= r_eor; 
                    p   <= {r_eor[7], p[6:2], r_eor == 1'b0, p[0]};
                
                end


                8'b011_xxx_01: begin 
                
                    a   <= r_adc[7:0]; 
                    p   <= {r_adc[7], r_adc_v, p[5:2], r_adc == 1'b0, r_adc[8]};

                end


                8'b101_xxx_01: begin
                
                    a   <= i_data;
                    p   <= {i_data[7], p[6:2], i_data == 1'b0, p[0]};
                
                end
                

                8'b11x_xxx_01: begin
                    
                    p   <= {i_data[7], r_sbc_v, p[5:2], r_sbc == 1'b0, p[0] ^ 1'b1};
                    if (opcode[5]) a <= r_sbc;
                
                end


            
            endcase




            if ({opcode[7:5], opcode[1:0]} == 5'b10001) begin
            
                t      <= 4'hA;
                o_data <= a;
                o_wr   <= 1'b1;
                
                if (~alt) pc <= pc + 1'b1;

            end 

            else if (opcode[1:0] == 2'b01) begin 
                            
                alt <= 1'b0; 
                t   <= 1'b0; 

                if (~alt) pc <= pc + 1'b1;

            end
        
        end

    endcase

end

endmodule