data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv
 line:40: before: "realtime"
1: b'%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:40: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  realtime  TP = 8.0ns,   \n                 ^~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:43: syntax error, unexpected int, expecting IDENTIFIER or \'=\' or do or final\n  int unsigned RSZ = 14   \n  ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:44: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:65: syntax error, unexpected assign\nassign adc_a = saw_a(adc_cyc);\n^~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:81: syntax error, unexpected always_ff\nalways_ff @ (posedge clk)\n^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:109: Unsupported: Dynamic array new\n  rdata_blk = new [len];\n              ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:116: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:252: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("red_pitaya_scope_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_scope_tb.sv:253: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, red_pitaya_scope_tb);\n  ^~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module red_pitaya_scope_tb #(

  realtime  TP = 8.0ns,

  int unsigned ADC_DW = 14,
  int unsigned RSZ = 14
);





function [ADC_DW-1:0] saw_a (input int unsigned cyc);
  saw_a = ADC_DW'(cyc*23);
endfunction: saw_a

function [ADC_DW-1:0] saw_b (input int unsigned cyc);
  cyc = cyc % (2**ADC_DW/5);
  saw_b = -2**(ADC_DW-1) + ADC_DW'(cyc*5);
endfunction: saw_b

logic              clk ;
logic              rstn;

logic [ADC_DW-1:0] adc_a;
logic [ADC_DW-1:0] adc_b;

assign adc_a = saw_a(adc_cyc);
assign adc_b = saw_b(adc_cyc);


initial        clk = 1'b0;
always #(TP/2) clk = ~clk;


initial begin
  rstn = 1'b0;
  repeat(4) @(posedge clk);
  rstn = 1'b1;
end


int unsigned adc_cyc=0;
always_ff @ (posedge clk)
adc_cyc <= adc_cyc+1;





logic            trig_ext ;

logic [ 32-1: 0] sys_addr ;
logic [ 32-1: 0] sys_wdata;
logic [  4-1: 0] sys_sel  ;
logic            sys_wen  ;
logic            sys_ren  ;
logic [ 32-1: 0] sys_rdata;
logic            sys_err  ;
logic            sys_ack  ;

logic        [ 32-1: 0] rdata;
logic signed [ 32-1: 0] rdata_blk [];
bit   signed [ 32-1: 0] rdata_ref [];
int unsigned            rdata_trg [$];
int unsigned            blk_size;

task read_blk (
  input int          adr,
  input int unsigned len
);
  rdata_blk = new [len];
  for (int unsigned i=0; i<len; i++) begin
    bus.read(adr+4*i, rdata_blk[i]);
  end 
endtask: read_blk


initial begin

  trig_ext = 1'b0;

  blk_size = 20;

  wait (rstn)
  repeat(10) @(posedge clk);


  bus.write(32'h14, 32'd1    );


  bus.write(32'h08,-32'd0000 );
  bus.write(32'h0C,-32'd7000 );
  bus.write(32'h20, 32'd20   );
  bus.write(32'h24, 32'd200  );


  bus.write(32'h50, 32'd0100);
  bus.write(32'h54, 32'd0200);
  bus.write(32'h70, 32'd0100);
  bus.write(32'h74, 32'd0200);

  bus.write(32'h10, blk_size );
























  fork

    begin: scope_trg

      repeat(20) @(posedge clk);       trig_ext = 1'b1;
      repeat( 1) @(posedge clk);       trig_ext = 1'b0;
    end

    begin: scope_run

      do begin
        bus.read(32'h94, rdata);
        repeat(20) @(posedge clk);
      end while (rdata & 2);
      repeat(20) @(posedge clk);

      read_blk (32'h30000, blk_size);

      $display ("trigger positions: %p", rdata_trg);
      $display ("data reference: %p", rdata_ref);
      $display ("data read     : %p", rdata_blk);
      if (rdata_ref == rdata_blk) $display ("SUCCESS");
      else                        $display ("FAILURE");
    end
  join

  repeat(100) @(posedge clk);
  $finish ();
end





sys_bus_model bus (

  .clk          (clk      ),
  .rstn         (rstn     ),

  .sys_addr     (sys_addr ),
  .sys_wdata    (sys_wdata),
  .sys_sel      (sys_sel  ),
  .sys_wen      (sys_wen  ),
  .sys_ren      (sys_ren  ),
  .sys_rdata    (sys_rdata),
  .sys_err      (sys_err  ),
  .sys_ack      (sys_ack  ) 
);

red_pitaya_scope #(
  .RSZ (RSZ)
) scope (

  .adc_clk_i      (clk      ),
  .adc_rstn_i     (rstn     ),
  .adc_a_i        (adc_a    ),
  .adc_b_i        (adc_b    ),

  .trig_ext_i     (trig_ext ),
  .trig_asg_i     (trig_ext ),

  .axi0_clk_o     (    ),  .axi1_clk_o     (    ),
  .axi0_rstn_o    (    ),  .axi1_rstn_o    (    ),
  .axi0_waddr_o   (    ),  .axi1_waddr_o   (    ),
  .axi0_wdata_o   (    ),  .axi1_wdata_o   (    ),
  .axi0_wsel_o    (    ),  .axi1_wsel_o    (    ),
  .axi0_wvalid_o  (    ),  .axi1_wvalid_o  (    ),
  .axi0_wlen_o    (    ),  .axi1_wlen_o    (    ),
  .axi0_wfixed_o  (    ),  .axi1_wfixed_o  (    ),
  .axi0_werr_i    (1'b0),  .axi1_werr_i    (1'b0),
  .axi0_wrdy_i    (1'b1),  .axi1_wrdy_i    (1'b1),

  .sys_addr       (sys_addr ),
  .sys_wdata      (sys_wdata),
  .sys_sel        (sys_sel  ),
  .sys_wen        (sys_wen  ),
  .sys_ren        (sys_ren  ),
  .sys_rdata      (sys_rdata),
  .sys_err        (sys_err  ),
  .sys_ack        (sys_ack  )
);





initial begin
  $dumpfile("red_pitaya_scope_tb.vcd");
  $dumpvars(0, red_pitaya_scope_tb);
end

endmodule
module red_pitaya_scope_tb #(

  realtime  TP = 8.0ns,

  int unsigned ADC_DW = 14,
  int unsigned RSZ = 14
);






function [ADC_DW-1:0] saw_a (input int unsigned cyc);
  saw_a = ADC_DW'(cyc*23);
endfunction: saw_a

function [ADC_DW-1:0] saw_b (input int unsigned cyc);
  cyc = cyc % (2**ADC_DW/5);
  saw_b = -2**(ADC_DW-1) + ADC_DW'(cyc*5);
endfunction: saw_b

logic              clk ;
logic              rstn;

logic [ADC_DW-1:0] adc_a;
logic [ADC_DW-1:0] adc_b;

assign adc_a = saw_a(adc_cyc);
assign adc_b = saw_b(adc_cyc);


initial        clk = 1'b0;
always #(TP/2) clk = ~clk;


initial begin
  rstn = 1'b0;
  repeat(4) @(posedge clk);
  rstn = 1'b1;
end


int unsigned adc_cyc=0;
always_ff @ (posedge clk)
adc_cyc <= adc_cyc+1;





logic            trig_ext ;

logic [ 32-1: 0] sys_addr ;
logic [ 32-1: 0] sys_wdata;
logic [  4-1: 0] sys_sel  ;
logic            sys_wen  ;
logic            sys_ren  ;
logic [ 32-1: 0] sys_rdata;
logic            sys_err  ;
logic            sys_ack  ;

logic        [ 32-1: 0] rdata;
logic signed [ 32-1: 0] rdata_blk [];
bit   signed [ 32-1: 0] rdata_ref [];
int unsigned            rdata_trg [$];
int unsigned            blk_size;

task read_blk (
  input int          adr,
  input int unsigned len
);
  rdata_blk = new [len];
  for (int unsigned i=0; i<len; i++) begin
    bus.read(adr+4*i, rdata_blk[i]);
  end 
endtask: read_blk


initial begin

  trig_ext = 1'b0;

  blk_size = 20;

  wait (rstn)
  repeat(10) @(posedge clk);


  bus.write(32'h14, 32'd1    );


  bus.write(32'h08,-32'd0000 );
  bus.write(32'h0C,-32'd7000 );
  bus.write(32'h20, 32'd20   );
  bus.write(32'h24, 32'd200  );


  bus.write(32'h50, 32'd0100);
  bus.write(32'h54, 32'd0200);
  bus.write(32'h70, 32'd0100);
  bus.write(32'h74, 32'd0200);

  bus.write(32'h10, blk_size );
























  fork

    begin: scope_trg

      repeat(20) @(posedge clk);       trig_ext = 1'b1;
      repeat( 1) @(posedge clk);       trig_ext = 1'b0;
    end

    begin: scope_run

      do begin
        bus.read(32'h94, rdata);
        repeat(20) @(posedge clk);
      end while (rdata & 2);
      repeat(20) @(posedge clk);

      read_blk (32'h30000, blk_size);

      $display ("trigger positions: %p", rdata_trg);
      $display ("data reference: %p", rdata_ref);
      $display ("data read     : %p", rdata_blk);
      if (rdata_ref == rdata_blk) $display ("SUCCESS");
      else                        $display ("FAILURE");
    end
  join

  repeat(100) @(posedge clk);
  $finish ();
end





sys_bus_model bus (

  .clk          (clk      ),
  .rstn         (rstn     ),

  .sys_addr     (sys_addr ),
  .sys_wdata    (sys_wdata),
  .sys_sel      (sys_sel  ),
  .sys_wen      (sys_wen  ),
  .sys_ren      (sys_ren  ),
  .sys_rdata    (sys_rdata),
  .sys_err      (sys_err  ),
  .sys_ack      (sys_ack  ) 
);

red_pitaya_scope #(
  .RSZ (RSZ)
) scope (

  .adc_clk_i      (clk      ),
  .adc_rstn_i     (rstn     ),
  .adc_a_i        (adc_a    ),
  .adc_b_i        (adc_b    ),

  .trig_ext_i     (trig_ext ),
  .trig_asg_i     (trig_ext ),

  .axi0_clk_o     (    ),  .axi1_clk_o     (    ),
  .axi0_rstn_o    (    ),  .axi1_rstn_o    (    ),
  .axi0_waddr_o   (    ),  .axi1_waddr_o   (    ),
  .axi0_wdata_o   (    ),  .axi1_wdata_o   (    ),
  .axi0_wsel_o    (    ),  .axi1_wsel_o    (    ),
  .axi0_wvalid_o  (    ),  .axi1_wvalid_o  (    ),
  .axi0_wlen_o    (    ),  .axi1_wlen_o    (    ),
  .axi0_wfixed_o  (    ),  .axi1_wfixed_o  (    ),
  .axi0_werr_i    (1'b0),  .axi1_werr_i    (1'b0),
  .axi0_wrdy_i    (1'b1),  .axi1_wrdy_i    (1'b1),

  .sys_addr       (sys_addr ),
  .sys_wdata      (sys_wdata),
  .sys_sel        (sys_sel  ),
  .sys_wen        (sys_wen  ),
  .sys_ren        (sys_ren  ),
  .sys_rdata      (sys_rdata),
  .sys_err        (sys_err  ),
  .sys_ack        (sys_ack  )
);





initial begin
  $dumpfile("red_pitaya_scope_tb.vcd");
  $dumpvars(0, red_pitaya_scope_tb);
end

endmodule