data/full_repos/permissive/13773754/hydra/hdl/address_generator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/13773754/hydra/hdl/address_generator.v:43: Operator ADD expects 24 bits on the LHS, but LHS\'s VARREF \'strand_offset\' generates 16 bits.\n                                                                                    : ... In instance address_generator\n                addr = strand_offset + (strand_idx - strand_length);\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/13773754/hydra/hdl/address_generator.v:43: Operator SUB expects 24 bits on the LHS, but LHS\'s VARREF \'strand_idx\' generates 16 bits.\n                                                                                    : ... In instance address_generator\n                addr = strand_offset + (strand_idx - strand_length);\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/13773754/hydra/hdl/address_generator.v:43: Operator SUB expects 24 bits on the RHS, but RHS\'s VARREF \'strand_length\' generates 16 bits.\n                                                                                    : ... In instance address_generator\n                addr = strand_offset + (strand_idx - strand_length);\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/13773754/hydra/hdl/address_generator.v:46: Operator ADD expects 24 bits on the LHS, but LHS\'s VARREF \'strand_offset\' generates 16 bits.\n                                                                                    : ... In instance address_generator\n                addr = strand_offset + strand_idx;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/13773754/hydra/hdl/address_generator.v:46: Operator ADD expects 24 bits on the RHS, but RHS\'s VARREF \'strand_idx\' generates 16 bits.\n                                                                                    : ... In instance address_generator\n                addr = strand_offset + strand_idx;\n                                     ^\n%Error: Exiting due to 5 warning(s)\n'
module address_generator (
    clk,
    rst_n,
    strand_offset,
    strand_idx,
    strand_length,
    addr
    );

    parameter MEM_ADDR_WIDTH = 24;
    parameter STRAND_PARAM_WIDTH = 16;

    input clk;
    input rst_n;


    input [STRAND_PARAM_WIDTH-1:0] strand_offset;
    input [STRAND_PARAM_WIDTH-1:0] strand_idx;
    input [STRAND_PARAM_WIDTH-1:0] strand_length;

    output reg [MEM_ADDR_WIDTH-1:0] addr;


    always @(posedge clk) begin
        if (rst_n == 1'b0) begin
            addr = { MEM_ADDR_WIDTH {1'b0} };
        end
        else begin


            if (strand_idx > strand_length - 1) begin
                addr = strand_offset + (strand_idx - strand_length);
            end
            else begin
                addr = strand_offset + strand_idx;
            end
        end
    end

 endmodule
module address_generator (
    clk,
    rst_n,
    strand_offset,
    strand_idx,
    strand_length,
    addr
    );


    parameter MEM_ADDR_WIDTH = 24;
    parameter STRAND_PARAM_WIDTH = 16;

    input clk;
    input rst_n;


    input [STRAND_PARAM_WIDTH-1:0] strand_offset;
    input [STRAND_PARAM_WIDTH-1:0] strand_idx;
    input [STRAND_PARAM_WIDTH-1:0] strand_length;

    output reg [MEM_ADDR_WIDTH-1:0] addr;


    always @(posedge clk) begin
        if (rst_n == 1'b0) begin
            addr = { MEM_ADDR_WIDTH {1'b0} };
        end
        else begin


            if (strand_idx > strand_length - 1) begin
                addr = strand_offset + (strand_idx - strand_length);
            end
            else begin
                addr = strand_offset + strand_idx;
            end
        end
    end

 endmodule