data/full_repos/permissive/129155059/04-struct_register/library.v
 line:27: before: ":"
1: b'%Error: data/full_repos/permissive/129155059/04-struct_register/library.v:5: Cannot find include file: definitions.v\n`include "definitions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/04-struct_register,data/full_repos/permissive/129155059/definitions.v\n             data/full_repos/permissive/129155059/04-struct_register,data/full_repos/permissive/129155059/definitions.v.v\n             data/full_repos/permissive/129155059/04-struct_register,data/full_repos/permissive/129155059/definitions.v.sv\n             definitions.v\n             definitions.v.v\n             definitions.v.sv\n             obj_dir/definitions.v\n             obj_dir/definitions.v.v\n             obj_dir/definitions.v.sv\n%Error: data/full_repos/permissive/129155059/04-struct_register/library.v:158: Define or directive not defined: \'`Ndir\'\n   input [`Ndir:0] dir;\n          ^~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/library.v:158: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   input [`Ndir:0] dir;\n               ^\n%Error: data/full_repos/permissive/129155059/04-struct_register/library.v:161: Define or directive not defined: \'`NumPwrCntr\'\n   reg [31:0]      PwrCntr [`NumPwrCntr:0];\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/library.v:161: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   reg [31:0]      PwrCntr [`NumPwrCntr:0];\n                                       ^\n%Error: Exiting due to 5 error(s)\n'
module ff_d ( output reg Q,
              output reg Qn,
              input wire D,
              input wire CLK,
              input wire ENB
              );

   parameter PwrC = 0;

   real time_a;
   real time_b;
   integer exep = 0;

   always @(posedge CLK) begin
      if (ENB == 0) begin
         Q <= #15 Q;
         Qn <= #15 Qn;
      end else begin
         Q <= #15 D;
         Qn <= #15 ~D;
      end
   end

   always @(posedge Q or negedge Q) begin

      letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;

   end

   always @ (posedge D or negedge D) begin
       time_a = $realtime;



 		   if (time_a != 0 && time_b != 0 ) begin
 			     if ((0 <= (time_b-time_a))&&((time_b-time_a) < 20)&&(exep == 0)) begin
 				       $display("D. Violación en tsetup en %d, con flanco %d. Captura de excepción.", time_a, time_b);
 				       exep <= 1;
 			     end else if ((-15.0 < (time_b-time_a))&& ((time_b-time_a) < 0) && (exep == 0)) begin
 				       $display("D. Violación en thold en %d, con flanco %d. Captura de excepción.", time_a, time_b);
 				       exep <= 1;
 			     end
 		   end
 	 end

 	 always @ (posedge CLK) begin
 		   time_b = $realtime;



 		   if (time_a != 0 && time_b !=0 ) begin
 			     if ((0 <= (time_b - time_a)) && ((time_b - time_a) < 20) && (exep == 0)) begin
 				       $display("CLK. Violación en tsetup en %d, con flanco %d. Captura de excepción.", time_a, time_b);
 				       exep <= 1;
 			     end else if ((-15.0 < (time_b - time_a)) && ((time_b - time_a) < 0) && (exep == 0)) begin
 				       $display("CLK. Violación en tsetup en %d, con flanco %d. Captura de excepción.", time_a, time_b);
 				       exep <= 1;
 			     end
 	     end
   end

endmodule
module ff_d ( output reg Q,
              output reg Qn,
              input wire D,
              input wire CLK,
              input wire ENB
              );


   parameter PwrC = 0;

   real time_a;
   real time_b;
   integer exep = 0;

   always @(posedge CLK) begin
      if (ENB == 0) begin
         Q <= #15 Q;
         Qn <= #15 Qn;
      end else begin
         Q <= #15 D;
         Qn <= #15 ~D;
      end
   end

   always @(posedge Q or negedge Q) begin

      letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;

   end

   always @ (posedge D or negedge D) begin
       time_a = $realtime;



 		   if (time_a != 0 && time_b != 0 ) begin
 			     if ((0 <= (time_b-time_a))&&((time_b-time_a) < 20)&&(exep == 0)) begin
 				       $display("D. Violación en tsetup en %d, con flanco %d. Captura de excepción.", time_a, time_b);
 				       exep <= 1;
 			     end else if ((-15.0 < (time_b-time_a))&& ((time_b-time_a) < 0) && (exep == 0)) begin
 				       $display("D. Violación en thold en %d, con flanco %d. Captura de excepción.", time_a, time_b);
 				       exep <= 1;
 			     end
 		   end
 	 end

 	 always @ (posedge CLK) begin
 		   time_b = $realtime;



 		   if (time_a != 0 && time_b !=0 ) begin
 			     if ((0 <= (time_b - time_a)) && ((time_b - time_a) < 20) && (exep == 0)) begin
 				       $display("CLK. Violación en tsetup en %d, con flanco %d. Captura de excepción.", time_a, time_b);
 				       exep <= 1;
 			     end else if ((-15.0 < (time_b - time_a)) && ((time_b - time_a) < 0) && (exep == 0)) begin
 				       $display("CLK. Violación en tsetup en %d, con flanco %d. Captura de excepción.", time_a, time_b);
 				       exep <= 1;
 			     end
 	     end
   end

endmodule