data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf/mux_n21.v
data/verilator_xmls/f0244aba-a5cd-4b0a-bf91-0addfff75b86.xml
module mux_n21 #(parameter nCTRL = 8)(ins,ctrls,out);

	localparam nIN = 2**nCTRL;
	
	input [nIN-1:0] ins;
	input [nCTRL-1:0] ctrls;
	output out;

	assign out = ins[ctrls];

endmodule
module mux_n21 #(parameter nCTRL = 8)(ins,ctrls,out);


	localparam nIN = 2**nCTRL;
	
	input [nIN-1:0] ins;
	input [nCTRL-1:0] ctrls;
	output out;

	assign out = ins[ctrls];

endmodule