data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv
 line:77: before: "unsigned"
1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:23: Cannot find file containing module: 'sync_edetect'\nsync_edetect sd(CLK, RX, rx_s, any_edge, neg_edge);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect.v\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect.sv\n             sync_edetect\n             sync_edetect.v\n             sync_edetect.sv\n             obj_dir/sync_edetect\n             obj_dir/sync_edetect.v\n             obj_dir/sync_edetect.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:33: Cannot find file containing module: 'counter'\ncounter #(16) bit_time_cnt(CLK, cnt_reset, count_en, bit_cnt_q );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:36: Cannot find file containing module: 'counter'\ncounter #(3) byte_cnt(CLK, resync, shift_bit, byte_cnt_q );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:38: Cannot find file containing module: 'shift_in_reg_right'\nshift_in_reg_right #(8) sr( CLK, resync, shift_bit, rx_s, DATA );\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:41: Cannot find file containing module: 'ffd'\nffd #(1) parity_fd(CLK, RESET, resync | shift_bit_p, par_fd_in, par_fd_q);\n^~~\n%Error: Exiting due to 5 error(s)\n"
module uart_rx_fsm( input  CLK,
                    input  RESET,
                    input  NEG_EDGE,
                    input  ANY_EDGE,
                    input  HALF_PERIOD,
                    input  FULL_PERIOD,
                    input  BYTE_DONE,
                    input  PARITY_EN,
                    output COUNT_EN,
                    output START_BIT,
                    output DATA_BIT,
                    output DP_BIT,
                    output DONE,
                    output READY );

enum int unsigned { ST_READY      = 0, 
                    ST_START_BIT  = 1, 
                    ST_DATA_BIT   = 2,
                    ST_PARITY_BIT = 3, 
                    ST_DONE       = 4 } state, next;

always_ff@(posedge CLK)
  if(RESET) state <= ST_READY;
  else      state <= next;

always_comb begin
  next = ST_READY;
  case(state)
  ST_READY:      if(NEG_EDGE)          next = ST_START_BIT;
                 else                  next = state;
                
  ST_START_BIT:  if(ANY_EDGE)          next = ST_READY;
                 else if(HALF_PERIOD)  next = ST_DATA_BIT;
                 else                  next = state;
                
  ST_DATA_BIT:   if(FULL_PERIOD & 
                    BYTE_DONE)
                    begin
                     if(PARITY_EN)     next = ST_PARITY_BIT;
                     else              next = ST_DONE;
                    end       
                 else                  next = state;

  ST_PARITY_BIT: if(FULL_PERIOD)       next = ST_DONE;
                 else                  next = state;
                
  ST_DONE:                             next = ST_READY;
  
  default:                             next = ST_READY;
  endcase
end

assign START_BIT = (state == ST_START_BIT);

assign DATA_BIT  = (state == ST_DATA_BIT);

assign DP_BIT    = DATA_BIT | (state == ST_PARITY_BIT);

assign COUNT_EN  = DP_BIT   | (state == ST_START_BIT);

assign DONE      = (state == ST_DONE);

assign READY     = (state == ST_READY);

endmodule
module uart_rx_fsm( input  CLK,
                    input  RESET,
                    input  NEG_EDGE,
                    input  ANY_EDGE,
                    input  HALF_PERIOD,
                    input  FULL_PERIOD,
                    input  BYTE_DONE,
                    input  PARITY_EN,
                    output COUNT_EN,
                    output START_BIT,
                    output DATA_BIT,
                    output DP_BIT,
                    output DONE,
                    output READY );


enum int unsigned { ST_READY      = 0, 
                    ST_START_BIT  = 1, 
                    ST_DATA_BIT   = 2,
                    ST_PARITY_BIT = 3, 
                    ST_DONE       = 4 } state, next;

always_ff@(posedge CLK)
  if(RESET) state <= ST_READY;
  else      state <= next;

always_comb begin
  next = ST_READY;
  case(state)
  ST_READY:      if(NEG_EDGE)          next = ST_START_BIT;
                 else                  next = state;
                
  ST_START_BIT:  if(ANY_EDGE)          next = ST_READY;
                 else if(HALF_PERIOD)  next = ST_DATA_BIT;
                 else                  next = state;
                
  ST_DATA_BIT:   if(FULL_PERIOD & 
                    BYTE_DONE)
                    begin
                     if(PARITY_EN)     next = ST_PARITY_BIT;
                     else              next = ST_DONE;
                    end       
                 else                  next = state;

  ST_PARITY_BIT: if(FULL_PERIOD)       next = ST_DONE;
                 else                  next = state;
                
  ST_DONE:                             next = ST_READY;
  
  default:                             next = ST_READY;
  endcase
end

assign START_BIT = (state == ST_START_BIT);

assign DATA_BIT  = (state == ST_DATA_BIT);

assign DP_BIT    = DATA_BIT | (state == ST_PARITY_BIT);

assign COUNT_EN  = DP_BIT   | (state == ST_START_BIT);

assign DONE      = (state == ST_DONE);

assign READY     = (state == ST_READY);

endmodule