data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:66: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/timescale.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/timescale.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:68: Cannot find include file: pci_constants.v\n`include "pci_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:136: Define or directive not defined: \'`FF_DELAY\'\n  pci_gnt_reg_out  <= #`FF_DELAY 1\'b1 ;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:137: Define or directive not defined: \'`FF_DELAY\'\n  pci_frame_reg_out <= #`FF_DELAY 1\'b0 ;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:138: Define or directive not defined: \'`FF_DELAY\'\n  pci_irdy_reg_out <= #`FF_DELAY 1\'b1 ;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:139: Define or directive not defined: \'`FF_DELAY\'\n  pci_trdy_reg_out <= #`FF_DELAY 1\'b1 ;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:140: Define or directive not defined: \'`FF_DELAY\'\n  pci_stop_reg_out <= #`FF_DELAY 1\'b1 ;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:141: Define or directive not defined: \'`FF_DELAY\'\n  pci_devsel_reg_out <= #`FF_DELAY 1\'b1 ;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:142: Define or directive not defined: \'`FF_DELAY\'\n  pci_idsel_reg_out <= #`FF_DELAY 1\'b0 ;  \n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:143: Define or directive not defined: \'`FF_DELAY\'\n  pci_ad_reg_out      <= #`FF_DELAY 32\'h0000_0000 ;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:144: Define or directive not defined: \'`FF_DELAY\'\n  pci_cbe_reg_out     <= #`FF_DELAY 4\'h0 ;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:148: Define or directive not defined: \'`FF_DELAY\'\n  pci_gnt_reg_out  <= #`FF_DELAY pci_gnt_in ;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:148: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pci_gnt_reg_out  <= #`FF_DELAY pci_gnt_in ;\n                                            ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:149: Define or directive not defined: \'`FF_DELAY\'\n  pci_frame_reg_out <= #`FF_DELAY pci_frame_in ;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:149: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pci_frame_reg_out <= #`FF_DELAY pci_frame_in ;\n                                               ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:150: Define or directive not defined: \'`FF_DELAY\'\n  pci_irdy_reg_out <= #`FF_DELAY pci_irdy_in ;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:150: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pci_irdy_reg_out <= #`FF_DELAY pci_irdy_in ;\n                                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:151: Define or directive not defined: \'`FF_DELAY\'\n  pci_trdy_reg_out <= #`FF_DELAY pci_trdy_in ;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:151: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pci_trdy_reg_out <= #`FF_DELAY pci_trdy_in ;\n                                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:152: Define or directive not defined: \'`FF_DELAY\'\n  pci_stop_reg_out <= #`FF_DELAY pci_stop_in ;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:152: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pci_stop_reg_out <= #`FF_DELAY pci_stop_in ;\n                                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:153: Define or directive not defined: \'`FF_DELAY\'\n  pci_devsel_reg_out <= #`FF_DELAY pci_devsel_in ;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:153: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pci_devsel_reg_out <= #`FF_DELAY pci_devsel_in ;\n                                                 ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:154: Define or directive not defined: \'`FF_DELAY\'\n  pci_idsel_reg_out <= #`FF_DELAY pci_idsel_in ;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:154: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pci_idsel_reg_out <= #`FF_DELAY pci_idsel_in ;\n                                               ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:155: Define or directive not defined: \'`FF_DELAY\'\n  pci_ad_reg_out      <= #`FF_DELAY pci_ad_in ;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:155: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pci_ad_reg_out      <= #`FF_DELAY pci_ad_in ;\n                                              ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:156: Define or directive not defined: \'`FF_DELAY\'\n  pci_cbe_reg_out     <= #`FF_DELAY pci_cbe_in ;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v:156: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pci_cbe_reg_out     <= #`FF_DELAY pci_cbe_in ;\n                                               ^\n%Error: Exiting due to 29 error(s)\n'
module pci_in_reg
(    
    reset_in,
    clk_in,
    init_complete_in,

    pci_gnt_in,
    pci_frame_in,
    pci_irdy_in,
    pci_trdy_in,
    pci_stop_in,
    pci_devsel_in,
    pci_idsel_in,
    pci_ad_in,
    pci_cbe_in,

    pci_gnt_reg_out,
    pci_frame_reg_out,
    pci_irdy_reg_out,
    pci_trdy_reg_out,
    pci_stop_reg_out,
    pci_devsel_reg_out,
    pci_idsel_reg_out,
    pci_ad_reg_out,
    pci_cbe_reg_out

);

input			reset_in, clk_in, init_complete_in  ;

input           pci_gnt_in ;
input           pci_frame_in ;
input           pci_irdy_in ;
input           pci_trdy_in ;
input           pci_stop_in ;
input           pci_devsel_in ;
input			pci_idsel_in ;
input [31:0]    pci_ad_in ;
input [3:0]     pci_cbe_in ;

output          pci_gnt_reg_out ;
output          pci_frame_reg_out ;
output          pci_irdy_reg_out ;
output          pci_trdy_reg_out ;
output          pci_stop_reg_out ;
output          pci_devsel_reg_out ;
output			pci_idsel_reg_out ;
output [31:0]   pci_ad_reg_out ;
output [3:0]    pci_cbe_reg_out ;


reg             pci_gnt_reg_out ;
reg             pci_frame_reg_out ;
reg             pci_irdy_reg_out ;
reg             pci_trdy_reg_out ;
reg             pci_stop_reg_out ;
reg             pci_devsel_reg_out ;
reg				pci_idsel_reg_out ;
reg    [31:0]   pci_ad_reg_out ;
reg    [3:0]    pci_cbe_reg_out ;

always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
    begin
		pci_gnt_reg_out		<= #`FF_DELAY 1'b1 ;
		pci_frame_reg_out	<= #`FF_DELAY 1'b0 ;
		pci_irdy_reg_out	<= #`FF_DELAY 1'b1 ;
		pci_trdy_reg_out	<= #`FF_DELAY 1'b1 ;
		pci_stop_reg_out	<= #`FF_DELAY 1'b1 ;
		pci_devsel_reg_out	<= #`FF_DELAY 1'b1 ;
		pci_idsel_reg_out	<= #`FF_DELAY 1'b0 ;
		pci_ad_reg_out      <= #`FF_DELAY 32'h0000_0000 ;
		pci_cbe_reg_out     <= #`FF_DELAY 4'h0 ;
    end
    else if (init_complete_in)
	begin
		pci_gnt_reg_out		<= #`FF_DELAY pci_gnt_in ;
		pci_frame_reg_out	<= #`FF_DELAY pci_frame_in ;
		pci_irdy_reg_out	<= #`FF_DELAY pci_irdy_in ;
		pci_trdy_reg_out	<= #`FF_DELAY pci_trdy_in ;
		pci_stop_reg_out	<= #`FF_DELAY pci_stop_in ;
		pci_devsel_reg_out	<= #`FF_DELAY pci_devsel_in ;
		pci_idsel_reg_out	<= #`FF_DELAY pci_idsel_in ;
		pci_ad_reg_out      <= #`FF_DELAY pci_ad_in ;
		pci_cbe_reg_out     <= #`FF_DELAY pci_cbe_in ;
	end
end

endmodule
module pci_in_reg
(    
    reset_in,
    clk_in,
    init_complete_in,

    pci_gnt_in,
    pci_frame_in,
    pci_irdy_in,
    pci_trdy_in,
    pci_stop_in,
    pci_devsel_in,
    pci_idsel_in,
    pci_ad_in,
    pci_cbe_in,

    pci_gnt_reg_out,
    pci_frame_reg_out,
    pci_irdy_reg_out,
    pci_trdy_reg_out,
    pci_stop_reg_out,
    pci_devsel_reg_out,
    pci_idsel_reg_out,
    pci_ad_reg_out,
    pci_cbe_reg_out

);


input			reset_in, clk_in, init_complete_in  ;

input           pci_gnt_in ;
input           pci_frame_in ;
input           pci_irdy_in ;
input           pci_trdy_in ;
input           pci_stop_in ;
input           pci_devsel_in ;
input			pci_idsel_in ;
input [31:0]    pci_ad_in ;
input [3:0]     pci_cbe_in ;

output          pci_gnt_reg_out ;
output          pci_frame_reg_out ;
output          pci_irdy_reg_out ;
output          pci_trdy_reg_out ;
output          pci_stop_reg_out ;
output          pci_devsel_reg_out ;
output			pci_idsel_reg_out ;
output [31:0]   pci_ad_reg_out ;
output [3:0]    pci_cbe_reg_out ;


reg             pci_gnt_reg_out ;
reg             pci_frame_reg_out ;
reg             pci_irdy_reg_out ;
reg             pci_trdy_reg_out ;
reg             pci_stop_reg_out ;
reg             pci_devsel_reg_out ;
reg				pci_idsel_reg_out ;
reg    [31:0]   pci_ad_reg_out ;
reg    [3:0]    pci_cbe_reg_out ;

always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
    begin
		pci_gnt_reg_out		<= #`FF_DELAY 1'b1 ;
		pci_frame_reg_out	<= #`FF_DELAY 1'b0 ;
		pci_irdy_reg_out	<= #`FF_DELAY 1'b1 ;
		pci_trdy_reg_out	<= #`FF_DELAY 1'b1 ;
		pci_stop_reg_out	<= #`FF_DELAY 1'b1 ;
		pci_devsel_reg_out	<= #`FF_DELAY 1'b1 ;
		pci_idsel_reg_out	<= #`FF_DELAY 1'b0 ;
		pci_ad_reg_out      <= #`FF_DELAY 32'h0000_0000 ;
		pci_cbe_reg_out     <= #`FF_DELAY 4'h0 ;
    end
    else if (init_complete_in)
	begin
		pci_gnt_reg_out		<= #`FF_DELAY pci_gnt_in ;
		pci_frame_reg_out	<= #`FF_DELAY pci_frame_in ;
		pci_irdy_reg_out	<= #`FF_DELAY pci_irdy_in ;
		pci_trdy_reg_out	<= #`FF_DELAY pci_trdy_in ;
		pci_stop_reg_out	<= #`FF_DELAY pci_stop_in ;
		pci_devsel_reg_out	<= #`FF_DELAY pci_devsel_in ;
		pci_idsel_reg_out	<= #`FF_DELAY pci_idsel_in ;
		pci_ad_reg_out      <= #`FF_DELAY pci_ad_in ;
		pci_cbe_reg_out     <= #`FF_DELAY pci_cbe_in ;
	end
end

endmodule