data/full_repos/permissive/115035459/verilog/src/example001.v
data/verilator_xmls/1d8d28bd-e343-4527-ac65-629594b02332.xml
module top (
	input J1_3, J1_4,
	output LED5
);
	assign LED5 = J1_3 & J1_4;
endmodule
module top (
	input J1_3, J1_4,
	output LED5
);

	assign LED5 = J1_3 & J1_4;
endmodule