data/full_repos/permissive/219228794/src/FPGA_GreenBeret.v
1: b"%Error: data/full_repos/permissive/219228794/src/FPGA_GreenBeret.v:47: Cannot find file containing module: 'MAIN'\nMAIN cpu\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/MAIN\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/MAIN.v\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/MAIN.sv\n             MAIN\n             MAIN.v\n             MAIN.sv\n             obj_dir/MAIN\n             obj_dir/MAIN.v\n             obj_dir/MAIN.sv\n%Error: data/full_repos/permissive/219228794/src/FPGA_GreenBeret.v:62: Cannot find file containing module: 'VIDEO'\nVIDEO vid\n^~~~~\n%Error: data/full_repos/permissive/219228794/src/FPGA_GreenBeret.v:78: Cannot find file containing module: 'SOUND'\nSOUND snd\n^~~~~\n%Error: Exiting due to 3 error(s)\n"
module CLKGEN
(
	input		clk48M,

	output	clk24M,
	output	clk12M,
	output	clk6M,
	output	clk3M
);
	
reg [3:0] clkdiv;
always @( posedge clk48M ) clkdiv <= clkdiv+4'd1;

assign clk24M = clkdiv[0];
assign clk12M = clkdiv[1];
assign clk6M  = clkdiv[2];
assign clk3M  = clkdiv[3];

endmodule
module CLKGEN
(
	input		clk48M,

	output	clk24M,
	output	clk12M,
	output	clk6M,
	output	clk3M
);

	
reg [3:0] clkdiv;
always @( posedge clk48M ) clkdiv <= clkdiv+4'd1;

assign clk24M = clkdiv[0];
assign clk12M = clkdiv[1];
assign clk6M  = clkdiv[2];
assign clk3M  = clkdiv[3];

endmodule