data/full_repos/permissive/143278/ivltests/casesynth4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth4.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a!==0 || b!==1) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth4.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a!==1 || b!==0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth4.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a!==0 || b!==0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth4.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a!==1 || b!==1) begin\n      ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
   reg [1:0] sel;
   reg	     d;
   wire      a, b;

   test dut (.a(a), .b(b), .sel(sel), .d(d));

   initial begin
      d = 0;
      sel = 0;
      #1 if (a!==0 || b!==1) begin
	 $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
	 $finish;
      end
      sel = 1;
      #1 if (a!==1 || b!==0) begin
	 $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
	 $finish;
      end
      sel = 2;
      #1 if (a!==0 || b!==0) begin
	 $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
	 $finish;
      end
      d = 1;
      #1 if (a!==1 || b!==1) begin
	 $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;

   reg [1:0] sel;
   reg	     d;
   wire      a, b;

   test dut (.a(a), .b(b), .sel(sel), .d(d));

   initial begin
      d = 0;
      sel = 0;
      #1 if (a!==0 || b!==1) begin
	 $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
	 $finish;
      end
      sel = 1;
      #1 if (a!==1 || b!==0) begin
	 $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
	 $finish;
      end
      sel = 2;
      #1 if (a!==0 || b!==0) begin
	 $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
	 $finish;
      end
      d = 1;
      #1 if (a!==1 || b!==1) begin
	 $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
	 $finish;
      end

      $display("PASSED");
   end
endmodule