data/full_repos/permissive/217697217/problems/03_led_blink/clk_div.v
data/verilator_xmls/22587df3-e3bf-452b-8d54-9385b563e925.xml
module clk_div #(parameter x = 10)(
  input clk,

  output clk_out
);


reg [x-1:0]cnt = 0;
assign clk_out = cnt[x-1];

always @ (posedge clk) begin
  cnt <= cnt + 1;
end
endmodule
module clk_div #(parameter x = 10)(
  input clk,

  output clk_out
);



reg [x-1:0]cnt = 0;
assign clk_out = cnt[x-1];

always @ (posedge clk) begin
  cnt <= cnt + 1;
end
endmodule