data/full_repos/permissive/169574047/module/module.srcs/sim_1/new/testbench.v
 line:38: before: "$"
1: b'%Error: data/full_repos/permissive/169574047/module/module.srcs/sim_1/new/testbench.v:32: Unsupported or unknown PLI call: $monitor\n    $monitor($time, " set = %b, reset = %b, q = %b\\n", set, reset, q);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169574047/module/module.srcs/sim_1/new/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #5 reset=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/module/module.srcs/sim_1/new/testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #5 reset=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/module/module.srcs/sim_1/new/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #5 set=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/module/module.srcs/sim_1/new/testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

wire q,qbar;
reg set,reset;

SR_latch m1(q, qbar, ~set, ~reset);

initial
begin
    $monitor($time, " set = %b, reset = %b, q = %b\n", set, reset, q);
    set=0;
    reset=0;
    #5 reset=1;
    #5 reset=0;
    #5 set=1;
    #5 $finish;
end

endmodule
module testbench;


wire q,qbar;
reg set,reset;

SR_latch m1(q, qbar, ~set, ~reset);

initial
begin
    $monitor($time, " set = %b, reset = %b, q = %b\n", set, reset, q);
    set=0;
    reset=0;
    #5 reset=1;
    #5 reset=0;
    #5 set=1;
    #5 $finish;
end

endmodule