data/full_repos/permissive/104269513/Fifo_mem.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/Fifo_mem.v:125: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/Fifo_mem.v:128: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk; \n        ^\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:137: Too many digits for 32 bit number: \'hff_9999_1010_0101_1010\n    in_fifo <= \'hff_9999_1010_0101_1010;\n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:141: Too many digits for 32 bit number: \'h00_0101_1010_0101_1010\n    in_fifo <= \'h00_0101_1010_0101_1010;   \n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:146: Too many digits for 32 bit number: \'h00_ABCD_AAAA_CAFE_0000\n    in_fifo <= \'h00_ABCD_AAAA_CAFE_0000; \n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:150: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n    in_fifo <= \'hff_0101_1010_0101_9999;   \n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:156: Too many digits for 32 bit number: \'hff_9999_1010_0101_1010\n    in_fifo <= \'hff_9999_1010_0101_1010;\n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:160: Too many digits for 32 bit number: \'h00_0101_1010_0101_1010\n    in_fifo <= \'h00_0101_1010_0101_1010;   \n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:163: Too many digits for 32 bit number: \'h00_ABCD_AAAA_CAFE_0000\n   in_fifo <= \'h00_ABCD_AAAA_CAFE_0000;    \n              ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:166: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n    in_fifo <= \'hff_0101_1010_0101_9999;\n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:172: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n    in_fifo <= \'hff_0101_1010_0101_9999;\n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifomem #(
				parameter ADR_WIDTH = 3,
				parameter DATA_WIDTH = 64,
				parameter CTRL_WIDTH = DATA_WIDTH/8	,
				parameter WIDTH = 72,
				parameter PROG_FULL_THRESHOLD = 2**ADR_WIDTH - 1
				)
						
				(
				input fiforead,
				input fifowrite,
				

				output full,
				output nearly_full,
				output nearly_empty,
				output empty,
				

				input [WIDTH-1:0] in_fifo,
				output reg [WIDTH-1:0] out_fifo,
				

				input clk,
				input rst);

				
parameter MAX_DEPTH = 2 ** ADR_WIDTH;
reg [ADR_WIDTH-1:0] WA;
reg [ADR_WIDTH-1:0] RA;

reg [WIDTH-1:0] queue [MAX_DEPTH-1:0];
reg [ADR_WIDTH:0] depth;


assign full = depth == MAX_DEPTH;
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;
assign nearly_empty = depth == 'h1;

assign in_rdy = (!full | !nearly_full) & fifowrite;
	
	
always @(posedge clk, posedge rst)
begin
	if (rst)
		begin
			WA <= 'h0;
			RA <= 'h0;
			depth <= 'h0;
	end
	else begin
		if (fifowrite & ~full) WA <= WA + 'h1;
		if (fiforead & ~(empty)) RA <= RA + 'h1;
		if ((fifowrite & ~full) & ~(fiforead & ~empty)) depth <= 
					depth + 'h1;
		else if (~(fifowrite & ~full) & (fiforead & ~empty)) depth <=
					depth - 'h1;


	end
end

always @(posedge clk)
begin

	out_fifo <= queue[RA];
	if (fifowrite & ~full)	queue[WA] <= in_fifo;
end

endmodule
module fifomem #(
				parameter ADR_WIDTH = 3,
				parameter DATA_WIDTH = 64,
				parameter CTRL_WIDTH = DATA_WIDTH/8	,
				parameter WIDTH = 72,
				parameter PROG_FULL_THRESHOLD = 2**ADR_WIDTH - 1
				)
						
				(
				input fiforead,
				input fifowrite,
				

				output full,
				output nearly_full,
				output nearly_empty,
				output empty,
				

				input [WIDTH-1:0] in_fifo,
				output reg [WIDTH-1:0] out_fifo,
				

				input clk,
				input rst);


				
parameter MAX_DEPTH = 2 ** ADR_WIDTH;
reg [ADR_WIDTH-1:0] WA;
reg [ADR_WIDTH-1:0] RA;

reg [WIDTH-1:0] queue [MAX_DEPTH-1:0];
reg [ADR_WIDTH:0] depth;


assign full = depth == MAX_DEPTH;
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;
assign nearly_empty = depth == 'h1;

assign in_rdy = (!full | !nearly_full) & fifowrite;
	
	
always @(posedge clk, posedge rst)
begin
	if (rst)
		begin
			WA <= 'h0;
			RA <= 'h0;
			depth <= 'h0;
	end
	else begin
		if (fifowrite & ~full) WA <= WA + 'h1;
		if (fiforead & ~(empty)) RA <= RA + 'h1;
		if ((fifowrite & ~full) & ~(fiforead & ~empty)) depth <= 
					depth + 'h1;
		else if (~(fifowrite & ~full) & (fiforead & ~empty)) depth <=
					depth - 'h1;


	end
end

always @(posedge clk)
begin

	out_fifo <= queue[RA];
	if (fifowrite & ~full)	queue[WA] <= in_fifo;
end

endmodule