data/full_repos/permissive/123218339/testbench.v
 line:685: before: ")"
1: b'%Error: data/full_repos/permissive/123218339/testbench.v:19: Cannot find include file: memory.v\n`include "memory.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123218339,data/full_repos/permissive/123218339/memory.v\n             data/full_repos/permissive/123218339,data/full_repos/permissive/123218339/memory.v.v\n             data/full_repos/permissive/123218339,data/full_repos/permissive/123218339/memory.v.sv\n             memory.v\n             memory.v.v\n             memory.v.sv\n             obj_dir/memory.v\n             obj_dir/memory.v.v\n             obj_dir/memory.v.sv\n%Error: data/full_repos/permissive/123218339/testbench.v:20: Cannot find include file: mux.v\n`include "mux.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/123218339/testbench.v:22: Cannot find include file: amISink.v\n`include "amISink.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123218339/testbench.v:23: Cannot find include file: amIForwarding.v\n`include "amIForwarding.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/123218339/testbench.v:25: Cannot find include file: neighborSinkInOtherCluster.v\n`include "neighborSinkInOtherCluster.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/123218339/testbench.v:26: Cannot find include file: findMyBest.v\n`include "findMyBest.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/123218339/testbench.v:27: Cannot find include file: betterNeighborsInMyCluster.v\n`include "betterNeighborsInMyCluster.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/123218339/testbench.v:28: Cannot find include file: selectMyAction.v\n`include "selectMyAction.v" \n         ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/123218339/testbench.v:88: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 clock = ~clock;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123218339/testbench.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #5 nrst = ~nrst;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123218339/testbench.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #25 nrst = ~nrst;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123218339/testbench.v:141: Unsupported: Ignoring delay on this delayed statement.\n            #25 nrst = ~nrst;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/123218339/testbench.v:145: Unsupported: Ignoring delay on this delayed statement.\n            #25 nrst = ~nrst;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/123218339/testbench.v:149: Unsupported: Ignoring delay on this delayed statement.\n            #25 nrst = ~nrst;\n            ^\n%Error: data/full_repos/permissive/123218339/testbench.v:166: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("testbench.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/123218339/testbench.v:167: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/123218339/testbench.v:170: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n       $display("%X%X", mem1.memory[(i*2)], mem1.memory[(i*2)+1],);\n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/123218339/testbench.v:173: Unsupported: Ignoring delay on this delayed statement.\n  #50000\n  ^\n%Error: Exiting due to 11 error(s), 7 warning(s)\n'
module testbench();
	reg clock, nrst, wr_en;
	reg done_learnCost;


    reg [`WORD_WIDTH-1:0] mem_data_in; 
    wire [`WORD_WIDTH-1:0] mem_data_out; 
	wire [`WORD_WIDTH-1:0] address;
	mem mem1(clock, address, wr_en, mem_data_in, mem_data_out);
    

    reg [2:0] addr_select;
    wire [`WORD_WIDTH-1:0] addr_0, addr_1, addr_2, addr_3, addr_4, addr_5, addr_6, addr_7;
    mux addr_mux(addr_select, address, addr_0, addr_1, addr_2, addr_3, addr_4, addr_5, addr_6, addr_7);
   

    reg [`WORD_WIDTH-1:0] MY_NODE_ID;
    wire forAggregation1, done_iamSink;
    amISink ais1(clock, nrst, done_learnCost, addr_1, mem_data_out, MY_NODE_ID, forAggregation1, done_iamSink);
  

    reg [`WORD_WIDTH-1:0] destinationID;
    wire iamForwarding, done_iamForwarding;
    amIForwarding aif1(clock, nrst, done_iamSink, MY_NODE_ID, destinationID, iamForwarding, done_iamForwarding);
	





    reg [`WORD_WIDTH-1:0] MY_CLUSTER_ID;
    wire forAggregation2, done_neighborSinkInOtherCluster;

	neighborSinkInOtherCluster nsioc1(clock, nrst, done_iamForwarding, addr_3, mem_data_out, MY_CLUSTER_ID, forAggregation2, done_neighborSinkInOtherCluster);
	










	









	initial begin
		clock = 0;
		forever #10 clock = ~clock;
	end


    initial begin
        nrst = 1;
        #5 nrst = ~nrst;
        #25 nrst = ~nrst;
    end


    initial begin
    	done_learnCost <= 1;
    	MY_NODE_ID <= 4;
    	destinationID <= 3;
    	MY_CLUSTER_ID <= 1;
    end


    always @ (*) begin
    	if (done_learnCost && !done_iamSink) begin
    		addr_select <= 1;
    	end

    	/
    end

    always @ (done_iamSink or done_iamForwarding or done_neighborSinkInOtherCluster) begin
        if (done_iamSink && forAggregation1) begin
            nrst = ~nrst;
            #25 nrst = ~nrst;
        end
        if (done_iamForwarding && !iamForwarding) begin
            nrst = ~nrst;
            #25 nrst = ~nrst;
        end
        if (done_neighborSinkInOtherCluster && forAggregation2) begin
            nrst = ~nrst;
            #25 nrst = ~nrst;
        end
    end    

	integer i;
	initial begin
		$dumpfile("testbench.vcd");
		$dumpvars(0, testbench);
		
		for (i=0;i<22;i=i+1) begin
      	$display("%X%X", mem1.memory[(i*2)], mem1.memory[(i*2)+1],);
    	end

		#50000
		$finish;
	end
endmodule
module testbench();

	reg clock, nrst, wr_en;
	reg done_learnCost;


    reg [`WORD_WIDTH-1:0] mem_data_in; 
    wire [`WORD_WIDTH-1:0] mem_data_out; 
	wire [`WORD_WIDTH-1:0] address;
	mem mem1(clock, address, wr_en, mem_data_in, mem_data_out);
    

    reg [2:0] addr_select;
    wire [`WORD_WIDTH-1:0] addr_0, addr_1, addr_2, addr_3, addr_4, addr_5, addr_6, addr_7;
    mux addr_mux(addr_select, address, addr_0, addr_1, addr_2, addr_3, addr_4, addr_5, addr_6, addr_7);
   

    reg [`WORD_WIDTH-1:0] MY_NODE_ID;
    wire forAggregation1, done_iamSink;
    amISink ais1(clock, nrst, done_learnCost, addr_1, mem_data_out, MY_NODE_ID, forAggregation1, done_iamSink);
  

    reg [`WORD_WIDTH-1:0] destinationID;
    wire iamForwarding, done_iamForwarding;
    amIForwarding aif1(clock, nrst, done_iamSink, MY_NODE_ID, destinationID, iamForwarding, done_iamForwarding);
	





    reg [`WORD_WIDTH-1:0] MY_CLUSTER_ID;
    wire forAggregation2, done_neighborSinkInOtherCluster;

	neighborSinkInOtherCluster nsioc1(clock, nrst, done_iamForwarding, addr_3, mem_data_out, MY_CLUSTER_ID, forAggregation2, done_neighborSinkInOtherCluster);
	










	









	initial begin
		clock = 0;
		forever #10 clock = ~clock;
	end


    initial begin
        nrst = 1;
        #5 nrst = ~nrst;
        #25 nrst = ~nrst;
    end


    initial begin
    	done_learnCost <= 1;
    	MY_NODE_ID <= 4;
    	destinationID <= 3;
    	MY_CLUSTER_ID <= 1;
    end


    always @ (*) begin
    	if (done_learnCost && !done_iamSink) begin
    		addr_select <= 1;
    	end

    	/
    end

    always @ (done_iamSink or done_iamForwarding or done_neighborSinkInOtherCluster) begin
        if (done_iamSink && forAggregation1) begin
            nrst = ~nrst;
            #25 nrst = ~nrst;
        end
        if (done_iamForwarding && !iamForwarding) begin
            nrst = ~nrst;
            #25 nrst = ~nrst;
        end
        if (done_neighborSinkInOtherCluster && forAggregation2) begin
            nrst = ~nrst;
            #25 nrst = ~nrst;
        end
    end    

	integer i;
	initial begin
		$dumpfile("testbench.vcd");
		$dumpvars(0, testbench);
		
		for (i=0;i<22;i=i+1) begin
      	$display("%X%X", mem1.memory[(i*2)], mem1.memory[(i*2)+1],);
    	end

		#50000
		$finish;
	end
endmodule