data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:7: Cannot find include file: ../../modules/hss_multiplexer/spio_hss_multiplexer_common.h\n`include "../../modules/hss_multiplexer/spio_hss_multiplexer_common.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/designs/raggedstone_ftdi,data/full_repos/permissive/19591557/../../modules/hss_multiplexer/spio_hss_multiplexer_common.h\n             data/full_repos/permissive/19591557/designs/raggedstone_ftdi,data/full_repos/permissive/19591557/../../modules/hss_multiplexer/spio_hss_multiplexer_common.h.v\n             data/full_repos/permissive/19591557/designs/raggedstone_ftdi,data/full_repos/permissive/19591557/../../modules/hss_multiplexer/spio_hss_multiplexer_common.h.sv\n             ../../modules/hss_multiplexer/spio_hss_multiplexer_common.h\n             ../../modules/hss_multiplexer/spio_hss_multiplexer_common.h.v\n             ../../modules/hss_multiplexer/spio_hss_multiplexer_common.h.sv\n             obj_dir/../../modules/hss_multiplexer/spio_hss_multiplexer_common.h\n             obj_dir/../../modules/hss_multiplexer/spio_hss_multiplexer_common.h.v\n             obj_dir/../../modules/hss_multiplexer/spio_hss_multiplexer_common.h.sv\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:8: Cannot find include file: ../../modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.h\n`include "../../modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:152: Define or directive not defined: \'`PKT_BITS\'\nwire [`PKT_BITS-1:0] hss_pkt_txdata_i [`NUM_CHANS-1:0];\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:152: Define or directive not defined: \'`NUM_CHANS\'\nwire [`PKT_BITS-1:0] hss_pkt_txdata_i [`NUM_CHANS-1:0];\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:153: Define or directive not defined: \'`NUM_CHANS\'\nwire                 hss_pkt_txvld_i  [`NUM_CHANS-1:0];\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:154: Define or directive not defined: \'`NUM_CHANS\'\nwire                 hss_pkt_txrdy_i  [`NUM_CHANS-1:0];\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:155: Define or directive not defined: \'`PKT_BITS\'\nwire [`PKT_BITS-1:0] hss_pkt_rxdata_i [`NUM_CHANS-1:0];\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:155: Define or directive not defined: \'`NUM_CHANS\'\nwire [`PKT_BITS-1:0] hss_pkt_rxdata_i [`NUM_CHANS-1:0];\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:156: Define or directive not defined: \'`NUM_CHANS\'\nwire                 hss_pkt_rxvld_i  [`NUM_CHANS-1:0];\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:157: Define or directive not defined: \'`NUM_CHANS\'\nwire                 hss_pkt_rxrdy_i  [`NUM_CHANS-1:0];\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:161: Define or directive not defined: \'`PKT_BITS\'\nwire [`PKT_BITS-1:0] uart_pkt_txdata_i;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:164: Define or directive not defined: \'`PKT_BITS\'\nwire [`PKT_BITS-1:0] uart_pkt_rxdata_i;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:184: Define or directive not defined: \'`REGA_BITS\'\nwire [`REGA_BITS-1:0] reg_addr_i;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:185: Define or directive not defined: \'`REGD_BITS\'\nwire [`REGD_BITS-1:0] reg_read_data_i;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:186: Define or directive not defined: \'`REGD_BITS\'\nwire [`REGD_BITS-1:0] reg_write_data_i;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:529: Define or directive not defined: \'`PKT_BITS\'\nwire [`PKT_BITS-1:0] fast_uart_pkt_txdata_i;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:532: Define or directive not defined: \'`PKT_BITS\'\nwire [`PKT_BITS-1:0] fast_uart_pkt_rxdata_i;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:565: Define or directive not defined: \'`PKT_BITS\'\nspio_link_speed_halver #( .PKT_BITS(`PKT_BITS))\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:578: Define or directive not defined: \'`PKT_BITS\'\nspio_link_speed_doubler #( .PKT_BITS(`PKT_BITS))\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:616: Define or directive not defined: \'`NUM_CHANS\'\ngenerate for (i = 2; i < `NUM_CHANS; i = i + 1)\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:616: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\ngenerate for (i = 2; i < `NUM_CHANS; i = i + 1)\n                                   ^\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:618: Define or directive not defined: \'`PKT_BITS\'\n  assign hss_pkt_txdata_i[i] = {`PKT_BITS{1\'bX}};\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:620: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:634: syntax error, unexpected generate\ngenerate for (i = 1; i < `NUM_CHANS; i = i + 1)\n^~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:634: Define or directive not defined: \'`NUM_CHANS\'\ngenerate for (i = 1; i < `NUM_CHANS; i = i + 1)\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:653: Define or directive not defined: \'`REGA_BITS\'\n  wire [1+`REGA_BITS+`REGD_BITS-1:0] chipscope_sync_out_i;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:653: Define or directive not defined: \'`REGD_BITS\'\n  wire [1+`REGA_BITS+`REGD_BITS-1:0] chipscope_sync_out_i;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:667: Define or directive not defined: \'`REGA_BITS\'\n  assign reg_addr_i                         = chipscope_sync_out_i[1+:`REGA_BITS];\n                                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:667: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign reg_addr_i                         = chipscope_sync_out_i[1+:`REGA_BITS];\n                                                                                ^\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:668: Define or directive not defined: \'`REGA_BITS\'\n  assign reg_write_data_i                   = chipscope_sync_out_i[1+`REGA_BITS+:`REGD_BITS];\n                                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:668: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n  assign reg_write_data_i                   = chipscope_sync_out_i[1+`REGA_BITS+:`REGD_BITS];\n                                                                               ^~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:668: Define or directive not defined: \'`REGD_BITS\'\n  assign reg_write_data_i                   = chipscope_sync_out_i[1+`REGA_BITS+:`REGD_BITS];\n                                                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:669: Define or directive not defined: \'`REGD_BITS\'\n  assign chipscope_sync_in_i[0+:`REGD_BITS] = reg_read_data_i;\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:669: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign chipscope_sync_in_i[0+:`REGD_BITS] = reg_read_data_i;\n                                          ^\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:672: Define or directive not defined: \'`REGD_BITS\'\n  assign chipscope_sync_in_i[`REGD_BITS+0 +:8] = { hss_pkt_rxrdy_i[7]\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:681: Define or directive not defined: \'`REGD_BITS\'\n  assign chipscope_sync_in_i[`REGD_BITS+8 +:8] = { hss_pkt_rxvld_i[7]\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:691: Define or directive not defined: \'`REGD_BITS\'\n  assign chipscope_sync_in_i[`REGD_BITS+16+:8] = { hss_pkt_txrdy_i[7]\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:700: Define or directive not defined: \'`REGD_BITS\'\n  assign chipscope_sync_in_i[`REGD_BITS+24+:8] = { hss_pkt_txvld_i[7]\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:711: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:717: Define or directive not defined: \'`VERS_REG\'\n  assign reg_addr_i       = `VERS_REG;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:717: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign reg_addr_i       = `VERS_REG;\n                                     ^\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:718: Define or directive not defined: \'`REGD_BITS\'\n  assign reg_write_data_i = {`REGD_BITS{1\'bX}};\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_ftdi/raggedstone_ftdi_top.v:720: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n'
module raggedstone_ftdi_top #(
                               parameter SIMULATION = 0

                             , parameter SIMULATION_GTPRESET_SPEEDUP = 0


                             , parameter DEBUG_CHIPSCOPE_VIO = 1


                             , parameter CLOCK_CORRECTION_INTERVAL = 1000

                             , parameter CLOCK_CORRECTION_INTERVAL_BITS = 10


                             , parameter NUM_HANDSHAKES = 100

                             , parameter NUM_HANDSHAKES_BITS = 7





                             , parameter UART_RX_BUFFER_ADDR_BITS = 4


                             , parameter UART_RX_HIGH_WATER_MARK = 8
                             )
                             (
                               input wire NRESET_IN
                               

                             , input wire NBUTTON_IN
                               

                             , output wire [5:2] LEDS_OUT
                               

                             , input wire REFCLK_PAD_P_IN
                             , input wire REFCLK_PAD_N_IN
                             

                             , input  wire HSS_RXN_IN
                             , input  wire HSS_RXP_IN
                             , output wire HSS_TXN_OUT
                             , output wire HSS_TXP_OUT
                               

                             , output wire FTDI_CTS_N_OUT
                             , output wire FTDI_DCD_N_OUT
                             , output wire FTDI_DSR_N_OUT
                             , output wire FTDI_RI_N_OUT
                             , input  wire FTDI_RTS_N_IN
                             , input  wire FTDI_DTR_N_IN
                             , input  wire FTDI_TXD_IN
                             , output wire FTDI_RXD_OUT
                             );

genvar i;


localparam GTP_LOOPBACK = 3'b000;


localparam RXEQMIX       =   2'b00;
localparam TXDIFFCTRL    = 4'b0000;
localparam TXPREEMPHASIS =  3'b000;







wire nreset_i;
wire reset_i;


wire gtp_reset_i;


wire clk_reset_i;


wire hss_reset_i;


wire led_reset_i;


wire [5:2] leds_i;


wire       nbutton_i;
wire       button_i;
reg  [1:0] button_sync_i;


wire gtpclkin_i;


wire [1:0] unbuffered_gtpclkout_i;
wire gtpclkout_i;


wire plllkdet_i;


wire gtpresetdone_i;


wire usrclk_i;
wire usrclk2_i;


wire uart_clk_i;


wire led_clk_i;


wire usrclks_stable_i;


wire [1:0] rxlossofsync_i;


wire [31:0] rxdata_i;
wire  [3:0] rxchariscomma_i;
wire  [3:0] rxcharisk_i;


wire [31:0] txdata_i;
wire  [3:0] txcharisk_i;



wire handshake_complete_i;
wire version_mismatch_i;



wire [`PKT_BITS-1:0] hss_pkt_txdata_i [`NUM_CHANS-1:0];
wire                 hss_pkt_txvld_i  [`NUM_CHANS-1:0];
wire                 hss_pkt_txrdy_i  [`NUM_CHANS-1:0];
wire [`PKT_BITS-1:0] hss_pkt_rxdata_i [`NUM_CHANS-1:0];
wire                 hss_pkt_rxvld_i  [`NUM_CHANS-1:0];
wire                 hss_pkt_rxrdy_i  [`NUM_CHANS-1:0];



wire [`PKT_BITS-1:0] uart_pkt_txdata_i;
wire                 uart_pkt_txvld_i;
wire                 uart_pkt_txrdy_i;
wire [`PKT_BITS-1:0] uart_pkt_rxdata_i;
wire                 uart_pkt_rxvld_i;
wire                 uart_pkt_rxrdy_i;


wire uart_rx_i;
wire uart_rx_synced_i;
wire uart_tx_i;
wire uart_cts_i;


wire uart_synchronising_i;



wire hss_activity_i;
wire uart_activity_i;


wire                  reg_write_i;
wire [`REGA_BITS-1:0] reg_addr_i;
wire [`REGD_BITS-1:0] reg_read_data_i;
wire [`REGD_BITS-1:0] reg_write_data_i;







IBUF nbuttons_buf_i (.I(NBUTTON_IN), .O(nbutton_i));


assign button_i = ~nbutton_i;


always @ (posedge usrclk2_i)
	button_sync_i <= {button_sync_i[0], button_i};







IBUF reset_buf (.I (NRESET_IN), .O (nreset_i));
assign reset_i = ~nreset_i;

assign gtp_reset_i = reset_i;

assign clk_reset_i = reset_i | !plllkdet_i;



assign hss_reset_i = !gtpresetdone_i & !usrclks_stable_i;

assign led_reset_i = !usrclks_stable_i;







OBUF leds_buf_i [5:2] (.I(leds_i[5:2]), .O(LEDS_OUT[5:2]));



spio_status_led_generator     #(
                                 .NUM_DEVICES(2)

                               , .ANIMATION_PERIOD_BITS(SIMULATION ? 10 : 26)

                               , .PULSE_DURATION(SIMULATION ? 2 : 3750000)


                               , .ACTIVITY_BLINK_BIT(SIMULATION ? 5 : 21)

                               , .PWM_BITS(7)


                               , .ACTIVITY_TIMEOUT(SIMULATION ? 2048 : 9375000)
                               , .ACTIVITY_TIMEOUT_BITS(24)
                               )
spio_status_led_generator_hss_i( .CLK_IN               (led_clk_i)
                               , .RESET_IN             (led_reset_i)
                               , .ERROR_IN             ({1'b0,                  version_mismatch_i})
                               , .CONNECTED_IN         ({!uart_synchronising_i, handshake_complete_i})
                               , .ACTIVITY_IN          ({uart_activity_i,       hss_activity_i})
                               , .LED_OUT              (leds_i[3:2])
                               , .ANIMATION_REPEAT_OUT ()
                               );


assign leds_i[5:4] = 2'b00;



assign hss_activity_i = (hss_pkt_rxvld_i[0] & hss_pkt_rxrdy_i[0])
                      | (hss_pkt_rxvld_i[1] & hss_pkt_rxrdy_i[1])
                      | (hss_pkt_rxvld_i[2] & hss_pkt_rxrdy_i[2])
                      | (hss_pkt_rxvld_i[3] & hss_pkt_rxrdy_i[3])
                      | (hss_pkt_rxvld_i[4] & hss_pkt_rxrdy_i[4])
                      | (hss_pkt_rxvld_i[5] & hss_pkt_rxrdy_i[5])
                      | (hss_pkt_rxvld_i[6] & hss_pkt_rxrdy_i[6])
                      | (hss_pkt_rxvld_i[7] & hss_pkt_rxrdy_i[7])
                      | (hss_pkt_txvld_i[0] & hss_pkt_txrdy_i[0])
                      | (hss_pkt_txvld_i[1] & hss_pkt_txrdy_i[1])
                      | (hss_pkt_txvld_i[2] & hss_pkt_txrdy_i[2])
                      | (hss_pkt_txvld_i[3] & hss_pkt_txrdy_i[3])
                      | (hss_pkt_txvld_i[4] & hss_pkt_txrdy_i[4])
                      | (hss_pkt_txvld_i[5] & hss_pkt_txrdy_i[5])
                      | (hss_pkt_txvld_i[6] & hss_pkt_txrdy_i[6])
                      | (hss_pkt_txvld_i[7] & hss_pkt_txrdy_i[7])
                      ;



assign uart_activity_i = (uart_pkt_rxvld_i & uart_pkt_rxrdy_i)
                       | (uart_pkt_txvld_i & uart_pkt_txrdy_i)
                       ;







IBUFDS refclk_ibufds_i ( .O (gtpclkin_i)
                       , .I (REFCLK_PAD_P_IN)
                       , .IB(REFCLK_PAD_N_IN)
                       );


BUFIO2 # (.DIVIDE (1), .DIVIDE_BYPASS ("TRUE"))
gtpclkout_0_pll_bufio2_i ( .I            (unbuffered_gtpclkout_i[0])
                         , .DIVCLK       (gtpclkout_i)
                         , .IOCLK        ()
                         , .SERDESSTROBE ()
                         );



wire clk_150_i;
wire clk_75_i;
wire clk_37_5_i;
clock_scaler
clock_scaler_i ( .CLK_IN1  (gtpclkout_i)
               , .CLK_OUT1 (clk_150_i)
               , .CLK_OUT2 (clk_75_i)
               , .CLK_OUT3 (clk_37_5_i)
               , .RESET    (clk_reset_i)
               , .LOCKED   (usrclks_stable_i)
               );

assign usrclk_i   = clk_150_i;
assign usrclk2_i  = clk_37_5_i;

assign uart_clk_i = clk_75_i;

assign led_clk_i  = clk_37_5_i;










gtp_x0_y0  #( .WRAPPER_SIM_GTPRESET_SPEEDUP (SIMULATION_GTPRESET_SPEEDUP)
            , .WRAPPER_SIMULATION           (SIMULATION)
            )
gtp_x0_y0_i (

                .TILE0_LOOPBACK0_IN         (3'b000)
            ,   .TILE0_LOOPBACK1_IN         (GTP_LOOPBACK)

            ,   .TILE0_CLK00_IN             (gtpclkin_i)
            ,   .TILE0_CLK01_IN             (1'b0)
            ,   .TILE0_GTPRESET0_IN         (gtp_reset_i)
            ,   .TILE0_GTPRESET1_IN         (gtp_reset_i)
            ,   .TILE0_PLLLKDET0_OUT        (plllkdet_i)
            ,   .TILE0_RESETDONE0_OUT       ()
            ,   .TILE0_RESETDONE1_OUT       (gtpresetdone_i)

            ,   .TILE0_RXCHARISCOMMA0_OUT   ()
            ,   .TILE0_RXCHARISCOMMA1_OUT   (rxchariscomma_i)
            ,   .TILE0_RXCHARISK0_OUT       ()
            ,   .TILE0_RXCHARISK1_OUT       (rxcharisk_i)
            ,   .TILE0_RXDISPERR0_OUT       ()
            ,   .TILE0_RXDISPERR1_OUT       ()
            ,   .TILE0_RXNOTINTABLE0_OUT    ()
            ,   .TILE0_RXNOTINTABLE1_OUT    ()

            ,   .TILE0_RXCLKCORCNT0_OUT     ()
            ,   .TILE0_RXCLKCORCNT1_OUT     ()

            ,   .TILE0_RXENMCOMMAALIGN0_IN  (1'b1)
            ,   .TILE0_RXENMCOMMAALIGN1_IN  (1'b1)
            ,   .TILE0_RXENPCOMMAALIGN0_IN  (1'b1)
            ,   .TILE0_RXENPCOMMAALIGN1_IN  (1'b1)

            ,   .TILE0_RXDATA0_OUT          ()
            ,   .TILE0_RXDATA1_OUT          (rxdata_i)
            ,   .TILE0_RXUSRCLK0_IN         (1'b0)
            ,   .TILE0_RXUSRCLK1_IN         (usrclk_i)
            ,   .TILE0_RXUSRCLK20_IN        (1'b0)
            ,   .TILE0_RXUSRCLK21_IN        (usrclk2_i)

            ,   .TILE0_RXN0_IN              (1'bX)
            ,   .TILE0_RXN1_IN              (HSS_RXN_IN)
            ,   .TILE0_RXP0_IN              (1'bX)
            ,   .TILE0_RXP1_IN              (HSS_RXP_IN)

            ,   .TILE0_RXLOSSOFSYNC0_OUT    ()
            ,   .TILE0_RXLOSSOFSYNC1_OUT    (rxlossofsync_i)

            ,   .TILE0_GTPCLKOUT0_OUT       (unbuffered_gtpclkout_i)
            ,   .TILE0_GTPCLKOUT1_OUT       ()

            ,   .TILE0_TXCHARISK0_IN        (4'bXXXX)
            ,   .TILE0_TXCHARISK1_IN        (txcharisk_i)

            ,   .TILE0_TXDATA0_IN           (32'hXXXX)
            ,   .TILE0_TXDATA1_IN           (txdata_i)
            ,   .TILE0_TXUSRCLK0_IN         (1'b0)
            ,   .TILE0_TXUSRCLK1_IN         (usrclk_i)
            ,   .TILE0_TXUSRCLK20_IN        (1'b0)
            ,   .TILE0_TXUSRCLK21_IN        (usrclk2_i)

            ,   .TILE0_TXN0_OUT             ()
            ,   .TILE0_TXN1_OUT             (HSS_TXN_OUT)
            ,   .TILE0_TXP0_OUT             ()
            ,   .TILE0_TXP1_OUT             (HSS_TXP_OUT)

            ,   .TILE0_RXCHANBONDSEQ0_OUT   ()
            ,   .TILE0_RXCHANBONDSEQ1_OUT   ()
            ,   .TILE0_RXCHANISALIGNED0_OUT ()
            ,   .TILE0_RXCHANISALIGNED1_OUT ()
            ,   .TILE0_RXCHANREALIGN0_OUT   ()
            ,   .TILE0_RXCHANREALIGN1_OUT   ()
            ,   .TILE0_RXCHBONDMASTER0_IN   (1'b0)
            ,   .TILE0_RXCHBONDMASTER1_IN   (1'b0)
            ,   .TILE0_RXCHBONDSLAVE0_IN    (1'b0)
            ,   .TILE0_RXCHBONDSLAVE1_IN    (1'b0)
            ,   .TILE0_RXENCHANSYNC0_IN     (1'b0)
            ,   .TILE0_RXENCHANSYNC1_IN     (1'b0)

            ,   .TILE0_RXEQMIX0_IN              (2'b00)
            ,   .TILE0_RXEQMIX1_IN              (RXEQMIX)
            ,   .TILE0_TXDIFFCTRL0_IN           (4'b0000)
            ,   .TILE0_TXDIFFCTRL1_IN           (TXDIFFCTRL)
            ,   .TILE0_TXPREEMPHASIS0_IN        (3'b000)
            ,   .TILE0_TXPREEMPHASIS1_IN        (TXPREEMPHASIS)
            );






spio_hss_multiplexer   #( .CLOCK_CORRECTION_INTERVAL      (CLOCK_CORRECTION_INTERVAL)
                        , .CLOCK_CORRECTION_INTERVAL_BITS (CLOCK_CORRECTION_INTERVAL_BITS)
                        , .NUM_HANDSHAKES                 (NUM_HANDSHAKES)
                        , .NUM_HANDSHAKES_BITS            (NUM_HANDSHAKES_BITS)
                        )
periph_hss_multiplexer_i( .CLK_IN                         (usrclk2_i)
                        , .RESET_IN                       (hss_reset_i)

                        , .HANDSHAKE_COMPLETE_OUT         (handshake_complete_i)
                        , .VERSION_MISMATCH_OUT           (version_mismatch_i)

                        , .RXDATA_IN                      (rxdata_i)
                        , .RXCHARISCOMMA_IN               (rxchariscomma_i)
                        , .RXCHARISK_IN                   (rxcharisk_i)
                        , .RXLOSSOFSYNC_IN                (rxlossofsync_i)
                        , .TXDATA_OUT                     (txdata_i)
                        , .TXCHARISK_OUT                  (txcharisk_i)

                        , .TX_PKT0_DATA_IN                (hss_pkt_txdata_i[0])
                        , .TX_PKT0_VLD_IN                 (hss_pkt_txvld_i[0])
                        , .TX_PKT0_RDY_OUT                (hss_pkt_txrdy_i[0])
                        , .TX_PKT1_DATA_IN                (hss_pkt_txdata_i[1])
                        , .TX_PKT1_VLD_IN                 (hss_pkt_txvld_i[1])
                        , .TX_PKT1_RDY_OUT                (hss_pkt_txrdy_i[1])
                        , .TX_PKT2_DATA_IN                (hss_pkt_txdata_i[2])
                        , .TX_PKT2_VLD_IN                 (hss_pkt_txvld_i[2])
                        , .TX_PKT2_RDY_OUT                (hss_pkt_txrdy_i[2])
                        , .TX_PKT3_DATA_IN                (hss_pkt_txdata_i[3])
                        , .TX_PKT3_VLD_IN                 (hss_pkt_txvld_i[3])
                        , .TX_PKT3_RDY_OUT                (hss_pkt_txrdy_i[3])
                        , .TX_PKT4_DATA_IN                (hss_pkt_txdata_i[4])
                        , .TX_PKT4_VLD_IN                 (hss_pkt_txvld_i[4])
                        , .TX_PKT4_RDY_OUT                (hss_pkt_txrdy_i[4])
                        , .TX_PKT5_DATA_IN                (hss_pkt_txdata_i[5])
                        , .TX_PKT5_VLD_IN                 (hss_pkt_txvld_i[5])
                        , .TX_PKT5_RDY_OUT                (hss_pkt_txrdy_i[5])
                        , .TX_PKT6_DATA_IN                (hss_pkt_txdata_i[6])
                        , .TX_PKT6_VLD_IN                 (hss_pkt_txvld_i[6])
                        , .TX_PKT6_RDY_OUT                (hss_pkt_txrdy_i[6])
                        , .TX_PKT7_DATA_IN                (hss_pkt_txdata_i[7])
                        , .TX_PKT7_VLD_IN                 (hss_pkt_txvld_i[7])
                        , .TX_PKT7_RDY_OUT                (hss_pkt_txrdy_i[7])
                        , .RX_PKT0_DATA_OUT               (hss_pkt_rxdata_i[0])
                        , .RX_PKT0_VLD_OUT                (hss_pkt_rxvld_i[0])
                        , .RX_PKT0_RDY_IN                 (hss_pkt_rxrdy_i[0])
                        , .RX_PKT1_DATA_OUT               (hss_pkt_rxdata_i[1])
                        , .RX_PKT1_VLD_OUT                (hss_pkt_rxvld_i[1])
                        , .RX_PKT1_RDY_IN                 (hss_pkt_rxrdy_i[1])
                        , .RX_PKT2_DATA_OUT               (hss_pkt_rxdata_i[2])
                        , .RX_PKT2_VLD_OUT                (hss_pkt_rxvld_i[2])
                        , .RX_PKT2_RDY_IN                 (hss_pkt_rxrdy_i[2])
                        , .RX_PKT3_DATA_OUT               (hss_pkt_rxdata_i[3])
                        , .RX_PKT3_VLD_OUT                (hss_pkt_rxvld_i[3])
                        , .RX_PKT3_RDY_IN                 (hss_pkt_rxrdy_i[3])
                        , .RX_PKT4_DATA_OUT               (hss_pkt_rxdata_i[4])
                        , .RX_PKT4_VLD_OUT                (hss_pkt_rxvld_i[4])
                        , .RX_PKT4_RDY_IN                 (hss_pkt_rxrdy_i[4])
                        , .RX_PKT5_DATA_OUT               (hss_pkt_rxdata_i[5])
                        , .RX_PKT5_VLD_OUT                (hss_pkt_rxvld_i[5])
                        , .RX_PKT5_RDY_IN                 (hss_pkt_rxrdy_i[5])
                        , .RX_PKT6_DATA_OUT               (hss_pkt_rxdata_i[6])
                        , .RX_PKT6_VLD_OUT                (hss_pkt_rxvld_i[6])
                        , .RX_PKT6_RDY_IN                 (hss_pkt_rxrdy_i[6])
                        , .RX_PKT7_DATA_OUT               (hss_pkt_rxdata_i[7])
                        , .RX_PKT7_VLD_OUT                (hss_pkt_rxvld_i[7])
                        , .RX_PKT7_RDY_IN                 (hss_pkt_rxrdy_i[7])

		                    , .REG_WRITE_IN                   (reg_write_i)
		                    , .REG_ADDR_IN                    (reg_addr_i)
		                    , .REG_READ_DATA_OUT              (reg_read_data_i)
		                    , .REG_WRITE_DATA_IN              (reg_write_data_i)
                        );







OBUF ftdi_cts_n_buf_i (.I (!uart_cts_i), .O(FTDI_CTS_N_OUT));
OBUF ftdi_dcd_n_buf_i (.I (1'b1),        .O(FTDI_DCD_N_OUT));
OBUF ftdi_dsr_n_buf_i (.I (1'b1),        .O(FTDI_DSR_N_OUT));
OBUF ftdi_ri_n_buf_i  (.I (1'b1),        .O(FTDI_RI_N_OUT));
IBUF ftdi_rts_n_buf_i (.O (),            .I(FTDI_RTS_N_IN));
IBUF ftdi_dtr_n_buf_i (.O (),            .I(FTDI_DTR_N_IN));
IBUF ftdi_txd_buf_i   (.O (uart_rx_i),   .I(FTDI_TXD_IN));
OBUF ftdi_rxd_buf_i   (.I (uart_tx_i),   .O(FTDI_RXD_OUT));



spio_uart_sync         #( .NUM_BITS      (1)
                        , .NUM_STAGES    (2)
                        , .INITIAL_VALUE (1'b1)
                        )
spio_uart_sync_tx_data_i( .CLK_IN   (uart_clk_i)
                        , .RESET_IN (reset_i)
                        , .DATA_IN  (uart_rx_i)
                        , .DATA_OUT (uart_rx_synced_i)
                        );



wire [`PKT_BITS-1:0] fast_uart_pkt_txdata_i;
wire                 fast_uart_pkt_txvld_i;
wire                 fast_uart_pkt_txrdy_i;
wire [`PKT_BITS-1:0] fast_uart_pkt_rxdata_i;
wire                 fast_uart_pkt_rxvld_i;
wire                 fast_uart_pkt_rxrdy_i;


spio_uart #( .IS_MASTER           (1'b0)
           , .BAUD_PERIOD         (75_000_000/3_000_000)
           , .BAUD_NUM_BITS       (5)
           , .RX_BUFFER_ADDR_BITS (UART_RX_BUFFER_ADDR_BITS)
           , .RX_HIGH_WATER_MARK  (UART_RX_HIGH_WATER_MARK)
           )
spio_uart_i( .CLK_IN                (uart_clk_i)
           , .RESET_IN              (reset_i)

           , .RX_IN                 (uart_rx_synced_i)
           , .CTS_IN                (1'b1)
           , .TX_OUT                (uart_tx_i)
           , .CTS_OUT               (uart_cts_i)

           , .RX_DATA_OUT           (fast_uart_pkt_rxdata_i)
           , .RX_VLD_OUT            (fast_uart_pkt_rxvld_i)
           , .RX_RDY_IN             (fast_uart_pkt_rxrdy_i)
           , .RX_PACKET_DROPPED_OUT ()
           , .TX_DATA_IN            (fast_uart_pkt_txdata_i)
           , .TX_VLD_IN             (fast_uart_pkt_txvld_i)
           , .TX_RDY_OUT            (fast_uart_pkt_txrdy_i)
           , .TX_PACKET_DROPPED_OUT ()

           , .SYNC_TRIGGER_IN       (1'b0)
           , .SYNCHRONISING_OUT     (uart_synchronising_i)
           );


spio_link_speed_halver #( .PKT_BITS(`PKT_BITS))
spio_link_speed_halver_i( .RESET_IN(reset_i)
                        , .SCLK_IN(usrclk2_i)
                        , .FCLK_IN(uart_clk_i)

                        , .DATA_IN(fast_uart_pkt_rxdata_i)
                        , .VLD_IN( fast_uart_pkt_rxvld_i)
                        , .RDY_OUT(fast_uart_pkt_rxrdy_i)

                        , .DATA_OUT(uart_pkt_rxdata_i)
                        , .VLD_OUT( uart_pkt_rxvld_i)
                        , .RDY_IN(  uart_pkt_rxrdy_i)
                        );
spio_link_speed_doubler #( .PKT_BITS(`PKT_BITS))
spio_link_speed_doubler_i( .RESET_IN(reset_i)
                         , .SCLK_IN(usrclk2_i)
                         , .FCLK_IN(uart_clk_i)

                         , .DATA_IN(uart_pkt_txdata_i)
                         , .VLD_IN( uart_pkt_txvld_i)
                         , .RDY_OUT(uart_pkt_txrdy_i)

                         , .DATA_OUT(fast_uart_pkt_txdata_i)
                         , .VLD_OUT( fast_uart_pkt_txvld_i)
                         , .RDY_IN(  fast_uart_pkt_txrdy_i)
                         );







assign hss_pkt_txdata_i[0] = uart_pkt_rxdata_i;
assign hss_pkt_txvld_i[0]  = uart_pkt_rxvld_i;
assign uart_pkt_rxrdy_i    = hss_pkt_txrdy_i[0];


assign hss_pkt_txdata_i[1] = { 32'hF0A0F030
                             , 32'h0000AAAA
                             , 2'b00
                             , 2'b00
                             , 2'b00
                             , 1'b1
                             , 1'b0
                             };


assign hss_pkt_txvld_i[1]  = button_sync_i[1];


generate for (i = 2; i < `NUM_CHANS; i = i + 1)
	begin : spinnaker_inactive_tx_links
		assign hss_pkt_txdata_i[i] = {`PKT_BITS{1'bX}};
		assign hss_pkt_txvld_i[i]  = 1'b0;
	end
endgenerate







assign uart_pkt_txdata_i  = hss_pkt_rxdata_i[0];
assign uart_pkt_txvld_i   = hss_pkt_rxvld_i[0];
assign hss_pkt_rxrdy_i[0] = uart_pkt_rxrdy_i;


generate for (i = 1; i < `NUM_CHANS; i = i + 1)
	begin : spinnaker_inactive_rx_links
		assign hss_pkt_rxrdy_i[i] = 1'b1;
	end
endgenerate








generate if (DEBUG_CHIPSCOPE_VIO)
	begin : chipscope_enabled
		
		wire [35:0] chipscope_control_i;
		
		wire [63:0]                        chipscope_sync_in_i;
		wire [1+`REGA_BITS+`REGD_BITS-1:0] chipscope_sync_out_i;
		

		chipscope_icon chipscope_icon_i (.CONTROL0 (chipscope_control_i));
		

		chipscope_vio chipscope_vio_i ( .CONTROL (chipscope_control_i)
		                              , .CLK     (usrclk2_i)
		                              , .SYNC_IN (chipscope_sync_in_i)
		                              , .SYNC_OUT(chipscope_sync_out_i)
		                              );
		

		assign reg_write_i                        = chipscope_sync_out_i[0];
		assign reg_addr_i                         = chipscope_sync_out_i[1+:`REGA_BITS];
		assign reg_write_data_i                   = chipscope_sync_out_i[1+`REGA_BITS+:`REGD_BITS];
		assign chipscope_sync_in_i[0+:`REGD_BITS] = reg_read_data_i;
		

		assign chipscope_sync_in_i[`REGD_BITS+0 +:8] = { hss_pkt_rxrdy_i[7]
		                                               , hss_pkt_rxrdy_i[6]
		                                               , hss_pkt_rxrdy_i[5]
		                                               , hss_pkt_rxrdy_i[4]
		                                               , hss_pkt_rxrdy_i[3]
		                                               , hss_pkt_rxrdy_i[2]
		                                               , hss_pkt_rxrdy_i[1]
		                                               , hss_pkt_rxrdy_i[0]
		                                               };
		assign chipscope_sync_in_i[`REGD_BITS+8 +:8] = { hss_pkt_rxvld_i[7]
		                                               , hss_pkt_rxvld_i[6]
		                                               , hss_pkt_rxvld_i[5]
		                                               , hss_pkt_rxvld_i[4]
		                                               , hss_pkt_rxvld_i[3]
		                                               , hss_pkt_rxvld_i[2]
		                                               , hss_pkt_rxvld_i[1]
		                                               , hss_pkt_rxvld_i[0]
		                                               };

		assign chipscope_sync_in_i[`REGD_BITS+16+:8] = { hss_pkt_txrdy_i[7]
		                                               , hss_pkt_txrdy_i[6]
		                                               , hss_pkt_txrdy_i[5]
		                                               , hss_pkt_txrdy_i[4]
		                                               , hss_pkt_txrdy_i[3]
		                                               , hss_pkt_txrdy_i[2]
		                                               , hss_pkt_txrdy_i[1]
		                                               , hss_pkt_txrdy_i[0]
		                                               };
		assign chipscope_sync_in_i[`REGD_BITS+24+:8] = { hss_pkt_txvld_i[7]
		                                               , hss_pkt_txvld_i[6]
		                                               , hss_pkt_txvld_i[5]
		                                               , hss_pkt_txvld_i[4]
		                                               , hss_pkt_txvld_i[3]
		                                               , hss_pkt_txvld_i[2]
		                                               , hss_pkt_txvld_i[1]
		                                               , hss_pkt_txvld_i[0]
		                                               };
		
		
	end
else
	begin : chipscope_disabled
		

		assign reg_write_i      = 1'b0;
		assign reg_addr_i       = `VERS_REG;
		assign reg_write_data_i = {`REGD_BITS{1'bX}};
		
	end
endgenerate


endmodule
module raggedstone_ftdi_top #(
                               parameter SIMULATION = 0

                             , parameter SIMULATION_GTPRESET_SPEEDUP = 0


                             , parameter DEBUG_CHIPSCOPE_VIO = 1


                             , parameter CLOCK_CORRECTION_INTERVAL = 1000

                             , parameter CLOCK_CORRECTION_INTERVAL_BITS = 10


                             , parameter NUM_HANDSHAKES = 100

                             , parameter NUM_HANDSHAKES_BITS = 7





                             , parameter UART_RX_BUFFER_ADDR_BITS = 4


                             , parameter UART_RX_HIGH_WATER_MARK = 8
                             )
                             (
                               input wire NRESET_IN
                               

                             , input wire NBUTTON_IN
                               

                             , output wire [5:2] LEDS_OUT
                               

                             , input wire REFCLK_PAD_P_IN
                             , input wire REFCLK_PAD_N_IN
                             

                             , input  wire HSS_RXN_IN
                             , input  wire HSS_RXP_IN
                             , output wire HSS_TXN_OUT
                             , output wire HSS_TXP_OUT
                               

                             , output wire FTDI_CTS_N_OUT
                             , output wire FTDI_DCD_N_OUT
                             , output wire FTDI_DSR_N_OUT
                             , output wire FTDI_RI_N_OUT
                             , input  wire FTDI_RTS_N_IN
                             , input  wire FTDI_DTR_N_IN
                             , input  wire FTDI_TXD_IN
                             , output wire FTDI_RXD_OUT
                             );


genvar i;


localparam GTP_LOOPBACK = 3'b000;


localparam RXEQMIX       =   2'b00;
localparam TXDIFFCTRL    = 4'b0000;
localparam TXPREEMPHASIS =  3'b000;







wire nreset_i;
wire reset_i;


wire gtp_reset_i;


wire clk_reset_i;


wire hss_reset_i;


wire led_reset_i;


wire [5:2] leds_i;


wire       nbutton_i;
wire       button_i;
reg  [1:0] button_sync_i;


wire gtpclkin_i;


wire [1:0] unbuffered_gtpclkout_i;
wire gtpclkout_i;


wire plllkdet_i;


wire gtpresetdone_i;


wire usrclk_i;
wire usrclk2_i;


wire uart_clk_i;


wire led_clk_i;


wire usrclks_stable_i;


wire [1:0] rxlossofsync_i;


wire [31:0] rxdata_i;
wire  [3:0] rxchariscomma_i;
wire  [3:0] rxcharisk_i;


wire [31:0] txdata_i;
wire  [3:0] txcharisk_i;



wire handshake_complete_i;
wire version_mismatch_i;



wire [`PKT_BITS-1:0] hss_pkt_txdata_i [`NUM_CHANS-1:0];
wire                 hss_pkt_txvld_i  [`NUM_CHANS-1:0];
wire                 hss_pkt_txrdy_i  [`NUM_CHANS-1:0];
wire [`PKT_BITS-1:0] hss_pkt_rxdata_i [`NUM_CHANS-1:0];
wire                 hss_pkt_rxvld_i  [`NUM_CHANS-1:0];
wire                 hss_pkt_rxrdy_i  [`NUM_CHANS-1:0];



wire [`PKT_BITS-1:0] uart_pkt_txdata_i;
wire                 uart_pkt_txvld_i;
wire                 uart_pkt_txrdy_i;
wire [`PKT_BITS-1:0] uart_pkt_rxdata_i;
wire                 uart_pkt_rxvld_i;
wire                 uart_pkt_rxrdy_i;


wire uart_rx_i;
wire uart_rx_synced_i;
wire uart_tx_i;
wire uart_cts_i;


wire uart_synchronising_i;



wire hss_activity_i;
wire uart_activity_i;


wire                  reg_write_i;
wire [`REGA_BITS-1:0] reg_addr_i;
wire [`REGD_BITS-1:0] reg_read_data_i;
wire [`REGD_BITS-1:0] reg_write_data_i;







IBUF nbuttons_buf_i (.I(NBUTTON_IN), .O(nbutton_i));


assign button_i = ~nbutton_i;


always @ (posedge usrclk2_i)
	button_sync_i <= {button_sync_i[0], button_i};







IBUF reset_buf (.I (NRESET_IN), .O (nreset_i));
assign reset_i = ~nreset_i;

assign gtp_reset_i = reset_i;

assign clk_reset_i = reset_i | !plllkdet_i;



assign hss_reset_i = !gtpresetdone_i & !usrclks_stable_i;

assign led_reset_i = !usrclks_stable_i;







OBUF leds_buf_i [5:2] (.I(leds_i[5:2]), .O(LEDS_OUT[5:2]));



spio_status_led_generator     #(
                                 .NUM_DEVICES(2)

                               , .ANIMATION_PERIOD_BITS(SIMULATION ? 10 : 26)

                               , .PULSE_DURATION(SIMULATION ? 2 : 3750000)


                               , .ACTIVITY_BLINK_BIT(SIMULATION ? 5 : 21)

                               , .PWM_BITS(7)


                               , .ACTIVITY_TIMEOUT(SIMULATION ? 2048 : 9375000)
                               , .ACTIVITY_TIMEOUT_BITS(24)
                               )
spio_status_led_generator_hss_i( .CLK_IN               (led_clk_i)
                               , .RESET_IN             (led_reset_i)
                               , .ERROR_IN             ({1'b0,                  version_mismatch_i})
                               , .CONNECTED_IN         ({!uart_synchronising_i, handshake_complete_i})
                               , .ACTIVITY_IN          ({uart_activity_i,       hss_activity_i})
                               , .LED_OUT              (leds_i[3:2])
                               , .ANIMATION_REPEAT_OUT ()
                               );


assign leds_i[5:4] = 2'b00;



assign hss_activity_i = (hss_pkt_rxvld_i[0] & hss_pkt_rxrdy_i[0])
                      | (hss_pkt_rxvld_i[1] & hss_pkt_rxrdy_i[1])
                      | (hss_pkt_rxvld_i[2] & hss_pkt_rxrdy_i[2])
                      | (hss_pkt_rxvld_i[3] & hss_pkt_rxrdy_i[3])
                      | (hss_pkt_rxvld_i[4] & hss_pkt_rxrdy_i[4])
                      | (hss_pkt_rxvld_i[5] & hss_pkt_rxrdy_i[5])
                      | (hss_pkt_rxvld_i[6] & hss_pkt_rxrdy_i[6])
                      | (hss_pkt_rxvld_i[7] & hss_pkt_rxrdy_i[7])
                      | (hss_pkt_txvld_i[0] & hss_pkt_txrdy_i[0])
                      | (hss_pkt_txvld_i[1] & hss_pkt_txrdy_i[1])
                      | (hss_pkt_txvld_i[2] & hss_pkt_txrdy_i[2])
                      | (hss_pkt_txvld_i[3] & hss_pkt_txrdy_i[3])
                      | (hss_pkt_txvld_i[4] & hss_pkt_txrdy_i[4])
                      | (hss_pkt_txvld_i[5] & hss_pkt_txrdy_i[5])
                      | (hss_pkt_txvld_i[6] & hss_pkt_txrdy_i[6])
                      | (hss_pkt_txvld_i[7] & hss_pkt_txrdy_i[7])
                      ;



assign uart_activity_i = (uart_pkt_rxvld_i & uart_pkt_rxrdy_i)
                       | (uart_pkt_txvld_i & uart_pkt_txrdy_i)
                       ;







IBUFDS refclk_ibufds_i ( .O (gtpclkin_i)
                       , .I (REFCLK_PAD_P_IN)
                       , .IB(REFCLK_PAD_N_IN)
                       );


BUFIO2 # (.DIVIDE (1), .DIVIDE_BYPASS ("TRUE"))
gtpclkout_0_pll_bufio2_i ( .I            (unbuffered_gtpclkout_i[0])
                         , .DIVCLK       (gtpclkout_i)
                         , .IOCLK        ()
                         , .SERDESSTROBE ()
                         );



wire clk_150_i;
wire clk_75_i;
wire clk_37_5_i;
clock_scaler
clock_scaler_i ( .CLK_IN1  (gtpclkout_i)
               , .CLK_OUT1 (clk_150_i)
               , .CLK_OUT2 (clk_75_i)
               , .CLK_OUT3 (clk_37_5_i)
               , .RESET    (clk_reset_i)
               , .LOCKED   (usrclks_stable_i)
               );

assign usrclk_i   = clk_150_i;
assign usrclk2_i  = clk_37_5_i;

assign uart_clk_i = clk_75_i;

assign led_clk_i  = clk_37_5_i;










gtp_x0_y0  #( .WRAPPER_SIM_GTPRESET_SPEEDUP (SIMULATION_GTPRESET_SPEEDUP)
            , .WRAPPER_SIMULATION           (SIMULATION)
            )
gtp_x0_y0_i (

                .TILE0_LOOPBACK0_IN         (3'b000)
            ,   .TILE0_LOOPBACK1_IN         (GTP_LOOPBACK)

            ,   .TILE0_CLK00_IN             (gtpclkin_i)
            ,   .TILE0_CLK01_IN             (1'b0)
            ,   .TILE0_GTPRESET0_IN         (gtp_reset_i)
            ,   .TILE0_GTPRESET1_IN         (gtp_reset_i)
            ,   .TILE0_PLLLKDET0_OUT        (plllkdet_i)
            ,   .TILE0_RESETDONE0_OUT       ()
            ,   .TILE0_RESETDONE1_OUT       (gtpresetdone_i)

            ,   .TILE0_RXCHARISCOMMA0_OUT   ()
            ,   .TILE0_RXCHARISCOMMA1_OUT   (rxchariscomma_i)
            ,   .TILE0_RXCHARISK0_OUT       ()
            ,   .TILE0_RXCHARISK1_OUT       (rxcharisk_i)
            ,   .TILE0_RXDISPERR0_OUT       ()
            ,   .TILE0_RXDISPERR1_OUT       ()
            ,   .TILE0_RXNOTINTABLE0_OUT    ()
            ,   .TILE0_RXNOTINTABLE1_OUT    ()

            ,   .TILE0_RXCLKCORCNT0_OUT     ()
            ,   .TILE0_RXCLKCORCNT1_OUT     ()

            ,   .TILE0_RXENMCOMMAALIGN0_IN  (1'b1)
            ,   .TILE0_RXENMCOMMAALIGN1_IN  (1'b1)
            ,   .TILE0_RXENPCOMMAALIGN0_IN  (1'b1)
            ,   .TILE0_RXENPCOMMAALIGN1_IN  (1'b1)

            ,   .TILE0_RXDATA0_OUT          ()
            ,   .TILE0_RXDATA1_OUT          (rxdata_i)
            ,   .TILE0_RXUSRCLK0_IN         (1'b0)
            ,   .TILE0_RXUSRCLK1_IN         (usrclk_i)
            ,   .TILE0_RXUSRCLK20_IN        (1'b0)
            ,   .TILE0_RXUSRCLK21_IN        (usrclk2_i)

            ,   .TILE0_RXN0_IN              (1'bX)
            ,   .TILE0_RXN1_IN              (HSS_RXN_IN)
            ,   .TILE0_RXP0_IN              (1'bX)
            ,   .TILE0_RXP1_IN              (HSS_RXP_IN)

            ,   .TILE0_RXLOSSOFSYNC0_OUT    ()
            ,   .TILE0_RXLOSSOFSYNC1_OUT    (rxlossofsync_i)

            ,   .TILE0_GTPCLKOUT0_OUT       (unbuffered_gtpclkout_i)
            ,   .TILE0_GTPCLKOUT1_OUT       ()

            ,   .TILE0_TXCHARISK0_IN        (4'bXXXX)
            ,   .TILE0_TXCHARISK1_IN        (txcharisk_i)

            ,   .TILE0_TXDATA0_IN           (32'hXXXX)
            ,   .TILE0_TXDATA1_IN           (txdata_i)
            ,   .TILE0_TXUSRCLK0_IN         (1'b0)
            ,   .TILE0_TXUSRCLK1_IN         (usrclk_i)
            ,   .TILE0_TXUSRCLK20_IN        (1'b0)
            ,   .TILE0_TXUSRCLK21_IN        (usrclk2_i)

            ,   .TILE0_TXN0_OUT             ()
            ,   .TILE0_TXN1_OUT             (HSS_TXN_OUT)
            ,   .TILE0_TXP0_OUT             ()
            ,   .TILE0_TXP1_OUT             (HSS_TXP_OUT)

            ,   .TILE0_RXCHANBONDSEQ0_OUT   ()
            ,   .TILE0_RXCHANBONDSEQ1_OUT   ()
            ,   .TILE0_RXCHANISALIGNED0_OUT ()
            ,   .TILE0_RXCHANISALIGNED1_OUT ()
            ,   .TILE0_RXCHANREALIGN0_OUT   ()
            ,   .TILE0_RXCHANREALIGN1_OUT   ()
            ,   .TILE0_RXCHBONDMASTER0_IN   (1'b0)
            ,   .TILE0_RXCHBONDMASTER1_IN   (1'b0)
            ,   .TILE0_RXCHBONDSLAVE0_IN    (1'b0)
            ,   .TILE0_RXCHBONDSLAVE1_IN    (1'b0)
            ,   .TILE0_RXENCHANSYNC0_IN     (1'b0)
            ,   .TILE0_RXENCHANSYNC1_IN     (1'b0)

            ,   .TILE0_RXEQMIX0_IN              (2'b00)
            ,   .TILE0_RXEQMIX1_IN              (RXEQMIX)
            ,   .TILE0_TXDIFFCTRL0_IN           (4'b0000)
            ,   .TILE0_TXDIFFCTRL1_IN           (TXDIFFCTRL)
            ,   .TILE0_TXPREEMPHASIS0_IN        (3'b000)
            ,   .TILE0_TXPREEMPHASIS1_IN        (TXPREEMPHASIS)
            );






spio_hss_multiplexer   #( .CLOCK_CORRECTION_INTERVAL      (CLOCK_CORRECTION_INTERVAL)
                        , .CLOCK_CORRECTION_INTERVAL_BITS (CLOCK_CORRECTION_INTERVAL_BITS)
                        , .NUM_HANDSHAKES                 (NUM_HANDSHAKES)
                        , .NUM_HANDSHAKES_BITS            (NUM_HANDSHAKES_BITS)
                        )
periph_hss_multiplexer_i( .CLK_IN                         (usrclk2_i)
                        , .RESET_IN                       (hss_reset_i)

                        , .HANDSHAKE_COMPLETE_OUT         (handshake_complete_i)
                        , .VERSION_MISMATCH_OUT           (version_mismatch_i)

                        , .RXDATA_IN                      (rxdata_i)
                        , .RXCHARISCOMMA_IN               (rxchariscomma_i)
                        , .RXCHARISK_IN                   (rxcharisk_i)
                        , .RXLOSSOFSYNC_IN                (rxlossofsync_i)
                        , .TXDATA_OUT                     (txdata_i)
                        , .TXCHARISK_OUT                  (txcharisk_i)

                        , .TX_PKT0_DATA_IN                (hss_pkt_txdata_i[0])
                        , .TX_PKT0_VLD_IN                 (hss_pkt_txvld_i[0])
                        , .TX_PKT0_RDY_OUT                (hss_pkt_txrdy_i[0])
                        , .TX_PKT1_DATA_IN                (hss_pkt_txdata_i[1])
                        , .TX_PKT1_VLD_IN                 (hss_pkt_txvld_i[1])
                        , .TX_PKT1_RDY_OUT                (hss_pkt_txrdy_i[1])
                        , .TX_PKT2_DATA_IN                (hss_pkt_txdata_i[2])
                        , .TX_PKT2_VLD_IN                 (hss_pkt_txvld_i[2])
                        , .TX_PKT2_RDY_OUT                (hss_pkt_txrdy_i[2])
                        , .TX_PKT3_DATA_IN                (hss_pkt_txdata_i[3])
                        , .TX_PKT3_VLD_IN                 (hss_pkt_txvld_i[3])
                        , .TX_PKT3_RDY_OUT                (hss_pkt_txrdy_i[3])
                        , .TX_PKT4_DATA_IN                (hss_pkt_txdata_i[4])
                        , .TX_PKT4_VLD_IN                 (hss_pkt_txvld_i[4])
                        , .TX_PKT4_RDY_OUT                (hss_pkt_txrdy_i[4])
                        , .TX_PKT5_DATA_IN                (hss_pkt_txdata_i[5])
                        , .TX_PKT5_VLD_IN                 (hss_pkt_txvld_i[5])
                        , .TX_PKT5_RDY_OUT                (hss_pkt_txrdy_i[5])
                        , .TX_PKT6_DATA_IN                (hss_pkt_txdata_i[6])
                        , .TX_PKT6_VLD_IN                 (hss_pkt_txvld_i[6])
                        , .TX_PKT6_RDY_OUT                (hss_pkt_txrdy_i[6])
                        , .TX_PKT7_DATA_IN                (hss_pkt_txdata_i[7])
                        , .TX_PKT7_VLD_IN                 (hss_pkt_txvld_i[7])
                        , .TX_PKT7_RDY_OUT                (hss_pkt_txrdy_i[7])
                        , .RX_PKT0_DATA_OUT               (hss_pkt_rxdata_i[0])
                        , .RX_PKT0_VLD_OUT                (hss_pkt_rxvld_i[0])
                        , .RX_PKT0_RDY_IN                 (hss_pkt_rxrdy_i[0])
                        , .RX_PKT1_DATA_OUT               (hss_pkt_rxdata_i[1])
                        , .RX_PKT1_VLD_OUT                (hss_pkt_rxvld_i[1])
                        , .RX_PKT1_RDY_IN                 (hss_pkt_rxrdy_i[1])
                        , .RX_PKT2_DATA_OUT               (hss_pkt_rxdata_i[2])
                        , .RX_PKT2_VLD_OUT                (hss_pkt_rxvld_i[2])
                        , .RX_PKT2_RDY_IN                 (hss_pkt_rxrdy_i[2])
                        , .RX_PKT3_DATA_OUT               (hss_pkt_rxdata_i[3])
                        , .RX_PKT3_VLD_OUT                (hss_pkt_rxvld_i[3])
                        , .RX_PKT3_RDY_IN                 (hss_pkt_rxrdy_i[3])
                        , .RX_PKT4_DATA_OUT               (hss_pkt_rxdata_i[4])
                        , .RX_PKT4_VLD_OUT                (hss_pkt_rxvld_i[4])
                        , .RX_PKT4_RDY_IN                 (hss_pkt_rxrdy_i[4])
                        , .RX_PKT5_DATA_OUT               (hss_pkt_rxdata_i[5])
                        , .RX_PKT5_VLD_OUT                (hss_pkt_rxvld_i[5])
                        , .RX_PKT5_RDY_IN                 (hss_pkt_rxrdy_i[5])
                        , .RX_PKT6_DATA_OUT               (hss_pkt_rxdata_i[6])
                        , .RX_PKT6_VLD_OUT                (hss_pkt_rxvld_i[6])
                        , .RX_PKT6_RDY_IN                 (hss_pkt_rxrdy_i[6])
                        , .RX_PKT7_DATA_OUT               (hss_pkt_rxdata_i[7])
                        , .RX_PKT7_VLD_OUT                (hss_pkt_rxvld_i[7])
                        , .RX_PKT7_RDY_IN                 (hss_pkt_rxrdy_i[7])

		                    , .REG_WRITE_IN                   (reg_write_i)
		                    , .REG_ADDR_IN                    (reg_addr_i)
		                    , .REG_READ_DATA_OUT              (reg_read_data_i)
		                    , .REG_WRITE_DATA_IN              (reg_write_data_i)
                        );







OBUF ftdi_cts_n_buf_i (.I (!uart_cts_i), .O(FTDI_CTS_N_OUT));
OBUF ftdi_dcd_n_buf_i (.I (1'b1),        .O(FTDI_DCD_N_OUT));
OBUF ftdi_dsr_n_buf_i (.I (1'b1),        .O(FTDI_DSR_N_OUT));
OBUF ftdi_ri_n_buf_i  (.I (1'b1),        .O(FTDI_RI_N_OUT));
IBUF ftdi_rts_n_buf_i (.O (),            .I(FTDI_RTS_N_IN));
IBUF ftdi_dtr_n_buf_i (.O (),            .I(FTDI_DTR_N_IN));
IBUF ftdi_txd_buf_i   (.O (uart_rx_i),   .I(FTDI_TXD_IN));
OBUF ftdi_rxd_buf_i   (.I (uart_tx_i),   .O(FTDI_RXD_OUT));



spio_uart_sync         #( .NUM_BITS      (1)
                        , .NUM_STAGES    (2)
                        , .INITIAL_VALUE (1'b1)
                        )
spio_uart_sync_tx_data_i( .CLK_IN   (uart_clk_i)
                        , .RESET_IN (reset_i)
                        , .DATA_IN  (uart_rx_i)
                        , .DATA_OUT (uart_rx_synced_i)
                        );



wire [`PKT_BITS-1:0] fast_uart_pkt_txdata_i;
wire                 fast_uart_pkt_txvld_i;
wire                 fast_uart_pkt_txrdy_i;
wire [`PKT_BITS-1:0] fast_uart_pkt_rxdata_i;
wire                 fast_uart_pkt_rxvld_i;
wire                 fast_uart_pkt_rxrdy_i;


spio_uart #( .IS_MASTER           (1'b0)
           , .BAUD_PERIOD         (75_000_000/3_000_000)
           , .BAUD_NUM_BITS       (5)
           , .RX_BUFFER_ADDR_BITS (UART_RX_BUFFER_ADDR_BITS)
           , .RX_HIGH_WATER_MARK  (UART_RX_HIGH_WATER_MARK)
           )
spio_uart_i( .CLK_IN                (uart_clk_i)
           , .RESET_IN              (reset_i)

           , .RX_IN                 (uart_rx_synced_i)
           , .CTS_IN                (1'b1)
           , .TX_OUT                (uart_tx_i)
           , .CTS_OUT               (uart_cts_i)

           , .RX_DATA_OUT           (fast_uart_pkt_rxdata_i)
           , .RX_VLD_OUT            (fast_uart_pkt_rxvld_i)
           , .RX_RDY_IN             (fast_uart_pkt_rxrdy_i)
           , .RX_PACKET_DROPPED_OUT ()
           , .TX_DATA_IN            (fast_uart_pkt_txdata_i)
           , .TX_VLD_IN             (fast_uart_pkt_txvld_i)
           , .TX_RDY_OUT            (fast_uart_pkt_txrdy_i)
           , .TX_PACKET_DROPPED_OUT ()

           , .SYNC_TRIGGER_IN       (1'b0)
           , .SYNCHRONISING_OUT     (uart_synchronising_i)
           );


spio_link_speed_halver #( .PKT_BITS(`PKT_BITS))
spio_link_speed_halver_i( .RESET_IN(reset_i)
                        , .SCLK_IN(usrclk2_i)
                        , .FCLK_IN(uart_clk_i)

                        , .DATA_IN(fast_uart_pkt_rxdata_i)
                        , .VLD_IN( fast_uart_pkt_rxvld_i)
                        , .RDY_OUT(fast_uart_pkt_rxrdy_i)

                        , .DATA_OUT(uart_pkt_rxdata_i)
                        , .VLD_OUT( uart_pkt_rxvld_i)
                        , .RDY_IN(  uart_pkt_rxrdy_i)
                        );
spio_link_speed_doubler #( .PKT_BITS(`PKT_BITS))
spio_link_speed_doubler_i( .RESET_IN(reset_i)
                         , .SCLK_IN(usrclk2_i)
                         , .FCLK_IN(uart_clk_i)

                         , .DATA_IN(uart_pkt_txdata_i)
                         , .VLD_IN( uart_pkt_txvld_i)
                         , .RDY_OUT(uart_pkt_txrdy_i)

                         , .DATA_OUT(fast_uart_pkt_txdata_i)
                         , .VLD_OUT( fast_uart_pkt_txvld_i)
                         , .RDY_IN(  fast_uart_pkt_txrdy_i)
                         );







assign hss_pkt_txdata_i[0] = uart_pkt_rxdata_i;
assign hss_pkt_txvld_i[0]  = uart_pkt_rxvld_i;
assign uart_pkt_rxrdy_i    = hss_pkt_txrdy_i[0];


assign hss_pkt_txdata_i[1] = { 32'hF0A0F030
                             , 32'h0000AAAA
                             , 2'b00
                             , 2'b00
                             , 2'b00
                             , 1'b1
                             , 1'b0
                             };


assign hss_pkt_txvld_i[1]  = button_sync_i[1];


generate for (i = 2; i < `NUM_CHANS; i = i + 1)
	begin : spinnaker_inactive_tx_links
		assign hss_pkt_txdata_i[i] = {`PKT_BITS{1'bX}};
		assign hss_pkt_txvld_i[i]  = 1'b0;
	end
endgenerate







assign uart_pkt_txdata_i  = hss_pkt_rxdata_i[0];
assign uart_pkt_txvld_i   = hss_pkt_rxvld_i[0];
assign hss_pkt_rxrdy_i[0] = uart_pkt_rxrdy_i;


generate for (i = 1; i < `NUM_CHANS; i = i + 1)
	begin : spinnaker_inactive_rx_links
		assign hss_pkt_rxrdy_i[i] = 1'b1;
	end
endgenerate








generate if (DEBUG_CHIPSCOPE_VIO)
	begin : chipscope_enabled
		
		wire [35:0] chipscope_control_i;
		
		wire [63:0]                        chipscope_sync_in_i;
		wire [1+`REGA_BITS+`REGD_BITS-1:0] chipscope_sync_out_i;
		

		chipscope_icon chipscope_icon_i (.CONTROL0 (chipscope_control_i));
		

		chipscope_vio chipscope_vio_i ( .CONTROL (chipscope_control_i)
		                              , .CLK     (usrclk2_i)
		                              , .SYNC_IN (chipscope_sync_in_i)
		                              , .SYNC_OUT(chipscope_sync_out_i)
		                              );
		

		assign reg_write_i                        = chipscope_sync_out_i[0];
		assign reg_addr_i                         = chipscope_sync_out_i[1+:`REGA_BITS];
		assign reg_write_data_i                   = chipscope_sync_out_i[1+`REGA_BITS+:`REGD_BITS];
		assign chipscope_sync_in_i[0+:`REGD_BITS] = reg_read_data_i;
		

		assign chipscope_sync_in_i[`REGD_BITS+0 +:8] = { hss_pkt_rxrdy_i[7]
		                                               , hss_pkt_rxrdy_i[6]
		                                               , hss_pkt_rxrdy_i[5]
		                                               , hss_pkt_rxrdy_i[4]
		                                               , hss_pkt_rxrdy_i[3]
		                                               , hss_pkt_rxrdy_i[2]
		                                               , hss_pkt_rxrdy_i[1]
		                                               , hss_pkt_rxrdy_i[0]
		                                               };
		assign chipscope_sync_in_i[`REGD_BITS+8 +:8] = { hss_pkt_rxvld_i[7]
		                                               , hss_pkt_rxvld_i[6]
		                                               , hss_pkt_rxvld_i[5]
		                                               , hss_pkt_rxvld_i[4]
		                                               , hss_pkt_rxvld_i[3]
		                                               , hss_pkt_rxvld_i[2]
		                                               , hss_pkt_rxvld_i[1]
		                                               , hss_pkt_rxvld_i[0]
		                                               };

		assign chipscope_sync_in_i[`REGD_BITS+16+:8] = { hss_pkt_txrdy_i[7]
		                                               , hss_pkt_txrdy_i[6]
		                                               , hss_pkt_txrdy_i[5]
		                                               , hss_pkt_txrdy_i[4]
		                                               , hss_pkt_txrdy_i[3]
		                                               , hss_pkt_txrdy_i[2]
		                                               , hss_pkt_txrdy_i[1]
		                                               , hss_pkt_txrdy_i[0]
		                                               };
		assign chipscope_sync_in_i[`REGD_BITS+24+:8] = { hss_pkt_txvld_i[7]
		                                               , hss_pkt_txvld_i[6]
		                                               , hss_pkt_txvld_i[5]
		                                               , hss_pkt_txvld_i[4]
		                                               , hss_pkt_txvld_i[3]
		                                               , hss_pkt_txvld_i[2]
		                                               , hss_pkt_txvld_i[1]
		                                               , hss_pkt_txvld_i[0]
		                                               };
		
		
	end
else
	begin : chipscope_disabled
		

		assign reg_write_i      = 1'b0;
		assign reg_addr_i       = `VERS_REG;
		assign reg_write_data_i = {`REGD_BITS{1'bX}};
		
	end
endgenerate


endmodule