data/full_repos/permissive/158845296/mux2.v
data/verilator_xmls/58ff87fe-4814-4ad3-bef4-64e0e5ffc7f0.xml
module mux2 #(parameter WIDTH = 32)
(
    input  sel,
    input  [(WIDTH-1):0] in0, in1,
    output [(WIDTH-1):0] out
);

    assign out = (sel) ? in1 : in0;

endmodule
module mux2 #(parameter WIDTH = 32)
(
    input  sel,
    input  [(WIDTH-1):0] in0, in1,
    output [(WIDTH-1):0] out
);


    assign out = (sel) ? in1 : in0;

endmodule