data/full_repos/permissive/141038711/tb/apb_regs_test.v
 line:51: before: "#"
1: b'%Error: data/full_repos/permissive/141038711/tb/apb_regs_test.v:50: syntax error, unexpected \'@\'\n      @(posedge pclk)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_regs_test.v:53: Unsupported: Ignoring delay on this delayed statement.\n       #(CLK_PERIOD*5) ; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_regs_test.v:71: Unsupported: Ignoring delay on this delayed statement.\n   #500 $stop;       \n   ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module apb_regs_test;

localparam CLK_PERIOD=100;




reg          reset_n;
reg          enable;


wire         pclk;
wire [ 15:0] paddr;
wire         pwrite;
wire         psel;
wire         penable;
wire [ 31:0] pwdata;
wire [ 31:0] prdata;
wire         pready;
wire         pslverr;


reg  [ 31:0] status32;
reg  [ 15:0] status16;
reg  [  7:0] status8;
wire [ 31:0] control32;
wire [ 15:0] control16;
wire [  7:0] control8;


   initial
   begin


      reset_n    = 1'b0;
      enable     = 1'b1;


      status32   = 32'h9c4e9a31;
      status16   = 16'h7832;
      status8    = 16'h2a;
      
      @(posedge pclk)
         #(CLK_PERIOD*5) ; 
      reset_n = 1'b1;
       #(CLK_PERIOD*5) ; 
       apb_bus0.read(16'h00,32'h9c4e9a31);
       apb_bus0.read(16'h04,32'h7832);
       apb_bus0.read(16'h08,32'h2a);
       apb_bus0.read(16'h14,32'h1234);
       
       apb_bus0.write(16'h10,32'h11223344);
       apb_bus0.write(16'h14,32'hAABB);
       apb_bus0.write(16'h18,32'hDD);
       apb_bus0.read(16'h10,32'h11223344);
       apb_bus0.read(16'h14,32'hxxxxAABB);
       apb_bus0.read(16'h18,32'hxxxxxxDD);
       apb_bus0.read(16'h1C,32'h00216948);
       apb_bus0.delay(3);
       if (apb_bus0.errors==0)
          $display("apb_regs test passed");
       else
          $display("apb_regs test FAILED!");
		 #500 $stop;       
   end


apb_regs
apb_regs_0 (


      .reset_n  (reset_n),
      .enable   (enable),


      .pclk     (pclk),
      .paddr    (paddr[4:0]),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr),


      .status32 (status32),
      .status16 (status16),
      .status8  (status8),
      .control32(control32),
      .control16(control16),
      .control8 (control8) 
   );
   
apb_bus 
#(.CLKPER(CLK_PERIOD)
 )
apb_bus0 (

      .pclk     (pclk),
      .paddr    (paddr),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr)
      ); 
   


endmodule
module apb_regs_test;


localparam CLK_PERIOD=100;




reg          reset_n;
reg          enable;


wire         pclk;
wire [ 15:0] paddr;
wire         pwrite;
wire         psel;
wire         penable;
wire [ 31:0] pwdata;
wire [ 31:0] prdata;
wire         pready;
wire         pslverr;


reg  [ 31:0] status32;
reg  [ 15:0] status16;
reg  [  7:0] status8;
wire [ 31:0] control32;
wire [ 15:0] control16;
wire [  7:0] control8;


   initial
   begin


      reset_n    = 1'b0;
      enable     = 1'b1;


      status32   = 32'h9c4e9a31;
      status16   = 16'h7832;
      status8    = 16'h2a;
      
      @(posedge pclk)
         #(CLK_PERIOD*5) ; 
      reset_n = 1'b1;
       #(CLK_PERIOD*5) ; 
       apb_bus0.read(16'h00,32'h9c4e9a31);
       apb_bus0.read(16'h04,32'h7832);
       apb_bus0.read(16'h08,32'h2a);
       apb_bus0.read(16'h14,32'h1234);
       
       apb_bus0.write(16'h10,32'h11223344);
       apb_bus0.write(16'h14,32'hAABB);
       apb_bus0.write(16'h18,32'hDD);
       apb_bus0.read(16'h10,32'h11223344);
       apb_bus0.read(16'h14,32'hxxxxAABB);
       apb_bus0.read(16'h18,32'hxxxxxxDD);
       apb_bus0.read(16'h1C,32'h00216948);
       apb_bus0.delay(3);
       if (apb_bus0.errors==0)
          $display("apb_regs test passed");
       else
          $display("apb_regs test FAILED!");
		 #500 $stop;       
   end


apb_regs
apb_regs_0 (


      .reset_n  (reset_n),
      .enable   (enable),


      .pclk     (pclk),
      .paddr    (paddr[4:0]),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr),


      .status32 (status32),
      .status16 (status16),
      .status8  (status8),
      .control32(control32),
      .control16(control16),
      .control8 (control8) 
   );
   
apb_bus 
#(.CLKPER(CLK_PERIOD)
 )
apb_bus0 (

      .pclk     (pclk),
      .paddr    (paddr),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr)
      ); 
   


endmodule