data/full_repos/permissive/107757225/audio/sram_reading_fsm.sv
 line:24: before: "logic"
1: b'%Warning-WIDTH: data/full_repos/permissive/107757225/audio/sram_reading_fsm.sv:21: Output port connection \'dout\' expects 16 bits on the pin connection, but pin connection\'s REPLICATE generates 20 bits.\n                                                                                 : ... In instance sram_reading_fsm\n .load (sram_reg_load), .dout({4\'b0, SRAM_ADDR[15:0]})\n                         ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sram_reading_fsm (
	input Clk,
	input reset,
	input start, cont,

	output logic SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_OE_N, SRAM_WE_N,
	output logic [19:0] SRAM_ADDR,
	output logic sram_data_load
	
);




logic sram_reg_load;

counter_reg sram_reg(
	.clk(Clk), .reset(reset),
	.load (sram_reg_load), .dout({4'b0, SRAM_ADDR[15:0]})
);

enum logic [2:0] {
	halted, 
	reading_sample_1,
	reading_sample_2,
	reading_sample_3,
	done
}   state, next_state;


always_ff @ (posedge Clk)
begin
    if (reset) 
        state <= halted;
    else 
        state <= next_state;
end

always_comb
begin 
    next_state = state;
 
    unique case (state)
        halted : 
            if (cont)
                next_state = reading_sample_1;                      
        reading_sample_1:
	        	next_state = reading_sample_2;
        reading_sample_2:
	        	next_state = reading_sample_3;
        reading_sample_3:
        	if(~cont)
	        	next_state = done;
        done:
        	next_state = halted;
        default : ;
	endcase


	SRAM_OE_N = 1'b1;
	SRAM_WE_N = 1'b1;
	sram_reg_load = 1'b0;
	sram_data_load = 1'b0;


    SRAM_CE_N = 1'b0;
    SRAM_UB_N = 1'b0;
 	SRAM_LB_N = 1'b0;


	case (state)

		reading_sample_1:
		begin
			SRAM_OE_N = 1'b0;
		end
		reading_sample_2:
		begin
			SRAM_OE_N = 1'b0;
		end
		reading_sample_3:
		begin
			SRAM_OE_N = 1'b0;
	        sram_data_load = 1'b1;
		end
		done:
			sram_reg_load = 1'b1;
		default: ;
	endcase

end
endmodule
module sram_reading_fsm (
	input Clk,
	input reset,
	input start, cont,

	output logic SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_OE_N, SRAM_WE_N,
	output logic [19:0] SRAM_ADDR,
	output logic sram_data_load
	
);





logic sram_reg_load;

counter_reg sram_reg(
	.clk(Clk), .reset(reset),
	.load (sram_reg_load), .dout({4'b0, SRAM_ADDR[15:0]})
);

enum logic [2:0] {
	halted, 
	reading_sample_1,
	reading_sample_2,
	reading_sample_3,
	done
}   state, next_state;


always_ff @ (posedge Clk)
begin
    if (reset) 
        state <= halted;
    else 
        state <= next_state;
end

always_comb
begin 
    next_state = state;
 
    unique case (state)
        halted : 
            if (cont)
                next_state = reading_sample_1;                      
        reading_sample_1:
	        	next_state = reading_sample_2;
        reading_sample_2:
	        	next_state = reading_sample_3;
        reading_sample_3:
        	if(~cont)
	        	next_state = done;
        done:
        	next_state = halted;
        default : ;
	endcase


	SRAM_OE_N = 1'b1;
	SRAM_WE_N = 1'b1;
	sram_reg_load = 1'b0;
	sram_data_load = 1'b0;


    SRAM_CE_N = 1'b0;
    SRAM_UB_N = 1'b0;
 	SRAM_LB_N = 1'b0;


	case (state)

		reading_sample_1:
		begin
			SRAM_OE_N = 1'b0;
		end
		reading_sample_2:
		begin
			SRAM_OE_N = 1'b0;
		end
		reading_sample_3:
		begin
			SRAM_OE_N = 1'b0;
	        sram_data_load = 1'b1;
		end
		done:
			sram_reg_load = 1'b1;
		default: ;
	endcase

end
endmodule