data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v
 line:70: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\nalways #15 rclk <= ~rclk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\nalways #5 wclk <= ~wclk;\n       ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v:22: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v:23: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #200\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #600\n ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module afifo16_tb;

reg	rclk		= 1;
reg	wclk		= 1;

reg	reset		= 0;
reg	read		= 0;
reg	write		= 0;

reg	[17:0]	wr_data	= 0;
wire	[17:0]	rd_data;

wire	full;
wire	empty;

always	#15	rclk	<= ~rclk;
always	#5	wclk	<= ~wclk;


initial begin : Sim
	$dumpfile ("tb.vcd");
	$dumpvars;
	
	#2
	reset	<= 1;
	
	#30
	reset	<= 0;
	
	#30
	read	<= 0;
	write	<= 0;
	
	#10
	write	<= 1;


	#200
	read	<= 1;
	
	#30
	write	<= 0;
	
	#600
	$finish;
end



always @(posedge wclk)
	wr_data	<= #5 $random;



afifo16 #('d18) FIFO0 (
	.reset_ni	(~reset),
	
	.rd_clk_i	(rclk),
	.rd_en_i	(read),
	.rd_data_o	(rd_data),
	
	.wr_clk_i	(wclk),
	.wr_en_i	(write),
	.wr_data_i	(wr_data),
	
	.wfull_o	(full),
	.rempty_o	(empty)
);


endmodule
module afifo16_tb;


reg	rclk		= 1;
reg	wclk		= 1;

reg	reset		= 0;
reg	read		= 0;
reg	write		= 0;

reg	[17:0]	wr_data	= 0;
wire	[17:0]	rd_data;

wire	full;
wire	empty;

always	#15	rclk	<= ~rclk;
always	#5	wclk	<= ~wclk;


initial begin : Sim
	$dumpfile ("tb.vcd");
	$dumpvars;
	
	#2
	reset	<= 1;
	
	#30
	reset	<= 0;
	
	#30
	read	<= 0;
	write	<= 0;
	
	#10
	write	<= 1;


	#200
	read	<= 1;
	
	#30
	write	<= 0;
	
	#600
	$finish;
end



always @(posedge wclk)
	wr_data	<= #5 $random;



afifo16 #('d18) FIFO0 (
	.reset_ni	(~reset),
	
	.rd_clk_i	(rclk),
	.rd_en_i	(read),
	.rd_data_o	(rd_data),
	
	.wr_clk_i	(wclk),
	.wr_en_i	(write),
	.wr_data_i	(wr_data),
	
	.wfull_o	(full),
	.rempty_o	(empty)
);


endmodule