data/full_repos/permissive/218779832/junk/register1.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/218779832/junk/register1.v:29: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance register1\nregmemory[3\'b000] <= 1\'b0;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/register1.v:30: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance register1\nregmemory[3\'b001] <= 1\'b0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/register1.v:31: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance register1\nregmemory[3\'b010] <= 1\'b0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/register1.v:32: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance register1\nregmemory[3\'b011] <= 1\'b0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/register1.v:33: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance register1\nregmemory[3\'b100] <= 1\'b0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/register1.v:34: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance register1\nregmemory[3\'b101] <= 1\'b0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/register1.v:35: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance register1\nregmemory[3\'b110] <= 1\'b0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/register1.v:36: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance register1\nregmemory[3\'b111] <= 1\'b0;\n                  ^~\n%Error: Exiting due to 8 warning(s)\n'
module register1 
(
    input clk,
    input [7:0] OR2,
    input [7:0] ALU_IN,
    input [1:0] mux_sel,

    input [1:0] enab,
    input [2:0] seg ,
    output [7:0] dataout_A,
    output [7:0] dataout_B

); 

reg [7:0] regmemory [7:0] ;


reg [7:0] dataout_A1 ;
reg [7:0] dataout_B1 ;



always @ *
begin 


if (enab == 2'b00)
begin 
regmemory[3'b000] <= 1'b0;
regmemory[3'b001] <= 1'b0;
regmemory[3'b010] <= 1'b0;
regmemory[3'b011] <= 1'b0;
regmemory[3'b100] <= 1'b0;
regmemory[3'b101] <= 1'b0;
regmemory[3'b110] <= 1'b0;
regmemory[3'b111] <= 1'b0;
end


else if (enab == 2'b01)
begin

if (mux_sel == 2'b00)
begin
regmemory[seg] = regmemory[3'b000];
end

else if (mux_sel == 2'b01)

begin 
regmemory[3'b000] = regmemory[seg];
end

else if (mux_sel == 2'b10)
begin
regmemory[seg] = OR2;
end

else if (mux_sel == 2'b11)
begin
regmemory[seg] = ALU_IN;
end
end

else if (enab == 2'b11)
begin
dataout_A1 = regmemory[3'b000];
dataout_B1 = regmemory[seg]; 
end

end

assign dataout_A = dataout_A1 ;
assign dataout_B = dataout_B1 ;

endmodule
module register1 
(
    input clk,
    input [7:0] OR2,
    input [7:0] ALU_IN,
    input [1:0] mux_sel,

    input [1:0] enab,
    input [2:0] seg ,
    output [7:0] dataout_A,
    output [7:0] dataout_B

);
 

reg [7:0] regmemory [7:0] ;


reg [7:0] dataout_A1 ;
reg [7:0] dataout_B1 ;



always @ *
begin 


if (enab == 2'b00)
begin 
regmemory[3'b000] <= 1'b0;
regmemory[3'b001] <= 1'b0;
regmemory[3'b010] <= 1'b0;
regmemory[3'b011] <= 1'b0;
regmemory[3'b100] <= 1'b0;
regmemory[3'b101] <= 1'b0;
regmemory[3'b110] <= 1'b0;
regmemory[3'b111] <= 1'b0;
end


else if (enab == 2'b01)
begin

if (mux_sel == 2'b00)
begin
regmemory[seg] = regmemory[3'b000];
end

else if (mux_sel == 2'b01)

begin 
regmemory[3'b000] = regmemory[seg];
end

else if (mux_sel == 2'b10)
begin
regmemory[seg] = OR2;
end

else if (mux_sel == 2'b11)
begin
regmemory[seg] = ALU_IN;
end
end

else if (enab == 2'b11)
begin
dataout_A1 = regmemory[3'b000];
dataout_B1 = regmemory[seg]; 
end

end

assign dataout_A = dataout_A1 ;
assign dataout_B = dataout_B1 ;

endmodule