data/full_repos/permissive/174783592/WallacePL/Adder/sum16bitPL.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/174783592/WallacePL/Adder/sum16bitPL.sv:1: Cannot find include file: Adder/kpgGen.v\n `include "Adder/kpgGen.v" \n          ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174783592/WallacePL/Adder,data/full_repos/permissive/174783592/Adder/kpgGen.v\n             data/full_repos/permissive/174783592/WallacePL/Adder,data/full_repos/permissive/174783592/Adder/kpgGen.v.v\n             data/full_repos/permissive/174783592/WallacePL/Adder,data/full_repos/permissive/174783592/Adder/kpgGen.v.sv\n             Adder/kpgGen.v\n             Adder/kpgGen.v.v\n             Adder/kpgGen.v.sv\n             obj_dir/Adder/kpgGen.v\n             obj_dir/Adder/kpgGen.v.v\n             obj_dir/Adder/kpgGen.v.sv\n%Error: data/full_repos/permissive/174783592/WallacePL/Adder/sum16bitPL.sv:2: Cannot find include file: Adder/kpgCmp.v\n `include "Adder/kpgCmp.v" \n          ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module sum16bitPL(a,b,kIn,sum,clk);

    input clk;
	input [15:0] a;
	input [15:0] b;
	input [1:0] kIn;
    integer k;
	wire [16:0] sumwire;
	output reg [16:0]sum;

	wire [1:0] kpgIn [16:0];
	wire [1:0] wl1 [16:0];
	reg  [1:0] ppl1 [16:0];
	wire [1:0] wl2 [16:0];
	reg  [1:0] ppl2 [16:0];
	wire [1:0] wl3 [16:0];
	reg  [1:0] ppl3 [16:0];
	wire [1:0] wl4 [16:0];
	reg  [1:0] ppl4 [16:0];

	reg [1:0] kpgOut[22:0];

	wire [16:0] temp;
	assign kpgIn [0] = kIn;	
	generate
		genvar i;


		for(i =0;i<16; i = i + 1)
		begin
			kpgGen gen(a[i],b[i],kpgIn[i+1]);
		end

		for(i=0;i<16;i = i +1)
		begin
			kpgCmp cmp(kpgIn[i+1],kpgIn[i],wl1[i+1]);
		end

		for(i=0;i<15;i = i +1)
		begin
			kpgCmp cmp(ppl1[i+2],ppl1[i],wl2[i+2]);
		end

		
		for(i=0;i<13;i = i +1)
		begin
			kpgCmp cmp(ppl2[i+4],ppl2[i],wl3[i+4]);
		end
	

		
		for(i=0;i<9;i = i +1)
		begin
			kpgCmp cmp(ppl3[i+8],ppl3[i],wl4[i+8]);
		end

	endgenerate

    assign wl1[0] = kpgIn[0];
    assign wl2[0] = ppl1[0];
	assign wl2[1] = ppl1[1];
    assign wl3[0] = ppl2[0];
	assign wl3[1] = ppl2[1];
	assign wl3[2] = ppl2[2];
	assign wl3[3] = ppl2[3];


	generate
		for(i=0 ;i<8;i= i+1)
		begin
		assign wl4[i] = ppl3[i];
		end
		endgenerate








	





	
	



















	always @(clk)
		begin
			for(k=0;k<=16;k = k +1)
			begin
			ppl1[k]<=wl1[k];
			ppl2[k]<=wl2[k];
			ppl3[k]<=wl3[k];
			kpgOut[k]<=wl4[k];
			
			end

			sum <= sumwire;
		end

    

	generate 
    genvar j;
    
	for(j=0;j<16;j=j+1)
		begin
			assign temp[j] = kpgOut[j][0]|kpgOut[j][1];
			assign sumwire[j]  = a[j]^b[j]^temp[j];
		end
	

	 assign sumwire[16] = kpgOut[16][0] | kpgOut[16][1];

    endgenerate





	endmodule
module sum16bitPL(a,b,kIn,sum,clk);


    input clk;
	input [15:0] a;
	input [15:0] b;
	input [1:0] kIn;
    integer k;
	wire [16:0] sumwire;
	output reg [16:0]sum;

	wire [1:0] kpgIn [16:0];
	wire [1:0] wl1 [16:0];
	reg  [1:0] ppl1 [16:0];
	wire [1:0] wl2 [16:0];
	reg  [1:0] ppl2 [16:0];
	wire [1:0] wl3 [16:0];
	reg  [1:0] ppl3 [16:0];
	wire [1:0] wl4 [16:0];
	reg  [1:0] ppl4 [16:0];

	reg [1:0] kpgOut[22:0];

	wire [16:0] temp;
	assign kpgIn [0] = kIn;	
	generate
		genvar i;


		for(i =0;i<16; i = i + 1)
		begin
			kpgGen gen(a[i],b[i],kpgIn[i+1]);
		end

		for(i=0;i<16;i = i +1)
		begin
			kpgCmp cmp(kpgIn[i+1],kpgIn[i],wl1[i+1]);
		end

		for(i=0;i<15;i = i +1)
		begin
			kpgCmp cmp(ppl1[i+2],ppl1[i],wl2[i+2]);
		end

		
		for(i=0;i<13;i = i +1)
		begin
			kpgCmp cmp(ppl2[i+4],ppl2[i],wl3[i+4]);
		end
	

		
		for(i=0;i<9;i = i +1)
		begin
			kpgCmp cmp(ppl3[i+8],ppl3[i],wl4[i+8]);
		end

	endgenerate

    assign wl1[0] = kpgIn[0];
    assign wl2[0] = ppl1[0];
	assign wl2[1] = ppl1[1];
    assign wl3[0] = ppl2[0];
	assign wl3[1] = ppl2[1];
	assign wl3[2] = ppl2[2];
	assign wl3[3] = ppl2[3];


	generate
		for(i=0 ;i<8;i= i+1)
		begin
		assign wl4[i] = ppl3[i];
		end
		endgenerate








	





	
	



















	always @(clk)
		begin
			for(k=0;k<=16;k = k +1)
			begin
			ppl1[k]<=wl1[k];
			ppl2[k]<=wl2[k];
			ppl3[k]<=wl3[k];
			kpgOut[k]<=wl4[k];
			
			end

			sum <= sumwire;
		end

    

	generate 
    genvar j;
    
	for(j=0;j<16;j=j+1)
		begin
			assign temp[j] = kpgOut[j][0]|kpgOut[j][1];
			assign sumwire[j]  = a[j]^b[j]^temp[j];
		end
	

	 assign sumwire[16] = kpgOut[16][0] | kpgOut[16][1];

    endgenerate





	endmodule