data/full_repos/permissive/129155059/proyecto-01/p2s/ffd_p2s_synth.v
1: b"%Error: data/full_repos/permissive/129155059/proyecto-01/p2s/ffd_p2s_synth.v:16: Cannot find file containing module: 'NOT'\n  NOT _05_ (\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/p2s,data/full_repos/permissive/129155059/NOT\n             data/full_repos/permissive/129155059/proyecto-01/p2s,data/full_repos/permissive/129155059/NOT.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s,data/full_repos/permissive/129155059/NOT.sv\n             NOT\n             NOT.v\n             NOT.sv\n             obj_dir/NOT\n             obj_dir/NOT.v\n             obj_dir/NOT.sv\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s/ffd_p2s_synth.v:20: Cannot find file containing module: 'NOR'\n  NOR _06_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s/ffd_p2s_synth.v:25: Cannot find file containing module: 'NAND'\n  NAND _07_ (\n  ^~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s/ffd_p2s_synth.v:30: Cannot find file containing module: 'NAND'\n  NAND _08_ (\n  ^~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s/ffd_p2s_synth.v:35: Cannot find file containing module: 'NOR'\n  NOR _09_ (\n  ^~~\n%Error: Exiting due to 5 error(s)\n"
module ffd_p2s_synth(CLK, D, ENB, valid_in, Q, valid_out);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  input CLK;
  input D;
  input ENB;
  output Q;
  reg Q;
  input valid_in;
  output valid_out;
  NOT _05_ (
    .A(D),
    .Y(_01_)
  );
  NOR _06_ (
    .A(Q),
    .B(valid_in),
    .Y(_02_)
  );
  NAND _07_ (
    .A(_01_),
    .B(valid_in),
    .Y(_03_)
  );
  NAND _08_ (
    .A(ENB),
    .B(_03_),
    .Y(_04_)
  );
  NOR _09_ (
    .A(_02_),
    .B(_04_),
    .Y(_00_)
  );
  always @(posedge CLK)
      Q <= _00_;
  assign valid_out = 1'h1;
endmodule
module ffd_p2s_synth(CLK, D, ENB, valid_in, Q, valid_out);

  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  input CLK;
  input D;
  input ENB;
  output Q;
  reg Q;
  input valid_in;
  output valid_out;
  NOT _05_ (
    .A(D),
    .Y(_01_)
  );
  NOR _06_ (
    .A(Q),
    .B(valid_in),
    .Y(_02_)
  );
  NAND _07_ (
    .A(_01_),
    .B(valid_in),
    .Y(_03_)
  );
  NAND _08_ (
    .A(ENB),
    .B(_03_),
    .Y(_04_)
  );
  NOR _09_ (
    .A(_02_),
    .B(_04_),
    .Y(_00_)
  );
  always @(posedge CLK)
      Q <= _00_;
  assign valid_out = 1'h1;
endmodule