data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new/P_to_BCD_tb.v
1: b'%Error: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new/P_to_BCD_tb.v:30: Cannot find file containing module: \'P_2_BCD\'\nP_2_BCD DUT (.P(in_P_tb[7:0]), .ones(BCD0_tb[3:0]),.tens(BCD1_tb[3:0]),.hundreds(BCD2_tb[3:0]));\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new,data/full_repos/permissive/124604849/P_2_BCD\n             data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new,data/full_repos/permissive/124604849/P_2_BCD.v\n             data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new,data/full_repos/permissive/124604849/P_2_BCD.sv\n             P_2_BCD\n             P_2_BCD.v\n             P_2_BCD.sv\n             obj_dir/P_2_BCD\n             obj_dir/P_2_BCD.v\n             obj_dir/P_2_BCD.sv\n%Warning-WIDTH: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new/P_to_BCD_tb.v:37: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                                         : ... In instance P_to_BCD_tb\n        in_P_tb = i;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module P_to_BCD_tb;

reg  [7:0] in_P_tb;                     
wire  [3:0] BCD0_tb;                    
wire  [3:0] BCD1_tb;
wire  [3:0] BCD2_tb;

P_2_BCD DUT (.P(in_P_tb[7:0]), .ones(BCD0_tb[3:0]),.tens(BCD1_tb[3:0]),.hundreds(BCD2_tb[3:0]));

integer i = 0;
initial
    begin
        for (i = 0; i < 256; i = i + 1)
        begin
        in_P_tb = i;
        $display("P = %b = %d",in_P_tb[7:0],in_P_tb[7:0]);
        $display("BCD0 = %b = %d",BCD0_tb[3:0],BCD0_tb[3:0]);
        $display("BCD1 = %b = %d",BCD1_tb[3:0],BCD1_tb[3:0]);
        $display("BCD2 = %b = %d\n\n",BCD2_tb[3:0],BCD2_tb[3:0]);
        end
        $finish;
end

endmodule
module P_to_BCD_tb;


reg  [7:0] in_P_tb;                     
wire  [3:0] BCD0_tb;                    
wire  [3:0] BCD1_tb;
wire  [3:0] BCD2_tb;

P_2_BCD DUT (.P(in_P_tb[7:0]), .ones(BCD0_tb[3:0]),.tens(BCD1_tb[3:0]),.hundreds(BCD2_tb[3:0]));

integer i = 0;
initial
    begin
        for (i = 0; i < 256; i = i + 1)
        begin
        in_P_tb = i;
        $display("P = %b = %d",in_P_tb[7:0],in_P_tb[7:0]);
        $display("BCD0 = %b = %d",BCD0_tb[3:0],BCD0_tb[3:0]);
        $display("BCD1 = %b = %d",BCD1_tb[3:0],BCD1_tb[3:0]);
        $display("BCD2 = %b = %d\n\n",BCD2_tb[3:0],BCD2_tb[3:0]);
        end
        $finish;
end

endmodule