data/full_repos/permissive/107757225/audio/clock_divider.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/107757225/audio/clock_divider.sv:39: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                 : ... Top module \'ClkDivider\'\nmodule ClkDivider (\n       ^~~~~~~~~~\n                                                                                 : ... Top module \'aud_xck_divider\'\nmodule aud_xck_divider (\n       ^~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module ClkDivider (
    input clk,
    input rst,
    output reg clk_div
    );


localparam constantNumber = 3000;



reg [31:0] count;

always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        count <= 32'b0;
    else if (count == constantNumber - 1)
        count <= 32'b0;
    else
        count <= count + 1;
end

always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        clk_div <= 1'b0;
    else if (count == constantNumber - 1)
        clk_div <= ~clk_div;
    else
        clk_div <= clk_div;
end
  
endmodule
module ClkDivider (
    input clk,
    input rst,
    output reg clk_div
    );



localparam constantNumber = 3000;



reg [31:0] count;

always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        count <= 32'b0;
    else if (count == constantNumber - 1)
        count <= 32'b0;
    else
        count <= count + 1;
end

always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        clk_div <= 1'b0;
    else if (count == constantNumber - 1)
        clk_div <= ~clk_div;
    else
        clk_div <= clk_div;
end
  
endmodule