data/full_repos/permissive/115074071/src/main/Datapath/RF.v
data/verilator_xmls/40831005-2362-4d84-9904-52dfc71c4ec8.xml
module RF(
    input   clk,
    input   RegWrite,

    input   [4:0]   ReadAddr1,
    input   [4:0]   ReadAddr2,

    input   [4:0]   WriteAddr,
    input   [31:0]  WriteData,
    
    output  [31:0]  ReadData1,
    output  [31:0]  ReadData2
);

    reg[31:0]   register[31:0];
    integer     i;

    initial begin
        for(i = 0; i < 32; i = i + 1)
            register[i] = 0;
    end

    always@(negedge clk) begin
        if (WriteAddr != 0 && RegWrite) begin
            register[WriteAddr] = WriteData[31:0];
            $display("RF Write: %x to %d", WriteData[31:0], WriteAddr);
        end

        $display("----------------------------------- RF Start ---------------------------------");
        for(i = 0; i < 32; i = i + 1)
            if (register[i] != 0) begin
                $display("RF %d: %x", i, register[i]);
            end
        $display("----------------------------------- RF fin -----------------------------------");
    end

    assign ReadData1 = register[ReadAddr1];
    assign ReadData2 = register[ReadAddr2];

endmodule
module RF(
    input   clk,
    input   RegWrite,

    input   [4:0]   ReadAddr1,
    input   [4:0]   ReadAddr2,

    input   [4:0]   WriteAddr,
    input   [31:0]  WriteData,
    
    output  [31:0]  ReadData1,
    output  [31:0]  ReadData2
);


    reg[31:0]   register[31:0];
    integer     i;

    initial begin
        for(i = 0; i < 32; i = i + 1)
            register[i] = 0;
    end

    always@(negedge clk) begin
        if (WriteAddr != 0 && RegWrite) begin
            register[WriteAddr] = WriteData[31:0];
            $display("RF Write: %x to %d", WriteData[31:0], WriteAddr);
        end

        $display("----------------------------------- RF Start ---------------------------------");
        for(i = 0; i < 32; i = i + 1)
            if (register[i] != 0) begin
                $display("RF %d: %x", i, register[i]);
            end
        $display("----------------------------------- RF fin -----------------------------------");
    end

    assign ReadData1 = register[ReadAddr1];
    assign ReadData2 = register[ReadAddr2];

endmodule