data/full_repos/permissive/135008983/code/Divider_50MHz.v
1: b'%Warning-WIDTH: data/full_repos/permissive/135008983/code/Divider_50MHz.v:27: Operator LT expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'Count_DIV\' generates 25 bits.\n                                                                            : ... In instance Divider_50MHz\n  if (Count_DIV<(CLK_Freq/(2*OUT_Freq)-1)) \n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Divider_50MHz(CLK_1HzOut, CLK_50M, nCLR);

output reg 	CLK_1HzOut;
input 		nCLR, CLK_50M;


parameter N = 25;

parameter CLK_Freq = 50000000;
parameter OUT_Freq = 1;


reg [N-1:0] Count_DIV;


always @(posedge CLK_50M or negedge nCLR) begin
	if (!nCLR) begin

		CLK_1HzOut <= 0;

		Count_DIV <= 0;
	end
	else  begin
		if (Count_DIV<(CLK_Freq/(2*OUT_Freq)-1)) 
			Count_DIV <= Count_DIV+1'b1; 
		else begin

			Count_DIV <= 0;
			CLK_1HzOut <= ~CLK_1HzOut;
		end
	end
end
endmodule
module Divider_50MHz(CLK_1HzOut, CLK_50M, nCLR);


output reg 	CLK_1HzOut;
input 		nCLR, CLK_50M;


parameter N = 25;

parameter CLK_Freq = 50000000;
parameter OUT_Freq = 1;


reg [N-1:0] Count_DIV;


always @(posedge CLK_50M or negedge nCLR) begin
	if (!nCLR) begin

		CLK_1HzOut <= 0;

		Count_DIV <= 0;
	end
	else  begin
		if (Count_DIV<(CLK_Freq/(2*OUT_Freq)-1)) 
			Count_DIV <= Count_DIV+1'b1; 
		else begin

			Count_DIV <= 0;
			CLK_1HzOut <= ~CLK_1HzOut;
		end
	end
end
endmodule