data/full_repos/permissive/135851130/Simpletron.v
data/verilator_xmls/a01c8e6d-299e-440a-90af-3fca0eeecc88.xml
module Simpletron( 
	input clk, 
	input reset, 
	input [7:0] data_in, 
	output [13:0] data_out
);

reg haltstate, overflow, af, sf, ldf, stf;
reg [4:0] pc;
reg [4:0] adbuff;
reg [7:0] acc;


localparam [2:0] HALT = 3'b000, 
					  BRANCH = 3'b001,	
					  BRIFACC = 3'b010,
					  BRIFOVF = 3'b011,
					  ADD = 3'b100,
					  SUBTRACT = 3'b101, 
					  LOAD = 3'b110,
					  STORE = 3'b111;

always @(posedge clk,posedge reset)
if(reset) 
begin
	haltstate = 1'b0; 
	overflow = 1'b0; 
	af = 1'b0; 
	sf = 1'b0; 
	ldf = 1'b0; 
	stf = 1'b0; 
	pc = 5'b00000; 
	acc = 8'b00000000; 
	adbuff = 5'b00000; 
end
else
	if(~haltstate)
		if(af)
			begin 
				{overflow,acc} = acc+data_in;
				af = 1'b0;
				adbuff = pc; 
			end
		else if(sf)
			begin 
				overflow = acc < data_in;
				acc = acc-data_in; sf = 1'b0;
				sf = 1'b0;
				adbuff = pc; 
			end 
		else if(ldf)
			begin 
				acc = data_in;
				ldf = 1'b0;
				adbuff = pc; 
			end
		else if(stf)
			begin   
				stf = 1'b0;
				adbuff = pc; 
			end
		else
			case(data_in[7:5])    
			HALT: 
				begin 
					haltstate = 1;
					adbuff = 5'b00000; 
					pc = 5'b00000; 
				end
			BRANCH: 
				begin 
					adbuff = data_in[4:0];
					pc = data_in[4:0];
				end
			BRIFACC: 
				if(acc==8'h00)
					begin  
						adbuff = data_in[4:0];
						pc = data_in[4:0];
					end 
				else 
					begin 
						pc = pc+1;
						adbuff = pc; 
					end 
			BRIFOVF: 
				if(overflow)
					begin 
						adbuff = data_in[4:0];
						pc = data_in[4:0];
					end
				else 
					begin 
						pc = pc+1; 
						adbuff = pc; 
					end 
			ADD: 
				begin 
					af = 1'b1;
					adbuff = data_in[4:0]; 
					pc = pc+1;
				end
			SUBTRACT: 
				begin 
					sf = 1'b1;
					adbuff = data_in[4:0]; 
					pc = pc+1;
				end
			LOAD: 
				begin 
					ldf = 1'b1;
					adbuff = data_in[4:0]; 
					pc = pc+1;
				end 
			STORE: 
				begin 
					stf = 1'b1;
					adbuff = data_in[4:0]; 
					pc = pc+1;
				end
			endcase 
			
assign data_out = {stf,adbuff,acc};
endmodule
module Simpletron( 
	input clk, 
	input reset, 
	input [7:0] data_in, 
	output [13:0] data_out
);


reg haltstate, overflow, af, sf, ldf, stf;
reg [4:0] pc;
reg [4:0] adbuff;
reg [7:0] acc;


localparam [2:0] HALT = 3'b000, 
					  BRANCH = 3'b001,	
					  BRIFACC = 3'b010,
					  BRIFOVF = 3'b011,
					  ADD = 3'b100,
					  SUBTRACT = 3'b101, 
					  LOAD = 3'b110,
					  STORE = 3'b111;

always @(posedge clk,posedge reset)
if(reset) 
begin
	haltstate = 1'b0; 
	overflow = 1'b0; 
	af = 1'b0; 
	sf = 1'b0; 
	ldf = 1'b0; 
	stf = 1'b0; 
	pc = 5'b00000; 
	acc = 8'b00000000; 
	adbuff = 5'b00000; 
end
else
	if(~haltstate)
		if(af)
			begin 
				{overflow,acc} = acc+data_in;
				af = 1'b0;
				adbuff = pc; 
			end
		else if(sf)
			begin 
				overflow = acc < data_in;
				acc = acc-data_in; sf = 1'b0;
				sf = 1'b0;
				adbuff = pc; 
			end 
		else if(ldf)
			begin 
				acc = data_in;
				ldf = 1'b0;
				adbuff = pc; 
			end
		else if(stf)
			begin   
				stf = 1'b0;
				adbuff = pc; 
			end
		else
			case(data_in[7:5])    
			HALT: 
				begin 
					haltstate = 1;
					adbuff = 5'b00000; 
					pc = 5'b00000; 
				end
			BRANCH: 
				begin 
					adbuff = data_in[4:0];
					pc = data_in[4:0];
				end
			BRIFACC: 
				if(acc==8'h00)
					begin  
						adbuff = data_in[4:0];
						pc = data_in[4:0];
					end 
				else 
					begin 
						pc = pc+1;
						adbuff = pc; 
					end 
			BRIFOVF: 
				if(overflow)
					begin 
						adbuff = data_in[4:0];
						pc = data_in[4:0];
					end
				else 
					begin 
						pc = pc+1; 
						adbuff = pc; 
					end 
			ADD: 
				begin 
					af = 1'b1;
					adbuff = data_in[4:0]; 
					pc = pc+1;
				end
			SUBTRACT: 
				begin 
					sf = 1'b1;
					adbuff = data_in[4:0]; 
					pc = pc+1;
				end
			LOAD: 
				begin 
					ldf = 1'b1;
					adbuff = data_in[4:0]; 
					pc = pc+1;
				end 
			STORE: 
				begin 
					stf = 1'b1;
					adbuff = data_in[4:0]; 
					pc = pc+1;
				end
			endcase 
			
assign data_out = {stf,adbuff,acc};
endmodule