data/full_repos/permissive/155064391/demo/oled_hello.v
None: at end of input
1: b'%Error: data/full_repos/permissive/155064391/demo/oled_hello.v:1: Cannot find include file: components/oled.v\n`include "components/oled.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155064391/demo,data/full_repos/permissive/155064391/components/oled.v\n             data/full_repos/permissive/155064391/demo,data/full_repos/permissive/155064391/components/oled.v.v\n             data/full_repos/permissive/155064391/demo,data/full_repos/permissive/155064391/components/oled.v.sv\n             components/oled.v\n             components/oled.v.v\n             components/oled.v.sv\n             obj_dir/components/oled.v\n             obj_dir/components/oled.v.v\n             obj_dir/components/oled.v.sv\n%Error: Exiting due to 1 error(s)\n'
module text_display(input wire       clk,
                    input wire       d_read,
                    input wire [2:0] d_page_idx,
                    input wire [6:0] d_column_idx,
                    output reg [7:0] d_data,
                    output reg       d_ack);

  reg [7:0]  font[0:128*8-1];
  reg [10:0] font_idx;
  reg        font_idx_ready = 0;

  reg [7:0]  text[0:16*8-1];
  reg [6:0]  text_idx;
  reg        text_idx_ready = 0;

  initial begin
    $readmemh("font.mem", font);
    $readmemh("text.mem", text);
    d_ack <= 0;
  end

  always @(posedge clk) begin
    d_ack <= 0;
    text_idx_ready <= 0;
    font_idx_ready <= 0;
    if (d_read) begin
      text_idx <= d_page_idx * 16 + d_column_idx / 8;
      text_idx_ready <= 1;
    end else if (text_idx_ready) begin
      font_idx <= (text[text_idx] - 'h20) * 8 + d_column_idx % 8;
      font_idx_ready <= 1;
    end else if (font_idx_ready) begin
      d_data <= font[font_idx];
      d_ack <= 1;
    end
  end
endmodule
module text_display(input wire       clk,
                    input wire       d_read,
                    input wire [2:0] d_page_idx,
                    input wire [6:0] d_column_idx,
                    output reg [7:0] d_data,
                    output reg       d_ack);


  reg [7:0]  font[0:128*8-1];
  reg [10:0] font_idx;
  reg        font_idx_ready = 0;

  reg [7:0]  text[0:16*8-1];
  reg [6:0]  text_idx;
  reg        text_idx_ready = 0;

  initial begin
    $readmemh("font.mem", font);
    $readmemh("text.mem", text);
    d_ack <= 0;
  end

  always @(posedge clk) begin
    d_ack <= 0;
    text_idx_ready <= 0;
    font_idx_ready <= 0;
    if (d_read) begin
      text_idx <= d_page_idx * 16 + d_column_idx / 8;
      text_idx_ready <= 1;
    end else if (text_idx_ready) begin
      font_idx <= (text[text_idx] - 'h20) * 8 + d_column_idx % 8;
      font_idx_ready <= 1;
    end else if (font_idx_ready) begin
      d_data <= font[font_idx];
      d_ack <= 1;
    end
  end
endmodule