data/full_repos/permissive/173670949/servo_test/top.v
 line:19: before: ";"
data/verilator_xmls/10f67bf0-efd2-49ed-a074-17e5762af874.xml
module Top(
    input ICE_CLK,
    output GLED5
);

    reg [18:0] counter = 0;

    always @(posedge ICE_CLK) begin
        counter <= counter + 1;
    end

    wire servo_clk;
    assign servo_clk = counter[18];



endmodule
module Top(
    input ICE_CLK,
    output GLED5
);


    reg [18:0] counter = 0;

    always @(posedge ICE_CLK) begin
        counter <= counter + 1;
    end

    wire servo_clk;
    assign servo_clk = counter[18];



endmodule