data/full_repos/permissive/143278/ivltests/br965.v
 line:22: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br965.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display(value);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module shim(
  inout wire bit0,
  inout wire bit1,
  inout wire bit2
);

wire [2:0] value = {bit2, bit1, bit0};

initial begin
  #1 $display(value);
  if (value === 2)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module shim(
  inout wire bit0,
  inout wire bit1,
  inout wire bit2
);


wire [2:0] value = {bit2, bit1, bit0};

initial begin
  #1 $display(value);
  if (value === 2)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule