data/full_repos/permissive/212495825/src/gaplus_stargen.v
 line:44: before: "<="
1: b'%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_stargen.v:58: Operator COND expects 12 bits on the Conditional False, but Conditional False\'s SEL generates 3 bits.\n                                                                            : ... In instance GAPLUS_STARGEN\n   sp1 <= C1[4] ? (12\'d384 * C1[2:0]) : C1[2:0]; sp1d <= C1[3];\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_stargen.v:59: Operator COND expects 12 bits on the Conditional False, but Conditional False\'s SEL generates 3 bits.\n                                                                            : ... In instance GAPLUS_STARGEN\n   sp2 <= C2[4] ? (12\'d384 * C2[2:0]) : C2[2:0]; sp2d <= C2[3];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_stargen.v:60: Operator COND expects 12 bits on the Conditional False, but Conditional False\'s SEL generates 3 bits.\n                                                                            : ... In instance GAPLUS_STARGEN\n   sp3 <= C3[4] ? (12\'d384 * C3[2:0]) : C3[2:0]; sp3d <= C3[3];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_stargen.v:72: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'oSTAR1\' generates 8 bits.\n                                                                            : ... In instance GAPLUS_STARGEN\n    OUT   <= ( oSTAR1 ? oSTAR1 : ( oSTAR2 ? oSTAR2 : oSTAR3 ) );\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_stargen.v:72: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'oSTAR2\' generates 8 bits.\n                                                                            : ... In instance GAPLUS_STARGEN\n    OUT   <= ( oSTAR1 ? oSTAR1 : ( oSTAR2 ? oSTAR2 : oSTAR3 ) );\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_stargen.v:81: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'sp1\' generates 12 bits.\n                                                                            : ... In instance GAPLUS_STARGEN\n   if ( sp1 ) begin sLFSR1 <= LFSR(sLFSR1,~sp1d); sp1 <= sp1-1; end\n   ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_stargen.v:82: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'sp2\' generates 12 bits.\n                                                                            : ... In instance GAPLUS_STARGEN\n   if ( sp2 ) begin sLFSR2 <= LFSR(sLFSR2,~sp2d); sp2 <= sp2-1; end\n   ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_stargen.v:83: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'sp3\' generates 12 bits.\n                                                                            : ... In instance GAPLUS_STARGEN\n   if ( sp3 ) begin sLFSR3 <= LFSR(sLFSR3,~sp3d); sp3 <= sp3-1; end\n   ^~\n%Error: Exiting due to 8 warning(s)\n'
function [15:0] LFSR;
input [15:0] in;
input			 dir;
	if ( dir ) LFSR = { in[14:0], ((in[15]^in[4])^in[2])^in[1] };
	else		  LFSR = { ((in[0]^in[2])^in[3])^in[5],  in[15:1] };
endfunction
function [15:0] LFSR;

input [15:0] in;
input			 dir;
	if ( dir ) LFSR = { in[14:0], ((in[15]^in[4])^in[2])^in[1] };
	else		  LFSR = { ((in[0]^in[2])^in[3])^in[5],  in[15:1] };
endfunction