data/full_repos/permissive/143278/ivltests/cond_wide.v
 line:28: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/cond_wide.v:28: Unsupported: Ignoring delay on this delayed statement.\n   initial #1 begin\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/cond_wide.v:29: Logical Operator WHILE expects 1 bit on the For Test Condition, but For Test Condition\'s VARREF \'foo\' generates 2 bits.\n                                                                         : ... In instance test\n      while (foo) begin\n      ^~~~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   reg [1:0] foo = 2'b10;

   initial #1 begin
      while (foo) begin
	 $display("PASSED");
	 $finish;
      end
      $display("FAILED -- foo = %b", foo);
   end

endmodule
module test;


   reg [1:0] foo = 2'b10;

   initial #1 begin
      while (foo) begin
	 $display("PASSED");
	 $finish;
      end
      $display("FAILED -- foo = %b", foo);
   end

endmodule