data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_new.v
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1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_new.v:79: Cannot find file containing module: 'FDDRRSE'\nFDDRRSE dm_fddr0 (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/FDDRRSE\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/FDDRRSE.v\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/FDDRRSE.sv\n             FDDRRSE\n             FDDRRSE.v\n             FDDRRSE.sv\n             obj_dir/FDDRRSE\n             obj_dir/FDDRRSE.v\n             obj_dir/FDDRRSE.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_new.v:90: Cannot find file containing module: 'FDDRRSE'\nFDDRRSE dm_fddr1 (\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module iobs_new (
	clock_i,
	reset_ni,
	

	ctl_ce_i,
	ctl_cke_i,
	
	ctl_cs_ni,
	ctl_ras_ni,
	ctl_cas_ni,
	ctl_we_ni,
	
	ctl_ba_i,
	ctl_a_i,
	
	ctl_dqs_i,
	ctl_dqs_o,
	ctl_dm_i,
	
	ctl_dq_i,
	ctl_dq_o,
	

	ddr_cke_o,
	ddr_ck_o,
	ddr_ck_no,
	
	ddr_cs_no,
	ddr_ras_no,
	ddr_cas_no,
	ddr_we_no,
	
	ddr_dqs_io,
	ddr_dm_o,
	
	ddr_dq_io
);

input	clock_i;
input	reset_ni;


input	ctl_ce_i;
input	ctl_cke_i;

input	ctl_cs_ni;
input	ctl_ras_ni;
input	ctl_cas_ni;
input	ctl_we_ni;

input	ctl_ba_i;
input	ctl_a_i;

input	ctl_dqs_i;
output	ctl_dqs_o;
input	ctl_dm_i;

input	ctl_dq_i;
output	ctl_dq_o;


output	ddr_cke_o;
output	ddr_ck_o;
output	ddr_ck_no;

output	ddr_cs_no;
output	ddr_ras_no;
output	ddr_cas_no;
output	ddr_we_no;

inout	ddr_dqs_io;
output	ddr_dm_o;

inout	ddr_dq_io;



FDDRRSE dm_fddr0 (
	.C0	(clock_270i),
	.C1	(~clock_270i),
	.CE	(1'b1),
	.D0	(cntrl_dm_i [2]),
	.D1	(cntrl_dm_i [0]),
	.R	(1'b0),
	.S	(1'b0),
	.Q	(ddr_dm_w [0])
);

FDDRRSE dm_fddr1 (
	.C0	(clock_270i),
	.C1	(~clock_270i),
	.CE	(1'b1),
	.D0	(ctl_dm_i [3]),
	.D1	(ctl_dm_i [1]),
	.R	(1'b0),
	.S	(1'b0),
	.Q	(ddr_dm_w [1])
);



endmodule
module iobs_new (
	clock_i,
	reset_ni,
	

	ctl_ce_i,
	ctl_cke_i,
	
	ctl_cs_ni,
	ctl_ras_ni,
	ctl_cas_ni,
	ctl_we_ni,
	
	ctl_ba_i,
	ctl_a_i,
	
	ctl_dqs_i,
	ctl_dqs_o,
	ctl_dm_i,
	
	ctl_dq_i,
	ctl_dq_o,
	

	ddr_cke_o,
	ddr_ck_o,
	ddr_ck_no,
	
	ddr_cs_no,
	ddr_ras_no,
	ddr_cas_no,
	ddr_we_no,
	
	ddr_dqs_io,
	ddr_dm_o,
	
	ddr_dq_io
);


input	clock_i;
input	reset_ni;


input	ctl_ce_i;
input	ctl_cke_i;

input	ctl_cs_ni;
input	ctl_ras_ni;
input	ctl_cas_ni;
input	ctl_we_ni;

input	ctl_ba_i;
input	ctl_a_i;

input	ctl_dqs_i;
output	ctl_dqs_o;
input	ctl_dm_i;

input	ctl_dq_i;
output	ctl_dq_o;


output	ddr_cke_o;
output	ddr_ck_o;
output	ddr_ck_no;

output	ddr_cs_no;
output	ddr_ras_no;
output	ddr_cas_no;
output	ddr_we_no;

inout	ddr_dqs_io;
output	ddr_dm_o;

inout	ddr_dq_io;



FDDRRSE dm_fddr0 (
	.C0	(clock_270i),
	.C1	(~clock_270i),
	.CE	(1'b1),
	.D0	(cntrl_dm_i [2]),
	.D1	(cntrl_dm_i [0]),
	.R	(1'b0),
	.S	(1'b0),
	.Q	(ddr_dm_w [0])
);

FDDRRSE dm_fddr1 (
	.C0	(clock_270i),
	.C1	(~clock_270i),
	.CE	(1'b1),
	.D0	(ctl_dm_i [3]),
	.D1	(ctl_dm_i [1]),
	.R	(1'b0),
	.S	(1'b0),
	.Q	(ddr_dm_w [1])
);



endmodule