data/full_repos/permissive/123627914/src/main/modules/binary2bcdQuad/binary2bcdQuad.v
data/verilator_xmls/5775a247-e1d4-4138-ae21-547a4540a2e0.xml
module binary2bcdQuad(
outputEnable ,
DATA    ,
SIGNAL  ,
BCD1    ,
BCD2    ,
BCD3    ,
BCD4
);

parameter DATA_WIDTH = 32;
parameter BCD_WIDTH = 4;


input                       outputEnable;
input   [DATA_WIDTH-1:0]    DATA;	


output reg                  SIGNAL;
output reg  [BCD_WIDTH-1:0] BCD1;
output reg  [BCD_WIDTH-1:0] BCD2;
output reg  [BCD_WIDTH-1:0] BCD3;
output reg  [BCD_WIDTH-1:0] BCD4;	


reg         [DATA_WIDTH-1:0]	ABSOLUTE_VALUE;
reg         [13:0]				PARTIAL_VALUE;
integer							INDEX;
localparam  [DATA_WIDTH-1:0]    MAXVALUE = 32'd9999;




always @ (DATA or outputEnable) begin
    if (outputEnable) begin
        ABSOLUTE_VALUE = (DATA[31]) ? ~(DATA-1'b1) : DATA;
        SIGNAL = DATA[31];
        if (ABSOLUTE_VALUE > MAXVALUE) begin
	        BCD1 = 4'b1010;
	        BCD2 = 4'b1010;
            BCD3 = 4'b1010;
	        BCD4 = 4'b1010;
            PARTIAL_VALUE = 14'b0;
            INDEX = 0;
	    end else begin	
            PARTIAL_VALUE = ABSOLUTE_VALUE[13:0];
            BCD1 = 4'b0000; 
            BCD2 = 4'b0000;
            BCD3 = 4'b0000; 
            BCD4 = 4'b0000;
            for (INDEX = 13; INDEX >= 0; INDEX = INDEX-1) begin
	            if(BCD1 >= 4'b0101) BCD1 = BCD1 + 4'b0011;
	            if(BCD2 >= 4'b0101) BCD2 = BCD2 + 4'b0011;
                if(BCD3 >= 4'b0101) BCD3 = BCD3 + 4'b0011;
	            if(BCD4 >= 4'b0101) BCD4 = BCD4 + 4'b0011;
	            BCD1 = BCD1 << 1;
	            BCD1[0] = BCD2[3];
                BCD2 = BCD2 << 1;
	            BCD2[0] = BCD3[3];
                BCD3 = BCD3 << 1;
	            BCD3[0] = BCD4[3];	
	            BCD4 = BCD4 << 1;
	            BCD4[0] = PARTIAL_VALUE[INDEX];
            end
        end
    end else begin
        BCD1 = 4'b1011;
        BCD2 = 4'b1011;
        BCD3 = 4'b1011;
        BCD4 = 4'b1011;
        SIGNAL = 1'b0;
        ABSOLUTE_VALUE = 32'b0;
        PARTIAL_VALUE = 14'b0;
        INDEX = 0;
    end
end

endmodule
module binary2bcdQuad(
outputEnable ,
DATA    ,
SIGNAL  ,
BCD1    ,
BCD2    ,
BCD3    ,
BCD4
);


parameter DATA_WIDTH = 32;
parameter BCD_WIDTH = 4;


input                       outputEnable;
input   [DATA_WIDTH-1:0]    DATA;	


output reg                  SIGNAL;
output reg  [BCD_WIDTH-1:0] BCD1;
output reg  [BCD_WIDTH-1:0] BCD2;
output reg  [BCD_WIDTH-1:0] BCD3;
output reg  [BCD_WIDTH-1:0] BCD4;	


reg         [DATA_WIDTH-1:0]	ABSOLUTE_VALUE;
reg         [13:0]				PARTIAL_VALUE;
integer							INDEX;
localparam  [DATA_WIDTH-1:0]    MAXVALUE = 32'd9999;




always @ (DATA or outputEnable) begin
    if (outputEnable) begin
        ABSOLUTE_VALUE = (DATA[31]) ? ~(DATA-1'b1) : DATA;
        SIGNAL = DATA[31];
        if (ABSOLUTE_VALUE > MAXVALUE) begin
	        BCD1 = 4'b1010;
	        BCD2 = 4'b1010;
            BCD3 = 4'b1010;
	        BCD4 = 4'b1010;
            PARTIAL_VALUE = 14'b0;
            INDEX = 0;
	    end else begin	
            PARTIAL_VALUE = ABSOLUTE_VALUE[13:0];
            BCD1 = 4'b0000; 
            BCD2 = 4'b0000;
            BCD3 = 4'b0000; 
            BCD4 = 4'b0000;
            for (INDEX = 13; INDEX >= 0; INDEX = INDEX-1) begin
	            if(BCD1 >= 4'b0101) BCD1 = BCD1 + 4'b0011;
	            if(BCD2 >= 4'b0101) BCD2 = BCD2 + 4'b0011;
                if(BCD3 >= 4'b0101) BCD3 = BCD3 + 4'b0011;
	            if(BCD4 >= 4'b0101) BCD4 = BCD4 + 4'b0011;
	            BCD1 = BCD1 << 1;
	            BCD1[0] = BCD2[3];
                BCD2 = BCD2 << 1;
	            BCD2[0] = BCD3[3];
                BCD3 = BCD3 << 1;
	            BCD3[0] = BCD4[3];	
	            BCD4 = BCD4 << 1;
	            BCD4[0] = PARTIAL_VALUE[INDEX];
            end
        end
    end else begin
        BCD1 = 4'b1011;
        BCD2 = 4'b1011;
        BCD3 = 4'b1011;
        BCD4 = 4'b1011;
        SIGNAL = 1'b0;
        ABSOLUTE_VALUE = 32'b0;
        PARTIAL_VALUE = 14'b0;
        INDEX = 0;
    end
end

endmodule