data/full_repos/permissive/195227969/work/code/m_condcode.v
 line:190 column:16: Illegal character "'"
data/verilator_xmls/2868e151-e08f-4af1-9b22-a11460bfe78f.xml
module m_condcode # ( parameter HIGHLEVEL = 0, MULDIV = 0 )
   (
    input        clk,
    input        alu_carryout,
    input [31:0] INSTR,
    input        A31,
    input        QQ31,

    input        use_dinx,
    input        cond_holdq,
    input        ceM,
    input [2:0]  s_alu,

    input        sa14,

    input        rzcy32,
    output       raluF,
    output       is_brcond,

    output       cmb_rF2,

    output       m_condcode_killwarnings
    );
   
   generate
      if ( MULDIV == 0 ) begin
         reg       cmb_aluF,tmp_raluF,tmp_is_brcond;
         
         always @(*)
           case (INSTR[14:12])
             3'b010 : cmb_aluF = ((A31^QQ31)&(~alu_carryout)) | (A31&QQ31);
             3'b011 : cmb_aluF = ~alu_carryout; 
             3'b100 : cmb_aluF = ((A31^QQ31)&(~alu_carryout)) | (A31&QQ31);
             3'b101 : cmb_aluF = ((A31^QQ31)&(~alu_carryout)) | (A31&QQ31);
             3'b110 : cmb_aluF = ~alu_carryout;
             3'b111 : cmb_aluF = ~alu_carryout;
             default: cmb_aluF = 1'b0;  
           endcase
         
         always @(posedge clk) 
           tmp_raluF <= cmb_aluF;
         assign raluF = tmp_raluF;
         
         always @(*)
           case (INSTR[14:12])
             3'b000 : tmp_is_brcond = ~rzcy32;
             3'b001 : tmp_is_brcond = rzcy32;
             3'b100 : tmp_is_brcond = raluF ;
             3'b101 : tmp_is_brcond = ~raluF;
             3'b110 : tmp_is_brcond = raluF ;
             3'b111 : tmp_is_brcond = ~raluF;
             default :tmp_is_brcond = 1'b0;
           endcase   
         assign is_brcond = tmp_is_brcond;
         assign m_condcode_killwarnings = &INSTR[31:15] | &INSTR[11:0];

         assign cmb_rF2 = 0;
         
      end else begin
         


         reg [2:0] feed;
         reg       tmp_rF;
         wire      rF;
         reg       cmb_aluF;
         reg       tmp_is_brcond;
         
         always @(*)                                  
           casez ({use_dinx,ceM,INSTR[25],INSTR[6:5],INSTR[14:12]})






             8'b 0_1_101_011 : feed = { 1'b0,  1'b0     , 1'b0     };
             8'b 0_1_101_001 : feed = { 1'b0,  1'b0     , rF       };
             8'b 0_1_101_010 : feed = { 1'b0,  1'b0     , rF       };
             8'b 0_1_101_1?? : feed = { 1'b0,  1'b0     , QQ31     };
             8'b 1_?_???_??? : feed = { 1'b0,  1'b0     , 1'b0     };
                                                 
             8'b 0_?_?00_011 : feed = { 1'b0,  1'b1     , 1'b1     };
             8'b 0_?_001_011 : feed = { 1'b0,  1'b1     , 1'b1     };
             8'b 0_?_?11_11? : feed = { 1'b0,  1'b1     , 1'b1     };

             8'b 0_0_101_011 : feed = { 1'b0,  1'b1     , 1'b0     };
             8'b 0_0_101_001 : feed = { 1'b0,  1'b1     , rF^A31   };
             8'b 0_0_101_010 : feed = { 1'b0,  1'b1     , rF^A31   };
             8'b 0_0_101_1?? : feed = { 1'b0,  1'b1     , rF^1'b1  };
                                             
             8'b 0_?_?00_010 : feed = { 1'b1,  A31&QQ31 , A31^QQ31};
             8'b 0_?_001_010 : feed = { 1'b1,  A31&QQ31 , A31^QQ31};
             8'b 0_?_?11_100 : feed = { 1'b1,  A31&QQ31 , A31^QQ31};
             8'b 0_?_?11_101 : feed = { 1'b1,  A31&QQ31 , A31^QQ31};
             default :       feed = 3'b000;
           endcase
         reg       basic;
         always @(*)
           casez (feed)
             3'b000 : basic = 1'b0;
             3'b001 : basic = 1'b1;
             3'b010 : basic = alu_carryout;
             3'b011 : basic = ~alu_carryout;
             3'b100 : basic = 1'b0;
             3'b101 : basic = ~alu_carryout;
             3'b11? : basic = 1'b1;
           endcase                             
         
         always @(*)
           casez ({sa14,s_alu})
             4'b1000 : cmb_aluF = rF;
             4'b00?? : cmb_aluF = 0;
             4'b0100 : cmb_aluF = basic;
             4'b0101 : cmb_aluF = 0;
             4'b011? : cmb_aluF = 0;
             default : cmb_aluF = basic;
           endcase
         
         always @(posedge clk)
           if ( ~cond_holdq )
             tmp_rF <= cmb_aluF;
         assign rF = tmp_rF;
         assign cmb_rF2 = cmb_aluF;

         always @(*)
           casez ({INSTR[6],INSTR[14],INSTR[12]})
             3'b0?? : tmp_is_brcond = ~rzcy32;
             3'b100 : tmp_is_brcond = ~rzcy32;
             3'b101 : tmp_is_brcond = rzcy32;
             3'b110 : tmp_is_brcond = rF ;
             3'b111 : tmp_is_brcond = ~rF;
           endcase   
         assign is_brcond = tmp_is_brcond;
         assign raluF = rF;
         assign m_condcode_killwarnings = &INSTR[31:26] | &INSTR[24:7] | &INSTR[4:0];
      end
   endgenerate
endmodule
module m_condcode # ( parameter HIGHLEVEL = 0, MULDIV = 0 )
   (
    input        clk,
    input        alu_carryout,
    input [31:0] INSTR,
    input        A31,
    input        QQ31,

    input        use_dinx,
    input        cond_holdq,
    input        ceM,
    input [2:0]  s_alu,

    input        sa14,

    input        rzcy32,
    output       raluF,
    output       is_brcond,

    output       cmb_rF2,

    output       m_condcode_killwarnings
    );

   
   generate
      if ( MULDIV == 0 ) begin
         reg       cmb_aluF,tmp_raluF,tmp_is_brcond;
         
         always @(*)
           case (INSTR[14:12])
             3'b010 : cmb_aluF = ((A31^QQ31)&(~alu_carryout)) | (A31&QQ31);
             3'b011 : cmb_aluF = ~alu_carryout; 
             3'b100 : cmb_aluF = ((A31^QQ31)&(~alu_carryout)) | (A31&QQ31);
             3'b101 : cmb_aluF = ((A31^QQ31)&(~alu_carryout)) | (A31&QQ31);
             3'b110 : cmb_aluF = ~alu_carryout;
             3'b111 : cmb_aluF = ~alu_carryout;
             default: cmb_aluF = 1'b0;  
           endcase
         
         always @(posedge clk) 
           tmp_raluF <= cmb_aluF;
         assign raluF = tmp_raluF;
         
         always @(*)
           case (INSTR[14:12])
             3'b000 : tmp_is_brcond = ~rzcy32;
             3'b001 : tmp_is_brcond = rzcy32;
             3'b100 : tmp_is_brcond = raluF ;
             3'b101 : tmp_is_brcond = ~raluF;
             3'b110 : tmp_is_brcond = raluF ;
             3'b111 : tmp_is_brcond = ~raluF;
             default :tmp_is_brcond = 1'b0;
           endcase   
         assign is_brcond = tmp_is_brcond;
         assign m_condcode_killwarnings = &INSTR[31:15] | &INSTR[11:0];

         assign cmb_rF2 = 0;
         
      end else begin
         


         reg [2:0] feed;
         reg       tmp_rF;
         wire      rF;
         reg       cmb_aluF;
         reg       tmp_is_brcond;
         
         always @(*)                                  
           casez ({use_dinx,ceM,INSTR[25],INSTR[6:5],INSTR[14:12]})






             8'b 0_1_101_011 : feed = { 1'b0,  1'b0     , 1'b0     };
             8'b 0_1_101_001 : feed = { 1'b0,  1'b0     , rF       };
             8'b 0_1_101_010 : feed = { 1'b0,  1'b0     , rF       };
             8'b 0_1_101_1?? : feed = { 1'b0,  1'b0     , QQ31     };
             8'b 1_?_???_??? : feed = { 1'b0,  1'b0     , 1'b0     };
                                                 
             8'b 0_?_?00_011 : feed = { 1'b0,  1'b1     , 1'b1     };
             8'b 0_?_001_011 : feed = { 1'b0,  1'b1     , 1'b1     };
             8'b 0_?_?11_11? : feed = { 1'b0,  1'b1     , 1'b1     };

             8'b 0_0_101_011 : feed = { 1'b0,  1'b1     , 1'b0     };
             8'b 0_0_101_001 : feed = { 1'b0,  1'b1     , rF^A31   };
             8'b 0_0_101_010 : feed = { 1'b0,  1'b1     , rF^A31   };
             8'b 0_0_101_1?? : feed = { 1'b0,  1'b1     , rF^1'b1  };
                                             
             8'b 0_?_?00_010 : feed = { 1'b1,  A31&QQ31 , A31^QQ31};
             8'b 0_?_001_010 : feed = { 1'b1,  A31&QQ31 , A31^QQ31};
             8'b 0_?_?11_100 : feed = { 1'b1,  A31&QQ31 , A31^QQ31};
             8'b 0_?_?11_101 : feed = { 1'b1,  A31&QQ31 , A31^QQ31};
             default :       feed = 3'b000;
           endcase
         reg       basic;
         always @(*)
           casez (feed)
             3'b000 : basic = 1'b0;
             3'b001 : basic = 1'b1;
             3'b010 : basic = alu_carryout;
             3'b011 : basic = ~alu_carryout;
             3'b100 : basic = 1'b0;
             3'b101 : basic = ~alu_carryout;
             3'b11? : basic = 1'b1;
           endcase                             
         
         always @(*)
           casez ({sa14,s_alu})
             4'b1000 : cmb_aluF = rF;
             4'b00?? : cmb_aluF = 0;
             4'b0100 : cmb_aluF = basic;
             4'b0101 : cmb_aluF = 0;
             4'b011? : cmb_aluF = 0;
             default : cmb_aluF = basic;
           endcase
         
         always @(posedge clk)
           if ( ~cond_holdq )
             tmp_rF <= cmb_aluF;
         assign rF = tmp_rF;
         assign cmb_rF2 = cmb_aluF;

         always @(*)
           casez ({INSTR[6],INSTR[14],INSTR[12]})
             3'b0?? : tmp_is_brcond = ~rzcy32;
             3'b100 : tmp_is_brcond = ~rzcy32;
             3'b101 : tmp_is_brcond = rzcy32;
             3'b110 : tmp_is_brcond = rF ;
             3'b111 : tmp_is_brcond = ~rF;
           endcase   
         assign is_brcond = tmp_is_brcond;
         assign raluF = rF;
         assign m_condcode_killwarnings = &INSTR[31:26] | &INSTR[24:7] | &INSTR[4:0];
      end
   endgenerate
endmodule