data/full_repos/permissive/208556773/src/dda_fsm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/208556773/src/dda_fsm.v:29: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n                                                                     : ... In instance dda_fsm\n  wire processing_move = (stepfinished[moveind] ^ stepready[moveind]);\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/208556773/src/dda_fsm.v:29: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n                                                                     : ... In instance dda_fsm\n  wire processing_move = (stepfinished[moveind] ^ stepready[moveind]);\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/208556773/src/dda_fsm.v:59: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n                                                                     : ... In instance dda_fsm\n      stepfinished[moveind] <= ~stepfinished[moveind];  \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/208556773/src/dda_fsm.v:59: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n                                                                     : ... In instance dda_fsm\n      stepfinished[moveind] <= ~stepfinished[moveind];  \n                                            ^\n%Error: Exiting due to 4 warning(s)\n'
module dda_fsm #(parameter buffer_bits = 2,
                 parameter buffer_size = 1,
                 parameter move_duration_bits = 32)
(
  input clk,
  input resetn,
  input dda_tick,
  input [move_duration_bits-1:0] move_duration,
  output loading_move,
  output executing_move,
  output reg move_done,
  output reg finishedmove,
  output reg [buffer_bits-1:0] moveind,
  input [buffer_size-1:0] stepready,
  output buffer_dtr
);



  (* onehot *) reg [buffer_size-1:0] stepfinished;


  wire processing_move = (stepfinished[moveind] ^ stepready[moveind]);
  assign loading_move = finishedmove & processing_move;
  assign executing_move = !finishedmove & processing_move;

  reg [move_duration_bits-1:0] tickdowncount;
  reg [1:0] dda_tick_r;

  always @(posedge clk) if (!resetn) begin
    move_done <= 0;
    finishedmove <= 1;
    stepfinished <= 0;
    moveind <= 0;
  end else if (resetn) begin

    if (loading_move) begin
      tickdowncount <= move_duration;
      finishedmove <= 0;
    end


    dda_tick_r <= {dda_tick_r[0], dda_tick};
    if (dda_tick_r == 2'b01 && executing_move) begin
      tickdowncount <= tickdowncount - 1'b1;
    end


    if (tickdowncount == 0 && executing_move) begin
      finishedmove <= 1;
      move_done <= ~move_done;
      moveind <= moveind + 1'b1;
      stepfinished[moveind] <= ~stepfinished[moveind];
    end
  end

  assign buffer_dtr = ~(~stepfinished == stepready);


endmodule
module dda_fsm #(parameter buffer_bits = 2,
                 parameter buffer_size = 1,
                 parameter move_duration_bits = 32)
(
  input clk,
  input resetn,
  input dda_tick,
  input [move_duration_bits-1:0] move_duration,
  output loading_move,
  output executing_move,
  output reg move_done,
  output reg finishedmove,
  output reg [buffer_bits-1:0] moveind,
  input [buffer_size-1:0] stepready,
  output buffer_dtr
);




  (* onehot *) reg [buffer_size-1:0] stepfinished;


  wire processing_move = (stepfinished[moveind] ^ stepready[moveind]);
  assign loading_move = finishedmove & processing_move;
  assign executing_move = !finishedmove & processing_move;

  reg [move_duration_bits-1:0] tickdowncount;
  reg [1:0] dda_tick_r;

  always @(posedge clk) if (!resetn) begin
    move_done <= 0;
    finishedmove <= 1;
    stepfinished <= 0;
    moveind <= 0;
  end else if (resetn) begin

    if (loading_move) begin
      tickdowncount <= move_duration;
      finishedmove <= 0;
    end


    dda_tick_r <= {dda_tick_r[0], dda_tick};
    if (dda_tick_r == 2'b01 && executing_move) begin
      tickdowncount <= tickdowncount - 1'b1;
    end


    if (tickdowncount == 0 && executing_move) begin
      finishedmove <= 1;
      move_done <= ~move_done;
      moveind <= moveind + 1'b1;
      stepfinished[moveind] <= ~stepfinished[moveind];
    end
  end

  assign buffer_dtr = ~(~stepfinished == stepready);


endmodule