data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite/main.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite/main.sv:21: Cannot find include file: rv_defs.v\n`include "rv_defs.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite,data/full_repos/permissive/161356276/rv_defs.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite,data/full_repos/permissive/161356276/rv_defs.v.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite,data/full_repos/permissive/161356276/rv_defs.v.sv\n             rv_defs.v\n             rv_defs.v.v\n             rv_defs.v.sv\n             obj_dir/rv_defs.v\n             obj_dir/rv_defs.v.v\n             obj_dir/rv_defs.v.sv\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite/main.sv:49: syntax error, unexpected $fopen, expecting TYPE-IDENTIFIER\n      int f = $fopen(filename,"r");\n              ^~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite/main.sv:80: Unsupported or unknown PLI call: $dist_uniform\n if(   $dist_uniform(seed, 0, 100 ) <= 100) begin\n       ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite/main.sv:139: Unsupported: Ignoring delay on this delayed statement.\n   always #5ns clk <= ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite/main.sv:149: syntax error, unexpected $fopen, expecting TYPE-IDENTIFIER\n      int f = $fopen( {test_dir,"/tests.lst"} ,"r");\n              ^~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite/main.sv:168: syntax error, unexpected \'@\'\n    repeat(3) @(posedge clk);\n              ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite/main.sv:171: syntax error, unexpected \'@\'\n    repeat(3) @(posedge clk);\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/tb/isa-testsuite/main.sv:176: Unsupported: Ignoring delay on this delayed statement.\n      #1us;\n      ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module main;

   
   reg clk = 0;
   reg rst = 1;
   
   wire [31:0] im_addr;
   reg [31:0] im_data;
   reg        im_valid;
   

   wire [31:0] dm_addr;
   wire [31:0] dm_data_s;
   reg [31:0] dm_data_l;
   wire [3:0]  dm_data_select;
   wire        dm_write;
   reg 	       dm_valid_l = 1;
   reg        dm_ready;
   
   localparam int mem_size = 16384;
   
   reg [31:0]  mem[0:mem_size - 1];

   task automatic load_ram(string filename);
      int f = $fopen(filename,"r");
      int     n, i;

      if( f == 0)
	begin
	   $error("can't open: %s", filename);
	   $stop;
	end
      
      
      
      while(!$feof(f))
        begin
           int addr, data;
           string cmd;
           
           $fscanf(f,"%s %08x %08x", cmd,addr,data);
           if(cmd == "write")
             begin
                mem[addr % mem_size] = data;
             end
        end
      
   endtask

   int seed;


   
   always@(posedge clk)
     begin
	if(   $dist_uniform(seed, 0, 100 ) <= 100) begin
	   im_data <= mem[(im_addr / 4) % mem_size];
	   im_valid <= 1;
	end else
	   im_valid <= 0;
	
	

	if(dm_write && dm_data_select[0])
	  mem [(dm_addr / 4) % mem_size][7:0] <= dm_data_s[7:0];
	if(dm_write && dm_data_select[1])
	  mem [(dm_addr / 4) % mem_size][15:8] <= dm_data_s[15:8];
	if(dm_write && dm_data_select[2])
	  mem [(dm_addr / 4) % mem_size][23:16] <= dm_data_s[23:16];
	if(dm_write && dm_data_select[3])
	  mem [(dm_addr / 4) % mem_size][31:24] <= dm_data_s[31:24];
	

	
	

	
	
     end


   
   always@(posedge clk)
     begin
	dm_ready <= 1'b1;

	dm_data_l <= mem[(dm_addr/4) % mem_size];
   end	   

   rv_cpu DUT
     (
      .clk_i(clk),
      .rst_i(rst),

      .irq_i ( irq ),
      

      .im_addr_o(im_addr),
      .im_data_i(im_data),
      .im_valid_i(im_valid),


      .dm_addr_o(dm_addr),
      .dm_data_s_o(dm_data_s),
      .dm_data_l_i(dm_data_l),
      .dm_data_select_o(dm_data_select),
      .dm_store_o(dm_write),
      .dm_load_o(),
      .dm_store_done_i(1'b1),
      .dm_load_done_i(1'b1),
      .dm_ready_i(dm_ready)
      );
   

   always #5ns clk <= ~clk;

   integer f_console, f_exec_log;
   reg 	   test_complete = 0;
   
   initial begin
      string tests[$];
      string test_dir = "../../sw/testsuite/isa";
      
      
      int f = $fopen( {test_dir,"/tests.lst"} ,"r");
      int     n, i;

      f_console = $fopen("console.txt","wb");

      while(!$feof(f))
        begin
           string fname;
           
           $fscanf(f,"%s", fname);
	   tests.push_back(fname);
	   
	   
        end


      for (i=0;i<tests.size();i++)
	begin
	   rst = 1;
	   repeat(3) @(posedge clk);
	   $display("Loading %s", {test_dir,"/",tests[i]} );
	   load_ram({test_dir,"/",tests[i]});
	   repeat(3) @(posedge clk);
	   rst = 0;
	   test_complete=  0;
	   
	   while(!test_complete)
	     #1us;
	   
	   
	end
      end
		    

   
   always@(posedge clk)
     if(dm_write)
       begin
	  if(dm_addr == 'h100000)
	    begin


	       $write("%c", dm_data_s[7:0]);
	       $fwrite(f_console,"%c", dm_data_s[7:0]);
	       $fflush(f_console);
	    end
	  else if(dm_addr == 'h100004)
	    begin

	       test_complete = 1;
	    end
       end
 
endmodule
module main;


   
   reg clk = 0;
   reg rst = 1;
   
   wire [31:0] im_addr;
   reg [31:0] im_data;
   reg        im_valid;
   

   wire [31:0] dm_addr;
   wire [31:0] dm_data_s;
   reg [31:0] dm_data_l;
   wire [3:0]  dm_data_select;
   wire        dm_write;
   reg 	       dm_valid_l = 1;
   reg        dm_ready;
   
   localparam int mem_size = 16384;
   
   reg [31:0]  mem[0:mem_size - 1];

   task automatic load_ram(string filename);
      int f = $fopen(filename,"r");
      int     n, i;

      if( f == 0)
	begin
	   $error("can't open: %s", filename);
	   $stop;
	end
      
      
      
      while(!$feof(f))
        begin
           int addr, data;
           string cmd;
           
           $fscanf(f,"%s %08x %08x", cmd,addr,data);
           if(cmd == "write")
             begin
                mem[addr % mem_size] = data;
             end
        end
      
   endtask

   int seed;


   
   always@(posedge clk)
     begin
	if(   $dist_uniform(seed, 0, 100 ) <= 100) begin
	   im_data <= mem[(im_addr / 4) % mem_size];
	   im_valid <= 1;
	end else
	   im_valid <= 0;
	
	

	if(dm_write && dm_data_select[0])
	  mem [(dm_addr / 4) % mem_size][7:0] <= dm_data_s[7:0];
	if(dm_write && dm_data_select[1])
	  mem [(dm_addr / 4) % mem_size][15:8] <= dm_data_s[15:8];
	if(dm_write && dm_data_select[2])
	  mem [(dm_addr / 4) % mem_size][23:16] <= dm_data_s[23:16];
	if(dm_write && dm_data_select[3])
	  mem [(dm_addr / 4) % mem_size][31:24] <= dm_data_s[31:24];
	

	
	

	
	
     end


   
   always@(posedge clk)
     begin
	dm_ready <= 1'b1;

	dm_data_l <= mem[(dm_addr/4) % mem_size];
   end	   

   rv_cpu DUT
     (
      .clk_i(clk),
      .rst_i(rst),

      .irq_i ( irq ),
      

      .im_addr_o(im_addr),
      .im_data_i(im_data),
      .im_valid_i(im_valid),


      .dm_addr_o(dm_addr),
      .dm_data_s_o(dm_data_s),
      .dm_data_l_i(dm_data_l),
      .dm_data_select_o(dm_data_select),
      .dm_store_o(dm_write),
      .dm_load_o(),
      .dm_store_done_i(1'b1),
      .dm_load_done_i(1'b1),
      .dm_ready_i(dm_ready)
      );
   

   always #5ns clk <= ~clk;

   integer f_console, f_exec_log;
   reg 	   test_complete = 0;
   
   initial begin
      string tests[$];
      string test_dir = "../../sw/testsuite/isa";
      
      
      int f = $fopen( {test_dir,"/tests.lst"} ,"r");
      int     n, i;

      f_console = $fopen("console.txt","wb");

      while(!$feof(f))
        begin
           string fname;
           
           $fscanf(f,"%s", fname);
	   tests.push_back(fname);
	   
	   
        end


      for (i=0;i<tests.size();i++)
	begin
	   rst = 1;
	   repeat(3) @(posedge clk);
	   $display("Loading %s", {test_dir,"/",tests[i]} );
	   load_ram({test_dir,"/",tests[i]});
	   repeat(3) @(posedge clk);
	   rst = 0;
	   test_complete=  0;
	   
	   while(!test_complete)
	     #1us;
	   
	   
	end
      end
		    

   
   always@(posedge clk)
     if(dm_write)
       begin
	  if(dm_addr == 'h100000)
	    begin


	       $write("%c", dm_data_s[7:0]);
	       $fwrite(f_console,"%c", dm_data_s[7:0]);
	       $fflush(f_console);
	    end
	  else if(dm_addr == 'h100004)
	    begin

	       test_complete = 1;
	    end
       end
 
endmodule