data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/5x5_Unidimensional/TOP.v
1: b"%Error: data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/5x5_Unidimensional/TOP.v:35: Cannot find file containing module: 'NovaCORE'\n NovaCORE#(1, 5, 10, 2, 1, 4, 1, 7) fpga(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/5x5_Unidimensional,data/full_repos/permissive/104784866/NovaCORE\n             data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/5x5_Unidimensional,data/full_repos/permissive/104784866/NovaCORE.v\n             data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/5x5_Unidimensional,data/full_repos/permissive/104784866/NovaCORE.sv\n             NovaCORE\n             NovaCORE.v\n             NovaCORE.sv\n             obj_dir/NovaCORE\n             obj_dir/NovaCORE.v\n             obj_dir/NovaCORE.sv\n%Error: Exiting due to 1 error(s)\n"
module TOP(
		clk,

		mode,
		c_bus,
		c_uid,
		c_clk,

		io_up_n,
		io_up_s,
		io_dn_n,
		io_dn_s,
		io_lt_n,
		io_lt_s,
		io_rt_n,
		io_rt_s
	);

	input clk;

	input mode;
	input [41:0] c_bus;
	input [6:0] c_uid;
	input c_clk;

	output [24:0] io_up_n;
	input [24:0] io_up_s;
	input [24:0] io_dn_n;
	output [24:0] io_dn_s;
	output [24:0] io_lt_n;
	input [24:0] io_lt_s;
	input [24:0] io_rt_n;
	output [24:0] io_rt_s;

	NovaCORE#(1, 5, 10, 2, 1, 4, 1, 7) fpga(
		.clk(clk),

		.mode(mode),
		.c_bus(c_bus),
		.c_uid(c_uid),
		.c_clk(c_clk),

		.io_up_n(io_up_n),
		.io_up_s(io_up_s),
		.io_dn_n(io_dn_n),
		.io_dn_s(io_dn_s),
		.io_lt_n(io_lt_n),
		.io_lt_s(io_lt_s),
		.io_rt_n(io_rt_n),
		.io_rt_s(io_rt_s)
	);

endmodule
module TOP(
		clk,

		mode,
		c_bus,
		c_uid,
		c_clk,

		io_up_n,
		io_up_s,
		io_dn_n,
		io_dn_s,
		io_lt_n,
		io_lt_s,
		io_rt_n,
		io_rt_s
	);


	input clk;

	input mode;
	input [41:0] c_bus;
	input [6:0] c_uid;
	input c_clk;

	output [24:0] io_up_n;
	input [24:0] io_up_s;
	input [24:0] io_dn_n;
	output [24:0] io_dn_s;
	output [24:0] io_lt_n;
	input [24:0] io_lt_s;
	input [24:0] io_rt_n;
	output [24:0] io_rt_s;

	NovaCORE#(1, 5, 10, 2, 1, 4, 1, 7) fpga(
		.clk(clk),

		.mode(mode),
		.c_bus(c_bus),
		.c_uid(c_uid),
		.c_clk(c_clk),

		.io_up_n(io_up_n),
		.io_up_s(io_up_s),
		.io_dn_n(io_dn_n),
		.io_dn_s(io_dn_s),
		.io_lt_n(io_lt_n),
		.io_lt_s(io_lt_s),
		.io_rt_n(io_rt_n),
		.io_rt_s(io_rt_s)
	);

endmodule