data/full_repos/permissive/169496369/instructionmem_8.v
data/verilator_xmls/1b95293b-f0a4-496b-b5ba-7bb66297e7cd.xml
module instructionmem_8(memread, read_address, instruction_re);
    
    input memread;
    
    input [5:0]read_address;
        
    output logic [31:0]instruction_re;


        
    logic [7:0]instruction_mem[63:0];    
    


    
    initial
    begin
        $readmemh("instr.mem", instruction_mem, 0, 63);
    end
    
    always_comb
    begin
        if(~memread)
            {instruction_re} = 
            {instruction_mem[read_address], instruction_mem[read_address + 6'd1], instruction_mem[read_address + 6'd2], instruction_mem[read_address + 6'd3]};
        else
            {instruction_re} = 32'hFFFFFFFF;
    end
endmodule
module instructionmem_8(memread, read_address, instruction_re);

    
    input memread;
    
    input [5:0]read_address;
        
    output logic [31:0]instruction_re;


        
    logic [7:0]instruction_mem[63:0];    
    


    
    initial
    begin
        $readmemh("instr.mem", instruction_mem, 0, 63);
    end
    
    always_comb
    begin
        if(~memread)
            {instruction_re} = 
            {instruction_mem[read_address], instruction_mem[read_address + 6'd1], instruction_mem[read_address + 6'd2], instruction_mem[read_address + 6'd3]};
        else
            {instruction_re} = 32'hFFFFFFFF;
    end
endmodule