data/full_repos/permissive/118895561/Project 2/bridge.v
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561.sv\n             2,data/full_repos/permissive/118895561\n             2,data/full_repos/permissive/118895561.v\n             2,data/full_repos/permissive/118895561.sv\n             obj_dir/2,data/full_repos/permissive/118895561\n             obj_dir/2,data/full_repos/permissive/118895561.v\n             obj_dir/2,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 2/bridge.v\n%Error: Exiting due to 3 error(s)\n'
module bridge(
    input [31:0] Addr,
	 input Device_WE,
    input [31:0] From_CPU,
    output [31:0] To_Counter,
    input [31:0] From_Counter_0,
    input [31:0] From_Counter_1,
    output [31:0] To_CPU,
    output [7:2] INT_REQ,
	 output Counter_0_WE,
	 output Counter_1_WE,
	 output [31:0] ADDR,
	 input  INT_REQ_0, INT_REQ_1
    );
	

	assign Counter_0_WE = (Addr[14] == 1 && Addr[5] == 0) ? Device_WE :
																			  1'b0	  ;
	 
	assign Counter_1_WE = (Addr[14] == 1 && Addr[5] == 1) ? Device_WE :
																			  1'b0	  ;
																			  
	assign To_Counter = From_CPU;
	
	assign ADDR = Addr;
	
	assign To_CPU = (Addr[14] == 1 && Addr[5] == 0) ? From_Counter_0 :
						 (Addr[14] == 1 && Addr[5] == 1) ? From_Counter_1 :
																				32'b0	  ;
																				
																				
	assign INT_REQ = {4'b0, INT_REQ_1, INT_REQ_0};

endmodule
module bridge(
    input [31:0] Addr,
	 input Device_WE,
    input [31:0] From_CPU,
    output [31:0] To_Counter,
    input [31:0] From_Counter_0,
    input [31:0] From_Counter_1,
    output [31:0] To_CPU,
    output [7:2] INT_REQ,
	 output Counter_0_WE,
	 output Counter_1_WE,
	 output [31:0] ADDR,
	 input  INT_REQ_0, INT_REQ_1
    );

	

	assign Counter_0_WE = (Addr[14] == 1 && Addr[5] == 0) ? Device_WE :
																			  1'b0	  ;
	 
	assign Counter_1_WE = (Addr[14] == 1 && Addr[5] == 1) ? Device_WE :
																			  1'b0	  ;
																			  
	assign To_Counter = From_CPU;
	
	assign ADDR = Addr;
	
	assign To_CPU = (Addr[14] == 1 && Addr[5] == 0) ? From_Counter_0 :
						 (Addr[14] == 1 && Addr[5] == 1) ? From_Counter_1 :
																				32'b0	  ;
																				
																				
	assign INT_REQ = {4'b0, INT_REQ_1, INT_REQ_0};

endmodule