data/full_repos/permissive/159610434/matrix_8x8/top.v
1: b"%Error: data/full_repos/permissive/159610434/matrix_8x8/top.v:60: Cannot find file containing module: 'rom'\n    rom u1 (.a(frame_count), .d(rom_out));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/159610434/matrix_8x8,data/full_repos/permissive/159610434/rom\n             data/full_repos/permissive/159610434/matrix_8x8,data/full_repos/permissive/159610434/rom.v\n             data/full_repos/permissive/159610434/matrix_8x8,data/full_repos/permissive/159610434/rom.sv\n             rom\n             rom.v\n             rom.sv\n             obj_dir/rom\n             obj_dir/rom.v\n             obj_dir/rom.sv\n%Error: Exiting due to 1 error(s)\n"
module top(
    input clk,
    output [4:0] bcount,
    output [3:0] a,
    output cs_n,
    output d
    );

    parameter FRAME_SIZE = 16;
    parameter CYCLE_WIDTH = FRAME_SIZE + 1;
    
    reg [4:0] bit_count = 0;
    reg [3:0] frame_count = 0;
    wire bit_count_max;
    wire frame_tick;
    wire cs;


    always @(negedge clk) begin
        if (bit_count_max)
            bit_count <= 0;
        else
            bit_count = bit_count + 1;     
    end


    assign bit_count_max = (bit_count == (CYCLE_WIDTH - 1)) ? 1'b1 : 1'b0;

    assign frame_tick = (bit_count == (CYCLE_WIDTH - 2)) ? 1'b1 : 1'b0;
    assign cs = (bit_count < (CYCLE_WIDTH - 1)) ? 1'b1 : 1'b0;
    
    always @(negedge clk) begin
        if (frame_tick)
            frame_count <= frame_count + 1;
    end

    wire [15:0] rom_out;
    
    rom u1 (.a(frame_count), .d(rom_out));
        
    reg [FRAME_SIZE-2:0] shift = {FRAME_SIZE-1{1'b0}};
    reg                  dout = 1'b0;
 
    always @(negedge clk) begin
       if (bit_count_max) begin
          shift <= rom_out[FRAME_SIZE-2:0];
          dout    <= rom_out[FRAME_SIZE-1];
       end
       else begin
          shift <= {shift[FRAME_SIZE-3:0], 1'b0};
          dout   <= shift[FRAME_SIZE-2];
       end
    end
    
    assign bcount = bit_count;
    assign a = frame_count;
    assign cs_n = ~cs;
    assign d = dout;

endmodule
module top(
    input clk,
    output [4:0] bcount,
    output [3:0] a,
    output cs_n,
    output d
    );


    parameter FRAME_SIZE = 16;
    parameter CYCLE_WIDTH = FRAME_SIZE + 1;
    
    reg [4:0] bit_count = 0;
    reg [3:0] frame_count = 0;
    wire bit_count_max;
    wire frame_tick;
    wire cs;


    always @(negedge clk) begin
        if (bit_count_max)
            bit_count <= 0;
        else
            bit_count = bit_count + 1;     
    end


    assign bit_count_max = (bit_count == (CYCLE_WIDTH - 1)) ? 1'b1 : 1'b0;

    assign frame_tick = (bit_count == (CYCLE_WIDTH - 2)) ? 1'b1 : 1'b0;
    assign cs = (bit_count < (CYCLE_WIDTH - 1)) ? 1'b1 : 1'b0;
    
    always @(negedge clk) begin
        if (frame_tick)
            frame_count <= frame_count + 1;
    end

    wire [15:0] rom_out;
    
    rom u1 (.a(frame_count), .d(rom_out));
        
    reg [FRAME_SIZE-2:0] shift = {FRAME_SIZE-1{1'b0}};
    reg                  dout = 1'b0;
 
    always @(negedge clk) begin
       if (bit_count_max) begin
          shift <= rom_out[FRAME_SIZE-2:0];
          dout    <= rom_out[FRAME_SIZE-1];
       end
       else begin
          shift <= {shift[FRAME_SIZE-3:0], 1'b0};
          dout   <= shift[FRAME_SIZE-2];
       end
    end
    
    assign bcount = bit_count;
    assign a = frame_count;
    assign cs_n = ~cs;
    assign d = dout;

endmodule