data/full_repos/permissive/162106151/rom_test/rom_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/162106151/rom_test/rom_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/162106151/rom_test/rom_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n #1000 rst = 1;\n ^\n%Error: data/full_repos/permissive/162106151/rom_test/rom_tb.v:17: Cannot find file containing module: \'rom_test\'\nrom_test u0 (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162106151/rom_test,data/full_repos/permissive/162106151/rom_test\n             data/full_repos/permissive/162106151/rom_test,data/full_repos/permissive/162106151/rom_test.v\n             data/full_repos/permissive/162106151/rom_test,data/full_repos/permissive/162106151/rom_test.sv\n             rom_test\n             rom_test.v\n             rom_test.sv\n             obj_dir/rom_test\n             obj_dir/rom_test.v\n             obj_dir/rom_test.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rom_tb;

reg clk, rst;
wire [7:0] led;

initial begin
	clk = 0;
	forever #10 clk = ~clk;
end

initial begin
	rst = 0;
	#1000 rst = 1;
end

rom_test u0 (
	.clk(clk),
	.resetn(rst),

	.led(led)
);


endmodule
module rom_tb;


reg clk, rst;
wire [7:0] led;

initial begin
	clk = 0;
	forever #10 clk = ~clk;
end

initial begin
	rst = 0;
	#1000 rst = 1;
end

rom_test u0 (
	.clk(clk),
	.resetn(rst),

	.led(led)
);


endmodule