data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:57: Cell has missing pin: \'clk1_out\'\n  pll_test u_pll_test (\n           ^~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:57: Cell has missing pin: \'clk2_out\'\n  pll_test u_pll_test (\n           ^~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:225: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg0 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:231: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:237: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg2 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:439: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg0 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:445: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:569: Cell has missing pin: \'en\'\n  reg_ar_as_w13 reg0 (\n                ^~~~\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:601: Cannot find file containing module: \'EG_LOGIC_BUFG\'\n  EG_LOGIC_BUFG bufg_feedback (\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.v\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.sv\n             EG_LOGIC_BUFG\n             EG_LOGIC_BUFG.v\n             EG_LOGIC_BUFG.sv\n             obj_dir/EG_LOGIC_BUFG\n             obj_dir/EG_LOGIC_BUFG.v\n             obj_dir/EG_LOGIC_BUFG.sv\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:604: Cannot find file containing module: \'EG_PHY_PLL\'\n  EG_PHY_PLL #(\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module pll_test
  (
  refclk,
  reset,
  clk0_out,
  clk1_out,
  clk2_out,
  extlock
  );

  input refclk;
  input reset;
  output clk0_out;
  output clk1_out;
  output clk2_out;
  output extlock;

  wire clk0_buf;

  EG_LOGIC_BUFG bufg_feedback (
    .i(clk0_buf),
    .o(clk0_out));
  EG_PHY_PLL #(
    .CLKC0_CPHASE(39),
    .CLKC0_DIV(40),
    .CLKC0_DIV2_ENABLE("DISABLE"),
    .CLKC0_ENABLE("ENABLE"),
    .CLKC0_FPHASE(0),
    .CLKC1_CPHASE(19),
    .CLKC1_DIV(20),
    .CLKC1_DIV2_ENABLE("DISABLE"),
    .CLKC1_ENABLE("ENABLE"),
    .CLKC1_FPHASE(0),
    .CLKC2_CPHASE(9),
    .CLKC2_DIV(10),
    .CLKC2_DIV2_ENABLE("DISABLE"),
    .CLKC2_ENABLE("ENABLE"),
    .CLKC2_FPHASE(0),
    .CLKC3_CPHASE(1),
    .CLKC3_DIV(1),
    .CLKC3_DIV2_ENABLE("DISABLE"),
    .CLKC3_ENABLE("DISABLE"),
    .CLKC3_FPHASE(0),
    .CLKC4_CPHASE(1),
    .CLKC4_DIV(1),
    .CLKC4_DIV2_ENABLE("DISABLE"),
    .CLKC4_ENABLE("DISABLE"),
    .CLKC4_FPHASE(0),
    .DERIVE_PLL_CLOCKS("DISABLE"),
    .DPHASE_SOURCE("DISABLE"),
    .DYNCFG("DISABLE"),
    .FBCLK_DIV(1),
    .FEEDBK_MODE("NORMAL"),
    .FEEDBK_PATH("CLKC0_EXT"),
    .FIN("25.000"),
    .FREQ_LOCK_ACCURACY(2),
    .GEN_BASIC_CLOCK("DISABLE"),
    .GMC_GAIN(6),
    .GMC_TEST(14),
    .ICP_CURRENT(3),
    .IF_ESCLKSTSW("DISABLE"),
    .INTFB_WAKE("DISABLE"),
    .KVCO(6),
    .LPF_CAPACITOR(3),
    .LPF_RESISTOR(2),
    .NORESET("DISABLE"),
    .ODIV_MUXC0("DIV"),
    .ODIV_MUXC1("DIV"),
    .ODIV_MUXC2("DIV"),
    .ODIV_MUXC3("DIV"),
    .ODIV_MUXC4("DIV"),
    .PLLC2RST_ENA("DISABLE"),
    .PLLC34RST_ENA("DISABLE"),
    .PLLMRST_ENA("DISABLE"),
    .PLLRST_ENA("ENABLE"),
    .PLL_LOCK_MODE(0),
    .PREDIV_MUXC0("VCO"),
    .PREDIV_MUXC1("VCO"),
    .PREDIV_MUXC2("VCO"),
    .PREDIV_MUXC3("VCO"),
    .PREDIV_MUXC4("VCO"),
    .REFCLK_DIV(1),
    .REFCLK_SEL("INTERNAL"),
    .STDBY_ENABLE("DISABLE"),
    .STDBY_VCO_ENA("DISABLE"),
    .SYNC_ENABLE("DISABLE"),
    .VCO_NORESET("DISABLE"))
    pll_inst (
    .daddr(6'b000000),
    .dclk(1'b0),
    .dcs(1'b0),
    .di(8'b00000000),
    .dwe(1'b0),
    .fbclk(clk0_out),
    .psclk(1'b0),
    .psclksel(3'b000),
    .psdown(1'b0),
    .psstep(1'b0),
    .refclk(refclk),
    .reset(reset),
    .stdby(1'b0),
    .clkc({open_n0,open_n1,clk2_out,clk1_out,clk0_buf}),
    .extlock(extlock));

endmodule
module pll_test
  (
  refclk,
  reset,
  clk0_out,
  clk1_out,
  clk2_out,
  extlock
  );


  input refclk;
  input reset;
  output clk0_out;
  output clk1_out;
  output clk2_out;
  output extlock;

  wire clk0_buf;

  EG_LOGIC_BUFG bufg_feedback (
    .i(clk0_buf),
    .o(clk0_out));
  EG_PHY_PLL #(
    .CLKC0_CPHASE(39),
    .CLKC0_DIV(40),
    .CLKC0_DIV2_ENABLE("DISABLE"),
    .CLKC0_ENABLE("ENABLE"),
    .CLKC0_FPHASE(0),
    .CLKC1_CPHASE(19),
    .CLKC1_DIV(20),
    .CLKC1_DIV2_ENABLE("DISABLE"),
    .CLKC1_ENABLE("ENABLE"),
    .CLKC1_FPHASE(0),
    .CLKC2_CPHASE(9),
    .CLKC2_DIV(10),
    .CLKC2_DIV2_ENABLE("DISABLE"),
    .CLKC2_ENABLE("ENABLE"),
    .CLKC2_FPHASE(0),
    .CLKC3_CPHASE(1),
    .CLKC3_DIV(1),
    .CLKC3_DIV2_ENABLE("DISABLE"),
    .CLKC3_ENABLE("DISABLE"),
    .CLKC3_FPHASE(0),
    .CLKC4_CPHASE(1),
    .CLKC4_DIV(1),
    .CLKC4_DIV2_ENABLE("DISABLE"),
    .CLKC4_ENABLE("DISABLE"),
    .CLKC4_FPHASE(0),
    .DERIVE_PLL_CLOCKS("DISABLE"),
    .DPHASE_SOURCE("DISABLE"),
    .DYNCFG("DISABLE"),
    .FBCLK_DIV(1),
    .FEEDBK_MODE("NORMAL"),
    .FEEDBK_PATH("CLKC0_EXT"),
    .FIN("25.000"),
    .FREQ_LOCK_ACCURACY(2),
    .GEN_BASIC_CLOCK("DISABLE"),
    .GMC_GAIN(6),
    .GMC_TEST(14),
    .ICP_CURRENT(3),
    .IF_ESCLKSTSW("DISABLE"),
    .INTFB_WAKE("DISABLE"),
    .KVCO(6),
    .LPF_CAPACITOR(3),
    .LPF_RESISTOR(2),
    .NORESET("DISABLE"),
    .ODIV_MUXC0("DIV"),
    .ODIV_MUXC1("DIV"),
    .ODIV_MUXC2("DIV"),
    .ODIV_MUXC3("DIV"),
    .ODIV_MUXC4("DIV"),
    .PLLC2RST_ENA("DISABLE"),
    .PLLC34RST_ENA("DISABLE"),
    .PLLMRST_ENA("DISABLE"),
    .PLLRST_ENA("ENABLE"),
    .PLL_LOCK_MODE(0),
    .PREDIV_MUXC0("VCO"),
    .PREDIV_MUXC1("VCO"),
    .PREDIV_MUXC2("VCO"),
    .PREDIV_MUXC3("VCO"),
    .PREDIV_MUXC4("VCO"),
    .REFCLK_DIV(1),
    .REFCLK_SEL("INTERNAL"),
    .STDBY_ENABLE("DISABLE"),
    .STDBY_VCO_ENA("DISABLE"),
    .SYNC_ENABLE("DISABLE"),
    .VCO_NORESET("DISABLE"))
    pll_inst (
    .daddr(6'b000000),
    .dclk(1'b0),
    .dcs(1'b0),
    .di(8'b00000000),
    .dwe(1'b0),
    .fbclk(clk0_out),
    .psclk(1'b0),
    .psclksel(3'b000),
    .psdown(1'b0),
    .psstep(1'b0),
    .refclk(refclk),
    .reset(reset),
    .stdby(1'b0),
    .clkc({open_n0,open_n1,clk2_out,clk1_out,clk0_buf}),
    .extlock(extlock));

endmodule