data/full_repos/permissive/146073027/Simple 32bit integer ALU.v
 line:28: before: "assign"
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/146073027/Simple\n        ... Looked in:\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.sv\n             data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027/Simple.sv\n             obj_dir/data/full_repos/permissive/146073027/Simple\n             obj_dir/data/full_repos/permissive/146073027/Simple.v\n             obj_dir/data/full_repos/permissive/146073027/Simple.sv\n%Error: Cannot find file containing module: 32bit\n%Error: Cannot find file containing module: integer\n%Error: Cannot find file containing module: ALU.v\n%Error: Exiting due to 4 error(s)\n'
module thirty_two_bit_comparator(out4,in1,in2);
  output [3:0]out4;
  wire out1,out2,out3;
  input [31:0]in1,in2;
  wire t1,t2,t3,t4,t5,t6,t7,t8,x1,x2,x3;
  wire s1[0:2];
  wire s2[0:2];
  wire s3;
  
  eight_bit_comparator ebc0(t1,t2,in1[31:24],in2[31:24],1);
  xnor(x1,t1,t2);
  eight_bit_comparator ebc1(t3,t4,in1[23:16],in2[23:16],x1);
  xnor(x2,t3,t4);
  eight_bit_comparator ebc2(t5,t6,in1[15:8],in2[15:8],x2);
  xnor(x3,t5,t6);
  eight_bit_comparator ebc3(t7,t8,in1[7:0],in2[7:0],x3);
  
  one_bit_fa ob0(s3,s1[0],0,t1,t3);
  one_bit_fa ob1(s3,s1[1],0,s1[0],t5);
  one_bit_fa ob2(s3,s1[2],0,s1[1],t7);
  one_bit_fa ob3(s3,s2[0],0,t2,t4);
  one_bit_fa ob4(s3,s2[1],0,s2[0],t6);
  one_bit_fa ob5(s3,s2[2],0,s2[1],t8);
  assign out1=s1[2];
  assign out2=s2[2];
  and(out3,~out2,~out1);
  assign out4={out1,out2,out3};
endmodule
module thirty_two_bit_comparator(out4,in1,in2);

  output [3:0]out4;
  wire out1,out2,out3;
  input [31:0]in1,in2;
  wire t1,t2,t3,t4,t5,t6,t7,t8,x1,x2,x3;
  wire s1[0:2];
  wire s2[0:2];
  wire s3;
  
  eight_bit_comparator ebc0(t1,t2,in1[31:24],in2[31:24],1);
  xnor(x1,t1,t2);
  eight_bit_comparator ebc1(t3,t4,in1[23:16],in2[23:16],x1);
  xnor(x2,t3,t4);
  eight_bit_comparator ebc2(t5,t6,in1[15:8],in2[15:8],x2);
  xnor(x3,t5,t6);
  eight_bit_comparator ebc3(t7,t8,in1[7:0],in2[7:0],x3);
  
  one_bit_fa ob0(s3,s1[0],0,t1,t3);
  one_bit_fa ob1(s3,s1[1],0,s1[0],t5);
  one_bit_fa ob2(s3,s1[2],0,s1[1],t7);
  one_bit_fa ob3(s3,s2[0],0,t2,t4);
  one_bit_fa ob4(s3,s2[1],0,s2[0],t6);
  one_bit_fa ob5(s3,s2[2],0,s2[1],t8);
  assign out1=s1[2];
  assign out2=s2[2];
  and(out3,~out2,~out1);
  assign out4={out1,out2,out3};
endmodule