data/full_repos/permissive/193419875/src/DataMemoryMUX.v
data/verilator_xmls/f4262917-3b49-46dc-805a-a33d763f178b.xml
module DataMemoryMUX
(
	input [63:0] readData,
	input [63:0] ALUresult,
	input memToReg,
	output reg [63:0] dataMemoryMUXout
);

	always @(*) case (memToReg)
		0: dataMemoryMUXout = ALUresult;
		1: dataMemoryMUXout = readData;
		default: dataMemoryMUXout = ALUresult;
	endcase
endmodule
module DataMemoryMUX
(
	input [63:0] readData,
	input [63:0] ALUresult,
	input memToReg,
	output reg [63:0] dataMemoryMUXout
);


	always @(*) case (memToReg)
		0: dataMemoryMUXout = ALUresult;
		1: dataMemoryMUXout = readData;
		default: dataMemoryMUXout = ALUresult;
	endcase
endmodule