data/full_repos/permissive/207835546/Multiplexer/Mux_struc/mux_tb.v
1: b'%Error: data/full_repos/permissive/207835546/Multiplexer/Mux_struc/mux_tb.v:3: Cannot find include file: mux_str.v\n`include "mux_str.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207835546/Multiplexer/Mux_struc,data/full_repos/permissive/207835546/mux_str.v\n             data/full_repos/permissive/207835546/Multiplexer/Mux_struc,data/full_repos/permissive/207835546/mux_str.v.v\n             data/full_repos/permissive/207835546/Multiplexer/Mux_struc,data/full_repos/permissive/207835546/mux_str.v.sv\n             mux_str.v\n             mux_str.v.v\n             mux_str.v.sv\n             obj_dir/mux_str.v\n             obj_dir/mux_str.v.v\n             obj_dir/mux_str.v.sv\n%Error: data/full_repos/permissive/207835546/Multiplexer/Mux_struc/mux_tb.v:35: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("mux_out.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/207835546/Multiplexer/Mux_struc/mux_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,mux8to1_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/207835546/Multiplexer/Mux_struc/mux_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/207835546/Multiplexer/Mux_struc/mux_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #20 Sel = count;\n    ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module mux8to1_tb;




 reg [2:0] Sel;

 reg [7:0] a;





 wire Out;

 



 reg [2:0] count = 3'd0;

 



 mux_str m1 (.out(Out),.sel(Sel),.a(a));


 initial begin
 
	$dumpfile("mux_out.vcd");
	$dumpvars(0,mux8to1_tb);





  #100;

        



  Sel = 3'd0;

  a = 8'b10101111;

  


  for (count = 0; count < 8; count = count + 1'b1)

  begin

    #20 Sel = count;

  end

 end      

endmodule
module mux8to1_tb;





 reg [2:0] Sel;

 reg [7:0] a;





 wire Out;

 



 reg [2:0] count = 3'd0;

 



 mux_str m1 (.out(Out),.sel(Sel),.a(a));


 initial begin
 
	$dumpfile("mux_out.vcd");
	$dumpvars(0,mux8to1_tb);





  #100;

        



  Sel = 3'd0;

  a = 8'b10101111;

  


  for (count = 0; count < 8; count = count + 1'b1)

  begin

    #20 Sel = count;

  end

 end      

endmodule