data/full_repos/permissive/169496369/mux2x1.v
data/verilator_xmls/d6235e25-4b5c-4e0b-9d47-f9966bccb7f0.xml
module mux2x1(a, b, s, o);
    input [7:0] a, b;
    input s;
    
    output logic [7:0]o;
    
    assign o = s ? b : a;
endmodule
module mux2x1(a, b, s, o);

    input [7:0] a, b;
    input s;
    
    output logic [7:0]o;
    
    assign o = s ? b : a;
endmodule