data/full_repos/permissive/160437780/Source/Top.v
 line:119: before: "898"
1: b'%Error: data/full_repos/permissive/160437780/Source/Top.v:30: Cannot find file containing module: \'color\'\n    color Run(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/160437780/Source,data/full_repos/permissive/160437780/color\n             data/full_repos/permissive/160437780/Source,data/full_repos/permissive/160437780/color.v\n             data/full_repos/permissive/160437780/Source,data/full_repos/permissive/160437780/color.sv\n             color\n             color.v\n             color.sv\n             obj_dir/color\n             obj_dir/color.v\n             obj_dir/color.sv\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/Top.v:93: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                    : ... In instance Top\n            case(ColorOut)\n            ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/Top.v:93: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h0\' generates 3 bits.\n                                                                    : ... In instance Top\n            case(ColorOut)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/Top.v:93: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h1\' generates 3 bits.\n                                                                    : ... In instance Top\n            case(ColorOut)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/Top.v:93: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h2\' generates 3 bits.\n                                                                    : ... In instance Top\n            case(ColorOut)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/Top.v:93: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h3\' generates 3 bits.\n                                                                    : ... In instance Top\n            case(ColorOut)\n            ^~~~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module Top(
    input clk,

    input Pulse,

    input Clear,
    output reg [3:0] ColorDis,
    output reg S2,
    output reg S3


    );
   
    wire ColorS2;
    wire ColorS3;


    wire [7:0] ColorOut;
    wire [7:0] RedDiv;
    wire [7:0] BlueDiv;
    wire [7:0] GreenDiv;
    reg [7:0] ColorPerc;
    reg RunSample = 0;

    wire TestDone;
   
    
    color Run(
        .Selector1(ColorS2),
        .Selector2(ColorS3),

        .Run(RunSample),
        .RedDiv(RedDiv),
        .BlueDiv(BlueDiv),
        .GreenDiv(GreenDiv),
        .TestDone(TestDone),
        .clk(clk),
        .Pulse(Pulse)
    );
    







    
    
    always @(posedge clk)
    begin
        S2 = ColorS2;
        S3 = ColorS3;


    end
    
    always @(posedge clk)
    begin
        if (1)
        begin 
            RunSample = 1;
        end
        if (Clear)
        begin
            RunSample = 0;
        end
    end
    
    always @(posedge clk)
    begin


















            ColorPerc <= 0;
            case(ColorOut)
            3'b100:
            begin
                ColorDis <= 4;
            end
            3'b000:
            begin
                ColorDis <= 0;
            end    
            3'b001:
            begin
                ColorDis <= 1;
            end
            3'b010:
            begin
                ColorDis <= 2;
            end
            3'b011:
            begin
            ColorDis <= 3;
            end
            endcase
        end

        
endmodule
module Top(
    input clk,

    input Pulse,

    input Clear,
    output reg [3:0] ColorDis,
    output reg S2,
    output reg S3


    );

   
    wire ColorS2;
    wire ColorS3;


    wire [7:0] ColorOut;
    wire [7:0] RedDiv;
    wire [7:0] BlueDiv;
    wire [7:0] GreenDiv;
    reg [7:0] ColorPerc;
    reg RunSample = 0;

    wire TestDone;
   
    
    color Run(
        .Selector1(ColorS2),
        .Selector2(ColorS3),

        .Run(RunSample),
        .RedDiv(RedDiv),
        .BlueDiv(BlueDiv),
        .GreenDiv(GreenDiv),
        .TestDone(TestDone),
        .clk(clk),
        .Pulse(Pulse)
    );
    







    
    
    always @(posedge clk)
    begin
        S2 = ColorS2;
        S3 = ColorS3;


    end
    
    always @(posedge clk)
    begin
        if (1)
        begin 
            RunSample = 1;
        end
        if (Clear)
        begin
            RunSample = 0;
        end
    end
    
    always @(posedge clk)
    begin


















            ColorPerc <= 0;
            case(ColorOut)
            3'b100:
            begin
                ColorDis <= 4;
            end
            3'b000:
            begin
                ColorDis <= 0;
            end    
            3'b001:
            begin
                ColorDis <= 1;
            end
            3'b010:
            begin
                ColorDis <= 2;
            end
            3'b011:
            begin
            ColorDis <= 3;
            end
            endcase
        end

        
endmodule