data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/lut6.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/c96777c5-fa33-4fbf-8760-6327bc42841b.xml
module lut6 (
input [5:0] in,
output out,
input [63:0] sram,
input [63:0] sram_inv);

  assign out = sram[in];

endmodule
module lut6 (
input [5:0] in,
output out,
input [63:0] sram,
input [63:0] sram_inv);


  assign out = sram[in];

endmodule