data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/syscon.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/syscon.v:40: Unsupported: Ignoring delay on this delayed statement.\n   #20 rst     <= 1\'b0;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/syscon.v:46: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module syscon(
   output logic clk_o,
   output logic rst_o
);

logic clk, rst;

initial begin
   clk         <= 1'b0;
   rst         <= 1'b1;
   #20 rst     <= 1'b0;
end




always #5 clk = ~clk;


assign clk_o = clk;
assign rst_o = rst;

endmodule
module syscon(
   output logic clk_o,
   output logic rst_o
);


logic clk, rst;

initial begin
   clk         <= 1'b0;
   rst         <= 1'b1;
   #20 rst     <= 1'b0;
end




always #5 clk = ~clk;


assign clk_o = clk;
assign rst_o = rst;

endmodule