data/full_repos/permissive/143278/ivltests/pr1948110.v
 line:11: before: "assign"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1948110.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1948110.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1948110.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1948110.v:11: Operator ITORD expects 32 bits on the LHS, but LHS\'s AND generates 1 bits.\n                                                                         : ... In instance top\n    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1948110.v:11: Operator ITORD expects 32 bits on the LHS, but LHS\'s AND generates 1 bits.\n                                                                         : ... In instance top\n    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1948110.v:21: Operator ITORD expects 32 bits on the LHS, but LHS\'s AND generates 1 bits.\n                                                                         : ... In instance top\n    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1948110.v:21: Operator ITORD expects 32 bits on the LHS, but LHS\'s AND generates 1 bits.\n                                                                         : ... In instance top\n    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1948110.v:30: Operator ITORD expects 32 bits on the LHS, but LHS\'s AND generates 1 bits.\n                                                                         : ... In instance top\n    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1948110.v:30: Operator ITORD expects 32 bits on the LHS, but LHS\'s AND generates 1 bits.\n                                                                         : ... In instance top\n    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));\n                                        ^\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass = 1'b1;
  reg a, b;
  real c, d;

  initial begin
    c = 0.0;
    d = 1.0;
    a = 1'b0;
    b = 1'b0;
    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));

    #1;
    if (c != 3.0) begin
      $display("FAILED, expected 3.0, got %f", c);
      pass = 1'b0;
    end

    a = 1'b1;
    b = 1'b0;
    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));
    #1;
    if (c != 2.0) begin
      $display("FAILED, expected 2.0, got %f", c);
      pass = 1'b0;
    end

    a = 1'b0;
    b = 1'b1;
    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));
    #1;
    if (c != 6.0) begin
      $display("FAILED, expected 6.0, got %f", c);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass = 1'b1;
  reg a, b;
  real c, d;

  initial begin
    c = 0.0;
    d = 1.0;
    a = 1'b0;
    b = 1'b0;
    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));

    #1;
    if (c != 3.0) begin
      $display("FAILED, expected 3.0, got %f", c);
      pass = 1'b0;
    end

    a = 1'b1;
    b = 1'b0;
    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));
    #1;
    if (c != 2.0) begin
      $display("FAILED, expected 2.0, got %f", c);
      pass = 1'b0;
    end

    a = 1'b0;
    b = 1'b1;
    assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));
    #1;
    if (c != 6.0) begin
      $display("FAILED, expected 6.0, got %f", c);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule