data/full_repos/permissive/18921956/template/Testbench.v
 line:33: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/18921956/template/Testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #0 rst_n = 1\'b0; clk = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/18921956/template/Testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #20 rst_n = 1\'b1; in = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/template/Testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #20 $display ("Simulate DesignName");\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/template/Testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #20 in = inputArr[i];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/template/Testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #40 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/template/Testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Error: data/full_repos/permissive/18921956/template/Testbench.v:13: Cannot find file containing module: \'DesignName\'\nDesignName DesignInstance(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18921956/template,data/full_repos/permissive/18921956/DesignName\n             data/full_repos/permissive/18921956/template,data/full_repos/permissive/18921956/DesignName.v\n             data/full_repos/permissive/18921956/template,data/full_repos/permissive/18921956/DesignName.sv\n             DesignName\n             DesignName.v\n             DesignName.sv\n             obj_dir/DesignName\n             obj_dir/DesignName.v\n             obj_dir/DesignName.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestBench;
reg in;
reg clk, rst_n;
wire out;

DesignName DesignInstance(
    out,
    in,
    clk,
    rst_n
);

initial begin
    #0 rst_n = 1'b0; clk = 1'b0;
    #20 rst_n = 1'b1; in = 1'b0;
    $display ("====================================================================");
    $display ("Time %t", $time);
    $display ("rst_n = %b\tin = %b\tout = %b",
                    rst_n, in, out);
    $display ("====================================================================");
end

wire [17:0] inputArr = 18'b0111_0001_0011_1110_00;
integer i;
initial begin
    #20 $display ("Simulate DesignName");
    for (i = 17; i >= 0; i = i - 1) begin
        #20 in = inputArr[i];
        $display ("====================================================================");
        $display ("Time %t", $time);
        $display ("rst_n = %b\tin = %b\tout = %b",
                        rst_n, in, out);
        $display ("====================================================================");
    end

    #40 $finish;
end

always begin
    #10 clk = ~clk;
end

endmodule
module TestBench;

reg in;
reg clk, rst_n;
wire out;

DesignName DesignInstance(
    out,
    in,
    clk,
    rst_n
);

initial begin
    #0 rst_n = 1'b0; clk = 1'b0;
    #20 rst_n = 1'b1; in = 1'b0;
    $display ("====================================================================");
    $display ("Time %t", $time);
    $display ("rst_n = %b\tin = %b\tout = %b",
                    rst_n, in, out);
    $display ("====================================================================");
end

wire [17:0] inputArr = 18'b0111_0001_0011_1110_00;
integer i;
initial begin
    #20 $display ("Simulate DesignName");
    for (i = 17; i >= 0; i = i - 1) begin
        #20 in = inputArr[i];
        $display ("====================================================================");
        $display ("Time %t", $time);
        $display ("rst_n = %b\tin = %b\tout = %b",
                        rst_n, in, out);
        $display ("====================================================================");
    end

    #40 $finish;
end

always begin
    #10 clk = ~clk;
end

endmodule