data/full_repos/permissive/125927162/UART/UART_tb.v
 line:80: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk = !clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/125927162/UART/UART_tb.v:62: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("UART.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/UART/UART_tb.v:63: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, TX);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/UART/UART_tb.v:64: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, RX);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #2\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n      #2\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n      #16\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n      #400\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n      #16\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n      #400\n      ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_tb();

   localparam BITS = 8;
   localparam STOPBITS = 1;
   localparam PARITY = 2;
   localparam DUMMYDATA_A = 8'b01010101;
   localparam DUMMYDATA_B = 8'b11001100;
   
   reg clk;
   reg rst;
   reg data_ready;

   
   wire rxtx;
   wire data_sent;
   wire rx_data_ready;
   
   reg [BITS - 1:0] txdata;
   wire [BITS - 1:0] rxdata;
   
   UART_TX #(.BITS(BITS),
	     .STOPBITS(STOPBITS),
	     .PARITY(PARITY))
   TX(
      .clk(clk),
      .rst(rst),
      .tx(rxtx),
      .data_ready(data_ready),
      .data(txdata),
      .data_sent(data_sent)
      );

   UART_RX #(.BITS(BITS),
	     .STOPBITS(STOPBITS),
	     .PARITY(PARITY))
   RX(
      .clk(clk),
      .rst(rst),
      .rx(rxtx),
      .data(rxdata),
      .data_ready(rx_data_ready)
      );

   always #1 clk = !clk;
   
   initial begin
      $dumpfile("UART.vcd");
      $dumpvars(0, TX);
      $dumpvars(0, RX);
      clk = 0;
      rst = 1;
      txdata = DUMMYDATA_A;
      #2
	rst = 0;
      #2
	data_ready = 1;
      #16
	data_ready = 0;
      #400
	txdata = DUMMYDATA_B;
        data_ready = 1;
      #16
	data_ready = 0;
      #400
      $finish;   
   end

endmodule
module UART_tb();


   localparam BITS = 8;
   localparam STOPBITS = 1;
   localparam PARITY = 2;
   localparam DUMMYDATA_A = 8'b01010101;
   localparam DUMMYDATA_B = 8'b11001100;
   
   reg clk;
   reg rst;
   reg data_ready;

   
   wire rxtx;
   wire data_sent;
   wire rx_data_ready;
   
   reg [BITS - 1:0] txdata;
   wire [BITS - 1:0] rxdata;
   
   UART_TX #(.BITS(BITS),
	     .STOPBITS(STOPBITS),
	     .PARITY(PARITY))
   TX(
      .clk(clk),
      .rst(rst),
      .tx(rxtx),
      .data_ready(data_ready),
      .data(txdata),
      .data_sent(data_sent)
      );

   UART_RX #(.BITS(BITS),
	     .STOPBITS(STOPBITS),
	     .PARITY(PARITY))
   RX(
      .clk(clk),
      .rst(rst),
      .rx(rxtx),
      .data(rxdata),
      .data_ready(rx_data_ready)
      );

   always #1 clk = !clk;
   
   initial begin
      $dumpfile("UART.vcd");
      $dumpvars(0, TX);
      $dumpvars(0, RX);
      clk = 0;
      rst = 1;
      txdata = DUMMYDATA_A;
      #2
	rst = 0;
      #2
	data_ready = 1;
      #16
	data_ready = 0;
      #400
	txdata = DUMMYDATA_B;
        data_ready = 1;
      #16
	data_ready = 0;
      #400
      $finish;   
   end

endmodule