data/full_repos/permissive/111258339/test/Datapath/alu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/111258339/test/Datapath/alu_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk<=~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111258339/test/Datapath/alu_tb.v:39: Cannot find file containing module: \'alu\'\n  alu alu0(\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/alu\n             data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/alu.v\n             data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb();
  `timescale  1ns/1ps
  
  reg clk;
  
  reg [31:0] num_1;
  reg [31:0] num_2;
  reg [1:0] ALUOp;
  reg Zero_output;
  reg[31:0] result_output;
  
  wire Zero;
  wire[31:0] result;
  
  integer fd;

  initial
  begin
    clk = 1;
    
    num_1 = 32'b0;
    num_2 = 32'b0;
    ALUOp = 2'b0;
    Zero_output = 1;
    result_output = 32'b0;
    
    fd=$fopen("test/data/Datapath/alu_td.txt","r");
  end
  
  always
    #1 clk<=~clk;
  
  alu alu0(
    .num_1(num_1),
    .num_2(num_2),
    .ALUOp(ALUOp),
    .Zero(Zero),
    .result(result)
  );
  
  always@(posedge clk)
  
  begin
    if (result != result_output)
      begin
        $display("testcase failed! result: %x, result_data: %x", result, result_output);
        $stop;
      end
    if (Zero != Zero_output)
      begin
        $display("testcase failed! Zero: %x, Zero_output: %x", Zero, Zero_output);
        $stop;
      end
    
    $fscanf(
      fd, "0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t", 
      num_1, num_2, ALUOp, Zero_output, result_output
    );
    
    $display(
      "testcase: 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t",
      num_1, num_2, ALUOp, Zero, Zero_output, result, result_output
    );
    
    if ($feof(fd))
    begin
      $fclose(fd);
      $display("pass!");
      $stop;
    end
  end
  
endmodule
module alu_tb();

  `timescale  1ns/1ps
  
  reg clk;
  
  reg [31:0] num_1;
  reg [31:0] num_2;
  reg [1:0] ALUOp;
  reg Zero_output;
  reg[31:0] result_output;
  
  wire Zero;
  wire[31:0] result;
  
  integer fd;

  initial
  begin
    clk = 1;
    
    num_1 = 32'b0;
    num_2 = 32'b0;
    ALUOp = 2'b0;
    Zero_output = 1;
    result_output = 32'b0;
    
    fd=$fopen("test/data/Datapath/alu_td.txt","r");
  end
  
  always
    #1 clk<=~clk;
  
  alu alu0(
    .num_1(num_1),
    .num_2(num_2),
    .ALUOp(ALUOp),
    .Zero(Zero),
    .result(result)
  );
  
  always@(posedge clk)
  
  begin
    if (result != result_output)
      begin
        $display("testcase failed! result: %x, result_data: %x", result, result_output);
        $stop;
      end
    if (Zero != Zero_output)
      begin
        $display("testcase failed! Zero: %x, Zero_output: %x", Zero, Zero_output);
        $stop;
      end
    
    $fscanf(
      fd, "0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t", 
      num_1, num_2, ALUOp, Zero_output, result_output
    );
    
    $display(
      "testcase: 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t",
      num_1, num_2, ALUOp, Zero, Zero_output, result, result_output
    );
    
    if ($feof(fd))
    begin
      $fclose(fd);
      $display("pass!");
      $stop;
    end
  end
  
endmodule