data/full_repos/permissive/112626266/new_decode_stage.v
1: b'%Warning-WIDTH: data/full_repos/permissive/112626266/new_decode_stage.v:57: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                          : ... In instance decode\n        DataB <= IDinst[10:6];\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/112626266/new_decode_stage.v:65: Cannot find file containing module: \'HazardUnit\'\n  HazardUnit HU(readReg1,readReg2,EXRegRt,ExMemStall,PCWrite,IFIDWrite,HazMuxCon);\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/HazardUnit\n             data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/HazardUnit.v\n             data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/HazardUnit.sv\n             HazardUnit\n             HazardUnit.v\n             HazardUnit.sv\n             obj_dir/HazardUnit\n             obj_dir/HazardUnit.v\n             obj_dir/HazardUnit.sv\n%Error: data/full_repos/permissive/112626266/new_decode_stage.v:67: Cannot find file containing module: \'Control\'\nControl thecontrol(IDinst[31:26],ConOut);\n^~~~~~~\n%Error: data/full_repos/permissive/112626266/new_decode_stage.v:70: Cannot find file containing module: \'RegFile\'\nRegFile rf(DataA,DataB_,readReg1,readReg2,WBRegRd,datatowirte,WBWB[0],clock);\n^~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module decode (clock,WBRegRd,WBWB,EXM,EXRegRt,datatowirte,IDpc_plus_4,IDinst,WB,M,EX,IDRegRs,IDRegRt,IDRegRd,DataA,DataB,imm_value,BranchAddr,brunch_taken,brunch_control ,PCWrite,IFIDWrite);


input clock ;
input [31:0] IDpc_plus_4,IDinst; 

input [2:0]EXM;
input [4:0]EXRegRt;

input [4:0]WBRegRd;
input [1:0] WBWB;
input [31:0] datatowirte;

output [1:0]WB;
output [2:0]M;
output [3:0]EX;
output [4:0]IDRegRs,IDRegRt,IDRegRd;
output [31:0]DataA,imm_value;
output reg [31:0] DataB;

output [31:0] BranchAddr ;
output brunch_taken,brunch_control,PCWrite,IFIDWrite;

 


assign IDRegRs[4:0]=IDinst[25:21]; 
assign IDRegRt[4:0]=IDinst[20:16]; 
assign IDRegRd[4:0]=IDinst[15:11]; 


assign imm_value ={IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15:0]}; 


assign BranchAddr = (imm_value << 2) + IDpc_plus_4;


wire [8:0] IDcontrol,ConOut;
wire HazMuxCon;

assign IDcontrol = HazMuxCon?ConOut:0;

reg [4:0] readReg1, readReg2;
wire signed [31:0] DataB_;
always @(*) begin
    if ((IDinst[31:26] == 0) && (IDinst[5:0] == 0)) begin
        readReg1 <= IDinst[20:16];
        readReg2 <= 0;
        DataB <= IDinst[10:6];
    end else begin
        readReg1 <= IDinst[25:21];
        readReg2 <= IDinst[20:16];
        DataB <= DataB_;
    end
end
wire ExMemStall = EXM[0] | EXM[1];
  HazardUnit HU(readReg1,readReg2,EXRegRt,ExMemStall,PCWrite,IFIDWrite,HazMuxCon);

Control thecontrol(IDinst[31:26],ConOut);


RegFile rf(DataA,DataB_,readReg1,readReg2,WBRegRd,datatowirte,WBWB[0],clock);

assign brunch_taken=(DataA==DataB)?1:0;
assign brunch_control=IDcontrol[6];

assign WB=IDcontrol[8:7];
assign M=IDcontrol[6:4];
assign EX=IDcontrol[3:0];

endmodule
module decode (clock,WBRegRd,WBWB,EXM,EXRegRt,datatowirte,IDpc_plus_4,IDinst,WB,M,EX,IDRegRs,IDRegRt,IDRegRd,DataA,DataB,imm_value,BranchAddr,brunch_taken,brunch_control ,PCWrite,IFIDWrite);



input clock ;
input [31:0] IDpc_plus_4,IDinst; 

input [2:0]EXM;
input [4:0]EXRegRt;

input [4:0]WBRegRd;
input [1:0] WBWB;
input [31:0] datatowirte;

output [1:0]WB;
output [2:0]M;
output [3:0]EX;
output [4:0]IDRegRs,IDRegRt,IDRegRd;
output [31:0]DataA,imm_value;
output reg [31:0] DataB;

output [31:0] BranchAddr ;
output brunch_taken,brunch_control,PCWrite,IFIDWrite;

 


assign IDRegRs[4:0]=IDinst[25:21]; 
assign IDRegRt[4:0]=IDinst[20:16]; 
assign IDRegRd[4:0]=IDinst[15:11]; 


assign imm_value ={IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15],IDinst[15:0]}; 


assign BranchAddr = (imm_value << 2) + IDpc_plus_4;


wire [8:0] IDcontrol,ConOut;
wire HazMuxCon;

assign IDcontrol = HazMuxCon?ConOut:0;

reg [4:0] readReg1, readReg2;
wire signed [31:0] DataB_;
always @(*) begin
    if ((IDinst[31:26] == 0) && (IDinst[5:0] == 0)) begin
        readReg1 <= IDinst[20:16];
        readReg2 <= 0;
        DataB <= IDinst[10:6];
    end else begin
        readReg1 <= IDinst[25:21];
        readReg2 <= IDinst[20:16];
        DataB <= DataB_;
    end
end
wire ExMemStall = EXM[0] | EXM[1];
  HazardUnit HU(readReg1,readReg2,EXRegRt,ExMemStall,PCWrite,IFIDWrite,HazMuxCon);

Control thecontrol(IDinst[31:26],ConOut);


RegFile rf(DataA,DataB_,readReg1,readReg2,WBRegRd,datatowirte,WBWB[0],clock);

assign brunch_taken=(DataA==DataB)?1:0;
assign brunch_control=IDcontrol[6];

assign WB=IDcontrol[8:7];
assign M=IDcontrol[6:4];
assign EX=IDcontrol[3:0];

endmodule