data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/register_file.v
data/verilator_xmls/92c0f7e6-707a-473e-870c-a467cac5c61e.xml
module register_file(clk, Read1, Read2, Data1, Data2, writeEnabled, writeData, writeAddress);

    input clk;
    input [4:0] writeAddress;
    input [31:0] writeData;
    input writeEnabled;
    input [4:0] Read1, Read2;
    output reg [31:0] Data1, Data2;
    reg[31:0] RF[0:31];
    integer i;
    initial
    begin
        
        RF[0] <= 'h00000000;
        RF[1] <= 'hA00000AA;
        RF[2] <= 'h10000011;
        RF[3] <= 'h20000022;
        RF[4] <= 'h30000033;
        RF[5] <= 'h40000044;
        RF[6] <= 'h50000055;
        RF[7] <= 'h60000066;
        RF[8] <= 'h70000077;
        RF[9] <= 'h80000088;
        RF[10] <= 'h90000099;
        
        
    end
    
    always @ (negedge clk)
    begin
        Data1 <= RF[Read1];
        Data2 <= RF[Read2];
    end
    
    always @(*)
    begin 
        if (writeEnabled)
        begin
            RF[writeAddress] <= writeData;
        end
    end
    
 
endmodule
module register_file(clk, Read1, Read2, Data1, Data2, writeEnabled, writeData, writeAddress);


    input clk;
    input [4:0] writeAddress;
    input [31:0] writeData;
    input writeEnabled;
    input [4:0] Read1, Read2;
    output reg [31:0] Data1, Data2;
    reg[31:0] RF[0:31];
    integer i;
    initial
    begin
        
        RF[0] <= 'h00000000;
        RF[1] <= 'hA00000AA;
        RF[2] <= 'h10000011;
        RF[3] <= 'h20000022;
        RF[4] <= 'h30000033;
        RF[5] <= 'h40000044;
        RF[6] <= 'h50000055;
        RF[7] <= 'h60000066;
        RF[8] <= 'h70000077;
        RF[9] <= 'h80000088;
        RF[10] <= 'h90000099;
        
        
    end
    
    always @ (negedge clk)
    begin
        Data1 <= RF[Read1];
        Data2 <= RF[Read2];
    end
    
    always @(*)
    begin 
        if (writeEnabled)
        begin
            RF[writeAddress] <= writeData;
        end
    end
    
 
endmodule