data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:94: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'cfg_paddr\' generates 6 bits.\n                                                                                           : ... In instance dma_cfg\n    addr_i = cfg_paddr >> 2;  \n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:103: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_pwdata\' generates 32 bits.\n                                                                                            : ... In instance dma_cfg\n          ValidAddr:  {reg1_repeat, reg1_valid}  <= cfg_pwdata;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:105: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_pwdata\' generates 32 bits.\n                                                                                            : ... In instance dma_cfg\n          ErrAddr:    last_err                   <= cfg_pwdata;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg1_len\' generates 16 bits.\n                                                                                            : ... In instance dma_cfg\n          LenAddr:       cfg_prdata <= reg1_len;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:112: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg1_burst\' generates 5 bits.\n                                                                                            : ... In instance dma_cfg\n          BurstAddr:     cfg_prdata <= reg1_burst;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:113: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                                            : ... In instance dma_cfg\n          ValidAddr:     cfg_prdata <= {dma_valid, reg1_repeat, reg1_valid};\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:114: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'dma_status\' generates 10 bits.\n                                                                                            : ... In instance dma_cfg\n          StatusAddr:    cfg_prdata <= dma_status;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:115: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'dma_remain\' generates 16 bits.\n                                                                                            : ... In instance dma_cfg\n          RemainAddr:    cfg_prdata <= dma_remain;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:116: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'dma_fifo_used\' generates 7 bits.\n                                                                                            : ... In instance dma_cfg\n          FifoUsedAddr:  cfg_prdata <= dma_fifo_used;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:117: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_irq\' generates 1 bits.\n                                                                                            : ... In instance dma_cfg\n          IrqAddr:       cfg_prdata <= cfg_irq;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:118: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'last_err\' generates 2 bits.\n                                                                                            : ... In instance dma_cfg\n          ErrAddr:       cfg_prdata <= last_err;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:120: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'dma_curr_len\' generates 16 bits.\n                                                                                            : ... In instance dma_cfg\n          CurrLenAddr:   cfg_prdata <= dma_curr_len;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:136: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'dma_err\' generates 2 bits.\n                                                                                            : ... In instance dma_cfg\n    if (dma_err)\n    ^~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_cfg.v:153: Cannot find file containing module: \'stream_buf_v\'\n  stream_buf_v #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/stream_buf_v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/stream_buf_v.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/stream_buf_v.sv\n             stream_buf_v\n             stream_buf_v.v\n             stream_buf_v.sv\n             obj_dir/stream_buf_v\n             obj_dir/stream_buf_v.v\n             obj_dir/stream_buf_v.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n'
module dma_cfg #(
  parameter AddrBits     = 32,
  parameter LengthBits   = 16,
  parameter BurstBits    = 5,
  parameter FifoUsedBits = 7)
(
  input                       clk,
  input                       rst,

  input [5:0]                 cfg_paddr,
  input                       cfg_psel,
  input                       cfg_penable,
  input                       cfg_pwrite,
  input [31:0]                cfg_pwdata,
  output                      cfg_pready,
  output reg [31:0]           cfg_prdata,
  output                      cfg_pslverr,
  output reg                  cfg_irq,

  output  [AddrBits-1:0]      dma_start,
  output  [LengthBits-1:0]    dma_len,
  output  [BurstBits-1:0]     dma_burst,
  output                      dma_valid,
  input                       dma_done,
  input [LengthBits-1:0]      dma_remain,
  input [FifoUsedBits-1:0]    dma_fifo_used,
  input [9:0]                 dma_status,
  input [1:0]                 dma_err,
  input [LengthBits-1:0]      dma_curr_len
);




  localparam
    StartAddr     = 0,
    LenAddr       = 1,
    BurstAddr     = 2,
    ValidAddr     = 3,





    StatusAddr    = 4,
    RemainAddr    = 5,
    FifoUsedAddr  = 6,
    IrqAddr       = 7,
    ErrAddr       = 8,
    PrevStartAddr = 9,
    CurrLenAddr   = 10;




  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;

  reg [AddrBits-1:0]          reg1_start, dma_start_prev;
  reg [LengthBits-1:0]        reg1_len;
  reg [BurstBits-1:0]         reg1_burst;
  reg                         reg1_valid, reg1_repeat;
  reg [1:0]                   last_err;
  wire                        reg1_ready;

  always @(posedge clk) begin :cfg
    integer   addr_i;
    addr_i = cfg_paddr >> 2;

    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        case (addr_i)
          StartAddr:  reg1_start                 <= cfg_pwdata[AddrBits-1:0];
          LenAddr:    reg1_len                   <= cfg_pwdata[LengthBits-1:0];
          BurstAddr:  reg1_burst                 <= cfg_pwdata[BurstBits-1:0];
          ValidAddr:  {reg1_repeat, reg1_valid}  <= cfg_pwdata;
          IrqAddr:    cfg_irq                    <= cfg_pwdata[0];
          ErrAddr:    last_err                   <= cfg_pwdata;
        endcase

      end else begin
        case (addr_i)
          StartAddr:     cfg_prdata <= reg1_start;
          LenAddr:       cfg_prdata <= reg1_len;
          BurstAddr:     cfg_prdata <= reg1_burst;
          ValidAddr:     cfg_prdata <= {dma_valid, reg1_repeat, reg1_valid};
          StatusAddr:    cfg_prdata <= dma_status;
          RemainAddr:    cfg_prdata <= dma_remain;
          FifoUsedAddr:  cfg_prdata <= dma_fifo_used;
          IrqAddr:       cfg_prdata <= cfg_irq;
          ErrAddr:       cfg_prdata <= last_err;
          PrevStartAddr: cfg_prdata <= dma_start_prev;
          CurrLenAddr:   cfg_prdata <= dma_curr_len;
        endcase
      end
    end


    if (reg1_valid & reg1_ready)
      reg1_valid <= 0;


    if (dma_done) begin
      cfg_irq         <= 1;
      dma_start_prev  <= dma_start;
    end


    if (dma_err)
      last_err <= dma_err;

    if (rst) begin
      reg1_valid  <= 0;
      reg1_repeat <= 0;
      reg1_start  <= 0;
      reg1_len    <= 0;
      reg1_burst  <= 16;
      cfg_irq     <= 0;
      last_err    <= 0;
    end
  end




  stream_buf_v #(
    .DataBits (AddrBits + LengthBits + BurstBits))
  cfg_buf(
    .clk      (clk),
    .rst      (rst),
    .in_valid (reg1_valid | reg1_repeat),
    .in_ready (reg1_ready),
    .in_data  ({reg1_start, reg1_len, reg1_burst}),
    .out_valid(dma_valid),
    .out_ready(dma_done),
    .out_data ({dma_start, dma_len, dma_burst}));

endmodule
module dma_cfg #(
  parameter AddrBits     = 32,
  parameter LengthBits   = 16,
  parameter BurstBits    = 5,
  parameter FifoUsedBits = 7)
(
  input                       clk,
  input                       rst,

  input [5:0]                 cfg_paddr,
  input                       cfg_psel,
  input                       cfg_penable,
  input                       cfg_pwrite,
  input [31:0]                cfg_pwdata,
  output                      cfg_pready,
  output reg [31:0]           cfg_prdata,
  output                      cfg_pslverr,
  output reg                  cfg_irq,

  output  [AddrBits-1:0]      dma_start,
  output  [LengthBits-1:0]    dma_len,
  output  [BurstBits-1:0]     dma_burst,
  output                      dma_valid,
  input                       dma_done,
  input [LengthBits-1:0]      dma_remain,
  input [FifoUsedBits-1:0]    dma_fifo_used,
  input [9:0]                 dma_status,
  input [1:0]                 dma_err,
  input [LengthBits-1:0]      dma_curr_len
);





  localparam
    StartAddr     = 0,
    LenAddr       = 1,
    BurstAddr     = 2,
    ValidAddr     = 3,





    StatusAddr    = 4,
    RemainAddr    = 5,
    FifoUsedAddr  = 6,
    IrqAddr       = 7,
    ErrAddr       = 8,
    PrevStartAddr = 9,
    CurrLenAddr   = 10;




  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;

  reg [AddrBits-1:0]          reg1_start, dma_start_prev;
  reg [LengthBits-1:0]        reg1_len;
  reg [BurstBits-1:0]         reg1_burst;
  reg                         reg1_valid, reg1_repeat;
  reg [1:0]                   last_err;
  wire                        reg1_ready;

  always @(posedge clk) begin :cfg
    integer   addr_i;
    addr_i = cfg_paddr >> 2;

    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        case (addr_i)
          StartAddr:  reg1_start                 <= cfg_pwdata[AddrBits-1:0];
          LenAddr:    reg1_len                   <= cfg_pwdata[LengthBits-1:0];
          BurstAddr:  reg1_burst                 <= cfg_pwdata[BurstBits-1:0];
          ValidAddr:  {reg1_repeat, reg1_valid}  <= cfg_pwdata;
          IrqAddr:    cfg_irq                    <= cfg_pwdata[0];
          ErrAddr:    last_err                   <= cfg_pwdata;
        endcase

      end else begin
        case (addr_i)
          StartAddr:     cfg_prdata <= reg1_start;
          LenAddr:       cfg_prdata <= reg1_len;
          BurstAddr:     cfg_prdata <= reg1_burst;
          ValidAddr:     cfg_prdata <= {dma_valid, reg1_repeat, reg1_valid};
          StatusAddr:    cfg_prdata <= dma_status;
          RemainAddr:    cfg_prdata <= dma_remain;
          FifoUsedAddr:  cfg_prdata <= dma_fifo_used;
          IrqAddr:       cfg_prdata <= cfg_irq;
          ErrAddr:       cfg_prdata <= last_err;
          PrevStartAddr: cfg_prdata <= dma_start_prev;
          CurrLenAddr:   cfg_prdata <= dma_curr_len;
        endcase
      end
    end


    if (reg1_valid & reg1_ready)
      reg1_valid <= 0;


    if (dma_done) begin
      cfg_irq         <= 1;
      dma_start_prev  <= dma_start;
    end


    if (dma_err)
      last_err <= dma_err;

    if (rst) begin
      reg1_valid  <= 0;
      reg1_repeat <= 0;
      reg1_start  <= 0;
      reg1_len    <= 0;
      reg1_burst  <= 16;
      cfg_irq     <= 0;
      last_err    <= 0;
    end
  end




  stream_buf_v #(
    .DataBits (AddrBits + LengthBits + BurstBits))
  cfg_buf(
    .clk      (clk),
    .rst      (rst),
    .in_valid (reg1_valid | reg1_repeat),
    .in_ready (reg1_ready),
    .in_data  ({reg1_start, reg1_len, reg1_burst}),
    .out_valid(dma_valid),
    .out_ready(dma_done),
    .out_data ({dma_start, dma_len, dma_burst}));

endmodule