data/full_repos/permissive/103257524/src/cpu/pipeline_insnfetch.v
data/verilator_xmls/94c834e1-3c97-4f03-b015-4e6500637f9c.xml
module pipeline_insnfetch(
	input CLK,
	input RST,
	
	output read_flag,
	output [31:0] addr,

	input [31:0] read_data,
	input busy,
	input done,
	
	input next_insn_enabled,
	input [31:0] next_insn,
	input busy_in,
	
	output reg [31:0] insn,
	output reg [31:0] insnPC,
	output reg placeholder_insn
    );
	
	reg [31:0] PC;
	wire [31:0] nextPC;
	
	assign nextPC = next_insn_enabled ? next_insn : PC + 4;
	assign addr = nextPC;
	assign read_flag = !busy_in && !busy;

	
	always @(posedge CLK or posedge RST) begin
		if(RST) begin
			PC <= -32'd4;
		end else if(!busy_in && !busy) begin
			PC <= nextPC;
		end
	end
	
	always @(*) begin
		if(!busy) begin
			insn = read_data;
			insnPC = PC;
			placeholder_insn = 0;
		end else begin
			insn = 0;
			insnPC = 0;
			placeholder_insn = 1;
		end
	end
	

	

endmodule
module pipeline_insnfetch(
	input CLK,
	input RST,
	
	output read_flag,
	output [31:0] addr,

	input [31:0] read_data,
	input busy,
	input done,
	
	input next_insn_enabled,
	input [31:0] next_insn,
	input busy_in,
	
	output reg [31:0] insn,
	output reg [31:0] insnPC,
	output reg placeholder_insn
    );

	
	reg [31:0] PC;
	wire [31:0] nextPC;
	
	assign nextPC = next_insn_enabled ? next_insn : PC + 4;
	assign addr = nextPC;
	assign read_flag = !busy_in && !busy;

	
	always @(posedge CLK or posedge RST) begin
		if(RST) begin
			PC <= -32'd4;
		end else if(!busy_in && !busy) begin
			PC <= nextPC;
		end
	end
	
	always @(*) begin
		if(!busy) begin
			insn = read_data;
			insnPC = PC;
			placeholder_insn = 0;
		end else begin
			insn = 0;
			insnPC = 0;
			placeholder_insn = 1;
		end
	end
	

	

endmodule