data/full_repos/permissive/159902111/PCPU_experiment/FU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:28: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                            : ... In instance FU\n    else if (RegWrite_wb && (Rd_wb != 4\'b0) && (Rd_wb == Rs_ex)) \n                                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:26: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                            : ... In instance FU\n    if (RegWrite_mem && (Rd_mem != 4\'b0) && (Rd_mem == Rs_ex)) \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:34: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                            : ... In instance FU\n    else if (RegWrite_wb && (Rd_wb != 4\'b0) && (Rd_wb == Rt_ex) && !op_ex) \n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:34: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'op_ex\' generates 6 bits.\n                                                                            : ... In instance FU\n    else if (RegWrite_wb && (Rd_wb != 4\'b0) && (Rd_wb == Rt_ex) && !op_ex) \n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:32: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                            : ... In instance FU\n    if (RegWrite_mem && (Rd_mem != 4\'b0) && (Rd_mem == Rt_ex) && !op_ex) \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:32: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'op_ex\' generates 6 bits.\n                                                                            : ... In instance FU\n    if (RegWrite_mem && (Rd_mem != 4\'b0) && (Rd_mem == Rt_ex) && !op_ex) \n                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:40: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                            : ... In instance FU\n    else if (RegWrite_wb && (Rd_wb != 4\'b0) && (Rd_wb == Rt_ex) && MemWrite_ex) \n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:38: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                            : ... In instance FU\n    if (RegWrite_mem && (Rd_mem != 4\'b0) && (Rd_mem == Rt_ex) && MemWrite_ex) \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:48: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                            : ... In instance FU\n    else if (RegWrite_wb && (Rd_wb != 4\'b0) && (Rd_wb == Rs_id) && Jump_id && !op_id) \n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:48: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'op_id\' generates 6 bits.\n                                                                            : ... In instance FU\n    else if (RegWrite_wb && (Rd_wb != 4\'b0) && (Rd_wb == Rs_id) && Jump_id && !op_id) \n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:46: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                            : ... In instance FU\n    else if (RegWrite_mem && (Rd_mem != 4\'b0) && (Rd_mem == Rs_id) && Jump_id && !op_id)\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:46: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'op_id\' generates 6 bits.\n                                                                            : ... In instance FU\n    else if (RegWrite_mem && (Rd_mem != 4\'b0) && (Rd_mem == Rs_id) && Jump_id && !op_id)\n                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:44: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                            : ... In instance FU\n    if (RegWrite_ex && (Rd_ex != 4\'b0) && (Rd_ex == Rs_id) && Jump_id && !op_id) \n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/FU.v:44: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'op_id\' generates 6 bits.\n                                                                            : ... In instance FU\n    if (RegWrite_ex && (Rd_ex != 4\'b0) && (Rd_ex == Rs_id) && Jump_id && !op_id) \n                                                                         ^\n%Error: Exiting due to 14 warning(s)\n'
module FU(
  input [4:0] Rs_id,
  input       Jump_id,
  input [4:0] Rs_ex,
  input [4:0] Rt_ex,
  input [4:0] Rd_ex,
  input [4:0] Rd_mem,
  input [4:0] Rd_wb,
  input [5:0] op_id,
  input [5:0] op_ex,
  input       MemWrite_ex,
  input       RegWrite_ex,
  input       RegWrite_mem,
  input       RegWrite_wb,
  
  output[1:0] ForwardA_o,
  output[1:0] ForwardB_o,
  output[1:0] ForwardC_o,
  output[1:0] ForwardD_o
  );
  reg [1:0] ForwardA, ForwardB, ForwardC, ForwardD;
  always@(*)
  begin

    if (RegWrite_mem && (Rd_mem != 4'b0) && (Rd_mem == Rs_ex))
      ForwardA = 2'd1;
    else if (RegWrite_wb && (Rd_wb != 4'b0) && (Rd_wb == Rs_ex))
      ForwardA = 2'd2;
    else ForwardA = 2'd0;

    if (RegWrite_mem && (Rd_mem != 4'b0) && (Rd_mem == Rt_ex) && !op_ex)
      ForwardB = 2'd1;
    else if (RegWrite_wb && (Rd_wb != 4'b0) && (Rd_wb == Rt_ex) && !op_ex)
      ForwardB = 2'd2;
    else ForwardB = 2'b0;

    if (RegWrite_mem && (Rd_mem != 4'b0) && (Rd_mem == Rt_ex) && MemWrite_ex)
      ForwardC = 2'd1;
    else if (RegWrite_wb && (Rd_wb != 4'b0) && (Rd_wb == Rt_ex) && MemWrite_ex)
      ForwardC = 2'd2;
    else ForwardC = 2'b0;

    if (RegWrite_ex && (Rd_ex != 4'b0) && (Rd_ex == Rs_id) && Jump_id && !op_id)
      ForwardD = 2'b01;
    else if (RegWrite_mem && (Rd_mem != 4'b0) && (Rd_mem == Rs_id) && Jump_id && !op_id)
      ForwardD = 2'b10;
    else if (RegWrite_wb && (Rd_wb != 4'b0) && (Rd_wb == Rs_id) && Jump_id && !op_id) 
      ForwardD = 2'b11;
    else
      ForwardD = 2'b0;
  end
  assign ForwardA_o = ForwardA;
  assign ForwardB_o = ForwardB;
  assign ForwardC_o = ForwardC;
  assign ForwardD_o = ForwardD;
endmodule
module FU(
  input [4:0] Rs_id,
  input       Jump_id,
  input [4:0] Rs_ex,
  input [4:0] Rt_ex,
  input [4:0] Rd_ex,
  input [4:0] Rd_mem,
  input [4:0] Rd_wb,
  input [5:0] op_id,
  input [5:0] op_ex,
  input       MemWrite_ex,
  input       RegWrite_ex,
  input       RegWrite_mem,
  input       RegWrite_wb,
  
  output[1:0] ForwardA_o,
  output[1:0] ForwardB_o,
  output[1:0] ForwardC_o,
  output[1:0] ForwardD_o
  );

  reg [1:0] ForwardA, ForwardB, ForwardC, ForwardD;
  always@(*)
  begin

    if (RegWrite_mem && (Rd_mem != 4'b0) && (Rd_mem == Rs_ex))
      ForwardA = 2'd1;
    else if (RegWrite_wb && (Rd_wb != 4'b0) && (Rd_wb == Rs_ex))
      ForwardA = 2'd2;
    else ForwardA = 2'd0;

    if (RegWrite_mem && (Rd_mem != 4'b0) && (Rd_mem == Rt_ex) && !op_ex)
      ForwardB = 2'd1;
    else if (RegWrite_wb && (Rd_wb != 4'b0) && (Rd_wb == Rt_ex) && !op_ex)
      ForwardB = 2'd2;
    else ForwardB = 2'b0;

    if (RegWrite_mem && (Rd_mem != 4'b0) && (Rd_mem == Rt_ex) && MemWrite_ex)
      ForwardC = 2'd1;
    else if (RegWrite_wb && (Rd_wb != 4'b0) && (Rd_wb == Rt_ex) && MemWrite_ex)
      ForwardC = 2'd2;
    else ForwardC = 2'b0;

    if (RegWrite_ex && (Rd_ex != 4'b0) && (Rd_ex == Rs_id) && Jump_id && !op_id)
      ForwardD = 2'b01;
    else if (RegWrite_mem && (Rd_mem != 4'b0) && (Rd_mem == Rs_id) && Jump_id && !op_id)
      ForwardD = 2'b10;
    else if (RegWrite_wb && (Rd_wb != 4'b0) && (Rd_wb == Rs_id) && Jump_id && !op_id) 
      ForwardD = 2'b11;
    else
      ForwardD = 2'b0;
  end
  assign ForwardA_o = ForwardA;
  assign ForwardB_o = ForwardB;
  assign ForwardC_o = ForwardC;
  assign ForwardD_o = ForwardD;
endmodule