data/full_repos/permissive/20951436/Code/fpga code/advanced code/Advanced code.v
1: b'%Error: Cannot find file containing module: code/advanced\n        ... Looked in:\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.v\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.sv\n             code/advanced\n             code/advanced.v\n             code/advanced.sv\n             obj_dir/code/advanced\n             obj_dir/code/advanced.v\n             obj_dir/code/advanced.sv\n%Error: Cannot find file containing module: code,data/full_repos/permissive/20951436\n%Error: Cannot find file containing module: data/full_repos/permissive/20951436/Code/fpga\n%Error: Cannot find file containing module: code/Advanced\n%Error: Cannot find file containing module: code.v\n%Error: Exiting due to 5 error(s)\n'
module PWM_timer(input clk, input [4:0] speed, input en, output out, output dirp, dirn);

	reg [4:0] speed_copy; initial speed_copy<=0;

	reg outlogic; initial outlogic<=0;
	assign out = (en ? outlogic : 0);
	
	reg [3:0] count; initial count<=0;

	always @(negedge count[3]) speed_copy <= (speed[4] ? ~speed[3:0]+1 : speed[3:0]);

	always @(negedge clk) begin
		count<=count+1;
		if (count==0 && speed_copy[3:0]!=0) begin
			outlogic<=1;
		end else if (count==speed_copy[3:0]) begin
			outlogic<=0;
		end
	end
	

	assign dirp = ( (speed==0) ? 1'b1 : (~speed_copy[4]) );
	assign dirn = ( (speed==0) ? 1'b1 : (speed_copy[4]) );

endmodule
module PWM_timer(input clk, input [4:0] speed, input en, output out, output dirp, dirn);


	reg [4:0] speed_copy; initial speed_copy<=0;

	reg outlogic; initial outlogic<=0;
	assign out = (en ? outlogic : 0);
	
	reg [3:0] count; initial count<=0;

	always @(negedge count[3]) speed_copy <= (speed[4] ? ~speed[3:0]+1 : speed[3:0]);

	always @(negedge clk) begin
		count<=count+1;
		if (count==0 && speed_copy[3:0]!=0) begin
			outlogic<=1;
		end else if (count==speed_copy[3:0]) begin
			outlogic<=0;
		end
	end
	

	assign dirp = ( (speed==0) ? 1'b1 : (~speed_copy[4]) );
	assign dirn = ( (speed==0) ? 1'b1 : (speed_copy[4]) );

endmodule