data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/uart.v
1: b"%Error: data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/uart.v:20: Duplicate declaration of signal: 'busy'\n                                                                                      : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg busy = 0'b1;\n    ^~~~\n        data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/uart.v:12: ... Location of original declaration\n output busy,\n        ^~~~\n%Error: Exiting due to 1 error(s)\n"
module uart_bit_counter(
	input clk,
	input [15:0] max,
	output overflow
	);

reg [15:0] count = 16'b0;

assign overflow = (count == max);

always @(posedge clk) begin
	count <= overflow ? 16'b0 : (count + 16'b1);
end

endmodule
module uart_bit_counter(
	input clk,
	input [15:0] max,
	output overflow
	);


reg [15:0] count = 16'b0;

assign overflow = (count == max);

always @(posedge clk) begin
	count <= overflow ? 16'b0 : (count + 16'b1);
end

endmodule