data/full_repos/permissive/18921956/HardwareLab/Lab8/ONE_PULSE.v
data/verilator_xmls/a7f83c78-a8cf-4506-b6be-c5341a2c6971.xml
module ONE_PULSE(PB_single_pulse, PB_debounced, clk);
  input clk;
  input PB_debounced;
  output PB_single_pulse;
  
  reg PB_single_pulse;
  reg PB_debounced_delay;
    
  always @(posedge clk)
  begin
    if (PB_debounced == 1'b0 & PB_debounced_delay == 1'b1)
      PB_single_pulse <= 1'b0;
    else
      PB_single_pulse <= 1'b1;

    PB_debounced_delay <= PB_debounced;
  end
endmodule
module ONE_PULSE(PB_single_pulse, PB_debounced, clk);

  input clk;
  input PB_debounced;
  output PB_single_pulse;
  
  reg PB_single_pulse;
  reg PB_debounced_delay;
    
  always @(posedge clk)
  begin
    if (PB_debounced == 1'b0 & PB_debounced_delay == 1'b1)
      PB_single_pulse <= 1'b0;
    else
      PB_single_pulse <= 1'b1;

    PB_debounced_delay <= PB_debounced;
  end
endmodule