data/full_repos/permissive/125592111/verilog/Instruction_Memory.v
data/verilator_xmls/376f63a4-a065-4dd6-81ba-020cce857d48.xml
module InstructionMemory(Addr, Inst

);

input [31:0] Addr;
output reg [31:0] Inst;

reg [31:0] MEM[0:255];



parameter in_file = "bin/.in_file_tmp";
initial begin
    $readmemh(in_file, MEM);
end 

always @(*) begin
	Inst <= MEM[Addr[9:2]];
end

endmodule
module InstructionMemory(Addr, Inst

);


input [31:0] Addr;
output reg [31:0] Inst;

reg [31:0] MEM[0:255];



parameter in_file = "bin/.in_file_tmp";
initial begin
    $readmemh(in_file, MEM);
end 

always @(*) begin
	Inst <= MEM[Addr[9:2]];
end

endmodule