data/full_repos/permissive/106408053/verilog/core.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/core.v:195: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/106408053/verilog/core.v:168: Signal definition not found, creating implicitly: \'sampled_extTriggerIn\'\nassign run = run_basic | run_adv | sampled_extTriggerIn;\n                                   ^~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106408053/verilog/core.v:342: Signal definition not found, creating implicitly: \'capture_basic\'\n                                                                          : ... Suggested alternative: \'arm_basic\'\nwire capture = capture_basic || capture_adv;\n               ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106408053/verilog/core.v:342: Signal definition not found, creating implicitly: \'capture_adv\'\n                                                                          : ... Suggested alternative: \'capture\'\nwire capture = capture_basic || capture_adv;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:141: Cannot find file containing module: \'reset_sync\'\nreset_sync reset_sync_core (clock, reset, reset_core); \n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/reset_sync\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/reset_sync.v\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/reset_sync.sv\n             reset_sync\n             reset_sync.v\n             reset_sync.sv\n             obj_dir/reset_sync\n             obj_dir/reset_sync.v\n             obj_dir/reset_sync.sv\n%Error: data/full_repos/permissive/106408053/verilog/core.v:142: Cannot find file containing module: \'reset_sync\'\nreset_sync reset_sync_sample (sampleClock, reset_core, reset_sample);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:165: Cannot find file containing module: \'dly_signal\'\ndly_signal extTriggerIn_reg (clock, extTriggerIn, sampled_extTriggerIn);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:166: Cannot find file containing module: \'dly_signal\'\ndly_signal extTriggerOut_reg (clock, run, extTriggerOut);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:220: Cannot find file containing module: \'BUFGMUX\'\nBUFGMUX BUFGMUX_intex(\n^~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:230: Cannot find file containing module: \'decoder\'\ndecoder decoder(\n^~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:253: Cannot find file containing module: \'flags\'\nflags flags(\n^~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:265: Cannot find file containing module: \'sync\'\nsync sync(\n^~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:281: Cannot find file containing module: \'async_fifo\'\nasync_fifo async_fifo(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:292: Cannot find file containing module: \'sampler\'\nsampler sampler(\n^~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:308: Cannot find file containing module: \'trigger\'\ntrigger trigger(\n^~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:328: Cannot find file containing module: \'trigger_adv\'\ntrigger_adv trigger_adv(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:348: Cannot find file containing module: \'delay_fifo\'\ndelay_fifo delay_fifo (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:361: Cannot find file containing module: \'data_align\'\ndata_align data_align (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:375: Cannot find file containing module: \'rle_enc\'\nrle_enc rle_enc (\n^~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:394: Cannot find file containing module: \'pipeline_stall\'\npipeline_stall dly_arm_reg (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:401: Cannot find file containing module: \'pipeline_stall\'\npipeline_stall dly_run_reg (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/core.v:412: Cannot find file containing module: \'controller\'\ncontroller controller(\n^~~~~~~~~~\n%Error: Exiting due to 18 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module core(
  clock, extReset, 
  extClock, extTriggerIn, 
  opcode, config_data, execute, indata, outputBusy, 

  sampleReady50, outputSend, stableInput,
  memoryWrData, memoryRead, memoryWrite, memoryLastWrite,
  extTriggerOut, extClockOut, armLEDnn, 
  triggerLEDnn, wrFlags, extTestMode);

parameter [31:0] MEMORY_DEPTH=6;

input clock;
input extReset;
input [7:0] opcode;
input [31:0] config_data;
input execute;
input [31:0] indata;
input extClock;
input outputBusy;
input extTriggerIn;

output sampleReady50;
output outputSend;
output [31:0] stableInput;
output [31:0] memoryWrData;
output memoryRead;
output memoryWrite;
output memoryLastWrite;
output extTriggerOut;
output extClockOut;
output armLEDnn;
output triggerLEDnn;
output wrFlags;
output extTestMode;





wire [31:0] syncedInput;

wire [3:0] wrtrigmask; 
wire [3:0] wrtrigval; 
wire [3:0] wrtrigcfg;
wire [3:0] wrtrigedge;
wire wrDivider; 
wire wrsize; 

wire sample_valid;
wire [31:0] sample_data; 

wire dly_sample_valid;
wire [31:0] dly_sample_data;

wire aligned_data_valid;
wire [31:0] aligned_data;

wire rle_data_valid; 
wire [31:0] rle_data;

wire arm_basic, arm_adv;
wire arm = arm_basic | arm_adv;

wire sampleClock; 





`ifdef SLOW_EXTCLK

reg [1:0] scount, next_scount;
assign extClockOut = scount[1];
initial scount=0;
always @ (posedge sampleClock)
begin
  scount = next_scount;
end
always @*
begin
  next_scount = scount+1'b1;
end

`else

wire extClockOut = sampleClock;

`endif





wire resetCmd;
wire reset = extReset | resetCmd;

reset_sync reset_sync_core (clock, reset, reset_core); 
reset_sync reset_sync_sample (sampleClock, reset_core, reset_sample);





wire [31:0] flags_reg;
wire demux_mode = flags_reg[0];
wire filter_mode = flags_reg[1];
wire [3:0] disabledGroups = flags_reg[5:2];
wire extClock_mode = flags_reg[6];
wire falling_edge = flags_reg[7];
wire rleEnable = flags_reg[8];
wire numberScheme = flags_reg[9];
wire extTestMode = flags_reg[10] && !numberScheme;
wire intTestMode = flags_reg[11];
wire [1:0] rle_mode = flags_reg[15:14];





wire run_basic, run_adv, run; 
dly_signal extTriggerIn_reg (clock, extTriggerIn, sampled_extTriggerIn);
dly_signal extTriggerOut_reg (clock, run, extTriggerOut);

assign run = run_basic | run_adv | sampled_extTriggerIn;






reg armLEDnn, next_armLEDnn;
reg triggerLEDnn, next_triggerLEDnn;

`ifdef HEARTBEAT
reg [31:0] hcount, next_hcount;
initial hcount=0;
always @ (posedge clock)
begin
  hcount = next_hcount;
end
`endif

always @(posedge clock) 
begin
  armLEDnn = next_armLEDnn;
  triggerLEDnn = next_triggerLEDnn;
end

always @*
begin
  #1;
  next_armLEDnn = armLEDnn;
  next_triggerLEDnn = triggerLEDnn;
  if (arm) 
    begin
      next_armLEDnn = ~1'b1;
      next_triggerLEDnn = ~1'b0;
    end
  else if (run) 
    begin
      next_armLEDnn = ~1'b0;
      next_triggerLEDnn = ~1'b1;
    end

`ifdef HEARTBEAT
  next_hcount = (~|hcount) ? 100000000 : (hcount-1'b1);
  next_armLEDnn = armLEDnn;
  if (~|hcount) next_armLEDnn = !armLEDnn;
`endif
end





BUFGMUX BUFGMUX_intex(
  .O(sampleClock),
  .I0(clock),
  .I1(extClock),
  .S(extClock_mode));





decoder decoder(
  .clock(clock),
  .execute(execute),
  .opcode(opcode),

  .wrtrigmask(wrtrigmask),
  .wrtrigval(wrtrigval),
  .wrtrigcfg(wrtrigcfg),
  .wrtrigedge(wrtrigedge),
  .wrspeed(wrDivider),
  .wrsize(wrsize),
  .wrFlags(wrFlags),
  .wrTrigSelect(wrTrigSelect),
  .wrTrigChain(wrTrigChain),
  .finish_now(finish_now),
  .arm_basic(arm_basic),
  .arm_adv(arm_adv),
  .resetCmd(resetCmd));





flags flags(
  .clock(clock),
  .wrFlags(wrFlags),
  .config_data(config_data),
  .finish_now(finish_now),

  .flags_reg(flags_reg));





sync sync(
  .clock(sampleClock),
  .indata(indata),
  .intTestMode(intTestMode),
  .numberScheme(numberScheme),
  .filter_mode(filter_mode),
  .demux_mode(demux_mode),
  .falling_edge(falling_edge),

  .outdata(syncedInput));






async_fifo async_fifo(
  .wrclk(sampleClock), .wrreset(reset_sample),
  .rdclk(clock), .rdreset(reset_core),
  .space_avail(), .wrenb(1'b1), .wrdata(syncedInput),
  .read_req(1'b1), .data_avail(), 
  .data_valid(stableValid), .data_out(stableInput));





sampler sampler(
  .clock(clock),
  .extClock_mode(extClock_mode),
  .wrDivider(wrDivider),
  .config_data(config_data[23:0]),
  .validIn(stableValid),
  .dataIn(stableInput),

  .validOut(sample_valid),
  .dataOut(sample_data),
  .ready50(sampleReady50));





trigger trigger(
  .clock(clock),
  .reset(reset_core),
  .validIn(sample_valid),
  .dataIn(sample_data),
  .wrMask(wrtrigmask),
  .wrValue(wrtrigval),
  .wrConfig(wrtrigcfg),
  .wrEdge(wrtrigedge),
  .config_data(config_data),
  .arm(arm_basic),
  .demux_mode(demux_mode),

  .run(run_basic),
  .capture(capture_basic));





trigger_adv trigger_adv(
  .clock(clock),
  .reset(reset_core),
  .validIn(sample_valid),
  .dataIn(sample_data),
  .wrSelect(wrTrigSelect),
  .wrChain(wrTrigChain),
  .config_data(config_data),
  .arm(arm_adv),
  .finish_now(finish_now),

  .run(run_adv),
  .capture(capture_adv));

wire capture = capture_basic || capture_adv;





delay_fifo delay_fifo (
  .clock(clock),
  .validIn(sample_valid),
  .dataIn(sample_data),

  .validOut(dly_sample_valid),
  .dataOut(dly_sample_data));
defparam delay_fifo.DELAY = 3;





data_align data_align (
  .clock(clock),
  .disabledGroups(disabledGroups),
  .validIn(dly_sample_valid && capture),
  .dataIn(dly_sample_data),

  .validOut(aligned_data_valid),
  .dataOut(aligned_data));






rle_enc rle_enc (
  .clock(clock),
  .reset(reset_core),
  .enable(rleEnable),
  .arm(arm),
  .rle_mode(rle_mode),
  .demux_mode(demux_mode),
  .disabledGroups(disabledGroups),
  .validIn(aligned_data_valid),
  .dataIn(aligned_data),

  .validOut(rle_data_valid),
  .dataOut(rle_data));






pipeline_stall dly_arm_reg (
  .clk(clock), 
  .reset(reset_core), 
  .datain(arm), 
  .dataout(dly_arm));
defparam dly_arm_reg.DELAY = 2;

pipeline_stall dly_run_reg (
  .clk(clock), 
  .reset(reset_core), 
  .datain(run), 
  .dataout(dly_run));
defparam dly_run_reg.DELAY = 1;





controller controller(
  .clock(clock),
  .reset(reset_core),
  .run(dly_run),
  .wrSize(wrsize),
  .config_data(config_data),
  .validIn(rle_data_valid),
  .dataIn(rle_data),
  .arm(dly_arm),
  .busy(outputBusy),

  .send(outputSend),
  .memoryWrData(memoryWrData),
  .memoryRead(memoryRead),
  .memoryWrite(memoryWrite),
  .memoryLastWrite(memoryLastWrite));

endmodule
module core(
  clock, extReset, 
  extClock, extTriggerIn, 
  opcode, config_data, execute, indata, outputBusy, 

  sampleReady50, outputSend, stableInput,
  memoryWrData, memoryRead, memoryWrite, memoryLastWrite,
  extTriggerOut, extClockOut, armLEDnn, 
  triggerLEDnn, wrFlags, extTestMode);


parameter [31:0] MEMORY_DEPTH=6;

input clock;
input extReset;
input [7:0] opcode;
input [31:0] config_data;
input execute;
input [31:0] indata;
input extClock;
input outputBusy;
input extTriggerIn;

output sampleReady50;
output outputSend;
output [31:0] stableInput;
output [31:0] memoryWrData;
output memoryRead;
output memoryWrite;
output memoryLastWrite;
output extTriggerOut;
output extClockOut;
output armLEDnn;
output triggerLEDnn;
output wrFlags;
output extTestMode;





wire [31:0] syncedInput;

wire [3:0] wrtrigmask; 
wire [3:0] wrtrigval; 
wire [3:0] wrtrigcfg;
wire [3:0] wrtrigedge;
wire wrDivider; 
wire wrsize; 

wire sample_valid;
wire [31:0] sample_data; 

wire dly_sample_valid;
wire [31:0] dly_sample_data;

wire aligned_data_valid;
wire [31:0] aligned_data;

wire rle_data_valid; 
wire [31:0] rle_data;

wire arm_basic, arm_adv;
wire arm = arm_basic | arm_adv;

wire sampleClock; 





`ifdef SLOW_EXTCLK

reg [1:0] scount, next_scount;
assign extClockOut = scount[1];
initial scount=0;
always @ (posedge sampleClock)
begin
  scount = next_scount;
end
always @*
begin
  next_scount = scount+1'b1;
end

`else

wire extClockOut = sampleClock;

`endif





wire resetCmd;
wire reset = extReset | resetCmd;

reset_sync reset_sync_core (clock, reset, reset_core); 
reset_sync reset_sync_sample (sampleClock, reset_core, reset_sample);





wire [31:0] flags_reg;
wire demux_mode = flags_reg[0];
wire filter_mode = flags_reg[1];
wire [3:0] disabledGroups = flags_reg[5:2];
wire extClock_mode = flags_reg[6];
wire falling_edge = flags_reg[7];
wire rleEnable = flags_reg[8];
wire numberScheme = flags_reg[9];
wire extTestMode = flags_reg[10] && !numberScheme;
wire intTestMode = flags_reg[11];
wire [1:0] rle_mode = flags_reg[15:14];





wire run_basic, run_adv, run; 
dly_signal extTriggerIn_reg (clock, extTriggerIn, sampled_extTriggerIn);
dly_signal extTriggerOut_reg (clock, run, extTriggerOut);

assign run = run_basic | run_adv | sampled_extTriggerIn;






reg armLEDnn, next_armLEDnn;
reg triggerLEDnn, next_triggerLEDnn;

`ifdef HEARTBEAT
reg [31:0] hcount, next_hcount;
initial hcount=0;
always @ (posedge clock)
begin
  hcount = next_hcount;
end
`endif

always @(posedge clock) 
begin
  armLEDnn = next_armLEDnn;
  triggerLEDnn = next_triggerLEDnn;
end

always @*
begin
  #1;
  next_armLEDnn = armLEDnn;
  next_triggerLEDnn = triggerLEDnn;
  if (arm) 
    begin
      next_armLEDnn = ~1'b1;
      next_triggerLEDnn = ~1'b0;
    end
  else if (run) 
    begin
      next_armLEDnn = ~1'b0;
      next_triggerLEDnn = ~1'b1;
    end

`ifdef HEARTBEAT
  next_hcount = (~|hcount) ? 100000000 : (hcount-1'b1);
  next_armLEDnn = armLEDnn;
  if (~|hcount) next_armLEDnn = !armLEDnn;
`endif
end





BUFGMUX BUFGMUX_intex(
  .O(sampleClock),
  .I0(clock),
  .I1(extClock),
  .S(extClock_mode));





decoder decoder(
  .clock(clock),
  .execute(execute),
  .opcode(opcode),

  .wrtrigmask(wrtrigmask),
  .wrtrigval(wrtrigval),
  .wrtrigcfg(wrtrigcfg),
  .wrtrigedge(wrtrigedge),
  .wrspeed(wrDivider),
  .wrsize(wrsize),
  .wrFlags(wrFlags),
  .wrTrigSelect(wrTrigSelect),
  .wrTrigChain(wrTrigChain),
  .finish_now(finish_now),
  .arm_basic(arm_basic),
  .arm_adv(arm_adv),
  .resetCmd(resetCmd));





flags flags(
  .clock(clock),
  .wrFlags(wrFlags),
  .config_data(config_data),
  .finish_now(finish_now),

  .flags_reg(flags_reg));





sync sync(
  .clock(sampleClock),
  .indata(indata),
  .intTestMode(intTestMode),
  .numberScheme(numberScheme),
  .filter_mode(filter_mode),
  .demux_mode(demux_mode),
  .falling_edge(falling_edge),

  .outdata(syncedInput));






async_fifo async_fifo(
  .wrclk(sampleClock), .wrreset(reset_sample),
  .rdclk(clock), .rdreset(reset_core),
  .space_avail(), .wrenb(1'b1), .wrdata(syncedInput),
  .read_req(1'b1), .data_avail(), 
  .data_valid(stableValid), .data_out(stableInput));





sampler sampler(
  .clock(clock),
  .extClock_mode(extClock_mode),
  .wrDivider(wrDivider),
  .config_data(config_data[23:0]),
  .validIn(stableValid),
  .dataIn(stableInput),

  .validOut(sample_valid),
  .dataOut(sample_data),
  .ready50(sampleReady50));





trigger trigger(
  .clock(clock),
  .reset(reset_core),
  .validIn(sample_valid),
  .dataIn(sample_data),
  .wrMask(wrtrigmask),
  .wrValue(wrtrigval),
  .wrConfig(wrtrigcfg),
  .wrEdge(wrtrigedge),
  .config_data(config_data),
  .arm(arm_basic),
  .demux_mode(demux_mode),

  .run(run_basic),
  .capture(capture_basic));





trigger_adv trigger_adv(
  .clock(clock),
  .reset(reset_core),
  .validIn(sample_valid),
  .dataIn(sample_data),
  .wrSelect(wrTrigSelect),
  .wrChain(wrTrigChain),
  .config_data(config_data),
  .arm(arm_adv),
  .finish_now(finish_now),

  .run(run_adv),
  .capture(capture_adv));

wire capture = capture_basic || capture_adv;





delay_fifo delay_fifo (
  .clock(clock),
  .validIn(sample_valid),
  .dataIn(sample_data),

  .validOut(dly_sample_valid),
  .dataOut(dly_sample_data));
defparam delay_fifo.DELAY = 3;





data_align data_align (
  .clock(clock),
  .disabledGroups(disabledGroups),
  .validIn(dly_sample_valid && capture),
  .dataIn(dly_sample_data),

  .validOut(aligned_data_valid),
  .dataOut(aligned_data));






rle_enc rle_enc (
  .clock(clock),
  .reset(reset_core),
  .enable(rleEnable),
  .arm(arm),
  .rle_mode(rle_mode),
  .demux_mode(demux_mode),
  .disabledGroups(disabledGroups),
  .validIn(aligned_data_valid),
  .dataIn(aligned_data),

  .validOut(rle_data_valid),
  .dataOut(rle_data));






pipeline_stall dly_arm_reg (
  .clk(clock), 
  .reset(reset_core), 
  .datain(arm), 
  .dataout(dly_arm));
defparam dly_arm_reg.DELAY = 2;

pipeline_stall dly_run_reg (
  .clk(clock), 
  .reset(reset_core), 
  .datain(run), 
  .dataout(dly_run));
defparam dly_run_reg.DELAY = 1;





controller controller(
  .clock(clock),
  .reset(reset_core),
  .run(dly_run),
  .wrSize(wrsize),
  .config_data(config_data),
  .validIn(rle_data_valid),
  .dataIn(rle_data),
  .arm(dly_arm),
  .busy(outputBusy),

  .send(outputSend),
  .memoryWrData(memoryWrData),
  .memoryRead(memoryRead),
  .memoryWrite(memoryWrite),
  .memoryLastWrite(memoryLastWrite));

endmodule