data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/thirty_two_bit_adder_testbench.v
1: b'%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/thirty_two_bit_adder_testbench.v:15: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("thirty_two_bit_adder.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/thirty_two_bit_adder_testbench.v:16: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,thirty_two_bit_adder_testbench);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/thirty_two_bit_adder_testbench.v:17: Unsupported or unknown PLI call: $monitor\n    $monitor(x, y, c_in, sum, c_out);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/thirty_two_bit_adder_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/thirty_two_bit_adder_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module thirty_two_bit_adder_testbench;

reg [31:0]x;
reg [31:0]y;
reg c_in;
wire [31:0]sum;
wire c_out;

thirty_two_bit_adder uut(.x(x), .y(y), .c_in(c_in), .sum(sum), .c_out(c_out));

initial begin
    
    $dumpfile("thirty_two_bit_adder.vcd");
    $dumpvars(0,thirty_two_bit_adder_testbench);
    $monitor(x, y, c_in, sum, c_out);
    

    c_in=0;
    




    x=32'd45000;
    y=32'd160000;
    #5
    if(sum!==32'd205000) $display("First check failed.");
    else $display("First check successful");


    x=32'd75000;
    y=32'd475005;
    #5
    if(sum!==32'd550005) $display("Second check failed.");
    else $display("Second check successful");


    $finish;
end
endmodule
module thirty_two_bit_adder_testbench;


reg [31:0]x;
reg [31:0]y;
reg c_in;
wire [31:0]sum;
wire c_out;

thirty_two_bit_adder uut(.x(x), .y(y), .c_in(c_in), .sum(sum), .c_out(c_out));

initial begin
    
    $dumpfile("thirty_two_bit_adder.vcd");
    $dumpvars(0,thirty_two_bit_adder_testbench);
    $monitor(x, y, c_in, sum, c_out);
    

    c_in=0;
    




    x=32'd45000;
    y=32'd160000;
    #5
    if(sum!==32'd205000) $display("First check failed.");
    else $display("First check successful");


    x=32'd75000;
    y=32'd475005;
    #5
    if(sum!==32'd550005) $display("Second check failed.");
    else $display("Second check successful");


    $finish;
end
endmodule