data/full_repos/permissive/111499712/fw/syn/top.v
1: b'%Error: data/full_repos/permissive/111499712/fw/syn/top.v:44: Cannot find file containing module: \'SB_PLL40_PAD\'\nSB_PLL40_PAD #(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111499712/fw/syn,data/full_repos/permissive/111499712/SB_PLL40_PAD\n             data/full_repos/permissive/111499712/fw/syn,data/full_repos/permissive/111499712/SB_PLL40_PAD.v\n             data/full_repos/permissive/111499712/fw/syn,data/full_repos/permissive/111499712/SB_PLL40_PAD.sv\n             SB_PLL40_PAD\n             SB_PLL40_PAD.v\n             SB_PLL40_PAD.sv\n             obj_dir/SB_PLL40_PAD\n             obj_dir/SB_PLL40_PAD.v\n             obj_dir/SB_PLL40_PAD.sv\n%Warning-WIDTH: data/full_repos/permissive/111499712/fw/syn/top.v:71: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                    : ... In instance top\n  resetn_gen <= {resetn_gen, pll_locked};\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:80: Cannot find file containing module: \'clock_generator\'\nclock_generator #(SpiPeriod) spi_clkgen(clk, reset, spi_clk, spi_reset);\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:122: Cannot find file containing module: \'coordinate_decoder\'\ncoordinate_decoder coordinate_decoder(spi_clk, sending_pixels, sample_pixel,\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:125: Cannot find file containing module: \'spi_ram_slave\'\nspi_ram_slave spi_ram_slave(clk, rpi_sck, rpi_cs, rpi_mosi,\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:128: Cannot find file containing module: \'ram_source\'\nram_source ram_source(spi_clk, spi_reset, frame_begin, sample_pixel,\n^~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:131: Cannot find file containing module: \'prbs_source\'\nprbs_source prbs_source(spi_clk, spi_reset, frame_begin, sample_pixel,\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:134: Cannot find file containing module: \'video_hack_1\'\nvideo_hack_1 video_hack_1(clk, reset, frame_begin, x, y,\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:137: Cannot find file containing module: \'video_hack_2\'\nvideo_hack_2 video_hack_2(clk, reset, frame_begin, x, y,\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/syn/top.v:149: Cannot find file containing module: \'pmodoledrgb_controller\'\npmodoledrgb_controller #(SpiFreq) pmodoledrgb_controller(spi_clk, spi_reset,\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 1 warning(s)\n'
module top(clk_100mhz, pmod1_1, pmod1_2, pmod1_3, pmod1_4, pmod1_7, pmod1_8,
  pmod1_9, pmod1_10, pmod2_7, pmod2_8, pmod2_9, pmod2_10, rpi_sck, rpi_cs,
  rpi_mosi);
parameter ClkFreq = 50000000;

input clk_100mhz;
output pmod1_1, pmod1_2, pmod1_3, pmod1_4, pmod1_7, pmod1_8, pmod1_9, pmod1_10;
input pmod2_7, pmod2_8, pmod2_9, pmod2_10;
input rpi_sck, rpi_cs, rpi_mosi;


wire clk_50mhz;
wire pll_locked;

SB_PLL40_PAD #(
  .FEEDBACK_PATH("SIMPLE"),
  .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
  .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
  .PLLOUT_SELECT("GENCLK"),
  .FDA_FEEDBACK(4'b1111),
  .FDA_RELATIVE(4'b1111),
  .DIVR(4'b0000),
  .DIVF(7'b0000111),
  .DIVQ(3'b100),
  .FILTER_RANGE(3'b101)
) pll (
  .PACKAGEPIN(clk_100mhz),
  .PLLOUTGLOBAL(clk_50mhz),
  .LOCK(pll_locked),
  .BYPASS(1'b0),
  .RESETB(1'b1)
);

wire clk = clk_50mhz;


reg [3:0] resetn_gen = 0;
reg reset;

always @(posedge clk) begin
  reset <= !&resetn_gen;
  resetn_gen <= {resetn_gen, pll_locked};
end


localparam SpiDesiredFreq = 6250000;
localparam SpiPeriod = (ClkFreq + (SpiDesiredFreq * 2) - 1) / (SpiDesiredFreq * 2);
localparam SpiFreq = ClkFreq / (SpiPeriod * 2);

wire spi_clk, spi_reset;
clock_generator #(SpiPeriod) spi_clkgen(clk, reset, spi_clk, spi_reset);


wire [3:0] btns = {pmod2_10, pmod2_9, pmod2_8, pmod2_7};
reg [1:0] video_source;

always @(posedge spi_clk) begin
  if (spi_reset)
    video_source <= 0;
  else if (frame_begin) begin
    if (btns[0])
      video_source <= 0;
    else if(btns[1])
      video_source <= 1;
    else if (btns[2])
      video_source <= 2;
    else if(btns[3])
      video_source <= 3;
  end
end


wire pmodoldedrgb_cs = pmod1_1;
wire pmodoldedrgb_sdin = pmod1_2;
assign pmod1_3 = 0;
wire pmodoldedrgb_sclk = pmod1_4;
wire pmodoldedrgb_d_cn = pmod1_7;
wire pmodoldedrgb_resn = pmod1_8;
wire pmodoldedrgb_vccen = pmod1_9;
wire pmodoldedrgb_pmoden = pmod1_10;

wire frame_begin, sending_pixels, sample_pixel;
wire [12:0] pixel_index;
wire [15:0] pixel_data, ram_pixel_data, prbs_pixel_data,
  video_hack_1_pixel_data, video_hack_2_pixel_data;
wire [6:0] x;
wire [5:0] y;

wire ram_wr;
wire [12:0] ram_addr;
wire [15:0] ram_data;

coordinate_decoder coordinate_decoder(spi_clk, sending_pixels, sample_pixel,
  x, y);

spi_ram_slave spi_ram_slave(clk, rpi_sck, rpi_cs, rpi_mosi,
  ram_addr, ram_data, ram_wr);

ram_source ram_source(spi_clk, spi_reset, frame_begin, sample_pixel,
  pixel_index, ram_pixel_data, clk, ram_wr, ram_addr, ram_data);

prbs_source prbs_source(spi_clk, spi_reset, frame_begin, sample_pixel,
  prbs_pixel_data);

video_hack_1 video_hack_1(clk, reset, frame_begin, x, y,
  video_hack_1_pixel_data);

video_hack_2 video_hack_2(clk, reset, frame_begin, x, y,
  video_hack_2_pixel_data);

always @(*) begin
  case (video_source)
    0: pixel_data = ram_pixel_data;
    1: pixel_data = prbs_pixel_data;
    2: pixel_data = video_hack_1_pixel_data;
    3: pixel_data = video_hack_2_pixel_data;
  endcase
end

pmodoledrgb_controller #(SpiFreq) pmodoledrgb_controller(spi_clk, spi_reset,
  frame_begin, sending_pixels, sample_pixel, pixel_index, pixel_data,
  pmodoldedrgb_cs, pmodoldedrgb_sdin, pmodoldedrgb_sclk, pmodoldedrgb_d_cn,
  pmodoldedrgb_resn, pmodoldedrgb_vccen, pmodoldedrgb_pmoden);

endmodule
module top(clk_100mhz, pmod1_1, pmod1_2, pmod1_3, pmod1_4, pmod1_7, pmod1_8,
  pmod1_9, pmod1_10, pmod2_7, pmod2_8, pmod2_9, pmod2_10, rpi_sck, rpi_cs,
  rpi_mosi);

parameter ClkFreq = 50000000;

input clk_100mhz;
output pmod1_1, pmod1_2, pmod1_3, pmod1_4, pmod1_7, pmod1_8, pmod1_9, pmod1_10;
input pmod2_7, pmod2_8, pmod2_9, pmod2_10;
input rpi_sck, rpi_cs, rpi_mosi;


wire clk_50mhz;
wire pll_locked;

SB_PLL40_PAD #(
  .FEEDBACK_PATH("SIMPLE"),
  .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
  .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
  .PLLOUT_SELECT("GENCLK"),
  .FDA_FEEDBACK(4'b1111),
  .FDA_RELATIVE(4'b1111),
  .DIVR(4'b0000),
  .DIVF(7'b0000111),
  .DIVQ(3'b100),
  .FILTER_RANGE(3'b101)
) pll (
  .PACKAGEPIN(clk_100mhz),
  .PLLOUTGLOBAL(clk_50mhz),
  .LOCK(pll_locked),
  .BYPASS(1'b0),
  .RESETB(1'b1)
);

wire clk = clk_50mhz;


reg [3:0] resetn_gen = 0;
reg reset;

always @(posedge clk) begin
  reset <= !&resetn_gen;
  resetn_gen <= {resetn_gen, pll_locked};
end


localparam SpiDesiredFreq = 6250000;
localparam SpiPeriod = (ClkFreq + (SpiDesiredFreq * 2) - 1) / (SpiDesiredFreq * 2);
localparam SpiFreq = ClkFreq / (SpiPeriod * 2);

wire spi_clk, spi_reset;
clock_generator #(SpiPeriod) spi_clkgen(clk, reset, spi_clk, spi_reset);


wire [3:0] btns = {pmod2_10, pmod2_9, pmod2_8, pmod2_7};
reg [1:0] video_source;

always @(posedge spi_clk) begin
  if (spi_reset)
    video_source <= 0;
  else if (frame_begin) begin
    if (btns[0])
      video_source <= 0;
    else if(btns[1])
      video_source <= 1;
    else if (btns[2])
      video_source <= 2;
    else if(btns[3])
      video_source <= 3;
  end
end


wire pmodoldedrgb_cs = pmod1_1;
wire pmodoldedrgb_sdin = pmod1_2;
assign pmod1_3 = 0;
wire pmodoldedrgb_sclk = pmod1_4;
wire pmodoldedrgb_d_cn = pmod1_7;
wire pmodoldedrgb_resn = pmod1_8;
wire pmodoldedrgb_vccen = pmod1_9;
wire pmodoldedrgb_pmoden = pmod1_10;

wire frame_begin, sending_pixels, sample_pixel;
wire [12:0] pixel_index;
wire [15:0] pixel_data, ram_pixel_data, prbs_pixel_data,
  video_hack_1_pixel_data, video_hack_2_pixel_data;
wire [6:0] x;
wire [5:0] y;

wire ram_wr;
wire [12:0] ram_addr;
wire [15:0] ram_data;

coordinate_decoder coordinate_decoder(spi_clk, sending_pixels, sample_pixel,
  x, y);

spi_ram_slave spi_ram_slave(clk, rpi_sck, rpi_cs, rpi_mosi,
  ram_addr, ram_data, ram_wr);

ram_source ram_source(spi_clk, spi_reset, frame_begin, sample_pixel,
  pixel_index, ram_pixel_data, clk, ram_wr, ram_addr, ram_data);

prbs_source prbs_source(spi_clk, spi_reset, frame_begin, sample_pixel,
  prbs_pixel_data);

video_hack_1 video_hack_1(clk, reset, frame_begin, x, y,
  video_hack_1_pixel_data);

video_hack_2 video_hack_2(clk, reset, frame_begin, x, y,
  video_hack_2_pixel_data);

always @(*) begin
  case (video_source)
    0: pixel_data = ram_pixel_data;
    1: pixel_data = prbs_pixel_data;
    2: pixel_data = video_hack_1_pixel_data;
    3: pixel_data = video_hack_2_pixel_data;
  endcase
end

pmodoledrgb_controller #(SpiFreq) pmodoledrgb_controller(spi_clk, spi_reset,
  frame_begin, sending_pixels, sample_pixel, pixel_index, pixel_data,
  pmodoldedrgb_cs, pmodoldedrgb_sdin, pmodoldedrgb_sclk, pmodoldedrgb_d_cn,
  pmodoldedrgb_resn, pmodoldedrgb_vccen, pmodoldedrgb_pmoden);

endmodule