data/full_repos/permissive/151745998/d_flipflop_tb.v
1: b'%Error: data/full_repos/permissive/151745998/d_flipflop_tb.v:2: Cannot find include file: d_flipflop.v\n`include "d_flipflop.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151745998,data/full_repos/permissive/151745998/d_flipflop.v\n             data/full_repos/permissive/151745998,data/full_repos/permissive/151745998/d_flipflop.v.v\n             data/full_repos/permissive/151745998,data/full_repos/permissive/151745998/d_flipflop.v.sv\n             d_flipflop.v\n             d_flipflop.v.v\n             d_flipflop.v.sv\n             obj_dir/d_flipflop.v\n             obj_dir/d_flipflop.v.v\n             obj_dir/d_flipflop.v.sv\n%Error: data/full_repos/permissive/151745998/d_flipflop_tb.v:11: Unsupported or unknown PLI call: $monitor\n    $monitor("out = %b", out);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/151745998/d_flipflop_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("d_flipflop_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/151745998/d_flipflop_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, d_flipflop_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/151745998/d_flipflop_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    d = 1\'bx; reset = 1; enable = 1\'bx; #30;\n                                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/151745998/d_flipflop_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    d = 0; reset = 0; enable = 1; #30;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/151745998/d_flipflop_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    d = 1; reset = 0; enable = 1; #30;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/151745998/d_flipflop_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    d = 0; reset = 0; enable = 0; #30;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/151745998/d_flipflop_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    d = 1; reset = 0; enable = 0; #30;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/151745998/d_flipflop_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk=!clk;\n         ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n'
module d_flipflop_tb;
  reg d, clk, enable, reset;
  wire out;

  d_flipflop ff(d, clk, enable, reset, out);

  initial begin
    $monitor("out = %b", out);
    $dumpfile("d_flipflop_tb.vcd");
    $dumpvars(0, d_flipflop_tb);
    clk = 0;
    d = 1'bx; reset = 1; enable = 1'bx; #30;
    d = 0; reset = 0; enable = 1; #30;
    d = 1; reset = 0; enable = 1; #30;
    d = 0; reset = 0; enable = 0; #30;
    d = 1; reset = 0; enable = 0; #30;
    $finish;
  end

  always #10 clk=!clk;
endmodule
module d_flipflop_tb;

  reg d, clk, enable, reset;
  wire out;

  d_flipflop ff(d, clk, enable, reset, out);

  initial begin
    $monitor("out = %b", out);
    $dumpfile("d_flipflop_tb.vcd");
    $dumpvars(0, d_flipflop_tb);
    clk = 0;
    d = 1'bx; reset = 1; enable = 1'bx; #30;
    d = 0; reset = 0; enable = 1; #30;
    d = 1; reset = 0; enable = 1; #30;
    d = 0; reset = 0; enable = 0; #30;
    d = 1; reset = 0; enable = 0; #30;
    $finish;
  end

  always #10 clk=!clk;
endmodule