data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v
1: b'%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:757: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h2a\' generates 6 bits.\n                                                                              : ... In instance pipeline_riscv.ALU\n    case (alu_code)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:526: Operator EQ expects 6 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                              : ... In instance pipeline_riscv.CTRL\n    if (rd[1]!=0 && ((J_type[1] && funct[1]==7\'h08) || S_type[1]==6\'h2B)) begin\n                                                                ^~\n%Error: Exiting due to 2 warning(s)\n'
module control (
  input clk,
  input nrst,
  input zero,
  input [31:0] inst,
  output jr,
  output jal,
  output jal_pc,
  output load,
  output wr_mem,
  output use_imm,
  output sw,
  output [`PIPELINE_STAGES*32-1:0] debug_inst,
  output reg [6:0] alu_code,
  output reg [2:0] sel_pc,
  output reg [1:0] flush,
  output reg wr_rf,
  output stall,
  output [2:0] fwd_opA,
  output [2:0] fwd_opB,
  output [2:0] fwd_sw,
  output [2:0] fwd_jr
  );

  genvar i;
  
  wire [5:0] op           [0:4];
  wire [4:0] rd           [0:4];
  wire [4:0] rs1          [0:4];
  wire [4:0] rs2          [0:4];
  wire [6:0] funct        [0:4];
  wire [31:0] inst_cache  [0:4];
  
  assign inst_cache[0] = inst;
  generate
    for (i=0; i<=4; i=i+1) begin
      assign op[i]      = inst_cache[i][5:0];
      assign rd[i]      = inst_cache[i][10:6];
      assign rs1[i]     = inst_cache[i][19:15];
      assign rs2[i]     = inst_cache[i][24:20];
      assign funct[i]   = inst_cache[i][31:25];
    end
  endgenerate
  assign debug_inst = {
    inst_cache[4],
    inst_cache[3],
    inst_cache[2],
    inst_cache[1],
    inst_cache[0]
  };
  

  
  reg [4:0] R_type;
  reg [4:0] I_type;
  reg [4:0] L_type;
  reg [4:0] S_type;
  reg [4:0] B_type;
  reg [4:0] J_type;
  generate
    for (i=0; i<=4; i=i+1) begin
      always@(op[i], funct[i]) begin
        R_type[i] = 0;
        I_type[i] = 0;
        L_type[i] = 0;
        S_type[i] = 0;
        B_type[i] = 0;
        J_type[i] = 0;
        case (op[i])
          6'h00:
            if (funct[i]==7'h08)
              J_type[i] = 1;
            else
              R_type[i] = 1;
          6'h08, 6'h0A:
            I_type[i] = 1;
          6'h23:
            L_type[i] = 1;
          6'h2B:
            S_type[i] = 1;
          6'h04, 6'h05:
            B_type[i] = 1;
          6'h02, 6'h03:
            J_type[i] = 1;
          default: begin
            R_type[i] = 0;
            I_type[i] = 0;
            L_type[i] = 0;
            S_type[i] = 0;
            B_type[i] = 0;
            J_type[i] = 0;
          end
        endcase
      end
    end
  endgenerate


  always@(op[2], funct[2]) begin
    case (op[2])
      6'h08, 6'h23, 6'h2B:  alu_code = 7'h20;
      6'h04, 6'h05:         alu_code = 7'h22;
      6'h0A:                alu_code = 7'h2A;
      6'h00:
        if (funct[2]==7'h08)
          alu_code = 7'h20;
        else
          alu_code = funct[2];
      default:              alu_code = 0;
    endcase
  end
  

  always@(op[1], funct[1], op[2], zero) begin
    case (op[2])
      6'h04: sel_pc[2] = zero;
      6'h05: sel_pc[2] = !zero;
      default: sel_pc[2] = 0;
    endcase
    
    case (op[1])
      6'h02, 6'h03:
        sel_pc[1:0] = 2'b10;
      6'h00:
        if (funct[1]==7'h08)
          sel_pc[1:0] = 2'b01;
        else
          sel_pc[1:0] = 2'b00;
      default:
        sel_pc[1:0] = 0;
    endcase
  end
  

  assign jr = ((op[1]==0) & (funct[1]==7'h08));
  assign jal = (op[1]==6'h03);
  assign jal_pc = (op[3]==6'h03);
  

  assign sw = (op[1]==6'h2B);
  

  assign use_imm = I_type[1] || L_type[1] || S_type[1];  


  assign load = L_type[3];
  assign wr_mem = (op[3]==6'h2B);
  

  always@(op[4]) begin
    case (op[4])
      6'h00, 6'h08, 6'h0A, 6'h23, 6'h03:
        wr_rf = 1;
      default:
        wr_rf = 0;
    endcase
  end


  wire [2:0] Lchk;
  wire [2:0] Ichk;
  wire [2:0] Rchk;
  
  assign Lchk = { L_type[2], L_type[3], L_type[4] };
  assign Ichk = { I_type[2], I_type[3], I_type[4] };
  assign Rchk = { R_type[2], R_type[3], R_type[4] };
  
  wire [2:0] rd_written;
  assign rd_written = Ichk | Rchk | Lchk;
  

  
  reg [2:0] rs1dep;
  reg [5*3-1:0] rs1_chk;

  always@(J_type[1], rd_written, rs1[1], rd[2], rd[3], rd[4]) begin
    if (rs1[1]!=0 && !J_type[1]) begin
      rs1_chk = ~( {3{rs1[1]}} ^ {rd[2], rd[3], rd[4]} );
      rs1dep = {
        (&rs1_chk[14:10]),
        (&rs1_chk[9:5]),
        (&rs1_chk[4:0])
      } & rd_written;
    end else begin
      rs1_chk = 0;
      rs1dep = 0;
    end
  end
  
  reg [2:0] rs2dep;
  reg [5*3-1:0] rs2_chk;

  always@(R_type[1], B_type[1], rd_written, rs2[1], rd[2], rd[3], rd[4]) begin
    if (rs2[1]!=0 && (R_type[1] || B_type[1])) begin
      rs2_chk = ~( {3{rs2[1]}} ^ {rd[2], rd[3], rd[4]} );
      rs2dep = {
        (&rs2_chk[14:10]),
        (&rs2_chk[9:5]),
        (&rs2_chk[4:0])        
      } & rd_written;
    end else begin
      rs2_chk = 0;
      rs2dep = 0;
    end
  end
  
  reg [2:0] rddep;
  reg [5*3-1:0] rd_chk;

  always@(J_type[1], S_type[1], funct[1], rd_written, rd[1], rd[2], rd[3], rd[4]) begin
    if (rd[1]!=0 && ((J_type[1] && funct[1]==7'h08) || S_type[1]==6'h2B)) begin
      rd_chk = ~( {3{rd[1]}} ^ {rd[2], rd[3], rd[4]} );
      rddep = {
        (&rd_chk[14:10]),
        (&rd_chk[9:5]),
        (&rd_chk[4:0])
      } & rd_written;
    end else begin
      rd_chk = 0;
      rddep = 0;
    end
  end
  

  assign stall = |( (rs1dep | rs2dep | rddep) & Lchk );
  

  always@(J_type[1], op[2], zero) begin
    if ( (op[2]==6'h04 && zero) || (op[2]==6'h05 && !zero) )
      flush = 2'b11;
    else
      if (J_type[1])
        flush = 2'b10;
      else
        flush = 2'b00;
  end
  
  
  reg_fwd FWD_VECTOR (
    .clk(clk),
    .nrst(nrst),
    .fwd_opA0(rs1dep),
    .fwd_opB0(rs2dep),
    .fwd_jr0(rddep),
    .fwd_opA(fwd_opA),
    .fwd_opB(fwd_opB),
    .fwd_sw(fwd_sw),
    .fwd_jr(fwd_jr)
  );
  
  reg32 if_id (
    .clk(clk),
    .nrst(nrst & !flush[1]),
    .en(!stall),
    .data_in(inst_cache[0]),
    .data_out(inst_cache[1])
  );
  
  reg32 id_exe (
    .clk(clk),
    .nrst(nrst & !flush[0] & !stall),
    .en(1'b1),
    .data_in(inst_cache[1]),
    .data_out(inst_cache[2])
  );
  
  reg32 exe_mem (
    .clk(clk),
    .nrst(nrst),
    .en(1'b1),
    .data_in(inst_cache[2]),
    .data_out(inst_cache[3])
  );
  
  reg32 mem_wb (
    .clk(clk),
    .nrst(nrst),
    .en(1'b1),
    .data_in(inst_cache[3]),
    .data_out(inst_cache[4])
  );
    
endmodule
module control (
  input clk,
  input nrst,
  input zero,
  input [31:0] inst,
  output jr,
  output jal,
  output jal_pc,
  output load,
  output wr_mem,
  output use_imm,
  output sw,
  output [`PIPELINE_STAGES*32-1:0] debug_inst,
  output reg [6:0] alu_code,
  output reg [2:0] sel_pc,
  output reg [1:0] flush,
  output reg wr_rf,
  output stall,
  output [2:0] fwd_opA,
  output [2:0] fwd_opB,
  output [2:0] fwd_sw,
  output [2:0] fwd_jr
  );


  genvar i;
  
  wire [5:0] op           [0:4];
  wire [4:0] rd           [0:4];
  wire [4:0] rs1          [0:4];
  wire [4:0] rs2          [0:4];
  wire [6:0] funct        [0:4];
  wire [31:0] inst_cache  [0:4];
  
  assign inst_cache[0] = inst;
  generate
    for (i=0; i<=4; i=i+1) begin
      assign op[i]      = inst_cache[i][5:0];
      assign rd[i]      = inst_cache[i][10:6];
      assign rs1[i]     = inst_cache[i][19:15];
      assign rs2[i]     = inst_cache[i][24:20];
      assign funct[i]   = inst_cache[i][31:25];
    end
  endgenerate
  assign debug_inst = {
    inst_cache[4],
    inst_cache[3],
    inst_cache[2],
    inst_cache[1],
    inst_cache[0]
  };
  

  
  reg [4:0] R_type;
  reg [4:0] I_type;
  reg [4:0] L_type;
  reg [4:0] S_type;
  reg [4:0] B_type;
  reg [4:0] J_type;
  generate
    for (i=0; i<=4; i=i+1) begin
      always@(op[i], funct[i]) begin
        R_type[i] = 0;
        I_type[i] = 0;
        L_type[i] = 0;
        S_type[i] = 0;
        B_type[i] = 0;
        J_type[i] = 0;
        case (op[i])
          6'h00:
            if (funct[i]==7'h08)
              J_type[i] = 1;
            else
              R_type[i] = 1;
          6'h08, 6'h0A:
            I_type[i] = 1;
          6'h23:
            L_type[i] = 1;
          6'h2B:
            S_type[i] = 1;
          6'h04, 6'h05:
            B_type[i] = 1;
          6'h02, 6'h03:
            J_type[i] = 1;
          default: begin
            R_type[i] = 0;
            I_type[i] = 0;
            L_type[i] = 0;
            S_type[i] = 0;
            B_type[i] = 0;
            J_type[i] = 0;
          end
        endcase
      end
    end
  endgenerate


  always@(op[2], funct[2]) begin
    case (op[2])
      6'h08, 6'h23, 6'h2B:  alu_code = 7'h20;
      6'h04, 6'h05:         alu_code = 7'h22;
      6'h0A:                alu_code = 7'h2A;
      6'h00:
        if (funct[2]==7'h08)
          alu_code = 7'h20;
        else
          alu_code = funct[2];
      default:              alu_code = 0;
    endcase
  end
  

  always@(op[1], funct[1], op[2], zero) begin
    case (op[2])
      6'h04: sel_pc[2] = zero;
      6'h05: sel_pc[2] = !zero;
      default: sel_pc[2] = 0;
    endcase
    
    case (op[1])
      6'h02, 6'h03:
        sel_pc[1:0] = 2'b10;
      6'h00:
        if (funct[1]==7'h08)
          sel_pc[1:0] = 2'b01;
        else
          sel_pc[1:0] = 2'b00;
      default:
        sel_pc[1:0] = 0;
    endcase
  end
  

  assign jr = ((op[1]==0) & (funct[1]==7'h08));
  assign jal = (op[1]==6'h03);
  assign jal_pc = (op[3]==6'h03);
  

  assign sw = (op[1]==6'h2B);
  

  assign use_imm = I_type[1] || L_type[1] || S_type[1];  


  assign load = L_type[3];
  assign wr_mem = (op[3]==6'h2B);
  

  always@(op[4]) begin
    case (op[4])
      6'h00, 6'h08, 6'h0A, 6'h23, 6'h03:
        wr_rf = 1;
      default:
        wr_rf = 0;
    endcase
  end


  wire [2:0] Lchk;
  wire [2:0] Ichk;
  wire [2:0] Rchk;
  
  assign Lchk = { L_type[2], L_type[3], L_type[4] };
  assign Ichk = { I_type[2], I_type[3], I_type[4] };
  assign Rchk = { R_type[2], R_type[3], R_type[4] };
  
  wire [2:0] rd_written;
  assign rd_written = Ichk | Rchk | Lchk;
  

  
  reg [2:0] rs1dep;
  reg [5*3-1:0] rs1_chk;

  always@(J_type[1], rd_written, rs1[1], rd[2], rd[3], rd[4]) begin
    if (rs1[1]!=0 && !J_type[1]) begin
      rs1_chk = ~( {3{rs1[1]}} ^ {rd[2], rd[3], rd[4]} );
      rs1dep = {
        (&rs1_chk[14:10]),
        (&rs1_chk[9:5]),
        (&rs1_chk[4:0])
      } & rd_written;
    end else begin
      rs1_chk = 0;
      rs1dep = 0;
    end
  end
  
  reg [2:0] rs2dep;
  reg [5*3-1:0] rs2_chk;

  always@(R_type[1], B_type[1], rd_written, rs2[1], rd[2], rd[3], rd[4]) begin
    if (rs2[1]!=0 && (R_type[1] || B_type[1])) begin
      rs2_chk = ~( {3{rs2[1]}} ^ {rd[2], rd[3], rd[4]} );
      rs2dep = {
        (&rs2_chk[14:10]),
        (&rs2_chk[9:5]),
        (&rs2_chk[4:0])        
      } & rd_written;
    end else begin
      rs2_chk = 0;
      rs2dep = 0;
    end
  end
  
  reg [2:0] rddep;
  reg [5*3-1:0] rd_chk;

  always@(J_type[1], S_type[1], funct[1], rd_written, rd[1], rd[2], rd[3], rd[4]) begin
    if (rd[1]!=0 && ((J_type[1] && funct[1]==7'h08) || S_type[1]==6'h2B)) begin
      rd_chk = ~( {3{rd[1]}} ^ {rd[2], rd[3], rd[4]} );
      rddep = {
        (&rd_chk[14:10]),
        (&rd_chk[9:5]),
        (&rd_chk[4:0])
      } & rd_written;
    end else begin
      rd_chk = 0;
      rddep = 0;
    end
  end
  

  assign stall = |( (rs1dep | rs2dep | rddep) & Lchk );
  

  always@(J_type[1], op[2], zero) begin
    if ( (op[2]==6'h04 && zero) || (op[2]==6'h05 && !zero) )
      flush = 2'b11;
    else
      if (J_type[1])
        flush = 2'b10;
      else
        flush = 2'b00;
  end
  
  
  reg_fwd FWD_VECTOR (
    .clk(clk),
    .nrst(nrst),
    .fwd_opA0(rs1dep),
    .fwd_opB0(rs2dep),
    .fwd_jr0(rddep),
    .fwd_opA(fwd_opA),
    .fwd_opB(fwd_opB),
    .fwd_sw(fwd_sw),
    .fwd_jr(fwd_jr)
  );
  
  reg32 if_id (
    .clk(clk),
    .nrst(nrst & !flush[1]),
    .en(!stall),
    .data_in(inst_cache[0]),
    .data_out(inst_cache[1])
  );
  
  reg32 id_exe (
    .clk(clk),
    .nrst(nrst & !flush[0] & !stall),
    .en(1'b1),
    .data_in(inst_cache[1]),
    .data_out(inst_cache[2])
  );
  
  reg32 exe_mem (
    .clk(clk),
    .nrst(nrst),
    .en(1'b1),
    .data_in(inst_cache[2]),
    .data_out(inst_cache[3])
  );
  
  reg32 mem_wb (
    .clk(clk),
    .nrst(nrst),
    .en(1'b1),
    .data_in(inst_cache[3]),
    .data_out(inst_cache[4])
  );
    
endmodule