data/full_repos/permissive/202473002/Stereo.srcs/sources_1/imports/FPGA/alu32.v
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data/verilator_xmls/451dba7a-3656-43ba-bc1c-36aa3e2a7029.xml
module alu32(out, overflow, zero, negative, inA, inB, control);
    output [31:0] out;
    output        overflow, zero, negative;
    input  [31:0] inA, inB;
    input   [2:0] control;

    wire   [32:0] inAE = { inA[31], inA };
    wire   [32:0] inBE = { inB[31], inB };
    wire   [32:0] outE = (({33{(control == `ALU_AND)}} &  (inAE & inBE)) |
                          ({33{(control == `ALU_OR)}}  &  (inAE | inBE)) |
                          ({33{(control == `ALU_XOR)}} &  (inAE ^ inBE)) |
                          ({33{(control == `ALU_NOR)}} & ~(inAE | inBE)) |
                          ({33{(control == `ALU_ADD)}} &  (inAE + inBE)) |
                          ({33{(control == `ALU_SUB)}} &  (inAE - inBE)));

    assign out = outE[31:0];
    assign zero = (out[31:18] == 14'b0) & (out[17:1] == 17'd0) & ~out[0];
    xor  x1(negative, out[31], 1'b0);
    xor  x2(overflow, out[31], outE[32]);
   
endmodule
module alu32(out, overflow, zero, negative, inA, inB, control);

    output [31:0] out;
    output        overflow, zero, negative;
    input  [31:0] inA, inB;
    input   [2:0] control;

    wire   [32:0] inAE = { inA[31], inA };
    wire   [32:0] inBE = { inB[31], inB };
    wire   [32:0] outE = (({33{(control == `ALU_AND)}} &  (inAE & inBE)) |
                          ({33{(control == `ALU_OR)}}  &  (inAE | inBE)) |
                          ({33{(control == `ALU_XOR)}} &  (inAE ^ inBE)) |
                          ({33{(control == `ALU_NOR)}} & ~(inAE | inBE)) |
                          ({33{(control == `ALU_ADD)}} &  (inAE + inBE)) |
                          ({33{(control == `ALU_SUB)}} &  (inAE - inBE)));

    assign out = outE[31:0];
    assign zero = (out[31:18] == 14'b0) & (out[17:1] == 17'd0) & ~out[0];
    xor  x1(negative, out[31], 1'b0);
    xor  x2(overflow, out[31], outE[32]);
   
endmodule