data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v
1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n             ^\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n              ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n                ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in replications.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n                        ^\n%Error: Exiting due to 4 warning(s)\n'
module digital_clock(
    input clk,
    input [13:0] swt,
    input reset,
    input myset,
    output reg [6:0] C,
    output reg DP,
    output reg [7:0] AN
    );
    

    wire [6:0] C1;
    wire [6:0] C2;
    wire [6:0] C3;
    wire [6:0] C4;
    

    reg [3:0] T1;
    reg [3:0] T2;
    reg [3:0] T3;
    reg [3:0] T4;
    

    reg [1:0] cnt;
    
    wire myclk1,myclk2;
    clkdiv1 c1(clk,myclk1);
    clkdiv2 c2(clk,myclk2);
    
    always@(posedge myclk1)
        DP<=~DP;
    
    always@(posedge myclk1, posedge reset, posedge myset)
    begin
    if(reset)
    begin
        T4<=4'b0000;
        T3<=4'b0000;
        T2<=4'b0000;
        T1<=4'b0000;
    end  
    else
    if(myset)
    begin
        T4<={0,0,swt[13],swt[12]};
        T3<=swt[11:8];
        T2<=swt[7:4];
        T1<=swt[3:0];
    end  
    else
        if(T4==4'b0010&T3==4'b0011&T2==4'b0101&T1==4'b1001)
        begin
            T4<=4'b0000;
            T3<=4'b0000;
            T2<=4'b0000;
            T1<=4'b0000;
        end
        else
            if(T3==4'b1001&T2==4'b0101&T1==4'b1001)
            begin
                T4<=T4+1;
                T3<=4'b0000;
                T2<=4'b0000;
                T1<=4'b0000;
            end
            else
                if(T2==4'b0101&T1==4'b1001)
                begin
                    T4<=T4;
                    T3<=T3+1;
                    T2<=4'b0000;
                    T1<=4'b0000;
                end
                else
                    if(T1==4'b1001)
                    begin
                        T4<=T4;
                        T3<=T3;
                        T2<=T2+1;
                        T1<=4'b0000;
                    end
                    else
                    begin
                        T4<=T4;
                        T3<=T3;
                        T2<=T2;
                        T1<=T1+1;
                    end
    end
    

    BCD_7_segment_display b1(T1[3:0],C1[6:0]);
    BCD_7_segment_display b2(T2[3:0],C2[6:0]);
    BCD_7_segment_display b3(T3[3:0],C3[6:0]);
    BCD_7_segment_display b4(T4[3:0],C4[6:0]);
    

    always@(posedge myclk2)
    begin
        case(cnt)
        2'b00:
            begin
            AN<=8'b11111110;
            C<=C1;
            cnt<=cnt+1;
            end
        2'b01:
            begin
            AN<=8'b11111101;
            C<=C2;
            cnt<=cnt+1;
            end
        2'b10:
            begin
            AN<=8'b11111011;
            C<=C3;
            cnt<=cnt+1;
            end
        2'b11:
            begin
            AN<=8'b11110111;
            C<=C4;
            cnt<=cnt+1;
            end
        endcase
    end
    
endmodule
module digital_clock(
    input clk,
    input [13:0] swt,
    input reset,
    input myset,
    output reg [6:0] C,
    output reg DP,
    output reg [7:0] AN
    );

    

    wire [6:0] C1;
    wire [6:0] C2;
    wire [6:0] C3;
    wire [6:0] C4;
    

    reg [3:0] T1;
    reg [3:0] T2;
    reg [3:0] T3;
    reg [3:0] T4;
    

    reg [1:0] cnt;
    
    wire myclk1,myclk2;
    clkdiv1 c1(clk,myclk1);
    clkdiv2 c2(clk,myclk2);
    
    always@(posedge myclk1)
        DP<=~DP;
    
    always@(posedge myclk1, posedge reset, posedge myset)
    begin
    if(reset)
    begin
        T4<=4'b0000;
        T3<=4'b0000;
        T2<=4'b0000;
        T1<=4'b0000;
    end  
    else
    if(myset)
    begin
        T4<={0,0,swt[13],swt[12]};
        T3<=swt[11:8];
        T2<=swt[7:4];
        T1<=swt[3:0];
    end  
    else
        if(T4==4'b0010&T3==4'b0011&T2==4'b0101&T1==4'b1001)
        begin
            T4<=4'b0000;
            T3<=4'b0000;
            T2<=4'b0000;
            T1<=4'b0000;
        end
        else
            if(T3==4'b1001&T2==4'b0101&T1==4'b1001)
            begin
                T4<=T4+1;
                T3<=4'b0000;
                T2<=4'b0000;
                T1<=4'b0000;
            end
            else
                if(T2==4'b0101&T1==4'b1001)
                begin
                    T4<=T4;
                    T3<=T3+1;
                    T2<=4'b0000;
                    T1<=4'b0000;
                end
                else
                    if(T1==4'b1001)
                    begin
                        T4<=T4;
                        T3<=T3;
                        T2<=T2+1;
                        T1<=4'b0000;
                    end
                    else
                    begin
                        T4<=T4;
                        T3<=T3;
                        T2<=T2;
                        T1<=T1+1;
                    end
    end
    

    BCD_7_segment_display b1(T1[3:0],C1[6:0]);
    BCD_7_segment_display b2(T2[3:0],C2[6:0]);
    BCD_7_segment_display b3(T3[3:0],C3[6:0]);
    BCD_7_segment_display b4(T4[3:0],C4[6:0]);
    

    always@(posedge myclk2)
    begin
        case(cnt)
        2'b00:
            begin
            AN<=8'b11111110;
            C<=C1;
            cnt<=cnt+1;
            end
        2'b01:
            begin
            AN<=8'b11111101;
            C<=C2;
            cnt<=cnt+1;
            end
        2'b10:
            begin
            AN<=8'b11111011;
            C<=C3;
            cnt<=cnt+1;
            end
        2'b11:
            begin
            AN<=8'b11110111;
            C<=C4;
            cnt<=cnt+1;
            end
        endcase
    end
    
endmodule