data/full_repos/permissive/173670949/uart_test/test.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/173670949/uart_test/test.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #(c_BIT_PERIOD);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173670949/uart_test/test.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/173670949/uart_test/test.v:37: Unsupported: Ignoring delay on this delayed statement.\n          #(c_BIT_PERIOD);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/173670949/uart_test/test.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #(c_BIT_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/173670949/uart_test/test.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;\n    ^\n%Error: data/full_repos/permissive/173670949/uart_test/test.v:74: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/173670949/uart_test/test.v:75: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, test);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/173670949/uart_test/test.v:77: syntax error, unexpected \'@\'\n      @(posedge r_Clock);\n      ^\n%Error: data/full_repos/permissive/173670949/uart_test/test.v:81: syntax error, unexpected \'@\'\n      @(posedge r_Clock);\n      ^\n%Error: data/full_repos/permissive/173670949/uart_test/test.v:83: syntax error, unexpected \'@\'\n      @(posedge w_Tx_Done);\n      ^\n%Error: data/full_repos/permissive/173670949/uart_test/test.v:88: syntax error, unexpected \'@\'\n      @(posedge r_Clock);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/173670949/uart_test/test.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #1000\n      ^\n%Error: Exiting due to 6 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();




  parameter c_CLOCK_PERIOD_NS = 100;
  parameter c_CLKS_PER_BIT    = 87;
  parameter c_BIT_PERIOD      = 8600;

  reg r_Clock = 0;
  reg r_Tx_DV = 0;
  wire w_Tx_Done;
  reg [7:0] r_Tx_Byte = 0;
  reg r_Rx_Serial = 1;
  wire [7:0] w_Rx_Byte;



  task UART_WRITE_BYTE;
    input [7:0] i_Data;
    integer     ii;
    begin


      r_Rx_Serial <= 1'b0;
      #(c_BIT_PERIOD);
      #1000;


      for (ii=0; ii<8; ii=ii+1)
        begin
          r_Rx_Serial <= i_Data[ii];
          #(c_BIT_PERIOD);
        end


      r_Rx_Serial <= 1'b1;
      #(c_BIT_PERIOD);
     end
  endtask


  uart_rx #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_INST
    (.SER_CLK(r_Clock),
     .RX_SERIAL(r_Rx_Serial),
     .RX_DV(),
     .RX_BYTE(w_Rx_Byte)
     );






  uart_tx2 #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_INST
    (.CLK(r_Clock),
     .TX_DV(r_Tx_DV),
     .TX_BYTE(r_Tx_Byte),
     .TX_DATA(),
     .DONE(w_Tx_Done)
     );


  always
    #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;



  initial begin
      $dumpfile("test.vcd");
      $dumpvars(0, test);

      @(posedge r_Clock);
      @(posedge r_Clock);
      r_Tx_DV <= 1'b1;
      r_Tx_Byte <= 8'b10101010;
      @(posedge r_Clock);
      r_Tx_DV <= 1'b0;
      @(posedge w_Tx_Done);


      @(posedge r_Clock);
      UART_WRITE_BYTE(8'h3F);
      @(posedge r_Clock);


      if (w_Rx_Byte == 8'h3F) begin
        $display("Test Passed - Correct Byte Received");
      end
      else begin
        $display("Test Failed - Incorrect Byte Received");
      end

      #1000
      $finish;
    end

endmodule
module test();





  parameter c_CLOCK_PERIOD_NS = 100;
  parameter c_CLKS_PER_BIT    = 87;
  parameter c_BIT_PERIOD      = 8600;

  reg r_Clock = 0;
  reg r_Tx_DV = 0;
  wire w_Tx_Done;
  reg [7:0] r_Tx_Byte = 0;
  reg r_Rx_Serial = 1;
  wire [7:0] w_Rx_Byte;



  task UART_WRITE_BYTE;
    input [7:0] i_Data;
    integer     ii;
    begin


      r_Rx_Serial <= 1'b0;
      #(c_BIT_PERIOD);
      #1000;


      for (ii=0; ii<8; ii=ii+1)
        begin
          r_Rx_Serial <= i_Data[ii];
          #(c_BIT_PERIOD);
        end


      r_Rx_Serial <= 1'b1;
      #(c_BIT_PERIOD);
     end
  endtask


  uart_rx #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_INST
    (.SER_CLK(r_Clock),
     .RX_SERIAL(r_Rx_Serial),
     .RX_DV(),
     .RX_BYTE(w_Rx_Byte)
     );






  uart_tx2 #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_INST
    (.CLK(r_Clock),
     .TX_DV(r_Tx_DV),
     .TX_BYTE(r_Tx_Byte),
     .TX_DATA(),
     .DONE(w_Tx_Done)
     );


  always
    #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;



  initial begin
      $dumpfile("test.vcd");
      $dumpvars(0, test);

      @(posedge r_Clock);
      @(posedge r_Clock);
      r_Tx_DV <= 1'b1;
      r_Tx_Byte <= 8'b10101010;
      @(posedge r_Clock);
      r_Tx_DV <= 1'b0;
      @(posedge w_Tx_Done);


      @(posedge r_Clock);
      UART_WRITE_BYTE(8'h3F);
      @(posedge r_Clock);


      if (w_Rx_Byte == 8'h3F) begin
        $display("Test Passed - Correct Byte Received");
      end
      else begin
        $display("Test Failed - Incorrect Byte Received");
      end

      #1000
      $finish;
    end

endmodule