data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:63: Cannot find include file: pci_constants.v\n`include "pci_constants.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v.sv\n             pci_constants.v\n             pci_constants.v.v\n             pci_constants.v.sv\n             obj_dir/pci_constants.v\n             obj_dir/pci_constants.v.v\n             obj_dir/pci_constants.v.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:65: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:100: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in  ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:101: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in  ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:102: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in  ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:103: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in  ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:104: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in  ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:105: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in  ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:106: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:107: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:108: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:109: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:110: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:111: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:112: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:113: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:114: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:115: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:116: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:117: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\ninput [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in   ;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v:178: Define or directive not defined: \'`WB_NUM_OF_DEC_ADDR_LINES\'\npci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec1\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module pci_wb_addr_mux
(
    `ifdef REGISTER_WBS_OUTPUTS
    clk_in,
    reset_in,
    sample_address_in,
    `endif
    address_in,
    bar0_in,
    bar1_in,
    bar2_in,
    bar3_in,
    bar4_in,
    bar5_in,
    am0_in,
    am1_in,
    am2_in,
    am3_in,
    am4_in,
    am5_in,
    ta0_in,
    ta1_in,
    ta2_in,
    ta3_in,
    ta4_in,
    ta5_in,
    at_en_in,
    hit_out,
    address_out
);

input [31:0] address_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in   ;
input [5:0]  at_en_in ;
output [5:0] hit_out  ;
output [31:0] address_out ;
reg    [31:0] address_out ;

wire [31:0] addr0 ;
wire [31:0] addr1 ;
wire [31:0] addr2 ;
wire [31:0] addr3 ;
wire [31:0] addr4 ;
wire [31:0] addr5 ;

wire [5:0] hit ;
assign hit_out = hit ;

`ifdef REGISTER_WBS_OUTPUTS
    input clk_in, reset_in, sample_address_in ;

    reg [31:0] address ;
    always@(posedge clk_in or posedge reset_in)
    begin
       if ( reset_in )
           address <= #`FF_DELAY 0 ;
       else
       if ( sample_address_in )
           address <= #`FF_DELAY address_in ;
    end
`else
    wire [31:0] address = address_in ;
`endif

`ifdef GUEST
    `ifdef NO_CNF_IMAGE
    `else
        `define PCI_WB_ADDR_MUX_DEC0_INCLUDE
    `endif
`else
`ifdef HOST
    `define PCI_WB_ADDR_MUX_DEC0_INCLUDE
`endif
`endif

`ifdef PCI_WB_ADDR_MUX_DEC0_INCLUDE
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec0
    (
     .hit       (hit[0]),
     .addr_out  (addr0),
     .addr_in   (address),
     .base_addr (bar0_in),
     .mask_addr (am0_in),
     .tran_addr (ta0_in),
     .at_en     (1'b0)
    ) ;
`else

    assign hit[0] = 1'b0 ;
    assign addr0  = 32'h0000_0000 ;
`endif


pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec1
(
 .hit       (hit[1]),
 .addr_out  (addr1),
 .addr_in   (address),
 .base_addr (bar1_in),
 .mask_addr (am1_in),
 .tran_addr (ta1_in),
 .at_en     (at_en_in[1])
) ;

`ifdef WB_IMAGE2
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec2
    (
     .hit       (hit[2]),
     .addr_out  (addr2),
     .addr_in   (address),
     .base_addr (bar2_in),
     .mask_addr (am2_in),
     .tran_addr (ta2_in),
     .at_en     (at_en_in[2])
    ) ;

`else
    assign hit[2] = 1'b0 ;
    assign addr2  = 0 ;
`endif

`ifdef WB_IMAGE3
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec3
    (
     .hit       (hit[3]),
     .addr_out  (addr3),
     .addr_in   (address),
     .base_addr (bar3_in),
     .mask_addr (am3_in),
     .tran_addr (ta3_in),
     .at_en     (at_en_in[3])
    ) ;
`else
    assign hit[3] = 1'b0 ;
    assign addr3  = 0 ;
`endif

`ifdef WB_IMAGE4
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec4
    (
     .hit       (hit[4]),
     .addr_out  (addr4),
     .addr_in   (address),
     .base_addr (bar4_in),
     .mask_addr (am4_in),
     .tran_addr (ta4_in),
     .at_en     (at_en_in[4])
    ) ;
`else
    assign hit[4] = 1'b0 ;
    assign addr4  = 0 ;
`endif

`ifdef WB_IMAGE5
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec5
    (
     .hit       (hit[5]),
     .addr_out  (addr5),
     .addr_in   (address),
     .base_addr (bar5_in),
     .mask_addr (am5_in),
     .tran_addr (ta5_in),
     .at_en     (at_en_in[5])
    ) ;
`else
    assign hit[5] = 1'b0 ;
    assign addr5  = 0 ;
`endif


always@
(
 hit or
 addr0 or
 addr1 or
 addr2 or
 addr3 or
 addr4 or
 addr5
)
begin
    case ( {hit[5:2], hit[0]} )
        5'b0_0_0_0_1: address_out = addr0 ;
        5'b0_0_0_1_0: address_out = addr2 ;
        5'b0_0_1_0_0: address_out = addr3 ;
        5'b0_1_0_0_0: address_out = addr4 ;
        5'b1_0_0_0_0: address_out = addr5 ;



        default:      address_out = addr1 ;
    endcase
end

endmodule
module pci_wb_addr_mux
(
    `ifdef REGISTER_WBS_OUTPUTS
    clk_in,
    reset_in,
    sample_address_in,
    `endif
    address_in,
    bar0_in,
    bar1_in,
    bar2_in,
    bar3_in,
    bar4_in,
    bar5_in,
    am0_in,
    am1_in,
    am2_in,
    am3_in,
    am4_in,
    am5_in,
    ta0_in,
    ta1_in,
    ta2_in,
    ta3_in,
    ta4_in,
    ta5_in,
    at_en_in,
    hit_out,
    address_out
);


input [31:0] address_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in   ;
input [5:0]  at_en_in ;
output [5:0] hit_out  ;
output [31:0] address_out ;
reg    [31:0] address_out ;

wire [31:0] addr0 ;
wire [31:0] addr1 ;
wire [31:0] addr2 ;
wire [31:0] addr3 ;
wire [31:0] addr4 ;
wire [31:0] addr5 ;

wire [5:0] hit ;
assign hit_out = hit ;

`ifdef REGISTER_WBS_OUTPUTS
    input clk_in, reset_in, sample_address_in ;

    reg [31:0] address ;
    always@(posedge clk_in or posedge reset_in)
    begin
       if ( reset_in )
           address <= #`FF_DELAY 0 ;
       else
       if ( sample_address_in )
           address <= #`FF_DELAY address_in ;
    end
`else
    wire [31:0] address = address_in ;
`endif

`ifdef GUEST
    `ifdef NO_CNF_IMAGE
    `else
        `define PCI_WB_ADDR_MUX_DEC0_INCLUDE
    `endif
`else
`ifdef HOST
    `define PCI_WB_ADDR_MUX_DEC0_INCLUDE
`endif
`endif

`ifdef PCI_WB_ADDR_MUX_DEC0_INCLUDE
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec0
    (
     .hit       (hit[0]),
     .addr_out  (addr0),
     .addr_in   (address),
     .base_addr (bar0_in),
     .mask_addr (am0_in),
     .tran_addr (ta0_in),
     .at_en     (1'b0)
    ) ;
`else

    assign hit[0] = 1'b0 ;
    assign addr0  = 32'h0000_0000 ;
`endif


pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec1
(
 .hit       (hit[1]),
 .addr_out  (addr1),
 .addr_in   (address),
 .base_addr (bar1_in),
 .mask_addr (am1_in),
 .tran_addr (ta1_in),
 .at_en     (at_en_in[1])
) ;

`ifdef WB_IMAGE2
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec2
    (
     .hit       (hit[2]),
     .addr_out  (addr2),
     .addr_in   (address),
     .base_addr (bar2_in),
     .mask_addr (am2_in),
     .tran_addr (ta2_in),
     .at_en     (at_en_in[2])
    ) ;

`else
    assign hit[2] = 1'b0 ;
    assign addr2  = 0 ;
`endif

`ifdef WB_IMAGE3
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec3
    (
     .hit       (hit[3]),
     .addr_out  (addr3),
     .addr_in   (address),
     .base_addr (bar3_in),
     .mask_addr (am3_in),
     .tran_addr (ta3_in),
     .at_en     (at_en_in[3])
    ) ;
`else
    assign hit[3] = 1'b0 ;
    assign addr3  = 0 ;
`endif

`ifdef WB_IMAGE4
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec4
    (
     .hit       (hit[4]),
     .addr_out  (addr4),
     .addr_in   (address),
     .base_addr (bar4_in),
     .mask_addr (am4_in),
     .tran_addr (ta4_in),
     .at_en     (at_en_in[4])
    ) ;
`else
    assign hit[4] = 1'b0 ;
    assign addr4  = 0 ;
`endif

`ifdef WB_IMAGE5
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec5
    (
     .hit       (hit[5]),
     .addr_out  (addr5),
     .addr_in   (address),
     .base_addr (bar5_in),
     .mask_addr (am5_in),
     .tran_addr (ta5_in),
     .at_en     (at_en_in[5])
    ) ;
`else
    assign hit[5] = 1'b0 ;
    assign addr5  = 0 ;
`endif


always@
(
 hit or
 addr0 or
 addr1 or
 addr2 or
 addr3 or
 addr4 or
 addr5
)
begin
    case ( {hit[5:2], hit[0]} )
        5'b0_0_0_0_1: address_out = addr0 ;
        5'b0_0_0_1_0: address_out = addr2 ;
        5'b0_0_1_0_0: address_out = addr3 ;
        5'b0_1_0_0_0: address_out = addr4 ;
        5'b1_0_0_0_0: address_out = addr5 ;



        default:      address_out = addr1 ;
    endcase
end

endmodule