data/full_repos/permissive/160024456/day03/part2_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160024456/day03/part2_test.v:8: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = !clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/160024456/day03/part2_test.v:11: Unsupported or unknown PLI call: $monitor\n    $monitor("solution (off by one)=", dut.solution, ", done=", dut.done, ", counter2=", dut.counter2);\n    ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module part2_test;

  reg clk = 0;
  wire [10:0] solution;

  part2 dut (.clk(clk));

  always #1 clk = !clk;

  initial begin
    $monitor("solution (off by one)=", dut.solution, ", done=", dut.done, ", counter2=", dut.counter2);
  end

  always @(posedge clk) begin
    if (dut.done == 1) begin
      $finish;
    end
  end
endmodule
module part2_test;


  reg clk = 0;
  wire [10:0] solution;

  part2 dut (.clk(clk));

  always #1 clk = !clk;

  initial begin
    $monitor("solution (off by one)=", dut.solution, ", done=", dut.done, ", counter2=", dut.counter2);
  end

  always @(posedge clk) begin
    if (dut.done == 1) begin
      $finish;
    end
  end
endmodule