data/full_repos/permissive/20289584/cup_TB.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/20289584/cup_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\nalways #20 clk  = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20289584/cup_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\nalways #10  rst = 1;\n       ^\n%Error: data/full_repos/permissive/20289584/cup_TB.v:23: Cannot find file containing module: \'ALL\'\n ALL test(.ddd(df),.ddd0(df_0),.clk_in(clk),.rst(rst),.pa(pb_s),.pb(pb_d),.pc(pb_h),.sell(ssel),.q0(q0),.q1(q1),.q2(q2),.q3(q3),.q4(q4),.q5(q5),.clkt(Carry),.a(a),.ff(seeel));\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/20289584,data/full_repos/permissive/20289584/ALL\n             data/full_repos/permissive/20289584,data/full_repos/permissive/20289584/ALL.v\n             data/full_repos/permissive/20289584,data/full_repos/permissive/20289584/ALL.sv\n             ALL\n             ALL.v\n             ALL.sv\n             obj_dir/ALL\n             obj_dir/ALL.v\n             obj_dir/ALL.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cup_TB;



parameter Bitwidth = 4;



reg clk,rst;
reg pb_s,pb_d,pb_h;
reg df,df_0,ed;
reg [1:0]ssel;
wire [1:0] a,seee1;
wire  pc,pd,pe,pf,q,pin_nameaaa;
wire [3:0] q0,q1,q2,q3,q4,q5;
wire [Bitwidth-1:0] CountOut;
wire [Bitwidth-1:0] CountOut1;
wire Carry;


 ALL test(.ddd(df),.ddd0(df_0),.clk_in(clk),.rst(rst),.pa(pb_s),.pb(pb_d),.pc(pb_h),.sell(ssel),.q0(q0),.q1(q1),.q2(q2),.q3(q3),.q4(q4),.q5(q5),.clkt(Carry),.a(a),.ff(seeel));

initial
begin
	pb_h=1;
	pb_d=1;
	pb_s=1;
	df = 0;
	df_0 = 0;
	clk = 0;
	rst = 0;
	ssel = 0;
end
always #20 clk  = ~clk;
always #10  rst = 1;

endmodule
module cup_TB;




parameter Bitwidth = 4;



reg clk,rst;
reg pb_s,pb_d,pb_h;
reg df,df_0,ed;
reg [1:0]ssel;
wire [1:0] a,seee1;
wire  pc,pd,pe,pf,q,pin_nameaaa;
wire [3:0] q0,q1,q2,q3,q4,q5;
wire [Bitwidth-1:0] CountOut;
wire [Bitwidth-1:0] CountOut1;
wire Carry;


 ALL test(.ddd(df),.ddd0(df_0),.clk_in(clk),.rst(rst),.pa(pb_s),.pb(pb_d),.pc(pb_h),.sell(ssel),.q0(q0),.q1(q1),.q2(q2),.q3(q3),.q4(q4),.q5(q5),.clkt(Carry),.a(a),.ff(seeel));

initial
begin
	pb_h=1;
	pb_d=1;
	pb_s=1;
	df = 0;
	df_0 = 0;
	clk = 0;
	rst = 0;
	ssel = 0;
end
always #20 clk  = ~clk;
always #10  rst = 1;

endmodule