data/full_repos/permissive/151863926/src/tb_main.v
 line:72: before: "("
1: b'%Error: data/full_repos/permissive/151863926/src/tb_main.v:5: Cannot find include file: register_file_address_space.v\n    `include "register_file_address_space.v" \n             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151863926/src,data/full_repos/permissive/151863926/register_file_address_space.v\n             data/full_repos/permissive/151863926/src,data/full_repos/permissive/151863926/register_file_address_space.v.v\n             data/full_repos/permissive/151863926/src,data/full_repos/permissive/151863926/register_file_address_space.v.sv\n             register_file_address_space.v\n             register_file_address_space.v.v\n             register_file_address_space.v.sv\n             obj_dir/register_file_address_space.v\n             obj_dir/register_file_address_space.v.v\n             obj_dir/register_file_address_space.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/151863926/src/tb_main.v:11: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk_sys = ~clk_sys;  \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/151863926/src/tb_main.v:13: Unsupported: Ignoring delay on this delayed statement.\n    always #8 clk_adc = ~clk_adc;  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/151863926/src/tb_main.v:15: Unsupported: Ignoring delay on this delayed statement.\n    initial #200 rst = 0;\n            ^\n%Error: data/full_repos/permissive/151863926/src/tb_main.v:27: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    wire [15:0] do;\n                ^~\n%Error: data/full_repos/permissive/151863926/src/tb_main.v:30: syntax error, unexpected \'@\'\n        @(negedge rst);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/151863926/src/tb_main.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/151863926/src/tb_main.v:32: syntax error, unexpected \'@\'\n        repeat (10) @(posedge clk_sys);\n                    ^\n%Error: data/full_repos/permissive/151863926/src/tb_main.v:199: syntax error, unexpected \'@\'\n        repeat (500) @(posedge clk_sys);\n                     ^\n%Error: data/full_repos/permissive/151863926/src/tb_main.v:202: syntax error, unexpected \'@\'\n        @(posedge clk_sys);\n        ^\n%Error: data/full_repos/permissive/151863926/src/tb_main.v:229: syntax error, unexpected \'@\'\n        repeat (500) @(posedge clk_sys);\n                     ^\n%Error: data/full_repos/permissive/151863926/src/tb_main.v:232: syntax error, unexpected \'@\'\n        @(posedge clk_sys);\n        ^\n%Error: data/full_repos/permissive/151863926/src/tb_main.v:269: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n        .do_o(do),                       \n              ^~\n%Error: data/full_repos/permissive/151863926/src/tb_main.v:372: syntax error, unexpected \'@\'\n        @(posedge sns_start_roi);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/151863926/src/tb_main.v:373: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/151863926/src/tb_main.v:376: Unsupported: Ignoring delay on this delayed statement.\n        #(2692800/2-400*1000);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/151863926/src/tb_main.v:378: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: Exiting due to 10 error(s), 7 warning(s)\n'
module tb();

    `include "register_file_address_space.v"
    
    reg clk_sys = 1;
    reg clk_adc = 1;
    reg rst = 1;

    always #5 clk_sys = ~clk_sys;

    always #8 clk_adc = ~clk_adc;
    
    initial #200 rst = 0;
    
    wire spi_SCK;
    wire spi_MOSI;
    wire spi_MISO;
    wire spi_CSN;
    
    wire di_req;
    reg  [15:0] di = 16'hXXXX;
    reg  wren = 0;
    wire wr_ack;
    wire do_valid;
    wire [15:0] do;
    
    initial begin
        @(negedge rst);
        #1;
        repeat (10) @(posedge clk_sys);
        


        @(posedge clk_sys);
        di = 16'hXXXX;
        wren = 0;


        



        





        







        
        repeat (500) @(posedge clk_sys);
        di = {RF_WRITE_BIT, ADDRESS_MODLED_PHASE, 8'h01};
        wren = 1;
        @(posedge clk_sys);
        wren = 0;
        























        
        repeat (500) @(posedge clk_sys);
        di = {RF_WRITE_BIT, ADDRESS_START_CYCLE, 8'h01};
        wren = 1;
        @(posedge clk_sys);
        wren = 0;
        







        
    end

    spi_master #(   
        .N(16),
        .CPOL(1),
        .CPHA(1),
        .PREFETCH(2),
        .SPI_2X_CLK_DIV(5)
    )
    spi_master (  
        .sclk_i(clk_sys),
        .pclk_i(clk_sys),
        .rst_i(rst),
        

        .spi_ssel_o(spi_CSN),
        .spi_sck_o(spi_SCK),
        .spi_mosi_o(spi_MOSI),
        .spi_miso_i(spi_MISO),
        

        .di_req_o(di_req),
        .di_i(di),
        .wren_i(wren),
        .wr_ack_o(wr_ack),
        .do_valid_o(do_valid),
        .do_o(do),
        
        .sck_ena_o(),
        .sck_ena_ce_o(),
        .do_transfer_o(),
        .wren_o(),
        .rx_bit_reg_o(),
        .state_dbg_o(),
        .core_clk_o(),
        .core_n_clk_o(),
        .core_ce_o(),
        .core_n_ce_o(),
        .sh_reg_dbg_o()
    );                      

    wire [15:0] PPID;
    wire PPIFS1;
    wire PPIFS2;
    wire PPIFS3;

    wire ppi_clk;
    
    wire sns_start_roi;
    reg  sns_enable_roi = 1'b0;
    wire sns_clk_roi;
    wire sns_hold;
    wire sns_reset_ccd;
    wire sns_sel_sr;
    wire sns_modsel;
    wire sns_modled;
    
    wire sns_ce_a;
    wire sns_ce_d;
    wire sns_sclk;
    reg  sns_sdi = 1;
    wire sns_sdo;
    
    wire adc_sdata_i;
    reg  adc_sdata_o = 1;
    wire adc_sdata_oen;
    wire adc_sclk;
    wire adc_sload;
    
    reg  [7:0] adc_data;
    always @(posedge clk_adc) adc_data <= $random;
    wire adc_sclk2;
    wire adc_sclk1;
    wire adc_cclk;
    
    main main
    (
        .clk_sys(clk_sys),
        .clk_adc(clk_adc),
        .rst(rst),
        

        .cpu_spi_SCK (spi_SCK),
        .cpu_spi_MOSI(spi_MOSI),
        .cpu_spi_MISO(spi_MISO),
        .cpu_spi_CSN (spi_CSN),

        .sns_start_roi_o (sns_start_roi),
        .sns_enable_roi_i(sns_enable_roi),
        .sns_clk_roi_o   (sns_clk_roi),
        .sns_hold_o      (sns_hold),
        .sns_reset_1_o   (sns_reset_ccd),
        .sns_sel_sr_o    (sns_sel_sr),
        .sns_modsel_o    (sns_modsel),
        .sns_modled_o    (sns_modled),

        .sns_cfg_ce_a_o(sns_ce_a),
        .sns_cfg_ce_d_o(sns_ce_d),
        .sns_cfg_sclk_o(sns_sclk),
        .sns_cfg_sdi_i (sns_sdi ),
        .sns_cfg_sdo_o (sns_sdo ),
        

        .adc_cfg_sdata_o    (adc_sdata_i),
        .adc_cfg_sdata_i    (adc_sdata_o),
        .adc_cfg_sdata_oen_o(adc_sdata_oen),
        .adc_cfg_sclk_o     (adc_sclk),
        .adc_cfg_sload_o    (adc_sload),

        .adc_data (adc_data),
        .adc_sclk2(adc_sclk2),
        .adc_sclk1(adc_sclk1),
        .adc_cclk (adc_cclk),
    

        .ppi_data(PPID),
        .ppi_fs1 (PPIFS1),
        .ppi_fs2 (PPIFS2),
        .ppi_fs3 (PPIFS3),
        .ppi_clk (ppi_clk),
        
        .adc_ctrl(),
        .start(),
        .cfg_register()
    );
    

    
    always begin
        @(posedge sns_start_roi);
        #10000;
        sns_enable_roi = 1;

        #(2692800/2-400*1000);
        sns_enable_roi = 0;
        #1;
    end


endmodule
module tb();


    `include "register_file_address_space.v"
    
    reg clk_sys = 1;
    reg clk_adc = 1;
    reg rst = 1;

    always #5 clk_sys = ~clk_sys;

    always #8 clk_adc = ~clk_adc;
    
    initial #200 rst = 0;
    
    wire spi_SCK;
    wire spi_MOSI;
    wire spi_MISO;
    wire spi_CSN;
    
    wire di_req;
    reg  [15:0] di = 16'hXXXX;
    reg  wren = 0;
    wire wr_ack;
    wire do_valid;
    wire [15:0] do;
    
    initial begin
        @(negedge rst);
        #1;
        repeat (10) @(posedge clk_sys);
        


        @(posedge clk_sys);
        di = 16'hXXXX;
        wren = 0;


        



        





        







        
        repeat (500) @(posedge clk_sys);
        di = {RF_WRITE_BIT, ADDRESS_MODLED_PHASE, 8'h01};
        wren = 1;
        @(posedge clk_sys);
        wren = 0;
        























        
        repeat (500) @(posedge clk_sys);
        di = {RF_WRITE_BIT, ADDRESS_START_CYCLE, 8'h01};
        wren = 1;
        @(posedge clk_sys);
        wren = 0;
        







        
    end

    spi_master #(   
        .N(16),
        .CPOL(1),
        .CPHA(1),
        .PREFETCH(2),
        .SPI_2X_CLK_DIV(5)
    )
    spi_master (  
        .sclk_i(clk_sys),
        .pclk_i(clk_sys),
        .rst_i(rst),
        

        .spi_ssel_o(spi_CSN),
        .spi_sck_o(spi_SCK),
        .spi_mosi_o(spi_MOSI),
        .spi_miso_i(spi_MISO),
        

        .di_req_o(di_req),
        .di_i(di),
        .wren_i(wren),
        .wr_ack_o(wr_ack),
        .do_valid_o(do_valid),
        .do_o(do),
        
        .sck_ena_o(),
        .sck_ena_ce_o(),
        .do_transfer_o(),
        .wren_o(),
        .rx_bit_reg_o(),
        .state_dbg_o(),
        .core_clk_o(),
        .core_n_clk_o(),
        .core_ce_o(),
        .core_n_ce_o(),
        .sh_reg_dbg_o()
    );                      

    wire [15:0] PPID;
    wire PPIFS1;
    wire PPIFS2;
    wire PPIFS3;

    wire ppi_clk;
    
    wire sns_start_roi;
    reg  sns_enable_roi = 1'b0;
    wire sns_clk_roi;
    wire sns_hold;
    wire sns_reset_ccd;
    wire sns_sel_sr;
    wire sns_modsel;
    wire sns_modled;
    
    wire sns_ce_a;
    wire sns_ce_d;
    wire sns_sclk;
    reg  sns_sdi = 1;
    wire sns_sdo;
    
    wire adc_sdata_i;
    reg  adc_sdata_o = 1;
    wire adc_sdata_oen;
    wire adc_sclk;
    wire adc_sload;
    
    reg  [7:0] adc_data;
    always @(posedge clk_adc) adc_data <= $random;
    wire adc_sclk2;
    wire adc_sclk1;
    wire adc_cclk;
    
    main main
    (
        .clk_sys(clk_sys),
        .clk_adc(clk_adc),
        .rst(rst),
        

        .cpu_spi_SCK (spi_SCK),
        .cpu_spi_MOSI(spi_MOSI),
        .cpu_spi_MISO(spi_MISO),
        .cpu_spi_CSN (spi_CSN),

        .sns_start_roi_o (sns_start_roi),
        .sns_enable_roi_i(sns_enable_roi),
        .sns_clk_roi_o   (sns_clk_roi),
        .sns_hold_o      (sns_hold),
        .sns_reset_1_o   (sns_reset_ccd),
        .sns_sel_sr_o    (sns_sel_sr),
        .sns_modsel_o    (sns_modsel),
        .sns_modled_o    (sns_modled),

        .sns_cfg_ce_a_o(sns_ce_a),
        .sns_cfg_ce_d_o(sns_ce_d),
        .sns_cfg_sclk_o(sns_sclk),
        .sns_cfg_sdi_i (sns_sdi ),
        .sns_cfg_sdo_o (sns_sdo ),
        

        .adc_cfg_sdata_o    (adc_sdata_i),
        .adc_cfg_sdata_i    (adc_sdata_o),
        .adc_cfg_sdata_oen_o(adc_sdata_oen),
        .adc_cfg_sclk_o     (adc_sclk),
        .adc_cfg_sload_o    (adc_sload),

        .adc_data (adc_data),
        .adc_sclk2(adc_sclk2),
        .adc_sclk1(adc_sclk1),
        .adc_cclk (adc_cclk),
    

        .ppi_data(PPID),
        .ppi_fs1 (PPIFS1),
        .ppi_fs2 (PPIFS2),
        .ppi_fs3 (PPIFS3),
        .ppi_clk (ppi_clk),
        
        .adc_ctrl(),
        .start(),
        .cfg_register()
    );
    

    
    always begin
        @(posedge sns_start_roi);
        #10000;
        sns_enable_roi = 1;

        #(2692800/2-400*1000);
        sns_enable_roi = 0;
        #1;
    end


endmodule