data/full_repos/permissive/14432793/OLD/I2C/test/test1.v
 line:13: before: "reset"
1: b'%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #40\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:97: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #10 \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:103: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #10 \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:107: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #10 \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:111: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #10 \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:116: Unsupported: Ignoring delay on this delayed statement.\n    #2\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test1.v:118: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Error: Exiting due to 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench1();

reg reset, clk, enable, in, Start, Stop;
wire sda;

test1 u1 ( clk, reset, enable, in, Start, Stop, sda );

always
  begin
    #5 clk = ~clk;
  end

initial
  begin
    reset = 0;
    clk = 1;
    enable = 0;
    in = 0;
    Start = 0;
    Stop = 0;
    #20
    reset = 1;
    #40
    Start = 1;
    #20;
    Start = 0;
    #20
    enable = 1;
    #20
    enable = 0;
    #20
    enable = 1;
    Start = 1;
    #20
    Start = 0;
    in = 0;
    #20
    in = 1;
    #10
    in = 0;
    #10 
    in = 1;
    #10
    in = 0;
    #10 
    in = 1;
    #10
    in = 0;
    #10 
    in = 1;
    #10
    in = 0;
    #10 
    in = 1;
    Stop = 1;
    #2
    Stop = 0;
    #50





    
    
    $finish;
  end

endmodule
module testbench1();


reg reset, clk, enable, in, Start, Stop;
wire sda;

test1 u1 ( clk, reset, enable, in, Start, Stop, sda );

always
  begin
    #5 clk = ~clk;
  end

initial
  begin
    reset = 0;
    clk = 1;
    enable = 0;
    in = 0;
    Start = 0;
    Stop = 0;
    #20
    reset = 1;
    #40
    Start = 1;
    #20;
    Start = 0;
    #20
    enable = 1;
    #20
    enable = 0;
    #20
    enable = 1;
    Start = 1;
    #20
    Start = 0;
    in = 0;
    #20
    in = 1;
    #10
    in = 0;
    #10 
    in = 1;
    #10
    in = 0;
    #10 
    in = 1;
    #10
    in = 0;
    #10 
    in = 1;
    #10
    in = 0;
    #10 
    in = 1;
    Stop = 1;
    #2
    Stop = 0;
    #50





    
    
    $finish;
  end

endmodule