data/full_repos/permissive/212763527/others/testbenches/disp_num_tb.v
 line:33: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/others/testbenches/disp_num_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    always #(PERIOD/2) \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/others/testbenches/disp_num_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    initial #2000\n            ^\n%Error: data/full_repos/permissive/212763527/others/testbenches/disp_num_tb.v:21: Cannot find file containing module: \'display_num\'\n    display_num #(interval) utt(clk, posb, num, dp, disp);\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/others/testbenches,data/full_repos/permissive/212763527/display_num\n             data/full_repos/permissive/212763527/others/testbenches,data/full_repos/permissive/212763527/display_num.v\n             data/full_repos/permissive/212763527/others/testbenches,data/full_repos/permissive/212763527/display_num.sv\n             display_num\n             display_num.v\n             display_num.sv\n             obj_dir/display_num\n             obj_dir/display_num.v\n             obj_dir/display_num.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
    parameter PERIOD  = 10;
    
    reg clk;
    wire[11:0] disp;

    parameter interval = 10;
    integer counter = 0;
    reg[3:0] num=0;
    reg[3:0] posb=4'b0111;
    reg dp = 0;

    initial
        clk=0;

    always #(PERIOD/2) 
        clk=~clk;

    display_num #(interval) utt(clk, posb, num, dp, disp);

    always @(posedge clk) begin
        counter <= counter + 1;
        if(counter == interval) begin
            counter <= 0;
            num <= num + 1;
        end
    end


    initial #2000
        $finish;

endmodule
module test;

    parameter PERIOD  = 10;
    
    reg clk;
    wire[11:0] disp;

    parameter interval = 10;
    integer counter = 0;
    reg[3:0] num=0;
    reg[3:0] posb=4'b0111;
    reg dp = 0;

    initial
        clk=0;

    always #(PERIOD/2) 
        clk=~clk;

    display_num #(interval) utt(clk, posb, num, dp, disp);

    always @(posedge clk) begin
        counter <= counter + 1;
        if(counter == interval) begin
            counter <= 0;
            num <= num + 1;
        end
    end


    initial #2000
        $finish;

endmodule