data/full_repos/permissive/178052224/Tarea5/demux/no_delay/src/BancoPrueba.v
1: b'%Error: data/full_repos/permissive/178052224/Tarea5/demux/no_delay/src/BancoPrueba.v:2: Cannot find include file: ./src/probador.v\n`include "./src/probador.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/178052224/Tarea5/demux/no_delay/src,data/full_repos/permissive/178052224/./src/probador.v\n             data/full_repos/permissive/178052224/Tarea5/demux/no_delay/src,data/full_repos/permissive/178052224/./src/probador.v.v\n             data/full_repos/permissive/178052224/Tarea5/demux/no_delay/src,data/full_repos/permissive/178052224/./src/probador.v.sv\n             ./src/probador.v\n             ./src/probador.v.v\n             ./src/probador.v.sv\n             obj_dir/./src/probador.v\n             obj_dir/./src/probador.v.v\n             obj_dir/./src/probador.v.sv\n%Error: data/full_repos/permissive/178052224/Tarea5/demux/no_delay/src/BancoPrueba.v:3: Cannot find include file: ./src/yosys_demux.v\n`include "./src/yosys_demux.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea5/demux/no_delay/src/BancoPrueba.v:4: Cannot find include file: ./lib/cmos_cells.v\n`include "./lib/cmos_cells.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module TestBench;



    wire		clk;
    wire [3:0]		data_in;
    wire [3:0]		data_out0;
    wire [3:0]		data_out1;
    wire		reset_L;



    demux dmux (

		.data_out0		(data_out0[3:0]),
		.data_out1		(data_out1[3:0]),

		.clk			(clk),
		.reset_L		(reset_L),
		.data_in		(data_in[3:0]));

    probador probador (

		       .clk		(clk),
		       .reset_L		(reset_L),
		       .data_in		(data_in[3:0]),

		       .data_out0	(data_out0[3:0]),
		       .data_out1	(data_out1[3:0]));
endmodule
module TestBench;




    wire		clk;
    wire [3:0]		data_in;
    wire [3:0]		data_out0;
    wire [3:0]		data_out1;
    wire		reset_L;



    demux dmux (

		.data_out0		(data_out0[3:0]),
		.data_out1		(data_out1[3:0]),

		.clk			(clk),
		.reset_L		(reset_L),
		.data_in		(data_in[3:0]));

    probador probador (

		       .clk		(clk),
		       .reset_L		(reset_L),
		       .data_in		(data_in[3:0]),

		       .data_out0	(data_out0[3:0]),
		       .data_out1	(data_out1[3:0]));
endmodule