data/full_repos/permissive/149769583/mac_macro_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/149769583/mac_macro_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #20 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac_macro_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #20 a = 1; b = 10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac_macro_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #20 a = 2; b = 10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac_macro_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #20 a = 3; b = 10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac_macro_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #20 a = 4; b = 0;\n        ^\n%Error: data/full_repos/permissive/149769583/mac_macro_tb.v:9: Cannot find file containing module: \'mac_macro\'\n    mac_macro DUT (.CLK(clk), .CE(CE), .CARRYIN(ci), .p_out(p), .A(a), .B(b));\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/mac_macro\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/mac_macro.v\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/mac_macro.sv\n             mac_macro\n             mac_macro.v\n             mac_macro.sv\n             obj_dir/mac_macro\n             obj_dir/mac_macro.v\n             obj_dir/mac_macro.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mac_macro_tb();

    wire [31:0] p;
    reg [15:0] a,b;
    reg clk;
    reg CE = 1;
    reg ci = 0;

    mac_macro DUT (.CLK(clk), .CE(CE), .CARRYIN(ci), .p_out(p), .A(a), .B(b));

    always begin
        #20 clk = ~clk;
    end

    initial begin
        clk=1;
        #20 a = 1; b = 10;
        #20 a = 2; b = 10;
        #20 a = 3; b = 10;
        #20 a = 4; b = 0;


    end
endmodule
module mac_macro_tb();


    wire [31:0] p;
    reg [15:0] a,b;
    reg clk;
    reg CE = 1;
    reg ci = 0;

    mac_macro DUT (.CLK(clk), .CE(CE), .CARRYIN(ci), .p_out(p), .A(a), .B(b));

    always begin
        #20 clk = ~clk;
    end

    initial begin
        clk=1;
        #20 a = 1; b = 10;
        #20 a = 2; b = 10;
        #20 a = 3; b = 10;
        #20 a = 4; b = 0;


    end
endmodule