data/full_repos/permissive/104667535/verilog/mcu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/104667535/verilog/mcu.v:284: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104667535/verilog/mcu.v:288: Unsupported: Ignoring delay on this delayed statement.\n            #100;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/104667535/verilog/mcu.v:295: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Error: data/full_repos/permissive/104667535/verilog/mcu.v:301: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mcu_test;
    reg clock;
    reg reset;
    wire [7:0] porta;
    wire [7:0] portb;

    mcu dut(
        .clock(clock),
        .reset(reset),
        .porta(porta),
        .portb(portb)
    );

    initial begin
        clock <= 0;
        #100;

        while (1) begin
            clock <= !clock;
            #100;
        end
    end

    initial begin
        reset <= 1;

        #1000;

        reset <= 0;
    end

    initial begin
        $dumpvars;
    end
endmodule
module mcu_test;

    reg clock;
    reg reset;
    wire [7:0] porta;
    wire [7:0] portb;

    mcu dut(
        .clock(clock),
        .reset(reset),
        .porta(porta),
        .portb(portb)
    );

    initial begin
        clock <= 0;
        #100;

        while (1) begin
            clock <= !clock;
            #100;
        end
    end

    initial begin
        reset <= 1;

        #1000;

        reset <= 0;
    end

    initial begin
        $dumpvars;
    end
endmodule