data/full_repos/permissive/188039952/SmartFusion2/sampleToTransmit.v
data/verilator_xmls/9da0dd03-db24-453c-b74d-b8bd442d59a6.xml
module sampleToTransmit (
		input 					CSReq,
		input 					is_transmitting,
		input						rst,
		input						clk,
		input 					matched,
		input						noFound,
		input						locked,
		input			[15:0]	CSCnt,
		input			[11:0]	ROSel,
		input			[15:0]	RO0Cnt,
		input 		[15:0]	RO1Cnt,
		input			[15:0]  	ClkCnt,
		input			[7:0]		randBits,
		output reg 	[7:0] 	tx_byte,
		output reg				transmit
	);
	

	reg	[3:0] 	transmitState;


	reg 	[15:0] 	CSCntReg;
	reg	[7:0]		CSCntRegLSB;
	wire 				CSCntCE;


	reg 	[15:0]	RO0Helper, RO1Helper, ClkHelper;
	reg 	[11:0]	ROSelHelper;
	reg				matchedHelper, noFoundHelper, lockedHelper;
	

	always @(posedge clk) begin
		if (rst) begin
			tx_byte 			<= 8'd0;
			transmitState 	<= 4'd0;
			transmit 		<= 1'b0;
			CSCntRegLSB		<= 8'd0;
			RO0Helper		<= 16'd0;
			RO1Helper		<= 16'd0;
			ClkHelper		<= 16'd0;
			ROSelHelper		<= 12'd0;
			matchedHelper	<= 1'b0;
			noFoundHelper	<= 1'b0;
			lockedHelper	<= 1'b0;
		end
		else begin
			if ((is_transmitting == 1'b0) && (transmit == 1'b0)) begin
				transmit <= 1'b1;
				case (transmitState)
					4'd0: begin
						tx_byte 			<= 8'h55;
						transmitState 	<= 4'd1;
					end
					4'd1: begin
						tx_byte 			<= CSCntReg[15:8];

						CSCntRegLSB		<= CSCntReg[7:0];
						RO0Helper		<= RO0Cnt;
						RO1Helper		<= RO1Cnt;
						ClkHelper		<= ClkCnt;
						ROSelHelper		<= ROSel;
						matchedHelper	<= matched;
						noFoundHelper	<= noFound;
						lockedHelper	<= locked;
						transmitState 	<= 4'd2;
					end
					4'd2: begin
						tx_byte 			<= CSCntRegLSB;
						transmitState 	<= 4'd3;
					end
					4'd3: begin
						tx_byte			<= RO0Helper[15:8];
						transmitState	<= 4'd4;
					end
					4'd4: begin
						tx_byte			<= RO0Helper[7:0];
						transmitState	<= 4'd5;
					end
					4'd5: begin
						tx_byte			<= RO1Helper[15:8];
						transmitState	<= 4'd6;
					end
					4'd6: begin
						tx_byte			<= RO1Helper[7:0];
						transmitState	<= 4'd7;
					end
					4'd7: begin
						tx_byte			<= ClkHelper[15:8];
						transmitState	<= 4'd8;
					end
					4'd8: begin
						tx_byte			<= ClkHelper[7:0];
						transmitState	<= 4'd9;
					end
					4'd9: begin
						tx_byte 			<= {2'b00, ROSelHelper[11:6]};
						transmitState	<= 4'd10;
					end
					4'd10: begin
						tx_byte			<= {2'b00, ROSelHelper[5:0]};
						transmitState	<= 4'd11;
					end
					4'd11: begin
						tx_byte			<= {matchedHelper, noFoundHelper, lockedHelper, 5'd0};
						transmitState	<= 4'd12;
					end
					4'd12: begin
						tx_byte			<= randBits;
						transmitState	<= 4'd13;
					end
					4'd13: begin
						tx_byte			<= 8'haa;
						transmitState	<= 4'd0;
					end
				endcase
			end
			if (transmit) begin
				transmit <= 1'b0;
			end
		end
	end
	

	always @(posedge clk) begin
		if (rst) begin
			CSCntReg <= 16'd0;
		end
		else begin
			if (CSReq) begin
				CSCntReg <= CSCnt;
			end
		end
	end
	
endmodule
module sampleToTransmit (
		input 					CSReq,
		input 					is_transmitting,
		input						rst,
		input						clk,
		input 					matched,
		input						noFound,
		input						locked,
		input			[15:0]	CSCnt,
		input			[11:0]	ROSel,
		input			[15:0]	RO0Cnt,
		input 		[15:0]	RO1Cnt,
		input			[15:0]  	ClkCnt,
		input			[7:0]		randBits,
		output reg 	[7:0] 	tx_byte,
		output reg				transmit
	);

	

	reg	[3:0] 	transmitState;


	reg 	[15:0] 	CSCntReg;
	reg	[7:0]		CSCntRegLSB;
	wire 				CSCntCE;


	reg 	[15:0]	RO0Helper, RO1Helper, ClkHelper;
	reg 	[11:0]	ROSelHelper;
	reg				matchedHelper, noFoundHelper, lockedHelper;
	

	always @(posedge clk) begin
		if (rst) begin
			tx_byte 			<= 8'd0;
			transmitState 	<= 4'd0;
			transmit 		<= 1'b0;
			CSCntRegLSB		<= 8'd0;
			RO0Helper		<= 16'd0;
			RO1Helper		<= 16'd0;
			ClkHelper		<= 16'd0;
			ROSelHelper		<= 12'd0;
			matchedHelper	<= 1'b0;
			noFoundHelper	<= 1'b0;
			lockedHelper	<= 1'b0;
		end
		else begin
			if ((is_transmitting == 1'b0) && (transmit == 1'b0)) begin
				transmit <= 1'b1;
				case (transmitState)
					4'd0: begin
						tx_byte 			<= 8'h55;
						transmitState 	<= 4'd1;
					end
					4'd1: begin
						tx_byte 			<= CSCntReg[15:8];

						CSCntRegLSB		<= CSCntReg[7:0];
						RO0Helper		<= RO0Cnt;
						RO1Helper		<= RO1Cnt;
						ClkHelper		<= ClkCnt;
						ROSelHelper		<= ROSel;
						matchedHelper	<= matched;
						noFoundHelper	<= noFound;
						lockedHelper	<= locked;
						transmitState 	<= 4'd2;
					end
					4'd2: begin
						tx_byte 			<= CSCntRegLSB;
						transmitState 	<= 4'd3;
					end
					4'd3: begin
						tx_byte			<= RO0Helper[15:8];
						transmitState	<= 4'd4;
					end
					4'd4: begin
						tx_byte			<= RO0Helper[7:0];
						transmitState	<= 4'd5;
					end
					4'd5: begin
						tx_byte			<= RO1Helper[15:8];
						transmitState	<= 4'd6;
					end
					4'd6: begin
						tx_byte			<= RO1Helper[7:0];
						transmitState	<= 4'd7;
					end
					4'd7: begin
						tx_byte			<= ClkHelper[15:8];
						transmitState	<= 4'd8;
					end
					4'd8: begin
						tx_byte			<= ClkHelper[7:0];
						transmitState	<= 4'd9;
					end
					4'd9: begin
						tx_byte 			<= {2'b00, ROSelHelper[11:6]};
						transmitState	<= 4'd10;
					end
					4'd10: begin
						tx_byte			<= {2'b00, ROSelHelper[5:0]};
						transmitState	<= 4'd11;
					end
					4'd11: begin
						tx_byte			<= {matchedHelper, noFoundHelper, lockedHelper, 5'd0};
						transmitState	<= 4'd12;
					end
					4'd12: begin
						tx_byte			<= randBits;
						transmitState	<= 4'd13;
					end
					4'd13: begin
						tx_byte			<= 8'haa;
						transmitState	<= 4'd0;
					end
				endcase
			end
			if (transmit) begin
				transmit <= 1'b0;
			end
		end
	end
	

	always @(posedge clk) begin
		if (rst) begin
			CSCntReg <= 16'd0;
		end
		else begin
			if (CSReq) begin
				CSCntReg <= CSCnt;
			end
		end
	end
	
endmodule