data/full_repos/permissive/203526788/IceStick/UART_String/top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/203526788/IceStick/UART_String/top.v:1: Cannot find include file: async.v\n`include "async.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203526788/IceStick/UART_String,data/full_repos/permissive/203526788/async.v\n             data/full_repos/permissive/203526788/IceStick/UART_String,data/full_repos/permissive/203526788/async.v.v\n             data/full_repos/permissive/203526788/IceStick/UART_String,data/full_repos/permissive/203526788/async.v.sv\n             async.v\n             async.v.v\n             async.v.sv\n             obj_dir/async.v\n             obj_dir/async.v.v\n             obj_dir/async.v.sv\n%Error: Exiting due to 1 error(s)\n'
module PULSE_GEN #(parameter FREQ = 1000) (
	input CLK,
	output wire outPin
	);


reg [32:0] count = 0;





reg enableOnce=0;
reg curr=0;

always @(posedge CLK)
begin
	if (count == 12_000_000 / FREQ -1)
	begin
		curr <= 1'b1;
		enableOnce <= 1'b1 & !curr;
		count <= 0;
	end
	else if (count == 0)
	begin
		curr <= 0;
		enableOnce <= 0; 
		count <= count + 1;
	end
	else
	begin
		count <= count + 1;
	end
end

assign outPin= enableOnce;
	
endmodule
module PULSE_GEN #(parameter FREQ = 1000) (
	input CLK,
	output wire outPin
	);



reg [32:0] count = 0;





reg enableOnce=0;
reg curr=0;

always @(posedge CLK)
begin
	if (count == 12_000_000 / FREQ -1)
	begin
		curr <= 1'b1;
		enableOnce <= 1'b1 & !curr;
		count <= 0;
	end
	else if (count == 0)
	begin
		curr <= 0;
		enableOnce <= 0; 
		count <= count + 1;
	end
	else
	begin
		count <= count + 1;
	end
end

assign outPin= enableOnce;
	
endmodule