data/full_repos/permissive/156417892/hdl/InstructionFetch/AddrGenerator/AddrGenerator_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/AddrGenerator/AddrGenerator_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/AddrGenerator/AddrGenerator_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/AddrGenerator/AddrGenerator_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Error: data/full_repos/permissive/156417892/hdl/InstructionFetch/AddrGenerator/AddrGenerator_test.v:42: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("./addrGenerator_test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/156417892/hdl/InstructionFetch/AddrGenerator/AddrGenerator_test.v:43: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;


   reg [31:0] adr_branch;
   reg PCSrc;
   reg [31:0] Add_in;


   wire [31:0] Ins_address;
   wire [31:0] Add_out;




    AddrGenerator uut(adr_branch,
                Add_in,
                Add_out,
                Ins_address,
                PCSrc);

   initial begin

      #10;
      Add_in = 2;
      adr_branch = 10;
      PCSrc = 0;
      
      #10;
      Add_in = 2;
      adr_branch = 10;
      PCSrc = 0;
      
      
      #100;


   end

   initial begin
      $dumpfile("./addrGenerator_test.vcd");
      $dumpvars;
   end

endmodule
module main_test;



   reg [31:0] adr_branch;
   reg PCSrc;
   reg [31:0] Add_in;


   wire [31:0] Ins_address;
   wire [31:0] Add_out;




    AddrGenerator uut(adr_branch,
                Add_in,
                Add_out,
                Ins_address,
                PCSrc);

   initial begin

      #10;
      Add_in = 2;
      adr_branch = 10;
      PCSrc = 0;
      
      #10;
      Add_in = 2;
      adr_branch = 10;
      PCSrc = 0;
      
      
      #100;


   end

   initial begin
      $dumpfile("./addrGenerator_test.vcd");
      $dumpvars;
   end

endmodule