data/full_repos/permissive/119758565/bit.v
1: b"%Error: data/full_repos/permissive/119758565/bit.v:30: syntax error, unexpected '(', expecting IDENTIFIER\n  mux(Out, in, load, c0);\n      ^~~\n%Error: Exiting due to 1 error(s)\n"
module Bit(
    input in,
    input load,
    input clk,
    output out
    );
	 
	 wire Out, c0;
	 
	 mux(Out, in, load, c0);
	 PosEdgeDFlipFlop(.data(c0), .clk(clk), .nq(), .q(out));
	 assign Out = out;


endmodule
module Bit(
    input in,
    input load,
    input clk,
    output out
    );

	 
	 wire Out, c0;
	 
	 mux(Out, in, load, c0);
	 PosEdgeDFlipFlop(.data(c0), .clk(clk), .nq(), .q(out));
	 assign Out = out;


endmodule