data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v
1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n             ^\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n              ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n                ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in replications.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n                        ^\n%Error: Exiting due to 4 warning(s)\n'
module clkdiv1(
    input inclk,
    output outclk
    );
    reg [35:0]q;
    always@(posedge inclk)
         q<=q+1;
    assign outclk=q[26];
endmodule
module clkdiv1(
    input inclk,
    output outclk
    );

    reg [35:0]q;
    always@(posedge inclk)
         q<=q+1;
    assign outclk=q[26];
endmodule