data/full_repos/permissive/118082957/main/proj1.v
 line:18: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:10: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20 rst=1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:17: Unsupported: Ignoring delay on this delayed statement.\n#435\n^\n%Warning-IMPLICIT: data/full_repos/permissive/118082957/main/proj1.v:648: Signal definition not found, creating implicitly: \'Zflag_reg\'\n   MAR_next, Zflag_reg, zflag_next);\n             ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/118082957/main/proj1.v:648: Signal definition not found, creating implicitly: \'zflag_next\'\n   MAR_next, Zflag_reg, zflag_next);\n                        ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/118082957/main/proj1.v:696: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'ACC_reg\' generates 16 bits.\n                                                                     : ... In instance tb_proj1.dut.datapath\n zflag = (!ACC_reg)? 1:0;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/118082957/main/proj1.v:19: Bit extraction of array[255:0] requires 8 bit index, not 16 bits.\n                                                                    : ... In instance tb_proj1\n$display("0x00d %d\\n",tb_proj1.dut.ram_ins.mem256x16[16\'h000d]);\n                                                    ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module registers(
 clk,
 rst,
 PC_reg,
 PC_next,
 IR_reg,
 IR_next,
 ACC_reg,
 ACC_next,
 MDR_reg,
 MDR_next,
 MAR_reg,
 MAR_next,
 Zflag_reg,
 zflag_next
 );

input wire clk;
input wire rst;
output reg [7:0]PC_reg;
input wire [7:0]PC_next;

output reg [15:0]IR_reg;
input wire [15:0]IR_next;
output reg [15:0]ACC_reg;
input wire [15:0]ACC_next;
output reg [15:0]MDR_reg;
input wire [15:0]MDR_next;
output reg [7:0]MAR_reg;
input wire [7:0]MAR_next;
output reg Zflag_reg;
input wire zflag_next;

always @(posedge clk or posedge rst) begin
if (rst) begin
	PC_reg <= 0;
	IR_reg <= 0;
	ACC_reg <= 0;
	MDR_reg <= 0;
	MAR_reg <= 0;
	Zflag_reg <= 0;
end else begin
	PC_reg <= PC_next;
	IR_reg <= IR_next;
	ACC_reg <= ACC_next;
	MDR_reg <= MDR_next;
	MAR_reg <= MAR_next;
	Zflag_reg <= zflag_next;
end

end





endmodule
module registers(
 clk,
 rst,
 PC_reg,
 PC_next,
 IR_reg,
 IR_next,
 ACC_reg,
 ACC_next,
 MDR_reg,
 MDR_next,
 MAR_reg,
 MAR_next,
 Zflag_reg,
 zflag_next
 );


input wire clk;
input wire rst;
output reg [7:0]PC_reg;
input wire [7:0]PC_next;

output reg [15:0]IR_reg;
input wire [15:0]IR_next;
output reg [15:0]ACC_reg;
input wire [15:0]ACC_next;
output reg [15:0]MDR_reg;
input wire [15:0]MDR_next;
output reg [7:0]MAR_reg;
input wire [7:0]MAR_next;
output reg Zflag_reg;
input wire zflag_next;

always @(posedge clk or posedge rst) begin
if (rst) begin
	PC_reg <= 0;
	IR_reg <= 0;
	ACC_reg <= 0;
	MDR_reg <= 0;
	MAR_reg <= 0;
	Zflag_reg <= 0;
end else begin
	PC_reg <= PC_next;
	IR_reg <= IR_next;
	ACC_reg <= ACC_next;
	MDR_reg <= MDR_next;
	MAR_reg <= MAR_next;
	Zflag_reg <= zflag_next;
end

end





endmodule