data/full_repos/permissive/106583614/Lab2/UARTBaudController_tb.v
 line:35 column:2: Illegal character '`'
1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTBaudController_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTBaudController_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTBaudController_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Error: data/full_repos/permissive/106583614/Lab2/UARTBaudController_tb.v:10: Cannot find file containing module: \'UARTBaudController\'\nUARTBaudController uart_controller_0 \n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController\n             data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController.v\n             data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTBaudController.sv\n             UARTBaudController\n             UARTBaudController.v\n             UARTBaudController.sv\n             obj_dir/UARTBaudController\n             obj_dir/UARTBaudController.v\n             obj_dir/UARTBaudController.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_UARTBaudController;
reg clk;
reg rst_n;

reg [2:0] baud_in;

wire mod_en;	
UARTBaudController uart_controller_0 
(
	.clk (clk),
	.reset (rst_n),
	.baud_select (baud_in),
	.sample_enable (mod_en)
);

localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;

initial 
begin
	clk = 1;
	rst_n = 1;
	#10;

	rst_n = 0;
	baud_in = 3'b101;
	#1000;


end

endmodule
module tb_UARTBaudController;

reg clk;
reg rst_n;

reg [2:0] baud_in;

wire mod_en;	
UARTBaudController uart_controller_0 
(
	.clk (clk),
	.reset (rst_n),
	.baud_select (baud_in),
	.sample_enable (mod_en)
);

localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;

initial 
begin
	clk = 1;
	rst_n = 1;
	#10;

	rst_n = 0;
	baud_in = 3'b101;
	#1000;


end

endmodule