data/full_repos/permissive/175132042/rtl/picorv32/scripts/presyn/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/175132042/rtl/picorv32/scripts/presyn/testbench.v:3: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/presyn/testbench.v:45: Unsupported: $fflush of all handles does not map to C++.\n     $fflush;\n     ^~~~~~~\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/presyn/testbench.v:64: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("testbench.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/presyn/testbench.v:65: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench);\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module picorv32_regs (
	input [4:0] A1ADDR, A2ADDR, B1ADDR,
	output reg [31:0] A1DATA, A2DATA,
	input [31:0] B1DATA,
	input B1EN, CLK1
);
	reg [31:0] memory [0:31];
	always @(posedge CLK1) begin
		A1DATA <= memory[A1ADDR];
		A2DATA <= memory[A2ADDR];
		if (B1EN) memory[B1ADDR] <= B1DATA;
	end
endmodule
module picorv32_regs (
	input [4:0] A1ADDR, A2ADDR, B1ADDR,
	output reg [31:0] A1DATA, A2DATA,
	input [31:0] B1DATA,
	input B1EN, CLK1
);

	reg [31:0] memory [0:31];
	always @(posedge CLK1) begin
		A1DATA <= memory[A1ADDR];
		A2DATA <= memory[A2ADDR];
		if (B1EN) memory[B1ADDR] <= B1DATA;
	end
endmodule