data/full_repos/permissive/107757225/reg_16.sv
data/verilator_xmls/c8767f1e-f767-4ef8-b8a3-5b4fcb34074f.xml
module reg_16 (
	input  logic clk,
	input  logic reset,
	input  logic load,
	input  logic [15:0] din,
	output logic [15:0] dout
);
always_ff @(posedge clk)
begin
	if(reset) begin
		dout <= 16'b0;
	end 
	else if(load) begin
		dout <= din;
	end
end

endmodule
module reg_16 (
	input  logic clk,
	input  logic reset,
	input  logic load,
	input  logic [15:0] din,
	output logic [15:0] dout
);

always_ff @(posedge clk)
begin
	if(reset) begin
		dout <= 16'b0;
	end 
	else if(load) begin
		dout <= din;
	end
end

endmodule