data/full_repos/permissive/20203462/mipsmulti.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:158: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'aluop\' generates 2 bits.\n                                                                   : ... In instance mips.c.ad\n    case(aluop)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:133: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'controls\' generates 17 bits.\n                                                                   : ... In instance mips.c.md\n    aluop} = controls;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:137: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h5010\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      FETCH:          controls <= 19\'b1010_00000_0100_00;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:138: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h30\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      DECODE:         controls <= 19\'b0000_00000_1100_00;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:139: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h420\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      MEMADR:         controls <= 19\'b0000_10000_1000_00;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:140: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h100\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      MEMRD:          controls <= 19\'b0000_00100_0000_00;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:141: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h880\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      MEMWB:          controls <= 19\'b0001_00010_0000_00;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:142: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h2100\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      MEMWR:          controls <= 19\'b0100_00100_0000_00;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:143: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h402\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      EXECUTE:        controls <= 19\'b0000_10000_0000_10;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:144: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h840\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      ALUWRITEBACK:   controls <= 19\'b0001_00001_0000_00;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:145: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h605\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      BRANCH:         controls <= 19\'b0000_11000_0001_01;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:146: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h420\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      ADDIEXECUTE:    controls <= 19\'b0000_10000_1000_00;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:147: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h800\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      ADDIWRITEBACK:  controls <= 19\'b0001_00000_0000_00;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:148: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h4008\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      JUMP:           controls <= 19\'b1000_00000_0010_00;     \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/20203462/mipsmulti.v:149: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'bxxxxxxxxxxx\' generates 19 bits.\n                                                                   : ... In instance mips.c.md\n      default:        controls <= 19\'b0000_xxxxx_xxxx_xx;  \n                               ^~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:201: Cannot find file containing module: \'flopenr\'\n  flopenr #(32) pcreg(clk, reset, pcen, pcnext, pc);\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20203462,data/full_repos/permissive/20203462/flopenr\n             data/full_repos/permissive/20203462,data/full_repos/permissive/20203462/flopenr.v\n             data/full_repos/permissive/20203462,data/full_repos/permissive/20203462/flopenr.sv\n             flopenr\n             flopenr.v\n             flopenr.sv\n             obj_dir/flopenr\n             obj_dir/flopenr.v\n             obj_dir/flopenr.sv\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:202: Cannot find file containing module: \'mux2\'\n  mux2    #(32) adrmux(pc, aluout, iord, adr);\n  ^~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:203: Cannot find file containing module: \'flopenr\'\n  flopenr #(32) instrreg(clk, reset, irwrite, readdata, instr);\n  ^~~~~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:204: Cannot find file containing module: \'flopr\'\n  flopr   #(32) datareg(clk, reset, readdata, data); \n  ^~~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:206: Cannot find file containing module: \'mux2\'\n  mux2    #(5)  regdstmux(instr[20:16], instr[15:11], regdst, writereg);\n  ^~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:207: Cannot find file containing module: \'mux2\'\n  mux2    #(32) wdmux(aluout, data, memtoreg, wd3);\n  ^~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:208: Cannot find file containing module: \'regfile\'\n  regfile       rf(clk, regwrite, instr[25:21], instr[20:16], \n  ^~~~~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:210: Cannot find file containing module: \'signext\'\n  signext       se(instr[15:0], signimm);\n  ^~~~~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:211: Cannot find file containing module: \'sl2\'\n  sl2           immsh(signimm, signimmsh);\n  ^~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:212: Cannot find file containing module: \'flopr\'\n  flopr   #(32) areg(clk, reset, rd1, a);\n  ^~~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:213: Cannot find file containing module: \'flopr\'\n  flopr   #(32) breg(clk, reset, rd2, writedata);\n  ^~~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:214: Cannot find file containing module: \'mux2\'\n  mux2    #(32) srcamux(pc, a, alusrca, srca);\n  ^~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:215: Cannot find file containing module: \'mux4\'\n  mux4    #(32) srcbmux(writedata, 32\'b100, signimm, signimmsh,\n  ^~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:217: Cannot find file containing module: \'alu\'\n  alu           alu(srca, srcb, alucontrol,\n  ^~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:219: Cannot find file containing module: \'flopr\'\n  flopr   #(32) alureg(clk, reset, aluresult, aluout);\n  ^~~~~\n%Error: data/full_repos/permissive/20203462/mipsmulti.v:220: Cannot find file containing module: \'mux3\'\n  mux3    #(32) pcmux(aluresult, aluout, \n  ^~~~\n%Error: Exiting due to 16 error(s), 15 warning(s)\n'
module controller(input        clk, reset,
                  input  [5:0] op, funct,
                  input        zero,
                  output       pcen, memwrite, irwrite, regwrite,
                  output       alusrca, iord, memtoreg, regdst,
                  output [1:0] alusrcb,
						output [1:0] pcsrc,
                  output [2:0] alucontrol);

  wire [1:0] aluop;
  wire       branch, pcwrite;


  maindec md(clk, reset, op,
             pcwrite, memwrite, irwrite, regwrite,
             alusrca, branch, iord, memtoreg, regdst, 
             alusrcb, pcsrc, aluop);
  aludec  ad(funct, aluop, alucontrol);

  assign pcen = pcwrite | (branch & zero);

endmodule
module controller(input        clk, reset,
                  input  [5:0] op, funct,
                  input        zero,
                  output       pcen, memwrite, irwrite, regwrite,
                  output       alusrca, iord, memtoreg, regdst,
                  output [1:0] alusrcb,
						output [1:0] pcsrc,
                  output [2:0] alucontrol);


  wire [1:0] aluop;
  wire       branch, pcwrite;


  maindec md(clk, reset, op,
             pcwrite, memwrite, irwrite, regwrite,
             alusrca, branch, iord, memtoreg, regdst, 
             alusrcb, pcsrc, aluop);
  aludec  ad(funct, aluop, alucontrol);

  assign pcen = pcwrite | (branch & zero);

endmodule