data/full_repos/permissive/11584509/source/salsa.v
data/verilator_xmls/a8b85f06-4d1d-4e6b-8aa2-c71e9c804937.xml
module salsa (clk, feedback, B, Bx, Bo);





input clk;
input feedback;
input [511:0]B;
input [511:0]Bx;

output [511:0]Bo;

wire [511:0]xx;




wire [511:0]xr;
reg [511:0]xrd;

salsa_core salsa1 (clk, feedback ? xrd : xx, xr);

genvar i;
generate
	for (i = 0; i < 16; i = i + 1) begin : XX

		assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];





		assign Bo[`IDX(i)] = xx[`IDX(i)] + xr[`IDX(i)];
	end
endgenerate

always @ (posedge clk)
	xrd <= xr;

endmodule
module salsa (clk, feedback, B, Bx, Bo);






input clk;
input feedback;
input [511:0]B;
input [511:0]Bx;

output [511:0]Bo;

wire [511:0]xx;




wire [511:0]xr;
reg [511:0]xrd;

salsa_core salsa1 (clk, feedback ? xrd : xx, xr);

genvar i;
generate
	for (i = 0; i < 16; i = i + 1) begin : XX

		assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];





		assign Bo[`IDX(i)] = xx[`IDX(i)] + xr[`IDX(i)];
	end
endgenerate

always @ (posedge clk)
	xrd <= xr;

endmodule