data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #00 clk = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v:15: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 clk = ~clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #27 D_IN = 16\'d54;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #27 D_IN = 16\'d977;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #27 D_IN = 16\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #27 D_IN = 16\'d6516;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #27 D_IN = 16\'d515;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #27 D_IN = 16\'d333;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #27 D_IN = 16\'d1804;\n  ^\n%Error: data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v:33: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("memoryDataRegister.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/126791278/testbenches/tb_memoryDataRegister.v:34: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_memoryDataRegister();
	
	wire [15:0] D_OUT;

	reg [15:0] D_IN;
	reg clk;

	memoryDataRegister uut(D_OUT, D_IN, clk);

	initial
	begin
		#00 clk = 1'b0;
		forever #10 clk = ~clk;
	end

	initial
	begin
		#27 D_IN = 16'd54;
		#27 D_IN = 16'd977;
		#27 D_IN = 16'd0;
		#27 D_IN = 16'd6516;
		#27 D_IN = 16'd515;
		#27 D_IN = 16'd333;
		#27 D_IN = 16'd1804;
		
		$stop;
	end

	initial
	begin
		$dumpfile("memoryDataRegister.vcd");
		$dumpvars;
	end

endmodule
module tb_memoryDataRegister();

	
	wire [15:0] D_OUT;

	reg [15:0] D_IN;
	reg clk;

	memoryDataRegister uut(D_OUT, D_IN, clk);

	initial
	begin
		#00 clk = 1'b0;
		forever #10 clk = ~clk;
	end

	initial
	begin
		#27 D_IN = 16'd54;
		#27 D_IN = 16'd977;
		#27 D_IN = 16'd0;
		#27 D_IN = 16'd6516;
		#27 D_IN = 16'd515;
		#27 D_IN = 16'd333;
		#27 D_IN = 16'd1804;
		
		$stop;
	end

	initial
	begin
		$dumpfile("memoryDataRegister.vcd");
		$dumpvars;
	end

endmodule