data/full_repos/permissive/166556094/usb/usb_uart_ecp5.v
None: at end of input
1: b'%Error: data/full_repos/permissive/166556094/usb/usb_uart_ecp5.v:32: Cannot find include file: ../../pipe/rtl/pipe_defs.v\n`include "../../pipe/rtl/pipe_defs.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166556094/usb,data/full_repos/permissive/166556094/../../pipe/rtl/pipe_defs.v\n             data/full_repos/permissive/166556094/usb,data/full_repos/permissive/166556094/../../pipe/rtl/pipe_defs.v.v\n             data/full_repos/permissive/166556094/usb,data/full_repos/permissive/166556094/../../pipe/rtl/pipe_defs.v.sv\n             ../../pipe/rtl/pipe_defs.v\n             ../../pipe/rtl/pipe_defs.v.v\n             ../../pipe/rtl/pipe_defs.v.sv\n             obj_dir/../../pipe/rtl/pipe_defs.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.sv\n%Error: data/full_repos/permissive/166556094/usb/usb_uart_ecp5.v:34: Define or directive not defined: \'`PS_d8\'\nmodule usb_uart  #( parameter PipeSpec = `PS_d8 ) (\n                                         ^~~~~~\n%Error: data/full_repos/permissive/166556094/usb/usb_uart_ecp5.v:34: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule usb_uart  #( parameter PipeSpec = `PS_d8 ) (\n                                                ^\n%Error: data/full_repos/permissive/166556094/usb/usb_uart_ecp5.v:42: Define or directive not defined: \'`P_m\'\n        inout [`P_m(PipeSpec):0] pipe_in,\n               ^~~~\n%Error: data/full_repos/permissive/166556094/usb/usb_uart_ecp5.v:43: Define or directive not defined: \'`P_m\'\n        inout [`P_m(PipeSpec):0] pipe_out,\n               ^~~~\n%Error: data/full_repos/permissive/166556094/usb/usb_uart_ecp5.v:48: Define or directive not defined: \'`P_Data_m\'\n    wire [`P_Data_m(PipeSpec):0] in_data;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/166556094/usb/usb_uart_ecp5.v:52: Define or directive not defined: \'`P_Data_m\'\n    wire [`P_Data_m(PipeSpec):0] out_data;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/166556094/usb/usb_uart_ecp5.v:56: syntax error, unexpected IDENTIFIER\n    p_unpack_data #( .PipeSpec( PipeSpec ) ) in_unpack_data( .pipe(pipe_in), .data(in_data) );\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module usb_uart_np (
  input  clk_48mhz,
  input reset,


  inout  pin_usb_p,
  inout  pin_usb_n,


  input [7:0] uart_in_data,
  input       uart_in_valid,
  output      uart_in_ready,


  output [7:0] uart_out_data,
  output       uart_out_valid,
  input        uart_out_ready,

  output [11:0] debug
);

    wire usb_p_tx;
    wire usb_n_tx;
    wire usb_p_rx;
    wire usb_n_rx;
    wire usb_tx_en;



    usb_uart_core_np u_u_c_np (
        .clk_48mhz  (clk_48mhz),
        .reset      (reset),


        .usb_p_tx(usb_p_tx),
        .usb_n_tx(usb_n_tx),
        .usb_p_rx(usb_p_rx),
        .usb_n_rx(usb_n_rx),
        .usb_tx_en(usb_tx_en),


        .uart_in_data( uart_in_data ),
        .uart_in_valid( uart_in_valid ),
        .uart_in_ready( uart_in_ready ),


        .uart_out_data( uart_out_data ),
        .uart_out_valid( uart_out_valid ),
        .uart_out_ready( uart_out_ready ),

        .debug( debug )
    );

    wire usb_p_in;
    wire usb_n_in;

    assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_in;
    assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_in;


	BB io_p( .I( usb_p_tx ), .T( !usb_tx_en ), .O( usb_p_in ), .B( pin_usb_p ) );
	BB io_n( .I( usb_n_tx ), .T( !usb_tx_en ), .O( usb_n_in ), .B( pin_usb_n ) );

endmodule
module usb_uart_np (
  input  clk_48mhz,
  input reset,


  inout  pin_usb_p,
  inout  pin_usb_n,


  input [7:0] uart_in_data,
  input       uart_in_valid,
  output      uart_in_ready,


  output [7:0] uart_out_data,
  output       uart_out_valid,
  input        uart_out_ready,

  output [11:0] debug
);


    wire usb_p_tx;
    wire usb_n_tx;
    wire usb_p_rx;
    wire usb_n_rx;
    wire usb_tx_en;



    usb_uart_core_np u_u_c_np (
        .clk_48mhz  (clk_48mhz),
        .reset      (reset),


        .usb_p_tx(usb_p_tx),
        .usb_n_tx(usb_n_tx),
        .usb_p_rx(usb_p_rx),
        .usb_n_rx(usb_n_rx),
        .usb_tx_en(usb_tx_en),


        .uart_in_data( uart_in_data ),
        .uart_in_valid( uart_in_valid ),
        .uart_in_ready( uart_in_ready ),


        .uart_out_data( uart_out_data ),
        .uart_out_valid( uart_out_valid ),
        .uart_out_ready( uart_out_ready ),

        .debug( debug )
    );

    wire usb_p_in;
    wire usb_n_in;

    assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_in;
    assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_in;


	BB io_p( .I( usb_p_tx ), .T( !usb_tx_en ), .O( usb_p_in ), .B( pin_usb_p ) );
	BB io_n( .I( usb_n_tx ), .T( !usb_tx_en ), .O( usb_n_in ), .B( pin_usb_n ) );

endmodule