data/full_repos/permissive/19818566/hardware/testcases/fpu100_div/fpga_sim/xpsLibraryPath_asic/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog/goc_wrapper.v
 line:7: before: ")"
1: b"%Error: data/full_repos/permissive/19818566/hardware/testcases/fpu100_div/fpga_sim/xpsLibraryPath_asic/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog/goc_wrapper.v:7: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: Exiting due to 1 error(s)\n"
module golden_circuit (
clk,
rst,
testVector,
resultVector,
);
input clk;
input rst;
input[69:0] testVector;
output[40:0] resultVector;
fpu toplevel_instance (
.opa_i(testVector [31:0]),
.opb_i(testVector [63:32]),
.fpu_op_i(testVector [66:64]),
.rmode_i(testVector [68:67]),
.output_o(resultVector [31:0]),
.clk_i(clk),
.start_i(testVector[69]),
.ready_o(resultVector[32]),
.ine_o(resultVector[33]),
.overflow_o(resultVector[34]),
.underflow_o(resultVector[35]),
.div_zero_o(resultVector[36]),
.inf_o(resultVector[37]),
.zero_o(resultVector[38]),
.qnan_o(resultVector[39]),
.snan_o(resultVector[40]));
endmodule
module golden_circuit (
clk,
rst,
testVector,
resultVector,
);

input clk;
input rst;
input[69:0] testVector;
output[40:0] resultVector;
fpu toplevel_instance (
.opa_i(testVector [31:0]),
.opb_i(testVector [63:32]),
.fpu_op_i(testVector [66:64]),
.rmode_i(testVector [68:67]),
.output_o(resultVector [31:0]),
.clk_i(clk),
.start_i(testVector[69]),
.ready_o(resultVector[32]),
.ine_o(resultVector[33]),
.overflow_o(resultVector[34]),
.underflow_o(resultVector[35]),
.div_zero_o(resultVector[36]),
.inf_o(resultVector[37]),
.zero_o(resultVector[38]),
.qnan_o(resultVector[39]),
.snan_o(resultVector[40]));
endmodule