data/full_repos/permissive/167489907/Data Path/With RAM/ram_datapath.v
 line:55: before: "."
1: b'%Error: Cannot find file containing module: Path/With\n        ... Looked in:\n             data/full_repos/permissive/167489907/Data/Path/With\n             data/full_repos/permissive/167489907/Data/Path/With.v\n             data/full_repos/permissive/167489907/Data/Path/With.sv\n             Path/With\n             Path/With.v\n             Path/With.sv\n             obj_dir/Path/With\n             obj_dir/Path/With.v\n             obj_dir/Path/With.sv\n%Error: Cannot find file containing module: RAM,data/full_repos/permissive/167489907\n%Error: Cannot find file containing module: data/full_repos/permissive/167489907/Data\n%Error: Cannot find file containing module: RAM/ram_datapath.v\n%Error: Exiting due to 4 error(s)\n'
module ram_datapath(
	input W,
	input clk,
	input rst,
	input EN_B,
	input EN_ALU,
	input EN_ADDR,
	input K_SEL,
	input PC_SEL,
	input C0,
	input WE,
	input OE,
	input [4:0] SA, SB, DA, FS,
	input [63:0] K,
	output [31:0] PC_in,
	output [3:0] Status,
	output [15:0] r0, r1, r2, r3, r4, r5, r6, r7,
	inout [63:0] D,
	output [31:0] ADDR);

wire [63:0] A, B, F, B_out;
wire [31:0] rom_out;
reg mem_select;



regfile32x64 regfile(.rdDataA(A), .rdDataB(B), .rdAddrA(SA), .rdAddrB(SB), .wrData(D), .wrAddr(DA), .write(W), .reset(rst), .clk(clk), .r0(r0), .r1(r1), .r2(r2), .r3(r3), .r4(r4), .r5(r5), .r6(r6), .r7(r7));
ALU_LEGv8 alu(.A(A), .B(B_out), .FS(FS), .C0(C0), .F(F), .status(Status));
ram_sp_sr_sw ram0(.clk(~clk), .address(ADDR[11:0]), .data(D), .cs(~mem_select), .we(WE), .oe(OE));
rom_case rom(.out(rom_out), .address(ADDR[11:0]));


tribuf64 rom_buffer(.in({32'b0, rom_out}), .control(mem_select & OE), .out(D));


always @(negedge clk) begin
if (ADDR < 12'h800) begin
		mem_select <= 1'b0;
end else if (ADDR >= 12'h800) begin
		mem_select <= 1'b1;
end
end




defparam ram0.DATA_WIDTH = 64;
defparam ram0.ADDR_WIDTH = 12;



Mux2to1 const_sel(.F(B_out), .A(K), .B(B), .Sel(K_SEL));
Mux2to1_32bit counter_sel(.F(PC_in), .A(K[31:0]), .B(A[31:0]), .Sel(PC_SEL));
tribuf64 B_enable(.in(B), .out(D), .control(EN_B));
tribuf64 ALU_enable(.in(F), .out(D), .control(EN_ALU));
tribuf32 ADDR_enable(.in(F[31:0]), .out(ADDR), .control(EN_ADDR));

endmodule
module ram_datapath(
	input W,
	input clk,
	input rst,
	input EN_B,
	input EN_ALU,
	input EN_ADDR,
	input K_SEL,
	input PC_SEL,
	input C0,
	input WE,
	input OE,
	input [4:0] SA, SB, DA, FS,
	input [63:0] K,
	output [31:0] PC_in,
	output [3:0] Status,
	output [15:0] r0, r1, r2, r3, r4, r5, r6, r7,
	inout [63:0] D,
	output [31:0] ADDR);


wire [63:0] A, B, F, B_out;
wire [31:0] rom_out;
reg mem_select;



regfile32x64 regfile(.rdDataA(A), .rdDataB(B), .rdAddrA(SA), .rdAddrB(SB), .wrData(D), .wrAddr(DA), .write(W), .reset(rst), .clk(clk), .r0(r0), .r1(r1), .r2(r2), .r3(r3), .r4(r4), .r5(r5), .r6(r6), .r7(r7));
ALU_LEGv8 alu(.A(A), .B(B_out), .FS(FS), .C0(C0), .F(F), .status(Status));
ram_sp_sr_sw ram0(.clk(~clk), .address(ADDR[11:0]), .data(D), .cs(~mem_select), .we(WE), .oe(OE));
rom_case rom(.out(rom_out), .address(ADDR[11:0]));


tribuf64 rom_buffer(.in({32'b0, rom_out}), .control(mem_select & OE), .out(D));


always @(negedge clk) begin
if (ADDR < 12'h800) begin
		mem_select <= 1'b0;
end else if (ADDR >= 12'h800) begin
		mem_select <= 1'b1;
end
end




defparam ram0.DATA_WIDTH = 64;
defparam ram0.ADDR_WIDTH = 12;



Mux2to1 const_sel(.F(B_out), .A(K), .B(B), .Sel(K_SEL));
Mux2to1_32bit counter_sel(.F(PC_in), .A(K[31:0]), .B(A[31:0]), .Sel(PC_SEL));
tribuf64 B_enable(.in(B), .out(D), .control(EN_B));
tribuf64 ALU_enable(.in(F), .out(D), .control(EN_ALU));
tribuf32 ADDR_enable(.in(F[31:0]), .out(ADDR), .control(EN_ADDR));

endmodule