data/full_repos/permissive/113471686/baseline/src/mtree.v
data/verilator_xmls/114311fa-51f3-493b-ba7c-2d8fc389679a.xml
module TREE_NODE #(parameter              DATW = 64,
                   parameter              KEYW = 32)
                  (input  wire            CLK,
                   input  wire            RST,
                   input  wire            IN_FULL,
                   input  wire [DATW-1:0] DIN0,
                   input  wire            ENQ0,
                   input  wire [DATW-1:0] DIN1,
                   input  wire            ENQ1,
                   output wire            FUL0,
                   output wire            FUL1,
                   output wire [DATW-1:0] DOUT,
                   output wire            DOUT_VLD);

  wire            fifo0_enq, fifo1_enq;
  wire            fifo0_deq, fifo1_deq;
  wire [DATW-1:0] fifo0_din, fifo1_din;
  wire [DATW-1:0] fifo0_dot, fifo1_dot;
  wire            fifo0_emp, fifo1_emp;
  wire            fifo0_ful, fifo1_ful;
  wire [1:0]      fifo0_cnt, fifo1_cnt;

  wire [DATW-1:0] scell_dot;
  wire            scell_doten;

  assign fifo0_enq = ENQ0;
  assign fifo1_enq = ENQ1;
  assign fifo0_din = DIN0;
  assign fifo1_din = DIN1;

  TWO_ENTRY_FIFO #(DATW)
  fifo0(CLK, RST, fifo0_enq, fifo0_deq, fifo0_din,
        fifo0_dot, fifo0_emp, fifo0_ful, fifo0_cnt);
  TWO_ENTRY_FIFO #(DATW)
  fifo1(CLK, RST, fifo1_enq, fifo1_deq, fifo1_din,
        fifo1_dot, fifo1_emp, fifo1_ful, fifo1_cnt);
  
  SORTER_CELL #(DATW, KEYW)
  sorter_cell(fifo0_dot, fifo1_dot, ~fifo0_emp, ~fifo1_emp, IN_FULL, 
              fifo0_deq, fifo1_deq, scell_dot, scell_doten);


  assign FUL0     = fifo0_ful;
  assign FUL1     = fifo1_ful;
  assign DOUT     = scell_dot;
  assign DOUT_VLD = scell_doten;
    
endmodule
module TREE_NODE #(parameter              DATW = 64,
                   parameter              KEYW = 32)
                  (input  wire            CLK,
                   input  wire            RST,
                   input  wire            IN_FULL,
                   input  wire [DATW-1:0] DIN0,
                   input  wire            ENQ0,
                   input  wire [DATW-1:0] DIN1,
                   input  wire            ENQ1,
                   output wire            FUL0,
                   output wire            FUL1,
                   output wire [DATW-1:0] DOUT,
                   output wire            DOUT_VLD);


  wire            fifo0_enq, fifo1_enq;
  wire            fifo0_deq, fifo1_deq;
  wire [DATW-1:0] fifo0_din, fifo1_din;
  wire [DATW-1:0] fifo0_dot, fifo1_dot;
  wire            fifo0_emp, fifo1_emp;
  wire            fifo0_ful, fifo1_ful;
  wire [1:0]      fifo0_cnt, fifo1_cnt;

  wire [DATW-1:0] scell_dot;
  wire            scell_doten;

  assign fifo0_enq = ENQ0;
  assign fifo1_enq = ENQ1;
  assign fifo0_din = DIN0;
  assign fifo1_din = DIN1;

  TWO_ENTRY_FIFO #(DATW)
  fifo0(CLK, RST, fifo0_enq, fifo0_deq, fifo0_din,
        fifo0_dot, fifo0_emp, fifo0_ful, fifo0_cnt);
  TWO_ENTRY_FIFO #(DATW)
  fifo1(CLK, RST, fifo1_enq, fifo1_deq, fifo1_din,
        fifo1_dot, fifo1_emp, fifo1_ful, fifo1_cnt);
  
  SORTER_CELL #(DATW, KEYW)
  sorter_cell(fifo0_dot, fifo1_dot, ~fifo0_emp, ~fifo1_emp, IN_FULL, 
              fifo0_deq, fifo1_deq, scell_dot, scell_doten);


  assign FUL0     = fifo0_ful;
  assign FUL1     = fifo1_ful;
  assign DOUT     = scell_dot;
  assign DOUT_VLD = scell_doten;
    
endmodule