data/full_repos/permissive/136264160/slave_1.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/136264160/slave_1.v:167: Operator SHIFTL expects 48 bits on the LHS, but LHS\'s VARREF \'xr\' generates 16 bits.\n                                                                  : ... In instance slave_1.kiwi3\nassign    far    = (xr<<16) + dick_re1 - dick_re2 ;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136264160/slave_1.v:168: Operator SHIFTL expects 48 bits on the LHS, but LHS\'s VARREF \'xi\' generates 16 bits.\n                                                                  : ... In instance slave_1.kiwi3\nassign    fai    = (xi<<16) + dick_im1 + dick_im2 ;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/136264160/slave_1.v:169: Operator SHIFTL expects 48 bits on the LHS, but LHS\'s VARREF \'xr\' generates 16 bits.\n                                                                  : ... In instance slave_1.kiwi3\nassign    fbr    = (xr<<16) - dick_re1 + dick_re2 ;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/136264160/slave_1.v:170: Operator SHIFTL expects 48 bits on the LHS, but LHS\'s VARREF \'xi\' generates 16 bits.\n                                                                  : ... In instance slave_1.kiwi3\nassign    fbi    = (xi<<16) - dick_im1 - dick_im2 ;\n                      ^~\n%Error: Exiting due to 4 warning(s)\n'
module butterfly0 (ar,ai,br,bi,xr,xi,yr,yi,w0r,w0i);

input     signed    [15:0]   xr ,yr ,xi ,yi ;
input     signed    [31:0]   w0r , w0i ;
output    signed    [15:0]   ar ,ai ,br ,bi  ;

assign ar = xr + yr ;
assign ai = xi ;
assign br = xr - yr ;
assign bi = xi ;

endmodule
module butterfly0 (ar,ai,br,bi,xr,xi,yr,yi,w0r,w0i);


input     signed    [15:0]   xr ,yr ,xi ,yi ;
input     signed    [31:0]   w0r , w0i ;
output    signed    [15:0]   ar ,ai ,br ,bi  ;

assign ar = xr + yr ;
assign ai = xi ;
assign br = xr - yr ;
assign bi = xi ;

endmodule