data/full_repos/permissive/106408053/verilog/async_fifo.v
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1: b'%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:175: Cannot find include file: gray.v\n`include "gray.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.v\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.sv\n             gray.v\n             gray.v.v\n             gray.v.sv\n             obj_dir/gray.v\n             obj_dir/gray.v.v\n             obj_dir/gray.v.sv\n%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:306: Cannot find include file: gray.v\n`include "gray.v" \n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:253: Unsupported: Ignoring delay on this delayed statement.\n          #1; \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:266: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:353: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:387: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n'
module async_fifo_wrpath (
  clk, reset, 
  space_avail, data_valid, wrdata,
  ram_wrenb, ram_wraddr, ram_wrdata,
  stable_wrptr, stable_rdptr);

parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;
parameter ASYNC_FIFO_FULLTHRESHOLD = 4;

input clk, reset;


output space_avail;
input data_valid;
input [ASYNC_FIFO_MAXDATA:0] wrdata;


output ram_wrenb;
output [ASYNC_FIFO_MAXINDEX:0] ram_wraddr;
output [ASYNC_FIFO_MAXDATA:0] ram_wrdata;


output [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr;
input [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr;

localparam WIDTH = ASYNC_FIFO_MAXINDEX+2;
`include "gray.v"





reg [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr, next_stable_wrptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] wrptr, next_wrptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] rdptr, next_rdptr;
reg space_avail, next_space_avail;

wire [ASYNC_FIFO_MAXINDEX+1:0] wrptr_plus1 = wrptr+1'b1;
wire [ASYNC_FIFO_MAXINDEX+1:0] fifo_depth = wrptr-rdptr;

wire [ASYNC_FIFO_MAXINDEX+1:0] gray_rdptr;
full_synchronizer #(WIDTH) sync_gray_rdptr (clk, reset, stable_rdptr, gray_rdptr);





wire ram_wrenb = data_valid;
wire [ASYNC_FIFO_MAXINDEX:0] ram_wraddr = wrptr[ASYNC_FIFO_MAXINDEX:0];
wire [ASYNC_FIFO_MAXDATA:0] ram_wrdata = wrdata;





initial 
begin 
  stable_wrptr = 0;
  rdptr = 0;
end
always @ (posedge clk or posedge reset)
begin
  if (reset) 
    begin
      stable_wrptr = 0;
      rdptr = 0;
    end
  else
    begin
      stable_wrptr = next_stable_wrptr;
      rdptr = next_rdptr;
    end
end

always @(*)
begin
  #1;
  next_stable_wrptr = bin2gray(next_wrptr);
  next_rdptr = gray2bin(gray_rdptr);
end





initial 
begin 
  space_avail = 0;
  wrptr = 0;
end
always @ (posedge clk or posedge reset)
begin
  if (reset) 
    begin
      space_avail = 1'b1;
      wrptr = 0;
    end
  else
    begin
      space_avail = next_space_avail;
      wrptr = next_wrptr;

      if (data_valid)
	begin
          #1; 
	  if (fifo_depth >= (1<<(ASYNC_FIFO_MAXINDEX+1)))
            begin
              $display ("%t: FIFO OVERFLOW!",$realtime);
              $finish;
            end
	end

    end
end

always @(*)
begin
  #1;
  next_space_avail = fifo_depth<((1<<(ASYNC_FIFO_MAXINDEX+1))-ASYNC_FIFO_FULLTHRESHOLD);
  next_wrptr = (data_valid && space_avail) ? wrptr_plus1 : wrptr;
end
endmodule
module async_fifo_wrpath (
  clk, reset, 
  space_avail, data_valid, wrdata,
  ram_wrenb, ram_wraddr, ram_wrdata,
  stable_wrptr, stable_rdptr);


parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;
parameter ASYNC_FIFO_FULLTHRESHOLD = 4;

input clk, reset;


output space_avail;
input data_valid;
input [ASYNC_FIFO_MAXDATA:0] wrdata;


output ram_wrenb;
output [ASYNC_FIFO_MAXINDEX:0] ram_wraddr;
output [ASYNC_FIFO_MAXDATA:0] ram_wrdata;


output [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr;
input [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr;

localparam WIDTH = ASYNC_FIFO_MAXINDEX+2;
`include "gray.v"





reg [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr, next_stable_wrptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] wrptr, next_wrptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] rdptr, next_rdptr;
reg space_avail, next_space_avail;

wire [ASYNC_FIFO_MAXINDEX+1:0] wrptr_plus1 = wrptr+1'b1;
wire [ASYNC_FIFO_MAXINDEX+1:0] fifo_depth = wrptr-rdptr;

wire [ASYNC_FIFO_MAXINDEX+1:0] gray_rdptr;
full_synchronizer #(WIDTH) sync_gray_rdptr (clk, reset, stable_rdptr, gray_rdptr);





wire ram_wrenb = data_valid;
wire [ASYNC_FIFO_MAXINDEX:0] ram_wraddr = wrptr[ASYNC_FIFO_MAXINDEX:0];
wire [ASYNC_FIFO_MAXDATA:0] ram_wrdata = wrdata;





initial 
begin 
  stable_wrptr = 0;
  rdptr = 0;
end
always @ (posedge clk or posedge reset)
begin
  if (reset) 
    begin
      stable_wrptr = 0;
      rdptr = 0;
    end
  else
    begin
      stable_wrptr = next_stable_wrptr;
      rdptr = next_rdptr;
    end
end

always @(*)
begin
  #1;
  next_stable_wrptr = bin2gray(next_wrptr);
  next_rdptr = gray2bin(gray_rdptr);
end





initial 
begin 
  space_avail = 0;
  wrptr = 0;
end
always @ (posedge clk or posedge reset)
begin
  if (reset) 
    begin
      space_avail = 1'b1;
      wrptr = 0;
    end
  else
    begin
      space_avail = next_space_avail;
      wrptr = next_wrptr;

      if (data_valid)
	begin
          #1; 
	  if (fifo_depth >= (1<<(ASYNC_FIFO_MAXINDEX+1)))
            begin
              $display ("%t: FIFO OVERFLOW!",$realtime);
              $finish;
            end
	end

    end
end

always @(*)
begin
  #1;
  next_space_avail = fifo_depth<((1<<(ASYNC_FIFO_MAXINDEX+1))-ASYNC_FIFO_FULLTHRESHOLD);
  next_wrptr = (data_valid && space_avail) ? wrptr_plus1 : wrptr;
end
endmodule