data/full_repos/permissive/120944384/code/synt/HDR_algorithm.sv
1: b'%Error: data/full_repos/permissive/120944384/code/synt/HDR_algorithm.sv:35: Cannot find file containing module: \'delay_rg\'\ndelay_rg\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120944384/code/synt,data/full_repos/permissive/120944384/delay_rg\n             data/full_repos/permissive/120944384/code/synt,data/full_repos/permissive/120944384/delay_rg.v\n             data/full_repos/permissive/120944384/code/synt,data/full_repos/permissive/120944384/delay_rg.sv\n             delay_rg\n             delay_rg.v\n             delay_rg.sv\n             obj_dir/delay_rg\n             obj_dir/delay_rg.v\n             obj_dir/delay_rg.sv\n%Error: data/full_repos/permissive/120944384/code/synt/HDR_algorithm.sv:47: Cannot find file containing module: \'delay_rg\'\ndelay_rg\n^~~~~~~~\n%Error: data/full_repos/permissive/120944384/code/synt/HDR_algorithm.sv:59: Cannot find file containing module: \'calc_weight_coef\'\ncalc_weight_coef \n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120944384/code/synt/HDR_algorithm.sv:70: Cannot find file containing module: \'calc_weight_coef\'\ncalc_weight_coef \n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120944384/code/synt/HDR_algorithm.sv:81: Cannot find file containing module: \'delay_rg\'\ndelay_rg\n^~~~~~~~\n%Error: data/full_repos/permissive/120944384/code/synt/HDR_algorithm.sv:105: Cannot find file containing module: \'HDR_divider\'\nHDR_divider HDR_divider_inst\n^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/120944384/code/synt/HDR_algorithm.sv:117: Operator ADD expects 34 bits on the LHS, but LHS\'s SEL generates 10 bits.\n                                                                                   : ... In instance HDR_algorithm\n  data_o <= quotient[9:0] + 1\'h1;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/120944384/code/synt/HDR_algorithm.sv:119: Operator ASSIGNDLY expects 34 bits on the Assign RHS, but Assign RHS\'s SEL generates 10 bits.\n                                                                                   : ... In instance HDR_algorithm\n  data_o <= quotient[9:0];\n         ^~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module HDR_algorithm
#(
	parameter DATA_WIDTH = 32
)
(

	input wire						clk,

	input wire	[DATA_WIDTH-1: 0]	data_i0,
	input wire	[DATA_WIDTH-1: 0]	data_i1,
	
	output reg 	[DATA_WIDTH+1: 0]	data_o
);

	wire 	[DATA_WIDTH-1: 0] 		weight_coef_0;
	wire 	[DATA_WIDTH-1: 0] 		weight_coef_1;
	
	reg		[DATA_WIDTH: 0] 		weight_coef_sum;
	wire 	[DATA_WIDTH: 0] 		weight_coef_sum_delay;	
	
	wire 	[DATA_WIDTH-1: 0] 		bright_delay_0;			
	wire 	[DATA_WIDTH-1: 0] 		bright_delay_1;	

	reg 	[(DATA_WIDTH*2): 0]		mult_0;
	reg 	[(DATA_WIDTH*2): 0] 	mult_1;	
	reg	 	[(DATA_WIDTH*2)+1: 0]   E;	
	
	wire	[17: 0]  				quotient;
	wire	[ 8: 0]  				remain;	
	
delay_rg
#(
	.W				( DATA_WIDTH	),
	.D				( 2				)
)
delay_rg_0
(
	.clk			( clk			),
	.data_in		( data_i0		),
	.data_out       ( bright_delay_0)
);

delay_rg
#(
	.W				( DATA_WIDTH	),
	.D				( 2				)
)
delay_rg_1
(
	.clk			( clk			),
	.data_in		( data_i1		),
	.data_out       ( bright_delay_1)
);
	
calc_weight_coef 
#(
	.DATA_WIDTH 	( DATA_WIDTH	)
)
calc_weight_coef_0
(
	.clk			( clk			),
	.Z              ( data_i0		),
	.weight_coef    ( weight_coef_0	)
);

calc_weight_coef 
#(
	.DATA_WIDTH 	( DATA_WIDTH	)
)
calc_weight_coef_1
(
	.clk			( clk			),
	.Z              ( data_i1		),
	.weight_coef    ( weight_coef_1	)
);

delay_rg
#(
	.W				( DATA_WIDTH+1	),
	.D				( 2				)
)
delay_weight
(
	.clk			( clk					),
	.data_in		( weight_coef_sum		),
	.data_out       ( weight_coef_sum_delay	)
);

always @( posedge clk )
	weight_coef_sum <= weight_coef_0 + weight_coef_1;
	
always @( posedge clk )
	begin
		mult_0	<= weight_coef_sum*bright_delay_0;
		mult_1	<= weight_coef_sum*bright_delay_1;		
	end

always @( posedge clk )
	E = mult_0 + mult_1;

HDR_divider HDR_divider_inst
(
	.clock			( clk					),
	.denom          ( weight_coef_sum_delay	),
	.numer          ( E						),
	.quotient       ( quotient				),
	.remain         ( remain				)
);


always @( posedge clk )
	if ( remain > 0 )
		data_o	<= quotient[9:0] + 1'h1;
	else
		data_o	<= quotient[9:0];

endmodule
module HDR_algorithm
#(
	parameter DATA_WIDTH = 32
)
(

	input wire						clk,

	input wire	[DATA_WIDTH-1: 0]	data_i0,
	input wire	[DATA_WIDTH-1: 0]	data_i1,
	
	output reg 	[DATA_WIDTH+1: 0]	data_o
);


	wire 	[DATA_WIDTH-1: 0] 		weight_coef_0;
	wire 	[DATA_WIDTH-1: 0] 		weight_coef_1;
	
	reg		[DATA_WIDTH: 0] 		weight_coef_sum;
	wire 	[DATA_WIDTH: 0] 		weight_coef_sum_delay;	
	
	wire 	[DATA_WIDTH-1: 0] 		bright_delay_0;			
	wire 	[DATA_WIDTH-1: 0] 		bright_delay_1;	

	reg 	[(DATA_WIDTH*2): 0]		mult_0;
	reg 	[(DATA_WIDTH*2): 0] 	mult_1;	
	reg	 	[(DATA_WIDTH*2)+1: 0]   E;	
	
	wire	[17: 0]  				quotient;
	wire	[ 8: 0]  				remain;	
	
delay_rg
#(
	.W				( DATA_WIDTH	),
	.D				( 2				)
)
delay_rg_0
(
	.clk			( clk			),
	.data_in		( data_i0		),
	.data_out       ( bright_delay_0)
);

delay_rg
#(
	.W				( DATA_WIDTH	),
	.D				( 2				)
)
delay_rg_1
(
	.clk			( clk			),
	.data_in		( data_i1		),
	.data_out       ( bright_delay_1)
);
	
calc_weight_coef 
#(
	.DATA_WIDTH 	( DATA_WIDTH	)
)
calc_weight_coef_0
(
	.clk			( clk			),
	.Z              ( data_i0		),
	.weight_coef    ( weight_coef_0	)
);

calc_weight_coef 
#(
	.DATA_WIDTH 	( DATA_WIDTH	)
)
calc_weight_coef_1
(
	.clk			( clk			),
	.Z              ( data_i1		),
	.weight_coef    ( weight_coef_1	)
);

delay_rg
#(
	.W				( DATA_WIDTH+1	),
	.D				( 2				)
)
delay_weight
(
	.clk			( clk					),
	.data_in		( weight_coef_sum		),
	.data_out       ( weight_coef_sum_delay	)
);

always @( posedge clk )
	weight_coef_sum <= weight_coef_0 + weight_coef_1;
	
always @( posedge clk )
	begin
		mult_0	<= weight_coef_sum*bright_delay_0;
		mult_1	<= weight_coef_sum*bright_delay_1;		
	end

always @( posedge clk )
	E = mult_0 + mult_1;

HDR_divider HDR_divider_inst
(
	.clock			( clk					),
	.denom          ( weight_coef_sum_delay	),
	.numer          ( E						),
	.quotient       ( quotient				),
	.remain         ( remain				)
);


always @( posedge clk )
	if ( remain > 0 )
		data_o	<= quotient[9:0] + 1'h1;
	else
		data_o	<= quotient[9:0];

endmodule