data/full_repos/permissive/17894630/Forwarding/Core.v
1: b"%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:94: Duplicate declaration of signal: 'instr'\n                                                                : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire[31:0] instr;\n             ^~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:24: ... Location of original declaration\n  output instr,\n         ^~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:95: Duplicate declaration of signal: 'IFID_instr'\n  reg[31:0] IFID_instr;\n            ^~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:25: ... Location of original declaration\n  output IFID_instr,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:96: Duplicate declaration of signal: 'IDEX_instr'\n  reg[31:0] IDEX_instr;\n            ^~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:26: ... Location of original declaration\n  output IDEX_instr,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:97: Duplicate declaration of signal: 'EXMEM_instr'\n  reg[31:0] EXMEM_instr;\n            ^~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:27: ... Location of original declaration\n  output EXMEM_instr,\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:98: Duplicate declaration of signal: 'MEMWB_instr'\n  reg[31:0] MEMWB_instr;\n            ^~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:28: ... Location of original declaration\n  output MEMWB_instr,\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:99: Duplicate declaration of signal: 'daddr'\n    reg[5:0] daddr;\n             ^~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:30: ... Location of original declaration\n    output daddr,\n           ^~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:100: Duplicate declaration of signal: 'dout'\n    wire[31:0] dout;\n               ^~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:31: ... Location of original declaration\n    output dout,\n           ^~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:101: Duplicate declaration of signal: 'MEMWB_dout'\n  reg[31:0] MEMWB_dout;\n            ^~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:32: ... Location of original declaration\n  output MEMWB_dout,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:102: Duplicate declaration of signal: 'wr'\n    reg[3:0] wr;\n             ^~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:33: ... Location of original declaration\n    output wr, \n           ^~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:103: Duplicate declaration of signal: 'EXMEM_wr'\n  reg[3:0] EXMEM_wr;\n           ^~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:34: ... Location of original declaration\n  output EXMEM_wr,\n         ^~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:104: Duplicate declaration of signal: 'pc'\n  reg[31:0] pc; \n            ^~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:35: ... Location of original declaration\n  output pc,\n         ^~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:105: Duplicate declaration of signal: 'IFID_pc'\n  reg[31:0] IFID_pc; \n            ^~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:36: ... Location of original declaration\n  output IFID_pc, \n         ^~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:106: Duplicate declaration of signal: 'IDEX_pc'\n  reg[31:0] IDEX_pc; \n            ^~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:37: ... Location of original declaration\n  output IDEX_pc, \n         ^~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:107: Duplicate declaration of signal: 'EXMEM_pc'\n  reg[31:0] EXMEM_pc; \n            ^~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:38: ... Location of original declaration\n  output EXMEM_pc, \n         ^~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:108: Duplicate declaration of signal: 'reg_din'\n  wire[31:0] reg_din;\n             ^~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:39: ... Location of original declaration\n  output reg_din,\n         ^~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:109: Duplicate declaration of signal: 'reg_raddr1'\n  reg[4:0] reg_raddr1;\n           ^~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:40: ... Location of original declaration\n  output reg_raddr1,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:110: Duplicate declaration of signal: 'reg_dout1'\n  wire[31:0] reg_dout1;\n             ^~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:41: ... Location of original declaration\n  output reg_dout1,\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:111: Duplicate declaration of signal: 'IDEX_reg_dout1'\n  reg[31:0] IDEX_reg_dout1;\n            ^~~~~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:42: ... Location of original declaration\n  output IDEX_reg_dout1,\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:112: Duplicate declaration of signal: 'reg_raddr2'\n  reg[4:0] reg_raddr2;\n           ^~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:43: ... Location of original declaration\n  output reg_raddr2,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:113: Duplicate declaration of signal: 'reg_dout2'\n  wire[31:0] reg_dout2;\n             ^~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:44: ... Location of original declaration\n  output reg_dout2,\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:114: Duplicate declaration of signal: 'IDEX_reg_dout2'\n  reg[31:0] IDEX_reg_dout2;\n            ^~~~~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:45: ... Location of original declaration\n  output IDEX_reg_dout2,\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:115: Duplicate declaration of signal: 'EXMEM_reg_dout2'\n  reg[31:0] EXMEM_reg_dout2;\n            ^~~~~~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:46: ... Location of original declaration\n  output EXMEM_reg_dout2,\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:116: Duplicate declaration of signal: 'wr_reg'\n  reg wr_reg;\n      ^~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:47: ... Location of original declaration\n  output wr_reg,\n         ^~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:117: Duplicate declaration of signal: 'EXMEM_wr_reg'\n  reg EXMEM_wr_reg;\n      ^~~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:48: ... Location of original declaration\n  output EXMEM_wr_reg,\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:118: Duplicate declaration of signal: 'MEMWB_wr_reg'\n  reg MEMWB_wr_reg;\n      ^~~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:49: ... Location of original declaration\n  output MEMWB_wr_reg,\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:119: Duplicate declaration of signal: 'reg_wr_addr'\n  reg[4:0] reg_wr_addr;\n           ^~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:50: ... Location of original declaration\n  output reg_wr_addr,\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:120: Duplicate declaration of signal: 'ALUOut'\n  reg[31:0] ALUOut;\n            ^~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:51: ... Location of original declaration\n  output ALUOut,\n         ^~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:121: Duplicate declaration of signal: 'EXMEM_ALUOut'\n  reg[31:0] EXMEM_ALUOut;\n            ^~~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:52: ... Location of original declaration\n  output EXMEM_ALUOut,\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:122: Duplicate declaration of signal: 'MEMWB_ALUOut'\n  reg[31:0] MEMWB_ALUOut;\n            ^~~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:53: ... Location of original declaration\n  output MEMWB_ALUOut,\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:123: Duplicate declaration of signal: 'ALUOp'\n  reg[3:0] ALUOp;\n           ^~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:54: ... Location of original declaration\n  output ALUOp,\n         ^~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:124: Duplicate declaration of signal: 'ALUSrc'\n  reg ALUSrc;\n      ^~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:55: ... Location of original declaration\n  output ALUSrc,\n         ^~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:125: Duplicate declaration of signal: 'ALUIn2'\n  reg[31:0] ALUIn2;\n            ^~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:56: ... Location of original declaration\n  output ALUIn2,\n         ^~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:126: Duplicate declaration of signal: 'MemToReg'\n  reg MemToReg;\n      ^~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:57: ... Location of original declaration\n  output MemToReg,\n         ^~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:127: Duplicate declaration of signal: 'EXMEM_MemToReg'\n  reg EXMEM_MemToReg;\n      ^~~~~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:58: ... Location of original declaration\n  output EXMEM_MemToReg,\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:128: Duplicate declaration of signal: 'MEMWB_MemToReg'\n  reg MEMWB_MemToReg;\n      ^~~~~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:59: ... Location of original declaration\n  output MEMWB_MemToReg,\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:129: Duplicate declaration of signal: 'RegDst'\n  reg RegDst;\n      ^~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:60: ... Location of original declaration\n  output RegDst,\n         ^~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:130: Duplicate declaration of signal: 'EXMEM_RegDst'\n  reg EXMEM_RegDst;\n      ^~~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:61: ... Location of original declaration\n  output EXMEM_RegDst,\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:131: Duplicate declaration of signal: 'MEMWB_RegDst'\n  reg MEMWB_RegDst;\n      ^~~~~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:62: ... Location of original declaration\n  output MEMWB_RegDst,\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:132: Duplicate declaration of signal: 'PCSrc'\n  reg PCSrc;\n      ^~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:63: ... Location of original declaration\n  output PCSrc,\n         ^~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:133: Duplicate declaration of signal: 'Zero'\n  reg Zero;\n      ^~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:67: ... Location of original declaration\n  output Zero,\n         ^~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:134: Duplicate declaration of signal: 'Branch'\n  reg Branch;\n      ^~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:68: ... Location of original declaration\n  output Branch,\n         ^~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:135: Duplicate declaration of signal: 'Jump'\n  reg Jump;\n      ^~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:69: ... Location of original declaration\n  output Jump,\n         ^~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:136: Duplicate declaration of signal: 'F10'\n  wire[31:0] F10;\n             ^~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:78: ... Location of original declaration\n  output F10,\n         ^~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:137: Duplicate declaration of signal: 'F4F8'\n  wire[31:0] F4F8;\n             ^~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:73: ... Location of original declaration\n  output F4F8,\n         ^~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:138: Duplicate declaration of signal: 'F2F6'\n  wire[31:0] F2F6;\n             ^~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:74: ... Location of original declaration\n  output F2F6,\n         ^~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:139: Duplicate declaration of signal: 'F1F5'\n  wire[31:0] F1F5;\n             ^~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:75: ... Location of original declaration\n  output F1F5,\n         ^~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:140: Duplicate declaration of signal: 'F3F7'\n  wire[31:0] F3F7;\n             ^~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:76: ... Location of original declaration\n  output F3F7,\n         ^~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:141: Duplicate declaration of signal: 'F9'\n  wire[31:0] F9;\n             ^~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:77: ... Location of original declaration\n  output F9,\n         ^~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:142: Duplicate declaration of signal: 'M3_Select'\n  reg[1:0] M3_Select;\n           ^~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:70: ... Location of original declaration\n  output M3_Select,\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/17894630/Forwarding/Core.v:143: Duplicate declaration of signal: 'M2_Select'\n  reg[1:0] M2_Select;\n           ^~~~~~~~~\n        data/full_repos/permissive/17894630/Forwarding/Core.v:71: ... Location of original declaration\n  output M2_Select,\n         ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module Core(
    input clk,
    input nrst,
	 output instr,
	 output IFID_instr,
	 output IDEX_instr,
	 output EXMEM_instr,
	 output MEMWB_instr,

    output daddr,
    output dout,
	 output MEMWB_dout,
    output wr, 
	 output EXMEM_wr,
	 output pc,
	 output IFID_pc, 
	 output IDEX_pc, 
	 output EXMEM_pc, 
	 output reg_din,
	 output reg_raddr1,
	 output reg_dout1,
	 output IDEX_reg_dout1,
	 output reg_raddr2,
	 output reg_dout2,
	 output IDEX_reg_dout2,
	 output EXMEM_reg_dout2,
	 output wr_reg,
	 output EXMEM_wr_reg,
	 output MEMWB_wr_reg,
	 output reg_wr_addr,
	 output ALUOut,
	 output EXMEM_ALUOut,
	 output MEMWB_ALUOut,
	 output ALUOp,
	 output ALUSrc,
	 output ALUIn2,
	 output MemToReg,
	 output EXMEM_MemToReg,
	 output MEMWB_MemToReg,
	 output RegDst,
	 output EXMEM_RegDst,
	 output MEMWB_RegDst,
	 output PCSrc,
	 output wire[31:0] ram1,
	 output wire[31:0] ram2,
	 output wire[31:0] ram3,
	 output Zero,
	 output Branch,
	 output Jump,
	 output M3_Select,
	 output M2_Select,
	 output M7_Select,
	 output F4F8,
	 output F2F6,
	 output F1F5,
	 output F3F7,
	 output F9,
	 output F10,
	 output IFID_RegisterRd,
	 output IFID_RegisterRt,
	 output IFID_RegisterRs,
	 output IDEX_RegisterRd,
	 output IDEX_RegisterRt,
	 output IDEX_RegisterRs,
	 output EXMEM_RegisterRd,
	 output EXMEM_RegisterRt,
	 output EXMEM_RegisterRs,
	 output MEMWB_RegisterRd,
	 output MEMWB_RegisterRt,
	 output MEMWB_RegisterRs
	 );

	
	 wire[31:0] instr;
	 reg[31:0] IFID_instr;
	 reg[31:0] IDEX_instr;
	 reg[31:0] EXMEM_instr;
	 reg[31:0] MEMWB_instr;
    reg[5:0] daddr;
    wire[31:0] dout;
	 reg[31:0] MEMWB_dout;
    reg[3:0] wr;
	 reg[3:0] EXMEM_wr;
	 reg[31:0] pc; 
	 reg[31:0] IFID_pc; 
	 reg[31:0] IDEX_pc; 
	 reg[31:0] EXMEM_pc; 
	 wire[31:0] reg_din;
	 reg[4:0] reg_raddr1;
	 wire[31:0] reg_dout1;
	 reg[31:0] IDEX_reg_dout1;
	 reg[4:0] reg_raddr2;
	 wire[31:0] reg_dout2;
	 reg[31:0] IDEX_reg_dout2;
	 reg[31:0] EXMEM_reg_dout2;
	 reg wr_reg;
	 reg EXMEM_wr_reg;
	 reg MEMWB_wr_reg;
	 reg[4:0] reg_wr_addr;
	 reg[31:0] ALUOut;
	 reg[31:0] EXMEM_ALUOut;
	 reg[31:0] MEMWB_ALUOut;
	 reg[3:0] ALUOp;
	 reg ALUSrc;
	 reg[31:0] ALUIn2;
	 reg MemToReg;
	 reg EXMEM_MemToReg;
	 reg MEMWB_MemToReg;
	 reg RegDst;
	 reg EXMEM_RegDst;
	 reg MEMWB_RegDst;
	 reg PCSrc;
	 reg Zero;
	 reg Branch;
	 reg Jump;
	 wire[31:0] F10;
	 wire[31:0] F4F8;
	 wire[31:0] F2F6;
	 wire[31:0] F1F5;
	 wire[31:0] F3F7;
	 wire[31:0] F9;
	 reg[1:0] M3_Select;
	 reg[1:0] M2_Select;
	 reg M7_Select;
	 reg[4:0] IFID_RegisterRd;
	 reg[4:0] IFID_RegisterRt;
	 reg[4:0] IFID_RegisterRs;
	 reg[4:0] IDEX_RegisterRd;
	 reg[4:0] IDEX_RegisterRt;
	 reg[4:0] IDEX_RegisterRs;
	 reg[4:0] EXMEM_RegisterRd;
	 reg[4:0] EXMEM_RegisterRt;
	 reg[4:0] EXMEM_RegisterRs;
	 reg[4:0] MEMWB_RegisterRd;
	 reg[4:0] MEMWB_RegisterRt;
	 reg[4:0] MEMWB_RegisterRs;
	 






	reg Carry;



	wire[7:0] din[0:3];


	reg[31:0] next_pc;
	reg[31:0] j_pc;
	reg[31:0] shifted_pc;
	reg[4:0] shamt;

	wire nclk;
	assign nclk = !(clk);
	regfile registers(
					clk,
					reg_raddr1,
					reg_dout1,
					reg_raddr2,
					reg_dout2,
					MEMWB_wr_reg,
					reg_wr_addr,
					reg_din,
					nrst,
					ram1,
					ram2,
					ram3
					);
	
	

	wire[31:0] dina;

	wire z;
	assign z = 0;
	IMem imem (
				  nclk,
				  z,
				  pc[7:2],
				  dina,
				  instr
					);
	DMem dmem_0 (
					  clk,
					  EXMEM_wr[0],
					  daddr[5:0],
					  EXMEM_reg_dout2[7:0],
					  dout[7:0]
					);
	DMem dmem_1 (
					  clk,
					  EXMEM_wr[1],
					  daddr[5:0],
					  EXMEM_reg_dout2[15:8],
					  dout[15:8]
					);
	DMem dmem_2 (
					  clk,
					  EXMEM_wr[2],
					  daddr[5:0],
					  EXMEM_reg_dout2[23:16],
					  dout[23:16]
					);
	DMem dmem_3 (
					  clk,
					  EXMEM_wr[3],
					  daddr[5:0],
					  EXMEM_reg_dout2[31:24],
					  dout[31:24]
					);	
	reg[31:0] JDest;
	reg JR;
	always @*
	begin


		JDest <= JR ? (IDEX_reg_dout1 << 2) : {4'b0000, IDEX_instr[25:0], 2'b00};
		j_pc <= Jump ? JDest : pc + 32'b100;
		shifted_pc <= (({{16{IDEX_instr[15]}}, IDEX_instr[15:0]}) << 2) + (IDEX_pc + 32'b100);
		PCSrc <= Branch & Zero;
		next_pc <= PCSrc ? shifted_pc : j_pc;

		reg_wr_addr <= MEMWB_RegDst ? MEMWB_instr[15:11] : MEMWB_instr[20:16];
		reg_raddr1 <= IFID_instr[25:21];
		reg_raddr2 <= IFID_instr[20:16];
		
		IFID_RegisterRd <= IFID_instr[31:26] == 6'b001000 ? IFID_instr[20:16] : IFID_instr[15:11];
		IFID_RegisterRt <= IFID_instr[20:16];
		IFID_RegisterRs <= IFID_instr[25:21];
		

		ALUIn2 <= ALUSrc ? {{16{IDEX_instr[15]}}, IDEX_instr[15:0]} : IDEX_reg_dout2;
	end

		assign reg_din = MEMWB_MemToReg ? MEMWB_dout : MEMWB_ALUOut;	

		assign F4F8 = EXMEM_ALUOut;
		assign F2F6 = EXMEM_ALUOut;
		assign F1F5 = EXMEM_ALUOut;
	   assign F3F7 = EXMEM_ALUOut;
		assign F9 = dout;
		assign F10 = dout;

	always @(posedge clk)
	begin
		if (~nrst)
		begin
			 pc = 32'b0;
			 Branch <= 0;
			 Jump <= 0;

		end
		else
		begin
			 pc = next_pc;
		end
	end
	

	always @(posedge clk)
	begin
		if (IFID_instr[31:26] == 6'b001000)
			ALUOp = 4'b0000;
		case (IFID_instr[31:26])
		6'b000000 :
		begin

			case (IFID_instr[10:0])
				11'b00000100000 :
				begin
					ALUOp = 4'b0000;
				end
				11'b00000100100 :
				begin
					ALUOp = 4'b0001;
				end
				11'b00000100010 :
				begin
					ALUOp = 4'b0100;
				end
				11'b00000100101:
				begin
					ALUOp = 4'b0010;
				end
				11'b00000100110:
				begin
					ALUOp = 4'b0111;
				end
				11'b00000011010, 11'b00000011011 :
				begin
					ALUOp = 4'b0101;
				end
				11'b00000011000, 11'b00000011001 :
				begin
					ALUOp = 4'b0110;
				end
				default :
				begin

				end
			endcase
		end
		6'b001101 :
			ALUOp = 4'b0010;
		6'b001110 :
			ALUOp = 4'b0111;
		6'b001100 :
			ALUOp = 4'b0000;
		6'b001000 , 6'b001001 :
			ALUOp = 4'b0000;
		6'b000100, 6'b000001, 6'b000111, 6'b000110, 6'b000001, 6'b000101 :
			ALUOp = 4'b0100;
		6'b100000 :
			ALUOp = 4'b0000;
		6'b001111 :
			ALUOp = 4'b0000;
		6'b100011 :
			ALUOp = 4'b0000;
		6'b101000 :
			ALUOp = 4'b0000;
		6'b101011 :
			ALUOp = 4'b0000;

		default :


			;
		endcase
	end

	always @(posedge clk)
	begin
		if (IFID_instr == 32'b0)
		begin
			wr_reg <= 0;
			wr <= 4'b0000;
			Branch <= 0;
			Jump <= 0;
			Branch <= 0;
		end
		else
		begin
			case (IFID_instr[31:26])
			6'b000000 :
			begin

				case (IFID_instr[10:0])
					11'b00000100000, 11'b00000100001, 11'b00000100010, 00000100011, 11'b00000100100, 11'b00000100101, 11'b00000100110 :

					begin
						RegDst <= 1;
						ALUSrc <= 0;



						wr_reg <= 1;
						MemToReg <= 0;
						Branch <= 0;
						Jump <= 0;
					end
					11'b00000000000 :
					case(IFID_instr[5:0])
						6'b000000 :
						begin
							RegDst <= 1;
							ALUSrc <= 0;
							wr_reg <= 1;
							MemToReg <= 0;
							Branch <= 0;
							Jump <= 0;
							shamt <= IDEX_instr[10:6];
						end
					endcase
					11'b00000001000 :
						if (IFID_instr[20:0] == 21'b1000)
						begin
							reg_raddr1 <= instr[25:21];
							wr_reg <= 0;
							wr <= 4'b0000;
							Branch <= 0;
							Jump <= 1;

						end
					default:
						;
				endcase
			end
			6'b001000, 6'b001001, 6'b001100, 6'b001101, 6'b001101 :
			begin
				RegDst <= 0;
				ALUSrc <= 1;

				wr_reg <= 1;
				MemToReg <= 0;
				Branch <= 0;
				Jump <= 0;
			end
			6'b000100 :
			begin
				Branch <= 1;
				Jump <= 0;
				MemToReg <= 0;
				wr_reg <= 0;
				wr <= 0;
				ALUSrc <= 0;
			end

			6'b100000 :
				begin
					RegDst <= 0;
					ALUSrc <= 1;
					wr[0] <= 0;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;


					wr_reg <= 1;
					MemToReg <= 1;
					PCSrc <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b100011 :
				begin
					RegDst <= 0;
					ALUSrc <= 1;
					wr[0] <= 0;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;


					wr_reg <= 1;
					MemToReg <= 1;
					PCSrc <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b101000 :
				begin
					ALUSrc <= 1;
					wr[0] <= 1;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;
					reg_raddr2 <= IFID_instr[20:16];
					wr_reg <= 0;
					MemToReg <= 0;
					PCSrc <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b101011 :
				begin
					ALUSrc <= 1;
					wr[0] <= 1;
					wr[1] <= 1;
					wr[2] <= 1;
					wr[3] <= 1;
					reg_raddr2 <= IFID_instr[20:16];
					wr_reg <= 0;
					MemToReg <= 0;
					PCSrc <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b000010 :
			begin
				wr_reg <= 0;
				wr <= 4'b0000;
				Branch <= 0;
				Jump <= 1;
				JR <= 0;
			end

			default :
				;
			endcase
		end
	end

	always @(posedge clk)
	begin
		if (nrst)
		begin
			MEMWB_instr <= EXMEM_instr;
			EXMEM_instr <= IDEX_instr;
			IDEX_instr <= IFID_instr;
			IFID_instr <= instr;
		
			EXMEM_pc <= IDEX_pc;
			IDEX_pc <= IFID_pc;
			IFID_pc <= pc;
			
			MEMWB_ALUOut <= EXMEM_ALUOut;
			EXMEM_ALUOut <= ALUOut;
			




			
			MEMWB_wr_reg <= EXMEM_wr_reg;
			EXMEM_wr_reg <= wr_reg;
			
			MEMWB_MemToReg <= EXMEM_MemToReg;
			EXMEM_MemToReg <= MemToReg;
			
			MEMWB_RegDst <= EXMEM_RegDst;
			EXMEM_RegDst <= RegDst;
			
			daddr[5:0] <= ALUOut[5:0];
			
			MEMWB_dout <= dout;
			
			EXMEM_wr <= wr;
			
			MEMWB_RegisterRd <= EXMEM_RegisterRd;
			EXMEM_RegisterRd <= IDEX_RegisterRd;
			IDEX_RegisterRd <= IFID_RegisterRd;
			
			MEMWB_RegisterRt <= EXMEM_RegisterRt;
			EXMEM_RegisterRt <= IDEX_RegisterRt;
			IDEX_RegisterRt <= IFID_RegisterRt;
			
			MEMWB_RegisterRs <= EXMEM_RegisterRs;
			EXMEM_RegisterRs <= IDEX_RegisterRs;
			IDEX_RegisterRs <= IFID_RegisterRs;
			
		end
	end
	

	always @(negedge clk)
	begin
		case (M3_Select)
		2'b00 :
			IDEX_reg_dout2 <= reg_dout2;


		2'b10 :
			IDEX_reg_dout2 <= F4F8;
		2'b11 :
			IDEX_reg_dout2 <= F2F6;
		default :
			IDEX_reg_dout2 <= reg_dout2;
		endcase
		case (M2_Select)
			2'b00 :
				IDEX_reg_dout1 <= F1F5;
			2'b01 :
				IDEX_reg_dout1 <= F3F7;
			2'b10 :
				IDEX_reg_dout1 <= F9;
			2'b11 :
				IDEX_reg_dout1 <= reg_dout1;
			default :
				IDEX_reg_dout1 <= reg_dout1;
		endcase

		EXMEM_reg_dout2 <= M7_Select ? F10 : IDEX_reg_dout2;
	end
	

	always @(*)
	begin
		M2_Select <= 2'b11;
		M3_Select <= 2'b00;
		M7_Select <= 0;
		if ((MEMWB_RegisterRt == EXMEM_RegisterRt) && (MEMWB_instr[31:26] == 6'b100011))
			M7_Select <= 1;
		if (EXMEM_wr_reg && (EXMEM_RegisterRd != 0))
		begin
			if (EXMEM_RegisterRd == IDEX_RegisterRs)

				M2_Select <= 2'b00;
			else
				M2_Select <= 2'b11;
			if (EXMEM_RegisterRd == IDEX_RegisterRt)

				M3_Select <= 2'b11;
			else
				M3_Select <= 2'b00;
		end
		if ((MEMWB_RegisterRt == IDEX_RegisterRs) && (MEMWB_instr[31:26] == 6'b100011))
				M2_Select <= 2'b10;
		if ((MEMWB_wr_reg && (MEMWB_RegisterRd != 0)) && !(EXMEM_wr_reg && (EXMEM_RegisterRd != 0) && ((EXMEM_RegisterRd == IDEX_RegisterRs))))
		begin
			if (MEMWB_RegisterRd == IDEX_RegisterRs)

				M2_Select <= 2'b01;
			else
				M2_Select <= 2'b11;
		end
		if ((MEMWB_wr_reg && (MEMWB_RegisterRd != 0)) && !(EXMEM_wr_reg && (EXMEM_RegisterRd != 0) && (EXMEM_RegisterRd == IDEX_RegisterRt)))
		begin
			if (MEMWB_RegisterRd == IDEX_RegisterRt)

				M3_Select <= 2'b10;
			else
				M3_Select <= 2'b00;
		end
	end
	


	always @(*)
	begin

		case (ALUOp)
		4'b0000 :
		begin
			ALUOut <= ALUIn2 + IDEX_reg_dout1;




		end
		4'b0001 :
		begin
			ALUOut <= IDEX_reg_dout1 & ALUIn2;
		end
		4'b0010 :
		begin
			ALUOut <= IDEX_reg_dout1 | ALUIn2;
		end
		4'b0011 :
		begin
			ALUOut <= ALUIn2 << shamt;
		end
		4'b0100 :
		begin
			ALUOut <= IDEX_reg_dout1 - ALUIn2;
			Zero <= (ALUOut == 32'b0) ? 1 : 0;
		end


		4'b0111 :
		begin
			ALUOut <= IDEX_reg_dout1 ^ ALUIn2;
		end
		default :
			;
		endcase
	end

endmodule
module Core(
    input clk,
    input nrst,
	 output instr,
	 output IFID_instr,
	 output IDEX_instr,
	 output EXMEM_instr,
	 output MEMWB_instr,

    output daddr,
    output dout,
	 output MEMWB_dout,
    output wr, 
	 output EXMEM_wr,
	 output pc,
	 output IFID_pc, 
	 output IDEX_pc, 
	 output EXMEM_pc, 
	 output reg_din,
	 output reg_raddr1,
	 output reg_dout1,
	 output IDEX_reg_dout1,
	 output reg_raddr2,
	 output reg_dout2,
	 output IDEX_reg_dout2,
	 output EXMEM_reg_dout2,
	 output wr_reg,
	 output EXMEM_wr_reg,
	 output MEMWB_wr_reg,
	 output reg_wr_addr,
	 output ALUOut,
	 output EXMEM_ALUOut,
	 output MEMWB_ALUOut,
	 output ALUOp,
	 output ALUSrc,
	 output ALUIn2,
	 output MemToReg,
	 output EXMEM_MemToReg,
	 output MEMWB_MemToReg,
	 output RegDst,
	 output EXMEM_RegDst,
	 output MEMWB_RegDst,
	 output PCSrc,
	 output wire[31:0] ram1,
	 output wire[31:0] ram2,
	 output wire[31:0] ram3,
	 output Zero,
	 output Branch,
	 output Jump,
	 output M3_Select,
	 output M2_Select,
	 output M7_Select,
	 output F4F8,
	 output F2F6,
	 output F1F5,
	 output F3F7,
	 output F9,
	 output F10,
	 output IFID_RegisterRd,
	 output IFID_RegisterRt,
	 output IFID_RegisterRs,
	 output IDEX_RegisterRd,
	 output IDEX_RegisterRt,
	 output IDEX_RegisterRs,
	 output EXMEM_RegisterRd,
	 output EXMEM_RegisterRt,
	 output EXMEM_RegisterRs,
	 output MEMWB_RegisterRd,
	 output MEMWB_RegisterRt,
	 output MEMWB_RegisterRs
	 );


	
	 wire[31:0] instr;
	 reg[31:0] IFID_instr;
	 reg[31:0] IDEX_instr;
	 reg[31:0] EXMEM_instr;
	 reg[31:0] MEMWB_instr;
    reg[5:0] daddr;
    wire[31:0] dout;
	 reg[31:0] MEMWB_dout;
    reg[3:0] wr;
	 reg[3:0] EXMEM_wr;
	 reg[31:0] pc; 
	 reg[31:0] IFID_pc; 
	 reg[31:0] IDEX_pc; 
	 reg[31:0] EXMEM_pc; 
	 wire[31:0] reg_din;
	 reg[4:0] reg_raddr1;
	 wire[31:0] reg_dout1;
	 reg[31:0] IDEX_reg_dout1;
	 reg[4:0] reg_raddr2;
	 wire[31:0] reg_dout2;
	 reg[31:0] IDEX_reg_dout2;
	 reg[31:0] EXMEM_reg_dout2;
	 reg wr_reg;
	 reg EXMEM_wr_reg;
	 reg MEMWB_wr_reg;
	 reg[4:0] reg_wr_addr;
	 reg[31:0] ALUOut;
	 reg[31:0] EXMEM_ALUOut;
	 reg[31:0] MEMWB_ALUOut;
	 reg[3:0] ALUOp;
	 reg ALUSrc;
	 reg[31:0] ALUIn2;
	 reg MemToReg;
	 reg EXMEM_MemToReg;
	 reg MEMWB_MemToReg;
	 reg RegDst;
	 reg EXMEM_RegDst;
	 reg MEMWB_RegDst;
	 reg PCSrc;
	 reg Zero;
	 reg Branch;
	 reg Jump;
	 wire[31:0] F10;
	 wire[31:0] F4F8;
	 wire[31:0] F2F6;
	 wire[31:0] F1F5;
	 wire[31:0] F3F7;
	 wire[31:0] F9;
	 reg[1:0] M3_Select;
	 reg[1:0] M2_Select;
	 reg M7_Select;
	 reg[4:0] IFID_RegisterRd;
	 reg[4:0] IFID_RegisterRt;
	 reg[4:0] IFID_RegisterRs;
	 reg[4:0] IDEX_RegisterRd;
	 reg[4:0] IDEX_RegisterRt;
	 reg[4:0] IDEX_RegisterRs;
	 reg[4:0] EXMEM_RegisterRd;
	 reg[4:0] EXMEM_RegisterRt;
	 reg[4:0] EXMEM_RegisterRs;
	 reg[4:0] MEMWB_RegisterRd;
	 reg[4:0] MEMWB_RegisterRt;
	 reg[4:0] MEMWB_RegisterRs;
	 






	reg Carry;



	wire[7:0] din[0:3];


	reg[31:0] next_pc;
	reg[31:0] j_pc;
	reg[31:0] shifted_pc;
	reg[4:0] shamt;

	wire nclk;
	assign nclk = !(clk);
	regfile registers(
					clk,
					reg_raddr1,
					reg_dout1,
					reg_raddr2,
					reg_dout2,
					MEMWB_wr_reg,
					reg_wr_addr,
					reg_din,
					nrst,
					ram1,
					ram2,
					ram3
					);
	
	

	wire[31:0] dina;

	wire z;
	assign z = 0;
	IMem imem (
				  nclk,
				  z,
				  pc[7:2],
				  dina,
				  instr
					);
	DMem dmem_0 (
					  clk,
					  EXMEM_wr[0],
					  daddr[5:0],
					  EXMEM_reg_dout2[7:0],
					  dout[7:0]
					);
	DMem dmem_1 (
					  clk,
					  EXMEM_wr[1],
					  daddr[5:0],
					  EXMEM_reg_dout2[15:8],
					  dout[15:8]
					);
	DMem dmem_2 (
					  clk,
					  EXMEM_wr[2],
					  daddr[5:0],
					  EXMEM_reg_dout2[23:16],
					  dout[23:16]
					);
	DMem dmem_3 (
					  clk,
					  EXMEM_wr[3],
					  daddr[5:0],
					  EXMEM_reg_dout2[31:24],
					  dout[31:24]
					);	
	reg[31:0] JDest;
	reg JR;
	always @*
	begin


		JDest <= JR ? (IDEX_reg_dout1 << 2) : {4'b0000, IDEX_instr[25:0], 2'b00};
		j_pc <= Jump ? JDest : pc + 32'b100;
		shifted_pc <= (({{16{IDEX_instr[15]}}, IDEX_instr[15:0]}) << 2) + (IDEX_pc + 32'b100);
		PCSrc <= Branch & Zero;
		next_pc <= PCSrc ? shifted_pc : j_pc;

		reg_wr_addr <= MEMWB_RegDst ? MEMWB_instr[15:11] : MEMWB_instr[20:16];
		reg_raddr1 <= IFID_instr[25:21];
		reg_raddr2 <= IFID_instr[20:16];
		
		IFID_RegisterRd <= IFID_instr[31:26] == 6'b001000 ? IFID_instr[20:16] : IFID_instr[15:11];
		IFID_RegisterRt <= IFID_instr[20:16];
		IFID_RegisterRs <= IFID_instr[25:21];
		

		ALUIn2 <= ALUSrc ? {{16{IDEX_instr[15]}}, IDEX_instr[15:0]} : IDEX_reg_dout2;
	end

		assign reg_din = MEMWB_MemToReg ? MEMWB_dout : MEMWB_ALUOut;	

		assign F4F8 = EXMEM_ALUOut;
		assign F2F6 = EXMEM_ALUOut;
		assign F1F5 = EXMEM_ALUOut;
	   assign F3F7 = EXMEM_ALUOut;
		assign F9 = dout;
		assign F10 = dout;

	always @(posedge clk)
	begin
		if (~nrst)
		begin
			 pc = 32'b0;
			 Branch <= 0;
			 Jump <= 0;

		end
		else
		begin
			 pc = next_pc;
		end
	end
	

	always @(posedge clk)
	begin
		if (IFID_instr[31:26] == 6'b001000)
			ALUOp = 4'b0000;
		case (IFID_instr[31:26])
		6'b000000 :
		begin

			case (IFID_instr[10:0])
				11'b00000100000 :
				begin
					ALUOp = 4'b0000;
				end
				11'b00000100100 :
				begin
					ALUOp = 4'b0001;
				end
				11'b00000100010 :
				begin
					ALUOp = 4'b0100;
				end
				11'b00000100101:
				begin
					ALUOp = 4'b0010;
				end
				11'b00000100110:
				begin
					ALUOp = 4'b0111;
				end
				11'b00000011010, 11'b00000011011 :
				begin
					ALUOp = 4'b0101;
				end
				11'b00000011000, 11'b00000011001 :
				begin
					ALUOp = 4'b0110;
				end
				default :
				begin

				end
			endcase
		end
		6'b001101 :
			ALUOp = 4'b0010;
		6'b001110 :
			ALUOp = 4'b0111;
		6'b001100 :
			ALUOp = 4'b0000;
		6'b001000 , 6'b001001 :
			ALUOp = 4'b0000;
		6'b000100, 6'b000001, 6'b000111, 6'b000110, 6'b000001, 6'b000101 :
			ALUOp = 4'b0100;
		6'b100000 :
			ALUOp = 4'b0000;
		6'b001111 :
			ALUOp = 4'b0000;
		6'b100011 :
			ALUOp = 4'b0000;
		6'b101000 :
			ALUOp = 4'b0000;
		6'b101011 :
			ALUOp = 4'b0000;

		default :


			;
		endcase
	end

	always @(posedge clk)
	begin
		if (IFID_instr == 32'b0)
		begin
			wr_reg <= 0;
			wr <= 4'b0000;
			Branch <= 0;
			Jump <= 0;
			Branch <= 0;
		end
		else
		begin
			case (IFID_instr[31:26])
			6'b000000 :
			begin

				case (IFID_instr[10:0])
					11'b00000100000, 11'b00000100001, 11'b00000100010, 00000100011, 11'b00000100100, 11'b00000100101, 11'b00000100110 :

					begin
						RegDst <= 1;
						ALUSrc <= 0;



						wr_reg <= 1;
						MemToReg <= 0;
						Branch <= 0;
						Jump <= 0;
					end
					11'b00000000000 :
					case(IFID_instr[5:0])
						6'b000000 :
						begin
							RegDst <= 1;
							ALUSrc <= 0;
							wr_reg <= 1;
							MemToReg <= 0;
							Branch <= 0;
							Jump <= 0;
							shamt <= IDEX_instr[10:6];
						end
					endcase
					11'b00000001000 :
						if (IFID_instr[20:0] == 21'b1000)
						begin
							reg_raddr1 <= instr[25:21];
							wr_reg <= 0;
							wr <= 4'b0000;
							Branch <= 0;
							Jump <= 1;

						end
					default:
						;
				endcase
			end
			6'b001000, 6'b001001, 6'b001100, 6'b001101, 6'b001101 :
			begin
				RegDst <= 0;
				ALUSrc <= 1;

				wr_reg <= 1;
				MemToReg <= 0;
				Branch <= 0;
				Jump <= 0;
			end
			6'b000100 :
			begin
				Branch <= 1;
				Jump <= 0;
				MemToReg <= 0;
				wr_reg <= 0;
				wr <= 0;
				ALUSrc <= 0;
			end

			6'b100000 :
				begin
					RegDst <= 0;
					ALUSrc <= 1;
					wr[0] <= 0;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;


					wr_reg <= 1;
					MemToReg <= 1;
					PCSrc <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b100011 :
				begin
					RegDst <= 0;
					ALUSrc <= 1;
					wr[0] <= 0;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;


					wr_reg <= 1;
					MemToReg <= 1;
					PCSrc <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b101000 :
				begin
					ALUSrc <= 1;
					wr[0] <= 1;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;
					reg_raddr2 <= IFID_instr[20:16];
					wr_reg <= 0;
					MemToReg <= 0;
					PCSrc <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b101011 :
				begin
					ALUSrc <= 1;
					wr[0] <= 1;
					wr[1] <= 1;
					wr[2] <= 1;
					wr[3] <= 1;
					reg_raddr2 <= IFID_instr[20:16];
					wr_reg <= 0;
					MemToReg <= 0;
					PCSrc <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b000010 :
			begin
				wr_reg <= 0;
				wr <= 4'b0000;
				Branch <= 0;
				Jump <= 1;
				JR <= 0;
			end

			default :
				;
			endcase
		end
	end

	always @(posedge clk)
	begin
		if (nrst)
		begin
			MEMWB_instr <= EXMEM_instr;
			EXMEM_instr <= IDEX_instr;
			IDEX_instr <= IFID_instr;
			IFID_instr <= instr;
		
			EXMEM_pc <= IDEX_pc;
			IDEX_pc <= IFID_pc;
			IFID_pc <= pc;
			
			MEMWB_ALUOut <= EXMEM_ALUOut;
			EXMEM_ALUOut <= ALUOut;
			




			
			MEMWB_wr_reg <= EXMEM_wr_reg;
			EXMEM_wr_reg <= wr_reg;
			
			MEMWB_MemToReg <= EXMEM_MemToReg;
			EXMEM_MemToReg <= MemToReg;
			
			MEMWB_RegDst <= EXMEM_RegDst;
			EXMEM_RegDst <= RegDst;
			
			daddr[5:0] <= ALUOut[5:0];
			
			MEMWB_dout <= dout;
			
			EXMEM_wr <= wr;
			
			MEMWB_RegisterRd <= EXMEM_RegisterRd;
			EXMEM_RegisterRd <= IDEX_RegisterRd;
			IDEX_RegisterRd <= IFID_RegisterRd;
			
			MEMWB_RegisterRt <= EXMEM_RegisterRt;
			EXMEM_RegisterRt <= IDEX_RegisterRt;
			IDEX_RegisterRt <= IFID_RegisterRt;
			
			MEMWB_RegisterRs <= EXMEM_RegisterRs;
			EXMEM_RegisterRs <= IDEX_RegisterRs;
			IDEX_RegisterRs <= IFID_RegisterRs;
			
		end
	end
	

	always @(negedge clk)
	begin
		case (M3_Select)
		2'b00 :
			IDEX_reg_dout2 <= reg_dout2;


		2'b10 :
			IDEX_reg_dout2 <= F4F8;
		2'b11 :
			IDEX_reg_dout2 <= F2F6;
		default :
			IDEX_reg_dout2 <= reg_dout2;
		endcase
		case (M2_Select)
			2'b00 :
				IDEX_reg_dout1 <= F1F5;
			2'b01 :
				IDEX_reg_dout1 <= F3F7;
			2'b10 :
				IDEX_reg_dout1 <= F9;
			2'b11 :
				IDEX_reg_dout1 <= reg_dout1;
			default :
				IDEX_reg_dout1 <= reg_dout1;
		endcase

		EXMEM_reg_dout2 <= M7_Select ? F10 : IDEX_reg_dout2;
	end
	

	always @(*)
	begin
		M2_Select <= 2'b11;
		M3_Select <= 2'b00;
		M7_Select <= 0;
		if ((MEMWB_RegisterRt == EXMEM_RegisterRt) && (MEMWB_instr[31:26] == 6'b100011))
			M7_Select <= 1;
		if (EXMEM_wr_reg && (EXMEM_RegisterRd != 0))
		begin
			if (EXMEM_RegisterRd == IDEX_RegisterRs)

				M2_Select <= 2'b00;
			else
				M2_Select <= 2'b11;
			if (EXMEM_RegisterRd == IDEX_RegisterRt)

				M3_Select <= 2'b11;
			else
				M3_Select <= 2'b00;
		end
		if ((MEMWB_RegisterRt == IDEX_RegisterRs) && (MEMWB_instr[31:26] == 6'b100011))
				M2_Select <= 2'b10;
		if ((MEMWB_wr_reg && (MEMWB_RegisterRd != 0)) && !(EXMEM_wr_reg && (EXMEM_RegisterRd != 0) && ((EXMEM_RegisterRd == IDEX_RegisterRs))))
		begin
			if (MEMWB_RegisterRd == IDEX_RegisterRs)

				M2_Select <= 2'b01;
			else
				M2_Select <= 2'b11;
		end
		if ((MEMWB_wr_reg && (MEMWB_RegisterRd != 0)) && !(EXMEM_wr_reg && (EXMEM_RegisterRd != 0) && (EXMEM_RegisterRd == IDEX_RegisterRt)))
		begin
			if (MEMWB_RegisterRd == IDEX_RegisterRt)

				M3_Select <= 2'b10;
			else
				M3_Select <= 2'b00;
		end
	end
	


	always @(*)
	begin

		case (ALUOp)
		4'b0000 :
		begin
			ALUOut <= ALUIn2 + IDEX_reg_dout1;




		end
		4'b0001 :
		begin
			ALUOut <= IDEX_reg_dout1 & ALUIn2;
		end
		4'b0010 :
		begin
			ALUOut <= IDEX_reg_dout1 | ALUIn2;
		end
		4'b0011 :
		begin
			ALUOut <= ALUIn2 << shamt;
		end
		4'b0100 :
		begin
			ALUOut <= IDEX_reg_dout1 - ALUIn2;
			Zero <= (ALUOut == 32'b0) ? 1 : 0;
		end


		4'b0111 :
		begin
			ALUOut <= IDEX_reg_dout1 ^ ALUIn2;
		end
		default :
			;
		endcase
	end

endmodule