data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/wishbone/settings_readback.v
data/verilator_xmls/7dddf436-e9f7-4b26-8701-e4ca5849011d.xml
module settings_readback
  #(parameter AWIDTH=16, parameter DWIDTH=32, parameter RB_ADDRW=2)
   (
    input wb_clk, 
    input wb_rst, 
    input [AWIDTH-1:0] wb_adr_i,
    input wb_stb_i,
    input wb_we_i,
    input [DWIDTH-1:0] rb_data,
    output reg [RB_ADDRW-1:0] rb_addr,
    output [DWIDTH-1:0] wb_dat_o,
    output reg rb_rd_stb
    );

   always @(posedge wb_clk)
     if (wb_stb_i && ~wb_we_i) begin
	rb_addr <= wb_adr_i[RB_ADDRW+1:2];
	rb_rd_stb <= 1'b1;	
     end else begin
	rb_rd_stb <= 1'b0;	
     end
   
   assign wb_dat_o = rb_data;

   

endmodule
module settings_readback
  #(parameter AWIDTH=16, parameter DWIDTH=32, parameter RB_ADDRW=2)
   (
    input wb_clk, 
    input wb_rst, 
    input [AWIDTH-1:0] wb_adr_i,
    input wb_stb_i,
    input wb_we_i,
    input [DWIDTH-1:0] rb_data,
    output reg [RB_ADDRW-1:0] rb_addr,
    output [DWIDTH-1:0] wb_dat_o,
    output reg rb_rd_stb
    );


   always @(posedge wb_clk)
     if (wb_stb_i && ~wb_we_i) begin
	rb_addr <= wb_adr_i[RB_ADDRW+1:2];
	rb_rd_stb <= 1'b1;	
     end else begin
	rb_rd_stb <= 1'b0;	
     end
   
   assign wb_dat_o = rb_data;

   

endmodule