data/full_repos/permissive/184431263/NOR/NOR2.v
data/verilator_xmls/a500f3ba-5cab-4977-b73f-19866b8a86b6.xml
module NOR2(Y, A0, A1, VDD, VSS );
  input A0, A1;
  output Y;
  inout VDD, VSS;

  assign Y = (A0 || A1) ? VSS : VDD ;
endmodule
module NOR2(Y, A0, A1, VDD, VSS );

  input A0, A1;
  output Y;
  inout VDD, VSS;

  assign Y = (A0 || A1) ? VSS : VDD ;
endmodule