data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top.v
1: b"%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top.v:16: Cannot find file containing module: 'timer'\ntimer #(RCWIDTH) timer0(.clk(clk), .rst(rst), .en(en));\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display2,data/full_repos/permissive/214278225/timer\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display2,data/full_repos/permissive/214278225/timer.v\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display2,data/full_repos/permissive/214278225/timer.sv\n             timer\n             timer.v\n             timer.sv\n             obj_dir/timer\n             obj_dir/timer.v\n             obj_dir/timer.sv\n%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top.v:17: Cannot find file containing module: 'stateMachine'\nstateMachine stateMachine0(.clk(clk), .rst(rst), .en(en), .state(state));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top.v:18: Cannot find file containing module: 'SevenSegFourDigwithEnable'\nSevenSegFourDigwithEnable #(SCWIDTH) SevenSegFourDigwithEnable0(.clk(clk), .rst(rst), .in({seg3, seg2, seg1, seg0}), .sevenSeg(sevenSeg), .anode(anode));\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top.v:19: Cannot find file containing module: 'rotateDigit'\nrotateDigit rotateDigit0(.in0({3'b000,dataIn[1:0]}), \n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module display2_top(clk, rst, dataIn, sevenSeg, anode);

input clk, rst;
input [7:0] dataIn;
output [3:0] anode;
output [7:0] sevenSeg;

parameter SCWIDTH = 15;
parameter RCWIDTH = 25;

wire [4:0] seg0, seg1, seg2, seg3;
wire en;
wire [2:0] state;

timer #(RCWIDTH) timer0(.clk(clk), .rst(rst), .en(en));
stateMachine stateMachine0(.clk(clk), .rst(rst), .en(en), .state(state));
SevenSegFourDigwithEnable #(SCWIDTH) SevenSegFourDigwithEnable0(.clk(clk), .rst(rst), .in({seg3, seg2, seg1, seg0}), .sevenSeg(sevenSeg), .anode(anode));
rotateDigit rotateDigit0(.in0({3'b000,dataIn[1:0]}), 
								 .in1({3'b000,dataIn[3:2]}), 
								 .in2({3'b000,dataIn[5:4]}), 
								 .in3({3'b000,dataIn[7:6]}), 
								 .in4(5'b10000), 
								 .in5(5'b10000), 
								 .in6(5'b10000), 
								 .state(state), 
								 .seg0(seg0), 
								 .seg1(seg1), 
								 .seg2(seg2), 
								 .seg3(seg3));
endmodule
module display2_top(clk, rst, dataIn, sevenSeg, anode);


input clk, rst;
input [7:0] dataIn;
output [3:0] anode;
output [7:0] sevenSeg;

parameter SCWIDTH = 15;
parameter RCWIDTH = 25;

wire [4:0] seg0, seg1, seg2, seg3;
wire en;
wire [2:0] state;

timer #(RCWIDTH) timer0(.clk(clk), .rst(rst), .en(en));
stateMachine stateMachine0(.clk(clk), .rst(rst), .en(en), .state(state));
SevenSegFourDigwithEnable #(SCWIDTH) SevenSegFourDigwithEnable0(.clk(clk), .rst(rst), .in({seg3, seg2, seg1, seg0}), .sevenSeg(sevenSeg), .anode(anode));
rotateDigit rotateDigit0(.in0({3'b000,dataIn[1:0]}), 
								 .in1({3'b000,dataIn[3:2]}), 
								 .in2({3'b000,dataIn[5:4]}), 
								 .in3({3'b000,dataIn[7:6]}), 
								 .in4(5'b10000), 
								 .in5(5'b10000), 
								 .in6(5'b10000), 
								 .state(state), 
								 .seg0(seg0), 
								 .seg1(seg1), 
								 .seg2(seg2), 
								 .seg3(seg3));
endmodule