data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v
 line:60: before: "signed"
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:52: Operator COND expects 35 bits on the Conditional True, but Conditional True\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                             : ... In instance jelly_fixed_atan2_multicycle\n    localparam  [34:0]   ANGLE_0   = SCALED_RADIAN ? 32\'h00000000 : 35\'h000000000;\n                                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:53: Operator COND expects 35 bits on the Conditional True, but Conditional True\'s CONST \'32\'h40000000\' generates 32 bits.\n                                                                                             : ... In instance jelly_fixed_atan2_multicycle\n    localparam  [34:0]   ANGLE_90  = SCALED_RADIAN ? 32\'h40000000 : 35\'h1921fb544;\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:54: Operator COND expects 35 bits on the Conditional True, but Conditional True\'s CONST \'32\'h80000000\' generates 32 bits.\n                                                                                             : ... In instance jelly_fixed_atan2_multicycle\n    localparam  [34:0]   ANGLE_180 = SCALED_RADIAN ? 32\'h80000000 : 35\'h3243f6a88;\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:55: Operator COND expects 35 bits on the Conditional True, but Conditional True\'s CONST \'32\'hc0000000\' generates 32 bits.\n                                                                                             : ... In instance jelly_fixed_atan2_multicycle\n    localparam  [34:0]   ANGLE_270 = SCALED_RADIAN ? 32\'hc0000000 : 35\'h4b65f1fcc;\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:56: Operator COND expects 35 bits on the Conditional True, but Conditional True\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                             : ... In instance jelly_fixed_atan2_multicycle\n    localparam  [34:0]   ANGLE_360 = SCALED_RADIAN ? 32\'h00000000 : 35\'h6487ed511;\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:62: Operator SHIFTR expects 35 bits on the LHS, but LHS\'s CONST \'32\'h80000000\' generates 32 bits.\n                                                                                             : ... In instance jelly_fixed_atan2_multicycle\n        q32_to_angle = (q32 + (32\'h80000000 >> Q_WIDTH)) >> (32 - Q_WIDTH);\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:62: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 35 bits.\n                                                                                             : ... In instance jelly_fixed_atan2_multicycle\n        q32_to_angle = (q32 + (32\'h80000000 >> Q_WIDTH)) >> (32 - Q_WIDTH);\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:69: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 64 bits.\n                                                                                             : ... In instance jelly_fixed_atan2_multicycle\n        q32rad_to_scaled = ((rad * 64\'h00000000_28be60dc) + 64\'h00000000_80000000) >> 32;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:80: Operator FUNCREF \'q32_to_angle\' expects 35 bits on the Function Argument, but Function Argument\'s FUNCREF \'q32rad_to_scaled\' generates 32 bits.\n                                                                                             : ... In instance jelly_fixed_atan2_multicycle\n            make_tbl = q32_to_angle(q32rad_to_scaled(q32rad));\n                       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:83: Operator FUNCREF \'q32_to_angle\' expects 35 bits on the Function Argument, but Function Argument\'s VARREF \'q32rad\' generates 32 bits.\n                                                                                             : ... In instance jelly_fixed_atan2_multicycle\n            make_tbl = q32_to_angle(q32rad);\n                       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:85: Operator GTE expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'idx\' generates 5 bits.\n                                                                                             : ... In instance jelly_fixed_atan2_multicycle\n        if ( idx >= Q_WIDTH ) begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:162: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'s_y\' generates 32 bits.\n                                                                                              : ... In instance jelly_fixed_atan2_multicycle\n                    reg_x     <= +(s_y <<< Q_WIDTH);\n                                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:163: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'s_x\' generates 32 bits.\n                                                                                              : ... In instance jelly_fixed_atan2_multicycle\n                    reg_y     <= -(s_x <<< Q_WIDTH);\n                                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:168: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'s_y\' generates 32 bits.\n                                                                                              : ... In instance jelly_fixed_atan2_multicycle\n                    reg_x     <= -(s_y <<< Q_WIDTH);\n                                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:169: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'s_x\' generates 32 bits.\n                                                                                              : ... In instance jelly_fixed_atan2_multicycle\n                    reg_y     <= +(s_x <<< Q_WIDTH);\n                                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_fixed_atan2_multicycle.v:189: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'reg_step\' generates 5 bits.\n                                                                                              : ... In instance jelly_fixed_atan2_multicycle\n                if ( reg_step == (Q_WIDTH-1) ) begin\n                              ^~\n%Error: Exiting due to 16 warning(s)\n'
function signed [31:0] q32rad_to_scaled(input [31:0] rad);
    begin
        q32rad_to_scaled = ((rad * 64'h00000000_28be60dc) + 64'h00000000_80000000) >> 32;
    end
    endfunction
function signed [31:0] q32rad_to_scaled(input [31:0] rad);

    begin
        q32rad_to_scaled = ((rad * 64'h00000000_28be60dc) + 64'h00000000_80000000) >> 32;
    end
    endfunction