data/full_repos/permissive/210844779/lab1/1.2.1/mux2x1.v
data/verilator_xmls/5f625cb2-9e30-4d3c-8521-761696367d77.xml
module mux2x1(I,S,Y);

input [1:0]I;
input S;
output Y;

wire [1:0]temp;
wire not_S;

not u0(not_S,S);
and u1(temp[0],not_S,I[0]);
and u2(temp[1],S,I[1]);
or u3(Y,temp[0],temp[1]);
 
endmodule
module mux2x1(I,S,Y);


input [1:0]I;
input S;
output Y;

wire [1:0]temp;
wire not_S;

not u0(not_S,S);
and u1(temp[0],not_S,I[0]);
and u2(temp[1],S,I[1]);
or u3(Y,temp[0],temp[1]);
 
endmodule