data/full_repos/permissive/204736068/SoM/RTL/common/spi_slave_core.sv
 line:125 column:31: Illegal character "'"
data/verilator_xmls/63d8f4c0-8412-4d8c-8407-ab0107adb2ea.xml
module spi_slave_core
  (

   input logic         ssn,
   input logic         sck,
   input logic         mosi,
   output logic        miso,


   input logic         clk,
   input logic         rst,
  

   output logic [7:0]  rx_data,
   output logic [23:0] address,
   output logic        we,
   output logic        rx_valid,

   input logic         tx_valid,
   input logic [7:0]   tx_data,

   input logic [7:0]   spi_id,
   input logic [7:0]   spi_status,

   output logic        reset_out,
  
   output logic        busy
   );


   parameter
     SPI_READ           = 8'h0B,
     SPI_WRITE          = 8'h02,
     SPI_POWERDOWN      = 8'hB9,
     SPI_EXIT_POWERDOWN = 8'hAB,
     SPI_ARM_RESET      = 8'h66,
     SPI_FIRE_RESET     = 8'h99
			  ;


   logic [7:0]         rx_buffer;
   logic [1:0]         addr_counter;
   logic               valid_toggle;
   logic               reset_armed;

   logic [1:0]         tx_valid_demet;
   logic [7:0]         tx_buffer[1:0];
   logic               tx_buf_sel;
   

   logic [1:0]         valid_toggle_meta;


   assign busy = ~ssn;
   

   always @(posedge clk, posedge rst)
     if (rst) begin
        valid_toggle_meta <= '0;
        rx_valid <= '0;
     end else begin
        valid_toggle_meta <= {valid_toggle_meta[0], valid_toggle};
        

        if (valid_toggle_meta[1] != valid_toggle_meta[0])
          rx_valid <= '1;
        else
          rx_valid <= '0;
     end

   

   logic [2:0] bit_index;
   logic [7:0] spi_rx_byte;
   assign spi_rx_byte = {rx_buffer[7:1], mosi};
   assign rx_data = spi_rx_byte;
   
   enum        logic [3:0] {
                            S_CMD='d0, 
                            S_ADDR='d1, 
                            S_DATA_0='d2, 
                            S_DATA_INCR='d3, 
                            S_ARM_RESET = 'd6,
                            S_FIRE_RESET = 'd7,
                            S_XXX = 'x
                            } state, next;


   always @(posedge sck, posedge ssn)
     if (ssn) state <= S_CMD;
     else     state <= next;


   always @* begin
      if (ssn)
        next = S_CMD;
      else begin
         case (state)
           S_CMD: 
             if (bit_index == 0) begin
                case(spi_rx_byte)
                  SPI_READ, SPI_WRITE: next = S_ADDR;
                  SPI_ARM_RESET: next = S_ARM_RESET;
                  default: next = S_CMD;
                endcase
             end else
               next = S_CMD;

           S_ADDR: if (bit_index==0 && addr_counter == 0) next = S_DATA_0; else next = S_ADDR;
           S_DATA_0: if (bit_index == 0) next = S_DATA_INCR; else next = S_DATA_0;
           S_DATA_INCR: next = S_DATA_INCR;
           S_ARM_RESET: next = S_ARM_RESET;
           default: next = S_CMD;
         endcase
      end
   end


   always @(posedge sck or posedge ssn or posedge rst) begin
      if (rst) begin 
         valid_toggle <= '0;
         reset_out <= '0;
         bit_index <= 'd7;
         rx_buffer <= '0;
         we <= '0;
         addr_counter <= 'd2;
         tx_buf_sel <= '0;
      end       else if (ssn) begin
         reset_out <= '0;
         bit_index <= 'd7;
         rx_buffer <= '0;
         we <= '0;
         addr_counter <= 'd2;
         tx_buf_sel <= '0;
         
      end       else begin
         if(bit_index == 0) begin
            bit_index <= 'd7;


            tx_buf_sel <= ~tx_buf_sel;

            case(state)
              S_CMD:
                begin
                   
                   case (spi_rx_byte)
                     SPI_WRITE: we <= 1'b1;
                     SPI_ARM_RESET: reset_armed <= '1;
                     SPI_FIRE_RESET: reset_out <= reset_armed ? 1'b1: 1'b0;
                   endcase

                end

              S_ADDR:
                begin
                   addr_counter <= addr_counter - 'd1;
                   case(addr_counter)
                     2: address[23:16] <= spi_rx_byte;
                     1: address[15: 8] <= spi_rx_byte;
                     0: address[ 7: 0] <= spi_rx_byte;
                   endcase
                end
              
              S_DATA_0:
                begin
                   bit_index <= 7;
                   valid_toggle <= ~valid_toggle;
                end
              
              S_DATA_INCR:
                begin
                   address <= address + 'd1;
                   bit_index <= 7;
                   valid_toggle <= ~valid_toggle;
                end
              
            endcase
         end
         else begin
            rx_buffer[bit_index] <= mosi;
            bit_index <= bit_index - 1;
         end
      end
   end


   logic tx_buf_sel_ne;
   logic tx_valid_d;
   assign miso = tx_buffer[tx_buf_sel_ne][7];
   logic [7:0] dbg_tx_buf_0, dbg_tx_buf_1;
   

   always @(negedge sck or posedge ssn or posedge tx_valid) begin
      if (tx_valid) 
         tx_valid_d <= 1'b1;
      else if (ssn)
         tx_valid_d <= 1'b0;
      else if (tx_valid_d) 
         tx_valid_d <= 1'b0;
   end


   always @(negedge sck or posedge ssn) begin
      if (ssn) begin


         tx_buffer[0] <= spi_id;
         tx_buffer[1] <= spi_status;
         tx_buf_sel_ne <= '0;
         tx_valid_demet <= '0;
      end else begin


         tx_valid_demet <= {tx_valid_demet[0], tx_valid_d};


         tx_buf_sel_ne <= tx_buf_sel;


         tx_buffer[tx_buf_sel_ne] <= {tx_buffer[tx_buf_sel_ne][6:0], 1'b0};


         if (tx_valid_demet[1])
           tx_buffer[~tx_buf_sel_ne] <= tx_data;

      end
   end

   assign dbg_tx_buf_0 = tx_buffer[0];
   assign dbg_tx_buf_1 = tx_buffer[1];

endmodule
module spi_slave_core
  (

   input logic         ssn,
   input logic         sck,
   input logic         mosi,
   output logic        miso,


   input logic         clk,
   input logic         rst,
  

   output logic [7:0]  rx_data,
   output logic [23:0] address,
   output logic        we,
   output logic        rx_valid,

   input logic         tx_valid,
   input logic [7:0]   tx_data,

   input logic [7:0]   spi_id,
   input logic [7:0]   spi_status,

   output logic        reset_out,
  
   output logic        busy
   );



   parameter
     SPI_READ           = 8'h0B,
     SPI_WRITE          = 8'h02,
     SPI_POWERDOWN      = 8'hB9,
     SPI_EXIT_POWERDOWN = 8'hAB,
     SPI_ARM_RESET      = 8'h66,
     SPI_FIRE_RESET     = 8'h99
			  ;


   logic [7:0]         rx_buffer;
   logic [1:0]         addr_counter;
   logic               valid_toggle;
   logic               reset_armed;

   logic [1:0]         tx_valid_demet;
   logic [7:0]         tx_buffer[1:0];
   logic               tx_buf_sel;
   

   logic [1:0]         valid_toggle_meta;


   assign busy = ~ssn;
   

   always @(posedge clk, posedge rst)
     if (rst) begin
        valid_toggle_meta <= '0;
        rx_valid <= '0;
     end else begin
        valid_toggle_meta <= {valid_toggle_meta[0], valid_toggle};
        

        if (valid_toggle_meta[1] != valid_toggle_meta[0])
          rx_valid <= '1;
        else
          rx_valid <= '0;
     end

   

   logic [2:0] bit_index;
   logic [7:0] spi_rx_byte;
   assign spi_rx_byte = {rx_buffer[7:1], mosi};
   assign rx_data = spi_rx_byte;
   
   enum        logic [3:0] {
                            S_CMD='d0, 
                            S_ADDR='d1, 
                            S_DATA_0='d2, 
                            S_DATA_INCR='d3, 
                            S_ARM_RESET = 'd6,
                            S_FIRE_RESET = 'd7,
                            S_XXX = 'x
                            } state, next;


   always @(posedge sck, posedge ssn)
     if (ssn) state <= S_CMD;
     else     state <= next;


   always @* begin
      if (ssn)
        next = S_CMD;
      else begin
         case (state)
           S_CMD: 
             if (bit_index == 0) begin
                case(spi_rx_byte)
                  SPI_READ, SPI_WRITE: next = S_ADDR;
                  SPI_ARM_RESET: next = S_ARM_RESET;
                  default: next = S_CMD;
                endcase
             end else
               next = S_CMD;

           S_ADDR: if (bit_index==0 && addr_counter == 0) next = S_DATA_0; else next = S_ADDR;
           S_DATA_0: if (bit_index == 0) next = S_DATA_INCR; else next = S_DATA_0;
           S_DATA_INCR: next = S_DATA_INCR;
           S_ARM_RESET: next = S_ARM_RESET;
           default: next = S_CMD;
         endcase
      end
   end


   always @(posedge sck or posedge ssn or posedge rst) begin
      if (rst) begin 
         valid_toggle <= '0;
         reset_out <= '0;
         bit_index <= 'd7;
         rx_buffer <= '0;
         we <= '0;
         addr_counter <= 'd2;
         tx_buf_sel <= '0;
      end       else if (ssn) begin
         reset_out <= '0;
         bit_index <= 'd7;
         rx_buffer <= '0;
         we <= '0;
         addr_counter <= 'd2;
         tx_buf_sel <= '0;
         
      end       else begin
         if(bit_index == 0) begin
            bit_index <= 'd7;


            tx_buf_sel <= ~tx_buf_sel;

            case(state)
              S_CMD:
                begin
                   
                   case (spi_rx_byte)
                     SPI_WRITE: we <= 1'b1;
                     SPI_ARM_RESET: reset_armed <= '1;
                     SPI_FIRE_RESET: reset_out <= reset_armed ? 1'b1: 1'b0;
                   endcase

                end

              S_ADDR:
                begin
                   addr_counter <= addr_counter - 'd1;
                   case(addr_counter)
                     2: address[23:16] <= spi_rx_byte;
                     1: address[15: 8] <= spi_rx_byte;
                     0: address[ 7: 0] <= spi_rx_byte;
                   endcase
                end
              
              S_DATA_0:
                begin
                   bit_index <= 7;
                   valid_toggle <= ~valid_toggle;
                end
              
              S_DATA_INCR:
                begin
                   address <= address + 'd1;
                   bit_index <= 7;
                   valid_toggle <= ~valid_toggle;
                end
              
            endcase
         end
         else begin
            rx_buffer[bit_index] <= mosi;
            bit_index <= bit_index - 1;
         end
      end
   end


   logic tx_buf_sel_ne;
   logic tx_valid_d;
   assign miso = tx_buffer[tx_buf_sel_ne][7];
   logic [7:0] dbg_tx_buf_0, dbg_tx_buf_1;
   

   always @(negedge sck or posedge ssn or posedge tx_valid) begin
      if (tx_valid) 
         tx_valid_d <= 1'b1;
      else if (ssn)
         tx_valid_d <= 1'b0;
      else if (tx_valid_d) 
         tx_valid_d <= 1'b0;
   end


   always @(negedge sck or posedge ssn) begin
      if (ssn) begin


         tx_buffer[0] <= spi_id;
         tx_buffer[1] <= spi_status;
         tx_buf_sel_ne <= '0;
         tx_valid_demet <= '0;
      end else begin


         tx_valid_demet <= {tx_valid_demet[0], tx_valid_d};


         tx_buf_sel_ne <= tx_buf_sel;


         tx_buffer[tx_buf_sel_ne] <= {tx_buffer[tx_buf_sel_ne][6:0], 1'b0};


         if (tx_valid_demet[1])
           tx_buffer[~tx_buf_sel_ne] <= tx_data;

      end
   end

   assign dbg_tx_buf_0 = tx_buffer[0];
   assign dbg_tx_buf_1 = tx_buffer[1];

endmodule