data/full_repos/permissive/117858561/rtl/eb1.v
data/verilator_xmls/5a93a2d9-4d20-482b-9188-e01161e1da12.xml
module eb1 #(
	parameter WIDTH = 8
) (
	input  clk, reset_n,

	input        [WIDTH-1:0] t0_data,
	input                    t0_valid,
	output logic             t0_ready,

	output logic [WIDTH-1:0] i0_data,
	output logic             i0_valid,
	input                    i0_ready
);


assign t0_ready = ~t0_valid | i0_ready;


always @(posedge clk)
	if( t0_valid & i0_ready )
		i0_data <= t0_data;


always @(posedge clk or negedge reset_n)
	if(~reset_n)
		i0_valid <= 0;
	else
		i0_valid <= (~i0_ready | t0_valid);

endmodule
module eb1 #(
	parameter WIDTH = 8
) (
	input  clk, reset_n,

	input        [WIDTH-1:0] t0_data,
	input                    t0_valid,
	output logic             t0_ready,

	output logic [WIDTH-1:0] i0_data,
	output logic             i0_valid,
	input                    i0_ready
);



assign t0_ready = ~t0_valid | i0_ready;


always @(posedge clk)
	if( t0_valid & i0_ready )
		i0_data <= t0_data;


always @(posedge clk or negedge reset_n)
	if(~reset_n)
		i0_valid <= 0;
	else
		i0_valid <= (~i0_ready | t0_valid);

endmodule