data/full_repos/permissive/158096953/z80_tb.v
 line:50: before: "forever"
1: b'%Error: data/full_repos/permissive/158096953/z80_tb.v:21: syntax error, unexpected int, expecting IDENTIFIER or \'=\' or do or final\nreg int;\n    ^~~\n%Error: data/full_repos/permissive/158096953/z80_tb.v:35: syntax error, unexpected \',\', expecting "\'{"\n int,\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/158096953/z80_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clk <= ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158096953/z80_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #20 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/158096953/z80_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/158096953/z80_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 1;\n ^\n%Error: data/full_repos/permissive/158096953/z80_tb.v:61: syntax error, unexpected <=, expecting IDENTIFIER or \'=\' or do or final\n int <= 1\'b1;\n     ^~\n%Error: data/full_repos/permissive/158096953/z80_tb.v:63: syntax error, unexpected <=, expecting "\'{"\n int <= 1\'b0;\n     ^~\n%Warning-STMTDLY: data/full_repos/permissive/158096953/z80_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n # 50620   \n ^\n%Error: data/full_repos/permissive/158096953/z80_tb.v:65: syntax error, unexpected <=, expecting "\'{"\n int <= 1\'b1;\n     ^~\n%Warning-STMTDLY: data/full_repos/permissive/158096953/z80_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n # 40\n ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n'
module z80_tb();

reg clk;
reg reset;
reg nmi;
reg int;
wire [7:0] data;
wire [15:0] address_out;
wire m1_out;
wire wr_out;
wire rd_out;
wire mreq_out;
wire iorq_out;
wire halt_out;

z80 z80_0(
	clk,
	reset,
	nmi,
	int,
	data,
	address_out,
	m1_out,
	wr_out,
	rd_out,
	mreq_out,
	iorq_out,
	halt_out
);

initial begin
	clk <= 1'b0;
	nmi <= 1'b1;
	#20 
	forever #20 clk <= ~clk;
end
initial begin
	reset = 1;
	#10 reset = 0;
	#10 reset = 1;
end

reg int_test;
initial begin

	int <= 1'b1;
	# 50620
	int <= 1'b0;
	# 40
	int <= 1'b1;



end



assign data = ((!iorq_out && !rd_out))? 8'hff : 8'hzz;
endmodule
module z80_tb();


reg clk;
reg reset;
reg nmi;
reg int;
wire [7:0] data;
wire [15:0] address_out;
wire m1_out;
wire wr_out;
wire rd_out;
wire mreq_out;
wire iorq_out;
wire halt_out;

z80 z80_0(
	clk,
	reset,
	nmi,
	int,
	data,
	address_out,
	m1_out,
	wr_out,
	rd_out,
	mreq_out,
	iorq_out,
	halt_out
);

initial begin
	clk <= 1'b0;
	nmi <= 1'b1;
	#20 
	forever #20 clk <= ~clk;
end
initial begin
	reset = 1;
	#10 reset = 0;
	#10 reset = 1;
end

reg int_test;
initial begin

	int <= 1'b1;
	# 50620
	int <= 1'b0;
	# 40
	int <= 1'b1;



end



assign data = ((!iorq_out && !rd_out))? 8'hff : 8'hzz;
endmodule