data/full_repos/permissive/143278/ivltests/pr985.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr985.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #1 ;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module child_module ( );


parameter		dec_addr_w = 4 ;
parameter		t0_addr    = 4'd0 ;
parameter		t1_addr    = 4'd0 ;



grandchild_module #(dec_addr_w, t0_addr, t1_addr) my_grandchild_module ( );

initial begin
  $display ("CHILD parameters are: %h %h %h", dec_addr_w, t0_addr, t1_addr) ;
end

endmodule
module child_module ( );



parameter		dec_addr_w = 4 ;
parameter		t0_addr    = 4'd0 ;
parameter		t1_addr    = 4'd0 ;



grandchild_module #(dec_addr_w, t0_addr, t1_addr) my_grandchild_module ( );

initial begin
  $display ("CHILD parameters are: %h %h %h", dec_addr_w, t0_addr, t1_addr) ;
end

endmodule