data/full_repos/permissive/174369527/SISD/alu_uadd-rtl.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/174369527/SISD/alu_uadd-rtl.v:37: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o_result'\n                                                                               : ... In instance alu_uadd\n   o_result[ii] <= i_s1[ii] ^ i_s2[ii] ^ r_carry[ii];\n   ^~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/174369527/SISD/alu_uadd-rtl.v:38: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'r_carry'\n                                                                               : ... In instance alu_uadd\n   r_carry[ii+1] <= (i_s1[ii] & i_s2[ii]) | (r_carry[ii] & (i_s1[ii] ^ i_s2[ii]));\n   ^~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module alu_uadd
	(
	i_s1,
	i_s2,
	o_result,
	o_carry
	);
	parameter SIZE = 8;
	input wire [SIZE-1:0] i_s1;
	input wire [SIZE-1:0] i_s2;
	output wire [SIZE-1:0] o_result;
	output wire [0:0] o_carry;

	wire [SIZE:1] r_carry = 0;

	assign o_carry = r_carry[SIZE];


	integer ii;
	always @ (*)
	begin
		o_result[0] <= i_s1[0] ^ i_s2[0];
		r_carry[1] <= i_s1[0] & i_s2[0];
		for (ii=1; ii<SIZE; ii = ii+1) begin
			o_result[ii] <= i_s1[ii] ^ i_s2[ii] ^ r_carry[ii];
			r_carry[ii+1] <= (i_s1[ii] & i_s2[ii]) | (r_carry[ii] & (i_s1[ii] ^ i_s2[ii]));
		end

	end

endmodule
module alu_uadd
	(
	i_s1,
	i_s2,
	o_result,
	o_carry
	);

	parameter SIZE = 8;
	input wire [SIZE-1:0] i_s1;
	input wire [SIZE-1:0] i_s2;
	output wire [SIZE-1:0] o_result;
	output wire [0:0] o_carry;

	wire [SIZE:1] r_carry = 0;

	assign o_carry = r_carry[SIZE];


	integer ii;
	always @ (*)
	begin
		o_result[0] <= i_s1[0] ^ i_s2[0];
		r_carry[1] <= i_s1[0] & i_s2[0];
		for (ii=1; ii<SIZE; ii = ii+1) begin
			o_result[ii] <= i_s1[ii] ^ i_s2[ii] ^ r_carry[ii];
			r_carry[ii+1] <= (i_s1[ii] & i_s2[ii]) | (r_carry[ii] & (i_s1[ii] ^ i_s2[ii]));
		end

	end

endmodule