data/full_repos/permissive/160437780/Source/FreqCounter.v
 line:8: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/160437780/Source/FreqCounter.v:8: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                           : ... In instance FreqCounter\n    output reg [9:0] Freq = 25\'b0,  \n                            ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/FreqCounter.v:13: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                            : ... In instance FreqCounter\n    reg [9:0] FreqCount = 25\'b0;  \n                          ^~~~~\n%Error: Exiting due to 2 warning(s)\n'
module FreqCounter(
    input CLK,
    input Pulse,
    input Start,
    output reg [9:0] Freq = 25'b0,
    output reg Finished = 0
    );
    
    reg [31:0] ClkCount = 32'b0;
    reg [9:0] FreqCount = 25'b0;
    reg last = 1'b0;
    reg meta = 1'b0;
    reg sync = 1'b0;
    
    localparam max = 32'd6_250_000;
    
    always @ (posedge CLK)
    begin
      if (Start)
      begin
        meta <= Pulse;
        sync <= meta;
        last <= sync;
      end
      else
      begin 
        meta = 0;
        sync = 0;
        last = 0;
      end
    end
        
    always @ (posedge CLK)
    begin
        if (~Start)
        begin
            Freq <= 0;
            ClkCount <= 0;
            FreqCount <= 0;
            Finished <= 0;
        end
        else
        begin
            if (ClkCount < max)
            begin
                 if (sync == 1 && last == 0)
                 begin
                      FreqCount <= FreqCount + 1;
                      ClkCount <= ClkCount + 1;
                 end
                 else
                 begin
                      ClkCount <= ClkCount + 1;
                 end
            end
            else
            begin
                Freq <= FreqCount;
                Finished <= 1;
            end
         end
      end
    
endmodule
module FreqCounter(
    input CLK,
    input Pulse,
    input Start,
    output reg [9:0] Freq = 25'b0,
    output reg Finished = 0
    );

    
    reg [31:0] ClkCount = 32'b0;
    reg [9:0] FreqCount = 25'b0;
    reg last = 1'b0;
    reg meta = 1'b0;
    reg sync = 1'b0;
    
    localparam max = 32'd6_250_000;
    
    always @ (posedge CLK)
    begin
      if (Start)
      begin
        meta <= Pulse;
        sync <= meta;
        last <= sync;
      end
      else
      begin 
        meta = 0;
        sync = 0;
        last = 0;
      end
    end
        
    always @ (posedge CLK)
    begin
        if (~Start)
        begin
            Freq <= 0;
            ClkCount <= 0;
            FreqCount <= 0;
            Finished <= 0;
        end
        else
        begin
            if (ClkCount < max)
            begin
                 if (sync == 1 && last == 0)
                 begin
                      FreqCount <= FreqCount + 1;
                      ClkCount <= ClkCount + 1;
                 end
                 else
                 begin
                      ClkCount <= ClkCount + 1;
                 end
            end
            else
            begin
                Freq <= FreqCount;
                Finished <= 1;
            end
         end
      end
    
endmodule