data/full_repos/permissive/117439233/hdl/src/mul_data_path.v
1: b"%Error: data/full_repos/permissive/117439233/hdl/src/mul_data_path.v:47: Cannot find file containing module: 'booth_multiplication'\n    booth_multiplication mul(\n    ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117439233/hdl/src,data/full_repos/permissive/117439233/booth_multiplication\n             data/full_repos/permissive/117439233/hdl/src,data/full_repos/permissive/117439233/booth_multiplication.v\n             data/full_repos/permissive/117439233/hdl/src,data/full_repos/permissive/117439233/booth_multiplication.sv\n             booth_multiplication\n             booth_multiplication.v\n             booth_multiplication.sv\n             obj_dir/booth_multiplication\n             obj_dir/booth_multiplication.v\n             obj_dir/booth_multiplication.sv\n%Error: data/full_repos/permissive/117439233/hdl/src/mul_data_path.v:72: Cannot find file containing module: 'CLA_64bit'\n CLA_64bit MAC(\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mul_data_path(
	input CLK,
	input RST,
	
	input A,
	input S,
	input WB,
	input [31:0] Rn,
	input [31:0] Rm,
	input [31:0] Rs,
	input [3:0] Rd,
	
	output MUL_S,
	output MUL_WB,
	output [63:0] MUL_Result,
	output [3:0] MUL_Address
	);
	
	wire [102:0] MUL_pipeline_reg_1;
	reg  [102:0] MUL_pipeline_reg_2;
	reg  [69:0]  MUL_pipeline_reg_3;
	

	
	assign MUL_pipeline_reg_1[102] = RST ? 0 : A;
	assign MUL_pipeline_reg_1[101] = RST ? 0 : S;
	assign MUL_pipeline_reg_1[100] = RST ? 0 : WB;
	assign MUL_pipeline_reg_1[99:68] = RST ? 0 : Rn;
	assign MUL_pipeline_reg_1[67:36] = RST ? 0 : Rm;
	assign MUL_pipeline_reg_1[35:4] = RST ? 0 : Rs;
	assign MUL_pipeline_reg_1[3:0] = RST ? 0 : Rd;
	

        wire [63:0] MUL_Res;        
    booth_multiplication mul(
        .A(MUL_pipeline_reg_1[67:36]),
        .B(MUL_pipeline_reg_1[35:4]),
        .hilo(MUL_Res)
    );

	always @ (posedge CLK)
		begin
			if(RST)
				begin
					MUL_pipeline_reg_2 <= 103'b0;
				end
			else
				begin
					MUL_pipeline_reg_2[102] <= MUL_pipeline_reg_1[102];
					MUL_pipeline_reg_2[101] <= MUL_pipeline_reg_1[101];
					MUL_pipeline_reg_2[100] <= MUL_pipeline_reg_1[100];
					MUL_pipeline_reg_2[99:68] <= MUL_pipeline_reg_1[99:68];
					MUL_pipeline_reg_2[67:4] <= MUL_Res;
					MUL_pipeline_reg_2[3:0] <= MUL_pipeline_reg_1[3:0];
				end
		end
		

	wire [63:0] MAC_Res;
	CLA_64bit MAC(
			.A(MUL_pipeline_reg_2[67:4]),
			.B({32'b0, MUL_pipeline_reg_2[99:68]}),
			.Cin(1'b0),
			.S(MAC_Res),
			.PG(PG),
			.GG(GG),
			.C32(C32)
			);

	wire [63:0] Result = MUL_pipeline_reg_2[102] ? MAC_Res : MUL_pipeline_reg_2[67:4];
	
	always @ (posedge CLK)
		begin
			if(RST)
				begin
					MUL_pipeline_reg_3 <= 70'b0;
				end
			else
				begin
					MUL_pipeline_reg_3[69] <= MUL_pipeline_reg_2[101];
					MUL_pipeline_reg_3[68] <= MUL_pipeline_reg_2[100];
					MUL_pipeline_reg_3[67:4] <= Result;
					MUL_pipeline_reg_3[3:0] <= MUL_pipeline_reg_2[3:0];
				end
		end
	
	assign MUL_S = MUL_pipeline_reg_3[69];
	assign MUL_WB = MUL_pipeline_reg_3[68];
	assign MUL_Result = MUL_pipeline_reg_3[67:4];
	assign MUL_Address = MUL_pipeline_reg_3[3:0];
	
endmodule
module mul_data_path(
	input CLK,
	input RST,
	
	input A,
	input S,
	input WB,
	input [31:0] Rn,
	input [31:0] Rm,
	input [31:0] Rs,
	input [3:0] Rd,
	
	output MUL_S,
	output MUL_WB,
	output [63:0] MUL_Result,
	output [3:0] MUL_Address
	);

	
	wire [102:0] MUL_pipeline_reg_1;
	reg  [102:0] MUL_pipeline_reg_2;
	reg  [69:0]  MUL_pipeline_reg_3;
	

	
	assign MUL_pipeline_reg_1[102] = RST ? 0 : A;
	assign MUL_pipeline_reg_1[101] = RST ? 0 : S;
	assign MUL_pipeline_reg_1[100] = RST ? 0 : WB;
	assign MUL_pipeline_reg_1[99:68] = RST ? 0 : Rn;
	assign MUL_pipeline_reg_1[67:36] = RST ? 0 : Rm;
	assign MUL_pipeline_reg_1[35:4] = RST ? 0 : Rs;
	assign MUL_pipeline_reg_1[3:0] = RST ? 0 : Rd;
	

        wire [63:0] MUL_Res;        
    booth_multiplication mul(
        .A(MUL_pipeline_reg_1[67:36]),
        .B(MUL_pipeline_reg_1[35:4]),
        .hilo(MUL_Res)
    );

	always @ (posedge CLK)
		begin
			if(RST)
				begin
					MUL_pipeline_reg_2 <= 103'b0;
				end
			else
				begin
					MUL_pipeline_reg_2[102] <= MUL_pipeline_reg_1[102];
					MUL_pipeline_reg_2[101] <= MUL_pipeline_reg_1[101];
					MUL_pipeline_reg_2[100] <= MUL_pipeline_reg_1[100];
					MUL_pipeline_reg_2[99:68] <= MUL_pipeline_reg_1[99:68];
					MUL_pipeline_reg_2[67:4] <= MUL_Res;
					MUL_pipeline_reg_2[3:0] <= MUL_pipeline_reg_1[3:0];
				end
		end
		

	wire [63:0] MAC_Res;
	CLA_64bit MAC(
			.A(MUL_pipeline_reg_2[67:4]),
			.B({32'b0, MUL_pipeline_reg_2[99:68]}),
			.Cin(1'b0),
			.S(MAC_Res),
			.PG(PG),
			.GG(GG),
			.C32(C32)
			);

	wire [63:0] Result = MUL_pipeline_reg_2[102] ? MAC_Res : MUL_pipeline_reg_2[67:4];
	
	always @ (posedge CLK)
		begin
			if(RST)
				begin
					MUL_pipeline_reg_3 <= 70'b0;
				end
			else
				begin
					MUL_pipeline_reg_3[69] <= MUL_pipeline_reg_2[101];
					MUL_pipeline_reg_3[68] <= MUL_pipeline_reg_2[100];
					MUL_pipeline_reg_3[67:4] <= Result;
					MUL_pipeline_reg_3[3:0] <= MUL_pipeline_reg_2[3:0];
				end
		end
	
	assign MUL_S = MUL_pipeline_reg_3[69];
	assign MUL_WB = MUL_pipeline_reg_3[68];
	assign MUL_Result = MUL_pipeline_reg_3[67:4];
	assign MUL_Address = MUL_pipeline_reg_3[3:0];
	
endmodule