data/full_repos/permissive/165514176/matrixmult_tb.v
 line:77: before: "assign"
1: b'%Warning-STMTDLY: data/full_repos/permissive/165514176/matrixmult_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        A = 0;  B = 0;  #10;\n                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165514176/matrixmult_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n   #500 \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/165514176/matrixmult_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n   #10\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/165514176/matrixmult_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n      #5  clk =  ! clk; \n      ^\n%Error: data/full_repos/permissive/165514176/matrixmult_tb.v:44: Cannot find file containing module: \'Mat_mult\'\n    Mat_mult uut (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165514176,data/full_repos/permissive/165514176/Mat_mult\n             data/full_repos/permissive/165514176,data/full_repos/permissive/165514176/Mat_mult.v\n             data/full_repos/permissive/165514176,data/full_repos/permissive/165514176/Mat_mult.sv\n             Mat_mult\n             Mat_mult.v\n             Mat_mult.sv\n             obj_dir/Mat_mult\n             obj_dir/Mat_mult.v\n             obj_dir/Mat_mult.sv\n%Error: data/full_repos/permissive/165514176/matrixmult_tb.v:52: Cannot find file containing module: \'cossin\'\n cossin trig (\n ^~~~~~\n%Error: data/full_repos/permissive/165514176/matrixmult_tb.v:65: Cannot find file containing module: \'div\'\n   div divider (\n   ^~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
parameter widthbig = 127; 
parameter width = 31;

    reg signed [widthbig:0] A;
    reg signed [widthbig:0] B;


    wire signed [widthbig:0] Res;
	 wire signed [width:0] Res2;
	reg signed [31:0]temp = 32'b1;
	reg signed [31:0]  divresult;
	reg signed [31:0] phasetocacl = 32'b1;
	reg start =0;
	wire donecos;
	wire signed [63:0] cossin;
	reg signed [31:0] cos;
	reg signed [31:0] sin;
	reg clk = 0;

    Mat_mult uut (
        .A(A), 
        .B(B), 
        .Res(Res),

		  .clk(clk)
    );
	 
	cossin trig (
  .aclk(clk),
  .s_axis_phase_tvalid(start),
  .s_axis_phase_tdata(phasetocacl),
  .m_axis_dout_tvalid(donecos),
  .m_axis_dout_tdata(cossin)
		);
	reg signed [31:0]temp1= 32'd25000;
	 reg signed [31:0]temp2 = 32'd5;
	 	 reg signed go = 1'b0;
    integer i,j,k;
	 wire [63:0] divout;
	 wire valid;
			div divider (
  .aclk(clk),
  .s_axis_divisor_tvalid(go),
  .s_axis_divisor_tdata(temp2),
  .s_axis_dividend_tvalid(go),
  .s_axis_dividend_tdata(temp1),
  .m_axis_dout_tvalid(valid),
  .m_axis_dout_tdata(divout)
		);	 

    initial begin

		  	 assign sin = cossin[31:0];
	 assign cos = cossin[63:32];
	 assign divresult = divout[63:32];
        A = 0;  B = 0;  #10;

		   start = 1'b1;
			go = 1'b1;
			#500 
			start = 1'b0;
			#10
			start = 1'b1;
			phasetocacl = 32'd88;
			
			
    end
    always@ (A or B)
    begin


		  temp = temp + 1;
	 	  A = {-32'd1,32'd2,32'd3,32'd4};
        B = {32'd1,32'd2 ,32'd3,temp};
		
	 end
	  always 
      #5  clk =  ! clk; 
		
endmodule
module tb;

parameter widthbig = 127; 
parameter width = 31;

    reg signed [widthbig:0] A;
    reg signed [widthbig:0] B;


    wire signed [widthbig:0] Res;
	 wire signed [width:0] Res2;
	reg signed [31:0]temp = 32'b1;
	reg signed [31:0]  divresult;
	reg signed [31:0] phasetocacl = 32'b1;
	reg start =0;
	wire donecos;
	wire signed [63:0] cossin;
	reg signed [31:0] cos;
	reg signed [31:0] sin;
	reg clk = 0;

    Mat_mult uut (
        .A(A), 
        .B(B), 
        .Res(Res),

		  .clk(clk)
    );
	 
	cossin trig (
  .aclk(clk),
  .s_axis_phase_tvalid(start),
  .s_axis_phase_tdata(phasetocacl),
  .m_axis_dout_tvalid(donecos),
  .m_axis_dout_tdata(cossin)
		);
	reg signed [31:0]temp1= 32'd25000;
	 reg signed [31:0]temp2 = 32'd5;
	 	 reg signed go = 1'b0;
    integer i,j,k;
	 wire [63:0] divout;
	 wire valid;
			div divider (
  .aclk(clk),
  .s_axis_divisor_tvalid(go),
  .s_axis_divisor_tdata(temp2),
  .s_axis_dividend_tvalid(go),
  .s_axis_dividend_tdata(temp1),
  .m_axis_dout_tvalid(valid),
  .m_axis_dout_tdata(divout)
		);	 

    initial begin

		  	 assign sin = cossin[31:0];
	 assign cos = cossin[63:32];
	 assign divresult = divout[63:32];
        A = 0;  B = 0;  #10;

		   start = 1'b1;
			go = 1'b1;
			#500 
			start = 1'b0;
			#10
			start = 1'b1;
			phasetocacl = 32'd88;
			
			
    end
    always@ (A or B)
    begin


		  temp = temp + 1;
	 	  A = {-32'd1,32'd2,32'd3,32'd4};
        B = {32'd1,32'd2 ,32'd3,temp};
		
	 end
	  always 
      #5  clk =  ! clk; 
		
endmodule