data/full_repos/permissive/149070951/tests/04-test-echo/echo.v
1: b'%Error: data/full_repos/permissive/149070951/tests/04-test-echo/echo.v:10: Cannot find include file: baudgen.vh\n`include "baudgen.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149070951/tests/04-test-echo,data/full_repos/permissive/149070951/baudgen.vh\n             data/full_repos/permissive/149070951/tests/04-test-echo,data/full_repos/permissive/149070951/baudgen.vh.v\n             data/full_repos/permissive/149070951/tests/04-test-echo,data/full_repos/permissive/149070951/baudgen.vh.sv\n             baudgen.vh\n             baudgen.vh.v\n             baudgen.vh.sv\n             obj_dir/baudgen.vh\n             obj_dir/baudgen.vh.v\n             obj_dir/baudgen.vh.sv\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/echo.v:14: Define or directive not defined: \'`B115200\'\n         parameter BAUDRATE = `B115200\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/echo.v:15: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n)(\n^\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/echo.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n         input wire rx,           \n         ^~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/echo.v:18: syntax error, unexpected output, expecting IDENTIFIER or do or final\n         output wire tx,           \n         ^~~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/echo.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n         output reg [3:0] leds    \n         ^~~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/echo.v:20: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/echo.v:35: syntax error, unexpected always\nalways @(posedge clk)\n^~~~~~\n%Error: Exiting due to 8 error(s)\n'
module echo #(
         parameter BAUDRATE = `B115200
)(
         input wire clk,
         input wire rx,
         output wire tx,
         output reg [3:0] leds
);


wire rcv;


wire [7:0] data;


reg rstn = 0;


wire ready;


always @(posedge clk)
  rstn <= 1;





always @(posedge clk)
  leds = data[3:0];


uart_rx #(.BAUDRATE(BAUDRATE))
  RX0 (.clk(clk),
       .rstn(rstn),
       .rx(rx),
       .rcv(rcv),
       .data(data)
      );


uart_tx #(.BAUDRATE(BAUDRATE))
  TX0 ( .clk(clk),
         .rstn(rstn),
         .start(rcv),
         .data(data),
         .tx(tx),
         .ready(ready)
       );


endmodule
module echo #(
         parameter BAUDRATE = `B115200
)(
         input wire clk,
         input wire rx,
         output wire tx,
         output reg [3:0] leds
);



wire rcv;


wire [7:0] data;


reg rstn = 0;


wire ready;


always @(posedge clk)
  rstn <= 1;





always @(posedge clk)
  leds = data[3:0];


uart_rx #(.BAUDRATE(BAUDRATE))
  RX0 (.clk(clk),
       .rstn(rstn),
       .rx(rx),
       .rcv(rcv),
       .data(data)
      );


uart_tx #(.BAUDRATE(BAUDRATE))
  TX0 ( .clk(clk),
         .rstn(rstn),
         .start(rcv),
         .data(data),
         .tx(tx),
         .ready(ready)
       );


endmodule