data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/pulse_synchronizer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/pulse_synchronizer.v:26: Operator EQ expects 56 bits on the LHS, but LHS\'s VARREF \'MODE\' generates 40 bits.\n                                                                                                                                       : ... In instance pulse_synchronizer\n  generate if (MODE == "POSEDGE") begin\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/pulse_synchronizer.v:31: Operator EQ expects 56 bits on the LHS, but LHS\'s VARREF \'MODE\' generates 40 bits.\n                                                                                                                                       : ... In instance pulse_synchronizer\n  end else if (MODE == "NEGEDGE") begin\n                    ^~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/pulse_synchronizer.v:50: Cannot find file containing module: \'synchronizer\'\n  synchronizer #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/synchronizer\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/synchronizer.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/synchronizer.sv\n             synchronizer\n             synchronizer.v\n             synchronizer.sv\n             obj_dir/synchronizer\n             obj_dir/synchronizer.v\n             obj_dir/synchronizer.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/pulse_synchronizer.v:57: Cannot find file containing module: \'synchronizer\'\n  synchronizer #(\n  ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module pulse_synchronizer #(
  parameter MODE   = "PULSE",
  parameter STAGES = 2
) (
  input   clk_a,
  input   rst_a,
  input   pulse_a,
  output  busy_a,
  input   clk_b,
  output  pulse_b
);

  wire trigger;
  generate if (MODE == "POSEDGE") begin
    reg pulse_a_del_pe = 1'b0;
    always @ (posedge clk_a)
      pulse_a_del_pe <= rst_a ? 1'b0 : pulse_a;
    assign trigger = pulse_a & ~pulse_a_del_pe;
  end else if (MODE == "NEGEDGE") begin
    reg pulse_a_del_ne = 1'b1;
    always @ (posedge clk_a)
      pulse_a_del_ne <= rst_a ? 1'b1 : pulse_a;
    assign trigger = ~pulse_a & pulse_a_del_ne;
  end else begin
    assign trigger = pulse_a;
  end endgenerate


  reg pulse_toggle_a = 1'b0;
  always @(posedge clk_a) begin
    pulse_toggle_a <= rst_a ? 1'b0 : (pulse_toggle_a ^ (trigger & ~busy_a));
  end

  wire pulse_toggle_b;
  reg  pulse_toggle_b_del = 1'b0;
  wire handshake_toggle_a;

  synchronizer #(
    .STAGES(STAGES), .INITIAL_VAL(0)
  ) toggle_sync_i (
    .clk(clk_b), .rst(1'b0), .in(pulse_toggle_a), .out(pulse_toggle_b)
  );


  synchronizer #(
    .STAGES(STAGES), .INITIAL_VAL(0)
  ) handshake_sync_i (
    .clk(clk_a), .rst(1'b0), .in(pulse_toggle_b_del), .out(handshake_toggle_a)
  );

  always @(posedge clk_b) begin
    pulse_toggle_b_del <= pulse_toggle_b;
  end

  assign pulse_b = pulse_toggle_b_del ^ pulse_toggle_b;
  assign busy_a = pulse_toggle_a ^ handshake_toggle_a;

endmodule
module pulse_synchronizer #(
  parameter MODE   = "PULSE",
  parameter STAGES = 2
) (
  input   clk_a,
  input   rst_a,
  input   pulse_a,
  output  busy_a,
  input   clk_b,
  output  pulse_b
);


  wire trigger;
  generate if (MODE == "POSEDGE") begin
    reg pulse_a_del_pe = 1'b0;
    always @ (posedge clk_a)
      pulse_a_del_pe <= rst_a ? 1'b0 : pulse_a;
    assign trigger = pulse_a & ~pulse_a_del_pe;
  end else if (MODE == "NEGEDGE") begin
    reg pulse_a_del_ne = 1'b1;
    always @ (posedge clk_a)
      pulse_a_del_ne <= rst_a ? 1'b1 : pulse_a;
    assign trigger = ~pulse_a & pulse_a_del_ne;
  end else begin
    assign trigger = pulse_a;
  end endgenerate


  reg pulse_toggle_a = 1'b0;
  always @(posedge clk_a) begin
    pulse_toggle_a <= rst_a ? 1'b0 : (pulse_toggle_a ^ (trigger & ~busy_a));
  end

  wire pulse_toggle_b;
  reg  pulse_toggle_b_del = 1'b0;
  wire handshake_toggle_a;

  synchronizer #(
    .STAGES(STAGES), .INITIAL_VAL(0)
  ) toggle_sync_i (
    .clk(clk_b), .rst(1'b0), .in(pulse_toggle_a), .out(pulse_toggle_b)
  );


  synchronizer #(
    .STAGES(STAGES), .INITIAL_VAL(0)
  ) handshake_sync_i (
    .clk(clk_a), .rst(1'b0), .in(pulse_toggle_b_del), .out(handshake_toggle_a)
  );

  always @(posedge clk_b) begin
    pulse_toggle_b_del <= pulse_toggle_b;
  end

  assign pulse_b = pulse_toggle_b_del ^ pulse_toggle_b;
  assign busy_a = pulse_toggle_a ^ handshake_toggle_a;

endmodule