data/full_repos/permissive/10136357/hardware/src/tests/top_test.v
None: at end of input
1: b'%Error: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10136357/hardware/src/tests,data/full_repos/permissive/10136357/consts.vh\n             data/full_repos/permissive/10136357/hardware/src/tests,data/full_repos/permissive/10136357/consts.vh.v\n             data/full_repos/permissive/10136357/hardware/src/tests,data/full_repos/permissive/10136357/consts.vh.sv\n             consts.vh\n             consts.vh.v\n             consts.vh.sv\n             obj_dir/consts.vh\n             obj_dir/consts.vh.v\n             obj_dir/consts.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:39: Unsupported: Ignoring delay on this delayed statement.\n always #(half_cycle) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:41: Define or directive not defined: \'`STR_LEN\'\n wire [(`STR_LEN * 8) - 1:0] s;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:41: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [(`STR_LEN * 8) - 1:0] s;\n                 ^\n%Error: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:53: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars();\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #(cycle);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #(cycle);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #(cycle);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10136357/hardware/src/tests/top_test.v:65: Unsupported: Ignoring delay on this delayed statement.\n   #(cycle);\n   ^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n'
module top_test ();
	reg clk;
	reg reset;

	initial clk = 0;
	parameter half_cycle = 5;
	localparam cycle = 2 * half_cycle;
	localparam timeout = 100;

	always #(half_cycle) clk = ~clk;

	wire [(`STR_LEN * 8) - 1:0] s;

	top top(.clk(clk), .reset(reset));

	inst_decoder id(.str(s), 
		.jump_target(top.dpath.jump_target), 
		.branch_target(top.dpath.branch_target),
		.inst(top.dpath.inst));

	integer i;

	initial begin
		$dumpvars();

		i = 0;


		#(cycle);
		reset = 1;
		#(cycle);
		reset = 0;
		#(cycle);

		while (top.dpath.cp.tohost == 0 && i < timeout) begin
			#(cycle);
			i = i + 1;
			$display("C %10d: pc=[%08x] [%s] W[r%2d=%08x][%b] R[r%2d=%08x] R[r%2d=%08x] inst=[%08x] %s", 
				i, top.dpath.pc, top.stall ? "S" : " ",
				top.dpath.ex_wd, top.dpath.rf_wdata, top.dpath.rf_wr_en,
				top.dpath.ex_rs1, top.dpath.rf_rd1, 
				top.dpath.ex_rs2, top.dpath.rf_rd2,
				top.dpath.inst,
				top.stall ? "" : s);
		end
	
		if (i == timeout) begin
			$display("*** TIMEOUT ***");
			$finish();
		end

		if (top.dpath.cp.tohost == 1) begin
			$display("*** SUCCESS (tohost = 1) ***");
		end else begin
			$display("*** FAILURE (tohost = %d) ***", top.dpath.cp.tohost);
		end

		$finish();
	end
	
endmodule
module top_test ();

	reg clk;
	reg reset;

	initial clk = 0;
	parameter half_cycle = 5;
	localparam cycle = 2 * half_cycle;
	localparam timeout = 100;

	always #(half_cycle) clk = ~clk;

	wire [(`STR_LEN * 8) - 1:0] s;

	top top(.clk(clk), .reset(reset));

	inst_decoder id(.str(s), 
		.jump_target(top.dpath.jump_target), 
		.branch_target(top.dpath.branch_target),
		.inst(top.dpath.inst));

	integer i;

	initial begin
		$dumpvars();

		i = 0;


		#(cycle);
		reset = 1;
		#(cycle);
		reset = 0;
		#(cycle);

		while (top.dpath.cp.tohost == 0 && i < timeout) begin
			#(cycle);
			i = i + 1;
			$display("C %10d: pc=[%08x] [%s] W[r%2d=%08x][%b] R[r%2d=%08x] R[r%2d=%08x] inst=[%08x] %s", 
				i, top.dpath.pc, top.stall ? "S" : " ",
				top.dpath.ex_wd, top.dpath.rf_wdata, top.dpath.rf_wr_en,
				top.dpath.ex_rs1, top.dpath.rf_rd1, 
				top.dpath.ex_rs2, top.dpath.rf_rd2,
				top.dpath.inst,
				top.stall ? "" : s);
		end
	
		if (i == timeout) begin
			$display("*** TIMEOUT ***");
			$finish();
		end

		if (top.dpath.cp.tohost == 1) begin
			$display("*** SUCCESS (tohost = 1) ***");
		end else begin
			$display("*** FAILURE (tohost = %d) ***", top.dpath.cp.tohost);
		end

		$finish();
	end
	
endmodule