data/full_repos/permissive/148324174/FIFO/sync_w2r.v
data/verilator_xmls/6fdbb551-f468-40dd-8a23-3ca7770f8d1f.xml
module sync_w2r #(
    parameter ADDRSIZE = 4
    )(
    output reg [ADDRSIZE:0] rwptr2,
    input      [ADDRSIZE:0] wptr,
    input                   rclk, rrst
    );

reg [ADDRSIZE:0] rwptr1;

always @(posedge rclk or posedge rrst) begin
    if (rrst) begin
        {rwptr2, rwptr1} <= 0;
    end
    else begin
        {rwptr2, rwptr1} <= {rwptr1, wptr};
    end
end

endmodule
module sync_w2r #(
    parameter ADDRSIZE = 4
    )(
    output reg [ADDRSIZE:0] rwptr2,
    input      [ADDRSIZE:0] wptr,
    input                   rclk, rrst
    );


reg [ADDRSIZE:0] rwptr1;

always @(posedge rclk or posedge rrst) begin
    if (rrst) begin
        {rwptr2, rwptr1} <= 0;
    end
    else begin
        {rwptr2, rwptr1} <= {rwptr1, wptr};
    end
end

endmodule