data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #101 in = 32\'h0080ffff;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #325150 \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit_tb.v:24: Cannot find file containing module: \'FP_to_posit\'\nFP_to_posit #(.N(N), .E(E), .es(es)) d1 (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/FP_to_posit\n             data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/FP_to_posit.v\n             data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/FP_to_posit.sv\n             FP_to_posit\n             FP_to_posit.v\n             FP_to_posit.sv\n             obj_dir/FP_to_posit\n             obj_dir/FP_to_posit.v\n             obj_dir/FP_to_posit.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FP_to_posit_tb_v;

function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction

parameter N=32;
parameter E=8;
parameter Bs=log2(N);
parameter es = 4;

reg [N-1:0] in;
reg clk;

wire [N-1:0] out;


FP_to_posit #(.N(N), .E(E), .es(es)) d1 (
	.in(in), 
	.out(out) 
	);


	initial begin

		clk = 1;

		#101 in = 32'h0080ffff;
		#325150 
		$fclose(outfile);
		$finish;
	end
	
always #5 clk=~clk;
always @(posedge clk) begin
	if (in < 32'h7f7fffff)
		in <= in + 65535;
end

integer outfile;
initial outfile = $fopen("FP_to_posit_out.txt", "wb");
  always @(negedge clk) begin
     $fwrite(outfile, "%h\t%h\n",in,out);
  end

endmodule
module FP_to_posit_tb_v;


function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction

parameter N=32;
parameter E=8;
parameter Bs=log2(N);
parameter es = 4;

reg [N-1:0] in;
reg clk;

wire [N-1:0] out;


FP_to_posit #(.N(N), .E(E), .es(es)) d1 (
	.in(in), 
	.out(out) 
	);


	initial begin

		clk = 1;

		#101 in = 32'h0080ffff;
		#325150 
		$fclose(outfile);
		$finish;
	end
	
always #5 clk=~clk;
always @(posedge clk) begin
	if (in < 32'h7f7fffff)
		in <= in + 65535;
end

integer outfile;
initial outfile = $fopen("FP_to_posit_out.txt", "wb");
  always @(negedge clk) begin
     $fwrite(outfile, "%h\t%h\n",in,out);
  end

endmodule