data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v
None: at end of input
1: b'%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:26: Cannot find include file: top_defines.vh\n`include "top_defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159016511/src/rtl/ahb,data/full_repos/permissive/159016511/top_defines.vh\n             data/full_repos/permissive/159016511/src/rtl/ahb,data/full_repos/permissive/159016511/top_defines.vh.v\n             data/full_repos/permissive/159016511/src/rtl/ahb,data/full_repos/permissive/159016511/top_defines.vh.sv\n             top_defines.vh\n             top_defines.vh.v\n             top_defines.vh.sv\n             obj_dir/top_defines.vh\n             obj_dir/top_defines.vh.v\n             obj_dir/top_defines.vh.sv\n%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:27: Cannot find include file: core_defines.vh\n`include "core_defines.vh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:28: Cannot find include file: ahb_defines.vh\n`include "ahb_defines.vh" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:38: Define or directive not defined: \'`AHB_DATA_WIDTH\'\n input wire [`AHB_DATA_WIDTH - 1 : 0] HRDATA,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:40: Define or directive not defined: \'`AHB_ADDR_WIDTH\'\n output wire [`AHB_ADDR_WIDTH - 1 : 0] HADDR,\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:44: Define or directive not defined: \'`ADDR_WIDTH\'\n input wire[`ADDR_WIDTH - 1 : 0 ] itcm_auto_load_addr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:46: Define or directive not defined: \'`ADDR_WIDTH\'\n input wire [`ADDR_WIDTH - 1 : 0] IAHB_addr,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:48: Define or directive not defined: \'`DATA_WIDTH\'\n output wire [`DATA_WIDTH - 1 : 0] IAHB_read_data,\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:127: Define or directive not defined: \'`NONSEQ\'\nassign HTRANS  = itcm_auto_load? `NONSEQ : ((state == ADDR_S) ? `NONSEQ : `IDLE);\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:127: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nassign HTRANS  = itcm_auto_load? `NONSEQ : ((state == ADDR_S) ? `NONSEQ : `IDLE);\n                                         ^\n%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:127: Define or directive not defined: \'`NONSEQ\'\nassign HTRANS  = itcm_auto_load? `NONSEQ : ((state == ADDR_S) ? `NONSEQ : `IDLE);\n                                                                ^~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/ahb/IAHB.v:127: Define or directive not defined: \'`IDLE\'\nassign HTRANS  = itcm_auto_load? `NONSEQ : ((state == ADDR_S) ? `NONSEQ : `IDLE);\n                                                                          ^~~~~\n%Error: Exiting due to 12 error(s)\n'
module IAHB (

	input wire HCLK,
	input wire HRESETn,
	output wire HBUSREQ,
	output wire HLOCK,
	input wire HGRANT,
	input wire HREADY,
	input wire [1:0] HRESP,
	input wire [`AHB_DATA_WIDTH - 1 : 0] HRDATA,
	output wire [1:0] HTRANS,
	output wire [`AHB_ADDR_WIDTH - 1 : 0] HADDR,
	output wire HWRITE,

	input wire itcm_auto_load,
	input wire[`ADDR_WIDTH - 1 : 0 ] itcm_auto_load_addr,
	input wire IAHB_access,
	input wire [`ADDR_WIDTH - 1 : 0] IAHB_addr,
	output wire IAHB_ready,
	output wire [`DATA_WIDTH - 1 : 0] IAHB_read_data,
	output wire IAHB_read_data_valid
);

parameter WAIT_FOR_GRANT_S 	= 2'b00;
parameter ADDR_S		= 2'b01;
parameter DATA_S		= 2'b10;

parameter FIFO_DEPTH = 8;
parameter PTR_WIDTH = 3;

reg[1:0] state, next_state;

always @ (posedge HCLK or negedge HRESETn)
begin
	if(!HRESETn)
	begin
		state <= WAIT_FOR_GRANT_S;
	end
	else
	begin
		state <= next_state;
	end
end

always @ *
begin
	case(state)
		WAIT_FOR_GRANT_S: 
		begin
			if(HBUSREQ && HGRANT && HREADY)
			begin
				next_state = ADDR_S;
			end
			else
			begin
				next_state = WAIT_FOR_GRANT_S;
			end
		end
		ADDR_S:
		begin
			if(HREADY)
			begin
				next_state = DATA_S;
			end
			else
			begin
				next_state = ADDR_S;
			end
		end
		DATA_S:
		begin
			if(HREADY)
			begin
				if(itcm_auto_load)
				begin
					next_state = DATA_S;
				end
				else
				begin
					next_state = WAIT_FOR_GRANT_S;
				end
			end
			else
			begin
				next_state = DATA_S;
			end
		end
		default:
		begin
			next_state = WAIT_FOR_GRANT_S;
		end
	endcase
end




assign HBUSREQ 	 = (IAHB_access && !HLOCK) || itcm_auto_load;
assign HTRANS	 = itcm_auto_load? `NONSEQ : ((state == ADDR_S) ? `NONSEQ : `IDLE);
assign HADDR	 = itcm_auto_load? itcm_auto_load_addr : ((state == ADDR_S) ? IAHB_addr : 32'h0);
assign HWRITE	 = 1'b0;
assign HLOCK     = |state;


assign IAHB_ready = HGRANT && HREADY;
assign IAHB_read_data_valid = (state == DATA_S) && HREADY;
assign IAHB_read_data = HRDATA;




endmodule
module IAHB (

	input wire HCLK,
	input wire HRESETn,
	output wire HBUSREQ,
	output wire HLOCK,
	input wire HGRANT,
	input wire HREADY,
	input wire [1:0] HRESP,
	input wire [`AHB_DATA_WIDTH - 1 : 0] HRDATA,
	output wire [1:0] HTRANS,
	output wire [`AHB_ADDR_WIDTH - 1 : 0] HADDR,
	output wire HWRITE,

	input wire itcm_auto_load,
	input wire[`ADDR_WIDTH - 1 : 0 ] itcm_auto_load_addr,
	input wire IAHB_access,
	input wire [`ADDR_WIDTH - 1 : 0] IAHB_addr,
	output wire IAHB_ready,
	output wire [`DATA_WIDTH - 1 : 0] IAHB_read_data,
	output wire IAHB_read_data_valid
);


parameter WAIT_FOR_GRANT_S 	= 2'b00;
parameter ADDR_S		= 2'b01;
parameter DATA_S		= 2'b10;

parameter FIFO_DEPTH = 8;
parameter PTR_WIDTH = 3;

reg[1:0] state, next_state;

always @ (posedge HCLK or negedge HRESETn)
begin
	if(!HRESETn)
	begin
		state <= WAIT_FOR_GRANT_S;
	end
	else
	begin
		state <= next_state;
	end
end

always @ *
begin
	case(state)
		WAIT_FOR_GRANT_S: 
		begin
			if(HBUSREQ && HGRANT && HREADY)
			begin
				next_state = ADDR_S;
			end
			else
			begin
				next_state = WAIT_FOR_GRANT_S;
			end
		end
		ADDR_S:
		begin
			if(HREADY)
			begin
				next_state = DATA_S;
			end
			else
			begin
				next_state = ADDR_S;
			end
		end
		DATA_S:
		begin
			if(HREADY)
			begin
				if(itcm_auto_load)
				begin
					next_state = DATA_S;
				end
				else
				begin
					next_state = WAIT_FOR_GRANT_S;
				end
			end
			else
			begin
				next_state = DATA_S;
			end
		end
		default:
		begin
			next_state = WAIT_FOR_GRANT_S;
		end
	endcase
end




assign HBUSREQ 	 = (IAHB_access && !HLOCK) || itcm_auto_load;
assign HTRANS	 = itcm_auto_load? `NONSEQ : ((state == ADDR_S) ? `NONSEQ : `IDLE);
assign HADDR	 = itcm_auto_load? itcm_auto_load_addr : ((state == ADDR_S) ? IAHB_addr : 32'h0);
assign HWRITE	 = 1'b0;
assign HLOCK     = |state;


assign IAHB_ready = HGRANT && HREADY;
assign IAHB_read_data_valid = (state == DATA_S) && HREADY;
assign IAHB_read_data = HRDATA;




endmodule