data/full_repos/permissive/168395472/problems/07_cpu_v1/reg_file.v
1: b'%Error: data/full_repos/permissive/168395472/problems/07_cpu_v1/reg_file.v:35: Unsupported or unknown PLI call: $strobe\n    $strobe("CPUv1: x0: %h x4: %h  x8: %h x12: %h\\nCPUv1: x1: %h x5: %h  x9: %h x13: %h\\nCPUv1: x2: %h x6: %h x10: %h x14: %h\\nCPUv1: x3: %h x7: %h x11: %h x15: %h",\n    ^~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reg_file(
    input clk,
    input [4:0]raddr0,
    input [4:0]raddr1,
    input [4:0]waddr,
    input [31:0]wdata,
    input we,

    output [31:0]rdata0,
    output [31:0]rdata1
);

reg [31:0]x[31:0];

genvar i;
generate
for (i = 0; i < 32; i = i + 1)
begin : reg_init
    initial
        x[i] = 32'b0;
end
endgenerate



always @(posedge clk) begin

    $strobe("CPUv1: x0: %h x4: %h  x8: %h x12: %h\nCPUv1: x1: %h x5: %h  x9: %h x13: %h\nCPUv1: x2: %h x6: %h x10: %h x14: %h\nCPUv1: x3: %h x7: %h x11: %h x15: %h",
            32'b0, x[4],   x[8],  x[12],   x[1],  x[5],   x[9],  x[13],   x[2],  x[6],  x[10],  x[14],   x[3],  x[7],  x[11],  x[15]);
end

endmodule
module reg_file(
    input clk,
    input [4:0]raddr0,
    input [4:0]raddr1,
    input [4:0]waddr,
    input [31:0]wdata,
    input we,

    output [31:0]rdata0,
    output [31:0]rdata1
);


reg [31:0]x[31:0];

genvar i;
generate
for (i = 0; i < 32; i = i + 1)
begin : reg_init
    initial
        x[i] = 32'b0;
end
endgenerate



always @(posedge clk) begin

    $strobe("CPUv1: x0: %h x4: %h  x8: %h x12: %h\nCPUv1: x1: %h x5: %h  x9: %h x13: %h\nCPUv1: x2: %h x6: %h x10: %h x14: %h\nCPUv1: x3: %h x7: %h x11: %h x15: %h",
            32'b0, x[4],   x[8],  x[12],   x[1],  x[5],   x[9],  x[13],   x[2],  x[6],  x[10],  x[14],   x[3],  x[7],  x[11],  x[15]);
end

endmodule