data/full_repos/permissive/188580251/Project5/Reg_D.v
None: at end of input
data/verilator_xmls/efcf4f25-3fd8-4d40-81c8-a3405a4ecd60.xml
module Reg_D(
    input Clock,
    input Reset,
    input Enable,
    input [31:0] IR_F,
    input [31:0] PC_F,
    output reg [31:0] IR_D,
    output reg [31:0] NPC_D
    );

	initial begin
		IR_D  = 0;
		NPC_D = 0;
	end
	
	always @ (posedge Clock) begin
		if(Reset == 1) begin
			IR_D  <= 0;
			NPC_D <= 0;
		end
		else if(Enable == 1) begin
			IR_D  <= IR_D;
			NPC_D <= NPC_D;
		end
		else begin
			IR_D  <= IR_F;
			NPC_D <= PC_F;
		end
	end

endmodule
module Reg_D(
    input Clock,
    input Reset,
    input Enable,
    input [31:0] IR_F,
    input [31:0] PC_F,
    output reg [31:0] IR_D,
    output reg [31:0] NPC_D
    );


	initial begin
		IR_D  = 0;
		NPC_D = 0;
	end
	
	always @ (posedge Clock) begin
		if(Reset == 1) begin
			IR_D  <= 0;
			NPC_D <= 0;
		end
		else if(Enable == 1) begin
			IR_D  <= IR_D;
			NPC_D <= NPC_D;
		end
		else begin
			IR_D  <= IR_F;
			NPC_D <= PC_F;
		end
	end

endmodule