data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Basic_Gates/mt2015_q4a.v
data/verilator_xmls/c889c847-3d87-49a6-91e3-87bce9512d29.xml
module top_module (input x, input y, output z);
    assign z = (x^y)&x;
endmodule
module top_module (input x, input y, output z);

    assign z = (x^y)&x;
endmodule