data/full_repos/permissive/143278/ivltests/assign_delay.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/assign_delay.v:32: Unsupported: Ignoring delay on this delayed statement.\n        # 20 b = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/assign_delay.v:33: Unsupported: Ignoring delay on this delayed statement.\n        # 5 if (a !== 0) begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/assign_delay.v:38: Unsupported: Ignoring delay on this delayed statement.\n        # 6 if (a !== 1) begin\n        ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
   wire a;
   reg b;

   assign #10 a = b;

   initial begin
        b = 0;
        # 20 b = 1;
        # 5 if (a !== 0) begin
            $display("FAILED -- a is %b", a);
            $finish;
        end

        # 6 if (a !== 1) begin
            $display("FAILED -- a is %b, should be 1", a);
            $finish;
        end

        $display("PASSED");
    end
endmodule
module test;

   wire a;
   reg b;

   assign #10 a = b;

   initial begin
        b = 0;
        # 20 b = 1;
        # 5 if (a !== 0) begin
            $display("FAILED -- a is %b", a);
            $finish;
        end

        # 6 if (a !== 1) begin
            $display("FAILED -- a is %b, should be 1", a);
            $finish;
        end

        $display("PASSED");
    end
endmodule