data/full_repos/permissive/106966316/memoria_datos_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoria_datos_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/106966316/memoria_datos_tb.v:31: Cannot find file containing module: \'memoria_datos\'\n memoria_datos uut(\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoria_datos\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoria_datos.v\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoria_datos.sv\n             memoria_datos\n             memoria_datos.v\n             memoria_datos.sv\n             obj_dir/memoria_datos\n             obj_dir/memoria_datos.v\n             obj_dir/memoria_datos.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memoria_datos_tb();
	reg clk;
    reg EscrMem;
    reg [31:0] Direc;
    reg [31:0] Datain;
    reg LeerMem;
    wire [31:0] Dataout;

	memoria_datos uut(
		.clk(clk),
		.EscrMem(EscrMem),
		.Direc(Direc),
		.Datain(Datain),
		.LeerMem(LeerMem),
		.Dataout(Dataout)
		);

always
	begin
		clk = 1'b1;
        #50;
        clk = 1'b0;
        #50;
	end

initial begin
	EscrMem	=	1'b1;
    LeerMem	=	1'b0;
	Direc 	=	32'b0000_0000_0000_0000__0000_0100_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;

	#100;

	EscrMem	=	1'b1;
    LeerMem	=	1'b0;
	Direc 	=	32'b0000_0000_0000_0000__0000_0000_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0010;


	#100;
	
	EscrMem	=	1'b1;
    LeerMem =    1'b0;
    Direc   =    32'b0000_0000_0000_0000__0000_0010_0110_0000;
    Datain  =    32'b0000_0000_0000_0000__0000_0000_0000_0011;


	#100;

	EscrMem	=	1'b0;
    LeerMem	=	1'b1;
	Direc 	=	32'b0000_0000_0000_0000__0000_0100_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;
	


	#100;
	
	EscrMem	=	1'b0;
    LeerMem    =    1'b1;
    Direc     =    32'b0000_0000_0000_0000__0000_0000_0110_0000;
    Datain    =    32'b0000_0000_0000_0000__0000_0000_0000_0010;


	#100;

	EscrMem	=	1'b0;
    LeerMem	=	1'b1;
	Direc 	=	32'b0000_0000_0000_0000__0000_0010_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0010;



end


    
endmodule
module memoria_datos_tb();

	reg clk;
    reg EscrMem;
    reg [31:0] Direc;
    reg [31:0] Datain;
    reg LeerMem;
    wire [31:0] Dataout;

	memoria_datos uut(
		.clk(clk),
		.EscrMem(EscrMem),
		.Direc(Direc),
		.Datain(Datain),
		.LeerMem(LeerMem),
		.Dataout(Dataout)
		);

always
	begin
		clk = 1'b1;
        #50;
        clk = 1'b0;
        #50;
	end

initial begin
	EscrMem	=	1'b1;
    LeerMem	=	1'b0;
	Direc 	=	32'b0000_0000_0000_0000__0000_0100_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;

	#100;

	EscrMem	=	1'b1;
    LeerMem	=	1'b0;
	Direc 	=	32'b0000_0000_0000_0000__0000_0000_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0010;


	#100;
	
	EscrMem	=	1'b1;
    LeerMem =    1'b0;
    Direc   =    32'b0000_0000_0000_0000__0000_0010_0110_0000;
    Datain  =    32'b0000_0000_0000_0000__0000_0000_0000_0011;


	#100;

	EscrMem	=	1'b0;
    LeerMem	=	1'b1;
	Direc 	=	32'b0000_0000_0000_0000__0000_0100_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;
	


	#100;
	
	EscrMem	=	1'b0;
    LeerMem    =    1'b1;
    Direc     =    32'b0000_0000_0000_0000__0000_0000_0110_0000;
    Datain    =    32'b0000_0000_0000_0000__0000_0000_0000_0010;


	#100;

	EscrMem	=	1'b0;
    LeerMem	=	1'b1;
	Direc 	=	32'b0000_0000_0000_0000__0000_0010_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0010;



end


    
endmodule