data/full_repos/permissive/161029703/src/periph/seg_disp.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/161029703/src/periph/seg_disp.v:28: Operator ADD expects 3 bits on the RHS, but RHS\'s REDAND generates 1 bits.\n                                                                             : ... In instance seg_disp\n        scan <= scan + (&divider);\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161029703/src/periph/seg_disp.v:30: Operator NOT expects 8 bits on the LHS, but LHS\'s ARRAYSEL generates 7 bits.\n                                                                             : ... In instance seg_disp\n        seg <= ~seg_all[scan];\n               ^\n%Error: Exiting due to 2 warning(s)\n'
module SEG7_LUT (   oSEG,iDIG   );
input   [3:0]   iDIG;
output  [6:0]   oSEG;
reg     [6:0]   oSEG;
always @(*)
begin
        case(iDIG)
        4'h1: oSEG = 7'b1111001;
        4'h2: oSEG = 7'b0100100;
        4'h3: oSEG = 7'b0110000;
        4'h4: oSEG = 7'b0011001;
        4'h5: oSEG = 7'b0010010;
        4'h6: oSEG = 7'b0000010;
        4'h7: oSEG = 7'b1111000;
        4'h8: oSEG = 7'b0000000;
        4'h9: oSEG = 7'b0011000;
        4'ha: oSEG = 7'b0001000;
        4'hb: oSEG = 7'b0000011;
        4'hc: oSEG = 7'b1000110;
        4'hd: oSEG = 7'b0100001;
        4'he: oSEG = 7'b0000110;
        4'hf: oSEG = 7'b0001110;
        4'h0: oSEG = 7'b1000000;
        endcase
end
endmodule
module SEG7_LUT (   oSEG,iDIG   );

input   [3:0]   iDIG;
output  [6:0]   oSEG;
reg     [6:0]   oSEG;
always @(*)
begin
        case(iDIG)
        4'h1: oSEG = 7'b1111001;
        4'h2: oSEG = 7'b0100100;
        4'h3: oSEG = 7'b0110000;
        4'h4: oSEG = 7'b0011001;
        4'h5: oSEG = 7'b0010010;
        4'h6: oSEG = 7'b0000010;
        4'h7: oSEG = 7'b1111000;
        4'h8: oSEG = 7'b0000000;
        4'h9: oSEG = 7'b0011000;
        4'ha: oSEG = 7'b0001000;
        4'hb: oSEG = 7'b0000011;
        4'hc: oSEG = 7'b1000110;
        4'hd: oSEG = 7'b0100001;
        4'he: oSEG = 7'b0000110;
        4'hf: oSEG = 7'b0001110;
        4'h0: oSEG = 7'b1000000;
        endcase
end
endmodule