data/full_repos/permissive/117179686/src/data_ram.v
1: b'%Error: data/full_repos/permissive/117179686/src/data_ram.v:1: Cannot find include file: defines.v\n`include "defines.v"  \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v.v\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:9: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] mem_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`DataAddrBus] mem_addr,\n                        ^\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:10: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] pc_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire who,  \n ^~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`DataBus] data_i,  \n ^~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:13: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] data_i,  \n            ^~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:14: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus] data_o,   \n            ^~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:17: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:22: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:28: Define or directive not defined: \'`ChipDisable\'\n  if (pc_ce == `ChipDisable || who == 1\'b1) begin\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:29: Define or directive not defined: \'`ZeroWord\'\n   inst <= `ZeroWord;\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:42: Define or directive not defined: \'`ChipDisable\'\n  if (mem_ce == `ChipDisable || who == 1\'b0) begin\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:44: Define or directive not defined: \'`WriteEnable\'\n  end else if(we == `WriteEnable) begin\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:77: Define or directive not defined: \'`ChipDisable\'\n  if (mem_ce == `ChipDisable || who == 1\'b0) begin\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:78: Define or directive not defined: \'`ZeroWord\'\n   data_o <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:79: Define or directive not defined: \'`WriteDisable\'\n  end else if(we == `WriteDisable) begin\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/data_ram.v:86: Define or directive not defined: \'`ZeroWord\'\n   data_o <= `ZeroWord;\n             ^~~~~~~~~\n%Error: Exiting due to 18 error(s)\n'
module data_ram(

	input wire clk,
	input wire pc_ce,
	input wire mem_ce,
	input wire we,
	input wire[`DataAddrBus] mem_addr,
	input wire[`InstAddrBus] pc_addr,
	input wire[3:0] sel,
	input wire who,
	input wire[`DataBus] data_i,
	output reg[`DataBus] data_o,
	output reg[31: 0] inst
	
);
	
	reg[31: 0] data_mem[0: 100000];
	
		
	initial begin
		$readmemh ( "a.S", data_mem);
	end
	

	always @ (*) begin
		if (pc_ce == `ChipDisable || who == 1'b1) begin
			inst <= `ZeroWord;
		end else begin
			inst <= {
				data_mem[pc_addr[31:2]][7:0],
				data_mem[pc_addr[31:2]][15:8],
				data_mem[pc_addr[31:2]][23:16],
				data_mem[pc_addr[31:2]][31:24]
			};
		end
	end
	

	always @ (posedge clk) begin
		if (mem_ce == `ChipDisable || who == 1'b0) begin

		end else if(we == `WriteEnable) begin
			if (sel[3] == 1'b1) begin

				data_mem[mem_addr[31: 2]][7: 0] <= data_i[7: 0];

		    end
			if (sel[2] == 1'b1) begin

				data_mem[mem_addr[31: 2]][15: 8] <= data_i[15: 8];

		    end
			if (sel[1] == 1'b1) begin

				data_mem[mem_addr[31: 2]][23: 16] <= data_i[23: 16];

		    end
			if (sel[0] == 1'b1) begin

				data_mem[mem_addr[31: 2]][31: 24] <= data_i[31: 24];


if (mem_addr[31: 2] == 7'b1000001) begin
	$display("%c", data_i[31: 24]);
end
				if (mem_addr[31: 2] == 7'b1000010 && data_i[31: 24] == 8'b11111111) begin
					$finish;
				end
		    end
		end
	end
	

	always @ (*) begin
		if (mem_ce == `ChipDisable || who == 1'b0) begin
			data_o <= `ZeroWord;
		end else if(we == `WriteDisable) begin

			data_o <= data_mem[mem_addr[31: 2]];
		end else begin
			data_o <= `ZeroWord;
		end
	end		

endmodule
module data_ram(

	input wire clk,
	input wire pc_ce,
	input wire mem_ce,
	input wire we,
	input wire[`DataAddrBus] mem_addr,
	input wire[`InstAddrBus] pc_addr,
	input wire[3:0] sel,
	input wire who,
	input wire[`DataBus] data_i,
	output reg[`DataBus] data_o,
	output reg[31: 0] inst
	
);

	
	reg[31: 0] data_mem[0: 100000];
	
		
	initial begin
		$readmemh ( "a.S", data_mem);
	end
	

	always @ (*) begin
		if (pc_ce == `ChipDisable || who == 1'b1) begin
			inst <= `ZeroWord;
		end else begin
			inst <= {
				data_mem[pc_addr[31:2]][7:0],
				data_mem[pc_addr[31:2]][15:8],
				data_mem[pc_addr[31:2]][23:16],
				data_mem[pc_addr[31:2]][31:24]
			};
		end
	end
	

	always @ (posedge clk) begin
		if (mem_ce == `ChipDisable || who == 1'b0) begin

		end else if(we == `WriteEnable) begin
			if (sel[3] == 1'b1) begin

				data_mem[mem_addr[31: 2]][7: 0] <= data_i[7: 0];

		    end
			if (sel[2] == 1'b1) begin

				data_mem[mem_addr[31: 2]][15: 8] <= data_i[15: 8];

		    end
			if (sel[1] == 1'b1) begin

				data_mem[mem_addr[31: 2]][23: 16] <= data_i[23: 16];

		    end
			if (sel[0] == 1'b1) begin

				data_mem[mem_addr[31: 2]][31: 24] <= data_i[31: 24];


if (mem_addr[31: 2] == 7'b1000001) begin
	$display("%c", data_i[31: 24]);
end
				if (mem_addr[31: 2] == 7'b1000010 && data_i[31: 24] == 8'b11111111) begin
					$finish;
				end
		    end
		end
	end
	

	always @ (*) begin
		if (mem_ce == `ChipDisable || who == 1'b0) begin
			data_o <= `ZeroWord;
		end else if(we == `WriteDisable) begin

			data_o <= data_mem[mem_addr[31: 2]];
		end else begin
			data_o <= `ZeroWord;
		end
	end		

endmodule