data/full_repos/permissive/120518070/main/source/tb_sarr.sv
 line:43: before: "+"
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:15: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:17: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:34: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:41: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:48: syntax error, unexpected \'@\'\n  @(negedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:52: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:57: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:62: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:69: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:75: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:79: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:84: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:89: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:93: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_sarr.sv:98: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: Exiting due to 13 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sarr();
	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg [7:0] tb_waddr_i;
	reg [7:0] tb_wdata_i;
	reg [7:0] tb_raddr_i;
	reg tb_swap_i;
	reg tb_renable_i;
	reg tb_wenable_i;
	reg [7:0] tb_rdata_o;


	sarr DUT_SARR (.clk(tb_clk),.waddr_i(tb_waddr_i),.wdata_i(tb_wdata_i),.swap_i(tb_swap_i),.wenable_i(tb_wenable_i),.renable_i(tb_renable_i),.raddr_i(tb_raddr_i),.rdata_o(tb_rdata_o));

	reg [8:0] tb_init;
initial
begin
	@(negedge tb_clk);

	tb_wenable_i = 0;
	tb_renable_i = 0;
	tb_swap_i = 0;
	tb_wdata_i = 0;
	tb_raddr_i = 0;
	@(negedge tb_clk);

	for( tb_init = 0; tb_init < 256 ;  tb_init++)
        begin
		tb_wenable_i = 1;
		tb_waddr_i = tb_init;
		tb_wdata_i = tb_init;
		@(negedge tb_clk);
	end
	@(negedge tb_clk);
	tb_wenable_i = 0;
	@(negedge tb_clk);

	tb_renable_i = 1;
	tb_raddr_i = 222;
	$info ("Readiging 222");
	@(negedge tb_clk);

	tb_renable_i = 1;
	tb_raddr_i = 22;
	$info ("Readiging 22");
	@(negedge tb_clk);

	tb_swap_i = 1;
	tb_renable_i = 0;
	tb_raddr_i = 254;
	tb_waddr_i = 252;
	$info ("Swapping 254 and 252");
	@(negedge tb_clk);

	tb_swap_i = 0;
	tb_renable_i = 1;
	tb_raddr_i = 254;
	$info ("Reading 254");
	@(negedge tb_clk);

	tb_raddr_i = 252;
	$info("READING 252");
	@(negedge tb_clk);

	tb_renable_i = 0;
	tb_raddr_i = 222;
	$info("DOING NOTHING");
	@(negedge tb_clk);
	tb_wenable_i = 1;
	tb_waddr_i = 255;
	tb_wdata_i = 0;
	$info("WRITING on location 255 value of 0");
	@(negedge tb_clk);
	tb_waddr_i = 252;
	tb_wdata_i = 69;
	$info("WRITING on location 252 value of 69");
	@(negedge tb_clk);
	tb_wenable_i = 0;
	tb_renable_i = 1;
	tb_raddr_i = 252;
	$info("DOUBLE Checking the location of 252 was written as 69");
	@(negedge tb_clk);
	tb_renable_i = 0;
end
endmodule
module tb_sarr();

	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg [7:0] tb_waddr_i;
	reg [7:0] tb_wdata_i;
	reg [7:0] tb_raddr_i;
	reg tb_swap_i;
	reg tb_renable_i;
	reg tb_wenable_i;
	reg [7:0] tb_rdata_o;


	sarr DUT_SARR (.clk(tb_clk),.waddr_i(tb_waddr_i),.wdata_i(tb_wdata_i),.swap_i(tb_swap_i),.wenable_i(tb_wenable_i),.renable_i(tb_renable_i),.raddr_i(tb_raddr_i),.rdata_o(tb_rdata_o));

	reg [8:0] tb_init;
initial
begin
	@(negedge tb_clk);

	tb_wenable_i = 0;
	tb_renable_i = 0;
	tb_swap_i = 0;
	tb_wdata_i = 0;
	tb_raddr_i = 0;
	@(negedge tb_clk);

	for( tb_init = 0; tb_init < 256 ;  tb_init++)
        begin
		tb_wenable_i = 1;
		tb_waddr_i = tb_init;
		tb_wdata_i = tb_init;
		@(negedge tb_clk);
	end
	@(negedge tb_clk);
	tb_wenable_i = 0;
	@(negedge tb_clk);

	tb_renable_i = 1;
	tb_raddr_i = 222;
	$info ("Readiging 222");
	@(negedge tb_clk);

	tb_renable_i = 1;
	tb_raddr_i = 22;
	$info ("Readiging 22");
	@(negedge tb_clk);

	tb_swap_i = 1;
	tb_renable_i = 0;
	tb_raddr_i = 254;
	tb_waddr_i = 252;
	$info ("Swapping 254 and 252");
	@(negedge tb_clk);

	tb_swap_i = 0;
	tb_renable_i = 1;
	tb_raddr_i = 254;
	$info ("Reading 254");
	@(negedge tb_clk);

	tb_raddr_i = 252;
	$info("READING 252");
	@(negedge tb_clk);

	tb_renable_i = 0;
	tb_raddr_i = 222;
	$info("DOING NOTHING");
	@(negedge tb_clk);
	tb_wenable_i = 1;
	tb_waddr_i = 255;
	tb_wdata_i = 0;
	$info("WRITING on location 255 value of 0");
	@(negedge tb_clk);
	tb_waddr_i = 252;
	tb_wdata_i = 69;
	$info("WRITING on location 252 value of 69");
	@(negedge tb_clk);
	tb_wenable_i = 0;
	tb_renable_i = 1;
	tb_raddr_i = 252;
	$info("DOUBLE Checking the location of 252 was written as 69");
	@(negedge tb_clk);
	tb_renable_i = 0;
end
endmodule