data/full_repos/permissive/141038711/hdl/apb_decode.v
1: b'%Warning-WIDTH: data/full_repos/permissive/141038711/hdl/apb_decode.v:87: Operator SHIFTL expects 3 bits on the LHS, but LHS\'s VARREF \'s_psel\' generates 1 bits.\n                                                                        : ... In instance apb_decode\n            m_psel = s_psel<<(PORTS-1);\n                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/141038711/hdl/apb_decode.v:92: Operator SHIFTL expects 3 bits on the LHS, but LHS\'s VARREF \'s_psel\' generates 1 bits.\n                                                                        : ... In instance apb_decode\n         m_psel = s_psel<<select_bits;      \n                        ^~\n%Error: Exiting due to 2 warning(s)\n'
module apb_decode
#(parameter PORTS      = 3,
            BOTREGION  = 1024,
            REGION     = 3072,
            TOP_DEFAULT   = 0
 )
(

   input      [31:0] s_paddr,
   input             s_pwrite,
   input             s_psel,
   input             s_penable,
   input      [31:0] s_pwdata,
   output     [31:0] s_prdata,
   output            s_pready,
   output            s_pslverr,
   

   output          [31:0] m_paddr,
   output                 m_pwrite,
   output reg [PORTS-1:0] m_psel,
   output                 m_penable,
   output          [31:0] m_pwdata,
   input   [PORTS*32-1:0] m_prdata,
   input      [PORTS-1:0] m_pready,
   input      [PORTS-1:0] m_pslverr
);

localparam BOT    = BOTREGION,
           TOP    = BOTREGION+REGION*PORTS;


localparam SELBITS = PORTS<=2    ? 1 :
                     PORTS<=4    ? 2 :
                     PORTS<=8    ? 3 :
                     PORTS<=16   ? 4 : 
                     PORTS<=32   ? 5 :
                     PORTS<=64   ? 6 :
                     0 ;

wire               select_error;    
reg  [SELBITS-1:0] select_bits;


   assign m_paddr   = s_paddr; 
   assign m_pwrite  = s_pwrite;
   assign m_penable = s_penable;
   assign m_pwdata  = s_pwdata;
   

   always @( * )
   begin : dec
      integer adrs_loop;
      select_bits = 0; 
      for (adrs_loop=BOT+REGION; adrs_loop<TOP; adrs_loop=adrs_loop+REGION)
      begin

         if (s_paddr>=adrs_loop)
            select_bits = select_bits + 1;
      end
   end

   assign select_error = !(s_paddr>=BOT && s_paddr<TOP);
   
   always @( * )
   begin
      if (select_error)
      begin
         if (TOP_DEFAULT)
            m_psel = s_psel<<(PORTS-1);
         else
            m_psel = {PORTS{1'b0}};         
      end
      else
         m_psel = s_psel<<select_bits;      
   end
    



   

   assign s_prdata  = m_prdata[select_bits*32 +: 32];
   

   assign s_pslverr = (m_pslverr[select_bits] | (select_error & ~TOP_DEFAULT));
   

   assign s_pready  = (m_pready[select_bits] | (select_error & ~TOP_DEFAULT));




endmodule
module apb_decode
#(parameter PORTS      = 3,
            BOTREGION  = 1024,
            REGION     = 3072,
            TOP_DEFAULT   = 0
 )
(

   input      [31:0] s_paddr,
   input             s_pwrite,
   input             s_psel,
   input             s_penable,
   input      [31:0] s_pwdata,
   output     [31:0] s_prdata,
   output            s_pready,
   output            s_pslverr,
   

   output          [31:0] m_paddr,
   output                 m_pwrite,
   output reg [PORTS-1:0] m_psel,
   output                 m_penable,
   output          [31:0] m_pwdata,
   input   [PORTS*32-1:0] m_prdata,
   input      [PORTS-1:0] m_pready,
   input      [PORTS-1:0] m_pslverr
);


localparam BOT    = BOTREGION,
           TOP    = BOTREGION+REGION*PORTS;


localparam SELBITS = PORTS<=2    ? 1 :
                     PORTS<=4    ? 2 :
                     PORTS<=8    ? 3 :
                     PORTS<=16   ? 4 : 
                     PORTS<=32   ? 5 :
                     PORTS<=64   ? 6 :
                     0 ;

wire               select_error;    
reg  [SELBITS-1:0] select_bits;


   assign m_paddr   = s_paddr; 
   assign m_pwrite  = s_pwrite;
   assign m_penable = s_penable;
   assign m_pwdata  = s_pwdata;
   

   always @( * )
   begin : dec
      integer adrs_loop;
      select_bits = 0; 
      for (adrs_loop=BOT+REGION; adrs_loop<TOP; adrs_loop=adrs_loop+REGION)
      begin

         if (s_paddr>=adrs_loop)
            select_bits = select_bits + 1;
      end
   end

   assign select_error = !(s_paddr>=BOT && s_paddr<TOP);
   
   always @( * )
   begin
      if (select_error)
      begin
         if (TOP_DEFAULT)
            m_psel = s_psel<<(PORTS-1);
         else
            m_psel = {PORTS{1'b0}};         
      end
      else
         m_psel = s_psel<<select_bits;      
   end
    



   

   assign s_prdata  = m_prdata[select_bits*32 +: 32];
   

   assign s_pslverr = (m_pslverr[select_bits] | (select_error & ~TOP_DEFAULT));
   

   assign s_pready  = (m_pready[select_bits] | (select_error & ~TOP_DEFAULT));




endmodule