data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:94: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:97: Unsupported: Ignoring delay on this delayed statement.\n            #(number_of_wait_cycles*PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:101: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:103: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:105: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:108: Unsupported: Ignoring delay on this delayed statement.\n            #(number_of_wait_cycles*PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:115: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:119: Unsupported: Ignoring delay on this delayed statement.\n                #(number_of_wait_cycles*PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:123: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:125: Unsupported: Ignoring delay on this delayed statement.\n                    #(PERIOD);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:127: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:131: Unsupported: Ignoring delay on this delayed statement.\n                #(number_of_wait_cycles*PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:146: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:149: Unsupported: Ignoring delay on this delayed statement.\n            #(number_of_wait_cycles*PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:153: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:155: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:157: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:160: Unsupported: Ignoring delay on this delayed statement.\n            #(number_of_wait_cycles*PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:167: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:171: Unsupported: Ignoring delay on this delayed statement.\n                #(number_of_wait_cycles*PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:175: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:177: Unsupported: Ignoring delay on this delayed statement.\n                    #(PERIOD);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:179: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:183: Unsupported: Ignoring delay on this delayed statement.\n                #(number_of_wait_cycles*PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:200: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:204: Unsupported: Ignoring delay on this delayed statement.\n            #(number_of_wait_cycles*PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:208: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:210: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:212: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:216: Unsupported: Ignoring delay on this delayed statement.\n            #(number_of_wait_cycles*PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:223: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:228: Unsupported: Ignoring delay on this delayed statement.\n                #((number_of_wait_cycles+1)*PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:232: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:234: Unsupported: Ignoring delay on this delayed statement.\n                    #(PERIOD);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:236: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:241: Unsupported: Ignoring delay on this delayed statement.\n                #((number_of_wait_cycles+1)*PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:258: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:262: Unsupported: Ignoring delay on this delayed statement.\n                #(number_of_wait_cycles*PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:266: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:268: Unsupported: Ignoring delay on this delayed statement.\n                    #(PERIOD);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:270: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:274: Unsupported: Ignoring delay on this delayed statement.\n                #(number_of_wait_cycles*PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:280: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:285: Unsupported: Ignoring delay on this delayed statement.\n                #((number_of_wait_cycles+1)*PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:304: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:308: Unsupported: Ignoring delay on this delayed statement.\n            #(number_of_wait_cycles*PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:312: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:314: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:316: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:320: Unsupported: Ignoring delay on this delayed statement.\n            #(number_of_wait_cycles*PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:329: Unsupported: Ignoring delay on this delayed statement.\n                        #(PERIOD);\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:334: Unsupported: Ignoring delay on this delayed statement.\n                        #((number_of_wait_cycles+1)*PERIOD);\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:338: Unsupported: Ignoring delay on this delayed statement.\n                        #(PERIOD);\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:340: Unsupported: Ignoring delay on this delayed statement.\n                            #(PERIOD);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:342: Unsupported: Ignoring delay on this delayed statement.\n                        #(PERIOD);\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:347: Unsupported: Ignoring delay on this delayed statement.\n                        #((number_of_wait_cycles+1)*PERIOD);\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:354: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:358: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:360: Unsupported: Ignoring delay on this delayed statement.\n                #((number_of_wait_cycles+1)*PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:364: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:366: Unsupported: Ignoring delay on this delayed statement.\n                    #(PERIOD);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:368: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:372: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:374: Unsupported: Ignoring delay on this delayed statement.\n                #((number_of_wait_cycles+1)*PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:417: Unsupported: Ignoring delay on this delayed statement.\n    #(PERIOD*2);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:419: Unsupported: Ignoring delay on this delayed statement.\n    #(PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:420: Unsupported: Ignoring delay on this delayed statement.\n    #(tb_delay);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:423: Unsupported: Ignoring delay on this delayed statement.\n    #(PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:452: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:507: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:512: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:514: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:516: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:518: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:522: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:523: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:528: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:530: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:532: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:534: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:538: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:540: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:545: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:547: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:549: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:551: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:555: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:557: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:562: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:564: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:566: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:568: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:572: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:574: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:579: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:581: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:583: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:585: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:589: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:591: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:596: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:598: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:600: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:602: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:606: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:608: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:613: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:615: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:617: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:619: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:623: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:625: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:628: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:630: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:638: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:640: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:647: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:649: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:656: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:658: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:665: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:668: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:675: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:677: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:679: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:681: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:685: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:686: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:691: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:693: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:695: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:697: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:701: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:703: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:708: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:710: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:712: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:714: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:718: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:720: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:725: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:727: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:729: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:731: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:735: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:737: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:742: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:744: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:746: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:748: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:752: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:754: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:759: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:761: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:763: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:765: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:769: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:771: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:776: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:778: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:780: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:782: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:786: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:788: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:791: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:793: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:801: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:803: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:810: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:812: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:819: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:821: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:828: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:831: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:839: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:841: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:843: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:845: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:849: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:850: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:855: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:857: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:859: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:861: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:865: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:867: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:872: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:874: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:876: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:878: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:882: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:884: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:889: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:891: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:893: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:895: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:899: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:901: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:906: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:908: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:910: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:912: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:916: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:918: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:923: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:925: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:927: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:929: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:933: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:935: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:940: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:942: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:944: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:946: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:950: Unsupported: Ignoring delay on this delayed statement.\n        #(number_of_wait_cycles*PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:952: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:955: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:957: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:965: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:967: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:974: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:976: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:983: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:986: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:991: Unsupported: Ignoring delay on this delayed statement.\n    #(PERIOD);\n    ^\n%Error: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:996: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/206746055/hw_project/verilog_source/ae_mode_stream/tb_friet_ae_32_bits.v:997: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, tb_friet_ae_32_bits);\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 226 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_friet_ae_32_bits();

parameter PERIOD = 1000;
parameter maximum_number_of_tests = 100;
parameter maximum_line_length = 10000;
parameter test_memory_file_friet_ae_initialization = "../data_tests/friet_ae.dat";
parameter test_combinational_rounds = 1;
parameter array_max_size = 1024;

reg test_arstn;
reg [31:0] test_din;
reg test_din_valid;
wire test_din_ready;
wire [31:0] test_dout;
wire test_dout_valid;
reg test_dout_ready;

reg [array_max_size-1:0] test_key;
reg [31:0] test_key_size;
reg [array_max_size-1:0] test_nonce;
reg [31:0] test_nonce_size;
reg [array_max_size-1:0] test_key_tag;
reg [31:0] test_key_tag_size;
reg [array_max_size-1:0] true_key_tag;
reg [31:0] true_key_tag_size;
reg [array_max_size-1:0] test_ad;
reg [31:0] test_ad_size;
reg [array_max_size-1:0] test_pt;
reg [31:0] test_pt_size;
reg [array_max_size-1:0] test_ct;
reg [31:0] test_ct_size;
reg [array_max_size-1:0] test_tag;
reg [31:0] test_tag_size;
reg [array_max_size-1:0] true_pt;
reg [31:0] true_pt_size;
reg [array_max_size-1:0] true_ct;
reg [31:0] true_ct_size;
reg [array_max_size-1:0] true_tag;
reg [31:0] true_tag_size;
reg [31:0] verification_tag;

reg [383:0] true_debug_state;


reg clk;
reg test_error = 1'b0;
reg test_verification = 1'b0;

localparam tb_delay = PERIOD/2;
localparam tb_delay_read = 3*PERIOD/4;
localparam number_of_wait_cycles = 0;

initial begin : clock_generator
    clk <= 1'b1;
    forever begin
        #(PERIOD/2);
        clk <= ~clk;
    end
end

friet_ae_32_bits
#(
    .COMBINATIONAL_ROUNDS(test_combinational_rounds)
)
test (
    .clk(clk),
    .arstn(test_arstn),
    .din(test_din),
    .din_valid(test_din_valid),
    .din_ready(test_din_ready),
    .dout(test_dout),
    .dout_valid(test_dout_valid),
    .dout_ready(test_dout_ready)
);

task send_key_or_nonce;
    input [array_max_size-1:0] send_array;
    input [31:0] send_array_size;
    integer i;
    begin
        i = 0;
        if(test_din_ready == 1'b1) begin
            test_din = send_array_size;
            test_din_valid = 1'b1;
            #(PERIOD);
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end else begin
            test_din = send_array_size;
            test_din_valid = 1'b1;
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end
        i = 0;
        while(i < send_array_size*8) begin
            if(test_din_ready == 1'b1) begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end else begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                while(test_din_ready != 1'b1) begin
                    #(PERIOD);
                end
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end
        end
    end
endtask

task send_ad;
    input [array_max_size-1:0] send_array;
    input [31:0] send_array_size;
    integer i;
    begin
        i = 0;
        if(test_din_ready == 1'b1) begin
            test_din = send_array_size;
            test_din_valid = 1'b1;
            #(PERIOD);
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end else begin
            test_din = send_array_size;
            test_din_valid = 1'b1;
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end
        i = 0;
        while(i < send_array_size*8) begin
            if(test_din_ready == 1'b1) begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end else begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                while(test_din_ready != 1'b1) begin
                    #(PERIOD);
                end
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end
        end
    end
endtask

task send_pt_receive_ct;
    input [array_max_size-1:0] send_array;
    input [31:0] send_array_size;
    output [array_max_size-1:0] receive_array;
    integer i;
    begin
        i = 0;
        receive_array = {array_max_size{1'b0}};
        if(test_din_ready == 1'b1) begin
            test_din = send_array_size[i +:32];
            test_din_valid = 1'b1;
            #(PERIOD);
            i = i + 32;
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end else begin
            test_din = send_array_size[i +:32];
            test_din_valid = 1'b1;
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
            i = i + 32;
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end
        i = 0;
        while(i < send_array_size*8) begin
            if(test_din_ready == 1'b1) begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                receive_array[i +:32] = test_dout;
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #((number_of_wait_cycles+1)*PERIOD);
            end else begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                while(test_din_ready != 1'b1) begin
                    #(PERIOD);
                end
                #(PERIOD);
                receive_array[i +:32] = test_dout;
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #((number_of_wait_cycles+1)*PERIOD);
            end
        end
    end
endtask

task receive_tag;
    input [31:0] receive_array_size;
    output [array_max_size-1:0] receive_array;
    integer i;
    begin
        i = 0;
        receive_array = {array_max_size{1'b0}};
        while(i < 32) begin
            if(test_din_ready == 1'b1) begin
                test_din = receive_array_size[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end else begin
                test_din = receive_array_size[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                while(test_din_ready != 1'b1) begin
                    #(PERIOD);
                end
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end
        end
        i = 0;
        while(i < receive_array_size*8) begin
            test_dout_ready = 1'b1;
            #(PERIOD);
            if(test_dout_valid == 1'b1) begin
                receive_array[i +:32] = test_dout;
                i = i + 32;
                test_dout_ready = 1'b0;
                #((number_of_wait_cycles+1)*PERIOD);
            end
        end
        test_dout_ready = 1'b0;
    end
endtask

task send_verify_tag;
    input [array_max_size-1:0] send_array;
    input [31:0] send_array_size;
    output [31:0] receive_array;
    integer i;
    begin
        i = 0;
        receive_array = {array_max_size{1'b0}};
        test_dout_ready = 1'b1;
        if(test_din_ready == 1'b1) begin
            test_din = send_array_size[i +:32];
            test_din_valid = 1'b1;
            #(PERIOD);
            i = i + 32;
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end else begin
            test_din = send_array_size[i +:32];
            test_din_valid = 1'b1;
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
            i = i + 32;
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end
        i = 0;
        if(send_array_size > 0) begin
            if(send_array_size > 4) begin
                while(i < ((send_array_size-4)*8)) begin
                    if(test_din_ready == 1'b1) begin
                        test_din = send_array[i +:32];
                        test_din_valid = 1'b1;
                        #(PERIOD);
                        receive_array = test_dout;
                        i = i + 32;
                        test_din_valid = 1'b0;
                        test_din = 32'b0;
                        #((number_of_wait_cycles+1)*PERIOD);
                    end else begin
                        test_din = send_array[i +:32];
                        test_din_valid = 1'b1;
                        #(PERIOD);
                        while(test_din_ready != 1'b1) begin
                            #(PERIOD);
                        end
                        #(PERIOD);
                        receive_array = test_dout;
                        i = i + 32;
                        test_din_valid = 1'b0;
                        test_din = 32'b0;
                        #((number_of_wait_cycles+1)*PERIOD);
                    end
                end
            end
            if(test_din_ready == 1'b1) begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                receive_array = test_dout;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(PERIOD);
                receive_array = test_dout;
                #((number_of_wait_cycles+1)*PERIOD);
            end else begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                while(test_din_ready != 1'b1) begin
                    #(PERIOD);
                end
                #(PERIOD);
                receive_array = test_dout;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(PERIOD);
                receive_array = test_dout;
                #((number_of_wait_cycles+1)*PERIOD);
            end
        end
        test_dout_ready = 1'b0;
    end
endtask

integer ram_file;
integer number_of_tests;
integer test_iterator;
integer status_ram_file;
integer load_iterator;
reg [7:0] test_read_buffer;
initial begin
    test_arstn <= 1'b0;
    test_din <= 32'b0;
    test_din_valid <= 1'b0;
    test_dout_ready <= 1'b0;
    test_key <= {array_max_size{1'b0}};
    test_key_size <= 32'b0;
    test_nonce <= {array_max_size{1'b0}};
    test_nonce_size <= 32'b0;
    test_key_tag <= {array_max_size{1'b0}};
    test_key_tag_size <= 32'b0;
    test_ad <= {array_max_size{1'b0}};
    test_ad_size <= 32'b0;
    test_pt <= {array_max_size{1'b0}};
    test_pt_size <= 32'b0;
    test_ct <= {array_max_size{1'b0}};
    test_ct_size <= 32'b0;
    test_tag <= {array_max_size{1'b0}};
    test_tag_size <= 32'b0;
    true_key_tag <= {array_max_size{1'b0}};
    true_key_tag_size <= 32'b0;
    true_pt <= {array_max_size{1'b0}};
    true_pt_size <= 32'b0;
    true_ct <= {array_max_size{1'b0}};
    true_ct_size <= 32'b0;
    true_tag <= {array_max_size{1'b0}};
    true_tag_size <= 32'b0;
    verification_tag <= 32'b0;
    test_error <= 1'b0;
    test_verification <= 1'b0;
    #(PERIOD*2);
    test_arstn <= 1'b1;
    #(PERIOD);
    #(tb_delay);
    ram_file = $fopen(test_memory_file_friet_ae_initialization, "r");
    status_ram_file = $fscanf(ram_file, "%d", number_of_tests);
    #(PERIOD);
    if((number_of_tests > maximum_number_of_tests) && (maximum_number_of_tests != 0)) begin
        number_of_tests = maximum_number_of_tests;
    end
    for (test_iterator = 1; test_iterator < number_of_tests; test_iterator = test_iterator + 1) begin
        test_error <= 1'b0;
        test_key <= {array_max_size{1'b0}};
        test_key_size <= 32'b0;
        test_nonce <= {array_max_size{1'b0}};
        test_nonce_size <= 32'b0;
        test_key_tag <= {array_max_size{1'b0}};
        test_key_tag_size <= 32'b0;
        test_ad <= {array_max_size{1'b0}};
        test_ad_size <= 32'b0;
        test_pt <= {array_max_size{1'b0}};
        test_pt_size <= 32'b0;
        test_ct <= {array_max_size{1'b0}};
        test_ct_size <= 32'b0;
        test_tag <= {array_max_size{1'b0}};
        test_tag_size <= 32'b0;
        true_key_tag <= {array_max_size{1'b0}};
        true_key_tag_size <= 32'b0;
        true_pt <= {array_max_size{1'b0}};
        true_pt_size <= 32'b0;
        true_ct <= {array_max_size{1'b0}};
        true_ct_size <= 32'b0;
        true_tag <= {array_max_size{1'b0}};
        true_tag_size <= 32'b0;
        verification_tag <= 32'b0;
        #(PERIOD);
        status_ram_file = $fscanf(ram_file, "%d", test_key_size);
        load_iterator = 0;
        while (load_iterator < test_key_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            test_key[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", test_nonce_size);
        load_iterator = 0;
        while (load_iterator < test_nonce_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            test_nonce[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", test_ad_size);
        load_iterator = 0;
        while (load_iterator < test_ad_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            test_ad[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", true_pt_size);
        test_pt_size = true_pt_size;
        load_iterator = 0;
        while (load_iterator < true_pt_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            true_pt[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", true_key_tag_size);
        test_key_tag_size = true_key_tag_size;
        load_iterator = 0;
        while (load_iterator < true_key_tag_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            true_key_tag[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", true_ct_size);
        test_ct_size = true_ct_size;
        load_iterator = 0;
        while (load_iterator < true_ct_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            true_ct[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", true_tag_size);
        test_tag_size = true_tag_size;
        load_iterator = 0;
        while (load_iterator < true_tag_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            true_tag[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%b", true_debug_state);
        #(PERIOD);

        test_din = 32'h00;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_key, test_key_size);
        #(PERIOD);
        
        test_din = 32'h02;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_nonce, test_nonce_size);
        #(PERIOD);
        
        test_din = 32'h04;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        receive_tag(test_key_tag_size, test_key_tag);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_ad(test_ad, test_ad_size);
        #(PERIOD);
        
        test_din = 32'h02;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_pt_receive_ct(true_pt, true_pt_size, test_ct);
        #(PERIOD);
        
        test_din = 32'h04;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        receive_tag(test_tag_size, test_tag);
        #(PERIOD);
        
        while(test_din_ready != 1'b1) begin
            #(PERIOD);
        end
        #(PERIOD);
        test_verification <= 1'b1;
        if (true_key_tag == test_key_tag) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed key tags do not match expected ones");
        end
        #(PERIOD);
        test_error <= 1'b0;
        #(PERIOD);
        if (true_ct == test_ct) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed ciphertext do not match expected ones");
        end
        #(PERIOD);
        test_error <= 1'b0;
        #(PERIOD);
        if (true_tag != test_tag) begin
            test_error <= 1'b1;
            $display("Computed tag do not match expected ones");
        end else begin
            test_error <= 1'b0;
        end
        #(PERIOD);
        test_error <= 1'b0;
        #(PERIOD);
        if (true_debug_state != test.permutation_state) begin
            test_error <= 1'b1;
            $display("Final state do not match expected one");
        end else begin
            test_error <= 1'b0;
        end
        #(PERIOD);
        test_verification <= 1'b0;
        test_error <= 1'b0;
        #(PERIOD);

        test_key_tag <= {array_max_size{1'b0}};
        
        test_din = 32'h00;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_key, test_key_size);
        #(PERIOD);
        
        test_din = 32'h02;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_nonce, test_nonce_size);
        #(PERIOD);
        
        test_din = 32'h04;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        receive_tag(test_key_tag_size, test_key_tag);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_ad(test_ad, test_ad_size);
        #(PERIOD);
        
        test_din = 32'h03;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_pt_receive_ct(true_ct, true_ct_size, test_pt);
        #(PERIOD);
        
        test_din = 32'h05;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_verify_tag(true_tag, true_tag_size, verification_tag);
        #(PERIOD);
        
        while(test_din_ready != 1'b1) begin
            #(PERIOD);
        end
        #(PERIOD);
        test_verification <= 1'b1;
        if (true_key_tag == test_key_tag) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed key tags do not match expected ones");
        end
        #PERIOD;
        test_error <= 1'b0;
        #PERIOD;
        if (true_pt == test_pt) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed plaintext do not match expected ones");
        end
        #PERIOD;
        test_error <= 1'b0;
        #PERIOD;
        if ((true_tag_size > 0) && (verification_tag != 32'b0)) begin
            test_error <= 1'b1;
            $display("Tags do not match expected ones");
        end else begin
            test_error <= 1'b0;
        end
        #PERIOD;
        test_error <= 1'b0;
        #PERIOD;
        if (true_debug_state != test.permutation_state) begin
            test_error <= 1'b1;
            $display("Final state do not match expected one");
        end else begin
            test_error <= 1'b0;
        end
        #PERIOD;
        test_verification <= 1'b0;
        test_error <= 1'b0;
        #PERIOD;

        test_key_tag <= {array_max_size{1'b0}};
        true_tag[0] = true_tag[0] ^ 1'b1;
        
        test_din = 32'h00;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_key, test_key_size);
        #(PERIOD);
        
        test_din = 32'h02;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_nonce, test_nonce_size);
        #(PERIOD);
        
        test_din = 32'h04;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 8'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        receive_tag(test_key_tag_size, test_key_tag);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_ad(test_ad, test_ad_size);
        #(PERIOD);
        
        test_din = 32'h03;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_pt_receive_ct(true_ct, true_ct_size, test_pt);
        #(PERIOD);
        
        test_din = 32'h05;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_verify_tag(true_tag, true_tag_size, verification_tag);
        #(PERIOD);
        
        while(test_din_ready != 1'b1) begin
            #(PERIOD);
        end
        #(PERIOD);
        test_verification <= 1'b1;
        if (true_key_tag == test_key_tag) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed key tags do not match expected ones");
        end
        #PERIOD;
        test_error <= 1'b0;
        #PERIOD;
        if (true_pt == test_pt) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed plaintext do not match expected ones");
        end
        #PERIOD;
        test_error <= 1'b0;
        #PERIOD;
        if ((true_tag_size > 0) && (verification_tag == 32'b0)) begin
            test_error <= 1'b1;
            $display("Tags are matching when they should not");
        end else begin
            test_error <= 1'b0;
        end
        #PERIOD;
        test_verification <= 1'b0;
        test_error <= 1'b0;
        #PERIOD;
    end
    $fclose(ram_file);
    $display("End of the test.");
    disable clock_generator;
    #(PERIOD);
end

initial
begin
    $dumpfile("dump.vcd");
    $dumpvars(1, tb_friet_ae_32_bits);
end

endmodule
module tb_friet_ae_32_bits();


parameter PERIOD = 1000;
parameter maximum_number_of_tests = 100;
parameter maximum_line_length = 10000;
parameter test_memory_file_friet_ae_initialization = "../data_tests/friet_ae.dat";
parameter test_combinational_rounds = 1;
parameter array_max_size = 1024;

reg test_arstn;
reg [31:0] test_din;
reg test_din_valid;
wire test_din_ready;
wire [31:0] test_dout;
wire test_dout_valid;
reg test_dout_ready;

reg [array_max_size-1:0] test_key;
reg [31:0] test_key_size;
reg [array_max_size-1:0] test_nonce;
reg [31:0] test_nonce_size;
reg [array_max_size-1:0] test_key_tag;
reg [31:0] test_key_tag_size;
reg [array_max_size-1:0] true_key_tag;
reg [31:0] true_key_tag_size;
reg [array_max_size-1:0] test_ad;
reg [31:0] test_ad_size;
reg [array_max_size-1:0] test_pt;
reg [31:0] test_pt_size;
reg [array_max_size-1:0] test_ct;
reg [31:0] test_ct_size;
reg [array_max_size-1:0] test_tag;
reg [31:0] test_tag_size;
reg [array_max_size-1:0] true_pt;
reg [31:0] true_pt_size;
reg [array_max_size-1:0] true_ct;
reg [31:0] true_ct_size;
reg [array_max_size-1:0] true_tag;
reg [31:0] true_tag_size;
reg [31:0] verification_tag;

reg [383:0] true_debug_state;


reg clk;
reg test_error = 1'b0;
reg test_verification = 1'b0;

localparam tb_delay = PERIOD/2;
localparam tb_delay_read = 3*PERIOD/4;
localparam number_of_wait_cycles = 0;

initial begin : clock_generator
    clk <= 1'b1;
    forever begin
        #(PERIOD/2);
        clk <= ~clk;
    end
end

friet_ae_32_bits
#(
    .COMBINATIONAL_ROUNDS(test_combinational_rounds)
)
test (
    .clk(clk),
    .arstn(test_arstn),
    .din(test_din),
    .din_valid(test_din_valid),
    .din_ready(test_din_ready),
    .dout(test_dout),
    .dout_valid(test_dout_valid),
    .dout_ready(test_dout_ready)
);

task send_key_or_nonce;
    input [array_max_size-1:0] send_array;
    input [31:0] send_array_size;
    integer i;
    begin
        i = 0;
        if(test_din_ready == 1'b1) begin
            test_din = send_array_size;
            test_din_valid = 1'b1;
            #(PERIOD);
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end else begin
            test_din = send_array_size;
            test_din_valid = 1'b1;
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end
        i = 0;
        while(i < send_array_size*8) begin
            if(test_din_ready == 1'b1) begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end else begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                while(test_din_ready != 1'b1) begin
                    #(PERIOD);
                end
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end
        end
    end
endtask

task send_ad;
    input [array_max_size-1:0] send_array;
    input [31:0] send_array_size;
    integer i;
    begin
        i = 0;
        if(test_din_ready == 1'b1) begin
            test_din = send_array_size;
            test_din_valid = 1'b1;
            #(PERIOD);
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end else begin
            test_din = send_array_size;
            test_din_valid = 1'b1;
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end
        i = 0;
        while(i < send_array_size*8) begin
            if(test_din_ready == 1'b1) begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end else begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                while(test_din_ready != 1'b1) begin
                    #(PERIOD);
                end
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end
        end
    end
endtask

task send_pt_receive_ct;
    input [array_max_size-1:0] send_array;
    input [31:0] send_array_size;
    output [array_max_size-1:0] receive_array;
    integer i;
    begin
        i = 0;
        receive_array = {array_max_size{1'b0}};
        if(test_din_ready == 1'b1) begin
            test_din = send_array_size[i +:32];
            test_din_valid = 1'b1;
            #(PERIOD);
            i = i + 32;
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end else begin
            test_din = send_array_size[i +:32];
            test_din_valid = 1'b1;
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
            i = i + 32;
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end
        i = 0;
        while(i < send_array_size*8) begin
            if(test_din_ready == 1'b1) begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                receive_array[i +:32] = test_dout;
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #((number_of_wait_cycles+1)*PERIOD);
            end else begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                while(test_din_ready != 1'b1) begin
                    #(PERIOD);
                end
                #(PERIOD);
                receive_array[i +:32] = test_dout;
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #((number_of_wait_cycles+1)*PERIOD);
            end
        end
    end
endtask

task receive_tag;
    input [31:0] receive_array_size;
    output [array_max_size-1:0] receive_array;
    integer i;
    begin
        i = 0;
        receive_array = {array_max_size{1'b0}};
        while(i < 32) begin
            if(test_din_ready == 1'b1) begin
                test_din = receive_array_size[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end else begin
                test_din = receive_array_size[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                while(test_din_ready != 1'b1) begin
                    #(PERIOD);
                end
                #(PERIOD);
                i = i + 32;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(number_of_wait_cycles*PERIOD);
            end
        end
        i = 0;
        while(i < receive_array_size*8) begin
            test_dout_ready = 1'b1;
            #(PERIOD);
            if(test_dout_valid == 1'b1) begin
                receive_array[i +:32] = test_dout;
                i = i + 32;
                test_dout_ready = 1'b0;
                #((number_of_wait_cycles+1)*PERIOD);
            end
        end
        test_dout_ready = 1'b0;
    end
endtask

task send_verify_tag;
    input [array_max_size-1:0] send_array;
    input [31:0] send_array_size;
    output [31:0] receive_array;
    integer i;
    begin
        i = 0;
        receive_array = {array_max_size{1'b0}};
        test_dout_ready = 1'b1;
        if(test_din_ready == 1'b1) begin
            test_din = send_array_size[i +:32];
            test_din_valid = 1'b1;
            #(PERIOD);
            i = i + 32;
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end else begin
            test_din = send_array_size[i +:32];
            test_din_valid = 1'b1;
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
            i = i + 32;
            test_din_valid = 1'b0;
            test_din = 32'b0;
            #(number_of_wait_cycles*PERIOD);
        end
        i = 0;
        if(send_array_size > 0) begin
            if(send_array_size > 4) begin
                while(i < ((send_array_size-4)*8)) begin
                    if(test_din_ready == 1'b1) begin
                        test_din = send_array[i +:32];
                        test_din_valid = 1'b1;
                        #(PERIOD);
                        receive_array = test_dout;
                        i = i + 32;
                        test_din_valid = 1'b0;
                        test_din = 32'b0;
                        #((number_of_wait_cycles+1)*PERIOD);
                    end else begin
                        test_din = send_array[i +:32];
                        test_din_valid = 1'b1;
                        #(PERIOD);
                        while(test_din_ready != 1'b1) begin
                            #(PERIOD);
                        end
                        #(PERIOD);
                        receive_array = test_dout;
                        i = i + 32;
                        test_din_valid = 1'b0;
                        test_din = 32'b0;
                        #((number_of_wait_cycles+1)*PERIOD);
                    end
                end
            end
            if(test_din_ready == 1'b1) begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                receive_array = test_dout;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(PERIOD);
                receive_array = test_dout;
                #((number_of_wait_cycles+1)*PERIOD);
            end else begin
                test_din = send_array[i +:32];
                test_din_valid = 1'b1;
                #(PERIOD);
                while(test_din_ready != 1'b1) begin
                    #(PERIOD);
                end
                #(PERIOD);
                receive_array = test_dout;
                test_din_valid = 1'b0;
                test_din = 32'b0;
                #(PERIOD);
                receive_array = test_dout;
                #((number_of_wait_cycles+1)*PERIOD);
            end
        end
        test_dout_ready = 1'b0;
    end
endtask

integer ram_file;
integer number_of_tests;
integer test_iterator;
integer status_ram_file;
integer load_iterator;
reg [7:0] test_read_buffer;
initial begin
    test_arstn <= 1'b0;
    test_din <= 32'b0;
    test_din_valid <= 1'b0;
    test_dout_ready <= 1'b0;
    test_key <= {array_max_size{1'b0}};
    test_key_size <= 32'b0;
    test_nonce <= {array_max_size{1'b0}};
    test_nonce_size <= 32'b0;
    test_key_tag <= {array_max_size{1'b0}};
    test_key_tag_size <= 32'b0;
    test_ad <= {array_max_size{1'b0}};
    test_ad_size <= 32'b0;
    test_pt <= {array_max_size{1'b0}};
    test_pt_size <= 32'b0;
    test_ct <= {array_max_size{1'b0}};
    test_ct_size <= 32'b0;
    test_tag <= {array_max_size{1'b0}};
    test_tag_size <= 32'b0;
    true_key_tag <= {array_max_size{1'b0}};
    true_key_tag_size <= 32'b0;
    true_pt <= {array_max_size{1'b0}};
    true_pt_size <= 32'b0;
    true_ct <= {array_max_size{1'b0}};
    true_ct_size <= 32'b0;
    true_tag <= {array_max_size{1'b0}};
    true_tag_size <= 32'b0;
    verification_tag <= 32'b0;
    test_error <= 1'b0;
    test_verification <= 1'b0;
    #(PERIOD*2);
    test_arstn <= 1'b1;
    #(PERIOD);
    #(tb_delay);
    ram_file = $fopen(test_memory_file_friet_ae_initialization, "r");
    status_ram_file = $fscanf(ram_file, "%d", number_of_tests);
    #(PERIOD);
    if((number_of_tests > maximum_number_of_tests) && (maximum_number_of_tests != 0)) begin
        number_of_tests = maximum_number_of_tests;
    end
    for (test_iterator = 1; test_iterator < number_of_tests; test_iterator = test_iterator + 1) begin
        test_error <= 1'b0;
        test_key <= {array_max_size{1'b0}};
        test_key_size <= 32'b0;
        test_nonce <= {array_max_size{1'b0}};
        test_nonce_size <= 32'b0;
        test_key_tag <= {array_max_size{1'b0}};
        test_key_tag_size <= 32'b0;
        test_ad <= {array_max_size{1'b0}};
        test_ad_size <= 32'b0;
        test_pt <= {array_max_size{1'b0}};
        test_pt_size <= 32'b0;
        test_ct <= {array_max_size{1'b0}};
        test_ct_size <= 32'b0;
        test_tag <= {array_max_size{1'b0}};
        test_tag_size <= 32'b0;
        true_key_tag <= {array_max_size{1'b0}};
        true_key_tag_size <= 32'b0;
        true_pt <= {array_max_size{1'b0}};
        true_pt_size <= 32'b0;
        true_ct <= {array_max_size{1'b0}};
        true_ct_size <= 32'b0;
        true_tag <= {array_max_size{1'b0}};
        true_tag_size <= 32'b0;
        verification_tag <= 32'b0;
        #(PERIOD);
        status_ram_file = $fscanf(ram_file, "%d", test_key_size);
        load_iterator = 0;
        while (load_iterator < test_key_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            test_key[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", test_nonce_size);
        load_iterator = 0;
        while (load_iterator < test_nonce_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            test_nonce[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", test_ad_size);
        load_iterator = 0;
        while (load_iterator < test_ad_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            test_ad[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", true_pt_size);
        test_pt_size = true_pt_size;
        load_iterator = 0;
        while (load_iterator < true_pt_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            true_pt[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", true_key_tag_size);
        test_key_tag_size = true_key_tag_size;
        load_iterator = 0;
        while (load_iterator < true_key_tag_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            true_key_tag[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", true_ct_size);
        test_ct_size = true_ct_size;
        load_iterator = 0;
        while (load_iterator < true_ct_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            true_ct[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%d", true_tag_size);
        test_tag_size = true_tag_size;
        load_iterator = 0;
        while (load_iterator < true_tag_size*8) begin
            status_ram_file = $fscanf(ram_file, "%b", test_read_buffer);
            true_tag[load_iterator +:8] = test_read_buffer;
            load_iterator = load_iterator + 8;
        end
        status_ram_file = $fscanf(ram_file, "%b", true_debug_state);
        #(PERIOD);

        test_din = 32'h00;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_key, test_key_size);
        #(PERIOD);
        
        test_din = 32'h02;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_nonce, test_nonce_size);
        #(PERIOD);
        
        test_din = 32'h04;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        receive_tag(test_key_tag_size, test_key_tag);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_ad(test_ad, test_ad_size);
        #(PERIOD);
        
        test_din = 32'h02;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_pt_receive_ct(true_pt, true_pt_size, test_ct);
        #(PERIOD);
        
        test_din = 32'h04;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        receive_tag(test_tag_size, test_tag);
        #(PERIOD);
        
        while(test_din_ready != 1'b1) begin
            #(PERIOD);
        end
        #(PERIOD);
        test_verification <= 1'b1;
        if (true_key_tag == test_key_tag) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed key tags do not match expected ones");
        end
        #(PERIOD);
        test_error <= 1'b0;
        #(PERIOD);
        if (true_ct == test_ct) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed ciphertext do not match expected ones");
        end
        #(PERIOD);
        test_error <= 1'b0;
        #(PERIOD);
        if (true_tag != test_tag) begin
            test_error <= 1'b1;
            $display("Computed tag do not match expected ones");
        end else begin
            test_error <= 1'b0;
        end
        #(PERIOD);
        test_error <= 1'b0;
        #(PERIOD);
        if (true_debug_state != test.permutation_state) begin
            test_error <= 1'b1;
            $display("Final state do not match expected one");
        end else begin
            test_error <= 1'b0;
        end
        #(PERIOD);
        test_verification <= 1'b0;
        test_error <= 1'b0;
        #(PERIOD);

        test_key_tag <= {array_max_size{1'b0}};
        
        test_din = 32'h00;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_key, test_key_size);
        #(PERIOD);
        
        test_din = 32'h02;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_nonce, test_nonce_size);
        #(PERIOD);
        
        test_din = 32'h04;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        receive_tag(test_key_tag_size, test_key_tag);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_ad(test_ad, test_ad_size);
        #(PERIOD);
        
        test_din = 32'h03;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_pt_receive_ct(true_ct, true_ct_size, test_pt);
        #(PERIOD);
        
        test_din = 32'h05;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_verify_tag(true_tag, true_tag_size, verification_tag);
        #(PERIOD);
        
        while(test_din_ready != 1'b1) begin
            #(PERIOD);
        end
        #(PERIOD);
        test_verification <= 1'b1;
        if (true_key_tag == test_key_tag) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed key tags do not match expected ones");
        end
        #PERIOD;
        test_error <= 1'b0;
        #PERIOD;
        if (true_pt == test_pt) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed plaintext do not match expected ones");
        end
        #PERIOD;
        test_error <= 1'b0;
        #PERIOD;
        if ((true_tag_size > 0) && (verification_tag != 32'b0)) begin
            test_error <= 1'b1;
            $display("Tags do not match expected ones");
        end else begin
            test_error <= 1'b0;
        end
        #PERIOD;
        test_error <= 1'b0;
        #PERIOD;
        if (true_debug_state != test.permutation_state) begin
            test_error <= 1'b1;
            $display("Final state do not match expected one");
        end else begin
            test_error <= 1'b0;
        end
        #PERIOD;
        test_verification <= 1'b0;
        test_error <= 1'b0;
        #PERIOD;

        test_key_tag <= {array_max_size{1'b0}};
        true_tag[0] = true_tag[0] ^ 1'b1;
        
        test_din = 32'h00;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_key, test_key_size);
        #(PERIOD);
        
        test_din = 32'h02;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_key_or_nonce(test_nonce, test_nonce_size);
        #(PERIOD);
        
        test_din = 32'h04;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 8'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        receive_tag(test_key_tag_size, test_key_tag);
        #(PERIOD);
        
        test_din = 32'h01;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_ad(test_ad, test_ad_size);
        #(PERIOD);
        
        test_din = 32'h03;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_pt_receive_ct(true_ct, true_ct_size, test_pt);
        #(PERIOD);
        
        test_din = 32'h05;
        test_din_valid = 1'b1;
        if(test_din_ready != 1'b1) begin
            #(PERIOD);
            while(test_din_ready != 1'b1) begin
                #(PERIOD);
            end
            #(PERIOD);
        end else begin
            #(PERIOD);
        end
        test_din = 32'h00;
        test_din_valid = 1'b0;
        #(number_of_wait_cycles*PERIOD);
        send_verify_tag(true_tag, true_tag_size, verification_tag);
        #(PERIOD);
        
        while(test_din_ready != 1'b1) begin
            #(PERIOD);
        end
        #(PERIOD);
        test_verification <= 1'b1;
        if (true_key_tag == test_key_tag) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed key tags do not match expected ones");
        end
        #PERIOD;
        test_error <= 1'b0;
        #PERIOD;
        if (true_pt == test_pt) begin
            test_error <= 1'b0;
        end else begin
            test_error <= 1'b1;
            $display("Computed plaintext do not match expected ones");
        end
        #PERIOD;
        test_error <= 1'b0;
        #PERIOD;
        if ((true_tag_size > 0) && (verification_tag == 32'b0)) begin
            test_error <= 1'b1;
            $display("Tags are matching when they should not");
        end else begin
            test_error <= 1'b0;
        end
        #PERIOD;
        test_verification <= 1'b0;
        test_error <= 1'b0;
        #PERIOD;
    end
    $fclose(ram_file);
    $display("End of the test.");
    disable clock_generator;
    #(PERIOD);
end

initial
begin
    $dumpfile("dump.vcd");
    $dumpvars(1, tb_friet_ae_32_bits);
end

endmodule