data/full_repos/permissive/114459345/srcCache/id_ex.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:10: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] id_pc,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] id_pc,\n                        ^\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:11: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] id_aluop,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:12: Define or directive not defined: \'`AluFunct3Bus\'\n input wire[`AluFunct3Bus] id_alufunct3,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:13: Define or directive not defined: \'`AluFunct7Bus\'\n input wire[`AluFunct7Bus] id_alufunct7,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] id_reg1,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] id_reg2,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:16: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] id_imm,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] id_wd,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:18: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] id_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:21: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus] ex_pc,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:22: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus] ex_aluop,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:23: Define or directive not defined: \'`AluFunct3Bus\'\n output reg[`AluFunct3Bus] ex_alufunct3,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:24: Define or directive not defined: \'`AluFunct7Bus\'\n output reg[`AluFunct7Bus] ex_alufunct7,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:25: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] ex_reg1,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:26: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] ex_reg2,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:27: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] ex_imm,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] ex_wd,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:29: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] ex_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:32: Define or directive not defined: \'`CtrlWidth\'\n input wire[`CtrlWidth] stall\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:37: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:38: Define or directive not defined: \'`NopInst\'\n   ex_pc <= `NopInst;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:39: Define or directive not defined: \'`NOP\'\n   ex_aluop <= `NOP;\n               ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:40: Define or directive not defined: \'`NOP_FUNCT3\'\n   ex_alufunct3 <= `NOP_FUNCT3;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:41: Define or directive not defined: \'`NOP_FUNCT7\'\n   ex_alufunct7 <= `NOP_FUNCT7;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:42: Define or directive not defined: \'`ZeroWord\'\n   ex_reg1 <= `ZeroWord;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:43: Define or directive not defined: \'`ZeroWord\'\n   ex_reg2 <= `ZeroWord;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:44: Define or directive not defined: \'`ZeroWord\'\n   ex_imm <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:45: Define or directive not defined: \'`NopRegAddr\'\n   ex_wd <= `NopRegAddr;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:46: Define or directive not defined: \'`WriteDisable\'\n   ex_wreg <= `WriteDisable;\n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:48: Define or directive not defined: \'`EX_BIT\'\n  else if(stall[`EX_BIT] == `Stop) begin\n                ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:48: Define or directive not defined: \'`Stop\'\n  else if(stall[`EX_BIT] == `Stop) begin\n                            ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:50: Define or directive not defined: \'`MEM_BIT\'\n   if(stall[`MEM_BIT] == `Continue) begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:50: Define or directive not defined: \'`Continue\'\n   if(stall[`MEM_BIT] == `Continue) begin\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:51: Define or directive not defined: \'`NopInst\'\n    ex_pc <= `NopInst;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:52: Define or directive not defined: \'`NOP\'\n    ex_aluop <= `NOP;\n                ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:53: Define or directive not defined: \'`NOP_FUNCT3\'\n    ex_alufunct3 <= `NOP_FUNCT3;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:54: Define or directive not defined: \'`NOP_FUNCT7\'\n    ex_alufunct7 <= `NOP_FUNCT7;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:55: Define or directive not defined: \'`ZeroWord\'\n    ex_reg1 <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:56: Define or directive not defined: \'`ZeroWord\'\n    ex_reg2 <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:57: Define or directive not defined: \'`ZeroWord\'\n    ex_imm <= `ZeroWord;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:58: Define or directive not defined: \'`NopRegAddr\'\n    ex_wd <= `NopRegAddr;\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:59: Define or directive not defined: \'`WriteDisable\'\n    ex_wreg <= `WriteDisable;    \n               ^~~~~~~~~~~~~\n%Error: Exiting due to 44 error(s)\n'
module id_ex(

	input wire clk,
	input wire rst,
	

	input wire[`InstAddrBus] id_pc,
	input wire[`AluOpBus] id_aluop,
	input wire[`AluFunct3Bus] id_alufunct3,
	input wire[`AluFunct7Bus] id_alufunct7,
	input wire[`RegBus] id_reg1,
	input wire[`RegBus] id_reg2,
	input wire[`RegBus] id_imm,
	input wire id_wreg,
	input wire[`RegAddrBus] id_wd,
	

	output reg[`InstAddrBus] ex_pc,
	output reg[`AluOpBus] ex_aluop,
	output reg[`AluFunct3Bus] ex_alufunct3,
	output reg[`AluFunct7Bus] ex_alufunct7,
	output reg[`RegBus] ex_reg1,
	output reg[`RegBus] ex_reg2,
	output reg[`RegBus] ex_imm,
	output reg ex_wreg,
	output reg[`RegAddrBus] ex_wd,
	

	input wire[`CtrlWidth] stall

);

	always @ (posedge clk) begin
		if(rst == `RstEnable) begin
			ex_pc <= `NopInst;
			ex_aluop <= `NOP;
			ex_alufunct3 <= `NOP_FUNCT3;
			ex_alufunct7 <= `NOP_FUNCT7;
			ex_reg1 <= `ZeroWord;
			ex_reg2 <= `ZeroWord;
			ex_imm <= `ZeroWord;
			ex_wd <= `NopRegAddr;
			ex_wreg <= `WriteDisable;
		end
		else if(stall[`EX_BIT] == `Stop) begin

			if(stall[`MEM_BIT] == `Continue) begin
				ex_pc <= `NopInst;
				ex_aluop <= `NOP;
				ex_alufunct3 <= `NOP_FUNCT3;
				ex_alufunct7 <= `NOP_FUNCT7;
				ex_reg1 <= `ZeroWord;
				ex_reg2 <= `ZeroWord;
				ex_imm <= `ZeroWord;
				ex_wd <= `NopRegAddr;
				ex_wreg <= `WriteDisable;				
			end
			else begin			

			end
		end
		else begin
			ex_pc <= id_pc;
			ex_aluop <= id_aluop;
			ex_alufunct3 <= id_alufunct3;
			ex_alufunct7 <= id_alufunct7;
			ex_reg1 <= id_reg1;
			ex_reg2 <= id_reg2;
			ex_imm <= id_imm;
			ex_wreg <= id_wreg;
			ex_wd <= id_wd;
		end
	end

endmodule
module id_ex(

	input wire clk,
	input wire rst,
	

	input wire[`InstAddrBus] id_pc,
	input wire[`AluOpBus] id_aluop,
	input wire[`AluFunct3Bus] id_alufunct3,
	input wire[`AluFunct7Bus] id_alufunct7,
	input wire[`RegBus] id_reg1,
	input wire[`RegBus] id_reg2,
	input wire[`RegBus] id_imm,
	input wire id_wreg,
	input wire[`RegAddrBus] id_wd,
	

	output reg[`InstAddrBus] ex_pc,
	output reg[`AluOpBus] ex_aluop,
	output reg[`AluFunct3Bus] ex_alufunct3,
	output reg[`AluFunct7Bus] ex_alufunct7,
	output reg[`RegBus] ex_reg1,
	output reg[`RegBus] ex_reg2,
	output reg[`RegBus] ex_imm,
	output reg ex_wreg,
	output reg[`RegAddrBus] ex_wd,
	

	input wire[`CtrlWidth] stall

);


	always @ (posedge clk) begin
		if(rst == `RstEnable) begin
			ex_pc <= `NopInst;
			ex_aluop <= `NOP;
			ex_alufunct3 <= `NOP_FUNCT3;
			ex_alufunct7 <= `NOP_FUNCT7;
			ex_reg1 <= `ZeroWord;
			ex_reg2 <= `ZeroWord;
			ex_imm <= `ZeroWord;
			ex_wd <= `NopRegAddr;
			ex_wreg <= `WriteDisable;
		end
		else if(stall[`EX_BIT] == `Stop) begin

			if(stall[`MEM_BIT] == `Continue) begin
				ex_pc <= `NopInst;
				ex_aluop <= `NOP;
				ex_alufunct3 <= `NOP_FUNCT3;
				ex_alufunct7 <= `NOP_FUNCT7;
				ex_reg1 <= `ZeroWord;
				ex_reg2 <= `ZeroWord;
				ex_imm <= `ZeroWord;
				ex_wd <= `NopRegAddr;
				ex_wreg <= `WriteDisable;				
			end
			else begin			

			end
		end
		else begin
			ex_pc <= id_pc;
			ex_aluop <= id_aluop;
			ex_alufunct3 <= id_alufunct3;
			ex_alufunct7 <= id_alufunct7;
			ex_reg1 <= id_reg1;
			ex_reg2 <= id_reg2;
			ex_imm <= id_imm;
			ex_wreg <= id_wreg;
			ex_wd <= id_wd;
		end
	end

endmodule