data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v
 line:51: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:47: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clock_i <= ~clock_i;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #174 serial_i <= 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #174 serial_i <= data[0];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #174 serial_i <= data[1];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #174 serial_i <= data[2];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #174 serial_i <= data[3];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #174 serial_i <= data[4];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #174 serial_i <= data[5];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #174 serial_i <= data[6];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #174 serial_i <= data[7];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #174 serial_i <= 1\'b1;  \n    ^\n%Error: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:10: Cannot find file containing module: \'maxv_5m570z_start_golden_top\'\nmaxv_5m570z_start_golden_top dut (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122777989/max_v_dev_kit/test,data/full_repos/permissive/122777989/maxv_5m570z_start_golden_top\n             data/full_repos/permissive/122777989/max_v_dev_kit/test,data/full_repos/permissive/122777989/maxv_5m570z_start_golden_top.v\n             data/full_repos/permissive/122777989/max_v_dev_kit/test,data/full_repos/permissive/122777989/maxv_5m570z_start_golden_top.sv\n             maxv_5m570z_start_golden_top\n             maxv_5m570z_start_golden_top.v\n             maxv_5m570z_start_golden_top.sv\n             obj_dir/maxv_5m570z_start_golden_top\n             obj_dir/maxv_5m570z_start_golden_top.v\n             obj_dir/maxv_5m570z_start_golden_top.sv\n%Warning-WIDTH: data/full_repos/permissive/122777989/max_v_dev_kit/test/loopback_test.v:43: Operator ASSIGNW expects 34 bits on the Assign RHS, but Assign RHS\'s CONST \'33\'h0\' generates 33 bits.\n                                                                                          : ... In instance loopbackTest\nassign gpio[36:3] = 33\'b0;\n                  ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module loopbackTest ();

reg clock_i = 1'b0;
reg reset_i = 1'b0;
reg serial_i = 1'b1;

wire [36:1] gpio;
wire serial_o;

maxv_5m570z_start_golden_top dut (
  .CLK_SE_AR(clock_i),
  .AGPIO(gpio),
  .USER_PB0(~reset_i)



























);

assign gpio[36:3] = 33'b0;
assign serial_o = gpio[1];
assign gpio[2] = serial_i;

always #1 clock_i <= ~clock_i;

initial begin
  #1
  send_packet(8'h55);
  send_packet(8'hAA);
  send_packet(8'hCC);
  send_packet(8'h33);
end

task send_packet;
  input [7:0] data;

  begin
    #174 serial_i <= 1'b0;
    #174 serial_i <= data[0];
    #174 serial_i <= data[1];
    #174 serial_i <= data[2];
    #174 serial_i <= data[3];
    #174 serial_i <= data[4];
    #174 serial_i <= data[5];
    #174 serial_i <= data[6];
    #174 serial_i <= data[7];
    #174 serial_i <= 1'b1;
  end
endtask

endmodule
module loopbackTest ();


reg clock_i = 1'b0;
reg reset_i = 1'b0;
reg serial_i = 1'b1;

wire [36:1] gpio;
wire serial_o;

maxv_5m570z_start_golden_top dut (
  .CLK_SE_AR(clock_i),
  .AGPIO(gpio),
  .USER_PB0(~reset_i)



























);

assign gpio[36:3] = 33'b0;
assign serial_o = gpio[1];
assign gpio[2] = serial_i;

always #1 clock_i <= ~clock_i;

initial begin
  #1
  send_packet(8'h55);
  send_packet(8'hAA);
  send_packet(8'hCC);
  send_packet(8'h33);
end

task send_packet;
  input [7:0] data;

  begin
    #174 serial_i <= 1'b0;
    #174 serial_i <= data[0];
    #174 serial_i <= data[1];
    #174 serial_i <= data[2];
    #174 serial_i <= data[3];
    #174 serial_i <= data[4];
    #174 serial_i <= data[5];
    #174 serial_i <= data[6];
    #174 serial_i <= data[7];
    #174 serial_i <= 1'b1;
  end
endtask

endmodule