data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v
1: b'%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:1: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:2: Cannot find include file: alu_ops.vh\n`include "alu_ops.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:3: Cannot find include file: rv32_opcodes.vh\n`include "rv32_opcodes.vh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:9: Define or directive not defined: \'`DATA_LEN\'\n   input wire [`DATA_LEN-1:0]    ex_src1,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:10: Define or directive not defined: \'`DATA_LEN\'\n   input wire [`DATA_LEN-1:0]    ex_src2,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:11: Define or directive not defined: \'`ADDR_LEN\'\n   input wire [`ADDR_LEN-1:0]    pc,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:12: Define or directive not defined: \'`DATA_LEN\'\n   input wire [`DATA_LEN-1:0]    imm,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:14: Define or directive not defined: \'`ALU_OP_WIDTH\'\n   input wire [`ALU_OP_WIDTH-1:0] alu_op,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:15: Define or directive not defined: \'`SPECTAG_LEN\'\n   input wire [`SPECTAG_LEN-1:0]  spectag,\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:17: Define or directive not defined: \'`ADDR_LEN\'\n   input wire [`ADDR_LEN-1:0]    praddr,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:20: Define or directive not defined: \'`DATA_LEN\'\n   output wire [`DATA_LEN-1:0]    result,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:25: Define or directive not defined: \'`ADDR_LEN\'\n   output wire [`ADDR_LEN-1:0]    jmpaddr,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:26: Define or directive not defined: \'`ADDR_LEN\'\n   output wire [`ADDR_LEN-1:0]    jmpaddr_taken,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:28: Define or directive not defined: \'`SPECTAG_LEN\'\n   output wire [`SPECTAG_LEN-1:0] tagregfix\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:33: Define or directive not defined: \'`DATA_LEN\'\n   wire [`DATA_LEN-1:0]        comprslt;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:43: Define or directive not defined: \'`RV32_JALR\'\n   assign jmpaddr_taken = (((opcode == `RV32_JALR) ? ex_src1 : pc) + imm);\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:43: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign jmpaddr_taken = (((opcode == `RV32_JALR) ? ex_src1 : pc) + imm);\n                                                 ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:45: Define or directive not defined: \'`RV32_JAL\'\n   assign brcond = ((opcode == `RV32_JAL) || (opcode == `RV32_JALR)) ?\n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign brcond = ((opcode == `RV32_JAL) || (opcode == `RV32_JALR)) ?\n                                        ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:45: Define or directive not defined: \'`RV32_JALR\'\n   assign brcond = ((opcode == `RV32_JAL) || (opcode == `RV32_JALR)) ?\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/exunit_branch.v:47: Define or directive not defined: \'`SPECTAG_LEN\'\n   assign tagregfix = {spectag[0], spectag[`SPECTAG_LEN-1:1]};\n                                           ^~~~~~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module exunit_branch
  (
   input wire 			  clk,
   input wire 			  reset,
   input wire [`DATA_LEN-1:0] 	  ex_src1,
   input wire [`DATA_LEN-1:0] 	  ex_src2,
   input wire [`ADDR_LEN-1:0] 	  pc,
   input wire [`DATA_LEN-1:0] 	  imm,
   input wire 			  dstval,
   input wire [`ALU_OP_WIDTH-1:0] alu_op,
   input wire [`SPECTAG_LEN-1:0]  spectag,
   input wire 			  specbit,
   input wire [`ADDR_LEN-1:0] 	  praddr,
   input wire [6:0] 		  opcode,
   input wire 			  issue,
   output wire [`DATA_LEN-1:0] 	  result,
   output wire 			  rrf_we,
   output wire 			  rob_we,
   output wire 			  prsuccess,
   output wire 			  prmiss,
   output wire [`ADDR_LEN-1:0] 	  jmpaddr,
   output wire [`ADDR_LEN-1:0] 	  jmpaddr_taken,
   output wire 			  brcond,
   output wire [`SPECTAG_LEN-1:0] tagregfix
   );

   reg 			       busy;
   
   wire [`DATA_LEN-1:0]        comprslt;
   wire 		       addrmatch = (jmpaddr == praddr) ? 1'b1 : 1'b0;

   
   assign rob_we = busy;
   assign rrf_we = busy & dstval;
   assign result = pc + 4;
   assign prsuccess = busy & addrmatch;
   assign prmiss = busy & ~addrmatch;
   assign jmpaddr = brcond ? jmpaddr_taken : (pc + 4);
   assign jmpaddr_taken = (((opcode == `RV32_JALR) ? ex_src1 : pc) + imm);
   
   assign brcond = ((opcode == `RV32_JAL) || (opcode == `RV32_JALR)) ?
			       1'b1 : comprslt[0];
   assign tagregfix = {spectag[0], spectag[`SPECTAG_LEN-1:1]};
   
   always @ (posedge clk) begin
      if (reset) begin
	 busy <= 0;
      end else begin
	 busy <= issue;
      end
   end
		  
   alu comparator
     (
      .op(alu_op),
      .in1(ex_src1),
      .in2(ex_src2),
      .out(comprslt)
      );
   
endmodule
module exunit_branch
  (
   input wire 			  clk,
   input wire 			  reset,
   input wire [`DATA_LEN-1:0] 	  ex_src1,
   input wire [`DATA_LEN-1:0] 	  ex_src2,
   input wire [`ADDR_LEN-1:0] 	  pc,
   input wire [`DATA_LEN-1:0] 	  imm,
   input wire 			  dstval,
   input wire [`ALU_OP_WIDTH-1:0] alu_op,
   input wire [`SPECTAG_LEN-1:0]  spectag,
   input wire 			  specbit,
   input wire [`ADDR_LEN-1:0] 	  praddr,
   input wire [6:0] 		  opcode,
   input wire 			  issue,
   output wire [`DATA_LEN-1:0] 	  result,
   output wire 			  rrf_we,
   output wire 			  rob_we,
   output wire 			  prsuccess,
   output wire 			  prmiss,
   output wire [`ADDR_LEN-1:0] 	  jmpaddr,
   output wire [`ADDR_LEN-1:0] 	  jmpaddr_taken,
   output wire 			  brcond,
   output wire [`SPECTAG_LEN-1:0] tagregfix
   );


   reg 			       busy;
   
   wire [`DATA_LEN-1:0]        comprslt;
   wire 		       addrmatch = (jmpaddr == praddr) ? 1'b1 : 1'b0;

   
   assign rob_we = busy;
   assign rrf_we = busy & dstval;
   assign result = pc + 4;
   assign prsuccess = busy & addrmatch;
   assign prmiss = busy & ~addrmatch;
   assign jmpaddr = brcond ? jmpaddr_taken : (pc + 4);
   assign jmpaddr_taken = (((opcode == `RV32_JALR) ? ex_src1 : pc) + imm);
   
   assign brcond = ((opcode == `RV32_JAL) || (opcode == `RV32_JALR)) ?
			       1'b1 : comprslt[0];
   assign tagregfix = {spectag[0], spectag[`SPECTAG_LEN-1:1]};
   
   always @ (posedge clk) begin
      if (reset) begin
	 busy <= 0;
      end else begin
	 busy <= issue;
      end
   end
		  
   alu comparator
     (
      .op(alu_op),
      .in1(ex_src1),
      .in2(ex_src2),
      .out(comprslt)
      );
   
endmodule