data/full_repos/permissive/196412397/blockram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/196412397/blockram.v:28: Bit extraction of array[307199:0] requires 19 bit index, not 17 bits.\n                                                                  : ... In instance rams_tdp_rf_rf\n            ram[addra] <= dia;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/196412397/blockram.v:29: Bit extraction of array[307199:0] requires 19 bit index, not 17 bits.\n                                                                  : ... In instance rams_tdp_rf_rf\n            doa <= ram[addra];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/196412397/blockram.v:37: Bit extraction of array[307199:0] requires 19 bit index, not 17 bits.\n                                                                  : ... In instance rams_tdp_rf_rf\n            ram[addrb] <= dib;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/196412397/blockram.v:38: Bit extraction of array[307199:0] requires 19 bit index, not 17 bits.\n                                                                  : ... In instance rams_tdp_rf_rf\n            dob <= ram[addrb];\n                      ^\n%Error: Exiting due to 4 warning(s)\n'
module rams_tdp_rf_rf #( parameter
    DEPTH =  307_200,
    ADDR_WIDTH = 17, 
    DATA_WIDTH = 8 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);

input clka,clkb,ena,enb,wea,web;
input [ADDR_WIDTH-1:0] addra,addrb;
input [DATA_WIDTH-1:0] dia,dib;
output [DATA_WIDTH-1:0] doa,dob;

reg [DATA_WIDTH-1:0] ram [ DEPTH - 1 :0];
reg [DATA_WIDTH-1:0] doa,dob;

always @(posedge clka)
begin
    if (ena)
    begin
        if (wea)
            ram[addra] <= dia;
            doa <= ram[addra];
        end
    end
always @(posedge clkb)
begin
    if (enb)
    begin
        if (web)
            ram[addrb] <= dib;
            dob <= ram[addrb];
    end
end
endmodule
module rams_tdp_rf_rf #( parameter
    DEPTH =  307_200,
    ADDR_WIDTH = 17, 
    DATA_WIDTH = 8 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);


input clka,clkb,ena,enb,wea,web;
input [ADDR_WIDTH-1:0] addra,addrb;
input [DATA_WIDTH-1:0] dia,dib;
output [DATA_WIDTH-1:0] doa,dob;

reg [DATA_WIDTH-1:0] ram [ DEPTH - 1 :0];
reg [DATA_WIDTH-1:0] doa,dob;

always @(posedge clka)
begin
    if (ena)
    begin
        if (wea)
            ram[addra] <= dia;
            doa <= ram[addra];
        end
    end
always @(posedge clkb)
begin
    if (enb)
    begin
        if (web)
            ram[addrb] <= dib;
            dob <= ram[addrb];
    end
end
endmodule