data/full_repos/permissive/132304455/src/equality_check.v
data/verilator_xmls/1400f56b-9cd7-4a51-b617-1de9d88885db.xml
module equality_check(input_correct,
                      input_done,
                      number_input,
                      number_desired,
                      button,
                      clk);

    output reg   input_correct, input_done;
    input  [5:0] number_input, number_desired;
    input        button, clk;

    wire equal = (number_input == number_desired);
    
    always@(posedge clk)
    begin
        input_done    <= button;
        input_correct <= (equal & button);
    end

endmodule
module equality_check(input_correct,
                      input_done,
                      number_input,
                      number_desired,
                      button,
                      clk);


    output reg   input_correct, input_done;
    input  [5:0] number_input, number_desired;
    input        button, clk;

    wire equal = (number_input == number_desired);
    
    always@(posedge clk)
    begin
        input_done    <= button;
        input_correct <= (equal & button);
    end

endmodule