data/full_repos/permissive/159823067/omercevik_hw4_32bitMips_SingleCycle_Datapath_verilog_files/nextPC.v
data/verilator_xmls/71065ab4-3801-444c-b995-58e2f5c63495.xml
module nextPC(PC, PCnext, clk);

	input clk;
	input [31:0] PC;
	output reg [31:0] PCnext;

	always @(posedge clk)
	begin
		PCnext = PC;
	end

endmodule
module nextPC(PC, PCnext, clk);


	input clk;
	input [31:0] PC;
	output reg [31:0] PCnext;

	always @(posedge clk)
	begin
		PCnext = PC;
	end

endmodule