data/full_repos/permissive/158922207/Verilog Design/modules/tri_state_buff.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/tri_state_buff.v\n%Error: Exiting due to 3 error(s)\n'
module tri_state_buff(out, in, switch);
parameter N = 4;
output [N-1:0] out;
input [N-1:0] in;
input switch;
reg [N-1:0] out = 0;

always @(switch)
if (switch == 1'b1) out <= 'bZ;
else out <= in;
endmodule
module tri_state_buff(out, in, switch);

parameter N = 4;
output [N-1:0] out;
input [N-1:0] in;
input switch;
reg [N-1:0] out = 0;

always @(switch)
if (switch == 1'b1) out <= 'bZ;
else out <= in;
endmodule