data/full_repos/permissive/136238697/verilogboxes/divmodder.v
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data/verilator_xmls/89544360-c7f0-45db-9a27-f4f559558543.xml
module divmodder
  #( parameter WIDTH = 32,
     parameter LATENCY = 4 
   )
   (
     input clock,
     input reset,
     input [WIDTH-1:0] in1,
     input [WIDTH-1:0] in2,
     output reg [WIDTH-1:0] div,
     output reg [WIDTH-1:0] mod
   );
  integer i;
  reg [WIDTH-1:0] sr1[LATENCY];
  reg [WIDTH-1:0] sr2[LATENCY];

  always @(posedge clock) begin
    begin
      sr1[0] <= in1 % in2;
      sr2[0] <= in1 / in2;
      for(i=1; i<LATENCY; i=i+1) begin
        sr1[i] <= sr1[i-1];
        sr2[i] <= sr2[i-1];
      end
    end
  end

  always @(*) begin
    mod = sr1[LATENCY-1];
    div = sr2[LATENCY-1];
  end

endmodule
module divmodder
  #( parameter WIDTH = 32,
     parameter LATENCY = 4 
   )
   (
     input clock,
     input reset,
     input [WIDTH-1:0] in1,
     input [WIDTH-1:0] in2,
     output reg [WIDTH-1:0] div,
     output reg [WIDTH-1:0] mod
   );

  integer i;
  reg [WIDTH-1:0] sr1[LATENCY];
  reg [WIDTH-1:0] sr2[LATENCY];

  always @(posedge clock) begin
    begin
      sr1[0] <= in1 % in2;
      sr2[0] <= in1 / in2;
      for(i=1; i<LATENCY; i=i+1) begin
        sr1[i] <= sr1[i-1];
        sr2[i] <= sr2[i-1];
      end
    end
  end

  always @(*) begin
    mod = sr1[LATENCY-1];
    div = sr2[LATENCY-1];
  end

endmodule