data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v
 line:22: before: "."
1: b'%Warning-MULTITOP: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:347: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'fpga_top\'\nmodule fpga_top(output wire WF_NEO);\n       ^~~~~~~~\n                                                                                                : ... Top module \'WF_random_5\'\n   module WF_random_5 (\n          ^~~~~~~~~~~\n                                                                                                : ... Top module \'WF_switch_debounce\'\n   module WF_switch_debounce (\n          ^~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:26: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:28: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:34: Signal definition not found, creating implicitly: \'two_ms\'\n           .timer_pulse(two_ms));\n                        ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:262: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance fpga_top.neopixel_inst\n                   pixel_bit_cnt <= 1\'b0;\n                                 ^~\n%Error: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:16: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.v\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module fpga_top(output wire WF_NEO);


   wire      clk_en = 1'b1;
	
   reg [23:0] np_pixels;







  SB_HFOSC OSC_i (
	    .CLKHFEN(clk_en),
	    .CLKHFPU(clk_en),
	    .CLKHF(clk));


   defparam OSC_i.CLKHF_DIV = "0b10";


     WF_timer #(.COUNT(119), .EVERY_CLK(1'b1)) ten_usec(
           .clk(clk),
           .enable(1'b1),
           .timer_pulse(ten_us));


     WF_timer #(.COUNT(199)) two_msec(
           .clk(clk),
           .enable(ten_us),
           .timer_pulse(two_ms));


    WF_neopixel_if #(
           .NUM_OF_PIXELS(1))
    neopixel_inst(
           .clk(clk),
           .ten_us(ten_us),
           .ram_rd_addr(),
           .ram_rd_data(np_pixels),
           .DOUT(WF_NEO));






  reg [1:0] cnt;
  reg [6:0] cnt2;
  reg       updn;
  reg [2:0] ph;


  wire [6:0] cnt2_G={cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};
  wire [6:0] cnt2_R={cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};
  wire [6:0] cnt2_B={cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};


   always @(posedge clk)
     begin
       if (two_ms)
	 begin
           cnt <= cnt + 2'h01;
           if (cnt == 0)
             begin
               if (cnt2 ==  127)
	         begin
                   cnt2 <= 126;
                   updn <= ~updn;
	           ph   <= ph + 3'b1;
	         end
	       else if (cnt2==1 && updn==1)
	         begin
                   cnt2 <= 1;
                   updn <= ~updn;
	           ph   <= ph + 3'b1;
	         end
	       else if (updn==0)
                 cnt2 <= cnt2 + 7'b1;
	       else
                 cnt2 <= cnt2 - 7'b1;
	     end
	  end
     end

   always @(*)
    case (ph)
      3'h0: np_pixels[23:0] <= {8'h00,8'hfe,8'h00};
      3'h1: np_pixels[23:0] <= {8'h00,8'h00,8'hfe};
      3'h2: np_pixels[23:0] <= {8'hfe,8'h00,8'h00};
      3'h3: np_pixels[23:0] <= {8'h00,{cnt2_R,1'b0},8'h00};
      3'h4: np_pixels[23:0] <= {8'h00,8'h00,{cnt2_G,1'b0}};
      3'h5: np_pixels[23:0] <= {{cnt2_B,1'b0},8'h00,8'h00};
      3'h6: np_pixels[23:0] <= {8'h00,{cnt2_R,1'b0},{~cnt2_G,1'b0}};
      3'h7: np_pixels[23:0] <= {{cnt2_B,1'b0},8'h00,{~cnt2_G,1'b0}};
    endcase

endmodule
module fpga_top(output wire WF_NEO);



   wire      clk_en = 1'b1;
	
   reg [23:0] np_pixels;







  SB_HFOSC OSC_i (
	    .CLKHFEN(clk_en),
	    .CLKHFPU(clk_en),
	    .CLKHF(clk));


   defparam OSC_i.CLKHF_DIV = "0b10";


     WF_timer #(.COUNT(119), .EVERY_CLK(1'b1)) ten_usec(
           .clk(clk),
           .enable(1'b1),
           .timer_pulse(ten_us));


     WF_timer #(.COUNT(199)) two_msec(
           .clk(clk),
           .enable(ten_us),
           .timer_pulse(two_ms));


    WF_neopixel_if #(
           .NUM_OF_PIXELS(1))
    neopixel_inst(
           .clk(clk),
           .ten_us(ten_us),
           .ram_rd_addr(),
           .ram_rd_data(np_pixels),
           .DOUT(WF_NEO));






  reg [1:0] cnt;
  reg [6:0] cnt2;
  reg       updn;
  reg [2:0] ph;


  wire [6:0] cnt2_G={cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};
  wire [6:0] cnt2_R={cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};
  wire [6:0] cnt2_B={cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};


   always @(posedge clk)
     begin
       if (two_ms)
	 begin
           cnt <= cnt + 2'h01;
           if (cnt == 0)
             begin
               if (cnt2 ==  127)
	         begin
                   cnt2 <= 126;
                   updn <= ~updn;
	           ph   <= ph + 3'b1;
	         end
	       else if (cnt2==1 && updn==1)
	         begin
                   cnt2 <= 1;
                   updn <= ~updn;
	           ph   <= ph + 3'b1;
	         end
	       else if (updn==0)
                 cnt2 <= cnt2 + 7'b1;
	       else
                 cnt2 <= cnt2 - 7'b1;
	     end
	  end
     end

   always @(*)
    case (ph)
      3'h0: np_pixels[23:0] <= {8'h00,8'hfe,8'h00};
      3'h1: np_pixels[23:0] <= {8'h00,8'h00,8'hfe};
      3'h2: np_pixels[23:0] <= {8'hfe,8'h00,8'h00};
      3'h3: np_pixels[23:0] <= {8'h00,{cnt2_R,1'b0},8'h00};
      3'h4: np_pixels[23:0] <= {8'h00,8'h00,{cnt2_G,1'b0}};
      3'h5: np_pixels[23:0] <= {{cnt2_B,1'b0},8'h00,8'h00};
      3'h6: np_pixels[23:0] <= {8'h00,{cnt2_R,1'b0},{~cnt2_G,1'b0}};
      3'h7: np_pixels[23:0] <= {{cnt2_B,1'b0},8'h00,{~cnt2_G,1'b0}};
    endcase

endmodule