data/full_repos/permissive/127511545/src/Register.v
1: b"%Error: data/full_repos/permissive/127511545/src/Register.v:72: Cannot find file containing module: 'DFlipFlop'\n DFlipFlop dff0(BitOutput, D, Reset, CLK);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/DFlipFlop\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/DFlipFlop.v\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/DFlipFlop.sv\n             DFlipFlop\n             DFlipFlop.v\n             DFlipFlop.sv\n             obj_dir/DFlipFlop\n             obj_dir/DFlipFlop.v\n             obj_dir/DFlipFlop.sv\n%Error: data/full_repos/permissive/127511545/src/Register.v:17: Cannot find file containing module: 'Decoder'\n Decoder d0(WriteEnable, RegisterWrite, WriteRegister);\n ^~~~~~~\n%Error: data/full_repos/permissive/127511545/src/Register.v:52: Cannot find file containing module: 'MUX32x32to32'\n%Error: data/full_repos/permissive/127511545/src/Register.v:55: Cannot find file containing module: 'MUX32x32to32'\n%Error: Exiting due to 4 error(s)\n"
module Register(RegisterOutput, RegisterInput, WriteEnable, Reset, CLK);

	output[31:0] RegisterOutput;
	input[31:0] RegisterInput;
	input WriteEnable, Reset, CLK;

	RegisterBit bit31(RegisterOutput[31], RegisterInput[31], WriteEnable, Reset, CLK);
	RegisterBit bit30(RegisterOutput[30], RegisterInput[30], WriteEnable, Reset, CLK);
	RegisterBit bit29(RegisterOutput[29], RegisterInput[29], WriteEnable, Reset, CLK);
	RegisterBit bit28(RegisterOutput[28], RegisterInput[28], WriteEnable, Reset, CLK);
	RegisterBit bit27(RegisterOutput[27], RegisterInput[27], WriteEnable, Reset, CLK);
	RegisterBit bit26(RegisterOutput[26], RegisterInput[26], WriteEnable, Reset, CLK);
	RegisterBit bit25(RegisterOutput[25], RegisterInput[25], WriteEnable, Reset, CLK);
	RegisterBit bit24(RegisterOutput[24], RegisterInput[24], WriteEnable, Reset, CLK);
	RegisterBit bit23(RegisterOutput[23], RegisterInput[23], WriteEnable, Reset, CLK);
	RegisterBit bit22(RegisterOutput[22], RegisterInput[22], WriteEnable, Reset, CLK);
	RegisterBit bit21(RegisterOutput[21], RegisterInput[21], WriteEnable, Reset, CLK);
	RegisterBit bit20(RegisterOutput[20], RegisterInput[20], WriteEnable, Reset, CLK);
	RegisterBit bit19(RegisterOutput[19], RegisterInput[19], WriteEnable, Reset, CLK);
	RegisterBit bit18(RegisterOutput[18], RegisterInput[18], WriteEnable, Reset, CLK);
	RegisterBit bit17(RegisterOutput[17], RegisterInput[17], WriteEnable, Reset, CLK);
	RegisterBit bit16(RegisterOutput[16], RegisterInput[16], WriteEnable, Reset, CLK);
	RegisterBit bit15(RegisterOutput[15], RegisterInput[15], WriteEnable, Reset, CLK);
	RegisterBit bit14(RegisterOutput[14], RegisterInput[14], WriteEnable, Reset, CLK);
	RegisterBit bit13(RegisterOutput[13], RegisterInput[13], WriteEnable, Reset, CLK);
	RegisterBit bit12(RegisterOutput[12], RegisterInput[12], WriteEnable, Reset, CLK);
	RegisterBit bit11(RegisterOutput[11], RegisterInput[11], WriteEnable, Reset, CLK);
	RegisterBit bit10(RegisterOutput[10], RegisterInput[10], WriteEnable, Reset, CLK);
	RegisterBit bit9(RegisterOutput[9], RegisterInput[9], WriteEnable, Reset, CLK);
	RegisterBit bit8(RegisterOutput[8], RegisterInput[8], WriteEnable, Reset, CLK);
	RegisterBit bit7(RegisterOutput[7], RegisterInput[7], WriteEnable, Reset, CLK);
	RegisterBit bit6(RegisterOutput[6], RegisterInput[6], WriteEnable, Reset, CLK);
	RegisterBit bit5(RegisterOutput[5], RegisterInput[5], WriteEnable, Reset, CLK);
	RegisterBit bit4(RegisterOutput[4], RegisterInput[4], WriteEnable, Reset, CLK);
	RegisterBit bit3(RegisterOutput[3], RegisterInput[3], WriteEnable, Reset, CLK);
	RegisterBit bit2(RegisterOutput[2], RegisterInput[2], WriteEnable, Reset, CLK);
	RegisterBit bit1(RegisterOutput[1], RegisterInput[1], WriteEnable, Reset, CLK);
	RegisterBit bit0(RegisterOutput[0], RegisterInput[0], WriteEnable, Reset, CLK);

endmodule
module Register(RegisterOutput, RegisterInput, WriteEnable, Reset, CLK);


	output[31:0] RegisterOutput;
	input[31:0] RegisterInput;
	input WriteEnable, Reset, CLK;

	RegisterBit bit31(RegisterOutput[31], RegisterInput[31], WriteEnable, Reset, CLK);
	RegisterBit bit30(RegisterOutput[30], RegisterInput[30], WriteEnable, Reset, CLK);
	RegisterBit bit29(RegisterOutput[29], RegisterInput[29], WriteEnable, Reset, CLK);
	RegisterBit bit28(RegisterOutput[28], RegisterInput[28], WriteEnable, Reset, CLK);
	RegisterBit bit27(RegisterOutput[27], RegisterInput[27], WriteEnable, Reset, CLK);
	RegisterBit bit26(RegisterOutput[26], RegisterInput[26], WriteEnable, Reset, CLK);
	RegisterBit bit25(RegisterOutput[25], RegisterInput[25], WriteEnable, Reset, CLK);
	RegisterBit bit24(RegisterOutput[24], RegisterInput[24], WriteEnable, Reset, CLK);
	RegisterBit bit23(RegisterOutput[23], RegisterInput[23], WriteEnable, Reset, CLK);
	RegisterBit bit22(RegisterOutput[22], RegisterInput[22], WriteEnable, Reset, CLK);
	RegisterBit bit21(RegisterOutput[21], RegisterInput[21], WriteEnable, Reset, CLK);
	RegisterBit bit20(RegisterOutput[20], RegisterInput[20], WriteEnable, Reset, CLK);
	RegisterBit bit19(RegisterOutput[19], RegisterInput[19], WriteEnable, Reset, CLK);
	RegisterBit bit18(RegisterOutput[18], RegisterInput[18], WriteEnable, Reset, CLK);
	RegisterBit bit17(RegisterOutput[17], RegisterInput[17], WriteEnable, Reset, CLK);
	RegisterBit bit16(RegisterOutput[16], RegisterInput[16], WriteEnable, Reset, CLK);
	RegisterBit bit15(RegisterOutput[15], RegisterInput[15], WriteEnable, Reset, CLK);
	RegisterBit bit14(RegisterOutput[14], RegisterInput[14], WriteEnable, Reset, CLK);
	RegisterBit bit13(RegisterOutput[13], RegisterInput[13], WriteEnable, Reset, CLK);
	RegisterBit bit12(RegisterOutput[12], RegisterInput[12], WriteEnable, Reset, CLK);
	RegisterBit bit11(RegisterOutput[11], RegisterInput[11], WriteEnable, Reset, CLK);
	RegisterBit bit10(RegisterOutput[10], RegisterInput[10], WriteEnable, Reset, CLK);
	RegisterBit bit9(RegisterOutput[9], RegisterInput[9], WriteEnable, Reset, CLK);
	RegisterBit bit8(RegisterOutput[8], RegisterInput[8], WriteEnable, Reset, CLK);
	RegisterBit bit7(RegisterOutput[7], RegisterInput[7], WriteEnable, Reset, CLK);
	RegisterBit bit6(RegisterOutput[6], RegisterInput[6], WriteEnable, Reset, CLK);
	RegisterBit bit5(RegisterOutput[5], RegisterInput[5], WriteEnable, Reset, CLK);
	RegisterBit bit4(RegisterOutput[4], RegisterInput[4], WriteEnable, Reset, CLK);
	RegisterBit bit3(RegisterOutput[3], RegisterInput[3], WriteEnable, Reset, CLK);
	RegisterBit bit2(RegisterOutput[2], RegisterInput[2], WriteEnable, Reset, CLK);
	RegisterBit bit1(RegisterOutput[1], RegisterInput[1], WriteEnable, Reset, CLK);
	RegisterBit bit0(RegisterOutput[0], RegisterInput[0], WriteEnable, Reset, CLK);

endmodule