data/full_repos/permissive/150947952/doc/ref/fpga-md5-cracker/commented-verilog/LcdLineWriter.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/150947952/doc/ref/fpga-md5-cracker/commented-verilog/LcdLineWriter.v:64: Multiple top level modules\n                                                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                     : ... Top module \'LcdLineWriter\'\nmodule LcdLineWriter(\n       ^~~~~~~~~~~~~\n                                                                                                                     : ... Top module \'LcdLineWriterTester\'\nmodule LcdLineWriterTester(\n       ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/150947952/doc/ref/fpga-md5-cracker/commented-verilog/LcdLineWriter.v:43: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                                                                  : ... In instance LcdLineWriter\n       char <= charArray[state] != \'h00 ? charArray[state] : \'h20;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/150947952/doc/ref/fpga-md5-cracker/commented-verilog/LcdLineWriter.v:43: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                                                                  : ... In instance LcdLineWriter\n       char <= charArray[state] != \'h00 ? charArray[state] : \'h20;\n                                                   ^\n%Error: Exiting due to 3 warning(s)\n'
module LcdLineWriterTester(
	output wire [127:0] line
);

`define AssignLine(__ofs, __value) assign line[__ofs * 8 + 7 : __ofs * 8] = __value;

`AssignLine(0, 'h41)
`AssignLine(1, 'h41)
`AssignLine(2, 'h41)
`AssignLine(3, 'h41)

`AssignLine(4, 'h42)
`AssignLine(5, 'h42)
`AssignLine(6, 'h42)
`AssignLine(7, 'h42)

`AssignLine(8, 'h43)
`AssignLine(9, 'h43)
`AssignLine(10, 'h43)
`AssignLine(11, 'h43)

`AssignLine(12, 'h41)
`AssignLine(13, 'h42)
`AssignLine(14, 'h43)
`AssignLine(15, 'h44)





endmodule
module LcdLineWriterTester(
	output wire [127:0] line
);


`define AssignLine(__ofs, __value) assign line[__ofs * 8 + 7 : __ofs * 8] = __value;

`AssignLine(0, 'h41)
`AssignLine(1, 'h41)
`AssignLine(2, 'h41)
`AssignLine(3, 'h41)

`AssignLine(4, 'h42)
`AssignLine(5, 'h42)
`AssignLine(6, 'h42)
`AssignLine(7, 'h42)

`AssignLine(8, 'h43)
`AssignLine(9, 'h43)
`AssignLine(10, 'h43)
`AssignLine(11, 'h43)

`AssignLine(12, 'h41)
`AssignLine(13, 'h42)
`AssignLine(14, 'h43)
`AssignLine(15, 'h44)





endmodule