data/full_repos/permissive/201224775/rtl/ic/ic_top.v
1: b"%Error: data/full_repos/permissive/201224775/rtl/ic/ic_top.v:166: Cannot find file containing module: 'ic_error_rsp_stub'\nic_error_rsp_stub i_error_stub_imem (\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201224775/rtl/ic,data/full_repos/permissive/201224775/ic_error_rsp_stub\n             data/full_repos/permissive/201224775/rtl/ic,data/full_repos/permissive/201224775/ic_error_rsp_stub.v\n             data/full_repos/permissive/201224775/rtl/ic,data/full_repos/permissive/201224775/ic_error_rsp_stub.sv\n             ic_error_rsp_stub\n             ic_error_rsp_stub.v\n             ic_error_rsp_stub.sv\n             obj_dir/ic_error_rsp_stub\n             obj_dir/ic_error_rsp_stub.v\n             obj_dir/ic_error_rsp_stub.sv\n%Error: data/full_repos/permissive/201224775/rtl/ic/ic_top.v:236: Cannot find file containing module: 'ic_cpu_bus_axi_bridge'\nic_cpu_bus_axi_bridge i_cpu_dmem_axi_bridge (\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201224775/rtl/ic/ic_top.v:316: Cannot find file containing module: 'ic_error_rsp_stub'\nic_error_rsp_stub i_error_stub_dmem (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201224775/rtl/ic/ic_top.v:373: Cannot find file containing module: 'ic_rsp_tracker'\nic_rsp_tracker #(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201224775/rtl/ic/ic_top.v:433: Cannot find file containing module: 'ic_rsp_tracker'\nic_rsp_tracker #(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201224775/rtl/ic/ic_top.v:450: Cannot find file containing module: 'ic_addr_decode'\nic_addr_decode #(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201224775/rtl/ic/ic_top.v:472: Cannot find file containing module: 'ic_addr_decode'\nic_addr_decode #(\n^~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module ic_top (

input  wire        g_clk            ,
input  wire        g_resetn         ,

input  wire        cpu_imem_req     ,
input  wire        cpu_imem_wen     ,
input  wire [ 3:0] cpu_imem_strb    ,
input  wire [31:0] cpu_imem_wdata   ,
input  wire [31:0] cpu_imem_addr    ,
output wire        cpu_imem_gnt     ,
output wire        cpu_imem_recv    ,
input  wire        cpu_imem_ack     ,
output wire        cpu_imem_error   ,
output wire [31:0] cpu_imem_rdata   ,

input  wire        cpu_dmem_req     ,
input  wire        cpu_dmem_wen     ,
input  wire [ 3:0] cpu_dmem_strb    ,
input  wire [31:0] cpu_dmem_wdata   ,
input  wire [31:0] cpu_dmem_addr    ,
output wire        cpu_dmem_gnt     ,
output wire        cpu_dmem_recv    ,
input  wire        cpu_dmem_ack     ,
output wire        cpu_dmem_error   ,
output wire [31:0] cpu_dmem_rdata   ,

output wire        rom_imem_req     ,
output wire        rom_imem_wen     ,
output wire [ 3:0] rom_imem_strb    ,
output wire [31:0] rom_imem_wdata   ,
output wire [31:0] rom_imem_addr    ,
input  wire        rom_imem_gnt     ,
input  wire        rom_imem_recv    ,
output wire        rom_imem_ack     ,
input  wire        rom_imem_error   ,
input  wire [31:0] rom_imem_rdata   ,

output wire        ram_imem_req     ,
output wire        ram_imem_wen     ,
output wire [ 3:0] ram_imem_strb    ,
output wire [31:0] ram_imem_wdata   ,
output wire [31:0] ram_imem_addr    ,
input  wire        ram_imem_gnt     ,
input  wire        ram_imem_recv    ,
output wire        ram_imem_ack     ,
input  wire        ram_imem_error   ,
input  wire [31:0] ram_imem_rdata   ,

output wire        rom_dmem_req     ,
output wire        rom_dmem_wen     ,
output wire [ 3:0] rom_dmem_strb    ,
output wire [31:0] rom_dmem_wdata   ,
output wire [31:0] rom_dmem_addr    ,
input  wire        rom_dmem_gnt     ,
input  wire        rom_dmem_recv    ,
output wire        rom_dmem_ack     ,
input  wire        rom_dmem_error   ,
input  wire [31:0] rom_dmem_rdata   ,

output wire        ram_dmem_req     ,
output wire        ram_dmem_wen     ,
output wire [ 3:0] ram_dmem_strb    ,
output wire [31:0] ram_dmem_wdata   ,
output wire [31:0] ram_dmem_addr    ,
input  wire        ram_dmem_gnt     ,
input  wire        ram_dmem_recv    ,
output wire        ram_dmem_ack     ,
input  wire        ram_dmem_error   ,
input  wire [31:0] ram_dmem_rdata   ,

output wire        m0_awvalid       ,
input  wire        m0_awready       ,
output wire [31:0] m0_awaddr        ,
output wire [ 2:0] m0_awprot        ,
                                    
output wire        m0_wvalid        ,
input  wire        m0_wready        ,
output wire [31:0] m0_wdata         ,
output wire [ 3:0] m0_wstrb         ,
                                    
input  wire        m0_bvalid        ,
output wire        m0_bready        ,
input  wire [ 1:0] m0_bresp         ,
                                    
output wire        m0_arvalid       ,
input  wire        m0_arready       ,
output wire [31:0] m0_araddr        ,
output wire [ 2:0] m0_arprot        ,
                                    
input  wire        m0_rvalid        ,
output wire        m0_rready        ,
input  wire [ 1:0] m0_rresp         ,
input  wire [31:0] m0_rdata

);





parameter MAP_ROM_MATCH = 32'h1000_0000;
parameter MAP_ROM_MASK  = 32'hFFFF_C000;
parameter MAP_ROM_RANGE = 32'h0000_03FF;

parameter MAP_RAM_MATCH = 32'h2000_0000;
parameter MAP_RAM_MASK  = 32'hFFFF_0000;
parameter MAP_RAM_RANGE = 32'h0000_FFFF;

parameter MAP_AXI_MATCH = 32'h4000_0000;
parameter MAP_AXI_MASK  = 32'hF000_0000;
parameter MAP_AXI_RANGE = 32'h0FFF_FFFF;






parameter ENABLE_AXI_BRIDGE = 1;





wire ic_imem_error    ;
wire ic_imem_route_rom;
wire ic_imem_route_ram;
wire ic_imem_route_axi;

wire ic_dmem_error    ;
wire ic_dmem_route_rom;
wire ic_dmem_route_ram;
wire ic_dmem_route_axi;





assign ram_imem_req   = ic_imem_route_ram && cpu_imem_req;

assign ram_imem_wen   = cpu_imem_wen  ;
assign ram_imem_strb  = cpu_imem_strb ;
assign ram_imem_wdata = cpu_imem_wdata;
assign ram_imem_addr  = cpu_imem_addr ;

assign ram_imem_ack   = imem_rsp_mask_ram && cpu_imem_ack;





wire        err_imem_req    = ic_imem_error && cpu_imem_req;

wire        err_imem_gnt    ;
wire        err_imem_recv   ;
wire        err_imem_ack    = imem_rsp_mask_err && cpu_imem_ack;
wire        err_imem_error  ;
wire [31:0] err_imem_rdata  ;

ic_error_rsp_stub i_error_stub_imem (
.g_clk      (g_clk          ),
.g_resetn   (g_resetn       ),
.enable     (err_imem_req   ),
.mem_req    (err_imem_req   ),
.mem_gnt    (err_imem_gnt   ),
.mem_wen    ( 1'b0          ),
.mem_strb   ( 4'b0          ),
.mem_wdata  (32'b0          ),
.mem_addr   (32'b0          ),
.mem_recv   (err_imem_recv  ),
.mem_ack    (err_imem_ack   ),
.mem_error  (err_imem_error ),
.mem_rdata  (err_imem_rdata )
);





assign rom_imem_req   = ic_imem_route_rom && cpu_imem_req;

assign rom_imem_wen   = cpu_imem_wen  ;
assign rom_imem_strb  = cpu_imem_strb ;
assign rom_imem_wdata = cpu_imem_wdata;
assign rom_imem_addr  = cpu_imem_addr ;

assign rom_imem_ack   = imem_rsp_mask_rom && cpu_imem_ack;






assign ram_dmem_req   = ic_dmem_route_ram && cpu_dmem_req;

assign ram_dmem_wen   = cpu_dmem_wen  ;
assign ram_dmem_strb  = cpu_dmem_strb ;
assign ram_dmem_wdata = cpu_dmem_wdata;
assign ram_dmem_addr  = cpu_dmem_addr ;

assign ram_dmem_ack   = dmem_rsp_mask_ram && cpu_dmem_ack;





assign rom_dmem_req   = ic_dmem_route_rom && cpu_dmem_req;

assign rom_dmem_wen   = cpu_dmem_wen  ;
assign rom_dmem_strb  = cpu_dmem_strb ;
assign rom_dmem_wdata = cpu_dmem_wdata;
assign rom_dmem_addr  = cpu_dmem_addr ;

assign rom_dmem_ack   = dmem_rsp_mask_rom && cpu_dmem_ack;





wire        axi_dmem_req    = ic_dmem_route_axi && cpu_dmem_req;

wire        axi_dmem_gnt    ;
wire        axi_dmem_recv   ;
wire        axi_dmem_ack    = dmem_rsp_mask_axi && cpu_dmem_ack;
wire        axi_dmem_error  ;
wire [31:0] axi_dmem_rdata  ;

generate if(ENABLE_AXI_BRIDGE) begin

ic_cpu_bus_axi_bridge i_cpu_dmem_axi_bridge (
.m0_aclk         (g_clk           ),
.m0_aresetn      (g_resetn        ),
.m0_awvalid      (m0_awvalid      ),
.m0_awready      (m0_awready      ),
.m0_awaddr       (m0_awaddr       ),
.m0_awprot       (m0_awprot       ),
.m0_wvalid       (m0_wvalid       ),
.m0_wready       (m0_wready       ),
.m0_wdata        (m0_wdata        ),
.m0_wstrb        (m0_wstrb        ),
.m0_bvalid       (m0_bvalid       ),
.m0_bready       (m0_bready       ),
.m0_bresp        (m0_bresp        ),
.m0_arvalid      (m0_arvalid      ),
.m0_arready      (m0_arready      ),
.m0_araddr       (m0_araddr       ),
.m0_arprot       (m0_arprot       ),
.m0_rvalid       (m0_rvalid       ),
.m0_rready       (m0_rready       ),
.m0_rresp        (m0_rresp        ),
.m0_rdata        (m0_rdata        ),
.enable          (axi_dmem_req    ),
.mem_req         (axi_dmem_req    ),
.mem_gnt         (axi_dmem_gnt    ),
.mem_wen         (cpu_dmem_wen    ),
.mem_strb        (cpu_dmem_strb   ),
.mem_wdata       (cpu_dmem_wdata  ),
.mem_addr        (cpu_dmem_addr   ),
.mem_recv        (axi_dmem_recv   ),
.mem_ack         (axi_dmem_ack    ),
.mem_error       (axi_dmem_error  ),
.mem_rdata       (axi_dmem_rdata  )
);

end else begin


assign m0_awvalid = 0;
assign m0_awaddr  = 0;
assign m0_awprot  = 0;
assign m0_wvalid  = 0;
assign m0_wdata   = 0;
assign m0_wstrb   = 0;
assign m0_bready  = 0;
assign m0_arvalid = 0;
assign m0_araddr  = 0;
assign m0_arprot  = 0;
assign m0_rready  = 0;

ic_error_rsp_stub i_error_stub_axi (
.g_clk      (g_clk          ),
.g_resetn   (g_resetn       ),
.enable     (axi_dmem_req   ),
.mem_req    (axi_dmem_req   ),
.mem_gnt    (axi_dmem_gnt   ),
.mem_wen    ( 1'b0          ),
.mem_strb   ( 4'b0          ),
.mem_wdata  (32'b0          ),
.mem_addr   (32'b0          ),
.mem_recv   (axi_dmem_recv  ),
.mem_ack    (axi_dmem_ack   ),
.mem_error  (axi_dmem_error ),
.mem_rdata  (axi_dmem_rdata )
);

end endgenerate





wire        err_dmem_req    = ic_dmem_error && cpu_dmem_req;

wire        err_dmem_gnt    ;
wire        err_dmem_recv   ;
wire        err_dmem_ack    = dmem_rsp_mask_err && cpu_dmem_ack;
wire        err_dmem_error  ;
wire [31:0] err_dmem_rdata  ;

ic_error_rsp_stub i_error_stub_dmem (
.g_clk      (g_clk          ),
.g_resetn   (g_resetn       ),
.enable     (err_dmem_req   ),
.mem_req    (err_dmem_req   ),
.mem_gnt    (err_dmem_gnt   ),
.mem_wen    ( 1'b0          ),
.mem_strb   ( 4'b0          ),
.mem_wdata  (32'b0          ),
.mem_addr   (32'b0          ),
.mem_recv   (err_dmem_recv  ),
.mem_ack    (err_dmem_ack   ),
.mem_error  (err_dmem_error ),
.mem_rdata  (err_dmem_rdata )
);





assign cpu_imem_recv =
    imem_rsp_mask_rom && rom_imem_recv    ||
    imem_rsp_mask_ram && ram_imem_recv    ||
    imem_rsp_mask_err && err_imem_recv    ;

assign cpu_imem_error=
    imem_rsp_mask_rom && rom_imem_error   ||
    imem_rsp_mask_ram && ram_imem_error   ||
    imem_rsp_mask_err && err_imem_error   ;

assign cpu_imem_rdata=
    {32{imem_rsp_mask_rom}} & rom_imem_rdata   |
    {32{imem_rsp_mask_ram}} & ram_imem_rdata   ;

assign cpu_imem_gnt   = imem_req_ready && (
    ic_imem_route_ram && ram_imem_gnt ||
    ic_imem_route_rom && rom_imem_gnt ||
    ic_imem_error     && err_imem_gnt );

wire [2:0] imem_reqs = {
    rom_imem_req && rom_imem_gnt,
    ram_imem_req && ram_imem_gnt,
    err_imem_req && err_imem_gnt
};

wire [2:0] imem_rsps = {
    rom_imem_recv && cpu_imem_ack,
    ram_imem_recv && cpu_imem_ack,
    err_imem_recv && cpu_imem_ack
};

wire [2:0] imem_rsp_mask;
wire       imem_rsp_mask_rom = imem_rsp_mask[2];
wire       imem_rsp_mask_ram = imem_rsp_mask[1];
wire       imem_rsp_mask_err = imem_rsp_mask[0];
wire       imem_req_ready;

ic_rsp_tracker #(
.ND (3),
.MAX_REQUESTS(3)
) i_ic_rsp_tracker_imem (
.g_clk          (g_clk         ),
.g_resetn       (g_resetn      ),
.requests       (imem_reqs     ),
.responses      (imem_rsps     ),
.response_gnt   (imem_rsp_mask ),
.ready          (imem_req_ready)
);





assign cpu_dmem_recv =
    dmem_rsp_mask_rom  && rom_dmem_recv    ||
    dmem_rsp_mask_ram  && ram_dmem_recv    ||
    dmem_rsp_mask_axi  && axi_dmem_recv    ||
    dmem_rsp_mask_err  && err_dmem_recv    ;

assign cpu_dmem_error=
    dmem_rsp_mask_rom  && rom_dmem_error   ||
    dmem_rsp_mask_ram  && ram_dmem_error   ||
    dmem_rsp_mask_axi  && axi_dmem_error   ||
    dmem_rsp_mask_err  && err_dmem_error   ;

assign cpu_dmem_rdata=
    {32{dmem_rsp_mask_rom}} & rom_dmem_rdata   |
    {32{dmem_rsp_mask_axi}} & axi_dmem_rdata   |
    {32{dmem_rsp_mask_ram}} & ram_dmem_rdata   ;

assign cpu_dmem_gnt   = dmem_req_ready && (
    ic_dmem_route_ram && ram_dmem_gnt ||
    ic_dmem_route_rom && rom_dmem_gnt ||
    ic_dmem_route_axi && axi_dmem_gnt ||
    ic_dmem_error     && err_dmem_gnt );

wire [3:0] dmem_reqs = {
    rom_dmem_req && rom_dmem_gnt,
    ram_dmem_req && ram_dmem_gnt,
    axi_dmem_req && axi_dmem_gnt,
    err_dmem_req && err_dmem_gnt
};

wire [3:0] dmem_rsps = {
    rom_dmem_recv && cpu_dmem_ack,
    ram_dmem_recv && cpu_dmem_ack,
    axi_dmem_recv && cpu_dmem_ack,
    err_dmem_recv && cpu_dmem_ack
};

wire [3:0] dmem_rsp_mask;
wire       dmem_rsp_mask_rom = dmem_rsp_mask[3];
wire       dmem_rsp_mask_ram = dmem_rsp_mask[2];
wire       dmem_rsp_mask_axi = dmem_rsp_mask[1];
wire       dmem_rsp_mask_err = dmem_rsp_mask[0];
wire       dmem_req_ready;

ic_rsp_tracker #(
.ND (4),
.MAX_REQUESTS(3)
) i_ic_rsp_tracker_dmem (
.g_clk          (g_clk         ),
.g_resetn       (g_resetn      ),
.requests       (dmem_reqs     ),
.responses      (dmem_rsps     ),
.response_gnt   (dmem_rsp_mask ),
.ready          (dmem_req_ready)
);






ic_addr_decode #(
.MAP_ROM_MATCH(MAP_ROM_MATCH),
.MAP_ROM_MASK (MAP_ROM_MASK ),
.MAP_ROM_RANGE(MAP_ROM_RANGE),
.MAP_RAM_MATCH(MAP_RAM_MATCH),
.MAP_RAM_MASK (MAP_RAM_MASK ),
.MAP_RAM_RANGE(MAP_RAM_RANGE),
.MAP_AXI_MATCH(MAP_AXI_MATCH),
.MAP_AXI_MASK (MAP_AXI_MASK ),
.MAP_AXI_RANGE(MAP_AXI_RANGE) 
) ic_addr_decode_cpu_imem (
.g_clk        (g_clk            ),
.g_resetn     (g_resetn         ),
.req_valid    (cpu_imem_req     ),
.req_addr     (cpu_imem_addr    ),
.req_dec_err  (ic_imem_error    ),
.route_rom    (ic_imem_route_rom),
.route_ram    (ic_imem_route_ram),
.route_axi    (ic_imem_route_axi)
);


ic_addr_decode #(
.MAP_ROM_MATCH(MAP_ROM_MATCH),
.MAP_ROM_MASK (MAP_ROM_MASK ),
.MAP_ROM_RANGE(MAP_ROM_RANGE),
.MAP_RAM_MATCH(MAP_RAM_MATCH),
.MAP_RAM_MASK (MAP_RAM_MASK ),
.MAP_RAM_RANGE(MAP_RAM_RANGE),
.MAP_AXI_MATCH(MAP_AXI_MATCH),
.MAP_AXI_MASK (MAP_AXI_MASK ),
.MAP_AXI_RANGE(MAP_AXI_RANGE) 
) ic_addr_decode_cpu_dmem (
.g_clk        (g_clk            ),
.g_resetn     (g_resetn         ),
.req_valid    (cpu_dmem_req     ),
.req_addr     (cpu_dmem_addr    ),
.req_dec_err  (ic_dmem_error    ),
.route_rom    (ic_dmem_route_rom),
.route_ram    (ic_dmem_route_ram),
.route_axi    (ic_dmem_route_axi)
);

`ifdef FORMAL_IC_TOP

initial assume(!g_resetn);

always @(posedge g_clk) if(g_resetn && $past(g_resetn)) begin

    assert(!(imem_rsp_mask_err && imem_rsp_mask_rom));

    assert(!(imem_rsp_mask_err && imem_rsp_mask_ram));

    assert(!(imem_rsp_mask_ram && imem_rsp_mask_rom));

    assert(!(dmem_rsp_mask_err && dmem_rsp_mask_rom));

    assert(!(dmem_rsp_mask_err && dmem_rsp_mask_ram));

    assert(!(dmem_rsp_mask_ram && dmem_rsp_mask_rom));
    
    assert(!(dmem_rsp_mask_ram && dmem_rsp_mask_axi));
    
    assert(!(dmem_rsp_mask_err && dmem_rsp_mask_axi));
    
    assert(!(dmem_rsp_mask_rom && dmem_rsp_mask_axi));


    if($past(cpu_imem_recv) && !$past(cpu_imem_ack)) begin
        assert($stable(cpu_imem_recv ));
        assert($stable(cpu_imem_rdata));
        assert($stable(cpu_imem_error));
    end

    if($past(cpu_dmem_recv) && !$past(cpu_dmem_ack)) begin
        assert($stable(cpu_dmem_recv ));
        assert($stable(cpu_dmem_rdata));
        assert($stable(cpu_dmem_error));
    end

end

`endif

endmodule
module ic_top (

input  wire        g_clk            ,
input  wire        g_resetn         ,

input  wire        cpu_imem_req     ,
input  wire        cpu_imem_wen     ,
input  wire [ 3:0] cpu_imem_strb    ,
input  wire [31:0] cpu_imem_wdata   ,
input  wire [31:0] cpu_imem_addr    ,
output wire        cpu_imem_gnt     ,
output wire        cpu_imem_recv    ,
input  wire        cpu_imem_ack     ,
output wire        cpu_imem_error   ,
output wire [31:0] cpu_imem_rdata   ,

input  wire        cpu_dmem_req     ,
input  wire        cpu_dmem_wen     ,
input  wire [ 3:0] cpu_dmem_strb    ,
input  wire [31:0] cpu_dmem_wdata   ,
input  wire [31:0] cpu_dmem_addr    ,
output wire        cpu_dmem_gnt     ,
output wire        cpu_dmem_recv    ,
input  wire        cpu_dmem_ack     ,
output wire        cpu_dmem_error   ,
output wire [31:0] cpu_dmem_rdata   ,

output wire        rom_imem_req     ,
output wire        rom_imem_wen     ,
output wire [ 3:0] rom_imem_strb    ,
output wire [31:0] rom_imem_wdata   ,
output wire [31:0] rom_imem_addr    ,
input  wire        rom_imem_gnt     ,
input  wire        rom_imem_recv    ,
output wire        rom_imem_ack     ,
input  wire        rom_imem_error   ,
input  wire [31:0] rom_imem_rdata   ,

output wire        ram_imem_req     ,
output wire        ram_imem_wen     ,
output wire [ 3:0] ram_imem_strb    ,
output wire [31:0] ram_imem_wdata   ,
output wire [31:0] ram_imem_addr    ,
input  wire        ram_imem_gnt     ,
input  wire        ram_imem_recv    ,
output wire        ram_imem_ack     ,
input  wire        ram_imem_error   ,
input  wire [31:0] ram_imem_rdata   ,

output wire        rom_dmem_req     ,
output wire        rom_dmem_wen     ,
output wire [ 3:0] rom_dmem_strb    ,
output wire [31:0] rom_dmem_wdata   ,
output wire [31:0] rom_dmem_addr    ,
input  wire        rom_dmem_gnt     ,
input  wire        rom_dmem_recv    ,
output wire        rom_dmem_ack     ,
input  wire        rom_dmem_error   ,
input  wire [31:0] rom_dmem_rdata   ,

output wire        ram_dmem_req     ,
output wire        ram_dmem_wen     ,
output wire [ 3:0] ram_dmem_strb    ,
output wire [31:0] ram_dmem_wdata   ,
output wire [31:0] ram_dmem_addr    ,
input  wire        ram_dmem_gnt     ,
input  wire        ram_dmem_recv    ,
output wire        ram_dmem_ack     ,
input  wire        ram_dmem_error   ,
input  wire [31:0] ram_dmem_rdata   ,

output wire        m0_awvalid       ,
input  wire        m0_awready       ,
output wire [31:0] m0_awaddr        ,
output wire [ 2:0] m0_awprot        ,
                                    
output wire        m0_wvalid        ,
input  wire        m0_wready        ,
output wire [31:0] m0_wdata         ,
output wire [ 3:0] m0_wstrb         ,
                                    
input  wire        m0_bvalid        ,
output wire        m0_bready        ,
input  wire [ 1:0] m0_bresp         ,
                                    
output wire        m0_arvalid       ,
input  wire        m0_arready       ,
output wire [31:0] m0_araddr        ,
output wire [ 2:0] m0_arprot        ,
                                    
input  wire        m0_rvalid        ,
output wire        m0_rready        ,
input  wire [ 1:0] m0_rresp         ,
input  wire [31:0] m0_rdata

);






parameter MAP_ROM_MATCH = 32'h1000_0000;
parameter MAP_ROM_MASK  = 32'hFFFF_C000;
parameter MAP_ROM_RANGE = 32'h0000_03FF;

parameter MAP_RAM_MATCH = 32'h2000_0000;
parameter MAP_RAM_MASK  = 32'hFFFF_0000;
parameter MAP_RAM_RANGE = 32'h0000_FFFF;

parameter MAP_AXI_MATCH = 32'h4000_0000;
parameter MAP_AXI_MASK  = 32'hF000_0000;
parameter MAP_AXI_RANGE = 32'h0FFF_FFFF;






parameter ENABLE_AXI_BRIDGE = 1;





wire ic_imem_error    ;
wire ic_imem_route_rom;
wire ic_imem_route_ram;
wire ic_imem_route_axi;

wire ic_dmem_error    ;
wire ic_dmem_route_rom;
wire ic_dmem_route_ram;
wire ic_dmem_route_axi;





assign ram_imem_req   = ic_imem_route_ram && cpu_imem_req;

assign ram_imem_wen   = cpu_imem_wen  ;
assign ram_imem_strb  = cpu_imem_strb ;
assign ram_imem_wdata = cpu_imem_wdata;
assign ram_imem_addr  = cpu_imem_addr ;

assign ram_imem_ack   = imem_rsp_mask_ram && cpu_imem_ack;





wire        err_imem_req    = ic_imem_error && cpu_imem_req;

wire        err_imem_gnt    ;
wire        err_imem_recv   ;
wire        err_imem_ack    = imem_rsp_mask_err && cpu_imem_ack;
wire        err_imem_error  ;
wire [31:0] err_imem_rdata  ;

ic_error_rsp_stub i_error_stub_imem (
.g_clk      (g_clk          ),
.g_resetn   (g_resetn       ),
.enable     (err_imem_req   ),
.mem_req    (err_imem_req   ),
.mem_gnt    (err_imem_gnt   ),
.mem_wen    ( 1'b0          ),
.mem_strb   ( 4'b0          ),
.mem_wdata  (32'b0          ),
.mem_addr   (32'b0          ),
.mem_recv   (err_imem_recv  ),
.mem_ack    (err_imem_ack   ),
.mem_error  (err_imem_error ),
.mem_rdata  (err_imem_rdata )
);





assign rom_imem_req   = ic_imem_route_rom && cpu_imem_req;

assign rom_imem_wen   = cpu_imem_wen  ;
assign rom_imem_strb  = cpu_imem_strb ;
assign rom_imem_wdata = cpu_imem_wdata;
assign rom_imem_addr  = cpu_imem_addr ;

assign rom_imem_ack   = imem_rsp_mask_rom && cpu_imem_ack;






assign ram_dmem_req   = ic_dmem_route_ram && cpu_dmem_req;

assign ram_dmem_wen   = cpu_dmem_wen  ;
assign ram_dmem_strb  = cpu_dmem_strb ;
assign ram_dmem_wdata = cpu_dmem_wdata;
assign ram_dmem_addr  = cpu_dmem_addr ;

assign ram_dmem_ack   = dmem_rsp_mask_ram && cpu_dmem_ack;





assign rom_dmem_req   = ic_dmem_route_rom && cpu_dmem_req;

assign rom_dmem_wen   = cpu_dmem_wen  ;
assign rom_dmem_strb  = cpu_dmem_strb ;
assign rom_dmem_wdata = cpu_dmem_wdata;
assign rom_dmem_addr  = cpu_dmem_addr ;

assign rom_dmem_ack   = dmem_rsp_mask_rom && cpu_dmem_ack;





wire        axi_dmem_req    = ic_dmem_route_axi && cpu_dmem_req;

wire        axi_dmem_gnt    ;
wire        axi_dmem_recv   ;
wire        axi_dmem_ack    = dmem_rsp_mask_axi && cpu_dmem_ack;
wire        axi_dmem_error  ;
wire [31:0] axi_dmem_rdata  ;

generate if(ENABLE_AXI_BRIDGE) begin

ic_cpu_bus_axi_bridge i_cpu_dmem_axi_bridge (
.m0_aclk         (g_clk           ),
.m0_aresetn      (g_resetn        ),
.m0_awvalid      (m0_awvalid      ),
.m0_awready      (m0_awready      ),
.m0_awaddr       (m0_awaddr       ),
.m0_awprot       (m0_awprot       ),
.m0_wvalid       (m0_wvalid       ),
.m0_wready       (m0_wready       ),
.m0_wdata        (m0_wdata        ),
.m0_wstrb        (m0_wstrb        ),
.m0_bvalid       (m0_bvalid       ),
.m0_bready       (m0_bready       ),
.m0_bresp        (m0_bresp        ),
.m0_arvalid      (m0_arvalid      ),
.m0_arready      (m0_arready      ),
.m0_araddr       (m0_araddr       ),
.m0_arprot       (m0_arprot       ),
.m0_rvalid       (m0_rvalid       ),
.m0_rready       (m0_rready       ),
.m0_rresp        (m0_rresp        ),
.m0_rdata        (m0_rdata        ),
.enable          (axi_dmem_req    ),
.mem_req         (axi_dmem_req    ),
.mem_gnt         (axi_dmem_gnt    ),
.mem_wen         (cpu_dmem_wen    ),
.mem_strb        (cpu_dmem_strb   ),
.mem_wdata       (cpu_dmem_wdata  ),
.mem_addr        (cpu_dmem_addr   ),
.mem_recv        (axi_dmem_recv   ),
.mem_ack         (axi_dmem_ack    ),
.mem_error       (axi_dmem_error  ),
.mem_rdata       (axi_dmem_rdata  )
);

end else begin


assign m0_awvalid = 0;
assign m0_awaddr  = 0;
assign m0_awprot  = 0;
assign m0_wvalid  = 0;
assign m0_wdata   = 0;
assign m0_wstrb   = 0;
assign m0_bready  = 0;
assign m0_arvalid = 0;
assign m0_araddr  = 0;
assign m0_arprot  = 0;
assign m0_rready  = 0;

ic_error_rsp_stub i_error_stub_axi (
.g_clk      (g_clk          ),
.g_resetn   (g_resetn       ),
.enable     (axi_dmem_req   ),
.mem_req    (axi_dmem_req   ),
.mem_gnt    (axi_dmem_gnt   ),
.mem_wen    ( 1'b0          ),
.mem_strb   ( 4'b0          ),
.mem_wdata  (32'b0          ),
.mem_addr   (32'b0          ),
.mem_recv   (axi_dmem_recv  ),
.mem_ack    (axi_dmem_ack   ),
.mem_error  (axi_dmem_error ),
.mem_rdata  (axi_dmem_rdata )
);

end endgenerate





wire        err_dmem_req    = ic_dmem_error && cpu_dmem_req;

wire        err_dmem_gnt    ;
wire        err_dmem_recv   ;
wire        err_dmem_ack    = dmem_rsp_mask_err && cpu_dmem_ack;
wire        err_dmem_error  ;
wire [31:0] err_dmem_rdata  ;

ic_error_rsp_stub i_error_stub_dmem (
.g_clk      (g_clk          ),
.g_resetn   (g_resetn       ),
.enable     (err_dmem_req   ),
.mem_req    (err_dmem_req   ),
.mem_gnt    (err_dmem_gnt   ),
.mem_wen    ( 1'b0          ),
.mem_strb   ( 4'b0          ),
.mem_wdata  (32'b0          ),
.mem_addr   (32'b0          ),
.mem_recv   (err_dmem_recv  ),
.mem_ack    (err_dmem_ack   ),
.mem_error  (err_dmem_error ),
.mem_rdata  (err_dmem_rdata )
);





assign cpu_imem_recv =
    imem_rsp_mask_rom && rom_imem_recv    ||
    imem_rsp_mask_ram && ram_imem_recv    ||
    imem_rsp_mask_err && err_imem_recv    ;

assign cpu_imem_error=
    imem_rsp_mask_rom && rom_imem_error   ||
    imem_rsp_mask_ram && ram_imem_error   ||
    imem_rsp_mask_err && err_imem_error   ;

assign cpu_imem_rdata=
    {32{imem_rsp_mask_rom}} & rom_imem_rdata   |
    {32{imem_rsp_mask_ram}} & ram_imem_rdata   ;

assign cpu_imem_gnt   = imem_req_ready && (
    ic_imem_route_ram && ram_imem_gnt ||
    ic_imem_route_rom && rom_imem_gnt ||
    ic_imem_error     && err_imem_gnt );

wire [2:0] imem_reqs = {
    rom_imem_req && rom_imem_gnt,
    ram_imem_req && ram_imem_gnt,
    err_imem_req && err_imem_gnt
};

wire [2:0] imem_rsps = {
    rom_imem_recv && cpu_imem_ack,
    ram_imem_recv && cpu_imem_ack,
    err_imem_recv && cpu_imem_ack
};

wire [2:0] imem_rsp_mask;
wire       imem_rsp_mask_rom = imem_rsp_mask[2];
wire       imem_rsp_mask_ram = imem_rsp_mask[1];
wire       imem_rsp_mask_err = imem_rsp_mask[0];
wire       imem_req_ready;

ic_rsp_tracker #(
.ND (3),
.MAX_REQUESTS(3)
) i_ic_rsp_tracker_imem (
.g_clk          (g_clk         ),
.g_resetn       (g_resetn      ),
.requests       (imem_reqs     ),
.responses      (imem_rsps     ),
.response_gnt   (imem_rsp_mask ),
.ready          (imem_req_ready)
);





assign cpu_dmem_recv =
    dmem_rsp_mask_rom  && rom_dmem_recv    ||
    dmem_rsp_mask_ram  && ram_dmem_recv    ||
    dmem_rsp_mask_axi  && axi_dmem_recv    ||
    dmem_rsp_mask_err  && err_dmem_recv    ;

assign cpu_dmem_error=
    dmem_rsp_mask_rom  && rom_dmem_error   ||
    dmem_rsp_mask_ram  && ram_dmem_error   ||
    dmem_rsp_mask_axi  && axi_dmem_error   ||
    dmem_rsp_mask_err  && err_dmem_error   ;

assign cpu_dmem_rdata=
    {32{dmem_rsp_mask_rom}} & rom_dmem_rdata   |
    {32{dmem_rsp_mask_axi}} & axi_dmem_rdata   |
    {32{dmem_rsp_mask_ram}} & ram_dmem_rdata   ;

assign cpu_dmem_gnt   = dmem_req_ready && (
    ic_dmem_route_ram && ram_dmem_gnt ||
    ic_dmem_route_rom && rom_dmem_gnt ||
    ic_dmem_route_axi && axi_dmem_gnt ||
    ic_dmem_error     && err_dmem_gnt );

wire [3:0] dmem_reqs = {
    rom_dmem_req && rom_dmem_gnt,
    ram_dmem_req && ram_dmem_gnt,
    axi_dmem_req && axi_dmem_gnt,
    err_dmem_req && err_dmem_gnt
};

wire [3:0] dmem_rsps = {
    rom_dmem_recv && cpu_dmem_ack,
    ram_dmem_recv && cpu_dmem_ack,
    axi_dmem_recv && cpu_dmem_ack,
    err_dmem_recv && cpu_dmem_ack
};

wire [3:0] dmem_rsp_mask;
wire       dmem_rsp_mask_rom = dmem_rsp_mask[3];
wire       dmem_rsp_mask_ram = dmem_rsp_mask[2];
wire       dmem_rsp_mask_axi = dmem_rsp_mask[1];
wire       dmem_rsp_mask_err = dmem_rsp_mask[0];
wire       dmem_req_ready;

ic_rsp_tracker #(
.ND (4),
.MAX_REQUESTS(3)
) i_ic_rsp_tracker_dmem (
.g_clk          (g_clk         ),
.g_resetn       (g_resetn      ),
.requests       (dmem_reqs     ),
.responses      (dmem_rsps     ),
.response_gnt   (dmem_rsp_mask ),
.ready          (dmem_req_ready)
);






ic_addr_decode #(
.MAP_ROM_MATCH(MAP_ROM_MATCH),
.MAP_ROM_MASK (MAP_ROM_MASK ),
.MAP_ROM_RANGE(MAP_ROM_RANGE),
.MAP_RAM_MATCH(MAP_RAM_MATCH),
.MAP_RAM_MASK (MAP_RAM_MASK ),
.MAP_RAM_RANGE(MAP_RAM_RANGE),
.MAP_AXI_MATCH(MAP_AXI_MATCH),
.MAP_AXI_MASK (MAP_AXI_MASK ),
.MAP_AXI_RANGE(MAP_AXI_RANGE) 
) ic_addr_decode_cpu_imem (
.g_clk        (g_clk            ),
.g_resetn     (g_resetn         ),
.req_valid    (cpu_imem_req     ),
.req_addr     (cpu_imem_addr    ),
.req_dec_err  (ic_imem_error    ),
.route_rom    (ic_imem_route_rom),
.route_ram    (ic_imem_route_ram),
.route_axi    (ic_imem_route_axi)
);


ic_addr_decode #(
.MAP_ROM_MATCH(MAP_ROM_MATCH),
.MAP_ROM_MASK (MAP_ROM_MASK ),
.MAP_ROM_RANGE(MAP_ROM_RANGE),
.MAP_RAM_MATCH(MAP_RAM_MATCH),
.MAP_RAM_MASK (MAP_RAM_MASK ),
.MAP_RAM_RANGE(MAP_RAM_RANGE),
.MAP_AXI_MATCH(MAP_AXI_MATCH),
.MAP_AXI_MASK (MAP_AXI_MASK ),
.MAP_AXI_RANGE(MAP_AXI_RANGE) 
) ic_addr_decode_cpu_dmem (
.g_clk        (g_clk            ),
.g_resetn     (g_resetn         ),
.req_valid    (cpu_dmem_req     ),
.req_addr     (cpu_dmem_addr    ),
.req_dec_err  (ic_dmem_error    ),
.route_rom    (ic_dmem_route_rom),
.route_ram    (ic_dmem_route_ram),
.route_axi    (ic_dmem_route_axi)
);

`ifdef FORMAL_IC_TOP

initial assume(!g_resetn);

always @(posedge g_clk) if(g_resetn && $past(g_resetn)) begin

    assert(!(imem_rsp_mask_err && imem_rsp_mask_rom));

    assert(!(imem_rsp_mask_err && imem_rsp_mask_ram));

    assert(!(imem_rsp_mask_ram && imem_rsp_mask_rom));

    assert(!(dmem_rsp_mask_err && dmem_rsp_mask_rom));

    assert(!(dmem_rsp_mask_err && dmem_rsp_mask_ram));

    assert(!(dmem_rsp_mask_ram && dmem_rsp_mask_rom));
    
    assert(!(dmem_rsp_mask_ram && dmem_rsp_mask_axi));
    
    assert(!(dmem_rsp_mask_err && dmem_rsp_mask_axi));
    
    assert(!(dmem_rsp_mask_rom && dmem_rsp_mask_axi));


    if($past(cpu_imem_recv) && !$past(cpu_imem_ack)) begin
        assert($stable(cpu_imem_recv ));
        assert($stable(cpu_imem_rdata));
        assert($stable(cpu_imem_error));
    end

    if($past(cpu_dmem_recv) && !$past(cpu_dmem_ack)) begin
        assert($stable(cpu_dmem_recv ));
        assert($stable(cpu_dmem_rdata));
        assert($stable(cpu_dmem_error));
    end

end

`endif

endmodule