data/full_repos/permissive/169848838/prj/tb/ram_16k_tb.v
data/verilator_xmls/879cee81-6ced-4c17-a5fe-8873377b7033.xml
module ram_16k_tb(
	input					clk,
	input		[13:0]		adr,
	input		[7:0]		data,
	output		[7:0]		q,
	input					we,
	input					en
);


	reg		[7:0]	Mem	[0:16383];




	always @(posedge clk)
		if (en&&we)
			Mem[adr] <= data;


	assign q = (en && ~we)?Mem[adr]:8'bz;

endmodule
module ram_16k_tb(
	input					clk,
	input		[13:0]		adr,
	input		[7:0]		data,
	output		[7:0]		q,
	input					we,
	input					en
);



	reg		[7:0]	Mem	[0:16383];




	always @(posedge clk)
		if (en&&we)
			Mem[adr] <= data;


	assign q = (en && ~we)?Mem[adr]:8'bz;

endmodule