data/full_repos/permissive/105546923/infra/hdl/uart_ctrl.v
None: at end of input
1: b'%Error: data/full_repos/permissive/105546923/infra/hdl/uart_ctrl.v:1: Cannot find include file: uart.vh\n`include "uart.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh\n             data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh.v\n             data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/uart.vh.sv\n             uart.vh\n             uart.vh.v\n             uart.vh.sv\n             obj_dir/uart.vh\n             obj_dir/uart.vh.v\n             obj_dir/uart.vh.sv\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_ctrl.v:7: Define or directive not defined: \'`UART_DATA_LENGTH\'\n   output [`UART_DATA_LENGTH - 1 : 0] rx_o,\n           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/uart_ctrl.v:9: Define or directive not defined: \'`UART_DATA_LENGTH\'\n   input [`UART_DATA_LENGTH - 1 : 0]  tx_i,\n          ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module uart_ctrl(
		 input 				    clk_rx_i,
		 input 				    clk_tx_i,
		 input 				    rx_i,
		 output [`UART_DATA_LENGTH - 1 : 0] rx_o,
		 output 			    rx_o_v,
		 input [`UART_DATA_LENGTH - 1 : 0]  tx_i,
		 input 				    tx_i_v,
		 output 			    tx_o,
		 output 			    tx_o_v 			    
		 );

   uart_rx uart_rx(
		   .clk_i(clk_rx_i),
		   .rx_i(rx_i),
		   .tx_o(rx_o),
		   .tx_o_v(rx_o_v)
		   );
   
   uart_tx uart_tx(
		   .clk_i (clk_tx_i),
		   .rx_i (tx_i),
		   .rx_i_v (tx_i_v),
		   .tx_o (tx_o),
		   .tx_o_v (tx_o_v)
		   );
   
endmodule
module uart_ctrl(
		 input 				    clk_rx_i,
		 input 				    clk_tx_i,
		 input 				    rx_i,
		 output [`UART_DATA_LENGTH - 1 : 0] rx_o,
		 output 			    rx_o_v,
		 input [`UART_DATA_LENGTH - 1 : 0]  tx_i,
		 input 				    tx_i_v,
		 output 			    tx_o,
		 output 			    tx_o_v 			    
		 );


   uart_rx uart_rx(
		   .clk_i(clk_rx_i),
		   .rx_i(rx_i),
		   .tx_o(rx_o),
		   .tx_o_v(rx_o_v)
		   );
   
   uart_tx uart_tx(
		   .clk_i (clk_tx_i),
		   .rx_i (tx_i),
		   .rx_i_v (tx_i_v),
		   .tx_o (tx_o),
		   .tx_o_v (tx_o_v)
		   );
   
endmodule