data/full_repos/permissive/193759799/src/ALU.v
data/verilator_xmls/5d40229b-aad1-4b0e-8525-9c318ead257a.xml
module ALU (
  input       [31:0] MuxOutA, MuxOutB,
  input  wire [3:0]  ALUCtrlOut,
  output reg  [31:0] ALUOut,
  output reg         Overflow
  );

  always @(*)
  begin
    case (ALUCtrlOut)
      4'b0000:            ALUOut  <= MuxOutA & MuxOutB;
      4'b0000:            ALUOut  <= MuxOutA & MuxOutB;
      4'b0001: {Overflow, ALUOut} <= MuxOutA + MuxOutB;
      4'b0001: {Overflow, ALUOut} <= MuxOutA + MuxOutB;
      4'b0010: {Overflow, ALUOut} <= MuxOutA - MuxOutB;
      4'b0011:            ALUOut  <= MuxOutA | MuxOutB;
      4'b0101:            ALUOut  <= MuxOutB << MuxOutA;
      4'b0110:            ALUOut  <= $unsigned (MuxOutB) >>  MuxOutA;
      4'b1000:            ALUOut  <= $signed   (MuxOutB) >>> MuxOutA;
      4'b1001:            ALUOut  <= MuxOutA < MuxOutB ? 1 : 0;
    endcase
  end

endmodule
module ALU (
  input       [31:0] MuxOutA, MuxOutB,
  input  wire [3:0]  ALUCtrlOut,
  output reg  [31:0] ALUOut,
  output reg         Overflow
  );


  always @(*)
  begin
    case (ALUCtrlOut)
      4'b0000:            ALUOut  <= MuxOutA & MuxOutB;
      4'b0000:            ALUOut  <= MuxOutA & MuxOutB;
      4'b0001: {Overflow, ALUOut} <= MuxOutA + MuxOutB;
      4'b0001: {Overflow, ALUOut} <= MuxOutA + MuxOutB;
      4'b0010: {Overflow, ALUOut} <= MuxOutA - MuxOutB;
      4'b0011:            ALUOut  <= MuxOutA | MuxOutB;
      4'b0101:            ALUOut  <= MuxOutB << MuxOutA;
      4'b0110:            ALUOut  <= $unsigned (MuxOutB) >>  MuxOutA;
      4'b1000:            ALUOut  <= $signed   (MuxOutB) >>> MuxOutA;
      4'b1001:            ALUOut  <= MuxOutA < MuxOutB ? 1 : 0;
    endcase
  end

endmodule