data/full_repos/permissive/132220215/testbenches/d_ff_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/132220215/testbenches/d_ff_tb.v:2: Cannot find include file: ../clock_gen.v\n`include "../clock_gen.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../clock_gen.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../clock_gen.v.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../clock_gen.v.sv\n             ../clock_gen.v\n             ../clock_gen.v.v\n             ../clock_gen.v.sv\n             obj_dir/../clock_gen.v\n             obj_dir/../clock_gen.v.v\n             obj_dir/../clock_gen.v.sv\n%Error: data/full_repos/permissive/132220215/testbenches/d_ff_tb.v:3: Cannot find include file: ../d_ff.v\n`include "../d_ff.v" \n         ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/d_ff_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n         #80 D_sig <= ~D_sig;              \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/132220215/testbenches/d_ff_tb.v:21: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("D_FF.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/132220215/testbenches/d_ff_tb.v:22: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,D_FF_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/d_ff_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #150 $finish;\n  ^\n%Error: data/full_repos/permissive/132220215/testbenches/d_ff_tb.v:33: Unsupported or unknown PLI call: $monitor\n $monitor(" Sim. Time: %g D : %b, clk : %b, Q : %b.",$time,D_sig,clk_sig,Q_inp); \n ^~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module D_FF_tb;

 output reg D_sig;
 wire clk_sig;
 input Q_inp;

 D_FF DFF0(.D(D_sig),.clk(clk_sig),.Q(Q_inp));
 clock CLK0(.out(clk_sig));

 initial
 begin

         D_sig <= 1'b0;       

         #80 D_sig <= ~D_sig;              
	 $dumpfile("D_FF.vcd");
	 $dumpvars(0,D_FF_tb);
	 #150 $finish;
 end



	
	


 initial
	$monitor(" Sim. Time: %g D : %b, clk : %b, Q : %b.",$time,D_sig,clk_sig,Q_inp); 

endmodule
module D_FF_tb;


 output reg D_sig;
 wire clk_sig;
 input Q_inp;

 D_FF DFF0(.D(D_sig),.clk(clk_sig),.Q(Q_inp));
 clock CLK0(.out(clk_sig));

 initial
 begin

         D_sig <= 1'b0;       

         #80 D_sig <= ~D_sig;              
	 $dumpfile("D_FF.vcd");
	 $dumpvars(0,D_FF_tb);
	 #150 $finish;
 end



	
	


 initial
	$monitor(" Sim. Time: %g D : %b, clk : %b, Q : %b.",$time,D_sig,clk_sig,Q_inp); 

endmodule