data/full_repos/permissive/128566293/Sources/verilog/VfD_shiftreg.v
data/verilator_xmls/043edfd7-8bfb-458c-bcde-5c83d4cda715.xml
module VfD_shiftreg (

    input           i_enable,
    output [4:0]    o_result,

    input           clk,
    input           rst
);



    reg [4:0]       r_shiftreg;

always @ (posedge rst or posedge clk)
begin
    if (rst)

        r_shiftreg <= 0;
    else

        if (i_enable)
            r_shiftreg <= {i_enable, r_shiftreg[4:1]};
end

assign o_result = r_shiftreg;

endmodule
module VfD_shiftreg (

    input           i_enable,
    output [4:0]    o_result,

    input           clk,
    input           rst
);




    reg [4:0]       r_shiftreg;

always @ (posedge rst or posedge clk)
begin
    if (rst)

        r_shiftreg <= 0;
    else

        if (i_enable)
            r_shiftreg <= {i_enable, r_shiftreg[4:1]};
end

assign o_result = r_shiftreg;

endmodule