data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:146: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:160: Unsupported: Ignoring delay on this delayed statement.\n   #8;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:162: Unsupported: Ignoring delay on this delayed statement.\n   #8;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:164: Unsupported: Ignoring delay on this delayed statement.\n   #8;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #4;\n  ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'write_clock\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'read_clock\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'sync_read_address\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'channel\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'start_read_address\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'end_read_address\'\n ) fg (\n   ^~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:111: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                       : ... Top module \'sequencer_sync\'\nmodule sequencer_sync #(\n       ^~~~~~~~~~~~~~\n                                                                                       : ... Top module \'function_generator_tb\'\nmodule function_generator_tb;\n       ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:129: Pin not found: \'clock\'\n  .clock(clock),\n   ^~~~~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sequencer_sync #(
	parameter ADDRESS_DEPTH_OSERDES = 16,
	parameter LOG2_OF_OSERDES_DATA_WIDTH = 3,
	parameter SYNC_OUT_STREAM_PICKOFF = 2
) (
	input clock, reset,
	input sync_read_address,
	input [31:0] start_sample,
	input [31:0] end_sample,
	output reg [ADDRESS_DEPTH_OSERDES-1:0] read_address = 0,
	output reg [SYNC_OUT_STREAM_PICKOFF:0] sync_out_stream = 0,
	output [7:0] sync_out_word
);
	reg [ADDRESS_DEPTH_OSERDES-1:0] last_read_address = 14'd4095;
	reg sync_out_raw = 0;
	always @(posedge clock) begin
		sync_out_raw <= 0;
		if (reset) begin
			read_address <= start_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH];
			last_read_address <= end_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH] - 1'b1;
			sync_out_stream <= 0;
		end else begin
			if (read_address==last_read_address || sync_read_address) begin
				read_address <= start_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH];
				last_read_address <= end_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH] - 1'b1;
				sync_out_raw <= 1;
			end else begin
				read_address <= read_address + 1'b1;
			end
			sync_out_stream <= { sync_out_stream[SYNC_OUT_STREAM_PICKOFF-1:0], sync_out_raw };
		end
	end
	assign sync_out_word = { sync_out_stream[1], 7'b0 };
endmodule
module sequencer_sync #(
	parameter ADDRESS_DEPTH_OSERDES = 16,
	parameter LOG2_OF_OSERDES_DATA_WIDTH = 3,
	parameter SYNC_OUT_STREAM_PICKOFF = 2
) (
	input clock, reset,
	input sync_read_address,
	input [31:0] start_sample,
	input [31:0] end_sample,
	output reg [ADDRESS_DEPTH_OSERDES-1:0] read_address = 0,
	output reg [SYNC_OUT_STREAM_PICKOFF:0] sync_out_stream = 0,
	output [7:0] sync_out_word
);

	reg [ADDRESS_DEPTH_OSERDES-1:0] last_read_address = 14'd4095;
	reg sync_out_raw = 0;
	always @(posedge clock) begin
		sync_out_raw <= 0;
		if (reset) begin
			read_address <= start_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH];
			last_read_address <= end_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH] - 1'b1;
			sync_out_stream <= 0;
		end else begin
			if (read_address==last_read_address || sync_read_address) begin
				read_address <= start_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH];
				last_read_address <= end_sample[ADDRESS_DEPTH_OSERDES-1:LOG2_OF_OSERDES_DATA_WIDTH] - 1'b1;
				sync_out_raw <= 1;
			end else begin
				read_address <= read_address + 1'b1;
			end
			sync_out_stream <= { sync_out_stream[SYNC_OUT_STREAM_PICKOFF-1:0], sync_out_raw };
		end
	end
	assign sync_out_word = { sync_out_stream[1], 7'b0 };
endmodule