data/full_repos/permissive/156609923/fifo/testbench.v
 line:137: before: "$"
1: b'%Error: data/full_repos/permissive/156609923/fifo/testbench.v:2: Cannot find include file: probador.v\n`include"probador.v" \n        ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156609923/fifo,data/full_repos/permissive/156609923/probador.v\n             data/full_repos/permissive/156609923/fifo,data/full_repos/permissive/156609923/probador.v.v\n             data/full_repos/permissive/156609923/fifo,data/full_repos/permissive/156609923/probador.v.sv\n             probador.v\n             probador.v.v\n             probador.v.sv\n             obj_dir/probador.v\n             obj_dir/probador.v.v\n             obj_dir/probador.v.sv\n%Error: data/full_repos/permissive/156609923/fifo/testbench.v:3: Cannot find include file: fifo.v\n`include "fifo.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/156609923/fifo/testbench.v:4: Cannot find include file: fifoSynth.v\n`include "fifoSynth.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156609923/fifo/testbench.v:5: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module testbench();
   parameter ADDR_WIDTH = 3;
   parameter BUS_SIZE = 5;

   parameter MEM_LENGTH = 1 << ADDR_WIDTH;
   


   wire			clk;
   wire			continua;
   wire [BUS_SIZE-1:0]	data_in;
   wire [BUS_SIZE-1:0]	data_out;
   wire			empty;
   wire			pause;
   wire			pop;
   wire			push;
   wire			reset;
   wire			valid;
wire			valid_out;
   wire			valid_outE;
   wire [BUS_SIZE-1:0]	data_outE;
   wire			emptyE;
   wire			pauseE;
   wire			continuaE;

   fifo each (

	      .pause			(pause),
	      .continua			(continua),
	      .empty			(empty),
	      .data_out			(data_out[BUS_SIZE-1:0]),
	      .valid_out(valid_out),

	      .clk			(clk),
	      .reset			(reset),
	      .pop			(pop),
	      .push			(push),
	      .data_in			(data_in[BUS_SIZE-1:0]),
	      .valid (valid));
   
    fifoSynth eachSynth (

	      .pause			(pauseE),
	      .continua			(continuaE),
	      .empty			(emptyE),
	      .data_out			(data_outE[BUS_SIZE-1:0]),
			 .valid_out(valid_outE),		 

	      .clk			(clk),
	      .reset			(reset),
	      .pop			(pop),
	      .push			(push),
	      .data_in			(data_in[BUS_SIZE-1:0]),
	      .valid (valid));    
   
   probador prob(

		 .clk			(clk),
		 .reset			(reset),
		 .push			(push),
		 .pop			(pop),
		 .data_in		(data_in[BUS_SIZE-1:0]),
		 .valid			(valid),

		 .empty			(empty),
		 .data_out_cond		(data_out[BUS_SIZE-1:0]),
		 .continua		(continua),
		 .pause			(pause),
		 .valid_out(valid_out),

		 .data_out_synth (data_outE),
		 .continua_syn		(continuaE),
		 .pause_syn			(pause),
		 .valid_out_syn(valid_outE),
		 .empty_syn		(emptyE)
		 
);
   
   endmodule
module testbench();

   parameter ADDR_WIDTH = 3;
   parameter BUS_SIZE = 5;

   parameter MEM_LENGTH = 1 << ADDR_WIDTH;
   


   wire			clk;
   wire			continua;
   wire [BUS_SIZE-1:0]	data_in;
   wire [BUS_SIZE-1:0]	data_out;
   wire			empty;
   wire			pause;
   wire			pop;
   wire			push;
   wire			reset;
   wire			valid;
wire			valid_out;
   wire			valid_outE;
   wire [BUS_SIZE-1:0]	data_outE;
   wire			emptyE;
   wire			pauseE;
   wire			continuaE;

   fifo each (

	      .pause			(pause),
	      .continua			(continua),
	      .empty			(empty),
	      .data_out			(data_out[BUS_SIZE-1:0]),
	      .valid_out(valid_out),

	      .clk			(clk),
	      .reset			(reset),
	      .pop			(pop),
	      .push			(push),
	      .data_in			(data_in[BUS_SIZE-1:0]),
	      .valid (valid));
   
    fifoSynth eachSynth (

	      .pause			(pauseE),
	      .continua			(continuaE),
	      .empty			(emptyE),
	      .data_out			(data_outE[BUS_SIZE-1:0]),
			 .valid_out(valid_outE),		 

	      .clk			(clk),
	      .reset			(reset),
	      .pop			(pop),
	      .push			(push),
	      .data_in			(data_in[BUS_SIZE-1:0]),
	      .valid (valid));    
   
   probador prob(

		 .clk			(clk),
		 .reset			(reset),
		 .push			(push),
		 .pop			(pop),
		 .data_in		(data_in[BUS_SIZE-1:0]),
		 .valid			(valid),

		 .empty			(empty),
		 .data_out_cond		(data_out[BUS_SIZE-1:0]),
		 .continua		(continua),
		 .pause			(pause),
		 .valid_out(valid_out),

		 .data_out_synth (data_outE),
		 .continua_syn		(continuaE),
		 .pause_syn			(pause),
		 .valid_out_syn(valid_outE),
		 .empty_syn		(emptyE)
		 
);
   
   endmodule