data/full_repos/permissive/136510272/projects/05_nes/evaluator.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/evaluator.v:14: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 9 bits.\n                                                                                   : ... In instance evaluator\nwire [2:0]  xbitn  = x - sprite[7:0];\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/evaluator.v:38: Operator GTE expects 9 bits on the RHS, but RHS\'s SEL generates 8 bits.\n                                                                                   : ... In instance evaluator\n    else if (x >= sprite[7:0] && x < (sprite[7:0] + 8) && valid) begin\n               ^~\n%Error: Exiting due to 2 warning(s)\n'
module evaluator(

    input wire         valid,
    input wire  [31:0] sprite,
    input wire  [ 4:0] bg,
    input wire  [ 8:0] x,
    output reg  [ 4:0] color,
    input wire  [ 7:0] ctrl

);


reg         opaque;
wire [2:0]  xbitn  = x - sprite[7:0];
wire [15:0] bits   = {sprite[24], sprite[ 8],
                      sprite[25], sprite[ 9],
                      sprite[26], sprite[10],
                      sprite[27], sprite[11],
                      sprite[28], sprite[12],
                      sprite[29], sprite[13],
                      sprite[30], sprite[14],
                      sprite[31], sprite[15]};

wire [3:0]  rcolor   = {sprite[17:16],
                        bits[ {xbitn[2:0], 1'b1} ],
                        bits[ {xbitn[2:0], 1'b0} ]};


always @* begin


    if (!ctrl[2] && x < 8 || !ctrl[4]) begin
    
        color = bg;      
    end


    else if (x >= sprite[7:0] && x < (sprite[7:0] + 8) && valid) begin
    

        opaque = rcolor[1:0] != 2'b00; 
        




        
        color  = opaque ? (sprite[16 + 5] && bg[1:0] == 2'b00 ? bg : {1'b1, rcolor}) : bg;
            
    end else begin
        
        color  = bg;    
    end

end

endmodule
module evaluator(

    input wire         valid,
    input wire  [31:0] sprite,
    input wire  [ 4:0] bg,
    input wire  [ 8:0] x,
    output reg  [ 4:0] color,
    input wire  [ 7:0] ctrl

);



reg         opaque;
wire [2:0]  xbitn  = x - sprite[7:0];
wire [15:0] bits   = {sprite[24], sprite[ 8],
                      sprite[25], sprite[ 9],
                      sprite[26], sprite[10],
                      sprite[27], sprite[11],
                      sprite[28], sprite[12],
                      sprite[29], sprite[13],
                      sprite[30], sprite[14],
                      sprite[31], sprite[15]};

wire [3:0]  rcolor   = {sprite[17:16],
                        bits[ {xbitn[2:0], 1'b1} ],
                        bits[ {xbitn[2:0], 1'b0} ]};


always @* begin


    if (!ctrl[2] && x < 8 || !ctrl[4]) begin
    
        color = bg;      
    end


    else if (x >= sprite[7:0] && x < (sprite[7:0] + 8) && valid) begin
    

        opaque = rcolor[1:0] != 2'b00; 
        




        
        color  = opaque ? (sprite[16 + 5] && bg[1:0] == 2'b00 ? bg : {1'b1, rcolor}) : bg;
            
    end else begin
        
        color  = bg;    
    end

end

endmodule