data/full_repos/permissive/159479522/buzzer_led.v
data/verilator_xmls/a73d462c-5024-4e8b-bd41-04168ae4abb0.xml
module buzzer_led(clk,clk_buzzer,reset,power_led,start_pause,module_select,water_select,buzzer_led );
 input wire clk,clk_buzzer,reset,power_led,start_pause,module_select,water_select;
      reg if_finish;
output reg buzzer_led;
reg [1:0] cont;   
initial begin
  buzzer_led=0;
  cont=0;
  if_finish=0;
  end
  
always @(posedge  clk_buzzer) begin
  if(reset||start_pause||module_select||water_select)  begin
     buzzer_led=1;
     end
  else begin
     if(if_finish==1)begin
        buzzer_led=1;
        cont=0;
     end
     if( buzzer_led)begin 
       cont=cont+1;
       buzzer_led=~buzzer_led;
        buzzer_led=1;
     if(cont>=3)
      buzzer_led=0;
     end
  end 
end 
endmodule
module buzzer_led(clk,clk_buzzer,reset,power_led,start_pause,module_select,water_select,buzzer_led );

 input wire clk,clk_buzzer,reset,power_led,start_pause,module_select,water_select;
      reg if_finish;
output reg buzzer_led;
reg [1:0] cont;   
initial begin
  buzzer_led=0;
  cont=0;
  if_finish=0;
  end
  
always @(posedge  clk_buzzer) begin
  if(reset||start_pause||module_select||water_select)  begin
     buzzer_led=1;
     end
  else begin
     if(if_finish==1)begin
        buzzer_led=1;
        cont=0;
     end
     if( buzzer_led)begin 
       cont=cont+1;
       buzzer_led=~buzzer_led;
        buzzer_led=1;
     if(cont>=3)
      buzzer_led=0;
     end
  end 
end 
endmodule