data/full_repos/permissive/159555381/mealy.v
 line:62: before: "$"
1: b'%Error: data/full_repos/permissive/159555381/mealy.v:42: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("mealy.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/159555381/mealy.v:43: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, wb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #15 reset = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:48: Unsupported: Ignoring delay on this delayed statement.\n always #5  clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #12 x = 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mealy.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module wb;
	output reg x, clk, reset;
	wire out;
	mealy mly(x, clk, reset, out);
	initial begin 
		$dumpfile("mealy.vcd");
		$dumpvars(0, wb);
		clk = 1'b0;
		reset = 1'b1;
		#15 reset = 1'b0;
	end
	always #5  clk = ~clk;
	initial begin
		#12 x = 0; 
		#10 x = 0; 
		#10 x = 1; 
		#10 x = 0; 
		#10 x = 1; 
		#10 x = 0; 
		#10 x = 1; 
		#10 x = 0;
		#10 x = 0; 
		#10 x = 1; 
		#10 x = 1; 
		#10 x = 0;
		#10 $finish;
	end
endmodule
module wb;

	output reg x, clk, reset;
	wire out;
	mealy mly(x, clk, reset, out);
	initial begin 
		$dumpfile("mealy.vcd");
		$dumpvars(0, wb);
		clk = 1'b0;
		reset = 1'b1;
		#15 reset = 1'b0;
	end
	always #5  clk = ~clk;
	initial begin
		#12 x = 0; 
		#10 x = 0; 
		#10 x = 1; 
		#10 x = 0; 
		#10 x = 1; 
		#10 x = 0; 
		#10 x = 1; 
		#10 x = 0;
		#10 x = 0; 
		#10 x = 1; 
		#10 x = 1; 
		#10 x = 0;
		#10 $finish;
	end
endmodule