data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:23: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("jeff-74x151-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:24: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, jeff_74x151_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10; C = 0; B = 0; A = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10; C = 0; B = 0; A = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 1; D0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10; C = 0; B = 1; A = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 1; D1 = 0; D0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10; C = 0; B = 1; A = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 1; D2 = 0; D1 = 0; D0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10; C = 1; B = 0; A = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 1; D3 = 0; D2 = 0; D1 = 0; D0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10; C = 1; B = 0; A = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10; D7 = 0; D6 = 0; D5 = 1; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #10; C = 1; B = 1; A = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10; D7 = 0; D6 = 1; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #10; C = 1; B = 1; A = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #10; D7 = 1; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/jeff-74x151/jeff-74x151-tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: Exiting due to 2 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module jeff_74x151_tb;


reg        D0, D1, D2, D3, D4, D5, D6, D7;
reg        A, B, C;
reg        EN;
wire       Y, W;


jeff_74x151 uut(
    .d0(D0), .d1(D1), .d2(D2), .d3(D3), .d4(D4), .d5(D5), .d6(D6), .d7(D7),
    .a(A), .b(B), .c(C),
    .en(EN),
    .y(Y), .w(W)
);


initial begin
    $dumpfile("jeff-74x151-tb.vcd");
    $dumpvars(0, jeff_74x151_tb);
end


initial begin
    $display("test start");
    D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    C = 0; B = 0; A = 0;
    EN = 1;

    #10; C = 0; B = 0; A = 0;
    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 1;
    #10; C = 0; B = 0; A = 1;
    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 1; D0 = 0;
    #10; C = 0; B = 1; A = 0;
    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 1; D1 = 0; D0 = 0;
    #10; C = 0; B = 1; A = 1;
    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 1; D2 = 0; D1 = 0; D0 = 0;
    #10; C = 1; B = 0; A = 0;
    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 1; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #10; C = 1; B = 0; A = 1;
    #10; D7 = 0; D6 = 0; D5 = 1; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #10; C = 1; B = 1; A = 0;
    #10; D7 = 0; D6 = 1; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #10; C = 1; B = 1; A = 1;
    #10; D7 = 1; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #10

    EN = 0;
    #10

    $display("test complete");
    $finish;
end

endmodule
module jeff_74x151_tb;



reg        D0, D1, D2, D3, D4, D5, D6, D7;
reg        A, B, C;
reg        EN;
wire       Y, W;


jeff_74x151 uut(
    .d0(D0), .d1(D1), .d2(D2), .d3(D3), .d4(D4), .d5(D5), .d6(D6), .d7(D7),
    .a(A), .b(B), .c(C),
    .en(EN),
    .y(Y), .w(W)
);


initial begin
    $dumpfile("jeff-74x151-tb.vcd");
    $dumpvars(0, jeff_74x151_tb);
end


initial begin
    $display("test start");
    D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    C = 0; B = 0; A = 0;
    EN = 1;

    #10; C = 0; B = 0; A = 0;
    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 1;
    #10; C = 0; B = 0; A = 1;
    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 1; D0 = 0;
    #10; C = 0; B = 1; A = 0;
    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 1; D1 = 0; D0 = 0;
    #10; C = 0; B = 1; A = 1;
    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 1; D2 = 0; D1 = 0; D0 = 0;
    #10; C = 1; B = 0; A = 0;
    #10; D7 = 0; D6 = 0; D5 = 0; D4 = 1; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #10; C = 1; B = 0; A = 1;
    #10; D7 = 0; D6 = 0; D5 = 1; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #10; C = 1; B = 1; A = 0;
    #10; D7 = 0; D6 = 1; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #10; C = 1; B = 1; A = 1;
    #10; D7 = 1; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #10

    EN = 0;
    #10

    $display("test complete");
    $finish;
end

endmodule