data/full_repos/permissive/116563702/decoder3_8/decoder3_8style.v
data/verilator_xmls/bdc38a7d-50a8-458b-b5c8-21873639dd89.xml
module decoder3_8( input [2:0] a,
		   output [7:0] y);

   assign y[0] = ~(|a);
   assign y[1] = ~a[2] & ~a[1] &  a[0];
   assign y[2] = ~a[2] &  a[1] & ~a[0];
   assign y[3] = ~a[2] &  a[1] &  a[0];
   assign y[4] =  a[2] & ~a[1] & ~a[0];
   assign y[5] =  a[2] & ~a[1] &  a[0];
   assign y[6] =  a[2] &  a[1] & ~a[0];
   assign y[7] =  &a;
endmodule
module decoder3_8( input [2:0] a,
		   output [7:0] y);


   assign y[0] = ~(|a);
   assign y[1] = ~a[2] & ~a[1] &  a[0];
   assign y[2] = ~a[2] &  a[1] & ~a[0];
   assign y[3] = ~a[2] &  a[1] &  a[0];
   assign y[4] =  a[2] & ~a[1] & ~a[0];
   assign y[5] =  a[2] & ~a[1] &  a[0];
   assign y[6] =  a[2] &  a[1] & ~a[0];
   assign y[7] =  &a;
endmodule