data/full_repos/permissive/201224775/rtl/ic/ic_addr_decode.v
data/verilator_xmls/ca56b0b1-5d7a-42c9-b7fd-5ff8eabdf587.xml
module ic_addr_decode (

input  wire        g_clk        ,
input  wire        g_resetn     ,

input  wire        req_valid    ,
input  wire [31:0] req_addr     ,

output wire        req_dec_err  ,

output wire        route_rom    ,
output wire        route_ram    ,
output wire        route_axi

);




parameter MAP_ROM_MATCH = 32'h1000_0000;
parameter MAP_ROM_MASK  = 32'hFFFF_FC00;
parameter MAP_ROM_RANGE = 32'h0000_03FF;

parameter MAP_RAM_MATCH = 32'h2000_0000;
parameter MAP_RAM_MASK  = 32'hFFFF_0000;
parameter MAP_RAM_RANGE = 32'h0000_FFFF;

parameter MAP_AXI_MATCH = 32'h4000_0000;
parameter MAP_AXI_MASK  = 32'hF000_0000;
parameter MAP_AXI_RANGE = 32'h0FFF_FFFF;




wire match_rom = ((req_addr &  MAP_ROM_MASK) == (           MAP_ROM_MATCH)) &&
                 ((req_addr & ~MAP_ROM_MASK) == (req_addr & MAP_ROM_RANGE)) ;

wire match_ram = ((req_addr &  MAP_RAM_MASK) == (           MAP_RAM_MATCH)) &&
                 ((req_addr & ~MAP_RAM_MASK) == (req_addr & MAP_RAM_RANGE)) ;

wire match_axi = ((req_addr &  MAP_AXI_MASK) == (           MAP_AXI_MATCH)) &&
                 ((req_addr & ~MAP_AXI_MASK) == (req_addr & MAP_AXI_RANGE)) ;




assign route_rom    = match_rom && req_valid;

assign route_ram    = match_ram && req_valid;

assign route_axi    = match_axi && req_valid;

assign req_dec_err  = !(match_rom || match_ram || match_axi) && req_valid;




`ifdef FORMAL_IC_ADDR_DECODE

initial assume(!g_resetn);

always @(posedge g_clk) if(g_resetn && $stable(g_resetn)) begin

    assert(!(route_rom && route_ram));
    
    assert(!(route_rom && route_axi));
    
    assert(!(route_ram && route_axi));

    cover(route_rom);

    cover(route_ram);
    
    cover(route_axi);

end

`endif

endmodule
module ic_addr_decode (

input  wire        g_clk        ,
input  wire        g_resetn     ,

input  wire        req_valid    ,
input  wire [31:0] req_addr     ,

output wire        req_dec_err  ,

output wire        route_rom    ,
output wire        route_ram    ,
output wire        route_axi

);





parameter MAP_ROM_MATCH = 32'h1000_0000;
parameter MAP_ROM_MASK  = 32'hFFFF_FC00;
parameter MAP_ROM_RANGE = 32'h0000_03FF;

parameter MAP_RAM_MATCH = 32'h2000_0000;
parameter MAP_RAM_MASK  = 32'hFFFF_0000;
parameter MAP_RAM_RANGE = 32'h0000_FFFF;

parameter MAP_AXI_MATCH = 32'h4000_0000;
parameter MAP_AXI_MASK  = 32'hF000_0000;
parameter MAP_AXI_RANGE = 32'h0FFF_FFFF;




wire match_rom = ((req_addr &  MAP_ROM_MASK) == (           MAP_ROM_MATCH)) &&
                 ((req_addr & ~MAP_ROM_MASK) == (req_addr & MAP_ROM_RANGE)) ;

wire match_ram = ((req_addr &  MAP_RAM_MASK) == (           MAP_RAM_MATCH)) &&
                 ((req_addr & ~MAP_RAM_MASK) == (req_addr & MAP_RAM_RANGE)) ;

wire match_axi = ((req_addr &  MAP_AXI_MASK) == (           MAP_AXI_MATCH)) &&
                 ((req_addr & ~MAP_AXI_MASK) == (req_addr & MAP_AXI_RANGE)) ;




assign route_rom    = match_rom && req_valid;

assign route_ram    = match_ram && req_valid;

assign route_axi    = match_axi && req_valid;

assign req_dec_err  = !(match_rom || match_ram || match_axi) && req_valid;




`ifdef FORMAL_IC_ADDR_DECODE

initial assume(!g_resetn);

always @(posedge g_clk) if(g_resetn && $stable(g_resetn)) begin

    assert(!(route_rom && route_ram));
    
    assert(!(route_rom && route_axi));
    
    assert(!(route_ram && route_axi));

    cover(route_rom);

    cover(route_ram);
    
    cover(route_axi);

end

`endif

endmodule