data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v
 line:26: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:14: Unsupported: Ignoring delay on this delayed statement.\n #0 clock = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:15: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clock = ~clock;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:20: Unsupported: Ignoring delay on this delayed statement.\n #00 a = 8\'b0000_0000; b = 8\'b0000_0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:21: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b0000_0000; b = 8\'b0000_0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:22: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b1111_1111; b = 8\'b1111_1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:23: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b1111_0000; b = 8\'b0000_1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:24: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b1010_1010; b = 8\'b0101_0101;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b1111_0000; b = 8\'b0000_1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:26: Unsupported: Ignoring delay on this delayed statement.\n #20 $stop;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:31: Unsupported: Ignoring delay on this delayed statement.\n #00 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:32: Unsupported: Ignoring delay on this delayed statement.\n #90 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:33: Unsupported: Ignoring delay on this delayed statement.\n #95 reset = 1\'b0;\n ^\n%Error: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:38: Unsupported or unknown PLI call: $monitor\n $monitor("time=3d, prod=16b, eop=1b, a=8b,b=8b,clock=1b, reset=1b",$time, prod, eop, a, b, clock, reset);\n ^~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:43: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("u_multiplier_8bit.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:44: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_u_multiplier_8bit();
wire [15:0] prod;
wire eop;

reg [7:0] a,b;
reg clock, reset;

u_multiplier_8bit uut(prod, eop, a, b, clock, reset);

initial
begin
	#0 clock = 1'b0;
	forever #20 clock = ~clock;
end

initial
begin
	#00 a = 8'b0000_0000; b = 8'b0000_0000;
	#20 a = 8'b0000_0000; b = 8'b0000_0000;
	#20 a = 8'b1111_1111; b = 8'b1111_1111;
	#20 a = 8'b1111_0000; b = 8'b0000_1111;
	#20 a = 8'b1010_1010; b = 8'b0101_0101;
	#20 a = 8'b1111_0000; b = 8'b0000_1111;
	#20 $stop;
end

initial
begin
	#00 reset = 1'b0;
	#90 reset = 1'b1;
	#95 reset = 1'b0;
end

initial
begin
	$monitor("time=3d, prod=16b, eop=1b, a=8b,b=8b,clock=1b, reset=1b",$time, prod, eop, a, b, clock, reset);
end

initial
begin
	$dumpfile("u_multiplier_8bit.vcd");
	$dumpvars;
end

endmodule
module tb_u_multiplier_8bit();

wire [15:0] prod;
wire eop;

reg [7:0] a,b;
reg clock, reset;

u_multiplier_8bit uut(prod, eop, a, b, clock, reset);

initial
begin
	#0 clock = 1'b0;
	forever #20 clock = ~clock;
end

initial
begin
	#00 a = 8'b0000_0000; b = 8'b0000_0000;
	#20 a = 8'b0000_0000; b = 8'b0000_0000;
	#20 a = 8'b1111_1111; b = 8'b1111_1111;
	#20 a = 8'b1111_0000; b = 8'b0000_1111;
	#20 a = 8'b1010_1010; b = 8'b0101_0101;
	#20 a = 8'b1111_0000; b = 8'b0000_1111;
	#20 $stop;
end

initial
begin
	#00 reset = 1'b0;
	#90 reset = 1'b1;
	#95 reset = 1'b0;
end

initial
begin
	$monitor("time=3d, prod=16b, eop=1b, a=8b,b=8b,clock=1b, reset=1b",$time, prod, eop, a, b, clock, reset);
end

initial
begin
	$dumpfile("u_multiplier_8bit.vcd");
	$dumpvars;
end

endmodule