data/full_repos/permissive/212394344/ALU_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:140: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:146: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:152: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:170: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:176: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:182: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:188: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:194: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:200: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:206: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:212: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:218: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ALU_TB.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/212394344/ALU_TB.v:40: Cannot find file containing module: \'ALU\'\n ALU uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/ALU\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/ALU.v\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 29 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_TB;


	reg [7:0] data_in;
	reg [7:0] A;
	reg [7:0] B;
	reg [4:0] op_dec;
	reg [7:0] ans_ex;


	wire [3:0] flag_ex;
	wire [7:0] ans_tmp;
	wire [7:0] data_out_buff;


	ALU uut (
		.flag_ex(flag_ex), 
		.ans_tmp(ans_tmp), 
		.data_out_buff(data_out_buff), 
		.data_in(data_in), 
		.A(A), 
		.B(B), 
		.op_dec(op_dec), 
		.ans_ex(ans_ex)
	);	
	
	initial begin
		
		
		
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00010;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01010;
		#1000;
	
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b11000;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11001;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11010;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11011;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11100;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11101;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11110;
		#1000;
        
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11111;
		#1000;
		
	end
      
endmodule
module ALU_TB;



	reg [7:0] data_in;
	reg [7:0] A;
	reg [7:0] B;
	reg [4:0] op_dec;
	reg [7:0] ans_ex;


	wire [3:0] flag_ex;
	wire [7:0] ans_tmp;
	wire [7:0] data_out_buff;


	ALU uut (
		.flag_ex(flag_ex), 
		.ans_tmp(ans_tmp), 
		.data_out_buff(data_out_buff), 
		.data_in(data_in), 
		.A(A), 
		.B(B), 
		.op_dec(op_dec), 
		.ans_ex(ans_ex)
	);	
	
	initial begin
		
		
		
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00010;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01010;
		#1000;
	
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b11000;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11001;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11010;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11011;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11100;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11101;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11110;
		#1000;
        
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11111;
		#1000;
		
	end
      
endmodule