data/full_repos/permissive/149769583/sram_tb2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb2.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #10 write_enable = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb2.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10 write_enable = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb2.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb2.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb2.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb2.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb2.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb2.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb2.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 6;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb2.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 7;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb2.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;   \n        ^\n%Warning-WIDTH: data/full_repos/permissive/149769583/sram_tb2.v:18: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h20601\' generates 18 bits.\n                                                                  : ... In instance sram_basic_testbench\n        data_in = 18\'b100000011000000001;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/149769583/sram_tb2.v:20: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h403\' generates 18 bits.\n                                                                  : ... In instance sram_basic_testbench\n        data_in = 18\'b000000010000000011;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/149769583/sram_tb2.v:22: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h805\' generates 18 bits.\n                                                                  : ... In instance sram_basic_testbench\n        data_in = 18\'b000000100000000101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/149769583/sram_tb2.v:24: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'hd01\' generates 18 bits.\n                                                                  : ... In instance sram_basic_testbench\n        data_in = 18\'b000000110100000001;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/149769583/sram_tb2.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h20302\' generates 18 bits.\n                                                                  : ... In instance sram_basic_testbench\n        data_in = 18\'b100000001100000010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/149769583/sram_tb2.v:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h20407\' generates 18 bits.\n                                                                  : ... In instance sram_basic_testbench\n        data_in = 18\'b100000010000000111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/149769583/sram_tb2.v:30: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h20303\' generates 18 bits.\n                                                                  : ... In instance sram_basic_testbench\n        data_in = 18\'b100000001100000011;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/149769583/sram_tb2.v:32: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h20303\' generates 18 bits.\n                                                                  : ... In instance sram_basic_testbench\n        data_in = 18\'b100000001100000011;\n                ^\n%Error: data/full_repos/permissive/149769583/sram_tb2.v:49: Cannot find file containing module: \'sram\'\n    sram DUT (\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/sram\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/sram.v\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/sram.sv\n             sram\n             sram.v\n             sram.sv\n             obj_dir/sram\n             obj_dir/sram.v\n             obj_dir/sram.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sram_basic_testbench();
    parameter ADDR_WIDTH = 4;
    parameter DATA_WIDTH = 32;
    parameter DEPTH = 32;

    reg clk;
    reg [ADDR_WIDTH-1:0] address;
    reg write_enable;
    reg [DATA_WIDTH-1:0] data_in;
    wire [DATA_WIDTH-1:0] data_out;

    initial begin
        $display("sram test bench 2");
        clk = 1;

        #10 write_enable = 1;
        address = 0;
        data_in = 18'b100000011000000001;
        address = 1;
        data_in = 18'b000000010000000011;
        address = 2;
        data_in = 18'b000000100000000101;
        address = 3;
        data_in = 18'b000000110100000001;
        address = 4;
        data_in = 18'b100000001100000010;
        address = 5;
        data_in = 18'b100000010000000111;
        address = 6;
        data_in = 18'b100000001100000011;
        address = 7;
        data_in = 18'b100000001100000011;

        #10 write_enable = 0;
        #10 address = 0;
        #10 address = 1;
        #10 address = 2;
        #10 address = 3;
        #10 address = 4;
        #10 address = 5;
        #10 address = 6;
        #10 address = 7;
    end

    always begin
        #5 clk = ~clk;
    end

    sram DUT (
        .i_clk(clk),
        .i_addr(address),
        .i_write(write_enable),
        .i_data(data_in),
        .o_data(data_out));

endmodule
module sram_basic_testbench();

    parameter ADDR_WIDTH = 4;
    parameter DATA_WIDTH = 32;
    parameter DEPTH = 32;

    reg clk;
    reg [ADDR_WIDTH-1:0] address;
    reg write_enable;
    reg [DATA_WIDTH-1:0] data_in;
    wire [DATA_WIDTH-1:0] data_out;

    initial begin
        $display("sram test bench 2");
        clk = 1;

        #10 write_enable = 1;
        address = 0;
        data_in = 18'b100000011000000001;
        address = 1;
        data_in = 18'b000000010000000011;
        address = 2;
        data_in = 18'b000000100000000101;
        address = 3;
        data_in = 18'b000000110100000001;
        address = 4;
        data_in = 18'b100000001100000010;
        address = 5;
        data_in = 18'b100000010000000111;
        address = 6;
        data_in = 18'b100000001100000011;
        address = 7;
        data_in = 18'b100000001100000011;

        #10 write_enable = 0;
        #10 address = 0;
        #10 address = 1;
        #10 address = 2;
        #10 address = 3;
        #10 address = 4;
        #10 address = 5;
        #10 address = 6;
        #10 address = 7;
    end

    always begin
        #5 clk = ~clk;
    end

    sram DUT (
        .i_clk(clk),
        .i_addr(address),
        .i_write(write_enable),
        .i_data(data_in),
        .o_data(data_out));

endmodule