data/full_repos/permissive/268184328/stopwatch/stopwatch.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/268184328/stopwatch/stopwatch.v:9: Cannot find include file: ./counter.v\n`include "./counter.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/268184328/stopwatch,data/full_repos/permissive/268184328/./counter.v\n             data/full_repos/permissive/268184328/stopwatch,data/full_repos/permissive/268184328/./counter.v.v\n             data/full_repos/permissive/268184328/stopwatch,data/full_repos/permissive/268184328/./counter.v.sv\n             ./counter.v\n             ./counter.v.v\n             ./counter.v.sv\n             obj_dir/./counter.v\n             obj_dir/./counter.v.v\n             obj_dir/./counter.v.sv\n%Error: data/full_repos/permissive/268184328/stopwatch/stopwatch.v:10: Cannot find include file: ./divider_s.v\n`include "./divider_s.v" \n         ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module stopwatch(clk, rst, sw_en, pause, clear, clk_out, time_sec_h, time_sec_l, time_msec_h, time_msec_l, time_out);


input clk, rst, clear, sw_en, pause;
output clk_out, time_out;
output [2:0] time_sec_h;
output [3:0] time_sec_l, time_msec_l, time_msec_h;

reg [2:0] time_sec_h;
reg [3:0] time_sec_l, time_msec_l, time_msec_h;
wire clk_1, clk_2;


wire [2:0] time_sec_h_in;
wire [3:0] time_sec_l_in, time_msec_l_in, time_msec_h_in;
reg time_out;


parameter time_set = 16'h1000;



divider_s divider_s (.clk(clk), 
					.rst(rst),
					.clk_1(clk_1),
					.clk_2(clk_2));

assign clk_out = clk_2;



counter counter(.clk_1(clk_1),
				.rst(rst),
				.clear(clear),
				.sw_en(sw_en),
				.time_sec_h(time_sec_h_in),
				.time_sec_l(time_sec_l_in),
				.time_msec_h(time_msec_h_in),
				.time_msec_l(time_msec_l_in));


always @(posedge clk or negedge rst) begin
	if (!rst) begin

		time_sec_h  <=0;
		time_sec_l  <=0;
		time_msec_h <=0;
		time_msec_l <=0; 
	end
	else if (!pause) begin
		time_sec_h  <=time_sec_h_in ;
		time_sec_l  <=time_sec_l_in ;
		time_msec_h <=time_msec_h_in;
		time_msec_l <=time_msec_l_in; 
	end

	else begin
		time_sec_h  <=time_sec_h ;
		time_sec_l  <=time_sec_l ;
		time_msec_h <=time_msec_h;
		time_msec_l <=time_msec_l; 
	end
end


always @(posedge clk or negedge rst) begin
	if (!rst)
		time_out <= 0;
	else  begin
		if ({time_sec_h, time_sec_l, time_msec_h, time_msec_l} == time_set)
			time_out = 1;
		else if ({time_sec_h, time_sec_l, time_msec_h, time_msec_l} == 16'h5999)
			time_out = 0;
	end
end

endmodule
module stopwatch(clk, rst, sw_en, pause, clear, clk_out, time_sec_h, time_sec_l, time_msec_h, time_msec_l, time_out);



input clk, rst, clear, sw_en, pause;
output clk_out, time_out;
output [2:0] time_sec_h;
output [3:0] time_sec_l, time_msec_l, time_msec_h;

reg [2:0] time_sec_h;
reg [3:0] time_sec_l, time_msec_l, time_msec_h;
wire clk_1, clk_2;


wire [2:0] time_sec_h_in;
wire [3:0] time_sec_l_in, time_msec_l_in, time_msec_h_in;
reg time_out;


parameter time_set = 16'h1000;



divider_s divider_s (.clk(clk), 
					.rst(rst),
					.clk_1(clk_1),
					.clk_2(clk_2));

assign clk_out = clk_2;



counter counter(.clk_1(clk_1),
				.rst(rst),
				.clear(clear),
				.sw_en(sw_en),
				.time_sec_h(time_sec_h_in),
				.time_sec_l(time_sec_l_in),
				.time_msec_h(time_msec_h_in),
				.time_msec_l(time_msec_l_in));


always @(posedge clk or negedge rst) begin
	if (!rst) begin

		time_sec_h  <=0;
		time_sec_l  <=0;
		time_msec_h <=0;
		time_msec_l <=0; 
	end
	else if (!pause) begin
		time_sec_h  <=time_sec_h_in ;
		time_sec_l  <=time_sec_l_in ;
		time_msec_h <=time_msec_h_in;
		time_msec_l <=time_msec_l_in; 
	end

	else begin
		time_sec_h  <=time_sec_h ;
		time_sec_l  <=time_sec_l ;
		time_msec_h <=time_msec_h;
		time_msec_l <=time_msec_l; 
	end
end


always @(posedge clk or negedge rst) begin
	if (!rst)
		time_out <= 0;
	else  begin
		if ({time_sec_h, time_sec_l, time_msec_h, time_msec_l} == time_set)
			time_out = 1;
		else if ({time_sec_h, time_sec_l, time_msec_h, time_msec_l} == 16'h5999)
			time_out = 0;
	end
end

endmodule