data/full_repos/permissive/123218339/selectMyAction.v
data/verilator_xmls/7f241919-11e9-4fc1-bf76-b0fca3e9d6c5.xml
module selectMyAction(clock, nrst, start, nexthop, nextsinks, action, forAggregation, done);
    input clock, nrst, start;
    input [`WORD_WIDTH-1:0] nexthop, nextsinks;
    output forAggregation, done;
    output [`WORD_WIDTH-1:0] action;


    reg forAggregation_buf, done_buf;
    reg [`WORD_WIDTH-1:0] action_buf;

    always @ (posedge clock) begin
        if (!nrst) begin
            done_buf <= 0;
            action_buf <= nexthop;
        end
        else begin
            if (start && !done_buf) begin
                if (nextsinks != 16'd65) begin
                    action_buf = nextsinks;

                end
                if (action_buf == 65) begin
                    forAggregation_buf = 1;


                end
                done_buf = 1;
            end
        end
    end

    assign done = done_buf;
    assign forAggregation = forAggregation_buf;
    assign action = action_buf;
endmodule
module selectMyAction(clock, nrst, start, nexthop, nextsinks, action, forAggregation, done);

    input clock, nrst, start;
    input [`WORD_WIDTH-1:0] nexthop, nextsinks;
    output forAggregation, done;
    output [`WORD_WIDTH-1:0] action;


    reg forAggregation_buf, done_buf;
    reg [`WORD_WIDTH-1:0] action_buf;

    always @ (posedge clock) begin
        if (!nrst) begin
            done_buf <= 0;
            action_buf <= nexthop;
        end
        else begin
            if (start && !done_buf) begin
                if (nextsinks != 16'd65) begin
                    action_buf = nextsinks;

                end
                if (action_buf == 65) begin
                    forAggregation_buf = 1;


                end
                done_buf = 1;
            end
        end
    end

    assign done = done_buf;
    assign forAggregation = forAggregation_buf;
    assign action = action_buf;
endmodule