data/full_repos/permissive/216344104/pwm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/216344104/pwm.v:32: Operator ASSIGNDLY expects 40 bits on the Assign RHS, but Assign RHS\'s CONST \'39\'h0\' generates 39 bits.\n                                                             : ... In instance pwmmodule\n   cnt <= 39\'d0;\n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pwmmodule(data,reset,clk,pwm,Hbridge1,Hbridge2);
input signed[39:0] data;
input clk;
input reset;
output reg pwm;
output reg Hbridge1,Hbridge2;

reg [39:0] cnt;
reg [39:0] value;

always@*
	if(data[23])
			begin
				value = -data;
				Hbridge1 = 1'b0;
				Hbridge2 = 1'b1;
			end
		else
			begin
				value = data;
				Hbridge1 = 1'b1;
				Hbridge2 = 1'b0;
			end

always@(posedge clk or negedge reset)
		if(!reset)
			cnt <= 39'd0;
		else
			cnt <= cnt + 1'b1; 

always@(posedge clk or negedge reset)
		if (!reset)
				pwm <= 1'b0;
		else
			begin
				if(cnt < value)
				pwm <= 1'b1;
				else
				pwm <= 1'b0;
			end
endmodule
module pwmmodule(data,reset,clk,pwm,Hbridge1,Hbridge2);

input signed[39:0] data;
input clk;
input reset;
output reg pwm;
output reg Hbridge1,Hbridge2;

reg [39:0] cnt;
reg [39:0] value;

always@*
	if(data[23])
			begin
				value = -data;
				Hbridge1 = 1'b0;
				Hbridge2 = 1'b1;
			end
		else
			begin
				value = data;
				Hbridge1 = 1'b1;
				Hbridge2 = 1'b0;
			end

always@(posedge clk or negedge reset)
		if(!reset)
			cnt <= 39'd0;
		else
			cnt <= cnt + 1'b1; 

always@(posedge clk or negedge reset)
		if (!reset)
				pwm <= 1'b0;
		else
			begin
				if(cnt < value)
				pwm <= 1'b1;
				else
				pwm <= 1'b0;
			end
endmodule