data/full_repos/permissive/115141190/Part_A/Instruction_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #100 reset = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #20 next_instruction <= 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #50000 next_instruction <= 1\'b1;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #20 next_instruction <= 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk <= ~clk;\n    ^\n%Error: data/full_repos/permissive/115141190/Part_A/Instruction_tb.v:8: Cannot find file containing module: \'Instruction\'\n  Instruction Instruction (\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115141190/Part_A,data/full_repos/permissive/115141190/Instruction\n             data/full_repos/permissive/115141190/Part_A,data/full_repos/permissive/115141190/Instruction.v\n             data/full_repos/permissive/115141190/Part_A,data/full_repos/permissive/115141190/Instruction.sv\n             Instruction\n             Instruction.v\n             Instruction.sv\n             obj_dir/Instruction\n             obj_dir/Instruction.v\n             obj_dir/Instruction.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Instruction_tb ();

reg clk, reset, next_instruction;
reg [9:0]db;
wire LCD_RS, LCD_RW, LCD_E, done;
wire [3:0]SF_D;

  Instruction Instruction (
      .clk              (clk),
      .reset            (reset),
      .next_instruction (next_instruction),
      .db               (db),
      .LCD_RS           (LCD_RS),
      .LCD_RW           (LCD_RW),
      .LCD_E            (LCD_E),
      .SF_D             (SF_D),
      .done             (done)
  );

  initial begin
    next_instruction <= 1'b0;
    clk = 0;
    reset = 1;
    #100 reset = 0;

    next_instruction <= 1'b1;
    db <= 10'b00_1010_0101;
    #20 next_instruction <= 1'b0;

    #50000 next_instruction <= 1'b1;
    db <= 10'b00_1111_0000;
    #20 next_instruction <= 1'b0;
  end

  always begin
    #10 clk <= ~clk;
  end

endmodule
module Instruction_tb ();


reg clk, reset, next_instruction;
reg [9:0]db;
wire LCD_RS, LCD_RW, LCD_E, done;
wire [3:0]SF_D;

  Instruction Instruction (
      .clk              (clk),
      .reset            (reset),
      .next_instruction (next_instruction),
      .db               (db),
      .LCD_RS           (LCD_RS),
      .LCD_RW           (LCD_RW),
      .LCD_E            (LCD_E),
      .SF_D             (SF_D),
      .done             (done)
  );

  initial begin
    next_instruction <= 1'b0;
    clk = 0;
    reset = 1;
    #100 reset = 0;

    next_instruction <= 1'b1;
    db <= 10'b00_1010_0101;
    #20 next_instruction <= 1'b0;

    #50000 next_instruction <= 1'b1;
    db <= 10'b00_1111_0000;
    #20 next_instruction <= 1'b0;
  end

  always begin
    #10 clk <= ~clk;
  end

endmodule