data/full_repos/permissive/136371172/address_generator.v
data/verilator_xmls/c4b5b333-5a23-423f-9db2-a81dd5af51a2.xml
module address_generator(
		input clk,
		input reset,
		input LOCKED,
		output [14:0] address
    );
	 
	 

	parameter row = 125;


	reg [1:0] step = 0;
	reg [14:0] cnt = 0;





	assign address = cnt + step * row;
	
	
	always@(posedge clk) 
		if(LOCKED)
		begin
		if(reset)
			begin
				cnt <= 0;
				step <= 0;
			end
		
				step <= step + 1;	
				
				if(step == 2)
				begin
					cnt <= cnt + 1;
					step <= 0;
				end
			
			if (address  >= 31250) begin
					cnt <= 0;
					step <= 0;
				end
				
		end
endmodule
module address_generator(
		input clk,
		input reset,
		input LOCKED,
		output [14:0] address
    );

	 
	 

	parameter row = 125;


	reg [1:0] step = 0;
	reg [14:0] cnt = 0;





	assign address = cnt + step * row;
	
	
	always@(posedge clk) 
		if(LOCKED)
		begin
		if(reset)
			begin
				cnt <= 0;
				step <= 0;
			end
		
				step <= step + 1;	
				
				if(step == 2)
				begin
					cnt <= cnt + 1;
					step <= 0;
				end
			
			if (address  >= 31250) begin
					cnt <= 0;
					step <= 0;
				end
				
		end
endmodule