data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:3: Cannot find include file: simdrv_defs.svh\n`include "simdrv_defs.svh" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm,data/full_repos/permissive/161356276/simdrv_defs.svh\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm,data/full_repos/permissive/161356276/simdrv_defs.svh.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm,data/full_repos/permissive/161356276/simdrv_defs.svh.sv\n             simdrv_defs.svh\n             simdrv_defs.svh.v\n             simdrv_defs.svh.sv\n             obj_dir/simdrv_defs.svh\n             obj_dir/simdrv_defs.svh.v\n             obj_dir/simdrv_defs.svh.sv\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:4: Cannot find include file: if_wb_master.svh\n`include "if_wb_master.svh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:6: Cannot find include file: regs/spwm_regs.vh\n`include "regs/spwm_regs.vh" \n         ^~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:13: Unsupported: Ignoring delay on this delayed statement.\n     #5ns clk_sys <= ~clk_sys;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:16: syntax error, unexpected \'@\'\n      repeat(5) @(posedge clk_sys);\n                ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:50: syntax error, unexpected IDENTIFIER\n      CWishboneAccessor acc;\n                        ^~~\n%Warning-STMTDLY: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:53: Unsupported: Ignoring delay on this delayed statement.\n      #1000ns;\n      ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:59: Define or directive not defined: \'`ADDR_SPWM_CR\'\n      acc.write(`ADDR_SPWM_CR, (2 << `SPWM_CR_PRESC_OFFSET) | (254 << `SPWM_CR_PERIOD_OFFSET));\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:59: Define or directive not defined: \'`SPWM_CR_PRESC_OFFSET\'\n      acc.write(`ADDR_SPWM_CR, (2 << `SPWM_CR_PRESC_OFFSET) | (254 << `SPWM_CR_PERIOD_OFFSET));\n                                     ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:59: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      acc.write(`ADDR_SPWM_CR, (2 << `SPWM_CR_PRESC_OFFSET) | (254 << `SPWM_CR_PERIOD_OFFSET));\n                                                          ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:59: Define or directive not defined: \'`SPWM_CR_PERIOD_OFFSET\'\n      acc.write(`ADDR_SPWM_CR, (2 << `SPWM_CR_PRESC_OFFSET) | (254 << `SPWM_CR_PERIOD_OFFSET));\n                                                                      ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:61: Define or directive not defined: \'`ADDR_SPWM_DR0\'\n      acc.write(`ADDR_SPWM_DR0, 0);\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:62: Define or directive not defined: \'`ADDR_SPWM_DR1\'\n      acc.write(`ADDR_SPWM_DR1, 20);\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:63: Define or directive not defined: \'`ADDR_SPWM_DR2\'\n      acc.write(`ADDR_SPWM_DR2, 40);\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:64: Define or directive not defined: \'`ADDR_SPWM_DR3\'\n      acc.write(`ADDR_SPWM_DR3, 127);\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:65: Define or directive not defined: \'`ADDR_SPWM_DR4\'\n      acc.write(`ADDR_SPWM_DR4, 240);\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/wb_simple_pwm/main.sv:66: Define or directive not defined: \'`ADDR_SPWM_DR5\'\n      acc.write(`ADDR_SPWM_DR5, 255);\n                ^~~~~~~~~~~~~~\n%Error: Exiting due to 15 error(s), 2 warning(s)\n'
module main;

   reg clk_sys=1, rst_n=0;

   always
     #5ns clk_sys <= ~clk_sys;

   initial begin 
      repeat(5) @(posedge clk_sys);
      rst_n <= 1;
   end
   

   IWishboneMaster #(32, 32) U_WB
     (
      .clk_i(clk_sys),
      .rst_n_i(rst_n)
      );

   
   wb_simple_pwm 

     #(.g_num_channels(8))
   DUT
     (
      .clk_sys_i (clk_sys),
      .rst_n_i   (rst_n),

      .wb_adr_i (U_WB.master.adr[5:0]),
      .wb_dat_i (U_WB.master.dat_o),
      .wb_dat_o (U_WB.master.dat_i),
      .wb_cyc_i (U_WB.master.cyc),
      .wb_stb_i (U_WB.master.stb),
      .wb_we_i  (U_WB.master.we),
      .wb_ack_o (U_WB.master.ack),
      .wb_sel_i (U_WB.master.sel),
      .wb_stall_o(U_WB.master.stall)

      );
   
   
   initial begin
      CWishboneAccessor acc;
      int i;
      
      #1000ns;
      acc = U_WB.get_accessor();
      acc.set_mode(PIPELINED);
      U_WB.settings.addr_gran = BYTE;

      
      acc.write(`ADDR_SPWM_CR, (2 << `SPWM_CR_PRESC_OFFSET) | (254 << `SPWM_CR_PERIOD_OFFSET));
      
      acc.write(`ADDR_SPWM_DR0, 0);
      acc.write(`ADDR_SPWM_DR1, 20);
      acc.write(`ADDR_SPWM_DR2, 40);
      acc.write(`ADDR_SPWM_DR3, 127);
      acc.write(`ADDR_SPWM_DR4, 240);
      acc.write(`ADDR_SPWM_DR5, 255);
      

      
      $stop;
     
   end
   
endmodule
module main;


   reg clk_sys=1, rst_n=0;

   always
     #5ns clk_sys <= ~clk_sys;

   initial begin 
      repeat(5) @(posedge clk_sys);
      rst_n <= 1;
   end
   

   IWishboneMaster #(32, 32) U_WB
     (
      .clk_i(clk_sys),
      .rst_n_i(rst_n)
      );

   
   wb_simple_pwm 

     #(.g_num_channels(8))
   DUT
     (
      .clk_sys_i (clk_sys),
      .rst_n_i   (rst_n),

      .wb_adr_i (U_WB.master.adr[5:0]),
      .wb_dat_i (U_WB.master.dat_o),
      .wb_dat_o (U_WB.master.dat_i),
      .wb_cyc_i (U_WB.master.cyc),
      .wb_stb_i (U_WB.master.stb),
      .wb_we_i  (U_WB.master.we),
      .wb_ack_o (U_WB.master.ack),
      .wb_sel_i (U_WB.master.sel),
      .wb_stall_o(U_WB.master.stall)

      );
   
   
   initial begin
      CWishboneAccessor acc;
      int i;
      
      #1000ns;
      acc = U_WB.get_accessor();
      acc.set_mode(PIPELINED);
      U_WB.settings.addr_gran = BYTE;

      
      acc.write(`ADDR_SPWM_CR, (2 << `SPWM_CR_PRESC_OFFSET) | (254 << `SPWM_CR_PERIOD_OFFSET));
      
      acc.write(`ADDR_SPWM_DR0, 0);
      acc.write(`ADDR_SPWM_DR1, 20);
      acc.write(`ADDR_SPWM_DR2, 40);
      acc.write(`ADDR_SPWM_DR3, 127);
      acc.write(`ADDR_SPWM_DR4, 240);
      acc.write(`ADDR_SPWM_DR5, 255);
      

      
      $stop;
     
   end
   
endmodule