data/full_repos/permissive/197264840/rtl/core/frv_interrupts.v
1: b'%Error: data/full_repos/permissive/197264840/rtl/core/frv_interrupts.v:32: Cannot find include file: frv_common.vh\n`include "frv_common.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197264840/rtl/core,data/full_repos/permissive/197264840/frv_common.vh\n             data/full_repos/permissive/197264840/rtl/core,data/full_repos/permissive/197264840/frv_common.vh.v\n             data/full_repos/permissive/197264840/rtl/core,data/full_repos/permissive/197264840/frv_common.vh.sv\n             frv_common.vh\n             frv_common.vh.v\n             frv_common.vh.sv\n             obj_dir/frv_common.vh\n             obj_dir/frv_common.vh.v\n             obj_dir/frv_common.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module frv_interrupt (

input               g_clk           ,
input               g_resetn        ,

input               mstatus_mie     ,

input               mie_meie        ,
input               mie_mtie        ,
input               mie_msie        ,

input               ex_pending      ,
input               ti_pending      ,
input               sw_pending      ,

output reg          mip_meip        ,
output reg          mip_mtip        ,
output reg          mip_msip        ,

output wire         int_trap_req    ,
output wire [ 5:0]  int_trap_cause  ,
input  wire         int_trap_ack

);

`include "frv_common.vh"

always @(posedge g_clk) begin
    if(!g_resetn) begin
        mip_meip <= 1'b0      ;
        mip_mtip <= 1'b0      ;
        mip_msip <= 1'b0      ;
    end else begin
        mip_meip <= ex_pending;
        mip_mtip <= ti_pending;
        mip_msip <= sw_pending;
    end
end

wire   raise_mei    = mstatus_mie && mie_meie && mip_meip;
wire   raise_mti    = mstatus_mie && mie_mtie && mip_mtip;
wire   raise_msi    = mstatus_mie && mie_msie && mip_msip;

assign int_trap_req = raise_mei || raise_mti || raise_msi;

assign int_trap_cause = 
    raise_mei   ? TRAP_INT_MEI  :
    raise_mti   ? TRAP_INT_MTI  :
    raise_msi   ? TRAP_INT_MSI  :
                             0  ;

endmodule
module frv_interrupt (

input               g_clk           ,
input               g_resetn        ,

input               mstatus_mie     ,

input               mie_meie        ,
input               mie_mtie        ,
input               mie_msie        ,

input               ex_pending      ,
input               ti_pending      ,
input               sw_pending      ,

output reg          mip_meip        ,
output reg          mip_mtip        ,
output reg          mip_msip        ,

output wire         int_trap_req    ,
output wire [ 5:0]  int_trap_cause  ,
input  wire         int_trap_ack

);


`include "frv_common.vh"

always @(posedge g_clk) begin
    if(!g_resetn) begin
        mip_meip <= 1'b0      ;
        mip_mtip <= 1'b0      ;
        mip_msip <= 1'b0      ;
    end else begin
        mip_meip <= ex_pending;
        mip_mtip <= ti_pending;
        mip_msip <= sw_pending;
    end
end

wire   raise_mei    = mstatus_mie && mie_meie && mip_meip;
wire   raise_mti    = mstatus_mie && mie_mtie && mip_mtip;
wire   raise_msi    = mstatus_mie && mie_msie && mip_msip;

assign int_trap_req = raise_mei || raise_mti || raise_msi;

assign int_trap_cause = 
    raise_mei   ? TRAP_INT_MEI  :
    raise_mti   ? TRAP_INT_MTI  :
    raise_msi   ? TRAP_INT_MSI  :
                             0  ;

endmodule