data/full_repos/permissive/128566293/Sources/verilog/VfD_heartbeat.v
1: b'%Warning-WIDTH: data/full_repos/permissive/128566293/Sources/verilog/VfD_heartbeat.v:35: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'r_divider\' generates 32 bits.\n                                                                                       : ... In instance VfD_heartbeat\n    assign w_zero = (r_divider)? 0: 1;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module VfD_heartbeat (

    output          o_led,

    input           clk,
    input           rst);


    parameter       f_clkin = 12_000_000;



    localparam      c_length = 5;
    localparam      c_pattern = 'b10100;

    wire            w_zero;
    reg [c_length-1:0] r_rotatereg;

always @ (posedge rst or posedge clk)
begin
    if (rst)
        r_rotatereg <= c_pattern;
    else

        r_rotatereg <= (w_zero)? {r_rotatereg[0], r_rotatereg[c_length-1:1]}: r_rotatereg;
end


assign o_led = r_rotatereg[0];



    integer         r_divider = 0;

    assign w_zero = (r_divider)? 0: 1;

always @ (posedge clk)
begin
    if (w_zero)

        r_divider <= (f_clkin / c_length);
    else

        r_divider <= r_divider - 1;
end

endmodule
module VfD_heartbeat (

    output          o_led,

    input           clk,
    input           rst);



    parameter       f_clkin = 12_000_000;



    localparam      c_length = 5;
    localparam      c_pattern = 'b10100;

    wire            w_zero;
    reg [c_length-1:0] r_rotatereg;

always @ (posedge rst or posedge clk)
begin
    if (rst)
        r_rotatereg <= c_pattern;
    else

        r_rotatereg <= (w_zero)? {r_rotatereg[0], r_rotatereg[c_length-1:1]}: r_rotatereg;
end


assign o_led = r_rotatereg[0];



    integer         r_divider = 0;

    assign w_zero = (r_divider)? 0: 1;

always @ (posedge clk)
begin
    if (w_zero)

        r_divider <= (f_clkin / c_length);
    else

        r_divider <= r_divider - 1;
end

endmodule