data/full_repos/permissive/190595283/Modulos/LeftShift2.v
data/verilator_xmls/c489ad5e-9e1f-46c7-b647-c8f701906380.xml
module LeftShift2 (entrada,saida);
  input [31:0]entrada;
  output reg [31:0]saida;
  always @ ( entrada ) begin
    saida = (entrada << 2);
  end
endmodule
module LeftShift2 (entrada,saida);

  input [31:0]entrada;
  output reg [31:0]saida;
  always @ ( entrada ) begin
    saida = (entrada << 2);
  end
endmodule