data/full_repos/permissive/143278/ivltests/br985.v
 line:26: before: "i"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br985.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(spi_sdo !== 1\'b1)\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br985.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #1 if(spi_sdo !== 1\'b0)\n        ^\n%Error: data/full_repos/permissive/143278/ivltests/br985.v:23: Cannot find file containing module: \'bug3\'\nbug3 dut(sel, value, spi_sdo);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/bug3\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/bug3.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/bug3.sv\n             bug3\n             bug3.v\n             bug3.sv\n             obj_dir/bug3\n             obj_dir/bug3.v\n             obj_dir/bug3.sv\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br985.v:37: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                     : ... In instance br985_test\n        sel = i;\n            ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module br985_test;
logic [3:0] sel;
logic value, spi_sdo;
bug3 dut(sel, value, spi_sdo);

initial begin
    int i;
    sel = 4'b0000;

    #1 if(spi_sdo !== 1'b1)
    begin
        $display("FAILED");
        $finish();
    end

    for(i = 1; i < 16; i = i + 1)
    begin
        sel = i;
        #1 if(spi_sdo !== 1'b0)
        begin
            $display("FAILED");
            $finish();
        end
    end

    $display("PASSED");
end

endmodule
module br985_test;

logic [3:0] sel;
logic value, spi_sdo;
bug3 dut(sel, value, spi_sdo);

initial begin
    int i;
    sel = 4'b0000;

    #1 if(spi_sdo !== 1'b1)
    begin
        $display("FAILED");
        $finish();
    end

    for(i = 1; i < 16; i = i + 1)
    begin
        sel = i;
        #1 if(spi_sdo !== 1'b0)
        begin
            $display("FAILED");
            $finish();
        end
    end

    $display("PASSED");
end

endmodule