data/full_repos/permissive/196412397/ov7670_registers.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h0\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h1\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h2\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h3\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h4\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h5\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h6\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h7\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h8\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h9\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'ha\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'hb\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'hc\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'hd\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'he\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'hf\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h10\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h11\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h12\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h13\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h14\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h15\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h16\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h17\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h18\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h19\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h1a\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h1b\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h1c\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h1d\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h1e\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h1f\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/196412397/ov7670_registers.v:32: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'8\'h20\' generates 8 bits.\n                                                                          : ... In instance ov7670_registers\n        case (address)\n        ^~~~\n%Error: Exiting due to 33 warning(s)\n'
module ov7670_registers(
    input   clk,
    input   resend,
    input   advance,
    output [15:0] command,
    output  finished
);

reg [15:0] sreg;
reg [8:0] address = 'h0;

reg r_resend_old = 0;

always@(posedge clk) begin
    r_resend_old <= resend;
end


always@(posedge clk) begin
    if (r_resend_old == 1 && resend == 0 ) begin 
        address <= 'h0;
    end
    else if (advance == 1) begin
        address <= address + 1;
    end

        case (address)



                




				














				



				



         


            





            


                                  


                                  


                                   


                                  


                                   


                                  


                                   


                                  


                                  


                                  


                                  





            





            8'd00 :  sreg <= 16'h1280;
            8'd01 :  sreg <= 16'h1280;
            8'd02 :  sreg <= 16'h1204;
            8'd03 :  sreg <= 16'h1100;
            8'd04 :  sreg <= 16'h0C00;
            8'd05 :  sreg <= 16'h3E00;
            
            8'd06 :  sreg <= 16'h8C00;
            8'd07 :  sreg <= 16'h0400;
            8'd08 :  sreg <= 16'h4010;
            8'd09 :  sreg <= 16'h3a04;
            8'd10 :  sreg <= 16'h1438;
            	8'd11 : sreg <= 16'h4fb3;
				8'd12 : sreg <= 16'h50b3;
				8'd13 : sreg <= 16'h5100;
				8'd14 : sreg <= 16'h523d;
				8'd15 : sreg <= 16'h53a7;
				8'd16 : sreg <= 16'h54e4;

            8'd17 :  sreg <= 16'h581e;
            8'd18 :  sreg <= 16'h3dc0;
            
            8'd19 :  sreg <= 16'h1713;
            8'd20 :  sreg <= 16'h1801;
            8'd21 :  sreg <= 16'h32b6;
            
            8'd22 :  sreg <= 16'h1902;
            8'd23 :  sreg <= 16'h1A7a;
            8'd24 :  sreg <= 16'h030a;



            





            


                                  


                                  



          




                                  


                                   


                                  


                                   



            8'd25 :  sreg <= 16'h9100;  
            8'd26 :  sreg <= 16'h9600;  
                                  
            8'd27 :  sreg <= 16'h9a00;  
            8'd28 :  sreg <= 16'hb084;  
                                  
            8'd29 :  sreg <= 16'hb10c;  
            8'd30 :  sreg <= 16'hb20e;  
                                  
            8'd31 :  sreg <= 16'hb382;  
            8'd32 :  sreg <= 16'hb80a;  
 




                




				














				



				



         


            





            


                                  


                                  


                                   


                                  


                                   


                                  


                                   


                                  


                                  


                                  


                                  





            




























            



            






            





            
               default : sreg <= 16'hffff;
        endcase;

end

assign command = sreg;
assign finished = (sreg == 16'hffff) ? 1'b1 : 1'b0;

endmodule
module ov7670_registers(
    input   clk,
    input   resend,
    input   advance,
    output [15:0] command,
    output  finished
);


reg [15:0] sreg;
reg [8:0] address = 'h0;

reg r_resend_old = 0;

always@(posedge clk) begin
    r_resend_old <= resend;
end


always@(posedge clk) begin
    if (r_resend_old == 1 && resend == 0 ) begin 
        address <= 'h0;
    end
    else if (advance == 1) begin
        address <= address + 1;
    end

        case (address)



                




				














				



				



         


            





            


                                  


                                  


                                   


                                  


                                   


                                  


                                   


                                  


                                  


                                  


                                  





            





            8'd00 :  sreg <= 16'h1280;
            8'd01 :  sreg <= 16'h1280;
            8'd02 :  sreg <= 16'h1204;
            8'd03 :  sreg <= 16'h1100;
            8'd04 :  sreg <= 16'h0C00;
            8'd05 :  sreg <= 16'h3E00;
            
            8'd06 :  sreg <= 16'h8C00;
            8'd07 :  sreg <= 16'h0400;
            8'd08 :  sreg <= 16'h4010;
            8'd09 :  sreg <= 16'h3a04;
            8'd10 :  sreg <= 16'h1438;
            	8'd11 : sreg <= 16'h4fb3;
				8'd12 : sreg <= 16'h50b3;
				8'd13 : sreg <= 16'h5100;
				8'd14 : sreg <= 16'h523d;
				8'd15 : sreg <= 16'h53a7;
				8'd16 : sreg <= 16'h54e4;

            8'd17 :  sreg <= 16'h581e;
            8'd18 :  sreg <= 16'h3dc0;
            
            8'd19 :  sreg <= 16'h1713;
            8'd20 :  sreg <= 16'h1801;
            8'd21 :  sreg <= 16'h32b6;
            
            8'd22 :  sreg <= 16'h1902;
            8'd23 :  sreg <= 16'h1A7a;
            8'd24 :  sreg <= 16'h030a;



            





            


                                  


                                  



          




                                  


                                   


                                  


                                   



            8'd25 :  sreg <= 16'h9100;  
            8'd26 :  sreg <= 16'h9600;  
                                  
            8'd27 :  sreg <= 16'h9a00;  
            8'd28 :  sreg <= 16'hb084;  
                                  
            8'd29 :  sreg <= 16'hb10c;  
            8'd30 :  sreg <= 16'hb20e;  
                                  
            8'd31 :  sreg <= 16'hb382;  
            8'd32 :  sreg <= 16'hb80a;  
 




                




				














				



				



         


            





            


                                  


                                  


                                   


                                  


                                   


                                  


                                   


                                  


                                  


                                  


                                  





            




























            



            






            





            
               default : sreg <= 16'hffff;
        endcase;

end

assign command = sreg;
assign finished = (sreg == 16'hffff) ? 1'b1 : 1'b0;

endmodule