data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/SevenSegFourDigwithEnable.v
data/verilator_xmls/98fe016e-da0b-4998-b934-5897f6d1b6ba.xml
module SevenSegOneDigwithEnable(in, sevenSeg);
input [4:0] in;
output reg [7:0] sevenSeg;

always@(*) begin
	if(in[4])
		sevenSeg = 8'b11111111;
	else begin
		case(in[3:0])
			0:  sevenSeg = 8'b00000011;
			1:  sevenSeg = 8'b10011111;
			2:  sevenSeg = 8'b00100101;
			3:  sevenSeg = 8'b00001101;
			4:  sevenSeg = 8'b10011001;
			5:  sevenSeg = 8'b01001001;
			6:  sevenSeg = 8'b01000001;
			7:  sevenSeg = 8'b00011111;
			8:  sevenSeg = 8'b00000001;
			9:  sevenSeg = 8'b00001001;
			10: sevenSeg = 8'b00010001;
			11: sevenSeg = 8'b11000001;
			12: sevenSeg = 8'b01100011;
			13: sevenSeg = 8'b10000101;
			14: sevenSeg = 8'b01100001;
			15: sevenSeg = 8'b01110001;
		endcase
	end
end
endmodule
module SevenSegOneDigwithEnable(in, sevenSeg);

input [4:0] in;
output reg [7:0] sevenSeg;

always@(*) begin
	if(in[4])
		sevenSeg = 8'b11111111;
	else begin
		case(in[3:0])
			0:  sevenSeg = 8'b00000011;
			1:  sevenSeg = 8'b10011111;
			2:  sevenSeg = 8'b00100101;
			3:  sevenSeg = 8'b00001101;
			4:  sevenSeg = 8'b10011001;
			5:  sevenSeg = 8'b01001001;
			6:  sevenSeg = 8'b01000001;
			7:  sevenSeg = 8'b00011111;
			8:  sevenSeg = 8'b00000001;
			9:  sevenSeg = 8'b00001001;
			10: sevenSeg = 8'b00010001;
			11: sevenSeg = 8'b11000001;
			12: sevenSeg = 8'b01100011;
			13: sevenSeg = 8'b10000101;
			14: sevenSeg = 8'b01100001;
			15: sevenSeg = 8'b01110001;
		endcase
	end
end
endmodule