data/full_repos/permissive/11525292/fpga/fpga.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/11525292/fpga/fpga.v:34: Cannot find file containing module: 'dcm'\n dcm dcm(.CLK_IN(input_clk), .CLK_OUT(clk));  \n ^~~\n        ... Looked in:\n             data/full_repos/permissive/11525292/fpga,data/full_repos/permissive/11525292/dcm\n             data/full_repos/permissive/11525292/fpga,data/full_repos/permissive/11525292/dcm.v\n             data/full_repos/permissive/11525292/fpga,data/full_repos/permissive/11525292/dcm.sv\n             dcm\n             dcm.v\n             dcm.sv\n             obj_dir/dcm\n             obj_dir/dcm.v\n             obj_dir/dcm.sv\n%Error: data/full_repos/permissive/11525292/fpga/fpga.v:48: Cannot find file containing module: 'debounce'\n   debounce btn_db(.clk(clk), .in(btn_sync2[idx]), .out(btn_debounced[idx]));\n   ^~~~~~~~\n%Error: data/full_repos/permissive/11525292/fpga/fpga.v:56: Cannot find file containing module: 'sseg'\n sseg #(.N(16)) sseg(.clk(clk), .in(sseg_data), .c(seg), .an(an));\n ^~~~\n%Error: data/full_repos/permissive/11525292/fpga/fpga.v:72: Cannot find file containing module: 'uart_multibyte_transmitter'\n uart_multibyte_transmitter #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(5)) uart_mbtx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .uart_tx(RsTx));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11525292/fpga/fpga.v:93: Cannot find file containing module: 'uart_multibyte_receiver'\n uart_multibyte_receiver #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(6)) uart_mbrx(.clk(clk), .data(uart_rx_data), .valid(uart_rx_valid), .ack(1'b0), .uart_rx(RsRx2));\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11525292/fpga/fpga.v:106: Cannot find file containing module: 'dsha_finisher'\n   dsha_finisher #(.START_ROUND(idx)) dsha(.clk(clk), .X(X), .Y(Y), .in_nonce(in_nonce), .hash(_out_hash[idx]), .out_nonce(_out_nonce[idx]), .accepted(_dsha_accepted[idx]));\n   ^~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module fpga(
		input wire input_clk,
		input wire [7:0] sw,
		input wire [4:0] btn,
		output wire [7:0] led,
		output wire [7:0] seg,
		output wire [3:0] an,
		output wire RsTx,
		input wire RsRx
	);

	wire clk;
	dcm dcm(.CLK_IN(input_clk), .CLK_OUT(clk));

	assign led = sw;
	

	reg [4:0] btn_sync, btn_sync2;
	always @(posedge clk) begin
		{btn_sync, btn_sync2} <= {btn, btn_sync};
	end
	
	wire [4:0] btn_debounced;
	genvar idx;
	generate
		for (idx=0; idx<5; idx=idx+1) begin: debounce_btn
			debounce btn_db(.clk(clk), .in(btn_sync2[idx]), .out(btn_debounced[idx]));
		end
	endgenerate
	
	reg [4:0] btn_prev;
	
	wire [15:0] sseg_data;
	assign sseg_data = in_nonce[31:16];
	sseg #(.N(16)) sseg(.clk(clk), .in(sseg_data), .c(seg), .an(an));
	
	

	
	wire uart_tx_req, uart_tx_ready;
	wire [255:0] uart_tx_data;
	assign uart_tx_data[7:0] = 8'haa;
	assign uart_tx_data[39:8] = out_nonce;
	assign uart_tx_data[47:40] = 8'haa;
	assign uart_tx_data[255:192] = 64'hdead432987beefaa;
	assign uart_tx_req = success;
	uart_multibyte_transmitter #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(5)) uart_mbtx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .uart_tx(RsTx));
	

	reg RsRx1=1, RsRx2=1;
	always @(posedge clk) begin
		{RsRx1, RsRx2} <= {RsRx, RsRx1};
	end
	wire uart_rx_valid;
	wire [511:0] uart_rx_data;
	wire [255:0] X;
	wire [95:0] Y;
	assign X = uart_rx_data[255:0];
	assign Y = uart_rx_data[351:256];

	
	reg [31:0] in_nonce = 32'h0;
	
	always @(posedge clk) begin
		if (accepted) in_nonce <= in_nonce + 1;
	end
	
	uart_multibyte_receiver #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(6)) uart_mbrx(.clk(clk), .data(uart_rx_data), .valid(uart_rx_valid), .ack(1'b0), .uart_rx(RsRx2));
	
	
	reg [31:0] out_nonce;
	wire accepted, success;
	
	localparam NUM_COPIES = 4;
	wire [255:0] _out_hash[NUM_COPIES-1:0];
	wire [31:0] _out_nonce[NUM_COPIES-1:0];
	wire [NUM_COPIES-1:0] _dsha_accepted, _dsha_success;
	generate	
		for (idx = 0; idx < NUM_COPIES; idx = idx + 1) begin: block_dsha
			assign _dsha_success[idx] = (_out_hash[idx][255:224+8] == 0) && (sw[0] || (_out_hash[idx][231:224] == 0));
			dsha_finisher #(.START_ROUND(idx)) dsha(.clk(clk), .X(X), .Y(Y), .in_nonce(in_nonce), .hash(_out_hash[idx]), .out_nonce(_out_nonce[idx]), .accepted(_dsha_accepted[idx]));
		end
	endgenerate
	integer i;
	always @(*) begin
		out_nonce = _out_nonce[0];
		

		for (i = 1; i < NUM_COPIES; i = i + 1) begin
			if (_dsha_success[i]) begin
				out_nonce = _out_nonce[i];
			end
		end
	end
	assign accepted = (_dsha_accepted != 0);
	assign success = (_dsha_success != 0);
	

	
	
	
	always @(posedge clk) begin
		btn_prev <= btn_debounced;
	end
endmodule
module fpga(
		input wire input_clk,
		input wire [7:0] sw,
		input wire [4:0] btn,
		output wire [7:0] led,
		output wire [7:0] seg,
		output wire [3:0] an,
		output wire RsTx,
		input wire RsRx
	);


	wire clk;
	dcm dcm(.CLK_IN(input_clk), .CLK_OUT(clk));

	assign led = sw;
	

	reg [4:0] btn_sync, btn_sync2;
	always @(posedge clk) begin
		{btn_sync, btn_sync2} <= {btn, btn_sync};
	end
	
	wire [4:0] btn_debounced;
	genvar idx;
	generate
		for (idx=0; idx<5; idx=idx+1) begin: debounce_btn
			debounce btn_db(.clk(clk), .in(btn_sync2[idx]), .out(btn_debounced[idx]));
		end
	endgenerate
	
	reg [4:0] btn_prev;
	
	wire [15:0] sseg_data;
	assign sseg_data = in_nonce[31:16];
	sseg #(.N(16)) sseg(.clk(clk), .in(sseg_data), .c(seg), .an(an));
	
	

	
	wire uart_tx_req, uart_tx_ready;
	wire [255:0] uart_tx_data;
	assign uart_tx_data[7:0] = 8'haa;
	assign uart_tx_data[39:8] = out_nonce;
	assign uart_tx_data[47:40] = 8'haa;
	assign uart_tx_data[255:192] = 64'hdead432987beefaa;
	assign uart_tx_req = success;
	uart_multibyte_transmitter #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(5)) uart_mbtx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .uart_tx(RsTx));
	

	reg RsRx1=1, RsRx2=1;
	always @(posedge clk) begin
		{RsRx1, RsRx2} <= {RsRx, RsRx1};
	end
	wire uart_rx_valid;
	wire [511:0] uart_rx_data;
	wire [255:0] X;
	wire [95:0] Y;
	assign X = uart_rx_data[255:0];
	assign Y = uart_rx_data[351:256];

	
	reg [31:0] in_nonce = 32'h0;
	
	always @(posedge clk) begin
		if (accepted) in_nonce <= in_nonce + 1;
	end
	
	uart_multibyte_receiver #(.CLK_CYCLES(694), .MSG_LOG_WIDTH(6)) uart_mbrx(.clk(clk), .data(uart_rx_data), .valid(uart_rx_valid), .ack(1'b0), .uart_rx(RsRx2));
	
	
	reg [31:0] out_nonce;
	wire accepted, success;
	
	localparam NUM_COPIES = 4;
	wire [255:0] _out_hash[NUM_COPIES-1:0];
	wire [31:0] _out_nonce[NUM_COPIES-1:0];
	wire [NUM_COPIES-1:0] _dsha_accepted, _dsha_success;
	generate	
		for (idx = 0; idx < NUM_COPIES; idx = idx + 1) begin: block_dsha
			assign _dsha_success[idx] = (_out_hash[idx][255:224+8] == 0) && (sw[0] || (_out_hash[idx][231:224] == 0));
			dsha_finisher #(.START_ROUND(idx)) dsha(.clk(clk), .X(X), .Y(Y), .in_nonce(in_nonce), .hash(_out_hash[idx]), .out_nonce(_out_nonce[idx]), .accepted(_dsha_accepted[idx]));
		end
	endgenerate
	integer i;
	always @(*) begin
		out_nonce = _out_nonce[0];
		

		for (i = 1; i < NUM_COPIES; i = i + 1) begin
			if (_dsha_success[i]) begin
				out_nonce = _out_nonce[i];
			end
		end
	end
	assign accepted = (_dsha_accepted != 0);
	assign success = (_dsha_success != 0);
	

	
	
	
	always @(posedge clk) begin
		btn_prev <= btn_debounced;
	end
endmodule