data/full_repos/permissive/106408053/verilog/stubs.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:151: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/stubs.v:161: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #0.1; O = (S) ? CI : DI; end\n                ^\n%Warning-MULTITOP: data/full_repos/permissive/106408053/verilog/stubs.v:13: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                          : ... Top module \'BUFG\'\nmodule BUFG(I,O);\n       ^~~~\n                                                                          : ... Top module \'BUFGMUX\'\nmodule BUFGMUX(O,I0,I1,S);\n       ^~~~~~~\n                                                                          : ... Top module \'DCM\'\nmodule DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);\n       ^~~\n                                                                          : ... Top module \'ODDR2\'\nmodule ODDR2(Q,D0,D1,C0,C1);\n       ^~~~~\n                                                                          : ... Top module \'RAMB16_S9\'\nmodule RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);\n       ^~~~~~~~~\n                                                                          : ... Top module \'RAM16X4S\'\nmodule RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);\n       ^~~~~~~~\n                                                                          : ... Top module \'SRLC16E\'\nmodule SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);\n       ^~~~~~~\n                                                                          : ... Top module \'MUXCY\'\nmodule MUXCY (S,CI,DI,O);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/stubs.v:143: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                                        : ... In instance SRLC16E\n  if (dly_CE) mem = {mem,dly_D};\n                  ^\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ODDR2(Q,D0,D1,C0,C1);
input D0,D1,C0,C1;
output Q;
reg Q;
initial Q=0;
always @(posedge C0) Q=D0;
always @(posedge C1) Q=D1;
endmodule
module ODDR2(Q,D0,D1,C0,C1);

input D0,D1,C0,C1;
output Q;
reg Q;
initial Q=0;
always @(posedge C0) Q=D0;
always @(posedge C1) Q=D1;
endmodule