data/full_repos/permissive/20270692/labs/lab11/sram/sram_fifo_tb.v
1: b'%Error: data/full_repos/permissive/20270692/labs/lab11/sram/sram_fifo_tb.v:11: Cannot find include file: sram_fifo.v\n`include "sram_fifo.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab11/sram,data/full_repos/permissive/20270692/sram_fifo.v\n             data/full_repos/permissive/20270692/labs/lab11/sram,data/full_repos/permissive/20270692/sram_fifo.v.v\n             data/full_repos/permissive/20270692/labs/lab11/sram,data/full_repos/permissive/20270692/sram_fifo.v.sv\n             sram_fifo.v\n             sram_fifo.v.v\n             sram_fifo.v.sv\n             obj_dir/sram_fifo.v\n             obj_dir/sram_fifo.v.v\n             obj_dir/sram_fifo.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/sram/sram_fifo_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    forever #5 clk=~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20270692/labs/lab11/sram/sram_fifo_tb.v:42: syntax error, unexpected \'@\'\n      @(posedge clk); begin  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/sram/sram_fifo_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/sram/sram_fifo_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #5 inputPacket = {bits{1\'b1}}; writeMode = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/sram/sram_fifo_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #80 writeMode = 0; readMode = 1; inputPacket = {bits{1\'b0}};\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/sram/sram_fifo_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #90 readMode = 0;\n    ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n'
module sram_fifo_tb (
    readMode,
    writeMode,
    inputPacket
  );

  parameter bits = 8;

  output readMode, writeMode;
  reg readMode, writeMode;
  reg readModeQ;

  output [bits-1:0] inputPacket;
  reg [bits-1:0] inputPacket;

  reg clk, rst;
  wire [bits-1:0] outputPacket;

  SRAM_fifo SRAM (readMode, writeMode, inputPacket, outputPacket, clk, rst);

  initial
  begin
    clk=0;
    forever #5 clk=~clk;
  end

  initial
  begin
    forever begin
      @(posedge clk); begin
        $display("time=%04d RW=%b%b I=%h O=%h clk=%b", $time,
            readModeQ, writeMode, inputPacket, outputPacket, clk);
        readModeQ = readMode;
      end
    end
  end

  initial
  begin

    rst = 1;
    readMode = 0;
    readModeQ = 0;
    writeMode = 0;
    #5 rst = 0;
    #5 inputPacket = {bits{1'b1}}; writeMode = 1;
    #80 writeMode = 0; readMode = 1; inputPacket = {bits{1'b0}};
    #90 readMode = 0;
    if (outputPacket === {bits{1'b1}}) begin
      $display("Pass");
    end else begin
      $display("Fail");
    end
    $finish;
  end

endmodule
module sram_fifo_tb (
    readMode,
    writeMode,
    inputPacket
  );


  parameter bits = 8;

  output readMode, writeMode;
  reg readMode, writeMode;
  reg readModeQ;

  output [bits-1:0] inputPacket;
  reg [bits-1:0] inputPacket;

  reg clk, rst;
  wire [bits-1:0] outputPacket;

  SRAM_fifo SRAM (readMode, writeMode, inputPacket, outputPacket, clk, rst);

  initial
  begin
    clk=0;
    forever #5 clk=~clk;
  end

  initial
  begin
    forever begin
      @(posedge clk); begin
        $display("time=%04d RW=%b%b I=%h O=%h clk=%b", $time,
            readModeQ, writeMode, inputPacket, outputPacket, clk);
        readModeQ = readMode;
      end
    end
  end

  initial
  begin

    rst = 1;
    readMode = 0;
    readModeQ = 0;
    writeMode = 0;
    #5 rst = 0;
    #5 inputPacket = {bits{1'b1}}; writeMode = 1;
    #80 writeMode = 0; readMode = 1; inputPacket = {bits{1'b0}};
    #90 readMode = 0;
    if (outputPacket === {bits{1'b1}}) begin
      $display("Pass");
    end else begin
      $display("Fail");
    end
    $finish;
  end

endmodule