data/full_repos/permissive/104504209/PGM8755/src/programmer.v
data/verilator_xmls/0420d440-0505-41e4-ae05-8e6c726308a7.xml
module delay_cycles(input clk, rst, en, output rdy);
	parameter WAIT_CYCLES = 1000000;
	parameter CTR_SIZE = $clog2(WAIT_CYCLES);
	
	reg[CTR_SIZE-1:0] counter;
	
	always@(posedge clk) begin
		if(rst || ~en) counter <= 0;
		else counter <= counter + 1'b1;
	end
	
	assign rdy = counter == WAIT_CYCLES;
	
endmodule
module delay_cycles(input clk, rst, en, output rdy);

	parameter WAIT_CYCLES = 1000000;
	parameter CTR_SIZE = $clog2(WAIT_CYCLES);
	
	reg[CTR_SIZE-1:0] counter;
	
	always@(posedge clk) begin
		if(rst || ~en) counter <= 0;
		else counter <= counter + 1'b1;
	end
	
	assign rdy = counter == WAIT_CYCLES;
	
endmodule