data/full_repos/permissive/152986713/ice40/starfield.v
1: b'%Error: data/full_repos/permissive/152986713/ice40/starfield.v:2: Cannot find include file: hvsync_generator.v\n`include "hvsync_generator.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v.v\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v.sv\n             hvsync_generator.v\n             hvsync_generator.v.v\n             hvsync_generator.v.sv\n             obj_dir/hvsync_generator.v\n             obj_dir/hvsync_generator.v.v\n             obj_dir/hvsync_generator.v.sv\n%Error: data/full_repos/permissive/152986713/ice40/starfield.v:3: Cannot find include file: lfsr.v\n`include "lfsr.v" \n         ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module starfield_top(clk, reset, out);

  input clk, reset;
  output [1:0] out;
  wire hsync, vsync;
  wire display_on;
  wire [8:0] hpos;
  wire [8:0] vpos;
  wire [15:0] lfsr;

  reg clk2;
  always @(posedge clk) begin
    clk2 <= !clk2;
  end

  hvsync_generator #(256,60,40,25) hvsync_gen(
    .clk(clk2),
    .reset(reset),
    .hsync(hsync),
    .vsync(vsync),
    .display_on(display_on),
    .hpos(hpos),
    .vpos(vpos)
  );
  
  wire star_enable = !hpos[8] & !vpos[8];
  

  LFSR #(16,16'b1000000001011,0) lfsr_gen(
    .clk(clk2),
    .reset(reset),
    .enable(star_enable),
    .lfsr(lfsr));

  wire star_on = &lfsr[15:9];

  assign out = (hsync||vsync) ? 0 : star_on ? (1+lfsr[1]+lfsr[2]) : 1;

endmodule
module starfield_top(clk, reset, out);


  input clk, reset;
  output [1:0] out;
  wire hsync, vsync;
  wire display_on;
  wire [8:0] hpos;
  wire [8:0] vpos;
  wire [15:0] lfsr;

  reg clk2;
  always @(posedge clk) begin
    clk2 <= !clk2;
  end

  hvsync_generator #(256,60,40,25) hvsync_gen(
    .clk(clk2),
    .reset(reset),
    .hsync(hsync),
    .vsync(vsync),
    .display_on(display_on),
    .hpos(hpos),
    .vpos(vpos)
  );
  
  wire star_enable = !hpos[8] & !vpos[8];
  

  LFSR #(16,16'b1000000001011,0) lfsr_gen(
    .clk(clk2),
    .reset(reset),
    .enable(star_enable),
    .lfsr(lfsr));

  wire star_on = &lfsr[15:9];

  assign out = (hsync||vsync) ? 0 : star_on ? (1+lfsr[1]+lfsr[2]) : 1;

endmodule