data/full_repos/permissive/123218339/amISink.v
data/verilator_xmls/c22cfdb1-a6bb-4bb7-a435-d07fd64a6bdd.xml
module amISink(clock, nrst, start, address, data_in, MY_NODE_ID, forAggregation, done);
    input clock, nrst, start;
    input [`WORD_WIDTH-1:0] data_in, MY_NODE_ID;
    output forAggregation, done;
    output [`WORD_WIDTH-1:0] address;


    reg forAggregation_buf, done_buf;
    reg [`WORD_WIDTH-1:0] address_count;
    
    always @ (posedge clock) begin
        if (!nrst) begin
            forAggregation_buf <= 0;
            done_buf <= 0;
            address_count <= 16'h8;
        end
        else begin
            if (start && !done_buf) begin

                if (MY_NODE_ID == data_in) begin
                    forAggregation_buf = 1;
                    done_buf = 1;

                end

                if (address_count == 16'h26)
                    done_buf = 1;
                else
                    address_count = address_count + 2;          
            end
        end
    end

    assign forAggregation = forAggregation_buf;
    assign done = done_buf;
    assign address = address_count;
endmodule
module amISink(clock, nrst, start, address, data_in, MY_NODE_ID, forAggregation, done);

    input clock, nrst, start;
    input [`WORD_WIDTH-1:0] data_in, MY_NODE_ID;
    output forAggregation, done;
    output [`WORD_WIDTH-1:0] address;


    reg forAggregation_buf, done_buf;
    reg [`WORD_WIDTH-1:0] address_count;
    
    always @ (posedge clock) begin
        if (!nrst) begin
            forAggregation_buf <= 0;
            done_buf <= 0;
            address_count <= 16'h8;
        end
        else begin
            if (start && !done_buf) begin

                if (MY_NODE_ID == data_in) begin
                    forAggregation_buf = 1;
                    done_buf = 1;

                end

                if (address_count == 16'h26)
                    done_buf = 1;
                else
                    address_count = address_count + 2;          
            end
        end
    end

    assign forAggregation = forAggregation_buf;
    assign done = done_buf;
    assign address = address_count;
endmodule