data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/sm2201_interface_board_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/sm2201_interface_board_testbench.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #60 isa_clk <= ~isa_clk; \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/sm2201_interface_board_testbench.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #120 counter <= counter + 1;\n        ^\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/sm2201_interface_board_testbench.v:60: Cannot find file containing module: \'sm2201_interface_board\'\n    sm2201_interface_board\n    ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/sm2201_interface_board\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/sm2201_interface_board.v\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/sm2201_interface_board.sv\n             sm2201_interface_board\n             sm2201_interface_board.v\n             sm2201_interface_board.sv\n             obj_dir/sm2201_interface_board\n             obj_dir/sm2201_interface_board.v\n             obj_dir/sm2201_interface_board.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sm2201_interface_board_testbench;


    reg isa_clk;
    reg isa_ior;
    wire isa_iow;
    reg isa_reset;
    reg isa_ale;
    reg isa_aen;
    wire q_r_debug;

    reg [9:0] isa_addr;
    wire [7:0] isa_data;
    reg [31:0] counter;
    reg [1:0] operation;


    wire [7:0] isa_irq;
    wire isa_chrdy;


    reg cb_prr;
    reg cb_zk4;
    wire [15:0] cb_data;
    reg [15:0] cb_data_out;
    wire [15:0] cb_data_in;
    wire [11:0] cb_addr;
    reg [7:0] isa_data_out;
    wire [7:0] isa_data_in;

    assign cb_data = q_r_debug == 1'b0 ? cb_data_out : cb_data_in;
    assign isa_data = q_r_debug == 1'b1 ? isa_data_out :isa_data_in;
    assign isa_iow = ~ isa_ior;


    sm2201_interface_board
    uut (

        .isa_clk(isa_clk), 
        .isa_reset(isa_reset), 
        .isa_ior(isa_ior), 
        .isa_iow(isa_iow), 
        .isa_addr(isa_addr),
        .isa_data(isa_data),
        .isa_ale(isa_ale),
        .isa_aen(isa_aen),

        .isa_chrdy(isa_chrdy),

        .q_r_debug(q_r_debug),

        .cb_prr(cb_prr),
        .cb_zk4(cb_zk4),
        .cb_cx1(cb_cx1),
        .cb_data(cb_data),
        .cb_addr(cb_addr)
    );

    initial 
    begin

        isa_reset <= 0;
        isa_clk <= 0;
        isa_ior <= 1;
        isa_addr <= 240;
        isa_ale <= 0;
        isa_aen <= 0;

        cb_prr <= 1;
        cb_zk4 <= 1;
        isa_data_out <= 8'b00011000;
        cb_data_out <= 16'b1111111111111111;
        counter <= 0;
        operation <= 0;
    end
    

    always
    begin
        #60 isa_clk <= ~isa_clk; 
        #120 counter <= counter + 1;

        if (counter == 10) 
        begin
            isa_ale <= 1;
        end
        else if (counter == 20)
        begin
            if (operation == 0)
                isa_ior <= 0;
        end
        else if (counter == 44)
        begin
            isa_ale <= 0;
        end

        else if (counter == 146)
        begin
            if (operation == 0)
                isa_ior <= 1;

            counter <= 10;
            operation <= operation + 1;
            if (operation == 1)
            begin
                isa_addr <= isa_addr + 1;
                operation <= 0;
            end

            if (isa_addr == 318)
            begin
                isa_addr <= 256;
            end
        end
    end
endmodule
module sm2201_interface_board_testbench;



    reg isa_clk;
    reg isa_ior;
    wire isa_iow;
    reg isa_reset;
    reg isa_ale;
    reg isa_aen;
    wire q_r_debug;

    reg [9:0] isa_addr;
    wire [7:0] isa_data;
    reg [31:0] counter;
    reg [1:0] operation;


    wire [7:0] isa_irq;
    wire isa_chrdy;


    reg cb_prr;
    reg cb_zk4;
    wire [15:0] cb_data;
    reg [15:0] cb_data_out;
    wire [15:0] cb_data_in;
    wire [11:0] cb_addr;
    reg [7:0] isa_data_out;
    wire [7:0] isa_data_in;

    assign cb_data = q_r_debug == 1'b0 ? cb_data_out : cb_data_in;
    assign isa_data = q_r_debug == 1'b1 ? isa_data_out :isa_data_in;
    assign isa_iow = ~ isa_ior;


    sm2201_interface_board
    uut (

        .isa_clk(isa_clk), 
        .isa_reset(isa_reset), 
        .isa_ior(isa_ior), 
        .isa_iow(isa_iow), 
        .isa_addr(isa_addr),
        .isa_data(isa_data),
        .isa_ale(isa_ale),
        .isa_aen(isa_aen),

        .isa_chrdy(isa_chrdy),

        .q_r_debug(q_r_debug),

        .cb_prr(cb_prr),
        .cb_zk4(cb_zk4),
        .cb_cx1(cb_cx1),
        .cb_data(cb_data),
        .cb_addr(cb_addr)
    );

    initial 
    begin

        isa_reset <= 0;
        isa_clk <= 0;
        isa_ior <= 1;
        isa_addr <= 240;
        isa_ale <= 0;
        isa_aen <= 0;

        cb_prr <= 1;
        cb_zk4 <= 1;
        isa_data_out <= 8'b00011000;
        cb_data_out <= 16'b1111111111111111;
        counter <= 0;
        operation <= 0;
    end
    

    always
    begin
        #60 isa_clk <= ~isa_clk; 
        #120 counter <= counter + 1;

        if (counter == 10) 
        begin
            isa_ale <= 1;
        end
        else if (counter == 20)
        begin
            if (operation == 0)
                isa_ior <= 0;
        end
        else if (counter == 44)
        begin
            isa_ale <= 0;
        end

        else if (counter == 146)
        begin
            if (operation == 0)
                isa_ior <= 1;

            counter <= 10;
            operation <= operation + 1;
            if (operation == 1)
            begin
                isa_addr <= isa_addr + 1;
                operation <= 0;
            end

            if (isa_addr == 318)
            begin
                isa_addr <= 256;
            end
        end
    end
endmodule