data/full_repos/permissive/133161058/cla.rca/hdl/mem.v
 line:33: before: ":"
1: b"%Error: data/full_repos/permissive/133161058/cla.rca/hdl/mem.v:33: Define or directive not defined: '`REG_SIZE'\n    output [`REG_SIZE:0] tanangle ;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/mem.v:33: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n    output [`REG_SIZE:0] tanangle ;\n                     ^\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/mem.v:36: Define or directive not defined: '`REG_SIZE'\nreg [`REG_SIZE:0] tanangle ;\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/mem.v:36: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\nreg [`REG_SIZE:0] tanangle ;\n              ^\n%Error: Exiting due to 4 error(s)\n"
module MEM (iteration, tanangle ) ;


    output [`REG_SIZE:0] tanangle ;
    input [3:0] iteration ;

reg [`REG_SIZE:0] tanangle ;

always @ (iteration)

   case (iteration)



    4'b0000: tanangle <= 16'b00101101_00000000 ;
    4'b0001: tanangle <= 16'b00011010_11111111 ;
    4'b0010: tanangle <= 16'b00001110_00001111 ;
    4'b0011: tanangle <= 16'b00000111_00111111 ;
    4'b0100: tanangle <= 16'b00000011_11111111 ;
    4'b0101: tanangle <= 16'b00000001_11111111 ;
    4'b0110: tanangle <= 16'b00000000_11111111 ;
    4'b0111: tanangle <= 16'b00000000_01111111 ;
    4'b1000: tanangle <= 16'b00000000_00111111 ;
    4'b1001: tanangle <= 16'b00000000_00011111 ;
    4'b1010: tanangle <= 16'b00000000_00001111 ;
    4'b1011: tanangle <= 16'b00000000_00000111 ;
    4'b1100: tanangle <= 16'b00000000_00000011 ;
    4'b1101: tanangle <= 16'b00000000_00000001 ;
    4'b1110: tanangle <= 16'b00000000_00000000 ;
    4'b1111: tanangle <= 16'b00000000_00000000 ;

   endcase

endmodule
module MEM (iteration, tanangle ) ;



    output [`REG_SIZE:0] tanangle ;
    input [3:0] iteration ;

reg [`REG_SIZE:0] tanangle ;

always @ (iteration)

   case (iteration)



    4'b0000: tanangle <= 16'b00101101_00000000 ;
    4'b0001: tanangle <= 16'b00011010_11111111 ;
    4'b0010: tanangle <= 16'b00001110_00001111 ;
    4'b0011: tanangle <= 16'b00000111_00111111 ;
    4'b0100: tanangle <= 16'b00000011_11111111 ;
    4'b0101: tanangle <= 16'b00000001_11111111 ;
    4'b0110: tanangle <= 16'b00000000_11111111 ;
    4'b0111: tanangle <= 16'b00000000_01111111 ;
    4'b1000: tanangle <= 16'b00000000_00111111 ;
    4'b1001: tanangle <= 16'b00000000_00011111 ;
    4'b1010: tanangle <= 16'b00000000_00001111 ;
    4'b1011: tanangle <= 16'b00000000_00000111 ;
    4'b1100: tanangle <= 16'b00000000_00000011 ;
    4'b1101: tanangle <= 16'b00000000_00000001 ;
    4'b1110: tanangle <= 16'b00000000_00000000 ;
    4'b1111: tanangle <= 16'b00000000_00000000 ;

   endcase

endmodule