data/full_repos/permissive/181665138/verilog/capitolo_ii/NAND.v
data/verilator_xmls/54a5dcf9-7b12-43e7-bd70-095eab288b51.xml
module NAND(x1, x0, z);
    input x1;
    input x0;
    output z;

    assign z = ({x1,x0} == 'B11)?0:1;
    



endmodule
module NAND(x1, x0, z);

    input x1;
    input x0;
    output z;

    assign z = ({x1,x0} == 'B11)?0:1;
    



endmodule