data/full_repos/permissive/173670949/upduino/blink_led/rgb_blink.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/173670949/upduino/blink_led/rgb_blink.v:55: Multiple top level modules\n                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                        : ... Top module \'rgb_blink\'\nmodule rgb_blink #(\n       ^~~~~~~~~\n                                                                                        : ... Top module \'Mux4In1Out\'\nmodule Mux4In1Out\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/173670949/upduino/blink_led/rgb_blink.v:18: Cannot find file containing module: \'SAWTOOTH\'\n    SAWTOOTH #(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173670949/upduino/blink_led,data/full_repos/permissive/173670949/SAWTOOTH\n             data/full_repos/permissive/173670949/upduino/blink_led,data/full_repos/permissive/173670949/SAWTOOTH.v\n             data/full_repos/permissive/173670949/upduino/blink_led,data/full_repos/permissive/173670949/SAWTOOTH.sv\n             SAWTOOTH\n             SAWTOOTH.v\n             SAWTOOTH.sv\n             obj_dir/SAWTOOTH\n             obj_dir/SAWTOOTH.v\n             obj_dir/SAWTOOTH.sv\n%Error: data/full_repos/permissive/173670949/upduino/blink_led/rgb_blink.v:28: Cannot find file containing module: \'PWM\'\n    PWM #(\n    ^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module Mux4Out1In
(
    output reg [3:0] outputs,
    input      [1:0] output_select,
    input            in
);

    always @(*) begin
        outputs                = {1'b0, 1'b0, 1'b0, 1'b0};
        outputs[output_select] = in;
        
    end

endmodule
module Mux4Out1In
(
    output reg [3:0] outputs,
    input      [1:0] output_select,
    input            in
);


    always @(*) begin
        outputs                = {1'b0, 1'b0, 1'b0, 1'b0};
        outputs[output_select] = in;
        
    end

endmodule