data/full_repos/permissive/209997170/Sound/pwm_tutorial/source/counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/pwm_tutorial/source/counter.v:21: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance counter\n      ctr_q <= 1\'b0;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module counter (
    input clk,
    input rst,
    output reg [7:0] value
  );
 
  reg[24:0] ctr_d, ctr_q;
 
  always @(ctr_q) begin
    ctr_d = ctr_q + 1'b1;
 
    if (ctr_q[24])
      value = ~ctr_q[23:16];
    else
      value = ctr_q[23:16];
 
  end
 
  always @(posedge clk) begin
    if (rst) begin
      ctr_q <= 1'b0;
    end else begin
      ctr_q <= ctr_d;
    end
  end
 
endmodule
module counter (
    input clk,
    input rst,
    output reg [7:0] value
  );

 
  reg[24:0] ctr_d, ctr_q;
 
  always @(ctr_q) begin
    ctr_d = ctr_q + 1'b1;
 
    if (ctr_q[24])
      value = ~ctr_q[23:16];
    else
      value = ctr_q[23:16];
 
  end
 
  always @(posedge clk) begin
    if (rst) begin
      ctr_q <= 1'b0;
    end else begin
      ctr_q <= ctr_d;
    end
  end
 
endmodule