data/full_repos/permissive/159016511/src/rtl/core/fetch.v
None: at end of input
1: b'%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:27: Cannot find include file: core_defines.vh\n`include "core_defines.vh" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159016511/src/rtl/core,data/full_repos/permissive/159016511/core_defines.vh\n             data/full_repos/permissive/159016511/src/rtl/core,data/full_repos/permissive/159016511/core_defines.vh.v\n             data/full_repos/permissive/159016511/src/rtl/core,data/full_repos/permissive/159016511/core_defines.vh.sv\n             core_defines.vh\n             core_defines.vh.v\n             core_defines.vh.sv\n             obj_dir/core_defines.vh\n             obj_dir/core_defines.vh.v\n             obj_dir/core_defines.vh.sv\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:33: Define or directive not defined: \'`ADDR_WIDTH\'\ninput wire [`ADDR_WIDTH - 1 : 0] boot_addr,   \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:39: Define or directive not defined: \'`ADDR_WIDTH\'\noutput reg [`ADDR_WIDTH - 1 : 0] pc_dec,   \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:43: Define or directive not defined: \'`INSTR_WIDTH\'\noutput reg [`INSTR_WIDTH - 1 : 0] instr_dec,   \n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:44: Define or directive not defined: \'`DATA_WIDTH\'\ninput wire signed [`DATA_WIDTH - 1 : 0] src_data1_ex,  \n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:45: Define or directive not defined: \'`DATA_WIDTH\'\ninput wire signed [`DATA_WIDTH - 1 : 0] imm_ex,   \n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:46: Define or directive not defined: \'`DATA_WIDTH\'\ninput wire signed [`DATA_WIDTH - 1 : 0] imm_dec,  \n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:47: Define or directive not defined: \'`ADDR_WIDTH\'\ninput wire [`ADDR_WIDTH - 1 : 0] pc_ex,    \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:54: Define or directive not defined: \'`ADDR_WIDTH\'\noutput reg [`ADDR_WIDTH - 1 : 0] next_pc,   \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:56: Define or directive not defined: \'`INSTR_WIDTH\'\ninput wire [`INSTR_WIDTH - 1 : 0] instr_read_data,   \n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:60: Define or directive not defined: \'`ADDR_WIDTH\'\noutput reg [`ADDR_WIDTH - 1 : 0] pc, \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:63: Define or directive not defined: \'`ADDR_WIDTH\'\noutput wire [`ADDR_WIDTH - 1 : 0] fault_pc,   \n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:65: Define or directive not defined: \'`ADDR_WIDTH\'\ninput wire  [`ADDR_WIDTH - 1 : 0] vector_addr,   \n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:66: Define or directive not defined: \'`ADDR_WIDTH\'\ninput wire [`ADDR_WIDTH - 1 : 0] mepc    \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:171: Define or directive not defined: \'`ADDR_WIDTH\'\nreg [`ADDR_WIDTH - 1 : 0] addr_adder_res;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:199: Define or directive not defined: \'`ADDR_WIDTH\'\nreg  [`ADDR_WIDTH - 1 : 0] addr_adder_res_r;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:204: Define or directive not defined: \'`INSTR_WIDTH\'\n  addr_adder_res_r <= {`INSTR_WIDTH{1\'b0}}; \n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:208: Define or directive not defined: \'`INSTR_WIDTH\'\n  addr_adder_res_r <= {`INSTR_WIDTH{1\'b0}}; \n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:216: Define or directive not defined: \'`ADDR_WIDTH\'\nwire  [`ADDR_WIDTH - 1 : 0] addr_adder_res_c = (branch_taken_ex_r || jal_dec_r || jalr_ex_r )? addr_adder_res_r : addr_adder_res;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:305: Define or directive not defined: \'`INSTR_WIDTH\'\n  instr_dec <= {`INSTR_WIDTH{1\'b0}};\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:313: Define or directive not defined: \'`INSTR_WIDTH\'\n   instr_dec <= {`INSTR_WIDTH{1\'b0}};\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/core/fetch.v:329: Define or directive not defined: \'`ADDR_WIDTH\'\nassign fault_pc = pc_misaligned ? pc : {`ADDR_WIDTH{1\'b0}};\n                                        ^~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module fetch (

input wire cpu_clk,
input wire cpu_rstn,
input wire [`ADDR_WIDTH - 1 : 0] boot_addr,


input wire jal_dec,
input wire jalr_ex,
input wire fence_dec,
output reg [`ADDR_WIDTH - 1 : 0] pc_dec,
input wire dec_valid,
input wire dec_ready,
output reg if_valid,
output reg [`INSTR_WIDTH - 1 : 0] instr_dec,
input wire signed [`DATA_WIDTH - 1 : 0] src_data1_ex,
input wire signed [`DATA_WIDTH - 1 : 0] imm_ex,
input wire signed [`DATA_WIDTH - 1 : 0] imm_dec,
input wire [`ADDR_WIDTH - 1 : 0] pc_ex,


input wire ex_ready,
input wire branch_taken_ex,


output reg [`ADDR_WIDTH - 1 : 0] next_pc,
input wire instr_read_data_valid,
input wire [`INSTR_WIDTH - 1 : 0] instr_read_data,
input wire addr_AHB,


output reg [`ADDR_WIDTH - 1 : 0] pc,	
input wire mret,
output wire pc_misaligned,
output wire [`ADDR_WIDTH - 1 : 0] fault_pc,
input wire trap,
input wire  [`ADDR_WIDTH - 1 : 0] vector_addr,
input wire [`ADDR_WIDTH - 1 : 0] mepc

);



















reg jal_dec_r;
reg jalr_ex_r;
reg branch_taken_ex_r;
reg mret_r;
reg fence_dec_r;

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		jal_dec_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		jal_dec_r <= 1'b0;
		else if(jal_dec)
		jal_dec_r <= 1'b1;
	end
end	

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		jalr_ex_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		jalr_ex_r <= 1'b0;
		else if(jalr_ex)
		jalr_ex_r <= 1'b1;
	end
end	

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		branch_taken_ex_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		branch_taken_ex_r <= 1'b0;
		else if(branch_taken_ex)
		branch_taken_ex_r <= 1'b1;
	end
end	

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		mret_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		mret_r <= 1'b0;
		else if(mret)
		mret_r <= 1'b1;
	end
end	

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		fence_dec_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		fence_dec_r <= 1'b0;
		else if(fence_dec)
		fence_dec_r <= 1'b1;
	end
end	



reg [`ADDR_WIDTH - 1 : 0] addr_adder_res;


always @ *
begin
	if(branch_taken_ex)
	begin
		addr_adder_res = pc_ex + imm_ex;
	end
	else if(jalr_ex)		
	begin
		addr_adder_res = src_data1_ex + imm_ex;
	end
	else if(jal_dec)
	begin
		addr_adder_res = pc_dec + imm_dec;
	end
	else if(instr_read_data_valid && dec_ready)
	begin
		addr_adder_res = pc + 4;
	end
	else
	begin
		addr_adder_res = pc;			
	end
end


reg  [`ADDR_WIDTH - 1 : 0] addr_adder_res_r;
always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		addr_adder_res_r <= {`INSTR_WIDTH{1'b0}};	
	end
	else if(instr_read_data_valid && dec_ready)
	begin
		addr_adder_res_r <= {`INSTR_WIDTH{1'b0}};	
	end
	else if(branch_taken_ex || jal_dec || jalr_ex)
	begin
		addr_adder_res_r <= addr_adder_res;
	end
end

wire  [`ADDR_WIDTH - 1 : 0] addr_adder_res_c = (branch_taken_ex_r || jal_dec_r || jalr_ex_r )? addr_adder_res_r : addr_adder_res;


wire keep_pc = ((fence_dec || fence_dec_r) && !instr_read_data_valid ) || !dec_ready ;
always @*
begin
	if(trap)
	begin
		next_pc = vector_addr;
	end
	else if(branch_taken_ex)
	begin
		next_pc = addr_adder_res_c;
	end
	else if (keep_pc)
	begin
		next_pc = pc;
	end
	else if(mret || mret_r)
	begin
		next_pc = mepc;
	end
	else
	begin
		next_pc = addr_adder_res_c;
	end
end


always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		pc <= boot_addr;
	end
	else
	begin
		if(instr_read_data_valid)
		pc <= next_pc;
	end
end




wire flush_if = jal_dec |jalr_ex | branch_taken_ex | trap | mret;
reg flush_if_r;

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		flush_if_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		flush_if_r <= 1'b0;
		else if(flush_if)
		flush_if_r <= 1'b1;
	end
end	





reg dec_not_ready_r;
always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		dec_not_ready_r <= 1'b0;
	end
	else 
	begin
		if(dec_ready)
			dec_not_ready_r <= 1'b0;
		else if(instr_read_data_valid)
			dec_not_ready_r <= 1'b1;
	end
end	


always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		if_valid <= 1'b0;
		instr_dec <= {`INSTR_WIDTH{1'b0}};
		pc_dec <= boot_addr;
	end
	else
	begin
		if(flush_if || flush_if_r)
		begin
			if_valid <= 1'b0;
			instr_dec <= {`INSTR_WIDTH{1'b0}};
		end
		else if(dec_ready)
		begin
			instr_dec <= instr_read_data;
			pc_dec <= pc;
			if_valid <= instr_read_data_valid || dec_not_ready_r;
		end
	end
end





assign pc_misaligned = (|pc[1:0]);
assign fault_pc = pc_misaligned ? pc : {`ADDR_WIDTH{1'b0}};


wire [31:0] branch_taken_ex_cnt;
en_cnt u_branch_taken_ex_cnt (.clk(cpu_clk), .rstn(cpu_rstn), .en(branch_taken_ex), .cnt (branch_taken_ex_cnt));

wire [31:0] jal_dec_cnt;
en_cnt u_jal_dec_cnt (.clk(cpu_clk), .rstn(cpu_rstn), .en(jal_dec), .cnt (jal_dec_cnt));

wire [31:0] jalr_ex_cnt;
en_cnt u_jalr_ex_cnt (.clk(cpu_clk), .rstn(cpu_rstn), .en(jalr_ex), .cnt (jalr_ex_cnt));


endmodule
module fetch (

input wire cpu_clk,
input wire cpu_rstn,
input wire [`ADDR_WIDTH - 1 : 0] boot_addr,


input wire jal_dec,
input wire jalr_ex,
input wire fence_dec,
output reg [`ADDR_WIDTH - 1 : 0] pc_dec,
input wire dec_valid,
input wire dec_ready,
output reg if_valid,
output reg [`INSTR_WIDTH - 1 : 0] instr_dec,
input wire signed [`DATA_WIDTH - 1 : 0] src_data1_ex,
input wire signed [`DATA_WIDTH - 1 : 0] imm_ex,
input wire signed [`DATA_WIDTH - 1 : 0] imm_dec,
input wire [`ADDR_WIDTH - 1 : 0] pc_ex,


input wire ex_ready,
input wire branch_taken_ex,


output reg [`ADDR_WIDTH - 1 : 0] next_pc,
input wire instr_read_data_valid,
input wire [`INSTR_WIDTH - 1 : 0] instr_read_data,
input wire addr_AHB,


output reg [`ADDR_WIDTH - 1 : 0] pc,	
input wire mret,
output wire pc_misaligned,
output wire [`ADDR_WIDTH - 1 : 0] fault_pc,
input wire trap,
input wire  [`ADDR_WIDTH - 1 : 0] vector_addr,
input wire [`ADDR_WIDTH - 1 : 0] mepc

);




















reg jal_dec_r;
reg jalr_ex_r;
reg branch_taken_ex_r;
reg mret_r;
reg fence_dec_r;

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		jal_dec_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		jal_dec_r <= 1'b0;
		else if(jal_dec)
		jal_dec_r <= 1'b1;
	end
end	

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		jalr_ex_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		jalr_ex_r <= 1'b0;
		else if(jalr_ex)
		jalr_ex_r <= 1'b1;
	end
end	

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		branch_taken_ex_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		branch_taken_ex_r <= 1'b0;
		else if(branch_taken_ex)
		branch_taken_ex_r <= 1'b1;
	end
end	

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		mret_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		mret_r <= 1'b0;
		else if(mret)
		mret_r <= 1'b1;
	end
end	

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		fence_dec_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		fence_dec_r <= 1'b0;
		else if(fence_dec)
		fence_dec_r <= 1'b1;
	end
end	



reg [`ADDR_WIDTH - 1 : 0] addr_adder_res;


always @ *
begin
	if(branch_taken_ex)
	begin
		addr_adder_res = pc_ex + imm_ex;
	end
	else if(jalr_ex)		
	begin
		addr_adder_res = src_data1_ex + imm_ex;
	end
	else if(jal_dec)
	begin
		addr_adder_res = pc_dec + imm_dec;
	end
	else if(instr_read_data_valid && dec_ready)
	begin
		addr_adder_res = pc + 4;
	end
	else
	begin
		addr_adder_res = pc;			
	end
end


reg  [`ADDR_WIDTH - 1 : 0] addr_adder_res_r;
always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		addr_adder_res_r <= {`INSTR_WIDTH{1'b0}};	
	end
	else if(instr_read_data_valid && dec_ready)
	begin
		addr_adder_res_r <= {`INSTR_WIDTH{1'b0}};	
	end
	else if(branch_taken_ex || jal_dec || jalr_ex)
	begin
		addr_adder_res_r <= addr_adder_res;
	end
end

wire  [`ADDR_WIDTH - 1 : 0] addr_adder_res_c = (branch_taken_ex_r || jal_dec_r || jalr_ex_r )? addr_adder_res_r : addr_adder_res;


wire keep_pc = ((fence_dec || fence_dec_r) && !instr_read_data_valid ) || !dec_ready ;
always @*
begin
	if(trap)
	begin
		next_pc = vector_addr;
	end
	else if(branch_taken_ex)
	begin
		next_pc = addr_adder_res_c;
	end
	else if (keep_pc)
	begin
		next_pc = pc;
	end
	else if(mret || mret_r)
	begin
		next_pc = mepc;
	end
	else
	begin
		next_pc = addr_adder_res_c;
	end
end


always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		pc <= boot_addr;
	end
	else
	begin
		if(instr_read_data_valid)
		pc <= next_pc;
	end
end




wire flush_if = jal_dec |jalr_ex | branch_taken_ex | trap | mret;
reg flush_if_r;

always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		flush_if_r <= 1'b0;
	end
	else 
	begin
		if(instr_read_data_valid && dec_ready)
		flush_if_r <= 1'b0;
		else if(flush_if)
		flush_if_r <= 1'b1;
	end
end	





reg dec_not_ready_r;
always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		dec_not_ready_r <= 1'b0;
	end
	else 
	begin
		if(dec_ready)
			dec_not_ready_r <= 1'b0;
		else if(instr_read_data_valid)
			dec_not_ready_r <= 1'b1;
	end
end	


always @ (posedge cpu_clk or negedge cpu_rstn)
begin
	if (~cpu_rstn)
	begin
		if_valid <= 1'b0;
		instr_dec <= {`INSTR_WIDTH{1'b0}};
		pc_dec <= boot_addr;
	end
	else
	begin
		if(flush_if || flush_if_r)
		begin
			if_valid <= 1'b0;
			instr_dec <= {`INSTR_WIDTH{1'b0}};
		end
		else if(dec_ready)
		begin
			instr_dec <= instr_read_data;
			pc_dec <= pc;
			if_valid <= instr_read_data_valid || dec_not_ready_r;
		end
	end
end





assign pc_misaligned = (|pc[1:0]);
assign fault_pc = pc_misaligned ? pc : {`ADDR_WIDTH{1'b0}};


wire [31:0] branch_taken_ex_cnt;
en_cnt u_branch_taken_ex_cnt (.clk(cpu_clk), .rstn(cpu_rstn), .en(branch_taken_ex), .cnt (branch_taken_ex_cnt));

wire [31:0] jal_dec_cnt;
en_cnt u_jal_dec_cnt (.clk(cpu_clk), .rstn(cpu_rstn), .en(jal_dec), .cnt (jal_dec_cnt));

wire [31:0] jalr_ex_cnt;
en_cnt u_jalr_ex_cnt (.clk(cpu_clk), .rstn(cpu_rstn), .en(jalr_ex), .cnt (jalr_ex_cnt));


endmodule