data/full_repos/permissive/184332405/mux.v
data/verilator_xmls/59033dd0-baaf-43b9-984c-4ccadc50b4a5.xml
module mux( s, ctrl, compare_in, andornot_in, addsub_in, overflow);

output reg [7:0] s;
input [1:0] ctrl;
input [7:0] compare_in;
input [7:0] andornot_in;
input [7:0] addsub_in;
input overflow;

initial begin
	s = 0;
end

always @( ctrl or compare_in or andornot_in or addsub_in or overflow) begin
	case(ctrl) 
	2'b00:   s <= compare_in;
	2'b01:   s <= andornot_in;
	2'b10:   s <= addsub_in;
	default: s <= 0;
	endcase
end

endmodule
module mux( s, ctrl, compare_in, andornot_in, addsub_in, overflow);


output reg [7:0] s;
input [1:0] ctrl;
input [7:0] compare_in;
input [7:0] andornot_in;
input [7:0] addsub_in;
input overflow;

initial begin
	s = 0;
end

always @( ctrl or compare_in or andornot_in or addsub_in or overflow) begin
	case(ctrl) 
	2'b00:   s <= compare_in;
	2'b01:   s <= andornot_in;
	2'b10:   s <= addsub_in;
	default: s <= 0;
	endcase
end

endmodule