data/full_repos/permissive/11649754/p2/core.v
1: b"%Error: data/full_repos/permissive/11649754/p2/core.v:5: Duplicate declaration of signal: 'IsEnd'\n                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n   wire   IsEnd = now_ >= Upto;\n          ^~~~~\n        data/full_repos/permissive/11649754/p2/core.v:1: ... Location of original declaration\nmodule core (input Init, input CLK, output IsEnd, output reg [31:0] sum_ );\n                                           ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module core (input Init, input CLK, output IsEnd, output reg [31:0] sum_ );
   parameter Upto = 4000000;
   reg [31:0]   last_;
   reg [31:0] 	now_;
   wire 		IsEnd = now_ >= Upto;

   initial begin
	  sum_ <= 0;
	  last_<= 1;
	  now_ <= 2;
   end
   
   always @(posedge CLK) begin
	  sum_ <= (IsEnd | ((now_ & 1) == 1)) ? sum_ :  sum_ + now_;
	  now_ <= (IsEnd) ? now_ : last_ + now_;
	  last_ <= (IsEnd) ? last_ : now_;
   end

endmodule
module core (input Init, input CLK, output IsEnd, output reg [31:0] sum_ );

   parameter Upto = 4000000;
   reg [31:0]   last_;
   reg [31:0] 	now_;
   wire 		IsEnd = now_ >= Upto;

   initial begin
	  sum_ <= 0;
	  last_<= 1;
	  now_ <= 2;
   end
   
   always @(posedge CLK) begin
	  sum_ <= (IsEnd | ((now_ & 1) == 1)) ? sum_ :  sum_ + now_;
	  now_ <= (IsEnd) ? now_ : last_ + now_;
	  last_ <= (IsEnd) ? last_ : now_;
   end

endmodule