data/full_repos/permissive/18477150/lib/shared/eth/sonic_gearbox_40_66.sv
data/verilator_xmls/4be2a20c-d93b-4a4b-bf27-5d8923e178f6.xml
module sonic_gearbox_40_66 (

   data_out, data_valid,

   clk_in, reset, data_in
   );
   input clk_in;
   input reset;
   input [39:0]  data_in;
   output [65:0] data_out;
   output 	 data_valid;

   logic [65:0]  data_out;
   logic 	 data_valid;
      
   reg [6:0]    state;
   reg [65:0] 	sr0;
   reg [65:0] 	sr1;
   reg 		valid;

   always @ (posedge clk_inor posedge reset) begin
      if (reset == 1'b1) begin
	 sr0 <= 66'h0;
	 sr1 <= 66'h0;
	 valid <= 1'b0;
      end
      else begin
	 case (state)
	   0: begin
	      sr1[39:0]  <= data_in[39:0];
	      sr1[65:40] <= 0;
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   1: begin
	      sr1[65:40] <= data_in[25:0];
	      sr0[13:0]  <= data_in[39:26];
	      sr0[65:14] <= 0;
	      valid      <= 1;
	   end
	   2: begin
	      sr1[13:0]  <= sr0[13:0];
	      sr1[53:14] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   3: begin
	      sr1[65:54] <= data_in[11:0];
	      sr0[27:0]  <= data_in[39:12];
	      sr0[65:28] <= 0;
	      valid      <= 1;
	   end
	   4: begin
	      sr1[27:0]  <= sr0[27:0];
	      sr1[65:28] <= data_in[37:0];
	      sr0[1:0]   <= data_in[39:38];
	      sr0[65:2]  <= 0;
	      valid      <= 1;
	   end
	   5: begin
	      sr1[1:0]   <= sr0[1:0];
	      sr1[41:2]  <= data_in[39:0];
	      sr0        <= 0;
	      valid      <= 0;
	   end
	   6: begin
	      sr1[65:42] <= data_in[23:0];
	      sr0[15:0]  <= data_in[39:24];
	      sr0[65:16] <= 0;
	      valid      <= 1;
	   end
	   7: begin
	      sr1[15:0]  <= sr0[15:0];
	      sr1[55:16] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	      
	   end
	   8: begin
	      sr1[65:56] <= data_in[9:0];
	      sr0[29:0]  <= data_in[39:10];
	      sr0[65:30] <= 0;
	      valid      <= 1;
	   end
	   9: begin
	      sr1[29:0]  <= sr0[29:0];
	      sr1[65:30] <= data_in[35:0];
	      sr0[3:0]   <= data_in[39:36];
	      sr0[65:4]  <= 0;
	      valid      <= 1;
	   end
	   10: begin
	      sr1[43:4]  <= data_in[39:0];
	      sr1[3:0]   <= sr0[3:0];
	      sr1[65:44] <= 0;
	      sr0        <= 0;
	      valid      <= 0;
	   end
	   11: begin
	      sr1[65:44] <= data_in[21:0];
	      sr0[17:0]  <= data_in[39:22];
	      sr0[65:18] <= 0;
	      valid      <= 1;
	   end
	   12: begin
	      sr1[17:0]  <= sr0[17:0];
	      sr1[57:18] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   13: begin
	      sr1[65:58] <= data_in[7:0];
	      sr0[31:0]  <= data_in[39:8];
	      sr0[65:32] <= 0;
	      valid      <= 1;
	   end
	   14: begin
	      sr1[31:0]  <= sr0[31:0];
	      sr1[65:32] <= data_in[33:0];
	      sr0[5:0]   <= data_in[39:34];
	      sr0[39:6]  <= 0;
	      valid      <= 1;
	   end
	   15: begin
	      sr1[45:6]  <= data_in[39:0];
	      sr1[5:0]   <= sr0[5:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   16: begin
	      sr1[65:46] <= data_in[19:0];
	      sr0[19:0]  <= data_in[39:20];
	      sr0[65:20] <= 0;
	      valid      <= 1;
	   end
	   17: begin
	      sr1[19:0]  <= sr0[19:0];
	      sr1[59:20] <= data_in[39:0];
	      sr0[59:0]  <= 0;
	      valid      <= 0;
	      
	   end
	   18: begin
	      sr1[65:60] <= data_in[5:0];
	      sr0[33:0]  <= data_in[39:6];
	      sr0[65:34] <= 0;
	      valid      <= 1;
	      
	   end
	   19: begin
	      sr1[33:0]  <= sr0[33:0];
	      sr1[65:34] <= data_in[31:0];
	      sr0[7:0]   <= data_in[39:32];
	      sr0[65:8]  <= 0;
	      valid      <= 1;
	   end
	   20: begin
	      sr1[7:0]   <= sr0[7:0];
	      sr1[47:8]  <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   21: begin
	      sr1[65:48] <= data_in[17:0];
	      sr0[21:0]  <= data_in[39:18];
	      sr0[65:22] <= 0;
	      valid      <= 1;
	   end
	   22: begin
	      sr1[21:0]  <= sr0[21:0];
	      sr1[61:22] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   23: begin
	      sr1[65:62] <= data_in[3:0];
	      sr0[35:0]  <= data_in[39:4];
	      sr0[65:36] <= 0;
	      valid      <= 1;
	   end
	   24: begin
	      sr1[35:0]  <= sr0[35:0];
	      sr1[65:36] <= data_in[29:0];
	      sr0[9:0]   <= data_in[39:30];
	      valid      <= 1;
	   end
	   25: begin
	      sr1[9:0]   <= sr0[9:0];
	      sr1[49:10] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   26: begin
	      sr1[65:50] <= data_in[15:0];
	      sr0[23:0]  <= data_in[39:16];
	      sr0[65:24] <= 0;
	      valid      <= 1;
	   end
	   27: begin
	      sr1[23:0]  <= sr0[23:0];
	      sr1[63:24] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   28: begin
	      sr1[65:64] <= data_in[1:0];
	      sr0[37:0]  <= data_in[39:2];
	      sr0[65:38] <= 0;
	      valid      <= 1;
	   end
	   29: begin
	      sr1[37:0]  <= sr0[37:0];
	      sr1[65:38] <= data_in[27:0];
	      sr0[11:0]  <= data_in[39:28];
	      valid      <= 1;
	   end
	   30: begin
	      sr1[11:0]  <= sr0[11:0];
	      sr1[51:12] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   31: begin
	      sr1[65:52] <= data_in[13:0];
	      sr0[25:0]  <= data_in[39:14];
	      sr0[65:26] <= 0;
	      valid      <= 1;
	   end
	   32: begin
	      sr1[25:0]  <= sr0[25:0];
	      sr1[65:26] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 1;
	   end
	 endcase
      end
   end

   always @ (posedge clk_inor posedge reset) begin
      if (reset) begin
	 state <= 7'h0;
      end
      else begin
	 state <= (state[5]) ? 7'h0 : (state + 1'b1);
      end
   end

   always @ (posedge clk_inor posedge reset) begin
      if (reset) begin
	 data_out <= 66'h0;
      end
      else if (valid == 1'b1) begin
	 data_out <= sr1;
      end
   end
   
   always @ (posedge clk_inor posedge reset) begin
      if (reset) begin
	 data_valid <= 1'b0;
      end
      else begin
	 data_valid <= valid;
      end
   end
   
  
endmodule
module sonic_gearbox_40_66 (

   data_out, data_valid,

   clk_in, reset, data_in
   );

   input clk_in;
   input reset;
   input [39:0]  data_in;
   output [65:0] data_out;
   output 	 data_valid;

   logic [65:0]  data_out;
   logic 	 data_valid;
      
   reg [6:0]    state;
   reg [65:0] 	sr0;
   reg [65:0] 	sr1;
   reg 		valid;

   always @ (posedge clk_inor posedge reset) begin
      if (reset == 1'b1) begin
	 sr0 <= 66'h0;
	 sr1 <= 66'h0;
	 valid <= 1'b0;
      end
      else begin
	 case (state)
	   0: begin
	      sr1[39:0]  <= data_in[39:0];
	      sr1[65:40] <= 0;
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   1: begin
	      sr1[65:40] <= data_in[25:0];
	      sr0[13:0]  <= data_in[39:26];
	      sr0[65:14] <= 0;
	      valid      <= 1;
	   end
	   2: begin
	      sr1[13:0]  <= sr0[13:0];
	      sr1[53:14] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   3: begin
	      sr1[65:54] <= data_in[11:0];
	      sr0[27:0]  <= data_in[39:12];
	      sr0[65:28] <= 0;
	      valid      <= 1;
	   end
	   4: begin
	      sr1[27:0]  <= sr0[27:0];
	      sr1[65:28] <= data_in[37:0];
	      sr0[1:0]   <= data_in[39:38];
	      sr0[65:2]  <= 0;
	      valid      <= 1;
	   end
	   5: begin
	      sr1[1:0]   <= sr0[1:0];
	      sr1[41:2]  <= data_in[39:0];
	      sr0        <= 0;
	      valid      <= 0;
	   end
	   6: begin
	      sr1[65:42] <= data_in[23:0];
	      sr0[15:0]  <= data_in[39:24];
	      sr0[65:16] <= 0;
	      valid      <= 1;
	   end
	   7: begin
	      sr1[15:0]  <= sr0[15:0];
	      sr1[55:16] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	      
	   end
	   8: begin
	      sr1[65:56] <= data_in[9:0];
	      sr0[29:0]  <= data_in[39:10];
	      sr0[65:30] <= 0;
	      valid      <= 1;
	   end
	   9: begin
	      sr1[29:0]  <= sr0[29:0];
	      sr1[65:30] <= data_in[35:0];
	      sr0[3:0]   <= data_in[39:36];
	      sr0[65:4]  <= 0;
	      valid      <= 1;
	   end
	   10: begin
	      sr1[43:4]  <= data_in[39:0];
	      sr1[3:0]   <= sr0[3:0];
	      sr1[65:44] <= 0;
	      sr0        <= 0;
	      valid      <= 0;
	   end
	   11: begin
	      sr1[65:44] <= data_in[21:0];
	      sr0[17:0]  <= data_in[39:22];
	      sr0[65:18] <= 0;
	      valid      <= 1;
	   end
	   12: begin
	      sr1[17:0]  <= sr0[17:0];
	      sr1[57:18] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   13: begin
	      sr1[65:58] <= data_in[7:0];
	      sr0[31:0]  <= data_in[39:8];
	      sr0[65:32] <= 0;
	      valid      <= 1;
	   end
	   14: begin
	      sr1[31:0]  <= sr0[31:0];
	      sr1[65:32] <= data_in[33:0];
	      sr0[5:0]   <= data_in[39:34];
	      sr0[39:6]  <= 0;
	      valid      <= 1;
	   end
	   15: begin
	      sr1[45:6]  <= data_in[39:0];
	      sr1[5:0]   <= sr0[5:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   16: begin
	      sr1[65:46] <= data_in[19:0];
	      sr0[19:0]  <= data_in[39:20];
	      sr0[65:20] <= 0;
	      valid      <= 1;
	   end
	   17: begin
	      sr1[19:0]  <= sr0[19:0];
	      sr1[59:20] <= data_in[39:0];
	      sr0[59:0]  <= 0;
	      valid      <= 0;
	      
	   end
	   18: begin
	      sr1[65:60] <= data_in[5:0];
	      sr0[33:0]  <= data_in[39:6];
	      sr0[65:34] <= 0;
	      valid      <= 1;
	      
	   end
	   19: begin
	      sr1[33:0]  <= sr0[33:0];
	      sr1[65:34] <= data_in[31:0];
	      sr0[7:0]   <= data_in[39:32];
	      sr0[65:8]  <= 0;
	      valid      <= 1;
	   end
	   20: begin
	      sr1[7:0]   <= sr0[7:0];
	      sr1[47:8]  <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   21: begin
	      sr1[65:48] <= data_in[17:0];
	      sr0[21:0]  <= data_in[39:18];
	      sr0[65:22] <= 0;
	      valid      <= 1;
	   end
	   22: begin
	      sr1[21:0]  <= sr0[21:0];
	      sr1[61:22] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   23: begin
	      sr1[65:62] <= data_in[3:0];
	      sr0[35:0]  <= data_in[39:4];
	      sr0[65:36] <= 0;
	      valid      <= 1;
	   end
	   24: begin
	      sr1[35:0]  <= sr0[35:0];
	      sr1[65:36] <= data_in[29:0];
	      sr0[9:0]   <= data_in[39:30];
	      valid      <= 1;
	   end
	   25: begin
	      sr1[9:0]   <= sr0[9:0];
	      sr1[49:10] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   26: begin
	      sr1[65:50] <= data_in[15:0];
	      sr0[23:0]  <= data_in[39:16];
	      sr0[65:24] <= 0;
	      valid      <= 1;
	   end
	   27: begin
	      sr1[23:0]  <= sr0[23:0];
	      sr1[63:24] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   28: begin
	      sr1[65:64] <= data_in[1:0];
	      sr0[37:0]  <= data_in[39:2];
	      sr0[65:38] <= 0;
	      valid      <= 1;
	   end
	   29: begin
	      sr1[37:0]  <= sr0[37:0];
	      sr1[65:38] <= data_in[27:0];
	      sr0[11:0]  <= data_in[39:28];
	      valid      <= 1;
	   end
	   30: begin
	      sr1[11:0]  <= sr0[11:0];
	      sr1[51:12] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 0;
	   end
	   31: begin
	      sr1[65:52] <= data_in[13:0];
	      sr0[25:0]  <= data_in[39:14];
	      sr0[65:26] <= 0;
	      valid      <= 1;
	   end
	   32: begin
	      sr1[25:0]  <= sr0[25:0];
	      sr1[65:26] <= data_in[39:0];
	      sr0[65:0]  <= 0;
	      valid      <= 1;
	   end
	 endcase
      end
   end

   always @ (posedge clk_inor posedge reset) begin
      if (reset) begin
	 state <= 7'h0;
      end
      else begin
	 state <= (state[5]) ? 7'h0 : (state + 1'b1);
      end
   end

   always @ (posedge clk_inor posedge reset) begin
      if (reset) begin
	 data_out <= 66'h0;
      end
      else if (valid == 1'b1) begin
	 data_out <= sr1;
      end
   end
   
   always @ (posedge clk_inor posedge reset) begin
      if (reset) begin
	 data_valid <= 1'b0;
      end
      else begin
	 data_valid <= valid;
      end
   end
   
  
endmodule