data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Mux.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Mux.v:32: Multiple top level modules\n                                                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                       : ... Top module \'Mux_5\'\nmodule Mux_5(\n       ^~~~~\n                                                                                                                       : ... Top module \'Mux_32\'\nmodule Mux_32(\n       ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Mux.v:38: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'SEL\' generates 32 bits.\n                                                                                                                    : ... In instance Mux_32\n    assign OUT= SEL ? INPUT1:INPUT2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Mux.v:29: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'SEL\' generates 5 bits.\n                                                                                                                    : ... In instance Mux_5\n    assign OUT= SEL ? INPUT1:INPUT2;\n                    ^\n%Error: Exiting due to 3 warning(s)\n'
module Mux_32(
    input [31:0] INPUT1,
    input [31:0] INPUT2,
    input [31:0] SEL,
    output [31:0] OUT  
);
    assign OUT= SEL ? INPUT1:INPUT2;
endmodule
module Mux_32(
    input [31:0] INPUT1,
    input [31:0] INPUT2,
    input [31:0] SEL,
    output [31:0] OUT  
);

    assign OUT= SEL ? INPUT1:INPUT2;
endmodule