data/full_repos/permissive/151116236/ParametricMux.v
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data/verilator_xmls/bef6fbc0-ba50-4c92-ab7d-a2b9a4678eab.xml
module mux #(parameter DATA_SIZE = 32, DATA_COUNT = 2, ADDR_SIZE = 1) (
output [DATA_SIZE - 1:0] outdata ,
input [DATA_SIZE*DATA_COUNT - 1:0] indata, [ADDR_SIZE - 1:0]   addr);

wire [DATA_SIZE-1:0] array[0:DATA_COUNT-1];

generate
	genvar i;
	for(i=0; i<DATA_COUNT; i=i+1) begin : gen1
		assign array[i] = indata[(i+1)*DATA_SIZE-1:i*DATA_SIZE];
	end
endgenerate

assign outdata = array[addr];

endmodule
module mux #(parameter DATA_SIZE = 32, DATA_COUNT = 2, ADDR_SIZE = 1) (
output [DATA_SIZE - 1:0] outdata ,
input [DATA_SIZE*DATA_COUNT - 1:0] indata, [ADDR_SIZE - 1:0]   addr);


wire [DATA_SIZE-1:0] array[0:DATA_COUNT-1];

generate
	genvar i;
	for(i=0; i<DATA_COUNT; i=i+1) begin : gen1
		assign array[i] = indata[(i+1)*DATA_SIZE-1:i*DATA_SIZE];
	end
endgenerate

assign outdata = array[addr];

endmodule