data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_WDMA_dat.v
1: b"%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_WDMA_dat.v:98: Cannot find file containing module: 'NV_NVDLA_SDP_WDMA_DAT_in'\nNV_NVDLA_SDP_WDMA_DAT_in u_in (\n^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/NV_NVDLA_SDP_WDMA_DAT_in\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/NV_NVDLA_SDP_WDMA_DAT_in.v\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/NV_NVDLA_SDP_WDMA_DAT_in.sv\n             NV_NVDLA_SDP_WDMA_DAT_in\n             NV_NVDLA_SDP_WDMA_DAT_in.v\n             NV_NVDLA_SDP_WDMA_DAT_in.sv\n             obj_dir/NV_NVDLA_SDP_WDMA_DAT_in\n             obj_dir/NV_NVDLA_SDP_WDMA_DAT_in.v\n             obj_dir/NV_NVDLA_SDP_WDMA_DAT_in.sv\n%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_WDMA_dat.v:129: Cannot find file containing module: 'NV_NVDLA_SDP_WDMA_DAT_out'\nNV_NVDLA_SDP_WDMA_DAT_out u_out (\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module NV_NVDLA_SDP_WDMA_dat (
   cmd2dat_dma_pd
  ,cmd2dat_dma_pvld
  ,cmd2dat_spt_pd
  ,cmd2dat_spt_pvld
  ,dma_wr_req_rdy
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,op_load
  ,pwrbus_ram_pd
  ,reg2dp_batch_number
  ,reg2dp_ew_alu_algo
  ,reg2dp_ew_alu_bypass
  ,reg2dp_ew_bypass
  ,reg2dp_height
  ,reg2dp_interrupt_ptr
  ,reg2dp_out_precision
  ,reg2dp_output_dst
  ,reg2dp_proc_precision
  ,reg2dp_width
  ,reg2dp_winograd
  ,sdp_dp2wdma_pd
  ,sdp_dp2wdma_valid
  ,cmd2dat_dma_prdy
  ,cmd2dat_spt_prdy
  ,dma_wr_req_pd
  ,dma_wr_req_vld
  ,dp2reg_done
  ,dp2reg_status_nan_output_num
  ,dp2reg_status_unequal
  ,intr_req_ptr
  ,intr_req_pvld
  ,sdp_dp2wdma_ready
  );



input nvdla_core_clk;
input nvdla_core_rstn;
input cmd2dat_dma_pvld;
output cmd2dat_dma_prdy;
input [32 -3 +13 +1:0] cmd2dat_dma_pd;
input cmd2dat_spt_pvld;
output cmd2dat_spt_prdy;
input [14:0] cmd2dat_spt_pd;
input sdp_dp2wdma_valid;
output sdp_dp2wdma_ready;
input [8*8 -1:0] sdp_dp2wdma_pd;
input dma_wr_req_rdy;
input op_load;
input [31:0] pwrbus_ram_pd;
input [4:0] reg2dp_batch_number;
input [1:0] reg2dp_ew_alu_algo;
input reg2dp_ew_alu_bypass;
input reg2dp_ew_bypass;
input [12:0] reg2dp_height;
input reg2dp_interrupt_ptr;
input [1:0] reg2dp_out_precision;
input reg2dp_output_dst;
input [1:0] reg2dp_proc_precision;
input [12:0] reg2dp_width;
input reg2dp_winograd;
output [66 -1:0] dma_wr_req_pd;
output dma_wr_req_vld;
output dp2reg_done;
output [31:0] dp2reg_status_nan_output_num;
output dp2reg_status_unequal;
output intr_req_ptr;
output intr_req_pvld;
wire [8*8 -1:0] dfifo0_rd_pd;
wire dfifo0_rd_prdy;
wire dfifo0_rd_pvld;
wire [8*8 -1:0] dfifo1_rd_pd;
wire dfifo1_rd_prdy;
wire dfifo1_rd_pvld;
wire [8*8 -1:0] dfifo2_rd_pd;
wire dfifo2_rd_prdy;
wire dfifo2_rd_pvld;
wire [8*8 -1:0] dfifo3_rd_pd;
wire dfifo3_rd_prdy;
wire dfifo3_rd_pvld;
NV_NVDLA_SDP_WDMA_DAT_in u_in (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld)
  ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy)
  ,.cmd2dat_spt_pd (cmd2dat_spt_pd[14:0])
  ,.sdp_dp2wdma_valid (sdp_dp2wdma_valid)
  ,.sdp_dp2wdma_ready (sdp_dp2wdma_ready)
  ,.sdp_dp2wdma_pd (sdp_dp2wdma_pd[8*8 -1:0])
  ,.dfifo0_rd_pvld (dfifo0_rd_pvld)
  ,.dfifo0_rd_prdy (dfifo0_rd_prdy)
  ,.dfifo0_rd_pd (dfifo0_rd_pd[8*8 -1:0])
  ,.dfifo1_rd_pvld (dfifo1_rd_pvld)
  ,.dfifo1_rd_prdy (dfifo1_rd_prdy)
  ,.dfifo1_rd_pd (dfifo1_rd_pd[8*8 -1:0])
  ,.dfifo2_rd_pvld (dfifo2_rd_pvld)
  ,.dfifo2_rd_prdy (dfifo2_rd_prdy)
  ,.dfifo2_rd_pd (dfifo2_rd_pd[8*8 -1:0])
  ,.dfifo3_rd_pvld (dfifo3_rd_pvld)
  ,.dfifo3_rd_prdy (dfifo3_rd_prdy)
  ,.dfifo3_rd_pd (dfifo3_rd_pd[8*8 -1:0])
  ,.reg2dp_batch_number (reg2dp_batch_number[4:0])
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_out_precision (reg2dp_out_precision[1:0])
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  ,.reg2dp_winograd (reg2dp_winograd)
  ,.dp2reg_status_nan_output_num (dp2reg_status_nan_output_num[31:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.op_load (op_load)
  );
NV_NVDLA_SDP_WDMA_DAT_out u_out (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld)
  ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy)
  ,.cmd2dat_dma_pd (cmd2dat_dma_pd[32 -3 +13 +1:0])
  ,.dfifo0_rd_pvld (dfifo0_rd_pvld)
  ,.dfifo0_rd_prdy (dfifo0_rd_prdy)
  ,.dfifo0_rd_pd (dfifo0_rd_pd[8*8 -1:0])
  ,.dfifo1_rd_pvld (dfifo1_rd_pvld)
  ,.dfifo1_rd_prdy (dfifo1_rd_prdy)
  ,.dfifo1_rd_pd (dfifo1_rd_pd[8*8 -1:0])
  ,.dfifo2_rd_pvld (dfifo2_rd_pvld)
  ,.dfifo2_rd_prdy (dfifo2_rd_prdy)
  ,.dfifo2_rd_pd (dfifo2_rd_pd[8*8 -1:0])
  ,.dfifo3_rd_pvld (dfifo3_rd_pvld)
  ,.dfifo3_rd_prdy (dfifo3_rd_prdy)
  ,.dfifo3_rd_pd (dfifo3_rd_pd[8*8 -1:0])
  ,.op_load (op_load)
  ,.reg2dp_batch_number (reg2dp_batch_number[4:0])
  ,.reg2dp_ew_alu_algo (reg2dp_ew_alu_algo[1:0])
  ,.reg2dp_ew_alu_bypass (reg2dp_ew_alu_bypass)
  ,.reg2dp_ew_bypass (reg2dp_ew_bypass)
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr)
  ,.reg2dp_out_precision (reg2dp_out_precision[1:0])
  ,.reg2dp_output_dst (reg2dp_output_dst)
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  ,.reg2dp_winograd (reg2dp_winograd)
  ,.dp2reg_done (dp2reg_done)
  ,.dp2reg_status_unequal (dp2reg_status_unequal)
  ,.dma_wr_req_rdy (dma_wr_req_rdy)
  ,.dma_wr_req_pd (dma_wr_req_pd[66 -1:0])
  ,.dma_wr_req_vld (dma_wr_req_vld)
  ,.intr_req_ptr (intr_req_ptr)
  ,.intr_req_pvld (intr_req_pvld)
  );
endmodule
module NV_NVDLA_SDP_WDMA_dat (
   cmd2dat_dma_pd
  ,cmd2dat_dma_pvld
  ,cmd2dat_spt_pd
  ,cmd2dat_spt_pvld
  ,dma_wr_req_rdy
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,op_load
  ,pwrbus_ram_pd
  ,reg2dp_batch_number
  ,reg2dp_ew_alu_algo
  ,reg2dp_ew_alu_bypass
  ,reg2dp_ew_bypass
  ,reg2dp_height
  ,reg2dp_interrupt_ptr
  ,reg2dp_out_precision
  ,reg2dp_output_dst
  ,reg2dp_proc_precision
  ,reg2dp_width
  ,reg2dp_winograd
  ,sdp_dp2wdma_pd
  ,sdp_dp2wdma_valid
  ,cmd2dat_dma_prdy
  ,cmd2dat_spt_prdy
  ,dma_wr_req_pd
  ,dma_wr_req_vld
  ,dp2reg_done
  ,dp2reg_status_nan_output_num
  ,dp2reg_status_unequal
  ,intr_req_ptr
  ,intr_req_pvld
  ,sdp_dp2wdma_ready
  );




input nvdla_core_clk;
input nvdla_core_rstn;
input cmd2dat_dma_pvld;
output cmd2dat_dma_prdy;
input [32 -3 +13 +1:0] cmd2dat_dma_pd;
input cmd2dat_spt_pvld;
output cmd2dat_spt_prdy;
input [14:0] cmd2dat_spt_pd;
input sdp_dp2wdma_valid;
output sdp_dp2wdma_ready;
input [8*8 -1:0] sdp_dp2wdma_pd;
input dma_wr_req_rdy;
input op_load;
input [31:0] pwrbus_ram_pd;
input [4:0] reg2dp_batch_number;
input [1:0] reg2dp_ew_alu_algo;
input reg2dp_ew_alu_bypass;
input reg2dp_ew_bypass;
input [12:0] reg2dp_height;
input reg2dp_interrupt_ptr;
input [1:0] reg2dp_out_precision;
input reg2dp_output_dst;
input [1:0] reg2dp_proc_precision;
input [12:0] reg2dp_width;
input reg2dp_winograd;
output [66 -1:0] dma_wr_req_pd;
output dma_wr_req_vld;
output dp2reg_done;
output [31:0] dp2reg_status_nan_output_num;
output dp2reg_status_unequal;
output intr_req_ptr;
output intr_req_pvld;
wire [8*8 -1:0] dfifo0_rd_pd;
wire dfifo0_rd_prdy;
wire dfifo0_rd_pvld;
wire [8*8 -1:0] dfifo1_rd_pd;
wire dfifo1_rd_prdy;
wire dfifo1_rd_pvld;
wire [8*8 -1:0] dfifo2_rd_pd;
wire dfifo2_rd_prdy;
wire dfifo2_rd_pvld;
wire [8*8 -1:0] dfifo3_rd_pd;
wire dfifo3_rd_prdy;
wire dfifo3_rd_pvld;
NV_NVDLA_SDP_WDMA_DAT_in u_in (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld)
  ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy)
  ,.cmd2dat_spt_pd (cmd2dat_spt_pd[14:0])
  ,.sdp_dp2wdma_valid (sdp_dp2wdma_valid)
  ,.sdp_dp2wdma_ready (sdp_dp2wdma_ready)
  ,.sdp_dp2wdma_pd (sdp_dp2wdma_pd[8*8 -1:0])
  ,.dfifo0_rd_pvld (dfifo0_rd_pvld)
  ,.dfifo0_rd_prdy (dfifo0_rd_prdy)
  ,.dfifo0_rd_pd (dfifo0_rd_pd[8*8 -1:0])
  ,.dfifo1_rd_pvld (dfifo1_rd_pvld)
  ,.dfifo1_rd_prdy (dfifo1_rd_prdy)
  ,.dfifo1_rd_pd (dfifo1_rd_pd[8*8 -1:0])
  ,.dfifo2_rd_pvld (dfifo2_rd_pvld)
  ,.dfifo2_rd_prdy (dfifo2_rd_prdy)
  ,.dfifo2_rd_pd (dfifo2_rd_pd[8*8 -1:0])
  ,.dfifo3_rd_pvld (dfifo3_rd_pvld)
  ,.dfifo3_rd_prdy (dfifo3_rd_prdy)
  ,.dfifo3_rd_pd (dfifo3_rd_pd[8*8 -1:0])
  ,.reg2dp_batch_number (reg2dp_batch_number[4:0])
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_out_precision (reg2dp_out_precision[1:0])
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  ,.reg2dp_winograd (reg2dp_winograd)
  ,.dp2reg_status_nan_output_num (dp2reg_status_nan_output_num[31:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.op_load (op_load)
  );
NV_NVDLA_SDP_WDMA_DAT_out u_out (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld)
  ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy)
  ,.cmd2dat_dma_pd (cmd2dat_dma_pd[32 -3 +13 +1:0])
  ,.dfifo0_rd_pvld (dfifo0_rd_pvld)
  ,.dfifo0_rd_prdy (dfifo0_rd_prdy)
  ,.dfifo0_rd_pd (dfifo0_rd_pd[8*8 -1:0])
  ,.dfifo1_rd_pvld (dfifo1_rd_pvld)
  ,.dfifo1_rd_prdy (dfifo1_rd_prdy)
  ,.dfifo1_rd_pd (dfifo1_rd_pd[8*8 -1:0])
  ,.dfifo2_rd_pvld (dfifo2_rd_pvld)
  ,.dfifo2_rd_prdy (dfifo2_rd_prdy)
  ,.dfifo2_rd_pd (dfifo2_rd_pd[8*8 -1:0])
  ,.dfifo3_rd_pvld (dfifo3_rd_pvld)
  ,.dfifo3_rd_prdy (dfifo3_rd_prdy)
  ,.dfifo3_rd_pd (dfifo3_rd_pd[8*8 -1:0])
  ,.op_load (op_load)
  ,.reg2dp_batch_number (reg2dp_batch_number[4:0])
  ,.reg2dp_ew_alu_algo (reg2dp_ew_alu_algo[1:0])
  ,.reg2dp_ew_alu_bypass (reg2dp_ew_alu_bypass)
  ,.reg2dp_ew_bypass (reg2dp_ew_bypass)
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr)
  ,.reg2dp_out_precision (reg2dp_out_precision[1:0])
  ,.reg2dp_output_dst (reg2dp_output_dst)
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  ,.reg2dp_winograd (reg2dp_winograd)
  ,.dp2reg_done (dp2reg_done)
  ,.dp2reg_status_unequal (dp2reg_status_unequal)
  ,.dma_wr_req_rdy (dma_wr_req_rdy)
  ,.dma_wr_req_pd (dma_wr_req_pd[66 -1:0])
  ,.dma_wr_req_vld (dma_wr_req_vld)
  ,.intr_req_ptr (intr_req_ptr)
  ,.intr_req_pvld (intr_req_pvld)
  );
endmodule