data/full_repos/permissive/169258653/multicycle/MIPS_multi_cycle_32bit/MIPS_multi_cycle_32bit.srcs/sources_1/new/signext.v
data/verilator_xmls/0ddc9aca-1a0a-4be5-94ec-189acc798f1f.xml
module signext(
    input [15:0] short,
    input extend,
    output reg [31:0] extended
    );
    

    always@(*)
    if(extend)
        extended={{16{short[15]}},short};
    else
        extended={16'h0000,short};
    
endmodule
module signext(
    input [15:0] short,
    input extend,
    output reg [31:0] extended
    );

    

    always@(*)
    if(extend)
        extended={{16{short[15]}},short};
    else
        extended={16'h0000,short};
    
endmodule