data/full_repos/permissive/18770871/shift_left_2.v
data/verilator_xmls/f9d4848b-1e94-458f-b83e-7f84322c7e4c.xml
module shift_left_2 (
  in, out);
  input [15:0] in;
  output [15:0] out;
  assign out = in << 2;
endmodule
module shift_left_2 (
  in, out);

  input [15:0] in;
  output [15:0] out;
  assign out = in << 2;
endmodule