data/full_repos/permissive/155217800/Part 1/Part1.v
 line:33: before: ")"
1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/155217800\n        ... Looked in:\n             data/full_repos/permissive/155217800/Part/1,data/full_repos/permissive/155217800\n             data/full_repos/permissive/155217800/Part/1,data/full_repos/permissive/155217800.v\n             data/full_repos/permissive/155217800/Part/1,data/full_repos/permissive/155217800.sv\n             1,data/full_repos/permissive/155217800\n             1,data/full_repos/permissive/155217800.v\n             1,data/full_repos/permissive/155217800.sv\n             obj_dir/1,data/full_repos/permissive/155217800\n             obj_dir/1,data/full_repos/permissive/155217800.v\n             obj_dir/1,data/full_repos/permissive/155217800.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/155217800/Part\n%Error: Cannot find file containing module: 1/Part1.v\n%Error: Exiting due to 3 error(s)\n'
module seven_segment_display(

	in,
	out
);

input [3:0] in;
output [6:0] out;



assign out[6] = (~in[3] & ~in[2] & ~in[1]) 	+ (~in[3] & in[2] & in[1] & in[0]); 
assign out[5] = (in[3] & in[2] & ~in[1]) 		+ (~in[3] & in[1] & in[0]) + (~in[3] & ~in[2] & in[0]) + (~in[3] & ~in[2] & in[1]); 
assign out[4] = (~in[3] & in[0]) 				+ (~in[3] & in[2] & ~in[1]) + (~in[2] & ~in[1] & in[0]);
assign out[3] = (in[2] & in[1] & in[0]) 		+ (~in[3] & in[2] & ~in[1] & ~in[0]) + (in[3] & ~in[2] & in[1] & ~in[0]) + (~in[2] & ~in[1] & in[0]);
assign out[2] = (in[3] & in[2] & ~in[0]) 		+ (~in[3] & ~in[2] & in[1] & ~in[0]) + (in[3] & in[2] & in[1]);
assign out[1] = (in[2] & in[1] & ~in[0]) 		+ (in[3] & in[1] & in[0]) + (~in[3] & in[2] & ~in[1] & in[0]) + (in[3] & in[2] & ~in[0]);
assign out[0] = (in[2] & ~in[1] & ~in[0]) 	+ (in[3] & in[2] & ~in[1]) + (~in[3] & ~in[2] & ~in[1] & in[0]) + (in[3] & ~in[2] & in[1] & in[0]);

endmodule
module seven_segment_display(

	in,
	out
);


input [3:0] in;
output [6:0] out;



assign out[6] = (~in[3] & ~in[2] & ~in[1]) 	+ (~in[3] & in[2] & in[1] & in[0]); 
assign out[5] = (in[3] & in[2] & ~in[1]) 		+ (~in[3] & in[1] & in[0]) + (~in[3] & ~in[2] & in[0]) + (~in[3] & ~in[2] & in[1]); 
assign out[4] = (~in[3] & in[0]) 				+ (~in[3] & in[2] & ~in[1]) + (~in[2] & ~in[1] & in[0]);
assign out[3] = (in[2] & in[1] & in[0]) 		+ (~in[3] & in[2] & ~in[1] & ~in[0]) + (in[3] & ~in[2] & in[1] & ~in[0]) + (~in[2] & ~in[1] & in[0]);
assign out[2] = (in[3] & in[2] & ~in[0]) 		+ (~in[3] & ~in[2] & in[1] & ~in[0]) + (in[3] & in[2] & in[1]);
assign out[1] = (in[2] & in[1] & ~in[0]) 		+ (in[3] & in[1] & in[0]) + (~in[3] & in[2] & ~in[1] & in[0]) + (in[3] & in[2] & ~in[0]);
assign out[0] = (in[2] & ~in[1] & ~in[0]) 	+ (in[3] & in[2] & ~in[1]) + (~in[3] & ~in[2] & ~in[1] & in[0]) + (in[3] & ~in[2] & in[1] & in[0]);

endmodule