data/full_repos/permissive/178052224/Tarea3y4/modules/nor.v
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1: b"%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/nor.v:16: Duplicate declaration of signal: 'a'\n                                                                      : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire a, b, y;\n         ^\n        data/full_repos/permissive/178052224/Tarea3y4/modules/nor.v:12: ... Location of original declaration\n    input a,\n          ^\n%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/nor.v:16: Duplicate declaration of signal: 'b'\n    wire a, b, y;\n            ^\n        data/full_repos/permissive/178052224/Tarea3y4/modules/nor.v:13: ... Location of original declaration\n    input b,      \n          ^\n%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/nor.v:16: Duplicate declaration of signal: 'y'\n    wire a, b, y;\n               ^\n        data/full_repos/permissive/178052224/Tarea3y4/modules/nor.v:14: ... Location of original declaration\n    output y \n           ^\n%Error: Exiting due to 3 error(s)\n"
module norG (
    input a,
    input b,      
    output y 
);
    wire a, b, y;
    
    parameter tpd_min = 1 ;
    parameter tpd_max = 4.5; 
    parameter Vcc = 5;

    assign #(tpd_min:tpd_max:tpd_max) y = !(a | b);
endmodule
module norG (
    input a,
    input b,      
    output y 
);

    wire a, b, y;
    
    parameter tpd_min = 1 ;
    parameter tpd_max = 4.5; 
    parameter Vcc = 5;

    assign #(tpd_min:tpd_max:tpd_max) y = !(a | b);
endmodule