data/full_repos/permissive/157005262/verilog/spoilers/keypad.v
 line:16: before: "+"
1: b"%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:23: syntax error, unexpected pullup, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule pullup(output wire pin, output wire d_in);\n       ^~~~~~\n%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\nmodule pullup(output wire pin, output wire d_in);\n                               ^~~~~~\n%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:49: syntax error, unexpected ',', expecting ')'\n  pullup io1(PIO1_02, row_pins[0]);\n                    ^\n%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:50: syntax error, unexpected ',', expecting ')'\n  pullup io2(PIO1_03, row_pins[1]);\n                    ^\n%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:51: syntax error, unexpected ',', expecting ')'\n  pullup io3(PIO1_04, row_pins[2]);\n                    ^\n%Error: data/full_repos/permissive/157005262/verilog/spoilers/keypad.v:52: syntax error, unexpected ',', expecting ')'\n  pullup io4(PIO1_05, row_pins[3]);\n                    ^\n%Error: Exiting due to 6 error(s)\n"
module top(input wire  iCE_CLK,
           input wire  PIO1_02,
           input wire  PIO1_03,
           input wire  PIO1_04,
           input wire  PIO1_05,
           output wire PIO1_06,
           output wire PIO1_07,
           output wire PIO1_08,
           output wire PIO1_09,
           output wire LED0,
           output wire LED1,
           output wire LED2,
           output wire LED3,
           output wire LED4);

  wire [3:0] row_pins;
  wire [3:0] column_pins;
  wire [15:0] keys;

  keypad k(iCE_CLK, column_pins, row_pins, keys);

  assign column_pins = {PIO1_09, PIO1_08, PIO1_07, PIO1_06};
  pullup io1(PIO1_02, row_pins[0]);
  pullup io2(PIO1_03, row_pins[1]);
  pullup io3(PIO1_04, row_pins[2]);
  pullup io4(PIO1_05, row_pins[3]);

  integer i;
  reg [3:0] key = 0;

  always @(posedge iCE_CLK) begin
    key <= 0;
    for (i = 0; i < 16; i++)
      if (keys[i])
        key <= i;
  end

  assign LED4 = !(|keys);
  assign LED0 = key[3];
  assign LED1 = key[2];
  assign LED2 = key[1];
  assign LED3 = key[0];
endmodule
module top(input wire  iCE_CLK,
           input wire  PIO1_02,
           input wire  PIO1_03,
           input wire  PIO1_04,
           input wire  PIO1_05,
           output wire PIO1_06,
           output wire PIO1_07,
           output wire PIO1_08,
           output wire PIO1_09,
           output wire LED0,
           output wire LED1,
           output wire LED2,
           output wire LED3,
           output wire LED4);


  wire [3:0] row_pins;
  wire [3:0] column_pins;
  wire [15:0] keys;

  keypad k(iCE_CLK, column_pins, row_pins, keys);

  assign column_pins = {PIO1_09, PIO1_08, PIO1_07, PIO1_06};
  pullup io1(PIO1_02, row_pins[0]);
  pullup io2(PIO1_03, row_pins[1]);
  pullup io3(PIO1_04, row_pins[2]);
  pullup io4(PIO1_05, row_pins[3]);

  integer i;
  reg [3:0] key = 0;

  always @(posedge iCE_CLK) begin
    key <= 0;
    for (i = 0; i < 16; i++)
      if (keys[i])
        key <= i;
  end

  assign LED4 = !(|keys);
  assign LED0 = key[3];
  assign LED1 = key[2];
  assign LED2 = key[1];
  assign LED3 = key[0];
endmodule