data/full_repos/permissive/175808891/verilog/prv32.v
 line:209: before: "("
1: b"%Error: data/full_repos/permissive/175808891/verilog/prv32.v:280: syntax error, unexpected type\n    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));\n                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:310: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    output reg [31:0] do\n                      ^~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:315: syntax error, unexpected '='\n        3'b100  : do = {24'b0,di[7:0]};\n                     ^\n%Error: Cannot continue\n"
module prv32_ID (
    input   wire [31:0] IR,
    output  wire        Imux_sel,
    output  wire [1:0]  WBmux_sel,
    output  wire        Cmux_sel,
    output  wire        SHmux_sel,
    output  wire        PCmux2_sel,
    output  wire        RAmux,
    output  wire        rfWr,
    output  wire        mWr,
    output  reg  [3:0]  ALU_sel,
    output  reg  [1:0]  ctrl,
    output              store,
    output              instr_w_rd,
    output              instr_w_rs1,
    output              instr_w_rs2

);
    
    wire [4:0] opcode = `OPCODE;
    wire [2:0] func3 = IR[`IR_funct3];
    wire [6:0] func7 = IR[`IR_funct7];
    
    wire I = (opcode == `OPCODE_Arith_I);
	wire R = (opcode == `OPCODE_Arith_R);
	wire IorR =  I | R;
	wire instr_logic = ((IorR==1'b1) && ((func3==`F3_XOR) || (func3==`F3_AND) || (func3==`F3_OR)));
	wire instr_shift = ((IorR==1'b1) && ((func3==`F3_SLL) || (func3==`F3_SRL) ));
	wire instr_slt = ((IorR==1'b1) && (func3==`F3_SLT));
	wire instr_sltu = ((IorR==1'b1) && (func3==`F3_SLTU));
	wire instr_store = (opcode == `OPCODE_Store);
	wire instr_load = (opcode == `OPCODE_Load);
	wire instr_add = R & (func3 == `F3_ADD) & (~func7[5]);
	wire instr_sub = R & (func3 == `F3_ADD) & (func7[5]);
	wire instr_addi = I & (func3 == `F3_ADD);
	wire instr_lui = (opcode == `OPCODE_LUI);
	wire instr_auipc = (opcode == `OPCODE_AUIPC);
	wire instr_branch = (opcode == `OPCODE_Branch);
	wire instr_jalr = (IR[`IR_opcode]==`OPCODE_JALR);
	wire instr_jal = (IR[`IR_opcode]==`OPCODE_JAL);
	wire instr_sll = ((IorR==1'b1) && (func3==`F3_SLL) && (func7 == 7'b0)); 
	wire instr_srl = ((IorR==1'b1) && (func3==`F3_SRL) && (func7 == 7'b0));
	wire instr_sra = ((IorR==1'b1) && (func3==`F3_SRL) && (func7 != 7'b0));
	wire instr_and = ((IorR==1'b1) && (func3==`F3_AND));
	wire instr_or = ((IorR==1'b1) && (func3==`F3_OR));
	wire instr_xor = ((IorR==1'b1) && (func3==`F3_XOR));
	
	assign instr_w_rd = (I | R | instr_auipc | instr_lui | instr_jalr | instr_jal | instr_load );
	assign instr_w_rs2 = IorR | instr_branch | instr_store;
	assign instr_w_rs1 = ~(instr_auipc | instr_lui | instr_jal);
	
	assign PCmux2_sel   =   instr_jalr;
	
    assign Cmux_sel     =   1'b1;
    assign WBmux_sel    =   instr_load ? 2'b11 :
                            (instr_jalr | instr_jal | instr_auipc) ? 2'b01 : 2'b00; 
    assign Imux_sel     =   instr_load  |
                            instr_store |

                            instr_lui   |
                            I           |
                            instr_jalr;
    assign SHmux_sel    =   I;
    assign rfWr = instr_load | IorR | instr_jalr | instr_jal | instr_lui |instr_auipc;
    assign RAmux = instr_auipc;
  
    assign mWr = instr_store;
    
    assign store = instr_store;
    


  
    always @ * begin
        case (1'b1)
            instr_load  :   ALU_sel = `ALU_ADD;
            instr_addi  :   ALU_sel = `ALU_ADD;
            instr_store :   ALU_sel = `ALU_ADD;
            instr_add   :   ALU_sel = `ALU_ADD; 
            instr_jalr  :   ALU_sel = `ALU_ADD;
            
            instr_lui   :   ALU_sel = `ALU_PASS;
            
            instr_sll   :   ALU_sel = `ALU_SLL;
            instr_srl   :   ALU_sel = `ALU_SRL;
            instr_sra   :   ALU_sel = `ALU_SRA;
            
            instr_slt   :   ALU_sel = `ALU_SLT;
            instr_sltu  :   ALU_sel = `ALU_SLTU;
            
            instr_and   :   ALU_sel = `ALU_AND;
            instr_or    :   ALU_sel = `ALU_OR;
            instr_xor   :   ALU_sel = `ALU_XOR;
            
            default     :   ALU_sel = `ALU_SUB;
        endcase
    end
    
    always @ * begin
        case (1'b1)
            instr_jalr  :   ctrl = 2'd1;
            instr_jal   :   ctrl = 2'd2;
            instr_branch:   ctrl = 2'd3;
            default     :   ctrl = 2'd0;
        endcase
    end
    
endmodule
module prv32_ID (
    input   wire [31:0] IR,
    output  wire        Imux_sel,
    output  wire [1:0]  WBmux_sel,
    output  wire        Cmux_sel,
    output  wire        SHmux_sel,
    output  wire        PCmux2_sel,
    output  wire        RAmux,
    output  wire        rfWr,
    output  wire        mWr,
    output  reg  [3:0]  ALU_sel,
    output  reg  [1:0]  ctrl,
    output              store,
    output              instr_w_rd,
    output              instr_w_rs1,
    output              instr_w_rs2

);

    
    wire [4:0] opcode = `OPCODE;
    wire [2:0] func3 = IR[`IR_funct3];
    wire [6:0] func7 = IR[`IR_funct7];
    
    wire I = (opcode == `OPCODE_Arith_I);
	wire R = (opcode == `OPCODE_Arith_R);
	wire IorR =  I | R;
	wire instr_logic = ((IorR==1'b1) && ((func3==`F3_XOR) || (func3==`F3_AND) || (func3==`F3_OR)));
	wire instr_shift = ((IorR==1'b1) && ((func3==`F3_SLL) || (func3==`F3_SRL) ));
	wire instr_slt = ((IorR==1'b1) && (func3==`F3_SLT));
	wire instr_sltu = ((IorR==1'b1) && (func3==`F3_SLTU));
	wire instr_store = (opcode == `OPCODE_Store);
	wire instr_load = (opcode == `OPCODE_Load);
	wire instr_add = R & (func3 == `F3_ADD) & (~func7[5]);
	wire instr_sub = R & (func3 == `F3_ADD) & (func7[5]);
	wire instr_addi = I & (func3 == `F3_ADD);
	wire instr_lui = (opcode == `OPCODE_LUI);
	wire instr_auipc = (opcode == `OPCODE_AUIPC);
	wire instr_branch = (opcode == `OPCODE_Branch);
	wire instr_jalr = (IR[`IR_opcode]==`OPCODE_JALR);
	wire instr_jal = (IR[`IR_opcode]==`OPCODE_JAL);
	wire instr_sll = ((IorR==1'b1) && (func3==`F3_SLL) && (func7 == 7'b0)); 
	wire instr_srl = ((IorR==1'b1) && (func3==`F3_SRL) && (func7 == 7'b0));
	wire instr_sra = ((IorR==1'b1) && (func3==`F3_SRL) && (func7 != 7'b0));
	wire instr_and = ((IorR==1'b1) && (func3==`F3_AND));
	wire instr_or = ((IorR==1'b1) && (func3==`F3_OR));
	wire instr_xor = ((IorR==1'b1) && (func3==`F3_XOR));
	
	assign instr_w_rd = (I | R | instr_auipc | instr_lui | instr_jalr | instr_jal | instr_load );
	assign instr_w_rs2 = IorR | instr_branch | instr_store;
	assign instr_w_rs1 = ~(instr_auipc | instr_lui | instr_jal);
	
	assign PCmux2_sel   =   instr_jalr;
	
    assign Cmux_sel     =   1'b1;
    assign WBmux_sel    =   instr_load ? 2'b11 :
                            (instr_jalr | instr_jal | instr_auipc) ? 2'b01 : 2'b00; 
    assign Imux_sel     =   instr_load  |
                            instr_store |

                            instr_lui   |
                            I           |
                            instr_jalr;
    assign SHmux_sel    =   I;
    assign rfWr = instr_load | IorR | instr_jalr | instr_jal | instr_lui |instr_auipc;
    assign RAmux = instr_auipc;
  
    assign mWr = instr_store;
    
    assign store = instr_store;
    


  
    always @ * begin
        case (1'b1)
            instr_load  :   ALU_sel = `ALU_ADD;
            instr_addi  :   ALU_sel = `ALU_ADD;
            instr_store :   ALU_sel = `ALU_ADD;
            instr_add   :   ALU_sel = `ALU_ADD; 
            instr_jalr  :   ALU_sel = `ALU_ADD;
            
            instr_lui   :   ALU_sel = `ALU_PASS;
            
            instr_sll   :   ALU_sel = `ALU_SLL;
            instr_srl   :   ALU_sel = `ALU_SRL;
            instr_sra   :   ALU_sel = `ALU_SRA;
            
            instr_slt   :   ALU_sel = `ALU_SLT;
            instr_sltu  :   ALU_sel = `ALU_SLTU;
            
            instr_and   :   ALU_sel = `ALU_AND;
            instr_or    :   ALU_sel = `ALU_OR;
            instr_xor   :   ALU_sel = `ALU_XOR;
            
            default     :   ALU_sel = `ALU_SUB;
        endcase
    end
    
    always @ * begin
        case (1'b1)
            instr_jalr  :   ctrl = 2'd1;
            instr_jal   :   ctrl = 2'd2;
            instr_branch:   ctrl = 2'd3;
            default     :   ctrl = 2'd0;
        endcase
    end
    
endmodule