data/full_repos/permissive/128659832/verilog/LEDS.v
 line:4 column:33: Illegal character "'"
data/verilator_xmls/68a8f178-ebda-4688-8b22-6ab4ae12ef76.xml
module LEDS #(
        parameter BASE_ADDR = 8'h 0A,
        data_width = 8
    ) (
        input wire clk,
        input wire [7:0] addr,
        input wire write_en,
        input wire rst,
        input wire [7:0] din,
        output wire [7:0] dout
    );

    reg [data_width-1:0] leds = 8'b 0;

    assign dout = leds;


    always @(posedge clk)
    begin
        if( rst ) leds <= 8'b 0;
        else if( write_en ) leds <= din;
        else leds <= leds;
    end

endmodule
module LEDS #(
        parameter BASE_ADDR = 8'h 0A,
        data_width = 8
    ) (
        input wire clk,
        input wire [7:0] addr,
        input wire write_en,
        input wire rst,
        input wire [7:0] din,
        output wire [7:0] dout
    );


    reg [data_width-1:0] leds = 8'b 0;

    assign dout = leds;


    always @(posedge clk)
    begin
        if( rst ) leds <= 8'b 0;
        else if( write_en ) leds <= din;
        else leds <= leds;
    end

endmodule