data/full_repos/permissive/137301388/source/mm_slave/product_test.v
data/verilator_xmls/bb928ab7-1c75-4d68-8f7f-d34308fce4f6.xml
module product_test(

clk_sys_i,
rst_n_i,


mm_s_addr_i,
mm_s_wdata_i,
mm_s_rdata_o,
mm_s_we_i,


pid_strap_i
);


parameter MM_ADDR_WIDTH = 8;
parameter MM_DATA_WIDTH = 16;

parameter REG_ADDR_PID = 'h00;
parameter REG_ADDR_TST = 'h02;

parameter FW_VERSION = 8'h01;


input clk_sys_i, rst_n_i;



input[MM_ADDR_WIDTH-1:0] mm_s_addr_i;
input[MM_DATA_WIDTH-1:0] mm_s_wdata_i;
output[MM_DATA_WIDTH-1:0] mm_s_rdata_o;

input mm_s_we_i;


input[3:0] pid_strap_i;


reg[3:0] pid_reg;
reg[MM_DATA_WIDTH-1:0] test_reg;
reg[MM_DATA_WIDTH-1:0] mm_s_rdata_o; 

reg edge_rst;



 always @(posedge clk_sys_i, negedge rst_n_i)
 begin
 	if(!rst_n_i) begin
 		test_reg <= 0;
 	end
 	else if(mm_s_we_i) begin
 		case(mm_s_addr_i)
 			REG_ADDR_TST:
 				test_reg <= mm_s_wdata_i;
 			default:
 				test_reg <= test_reg;
 		endcase
 	end
 end


always @(mm_s_addr_i, pid_reg, test_reg, rst_n_i)
begin
	if(!rst_n_i) begin
		mm_s_rdata_o <= 0;
	end
	else begin
		case(mm_s_addr_i)
			REG_ADDR_PID:
				mm_s_rdata_o <= {FW_VERSION, 4'h0, pid_reg[3:0]};
			REG_ADDR_TST:
 				mm_s_rdata_o <= test_reg;
			default:
				mm_s_rdata_o <= 0;
		endcase
	end
end



always @(posedge clk_sys_i)
begin
	edge_rst <= rst_n_i;
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i)
		pid_reg <= 0;
	else if(!edge_rst)
		pid_reg <= pid_strap_i;
	else
		pid_reg <= pid_reg;
end


endmodule
module product_test(

clk_sys_i,
rst_n_i,


mm_s_addr_i,
mm_s_wdata_i,
mm_s_rdata_o,
mm_s_we_i,


pid_strap_i
);



parameter MM_ADDR_WIDTH = 8;
parameter MM_DATA_WIDTH = 16;

parameter REG_ADDR_PID = 'h00;
parameter REG_ADDR_TST = 'h02;

parameter FW_VERSION = 8'h01;


input clk_sys_i, rst_n_i;



input[MM_ADDR_WIDTH-1:0] mm_s_addr_i;
input[MM_DATA_WIDTH-1:0] mm_s_wdata_i;
output[MM_DATA_WIDTH-1:0] mm_s_rdata_o;

input mm_s_we_i;


input[3:0] pid_strap_i;


reg[3:0] pid_reg;
reg[MM_DATA_WIDTH-1:0] test_reg;
reg[MM_DATA_WIDTH-1:0] mm_s_rdata_o; 

reg edge_rst;



 always @(posedge clk_sys_i, negedge rst_n_i)
 begin
 	if(!rst_n_i) begin
 		test_reg <= 0;
 	end
 	else if(mm_s_we_i) begin
 		case(mm_s_addr_i)
 			REG_ADDR_TST:
 				test_reg <= mm_s_wdata_i;
 			default:
 				test_reg <= test_reg;
 		endcase
 	end
 end


always @(mm_s_addr_i, pid_reg, test_reg, rst_n_i)
begin
	if(!rst_n_i) begin
		mm_s_rdata_o <= 0;
	end
	else begin
		case(mm_s_addr_i)
			REG_ADDR_PID:
				mm_s_rdata_o <= {FW_VERSION, 4'h0, pid_reg[3:0]};
			REG_ADDR_TST:
 				mm_s_rdata_o <= test_reg;
			default:
				mm_s_rdata_o <= 0;
		endcase
	end
end



always @(posedge clk_sys_i)
begin
	edge_rst <= rst_n_i;
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i)
		pid_reg <= 0;
	else if(!edge_rst)
		pid_reg <= pid_strap_i;
	else
		pid_reg <= pid_reg;
end


endmodule