data/full_repos/permissive/21051978/processor/cpu_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/21051978/processor/cpu_tb.v:15: Cannot find include file: cpu.v\n`include "cpu.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/cpu.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/cpu.v.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/cpu.v.sv\n             cpu.v\n             cpu.v.v\n             cpu.v.sv\n             obj_dir/cpu.v\n             obj_dir/cpu.v.v\n             obj_dir/cpu.v.sv\n%Error: data/full_repos/permissive/21051978/processor/cpu_tb.v:16: Cannot find include file: dmem.v\n`include "dmem.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/cpu_tb.v:17: Cannot find include file: imem.v\n`include "imem.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/cpu_tb.v:75: syntax error, unexpected \'@\'\n  repeat(5) @(negedge Clk);               \n            ^\n%Error: data/full_repos/permissive/21051978/processor/cpu_tb.v:80: Unsupported: wait statements\n  wait (Instruction == 32\'h00000000);\n  ^~~~\n%Error: data/full_repos/permissive/21051978/processor/cpu_tb.v:84: syntax error, unexpected \'@\'\n  repeat(5) @(negedge Clk); \n            ^\n%Error: data/full_repos/permissive/21051978/processor/cpu_tb.v:86: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n  dmem_dump_file = $fopen("dmem.dump");  \n                   ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/cpu_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n   always #(5 / 2) Clk <= ~Clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 7 error(s), 1 warning(s)\n'
module cpu_tb;
reg Clk, Reset;
wire [0:31] ProgramCounter;
wire [0:31] Instruction;
wire [0:20] MemAddr;
wire [0:127] DataIn, DataOut;

   integer 	 dmem_dump_file;
   integer 	 i;
   integer 	 cycle_number;



imem IM(
         .addr       (ProgramCounter[22:29]),
         .dataOut    (Instruction)
         );


cpu TROY (
        .clk          (Clk), 
        .reset        (Reset), 
        .instruction  (Instruction),
        .pc           (ProgramCounter),
        .dataIn       (DataIn),
        .dataOut      (DataOut),
        .memAddr      (MemAddr),
        .memWrEn      (MemWrEn),
        .memEn        (MemEn)
        );


dmem DMEM (
             .clk	   (Clk),
             .memAddr   (MemAddr[13:20]),
             .dataIn    (DataOut),
             .wrEn      (MemWrEn),
             .memEn     (MemEn),
             .dataOut   (DataIn)
            );




   initial
     begin
		$readmemh("imem.fill", IM.mem);
		$readmemh("dmem.fill", DMEM.mem);
		Clk <= 0;
		Reset <= 1'b1;
		repeat(5) @(negedge Clk);
		Reset <= 1'b0;



		wait (Instruction == 32'h00000000);

		$display("The program completed in %d cycles", cycle_number);

		repeat(5) @(negedge Clk); 

		dmem_dump_file = $fopen("dmem.dump");

		for (i=0; i<64; i=i+1)
		  begin
			 $fdisplay(dmem_dump_file, "Memory location #%d : %h ", i, DMEM.mem[i]);
  		  end
		$fclose(dmem_dump_file);
		$stop;
	 end
   

   always #(`CYCLE_TIME / 2) Clk <= ~Clk;
   

   always @ (posedge Clk)
	 begin
		if (Reset)
		  cycle_number <= 0;
		else
		  cycle_number <= cycle_number + 1;
	 end


endmodule
module cpu_tb;

reg Clk, Reset;
wire [0:31] ProgramCounter;
wire [0:31] Instruction;
wire [0:20] MemAddr;
wire [0:127] DataIn, DataOut;

   integer 	 dmem_dump_file;
   integer 	 i;
   integer 	 cycle_number;



imem IM(
         .addr       (ProgramCounter[22:29]),
         .dataOut    (Instruction)
         );


cpu TROY (
        .clk          (Clk), 
        .reset        (Reset), 
        .instruction  (Instruction),
        .pc           (ProgramCounter),
        .dataIn       (DataIn),
        .dataOut      (DataOut),
        .memAddr      (MemAddr),
        .memWrEn      (MemWrEn),
        .memEn        (MemEn)
        );


dmem DMEM (
             .clk	   (Clk),
             .memAddr   (MemAddr[13:20]),
             .dataIn    (DataOut),
             .wrEn      (MemWrEn),
             .memEn     (MemEn),
             .dataOut   (DataIn)
            );




   initial
     begin
		$readmemh("imem.fill", IM.mem);
		$readmemh("dmem.fill", DMEM.mem);
		Clk <= 0;
		Reset <= 1'b1;
		repeat(5) @(negedge Clk);
		Reset <= 1'b0;



		wait (Instruction == 32'h00000000);

		$display("The program completed in %d cycles", cycle_number);

		repeat(5) @(negedge Clk); 

		dmem_dump_file = $fopen("dmem.dump");

		for (i=0; i<64; i=i+1)
		  begin
			 $fdisplay(dmem_dump_file, "Memory location #%d : %h ", i, DMEM.mem[i]);
  		  end
		$fclose(dmem_dump_file);
		$stop;
	 end
   

   always #(`CYCLE_TIME / 2) Clk <= ~Clk;
   

   always @ (posedge Clk)
	 begin
		if (Reset)
		  cycle_number <= 0;
		else
		  cycle_number <= cycle_number + 1;
	 end


endmodule