data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v
 line:61: before: "("
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:3: Cannot find include file: ../s2p/freq_div_cond.v\n`include "../s2p/freq_div_cond.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/../s2p/freq_div_cond.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/../s2p/freq_div_cond.v.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/../s2p/freq_div_cond.v.sv\n             ../s2p/freq_div_cond.v\n             ../s2p/freq_div_cond.v.v\n             ../s2p/freq_div_cond.v.sv\n             obj_dir/../s2p/freq_div_cond.v\n             obj_dir/../s2p/freq_div_cond.v.v\n             obj_dir/../s2p/freq_div_cond.v.sv\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:24: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("p2s_s2p.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:25: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:34: Unsupported: Ignoring delay on this delayed statement.\n    repeat(2) #500 CLK_2MHz = ~CLK_2MHz;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #500\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:38: Unsupported: Ignoring delay on this delayed statement.\n    forever #500 CLK_2MHz = ~CLK_2MHz;\n            ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:46: syntax error, unexpected \'@\'\n    @(posedge ENB)\n    ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:49: syntax error, unexpected \'@\'\n    repeat(8) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:51: syntax error, unexpected \'@\'\n    repeat(8) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:53: syntax error, unexpected \'@\'\n    repeat(8) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:55: syntax error, unexpected \'@\'\n    repeat(8) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:57: syntax error, unexpected \'@\'\n    repeat(8) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:59: syntax error, unexpected \'@\'\n    repeat(8) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:61: syntax error, unexpected \'@\'\n    repeat(8) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:63: syntax error, unexpected \'@\'\n    repeat(8) @(posedge CLK_2MHz);\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/tester.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #500 $finish;\n    ^\n%Error: Exiting due to 12 error(s), 4 warning(s)\n'
module tester_s2p(  output reg          CLK_2MHz,
                    output              CLK_1MHz,
                    output              CLK_500KHz,
                    output              CLK_250KHz,
                    output reg          ENB,
                    output reg          reset,

                    output reg  [31:0]  DATO,
                    output reg          VALID
                    );

  freq_div_cond clocks_cond ( .CLK    (CLK_2MHz),
                              .reset  (reset),
                              .CLK_2  (CLK_1MHz),
                              .CLK_4  (CLK_500KHz),
                              .CLK_8  (CLK_250KHz)
                              );

  initial begin
    $dumpfile("p2s_s2p.vcd");
    $dumpvars;
  end

  initial begin
    CLK_2MHz = 1'b0;
    ENB = 1'b0;
    reset = 1'b0;

    #500
    repeat(2) #500 CLK_2MHz = ~CLK_2MHz;
    ENB = 1'b1;
    reset = 1'b1;
    VALID = 1'b1;
    forever #500 CLK_2MHz = ~CLK_2MHz;
  end





  initial begin
    @(posedge ENB)
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h01234567;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h89ABCDEF;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h092B4D6F;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h81A3C5E7;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h76543210;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'hFEDCBA98;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'hF6D4B290;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h7E5C3A18;
    repeat(8) @(posedge CLK_2MHz);
    #500 $finish;
  end

endmodule
module tester_s2p(  output reg          CLK_2MHz,
                    output              CLK_1MHz,
                    output              CLK_500KHz,
                    output              CLK_250KHz,
                    output reg          ENB,
                    output reg          reset,

                    output reg  [31:0]  DATO,
                    output reg          VALID
                    );


  freq_div_cond clocks_cond ( .CLK    (CLK_2MHz),
                              .reset  (reset),
                              .CLK_2  (CLK_1MHz),
                              .CLK_4  (CLK_500KHz),
                              .CLK_8  (CLK_250KHz)
                              );

  initial begin
    $dumpfile("p2s_s2p.vcd");
    $dumpvars;
  end

  initial begin
    CLK_2MHz = 1'b0;
    ENB = 1'b0;
    reset = 1'b0;

    #500
    repeat(2) #500 CLK_2MHz = ~CLK_2MHz;
    ENB = 1'b1;
    reset = 1'b1;
    VALID = 1'b1;
    forever #500 CLK_2MHz = ~CLK_2MHz;
  end





  initial begin
    @(posedge ENB)
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h01234567;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h89ABCDEF;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h092B4D6F;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h81A3C5E7;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h76543210;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'hFEDCBA98;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'hF6D4B290;
    repeat(8) @(posedge CLK_2MHz);
    DATO = 32'h7E5C3A18;
    repeat(8) @(posedge CLK_2MHz);
    #500 $finish;
  end

endmodule