data/full_repos/permissive/100597706/testing/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n   always # 5 clk = ~ clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[4] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[4] = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[14] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[14] = 1\'b0;\n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module m_wrapper #(parameter logHBank = 10) (
	input clk,
	input [31:0] baddr,
	input [31:0] bdi,
	input [1:0] bsz,
	input bwr,
	output [31:0] bdo,
	output brdy,
	output CS
);

	wire [31:0] bdo_m;
	wire brdy_m;


`ifdef _DBUG_
	always @ (posedge clk)begin
		$display("baddr_m: %h, CSM = %b, bdo_m = %h, brdy_m = %b", baddr, CS, bdo_m, brdy_m);
	end

`endif
	assign CS = (baddr[31:logHBank+2] == 0);

	wire mwr = CS & bwr;

	memory #(logHBank) M (.clk(clk), .bdi(bdi), .baddr(baddr), .bdo(bdo_m), .mwr(mwr), .bsz(bsz), .brdy(brdy_m));

    assign bdo = CS? bdo_m : 32'hZZZZZZZZ;
	assign brdy = CS? brdy_m : 1'bz;

endmodule
module m_wrapper #(parameter logHBank = 10) (
	input clk,
	input [31:0] baddr,
	input [31:0] bdi,
	input [1:0] bsz,
	input bwr,
	output [31:0] bdo,
	output brdy,
	output CS
);


	wire [31:0] bdo_m;
	wire brdy_m;


`ifdef _DBUG_
	always @ (posedge clk)begin
		$display("baddr_m: %h, CSM = %b, bdo_m = %h, brdy_m = %b", baddr, CS, bdo_m, brdy_m);
	end

`endif
	assign CS = (baddr[31:logHBank+2] == 0);

	wire mwr = CS & bwr;

	memory #(logHBank) M (.clk(clk), .bdi(bdi), .baddr(baddr), .bdo(bdo_m), .mwr(mwr), .bsz(bsz), .brdy(brdy_m));

    assign bdo = CS? bdo_m : 32'hZZZZZZZZ;
	assign brdy = CS? brdy_m : 1'bz;

endmodule