data/full_repos/permissive/130536678/Pipeline-With-Hazard-And-Forwarding/CPU_TEST.v
 line:34: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/130536678/Pipeline-With-Hazard-And-Forwarding/CPU_TEST.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #30 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/130536678/Pipeline-With-Hazard-And-Forwarding/CPU_TEST.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #1 CLOCK = ~CLOCK; RESET = 1\'b0;\n    ^\n%Error: data/full_repos/permissive/130536678/Pipeline-With-Hazard-And-Forwarding/CPU_TEST.v:26: Cannot find file containing module: \'ARM_CPU\'\n  ARM_CPU core (RESET, CLOCK, IC_wire, mem_data_out, PC_wire, mem_address, mem_data_in, control_memwrite, control_memread);\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/130536678/Pipeline-With-Hazard-And-Forwarding,data/full_repos/permissive/130536678/ARM_CPU\n             data/full_repos/permissive/130536678/Pipeline-With-Hazard-And-Forwarding,data/full_repos/permissive/130536678/ARM_CPU.v\n             data/full_repos/permissive/130536678/Pipeline-With-Hazard-And-Forwarding,data/full_repos/permissive/130536678/ARM_CPU.sv\n             ARM_CPU\n             ARM_CPU.v\n             ARM_CPU.sv\n             obj_dir/ARM_CPU\n             obj_dir/ARM_CPU.v\n             obj_dir/ARM_CPU.sv\n%Error: data/full_repos/permissive/130536678/Pipeline-With-Hazard-And-Forwarding/CPU_TEST.v:27: Cannot find file containing module: \'IC\'\n  IC mem1 (PC_wire, IC_wire);\n  ^~\n%Error: data/full_repos/permissive/130536678/Pipeline-With-Hazard-And-Forwarding/CPU_TEST.v:28: Cannot find file containing module: \'Data_Memory\'\n  Data_Memory mem2 (mem_address, mem_data_in, control_memwrite, control_memread, mem_data_out);\n  ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPU_TEST;
  

  reg RESET;
  reg CLOCK;
  

  wire [63:0] PC_wire;
  wire [31:0] IC_wire;
  

  wire [63:0] mem_address;
  wire [63:0] mem_data_in;
  wire control_memwrite;
  wire control_memread;
  wire [63:0] mem_data_out;
  
  ARM_CPU core (RESET, CLOCK, IC_wire, mem_data_out, PC_wire, mem_address, mem_data_in, control_memwrite, control_memread);
  IC mem1 (PC_wire, IC_wire);
  Data_Memory mem2 (mem_address, mem_data_in, control_memwrite, control_memread, mem_data_out);
  

  initial begin
    CLOCK = 1'b0;
    RESET = 1'b1;
    #30 $finish;
  end
  

  always begin
    #1 CLOCK = ~CLOCK; RESET = 1'b0;
  end
  
endmodule
module CPU_TEST;

  

  reg RESET;
  reg CLOCK;
  

  wire [63:0] PC_wire;
  wire [31:0] IC_wire;
  

  wire [63:0] mem_address;
  wire [63:0] mem_data_in;
  wire control_memwrite;
  wire control_memread;
  wire [63:0] mem_data_out;
  
  ARM_CPU core (RESET, CLOCK, IC_wire, mem_data_out, PC_wire, mem_address, mem_data_in, control_memwrite, control_memread);
  IC mem1 (PC_wire, IC_wire);
  Data_Memory mem2 (mem_address, mem_data_in, control_memwrite, control_memread, mem_data_out);
  

  initial begin
    CLOCK = 1'b0;
    RESET = 1'b1;
    #30 $finish;
  end
  

  always begin
    #1 CLOCK = ~CLOCK; RESET = 1'b0;
  end
  
endmodule