data/full_repos/permissive/123786074/processor_top/alu.v
data/verilator_xmls/87224eb5-bebf-45df-bf53-e73be9757b63.xml
module alu (
	A_bus,
	B_bus,
	operator,
	C_bus,
	Z); 

 input 			[15:0] 	A_bus;
 input 			[15:0] 	B_bus;
 input 			[2:0]  	operator;
 output reg		[15:0] 	C_bus;
 output reg   				Z=0;

  
 parameter 	ADD=3'd0,
				SUB=3'd1,
				PASS=3'd2,
				ZER=3'd3,
				DECA=3'd4,
				MUL4=3'd5,
				DIV2=3'd6;
  
 always@(operator or A_bus or B_bus) 
 begin
	case (operator)
		ADD: 
			begin 
				C_bus = A_bus + B_bus; 
				Z = (C_bus==16'd0); 
			end 
		SUB: 
			begin 
				C_bus = A_bus - B_bus; 
				Z = (C_bus==16'd0);
			end
		PASS: 
			begin 
				C_bus = B_bus; 
				Z = (C_bus==16'd0);
			end
		ZER: 
			begin 
				C_bus = 0; 
				Z = 0;
			end 
		DECA:
			begin 
				C_bus = A_bus-16'd1;
				Z = (C_bus==16'd0);
			end 
		MUL4:
			begin
				C_bus = B_bus << 2;
				Z = 0;
			end
		DIV2:
			begin
				C_bus = B_bus >> 1; 
				Z = (C_bus==16'd0);
			end 
    
	endcase 
 end 
endmodule
module alu (
	A_bus,
	B_bus,
	operator,
	C_bus,
	Z);
 

 input 			[15:0] 	A_bus;
 input 			[15:0] 	B_bus;
 input 			[2:0]  	operator;
 output reg		[15:0] 	C_bus;
 output reg   				Z=0;

  
 parameter 	ADD=3'd0,
				SUB=3'd1,
				PASS=3'd2,
				ZER=3'd3,
				DECA=3'd4,
				MUL4=3'd5,
				DIV2=3'd6;
  
 always@(operator or A_bus or B_bus) 
 begin
	case (operator)
		ADD: 
			begin 
				C_bus = A_bus + B_bus; 
				Z = (C_bus==16'd0); 
			end 
		SUB: 
			begin 
				C_bus = A_bus - B_bus; 
				Z = (C_bus==16'd0);
			end
		PASS: 
			begin 
				C_bus = B_bus; 
				Z = (C_bus==16'd0);
			end
		ZER: 
			begin 
				C_bus = 0; 
				Z = 0;
			end 
		DECA:
			begin 
				C_bus = A_bus-16'd1;
				Z = (C_bus==16'd0);
			end 
		MUL4:
			begin
				C_bus = B_bus << 2;
				Z = 0;
			end
		DIV2:
			begin
				C_bus = B_bus >> 1; 
				Z = (C_bus==16'd0);
			end 
    
	endcase 
 end 
endmodule