data/full_repos/permissive/135852214/Verilog/mexor4.v
data/verilator_xmls/582e3612-4795-485c-b883-e4c3cc394350.xml
module mexor4(
    input [5:0] in,
    output [5:0] out
    );
wire w;
assign w = in[0] & in[1];
assign out[0] = in[0];
assign out[1] = in[1];
assign out[2] = in[2] ^ w;
assign out[3] = in[3] ^ w;
assign out[4] = in[4] ^ w;
assign out[5] = in[5] ^ w;

endmodule
module mexor4(
    input [5:0] in,
    output [5:0] out
    );

wire w;
assign w = in[0] & in[1];
assign out[0] = in[0];
assign out[1] = in[1];
assign out[2] = in[2] ^ w;
assign out[3] = in[3] ^ w;
assign out[4] = in[4] ^ w;
assign out[5] = in[5] ^ w;

endmodule