data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v
 line:22: before: "."
1: b'%Warning-MULTITOP: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:347: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'fpga_top\'\nmodule fpga_top(output wire WF_NEO);\n       ^~~~~~~~\n                                                                                                : ... Top module \'WF_random_5\'\n   module WF_random_5 (\n          ^~~~~~~~~~~\n                                                                                                : ... Top module \'WF_switch_debounce\'\n   module WF_switch_debounce (\n          ^~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:26: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:28: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:34: Signal definition not found, creating implicitly: \'two_ms\'\n           .timer_pulse(two_ms));\n                        ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:262: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance fpga_top.neopixel_inst\n                   pixel_bit_cnt <= 1\'b0;\n                                 ^~\n%Error: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:16: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.v\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module WF_timer (
       input  wire clk,
       input  wire enable,
       output reg  timer_pulse
   );

   parameter [9:0] COUNT = 499;
   parameter       EVERY_CLK = 1'b0;

    reg [9:0] counter;

    always @ (posedge clk)
        if (enable)
          begin
            if (counter == COUNT)
              begin
                timer_pulse <= 1'b1;
                counter     <= 'b0;
              end
           else
             begin
              counter     <= counter + 'b1;
              if (EVERY_CLK)
               timer_pulse <= 1'b0;
             end

          end
        else
            timer_pulse <= 1'b0;

   endmodule
module WF_timer (
       input  wire clk,
       input  wire enable,
       output reg  timer_pulse
   );


   parameter [9:0] COUNT = 499;
   parameter       EVERY_CLK = 1'b0;

    reg [9:0] counter;

    always @ (posedge clk)
        if (enable)
          begin
            if (counter == COUNT)
              begin
                timer_pulse <= 1'b1;
                counter     <= 'b0;
              end
           else
             begin
              counter     <= counter + 'b1;
              if (EVERY_CLK)
               timer_pulse <= 1'b0;
             end

          end
        else
            timer_pulse <= 1'b0;

   endmodule