data/full_repos/permissive/211866113/accumulator_tester.v
 line:176: before: "for"
1: b'%Error: data/full_repos/permissive/211866113/accumulator_tester.v:1: Cannot find include file: Accumulator.v\n`include "Accumulator.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/Accumulator.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/Accumulator.v.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/Accumulator.v.sv\n             Accumulator.v\n             Accumulator.v.v\n             Accumulator.v.sv\n             obj_dir/Accumulator.v\n             obj_dir/Accumulator.v.v\n             obj_dir/Accumulator.v.sv\n%Error: data/full_repos/permissive/211866113/accumulator_tester.v:2: Cannot find include file: word_gen.v\n`include "word_gen.v" \n         ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/211866113/accumulator_tester.v:34: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/211866113/accumulator_tester.v:38: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("Basic_Accumulator_test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/211866113/accumulator_tester.v:39: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0);  \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/211866113/accumulator_tester.v:41: Unsupported or unknown PLI call: $monitor\n        $monitor($time, "\\t%b\\t%b\\t%b\\t%b", clk, reset, Input, Output);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/211866113/accumulator_tester.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = TRUE;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/accumulator_tester.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #5 reset = FALSE;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/accumulator_tester.v:49: Unsupported: Ignoring delay on this delayed statement.\n            #1 gen_next = FALSE;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/accumulator_tester.v:50: Unsupported: Ignoring delay on this delayed statement.\n            if (i==3) #5 $finish;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/accumulator_tester.v:51: Unsupported: Ignoring delay on this delayed statement.\n            #9 gen_next = TRUE;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/accumulator_tester.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/accumulator_tester.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #5 $finish;\n        ^\n%Error: Exiting due to 5 error(s), 8 warning(s)\n'
module Accumulator_tester ();
    parameter FALSE = 1'b0;
    parameter TRUE = 1'b1;

    integer i;

    reg     clk = 1'b0;


    reg     gen_next;
    wire [2:0] Input;


    wire [2:0] Output;
    wire carry;
    reg    reset;

    word_gen my_gen(gen_next, Input);
    accumulator my_acc(clk, reset, Input, Output);

    always begin
	clk <= ~clk;
	#5;
    end

    initial begin
        $dumpfile("Basic_Accumulator_test.vcd");
        $dumpvars(0);
        $display("\t\ttime \tclk\treset\tInput\tOutput");
        $monitor($time, "\t%b\t%b\t%b\t%b", clk, reset, Input, Output);
        i=0;
        reset = FALSE;

        #10 reset = TRUE;
        #5 reset = FALSE;
        #5
        for (i = 0; i< 4; i = i + 1) begin
            #1 gen_next = FALSE;
            if (i==3) #5 $finish;
            #9 gen_next = TRUE;
        end
        #5 $finish;
    end

endmodule
module Accumulator_tester ();

    parameter FALSE = 1'b0;
    parameter TRUE = 1'b1;

    integer i;

    reg     clk = 1'b0;


    reg     gen_next;
    wire [2:0] Input;


    wire [2:0] Output;
    wire carry;
    reg    reset;

    word_gen my_gen(gen_next, Input);
    accumulator my_acc(clk, reset, Input, Output);

    always begin
	clk <= ~clk;
	#5;
    end

    initial begin
        $dumpfile("Basic_Accumulator_test.vcd");
        $dumpvars(0);
        $display("\t\ttime \tclk\treset\tInput\tOutput");
        $monitor($time, "\t%b\t%b\t%b\t%b", clk, reset, Input, Output);
        i=0;
        reset = FALSE;

        #10 reset = TRUE;
        #5 reset = FALSE;
        #5
        for (i = 0; i< 4; i = i + 1) begin
            #1 gen_next = FALSE;
            if (i==3) #5 $finish;
            #9 gen_next = TRUE;
        end
        #5 $finish;
    end

endmodule