data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:71: Cell has missing pin: \'extlock\'\n  PLL uut (\n      ^~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:231: Cell has missing pin: \'en\'\n  reg_ar_as_w12 reg0 (\n                ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:237: Cell has missing pin: \'en\'\n  reg_ar_as_w12 reg1 (\n                ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:287: Cell has missing pin: \'en\'\n  reg_ar_as_w24 reg0 (\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n0\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n1\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n2\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n3\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n4\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n5\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n6\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n7\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n8\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n9\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                                ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n10\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                                        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n11\'\n                                                                                             : ... Suggested alternative: \'open_n1\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                                                 ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n12\'\n                                                                                             : ... Suggested alternative: \'open_n1\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                                                          ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n13\'\n                                                                                             : ... Suggested alternative: \'open_n1\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                                                                   ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n14\'\n                                                                                             : ... Suggested alternative: \'open_n1\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                                                                            ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n15\'\n                                                                                             : ... Suggested alternative: \'open_n1\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                                                                                     ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n16\'\n                                                                                             : ... Suggested alternative: \'open_n1\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                                                                                              ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n17\'\n                                                                                             : ... Suggested alternative: \'open_n1\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                                                                                                       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n18\'\n                                                                                             : ... Suggested alternative: \'open_n1\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                                                                                                                ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:225: Signal definition not found, creating implicitly: \'open_n19\'\n                                                                                             : ... Suggested alternative: \'open_n1\'\n    .o({open_n0,open_n1,open_n2,open_n3,open_n4,open_n5,open_n6,open_n7,open_n8,open_n9,open_n10,open_n11,open_n12,open_n13,open_n14,open_n15,open_n16,open_n17,open_n18,open_n19,lcd_xpos}));   \n                                                                                                                                                                         ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n20\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n21\'\n                                                                                             : ... Suggested alternative: \'open_n1\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                 ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n22\'\n                                                                                             : ... Suggested alternative: \'open_n12\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                          ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n23\'\n                                                                                             : ... Suggested alternative: \'open_n13\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                   ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n24\'\n                                                                                             : ... Suggested alternative: \'open_n14\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                            ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n25\'\n                                                                                             : ... Suggested alternative: \'open_n15\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                     ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n26\'\n                                                                                             : ... Suggested alternative: \'open_n16\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                              ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n27\'\n                                                                                             : ... Suggested alternative: \'open_n17\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n28\'\n                                                                                             : ... Suggested alternative: \'open_n18\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n29\'\n                                                                                             : ... Suggested alternative: \'open_n19\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                         ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n30\'\n                                                                                             : ... Suggested alternative: \'open_n0\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                                  ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n31\'\n                                                                                             : ... Suggested alternative: \'open_n1\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                                           ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n32\'\n                                                                                             : ... Suggested alternative: \'open_n12\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                                                    ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n33\'\n                                                                                             : ... Suggested alternative: \'open_n13\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                                                             ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n34\'\n                                                                                             : ... Suggested alternative: \'open_n14\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                                                                      ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n35\'\n                                                                                             : ... Suggested alternative: \'open_n15\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                                                                               ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n36\'\n                                                                                             : ... Suggested alternative: \'open_n16\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                                                                                        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n37\'\n                                                                                             : ... Suggested alternative: \'open_n17\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                                                                                                 ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n38\'\n                                                                                             : ... Suggested alternative: \'open_n18\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                                                                                                          ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:230: Signal definition not found, creating implicitly: \'open_n39\'\n                                                                                             : ... Suggested alternative: \'open_n19\'\n    .o({open_n20,open_n21,open_n22,open_n23,open_n24,open_n25,open_n26,open_n27,open_n28,open_n29,open_n30,open_n31,open_n32,open_n33,open_n34,open_n35,open_n36,open_n37,open_n38,open_n39,lcd_ypos}));   \n                                                                                                                                                                                   ^~~~~~~~\n%Error: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:312: Cannot find file containing module: \'EG_LOGIC_BUFG\'\n  EG_LOGIC_BUFG bufg_feedback (\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/8_VGA_Demo,data/full_repos/permissive/194847941/EG_LOGIC_BUFG\n             data/full_repos/permissive/194847941/demo/8_VGA_Demo,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.v\n             data/full_repos/permissive/194847941/demo/8_VGA_Demo,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.sv\n             EG_LOGIC_BUFG\n             EG_LOGIC_BUFG.v\n             EG_LOGIC_BUFG.sv\n             obj_dir/EG_LOGIC_BUFG\n             obj_dir/EG_LOGIC_BUFG.v\n             obj_dir/EG_LOGIC_BUFG.sv\n%Error: data/full_repos/permissive/194847941/demo/8_VGA_Demo/VGA_Demo_tdread.v:315: Cannot find file containing module: \'EG_PHY_PLL\'\n  EG_PHY_PLL #(\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 44 warning(s)\n'
module PLL
  (
  refclk,
  reset,
  clk0_out,
  extlock
  );

  input refclk;
  input reset;
  output clk0_out;
  output extlock;

  wire clk0_buf;

  EG_LOGIC_BUFG bufg_feedback (
    .i(clk0_buf),
    .o(clk0_out));
  EG_PHY_PLL #(
    .CLKC0_CPHASE(8),
    .CLKC0_DIV(9),
    .CLKC0_DIV2_ENABLE("DISABLE"),
    .CLKC0_ENABLE("ENABLE"),
    .CLKC0_FPHASE(0),
    .CLKC1_CPHASE(1),
    .CLKC1_DIV(1),
    .CLKC1_DIV2_ENABLE("DISABLE"),
    .CLKC1_ENABLE("DISABLE"),
    .CLKC1_FPHASE(0),
    .CLKC2_CPHASE(1),
    .CLKC2_DIV(1),
    .CLKC2_DIV2_ENABLE("DISABLE"),
    .CLKC2_ENABLE("DISABLE"),
    .CLKC2_FPHASE(0),
    .CLKC3_CPHASE(1),
    .CLKC3_DIV(1),
    .CLKC3_DIV2_ENABLE("DISABLE"),
    .CLKC3_ENABLE("DISABLE"),
    .CLKC3_FPHASE(0),
    .CLKC4_CPHASE(1),
    .CLKC4_DIV(1),
    .CLKC4_DIV2_ENABLE("DISABLE"),
    .CLKC4_ENABLE("DISABLE"),
    .CLKC4_FPHASE(0),
    .DERIVE_PLL_CLOCKS("DISABLE"),
    .DPHASE_SOURCE("DISABLE"),
    .DYNCFG("DISABLE"),
    .FBCLK_DIV(9),
    .FEEDBK_MODE("NORMAL"),
    .FEEDBK_PATH("CLKC0_EXT"),
    .FIN("24.000"),
    .FREQ_LOCK_ACCURACY(2),
    .GEN_BASIC_CLOCK("DISABLE"),
    .GMC_GAIN(6),
    .GMC_TEST(14),
    .ICP_CURRENT(3),
    .IF_ESCLKSTSW("DISABLE"),
    .INTFB_WAKE("DISABLE"),
    .KVCO(6),
    .LPF_CAPACITOR(3),
    .LPF_RESISTOR(2),
    .NORESET("DISABLE"),
    .ODIV_MUXC0("DIV"),
    .ODIV_MUXC1("DIV"),
    .ODIV_MUXC2("DIV"),
    .ODIV_MUXC3("DIV"),
    .ODIV_MUXC4("DIV"),
    .PLLC2RST_ENA("DISABLE"),
    .PLLC34RST_ENA("DISABLE"),
    .PLLMRST_ENA("DISABLE"),
    .PLLRST_ENA("ENABLE"),
    .PLL_LOCK_MODE(0),
    .PREDIV_MUXC0("VCO"),
    .PREDIV_MUXC1("VCO"),
    .PREDIV_MUXC2("VCO"),
    .PREDIV_MUXC3("VCO"),
    .PREDIV_MUXC4("VCO"),
    .REFCLK_DIV(2),
    .REFCLK_SEL("INTERNAL"),
    .STDBY_ENABLE("DISABLE"),
    .STDBY_VCO_ENA("DISABLE"),
    .SYNC_ENABLE("DISABLE"),
    .VCO_NORESET("DISABLE"))
    pll_inst (
    .daddr(6'b000000),
    .dclk(1'b0),
    .dcs(1'b0),
    .di(8'b00000000),
    .dwe(1'b0),
    .fbclk(clk0_out),
    .psclk(1'b0),
    .psclksel(3'b000),
    .psdown(1'b0),
    .psstep(1'b0),
    .refclk(refclk),
    .reset(reset),
    .stdby(1'b0),
    .clkc({open_n0,open_n1,open_n2,open_n3,clk0_buf}),
    .extlock(extlock));

endmodule
module PLL
  (
  refclk,
  reset,
  clk0_out,
  extlock
  );


  input refclk;
  input reset;
  output clk0_out;
  output extlock;

  wire clk0_buf;

  EG_LOGIC_BUFG bufg_feedback (
    .i(clk0_buf),
    .o(clk0_out));
  EG_PHY_PLL #(
    .CLKC0_CPHASE(8),
    .CLKC0_DIV(9),
    .CLKC0_DIV2_ENABLE("DISABLE"),
    .CLKC0_ENABLE("ENABLE"),
    .CLKC0_FPHASE(0),
    .CLKC1_CPHASE(1),
    .CLKC1_DIV(1),
    .CLKC1_DIV2_ENABLE("DISABLE"),
    .CLKC1_ENABLE("DISABLE"),
    .CLKC1_FPHASE(0),
    .CLKC2_CPHASE(1),
    .CLKC2_DIV(1),
    .CLKC2_DIV2_ENABLE("DISABLE"),
    .CLKC2_ENABLE("DISABLE"),
    .CLKC2_FPHASE(0),
    .CLKC3_CPHASE(1),
    .CLKC3_DIV(1),
    .CLKC3_DIV2_ENABLE("DISABLE"),
    .CLKC3_ENABLE("DISABLE"),
    .CLKC3_FPHASE(0),
    .CLKC4_CPHASE(1),
    .CLKC4_DIV(1),
    .CLKC4_DIV2_ENABLE("DISABLE"),
    .CLKC4_ENABLE("DISABLE"),
    .CLKC4_FPHASE(0),
    .DERIVE_PLL_CLOCKS("DISABLE"),
    .DPHASE_SOURCE("DISABLE"),
    .DYNCFG("DISABLE"),
    .FBCLK_DIV(9),
    .FEEDBK_MODE("NORMAL"),
    .FEEDBK_PATH("CLKC0_EXT"),
    .FIN("24.000"),
    .FREQ_LOCK_ACCURACY(2),
    .GEN_BASIC_CLOCK("DISABLE"),
    .GMC_GAIN(6),
    .GMC_TEST(14),
    .ICP_CURRENT(3),
    .IF_ESCLKSTSW("DISABLE"),
    .INTFB_WAKE("DISABLE"),
    .KVCO(6),
    .LPF_CAPACITOR(3),
    .LPF_RESISTOR(2),
    .NORESET("DISABLE"),
    .ODIV_MUXC0("DIV"),
    .ODIV_MUXC1("DIV"),
    .ODIV_MUXC2("DIV"),
    .ODIV_MUXC3("DIV"),
    .ODIV_MUXC4("DIV"),
    .PLLC2RST_ENA("DISABLE"),
    .PLLC34RST_ENA("DISABLE"),
    .PLLMRST_ENA("DISABLE"),
    .PLLRST_ENA("ENABLE"),
    .PLL_LOCK_MODE(0),
    .PREDIV_MUXC0("VCO"),
    .PREDIV_MUXC1("VCO"),
    .PREDIV_MUXC2("VCO"),
    .PREDIV_MUXC3("VCO"),
    .PREDIV_MUXC4("VCO"),
    .REFCLK_DIV(2),
    .REFCLK_SEL("INTERNAL"),
    .STDBY_ENABLE("DISABLE"),
    .STDBY_VCO_ENA("DISABLE"),
    .SYNC_ENABLE("DISABLE"),
    .VCO_NORESET("DISABLE"))
    pll_inst (
    .daddr(6'b000000),
    .dclk(1'b0),
    .dcs(1'b0),
    .di(8'b00000000),
    .dwe(1'b0),
    .fbclk(clk0_out),
    .psclk(1'b0),
    .psclksel(3'b000),
    .psdown(1'b0),
    .psstep(1'b0),
    .refclk(refclk),
    .reset(reset),
    .stdby(1'b0),
    .clkc({open_n0,open_n1,open_n2,open_n3,clk0_buf}),
    .extlock(extlock));

endmodule