data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b7.v
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1: b'%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b7.v:52: Cannot find file containing module: \'jt74138\'\njt74138 u_13A(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74138\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74138.v\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74138.sv\n             jt74138\n             jt74138.v\n             jt74138.sv\n             obj_dir/jt74138\n             obj_dir/jt74138.v\n             obj_dir/jt74138.sv\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b7.v:67: Cannot find file containing module: \'jt74273\'\njt74273 u_12A(\n^~~~~~~\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b7.v:74: Cannot find file containing module: \'jt7474\'\njt7474 u_14A(\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b7.v:87: Operator XOR expects 8 bits on the RHS, but RHS\'s REPLICATE generates 7 bits.\n                                                                                 : ... In instance jt_gng_b7\n HF[6:0] = {8{FLIP}}^{H64,H32,H16,H8,H4,H2,H1};\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b7.v:87: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s XOR generates 8 bits.\n                                                                                 : ... In instance jt_gng_b7\n HF[6:0] = {8{FLIP}}^{H64,H32,H16,H8,H4,H2,H1};\n         ^\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b7.v:106: Cannot find file containing module: \'jt74138\'\njt74138 u_10C(\n^~~~~~~\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b7.v:128: Cannot find file containing module: \'jt7474\'\njt7474 u_7Ca(\n^~~~~~\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b7.v:136: Cannot find file containing module: \'jt7474\'\njt7474 u_7Cb(\n^~~~~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module jt_gng_b7(
	input	[7:0]	DB,
	input	[3:0]	AB,
	input			CBCS_b,
	input			G6M,
	input			FLIP,
	input			H256,
	input			H128,
	input			H64,
	input			H32,
	input			H16,
	input			H8,
	input			H4,
	input			H2,
	input			H1,
	output			SH2,
	output			SH8,
	output			SH16,
	output			SH32,
	output			SH64,
	output			SH128,
	output			SH256,
	input			SCRCS_b,
	output			MRDY2_b,
	output			SCREN_b,
	output			POS2,
	output			POS3,
	output	reg		S0H,
	output	reg		S2H,
	output	reg		S4H,
	output			FLIP_buf,
	output			S7H_b,
	output			S6M

);

wire [7:0] POS;
assign POS2=POS[2];
assign POS3=POS[3];

assign FLIP_buf = FLIP;
assign S6M = G6M;

jt74138 u_13A(
	.e1_b	( CBCS_b	),
	.e2_b	( CBCS_b	),
	.e3		( AB[3]		),
	.a		( AB[2:0]	),
	.y_b	( POS		)
);

wire [8:0] hscroll;
reg [7:0] DBdly;



always @(posedge H1) DBdly <= DB;

jt74273 u_12A(
	.d		( DBdly			),
	.q		( hscroll[7:0]	),
	.cl_b	( 1'b1			),
	.clk	( POS[0]		)
);

jt7474 u_14A(
	.d		( DBdly[0]		),
	.pr_b	( 1'b1			),
	.cl_b	( 1'b1			),
	.clk	( POS[1]		),
	.q		( hscroll[8]	)
);

reg [8:0] HF, SHx;
reg Haux;

always @(*) begin

	HF[6:0] = {8{FLIP}}^{H64,H32,H16,H8,H4,H2,H1};

	Haux  = ~FLIP ^ HF[6];

	HF[8] = ~H256;
	HF[7] = (~H256&~HF[6])^(FLIP&H128);

	SHx = hscroll + HF;
end

assign SH256 = SHx[8];
assign SH128 = SHx[7];
assign  SH64 = SHx[6];
assign  SH32 = SHx[5];
assign  SH16 = SHx[4];
assign   SH8 = SHx[3];

wire [7:0] SHdecod;

jt74138 u_10C(
	.e1_b	( 1'b0		),
	.e2_b	( 1'b0		),
	.e3		( 1'b1		),
	.a		( {3{FLIP}}^SHx[2:0]	),
	.y_b	( SHdecod	)
);

assign S7H_b = SHdecod[7];
reg clk_mrdy;

always @(posedge G6M) begin
	S0H 	 = ~SHdecod[7];
	clk_mrdy = ~SHdecod[5];
	S4H 	 = ~SHdecod[3];
	S2H 	 = ~SHdecod[1];
end

assign SH2 = SHx[1];

wire [1:0] mrdyq;

jt7474 u_7Ca(
	.d		( 1'b1 		),
	.pr_b	( 1'b1 		),
	.clk	( clk_mrdy	),
	.cl_b	( mrdyq[0]	),
	.q		( mrdyq[1]	)
);

jt7474 u_7Cb(
	.d		( 1'b1 		),
	.pr_b	( 1'b1 		),
	.clk	( S4H		),
	.cl_b	( ~S0H		),
	.q		( mrdyq[0]	)
);

assign MRDY2_b =  mrdyq[1] | SCRCS_b;
assign SCREN_b = ~mrdyq[0] | SCRCS_b;

endmodule
module jt_gng_b7(
	input	[7:0]	DB,
	input	[3:0]	AB,
	input			CBCS_b,
	input			G6M,
	input			FLIP,
	input			H256,
	input			H128,
	input			H64,
	input			H32,
	input			H16,
	input			H8,
	input			H4,
	input			H2,
	input			H1,
	output			SH2,
	output			SH8,
	output			SH16,
	output			SH32,
	output			SH64,
	output			SH128,
	output			SH256,
	input			SCRCS_b,
	output			MRDY2_b,
	output			SCREN_b,
	output			POS2,
	output			POS3,
	output	reg		S0H,
	output	reg		S2H,
	output	reg		S4H,
	output			FLIP_buf,
	output			S7H_b,
	output			S6M

);


wire [7:0] POS;
assign POS2=POS[2];
assign POS3=POS[3];

assign FLIP_buf = FLIP;
assign S6M = G6M;

jt74138 u_13A(
	.e1_b	( CBCS_b	),
	.e2_b	( CBCS_b	),
	.e3		( AB[3]		),
	.a		( AB[2:0]	),
	.y_b	( POS		)
);

wire [8:0] hscroll;
reg [7:0] DBdly;



always @(posedge H1) DBdly <= DB;

jt74273 u_12A(
	.d		( DBdly			),
	.q		( hscroll[7:0]	),
	.cl_b	( 1'b1			),
	.clk	( POS[0]		)
);

jt7474 u_14A(
	.d		( DBdly[0]		),
	.pr_b	( 1'b1			),
	.cl_b	( 1'b1			),
	.clk	( POS[1]		),
	.q		( hscroll[8]	)
);

reg [8:0] HF, SHx;
reg Haux;

always @(*) begin

	HF[6:0] = {8{FLIP}}^{H64,H32,H16,H8,H4,H2,H1};

	Haux  = ~FLIP ^ HF[6];

	HF[8] = ~H256;
	HF[7] = (~H256&~HF[6])^(FLIP&H128);

	SHx = hscroll + HF;
end

assign SH256 = SHx[8];
assign SH128 = SHx[7];
assign  SH64 = SHx[6];
assign  SH32 = SHx[5];
assign  SH16 = SHx[4];
assign   SH8 = SHx[3];

wire [7:0] SHdecod;

jt74138 u_10C(
	.e1_b	( 1'b0		),
	.e2_b	( 1'b0		),
	.e3		( 1'b1		),
	.a		( {3{FLIP}}^SHx[2:0]	),
	.y_b	( SHdecod	)
);

assign S7H_b = SHdecod[7];
reg clk_mrdy;

always @(posedge G6M) begin
	S0H 	 = ~SHdecod[7];
	clk_mrdy = ~SHdecod[5];
	S4H 	 = ~SHdecod[3];
	S2H 	 = ~SHdecod[1];
end

assign SH2 = SHx[1];

wire [1:0] mrdyq;

jt7474 u_7Ca(
	.d		( 1'b1 		),
	.pr_b	( 1'b1 		),
	.clk	( clk_mrdy	),
	.cl_b	( mrdyq[0]	),
	.q		( mrdyq[1]	)
);

jt7474 u_7Cb(
	.d		( 1'b1 		),
	.pr_b	( 1'b1 		),
	.clk	( S4H		),
	.cl_b	( ~S0H		),
	.q		( mrdyq[0]	)
);

assign MRDY2_b =  mrdyq[1] | SCRCS_b;
assign SCREN_b = ~mrdyq[0] | SCRCS_b;

endmodule