data/full_repos/permissive/143278/ivltests/pr273.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr273.v:38: Unsupported: Ignoring delay on this delayed statement.\n     #8;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr273.v:40: Unsupported: Ignoring delay on this delayed statement.\n     #8;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr273.v:48: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

reg clk;
reg [1:0] in0;
reg [1:0] in1;
reg sel0,sel1;
wire [1:0] q;

dff2 u1 (q,clk,in0[sel0],in1[sel1]);

initial
  begin
     clk = 0;
     in0 = 2'b0;
     in1 = 2'b0;
     sel0 = 1'b0;
     sel1 = 1'b1;
     #8;
     $display("initial val =%x",q);
     #8;
     if(q == 2'b0)
	     $display("PASSED");
     else
	     $display("FAILED");
     $finish ;
  end

always #5 clk = ~clk;

endmodule
module test;


reg clk;
reg [1:0] in0;
reg [1:0] in1;
reg sel0,sel1;
wire [1:0] q;

dff2 u1 (q,clk,in0[sel0],in1[sel1]);

initial
  begin
     clk = 0;
     in0 = 2'b0;
     in1 = 2'b0;
     sel0 = 1'b0;
     sel1 = 1'b1;
     #8;
     $display("initial val =%x",q);
     #8;
     if(q == 2'b0)
	     $display("PASSED");
     else
	     $display("FAILED");
     $finish ;
  end

always #5 clk = ~clk;

endmodule