data/full_repos/permissive/156609923/final/testbench.v
 line:176: before: "("
1: b'%Error: data/full_repos/permissive/156609923/final/testbench.v:2: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156609923/final,data/full_repos/permissive/156609923/cmos_cells.v\n             data/full_repos/permissive/156609923/final,data/full_repos/permissive/156609923/cmos_cells.v.v\n             data/full_repos/permissive/156609923/final,data/full_repos/permissive/156609923/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: data/full_repos/permissive/156609923/final/testbench.v:3: Cannot find include file: probador.v\n`include"probador.v" \n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156609923/final/testbench.v:4: Cannot find include file: PCIE_trans.v\n`include "PCIE_trans.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156609923/final/testbench.v:5: Cannot find include file: PCIE_Synth.v\n`include "PCIE_Synth.v" \n         ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module testbench #(
parameter ADDR_WIDTH = 3,
parameter BUS_SIZE = 5,
parameter MEM_LENGTH = 1 << ADDR_WIDTH);


   wire			clk;
   wire			continue_VC0P0;
   wire			continue_VC0P1;
   wire			continue_VC1P0;
   wire			continue_VC1P1;
   
   wire [BUS_SIZE:0]	data_p0;
   wire [BUS_SIZE:0]	data_p1;
   wire [4:0]		out_p0;
   wire [4:0]		out_p1;
   
wire			pause_VC0P0;
   wire			pause_VC0P1;
   wire			pause_VC1P0;
   wire			pause_VC1P1;

   wire			reset;
   wire [3:0]		umbralA;
   wire [3:0]		umbralB;
   wire			valid_p0;
   wire			valid_p1;

   wire			continue_VC0P0E;
   wire			continue_VC0P1E;
   wire			continue_VC1P0E;
   wire			continue_VC1P1E;
   wire [4:0] 		out_p0E;
   wire [4:0]		out_p1E;
   wire			pause_VC0P0E;
   wire			pause_VC0P1E;
   wire			pause_VC1P0E;
   wire			pause_VC1P1E;
  
   wire 		init,idle,error,active,idleE,errorE,activeE;
   wire [7:0] 		umbrales_VCFC,umbrales_VCFCE;
   
   

  
   probador probador1(

		      .clk		(clk),
		      .reset		(reset),
		      .data_p0		(data_p0),
		      .valid_p0		(valid_p0),
		      .data_p1		(data_p1),
		      .valid_p1		(valid_p1),
		      .umbralA		(umbralA),
		      .umbralB		(umbralB),
		      .init (init),

		      .out_p1		(out_p1[BUS_SIZE-1:0]),
		      .out_p0		(out_p0[BUS_SIZE-1:0]),
		      .continue_VC0P0	(continue_VC0P0),
		      .continue_VC1P0	(continue_VC1P0),
		      .continue_VC0P1	(continue_VC0P1),
		      .continue_VC1P1	(continue_VC1P1),
		      .pause_VC0P0	(pause_VC0P0),
		      .pause_VC1P0	(pause_VC1P0),
		      .pause_VC0P1	(pause_VC0P1),
		      .pause_VC1P1	(pause_VC1P1),
		      .active(active),
		      .error(error),
		      .idle(idle),
		      .umbrales_VCFC(umbrales_VCFC),

		      .out_p1E		(out_p1E[BUS_SIZE-1:0]),
		      .out_p0E		(out_p0E[BUS_SIZE-1:0]),
		      .continue_VC0P0E	(continue_VC0P0E),
		      .continue_VC1P0E	(continue_VC1P0E),
		      .continue_VC0P1E	(continue_VC0P1E),
		      .continue_VC1P1E	(continue_VC1P1E),
		      .pause_VC0P0E	(pause_VC0P0E),
		      .pause_VC1P0E	(pause_VC1P0E),
		      .pause_VC0P1E	(pause_VC0P1E),
		      .pause_VC1P1E	(pause_VC1P1E),
		      .activeE(activeE),
		      .errorE(errorE),
		      .idleE(idleE),
		      .umbrales_VCFCE(umbrales_VCFCE));
   
   PCIE_trans transac(

		      .out_p0		(out_p0[4:0]),
		      .out_p1		(out_p1[4:0]),
		      .pause_VC0P0	(pause_VC0P0),
		      .pause_VC1P0	(pause_VC1P0),
		      .pause_VC0P1	(pause_VC0P1),
		      .pause_VC1P1	(pause_VC1P1),
		      .continue_VC0P0	(continue_VC0P0),
		      .continue_VC1P0	(continue_VC1P0),
		      .continue_VC0P1	(continue_VC0P1),
		      .continue_VC1P1	(continue_VC1P1),
		      .active(active),
		      .error(error),
		      .idle(idle),
		      .umbrales_VCFC(umbrales_VCFC),

		      .clk		(clk),
		      .reset		(reset),
		      .valid_p0		(valid_p0),
		      .valid_p1		(valid_p1),
		      .data_p0		(data_p0[5:0]),
		      .data_p1		(data_p1[5:0]),
		      .umbralA		(umbralA[3:0]),
		      .umbralB		(umbralB[3:0]),
		      .init (init));

   PCIE_Synth transacSynth(

			   .continue_VC0P0	(continue_VC0P0E),
			   .continue_VC0P1	(continue_VC0P1E),
			   .continue_VC1P0	(continue_VC1P0E),
			   .continue_VC1P1	(continue_VC1P1E),
			   .out_p0		(out_p0E[4:0]),
			   .out_p1		(out_p1E[4:0]),
			   .pause_VC0P0		(pause_VC0P0E),
			   .pause_VC0P1		(pause_VC0P1E),
			   .pause_VC1P0		(pause_VC1P0E),
			   .pause_VC1P1		(pause_VC1P1E),
			   .active(activeE),
			   .error(errorE),
			   .idle(idleE),
			   .umbrales_VCFC(umbrales_VCFCE),

			   .clk			(clk),
			   .data_p0		(data_p0[5:0]),
			   .data_p1		(data_p1[5:0]),
			   .reset		(reset),
			   .umbralA		(umbralA[3:0]),
			   .umbralB		(umbralB[3:0]),
			   .valid_p0		(valid_p0),
			   .valid_p1		(valid_p1),
			   .init(init));
   


   endmodule
module testbench #(
parameter ADDR_WIDTH = 3,
parameter BUS_SIZE = 5,
parameter MEM_LENGTH = 1 << ADDR_WIDTH);



   wire			clk;
   wire			continue_VC0P0;
   wire			continue_VC0P1;
   wire			continue_VC1P0;
   wire			continue_VC1P1;
   
   wire [BUS_SIZE:0]	data_p0;
   wire [BUS_SIZE:0]	data_p1;
   wire [4:0]		out_p0;
   wire [4:0]		out_p1;
   
wire			pause_VC0P0;
   wire			pause_VC0P1;
   wire			pause_VC1P0;
   wire			pause_VC1P1;

   wire			reset;
   wire [3:0]		umbralA;
   wire [3:0]		umbralB;
   wire			valid_p0;
   wire			valid_p1;

   wire			continue_VC0P0E;
   wire			continue_VC0P1E;
   wire			continue_VC1P0E;
   wire			continue_VC1P1E;
   wire [4:0] 		out_p0E;
   wire [4:0]		out_p1E;
   wire			pause_VC0P0E;
   wire			pause_VC0P1E;
   wire			pause_VC1P0E;
   wire			pause_VC1P1E;
  
   wire 		init,idle,error,active,idleE,errorE,activeE;
   wire [7:0] 		umbrales_VCFC,umbrales_VCFCE;
   
   

  
   probador probador1(

		      .clk		(clk),
		      .reset		(reset),
		      .data_p0		(data_p0),
		      .valid_p0		(valid_p0),
		      .data_p1		(data_p1),
		      .valid_p1		(valid_p1),
		      .umbralA		(umbralA),
		      .umbralB		(umbralB),
		      .init (init),

		      .out_p1		(out_p1[BUS_SIZE-1:0]),
		      .out_p0		(out_p0[BUS_SIZE-1:0]),
		      .continue_VC0P0	(continue_VC0P0),
		      .continue_VC1P0	(continue_VC1P0),
		      .continue_VC0P1	(continue_VC0P1),
		      .continue_VC1P1	(continue_VC1P1),
		      .pause_VC0P0	(pause_VC0P0),
		      .pause_VC1P0	(pause_VC1P0),
		      .pause_VC0P1	(pause_VC0P1),
		      .pause_VC1P1	(pause_VC1P1),
		      .active(active),
		      .error(error),
		      .idle(idle),
		      .umbrales_VCFC(umbrales_VCFC),

		      .out_p1E		(out_p1E[BUS_SIZE-1:0]),
		      .out_p0E		(out_p0E[BUS_SIZE-1:0]),
		      .continue_VC0P0E	(continue_VC0P0E),
		      .continue_VC1P0E	(continue_VC1P0E),
		      .continue_VC0P1E	(continue_VC0P1E),
		      .continue_VC1P1E	(continue_VC1P1E),
		      .pause_VC0P0E	(pause_VC0P0E),
		      .pause_VC1P0E	(pause_VC1P0E),
		      .pause_VC0P1E	(pause_VC0P1E),
		      .pause_VC1P1E	(pause_VC1P1E),
		      .activeE(activeE),
		      .errorE(errorE),
		      .idleE(idleE),
		      .umbrales_VCFCE(umbrales_VCFCE));
   
   PCIE_trans transac(

		      .out_p0		(out_p0[4:0]),
		      .out_p1		(out_p1[4:0]),
		      .pause_VC0P0	(pause_VC0P0),
		      .pause_VC1P0	(pause_VC1P0),
		      .pause_VC0P1	(pause_VC0P1),
		      .pause_VC1P1	(pause_VC1P1),
		      .continue_VC0P0	(continue_VC0P0),
		      .continue_VC1P0	(continue_VC1P0),
		      .continue_VC0P1	(continue_VC0P1),
		      .continue_VC1P1	(continue_VC1P1),
		      .active(active),
		      .error(error),
		      .idle(idle),
		      .umbrales_VCFC(umbrales_VCFC),

		      .clk		(clk),
		      .reset		(reset),
		      .valid_p0		(valid_p0),
		      .valid_p1		(valid_p1),
		      .data_p0		(data_p0[5:0]),
		      .data_p1		(data_p1[5:0]),
		      .umbralA		(umbralA[3:0]),
		      .umbralB		(umbralB[3:0]),
		      .init (init));

   PCIE_Synth transacSynth(

			   .continue_VC0P0	(continue_VC0P0E),
			   .continue_VC0P1	(continue_VC0P1E),
			   .continue_VC1P0	(continue_VC1P0E),
			   .continue_VC1P1	(continue_VC1P1E),
			   .out_p0		(out_p0E[4:0]),
			   .out_p1		(out_p1E[4:0]),
			   .pause_VC0P0		(pause_VC0P0E),
			   .pause_VC0P1		(pause_VC0P1E),
			   .pause_VC1P0		(pause_VC1P0E),
			   .pause_VC1P1		(pause_VC1P1E),
			   .active(activeE),
			   .error(errorE),
			   .idle(idleE),
			   .umbrales_VCFC(umbrales_VCFCE),

			   .clk			(clk),
			   .data_p0		(data_p0[5:0]),
			   .data_p1		(data_p1[5:0]),
			   .reset		(reset),
			   .umbralA		(umbralA[3:0]),
			   .umbralB		(umbralB[3:0]),
			   .valid_p0		(valid_p0),
			   .valid_p1		(valid_p1),
			   .init(init));
   


   endmodule