data/full_repos/permissive/149848590/src/cpu/core/utility/PipelineDeliver.v
data/verilator_xmls/fb7381b6-bca8-49c9-af16-f148f165dd71.xml
module PipelineDeliver #(parameter width = 1) (
    input clk,
    input rst,
    input flush,
    input stall_current_stage,
    input stall_next_stage,
    input [width - 1:0] in,
    output reg[width - 1:0] out
);

    always @(posedge clk) begin
        if (!rst) begin
            out <= 0;
        end
        else if (flush) begin
            out <= 0;
        end
        else if (stall_current_stage && !stall_next_stage) begin
            out <= 0;
        end
        else if (!stall_current_stage) begin
            out <= in;
        end
    end

endmodule
module PipelineDeliver #(parameter width = 1) (
    input clk,
    input rst,
    input flush,
    input stall_current_stage,
    input stall_next_stage,
    input [width - 1:0] in,
    output reg[width - 1:0] out
);


    always @(posedge clk) begin
        if (!rst) begin
            out <= 0;
        end
        else if (flush) begin
            out <= 0;
        end
        else if (stall_current_stage && !stall_next_stage) begin
            out <= 0;
        end
        else if (!stall_current_stage) begin
            out <= in;
        end
    end

endmodule