data/full_repos/permissive/136684498/PC.v
data/verilator_xmls/05b65dbf-e7e7-441c-88fb-bfb368b9e5b1.xml
module PCUnit(in,PC,clk,sig,rst);
    output reg [31:0] PC;
    input [31:0] in;
    input clk;
    input sig;
    input rst;

    initial
    begin
        PC = 32'h0000_000;
    end
    always@(negedge clk or posedge rst)
	begin
        if (rst)
        begin
            PC = 32'h0000_000;
        end
		else if (sig)
            begin
                PC = in;
            end
    end
endmodule
module PCUnit(in,PC,clk,sig,rst);

    output reg [31:0] PC;
    input [31:0] in;
    input clk;
    input sig;
    input rst;

    initial
    begin
        PC = 32'h0000_000;
    end
    always@(negedge clk or posedge rst)
	begin
        if (rst)
        begin
            PC = 32'h0000_000;
        end
		else if (sig)
            begin
                PC = in;
            end
    end
endmodule