data/full_repos/permissive/217756734/Verilog2001/Full AES Design And Data Communication/inv_sub_byte.v
1: b'%Error: Cannot find file containing module: AES\n        ... Looked in:\n             data/full_repos/permissive/217756734/Verilog2001/Full/AES\n             data/full_repos/permissive/217756734/Verilog2001/Full/AES.v\n             data/full_repos/permissive/217756734/Verilog2001/Full/AES.sv\n             AES\n             AES.v\n             AES.sv\n             obj_dir/AES\n             obj_dir/AES.v\n             obj_dir/AES.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: And\n%Error: Cannot find file containing module: Data\n%Error: Cannot find file containing module: Communication,data/full_repos/permissive/217756734\n%Error: Cannot find file containing module: data/full_repos/permissive/217756734/Verilog2001/Full\n%Error: Cannot find file containing module: Communication/inv_sub_byte.v\n%Error: Exiting due to 7 error(s)\n'
module inv_sub_byte(
	input  [127:0] inputData,
	input  startTransition,
	output [127:0] outputData
);



genvar twoBytes;
generate for(twoBytes = 0; twoBytes < 128; twoBytes = twoBytes + 8) begin: subByte
	inv_s_box subValue(
		.inputValue	 (inputData[twoBytes +:8]),
		.outputValue (outputData[twoBytes +:8])
	);
end
endgenerate

endmodule
module inv_sub_byte(
	input  [127:0] inputData,
	input  startTransition,
	output [127:0] outputData
);




genvar twoBytes;
generate for(twoBytes = 0; twoBytes < 128; twoBytes = twoBytes + 8) begin: subByte
	inv_s_box subValue(
		.inputValue	 (inputData[twoBytes +:8]),
		.outputValue (outputData[twoBytes +:8])
	);
end
endgenerate

endmodule