data/full_repos/permissive/100638358/TRAB3_triangulo02.v
 line:69: before: "$"
1: b'%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:22: syntax error, unexpected inside, expecting \'[\'\n    output inside\n           ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:27: syntax error, unexpected assign\n    assign inside = (sign1 == 1 && sign2 == 1 && sign3 == 1) ? 1:0;\n    ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:38: syntax error, unexpected inside, expecting IDENTIFIER or do or final\n    wire inside;\n         ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:40: syntax error, unexpected inside, expecting \')\'\n    TestTriangle A(X1, Y1, X2, Y2, X3, Y3, X4, Y, inside);\n                                                  ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:44: Unsupported or unknown PLI call: $dumpvars\n           $dumpvars(0,A);\n           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:45: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:56: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:59: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:62: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:65: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:68: Unsupported: Ignoring delay on this delayed statement.\n           #40\n           ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n'
module TestTriangle (
    input [11:0] X1, Y1, X2, Y2, X3, Y3, X4, Y,
    output inside
);

    wire sign1, sign2, sign3;

    assign inside = (sign1 == 1 && sign2 == 1 && sign3 == 1) ? 1:0;

    sign out1(X1, Y1, X2, Y2, X4, Y, sign1);
    sign out2(X2, Y2, X3, Y3, X4, Y, sign2);
    sign out3(X3, Y3, X1, Y1, X4, Y, sign3);

endmodule
module TestTriangle (
    input [11:0] X1, Y1, X2, Y2, X3, Y3, X4, Y,
    output inside
);


    wire sign1, sign2, sign3;

    assign inside = (sign1 == 1 && sign2 == 1 && sign3 == 1) ? 1:0;

    sign out1(X1, Y1, X2, Y2, X4, Y, sign1);
    sign out2(X2, Y2, X3, Y3, X4, Y, sign2);
    sign out3(X3, Y3, X1, Y1, X4, Y, sign3);

endmodule