data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_performance_counters_tb.v
 line:46: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_performance_counters_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  always #125 clk = ~clk;   \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_performance_counters_tb.v:46: syntax error, unexpected \'@\'\n    repeat (1000) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_performance_counters_tb.v:85: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_performance_counters_tb.v:91: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_performance_counters_tb.v:94: syntax error, unexpected \'@\'\n      repeat (100) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_performance_counters_tb.v:97: syntax error, unexpected \'@\'\n    repeat (10000) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_performance_counters_tb.v:105: syntax error, unexpected \'@\'\n      @(oled_bfm_i.r_fc >= 100);\n      ^\n%Error: Exiting due to 6 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module oled_performance_counters_tb;
  parameter
    C_COLS	= 128,
    C_ROWS	= 32,
    C_COUNTER_N = 64,
    C_COUNTER_W = 6;


  reg clk;
  initial clk = 0;
  always #125 clk = ~clk;

  integer delay = 400000;

  always @(posedge clk) begin
    if (delay > 0)	delay = delay - 1;
    else begin
      delay = 400000;
      $display("--- PROGRESS: 100ms ---");
    end
  end


  reg rst_n;
  initial begin
    rst_n = 0;
    repeat (1000) @(posedge clk);
    rst_n = 1;
    $display("--- RESET PHASE FINISHED ---");
  end


  reg [C_COUNTER_N - 1:0] r_intr;


  wire sclk, sdc, sdin;
  oled_performance_counters #(
    .C_COUNTER_N (C_COUNTER_N),
    .C_COUNTER_W (C_COUNTER_W),
    .C_COLS (C_COLS >> 1),
    .C_ROWS (C_ROWS)
  ) pc_i (
    .clk ( clk ),
    .rst_n ( rst_n ),
    .intr ( r_intr ),
    .ready ( rst_n ),
    .oled_sclk ( sclk ),
    .oled_dc ( sdc ),
    .oled_sdin ( sdin )
  );

  oled_bfm #(
    .C_COLS (C_COLS),
    .C_ROWS (C_ROWS)
  ) oled_bfm_i (
    .clk ( sclk ),
    .rst_n ( rst_n ),
    .sclk ( sclk ),
    .sdc ( sdc ),
    .sdin ( sdin )
  );

  integer i;

  initial begin
    @(posedge rst_n);


    repeat (1 << C_COUNTER_W) begin
      r_intr <= {63'b0, 1'b1};
      repeat (C_COUNTER_N) begin
        repeat (100) @(posedge clk);
        r_intr <= r_intr << 1;
      end
      repeat (100) @(posedge clk);
    end

    repeat (10000) @(posedge clk);
    for (i = 0; i < C_COUNTER_N; i = i + 1) begin
      show_pc_value(i);
      if (|pc_i.r_pc[i]) $stop;
    end

    $display("\nFINISHED - TEST PASSED");
    if (oled_bfm_i.r_fc < 100)
      @(oled_bfm_i.r_fc >= 100);
    $finish;
  end

  task automatic show_pc_value;
    input integer i;
    begin
      if (pc_i.r_pc[i] == 'h0)
        $display("r_pc[%d] = %b (%d) \tVALUE OK!", i,
          pc_i.r_pc[i],
          pc_i.r_pc[i]);
      else
        $display("r_pc[%d] = %b (%d) \tERROR!", i,
          pc_i.r_pc[i],
          pc_i.r_pc[i]);
    end
  endtask
endmodule
module oled_performance_counters_tb;

  parameter
    C_COLS	= 128,
    C_ROWS	= 32,
    C_COUNTER_N = 64,
    C_COUNTER_W = 6;


  reg clk;
  initial clk = 0;
  always #125 clk = ~clk;

  integer delay = 400000;

  always @(posedge clk) begin
    if (delay > 0)	delay = delay - 1;
    else begin
      delay = 400000;
      $display("--- PROGRESS: 100ms ---");
    end
  end


  reg rst_n;
  initial begin
    rst_n = 0;
    repeat (1000) @(posedge clk);
    rst_n = 1;
    $display("--- RESET PHASE FINISHED ---");
  end


  reg [C_COUNTER_N - 1:0] r_intr;


  wire sclk, sdc, sdin;
  oled_performance_counters #(
    .C_COUNTER_N (C_COUNTER_N),
    .C_COUNTER_W (C_COUNTER_W),
    .C_COLS (C_COLS >> 1),
    .C_ROWS (C_ROWS)
  ) pc_i (
    .clk ( clk ),
    .rst_n ( rst_n ),
    .intr ( r_intr ),
    .ready ( rst_n ),
    .oled_sclk ( sclk ),
    .oled_dc ( sdc ),
    .oled_sdin ( sdin )
  );

  oled_bfm #(
    .C_COLS (C_COLS),
    .C_ROWS (C_ROWS)
  ) oled_bfm_i (
    .clk ( sclk ),
    .rst_n ( rst_n ),
    .sclk ( sclk ),
    .sdc ( sdc ),
    .sdin ( sdin )
  );

  integer i;

  initial begin
    @(posedge rst_n);


    repeat (1 << C_COUNTER_W) begin
      r_intr <= {63'b0, 1'b1};
      repeat (C_COUNTER_N) begin
        repeat (100) @(posedge clk);
        r_intr <= r_intr << 1;
      end
      repeat (100) @(posedge clk);
    end

    repeat (10000) @(posedge clk);
    for (i = 0; i < C_COUNTER_N; i = i + 1) begin
      show_pc_value(i);
      if (|pc_i.r_pc[i]) $stop;
    end

    $display("\nFINISHED - TEST PASSED");
    if (oled_bfm_i.r_fc < 100)
      @(oled_bfm_i.r_fc >= 100);
    $finish;
  end

  task automatic show_pc_value;
    input integer i;
    begin
      if (pc_i.r_pc[i] == 'h0)
        $display("r_pc[%d] = %b (%d) \tVALUE OK!", i,
          pc_i.r_pc[i],
          pc_i.r_pc[i]);
      else
        $display("r_pc[%d] = %b (%d) \tERROR!", i,
          pc_i.r_pc[i],
          pc_i.r_pc[i]);
    end
  endtask
endmodule