data/full_repos/permissive/106408053/verilog/serial_receiver.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/serial_receiver.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/serial_receiver.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/serial_receiver.v:127: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'rx_count\' generates 10 bits.\n                                                                                  : ... In instance serial_receiver\n        if (rx_count == BITLENGTH/2 - 1) begin\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/serial_receiver.v:138: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'rx_count\' generates 10 bits.\n                                                                                  : ... In instance serial_receiver\n      if (rx_count == BITLENGTH - 1) begin\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/serial_receiver.v:148: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'rx_count\' generates 10 bits.\n                                                                                  : ... In instance serial_receiver\n      if (rx_count == BITLENGTH - 1) begin\n                   ^~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module serial_receiver(
  clock, extReset, 
  rx, transmitting,

  op, data, execute);

parameter [31:0] FREQ = 100000000;
parameter [31:0] RATE = 115200;

input clock;
input extReset;
input rx;
input transmitting;
output [7:0] op;
output [31:0] data;
output execute;

parameter 
  READOPCODE = 1'h0,
  READLONG = 1'h1;

parameter [1:0]
  RX_IDLE = 2'h0,
  RX_START = 2'h1,
  RX_RECEIVE = 2'h2,
  RX_STOP = 2'h3;

parameter BITLENGTH = FREQ / RATE;

reg state, next_state;
reg [1:0] bytecount, next_bytecount;
reg [7:0] opcode, next_opcode;
reg [31:0] databuf, next_databuf;
reg execute, next_execute;

reg [1:0] rx_state, next_rx_state;
reg [9:0] rx_count, next_rx_count;
reg [2:0] bitcount, next_bitcount;
reg [7:0] rxByte, next_rxByte;
reg byteready, next_byteready;

assign op = opcode;
assign data = databuf;





always @(posedge clock or posedge extReset) 
begin
  if (extReset) begin
    rx_state = RX_IDLE;
    bitcount = 3'b0;
    rxByte = 8'b0;
    byteready = 1'b0;
    rx_count = 10'd0;
  end else begin 
    rx_state = next_rx_state;
    bitcount = next_bitcount;
    rxByte = next_rxByte;
    byteready = next_byteready;
    rx_count = next_rx_count;
  end
end

always @*
begin
  #1;
  next_rx_state = rx_state;
  next_bitcount = bitcount;
  next_rxByte = rxByte;
  next_byteready = 1'b0;
  next_rx_count = 0;

  case(rx_state)
    RX_IDLE: begin
      if (!rx & !transmitting) begin
        next_rx_state = RX_START;
      end
    end
    RX_START: begin
      if (!rx) begin
        next_rx_count = rx_count + 1'b1;
        if (rx_count == BITLENGTH/2 - 1) begin
          next_rx_state = RX_RECEIVE;
          next_rx_count = 0;
          next_rxByte = 8'b0;
        end
      end else begin
        next_rx_state = RX_IDLE;
      end
    end
    RX_RECEIVE: begin
      next_rx_count = rx_count + 1'b1;
      if (rx_count == BITLENGTH - 1) begin
        next_rx_count = 0;
        next_bitcount = bitcount + 1'b1;
        next_rxByte = {rx, rxByte[7:1]};
        if (bitcount == 3'd7)
          next_rx_state = RX_STOP;
      end
    end
    RX_STOP: begin
      next_rx_count = rx_count + 1'b1;
      if (rx_count == BITLENGTH - 1) begin
        next_rx_count = 0;
        next_byteready = 1'b1;
        next_rx_state = RX_IDLE;
      end
    end
  endcase
end




always @(posedge clock or posedge extReset) 
begin
  if (extReset)
    state = READOPCODE;
  else state = next_state;
end

initial databuf = 0;
always @(posedge clock) 
begin
  bytecount = next_bytecount;
  opcode = next_opcode;
  databuf = next_databuf;
  execute = next_execute;
end

always @*
begin
  #1;
  next_state = state;
  next_bytecount = bytecount;
  next_opcode = opcode;
  next_databuf = databuf;
  next_execute = 1'b0;
  
  case (state)
    READOPCODE :
      begin
        next_bytecount = 0;
        if (byteready)
          begin
            next_opcode = rxByte;
            if (rxByte[7])
              next_state = READLONG;
            else
              begin
                next_execute = 1'b1;
                  next_state = READOPCODE;
              end
          end
      end

    READLONG :
      begin
        if (byteready)
          begin
            next_bytecount = bytecount + 1'b1;
            next_databuf = {rxByte,databuf[31:8]};
            if (&bytecount)
              begin
                next_execute = 1'b1;
                  next_state = READOPCODE;
              end
          end
      end
  endcase
end
endmodule
module serial_receiver(
  clock, extReset, 
  rx, transmitting,

  op, data, execute);


parameter [31:0] FREQ = 100000000;
parameter [31:0] RATE = 115200;

input clock;
input extReset;
input rx;
input transmitting;
output [7:0] op;
output [31:0] data;
output execute;

parameter 
  READOPCODE = 1'h0,
  READLONG = 1'h1;

parameter [1:0]
  RX_IDLE = 2'h0,
  RX_START = 2'h1,
  RX_RECEIVE = 2'h2,
  RX_STOP = 2'h3;

parameter BITLENGTH = FREQ / RATE;

reg state, next_state;
reg [1:0] bytecount, next_bytecount;
reg [7:0] opcode, next_opcode;
reg [31:0] databuf, next_databuf;
reg execute, next_execute;

reg [1:0] rx_state, next_rx_state;
reg [9:0] rx_count, next_rx_count;
reg [2:0] bitcount, next_bitcount;
reg [7:0] rxByte, next_rxByte;
reg byteready, next_byteready;

assign op = opcode;
assign data = databuf;





always @(posedge clock or posedge extReset) 
begin
  if (extReset) begin
    rx_state = RX_IDLE;
    bitcount = 3'b0;
    rxByte = 8'b0;
    byteready = 1'b0;
    rx_count = 10'd0;
  end else begin 
    rx_state = next_rx_state;
    bitcount = next_bitcount;
    rxByte = next_rxByte;
    byteready = next_byteready;
    rx_count = next_rx_count;
  end
end

always @*
begin
  #1;
  next_rx_state = rx_state;
  next_bitcount = bitcount;
  next_rxByte = rxByte;
  next_byteready = 1'b0;
  next_rx_count = 0;

  case(rx_state)
    RX_IDLE: begin
      if (!rx & !transmitting) begin
        next_rx_state = RX_START;
      end
    end
    RX_START: begin
      if (!rx) begin
        next_rx_count = rx_count + 1'b1;
        if (rx_count == BITLENGTH/2 - 1) begin
          next_rx_state = RX_RECEIVE;
          next_rx_count = 0;
          next_rxByte = 8'b0;
        end
      end else begin
        next_rx_state = RX_IDLE;
      end
    end
    RX_RECEIVE: begin
      next_rx_count = rx_count + 1'b1;
      if (rx_count == BITLENGTH - 1) begin
        next_rx_count = 0;
        next_bitcount = bitcount + 1'b1;
        next_rxByte = {rx, rxByte[7:1]};
        if (bitcount == 3'd7)
          next_rx_state = RX_STOP;
      end
    end
    RX_STOP: begin
      next_rx_count = rx_count + 1'b1;
      if (rx_count == BITLENGTH - 1) begin
        next_rx_count = 0;
        next_byteready = 1'b1;
        next_rx_state = RX_IDLE;
      end
    end
  endcase
end




always @(posedge clock or posedge extReset) 
begin
  if (extReset)
    state = READOPCODE;
  else state = next_state;
end

initial databuf = 0;
always @(posedge clock) 
begin
  bytecount = next_bytecount;
  opcode = next_opcode;
  databuf = next_databuf;
  execute = next_execute;
end

always @*
begin
  #1;
  next_state = state;
  next_bytecount = bytecount;
  next_opcode = opcode;
  next_databuf = databuf;
  next_execute = 1'b0;
  
  case (state)
    READOPCODE :
      begin
        next_bytecount = 0;
        if (byteready)
          begin
            next_opcode = rxByte;
            if (rxByte[7])
              next_state = READLONG;
            else
              begin
                next_execute = 1'b1;
                  next_state = READOPCODE;
              end
          end
      end

    READLONG :
      begin
        if (byteready)
          begin
            next_bytecount = bytecount + 1'b1;
            next_databuf = {rxByte,databuf[31:8]};
            if (&bytecount)
              begin
                next_execute = 1'b1;
                  next_state = READOPCODE;
              end
          end
      end
  endcase
end
endmodule