data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v:1: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: Exiting due to 1 error(s)\n'
module mux_p2s_synth(sel, data_in, data_out);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire _17_;
  wire _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  wire _22_;
  input [7:0] data_in;
  output data_out;
  input [2:0] sel;
  NAND _23_ (
    .A(data_in[7]),
    .B(sel[2]),
    .Y(_00_)
  );
  NOT _24_ (
    .A(sel[2]),
    .Y(_01_)
  );
  NAND _25_ (
    .A(data_in[3]),
    .B(_01_),
    .Y(_02_)
  );
  NAND _26_ (
    .A(_02_),
    .B(_00_),
    .Y(_03_)
  );
  NAND _27_ (
    .A(_03_),
    .B(sel[0]),
    .Y(_04_)
  );
  NOT _28_ (
    .A(sel[0]),
    .Y(_05_)
  );
  NOR _29_ (
    .A(data_in[2]),
    .B(sel[2]),
    .Y(_06_)
  );
  NOR _30_ (
    .A(data_in[6]),
    .B(_01_),
    .Y(_07_)
  );
  NOR _31_ (
    .A(_07_),
    .B(_06_),
    .Y(_08_)
  );
  NAND _32_ (
    .A(_08_),
    .B(_05_),
    .Y(_09_)
  );
  NAND _33_ (
    .A(_09_),
    .B(_04_),
    .Y(_10_)
  );
  NAND _34_ (
    .A(_10_),
    .B(sel[1]),
    .Y(_11_)
  );
  NOT _35_ (
    .A(sel[1]),
    .Y(_12_)
  );
  NAND _36_ (
    .A(data_in[1]),
    .B(_01_),
    .Y(_13_)
  );
  NAND _37_ (
    .A(data_in[5]),
    .B(sel[2]),
    .Y(_14_)
  );
  NAND _38_ (
    .A(_14_),
    .B(_13_),
    .Y(_15_)
  );
  NAND _39_ (
    .A(_15_),
    .B(sel[0]),
    .Y(_16_)
  );
  NOR _40_ (
    .A(data_in[0]),
    .B(sel[2]),
    .Y(_17_)
  );
  NOR _41_ (
    .A(data_in[4]),
    .B(_01_),
    .Y(_18_)
  );
  NOR _42_ (
    .A(_18_),
    .B(_17_),
    .Y(_19_)
  );
  NAND _43_ (
    .A(_19_),
    .B(_05_),
    .Y(_20_)
  );
  NAND _44_ (
    .A(_20_),
    .B(_16_),
    .Y(_21_)
  );
  NAND _45_ (
    .A(_21_),
    .B(_12_),
    .Y(_22_)
  );
  NAND _46_ (
    .A(_22_),
    .B(_11_),
    .Y(data_out)
  );
endmodule
module mux_p2s_synth(sel, data_in, data_out);

  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire _17_;
  wire _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  wire _22_;
  input [7:0] data_in;
  output data_out;
  input [2:0] sel;
  NAND _23_ (
    .A(data_in[7]),
    .B(sel[2]),
    .Y(_00_)
  );
  NOT _24_ (
    .A(sel[2]),
    .Y(_01_)
  );
  NAND _25_ (
    .A(data_in[3]),
    .B(_01_),
    .Y(_02_)
  );
  NAND _26_ (
    .A(_02_),
    .B(_00_),
    .Y(_03_)
  );
  NAND _27_ (
    .A(_03_),
    .B(sel[0]),
    .Y(_04_)
  );
  NOT _28_ (
    .A(sel[0]),
    .Y(_05_)
  );
  NOR _29_ (
    .A(data_in[2]),
    .B(sel[2]),
    .Y(_06_)
  );
  NOR _30_ (
    .A(data_in[6]),
    .B(_01_),
    .Y(_07_)
  );
  NOR _31_ (
    .A(_07_),
    .B(_06_),
    .Y(_08_)
  );
  NAND _32_ (
    .A(_08_),
    .B(_05_),
    .Y(_09_)
  );
  NAND _33_ (
    .A(_09_),
    .B(_04_),
    .Y(_10_)
  );
  NAND _34_ (
    .A(_10_),
    .B(sel[1]),
    .Y(_11_)
  );
  NOT _35_ (
    .A(sel[1]),
    .Y(_12_)
  );
  NAND _36_ (
    .A(data_in[1]),
    .B(_01_),
    .Y(_13_)
  );
  NAND _37_ (
    .A(data_in[5]),
    .B(sel[2]),
    .Y(_14_)
  );
  NAND _38_ (
    .A(_14_),
    .B(_13_),
    .Y(_15_)
  );
  NAND _39_ (
    .A(_15_),
    .B(sel[0]),
    .Y(_16_)
  );
  NOR _40_ (
    .A(data_in[0]),
    .B(sel[2]),
    .Y(_17_)
  );
  NOR _41_ (
    .A(data_in[4]),
    .B(_01_),
    .Y(_18_)
  );
  NOR _42_ (
    .A(_18_),
    .B(_17_),
    .Y(_19_)
  );
  NAND _43_ (
    .A(_19_),
    .B(_05_),
    .Y(_20_)
  );
  NAND _44_ (
    .A(_20_),
    .B(_16_),
    .Y(_21_)
  );
  NAND _45_ (
    .A(_21_),
    .B(_12_),
    .Y(_22_)
  );
  NAND _46_ (
    .A(_22_),
    .B(_11_),
    .Y(data_out)
  );
endmodule