data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design/counter.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design/counter.v:42: Cannot find file containing module: 'd_trig'\n                d_trig #(\n                ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design,data/full_repos/permissive/110143902/d_trig\n             data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design,data/full_repos/permissive/110143902/d_trig.v\n             data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design,data/full_repos/permissive/110143902/d_trig.sv\n             d_trig\n             d_trig.v\n             d_trig.sv\n             obj_dir/d_trig\n             obj_dir/d_trig.v\n             obj_dir/d_trig.sv\n%Error: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design/counter.v:54: Cannot find file containing module: 'd_trig'\n                 d_trig #(\n                 ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module counter (
    DCLR, C, CLR,
    Q, notQ,
    overflow
    );


    parameter                          DATA_WIDTH = 4;
    parameter                          CLEAR_VAL  = 1;


    input wire [DATA_WIDTH - 1 : 0] DCLR;
    input wire C, CLR;
    output wire [DATA_WIDTH - 1 : 0] Q, notQ;
    output reg overflow;


    wire [DATA_WIDTH - 1 : 0] d_trig_Q, d_trig_notQ;
    reg  [DATA_WIDTH - 1 : 0] d_trig_Q_neg;
    genvar i;
    integer j;



    generate
        for(i = 0; i < DATA_WIDTH; i = i + 1) begin
            if(i == 0) begin
                d_trig #(
                    .CLEAR_VAL(CLEAR_VAL)
                ) d_trig_0 (
                    .D(d_trig_Q[0]),
                    .DCLR(DCLR[0]),
                    .C(C),
                    .CLR(CLR),
                    .Q(d_trig_notQ[0]),
                    .notQ(d_trig_Q[0])
                );
            end
            else begin
                 d_trig #(
                    .CLEAR_VAL(CLEAR_VAL)
                ) d_trig_i (
                    .D(d_trig_Q[i]),
                    .DCLR(DCLR[i]),
                    .C(d_trig_Q[i - 1]),
                    .CLR(CLR),
                    .Q(d_trig_notQ[i]),
                    .notQ(d_trig_Q[i])
                );
            end
        end
    endgenerate

    generate
        for(i = 0; i < DATA_WIDTH; i = i + 1) begin
            assign Q[i]    = d_trig_notQ[i];
            assign notQ[i] = d_trig_Q[i];
        end
    endgenerate

    generate
        for(i = 0; i < DATA_WIDTH; i = i + 1) begin
            always @(d_trig_Q[i]) begin
                if(d_trig_Q[i])
                    d_trig_Q_neg[i] <= 1;
                else
                    d_trig_Q_neg[i] <= 0;
            end
        end
    endgenerate

    always @* begin
        overflow = 1'b1;
        for(j = 0; j < DATA_WIDTH; j = j + 1)
            overflow = overflow & d_trig_Q_neg[j];
    end

endmodule
module counter (
    DCLR, C, CLR,
    Q, notQ,
    overflow
    );



    parameter                          DATA_WIDTH = 4;
    parameter                          CLEAR_VAL  = 1;


    input wire [DATA_WIDTH - 1 : 0] DCLR;
    input wire C, CLR;
    output wire [DATA_WIDTH - 1 : 0] Q, notQ;
    output reg overflow;


    wire [DATA_WIDTH - 1 : 0] d_trig_Q, d_trig_notQ;
    reg  [DATA_WIDTH - 1 : 0] d_trig_Q_neg;
    genvar i;
    integer j;



    generate
        for(i = 0; i < DATA_WIDTH; i = i + 1) begin
            if(i == 0) begin
                d_trig #(
                    .CLEAR_VAL(CLEAR_VAL)
                ) d_trig_0 (
                    .D(d_trig_Q[0]),
                    .DCLR(DCLR[0]),
                    .C(C),
                    .CLR(CLR),
                    .Q(d_trig_notQ[0]),
                    .notQ(d_trig_Q[0])
                );
            end
            else begin
                 d_trig #(
                    .CLEAR_VAL(CLEAR_VAL)
                ) d_trig_i (
                    .D(d_trig_Q[i]),
                    .DCLR(DCLR[i]),
                    .C(d_trig_Q[i - 1]),
                    .CLR(CLR),
                    .Q(d_trig_notQ[i]),
                    .notQ(d_trig_Q[i])
                );
            end
        end
    endgenerate

    generate
        for(i = 0; i < DATA_WIDTH; i = i + 1) begin
            assign Q[i]    = d_trig_notQ[i];
            assign notQ[i] = d_trig_Q[i];
        end
    endgenerate

    generate
        for(i = 0; i < DATA_WIDTH; i = i + 1) begin
            always @(d_trig_Q[i]) begin
                if(d_trig_Q[i])
                    d_trig_Q_neg[i] <= 1;
                else
                    d_trig_Q_neg[i] <= 0;
            end
        end
    endgenerate

    always @* begin
        overflow = 1'b1;
        for(j = 0; j < DATA_WIDTH; j = j + 1)
            overflow = overflow & d_trig_Q_neg[j];
    end

endmodule