data/full_repos/permissive/148324174/CombLogic/SR.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/148324174/CombLogic/SR.v:6: Signal definition not found, creating implicitly: \'q\'\nassign #1 Q = q;\n              ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/148324174/CombLogic/SR.v:7: Signal definition not found, creating implicitly: \'qn\'\n                                                                        : ... Suggested alternative: \'Qn\'\nassign #1 Qn = qn;\n               ^~\n%Error: Exiting due to 2 warning(s)\n'
module SR(
	output Q, Qn,
	input S, R
	);

assign #1 Q = q;
assign #1 Qn = qn;

assign #10 q = ~(S&qn);
assign #10 qn = ~(R&q);

endmodule
module SR(
	output Q, Qn,
	input S, R
	);


assign #1 Q = q;
assign #1 Qn = qn;

assign #10 q = ~(S&qn);
assign #10 qn = ~(R&q);

endmodule