data/full_repos/permissive/165873996/src/modified/myvgasync.v
1: b'%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/myvgasync.v:55: Operator COND expects 32 or 10 bits on the Conditional True, but Conditional True\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance myvgasync\n  h_count_next = (reset || h_count_reg == H_MAX) ? 9\'b0 : h_count_reg + 1;\n                                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/myvgasync.v:58: Operator COND expects 32 or 10 bits on the Conditional True, but Conditional True\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance myvgasync\n                 (v_count_reg == V_MAX ? 9\'b0 : v_count_reg + 1) \n                                       ^\n%Error: Exiting due to 2 warning(s)\n'
module myvgasync

	(
		input wire clk,
		input wire reset,
		output wire hsync, vsync, video_on,
		output wire [9:0] x, y
	);
	

	localparam H_DISPLAY       = 640;
	localparam H_L_BORDER      =  48;
	localparam H_R_BORDER      =  16;
	localparam H_RETRACE       =  96;
	localparam H_MAX           = H_DISPLAY + H_L_BORDER + H_R_BORDER + H_RETRACE - 1;
	localparam START_H_RETRACE = H_DISPLAY + H_R_BORDER;
	localparam END_H_RETRACE   = H_DISPLAY + H_R_BORDER + H_RETRACE - 1;
	
	localparam V_DISPLAY       = 480;
	localparam V_T_BORDER      =  10;
	localparam V_B_BORDER      =  33;
	localparam V_RETRACE       =   2;
	localparam V_MAX           = V_DISPLAY + V_T_BORDER + V_B_BORDER + V_RETRACE - 1;
        localparam START_V_RETRACE = V_DISPLAY + V_B_BORDER;
	localparam END_V_RETRACE   = V_DISPLAY + V_B_BORDER + V_RETRACE - 1;
	

	reg [9:0] h_count_reg, h_count_next, v_count_reg, v_count_next;
	

	reg vsync_reg, hsync_reg;
	wire vsync_next, hsync_next;
	wire pixel_tick;
 

	always @(posedge clk, posedge reset)
		if(reset)
			begin
           		v_count_reg <= 0;
            		h_count_reg <= 0;
            		vsync_reg   <= 0;
            		hsync_reg   <= 0;
			end
		else
			begin
            		v_count_reg <= v_count_next;
            		h_count_reg <= h_count_next;
            		vsync_reg   <= vsync_next;
            		hsync_reg   <= hsync_next;
			end
			

	always @*
		begin
		h_count_next = (reset || h_count_reg == H_MAX) ? 9'b0 : h_count_reg + 1;
		
		v_count_next = (reset || h_count_reg == H_MAX) ? 
		               (v_count_reg == V_MAX ? 9'b0 : v_count_reg + 1) 
			       : v_count_reg;
		end
		


   assign hsync_next = h_count_reg >= START_H_RETRACE && h_count_reg <= END_H_RETRACE;
   

   assign vsync_next = v_count_reg >= START_V_RETRACE && v_count_reg <= END_V_RETRACE;


   assign video_on = !reset && (h_count_reg < H_DISPLAY) && (v_count_reg < V_DISPLAY);


   assign hsync  = ~hsync_reg;
   assign vsync  = ~vsync_reg;
   assign x      = h_count_reg;
   assign y      = v_count_reg;
endmodule
module myvgasync

	(
		input wire clk,
		input wire reset,
		output wire hsync, vsync, video_on,
		output wire [9:0] x, y
	);

	

	localparam H_DISPLAY       = 640;
	localparam H_L_BORDER      =  48;
	localparam H_R_BORDER      =  16;
	localparam H_RETRACE       =  96;
	localparam H_MAX           = H_DISPLAY + H_L_BORDER + H_R_BORDER + H_RETRACE - 1;
	localparam START_H_RETRACE = H_DISPLAY + H_R_BORDER;
	localparam END_H_RETRACE   = H_DISPLAY + H_R_BORDER + H_RETRACE - 1;
	
	localparam V_DISPLAY       = 480;
	localparam V_T_BORDER      =  10;
	localparam V_B_BORDER      =  33;
	localparam V_RETRACE       =   2;
	localparam V_MAX           = V_DISPLAY + V_T_BORDER + V_B_BORDER + V_RETRACE - 1;
        localparam START_V_RETRACE = V_DISPLAY + V_B_BORDER;
	localparam END_V_RETRACE   = V_DISPLAY + V_B_BORDER + V_RETRACE - 1;
	

	reg [9:0] h_count_reg, h_count_next, v_count_reg, v_count_next;
	

	reg vsync_reg, hsync_reg;
	wire vsync_next, hsync_next;
	wire pixel_tick;
 

	always @(posedge clk, posedge reset)
		if(reset)
			begin
           		v_count_reg <= 0;
            		h_count_reg <= 0;
            		vsync_reg   <= 0;
            		hsync_reg   <= 0;
			end
		else
			begin
            		v_count_reg <= v_count_next;
            		h_count_reg <= h_count_next;
            		vsync_reg   <= vsync_next;
            		hsync_reg   <= hsync_next;
			end
			

	always @*
		begin
		h_count_next = (reset || h_count_reg == H_MAX) ? 9'b0 : h_count_reg + 1;
		
		v_count_next = (reset || h_count_reg == H_MAX) ? 
		               (v_count_reg == V_MAX ? 9'b0 : v_count_reg + 1) 
			       : v_count_reg;
		end
		


   assign hsync_next = h_count_reg >= START_H_RETRACE && h_count_reg <= END_H_RETRACE;
   

   assign vsync_next = v_count_reg >= START_V_RETRACE && v_count_reg <= END_V_RETRACE;


   assign video_on = !reset && (h_count_reg < H_DISPLAY) && (v_count_reg < V_DISPLAY);


   assign hsync  = ~hsync_reg;
   assign vsync  = ~vsync_reg;
   assign x      = h_count_reg;
   assign y      = v_count_reg;
endmodule