data/full_repos/permissive/130234582/demo_002/CLK_DIV_2.v
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data/verilator_xmls/88c31448-727a-40bf-a47e-97149fd98523.xml
module CLK_DIV_2
(



    input           clk,
    input           rst_n,


    output reg      clk_o
);





always @(posedge clk or negedge rst_n) 
    if(~rst_n)

        clk_o <= 0;
    else
        clk_o <= ~clk_o;
    
endmodule
module CLK_DIV_2
(



    input           clk,
    input           rst_n,


    output reg      clk_o
);






always @(posedge clk or negedge rst_n) 
    if(~rst_n)

        clk_o <= 0;
    else
        clk_o <= ~clk_o;
    
endmodule