data/full_repos/permissive/19818566/software/host/davester_combinational_extractor/tb_test_citcuit.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/19818566/software/host/davester_combinational_extractor/tb_test_citcuit.v:7: Unsupported: Ignoring delay on this delayed statement.\n   always #300 clk = !clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/19818566/software/host/davester_combinational_extractor/tb_test_citcuit.v:20: Unsupported or unknown PLI call: $sdf_annotate\n      $sdf_annotate("mydesign.sdf",DUT,,,"MAXIMUM");\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19818566/software/host/davester_combinational_extractor/tb_test_citcuit.v:20: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      $sdf_annotate("mydesign.sdf",DUT,,,"MAXIMUM");\n                                       ^\n%Error: data/full_repos/permissive/19818566/software/host/davester_combinational_extractor/tb_test_citcuit.v:21: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19818566/software/host/davester_combinational_extractor/tb_test_citcuit.v:22: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0,main);\n      ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
   
   
   reg clk = 0;
   always #300 clk = !clk;

   reg A,B,C;

   integer ret;
   integer tvec_file;
   
   reg   Aval,Bval,Cval,Gval;
   integer   delay=0;
   reg [3:0]	     gg="0000";
   
   
   initial begin
      $sdf_annotate("mydesign.sdf",DUT,,,"MAXIMUM");
      $dumpfile("test.vcd");
      $dumpvars(0,main);
      
      tvec_file = $fopen("../test_circuit.tvec", "r");
      if (tvec_file == 0) begin
	 $display("data_file handle was NULL");
	 $finish;
      end
   end   
   
   always @(posedge clk) begin
      gg = {gg[2:0], gg[3]};
      
      ret = $fscanf(tvec_file, "%b,%b,%b,%b\n", Aval,Bval,Cval,Gval); 
      if (!$feof(tvec_file)) begin
	 A = Aval;
	 B = Bval;
	 C = Cval;
	 gg[0] = Gval;
	 
	 end
      else 
	begin
	   if (delay==4) begin
	      $display("SoE: %d",sum_of_errors);
	      $finish;
	   end
	   else begin
	      gg[0] = Gval;
	      delay = delay + 1;
	   end
	end
 end
   
   
   wire G;
   
   test_circuit DUT (.clk(clk),
		     .A(A),
		     .B(B),
		     .C(C),
		     .G(G));
   



   integer sum_of_errors=0;
   
   always @(posedge clk) begin
      if (G != gg[3]) begin
	 if (delay != 4) begin

	    sum_of_errors = sum_of_errors + 1;
	 end
      end
   end
   

   
   always @(posedge clk) begin      

   end
endmodule
module main;

   
   
   reg clk = 0;
   always #300 clk = !clk;

   reg A,B,C;

   integer ret;
   integer tvec_file;
   
   reg   Aval,Bval,Cval,Gval;
   integer   delay=0;
   reg [3:0]	     gg="0000";
   
   
   initial begin
      $sdf_annotate("mydesign.sdf",DUT,,,"MAXIMUM");
      $dumpfile("test.vcd");
      $dumpvars(0,main);
      
      tvec_file = $fopen("../test_circuit.tvec", "r");
      if (tvec_file == 0) begin
	 $display("data_file handle was NULL");
	 $finish;
      end
   end   
   
   always @(posedge clk) begin
      gg = {gg[2:0], gg[3]};
      
      ret = $fscanf(tvec_file, "%b,%b,%b,%b\n", Aval,Bval,Cval,Gval); 
      if (!$feof(tvec_file)) begin
	 A = Aval;
	 B = Bval;
	 C = Cval;
	 gg[0] = Gval;
	 
	 end
      else 
	begin
	   if (delay==4) begin
	      $display("SoE: %d",sum_of_errors);
	      $finish;
	   end
	   else begin
	      gg[0] = Gval;
	      delay = delay + 1;
	   end
	end
 end
   
   
   wire G;
   
   test_circuit DUT (.clk(clk),
		     .A(A),
		     .B(B),
		     .C(C),
		     .G(G));
   



   integer sum_of_errors=0;
   
   always @(posedge clk) begin
      if (G != gg[3]) begin
	 if (delay != 4) begin

	    sum_of_errors = sum_of_errors + 1;
	 end
      end
   end
   

   
   always @(posedge clk) begin      

   end
endmodule