data/full_repos/permissive/164251444/analog/cdk_oa/PFET1/netlist/pre_netlist/verilog.v
 line:14: before: "CDS_LIBNAME"
1: b"%Error: data/full_repos/permissive/164251444/analog/cdk_oa/PFET1/netlist/pre_netlist/verilog.v:19: Cannot find file containing module: 'PFET_B'\nPFET_B  P0 ( .b(VNW), .s(S), .g(G), .d(D));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164251444/analog/cdk_oa/PFET1/netlist/pre_netlist,data/full_repos/permissive/164251444/PFET_B\n             data/full_repos/permissive/164251444/analog/cdk_oa/PFET1/netlist/pre_netlist,data/full_repos/permissive/164251444/PFET_B.v\n             data/full_repos/permissive/164251444/analog/cdk_oa/PFET1/netlist/pre_netlist,data/full_repos/permissive/164251444/PFET_B.sv\n             PFET_B\n             PFET_B.v\n             PFET_B.sv\n             obj_dir/PFET_B\n             obj_dir/PFET_B.v\n             obj_dir/PFET_B.sv\n%Error: Exiting due to 1 error(s)\n"
module pfet1 ( D, G, S, VDD, VNW, VPW, VSS );

  inout VNW;
  inout S;
  inout VDD;
  inout VSS;
  inout G;
  inout D;
  inout VPW;
specify 
    specparam CDS_LIBNAME  = "RAIL12";
    specparam CDS_CELLNAME = "pfet1";
    specparam CDS_VIEWNAME = "schematic";
endspecify

PFET_B  P0 ( .b(VNW), .s(S), .g(G), .d(D));
endmodule
module pfet1 ( D, G, S, VDD, VNW, VPW, VSS );


  inout VNW;
  inout S;
  inout VDD;
  inout VSS;
  inout G;
  inout D;
  inout VPW;
specify 
    specparam CDS_LIBNAME  = "RAIL12";
    specparam CDS_CELLNAME = "pfet1";
    specparam CDS_VIEWNAME = "schematic";
endspecify

PFET_B  P0 ( .b(VNW), .s(S), .g(G), .d(D));
endmodule