data/full_repos/permissive/117179686/src/cache.v
 line:117: before: "endmodule"
1: b'%Error: data/full_repos/permissive/117179686/src/cache.v:1: Cannot find include file: defines.v\n`include "defines.v"  \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v.v\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/117179686/src/cache.v:6: syntax error, unexpected endmodule, expecting \';\'\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/cache.v:18: syntax error, unexpected \')\', expecting \'[\'\n);\n^\n%Error: data/full_repos/permissive/117179686/src/cache.v:19: Define or directive not defined: \'`DataMemNum\'\n reg[31: 0] data_mem[0:`DataMemNum-1];\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/cache.v:21: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/cache.v:27: syntax error, unexpected rand, expecting IDENTIFIER or \'=\' or do or final\n reg[1: 0] rand;\n           ^~~~\n%Error: data/full_repos/permissive/117179686/src/cache.v:30: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/117179686/src/cache.v:42: syntax error, unexpected always\n always @(*) begin\n ^~~~~~\n%Error: Exiting due to 8 error(s)\n'
module cache(
	input wire 			clk,
	input wire[31: 0] 	addr_i,
	input wire 			who,
	input wire 			modify,
	input wire[7: 0]	data_i,
	
	output wire[31: 0]	pc_out,
	output wire[7: 0]	mem_out,
	
);
	reg[31: 0] data_mem[0:`DataMemNum-1];
	
	initial begin
		$readmemh ( "a.S", data_mem);
	end
	
	reg[21: 0] block[5 + 2 : 0];
	reg[7: 0] data[5 + 2: 0][5: 0];
	reg[1: 0] rand;
	reg[7: 0] i;
	
	initial begin
		rand = 0;
		for (i = 0; i < 8'b11111111; i = i + 1) begin
			block[i] = 22'b0;
		end
	end
	always @(posedge clk) begin
		rand = rand + 1'b1;
	end
	
	reg[5: 0] idx;
	reg[20: 0] real_tag;
	always @(*) begin
		idx <= addr_i[11: 6];
		real_tag <= addr_i[31: 12];
	end
	
	always @(*) begin
		if (block[{idx, 2'b00}][21] == 1'b1 && block[{idx, 2'b00}][19: 0] == real_tag) begin
			if (who == 1'b0) begin
				
			end else begin
			
			end
		end else if (block[{idx, 2'b00}][21] == 1'b1 && block[{idx, 2'b00}][19: 0] == real_tag) begin
			
		end else if (block[{idx, 2'b00}][21] == 1'b1 && block[{idx, 2'b00}][19: 0] == real_tag) begin
			
		end else if (block[{idx, 2'b00}][21] == 1'b1 && block[{idx, 2'b00}][19: 0] == real_tag) begin
			
		end else begin
		
		end
	end

endmodule
module cache(
	input wire 			clk,
	input wire[31: 0] 	addr_i,
	input wire 			who,
	input wire 			modify,
	input wire[7: 0]	data_i,
	
	output wire[31: 0]	pc_out,
	output wire[7: 0]	mem_out,
	
);

	reg[31: 0] data_mem[0:`DataMemNum-1];
	
	initial begin
		$readmemh ( "a.S", data_mem);
	end
	
	reg[21: 0] block[5 + 2 : 0];
	reg[7: 0] data[5 + 2: 0][5: 0];
	reg[1: 0] rand;
	reg[7: 0] i;
	
	initial begin
		rand = 0;
		for (i = 0; i < 8'b11111111; i = i + 1) begin
			block[i] = 22'b0;
		end
	end
	always @(posedge clk) begin
		rand = rand + 1'b1;
	end
	
	reg[5: 0] idx;
	reg[20: 0] real_tag;
	always @(*) begin
		idx <= addr_i[11: 6];
		real_tag <= addr_i[31: 12];
	end
	
	always @(*) begin
		if (block[{idx, 2'b00}][21] == 1'b1 && block[{idx, 2'b00}][19: 0] == real_tag) begin
			if (who == 1'b0) begin
				
			end else begin
			
			end
		end else if (block[{idx, 2'b00}][21] == 1'b1 && block[{idx, 2'b00}][19: 0] == real_tag) begin
			
		end else if (block[{idx, 2'b00}][21] == 1'b1 && block[{idx, 2'b00}][19: 0] == real_tag) begin
			
		end else if (block[{idx, 2'b00}][21] == 1'b1 && block[{idx, 2'b00}][19: 0] == real_tag) begin
			
		end else begin
		
		end
	end

endmodule