data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
1: b'%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:80: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:82: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:86: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\nparameter width = `OR1200_OPERAND_WIDTH;\n                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter width = `OR1200_OPERAND_WIDTH;\n                                       ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:92: Define or directive not defined: \'`OR1200_LSUOP_WIDTH\'\ninput [`OR1200_LSUOP_WIDTH-1:0] lsu_op;\n       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:410: Define or directive not defined: \'`OR1200_LSUOP_LBZ\'\n  `OR1200_LSUOP_LBZ: begin\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:410: syntax error, unexpected \':\', expecting endcase\n  `OR1200_LSUOP_LBZ: begin\n                   ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:414: Define or directive not defined: \'`OR1200_LSUOP_LBS\'\n  `OR1200_LSUOP_LBS: begin\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:414: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n  `OR1200_LSUOP_LBS: begin\n                     ^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:418: Define or directive not defined: \'`OR1200_LSUOP_LHZ\'\n  `OR1200_LSUOP_LHZ: begin\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:418: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n  `OR1200_LSUOP_LHZ: begin\n                     ^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:422: Define or directive not defined: \'`OR1200_LSUOP_LHS\'\n  `OR1200_LSUOP_LHS: begin\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:422: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n  `OR1200_LSUOP_LHS: begin\n                     ^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v:426: syntax error, unexpected \':\', expecting clocking\n  default:\n         ^\n%Error: Cannot continue\n'
module or1200_mem2reg(addr, lsu_op, memdata, regdata);

parameter width = `OR1200_OPERAND_WIDTH;




input	[1:0]			addr;
input	[`OR1200_LSUOP_WIDTH-1:0]	lsu_op;
input	[width-1:0]		memdata;
output	[width-1:0]		regdata;





`ifdef OR1200_IMPL_MEM2REG2

`define OR1200_M2R_BYTE0 4'b0000
`define OR1200_M2R_BYTE1 4'b0001
`define OR1200_M2R_BYTE2 4'b0010
`define OR1200_M2R_BYTE3 4'b0011
`define OR1200_M2R_EXTB0 4'b0100
`define OR1200_M2R_EXTB1 4'b0101
`define OR1200_M2R_EXTB2 4'b0110
`define OR1200_M2R_EXTB3 4'b0111
`define OR1200_M2R_ZERO  4'b0000

reg	[7:0]			regdata_hh;
reg	[7:0]			regdata_hl;
reg	[7:0]			regdata_lh;
reg	[7:0]			regdata_ll;
reg	[width-1:0]		aligned;
reg	[3:0]			sel_byte0, sel_byte1,
				sel_byte2, sel_byte3;

assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};




always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b01x, 2'b00}:
			sel_byte0 = `OR1200_M2R_BYTE3;
		{3'b01x, 2'b01},
		{3'b10x, 2'b00}:
			sel_byte0 = `OR1200_M2R_BYTE2;
		{3'b01x, 2'b10}:
			sel_byte0 = `OR1200_M2R_BYTE1;
		default:
			sel_byte0 = `OR1200_M2R_BYTE0;
	endcase
end




always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b010, 2'bxx}:
			sel_byte1 = `OR1200_M2R_ZERO;
		{3'b011, 2'b00}:
			sel_byte1 = `OR1200_M2R_EXTB3;
		{3'b011, 2'b01}:
			sel_byte1 = `OR1200_M2R_EXTB2;
		{3'b011, 2'b10}:
			sel_byte1 = `OR1200_M2R_EXTB1;
		{3'b011, 2'b11}:
			sel_byte1 = `OR1200_M2R_EXTB0;
		{3'b10x, 2'b00}:
			sel_byte1 = `OR1200_M2R_BYTE3;
		default:
			sel_byte1 = `OR1200_M2R_BYTE1;
	endcase
end




always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b010, 2'bxx},
		{3'b100, 2'bxx}:
			sel_byte2 = `OR1200_M2R_ZERO;
		{3'b011, 2'b00},
		{3'b101, 2'b00}:
			sel_byte2 = `OR1200_M2R_EXTB3;
		{3'b011, 2'b01}:
			sel_byte2 = `OR1200_M2R_EXTB2;
		{3'b011, 2'b10},
		{3'b101, 2'b10}:
			sel_byte2 = `OR1200_M2R_EXTB1;
		{3'b011, 2'b11}:
			sel_byte2 = `OR1200_M2R_EXTB0;
		default:
			sel_byte2 = `OR1200_M2R_BYTE2;
	endcase
end




always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b010, 2'bxx},
		{3'b100, 2'bxx}:
			sel_byte3 = `OR1200_M2R_ZERO;
		{3'b011, 2'b00},
		{3'b101, 2'b00}:
			sel_byte3 = `OR1200_M2R_EXTB3;
		{3'b011, 2'b01}:
			sel_byte3 = `OR1200_M2R_EXTB2;
		{3'b011, 2'b10},
		{3'b101, 2'b10}:
			sel_byte3 = `OR1200_M2R_EXTB1;
		{3'b011, 2'b11}:
			sel_byte3 = `OR1200_M2R_EXTB0;
		default:
			sel_byte3 = `OR1200_M2R_BYTE3;
	endcase
end




always @(sel_byte0 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte0)
`else
	case(sel_byte0)
`endif
`else
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte0)
`else
	case(sel_byte0)
`endif
`endif
		`OR1200_M2R_BYTE0: begin
				regdata_ll = memdata[7:0];
			end
		`OR1200_M2R_BYTE1: begin
				regdata_ll = memdata[15:8];
			end
		`OR1200_M2R_BYTE2: begin
				regdata_ll = memdata[23:16];
			end
`ifdef OR1200_CASE_DEFAULT
		default: begin
`else
		`OR1200_M2R_BYTE3: begin
`endif
				regdata_ll = memdata[31:24];
			end
	endcase
end




always @(sel_byte1 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte1)
`else
	case(sel_byte1)
`endif
`else
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte1)
`else
	case(sel_byte1)
`endif
`endif
		`OR1200_M2R_ZERO: begin
				regdata_lh = 8'h00;
			end
		`OR1200_M2R_BYTE1: begin
				regdata_lh = memdata[15:8];
			end
		`OR1200_M2R_BYTE3: begin
				regdata_lh = memdata[31:24];
			end
		`OR1200_M2R_EXTB0: begin
				regdata_lh = {8{memdata[7]}};
			end
		`OR1200_M2R_EXTB1: begin
				regdata_lh = {8{memdata[15]}};
			end
		`OR1200_M2R_EXTB2: begin
				regdata_lh = {8{memdata[23]}};
			end
`ifdef OR1200_CASE_DEFAULT
		default: begin
`else
		`OR1200_M2R_EXTB3: begin
`endif
				regdata_lh = {8{memdata[31]}};
			end
	endcase
end




always @(sel_byte2 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte2)
`else
	case(sel_byte2)
`endif
`else
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte2)
`else
	case(sel_byte2)
`endif
`endif
		`OR1200_M2R_ZERO: begin
				regdata_hl = 8'h00;
			end
		`OR1200_M2R_BYTE2: begin
				regdata_hl = memdata[23:16];
			end
		`OR1200_M2R_EXTB0: begin
				regdata_hl = {8{memdata[7]}};
			end
		`OR1200_M2R_EXTB1: begin
				regdata_hl = {8{memdata[15]}};
			end
		`OR1200_M2R_EXTB2: begin
				regdata_hl = {8{memdata[23]}};
			end
`ifdef OR1200_CASE_DEFAULT
		default: begin
`else
		`OR1200_M2R_EXTB3: begin
`endif
				regdata_hl = {8{memdata[31]}};
			end
	endcase
end




always @(sel_byte3 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte3)
`else
	case(sel_byte3)
`endif
`else
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte3)
`else
	case(sel_byte3)
`endif
`endif
		`OR1200_M2R_ZERO: begin
				regdata_hh = 8'h00;
			end
		`OR1200_M2R_BYTE3: begin
				regdata_hh = memdata[31:24];
			end
		`OR1200_M2R_EXTB0: begin
				regdata_hh = {8{memdata[7]}};
			end
		`OR1200_M2R_EXTB1: begin
				regdata_hh = {8{memdata[15]}};
			end
		`OR1200_M2R_EXTB2: begin
				regdata_hh = {8{memdata[23]}};
			end
`ifdef OR1200_CASE_DEFAULT
		`OR1200_M2R_EXTB3: begin
`else
		`OR1200_M2R_EXTB3: begin
`endif
				regdata_hh = {8{memdata[31]}};
			end
	endcase
end

`else





reg	[width-1:0]		regdata;
reg	[width-1:0]		aligned;




always @(addr or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
	case(addr)
`else
	case(addr)
`endif
		2'b00:
			aligned = memdata;
		2'b01:
			aligned = {memdata[23:0], 8'b0};
		2'b10:
			aligned = {memdata[15:0], 16'b0};
		2'b11:
			aligned = {memdata[7:0], 24'b0};
	endcase
end




always @(lsu_op or aligned) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
	case(lsu_op)
`else
	case(lsu_op)
`endif
		`OR1200_LSUOP_LBZ: begin
				regdata[7:0] = aligned[31:24];
				regdata[31:8] = 24'b0;
			end
		`OR1200_LSUOP_LBS: begin
				regdata[7:0] = aligned[31:24];
				regdata[31:8] = {24{aligned[31]}};
			end
		`OR1200_LSUOP_LHZ: begin
				regdata[15:0] = aligned[31:16];
				regdata[31:16] = 16'b0;
			end
		`OR1200_LSUOP_LHS: begin
				regdata[15:0] = aligned[31:16];
				regdata[31:16] = {16{aligned[31]}};
			end
		default:
				regdata = aligned;
	endcase
end

`endif

endmodule
module or1200_mem2reg(addr, lsu_op, memdata, regdata);


parameter width = `OR1200_OPERAND_WIDTH;




input	[1:0]			addr;
input	[`OR1200_LSUOP_WIDTH-1:0]	lsu_op;
input	[width-1:0]		memdata;
output	[width-1:0]		regdata;





`ifdef OR1200_IMPL_MEM2REG2

`define OR1200_M2R_BYTE0 4'b0000
`define OR1200_M2R_BYTE1 4'b0001
`define OR1200_M2R_BYTE2 4'b0010
`define OR1200_M2R_BYTE3 4'b0011
`define OR1200_M2R_EXTB0 4'b0100
`define OR1200_M2R_EXTB1 4'b0101
`define OR1200_M2R_EXTB2 4'b0110
`define OR1200_M2R_EXTB3 4'b0111
`define OR1200_M2R_ZERO  4'b0000

reg	[7:0]			regdata_hh;
reg	[7:0]			regdata_hl;
reg	[7:0]			regdata_lh;
reg	[7:0]			regdata_ll;
reg	[width-1:0]		aligned;
reg	[3:0]			sel_byte0, sel_byte1,
				sel_byte2, sel_byte3;

assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};




always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b01x, 2'b00}:
			sel_byte0 = `OR1200_M2R_BYTE3;
		{3'b01x, 2'b01},
		{3'b10x, 2'b00}:
			sel_byte0 = `OR1200_M2R_BYTE2;
		{3'b01x, 2'b10}:
			sel_byte0 = `OR1200_M2R_BYTE1;
		default:
			sel_byte0 = `OR1200_M2R_BYTE0;
	endcase
end




always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b010, 2'bxx}:
			sel_byte1 = `OR1200_M2R_ZERO;
		{3'b011, 2'b00}:
			sel_byte1 = `OR1200_M2R_EXTB3;
		{3'b011, 2'b01}:
			sel_byte1 = `OR1200_M2R_EXTB2;
		{3'b011, 2'b10}:
			sel_byte1 = `OR1200_M2R_EXTB1;
		{3'b011, 2'b11}:
			sel_byte1 = `OR1200_M2R_EXTB0;
		{3'b10x, 2'b00}:
			sel_byte1 = `OR1200_M2R_BYTE3;
		default:
			sel_byte1 = `OR1200_M2R_BYTE1;
	endcase
end




always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b010, 2'bxx},
		{3'b100, 2'bxx}:
			sel_byte2 = `OR1200_M2R_ZERO;
		{3'b011, 2'b00},
		{3'b101, 2'b00}:
			sel_byte2 = `OR1200_M2R_EXTB3;
		{3'b011, 2'b01}:
			sel_byte2 = `OR1200_M2R_EXTB2;
		{3'b011, 2'b10},
		{3'b101, 2'b10}:
			sel_byte2 = `OR1200_M2R_EXTB1;
		{3'b011, 2'b11}:
			sel_byte2 = `OR1200_M2R_EXTB0;
		default:
			sel_byte2 = `OR1200_M2R_BYTE2;
	endcase
end




always @(addr or lsu_op) begin
	casex({lsu_op[2:0], addr})
		{3'b010, 2'bxx},
		{3'b100, 2'bxx}:
			sel_byte3 = `OR1200_M2R_ZERO;
		{3'b011, 2'b00},
		{3'b101, 2'b00}:
			sel_byte3 = `OR1200_M2R_EXTB3;
		{3'b011, 2'b01}:
			sel_byte3 = `OR1200_M2R_EXTB2;
		{3'b011, 2'b10},
		{3'b101, 2'b10}:
			sel_byte3 = `OR1200_M2R_EXTB1;
		{3'b011, 2'b11}:
			sel_byte3 = `OR1200_M2R_EXTB0;
		default:
			sel_byte3 = `OR1200_M2R_BYTE3;
	endcase
end




always @(sel_byte0 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte0)
`else
	case(sel_byte0)
`endif
`else
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte0)
`else
	case(sel_byte0)
`endif
`endif
		`OR1200_M2R_BYTE0: begin
				regdata_ll = memdata[7:0];
			end
		`OR1200_M2R_BYTE1: begin
				regdata_ll = memdata[15:8];
			end
		`OR1200_M2R_BYTE2: begin
				regdata_ll = memdata[23:16];
			end
`ifdef OR1200_CASE_DEFAULT
		default: begin
`else
		`OR1200_M2R_BYTE3: begin
`endif
				regdata_ll = memdata[31:24];
			end
	endcase
end




always @(sel_byte1 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte1)
`else
	case(sel_byte1)
`endif
`else
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte1)
`else
	case(sel_byte1)
`endif
`endif
		`OR1200_M2R_ZERO: begin
				regdata_lh = 8'h00;
			end
		`OR1200_M2R_BYTE1: begin
				regdata_lh = memdata[15:8];
			end
		`OR1200_M2R_BYTE3: begin
				regdata_lh = memdata[31:24];
			end
		`OR1200_M2R_EXTB0: begin
				regdata_lh = {8{memdata[7]}};
			end
		`OR1200_M2R_EXTB1: begin
				regdata_lh = {8{memdata[15]}};
			end
		`OR1200_M2R_EXTB2: begin
				regdata_lh = {8{memdata[23]}};
			end
`ifdef OR1200_CASE_DEFAULT
		default: begin
`else
		`OR1200_M2R_EXTB3: begin
`endif
				regdata_lh = {8{memdata[31]}};
			end
	endcase
end




always @(sel_byte2 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte2)
`else
	case(sel_byte2)
`endif
`else
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte2)
`else
	case(sel_byte2)
`endif
`endif
		`OR1200_M2R_ZERO: begin
				regdata_hl = 8'h00;
			end
		`OR1200_M2R_BYTE2: begin
				regdata_hl = memdata[23:16];
			end
		`OR1200_M2R_EXTB0: begin
				regdata_hl = {8{memdata[7]}};
			end
		`OR1200_M2R_EXTB1: begin
				regdata_hl = {8{memdata[15]}};
			end
		`OR1200_M2R_EXTB2: begin
				regdata_hl = {8{memdata[23]}};
			end
`ifdef OR1200_CASE_DEFAULT
		default: begin
`else
		`OR1200_M2R_EXTB3: begin
`endif
				regdata_hl = {8{memdata[31]}};
			end
	endcase
end




always @(sel_byte3 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte3)
`else
	case(sel_byte3)
`endif
`else
`ifdef OR1200_CASE_DEFAULT
	case(sel_byte3)
`else
	case(sel_byte3)
`endif
`endif
		`OR1200_M2R_ZERO: begin
				regdata_hh = 8'h00;
			end
		`OR1200_M2R_BYTE3: begin
				regdata_hh = memdata[31:24];
			end
		`OR1200_M2R_EXTB0: begin
				regdata_hh = {8{memdata[7]}};
			end
		`OR1200_M2R_EXTB1: begin
				regdata_hh = {8{memdata[15]}};
			end
		`OR1200_M2R_EXTB2: begin
				regdata_hh = {8{memdata[23]}};
			end
`ifdef OR1200_CASE_DEFAULT
		`OR1200_M2R_EXTB3: begin
`else
		`OR1200_M2R_EXTB3: begin
`endif
				regdata_hh = {8{memdata[31]}};
			end
	endcase
end

`else





reg	[width-1:0]		regdata;
reg	[width-1:0]		aligned;




always @(addr or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
	case(addr)
`else
	case(addr)
`endif
		2'b00:
			aligned = memdata;
		2'b01:
			aligned = {memdata[23:0], 8'b0};
		2'b10:
			aligned = {memdata[15:0], 16'b0};
		2'b11:
			aligned = {memdata[7:0], 24'b0};
	endcase
end




always @(lsu_op or aligned) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
	case(lsu_op)
`else
	case(lsu_op)
`endif
		`OR1200_LSUOP_LBZ: begin
				regdata[7:0] = aligned[31:24];
				regdata[31:8] = 24'b0;
			end
		`OR1200_LSUOP_LBS: begin
				regdata[7:0] = aligned[31:24];
				regdata[31:8] = {24{aligned[31]}};
			end
		`OR1200_LSUOP_LHZ: begin
				regdata[15:0] = aligned[31:16];
				regdata[31:16] = 16'b0;
			end
		`OR1200_LSUOP_LHS: begin
				regdata[15:0] = aligned[31:16];
				regdata[31:16] = {16{aligned[31]}};
			end
		default:
				regdata = aligned;
	endcase
end

`endif

endmodule