data/full_repos/permissive/178828990/tb.v
 line:118: before: "gray_valid"
1: b'%Warning-STMTDLY: data/full_repos/permissive/178828990/tb.v:106: Unsupported: Ignoring delay on this delayed statement.\nalways begin #(10/2) CLK = ~CLK; end\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/178828990/tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #0 reset = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/178828990/tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/178828990/tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #(10*2) reset = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/178828990/tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #0 gray_valid = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/178828990/tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #(10*5);\n  ^\n%Error: data/full_repos/permissive/178828990/tb.v:118: syntax error, unexpected \'@\'\n  @(negedge CLK) gray_valid = 1\'b1;\n  ^\n%Error: data/full_repos/permissive/178828990/tb.v:121: syntax error, unexpected \'@\'\n    @(negedge CLK) gray_data = pat_mem[i];\n    ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
reg CLK;
reg reset;
reg [7:0] pat_mem [0:99];
reg [7:0] exp_mem [0:17];
reg gray_valid;
reg [7:0] gray_data;
integer i;


wire CNT_valid;
wire [7:0] CNT [1:6];
wire code_valid;
wire [7:0] HC [1:6];
wire [7:0] M [1:6]; 

reg flag1;
reg flag2;
reg flag3;
reg done1;

wire [47:0] CNT_G, CNT_EXP;
wire [47:0] HC_G, HC_EXP;
wire [47:0] M_G, M_EXP;


`ifdef SDF
  initial $sdf_annotate(`SDFFILE, u_huffman);
`endif







huffman u_huffman(.clk(CLK), .reset(reset), .gray_valid(gray_valid), .gray_data(gray_data),
    .CNT_valid(CNT_valid), 
    .CNT1(CNT[1]),
    .CNT2(CNT[2]),
    .CNT3(CNT[3]),
    .CNT4(CNT[4]),
    .CNT5(CNT[5]),
    .CNT6(CNT[6]),
    .code_valid(code_valid), 
    .HC1(HC[1]),
    .HC2(HC[2]),
    .HC3(HC[3]),
    .HC4(HC[4]),
    .HC5(HC[5]),
    .HC6(HC[6]),
    .M1(M[1]),
    .M2(M[2]),
    .M3(M[3]),
    .M4(M[4]),
    .M5(M[5]),
    .M6(M[6]) );

assign CNT_G = {CNT[1], CNT[2], CNT[3], CNT[4], CNT[5], CNT[6]};
assign CNT_EXP = {exp_mem[0], exp_mem[1], exp_mem[2], exp_mem[3], exp_mem[4], exp_mem[5]};
assign HC_G = {HC[1], HC[2], HC[3], HC[4], HC[5], HC[6]};
assign HC_EXP = {exp_mem[6], exp_mem[7], exp_mem[8], exp_mem[9], exp_mem[10], exp_mem[11]};
assign M_G = {M[1], M[2], M[3], M[4], M[5], M[6]};
assign M_EXP = {exp_mem[12], exp_mem[13], exp_mem[14], exp_mem[15], exp_mem[16], exp_mem[17]};

initial $readmemh(`PAT, pat_mem);
initial $readmemh(`EXP, exp_mem);
initial $display("%s and %s were used for this simulation.", `PAT, `EXP);

initial CLK = 1'b0;

always begin #(`CLK_period/2) CLK = ~CLK; end

initial begin
  #0 reset = 1'b0;
  #`CLK_period reset = 1'b1;
  #(`CLK_period*2) reset = 1'b0;
end

initial begin
  #0 gray_valid = 1'b0;
     i = 0;
  #(`CLK_period*5);
  @(negedge CLK) gray_valid = 1'b1;
  gray_data = pat_mem[i];
  for (i=1;i<100;i=i+1)
    @(negedge CLK) gray_data = pat_mem[i];
  @(negedge CLK) gray_valid = 1'b0;
       gray_data = 8'b0;
end


always@(negedge CLK) begin
  if (reset) begin
    done1 <= 1'b0;
    flag1 <= 1'b0;
    flag2 <= 1'b0;
    flag3 <= 1'b0;
  end else begin

    if(CNT_valid == 1'b1) begin
      if (CNT_G == CNT_EXP) begin
        $display("Check CNT : PASS");
        flag1 <= 1'b1;
      end else begin
        $display("Check CNT : ERROR. Please fixed it first!");
        $display("Simulation stop here.");
        $finish;
      end
      done1 <= 1'b1;
    end

    if(code_valid == 1'b1) begin

      case ({(HC_G == HC_EXP),(M_G == M_EXP)})
        2'b00: begin
                 $display("Check HC : ERROR");
                 $display("Check M : ERROR");
                 $display("Simulation stop here.");
                 $finish;
               end
        2'b01: begin
                 $display("Check HC : ERROR");
                 $display("Check M : PASS");
                 $display("Simulation stop here.");
                 $finish;
               end
        2'b10: begin
                 $display("Check HC : PASS");
                 $display("Check M : ERRPR");
                 $display("Simulation stop here.");
                 $finish;
               end
        2'b11: begin
                 $display("Check HC : PASS");
                 $display("Check M : PASS");
                 if(flag1 == 1'b1)
                   $display("You PASS the contest now.");
                 else
                   $display("Where are those CNT output?");
                 $finish;

               end
        endcase
    end

  end
end




endmodule
module tb;

reg CLK;
reg reset;
reg [7:0] pat_mem [0:99];
reg [7:0] exp_mem [0:17];
reg gray_valid;
reg [7:0] gray_data;
integer i;


wire CNT_valid;
wire [7:0] CNT [1:6];
wire code_valid;
wire [7:0] HC [1:6];
wire [7:0] M [1:6]; 

reg flag1;
reg flag2;
reg flag3;
reg done1;

wire [47:0] CNT_G, CNT_EXP;
wire [47:0] HC_G, HC_EXP;
wire [47:0] M_G, M_EXP;


`ifdef SDF
  initial $sdf_annotate(`SDFFILE, u_huffman);
`endif







huffman u_huffman(.clk(CLK), .reset(reset), .gray_valid(gray_valid), .gray_data(gray_data),
    .CNT_valid(CNT_valid), 
    .CNT1(CNT[1]),
    .CNT2(CNT[2]),
    .CNT3(CNT[3]),
    .CNT4(CNT[4]),
    .CNT5(CNT[5]),
    .CNT6(CNT[6]),
    .code_valid(code_valid), 
    .HC1(HC[1]),
    .HC2(HC[2]),
    .HC3(HC[3]),
    .HC4(HC[4]),
    .HC5(HC[5]),
    .HC6(HC[6]),
    .M1(M[1]),
    .M2(M[2]),
    .M3(M[3]),
    .M4(M[4]),
    .M5(M[5]),
    .M6(M[6]) );

assign CNT_G = {CNT[1], CNT[2], CNT[3], CNT[4], CNT[5], CNT[6]};
assign CNT_EXP = {exp_mem[0], exp_mem[1], exp_mem[2], exp_mem[3], exp_mem[4], exp_mem[5]};
assign HC_G = {HC[1], HC[2], HC[3], HC[4], HC[5], HC[6]};
assign HC_EXP = {exp_mem[6], exp_mem[7], exp_mem[8], exp_mem[9], exp_mem[10], exp_mem[11]};
assign M_G = {M[1], M[2], M[3], M[4], M[5], M[6]};
assign M_EXP = {exp_mem[12], exp_mem[13], exp_mem[14], exp_mem[15], exp_mem[16], exp_mem[17]};

initial $readmemh(`PAT, pat_mem);
initial $readmemh(`EXP, exp_mem);
initial $display("%s and %s were used for this simulation.", `PAT, `EXP);

initial CLK = 1'b0;

always begin #(`CLK_period/2) CLK = ~CLK; end

initial begin
  #0 reset = 1'b0;
  #`CLK_period reset = 1'b1;
  #(`CLK_period*2) reset = 1'b0;
end

initial begin
  #0 gray_valid = 1'b0;
     i = 0;
  #(`CLK_period*5);
  @(negedge CLK) gray_valid = 1'b1;
  gray_data = pat_mem[i];
  for (i=1;i<100;i=i+1)
    @(negedge CLK) gray_data = pat_mem[i];
  @(negedge CLK) gray_valid = 1'b0;
       gray_data = 8'b0;
end


always@(negedge CLK) begin
  if (reset) begin
    done1 <= 1'b0;
    flag1 <= 1'b0;
    flag2 <= 1'b0;
    flag3 <= 1'b0;
  end else begin

    if(CNT_valid == 1'b1) begin
      if (CNT_G == CNT_EXP) begin
        $display("Check CNT : PASS");
        flag1 <= 1'b1;
      end else begin
        $display("Check CNT : ERROR. Please fixed it first!");
        $display("Simulation stop here.");
        $finish;
      end
      done1 <= 1'b1;
    end

    if(code_valid == 1'b1) begin

      case ({(HC_G == HC_EXP),(M_G == M_EXP)})
        2'b00: begin
                 $display("Check HC : ERROR");
                 $display("Check M : ERROR");
                 $display("Simulation stop here.");
                 $finish;
               end
        2'b01: begin
                 $display("Check HC : ERROR");
                 $display("Check M : PASS");
                 $display("Simulation stop here.");
                 $finish;
               end
        2'b10: begin
                 $display("Check HC : PASS");
                 $display("Check M : ERRPR");
                 $display("Simulation stop here.");
                 $finish;
               end
        2'b11: begin
                 $display("Check HC : PASS");
                 $display("Check M : PASS");
                 if(flag1 == 1'b1)
                   $display("You PASS the contest now.");
                 else
                   $display("Where are those CNT output?");
                 $finish;

               end
        endcase
    end

  end
end




endmodule