data/full_repos/permissive/201488448/2_circuits/2_sequential/fsm/15_ps2parser.v
data/verilator_xmls/ecb8c164-e63d-4093-96cd-59273414de4d.xml
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output done);

    parameter b1 = 2'd0, b2 = 2'd1, b3 = 2'd2, dn = 2'd3;
    reg	[1:0]	state, next_state;
    

    always@(*) begin
        case({state, in[3]})
            {b1, 1'b0}:	next_state = b1;
            {b1, 1'b1}:	next_state = b2;
            {b2, 1'b0}:	next_state = b3;
            {b2, 1'b1}:	next_state = b3;
            {b3, 1'b0}:	next_state = dn;
            {b3, 1'b1}:	next_state = dn;
            {dn, 1'b0}:	next_state = b1;
            {dn, 1'b1}:	next_state = b2;
        endcase
    end

    always@(posedge clk) begin
        if(reset)
            state <= b1;
        else
            state <= next_state;
    end

    assign	done = (state == dn);
    
endmodule
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output done);


    parameter b1 = 2'd0, b2 = 2'd1, b3 = 2'd2, dn = 2'd3;
    reg	[1:0]	state, next_state;
    

    always@(*) begin
        case({state, in[3]})
            {b1, 1'b0}:	next_state = b1;
            {b1, 1'b1}:	next_state = b2;
            {b2, 1'b0}:	next_state = b3;
            {b2, 1'b1}:	next_state = b3;
            {b3, 1'b0}:	next_state = dn;
            {b3, 1'b1}:	next_state = dn;
            {dn, 1'b0}:	next_state = b1;
            {dn, 1'b1}:	next_state = b2;
        endcase
    end

    always@(posedge clk) begin
        if(reset)
            state <= b1;
        else
            state <= next_state;
    end

    assign	done = (state == dn);
    
endmodule