data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src/ControlUnit.v
 line:65: before: "input"
1: b'%Error: data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src/ControlUnit.v:12: Cannot find include file: Parameters.v\n`include "Parameters.v"    \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v.v\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v.sv\n             Parameters.v\n             Parameters.v.v\n             Parameters.v.sv\n             obj_dir/Parameters.v\n             obj_dir/Parameters.v.v\n             obj_dir/Parameters.v.sv\n%Error: Exiting due to 1 error(s)\n'
module ControlUnit(
    input wire [6:0] Op,
    input wire [2:0] Fn3,
    input wire [6:0] Fn7,
    output wire JalD,
    output wire JalrD,
    output reg [2:0] RegWriteD,
    output wire MemToRegD,
    output reg [3:0] MemWriteD,
    output wire LoadNpcD,
    output reg [1:0] RegReadD,
    output reg [2:0] BranchTypeD,
    output reg [3:0] AluContrlD,
    output wire [1:0] AluSrc2D,
    output wire AluSrc1D,
    output reg [2:0] ImmType        
    );
endmodule
module ControlUnit(
    input wire [6:0] Op,
    input wire [2:0] Fn3,
    input wire [6:0] Fn7,
    output wire JalD,
    output wire JalrD,
    output reg [2:0] RegWriteD,
    output wire MemToRegD,
    output reg [3:0] MemWriteD,
    output wire LoadNpcD,
    output reg [1:0] RegReadD,
    output reg [2:0] BranchTypeD,
    output reg [3:0] AluContrlD,
    output wire [1:0] AluSrc2D,
    output wire AluSrc1D,
    output reg [2:0] ImmType        
    );

endmodule