data/full_repos/permissive/117026779/sim/Test_VGA.v
 line:86: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA.v:106: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA.v:110: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA.v:111: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: data/full_repos/permissive/117026779/sim/Test_VGA.v:41: Cannot find file containing module: \'VGA_Terminal\'\nVGA_Terminal vga_term(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/VGA_Terminal\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/VGA_Terminal.v\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/VGA_Terminal.sv\n             VGA_Terminal\n             VGA_Terminal.v\n             VGA_Terminal.sv\n             obj_dir/VGA_Terminal\n             obj_dir/VGA_Terminal.v\n             obj_dir/VGA_Terminal.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_VGA;

reg clk;
reg rst;
wire hsync;
wire vsync;
wire [3:0] r;
wire [3:0] g;
wire [3:0] b;
wire [11:0] address;
wire [8:0] data;
wire cs;

assign address = 0;
assign data = 0;
assign cs = 0;
wire busy;

VGA_Terminal vga_term(
    .clk(clk),
    .rst(rst),
    .hsync(hsync),
    .vsync(vsync),
    .r(r),
    .g(g),
    .b(b),
    .value0(32'h11111111),
    .value1(32'h22222222),
    .value2(32'h33333333),
    .value3(32'h44444444),
    .value4(32'h55555555),
    .value5(32'h66666666),
    .value6(32'h77777777),
    .value7(32'h88888888),
    .value8(32'h99999999),
    .value9(32'h9ABCDEF0),
    .value10(32'h12345678),
    .value11(32'h12345678),
    .value12(32'h22222222),
    .value13(32'h33333333),
    .value14(32'h44444444),
    .value15(32'h55555555),
    .value16(32'h66666666),
    .value17(32'h77777777),
    .value18(32'h88888888),
    .value19(32'hDEADBEEF),
    .address(address),
    .data(data),
    .cs(cs),
    .busy(busy),
    .text(3'b010),
    .background(3'b000)
);

task RESET;
begin
    rst = 0;
    clk = 0;
    #5
    rst = 1;
    #5
    rst = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask

parameter FULL_CYCLE = 32'd10_000_000;

initial begin
    #10
    #10
	RESET;
	CLOCK(FULL_CYCLE);

    #10 $stop;
    #5 $finish;
end

endmodule
module Test_VGA;


reg clk;
reg rst;
wire hsync;
wire vsync;
wire [3:0] r;
wire [3:0] g;
wire [3:0] b;
wire [11:0] address;
wire [8:0] data;
wire cs;

assign address = 0;
assign data = 0;
assign cs = 0;
wire busy;

VGA_Terminal vga_term(
    .clk(clk),
    .rst(rst),
    .hsync(hsync),
    .vsync(vsync),
    .r(r),
    .g(g),
    .b(b),
    .value0(32'h11111111),
    .value1(32'h22222222),
    .value2(32'h33333333),
    .value3(32'h44444444),
    .value4(32'h55555555),
    .value5(32'h66666666),
    .value6(32'h77777777),
    .value7(32'h88888888),
    .value8(32'h99999999),
    .value9(32'h9ABCDEF0),
    .value10(32'h12345678),
    .value11(32'h12345678),
    .value12(32'h22222222),
    .value13(32'h33333333),
    .value14(32'h44444444),
    .value15(32'h55555555),
    .value16(32'h66666666),
    .value17(32'h77777777),
    .value18(32'h88888888),
    .value19(32'hDEADBEEF),
    .address(address),
    .data(data),
    .cs(cs),
    .busy(busy),
    .text(3'b010),
    .background(3'b000)
);

task RESET;
begin
    rst = 0;
    clk = 0;
    #5
    rst = 1;
    #5
    rst = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask

parameter FULL_CYCLE = 32'd10_000_000;

initial begin
    #10
    #10
	RESET;
	CLOCK(FULL_CYCLE);

    #10 $stop;
    #5 $finish;
end

endmodule