data/full_repos/permissive/13111265/verilog/src/receivers/ClkRecoverSetCounter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/13111265/verilog/src/receivers/ClkRecoverSetCounter.v:71: Operator ADD expects 4 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                                   : ... In instance ClkRecoverSetCounter\n                    phaseAccum <= phaseAccum + 2\'d2;\n                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/13111265/verilog/src/receivers/ClkRecoverSetCounter.v:83: Operator ADD expects 4 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                                   : ... In instance ClkRecoverSetCounter\n                phaseAccum <= phaseAccum + 2\'d1;\n                                         ^\n%Error: Exiting due to 2 warning(s)\n'
module ClkRecoverSetCounter #(
    parameter TARGET_PERIOD = 10
)
(

    input clk,
    input rst,
    input rx,

    output reg clkStrobe,
    output reg rxClocked
);

parameter PHASE_HIGH = $clog2(TARGET_PERIOD-1) - 1;

wire intClk;

reg [PHASE_HIGH:0] phaseAccum;
reg intClkD1;
reg rxD1;
reg started;


wire refClk;
reg isZero;
assign refClk = (phaseAccum == 'd0) && ~isZero;
always @(posedge clk) begin
    isZero <= phaseAccum == 'd0;
end

assign intClk = (phaseAccum == (TARGET_PERIOD>>1));
always @(posedge clk) begin
    rxD1 <= rx;
    intClkD1  <= intClk;
    clkStrobe <= intClk & ~intClkD1;
    rxClocked <= (intClk & ~intClkD1) ? rx : rxClocked;
end


always @(posedge clk) begin
    if (rst) begin
        phaseAccum <= 'd0;
        started    <= 1'b0;
    end
    else begin
        if (started) begin

            if ((rxD1 ^ rx) && (phaseAccum >= (TARGET_PERIOD>>1))) begin
                if (phaseAccum == TARGET_PERIOD-1) begin
                    phaseAccum <= 'd1;
                end
                else if (phaseAccum == TARGET_PERIOD-2) begin
                    phaseAccum <= 'd0;
                end
                else begin
                    phaseAccum <= phaseAccum + 2'd2;
                end
            end

            else if ((rxD1 ^ rx) && (phaseAccum != 'd0)) begin
                phaseAccum <= phaseAccum;
            end

            else if (phaseAccum == TARGET_PERIOD-1) begin
                phaseAccum <= 'd0;
            end
            else begin
                phaseAccum <= phaseAccum + 2'd1;
            end
        end
        else begin
            started <= rxD1 ^ rx;
            phaseAccum <= 'd0;
        end
    end
end




endmodule
module ClkRecoverSetCounter #(
    parameter TARGET_PERIOD = 10
)
(

    input clk,
    input rst,
    input rx,

    output reg clkStrobe,
    output reg rxClocked
);


parameter PHASE_HIGH = $clog2(TARGET_PERIOD-1) - 1;

wire intClk;

reg [PHASE_HIGH:0] phaseAccum;
reg intClkD1;
reg rxD1;
reg started;


wire refClk;
reg isZero;
assign refClk = (phaseAccum == 'd0) && ~isZero;
always @(posedge clk) begin
    isZero <= phaseAccum == 'd0;
end

assign intClk = (phaseAccum == (TARGET_PERIOD>>1));
always @(posedge clk) begin
    rxD1 <= rx;
    intClkD1  <= intClk;
    clkStrobe <= intClk & ~intClkD1;
    rxClocked <= (intClk & ~intClkD1) ? rx : rxClocked;
end


always @(posedge clk) begin
    if (rst) begin
        phaseAccum <= 'd0;
        started    <= 1'b0;
    end
    else begin
        if (started) begin

            if ((rxD1 ^ rx) && (phaseAccum >= (TARGET_PERIOD>>1))) begin
                if (phaseAccum == TARGET_PERIOD-1) begin
                    phaseAccum <= 'd1;
                end
                else if (phaseAccum == TARGET_PERIOD-2) begin
                    phaseAccum <= 'd0;
                end
                else begin
                    phaseAccum <= phaseAccum + 2'd2;
                end
            end

            else if ((rxD1 ^ rx) && (phaseAccum != 'd0)) begin
                phaseAccum <= phaseAccum;
            end

            else if (phaseAccum == TARGET_PERIOD-1) begin
                phaseAccum <= 'd0;
            end
            else begin
                phaseAccum <= phaseAccum + 2'd1;
            end
        end
        else begin
            started <= rxD1 ^ rx;
            phaseAccum <= 'd0;
        end
    end
end




endmodule