data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/thinpad_top.v
'utf-8' codec can't decode byte 0xba in position 3088: invalid start byte
1: b'%Error: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/thinpad_top.v:88: Cannot find file containing module: \'pll_example\'\npll_example clock_gen \n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new,data/full_repos/permissive/155070420/pll_example\n             data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new,data/full_repos/permissive/155070420/pll_example.v\n             data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new,data/full_repos/permissive/155070420/pll_example.sv\n             pll_example\n             pll_example.v\n             pll_example.sv\n             obj_dir/pll_example\n             obj_dir/pll_example.v\n             obj_dir/pll_example.sv\n%Warning-WIDTH: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/thinpad_top.v:360: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'count\' generates 4 bits.\n                                                                                                     : ... In instance thinpad_top\n                temp_addr <= input_address[19:0] + count;\n                                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/thinpad_top.v:364: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'count\' generates 4 bits.\n                                                                                                     : ... In instance thinpad_top\n                temp_data <= input_data + count;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/thinpad_top.v:376: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'count\' generates 4 bits.\n                                                                                                     : ... In instance thinpad_top\n                temp_addr <= input_address[19:0] + count;\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/thinpad_top.v:394: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'count\' generates 4 bits.\n                                                                                                     : ... In instance thinpad_top\n                temp_addr <= input_address[19:0] + count;\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/thinpad_top.v:414: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'count\' generates 4 bits.\n                                                                                                     : ... In instance thinpad_top\n                temp_addr2 <= input_address[19:0] + count;\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/thinpad_top.v:422: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'count\' generates 4 bits.\n                                                                                                     : ... In instance thinpad_top\n                temp_addr2 <= input_address[19:0] + count;\n                                                  ^\n%Error: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/thinpad_top.v:501: Cannot find file containing module: \'async_receiver\'\nasync_receiver #(.ClkFrequency(50000000),.Baud(9600))  \n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/thinpad_top.v:527: Cannot find file containing module: \'async_transmitter\'\nasync_transmitter #(.ClkFrequency(50000000),.Baud(9600))  \n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/thinpad_top.v:542: Cannot find file containing module: \'vga\'\nvga #(12, 800, 856, 976, 1040, 600, 637, 643, 666, 1, 1) vga800x600at75 (\n^~~\n%Error: Exiting due to 4 error(s), 6 warning(s)\n'
module thinpad_top(
    input wire clk_50M,
    input wire clk_11M0592,

    input wire clock_btn,
    input wire reset_btn,

    input  wire[3:0]  touch_btn,
    input  wire[31:0] dip_sw,
    output wire[15:0] leds,
    output wire[7:0]  dpy0,
    output wire[7:0]  dpy1,


    output wire uart_rdn,
    output wire uart_wrn,
    input wire uart_dataready,
    input wire uart_tbre,
    input wire uart_tsre,


    inout wire[31:0] base_ram_data,
    output wire[19:0] base_ram_addr,
    output wire[3:0] base_ram_be_n,
    output wire base_ram_ce_n,
    output wire base_ram_oe_n,
    output wire base_ram_we_n,


    inout wire[31:0] ext_ram_data,
    output wire[19:0] ext_ram_addr,
    output wire[3:0] ext_ram_be_n,
    output wire ext_ram_ce_n,
    output wire ext_ram_oe_n,
    output wire ext_ram_we_n,


    output wire txd,
    input  wire rxd,


    output wire [22:0]flash_a,
    inout  wire [15:0]flash_d,
    output wire flash_rp_n,
    output wire flash_vpen,
    output wire flash_ce_n,
    output wire flash_oe_n,
    output wire flash_we_n,
    output wire flash_byte_n,


    output wire sl811_a0,

    output wire sl811_wr_n,
    output wire sl811_rd_n,
    output wire sl811_cs_n,
    output wire sl811_rst_n,
    output wire sl811_dack_n,
    input  wire sl811_intrq,
    input  wire sl811_drq_n,


    output wire dm9k_cmd,
    inout  wire[15:0] dm9k_sd,
    output wire dm9k_iow_n,
    output wire dm9k_ior_n,
    output wire dm9k_cs_n,
    output wire dm9k_pwrst_n,
    input  wire dm9k_int,


    output wire[2:0] video_red,
    output wire[2:0] video_green,
    output wire[1:0] video_blue,
    output wire video_hsync,
    output wire video_vsync,
    output wire video_clk,
    output wire video_de
);





wire locked, clk_10M, clk_20M;
pll_example clock_gen 
 (

  .clk_out1(clk_10M),
  .clk_out2(clk_20M),

  .reset(reset_btn),
  .locked(locked),

  .clk_in1(clk_50M)
 );

reg reset_of_clk10M;

always@(posedge clk_10M or negedge locked) begin
    if(~locked) reset_of_clk10M <= 1'b1;
    else        reset_of_clk10M <= 1'b0;
end

always@(posedge clk_10M or posedge reset_of_clk10M) begin
    if(reset_of_clk10M)begin

    end
    else begin

    end
end


















reg[15:0] led_bits;
assign leds = led_bits;


reg[31:0] input_address;
reg[31:0] input_data;
reg [2:0] state;
reg [3:0] count = 0;
localparam [2:0] SWITCH_ADDRESS = 3'b000,
                 SWITCH_DATA = 3'b001,
                 STORE_DATA = 3'b010,
                 LED_DATA = 3'b011,
                 STORE_DATA2 = 3'b100,
                 LED_DATA2 = 3'b101;


reg begin_end = 1'b0;
reg data_got = 1'b0;
reg temp_ce, temp_oe, temp_we;
reg[31:0] temp_data;
reg[19:0] temp_addr;
reg[3:0] temp_be;
assign base_ram_ce_n = temp_ce;
assign base_ram_oe_n = temp_oe;
assign base_ram_we_n = temp_we;
assign base_ram_data = temp_data;
assign base_ram_addr = temp_addr;
assign base_ram_be_n = temp_be;

reg temp_ce2, temp_oe2, temp_we2;
reg[31:0] temp_data2;
reg[19:0] temp_addr2;
reg[3:0] temp_be2;
assign ext_ram_ce_n = temp_ce2;
assign ext_ram_oe_n = temp_oe2;
assign ext_ram_we_n = temp_we2;
assign ext_ram_data = temp_data2;
assign ext_ram_addr = temp_addr2;
assign ext_ram_be_n = temp_be2;


always @(posedge clock_btn or posedge reset_btn) begin
    if(reset_btn) begin
        state <= SWITCH_ADDRESS;
        count <= 4'b0000;
    end
    else begin
        case(state)
        SWITCH_ADDRESS: begin
            input_address <= dip_sw;
            state <= SWITCH_DATA;
        end
        SWITCH_DATA: begin
            input_data <= dip_sw;
            state <= STORE_DATA;
        end
        STORE_DATA: begin
            if(count == 9) begin
                state <= LED_DATA;
                count <= 4'b0000;
            end
            else begin
                count <= count + 1'b1;
            end
        end
        LED_DATA: begin
            if(count == 9) begin
                state <= STORE_DATA2;
                count <= 4'b0000;
            end
            else begin
                count <= count + 1'b1;
            end
        end
        STORE_DATA2: begin
            if(count == 9) begin
                state <= LED_DATA2;
                count <= 4'b0000;
            end
            else begin
                count <= count + 1'b1;
            end
        end
        LED_DATA2: begin
            if(count == 9) begin
                state <= SWITCH_ADDRESS;
                count <= 4'b0000;
            end
            else begin
                count <= count + 1'b1;
            end
        end
        default: begin
            state <= SWITCH_ADDRESS;
            count <= 4'b0000;
        end
        endcase;
    end
end

always @(posedge clk_50M) begin
    if(clk_50M) begin
        temp_be <= 4'b0000;
        if(state == STORE_DATA) begin
            if(~begin_end) begin
                temp_addr <= input_address[19:0] + count;
                temp_ce <= 1'b0;
                temp_oe <= 1'b1;
                temp_we <= 1'b0;
                temp_data <= input_data + count;
                begin_end <= 1'b1;
            end
            else begin
                temp_ce <= 1'b1;
                temp_oe <= 1'b1;
                temp_we <= 1'b1;
                begin_end <= 1'b0;
            end
        end
        else if(state == LED_DATA) begin
            if(~begin_end) begin
                temp_addr <= input_address[19:0] + count;
                temp_data <= 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
                temp_ce <= 1'b0;
                temp_oe <= 1'b0;
                temp_we <= 1'b1;
                begin_end <= 1'b1;
                data_got <= 1'b0;
            end
            else begin
                temp_ce <= 1'b1;
                temp_oe <= 1'b1;
                temp_we <= 1'b1;
                begin_end <= 1'b0;
                data_got <= 1'b1;
            end
        end
        else if(state == STORE_DATA2) begin
            if(~begin_end) begin
                temp_addr <= input_address[19:0] + count;
                temp_data <= 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
                temp_ce <= 1'b0;
                temp_oe <= 1'b0;
                temp_we <= 1'b1;
                begin_end <= 1'b1;
                data_got <= 1'b0;

                temp_ce2 <= 1'b1;
                temp_oe2 <= 1'b1;
                temp_we2 <= 1'b1;
            end
            else begin
                temp_ce <= 1'b1;
                temp_oe <= 1'b1;
                temp_we <= 1'b1;
                begin_end <= 1'b0;
                data_got <= 1'b1;

                temp_data2 <= temp_data - 1'b1;
                temp_addr2 <= input_address[19:0] + count;
                temp_ce2 <= 1'b0;
                temp_oe2 <= 1'b1;
                temp_we2 <= 1'b0;
            end
        end
        else if(state == LED_DATA2) begin
            if(~begin_end) begin
                temp_addr2 <= input_address[19:0] + count;
                temp_data2 <= 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
                temp_ce2 <= 1'b0;
                temp_oe2 <= 1'b0;
                temp_we2 <= 1'b1;
                begin_end <= 1'b1;
                data_got <= 1'b0;
            end
            else begin
                temp_ce2 <= 1'b1;
                temp_oe2 <= 1'b1;
                temp_we2 <= 1'b1;
                begin_end <= 1'b0;
                data_got <= 1'b1;
            end
        end
    end
end

always @(state, data_got) begin
    case(state)
    SWITCH_ADDRESS: begin
        led_bits <= 16'b0101010101010101;
    end
    SWITCH_DATA: begin
        led_bits <= input_address[15:0];
    end
    STORE_DATA: begin
        led_bits <= {temp_addr[7:0], temp_data[7:0]};
    end
    LED_DATA: begin
        if(~data_got) begin
            led_bits <= 16'b0000000000000000;
        end
        else begin
            led_bits <= {temp_addr[7:0], temp_data[7:0]};
        end
    end
    STORE_DATA2: begin
        led_bits <= {temp_addr2[7:0], temp_data2[7:0]};
    end
    LED_DATA2: begin
        if(~data_got) begin
            led_bits <= 16'b0000000000000000;
        end
        else begin
            led_bits <= {temp_addr2[7:0], temp_data2[7:0]};
        end
    end
    default: begin
        led_bits <= 16'b0101010100000000;
    end
    endcase;
end




















wire [7:0] ext_uart_rx;
reg  [7:0] ext_uart_buffer, ext_uart_tx;
wire ext_uart_ready, ext_uart_busy;
reg ext_uart_start, ext_uart_avai;

async_receiver #(.ClkFrequency(50000000),.Baud(9600))
    ext_uart_r(
        .clk(clk_50M),
        .RxD(rxd),
        .RxD_data_ready(ext_uart_ready),
        .RxD_clear(ext_uart_ready),
        .RxD_data(ext_uart_rx)
    );
    
always @(posedge clk_50M) begin
    if(ext_uart_ready)begin
        ext_uart_buffer <= ext_uart_rx;
        ext_uart_avai <= 1;
    end else if(!ext_uart_busy && ext_uart_avai)begin 
        ext_uart_avai <= 0;
    end
end
always @(posedge clk_50M) begin
    if(!ext_uart_busy && ext_uart_avai)begin 
        ext_uart_tx <= ext_uart_buffer;
        ext_uart_start <= 1;
    end else begin 
        ext_uart_start <= 0;
    end
end

async_transmitter #(.ClkFrequency(50000000),.Baud(9600))
    ext_uart_t(
        .clk(clk_50M),
        .TxD(txd),
        .TxD_busy(ext_uart_busy),
        .TxD_start(ext_uart_start),
        .TxD_data(ext_uart_tx)
    );


wire [11:0] hdata;
assign video_red = hdata < 266 ? 3'b111 : 0;
assign video_green = hdata < 532 && hdata >= 266 ? 3'b111 : 0;
assign video_blue = hdata >= 532 ? 2'b11 : 0;
assign video_clk = clk_50M;
vga #(12, 800, 856, 976, 1040, 600, 637, 643, 666, 1, 1) vga800x600at75 (
    .clk(clk_50M), 
    .hdata(hdata),
    .vdata(),
    .hsync(video_hsync),
    .vsync(video_vsync),
    .data_enable(video_de)
);


endmodule
module thinpad_top(
    input wire clk_50M,
    input wire clk_11M0592,

    input wire clock_btn,
    input wire reset_btn,

    input  wire[3:0]  touch_btn,
    input  wire[31:0] dip_sw,
    output wire[15:0] leds,
    output wire[7:0]  dpy0,
    output wire[7:0]  dpy1,


    output wire uart_rdn,
    output wire uart_wrn,
    input wire uart_dataready,
    input wire uart_tbre,
    input wire uart_tsre,


    inout wire[31:0] base_ram_data,
    output wire[19:0] base_ram_addr,
    output wire[3:0] base_ram_be_n,
    output wire base_ram_ce_n,
    output wire base_ram_oe_n,
    output wire base_ram_we_n,


    inout wire[31:0] ext_ram_data,
    output wire[19:0] ext_ram_addr,
    output wire[3:0] ext_ram_be_n,
    output wire ext_ram_ce_n,
    output wire ext_ram_oe_n,
    output wire ext_ram_we_n,


    output wire txd,
    input  wire rxd,


    output wire [22:0]flash_a,
    inout  wire [15:0]flash_d,
    output wire flash_rp_n,
    output wire flash_vpen,
    output wire flash_ce_n,
    output wire flash_oe_n,
    output wire flash_we_n,
    output wire flash_byte_n,


    output wire sl811_a0,

    output wire sl811_wr_n,
    output wire sl811_rd_n,
    output wire sl811_cs_n,
    output wire sl811_rst_n,
    output wire sl811_dack_n,
    input  wire sl811_intrq,
    input  wire sl811_drq_n,


    output wire dm9k_cmd,
    inout  wire[15:0] dm9k_sd,
    output wire dm9k_iow_n,
    output wire dm9k_ior_n,
    output wire dm9k_cs_n,
    output wire dm9k_pwrst_n,
    input  wire dm9k_int,


    output wire[2:0] video_red,
    output wire[2:0] video_green,
    output wire[1:0] video_blue,
    output wire video_hsync,
    output wire video_vsync,
    output wire video_clk,
    output wire video_de
);






wire locked, clk_10M, clk_20M;
pll_example clock_gen 
 (

  .clk_out1(clk_10M),
  .clk_out2(clk_20M),

  .reset(reset_btn),
  .locked(locked),

  .clk_in1(clk_50M)
 );

reg reset_of_clk10M;

always@(posedge clk_10M or negedge locked) begin
    if(~locked) reset_of_clk10M <= 1'b1;
    else        reset_of_clk10M <= 1'b0;
end

always@(posedge clk_10M or posedge reset_of_clk10M) begin
    if(reset_of_clk10M)begin

    end
    else begin

    end
end


















reg[15:0] led_bits;
assign leds = led_bits;


reg[31:0] input_address;
reg[31:0] input_data;
reg [2:0] state;
reg [3:0] count = 0;
localparam [2:0] SWITCH_ADDRESS = 3'b000,
                 SWITCH_DATA = 3'b001,
                 STORE_DATA = 3'b010,
                 LED_DATA = 3'b011,
                 STORE_DATA2 = 3'b100,
                 LED_DATA2 = 3'b101;


reg begin_end = 1'b0;
reg data_got = 1'b0;
reg temp_ce, temp_oe, temp_we;
reg[31:0] temp_data;
reg[19:0] temp_addr;
reg[3:0] temp_be;
assign base_ram_ce_n = temp_ce;
assign base_ram_oe_n = temp_oe;
assign base_ram_we_n = temp_we;
assign base_ram_data = temp_data;
assign base_ram_addr = temp_addr;
assign base_ram_be_n = temp_be;

reg temp_ce2, temp_oe2, temp_we2;
reg[31:0] temp_data2;
reg[19:0] temp_addr2;
reg[3:0] temp_be2;
assign ext_ram_ce_n = temp_ce2;
assign ext_ram_oe_n = temp_oe2;
assign ext_ram_we_n = temp_we2;
assign ext_ram_data = temp_data2;
assign ext_ram_addr = temp_addr2;
assign ext_ram_be_n = temp_be2;


always @(posedge clock_btn or posedge reset_btn) begin
    if(reset_btn) begin
        state <= SWITCH_ADDRESS;
        count <= 4'b0000;
    end
    else begin
        case(state)
        SWITCH_ADDRESS: begin
            input_address <= dip_sw;
            state <= SWITCH_DATA;
        end
        SWITCH_DATA: begin
            input_data <= dip_sw;
            state <= STORE_DATA;
        end
        STORE_DATA: begin
            if(count == 9) begin
                state <= LED_DATA;
                count <= 4'b0000;
            end
            else begin
                count <= count + 1'b1;
            end
        end
        LED_DATA: begin
            if(count == 9) begin
                state <= STORE_DATA2;
                count <= 4'b0000;
            end
            else begin
                count <= count + 1'b1;
            end
        end
        STORE_DATA2: begin
            if(count == 9) begin
                state <= LED_DATA2;
                count <= 4'b0000;
            end
            else begin
                count <= count + 1'b1;
            end
        end
        LED_DATA2: begin
            if(count == 9) begin
                state <= SWITCH_ADDRESS;
                count <= 4'b0000;
            end
            else begin
                count <= count + 1'b1;
            end
        end
        default: begin
            state <= SWITCH_ADDRESS;
            count <= 4'b0000;
        end
        endcase;
    end
end

always @(posedge clk_50M) begin
    if(clk_50M) begin
        temp_be <= 4'b0000;
        if(state == STORE_DATA) begin
            if(~begin_end) begin
                temp_addr <= input_address[19:0] + count;
                temp_ce <= 1'b0;
                temp_oe <= 1'b1;
                temp_we <= 1'b0;
                temp_data <= input_data + count;
                begin_end <= 1'b1;
            end
            else begin
                temp_ce <= 1'b1;
                temp_oe <= 1'b1;
                temp_we <= 1'b1;
                begin_end <= 1'b0;
            end
        end
        else if(state == LED_DATA) begin
            if(~begin_end) begin
                temp_addr <= input_address[19:0] + count;
                temp_data <= 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
                temp_ce <= 1'b0;
                temp_oe <= 1'b0;
                temp_we <= 1'b1;
                begin_end <= 1'b1;
                data_got <= 1'b0;
            end
            else begin
                temp_ce <= 1'b1;
                temp_oe <= 1'b1;
                temp_we <= 1'b1;
                begin_end <= 1'b0;
                data_got <= 1'b1;
            end
        end
        else if(state == STORE_DATA2) begin
            if(~begin_end) begin
                temp_addr <= input_address[19:0] + count;
                temp_data <= 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
                temp_ce <= 1'b0;
                temp_oe <= 1'b0;
                temp_we <= 1'b1;
                begin_end <= 1'b1;
                data_got <= 1'b0;

                temp_ce2 <= 1'b1;
                temp_oe2 <= 1'b1;
                temp_we2 <= 1'b1;
            end
            else begin
                temp_ce <= 1'b1;
                temp_oe <= 1'b1;
                temp_we <= 1'b1;
                begin_end <= 1'b0;
                data_got <= 1'b1;

                temp_data2 <= temp_data - 1'b1;
                temp_addr2 <= input_address[19:0] + count;
                temp_ce2 <= 1'b0;
                temp_oe2 <= 1'b1;
                temp_we2 <= 1'b0;
            end
        end
        else if(state == LED_DATA2) begin
            if(~begin_end) begin
                temp_addr2 <= input_address[19:0] + count;
                temp_data2 <= 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
                temp_ce2 <= 1'b0;
                temp_oe2 <= 1'b0;
                temp_we2 <= 1'b1;
                begin_end <= 1'b1;
                data_got <= 1'b0;
            end
            else begin
                temp_ce2 <= 1'b1;
                temp_oe2 <= 1'b1;
                temp_we2 <= 1'b1;
                begin_end <= 1'b0;
                data_got <= 1'b1;
            end
        end
    end
end

always @(state, data_got) begin
    case(state)
    SWITCH_ADDRESS: begin
        led_bits <= 16'b0101010101010101;
    end
    SWITCH_DATA: begin
        led_bits <= input_address[15:0];
    end
    STORE_DATA: begin
        led_bits <= {temp_addr[7:0], temp_data[7:0]};
    end
    LED_DATA: begin
        if(~data_got) begin
            led_bits <= 16'b0000000000000000;
        end
        else begin
            led_bits <= {temp_addr[7:0], temp_data[7:0]};
        end
    end
    STORE_DATA2: begin
        led_bits <= {temp_addr2[7:0], temp_data2[7:0]};
    end
    LED_DATA2: begin
        if(~data_got) begin
            led_bits <= 16'b0000000000000000;
        end
        else begin
            led_bits <= {temp_addr2[7:0], temp_data2[7:0]};
        end
    end
    default: begin
        led_bits <= 16'b0101010100000000;
    end
    endcase;
end




















wire [7:0] ext_uart_rx;
reg  [7:0] ext_uart_buffer, ext_uart_tx;
wire ext_uart_ready, ext_uart_busy;
reg ext_uart_start, ext_uart_avai;

async_receiver #(.ClkFrequency(50000000),.Baud(9600))
    ext_uart_r(
        .clk(clk_50M),
        .RxD(rxd),
        .RxD_data_ready(ext_uart_ready),
        .RxD_clear(ext_uart_ready),
        .RxD_data(ext_uart_rx)
    );
    
always @(posedge clk_50M) begin
    if(ext_uart_ready)begin
        ext_uart_buffer <= ext_uart_rx;
        ext_uart_avai <= 1;
    end else if(!ext_uart_busy && ext_uart_avai)begin 
        ext_uart_avai <= 0;
    end
end
always @(posedge clk_50M) begin
    if(!ext_uart_busy && ext_uart_avai)begin 
        ext_uart_tx <= ext_uart_buffer;
        ext_uart_start <= 1;
    end else begin 
        ext_uart_start <= 0;
    end
end

async_transmitter #(.ClkFrequency(50000000),.Baud(9600))
    ext_uart_t(
        .clk(clk_50M),
        .TxD(txd),
        .TxD_busy(ext_uart_busy),
        .TxD_start(ext_uart_start),
        .TxD_data(ext_uart_tx)
    );


wire [11:0] hdata;
assign video_red = hdata < 266 ? 3'b111 : 0;
assign video_green = hdata < 532 && hdata >= 266 ? 3'b111 : 0;
assign video_blue = hdata >= 532 ? 2'b11 : 0;
assign video_clk = clk_50M;
vga #(12, 800, 856, 976, 1040, 600, 637, 643, 666, 1, 1) vga800x600at75 (
    .clk(clk_50M), 
    .hdata(hdata),
    .vdata(),
    .hsync(video_hsync),
    .vsync(video_vsync),
    .data_enable(video_de)
);


endmodule