data/full_repos/permissive/169496369/shiftleft2_26.v
data/verilator_xmls/03913c69-9e1b-437c-8b7f-893550432df9.xml
module shiftleft2_26(a, b, c);
    input [25:0] a;
    input [3:0] b;
    
    output [31:0] c;
    
    logic [27:0] d;
    
    assign d = (({2'b00, a}) << 2'd2);
    
    assign c = {b, d};
endmodule
module shiftleft2_26(a, b, c);

    input [25:0] a;
    input [3:0] b;
    
    output [31:0] c;
    
    logic [27:0] d;
    
    assign d = (({2'b00, a}) << 2'd2);
    
    assign c = {b, d};
endmodule