data/full_repos/permissive/141582589/src/common_rtl/video/vin_frame_buffer_ctrl.v
'utf-8' codec can't decode byte 0xbf in position 24: invalid start byte
1: b'%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/video/vin_frame_buffer_ctrl.v:45: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                                    : ... In instance vin_frame_buffer_ctrl\nreg[10:0] burst_line = 12\'d0; \n                       ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/141582589/src/common_rtl/video/vin_frame_buffer_ctrl.v:75: Cannot find file containing module: \'lite_fifo\'\nlite_fifo#\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/lite_fifo\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/lite_fifo.v\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/lite_fifo.sv\n             lite_fifo\n             lite_fifo.v\n             lite_fifo.sv\n             obj_dir/lite_fifo\n             obj_dir/lite_fifo.v\n             obj_dir/lite_fifo.sv\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/video/vin_frame_buffer_ctrl.v:227: Operator GTE expects 10 bits on the LHS, but LHS\'s VARREF \'rdusedw\' generates 8 bits.\n                                                                                                     : ... In instance vin_frame_buffer_ctrl\n   else if((rdusedw >= BURST_LEN[7:0]) || (remain_len <= BURST_LEN && rdusedw >= remain_len - 10\'d1))\n                                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/video/vin_frame_buffer_ctrl.v:243: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'burst_line\' generates 11 bits.\n                                                                                                     : ... In instance vin_frame_buffer_ctrl\n  wr_max_line <= burst_line;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/video/vin_frame_buffer_ctrl.v:251: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                                     : ... In instance vin_frame_buffer_ctrl\n  burst_line <= 12\'d0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/video/vin_frame_buffer_ctrl.v:253: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                                     : ... In instance vin_frame_buffer_ctrl\n  burst_line <= 12\'d0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/video/vin_frame_buffer_ctrl.v:255: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 12 bits.\n                                                                                                     : ... In instance vin_frame_buffer_ctrl\n  burst_line <= burst_line + 12\'d1;\n             ^~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module vin_frame_buffer_ctrl
 #(
	parameter MEM_DATA_BITS = 64,
	parameter INTERLACE = 1
) 
(
	input rst_n,
	input vin_clk,
	input vin_vs,
	input vin_f,
	input vin_de,
	input[15:0] vin_data,
	input[11:0] vin_width,
	input[11:0] vin_height,
	output reg fifo_afull,
	input mem_clk,
	output reg wr_burst_req,
	output reg[9:0] wr_burst_len,

	output reg[26:0] wr_burst_addr,
	input wr_burst_data_req,
	output[MEM_DATA_BITS - 1:0] wr_burst_data,
	input burst_finish,
	output reg[11:0] wr_max_line,
	input[1:0] base_addr,
	output reg[1:0] frame_addr
);                                                   
initial                                              
begin
	frame_addr <= 2'd0;
end
localparam BURST_LEN = 10'd128;
localparam BURST_IDLE = 3'd0;
localparam BURST_ONE_LINE_START = 3'd1;
localparam BURSTING = 3'd2;
localparam BURST_END = 3'd3;
localparam BURST_ONE_LINE_END = 3'd4;
reg[2:0] burst_state = 3'd0;
reg[2:0] burst_state_next = 3'd0;
reg[10:0] burst_line = 12'd0;
reg[9:0] byte_per_line = 10'd0;


reg[9:0] remain_len = 10'd0;
wire[MEM_DATA_BITS - 1:0] data;
reg[15:0] pixel0 = 16'd0;
reg[15:0] pixel1 = 16'd0;
reg[15:0] pixel2 = 16'd0;
reg[15:0] pixel3 = 16'd0;
reg[11:0] data_cnt  = 12'd0;
reg vin_vs_mem_clk_d0 = 1'b0;
reg vin_vs_mem_clk_d1 = 1'b0;
reg vin_vs_d0 = 1'b0;
reg vin_vs_d1 = 1'b0;
reg frame_flag = 1'b0;
reg frame_flag_vin = 1'b0;
reg fifo_wr_req = 1'b0;
wire[7:0] rdusedw;
wire[7:0] wrusedw;
always@(posedge vin_clk)
begin
	fifo_afull <= (wrusedw > 8'd245);
end

`ifdef Xilinx
assign data = {pixel0,pixel1,pixel2,pixel3};
`else
assign data = {pixel3,pixel2,pixel1,pixel0};
`endif
lite_fifo#
(
	.COMMON_CLOCK(0),
	.ADDR_WIDTH(8),
	.DATA_WIDTH(64)
)  vin_frame_buffer_ctrl_fifo_m0(
	.aclr(frame_flag),
	.data(data),
	.rdclk(mem_clk),
	.rdreq(wr_burst_data_req),
	.wrclk(vin_clk),
	.wrreq(fifo_wr_req),
	.q(wr_burst_data),
	.rdempty(),
	.rdusedw(rdusedw),
	.wrfull(),
	.wrusedw(wrusedw)); 
		
always@(posedge vin_clk)
begin
	vin_vs_d0 <= vin_vs;
	vin_vs_d1 <= vin_vs_d0;
	frame_flag_vin <= vin_vs_d0 && ~vin_vs_d1;
end

always@(posedge vin_clk)
begin
	if(!rst_n)
		data_cnt <= 12'd0;
	else if(frame_flag_vin)
		data_cnt <= 12'd0;
	else if(vin_de)
		begin
			if(data_cnt == vin_width - 12'd1)
				data_cnt <= 12'd0;
			else
				data_cnt <= data_cnt + 12'd1;
		end
	else
		data_cnt <= data_cnt;
end

always@(posedge vin_clk)
begin
	if(vin_de && (data_cnt[1:0] == 2'd0))
		pixel0 <= vin_data;
	else
		pixel0 <= pixel0;		
end

always@(posedge vin_clk)
begin
	if(vin_de && (data_cnt[1:0] == 2'd1))
		pixel1 <= vin_data;
	else
		pixel1 <= pixel1;		
end

always@(posedge vin_clk)
begin
	if(vin_de && (data_cnt[1:0] == 2'd2))
		pixel2 <= vin_data;
	else
		pixel2 <= pixel2;
end

always@(posedge vin_clk)
begin
	if(vin_de && (data_cnt[1:0] == 2'd3))
		pixel3 <= vin_data;
	else
		pixel3 <= pixel3;
end

always@(posedge vin_clk)
begin
	if(vin_de &&(data_cnt[1:0] == 2'd3 || data_cnt == vin_width - 12'd1))
		fifo_wr_req <= 1'b1;
	else
		fifo_wr_req <= 1'b0;
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		byte_per_line <= 10'd0;
	else if(frame_flag)
		if(vin_width[1:0] == 2'd0)
			byte_per_line <= vin_width[11:2];
		else
			byte_per_line <= vin_width[11:2] + 10'd1;
	else
		byte_per_line <= byte_per_line;
end


wire[26:0] ddr_wr_base;
generate
	if(INTERLACE)

		assign ddr_wr_base = {1'b0,base_addr,frame_addr[1:0],burst_line[9:0],vin_f,8'd0,3'd0};
	else

		assign ddr_wr_base =  {base_addr,frame_addr[1:0],burst_line[10:0],9'd0,3'd0};
endgenerate	
always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)

		wr_burst_addr <= 27'd0;
	else if(burst_state_next == BURST_ONE_LINE_START)
		wr_burst_addr <= ddr_wr_base;
	else if(burst_state_next == BURST_END  && burst_state != BURST_END)
		wr_burst_addr <= wr_burst_addr + {15'd0,BURST_LEN[8:0],3'd0};
	else
		wr_burst_addr <= wr_burst_addr;
end

always@(posedge mem_clk)
begin
	vin_vs_mem_clk_d0 <= vin_vs;
	vin_vs_mem_clk_d1 <= vin_vs_mem_clk_d0;
	frame_flag <= vin_vs_mem_clk_d0 && ~vin_vs_mem_clk_d1;
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		burst_state <= BURST_IDLE;
	else if(frame_flag)
		burst_state <= BURST_IDLE;
	else
		burst_state <= burst_state_next;
end
always@(*)
begin
	case(burst_state)
		BURST_IDLE:
			if(rdusedw > BURST_LEN[7:0])
				burst_state_next <= BURST_ONE_LINE_START;
			else
				burst_state_next <= BURST_IDLE;
		BURST_ONE_LINE_START:
			burst_state_next <= BURSTING;
		BURSTING:
			if(burst_finish)
				burst_state_next <= BURST_END;
			else
				burst_state_next <= BURSTING;
		BURST_END:
			if(remain_len == 10'd0)
				burst_state_next <= BURST_ONE_LINE_END;
			else if((rdusedw >= BURST_LEN[7:0]) || (remain_len <= BURST_LEN && rdusedw >= remain_len - 10'd1))
				burst_state_next <= BURSTING;
			else
				burst_state_next <= BURST_END;
		BURST_ONE_LINE_END:
			burst_state_next <= BURST_IDLE;
		default:
			burst_state_next <= BURST_IDLE;
	endcase
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		wr_max_line <= 12'd0;
	else if(frame_flag)
		wr_max_line <= burst_line;
	else
		wr_max_line <= wr_max_line;
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		burst_line <= 12'd0;
	else if(frame_flag)
		burst_line <= 12'd0;
	else if(burst_state == BURST_ONE_LINE_END)
		burst_line <= burst_line + 12'd1;
	else
		burst_line <= burst_line;
end
always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		frame_addr <= 2'd0;
	else if(frame_flag && vin_f)

		frame_addr <= frame_addr + 2'd1;
	else
		frame_addr <= frame_addr;
end	


always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		remain_len <= 10'd0;
	else if(burst_state_next == BURST_ONE_LINE_START)
		remain_len <= byte_per_line;
	else if(burst_state_next == BURST_END && burst_state != BURST_END)
		if(remain_len < BURST_LEN)
			remain_len <= 10'd0;
		else
			remain_len <= remain_len - BURST_LEN;	
	else
		remain_len <= remain_len;
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		wr_burst_len <= 10'd0;
	else if(burst_state_next == BURSTING && burst_state != BURSTING)
		if(remain_len > BURST_LEN)
			wr_burst_len <= BURST_LEN;
		else
			wr_burst_len <= remain_len;
	else
		wr_burst_len <=  wr_burst_len;
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		wr_burst_req <= 1'd0;
	else if(burst_state_next == BURSTING && burst_state != BURSTING)
		wr_burst_req <= 1'b1;
	else if(burst_finish  || wr_burst_data_req || burst_state == BURST_IDLE)
		wr_burst_req <= 1'b0;
	else
		wr_burst_req <= wr_burst_req;
end

endmodule
module vin_frame_buffer_ctrl
 #(
	parameter MEM_DATA_BITS = 64,
	parameter INTERLACE = 1
) 
(
	input rst_n,
	input vin_clk,
	input vin_vs,
	input vin_f,
	input vin_de,
	input[15:0] vin_data,
	input[11:0] vin_width,
	input[11:0] vin_height,
	output reg fifo_afull,
	input mem_clk,
	output reg wr_burst_req,
	output reg[9:0] wr_burst_len,

	output reg[26:0] wr_burst_addr,
	input wr_burst_data_req,
	output[MEM_DATA_BITS - 1:0] wr_burst_data,
	input burst_finish,
	output reg[11:0] wr_max_line,
	input[1:0] base_addr,
	output reg[1:0] frame_addr
);
                                                   
initial                                              
begin
	frame_addr <= 2'd0;
end
localparam BURST_LEN = 10'd128;
localparam BURST_IDLE = 3'd0;
localparam BURST_ONE_LINE_START = 3'd1;
localparam BURSTING = 3'd2;
localparam BURST_END = 3'd3;
localparam BURST_ONE_LINE_END = 3'd4;
reg[2:0] burst_state = 3'd0;
reg[2:0] burst_state_next = 3'd0;
reg[10:0] burst_line = 12'd0;
reg[9:0] byte_per_line = 10'd0;


reg[9:0] remain_len = 10'd0;
wire[MEM_DATA_BITS - 1:0] data;
reg[15:0] pixel0 = 16'd0;
reg[15:0] pixel1 = 16'd0;
reg[15:0] pixel2 = 16'd0;
reg[15:0] pixel3 = 16'd0;
reg[11:0] data_cnt  = 12'd0;
reg vin_vs_mem_clk_d0 = 1'b0;
reg vin_vs_mem_clk_d1 = 1'b0;
reg vin_vs_d0 = 1'b0;
reg vin_vs_d1 = 1'b0;
reg frame_flag = 1'b0;
reg frame_flag_vin = 1'b0;
reg fifo_wr_req = 1'b0;
wire[7:0] rdusedw;
wire[7:0] wrusedw;
always@(posedge vin_clk)
begin
	fifo_afull <= (wrusedw > 8'd245);
end

`ifdef Xilinx
assign data = {pixel0,pixel1,pixel2,pixel3};
`else
assign data = {pixel3,pixel2,pixel1,pixel0};
`endif
lite_fifo#
(
	.COMMON_CLOCK(0),
	.ADDR_WIDTH(8),
	.DATA_WIDTH(64)
)  vin_frame_buffer_ctrl_fifo_m0(
	.aclr(frame_flag),
	.data(data),
	.rdclk(mem_clk),
	.rdreq(wr_burst_data_req),
	.wrclk(vin_clk),
	.wrreq(fifo_wr_req),
	.q(wr_burst_data),
	.rdempty(),
	.rdusedw(rdusedw),
	.wrfull(),
	.wrusedw(wrusedw)); 
		
always@(posedge vin_clk)
begin
	vin_vs_d0 <= vin_vs;
	vin_vs_d1 <= vin_vs_d0;
	frame_flag_vin <= vin_vs_d0 && ~vin_vs_d1;
end

always@(posedge vin_clk)
begin
	if(!rst_n)
		data_cnt <= 12'd0;
	else if(frame_flag_vin)
		data_cnt <= 12'd0;
	else if(vin_de)
		begin
			if(data_cnt == vin_width - 12'd1)
				data_cnt <= 12'd0;
			else
				data_cnt <= data_cnt + 12'd1;
		end
	else
		data_cnt <= data_cnt;
end

always@(posedge vin_clk)
begin
	if(vin_de && (data_cnt[1:0] == 2'd0))
		pixel0 <= vin_data;
	else
		pixel0 <= pixel0;		
end

always@(posedge vin_clk)
begin
	if(vin_de && (data_cnt[1:0] == 2'd1))
		pixel1 <= vin_data;
	else
		pixel1 <= pixel1;		
end

always@(posedge vin_clk)
begin
	if(vin_de && (data_cnt[1:0] == 2'd2))
		pixel2 <= vin_data;
	else
		pixel2 <= pixel2;
end

always@(posedge vin_clk)
begin
	if(vin_de && (data_cnt[1:0] == 2'd3))
		pixel3 <= vin_data;
	else
		pixel3 <= pixel3;
end

always@(posedge vin_clk)
begin
	if(vin_de &&(data_cnt[1:0] == 2'd3 || data_cnt == vin_width - 12'd1))
		fifo_wr_req <= 1'b1;
	else
		fifo_wr_req <= 1'b0;
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		byte_per_line <= 10'd0;
	else if(frame_flag)
		if(vin_width[1:0] == 2'd0)
			byte_per_line <= vin_width[11:2];
		else
			byte_per_line <= vin_width[11:2] + 10'd1;
	else
		byte_per_line <= byte_per_line;
end


wire[26:0] ddr_wr_base;
generate
	if(INTERLACE)

		assign ddr_wr_base = {1'b0,base_addr,frame_addr[1:0],burst_line[9:0],vin_f,8'd0,3'd0};
	else

		assign ddr_wr_base =  {base_addr,frame_addr[1:0],burst_line[10:0],9'd0,3'd0};
endgenerate	
always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)

		wr_burst_addr <= 27'd0;
	else if(burst_state_next == BURST_ONE_LINE_START)
		wr_burst_addr <= ddr_wr_base;
	else if(burst_state_next == BURST_END  && burst_state != BURST_END)
		wr_burst_addr <= wr_burst_addr + {15'd0,BURST_LEN[8:0],3'd0};
	else
		wr_burst_addr <= wr_burst_addr;
end

always@(posedge mem_clk)
begin
	vin_vs_mem_clk_d0 <= vin_vs;
	vin_vs_mem_clk_d1 <= vin_vs_mem_clk_d0;
	frame_flag <= vin_vs_mem_clk_d0 && ~vin_vs_mem_clk_d1;
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		burst_state <= BURST_IDLE;
	else if(frame_flag)
		burst_state <= BURST_IDLE;
	else
		burst_state <= burst_state_next;
end
always@(*)
begin
	case(burst_state)
		BURST_IDLE:
			if(rdusedw > BURST_LEN[7:0])
				burst_state_next <= BURST_ONE_LINE_START;
			else
				burst_state_next <= BURST_IDLE;
		BURST_ONE_LINE_START:
			burst_state_next <= BURSTING;
		BURSTING:
			if(burst_finish)
				burst_state_next <= BURST_END;
			else
				burst_state_next <= BURSTING;
		BURST_END:
			if(remain_len == 10'd0)
				burst_state_next <= BURST_ONE_LINE_END;
			else if((rdusedw >= BURST_LEN[7:0]) || (remain_len <= BURST_LEN && rdusedw >= remain_len - 10'd1))
				burst_state_next <= BURSTING;
			else
				burst_state_next <= BURST_END;
		BURST_ONE_LINE_END:
			burst_state_next <= BURST_IDLE;
		default:
			burst_state_next <= BURST_IDLE;
	endcase
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		wr_max_line <= 12'd0;
	else if(frame_flag)
		wr_max_line <= burst_line;
	else
		wr_max_line <= wr_max_line;
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		burst_line <= 12'd0;
	else if(frame_flag)
		burst_line <= 12'd0;
	else if(burst_state == BURST_ONE_LINE_END)
		burst_line <= burst_line + 12'd1;
	else
		burst_line <= burst_line;
end
always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		frame_addr <= 2'd0;
	else if(frame_flag && vin_f)

		frame_addr <= frame_addr + 2'd1;
	else
		frame_addr <= frame_addr;
end	


always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		remain_len <= 10'd0;
	else if(burst_state_next == BURST_ONE_LINE_START)
		remain_len <= byte_per_line;
	else if(burst_state_next == BURST_END && burst_state != BURST_END)
		if(remain_len < BURST_LEN)
			remain_len <= 10'd0;
		else
			remain_len <= remain_len - BURST_LEN;	
	else
		remain_len <= remain_len;
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		wr_burst_len <= 10'd0;
	else if(burst_state_next == BURSTING && burst_state != BURSTING)
		if(remain_len > BURST_LEN)
			wr_burst_len <= BURST_LEN;
		else
			wr_burst_len <= remain_len;
	else
		wr_burst_len <=  wr_burst_len;
end

always@(posedge mem_clk or negedge rst_n)
begin
	if(!rst_n)
		wr_burst_req <= 1'd0;
	else if(burst_state_next == BURSTING && burst_state != BURSTING)
		wr_burst_req <= 1'b1;
	else if(burst_finish  || wr_burst_data_req || burst_state == BURST_IDLE)
		wr_burst_req <= 1'b0;
	else
		wr_burst_req <= wr_burst_req;
end

endmodule