data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/core_top.v
1: b"%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/core_top.v:31: Cannot find file containing module: 'core'\ncore CPU0\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/core\n             data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/core.v\n             data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/core.sv\n             core\n             core.v\n             core.sv\n             obj_dir/core\n             obj_dir/core.v\n             obj_dir/core.sv\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/core_top.v:40: Cannot find file containing module: 'mmu'\nmmu MMU0\n^~~\n%Error: Exiting due to 2 error(s)\n"
module core_top
(
  input wire 	      clk, 
  input wire 	      resetb,




  output wire [7:0]  io_addr,
  output wire 	      io_en, 
  output wire 	      io_we, 
  input wire [31:0]  io_data_read, 
  output wire [31:0] io_data_write,
  input wire irq_mtimecmp


);

wire 	      dm_we;
wire [31:0] 	      im_addr;
wire [31:0] 	      im_do;
wire [31:0] 	      dm_addr;
wire [31:0] 	      dm_di;
wire [31:0] 	      dm_do;
wire [3:0] 	      dm_be;
wire 	      dm_is_signed;

core CPU0
(
  .clk(clk), .resetb(resetb),
  .dm_we(dm_we), .im_addr(im_addr), .im_do(im_do),
  .dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
  .dm_be(dm_be), .dm_is_signed(dm_is_signed),
  .irq_mtimecmp(irq_mtimecmp)
);

mmu MMU0
(
  .clk(clk), .resetb(resetb),
  .dm_we(dm_we),
  .im_addr(im_addr), .im_do(im_do),
  .dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
  .dm_be(dm_be), .is_signed(dm_is_signed),


  .io_addr(io_addr), .io_en(io_en), .io_we(io_we),
  .io_data_read(io_data_read), .io_data_write(io_data_write)
);


endmodule
module core_top
(
  input wire 	      clk, 
  input wire 	      resetb,




  output wire [7:0]  io_addr,
  output wire 	      io_en, 
  output wire 	      io_we, 
  input wire [31:0]  io_data_read, 
  output wire [31:0] io_data_write,
  input wire irq_mtimecmp


);


wire 	      dm_we;
wire [31:0] 	      im_addr;
wire [31:0] 	      im_do;
wire [31:0] 	      dm_addr;
wire [31:0] 	      dm_di;
wire [31:0] 	      dm_do;
wire [3:0] 	      dm_be;
wire 	      dm_is_signed;

core CPU0
(
  .clk(clk), .resetb(resetb),
  .dm_we(dm_we), .im_addr(im_addr), .im_do(im_do),
  .dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
  .dm_be(dm_be), .dm_is_signed(dm_is_signed),
  .irq_mtimecmp(irq_mtimecmp)
);

mmu MMU0
(
  .clk(clk), .resetb(resetb),
  .dm_we(dm_we),
  .im_addr(im_addr), .im_do(im_do),
  .dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
  .dm_be(dm_be), .is_signed(dm_is_signed),


  .io_addr(io_addr), .io_en(io_en), .io_we(io_we),
  .io_data_read(io_data_read), .io_data_write(io_data_write)
);


endmodule