data/full_repos/permissive/127284262/Decoder.v
data/verilator_xmls/2933dd62-62f6-4256-b1ac-0d60c93b1d7c.xml
module Decoder(	input	[3:0] a,
				output	reg [6:0] d);
    
	always@(*)
		case (a)

			4'b0001: d = 7'b1111001;
			4'b0010: d = 7'b0100100;
			4'b0011: d = 7'b0110000;
			4'b0100: d = 7'b0011001;
			4'b0101: d = 7'b0010010;
			4'b0110: d = 7'b0000010;
			4'b0111: d = 7'b1111000;
			4'b1000: d = 7'b0000000;
			4'b1001: d = 7'b0010000;
			4'b1010: d = 7'b0001000;
			4'b1011: d = 7'b0000011;
			4'b1100: d = 7'b1000110;
			4'b1101: d = 7'b0100001;
			4'b1110: d = 7'b0000110;
			4'b1111: d = 7'b0001110;
			default: d = 7'b1000000;

		endcase
endmodule
module Decoder(	input	[3:0] a,
				output	reg [6:0] d);

    
	always@(*)
		case (a)

			4'b0001: d = 7'b1111001;
			4'b0010: d = 7'b0100100;
			4'b0011: d = 7'b0110000;
			4'b0100: d = 7'b0011001;
			4'b0101: d = 7'b0010010;
			4'b0110: d = 7'b0000010;
			4'b0111: d = 7'b1111000;
			4'b1000: d = 7'b0000000;
			4'b1001: d = 7'b0010000;
			4'b1010: d = 7'b0001000;
			4'b1011: d = 7'b0000011;
			4'b1100: d = 7'b1000110;
			4'b1101: d = 7'b0100001;
			4'b1110: d = 7'b0000110;
			4'b1111: d = 7'b0001110;
			default: d = 7'b1000000;

		endcase
endmodule