data/full_repos/permissive/210737016/wam_gen.v
1: b'%Error: data/full_repos/permissive/210737016/wam_gen.v:48: Cannot find file containing module: \'wam_par\'\n    wam_par par( .hrdn(hrdn), .age(age), .rto(rto) );\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_par\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_par.v\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_par.sv\n             wam_par\n             wam_par.v\n             wam_par.sv\n             obj_dir/wam_par\n             obj_dir/wam_par.v\n             obj_dir/wam_par.sv\n%Warning-WIDTH: data/full_repos/permissive/210737016/wam_gen.v:84: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'j\' generates 3 bits.\n                                                                 : ... In instance wam_gen\n                            if (j==i) begin                          \n                                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module wam_rdn(
    input wire clk,
    input wire load,
    input wire [7:0] seed,
    output reg [7:0] num
    );

    always @( posedge clk or posedge load ) begin
        if(load)
            num <= seed;
        else begin
            num[0] <= num[7];
            num[1] <= num[0];
            num[2] <= num[1];
            num[3] <= num[2];
            num[4] <= num[3]^num[7];
            num[5] <= num[4]^num[7];
            num[6] <= num[5]^num[7];
            num[7] <= num[6];
        end
    end
endmodule
module wam_rdn(
    input wire clk,
    input wire load,
    input wire [7:0] seed,
    output reg [7:0] num
    );


    always @( posedge clk or posedge load ) begin
        if(load)
            num <= seed;
        else begin
            num[0] <= num[7];
            num[1] <= num[0];
            num[2] <= num[1];
            num[3] <= num[2];
            num[4] <= num[3]^num[7];
            num[5] <= num[4]^num[7];
            num[6] <= num[5]^num[7];
            num[7] <= num[6];
        end
    end
endmodule