data/full_repos/permissive/114811571/test/samples/single_wire/single_wire.v
data/verilator_xmls/33f21431-0ab9-4e51-9194-7826dc8ab4c1.xml
module single_wire(in0, in1, out);
   input wire in0;
   input wire in1;
   output wire out;

   assign out = in0 & in1;
   
   
endmodule
module single_wire(in0, in1, out);

   input wire in0;
   input wire in1;
   output wire out;

   assign out = in0 & in1;
   
   
endmodule