data/full_repos/permissive/136510272/projects/atmega/icarus.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/atmega/icarus.v:60: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk         = ~clk;       \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/atmega/icarus.v:61: Unsupported: Ignoring delay on this delayed statement.\nalways #2   clock_25    = ~clock_25;  \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/atmega/icarus.v:62: Unsupported: Ignoring delay on this delayed statement.\nalways #4   clock_12    = ~clock_12;  \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/atmega/icarus.v:63: Unsupported: Ignoring delay on this delayed statement.\nalways #8   clock_6     = ~clock_6;   \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/atmega/icarus.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #2000 $finish;\n  ^\n%Error: data/full_repos/permissive/136510272/projects/atmega/icarus.v:81: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("icarus_result.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/atmega/icarus.v:82: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, main);\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;





reg clk;
reg clock_25;
reg clock_12;
reg clock_6;


reg [3:0]   led;
reg [1:0]   keys;


reg         adc_clock_20mhz;
reg [7:0]   adc_input;


reg        sdram_clock;
reg [11:0] sdram_addr;
reg [1:0]  sdram_bank;
reg [15:0] sdram_dq;
reg        sdram_ldqm;
reg        sdram_udqm;
reg        sdram_ras;
reg        sdram_cas;
reg        sdram_we;
    

reg [4:0]  vga_red;
reg [5:0]  vga_green;
reg [4:0]  vga_blue;
reg        vga_hs;
reg        vga_vs;


reg        ftdi_rx;
reg        ftdi_tx;




reg [1:0]  usb;


reg        sound_left;
reg        sound_right;


reg [1:0]  ps2_keyb;
reg [1:0]  ps2_mouse;


always #0.5 clk         = ~clk;
always #2   clock_25    = ~clock_25;
always #4   clock_12    = ~clock_12;
always #8   clock_6     = ~clock_6;


initial begin

  clk      = 1;
  clock_25 = 0;
  clock_12 = 0;
  clock_6  = 0;
  #2000 $finish;

end 



initial
begin

    $dumpfile("icarus_result.vcd");
    $dumpvars(0, main);

end

wire CLK_I = clock_25;
wire RST_I = 1'b0;


wire [13:0] ROM_A;


wire [21:0] ADR_O;


reg  [15:0] ROM_I;
reg  [15:0] DAT_I;
wire [15:0] DAT_O;





core ACORE(

    CLK_I,
    RST_I,
    ROM_A,
    ROM_I, 
    ADR_O,
    DAT_I, 
    DAT_O, 
    WE_O
    
);




reg [15:0] ram_8m [65535 : 0];
reg [15:0] rom_32k [32767 : 0];
reg [15:0] t_DAT_I;

integer j;
initial begin

    $readmemh("core.hex", rom_32k);
    
    ram_8m[ 16'h00 ] = 16'h1234;
    ram_8m[ 16'h01 ] = 16'h2345;
    ram_8m[ 16'h80 ] = 16'hAFBF;
    ram_8m[ 16'h81 ] = 16'h2345;

end

always @(posedge clk) begin

      ROM_I <= rom_32k[ ROM_A ];         
    t_DAT_I <= ram_8m[ ADR_O[21:1] ];
      DAT_I <= t_DAT_I;

end

endmodule
module main;






reg clk;
reg clock_25;
reg clock_12;
reg clock_6;


reg [3:0]   led;
reg [1:0]   keys;


reg         adc_clock_20mhz;
reg [7:0]   adc_input;


reg        sdram_clock;
reg [11:0] sdram_addr;
reg [1:0]  sdram_bank;
reg [15:0] sdram_dq;
reg        sdram_ldqm;
reg        sdram_udqm;
reg        sdram_ras;
reg        sdram_cas;
reg        sdram_we;
    

reg [4:0]  vga_red;
reg [5:0]  vga_green;
reg [4:0]  vga_blue;
reg        vga_hs;
reg        vga_vs;


reg        ftdi_rx;
reg        ftdi_tx;




reg [1:0]  usb;


reg        sound_left;
reg        sound_right;


reg [1:0]  ps2_keyb;
reg [1:0]  ps2_mouse;


always #0.5 clk         = ~clk;
always #2   clock_25    = ~clock_25;
always #4   clock_12    = ~clock_12;
always #8   clock_6     = ~clock_6;


initial begin

  clk      = 1;
  clock_25 = 0;
  clock_12 = 0;
  clock_6  = 0;
  #2000 $finish;

end 



initial
begin

    $dumpfile("icarus_result.vcd");
    $dumpvars(0, main);

end

wire CLK_I = clock_25;
wire RST_I = 1'b0;


wire [13:0] ROM_A;


wire [21:0] ADR_O;


reg  [15:0] ROM_I;
reg  [15:0] DAT_I;
wire [15:0] DAT_O;





core ACORE(

    CLK_I,
    RST_I,
    ROM_A,
    ROM_I, 
    ADR_O,
    DAT_I, 
    DAT_O, 
    WE_O
    
);




reg [15:0] ram_8m [65535 : 0];
reg [15:0] rom_32k [32767 : 0];
reg [15:0] t_DAT_I;

integer j;
initial begin

    $readmemh("core.hex", rom_32k);
    
    ram_8m[ 16'h00 ] = 16'h1234;
    ram_8m[ 16'h01 ] = 16'h2345;
    ram_8m[ 16'h80 ] = 16'hAFBF;
    ram_8m[ 16'h81 ] = 16'h2345;

end

always @(posedge clk) begin

      ROM_I <= rom_32k[ ROM_A ];         
    t_DAT_I <= ram_8m[ ADR_O[21:1] ];
      DAT_I <= t_DAT_I;

end

endmodule