data/full_repos/permissive/175808891/verilog/rv32cpu.v
1: b"%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:234: syntax error, unexpected type\n    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));\n                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:285: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\nmodule shifter(input[31:0] a, input [4:0] shamt, input[1:0] type,  output [31:0] r);\n                                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:288: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:343: syntax error, unexpected ',', expecting IDENTIFIER or do or final\n input   wire            int,\n                            ^\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:345: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input   wire            nmi\n ^~~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:369: syntax error, unexpected always\nalways @(posedge clk or posedge rst)\n^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module PCUnit (
	input	wire				clk,
	input	wire				rst,
	input	wire 	[31:0]		TA,
	input	wire 	[31:0]		Imm,
	output	reg		[31:0]		PC,
	output	wire	[31:0]		ftPC,
	output	wire	[31:0]		iPC,
	input	wire				load,
	input	wire	[1:0]		sel			
);

	wire [31:0]	nPC;
	assign	nPC		=	sel[1] ? iPC : TA;
	assign 	ftPC	= 	PC + (sel[1] ? 32'h2 : 32'h4);
	assign 	iPC		=	PC + Imm;

	always @ (posedge clk or posedge rst)
	if(rst)	
		PC <= 32'b0;
	else if(load)
		case (sel[0])
			1'b0	:	PC <= ftPC;
			2'b1	:	PC <= nPC; 
		endcase
endmodule
module PCUnit (
	input	wire				clk,
	input	wire				rst,
	input	wire 	[31:0]		TA,
	input	wire 	[31:0]		Imm,
	output	reg		[31:0]		PC,
	output	wire	[31:0]		ftPC,
	output	wire	[31:0]		iPC,
	input	wire				load,
	input	wire	[1:0]		sel			
);


	wire [31:0]	nPC;
	assign	nPC		=	sel[1] ? iPC : TA;
	assign 	ftPC	= 	PC + (sel[1] ? 32'h2 : 32'h4);
	assign 	iPC		=	PC + Imm;

	always @ (posedge clk or posedge rst)
	if(rst)	
		PC <= 32'b0;
	else if(load)
		case (sel[0])
			1'b0	:	PC <= ftPC;
			2'b1	:	PC <= nPC; 
		endcase
endmodule