data/full_repos/permissive/123690745/GRF.v
data/verilator_xmls/ad0cbaf7-b488-40fb-ad91-d3c2ec45f5fa.xml
module GRF(
    input [4:0] A1,
    input [4:0] A2,
    input [4:0] A3,
    input [31:0] WD,

	 input [31:0] InstrW,
	 input Clr,
	 input Clk,
    output [31:0] RD1,
    output [31:0] RD2,
    input WE,
	 input [31:0] PCW
    );
	 
	reg [31:0] Registers [31:0];
	assign RD1 = Registers[A1];
	assign RD2 = Registers[A2];
	integer i;
	initial begin
		for (i = 0;i<32;i=i+1) begin
			Registers[i] = 0;
		end
	end
	always @(posedge Clk) begin
		if (Clr) begin
			for (i = 0;i<32;i=i+1) begin
				Registers[i] = 0;

			end
		end
		else begin
			if (WE) begin
				Registers[A3] = WD;

				$display("$%d <= %h",A3,WD);


				
			end
		end
		Registers[0] = 0;
		for (i = 0;i<32;i=i+1) begin

		end
	end
endmodule
module GRF(
    input [4:0] A1,
    input [4:0] A2,
    input [4:0] A3,
    input [31:0] WD,

	 input [31:0] InstrW,
	 input Clr,
	 input Clk,
    output [31:0] RD1,
    output [31:0] RD2,
    input WE,
	 input [31:0] PCW
    );

	 
	reg [31:0] Registers [31:0];
	assign RD1 = Registers[A1];
	assign RD2 = Registers[A2];
	integer i;
	initial begin
		for (i = 0;i<32;i=i+1) begin
			Registers[i] = 0;
		end
	end
	always @(posedge Clk) begin
		if (Clr) begin
			for (i = 0;i<32;i=i+1) begin
				Registers[i] = 0;

			end
		end
		else begin
			if (WE) begin
				Registers[A3] = WD;

				$display("$%d <= %h",A3,WD);


				
			end
		end
		Registers[0] = 0;
		for (i = 0;i<32;i=i+1) begin

		end
	end
endmodule