data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/wishbone_bus.v
 line:53: before: "["
1: b'%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/wishbone_bus.v:70: Cannot find file containing module: \'wishbone_bus_selector\'\nwishbone_bus_selector selector(\n^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/wishbone_bus_selector\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/wishbone_bus_selector.v\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/wishbone_bus_selector.sv\n             wishbone_bus_selector\n             wishbone_bus_selector.v\n             wishbone_bus_selector.sv\n             obj_dir/wishbone_bus_selector\n             obj_dir/wishbone_bus_selector.v\n             obj_dir/wishbone_bus_selector.sv\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/wishbone_bus.v:110: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                          : ... In instance wishbone_bus\n    assign wb_sel_s[i] = (current_slave == i) ? wb_sel_m : 3\'b0;\n                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module wishbone_bus 
#( parameter SLAVES=1)
 (
    input logic         sysClk,
    input logic         sysRst, 

    

    output logic        wb_clk_m,
    output logic        wb_rst_m,
    output logic        wb_ack_m,
    output logic        wb_err_m,
    output logic        wb_stall_m,
    input  logic        wb_cyc_m,
    input  logic        wb_stb_m,
    output logic [31:0] wb_dat_i_m,
    input  logic        wb_we_m,
    input  logic [3:0]  wb_sel_m,
    input  logic [31:0] wb_adr_m,
    input  logic [31:0] wb_dat_o_m,

    

    output logic        wb_clk_s   [SLAVES-1:0],
    output logic        wb_rst_s   [SLAVES-1:0],
    output logic        wb_cyc_s   [SLAVES-1:0],
    output logic        wb_stb_s   [SLAVES-1:0],
    output logic        wb_we_s    [SLAVES-1:0],
    output logic [3:0]  wb_sel_s   [SLAVES-1:0],
    output logic [31:0] wb_dat_i_s [SLAVES-1:0],
    output logic [31:0] wb_adr_s   [SLAVES-1:0],
    input  logic        wb_ack_s   [SLAVES-1:0],
    input  logic        wb_err_s   [SLAVES-1:0],
    input  logic        wb_stall_s [SLAVES-1:0],
    input  logic [31:0] wb_dat_o_s [SLAVES-1:0]

);

logic [31:0] current_slave;

wishbone_bus_selector selector(
    .address(wb_adr_m),
    .slave(current_slave)
);

genvar i; 




assign wb_clk_m = sysClk;
assign wb_rst_m = sysRst;

generate        
for (i = 0; i < SLAVES; i=i+1) begin      
  assign wb_clk_s[i] = sysClk;
  assign wb_rst_s[i] = sysRst;
end;
endgenerate





generate        
for (i = 0; i < SLAVES; i=i+1) begin      
  assign wb_adr_s[i]   = wb_adr_m;
  assign wb_dat_i_s[i] = wb_dat_o_m;
end;
endgenerate 





generate
for (i = 0; i < SLAVES; i=i+1) begin
    assign wb_cyc_s[i] = (current_slave == i) ? wb_cyc_m : 1'b0;
    assign wb_stb_s[i] = (current_slave == i) ? wb_stb_m : 1'b0;
    assign wb_we_s[i]  = (current_slave == i) ? wb_we_m  : 1'b0;
    assign wb_sel_s[i] = (current_slave == i) ? wb_sel_m : 3'b0;
end;
endgenerate





assign wb_dat_i_m = (current_slave == SLAVES && wb_we_m == 1'b1)? 32'b0 :
                                                wb_dat_o_s[current_slave];              
assign wb_ack_m   = (current_slave == SLAVES) ? 1'b0 :
                                                wb_ack_s[current_slave];
assign wb_err_m   = (current_slave == SLAVES) ? 1'b0 :
                                                wb_err_s[current_slave];
assign wb_stall_m = (current_slave == SLAVES) ? 1'b0 : 
                                                wb_stall_s[current_slave];


endmodule
module wishbone_bus 
#( parameter SLAVES=1)
 (
    input logic         sysClk,
    input logic         sysRst, 

    

    output logic        wb_clk_m,
    output logic        wb_rst_m,
    output logic        wb_ack_m,
    output logic        wb_err_m,
    output logic        wb_stall_m,
    input  logic        wb_cyc_m,
    input  logic        wb_stb_m,
    output logic [31:0] wb_dat_i_m,
    input  logic        wb_we_m,
    input  logic [3:0]  wb_sel_m,
    input  logic [31:0] wb_adr_m,
    input  logic [31:0] wb_dat_o_m,

    

    output logic        wb_clk_s   [SLAVES-1:0],
    output logic        wb_rst_s   [SLAVES-1:0],
    output logic        wb_cyc_s   [SLAVES-1:0],
    output logic        wb_stb_s   [SLAVES-1:0],
    output logic        wb_we_s    [SLAVES-1:0],
    output logic [3:0]  wb_sel_s   [SLAVES-1:0],
    output logic [31:0] wb_dat_i_s [SLAVES-1:0],
    output logic [31:0] wb_adr_s   [SLAVES-1:0],
    input  logic        wb_ack_s   [SLAVES-1:0],
    input  logic        wb_err_s   [SLAVES-1:0],
    input  logic        wb_stall_s [SLAVES-1:0],
    input  logic [31:0] wb_dat_o_s [SLAVES-1:0]

);


logic [31:0] current_slave;

wishbone_bus_selector selector(
    .address(wb_adr_m),
    .slave(current_slave)
);

genvar i; 




assign wb_clk_m = sysClk;
assign wb_rst_m = sysRst;

generate        
for (i = 0; i < SLAVES; i=i+1) begin      
  assign wb_clk_s[i] = sysClk;
  assign wb_rst_s[i] = sysRst;
end;
endgenerate





generate        
for (i = 0; i < SLAVES; i=i+1) begin      
  assign wb_adr_s[i]   = wb_adr_m;
  assign wb_dat_i_s[i] = wb_dat_o_m;
end;
endgenerate 





generate
for (i = 0; i < SLAVES; i=i+1) begin
    assign wb_cyc_s[i] = (current_slave == i) ? wb_cyc_m : 1'b0;
    assign wb_stb_s[i] = (current_slave == i) ? wb_stb_m : 1'b0;
    assign wb_we_s[i]  = (current_slave == i) ? wb_we_m  : 1'b0;
    assign wb_sel_s[i] = (current_slave == i) ? wb_sel_m : 3'b0;
end;
endgenerate





assign wb_dat_i_m = (current_slave == SLAVES && wb_we_m == 1'b1)? 32'b0 :
                                                wb_dat_o_s[current_slave];              
assign wb_ack_m   = (current_slave == SLAVES) ? 1'b0 :
                                                wb_ack_s[current_slave];
assign wb_err_m   = (current_slave == SLAVES) ? 1'b0 :
                                                wb_err_s[current_slave];
assign wb_stall_m = (current_slave == SLAVES) ? 1'b0 : 
                                                wb_stall_s[current_slave];


endmodule