data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n   always #5  clk_x <= ~clk_x;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n   always #5  clk_b <= ~clk_b;\n          ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:73: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile ("vcd/correlator_tb.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:74: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n      #35 rst <= 1; #40 rst <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n      #35 rst <= 1; #40 rst <= 0;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n      #40 set <= 1; num <= 1; val <= COUNT; ptr <= 11\'h701;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n      while (!fin) #10;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n      #40  en <= 1; strobe <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n      while (!sw) #10;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n      while (sw) #10;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n      #80 get <= 1; dev <= 3\'h0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n      while (!fin) #10;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n      while (!sw) #10;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n      while (!wrap_cnt) #10;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n      #10 en <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n      #80 get <= 1; dev <= 3\'h0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n      while (!fin) #10;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n      #80 get <= 1; dev <= 3\'h6;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n      while (!fin) #10;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n      #80 $display("\\n%8t: Simulation finished:", $time);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/correlator/tart_visibilities_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n      #12000 $display ("TIMEOUT!");\n      ^\n%Error: Exiting due to 2 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tart_visibilities_tb;

   parameter BLOCK = 32;
   parameter MSB   = BLOCK-1;
   parameter MRATE = 12;
   parameter DELAY = 3;
   parameter COUNT = 4;

   wire [MSB:0] dat_c, val_c, blocksize;
   wire [9:0]   adr_c;
   wire [7:0]   dat;
   reg          clk_x = 1, clk_b = 1, rst = 0, en = 0;
   reg          cyc = 0, stb = 0, we = 0, bst = 0;
   reg [11:0]   adr;
   reg [7:0]    val;
   reg          set = 0, get = 0, fin = 0, sw = 0;
   reg [2:0]    dev = 0;
   wire         ack;
   wire         cyc_c, stb_c, we_c, bst_c, ack_c;



   always #5  clk_x <= ~clk_x;
   always #5  clk_b <= ~clk_b;





   integer      num = 0;
   integer      ptr = 0;
   initial begin : SIM_BLOCK
      $dumpfile ("vcd/correlator_tb.vcd");
      $dumpvars;


      $display("\n%8t: Issuing reset:\n", $time);
      #35 rst <= 1; #40 rst <= 0;


      $display("\n%8t: Setting up the block-size:", $time);
      #40 set <= 1; num <= 1; val <= COUNT; ptr <= 11'h701;
      while (!fin) #10;


      $display("%8t: Beginning data-correlation (bank 0):", $time);
      #40  en <= 1; strobe <= 1;
      while (!sw) #10;


      $display("%8t: Switching banks (bank 1):", $time);
      while (sw) #10;
      $display("%8t: Reading back visibilities (bank 0):", $time);
      #80 get <= 1; dev <= 3'h0;
      while (!fin) #10;


      while (!sw) #10;
      $display("\n%8t: Stopping data-correlation (bank 1):", $time);
      while (!wrap_cnt) #10;
      #10 en <= 0;


      $display("%8t: Reading back visibilities (bank 1):", $time);
      #80 get <= 1; dev <= 3'h0;
      while (!fin) #10;


      $display("\n%8t: Reading back counts (bank 1):", $time);
      #80 get <= 1; dev <= 3'h6;
      while (!fin) #10;


      #80 $display("\n%8t: Simulation finished:", $time);
      $finish;
   end

   initial begin : SIM_FAILED
      #12000 $display ("TIMEOUT!");
      $finish;
   end




   reg [23:0] antenna;
   reg [3:0]  cnt = 0;
   reg        strobe = 0;
   wire [3:0] next_cnt = wrap_cnt ? 0 : cnt + 1 ;
   wire       wrap_cnt = cnt == MRATE-1;

   always @(posedge clk_x)
     if (rst) cnt <= #DELAY 0;
     else     cnt <= #DELAY en ? next_cnt : cnt;

   always @(posedge clk_x)
     if (rst) strobe <= #DELAY 0;
     else     strobe <= #DELAY en && wrap_cnt;

   initial antenna <= #DELAY $random;
   always @(posedge clk_x)
     if (!rst && en && wrap_cnt)
       antenna <= #DELAY $random;

   reg        sw_wait = 0;
   always @(posedge clk_b)
     if (rst) {sw, sw_wait} <= #DELAY 0;
     else if (!sw && !sw_wait && available) {sw, sw_wait} <= #DELAY 3;
     else if (sw && sw_wait && available) sw <= #DELAY 0;
     else if (sw_wait && !available) sw_wait <= #DELAY 0;




   wire       bst_w = num > 2 && cyc;

   always @(posedge clk)
     if (rst) bst <= #DELAY 0;
     else     bst <= #DELAY bst_w || (set || get) && num > 1;

   always @(posedge clk_b)
     if (rst) bst <= #DELAY 0;
     else     bst <= #DELAY bst_w;

   always @(posedge clk_b)
     if (rst) begin
        {fin, get, set} <= #DELAY 0;
        {cyc, stb, we } <= #DELAY 0;
     end
     else if (set) begin
        $display("%8t: write beginning (num = %1d)", $time, num);
        {fin, get, set} <= #DELAY 0;
        {cyc, stb, we } <= #DELAY 7;
     end
     else if (get) begin
        $display("%8t: read beginning (num = %1d)", $time, num);
        {fin, get, set} <= #DELAY 0;
        {cyc, stb, we } <= #DELAY 6;
     end
     else if (cyc) begin
        if (!stb && ack) $display("%8t: transfer ending", $time);
        {fin, get, set} <= #DELAY {!stb && ack, get, set};
        {cyc, stb, we } <= #DELAY {stb || !ack, bst, we && (stb || !ack)};
     end
     else begin
        {fin, get, set} <= #DELAY 0;
        {cyc, stb, we } <= #DELAY 0;
     end

   wire [ASB:0] next_adr = bst ? adr + 1 : adr;

   always @(posedge clk)
     if (rst)             adr <= #DELAY 0;
     else if (set || get) adr <= #DELAY ptr;
     else if (cyc)        adr <= #DELAY next_adr;

   always @(posedge clk)
     if (cyc && stb) num <= #DELAY num - 1;



   reg [10:0]  adr_r;
   reg [5:0]   ci;
   reg [4:0]   ri;

   always @(posedge clk_b)
     begin
        adr_r <= adr;
        {ci, ri} <= adr_r;
        if (cyc && stb && !we && ack)
          $display("%8t: Vis = %08x (c: %02x, r:%02x)", $time, dat, ci, ri);
     end





   tart_visibilities
     #(  .BLOCK (BLOCK),
         .COUNT (24),
         .MRATE (MRATE),
         .DELAY (DELAY)
         ) TART_VISIBILITIES0
       ( .clk_i(clk_b),
         .rst_i(rst),

         .cyc_i(cyc),
         .stb_i(stb),
         .we_i (we),
         .bst_i(bst),
         .ack_o(ack),
         .adr_i(adr),
         .byt_i(val),
         .byt_o(dat),

         .cyc_o(cyc_c),
         .stb_o(stb_c),
         .we_o (we_c ),
         .bst_o(bst_c),
         .ack_i(ack_c),
         .adr_o(adr_c),
         .dat_i(val_c),
         .dat_o(dat_c),

         .switching(switching),
         .blocksize(blocksize),
         .available(available)
         );

   wb_sram #( .WIDTH(32), .SBITS(10) ) SRAM0
     ( .clk_i(clk),
       .rst_i(rst),
       .cyc_i(cyc),
       .stb_i(stb),
       .we_i (we),
       .bst_i(bst),
       .ack_o(ack),
       .adr_i(adr),
       .dat_i(val),
       .dat_o(dat)
       );


endmodule
module tart_visibilities_tb;


   parameter BLOCK = 32;
   parameter MSB   = BLOCK-1;
   parameter MRATE = 12;
   parameter DELAY = 3;
   parameter COUNT = 4;

   wire [MSB:0] dat_c, val_c, blocksize;
   wire [9:0]   adr_c;
   wire [7:0]   dat;
   reg          clk_x = 1, clk_b = 1, rst = 0, en = 0;
   reg          cyc = 0, stb = 0, we = 0, bst = 0;
   reg [11:0]   adr;
   reg [7:0]    val;
   reg          set = 0, get = 0, fin = 0, sw = 0;
   reg [2:0]    dev = 0;
   wire         ack;
   wire         cyc_c, stb_c, we_c, bst_c, ack_c;



   always #5  clk_x <= ~clk_x;
   always #5  clk_b <= ~clk_b;





   integer      num = 0;
   integer      ptr = 0;
   initial begin : SIM_BLOCK
      $dumpfile ("vcd/correlator_tb.vcd");
      $dumpvars;


      $display("\n%8t: Issuing reset:\n", $time);
      #35 rst <= 1; #40 rst <= 0;


      $display("\n%8t: Setting up the block-size:", $time);
      #40 set <= 1; num <= 1; val <= COUNT; ptr <= 11'h701;
      while (!fin) #10;


      $display("%8t: Beginning data-correlation (bank 0):", $time);
      #40  en <= 1; strobe <= 1;
      while (!sw) #10;


      $display("%8t: Switching banks (bank 1):", $time);
      while (sw) #10;
      $display("%8t: Reading back visibilities (bank 0):", $time);
      #80 get <= 1; dev <= 3'h0;
      while (!fin) #10;


      while (!sw) #10;
      $display("\n%8t: Stopping data-correlation (bank 1):", $time);
      while (!wrap_cnt) #10;
      #10 en <= 0;


      $display("%8t: Reading back visibilities (bank 1):", $time);
      #80 get <= 1; dev <= 3'h0;
      while (!fin) #10;


      $display("\n%8t: Reading back counts (bank 1):", $time);
      #80 get <= 1; dev <= 3'h6;
      while (!fin) #10;


      #80 $display("\n%8t: Simulation finished:", $time);
      $finish;
   end

   initial begin : SIM_FAILED
      #12000 $display ("TIMEOUT!");
      $finish;
   end




   reg [23:0] antenna;
   reg [3:0]  cnt = 0;
   reg        strobe = 0;
   wire [3:0] next_cnt = wrap_cnt ? 0 : cnt + 1 ;
   wire       wrap_cnt = cnt == MRATE-1;

   always @(posedge clk_x)
     if (rst) cnt <= #DELAY 0;
     else     cnt <= #DELAY en ? next_cnt : cnt;

   always @(posedge clk_x)
     if (rst) strobe <= #DELAY 0;
     else     strobe <= #DELAY en && wrap_cnt;

   initial antenna <= #DELAY $random;
   always @(posedge clk_x)
     if (!rst && en && wrap_cnt)
       antenna <= #DELAY $random;

   reg        sw_wait = 0;
   always @(posedge clk_b)
     if (rst) {sw, sw_wait} <= #DELAY 0;
     else if (!sw && !sw_wait && available) {sw, sw_wait} <= #DELAY 3;
     else if (sw && sw_wait && available) sw <= #DELAY 0;
     else if (sw_wait && !available) sw_wait <= #DELAY 0;




   wire       bst_w = num > 2 && cyc;

   always @(posedge clk)
     if (rst) bst <= #DELAY 0;
     else     bst <= #DELAY bst_w || (set || get) && num > 1;

   always @(posedge clk_b)
     if (rst) bst <= #DELAY 0;
     else     bst <= #DELAY bst_w;

   always @(posedge clk_b)
     if (rst) begin
        {fin, get, set} <= #DELAY 0;
        {cyc, stb, we } <= #DELAY 0;
     end
     else if (set) begin
        $display("%8t: write beginning (num = %1d)", $time, num);
        {fin, get, set} <= #DELAY 0;
        {cyc, stb, we } <= #DELAY 7;
     end
     else if (get) begin
        $display("%8t: read beginning (num = %1d)", $time, num);
        {fin, get, set} <= #DELAY 0;
        {cyc, stb, we } <= #DELAY 6;
     end
     else if (cyc) begin
        if (!stb && ack) $display("%8t: transfer ending", $time);
        {fin, get, set} <= #DELAY {!stb && ack, get, set};
        {cyc, stb, we } <= #DELAY {stb || !ack, bst, we && (stb || !ack)};
     end
     else begin
        {fin, get, set} <= #DELAY 0;
        {cyc, stb, we } <= #DELAY 0;
     end

   wire [ASB:0] next_adr = bst ? adr + 1 : adr;

   always @(posedge clk)
     if (rst)             adr <= #DELAY 0;
     else if (set || get) adr <= #DELAY ptr;
     else if (cyc)        adr <= #DELAY next_adr;

   always @(posedge clk)
     if (cyc && stb) num <= #DELAY num - 1;



   reg [10:0]  adr_r;
   reg [5:0]   ci;
   reg [4:0]   ri;

   always @(posedge clk_b)
     begin
        adr_r <= adr;
        {ci, ri} <= adr_r;
        if (cyc && stb && !we && ack)
          $display("%8t: Vis = %08x (c: %02x, r:%02x)", $time, dat, ci, ri);
     end





   tart_visibilities
     #(  .BLOCK (BLOCK),
         .COUNT (24),
         .MRATE (MRATE),
         .DELAY (DELAY)
         ) TART_VISIBILITIES0
       ( .clk_i(clk_b),
         .rst_i(rst),

         .cyc_i(cyc),
         .stb_i(stb),
         .we_i (we),
         .bst_i(bst),
         .ack_o(ack),
         .adr_i(adr),
         .byt_i(val),
         .byt_o(dat),

         .cyc_o(cyc_c),
         .stb_o(stb_c),
         .we_o (we_c ),
         .bst_o(bst_c),
         .ack_i(ack_c),
         .adr_o(adr_c),
         .dat_i(val_c),
         .dat_o(dat_c),

         .switching(switching),
         .blocksize(blocksize),
         .available(available)
         );

   wb_sram #( .WIDTH(32), .SBITS(10) ) SRAM0
     ( .clk_i(clk),
       .rst_i(rst),
       .cyc_i(cyc),
       .stb_i(stb),
       .we_i (we),
       .bst_i(bst),
       .ack_o(ack),
       .adr_i(adr),
       .dat_i(val),
       .dat_o(dat)
       );


endmodule