data/full_repos/permissive/156966470/ver/dcrm/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156966470/ver/dcrm/test.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #30000 rst=1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156966470/ver/dcrm/test.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #1000_000;\n        ^\n%Error: data/full_repos/permissive/156966470/ver/dcrm/test.v:49: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test.lxt");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/156966470/ver/dcrm/test.v:50: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/156966470/ver/dcrm/test.v:51: Unsupported or unknown PLI call: $dumpon\n        $dumpon;\n        ^~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

reg clk, rst;

initial begin
    clk = 1'b0;
    forever clk = #12500 ~clk;
end

integer simcnt;

initial begin
    rst = 1'b1;
    #30000 rst=1'b0;
    $display("Reset over: simulation starts");
    for( simcnt=0; simcnt<1000; simcnt=simcnt+1)
        #1000_000;
    $finish;
end

wire signed [7:0] dout;

reg [15:0] cnt;
wire [7:0] din;

always @(posedge clk)
    if( rst ) begin
        cnt <= 0;
    end else begin
        cnt <= cnt + 1;
    end

assign din = cnt[10:5]  + cnt[3:0];


jt49_dcrm2 UUT(
    .clk  ( clk   ),
    .cen  ( 1'b1  ),
    .rst  ( rst   ),
    .din  ( din   ),
    .dout ( dout  )
);

`ifndef NCVERILOG
    initial begin
        $display("DUMP enabled");
        $dumpfile("test.lxt");
        $dumpvars;
        $dumpon;
    end
`else
    initial begin
        $display("NC Verilog: will dump all signals");
        $shm_open("test.shm");
        $shm_probe(UUT,"AS");
    end
`endif

endmodule
module test;


reg clk, rst;

initial begin
    clk = 1'b0;
    forever clk = #12500 ~clk;
end

integer simcnt;

initial begin
    rst = 1'b1;
    #30000 rst=1'b0;
    $display("Reset over: simulation starts");
    for( simcnt=0; simcnt<1000; simcnt=simcnt+1)
        #1000_000;
    $finish;
end

wire signed [7:0] dout;

reg [15:0] cnt;
wire [7:0] din;

always @(posedge clk)
    if( rst ) begin
        cnt <= 0;
    end else begin
        cnt <= cnt + 1;
    end

assign din = cnt[10:5]  + cnt[3:0];


jt49_dcrm2 UUT(
    .clk  ( clk   ),
    .cen  ( 1'b1  ),
    .rst  ( rst   ),
    .din  ( din   ),
    .dout ( dout  )
);

`ifndef NCVERILOG
    initial begin
        $display("DUMP enabled");
        $dumpfile("test.lxt");
        $dumpvars;
        $dumpon;
    end
`else
    initial begin
        $display("NC Verilog: will dump all signals");
        $shm_open("test.shm");
        $shm_probe(UUT,"AS");
    end
`endif

endmodule