data/full_repos/permissive/184108896/pe.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/184108896/pe.v:14: Cannot find include file: params.v\n`include "params.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/184108896,data/full_repos/permissive/184108896/params.v\n             data/full_repos/permissive/184108896,data/full_repos/permissive/184108896/params.v.v\n             data/full_repos/permissive/184108896,data/full_repos/permissive/184108896/params.v.sv\n             params.v\n             params.v.v\n             params.v.sv\n             obj_dir/params.v\n             obj_dir/params.v.v\n             obj_dir/params.v.sv\n%Error: data/full_repos/permissive/184108896/pe.v:30: Define or directive not defined: \'`logB\'\nparameter id = `logB\'b0;\n               ^~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:33: Define or directive not defined: \'`L\'\ninput [`L*`WIDTH-1: 0] in;\n       ^~\n%Error: data/full_repos/permissive/184108896/pe.v:33: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\ninput [`L*`WIDTH-1: 0] in;\n         ^\n%Error: data/full_repos/permissive/184108896/pe.v:33: Define or directive not defined: \'`WIDTH\'\ninput [`L*`WIDTH-1: 0] in;\n          ^~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:34: Define or directive not defined: \'`INSTR_WIDTH\'\ninput [`INSTR_WIDTH-1: 0]  instr_in;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:36: Define or directive not defined: \'`L\'\noutput [`L*`WIDTH-1:0] out;\n        ^~\n%Error: data/full_repos/permissive/184108896/pe.v:36: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\noutput [`L*`WIDTH-1:0] out;\n          ^\n%Error: data/full_repos/permissive/184108896/pe.v:36: Define or directive not defined: \'`WIDTH\'\noutput [`L*`WIDTH-1:0] out;\n           ^~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:38: Define or directive not defined: \'`INSTR_WIDTH\'\noutput [`INSTR_WIDTH-1: 0] instr_out;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:41: Define or directive not defined: \'`INSTR_WIDTH\'\nreg [`INSTR_WIDTH-1: 0] instr_out1;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:42: Define or directive not defined: \'`INSTR_WIDTH\'\nreg [`INSTR_WIDTH-1: 0] instr_out2;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:43: Define or directive not defined: \'`INSTR_WIDTH\'\nreg [`INSTR_WIDTH-1: 0] instr_out3;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:45: Define or directive not defined: \'`OP_WIDTH\'\nwire [`OP_WIDTH-1: 0] command1;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:46: Define or directive not defined: \'`OP_WIDTH\'\nreg [`OP_WIDTH-1: 0] command2;\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:47: Define or directive not defined: \'`OP_WIDTH\'\nreg [`OP_WIDTH-1: 0] command3;\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:49: Define or directive not defined: \'`L\'\nwire [`L*`WIDTH-1: 0] in1;\n      ^~\n%Error: data/full_repos/permissive/184108896/pe.v:49: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nwire [`L*`WIDTH-1: 0] in1;\n        ^\n%Error: data/full_repos/permissive/184108896/pe.v:49: Define or directive not defined: \'`WIDTH\'\nwire [`L*`WIDTH-1: 0] in1;\n         ^~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:50: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1: 0] in2;\n     ^~\n%Error: data/full_repos/permissive/184108896/pe.v:50: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1: 0] in2;\n       ^\n%Error: data/full_repos/permissive/184108896/pe.v:50: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1: 0] in2;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:51: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1: 0] in3;\n     ^~\n%Error: data/full_repos/permissive/184108896/pe.v:51: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1: 0] in3;\n       ^\n%Error: data/full_repos/permissive/184108896/pe.v:51: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1: 0] in3;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:52: Define or directive not defined: \'`L\'\nwire [`L*`WIDTH-1: 0] out0;\n      ^~\n%Error: data/full_repos/permissive/184108896/pe.v:52: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nwire [`L*`WIDTH-1: 0] out0;\n        ^\n%Error: data/full_repos/permissive/184108896/pe.v:52: Define or directive not defined: \'`WIDTH\'\nwire [`L*`WIDTH-1: 0] out0;\n         ^~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:53: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1: 0] d0;\n     ^~\n%Error: data/full_repos/permissive/184108896/pe.v:53: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1: 0] d0;\n       ^\n%Error: data/full_repos/permissive/184108896/pe.v:53: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1: 0] d0;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:54: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1: 0] d1;\n     ^~\n%Error: data/full_repos/permissive/184108896/pe.v:54: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1: 0] d1;\n       ^\n%Error: data/full_repos/permissive/184108896/pe.v:54: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1: 0] d1;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:56: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1: 0] out;\n     ^~\n%Error: data/full_repos/permissive/184108896/pe.v:56: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1: 0] out;\n       ^\n%Error: data/full_repos/permissive/184108896/pe.v:56: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1: 0] out;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:60: Define or directive not defined: \'`ADDR_WIDTH\'\nreg [`ADDR_WIDTH-1: 0] ls0_raddr;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:61: Define or directive not defined: \'`ADDR_WIDTH\'\nreg [`ADDR_WIDTH-1: 0] ls0_waddr;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:62: Define or directive not defined: \'`ADDR_WIDTH\'\nreg [`ADDR_WIDTH-1: 0] ls1_raddr;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:63: Define or directive not defined: \'`ADDR_WIDTH\'\nreg [`ADDR_WIDTH-1: 0] ls1_waddr;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:69: Define or directive not defined: \'`L\'\nwire [`L*`WIDTH-1: 0] ls0_dOut;\n      ^~\n%Error: data/full_repos/permissive/184108896/pe.v:69: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nwire [`L*`WIDTH-1: 0] ls0_dOut;\n        ^\n%Error: data/full_repos/permissive/184108896/pe.v:69: Define or directive not defined: \'`WIDTH\'\nwire [`L*`WIDTH-1: 0] ls0_dOut;\n         ^~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:70: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1: 0] ls0_dIn;\n     ^~\n%Error: data/full_repos/permissive/184108896/pe.v:70: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1: 0] ls0_dIn;\n       ^\n%Error: data/full_repos/permissive/184108896/pe.v:70: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1: 0] ls0_dIn;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/pe.v:71: Define or directive not defined: \'`L\'\nwire [`L*`WIDTH-1: 0] ls1_dOut;\n      ^~\n%Error: data/full_repos/permissive/184108896/pe.v:71: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nwire [`L*`WIDTH-1: 0] ls1_dOut;\n        ^\n%Error: data/full_repos/permissive/184108896/pe.v:71: Define or directive not defined: \'`WIDTH\'\nwire [`L*`WIDTH-1: 0] ls1_dOut;\n         ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module pe(

	reset,
	clk,
	in,
	instr_in,

	out,
	out_valid,
	instr_out
);



parameter id = `logB'b0;

input reset, clk;
input [`L*`WIDTH-1: 0] in;
input [`INSTR_WIDTH-1: 0]  instr_in;

output [`L*`WIDTH-1:0] out;
output out_valid;
output [`INSTR_WIDTH-1: 0] instr_out;


reg [`INSTR_WIDTH-1: 0] instr_out1;
reg [`INSTR_WIDTH-1: 0] instr_out2;
reg [`INSTR_WIDTH-1: 0] instr_out3;

wire [`OP_WIDTH-1: 0] command1;
reg [`OP_WIDTH-1: 0] command2;
reg [`OP_WIDTH-1: 0] command3;

wire [`L*`WIDTH-1: 0] in1;
reg [`L*`WIDTH-1: 0] in2;
reg [`L*`WIDTH-1: 0] in3;
wire [`L*`WIDTH-1: 0] out0;
reg [`L*`WIDTH-1: 0] d0;
reg [`L*`WIDTH-1: 0] d1;

reg [`L*`WIDTH-1: 0] out;
reg out_valid;


reg [`ADDR_WIDTH-1: 0] ls0_raddr;
reg [`ADDR_WIDTH-1: 0] ls0_waddr;
reg [`ADDR_WIDTH-1: 0] ls1_raddr;
reg [`ADDR_WIDTH-1: 0] ls1_waddr;


reg ls0_we;
reg ls1_we;

wire [`L*`WIDTH-1: 0] ls0_dOut;
reg [`L*`WIDTH-1: 0] ls0_dIn;
wire [`L*`WIDTH-1: 0] ls1_dOut;
reg [`L*`WIDTH-1: 0] ls1_dIn;
reg [`ADDR_WIDTH-1: 0] addr0;
wire [`ADDR_WIDTH-1: 0] addr1;

reg [`logL-1: 0] part_select;


always @(posedge clk, posedge reset)
begin
	if (reset == 1'b1)
	begin
		ls0_waddr <= {`ADDR_WIDTH {1'b1}};
		ls1_waddr <= {`ADDR_WIDTH {1'b1}};

		addr0 <= 0;
		ls0_we <= 0;
		ls1_we <= 0;

		in2 <= `L*`WIDTH'b0;
		in3 <= `L*`WIDTH'b0;

		instr_out1 <= {`logB'b0, `IDLE};
		instr_out2 <= {`logB'b0, `IDLE};
		instr_out3 <= {`logB'b0, `IDLE};

		out <= {`L*`WIDTH{1'b1}};
		out_valid <= 1'b0;

	end
	else
	begin



		case(command1)
		`READ0:
		begin
			ls0_waddr <= ls0_waddr + 1'b1;
			ls0_we <= 1'b1;
			ls1_we <= 1'b0;
			ls0_dIn <= in1;
		end
		`READ1:
		begin
			ls1_waddr <= ls1_waddr + 1'b1;
			ls0_we <= 1'b0;
			ls1_we <= 1'b1;
			ls1_dIn <= in1;
		end
		`COMPUTE:
		begin
			ls0_we <= 1'b0;
			ls1_we <= 1'b0;
			addr0 <= addr0 + 1'b1;
			part_select <= instr_in[`OP_WIDTH + `logL - 1: `OP_WIDTH];
			in2 <= in1;
		end
		`FORWARD:
		begin
			ls0_we <= 1'b0;
			ls1_we <= 1'b0;
			in2 <= in1;
		end
		default:
		begin
			ls0_we <= 1'b0;
			ls1_we <= 1'b0;
			in2 <= in1;
		end
		endcase



		case(command2)
		`COMPUTE:
		begin
			d0 <= ls0_dOut;
			d1[1*`WIDTH-1: 0*`WIDTH] <= ls1_dOut[part_select*`WIDTH +: `WIDTH];
			d1[2*`WIDTH-1: 1*`WIDTH] <= ls1_dOut[part_select*`WIDTH +: `WIDTH];
			d1[3*`WIDTH-1: 2*`WIDTH] <= ls1_dOut[part_select*`WIDTH +: `WIDTH];
			d1[4*`WIDTH-1: 3*`WIDTH] <= ls1_dOut[part_select*`WIDTH +: `WIDTH];
			in3 <= in2;
		end
		default:
		begin
			d0 <= `L*`WIDTH'b0;
			d1 <= `L*`WIDTH'b0;
			in3 <= in2;
		end
		endcase




		case(command3)
		`COMPUTE:
		begin
			out <= out0;
			out_valid <= 1'b1;
		end
		`FORWARD:
		begin
			out <= in3;
			out_valid <= 1'b1;
		end
		default:
		begin
			out <= `L*`WIDTH'b0;
			out_valid <= 1'b0;
		end
		endcase
		instr_out1 <= instr_in;
		instr_out2 <= instr_out1;
		instr_out3 <= instr_out2;
		command2 <= command1;
		command3 <= command2;
	end
end


generate
genvar i;
for (i=0; i<`L; i=i+1)
begin: op_array
	op op_inst(
	.in0(in3[(i+1)*`WIDTH-1 : i*`WIDTH]),
	.in1(d0[(i+1)*`WIDTH-1 : i*`WIDTH]),
	.in2(d1[(i+1)*`WIDTH-1 : i*`WIDTH]),
	.out0(out0[(i+1)*`WIDTH-1 : i*`WIDTH]));
end
endgenerate

assign addr1 = instr_in[`INSTR_WIDTH-2: `OP_WIDTH + `logL];
always @(*)
begin
	if (command1 == `COMPUTE)
	begin
		ls0_raddr <= addr0;
		ls1_raddr <= addr1;
	end
	else
	begin
		ls0_raddr <= 0;
		ls1_raddr <= 0;
	end
end
assign instr_out = instr_out3;
assign in1 = in;


local_store #(`B*`B/`L/`B) ls0(
	.clk(clk),
	.we(ls0_we),
	.a_r(ls0_raddr),
	.a_w(ls0_waddr),
	.di(ls0_dIn),
	.dout(ls0_dOut)
);


local_store #(`B*`B/`L/`B) ls1(
	.clk(clk),
	.we(ls1_we),
	.a_r(ls1_raddr),
	.a_w(ls1_waddr),
	.di(ls1_dIn),
	.dout(ls1_dOut)
);



pe_instr_decoder #id pe_instr_decoder_inst(
	.instr_in(instr_in),
	.command(command1)
);
endmodule
module pe(

	reset,
	clk,
	in,
	instr_in,

	out,
	out_valid,
	instr_out
);




parameter id = `logB'b0;

input reset, clk;
input [`L*`WIDTH-1: 0] in;
input [`INSTR_WIDTH-1: 0]  instr_in;

output [`L*`WIDTH-1:0] out;
output out_valid;
output [`INSTR_WIDTH-1: 0] instr_out;


reg [`INSTR_WIDTH-1: 0] instr_out1;
reg [`INSTR_WIDTH-1: 0] instr_out2;
reg [`INSTR_WIDTH-1: 0] instr_out3;

wire [`OP_WIDTH-1: 0] command1;
reg [`OP_WIDTH-1: 0] command2;
reg [`OP_WIDTH-1: 0] command3;

wire [`L*`WIDTH-1: 0] in1;
reg [`L*`WIDTH-1: 0] in2;
reg [`L*`WIDTH-1: 0] in3;
wire [`L*`WIDTH-1: 0] out0;
reg [`L*`WIDTH-1: 0] d0;
reg [`L*`WIDTH-1: 0] d1;

reg [`L*`WIDTH-1: 0] out;
reg out_valid;


reg [`ADDR_WIDTH-1: 0] ls0_raddr;
reg [`ADDR_WIDTH-1: 0] ls0_waddr;
reg [`ADDR_WIDTH-1: 0] ls1_raddr;
reg [`ADDR_WIDTH-1: 0] ls1_waddr;


reg ls0_we;
reg ls1_we;

wire [`L*`WIDTH-1: 0] ls0_dOut;
reg [`L*`WIDTH-1: 0] ls0_dIn;
wire [`L*`WIDTH-1: 0] ls1_dOut;
reg [`L*`WIDTH-1: 0] ls1_dIn;
reg [`ADDR_WIDTH-1: 0] addr0;
wire [`ADDR_WIDTH-1: 0] addr1;

reg [`logL-1: 0] part_select;


always @(posedge clk, posedge reset)
begin
	if (reset == 1'b1)
	begin
		ls0_waddr <= {`ADDR_WIDTH {1'b1}};
		ls1_waddr <= {`ADDR_WIDTH {1'b1}};

		addr0 <= 0;
		ls0_we <= 0;
		ls1_we <= 0;

		in2 <= `L*`WIDTH'b0;
		in3 <= `L*`WIDTH'b0;

		instr_out1 <= {`logB'b0, `IDLE};
		instr_out2 <= {`logB'b0, `IDLE};
		instr_out3 <= {`logB'b0, `IDLE};

		out <= {`L*`WIDTH{1'b1}};
		out_valid <= 1'b0;

	end
	else
	begin



		case(command1)
		`READ0:
		begin
			ls0_waddr <= ls0_waddr + 1'b1;
			ls0_we <= 1'b1;
			ls1_we <= 1'b0;
			ls0_dIn <= in1;
		end
		`READ1:
		begin
			ls1_waddr <= ls1_waddr + 1'b1;
			ls0_we <= 1'b0;
			ls1_we <= 1'b1;
			ls1_dIn <= in1;
		end
		`COMPUTE:
		begin
			ls0_we <= 1'b0;
			ls1_we <= 1'b0;
			addr0 <= addr0 + 1'b1;
			part_select <= instr_in[`OP_WIDTH + `logL - 1: `OP_WIDTH];
			in2 <= in1;
		end
		`FORWARD:
		begin
			ls0_we <= 1'b0;
			ls1_we <= 1'b0;
			in2 <= in1;
		end
		default:
		begin
			ls0_we <= 1'b0;
			ls1_we <= 1'b0;
			in2 <= in1;
		end
		endcase



		case(command2)
		`COMPUTE:
		begin
			d0 <= ls0_dOut;
			d1[1*`WIDTH-1: 0*`WIDTH] <= ls1_dOut[part_select*`WIDTH +: `WIDTH];
			d1[2*`WIDTH-1: 1*`WIDTH] <= ls1_dOut[part_select*`WIDTH +: `WIDTH];
			d1[3*`WIDTH-1: 2*`WIDTH] <= ls1_dOut[part_select*`WIDTH +: `WIDTH];
			d1[4*`WIDTH-1: 3*`WIDTH] <= ls1_dOut[part_select*`WIDTH +: `WIDTH];
			in3 <= in2;
		end
		default:
		begin
			d0 <= `L*`WIDTH'b0;
			d1 <= `L*`WIDTH'b0;
			in3 <= in2;
		end
		endcase




		case(command3)
		`COMPUTE:
		begin
			out <= out0;
			out_valid <= 1'b1;
		end
		`FORWARD:
		begin
			out <= in3;
			out_valid <= 1'b1;
		end
		default:
		begin
			out <= `L*`WIDTH'b0;
			out_valid <= 1'b0;
		end
		endcase
		instr_out1 <= instr_in;
		instr_out2 <= instr_out1;
		instr_out3 <= instr_out2;
		command2 <= command1;
		command3 <= command2;
	end
end


generate
genvar i;
for (i=0; i<`L; i=i+1)
begin: op_array
	op op_inst(
	.in0(in3[(i+1)*`WIDTH-1 : i*`WIDTH]),
	.in1(d0[(i+1)*`WIDTH-1 : i*`WIDTH]),
	.in2(d1[(i+1)*`WIDTH-1 : i*`WIDTH]),
	.out0(out0[(i+1)*`WIDTH-1 : i*`WIDTH]));
end
endgenerate

assign addr1 = instr_in[`INSTR_WIDTH-2: `OP_WIDTH + `logL];
always @(*)
begin
	if (command1 == `COMPUTE)
	begin
		ls0_raddr <= addr0;
		ls1_raddr <= addr1;
	end
	else
	begin
		ls0_raddr <= 0;
		ls1_raddr <= 0;
	end
end
assign instr_out = instr_out3;
assign in1 = in;


local_store #(`B*`B/`L/`B) ls0(
	.clk(clk),
	.we(ls0_we),
	.a_r(ls0_raddr),
	.a_w(ls0_waddr),
	.di(ls0_dIn),
	.dout(ls0_dOut)
);


local_store #(`B*`B/`L/`B) ls1(
	.clk(clk),
	.we(ls1_we),
	.a_r(ls1_raddr),
	.a_w(ls1_waddr),
	.di(ls1_dIn),
	.dout(ls1_dOut)
);



pe_instr_decoder #id pe_instr_decoder_inst(
	.instr_in(instr_in),
	.command(command1)
);
endmodule