data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n   #21;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n   #21;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n   #21;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n   #21;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n   #21;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n   #21;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #21\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #21;\n  ^\n%Error: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:38: Cannot find file containing module: \'CameraController\'\n CameraController uut (\n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new,data/full_repos/permissive/123043192/CameraController\n             data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new,data/full_repos/permissive/123043192/CameraController.v\n             data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new,data/full_repos/permissive/123043192/CameraController.sv\n             CameraController\n             CameraController.v\n             CameraController.sv\n             obj_dir/CameraController\n             obj_dir/CameraController.v\n             obj_dir/CameraController.sv\n%Warning-WIDTH: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:71: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                                             : ... In instance cameraController_tb\n   cam_byte = i;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:84: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                                             : ... In instance cameraController_tb\n   cam_byte = i;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sim_1/new/cameraController_tb.v:97: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                                             : ... In instance cameraController_tb\n   cam_byte = i;\n            ^\n%Error: Exiting due to 1 error(s), 23 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cameraController_tb;
	integer i;

	reg [7:0] cam_byte;
	reg pclk;
	reg vsync;
	reg href;


	wire xclk;
	wire [15:0] pixel_data;


	CameraController uut (
		.cam_byte(cam_byte), 
		.pclk(pclk), 
		.vsync(vsync), 
		.href(href), 
		.xclk(xclk), 
		.pixel_data(pixel_data)
	);

	initial begin

		cam_byte = 0;
		pclk = 0;
		vsync = 1;
		href = 0;


		#100;
        

		
		cam_byte = 8'h88;
		vsync = 0;
		#21;
		pclk = 1;
		#21;
		pclk = 0;
		href = 1;
		for(i = 0; i < 640; i = i + 1) begin
			#21;
			pclk = 1;
			#21;
			pclk = 0;
			cam_byte = i;
		end
		href = 0;
		#21;
		pclk = 1;
		#21;
		pclk = 0;
		href = 1;
		for(i = 0; i < 640; i = i + 1) begin
			#21;
			pclk = 1;
			#21;
			pclk = 0;
			cam_byte = i;
		end
		href = 0;
		#21;
		pclk = 1;
		#21;
		pclk = 0;
		href = 1;
		for(i = 0; i < 640; i = i + 1) begin
			#21;
			pclk = 1;
			#21;
			pclk = 0;
			cam_byte = i;
		end
		href = 0;
		#21
		pclk = 1;
		#21;
		pclk = 0;
		#21;
		pclk = 1;
		#21;
		pclk = 0;
		#21;
		pclk = 1;
		#21;
		pclk = 0;
		vsync = 1;
		#21;
	end
      
endmodule
module cameraController_tb;

	integer i;

	reg [7:0] cam_byte;
	reg pclk;
	reg vsync;
	reg href;


	wire xclk;
	wire [15:0] pixel_data;


	CameraController uut (
		.cam_byte(cam_byte), 
		.pclk(pclk), 
		.vsync(vsync), 
		.href(href), 
		.xclk(xclk), 
		.pixel_data(pixel_data)
	);

	initial begin

		cam_byte = 0;
		pclk = 0;
		vsync = 1;
		href = 0;


		#100;
        

		
		cam_byte = 8'h88;
		vsync = 0;
		#21;
		pclk = 1;
		#21;
		pclk = 0;
		href = 1;
		for(i = 0; i < 640; i = i + 1) begin
			#21;
			pclk = 1;
			#21;
			pclk = 0;
			cam_byte = i;
		end
		href = 0;
		#21;
		pclk = 1;
		#21;
		pclk = 0;
		href = 1;
		for(i = 0; i < 640; i = i + 1) begin
			#21;
			pclk = 1;
			#21;
			pclk = 0;
			cam_byte = i;
		end
		href = 0;
		#21;
		pclk = 1;
		#21;
		pclk = 0;
		href = 1;
		for(i = 0; i < 640; i = i + 1) begin
			#21;
			pclk = 1;
			#21;
			pclk = 0;
			cam_byte = i;
		end
		href = 0;
		#21
		pclk = 1;
		#21;
		pclk = 0;
		#21;
		pclk = 1;
		#21;
		pclk = 0;
		#21;
		pclk = 1;
		#21;
		pclk = 0;
		vsync = 1;
		#21;
	end
      
endmodule