data/full_repos/permissive/169496369/inc_dec.v
data/verilator_xmls/473756be-48cf-4524-9f99-c9bb6d8641af.xml
module inc_dec(a, control, o);
    input [7:0]a;
    input [1:0]control;
    output logic [7:0]o;
    
    always_comb
    begin
        if(control == 2'd2)
            o = a + 1;
        else if(control == 2'd0)
            o = a - 1;
        else
            o = a;
    end
endmodule
module inc_dec(a, control, o);

    input [7:0]a;
    input [1:0]control;
    output logic [7:0]o;
    
    always_comb
    begin
        if(control == 2'd2)
            o = a + 1;
        else if(control == 2'd0)
            o = a - 1;
        else
            o = a;
    end
endmodule