data/full_repos/permissive/143278/ivltests/npmos.v
 line:4: before: "reg"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/npmos.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (no !== 1\'bz) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/npmos.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (no !== 1\'bz) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/npmos.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (no !== 1\'b1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/npmos.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (no !== 1\'b0) begin\n      ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire no, po;
   reg	d, c;

   nmos n (no, d, c);
   pmos p (po, d, c);

   initial begin
      c = 0;
      d = 0;

      #1 if (no !== 1'bz) begin
	 $display("FAILED -- n (%b, %b, %b)", no, d, c);
	 $finish;
      end

      if (po !== 1'b0) begin
	 $display("FAILED -- p (%b, %b, %b)", po, d, c);
	 $finish;
      end

      d = 1;

      #1 if (no !== 1'bz) begin
	 $display("FAILED -- n (%b, %b, %b)", no, d, c);
	 $finish;
      end

      if (po !== 1'b1) begin
	 $display("FAILED -- p (%b, %b, %b)", po, d, c);
	 $finish;
      end

      c = 1;

      #1 if (no !== 1'b1) begin
	 $display("FAILED -- n (%b, %b, %b)", no, d, c);
	 $finish;
      end

      if (po !== 1'bz) begin
	 $display("FAILED -- p (%b, %b, %b)", po, d, c);
	 $finish;
      end

      d = 0;

      #1 if (no !== 1'b0) begin
	 $display("FAILED -- n (%b, %b, %b)", no, d, c);
	 $finish;
      end

      if (po !== 1'bz) begin
	 $display("FAILED -- p (%b, %b, %b)", po, d, c);
	 $finish;
      end

      $display("PASSED");

   end

endmodule
module main;


   wire no, po;
   reg	d, c;

   nmos n (no, d, c);
   pmos p (po, d, c);

   initial begin
      c = 0;
      d = 0;

      #1 if (no !== 1'bz) begin
	 $display("FAILED -- n (%b, %b, %b)", no, d, c);
	 $finish;
      end

      if (po !== 1'b0) begin
	 $display("FAILED -- p (%b, %b, %b)", po, d, c);
	 $finish;
      end

      d = 1;

      #1 if (no !== 1'bz) begin
	 $display("FAILED -- n (%b, %b, %b)", no, d, c);
	 $finish;
      end

      if (po !== 1'b1) begin
	 $display("FAILED -- p (%b, %b, %b)", po, d, c);
	 $finish;
      end

      c = 1;

      #1 if (no !== 1'b1) begin
	 $display("FAILED -- n (%b, %b, %b)", no, d, c);
	 $finish;
      end

      if (po !== 1'bz) begin
	 $display("FAILED -- p (%b, %b, %b)", po, d, c);
	 $finish;
      end

      d = 0;

      #1 if (no !== 1'b0) begin
	 $display("FAILED -- n (%b, %b, %b)", no, d, c);
	 $finish;
      end

      if (po !== 1'bz) begin
	 $display("FAILED -- p (%b, %b, %b)", po, d, c);
	 $finish;
      end

      $display("PASSED");

   end

endmodule