data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mips.v
 line:206: before: "begin"
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mips.v\n%Error: Exiting due to 4 error(s)\n'
module mips #(parameter WIDTH = 8, REGBITS = 3)
             (input              clk, reset, 
              input  [WIDTH-1:0] memdata, 
              output             memread, memwrite, 
              output [WIDTH-1:0] adr, writedata);

   wire [31:0] instr;
   wire        zero, alusrca, memtoreg, iord, pcen, regwrite, regdst;
   wire [1:0]  aluop,pcsource,alusrcb;
   wire [3:0]  irwrite;
   wire [2:0]  alucont;

   controller  cont(clk, reset, instr[31:26], zero, memread, memwrite, 
                    alusrca, memtoreg, iord, pcen, regwrite, regdst,
                    pcsource, alusrcb, aluop, irwrite);
   alucontrol  ac(aluop, instr[5:0], alucont);
   datapath    #(WIDTH, REGBITS) 
               dp(clk, reset, memdata, alusrca, memtoreg, iord, pcen,
                  regwrite, regdst, pcsource, alusrcb, irwrite, alucont,
                  zero, instr, adr, writedata);
endmodule
module mips #(parameter WIDTH = 8, REGBITS = 3)
             (input              clk, reset, 
              input  [WIDTH-1:0] memdata, 
              output             memread, memwrite, 
              output [WIDTH-1:0] adr, writedata);


   wire [31:0] instr;
   wire        zero, alusrca, memtoreg, iord, pcen, regwrite, regdst;
   wire [1:0]  aluop,pcsource,alusrcb;
   wire [3:0]  irwrite;
   wire [2:0]  alucont;

   controller  cont(clk, reset, instr[31:26], zero, memread, memwrite, 
                    alusrca, memtoreg, iord, pcen, regwrite, regdst,
                    pcsource, alusrcb, aluop, irwrite);
   alucontrol  ac(aluop, instr[5:0], alucont);
   datapath    #(WIDTH, REGBITS) 
               dp(clk, reset, memdata, alusrca, memtoreg, iord, pcen,
                  regwrite, regdst, pcsource, alusrcb, irwrite, alucont,
                  zero, instr, adr, writedata);
endmodule