data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/boolean_25.v
data/verilator_xmls/8c675d3a-31d8-4dbc-aadc-560172bcf020.xml
module boolean_25 (
    output reg [15:0] out,
    input [5:0] alufn,
    input [15:0] a,
    input [15:0] b
  );
  
  
  
  always @* begin
    out = 16'bxxxxxxxxxxxxxxxx;
    
    case (alufn)
      6'h18: begin
        out = a & b;
      end
      6'h1e: begin
        out = a | b;
      end
      6'h16: begin
        out = a ^ b;
      end
      6'h1a: begin
        out = a;
      end
      6'h1c: begin
        out = b;
      end
      6'h17: begin
        out = ~(a & b);
      end
      6'h11: begin
        out = ~(a | b);
      end
    endcase
  end
endmodule
module boolean_25 (
    output reg [15:0] out,
    input [5:0] alufn,
    input [15:0] a,
    input [15:0] b
  );

  
  
  
  always @* begin
    out = 16'bxxxxxxxxxxxxxxxx;
    
    case (alufn)
      6'h18: begin
        out = a & b;
      end
      6'h1e: begin
        out = a | b;
      end
      6'h16: begin
        out = a ^ b;
      end
      6'h1a: begin
        out = a;
      end
      6'h1c: begin
        out = b;
      end
      6'h17: begin
        out = ~(a & b);
      end
      6'h11: begin
        out = ~(a | b);
      end
    endcase
  end
endmodule