data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v
1: b"%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74: Cannot find file containing module: 'top'\ntop top_0(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl,data/full_repos/permissive/137416811/top\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl,data/full_repos/permissive/137416811/top.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl,data/full_repos/permissive/137416811/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86: Cannot find file containing module: 'top'\ntop top_1(\n^~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:98: Cannot find file containing module: 'top'\ntop top_2(\n^~~\n%Error: Exiting due to 3 error(s)\n"
module  multi_enc_decx2x4(

    clock,
    datain,
    datain1,
    datain1_0,
    datain_0,
    reset,

    dataout,
    dataout1,
    dataout1_0,
    dataout_0
);




input          clock;
input  [127:0] datain;
input  [127:0] datain1;
input  [127:0] datain1_0;
input  [127:0] datain_0;
input          reset;



output [127:0] dataout;
output [127:0] dataout1;
output [127:0] dataout1_0;
output [127:0] dataout_0;



wire           clock;
wire   [127:0] datain;
wire   [127:0] datain1;
wire   [127:0] datain1_0;
wire   [127:0] datain_0;
wire   [127:0] dataout_net_0;
wire   [127:0] dataout1_net_0;
wire   [127:0] dataout1_0_net_0;
wire   [127:0] dataout_0_net_0;
wire           reset;
wire   [127:0] top_0_dataout;
wire   [127:0] top_1_dataout1;
wire   [127:0] dataout_net_1;
wire   [127:0] dataout1_net_1;
wire   [127:0] dataout1_0_net_1;
wire   [127:0] dataout_0_net_1;



assign dataout_net_1     = dataout_net_0;
assign dataout[127:0]    = dataout_net_1;
assign dataout1_net_1    = dataout1_net_0;
assign dataout1[127:0]   = dataout1_net_1;
assign dataout1_0_net_1  = dataout1_0_net_0;
assign dataout1_0[127:0] = dataout1_0_net_1;
assign dataout_0_net_1   = dataout_0_net_0;
assign dataout_0[127:0]  = dataout_0_net_1;




top top_0(

        .clock    ( clock ),
        .reset    ( reset ),
        .datain   ( datain ),
        .datain1  ( datain1 ),

        .dataout  ( top_0_dataout ),
        .dataout1 ( dataout1_0_net_0 ) 
        );


top top_1(

        .clock    ( clock ),
        .reset    ( reset ),
        .datain   ( datain_0 ),
        .datain1  ( datain1_0 ),

        .dataout  ( dataout_0_net_0 ),
        .dataout1 ( top_1_dataout1 ) 
        );


top top_2(

        .clock    ( clock ),
        .reset    ( reset ),
        .datain   ( top_0_dataout ),
        .datain1  ( top_1_dataout1 ),

        .dataout  ( dataout_net_0 ),
        .dataout1 ( dataout1_net_0 ) 
        );


endmodule
module  multi_enc_decx2x4(

    clock,
    datain,
    datain1,
    datain1_0,
    datain_0,
    reset,

    dataout,
    dataout1,
    dataout1_0,
    dataout_0
);





input          clock;
input  [127:0] datain;
input  [127:0] datain1;
input  [127:0] datain1_0;
input  [127:0] datain_0;
input          reset;



output [127:0] dataout;
output [127:0] dataout1;
output [127:0] dataout1_0;
output [127:0] dataout_0;



wire           clock;
wire   [127:0] datain;
wire   [127:0] datain1;
wire   [127:0] datain1_0;
wire   [127:0] datain_0;
wire   [127:0] dataout_net_0;
wire   [127:0] dataout1_net_0;
wire   [127:0] dataout1_0_net_0;
wire   [127:0] dataout_0_net_0;
wire           reset;
wire   [127:0] top_0_dataout;
wire   [127:0] top_1_dataout1;
wire   [127:0] dataout_net_1;
wire   [127:0] dataout1_net_1;
wire   [127:0] dataout1_0_net_1;
wire   [127:0] dataout_0_net_1;



assign dataout_net_1     = dataout_net_0;
assign dataout[127:0]    = dataout_net_1;
assign dataout1_net_1    = dataout1_net_0;
assign dataout1[127:0]   = dataout1_net_1;
assign dataout1_0_net_1  = dataout1_0_net_0;
assign dataout1_0[127:0] = dataout1_0_net_1;
assign dataout_0_net_1   = dataout_0_net_0;
assign dataout_0[127:0]  = dataout_0_net_1;




top top_0(

        .clock    ( clock ),
        .reset    ( reset ),
        .datain   ( datain ),
        .datain1  ( datain1 ),

        .dataout  ( top_0_dataout ),
        .dataout1 ( dataout1_0_net_0 ) 
        );


top top_1(

        .clock    ( clock ),
        .reset    ( reset ),
        .datain   ( datain_0 ),
        .datain1  ( datain1_0 ),

        .dataout  ( dataout_0_net_0 ),
        .dataout1 ( top_1_dataout1 ) 
        );


top top_2(

        .clock    ( clock ),
        .reset    ( reset ),
        .datain   ( top_0_dataout ),
        .datain1  ( top_1_dataout1 ),

        .dataout  ( dataout_net_0 ),
        .dataout1 ( dataout1_net_0 ) 
        );


endmodule