data/full_repos/permissive/128659832/verilog/PROG.v
data/verilator_xmls/650ac35f-81ca-42b8-8dc1-6876b97d5cca.xml
module PROG (din, Addr, write_en, clk, Data);
  parameter addr_width = 8;
  parameter data_width = 8;
  parameter PROGRAM = "dummy_prg.hex";

  input [addr_width-1:0] Addr;
  input [data_width-1:0] din;
  input write_en, clk;

  output [data_width-1:0] Data;

  reg [data_width-1:0] Data;
  reg [data_width-1:0] rom [(1<<addr_width)-1:0];

  initial begin
      if( PROGRAM !=0 ) $readmemh(PROGRAM, rom);
  end

  always @(posedge clk)
  begin
    if (write_en)
      rom[(Addr)] <= din;
    Data = rom[Addr];
  end
endmodule
module PROG (din, Addr, write_en, clk, Data);

  parameter addr_width = 8;
  parameter data_width = 8;
  parameter PROGRAM = "dummy_prg.hex";

  input [addr_width-1:0] Addr;
  input [data_width-1:0] din;
  input write_en, clk;

  output [data_width-1:0] Data;

  reg [data_width-1:0] Data;
  reg [data_width-1:0] rom [(1<<addr_width)-1:0];

  initial begin
      if( PROGRAM !=0 ) $readmemh(PROGRAM, rom);
  end

  always @(posedge clk)
  begin
    if (write_en)
      rom[(Addr)] <= din;
    Data = rom[Addr];
  end
endmodule