data/full_repos/permissive/100597706/testing/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n   always # 5 clk = ~ clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[4] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[4] = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[14] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[14] = 1\'b0;\n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module AHBSLAVE_M #(parameter logHBank = 10)
(
			input HSEL,

			input HCLK,
			input HRST,

			input HREADY,
			input [31:0] HADDR,
			input HTRANS,
			input HWRITE,
			input [1:0] HSIZE,
			
			input [31:0] HWDATA,

			output HREADYout,
			output [31:0] HRDATA
	
);






  reg last_HSEL, last_HWRITE, last_HTRANS;
  reg [31:0] last_HADDR;
  reg [1:0] last_HSIZE;

 
  always @(posedge HCLK, posedge HRST)
  begin
	 if(HRST)
	 begin
		last_HSEL <= 1'b0;
        last_HWRITE <= 1'b0;
        last_HTRANS <= 1'b1;
		last_HADDR <= 32'd0;
		last_HSIZE <= 2'b0;
	 end
    else if(HREADY)
    begin
        last_HSEL <= HSEL;
        last_HWRITE <= HWRITE;
        last_HTRANS <= HTRANS;
		last_HADDR <= HADDR;
		last_HSIZE <= HSIZE;
    end
  end

  reg [31:0] baddr_buffer;
  always @ (*)
    if (last_HSEL)
        baddr_buffer = last_HADDR;

  memory #(logHBank) M (.clk(HCLK), .bdi(HWDATA), .baddr(baddr_buffer), .bdo(HRDATA), .mwr(last_HWRITE & last_HTRANS), .bsz(last_HSIZE), .brdy(HREADYout));
`ifdef _DBUG_
    always @ *
        $display("HRDATA_memory = %h", HRDATA);
    always @ *
        $display("baddr_buffer = %h", baddr_buffer);
    always @ *
        $display("last_HSEL = %h", last_HSEL);
`endif

endmodule
module AHBSLAVE_M #(parameter logHBank = 10)
(
			input HSEL,

			input HCLK,
			input HRST,

			input HREADY,
			input [31:0] HADDR,
			input HTRANS,
			input HWRITE,
			input [1:0] HSIZE,
			
			input [31:0] HWDATA,

			output HREADYout,
			output [31:0] HRDATA
	
);







  reg last_HSEL, last_HWRITE, last_HTRANS;
  reg [31:0] last_HADDR;
  reg [1:0] last_HSIZE;

 
  always @(posedge HCLK, posedge HRST)
  begin
	 if(HRST)
	 begin
		last_HSEL <= 1'b0;
        last_HWRITE <= 1'b0;
        last_HTRANS <= 1'b1;
		last_HADDR <= 32'd0;
		last_HSIZE <= 2'b0;
	 end
    else if(HREADY)
    begin
        last_HSEL <= HSEL;
        last_HWRITE <= HWRITE;
        last_HTRANS <= HTRANS;
		last_HADDR <= HADDR;
		last_HSIZE <= HSIZE;
    end
  end

  reg [31:0] baddr_buffer;
  always @ (*)
    if (last_HSEL)
        baddr_buffer = last_HADDR;

  memory #(logHBank) M (.clk(HCLK), .bdi(HWDATA), .baddr(baddr_buffer), .bdo(HRDATA), .mwr(last_HWRITE & last_HTRANS), .bsz(last_HSIZE), .brdy(HREADYout));
`ifdef _DBUG_
    always @ *
        $display("HRDATA_memory = %h", HRDATA);
    always @ *
        $display("baddr_buffer = %h", baddr_buffer);
    always @ *
        $display("last_HSEL = %h", last_HSEL);
`endif

endmodule