data/full_repos/permissive/205055389/test/verga/memory3.v
 line:20: before: "@"
1: b'%Error: data/full_repos/permissive/205055389/test/verga/memory3.v:20: syntax error, unexpected \'@\', expecting TYPE-IDENTIFIER\n m[3] <= @(posedge x) 8\'h99;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/memory3.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #1 $display($time,": m[3]=",m[3]," w=",w);\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/memory3.v:29: Unsupported: Ignoring delay on this delayed statement.\n #6 x = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/memory3.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 x = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/memory3.v:32: Unsupported: Ignoring delay on this delayed statement.\n #3 x = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/memory3.v:33: Unsupported: Ignoring delay on this delayed statement.\n #3 m[4] = 9;\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module top;
   reg [7:0] m[0:255];
   reg [7:0] addr;
   reg x = 1'b0;
   integer i;
   wire [7:0] w;

   assign     w = m[3];

   always @(w)
     $display($time,": w changed to ",w);
   
   initial
     begin
	m[3][7:4] = 9;
	m[3][3:0] = 2;

	m[3] <= #2 7;
	m[3][7:4] <= #3 3;
	m[3] <= @(posedge x) 8'h99;

	$display($time,": m[3]=",m[3]," w=",w);
	for (i = 0;i < 20;i = i+1)
	  #1 $display($time,": m[3]=",m[3]," w=",w);
     end

   initial
     begin
	#6 x = 1'b1;
	#3 x = 1'b0;
	m[3] = 8'h42;
	#3 x = 1'b1;
	#3 m[4] = 9;
     end
   
endmodule
module top;

   reg [7:0] m[0:255];
   reg [7:0] addr;
   reg x = 1'b0;
   integer i;
   wire [7:0] w;

   assign     w = m[3];

   always @(w)
     $display($time,": w changed to ",w);
   
   initial
     begin
	m[3][7:4] = 9;
	m[3][3:0] = 2;

	m[3] <= #2 7;
	m[3][7:4] <= #3 3;
	m[3] <= @(posedge x) 8'h99;

	$display($time,": m[3]=",m[3]," w=",w);
	for (i = 0;i < 20;i = i+1)
	  #1 $display($time,": m[3]=",m[3]," w=",w);
     end

   initial
     begin
	#6 x = 1'b1;
	#3 x = 1'b0;
	m[3] = 8'h42;
	#3 x = 1'b1;
	#3 m[4] = 9;
     end
   
endmodule