data/full_repos/permissive/169574047/ripple_carry_counter/ripple_carry_counter.srcs/sources_1/new/D_FF.v
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data/verilator_xmls/8adb1291-48a2-4ee2-a77c-c76d5a396d19.xml
module D_FF(
output reg q,
input d,
input clk,
input reset
    );
    
    always@(posedge reset or negedge clk)
    if(reset)
        q <= 1'b0;
    else
        q <= d;
endmodule
module D_FF(
output reg q,
input d,
input clk,
input reset
    );

    
    always@(posedge reset or negedge clk)
    if(reset)
        q <= 1'b0;
    else
        q <= d;
endmodule