data/full_repos/permissive/219428126/full_adder_tb.v
 line:21: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/219428126/full_adder_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #0 A = 0; B = 0; X = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/219428126/full_adder_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1 A = 1; B = 0; X = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/219428126/full_adder_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1 A = 0; B = 1; X = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/219428126/full_adder_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1 A = 1; B = 1; X = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/219428126/full_adder_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1 A = 0; B = 0; X = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/219428126/full_adder_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1 A = 1; B = 0; X = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/219428126/full_adder_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1 A = 0; B = 1; X = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/219428126/full_adder_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1 A = 1; B = 1; X = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/219428126/full_adder_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1 $stop;\n    ^\n%Error: data/full_repos/permissive/219428126/full_adder_tb.v:7: Cannot find file containing module: \'full_adder\'\n  full_adder i1 (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219428126,data/full_repos/permissive/219428126/full_adder\n             data/full_repos/permissive/219428126,data/full_repos/permissive/219428126/full_adder.v\n             data/full_repos/permissive/219428126,data/full_repos/permissive/219428126/full_adder.sv\n             full_adder\n             full_adder.v\n             full_adder.sv\n             obj_dir/full_adder\n             obj_dir/full_adder.v\n             obj_dir/full_adder.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module full_adder_tb;
  reg  A, B, X;
  wire S, C;

  full_adder i1 (
    .A(A), .B(B), .X(X),
    .S(S), .C(C)
  );

  initial begin
    #0 A = 0; B = 0; X = 0;
    #1 A = 1; B = 0; X = 0;
    #1 A = 0; B = 1; X = 0;
    #1 A = 1; B = 1; X = 0;
    #1 A = 0; B = 0; X = 1;
    #1 A = 1; B = 0; X = 1;
    #1 A = 0; B = 1; X = 1;
    #1 A = 1; B = 1; X = 1;
    #1 $stop;
  end
endmodule
module full_adder_tb;

  reg  A, B, X;
  wire S, C;

  full_adder i1 (
    .A(A), .B(B), .X(X),
    .S(S), .C(C)
  );

  initial begin
    #0 A = 0; B = 0; X = 0;
    #1 A = 1; B = 0; X = 0;
    #1 A = 0; B = 1; X = 0;
    #1 A = 1; B = 1; X = 0;
    #1 A = 0; B = 0; X = 1;
    #1 A = 1; B = 0; X = 1;
    #1 A = 0; B = 1; X = 1;
    #1 A = 1; B = 1; X = 1;
    #1 $stop;
  end
endmodule