data/full_repos/permissive/136510272/projects/05_nes/uart.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/uart.v:19: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance uart\nreg [6:0] period   = 1\'b0;   \n                     ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/uart.v:20: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance uart\nreg [3:0] num_bits = 1\'b0;   \n                     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/uart.v:21: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance uart\nreg [1:0] flg      = 1\'b0;   \n                     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/uart.v:56: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance uart\n            period <= 1\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/uart.v:62: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance uart\n                num_bits <= 1\'b0;            \n                         ^~\n%Error: Exiting due to 5 warning(s)\n'
module uart(
	input   wire            clk12,
	input   wire            rx,
	output  reg     [7:0]   rx_byte,
	output  wire            rx_ready
);


parameter R_COUNT = 26;

reg [8:0] rc_data;
reg [1:0] latch;
reg [6:0] period   = 1'b0;
reg [3:0] num_bits = 1'b0;
reg [1:0] flg      = 1'b0;
reg       waiting  = 1'b1;


assign rx_ready = (flg == 2'b10);


wire spad = latch[1] & !latch[0];


always @(posedge clk12) latch <= {latch[0], rx};  


wire eof = (period == R_COUNT && num_bits == 4'd9);






always @(posedge clk12) begin



    if (waiting & spad) begin    
        waiting <= 1'b0;        
        
    end
    

    else if (!waiting) begin
        

        if (period == R_COUNT) begin

            period <= 1'b0;
    

            if (num_bits == 4'd9) begin
            
                waiting  <= 1'b1;
                num_bits <= 1'b0;
                rx_byte  <= rc_data[7:0];


            end else num_bits <= num_bits + 1'b1;

        end
        else begin
        

            if (period == R_COUNT / 2) rc_data <= {latch[1], rc_data[8:1]};            


            period <= period + 1'b1;

        end

    end
    

    flg <= {flg[0], eof};

end

endmodule
module uart(
	input   wire            clk12,
	input   wire            rx,
	output  reg     [7:0]   rx_byte,
	output  wire            rx_ready
);



parameter R_COUNT = 26;

reg [8:0] rc_data;
reg [1:0] latch;
reg [6:0] period   = 1'b0;
reg [3:0] num_bits = 1'b0;
reg [1:0] flg      = 1'b0;
reg       waiting  = 1'b1;


assign rx_ready = (flg == 2'b10);


wire spad = latch[1] & !latch[0];


always @(posedge clk12) latch <= {latch[0], rx};  


wire eof = (period == R_COUNT && num_bits == 4'd9);






always @(posedge clk12) begin



    if (waiting & spad) begin    
        waiting <= 1'b0;        
        
    end
    

    else if (!waiting) begin
        

        if (period == R_COUNT) begin

            period <= 1'b0;
    

            if (num_bits == 4'd9) begin
            
                waiting  <= 1'b1;
                num_bits <= 1'b0;
                rx_byte  <= rc_data[7:0];


            end else num_bits <= num_bits + 1'b1;

        end
        else begin
        

            if (period == R_COUNT / 2) rc_data <= {latch[1], rc_data[8:1]};            


            period <= period + 1'b1;

        end

    end
    

    flg <= {flg[0], eof};

end

endmodule