data/full_repos/permissive/189158922/verilog_src/force_end.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/force_end.v:34: Operator EQ expects 25 bits on the RHS, but RHS\'s VARREF \'allowed_cycles\' generates 24 bits.\n                                                                               : ... In instance top\n  assign \\$1  = counter == (* src = "force_end.py:61" *) allowed_cycles;\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top(allowed_cycles, rst, clk, fend, valid_in);
  wire \$1 ;
  wire [25:0] \$3 ;
  wire [25:0] \$4 ;
  (* src = "force_end.py:51" *)
  reg [24:0] \$next\counter ;
  (* src = "force_end.py:41" *)
  reg \$next\fend ;
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] \$next\fsm_state ;
  (* src = "force_end.py:39" *)
  input [23:0] allowed_cycles;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* init = 25'h0000000 *)
  (* src = "force_end.py:51" *)
  reg [24:0] counter = 25'h0000000;
  (* init = 1'h0 *)
  (* src = "force_end.py:41" *)
  output fend;
  reg fend = 1'h0;
  (* init = 2'h0 *)
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] fsm_state = 2'h0;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "force_end.py:38" *)
  input valid_in;
  assign \$1  = counter == (* src = "force_end.py:61" *) allowed_cycles;
  assign \$4  = counter + (* src = "force_end.py:60" *) 1'h1;
  always @(posedge clk)
      fend <= \$next\fend ;
  always @(posedge clk)
      counter <= \$next\counter ;
  always @(posedge clk)
      fsm_state <= \$next\fsm_state ;
  always @* begin
    \$next\fsm_state  = fsm_state;
    casez (fsm_state)
      2'h0:
          casez (valid_in)
            1'h1:
                \$next\fsm_state  = 2'h1;
          endcase
      2'h1:
          casez (\$1 )
            1'h1:
                \$next\fsm_state  = 2'h2;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fsm_state  = 2'h0;
    endcase
  end
  always @* begin
    \$next\counter  = counter;
    casez (fsm_state)
      2'h1:
          \$next\counter  = \$3 [24:0];
    endcase
    casez (rst)
      1'h1:
          \$next\counter  = 25'h0000000;
    endcase
  end
  always @* begin
    \$next\fend  = fend;
    casez (fsm_state)
      2'h2:
          \$next\fend  = 1'h1;
    endcase
    casez (rst)
      1'h1:
          \$next\fend  = 1'h0;
    endcase
  end
  assign \$3  = \$4 ;
endmodule
module top(allowed_cycles, rst, clk, fend, valid_in);

  wire \$1 ;
  wire [25:0] \$3 ;
  wire [25:0] \$4 ;
  (* src = "force_end.py:51" *)
  reg [24:0] \$next\counter ;
  (* src = "force_end.py:41" *)
  reg \$next\fend ;
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] \$next\fsm_state ;
  (* src = "force_end.py:39" *)
  input [23:0] allowed_cycles;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* init = 25'h0000000 *)
  (* src = "force_end.py:51" *)
  reg [24:0] counter = 25'h0000000;
  (* init = 1'h0 *)
  (* src = "force_end.py:41" *)
  output fend;
  reg fend = 1'h0;
  (* init = 2'h0 *)
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] fsm_state = 2'h0;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "force_end.py:38" *)
  input valid_in;
  assign \$1  = counter == (* src = "force_end.py:61" *) allowed_cycles;
  assign \$4  = counter + (* src = "force_end.py:60" *) 1'h1;
  always @(posedge clk)
      fend <= \$next\fend ;
  always @(posedge clk)
      counter <= \$next\counter ;
  always @(posedge clk)
      fsm_state <= \$next\fsm_state ;
  always @* begin
    \$next\fsm_state  = fsm_state;
    casez (fsm_state)
      2'h0:
          casez (valid_in)
            1'h1:
                \$next\fsm_state  = 2'h1;
          endcase
      2'h1:
          casez (\$1 )
            1'h1:
                \$next\fsm_state  = 2'h2;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fsm_state  = 2'h0;
    endcase
  end
  always @* begin
    \$next\counter  = counter;
    casez (fsm_state)
      2'h1:
          \$next\counter  = \$3 [24:0];
    endcase
    casez (rst)
      1'h1:
          \$next\counter  = 25'h0000000;
    endcase
  end
  always @* begin
    \$next\fend  = fend;
    casez (fsm_state)
      2'h2:
          \$next\fend  = 1'h1;
    endcase
    casez (rst)
      1'h1:
          \$next\fend  = 1'h0;
    endcase
  end
  assign \$3  = \$4 ;
endmodule