data/full_repos/permissive/211316121/lab5_2/TransFF.v
data/verilator_xmls/75e9f43b-e33a-4aff-85cf-98cd7b56ec35.xml
module CLKDIV(
    input clkstd,
    output clk
);
reg [28:0] q;

always@(posedge clkstd)
    q<=q+1;

assign clk=q[26];

endmodule
module CLKDIV(
    input clkstd,
    output clk
);

reg [28:0] q;

always@(posedge clkstd)
    q<=q+1;

assign clk=q[26];

endmodule