data/full_repos/permissive/148201731/rtl/fetch/top_fetch.v
data/verilator_xmls/b94cbfcb-9ebb-4b5b-b399-f8db6a86e0fb.xml
module top_fetch
#(
    parameter PC_DATA_WIDTH = 20,
    parameter INSTRUCTION_WIDTH = 32,
    parameter PC_INITIAL_ADDRESS = 20'h0
)(
    input clk,
    input rst_n,
    input en,
    input stall,



    input select_new_pc_in,
    input [PC_DATA_WIDTH-1:0] new_pc_in,


    output [PC_DATA_WIDTH-1:0] pc_out,

    output [PC_DATA_WIDTH-1:0] inst_mem_addr_out,
    input boot_mode
);


reg [PC_DATA_WIDTH-1:0] pc;
reg [PC_DATA_WIDTH-1:0] pc_mux_data;
reg [PC_DATA_WIDTH-1:0] pc_adder_data;




always@(*)
begin
  case(select_new_pc_in)
    0 : pc_mux_data = pc_adder_data;
    1 : pc_mux_data = new_pc_in;
  endcase
end




always@(*)
begin
  pc_adder_data = pc + 20'd4;
end




assign inst_mem_addr_out = pc;

always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        pc <= PC_INITIAL_ADDRESS;
    end 
    else if (boot_mode) begin
        pc <= PC_INITIAL_ADDRESS;
    end
    else if((!stall)&en) begin
        pc <= pc_mux_data;
    end
end

assign pc_out = pc;






















endmodule
module top_fetch
#(
    parameter PC_DATA_WIDTH = 20,
    parameter INSTRUCTION_WIDTH = 32,
    parameter PC_INITIAL_ADDRESS = 20'h0
)(
    input clk,
    input rst_n,
    input en,
    input stall,



    input select_new_pc_in,
    input [PC_DATA_WIDTH-1:0] new_pc_in,


    output [PC_DATA_WIDTH-1:0] pc_out,

    output [PC_DATA_WIDTH-1:0] inst_mem_addr_out,
    input boot_mode
);



reg [PC_DATA_WIDTH-1:0] pc;
reg [PC_DATA_WIDTH-1:0] pc_mux_data;
reg [PC_DATA_WIDTH-1:0] pc_adder_data;




always@(*)
begin
  case(select_new_pc_in)
    0 : pc_mux_data = pc_adder_data;
    1 : pc_mux_data = new_pc_in;
  endcase
end




always@(*)
begin
  pc_adder_data = pc + 20'd4;
end




assign inst_mem_addr_out = pc;

always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        pc <= PC_INITIAL_ADDRESS;
    end 
    else if (boot_mode) begin
        pc <= PC_INITIAL_ADDRESS;
    end
    else if((!stall)&en) begin
        pc <= pc_mux_data;
    end
end

assign pc_out = pc;






















endmodule