data/full_repos/permissive/142466462/ReactionTimer.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/142466462/ReactionTimer.v:41: Unsupported: Ignoring delay on this delayed statement.\n   #10 len=1\'b1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/142466462/ReactionTimer.v:25: Duplicate declaration of signal: \'rtime\'\n                                                               : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg [11:0] rtime;\n           ^~~~~\n        data/full_repos/permissive/142466462/ReactionTimer.v:23: ... Location of original declaration\n    output len, rtime, slow\n                ^~~~~\n%Error: data/full_repos/permissive/142466462/ReactionTimer.v:26: Duplicate declaration of signal: \'len\'\nreg len;\n    ^~~\n        data/full_repos/permissive/142466462/ReactionTimer.v:23: ... Location of original declaration\n    output len, rtime, slow\n           ^~~\n%Error: data/full_repos/permissive/142466462/ReactionTimer.v:27: Duplicate declaration of signal: \'slow\'\nreg slow;\n    ^~~~\n        data/full_repos/permissive/142466462/ReactionTimer.v:23: ... Location of original declaration\n    output len, rtime, slow\n                       ^~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ReactionTimer(
    input clk, rst, B,
    output len, rtime, slow
    );
reg [11:0] rtime;
reg len;
reg slow;
reg reset;
wire [11:0] rtime1;
initial
begin
  rtime=12'b000000000000;
  reset=1'b0;
  len=1'b0;
  slow=1'b0;
end
 
ripple_counter rpp0(rtime1, clk, reset);
always @(posedge rst)
begin
   #10 len=1'b1;
   reset=1'b1;
	if(B)
	begin
		if(rtime1>12'b011111010000)
		begin	 
			 rtime=12'b011111010000;
			 slow=1'b1;
			 len=1'b0;
		end
	   else
		begin
		    rtime=rtime1;
		    slow=1'b0;
			 len=1'b0;
		end
	end
	else
	begin
	    rtime=rtime1;
   end
end      	
endmodule
module ReactionTimer(
    input clk, rst, B,
    output len, rtime, slow
    );

reg [11:0] rtime;
reg len;
reg slow;
reg reset;
wire [11:0] rtime1;
initial
begin
  rtime=12'b000000000000;
  reset=1'b0;
  len=1'b0;
  slow=1'b0;
end
 
ripple_counter rpp0(rtime1, clk, reset);
always @(posedge rst)
begin
   #10 len=1'b1;
   reset=1'b1;
	if(B)
	begin
		if(rtime1>12'b011111010000)
		begin	 
			 rtime=12'b011111010000;
			 slow=1'b1;
			 len=1'b0;
		end
	   else
		begin
		    rtime=rtime1;
		    slow=1'b0;
			 len=1'b0;
		end
	end
	else
	begin
	    rtime=rtime1;
   end
end      	
endmodule