data/full_repos/permissive/214823094/code/clkdiv.v
data/verilator_xmls/372162b6-1756-4f29-a043-30e148386383.xml
module clkdiv(
    input mclk,

    output clk190,
    output clk48,
    output clk1_4hz
    );
    reg [27:0]q;
    always@(posedge mclk)




         q<=q+1;

    assign clk190=q[18];
    assign clk48=q[20];
    assign clk1_4hz=q[24];         
endmodule
module clkdiv(
    input mclk,

    output clk190,
    output clk48,
    output clk1_4hz
    );

    reg [27:0]q;
    always@(posedge mclk)




         q<=q+1;

    assign clk190=q[18];
    assign clk48=q[20];
    assign clk1_4hz=q[24];         
endmodule