data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/core/unused_reg.v
 line:34 column:23: Illegal character "'"
1: b"%Error: data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/core/unused_reg.v:23: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n      output [`CPCI_NF2_DATA_WIDTH - 1:0]    reg_rd_data,\n              ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/core/unused_reg.v:24: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n      input [`CPCI_NF2_DATA_WIDTH - 1:0]     reg_wr_data,\n             ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module unused_reg
   #(
      parameter REG_ADDR_WIDTH = 5
   )
   (

      input                                  reg_req,
      output                                 reg_ack,
      input                                  reg_rd_wr_L,

      input [REG_ADDR_WIDTH - 1:0]           reg_addr,

      output [`CPCI_NF2_DATA_WIDTH - 1:0]    reg_rd_data,
      input [`CPCI_NF2_DATA_WIDTH - 1:0]     reg_wr_data,


      input                                  clk,
      input                                  reset
   );


reg reg_req_d1;

assign reg_rd_data = 'h dead_beef;


assign reg_ack = reg_req && !reg_req_d1;

always @(posedge clk)
begin
   reg_req_d1 <= reg_req;
end

endmodule
module unused_reg
   #(
      parameter REG_ADDR_WIDTH = 5
   )
   (

      input                                  reg_req,
      output                                 reg_ack,
      input                                  reg_rd_wr_L,

      input [REG_ADDR_WIDTH - 1:0]           reg_addr,

      output [`CPCI_NF2_DATA_WIDTH - 1:0]    reg_rd_data,
      input [`CPCI_NF2_DATA_WIDTH - 1:0]     reg_wr_data,


      input                                  clk,
      input                                  reset
   );



reg reg_req_d1;

assign reg_rd_data = 'h dead_beef;


assign reg_ack = reg_req && !reg_req_d1;

always @(posedge clk)
begin
   reg_req_d1 <= reg_req;
end

endmodule