data/full_repos/permissive/143278/ivltests/pr1120.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1120.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1120.v:27: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                      : ... In instance pr1120\nassign foo[31:16] = (bar & 32\'hffffffff) >> 16;\n                  ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pr1120 ();

wire  [31:0] foo;
reg  [31:0] bar;


assign foo[31:16] = (bar & 32'hffffffff) >> 16;



initial
  begin
    bar = 32'ha5a5_3f3f;
    #100;
    $display("foo[31:16] = %x bar = %x",foo[31:16],bar);

    if(foo[31:16] === 16'ha5a5)
	$display("PASS (%x)",foo[31:16]);
     else
       $display("FAIL (%x vs %x)",foo[31:16],((bar & 32'hffffffff) >> 16));
    $finish;
  end
endmodule
module pr1120 ();


wire  [31:0] foo;
reg  [31:0] bar;


assign foo[31:16] = (bar & 32'hffffffff) >> 16;



initial
  begin
    bar = 32'ha5a5_3f3f;
    #100;
    $display("foo[31:16] = %x bar = %x",foo[31:16],bar);

    if(foo[31:16] === 16'ha5a5)
	$display("PASS (%x)",foo[31:16]);
     else
       $display("FAIL (%x vs %x)",foo[31:16],((bar & 32'hffffffff) >> 16));
    $finish;
  end
endmodule