data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder38.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder38.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=6\'b100001;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder38.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=6\'b100010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder38.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=6\'b100011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder38.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=6\'b100100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder38.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=6\'b100101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder38.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=6\'b100110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder38.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=6\'b100111;  \n        ^\n%Error: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder38.v:26: Cannot find file containing module: \'Top_decoder38\'\n    Top_decoder38 sim38(in,out);\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab1/sim_1/new,data/full_repos/permissive/211316121/Top_decoder38\n             data/full_repos/permissive/211316121/lab1/sim_1/new,data/full_repos/permissive/211316121/Top_decoder38.v\n             data/full_repos/permissive/211316121/lab1/sim_1/new,data/full_repos/permissive/211316121/Top_decoder38.sv\n             Top_decoder38\n             Top_decoder38.v\n             Top_decoder38.sv\n             obj_dir/Top_decoder38\n             obj_dir/Top_decoder38.v\n             obj_dir/Top_decoder38.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_decoder38();
    reg [5:0] in;
    wire [7:0] out;
    Top_decoder38 sim38(in,out);
    initial
        begin
            in=6'b100000;
        #10 in=6'b100001;
        #10 in=6'b100010;
        #10 in=6'b100011;
        #10 in=6'b100100;
        #10 in=6'b100101;
        #10 in=6'b100110;
        #10 in=6'b100111;  
        end
endmodule
module sim_decoder38();

    reg [5:0] in;
    wire [7:0] out;
    Top_decoder38 sim38(in,out);
    initial
        begin
            in=6'b100000;
        #10 in=6'b100001;
        #10 in=6'b100010;
        #10 in=6'b100011;
        #10 in=6'b100100;
        #10 in=6'b100101;
        #10 in=6'b100110;
        #10 in=6'b100111;  
        end
endmodule