data/full_repos/permissive/165663914/firmware/pulsegen.v
data/verilator_xmls/ea9215df-2631-4e83-b028-aa8f1e4f5c9a.xml
module pulsegen (
input wire sig,
input wire rst,
input wire clk,
output wire pulse);

parameter TPD = 0.7;

reg p1;
always @(posedge clk)
begin
  if (rst)
    p1 <= #TPD 1'b0;
  else
    p1 <= #TPD sig;
end

assign pulse = sig & !p1;

endmodule
module pulsegen (
input wire sig,
input wire rst,
input wire clk,
output wire pulse);


parameter TPD = 0.7;

reg p1;
always @(posedge clk)
begin
  if (rst)
    p1 <= #TPD 1'b0;
  else
    p1 <= #TPD sig;
end

assign pulse = sig & !p1;

endmodule