data/full_repos/permissive/154424341/rtl/verilog/spi_v2.v
 line:142: before: "("
1: b"%Error: data/full_repos/permissive/154424341/rtl/verilog/spi_v2.v:167: Cannot find file containing module: 'BUFGMUX'\n BUFGMUX BUFGMUX_sck_s (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154424341/rtl/verilog,data/full_repos/permissive/154424341/BUFGMUX\n             data/full_repos/permissive/154424341/rtl/verilog,data/full_repos/permissive/154424341/BUFGMUX.v\n             data/full_repos/permissive/154424341/rtl/verilog,data/full_repos/permissive/154424341/BUFGMUX.sv\n             BUFGMUX\n             BUFGMUX.v\n             BUFGMUX.sv\n             obj_dir/BUFGMUX\n             obj_dir/BUFGMUX.v\n             obj_dir/BUFGMUX.sv\n%Error: data/full_repos/permissive/154424341/rtl/verilog/spi_v2.v:173: Cannot find file containing module: 'BUFGMUX'\n BUFGMUX BUFGMUX_scko (\n ^~~~~~~\n%Error: data/full_repos/permissive/154424341/rtl/verilog/spi_v2.v:199: Cannot find file containing module: 'MUXCY'\n MUXCY MUXCY_tlphase (\n ^~~~~\n%Error: data/full_repos/permissive/154424341/rtl/verilog/spi_v2.v:205: Cannot find file containing module: 'MUXCY'\n MUXCY MUXCY_rlphase (\n ^~~~~\n%Error: Exiting due to 4 error(s)\n"
module spi_v2(
				clk_i,rst_i,cpol_i,cpha_i,start_i,miso_i,mosi_o,sck_o,ss_o,txdata_i,rxdata_o,buzy
    );

	parameter DATA_SIZE 		= 8;
	
	input 		clk_i;
	input 		rst_i;
	input 		cpol_i;
	input 		cpha_i;
	input			start_i;
	input 		miso_i;
	output reg	mosi_o;
	output 		sck_o;
	output reg	ss_o;
	input			[DATA_SIZE-1:0] txdata_i;
	output reg	[DATA_SIZE-1:0] rxdata_o;
	output 		buzy;
	
	reg[5:0] state;
	reg [7:0] count;
	reg [1:0]start_reg;
	parameter IDLE			=6'b000001;
	parameter SCKALIGN	=6'b000010;
	parameter START		=6'b000100;
	parameter REST			=6'b001000;
	parameter STOP			=6'b010000;
	parameter END			=6'b100000;
	
	parameter MAX_COUNT = DATA_SIZE*2;
	
	reg [DATA_SIZE-1:0] 	tx_buff,rx_buff;
	reg sck_t,sckn_t;
	wire sck_s;
	reg clk_align;
	reg tx_load,rx_load,rx_load_d,tx_load_d;
	wire tx_load_s,rx_load_s;
	wire start_lth;
	reg ss_d;

	always@(posedge clk_i) begin :st_machine
		if(~rst_i) begin			
			ss_d		<=1'b1;
			rx_load	<=1'b0;
			tx_load	<=1'b0;

			state<=IDLE;
		end else begin
			case (state)
			IDLE: begin
				ss_d		<=1'b1;
				rx_load	<=1'b0;
				tx_load	<=1'b0;

				if(start_lth) begin
					state		<=SCKALIGN;
					tx_load	<=1'b1;
				end else begin
					state		<=IDLE;
				end
			end
			SCKALIGN: begin

				if(sckn_t) begin
					state<=START;
				end
			end
			START: begin
				ss_d		<=1'b0;
				tx_load	<=1'b1;

				count<=0;
				state<=REST;
			end
			REST: begin

				tx_load	<=1'b0;
				if(count<MAX_COUNT-1) begin
					count<=count+1;
				end else begin
					state<=STOP;
				end
			end
			STOP: begin
				ss_d<=1'b1;
				rx_load<=1'b1;
				state<=END;
			end
			END: begin
				state<=IDLE;
			end
			endcase
		end
	end
	assign buzy=~ss_o;

	always@(posedge clk_i or negedge rst_i) begin
		if(!rst_i) begin
			start_reg<=2'b11;
		end else begin
			start_reg<={start_reg[0],start_i};
		end
	end
	assign start_lth=start_reg==2'b01;


	always@(negedge sck_s or negedge rst_i) begin :tx_shifter
		if(~rst_i) begin
			tx_buff<=0;
		end else begin
			if(tx_load_s) begin
				tx_buff<=txdata_i;	
			end else begin
				tx_buff<={1'b0,tx_buff[DATA_SIZE-1:1]};
				mosi_o<=tx_buff[0];
			end
		end
	end



	always@(posedge(sck_s) or negedge(rst_i) ) begin :rx_shifter
		if(~rst_i) begin
			rxdata_o<=0;
			rx_buff<=0;
		end else begin
			if(rx_load_s) begin
				rxdata_o<=rx_buff;
			end else begin
				rx_buff<={miso_i,rx_buff[DATA_SIZE-1:1]};
			end
		end
	end

	

	always@(posedge clk_i or negedge rst_i) begin
		if(~rst_i) begin
			sck_t<=1'b0;
			sckn_t<=1'b1;
		end else begin
			sck_t<=~sck_t;
			sckn_t<=sck_t;
		end
	end

	BUFGMUX BUFGMUX_sck_s (
		.O		(sck_s),
		.I0	(sckn_t),
		.I1	(sck_t),
		.S		(cpha_i)
	);
	BUFGMUX BUFGMUX_scko (
		.O		(sck_o),
		.I0	(sckn_t),
		.I1	(sck_t),
		.S		(cpol_i)
	);

	
	always@(posedge clk_i or negedge rst_i) begin
		if(~rst_i) begin
			ss_o<=1'b1;
		end else begin
			ss_o<=ss_d;
		end
	end
	

	always@(posedge clk_i or negedge rst_i) begin
		if(~rst_i) begin
			rx_load_d<=1'b0;
			tx_load_d<=1'b0;
		end else begin
			rx_load_d<=rx_load;
			tx_load_d<=tx_load;
		end
	end
	MUXCY MUXCY_tlphase (
		.O		(tx_load_s),
		.DI	(tx_load), 
		.CI	(tx_load_d),
		.S		(cpha_i)
	);
	MUXCY MUXCY_rlphase (
		.O		(rx_load_s),
		.DI	(rx_load),
		.CI	(rx_load_d),
		.S		(cpha_i)
	);

endmodule
module spi_v2(
				clk_i,rst_i,cpol_i,cpha_i,start_i,miso_i,mosi_o,sck_o,ss_o,txdata_i,rxdata_o,buzy
    );


	parameter DATA_SIZE 		= 8;
	
	input 		clk_i;
	input 		rst_i;
	input 		cpol_i;
	input 		cpha_i;
	input			start_i;
	input 		miso_i;
	output reg	mosi_o;
	output 		sck_o;
	output reg	ss_o;
	input			[DATA_SIZE-1:0] txdata_i;
	output reg	[DATA_SIZE-1:0] rxdata_o;
	output 		buzy;
	
	reg[5:0] state;
	reg [7:0] count;
	reg [1:0]start_reg;
	parameter IDLE			=6'b000001;
	parameter SCKALIGN	=6'b000010;
	parameter START		=6'b000100;
	parameter REST			=6'b001000;
	parameter STOP			=6'b010000;
	parameter END			=6'b100000;
	
	parameter MAX_COUNT = DATA_SIZE*2;
	
	reg [DATA_SIZE-1:0] 	tx_buff,rx_buff;
	reg sck_t,sckn_t;
	wire sck_s;
	reg clk_align;
	reg tx_load,rx_load,rx_load_d,tx_load_d;
	wire tx_load_s,rx_load_s;
	wire start_lth;
	reg ss_d;

	always@(posedge clk_i) begin :st_machine
		if(~rst_i) begin			
			ss_d		<=1'b1;
			rx_load	<=1'b0;
			tx_load	<=1'b0;

			state<=IDLE;
		end else begin
			case (state)
			IDLE: begin
				ss_d		<=1'b1;
				rx_load	<=1'b0;
				tx_load	<=1'b0;

				if(start_lth) begin
					state		<=SCKALIGN;
					tx_load	<=1'b1;
				end else begin
					state		<=IDLE;
				end
			end
			SCKALIGN: begin

				if(sckn_t) begin
					state<=START;
				end
			end
			START: begin
				ss_d		<=1'b0;
				tx_load	<=1'b1;

				count<=0;
				state<=REST;
			end
			REST: begin

				tx_load	<=1'b0;
				if(count<MAX_COUNT-1) begin
					count<=count+1;
				end else begin
					state<=STOP;
				end
			end
			STOP: begin
				ss_d<=1'b1;
				rx_load<=1'b1;
				state<=END;
			end
			END: begin
				state<=IDLE;
			end
			endcase
		end
	end
	assign buzy=~ss_o;

	always@(posedge clk_i or negedge rst_i) begin
		if(!rst_i) begin
			start_reg<=2'b11;
		end else begin
			start_reg<={start_reg[0],start_i};
		end
	end
	assign start_lth=start_reg==2'b01;


	always@(negedge sck_s or negedge rst_i) begin :tx_shifter
		if(~rst_i) begin
			tx_buff<=0;
		end else begin
			if(tx_load_s) begin
				tx_buff<=txdata_i;	
			end else begin
				tx_buff<={1'b0,tx_buff[DATA_SIZE-1:1]};
				mosi_o<=tx_buff[0];
			end
		end
	end



	always@(posedge(sck_s) or negedge(rst_i) ) begin :rx_shifter
		if(~rst_i) begin
			rxdata_o<=0;
			rx_buff<=0;
		end else begin
			if(rx_load_s) begin
				rxdata_o<=rx_buff;
			end else begin
				rx_buff<={miso_i,rx_buff[DATA_SIZE-1:1]};
			end
		end
	end

	

	always@(posedge clk_i or negedge rst_i) begin
		if(~rst_i) begin
			sck_t<=1'b0;
			sckn_t<=1'b1;
		end else begin
			sck_t<=~sck_t;
			sckn_t<=sck_t;
		end
	end

	BUFGMUX BUFGMUX_sck_s (
		.O		(sck_s),
		.I0	(sckn_t),
		.I1	(sck_t),
		.S		(cpha_i)
	);
	BUFGMUX BUFGMUX_scko (
		.O		(sck_o),
		.I0	(sckn_t),
		.I1	(sck_t),
		.S		(cpol_i)
	);

	
	always@(posedge clk_i or negedge rst_i) begin
		if(~rst_i) begin
			ss_o<=1'b1;
		end else begin
			ss_o<=ss_d;
		end
	end
	

	always@(posedge clk_i or negedge rst_i) begin
		if(~rst_i) begin
			rx_load_d<=1'b0;
			tx_load_d<=1'b0;
		end else begin
			rx_load_d<=rx_load;
			tx_load_d<=tx_load;
		end
	end
	MUXCY MUXCY_tlphase (
		.O		(tx_load_s),
		.DI	(tx_load), 
		.CI	(tx_load_d),
		.S		(cpha_i)
	);
	MUXCY MUXCY_rlphase (
		.O		(rx_load_s),
		.DI	(rx_load),
		.CI	(rx_load_d),
		.S		(cpha_i)
	);

endmodule