data/full_repos/permissive/184431263/ADDERS/FA.v
data/verilator_xmls/dd20d943-e208-48e8-adff-f22bd71bcb5d.xml
module FA(COUT, SUM, A, B, CIN, VDD, VSS );
  input A, B, CIN;
  output COUT, SUM;
  inout VDD, VSS;

  assign SUM=(A ^ B ^ CIN) ? VDD : VSS ;
  assign COUT=((A && B) || (A && CIN) || (B && CIN)) ? VDD : VSS ;
endmodule
module FA(COUT, SUM, A, B, CIN, VDD, VSS );

  input A, B, CIN;
  output COUT, SUM;
  inout VDD, VSS;

  assign SUM=(A ^ B ^ CIN) ? VDD : VSS ;
  assign COUT=((A && B) || (A && CIN) || (B && CIN)) ? VDD : VSS ;
endmodule