data/full_repos/permissive/210946536/src/modules/instruction_fetch.v
 line:109: before: "integer"
1: b'%Warning-WIDTH: data/full_repos/permissive/210946536/src/modules/instruction_fetch.v:51: Operator SUB expects 33 bits on the LHS, but LHS\'s SIGNED generates 16 bits.\n                                                                                       : ... In instance instruction_fetch\n             4\'b1000: pc <= $signed({1\'b0, pc})+($signed(i_inm_i)-1)*4;  \n                                                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/210946536/src/modules/instruction_fetch.v:51: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s ADD generates 33 bits.\n                                                                                       : ... In instance instruction_fetch\n             4\'b1000: pc <= $signed({1\'b0, pc})+($signed(i_inm_i)-1)*4;  \n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/210946536/src/modules/instruction_fetch.v:53: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'i_inm_j\' generates 26 bits.\n                                                                                       : ... In instance instruction_fetch\n             4\'b0010: pc <= (pc & 32\'hF0000000) | (i_inm_j << 2);  \n                                                           ^~\n%Error: data/full_repos/permissive/210946536/src/modules/instruction_fetch.v:64: Cannot find file containing module: \'byte_enabled_dual_port\'\n   byte_enabled_dual_port\n   ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210946536/src/modules,data/full_repos/permissive/210946536/byte_enabled_dual_port\n             data/full_repos/permissive/210946536/src/modules,data/full_repos/permissive/210946536/byte_enabled_dual_port.v\n             data/full_repos/permissive/210946536/src/modules,data/full_repos/permissive/210946536/byte_enabled_dual_port.sv\n             byte_enabled_dual_port\n             byte_enabled_dual_port.v\n             byte_enabled_dual_port.sv\n             obj_dir/byte_enabled_dual_port\n             obj_dir/byte_enabled_dual_port.v\n             obj_dir/byte_enabled_dual_port.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module instruction_fetch
  #(
    parameter NB_REG             = 32,
    parameter NB_INSTR           = 32,
    parameter N_ADDR             = 2048,
    parameter NB_INM_I           = 16,
    parameter NB_INM_J           = 26,
    parameter INSTR_FILE         = ""
    )
   (
    output wire [NB_INSTR-1:0] o_ir,
    output reg [NB_REG-1:0]    o_pc,


    output wire [NB_REG-1:0]   o_debug_instrmem_data,
    output wire [NB_REG-1:0]   o_debug_system_pc,

    input wire [NB_INM_I-1:0]  i_inm_i,
    input wire [NB_INM_J-1:0]  i_inm_j,
    input wire [NB_REG-1:0]    i_rs,
    input wire                 i_hazard,

    input wire                 i_jump_inm,
    input wire                 i_jump_rs,
    input wire                 i_branch,


    input wire [16-1:0]        i_debug_instrmem_addr,
    input wire [NB_INSTR-1:0]  i_debug_instrmem_data,
    input wire [4-1:0]         i_debug_instrmem_we,
    input wire                 i_debug_instrmem_re,

    input wire                 i_clock,
    input wire                 i_reset,
    input wire                 i_valid
    ) ;
   localparam LOG2_N_INSMEM_ADDR = clogb2(N_ADDR-1);

   reg [NB_REG-1:0]            pc ;
   wire [NB_INSTR-1:0]         mem_ir ;

   assign o_debug_system_pc = pc;

   always @(posedge i_clock)
     begin
        if (i_reset) begin
           pc <= {NB_REG{1'b0}};
           o_pc <= {NB_REG{1'b0}};
        end else if (i_valid) begin
           case ({i_branch, i_jump_rs, i_jump_inm, i_hazard})
             4'b1000: pc <= $signed({1'b0, pc})+($signed(i_inm_i)-1)*4;
             4'b0100: pc <= i_rs;
             4'b0010: pc <= (pc & 32'hF0000000) | (i_inm_j << 2);
             4'b???1: pc <= pc;
             4'b0000: pc <= pc+4 ;
             default: pc <= pc;
           endcase
           o_pc <= pc+4;
        end
     end

   assign o_ir = mem_ir ;

   byte_enabled_dual_port
     #(
       .NB_COL          (4                                              ),
       .COL_WIDTH       (8                                              ),
       .RAM_DEPTH       (N_ADDR                                         ),
       .RAM_PERFORMANCE ("LOW_LATENCY"                                  ),
       .INIT_FILE       (INSTR_FILE                                     )
       )
   u_instruction_memory
     (
      .o_data_a         (mem_ir                                         ),
      .o_data_b         (o_debug_instrmem_data                          ),
      .i_addr_a         (pc[LOG2_N_INSMEM_ADDR+2-1-:LOG2_N_INSMEM_ADDR] ),
      .i_addr_b         (i_debug_instrmem_addr                          ),
      .i_data_a         ({32{1'b0}}                                     ),
      .i_data_b         (i_debug_instrmem_data                          ),
      .i_clock          (i_clock                                        ),
      .wea              (1'b0                                           ),
      .web              (i_debug_instrmem_we                            ),
      .ena              ((~i_hazard & i_valid) | i_reset                ),
      .enb              (i_debug_instrmem_re | |i_debug_instrmem_we     ),
      .i_reset_a        (i_reset                                        ),
      .i_reset_b        (i_reset                                        ),
      .i_rea            (1'b1                                           ),
      .i_reb            (1'b1                                           )
      );



   function integer clogb2;
      input integer                   depth;
      for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
   endfunction

endmodule
module instruction_fetch
  #(
    parameter NB_REG             = 32,
    parameter NB_INSTR           = 32,
    parameter N_ADDR             = 2048,
    parameter NB_INM_I           = 16,
    parameter NB_INM_J           = 26,
    parameter INSTR_FILE         = ""
    )
   (
    output wire [NB_INSTR-1:0] o_ir,
    output reg [NB_REG-1:0]    o_pc,


    output wire [NB_REG-1:0]   o_debug_instrmem_data,
    output wire [NB_REG-1:0]   o_debug_system_pc,

    input wire [NB_INM_I-1:0]  i_inm_i,
    input wire [NB_INM_J-1:0]  i_inm_j,
    input wire [NB_REG-1:0]    i_rs,
    input wire                 i_hazard,

    input wire                 i_jump_inm,
    input wire                 i_jump_rs,
    input wire                 i_branch,


    input wire [16-1:0]        i_debug_instrmem_addr,
    input wire [NB_INSTR-1:0]  i_debug_instrmem_data,
    input wire [4-1:0]         i_debug_instrmem_we,
    input wire                 i_debug_instrmem_re,

    input wire                 i_clock,
    input wire                 i_reset,
    input wire                 i_valid
    ) ;

   localparam LOG2_N_INSMEM_ADDR = clogb2(N_ADDR-1);

   reg [NB_REG-1:0]            pc ;
   wire [NB_INSTR-1:0]         mem_ir ;

   assign o_debug_system_pc = pc;

   always @(posedge i_clock)
     begin
        if (i_reset) begin
           pc <= {NB_REG{1'b0}};
           o_pc <= {NB_REG{1'b0}};
        end else if (i_valid) begin
           case ({i_branch, i_jump_rs, i_jump_inm, i_hazard})
             4'b1000: pc <= $signed({1'b0, pc})+($signed(i_inm_i)-1)*4;
             4'b0100: pc <= i_rs;
             4'b0010: pc <= (pc & 32'hF0000000) | (i_inm_j << 2);
             4'b???1: pc <= pc;
             4'b0000: pc <= pc+4 ;
             default: pc <= pc;
           endcase
           o_pc <= pc+4;
        end
     end

   assign o_ir = mem_ir ;

   byte_enabled_dual_port
     #(
       .NB_COL          (4                                              ),
       .COL_WIDTH       (8                                              ),
       .RAM_DEPTH       (N_ADDR                                         ),
       .RAM_PERFORMANCE ("LOW_LATENCY"                                  ),
       .INIT_FILE       (INSTR_FILE                                     )
       )
   u_instruction_memory
     (
      .o_data_a         (mem_ir                                         ),
      .o_data_b         (o_debug_instrmem_data                          ),
      .i_addr_a         (pc[LOG2_N_INSMEM_ADDR+2-1-:LOG2_N_INSMEM_ADDR] ),
      .i_addr_b         (i_debug_instrmem_addr                          ),
      .i_data_a         ({32{1'b0}}                                     ),
      .i_data_b         (i_debug_instrmem_data                          ),
      .i_clock          (i_clock                                        ),
      .wea              (1'b0                                           ),
      .web              (i_debug_instrmem_we                            ),
      .ena              ((~i_hazard & i_valid) | i_reset                ),
      .enb              (i_debug_instrmem_re | |i_debug_instrmem_we     ),
      .i_reset_a        (i_reset                                        ),
      .i_reset_b        (i_reset                                        ),
      .i_rea            (1'b1                                           ),
      .i_reb            (1'b1                                           )
      );



   function integer clogb2;
      input integer                   depth;
      for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
   endfunction

endmodule