data/full_repos/permissive/194847941/demo/6_uart_loopback/source/rtl/uart_top.v
'utf-8' codec can't decode byte 0xcf in position 269: invalid continuation byte
1: b"%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/source/rtl/uart_top.v:41: Cannot find file containing module: 'pll_test'\npll_test u_pll_test\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/6_uart_loopback/source/rtl,data/full_repos/permissive/194847941/pll_test\n             data/full_repos/permissive/194847941/demo/6_uart_loopback/source/rtl,data/full_repos/permissive/194847941/pll_test.v\n             data/full_repos/permissive/194847941/demo/6_uart_loopback/source/rtl,data/full_repos/permissive/194847941/pll_test.sv\n             pll_test\n             pll_test.v\n             pll_test.sv\n             obj_dir/pll_test\n             obj_dir/pll_test.v\n             obj_dir/pll_test.sv\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/source/rtl/uart_top.v:52: Cannot find file containing module: 'speed_setting'\nspeed_setting\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/source/rtl/uart_top.v:67: Cannot find file containing module: 'my_uart_rx'\nmy_uart_rx my_uart_rx\n^~~~~~~~~~\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/source/rtl/uart_top.v:81: Cannot find file containing module: 'speed_setting'\nspeed_setting\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/source/rtl/uart_top.v:95: Cannot find file containing module: 'my_uart_tx'\nmy_uart_tx my_uart_tx\n^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module uart_top
#(
    parameter BPS_SET      =   96,
    parameter CLK_PERIORD  =   40
)
(
	input 	wire	ext_clk_25m,
	input 	wire	ext_rst_n,
	input 	wire	uart_rx,
	output 	wire	uart_tx
);													


wire clk_25m;
wire clk_50m;
wire clk_100m;
wire sys_rst_n;


wire bps_start1,bps_start2;
wire clk_bps1,clk_bps2;
wire [7:0] rx_data;
wire rx_int;



pll_test u_pll_test
(
	.refclk		    (ext_clk_25m	),
	.reset		    (~ext_rst_n		),
	.extlock	    (sys_rst_n		),
	.clk0_out	    (clk_25m		),
	.clk1_out	    (clk_50m		),
	.clk2_out	    (clk_100m		)
);


speed_setting
#(
	.BPS_SET	    (BPS_SET	    ),
	.CLK_PERIORD	(CLK_PERIORD    )
)
speed_rx

(	
    .clk            (clk_25m        ),
    .rst_n          (sys_rst_n      ),
    .bps_start      (bps_start1     ),
    .clk_bps        (clk_bps1       )
);


my_uart_rx	my_uart_rx
(		
	.clk            (clk_25m        ),
	.rst_n          (sys_rst_n      ),
	.uart_rx        (uart_rx        ),
	.rx_data        (rx_data        ),
	.rx_int         (rx_int         ),
	.clk_bps        (clk_bps1       ),
	.bps_start      (bps_start1     )
);
		



speed_setting
#(
	.BPS_SET	    (BPS_SET	    ),
	.CLK_PERIORD	(CLK_PERIORD	)
)
speed_tx
(	
	.clk            (clk_25m        ),
	.rst_n          (sys_rst_n      ),
	.bps_start      (bps_start2     ),
	.clk_bps        (clk_bps2       )
);
						

my_uart_tx	my_uart_tx
(		
	.clk            (clk_25m        ),
	.rst_n          (sys_rst_n      ),
	.rx_data        (rx_data        ),
	.rx_int         (rx_int         ),
	.uart_tx        (uart_tx        ),
	.clk_bps        (clk_bps2       ),
	.bps_start      (bps_start2     )
);


endmodule
module uart_top
#(
    parameter BPS_SET      =   96,
    parameter CLK_PERIORD  =   40
)
(
	input 	wire	ext_clk_25m,
	input 	wire	ext_rst_n,
	input 	wire	uart_rx,
	output 	wire	uart_tx
);
													


wire clk_25m;
wire clk_50m;
wire clk_100m;
wire sys_rst_n;


wire bps_start1,bps_start2;
wire clk_bps1,clk_bps2;
wire [7:0] rx_data;
wire rx_int;



pll_test u_pll_test
(
	.refclk		    (ext_clk_25m	),
	.reset		    (~ext_rst_n		),
	.extlock	    (sys_rst_n		),
	.clk0_out	    (clk_25m		),
	.clk1_out	    (clk_50m		),
	.clk2_out	    (clk_100m		)
);


speed_setting
#(
	.BPS_SET	    (BPS_SET	    ),
	.CLK_PERIORD	(CLK_PERIORD    )
)
speed_rx

(	
    .clk            (clk_25m        ),
    .rst_n          (sys_rst_n      ),
    .bps_start      (bps_start1     ),
    .clk_bps        (clk_bps1       )
);


my_uart_rx	my_uart_rx
(		
	.clk            (clk_25m        ),
	.rst_n          (sys_rst_n      ),
	.uart_rx        (uart_rx        ),
	.rx_data        (rx_data        ),
	.rx_int         (rx_int         ),
	.clk_bps        (clk_bps1       ),
	.bps_start      (bps_start1     )
);
		



speed_setting
#(
	.BPS_SET	    (BPS_SET	    ),
	.CLK_PERIORD	(CLK_PERIORD	)
)
speed_tx
(	
	.clk            (clk_25m        ),
	.rst_n          (sys_rst_n      ),
	.bps_start      (bps_start2     ),
	.clk_bps        (clk_bps2       )
);
						

my_uart_tx	my_uart_tx
(		
	.clk            (clk_25m        ),
	.rst_n          (sys_rst_n      ),
	.rx_data        (rx_data        ),
	.rx_int         (rx_int         ),
	.uart_tx        (uart_tx        ),
	.clk_bps        (clk_bps2       ),
	.bps_start      (bps_start2     )
);


endmodule