data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:277: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n   if ( ram_wptr >= (kernel_m - 1) )\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:312: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n     field_con_idx[y] <= ( ram_wptr_sync[1] + kernel_m - y - kernel_m );\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:312: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n     field_con_idx[y] <= ( ram_wptr_sync[1] + kernel_m - y - kernel_m );\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:314: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n     field_con_idx[y] <= ( ram_wptr_sync[1] + kernel_m - y );\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:311: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n    else if((( ram_wptr_sync[1] + kernel_m - y ) > kernel_m ) && (( ram_wptr_sync[1] + kernel_m - y ) < ( kernel_m <<< 1 )))\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:311: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n    else if((( ram_wptr_sync[1] + kernel_m - y ) > kernel_m ) && (( ram_wptr_sync[1] + kernel_m - y ) < ( kernel_m <<< 1 )))\n                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:311: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n    else if((( ram_wptr_sync[1] + kernel_m - y ) > kernel_m ) && (( ram_wptr_sync[1] + kernel_m - y ) < ( kernel_m <<< 1 )))\n                                                                                                                   ^~~\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:309: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n    if ((( ram_wptr_sync[1] + kernel_m - y ) == kernel_m ) || (( ram_wptr_sync[1] + kernel_m - y ) == ( kernel_m <<< 1 )))\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:309: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n    if ((( ram_wptr_sync[1] + kernel_m - y ) == kernel_m ) || (( ram_wptr_sync[1] + kernel_m - y ) == ( kernel_m <<< 1 )))\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:309: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n    if ((( ram_wptr_sync[1] + kernel_m - y ) == kernel_m ) || (( ram_wptr_sync[1] + kernel_m - y ) == ( kernel_m <<< 1 )))\n                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:309: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n    if ((( ram_wptr_sync[1] + kernel_m - y ) == kernel_m ) || (( ram_wptr_sync[1] + kernel_m - y ) == ( kernel_m <<< 1 )))\n                                                                                                                 ^~~\n%Warning-SELRANGE: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:461: Selection index out of range: 9 outside 8:0\n                                                                                                           : ... In instance npu_conv_rtl\n      ATnode[ at_node_idx ] <= field_mult[ at_node_idx ];\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:461: Selection index out of range: 10 outside 8:0\n                                                                                                           : ... In instance npu_conv_rtl\n      ATnode[ at_node_idx ] <= field_mult[ at_node_idx ];\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:461: Selection index out of range: 11 outside 8:0\n                                                                                                           : ... In instance npu_conv_rtl\n      ATnode[ at_node_idx ] <= field_mult[ at_node_idx ];\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:461: Selection index out of range: 12 outside 8:0\n                                                                                                           : ... In instance npu_conv_rtl\n      ATnode[ at_node_idx ] <= field_mult[ at_node_idx ];\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:461: Selection index out of range: 13 outside 8:0\n                                                                                                           : ... In instance npu_conv_rtl\n      ATnode[ at_node_idx ] <= field_mult[ at_node_idx ];\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:461: Selection index out of range: 14 outside 8:0\n                                                                                                           : ... In instance npu_conv_rtl\n      ATnode[ at_node_idx ] <= field_mult[ at_node_idx ];\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:461: Selection index out of range: 15 outside 8:0\n                                                                                                           : ... In instance npu_conv_rtl\n      ATnode[ at_node_idx ] <= field_mult[ at_node_idx ];\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:518: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'kernel_n\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n  div_denom   <= kernel_n;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:525: Operator COND expects 57 bits on the Conditional False, but Conditional False\'s VARREF \'DATA_UNIT\' generates 32 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n  div_denom   <= ( arith_type == POOL_TYPE && pool_type == MEAN_TYPE )? {32\'D0, ( kernel_m * kernel_n ), {FRAC_WIDTH{1\'B0}}} : DATA_UNIT;\n                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:525: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 57 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n  div_denom   <= ( arith_type == POOL_TYPE && pool_type == MEAN_TYPE )? {32\'D0, ( kernel_m * kernel_n ), {FRAC_WIDTH{1\'B0}}} : DATA_UNIT;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:560: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'kernel_n\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n  if ( ConvCycCol >= ( kernel_n - 1 ) || ConvResCol >= ( width - 1 ))\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:568: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n   if ( ConvCycRow >= ( kernel_m - 1 ))\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:579: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'kernel_n\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\nassign write_data_validx = ( arith_type == CONV_TYPE )? ( pool_opt_col_rdy && div_dst_en && ( ConvResCol >= ( kernel_n - 1 )) && ( ConvResRow >= ( kernel_m - 1 )) ) : \n                                                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:579: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\nassign write_data_validx = ( arith_type == CONV_TYPE )? ( pool_opt_col_rdy && div_dst_en && ( ConvResCol >= ( kernel_n - 1 )) && ( ConvResRow >= ( kernel_m - 1 )) ) : \n                                                                                                                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:580: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'kernel_n\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n       ( arith_type == POOL_TYPE )? ( pool_opt_col_rdy && div_dst_en && ( ConvCycCol == ( kernel_n - 1 )) && ( ConvCycRow == ( kernel_m - 1 )) ) : \n                                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:580: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'kernel_m\' generates 9 bits.\n                                                                                                        : ... In instance npu_conv_rtl\n       ( arith_type == POOL_TYPE )? ( pool_opt_col_rdy && div_dst_en && ( ConvCycCol == ( kernel_n - 1 )) && ( ConvCycRow == ( kernel_m - 1 )) ) : \n                                                                                                                                        ^\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:609: Cannot find file containing module: \'fixed_sdiv\'\nfixed_sdiv u0_fixed_sdiv\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu,data/full_repos/permissive/143584361/fixed_sdiv\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu,data/full_repos/permissive/143584361/fixed_sdiv.v\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu,data/full_repos/permissive/143584361/fixed_sdiv.sv\n             fixed_sdiv\n             fixed_sdiv.v\n             fixed_sdiv.sv\n             obj_dir/fixed_sdiv\n             obj_dir/fixed_sdiv.v\n             obj_dir/fixed_sdiv.sv\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/npu/npu_conv_rtl.v:631: Cannot find file containing module: \'dpram_2p\'\n  dpram_2p \n  ^~~~~~~~\n%Error: Exiting due to 2 error(s), 27 warning(s)\n'
function integer CeilLog2;
	input	[31:0]	size;
	integer i;
begin	
	CeilLog2 = 1;
	for ( i = 1; 2 ** i < size; i = i + 1 )
		CeilLog2 = i + 1;
end		
endfunction
function integer CeilLog2;

	input	[31:0]	size;
	integer i;
begin	
	CeilLog2 = 1;
	for ( i = 1; 2 ** i < size; i = i + 1 )
		CeilLog2 = i + 1;
end		
endfunction