data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v
'utf-8' codec can't decode byte 0xbe in position 25: invalid start byte
1: b'%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:2: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.v\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:43: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n   if(stopFlag == `False) begin\n                  ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:43: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   if(stopFlag == `False) begin\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:45: Unsupported: Ignoring delay on this delayed statement.\n       #50 clk = 1\'b0;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:46: syntax error, unexpected else\n   end else begin\n       ^~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:55: Define or directive not defined: \'`True\'\n  if (rst == `True) begin\n             ^~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:55: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (rst == `True) begin\n                  ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/test0.v:63: syntax error, unexpected $display\n     $display("regs[%d] = %d",i ,top.cpu.regFile.regs[i]);\n     ^~~~~~~~\n%Error: Cannot continue\n'
module test0();

	reg clk,rst;
	reg stopFlag;
	Top top(
	    	.clk(clk),
	    	.rst(rst));
    initial begin

		$readmemh("insts.mem",	top.cpu.iCache.inst);
    	clk = 1'b0;
    	stopFlag = 1'b0;
    	forever begin
			if(stopFlag == `False) begin
				#50 clk = 1'b1;
	    		#50 clk = 1'b0;
			end else begin
				#50;
			end
    	end
    end
	reg [31:0] count;
	reg [31:0] i;
	always @( posedge clk ) begin
		$display("newCLK");
		if (rst == `True) begin
			count <= 0;
		end else begin
			if(count == 50) begin
				stopFlag = 1'b1;
				$display("end");
				#200;
				for(i=0;i<32;i=i+1) begin
					$display("regs[%d] = %d",i ,top.cpu.regFile.regs[i]);
				end
				$stop;
			end
			$display("[Clock]: %d",count );
			count <= count + 1;
		end
	end
    initial begin
    	rst = 1'b1;
    	#200 rst = 1'b0;

    end
endmodule
module test0();


	reg clk,rst;
	reg stopFlag;
	Top top(
	    	.clk(clk),
	    	.rst(rst));
    initial begin

		$readmemh("insts.mem",	top.cpu.iCache.inst);
    	clk = 1'b0;
    	stopFlag = 1'b0;
    	forever begin
			if(stopFlag == `False) begin
				#50 clk = 1'b1;
	    		#50 clk = 1'b0;
			end else begin
				#50;
			end
    	end
    end
	reg [31:0] count;
	reg [31:0] i;
	always @( posedge clk ) begin
		$display("newCLK");
		if (rst == `True) begin
			count <= 0;
		end else begin
			if(count == 50) begin
				stopFlag = 1'b1;
				$display("end");
				#200;
				for(i=0;i<32;i=i+1) begin
					$display("regs[%d] = %d",i ,top.cpu.regFile.regs[i]);
				end
				$stop;
			end
			$display("[Clock]: %d",count );
			count <= count + 1;
		end
	end
    initial begin
    	rst = 1'b1;
    	#200 rst = 1'b0;

    end
endmodule