data/full_repos/permissive/143278/ivltests/pr2224949.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2224949.v:12: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2224949.v:8: Input port connection \'a\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'a\' generates 64 bits.\n                                                                        : ... In instance t\nam dut(a, b);\n       ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2224949.v:8: Output port connection \'b\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'b\' generates 64 bits.\n                                                                        : ... In instance t\nam dut(a, b);\n          ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module am(
	a, b
);

input [15:0] a;
output [15:0] b;

assign b = a ^ 1;

endmodule
module am(
	a, b
);


input [15:0] a;
output [15:0] b;

assign b = a ^ 1;

endmodule