data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder1.v
 line:50: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder1.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder1.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Error: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder1.v:32: Cannot find file containing module: \'padder1\'\n    padder1 uut (\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21918028/high_throughput_core/testbench,data/full_repos/permissive/21918028/padder1\n             data/full_repos/permissive/21918028/high_throughput_core/testbench,data/full_repos/permissive/21918028/padder1.v\n             data/full_repos/permissive/21918028/high_throughput_core/testbench,data/full_repos/permissive/21918028/padder1.sv\n             padder1\n             padder1.v\n             padder1.sv\n             obj_dir/padder1\n             obj_dir/padder1.v\n             obj_dir/padder1.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_padder1;


    reg [63:0] in;
    reg [2:0] byte_num;


    wire [63:0] out;
    
    reg [63:0] wish;


    padder1 uut (
        .in(in),
        .byte_num(byte_num),
        .out(out)
    );

    initial begin

        in = 0;
        byte_num = 0;


        #100;


        in = 64'h1234567890ABCDEF;
        byte_num = 0;
        wish = {8'h01, 56'h0};
        check;
        byte_num = 1;
        wish = 64'h1201000000000000;
        check;
        byte_num = 2;
        wish = 64'h1234010000000000;
        check;
        byte_num = 3;
        wish = 64'h1234560100000000;
        check;
        byte_num = 4;
        wish = 64'h1234567801000000;
        check;
        byte_num = 5;
        wish = 64'h1234567890010000;
        check;
        byte_num = 6;
        wish = 64'h1234567890AB0100;
        check;
        byte_num = 7;
        wish = 64'h1234567890ABCD01;
        check;
        $display("Good!");
        $finish;
    end

    task check;
      begin
        #(`P);
        if (out !== wish)
          begin
            $display("E");
            $finish;
          end
      end
    endtask
endmodule
module test_padder1;



    reg [63:0] in;
    reg [2:0] byte_num;


    wire [63:0] out;
    
    reg [63:0] wish;


    padder1 uut (
        .in(in),
        .byte_num(byte_num),
        .out(out)
    );

    initial begin

        in = 0;
        byte_num = 0;


        #100;


        in = 64'h1234567890ABCDEF;
        byte_num = 0;
        wish = {8'h01, 56'h0};
        check;
        byte_num = 1;
        wish = 64'h1201000000000000;
        check;
        byte_num = 2;
        wish = 64'h1234010000000000;
        check;
        byte_num = 3;
        wish = 64'h1234560100000000;
        check;
        byte_num = 4;
        wish = 64'h1234567801000000;
        check;
        byte_num = 5;
        wish = 64'h1234567890010000;
        check;
        byte_num = 6;
        wish = 64'h1234567890AB0100;
        check;
        byte_num = 7;
        wish = 64'h1234567890ABCD01;
        check;
        $display("Good!");
        $finish;
    end

    task check;
      begin
        #(`P);
        if (out !== wish)
          begin
            $display("E");
            $finish;
          end
      end
    endtask
endmodule