data/full_repos/permissive/143278/vpi/br_ml20191013.v
 line:25: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vpi/br_ml20191013.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("$pow(2,3) returns %d", $pow(2,3));\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/vpi/br_ml20191013.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #1 result = $pow(a,b);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/vpi/br_ml20191013.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("$pow(a,b) returns %d (a=%d b=%d)", result, a, b);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/vpi/br_ml20191013.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #1 $finish(0);\n      ^\n%Warning-REALCVT: data/full_repos/permissive/143278/vpi/br_ml20191013.v:26: Implicit conversion of real to integer\n      #1 result = $pow(a,b);\n                  ^~~~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

  reg [31:0]  result;
  reg         a, b;

  initial
    begin
      $display("Start simulation pow_test.v");
      a = 1;
      b = 0;


      #1 $display("$pow(2,3) returns %d", $pow(2,3));
      #1 result = $pow(a,b);
      #1 $display("$pow(a,b) returns %d (a=%d b=%d)", result, a, b);
      #1 $finish(0);
    end

endmodule
module test;


  reg [31:0]  result;
  reg         a, b;

  initial
    begin
      $display("Start simulation pow_test.v");
      a = 1;
      b = 0;


      #1 $display("$pow(2,3) returns %d", $pow(2,3));
      #1 result = $pow(a,b);
      #1 $display("$pow(a,b) returns %d (a=%d b=%d)", result, a, b);
      #1 $finish(0);
    end

endmodule