data/full_repos/permissive/196851857/datapath/adder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/196851857/datapath/adder.v:13: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'ci\' generates 1 bits.\n                                                                        : ... In instance adder\n  assign {co,sum}=a+b+ci;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module adder(a, b, ci, 
  sum, co, cf, zf, sf, of
);
  parameter WIDTH = 32;
  
  input [WIDTH-1:0] a,b;
  input ci;

  output [WIDTH-1:0] sum;
  output co;
  output cf,zf,sf,of;

  assign {co,sum}=a+b+ci;
  assign sf = sum[WIDTH-1];
  assign of = (sf^a[WIDTH-1])&(sf^b[WIDTH-1]);
  assign zf = sum==0 ? 1 : 0;
  assign cf = co^ci;
endmodule
module adder(a, b, ci, 
  sum, co, cf, zf, sf, of
);

  parameter WIDTH = 32;
  
  input [WIDTH-1:0] a,b;
  input ci;

  output [WIDTH-1:0] sum;
  output co;
  output cf,zf,sf,of;

  assign {co,sum}=a+b+ci;
  assign sf = sum[WIDTH-1];
  assign of = (sf^a[WIDTH-1])&(sf^b[WIDTH-1]);
  assign zf = sum==0 ? 1 : 0;
  assign cf = co^ci;
endmodule