data/full_repos/permissive/121410129/Step3/GrayCounter_Nbit_Pulse.v
data/verilator_xmls/3ed56f9d-e7a4-4125-aa46-0251d328bacf.xml
module GrayCounter_Pulse(clk, reset, pulse);
input wire clk, reset;
output reg pulse;

parameter distance = 100000000;
reg [26:0]counter;

always @(posedge clk or posedge reset) begin
	if (reset == 1'b1) begin

		counter <= 27'd0;
		pulse 	<= 1'b0;
	end
	else begin

			if (counter == distance) begin
				pulse 	<= 1'b1;
				counter <= 27'd0;
			end
			else begin
				pulse 	<= 1'b0;
				counter <= counter + 1;
			end
	end
end

endmodule
module GrayCounter_Pulse(clk, reset, pulse);

input wire clk, reset;
output reg pulse;

parameter distance = 100000000;
reg [26:0]counter;

always @(posedge clk or posedge reset) begin
	if (reset == 1'b1) begin

		counter <= 27'd0;
		pulse 	<= 1'b0;
	end
	else begin

			if (counter == distance) begin
				pulse 	<= 1'b1;
				counter <= 27'd0;
			end
			else begin
				pulse 	<= 1'b0;
				counter <= counter + 1;
			end
	end
end

endmodule