data/full_repos/permissive/173003307/src/processor.v
1: b'%Warning-WIDTH: data/full_repos/permissive/173003307/src/processor.v:75: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'CurrProgCounterOffset\' generates 2 bits.\n                                                                       : ... In instance Processor\n    assign ActualAddress = CurrProgCounter + CurrProgCounterOffset;\n                                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/173003307/src/processor.v:84: Cannot find file containing module: \'ALU\'\n    ALU ALU0(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/173003307/src,data/full_repos/permissive/173003307/ALU\n             data/full_repos/permissive/173003307/src,data/full_repos/permissive/173003307/ALU.v\n             data/full_repos/permissive/173003307/src,data/full_repos/permissive/173003307/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module Processor(

                    input CLK,
                    input RESET,

                    inout [7:0] BUS_DATA,
                    output [7:0] BUS_ADDR,
                    output BUS_WE,

                    output [7:0] ROM_ADDRESS,
                    input [7:0] ROM_DATA,

                    input [1:0] BUS_INTERRUPTS_RAISE,
                    output [1:0] BUS_INTERRUPTS_ACK
                    );
                    


    wire [7:0] BusDataIn;
    reg [7:0] CurrBusDataOut, NextBusDataOut;
    reg CurrBusDataOutWE, NextBusDataOutWE;
    

    assign BusDataIn = BUS_DATA;
    assign BUS_DATA = CurrBusDataOutWE ? CurrBusDataOut : 8'hZZ;
    assign BUS_WE = CurrBusDataOutWE;
    

    reg [7:0] CurrBusAddr, NextBusAddr;
    
    assign BUS_ADDR = CurrBusAddr;
    


    reg [7:0] CurrRegA, NextRegA;
    reg [7:0] CurrRegB, NextRegB;
    reg CurrRegSelect, NextRegSelect;
    reg [7:0] CurrProgContext, NextProgContext;

    reg [1:0] CurrInterruptAck, NextInterruptAck;
    
    assign BUS_INTERRUPTS_ACK = CurrInterruptAck;
    



    reg [7:0] CurrProgCounter, NextProgCounter;
    reg [1:0] CurrProgCounterOffset, NextProgCounterOffset;
    wire [7:0] ProgMemoryOut;
    wire [7:0] ActualAddress;
    
    assign ActualAddress = CurrProgCounter + CurrProgCounterOffset;
    

    assign ROM_ADDRESS = ActualAddress;
    assign ProgMemoryOut = ROM_DATA;
    


    wire [7:0] AluOut;
    ALU ALU0(

            .CLK(CLK),
            .RESET(RESET),

            .IN_A(CurrRegA),
            .IN_B(CurrRegB),
            .ALU_Op_Code(ProgMemoryOut[7:4]),
            .OUT_RESULT(AluOut)
            );
            

















    
    parameter [7:0]
    
    IDLE = 8'hF0,
    GET_THREAD_START_ADDR_0 = 8'hF1,
    GET_THREAD_START_ADDR_1 = 8'hF2,
    GET_THREAD_START_ADDR_2 = 8'hF3,
    


    CHOOSE_OPP = 8'h00,
    

    READ_FROM_MEM_TO_A = 8'h10,
    READ_FROM_MEM_TO_B = 8'h11,
    READ_FROM_MEM_0 = 8'h12,
    READ_FROM_MEM_1 = 8'h13,
    READ_FROM_MEM_2 = 8'h14,
    WRITE_TO_MEM_FROM_A = 8'h20,
    WRITE_TO_MEM_FROM_B = 8'h21,
    WRITE_TO_MEM_0 = 8'h22,
    

    DO_MATHS_OPP_SAVE_IN_A = 8'h30,
    DO_MATHS_OPP_SAVE_IN_B = 8'h31,
    DO_MATHS_OPP_0 = 8'h32,
    

    IF_A_EQUALITY_B_GOTO   = 8'h40,
    IF_A_EQUALITY_B_GOTO_0 = 8'h41,
    IF_A_EQUALITY_B_GOTO_1 = 8'h42,
    

    GOTO_ADDR            = 8'h50,
    GOTO_ADDR_0          = 8'h51,
    GOTO_ADDR_1          = 8'h52,
    GOTO_IDLE            = 8'h53,
    

    FUNCTION_START       = 8'h60,
    FUNCTION_START_0     = 8'h61,
    FUNCTION_START_1     = 8'h62,
    RETURN               = 8'h63,
    RETURN_0             = 8'h64,
    

    DEREFERENCE_A        = 8'h70,
    DEREFERENCE_B        = 8'h71,     
    DEREFERENCE_0        = 8'h72,
    DEREFERENCE_1        = 8'h73,
    DEREFERENCE_2        = 8'h74;
        

    reg [7:0] CurrState, NextState;
    always@(posedge CLK) 
    begin
        if(RESET) 
        begin
            CurrState = 8'h00;
            CurrProgCounter = 8'h00;
            CurrProgCounterOffset = 2'h0;
            CurrBusAddr = 8'hFF;
            CurrBusDataOut = 8'h00;
            CurrBusDataOutWE = 1'b0;
            CurrRegA = 8'h00;
            CurrRegB = 8'h00;
            CurrRegSelect = 1'b0;
            CurrProgContext = 8'h00;
            CurrInterruptAck = 2'b00;
        end 
        
        else 
        
        begin
            CurrState = NextState;
            CurrProgCounter = NextProgCounter;
            CurrProgCounterOffset = NextProgCounterOffset;
            CurrBusAddr = NextBusAddr;
            CurrBusDataOut = NextBusDataOut;
            CurrBusDataOutWE = NextBusDataOutWE;
            CurrRegA = NextRegA;
            CurrRegB = NextRegB;
            CurrRegSelect = NextRegSelect;
            CurrProgContext = NextProgContext;
            CurrInterruptAck = NextInterruptAck;
        end
    end
    

    always@* 
    begin

        NextState = CurrState;
        NextProgCounter = CurrProgCounter;
        NextProgCounterOffset = 2'h0;
        NextBusAddr = 8'hFF;
        NextBusDataOut = CurrBusDataOut;
        NextBusDataOutWE = 1'b0;
        NextRegA = CurrRegA;
        NextRegB = CurrRegB;
        NextRegSelect = CurrRegSelect;
        NextProgContext = CurrProgContext;
        NextInterruptAck = 2'b00;

        case (CurrState)


            IDLE: 
            begin
                if(BUS_INTERRUPTS_RAISE[0]) begin
                    NextState = GET_THREAD_START_ADDR_0;
                    NextProgCounter = 8'hFF;
                    NextInterruptAck = 2'b01;
                end 
                
                else if(BUS_INTERRUPTS_RAISE[1]) begin
                    NextState = GET_THREAD_START_ADDR_0;
                    NextProgCounter = 8'hFE;
                    NextInterruptAck = 2'b10;
                end 
                
                else 
                begin
                    NextState = IDLE;
                    NextProgCounter = 8'hF0;
                    NextInterruptAck = 2'b00;
                end
            end
            

            GET_THREAD_START_ADDR_0: 
            begin
                NextState = GET_THREAD_START_ADDR_1;
            end
            

            GET_THREAD_START_ADDR_1: 
            begin
                NextState = GET_THREAD_START_ADDR_2;
                NextProgCounter = ProgMemoryOut;
            end
            

            GET_THREAD_START_ADDR_2:
            begin
                NextState = CHOOSE_OPP;
            end
            


            CHOOSE_OPP: 
            begin
                 case (ProgMemoryOut[3:0])
                     4'h0: NextState = READ_FROM_MEM_TO_A;
                     4'h1: NextState = READ_FROM_MEM_TO_B;
                     4'h2: NextState = WRITE_TO_MEM_FROM_A;
                     4'h3: NextState = WRITE_TO_MEM_FROM_B;
                     4'h4: NextState = DO_MATHS_OPP_SAVE_IN_A;
                     4'h5: NextState = DO_MATHS_OPP_SAVE_IN_B;
                     4'h6: NextState = IF_A_EQUALITY_B_GOTO;
                     4'h7: NextState = GOTO_ADDR;
                     4'h8: NextState = GOTO_IDLE;
                     4'h9: NextState = FUNCTION_START;
                     4'hA: NextState = RETURN;
                     4'hB: NextState = DEREFERENCE_A;
                     4'hC: NextState = DEREFERENCE_B;
                     default:
                           NextState = CurrState;
                 endcase
                 
                 NextProgCounterOffset = 2'h1;
            end
            



            READ_FROM_MEM_TO_A:
            begin
                NextState = READ_FROM_MEM_0;
                NextRegSelect = 1'b0;
            end
            


            READ_FROM_MEM_TO_B:
            begin
                NextState = READ_FROM_MEM_0;
                NextRegSelect = 1'b1;
            end
            

            READ_FROM_MEM_0: 
            begin
                NextState = READ_FROM_MEM_1;
                NextBusAddr = ProgMemoryOut;
            end
            



            READ_FROM_MEM_1: 
            begin
                NextState = READ_FROM_MEM_2;
                NextProgCounter = CurrProgCounter + 2;
            end
            

            READ_FROM_MEM_2: 
            begin
                NextState = CHOOSE_OPP;
                if(!CurrRegSelect)
                    NextRegA = BusDataIn;
                else
                    NextRegB = BusDataIn;
            end
            





            WRITE_TO_MEM_FROM_A:
            begin
                NextState = WRITE_TO_MEM_0;
                NextRegSelect = 1'b0;
                NextProgCounter = CurrProgCounter + 2;
            end
            




            WRITE_TO_MEM_FROM_B:
            begin
                NextState = WRITE_TO_MEM_0;
                NextRegSelect = 1'b1;
                NextProgCounter = CurrProgCounter + 2;
            end
            


            WRITE_TO_MEM_0: 
            begin
                NextState = CHOOSE_OPP;
                NextBusAddr = ProgMemoryOut;
                if(!NextRegSelect)
                    NextBusDataOut = CurrRegA;
                else
                    NextBusDataOut = CurrRegB;
                NextBusDataOutWE = 1'b1;
            end
            





            DO_MATHS_OPP_SAVE_IN_A: 
            begin
                NextState = DO_MATHS_OPP_0;
                NextRegA = AluOut;
                NextProgCounter = CurrProgCounter + 1;
            end


            DO_MATHS_OPP_SAVE_IN_B: 
            begin
                NextState = DO_MATHS_OPP_0;
                NextRegB = AluOut;
                NextProgCounter = CurrProgCounter + 1;
            end
            

            DO_MATHS_OPP_0: 
                NextState = CHOOSE_OPP;
            



            IF_A_EQUALITY_B_GOTO:
                NextState = IF_A_EQUALITY_B_GOTO_0;
            IF_A_EQUALITY_B_GOTO_0:
            begin
            NextState = IF_A_EQUALITY_B_GOTO_1;
                if (AluOut == 8'h01)
                begin

                    NextProgCounter = ProgMemoryOut;
                end
                else
                begin
                    NextProgCounter = CurrProgCounter + 2;
                end
            end

            IF_A_EQUALITY_B_GOTO_1:
            begin
                NextState = CHOOSE_OPP;
            end
            
            GOTO_ADDR:
                NextState = GOTO_ADDR_0;
            
            GOTO_ADDR_0:
            begin
                NextProgCounter =  ProgMemoryOut;
                NextState = GOTO_ADDR_1;
            end
            
            GOTO_ADDR_1:
                NextState = CHOOSE_OPP;

            FUNCTION_START:
            begin
                NextState = FUNCTION_START_0;
                NextProgContext = CurrProgCounter + 2;
            end
            
            FUNCTION_START_0:
            begin
                NextProgCounter = ProgMemoryOut;
                NextState = FUNCTION_START_1;
            end
            
            FUNCTION_START_1:
                NextState = CHOOSE_OPP;
            
            RETURN:
            begin
                NextState = RETURN_0;
                NextProgCounter = CurrProgContext; 
            end
            RETURN_0:
                NextState = CHOOSE_OPP;
                

            
            DEREFERENCE_A:
            begin
                NextState = DEREFERENCE_0;
                NextRegSelect = 1'b0;
            end
            
            DEREFERENCE_B:
            begin
                NextState = DEREFERENCE_0;
                NextRegSelect = 1'b1;
            end
            
            DEREFERENCE_0:
            begin
                NextState = DEREFERENCE_1;
                if (CurrRegSelect)
                    NextBusAddr = CurrRegB;   
                else if (~CurrRegSelect)
                    NextBusAddr = CurrRegA;
            end
            
            DEREFERENCE_1:
            begin
                NextState = DEREFERENCE_2;
                NextProgCounter = CurrProgCounter + 1;
            end
            
            DEREFERENCE_2:
            begin
                NextState = CHOOSE_OPP;
            
                if(!CurrRegSelect)
                    NextRegA = BusDataIn;
                else
                    NextRegB = BusDataIn;
            end
            
            GOTO_IDLE:
            begin
                NextState = IDLE;
            end
        endcase
    end
    
    
    endmodule
module Processor(

                    input CLK,
                    input RESET,

                    inout [7:0] BUS_DATA,
                    output [7:0] BUS_ADDR,
                    output BUS_WE,

                    output [7:0] ROM_ADDRESS,
                    input [7:0] ROM_DATA,

                    input [1:0] BUS_INTERRUPTS_RAISE,
                    output [1:0] BUS_INTERRUPTS_ACK
                    );

                    


    wire [7:0] BusDataIn;
    reg [7:0] CurrBusDataOut, NextBusDataOut;
    reg CurrBusDataOutWE, NextBusDataOutWE;
    

    assign BusDataIn = BUS_DATA;
    assign BUS_DATA = CurrBusDataOutWE ? CurrBusDataOut : 8'hZZ;
    assign BUS_WE = CurrBusDataOutWE;
    

    reg [7:0] CurrBusAddr, NextBusAddr;
    
    assign BUS_ADDR = CurrBusAddr;
    


    reg [7:0] CurrRegA, NextRegA;
    reg [7:0] CurrRegB, NextRegB;
    reg CurrRegSelect, NextRegSelect;
    reg [7:0] CurrProgContext, NextProgContext;

    reg [1:0] CurrInterruptAck, NextInterruptAck;
    
    assign BUS_INTERRUPTS_ACK = CurrInterruptAck;
    



    reg [7:0] CurrProgCounter, NextProgCounter;
    reg [1:0] CurrProgCounterOffset, NextProgCounterOffset;
    wire [7:0] ProgMemoryOut;
    wire [7:0] ActualAddress;
    
    assign ActualAddress = CurrProgCounter + CurrProgCounterOffset;
    

    assign ROM_ADDRESS = ActualAddress;
    assign ProgMemoryOut = ROM_DATA;
    


    wire [7:0] AluOut;
    ALU ALU0(

            .CLK(CLK),
            .RESET(RESET),

            .IN_A(CurrRegA),
            .IN_B(CurrRegB),
            .ALU_Op_Code(ProgMemoryOut[7:4]),
            .OUT_RESULT(AluOut)
            );
            

















    
    parameter [7:0]
    
    IDLE = 8'hF0,
    GET_THREAD_START_ADDR_0 = 8'hF1,
    GET_THREAD_START_ADDR_1 = 8'hF2,
    GET_THREAD_START_ADDR_2 = 8'hF3,
    


    CHOOSE_OPP = 8'h00,
    

    READ_FROM_MEM_TO_A = 8'h10,
    READ_FROM_MEM_TO_B = 8'h11,
    READ_FROM_MEM_0 = 8'h12,
    READ_FROM_MEM_1 = 8'h13,
    READ_FROM_MEM_2 = 8'h14,
    WRITE_TO_MEM_FROM_A = 8'h20,
    WRITE_TO_MEM_FROM_B = 8'h21,
    WRITE_TO_MEM_0 = 8'h22,
    

    DO_MATHS_OPP_SAVE_IN_A = 8'h30,
    DO_MATHS_OPP_SAVE_IN_B = 8'h31,
    DO_MATHS_OPP_0 = 8'h32,
    

    IF_A_EQUALITY_B_GOTO   = 8'h40,
    IF_A_EQUALITY_B_GOTO_0 = 8'h41,
    IF_A_EQUALITY_B_GOTO_1 = 8'h42,
    

    GOTO_ADDR            = 8'h50,
    GOTO_ADDR_0          = 8'h51,
    GOTO_ADDR_1          = 8'h52,
    GOTO_IDLE            = 8'h53,
    

    FUNCTION_START       = 8'h60,
    FUNCTION_START_0     = 8'h61,
    FUNCTION_START_1     = 8'h62,
    RETURN               = 8'h63,
    RETURN_0             = 8'h64,
    

    DEREFERENCE_A        = 8'h70,
    DEREFERENCE_B        = 8'h71,     
    DEREFERENCE_0        = 8'h72,
    DEREFERENCE_1        = 8'h73,
    DEREFERENCE_2        = 8'h74;
        

    reg [7:0] CurrState, NextState;
    always@(posedge CLK) 
    begin
        if(RESET) 
        begin
            CurrState = 8'h00;
            CurrProgCounter = 8'h00;
            CurrProgCounterOffset = 2'h0;
            CurrBusAddr = 8'hFF;
            CurrBusDataOut = 8'h00;
            CurrBusDataOutWE = 1'b0;
            CurrRegA = 8'h00;
            CurrRegB = 8'h00;
            CurrRegSelect = 1'b0;
            CurrProgContext = 8'h00;
            CurrInterruptAck = 2'b00;
        end 
        
        else 
        
        begin
            CurrState = NextState;
            CurrProgCounter = NextProgCounter;
            CurrProgCounterOffset = NextProgCounterOffset;
            CurrBusAddr = NextBusAddr;
            CurrBusDataOut = NextBusDataOut;
            CurrBusDataOutWE = NextBusDataOutWE;
            CurrRegA = NextRegA;
            CurrRegB = NextRegB;
            CurrRegSelect = NextRegSelect;
            CurrProgContext = NextProgContext;
            CurrInterruptAck = NextInterruptAck;
        end
    end
    

    always@* 
    begin

        NextState = CurrState;
        NextProgCounter = CurrProgCounter;
        NextProgCounterOffset = 2'h0;
        NextBusAddr = 8'hFF;
        NextBusDataOut = CurrBusDataOut;
        NextBusDataOutWE = 1'b0;
        NextRegA = CurrRegA;
        NextRegB = CurrRegB;
        NextRegSelect = CurrRegSelect;
        NextProgContext = CurrProgContext;
        NextInterruptAck = 2'b00;

        case (CurrState)


            IDLE: 
            begin
                if(BUS_INTERRUPTS_RAISE[0]) begin
                    NextState = GET_THREAD_START_ADDR_0;
                    NextProgCounter = 8'hFF;
                    NextInterruptAck = 2'b01;
                end 
                
                else if(BUS_INTERRUPTS_RAISE[1]) begin
                    NextState = GET_THREAD_START_ADDR_0;
                    NextProgCounter = 8'hFE;
                    NextInterruptAck = 2'b10;
                end 
                
                else 
                begin
                    NextState = IDLE;
                    NextProgCounter = 8'hF0;
                    NextInterruptAck = 2'b00;
                end
            end
            

            GET_THREAD_START_ADDR_0: 
            begin
                NextState = GET_THREAD_START_ADDR_1;
            end
            

            GET_THREAD_START_ADDR_1: 
            begin
                NextState = GET_THREAD_START_ADDR_2;
                NextProgCounter = ProgMemoryOut;
            end
            

            GET_THREAD_START_ADDR_2:
            begin
                NextState = CHOOSE_OPP;
            end
            


            CHOOSE_OPP: 
            begin
                 case (ProgMemoryOut[3:0])
                     4'h0: NextState = READ_FROM_MEM_TO_A;
                     4'h1: NextState = READ_FROM_MEM_TO_B;
                     4'h2: NextState = WRITE_TO_MEM_FROM_A;
                     4'h3: NextState = WRITE_TO_MEM_FROM_B;
                     4'h4: NextState = DO_MATHS_OPP_SAVE_IN_A;
                     4'h5: NextState = DO_MATHS_OPP_SAVE_IN_B;
                     4'h6: NextState = IF_A_EQUALITY_B_GOTO;
                     4'h7: NextState = GOTO_ADDR;
                     4'h8: NextState = GOTO_IDLE;
                     4'h9: NextState = FUNCTION_START;
                     4'hA: NextState = RETURN;
                     4'hB: NextState = DEREFERENCE_A;
                     4'hC: NextState = DEREFERENCE_B;
                     default:
                           NextState = CurrState;
                 endcase
                 
                 NextProgCounterOffset = 2'h1;
            end
            



            READ_FROM_MEM_TO_A:
            begin
                NextState = READ_FROM_MEM_0;
                NextRegSelect = 1'b0;
            end
            


            READ_FROM_MEM_TO_B:
            begin
                NextState = READ_FROM_MEM_0;
                NextRegSelect = 1'b1;
            end
            

            READ_FROM_MEM_0: 
            begin
                NextState = READ_FROM_MEM_1;
                NextBusAddr = ProgMemoryOut;
            end
            



            READ_FROM_MEM_1: 
            begin
                NextState = READ_FROM_MEM_2;
                NextProgCounter = CurrProgCounter + 2;
            end
            

            READ_FROM_MEM_2: 
            begin
                NextState = CHOOSE_OPP;
                if(!CurrRegSelect)
                    NextRegA = BusDataIn;
                else
                    NextRegB = BusDataIn;
            end
            





            WRITE_TO_MEM_FROM_A:
            begin
                NextState = WRITE_TO_MEM_0;
                NextRegSelect = 1'b0;
                NextProgCounter = CurrProgCounter + 2;
            end
            




            WRITE_TO_MEM_FROM_B:
            begin
                NextState = WRITE_TO_MEM_0;
                NextRegSelect = 1'b1;
                NextProgCounter = CurrProgCounter + 2;
            end
            


            WRITE_TO_MEM_0: 
            begin
                NextState = CHOOSE_OPP;
                NextBusAddr = ProgMemoryOut;
                if(!NextRegSelect)
                    NextBusDataOut = CurrRegA;
                else
                    NextBusDataOut = CurrRegB;
                NextBusDataOutWE = 1'b1;
            end
            





            DO_MATHS_OPP_SAVE_IN_A: 
            begin
                NextState = DO_MATHS_OPP_0;
                NextRegA = AluOut;
                NextProgCounter = CurrProgCounter + 1;
            end


            DO_MATHS_OPP_SAVE_IN_B: 
            begin
                NextState = DO_MATHS_OPP_0;
                NextRegB = AluOut;
                NextProgCounter = CurrProgCounter + 1;
            end
            

            DO_MATHS_OPP_0: 
                NextState = CHOOSE_OPP;
            



            IF_A_EQUALITY_B_GOTO:
                NextState = IF_A_EQUALITY_B_GOTO_0;
            IF_A_EQUALITY_B_GOTO_0:
            begin
            NextState = IF_A_EQUALITY_B_GOTO_1;
                if (AluOut == 8'h01)
                begin

                    NextProgCounter = ProgMemoryOut;
                end
                else
                begin
                    NextProgCounter = CurrProgCounter + 2;
                end
            end

            IF_A_EQUALITY_B_GOTO_1:
            begin
                NextState = CHOOSE_OPP;
            end
            
            GOTO_ADDR:
                NextState = GOTO_ADDR_0;
            
            GOTO_ADDR_0:
            begin
                NextProgCounter =  ProgMemoryOut;
                NextState = GOTO_ADDR_1;
            end
            
            GOTO_ADDR_1:
                NextState = CHOOSE_OPP;

            FUNCTION_START:
            begin
                NextState = FUNCTION_START_0;
                NextProgContext = CurrProgCounter + 2;
            end
            
            FUNCTION_START_0:
            begin
                NextProgCounter = ProgMemoryOut;
                NextState = FUNCTION_START_1;
            end
            
            FUNCTION_START_1:
                NextState = CHOOSE_OPP;
            
            RETURN:
            begin
                NextState = RETURN_0;
                NextProgCounter = CurrProgContext; 
            end
            RETURN_0:
                NextState = CHOOSE_OPP;
                

            
            DEREFERENCE_A:
            begin
                NextState = DEREFERENCE_0;
                NextRegSelect = 1'b0;
            end
            
            DEREFERENCE_B:
            begin
                NextState = DEREFERENCE_0;
                NextRegSelect = 1'b1;
            end
            
            DEREFERENCE_0:
            begin
                NextState = DEREFERENCE_1;
                if (CurrRegSelect)
                    NextBusAddr = CurrRegB;   
                else if (~CurrRegSelect)
                    NextBusAddr = CurrRegA;
            end
            
            DEREFERENCE_1:
            begin
                NextState = DEREFERENCE_2;
                NextProgCounter = CurrProgCounter + 1;
            end
            
            DEREFERENCE_2:
            begin
                NextState = CHOOSE_OPP;
            
                if(!CurrRegSelect)
                    NextRegA = BusDataIn;
                else
                    NextRegB = BusDataIn;
            end
            
            GOTO_IDLE:
            begin
                NextState = IDLE;
            end
        endcase
    end
    
    
    endmodule