data/full_repos/permissive/196851857/datapath/pc.v
None: at end of input
data/verilator_xmls/a019c78c-d6cc-46a5-ae81-3156689e90ea.xml
module pc(
  input rst,clk,
  input [31:0] NPC,
  output reg [31:0] PC
);
  initial 
  begin 
     PC = 32'h0000_3000;
  end
  always@(posedge clk)
  begin
    PC <= rst ? 32'h0000_3000 : NPC;
  end
endmodule
module pc(
  input rst,clk,
  input [31:0] NPC,
  output reg [31:0] PC
);

  initial 
  begin 
     PC = 32'h0000_3000;
  end
  always@(posedge clk)
  begin
    PC <= rst ? 32'h0000_3000 : NPC;
  end
endmodule