data/full_repos/permissive/143278/ivltests/pr859.v
 line:15: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr859.v:15: Unsupported: Ignoring delay on this delayed statement.\n   initial #1 $display("PASSED");\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test(output reg [15:0] probe_data,input wire [3:0] probe_sel);

   always @*
     case(probe_sel)
       4'h0 :;
       default : probe_data = 16'b0;
     endcase

   initial #1 $display("PASSED");

endmodule
module test(output reg [15:0] probe_data,input wire [3:0] probe_sel);


   always @*
     case(probe_sel)
       4'h0 :;
       default : probe_data = 16'b0;
     endcase

   initial #1 $display("PASSED");

endmodule