data/full_repos/permissive/159610434/i8255/testbench/top_tb.v
 line:1: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/159610434/i8255/testbench/top_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #TCQ\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159610434/i8255/testbench/top_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #(TCQ*2)\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/159610434/i8255/testbench/top_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #TCQ\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/159610434/i8255/testbench/top_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #(TCQ*2)\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/159610434/i8255/testbench/top_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #TCQ\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/159610434/i8255/testbench/top_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #(TCQ*2)\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/159610434/i8255/testbench/top_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #TCQ\n        ^\n%Error: data/full_repos/permissive/159610434/i8255/testbench/top_tb.v:14: Cannot find file containing module: \'top\'\n    top uut (\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/159610434/i8255/testbench,data/full_repos/permissive/159610434/top\n             data/full_repos/permissive/159610434/i8255/testbench,data/full_repos/permissive/159610434/top.v\n             data/full_repos/permissive/159610434/i8255/testbench,data/full_repos/permissive/159610434/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb(
);

    parameter TCQ = 10;

    reg reset;
    reg rd_n, wr_n, cs_n;
    reg [1:0] a;
    reg [7:0] d;
    wire [7:0] porta, portb, portc;

    top uut (
        .reset(reset),
        .cs_n(cs_n),
        .rd_n(rd_n),
        .wr_n(wr_n),
        .a(a),
        .d(d),
        .pa(porta),
        .pb(portb),
        .pc(portc)
    );

    initial begin
        reset = 1;
        cs_n = 1; rd_n = 1; wr_n = 1;
        a = 0;
        d = 0;
        #TCQ
            reset = 0;

        #(TCQ*2)
            cs_n = 0;
            wr_n = 0;
            a = 3;
            d = 8'h80;
        #TCQ
            cs_n = 1;
            wr_n = 1;

        #(TCQ*2)
            cs_n = 0;
            wr_n = 0;
            a = 3;
            d = 8'h83;
        #TCQ
            cs_n = 1;
            wr_n = 1;

        #(TCQ*2)
            cs_n = 0;
            wr_n = 0;
            a = 0;
            d = 8'hff;
        #TCQ
            cs_n = 1;
            wr_n = 1;
    end

endmodule
module top_tb(
);


    parameter TCQ = 10;

    reg reset;
    reg rd_n, wr_n, cs_n;
    reg [1:0] a;
    reg [7:0] d;
    wire [7:0] porta, portb, portc;

    top uut (
        .reset(reset),
        .cs_n(cs_n),
        .rd_n(rd_n),
        .wr_n(wr_n),
        .a(a),
        .d(d),
        .pa(porta),
        .pb(portb),
        .pc(portc)
    );

    initial begin
        reset = 1;
        cs_n = 1; rd_n = 1; wr_n = 1;
        a = 0;
        d = 0;
        #TCQ
            reset = 0;

        #(TCQ*2)
            cs_n = 0;
            wr_n = 0;
            a = 3;
            d = 8'h80;
        #TCQ
            cs_n = 1;
            wr_n = 1;

        #(TCQ*2)
            cs_n = 0;
            wr_n = 0;
            a = 3;
            d = 8'h83;
        #TCQ
            cs_n = 1;
            wr_n = 1;

        #(TCQ*2)
            cs_n = 0;
            wr_n = 0;
            a = 0;
            d = 8'hff;
        #TCQ
            cs_n = 1;
            wr_n = 1;
    end

endmodule