data/full_repos/permissive/147645128/source/misc/clock_div.v
1: b'%Warning-WIDTH: data/full_repos/permissive/147645128/source/misc/clock_div.v:56: Operator EQ expects 32 or 25 bits on the LHS, but LHS\'s VARREF \'clk_pre_cnt\' generates 21 bits.\n                                                                               : ... In instance clock_div\n  if(clk_pre_cnt == (FREQ_SYSCLK / 32 - 1))\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module clock_div(
clk_sys_i,
rst_n_i,

clk_16hz_o,
clk_8hz_o,
clk_1hz_o
);


parameter FREQ_SYSCLK = 25_000_000;


input clk_sys_i, rst_n_i;
output clk_16hz_o, clk_8hz_o, clk_1hz_o;

reg[20:0] clk_pre_cnt;
reg[4:0] clk_post_cnt;



always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		clk_pre_cnt <= 0;
	end
	else begin

		if(clk_pre_cnt == (FREQ_SYSCLK / 32 - 1))
			clk_pre_cnt <= 0;
		else
			clk_pre_cnt <= clk_pre_cnt + 1'b1;
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		clk_post_cnt <= 0;
	end
	else if(clk_pre_cnt == 0) begin
		clk_post_cnt <= clk_post_cnt + 1'b1;
	end
end


wire clk_16hz_o = clk_post_cnt[0];
wire clk_8hz_o = clk_post_cnt[1];
wire clk_1hz_o = clk_post_cnt[4];

endmodule
module clock_div(
clk_sys_i,
rst_n_i,

clk_16hz_o,
clk_8hz_o,
clk_1hz_o
);



parameter FREQ_SYSCLK = 25_000_000;


input clk_sys_i, rst_n_i;
output clk_16hz_o, clk_8hz_o, clk_1hz_o;

reg[20:0] clk_pre_cnt;
reg[4:0] clk_post_cnt;



always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		clk_pre_cnt <= 0;
	end
	else begin

		if(clk_pre_cnt == (FREQ_SYSCLK / 32 - 1))
			clk_pre_cnt <= 0;
		else
			clk_pre_cnt <= clk_pre_cnt + 1'b1;
	end
end


always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		clk_post_cnt <= 0;
	end
	else if(clk_pre_cnt == 0) begin
		clk_post_cnt <= clk_post_cnt + 1'b1;
	end
end


wire clk_16hz_o = clk_post_cnt[0];
wire clk_8hz_o = clk_post_cnt[1];
wire clk_1hz_o = clk_post_cnt[4];

endmodule