data/full_repos/permissive/190595283/Modulos/Memoria_instrucoes.v
data/verilator_xmls/ce78b0d0-4ba8-45c8-8b2d-7a378b1181ae.xml
module Memoria_instrucoes (endereco,instrucao);
  input [31:0]endereco;
  output reg [31:0] instrucao;
  reg [31:0]I_Mem[0:31];

  initial begin
        I_Mem[0] = 32'b00000001000010010101000000100000;
        I_Mem[1] = 32'b00000010000100011001000000100000;
        I_Mem[2] = 32'b00000010100100111010100000100010;
        I_Mem[3] = 32'b00000001100010110110100000100010;
        I_Mem[4] = 32'b00000010010011011011000000100101;
        I_Mem[5] = 32'b00000001010101010111000000100101;
        I_Mem[6] = 32'b00000010010011011011100000100100;
        I_Mem[7] = 32'b00000001010101010111100000100100;
        I_Mem[8] = 32'b00000010010011010100000000100111;
        I_Mem[9] = 32'b00000001010101011000000000100111;
        I_Mem[10] = 32'b00000001110011010100100000101010;
        I_Mem[11] = 32'b00000001101011101000100000101010;
        I_Mem[12] = 32'b10001110010010100000000000000100;
        I_Mem[13] = 32'b10001110001010110000000000001000;
        I_Mem[14] = 32'b10101110010011000000000000000100;
        I_Mem[15] = 32'b10101110001011010000000000001000;
        I_Mem[16] = 32'b00000010010011010100000000100110;
        I_Mem[17] = 32'b00000001010101011000000000100110;
        I_Mem[18] = 32'b00010110100101010000000000000001;
        I_Mem[19] = 32'b00010110100101010000000000000001;
        I_Mem[20] = 32'b00010010001101011111111111110000;

    end
  always @ (endereco) begin
    instrucao <= I_Mem[endereco/4];
  end
endmodule
module Memoria_instrucoes (endereco,instrucao);

  input [31:0]endereco;
  output reg [31:0] instrucao;
  reg [31:0]I_Mem[0:31];

  initial begin
        I_Mem[0] = 32'b00000001000010010101000000100000;
        I_Mem[1] = 32'b00000010000100011001000000100000;
        I_Mem[2] = 32'b00000010100100111010100000100010;
        I_Mem[3] = 32'b00000001100010110110100000100010;
        I_Mem[4] = 32'b00000010010011011011000000100101;
        I_Mem[5] = 32'b00000001010101010111000000100101;
        I_Mem[6] = 32'b00000010010011011011100000100100;
        I_Mem[7] = 32'b00000001010101010111100000100100;
        I_Mem[8] = 32'b00000010010011010100000000100111;
        I_Mem[9] = 32'b00000001010101011000000000100111;
        I_Mem[10] = 32'b00000001110011010100100000101010;
        I_Mem[11] = 32'b00000001101011101000100000101010;
        I_Mem[12] = 32'b10001110010010100000000000000100;
        I_Mem[13] = 32'b10001110001010110000000000001000;
        I_Mem[14] = 32'b10101110010011000000000000000100;
        I_Mem[15] = 32'b10101110001011010000000000001000;
        I_Mem[16] = 32'b00000010010011010100000000100110;
        I_Mem[17] = 32'b00000001010101011000000000100110;
        I_Mem[18] = 32'b00010110100101010000000000000001;
        I_Mem[19] = 32'b00010110100101010000000000000001;
        I_Mem[20] = 32'b00010010001101011111111111110000;

    end
  always @ (endereco) begin
    instrucao <= I_Mem[endereco/4];
  end
endmodule