data/full_repos/permissive/217662009/verilog/m序列/m_seq.v
data/verilator_xmls/64b16894-6fd8-4331-81f7-e338088d7e08.xml
module m_seq
(
	input							clk		,
	input							rst		,

	input							en		,
	output	reg						data_out,
	output	reg						data_vld
);

reg [3:0]	data_count = 4'b1000	;


always @ (posedge clk or posedge rst)
begin
	if (rst)
	begin
		data_out	<=	1'b0;
		data_vld	<=	1'b0;
		data_count	<=	4'b1000	;
	end
	else if (en)
	begin
		data_out	<=	data_count[0];
		data_count[2:0]	<=	data_count[3:1];
		data_count[3]	<=	data_count[0] ^ data_count[3];
		data_vld	<=	1'b1;
	end
	else
	begin
		data_vld	<=	1'b0;
	end
end

endmodule
module m_seq
(
	input							clk		,
	input							rst		,

	input							en		,
	output	reg						data_out,
	output	reg						data_vld
);


reg [3:0]	data_count = 4'b1000	;


always @ (posedge clk or posedge rst)
begin
	if (rst)
	begin
		data_out	<=	1'b0;
		data_vld	<=	1'b0;
		data_count	<=	4'b1000	;
	end
	else if (en)
	begin
		data_out	<=	data_count[0];
		data_count[2:0]	<=	data_count[3:1];
		data_count[3]	<=	data_count[0] ^ data_count[3];
		data_vld	<=	1'b1;
	end
	else
	begin
		data_vld	<=	1'b0;
	end
end

endmodule