data/full_repos/permissive/154352170/MUX.v
None: at end of input
1: b'%Warning-MULTITOP: data/full_repos/permissive/154352170/MUX.v:42: Multiple top level modules\n                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                : ... Top module \'ALU_MUX_A\'\nmodule ALU_MUX_A(\n       ^~~~~~~~~\n                                                                : ... Top module \'ALU_MUX_B\'\nmodule ALU_MUX_B(\n       ^~~~~~~~~\n                                                                : ... Top module \'RegData_MUX\'\nmodule RegData_MUX(\n       ^~~~~~~~~~~\n                                                                : ... Top module \'WA_MUX\'\nmodule WA_MUX(\n       ^~~~~~\n                                                                : ... Top module \'MFRTM\'\nmodule MFRTM(\n       ^~~~~\n                                                                : ... Top module \'MFRTE\'\nmodule MFRTE(\n       ^~~~~\n                                                                : ... Top module \'MFRSE\'\nmodule MFRSE(\n       ^~~~~\n                                                                : ... Top module \'MFRTD\'\nmodule MFRTD(\n       ^~~~~\n                                                                : ... Top module \'MFRSD\'\nmodule MFRSD(\n       ^~~~~\n%Error: Exiting due to 1 warning(s)\n'
module MFRSD(
    input [1:0] ForwardRSD,
	 input [31:0] RD1,
	 input [31:0] ALU_Out_M,
	 input [31:0] PC_Out_M,
	 output [31:0] RS_D
	 );
	 
	 reg [31:0] RS;
	 assign RS_D = RS;
	 
	 always @ (*) begin
	    
		 if (ForwardRSD == 2'b00)
		    RS <= RD1;
		 
		 if (ForwardRSD == 2'b01)
		    RS <= ALU_Out_M;
		 
		 if (ForwardRSD == 2'b10)
		    RS <= PC_Out_M + 8;
	 
	 end
	 
endmodule
module MFRSD(
    input [1:0] ForwardRSD,
	 input [31:0] RD1,
	 input [31:0] ALU_Out_M,
	 input [31:0] PC_Out_M,
	 output [31:0] RS_D
	 );

	 
	 reg [31:0] RS;
	 assign RS_D = RS;
	 
	 always @ (*) begin
	    
		 if (ForwardRSD == 2'b00)
		    RS <= RD1;
		 
		 if (ForwardRSD == 2'b01)
		    RS <= ALU_Out_M;
		 
		 if (ForwardRSD == 2'b10)
		    RS <= PC_Out_M + 8;
	 
	 end
	 
endmodule