data/full_repos/permissive/125520060/problem-1001-compare/tb_top.v
 line:19: before: "$"
1: b'%Error: data/full_repos/permissive/125520060/problem-1001-compare/tb_top.v:9: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/125520060/problem-1001-compare/tb_top.v:10: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, u_compare);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/125520060/problem-1001-compare/tb_top.v:11: Unsupported or unknown PLI call: $monitor\n    $monitor("Time = %3d, a = %b, b = %b, equal = %b",\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125520060/problem-1001-compare/tb_top.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #10 a=0; b=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125520060/problem-1001-compare/tb_top.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 a=1; b=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/125520060/problem-1001-compare/tb_top.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #10 a=1; b=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/125520060/problem-1001-compare/tb_top.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10 a=0; b=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/125520060/problem-1001-compare/tb_top.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_compare;

reg     a, b;
wire    equal;

compare u_compare(a, b, equal);

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(1, u_compare);
    $monitor("Time = %3d, a = %b, b = %b, equal = %b",
             $time, a, b, equal);

        a=0; b=0;
    #10 a=0; b=1;
    #10 a=1; b=1;
    #10 a=1; b=0;
    #10 a=0; b=0;
    #10 $finish;
end

endmodule
module tb_compare;


reg     a, b;
wire    equal;

compare u_compare(a, b, equal);

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(1, u_compare);
    $monitor("Time = %3d, a = %b, b = %b, equal = %b",
             $time, a, b, equal);

        a=0; b=0;
    #10 a=0; b=1;
    #10 a=1; b=1;
    #10 a=1; b=0;
    #10 a=0; b=0;
    #10 $finish;
end

endmodule