data/full_repos/permissive/146975244/InOut.v
1: b'%Warning-WIDTH: data/full_repos/permissive/146975244/InOut.v:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'BusIn\' generates 15 bits.\n                                                               : ... In instance InOut\n  Data = BusIn;\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/146975244/InOut.v:25: Cannot find file containing module: \'BCD\'\nBCD bBCD2(.binary(pc[9:0]), .Hundreds(Hnd1[3:0]), .Tens(Tns1[3:0]), .Ones(Ons1[3:0]));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/146975244,data/full_repos/permissive/146975244/BCD\n             data/full_repos/permissive/146975244,data/full_repos/permissive/146975244/BCD.v\n             data/full_repos/permissive/146975244,data/full_repos/permissive/146975244/BCD.sv\n             BCD\n             BCD.v\n             BCD.sv\n             obj_dir/BCD\n             obj_dir/BCD.v\n             obj_dir/BCD.sv\n%Error: data/full_repos/permissive/146975244/InOut.v:27: Cannot find file containing module: \'BCD\'\nBCD bBCD(.binary(Data[9:0]), .Hundreds(Hnd[3:0]), .Tens(Tns[3:0]), .Ones(Ons[3:0]));\n^~~\n%Error: data/full_repos/permissive/146975244/InOut.v:28: Cannot find file containing module: \'DisplayF\'\nDisplayF vD1(.sum(Ons[3:0]), .Hex(Hex1));\n^~~~~~~~\n%Error: data/full_repos/permissive/146975244/InOut.v:29: Cannot find file containing module: \'DisplayF\'\nDisplayF vD2(.sum(Tns[3:0]), .Hex(Hex2));\n^~~~~~~~\n%Error: data/full_repos/permissive/146975244/InOut.v:30: Cannot find file containing module: \'DisplayF\'\nDisplayF vD3(.sum(Hnd[3:0]), .Hex(Hex3));\n^~~~~~~~\n%Error: data/full_repos/permissive/146975244/InOut.v:31: Cannot find file containing module: \'DisplayF\'\nDisplayF vD4(.sum(Ons1[3:0]), .Hex(Hex4));\n^~~~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module InOut(clock, I, O, BusIn, DataLCD, resALU, Hex1, Hex2, Hex3, Hex4, pc);

input clock, I, O;
input [10:0] pc;
input [31:0] resALU;
input [14:0] BusIn;
reg [31:0] Data;
wire [3:0] Hnd, Tns, Ons, Hnd1, Tns1, Ons1;
output [6:0] Hex1, Hex2, Hex3, Hex4;
output [14:0] DataLCD;

initial begin
	Data = 0;
end
always @(*) begin
	if (I) begin
		Data = BusIn;
	end
	
	else if (O == 1) begin
		Data = resALU;
	end
end
assign DataLCD = BusIn;
BCD bBCD2(.binary(pc[9:0]), .Hundreds(Hnd1[3:0]), .Tens(Tns1[3:0]), .Ones(Ons1[3:0]));

BCD bBCD(.binary(Data[9:0]), .Hundreds(Hnd[3:0]), .Tens(Tns[3:0]), .Ones(Ons[3:0]));
DisplayF vD1(.sum(Ons[3:0]), .Hex(Hex1));
DisplayF vD2(.sum(Tns[3:0]), .Hex(Hex2));
DisplayF vD3(.sum(Hnd[3:0]), .Hex(Hex3));
DisplayF vD4(.sum(Ons1[3:0]), .Hex(Hex4));

endmodule
module InOut(clock, I, O, BusIn, DataLCD, resALU, Hex1, Hex2, Hex3, Hex4, pc);


input clock, I, O;
input [10:0] pc;
input [31:0] resALU;
input [14:0] BusIn;
reg [31:0] Data;
wire [3:0] Hnd, Tns, Ons, Hnd1, Tns1, Ons1;
output [6:0] Hex1, Hex2, Hex3, Hex4;
output [14:0] DataLCD;

initial begin
	Data = 0;
end
always @(*) begin
	if (I) begin
		Data = BusIn;
	end
	
	else if (O == 1) begin
		Data = resALU;
	end
end
assign DataLCD = BusIn;
BCD bBCD2(.binary(pc[9:0]), .Hundreds(Hnd1[3:0]), .Tens(Tns1[3:0]), .Ones(Ons1[3:0]));

BCD bBCD(.binary(Data[9:0]), .Hundreds(Hnd[3:0]), .Tens(Tns[3:0]), .Ones(Ons[3:0]));
DisplayF vD1(.sum(Ons[3:0]), .Hex(Hex1));
DisplayF vD2(.sum(Tns[3:0]), .Hex(Hex2));
DisplayF vD3(.sum(Hnd[3:0]), .Hex(Hex3));
DisplayF vD4(.sum(Ons1[3:0]), .Hex(Hex4));

endmodule