data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:210: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg0 (\n               ^~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:216: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:222: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg2 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:228: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg3 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:234: Cell has missing pin: \'en\'\n  reg_ar_as_w18 reg4 (\n                ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:240: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg5 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:246: Cell has missing pin: \'en\'\n  reg_ar_as_w25 reg6 (\n                ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:252: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg7 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:580: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg0 (\n               ^~~~\n%Error: Exiting due to 9 warning(s)\n'
module reg_ar_as_w4
  (
  clk,
  d,
  en,
  reset,
  set,
  q
  );

  input clk;
  input [3:0] d;
  input en;
  input [3:0] reset;
  input [3:0] set;
  output [3:0] q;



endmodule
module reg_ar_as_w4
  (
  clk,
  d,
  en,
  reset,
  set,
  q
  );


  input clk;
  input [3:0] d;
  input en;
  input [3:0] reset;
  input [3:0] set;
  output [3:0] q;



endmodule