data/full_repos/permissive/142505464/modules/dpram/rtl/verilog/dpram.v
data/verilator_xmls/5d03bd68-4bfa-40b5-98e2-89d019f6b50a.xml
module dpram(
	clka, clkb,
	addra, douta, dina, wena,
	addrb, doutb, dinb, wenb
);
parameter aw=8;
parameter dw=8;
parameter sz=(32'b1<<aw)-1;
	input clka, clkb, wena, wenb;
	input [aw-1:0] addra, addrb;
	input [dw-1:0] dina, dinb;
	output [dw-1:0] douta, doutb;

reg [dw-1:0] mem[sz:0];
reg [dw-1:0] douta, doutb;




`ifdef SIMULATE
integer k=0;
initial
begin
	for (k=0;k<sz+1;k=k+1)
	begin
		mem[k]=0;
	end
end
`endif


always @(posedge clka) begin
	if (wena) mem[addra]<=dina;
	douta <= mem[addra];
end
always @(posedge clkb) begin
	if (wenb) mem[addrb]<=dinb;
	doutb <= mem[addrb];
end

endmodule
module dpram(
	clka, clkb,
	addra, douta, dina, wena,
	addrb, doutb, dinb, wenb
);

parameter aw=8;
parameter dw=8;
parameter sz=(32'b1<<aw)-1;
	input clka, clkb, wena, wenb;
	input [aw-1:0] addra, addrb;
	input [dw-1:0] dina, dinb;
	output [dw-1:0] douta, doutb;

reg [dw-1:0] mem[sz:0];
reg [dw-1:0] douta, doutb;




`ifdef SIMULATE
integer k=0;
initial
begin
	for (k=0;k<sz+1;k=k+1)
	begin
		mem[k]=0;
	end
end
`endif


always @(posedge clka) begin
	if (wena) mem[addra]<=dina;
	douta <= mem[addra];
end
always @(posedge clkb) begin
	if (wenb) mem[addrb]<=dinb;
	doutb <= mem[addrb];
end

endmodule