data/full_repos/permissive/149070951/tests/02-test-pushbuttons/pushbuttons.v
data/verilator_xmls/74ae67c8-a0b1-42f8-95ef-7e8f037ce6b9.xml
module leds(input wire SW1,
            input wire SW2,
            output wire LED0,
            output wire LED1);

assign {LED0, LED1} = {SW1, SW2};

endmodule
module leds(input wire SW1,
            input wire SW2,
            output wire LED0,
            output wire LED1);


assign {LED0, LED1} = {SW1, SW2};

endmodule