data/full_repos/permissive/158922207/Verilog Design/modules/PCSrc_Mux.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/PCSrc_Mux.v\n%Error: Exiting due to 3 error(s)\n'
module PCSrc_Mux(pcNext, pc4,BranchAddr,jumpAddress, RSout,PCorBranch,Jump,jr);
input [31:0] pc4, BranchAddr,jumpAddress, RSout;
input PCorBranch, Jump, jr;
output reg [31:0] pcNext;

always @(*)begin
    case({PCorBranch,Jump,jr})
        3'b000: pcNext <= pc4;
        3'b100: pcNext <= BranchAddr;
        3'b010: pcNext <= jumpAddress;
        3'b001: pcNext <= RSout;
        default: pcNext <= 0;
    endcase
end

endmodule
module PCSrc_Mux(pcNext, pc4,BranchAddr,jumpAddress, RSout,PCorBranch,Jump,jr);

input [31:0] pc4, BranchAddr,jumpAddress, RSout;
input PCorBranch, Jump, jr;
output reg [31:0] pcNext;

always @(*)begin
    case({PCorBranch,Jump,jr})
        3'b000: pcNext <= pc4;
        3'b100: pcNext <= BranchAddr;
        3'b010: pcNext <= jumpAddress;
        3'b001: pcNext <= RSout;
        default: pcNext <= 0;
    endcase
end

endmodule