data/full_repos/permissive/167746421/pe_core/genesis/test_full_add.svp
 line:4: before: "parameter"
1: b"%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_full_add.svp:3: Define or directive not defined: '`mname'\nmodule `mname`  #(\n       ^~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_full_add.svp:3: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule `mname`  #(\n             ^\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_full_add.svp:5: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter Segs      = 4,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_full_add.svp:6: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter SegWidth  = 4\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_full_add.svp:7: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_full_add.svp:16: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [Segs-1:0]    c_out\n  ^~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_full_add.svp:17: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_full_add.svp:22: syntax error, unexpected assign\nassign c_out = is_vec ? c_out_full : {c_out_full[Segs-1], {(Segs-1){1'b0}}};\n^~~~~~\n%Error: Exiting due to 8 error(s)\n"
module `mname`  #(
  parameter DataWidth = 16,
  parameter Segs      = 4,
  parameter SegWidth  = 4
) (

  input  [DataWidth-1:0]        a,
  input  [DataWidth-1:0]        b,
  input                         c_in,

  input  						is_vec,

  output logic [DataWidth-1:0]  res,
  output logic [Segs-1:0]    c_out
);

logic [Segs-1:0] carries_in;
logic [Segs-1:0] c_out_full;

assign c_out = is_vec ? c_out_full : {c_out_full[Segs-1], {(Segs-1){1'b0}}};

assign carries_in[0] = c_in;

genvar vec_el;

generate
	for(vec_el=0; vec_el<Segs; vec_el=vec_el + 1) begin: GEN_VEC_ADD
		if(vec_el != Segs - 1) begin
			assign carries_in[vec_el + 1] = is_vec ? c_in : c_out_full[vec_el];
		end
		assign {c_out_full[vec_el], res[((vec_el + 1)*SegWidth) - 1 : (vec_el*SegWidth)]} = 
					a[((vec_el + 1)*SegWidth) - 1 : (vec_el*SegWidth)] + b[((vec_el + 1)*SegWidth) - 1 : (vec_el*SegWidth)] + carries_in[vec_el];
	end

endgenerate

endmodule
module `mname`  #(
  parameter DataWidth = 16,
  parameter Segs      = 4,
  parameter SegWidth  = 4
) (

  input  [DataWidth-1:0]        a,
  input  [DataWidth-1:0]        b,
  input                         c_in,

  input  						is_vec,

  output logic [DataWidth-1:0]  res,
  output logic [Segs-1:0]    c_out
);


logic [Segs-1:0] carries_in;
logic [Segs-1:0] c_out_full;

assign c_out = is_vec ? c_out_full : {c_out_full[Segs-1], {(Segs-1){1'b0}}};

assign carries_in[0] = c_in;

genvar vec_el;

generate
	for(vec_el=0; vec_el<Segs; vec_el=vec_el + 1) begin: GEN_VEC_ADD
		if(vec_el != Segs - 1) begin
			assign carries_in[vec_el + 1] = is_vec ? c_in : c_out_full[vec_el];
		end
		assign {c_out_full[vec_el], res[((vec_el + 1)*SegWidth) - 1 : (vec_el*SegWidth)]} = 
					a[((vec_el + 1)*SegWidth) - 1 : (vec_el*SegWidth)] + b[((vec_el + 1)*SegWidth) - 1 : (vec_el*SegWidth)] + carries_in[vec_el];
	end

endgenerate

endmodule