data/full_repos/permissive/213507744/Graph/char_ram.v
data/verilator_xmls/6a1dc457-0d73-4461-9e78-f44bcd362154.xml
module  char_ram(
input   clk,

input   [12:0]  transed_address,




input   [6:0]   data_input, 

output  [6:0]   data_output, 

input   [3:0]   write_enable);
    reg [12:0]  address_reg;
    reg [6:0]   char_ram    [0:4799];


    always @(posedge clk) begin
        if (write_enable[0])
            char_ram[transed_address] <= data_input;
        address_reg <= address_reg;
    end
    assign data_output = char_ram[address_reg];
endmodule
module  char_ram(
input   clk,

input   [12:0]  transed_address,




input   [6:0]   data_input, 

output  [6:0]   data_output, 

input   [3:0]   write_enable);

    reg [12:0]  address_reg;
    reg [6:0]   char_ram    [0:4799];


    always @(posedge clk) begin
        if (write_enable[0])
            char_ram[transed_address] <= data_input;
        address_reg <= address_reg;
    end
    assign data_output = char_ram[address_reg];
endmodule