data/full_repos/permissive/196483925/testbench/viterbi_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/196483925/testbench/viterbi_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n #(clk_cycle/2);\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/196483925/testbench/viterbi_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n #(clk_cycle/2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/196483925/testbench/viterbi_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n #256\n ^\n%Warning-STMTDLY: data/full_repos/permissive/196483925/testbench/viterbi_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n #80000;\n ^\n%Error: data/full_repos/permissive/196483925/testbench/viterbi_tb.v:178: Unsupported or unknown PLI call: $vcdplusfile\n $vcdplusfile("result.vpd");\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/196483925/testbench/viterbi_tb.v:179: Unsupported or unknown PLI call: $vcdpluson\n $vcdpluson;\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sram21x64 (clk, cs, we, addr, wdata, rdata);


input clk, cs, we; 
input [4:0] addr;
input [63:0] wdata;
output [63:0] rdata;

reg [63:0] rdata;
reg [63:0] memreg[0:20];


always @(posedge clk) 
begin
	if (!cs) begin
		rdata <= 64'bz; 
	end
	else if (we) begin
		memreg[addr] <= wdata;
		rdata <= wdata;
	end 
	else begin
		rdata <= memreg[addr];
	end
end

endmodule
module sram21x64 (clk, cs, we, addr, wdata, rdata);



input clk, cs, we; 
input [4:0] addr;
input [63:0] wdata;
output [63:0] rdata;

reg [63:0] rdata;
reg [63:0] memreg[0:20];


always @(posedge clk) 
begin
	if (!cs) begin
		rdata <= 64'bz; 
	end
	else if (we) begin
		memreg[addr] <= wdata;
		rdata <= wdata;
	end 
	else begin
		rdata <= memreg[addr];
	end
end

endmodule