data/full_repos/permissive/106408053/verilog/trigger_adv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n              ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram_byte (clock, addr, wrenb, wrdata, rddata);
input clock;
input [3:0] addr;
input wrenb;
input [7:0] wrdata;
output [7:0] rddata;
RAM16X4S ram0 (
  .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .WCLK(clock), .WE(wrenb), 
  .D0(wrdata[0]), .D1(wrdata[1]), .D2(wrdata[2]), .D3(wrdata[3]),
  .O0(rddata[0]), .O1(rddata[1]), .O2(rddata[2]), .O3(rddata[3]));
RAM16X4S ram1 (
  .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .WCLK(clock), .WE(wrenb), 
  .D0(wrdata[4]), .D1(wrdata[5]), .D2(wrdata[6]), .D3(wrdata[7]),
  .O0(rddata[4]), .O1(rddata[5]), .O2(rddata[6]), .O3(rddata[7]));
endmodule
module ram_byte (clock, addr, wrenb, wrdata, rddata);

input clock;
input [3:0] addr;
input wrenb;
input [7:0] wrdata;
output [7:0] rddata;
RAM16X4S ram0 (
  .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .WCLK(clock), .WE(wrenb), 
  .D0(wrdata[0]), .D1(wrdata[1]), .D2(wrdata[2]), .D3(wrdata[3]),
  .O0(rddata[0]), .O1(rddata[1]), .O2(rddata[2]), .O3(rddata[3]));
RAM16X4S ram1 (
  .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), .WCLK(clock), .WE(wrenb), 
  .D0(wrdata[4]), .D1(wrdata[5]), .D2(wrdata[6]), .D3(wrdata[7]),
  .O0(rddata[4]), .O1(rddata[5]), .O2(rddata[6]), .O3(rddata[7]));
endmodule