data/full_repos/permissive/158984095/Homework2/Question4/HW2_4_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question4/HW2_4_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n# 20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question4/HW2_4_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n# 20;\n^\n%Error: data/full_repos/permissive/158984095/Homework2/Question4/HW2_4_tb.v:19: Unsupported or unknown PLI call: $monitor\n$monitor($time,"clk=%b\\treset=%b\\tskip=%b\\tstate=%b\\tcount=%b\\tshutter=%b\\n",clk,reset,skip,state,count,shutter);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question4/HW2_4_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n# 5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question4/HW2_4_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n# 5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question4/HW2_4_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n# 15;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question4/HW2_4_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n# 1030;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question4/HW2_4_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n# 1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question4/HW2_4_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n# 50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question4/HW2_4_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n# 100;\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FSM_testbench();
reg clk;
reg reset;
reg skip;
wire [1:0] state;
wire [2:0] count;
wire shutter;

FSM testbench_instantiation(clk,reset,skip,state[1:0],count[2:0],shutter);

always begin
clk <= 1'b0;
# 20;
clk <= 1'b1;
# 20;
end

initial begin
$monitor($time,"clk=%b\treset=%b\tskip=%b\tstate=%b\tcount=%b\tshutter=%b\n",clk,reset,skip,state,count,shutter);
# 5;
reset = 1'b1;
# 5;
skip = 1'b0;
# 15;
reset = 1'b0;
# 1030;
skip = 1'b1;
# 1000;
reset = 1'b1;
# 50;
reset = 1'b0;
# 100;
end
endmodule
module FSM_testbench();

reg clk;
reg reset;
reg skip;
wire [1:0] state;
wire [2:0] count;
wire shutter;

FSM testbench_instantiation(clk,reset,skip,state[1:0],count[2:0],shutter);

always begin
clk <= 1'b0;
# 20;
clk <= 1'b1;
# 20;
end

initial begin
$monitor($time,"clk=%b\treset=%b\tskip=%b\tstate=%b\tcount=%b\tshutter=%b\n",clk,reset,skip,state,count,shutter);
# 5;
reset = 1'b1;
# 5;
skip = 1'b0;
# 15;
reset = 1'b0;
# 1030;
skip = 1'b1;
# 1000;
reset = 1'b1;
# 50;
reset = 1'b0;
# 100;
end
endmodule