data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v
1: b'%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:6: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:75: Define or directive not defined: \'`SERIAL_WCNT\'\n      end else if( waitnum >= `SERIAL_WCNT ) begin\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:75: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      end else if( waitnum >= `SERIAL_WCNT ) begin\n                                           ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:81: syntax error, unexpected else\n      end else begin\n          ^~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:192: Define or directive not defined: \'`SERIAL_WCNT\'\n   assign waitcnt = `SERIAL_WCNT;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:192: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   assign waitcnt = `SERIAL_WCNT;\n                                ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:283: Define or directive not defined: \'`APP_SIZE\'\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:283: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                               ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:287: Define or directive not defined: \'`APP_SIZE\'\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:287: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                               ^\n%Error: Exiting due to 10 error(s)\n'
module TX_FIFO(CLK, RST_X, D_IN, WE, RE, D_OUT, D_EN, RDY, ERR);
   input  wire       CLK, RST_X, WE, RE;
   input  wire [7:0] D_IN;
   output reg [7:0]  D_OUT;
   output reg        D_EN, ERR;
   output wire       RDY;
   
   reg [7:0] 	     mem [0:2048-1];
   reg [10:0] 	     head, tail;
   
   assign RDY = (D_EN==0 && head!=tail);
   
   always @(posedge CLK) begin
      if(~RST_X) begin 
         {D_EN, ERR, head, tail, D_OUT} <= 0;
      end
      else begin            
         if(WE) begin
            mem[tail] <= D_IN;
            tail <= tail + 1;
            if(head == (tail + 1)) ERR <= 1;
         end
         
         if(RE) begin
            D_OUT <= mem[head];
            D_EN  <= 1;
            head <= head + 1;
         end else begin
            D_EN <= 0;
         end
      end
   end
endmodule
module TX_FIFO(CLK, RST_X, D_IN, WE, RE, D_OUT, D_EN, RDY, ERR);

   input  wire       CLK, RST_X, WE, RE;
   input  wire [7:0] D_IN;
   output reg [7:0]  D_OUT;
   output reg        D_EN, ERR;
   output wire       RDY;
   
   reg [7:0] 	     mem [0:2048-1];
   reg [10:0] 	     head, tail;
   
   assign RDY = (D_EN==0 && head!=tail);
   
   always @(posedge CLK) begin
      if(~RST_X) begin 
         {D_EN, ERR, head, tail, D_OUT} <= 0;
      end
      else begin            
         if(WE) begin
            mem[tail] <= D_IN;
            tail <= tail + 1;
            if(head == (tail + 1)) ERR <= 1;
         end
         
         if(RE) begin
            D_OUT <= mem[head];
            D_EN  <= 1;
            head <= head + 1;
         end else begin
            D_EN <= 0;
         end
      end
   end
endmodule