data/full_repos/permissive/125531440/core/src/main/verilog/loopback/counter.v
 line:89: before: "function"
1: b'%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/counter.v:46: Cannot find include file: functions.vh\n`include "functions.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/functions.vh\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/functions.vh.v\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/functions.vh.sv\n             functions.vh\n             functions.vh.v\n             functions.vh.sv\n             obj_dir/functions.vh\n             obj_dir/functions.vh.v\n             obj_dir/functions.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module counter
    #(parameter C_MAX_VALUE = 10,
      parameter C_SAT_VALUE = 10,
      parameter C_RST_VALUE = 0)
    (
     input                              CLK,
     input                              RST_IN,

     input                              ENABLE,
     output [clog2s(C_MAX_VALUE+1)-1:0] VALUE
     );
    wire                                wEnable;
    reg [clog2s(C_MAX_VALUE+1)-1:0]     wCtrValue;
    reg [clog2s(C_MAX_VALUE+1)-1:0]     rCtrValue;

    assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue);

    assign VALUE = rCtrValue;
    always @(posedge CLK) begin
        if(RST_IN) begin
            rCtrValue <= C_RST_VALUE[clog2s(C_MAX_VALUE+1)-1:0];
        end else if(wEnable) begin
            rCtrValue <= rCtrValue + 1;
        end
    end
endmodule
module counter
    #(parameter C_MAX_VALUE = 10,
      parameter C_SAT_VALUE = 10,
      parameter C_RST_VALUE = 0)
    (
     input                              CLK,
     input                              RST_IN,

     input                              ENABLE,
     output [clog2s(C_MAX_VALUE+1)-1:0] VALUE
     );

    wire                                wEnable;
    reg [clog2s(C_MAX_VALUE+1)-1:0]     wCtrValue;
    reg [clog2s(C_MAX_VALUE+1)-1:0]     rCtrValue;

    assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue);

    assign VALUE = rCtrValue;
    always @(posedge CLK) begin
        if(RST_IN) begin
            rCtrValue <= C_RST_VALUE[clog2s(C_MAX_VALUE+1)-1:0];
        end else if(wEnable) begin
            rCtrValue <= rCtrValue + 1;
        end
    end
endmodule