data/full_repos/permissive/100752663/src/mod_sdram_controller.v
 line:106 column:19: Illegal character "'"
1: b'%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:99: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'a_q\' generates 13 bits.\n                                                                                  : ... In instance mod_sdram_controller\n    assign out_sdram_a = a_q;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:103: Cannot find file containing module: \'SB_IO\'\n    SB_IO #(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/100752663/src,data/full_repos/permissive/100752663/SB_IO\n             data/full_repos/permissive/100752663/src,data/full_repos/permissive/100752663/SB_IO.v\n             data/full_repos/permissive/100752663/src,data/full_repos/permissive/100752663/SB_IO.sv\n             SB_IO\n             SB_IO.v\n             SB_IO.sv\n             obj_dir/SB_IO\n             obj_dir/SB_IO.v\n             obj_dir/SB_IO.sv\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:154: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                                   : ... In instance mod_sdram_controller\n        a_d = 11\'d0;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:203: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                                   : ... In instance mod_sdram_controller\n                a_d = 11\'b0;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:213: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'13\'h0\' generates 13 bits.\n                                                                                   : ... In instance mod_sdram_controller\n                if (delay_ctr_q == 13\'d0) begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:227: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n                                                                                   : ... In instance mod_sdram_controller\n                delay_ctr_d = 13\'d0;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:232: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h7\' generates 13 bits.\n                                                                                   : ... In instance mod_sdram_controller\n                delay_ctr_d = 13\'d7;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:238: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h7\' generates 13 bits.\n                                                                                   : ... In instance mod_sdram_controller\n                delay_ctr_d = 13\'d7;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:251: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h2\' generates 13 bits.\n                                                                                   : ... In instance mod_sdram_controller\n                delay_ctr_d = 13\'d2;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:298: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h6\' generates 13 bits.\n                                                                                   : ... In instance mod_sdram_controller\n                delay_ctr_d = 13\'d6;  \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:307: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n                                                                                   : ... In instance mod_sdram_controller\n                delay_ctr_d = 13\'d0;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:325: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h2\' generates 13 bits.\n                                                                                   : ... In instance mod_sdram_controller\n                delay_ctr_d = 13\'d2;  \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:362: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n                                                                                   : ... In instance mod_sdram_controller\n                delay_ctr_d = 13\'d0;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:396: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'a_d\' generates 12 bits.\n                                                                                   : ... In instance mod_sdram_controller\n        a_q <= a_d;\n            ^~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n'
module mod_sdram_controller (
    input in_sdram_clk,
    input in_rst,


    output out_sdram_cle,
    output out_sdram_cs,
    output out_sdram_cas,
    output out_sdram_ras,
    output out_sdram_we,
    output out_sdram_dqm,
    output [1:0] out_sdram_ba,
    output [11:0] out_sdram_a,
    inout [7:0] inout_sdram_dq,


    input [21:0] in_addr,
    input in_rw,
    input [31:0] in_data,
    output [31:0] out_data,
    output out_busy,
    input in_valid,
    output out_valid
);


    localparam CMD_UNSELECTED    = 4'b1000;
    localparam CMD_NOP           = 4'b0111;
    localparam CMD_ACTIVE        = 4'b0011;
    localparam CMD_READ          = 4'b0101;
    localparam CMD_WRITE         = 4'b0100;
    localparam CMD_TERMINATE     = 4'b0110;
    localparam CMD_PRECHARGE     = 4'b0010;
    localparam CMD_REFRESH       = 4'b0001;
    localparam CMD_LOAD_MODE_REG = 4'b0000;

    localparam STATE_SIZE = 4;
    localparam INIT = 0,
               WAIT = 1,
               PRECHARGE_INIT = 2,
               REFRESH_INIT_1 = 3,
               REFRESH_INIT_2 = 4,
               LOAD_MODE_REG = 5,
               IDLE = 6,
               REFRESH = 7,
               ACTIVATE = 8,
               READ = 9,
               READ_RES = 10,
               WRITE = 11,
               PRECHARGE = 12;


    reg cle_d, dqm_d;
    reg [3:0] cmd_d;
    reg [1:0] ba_d;
    reg [11:0] a_d;
    reg [7:0] dq_d;
    reg [7:0] dqi_d;




    (* IOB = "TRUE" *)
    reg cle_q, dqm_q;
    (* IOB = "TRUE" *)
    reg [3:0] cmd_q;
    (* IOB = "TRUE" *)
    reg [1:0] ba_q;
    (* IOB = "TRUE" *)
    reg [12:0] a_q;
    (* IOB = "TRUE" *)
    reg [7:0] dq_q;
    (* IOB = "TRUE" *)
    wire [7:0] dqi_q;
    reg dq_en_d, dq_en_q;


    assign out_sdram_cle = cle_q;
    assign out_sdram_cs = cmd_q[3];
    assign out_sdram_ras = cmd_q[2];
    assign out_sdram_cas = cmd_q[1];
    assign out_sdram_we = cmd_q[0];
    assign out_sdram_dqm = dqm_q;
    assign out_sdram_ba = ba_q;
    assign out_sdram_a = a_q;



    SB_IO #(


      .PIN_TYPE(6'b 1010_01),
      .PULLUP(1'b 0)
    ) data_io [7:0] (
      .PACKAGE_PIN(inout_sdram_dq),
      .OUTPUT_ENABLE(dq_en_d),
      .D_OUT_0(dq_q),
      .D_IN_0(dqi_q)
    );

    reg [STATE_SIZE-1:0] state_d, state_q = INIT;
    reg [STATE_SIZE-1:0] next_state_d, next_state_q;

    reg [21:0] addr_d, addr_q;
    reg [31:0] data_d, data_q;
    reg out_valid_d, out_valid_q;

    assign out_data = data_q;
    assign out_busy = !ready_q;
    assign out_valid = out_valid_q;

    reg [15:0] delay_ctr_d, delay_ctr_q;
    reg [1:0] byte_ctr_d, byte_ctr_q;

    reg [9:0] refresh_ctr_d, refresh_ctr_q;
    reg refresh_flag_d, refresh_flag_q;

    reg ready_d, ready_q;
    reg saved_rw_d, saved_rw_q;
    reg [21:0] saved_addr_d, saved_addr_q;
    reg [31:0] saved_data_d, saved_data_q;

    reg rw_op_d, rw_op_q;

    reg [3:0] row_open_d, row_open_q;
    reg [11:0] row_addr_d[3:0], row_addr_q[3:0];

    reg [2:0] precharge_bank_d, precharge_bank_q;
    integer i;

    always @* begin

        dq_d = dq_q;
        dqi_d = dqi_q;
        dq_en_d = 1'b0;
        cle_d = cle_q;
        cmd_d = CMD_NOP;
        dqm_d = 1'b0;
        ba_d = 2'd0;
        a_d = 11'd0;
        state_d = state_q;
        next_state_d = next_state_q;
        delay_ctr_d = delay_ctr_q;
        addr_d = addr_q;
        data_d = data_q;
        out_valid_d = 1'b0;
        precharge_bank_d = precharge_bank_q;
        rw_op_d = rw_op_q;
        byte_ctr_d = 2'd0;

        row_open_d = row_open_q;


        for (i = 0; i < 4; i = i + 1)
            row_addr_d[i] = row_addr_q[i];



        refresh_flag_d = refresh_flag_q;
        refresh_ctr_d = refresh_ctr_q + 1'b1;


        if (refresh_ctr_q > 10'd750) begin
            refresh_ctr_d = 10'd0;
            refresh_flag_d = 1'b1;
        end

        saved_rw_d = saved_rw_q;
        saved_data_d = saved_data_q;
        saved_addr_d = saved_addr_q;
        ready_d = ready_q;




        if (ready_q && in_valid) begin
            saved_rw_d = in_rw;
            saved_data_d = in_data;
            saved_addr_d = in_addr;
            ready_d = 1'b0;
        end

        case (state_q)

            INIT: begin
                ready_d = 1'b0;
                row_open_d = 4'b0;
                out_valid_d = 1'b0;
                a_d = 11'b0;
                ba_d = 2'b0;
                cle_d = 1'b1;
                state_d = WAIT;
                delay_ctr_d = 16'd19000;
                next_state_d = PRECHARGE_INIT;
                dq_en_d = 1'b0;
            end
            WAIT: begin
                delay_ctr_d = delay_ctr_q - 1'b1;
                if (delay_ctr_q == 13'd0) begin
                    state_d = next_state_q;
                    if (next_state_q == WRITE) begin
                        dq_en_d = 1'b1;
                        dq_d = data_q[7:0];
                    end
                end
            end
            PRECHARGE_INIT: begin
                cmd_d = CMD_PRECHARGE;
                a_d[10] = 1'b1;
                ba_d = 2'd0;
                state_d = WAIT;
                next_state_d = REFRESH_INIT_1;
                delay_ctr_d = 13'd0;
            end
            REFRESH_INIT_1: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 13'd7;
                next_state_d = REFRESH_INIT_2;
            end
            REFRESH_INIT_2: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 13'd7;
                next_state_d = LOAD_MODE_REG;
            end
            LOAD_MODE_REG: begin
                cmd_d = CMD_LOAD_MODE_REG;
                ba_d = 2'b0;
                a_d = { 2'b00,
                         1'b0,
                        2'b00,
                       3'b010,
                         1'b0,
                       3'b010 };
                state_d = WAIT;
                delay_ctr_d = 13'd2;
                next_state_d = IDLE;
                refresh_flag_d = 1'b0;
                refresh_ctr_d = 10'b1;
                ready_d = 1'b1;
            end


            IDLE: begin
                if (refresh_flag_q) begin
                    state_d = PRECHARGE;
                    next_state_d = REFRESH;
                    precharge_bank_d = 3'b100;
                    refresh_flag_d = 1'b0;
                end else if (!ready_q) begin
                    ready_d = 1'b1;
                    rw_op_d = saved_rw_q;
                    addr_d = saved_addr_q;

                    if (saved_rw_q)
                        data_d = saved_data_q;


                    if (row_open_q[saved_addr_q[21:20]]) begin
                        if (row_addr_q[saved_addr_q[21:20]] == saved_addr_q[19:8]) begin

                            if (saved_rw_q)
                                state_d = WRITE;
                            else
                                state_d = READ;
                        end else begin

                            state_d = PRECHARGE;
                            precharge_bank_d = {1'b0, saved_addr_q[21:20]};
                            next_state_d = ACTIVATE;
                        end
                    end else begin

                        state_d = ACTIVATE;
                    end
                end
            end


            REFRESH: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 13'd6;
                next_state_d = IDLE;
            end


            ACTIVATE: begin
                cmd_d = CMD_ACTIVE;
                a_d = addr_q[19:8];
                ba_d = addr_q[21:20];
                delay_ctr_d = 13'd0;
                state_d = WAIT;

                if (rw_op_q)
                    next_state_d = WRITE;
                else
                    next_state_d = READ;

                row_open_d[addr_q[21:20]] = 1'b1;
                row_addr_d[addr_q[21:20]] = addr_q[19:8];
            end


            READ: begin
                cmd_d = CMD_READ;
                a_d = {2'b0, addr_q[7:0], 2'b0};
                ba_d = addr_q[21:20];
                state_d = WAIT;
                delay_ctr_d = 13'd2;
                next_state_d = READ_RES;

            end
            READ_RES: begin
                byte_ctr_d = byte_ctr_q + 1'b1;
                data_d = {dqi_q, data_q[31:8]};
                if (byte_ctr_q == 2'd3) begin
                    out_valid_d = 1'b1;
                    state_d = IDLE;
                end
            end


            WRITE: begin
                byte_ctr_d = byte_ctr_q + 1'b1;

                if (byte_ctr_q == 2'd0)
                    cmd_d = CMD_WRITE;

                dq_d = data_q[7:0];
                data_d = {8'h00, data_q[31:8]};
                dq_en_d = 1'b1;
                a_d = {2'b0, addr_q[7:0], 2'b00};
                ba_d = addr_q[21:20];

                if (byte_ctr_q == 2'd3) begin
                    state_d = IDLE;
                end
            end


            PRECHARGE: begin
                cmd_d = CMD_PRECHARGE;
                a_d[10] = precharge_bank_q[2];
                ba_d = precharge_bank_q[1:0];
                state_d = WAIT;
                delay_ctr_d = 13'd0;

                if (precharge_bank_q[2]) begin
                    row_open_d = 4'b0000;
                end else begin
                    row_open_d[precharge_bank_q[1:0]] = 1'b0;
                end
            end

            default: state_d = INIT;
        endcase

    end

    always @(posedge in_sdram_clk) begin
        if(in_rst) begin
            cle_q <= 1'b0;
            dq_en_q <= 1'b0;
            state_q <= INIT;
            ready_q <= 1'b0;
        end else begin
            cle_q <= cle_d;
            dq_en_q <= dq_en_d;
            state_q <= state_d;
            ready_q <= ready_d;
        end

        saved_rw_q <= saved_rw_d;
        saved_data_q <= saved_data_d;
        saved_addr_q <= saved_addr_d;

        cmd_q <= cmd_d;
        dqm_q <= dqm_d;
        ba_q <= ba_d;
        a_q <= a_d;
        dq_q <= dq_d;

        next_state_q <= next_state_d;
        refresh_flag_q <= refresh_flag_d;
        refresh_ctr_q <= refresh_ctr_d;
        data_q <= data_d;
        addr_q <= addr_d;
        out_valid_q <= out_valid_d;
        row_open_q <= row_open_d;
        for (i = 0; i < 4; i = i + 1)
            row_addr_q[i] <= row_addr_d[i];
        precharge_bank_q <= precharge_bank_d;
        rw_op_q <= rw_op_d;
        byte_ctr_q <= byte_ctr_d;
        delay_ctr_q <= delay_ctr_d;
    end
endmodule
module mod_sdram_controller (
    input in_sdram_clk,
    input in_rst,


    output out_sdram_cle,
    output out_sdram_cs,
    output out_sdram_cas,
    output out_sdram_ras,
    output out_sdram_we,
    output out_sdram_dqm,
    output [1:0] out_sdram_ba,
    output [11:0] out_sdram_a,
    inout [7:0] inout_sdram_dq,


    input [21:0] in_addr,
    input in_rw,
    input [31:0] in_data,
    output [31:0] out_data,
    output out_busy,
    input in_valid,
    output out_valid
);



    localparam CMD_UNSELECTED    = 4'b1000;
    localparam CMD_NOP           = 4'b0111;
    localparam CMD_ACTIVE        = 4'b0011;
    localparam CMD_READ          = 4'b0101;
    localparam CMD_WRITE         = 4'b0100;
    localparam CMD_TERMINATE     = 4'b0110;
    localparam CMD_PRECHARGE     = 4'b0010;
    localparam CMD_REFRESH       = 4'b0001;
    localparam CMD_LOAD_MODE_REG = 4'b0000;

    localparam STATE_SIZE = 4;
    localparam INIT = 0,
               WAIT = 1,
               PRECHARGE_INIT = 2,
               REFRESH_INIT_1 = 3,
               REFRESH_INIT_2 = 4,
               LOAD_MODE_REG = 5,
               IDLE = 6,
               REFRESH = 7,
               ACTIVATE = 8,
               READ = 9,
               READ_RES = 10,
               WRITE = 11,
               PRECHARGE = 12;


    reg cle_d, dqm_d;
    reg [3:0] cmd_d;
    reg [1:0] ba_d;
    reg [11:0] a_d;
    reg [7:0] dq_d;
    reg [7:0] dqi_d;




    (* IOB = "TRUE" *)
    reg cle_q, dqm_q;
    (* IOB = "TRUE" *)
    reg [3:0] cmd_q;
    (* IOB = "TRUE" *)
    reg [1:0] ba_q;
    (* IOB = "TRUE" *)
    reg [12:0] a_q;
    (* IOB = "TRUE" *)
    reg [7:0] dq_q;
    (* IOB = "TRUE" *)
    wire [7:0] dqi_q;
    reg dq_en_d, dq_en_q;


    assign out_sdram_cle = cle_q;
    assign out_sdram_cs = cmd_q[3];
    assign out_sdram_ras = cmd_q[2];
    assign out_sdram_cas = cmd_q[1];
    assign out_sdram_we = cmd_q[0];
    assign out_sdram_dqm = dqm_q;
    assign out_sdram_ba = ba_q;
    assign out_sdram_a = a_q;



    SB_IO #(


      .PIN_TYPE(6'b 1010_01),
      .PULLUP(1'b 0)
    ) data_io [7:0] (
      .PACKAGE_PIN(inout_sdram_dq),
      .OUTPUT_ENABLE(dq_en_d),
      .D_OUT_0(dq_q),
      .D_IN_0(dqi_q)
    );

    reg [STATE_SIZE-1:0] state_d, state_q = INIT;
    reg [STATE_SIZE-1:0] next_state_d, next_state_q;

    reg [21:0] addr_d, addr_q;
    reg [31:0] data_d, data_q;
    reg out_valid_d, out_valid_q;

    assign out_data = data_q;
    assign out_busy = !ready_q;
    assign out_valid = out_valid_q;

    reg [15:0] delay_ctr_d, delay_ctr_q;
    reg [1:0] byte_ctr_d, byte_ctr_q;

    reg [9:0] refresh_ctr_d, refresh_ctr_q;
    reg refresh_flag_d, refresh_flag_q;

    reg ready_d, ready_q;
    reg saved_rw_d, saved_rw_q;
    reg [21:0] saved_addr_d, saved_addr_q;
    reg [31:0] saved_data_d, saved_data_q;

    reg rw_op_d, rw_op_q;

    reg [3:0] row_open_d, row_open_q;
    reg [11:0] row_addr_d[3:0], row_addr_q[3:0];

    reg [2:0] precharge_bank_d, precharge_bank_q;
    integer i;

    always @* begin

        dq_d = dq_q;
        dqi_d = dqi_q;
        dq_en_d = 1'b0;
        cle_d = cle_q;
        cmd_d = CMD_NOP;
        dqm_d = 1'b0;
        ba_d = 2'd0;
        a_d = 11'd0;
        state_d = state_q;
        next_state_d = next_state_q;
        delay_ctr_d = delay_ctr_q;
        addr_d = addr_q;
        data_d = data_q;
        out_valid_d = 1'b0;
        precharge_bank_d = precharge_bank_q;
        rw_op_d = rw_op_q;
        byte_ctr_d = 2'd0;

        row_open_d = row_open_q;


        for (i = 0; i < 4; i = i + 1)
            row_addr_d[i] = row_addr_q[i];



        refresh_flag_d = refresh_flag_q;
        refresh_ctr_d = refresh_ctr_q + 1'b1;


        if (refresh_ctr_q > 10'd750) begin
            refresh_ctr_d = 10'd0;
            refresh_flag_d = 1'b1;
        end

        saved_rw_d = saved_rw_q;
        saved_data_d = saved_data_q;
        saved_addr_d = saved_addr_q;
        ready_d = ready_q;




        if (ready_q && in_valid) begin
            saved_rw_d = in_rw;
            saved_data_d = in_data;
            saved_addr_d = in_addr;
            ready_d = 1'b0;
        end

        case (state_q)

            INIT: begin
                ready_d = 1'b0;
                row_open_d = 4'b0;
                out_valid_d = 1'b0;
                a_d = 11'b0;
                ba_d = 2'b0;
                cle_d = 1'b1;
                state_d = WAIT;
                delay_ctr_d = 16'd19000;
                next_state_d = PRECHARGE_INIT;
                dq_en_d = 1'b0;
            end
            WAIT: begin
                delay_ctr_d = delay_ctr_q - 1'b1;
                if (delay_ctr_q == 13'd0) begin
                    state_d = next_state_q;
                    if (next_state_q == WRITE) begin
                        dq_en_d = 1'b1;
                        dq_d = data_q[7:0];
                    end
                end
            end
            PRECHARGE_INIT: begin
                cmd_d = CMD_PRECHARGE;
                a_d[10] = 1'b1;
                ba_d = 2'd0;
                state_d = WAIT;
                next_state_d = REFRESH_INIT_1;
                delay_ctr_d = 13'd0;
            end
            REFRESH_INIT_1: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 13'd7;
                next_state_d = REFRESH_INIT_2;
            end
            REFRESH_INIT_2: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 13'd7;
                next_state_d = LOAD_MODE_REG;
            end
            LOAD_MODE_REG: begin
                cmd_d = CMD_LOAD_MODE_REG;
                ba_d = 2'b0;
                a_d = { 2'b00,
                         1'b0,
                        2'b00,
                       3'b010,
                         1'b0,
                       3'b010 };
                state_d = WAIT;
                delay_ctr_d = 13'd2;
                next_state_d = IDLE;
                refresh_flag_d = 1'b0;
                refresh_ctr_d = 10'b1;
                ready_d = 1'b1;
            end


            IDLE: begin
                if (refresh_flag_q) begin
                    state_d = PRECHARGE;
                    next_state_d = REFRESH;
                    precharge_bank_d = 3'b100;
                    refresh_flag_d = 1'b0;
                end else if (!ready_q) begin
                    ready_d = 1'b1;
                    rw_op_d = saved_rw_q;
                    addr_d = saved_addr_q;

                    if (saved_rw_q)
                        data_d = saved_data_q;


                    if (row_open_q[saved_addr_q[21:20]]) begin
                        if (row_addr_q[saved_addr_q[21:20]] == saved_addr_q[19:8]) begin

                            if (saved_rw_q)
                                state_d = WRITE;
                            else
                                state_d = READ;
                        end else begin

                            state_d = PRECHARGE;
                            precharge_bank_d = {1'b0, saved_addr_q[21:20]};
                            next_state_d = ACTIVATE;
                        end
                    end else begin

                        state_d = ACTIVATE;
                    end
                end
            end


            REFRESH: begin
                cmd_d = CMD_REFRESH;
                state_d = WAIT;
                delay_ctr_d = 13'd6;
                next_state_d = IDLE;
            end


            ACTIVATE: begin
                cmd_d = CMD_ACTIVE;
                a_d = addr_q[19:8];
                ba_d = addr_q[21:20];
                delay_ctr_d = 13'd0;
                state_d = WAIT;

                if (rw_op_q)
                    next_state_d = WRITE;
                else
                    next_state_d = READ;

                row_open_d[addr_q[21:20]] = 1'b1;
                row_addr_d[addr_q[21:20]] = addr_q[19:8];
            end


            READ: begin
                cmd_d = CMD_READ;
                a_d = {2'b0, addr_q[7:0], 2'b0};
                ba_d = addr_q[21:20];
                state_d = WAIT;
                delay_ctr_d = 13'd2;
                next_state_d = READ_RES;

            end
            READ_RES: begin
                byte_ctr_d = byte_ctr_q + 1'b1;
                data_d = {dqi_q, data_q[31:8]};
                if (byte_ctr_q == 2'd3) begin
                    out_valid_d = 1'b1;
                    state_d = IDLE;
                end
            end


            WRITE: begin
                byte_ctr_d = byte_ctr_q + 1'b1;

                if (byte_ctr_q == 2'd0)
                    cmd_d = CMD_WRITE;

                dq_d = data_q[7:0];
                data_d = {8'h00, data_q[31:8]};
                dq_en_d = 1'b1;
                a_d = {2'b0, addr_q[7:0], 2'b00};
                ba_d = addr_q[21:20];

                if (byte_ctr_q == 2'd3) begin
                    state_d = IDLE;
                end
            end


            PRECHARGE: begin
                cmd_d = CMD_PRECHARGE;
                a_d[10] = precharge_bank_q[2];
                ba_d = precharge_bank_q[1:0];
                state_d = WAIT;
                delay_ctr_d = 13'd0;

                if (precharge_bank_q[2]) begin
                    row_open_d = 4'b0000;
                end else begin
                    row_open_d[precharge_bank_q[1:0]] = 1'b0;
                end
            end

            default: state_d = INIT;
        endcase

    end

    always @(posedge in_sdram_clk) begin
        if(in_rst) begin
            cle_q <= 1'b0;
            dq_en_q <= 1'b0;
            state_q <= INIT;
            ready_q <= 1'b0;
        end else begin
            cle_q <= cle_d;
            dq_en_q <= dq_en_d;
            state_q <= state_d;
            ready_q <= ready_d;
        end

        saved_rw_q <= saved_rw_d;
        saved_data_q <= saved_data_d;
        saved_addr_q <= saved_addr_d;

        cmd_q <= cmd_d;
        dqm_q <= dqm_d;
        ba_q <= ba_d;
        a_q <= a_d;
        dq_q <= dq_d;

        next_state_q <= next_state_d;
        refresh_flag_q <= refresh_flag_d;
        refresh_ctr_q <= refresh_ctr_d;
        data_q <= data_d;
        addr_q <= addr_d;
        out_valid_q <= out_valid_d;
        row_open_q <= row_open_d;
        for (i = 0; i < 4; i = i + 1)
            row_addr_q[i] <= row_addr_d[i];
        precharge_bank_q <= precharge_bank_d;
        rw_op_q <= rw_op_d;
        byte_ctr_q <= byte_ctr_d;
        delay_ctr_q <= delay_ctr_d;
    end
endmodule