data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/and_gate_testbench.v
 line:26: before: "$"
1: b'%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/and_gate_testbench.v:12: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("and_gate.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/and_gate_testbench.v:13: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,and_gate_testbench);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/and_gate_testbench.v:14: Unsupported or unknown PLI call: $monitor\n    $monitor("At time %2t, x = %d y = %d out = %d", $time, x, y, out);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/and_gate_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/and_gate_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/and_gate_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/and_gate_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module and_gate_testbench;

reg x, y;
wire out;

and_gate uut(.x(x), .y(y), .z(out));

initial begin
    
    $dumpfile("and_gate.vcd");
    $dumpvars(0,and_gate_testbench);
    $monitor("At time %2t, x = %d y = %d out = %d", $time, x, y, out);
    

    x=0; y=0;
    #5
    x=0; y=1;
    #5
    x=1; y=0;
    #5
    x=1; y=1;
    #5
    
    $finish;
end
endmodule
module and_gate_testbench;


reg x, y;
wire out;

and_gate uut(.x(x), .y(y), .z(out));

initial begin
    
    $dumpfile("and_gate.vcd");
    $dumpvars(0,and_gate_testbench);
    $monitor("At time %2t, x = %d y = %d out = %d", $time, x, y, out);
    

    x=0; y=0;
    #5
    x=0; y=1;
    #5
    x=1; y=0;
    #5
    x=1; y=1;
    #5
    
    $finish;
end
endmodule