data/full_repos/permissive/128497744/fsm_calculator_part3/Full_Calculator/Full_Calculator.srcs/sources_1/new/Calc/Calc_CU.v
data/verilator_xmls/8cd1cb2c-7f94-4d97-b9e6-97217fec6251.xml
module Calc_CU(
    input go, clk, rst,
    input [1:0] op,
    output [3:0] cs,
    output reg [14:0] cw
);


parameter Idle                  = 4'd0,
          In1_into_R1           = 4'd1,
          In2_into_R2           = 4'd2,
          Wait                  = 4'd3,
          R1_plus_R2_into_R3    = 4'd4,
          R1_minus_R2_into_R3   = 4'd5,
          R1_and_R2_into_R3     = 4'd6,
          R1_xor_R2_into_R3     = 4'd7,
          out_done              = 4'd8;


reg [3:0] CS, NS;


always @ (CS, go)
begin
    case(CS)
        Idle:                   NS <= (go) ? In1_into_R1 : Idle;
        In1_into_R1:            NS <= In2_into_R2;
        In2_into_R2:            NS <= Wait;
        Wait:
            begin
                  case(op)
                     2'b00:     NS <= R1_plus_R2_into_R3;
                     2'b01:     NS <= R1_minus_R2_into_R3;
                     2'b10:     NS <= R1_and_R2_into_R3;
                     2'b11:     NS <= R1_xor_R2_into_R3;
                  endcase
            end
        R1_plus_R2_into_R3:     NS <= out_done;
        R1_minus_R2_into_R3:    NS <= out_done;
        R1_and_R2_into_R3:      NS <= out_done;
        R1_xor_R2_into_R3:      NS <= out_done;
        out_done:               NS <= (rst) ? Idle : out_done;
        default:                NS <= Idle;
     endcase
end


always @ (posedge clk, posedge rst)
    if (rst)
        CS <= Idle;
    else
        CS <= NS;


always @ (CS)
begin
    case(CS)
        Idle:                cw <= 15'b01_00_0_00_0_00_0_00_0_0;
        In1_into_R1:         cw <= 15'b11_01_1_00_0_00_0_00_0_0;
        In2_into_R2:         cw <= 15'b10_10_1_00_0_00_0_00_0_0;
        Wait:                cw <= 15'b01_00_0_00_0_00_0_00_0_0;
        R1_plus_R2_into_R3:  cw <= 15'b00_11_1_01_1_10_1_00_0_0;
        R1_minus_R2_into_R3: cw <= 15'b00_11_1_01_1_10_1_01_0_0;
        R1_and_R2_into_R3:   cw <= 15'b00_11_1_01_1_10_1_10_0_0;
        R1_xor_R2_into_R3:   cw <= 15'b00_11_1_01_1_10_1_11_0_0;
        out_done:            cw <= 15'b01_00_0_11_1_11_1_10_1_1;    
    endcase

end

assign cs = CS;
          


endmodule
module Calc_CU(
    input go, clk, rst,
    input [1:0] op,
    output [3:0] cs,
    output reg [14:0] cw
);



parameter Idle                  = 4'd0,
          In1_into_R1           = 4'd1,
          In2_into_R2           = 4'd2,
          Wait                  = 4'd3,
          R1_plus_R2_into_R3    = 4'd4,
          R1_minus_R2_into_R3   = 4'd5,
          R1_and_R2_into_R3     = 4'd6,
          R1_xor_R2_into_R3     = 4'd7,
          out_done              = 4'd8;


reg [3:0] CS, NS;


always @ (CS, go)
begin
    case(CS)
        Idle:                   NS <= (go) ? In1_into_R1 : Idle;
        In1_into_R1:            NS <= In2_into_R2;
        In2_into_R2:            NS <= Wait;
        Wait:
            begin
                  case(op)
                     2'b00:     NS <= R1_plus_R2_into_R3;
                     2'b01:     NS <= R1_minus_R2_into_R3;
                     2'b10:     NS <= R1_and_R2_into_R3;
                     2'b11:     NS <= R1_xor_R2_into_R3;
                  endcase
            end
        R1_plus_R2_into_R3:     NS <= out_done;
        R1_minus_R2_into_R3:    NS <= out_done;
        R1_and_R2_into_R3:      NS <= out_done;
        R1_xor_R2_into_R3:      NS <= out_done;
        out_done:               NS <= (rst) ? Idle : out_done;
        default:                NS <= Idle;
     endcase
end


always @ (posedge clk, posedge rst)
    if (rst)
        CS <= Idle;
    else
        CS <= NS;


always @ (CS)
begin
    case(CS)
        Idle:                cw <= 15'b01_00_0_00_0_00_0_00_0_0;
        In1_into_R1:         cw <= 15'b11_01_1_00_0_00_0_00_0_0;
        In2_into_R2:         cw <= 15'b10_10_1_00_0_00_0_00_0_0;
        Wait:                cw <= 15'b01_00_0_00_0_00_0_00_0_0;
        R1_plus_R2_into_R3:  cw <= 15'b00_11_1_01_1_10_1_00_0_0;
        R1_minus_R2_into_R3: cw <= 15'b00_11_1_01_1_10_1_01_0_0;
        R1_and_R2_into_R3:   cw <= 15'b00_11_1_01_1_10_1_10_0_0;
        R1_xor_R2_into_R3:   cw <= 15'b00_11_1_01_1_10_1_11_0_0;
        out_done:            cw <= 15'b01_00_0_11_1_11_1_10_1_1;    
    endcase

end

assign cs = CS;
          


endmodule