data/full_repos/permissive/159897054/blinky.v
1: b"%Error: data/full_repos/permissive/159897054/blinky.v:5: Duplicate declaration of signal: 'i_clk'\n                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire i_clk;\n         ^~~~~\n        data/full_repos/permissive/159897054/blinky.v:3: ... Location of original declaration\nmodule blinky(input i_clk, input [6:0] btn, output [7:0] o_led);\n                    ^~~~~\n%Error: data/full_repos/permissive/159897054/blinky.v:6: Duplicate declaration of signal: 'btn'\n    wire [6:0] btn;\n               ^~~\n        data/full_repos/permissive/159897054/blinky.v:3: ... Location of original declaration\nmodule blinky(input i_clk, input [6:0] btn, output [7:0] o_led);\n                                       ^~~\n%Error: data/full_repos/permissive/159897054/blinky.v:7: Duplicate declaration of signal: 'o_led'\n    wire [7:0] o_led;\n               ^~~~~\n        data/full_repos/permissive/159897054/blinky.v:3: ... Location of original declaration\nmodule blinky(input i_clk, input [6:0] btn, output [7:0] o_led);\n                                                         ^~~~~\n%Error: Exiting due to 3 error(s)\n"
module blinky(input i_clk, input [6:0] btn, output [7:0] o_led);

    wire i_clk;
    wire [6:0] btn;
    wire [7:0] o_led;
`else
module top(input clk_25mhz,
           input [6:0] btn,
           output [7:0] led,
           output wifi_gpio0);

    wire i_clk;


    assign wifi_gpio0 = 1'b1;
    assign i_clk= clk_25mhz;
    reg [7:0] o_led;
    assign led= o_led;
`endif

    localparam ctr_width = 32;
    reg [ctr_width-1:0] ctr = 0;

    always @(posedge i_clk) begin
               ctr <= ctr + 1;
          o_led[7] <= 1;
          o_led[6] <= btn[1];
        o_led[5:0] <= ctr[23:18];
    end

endmodule
module blinky(input i_clk, input [6:0] btn, output [7:0] o_led);


    wire i_clk;
    wire [6:0] btn;
    wire [7:0] o_led;
`else
module top(input clk_25mhz,
           input [6:0] btn,
           output [7:0] led,
           output wifi_gpio0);

    wire i_clk;


    assign wifi_gpio0 = 1'b1;
    assign i_clk= clk_25mhz;
    reg [7:0] o_led;
    assign led= o_led;
`endif

    localparam ctr_width = 32;
    reg [ctr_width-1:0] ctr = 0;

    always @(posedge i_clk) begin
               ctr <= ctr + 1;
          o_led[7] <= 1;
          o_led[6] <= btn[1];
        o_led[5:0] <= ctr[23:18];
    end

endmodule