data/full_repos/permissive/100975158/MIPS32_Full/Processor/Processor.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/Processor.v:3: Cannot find include file: Constants.v\n`include "Constants.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.v\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.sv\n             Constants.v\n             Constants.v.v\n             Constants.v.sv\n             obj_dir/Constants.v\n             obj_dir/Constants.v.v\n             obj_dir/Constants.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Processor (
    input clock,
    input reset,

    output              d_test_valid,

    output reg          me_memory_write_out,
    output reg          me_memory_read_out,
    output reg [31:0]   me_memory_data_write_out,
    output reg [31:0]   me_memory_address_out,
    input      [31:0]   me_memory_data_read_in

);

    parameter INSTRUCTIONS = "C:/Outros/Full Processor/MIPS32_Processor/Final Project/MIPS32_Full/Testing Codes/Exponential.txt";



    wire        if_stall;
    wire        if_flush;
    wire [31:0] if_pc;
    wire [31:0] if_pc_out;
    wire [31:0] if_pc_usable;
    wire [31:0] if_pc_add_4;
    wire [31:0] if_instruction;
    wire        if_bra_delay;



    wire        id_stall;
    wire        id_reg_dst;
    wire        id_alu_src;
    wire        id_mem_write;
    wire        id_mem_read;
    wire        id_mem_to_reg;
    wire        id_reg_write;
    wire        id_cmp_eq;
    wire        id_sign_extend;
    wire        id_jump_link;
    wire [4:0]  id_alu_op;
    wire        id_branch_delay_slot;


    wire [1:0]  id_fwd_rs_sel;
    wire [1:0]  id_fwd_rt_sel;
    wire        id_w_rs_ex;
    wire        id_n_rs_ex;
    wire        id_w_rt_ex;
    wire        id_n_rt_ex;


    wire [1:0]  id_pc_source_sel;


    wire [31:0] id_instruction;
    wire [4:0]  id_rs = id_instruction[25:21];
    wire [4:0]  id_rt = id_instruction[20:16];
    wire [5:0]  id_opcode = id_instruction[31:26];
    wire [5:0]  id_funct = id_instruction[5:0];
    wire [31:0] id_reg1_data;
    wire [31:0] id_reg1_end;
    wire [31:0] id_reg2_data;
    wire [31:0] id_reg2_end;
    wire [31:0] id_immediate = id_instruction[15:0];
    wire [31:0] id_pc_add_4;
    wire [31:0] id_pc;
    wire [31:0] id_jump_address = id_instruction[25:0];
    wire [31:0] id_jump_address_usable = {id_pc_add_4[31:28], id_jump_address[25:0], 2'b00};
    wire [31:0] id_sign_extended_immediate = (id_sign_extend & id_immediate[15]) ? {14'h3fff, id_immediate[15:0]} : {14'h0000, id_immediate[15:0]};
    wire [31:0] id_immediate_left_shifted2 = {id_sign_extended_immediate[29:0], 2'b00};
    wire [31:0] id_branch_address;



    wire        ex_stall;
    wire        ex_mem_read;
    wire        ex_mem_write;
    wire        ex_mem_to_reg;
    wire        ex_reg_write;
    wire        ex_alu_src;
    wire        ex_jump_link;
    wire [1:0]  ex_jump_link_reg_dst;
    wire [4:0]  ex_alu_op;


    wire [1:0]  ex_fwd_rs_sel;
    wire [1:0]  ex_fwd_rt_sel;
    wire        ex_w_rs_ex;
    wire        ex_n_rs_ex;
    wire        ex_w_rt_ex;
    wire        ex_n_rt_ex;


    wire [4:0]  ex_rs;
    wire [4:0]  ex_rt;
    wire [4:0]  ex_rd;
    wire [4:0]  ex_rt_rd;
    wire [4:0]  ex_shamt;
    wire [31:0] ex_reg1_data;
    wire [31:0] ex_reg1_fwd;
    wire [31:0] ex_reg2_data;
    wire [31:0] ex_reg2_fwd;
    wire [31:0] ex_data2_imm;
    wire [31:0] ex_sign_extended_immediate;
    wire [31:0] ex_alu_result;
    wire [31:0] ex_pc;
    wire        ex_alu_overflow;



    wire        me_mem_read;
    wire        me_mem_write;
    wire        me_mem_to_reg;
    wire        me_reg_write;


    wire        me_write_data_fwd_sel;


    wire [4:0]  me_rt_rd;
    wire [31:0] me_alu_result;
    wire [31:0] me_data2_reg;
    wire [31:0] me_pc;
    wire [31:0] me_mem_read_data;
    wire [31:0] me_mem_write_data;


    wire        wb_mem_to_reg;
    wire        wb_reg_write;
    wire [4:0]  wb_rt_rd;
    wire [31:0] wb_data_memory;
    wire [31:0] wb_alu_result;
    wire [31:0] wb_write_data;


    wire [7:0]  id_signal_forwarding;
    wire [7:0]  final_signal_forwarding;


    assign final_signal_forwarding = {id_signal_forwarding[7:4], ex_w_rs_ex, ex_n_rs_ex, ex_w_rt_ex, ex_n_rt_ex};

    assign if_bra_delay = id_branch_delay_slot;

    always @ ( * ) begin
         me_memory_address_out    <= me_alu_result;
         me_memory_write_out      <= me_mem_write;
         me_memory_read_out       <= me_mem_read;
         me_memory_data_write_out <= me_mem_write_data;
    end

    assign me_mem_read_data        = me_memory_data_read_in;









    Multiplex4 #(.WIDTH(32)) PC_Source_Selection_Mux (
        .sel (id_pc_source_sel),
        .in0 (if_pc_add_4),
        .in1 (id_jump_address_usable),
        .in2 (id_branch_address),
        .in3 (id_reg1_end),
        .out (if_pc_out)
    );


    PC_Latch PC (
        .clock  (clock),
        .reset  (reset),
        .enable (~(if_stall | id_stall)),
        .data   (if_pc_out),
        .value  (if_pc_usable)
    );


    InstructionMemoryInterface #(.INSTRUCTION_FILE(INSTRUCTIONS)) instruction_memory (
        .if_stall       (if_stall),
        .if_pc_usable   (if_pc_usable),
        .if_instruction (if_instruction)
    );


    SimpleAdder PC_Increment (
        .A (if_pc_usable),
        .B (32'h00000004),
        .C (if_pc_add_4)
    );


    Instruction_Fetch_Decode_Pipeline IF_ID (
        .clock          (clock),
        .reset          (reset),
        .if_flush       (if_flush),
        .if_stall       (if_stall),
        .id_stall       (id_stall),
        .if_bra_delay   (if_bra_delay),
        .if_pc_add_4    (if_pc_add_4),
        .if_pc_usable   (if_pc_usable),
        .if_instruction (if_instruction),
        .id_pc_add_4    (id_pc_add_4),
        .id_instruction (id_instruction),
        .id_pc          (id_pc)
    );






    RegisterFile RegisterAccess (
        .clock          (clock),
        .reset          (reset),
        .read_reg1      (id_rs),
        .read_reg2      (id_rt),
        .wb_rt_rd       (wb_rt_rd),
        .wb_write_data  (wb_write_data),
        .wb_reg_write   (wb_reg_write),
        .id_reg1_data   (id_reg1_data),
        .id_reg2_data   (id_reg2_data)
    );


    Multiplex4 #(.WIDTH(32)) ID_RS_Forwarding_Mux (
        .sel (id_fwd_rs_sel),
        .in0 (id_reg1_data),
        .in1 (me_alu_result),
        .in2 (wb_write_data),
        .in3 (32'hxxxxxxxx),
        .out (id_reg1_end)
    );


    Multiplex4 #(.WIDTH(32)) ID_RT_Forwarding_Mux (
        .sel (id_fwd_rt_sel),
        .in0 (id_reg2_data),
        .in1 (me_alu_result),
        .in2 (wb_write_data),
        .in3 (32'hxxxxxxxx),
        .out (id_reg2_end)
    );


    Comparator Branch_Antecipation (
        .A      (id_reg1_end),
        .B      (id_reg2_end),
        .Equals (id_cmp_eq)
    );


    SimpleAdder Branch_Address_Calculation (
        .A (id_pc_add_4),
        .B (id_immediate_left_shifted2),
        .C (id_branch_address)
    );


    ControlUnity Control (
        .id_stall               (id_stall),
        .id_opcode              (id_opcode),
        .id_funct               (id_funct),
        .id_cmp_eq              (id_cmp_eq),
        .if_flush               (if_flush),
        .id_signal_forwarding   (id_signal_forwarding),
        .id_pc_source_sel       (id_pc_source_sel),
        .id_sign_extend         (id_sign_extend),
        .id_jump_link           (id_jump_link),
        .id_reg_dst             (id_reg_dst),
        .id_alu_src             (id_alu_src),
        .id_alu_op              (id_alu_op),
        .id_mem_read            (id_mem_read),
        .id_mem_write           (id_mem_write),
        .id_mem_to_reg          (id_mem_to_reg),
        .id_reg_write           (id_reg_write),
        .id_branch_delay_slot   (id_branch_delay_slot)
    );


    Forwarding_Hazard_Unity ForwardingHazardControl (
        .sig_hazards    (final_signal_forwarding),
        .id_rs          (id_rs),
        .id_rt          (id_rt),
        .ex_rs          (ex_rs),
        .ex_rt          (ex_rt),
        .ex_rt_rd       (ex_rt_rd),
        .me_rt_rd       (me_rt_rd),
        .wb_rt_rd       (wb_rt_rd),
        .ex_jump_link   (ex_jump_link),
        .ex_reg_write   (ex_reg_write),
        .me_reg_write   (me_reg_write),
        .wb_reg_write   (wb_reg_write),
        .me_mem_read    (me_mem_read),
        .me_mem_write   (me_mem_write),
        .me_mem_to_reg  (me_mem_to_reg),
        .id_stall       (id_stall),
        .ex_stall       (ex_stall),
        .id_fwd_rs_sel  (id_fwd_rs_sel),
        .id_fwd_rt_sel  (id_fwd_rt_sel),
        .ex_fwd_rs_sel  (ex_fwd_rs_sel),
        .ex_fwd_rt_sel  (ex_fwd_rt_sel),
        .me_write_data_fwd_sel  (me_write_data_fwd_sel)
    );


    Instruction_Decode_Execute_Pipeline ID_EX (
        .clock                      (clock),
        .reset                      (reset),
        .id_stall                   (id_stall),
        .ex_stall                   (ex_stall),

        .id_jump_link               (id_jump_link),
        .id_reg_dst                 (id_reg_dst),
        .id_alu_src                 (id_alu_src),
        .id_alu_op                  (id_alu_op),
        .id_mem_read                (id_mem_read),
        .id_mem_write               (id_mem_write),
        .id_mem_to_reg              (id_mem_to_reg),
        .id_reg_write               (id_reg_write),
        .id_rs                      (id_rs),
        .id_rt                      (id_rt),
        .id_w_rs_ex                 (id_signal_forwarding[3]),
        .id_n_rs_ex                 (id_signal_forwarding[2]),
        .id_w_rt_ex                 (id_signal_forwarding[1]),
        .id_n_rt_ex                 (id_signal_forwarding[0]),
        .id_reg1_end                (id_reg1_end),
        .id_reg2_end                (id_reg2_end),
        .id_sign_extended_immediate (id_sign_extended_immediate[16:0]),
        .id_pc                      (id_pc),

        .ex_jump_link               (ex_jump_link),
        .ex_jump_link_reg_dst       (ex_jump_link_reg_dst),
        .ex_alu_src                 (ex_alu_src),
        .ex_alu_op                  (ex_alu_op),
        .ex_mem_read                (ex_mem_read),
        .ex_mem_write               (ex_mem_write),
        .ex_mem_to_reg              (ex_mem_to_reg),
        .ex_reg_write               (ex_reg_write),
        .ex_rs                      (ex_rs),
        .ex_rt                      (ex_rt),
        .ex_w_rs_ex                 (ex_w_rs_ex),
        .ex_n_rs_ex                 (ex_n_rs_ex),
        .ex_w_rt_ex                 (ex_w_rt_ex),
        .ex_n_rt_ex                 (ex_n_rt_ex),
        .ex_reg1_data               (ex_reg1_data),
        .ex_reg2_data               (ex_reg2_data),
        .ex_sign_extended_immediate (ex_sign_extended_immediate),
        .ex_rd                      (ex_rd),
        .ex_shamt                   (ex_shamt),
        .ex_pc                      (ex_pc)
    );




    Multiplex4 #(.WIDTH(32)) EX_RS_Forwarding_Mux (
        .sel (ex_fwd_rs_sel),
        .in0 (ex_reg1_data),
        .in1 (me_alu_result),
        .in2 (wb_write_data),
        .in3 (ex_pc),
        .out (ex_reg1_fwd)
    );


    Multiplex4 #(.WIDTH(32)) EX_RT_Forwarding_Mux (
        .sel (ex_fwd_rt_sel),
        .in0 (ex_reg2_data),
        .in1 (me_alu_result),
        .in2 (wb_write_data),
        .in3 (32'h00000004),
        .out (ex_reg2_fwd)
    );


    assign ex_data2_imm = (ex_alu_src) ? ex_sign_extended_immediate : ex_reg2_fwd;


    Multiplex4 #(.WIDTH(5)) EX_Reg_Destination_Mux (
        .sel (ex_jump_link_reg_dst),
        .in0 (ex_rt),
        .in1 (ex_rd),
        .in2 (5'b11111),
        .in3 (5'bxxxxx),
        .out (ex_rt_rd)
    );


    ArithmeticLogicUnit ALU (
        .A          (ex_reg1_fwd),
        .B          (ex_data2_imm),
        .operation  (ex_alu_op),
        .shamt      (ex_shamt),
        .result     (ex_alu_result),
        .overflow   (ex_alu_overflow)
    );


    Execute_Memory_Pipeline EX_MEM (
        .clock          (clock),
        .reset          (reset),
        .ex_stall       (ex_stall),

        .ex_mem_read    (ex_mem_read),
        .ex_mem_write   (ex_mem_write),
        .ex_mem_to_reg  (ex_mem_to_reg),
        .ex_reg_write   (ex_reg_write),
        .ex_alu_result  (ex_alu_result),
        .ex_reg2_fwd    (ex_reg2_fwd),
        .ex_rt_rd       (ex_rt_rd),

        .me_mem_read    (me_mem_read),
        .me_mem_write   (me_mem_write),
        .me_mem_to_reg  (me_mem_to_reg),
        .me_reg_write   (me_reg_write),
        .me_alu_result  (me_alu_result),
        .me_data2_reg   (me_data2_reg),
        .me_rt_rd       (me_rt_rd)
    );




    assign me_mem_write_data = (me_write_data_fwd_sel) ? wb_write_data : me_data2_reg;




    assign d_test_valid = (me_alu_result >= 32'd256) ? 1'b1 : 1'b0;


    Memory_WriteBack_Pipeline MEM_WB (
        .clock              (clock),
        .reset              (reset),

        .me_reg_write       (me_reg_write),
        .me_mem_to_reg      (me_mem_to_reg),
        .me_mem_read_data   (me_mem_read_data),
        .me_alu_result      (me_alu_result),
        .me_rt_rd           (me_rt_rd),

        .wb_reg_write       (wb_reg_write),
        .wb_mem_to_reg      (wb_mem_to_reg),
        .wb_data_memory     (wb_data_memory),
        .wb_alu_result      (wb_alu_result),
        .wb_rt_rd           (wb_rt_rd)
    );




    assign wb_write_data = (wb_mem_to_reg) ? wb_data_memory : wb_alu_result;
endmodule
module Processor (
    input clock,
    input reset,

    output              d_test_valid,

    output reg          me_memory_write_out,
    output reg          me_memory_read_out,
    output reg [31:0]   me_memory_data_write_out,
    output reg [31:0]   me_memory_address_out,
    input      [31:0]   me_memory_data_read_in

);


    parameter INSTRUCTIONS = "C:/Outros/Full Processor/MIPS32_Processor/Final Project/MIPS32_Full/Testing Codes/Exponential.txt";



    wire        if_stall;
    wire        if_flush;
    wire [31:0] if_pc;
    wire [31:0] if_pc_out;
    wire [31:0] if_pc_usable;
    wire [31:0] if_pc_add_4;
    wire [31:0] if_instruction;
    wire        if_bra_delay;



    wire        id_stall;
    wire        id_reg_dst;
    wire        id_alu_src;
    wire        id_mem_write;
    wire        id_mem_read;
    wire        id_mem_to_reg;
    wire        id_reg_write;
    wire        id_cmp_eq;
    wire        id_sign_extend;
    wire        id_jump_link;
    wire [4:0]  id_alu_op;
    wire        id_branch_delay_slot;


    wire [1:0]  id_fwd_rs_sel;
    wire [1:0]  id_fwd_rt_sel;
    wire        id_w_rs_ex;
    wire        id_n_rs_ex;
    wire        id_w_rt_ex;
    wire        id_n_rt_ex;


    wire [1:0]  id_pc_source_sel;


    wire [31:0] id_instruction;
    wire [4:0]  id_rs = id_instruction[25:21];
    wire [4:0]  id_rt = id_instruction[20:16];
    wire [5:0]  id_opcode = id_instruction[31:26];
    wire [5:0]  id_funct = id_instruction[5:0];
    wire [31:0] id_reg1_data;
    wire [31:0] id_reg1_end;
    wire [31:0] id_reg2_data;
    wire [31:0] id_reg2_end;
    wire [31:0] id_immediate = id_instruction[15:0];
    wire [31:0] id_pc_add_4;
    wire [31:0] id_pc;
    wire [31:0] id_jump_address = id_instruction[25:0];
    wire [31:0] id_jump_address_usable = {id_pc_add_4[31:28], id_jump_address[25:0], 2'b00};
    wire [31:0] id_sign_extended_immediate = (id_sign_extend & id_immediate[15]) ? {14'h3fff, id_immediate[15:0]} : {14'h0000, id_immediate[15:0]};
    wire [31:0] id_immediate_left_shifted2 = {id_sign_extended_immediate[29:0], 2'b00};
    wire [31:0] id_branch_address;



    wire        ex_stall;
    wire        ex_mem_read;
    wire        ex_mem_write;
    wire        ex_mem_to_reg;
    wire        ex_reg_write;
    wire        ex_alu_src;
    wire        ex_jump_link;
    wire [1:0]  ex_jump_link_reg_dst;
    wire [4:0]  ex_alu_op;


    wire [1:0]  ex_fwd_rs_sel;
    wire [1:0]  ex_fwd_rt_sel;
    wire        ex_w_rs_ex;
    wire        ex_n_rs_ex;
    wire        ex_w_rt_ex;
    wire        ex_n_rt_ex;


    wire [4:0]  ex_rs;
    wire [4:0]  ex_rt;
    wire [4:0]  ex_rd;
    wire [4:0]  ex_rt_rd;
    wire [4:0]  ex_shamt;
    wire [31:0] ex_reg1_data;
    wire [31:0] ex_reg1_fwd;
    wire [31:0] ex_reg2_data;
    wire [31:0] ex_reg2_fwd;
    wire [31:0] ex_data2_imm;
    wire [31:0] ex_sign_extended_immediate;
    wire [31:0] ex_alu_result;
    wire [31:0] ex_pc;
    wire        ex_alu_overflow;



    wire        me_mem_read;
    wire        me_mem_write;
    wire        me_mem_to_reg;
    wire        me_reg_write;


    wire        me_write_data_fwd_sel;


    wire [4:0]  me_rt_rd;
    wire [31:0] me_alu_result;
    wire [31:0] me_data2_reg;
    wire [31:0] me_pc;
    wire [31:0] me_mem_read_data;
    wire [31:0] me_mem_write_data;


    wire        wb_mem_to_reg;
    wire        wb_reg_write;
    wire [4:0]  wb_rt_rd;
    wire [31:0] wb_data_memory;
    wire [31:0] wb_alu_result;
    wire [31:0] wb_write_data;


    wire [7:0]  id_signal_forwarding;
    wire [7:0]  final_signal_forwarding;


    assign final_signal_forwarding = {id_signal_forwarding[7:4], ex_w_rs_ex, ex_n_rs_ex, ex_w_rt_ex, ex_n_rt_ex};

    assign if_bra_delay = id_branch_delay_slot;

    always @ ( * ) begin
         me_memory_address_out    <= me_alu_result;
         me_memory_write_out      <= me_mem_write;
         me_memory_read_out       <= me_mem_read;
         me_memory_data_write_out <= me_mem_write_data;
    end

    assign me_mem_read_data        = me_memory_data_read_in;









    Multiplex4 #(.WIDTH(32)) PC_Source_Selection_Mux (
        .sel (id_pc_source_sel),
        .in0 (if_pc_add_4),
        .in1 (id_jump_address_usable),
        .in2 (id_branch_address),
        .in3 (id_reg1_end),
        .out (if_pc_out)
    );


    PC_Latch PC (
        .clock  (clock),
        .reset  (reset),
        .enable (~(if_stall | id_stall)),
        .data   (if_pc_out),
        .value  (if_pc_usable)
    );


    InstructionMemoryInterface #(.INSTRUCTION_FILE(INSTRUCTIONS)) instruction_memory (
        .if_stall       (if_stall),
        .if_pc_usable   (if_pc_usable),
        .if_instruction (if_instruction)
    );


    SimpleAdder PC_Increment (
        .A (if_pc_usable),
        .B (32'h00000004),
        .C (if_pc_add_4)
    );


    Instruction_Fetch_Decode_Pipeline IF_ID (
        .clock          (clock),
        .reset          (reset),
        .if_flush       (if_flush),
        .if_stall       (if_stall),
        .id_stall       (id_stall),
        .if_bra_delay   (if_bra_delay),
        .if_pc_add_4    (if_pc_add_4),
        .if_pc_usable   (if_pc_usable),
        .if_instruction (if_instruction),
        .id_pc_add_4    (id_pc_add_4),
        .id_instruction (id_instruction),
        .id_pc          (id_pc)
    );






    RegisterFile RegisterAccess (
        .clock          (clock),
        .reset          (reset),
        .read_reg1      (id_rs),
        .read_reg2      (id_rt),
        .wb_rt_rd       (wb_rt_rd),
        .wb_write_data  (wb_write_data),
        .wb_reg_write   (wb_reg_write),
        .id_reg1_data   (id_reg1_data),
        .id_reg2_data   (id_reg2_data)
    );


    Multiplex4 #(.WIDTH(32)) ID_RS_Forwarding_Mux (
        .sel (id_fwd_rs_sel),
        .in0 (id_reg1_data),
        .in1 (me_alu_result),
        .in2 (wb_write_data),
        .in3 (32'hxxxxxxxx),
        .out (id_reg1_end)
    );


    Multiplex4 #(.WIDTH(32)) ID_RT_Forwarding_Mux (
        .sel (id_fwd_rt_sel),
        .in0 (id_reg2_data),
        .in1 (me_alu_result),
        .in2 (wb_write_data),
        .in3 (32'hxxxxxxxx),
        .out (id_reg2_end)
    );


    Comparator Branch_Antecipation (
        .A      (id_reg1_end),
        .B      (id_reg2_end),
        .Equals (id_cmp_eq)
    );


    SimpleAdder Branch_Address_Calculation (
        .A (id_pc_add_4),
        .B (id_immediate_left_shifted2),
        .C (id_branch_address)
    );


    ControlUnity Control (
        .id_stall               (id_stall),
        .id_opcode              (id_opcode),
        .id_funct               (id_funct),
        .id_cmp_eq              (id_cmp_eq),
        .if_flush               (if_flush),
        .id_signal_forwarding   (id_signal_forwarding),
        .id_pc_source_sel       (id_pc_source_sel),
        .id_sign_extend         (id_sign_extend),
        .id_jump_link           (id_jump_link),
        .id_reg_dst             (id_reg_dst),
        .id_alu_src             (id_alu_src),
        .id_alu_op              (id_alu_op),
        .id_mem_read            (id_mem_read),
        .id_mem_write           (id_mem_write),
        .id_mem_to_reg          (id_mem_to_reg),
        .id_reg_write           (id_reg_write),
        .id_branch_delay_slot   (id_branch_delay_slot)
    );


    Forwarding_Hazard_Unity ForwardingHazardControl (
        .sig_hazards    (final_signal_forwarding),
        .id_rs          (id_rs),
        .id_rt          (id_rt),
        .ex_rs          (ex_rs),
        .ex_rt          (ex_rt),
        .ex_rt_rd       (ex_rt_rd),
        .me_rt_rd       (me_rt_rd),
        .wb_rt_rd       (wb_rt_rd),
        .ex_jump_link   (ex_jump_link),
        .ex_reg_write   (ex_reg_write),
        .me_reg_write   (me_reg_write),
        .wb_reg_write   (wb_reg_write),
        .me_mem_read    (me_mem_read),
        .me_mem_write   (me_mem_write),
        .me_mem_to_reg  (me_mem_to_reg),
        .id_stall       (id_stall),
        .ex_stall       (ex_stall),
        .id_fwd_rs_sel  (id_fwd_rs_sel),
        .id_fwd_rt_sel  (id_fwd_rt_sel),
        .ex_fwd_rs_sel  (ex_fwd_rs_sel),
        .ex_fwd_rt_sel  (ex_fwd_rt_sel),
        .me_write_data_fwd_sel  (me_write_data_fwd_sel)
    );


    Instruction_Decode_Execute_Pipeline ID_EX (
        .clock                      (clock),
        .reset                      (reset),
        .id_stall                   (id_stall),
        .ex_stall                   (ex_stall),

        .id_jump_link               (id_jump_link),
        .id_reg_dst                 (id_reg_dst),
        .id_alu_src                 (id_alu_src),
        .id_alu_op                  (id_alu_op),
        .id_mem_read                (id_mem_read),
        .id_mem_write               (id_mem_write),
        .id_mem_to_reg              (id_mem_to_reg),
        .id_reg_write               (id_reg_write),
        .id_rs                      (id_rs),
        .id_rt                      (id_rt),
        .id_w_rs_ex                 (id_signal_forwarding[3]),
        .id_n_rs_ex                 (id_signal_forwarding[2]),
        .id_w_rt_ex                 (id_signal_forwarding[1]),
        .id_n_rt_ex                 (id_signal_forwarding[0]),
        .id_reg1_end                (id_reg1_end),
        .id_reg2_end                (id_reg2_end),
        .id_sign_extended_immediate (id_sign_extended_immediate[16:0]),
        .id_pc                      (id_pc),

        .ex_jump_link               (ex_jump_link),
        .ex_jump_link_reg_dst       (ex_jump_link_reg_dst),
        .ex_alu_src                 (ex_alu_src),
        .ex_alu_op                  (ex_alu_op),
        .ex_mem_read                (ex_mem_read),
        .ex_mem_write               (ex_mem_write),
        .ex_mem_to_reg              (ex_mem_to_reg),
        .ex_reg_write               (ex_reg_write),
        .ex_rs                      (ex_rs),
        .ex_rt                      (ex_rt),
        .ex_w_rs_ex                 (ex_w_rs_ex),
        .ex_n_rs_ex                 (ex_n_rs_ex),
        .ex_w_rt_ex                 (ex_w_rt_ex),
        .ex_n_rt_ex                 (ex_n_rt_ex),
        .ex_reg1_data               (ex_reg1_data),
        .ex_reg2_data               (ex_reg2_data),
        .ex_sign_extended_immediate (ex_sign_extended_immediate),
        .ex_rd                      (ex_rd),
        .ex_shamt                   (ex_shamt),
        .ex_pc                      (ex_pc)
    );




    Multiplex4 #(.WIDTH(32)) EX_RS_Forwarding_Mux (
        .sel (ex_fwd_rs_sel),
        .in0 (ex_reg1_data),
        .in1 (me_alu_result),
        .in2 (wb_write_data),
        .in3 (ex_pc),
        .out (ex_reg1_fwd)
    );


    Multiplex4 #(.WIDTH(32)) EX_RT_Forwarding_Mux (
        .sel (ex_fwd_rt_sel),
        .in0 (ex_reg2_data),
        .in1 (me_alu_result),
        .in2 (wb_write_data),
        .in3 (32'h00000004),
        .out (ex_reg2_fwd)
    );


    assign ex_data2_imm = (ex_alu_src) ? ex_sign_extended_immediate : ex_reg2_fwd;


    Multiplex4 #(.WIDTH(5)) EX_Reg_Destination_Mux (
        .sel (ex_jump_link_reg_dst),
        .in0 (ex_rt),
        .in1 (ex_rd),
        .in2 (5'b11111),
        .in3 (5'bxxxxx),
        .out (ex_rt_rd)
    );


    ArithmeticLogicUnit ALU (
        .A          (ex_reg1_fwd),
        .B          (ex_data2_imm),
        .operation  (ex_alu_op),
        .shamt      (ex_shamt),
        .result     (ex_alu_result),
        .overflow   (ex_alu_overflow)
    );


    Execute_Memory_Pipeline EX_MEM (
        .clock          (clock),
        .reset          (reset),
        .ex_stall       (ex_stall),

        .ex_mem_read    (ex_mem_read),
        .ex_mem_write   (ex_mem_write),
        .ex_mem_to_reg  (ex_mem_to_reg),
        .ex_reg_write   (ex_reg_write),
        .ex_alu_result  (ex_alu_result),
        .ex_reg2_fwd    (ex_reg2_fwd),
        .ex_rt_rd       (ex_rt_rd),

        .me_mem_read    (me_mem_read),
        .me_mem_write   (me_mem_write),
        .me_mem_to_reg  (me_mem_to_reg),
        .me_reg_write   (me_reg_write),
        .me_alu_result  (me_alu_result),
        .me_data2_reg   (me_data2_reg),
        .me_rt_rd       (me_rt_rd)
    );




    assign me_mem_write_data = (me_write_data_fwd_sel) ? wb_write_data : me_data2_reg;




    assign d_test_valid = (me_alu_result >= 32'd256) ? 1'b1 : 1'b0;


    Memory_WriteBack_Pipeline MEM_WB (
        .clock              (clock),
        .reset              (reset),

        .me_reg_write       (me_reg_write),
        .me_mem_to_reg      (me_mem_to_reg),
        .me_mem_read_data   (me_mem_read_data),
        .me_alu_result      (me_alu_result),
        .me_rt_rd           (me_rt_rd),

        .wb_reg_write       (wb_reg_write),
        .wb_mem_to_reg      (wb_mem_to_reg),
        .wb_data_memory     (wb_data_memory),
        .wb_alu_result      (wb_alu_result),
        .wb_rt_rd           (wb_rt_rd)
    );




    assign wb_write_data = (wb_mem_to_reg) ? wb_data_memory : wb_alu_result;
endmodule