data/full_repos/permissive/143278/ivltests/port-test3.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test3.v:40: Unsupported: Ignoring delay on this delayed statement.\n                #1000;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test3.v:45: Unsupported: Ignoring delay on this delayed statement.\n                # 10 clock <= ~clock;\n                ^\n%Error-ASSIGNIN: data/full_repos/permissive/143278/ivltests/port-test3.v:21: Assigning to input/const variable: \'rw\'\n                rw <= 1\'b1;\n                ^~\n%Error-ASSIGNIN: data/full_repos/permissive/143278/ivltests/port-test3.v:25: Assigning to input/const variable: \'rw\'\n                rw <= 1\'b0;\n                ^~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module BENCH ();

        reg [15:0] address, data;
        reg rw, clock, reset;

        CPU fm (address, data, rw, clock, reset);

        initial begin
                clock <= 0;
                reset <= 1;
                #1000;
                $finish;
        end

        always begin
                # 10 clock <= ~clock;
        end

endmodule
module BENCH ();


        reg [15:0] address, data;
        reg rw, clock, reset;

        CPU fm (address, data, rw, clock, reset);

        initial begin
                clock <= 0;
                reset <= 1;
                #1000;
                $finish;
        end

        always begin
                # 10 clock <= ~clock;
        end

endmodule