data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v
'utf-8' codec can't decode byte 0xbe in position 5: invalid start byte
1: b'%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:2: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.v\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:9: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus]       wd_i,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus]       wd_i,\n                       ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus]       wdata_i,\n ^~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:11: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]       wdata_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:13: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus]        aluop_i,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]          mem_addr_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]          reg2_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:18: Define or directive not defined: \'`RegBus\'\n   input wire[`RegBus]          mem_data_i,\n              ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:21: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus]      wd_o,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus]      wdata_o,\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:23: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]      wdata_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:26: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]          mem_addr_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[3:0]              mem_sel_o,\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus]          mem_data_o,\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:29: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]          mem_data_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:34: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] zero32;\n      ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] zero32;\n             ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:36: syntax error, unexpected assign\n assign mem_we_o = mem_we ;\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:37: Define or directive not defined: \'`ZeroWord\'\n assign zero32 = `ZeroWord;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:42: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:43: Define or directive not defined: \'`NOPRegAddr\'\n   wd_o <= `NOPRegAddr;\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:44: Define or directive not defined: \'`WriteDisable\'\n   wreg_o <= `WriteDisable;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:45: Define or directive not defined: \'`ZeroWord\'\n     wdata_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:46: Define or directive not defined: \'`ZeroWord\'\n     mem_addr_o <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:47: Define or directive not defined: \'`WriteDisable\'\n    mem_we <= `WriteDisable;\n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:49: Define or directive not defined: \'`ZeroWord\'\n    mem_data_o <= `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:50: Define or directive not defined: \'`ChipDisable\'\n    mem_ce_o <= `ChipDisable;\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:55: Define or directive not defined: \'`WriteDisable\'\n   mem_we <= `WriteDisable;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:56: Define or directive not defined: \'`ZeroWord\'\n   mem_addr_o <= `ZeroWord;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:58: Define or directive not defined: \'`ChipDisable\'\n   mem_ce_o <= `ChipDisable;\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:60: Define or directive not defined: \'`EXE_LB_OP\'\n    `EXE_LB_OP:  begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:62: Define or directive not defined: \'`WriteDisable\'\n     mem_we <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:63: Define or directive not defined: \'`ChipEnable\'\n     mem_ce_o <= `ChipEnable;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:67: Define or directive not defined: \'`EXE_LBU_OP\'\n    `EXE_LBU_OP:  begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:69: Define or directive not defined: \'`WriteDisable\'\n     mem_we <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:70: Define or directive not defined: \'`ChipEnable\'\n     mem_ce_o <= `ChipEnable;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:74: Define or directive not defined: \'`EXE_LH_OP\'\n    `EXE_LH_OP:  begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:76: Define or directive not defined: \'`WriteDisable\'\n     mem_we <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:77: Define or directive not defined: \'`ChipEnable\'\n     mem_ce_o <= `ChipEnable;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:81: Define or directive not defined: \'`EXE_LHU_OP\'\n    `EXE_LHU_OP:  begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:83: Define or directive not defined: \'`WriteDisable\'\n     mem_we <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:84: Define or directive not defined: \'`ChipEnable\'\n     mem_ce_o <= `ChipEnable;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:88: Define or directive not defined: \'`EXE_LW_OP\'\n    `EXE_LW_OP:  begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:90: Define or directive not defined: \'`WriteDisable\'\n     mem_we <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:91: Define or directive not defined: \'`ChipEnable\'\n     mem_ce_o <= `ChipEnable;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:95: Define or directive not defined: \'`EXE_SB_OP\'\n    `EXE_SB_OP:  begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:97: Define or directive not defined: \'`WriteEnable\'\n     mem_we <= `WriteEnable;\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:99: Define or directive not defined: \'`ChipEnable\'\n     mem_ce_o <= `ChipEnable;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/mem.v:102: Define or directive not defined: \'`EXE_SH_OP\'\n    `EXE_SH_OP:  begin\n    ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mem(

	input wire										rst,


	input wire[`RegAddrBus]       wd_i,
	input wire                    wreg_i,
	input wire[`RegBus]					  wdata_i,

	input wire[`AluOpBus]        aluop_i,
	input wire[`RegBus]          mem_addr_i,
	input wire[`RegBus]          reg2_i,


  	input wire[`RegBus]          mem_data_i,


	output reg[`RegAddrBus]      wd_o,
	output reg                   wreg_o,
	output reg[`RegBus]					 wdata_o,


	output reg[`RegBus]          mem_addr_o,
	output wire									 mem_we_o,
	output reg[3:0]              mem_sel_o,
	output reg[`RegBus]          mem_data_o,
	output reg                   mem_ce_o

);

	wire[`RegBus] zero32;
	reg mem_we;
	assign mem_we_o = mem_we ;
	assign zero32 = `ZeroWord;



	always @ (*) begin
		if(rst == `RstEnable) begin
			wd_o <= `NOPRegAddr;
			wreg_o <= `WriteDisable;
		  	wdata_o <= `ZeroWord;
		  	mem_addr_o <= `ZeroWord;
		 	mem_we <= `WriteDisable;
		 	mem_sel_o <= 4'b0000;
		 	mem_data_o <= `ZeroWord;
		 	mem_ce_o <= `ChipDisable;
		end else begin
		  wd_o <= wd_i;
			wreg_o <= wreg_i;
			wdata_o <= wdata_i;
			mem_we <= `WriteDisable;
			mem_addr_o <= `ZeroWord;

			mem_ce_o <= `ChipDisable;
			case (aluop_i)
				`EXE_LB_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteDisable;
					mem_ce_o <= `ChipEnable;
					wdata_o <= {{24{mem_data_i[7]}}, mem_data_i[7:0]};

				end
				`EXE_LBU_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteDisable;
					mem_ce_o <= `ChipEnable;
					wdata_o <= {{24{1'b0}}, mem_data_i[7:0]};

				end
				`EXE_LH_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteDisable;
					mem_ce_o <= `ChipEnable;
					wdata_o <= {{16{mem_data_i[15]}}, mem_data_i[15:0]};

				end
				`EXE_LHU_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteDisable;
					mem_ce_o <= `ChipEnable;
					wdata_o <= {{16{1'b0}}, mem_data_i[15:0]};

				end
				`EXE_LW_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteDisable;
					mem_ce_o <= `ChipEnable;
					wdata_o <= mem_data_i;

				end
				`EXE_SB_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteEnable;
					mem_data_o <= {{24{1'b0}},reg2_i[7:0]};
					mem_ce_o <= `ChipEnable;
					mem_sel_o <= 4'b0001;
				end
				`EXE_SH_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteEnable;
					mem_data_o <= {{16{1'b0}},reg2_i[15:0]};
					mem_ce_o <= `ChipEnable;
					mem_sel_o <= 4'b0010;
				end
				`EXE_SW_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteEnable;
					mem_data_o <= reg2_i;
					mem_ce_o <= `ChipEnable;
					mem_sel_o <= 4'b0100;
				end
			endcase
		end
	end


endmodule
module mem(

	input wire										rst,


	input wire[`RegAddrBus]       wd_i,
	input wire                    wreg_i,
	input wire[`RegBus]					  wdata_i,

	input wire[`AluOpBus]        aluop_i,
	input wire[`RegBus]          mem_addr_i,
	input wire[`RegBus]          reg2_i,


  	input wire[`RegBus]          mem_data_i,


	output reg[`RegAddrBus]      wd_o,
	output reg                   wreg_o,
	output reg[`RegBus]					 wdata_o,


	output reg[`RegBus]          mem_addr_o,
	output wire									 mem_we_o,
	output reg[3:0]              mem_sel_o,
	output reg[`RegBus]          mem_data_o,
	output reg                   mem_ce_o

);


	wire[`RegBus] zero32;
	reg mem_we;
	assign mem_we_o = mem_we ;
	assign zero32 = `ZeroWord;



	always @ (*) begin
		if(rst == `RstEnable) begin
			wd_o <= `NOPRegAddr;
			wreg_o <= `WriteDisable;
		  	wdata_o <= `ZeroWord;
		  	mem_addr_o <= `ZeroWord;
		 	mem_we <= `WriteDisable;
		 	mem_sel_o <= 4'b0000;
		 	mem_data_o <= `ZeroWord;
		 	mem_ce_o <= `ChipDisable;
		end else begin
		  wd_o <= wd_i;
			wreg_o <= wreg_i;
			wdata_o <= wdata_i;
			mem_we <= `WriteDisable;
			mem_addr_o <= `ZeroWord;

			mem_ce_o <= `ChipDisable;
			case (aluop_i)
				`EXE_LB_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteDisable;
					mem_ce_o <= `ChipEnable;
					wdata_o <= {{24{mem_data_i[7]}}, mem_data_i[7:0]};

				end
				`EXE_LBU_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteDisable;
					mem_ce_o <= `ChipEnable;
					wdata_o <= {{24{1'b0}}, mem_data_i[7:0]};

				end
				`EXE_LH_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteDisable;
					mem_ce_o <= `ChipEnable;
					wdata_o <= {{16{mem_data_i[15]}}, mem_data_i[15:0]};

				end
				`EXE_LHU_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteDisable;
					mem_ce_o <= `ChipEnable;
					wdata_o <= {{16{1'b0}}, mem_data_i[15:0]};

				end
				`EXE_LW_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteDisable;
					mem_ce_o <= `ChipEnable;
					wdata_o <= mem_data_i;

				end
				`EXE_SB_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteEnable;
					mem_data_o <= {{24{1'b0}},reg2_i[7:0]};
					mem_ce_o <= `ChipEnable;
					mem_sel_o <= 4'b0001;
				end
				`EXE_SH_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteEnable;
					mem_data_o <= {{16{1'b0}},reg2_i[15:0]};
					mem_ce_o <= `ChipEnable;
					mem_sel_o <= 4'b0010;
				end
				`EXE_SW_OP:		begin
					mem_addr_o <= mem_addr_i;
					mem_we <= `WriteEnable;
					mem_data_o <= reg2_i;
					mem_ce_o <= `ChipEnable;
					mem_sel_o <= 4'b0100;
				end
			endcase
		end
	end


endmodule