data/full_repos/permissive/212981921/rtl/ls30.v
 line:26: before: "RESS"
data/verilator_xmls/721e0f74-5395-4e81-82c7-7ce0a856eaa2.xml
module ls30
(
    input wire  a, b, c, d, e, f, g, h,
    output wire y
);

assign y = ~(a & b & c & d & e & f & g & h);

endmodule
module ls30
(
    input wire  a, b, c, d, e, f, g, h,
    output wire y
);


assign y = ~(a & b & c & d & e & f & g & h);

endmodule