data/full_repos/permissive/143286506/execute.v
 line:45: before: "case"
1: b"%Error: data/full_repos/permissive/143286506/execute.v:97: syntax error, unexpected INTEGER NUMBER\n      5'b01_001: assign reg2 = {8'd0,r2[7:0],r2[15:8].8'd0};\n                                                      ^~~~\n%Error: data/full_repos/permissive/143286506/execute.v:118: syntax error, unexpected ',', expecting '}'\n      5'b00_000: assign res = {24{dm_r_data [7]},dm_r_data [7:0]};\n                                                ^\n%Error: data/full_repos/permissive/143286506/execute.v:119: syntax error, unexpected ',', expecting '}'\n      5'b01_000: assign res = {24{dm_r_data [15]},dm_r_data [15:8]};\n                                                 ^\n%Error: data/full_repos/permissive/143286506/execute.v:120: syntax error, unexpected ',', expecting '}'\n      5'b10_000: assign res = {24{dm_r_data [23]},dm_r_data [23:16]};\n                                                 ^\n%Error: data/full_repos/permissive/143286506/execute.v:121: syntax error, unexpected ',', expecting '}'\n      5'b11_000: assign res = {24{dm_r_data [31]},dm_r_data [31:24]};\n                                                 ^\n%Error: data/full_repos/permissive/143286506/execute.v:126: syntax error, unexpected ',', expecting '}'\n      5'b00_001: assign res = {16{dm_r_data [7]},dm_r_data [7:0],dm_r_data [15:8]};\n                                                ^\n%Error: data/full_repos/permissive/143286506/execute.v:127: syntax error, unexpected ',', expecting '}'\n      5'b01_001: assign res = {16{dm_r_data [15]},dm_r_data [15:8],dm_r_data [23:16]};\n                                                 ^\n%Error: data/full_repos/permissive/143286506/execute.v:128: syntax error, unexpected ',', expecting '}'\n      5'b10_001: assign res = {16{dm_r_data [23]},dm_r_data [23:16],dm_r_data [31:24]};\n                                                 ^\n%Error: data/full_repos/permissive/143286506/execute.v:143: syntax error, unexpected '(', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule (alures,memres,CSRres,lastres,selectop);\n        ^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module alu (r1,r2,shamt,imm,rd,mainop,subop,riselect);
    input [31:0]r1;
    input [31:0]r2;
    input [4:0]shamt;
    input [31:0]imm;

    input [2:0]mainop;
    input subop;
    input riselect;

    output rd;

    wire [3:0]aluop;
    wire [31:0]op1;
    wire [31:0]op2;

    assign aluop = {subop,mainop[2:0]};
    assign op1 = r1;
    assign op2 = (riselect)?r2:imm;
    case (op)
      ALU_ADD:  assign rd = op1 + op2;
      ALU_SUB:  assign rd = op1 - op2;
      ALU_SL:   assign rd = op1 << op2[4:0];
      ALU_SLT:  assign rd = $signed(op1) < $signed(op2);
      ALU_SLTU: assign rd = op1 < op2;
      ALU_XOR:  assign rd = op1 ^ op2;
      ALU_SRL:  assign rd = op1 >> op2[4:0];
      ALU_SRA:  assign rd = op1 >>> op2[4:0];
      ALU_OR:   assign rd = op1 | op2;
      ALU_AND:  assign rd = op1 & op2;
      default:  assign rd = 32'bx; 
    endcase
endmodule
module alu (r1,r2,shamt,imm,rd,mainop,subop,riselect);

    input [31:0]r1;
    input [31:0]r2;
    input [4:0]shamt;
    input [31:0]imm;

    input [2:0]mainop;
    input subop;
    input riselect;

    output rd;

    wire [3:0]aluop;
    wire [31:0]op1;
    wire [31:0]op2;

    assign aluop = {subop,mainop[2:0]};
    assign op1 = r1;
    assign op2 = (riselect)?r2:imm;
    case (op)
      ALU_ADD:  assign rd = op1 + op2;
      ALU_SUB:  assign rd = op1 - op2;
      ALU_SL:   assign rd = op1 << op2[4:0];
      ALU_SLT:  assign rd = $signed(op1) < $signed(op2);
      ALU_SLTU: assign rd = op1 < op2;
      ALU_XOR:  assign rd = op1 ^ op2;
      ALU_SRL:  assign rd = op1 >> op2[4:0];
      ALU_SRA:  assign rd = op1 >>> op2[4:0];
      ALU_OR:   assign rd = op1 | op2;
      ALU_AND:  assign rd = op1 & op2;
      default:  assign rd = 32'bx; 
    endcase
endmodule