data/full_repos/permissive/21702465/source/Runs.v
1: b"%Error: data/full_repos/permissive/21702465/source/Runs.v:25: syntax error, unexpected rand, expecting '['\n    input wire rand,\n               ^~~~\n%Error: data/full_repos/permissive/21702465/source/Runs.v:35: syntax error, unexpected assign\nassign en = (count_bits1 == (N-1));\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Runs(
    input wire clk,
    input wire rst,
    input wire rand,
    output wire pass
    );
	 
parameter N = 20000;

reg [14:0] count_bits0, count_bits1, count_ones, count_runs;
reg rand1;
wire en;
wire p_1, p_2;
assign en = (count_bits1 == (N-1));
assign pass = p_1 & p_2;

decision decision(
	.clk(clk),
	.rst(rst),
	.en(en),
	.count_ones(count_ones),
	.count_runs(count_runs),
	.p_1(p_1),
	.p_2(p_2)
	);

always @(posedge clk)
	if (rst) begin
		count_bits0 <= 15'H7FFF;
		count_bits1 <= 0;
		count_ones <= 0;
		count_runs <= 1;
		rand1 <= 0;
	end
	else begin 
		rand1 <= rand;
		
		count_bits0 <= count_bits0 + 1;
		count_bits1 <= count_bits0;
		if (count_bits0 == (N-1)) begin
			count_bits0 <= 0;
		end
		
		if (rand) count_ones <= count_ones + 1;	
		if (rand1^rand) count_runs <= count_runs + 1;		
		
		if (count_bits1 == (N-1)) begin
			count_ones <= rand;
			count_runs <= rand1^rand + 1;

		end
	end



endmodule
module Runs(
    input wire clk,
    input wire rst,
    input wire rand,
    output wire pass
    );

	 
parameter N = 20000;

reg [14:0] count_bits0, count_bits1, count_ones, count_runs;
reg rand1;
wire en;
wire p_1, p_2;
assign en = (count_bits1 == (N-1));
assign pass = p_1 & p_2;

decision decision(
	.clk(clk),
	.rst(rst),
	.en(en),
	.count_ones(count_ones),
	.count_runs(count_runs),
	.p_1(p_1),
	.p_2(p_2)
	);

always @(posedge clk)
	if (rst) begin
		count_bits0 <= 15'H7FFF;
		count_bits1 <= 0;
		count_ones <= 0;
		count_runs <= 1;
		rand1 <= 0;
	end
	else begin 
		rand1 <= rand;
		
		count_bits0 <= count_bits0 + 1;
		count_bits1 <= count_bits0;
		if (count_bits0 == (N-1)) begin
			count_bits0 <= 0;
		end
		
		if (rand) count_ones <= count_ones + 1;	
		if (rand1^rand) count_runs <= count_runs + 1;		
		
		if (count_bits1 == (N-1)) begin
			count_ones <= rand;
			count_runs <= rand1^rand + 1;

		end
	end



endmodule