data/full_repos/permissive/194781874/bcd_to_bin.v
1: b'%Warning-WIDTH: data/full_repos/permissive/194781874/bcd_to_bin.v:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                    : ... In instance bcd_to_bin\n        BIN = 12\'b0;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module bcd_to_bin(
    input [19:0] BCD,
    output reg [31:0] BIN
    );
    
    reg [3:0] NUM;
    reg [3:0] i;
    
    always @ (BCD) begin
        BIN = 12'b0;
        for (i = 0; i < 5; i = i + 1) begin
            NUM = {BCD[3+(i*4)], BCD[2+(i*4)], BCD[1+(i*4)], BCD[(i*4)]};
            case (NUM)
                4'b0000: BIN = BIN + (0 * (10 ** i));
                4'b0001: BIN = BIN + (1 * (10 ** i));
                4'b0010: BIN = BIN + (2 * (10 ** i));
                4'b0011: BIN = BIN + (3 * (10 ** i));
                4'b0100: BIN = BIN + (4 * (10 ** i));
                4'b0101: BIN = BIN + (5 * (10 ** i));
                4'b0110: BIN = BIN + (6 * (10 ** i));
                4'b0111: BIN = BIN + (7 * (10 ** i));
                4'b1000: BIN = BIN + (8 * (10 ** i));
                4'b1001: BIN = BIN + (9 * (10 ** i));
            endcase
        end
    end
        
endmodule
module bcd_to_bin(
    input [19:0] BCD,
    output reg [31:0] BIN
    );

    
    reg [3:0] NUM;
    reg [3:0] i;
    
    always @ (BCD) begin
        BIN = 12'b0;
        for (i = 0; i < 5; i = i + 1) begin
            NUM = {BCD[3+(i*4)], BCD[2+(i*4)], BCD[1+(i*4)], BCD[(i*4)]};
            case (NUM)
                4'b0000: BIN = BIN + (0 * (10 ** i));
                4'b0001: BIN = BIN + (1 * (10 ** i));
                4'b0010: BIN = BIN + (2 * (10 ** i));
                4'b0011: BIN = BIN + (3 * (10 ** i));
                4'b0100: BIN = BIN + (4 * (10 ** i));
                4'b0101: BIN = BIN + (5 * (10 ** i));
                4'b0110: BIN = BIN + (6 * (10 ** i));
                4'b0111: BIN = BIN + (7 * (10 ** i));
                4'b1000: BIN = BIN + (8 * (10 ** i));
                4'b1001: BIN = BIN + (9 * (10 ** i));
            endcase
        end
    end
        
endmodule