data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ALU.v
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ALU.v\n%Error: Exiting due to 4 error(s)\n'
module ALU(
   input [15:0] aInput,
   input [15:0] bInput,
   input [2:0] opCode,
   input sub,
   input aInvert,
   input bInvert,
	input ShiftImm,
   output [15:0] res,
	output [4:0] CLFZN
   );
	
	reg [15:0] A;
	reg [15:0] B;
	
	reg [15:0] aluResult;
	
	assign res = aluResult;


	

	assign CLFZN[0] = ($signed(A) < $signed(B));
	assign CLFZN[1] = (A == B);
	assign CLFZN[2] = (A[15] == B[15]) && (aluResult[15] != A[15]);
	assign CLFZN[3] = (A < B);
	assign CLFZN[4] = (A[15] && B[15]) || (!aluResult[15] && ( (!A[15] && B[15]) || (A[15] && !B[15])));
	
	
	always @(*) begin
		if (aInvert) A = ~aInput;
		else A = aInput;
		
		if (bInvert) B = ~bInput;
		else B = bInput;
	end
	
	always@(*) begin
		case (opCode) 
			3'b000:	
				begin
					aluResult = A + B + sub;
				end
			3'b001:			
				begin
					aluResult = A & B;
				end
			3'b010:
				begin
					aluResult = A | B;
				end
			3'b011:
				begin
					aluResult = A ^ B;
				end
			3'b101:								
				begin
					if (!ShiftImm && B>=15)
						aluResult = A <<< 15;
					else
						case(B[3:0])
							0: aluResult = A <<< 0;
							1: aluResult = A <<< 1;
							2: aluResult = A <<< 2;
							3: aluResult = A <<< 3;
							4: aluResult = A <<< 4;
							5: aluResult = A <<< 5;
							6: aluResult = A <<< 6;
							7: aluResult = A <<< 7;
							8: aluResult = A <<< 8;
							9: aluResult = A <<< 9;
							10: aluResult = A <<< 10;
							11: aluResult = A <<< 11;
							12: aluResult = A <<< 12;
							13: aluResult = A <<< 13;
							14: aluResult = A <<< 14;
							15: aluResult = A <<< 15;
							default: aluResult = A <<< 0;
						endcase
				end
			3'b110:								
				begin
					if (!ShiftImm && B>=15)
						aluResult = A >>> 15;
					else
						case(B[3:0])
							0: aluResult = A >>> 0;
							1: aluResult = A >>> 1;
							2: aluResult = A >>> 2;
							3: aluResult = A >>> 3;
							4: aluResult = A >>> 4;
							5: aluResult = A >>> 5;
							6: aluResult = A >>> 6;
							7: aluResult = A >>> 7;
							8: aluResult = A >>> 8;
							9: aluResult = A >>> 9;
							10: aluResult = A >>> 10;
							11: aluResult = A >>> 11;
							12: aluResult = A >>> 12;
							13: aluResult = A >>> 13;
							14: aluResult = A >>> 14;
							15: aluResult = A >>> 15;
							default: aluResult = A >>> 0;
						endcase
				end
			3'b111:
				begin
					if (!ShiftImm && B>=15)
						aluResult = A >> 15;
					else
						case(B[3:0])
							0: aluResult = A >> 0;
							1: aluResult = A >> 1;
							2: aluResult = A >> 2;
							3: aluResult = A >> 3;
							4: aluResult = A >> 4;
							5: aluResult = A >> 5;
							6: aluResult = A >> 6;
							7: aluResult = A >> 7;
							8: aluResult = A >> 8;
							9: aluResult = A >> 9;
							10: aluResult = A>> 10;
							11: aluResult = A >> 11;
							12: aluResult = A >> 12;
							13: aluResult = A >> 13;
							14: aluResult = A >> 14;
							15: aluResult = A >> 15;
							default: aluResult = A >> 0;
						endcase
				end
			default: 
				begin
					aluResult = 0;
				end
		endcase
	end
	
endmodule
module ALU(
   input [15:0] aInput,
   input [15:0] bInput,
   input [2:0] opCode,
   input sub,
   input aInvert,
   input bInvert,
	input ShiftImm,
   output [15:0] res,
	output [4:0] CLFZN
   );

	
	reg [15:0] A;
	reg [15:0] B;
	
	reg [15:0] aluResult;
	
	assign res = aluResult;


	

	assign CLFZN[0] = ($signed(A) < $signed(B));
	assign CLFZN[1] = (A == B);
	assign CLFZN[2] = (A[15] == B[15]) && (aluResult[15] != A[15]);
	assign CLFZN[3] = (A < B);
	assign CLFZN[4] = (A[15] && B[15]) || (!aluResult[15] && ( (!A[15] && B[15]) || (A[15] && !B[15])));
	
	
	always @(*) begin
		if (aInvert) A = ~aInput;
		else A = aInput;
		
		if (bInvert) B = ~bInput;
		else B = bInput;
	end
	
	always@(*) begin
		case (opCode) 
			3'b000:	
				begin
					aluResult = A + B + sub;
				end
			3'b001:			
				begin
					aluResult = A & B;
				end
			3'b010:
				begin
					aluResult = A | B;
				end
			3'b011:
				begin
					aluResult = A ^ B;
				end
			3'b101:								
				begin
					if (!ShiftImm && B>=15)
						aluResult = A <<< 15;
					else
						case(B[3:0])
							0: aluResult = A <<< 0;
							1: aluResult = A <<< 1;
							2: aluResult = A <<< 2;
							3: aluResult = A <<< 3;
							4: aluResult = A <<< 4;
							5: aluResult = A <<< 5;
							6: aluResult = A <<< 6;
							7: aluResult = A <<< 7;
							8: aluResult = A <<< 8;
							9: aluResult = A <<< 9;
							10: aluResult = A <<< 10;
							11: aluResult = A <<< 11;
							12: aluResult = A <<< 12;
							13: aluResult = A <<< 13;
							14: aluResult = A <<< 14;
							15: aluResult = A <<< 15;
							default: aluResult = A <<< 0;
						endcase
				end
			3'b110:								
				begin
					if (!ShiftImm && B>=15)
						aluResult = A >>> 15;
					else
						case(B[3:0])
							0: aluResult = A >>> 0;
							1: aluResult = A >>> 1;
							2: aluResult = A >>> 2;
							3: aluResult = A >>> 3;
							4: aluResult = A >>> 4;
							5: aluResult = A >>> 5;
							6: aluResult = A >>> 6;
							7: aluResult = A >>> 7;
							8: aluResult = A >>> 8;
							9: aluResult = A >>> 9;
							10: aluResult = A >>> 10;
							11: aluResult = A >>> 11;
							12: aluResult = A >>> 12;
							13: aluResult = A >>> 13;
							14: aluResult = A >>> 14;
							15: aluResult = A >>> 15;
							default: aluResult = A >>> 0;
						endcase
				end
			3'b111:
				begin
					if (!ShiftImm && B>=15)
						aluResult = A >> 15;
					else
						case(B[3:0])
							0: aluResult = A >> 0;
							1: aluResult = A >> 1;
							2: aluResult = A >> 2;
							3: aluResult = A >> 3;
							4: aluResult = A >> 4;
							5: aluResult = A >> 5;
							6: aluResult = A >> 6;
							7: aluResult = A >> 7;
							8: aluResult = A >> 8;
							9: aluResult = A >> 9;
							10: aluResult = A>> 10;
							11: aluResult = A >> 11;
							12: aluResult = A >> 12;
							13: aluResult = A >> 13;
							14: aluResult = A >> 14;
							15: aluResult = A >> 15;
							default: aluResult = A >> 0;
						endcase
				end
			default: 
				begin
					aluResult = 0;
				end
		endcase
	end
	
endmodule