data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/prgm_cntr.v
1: b'%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/prgm_cntr.v:43: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'k\' generates 8 bits.\n                                                                                                                                : ... In instance prgm_cntr\n      3\'b001:  pc_in = k;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/prgm_cntr.v:44: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'stack1\' generates 8 bits.\n                                                                                                                                : ... In instance prgm_cntr\n      3\'b010:  pc_in = stack1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/prgm_cntr.v:45: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'stack2\' generates 8 bits.\n                                                                                                                                : ... In instance prgm_cntr\n      3\'b011:  pc_in = stack2;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/prgm_cntr.v:46: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'fin\' generates 8 bits.\n                                                                                                                                : ... In instance prgm_cntr\n      3\'b100:  pc_in = fin;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/prgm_cntr.v:102: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                                                                                 : ... In instance prgm_cntr\n   stack1 <= 11\'b00000000000;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/prgm_cntr.v:105: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'pc_in\' generates 11 bits.\n                                                                                                                                 : ... In instance prgm_cntr\n    stack1 <= pc_in;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/prgm_cntr.v:113: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                                                                                 : ... In instance prgm_cntr\n   stack2 <= 11\'b00000000000;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/prgm_cntr.v:116: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'pc_in\' generates 11 bits.\n                                                                                                                                 : ... In instance prgm_cntr\n     stack2 <= pc_in;\n            ^~\n%Error: Exiting due to 8 warning(s)\n'
module prgm_cntr ( clk4, resetn, inst, k, fin, pc );

input clk4, resetn;

input [11:0] inst;

input [7:0] k;

input [7:0] fin;

output [10:0] pc;
reg [10:0] pc;



 
`define PC_SELECT_PCPLUS1       3'b000
`define PC_SELECT_K             3'b001
`define PC_SELECT_STACK1        3'b010
`define PC_SELECT_STACK2        3'b011
`define PC_SELECT_FOUT          3'b100
`define PC_SELECT_RESET_VECTOR  3'b101
`define RESET_VECTOR            11'b11111111111



reg[10:0] pc_in;
reg [2:0] pc_sel;

reg [1:0] stacklevel;
reg [1:0] stacklevel_in;

reg [7:0] stack1, stack2;

reg [10:0] pcplus1;

wire reset = ~resetn;


always @(pc_sel or pcplus1 or k or stack1 or stack2 or fin or pc) begin
   case (pc_sel)
      3'b000:  pc_in = pcplus1;
      3'b001:  pc_in = k;
      3'b010:  pc_in = stack1;
      3'b011:  pc_in = stack2;
      3'b100:  pc_in = fin;

      3'b101:  pc_in = `RESET_VECTOR;
      

	     default:
            pc_in = pc;


   endcase
end

always@(posedge clk4 or posedge reset)
begin
if(reset == 1'b1)
  begin
    stacklevel <= 2'b00;
    pcplus1 <= 11'b00000000000;
	pc <= 11'b00000000000;
  end
else
  begin
    stacklevel <= stacklevel_in;
    pcplus1 <= pc_in + 1'b1;
	pc <= pc_in;
  end
end




always @(inst or stacklevel or reset) begin
   if (reset == 1'b1) begin
      pc_sel = `PC_SELECT_RESET_VECTOR;
   end
   else begin
      casex ({inst, stacklevel})
         14'b101?_????_????_??: pc_sel = `PC_SELECT_K;
         14'b1001_????_????_??: pc_sel = `PC_SELECT_K;
         14'b1000_????_????_00: pc_sel = `PC_SELECT_STACK1;
         14'b1000_????_????_01: pc_sel = `PC_SELECT_STACK1;
         14'b1000_????_????_10: pc_sel = `PC_SELECT_STACK2;
         14'b1000_????_????_11: pc_sel = `PC_SELECT_STACK2;
         14'b0010_0010_0010_??: pc_sel = `PC_SELECT_FOUT;
		 14'b0001_1110_0010_??: pc_sel = `PC_SELECT_FOUT;
         default:
            pc_sel = `PC_SELECT_PCPLUS1;
      endcase
   end
end



always@(posedge clk4 or posedge reset)
begin  
   if (reset)
   stack1 <= 11'b00000000000;
   else if (inst[11:8] == 4'b1001 && stacklevel == 2'b00)
     begin
	   stack1 <= pc_in;
       $display ("Write to STACK1: %0h", pc);
	 end
end

always@(posedge clk4 or posedge reset)
begin  
   if (reset)
   stack2 <= 11'b00000000000;
   else if (inst[11:8] == 4'b1001 && stacklevel == 2'b01)
      begin
	    stack2 <= pc_in;
       $display ("Write to STACK2: %0h", pc);
	  end
end









always @(inst or stacklevel or reset) begin




      casex ({inst, stacklevel})

         14'b1001_????_????_00: stacklevel_in = 2'b01;
         14'b1001_????_????_01: stacklevel_in = 2'b10;
         14'b1001_????_????_10: stacklevel_in = 2'b10;
         14'b1001_????_????_11: stacklevel_in = 2'b00;


         14'b1000_????_????_00: stacklevel_in = 2'b00;
         14'b1000_????_????_01: stacklevel_in = 2'b00;
         14'b1000_????_????_10: stacklevel_in = 2'b01;
         14'b1000_????_????_11: stacklevel_in = 2'b10;
         default:
         stacklevel_in = stacklevel;
      endcase

end

endmodule
module prgm_cntr ( clk4, resetn, inst, k, fin, pc );


input clk4, resetn;

input [11:0] inst;

input [7:0] k;

input [7:0] fin;

output [10:0] pc;
reg [10:0] pc;



 
`define PC_SELECT_PCPLUS1       3'b000
`define PC_SELECT_K             3'b001
`define PC_SELECT_STACK1        3'b010
`define PC_SELECT_STACK2        3'b011
`define PC_SELECT_FOUT          3'b100
`define PC_SELECT_RESET_VECTOR  3'b101
`define RESET_VECTOR            11'b11111111111



reg[10:0] pc_in;
reg [2:0] pc_sel;

reg [1:0] stacklevel;
reg [1:0] stacklevel_in;

reg [7:0] stack1, stack2;

reg [10:0] pcplus1;

wire reset = ~resetn;


always @(pc_sel or pcplus1 or k or stack1 or stack2 or fin or pc) begin
   case (pc_sel)
      3'b000:  pc_in = pcplus1;
      3'b001:  pc_in = k;
      3'b010:  pc_in = stack1;
      3'b011:  pc_in = stack2;
      3'b100:  pc_in = fin;

      3'b101:  pc_in = `RESET_VECTOR;
      

	     default:
            pc_in = pc;


   endcase
end

always@(posedge clk4 or posedge reset)
begin
if(reset == 1'b1)
  begin
    stacklevel <= 2'b00;
    pcplus1 <= 11'b00000000000;
	pc <= 11'b00000000000;
  end
else
  begin
    stacklevel <= stacklevel_in;
    pcplus1 <= pc_in + 1'b1;
	pc <= pc_in;
  end
end




always @(inst or stacklevel or reset) begin
   if (reset == 1'b1) begin
      pc_sel = `PC_SELECT_RESET_VECTOR;
   end
   else begin
      casex ({inst, stacklevel})
         14'b101?_????_????_??: pc_sel = `PC_SELECT_K;
         14'b1001_????_????_??: pc_sel = `PC_SELECT_K;
         14'b1000_????_????_00: pc_sel = `PC_SELECT_STACK1;
         14'b1000_????_????_01: pc_sel = `PC_SELECT_STACK1;
         14'b1000_????_????_10: pc_sel = `PC_SELECT_STACK2;
         14'b1000_????_????_11: pc_sel = `PC_SELECT_STACK2;
         14'b0010_0010_0010_??: pc_sel = `PC_SELECT_FOUT;
		 14'b0001_1110_0010_??: pc_sel = `PC_SELECT_FOUT;
         default:
            pc_sel = `PC_SELECT_PCPLUS1;
      endcase
   end
end



always@(posedge clk4 or posedge reset)
begin  
   if (reset)
   stack1 <= 11'b00000000000;
   else if (inst[11:8] == 4'b1001 && stacklevel == 2'b00)
     begin
	   stack1 <= pc_in;
       $display ("Write to STACK1: %0h", pc);
	 end
end

always@(posedge clk4 or posedge reset)
begin  
   if (reset)
   stack2 <= 11'b00000000000;
   else if (inst[11:8] == 4'b1001 && stacklevel == 2'b01)
      begin
	    stack2 <= pc_in;
       $display ("Write to STACK2: %0h", pc);
	  end
end









always @(inst or stacklevel or reset) begin




      casex ({inst, stacklevel})

         14'b1001_????_????_00: stacklevel_in = 2'b01;
         14'b1001_????_????_01: stacklevel_in = 2'b10;
         14'b1001_????_????_10: stacklevel_in = 2'b10;
         14'b1001_????_????_11: stacklevel_in = 2'b00;


         14'b1000_????_????_00: stacklevel_in = 2'b00;
         14'b1000_????_????_01: stacklevel_in = 2'b00;
         14'b1000_????_????_10: stacklevel_in = 2'b01;
         14'b1000_????_????_11: stacklevel_in = 2'b10;
         default:
         stacklevel_in = stacklevel;
      endcase

end

endmodule