data/full_repos/permissive/157005262/verilog/spoilers/traffic.v
data/verilator_xmls/a7f3cdd9-e7bf-4eb6-b82c-42952190f916.xml
module traffic(input wire  clk,
               input wire  go,
               output wire red,
               output wire yellow,
               output wire green);

  reg [1:0] state = 0;
  reg [1:0] counter;
  assign red = (state == 0 || state == 1);
  assign yellow = (state == 1 || state == 2);
  assign green = (state == 3);

  always @(posedge clk) begin
    case (state)
      0: begin
        if (go) begin
          state <= 1;
          counter <= 2;
        end
      end
      1: begin
        if (counter == 0)
          state <= 3;
        else
          counter <= counter - 1;
      end
      2: begin
        if (counter == 0)
          state <= 0;
        else
          counter <= counter - 1;
      end
      3: if (!go) begin
        state <= 2;
        counter <= 2;
      end
    endcase
  end
endmodule
module traffic(input wire  clk,
               input wire  go,
               output wire red,
               output wire yellow,
               output wire green);


  reg [1:0] state = 0;
  reg [1:0] counter;
  assign red = (state == 0 || state == 1);
  assign yellow = (state == 1 || state == 2);
  assign green = (state == 3);

  always @(posedge clk) begin
    case (state)
      0: begin
        if (go) begin
          state <= 1;
          counter <= 2;
        end
      end
      1: begin
        if (counter == 0)
          state <= 3;
        else
          counter <= counter - 1;
      end
      2: begin
        if (counter == 0)
          state <= 0;
        else
          counter <= counter - 1;
      end
      3: if (!go) begin
        state <= 2;
        counter <= 2;
      end
    endcase
  end
endmodule