data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux2to1_design.v
 line:37: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux2to1_design.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux2to1_design.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux2to1_design.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux2to1_design.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Error: data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux2to1_design.v:21: Cannot find file containing module: \'mux2to1_design\'\n    mux2to1_design utt\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches,data/full_repos/permissive/212763527/mux2to1_design\n             data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches,data/full_repos/permissive/212763527/mux2to1_design.v\n             data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches,data/full_repos/permissive/212763527/mux2to1_design.sv\n             mux2to1_design\n             mux2to1_design.v\n             mux2to1_design.sv\n             obj_dir/mux2to1_design\n             obj_dir/mux2to1_design.v\n             obj_dir/mux2to1_design.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_module_name;



    reg w0;
    reg w1;
    reg s;


    wire f;

    initial begin
        s = 1'b0;
        w0 = 1'b0;
        w1 = 1'b1;
    end


    mux2to1_design utt
    (
        .w0(w0),
        .w1(w1),
        .s(s),
        .f(f)
    );

    initial begin
        #5
        w0 = 1'b1;
        #5
        s = 1'b1;
        #5
        w1 = 1'b1;
        #5
        $finish;
    end

endmodule
module tb_module_name;




    reg w0;
    reg w1;
    reg s;


    wire f;

    initial begin
        s = 1'b0;
        w0 = 1'b0;
        w1 = 1'b1;
    end


    mux2to1_design utt
    (
        .w0(w0),
        .w1(w1),
        .s(s),
        .f(f)
    );

    initial begin
        #5
        w0 = 1'b1;
        #5
        s = 1'b1;
        #5
        w1 = 1'b1;
        #5
        $finish;
    end

endmodule