data/full_repos/permissive/196257568/io_verilog/mod.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/196257568/io_verilog/mod.v:14: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'div\' generates 5 bits.\n                                                                        : ... In instance mod\n            check <= check - div;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/196257568/io_verilog/mod.v:13: Operator GTE expects 8 bits on the RHS, but RHS\'s VARREF \'div\' generates 5 bits.\n                                                                        : ... In instance mod\n        else if(check >= div)\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/196257568/io_verilog/mod.v:15: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'div\' generates 5 bits.\n                                                                        : ... In instance mod\n        if(check < div)\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/196257568/io_verilog/mod.v:17: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'div\' generates 5 bits.\n                                                                        : ... In instance mod\n        update <= (check < div) ? 1 : 0;\n                         ^\n%Error: Exiting due to 4 warning(s)\n'
module mod(clock, div, inputval, outputval);
    input clock;
    input[4:0] div;
    input[7:0] inputval;
    output reg[7:0] outputval;
    reg[7:0] check, origval;
    reg update = 1;

    always@(posedge clock) begin
        if(update) begin
            check <= inputval + 1;
            origval <= inputval; end
        else if(check >= div)
            check <= check - div;
        if(check < div)
            outputval <= origval - check;
        update <= (check < div) ? 1 : 0;
    end
endmodule
module mod(clock, div, inputval, outputval);

    input clock;
    input[4:0] div;
    input[7:0] inputval;
    output reg[7:0] outputval;
    reg[7:0] check, origval;
    reg update = 1;

    always@(posedge clock) begin
        if(update) begin
            check <= inputval + 1;
            origval <= inputval; end
        else if(check >= div)
            check <= check - div;
        if(check < div)
            outputval <= origval - check;
        update <= (check < div) ? 1 : 0;
    end
endmodule