data/full_repos/permissive/136238697/verilogboxes/multiplier.v
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data/verilator_xmls/9d37bfd9-5db3-42d5-bff3-3d5a5051341e.xml
module multiplier
  #( parameter WIDTH = 32,
     parameter LATENCY = 4 
   )
   (
     input clock,
     input reset,
     input [WIDTH-1:0] in1,
     input [WIDTH-1:0] in2,
     output reg [WIDTH-1:0] out
   );
  integer i;
  reg [WIDTH-1:0] sr[LATENCY];

  always @(posedge clock) begin
    begin
      sr[0] <= in1 * in2;
      for(i=1; i<LATENCY; i=i+1) begin
        sr[i] <= sr[i-1];
      end
    end
  end

  always @(*) begin
    out = sr[LATENCY-1];
  end

endmodule
module multiplier
  #( parameter WIDTH = 32,
     parameter LATENCY = 4 
   )
   (
     input clock,
     input reset,
     input [WIDTH-1:0] in1,
     input [WIDTH-1:0] in2,
     output reg [WIDTH-1:0] out
   );

  integer i;
  reg [WIDTH-1:0] sr[LATENCY];

  always @(posedge clock) begin
    begin
      sr[0] <= in1 * in2;
      for(i=1; i<LATENCY; i=i+1) begin
        sr[i] <= sr[i-1];
      end
    end
  end

  always @(*) begin
    out = sr[LATENCY-1];
  end

endmodule