data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_testpat_xgmii.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_testpat_xgmii.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_testpat_xgmii.v:43: Cannot find file containing module: \'testpat_xgmii_rx\'\ntestpat_xgmii_rx testpat_xgmii_rx_0(.CLK(clk), .RESET(reset), .STARTBTN(1), .PKTLEN(pktlen),\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new,data/full_repos/permissive/156650005/testpat_xgmii_rx\n             data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new,data/full_repos/permissive/156650005/testpat_xgmii_rx.v\n             data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new,data/full_repos/permissive/156650005/testpat_xgmii_rx.sv\n             testpat_xgmii_rx\n             testpat_xgmii_rx.v\n             testpat_xgmii_rx.sv\n             obj_dir/testpat_xgmii_rx\n             obj_dir/testpat_xgmii_rx.v\n             obj_dir/testpat_xgmii_rx.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_testpat_xgmii();

reg clk;
reg reset;

wire [15:0] pktlen = 64;
wire [15:0] gaplen = 12;
wire [63:0] out_rxd;
wire [7:0] out_rxc;

initial begin
    clk = 0;
    forever clk = #1 !clk;
end

initial begin
    reset = 1;
    #10 reset = 0;
end

testpat_xgmii_rx testpat_xgmii_rx_0(.CLK(clk), .RESET(reset), .STARTBTN(1), .PKTLEN(pktlen),
    .GAPLEN(gaplen), .IN_RXD(0), .IN_RXC(0), .OUT_RXD(out_rxd), .OUT_RXC(out_rxc));

endmodule
module sim_testpat_xgmii();


reg clk;
reg reset;

wire [15:0] pktlen = 64;
wire [15:0] gaplen = 12;
wire [63:0] out_rxd;
wire [7:0] out_rxc;

initial begin
    clk = 0;
    forever clk = #1 !clk;
end

initial begin
    reset = 1;
    #10 reset = 0;
end

testpat_xgmii_rx testpat_xgmii_rx_0(.CLK(clk), .RESET(reset), .STARTBTN(1), .PKTLEN(pktlen),
    .GAPLEN(gaplen), .IN_RXD(0), .IN_RXC(0), .OUT_RXD(out_rxd), .OUT_RXC(out_rxc));

endmodule