data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv
 line:11: before: "["
1: b'%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:32: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:34: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:36: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:38: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:40: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:42: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:44: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:46: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:48: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Error: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:54: Unsupported or unknown PLI call: $monitor\n        $monitor("a=%b b=%b c=%b d=%b sel=%b data[0]=%b data[1]=%b data[2]=%b", \n        ^~~~~~~~\n%Error: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:55: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                  a,   b,   c,   d,   sel,   data[0],   data[1],   data[2],   );\n                                                                              ^\n%Error: data/full_repos/permissive/147690299/lab/14_comb_mux_onehot/tb/testbench.sv:58: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;   \n        ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

    reg  [1:0] a;
    reg  [1:0] b;
    reg  [1:0] c;
    reg  [1:0] d;
    reg  [3:0] sel;
    wire [2:0][1:0] data;
 

    lab_top dut
    (
        .idata0 ( a       ),
        .idata1 ( b       ),
        .idata2 ( c       ),
        .idata3 ( c       ),
        .sel    ( sel     ),
        .odata0 ( data[0] ),
        .odata1 ( data[1] ),
        .odata2 ( data[2] ) 
    );

    initial 
        begin
            a = 2'b00;
            b = 2'b01;
            c = 2'b10;
            d = 2'b11;
            #5;
            sel = 4'b0000;
            #10;
            sel = 4'b0001;
            #10
            sel = 4'b0010;
            #10;
            sel = 4'b0100;
            #10;
            sel = 4'b1000;
            #10;
            sel = 4'b0011;
            #10;
            sel = 4'b1010;
            #10;
            sel = 4'b1111;
            #10;
            $finish();
        end


    initial 
        $monitor("a=%b b=%b c=%b d=%b sel=%b data[0]=%b data[1]=%b data[2]=%b", 
                  a,   b,   c,   d,   sel,   data[0],   data[1],   data[2],   );

    initial 
        $dumpvars;
endmodule
module testbench;


    reg  [1:0] a;
    reg  [1:0] b;
    reg  [1:0] c;
    reg  [1:0] d;
    reg  [3:0] sel;
    wire [2:0][1:0] data;
 

    lab_top dut
    (
        .idata0 ( a       ),
        .idata1 ( b       ),
        .idata2 ( c       ),
        .idata3 ( c       ),
        .sel    ( sel     ),
        .odata0 ( data[0] ),
        .odata1 ( data[1] ),
        .odata2 ( data[2] ) 
    );

    initial 
        begin
            a = 2'b00;
            b = 2'b01;
            c = 2'b10;
            d = 2'b11;
            #5;
            sel = 4'b0000;
            #10;
            sel = 4'b0001;
            #10
            sel = 4'b0010;
            #10;
            sel = 4'b0100;
            #10;
            sel = 4'b1000;
            #10;
            sel = 4'b0011;
            #10;
            sel = 4'b1010;
            #10;
            sel = 4'b1111;
            #10;
            $finish();
        end


    initial 
        $monitor("a=%b b=%b c=%b d=%b sel=%b data[0]=%b data[1]=%b data[2]=%b", 
                  a,   b,   c,   d,   sel,   data[0],   data[1],   data[2],   );

    initial 
        $dumpvars;
endmodule