data/full_repos/permissive/197102055/src/sdramc/mem_ctrl.v
1: b"%Error: data/full_repos/permissive/197102055/src/sdramc/mem_ctrl.v:161: Cannot find file containing module: 'sdram_init'\nsdram_init  sdram_init_x(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197102055/src/sdramc,data/full_repos/permissive/197102055/sdram_init\n             data/full_repos/permissive/197102055/src/sdramc,data/full_repos/permissive/197102055/sdram_init.v\n             data/full_repos/permissive/197102055/src/sdramc,data/full_repos/permissive/197102055/sdram_init.sv\n             sdram_init\n             sdram_init.v\n             sdram_init.sv\n             obj_dir/sdram_init\n             obj_dir/sdram_init.v\n             obj_dir/sdram_init.sv\n%Error: data/full_repos/permissive/197102055/src/sdramc/mem_ctrl.v:167: Cannot find file containing module: 'sdram_ctl'\nsdram_ctl sdram_ctl(\n^~~~~~~~~\n%Error: data/full_repos/permissive/197102055/src/sdramc/mem_ctrl.v:192: Cannot find file containing module: 'sdram_io'\nsdram_io sdram_io(\n^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module mem_ctrl (

	input   sdram_clk,
	input   sdram_rst_,


    	input	       	wr_req,
    	output         	wr_valid,
    	input	[31:0]  wr_addr,
    	input  	[15:0]  wr_data,


	input		rd_req,
	output		rd_valid,
	input	[31:0]	rd_addr,
	output		rd_rdy,
	output	[15:0]	rd_data,

	output		sd_init_done,
    

	output  [12:0]  sdram_addr,
	output  [1:0]   sdram_ba, 
	inout   [15:0]  sdram_dq,
	output          sdram_ras_,
	output          sdram_cas_,
	output          sdram_we_,
	output  	 		 sdram_dqml,
	output			 sdram_dqmh,
	output          sdram_cke,
	output          sdram_cs_
);




wire	[15:0]	sdram_dqo;
wire	[15:0]	sdram_dqi;
wire	[15:0]	sdram_dq_oe;

wire            STOP_CLK;
wire            PAA;
wire            SET_MODE;
wire    [2:0]   BLK_SIZE;


wire            IS_SEQ;

wire            MODULE_BK_NUM;
wire    [1:0]   ROW_SIZE;
wire    [1:0]   BIT_SIZE;
wire            BK_SIZE;
wire    [2:0]   COL_SIZE;

wire    [1:0]   tRCD;
wire    [1:0]   tCAS;
wire    [1:0]   tRP;
wire    [2:0]   tRAS;
wire    [11:0]  tREF;
wire    [3:0]   tRC;

wire	[31:0]	sys_addr;
wire		sys_rd;
wire		sys_wr;
wire	[15:0]	sys_wdata;
wire	[15:0]	sys_rdata;
wire		sys_rd_rdy;
wire		sys_burst_rdy;

wire	[12:0]  isdram_addr;
wire	[1:0]   isdram_ba; 
wire	[15:0]  isdram_dqi;
wire	[15:0]  isdram_dqo;
wire          isdram_dq_oe;
wire	        isdram_ras_;
wire	        isdram_cas_;
wire	        isdram_we_;
wire			  isdram_dqm;
wire	        isdram_cke;
wire	        isdram_cs_;

assign sd_init_done = PAA;




assign sys_addr = wr_req ? wr_addr : rd_addr;
assign sys_rd = rd_req;
assign sys_wr = wr_req;
assign sys_wdata = wr_data;
assign rd_data = sys_rdata;
assign wr_valid = wr_req & sys_burst_rdy;
assign rd_valid = rd_req & sys_burst_rdy;
assign rd_rdy = sys_rd_rdy;




assign sdram_dq[0]     = sdram_dq_oe[0] ? sdram_dqo[0] : 1'Hz;
assign sdram_dq[1]     = sdram_dq_oe[1] ? sdram_dqo[1] : 1'Hz;
assign sdram_dq[2]     = sdram_dq_oe[2] ? sdram_dqo[2] : 1'Hz;
assign sdram_dq[3]     = sdram_dq_oe[3] ? sdram_dqo[3] : 1'Hz;
assign sdram_dq[4]     = sdram_dq_oe[4] ? sdram_dqo[4] : 1'Hz;
assign sdram_dq[5]     = sdram_dq_oe[5] ? sdram_dqo[5] : 1'Hz;
assign sdram_dq[6]     = sdram_dq_oe[6] ? sdram_dqo[6] : 1'Hz;
assign sdram_dq[7]     = sdram_dq_oe[7] ? sdram_dqo[7] : 1'Hz;
assign sdram_dq[8]     = sdram_dq_oe[8] ? sdram_dqo[8] : 1'Hz;
assign sdram_dq[9]     = sdram_dq_oe[9] ? sdram_dqo[9] : 1'Hz;
assign sdram_dq[10]     = sdram_dq_oe[10] ? sdram_dqo[10] : 1'Hz;
assign sdram_dq[11]     = sdram_dq_oe[11] ? sdram_dqo[11] : 1'Hz;
assign sdram_dq[12]     = sdram_dq_oe[12] ? sdram_dqo[12] : 1'Hz;
assign sdram_dq[13]     = sdram_dq_oe[13] ? sdram_dqo[13] : 1'Hz;
assign sdram_dq[14]     = sdram_dq_oe[14] ? sdram_dqo[14] : 1'Hz;
assign sdram_dq[15]     = sdram_dq_oe[15] ? sdram_dqo[15] : 1'Hz;
assign sdram_dqi = sdram_dq;




assign STOP_CLK         = 1'b0;
assign BLK_SIZE         = 3'b000;
assign IS_SEQ           = 1'b0;
assign MODULE_BK_NUM    = 1'b1;     
assign ROW_SIZE         = 2'b10;
assign BIT_SIZE         = 2'b10;
assign BK_SIZE          = 1'b1;
assign COL_SIZE         = 3'b001;
assign tRCD             = 2'b10;
assign tCAS             = 2'b11;
assign tRP              = 2'b11;
assign tRAS             = 3'b110;
assign tREF             = 12'd257;
assign tRC              = 4'b1000;




sdram_init  sdram_init_x(
    .sdram_clk(sdram_clk),    .sdram_rst_(sdram_rst_),

    .PAA(PAA),          .SET_MODE(SET_MODE)
);

sdram_ctl sdram_ctl(
    .CLK(sdram_clk),  .RST_(sdram_rst_),
                                

    .STOP_CLK(STOP_CLK), .PAA(PAA), .SET_MODE(SET_MODE), .BLK_SIZE(BLK_SIZE), .IS_SEQ(IS_SEQ), 
    .MODULE_BK_NUM(MODULE_BK_NUM), .ROW_SIZE(ROW_SIZE), .COL_SIZE(COL_SIZE[1:0]), .BK_SIZE(BK_SIZE), .BIT_SIZE(BIT_SIZE), 
    .tRCD(tRCD), .tCAS(tCAS), .tRAS(tRAS), .tRP(tRP),
    .tREF(tREF), .tRC(tRC),
    

    .ADDR(sys_addr), .RD(sys_rd), .WR(sys_wr), .DAT_I(sys_wdata), .DAT_O(sys_rdata),
    .RD_DAT_RDY(sys_rd_rdy), .BURST_RDY(sys_burst_rdy), .RW(),
    .CPU_GNT_(1'b0), .MUX_EN(),
    

    .CKE(isdram_cke), .CS_(isdram_cs_),
    .RAS_(isdram_ras_), .CAS_(isdram_cas_), .WE_(isdram_we_), .DQM(isdram_dqm),
    .BA(isdram_ba),  .DIMM_ADDR(isdram_addr),    
    .DQ_I(isdram_dqi), .DQ_O(isdram_dqo), .DQ_OE(isdram_dq_oe)




);

sdram_io sdram_io(

    .sdram_clk(sdram_clk),


    .sdram_addr(isdram_addr), .sdram_ba(isdram_ba), .sdram_dqo(isdram_dqo),
    .sdram_dqi(isdram_dqi), .sdram_dq_oe(isdram_dq_oe), .sdram_ras_(isdram_ras_),
    .sdram_cas_(isdram_cas_), .sdram_we_(isdram_we_), .sdram_dqm(isdram_dqm), 
	 .sdram_cke(isdram_cke), .sdram_cs_(isdram_cs_),


    .pad_addr(sdram_addr), .pad_ba(sdram_ba), .pad_dqo(sdram_dqo), 
	 .pad_dqi(sdram_dqi), .pad_dq_oe(sdram_dq_oe), .pad_ras_(sdram_ras_), 
	 .pad_cas_(sdram_cas_), .pad_we_(sdram_we_), .pad_dqml(sdram_dqml), .pad_dqmh(sdram_dqmh),
    .pad_cke(sdram_cke), .pad_cs_(sdram_cs_)
);

endmodule
module mem_ctrl (

	input   sdram_clk,
	input   sdram_rst_,


    	input	       	wr_req,
    	output         	wr_valid,
    	input	[31:0]  wr_addr,
    	input  	[15:0]  wr_data,


	input		rd_req,
	output		rd_valid,
	input	[31:0]	rd_addr,
	output		rd_rdy,
	output	[15:0]	rd_data,

	output		sd_init_done,
    

	output  [12:0]  sdram_addr,
	output  [1:0]   sdram_ba, 
	inout   [15:0]  sdram_dq,
	output          sdram_ras_,
	output          sdram_cas_,
	output          sdram_we_,
	output  	 		 sdram_dqml,
	output			 sdram_dqmh,
	output          sdram_cke,
	output          sdram_cs_
);





wire	[15:0]	sdram_dqo;
wire	[15:0]	sdram_dqi;
wire	[15:0]	sdram_dq_oe;

wire            STOP_CLK;
wire            PAA;
wire            SET_MODE;
wire    [2:0]   BLK_SIZE;


wire            IS_SEQ;

wire            MODULE_BK_NUM;
wire    [1:0]   ROW_SIZE;
wire    [1:0]   BIT_SIZE;
wire            BK_SIZE;
wire    [2:0]   COL_SIZE;

wire    [1:0]   tRCD;
wire    [1:0]   tCAS;
wire    [1:0]   tRP;
wire    [2:0]   tRAS;
wire    [11:0]  tREF;
wire    [3:0]   tRC;

wire	[31:0]	sys_addr;
wire		sys_rd;
wire		sys_wr;
wire	[15:0]	sys_wdata;
wire	[15:0]	sys_rdata;
wire		sys_rd_rdy;
wire		sys_burst_rdy;

wire	[12:0]  isdram_addr;
wire	[1:0]   isdram_ba; 
wire	[15:0]  isdram_dqi;
wire	[15:0]  isdram_dqo;
wire          isdram_dq_oe;
wire	        isdram_ras_;
wire	        isdram_cas_;
wire	        isdram_we_;
wire			  isdram_dqm;
wire	        isdram_cke;
wire	        isdram_cs_;

assign sd_init_done = PAA;




assign sys_addr = wr_req ? wr_addr : rd_addr;
assign sys_rd = rd_req;
assign sys_wr = wr_req;
assign sys_wdata = wr_data;
assign rd_data = sys_rdata;
assign wr_valid = wr_req & sys_burst_rdy;
assign rd_valid = rd_req & sys_burst_rdy;
assign rd_rdy = sys_rd_rdy;




assign sdram_dq[0]     = sdram_dq_oe[0] ? sdram_dqo[0] : 1'Hz;
assign sdram_dq[1]     = sdram_dq_oe[1] ? sdram_dqo[1] : 1'Hz;
assign sdram_dq[2]     = sdram_dq_oe[2] ? sdram_dqo[2] : 1'Hz;
assign sdram_dq[3]     = sdram_dq_oe[3] ? sdram_dqo[3] : 1'Hz;
assign sdram_dq[4]     = sdram_dq_oe[4] ? sdram_dqo[4] : 1'Hz;
assign sdram_dq[5]     = sdram_dq_oe[5] ? sdram_dqo[5] : 1'Hz;
assign sdram_dq[6]     = sdram_dq_oe[6] ? sdram_dqo[6] : 1'Hz;
assign sdram_dq[7]     = sdram_dq_oe[7] ? sdram_dqo[7] : 1'Hz;
assign sdram_dq[8]     = sdram_dq_oe[8] ? sdram_dqo[8] : 1'Hz;
assign sdram_dq[9]     = sdram_dq_oe[9] ? sdram_dqo[9] : 1'Hz;
assign sdram_dq[10]     = sdram_dq_oe[10] ? sdram_dqo[10] : 1'Hz;
assign sdram_dq[11]     = sdram_dq_oe[11] ? sdram_dqo[11] : 1'Hz;
assign sdram_dq[12]     = sdram_dq_oe[12] ? sdram_dqo[12] : 1'Hz;
assign sdram_dq[13]     = sdram_dq_oe[13] ? sdram_dqo[13] : 1'Hz;
assign sdram_dq[14]     = sdram_dq_oe[14] ? sdram_dqo[14] : 1'Hz;
assign sdram_dq[15]     = sdram_dq_oe[15] ? sdram_dqo[15] : 1'Hz;
assign sdram_dqi = sdram_dq;




assign STOP_CLK         = 1'b0;
assign BLK_SIZE         = 3'b000;
assign IS_SEQ           = 1'b0;
assign MODULE_BK_NUM    = 1'b1;     
assign ROW_SIZE         = 2'b10;
assign BIT_SIZE         = 2'b10;
assign BK_SIZE          = 1'b1;
assign COL_SIZE         = 3'b001;
assign tRCD             = 2'b10;
assign tCAS             = 2'b11;
assign tRP              = 2'b11;
assign tRAS             = 3'b110;
assign tREF             = 12'd257;
assign tRC              = 4'b1000;




sdram_init  sdram_init_x(
    .sdram_clk(sdram_clk),    .sdram_rst_(sdram_rst_),

    .PAA(PAA),          .SET_MODE(SET_MODE)
);

sdram_ctl sdram_ctl(
    .CLK(sdram_clk),  .RST_(sdram_rst_),
                                

    .STOP_CLK(STOP_CLK), .PAA(PAA), .SET_MODE(SET_MODE), .BLK_SIZE(BLK_SIZE), .IS_SEQ(IS_SEQ), 
    .MODULE_BK_NUM(MODULE_BK_NUM), .ROW_SIZE(ROW_SIZE), .COL_SIZE(COL_SIZE[1:0]), .BK_SIZE(BK_SIZE), .BIT_SIZE(BIT_SIZE), 
    .tRCD(tRCD), .tCAS(tCAS), .tRAS(tRAS), .tRP(tRP),
    .tREF(tREF), .tRC(tRC),
    

    .ADDR(sys_addr), .RD(sys_rd), .WR(sys_wr), .DAT_I(sys_wdata), .DAT_O(sys_rdata),
    .RD_DAT_RDY(sys_rd_rdy), .BURST_RDY(sys_burst_rdy), .RW(),
    .CPU_GNT_(1'b0), .MUX_EN(),
    

    .CKE(isdram_cke), .CS_(isdram_cs_),
    .RAS_(isdram_ras_), .CAS_(isdram_cas_), .WE_(isdram_we_), .DQM(isdram_dqm),
    .BA(isdram_ba),  .DIMM_ADDR(isdram_addr),    
    .DQ_I(isdram_dqi), .DQ_O(isdram_dqo), .DQ_OE(isdram_dq_oe)




);

sdram_io sdram_io(

    .sdram_clk(sdram_clk),


    .sdram_addr(isdram_addr), .sdram_ba(isdram_ba), .sdram_dqo(isdram_dqo),
    .sdram_dqi(isdram_dqi), .sdram_dq_oe(isdram_dq_oe), .sdram_ras_(isdram_ras_),
    .sdram_cas_(isdram_cas_), .sdram_we_(isdram_we_), .sdram_dqm(isdram_dqm), 
	 .sdram_cke(isdram_cke), .sdram_cs_(isdram_cs_),


    .pad_addr(sdram_addr), .pad_ba(sdram_ba), .pad_dqo(sdram_dqo), 
	 .pad_dqi(sdram_dqi), .pad_dq_oe(sdram_dq_oe), .pad_ras_(sdram_ras_), 
	 .pad_cas_(sdram_cas_), .pad_we_(sdram_we_), .pad_dqml(sdram_dqml), .pad_dqmh(sdram_dqmh),
    .pad_cke(sdram_cke), .pad_cs_(sdram_cs_)
);

endmodule