data/full_repos/permissive/133149315/clk_div/sim/tb.v
 line:21: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_div/sim/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_div/sim/tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_div/sim/tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #2210;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_div/sim/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #1000;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_div/sim/tb.v:31: Unsupported: Ignoring delay on this delayed statement.\nalways #3.78 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/133149315/clk_div/sim/tb.v:45: Unsupported or unknown PLI call: $fsdbDumpfile\n     $fsdbDumpfile("tb.fsdb");\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133149315/clk_div/sim/tb.v:46: Unsupported or unknown PLI call: $fsdbDumpvars\n     $fsdbDumpvars();\n     ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;

reg clk;
reg rstn;

reg [7:0] div;
reg       div_tog;


initial begin
   clk = 1'b0;
   div_tog = 1'b0;
   rstn= 1'b1;
   div = 8'h0;
   #100;
   rstn= 1'b0;
   #100;
   rstn= 1'b1;

   repeat(100) begin
      #2210;
      div     = $random & 5'h0f;
      div_tog = ~div_tog;
   end

   #1000;
   $finish;
end

always #3.78 clk = ~clk;

wire o_clk;

clk_div i_clk_div(
.i_clk    (clk),
.i_rstn   (rstn),
.i_div    (div),
.i_div_tog(div_tog),
.o_clk    (o_clk)
);


initial begin
     $fsdbDumpfile("tb.fsdb");
     $fsdbDumpvars();
end

endmodule
module tb;


reg clk;
reg rstn;

reg [7:0] div;
reg       div_tog;


initial begin
   clk = 1'b0;
   div_tog = 1'b0;
   rstn= 1'b1;
   div = 8'h0;
   #100;
   rstn= 1'b0;
   #100;
   rstn= 1'b1;

   repeat(100) begin
      #2210;
      div     = $random & 5'h0f;
      div_tog = ~div_tog;
   end

   #1000;
   $finish;
end

always #3.78 clk = ~clk;

wire o_clk;

clk_div i_clk_div(
.i_clk    (clk),
.i_rstn   (rstn),
.i_div    (div),
.i_div_tog(div_tog),
.o_clk    (o_clk)
);


initial begin
     $fsdbDumpfile("tb.fsdb");
     $fsdbDumpvars();
end

endmodule