data/full_repos/permissive/173099254/lab1/fisier_sursa.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/173099254/lab1/fisier_sursa.v:17: Unsupported: Ignoring delay on this delayed statement.\n#20 x=8\'b11110000;  \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module exemplu(input [7:0] x, output y);

assign y=x[7] & x[6] & x[5] & x[4];


endmodule
module exemplu(input [7:0] x, output y);


assign y=x[7] & x[6] & x[5] & x[4];


endmodule