data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/sm2201_interface_board_bus_passivity_testbench.v
 line:66: before: "reg"
1: b'%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/sm2201_interface_board_bus_passivity_testbench.v:118: Unsupported: Ignoring delay on this delayed statement.\n        #75 isa_clk <= ~isa_clk; \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/sm2201_interface_board_bus_passivity_testbench.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #150 counter <= counter + 1;\n        ^\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/sm2201_interface_board_bus_passivity_testbench.v:70: Cannot find file containing module: \'sm2201_interface_board\'\n    sm2201_interface_board\n    ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/sm2201_interface_board\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/sm2201_interface_board.v\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/sm2201_interface_board.sv\n             sm2201_interface_board\n             sm2201_interface_board.v\n             sm2201_interface_board.sv\n             obj_dir/sm2201_interface_board\n             obj_dir/sm2201_interface_board.v\n             obj_dir/sm2201_interface_board.sv\n%Warning-WIDTH: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/sm2201_interface_board_bus_passivity_testbench.v:107: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                                                                                          : ... In instance sm2201_interface_board_bus_passivity_testbench\n        isa_data_out <= 16\'b0000000000000000;\n                     ^~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sm2201_interface_board_bus_passivity_testbench;


    reg isa_clk;
    reg isa_ior;
    reg isa_iow;
    reg isa_reset;
    reg isa_ale;
    reg isa_aen;
    wire q_r_debug;

    reg [9:0] isa_addr;
    wire [7:0] isa_data;
    reg [31:0] counter;
    reg [1:0] operation;
    reg [31:0] state;
    wire cb_b_b1;


    wire [7:0] isa_irq;
    wire isa_chrdy;


    reg cb_prr;
    reg cb_zk4;
    wire [15:0] cb_data;
    reg [15:0] cb_data_out;


    wire [11:0] cb_addr;
    reg [7:0] isa_data_out;

    

    assign cb_data = cb_b_b1 == 1'b1 ? cb_data_out : 16'b0000000000000000;




    localparam reg[31:0] WRITE_ADDR_INT_REG_READY = 0;
    localparam reg[31:0] WRITE_ADDR_INT_REG_SEND = 1;


    sm2201_interface_board
    uut (

        .isa_clk(isa_clk), 
        .isa_reset(isa_reset), 
        .isa_ior(isa_ior), 
        .isa_iow(isa_iow), 
        .isa_addr(isa_addr),
        .isa_data(isa_data),
        .isa_ale(isa_ale),
        .isa_aen(isa_aen),

        .isa_chrdy(isa_chrdy),

        .q_r_debug(q_r_debug),

        .cb_prr(cb_prr),
        .cb_zk4(cb_zk4),
        .cb_cx1(cb_cx1),
        .cb_data(cb_data),
        .cb_addr(cb_addr),
        .cb_b_b1(cb_b_b1)
    );

    initial 
    begin

        isa_reset <= 0;
        isa_clk <= 0;
        isa_ior <= 1;
        isa_iow <= 1;
        isa_addr <= 34;
        isa_ale <= 0;
        isa_aen <= 0;

        cb_prr <= 1;
        cb_zk4 <= 1;
        isa_data_out <= 16'b0000000000000000;
        cb_data_out <=
		               16'b1111111111111111;

        counter <= 0;
        operation <= 0;
    end
    

    always
    begin
        #75 isa_clk <= ~isa_clk; 
        #150 counter <= counter + 1;
        if (counter == 100)
        begin
            isa_addr <= 262;
            isa_ale <= 1'b1;
        end
        if (counter == 110)
            isa_ale <= 1'b0;
        if (counter == 120)
            isa_ior <= 1'b0;
        if (counter == 200)
            isa_ior <= 1'b1;
    end
endmodule
module sm2201_interface_board_bus_passivity_testbench;



    reg isa_clk;
    reg isa_ior;
    reg isa_iow;
    reg isa_reset;
    reg isa_ale;
    reg isa_aen;
    wire q_r_debug;

    reg [9:0] isa_addr;
    wire [7:0] isa_data;
    reg [31:0] counter;
    reg [1:0] operation;
    reg [31:0] state;
    wire cb_b_b1;


    wire [7:0] isa_irq;
    wire isa_chrdy;


    reg cb_prr;
    reg cb_zk4;
    wire [15:0] cb_data;
    reg [15:0] cb_data_out;


    wire [11:0] cb_addr;
    reg [7:0] isa_data_out;

    

    assign cb_data = cb_b_b1 == 1'b1 ? cb_data_out : 16'b0000000000000000;




    localparam reg[31:0] WRITE_ADDR_INT_REG_READY = 0;
    localparam reg[31:0] WRITE_ADDR_INT_REG_SEND = 1;


    sm2201_interface_board
    uut (

        .isa_clk(isa_clk), 
        .isa_reset(isa_reset), 
        .isa_ior(isa_ior), 
        .isa_iow(isa_iow), 
        .isa_addr(isa_addr),
        .isa_data(isa_data),
        .isa_ale(isa_ale),
        .isa_aen(isa_aen),

        .isa_chrdy(isa_chrdy),

        .q_r_debug(q_r_debug),

        .cb_prr(cb_prr),
        .cb_zk4(cb_zk4),
        .cb_cx1(cb_cx1),
        .cb_data(cb_data),
        .cb_addr(cb_addr),
        .cb_b_b1(cb_b_b1)
    );

    initial 
    begin

        isa_reset <= 0;
        isa_clk <= 0;
        isa_ior <= 1;
        isa_iow <= 1;
        isa_addr <= 34;
        isa_ale <= 0;
        isa_aen <= 0;

        cb_prr <= 1;
        cb_zk4 <= 1;
        isa_data_out <= 16'b0000000000000000;
        cb_data_out <=
		               16'b1111111111111111;

        counter <= 0;
        operation <= 0;
    end
    

    always
    begin
        #75 isa_clk <= ~isa_clk; 
        #150 counter <= counter + 1;
        if (counter == 100)
        begin
            isa_addr <= 262;
            isa_ale <= 1'b1;
        end
        if (counter == 110)
            isa_ale <= 1'b0;
        if (counter == 120)
            isa_ior <= 1'b0;
        if (counter == 200)
            isa_ior <= 1'b1;
    end
endmodule