data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/block_SDP.v
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/block_SDP.v:157: Cannot find file containing module: 'correlator_SDP'\n   correlator_SDP\n   ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/correlator_SDP\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/correlator_SDP.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/correlator_SDP.sv\n             correlator_SDP\n             correlator_SDP.v\n             correlator_SDP.sv\n             obj_dir/correlator_SDP\n             obj_dir/correlator_SDP.v\n             obj_dir/correlator_SDP.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/block_SDP.v:176: Cannot find file containing module: 'correlator_SDP'\n   correlator_SDP\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/block_SDP.v:195: Cannot find file containing module: 'correlator_SDP'\n   correlator_SDP\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/block_SDP.v:214: Cannot find file containing module: 'correlator_SDP'\n   correlator_SDP\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/block_SDP.v:238: Cannot find file containing module: 'MUX8'\n   MUX8 #( .WIDTH(ACCUM) ) DMUX\n   ^~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/block_SDP.v:256: Cannot find file containing module: 'RAMB8X32_SDP'\n   RAMB8X32_SDP #(.DELAY(DELAY)) VISRAM [NSRAM-1:0]\n   ^~~~~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/block_SDP.v:256: ../V3Width.cpp:3377: Visit function missing? Widthed expectation for this node: PARSEREF 0x5583772f1d70 <e1334> {c256}  NSRAM [TEXT]\n                                                                                                                     : ... In instance block_SDP\n   RAMB8X32_SDP #(.DELAY(DELAY)) VISRAM [NSRAM-1:0]\n                                         ^~~~~\n"
module block_SDP
  #(
    parameter ACCUM = 24,
    parameter MSB   = ACCUM-1,
    parameter IBITS = 24,
    parameter ISB   = IBITS-1,


    parameter PAIRS0 = 120'h0,
    parameter PAIRS1 = 120'h0,
    parameter PAIRS2 = 120'h0,
    parameter PAIRS3 = 120'h0,


    parameter WIDTH = ACCUM*2,
    parameter WSB   = WIDTH-1,
    parameter QBITS = WIDTH*4,
    parameter QSB   = QBITS-1,


    parameter TRATE = 12,
    parameter TBITS = 4,
    parameter TSB   = TBITS-1,


    parameter XBITS = 4,
    parameter XSB   = XBITS-1,
    parameter NSRAM = ACCUM>>2,


    parameter ABITS = TBITS+XBITS,
    parameter ASB   = ABITS-1,
    parameter JBITS = ABITS+3,
    parameter JSB   = JBITS-1,


    parameter DELAY = 3)
   (
    input          clk_x,


    input [TSB:0]  x_rd_adr_i,
    input [TSB:0]  x_wr_adr_i,

    input [TSB:0]  y_rd_adr_i,
    input [TSB:0]  y_wr_adr_i,

    input [XSB:0]  bank_adr_i,


    input          sw_i,
    input          en_i,
    input [ISB:0]  re_i,
    input [ISB:0]  im_i,


    input          sram_ck_i,
    input          sram_ce_i,
    input [JSB:0]  sram_ad_i,
    output [MSB:0] sram_do_o
    );


   wire [7:0]      waddr = {bank_adr_i, x_wr_adr_i};
   wire            write;
   wire [WSB:0]    vis0, vis1, vis2, vis3;
   wire [QSB:0]    vis;


   reg [2:0]       sram_sel;
   wire [ASB:0]    sram_ad_w;
   wire [QSB:0]    sram_do_w;
   wire [MSB:0]    sram_do;
   reg [MSB:0]     sram_dat;
   wire [MSB:0]    sram_d0, sram_d2, sram_d4, sram_d6;
   wire [MSB:0]    sram_d1, sram_d3, sram_d5, sram_d7;




   assign sram_do_o = sram_dat;


   assign sram_ad_w = sram_ad_i[JSB:3];


   assign {sram_d7, sram_d6, sram_d5, sram_d4,
           sram_d3, sram_d2, sram_d1, sram_d0} = sram_do_w;


   assign vis = {vis3, vis2, vis1, vis0};




   always @(posedge sram_ck_i) begin
      sram_sel <= #DELAY sram_ad_i[2:0];
      sram_dat <= #DELAY sram_do;
   end





   correlator_SDP
     #(  .ACCUM(ACCUM),
         .SUMHI(0),
         .TBITS(TBITS),
         .PAIRS(PAIRS0),
         .DELAY(DELAY)
         ) CORN0
       ( .clk_x(clk_x),
         .sw(sw_i),
         .en(en_i),
         .re(re_i),
         .im(im_i),
         .rd(x_rd_adr_i),
         .wr(x_wr_adr_i),

         .vld(write),
         .vis(vis0)
         );

   correlator_SDP
     #(  .ACCUM(ACCUM),
         .SUMHI(0),
         .TBITS(TBITS),
         .PAIRS(PAIRS1),
         .DELAY(DELAY)
         ) CORN1
       ( .clk_x(clk_x),
         .sw(sw_i),
         .en(en_i),
         .re(re_i),
         .im(im_i),
         .rd(x_rd_adr_i),
         .wr(x_wr_adr_i),

         .vld(),
         .vis(vis1)
         );

   correlator_SDP
     #(  .ACCUM(ACCUM),
         .SUMHI(0),
         .TBITS(TBITS),
         .PAIRS(PAIRS2),
         .DELAY(DELAY)
         ) CORN2
       ( .clk_x(clk_x),
         .sw(sw_i),
         .en(en_i),
         .re(re_i),
         .im(im_i),
         .rd(y_rd_adr_i),
         .wr(y_wr_adr_i),

         .vld(),
         .vis(vis2)
         );

   correlator_SDP
     #(  .ACCUM(ACCUM),
         .SUMHI(1),
         .TBITS(TBITS),
         .PAIRS(PAIRS3),
         .DELAY(DELAY)
         ) CORN3
       ( .clk_x(clk_x),
         .sw(sw_i),
         .en(en_i),
         .re(re_i),
         .im(im_i),
         .rd(y_rd_adr_i),
         .wr(y_wr_adr_i),

         .vld(),
         .vis(vis3)
         );






   MUX8 #( .WIDTH(ACCUM) ) DMUX
     ( .a(sram_d0),
       .b(sram_d1),
       .c(sram_d2),
       .d(sram_d3),
       .e(sram_d4),
       .f(sram_d5),
       .g(sram_d6),
       .h(sram_d7),
       .s(sram_sel),
       .x(sram_do)
       );






   RAMB8X32_SDP #(.DELAY(DELAY)) VISRAM [NSRAM-1:0]
     (
       .WCLK (clk_x),
       .WE   (write),
       .WADDR(waddr),
       .DI   (vis),


       .RCLK (sram_ck_i),
       .CE   (sram_ce_i),
       .RADDR(sram_ad_w),
       .DO   (sram_do_w)
       );


endmodule
module block_SDP
  #(
    parameter ACCUM = 24,
    parameter MSB   = ACCUM-1,
    parameter IBITS = 24,
    parameter ISB   = IBITS-1,


    parameter PAIRS0 = 120'h0,
    parameter PAIRS1 = 120'h0,
    parameter PAIRS2 = 120'h0,
    parameter PAIRS3 = 120'h0,


    parameter WIDTH = ACCUM*2,
    parameter WSB   = WIDTH-1,
    parameter QBITS = WIDTH*4,
    parameter QSB   = QBITS-1,


    parameter TRATE = 12,
    parameter TBITS = 4,
    parameter TSB   = TBITS-1,


    parameter XBITS = 4,
    parameter XSB   = XBITS-1,
    parameter NSRAM = ACCUM>>2,


    parameter ABITS = TBITS+XBITS,
    parameter ASB   = ABITS-1,
    parameter JBITS = ABITS+3,
    parameter JSB   = JBITS-1,


    parameter DELAY = 3)
   (
    input          clk_x,


    input [TSB:0]  x_rd_adr_i,
    input [TSB:0]  x_wr_adr_i,

    input [TSB:0]  y_rd_adr_i,
    input [TSB:0]  y_wr_adr_i,

    input [XSB:0]  bank_adr_i,


    input          sw_i,
    input          en_i,
    input [ISB:0]  re_i,
    input [ISB:0]  im_i,


    input          sram_ck_i,
    input          sram_ce_i,
    input [JSB:0]  sram_ad_i,
    output [MSB:0] sram_do_o
    );



   wire [7:0]      waddr = {bank_adr_i, x_wr_adr_i};
   wire            write;
   wire [WSB:0]    vis0, vis1, vis2, vis3;
   wire [QSB:0]    vis;


   reg [2:0]       sram_sel;
   wire [ASB:0]    sram_ad_w;
   wire [QSB:0]    sram_do_w;
   wire [MSB:0]    sram_do;
   reg [MSB:0]     sram_dat;
   wire [MSB:0]    sram_d0, sram_d2, sram_d4, sram_d6;
   wire [MSB:0]    sram_d1, sram_d3, sram_d5, sram_d7;




   assign sram_do_o = sram_dat;


   assign sram_ad_w = sram_ad_i[JSB:3];


   assign {sram_d7, sram_d6, sram_d5, sram_d4,
           sram_d3, sram_d2, sram_d1, sram_d0} = sram_do_w;


   assign vis = {vis3, vis2, vis1, vis0};




   always @(posedge sram_ck_i) begin
      sram_sel <= #DELAY sram_ad_i[2:0];
      sram_dat <= #DELAY sram_do;
   end





   correlator_SDP
     #(  .ACCUM(ACCUM),
         .SUMHI(0),
         .TBITS(TBITS),
         .PAIRS(PAIRS0),
         .DELAY(DELAY)
         ) CORN0
       ( .clk_x(clk_x),
         .sw(sw_i),
         .en(en_i),
         .re(re_i),
         .im(im_i),
         .rd(x_rd_adr_i),
         .wr(x_wr_adr_i),

         .vld(write),
         .vis(vis0)
         );

   correlator_SDP
     #(  .ACCUM(ACCUM),
         .SUMHI(0),
         .TBITS(TBITS),
         .PAIRS(PAIRS1),
         .DELAY(DELAY)
         ) CORN1
       ( .clk_x(clk_x),
         .sw(sw_i),
         .en(en_i),
         .re(re_i),
         .im(im_i),
         .rd(x_rd_adr_i),
         .wr(x_wr_adr_i),

         .vld(),
         .vis(vis1)
         );

   correlator_SDP
     #(  .ACCUM(ACCUM),
         .SUMHI(0),
         .TBITS(TBITS),
         .PAIRS(PAIRS2),
         .DELAY(DELAY)
         ) CORN2
       ( .clk_x(clk_x),
         .sw(sw_i),
         .en(en_i),
         .re(re_i),
         .im(im_i),
         .rd(y_rd_adr_i),
         .wr(y_wr_adr_i),

         .vld(),
         .vis(vis2)
         );

   correlator_SDP
     #(  .ACCUM(ACCUM),
         .SUMHI(1),
         .TBITS(TBITS),
         .PAIRS(PAIRS3),
         .DELAY(DELAY)
         ) CORN3
       ( .clk_x(clk_x),
         .sw(sw_i),
         .en(en_i),
         .re(re_i),
         .im(im_i),
         .rd(y_rd_adr_i),
         .wr(y_wr_adr_i),

         .vld(),
         .vis(vis3)
         );






   MUX8 #( .WIDTH(ACCUM) ) DMUX
     ( .a(sram_d0),
       .b(sram_d1),
       .c(sram_d2),
       .d(sram_d3),
       .e(sram_d4),
       .f(sram_d5),
       .g(sram_d6),
       .h(sram_d7),
       .s(sram_sel),
       .x(sram_do)
       );






   RAMB8X32_SDP #(.DELAY(DELAY)) VISRAM [NSRAM-1:0]
     (
       .WCLK (clk_x),
       .WE   (write),
       .WADDR(waddr),
       .DI   (vis),


       .RCLK (sram_ck_i),
       .CE   (sram_ce_i),
       .RADDR(sram_ad_w),
       .DO   (sram_do_w)
       );


endmodule