data/full_repos/permissive/143278/ivltests/br_gh15.v
 line:11: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh15.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #0 $display("%b", y);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br_gh15.v:8: Operator ADD expects 4 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                      : ... In instance bug\nassign y = 4\'bxx00 + 2\'b00;\n                   ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug();

wire [3:0] y;

assign y = 4'bxx00 + 2'b00;

initial begin
  #0 $display("%b", y);
  if (y === 4'bxxxx)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module bug();


wire [3:0] y;

assign y = 4'bxx00 + 2'b00;

initial begin
  #0 $display("%b", y);
  if (y === 4'bxxxx)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule