data/full_repos/permissive/173099254/lab7/cod.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173099254/lab7/cod.v:35: Unsupported: Ignoring delay on this delayed statement.\nalways #5 CLK=~CLK;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab7/cod.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = i;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab7/cod.v:52: Unsupported: Ignoring delay on this delayed statement.\n   #20 A = i;\n   ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab7/cod.v:45: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                  : ... In instance ram_test\n  #20 A = i;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab7/cod.v:46: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                  : ... In instance ram_test\n  data_write = i;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab7/cod.v:52: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                  : ... In instance ram_test\n   #20 A = i;\n         ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram_test();
wire [3:0]DOUT;
reg [3:0]A;
reg CLK, OE,WE;
reg [3:0]data_write;
integer i;

assign DOUT=data_write;
always #5 CLK=~CLK;

initial begin

  data_write=0;
  WE=1;
  OE=1;
  CLK=0;
  A=0;
 for(i=0;i<16;i=i+1) begin
  #20 A = i;
  data_write = i;
 end 

 WE=0;
 data_write = 4'bz;
 for(i=0;i<16;i=i+1) begin
   #20 A = i;
  end
end
ram ram_component(A, CLK, OE, WE, DOUT);
endmodule
module ram_test();

wire [3:0]DOUT;
reg [3:0]A;
reg CLK, OE,WE;
reg [3:0]data_write;
integer i;

assign DOUT=data_write;
always #5 CLK=~CLK;

initial begin

  data_write=0;
  WE=1;
  OE=1;
  CLK=0;
  A=0;
 for(i=0;i<16;i=i+1) begin
  #20 A = i;
  data_write = i;
 end 

 WE=0;
 data_write = 4'bz;
 for(i=0;i<16;i=i+1) begin
   #20 A = i;
  end
end
ram ram_component(A, CLK, OE, WE, DOUT);
endmodule