data/full_repos/permissive/217347804/DE2-115/UART_RX.v
data/verilator_xmls/cb126240-b2db-444a-865c-3be04917a3e0.xml
module UART_RX(CLK50MHz, RESET, RX, DATA);




	

	input CLK50MHz;
	input RX;
	input RESET;
	output reg [7:0] DATA;



	

	reg [17:0] counter;
	reg tick;
	

	reg [3:0] statemachine;
	reg [4:0] pointer;
	reg [7:0] cache;
	reg [2:0] cacheIndex;
	wire parityBit;
	
	


	assign parityBit = cache[0]^cache[1]^cache[2]^cache[3]^cache[4]^cache[5]^cache[6]^cache[7]; 



	always @(posedge tick or negedge RESET)
	begin
		if (RESET == 0)
			begin
				statemachine <= 4'd3;
				pointer <= 0;
				cache <= 0;
				cacheIndex <= 0;
				
				DATA <= 8'd0;
				
			end
		else
			begin
				case (statemachine)


					4'd0	: 
					begin
						if (RX == 0 || pointer != 0)
							begin
								pointer <= pointer + 1;
								if (pointer == 5'd24)
								begin
									statemachine <= statemachine + 1;
									pointer <= 0;
									cacheIndex <= 0;
								end
							end
						else
							pointer <= 0;
					end


					4'd1	:
					begin
						if (pointer == 0)
							begin
								cache[cacheIndex] <= RX;
								pointer <= pointer + 1;
							end
						else
							begin
								pointer <= pointer + 1;

								if (pointer == 5'd16)
								begin
									if (cacheIndex == 3'd7)
										begin
											cacheIndex <= 0;
											statemachine <= 4'd2;
											pointer <= 0;
										end
									else
										begin
											cacheIndex <= cacheIndex + 1;
											pointer <= 0;
										end
								end
							end
					end


					4'd2	:
					begin
						if (pointer == 0)
							begin

								
								pointer <= pointer + 1;
								
								


									DATA <= cache;


							end
						else
							begin
								pointer <= pointer + 1;

								if (pointer == 5'd16)
								begin
									pointer <= 0;
									statemachine <= 4'd3;
								end
							end
					end



					default	:
					begin
						if (RX == 1)
						begin
							pointer <= 0;
							statemachine <= 4'd0;
						end
					end
				endcase
			end
	end



	always @(posedge CLK50MHz or negedge RESET)
	begin
		if (RESET == 0)
			begin
				tick <= 0;
				counter <= 18'd0;
			end
		else
			begin
				counter <= counter + 1;
				if (counter == 18'd153000)
				begin
					tick <= !tick;
					counter <= 18'd0;
				end
			end

	end


endmodule
module UART_RX(CLK50MHz, RESET, RX, DATA);





	

	input CLK50MHz;
	input RX;
	input RESET;
	output reg [7:0] DATA;



	

	reg [17:0] counter;
	reg tick;
	

	reg [3:0] statemachine;
	reg [4:0] pointer;
	reg [7:0] cache;
	reg [2:0] cacheIndex;
	wire parityBit;
	
	


	assign parityBit = cache[0]^cache[1]^cache[2]^cache[3]^cache[4]^cache[5]^cache[6]^cache[7]; 



	always @(posedge tick or negedge RESET)
	begin
		if (RESET == 0)
			begin
				statemachine <= 4'd3;
				pointer <= 0;
				cache <= 0;
				cacheIndex <= 0;
				
				DATA <= 8'd0;
				
			end
		else
			begin
				case (statemachine)


					4'd0	: 
					begin
						if (RX == 0 || pointer != 0)
							begin
								pointer <= pointer + 1;
								if (pointer == 5'd24)
								begin
									statemachine <= statemachine + 1;
									pointer <= 0;
									cacheIndex <= 0;
								end
							end
						else
							pointer <= 0;
					end


					4'd1	:
					begin
						if (pointer == 0)
							begin
								cache[cacheIndex] <= RX;
								pointer <= pointer + 1;
							end
						else
							begin
								pointer <= pointer + 1;

								if (pointer == 5'd16)
								begin
									if (cacheIndex == 3'd7)
										begin
											cacheIndex <= 0;
											statemachine <= 4'd2;
											pointer <= 0;
										end
									else
										begin
											cacheIndex <= cacheIndex + 1;
											pointer <= 0;
										end
								end
							end
					end


					4'd2	:
					begin
						if (pointer == 0)
							begin

								
								pointer <= pointer + 1;
								
								


									DATA <= cache;


							end
						else
							begin
								pointer <= pointer + 1;

								if (pointer == 5'd16)
								begin
									pointer <= 0;
									statemachine <= 4'd3;
								end
							end
					end



					default	:
					begin
						if (RX == 1)
						begin
							pointer <= 0;
							statemachine <= 4'd0;
						end
					end
				endcase
			end
	end



	always @(posedge CLK50MHz or negedge RESET)
	begin
		if (RESET == 0)
			begin
				tick <= 0;
				counter <= 18'd0;
			end
		else
			begin
				counter <= counter + 1;
				if (counter == 18'd153000)
				begin
					tick <= !tick;
					counter <= 18'd0;
				end
			end

	end


endmodule