data/full_repos/permissive/123690745/HazardUnit.v
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data/verilator_xmls/c6bbdcca-0fa4-4aef-aeb6-9d4308f2f280.xml
module HazardUnit(
    output reg StallF,
    output reg StallD,
    output reg [1:0] ForwardAD = 0, 
    output reg [1:0] ForwardBD = 0,
    output reg FlushE,
    output reg [1:0] ForwardAE = 0,
    output reg [1:0] ForwardBE = 0,
	 output reg ForwardM = 0,
	 output reg MulFlushE = 0,
	 input clk,
    input BranchD,
	 input BranchE,
	 input MemtoRegD,
    input MemtoRegE,
    input RegWriteE,
    input MemtoRegM,
    input RegWriteM,
    input RegWriteW,
	 input MemWriteD,
	 input MemWriteM,
	 input EXLClearD,
	 input CP0WriteE,
	 input CP0WriteM,
    input [4:0] RsD,
    input [4:0] RtD,
    input [4:0] RsE,
    input [4:0] RtE,
	 input [4:0] RdE,
	 input [4:0] RdM,
    input [4:0] WriteRegE,
    input [4:0] WriteRegM,
    input [4:0] WriteRegW,
	 
	 input MDUseD,
	 input BusyE,
	 input StartE
    );


	 always @(*) begin




		if (RsE == WriteRegM && RegWriteM == 1 && WriteRegM != 0 && MemtoRegM == 0 && BranchE != 1) ForwardAE <= 2;
		else
		if (RsE == WriteRegW && RegWriteW == 1 && WriteRegW != 0 && BranchE != 1) ForwardAE <= 1;
		else
		ForwardAE <= 0;
		if (RtE == WriteRegM && RegWriteM == 1 && WriteRegM != 0 && MemtoRegM == 0 && BranchE != 1) ForwardBE <= 2;
		else
		if (RtE == WriteRegW && RegWriteW == 1 && WriteRegW != 0 && BranchE != 1) ForwardBE <= 1;
		else 
		ForwardBE <= 0;
		

		if (RsD == WriteRegM && RegWriteM == 1 && WriteRegM != 0 && MemtoRegM == 0 && BranchD == 1) ForwardAD <= 2;
		else
		if (RsD == WriteRegW && RegWriteW == 1 && WriteRegW != 0) ForwardAD <= 1;
		else
		ForwardAD <= 0;
		
		if (RtD == WriteRegM && RegWriteM == 1 && WriteRegM != 0 && MemtoRegM == 0 && BranchD == 1) ForwardBD <= 2;
		else
		if (RtD == WriteRegW && RegWriteW == 1 && WriteRegW != 0) ForwardBD <= 1;
		else
		ForwardBD <= 0;		


		if (WriteRegM == WriteRegW && RegWriteW == 1 && WriteRegW != 0) ForwardM <= 1;
		else
		ForwardM <= 0;
	




		if ((RsD == WriteRegE) && RegWriteE == 1 && WriteRegE != 0 && MemtoRegE == 1) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
		end
		else if ((RtD == WriteRegE) && MemWriteD == 0 && MemtoRegD == 0 && RegWriteE == 1 && WriteRegE != 0 && MemtoRegE == 1) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
		end
		else if ((RsD == WriteRegE || RtD == WriteRegE) && RegWriteE == 1 && WriteRegE != 0 && BranchD == 1) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
		end
		else if ((RsD == WriteRegM || RtD == WriteRegM) && RegWriteM == 1 && WriteRegM != 0 && MemtoRegM == 1 && BranchD == 1) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
		end
		else if (MDUseD && (BusyE||StartE)) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
			MulFlushE <= 1;
		end
		else if (EXLClearD == 1 &&  (((CP0WriteE && RdE == 14)|| (CP0WriteM && RdM == 14))) ) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
		end
		else begin
			FlushE <= 0;
			StallD <= 0;
			StallF <= 0;
			MulFlushE <= 0;
		end
	 end
	 
endmodule
module HazardUnit(
    output reg StallF,
    output reg StallD,
    output reg [1:0] ForwardAD = 0, 
    output reg [1:0] ForwardBD = 0,
    output reg FlushE,
    output reg [1:0] ForwardAE = 0,
    output reg [1:0] ForwardBE = 0,
	 output reg ForwardM = 0,
	 output reg MulFlushE = 0,
	 input clk,
    input BranchD,
	 input BranchE,
	 input MemtoRegD,
    input MemtoRegE,
    input RegWriteE,
    input MemtoRegM,
    input RegWriteM,
    input RegWriteW,
	 input MemWriteD,
	 input MemWriteM,
	 input EXLClearD,
	 input CP0WriteE,
	 input CP0WriteM,
    input [4:0] RsD,
    input [4:0] RtD,
    input [4:0] RsE,
    input [4:0] RtE,
	 input [4:0] RdE,
	 input [4:0] RdM,
    input [4:0] WriteRegE,
    input [4:0] WriteRegM,
    input [4:0] WriteRegW,
	 
	 input MDUseD,
	 input BusyE,
	 input StartE
    );



	 always @(*) begin




		if (RsE == WriteRegM && RegWriteM == 1 && WriteRegM != 0 && MemtoRegM == 0 && BranchE != 1) ForwardAE <= 2;
		else
		if (RsE == WriteRegW && RegWriteW == 1 && WriteRegW != 0 && BranchE != 1) ForwardAE <= 1;
		else
		ForwardAE <= 0;
		if (RtE == WriteRegM && RegWriteM == 1 && WriteRegM != 0 && MemtoRegM == 0 && BranchE != 1) ForwardBE <= 2;
		else
		if (RtE == WriteRegW && RegWriteW == 1 && WriteRegW != 0 && BranchE != 1) ForwardBE <= 1;
		else 
		ForwardBE <= 0;
		

		if (RsD == WriteRegM && RegWriteM == 1 && WriteRegM != 0 && MemtoRegM == 0 && BranchD == 1) ForwardAD <= 2;
		else
		if (RsD == WriteRegW && RegWriteW == 1 && WriteRegW != 0) ForwardAD <= 1;
		else
		ForwardAD <= 0;
		
		if (RtD == WriteRegM && RegWriteM == 1 && WriteRegM != 0 && MemtoRegM == 0 && BranchD == 1) ForwardBD <= 2;
		else
		if (RtD == WriteRegW && RegWriteW == 1 && WriteRegW != 0) ForwardBD <= 1;
		else
		ForwardBD <= 0;		


		if (WriteRegM == WriteRegW && RegWriteW == 1 && WriteRegW != 0) ForwardM <= 1;
		else
		ForwardM <= 0;
	




		if ((RsD == WriteRegE) && RegWriteE == 1 && WriteRegE != 0 && MemtoRegE == 1) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
		end
		else if ((RtD == WriteRegE) && MemWriteD == 0 && MemtoRegD == 0 && RegWriteE == 1 && WriteRegE != 0 && MemtoRegE == 1) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
		end
		else if ((RsD == WriteRegE || RtD == WriteRegE) && RegWriteE == 1 && WriteRegE != 0 && BranchD == 1) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
		end
		else if ((RsD == WriteRegM || RtD == WriteRegM) && RegWriteM == 1 && WriteRegM != 0 && MemtoRegM == 1 && BranchD == 1) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
		end
		else if (MDUseD && (BusyE||StartE)) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
			MulFlushE <= 1;
		end
		else if (EXLClearD == 1 &&  (((CP0WriteE && RdE == 14)|| (CP0WriteM && RdM == 14))) ) begin
			FlushE <= 1;
			StallD <= 1;
			StallF <= 1;
		end
		else begin
			FlushE <= 0;
			StallD <= 0;
			StallF <= 0;
			MulFlushE <= 0;
		end
	 end
	 
endmodule