data/full_repos/permissive/192147978/cs161_processor_tb.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/192147978/cs161_processor_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  # 20 ; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/192147978/cs161_processor_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  # 20 ; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/192147978/cs161_processor_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  # 20 ; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/192147978/cs161_processor_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #20 clk = ~clk;\n  ^\n%Error: data/full_repos/permissive/192147978/cs161_processor_tb.v:21: Cannot find file containing module: \'cs161_processor\'\n cs161_processor uut (\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/192147978,data/full_repos/permissive/192147978/cs161_processor\n             data/full_repos/permissive/192147978,data/full_repos/permissive/192147978/cs161_processor.v\n             data/full_repos/permissive/192147978,data/full_repos/permissive/192147978/cs161_processor.sv\n             cs161_processor\n             cs161_processor.v\n             cs161_processor.sv\n             obj_dir/cs161_processor\n             obj_dir/cs161_processor.v\n             obj_dir/cs161_processor.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cs161_processor_testbench( );


  
  reg clk ;
  reg rst ;


  
  wire [31:0] prog_count  ;
  wire [5:0] instr_opcode ;
  wire [4:0] reg1_addr    ;
  wire [31:0] reg1_data   ;
  wire [4:0] reg2_addr  ;
  wire [31:0] reg2_data ;
  wire [4:0] write_reg_addr ;
  wire [31:0] write_reg_data ;

 cs161_processor uut (
    .clk                 ( clk ),
    .rst                 ( rst ),
    .prog_count          ( prog_count ),
    .instr_opcode        ( instr_opcode ),
    .reg1_addr           ( reg1_addr ),
    .reg1_data           ( reg1_data ),
    .reg2_addr           ( reg2_addr ),
    .reg2_data           ( reg2_data ) ,
    .write_reg_addr      ( write_reg_addr ),
    .write_reg_data      ( write_reg_data )
    );
  
  	initial begin 
	 
	 clk = 0 ; 
	 rst = 1 ; 
	 # 20 ; 
	 
	 clk = 1 ; 
	 rst = 1 ; 
	 # 20 ; 

	 clk = 0 ; 
	 rst = 0 ; 
	 # 20 ; 
		 
	 forever begin 
		#20 clk = ~clk;
	 end 
	 
	end 
	
endmodule
module cs161_processor_testbench( );



  
  reg clk ;
  reg rst ;


  
  wire [31:0] prog_count  ;
  wire [5:0] instr_opcode ;
  wire [4:0] reg1_addr    ;
  wire [31:0] reg1_data   ;
  wire [4:0] reg2_addr  ;
  wire [31:0] reg2_data ;
  wire [4:0] write_reg_addr ;
  wire [31:0] write_reg_data ;

 cs161_processor uut (
    .clk                 ( clk ),
    .rst                 ( rst ),
    .prog_count          ( prog_count ),
    .instr_opcode        ( instr_opcode ),
    .reg1_addr           ( reg1_addr ),
    .reg1_data           ( reg1_data ),
    .reg2_addr           ( reg2_addr ),
    .reg2_data           ( reg2_data ) ,
    .write_reg_addr      ( write_reg_addr ),
    .write_reg_data      ( write_reg_data )
    );
  
  	initial begin 
	 
	 clk = 0 ; 
	 rst = 1 ; 
	 # 20 ; 
	 
	 clk = 1 ; 
	 rst = 1 ; 
	 # 20 ; 

	 clk = 0 ; 
	 rst = 0 ; 
	 # 20 ; 
		 
	 forever begin 
		#20 clk = ~clk;
	 end 
	 
	end 
	
endmodule