data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v
1: b'%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:2: Cannot find include file: fir.v\n`include "fir.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench,data/full_repos/permissive/198139336/fir.v\n             data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench,data/full_repos/permissive/198139336/fir.v.v\n             data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench,data/full_repos/permissive/198139336/fir.v.sv\n             fir.v\n             fir.v.v\n             fir.v.sv\n             obj_dir/fir.v\n             obj_dir/fir.v.v\n             obj_dir/fir.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    forever #10 clk <= ~clk; \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:25: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("square_wave.fsdb");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:26: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n     #12;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #12;\n  ^\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:58: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:60: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:65: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:70: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:76: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:78: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:82: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:85: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:89: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:92: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/198139336/DD_lab11/Lab_11_HW_testbench/tb.v:97: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 14 error(s), 3 warning(s)\n'
module tb;


	reg   clk,rst;
	reg   [1:0 ] ctrl;
	reg   [15:0]  din;
	reg   [15:0]  addr; 
	reg   rst_n;
	reg [15:0] in_a[0:63];
	reg [15:0] in_b[0:63];
	reg [15:0] ans [0:63];
	wire   [15:0] dout;
	wire   bsy;
    integer i;

    initial begin
    clk = 0;
    forever #10 clk <= ~clk; 
    end  
	
	initial begin
		$dumpfile("square_wave.fsdb");
		$dumpvars;
	end
	
	fir fir(
    .clk(clk),
	.rst(rst),
    .din(din),
    .ctrl(ctrl),
    .addr(addr),
    .dout(dout),
    .bsy(bsy)
    );
	

    reg [15:0] mem1[0:35];
	reg [15:0] mem2[0:35];
	

    initial begin
        $readmemb("./databin3.mem" , mem1);
		$readmemb("./ans.mem" , mem2);
    end
	
    initial begin

	    addr <= 0;
	    rst <= 1'b0;
	    #12;
	    rst <= 1'b1;
		#12;
		
	    ctrl <= 2'b10;
		@(posedge clk);
		ctrl <= 2'b00;
		@(posedge clk);
		


	    for (i=1;i<37;i=i+1) begin
		    @(posedge clk);
		    din <= mem1[i-1];
		    addr <= (i*4);
	    end
		
		@(posedge clk);
		din <= mem1[0];
	    addr <= 0;
			
		$display("start run");
		
		@(posedge clk);
		ctrl <= 2'b01;
		@(posedge clk);
		ctrl <= 2'b00;
		
		$display("polling busy");
		@(posedge clk);
		
	    while(bsy!=1'b0) begin
		    @(posedge clk);
	    end
		
		$display("operation finish");
		@(posedge clk);
		for (i=1;i<37;i=i+1) begin
		    addr <= (i*4);
		    @(posedge clk);
			@(posedge clk);
			ans[i-1]<=dout;
	    end
		
		@(posedge clk);
		
		for(i=0;i<36;i=i+1) begin
			if(mem2[i]===16'dx && ans[i]===16'dx) begin
				$display("========================");
				$display("=      Correct[%02d]   =",i);
				$display("========================");
				$display("your answer:%d\nreal answer:%d",ans[i],mem2[i]);
			end
			else begin
				casez({|(mem2[i]^ans[i])})
					1'b1: begin
						$display("========================");
						$display("=        Wrong[%02d]   =",i);
						$display("========================");
						$display("your answer:%d\nreal answer:%d",ans[i],mem2[i]);
					end
					1'b0: begin
						$display("========================");
						$display("=      Correct[%02d]   =",i);
						$display("========================");
						$display("your answer:%d\nreal answer:%d",ans[i],mem2[i]);
					end
					1'bx: begin
						$display("========================");
						$display("=        Wrong[%02d]   =",i);
						$display("========================");
						$display("your answer:%d\nreal answer:%d",ans[i],mem2[i]);
					end
				endcase
			end
		end
		
		$finish;
    end

endmodule
module tb;



	reg   clk,rst;
	reg   [1:0 ] ctrl;
	reg   [15:0]  din;
	reg   [15:0]  addr; 
	reg   rst_n;
	reg [15:0] in_a[0:63];
	reg [15:0] in_b[0:63];
	reg [15:0] ans [0:63];
	wire   [15:0] dout;
	wire   bsy;
    integer i;

    initial begin
    clk = 0;
    forever #10 clk <= ~clk; 
    end  
	
	initial begin
		$dumpfile("square_wave.fsdb");
		$dumpvars;
	end
	
	fir fir(
    .clk(clk),
	.rst(rst),
    .din(din),
    .ctrl(ctrl),
    .addr(addr),
    .dout(dout),
    .bsy(bsy)
    );
	

    reg [15:0] mem1[0:35];
	reg [15:0] mem2[0:35];
	

    initial begin
        $readmemb("./databin3.mem" , mem1);
		$readmemb("./ans.mem" , mem2);
    end
	
    initial begin

	    addr <= 0;
	    rst <= 1'b0;
	    #12;
	    rst <= 1'b1;
		#12;
		
	    ctrl <= 2'b10;
		@(posedge clk);
		ctrl <= 2'b00;
		@(posedge clk);
		


	    for (i=1;i<37;i=i+1) begin
		    @(posedge clk);
		    din <= mem1[i-1];
		    addr <= (i*4);
	    end
		
		@(posedge clk);
		din <= mem1[0];
	    addr <= 0;
			
		$display("start run");
		
		@(posedge clk);
		ctrl <= 2'b01;
		@(posedge clk);
		ctrl <= 2'b00;
		
		$display("polling busy");
		@(posedge clk);
		
	    while(bsy!=1'b0) begin
		    @(posedge clk);
	    end
		
		$display("operation finish");
		@(posedge clk);
		for (i=1;i<37;i=i+1) begin
		    addr <= (i*4);
		    @(posedge clk);
			@(posedge clk);
			ans[i-1]<=dout;
	    end
		
		@(posedge clk);
		
		for(i=0;i<36;i=i+1) begin
			if(mem2[i]===16'dx && ans[i]===16'dx) begin
				$display("========================");
				$display("=      Correct[%02d]   =",i);
				$display("========================");
				$display("your answer:%d\nreal answer:%d",ans[i],mem2[i]);
			end
			else begin
				casez({|(mem2[i]^ans[i])})
					1'b1: begin
						$display("========================");
						$display("=        Wrong[%02d]   =",i);
						$display("========================");
						$display("your answer:%d\nreal answer:%d",ans[i],mem2[i]);
					end
					1'b0: begin
						$display("========================");
						$display("=      Correct[%02d]   =",i);
						$display("========================");
						$display("your answer:%d\nreal answer:%d",ans[i],mem2[i]);
					end
					1'bx: begin
						$display("========================");
						$display("=        Wrong[%02d]   =",i);
						$display("========================");
						$display("your answer:%d\nreal answer:%d",ans[i],mem2[i]);
					end
				endcase
			end
		end
		
		$finish;
    end

endmodule