data/full_repos/permissive/167274925/Mux5Bit2To1.v
data/verilator_xmls/cfa3d631-50b7-40c2-85bd-cd53d1dc076f.xml
module Mux5Bit2To1(out, inA, inB, sel);

    output reg [4:0] out;
   
    input [4:0] inA;
    input [4:0] inB;
    input sel;
 
   always@*begin 
      case(sel)
      1'b0:out<=inA;
      1'b1:out<=inB;
      endcase 
   end 
endmodule
module Mux5Bit2To1(out, inA, inB, sel);


    output reg [4:0] out;
   
    input [4:0] inA;
    input [4:0] inB;
    input sel;
 
   always@*begin 
      case(sel)
      1'b0:out<=inA;
      1'b1:out<=inB;
      endcase 
   end 
endmodule