data/full_repos/permissive/211316121/lab6_2_nexys4/clkdiv.v
data/verilator_xmls/7bfc9135-fdb5-4b03-848e-68c28e11213e.xml
module clkdiv2(
    input mclk,

    output clk380,
    output clk6000,
    output clk190,
    output clk1_4hz
    );
    reg [27:0]q;
    always@(posedge mclk)
      q<=q+1;

    assign clk380=q[17];
    assign clk6000=q[13];
    assign clk190=q[18];
    assign clk1_4hz=q[24];

endmodule
module clkdiv2(
    input mclk,

    output clk380,
    output clk6000,
    output clk190,
    output clk1_4hz
    );

    reg [27:0]q;
    always@(posedge mclk)
      q<=q+1;

    assign clk380=q[17];
    assign clk6000=q[13];
    assign clk190=q[18];
    assign clk1_4hz=q[24];

endmodule