data/full_repos/permissive/143278/ivltests/eeq.v
 line:50 column:11: Illegal character "'"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:42: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:50: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b zx10; b = 4\'b zx10; #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:50: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b zx10; b = 4\'b zx10; #1;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:51: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b 1x10; b = 4\'b zx10; #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:51: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b 1x10; b = 4\'b zx10; #1;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:52: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b xz10; b = 4\'b zx10; #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:52: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b xz10; b = 4\'b zx10; #1;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b xz01; b = 4\'b zx10; #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b xz01; b = 4\'b zx10; #1;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b 0000; b = 4\'b 0000; #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b 0000; b = 4\'b 0000; #1;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:55: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b 1111; b = 4\'b 1111; #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:55: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b 1111; b = 4\'b 1111; #1;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:56: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b xxxx; b = 4\'b xxxx; #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:56: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b xxxx; b = 4\'b xxxx; #1;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:57: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b zzzz; b = 4\'b zzzz; #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:57: Unsupported: Ignoring delay on this delayed statement.\n #1 a = 4\'b zzzz; b = 4\'b zzzz; #1;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eeq.v:58: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module eeq;

   reg [3:0] a, b;

   wire      eeq = a === b;
`ifdef DONT_TEST_NEE
   wire      nee = ~(a === b);
`else
   wire      nee = a !== b;
`endif

   reg	     err;

   always
     begin
	#2;
	$display("%b %b ===%b !==%b", a, b, eeq, nee);
	if (((a === b) !== eeq) || ((a !== b) !== nee)) err = 1;
     end

   initial
     begin
	err = 0;
	#1 a = 4'b zx10; b = 4'b zx10; #1;
	#1 a = 4'b 1x10; b = 4'b zx10; #1;
	#1 a = 4'b xz10; b = 4'b zx10; #1;
	#1 a = 4'b xz01; b = 4'b zx10; #1;
	#1 a = 4'b 0000; b = 4'b 0000; #1;
	#1 a = 4'b 1111; b = 4'b 1111; #1;
	#1 a = 4'b xxxx; b = 4'b xxxx; #1;
	#1 a = 4'b zzzz; b = 4'b zzzz; #1;
	#1;
	if (err)
	  $display("FAILED");
	else
	  $display("PASSED");
	$finish;
     end

endmodule
module eeq;


   reg [3:0] a, b;

   wire      eeq = a === b;
`ifdef DONT_TEST_NEE
   wire      nee = ~(a === b);
`else
   wire      nee = a !== b;
`endif

   reg	     err;

   always
     begin
	#2;
	$display("%b %b ===%b !==%b", a, b, eeq, nee);
	if (((a === b) !== eeq) || ((a !== b) !== nee)) err = 1;
     end

   initial
     begin
	err = 0;
	#1 a = 4'b zx10; b = 4'b zx10; #1;
	#1 a = 4'b 1x10; b = 4'b zx10; #1;
	#1 a = 4'b xz10; b = 4'b zx10; #1;
	#1 a = 4'b xz01; b = 4'b zx10; #1;
	#1 a = 4'b 0000; b = 4'b 0000; #1;
	#1 a = 4'b 1111; b = 4'b 1111; #1;
	#1 a = 4'b xxxx; b = 4'b xxxx; #1;
	#1 a = 4'b zzzz; b = 4'b zzzz; #1;
	#1;
	if (err)
	  $display("FAILED");
	else
	  $display("PASSED");
	$finish;
     end

endmodule