data/full_repos/permissive/201488448/2_circuits/2_sequential/34_shift.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/34_shift.v:23: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q'\n                                                                                              : ... In instance top_module.a0\n        Q <= D; \n        ^\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
);

    muxdff a3(KEY[0], KEY[3], SW[3], KEY[1], KEY[2], LEDR[3]);
    muxdff a2(KEY[0], LEDR[3], SW[2], KEY[1], KEY[2], LEDR[2]);
    muxdff a1(KEY[0], LEDR[2], SW[1], KEY[1], KEY[2], LEDR[1]);
    muxdff a0(KEY[0], LEDR[1], SW[0], KEY[1], KEY[2], LEDR[0]);
    
endmodule
module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
);


    muxdff a3(KEY[0], KEY[3], SW[3], KEY[1], KEY[2], LEDR[3]);
    muxdff a2(KEY[0], LEDR[3], SW[2], KEY[1], KEY[2], LEDR[2]);
    muxdff a1(KEY[0], LEDR[2], SW[1], KEY[1], KEY[2], LEDR[1]);
    muxdff a0(KEY[0], LEDR[1], SW[0], KEY[1], KEY[2], LEDR[0]);
    
endmodule