data/full_repos/permissive/163115503/simple_light_toggle_with_debounce/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/163115503/simple_light_toggle_with_debounce/top.v:16: Operator ASSIGN expects 31 bits on the Assign RHS, but Assign RHS\'s VARREF \'clk_time\' generates 61 bits.\n                                                                                               : ... In instance top\n   last_switch_time = clk_time;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/163115503/simple_light_toggle_with_debounce/top.v:14: Operator SUB expects 61 bits on the RHS, but RHS\'s VARREF \'last_switch_time\' generates 31 bits.\n                                                                                               : ... In instance top\n  if (clk_time - last_switch_time > 4000000) begin\n               ^\n%Error: Exiting due to 2 warning(s)\n'
module top (
	input CLK,
	input PIN_1,
	output PIN_13,
	output LED
);

	reg [60:0] clk_time;
	reg [30:0] last_switch_time;
	reg led_state;


	always @(posedge PIN_1) begin
		if (clk_time - last_switch_time > 4000000) begin
			led_state = !led_state;
			last_switch_time = clk_time;
		end
	end

	always @(posedge CLK) begin
		clk_time <= clk_time + 1;
	end

	assign LED = led_state;
	assign PIN_13 = led_state;
endmodule
module top (
	input CLK,
	input PIN_1,
	output PIN_13,
	output LED
);


	reg [60:0] clk_time;
	reg [30:0] last_switch_time;
	reg led_state;


	always @(posedge PIN_1) begin
		if (clk_time - last_switch_time > 4000000) begin
			led_state = !led_state;
			last_switch_time = clk_time;
		end
	end

	always @(posedge CLK) begin
		clk_time <= clk_time + 1;
	end

	assign LED = led_state;
	assign PIN_13 = led_state;
endmodule