data/full_repos/permissive/181665138/verilog/capitolo_iv/D_flip_flop_7474.v
1: b'%Error: data/full_repos/permissive/181665138/verilog/capitolo_iv/D_flip_flop_7474.v:26: Cannot find include file: Clock.v\n`include "Clock.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181665138/verilog/capitolo_iv,data/full_repos/permissive/181665138/Clock.v\n             data/full_repos/permissive/181665138/verilog/capitolo_iv,data/full_repos/permissive/181665138/Clock.v.v\n             data/full_repos/permissive/181665138/verilog/capitolo_iv,data/full_repos/permissive/181665138/Clock.v.sv\n             Clock.v\n             Clock.v.v\n             Clock.v.sv\n             obj_dir/Clock.v\n             obj_dir/Clock.v.v\n             obj_dir/Clock.v.sv\n%Error: data/full_repos/permissive/181665138/verilog/capitolo_iv/D_flip_flop_7474.v:27: Cannot find include file: Latch_SR.v\n`include "Latch_SR.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module D_flip_flop_7474(q, qN, d, p);
    input d, p;
    output q, qN;

    wire c;
    Clock clock(c);

    assign p = c;

    wire r0, s0, y0, yN0;
    Latch_SR Latch_SR_0(y0, yN0, s0, r0);

    wire r1, s1, y1, yN1;
    Latch_SR Latch_SR_1(y1, yN1, s1, r1);

    assign #2 r0 = ~p;
    assign #2 s0 = ~(~p | d | y1);

    assign #4 r1 = ~p;
    assign #4 r1 = ~(~p | ~d | y0);

    wire y2, yN2;
    Latch_SR Latch_SR(y2, yN2, y1, y0);

    assign #6 q = y2;
    assign #6 qN = yN2;
endmodule
module D_flip_flop_7474(q, qN, d, p);

    input d, p;
    output q, qN;

    wire c;
    Clock clock(c);

    assign p = c;

    wire r0, s0, y0, yN0;
    Latch_SR Latch_SR_0(y0, yN0, s0, r0);

    wire r1, s1, y1, yN1;
    Latch_SR Latch_SR_1(y1, yN1, s1, r1);

    assign #2 r0 = ~p;
    assign #2 s0 = ~(~p | d | y1);

    assign #4 r1 = ~p;
    assign #4 r1 = ~(~p | ~d | y0);

    wire y2, yN2;
    Latch_SR Latch_SR(y2, yN2, y1, y0);

    assign #6 q = y2;
    assign #6 qN = yN2;
endmodule