data/full_repos/permissive/106029354/verilog_source/pipeline1_testbench.v
 line:110: before: "integer"
1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline1_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n             params_proc.v\n             params_proc.v.v\n             params_proc.v.sv\n             obj_dir/params_proc.v\n             obj_dir/params_proc.v.v\n             obj_dir/params_proc.v.sv\n%Error: data/full_repos/permissive/106029354/verilog_source/pipeline1_testbench.v:153: Cannot find include file: testbench.v\n`include "testbench.v" \n         ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/pipeline1_testbench.v:65: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module pipeline1_testbench();


`include "params_proc.v"


parameter N_TESTES = 7;


reg [INSTR_WIDTH-1:0] ram [0:(1<<MEM_WIDTH)-1];


reg clk_in, RST, pc_chg;
reg [PC_WIDTH-1:0] pc_in;

wire [INSTR_WIDTH-1:0] instr;
wire [PC_WIDTH-1:0] pc_out;


pipeline1 pipeline10(
	.clk_in(clk_in),
	.RST(RST),
	.pc_chg(pc_chg),
	.pc_in(pc_in),
	.instr(instr),
	.pc_out(pc_out)
	);


task init_input;
begin
    pc_chg = 0;
	pc_in = 0;

	$readmemb("../assembler/program.bin", ram);
end
endtask


task execute_test;
    input integer testes;
    output reg status;


    parameter TESTE1_CHG = 0,
        TESTE1_IN = 3;        

	parameter TESTE2_CHG = 0,
        TESTE2_IN = 4;        

	parameter TESTE3_CHG = 1,
        TESTE3_IN = 6;        

	parameter TESTE4_CHG = 0,
        TESTE4_IN = 1;        

	parameter TESTE5_CHG = 1,
        TESTE5_IN = 2;        

	parameter TESTE6_CHG = 0,
        TESTE6_IN = 10;        

begin

	#1
    case(testes)
	0: begin
	    pc_chg <= TESTE1_CHG;
	    pc_in  <= TESTE1_IN;				
		if (pc_out == PC_INITIAL+2 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	1: begin
	    pc_chg <= TESTE2_CHG;
	    pc_in  <= TESTE2_IN;
		if (pc_out == PC_INITIAL+3 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	2: begin
	    pc_chg <= TESTE3_CHG;
	    pc_in  <= TESTE3_IN;
		if (pc_out == PC_INITIAL+4 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	3: begin
		pc_chg <= TESTE4_CHG;
	    pc_in  <= TESTE4_IN;
		if (pc_out == TESTE3_IN+1 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	4: begin
		pc_chg <= TESTE5_CHG;
	    pc_in  <= TESTE5_IN;
		if (pc_out == TESTE3_IN+2 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	5: begin
		pc_chg <= TESTE6_CHG;
	    pc_in  <= TESTE6_IN;
		if (pc_out == TESTE5_IN+1 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	default: begin			
		status <= 0;
	end
	endcase
end
endtask


task display_input;
    input integer testes;
    input reg status;
begin
    $display("  Teste # %2d  =>  ", testes);
    $display("\t ------ ENTRADAS -------  ");
    $display("\t PC_CHG: %b  ",  pc_chg);
	$display("\t PC_IN:  %6d  ", pc_in);    
end
endtask


task display_output;
    input integer testes;
    input reg status;
begin
    $display("\t ------ SAIDAS -------  ");
    $display("\t INSTR (%3d): %b  ", INSTR_WIDTH, instr);
	$display("\t PC_OUT: %6d  ", pc_out);	
end
endtask



`include "testbench.v"


endmodule
module pipeline1_testbench();



`include "params_proc.v"


parameter N_TESTES = 7;


reg [INSTR_WIDTH-1:0] ram [0:(1<<MEM_WIDTH)-1];


reg clk_in, RST, pc_chg;
reg [PC_WIDTH-1:0] pc_in;

wire [INSTR_WIDTH-1:0] instr;
wire [PC_WIDTH-1:0] pc_out;


pipeline1 pipeline10(
	.clk_in(clk_in),
	.RST(RST),
	.pc_chg(pc_chg),
	.pc_in(pc_in),
	.instr(instr),
	.pc_out(pc_out)
	);


task init_input;
begin
    pc_chg = 0;
	pc_in = 0;

	$readmemb("../assembler/program.bin", ram);
end
endtask


task execute_test;
    input integer testes;
    output reg status;


    parameter TESTE1_CHG = 0,
        TESTE1_IN = 3;        

	parameter TESTE2_CHG = 0,
        TESTE2_IN = 4;        

	parameter TESTE3_CHG = 1,
        TESTE3_IN = 6;        

	parameter TESTE4_CHG = 0,
        TESTE4_IN = 1;        

	parameter TESTE5_CHG = 1,
        TESTE5_IN = 2;        

	parameter TESTE6_CHG = 0,
        TESTE6_IN = 10;        

begin

	#1
    case(testes)
	0: begin
	    pc_chg <= TESTE1_CHG;
	    pc_in  <= TESTE1_IN;				
		if (pc_out == PC_INITIAL+2 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	1: begin
	    pc_chg <= TESTE2_CHG;
	    pc_in  <= TESTE2_IN;
		if (pc_out == PC_INITIAL+3 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	2: begin
	    pc_chg <= TESTE3_CHG;
	    pc_in  <= TESTE3_IN;
		if (pc_out == PC_INITIAL+4 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	3: begin
		pc_chg <= TESTE4_CHG;
	    pc_in  <= TESTE4_IN;
		if (pc_out == TESTE3_IN+1 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	4: begin
		pc_chg <= TESTE5_CHG;
	    pc_in  <= TESTE5_IN;
		if (pc_out == TESTE3_IN+2 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	5: begin
		pc_chg <= TESTE6_CHG;
	    pc_in  <= TESTE6_IN;
		if (pc_out == TESTE5_IN+1 && instr == ram[pc_out-1]) begin
          status <= 0;
        end else begin
          status <= 1;                      
        end
	end
	default: begin			
		status <= 0;
	end
	endcase
end
endtask


task display_input;
    input integer testes;
    input reg status;
begin
    $display("  Teste # %2d  =>  ", testes);
    $display("\t ------ ENTRADAS -------  ");
    $display("\t PC_CHG: %b  ",  pc_chg);
	$display("\t PC_IN:  %6d  ", pc_in);    
end
endtask


task display_output;
    input integer testes;
    input reg status;
begin
    $display("\t ------ SAIDAS -------  ");
    $display("\t INSTR (%3d): %b  ", INSTR_WIDTH, instr);
	$display("\t PC_OUT: %6d  ", pc_out);	
end
endtask



`include "testbench.v"


endmodule