data/full_repos/permissive/133571498/dance/div.v
data/verilator_xmls/bfd070ed-3818-42e8-ae62-56ad5597661f.xml
module div #(parameter N = 22) (
    input clock, reset,
    output slow_clock
);

    reg [N-1:0] count;

	always @(posedge clock, posedge reset) begin
        if (reset) begin
            count <= 0;
        end
        else begin
            count <= count + 1;
        end
    end

	assign slow_clock = count[N-1];

endmodule
module div #(parameter N = 22) (
    input clock, reset,
    output slow_clock
);


    reg [N-1:0] count;

	always @(posedge clock, posedge reset) begin
        if (reset) begin
            count <= 0;
        end
        else begin
            count <= count + 1;
        end
    end

	assign slow_clock = count[N-1];

endmodule