data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/stream_fifo_2clk.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/stream_fifo_2clk.v:23: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module stream_fifo_2clk (din_clk,  din_rst,  din_valid,  din_ready,  din_data,  din_free,
                         dout_clk, dout_rst, dout_valid, dout_ready, dout_data, dout_used);
`include "util.vh"
  parameter             Width = 8;
  parameter             Depth = 1024;
  localparam            UsedBits  = clog2(Depth+1);

  input                 din_clk;
  input                 din_rst;
  input                 din_valid;
  output                din_ready;
  input  [Width-1:0]    din_data;
  output [UsedBits-1:0] din_free;

  input                 dout_clk;
  input                 dout_rst;
  output                dout_valid;
  input                 dout_ready;
  output [Width-1:0]    dout_data;
  output [UsedBits-1:0] dout_used;


  wire full, empty, rd_en, wr_en;

  assign wr_en     = ~full & din_valid;
  assign din_ready = ~full;

  assign rd_en      = ~empty & dout_ready;
  assign dout_valid = ~empty;

  fifo_2clk #(
    .Width (Width),
    .Depth (Depth))
  fifo(
    .wr_clk  (din_clk),
    .wr_rst  (din_rst),
    .wr_en   (wr_en),
    .wr_data (din_data),
    .wr_free (din_free),
    .wr_full (full),

    .rd_clk  (dout_clk),
    .rd_rst  (dout_rst),
    .rd_en   (rd_en),
    .rd_data (dout_data),
    .rd_used (dout_used),
    .rd_empty(empty));

endmodule
module stream_fifo_2clk (din_clk,  din_rst,  din_valid,  din_ready,  din_data,  din_free,
                         dout_clk, dout_rst, dout_valid, dout_ready, dout_data, dout_used);

`include "util.vh"
  parameter             Width = 8;
  parameter             Depth = 1024;
  localparam            UsedBits  = clog2(Depth+1);

  input                 din_clk;
  input                 din_rst;
  input                 din_valid;
  output                din_ready;
  input  [Width-1:0]    din_data;
  output [UsedBits-1:0] din_free;

  input                 dout_clk;
  input                 dout_rst;
  output                dout_valid;
  input                 dout_ready;
  output [Width-1:0]    dout_data;
  output [UsedBits-1:0] dout_used;


  wire full, empty, rd_en, wr_en;

  assign wr_en     = ~full & din_valid;
  assign din_ready = ~full;

  assign rd_en      = ~empty & dout_ready;
  assign dout_valid = ~empty;

  fifo_2clk #(
    .Width (Width),
    .Depth (Depth))
  fifo(
    .wr_clk  (din_clk),
    .wr_rst  (din_rst),
    .wr_en   (wr_en),
    .wr_data (din_data),
    .wr_free (din_free),
    .wr_full (full),

    .rd_clk  (dout_clk),
    .rd_rst  (dout_rst),
    .rd_en   (rd_en),
    .rd_data (dout_data),
    .rd_used (dout_used),
    .rd_empty(empty));

endmodule