data/full_repos/permissive/157005262/verilog/spoilers/counter.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/d4483238-f94f-4d85-9e7c-35c091cc96fa.xml
module counter(input wire       clk,
               input wire       en,
               input wire       rst,
               output reg [3:0] count);
  always @(posedge clk) begin
    if (rst)
      count <= 0;
    else if (en)
      count <= count + 1;
  end
endmodule
module counter(input wire       clk,
               input wire       en,
               input wire       rst,
               output reg [3:0] count);

  always @(posedge clk) begin
    if (rst)
      count <= 0;
    else if (en)
      count <= count + 1;
  end
endmodule