data/full_repos/permissive/172912857/project_bcd_7dig/bcd_7dig.v
 line:115: before: "("
data/verilator_xmls/2c5f037e-d35a-4abe-b4b8-0ad997fa253c.xml
module counter(
    input reset,
    input clk,
    output reg [1:0] out
    );



    always @(posedge clk, posedge reset)
        if (reset) begin
        out <= 2'b00 ;
        end 
        else begin
        out <= out + 1;
        end
endmodule
module counter(
    input reset,
    input clk,
    output reg [1:0] out
    );




    always @(posedge clk, posedge reset)
        if (reset) begin
        out <= 2'b00 ;
        end 
        else begin
        out <= out + 1;
        end
endmodule