data/full_repos/permissive/158922207/Verilog Design/modules/N_clock_divider.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/N_clock_divider.v\n%Error: Exiting due to 3 error(s)\n'
module N_clock_divider(clk_out, clk_in, reset);
parameter N = 18, n = 200000;
output clk_out;
input clk_in, reset;

wire [N-1:0] Q;
reg out1;


N_bit_counter #(N) counter (Q, clk_out, 4'b0000, reset, clk_in, 1'b1);
 
always @(posedge clk_in, posedge reset) begin
out1 = 0;
if (reset ==  1'b1) out1 <= 0;
else if ( (Q + 1) == (n-1)) out1 <= 1;
else out1 <= 0;
end 
assign clk_out = out1;
endmodule
module N_clock_divider(clk_out, clk_in, reset);

parameter N = 18, n = 200000;
output clk_out;
input clk_in, reset;

wire [N-1:0] Q;
reg out1;


N_bit_counter #(N) counter (Q, clk_out, 4'b0000, reset, clk_in, 1'b1);
 
always @(posedge clk_in, posedge reset) begin
out1 = 0;
if (reset ==  1'b1) out1 <= 0;
else if ( (Q + 1) == (n-1)) out1 <= 1;
else out1 <= 0;
end 
assign clk_out = out1;
endmodule