data/full_repos/permissive/128497744/fsm_calculator_part3/Full_Calculator/Full_Calculator.srcs/sources_1/new/D_FF.v
data/verilator_xmls/d178d9fd-ee76-4284-8e6a-44ecc0c0a3cb.xml
module D_FF #(parameter Data_width = 4)(
    input clk, rst, en,
    input [Data_width - 1:0] D,
    output reg [Data_width - 1:0] Q
    );
    
    always@ (posedge clk)
    begin
        if (rst)
            Q <= 0;
        else if (en)
            Q <= D;
        else
            Q <= Q;
    end
endmodule
module D_FF #(parameter Data_width = 4)(
    input clk, rst, en,
    input [Data_width - 1:0] D,
    output reg [Data_width - 1:0] Q
    );

    
    always@ (posedge clk)
    begin
        if (rst)
            Q <= 0;
        else if (en)
            Q <= D;
        else
            Q <= Q;
    end
endmodule