data/full_repos/permissive/174895599/tf_mash_dac.v
 line:42: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/174895599/tf_mash_dac.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174895599/tf_mash_dac.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/174895599/tf_mash_dac.v:34: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174895599/tf_mash_dac.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/174895599/tf_mash_dac.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/174895599/tf_mash_dac.v:45: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tf_mash_dac;


reg clk;
reg rst_n;
reg [15:0] in;
wire  out;


mash_dac mash_dac_i0
(
.clk(clk),
.rst_n(rst_n),
.in(in),
.out(out)
);

always
begin
  clk = 0;
  #1;
  clk = 1;
  #1;
end

real sum;
integer numclocks=100000;

initial
begin
  $dumpvars;

  in = 32767;
  rst_n = 0;
  #10;
  rst_n = 1;
  #1000;
  sum = 0.0;
  repeat(numclocks)
  begin
    sum = sum + (1.0)*(out);
    @(posedge clk);
  end
  
  $display("Average was %0f",sum/numclocks);
  
  $finish;
end


endmodule
module tf_mash_dac;



reg clk;
reg rst_n;
reg [15:0] in;
wire  out;


mash_dac mash_dac_i0
(
.clk(clk),
.rst_n(rst_n),
.in(in),
.out(out)
);

always
begin
  clk = 0;
  #1;
  clk = 1;
  #1;
end

real sum;
integer numclocks=100000;

initial
begin
  $dumpvars;

  in = 32767;
  rst_n = 0;
  #10;
  rst_n = 1;
  #1000;
  sum = 0.0;
  repeat(numclocks)
  begin
    sum = sum + (1.0)*(out);
    @(posedge clk);
  end
  
  $display("Average was %0f",sum/numclocks);
  
  $finish;
end


endmodule