data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/TERASIC_ALSA.v
1: b"%Error: data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/TERASIC_ALSA.v:84: Cannot find file containing module: 'i2s_output_apb'\ni2s_output_apb i2s_output_apb_inst(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA,data/full_repos/permissive/182333580/i2s_output_apb\n             data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA,data/full_repos/permissive/182333580/i2s_output_apb.v\n             data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA,data/full_repos/permissive/182333580/i2s_output_apb.sv\n             i2s_output_apb\n             i2s_output_apb.v\n             i2s_output_apb.sv\n             obj_dir/i2s_output_apb\n             obj_dir/i2s_output_apb.v\n             obj_dir/i2s_output_apb.sv\n%Error: data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/TERASIC_ALSA.v:120: Cannot find file containing module: 'i2s_clkctrl_apb'\ni2s_clkctrl_apb i2s_clkctrl_apb_inst(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/TERASIC_ALSA.v:150: Cannot find file containing module: 'i2s_shift_out'\n i2s_shift_out i2s_shift_out48(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/TERASIC_ALSA.v:166: Cannot find file containing module: 'i2s_shift_out'\n i2s_shift_out i2s_shift_out44(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/TERASIC_ALSA.v:184: Cannot find file containing module: 'i2s_shift_in'\n i2s_shift_in i2s_shift_in48(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/TERASIC_ALSA.v:201: Cannot find file containing module: 'i2s_shift_in'\n i2s_shift_in i2s_shift_in44(\n ^~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module TERASIC_ALSA(
	input 		clk,
	input 		reset_n,


	input 	[4:0]		output_paddr,
	input 				output_penable,
	input 				output_pwrite,
	input  	[31:0]	output_pwdata,
	input 				output_psel,
	output 	[31:0]	output_prdata,
	output 				output_pready,

	input		[4:0]		clkctrl_paddr,
	input					clkctrl_penable,
	input					clkctrl_pwrite,
	input 	[31:0]	clkctrl_pwdata,
	input					clkctrl_psel,
	output 	[31:0]	clkctrl_prdata,
	output				clkctrl_pready,


	input					clk_48,
	input					clk_44,


	output 				playback_dma_req,
	input 				playback_dma_ack,

	output 				capture_dma_req,
	input 				capture_dma_ack,



	input						AUD_ADCDAT,
	inout						AUD_ADCLRCK,
	inout						AUD_BCLK,
	output					AUD_DACDAT,
	inout						AUD_DACLRCK,
	output					AUD_XCK

);


wire	clock_bridge_0_out_clk_clk;
wire 	clock_bridge_48_out_clk_clk;
wire 	clock_bridge_44_out_clk_clk;
assign clock_bridge_0_out_clk_clk = clk;
assign clock_bridge_48_out_clk_clk = clk_48;
assign clock_bridge_44_out_clk_clk = clk_44;



	wire	[63:0]	i2s_output_apb_0_playback_fifo_data;
	wire				i2s_output_apb_0_playback_fifo_read;
	wire				i2s_output_apb_0_playback_fifo_empty;
	wire				i2s_output_apb_0_playback_fifo_full;
	wire				i2s_output_apb_0_playback_fifo_clk;
	wire				i2s_output_apb_0_playback_dma_enable;
	wire				i2s_playback_enable;
	wire	[63:0]	i2s_output_apb_0_capture_fifo_data;
	wire				i2s_output_apb_0_capture_fifo_write;
	wire				i2s_output_apb_0_capture_fifo_empty;
	wire				i2s_output_apb_0_capture_fifo_full;
	wire				i2s_output_apb_0_capture_fifo_clk;
	wire				i2s_output_apb_0_capture_dma_enable;
	wire				i2s_capture_enable;

	wire				i2s_clkctrl_apb_0_ext_bclk;
	wire				i2s_clkctrl_apb_0_ext_playback_lrclk;
	wire				i2s_clkctrl_apb_0_ext_capture_lrclk;
	wire				i2s_clkctrl_apb_0_conduit_master_slave_mode;
	wire				i2s_clkctrl_apb_0_conduit_clk_sel_48_44;
	wire				i2s_clkctrl_apb_0_conduit_bclk;
	wire				i2s_clkctrl_apb_0_conduit_playback_lrclk;
	wire				i2s_clkctrl_apb_0_conduit_capture_lrclk;
	wire				i2s_clkctrl_apb_0_mclk_clk;





i2s_output_apb i2s_output_apb_inst(
	.clk(clk),
	.reset_n(reset_n),

	.paddr(output_paddr),
	.penable(output_penable),
	.pwrite(output_pwrite),
	.pwdata(output_pwdata),
	.psel(output_psel),
	.prdata(output_prdata),
	.pready(output_pready),

	.playback_fifo_data(i2s_output_apb_0_playback_fifo_data),
	.playback_fifo_read(i2s_output_apb_0_playback_fifo_read),
	.playback_fifo_empty(i2s_output_apb_0_playback_fifo_empty),
	.playback_fifo_full(i2s_output_apb_0_playback_fifo_full),
	.playback_fifo_clk(i2s_output_apb_0_playback_fifo_clk),

	.playback_dma_req(playback_dma_req),
	.playback_dma_ack(playback_dma_ack),
	.playback_dma_enable(i2s_output_apb_0_playback_dma_enable),

	.capture_fifo_data(i2s_output_apb_0_capture_fifo_data),
	.capture_fifo_write(i2s_output_apb_0_capture_fifo_write),
	.capture_fifo_empty(i2s_output_apb_0_capture_fifo_empty),
	.capture_fifo_full(i2s_output_apb_0_capture_fifo_full),
	.capture_fifo_clk(i2s_output_apb_0_capture_fifo_clk),

	.capture_dma_req(capture_dma_req),
	.capture_dma_ack(capture_dma_ack),
	.capture_dma_enable(i2s_output_apb_0_capture_dma_enable)
);




i2s_clkctrl_apb i2s_clkctrl_apb_inst(
	.clk(clk),
	.reset_n(reset_n),

	.paddr(clkctrl_paddr),
	.penable(clkctrl_penable),
	.pwrite(clkctrl_pwrite),
	.pwdata(clkctrl_pwdata),
	.psel(clkctrl_psel),
	.prdata(clkctrl_prdata),
	.pready(clkctrl_pready),

	.clk_48(clk_48),
	.clk_44(clk_44),

	.ext_bclk(i2s_clkctrl_apb_0_ext_bclk),
	.ext_playback_lrclk(i2s_clkctrl_apb_0_ext_playback_lrclk),
	.ext_capture_lrclk(i2s_clkctrl_apb_0_ext_capture_lrclk),
	.master_slave_mode(i2s_clkctrl_apb_0_conduit_master_slave_mode),

	.clk_sel_48_44(i2s_clkctrl_apb_0_conduit_clk_sel_48_44),
	.mclk(i2s_clkctrl_apb_0_mclk_clk),
	.bclk(i2s_clkctrl_apb_0_conduit_bclk),
	.playback_lrclk(i2s_clkctrl_apb_0_conduit_playback_lrclk),
	.capture_lrclk(i2s_clkctrl_apb_0_ext_capture_lrclk)
);


	wire i2s_playback_fifo_ack48;
	wire i2s_data_out48;
	i2s_shift_out i2s_shift_out48(
		.reset_n							(reset_n),
		.clk								(clock_bridge_48_out_clk_clk),

		.fifo_right_data					(i2s_output_apb_0_playback_fifo_data[63:32]),
		.fifo_left_data						(i2s_output_apb_0_playback_fifo_data[31:0]),
		.fifo_ready							(~i2s_output_apb_0_playback_fifo_empty),
		.fifo_ack							(i2s_playback_fifo_ack48),

		.enable								(i2s_playback_enable),
		.bclk								(i2s_clkctrl_apb_0_conduit_bclk),
		.lrclk								(i2s_clkctrl_apb_0_conduit_playback_lrclk),
		.data_out							(i2s_data_out48)
	);
	wire i2s_playback_fifo_ack44;
	wire i2s_data_out44;
	i2s_shift_out i2s_shift_out44(
		.reset_n							(reset_n),
		.clk								(clock_bridge_44_out_clk_clk),

		.fifo_right_data					(i2s_output_apb_0_playback_fifo_data[63:32]),
		.fifo_left_data						(i2s_output_apb_0_playback_fifo_data[31:0]),
		.fifo_ready							(~i2s_output_apb_0_playback_fifo_empty),
		.fifo_ack							(i2s_playback_fifo_ack44),

		.enable								(i2s_playback_enable),
		.bclk								(i2s_clkctrl_apb_0_conduit_bclk),
		.lrclk								(i2s_clkctrl_apb_0_conduit_playback_lrclk),
		.data_out							(i2s_data_out44)
	);

	wire i2s_capture_fifo_write48;
	wire i2s_data_in48;
	wire [63:0] i2s_capture_fifo_data48;
	i2s_shift_in i2s_shift_in48(
		.reset_n							(reset_n),
		.clk								(clock_bridge_48_out_clk_clk),

		.fifo_right_data					(i2s_capture_fifo_data48[63:32]),
		.fifo_left_data						(i2s_capture_fifo_data48[31:0]),
		.fifo_ready							(~i2s_output_apb_0_capture_fifo_full),
		.fifo_write							(i2s_capture_fifo_write48),

		.enable								(i2s_capture_enable),
		.bclk								(i2s_clkctrl_apb_0_conduit_bclk),
		.lrclk								(i2s_clkctrl_apb_0_conduit_capture_lrclk),
		.data_in							(i2s_data_in48)
	);
	wire i2s_capture_fifo_write44;
	wire i2s_data_in44;
	wire [63:0] i2s_capture_fifo_data44;
	i2s_shift_in i2s_shift_in44(
		.reset_n							(reset_n),
		.clk								(clock_bridge_44_out_clk_clk),

		.fifo_right_data					(i2s_capture_fifo_data44[63:32]),
		.fifo_left_data						(i2s_capture_fifo_data44[31:0]),
		.fifo_ready							(~i2s_output_apb_0_capture_fifo_full),
		.fifo_write							(i2s_capture_fifo_write44),

		.enable								(i2s_capture_enable),
		.bclk								(i2s_clkctrl_apb_0_conduit_bclk),
		.lrclk								(i2s_clkctrl_apb_0_conduit_capture_lrclk),
		.data_in							(i2s_data_in44)
	);


	assign AUD_XCK = i2s_clkctrl_apb_0_mclk_clk;
	assign i2s_playback_enable = i2s_output_apb_0_playback_dma_enable & ~i2s_output_apb_0_playback_fifo_empty;
	assign i2s_capture_enable = i2s_output_apb_0_capture_dma_enable & ~i2s_output_apb_0_capture_fifo_full;


	reg [2:0] i2s_playback_fifo_ack_synchro;
    wire i2s_playback_fifo_ack;
	assign i2s_playback_fifo_ack = i2s_clkctrl_apb_0_conduit_clk_sel_48_44 ?
		i2s_playback_fifo_ack44 : i2s_playback_fifo_ack48;
	always @(posedge clock_bridge_0_out_clk_clk or negedge reset_n)
		if (~reset_n)
			i2s_playback_fifo_ack_synchro <= 0;
		else
			i2s_playback_fifo_ack_synchro <= {i2s_playback_fifo_ack_synchro[1:0], i2s_playback_fifo_ack};
	assign i2s_output_apb_0_playback_fifo_read = i2s_playback_fifo_ack_synchro[2] & ~i2s_playback_fifo_ack_synchro[1];
	assign i2s_output_apb_0_playback_fifo_clk = clock_bridge_0_out_clk_clk;


	reg [2:0] i2s_capture_fifo_write_synchro;
    wire i2s_capture_fifo_write;
	assign i2s_capture_fifo_write = i2s_clkctrl_apb_0_conduit_clk_sel_48_44 ?
		i2s_capture_fifo_write44 : i2s_capture_fifo_write48;
	always @(posedge clock_bridge_0_out_clk_clk or negedge reset_n)
		if (~reset_n)
			i2s_capture_fifo_write_synchro <= 0;
		else
			i2s_capture_fifo_write_synchro <= {i2s_capture_fifo_write_synchro[1:0], i2s_capture_fifo_write};
	assign i2s_output_apb_0_capture_fifo_write = i2s_capture_fifo_write_synchro[2] & ~i2s_capture_fifo_write_synchro[1];
	assign i2s_output_apb_0_capture_fifo_clk = clock_bridge_0_out_clk_clk;


	assign i2s_output_apb_0_capture_fifo_data = i2s_clkctrl_apb_0_conduit_clk_sel_48_44 ?
		i2s_capture_fifo_data48 : i2s_capture_fifo_data44;


	assign AUD_DACDAT = i2s_clkctrl_apb_0_conduit_clk_sel_48_44 ? i2s_data_out44 : i2s_data_out48;


	assign i2s_data_in44 = AUD_ADCDAT;
	assign i2s_data_in48 = AUD_ADCDAT;




	assign AUD_BCLK = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_bclk : 1'bZ;
	assign AUD_DACLRCK = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_playback_lrclk : 1'bZ;
	assign AUD_ADCLRCK = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_capture_lrclk : 1'bZ;

	assign i2s_clkctrl_apb_0_ext_bclk = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_bclk : AUD_BCLK;
	assign i2s_clkctrl_apb_0_ext_playback_lrclk = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_playback_lrclk : AUD_DACLRCK;
	assign i2s_clkctrl_apb_0_ext_capture_lrclk = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_capture_lrclk : AUD_DACLRCK;





endmodule
module TERASIC_ALSA(
	input 		clk,
	input 		reset_n,


	input 	[4:0]		output_paddr,
	input 				output_penable,
	input 				output_pwrite,
	input  	[31:0]	output_pwdata,
	input 				output_psel,
	output 	[31:0]	output_prdata,
	output 				output_pready,

	input		[4:0]		clkctrl_paddr,
	input					clkctrl_penable,
	input					clkctrl_pwrite,
	input 	[31:0]	clkctrl_pwdata,
	input					clkctrl_psel,
	output 	[31:0]	clkctrl_prdata,
	output				clkctrl_pready,


	input					clk_48,
	input					clk_44,


	output 				playback_dma_req,
	input 				playback_dma_ack,

	output 				capture_dma_req,
	input 				capture_dma_ack,



	input						AUD_ADCDAT,
	inout						AUD_ADCLRCK,
	inout						AUD_BCLK,
	output					AUD_DACDAT,
	inout						AUD_DACLRCK,
	output					AUD_XCK

);



wire	clock_bridge_0_out_clk_clk;
wire 	clock_bridge_48_out_clk_clk;
wire 	clock_bridge_44_out_clk_clk;
assign clock_bridge_0_out_clk_clk = clk;
assign clock_bridge_48_out_clk_clk = clk_48;
assign clock_bridge_44_out_clk_clk = clk_44;



	wire	[63:0]	i2s_output_apb_0_playback_fifo_data;
	wire				i2s_output_apb_0_playback_fifo_read;
	wire				i2s_output_apb_0_playback_fifo_empty;
	wire				i2s_output_apb_0_playback_fifo_full;
	wire				i2s_output_apb_0_playback_fifo_clk;
	wire				i2s_output_apb_0_playback_dma_enable;
	wire				i2s_playback_enable;
	wire	[63:0]	i2s_output_apb_0_capture_fifo_data;
	wire				i2s_output_apb_0_capture_fifo_write;
	wire				i2s_output_apb_0_capture_fifo_empty;
	wire				i2s_output_apb_0_capture_fifo_full;
	wire				i2s_output_apb_0_capture_fifo_clk;
	wire				i2s_output_apb_0_capture_dma_enable;
	wire				i2s_capture_enable;

	wire				i2s_clkctrl_apb_0_ext_bclk;
	wire				i2s_clkctrl_apb_0_ext_playback_lrclk;
	wire				i2s_clkctrl_apb_0_ext_capture_lrclk;
	wire				i2s_clkctrl_apb_0_conduit_master_slave_mode;
	wire				i2s_clkctrl_apb_0_conduit_clk_sel_48_44;
	wire				i2s_clkctrl_apb_0_conduit_bclk;
	wire				i2s_clkctrl_apb_0_conduit_playback_lrclk;
	wire				i2s_clkctrl_apb_0_conduit_capture_lrclk;
	wire				i2s_clkctrl_apb_0_mclk_clk;





i2s_output_apb i2s_output_apb_inst(
	.clk(clk),
	.reset_n(reset_n),

	.paddr(output_paddr),
	.penable(output_penable),
	.pwrite(output_pwrite),
	.pwdata(output_pwdata),
	.psel(output_psel),
	.prdata(output_prdata),
	.pready(output_pready),

	.playback_fifo_data(i2s_output_apb_0_playback_fifo_data),
	.playback_fifo_read(i2s_output_apb_0_playback_fifo_read),
	.playback_fifo_empty(i2s_output_apb_0_playback_fifo_empty),
	.playback_fifo_full(i2s_output_apb_0_playback_fifo_full),
	.playback_fifo_clk(i2s_output_apb_0_playback_fifo_clk),

	.playback_dma_req(playback_dma_req),
	.playback_dma_ack(playback_dma_ack),
	.playback_dma_enable(i2s_output_apb_0_playback_dma_enable),

	.capture_fifo_data(i2s_output_apb_0_capture_fifo_data),
	.capture_fifo_write(i2s_output_apb_0_capture_fifo_write),
	.capture_fifo_empty(i2s_output_apb_0_capture_fifo_empty),
	.capture_fifo_full(i2s_output_apb_0_capture_fifo_full),
	.capture_fifo_clk(i2s_output_apb_0_capture_fifo_clk),

	.capture_dma_req(capture_dma_req),
	.capture_dma_ack(capture_dma_ack),
	.capture_dma_enable(i2s_output_apb_0_capture_dma_enable)
);




i2s_clkctrl_apb i2s_clkctrl_apb_inst(
	.clk(clk),
	.reset_n(reset_n),

	.paddr(clkctrl_paddr),
	.penable(clkctrl_penable),
	.pwrite(clkctrl_pwrite),
	.pwdata(clkctrl_pwdata),
	.psel(clkctrl_psel),
	.prdata(clkctrl_prdata),
	.pready(clkctrl_pready),

	.clk_48(clk_48),
	.clk_44(clk_44),

	.ext_bclk(i2s_clkctrl_apb_0_ext_bclk),
	.ext_playback_lrclk(i2s_clkctrl_apb_0_ext_playback_lrclk),
	.ext_capture_lrclk(i2s_clkctrl_apb_0_ext_capture_lrclk),
	.master_slave_mode(i2s_clkctrl_apb_0_conduit_master_slave_mode),

	.clk_sel_48_44(i2s_clkctrl_apb_0_conduit_clk_sel_48_44),
	.mclk(i2s_clkctrl_apb_0_mclk_clk),
	.bclk(i2s_clkctrl_apb_0_conduit_bclk),
	.playback_lrclk(i2s_clkctrl_apb_0_conduit_playback_lrclk),
	.capture_lrclk(i2s_clkctrl_apb_0_ext_capture_lrclk)
);


	wire i2s_playback_fifo_ack48;
	wire i2s_data_out48;
	i2s_shift_out i2s_shift_out48(
		.reset_n							(reset_n),
		.clk								(clock_bridge_48_out_clk_clk),

		.fifo_right_data					(i2s_output_apb_0_playback_fifo_data[63:32]),
		.fifo_left_data						(i2s_output_apb_0_playback_fifo_data[31:0]),
		.fifo_ready							(~i2s_output_apb_0_playback_fifo_empty),
		.fifo_ack							(i2s_playback_fifo_ack48),

		.enable								(i2s_playback_enable),
		.bclk								(i2s_clkctrl_apb_0_conduit_bclk),
		.lrclk								(i2s_clkctrl_apb_0_conduit_playback_lrclk),
		.data_out							(i2s_data_out48)
	);
	wire i2s_playback_fifo_ack44;
	wire i2s_data_out44;
	i2s_shift_out i2s_shift_out44(
		.reset_n							(reset_n),
		.clk								(clock_bridge_44_out_clk_clk),

		.fifo_right_data					(i2s_output_apb_0_playback_fifo_data[63:32]),
		.fifo_left_data						(i2s_output_apb_0_playback_fifo_data[31:0]),
		.fifo_ready							(~i2s_output_apb_0_playback_fifo_empty),
		.fifo_ack							(i2s_playback_fifo_ack44),

		.enable								(i2s_playback_enable),
		.bclk								(i2s_clkctrl_apb_0_conduit_bclk),
		.lrclk								(i2s_clkctrl_apb_0_conduit_playback_lrclk),
		.data_out							(i2s_data_out44)
	);

	wire i2s_capture_fifo_write48;
	wire i2s_data_in48;
	wire [63:0] i2s_capture_fifo_data48;
	i2s_shift_in i2s_shift_in48(
		.reset_n							(reset_n),
		.clk								(clock_bridge_48_out_clk_clk),

		.fifo_right_data					(i2s_capture_fifo_data48[63:32]),
		.fifo_left_data						(i2s_capture_fifo_data48[31:0]),
		.fifo_ready							(~i2s_output_apb_0_capture_fifo_full),
		.fifo_write							(i2s_capture_fifo_write48),

		.enable								(i2s_capture_enable),
		.bclk								(i2s_clkctrl_apb_0_conduit_bclk),
		.lrclk								(i2s_clkctrl_apb_0_conduit_capture_lrclk),
		.data_in							(i2s_data_in48)
	);
	wire i2s_capture_fifo_write44;
	wire i2s_data_in44;
	wire [63:0] i2s_capture_fifo_data44;
	i2s_shift_in i2s_shift_in44(
		.reset_n							(reset_n),
		.clk								(clock_bridge_44_out_clk_clk),

		.fifo_right_data					(i2s_capture_fifo_data44[63:32]),
		.fifo_left_data						(i2s_capture_fifo_data44[31:0]),
		.fifo_ready							(~i2s_output_apb_0_capture_fifo_full),
		.fifo_write							(i2s_capture_fifo_write44),

		.enable								(i2s_capture_enable),
		.bclk								(i2s_clkctrl_apb_0_conduit_bclk),
		.lrclk								(i2s_clkctrl_apb_0_conduit_capture_lrclk),
		.data_in							(i2s_data_in44)
	);


	assign AUD_XCK = i2s_clkctrl_apb_0_mclk_clk;
	assign i2s_playback_enable = i2s_output_apb_0_playback_dma_enable & ~i2s_output_apb_0_playback_fifo_empty;
	assign i2s_capture_enable = i2s_output_apb_0_capture_dma_enable & ~i2s_output_apb_0_capture_fifo_full;


	reg [2:0] i2s_playback_fifo_ack_synchro;
    wire i2s_playback_fifo_ack;
	assign i2s_playback_fifo_ack = i2s_clkctrl_apb_0_conduit_clk_sel_48_44 ?
		i2s_playback_fifo_ack44 : i2s_playback_fifo_ack48;
	always @(posedge clock_bridge_0_out_clk_clk or negedge reset_n)
		if (~reset_n)
			i2s_playback_fifo_ack_synchro <= 0;
		else
			i2s_playback_fifo_ack_synchro <= {i2s_playback_fifo_ack_synchro[1:0], i2s_playback_fifo_ack};
	assign i2s_output_apb_0_playback_fifo_read = i2s_playback_fifo_ack_synchro[2] & ~i2s_playback_fifo_ack_synchro[1];
	assign i2s_output_apb_0_playback_fifo_clk = clock_bridge_0_out_clk_clk;


	reg [2:0] i2s_capture_fifo_write_synchro;
    wire i2s_capture_fifo_write;
	assign i2s_capture_fifo_write = i2s_clkctrl_apb_0_conduit_clk_sel_48_44 ?
		i2s_capture_fifo_write44 : i2s_capture_fifo_write48;
	always @(posedge clock_bridge_0_out_clk_clk or negedge reset_n)
		if (~reset_n)
			i2s_capture_fifo_write_synchro <= 0;
		else
			i2s_capture_fifo_write_synchro <= {i2s_capture_fifo_write_synchro[1:0], i2s_capture_fifo_write};
	assign i2s_output_apb_0_capture_fifo_write = i2s_capture_fifo_write_synchro[2] & ~i2s_capture_fifo_write_synchro[1];
	assign i2s_output_apb_0_capture_fifo_clk = clock_bridge_0_out_clk_clk;


	assign i2s_output_apb_0_capture_fifo_data = i2s_clkctrl_apb_0_conduit_clk_sel_48_44 ?
		i2s_capture_fifo_data48 : i2s_capture_fifo_data44;


	assign AUD_DACDAT = i2s_clkctrl_apb_0_conduit_clk_sel_48_44 ? i2s_data_out44 : i2s_data_out48;


	assign i2s_data_in44 = AUD_ADCDAT;
	assign i2s_data_in48 = AUD_ADCDAT;




	assign AUD_BCLK = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_bclk : 1'bZ;
	assign AUD_DACLRCK = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_playback_lrclk : 1'bZ;
	assign AUD_ADCLRCK = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_capture_lrclk : 1'bZ;

	assign i2s_clkctrl_apb_0_ext_bclk = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_bclk : AUD_BCLK;
	assign i2s_clkctrl_apb_0_ext_playback_lrclk = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_playback_lrclk : AUD_DACLRCK;
	assign i2s_clkctrl_apb_0_ext_capture_lrclk = i2s_clkctrl_apb_0_conduit_master_slave_mode ?
		i2s_clkctrl_apb_0_conduit_capture_lrclk : AUD_DACLRCK;





endmodule