data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:21: Operator AND expects 64 bits on the LHS, but LHS\'s VARREF \'rs\' generates 32 bits.\n                                                                                : ... In instance ALU\n  saida = rs & rt;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:21: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'rt\' generates 32 bits.\n                                                                                : ... In instance ALU\n  saida = rs & rt;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:23: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'rs\' generates 32 bits.\n                                                                                : ... In instance ALU\n  saida = rs | rt;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:23: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'rt\' generates 32 bits.\n                                                                                : ... In instance ALU\n  saida = rs | rt;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:25: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'rs\' generates 32 bits.\n                                                                                : ... In instance ALU\n  saida = rs + rt;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:25: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'rt\' generates 32 bits.\n                                                                                : ... In instance ALU\n  saida = rs + rt;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:29: Operator DIV expects 64 bits on the LHS, but LHS\'s VARREF \'rs\' generates 32 bits.\n                                                                                : ... In instance ALU\n  saida = rs / rt;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:29: Operator DIV expects 64 bits on the RHS, but RHS\'s VARREF \'rt\' generates 32 bits.\n                                                                                : ... In instance ALU\n  saida = rs / rt;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:31: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'rs\' generates 32 bits.\n                                                                                : ... In instance ALU\n  saida = rs - rt;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:31: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'rt\' generates 32 bits.\n                                                                                : ... In instance ALU\n  saida = rs - rt;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:33: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                                : ... In instance ALU\n  saida = (rs < rt);  \n        ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:43: Operator EQ expects 64 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                : ... In instance ALU\n  if(saida == 1\'b0)\n           ^~\n%Error: Exiting due to 12 warning(s)\n'
module ALU(input[31:0] rs, rt, input[2:0] sinalOperacao,output[31:0] resultado, output zero, overflow);





reg [63:0] saida;
reg over, tzero;
	always @ *
	case (sinalOperacao)
	3'b000:
		saida = rs & rt;
	3'b001:
		saida = rs | rt;
	3'b010:
		saida = rs + rt;
	3'b011:
		saida = rs * rt;
	3'b100:
		saida = rs / rt;
	3'b110:
		saida = rs - rt;
	3'b111:
		saida = (rs < rt);

	endcase

	always @ ( * ) begin

		if(saida[63:32] > 32'b0)
			over = 1'b1;
		else
			over = 1'b0;
		if(saida == 1'b0)
			tzero = 1'b1;
		else
			tzero = 1'b0;

	end

assign resultado = saida[31:0];
assign overflow = over;
assign zero = tzero;

endmodule
module ALU(input[31:0] rs, rt, input[2:0] sinalOperacao,output[31:0] resultado, output zero, overflow);






reg [63:0] saida;
reg over, tzero;
	always @ *
	case (sinalOperacao)
	3'b000:
		saida = rs & rt;
	3'b001:
		saida = rs | rt;
	3'b010:
		saida = rs + rt;
	3'b011:
		saida = rs * rt;
	3'b100:
		saida = rs / rt;
	3'b110:
		saida = rs - rt;
	3'b111:
		saida = (rs < rt);

	endcase

	always @ ( * ) begin

		if(saida[63:32] > 32'b0)
			over = 1'b1;
		else
			over = 1'b0;
		if(saida == 1'b0)
			tzero = 1'b1;
		else
			tzero = 1'b0;

	end

assign resultado = saida[31:0];
assign overflow = over;
assign zero = tzero;

endmodule