data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Hybrid/Hybrid.v
1: b'%Error: Cannot find file containing module: Project/SourceCode/Hybrid,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Hybrid,data/full_repos/permissive/119107706\n             Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Hybrid/Hybrid.v\n%Error: Exiting due to 3 error(s)\n'
module Hybrid
		#(	parameter WL = 24,
						 LUT_bits = 26,
						 LUT_addWidth = 11,
						 dWL = 27,
						 p = 1,
						 LUT_capacity = 2**(LUT_addWidth+p)
		 )
		(
			input CLK, nRST,
			input CE,
			input [WL-1:0] din,
			input [1:0]	FUNCTION,
			output reg [WL-1:0] dout
		);		 
		

		reg  [LUT_bits-1 : 0]     LUT_rec 	[LUT_capacity-1 : 0];
		reg  [LUT_bits-1 : 0]	  LUT_sqrt  [LUT_capacity-1 : 0];
		reg  [LUT_bits-1 : 0]	  LUT_isqt  [LUT_capacity-1 : 0];


		reg  [LUT_bits-1 : 0]	  iniValue;
		reg  [LUT_addWidth:0]     reg_cmp;
		reg  [dWL-1:0] oneFP =  0;
		reg  [dWL-1:0] xopow;
		wire [dWL-1:0] xopow_wire;
		wire [dWL-1:0] xopow_net;
		wire [dWL-1:0] ini_net;
		wire [dWL-1:0] mul2_net;
		reg  [dWL-1:0] ini = 0;
		wire [dWL-1:0] input_mul1;
		wire  [WL-1:0]  tmp_result;
		reg  [dWL-1:0] iniFP;
		reg  [WL-LUT_addWidth-1:0] xo;
		reg	Sel;

integer pointer;		


		always @ (posedge CLK) begin
			if(~nRST) begin
					Sel <= 1'b0;
					pointer <= 0;
					ini <= 0;
					iniFP <= 0;
			end
			else begin
				if (CE) begin
					xopow <= xopow_net;
					if (pointer == p) begin

						dout <= tmp_result;
						pointer <= 0;
						Sel <= 1'b0;
						ini <= 0;
					end else begin
						pointer <= pointer + 1;
						Sel <= 1'b1;
						ini <= ini_net;
					end
				end
			end
		end	

		always @* begin
			if(~nRST) begin
				reg_cmp <= 0;
				iniValue <= 0;
				oneFP[dWL-2] <= 1'b1;
				xo <= 0;
			end else begin
				if (CE) begin
					reg_cmp  <= din[WL-2-1 : WL-1-LUT_addWidth-1];
					if (FUNCTION == 2'b00)
						iniValue <= LUT_rec[reg_cmp + pointer*(2**LUT_addWidth)];
					else if (FUNCTION == 2'b01)
						iniValue <= LUT_sqrt[reg_cmp + pointer*(2**LUT_addWidth)];
					else
						iniValue <= LUT_isqt[reg_cmp + pointer*(2**LUT_addWidth)];
					
					xo <= din[WL-2-LUT_addWidth-1:0];
				end
			end
		end		

multiplexer #(.N(dWL)) Sel_input_mux (.a(oneFP),.b(xopow),.Sel(Sel),.out(input_mul1));	

sMult #(.WI1(2), .WF1(WL-LUT_addWidth-2), .WI2(2), .WF2(dWL-2), .WIO(2), .WFO(dWL-2)) multiplier_1 
				   (.CLK(CLK), .RST(nRST), .in1(xo), .in2(input_mul1), .out(xopow_net));		
					
sMult #(.WI1(2), .WF1(LUT_bits-2), .WI2(2), .WF2(dWL-2), .WIO(2), .WFO(dWL-2)) multiplier_2 
				   (.CLK(CLK), .RST(nRST), .in1(iniValue), .in2(input_mul1), .out(mul2_net));

sAdd 		#(	.WI1(2),
				.WF1(dWL-2),
				.WI2(2),
				.WF2(dWL-2),
				.WIO(2),
				.WFO(dWL-2)) 	Fang_fixed_adder 
			 ( .CLK(CLK), .RST(nRST), .in1(mul2_net), .in2(ini), .out(ini_net));





	ux_round2nearest
		#(
			.WordLength(dWL),
			.RoundLength(dWL-WL)
		 )
	Fang_round 
		(
			.CLK(CLK),
			.RESET(RST),
			.CE(CE),
			.x(ini_net),
			.y(tmp_result)
		 );	

	
endmodule
module Hybrid
		#(	parameter WL = 24,
						 LUT_bits = 26,
						 LUT_addWidth = 11,
						 dWL = 27,
						 p = 1,
						 LUT_capacity = 2**(LUT_addWidth+p)
		 )
		(
			input CLK, nRST,
			input CE,
			input [WL-1:0] din,
			input [1:0]	FUNCTION,
			output reg [WL-1:0] dout
		);
		 
		

		reg  [LUT_bits-1 : 0]     LUT_rec 	[LUT_capacity-1 : 0];
		reg  [LUT_bits-1 : 0]	  LUT_sqrt  [LUT_capacity-1 : 0];
		reg  [LUT_bits-1 : 0]	  LUT_isqt  [LUT_capacity-1 : 0];


		reg  [LUT_bits-1 : 0]	  iniValue;
		reg  [LUT_addWidth:0]     reg_cmp;
		reg  [dWL-1:0] oneFP =  0;
		reg  [dWL-1:0] xopow;
		wire [dWL-1:0] xopow_wire;
		wire [dWL-1:0] xopow_net;
		wire [dWL-1:0] ini_net;
		wire [dWL-1:0] mul2_net;
		reg  [dWL-1:0] ini = 0;
		wire [dWL-1:0] input_mul1;
		wire  [WL-1:0]  tmp_result;
		reg  [dWL-1:0] iniFP;
		reg  [WL-LUT_addWidth-1:0] xo;
		reg	Sel;

integer pointer;		


		always @ (posedge CLK) begin
			if(~nRST) begin
					Sel <= 1'b0;
					pointer <= 0;
					ini <= 0;
					iniFP <= 0;
			end
			else begin
				if (CE) begin
					xopow <= xopow_net;
					if (pointer == p) begin

						dout <= tmp_result;
						pointer <= 0;
						Sel <= 1'b0;
						ini <= 0;
					end else begin
						pointer <= pointer + 1;
						Sel <= 1'b1;
						ini <= ini_net;
					end
				end
			end
		end	

		always @* begin
			if(~nRST) begin
				reg_cmp <= 0;
				iniValue <= 0;
				oneFP[dWL-2] <= 1'b1;
				xo <= 0;
			end else begin
				if (CE) begin
					reg_cmp  <= din[WL-2-1 : WL-1-LUT_addWidth-1];
					if (FUNCTION == 2'b00)
						iniValue <= LUT_rec[reg_cmp + pointer*(2**LUT_addWidth)];
					else if (FUNCTION == 2'b01)
						iniValue <= LUT_sqrt[reg_cmp + pointer*(2**LUT_addWidth)];
					else
						iniValue <= LUT_isqt[reg_cmp + pointer*(2**LUT_addWidth)];
					
					xo <= din[WL-2-LUT_addWidth-1:0];
				end
			end
		end		

multiplexer #(.N(dWL)) Sel_input_mux (.a(oneFP),.b(xopow),.Sel(Sel),.out(input_mul1));	

sMult #(.WI1(2), .WF1(WL-LUT_addWidth-2), .WI2(2), .WF2(dWL-2), .WIO(2), .WFO(dWL-2)) multiplier_1 
				   (.CLK(CLK), .RST(nRST), .in1(xo), .in2(input_mul1), .out(xopow_net));		
					
sMult #(.WI1(2), .WF1(LUT_bits-2), .WI2(2), .WF2(dWL-2), .WIO(2), .WFO(dWL-2)) multiplier_2 
				   (.CLK(CLK), .RST(nRST), .in1(iniValue), .in2(input_mul1), .out(mul2_net));

sAdd 		#(	.WI1(2),
				.WF1(dWL-2),
				.WI2(2),
				.WF2(dWL-2),
				.WIO(2),
				.WFO(dWL-2)) 	Fang_fixed_adder 
			 ( .CLK(CLK), .RST(nRST), .in1(mul2_net), .in2(ini), .out(ini_net));





	ux_round2nearest
		#(
			.WordLength(dWL),
			.RoundLength(dWL-WL)
		 )
	Fang_round 
		(
			.CLK(CLK),
			.RESET(RST),
			.CE(CE),
			.x(ini_net),
			.y(tmp_result)
		 );	

	
endmodule