data/full_repos/permissive/147086086/Lab0/hw/logic_elements.v
data/verilator_xmls/d3073a19-dcc7-45cb-896d-2bc8d20bc3f0.xml
module logic_elements(SW, LEDR);

input   [9:0]   SW;
output  [9:0]   LEDR;

wire    [9:0]   y;
wire    [9:0]   x;

assign LEDR = y;
assign x = SW;

assign y[0] = ~x[0];

assign y[1] = x[0] & x[1];

assign y[2] = ~(x[0] & x[1]);

assign y[3] = x[0] | x[1];

assign y[4] = ~(x[0] | x[1]);

assign y[5] = x[0] ^ x[1];

assign y[9:6] = 4'b1010;

endmodule
module logic_elements(SW, LEDR);


input   [9:0]   SW;
output  [9:0]   LEDR;

wire    [9:0]   y;
wire    [9:0]   x;

assign LEDR = y;
assign x = SW;

assign y[0] = ~x[0];

assign y[1] = x[0] & x[1];

assign y[2] = ~(x[0] & x[1]);

assign y[3] = x[0] | x[1];

assign y[4] = ~(x[0] | x[1]);

assign y[5] = x[0] ^ x[1];

assign y[9:6] = 4'b1010;

endmodule