data/full_repos/permissive/173670949/blinkcycle/tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/173670949/blinkcycle/tb.v:7: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/173670949/blinkcycle/tb.v:8: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, top_inst);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/173670949/blinkcycle/tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #1_000_000_000;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173670949/blinkcycle/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk <= !clk;\n           ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, top_inst);
        #1_000_000_000;
        $finish;
    end

    reg clk = 0;
    always #1 clk <= !clk;

    wire rled1;
    wire rled2;
    wire rled3;
    wire rled4;
    wire gled5;
    top top_inst(clk, rled1, rled2, rled3, rled4, gled5);

endmodule
module tb();


    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, top_inst);
        #1_000_000_000;
        $finish;
    end

    reg clk = 0;
    always #1 clk <= !clk;

    wire rled1;
    wire rled2;
    wire rled3;
    wire rled4;
    wire gled5;
    top top_inst(clk, rled1, rled2, rled3, rled4, gled5);

endmodule