data/full_repos/permissive/170402453/RS232.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170402453/RS232.v:69: Bit extraction of var[7:0] requires 3 bit index, not 6 bits.\n                                                               : ... In instance RS232\n    RXData_[ReceiveCounter] <= (Majority > 2);\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/170402453/RS232.v:118: Bit extraction of var[7:0] requires 3 bit index, not 6 bits.\n                                                                : ... In instance RS232\n    TX_ <= ~TXData[SendingCounter];\n                  ^\n%Error: Exiting due to 2 warning(s)\n'
module RS232(
	 input CLK,
    input RX,
    output TX,
    output ReceiveCLK,
	 input sendCLK,
	 output [7:0] RXData,
	 input [7:0] TXData
    );
	 
	 reg ReceiveCLK_, TX_;
	 reg [7:0] RXData_;
	 reg Receiving, Sending;
	 reg [5:0] ReceiveCounter, SendingCounter;
	 

	 reg [2:0] Majority, MajorityCounter, MajorityCounter2;
	 reg TSet;
	 
	 initial begin
		ReceiveCLK_ = 0;
		RXData_ = 0;
		Receiving = 0;
		ReceiveCounter = 0;
		Sending = 0;
		SendingCounter = 0;
		Majority=0;
		MajorityCounter=0;
		MajorityCounter2=0;
		TSet=0;
		TX_ = 0;
	 end
	 
	 assign ReceiveCLK = ReceiveCLK_;
	 assign RXData = ~RXData_;
	 assign TX = TX_;
	 


	 always @ (posedge CLK) begin
		ReceiveCLK_ <= 0;
	 
	   if(Receiving) begin
			TSet <= 0;
			if(MajorityCounter >= 4) begin
				MajorityCounter <= 0;

				RXData_[ReceiveCounter] <= (Majority > 2);

				

				if(ReceiveCounter >= 7) begin
					ReceiveCounter <= 0;
					Receiving <= 0;
					ReceiveCLK_ <= 1;

				end else ReceiveCounter <= ReceiveCounter + 1;
				
				Majority <= 0;
			end else begin
				MajorityCounter <= MajorityCounter+1;
				Majority <= (RX) ? Majority+1 : Majority;
			end
		end
		

		TSet <= (~Receiving && RX) ? 1 : TSet;
		if(TSet)	begin
			if(MajorityCounter >= 4) begin
				MajorityCounter <= 0;
				
				ReceiveCounter <= 0;
				RXData_ <= 0;
				Receiving <= 1;
				Majority <= 0;
				TSet <= 0;
			end else begin
				MajorityCounter <= MajorityCounter+1;
			end
		end
	 end
	 
	 


	 always @(negedge CLK) begin
		if(sendCLK && ~Sending) begin
			TX_ <= 1;
			SendingCounter <= 0;
			Sending <= 1;
		end
		

		if(Sending) begin
			if(MajorityCounter2 >= 4) begin
				MajorityCounter2 <= 0;
				TX_ <= ~TXData[SendingCounter];

				

				if(SendingCounter >= 8) begin
					SendingCounter <= 0;
					Sending <= 0;
					TX_ <= 0;

				end else SendingCounter <= SendingCounter + 1;
			end else begin
				MajorityCounter2 <= MajorityCounter2+1; 
			end
		end
	end
endmodule
module RS232(
	 input CLK,
    input RX,
    output TX,
    output ReceiveCLK,
	 input sendCLK,
	 output [7:0] RXData,
	 input [7:0] TXData
    );

	 
	 reg ReceiveCLK_, TX_;
	 reg [7:0] RXData_;
	 reg Receiving, Sending;
	 reg [5:0] ReceiveCounter, SendingCounter;
	 

	 reg [2:0] Majority, MajorityCounter, MajorityCounter2;
	 reg TSet;
	 
	 initial begin
		ReceiveCLK_ = 0;
		RXData_ = 0;
		Receiving = 0;
		ReceiveCounter = 0;
		Sending = 0;
		SendingCounter = 0;
		Majority=0;
		MajorityCounter=0;
		MajorityCounter2=0;
		TSet=0;
		TX_ = 0;
	 end
	 
	 assign ReceiveCLK = ReceiveCLK_;
	 assign RXData = ~RXData_;
	 assign TX = TX_;
	 


	 always @ (posedge CLK) begin
		ReceiveCLK_ <= 0;
	 
	   if(Receiving) begin
			TSet <= 0;
			if(MajorityCounter >= 4) begin
				MajorityCounter <= 0;

				RXData_[ReceiveCounter] <= (Majority > 2);

				

				if(ReceiveCounter >= 7) begin
					ReceiveCounter <= 0;
					Receiving <= 0;
					ReceiveCLK_ <= 1;

				end else ReceiveCounter <= ReceiveCounter + 1;
				
				Majority <= 0;
			end else begin
				MajorityCounter <= MajorityCounter+1;
				Majority <= (RX) ? Majority+1 : Majority;
			end
		end
		

		TSet <= (~Receiving && RX) ? 1 : TSet;
		if(TSet)	begin
			if(MajorityCounter >= 4) begin
				MajorityCounter <= 0;
				
				ReceiveCounter <= 0;
				RXData_ <= 0;
				Receiving <= 1;
				Majority <= 0;
				TSet <= 0;
			end else begin
				MajorityCounter <= MajorityCounter+1;
			end
		end
	 end
	 
	 


	 always @(negedge CLK) begin
		if(sendCLK && ~Sending) begin
			TX_ <= 1;
			SendingCounter <= 0;
			Sending <= 1;
		end
		

		if(Sending) begin
			if(MajorityCounter2 >= 4) begin
				MajorityCounter2 <= 0;
				TX_ <= ~TXData[SendingCounter];

				

				if(SendingCounter >= 8) begin
					SendingCounter <= 0;
					Sending <= 0;
					TX_ <= 0;

				end else SendingCounter <= SendingCounter + 1;
			end else begin
				MajorityCounter2 <= MajorityCounter2+1; 
			end
		end
	end
endmodule