data/full_repos/permissive/211316121/lab7_1_nexys4/Traffic.v
data/verilator_xmls/ca577149-9261-4fa3-876c-03fa47d393ac.xml
module Traffic(
input sec5,
input sec10,
input clk,
input clr,
output [5:0] lights,
output reg reset
);
parameter GR=6'b0_0_1_1_0_0,
           YR=6'b0_1_0_1_0_0,
           RG=6'b1_0_0_0_0_1,
           RY=6'b1_0_0_0_1_0;
reg [5:0] state;

always@(posedge clk)
begin
if(clr) begin state<=GR;reset<=1; end
else
    begin
    reset<=0;
        case(state)
            GR:if(sec10) begin state<=YR;reset<=1;end
            YR:if(sec5) begin state<=RG;reset<=1;end
            RG:if(sec10) begin state<=RY;reset<=1;end
            RY:if(sec5) begin state<=GR;reset<=1;end
            default:     begin state<=GR;reset<=1;end
        endcase
    end
end

assign lights=state;
endmodule
module Traffic(
input sec5,
input sec10,
input clk,
input clr,
output [5:0] lights,
output reg reset
);

parameter GR=6'b0_0_1_1_0_0,
           YR=6'b0_1_0_1_0_0,
           RG=6'b1_0_0_0_0_1,
           RY=6'b1_0_0_0_1_0;
reg [5:0] state;

always@(posedge clk)
begin
if(clr) begin state<=GR;reset<=1; end
else
    begin
    reset<=0;
        case(state)
            GR:if(sec10) begin state<=YR;reset<=1;end
            YR:if(sec5) begin state<=RG;reset<=1;end
            RG:if(sec10) begin state<=RY;reset<=1;end
            RY:if(sec5) begin state<=GR;reset<=1;end
            default:     begin state<=GR;reset<=1;end
        endcase
    end
end

assign lights=state;
endmodule