data/full_repos/permissive/117337560/primitive_logic_gates/AND/and_user_defined_model.v
 line:1: before: "primitive"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117337560/primitive_logic_gates/AND/and_user_defined_model.v:26: Unsupported: Ignoring delay on this delayed statement.\n     #100 a=1;b=0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117337560/primitive_logic_gates/AND/and_user_defined_model.v:27: Unsupported: Ignoring delay on this delayed statement.\n     #100 a=0;b=1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/primitive_logic_gates/AND/and_user_defined_model.v:28: Unsupported: Ignoring delay on this delayed statement.\n     #100 a=1;b=1;\n     ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module and_user_defined_model(c,a,b);
    output c;
    input a,b;
    my_and g(c,a,b);
endmodule
module and_user_defined_model(c,a,b);

    output c;
    input a,b;
    my_and g(c,a,b);
endmodule