data/full_repos/permissive/143278/ivltests/gate_connect1.v
 line:17: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/gate_connect1.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("out = %b", out);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/gate_connect1.v:12: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                             : ... In instance top\nbuf buf2(out[1], 2\'b01);\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/gate_connect1.v:13: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                             : ... In instance top\nbuf buf3(out[2], in[1:0]);\n    ^~~~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

reg  [1:0] in;
wire [2:0] out;

buf buf1(out[0], 1);
buf buf2(out[1], 2'b01);
buf buf3(out[2], in[1:0]);

initial begin
  in = 1;
  #1 $display("out = %b", out);
  if (out === 3'b111)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module top;


reg  [1:0] in;
wire [2:0] out;

buf buf1(out[0], 1);
buf buf2(out[1], 2'b01);
buf buf3(out[2], in[1:0]);

initial begin
  in = 1;
  #1 $display("out = %b", out);
  if (out === 3'b111)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule