data/full_repos/permissive/114459345/srcCache/data_ram.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:10: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] wvalid_bit,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`ValidBitBus] wvalid_bit,\n                        ^\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:11: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] waddr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:12: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] data_i,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`ValidBitBus] rvalid_bit,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:16: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] rvalid_bit,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:17: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] raddr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:18: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus] data_o\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:22: Define or directive not defined: \'`DataMemNum\'\n reg[7:0] data_mem[0:`DataMemNum-1];\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:25: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:26: Define or directive not defined: \'`DataMemNum\'\n  for(i = 0; i < `DataMemNum; i = i + 1) begin\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:33: Define or directive not defined: \'`ChipDisable\'\n  if(ce == `ChipDisable) begin\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:36: Define or directive not defined: \'`WriteEnable\'\n  else if(we == `WriteEnable) begin  \n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:38: Define or directive not defined: \'`Byte\'\n    `Byte : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:42: Define or directive not defined: \'`Half\'\n    `Half : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:47: Define or directive not defined: \'`Word\'\n    `Word : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:69: Define or directive not defined: \'`ChipDisable\'\n  if(ce == `ChipDisable) begin\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:70: Define or directive not defined: \'`ZeroWord\'\n   data_o <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:72: Define or directive not defined: \'`WriteEnable\'\n  else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:72: Define or directive not defined: \'`ReadEnable\'\n  else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:75: Define or directive not defined: \'`ReadEnable\'\n  else if(re == `ReadEnable) begin  \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:77: Define or directive not defined: \'`Byte\'\n    `Byte : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:80: Define or directive not defined: \'`Half\'\n    `Half : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:83: Define or directive not defined: \'`Word\'\n    `Word : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:90: Define or directive not defined: \'`ZeroWord\'\n   data_o <= `ZeroWord;\n             ^~~~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module data_ram(

	input wire ce,
	

	input wire we,
	input wire[`ValidBitBus] wvalid_bit,
	input wire[`DataAddrBus] waddr,
	input wire[`DataBus] data_i,
	

	input wire re,
	input wire[`ValidBitBus] rvalid_bit,
	input wire[`DataAddrBus] raddr,
	output reg[`DataBus] data_o

);

	reg[7:0] data_mem[0:`DataMemNum-1];
	
	integer i;
	initial begin
		for(i = 0; i < `DataMemNum; i = i + 1) begin
			data_mem[i] = 8'h00;
		end
	end
	

	always @ (*) begin
		if(ce == `ChipDisable) begin

		end
		else if(we == `WriteEnable) begin
			case(wvalid_bit)
				`Byte : begin
					data_mem[waddr] <= data_i[7:0];

				end
				`Half : begin
					data_mem[waddr] <= data_i[7:0];
					data_mem[waddr+1] <= data_i[15:8];

				end
				`Word : begin
					data_mem[waddr] <= data_i[7:0];
					data_mem[waddr+1] <= data_i[15:8];
					data_mem[waddr+2] <= data_i[23:16];
					data_mem[waddr+3] <= data_i[31:24];

				end
				default : begin

				end
			endcase






		end
	end


	always @ (*) begin
		if(ce == `ChipDisable) begin
			data_o <= `ZeroWord;
		end
		else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
			data_o <= data_i;
		end
		else if(re == `ReadEnable) begin
			case(rvalid_bit)
				`Byte : begin
					data_o <= {{24{1'b0}}, data_mem[raddr]};
				end
				`Half : begin
					data_o <= {{16{1'b0}}, data_mem[raddr+1],data_mem[raddr]};
				end
				`Word : begin
					data_o <= {data_mem[raddr+3],data_mem[raddr+2],data_mem[raddr+1],data_mem[raddr]};
				end
			endcase

		end
		else begin
			data_o <= `ZeroWord;
		end
	end

endmodule
module data_ram(

	input wire ce,
	

	input wire we,
	input wire[`ValidBitBus] wvalid_bit,
	input wire[`DataAddrBus] waddr,
	input wire[`DataBus] data_i,
	

	input wire re,
	input wire[`ValidBitBus] rvalid_bit,
	input wire[`DataAddrBus] raddr,
	output reg[`DataBus] data_o

);


	reg[7:0] data_mem[0:`DataMemNum-1];
	
	integer i;
	initial begin
		for(i = 0; i < `DataMemNum; i = i + 1) begin
			data_mem[i] = 8'h00;
		end
	end
	

	always @ (*) begin
		if(ce == `ChipDisable) begin

		end
		else if(we == `WriteEnable) begin
			case(wvalid_bit)
				`Byte : begin
					data_mem[waddr] <= data_i[7:0];

				end
				`Half : begin
					data_mem[waddr] <= data_i[7:0];
					data_mem[waddr+1] <= data_i[15:8];

				end
				`Word : begin
					data_mem[waddr] <= data_i[7:0];
					data_mem[waddr+1] <= data_i[15:8];
					data_mem[waddr+2] <= data_i[23:16];
					data_mem[waddr+3] <= data_i[31:24];

				end
				default : begin

				end
			endcase






		end
	end


	always @ (*) begin
		if(ce == `ChipDisable) begin
			data_o <= `ZeroWord;
		end
		else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
			data_o <= data_i;
		end
		else if(re == `ReadEnable) begin
			case(rvalid_bit)
				`Byte : begin
					data_o <= {{24{1'b0}}, data_mem[raddr]};
				end
				`Half : begin
					data_o <= {{16{1'b0}}, data_mem[raddr+1],data_mem[raddr]};
				end
				`Word : begin
					data_o <= {data_mem[raddr+3],data_mem[raddr+2],data_mem[raddr+1],data_mem[raddr]};
				end
			endcase

		end
		else begin
			data_o <= `ZeroWord;
		end
	end

endmodule