data/full_repos/permissive/129155059/proyecto-01/includes/ffd_p2s_cond.v
data/verilator_xmls/a4e0b2c7-86ae-4fce-bd0f-2ead757b6512.xml
module ffd_p2s_cond(input CLK,
                    input D,
                    input ENB,
                    input valid_in,
                    output reg Q,
                    output reg valid_out
                    );

  always @ (posedge CLK) begin
    if (ENB) begin
      if (valid_in) begin
        Q <= D;
      end else begin
        Q <= Q;
      end
    end else begin
      Q <= 1'bz;

    end
  end

  always @ (D) begin
    valid_out = 1'b1;
  end

endmodule
module ffd_p2s_cond(input CLK,
                    input D,
                    input ENB,
                    input valid_in,
                    output reg Q,
                    output reg valid_out
                    );


  always @ (posedge CLK) begin
    if (ENB) begin
      if (valid_in) begin
        Q <= D;
      end else begin
        Q <= Q;
      end
    end else begin
      Q <= 1'bz;

    end
  end

  always @ (D) begin
    valid_out = 1'b1;
  end

endmodule