data/full_repos/permissive/201488448/2_circuits/2_sequential/18_dualedge.v
data/verilator_xmls/4b96c865-c694-4f29-95b1-a4fb70dce14d.xml
module top_module (
    input clk,
    input d,
    output q
);
	reg q1,q2;
    always@(posedge clk)
        q1 <= d;
    always@(negedge clk)
        q2 <= d;
    assign	q = clk?q1:q2;
    
endmodule
module top_module (
    input clk,
    input d,
    output q
);

	reg q1,q2;
    always@(posedge clk)
        q1 <= d;
    always@(negedge clk)
        q2 <= d;
    assign	q = clk?q1:q2;
    
endmodule