data/full_repos/permissive/117756790/blinkers/simple_blinker.v
 line:9: before: ","
data/verilator_xmls/9890dee8-4855-487e-bd8a-72b0b6c8f01e.xml
module simple_blinker(
  input clk,
  input rst,
  output blink
);














reg [24:0] counter_d, counter_q;




assign blink = counter_q[24];







always @(counter_q) begin


  counter_d = counter_q + 1'b1;
end




always @(posedge clk) begin
  if (rst) begin


    counter_q <= 25'b0;
  end else begin
    counter_q <= counter_d;
  end
end

endmodule
module simple_blinker(
  input clk,
  input rst,
  output blink
);















reg [24:0] counter_d, counter_q;




assign blink = counter_q[24];







always @(counter_q) begin


  counter_d = counter_q + 1'b1;
end




always @(posedge clk) begin
  if (rst) begin


    counter_q <= 25'b0;
  end else begin
    counter_q <= counter_d;
  end
end

endmodule