data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/full_adder.v
1: b"%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/full_adder.v:10: Cannot find file containing module: 'half_adder'\nhalf_adder half1(.x(x), .y(y), .sum(sum_internal), .carry(co_1));  \n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/half_adder\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/half_adder.v\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/half_adder.sv\n             half_adder\n             half_adder.v\n             half_adder.sv\n             obj_dir/half_adder\n             obj_dir/half_adder.v\n             obj_dir/half_adder.sv\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/full_adder.v:11: Cannot find file containing module: 'half_adder'\nhalf_adder half2(.x(c_in), .y(sum_internal), .sum(sum), .carry(co_2));  \n^~~~~~~~~~\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/full_adder.v:12: Cannot find file containing module: 'or_gate'\nor_gate my_or(.x(co_1), .y(co_2), .z(c_out));\n^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module full_adder(input wire x, input wire y, input wire c_in, output wire sum, output wire c_out);



wire co_1, co_2;
wire sum_internal;

half_adder half1(.x(x), .y(y), .sum(sum_internal), .carry(co_1));
half_adder half2(.x(c_in), .y(sum_internal), .sum(sum), .carry(co_2));
or_gate my_or(.x(co_1), .y(co_2), .z(c_out));

endmodule
module full_adder(input wire x, input wire y, input wire c_in, output wire sum, output wire c_out);




wire co_1, co_2;
wire sum_internal;

half_adder half1(.x(x), .y(y), .sum(sum_internal), .carry(co_1));
half_adder half2(.x(c_in), .y(sum_internal), .sum(sum), .carry(co_2));
or_gate my_or(.x(co_1), .y(co_2), .z(c_out));

endmodule