data/full_repos/permissive/189158922/verilog_src/lj92_pipeline_fifo.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/lj92_pipeline_fifo.v:351: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance top.fifo.unbuffered\n  assign \\$10  = produce == (* src = "nmigen/lib/fifo.py:102" *) 1\'h0;\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/lj92_pipeline_fifo.v:371: Operator NEQ expects 7 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance top.fifo.unbuffered\n  assign \\$4  = level != (* src = "nmigen/lib/fifo.py:145" *) 1\'h0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/lj92_pipeline_fifo.v:67: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'readable\' generates 1 bits.\n                                                                                        : ... In instance top.fifo\n  assign \\$7  = unbuffered_level + (* src = "nmigen/lib/fifo.py:263" *) readable;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/lj92_pipeline_fifo.v:192: Operator GTE expects 8 bits on the RHS, but RHS\'s CONST \'7\'h76\' generates 7 bits.\n                                                                                         : ... In instance top\n  assign \\$1  = fifo_level >= (* src = "lj92_pipeline_fifo.py:99" *) 7\'h76;\n                           ^~\n%Error: Exiting due to 4 warning(s)\n'
module fifo(we, re, rst, clk, dout, readable, level, din);
  wire \$1 ;
  wire \$3 ;
  wire \$5 ;
  wire [7:0] \$7 ;
  (* src = "nmigen/lib/fifo.py:69" *)
  reg [68:0] \$next\dout ;
  (* src = "nmigen/lib/fifo.py:238" *)
  reg [7:0] \$next\level ;
  (* src = "nmigen/lib/fifo.py:70" *)
  reg \$next\readable ;
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [68:0] \$next\unbuffered_din ;
  (* src = "nmigen/lib/fifo.py:71" *)
  reg \$next\unbuffered_re ;
  (* src = "nmigen/lib/fifo.py:139" *)
  reg \$next\unbuffered_replace ;
  (* src = "nmigen/lib/fifo.py:67" *)
  reg \$next\unbuffered_we ;
  (* src = "nmigen/lib/fifo.py:66" *)
  reg \$next\writable ;
  (* init = 1'h0 *)
  reg \$verilog_initial_trigger  = 1'h0;
  (* src = "nmigen/hdl/mem.py:97" *)
  input clk;
  (* src = "nmigen/lib/fifo.py:65" *)
  input [68:0] din;
  (* src = "nmigen/lib/fifo.py:69" *)
  output [68:0] dout;
  (* src = "nmigen/lib/fifo.py:238" *)
  output [7:0] level;
  (* src = "nmigen/lib/fifo.py:71" *)
  input re;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:70" *)
  output readable;
  reg readable = 1'h0;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "nmigen/lib/fifo.py:65" *)
  wire [68:0] unbuffered_din;
  (* src = "nmigen/lib/fifo.py:69" *)
  wire [68:0] unbuffered_dout;
  (* src = "nmigen/lib/fifo.py:138" *)
  wire [6:0] unbuffered_level;
  (* src = "nmigen/lib/fifo.py:71" *)
  wire unbuffered_re;
  (* src = "nmigen/lib/fifo.py:70" *)
  wire unbuffered_readable;
  (* src = "nmigen/lib/fifo.py:139" *)
  wire unbuffered_replace;
  (* src = "nmigen/lib/fifo.py:67" *)
  wire unbuffered_we;
  (* src = "nmigen/lib/fifo.py:66" *)
  wire unbuffered_writable;
  (* src = "nmigen/lib/fifo.py:67" *)
  input we;
  (* src = "nmigen/lib/fifo.py:66" *)
  wire writable;
  assign \$1  = ~ (* src = "nmigen/lib/fifo.py:256" *) readable;
  assign \$3  = \$1  | (* src = "nmigen/lib/fifo.py:256" *) re;
  assign \$5  = unbuffered_readable & (* src = "nmigen/lib/fifo.py:256" *) \$3 ;
  assign \$7  = unbuffered_level + (* src = "nmigen/lib/fifo.py:263" *) readable;
  always @(posedge clk)
      readable <= \$next\readable ;
  unbuffered unbuffered (
    .clk(clk),
    .din(unbuffered_din),
    .dout(unbuffered_dout),
    .level(unbuffered_level),
    .re(unbuffered_re),
    .readable(unbuffered_readable),
    .replace(unbuffered_replace),
    .rst(rst),
    .we(unbuffered_we),
    .writable(unbuffered_writable)
  );
  always @* begin
    \$next\unbuffered_din  = 69'h000000000000000000;
    \$next\unbuffered_din  = din;
  end
  always @* begin
    \$next\unbuffered_we  = 1'h0;
    \$next\unbuffered_we  = we;
  end
  always @* begin
    \$next\writable  = 1'h0;
    \$next\writable  = unbuffered_writable;
  end
  always @* begin
    \$next\unbuffered_replace  = 1'h0;
    \$next\unbuffered_replace  = 1'h0;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\dout  = 69'h000000000000000000;
    \$next\dout  = unbuffered_dout;
  end
  always @* begin
    \$next\unbuffered_re  = 1'h0;
    \$next\unbuffered_re  = \$5 ;
  end
  always @* begin
    \$next\readable  = readable;
    casez ({ re, unbuffered_re })
      2'bz1:
          \$next\readable  = 1'h1;
      2'b1z:
          \$next\readable  = 1'h0;
    endcase
    casez (rst)
      1'h1:
          \$next\readable  = 1'h0;
    endcase
  end
  always @* begin
    \$next\level  = 8'h00;
    \$next\level  = \$7 ;
  end
  assign level = \$next\level ;
  assign unbuffered_re = \$next\unbuffered_re ;
  assign dout = \$next\dout ;
  assign unbuffered_replace = \$next\unbuffered_replace ;
  assign writable = \$next\writable ;
  assign unbuffered_we = \$next\unbuffered_we ;
  assign unbuffered_din = \$next\unbuffered_din ;
endmodule
module fifo(we, re, rst, clk, dout, readable, level, din);

  wire \$1 ;
  wire \$3 ;
  wire \$5 ;
  wire [7:0] \$7 ;
  (* src = "nmigen/lib/fifo.py:69" *)
  reg [68:0] \$next\dout ;
  (* src = "nmigen/lib/fifo.py:238" *)
  reg [7:0] \$next\level ;
  (* src = "nmigen/lib/fifo.py:70" *)
  reg \$next\readable ;
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [68:0] \$next\unbuffered_din ;
  (* src = "nmigen/lib/fifo.py:71" *)
  reg \$next\unbuffered_re ;
  (* src = "nmigen/lib/fifo.py:139" *)
  reg \$next\unbuffered_replace ;
  (* src = "nmigen/lib/fifo.py:67" *)
  reg \$next\unbuffered_we ;
  (* src = "nmigen/lib/fifo.py:66" *)
  reg \$next\writable ;
  (* init = 1'h0 *)
  reg \$verilog_initial_trigger  = 1'h0;
  (* src = "nmigen/hdl/mem.py:97" *)
  input clk;
  (* src = "nmigen/lib/fifo.py:65" *)
  input [68:0] din;
  (* src = "nmigen/lib/fifo.py:69" *)
  output [68:0] dout;
  (* src = "nmigen/lib/fifo.py:238" *)
  output [7:0] level;
  (* src = "nmigen/lib/fifo.py:71" *)
  input re;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:70" *)
  output readable;
  reg readable = 1'h0;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "nmigen/lib/fifo.py:65" *)
  wire [68:0] unbuffered_din;
  (* src = "nmigen/lib/fifo.py:69" *)
  wire [68:0] unbuffered_dout;
  (* src = "nmigen/lib/fifo.py:138" *)
  wire [6:0] unbuffered_level;
  (* src = "nmigen/lib/fifo.py:71" *)
  wire unbuffered_re;
  (* src = "nmigen/lib/fifo.py:70" *)
  wire unbuffered_readable;
  (* src = "nmigen/lib/fifo.py:139" *)
  wire unbuffered_replace;
  (* src = "nmigen/lib/fifo.py:67" *)
  wire unbuffered_we;
  (* src = "nmigen/lib/fifo.py:66" *)
  wire unbuffered_writable;
  (* src = "nmigen/lib/fifo.py:67" *)
  input we;
  (* src = "nmigen/lib/fifo.py:66" *)
  wire writable;
  assign \$1  = ~ (* src = "nmigen/lib/fifo.py:256" *) readable;
  assign \$3  = \$1  | (* src = "nmigen/lib/fifo.py:256" *) re;
  assign \$5  = unbuffered_readable & (* src = "nmigen/lib/fifo.py:256" *) \$3 ;
  assign \$7  = unbuffered_level + (* src = "nmigen/lib/fifo.py:263" *) readable;
  always @(posedge clk)
      readable <= \$next\readable ;
  unbuffered unbuffered (
    .clk(clk),
    .din(unbuffered_din),
    .dout(unbuffered_dout),
    .level(unbuffered_level),
    .re(unbuffered_re),
    .readable(unbuffered_readable),
    .replace(unbuffered_replace),
    .rst(rst),
    .we(unbuffered_we),
    .writable(unbuffered_writable)
  );
  always @* begin
    \$next\unbuffered_din  = 69'h000000000000000000;
    \$next\unbuffered_din  = din;
  end
  always @* begin
    \$next\unbuffered_we  = 1'h0;
    \$next\unbuffered_we  = we;
  end
  always @* begin
    \$next\writable  = 1'h0;
    \$next\writable  = unbuffered_writable;
  end
  always @* begin
    \$next\unbuffered_replace  = 1'h0;
    \$next\unbuffered_replace  = 1'h0;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\dout  = 69'h000000000000000000;
    \$next\dout  = unbuffered_dout;
  end
  always @* begin
    \$next\unbuffered_re  = 1'h0;
    \$next\unbuffered_re  = \$5 ;
  end
  always @* begin
    \$next\readable  = readable;
    casez ({ re, unbuffered_re })
      2'bz1:
          \$next\readable  = 1'h1;
      2'b1z:
          \$next\readable  = 1'h0;
    endcase
    casez (rst)
      1'h1:
          \$next\readable  = 1'h0;
    endcase
  end
  always @* begin
    \$next\level  = 8'h00;
    \$next\level  = \$7 ;
  end
  assign level = \$next\level ;
  assign unbuffered_re = \$next\unbuffered_re ;
  assign dout = \$next\dout ;
  assign unbuffered_replace = \$next\unbuffered_replace ;
  assign writable = \$next\writable ;
  assign unbuffered_we = \$next\unbuffered_we ;
  assign unbuffered_din = \$next\unbuffered_din ;
endmodule