data/full_repos/permissive/124591763/ram/ram_tb.v
 line:37: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/124591763/ram/ram_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk <= ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/124591763/ram/ram_tb.v:29: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("ram_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/124591763/ram/ram_tb.v:30: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/124591763/ram/ram_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #50  wr_en <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/ram/ram_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #300 wr_en <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/ram/ram_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram_tb;

	reg        clk   = 1'b0;
	reg        wr_en = 1'b0;
	reg  [7:0] d_in  = 8'h0;
	reg  [7:0] addr  = 8'h0;
	wire [7:0] d_out;

	ram uut (
		.clk   (clk  ),
		.wr_en (wr_en),
		.d_in  (d_in ),
		.addr  (addr ),
		.d_out (d_out)
	);

	always #5 clk <= ~clk;

	always @ (posedge clk) begin
		d_in <= #1 d_in + 8'h1;

		if (&(addr[2:0])) addr <= #1 8'h0;
		else              addr <= #1 addr + 8'h1;
	end

	initial begin
		$dumpfile("ram_tb.vcd");
		$dumpvars;

		#50  wr_en <= 1'b1;
		#300 wr_en <= 1'b0;

		#50

		$display("simulation done");
		$finish;
	end

endmodule
module ram_tb;


	reg        clk   = 1'b0;
	reg        wr_en = 1'b0;
	reg  [7:0] d_in  = 8'h0;
	reg  [7:0] addr  = 8'h0;
	wire [7:0] d_out;

	ram uut (
		.clk   (clk  ),
		.wr_en (wr_en),
		.d_in  (d_in ),
		.addr  (addr ),
		.d_out (d_out)
	);

	always #5 clk <= ~clk;

	always @ (posedge clk) begin
		d_in <= #1 d_in + 8'h1;

		if (&(addr[2:0])) addr <= #1 8'h0;
		else              addr <= #1 addr + 8'h1;
	end

	initial begin
		$dumpfile("ram_tb.vcd");
		$dumpvars;

		#50  wr_en <= 1'b1;
		#300 wr_en <= 1'b0;

		#50

		$display("simulation done");
		$finish;
	end

endmodule