data/full_repos/permissive/161029703/xilinx/CPLD/top.v
data/verilator_xmls/0079df8a-c76c-4091-ac00-4001fc1ac9ca.xml
module top(
input wire clk,
input wire rxd,
output wire txd,
input wire exp1,
output wire exp2,
inout wire[3:0] interconn
    );

assign txd = interconn[0];
assign interconn[1] = rxd;

assign exp2 = interconn[2];
assign interconn[3] = exp1;

endmodule
module top(
input wire clk,
input wire rxd,
output wire txd,
input wire exp1,
output wire exp2,
inout wire[3:0] interconn
    );


assign txd = interconn[0];
assign interconn[1] = rxd;

assign exp2 = interconn[2];
assign interconn[3] = exp1;

endmodule