data/full_repos/permissive/102515926/Modules/MUX2x1.v
data/verilator_xmls/3ca89e6d-3277-42f6-8437-ef5b80202d32.xml
module MUX2x1(a, b, sel, d);

    parameter DATAWIDTH = 64;

    input [DATAWIDTH - 1:0] a, b;
    input sel;
    
    output reg [DATAWIDTH - 1:0] d;
    
    always @(*) begin
        
        if(sel == 0)
            d <= a;
        else
            d <= b;
    
    end
    
endmodule
module MUX2x1(a, b, sel, d);


    parameter DATAWIDTH = 64;

    input [DATAWIDTH - 1:0] a, b;
    input sel;
    
    output reg [DATAWIDTH - 1:0] d;
    
    always @(*) begin
        
        if(sel == 0)
            d <= a;
        else
            d <= b;
    
    end
    
endmodule