data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v
None: at end of input
1: b'%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:2: Cannot find include file: ./modulos/salidaSerial.v\n  `include "./modulos/salidaSerial.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/salidaSerial.v\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/salidaSerial.v.v\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/salidaSerial.v.sv\n             ./modulos/salidaSerial.v\n             ./modulos/salidaSerial.v.v\n             ./modulos/salidaSerial.v.sv\n             obj_dir/./modulos/salidaSerial.v\n             obj_dir/./modulos/salidaSerial.v.v\n             obj_dir/./modulos/salidaSerial.v.sv\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:5: Cannot find include file: ./modulos/registro4bits.v\n  `include "./modulos/registro4bits.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:8: Cannot find include file: ./modulos/bitHolder.v\n  `include "./modulos/bitHolder.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:11: Cannot find include file: ./modulos/ternarioDoble.v\n  `include "./modulos/ternarioDoble.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:14: Cannot find include file: ./modulos/serialOcontiguo.v\n  `include "./modulos/serialOcontiguo.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:17: Cannot find include file: ./modulos/enabler.v\n  `include "./modulos/enabler.v" \n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:21: Cannot find include file: ../tarea3/modulos/norGate.v\n  `include "../tarea3/modulos/norGate.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:24: Cannot find include file: ../tarea3/modulos/notGate.v\n  `include "../tarea3/modulos/notGate.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:27: Cannot find include file: ../tarea3/modulos/nandGate.v\n  `include "../tarea3/modulos/nandGate.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:30: Cannot find include file: ../tarea3/modulos/mux.v\n  `include "../tarea3/modulos/mux.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:33: Cannot find include file: ../tarea3/modulos/ffD.v\n  `include "../tarea3/modulos/ffD.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:37: Cannot find include file: ./modulos/sreg.v\n  `include "./modulos/sreg.v" \n           ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:95: Unsupported: Ignoring delay on this delayed statement.\n  initial # 50 clk = 0;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:97: Unsupported: Ignoring delay on this delayed statement.\n  always # 17.4 clk = ~clk;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:111: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:112: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:123: Unsupported: Ignoring delay on this delayed statement.\n    # 10;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:125: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:131: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:133: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:138: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:140: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:145: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:147: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:152: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:154: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:159: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:161: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:167: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:169: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:174: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:176: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:181: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:183: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:188: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:190: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:197: Unsupported: Ignoring delay on this delayed statement.\n    # 200\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:201: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:207: Unsupported: Ignoring delay on this delayed statement.\n    # 400\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:209: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:212: Unsupported: Ignoring delay on this delayed statement.\n    # 400\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:215: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:219: Unsupported: Ignoring delay on this delayed statement.\n    # 400\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:221: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:224: Unsupported: Ignoring delay on this delayed statement.\n    # 90\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:226: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:229: Unsupported: Ignoring delay on this delayed statement.\n    # 60\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:231: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:234: Unsupported: Ignoring delay on this delayed statement.\n    # 40\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:236: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:239: Unsupported: Ignoring delay on this delayed statement.\n    # 550;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:240: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:244: Unsupported: Ignoring delay on this delayed statement.\n    # 60;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:246: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:254: Unsupported: Ignoring delay on this delayed statement.\n    # 200\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:257: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:262: Unsupported: Ignoring delay on this delayed statement.\n    # 400\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:264: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:267: Unsupported: Ignoring delay on this delayed statement.\n    # 550;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:268: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:279: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./tests/testregistro4bits.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:280: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:285: Unsupported or unknown PLI call: $monitor\n    $monitor            ("%t| %b   | %b   | %b    | %b   | %b | %b | %b     | %f ns",\n    ^~~~~~~~\n%Error: Exiting due to 38 error(s), 25 warning(s)\n'
module testregistro4bits ();









  wire [3:0] qe;
  wire s_oute;

  reg clk;
  reg enb;
  reg dir;
  reg s_in;

  reg [1:0] modo;
  reg [3:0] d;

  wire [3:0] qc;
  wire s_outc;


  registro4bits estructural(
	.clk(clk),
	.enb(enb),
	.dir(dir),
	.s_in(s_in),
	.modo(modo),
	.d(d),
	.q(qe),
	.s_out(s_oute)
  );

  rdesplazante conductual(
	.CLK(clk),
	.ENB(enb),
	.DIR(dir),
	.S_IN(s_in),
	.MODE(modo),
	.D(d),
	.Q(qc),
	.S_OUT(s_outc)
  );


  initial # 50 clk = 0;

  always # 17.4 clk = ~clk;

  always @(qe,qc ) begin
	  if(qe != qc)$display("<<<<<<<<<<<<<<<<HAY ADiferencias entre las salidas  q  >>>>>>>>>>>>>>>>>>>");

  end

  always @(s_outc,s_oute ) begin
	  if(s_outc != s_oute)$display("<<<<<<<<<<<<<<<<HAY ADiferencias entre las salidas s_out  >>>>>>>>>>>>>>>>>>>");

  end

  initial begin

    # 50;
    @(posedge clk);
    modo <= 2'b00;









    # 10;
    $display("se carga 0000");
    @(posedge clk);
      enb <= 1;
      modo <= 2'b10;
      d <= 4'b0000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0001");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0001;
      dir <= 1'bx;

    # 50;
    $display("se carga 0010");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0010;
      dir <= 1'bx;

    # 50;
    $display("se carga 0100");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0100;
      dir <= 1'bx;

    # 50;
    $display("se carga 1000");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b1000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0000");
    @(posedge clk);
      enb <= 1;
      modo <= 2'b10;
      d <= 4'b0000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0001");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0001;
      dir <= 1'bx;

    # 50;
    $display("se carga 0011");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0011;
      dir <= 1'bx;

    # 50;
    $display("se carga 0111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0111;
      dir <= 1'bx;

    # 50;
    $display("se carga 1111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b1111;
      dir <= 1'bx;



    # 200
    $display("---\nModo de Carga en Serie\n---");
    $display("Hacia la izquierda");
    $display("con s_in = 0");
    @(posedge clk);
      d <= 4'bzzzz;
      modo <= 2'b00;
      dir <= 1'b0;
      s_in <= 2'b0;

    # 400
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1;

    # 400
    $display("Hacia la derecha");
    $display("con s_in = 0");
    @(posedge clk);
      dir <= 1'b1;
      s_in <= 0;

    # 400
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b1;

    # 90
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b0;

    # 60
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b1;

    # 40
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b0;

    # 550;
    @(posedge clk);


   $display("Hacemos otra carga paralela antes de la rotacion circular");
    # 60;
    $display("se carga 0111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0111;
      dir <= 1'bx;




    # 200
    $display("---\nModo de rotacion circular\n---");
    $display("Hacia la izquierda");
    @(posedge clk);
      d <= 4'bzzzz;
      modo <= 2'b01;
      dir <= 1'b0;

    # 400
    $display("Hacia la derecha");
    @(posedge clk);
      dir <= 1'b1;

    # 550;
    @(posedge clk);

    $display("------------------------------------");
    $display("##### FIN TEST DE REGISTRO    #####-");
    $display("------------------------------------");

    $finish;
  end

  initial
    begin
    $dumpfile("./tests/testregistro4bits.vcd");
    $dumpvars;
    $display("------------------------------------");
    $display("-- Test para modulo registro4bits --");
    $display("------------------------------------");
    $display ("\t     tiempo | enb | dir | s_in | modo | d    | q    | s_out | tiempo");
    $monitor            ("%t| %b   | %b   | %b    | %b   | %b | %b | %b     | %f ns",
                          $time, enb, dir, s_in, modo, d, qc, s_outc , $realtime);
  end
endmodule
module testregistro4bits ();










  wire [3:0] qe;
  wire s_oute;

  reg clk;
  reg enb;
  reg dir;
  reg s_in;

  reg [1:0] modo;
  reg [3:0] d;

  wire [3:0] qc;
  wire s_outc;


  registro4bits estructural(
	.clk(clk),
	.enb(enb),
	.dir(dir),
	.s_in(s_in),
	.modo(modo),
	.d(d),
	.q(qe),
	.s_out(s_oute)
  );

  rdesplazante conductual(
	.CLK(clk),
	.ENB(enb),
	.DIR(dir),
	.S_IN(s_in),
	.MODE(modo),
	.D(d),
	.Q(qc),
	.S_OUT(s_outc)
  );


  initial # 50 clk = 0;

  always # 17.4 clk = ~clk;

  always @(qe,qc ) begin
	  if(qe != qc)$display("<<<<<<<<<<<<<<<<HAY ADiferencias entre las salidas  q  >>>>>>>>>>>>>>>>>>>");

  end

  always @(s_outc,s_oute ) begin
	  if(s_outc != s_oute)$display("<<<<<<<<<<<<<<<<HAY ADiferencias entre las salidas s_out  >>>>>>>>>>>>>>>>>>>");

  end

  initial begin

    # 50;
    @(posedge clk);
    modo <= 2'b00;









    # 10;
    $display("se carga 0000");
    @(posedge clk);
      enb <= 1;
      modo <= 2'b10;
      d <= 4'b0000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0001");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0001;
      dir <= 1'bx;

    # 50;
    $display("se carga 0010");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0010;
      dir <= 1'bx;

    # 50;
    $display("se carga 0100");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0100;
      dir <= 1'bx;

    # 50;
    $display("se carga 1000");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b1000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0000");
    @(posedge clk);
      enb <= 1;
      modo <= 2'b10;
      d <= 4'b0000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0001");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0001;
      dir <= 1'bx;

    # 50;
    $display("se carga 0011");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0011;
      dir <= 1'bx;

    # 50;
    $display("se carga 0111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0111;
      dir <= 1'bx;

    # 50;
    $display("se carga 1111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b1111;
      dir <= 1'bx;



    # 200
    $display("---\nModo de Carga en Serie\n---");
    $display("Hacia la izquierda");
    $display("con s_in = 0");
    @(posedge clk);
      d <= 4'bzzzz;
      modo <= 2'b00;
      dir <= 1'b0;
      s_in <= 2'b0;

    # 400
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1;

    # 400
    $display("Hacia la derecha");
    $display("con s_in = 0");
    @(posedge clk);
      dir <= 1'b1;
      s_in <= 0;

    # 400
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b1;

    # 90
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b0;

    # 60
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b1;

    # 40
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b0;

    # 550;
    @(posedge clk);


   $display("Hacemos otra carga paralela antes de la rotacion circular");
    # 60;
    $display("se carga 0111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0111;
      dir <= 1'bx;




    # 200
    $display("---\nModo de rotacion circular\n---");
    $display("Hacia la izquierda");
    @(posedge clk);
      d <= 4'bzzzz;
      modo <= 2'b01;
      dir <= 1'b0;

    # 400
    $display("Hacia la derecha");
    @(posedge clk);
      dir <= 1'b1;

    # 550;
    @(posedge clk);

    $display("------------------------------------");
    $display("##### FIN TEST DE REGISTRO    #####-");
    $display("------------------------------------");

    $finish;
  end

  initial
    begin
    $dumpfile("./tests/testregistro4bits.vcd");
    $dumpvars;
    $display("------------------------------------");
    $display("-- Test para modulo registro4bits --");
    $display("------------------------------------");
    $display ("\t     tiempo | enb | dir | s_in | modo | d    | q    | s_out | tiempo");
    $monitor            ("%t| %b   | %b   | %b    | %b   | %b | %b | %b     | %f ns",
                          $time, enb, dir, s_in, modo, d, qc, s_outc , $realtime);
  end
endmodule