data/full_repos/permissive/140572461/hdl/clk_div.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/140572461/hdl/clk_div.v:55: Unsupported: Ignoring delay on this delayed statement.\nalways #1\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/140572461/hdl/clk_div.v:24: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'counter\' generates 5 bits.\n                                                                     : ... In instance clk_div_tb.DUT\n        if (counter == COUNTER_MAX - 1) begin\n                    ^~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clk_div_tb;

reg clk_50;
wire clk_1;

clk_div DUT(
    .clk (clk_50),
    .enable (1'b1),
    .clk_out (clk_1)
);

initial begin
    clk_50 = 1'b0;
end

always #1
    clk_50 = !clk_50;

endmodule
module clk_div_tb;


reg clk_50;
wire clk_1;

clk_div DUT(
    .clk (clk_50),
    .enable (1'b1),
    .clk_out (clk_1)
);

initial begin
    clk_50 = 1'b0;
end

always #1
    clk_50 = !clk_50;

endmodule