data/full_repos/permissive/19572582/Lab4/t_flipflop.v
data/verilator_xmls/d028aa37-4a28-41f5-83da-7e49194fda45.xml
module t_flipflop (En, Clk, Clr, Q);
  input En, Clk, Clr;
  output reg Q;

  always @ (posedge Clk)
    if (Clr)
      Q = 0;
    else if (En)
      Q = ~Q;

endmodule
module t_flipflop (En, Clk, Clr, Q);

  input En, Clk, Clr;
  output reg Q;

  always @ (posedge Clk)
    if (Clr)
      Q = 0;
    else if (En)
      Q = ~Q;

endmodule