data/full_repos/permissive/139213403/FPGA/led_matrix.v
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1: b'%Error: data/full_repos/permissive/139213403/FPGA/led_matrix.v:33: Cannot find file containing module: \'pwm\'\n pwm #(.N(PWM_BITS), .M(LEDS_N + LEDS_M)) pwm_n(.clk(clk), .reset(reset), .in({ cur_n, cur_m }), .w(brightness), .out({ n_en, m_en })); \n ^~~\n        ... Looked in:\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/pwm\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/pwm.v\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/pwm.sv\n             pwm\n             pwm.v\n             pwm.sv\n             obj_dir/pwm\n             obj_dir/pwm.v\n             obj_dir/pwm.sv\n%Error: data/full_repos/permissive/139213403/FPGA/led_matrix.v:34: Cannot find file containing module: \'mod_m_counter\'\n mod_m_counter #(.M_BITS(LED_PERIOD_BITS)) tick_counter(.clk(clk), .reset(reset), .m(led_period), .max_tick(led_tick), .q());\n ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_matrix.v:39: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                         : ... In instance led_matrix\n   en_reg[sel_addr] = en;\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_matrix.v:69: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance led_matrix\n       n_i_next = 1\'b0;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_matrix.v:73: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance led_matrix\n         m_i_next = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_matrix.v:74: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance led_matrix\n         addr_i_next = 1\'b0;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_matrix.v:67: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'n_i_next\' generates 2 bits.\n                                                                         : ... In instance led_matrix\n     if (n_i_next == LEDS_N)\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_matrix.v:82: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                         : ... In instance led_matrix\n assign cur_n = en_reg[addr_i_reg] << n_i_reg;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_matrix.v:82: Operator SHIFTL expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                         : ... In instance led_matrix\n assign cur_n = en_reg[addr_i_reg] << n_i_reg;\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_matrix.v:83: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                         : ... In instance led_matrix\n assign cur_m = en_reg[addr_i_reg] << m_i_reg;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_matrix.v:83: Operator SHIFTL expects 2 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                         : ... In instance led_matrix\n assign cur_m = en_reg[addr_i_reg] << m_i_reg;\n                                   ^~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n'
module led_matrix
#(

	parameter LEDS_N=4,
				 LEDS_M=2,
				 N_BITS = 2,
				 M_BITS = 2,
	

				 PWM_BITS=12,
				 LED_PERIOD_BITS=24
)
(
	input wire clk, reset,
	input wire [PWM_BITS-1:0] brightness,
	input wire [N_BITS + M_BITS - 1:0] sel_addr,
	input wire sel, en,
	input wire [LED_PERIOD_BITS-1:0] led_period,
	output wire [LEDS_N-1:0] n_en,
	output wire [LEDS_M-1:0] m_en,
	output reg done_tick
);

	reg [(LEDS_N*LEDS_M)-1:0] en_reg;
	reg [N_BITS + M_BITS - 1:0] addr_i_reg, addr_i_next;
	reg [N_BITS-1:0] n_i_reg, n_i_next;
	reg [M_BITS-1:0] m_i_reg, m_i_next;
	wire [LEDS_N-1:0] cur_n;
	wire [LEDS_M-1:0] cur_m;
	wire led_tick;

	pwm #(.N(PWM_BITS), .M(LEDS_N + LEDS_M)) pwm_n(.clk(clk), .reset(reset), .in({ cur_n, cur_m }), .w(brightness), .out({ n_en, m_en })); 
	mod_m_counter #(.M_BITS(LED_PERIOD_BITS)) tick_counter(.clk(clk), .reset(reset), .m(led_period), .max_tick(led_tick), .q());
	

	always @(posedge clk)
		if (sel)
			en_reg[sel_addr] = en;
	

	always @(posedge clk, posedge reset)
		if (reset)
			begin
				n_i_reg <= 0;
				m_i_reg <= 0;
				addr_i_reg <= 0;
			end
		else
			begin
				n_i_reg <= n_i_next;
				m_i_reg <= m_i_next;
				addr_i_reg <= addr_i_next;
			end
	

	always @*
		begin
			done_tick = 1'b0;
			n_i_next = n_i_reg;
			m_i_next = m_i_reg;
			addr_i_next = addr_i_reg;
			if (led_tick)
				begin
					n_i_next = n_i_reg + 1'b1;
					addr_i_next = addr_i_reg + 1'b1;
					if (n_i_next == LEDS_N)
						begin
							n_i_next = 1'b0;
							m_i_next = m_i_reg + 1'b1;
							if (m_i_next == LEDS_M)
								begin
									m_i_next = 1'b0;
									addr_i_next = 1'b0;
									done_tick = 1'b1;
								end
						end
						
				end
		end
	
	assign cur_n = en_reg[addr_i_reg] << n_i_reg;
	assign cur_m = en_reg[addr_i_reg] << m_i_reg;
			
endmodule
module led_matrix
#(

	parameter LEDS_N=4,
				 LEDS_M=2,
				 N_BITS = 2,
				 M_BITS = 2,
	

				 PWM_BITS=12,
				 LED_PERIOD_BITS=24
)
(
	input wire clk, reset,
	input wire [PWM_BITS-1:0] brightness,
	input wire [N_BITS + M_BITS - 1:0] sel_addr,
	input wire sel, en,
	input wire [LED_PERIOD_BITS-1:0] led_period,
	output wire [LEDS_N-1:0] n_en,
	output wire [LEDS_M-1:0] m_en,
	output reg done_tick
);


	reg [(LEDS_N*LEDS_M)-1:0] en_reg;
	reg [N_BITS + M_BITS - 1:0] addr_i_reg, addr_i_next;
	reg [N_BITS-1:0] n_i_reg, n_i_next;
	reg [M_BITS-1:0] m_i_reg, m_i_next;
	wire [LEDS_N-1:0] cur_n;
	wire [LEDS_M-1:0] cur_m;
	wire led_tick;

	pwm #(.N(PWM_BITS), .M(LEDS_N + LEDS_M)) pwm_n(.clk(clk), .reset(reset), .in({ cur_n, cur_m }), .w(brightness), .out({ n_en, m_en })); 
	mod_m_counter #(.M_BITS(LED_PERIOD_BITS)) tick_counter(.clk(clk), .reset(reset), .m(led_period), .max_tick(led_tick), .q());
	

	always @(posedge clk)
		if (sel)
			en_reg[sel_addr] = en;
	

	always @(posedge clk, posedge reset)
		if (reset)
			begin
				n_i_reg <= 0;
				m_i_reg <= 0;
				addr_i_reg <= 0;
			end
		else
			begin
				n_i_reg <= n_i_next;
				m_i_reg <= m_i_next;
				addr_i_reg <= addr_i_next;
			end
	

	always @*
		begin
			done_tick = 1'b0;
			n_i_next = n_i_reg;
			m_i_next = m_i_reg;
			addr_i_next = addr_i_reg;
			if (led_tick)
				begin
					n_i_next = n_i_reg + 1'b1;
					addr_i_next = addr_i_reg + 1'b1;
					if (n_i_next == LEDS_N)
						begin
							n_i_next = 1'b0;
							m_i_next = m_i_reg + 1'b1;
							if (m_i_next == LEDS_M)
								begin
									m_i_next = 1'b0;
									addr_i_next = 1'b0;
									done_tick = 1'b1;
								end
						end
						
				end
		end
	
	assign cur_n = en_reg[addr_i_reg] << n_i_reg;
	assign cur_m = en_reg[addr_i_reg] << m_i_reg;
			
endmodule