data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v
 line:156: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_reset_01 = 1\'b1;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:96: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #1000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:111: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:115: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:116: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:117: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:118: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:123: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:125: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:126: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:127: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:128: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:130: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:132: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:133: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:134: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:135: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:138: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:142: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:146: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:147: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:149: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:150: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:151: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:152: Unsupported: Ignoring delay on this delayed statement.\n        #104167 i_rx_01 = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:156: Unsupported: Ignoring delay on this delayed statement.\n        #1000000 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:159: Unsupported: Ignoring delay on this delayed statement.\n    always #5 i_clk_01=~i_clk_01;  \n           ^\n%Error: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_top_uart.v:161: Cannot find file containing module: \'top_uart\'\n    top_uart #(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/top_uart\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/top_uart.v\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/top_uart.sv\n             top_uart\n             top_uart.v\n             top_uart.sv\n             obj_dir/top_uart\n             obj_dir/top_uart.v\n             obj_dir/top_uart.sv\n%Error: Exiting due to 1 error(s), 84 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top_uart();
    parameter DBIT_01 = 8;
    parameter SB_TICK_01 = 16;

    parameter BAUDRATE_DIVISOR_01 = 651;

    parameter BAUDRATE_DIVISOR_BITS_01 = 10;

    parameter NB_OP_01 = 6;


    reg              i_clk_01; 
    reg              i_reset_01;
    reg              i_rx_01;

    wire             o_tx_01;

    initial begin
        i_clk_01 = 1'b0; 
        i_reset_01 = 1'b0;
        i_rx_01 = 1'b1;

        #10 i_reset_01 = 1'b1;
        


        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;


        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;


        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        
        #1000000;

        

        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;


        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;


        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        

        
        #1000000 $finish;
    end
    
    always #5 i_clk_01=~i_clk_01;

    top_uart #(
            .DBIT                   (DBIT_01),
            .SB_TICK                (SB_TICK_01),
            .BAUDRATE_DIVISOR       (BAUDRATE_DIVISOR_01),
            .BAUDRATE_DIVISOR_BITS  (BAUDRATE_DIVISOR_BITS_01),
            .NB_OP                  (NB_OP_01)
        )
    top_uart_01 (
        .i_clk      (i_clk_01),
        .i_reset    (i_reset_01),
        .RsRx       (i_rx_01),
        .RsTx       (o_tx_01)
        );

endmodule
module tb_top_uart();

    parameter DBIT_01 = 8;
    parameter SB_TICK_01 = 16;

    parameter BAUDRATE_DIVISOR_01 = 651;

    parameter BAUDRATE_DIVISOR_BITS_01 = 10;

    parameter NB_OP_01 = 6;


    reg              i_clk_01; 
    reg              i_reset_01;
    reg              i_rx_01;

    wire             o_tx_01;

    initial begin
        i_clk_01 = 1'b0; 
        i_reset_01 = 1'b0;
        i_rx_01 = 1'b1;

        #10 i_reset_01 = 1'b1;
        


        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;


        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;


        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        
        #1000000;

        

        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;


        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;


        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b0;
        #104167 i_rx_01 = 1'b0;
        
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        #104167 i_rx_01 = 1'b1;
        

        
        #1000000 $finish;
    end
    
    always #5 i_clk_01=~i_clk_01;

    top_uart #(
            .DBIT                   (DBIT_01),
            .SB_TICK                (SB_TICK_01),
            .BAUDRATE_DIVISOR       (BAUDRATE_DIVISOR_01),
            .BAUDRATE_DIVISOR_BITS  (BAUDRATE_DIVISOR_BITS_01),
            .NB_OP                  (NB_OP_01)
        )
    top_uart_01 (
        .i_clk      (i_clk_01),
        .i_reset    (i_reset_01),
        .RsRx       (i_rx_01),
        .RsTx       (o_tx_01)
        );

endmodule