data/full_repos/permissive/147265957/src/romemory.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/147265957/src/romemory.v:31: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                      : ... In instance romemory\n    assign cont = memory[addr];\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/147265957/src/romemory.v:31: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 4 bits.\n                                                                      : ... In instance romemory\n    assign cont = memory[addr];\n                ^\n%Error: Exiting due to 2 warning(s)\n'
module romemory(
addr,cont
    );
    parameter WIDTH = 8;
    input [3:0] addr;
    reg [3:0] memory [WIDTH-1:0];
    output [WIDTH-1:0] cont;
    initial $readmemh("linkedlist.txt",memory);
    assign cont = memory[addr];
endmodule
module romemory(
addr,cont
    );

    parameter WIDTH = 8;
    input [3:0] addr;
    reg [3:0] memory [WIDTH-1:0];
    output [WIDTH-1:0] cont;
    initial $readmemh("linkedlist.txt",memory);
    assign cont = memory[addr];
endmodule