data/full_repos/permissive/113780415/src/top_test.v
 line:1736: before: "&&"
1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(posedge clk && enable == 1'b1)\n                                   ^~\n%Error: Cannot continue\n"
module AALU(x, y, lose, bonus, enable);





	input [4:0] x;

	input [4:0] y;

	input enable;

	output [4:0] bonus;

	output lose;

	wire [4:0] greater;

	wire [4:0] lower;

	

	comparator comp(

			.x(x[4:0]),

			.y(y[4:0]),

			.greater(greater[4:0]),

			.enable(enable),

			.lower(lower[4:0]),

			.same(lose)

			);

	

	subtractor sub(

			.operandone(greater[4:0]),

			.operandtwo(lower[4:0]),

			.enable(enable),

			.result(bonus[4:0])

			);



endmodule
module AALU(x, y, lose, bonus, enable);






	input [4:0] x;

	input [4:0] y;

	input enable;

	output [4:0] bonus;

	output lose;

	wire [4:0] greater;

	wire [4:0] lower;

	

	comparator comp(

			.x(x[4:0]),

			.y(y[4:0]),

			.greater(greater[4:0]),

			.enable(enable),

			.lower(lower[4:0]),

			.same(lose)

			);

	

	subtractor sub(

			.operandone(greater[4:0]),

			.operandtwo(lower[4:0]),

			.enable(enable),

			.result(bonus[4:0])

			);



endmodule