data/full_repos/permissive/146399661/src/rsa/test_emul_sql.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_emul_sql.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_emul_sql.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_emul_sql.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_emul_sql.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_emul_sql.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rsa/test_emul_sql.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: data/full_repos/permissive/146399661/src/rsa/test_emul_sql.v:8: Cannot find file containing module: \'emul_sql\'\nemul_sql emul_sql(x,a,b,clock,enable,reset,ready);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146399661/src/rsa,data/full_repos/permissive/146399661/emul_sql\n             data/full_repos/permissive/146399661/src/rsa,data/full_repos/permissive/146399661/emul_sql.v\n             data/full_repos/permissive/146399661/src/rsa,data/full_repos/permissive/146399661/emul_sql.sv\n             emul_sql\n             emul_sql.v\n             emul_sql.sv\n             obj_dir/emul_sql\n             obj_dir/emul_sql.v\n             obj_dir/emul_sql.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

reg [7:0] a,b;
reg clock,reset,enable;
wire [15:0] x;
wire ready;

emul_sql emul_sql(x,a,b,clock,enable,reset,ready);

initial begin 
    $display("test >> Resetting the emul_sql module");
    reset = 1;
    enable = 0;
    #10;
    reset = 0;
    if (~ready) begin
        $display("test >> emul_sql is ready");
    end
    else begin
        $display("test >> emul_sql is not ready");
    end
    a = 8'b00001111;
    b = 8'b11111111;
    enable = 1;

    $display("test >> Waiting till emul_sql has its data ready");
    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> emul_sql has its data ready!");
    enable = 0;
    $display("test >> a was %d, b was %d, axb = %d",a,b,x);

    $display("test >> Resetting the emul_sql module for the next computation");

    enable = 0;
    reset = 1;
    while (ready != 1'b0) begin
        #1;
    end
    reset = 0;

    $display("test >> emul_sql is ready");

    a = 8'b10101111;
    b = 8'b11011011;
    enable = 1;

    $display("test >> Waiting till emul_sql has its data ready");
    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> emul_sql has its data ready!");
    enable = 0;

    $display("test >> a was %d, b was %d, axb = %d",a,b,x);
end

always begin
    clock = 0; 
    #5;
    clock = 1;
    #5;
end

endmodule
module main;


reg [7:0] a,b;
reg clock,reset,enable;
wire [15:0] x;
wire ready;

emul_sql emul_sql(x,a,b,clock,enable,reset,ready);

initial begin 
    $display("test >> Resetting the emul_sql module");
    reset = 1;
    enable = 0;
    #10;
    reset = 0;
    if (~ready) begin
        $display("test >> emul_sql is ready");
    end
    else begin
        $display("test >> emul_sql is not ready");
    end
    a = 8'b00001111;
    b = 8'b11111111;
    enable = 1;

    $display("test >> Waiting till emul_sql has its data ready");
    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> emul_sql has its data ready!");
    enable = 0;
    $display("test >> a was %d, b was %d, axb = %d",a,b,x);

    $display("test >> Resetting the emul_sql module for the next computation");

    enable = 0;
    reset = 1;
    while (ready != 1'b0) begin
        #1;
    end
    reset = 0;

    $display("test >> emul_sql is ready");

    a = 8'b10101111;
    b = 8'b11011011;
    enable = 1;

    $display("test >> Waiting till emul_sql has its data ready");
    while (ready == 1'b0) begin
        #1;
    end

    $display("test >> emul_sql has its data ready!");
    enable = 0;

    $display("test >> a was %d, b was %d, axb = %d",a,b,x);
end

always begin
    clock = 0; 
    #5;
    clock = 1;
    #5;
end

endmodule