data/full_repos/permissive/143278/ivltests/port-test2.v
 line:13: before: ","
1: b'%Error: data/full_repos/permissive/143278/ivltests/port-test2.v:13: syntax error, unexpected \',\', expecting \'[\'\n    ,\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test2.v:57: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test2.v:72: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module port_3
  (
    dummy_1,
,
    in[7:0],
    dummy_2,
    out[7:0],

   );
   input [7:0]  in;
   output [7:0] out;
   output	dummy_1;
   output	dummy_2;
   assign	out = in;
endmodule
module port_3
  (
    dummy_1,
,
    in[7:0],
    dummy_2,
    out[7:0],

   );

   input [7:0]  in;
   output [7:0] out;
   output	dummy_1;
   output	dummy_2;
   assign	out = in;
endmodule