data/full_repos/permissive/115837888/source-7400/74377.v
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data/verilator_xmls/1dc2a604-46db-42f4-8062-480015af25bb.xml
module ttl_74377 #(parameter WIDTH = 8, DELAY_RISE = 0, DELAY_FALL = 0)
(
  input Enable_bar,
  input [WIDTH-1:0] D,
  input Clk,
  output [WIDTH-1:0] Q
);


reg [WIDTH-1:0] Q_current;

always @(posedge Clk)
begin
  if (!Enable_bar)
    Q_current <= D;
end


assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;

endmodule
module ttl_74377 #(parameter WIDTH = 8, DELAY_RISE = 0, DELAY_FALL = 0)
(
  input Enable_bar,
  input [WIDTH-1:0] D,
  input Clk,
  output [WIDTH-1:0] Q
);



reg [WIDTH-1:0] Q_current;

always @(posedge Clk)
begin
  if (!Enable_bar)
    Q_current <= D;
end


assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;

endmodule