data/full_repos/permissive/188068190/ridecore-src-buggy/search_be.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/188068190/ridecore-src-buggy/search_be.v:26: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'search_begin\'\nmodule search_begin #(\n       ^~~~~~~~~~~~\n                                                                                         : ... Top module \'search_end\'\nmodule search_end #(\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188068190/ridecore-src-buggy/search_be.v:42: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                      : ... In instance search_end\n     out = i;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/188068190/ridecore-src-buggy/search_be.v:18: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                      : ... In instance search_begin\n     out = i;\n         ^\n%Error: Exiting due to 3 warning(s)\n'
module search_begin #(
		      parameter ENTSEL = 2,
		      parameter ENTNUM = 4
		     )
  (
   input wire [ENTNUM-1:0] in,
   output reg [ENTSEL-1:0] out,
   output reg 		   en
   );

   integer 		   i;
   always @ (*) begin
      out = 0;
      en = 0;
      for (i = ENTNUM-1; i >= 0 ; i = i - 1) begin
	 if (in[i]) begin
	    out = i;
	    en = 1;
	 end
      end
   end
   
endmodule
module search_begin #(
		      parameter ENTSEL = 2,
		      parameter ENTNUM = 4
		     )
  (
   input wire [ENTNUM-1:0] in,
   output reg [ENTSEL-1:0] out,
   output reg 		   en
   );


   integer 		   i;
   always @ (*) begin
      out = 0;
      en = 0;
      for (i = ENTNUM-1; i >= 0 ; i = i - 1) begin
	 if (in[i]) begin
	    out = i;
	    en = 1;
	 end
      end
   end
   
endmodule