data/full_repos/permissive/185658197/src/step-3/verilog/multiplier.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/185658197/src/step-3/verilog/multiplier.v:83: Cell has missing pin: \'c\'\n  Subtractor #(.bits(16)) final_subtractor (\n                          ^~~~~~~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Subtractor #(parameter bits = 1) (
    input [(bits-1):0] a,
    input [(bits-1):0] b,
    output [(bits-1):0] d,
    output c
);
    wire [bits:0] temp;
    assign temp = a - b;
    assign d = temp[(bits - 1):0];
    assign c = temp[bits];
endmodule
module Subtractor #(parameter bits = 1) (
    input [(bits-1):0] a,
    input [(bits-1):0] b,
    output [(bits-1):0] d,
    output c
);

    wire [bits:0] temp;
    assign temp = a - b;
    assign d = temp[(bits - 1):0];
    assign c = temp[bits];
endmodule