data/full_repos/permissive/161526648/SingleCycle.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:300: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                      : ... In instance SingleCycle.alu\n    result = ALUsrc1 < ALUsrc2;  \n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:227: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                      : ... In instance SingleCycle.ImExtend\n assign out = $signed(in);\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module InstructionMemory(ReadAddress,Instruction);
	input [31:0]ReadAddress;
	output reg [31:0]Instruction;
	reg [31:0]memory[29:0];
	initial begin
		memory[0] = 32'b00100000000010000000000000100000;
		memory[1] = 32'b00100000000010010000000000100111;
		memory[2] = 32'b00000001000010011000000000100100;
		memory[3] = 32'b00000001000010011000000000100101;
		memory[4] = 32'b10101100000100000000000000000100;
		memory[5] = 32'b10101100000010000000000000001000;
		memory[6] = 32'b00000001000010011000100000100000;
		memory[7] = 32'b00000001000010011001000000100010;
		memory[8] = 32'b00010010001100100000000000001001;
		memory[9] = 32'b10001100000100010000000000000100;
		memory[10]= 32'b00110010001100100000000000011000;
		memory[11] =32'b00010010001100100000000000001001;
		memory[12] =32'b10001100000100110000000000001000;
		memory[13] =32'b00010010000100110000000000001010;
		memory[14] =32'b00000010010100011010000000101010;
		memory[15] =32'b00010010100000000000000000001111;
		memory[16] =32'b00000010001000001001000000100000;
		memory[17] =32'b00001000000000000000000000001110;
		memory[18] =32'b00100000000010000000000000000000;
		memory[19] =32'b00100000000010010000000000000000;
		memory[20] =32'b00001000000000000000000000011111;
		memory[21] =32'b00100000000010000000000000000001;
		memory[22] =32'b00100000000010010000000000000001;
		memory[23] =32'b00001000000000000000000000011111;
		memory[24] =32'b00100000000010000000000000000010;
		memory[25] =32'b00100000000010010000000000000010;
		memory[26] =32'b00001000000000000000000000011111;
		memory[27] =32'b00100000000010000000000000000011;
		memory[28] =32'b00100000000010010000000000000011;
		memory[29] =32'b00001000000000000000000000011111;

	end
	always @(ReadAddress) begin
		Instruction = memory[ReadAddress/4];
	end
endmodule
module InstructionMemory(ReadAddress,Instruction);

	input [31:0]ReadAddress;
	output reg [31:0]Instruction;
	reg [31:0]memory[29:0];
	initial begin
		memory[0] = 32'b00100000000010000000000000100000;
		memory[1] = 32'b00100000000010010000000000100111;
		memory[2] = 32'b00000001000010011000000000100100;
		memory[3] = 32'b00000001000010011000000000100101;
		memory[4] = 32'b10101100000100000000000000000100;
		memory[5] = 32'b10101100000010000000000000001000;
		memory[6] = 32'b00000001000010011000100000100000;
		memory[7] = 32'b00000001000010011001000000100010;
		memory[8] = 32'b00010010001100100000000000001001;
		memory[9] = 32'b10001100000100010000000000000100;
		memory[10]= 32'b00110010001100100000000000011000;
		memory[11] =32'b00010010001100100000000000001001;
		memory[12] =32'b10001100000100110000000000001000;
		memory[13] =32'b00010010000100110000000000001010;
		memory[14] =32'b00000010010100011010000000101010;
		memory[15] =32'b00010010100000000000000000001111;
		memory[16] =32'b00000010001000001001000000100000;
		memory[17] =32'b00001000000000000000000000001110;
		memory[18] =32'b00100000000010000000000000000000;
		memory[19] =32'b00100000000010010000000000000000;
		memory[20] =32'b00001000000000000000000000011111;
		memory[21] =32'b00100000000010000000000000000001;
		memory[22] =32'b00100000000010010000000000000001;
		memory[23] =32'b00001000000000000000000000011111;
		memory[24] =32'b00100000000010000000000000000010;
		memory[25] =32'b00100000000010010000000000000010;
		memory[26] =32'b00001000000000000000000000011111;
		memory[27] =32'b00100000000010000000000000000011;
		memory[28] =32'b00100000000010010000000000000011;
		memory[29] =32'b00001000000000000000000000011111;

	end
	always @(ReadAddress) begin
		Instruction = memory[ReadAddress/4];
	end
endmodule