data/full_repos/permissive/109846502/main_controllertb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/main_controllertb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  forever #7 lcd_finish = ~lcd_finish;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_controllertb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #20 rst = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_controllertb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  forever #1 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/109846502/main_controllertb.v:33: Cannot find file containing module: \'main_controller\'\n main_controller uut (\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main_controller\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main_controller.v\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main_controller.sv\n             main_controller\n             main_controller.v\n             main_controller.sv\n             obj_dir/main_controller\n             obj_dir/main_controller.v\n             obj_dir/main_controller.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_controllertb;


	reg rst;
	reg clk;
	reg lcd_finish;


	main_controller uut (
		.rst(rst), 
		.clk(clk), 
		.lcd_finish(lcd_finish)
	);

	initial begin
		lcd_finish = 1'b1;
		forever #7 lcd_finish = ~lcd_finish;
	end
	
	initial begin
		clk = 1'b0;
		rst = 1'b1;
		#20 rst = 1'b0;
		forever #1 clk = ~clk;
	end
endmodule
module main_controllertb;



	reg rst;
	reg clk;
	reg lcd_finish;


	main_controller uut (
		.rst(rst), 
		.clk(clk), 
		.lcd_finish(lcd_finish)
	);

	initial begin
		lcd_finish = 1'b1;
		forever #7 lcd_finish = ~lcd_finish;
	end
	
	initial begin
		clk = 1'b0;
		rst = 1'b1;
		#20 rst = 1'b0;
		forever #1 clk = ~clk;
	end
endmodule