data/full_repos/permissive/122184933/FPGA/dphy.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/dphy.v:27: Signal definition not found, creating implicitly: \'d_hs_rdy\'\n                                                                      : ... Suggested alternative: \'d_hs_mode\'\nassign c_enable = !(d_hs_rdy) | enable;\n                    ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/dphy.v:27: Signal definition not found, creating implicitly: \'c_enable\'\n                                                                      : ... Suggested alternative: \'enable\'\nassign c_enable = !(d_hs_rdy) | enable;\n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/dphy.v:29: Signal definition not found, creating implicitly: \'d_enable\'\n                                                                      : ... Suggested alternative: \'c_enable\'\nassign d_enable = enable;\n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/dphy.v:31: Signal definition not found, creating implicitly: \'d_lane_idle\'\nassign c_hs_req = c_hs_mode | !d_lane_idle;\n                               ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/dphy.v:31: Signal definition not found, creating implicitly: \'c_hs_req\'\nassign c_hs_req = c_hs_mode | !d_lane_idle;\n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/dphy.v:33: Signal definition not found, creating implicitly: \'c_hs_rdy\'\n                                                                      : ... Suggested alternative: \'d_hs_rdy\'\nassign d_hs_req = d_hs_mode & c_hs_rdy;\n                              ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/dphy.v:33: Signal definition not found, creating implicitly: \'d_hs_req\'\n                                                                      : ... Suggested alternative: \'c_hs_req\'\nassign d_hs_req = d_hs_mode & c_hs_rdy;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/122184933/FPGA/dphy.v:36: Cannot find file containing module: \'delay\'\ndelay # (.LENGTH(2)) delay_clock_lane (.a(bit_clk), .o(bit_clk_del));\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/delay\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/delay.v\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/delay.sv\n             delay\n             delay.v\n             delay.sv\n             obj_dir/delay\n             obj_dir/delay.v\n             obj_dir/delay.sv\n%Error: data/full_repos/permissive/122184933/FPGA/dphy.v:39: Cannot find file containing module: \'clock_lane\'\nclock_lane clock_lane_i (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/122184933/FPGA/dphy.v:54: Cannot find file containing module: \'data_lane\'\ndata_lane data_lane_i (\n^~~~~~~~~\n%Error: Exiting due to 3 error(s), 7 warning(s)\n'
module dphy (

	input wire byte_clk, 

	input wire bit_clk, 

	input wire byte_rst, bit_rst,


	input wire [7:0] data,

	input wire enable,

	output wire ack,
	

	input wire c_hs_mode, d_hs_mode,
	

	output wire c_lp_p, c_lp_n, c_hs,

	output wire d_lp_p, d_lp_n, d_hs
);


assign c_enable = !(d_hs_rdy) | enable;

assign d_enable = enable;

assign c_hs_req = c_hs_mode | !d_lane_idle;

assign d_hs_req = d_hs_mode & c_hs_rdy;


delay # (.LENGTH(2)) delay_clock_lane (.a(bit_clk), .o(bit_clk_del));


clock_lane clock_lane_i (

	.byte_clk(byte_clk), .bit_clk(bit_clk_del),

	.byte_rst(byte_rst), .bit_rst(bit_rst),
	

	.enable(c_enable),

	.hs_req(c_hs_req), .hs_rdy(c_hs_rdy), .lane_idle(c_lane_idle),

	.lp_p(c_lp_p), .lp_n(c_lp_n), .hs(c_hs)
);


data_lane data_lane_i (

	.byte_clk(byte_clk), .bit_clk(bit_clk),

	.byte_rst(byte_rst), .bit_rst(bit_rst),
	

	.data(data), .enable(d_enable), .ack(ack),

	.hs_req(d_hs_req), .hs_rdy(d_hs_rdy), .lane_idle(d_lane_idle),

	.lp_p(d_lp_p), .lp_n(d_lp_n), .hs(d_hs)
);


endmodule
module dphy (

	input wire byte_clk, 

	input wire bit_clk, 

	input wire byte_rst, bit_rst,


	input wire [7:0] data,

	input wire enable,

	output wire ack,
	

	input wire c_hs_mode, d_hs_mode,
	

	output wire c_lp_p, c_lp_n, c_hs,

	output wire d_lp_p, d_lp_n, d_hs
);



assign c_enable = !(d_hs_rdy) | enable;

assign d_enable = enable;

assign c_hs_req = c_hs_mode | !d_lane_idle;

assign d_hs_req = d_hs_mode & c_hs_rdy;


delay # (.LENGTH(2)) delay_clock_lane (.a(bit_clk), .o(bit_clk_del));


clock_lane clock_lane_i (

	.byte_clk(byte_clk), .bit_clk(bit_clk_del),

	.byte_rst(byte_rst), .bit_rst(bit_rst),
	

	.enable(c_enable),

	.hs_req(c_hs_req), .hs_rdy(c_hs_rdy), .lane_idle(c_lane_idle),

	.lp_p(c_lp_p), .lp_n(c_lp_n), .hs(c_hs)
);


data_lane data_lane_i (

	.byte_clk(byte_clk), .bit_clk(bit_clk),

	.byte_rst(byte_rst), .bit_rst(bit_rst),
	

	.data(data), .enable(d_enable), .ack(ack),

	.hs_req(d_hs_req), .hs_rdy(d_hs_rdy), .lane_idle(d_lane_idle),

	.lp_p(d_lp_p), .lp_n(d_lp_n), .hs(d_hs)
);


endmodule