data/full_repos/permissive/138580357/test/BtoH.v
1: b'%Warning-WIDTH: data/full_repos/permissive/138580357/test/BtoH.v:6: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                  : ... In instance BtoH\ncase(i4)\n^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/138580357/test/BtoH.v:6: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                  : ... In instance BtoH\ncase(i4)\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/138580357/test/BtoH.v:6: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n                                                                  : ... In instance BtoH\ncase(i4)\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/138580357/test/BtoH.v:6: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n                                                                  : ... In instance BtoH\ncase(i4)\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/138580357/test/BtoH.v:6: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                  : ... In instance BtoH\ncase(i4)\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/138580357/test/BtoH.v:6: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h5\' generates 4 bits.\n                                                                  : ... In instance BtoH\ncase(i4)\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/138580357/test/BtoH.v:6: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h6\' generates 4 bits.\n                                                                  : ... In instance BtoH\ncase(i4)\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/138580357/test/BtoH.v:6: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h7\' generates 4 bits.\n                                                                  : ... In instance BtoH\ncase(i4)\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/138580357/test/BtoH.v:6: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                  : ... In instance BtoH\ncase(i4)\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/138580357/test/BtoH.v:6: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                  : ... In instance BtoH\ncase(i4)\n^~~~\n%Error: Exiting due to 10 warning(s)\n'
module BtoH(i4,o7);
input[4:0] i4;
output reg[6:0] o7;
always@(i4)
begin
case(i4)
4'd0:o7=7'b1000000;
4'd1:o7=7'b1111001;
4'd2:o7=7'b0100100;
4'd3:o7=7'b0100000;
4'd4:o7=7'b0011001;
4'd5:o7=7'b0010010;
4'd6:o7=7'b0000010;
4'd7:o7=7'b1111000;
4'd8:o7=7'b0000000;
4'd9:o7=7'b0010000;
default:o7=7'b1111111;
endcase
end
endmodule
module BtoH(i4,o7);

input[4:0] i4;
output reg[6:0] o7;
always@(i4)
begin
case(i4)
4'd0:o7=7'b1000000;
4'd1:o7=7'b1111001;
4'd2:o7=7'b0100100;
4'd3:o7=7'b0100000;
4'd4:o7=7'b0011001;
4'd5:o7=7'b0010010;
4'd6:o7=7'b0000010;
4'd7:o7=7'b1111000;
4'd8:o7=7'b0000000;
4'd9:o7=7'b0010000;
default:o7=7'b1111111;
endcase
end
endmodule