data/full_repos/permissive/149769583/sram_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;   \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #10 we_a = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 6;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = 7;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10 we_a = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10 we_b = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10 addr_b = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10 addr_b = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10 addr_b = 2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 addr_b = 3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10 addr_b = 4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10 addr_b = 5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10 addr_b = 6;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/sram_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10 addr_b = 7;\n        ^\n%Error: data/full_repos/permissive/149769583/sram_tb.v:52: Cannot find file containing module: \'sram\'\n    sram DUT (\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/sram\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/sram.v\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/sram.sv\n             sram\n             sram.v\n             sram.sv\n             obj_dir/sram\n             obj_dir/sram.v\n             obj_dir/sram.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sram_basic_testbench();
    parameter ADDR_WIDTH = 3;
    parameter DATA_WIDTH = 34;
    parameter DEPTH = 8;

    reg clk;
    reg [ADDR_WIDTH-1:0] address,addr_b;
    reg we_a, we_b;
    reg [DATA_WIDTH-1:0] data_a,data_b;
    wire [DATA_WIDTH-1:0] q_a,q_b;

    always begin
        #5 clk = ~clk;
    end

    initial begin
        $display("sram test bench");
        clk = 1;

        #10 we_a = 1;
        address = 0;
        data_a = {8'd10,8'd0,8'd0,10'd245};
        #10 address = 1;
        data_a = {8'd0,8'd10,8'd0,10'd175};
        #10 address = 2;
        data_a = {8'd10,8'd0,8'd0,10'd495};
        #10 address = 3;
        data_a = {8'd10,8'd0,8'd0,10'd485};
        #10 address = 4;
        data_a = {8'd0,8'd10,8'd0,10'd165};
        #10 address = 5;
        data_a = {8'd0,8'd10,8'd0,10'd155};
        #10 address = 6;
        data_a = {8'd0,8'd0,8'd10,10'd595};
        #10 address = 7;
        data_a = {8'd0,8'd0,8'd10,10'd695};

        #10 we_a = 0;
        #10 we_b = 0;
        #10 addr_b = 0;
        #10 addr_b = 1;
        #10 addr_b = 2;
        #10 addr_b = 3;
        #10 addr_b = 4;
        #10 addr_b = 5;
        #10 addr_b = 6;
        #10 addr_b = 7;
    end


    sram DUT (
        .clk(clk),
        .addr_a(address),
        .addr_b(addr_b),
        .data_a(data_a),
        .data_b(data_b),
        .we_a(we_a),
        .q_b(q_b)
        );

endmodule
module sram_basic_testbench();

    parameter ADDR_WIDTH = 3;
    parameter DATA_WIDTH = 34;
    parameter DEPTH = 8;

    reg clk;
    reg [ADDR_WIDTH-1:0] address,addr_b;
    reg we_a, we_b;
    reg [DATA_WIDTH-1:0] data_a,data_b;
    wire [DATA_WIDTH-1:0] q_a,q_b;

    always begin
        #5 clk = ~clk;
    end

    initial begin
        $display("sram test bench");
        clk = 1;

        #10 we_a = 1;
        address = 0;
        data_a = {8'd10,8'd0,8'd0,10'd245};
        #10 address = 1;
        data_a = {8'd0,8'd10,8'd0,10'd175};
        #10 address = 2;
        data_a = {8'd10,8'd0,8'd0,10'd495};
        #10 address = 3;
        data_a = {8'd10,8'd0,8'd0,10'd485};
        #10 address = 4;
        data_a = {8'd0,8'd10,8'd0,10'd165};
        #10 address = 5;
        data_a = {8'd0,8'd10,8'd0,10'd155};
        #10 address = 6;
        data_a = {8'd0,8'd0,8'd10,10'd595};
        #10 address = 7;
        data_a = {8'd0,8'd0,8'd10,10'd695};

        #10 we_a = 0;
        #10 we_b = 0;
        #10 addr_b = 0;
        #10 addr_b = 1;
        #10 addr_b = 2;
        #10 addr_b = 3;
        #10 addr_b = 4;
        #10 addr_b = 5;
        #10 addr_b = 6;
        #10 addr_b = 7;
    end


    sram DUT (
        .clk(clk),
        .addr_a(address),
        .addr_b(addr_b),
        .data_a(data_a),
        .data_b(data_b),
        .we_a(we_a),
        .q_b(q_b)
        );

endmodule