data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v
None: at end of input
1: b'%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:9: Cannot find include file: riscv_defs.v\n`include "riscv_defs.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v.v\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v.sv\n             riscv_defs.v\n             riscv_defs.v.v\n             riscv_defs.v.sv\n             obj_dir/riscv_defs.v\n             obj_dir/riscv_defs.v.v\n             obj_dir/riscv_defs.v.sv\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:23: Define or directive not defined: \'`RV_XLEN\'\n        output reg  [`RV_XLEN-1:0] lsq_reg_data_o,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:32: Define or directive not defined: \'`RV_XLEN\'\n        input  wire [`RV_XLEN-1:0] exs_regs2_data_i,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:33: Define or directive not defined: \'`RV_XLEN\'\n        input  wire [`RV_XLEN-1:0] exs_addr_i,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:37: Define or directive not defined: \'`RV_XLEN\'\n        output wire [`RV_XLEN-1:0] plic_int_rspdata_o,  \n                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:44: Define or directive not defined: \'`RV_XLEN\'\n        output wire [`RV_XLEN-1:0] dreqaddr_o,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:45: Define or directive not defined: \'`RV_XLEN\'\n        output wire [`RV_XLEN-1:0] dreqdata_o,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:50: Define or directive not defined: \'`RV_XLEN\'\n        input  wire [`RV_XLEN-1:0] drspdata_i\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:58: Define or directive not defined: \'`RV_XLEN\'\n    reg               [`RV_XLEN-1:0] exs_regs2_data_justified;\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:60: Define or directive not defined: \'`RV_XLEN\'\n    parameter C_REQ_FIFO_WIDTH = `RV_XLEN + `RV_XLEN + 3 + 2 + 1;\n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:60: Define or directive not defined: \'`RV_XLEN\'\n    parameter C_REQ_FIFO_WIDTH = `RV_XLEN + `RV_XLEN + 3 + 2 + 1;\n                                            ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:65: Define or directive not defined: \'`RV_XLEN\'\n    wire              [`RV_XLEN-1:0] req_fifo_rd_data_addr;\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:66: Define or directive not defined: \'`RV_XLEN\'\n    wire              [`RV_XLEN-1:0] req_fifo_rd_data_data;\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:72: Define or directive not defined: \'`RV_XLEN_X\'\n    parameter C_RSP_CTRL_FIFO_WIDTH = `RV_XLEN_X-3 + 5 + 3;\n                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:73: Define or directive not defined: \'`RV_XLEN_X\'\n    wire            [`RV_XLEN_X-4:0] req_ctrl_fifo_rd_data_alignment;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:82: Define or directive not defined: \'`RV_XLEN\'\n    wire              [`RV_XLEN-1:0] rsp_data_fifo_wr_data;\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:83: Define or directive not defined: \'`RV_XLEN\'\n    wire              [`RV_XLEN-1:0] rsp_data_fifo_rd_data;\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:85: Define or directive not defined: \'`RV_XLEN\'\n    reg               [`RV_XLEN-1:0] rsp_data_justified;\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:136: Define or directive not defined: \'`RV_XLEN\'\n                                 { `RV_XLEN-5 {1\'b0} }, exs_regd_addr_i,\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:149: Define or directive not defined: \'`RV_XLEN\'\n    assign req_fifo_rd_data_addr   = req_fifo_rd_data[`RV_XLEN + 3 + 2 + 1 +: `RV_XLEN];\n                                                      ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:149: Define or directive not defined: \'`RV_XLEN\'\n    assign req_fifo_rd_data_addr   = req_fifo_rd_data[`RV_XLEN + 3 + 2 + 1 +: `RV_XLEN];\n                                                                              ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:149: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign req_fifo_rd_data_addr   = req_fifo_rd_data[`RV_XLEN + 3 + 2 + 1 +: `RV_XLEN];\n                                                                                      ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:150: Define or directive not defined: \'`RV_XLEN\'\n    assign req_fifo_rd_data_data   = req_fifo_rd_data[           3 + 2 + 1 +: `RV_XLEN];\n                                                                              ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:150: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign req_fifo_rd_data_data   = req_fifo_rd_data[           3 + 2 + 1 +: `RV_XLEN];\n                                                                                      ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:181: Define or directive not defined: \'`RV_XLEN_X\'\n    assign req_ctrl_fifo_wr_data = { req_fifo_rd_data_addr[`RV_XLEN_X-4:0], req_fifo_rd_data_regd, req_fifo_rd_data_funct3 };\n                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:183: Define or directive not defined: \'`RV_XLEN_X\'\n    assign req_ctrl_fifo_rd_data_alignment = req_ctrl_fifo_rd_data[8 +: `RV_XLEN_X-3];\n                                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:212: Define or directive not defined: \'`RV_XLEN\'\n    assign rsp_data_fifo_wr_data = (drsprerr_i ? { `RV_XLEN {1\'b0} } : drspdata_i);  \n                                                   ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:217: Define or directive not defined: \'`RV_XLEN\'\n            .C_FIFO_WIDTH       (`RV_XLEN),\n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:243: Define or directive not defined: \'`RV_XLEN\'\n                    lsq_reg_data_o = { { `RV_XLEN-8 {1\'b1} }, rsp_data_justified[7:0] };\n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:245: Define or directive not defined: \'`RV_XLEN\'\n                    lsq_reg_data_o = { { `RV_XLEN-8 {1\'b0} }, rsp_data_justified[7:0] };\n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:250: Define or directive not defined: \'`RV_XLEN\'\n                    lsq_reg_data_o = { { `RV_XLEN-16 {1\'b1} }, rsp_data_justified[15:0] };\n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:252: Define or directive not defined: \'`RV_XLEN\'\n                    lsq_reg_data_o = { { `RV_XLEN-16 {1\'b0} }, rsp_data_justified[15:0] };\n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:256: Define or directive not defined: \'`RV_XLEN\'\n                if (`RV_XLEN == 64) begin  \n                    ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:256: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n                if (`RV_XLEN == 64) begin  \n                             ^~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:258: Define or directive not defined: \'`RV_XLEN\'\n                        lsq_reg_data_o = { { `RV_XLEN-32 {1\'b1} }, rsp_data_justified[31:0] };\n                                             ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:260: Define or directive not defined: \'`RV_XLEN\'\n                        lsq_reg_data_o = { { `RV_XLEN-32 {1\'b0} }, rsp_data_justified[31:0] };\n                                             ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:270: Define or directive not defined: \'`RV_XLEN\'\n                lsq_reg_data_o = { { `RV_XLEN-8 {1\'b0} }, rsp_data_justified[7:0] };\n                                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:273: Define or directive not defined: \'`RV_XLEN\'\n                lsq_reg_data_o = { { `RV_XLEN-16 {1\'b0} }, rsp_data_justified[15:0] };\n                                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:276: Define or directive not defined: \'`RV_XLEN\'\n                if (`RV_XLEN == 64) begin  \n                    ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:277: Define or directive not defined: \'`RV_XLEN\'\n                    lsq_reg_data_o = { { `RV_XLEN-32 {1\'b0} }, rsp_data_justified[31:0] };\n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:290: Define or directive not defined: \'`RV_XLEN\'\n            2\'b01   : rsp_data_justified = {  8\'b0, rsp_data_fifo_rd_data[`RV_XLEN-1: 8] };\n                                                                          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:291: Define or directive not defined: \'`RV_XLEN\'\n            2\'b10   : rsp_data_justified = { 16\'b0, rsp_data_fifo_rd_data[`RV_XLEN-1:16] };\n                                                                          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:292: Define or directive not defined: \'`RV_XLEN\'\n            2\'b11   : rsp_data_justified = { 24\'b0, rsp_data_fifo_rd_data[`RV_XLEN-1:24] };\n                                                                          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:302: Define or directive not defined: \'`RV_ASSERT\'\n        `RV_ASSERT((`RV_XLEN == 32 || `RV_XLEN == 64), "Invalid value for RV_XLEN.  Must be 32 or 64.")\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:302: Define or directive not defined: \'`RV_XLEN\'\n        `RV_ASSERT((`RV_XLEN == 32 || `RV_XLEN == 64), "Invalid value for RV_XLEN.  Must be 32 or 64.")\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_lsqueue.v:302: Define or directive not defined: \'`RV_XLEN\'\n        `RV_ASSERT((`RV_XLEN == 32 || `RV_XLEN == 64), "Invalid value for RV_XLEN.  Must be 32 or 64.")\n                                      ^~~~~~~~\n%Error: Cannot continue\n'
module merlin_lsqueue
    #(
        parameter C_FIFO_PASSTHROUGH = 0,
        parameter C_FIFO_DEPTH_X     = 2
    )
    (

        input  wire                clk_i,
        input  wire                reset_i,

        output wire                lsq_reg_wr_o,
        output wire          [4:0] lsq_reg_addr_o,
        output reg  [`RV_XLEN-1:0] lsq_reg_data_o,

        output wire                exs_full_o,
        output wire                exs_empty_o,
        input  wire                exs_lq_wr_i,
        input  wire                exs_sq_wr_i,
        input  wire          [1:0] exs_hpl_i,
        input  wire          [2:0] exs_funct3_i,
        input  wire          [4:0] exs_regd_addr_i,
        input  wire [`RV_XLEN-1:0] exs_regs2_data_i,
        input  wire [`RV_XLEN-1:0] exs_addr_i,

        output wire                plic_int_laf_o,
        output wire                plic_int_saf_o,
        output wire [`RV_XLEN-1:0] plic_int_rspdata_o,

        input  wire                dreqready_i,
        output wire                dreqvalid_o,
        output wire          [1:0] dreqsize_o,
        output wire                dreqwrite_o,
        output wire          [1:0] dreqhpl_o,
        output wire [`RV_XLEN-1:0] dreqaddr_o,
        output wire [`RV_XLEN-1:0] dreqdata_o,
        output wire                drspready_o,
        input  wire                drspvalid_i,
        input  wire                drsprerr_i,
        input  wire                drspwerr_i,
        input  wire [`RV_XLEN-1:0] drspdata_i
    );




    wire                             request;

    reg               [`RV_XLEN-1:0] exs_regs2_data_justified;

    parameter C_REQ_FIFO_WIDTH = `RV_XLEN + `RV_XLEN + 3 + 2 + 1;
    wire                             req_fifo_wr;
    reg       [C_REQ_FIFO_WIDTH-1:0] req_fifo_wr_data;
    wire      [C_REQ_FIFO_WIDTH-1:0] req_fifo_rd_data;
    wire                             req_fifo_empty;
    wire              [`RV_XLEN-1:0] req_fifo_rd_data_addr;
    wire              [`RV_XLEN-1:0] req_fifo_rd_data_data;
    wire                       [4:0] req_fifo_rd_data_regd;
    wire                       [2:0] req_fifo_rd_data_funct3;
    wire                       [1:0] req_fifo_rd_data_hpl;
    wire                             req_fifo_rd_data_wr;

    parameter C_RSP_CTRL_FIFO_WIDTH = `RV_XLEN_X-3 + 5 + 3;
    wire            [`RV_XLEN_X-4:0] req_ctrl_fifo_rd_data_alignment;
    wire                       [2:0] req_ctrl_fifo_rd_data_funct3;
    wire                             rsp_ctrl_fifo_empty;
    wire                             rsp_ctrl_fifo_full;
    wire [C_RSP_CTRL_FIFO_WIDTH-1:0] req_ctrl_fifo_wr_data;
    wire [C_RSP_CTRL_FIFO_WIDTH-1:0] req_ctrl_fifo_rd_data;

    wire                             rsp_data_fifo_empty;
    wire                             rsp_data_fifo_full;
    wire              [`RV_XLEN-1:0] rsp_data_fifo_wr_data;
    wire              [`RV_XLEN-1:0] rsp_data_fifo_rd_data;

    reg               [`RV_XLEN-1:0] rsp_data_justified;






    assign request = dreqvalid_o & dreqready_i;

    assign lsq_reg_wr_o = ~rsp_data_fifo_empty;

    assign exs_empty_o = rsp_ctrl_fifo_empty & req_fifo_empty;

    assign plic_int_laf_o     = drspready_o & drsprerr_i;
    assign plic_int_saf_o     = drspready_o & drspwerr_i;
    assign plic_int_rspdata_o = drspdata_i;

    assign dreqvalid_o  = ~req_fifo_empty & ~rsp_ctrl_fifo_full;
    assign dreqsize_o   =  req_fifo_rd_data_funct3[1:0];
    assign dreqwrite_o  =  req_fifo_rd_data_wr;
    assign dreqhpl_o    =  req_fifo_rd_data_hpl;
    assign dreqaddr_o   =  req_fifo_rd_data_addr;
    assign dreqdata_o   =  req_fifo_rd_data_data;

    assign drspready_o = drspvalid_i & (~rsp_data_fifo_full | drspwerr_i);





    always @ (*) begin
        case (exs_funct3_i)
            3'b000  : exs_regs2_data_justified = { exs_regs2_data_i[ 7:0],
                                                   exs_regs2_data_i[ 7:0],
                                                   exs_regs2_data_i[ 7:0],
                                                   exs_regs2_data_i[ 7:0] };
            3'b001  : exs_regs2_data_justified = { exs_regs2_data_i[15:0],
                                                   exs_regs2_data_i[15:0] };
            default : exs_regs2_data_justified = exs_regs2_data_i;
        endcase
    end





    assign req_fifo_wr = exs_lq_wr_i | exs_sq_wr_i;

    always @ (*) begin
        if (exs_lq_wr_i) begin
            req_fifo_wr_data = { exs_addr_i,
                                 { `RV_XLEN-5 {1'b0} }, exs_regd_addr_i,
                                 exs_funct3_i,
                                 exs_hpl_i,
                                 exs_sq_wr_i };
        end else begin
            req_fifo_wr_data = { exs_addr_i,
                                 exs_regs2_data_justified,
                                 exs_funct3_i,
                                 exs_hpl_i,
                                 exs_sq_wr_i };
        end
    end

    assign req_fifo_rd_data_addr   = req_fifo_rd_data[`RV_XLEN + 3 + 2 + 1 +: `RV_XLEN];
    assign req_fifo_rd_data_data   = req_fifo_rd_data[           3 + 2 + 1 +: `RV_XLEN];
    assign req_fifo_rd_data_regd   = req_fifo_rd_data[           3 + 2 + 1 +:        5];
    assign req_fifo_rd_data_funct3 = req_fifo_rd_data[               2 + 1 +:        3];
    assign req_fifo_rd_data_hpl    = req_fifo_rd_data[                   1 +:        2];
    assign req_fifo_rd_data_wr     = req_fifo_rd_data[0];

    merlin_fifo
        #(
            .C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
            .C_FIFO_WIDTH       (C_REQ_FIFO_WIDTH),
            .C_FIFO_DEPTH_X     (C_FIFO_DEPTH_X)
        ) i_req_merlin_fifo (

            .clk_i              (clk_i),
            .reset_i            (reset_i),

            .flush_i            (1'b0),
            .empty_o            (req_fifo_empty),
            .full_o             (exs_full_o),

            .wr_i               (req_fifo_wr),
            .din_i              (req_fifo_wr_data),

            .rd_i               (request),
            .dout_o             (req_fifo_rd_data)
        );





    assign req_ctrl_fifo_wr_data = { req_fifo_rd_data_addr[`RV_XLEN_X-4:0], req_fifo_rd_data_regd, req_fifo_rd_data_funct3 };

    assign req_ctrl_fifo_rd_data_alignment = req_ctrl_fifo_rd_data[8 +: `RV_XLEN_X-3];
    assign lsq_reg_addr_o                  = req_ctrl_fifo_rd_data[3 +: 5];
    assign req_ctrl_fifo_rd_data_funct3    = req_ctrl_fifo_rd_data[0 +: 3];

    merlin_fifo
        #(
            .C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
            .C_FIFO_WIDTH       (C_RSP_CTRL_FIFO_WIDTH),
            .C_FIFO_DEPTH_X     (C_FIFO_DEPTH_X)
        ) i_rsp_ctrl_merlin_fifo (

            .clk_i              (clk_i),
            .reset_i            (reset_i),

            .flush_i            (1'b0),
            .empty_o            (rsp_ctrl_fifo_empty),
            .full_o             (rsp_ctrl_fifo_full),

            .wr_i               (request & ~req_fifo_rd_data_wr),
            .din_i              (req_ctrl_fifo_wr_data),

            .rd_i               (lsq_reg_wr_o),
            .dout_o             (req_ctrl_fifo_rd_data)
        );





    assign rsp_data_fifo_wr_data = (drsprerr_i ? { `RV_XLEN {1'b0} } : drspdata_i);

    merlin_fifo
        #(
            .C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
            .C_FIFO_WIDTH       (`RV_XLEN),
            .C_FIFO_DEPTH_X     (C_FIFO_DEPTH_X)
        ) i_rsp_data_merlin_fifo (

            .clk_i              (clk_i),
            .reset_i            (reset_i),

            .flush_i            (1'b0),
            .empty_o            (rsp_data_fifo_empty),
            .full_o             (rsp_data_fifo_full),

            .wr_i               (drspready_o & ~drspwerr_i),
            .din_i              (rsp_data_fifo_wr_data),

            .rd_i               (lsq_reg_wr_o),
            .dout_o             (rsp_data_fifo_rd_data)
        );





    always @ (*) begin
        case (req_ctrl_fifo_rd_data_funct3)
            3'b000 : begin
                if (rsp_data_justified[7]) begin
                    lsq_reg_data_o = { { `RV_XLEN-8 {1'b1} }, rsp_data_justified[7:0] };
                end else begin
                    lsq_reg_data_o = { { `RV_XLEN-8 {1'b0} }, rsp_data_justified[7:0] };
                end
            end
            3'b001 : begin
                if (rsp_data_justified[15]) begin
                    lsq_reg_data_o = { { `RV_XLEN-16 {1'b1} }, rsp_data_justified[15:0] };
                end else begin
                    lsq_reg_data_o = { { `RV_XLEN-16 {1'b0} }, rsp_data_justified[15:0] };
                end
            end
            3'b010 : begin
                if (`RV_XLEN == 64) begin
                    if (rsp_data_justified[31]) begin
                        lsq_reg_data_o = { { `RV_XLEN-32 {1'b1} }, rsp_data_justified[31:0] };
                    end else begin
                        lsq_reg_data_o = { { `RV_XLEN-32 {1'b0} }, rsp_data_justified[31:0] };
                    end
                end else begin
                    lsq_reg_data_o = rsp_data_justified;
                end
            end
            3'b011 : begin
                lsq_reg_data_o = rsp_data_justified;
            end
            3'b100 : begin
                lsq_reg_data_o = { { `RV_XLEN-8 {1'b0} }, rsp_data_justified[7:0] };
            end
            3'b101 : begin
                lsq_reg_data_o = { { `RV_XLEN-16 {1'b0} }, rsp_data_justified[15:0] };
            end
            3'b110 : begin
                if (`RV_XLEN == 64) begin
                    lsq_reg_data_o = { { `RV_XLEN-32 {1'b0} }, rsp_data_justified[31:0] };
                end else begin
                    lsq_reg_data_o = rsp_data_justified;
                end
            end
            default : begin
                lsq_reg_data_o = rsp_data_justified;
            end
        endcase
    end

    always @ (*) begin
        case (req_ctrl_fifo_rd_data_alignment)
            2'b01   : rsp_data_justified = {  8'b0, rsp_data_fifo_rd_data[`RV_XLEN-1: 8] };
            2'b10   : rsp_data_justified = { 16'b0, rsp_data_fifo_rd_data[`RV_XLEN-1:16] };
            2'b11   : rsp_data_justified = { 24'b0, rsp_data_fifo_rd_data[`RV_XLEN-1:24] };
            default : rsp_data_justified = rsp_data_fifo_rd_data;
        endcase
    end





    initial begin
        `RV_ASSERT((`RV_XLEN == 32 || `RV_XLEN == 64), "Invalid value for RV_XLEN.  Must be 32 or 64.")
    end
endmodule
module merlin_lsqueue
    #(
        parameter C_FIFO_PASSTHROUGH = 0,
        parameter C_FIFO_DEPTH_X     = 2
    )
    (

        input  wire                clk_i,
        input  wire                reset_i,

        output wire                lsq_reg_wr_o,
        output wire          [4:0] lsq_reg_addr_o,
        output reg  [`RV_XLEN-1:0] lsq_reg_data_o,

        output wire                exs_full_o,
        output wire                exs_empty_o,
        input  wire                exs_lq_wr_i,
        input  wire                exs_sq_wr_i,
        input  wire          [1:0] exs_hpl_i,
        input  wire          [2:0] exs_funct3_i,
        input  wire          [4:0] exs_regd_addr_i,
        input  wire [`RV_XLEN-1:0] exs_regs2_data_i,
        input  wire [`RV_XLEN-1:0] exs_addr_i,

        output wire                plic_int_laf_o,
        output wire                plic_int_saf_o,
        output wire [`RV_XLEN-1:0] plic_int_rspdata_o,

        input  wire                dreqready_i,
        output wire                dreqvalid_o,
        output wire          [1:0] dreqsize_o,
        output wire                dreqwrite_o,
        output wire          [1:0] dreqhpl_o,
        output wire [`RV_XLEN-1:0] dreqaddr_o,
        output wire [`RV_XLEN-1:0] dreqdata_o,
        output wire                drspready_o,
        input  wire                drspvalid_i,
        input  wire                drsprerr_i,
        input  wire                drspwerr_i,
        input  wire [`RV_XLEN-1:0] drspdata_i
    );





    wire                             request;

    reg               [`RV_XLEN-1:0] exs_regs2_data_justified;

    parameter C_REQ_FIFO_WIDTH = `RV_XLEN + `RV_XLEN + 3 + 2 + 1;
    wire                             req_fifo_wr;
    reg       [C_REQ_FIFO_WIDTH-1:0] req_fifo_wr_data;
    wire      [C_REQ_FIFO_WIDTH-1:0] req_fifo_rd_data;
    wire                             req_fifo_empty;
    wire              [`RV_XLEN-1:0] req_fifo_rd_data_addr;
    wire              [`RV_XLEN-1:0] req_fifo_rd_data_data;
    wire                       [4:0] req_fifo_rd_data_regd;
    wire                       [2:0] req_fifo_rd_data_funct3;
    wire                       [1:0] req_fifo_rd_data_hpl;
    wire                             req_fifo_rd_data_wr;

    parameter C_RSP_CTRL_FIFO_WIDTH = `RV_XLEN_X-3 + 5 + 3;
    wire            [`RV_XLEN_X-4:0] req_ctrl_fifo_rd_data_alignment;
    wire                       [2:0] req_ctrl_fifo_rd_data_funct3;
    wire                             rsp_ctrl_fifo_empty;
    wire                             rsp_ctrl_fifo_full;
    wire [C_RSP_CTRL_FIFO_WIDTH-1:0] req_ctrl_fifo_wr_data;
    wire [C_RSP_CTRL_FIFO_WIDTH-1:0] req_ctrl_fifo_rd_data;

    wire                             rsp_data_fifo_empty;
    wire                             rsp_data_fifo_full;
    wire              [`RV_XLEN-1:0] rsp_data_fifo_wr_data;
    wire              [`RV_XLEN-1:0] rsp_data_fifo_rd_data;

    reg               [`RV_XLEN-1:0] rsp_data_justified;






    assign request = dreqvalid_o & dreqready_i;

    assign lsq_reg_wr_o = ~rsp_data_fifo_empty;

    assign exs_empty_o = rsp_ctrl_fifo_empty & req_fifo_empty;

    assign plic_int_laf_o     = drspready_o & drsprerr_i;
    assign plic_int_saf_o     = drspready_o & drspwerr_i;
    assign plic_int_rspdata_o = drspdata_i;

    assign dreqvalid_o  = ~req_fifo_empty & ~rsp_ctrl_fifo_full;
    assign dreqsize_o   =  req_fifo_rd_data_funct3[1:0];
    assign dreqwrite_o  =  req_fifo_rd_data_wr;
    assign dreqhpl_o    =  req_fifo_rd_data_hpl;
    assign dreqaddr_o   =  req_fifo_rd_data_addr;
    assign dreqdata_o   =  req_fifo_rd_data_data;

    assign drspready_o = drspvalid_i & (~rsp_data_fifo_full | drspwerr_i);





    always @ (*) begin
        case (exs_funct3_i)
            3'b000  : exs_regs2_data_justified = { exs_regs2_data_i[ 7:0],
                                                   exs_regs2_data_i[ 7:0],
                                                   exs_regs2_data_i[ 7:0],
                                                   exs_regs2_data_i[ 7:0] };
            3'b001  : exs_regs2_data_justified = { exs_regs2_data_i[15:0],
                                                   exs_regs2_data_i[15:0] };
            default : exs_regs2_data_justified = exs_regs2_data_i;
        endcase
    end





    assign req_fifo_wr = exs_lq_wr_i | exs_sq_wr_i;

    always @ (*) begin
        if (exs_lq_wr_i) begin
            req_fifo_wr_data = { exs_addr_i,
                                 { `RV_XLEN-5 {1'b0} }, exs_regd_addr_i,
                                 exs_funct3_i,
                                 exs_hpl_i,
                                 exs_sq_wr_i };
        end else begin
            req_fifo_wr_data = { exs_addr_i,
                                 exs_regs2_data_justified,
                                 exs_funct3_i,
                                 exs_hpl_i,
                                 exs_sq_wr_i };
        end
    end

    assign req_fifo_rd_data_addr   = req_fifo_rd_data[`RV_XLEN + 3 + 2 + 1 +: `RV_XLEN];
    assign req_fifo_rd_data_data   = req_fifo_rd_data[           3 + 2 + 1 +: `RV_XLEN];
    assign req_fifo_rd_data_regd   = req_fifo_rd_data[           3 + 2 + 1 +:        5];
    assign req_fifo_rd_data_funct3 = req_fifo_rd_data[               2 + 1 +:        3];
    assign req_fifo_rd_data_hpl    = req_fifo_rd_data[                   1 +:        2];
    assign req_fifo_rd_data_wr     = req_fifo_rd_data[0];

    merlin_fifo
        #(
            .C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
            .C_FIFO_WIDTH       (C_REQ_FIFO_WIDTH),
            .C_FIFO_DEPTH_X     (C_FIFO_DEPTH_X)
        ) i_req_merlin_fifo (

            .clk_i              (clk_i),
            .reset_i            (reset_i),

            .flush_i            (1'b0),
            .empty_o            (req_fifo_empty),
            .full_o             (exs_full_o),

            .wr_i               (req_fifo_wr),
            .din_i              (req_fifo_wr_data),

            .rd_i               (request),
            .dout_o             (req_fifo_rd_data)
        );





    assign req_ctrl_fifo_wr_data = { req_fifo_rd_data_addr[`RV_XLEN_X-4:0], req_fifo_rd_data_regd, req_fifo_rd_data_funct3 };

    assign req_ctrl_fifo_rd_data_alignment = req_ctrl_fifo_rd_data[8 +: `RV_XLEN_X-3];
    assign lsq_reg_addr_o                  = req_ctrl_fifo_rd_data[3 +: 5];
    assign req_ctrl_fifo_rd_data_funct3    = req_ctrl_fifo_rd_data[0 +: 3];

    merlin_fifo
        #(
            .C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
            .C_FIFO_WIDTH       (C_RSP_CTRL_FIFO_WIDTH),
            .C_FIFO_DEPTH_X     (C_FIFO_DEPTH_X)
        ) i_rsp_ctrl_merlin_fifo (

            .clk_i              (clk_i),
            .reset_i            (reset_i),

            .flush_i            (1'b0),
            .empty_o            (rsp_ctrl_fifo_empty),
            .full_o             (rsp_ctrl_fifo_full),

            .wr_i               (request & ~req_fifo_rd_data_wr),
            .din_i              (req_ctrl_fifo_wr_data),

            .rd_i               (lsq_reg_wr_o),
            .dout_o             (req_ctrl_fifo_rd_data)
        );





    assign rsp_data_fifo_wr_data = (drsprerr_i ? { `RV_XLEN {1'b0} } : drspdata_i);

    merlin_fifo
        #(
            .C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
            .C_FIFO_WIDTH       (`RV_XLEN),
            .C_FIFO_DEPTH_X     (C_FIFO_DEPTH_X)
        ) i_rsp_data_merlin_fifo (

            .clk_i              (clk_i),
            .reset_i            (reset_i),

            .flush_i            (1'b0),
            .empty_o            (rsp_data_fifo_empty),
            .full_o             (rsp_data_fifo_full),

            .wr_i               (drspready_o & ~drspwerr_i),
            .din_i              (rsp_data_fifo_wr_data),

            .rd_i               (lsq_reg_wr_o),
            .dout_o             (rsp_data_fifo_rd_data)
        );





    always @ (*) begin
        case (req_ctrl_fifo_rd_data_funct3)
            3'b000 : begin
                if (rsp_data_justified[7]) begin
                    lsq_reg_data_o = { { `RV_XLEN-8 {1'b1} }, rsp_data_justified[7:0] };
                end else begin
                    lsq_reg_data_o = { { `RV_XLEN-8 {1'b0} }, rsp_data_justified[7:0] };
                end
            end
            3'b001 : begin
                if (rsp_data_justified[15]) begin
                    lsq_reg_data_o = { { `RV_XLEN-16 {1'b1} }, rsp_data_justified[15:0] };
                end else begin
                    lsq_reg_data_o = { { `RV_XLEN-16 {1'b0} }, rsp_data_justified[15:0] };
                end
            end
            3'b010 : begin
                if (`RV_XLEN == 64) begin
                    if (rsp_data_justified[31]) begin
                        lsq_reg_data_o = { { `RV_XLEN-32 {1'b1} }, rsp_data_justified[31:0] };
                    end else begin
                        lsq_reg_data_o = { { `RV_XLEN-32 {1'b0} }, rsp_data_justified[31:0] };
                    end
                end else begin
                    lsq_reg_data_o = rsp_data_justified;
                end
            end
            3'b011 : begin
                lsq_reg_data_o = rsp_data_justified;
            end
            3'b100 : begin
                lsq_reg_data_o = { { `RV_XLEN-8 {1'b0} }, rsp_data_justified[7:0] };
            end
            3'b101 : begin
                lsq_reg_data_o = { { `RV_XLEN-16 {1'b0} }, rsp_data_justified[15:0] };
            end
            3'b110 : begin
                if (`RV_XLEN == 64) begin
                    lsq_reg_data_o = { { `RV_XLEN-32 {1'b0} }, rsp_data_justified[31:0] };
                end else begin
                    lsq_reg_data_o = rsp_data_justified;
                end
            end
            default : begin
                lsq_reg_data_o = rsp_data_justified;
            end
        endcase
    end

    always @ (*) begin
        case (req_ctrl_fifo_rd_data_alignment)
            2'b01   : rsp_data_justified = {  8'b0, rsp_data_fifo_rd_data[`RV_XLEN-1: 8] };
            2'b10   : rsp_data_justified = { 16'b0, rsp_data_fifo_rd_data[`RV_XLEN-1:16] };
            2'b11   : rsp_data_justified = { 24'b0, rsp_data_fifo_rd_data[`RV_XLEN-1:24] };
            default : rsp_data_justified = rsp_data_fifo_rd_data;
        endcase
    end





    initial begin
        `RV_ASSERT((`RV_XLEN == 32 || `RV_XLEN == 64), "Invalid value for RV_XLEN.  Must be 32 or 64.")
    end
endmodule