data/full_repos/permissive/202237519/verilog/digitalsystem6/sr.v
data/verilator_xmls/adb04a40-34de-468d-b88b-c43e95c207ee.xml
module sr_latch(s, r, Q, nQ);
  input s,r;
  output Q, nQ;
  assign Q = ~ (s & nQ);
  assign nQ = ~ (r & Q);
endmodule
module sr_latch(s, r, Q, nQ);

  input s,r;
  output Q, nQ;
  assign Q = ~ (s & nQ);
  assign nQ = ~ (r & Q);
endmodule