data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/hdl/mm_to_lite_v1_0_M_AXI_LITE.v
 line:115: before: "("
data/verilator_xmls/be1e009f-d062-4009-9bbe-3437360a4109.xml
module mm_to_lite_v1_0_M_AXI_LITE #
	(







		parameter  C_M_TARGET_SLAVE_BASE_ADDR	= 32'h40000000,


		parameter integer C_M_AXI_ADDR_WIDTH	= 32,


		parameter integer C_M_AXI_DATA_WIDTH	= 32
	)
	(


		input wire start_write,
		input wire [C_M_AXI_ADDR_WIDTH-1 : 0] s_axi_awaddr_dd,
		input wire [C_M_AXI_DATA_WIDTH-1 : 0] s_axi_wdata_dd,
		output reg end_write,

		input wire start_read,
		input wire [C_M_AXI_ADDR_WIDTH-1 : 0] s_axi_araddr_dd,
		output reg [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_rdata_dd,
		output reg end_read,





		input wire  M_AXI_ACLK,

		input wire  M_AXI_ARESETN,

		output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,



		output wire [2 : 0] M_AXI_AWPROT,


		output reg  M_AXI_AWVALID,


		input wire  M_AXI_AWREADY,

		output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,



		output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,

		output reg  M_AXI_WVALID,

		input wire  M_AXI_WREADY,


		input wire [1 : 0] M_AXI_BRESP,


		input wire  M_AXI_BVALID,

		output reg  M_AXI_BREADY,

		output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,



		output wire [2 : 0] M_AXI_ARPROT,


		output reg  M_AXI_ARVALID,


		input wire  M_AXI_ARREADY,

		input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,

		input wire [1 : 0] M_AXI_RRESP,

		input wire  M_AXI_RVALID,

		output reg  M_AXI_RREADY
	);
                                              




	function integer clogb2 (input integer bit_depth);              
	  begin                                                           
	  for(clogb2=0; bit_depth>0; clogb2=clogb2+1)                   
	    bit_depth = bit_depth >> 1;                                 
	  end                                                           
	endfunction 




	localparam integer STATE_BIT_WIDTH 		= 5;
	localparam [STATE_BIT_WIDTH - 1 : 0] IDLE 	= 5'b00001;
	localparam [STATE_BIT_WIDTH - 1 : 0] ALL 	= 5'b00010;
	localparam [STATE_BIT_WIDTH - 1 : 0] ADDR 	= 5'b00100;
	localparam [STATE_BIT_WIDTH - 1 : 0] DATA 	= 5'b01000;
	localparam [STATE_BIT_WIDTH - 1 : 0] RESP 	= 5'b10000;

	reg  [STATE_BIT_WIDTH - 1 : 0] 		state_read;
	reg  [STATE_BIT_WIDTH - 1 : 0] 		next_state_read;

	reg  [STATE_BIT_WIDTH - 1 : 0] 		state_write;
	reg  [STATE_BIT_WIDTH - 1 : 0] 		next_state_write;


	always @( posedge M_AXI_ACLK )
	begin
	  if ( M_AXI_ARESETN == 1'b0 )
		begin
		    state_read <= IDLE;
		    state_write <= IDLE;
		end
	  else
		begin
		    state_read <= next_state_read;
		    state_write <= next_state_write;
		end
	end






	assign M_AXI_WSTRB = {C_M_AXI_DATA_WIDTH/8{1'b1}};
	assign M_AXI_AWPROT = 3'b000;

	assign M_AXI_AWADDR = s_axi_awaddr_dd;
	assign M_AXI_WDATA = s_axi_wdata_dd;



	always @( * )
	begin
	    M_AXI_AWVALID = 1'b0;
	    M_AXI_WVALID = 1'b0;
	    M_AXI_BREADY = 1'b0;
	    end_write = 1'b0;

	    case(state_write)
		IDLE:
		    begin
			if(start_write == 1'b1)
			    begin
				next_state_write = ALL;
			    end
			else
			    begin
		    		next_state_write = IDLE;
			    end
		    end
		ALL:
		    begin
	    		M_AXI_AWVALID = 1'b1;
	    		M_AXI_WVALID = 1'b1;
			if(M_AXI_AWREADY == 1'b1 && M_AXI_WREADY == 1'b1)
			    begin
				next_state_write = RESP;
			    end
			else if(M_AXI_AWREADY == 1'b1)
			    begin
				next_state_write = DATA;
			    end
			else if(M_AXI_WREADY == 1'b1)
			    begin
				next_state_write = ADDR;
			    end
			else
			    begin
		    		next_state_write = ALL;
			    end
		    end
		ADDR:
		    begin
	    		M_AXI_AWVALID = 1'b1;
			if(M_AXI_AWREADY == 1'b1)
			    begin
				next_state_write = RESP;
			    end
			else
			    begin
		    		next_state_write = ADDR;
			    end
		    end
		DATA:
		    begin
	    		M_AXI_WVALID = 1'b1;
			if(M_AXI_WREADY == 1'b1)
			    begin
				next_state_write = RESP;
			    end
			else
			    begin
		    		next_state_write = DATA;
			    end
		    end
		RESP:
		    begin
	    		M_AXI_BREADY = 1'b1;
			if(M_AXI_BVALID == 1'b1)
			    begin
	    			end_write = 1'b1;
				next_state_write = IDLE;
			    end
			else
			    begin
		    		next_state_write = RESP;
			    end
		    end
		default:
		    next_state_write = IDLE;
	    endcase
	end






	assign M_AXI_ARPROT = 3'b000;
	assign M_AXI_ARADDR = s_axi_araddr_dd;


	always @( posedge M_AXI_ACLK )
	begin
	  if ( M_AXI_RVALID == 1'b1 && M_AXI_RREADY == 1'b1 )
		begin
		    m_axi_rdata_dd <= M_AXI_RDATA;
		end
	end



	always @( * )
	begin
	    M_AXI_ARVALID = 1'b0;
	    M_AXI_RREADY = 1'b0;
	    end_read = 1'b0;

	    case(state_read)
		IDLE:
		    begin
			if(start_read == 1'b1)
			    begin
				next_state_read = ALL;
			    end
			else
			    begin
		    		next_state_read = IDLE;
			    end
		    end
		ALL:
		    begin
	    		M_AXI_ARVALID = 1'b1;
	    		M_AXI_RREADY = 1'b1;
			if(M_AXI_ARREADY == 1'b1 && M_AXI_RVALID == 1'b1)
			    begin
	    			end_read = 1'b1;
				next_state_read = IDLE;
			    end
			else if(M_AXI_ARREADY == 1'b1)
			    begin
				next_state_read = DATA;
			    end
			else if(M_AXI_RVALID == 1'b1)
			    begin
				next_state_read = ADDR;
			    end
			else
			    begin
		    		next_state_read = ALL;
			    end
		    end
		ADDR:
		    begin
	    		M_AXI_ARVALID = 1'b1;
			if(M_AXI_ARREADY == 1'b1)
			    begin
	    			end_read = 1'b1;
				next_state_read = IDLE;
			    end
			else
			    begin
		    		next_state_read = ADDR;
			    end
		    end
		DATA:
		    begin
	    		M_AXI_RREADY = 1'b1;
			if(M_AXI_RVALID == 1'b1)
			    begin
	    			end_read = 1'b1;
				next_state_read = IDLE;
			    end
			else
			    begin
		    		next_state_read = DATA;
			    end
		    end
		default:
		    next_state_read = IDLE;
	    endcase
	end



	endmodule
module mm_to_lite_v1_0_M_AXI_LITE #
	(







		parameter  C_M_TARGET_SLAVE_BASE_ADDR	= 32'h40000000,


		parameter integer C_M_AXI_ADDR_WIDTH	= 32,


		parameter integer C_M_AXI_DATA_WIDTH	= 32
	)
	(


		input wire start_write,
		input wire [C_M_AXI_ADDR_WIDTH-1 : 0] s_axi_awaddr_dd,
		input wire [C_M_AXI_DATA_WIDTH-1 : 0] s_axi_wdata_dd,
		output reg end_write,

		input wire start_read,
		input wire [C_M_AXI_ADDR_WIDTH-1 : 0] s_axi_araddr_dd,
		output reg [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_rdata_dd,
		output reg end_read,





		input wire  M_AXI_ACLK,

		input wire  M_AXI_ARESETN,

		output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,



		output wire [2 : 0] M_AXI_AWPROT,


		output reg  M_AXI_AWVALID,


		input wire  M_AXI_AWREADY,

		output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,



		output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,

		output reg  M_AXI_WVALID,

		input wire  M_AXI_WREADY,


		input wire [1 : 0] M_AXI_BRESP,


		input wire  M_AXI_BVALID,

		output reg  M_AXI_BREADY,

		output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,



		output wire [2 : 0] M_AXI_ARPROT,


		output reg  M_AXI_ARVALID,


		input wire  M_AXI_ARREADY,

		input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,

		input wire [1 : 0] M_AXI_RRESP,

		input wire  M_AXI_RVALID,

		output reg  M_AXI_RREADY
	);

                                              




	function integer clogb2 (input integer bit_depth);              
	  begin                                                           
	  for(clogb2=0; bit_depth>0; clogb2=clogb2+1)                   
	    bit_depth = bit_depth >> 1;                                 
	  end                                                           
	endfunction 




	localparam integer STATE_BIT_WIDTH 		= 5;
	localparam [STATE_BIT_WIDTH - 1 : 0] IDLE 	= 5'b00001;
	localparam [STATE_BIT_WIDTH - 1 : 0] ALL 	= 5'b00010;
	localparam [STATE_BIT_WIDTH - 1 : 0] ADDR 	= 5'b00100;
	localparam [STATE_BIT_WIDTH - 1 : 0] DATA 	= 5'b01000;
	localparam [STATE_BIT_WIDTH - 1 : 0] RESP 	= 5'b10000;

	reg  [STATE_BIT_WIDTH - 1 : 0] 		state_read;
	reg  [STATE_BIT_WIDTH - 1 : 0] 		next_state_read;

	reg  [STATE_BIT_WIDTH - 1 : 0] 		state_write;
	reg  [STATE_BIT_WIDTH - 1 : 0] 		next_state_write;


	always @( posedge M_AXI_ACLK )
	begin
	  if ( M_AXI_ARESETN == 1'b0 )
		begin
		    state_read <= IDLE;
		    state_write <= IDLE;
		end
	  else
		begin
		    state_read <= next_state_read;
		    state_write <= next_state_write;
		end
	end






	assign M_AXI_WSTRB = {C_M_AXI_DATA_WIDTH/8{1'b1}};
	assign M_AXI_AWPROT = 3'b000;

	assign M_AXI_AWADDR = s_axi_awaddr_dd;
	assign M_AXI_WDATA = s_axi_wdata_dd;



	always @( * )
	begin
	    M_AXI_AWVALID = 1'b0;
	    M_AXI_WVALID = 1'b0;
	    M_AXI_BREADY = 1'b0;
	    end_write = 1'b0;

	    case(state_write)
		IDLE:
		    begin
			if(start_write == 1'b1)
			    begin
				next_state_write = ALL;
			    end
			else
			    begin
		    		next_state_write = IDLE;
			    end
		    end
		ALL:
		    begin
	    		M_AXI_AWVALID = 1'b1;
	    		M_AXI_WVALID = 1'b1;
			if(M_AXI_AWREADY == 1'b1 && M_AXI_WREADY == 1'b1)
			    begin
				next_state_write = RESP;
			    end
			else if(M_AXI_AWREADY == 1'b1)
			    begin
				next_state_write = DATA;
			    end
			else if(M_AXI_WREADY == 1'b1)
			    begin
				next_state_write = ADDR;
			    end
			else
			    begin
		    		next_state_write = ALL;
			    end
		    end
		ADDR:
		    begin
	    		M_AXI_AWVALID = 1'b1;
			if(M_AXI_AWREADY == 1'b1)
			    begin
				next_state_write = RESP;
			    end
			else
			    begin
		    		next_state_write = ADDR;
			    end
		    end
		DATA:
		    begin
	    		M_AXI_WVALID = 1'b1;
			if(M_AXI_WREADY == 1'b1)
			    begin
				next_state_write = RESP;
			    end
			else
			    begin
		    		next_state_write = DATA;
			    end
		    end
		RESP:
		    begin
	    		M_AXI_BREADY = 1'b1;
			if(M_AXI_BVALID == 1'b1)
			    begin
	    			end_write = 1'b1;
				next_state_write = IDLE;
			    end
			else
			    begin
		    		next_state_write = RESP;
			    end
		    end
		default:
		    next_state_write = IDLE;
	    endcase
	end






	assign M_AXI_ARPROT = 3'b000;
	assign M_AXI_ARADDR = s_axi_araddr_dd;


	always @( posedge M_AXI_ACLK )
	begin
	  if ( M_AXI_RVALID == 1'b1 && M_AXI_RREADY == 1'b1 )
		begin
		    m_axi_rdata_dd <= M_AXI_RDATA;
		end
	end



	always @( * )
	begin
	    M_AXI_ARVALID = 1'b0;
	    M_AXI_RREADY = 1'b0;
	    end_read = 1'b0;

	    case(state_read)
		IDLE:
		    begin
			if(start_read == 1'b1)
			    begin
				next_state_read = ALL;
			    end
			else
			    begin
		    		next_state_read = IDLE;
			    end
		    end
		ALL:
		    begin
	    		M_AXI_ARVALID = 1'b1;
	    		M_AXI_RREADY = 1'b1;
			if(M_AXI_ARREADY == 1'b1 && M_AXI_RVALID == 1'b1)
			    begin
	    			end_read = 1'b1;
				next_state_read = IDLE;
			    end
			else if(M_AXI_ARREADY == 1'b1)
			    begin
				next_state_read = DATA;
			    end
			else if(M_AXI_RVALID == 1'b1)
			    begin
				next_state_read = ADDR;
			    end
			else
			    begin
		    		next_state_read = ALL;
			    end
		    end
		ADDR:
		    begin
	    		M_AXI_ARVALID = 1'b1;
			if(M_AXI_ARREADY == 1'b1)
			    begin
	    			end_read = 1'b1;
				next_state_read = IDLE;
			    end
			else
			    begin
		    		next_state_read = ADDR;
			    end
		    end
		DATA:
		    begin
	    		M_AXI_RREADY = 1'b1;
			if(M_AXI_RVALID == 1'b1)
			    begin
	    			end_read = 1'b1;
				next_state_read = IDLE;
			    end
			else
			    begin
		    		next_state_read = DATA;
			    end
		    end
		default:
		    next_state_read = IDLE;
	    endcase
	end



	endmodule