data/full_repos/permissive/168753118/rtl/Core101_top.v
1: b"%Error: data/full_repos/permissive/168753118/rtl/Core101_top.v:42: Cannot find file containing module: 'Core101'\nCore101 core101 (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/168753118/rtl,data/full_repos/permissive/168753118/Core101\n             data/full_repos/permissive/168753118/rtl,data/full_repos/permissive/168753118/Core101.v\n             data/full_repos/permissive/168753118/rtl,data/full_repos/permissive/168753118/Core101.sv\n             Core101\n             Core101.v\n             Core101.sv\n             obj_dir/Core101\n             obj_dir/Core101.v\n             obj_dir/Core101.sv\n%Error: data/full_repos/permissive/168753118/rtl/Core101_top.v:63: Cannot find file containing module: 'INS_MEM'\nINS_MEM #(.XLEN(32)) ins_memory (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101_top.v:71: Cannot find file containing module: 'DATA_MEM'\nDATA_MEM #(.XLEN(32)) data_memory (\n^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module Core101_top #(
  parameter XLEN = 32
) (
  input clock_in,
  input reset_in
);



wire ins_mem_valid_wire;
wire ins_mem_ready_wire;
wire [31:0] ins_mem_addr_wire;
wire [31:0] ins_mem_data_wire;


wire data_mem_valid_wire;
wire data_mem_ready_wire;
wire data_mem_write_wire;
wire [31:0] data_mem_addr_wire;
wire [31:0] data_mem_data_inbound_wire;
wire [31:0] data_mem_data_outbound_wire;




Core101 core101 (

  .clock_in(clock_in),
  .reset_in(reset_in),


  .ins_mem_valid_out(ins_mem_valid_wire),
  .ins_mem_addr_out(ins_mem_addr_wire),
  .ins_mem_ready_in(ins_mem_ready_wire),
  .ins_mem_data_in(ins_mem_data_wire),


  .data_mem_valid_out(data_mem_valid_wire),
  .data_mem_write_out(data_mem_write_wire),
  .data_mem_addr_out(data_mem_addr_wire),
  .data_mem_data_out(data_mem_data_outbound_wire),
  .data_mem_ready_in(data_mem_ready_wire),
  .data_mem_data_in(data_mem_data_inbound_wire)
);


INS_MEM #(.XLEN(32)) ins_memory (
  .ins_mem_valid_in(ins_mem_valid_wire),
  .ins_mem_addr_in(ins_mem_addr_wire),
  .ins_mem_ready_out(ins_mem_ready_wire),
  .ins_mem_data_out(ins_mem_data_wire)
);


DATA_MEM #(.XLEN(32)) data_memory (
  .data_mem_valid_in(data_mem_valid_wire),
  .data_mem_write_in(data_mem_write_wire),
  .data_mem_addr_in(data_mem_addr_wire),
  .data_mem_data_in(data_mem_data_inbound_wire),
  .data_mem_data_out(data_mem_data_outbound_wire),
  .data_mem_ready_out(data_mem_ready_wire)
);

endmodule
module Core101_top #(
  parameter XLEN = 32
) (
  input clock_in,
  input reset_in
);




wire ins_mem_valid_wire;
wire ins_mem_ready_wire;
wire [31:0] ins_mem_addr_wire;
wire [31:0] ins_mem_data_wire;


wire data_mem_valid_wire;
wire data_mem_ready_wire;
wire data_mem_write_wire;
wire [31:0] data_mem_addr_wire;
wire [31:0] data_mem_data_inbound_wire;
wire [31:0] data_mem_data_outbound_wire;




Core101 core101 (

  .clock_in(clock_in),
  .reset_in(reset_in),


  .ins_mem_valid_out(ins_mem_valid_wire),
  .ins_mem_addr_out(ins_mem_addr_wire),
  .ins_mem_ready_in(ins_mem_ready_wire),
  .ins_mem_data_in(ins_mem_data_wire),


  .data_mem_valid_out(data_mem_valid_wire),
  .data_mem_write_out(data_mem_write_wire),
  .data_mem_addr_out(data_mem_addr_wire),
  .data_mem_data_out(data_mem_data_outbound_wire),
  .data_mem_ready_in(data_mem_ready_wire),
  .data_mem_data_in(data_mem_data_inbound_wire)
);


INS_MEM #(.XLEN(32)) ins_memory (
  .ins_mem_valid_in(ins_mem_valid_wire),
  .ins_mem_addr_in(ins_mem_addr_wire),
  .ins_mem_ready_out(ins_mem_ready_wire),
  .ins_mem_data_out(ins_mem_data_wire)
);


DATA_MEM #(.XLEN(32)) data_memory (
  .data_mem_valid_in(data_mem_valid_wire),
  .data_mem_write_in(data_mem_write_wire),
  .data_mem_addr_in(data_mem_addr_wire),
  .data_mem_data_in(data_mem_data_inbound_wire),
  .data_mem_data_out(data_mem_data_outbound_wire),
  .data_mem_ready_out(data_mem_ready_wire)
);

endmodule