data/full_repos/permissive/118480210/generalRGBmod/firmware/rtl/n64_igr.v
None: at end of input
1: b'%Error: data/full_repos/permissive/118480210/generalRGBmod/firmware/rtl/n64_igr.v:65: Cannot find include file: vh/igr_params.vh\n`include "vh/igr_params.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/118480210/generalRGBmod/firmware/rtl,data/full_repos/permissive/118480210/vh/igr_params.vh\n             data/full_repos/permissive/118480210/generalRGBmod/firmware/rtl,data/full_repos/permissive/118480210/vh/igr_params.vh.v\n             data/full_repos/permissive/118480210/generalRGBmod/firmware/rtl,data/full_repos/permissive/118480210/vh/igr_params.vh.sv\n             vh/igr_params.vh\n             vh/igr_params.vh.v\n             vh/igr_params.vh.sv\n             obj_dir/vh/igr_params.vh\n             obj_dir/vh/igr_params.vh.v\n             obj_dir/vh/igr_params.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module n64_igr (
  input      nCLK,
  input      nRST_IGR,
  output reg DRV_RST,

  input CTRL,

  input Default_nForceDeBlur,
  input Default_DeBlur,
  input Default_n15bit_mode,

  output reg nDeBlur,
  output reg nForceDeBlur,
  output reg n15bit_mode

`ifdef OPTION_INVLPF
  ,
  output reg InvLPF
`endif
);

`include "vh/igr_params.vh"

`ifdef OPTION_INVLPF
  initial InvLPF = 1'b0;
`endif









  reg nCLK2 = 1'b0;
  reg [2:0] div_clk_cnt = 3'b000;

  always @(negedge nCLK) begin
    if (div_clk_cnt == 3'b101) begin
      nCLK2 <= ~nCLK2;
      div_clk_cnt <= 3'b000;
    end else
      div_clk_cnt <= div_clk_cnt + 1'b1;
  end


reg [1:0] read_state  = 2'b0;

parameter ST_WAIT4N64 = 2'b00;
parameter ST_N64_RD   = 2'b01;
parameter ST_CTRL_RD  = 2'b10;

reg [3:0] sampling_point_n64  = 4'h9;
reg [3:0] sampling_point_ctrl = 4'h9;

reg        prev_ctrl    =  1'b1;
reg [11:0] wait_cnt     = 12'b0;

reg [15:0] data_stream      = 16'b0;
reg  [3:0] data_cnt         =  4'h0;

`ifdef OPTION_INVLPF
  reg [ 3:0] remember_data    =  4'h0;
  reg [15:0] prev_data_stream = 16'h0;
`endif

reg initiate_nrst = 1'b0;

reg nfirstboot = 1'b0;










always @(negedge nCLK2) begin
  case (read_state)
    ST_WAIT4N64:
      if (&wait_cnt) begin
        read_state    <= ST_N64_RD;
        data_stream   <= 16'h0000;
        data_cnt      <=  4'h0;
        initiate_nrst <=  1'b0;
      end
    ST_N64_RD: begin
      if (wait_cnt[7:0] == {4'h0,sampling_point_n64}) begin
        if (data_cnt[3])
          if (data_stream[13:6] == 8'b00000001 & CTRL) begin


            read_state  <= ST_CTRL_RD;
            data_stream <= 16'h0000;
            data_cnt    <=  4'h0;
          end else
            read_state  <= ST_WAIT4N64;
        else begin
          data_stream[13:7] <= data_stream[12:6];
          data_stream[6]    <= CTRL;
          data_cnt          <= data_cnt + 1'b1;
        end
      end
      if (&{prev_ctrl,~CTRL,|data_cnt})
        sampling_point_n64 <= wait_cnt[4:1];
    end
    ST_CTRL_RD: begin
      if (wait_cnt[7:0] == {4'h0,sampling_point_ctrl}) begin
        if (&data_cnt) begin
          if ({data_stream[14:0], CTRL} == igr_deblur_off) begin
            nForceDeBlur <= 1'b0;
            nDeBlur      <= 1'b1;
          end
          if ({data_stream[14:0], CTRL} == igr_deblur_on) begin
            nForceDeBlur <= 1'b0;
            nDeBlur      <= 1'b0;
          end
          if ({data_stream[14:0], CTRL} == igr_15bitmode_off) begin
`ifdef DEBUG
            nForceDeBlur <= 1'b1;
`endif
            n15bit_mode  <= 1'b1;
          end
          if ({data_stream[14:0], CTRL} == igr_15bitmode_on) begin
`ifdef DEBUG
            nForceDeBlur <= 1'b1;
`endif
            n15bit_mode  <= 1'b0;
          end
`ifdef OPTION_INVLPF
          if ({data_stream[14:0], CTRL} == igr_toggle_LPF) begin
            if (prev_data_stream != {data_stream[14:0], CTRL})
              InvLPF <= ~InvLPF;
            remember_data <= 4'hf;
          end
`endif
          if ({data_stream[14:0], CTRL} == igr_reset) begin
            initiate_nrst <= 1'b1;
          end
          read_state  <= ST_WAIT4N64;
`ifdef OPTION_INVLPF
          if (~|remember_data)
            prev_data_stream <= {data_stream[14:0], CTRL};
          else
            remember_data <= remember_data - 1'b1;
`endif
        end else begin
          data_stream[15:1] <= data_stream[14:0];
          data_stream[0]    <= CTRL;
          data_cnt          <= data_cnt + 1'b1;
        end
      end
      if (&{prev_ctrl,~CTRL,|data_cnt})
        sampling_point_ctrl <= wait_cnt[4:1];
    end
  endcase


  if (prev_ctrl & ~CTRL)
    wait_cnt <= 12'h000;
  else if (~&wait_cnt)
    wait_cnt <= wait_cnt + 1'b1;

  prev_ctrl <= CTRL;

  if (~nRST_IGR) begin
`ifdef OPTION_INVLPF
    InvLPF      <= 1'b0;
`endif

    nForceDeBlur <= Default_nForceDeBlur;

    read_state    <= ST_WAIT4N64;
    wait_cnt      <= 12'h000;
    prev_ctrl     <=  1'b1;
    initiate_nrst <=  1'b0;
  end

  if (~nfirstboot) begin
    nfirstboot   <=  1'b1;
    nForceDeBlur <=  Default_nForceDeBlur;
    nDeBlur      <= ~Default_DeBlur;
    n15bit_mode  <=  Default_n15bit_mode;
  end
end


reg [17:0] rst_cnt = 18'b0;

always @(negedge nCLK2) begin
  if (initiate_nrst == 1'b1) begin
    DRV_RST <= 1'b1;
    rst_cnt <= 18'h3ffff;
  end else if (|rst_cnt)
    rst_cnt <= rst_cnt - 1'b1;
  else
    DRV_RST <= 1'b0;
end

endmodule
module n64_igr (
  input      nCLK,
  input      nRST_IGR,
  output reg DRV_RST,

  input CTRL,

  input Default_nForceDeBlur,
  input Default_DeBlur,
  input Default_n15bit_mode,

  output reg nDeBlur,
  output reg nForceDeBlur,
  output reg n15bit_mode

`ifdef OPTION_INVLPF
  ,
  output reg InvLPF
`endif
);


`include "vh/igr_params.vh"

`ifdef OPTION_INVLPF
  initial InvLPF = 1'b0;
`endif









  reg nCLK2 = 1'b0;
  reg [2:0] div_clk_cnt = 3'b000;

  always @(negedge nCLK) begin
    if (div_clk_cnt == 3'b101) begin
      nCLK2 <= ~nCLK2;
      div_clk_cnt <= 3'b000;
    end else
      div_clk_cnt <= div_clk_cnt + 1'b1;
  end


reg [1:0] read_state  = 2'b0;

parameter ST_WAIT4N64 = 2'b00;
parameter ST_N64_RD   = 2'b01;
parameter ST_CTRL_RD  = 2'b10;

reg [3:0] sampling_point_n64  = 4'h9;
reg [3:0] sampling_point_ctrl = 4'h9;

reg        prev_ctrl    =  1'b1;
reg [11:0] wait_cnt     = 12'b0;

reg [15:0] data_stream      = 16'b0;
reg  [3:0] data_cnt         =  4'h0;

`ifdef OPTION_INVLPF
  reg [ 3:0] remember_data    =  4'h0;
  reg [15:0] prev_data_stream = 16'h0;
`endif

reg initiate_nrst = 1'b0;

reg nfirstboot = 1'b0;










always @(negedge nCLK2) begin
  case (read_state)
    ST_WAIT4N64:
      if (&wait_cnt) begin
        read_state    <= ST_N64_RD;
        data_stream   <= 16'h0000;
        data_cnt      <=  4'h0;
        initiate_nrst <=  1'b0;
      end
    ST_N64_RD: begin
      if (wait_cnt[7:0] == {4'h0,sampling_point_n64}) begin
        if (data_cnt[3])
          if (data_stream[13:6] == 8'b00000001 & CTRL) begin


            read_state  <= ST_CTRL_RD;
            data_stream <= 16'h0000;
            data_cnt    <=  4'h0;
          end else
            read_state  <= ST_WAIT4N64;
        else begin
          data_stream[13:7] <= data_stream[12:6];
          data_stream[6]    <= CTRL;
          data_cnt          <= data_cnt + 1'b1;
        end
      end
      if (&{prev_ctrl,~CTRL,|data_cnt})
        sampling_point_n64 <= wait_cnt[4:1];
    end
    ST_CTRL_RD: begin
      if (wait_cnt[7:0] == {4'h0,sampling_point_ctrl}) begin
        if (&data_cnt) begin
          if ({data_stream[14:0], CTRL} == igr_deblur_off) begin
            nForceDeBlur <= 1'b0;
            nDeBlur      <= 1'b1;
          end
          if ({data_stream[14:0], CTRL} == igr_deblur_on) begin
            nForceDeBlur <= 1'b0;
            nDeBlur      <= 1'b0;
          end
          if ({data_stream[14:0], CTRL} == igr_15bitmode_off) begin
`ifdef DEBUG
            nForceDeBlur <= 1'b1;
`endif
            n15bit_mode  <= 1'b1;
          end
          if ({data_stream[14:0], CTRL} == igr_15bitmode_on) begin
`ifdef DEBUG
            nForceDeBlur <= 1'b1;
`endif
            n15bit_mode  <= 1'b0;
          end
`ifdef OPTION_INVLPF
          if ({data_stream[14:0], CTRL} == igr_toggle_LPF) begin
            if (prev_data_stream != {data_stream[14:0], CTRL})
              InvLPF <= ~InvLPF;
            remember_data <= 4'hf;
          end
`endif
          if ({data_stream[14:0], CTRL} == igr_reset) begin
            initiate_nrst <= 1'b1;
          end
          read_state  <= ST_WAIT4N64;
`ifdef OPTION_INVLPF
          if (~|remember_data)
            prev_data_stream <= {data_stream[14:0], CTRL};
          else
            remember_data <= remember_data - 1'b1;
`endif
        end else begin
          data_stream[15:1] <= data_stream[14:0];
          data_stream[0]    <= CTRL;
          data_cnt          <= data_cnt + 1'b1;
        end
      end
      if (&{prev_ctrl,~CTRL,|data_cnt})
        sampling_point_ctrl <= wait_cnt[4:1];
    end
  endcase


  if (prev_ctrl & ~CTRL)
    wait_cnt <= 12'h000;
  else if (~&wait_cnt)
    wait_cnt <= wait_cnt + 1'b1;

  prev_ctrl <= CTRL;

  if (~nRST_IGR) begin
`ifdef OPTION_INVLPF
    InvLPF      <= 1'b0;
`endif

    nForceDeBlur <= Default_nForceDeBlur;

    read_state    <= ST_WAIT4N64;
    wait_cnt      <= 12'h000;
    prev_ctrl     <=  1'b1;
    initiate_nrst <=  1'b0;
  end

  if (~nfirstboot) begin
    nfirstboot   <=  1'b1;
    nForceDeBlur <=  Default_nForceDeBlur;
    nDeBlur      <= ~Default_DeBlur;
    n15bit_mode  <=  Default_n15bit_mode;
  end
end


reg [17:0] rst_cnt = 18'b0;

always @(negedge nCLK2) begin
  if (initiate_nrst == 1'b1) begin
    DRV_RST <= 1'b1;
    rst_cnt <= 18'h3ffff;
  end else if (|rst_cnt)
    rst_cnt <= rst_cnt - 1'b1;
  else
    DRV_RST <= 1'b0;
end

endmodule