data/full_repos/permissive/156721532/UART/FIR_pipeline.v
1: b'%Error: data/full_repos/permissive/156721532/UART/FIR_pipeline.v:5: Cannot find include file: macros.v\n`include "macros.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156721532/UART,data/full_repos/permissive/156721532/macros.v\n             data/full_repos/permissive/156721532/UART,data/full_repos/permissive/156721532/macros.v.v\n             data/full_repos/permissive/156721532/UART,data/full_repos/permissive/156721532/macros.v.sv\n             macros.v\n             macros.v.v\n             macros.v.sv\n             obj_dir/macros.v\n             obj_dir/macros.v.v\n             obj_dir/macros.v.sv\n%Error: data/full_repos/permissive/156721532/UART/FIR_pipeline.v:36: Define or directive not defined: \'`LOG2_CEIL\'\n  parameter OUT_WIDTH = 2 * WIDTH + `LOG2_CEIL(LENGTH) - 1;\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/156721532/UART/FIR_pipeline.v:52: Define or directive not defined: \'`LOG2_CEIL\'\n  localparam  ADDRESS_RANGE = `LOG2_CEIL(LENGTH);\n                              ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module FIR_sync(
            clk,
            rst,
            FIR_input,
            input_valid,
            FIR_output,
            output_valid
          );
  parameter LENGTH = 64;
  parameter WIDTH = 16;
  parameter OUT_WIDTH = 2 * WIDTH + `LOG2_CEIL(LENGTH) - 1;

  input clk, rst, input_valid;
  input signed [WIDTH-1:0] FIR_input;
  output reg output_valid;
  output reg signed [OUT_WIDTH - 1:0] FIR_output;

  wire [WIDTH-1:0] coeff;


  reg signed [WIDTH-1:0] shiftreg[0:LENGTH-1];

  localparam WAIT = 0, START = 1, LOAD_COEFF = 2, CALC_MUL = 3, CALC_SUM = 4, SAVE = 5, DONE = 6;
  reg [2:0] ps, ns;
  reg signed [OUT_WIDTH - 1:0] ACC;
  reg signed [2*WIDTH - 1:0] PREG;
  localparam  ADDRESS_RANGE = `LOG2_CEIL(LENGTH);
  reg [ADDRESS_RANGE - 1:0] address;
  reg ldACC, addrCount, addrRst, ACCRst, shen, ldPREG, ldOut;
  wire mul_finished;
  wire signed [OUT_WIDTH - 1:0] sum;
  wire signed [2*WIDTH - 1:0] product;




  ROM coROM (.clock(clk), .address(address), .q(coeff));

  multiplier #(WIDTH) MULT(
                  .a(shiftreg[address]),
                  .b(coeff),
                  .p(product)
                  );

  assign sum = ACC + PREG;
  assign mul_finished = (address == LENGTH - 1) ? 1'b1:1'b0;

  integer i;
  always @(posedge clk) begin
    if(rst)begin
      ps <= 0;
      for(i = 0; i < LENGTH; i = i + 1)
        shiftreg[i] <= 0;
    end
    else
      ps <= ns;
    if(shen)begin
      for(i = 0; i < LENGTH - 1; i = i + 1)
        shiftreg[i + 1] <= shiftreg[i];
      shiftreg[0] <= FIR_input;
    end
    if(addrRst)
      address <= 0;
    else if(addrCount)
      address <= address + 1;
    if(ACCRst)begin
      ACC <= 0;
      PREG <= 0;
    end
    else if(ldACC)
      ACC <= sum;
    if (ldPREG)
      PREG <= product;
    if(ldOut)
      FIR_output <= ACC;
  end

  always @(ps, input_valid, mul_finished) begin
    ns = WAIT;
    case(ps)
      WAIT: if(input_valid) ns = START; else ns = WAIT;
      START: if(input_valid) ns = START; else ns = LOAD_COEFF;
      LOAD_COEFF: ns = CALC_MUL;
      CALC_MUL: ns = CALC_SUM;
      CALC_SUM: if(mul_finished) ns = SAVE; else ns = LOAD_COEFF;
      SAVE: ns = DONE;
      DONE: if(input_valid) ns = START; else ns = WAIT;
      default: ns = WAIT;
    endcase
  end

  always@(ps)begin
    addrCount = 0;
    ldACC = 0;
    addrRst = 0;
    ACCRst = 0;
    output_valid = 0;
    shen = 0;
    ldPREG = 0;
    ldOut = 0;
    case(ps)
      START: begin addrRst = 1'b1; ACCRst = 1'b1; shen = 1'b1; end
      CALC_MUL: ldPREG = 1'b1;
      CALC_SUM: begin addrCount = 1'b1; ldACC = 1'b1; end
      SAVE: ldOut = 1'b1;
      DONE: output_valid = 1'b1;
      default: output_valid = 1'b0;
    endcase
  end

endmodule
module FIR_sync(
            clk,
            rst,
            FIR_input,
            input_valid,
            FIR_output,
            output_valid
          );

  parameter LENGTH = 64;
  parameter WIDTH = 16;
  parameter OUT_WIDTH = 2 * WIDTH + `LOG2_CEIL(LENGTH) - 1;

  input clk, rst, input_valid;
  input signed [WIDTH-1:0] FIR_input;
  output reg output_valid;
  output reg signed [OUT_WIDTH - 1:0] FIR_output;

  wire [WIDTH-1:0] coeff;


  reg signed [WIDTH-1:0] shiftreg[0:LENGTH-1];

  localparam WAIT = 0, START = 1, LOAD_COEFF = 2, CALC_MUL = 3, CALC_SUM = 4, SAVE = 5, DONE = 6;
  reg [2:0] ps, ns;
  reg signed [OUT_WIDTH - 1:0] ACC;
  reg signed [2*WIDTH - 1:0] PREG;
  localparam  ADDRESS_RANGE = `LOG2_CEIL(LENGTH);
  reg [ADDRESS_RANGE - 1:0] address;
  reg ldACC, addrCount, addrRst, ACCRst, shen, ldPREG, ldOut;
  wire mul_finished;
  wire signed [OUT_WIDTH - 1:0] sum;
  wire signed [2*WIDTH - 1:0] product;




  ROM coROM (.clock(clk), .address(address), .q(coeff));

  multiplier #(WIDTH) MULT(
                  .a(shiftreg[address]),
                  .b(coeff),
                  .p(product)
                  );

  assign sum = ACC + PREG;
  assign mul_finished = (address == LENGTH - 1) ? 1'b1:1'b0;

  integer i;
  always @(posedge clk) begin
    if(rst)begin
      ps <= 0;
      for(i = 0; i < LENGTH; i = i + 1)
        shiftreg[i] <= 0;
    end
    else
      ps <= ns;
    if(shen)begin
      for(i = 0; i < LENGTH - 1; i = i + 1)
        shiftreg[i + 1] <= shiftreg[i];
      shiftreg[0] <= FIR_input;
    end
    if(addrRst)
      address <= 0;
    else if(addrCount)
      address <= address + 1;
    if(ACCRst)begin
      ACC <= 0;
      PREG <= 0;
    end
    else if(ldACC)
      ACC <= sum;
    if (ldPREG)
      PREG <= product;
    if(ldOut)
      FIR_output <= ACC;
  end

  always @(ps, input_valid, mul_finished) begin
    ns = WAIT;
    case(ps)
      WAIT: if(input_valid) ns = START; else ns = WAIT;
      START: if(input_valid) ns = START; else ns = LOAD_COEFF;
      LOAD_COEFF: ns = CALC_MUL;
      CALC_MUL: ns = CALC_SUM;
      CALC_SUM: if(mul_finished) ns = SAVE; else ns = LOAD_COEFF;
      SAVE: ns = DONE;
      DONE: if(input_valid) ns = START; else ns = WAIT;
      default: ns = WAIT;
    endcase
  end

  always@(ps)begin
    addrCount = 0;
    ldACC = 0;
    addrRst = 0;
    ACCRst = 0;
    output_valid = 0;
    shen = 0;
    ldPREG = 0;
    ldOut = 0;
    case(ps)
      START: begin addrRst = 1'b1; ACCRst = 1'b1; shen = 1'b1; end
      CALC_MUL: ldPREG = 1'b1;
      CALC_SUM: begin addrCount = 1'b1; ldACC = 1'b1; end
      SAVE: ldOut = 1'b1;
      DONE: output_valid = 1'b1;
      default: output_valid = 1'b0;
    endcase
  end

endmodule