data/full_repos/permissive/200314387/verilog/74573/hct74573.v
 line:34: before: "="
data/verilator_xmls/f947447c-fb39-4736-890e-96fbbd3ded27.xml
module hct74573 (
    input LE,
    input _OE,
	input [7:0] D,
    output [7:0] Q
);
    parameter LOG=0;

    reg [7:0] data;
    
    specify
    (D => Q) = (17);
    (LE *> Q) = (15);
    (_OE *> Q) = (18);
    endspecify
    
    always @(D or LE)
        if (LE)
        begin 
            data = D;
        end
    
    assign Q = _OE ? 8'bz : data;

    if (LOG) always @* 
        $display("%09t ", $time, 
                " LE=%1b", LE,
                " _OE=%1b", _OE,
                " D=%8b", D,
                " Q=%8b", D,
                "%m");
        
    
endmodule
module hct74573 (
    input LE,
    input _OE,
	input [7:0] D,
    output [7:0] Q
);

    parameter LOG=0;

    reg [7:0] data;
    
    specify
    (D => Q) = (17);
    (LE *> Q) = (15);
    (_OE *> Q) = (18);
    endspecify
    
    always @(D or LE)
        if (LE)
        begin 
            data = D;
        end
    
    assign Q = _OE ? 8'bz : data;

    if (LOG) always @* 
        $display("%09t ", $time, 
                " LE=%1b", LE,
                " _OE=%1b", _OE,
                " D=%8b", D,
                " Q=%8b", D,
                "%m");
        
    
endmodule