data/full_repos/permissive/16142629/rtl/zet_decode.v
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1: b'%Error: data/full_repos/permissive/16142629/rtl/zet_decode.v:21: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/16142629/rtl,data/full_repos/permissive/16142629/defines.v\n             data/full_repos/permissive/16142629/rtl,data/full_repos/permissive/16142629/defines.v.v\n             data/full_repos/permissive/16142629/rtl,data/full_repos/permissive/16142629/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/16142629/rtl/zet_decode.v:58: Define or directive not defined: \'`MICRO_ADDR_WIDTH\'\n  output [`MICRO_ADDR_WIDTH-1:0] seq_addr_o,\n          ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module zet_decode (
  input clk,
  input rst_i,
  input flush_i,
  input [7:0] instruction_i,
  input instruction_valid_i,
  output reg next_instruction_o,


  output reg [15:0] instruction_cs_o,
  output reg [15:0] instruction_ip_o,


  output reg [3:0] inst_pr_o,

  output reg [3:0] adrs_pr_o,

  output reg [3:0] oper_pr_o,

  output reg [3:0] sovr_pr_o,
  
  output reg [7:0] opcode_o,
  
  output need_modrm_o,
  output reg [7:0] modrm_o,
  
  output need_off_o,
  output off_size_o,
  output reg [15:0] offset_o,
  
  output need_imm_o,
  output imm_size_o,
  output reg [15:0] immediate_o,


  output [`MICRO_ADDR_WIDTH-1:0] seq_addr_o,
  output [3:0] src_o,
  output [3:0] dst_o,
  output [3:0] base_o,
  output [3:0] index_o,
  output [1:0] seg_o,
  
  output reg decoded_valid_o,
  input next_decoded_i

);



localparam [3:0]
  idle_st       = 4'd0,
  prefix_st     = 4'd1,
  opcode_st     = 4'd2,
  modrm_st      = 4'd3,
  offset_st     = 4'd4,
  offset2_st    = 4'd5,
  immediate_st  = 4'd6,
  immediate2_st = 4'd7,
  execute_st    = 4'd8;

reg [3:0] state;
reg [3:0] next_state;

reg decoder_flush;
wire dflush;


reg [3:0] prefix_grp;
reg [2:0] prefix;
wire prefix_decoded;


wire rep;
wire [2:0] sop;


reg latch_prefix;
reg latch_opcode;
reg latch_modrm;

reg latch_offset_1;
reg latch_offset_2;

reg latch_immediate_1;
reg latch_immediate_2;



zet_opcode_deco opcode_deco (opcode_o, modrm_o, rep, sop, seq_addr_o, need_modrm_o,
                             need_off_o, need_imm_o, off_size_o, imm_size_o, src_o, dst_o,
                             base_o, index_o, seg_o);




assign dflush = decoder_flush | flush_i;


assign prefix_decoded = |prefix_grp;


assign rep = inst_pr_o[2] | inst_pr_o[1];
assign sop = { sovr_pr_o[3], sovr_pr_o[1:0] };




always @(*)
  case (instruction_i)

    8'hf0: begin prefix_grp <= 4'b1000; prefix <= 3'b001; end
    8'hf2: begin prefix_grp <= 4'b1000; prefix <= 3'b010; end
    8'hf3: begin prefix_grp <= 4'b1000; prefix <= 3'b100; end

    8'h67: begin prefix_grp <= 4'b0100; prefix <= 3'b001; end

    8'h66: begin prefix_grp <= 4'b0010; prefix <= 3'b001; end

    8'h26: begin prefix_grp <= 4'b0001; prefix <= 3'b000; end
    8'h2e: begin prefix_grp <= 4'b0001; prefix <= 3'b001; end
    8'h36: begin prefix_grp <= 4'b0001; prefix <= 3'b010; end
    8'h3e: begin prefix_grp <= 4'b0001; prefix <= 3'b011; end
    8'h64: begin prefix_grp <= 4'b0001; prefix <= 3'b100; end
    8'h65: begin prefix_grp <= 4'b0001; prefix <= 3'b101; end

    default: begin prefix_grp <= 4'b0000; prefix <= 3'b000; end
  endcase


always @(posedge clk)
  if (rst_i) begin
    inst_pr_o <= 4'b0000;
    adrs_pr_o <= 4'b0000;
    oper_pr_o <= 4'b0000;
    sovr_pr_o <= 4'b0000;
  end
  else
  if (dflush) begin
    inst_pr_o <= 4'b0000;
    adrs_pr_o <= 4'b0000;
    oper_pr_o <= 4'b0000;
    sovr_pr_o <= 4'b0000;
  end
  else
  begin
    if (latch_prefix) begin
      inst_pr_o <= prefix_grp[3] ? {prefix_decoded, prefix} : inst_pr_o;
      adrs_pr_o <= prefix_grp[2] ? {prefix_decoded, prefix} : adrs_pr_o;
      oper_pr_o <= prefix_grp[1] ? {prefix_decoded, prefix} : oper_pr_o;
      sovr_pr_o <= prefix_grp[0] ? {prefix_decoded, prefix} : sovr_pr_o;
    end
  end


always @(posedge clk)
  if (rst_i)

    opcode_o <= 8'h90;
  else
  if (dflush)

    opcode_o <= 8'h90;
  else
  if (latch_opcode)
    opcode_o <= instruction_i;


always @(posedge clk)
  if (rst_i)
    modrm_o <= 8'b0;
  else
  if (dflush)
    modrm_o <= 8'b0;
  else
  if (latch_modrm)
    modrm_o <= instruction_i;


always @(posedge clk)
  if (rst_i)
    offset_o <= 16'b0;
  else
  if (dflush)
    offset_o <= 16'b0;
  else
  if (latch_offset_1)
    offset_o[7:0] <= instruction_i;
  else
  if (latch_offset_2)
    offset_o[15:8] <= instruction_i;


always @(posedge clk)
  if (rst_i)
    immediate_o <= 16'b0;
  else
  if (dflush)
    immediate_o <= 16'b0;
  else
  if (latch_immediate_1)
    immediate_o[7:0] <= instruction_i;
  else
  if (latch_immediate_2)
    immediate_o[15:8] <= instruction_i;


always @(posedge clk)
  if (rst_i) state <= idle_st;
  else
  if (dflush) state <= idle_st;
  else
  state <= next_state;


always @(*) begin
    next_state = state;

    next_instruction_o = 1'b0;

    
    decoder_flush = 1'b0;

    latch_prefix = 1'b0;
    latch_opcode = 1'b0;
    latch_modrm = 1'b0;

    latch_offset_1 = 1'b0;
    latch_offset_2 = 1'b0;

    latch_immediate_1 = 1'b0;
    latch_immediate_2 = 1'b0;

    decoded_valid_o = 1'b0;

    case (state)
      idle_st: begin


          if (instruction_valid_i) begin
              next_state = prefix_st;
          end
      end
      prefix_st: begin
        if (instruction_valid_i) begin
          if (prefix_decoded) begin
            latch_prefix = 1'b1;
            next_state = prefix_st;
          end
          else begin
            latch_opcode = 1'b1;
            next_state = opcode_st;
          end
          next_instruction_o = 1'b1;
        end
      end
      opcode_st: begin
        if (need_modrm_o) begin
          if (instruction_valid_i) begin
            latch_modrm = 1'b1;
            next_instruction_o = 1'b1;
            next_state = modrm_st;
          end
        end
        else 
        if (need_off_o) next_state = offset_st;
        else
        if (need_imm_o) next_state = immediate_st;
        else
        next_state = execute_st;
      end
      modrm_st: begin
        if (need_off_o) next_state = offset_st;
        else
        if (need_imm_o) next_state = immediate_st;
        else
        next_state = execute_st;
      end
      offset_st: begin
        if (off_size_o) begin
          if (instruction_valid_i) begin
            latch_offset_1 = 1'b1;
            next_instruction_o = 1'b1;
            next_state = offset2_st;
          end
        end
        else
        if (instruction_valid_i) begin
          latch_offset_1 = 1'b1;
          next_instruction_o = 1'b1;
          if (need_imm_o) next_state = immediate_st;
          else next_state = execute_st;
        end
      end
      offset2_st: begin
        if (instruction_valid_i) begin
          latch_offset_2 = 1'b1;
          next_instruction_o = 1'b1;
          if (need_imm_o) next_state = immediate_st;
          else next_state = execute_st;
        end
      end
      immediate_st: begin
        if (imm_size_o) begin
          if (instruction_valid_i) begin
            latch_immediate_1 = 1'b1;
            next_instruction_o = 1'b1;
            next_state = immediate2_st;
          end
        end
        else
        if (instruction_valid_i) begin
          latch_immediate_1 = 1'b1;
          next_instruction_o = 1'b1;
          next_state = execute_st;
        end
      end
      immediate2_st: begin
        if (instruction_valid_i) begin
          latch_immediate_2 = 1'b1;
          next_instruction_o = 1'b1;
          next_state = execute_st;
        end
      end
      execute_st: begin
        decoded_valid_o = 1'b1;
        if (next_decoded_i) begin

          decoder_flush = 1'b1;
          next_state = idle_st;
        end
      end
    endcase
end

endmodule
module zet_decode (
  input clk,
  input rst_i,
  input flush_i,
  input [7:0] instruction_i,
  input instruction_valid_i,
  output reg next_instruction_o,


  output reg [15:0] instruction_cs_o,
  output reg [15:0] instruction_ip_o,


  output reg [3:0] inst_pr_o,

  output reg [3:0] adrs_pr_o,

  output reg [3:0] oper_pr_o,

  output reg [3:0] sovr_pr_o,
  
  output reg [7:0] opcode_o,
  
  output need_modrm_o,
  output reg [7:0] modrm_o,
  
  output need_off_o,
  output off_size_o,
  output reg [15:0] offset_o,
  
  output need_imm_o,
  output imm_size_o,
  output reg [15:0] immediate_o,


  output [`MICRO_ADDR_WIDTH-1:0] seq_addr_o,
  output [3:0] src_o,
  output [3:0] dst_o,
  output [3:0] base_o,
  output [3:0] index_o,
  output [1:0] seg_o,
  
  output reg decoded_valid_o,
  input next_decoded_i

);




localparam [3:0]
  idle_st       = 4'd0,
  prefix_st     = 4'd1,
  opcode_st     = 4'd2,
  modrm_st      = 4'd3,
  offset_st     = 4'd4,
  offset2_st    = 4'd5,
  immediate_st  = 4'd6,
  immediate2_st = 4'd7,
  execute_st    = 4'd8;

reg [3:0] state;
reg [3:0] next_state;

reg decoder_flush;
wire dflush;


reg [3:0] prefix_grp;
reg [2:0] prefix;
wire prefix_decoded;


wire rep;
wire [2:0] sop;


reg latch_prefix;
reg latch_opcode;
reg latch_modrm;

reg latch_offset_1;
reg latch_offset_2;

reg latch_immediate_1;
reg latch_immediate_2;



zet_opcode_deco opcode_deco (opcode_o, modrm_o, rep, sop, seq_addr_o, need_modrm_o,
                             need_off_o, need_imm_o, off_size_o, imm_size_o, src_o, dst_o,
                             base_o, index_o, seg_o);




assign dflush = decoder_flush | flush_i;


assign prefix_decoded = |prefix_grp;


assign rep = inst_pr_o[2] | inst_pr_o[1];
assign sop = { sovr_pr_o[3], sovr_pr_o[1:0] };




always @(*)
  case (instruction_i)

    8'hf0: begin prefix_grp <= 4'b1000; prefix <= 3'b001; end
    8'hf2: begin prefix_grp <= 4'b1000; prefix <= 3'b010; end
    8'hf3: begin prefix_grp <= 4'b1000; prefix <= 3'b100; end

    8'h67: begin prefix_grp <= 4'b0100; prefix <= 3'b001; end

    8'h66: begin prefix_grp <= 4'b0010; prefix <= 3'b001; end

    8'h26: begin prefix_grp <= 4'b0001; prefix <= 3'b000; end
    8'h2e: begin prefix_grp <= 4'b0001; prefix <= 3'b001; end
    8'h36: begin prefix_grp <= 4'b0001; prefix <= 3'b010; end
    8'h3e: begin prefix_grp <= 4'b0001; prefix <= 3'b011; end
    8'h64: begin prefix_grp <= 4'b0001; prefix <= 3'b100; end
    8'h65: begin prefix_grp <= 4'b0001; prefix <= 3'b101; end

    default: begin prefix_grp <= 4'b0000; prefix <= 3'b000; end
  endcase


always @(posedge clk)
  if (rst_i) begin
    inst_pr_o <= 4'b0000;
    adrs_pr_o <= 4'b0000;
    oper_pr_o <= 4'b0000;
    sovr_pr_o <= 4'b0000;
  end
  else
  if (dflush) begin
    inst_pr_o <= 4'b0000;
    adrs_pr_o <= 4'b0000;
    oper_pr_o <= 4'b0000;
    sovr_pr_o <= 4'b0000;
  end
  else
  begin
    if (latch_prefix) begin
      inst_pr_o <= prefix_grp[3] ? {prefix_decoded, prefix} : inst_pr_o;
      adrs_pr_o <= prefix_grp[2] ? {prefix_decoded, prefix} : adrs_pr_o;
      oper_pr_o <= prefix_grp[1] ? {prefix_decoded, prefix} : oper_pr_o;
      sovr_pr_o <= prefix_grp[0] ? {prefix_decoded, prefix} : sovr_pr_o;
    end
  end


always @(posedge clk)
  if (rst_i)

    opcode_o <= 8'h90;
  else
  if (dflush)

    opcode_o <= 8'h90;
  else
  if (latch_opcode)
    opcode_o <= instruction_i;


always @(posedge clk)
  if (rst_i)
    modrm_o <= 8'b0;
  else
  if (dflush)
    modrm_o <= 8'b0;
  else
  if (latch_modrm)
    modrm_o <= instruction_i;


always @(posedge clk)
  if (rst_i)
    offset_o <= 16'b0;
  else
  if (dflush)
    offset_o <= 16'b0;
  else
  if (latch_offset_1)
    offset_o[7:0] <= instruction_i;
  else
  if (latch_offset_2)
    offset_o[15:8] <= instruction_i;


always @(posedge clk)
  if (rst_i)
    immediate_o <= 16'b0;
  else
  if (dflush)
    immediate_o <= 16'b0;
  else
  if (latch_immediate_1)
    immediate_o[7:0] <= instruction_i;
  else
  if (latch_immediate_2)
    immediate_o[15:8] <= instruction_i;


always @(posedge clk)
  if (rst_i) state <= idle_st;
  else
  if (dflush) state <= idle_st;
  else
  state <= next_state;


always @(*) begin
    next_state = state;

    next_instruction_o = 1'b0;

    
    decoder_flush = 1'b0;

    latch_prefix = 1'b0;
    latch_opcode = 1'b0;
    latch_modrm = 1'b0;

    latch_offset_1 = 1'b0;
    latch_offset_2 = 1'b0;

    latch_immediate_1 = 1'b0;
    latch_immediate_2 = 1'b0;

    decoded_valid_o = 1'b0;

    case (state)
      idle_st: begin


          if (instruction_valid_i) begin
              next_state = prefix_st;
          end
      end
      prefix_st: begin
        if (instruction_valid_i) begin
          if (prefix_decoded) begin
            latch_prefix = 1'b1;
            next_state = prefix_st;
          end
          else begin
            latch_opcode = 1'b1;
            next_state = opcode_st;
          end
          next_instruction_o = 1'b1;
        end
      end
      opcode_st: begin
        if (need_modrm_o) begin
          if (instruction_valid_i) begin
            latch_modrm = 1'b1;
            next_instruction_o = 1'b1;
            next_state = modrm_st;
          end
        end
        else 
        if (need_off_o) next_state = offset_st;
        else
        if (need_imm_o) next_state = immediate_st;
        else
        next_state = execute_st;
      end
      modrm_st: begin
        if (need_off_o) next_state = offset_st;
        else
        if (need_imm_o) next_state = immediate_st;
        else
        next_state = execute_st;
      end
      offset_st: begin
        if (off_size_o) begin
          if (instruction_valid_i) begin
            latch_offset_1 = 1'b1;
            next_instruction_o = 1'b1;
            next_state = offset2_st;
          end
        end
        else
        if (instruction_valid_i) begin
          latch_offset_1 = 1'b1;
          next_instruction_o = 1'b1;
          if (need_imm_o) next_state = immediate_st;
          else next_state = execute_st;
        end
      end
      offset2_st: begin
        if (instruction_valid_i) begin
          latch_offset_2 = 1'b1;
          next_instruction_o = 1'b1;
          if (need_imm_o) next_state = immediate_st;
          else next_state = execute_st;
        end
      end
      immediate_st: begin
        if (imm_size_o) begin
          if (instruction_valid_i) begin
            latch_immediate_1 = 1'b1;
            next_instruction_o = 1'b1;
            next_state = immediate2_st;
          end
        end
        else
        if (instruction_valid_i) begin
          latch_immediate_1 = 1'b1;
          next_instruction_o = 1'b1;
          next_state = execute_st;
        end
      end
      immediate2_st: begin
        if (instruction_valid_i) begin
          latch_immediate_2 = 1'b1;
          next_instruction_o = 1'b1;
          next_state = execute_st;
        end
      end
      execute_st: begin
        decoded_valid_o = 1'b1;
        if (next_decoded_i) begin

          decoder_flush = 1'b1;
          next_state = idle_st;
        end
      end
    endcase
end

endmodule