data/full_repos/permissive/116468596/ringCounter.v
1: b"%Error: data/full_repos/permissive/116468596/ringCounter.v:34: Cannot find file containing module: 'FDRE'\n        FDRE #(.INIT(1'b1) ) ff_instance_1 (.C(clk), .R(reset), .CE(digsel), .D(outQ[3]), .Q(outQ[0]));\n        ^~~~\n        ... Looked in:\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n             FDRE\n             FDRE.v\n             FDRE.sv\n             obj_dir/FDRE\n             obj_dir/FDRE.v\n             obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/ringCounter.v:35: Cannot find file containing module: 'FDRE'\n        FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(digsel), .D(outQ[0]), .Q(outQ[1]));\n        ^~~~\n%Error: data/full_repos/permissive/116468596/ringCounter.v:36: Cannot find file containing module: 'FDRE'\n        FDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(reset), .CE(digsel), .D(outQ[1]), .Q(outQ[2]));\n        ^~~~\n%Error: data/full_repos/permissive/116468596/ringCounter.v:37: Cannot find file containing module: 'FDRE'\n        FDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(reset), .CE(digsel), .D(outQ[2]), .Q(outQ[3]));\n        ^~~~\n%Error: Exiting due to 4 error(s)\n"
module ringCounter(
    input clk,digsel,
    output [3:0] sel
    );
    wire [3:0] outQ;






        FDRE #(.INIT(1'b1) ) ff_instance_1 (.C(clk), .R(reset), .CE(digsel), .D(outQ[3]), .Q(outQ[0]));
        FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(digsel), .D(outQ[0]), .Q(outQ[1]));
        FDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(reset), .CE(digsel), .D(outQ[1]), .Q(outQ[2]));
        FDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(reset), .CE(digsel), .D(outQ[2]), .Q(outQ[3]));
        
        assign sel = outQ;





endmodule
module ringCounter(
    input clk,digsel,
    output [3:0] sel
    );

    wire [3:0] outQ;






        FDRE #(.INIT(1'b1) ) ff_instance_1 (.C(clk), .R(reset), .CE(digsel), .D(outQ[3]), .Q(outQ[0]));
        FDRE #(.INIT(1'b0) ) ff_instance_2 (.C(clk), .R(reset), .CE(digsel), .D(outQ[0]), .Q(outQ[1]));
        FDRE #(.INIT(1'b0) ) ff_instance_3 (.C(clk), .R(reset), .CE(digsel), .D(outQ[1]), .Q(outQ[2]));
        FDRE #(.INIT(1'b0) ) ff_instance_4 (.C(clk), .R(reset), .CE(digsel), .D(outQ[2]), .Q(outQ[3]));
        
        assign sel = outQ;





endmodule