data/full_repos/permissive/217697217/problems/00_invertor/testbench.v
 line:38: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/217697217/problems/00_invertor/testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n     #2 clk = ~clk;  \n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/217697217/problems/00_invertor/testbench.v:36: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;       \n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/217697217/problems/00_invertor/testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;     \n    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

reg clk = 1'b0;

always begin
     #2 clk = ~clk;
end

wire clk1;
wire clk2;
wire clk3;
pset00_test pset00_test(.in(clk), .out(clk1));
pset00_invertor pset00_invertor(.in(clk), .out(clk2));
pset00_halffreq pset00_halffreq(.in(clk), .out(clk3));




initial begin
    $dumpvars;
    $display("Test started...");
    #10 $finish;
end

endmodule
module testbench();


reg clk = 1'b0;

always begin
     #2 clk = ~clk;
end

wire clk1;
wire clk2;
wire clk3;
pset00_test pset00_test(.in(clk), .out(clk1));
pset00_invertor pset00_invertor(.in(clk), .out(clk2));
pset00_halffreq pset00_halffreq(.in(clk), .out(clk3));




initial begin
    $dumpvars;
    $display("Test started...");
    #10 $finish;
end

endmodule