data/full_repos/permissive/143278/ivltests/pr564.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/143278/ivltests/pr564.v:26: Little bit endian vector: MSB < LSB of bit range: 0:7\n   parameter [0:7] backwards = 8\'b10001111;\n             ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module main( );


   parameter [7:0] forwards  = 8'b11110001;
   parameter [0:7] backwards = 8'b10001111;

   integer         i;

   initial begin
      for (i = 0 ;  i < 8 ;  i = i + 1) begin
	 $write("forwards[%0d] === %b, ", i, forwards[i]);
	 $display("backwards[%0d] === %b", i, backwards[i]);

	 if (forwards[i] !== backwards[i]) begin
	    $display("FAILED -- forwards[%0d] !== backwards[%0d]", i, i);
	    $finish;
	 end
      end

      $display("PASSED");
   end
endmodule
module main( );



   parameter [7:0] forwards  = 8'b11110001;
   parameter [0:7] backwards = 8'b10001111;

   integer         i;

   initial begin
      for (i = 0 ;  i < 8 ;  i = i + 1) begin
	 $write("forwards[%0d] === %b, ", i, forwards[i]);
	 $display("backwards[%0d] === %b", i, backwards[i]);

	 if (forwards[i] !== backwards[i]) begin
	    $display("FAILED -- forwards[%0d] !== backwards[%0d]", i, i);
	    $finish;
	 end
      end

      $display("PASSED");
   end
endmodule