data/full_repos/permissive/198139336/FPAdder/fp32_align.v
1: b"%Error: data/full_repos/permissive/198139336/FPAdder/fp32_align.v:21: Duplicate declaration of signal: 'large_frac24'\n                                                                    : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire [23:0] large_frac24 = {fp_large_hidden_bit, fp_large[22:0]};\n             ^~~~~~~~~~~~\n        data/full_repos/permissive/198139336/FPAdder/fp32_align.v:10: ... Location of original declaration\n output [23:0] large_frac24,   \n               ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module fadd_align (		
	input [31:0] a, b,
	input sub,
	output sign,
	output [7:0] temp_exp,
	output op_sub,
	output [23:0] large_frac24,
	output [26:0] small_frac27);


	wire exchange = (b[30:0] > a[30:0]);
	wire [31:0] fp_large = exchange? b : a;
	wire [31:0] fp_small = exchange? a : b;


	wire fp_large_hidden_bit = |fp_large[30:23];
	wire fp_small_hidden_bit = |fp_small[30:23];
	wire [23:0] large_frac24 = {fp_large_hidden_bit, fp_large[22:0]};
	wire [23:0] small_frac24 = {fp_small_hidden_bit, fp_small[22:0]};


	assign temp_exp = fp_large[30:23];


	assign sign = exchange ? sub^b[31] : a[31];
	

	assign op_sub = sub ^ fp_large[31] ^ fp_small[31];
	

	wire [7:0] exp_diff = fp_large[30:23] - fp_small[30:23];
	

	wire [49:0] small_frac50 = (exp_diff >= 26) ? 
								{26'h0, small_frac24} : 
								{small_frac24, 26'h0} >> exp_diff;
	

	assign small_frac27 = {small_frac50[49:24], |small_frac50[23:0]};
endmodule
module fadd_align (		
	input [31:0] a, b,
	input sub,
	output sign,
	output [7:0] temp_exp,
	output op_sub,
	output [23:0] large_frac24,
	output [26:0] small_frac27);



	wire exchange = (b[30:0] > a[30:0]);
	wire [31:0] fp_large = exchange? b : a;
	wire [31:0] fp_small = exchange? a : b;


	wire fp_large_hidden_bit = |fp_large[30:23];
	wire fp_small_hidden_bit = |fp_small[30:23];
	wire [23:0] large_frac24 = {fp_large_hidden_bit, fp_large[22:0]};
	wire [23:0] small_frac24 = {fp_small_hidden_bit, fp_small[22:0]};


	assign temp_exp = fp_large[30:23];


	assign sign = exchange ? sub^b[31] : a[31];
	

	assign op_sub = sub ^ fp_large[31] ^ fp_small[31];
	

	wire [7:0] exp_diff = fp_large[30:23] - fp_small[30:23];
	

	wire [49:0] small_frac50 = (exp_diff >= 26) ? 
								{26'h0, small_frac24} : 
								{small_frac24, 26'h0} >> exp_diff;
	

	assign small_frac27 = {small_frac50[49:24], |small_frac50[23:0]};
endmodule