data/full_repos/permissive/19435930/uart_send_test.v
 line:63: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #18.52;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #18.52;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #18.52;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #18.52;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #18.52;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #18.52;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #9000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #9000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:61: Unsupported: Ignoring delay on this delayed statement.\n always #18.52 CLK <= ~CLK; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/uart_send_test.v:63: Unsupported: Ignoring delay on this delayed statement.\n initial #25000 $finish;\n         ^\n%Error: data/full_repos/permissive/19435930/uart_send_test.v:16: Cannot find file containing module: \'uart_send\'\n uart_send uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/uart_send\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/uart_send.v\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/uart_send.sv\n             uart_send\n             uart_send.v\n             uart_send.sv\n             obj_dir/uart_send\n             obj_dir/uart_send.v\n             obj_dir/uart_send.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_send_test;


	reg RST;
	reg CLK;
	reg [7:0] DATA;
	reg DATA_READY;


	wire TXD;
	wire IDLE;
	

	uart_send uut (
		.RST(RST), 
		.CLK(CLK),
		.DATA(DATA), 
		.DATA_READY(DATA_READY), 
		.TXD(TXD), 
		.IDLE(IDLE)
	);

	initial begin

		RST = 1;
		CLK = 1;
		DATA = 8'bXXXXXXXX;
		DATA_READY = 0;



		#18.52;
		#18.52;
	
		#18.52;
		#18.52;

		RST = 0;
		
		#18.52;
		#18.52;
		
		DATA = 8'b10101010;
		DATA_READY = 1;
		#1000;
		DATA_READY = 0;
		DATA = 8'bXXXXXXXX;
		#9000
		
		DATA = 8'b01001100;
		DATA_READY = 1;
		#1000;
		DATA_READY = 0;
		DATA = 8'bXXXXXXXX;
		#9000;
		
	end

	always #18.52 CLK <= ~CLK;	
	
	initial #25000 $finish;
	
endmodule
module uart_send_test;



	reg RST;
	reg CLK;
	reg [7:0] DATA;
	reg DATA_READY;


	wire TXD;
	wire IDLE;
	

	uart_send uut (
		.RST(RST), 
		.CLK(CLK),
		.DATA(DATA), 
		.DATA_READY(DATA_READY), 
		.TXD(TXD), 
		.IDLE(IDLE)
	);

	initial begin

		RST = 1;
		CLK = 1;
		DATA = 8'bXXXXXXXX;
		DATA_READY = 0;



		#18.52;
		#18.52;
	
		#18.52;
		#18.52;

		RST = 0;
		
		#18.52;
		#18.52;
		
		DATA = 8'b10101010;
		DATA_READY = 1;
		#1000;
		DATA_READY = 0;
		DATA = 8'bXXXXXXXX;
		#9000
		
		DATA = 8'b01001100;
		DATA_READY = 1;
		#1000;
		DATA_READY = 0;
		DATA = 8'bXXXXXXXX;
		#9000;
		
	end

	always #18.52 CLK <= ~CLK;	
	
	initial #25000 $finish;
	
endmodule