data/full_repos/permissive/170267528/state1/TODO/graph/prm_chk_v1_0_S00_AXI.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170267528/state1/TODO/graph/prm_chk_v1_0_S00_AXI.v:785: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                                 : ... In instance prm_chk_v1_0_S00_AXI\n    axi_araddr  <= 32\'b0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/170267528/state1/TODO/graph/prm_chk_v1_0_S00_AXI.v:885: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 10 bits.\n                                                                                                 : ... In instance prm_chk_v1_0_S00_AXI\n   6\'h2A   : reg_data_out <= edgeMask_Wire[1033:1024]; \n                          ^~\n%Error: data/full_repos/permissive/170267528/state1/TODO/graph/prm_chk_v1_0_S00_AXI.v:944: Cannot find file containing module: \'prm_LUT_chk\'\nprm_LUT_chk i_prm_LUT_chk(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170267528/state1/TODO/graph,data/full_repos/permissive/170267528/prm_LUT_chk\n             data/full_repos/permissive/170267528/state1/TODO/graph,data/full_repos/permissive/170267528/prm_LUT_chk.v\n             data/full_repos/permissive/170267528/state1/TODO/graph,data/full_repos/permissive/170267528/prm_LUT_chk.sv\n             prm_LUT_chk\n             prm_LUT_chk.v\n             prm_LUT_chk.sv\n             obj_dir/prm_LUT_chk\n             obj_dir/prm_LUT_chk.v\n             obj_dir/prm_LUT_chk.sv\n%Error: data/full_repos/permissive/170267528/state1/TODO/graph/prm_chk_v1_0_S00_AXI.v:953: Cannot find file containing module: \'graph\'\ngraph i_graph(\n^~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module prm_chk_v1_0_S00_AXI #
	(






		parameter integer C_S_AXI_DATA_WIDTH	= 32,

		parameter integer C_S_AXI_ADDR_WIDTH	= 8
	)
	(

		output [10:0] ramAddress,
		input [15:0] RAMData,




		input wire  S_AXI_ACLK,

		input wire  S_AXI_ARESETN,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



		input wire [2 : 0] S_AXI_AWPROT,


		input wire  S_AXI_AWVALID,


		output wire  S_AXI_AWREADY,

		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


		input wire  S_AXI_WVALID,


		output wire  S_AXI_WREADY,


		output wire [1 : 0] S_AXI_BRESP,


		output wire  S_AXI_BVALID,


		input wire  S_AXI_BREADY,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



		input wire [2 : 0] S_AXI_ARPROT,


		input wire  S_AXI_ARVALID,


		output wire  S_AXI_ARREADY,

		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


		output wire [1 : 0] S_AXI_RRESP,


		output wire  S_AXI_RVALID,


		input wire  S_AXI_RREADY
	);


	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;






	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 5;




	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg4;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg5;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg6;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg7;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg8;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg9;
































	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg42;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg43;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg44;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg45;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg46;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg47;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg48;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg49;
	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;
	reg	 aw_en;


	reg [1033:0] availableEdge = 1034'b0;
	wire [109:0] selectEdge_Wire;
	wire [1033:0] edgeMask_Wire;
	wire [2:0] stateMonitor;





	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_awready <= 1'b0;
		  aw_en <= 1'b1;
		end 
	  else
		begin    
		  if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
			begin




			  axi_awready <= 1'b1;
			  aw_en <= 1'b0;
			end
			else if (S_AXI_BREADY && axi_bvalid)
				begin
				  aw_en <= 1'b1;
				  axi_awready <= 1'b0;
				end
		  else           
			begin
			  axi_awready <= 1'b0;
			end
		end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_awaddr <= 0;
		end 
	  else
		begin    
		  if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
			begin

			  axi_awaddr <= S_AXI_AWADDR;
			end
		end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_wready <= 1'b0;
		end 
	  else
		begin    
		  if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
			begin




			  axi_wready <= 1'b1;
			end
		  else
			begin
			  axi_wready <= 1'b0;
			end
		end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  slv_reg0 <= 0;
		  slv_reg1 <= 0;
		  slv_reg2 <= 0;
		  slv_reg3 <= 0;
		  slv_reg4 <= 0;
		  slv_reg5 <= 0;
		  slv_reg6 <= 0;
		  slv_reg7 <= 0;
		  slv_reg8 <= 0;
		  slv_reg9 <= 0;
































		  slv_reg42 <= 0;
		  slv_reg43 <= 0;
		  slv_reg44 <= 0;
		  slv_reg45 <= 0;
		  slv_reg46 <= 0;
		  slv_reg47 <= 0;
		  slv_reg48 <= 0;
		  slv_reg49 <= 0;
		end 
	  else begin
		if (slv_reg_wren)
		  begin
			case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
			  6'h00:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h01:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h02:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h03:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h04:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h05:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h06:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h07:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h08:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h09:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
































































































































































































































			  6'h2A:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg42[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h2B:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg43[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h2C:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg44[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h2D:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg45[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h2E:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg46[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h2F:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg47[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h30:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg48[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h31:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg49[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  default : begin
						  slv_reg0 <= slv_reg0;
						  slv_reg1 <= slv_reg1;
						  slv_reg2 <= slv_reg2;
						  slv_reg3 <= slv_reg3;
						  slv_reg4 <= slv_reg4;
						  slv_reg5 <= slv_reg5;
						  slv_reg6 <= slv_reg6;
						  slv_reg7 <= slv_reg7;
						  slv_reg8 <= slv_reg8;
						  slv_reg9 <= slv_reg9;
































						  slv_reg42 <= slv_reg42;
						  slv_reg43 <= slv_reg43;
						  slv_reg44 <= slv_reg44;
						  slv_reg45 <= slv_reg45;
						  slv_reg46 <= slv_reg46;
						  slv_reg47 <= slv_reg47;
						  slv_reg48 <= slv_reg48;
						  slv_reg49 <= slv_reg49;
						end
			endcase
		  end
	  end
	end    







	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_bvalid  <= 0;
		  axi_bresp   <= 2'b0;
		end 
	  else
		begin    
		  if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
			begin

			  axi_bvalid <= 1'b1;
			  axi_bresp  <= 2'b0;
			end
		  else
			begin
			  if (S_AXI_BREADY && axi_bvalid) 


				begin
				  axi_bvalid <= 1'b0; 
				end  
			end
		end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_arready <= 1'b0;
		  axi_araddr  <= 32'b0;
		end 
	  else
		begin    
		  if (~axi_arready && S_AXI_ARVALID)
			begin

			  axi_arready <= 1'b1;

			  axi_araddr  <= S_AXI_ARADDR;
			end
		  else
			begin
			  axi_arready <= 1'b0;
			end
		end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_rvalid <= 0;
		  axi_rresp  <= 0;
		end 
	  else
		begin    
		  if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
			begin

			  axi_rvalid <= 1'b1;
			  axi_rresp  <= 2'b0;
			end   
		  else if (axi_rvalid && S_AXI_RREADY)
			begin

			  axi_rvalid <= 1'b0;
			end                
		end
	end    




	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

		  case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )

			6'h00   : reg_data_out <= {21'b0,selectEdge_Wire[10:0]};
			6'h01   : reg_data_out <= {21'b0,selectEdge_Wire[21:11]};
			6'h02   : reg_data_out <= {21'b0,selectEdge_Wire[32:22]};
			6'h03   : reg_data_out <= {21'b0,selectEdge_Wire[43:33]};
			6'h04   : reg_data_out <= {21'b0,selectEdge_Wire[54:44]};
			6'h05   : reg_data_out <= {21'b0,selectEdge_Wire[65:55]};
			6'h06   : reg_data_out <= {21'b0,selectEdge_Wire[76:66]};
			6'h07   : reg_data_out <= {21'b0,selectEdge_Wire[87:77]};
			6'h08   : reg_data_out <= {21'b0,selectEdge_Wire[98:88]};
			6'h09   : reg_data_out <= {21'b0,selectEdge_Wire[109:99]};
			6'h0A   : reg_data_out <= edgeMask_Wire[31:0];
			6'h0B   : reg_data_out <= edgeMask_Wire[63:32];
			6'h0C   : reg_data_out <= edgeMask_Wire[95:64];
			6'h0D   : reg_data_out <= edgeMask_Wire[127:96];
			6'h0E   : reg_data_out <= edgeMask_Wire[159:128];
			6'h0F   : reg_data_out <= edgeMask_Wire[191:160];
			6'h10   : reg_data_out <= edgeMask_Wire[223:192];
			6'h11   : reg_data_out <= edgeMask_Wire[255:224];
			6'h12   : reg_data_out <= edgeMask_Wire[287:256];
			6'h13   : reg_data_out <= edgeMask_Wire[319:288];
			6'h14   : reg_data_out <= edgeMask_Wire[351:320];
			6'h15   : reg_data_out <= edgeMask_Wire[383:352];
			6'h16   : reg_data_out <= edgeMask_Wire[415:384];
			6'h17   : reg_data_out <= edgeMask_Wire[447:416];
			6'h18   : reg_data_out <= edgeMask_Wire[479:448];
			6'h19   : reg_data_out <= edgeMask_Wire[511:480];
			6'h1A   : reg_data_out <= edgeMask_Wire[543:512];
			6'h1B   : reg_data_out <= edgeMask_Wire[575:544];
			6'h1C   : reg_data_out <= edgeMask_Wire[607:576];
			6'h1D   : reg_data_out <= edgeMask_Wire[639:608];
			6'h1E   : reg_data_out <= edgeMask_Wire[671:640];
			6'h1F   : reg_data_out <= edgeMask_Wire[703:672];
			6'h20   : reg_data_out <= edgeMask_Wire[735:704];
			6'h21   : reg_data_out <= edgeMask_Wire[767:736];
			6'h22   : reg_data_out <= edgeMask_Wire[799:768];
			6'h23   : reg_data_out <= edgeMask_Wire[831:800];
			6'h24   : reg_data_out <= edgeMask_Wire[863:832];
			6'h25   : reg_data_out <= edgeMask_Wire[895:864];
			6'h26   : reg_data_out <= edgeMask_Wire[927:896];
			6'h27   : reg_data_out <= edgeMask_Wire[959:928];
			6'h28   : reg_data_out <= edgeMask_Wire[991:960];
			6'h29   : reg_data_out <= edgeMask_Wire[1023:992];
			6'h2A   : reg_data_out <= edgeMask_Wire[1033:1024];
			6'h2B   : reg_data_out <= {29'b0,stateMonitor};
			6'h2C   : reg_data_out <= slv_reg44;
			6'h2D   : reg_data_out <= slv_reg45;
			6'h2E   : reg_data_out <= slv_reg46;
			6'h2F   : reg_data_out <= slv_reg47;
			6'h30   : reg_data_out <= slv_reg48;
			6'h31   : reg_data_out <= slv_reg49;
			default : reg_data_out <= 0;
		  endcase
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_rdata  <= 0;
		end 
	  else
		begin    



		  if (slv_reg_rden)
			begin
			  axi_rdata <= reg_data_out;
			end   
		end
	end    








	wire [1033:0] outputMask_Wire;

	always @ ( posedge S_AXI_ACLK ) begin

		if ( S_AXI_ARESETN == 1'b0 || slv_reg49[0] == 1'b1 ) begin
			availableEdge <= 1034'b0;



		end

		else begin
			availableEdge <= availableEdge | outputMask_Wire;

		end
	end





prm_LUT_chk i_prm_LUT_chk(
	.X(slv_reg48[13:10]),
	.Y(slv_reg48[9:5]),
	.Z(slv_reg48[4:0]),
	.edge_mask(outputMask_Wire)
);



graph i_graph(
	.CLK(S_AXI_ACLK),
	.RST_n(S_AXI_ARESETN),
	.edgeMask(availableEdge),
	.control(slv_reg49[2:0]),
	.startPose(slv_reg47[7:0]),
	.endPose(slv_reg46[7:0]),


	.ramAddress(ramAddress),
	.RAMData(RAMData),

	.edgeMask_Reg(edgeMask_Wire),
	.selectEdge(selectEdge_Wire),


	.state(stateMonitor)
);


	endmodule
module prm_chk_v1_0_S00_AXI #
	(






		parameter integer C_S_AXI_DATA_WIDTH	= 32,

		parameter integer C_S_AXI_ADDR_WIDTH	= 8
	)
	(

		output [10:0] ramAddress,
		input [15:0] RAMData,




		input wire  S_AXI_ACLK,

		input wire  S_AXI_ARESETN,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



		input wire [2 : 0] S_AXI_AWPROT,


		input wire  S_AXI_AWVALID,


		output wire  S_AXI_AWREADY,

		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


		input wire  S_AXI_WVALID,


		output wire  S_AXI_WREADY,


		output wire [1 : 0] S_AXI_BRESP,


		output wire  S_AXI_BVALID,


		input wire  S_AXI_BREADY,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



		input wire [2 : 0] S_AXI_ARPROT,


		input wire  S_AXI_ARVALID,


		output wire  S_AXI_ARREADY,

		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


		output wire [1 : 0] S_AXI_RRESP,


		output wire  S_AXI_RVALID,


		input wire  S_AXI_RREADY
	);



	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;






	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 5;




	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg4;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg5;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg6;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg7;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg8;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg9;
































	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg42;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg43;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg44;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg45;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg46;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg47;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg48;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg49;
	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;
	reg	 aw_en;


	reg [1033:0] availableEdge = 1034'b0;
	wire [109:0] selectEdge_Wire;
	wire [1033:0] edgeMask_Wire;
	wire [2:0] stateMonitor;





	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_awready <= 1'b0;
		  aw_en <= 1'b1;
		end 
	  else
		begin    
		  if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
			begin




			  axi_awready <= 1'b1;
			  aw_en <= 1'b0;
			end
			else if (S_AXI_BREADY && axi_bvalid)
				begin
				  aw_en <= 1'b1;
				  axi_awready <= 1'b0;
				end
		  else           
			begin
			  axi_awready <= 1'b0;
			end
		end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_awaddr <= 0;
		end 
	  else
		begin    
		  if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
			begin

			  axi_awaddr <= S_AXI_AWADDR;
			end
		end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_wready <= 1'b0;
		end 
	  else
		begin    
		  if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
			begin




			  axi_wready <= 1'b1;
			end
		  else
			begin
			  axi_wready <= 1'b0;
			end
		end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  slv_reg0 <= 0;
		  slv_reg1 <= 0;
		  slv_reg2 <= 0;
		  slv_reg3 <= 0;
		  slv_reg4 <= 0;
		  slv_reg5 <= 0;
		  slv_reg6 <= 0;
		  slv_reg7 <= 0;
		  slv_reg8 <= 0;
		  slv_reg9 <= 0;
































		  slv_reg42 <= 0;
		  slv_reg43 <= 0;
		  slv_reg44 <= 0;
		  slv_reg45 <= 0;
		  slv_reg46 <= 0;
		  slv_reg47 <= 0;
		  slv_reg48 <= 0;
		  slv_reg49 <= 0;
		end 
	  else begin
		if (slv_reg_wren)
		  begin
			case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
			  6'h00:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h01:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h02:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h03:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h04:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h05:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h06:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h07:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h08:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h09:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
































































































































































































































			  6'h2A:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg42[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h2B:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg43[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h2C:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg44[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h2D:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg45[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h2E:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg46[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h2F:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg47[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h30:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg48[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  6'h31:
				for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
				  if ( S_AXI_WSTRB[byte_index] == 1 ) begin


					slv_reg49[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
				  end  
			  default : begin
						  slv_reg0 <= slv_reg0;
						  slv_reg1 <= slv_reg1;
						  slv_reg2 <= slv_reg2;
						  slv_reg3 <= slv_reg3;
						  slv_reg4 <= slv_reg4;
						  slv_reg5 <= slv_reg5;
						  slv_reg6 <= slv_reg6;
						  slv_reg7 <= slv_reg7;
						  slv_reg8 <= slv_reg8;
						  slv_reg9 <= slv_reg9;
































						  slv_reg42 <= slv_reg42;
						  slv_reg43 <= slv_reg43;
						  slv_reg44 <= slv_reg44;
						  slv_reg45 <= slv_reg45;
						  slv_reg46 <= slv_reg46;
						  slv_reg47 <= slv_reg47;
						  slv_reg48 <= slv_reg48;
						  slv_reg49 <= slv_reg49;
						end
			endcase
		  end
	  end
	end    







	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_bvalid  <= 0;
		  axi_bresp   <= 2'b0;
		end 
	  else
		begin    
		  if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
			begin

			  axi_bvalid <= 1'b1;
			  axi_bresp  <= 2'b0;
			end
		  else
			begin
			  if (S_AXI_BREADY && axi_bvalid) 


				begin
				  axi_bvalid <= 1'b0; 
				end  
			end
		end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_arready <= 1'b0;
		  axi_araddr  <= 32'b0;
		end 
	  else
		begin    
		  if (~axi_arready && S_AXI_ARVALID)
			begin

			  axi_arready <= 1'b1;

			  axi_araddr  <= S_AXI_ARADDR;
			end
		  else
			begin
			  axi_arready <= 1'b0;
			end
		end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_rvalid <= 0;
		  axi_rresp  <= 0;
		end 
	  else
		begin    
		  if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
			begin

			  axi_rvalid <= 1'b1;
			  axi_rresp  <= 2'b0;
			end   
		  else if (axi_rvalid && S_AXI_RREADY)
			begin

			  axi_rvalid <= 1'b0;
			end                
		end
	end    




	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

		  case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )

			6'h00   : reg_data_out <= {21'b0,selectEdge_Wire[10:0]};
			6'h01   : reg_data_out <= {21'b0,selectEdge_Wire[21:11]};
			6'h02   : reg_data_out <= {21'b0,selectEdge_Wire[32:22]};
			6'h03   : reg_data_out <= {21'b0,selectEdge_Wire[43:33]};
			6'h04   : reg_data_out <= {21'b0,selectEdge_Wire[54:44]};
			6'h05   : reg_data_out <= {21'b0,selectEdge_Wire[65:55]};
			6'h06   : reg_data_out <= {21'b0,selectEdge_Wire[76:66]};
			6'h07   : reg_data_out <= {21'b0,selectEdge_Wire[87:77]};
			6'h08   : reg_data_out <= {21'b0,selectEdge_Wire[98:88]};
			6'h09   : reg_data_out <= {21'b0,selectEdge_Wire[109:99]};
			6'h0A   : reg_data_out <= edgeMask_Wire[31:0];
			6'h0B   : reg_data_out <= edgeMask_Wire[63:32];
			6'h0C   : reg_data_out <= edgeMask_Wire[95:64];
			6'h0D   : reg_data_out <= edgeMask_Wire[127:96];
			6'h0E   : reg_data_out <= edgeMask_Wire[159:128];
			6'h0F   : reg_data_out <= edgeMask_Wire[191:160];
			6'h10   : reg_data_out <= edgeMask_Wire[223:192];
			6'h11   : reg_data_out <= edgeMask_Wire[255:224];
			6'h12   : reg_data_out <= edgeMask_Wire[287:256];
			6'h13   : reg_data_out <= edgeMask_Wire[319:288];
			6'h14   : reg_data_out <= edgeMask_Wire[351:320];
			6'h15   : reg_data_out <= edgeMask_Wire[383:352];
			6'h16   : reg_data_out <= edgeMask_Wire[415:384];
			6'h17   : reg_data_out <= edgeMask_Wire[447:416];
			6'h18   : reg_data_out <= edgeMask_Wire[479:448];
			6'h19   : reg_data_out <= edgeMask_Wire[511:480];
			6'h1A   : reg_data_out <= edgeMask_Wire[543:512];
			6'h1B   : reg_data_out <= edgeMask_Wire[575:544];
			6'h1C   : reg_data_out <= edgeMask_Wire[607:576];
			6'h1D   : reg_data_out <= edgeMask_Wire[639:608];
			6'h1E   : reg_data_out <= edgeMask_Wire[671:640];
			6'h1F   : reg_data_out <= edgeMask_Wire[703:672];
			6'h20   : reg_data_out <= edgeMask_Wire[735:704];
			6'h21   : reg_data_out <= edgeMask_Wire[767:736];
			6'h22   : reg_data_out <= edgeMask_Wire[799:768];
			6'h23   : reg_data_out <= edgeMask_Wire[831:800];
			6'h24   : reg_data_out <= edgeMask_Wire[863:832];
			6'h25   : reg_data_out <= edgeMask_Wire[895:864];
			6'h26   : reg_data_out <= edgeMask_Wire[927:896];
			6'h27   : reg_data_out <= edgeMask_Wire[959:928];
			6'h28   : reg_data_out <= edgeMask_Wire[991:960];
			6'h29   : reg_data_out <= edgeMask_Wire[1023:992];
			6'h2A   : reg_data_out <= edgeMask_Wire[1033:1024];
			6'h2B   : reg_data_out <= {29'b0,stateMonitor};
			6'h2C   : reg_data_out <= slv_reg44;
			6'h2D   : reg_data_out <= slv_reg45;
			6'h2E   : reg_data_out <= slv_reg46;
			6'h2F   : reg_data_out <= slv_reg47;
			6'h30   : reg_data_out <= slv_reg48;
			6'h31   : reg_data_out <= slv_reg49;
			default : reg_data_out <= 0;
		  endcase
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
		begin
		  axi_rdata  <= 0;
		end 
	  else
		begin    



		  if (slv_reg_rden)
			begin
			  axi_rdata <= reg_data_out;
			end   
		end
	end    








	wire [1033:0] outputMask_Wire;

	always @ ( posedge S_AXI_ACLK ) begin

		if ( S_AXI_ARESETN == 1'b0 || slv_reg49[0] == 1'b1 ) begin
			availableEdge <= 1034'b0;



		end

		else begin
			availableEdge <= availableEdge | outputMask_Wire;

		end
	end





prm_LUT_chk i_prm_LUT_chk(
	.X(slv_reg48[13:10]),
	.Y(slv_reg48[9:5]),
	.Z(slv_reg48[4:0]),
	.edge_mask(outputMask_Wire)
);



graph i_graph(
	.CLK(S_AXI_ACLK),
	.RST_n(S_AXI_ARESETN),
	.edgeMask(availableEdge),
	.control(slv_reg49[2:0]),
	.startPose(slv_reg47[7:0]),
	.endPose(slv_reg46[7:0]),


	.ramAddress(ramAddress),
	.RAMData(RAMData),

	.edgeMask_Reg(edgeMask_Wire),
	.selectEdge(selectEdge_Wire),


	.state(stateMonitor)
);


	endmodule