data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v
1: b'%Error: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:23: Cannot find include file: encoder.syn.v\n`include "encoder.syn.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3,data/full_repos/permissive/20688874/encoder.syn.v\n             data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3,data/full_repos/permissive/20688874/encoder.syn.v.v\n             data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3,data/full_repos/permissive/20688874/encoder.syn.v.sv\n             encoder.syn.v\n             encoder.syn.v.v\n             encoder.syn.v.sv\n             obj_dir/encoder.syn.v\n             obj_dir/encoder.syn.v.v\n             obj_dir/encoder.syn.v.sv\n%Error: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:24: Cannot find include file: decoder.syn.v\n`include "decoder.syn.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:25: Cannot find include file: pipelinedec.v\n`include "pipelinedec.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:26: Cannot find include file: /auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v\n`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"  \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:102: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:103: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk = 1;\n     ^\n%Error: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:182: Unsupported or unknown PLI call: $sdf_annotate\n  $sdf_annotate("../sdf/encoder.sdf",enc,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:183: Unsupported or unknown PLI call: $sdf_annotate\n  $sdf_annotate("../sdf/decoder.sdf",dec,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");\n  ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:189: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:196: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:204: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:211: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:218: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:230: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:236: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:242: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:248: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/syn/netlist/test_case_3/pipelinedectb.v:255: Unsupported: Ignoring delay on this delayed statement.\n  #300;\n  ^\n%Error: Exiting due to 6 error(s), 13 warning(s)\n'
module tb_pipeline();

	


	wire [18:0] c;

	wire [18:0] cx;

	wire [5:0] q;

	
	


	reg [5:0] b;
	reg [5:0] r_b;
	reg [18:0] e;
	reg [18:0] r_e;

	reg [18:0] r_c;
	reg [18:0] rr_e;
	reg [5:0] rr_b;




	reg [18:0] r_qx;
	reg [5:0] rb;
	
	reg clk,reset;
	reg [18:0] e2;
	
	
	
	encoder enc (


		r_b,c);
	
	decoder dec (


		r_qx,q);
	
	large_xor xr (


		r_c,rr_e,cx);
	
	
	
	

	always begin

    	#10 clk = 0;
    	#10 clk = 1;
    end		
	
	
	
	
	
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			r_b<=0;
			r_e<=0;
		end
		else
		begin
			r_e<=e;
			r_b<=b;
		end
	end
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			r_c<=0;
			rr_e<=0;
			rr_b<=0;
		end
		else
		begin
			r_c<=c;
			rr_e<=r_e;
			rr_b<=r_b;
		end
	end
	
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			rb<=0;
		end
		else
		begin
			r_qx<=cx;
			rb<=rr_b;
			e2<=rr_e;
		end
	end
	

	

	initial
	begin
		$sdf_annotate("../sdf/encoder.sdf",enc,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
		$sdf_annotate("../sdf/decoder.sdf",dec,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
		
		

		$display(" << Starting the simulation >>");
		reset=1;
		#20;
		reset=0;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		

		#20;
		b = $random;
		e = 19'b0000010000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		
		#20;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		
		#20;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0000100000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0000000000100000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0010000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
				
		#300;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_pipeline();


	


	wire [18:0] c;

	wire [18:0] cx;

	wire [5:0] q;

	
	


	reg [5:0] b;
	reg [5:0] r_b;
	reg [18:0] e;
	reg [18:0] r_e;

	reg [18:0] r_c;
	reg [18:0] rr_e;
	reg [5:0] rr_b;




	reg [18:0] r_qx;
	reg [5:0] rb;
	
	reg clk,reset;
	reg [18:0] e2;
	
	
	
	encoder enc (


		r_b,c);
	
	decoder dec (


		r_qx,q);
	
	large_xor xr (


		r_c,rr_e,cx);
	
	
	
	

	always begin

    	#10 clk = 0;
    	#10 clk = 1;
    end		
	
	
	
	
	
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			r_b<=0;
			r_e<=0;
		end
		else
		begin
			r_e<=e;
			r_b<=b;
		end
	end
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			r_c<=0;
			rr_e<=0;
			rr_b<=0;
		end
		else
		begin
			r_c<=c;
			rr_e<=r_e;
			rr_b<=r_b;
		end
	end
	
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			rb<=0;
		end
		else
		begin
			r_qx<=cx;
			rb<=rr_b;
			e2<=rr_e;
		end
	end
	

	

	initial
	begin
		$sdf_annotate("../sdf/encoder.sdf",enc,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
		$sdf_annotate("../sdf/decoder.sdf",dec,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
		
		

		$display(" << Starting the simulation >>");
		reset=1;
		#20;
		reset=0;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		

		#20;
		b = $random;
		e = 19'b0000010000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		
		#20;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		
		#20;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0000100000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0000000000100000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0010000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 19'b0000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
				
		#300;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule