data/full_repos/permissive/220187565/wishbone_cyc10/rom_wishbone.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/220187565/wishbone_cyc10/rom_wishbone.v:1: Cannot find include file: cpu/defines.v\n`include "cpu/defines.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220187565/wishbone_cyc10,data/full_repos/permissive/220187565/cpu/defines.v\n             data/full_repos/permissive/220187565/wishbone_cyc10,data/full_repos/permissive/220187565/cpu/defines.v.v\n             data/full_repos/permissive/220187565/wishbone_cyc10,data/full_repos/permissive/220187565/cpu/defines.v.sv\n             cpu/defines.v\n             cpu/defines.v.v\n             cpu/defines.v.sv\n             obj_dir/cpu/defines.v\n             obj_dir/cpu/defines.v.v\n             obj_dir/cpu/defines.v.sv\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/rom_wishbone.v:6: Define or directive not defined: \'`WishboneDataBus\'\n  input  [`WishboneDataBus]  wishbone_addr_i,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/rom_wishbone.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input  [`WishboneDataBus]  wishbone_addr_i,\n                          ^\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/rom_wishbone.v:7: Define or directive not defined: \'`WishboneDataBus\'\n  input  [`WishboneDataBus]  wishbone_data_i,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/rom_wishbone.v:9: Define or directive not defined: \'`WishboneSelBus\'\n  input  [`WishboneSelBus]  wishbone_sel_i,\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/rom_wishbone.v:12: Define or directive not defined: \'`WishboneDataBus\'\n  output [`WishboneDataBus] wishbone_data_o,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/rom_wishbone.v:33: syntax error, unexpected assign\n assign request = wishbone_stb_i & wishbone_cyc_i;\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/rom_wishbone.v:36: Define or directive not defined: \'`RstEnable\'\n  if(rst_n == `RstEnable)\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/rom_wishbone.v:45: Define or directive not defined: \'`RstEnable\'\n  if (rst_n == `RstEnable)\n               ^~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module rom_wishbone (
	 input 						 	 clk,
	 input 						 	 rst_n,	
	 input  [`WishboneDataBus]	 wishbone_addr_i,
	 input  [`WishboneDataBus]  wishbone_data_i,
	 input							 wishbone_we_i,
	 input  [`WishboneSelBus]	 wishbone_sel_i,
	 input 							 wishbone_stb_i,
	 input							 wishbone_cyc_i,
	 output	[`WishboneDataBus] wishbone_data_o,
	 output							 wishbone_ack_o
);

ip_rom ip_rom0 (
	.address		(wishbone_addr_i[15:2]),
	.clock		(clk),	
	.q				(wishbone_data_o)
);


	wire request;


	reg  request_delay;
	wire request_rising_edge;


	reg  [2:0]ram_ack_delay;


	assign request = wishbone_stb_i & wishbone_cyc_i;

	always @ (posedge clk or negedge rst_n)
		if(rst_n == `RstEnable)
			request_delay <= 1'b0;
		else
			request_delay <= request;
 
 	assign request_rising_edge = ((request_delay ^ request) & request) | (request & request_delay & ram_ack_delay[2]);

always @ (posedge clk or negedge rst_n)
	begin
		if (rst_n == `RstEnable)
		begin
			{ram_ack_delay} <= 3'b000;
		end
		else if(request == 1'b0)
		begin
			{ram_ack_delay} <= 3'b000;
		end
		else if (request_rising_edge == 1'b1)
		begin
			{ram_ack_delay} <= {ram_ack_delay[1:0], 1'b1};	
		end
		else
		begin
			{ram_ack_delay} <= {ram_ack_delay[1:0], 1'b0};
		end
	end

	assign wishbone_ack_o = ram_ack_delay[0] & request;


endmodule
module rom_wishbone (
	 input 						 	 clk,
	 input 						 	 rst_n,	
	 input  [`WishboneDataBus]	 wishbone_addr_i,
	 input  [`WishboneDataBus]  wishbone_data_i,
	 input							 wishbone_we_i,
	 input  [`WishboneSelBus]	 wishbone_sel_i,
	 input 							 wishbone_stb_i,
	 input							 wishbone_cyc_i,
	 output	[`WishboneDataBus] wishbone_data_o,
	 output							 wishbone_ack_o
);


ip_rom ip_rom0 (
	.address		(wishbone_addr_i[15:2]),
	.clock		(clk),	
	.q				(wishbone_data_o)
);


	wire request;


	reg  request_delay;
	wire request_rising_edge;


	reg  [2:0]ram_ack_delay;


	assign request = wishbone_stb_i & wishbone_cyc_i;

	always @ (posedge clk or negedge rst_n)
		if(rst_n == `RstEnable)
			request_delay <= 1'b0;
		else
			request_delay <= request;
 
 	assign request_rising_edge = ((request_delay ^ request) & request) | (request & request_delay & ram_ack_delay[2]);

always @ (posedge clk or negedge rst_n)
	begin
		if (rst_n == `RstEnable)
		begin
			{ram_ack_delay} <= 3'b000;
		end
		else if(request == 1'b0)
		begin
			{ram_ack_delay} <= 3'b000;
		end
		else if (request_rising_edge == 1'b1)
		begin
			{ram_ack_delay} <= {ram_ack_delay[1:0], 1'b1};	
		end
		else
		begin
			{ram_ack_delay} <= {ram_ack_delay[1:0], 1'b0};
		end
	end

	assign wishbone_ack_o = ram_ack_delay[0] & request;


endmodule