data/full_repos/permissive/143278/ivltests/vhdl_elab_range.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_elab_range.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_elab_range.v:24: Cannot find file containing module: \'vhdl_elab_range\'\nvhdl_elab_range dut(left, right);\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_elab_range\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_elab_range.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_elab_range.sv\n             vhdl_elab_range\n             vhdl_elab_range.v\n             vhdl_elab_range.sv\n             obj_dir/vhdl_elab_range\n             obj_dir/vhdl_elab_range.v\n             obj_dir/vhdl_elab_range.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vhdl_elab_range_test;
integer left, right;
vhdl_elab_range dut(left, right);

initial begin
    #1;

    if(left !== 2) begin
        $display("FAILED 1");
        $finish();
    end

    if(right !== 0) begin
        $display("FAILED 2");
        $finish();
    end

    $display("PASSED");
end

endmodule
module vhdl_elab_range_test;

integer left, right;
vhdl_elab_range dut(left, right);

initial begin
    #1;

    if(left !== 2) begin
        $display("FAILED 1");
        $finish();
    end

    if(right !== 0) begin
        $display("FAILED 2");
        $finish();
    end

    $display("PASSED");
end

endmodule