data/full_repos/permissive/143278/ivltests/always3.1.6B.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:28: Unsupported: Ignoring delay on this delayed statement.\n           #0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:30: Unsupported: Ignoring delay on this delayed statement.\n           #1 ;      \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:32: Unsupported: Ignoring delay on this delayed statement.\n           #9 ;         \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:38: Unsupported: Ignoring delay on this delayed statement.\n           #1 ;      \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:41: Unsupported: Ignoring delay on this delayed statement.\n           #5 ;      \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:47: Unsupported: Ignoring delay on this delayed statement.\n           #1;      \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:50: Unsupported: Ignoring delay on this delayed statement.\n           #5;      \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:57: Unsupported: Ignoring delay on this delayed statement.\n           #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:65: Unsupported: Ignoring delay on this delayed statement.\n                            #3 ;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:67: Unsupported: Ignoring delay on this delayed statement.\n                            #3 ;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:70: Unsupported: Ignoring delay on this delayed statement.\n                            #3 ;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:72: Unsupported: Ignoring delay on this delayed statement.\n                            #3 ;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:75: Unsupported: Ignoring delay on this delayed statement.\n                            #3 ;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.6B.v:77: Unsupported: Ignoring delay on this delayed statement.\n                            #3 ;\n                            ^\n%Error: Exiting due to 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ;

reg [3:0] value1,value2,value3;

initial
	begin
           #0;
           value3 = 0;
           #1 ;
           value1 = 4'b0000 ;
           #9 ;
           if(value2 != 4'b0)
             begin
                $display("FAILED - always3.1.6B - casex 0 at %t",$time);
                value3 = 1;
             end
           #1 ;
           value1 = 4'b0011 ;

           #5 ;
           if(value2 != 4'b0001)
             begin
                $display("FAILED - always3.1.6B - casex 1 at %t",$time);
                value3 = 1;
             end
           #1;
           value1 = 4'b0100;

           #5;
           if(value2 != 4'b0010)
             begin
                $display("FAILED - always3.1.6B - casex 2 at %t",$time);
                value3 = 1;
             end

           #10;
           if(value3 == 0)
              $display("PASSED");
	   $finish;
        end

always  casex (value1)
               4'b0000: begin
                            #3 ;
                            value2 = 4'b0000 ;
                            #3 ;
                        end
               4'b00x1: begin
                            #3 ;
                            value2 = 4'b0001 ;
                            #3 ;
                        end
               4'b0100: begin
                            #3 ;
                            value2 = 4'b0010 ;
                            #3 ;
                        end
         endcase


endmodule
module main ;


reg [3:0] value1,value2,value3;

initial
	begin
           #0;
           value3 = 0;
           #1 ;
           value1 = 4'b0000 ;
           #9 ;
           if(value2 != 4'b0)
             begin
                $display("FAILED - always3.1.6B - casex 0 at %t",$time);
                value3 = 1;
             end
           #1 ;
           value1 = 4'b0011 ;

           #5 ;
           if(value2 != 4'b0001)
             begin
                $display("FAILED - always3.1.6B - casex 1 at %t",$time);
                value3 = 1;
             end
           #1;
           value1 = 4'b0100;

           #5;
           if(value2 != 4'b0010)
             begin
                $display("FAILED - always3.1.6B - casex 2 at %t",$time);
                value3 = 1;
             end

           #10;
           if(value3 == 0)
              $display("PASSED");
	   $finish;
        end

always  casex (value1)
               4'b0000: begin
                            #3 ;
                            value2 = 4'b0000 ;
                            #3 ;
                        end
               4'b00x1: begin
                            #3 ;
                            value2 = 4'b0001 ;
                            #3 ;
                        end
               4'b0100: begin
                            #3 ;
                            value2 = 4'b0010 ;
                            #3 ;
                        end
         endcase


endmodule