data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/counter_4.v
 line:26: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/counter_4.v:26: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                           : ... In instance counter_4\n  reg [13:0] M_ctr_d, M_ctr_q = 1\'h0;\n                                ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/counter_4.v:37: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                           : ... In instance counter_4\n        M_ctr_d = 1\'h0;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/counter_4.v:36: Operator EQ expects 14 bits on the RHS, but RHS\'s CONST \'11\'h3ff\' generates 11 bits.\n                                                                                                                                                           : ... In instance counter_4\n      if (1\'h0 && M_ctr_q == 11\'h3ff) begin\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/counter_4.v:42: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h3ff\' generates 11 bits.\n                                                                                                                                                           : ... In instance counter_4\n        M_ctr_d = 11\'h3ff;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/counter_4.v:41: Operator EQ expects 14 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                           : ... In instance counter_4\n      if (1\'h0 && M_ctr_q == 1\'h0) begin\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/counter_4.v:49: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                           : ... In instance counter_4\n      M_ctr_q <= 1\'h0;\n              ^~\n%Error: Exiting due to 6 warning(s)\n'
module counter_4 (
    input clk,
    input rst,
    output reg [3:0] value
  );
  
  localparam SIZE = 3'h4;
  localparam DIV = 4'ha;
  localparam TOP = 1'h0;
  localparam UP = 1'h1;
  
  
  reg [13:0] M_ctr_d, M_ctr_q = 1'h0;
  
  localparam MAX_VALUE = 11'h3ff;
  
  always @* begin
    M_ctr_d = M_ctr_q;
    
    value = M_ctr_q[10+3-:4];
    if (1'h1) begin
      M_ctr_d = M_ctr_q + 1'h1;
      if (1'h0 && M_ctr_q == 11'h3ff) begin
        M_ctr_d = 1'h0;
      end
    end else begin
      M_ctr_d = M_ctr_q - 1'h1;
      if (1'h0 && M_ctr_q == 1'h0) begin
        M_ctr_d = 11'h3ff;
      end
    end
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_ctr_q <= 1'h0;
    end else begin
      M_ctr_q <= M_ctr_d;
    end
  end
  
endmodule
module counter_4 (
    input clk,
    input rst,
    output reg [3:0] value
  );

  
  localparam SIZE = 3'h4;
  localparam DIV = 4'ha;
  localparam TOP = 1'h0;
  localparam UP = 1'h1;
  
  
  reg [13:0] M_ctr_d, M_ctr_q = 1'h0;
  
  localparam MAX_VALUE = 11'h3ff;
  
  always @* begin
    M_ctr_d = M_ctr_q;
    
    value = M_ctr_q[10+3-:4];
    if (1'h1) begin
      M_ctr_d = M_ctr_q + 1'h1;
      if (1'h0 && M_ctr_q == 11'h3ff) begin
        M_ctr_d = 1'h0;
      end
    end else begin
      M_ctr_d = M_ctr_q - 1'h1;
      if (1'h0 && M_ctr_q == 1'h0) begin
        M_ctr_d = 11'h3ff;
      end
    end
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_ctr_q <= 1'h0;
    end else begin
      M_ctr_q <= M_ctr_d;
    end
  end
  
endmodule