data/full_repos/permissive/206437232/TP1-ALU-2019/Verilog/Top_ALU.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/206437232/TP1-ALU-2019/Verilog/Top_ALU.v:44: Cannot find file containing module: \'ALU\'\n    ALU\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP1-ALU-2019/Verilog,data/full_repos/permissive/206437232/ALU\n             data/full_repos/permissive/206437232/TP1-ALU-2019/Verilog,data/full_repos/permissive/206437232/ALU.v\n             data/full_repos/permissive/206437232/TP1-ALU-2019/Verilog,data/full_repos/permissive/206437232/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP1-ALU-2019/Verilog/Top_ALU.v:60: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'i_sw\' generates 8 bits.\n                                                                                      : ... In instance Top_ALU\n            i_operation   <= i_sw;\n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module Top_ALU

    #(parameter 
    NB_SW = 8,
    NB_OP = 6, 
    NB_LED = 8, 
    NB_BUT = 3
     )

    (
    input                   i_clk,
    input   [NB_SW-1:0]     i_sw,
    input   [NB_BUT-1:0]    i_btn,
    output  [NB_LED-1:0]    o_led
    );
   
    reg signed [NB_SW-1:0]     i_data_a;
    reg signed [NB_SW-1:0]     i_data_b;
    reg        [NB_OP-1:0]     i_operation;
    wire       [NB_LED-1:0]    o_leds;
    
    ALU
    u_ALU(.i_data_a       (i_data_a),
          .i_data_b       (i_data_b),
          .i_operation    (i_operation),
          .o_result       (o_leds)
    );
    
    always @(posedge i_clk) 
    begin
        if(i_btn[0] == 1'b1)
            i_data_a      <= i_sw;
            
        else if(i_btn[1] == 1'b1)
            i_data_b      <= i_sw;
            
        else if(i_btn[2] == 1'b1)
            i_operation   <= i_sw;
            
        else begin
            i_data_a    <= i_data_a;
            i_data_b    <= i_data_b;
            i_operation <= i_operation;
        end
    end
    
    assign o_led = o_leds;
    
endmodule
module Top_ALU

    #(parameter 
    NB_SW = 8,
    NB_OP = 6, 
    NB_LED = 8, 
    NB_BUT = 3
     )

    (
    input                   i_clk,
    input   [NB_SW-1:0]     i_sw,
    input   [NB_BUT-1:0]    i_btn,
    output  [NB_LED-1:0]    o_led
    );

   
    reg signed [NB_SW-1:0]     i_data_a;
    reg signed [NB_SW-1:0]     i_data_b;
    reg        [NB_OP-1:0]     i_operation;
    wire       [NB_LED-1:0]    o_leds;
    
    ALU
    u_ALU(.i_data_a       (i_data_a),
          .i_data_b       (i_data_b),
          .i_operation    (i_operation),
          .o_result       (o_leds)
    );
    
    always @(posedge i_clk) 
    begin
        if(i_btn[0] == 1'b1)
            i_data_a      <= i_sw;
            
        else if(i_btn[1] == 1'b1)
            i_data_b      <= i_sw;
            
        else if(i_btn[2] == 1'b1)
            i_operation   <= i_sw;
            
        else begin
            i_data_a    <= i_data_a;
            i_data_b    <= i_data_b;
            i_operation <= i_operation;
        end
    end
    
    assign o_led = o_leds;
    
endmodule