data/full_repos/permissive/157424577/cache_controller.v
data/verilator_xmls/c7a84e19-d37a-483f-88f3-8cd8feed73a2.xml
module cache_controller(clk,hit,read);
    input clk;
    input hit;
    
    output reg read;

    always@(posedge clk)
    begin
        if(hit == 1) begin
            read = 1;
        end
        else begin
            read = 0;
        end
    end
endmodule
module cache_controller(clk,hit,read);

    input clk;
    input hit;
    
    output reg read;

    always@(posedge clk)
    begin
        if(hit == 1) begin
            read = 1;
        end
        else begin
            read = 0;
        end
    end
endmodule