data/full_repos/permissive/127511545/src/WriteBackForwardUnit.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/WriteBackForwardUnit.v:44: Signal definition not found, creating implicitly: \'OrAddress\'\n                                                                                     : ... Suggested alternative: \'XorAddress\'\n or #(50) o0(OrAddress, XorAddress[4], XorAddress[3], XorAddress[2], XorAddress[1], XorAddress[0]);\n             ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/WriteBackForwardUnit.v:17: Signal definition not found, creating implicitly: \'OrOutput1\'\n or #(50) o0(OrOutput1, WriteRegister[4], WriteRegister[3], WriteRegister[2], WriteRegister[1], WriteRegister[0]);\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/127511545/src/WriteBackForwardUnit.v:24: Cannot find file containing module: \'MUX2x32to32\'\n MUX2x32to32 mux0(ReadData1Output, ReadData1, WriteData, ReadSourceRs);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/MUX2x32to32\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/MUX2x32to32.v\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/MUX2x32to32.sv\n             MUX2x32to32\n             MUX2x32to32.v\n             MUX2x32to32.sv\n             obj_dir/MUX2x32to32\n             obj_dir/MUX2x32to32.v\n             obj_dir/MUX2x32to32.sv\n%Error: data/full_repos/permissive/127511545/src/WriteBackForwardUnit.v:25: Cannot find file containing module: \'MUX2x32to32\'\n MUX2x32to32 mux1(ReadData2Output, ReadData2, WriteData, ReadSourceRt);\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module CompareAddress(Equal, Address1, Address2);

	output Equal;
	wire Equal;
	input[4:0] Address1, Address2;
	wire[4:0] Address1, Address2, XorAddress;

	xor #(50) x0(XorAddress[4], Address1[4], Address2[4]);
	xor #(50) x1(XorAddress[3], Address1[3], Address2[3]);
	xor #(50) x2(XorAddress[2], Address1[2], Address2[2]);
	xor #(50) x3(XorAddress[1], Address1[1], Address2[1]);
	xor #(50) x4(XorAddress[0], Address1[0], Address2[0]);
	or #(50) o0(OrAddress, XorAddress[4], XorAddress[3], XorAddress[2], XorAddress[1], XorAddress[0]);
	not #(50) inv0(Equal, OrAddress);

endmodule
module CompareAddress(Equal, Address1, Address2);


	output Equal;
	wire Equal;
	input[4:0] Address1, Address2;
	wire[4:0] Address1, Address2, XorAddress;

	xor #(50) x0(XorAddress[4], Address1[4], Address2[4]);
	xor #(50) x1(XorAddress[3], Address1[3], Address2[3]);
	xor #(50) x2(XorAddress[2], Address1[2], Address2[2]);
	xor #(50) x3(XorAddress[1], Address1[1], Address2[1]);
	xor #(50) x4(XorAddress[0], Address1[0], Address2[0]);
	or #(50) o0(OrAddress, XorAddress[4], XorAddress[3], XorAddress[2], XorAddress[1], XorAddress[0]);
	not #(50) inv0(Equal, OrAddress);

endmodule