data/full_repos/permissive/168753118/rtl/modules/PIPELINE_CONTROL.v
data/verilator_xmls/cb0d658d-78a7-4345-9b9d-293bbc5f1ca3.xml
module PIPELINE_CONTROL (
  input pipeline_clock_in,
  input pipeline_reset_in,


  input pipeline_offset_flag_in,
  input pipeline_target_flag_in,
  input pipeline_prediction_flag_in,

  output pipeline_ins_mem_valid_out,
  input pipeline_ins_mem_ready_in,

  output pipeline_pc_if_set_out,
  output pipeline_if_dec_set_out
);


endmodule
module PIPELINE_CONTROL (
  input pipeline_clock_in,
  input pipeline_reset_in,


  input pipeline_offset_flag_in,
  input pipeline_target_flag_in,
  input pipeline_prediction_flag_in,

  output pipeline_ins_mem_valid_out,
  input pipeline_ins_mem_ready_in,

  output pipeline_pc_if_set_out,
  output pipeline_if_dec_set_out
);



endmodule