data/full_repos/permissive/143278/ivltests/pr1691599b.v
 line:33: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1691599b.v:25: Unsupported: Ignoring delay on this delayed statement.\n  initial #1\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1691599b.v:33: Unsupported: Ignoring delay on this delayed statement.\n   initial #10 $display("PASSED");\n           ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   parameter cnt = 4;

   genvar i;
   generate
      for (i = 0; i < cnt; i = i+1) begin : target
	 reg [1:0] val;
      end
   endgenerate

   initial begin
      target[0].val = 0;
      target[1].val = 1;
      target[2].val = 2;
      target[3].val = 3;
   end

   generate
      for (i = 0; i < cnt; i = i+1) begin : sink
	 wire [1:0] val = target[i].val;

	 initial #1
	   if (val !== i) begin
	      $display("FAILED: sink[%0d].val = %b", i, val);
	      $finish;
	   end
      end
   endgenerate

   initial #10 $display("PASSED");

endmodule
module main;


   parameter cnt = 4;

   genvar i;
   generate
      for (i = 0; i < cnt; i = i+1) begin : target
	 reg [1:0] val;
      end
   endgenerate

   initial begin
      target[0].val = 0;
      target[1].val = 1;
      target[2].val = 2;
      target[3].val = 3;
   end

   generate
      for (i = 0; i < cnt; i = i+1) begin : sink
	 wire [1:0] val = target[i].val;

	 initial #1
	   if (val !== i) begin
	      $display("FAILED: sink[%0d].val = %b", i, val);
	      $finish;
	   end
      end
   endgenerate

   initial #10 $display("PASSED");

endmodule