data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/syzygy-brain-dac.v
1: b"%Error: data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/syzygy-brain-dac.v:96: Cannot find file containing module: 'syzygy_dac_top'\nsyzygy_dac_top dac_top(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120851390/pod-dac-ad9116/hdl,data/full_repos/permissive/120851390/syzygy_dac_top\n             data/full_repos/permissive/120851390/pod-dac-ad9116/hdl,data/full_repos/permissive/120851390/syzygy_dac_top.v\n             data/full_repos/permissive/120851390/pod-dac-ad9116/hdl,data/full_repos/permissive/120851390/syzygy_dac_top.sv\n             syzygy_dac_top\n             syzygy_dac_top.v\n             syzygy_dac_top.sv\n             obj_dir/syzygy_dac_top\n             obj_dir/syzygy_dac_top.v\n             obj_dir/syzygy_dac_top.sv\n%Error: data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/syzygy-brain-dac.v:115: Cannot find file containing module: 'design_1_wrapper'\ndesign_1_wrapper design_1_i\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module syzygy_brain_dac (
	inout  wire [14:0] DDR_addr,
	inout  wire  [2:0] DDR_ba,
	inout  wire        DDR_cas_n,
    inout  wire        DDR_ck_n,
    inout  wire        DDR_ck_p,
    inout  wire        DDR_cke,
    inout  wire        DDR_cs_n,
    inout  wire  [3:0] DDR_dm,
    inout  wire [31:0] DDR_dq,
    inout  wire  [3:0] DDR_dqs_n,
    inout  wire  [3:0] DDR_dqs_p,
    inout  wire        DDR_odt,
    inout  wire        DDR_ras_n,
    inout  wire        DDR_reset_n,
    inout  wire        DDR_we_n,
    inout  wire        FIXED_IO_ddr_vrn,
    inout  wire        FIXED_IO_ddr_vrp,
    inout  wire [53:0] FIXED_IO_mio,
    inout  wire        FIXED_IO_ps_clk,
    inout  wire        FIXED_IO_ps_porb,
    inout  wire        FIXED_IO_ps_srstb,
    

    output wire [11:0] dac_data,
    output wire        dac_clk,
    output wire        dac_reset_pinmd,
    output wire        dac_sclk,
    inout  wire        dac_sdio,
    output wire        dac_cs_n,
    
    output wire        dac_opamp_en,
	
	output wire [7:0]  led,
	input  wire [1:0]  button
	);

wire        clk;
wire        sw_reset;
wire [31:0] gpio_2;

reg  [31:0] count;

wire [31:0] dds_addr;
wire [31:0] dds_data;
wire [15:0] dds_rate;
wire [15:0] dac_fsadj;

assign led = count[31:24];

assign sw_reset = gpio_2[0];

assign dac_opamp_en = 1'b1;

always @(posedge clk) begin
	count <= count + 1'b1;
end

syzygy_dac_top dac_top(
	.clk         (clk),
	.reset_async ((~button[0]) || sw_reset),
	

	.dds_addr (dds_addr),
	.dds_data (dds_data),
	.dds_rate (dds_rate),
	.dac_fsadj (dac_fsadj),
	

	.dac_data (dac_data),
	.dac_clk (dac_clk),
	.dac_reset_pinmd (dac_reset_pinmd),
	.dac_sclk (dac_sclk),
	.dac_sdio (dac_sdio),
	.dac_cs_n (dac_cs_n)
	);

design_1_wrapper design_1_i
       (.DDR_addr(DDR_addr),
        .DDR_ba(DDR_ba),
        .DDR_cas_n(DDR_cas_n),
        .DDR_ck_n(DDR_ck_n),
        .DDR_ck_p(DDR_ck_p),
        .DDR_cke(DDR_cke),
        .DDR_cs_n(DDR_cs_n),
        .DDR_dm(DDR_dm),
        .DDR_dq(DDR_dq),
        .DDR_dqs_n(DDR_dqs_n),
        .DDR_dqs_p(DDR_dqs_p),
        .DDR_odt(DDR_odt),
        .DDR_ras_n(DDR_ras_n),
        .DDR_reset_n(DDR_reset_n),
        .DDR_we_n(DDR_we_n),
        .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
        .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
        .FIXED_IO_mio(FIXED_IO_mio),
        .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
        .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
        .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
        .BRAM_PORTB_0_addr (dds_addr),
        .BRAM_PORTB_0_clk  (clk),
        .BRAM_PORTB_0_din  (),
        .BRAM_PORTB_0_dout (dds_data),
        .BRAM_PORTB_0_en   (1'b1),
        .BRAM_PORTB_0_rst  (1'b0),
        .BRAM_PORTB_0_we   (1'b0),
        .gpio_rtl_0_tri_o(dds_rate),
        .gpio_rtl_1_tri_o(dac_fsadj),
        .gpio_rtl_2_tri_o(gpio_2),
        .clk_out (clk));

endmodule
module syzygy_brain_dac (
	inout  wire [14:0] DDR_addr,
	inout  wire  [2:0] DDR_ba,
	inout  wire        DDR_cas_n,
    inout  wire        DDR_ck_n,
    inout  wire        DDR_ck_p,
    inout  wire        DDR_cke,
    inout  wire        DDR_cs_n,
    inout  wire  [3:0] DDR_dm,
    inout  wire [31:0] DDR_dq,
    inout  wire  [3:0] DDR_dqs_n,
    inout  wire  [3:0] DDR_dqs_p,
    inout  wire        DDR_odt,
    inout  wire        DDR_ras_n,
    inout  wire        DDR_reset_n,
    inout  wire        DDR_we_n,
    inout  wire        FIXED_IO_ddr_vrn,
    inout  wire        FIXED_IO_ddr_vrp,
    inout  wire [53:0] FIXED_IO_mio,
    inout  wire        FIXED_IO_ps_clk,
    inout  wire        FIXED_IO_ps_porb,
    inout  wire        FIXED_IO_ps_srstb,
    

    output wire [11:0] dac_data,
    output wire        dac_clk,
    output wire        dac_reset_pinmd,
    output wire        dac_sclk,
    inout  wire        dac_sdio,
    output wire        dac_cs_n,
    
    output wire        dac_opamp_en,
	
	output wire [7:0]  led,
	input  wire [1:0]  button
	);


wire        clk;
wire        sw_reset;
wire [31:0] gpio_2;

reg  [31:0] count;

wire [31:0] dds_addr;
wire [31:0] dds_data;
wire [15:0] dds_rate;
wire [15:0] dac_fsadj;

assign led = count[31:24];

assign sw_reset = gpio_2[0];

assign dac_opamp_en = 1'b1;

always @(posedge clk) begin
	count <= count + 1'b1;
end

syzygy_dac_top dac_top(
	.clk         (clk),
	.reset_async ((~button[0]) || sw_reset),
	

	.dds_addr (dds_addr),
	.dds_data (dds_data),
	.dds_rate (dds_rate),
	.dac_fsadj (dac_fsadj),
	

	.dac_data (dac_data),
	.dac_clk (dac_clk),
	.dac_reset_pinmd (dac_reset_pinmd),
	.dac_sclk (dac_sclk),
	.dac_sdio (dac_sdio),
	.dac_cs_n (dac_cs_n)
	);

design_1_wrapper design_1_i
       (.DDR_addr(DDR_addr),
        .DDR_ba(DDR_ba),
        .DDR_cas_n(DDR_cas_n),
        .DDR_ck_n(DDR_ck_n),
        .DDR_ck_p(DDR_ck_p),
        .DDR_cke(DDR_cke),
        .DDR_cs_n(DDR_cs_n),
        .DDR_dm(DDR_dm),
        .DDR_dq(DDR_dq),
        .DDR_dqs_n(DDR_dqs_n),
        .DDR_dqs_p(DDR_dqs_p),
        .DDR_odt(DDR_odt),
        .DDR_ras_n(DDR_ras_n),
        .DDR_reset_n(DDR_reset_n),
        .DDR_we_n(DDR_we_n),
        .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
        .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
        .FIXED_IO_mio(FIXED_IO_mio),
        .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
        .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
        .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
        .BRAM_PORTB_0_addr (dds_addr),
        .BRAM_PORTB_0_clk  (clk),
        .BRAM_PORTB_0_din  (),
        .BRAM_PORTB_0_dout (dds_data),
        .BRAM_PORTB_0_en   (1'b1),
        .BRAM_PORTB_0_rst  (1'b0),
        .BRAM_PORTB_0_we   (1'b0),
        .gpio_rtl_0_tri_o(dds_rate),
        .gpio_rtl_1_tri_o(dac_fsadj),
        .gpio_rtl_2_tri_o(gpio_2),
        .clk_out (clk));

endmodule