data/full_repos/permissive/147690299/lab/13_comb_mux_Nbit/rtl/lab_top.sv
 line:25: before: "["
1: b"%Error: data/full_repos/permissive/147690299/lab/13_comb_mux_Nbit/rtl/lab_top.sv:18: Cannot find file containing module: 'b2_mux_3_1_case_full'\n b2_mux_3_1_case_full         b2_mux_3_1_case_full    (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata0));\n ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147690299/lab/13_comb_mux_Nbit/rtl,data/full_repos/permissive/147690299/b2_mux_3_1_case_full\n             data/full_repos/permissive/147690299/lab/13_comb_mux_Nbit/rtl,data/full_repos/permissive/147690299/b2_mux_3_1_case_full.v\n             data/full_repos/permissive/147690299/lab/13_comb_mux_Nbit/rtl,data/full_repos/permissive/147690299/b2_mux_3_1_case_full.sv\n             b2_mux_3_1_case_full\n             b2_mux_3_1_case_full.v\n             b2_mux_3_1_case_full.sv\n             obj_dir/b2_mux_3_1_case_full\n             obj_dir/b2_mux_3_1_case_full.v\n             obj_dir/b2_mux_3_1_case_full.sv\n%Error: data/full_repos/permissive/147690299/lab/13_comb_mux_Nbit/rtl/lab_top.sv:19: Cannot find file containing module: 'b2_mux_3_1_case'\n b2_mux_3_1_case              b2_mux_3_1_case         (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata1));\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147690299/lab/13_comb_mux_Nbit/rtl/lab_top.sv:20: Cannot find file containing module: 'b2_mux_3_1_case_default'\n b2_mux_3_1_case_default      b2_mux_3_1_case_default (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata2));\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147690299/lab/13_comb_mux_Nbit/rtl/lab_top.sv:21: Cannot find file containing module: 'b2_mux_3_1_casez'\n    b2_mux_3_1_casez        #(2) b2_mux_3_1_casez        (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata3));\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147690299/lab/13_comb_mux_Nbit/rtl/lab_top.sv:29: Cannot find file containing module: 'bN_mux_N_1'\n    bN_mux_N_1\n    ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module lab_top
(
    input  [1:0] idata0,
    input  [1:0] idata1,
    input  [1:0] idata2,
    input  [1:0] sel,
    output [1:0] odata0,
    output [1:0] odata1,
    output [1:0] odata2,
    output [1:0] odata3, 
    output [1:0] odata4 
);

	b2_mux_3_1_case_full         b2_mux_3_1_case_full    (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata0));
	b2_mux_3_1_case              b2_mux_3_1_case         (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata1));
	b2_mux_3_1_case_default      b2_mux_3_1_case_default (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata2));
    b2_mux_3_1_casez        #(2) b2_mux_3_1_casez        (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata3));

`ifdef ENABLE_SV_CODE

    wire [3:0][1:0] input_data;

    assign input_data = { idata2, idata2, idata1, idata0 };

    bN_mux_N_1
    #(
        .DATA_WIDTH ( 2 ),
        .ADDR_WIDTH ( 2 )
    )
    bN_mux_N_1
    (
        .d   ( input_data ),
        .sel ( sel        ),
        .y   ( odata4     )
    );

`else
    assign odata4 = 2'b0;
`endif
	
endmodule
module lab_top
(
    input  [1:0] idata0,
    input  [1:0] idata1,
    input  [1:0] idata2,
    input  [1:0] sel,
    output [1:0] odata0,
    output [1:0] odata1,
    output [1:0] odata2,
    output [1:0] odata3, 
    output [1:0] odata4 
);


	b2_mux_3_1_case_full         b2_mux_3_1_case_full    (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata0));
	b2_mux_3_1_case              b2_mux_3_1_case         (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata1));
	b2_mux_3_1_case_default      b2_mux_3_1_case_default (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata2));
    b2_mux_3_1_casez        #(2) b2_mux_3_1_casez        (.d0(idata0),.d1(idata1),.d2(idata2),.sel(sel),.y(odata3));

`ifdef ENABLE_SV_CODE

    wire [3:0][1:0] input_data;

    assign input_data = { idata2, idata2, idata1, idata0 };

    bN_mux_N_1
    #(
        .DATA_WIDTH ( 2 ),
        .ADDR_WIDTH ( 2 )
    )
    bN_mux_N_1
    (
        .d   ( input_data ),
        .sel ( sel        ),
        .y   ( odata4     )
    );

`else
    assign odata4 = 2'b0;
`endif
	
endmodule