data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v
 line:39: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n      forever #4 clk = ~clk;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:40: syntax error, unexpected \'@\'\n            @(negedge clk)\n            ^\n%Error: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:41: Unsupported or unknown PLI call: $urandom\n              data_in = $urandom%2;\n                        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n         #10 rst_n = 1\'b0;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n         #10 rst_n = 1\'b1;\n         ^\n%Error: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:59: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars();\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:61: Unsupported or unknown PLI call: $monitor\n      $monitor("@time=%0t\\t data_out=0x%h\\t",$time,data_out);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n         #50 push;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/06_shift_reg/simulation/shift_reg_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n      #200 $finish;\n      ^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module shift_reg_tb;

   localparam WIDTH=8;
   
   reg        clk;
   reg        rst_n;
   reg        shift_en;
   reg        data_in;
   wire [7:0] data_out;
   wire       serial_out;
      
   
   shift_reg #(.WIDTH(WIDTH)) shft
   (
      .data_out   ( data_out   ),
      .serial_out ( serial_out ),

      .clk        ( clk        ),
      .rst_n      ( rst_n      ),
      .data_in    ( data_in    ),
      .shift_en   ( shift_en   )
   );


   initial begin
      clk = 0;
      forever #4 clk = ~clk;
   end


   task push;
      begin
         $display("########## Shift enable active ##########");
         shift_en  = 1'b1;
         repeat(9)begin
            @(negedge clk)
              data_in = $urandom%2;
         end
         shift_en  = 1'b0;
         $display("########## Shift enable disable ##########\n");
      end
   endtask


   task async_rst;
      begin
         $display("########## RESET start! ##########");
         #10 rst_n = 1'b0;
         #10 rst_n = 1'b1;
         $display("########## RESET finish!\n ##########");
      end
   endtask
   
   initial begin
      $dumpvars();
      $display("#################### Starting simulation ####################");
      $monitor("@time=%0t\t data_out=0x%h\t",$time,data_out);
      
      shift_en  = 1'b0;
      rst_n     = 1'b1;
      data_in   = 1'b0;
      

      async_rst();
      

      repeat(10) begin
         #50 push;
      end      
      #200 $finish;
   end
   
endmodule
module shift_reg_tb;


   localparam WIDTH=8;
   
   reg        clk;
   reg        rst_n;
   reg        shift_en;
   reg        data_in;
   wire [7:0] data_out;
   wire       serial_out;
      
   
   shift_reg #(.WIDTH(WIDTH)) shft
   (
      .data_out   ( data_out   ),
      .serial_out ( serial_out ),

      .clk        ( clk        ),
      .rst_n      ( rst_n      ),
      .data_in    ( data_in    ),
      .shift_en   ( shift_en   )
   );


   initial begin
      clk = 0;
      forever #4 clk = ~clk;
   end


   task push;
      begin
         $display("########## Shift enable active ##########");
         shift_en  = 1'b1;
         repeat(9)begin
            @(negedge clk)
              data_in = $urandom%2;
         end
         shift_en  = 1'b0;
         $display("########## Shift enable disable ##########\n");
      end
   endtask


   task async_rst;
      begin
         $display("########## RESET start! ##########");
         #10 rst_n = 1'b0;
         #10 rst_n = 1'b1;
         $display("########## RESET finish!\n ##########");
      end
   endtask
   
   initial begin
      $dumpvars();
      $display("#################### Starting simulation ####################");
      $monitor("@time=%0t\t data_out=0x%h\t",$time,data_out);
      
      shift_en  = 1'b0;
      rst_n     = 1'b1;
      data_in   = 1'b0;
      

      async_rst();
      

      repeat(10) begin
         #50 push;
      end      
      #200 $finish;
   end
   
endmodule