data/full_repos/permissive/166023910/adders_8/source_v/add8_239.v
data/verilator_xmls/de9fe820-caf8-4779-8746-4ac3babc5692.xml
module PDKGENNAND3X1(input A, input B, input C, output Y );
     assign Y = ~((A & B) & C);
endmodule
module PDKGENNAND3X1(input A, input B, input C, output Y );

     assign Y = ~((A & B) & C);
endmodule