data/full_repos/permissive/143278/ivltests/analog2.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/143278/ivltests/analog2.v:1: syntax error, unexpected IDENTIFIER\nnature Voltage;\n^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/analog2.v:24: syntax error, unexpected \'<\', expecting \',\' or \';\'\n   analog V(out) <+ transition(value, 0, 4);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/analog2.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #10 if (V(out) != value) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/analog2.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #2 if (abs(V(out) - value/2) > 1e-6) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/analog2.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #2 if (V(out) != value) begin\n      ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module main;

   real value;
   voltage in, out;
   analog V(out) <+ transition(value, 0, 4);

   initial begin
      value = 0.0;
      #10 if (V(out) != value) begin
	 $display("FAILED -- value=%g, res=%g", value, V(out));
	 $finish;
      end



      value = 2.0;

      #2 if (abs(V(out) - value/2) > 1e-6) begin
	 $display("FAILED -- value=%g, value/2=%g, res=%f", value, value/2, V(out));
	 $finish;
      end



      #2 if (V(out) != value) begin
	 $display("FAILED -- value=%g, res=%f", value, V(out));
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   real value;
   voltage in, out;
   analog V(out) <+ transition(value, 0, 4);

   initial begin
      value = 0.0;
      #10 if (V(out) != value) begin
	 $display("FAILED -- value=%g, res=%g", value, V(out));
	 $finish;
      end



      value = 2.0;

      #2 if (abs(V(out) - value/2) > 1e-6) begin
	 $display("FAILED -- value=%g, value/2=%g, res=%f", value, value/2, V(out));
	 $finish;
      end



      #2 if (V(out) != value) begin
	 $display("FAILED -- value=%g, res=%f", value, V(out));
	 $finish;
      end

      $display("PASSED");
   end

endmodule