data/full_repos/permissive/123627914/src/main/modules/address-mux2/addressMux2.v
data/verilator_xmls/fc4bc7d7-b2b0-43ad-86ec-2b6bf4dc3321.xml
module addressMux2(
IADDR1  ,
IADDR2  ,
SELECT  ,
OADDR
);

parameter ADDR_WIDTH = 11;


input   [ADDR_WIDTH-1:0]    IADDR1;
input   [ADDR_WIDTH-1:0] 	IADDR2;
input                       SELECT;


output wire [ADDR_WIDTH-1:0]    OADDR;




assign OADDR = (SELECT) ? IADDR2 : IADDR1;

endmodule
module addressMux2(
IADDR1  ,
IADDR2  ,
SELECT  ,
OADDR
);


parameter ADDR_WIDTH = 11;


input   [ADDR_WIDTH-1:0]    IADDR1;
input   [ADDR_WIDTH-1:0] 	IADDR2;
input                       SELECT;


output wire [ADDR_WIDTH-1:0]    OADDR;




assign OADDR = (SELECT) ? IADDR2 : IADDR1;

endmodule