data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v
1: b'%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:49: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:53: Define or directive not defined: \'`E203_PC_SIZE\'\n input  [`E203_PC_SIZE-1:0] pc_rtvec,  \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:58: Define or directive not defined: \'`E203_INSTR_SIZE\'\n output [`E203_INSTR_SIZE-1:0] ifu_o_ir, \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:59: Define or directive not defined: \'`E203_PC_SIZE\'\n output [`E203_PC_SIZE-1:0] ifu_o_pc,    \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:62: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:63: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:71: Define or directive not defined: \'`E203_PC_SIZE\'\n input   [`E203_PC_SIZE-1:0] pipe_flush_add_op1,  \n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:72: Define or directive not defined: \'`E203_PC_SIZE\'\n input   [`E203_PC_SIZE-1:0] pipe_flush_add_op2,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:87: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0] rf2ifu_x1,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:88: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0] rf2ifu_rs1,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:91: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n input  [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:109: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0]   ifu_req_pc; \n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu.v:116: Define or directive not defined: \'`E203_INSTR_SIZE\'\n wire [`E203_INSTR_SIZE-1:0] ifu_rsp_instr; \n       ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module e203_ifu(

	input  [`E203_PC_SIZE-1:0] pc_rtvec,  
	



	output [`E203_INSTR_SIZE-1:0] ifu_o_ir,
	output [`E203_PC_SIZE-1:0] ifu_o_pc,
	output ifu_o_pc_vld,

	output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
	output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
	output ifu_o_prdt_taken,
	output ifu_o_muldiv_b2b,               
	output ifu_o_valid,
	input  ifu_o_ready,


	input   pipe_flush_req,
	input   [`E203_PC_SIZE-1:0] pipe_flush_add_op1,  
	input   [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
	`ifdef E203_TIMING_BOOST
	input   [`E203_PC_SIZE-1:0] pipe_flush_pc,  
	`endif

			





	input  ifu_halt_req,
	output ifu_halt_ack,

	input  oitf_empty,
	input  [`E203_XLEN-1:0] rf2ifu_x1,
	input  [`E203_XLEN-1:0] rf2ifu_rs1,
	input  dec2ifu_rden,
	input  dec2ifu_rs1en,
	input  [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
	input  dec2ifu_mulhsu,
	input  dec2ifu_div   ,
	input  dec2ifu_rem   ,
	input  dec2ifu_divu  ,
	input  dec2ifu_remu  ,

	input  clk,
	input  rst_n
	);





	
	wire ifu_req_valid; 
	wire ifu_req_ready; 
	wire [`E203_PC_SIZE-1:0]   ifu_req_pc; 



	wire ifu_rsp_valid; 
	wire ifu_rsp_ready; 

	wire [`E203_INSTR_SIZE-1:0] ifu_rsp_instr; 





(* DONT_TOUCH = "TRUE" *)
	e203_ifu_ifetch u_e203_ifu_ifetch(

		.pc_rtvec      (pc_rtvec),  
.ifu_req_valid (ifu_req_valid),
.ifu_req_ready (ifu_req_ready),
.ifu_req_pc    (ifu_req_pc   ),

.ifu_rsp_valid (ifu_rsp_valid),
.ifu_rsp_ready (ifu_rsp_ready),
.ifu_rsp_instr (ifu_rsp_instr),


		.ifu_o_ir      (ifu_o_ir     ),
		.ifu_o_pc      (ifu_o_pc     ),
		.ifu_o_pc_vld  (ifu_o_pc_vld ),
		.ifu_o_rs1idx  (ifu_o_rs1idx),
		.ifu_o_rs2idx  (ifu_o_rs2idx),
		.ifu_o_prdt_taken(ifu_o_prdt_taken),
		.ifu_o_muldiv_b2b(ifu_o_muldiv_b2b),
		.ifu_o_valid   (ifu_o_valid  ),
		.ifu_o_ready   (ifu_o_ready  ),

		.pipe_flush_req     (pipe_flush_req    ),
		.pipe_flush_add_op1 (pipe_flush_add_op1),     
	`ifdef E203_TIMING_BOOST
		.pipe_flush_pc      (pipe_flush_pc),  
	`endif
		.pipe_flush_add_op2 (pipe_flush_add_op2), 
		.ifu_halt_req  (ifu_halt_req ),
		.ifu_halt_ack  (ifu_halt_ack ),

		.oitf_empty    (oitf_empty   ),
		.rf2ifu_x1     (rf2ifu_x1    ),
		.rf2ifu_rs1    (rf2ifu_rs1   ),
		.dec2ifu_rden  (dec2ifu_rden ),
		.dec2ifu_rs1en (dec2ifu_rs1en),
		.dec2ifu_rdidx (dec2ifu_rdidx),
		.dec2ifu_mulhsu(dec2ifu_mulhsu),
		.dec2ifu_div   (dec2ifu_div   ),
		.dec2ifu_rem   (dec2ifu_rem   ),
		.dec2ifu_divu  (dec2ifu_divu  ),
		.dec2ifu_remu  (dec2ifu_remu  ),

		.clk           (clk          ),
		.rst_n         (rst_n        ) 
	);


(* DONT_TOUCH = "TRUE" *)
	e203_ifu_ift2itcm u_e203_ifu_ift2itcm (
		.ifu_req_valid (ifu_req_valid),
		.ifu_req_ready (ifu_req_ready),
		.ifu_req_pc    (ifu_req_pc   ),

		.ifu_rsp_valid (ifu_rsp_valid),
		.ifu_rsp_ready (ifu_rsp_ready),
		.ifu_rsp_instr (ifu_rsp_instr),


		.clk           (clk          ),
		.rst_n         (rst_n        ) 
	);

	
endmodule
module e203_ifu(

	input  [`E203_PC_SIZE-1:0] pc_rtvec,  
	



	output [`E203_INSTR_SIZE-1:0] ifu_o_ir,
	output [`E203_PC_SIZE-1:0] ifu_o_pc,
	output ifu_o_pc_vld,

	output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
	output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
	output ifu_o_prdt_taken,
	output ifu_o_muldiv_b2b,               
	output ifu_o_valid,
	input  ifu_o_ready,


	input   pipe_flush_req,
	input   [`E203_PC_SIZE-1:0] pipe_flush_add_op1,  
	input   [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
	`ifdef E203_TIMING_BOOST
	input   [`E203_PC_SIZE-1:0] pipe_flush_pc,  
	`endif

			





	input  ifu_halt_req,
	output ifu_halt_ack,

	input  oitf_empty,
	input  [`E203_XLEN-1:0] rf2ifu_x1,
	input  [`E203_XLEN-1:0] rf2ifu_rs1,
	input  dec2ifu_rden,
	input  dec2ifu_rs1en,
	input  [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
	input  dec2ifu_mulhsu,
	input  dec2ifu_div   ,
	input  dec2ifu_rem   ,
	input  dec2ifu_divu  ,
	input  dec2ifu_remu  ,

	input  clk,
	input  rst_n
	);






	
	wire ifu_req_valid; 
	wire ifu_req_ready; 
	wire [`E203_PC_SIZE-1:0]   ifu_req_pc; 



	wire ifu_rsp_valid; 
	wire ifu_rsp_ready; 

	wire [`E203_INSTR_SIZE-1:0] ifu_rsp_instr; 





(* DONT_TOUCH = "TRUE" *)
	e203_ifu_ifetch u_e203_ifu_ifetch(

		.pc_rtvec      (pc_rtvec),  
.ifu_req_valid (ifu_req_valid),
.ifu_req_ready (ifu_req_ready),
.ifu_req_pc    (ifu_req_pc   ),

.ifu_rsp_valid (ifu_rsp_valid),
.ifu_rsp_ready (ifu_rsp_ready),
.ifu_rsp_instr (ifu_rsp_instr),


		.ifu_o_ir      (ifu_o_ir     ),
		.ifu_o_pc      (ifu_o_pc     ),
		.ifu_o_pc_vld  (ifu_o_pc_vld ),
		.ifu_o_rs1idx  (ifu_o_rs1idx),
		.ifu_o_rs2idx  (ifu_o_rs2idx),
		.ifu_o_prdt_taken(ifu_o_prdt_taken),
		.ifu_o_muldiv_b2b(ifu_o_muldiv_b2b),
		.ifu_o_valid   (ifu_o_valid  ),
		.ifu_o_ready   (ifu_o_ready  ),

		.pipe_flush_req     (pipe_flush_req    ),
		.pipe_flush_add_op1 (pipe_flush_add_op1),     
	`ifdef E203_TIMING_BOOST
		.pipe_flush_pc      (pipe_flush_pc),  
	`endif
		.pipe_flush_add_op2 (pipe_flush_add_op2), 
		.ifu_halt_req  (ifu_halt_req ),
		.ifu_halt_ack  (ifu_halt_ack ),

		.oitf_empty    (oitf_empty   ),
		.rf2ifu_x1     (rf2ifu_x1    ),
		.rf2ifu_rs1    (rf2ifu_rs1   ),
		.dec2ifu_rden  (dec2ifu_rden ),
		.dec2ifu_rs1en (dec2ifu_rs1en),
		.dec2ifu_rdidx (dec2ifu_rdidx),
		.dec2ifu_mulhsu(dec2ifu_mulhsu),
		.dec2ifu_div   (dec2ifu_div   ),
		.dec2ifu_rem   (dec2ifu_rem   ),
		.dec2ifu_divu  (dec2ifu_divu  ),
		.dec2ifu_remu  (dec2ifu_remu  ),

		.clk           (clk          ),
		.rst_n         (rst_n        ) 
	);


(* DONT_TOUCH = "TRUE" *)
	e203_ifu_ift2itcm u_e203_ifu_ift2itcm (
		.ifu_req_valid (ifu_req_valid),
		.ifu_req_ready (ifu_req_ready),
		.ifu_req_pc    (ifu_req_pc   ),

		.ifu_rsp_valid (ifu_rsp_valid),
		.ifu_rsp_ready (ifu_rsp_ready),
		.ifu_rsp_instr (ifu_rsp_instr),


		.clk           (clk          ),
		.rst_n         (rst_n        ) 
	);

	
endmodule