data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/tse_mac_loopback.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/tse_mac_loopback.v:65: Unsupported: Ignoring delay on this delayed statement.\n     #4 clk_tmp <= ~clk_tmp;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/tse_mac_loopback.v:70: Unsupported: Ignoring delay on this delayed statement.\n     #20 reconfig_clk_tmp <= ~reconfig_clk_tmp;\n     ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tse_mac_loopback (
  ref_clk,


  txp,
  rxp


);

  output ref_clk;


  input txp;
  output rxp;


  reg clk_tmp;
  initial
     clk_tmp <= 1'b0;
  always
     #4 clk_tmp <= ~clk_tmp;
  reg reconfig_clk_tmp;
  initial
     reconfig_clk_tmp <= 1'b0;
  always
     #20 reconfig_clk_tmp <= ~reconfig_clk_tmp;
  assign ref_clk = clk_tmp;


  assign rxp=txp;


endmodule
module tse_mac_loopback (
  ref_clk,


  txp,
  rxp


);


  output ref_clk;


  input txp;
  output rxp;


  reg clk_tmp;
  initial
     clk_tmp <= 1'b0;
  always
     #4 clk_tmp <= ~clk_tmp;
  reg reconfig_clk_tmp;
  initial
     reconfig_clk_tmp <= 1'b0;
  always
     #20 reconfig_clk_tmp <= ~reconfig_clk_tmp;
  assign ref_clk = clk_tmp;


  assign rxp=txp;


endmodule