data/full_repos/permissive/2084115/rtl/primitive/jelly2_ram32x1d.sv
 line:40 column:17: Illegal character "'"
data/verilator_xmls/6e3d969e-fedf-4f2b-8004-0aa830d7efdb.xml
module jelly2_ram32x1d
        #(
            parameter   INIT             = 32'd0,
            parameter   IS_WCLK_INVERTED = 1'b0,
            parameter   DEVICE           = "RTL"
        )
        (
            input   wire                wclk,
            input   wire                wen,
            input   wire    [4:0]       waddr,
            input   wire                wdin,
            output  reg                 wdout,
            
            input   wire    [4:0]       raddr,
            output  reg                 rdout
        );

`ifdef VERILATOR
    localparam  SIM = 1'b1;
`else
    localparam  SIM = 1'b0;
`endif

    generate
    if ( !SIM && (
            256'(DEVICE) == 256'("SPARTAN6") ||
            256'(DEVICE) == 256'("VIRTEX6") ||
            256'(DEVICE) == 256'("7SERIES") ||
            256'(DEVICE) == 256'("ULTRASCALE") ||
            256'(DEVICE) == 256'("ULTRASCALE_PLUS") ||
            256'(DEVICE) == 256'("ULTRASCALE_PLUS_ES1") ||
            256'(DEVICE) == 256'("ULTRASCALE_PLUS_ES2")) ) begin : xilinx_ram32x1d

        RAM32X1D
                #(
                    .INIT               (INIT),
                    .IS_WCLK_INVERTED   (IS_WCLK_INVERTED)
                )
            i_ram32x1d
                (
                    .WCLK               (wclk),
                    .WE                 (wen),
                    .A0                 (waddr[0]),
                    .A1                 (waddr[1]),
                    .A2                 (waddr[2]),
                    .A3                 (waddr[3]),
                    .A4                 (waddr[4]),
                    .D                  (wdin),
                    .SPO                (wdout),

                    .DPRA0              (raddr[0]),
                    .DPRA1              (raddr[1]),
                    .DPRA2              (raddr[2]),
                    .DPRA3              (raddr[3]),
                    .DPRA4              (raddr[4]),
                    .DPO                (rdout)
                );
    end
    else begin
        logic   [31:0]  mem = INIT;
        logic           clock;
        assign clock = IS_WCLK_INVERTED ? ~wclk : wclk;

        always_ff @(posedge clock) begin
            if ( wen ) begin
                mem[waddr] <= wdin;
            end
        end

        always_comb begin
            wdout = mem[waddr];
        end

        always_comb begin
            rdout = mem[raddr];
        end
    end
    endgenerate

endmodule
module jelly2_ram32x1d
        #(
            parameter   INIT             = 32'd0,
            parameter   IS_WCLK_INVERTED = 1'b0,
            parameter   DEVICE           = "RTL"
        )
        (
            input   wire                wclk,
            input   wire                wen,
            input   wire    [4:0]       waddr,
            input   wire                wdin,
            output  reg                 wdout,
            
            input   wire    [4:0]       raddr,
            output  reg                 rdout
        );


`ifdef VERILATOR
    localparam  SIM = 1'b1;
`else
    localparam  SIM = 1'b0;
`endif

    generate
    if ( !SIM && (
            256'(DEVICE) == 256'("SPARTAN6") ||
            256'(DEVICE) == 256'("VIRTEX6") ||
            256'(DEVICE) == 256'("7SERIES") ||
            256'(DEVICE) == 256'("ULTRASCALE") ||
            256'(DEVICE) == 256'("ULTRASCALE_PLUS") ||
            256'(DEVICE) == 256'("ULTRASCALE_PLUS_ES1") ||
            256'(DEVICE) == 256'("ULTRASCALE_PLUS_ES2")) ) begin : xilinx_ram32x1d

        RAM32X1D
                #(
                    .INIT               (INIT),
                    .IS_WCLK_INVERTED   (IS_WCLK_INVERTED)
                )
            i_ram32x1d
                (
                    .WCLK               (wclk),
                    .WE                 (wen),
                    .A0                 (waddr[0]),
                    .A1                 (waddr[1]),
                    .A2                 (waddr[2]),
                    .A3                 (waddr[3]),
                    .A4                 (waddr[4]),
                    .D                  (wdin),
                    .SPO                (wdout),

                    .DPRA0              (raddr[0]),
                    .DPRA1              (raddr[1]),
                    .DPRA2              (raddr[2]),
                    .DPRA3              (raddr[3]),
                    .DPRA4              (raddr[4]),
                    .DPO                (rdout)
                );
    end
    else begin
        logic   [31:0]  mem = INIT;
        logic           clock;
        assign clock = IS_WCLK_INVERTED ? ~wclk : wclk;

        always_ff @(posedge clock) begin
            if ( wen ) begin
                mem[waddr] <= wdin;
            end
        end

        always_comb begin
            wdout = mem[waddr];
        end

        always_comb begin
            rdout = mem[raddr];
        end
    end
    endgenerate

endmodule