data/full_repos/permissive/139213403/FPGA/blastit_demo_mcu.v
1: b"%Error: data/full_repos/permissive/139213403/FPGA/blastit_demo_mcu.v:56: Cannot find file containing module: 'controller'\n controller mcu(.clock_50_clk(CLOCK_50), .reset_reset_n(1), .warning_en_export(WARN));\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/controller\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/controller.v\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/controller.sv\n             controller\n             controller.v\n             controller.sv\n             obj_dir/controller\n             obj_dir/controller.v\n             obj_dir/controller.sv\n%Error: Exiting due to 1 error(s)\n"
module blastit_demo_mcu
(



	input wire CLOCK_50,




	input wire DAYLIGHT,
	



	input wire UART_RX,
	



	output wire[7:0] C_SSEG,
	



	output wire[15:0] C,
	



	output wire[9:0] D,
	



	output wire[9:0] G,
	



	output wire UART_TX,
	



	output wire[3:0] LED,
	



	output wire WARN
);


	controller mcu(.clock_50_clk(CLOCK_50), .reset_reset_n(1), .warning_en_export(WARN));

	
endmodule
module blastit_demo_mcu
(



	input wire CLOCK_50,




	input wire DAYLIGHT,
	



	input wire UART_RX,
	



	output wire[7:0] C_SSEG,
	



	output wire[15:0] C,
	



	output wire[9:0] D,
	



	output wire[9:0] G,
	



	output wire UART_TX,
	



	output wire[3:0] LED,
	



	output wire WARN
);



	controller mcu(.clock_50_clk(CLOCK_50), .reset_reset_n(1), .warning_en_export(WARN));

	
endmodule