data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:112: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbwstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?0 : {cmbwstate,ReloadWCnt,writeack} = 3'b010;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:112: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadWCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?0 : {cmbwstate,ReloadWCnt,writeack} = 3'b010;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:112: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'writeack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?0 : {cmbwstate,ReloadWCnt,writeack} = 3'b010;\n                                       ^~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:113: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbwstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?0 : {cmbwstate,ReloadWCnt,writeack} = 3'b110;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:113: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadWCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?0 : {cmbwstate,ReloadWCnt,writeack} = 3'b110;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:113: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'writeack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?0 : {cmbwstate,ReloadWCnt,writeack} = 3'b110;\n                                       ^~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:114: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbwstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?1 : {cmbwstate,ReloadWCnt,writeack} = 3'b010;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:114: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadWCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?1 : {cmbwstate,ReloadWCnt,writeack} = 3'b010;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:114: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'writeack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?1 : {cmbwstate,ReloadWCnt,writeack} = 3'b010;\n                                       ^~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:115: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbwstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?1 : {cmbwstate,ReloadWCnt,writeack} = 3'b011;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:115: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadWCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?1 : {cmbwstate,ReloadWCnt,writeack} = 3'b011;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:115: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'writeack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?1 : {cmbwstate,ReloadWCnt,writeack} = 3'b011;\n                                       ^~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:116: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbwstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?0? : {cmbwstate,ReloadWCnt,writeack} = 3'b100;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:116: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadWCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?0? : {cmbwstate,ReloadWCnt,writeack} = 3'b100;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:116: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'writeack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?0? : {cmbwstate,ReloadWCnt,writeack} = 3'b100;\n                                       ^~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:117: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbwstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?1? : {cmbwstate,ReloadWCnt,writeack} = 3'b001;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:117: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadWCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?1? : {cmbwstate,ReloadWCnt,writeack} = 3'b001;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:117: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'writeack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?1? : {cmbwstate,ReloadWCnt,writeack} = 3'b001;\n                                       ^~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:150: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbrstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?0 : {cmbrstate,ReloadRCnt,readack} = 3'b010;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:150: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadRCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?0 : {cmbrstate,ReloadRCnt,readack} = 3'b010;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:150: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'readack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?0 : {cmbrstate,ReloadRCnt,readack} = 3'b010;\n                                       ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:151: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbrstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?0 : {cmbrstate,ReloadRCnt,readack} = 3'b110;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:151: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadRCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?0 : {cmbrstate,ReloadRCnt,readack} = 3'b110;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:151: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'readack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?0 : {cmbrstate,ReloadRCnt,readack} = 3'b110;\n                                       ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:152: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbrstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?1 : {cmbrstate,ReloadRCnt,readack} = 3'b010;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:152: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadRCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?1 : {cmbrstate,ReloadRCnt,readack} = 3'b010;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:152: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'readack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b00?1 : {cmbrstate,ReloadRCnt,readack} = 3'b010;\n                                       ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:153: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbrstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?1 : {cmbrstate,ReloadRCnt,readack} = 3'b011;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:153: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadRCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?1 : {cmbrstate,ReloadRCnt,readack} = 3'b011;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:153: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'readack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b01?1 : {cmbrstate,ReloadRCnt,readack} = 3'b011;\n                                       ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:154: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbrstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?0? : {cmbrstate,ReloadRCnt,readack} = 3'b100;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:154: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadRCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?0? : {cmbrstate,ReloadRCnt,readack} = 3'b100;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:154: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'readack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?0? : {cmbrstate,ReloadRCnt,readack} = 3'b100;\n                                       ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:155: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cmbrstate'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?1? : {cmbrstate,ReloadRCnt,readack} = 3'b001;\n                  ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:155: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ReloadRCnt'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?1? : {cmbrstate,ReloadRCnt,readack} = 3'b001;\n                            ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/195227969/work/code/simcode/m_dyn_wishbonereg.v:155: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'readack'\n                                                                                                  : ... In instance m_dyn_wishbonereg\n       4'b1?1? : {cmbrstate,ReloadRCnt,readack} = 3'b001;\n                                       ^~~~~~~\n%Error: Exiting due to 36 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module m_dyn_wishbonereg
  # ( parameter INITVAL = 32'hdeadbabe,
      parameter CHECK_RULE_3_55 = 0
      )
   (
    input         CLK_I,
    input [31:0]  DAT_I,
    input         STB_I,
    input         WE_I,
    input [3:0]   SEL_I,
    input [5:0]   writelatency,
    input [5:0]   readlatency,
    output [31:0] DAT_O,
    output        ACK_O
    );
   
   wire [3:0]     ce;
   reg [31:0]     r;

   wire           readack,writeack;

   
   initial begin
      r = INITVAL;
   end
   
   assign ce[0] = SEL_I[0] & STB_I & WE_I;
   assign ce[1] = SEL_I[1] & STB_I & WE_I;
   assign ce[2] = SEL_I[2] & STB_I & WE_I;
   assign ce[3] = SEL_I[3] & STB_I & WE_I;
   
   always @(posedge CLK_I) begin
      if ( ce[0] ) r[ 7: 0] <= DAT_I[ 7: 0];
      if ( ce[1] ) r[15: 8] <= DAT_I[15: 8];
      if ( ce[2] ) r[23:16] <= DAT_I[23:16];
      if ( ce[3] ) r[31:24] <= DAT_I[31:24];
   end


   reg [5:0] Wcnt;
   wire      WLat0 = writelatency == 0;
   wire      WcntEq0 = Wcnt == 0;
   wire      writestrobe = STB_I & WE_I;
   reg       wstate;
   wire      cmbwstate,ReloadWCnt;
   
   always @(WLat0 or WcntEq0 or writestrobe or wstate)
     casez ( {wstate,writestrobe,WcntEq0,WLat0} )
       4'b00?0 : {cmbwstate,ReloadWCnt,writeack} = 3'b010;
       4'b01?0 : {cmbwstate,ReloadWCnt,writeack} = 3'b110;
       4'b00?1 : {cmbwstate,ReloadWCnt,writeack} = 3'b010;
       4'b01?1 : {cmbwstate,ReloadWCnt,writeack} = 3'b011;
       4'b1?0? : {cmbwstate,ReloadWCnt,writeack} = 3'b100;
       4'b1?1? : {cmbwstate,ReloadWCnt,writeack} = 3'b001;
     endcase

   always @(posedge CLK_I) 
     wstate <= cmbwstate;

   always @(posedge CLK_I) 
     if ( ReloadWCnt )
       Wcnt <= writelatency;
     else
       Wcnt <= Wcnt - 1;


   reg [5:0] Rcnt;
   wire      RLat0 = readlatency == 0;
   wire      RcntEq0 = Rcnt == 0;
   wire      readstrobe = STB_I & ~WE_I;
   reg       rstate;
   wire      cmbrstate,ReloadRCnt;
   
   always @(RLat0 or RcntEq0 or readstrobe or rstate)
     casez ( {rstate,readstrobe,RcntEq0,RLat0} )
       4'b00?0 : {cmbrstate,ReloadRCnt,readack} = 3'b010;
       4'b01?0 : {cmbrstate,ReloadRCnt,readack} = 3'b110;
       4'b00?1 : {cmbrstate,ReloadRCnt,readack} = 3'b010;
       4'b01?1 : {cmbrstate,ReloadRCnt,readack} = 3'b011;
       4'b1?0? : {cmbrstate,ReloadRCnt,readack} = 3'b100;
       4'b1?1? : {cmbrstate,ReloadRCnt,readack} = 3'b001;
     endcase

   always @(posedge CLK_I) 
     rstate <= cmbrstate;

   always @(posedge CLK_I) 
     if ( ReloadRCnt )
       Rcnt <= readlatency;
     else
       Rcnt <= Rcnt - 1;

   assign ACK_O = readack | writeack;
   assign DAT_O = ACK_O ? r : 32'hd0d0d0d0;
endmodule
module m_dyn_wishbonereg
  # ( parameter INITVAL = 32'hdeadbabe,
      parameter CHECK_RULE_3_55 = 0
      )
   (
    input         CLK_I,
    input [31:0]  DAT_I,
    input         STB_I,
    input         WE_I,
    input [3:0]   SEL_I,
    input [5:0]   writelatency,
    input [5:0]   readlatency,
    output [31:0] DAT_O,
    output        ACK_O
    );

   
   wire [3:0]     ce;
   reg [31:0]     r;

   wire           readack,writeack;

   
   initial begin
      r = INITVAL;
   end
   
   assign ce[0] = SEL_I[0] & STB_I & WE_I;
   assign ce[1] = SEL_I[1] & STB_I & WE_I;
   assign ce[2] = SEL_I[2] & STB_I & WE_I;
   assign ce[3] = SEL_I[3] & STB_I & WE_I;
   
   always @(posedge CLK_I) begin
      if ( ce[0] ) r[ 7: 0] <= DAT_I[ 7: 0];
      if ( ce[1] ) r[15: 8] <= DAT_I[15: 8];
      if ( ce[2] ) r[23:16] <= DAT_I[23:16];
      if ( ce[3] ) r[31:24] <= DAT_I[31:24];
   end


   reg [5:0] Wcnt;
   wire      WLat0 = writelatency == 0;
   wire      WcntEq0 = Wcnt == 0;
   wire      writestrobe = STB_I & WE_I;
   reg       wstate;
   wire      cmbwstate,ReloadWCnt;
   
   always @(WLat0 or WcntEq0 or writestrobe or wstate)
     casez ( {wstate,writestrobe,WcntEq0,WLat0} )
       4'b00?0 : {cmbwstate,ReloadWCnt,writeack} = 3'b010;
       4'b01?0 : {cmbwstate,ReloadWCnt,writeack} = 3'b110;
       4'b00?1 : {cmbwstate,ReloadWCnt,writeack} = 3'b010;
       4'b01?1 : {cmbwstate,ReloadWCnt,writeack} = 3'b011;
       4'b1?0? : {cmbwstate,ReloadWCnt,writeack} = 3'b100;
       4'b1?1? : {cmbwstate,ReloadWCnt,writeack} = 3'b001;
     endcase

   always @(posedge CLK_I) 
     wstate <= cmbwstate;

   always @(posedge CLK_I) 
     if ( ReloadWCnt )
       Wcnt <= writelatency;
     else
       Wcnt <= Wcnt - 1;


   reg [5:0] Rcnt;
   wire      RLat0 = readlatency == 0;
   wire      RcntEq0 = Rcnt == 0;
   wire      readstrobe = STB_I & ~WE_I;
   reg       rstate;
   wire      cmbrstate,ReloadRCnt;
   
   always @(RLat0 or RcntEq0 or readstrobe or rstate)
     casez ( {rstate,readstrobe,RcntEq0,RLat0} )
       4'b00?0 : {cmbrstate,ReloadRCnt,readack} = 3'b010;
       4'b01?0 : {cmbrstate,ReloadRCnt,readack} = 3'b110;
       4'b00?1 : {cmbrstate,ReloadRCnt,readack} = 3'b010;
       4'b01?1 : {cmbrstate,ReloadRCnt,readack} = 3'b011;
       4'b1?0? : {cmbrstate,ReloadRCnt,readack} = 3'b100;
       4'b1?1? : {cmbrstate,ReloadRCnt,readack} = 3'b001;
     endcase

   always @(posedge CLK_I) 
     rstate <= cmbrstate;

   always @(posedge CLK_I) 
     if ( ReloadRCnt )
       Rcnt <= readlatency;
     else
       Rcnt <= Rcnt - 1;

   assign ACK_O = readack | writeack;
   assign DAT_O = ACK_O ? r : 32'hd0d0d0d0;
endmodule