data/full_repos/permissive/179980995/Lab2/main.v
data/verilator_xmls/ffe682a8-a3d9-41a3-a9f9-e88c87fa4fb3.xml
module logic_unit(
input a,
input b,
input [1:0] s,
output reg h
);
always@(*) begin
case(s)
2'b00: h = a & b;
2'b01: h = a | b;
2'b10: h = a ^ b;
2'b11: h = ~(a ^ b);
endcase
end
endmodule
module logic_unit(
input a,
input b,
input [1:0] s,
output reg h
);

always@(*) begin
case(s)
2'b00: h = a & b;
2'b01: h = a | b;
2'b10: h = a ^ b;
2'b11: h = ~(a ^ b);
endcase
end
endmodule