data/full_repos/permissive/129127690/demux_4_16.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/129127690/demux_4_16.v:7: Cannot find file containing module: 'demux_3_8'\n  demux_3_8 #(bus_size) deco_1_1(select[2:0],stage_1_1,a,b,c,d,e,f,g,h);\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/demux_3_8\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/demux_3_8.v\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/demux_3_8.sv\n             demux_3_8\n             demux_3_8.v\n             demux_3_8.sv\n             obj_dir/demux_3_8\n             obj_dir/demux_3_8.v\n             obj_dir/demux_3_8.sv\n%Error: data/full_repos/permissive/129127690/demux_4_16.v:8: Cannot find file containing module: 'demux_3_8'\n  demux_3_8 #(bus_size) deco_1_2(select[2:0],stage_1_2,i,j,k,l, m,n,o,p);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/129127690/demux_4_16.v:9: Cannot find file containing module: 'deco_1_2'\n  deco_1_2 #(bus_size) deco_1(select[3],in,stage_1_1,stage_1_2);  \n  ^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module demux_4_16 #(parameter bus_size = 8)
	(input  [3:0] select,
		input  [bus_size-1:0] in,
		output  [bus_size-1:0] a,b,c,d, e,f,g,h, i,j,k,l, m,n,o,p);
		
		wire [bus_size-1:0] stage_1_1,stage1_2;
		demux_3_8 #(bus_size) deco_1_1(select[2:0],stage_1_1,a,b,c,d,e,f,g,h);
		demux_3_8 #(bus_size) deco_1_2(select[2:0],stage_1_2,i,j,k,l, m,n,o,p);
		deco_1_2 #(bus_size) deco_1(select[3],in,stage_1_1,stage_1_2);		
		
		
endmodule
module demux_4_16 #(parameter bus_size = 8)
	(input  [3:0] select,
		input  [bus_size-1:0] in,
		output  [bus_size-1:0] a,b,c,d, e,f,g,h, i,j,k,l, m,n,o,p);

		
		wire [bus_size-1:0] stage_1_1,stage1_2;
		demux_3_8 #(bus_size) deco_1_1(select[2:0],stage_1_1,a,b,c,d,e,f,g,h);
		demux_3_8 #(bus_size) deco_1_2(select[2:0],stage_1_2,i,j,k,l, m,n,o,p);
		deco_1_2 #(bus_size) deco_1(select[3],in,stage_1_1,stage_1_2);		
		
		
endmodule