data/full_repos/permissive/117436613/DE0_MMIX.v
1: b"%Error: data/full_repos/permissive/117436613/DE0_MMIX.v:214: Cannot find file containing module: 'MMIX_system'\n    MMIX_system u0 (\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117436613,data/full_repos/permissive/117436613/MMIX_system\n             data/full_repos/permissive/117436613,data/full_repos/permissive/117436613/MMIX_system.v\n             data/full_repos/permissive/117436613,data/full_repos/permissive/117436613/MMIX_system.sv\n             MMIX_system\n             MMIX_system.v\n             MMIX_system.sv\n             obj_dir/MMIX_system\n             obj_dir/MMIX_system.v\n             obj_dir/MMIX_system.sv\n%Error: Exiting due to 1 error(s)\n"
module DE0_MMIX
	(

		CLOCK_50,
		CLOCK_50_2,

		BUTTON,

		SW,

		HEX0_D,
		HEX0_DP,
		HEX1_D,
		HEX1_DP,
		HEX2_D,
		HEX2_DP,
		HEX3_D,
		HEX3_DP,

		LEDG,

		UART_TXD,
		UART_RXD,
		UART_CTS,
		UART_RTS,

		DRAM_DQ,
		DRAM_ADDR,
		DRAM_LDQM,
		DRAM_UDQM,
		DRAM_WE_N,
		DRAM_CAS_N,
		DRAM_RAS_N,
		DRAM_CS_N,
		DRAM_BA_0,
		DRAM_BA_1,
		DRAM_CLK,
		DRAM_CKE,

		FL_DQ,
		FL_DQ15_AM1,
		FL_ADDR,
		FL_WE_N,
		FL_RST_N,
		FL_OE_N,
		FL_CE_N,
		FL_WP_N,
		FL_BYTE_N,
		FL_RY,

		LCD_BLON,
		LCD_RW,
		LCD_EN,
		LCD_RS,
		LCD_DATA,

		SD_DAT0,
		SD_DAT3,
		SD_CMD,
		SD_CLK,
		SD_WP_N,

		PS2_KBDAT,
		PS2_KBCLK,
		PS2_MSDAT,
		PS2_MSCLK,

		VGA_HS,
		VGA_VS,
		VGA_R,
		VGA_G,
		VGA_B,

		GPIO0_CLKIN,
		GPIO0_CLKOUT,
		GPIO0_D,
		GPIO1_CLKIN,
		GPIO1_CLKOUT,
		GPIO1_D
	);


input			CLOCK_50;
input			CLOCK_50_2;

input	[2:0]	BUTTON;

input	[9:0]	SW;

output	[6:0]	HEX0_D;
output			HEX0_DP;
output	[6:0]	HEX1_D;
output			HEX1_DP;
output	[6:0]	HEX2_D;
output			HEX2_DP;
output	[6:0]	HEX3_D;
output			HEX3_DP;

output	[9:0]	LEDG;

output			UART_TXD;
input			UART_RXD;
output			UART_CTS;
input			UART_RTS;

inout	[15:0]	DRAM_DQ;
output	[12:0]	DRAM_ADDR;
output			DRAM_LDQM;
output			DRAM_UDQM;
output			DRAM_WE_N;
output			DRAM_CAS_N;
output			DRAM_RAS_N;
output			DRAM_CS_N;
output			DRAM_BA_0;
output			DRAM_BA_1;
output			DRAM_CLK;
output			DRAM_CKE;

inout	[14:0]	FL_DQ;
inout			FL_DQ15_AM1;
output	[21:0]	FL_ADDR;
output			FL_WE_N;
output			FL_RST_N;
output			FL_OE_N;
output			FL_CE_N;
output			FL_WP_N;
output			FL_BYTE_N;
input			FL_RY;

inout	[7:0]	LCD_DATA;
output			LCD_BLON;
output			LCD_RW;
output			LCD_EN;
output			LCD_RS;

inout			SD_DAT0;
inout			SD_DAT3;
inout			SD_CMD;
output			SD_CLK;
input			SD_WP_N;

inout		 	PS2_KBDAT;
inout			PS2_KBCLK;
inout		 	PS2_MSDAT;
inout			PS2_MSCLK;

output			VGA_HS;
output			VGA_VS;
output	[3:0]	VGA_R;
output	[3:0]	VGA_G;
output	[3:0]	VGA_B;

input	[1:0]	GPIO0_CLKIN;
output	[1:0]	GPIO0_CLKOUT;
inout	[31:0]	GPIO0_D;
input	[1:0]	GPIO1_CLKIN;
output	[1:0]	GPIO1_CLKOUT;
inout	[31:0]	GPIO1_D;












    MMIX_system u0 (
        .dbg_led_led		({HEX3_DP, HEX3_D, HEX2_DP, HEX2_D, HEX1_DP, HEX1_D, HEX0_DP, HEX0_D}),
        .dbg_led_btn		(BUTTON),
        .dbg_led_ledg		(LEDG),
        .dbg_led_sw			(SW),
        .clk_clk       (CLOCK_50),
        .reset_reset_n (BUTTON[0]),
        .sdram_wire_addr   (DRAM_ADDR),
        .sdram_wire_ba     ({DRAM_BA_1, DRAM_BA_0}),
        .sdram_wire_cas_n  (DRAM_CAS_N),
        .sdram_wire_cke    (DRAM_CKE),
        .sdram_wire_cs_n   (DRAM_CS_N),
        .sdram_wire_dq     (DRAM_DQ),
        .sdram_wire_dqm    ({DRAM_UDQM, DRAM_LDQM}),
        .sdram_wire_ras_n  (DRAM_RAS_N),
        .sdram_wire_we_n   (DRAM_WE_N),
        .sdram_clk_clk     (DRAM_CLK),
        .flash_wire_ADDR  ({FL_ADDR[20:0],FL_DQ15_AM1}),
        .flash_wire_CE_N  (FL_CE_N),
        .flash_wire_OE_N  (FL_OE_N),
        .flash_wire_WE_N  (FL_WE_N),
        .flash_wire_RST_N (FL_RST_N),
        .flash_wire_DQ    (FL_DQ[7:0]),
        .vga_wire_CLK     (),
        .vga_wire_HS      (VGA_HS),
        .vga_wire_VS      (VGA_VS),
        .vga_wire_R       (VGA_R),
        .vga_wire_G       (VGA_G),
        .vga_wire_B       (VGA_B),
        .ps2_wire_CLK            (PS2_KBCLK),
        .ps2_wire_DAT            (PS2_KBDAT),
        .sd_card_wire_b_SD_cmd   (SD_CMD),
        .sd_card_wire_b_SD_dat   (SD_DAT0),
        .sd_card_wire_b_SD_dat3  (SD_DAT3),
        .sd_card_wire_o_SD_clock (SD_CLK)
	 );

endmodule
module DE0_MMIX
	(

		CLOCK_50,
		CLOCK_50_2,

		BUTTON,

		SW,

		HEX0_D,
		HEX0_DP,
		HEX1_D,
		HEX1_DP,
		HEX2_D,
		HEX2_DP,
		HEX3_D,
		HEX3_DP,

		LEDG,

		UART_TXD,
		UART_RXD,
		UART_CTS,
		UART_RTS,

		DRAM_DQ,
		DRAM_ADDR,
		DRAM_LDQM,
		DRAM_UDQM,
		DRAM_WE_N,
		DRAM_CAS_N,
		DRAM_RAS_N,
		DRAM_CS_N,
		DRAM_BA_0,
		DRAM_BA_1,
		DRAM_CLK,
		DRAM_CKE,

		FL_DQ,
		FL_DQ15_AM1,
		FL_ADDR,
		FL_WE_N,
		FL_RST_N,
		FL_OE_N,
		FL_CE_N,
		FL_WP_N,
		FL_BYTE_N,
		FL_RY,

		LCD_BLON,
		LCD_RW,
		LCD_EN,
		LCD_RS,
		LCD_DATA,

		SD_DAT0,
		SD_DAT3,
		SD_CMD,
		SD_CLK,
		SD_WP_N,

		PS2_KBDAT,
		PS2_KBCLK,
		PS2_MSDAT,
		PS2_MSCLK,

		VGA_HS,
		VGA_VS,
		VGA_R,
		VGA_G,
		VGA_B,

		GPIO0_CLKIN,
		GPIO0_CLKOUT,
		GPIO0_D,
		GPIO1_CLKIN,
		GPIO1_CLKOUT,
		GPIO1_D
	);



input			CLOCK_50;
input			CLOCK_50_2;

input	[2:0]	BUTTON;

input	[9:0]	SW;

output	[6:0]	HEX0_D;
output			HEX0_DP;
output	[6:0]	HEX1_D;
output			HEX1_DP;
output	[6:0]	HEX2_D;
output			HEX2_DP;
output	[6:0]	HEX3_D;
output			HEX3_DP;

output	[9:0]	LEDG;

output			UART_TXD;
input			UART_RXD;
output			UART_CTS;
input			UART_RTS;

inout	[15:0]	DRAM_DQ;
output	[12:0]	DRAM_ADDR;
output			DRAM_LDQM;
output			DRAM_UDQM;
output			DRAM_WE_N;
output			DRAM_CAS_N;
output			DRAM_RAS_N;
output			DRAM_CS_N;
output			DRAM_BA_0;
output			DRAM_BA_1;
output			DRAM_CLK;
output			DRAM_CKE;

inout	[14:0]	FL_DQ;
inout			FL_DQ15_AM1;
output	[21:0]	FL_ADDR;
output			FL_WE_N;
output			FL_RST_N;
output			FL_OE_N;
output			FL_CE_N;
output			FL_WP_N;
output			FL_BYTE_N;
input			FL_RY;

inout	[7:0]	LCD_DATA;
output			LCD_BLON;
output			LCD_RW;
output			LCD_EN;
output			LCD_RS;

inout			SD_DAT0;
inout			SD_DAT3;
inout			SD_CMD;
output			SD_CLK;
input			SD_WP_N;

inout		 	PS2_KBDAT;
inout			PS2_KBCLK;
inout		 	PS2_MSDAT;
inout			PS2_MSCLK;

output			VGA_HS;
output			VGA_VS;
output	[3:0]	VGA_R;
output	[3:0]	VGA_G;
output	[3:0]	VGA_B;

input	[1:0]	GPIO0_CLKIN;
output	[1:0]	GPIO0_CLKOUT;
inout	[31:0]	GPIO0_D;
input	[1:0]	GPIO1_CLKIN;
output	[1:0]	GPIO1_CLKOUT;
inout	[31:0]	GPIO1_D;












    MMIX_system u0 (
        .dbg_led_led		({HEX3_DP, HEX3_D, HEX2_DP, HEX2_D, HEX1_DP, HEX1_D, HEX0_DP, HEX0_D}),
        .dbg_led_btn		(BUTTON),
        .dbg_led_ledg		(LEDG),
        .dbg_led_sw			(SW),
        .clk_clk       (CLOCK_50),
        .reset_reset_n (BUTTON[0]),
        .sdram_wire_addr   (DRAM_ADDR),
        .sdram_wire_ba     ({DRAM_BA_1, DRAM_BA_0}),
        .sdram_wire_cas_n  (DRAM_CAS_N),
        .sdram_wire_cke    (DRAM_CKE),
        .sdram_wire_cs_n   (DRAM_CS_N),
        .sdram_wire_dq     (DRAM_DQ),
        .sdram_wire_dqm    ({DRAM_UDQM, DRAM_LDQM}),
        .sdram_wire_ras_n  (DRAM_RAS_N),
        .sdram_wire_we_n   (DRAM_WE_N),
        .sdram_clk_clk     (DRAM_CLK),
        .flash_wire_ADDR  ({FL_ADDR[20:0],FL_DQ15_AM1}),
        .flash_wire_CE_N  (FL_CE_N),
        .flash_wire_OE_N  (FL_OE_N),
        .flash_wire_WE_N  (FL_WE_N),
        .flash_wire_RST_N (FL_RST_N),
        .flash_wire_DQ    (FL_DQ[7:0]),
        .vga_wire_CLK     (),
        .vga_wire_HS      (VGA_HS),
        .vga_wire_VS      (VGA_VS),
        .vga_wire_R       (VGA_R),
        .vga_wire_G       (VGA_G),
        .vga_wire_B       (VGA_B),
        .ps2_wire_CLK            (PS2_KBCLK),
        .ps2_wire_DAT            (PS2_KBDAT),
        .sd_card_wire_b_SD_cmd   (SD_CMD),
        .sd_card_wire_b_SD_dat   (SD_DAT0),
        .sd_card_wire_b_SD_dat3  (SD_DAT3),
        .sd_card_wire_o_SD_clock (SD_CLK)
	 );

endmodule