data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v
 line:89: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'h7C0; msrwen = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'h7C1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'h7C2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'h7C3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'h000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, csrdata = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'h7C0; msrwen = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'h7C1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'h7C2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'h7C3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'h000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, csrdata = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC0; msrwen = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1; msrwen = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n        #10 pc = 32\'h00000004;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n        #5 illegalinst = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n        #10 illegalinst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'hFC0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n        #10 pc = 32\'h00000008;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n        #5 ebreak = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n        #10 ebreak = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'hFC0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n        #10 pc = 32\'h0000000c;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n        #5 ecall = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n        #10 ecall = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'hFC0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:198: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'h7C0; msrwen = 1; rs1data = 32\'h00000001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:204: Unsupported: Ignoring delay on this delayed statement.\n        #10 pc = 32\'h00000004;  msrwen = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n        #5 illegalinst = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:207: Unsupported: Ignoring delay on this delayed statement.\n        #10 illegalinst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'hFC0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:210: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:212: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:216: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'h7C0; msrwen = 1; rs1data = 32\'h00000001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:217: Unsupported: Ignoring delay on this delayed statement.\n        #10 pc = 32\'h00000008;  msrwen = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:218: Unsupported: Ignoring delay on this delayed statement.\n        #5 ebreak = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:219: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n        #10 ebreak = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'hFC0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:222: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:223: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:225: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:229: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'h7C0; msrwen = 1; rs1data = 32\'h00000001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:230: Unsupported: Ignoring delay on this delayed statement.\n        #10 pc = 32\'h0000000c;  msrwen = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:231: Unsupported: Ignoring delay on this delayed statement.\n        #5 ecall = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n        #10 ecall = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:234: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'hFC0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:238: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:239: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:243: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:244: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'h7C0; msrwen = 1; rs1data = 32\'h00000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:249: Unsupported: Ignoring delay on this delayed statement.\n        #10 pc = 32\'h0000000f;  msrwen = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:250: Unsupported: Ignoring delay on this delayed statement.\n        #5 extinterrupt = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:251: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n        #10 extinterrupt = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:253: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'hFC0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:255: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:257: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:262: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'h7C0; msrwen = 1; rs1data = 32\'h00000001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:263: Unsupported: Ignoring delay on this delayed statement.\n        #10 pc = 32\'h0000000f;  msrwen = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n        #5 extinterrupt = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:265: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:266: Unsupported: Ignoring delay on this delayed statement.\n        #10 extinterrupt = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:267: Unsupported: Ignoring delay on this delayed statement.\n        #5 csraddr = 12\'hFC0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:268: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:269: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:270: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:271: Unsupported: Ignoring delay on this delayed statement.\n        #10 csraddr = 12\'hFC2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:272: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:275: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/privilege_tb.v:37: Cannot find file containing module: \'privilege\'\n privilege #(\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/privilege\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/privilege.v\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/privilege.sv\n             privilege\n             privilege.v\n             privilege.sv\n             obj_dir/privilege\n             obj_dir/privilege.v\n             obj_dir/privilege.sv\n%Error: Exiting due to 1 error(s), 135 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module privilege_tb;
	

	reg clk;
	reg reset;
	

	reg ecall;
	reg ebreak;
	reg illegalinst;
	reg extinterrupt;
	

	reg [31:0] pc;
	

	reg msrwen;
    reg [11:0] csraddr;
    reg [3:0] rs1addr;
    reg [31:0] rs1data;
    wire [31:0] csrdata;
    

    wire exception;
    wire [31:0] mux_epc_return;
    wire [31:0] mux_mevect;
    

	wire [2:0] mstatus;
	wire [4:0] mcause;
	wire [31:0] mepc;
	wire [31:0] mevect;


	privilege #(
	   .VECTOR(32'h00000004)
	)
	privilege(
		.I_clk(clk),
		.I_rst(reset),
        

        .I_ecall(ecall),
        .I_ebreak(ebreak),
        .I_illegalinst(illegalinst),
        

        .I_extinterrupt(extinterrupt),
        
        

        .I_pc(pc),
        .I_msrwen(msrwen),
        .I_csraddr(csraddr),
        .I_rs1addr(rs1addr),
        .I_rs1data(rs1data),
        .O_csrdata(csrdata),
        

        .O_exception(exception),
        .O_epcreturn(mux_epc_return),
        .O_evect(mux_mevect),
        

        .mstatus(mstatus),
        .mcause(mcause),
        .mepc(mepc),
        .mevect(mevect)
        );


	always begin
		#5 clk = ~clk;
	end

	initial begin

		clk = 1; reset = 0; csraddr = 12'h000; rs1addr= 4'b0001; rs1data = 32'hFFFFFFFF; msrwen = 1; 
        extinterrupt = 0; illegalinst = 0; ebreak = 0; ecall = 0; pc = 32'h00000000;
        

        $display("Checking read-only addresses don't write to MSR");
        $display("rs1data = %h", rs1data);
        

        #10 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC3;
        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);


        $display("\nChecking read-write addresses don't write to MSR when msrwen = 0");
        $display("rs1data = %h", rs1data);
        
        #10 csraddr = 12'h7C0; msrwen = 0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C3;
        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);
        

        $display("\nChecking invalid read address output's zero on csr_data");
        #10 csraddr = 12'h000;
        #10 $display("csraddr = %h, csrdata = %b", csraddr, csrdata);
        

        $display("\nChecking read-write addresses write to MSR when msrwen = 1");
        $display("Note: The output value of csrdata will be the previous value in the msr");
        #10 csraddr = 12'h7C0; msrwen = 1;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C3;
        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);
        

        $display("\nChecking invalid write address output's zero on csr_data");
        #10 csraddr = 12'h000;
        #10 $display("csraddr = %h, csrdata = %b", csraddr, csrdata);
        

        $display("\nChecking read-only addresses to make sure that the MSR have updated with the new value");
        #10 csraddr = 12'hFC0; msrwen = 0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC3;
        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);
        


        

        $display("\nChecking that reset re-initialises the registers correctly.");
        #10 reset = 1; msrwen = 0;
        #10 reset = 0;
        #10 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC3;
        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);
        

        $display("\n\nRunning Negedge tests now");
        
        $display("\nChecking Expections work correct when MEIE is 0");

        $display("\nChecking illegal instruction exception");
        #10 pc = 32'h00000004;
        #5 illegalinst = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 illegalinst = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking ebreak exception");
        #10 pc = 32'h00000008;
        #5 ebreak = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 ebreak = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking ecall exception");
        #10 pc = 32'h0000000c;
        #5 ecall = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 ecall = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking Expections work correct when MEIE is 1");

        $display("\nChecking illegal instruction exception");
        #5 csraddr = 12'h7C0; msrwen = 1; rs1data = 32'h00000001;
        #10 pc = 32'h00000004;  msrwen = 0;
        #5 illegalinst = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 illegalinst = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking ebreak exception");
        #5 csraddr = 12'h7C0; msrwen = 1; rs1data = 32'h00000001;
        #10 pc = 32'h00000008;  msrwen = 0;
        #5 ebreak = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 ebreak = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking ecall exception");
        #5 csraddr = 12'h7C0; msrwen = 1; rs1data = 32'h00000001;
        #10 pc = 32'h0000000c;  msrwen = 0;
        #5 ecall = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 ecall = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking External Interrupts work correctly");

        #10 reset = 1;
        #10 reset = 0;
        

        $display("\nChecking interrupts don't occur when MEIE is 0");
        #5 csraddr = 12'h7C0; msrwen = 1; rs1data = 32'h00000000;
        #10 pc = 32'h0000000f;  msrwen = 0;
        #5 extinterrupt = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 extinterrupt = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        

        $display("\nChecking interrupts occur when MEIE is 1");
        #5 csraddr = 12'h7C0; msrwen = 1; rs1data = 32'h00000001;
        #10 pc = 32'h0000000f;  msrwen = 0;
        #5 extinterrupt = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 extinterrupt = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);


		#10 $finish;
	end
	
endmodule
module privilege_tb;

	

	reg clk;
	reg reset;
	

	reg ecall;
	reg ebreak;
	reg illegalinst;
	reg extinterrupt;
	

	reg [31:0] pc;
	

	reg msrwen;
    reg [11:0] csraddr;
    reg [3:0] rs1addr;
    reg [31:0] rs1data;
    wire [31:0] csrdata;
    

    wire exception;
    wire [31:0] mux_epc_return;
    wire [31:0] mux_mevect;
    

	wire [2:0] mstatus;
	wire [4:0] mcause;
	wire [31:0] mepc;
	wire [31:0] mevect;


	privilege #(
	   .VECTOR(32'h00000004)
	)
	privilege(
		.I_clk(clk),
		.I_rst(reset),
        

        .I_ecall(ecall),
        .I_ebreak(ebreak),
        .I_illegalinst(illegalinst),
        

        .I_extinterrupt(extinterrupt),
        
        

        .I_pc(pc),
        .I_msrwen(msrwen),
        .I_csraddr(csraddr),
        .I_rs1addr(rs1addr),
        .I_rs1data(rs1data),
        .O_csrdata(csrdata),
        

        .O_exception(exception),
        .O_epcreturn(mux_epc_return),
        .O_evect(mux_mevect),
        

        .mstatus(mstatus),
        .mcause(mcause),
        .mepc(mepc),
        .mevect(mevect)
        );


	always begin
		#5 clk = ~clk;
	end

	initial begin

		clk = 1; reset = 0; csraddr = 12'h000; rs1addr= 4'b0001; rs1data = 32'hFFFFFFFF; msrwen = 1; 
        extinterrupt = 0; illegalinst = 0; ebreak = 0; ecall = 0; pc = 32'h00000000;
        

        $display("Checking read-only addresses don't write to MSR");
        $display("rs1data = %h", rs1data);
        

        #10 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC3;
        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);


        $display("\nChecking read-write addresses don't write to MSR when msrwen = 0");
        $display("rs1data = %h", rs1data);
        
        #10 csraddr = 12'h7C0; msrwen = 0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C3;
        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);
        

        $display("\nChecking invalid read address output's zero on csr_data");
        #10 csraddr = 12'h000;
        #10 $display("csraddr = %h, csrdata = %b", csraddr, csrdata);
        

        $display("\nChecking read-write addresses write to MSR when msrwen = 1");
        $display("Note: The output value of csrdata will be the previous value in the msr");
        #10 csraddr = 12'h7C0; msrwen = 1;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        #10 csraddr = 12'h7C3;
        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);
        

        $display("\nChecking invalid write address output's zero on csr_data");
        #10 csraddr = 12'h000;
        #10 $display("csraddr = %h, csrdata = %b", csraddr, csrdata);
        

        $display("\nChecking read-only addresses to make sure that the MSR have updated with the new value");
        #10 csraddr = 12'hFC0; msrwen = 0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC3;
        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);
        


        

        $display("\nChecking that reset re-initialises the registers correctly.");
        #10 reset = 1; msrwen = 0;
        #10 reset = 0;
        #10 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC3;
        #10 $display("csraddr = %h, mevect = %b", csraddr, csrdata);
        

        $display("\n\nRunning Negedge tests now");
        
        $display("\nChecking Expections work correct when MEIE is 0");

        $display("\nChecking illegal instruction exception");
        #10 pc = 32'h00000004;
        #5 illegalinst = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 illegalinst = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking ebreak exception");
        #10 pc = 32'h00000008;
        #5 ebreak = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 ebreak = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking ecall exception");
        #10 pc = 32'h0000000c;
        #5 ecall = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 ecall = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking Expections work correct when MEIE is 1");

        $display("\nChecking illegal instruction exception");
        #5 csraddr = 12'h7C0; msrwen = 1; rs1data = 32'h00000001;
        #10 pc = 32'h00000004;  msrwen = 0;
        #5 illegalinst = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 illegalinst = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking ebreak exception");
        #5 csraddr = 12'h7C0; msrwen = 1; rs1data = 32'h00000001;
        #10 pc = 32'h00000008;  msrwen = 0;
        #5 ebreak = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 ebreak = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking ecall exception");
        #5 csraddr = 12'h7C0; msrwen = 1; rs1data = 32'h00000001;
        #10 pc = 32'h0000000c;  msrwen = 0;
        #5 ecall = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 ecall = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        
        $display("\nChecking External Interrupts work correctly");

        #10 reset = 1;
        #10 reset = 0;
        

        $display("\nChecking interrupts don't occur when MEIE is 0");
        #5 csraddr = 12'h7C0; msrwen = 1; rs1data = 32'h00000000;
        #10 pc = 32'h0000000f;  msrwen = 0;
        #5 extinterrupt = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 extinterrupt = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);
        

        $display("\nChecking interrupts occur when MEIE is 1");
        #5 csraddr = 12'h7C0; msrwen = 1; rs1data = 32'h00000001;
        #10 pc = 32'h0000000f;  msrwen = 0;
        #5 extinterrupt = 1;
        #10 $display("Exception = %h; PC = %h, EPC_RETURN = %h", exception, pc, mux_epc_return);
        #10 extinterrupt = 0;
        #5 csraddr = 12'hFC0;
        #10 $display("csraddr = %h, mstatus = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC1;
        #10 $display("csraddr = %h, mcause = %b", csraddr, csrdata);
        #10 csraddr = 12'hFC2;
        #10 $display("csraddr = %h, mepc = %b", csraddr, csrdata);


		#10 $finish;
	end
	
endmodule