data/full_repos/permissive/150331006/src/Project2_top.v
1: b"%Error: data/full_repos/permissive/150331006/src/Project2_top.v:15: Cannot find file containing module: 'Go'\n Go G1(CLK,DISPLAY0,DISPLAY1,DISPLAY2,DISPLAY3,DISPLAY4,DISPLAY5);\n ^~\n        ... Looked in:\n             data/full_repos/permissive/150331006/src,data/full_repos/permissive/150331006/Go\n             data/full_repos/permissive/150331006/src,data/full_repos/permissive/150331006/Go.v\n             data/full_repos/permissive/150331006/src,data/full_repos/permissive/150331006/Go.sv\n             Go\n             Go.v\n             Go.sv\n             obj_dir/Go\n             obj_dir/Go.v\n             obj_dir/Go.sv\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:17: Cannot find file containing module: 'LFSR'\n LFSR L1(LAG,Q);\n ^~~~\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:19: Cannot find file containing module: 'Down_count'\n Down_count DO1(KEY[0],LAG,DC_EN,DC_CLR,Q,DC_DONE);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:21: Cannot find file containing module: 'High_score'\n High_score H1(CLK,HIGH_EN,BCD,HIGH);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:23: Cannot find file containing module: 'Clock_divider'\n Clock_divider D1(CLK,LAG);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:25: Cannot find file containing module: 'FSM'\n FSM F1(SW,KEY,LAG,DC_DONE,DC_EN,DC_CLR,BCD_EN,BCD_CLR,HIGH_EN,LED);\n ^~~\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:27: Cannot find file containing module: 'BCD_counter'\n BCD_counter C1(BCD_EN,BCD_CLR,LAG,BCD[3:0],BCD[7:4],BCD[11:8],BCD[15:12],BCD[19:16],BCD[23:20]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:29: Cannot find file containing module: 'BCD_decoder'\n BCD_decoder B1(BCD_EN,DC_CLR,CLK,SW,BCD[3:0],HIGH[3:0],HEX0,DISPLAY0);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:30: Cannot find file containing module: 'BCD_decoder'\n BCD_decoder B2(BCD_EN,DC_CLR,CLK,SW,BCD[7:4],HIGH[7:4],HEX1,DISPLAY1);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:31: Cannot find file containing module: 'BCD_decoder'\n BCD_decoder B3(BCD_EN,DC_CLR,CLK,SW,BCD[11:8],HIGH[11:8],HEX2,DISPLAY2);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:32: Cannot find file containing module: 'BCD_decoder'\n BCD_decoder B4(BCD_EN,DC_CLR,CLK,SW,BCD[15:12],HIGH[15:12],HEX3,DISPLAY3);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:33: Cannot find file containing module: 'BCD_decoder'\n BCD_decoder B5(BCD_EN,DC_CLR,CLK,SW,BCD[19:16],HIGH[19:16],HEX4,DISPLAY4);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/150331006/src/Project2_top.v:34: Cannot find file containing module: 'BCD_decoder'\n BCD_decoder B6(BCD_EN,DC_CLR,CLK,SW,BCD[23:20],BCD[23:20],HEX5,DISPLAY5);\n ^~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n"
module Project2_top(CLK,KEY,SW,LED,HEX0,HEX1,HEX2,HEX3,HEX4, HEX5);
	input CLK,SW;
	input [1:0] KEY;
	output LED;
	output [7:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5;
	wire DC_EN,DC_CLR,BCD_EN,BCD_CLR,HIGH_EN,DC_DONE,LAG;
	wire [23:0] BCD,HIGH;
	wire [10:0] Q;
	wire [7:0] DISPLAY0,DISPLAY1,DISPLAY2,DISPLAY3,DISPLAY4,DISPLAY5;
	
	Go G1(CLK,DISPLAY0,DISPLAY1,DISPLAY2,DISPLAY3,DISPLAY4,DISPLAY5);
	
	LFSR L1(LAG,Q);
	
	Down_count DO1(KEY[0],LAG,DC_EN,DC_CLR,Q,DC_DONE);
	
	High_score H1(CLK,HIGH_EN,BCD,HIGH);
	
	Clock_divider D1(CLK,LAG);
	
	FSM F1(SW,KEY,LAG,DC_DONE,DC_EN,DC_CLR,BCD_EN,BCD_CLR,HIGH_EN,LED);
	
	BCD_counter C1(BCD_EN,BCD_CLR,LAG,BCD[3:0],BCD[7:4],BCD[11:8],BCD[15:12],BCD[19:16],BCD[23:20]);
	
	BCD_decoder B1(BCD_EN,DC_CLR,CLK,SW,BCD[3:0],HIGH[3:0],HEX0,DISPLAY0);
	BCD_decoder B2(BCD_EN,DC_CLR,CLK,SW,BCD[7:4],HIGH[7:4],HEX1,DISPLAY1);
	BCD_decoder B3(BCD_EN,DC_CLR,CLK,SW,BCD[11:8],HIGH[11:8],HEX2,DISPLAY2);
	BCD_decoder B4(BCD_EN,DC_CLR,CLK,SW,BCD[15:12],HIGH[15:12],HEX3,DISPLAY3);
	BCD_decoder B5(BCD_EN,DC_CLR,CLK,SW,BCD[19:16],HIGH[19:16],HEX4,DISPLAY4);
	BCD_decoder B6(BCD_EN,DC_CLR,CLK,SW,BCD[23:20],BCD[23:20],HEX5,DISPLAY5);
endmodule
module Project2_top(CLK,KEY,SW,LED,HEX0,HEX1,HEX2,HEX3,HEX4, HEX5);

	input CLK,SW;
	input [1:0] KEY;
	output LED;
	output [7:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5;
	wire DC_EN,DC_CLR,BCD_EN,BCD_CLR,HIGH_EN,DC_DONE,LAG;
	wire [23:0] BCD,HIGH;
	wire [10:0] Q;
	wire [7:0] DISPLAY0,DISPLAY1,DISPLAY2,DISPLAY3,DISPLAY4,DISPLAY5;
	
	Go G1(CLK,DISPLAY0,DISPLAY1,DISPLAY2,DISPLAY3,DISPLAY4,DISPLAY5);
	
	LFSR L1(LAG,Q);
	
	Down_count DO1(KEY[0],LAG,DC_EN,DC_CLR,Q,DC_DONE);
	
	High_score H1(CLK,HIGH_EN,BCD,HIGH);
	
	Clock_divider D1(CLK,LAG);
	
	FSM F1(SW,KEY,LAG,DC_DONE,DC_EN,DC_CLR,BCD_EN,BCD_CLR,HIGH_EN,LED);
	
	BCD_counter C1(BCD_EN,BCD_CLR,LAG,BCD[3:0],BCD[7:4],BCD[11:8],BCD[15:12],BCD[19:16],BCD[23:20]);
	
	BCD_decoder B1(BCD_EN,DC_CLR,CLK,SW,BCD[3:0],HIGH[3:0],HEX0,DISPLAY0);
	BCD_decoder B2(BCD_EN,DC_CLR,CLK,SW,BCD[7:4],HIGH[7:4],HEX1,DISPLAY1);
	BCD_decoder B3(BCD_EN,DC_CLR,CLK,SW,BCD[11:8],HIGH[11:8],HEX2,DISPLAY2);
	BCD_decoder B4(BCD_EN,DC_CLR,CLK,SW,BCD[15:12],HIGH[15:12],HEX3,DISPLAY3);
	BCD_decoder B5(BCD_EN,DC_CLR,CLK,SW,BCD[19:16],HIGH[19:16],HEX4,DISPLAY4);
	BCD_decoder B6(BCD_EN,DC_CLR,CLK,SW,BCD[23:20],BCD[23:20],HEX5,DISPLAY5);
endmodule