data/full_repos/permissive/131358616/design/uart_echo/uart_echo.v
1: b"%Error: data/full_repos/permissive/131358616/design/uart_echo/uart_echo.v:30: Cannot find file containing module: 'uart'\nuart #(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/131358616/design/uart_echo,data/full_repos/permissive/131358616/uart\n             data/full_repos/permissive/131358616/design/uart_echo,data/full_repos/permissive/131358616/uart.v\n             data/full_repos/permissive/131358616/design/uart_echo,data/full_repos/permissive/131358616/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Error: Exiting due to 1 error(s)\n"
module uart_echo (
    input wire rst_n,
    input wire clk,
	
    output reg [7:0] byte_cnt,
    output wire error,

    input wire rx,
	output wire tx
);

parameter  clock_frequency        = 12000000;
parameter  baud_rate              = 9600;



wire rx_busy, tx_busy, new_value;

wire [7:0] received_data;

uart #(
	.clock_frequency(clock_frequency),
	.baud_rate(baud_rate)
) uart(
    .rst_n(rst_n),
    .clk(clk),
    .rx(rx),
	.tx(tx),
    .clear(new_value),
	.start_transmit(new_value),
    .rx_busy(rx_busy),
	.tx_busy(tx_busy),
    .error(error),
    .new_value(new_value),
	.data_to_send(received_data),
    .recvd_data(received_data)
);



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        byte_cnt <= 0;
    end else if (new_value) begin
        byte_cnt <= byte_cnt + 1;
    end
end

endmodule
module uart_echo (
    input wire rst_n,
    input wire clk,
	
    output reg [7:0] byte_cnt,
    output wire error,

    input wire rx,
	output wire tx
);


parameter  clock_frequency        = 12000000;
parameter  baud_rate              = 9600;



wire rx_busy, tx_busy, new_value;

wire [7:0] received_data;

uart #(
	.clock_frequency(clock_frequency),
	.baud_rate(baud_rate)
) uart(
    .rst_n(rst_n),
    .clk(clk),
    .rx(rx),
	.tx(tx),
    .clear(new_value),
	.start_transmit(new_value),
    .rx_busy(rx_busy),
	.tx_busy(tx_busy),
    .error(error),
    .new_value(new_value),
	.data_to_send(received_data),
    .recvd_data(received_data)
);



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        byte_cnt <= 0;
    end else if (new_value) begin
        byte_cnt <= byte_cnt + 1;
    end
end

endmodule