data/full_repos/permissive/136702298/3.Código/biestableJK.v
data/verilator_xmls/85641c11-0200-4887-9f6b-b82639ce7b3b.xml
module biestableJK (output reg Q, output wire NQ, input wire J, input wire K,   input wire C);

  not(NQ,Q);
  initial
  begin

    Q='b0;
  end    

  always @(posedge C)
    case ({J,K})
      2'b10: Q='b1;
      2'b01: Q='b0;
      2'b11: Q=~Q;
    endcase
endmodule
module biestableJK (output reg Q, output wire NQ, input wire J, input wire K,   input wire C);


  not(NQ,Q);
  initial
  begin

    Q='b0;
  end    

  always @(posedge C)
    case ({J,K})
      2'b10: Q='b1;
      2'b01: Q='b0;
      2'b11: Q=~Q;
    endcase
endmodule