data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_timer.v
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1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_timer.v:68: Cannot find include file: ../core/rfnoc_chdr_utils.vh\n  `include "../core/rfnoc_chdr_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/../core/rfnoc_chdr_utils.vh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/../core/rfnoc_chdr_utils.vh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/../core/rfnoc_chdr_utils.vh.sv\n             ../core/rfnoc_chdr_utils.vh\n             ../core/rfnoc_chdr_utils.vh.v\n             ../core/rfnoc_chdr_utils.vh.sv\n             obj_dir/../core/rfnoc_chdr_utils.vh\n             obj_dir/../core/rfnoc_chdr_utils.vh.v\n             obj_dir/../core/rfnoc_chdr_utils.vh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_timer.v:69: Cannot find include file: ../core/rfnoc_axis_ctrl_utils.vh\n  `include "../core/rfnoc_axis_ctrl_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module ctrlport_timer #(
  parameter [0:0] EXEC_LATE_CMDS = 1
)(

  input  wire         clk,
  input  wire         rst,

  input  wire [63:0]  time_now,
  input  wire         time_now_stb,
  input  wire [3:0]   time_ignore_bits,

  input  wire         s_ctrlport_req_wr,
  input  wire         s_ctrlport_req_rd,
  input  wire [19:0]  s_ctrlport_req_addr,
  input  wire [31:0]  s_ctrlport_req_data,
  input  wire [3:0]   s_ctrlport_req_byte_en,
  input  wire         s_ctrlport_req_has_time,
  input  wire [63:0]  s_ctrlport_req_time,

  output wire         s_ctrlport_resp_ack,
  output wire [1:0]   s_ctrlport_resp_status,
  output wire [31:0]  s_ctrlport_resp_data,

  output wire         m_ctrlport_req_wr,
  output wire         m_ctrlport_req_rd,
  output wire [19:0]  m_ctrlport_req_addr,
  output wire [31:0]  m_ctrlport_req_data,
  output wire [3:0]   m_ctrlport_req_byte_en,

  input  wire         m_ctrlport_resp_ack,
  input  wire [1:0]   m_ctrlport_resp_status,
  input  wire [31:0]  m_ctrlport_resp_data
);

  `include "../core/rfnoc_chdr_utils.vh"
  `include "../core/rfnoc_axis_ctrl_utils.vh"








  reg          pending, has_time, on_time, late;
  wire         exec, consume, valid;

  wire         cached_req_wr, cached_req_rd;
  wire [19:0]  cached_req_addr;
  wire [31:0]  cached_req_data;
  wire [3:0]   cached_req_byte_en;
  wire         cached_req_has_time;
  wire [63:0]  cached_req_time;
  wire         cached_req_valid;

  axi_fifo_flop #(.WIDTH(1+1+20+32+4+1+64)) req_cache_i (
    .clk(clk), .reset(rst), .clear(1'b0),
    .i_tdata({s_ctrlport_req_wr, s_ctrlport_req_rd, s_ctrlport_req_addr, s_ctrlport_req_data,
              s_ctrlport_req_byte_en, s_ctrlport_req_has_time, s_ctrlport_req_time}),
    .i_tvalid(s_ctrlport_req_wr | s_ctrlport_req_rd), .i_tready(),
    .o_tdata({cached_req_wr, cached_req_rd, cached_req_addr, cached_req_data,
              cached_req_byte_en, cached_req_has_time, cached_req_time}),
    .o_tvalid(cached_req_valid), .o_tready(consume),
    .occupied(), .space()
  );


  wire [63:0] mask = (~64'd0 << time_ignore_bits);


  reg        has_time_0;
  reg        has_time_1;
  reg        valid_0;
  reg        valid_1;
  reg [63:0] time_0;
  reg        time_stb_1, time_stb_0;
  reg [63:0] req_time_0;
  reg        on_time_1;
  reg        late_1;





  always @(posedge clk) begin
    if (rst || consume) begin
      has_time_0 <= 'bX;
      time_stb_0 <= 'bX;
      time_0     <= 'bX;
      req_time_0 <= 'bX;
      has_time_1 <= 'bX;
      time_stb_1 <= 'bX;
      on_time_1  <= 'bX;
      late_1     <= 'bX;
      has_time   <= 'bX;
      on_time    <= 'bX;

      valid_0    <= 1'b0;
      valid_1    <= 1'b0;
      pending    <= 1'b0;
      late       <= 1'b0;
    end else begin

      valid_0    <= cached_req_valid;
      has_time_0 <= cached_req_has_time;
      time_stb_0 <= time_now_stb;
      time_0     <= time_now & mask;
      req_time_0 <= cached_req_time & mask;


      valid_1    <= valid_0;
      has_time_1 <= has_time_0;
      time_stb_1 <= time_stb_0;
      on_time_1  <= req_time_0 == time_0;
      late_1     <= req_time_0 <  time_0;


      pending  <= valid_1;
      has_time <= has_time_1;
      on_time  <= valid_1 && has_time_1 && time_stb_1 && on_time_1;
      late     <= valid_1 && has_time_1 && time_stb_1 && late_1;
    end
  end


  assign exec    = pending && (!has_time || on_time || (EXEC_LATE_CMDS && late));
  assign consume = exec || late;

  assign m_ctrlport_req_wr      = cached_req_wr & exec;
  assign m_ctrlport_req_rd      = cached_req_rd & exec;
  assign m_ctrlport_req_addr    = cached_req_addr;
  assign m_ctrlport_req_data    = cached_req_data;
  assign m_ctrlport_req_byte_en = cached_req_byte_en;

  wire [1:0] resp_status = (late && !exec) ? AXIS_CTRL_STS_TSERR : m_ctrlport_resp_status;
  axi_fifo_flop #(.WIDTH(2+32)) resp_cache_i (
    .clk(clk), .reset(rst), .clear(1'b0),
    .i_tdata({resp_status, m_ctrlport_resp_data}),
    .i_tvalid(m_ctrlport_resp_ack || (late && !exec)), .i_tready(),
    .o_tdata({s_ctrlport_resp_status, s_ctrlport_resp_data}),
    .o_tvalid(s_ctrlport_resp_ack), .o_tready(s_ctrlport_resp_ack),
    .occupied(), .space()
  );

endmodule
module ctrlport_timer #(
  parameter [0:0] EXEC_LATE_CMDS = 1
)(

  input  wire         clk,
  input  wire         rst,

  input  wire [63:0]  time_now,
  input  wire         time_now_stb,
  input  wire [3:0]   time_ignore_bits,

  input  wire         s_ctrlport_req_wr,
  input  wire         s_ctrlport_req_rd,
  input  wire [19:0]  s_ctrlport_req_addr,
  input  wire [31:0]  s_ctrlport_req_data,
  input  wire [3:0]   s_ctrlport_req_byte_en,
  input  wire         s_ctrlport_req_has_time,
  input  wire [63:0]  s_ctrlport_req_time,

  output wire         s_ctrlport_resp_ack,
  output wire [1:0]   s_ctrlport_resp_status,
  output wire [31:0]  s_ctrlport_resp_data,

  output wire         m_ctrlport_req_wr,
  output wire         m_ctrlport_req_rd,
  output wire [19:0]  m_ctrlport_req_addr,
  output wire [31:0]  m_ctrlport_req_data,
  output wire [3:0]   m_ctrlport_req_byte_en,

  input  wire         m_ctrlport_resp_ack,
  input  wire [1:0]   m_ctrlport_resp_status,
  input  wire [31:0]  m_ctrlport_resp_data
);


  `include "../core/rfnoc_chdr_utils.vh"
  `include "../core/rfnoc_axis_ctrl_utils.vh"








  reg          pending, has_time, on_time, late;
  wire         exec, consume, valid;

  wire         cached_req_wr, cached_req_rd;
  wire [19:0]  cached_req_addr;
  wire [31:0]  cached_req_data;
  wire [3:0]   cached_req_byte_en;
  wire         cached_req_has_time;
  wire [63:0]  cached_req_time;
  wire         cached_req_valid;

  axi_fifo_flop #(.WIDTH(1+1+20+32+4+1+64)) req_cache_i (
    .clk(clk), .reset(rst), .clear(1'b0),
    .i_tdata({s_ctrlport_req_wr, s_ctrlport_req_rd, s_ctrlport_req_addr, s_ctrlport_req_data,
              s_ctrlport_req_byte_en, s_ctrlport_req_has_time, s_ctrlport_req_time}),
    .i_tvalid(s_ctrlport_req_wr | s_ctrlport_req_rd), .i_tready(),
    .o_tdata({cached_req_wr, cached_req_rd, cached_req_addr, cached_req_data,
              cached_req_byte_en, cached_req_has_time, cached_req_time}),
    .o_tvalid(cached_req_valid), .o_tready(consume),
    .occupied(), .space()
  );


  wire [63:0] mask = (~64'd0 << time_ignore_bits);


  reg        has_time_0;
  reg        has_time_1;
  reg        valid_0;
  reg        valid_1;
  reg [63:0] time_0;
  reg        time_stb_1, time_stb_0;
  reg [63:0] req_time_0;
  reg        on_time_1;
  reg        late_1;





  always @(posedge clk) begin
    if (rst || consume) begin
      has_time_0 <= 'bX;
      time_stb_0 <= 'bX;
      time_0     <= 'bX;
      req_time_0 <= 'bX;
      has_time_1 <= 'bX;
      time_stb_1 <= 'bX;
      on_time_1  <= 'bX;
      late_1     <= 'bX;
      has_time   <= 'bX;
      on_time    <= 'bX;

      valid_0    <= 1'b0;
      valid_1    <= 1'b0;
      pending    <= 1'b0;
      late       <= 1'b0;
    end else begin

      valid_0    <= cached_req_valid;
      has_time_0 <= cached_req_has_time;
      time_stb_0 <= time_now_stb;
      time_0     <= time_now & mask;
      req_time_0 <= cached_req_time & mask;


      valid_1    <= valid_0;
      has_time_1 <= has_time_0;
      time_stb_1 <= time_stb_0;
      on_time_1  <= req_time_0 == time_0;
      late_1     <= req_time_0 <  time_0;


      pending  <= valid_1;
      has_time <= has_time_1;
      on_time  <= valid_1 && has_time_1 && time_stb_1 && on_time_1;
      late     <= valid_1 && has_time_1 && time_stb_1 && late_1;
    end
  end


  assign exec    = pending && (!has_time || on_time || (EXEC_LATE_CMDS && late));
  assign consume = exec || late;

  assign m_ctrlport_req_wr      = cached_req_wr & exec;
  assign m_ctrlport_req_rd      = cached_req_rd & exec;
  assign m_ctrlport_req_addr    = cached_req_addr;
  assign m_ctrlport_req_data    = cached_req_data;
  assign m_ctrlport_req_byte_en = cached_req_byte_en;

  wire [1:0] resp_status = (late && !exec) ? AXIS_CTRL_STS_TSERR : m_ctrlport_resp_status;
  axi_fifo_flop #(.WIDTH(2+32)) resp_cache_i (
    .clk(clk), .reset(rst), .clear(1'b0),
    .i_tdata({resp_status, m_ctrlport_resp_data}),
    .i_tvalid(m_ctrlport_resp_ack || (late && !exec)), .i_tready(),
    .o_tdata({s_ctrlport_resp_status, s_ctrlport_resp_data}),
    .o_tvalid(s_ctrlport_resp_ack), .o_tready(s_ctrlport_resp_ack),
    .occupied(), .space()
  );

endmodule