data/full_repos/permissive/216210370/soc/rtc.v
1: b"%Error: data/full_repos/permissive/216210370/soc/rtc.v:892: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.v\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:510: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:469: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:409: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:197: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module rtc_clk_div(
  cnt_en,
  i_rtc_ext_clk,
  pclk,
  presetn,
  rtc_clk,
  rtcclkdivcfg,
  test_mode
);
input           cnt_en;       
input           i_rtc_ext_clk; 
input           pclk;         
input           presetn;      
input   [19:0]  rtcclkdivcfg; 
input           test_mode;    
output          rtc_clk;      
reg     [19:0]  cnt;          
wire            cntEq0;       
wire            cnt_en;       
wire            gate_en;      
wire            i_rtc_ext_clk; 
wire            pclk;         
wire            presetn;      
wire            rtc_clk;      
wire            rtc_clk_div;  
wire    [19:0]  rtcclkdivcfg; 
wire            test_mode;    
assign cntEq0 = cnt[19:0] == rtcclkdivcfg[19:0];
always @(posedge i_rtc_ext_clk or negedge presetn)
begin
	if(~presetn)
		cnt[19:0] <= 20'b0;
	else if(cntEq0)
		cnt[19:0] <= 20'b0;
	else if(cnt_en)
		cnt[19:0] <= cnt[19:0] + 20'b1;
end
assign gate_en = cntEq0;
gated_clk_cell  x_gatecell (
  .clk_in               (i_rtc_ext_clk       ),
  .clk_out              (rtc_clk_div         ),
  .external_en          (gate_en             ),
  .global_en            (1'b0                ),
  .local_en             (1'b0                ),
  .module_en            (1'b0                ),
  .pad_yy_gate_clk_en_b (1'b0                ),
  .pad_yy_test_mode     (test_mode           )
);
assign rtc_clk = test_mode ? pclk : rtc_clk_div;
endmodule
module rtc_clk_div(
  cnt_en,
  i_rtc_ext_clk,
  pclk,
  presetn,
  rtc_clk,
  rtcclkdivcfg,
  test_mode
);

input           cnt_en;       
input           i_rtc_ext_clk; 
input           pclk;         
input           presetn;      
input   [19:0]  rtcclkdivcfg; 
input           test_mode;    
output          rtc_clk;      
reg     [19:0]  cnt;          
wire            cntEq0;       
wire            cnt_en;       
wire            gate_en;      
wire            i_rtc_ext_clk; 
wire            pclk;         
wire            presetn;      
wire            rtc_clk;      
wire            rtc_clk_div;  
wire    [19:0]  rtcclkdivcfg; 
wire            test_mode;    
assign cntEq0 = cnt[19:0] == rtcclkdivcfg[19:0];
always @(posedge i_rtc_ext_clk or negedge presetn)
begin
	if(~presetn)
		cnt[19:0] <= 20'b0;
	else if(cntEq0)
		cnt[19:0] <= 20'b0;
	else if(cnt_en)
		cnt[19:0] <= cnt[19:0] + 20'b1;
end
assign gate_en = cntEq0;
gated_clk_cell  x_gatecell (
  .clk_in               (i_rtc_ext_clk       ),
  .clk_out              (rtc_clk_div         ),
  .external_en          (gate_en             ),
  .global_en            (1'b0                ),
  .local_en             (1'b0                ),
  .module_en            (1'b0                ),
  .pad_yy_gate_clk_en_b (1'b0                ),
  .pad_yy_test_mode     (test_mode           )
);
assign rtc_clk = test_mode ? pclk : rtc_clk_div;
endmodule