data/full_repos/permissive/123690745/GCS.v
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data/verilator_xmls/7d1cd227-9939-408b-bd1c-2f0ba78ca479.xml
module GCS(
	 input nop,
    input addu,
    input subu,
    input ori,
    input lui,
    input jal,
	 input jalr,
	 input j,
    input jr,
	 input sll,
	 input srl,
	 input and0,
	 input or0,
	 input slt,
	 input sltu,
	 input sra,
	 input sllv,
	 input srlv,
	 input srav,
	 input xor0,
	 input nor0,
	 
	 input addiu,
	 input xori,
	 input slti,
	 input sltiu,
	 input andi,
	 
	 input beq,
	 input bne,
	 input blez,
	 input bgtz,
	 input bltz,
	 input bgez,
	 input bltzall, 
	 
	 input lw,
	 input lb,
	 input lbu,
	 input lh,
	 input lhu,
	 
	 input sw,
	 input sb,
	 input sh,
	 
	 input mult,
	 input multu,
	 input div,
	 input divu,

	 input mfhi,
	 input mflo,
	 input mthi,
	 input mtlo,
	 
	 input ins,
	 input ext,
	 
	 input lwl,
	 input lwr,
	 
	 input add,
	 input sub,
	 input addi,
	 
	 input eret,
	 input mfc0,
	 input mtc0,
	 
	 output Shift,
    output GRFWE,
    output RAMWE,
    output GRFA3Select,
    output GRFWDSelect,
    output ALUBSelect,
    output [3:0] ALUOP,
	 output ExtSign,
	 output ALUASelect,
	 output Branch,

	 output RsDSelect,
	 output RtDSelect,
	 output RdDSelect,
	 output RD1DSelect,
	 output RD2DSelect,
	 
	 output [1:0] MemType,
	 output LoadExtSign,
	 
	 output Start,
	 output MDSign,
	 output MD,
	 
	 output [1:0] ALUOutESelect,
	 
	 output MDUse,
	 output HLWrite,
	 
	 output LeftRight,
	 
	 output OverflowCheck,
	 
	 output CP0Write,
	 output CP0Read,
	 output EXLClear,
	 output CancelF
    );

	wire calR = addu || subu || slt || sltu || sll || srl || sra || sllv || srlv || srav || xor0 || nor0 || add || sub;
	wire calI = addiu || ext || xori || slti || sltiu || andi || addi;
	wire beqType = beq || bne || blez || bgtz || bltz || bgez || bltzall;
	wire store = sw || sh || sb;
	wire load = lw || lb || lbu || lh || lhu || lwl || lwr || mfc0;
	wire mf = mfhi || mflo;



	 
	assign ALUOutESelect =  mfhi ? 1:
									mflo ? 2: 0;
	
	assign Start = mult || multu || div || divu;
	assign MDSign = mult || div;
	assign MD = div || divu || mtlo;
	assign HLWrite = mthi || mtlo;
	assign MDUse = mult || multu || div || divu || mfhi || mflo || mthi || mtlo;
	
	 
	assign Shift = sll || srl || sra; 
	assign GRFWE = addu||subu||ori||lui||jal||and0||or0||jalr||bltzall||calR||calI||load||mf||ins;
	assign RAMWE = store;

	assign GRFA3Select = addu||subu||sll||srl||and0||or0||jal||jalr||bltzall||calR||mf;




	assign GRFWDSelect = load;

	
	assign ALUBSelect = load||store||lui||ori||calI;

	assign ExtSign = beqType||load||store||addiu||addi||slti||sltiu;
	assign LoadExtSign = lb || lh;


	assign ALUOP[0] = jal || bltzall || jalr || beq || subu || sub || sll || sllv || and0 || andi || slt || slti || sra || srav || nor0 || ext;
	assign ALUOP[1] = jal || bltzall || jalr || ori || or0 || srl || srlv || and0 || andi || slt || slti || xor0 || xori || nor0;
	assign ALUOP[2] = lui || sll || sllv || srl || srlv || slt || slti || ins || ext;
	assign ALUOP[3] = sltu || sltiu || sra || srav || xor0 || xori || nor0 || ins || ext;

	assign ALUASelect = sll || srl;

	assign Branch = beqType || jal || jr || j || jalr;

	assign RsDSelect = jal;
	assign RtDSelect = jal || bltzall;
	assign RdDSelect = jal || bltzall;
	assign RD1DSelect = jal || jalr || bltzall || mf;
	assign RD2DSelect = jal || jalr || bltzall || mf;
	
	assign MemType = (sw || lw) ? 2'b00:
						  (sh || lh || lhu)? 2'b01:
						  (lwl || lwr)? 2'b10:
						  2'b11;
						  
	assign LeftRight = lwr;
	assign OverflowCheck = add || sub || addi;

	assign CP0Write = mtc0;
	assign CP0Read  = mfc0;
	assign CancelF = eret;
	assign EXLClear = eret;
	
endmodule
module GCS(
	 input nop,
    input addu,
    input subu,
    input ori,
    input lui,
    input jal,
	 input jalr,
	 input j,
    input jr,
	 input sll,
	 input srl,
	 input and0,
	 input or0,
	 input slt,
	 input sltu,
	 input sra,
	 input sllv,
	 input srlv,
	 input srav,
	 input xor0,
	 input nor0,
	 
	 input addiu,
	 input xori,
	 input slti,
	 input sltiu,
	 input andi,
	 
	 input beq,
	 input bne,
	 input blez,
	 input bgtz,
	 input bltz,
	 input bgez,
	 input bltzall, 
	 
	 input lw,
	 input lb,
	 input lbu,
	 input lh,
	 input lhu,
	 
	 input sw,
	 input sb,
	 input sh,
	 
	 input mult,
	 input multu,
	 input div,
	 input divu,

	 input mfhi,
	 input mflo,
	 input mthi,
	 input mtlo,
	 
	 input ins,
	 input ext,
	 
	 input lwl,
	 input lwr,
	 
	 input add,
	 input sub,
	 input addi,
	 
	 input eret,
	 input mfc0,
	 input mtc0,
	 
	 output Shift,
    output GRFWE,
    output RAMWE,
    output GRFA3Select,
    output GRFWDSelect,
    output ALUBSelect,
    output [3:0] ALUOP,
	 output ExtSign,
	 output ALUASelect,
	 output Branch,

	 output RsDSelect,
	 output RtDSelect,
	 output RdDSelect,
	 output RD1DSelect,
	 output RD2DSelect,
	 
	 output [1:0] MemType,
	 output LoadExtSign,
	 
	 output Start,
	 output MDSign,
	 output MD,
	 
	 output [1:0] ALUOutESelect,
	 
	 output MDUse,
	 output HLWrite,
	 
	 output LeftRight,
	 
	 output OverflowCheck,
	 
	 output CP0Write,
	 output CP0Read,
	 output EXLClear,
	 output CancelF
    );


	wire calR = addu || subu || slt || sltu || sll || srl || sra || sllv || srlv || srav || xor0 || nor0 || add || sub;
	wire calI = addiu || ext || xori || slti || sltiu || andi || addi;
	wire beqType = beq || bne || blez || bgtz || bltz || bgez || bltzall;
	wire store = sw || sh || sb;
	wire load = lw || lb || lbu || lh || lhu || lwl || lwr || mfc0;
	wire mf = mfhi || mflo;



	 
	assign ALUOutESelect =  mfhi ? 1:
									mflo ? 2: 0;
	
	assign Start = mult || multu || div || divu;
	assign MDSign = mult || div;
	assign MD = div || divu || mtlo;
	assign HLWrite = mthi || mtlo;
	assign MDUse = mult || multu || div || divu || mfhi || mflo || mthi || mtlo;
	
	 
	assign Shift = sll || srl || sra; 
	assign GRFWE = addu||subu||ori||lui||jal||and0||or0||jalr||bltzall||calR||calI||load||mf||ins;
	assign RAMWE = store;

	assign GRFA3Select = addu||subu||sll||srl||and0||or0||jal||jalr||bltzall||calR||mf;




	assign GRFWDSelect = load;

	
	assign ALUBSelect = load||store||lui||ori||calI;

	assign ExtSign = beqType||load||store||addiu||addi||slti||sltiu;
	assign LoadExtSign = lb || lh;


	assign ALUOP[0] = jal || bltzall || jalr || beq || subu || sub || sll || sllv || and0 || andi || slt || slti || sra || srav || nor0 || ext;
	assign ALUOP[1] = jal || bltzall || jalr || ori || or0 || srl || srlv || and0 || andi || slt || slti || xor0 || xori || nor0;
	assign ALUOP[2] = lui || sll || sllv || srl || srlv || slt || slti || ins || ext;
	assign ALUOP[3] = sltu || sltiu || sra || srav || xor0 || xori || nor0 || ins || ext;

	assign ALUASelect = sll || srl;

	assign Branch = beqType || jal || jr || j || jalr;

	assign RsDSelect = jal;
	assign RtDSelect = jal || bltzall;
	assign RdDSelect = jal || bltzall;
	assign RD1DSelect = jal || jalr || bltzall || mf;
	assign RD2DSelect = jal || jalr || bltzall || mf;
	
	assign MemType = (sw || lw) ? 2'b00:
						  (sh || lh || lhu)? 2'b01:
						  (lwl || lwr)? 2'b10:
						  2'b11;
						  
	assign LeftRight = lwr;
	assign OverflowCheck = add || sub || addi;

	assign CP0Write = mtc0;
	assign CP0Read  = mfc0;
	assign CancelF = eret;
	assign EXLClear = eret;
	
endmodule