data/full_repos/permissive/136510272/projects/05_nes/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:34: Operator OR expects 9 bits on the LHS, but LHS\'s VARREF \'A\' generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b0000: R = A | B;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:34: Operator OR expects 9 bits on the RHS, but RHS\'s VARREF \'B\' generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b0000: R = A | B;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:35: Operator AND expects 9 bits on the LHS, but LHS\'s VARREF \'A\' generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b0001: R = A & B;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:35: Operator AND expects 9 bits on the RHS, but RHS\'s VARREF \'B\' generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b0001: R = A & B;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:36: Operator XOR expects 9 bits on the LHS, but LHS\'s VARREF \'A\' generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b0010: R = A ^ B;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:36: Operator XOR expects 9 bits on the RHS, but RHS\'s VARREF \'B\' generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b0010: R = A ^ B;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:37: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'Cin\' generates 1 bits.\n                                                                             : ... In instance alu\n          4\'b0011: R = A + B + Cin;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:38: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'A\' generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b0100: R = A;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:39: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'B\' generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b0101: R = B;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:41: Operator SUB expects 9 bits on the RHS, but RHS\'s LOGNOT generates 1 bits.\n                                                                             : ... In instance alu\n          4\'b0111: R = A - B - !Cin;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:42: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b1000: R = {B[6:0], 1\'b0};\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:43: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b1001: R = {B[6:0], P[0]};\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:44: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b1010: R = {1\'b0, B[7:1]};\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:45: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b1011: R = {P[0], B[7:1]};\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:46: Operator AND expects 9 bits on the LHS, but LHS\'s VARREF \'A\' generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b1101: R = A & B;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/alu.v:46: Operator AND expects 9 bits on the RHS, but RHS\'s VARREF \'B\' generates 8 bits.\n                                                                             : ... In instance alu\n          4\'b1101: R = A & B;\n                         ^\n%Error: Exiting due to 16 warning(s)\n'
module alu(


    input  wire [7:0] A,
    input  wire [7:0] B,
    input  wire [3:0] ALU,
    input  wire [7:0] P,
    input  wire [2:0] OP,
    

    output wire [7:0] AR,
    output reg  [7:0] AF
        
);

assign AR = R[7:0];


reg  [8:0] R; 


wire Zero  = ~|R[7:0];
wire Sign  =  R[7];
wire oADC  = (A[7] ^ B[7] ^ 1'b1) & (A[7] ^ R[7]);
wire oSBC  = (A[7] ^ B[7] ^ 1'b0) & (A[7] ^ R[7]);
wire Cin   =  P[0];
wire Carry =  R[8];

always @* begin


    case (ALU)

4'b0000: R = A | B;
4'b0001: R = A & B;
4'b0010: R = A ^ B;
4'b0011: R = A + B + Cin;
4'b0100: R = A;
4'b0101: R = B;
4'b0110: R = A - B;
4'b0111: R = A - B - !Cin;
4'b1000: R = {B[6:0], 1'b0};
4'b1001: R = {B[6:0], P[0]};
4'b1010: R = {1'b0, B[7:1]};
4'b1011: R = {P[0], B[7:1]};
4'b1101: R = A & B;
4'b1110: R = B - 1;
4'b1111: R = B + 1;

    endcase
    

    casex (ALU) 
        

        4'b000x,
        4'b0010,
        4'b010x,
        4'b111x:
                 AF = {Sign,       P[6:2], Zero, P[0]};
        

        4'b0011: AF = {Sign, oADC, P[5:2], Zero, Carry}; 
        

        4'b0110: AF = {Sign,       P[6:2], Zero, ~Carry};
        

        4'b0111: AF = {Sign, oSBC, P[5:2], Zero, ~Carry};        
        


        4'b100x: AF = {Sign, P[6:2], Zero, B[7]};
        

        4'b101x: AF = {Sign, P[6:2], Zero, B[0]};
        

        4'b1100: casex (OP)
        
3'b00x: AF = {P[7:1], OP[0]};
3'b01x: AF = {P[7:3], OP[0], P[1:0]};
3'b101: AF = {P[7],   1'b0,  P[5:0]};
3'b11x: AF = {P[7:4], OP[0], P[2:0]};
            
        endcase
        

        4'b1101: AF = {B[7:6], P[5:2], Zero, P[0]};
         
    endcase
    
end

endmodule
module alu(


    input  wire [7:0] A,
    input  wire [7:0] B,
    input  wire [3:0] ALU,
    input  wire [7:0] P,
    input  wire [2:0] OP,
    

    output wire [7:0] AR,
    output reg  [7:0] AF
        
);


assign AR = R[7:0];


reg  [8:0] R; 


wire Zero  = ~|R[7:0];
wire Sign  =  R[7];
wire oADC  = (A[7] ^ B[7] ^ 1'b1) & (A[7] ^ R[7]);
wire oSBC  = (A[7] ^ B[7] ^ 1'b0) & (A[7] ^ R[7]);
wire Cin   =  P[0];
wire Carry =  R[8];

always @* begin


    case (ALU)

4'b0000: R = A | B;
4'b0001: R = A & B;
4'b0010: R = A ^ B;
4'b0011: R = A + B + Cin;
4'b0100: R = A;
4'b0101: R = B;
4'b0110: R = A - B;
4'b0111: R = A - B - !Cin;
4'b1000: R = {B[6:0], 1'b0};
4'b1001: R = {B[6:0], P[0]};
4'b1010: R = {1'b0, B[7:1]};
4'b1011: R = {P[0], B[7:1]};
4'b1101: R = A & B;
4'b1110: R = B - 1;
4'b1111: R = B + 1;

    endcase
    

    casex (ALU) 
        

        4'b000x,
        4'b0010,
        4'b010x,
        4'b111x:
                 AF = {Sign,       P[6:2], Zero, P[0]};
        

        4'b0011: AF = {Sign, oADC, P[5:2], Zero, Carry}; 
        

        4'b0110: AF = {Sign,       P[6:2], Zero, ~Carry};
        

        4'b0111: AF = {Sign, oSBC, P[5:2], Zero, ~Carry};        
        


        4'b100x: AF = {Sign, P[6:2], Zero, B[7]};
        

        4'b101x: AF = {Sign, P[6:2], Zero, B[0]};
        

        4'b1100: casex (OP)
        
3'b00x: AF = {P[7:1], OP[0]};
3'b01x: AF = {P[7:3], OP[0], P[1:0]};
3'b101: AF = {P[7],   1'b0,  P[5:0]};
3'b11x: AF = {P[7:4], OP[0], P[2:0]};
            
        endcase
        

        4'b1101: AF = {B[7:6], P[5:2], Zero, P[0]};
         
    endcase
    
end

endmodule