data/full_repos/permissive/143278/vhdl_tests/pr2555831.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/pr2555831.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module buff (out, in);
  parameter SIZE=1;
  output [SIZE-1:0] out;
  input [SIZE-1:0]  in;
  assign out[SIZE-1:0] = in[SIZE-1:0];
endmodule
module buff (out, in);

  parameter SIZE=1;
  output [SIZE-1:0] out;
  input [SIZE-1:0]  in;
  assign out[SIZE-1:0] = in[SIZE-1:0];
endmodule