data/full_repos/permissive/166008742/src/tb_arb_rr.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_arb_rr.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/166008742/src/tb_arb_rr.v:45: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_arb_rr.v:47: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_arb_rr.v:50: syntax error, unexpected \'@\'\n        repeat (10) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/166008742/src/tb_arb_rr.v:53: syntax error, unexpected \'@\'\n        repeat (10) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/166008742/src/tb_arb_rr.v:56: syntax error, unexpected \'@\'\n        repeat (10) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/166008742/src/tb_arb_rr.v:59: syntax error, unexpected \'@\'\n        repeat (10) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/166008742/src/tb_arb_rr.v:62: syntax error, unexpected \'@\'\n        repeat (10) @(posedge clk);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_arb_rr.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: Exiting due to 7 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_arb_rr ();
    parameter PORTS_NUM = 3;

    reg reset;
    reg clk;

    reg  [PORTS_NUM-1:0] req;
    wire [PORTS_NUM-1:0] gnt;

    arb_rr #(PORTS_NUM) dut(
        .reset(reset),
        .clk(clk),

        .req(req),
        .gnt(gnt)
    );

    always begin
        #1;
        clk <= ~clk;
    end

    initial begin
            clk <= 0;
            reset <= 1;
            req <= 0;

        repeat (100) @(posedge clk);
            reset <= 0;
        repeat (100) @(posedge clk);

        req <= 1;
        repeat (10) @(posedge clk);

        req <= 0;
        repeat (10) @(posedge clk);

        req <= 3;
        repeat (10) @(posedge clk);

        req <= 1;
        repeat (10) @(posedge clk);

        req <= 0;
        repeat (10) @(posedge clk);

        #100;
    end

endmodule
module tb_arb_rr ();

    parameter PORTS_NUM = 3;

    reg reset;
    reg clk;

    reg  [PORTS_NUM-1:0] req;
    wire [PORTS_NUM-1:0] gnt;

    arb_rr #(PORTS_NUM) dut(
        .reset(reset),
        .clk(clk),

        .req(req),
        .gnt(gnt)
    );

    always begin
        #1;
        clk <= ~clk;
    end

    initial begin
            clk <= 0;
            reset <= 1;
            req <= 0;

        repeat (100) @(posedge clk);
            reset <= 0;
        repeat (100) @(posedge clk);

        req <= 1;
        repeat (10) @(posedge clk);

        req <= 0;
        repeat (10) @(posedge clk);

        req <= 3;
        repeat (10) @(posedge clk);

        req <= 1;
        repeat (10) @(posedge clk);

        req <= 0;
        repeat (10) @(posedge clk);

        #100;
    end

endmodule