data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/control.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/bd616dbf-0564-49ae-a81a-3b49ad3d8479.xml
module control(
	input clk,
	input rst_n,
	
	input [31:0] instruction,
	
	output reg [1:0] optype,
	output reg [4:0] aluop,
	
	output reg reg_AOM,
	output reg regwe,
	output reg Wr,
	
	output reg memwe,
	
	output reg br,
	output reg j_or_b
);























always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
	end
	else
	begin
	end
end


reg [31:0] inter_instruct;
always@(*)
begin
	inter_instruct=instruction;
	aluop=5'b1;
	case(inter_instruct[31:26])
		6'b000000:
		begin
			if(inter_instruct[10:0]==11'h20)
			begin
				optype=2'h0;
				reg_AOM=1;
				regwe=1;
				memwe=0;
				Wr=0;
				br=0;
			end
		end
		6'b001000:
		begin
			optype=2'h1;
			reg_AOM=1;
			regwe=1;
			memwe=0;
			Wr=0;
			br=0;
		end
		6'b100011:
		begin
			optype=2'h1;
			regwe=1;
			reg_AOM=0;
			memwe=0;
			Wr=0;
			br=0;
		end
		6'b101011:
		begin
			optype=2'h1;
			regwe=0;
			reg_AOM=0;
			memwe=1;
			Wr=1;
			br=0;
		end
		6'b000111:
		begin
			optype=2'h1;
			regwe=0;
			reg_AOM=0;
			memwe=0;
			Wr=0;
			br=1;
			j_or_b=0;
			aluop=5'h7;
		end
		6'b000010:
		begin
			optype=2'h2;
			regwe=0;
			reg_AOM=0;
			memwe=0;
			Wr=0;
			br=1;
			j_or_b=1;
		end
		default:
		begin
			optype=2'h3;
			regwe=0;
			reg_AOM=0;
			memwe=0;
			Wr=0;
			br=0;
		end
	endcase
	
end


endmodule
module control(
	input clk,
	input rst_n,
	
	input [31:0] instruction,
	
	output reg [1:0] optype,
	output reg [4:0] aluop,
	
	output reg reg_AOM,
	output reg regwe,
	output reg Wr,
	
	output reg memwe,
	
	output reg br,
	output reg j_or_b
);
























always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
	end
	else
	begin
	end
end


reg [31:0] inter_instruct;
always@(*)
begin
	inter_instruct=instruction;
	aluop=5'b1;
	case(inter_instruct[31:26])
		6'b000000:
		begin
			if(inter_instruct[10:0]==11'h20)
			begin
				optype=2'h0;
				reg_AOM=1;
				regwe=1;
				memwe=0;
				Wr=0;
				br=0;
			end
		end
		6'b001000:
		begin
			optype=2'h1;
			reg_AOM=1;
			regwe=1;
			memwe=0;
			Wr=0;
			br=0;
		end
		6'b100011:
		begin
			optype=2'h1;
			regwe=1;
			reg_AOM=0;
			memwe=0;
			Wr=0;
			br=0;
		end
		6'b101011:
		begin
			optype=2'h1;
			regwe=0;
			reg_AOM=0;
			memwe=1;
			Wr=1;
			br=0;
		end
		6'b000111:
		begin
			optype=2'h1;
			regwe=0;
			reg_AOM=0;
			memwe=0;
			Wr=0;
			br=1;
			j_or_b=0;
			aluop=5'h7;
		end
		6'b000010:
		begin
			optype=2'h2;
			regwe=0;
			reg_AOM=0;
			memwe=0;
			Wr=0;
			br=1;
			j_or_b=1;
		end
		default:
		begin
			optype=2'h3;
			regwe=0;
			reg_AOM=0;
			memwe=0;
			Wr=0;
			br=0;
		end
	endcase
	
end


endmodule