data/full_repos/permissive/161029703/src/uma/L2Cache/LoadManager.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161029703/src/uma/L2Cache/LoadManager.v:50: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'mem_raddr\' generates 8 bits.\n                                                                                     : ... In instance LoadManager\n            addr_prev <= mem_raddr;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161029703/src/uma/L2Cache/LoadManager.v:52: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'mem_raddr\' generates 8 bits.\n                                                                                     : ... In instance LoadManager\n            addr_prev <= mem_raddr;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/161029703/src/uma/L2Cache/LoadManager.v:53: Operator NEQ expects 32 bits on the RHS, but RHS\'s VARREF \'mem_raddr\' generates 8 bits.\n                                                                                     : ... In instance LoadManager\n            if (addr_prev != mem_raddr)\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/161029703/src/uma/L2Cache/LoadManager.v:66: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'mem_raddr\' generates 8 bits.\n                                                                                     : ... In instance LoadManager\n            if (mem_raddr != addr_prev)\n                          ^~\n%Error: Exiting due to 4 warning(s)\n'
module LoadManager(clk, reset, 
                   wtrig, rtrig, physical_addr, group_addr,
                   bus_rreq, bus_wreq, bus_acc, bus_addr, bus_rdata, bus_wdata, bus_busy,
                   mem_wreq, mem_raddr, mem_waddr, mem_rdata, mem_wdata,
                   fault, finish);
    
	input wire clk, reset;
    

	input wire rtrig, wtrig;
	input wire [31:0] physical_addr;
	input wire [7:0] group_addr;
	

	output reg  bus_rreq, bus_wreq;
	output wire [31:0] bus_addr;
	output wire [31:0] bus_wdata;
	input  wire [31:0] bus_rdata;
	input  wire bus_acc, bus_busy;
    

	output reg  mem_wreq;
	output reg  [7:0] mem_raddr, mem_waddr;
	output reg  [31:0] mem_wdata;
	input  wire [31:0] mem_rdata;
    

	output reg fault;
	output reg finish;
	
    reg  enable_output;
    wire [31:0] bus_wdata_internal;
    reg  [31:0] bus_addr_internal;
    assign bus_addr = enable_output ? bus_addr_internal : 32'h0;
    assign bus_wdata = enable_output ? bus_wdata_internal : 32'h0;
    




    reg [31:0] addr_prev;
    reg [31:0] data_reg;
    reg        use_latch;
    assign bus_wdata_internal = use_latch ? data_reg : mem_rdata;
    always @(posedge clk) begin
        if (reset) begin
            addr_prev <= mem_raddr;
        end else begin
            addr_prev <= mem_raddr;
            if (addr_prev != mem_raddr)
                use_latch <= 1'b0;
            else    
                use_latch <= 1'b1;
        end
    end
    

    reg cur_read;
    always @(posedge clk) begin
        if (reset) begin
            cur_read <= 1'b0;
        end else begin
            if (mem_raddr != addr_prev)
                cur_read <= 1'b1;
            else
                cur_read <= 1'b0;

            if (cur_read) begin
                data_reg <= mem_rdata;
            end
        end
    end
        
    

    `define LOADER_STATE_IDLE 4'h0
	`define LOADER_STATE_WRITE_REQ1 4'h1
    `define LOADER_STATE_WRITE_REQ2 4'h2
	`define LOADER_STATE_WRITE 4'h3
	`define LOADER_STATE_READ_REQ1 4'h5
    `define LOADER_STATE_READ_REQ2 4'h6
 	`define LOADER_STATE_READ 4'h7
    `define LOADER_STATE_WAIT   4'h8
	`define LOADER_STATE_FINISH 4'h9
    
	reg [3:0] state;
	reg [31:0] physical_addr_latch;
	reg [7:0] group_addr_latch;
	reg [7:0] read_ptr;

	always @(posedge clk) begin
		if (reset) begin
			state <= `LOADER_STATE_IDLE;
			bus_wreq <= 1'b0;
			bus_rreq <= 1'b0;
			mem_wreq <= 1'b0;
            finish <= 1'b0;
            enable_output <= 1'b0;
		end else begin
			case (state)
			`LOADER_STATE_IDLE: begin
				if (rtrig | wtrig) begin
					physical_addr_latch <= {physical_addr[31:6], 6'h0};
					group_addr_latch <= {group_addr[7:4], 4'h0};
					if (wtrig) begin
						state <= `LOADER_STATE_WRITE_REQ1;
						bus_wreq <= 1'b1;
						mem_raddr <= {group_addr[7:4], 4'h0};
					end else begin
						state <= `LOADER_STATE_READ_REQ1;
						bus_rreq <= 1'b1;
					end
				end
			end
			`LOADER_STATE_WRITE_REQ1: begin
                mem_raddr <= mem_raddr + 8'h1;
                state <= `LOADER_STATE_WRITE_REQ2;
			end
            `LOADER_STATE_WRITE_REQ2: begin
            	if (bus_acc) begin
					state <= `LOADER_STATE_WRITE;
					bus_addr_internal <= physical_addr_latch;
					mem_raddr <= mem_raddr + 8'h1;
                    enable_output <= 1'b1;
				end
            end
			`LOADER_STATE_WRITE: begin
				if ((bus_addr_internal[5:2] == 4'h0) | ~bus_busy) begin
                    mem_raddr <= mem_raddr + 8'h1;
                    bus_addr_internal <= bus_addr_internal + 32'd4;
                end
                if (bus_addr_internal[5:2] == 4'hE & ~bus_busy) begin
                    bus_wreq <= 1'b0;
                    state <= `LOADER_STATE_WAIT;
                end
			end
            `LOADER_STATE_READ_REQ1: begin
                if (bus_acc) begin
                    state <= `LOADER_STATE_READ_REQ2;
                    bus_addr_internal <= physical_addr_latch;
                    read_ptr <= group_addr_latch;
                    enable_output <= 1'b1;
                end 
             end    
			`LOADER_STATE_READ_REQ2: begin
                bus_addr_internal <= bus_addr_internal + 32'h4;
                state <= `LOADER_STATE_READ;
			end
			`LOADER_STATE_READ: begin
                if (~bus_busy) begin
                    read_ptr <= read_ptr + 8'h1;
                    mem_wreq <= 1'b1;
                    mem_wdata <= bus_rdata;
                    mem_waddr <= read_ptr;
                    if (read_ptr[3:0] == 4'hF) begin
                        state <= `LOADER_STATE_WAIT;
                    end
                end else begin
                    mem_wreq <= 1'b0;
                end
                
                if (bus_addr_internal[5:2] == 4'hE) begin
                    bus_rreq <= 1'b0;
                end
                if (bus_addr_internal[5:2] != 4'hF) begin
                    bus_addr_internal <= bus_addr_internal + 32'h4;
                end
			end
            `LOADER_STATE_WAIT: begin
                mem_wreq <= 1'b0;


                if (~bus_acc) begin
                    finish <= 1'b1;
                    state <= `LOADER_STATE_FINISH;
                    enable_output <= 1'b0;
                end
            end
			`LOADER_STATE_FINISH: begin
                finish <= 1'b0;
                state <= `LOADER_STATE_IDLE;
			end
			endcase
		end
	end
	

    `define LOADER_MAX_TIMEOUT 32'd10000000
	reg [31:0] watch_dog;
	always @(posedge clk) begin
		if (reset) begin
			watch_dog <= 32'd0;
			fault <= 1'b0;
		end else begin
			if (state == `LOADER_STATE_IDLE) begin
				watch_dog <= 32'd0;
			end else if(watch_dog == `LOADER_MAX_TIMEOUT) begin
				fault <= 1'b1;
				watch_dog <= 32'd0;
			end else begin
				watch_dog <= watch_dog + 32'd1;
			end
		end
	end

endmodule
module LoadManager(clk, reset, 
                   wtrig, rtrig, physical_addr, group_addr,
                   bus_rreq, bus_wreq, bus_acc, bus_addr, bus_rdata, bus_wdata, bus_busy,
                   mem_wreq, mem_raddr, mem_waddr, mem_rdata, mem_wdata,
                   fault, finish);

    
	input wire clk, reset;
    

	input wire rtrig, wtrig;
	input wire [31:0] physical_addr;
	input wire [7:0] group_addr;
	

	output reg  bus_rreq, bus_wreq;
	output wire [31:0] bus_addr;
	output wire [31:0] bus_wdata;
	input  wire [31:0] bus_rdata;
	input  wire bus_acc, bus_busy;
    

	output reg  mem_wreq;
	output reg  [7:0] mem_raddr, mem_waddr;
	output reg  [31:0] mem_wdata;
	input  wire [31:0] mem_rdata;
    

	output reg fault;
	output reg finish;
	
    reg  enable_output;
    wire [31:0] bus_wdata_internal;
    reg  [31:0] bus_addr_internal;
    assign bus_addr = enable_output ? bus_addr_internal : 32'h0;
    assign bus_wdata = enable_output ? bus_wdata_internal : 32'h0;
    




    reg [31:0] addr_prev;
    reg [31:0] data_reg;
    reg        use_latch;
    assign bus_wdata_internal = use_latch ? data_reg : mem_rdata;
    always @(posedge clk) begin
        if (reset) begin
            addr_prev <= mem_raddr;
        end else begin
            addr_prev <= mem_raddr;
            if (addr_prev != mem_raddr)
                use_latch <= 1'b0;
            else    
                use_latch <= 1'b1;
        end
    end
    

    reg cur_read;
    always @(posedge clk) begin
        if (reset) begin
            cur_read <= 1'b0;
        end else begin
            if (mem_raddr != addr_prev)
                cur_read <= 1'b1;
            else
                cur_read <= 1'b0;

            if (cur_read) begin
                data_reg <= mem_rdata;
            end
        end
    end
        
    

    `define LOADER_STATE_IDLE 4'h0
	`define LOADER_STATE_WRITE_REQ1 4'h1
    `define LOADER_STATE_WRITE_REQ2 4'h2
	`define LOADER_STATE_WRITE 4'h3
	`define LOADER_STATE_READ_REQ1 4'h5
    `define LOADER_STATE_READ_REQ2 4'h6
 	`define LOADER_STATE_READ 4'h7
    `define LOADER_STATE_WAIT   4'h8
	`define LOADER_STATE_FINISH 4'h9
    
	reg [3:0] state;
	reg [31:0] physical_addr_latch;
	reg [7:0] group_addr_latch;
	reg [7:0] read_ptr;

	always @(posedge clk) begin
		if (reset) begin
			state <= `LOADER_STATE_IDLE;
			bus_wreq <= 1'b0;
			bus_rreq <= 1'b0;
			mem_wreq <= 1'b0;
            finish <= 1'b0;
            enable_output <= 1'b0;
		end else begin
			case (state)
			`LOADER_STATE_IDLE: begin
				if (rtrig | wtrig) begin
					physical_addr_latch <= {physical_addr[31:6], 6'h0};
					group_addr_latch <= {group_addr[7:4], 4'h0};
					if (wtrig) begin
						state <= `LOADER_STATE_WRITE_REQ1;
						bus_wreq <= 1'b1;
						mem_raddr <= {group_addr[7:4], 4'h0};
					end else begin
						state <= `LOADER_STATE_READ_REQ1;
						bus_rreq <= 1'b1;
					end
				end
			end
			`LOADER_STATE_WRITE_REQ1: begin
                mem_raddr <= mem_raddr + 8'h1;
                state <= `LOADER_STATE_WRITE_REQ2;
			end
            `LOADER_STATE_WRITE_REQ2: begin
            	if (bus_acc) begin
					state <= `LOADER_STATE_WRITE;
					bus_addr_internal <= physical_addr_latch;
					mem_raddr <= mem_raddr + 8'h1;
                    enable_output <= 1'b1;
				end
            end
			`LOADER_STATE_WRITE: begin
				if ((bus_addr_internal[5:2] == 4'h0) | ~bus_busy) begin
                    mem_raddr <= mem_raddr + 8'h1;
                    bus_addr_internal <= bus_addr_internal + 32'd4;
                end
                if (bus_addr_internal[5:2] == 4'hE & ~bus_busy) begin
                    bus_wreq <= 1'b0;
                    state <= `LOADER_STATE_WAIT;
                end
			end
            `LOADER_STATE_READ_REQ1: begin
                if (bus_acc) begin
                    state <= `LOADER_STATE_READ_REQ2;
                    bus_addr_internal <= physical_addr_latch;
                    read_ptr <= group_addr_latch;
                    enable_output <= 1'b1;
                end 
             end    
			`LOADER_STATE_READ_REQ2: begin
                bus_addr_internal <= bus_addr_internal + 32'h4;
                state <= `LOADER_STATE_READ;
			end
			`LOADER_STATE_READ: begin
                if (~bus_busy) begin
                    read_ptr <= read_ptr + 8'h1;
                    mem_wreq <= 1'b1;
                    mem_wdata <= bus_rdata;
                    mem_waddr <= read_ptr;
                    if (read_ptr[3:0] == 4'hF) begin
                        state <= `LOADER_STATE_WAIT;
                    end
                end else begin
                    mem_wreq <= 1'b0;
                end
                
                if (bus_addr_internal[5:2] == 4'hE) begin
                    bus_rreq <= 1'b0;
                end
                if (bus_addr_internal[5:2] != 4'hF) begin
                    bus_addr_internal <= bus_addr_internal + 32'h4;
                end
			end
            `LOADER_STATE_WAIT: begin
                mem_wreq <= 1'b0;


                if (~bus_acc) begin
                    finish <= 1'b1;
                    state <= `LOADER_STATE_FINISH;
                    enable_output <= 1'b0;
                end
            end
			`LOADER_STATE_FINISH: begin
                finish <= 1'b0;
                state <= `LOADER_STATE_IDLE;
			end
			endcase
		end
	end
	

    `define LOADER_MAX_TIMEOUT 32'd10000000
	reg [31:0] watch_dog;
	always @(posedge clk) begin
		if (reset) begin
			watch_dog <= 32'd0;
			fault <= 1'b0;
		end else begin
			if (state == `LOADER_STATE_IDLE) begin
				watch_dog <= 32'd0;
			end else if(watch_dog == `LOADER_MAX_TIMEOUT) begin
				fault <= 1'b1;
				watch_dog <= 32'd0;
			end else begin
				watch_dog <= watch_dog + 32'd1;
			end
		end
	end

endmodule