data/full_repos/permissive/143278/ivltests/pr1841300.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1841300.v:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 5 bits.\n                                                                        : ... In instance test\n      b = $signed(a);\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1841300.v:10: Operator FUNCREF \'_$Finv5\' expects 5 bits on the Function Argument, but Function Argument\'s CONST \'32\'hab\' generates 32 bits.\n                                                                         : ... In instance test\n      c = $signed(_$Finv5(32\'hab));\n                  ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1841300.v:10: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 5 bits.\n                                                                         : ... In instance test\n      c = $signed(_$Finv5(32\'hab));\n        ^\n%Error: Exiting due to 3 warning(s)\n'
module test;
   reg[4:0] a;
   reg [31:0] b, c;
   initial begin
      a = 5'b10100;
      b = $signed(a);
      c = $signed(_$Finv5(32'hab));
      $display("a is '%h'; b is '%h'; c is '%h'", a, b, c);
   end
   function [4:0] _$Finv5;
      input l;
      reg [4:0] l;
      _$Finv5 = ~l;
   endfunction
endmodule
module test;

   reg[4:0] a;
   reg [31:0] b, c;
   initial begin
      a = 5'b10100;
      b = $signed(a);
      c = $signed(_$Finv5(32'hab));
      $display("a is '%h'; b is '%h'; c is '%h'", a, b, c);
   end
   function [4:0] _$Finv5;
      input l;
      reg [4:0] l;
      _$Finv5 = ~l;
   endfunction
endmodule