data/full_repos/permissive/220262286/src/decoder.v
1: b'%Error: data/full_repos/permissive/220262286/src/decoder.v:1: Cannot find include file: include/define.v\n`include "include/define.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220262286/src,data/full_repos/permissive/220262286/include/define.v\n             data/full_repos/permissive/220262286/src,data/full_repos/permissive/220262286/include/define.v.v\n             data/full_repos/permissive/220262286/src,data/full_repos/permissive/220262286/include/define.v.sv\n             include/define.v\n             include/define.v.v\n             include/define.v.sv\n             obj_dir/include/define.v\n             obj_dir/include/define.v.v\n             obj_dir/include/define.v.sv\n%Error: data/full_repos/permissive/220262286/src/decoder.v:32: Define or directive not defined: \'`ALU_OP_ADD\'\n            alu_op = `ALU_OP_ADD;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220262286/src/decoder.v:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            alu_op = `ALU_OP_ADD;\n                                ^\n%Error: Exiting due to 3 error(s)\n'
module DECODER(
    input [5:0] ins_op,
    input [5:0] func_code,
    output reg reg_dst,
    output reg alu_src,
    output reg mem_to_reg,
    output reg reg_write,
    output reg mem_read,
    output reg mem_write,
    output reg branch,
    output reg jmp,
    output reg [2:0] alu_op
);

always @* begin
    reg_dst = 1'b0;
    alu_src = 1'b0;
    mem_to_reg = 1'b0;
    reg_write = 1'b0;
    mem_read = 1'b0;
    mem_write = 1'b0;
    branch = 1'b0;
    jmp = 1'b0;
    alu_op = 4'b000;
    
    case(ins_op)
        8: begin
            alu_src = 1'b1;
            reg_write = 1'b1;
            alu_op = `ALU_OP_ADD;
        end
    endcase
end

endmodule
module DECODER(
    input [5:0] ins_op,
    input [5:0] func_code,
    output reg reg_dst,
    output reg alu_src,
    output reg mem_to_reg,
    output reg reg_write,
    output reg mem_read,
    output reg mem_write,
    output reg branch,
    output reg jmp,
    output reg [2:0] alu_op
);


always @* begin
    reg_dst = 1'b0;
    alu_src = 1'b0;
    mem_to_reg = 1'b0;
    reg_write = 1'b0;
    mem_read = 1'b0;
    mem_write = 1'b0;
    branch = 1'b0;
    jmp = 1'b0;
    alu_op = 4'b000;
    
    case(ins_op)
        8: begin
            alu_src = 1'b1;
            reg_write = 1'b1;
            alu_op = `ALU_OP_ADD;
        end
    endcase
end

endmodule