data/full_repos/permissive/115141190/Init_counter_generator.v
data/verilator_xmls/55b59727-e06a-4ed6-9894-6745a7dd4728.xml
module Init_counter_generator (clk, reset, clk_cnt);
input wire clk, reset;
output wire [19:0]clk_cnt;

reg [19:0]next_clk_cnt;

assign clk_cnt = next_clk_cnt;

always @ (posedge clk or posedge reset)
begin
	if (reset == 1'b1) begin
		next_clk_cnt <= 20'b0;
	end
	else begin
	  	next_clk_cnt <= clk_cnt + 20'd1;
		if (clk_cnt == 20'd964048) begin
		  next_clk_cnt <= 20'd0;
		end
	end
end
endmodule
module Init_counter_generator (clk, reset, clk_cnt);

input wire clk, reset;
output wire [19:0]clk_cnt;

reg [19:0]next_clk_cnt;

assign clk_cnt = next_clk_cnt;

always @ (posedge clk or posedge reset)
begin
	if (reset == 1'b1) begin
		next_clk_cnt <= 20'b0;
	end
	else begin
	  	next_clk_cnt <= clk_cnt + 20'd1;
		if (clk_cnt == 20'd964048) begin
		  next_clk_cnt <= 20'd0;
		end
	end
end
endmodule