data/full_repos/permissive/159001439/src/divider.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:108: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'dividend_i\' generates 16 bits.\n                                                                      : ... In instance divider\n      grand_dividend <= dividend_i << R_PP;\n                                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:112: Operator SHIFTL expects 24 bits on the LHS, but LHS\'s VARREF \'divisor_i\' generates 8 bits.\n                                                                      : ... In instance divider\n      grand_divisor  <= divisor_i << (N_PP+R_PP-S_PP-1);\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:127: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'subtract_node\' generates 25 bits.\n                                                                      : ... In instance divider\n      if (~subtract_node[M_PP+N_PP+R_PP-1]) grand_dividend <= subtract_node;\n                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:143: Operator SUB expects 25 bits on the LHS, but LHS\'s REPLICATE generates 18 bits.\n                                                                      : ... In instance divider\nassign subtract_node = {1\'b0,grand_dividend} - {1\'b0,grand_divisor};\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:148: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s COND generates 17 bits.\n                                                                      : ... In instance divider\nassign quotient_o = (HOLD_OUTPUT == 0)?(quotient>>R_PP):(quotient_reg>>R_PP);\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:149: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 17 bits.\n                                                                      : ... In instance divider\nassign remainder_o = (HOLD_OUTPUT == 0)?quotient:quotient_reg;\n                   ^\n%Error: Exiting due to 6 warning(s)\n'
function integer clogb2 (input integer size);
begin
	size = size - 1;
	for (clogb2=1; size>1; clogb2=clogb2+1)
		size = size >> 1;
end
endfunction
function integer clogb2 (input integer size);

begin
	size = size - 1;
	for (clogb2=1; size>1; clogb2=clogb2+1)
		size = size >> 1;
end
endfunction