data/full_repos/permissive/201488448/3_verification/1_sim/07_comb2.v
data/verilator_xmls/2586598d-4aba-4830-a898-424161852383.xml
module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );

    assign q = ~(a^b^c^d);

endmodule
module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );


    assign q = ~(a^b^c^d);

endmodule