data/full_repos/permissive/200650987/project/display/soc_up/rtl/APB_DEV/URT/uart_top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/200650987/project/display/soc_up/rtl/APB_DEV/URT/uart_top.v:34: Cannot find include file: uart_defines.h\n`include "uart_defines.h" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200650987/project/display/soc_up/rtl/APB_DEV/URT,data/full_repos/permissive/200650987/uart_defines.h\n             data/full_repos/permissive/200650987/project/display/soc_up/rtl/APB_DEV/URT,data/full_repos/permissive/200650987/uart_defines.h.v\n             data/full_repos/permissive/200650987/project/display/soc_up/rtl/APB_DEV/URT,data/full_repos/permissive/200650987/uart_defines.h.sv\n             uart_defines.h\n             uart_defines.h.v\n             uart_defines.h.sv\n             obj_dir/uart_defines.h\n             obj_dir/uart_defines.h.v\n             obj_dir/uart_defines.h.sv\n%Error: Exiting due to 1 error(s)\n'
module UART_TOP(
        PCLK,        PRST_,
        PSEL,        PENABLE,     PADDR,       PWRITE,
        PWDATA,      URT_PRDATA,

        INT, clk_carrier, 
        
        TXD_i, TXD_o, TXD_oe,     
        RXD_i, RXD_o, RXD_oe,
        
        RTS,         CTS,         DSR,
        DCD,         DTR,         RI
    );

input   PCLK,        PRST_;
input   PSEL,        PENABLE,     PWRITE;
input   [7:0]     PADDR;
input   [7:0]     PWDATA;
output  [7:0]     URT_PRDATA;

output  INT;
input   clk_carrier; 

input   TXD_i;
output  TXD_o;
output  TXD_oe;
input   RXD_i;
output  RXD_o;
output  RXD_oe;

output  RTS;
input   CTS,         DSR,         DCD;
output  DTR;
input   RI;

wire prst = !PRST_;
wire we   = PSEL & PENABLE & PWRITE;      
wire re   = PSEL & PENABLE & !PWRITE;               

wire rx_en;
wire tx2rx_en;
wire isomode;

assign  TXD_oe = isomode&&(rx_en||tx2rx_en) ? 1'b1:1'b0;
assign  RXD_oe =~isomode;

uart_regs	regs(
    .clk         (PCLK       ),
    .rst         (prst       ),
    .clk_carrier (clk_carrier),
    .addr        (PADDR[2:0] ),
    .dat_i       (PWDATA     ),
    .dat_o       (URT_PRDATA ),
    .we          (we         ),
    .re          (re         ),
    
    .modem_inputs({ CTS, DSR, RI, DCD }	),
    .rts_pad_o   (RTS      ),
    .dtr_pad_o   (DTR      ),
    .stx_pad_o   (TXD_o	   ),
    .TXD_i       (TXD_i    ),
    .srx_pad_i   (RXD_i    ),
    .RXD_o       (RXD_o    ),
    .int_o       ( INT     ),
    .tx2rx_en    (tx2rx_en ),
    .rx_en       (rx_en    ),
    .usart_mode  (isomode  )

);


endmodule
module UART_TOP(
        PCLK,        PRST_,
        PSEL,        PENABLE,     PADDR,       PWRITE,
        PWDATA,      URT_PRDATA,

        INT, clk_carrier, 
        
        TXD_i, TXD_o, TXD_oe,     
        RXD_i, RXD_o, RXD_oe,
        
        RTS,         CTS,         DSR,
        DCD,         DTR,         RI
    );


input   PCLK,        PRST_;
input   PSEL,        PENABLE,     PWRITE;
input   [7:0]     PADDR;
input   [7:0]     PWDATA;
output  [7:0]     URT_PRDATA;

output  INT;
input   clk_carrier; 

input   TXD_i;
output  TXD_o;
output  TXD_oe;
input   RXD_i;
output  RXD_o;
output  RXD_oe;

output  RTS;
input   CTS,         DSR,         DCD;
output  DTR;
input   RI;

wire prst = !PRST_;
wire we   = PSEL & PENABLE & PWRITE;      
wire re   = PSEL & PENABLE & !PWRITE;               

wire rx_en;
wire tx2rx_en;
wire isomode;

assign  TXD_oe = isomode&&(rx_en||tx2rx_en) ? 1'b1:1'b0;
assign  RXD_oe =~isomode;

uart_regs	regs(
    .clk         (PCLK       ),
    .rst         (prst       ),
    .clk_carrier (clk_carrier),
    .addr        (PADDR[2:0] ),
    .dat_i       (PWDATA     ),
    .dat_o       (URT_PRDATA ),
    .we          (we         ),
    .re          (re         ),
    
    .modem_inputs({ CTS, DSR, RI, DCD }	),
    .rts_pad_o   (RTS      ),
    .dtr_pad_o   (DTR      ),
    .stx_pad_o   (TXD_o	   ),
    .TXD_i       (TXD_i    ),
    .srx_pad_i   (RXD_i    ),
    .RXD_o       (RXD_o    ),
    .int_o       ( INT     ),
    .tx2rx_en    (tx2rx_en ),
    .rx_en       (rx_en    ),
    .usart_mode  (isomode  )

);


endmodule