data/full_repos/permissive/105948944/sources/sync_rebuiltSignal.v
1: b"%Error: data/full_repos/permissive/105948944/sources/sync_rebuiltSignal.v:32: Cannot find file containing module: 'signalSync'\n    signalSync sync_reb0(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync\n             data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync.v\n             data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync.sv\n             signalSync\n             signalSync.v\n             signalSync.sv\n             obj_dir/signalSync\n             obj_dir/signalSync.v\n             obj_dir/signalSync.sv\n%Error: data/full_repos/permissive/105948944/sources/sync_rebuiltSignal.v:48: Cannot find file containing module: 'signalSync'\n    signalSync sync_reb1(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/105948944/sources/sync_rebuiltSignal.v:65: Cannot find file containing module: 'signalSync'\n    signalSync sync_reb2(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/105948944/sources/sync_rebuiltSignal.v:82: Cannot find file containing module: 'signalSync'\n    signalSync sync_reb3(\n    ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module sync_rebuiltSignal(
    input clock,
    input [3:0] sensors,
    output [3:0] rebuiltSignal
    );
    
    reg [3:0] rebuiltSignal_reg;
    wire [3:0] rising_edge_wire;
    wire [3:0] falling_edge_wire;    
    

    signalSync sync_reb0(
        .clock(clock),
        .asynchronous_signal(sensors[0]),
        .rising_edge(rising_edge_wire[0]),
        .falling_edge(falling_edge_wire[0])
    );
    always@(posedge clock) begin
        if (rising_edge_wire[0])
            rebuiltSignal_reg[0] <= 1;
        else if (falling_edge_wire[0])
            rebuiltSignal_reg[0] <= 0; 



    end
    
    signalSync sync_reb1(
        .clock(clock),
        .asynchronous_signal(sensors[1]),
        .rising_edge(rising_edge_wire[1]),
        .falling_edge(falling_edge_wire[1])
    );
    
    always@(posedge clock) begin
        if (rising_edge_wire[1])
            rebuiltSignal_reg[1] <= 1;
        else if (falling_edge_wire[1])
            rebuiltSignal_reg[1] <= 0; 



    end
    
    signalSync sync_reb2(
        .clock(clock),
        .asynchronous_signal(sensors[2]),
        .rising_edge(rising_edge_wire[2]),
        .falling_edge(falling_edge_wire[2])
    );
    
    always@(posedge clock) begin
        if (rising_edge_wire[2])
            rebuiltSignal_reg[2] <= 1;
        else if (falling_edge_wire[2])
            rebuiltSignal_reg[2] <= 0;


 
    end
    
    signalSync sync_reb3(
        .clock(clock),
        .asynchronous_signal(sensors[3]),
        .rising_edge(rising_edge_wire[3]),
        .falling_edge(falling_edge_wire[3])
    );
    
    always@(posedge clock) begin
        if (rising_edge_wire[3])
            rebuiltSignal_reg[3] <= 1;
        else if (falling_edge_wire[3])
            rebuiltSignal_reg[3] <= 0; 


    end
    
    
    assign rebuiltSignal = rebuiltSignal_reg;
endmodule
module sync_rebuiltSignal(
    input clock,
    input [3:0] sensors,
    output [3:0] rebuiltSignal
    );

    
    reg [3:0] rebuiltSignal_reg;
    wire [3:0] rising_edge_wire;
    wire [3:0] falling_edge_wire;    
    

    signalSync sync_reb0(
        .clock(clock),
        .asynchronous_signal(sensors[0]),
        .rising_edge(rising_edge_wire[0]),
        .falling_edge(falling_edge_wire[0])
    );
    always@(posedge clock) begin
        if (rising_edge_wire[0])
            rebuiltSignal_reg[0] <= 1;
        else if (falling_edge_wire[0])
            rebuiltSignal_reg[0] <= 0; 



    end
    
    signalSync sync_reb1(
        .clock(clock),
        .asynchronous_signal(sensors[1]),
        .rising_edge(rising_edge_wire[1]),
        .falling_edge(falling_edge_wire[1])
    );
    
    always@(posedge clock) begin
        if (rising_edge_wire[1])
            rebuiltSignal_reg[1] <= 1;
        else if (falling_edge_wire[1])
            rebuiltSignal_reg[1] <= 0; 



    end
    
    signalSync sync_reb2(
        .clock(clock),
        .asynchronous_signal(sensors[2]),
        .rising_edge(rising_edge_wire[2]),
        .falling_edge(falling_edge_wire[2])
    );
    
    always@(posedge clock) begin
        if (rising_edge_wire[2])
            rebuiltSignal_reg[2] <= 1;
        else if (falling_edge_wire[2])
            rebuiltSignal_reg[2] <= 0;


 
    end
    
    signalSync sync_reb3(
        .clock(clock),
        .asynchronous_signal(sensors[3]),
        .rising_edge(rising_edge_wire[3]),
        .falling_edge(falling_edge_wire[3])
    );
    
    always@(posedge clock) begin
        if (rising_edge_wire[3])
            rebuiltSignal_reg[3] <= 1;
        else if (falling_edge_wire[3])
            rebuiltSignal_reg[3] <= 0; 


    end
    
    
    assign rebuiltSignal = rebuiltSignal_reg;
endmodule