data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_system_subtracter_32.v
 line:35: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_system_subtracter_32.v:30: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD/2) \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_system_subtracter_32.v:35: Unsupported: Ignoring delay on this delayed statement.\n        repeat (10) #500 begin\n                    ^\n%Error: data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_system_subtracter_32.v:21: Cannot find file containing module: \'system_subtracter_32\'\n    system_subtracter_32 utt(\n    ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches,data/full_repos/permissive/212763527/system_subtracter_32\n             data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches,data/full_repos/permissive/212763527/system_subtracter_32.v\n             data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches,data/full_repos/permissive/212763527/system_subtracter_32.sv\n             system_subtracter_32\n             system_subtracter_32.v\n             system_subtracter_32.sv\n             obj_dir/system_subtracter_32\n             obj_dir/system_subtracter_32.v\n             obj_dir/system_subtracter_32.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_system_subtracter_32;

    reg clk;



    reg [31:0] x;
    reg [31:0] y;


    wire [31:0] s;

    initial begin
        clk = 0;
        x = 32'b111;
        y = 32'b101;
    end
    
    system_subtracter_32 utt(

        .CLK (clk),
        .x(x),
        .y(y),
        .s(s)
    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin

        repeat (10) #500 begin
            x = x + 500;
            y = y + 100;
        end
        $finish;
    end

endmodule
module tb_system_subtracter_32;


    reg clk;



    reg [31:0] x;
    reg [31:0] y;


    wire [31:0] s;

    initial begin
        clk = 0;
        x = 32'b111;
        y = 32'b101;
    end
    
    system_subtracter_32 utt(

        .CLK (clk),
        .x(x),
        .y(y),
        .s(s)
    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin

        repeat (10) #500 begin
            x = x + 500;
            y = y + 100;
        end
        $finish;
    end

endmodule