data/full_repos/permissive/162874044/HDL Files/counter.v
 line:59: before: "("
1: b'%Error: Cannot find file containing module: Files,data/full_repos/permissive/162874044\n        ... Looked in:\n             data/full_repos/permissive/162874044/HDL/Files,data/full_repos/permissive/162874044\n             data/full_repos/permissive/162874044/HDL/Files,data/full_repos/permissive/162874044.v\n             data/full_repos/permissive/162874044/HDL/Files,data/full_repos/permissive/162874044.sv\n             Files,data/full_repos/permissive/162874044\n             Files,data/full_repos/permissive/162874044.v\n             Files,data/full_repos/permissive/162874044.sv\n             obj_dir/Files,data/full_repos/permissive/162874044\n             obj_dir/Files,data/full_repos/permissive/162874044.v\n             obj_dir/Files,data/full_repos/permissive/162874044.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/162874044/HDL\n%Error: Cannot find file containing module: Files/counter.v\n%Error: Exiting due to 3 error(s)\n'
module counter


#( parameter busWidth = 4 )
(


	input clock,
	input [ ( busWidth - 1 ) : 0 ] D,

	input masterReset_n,
	input countEnable,
	input parallelEnable_n,
	

	output [ ( busWidth - 1 ) : 0 ] Q,
	output terminalCount

);


	reg [ ( busWidth - 1 ) : 0 ] counterValue;
	

	assign Q 				= counterValue;
	assign terminalCount = &( counterValue );
	


	always @( posedge( clock ), negedge( masterReset_n ) )
		begin	
				

			if ( masterReset_n == 1'b0 )
				begin	
					counterValue <= 0;
				end
				

			else if ( parallelEnable_n == 1'b0 )
				begin
					counterValue  <=  D;
				end
				

			else if ( countEnable == 1'b1 )
				begin
					

					if( ( counterValue == ( 2**( busWidth ) - 1 ) ) )
						begin
							counterValue <= 0;
						end
											

					else
						begin
							counterValue <= counterValue + 1'b1;
						end
			
				end
				

			else 
				begin
					counterValue <= counterValue;
				end
				
				
	end
	

endmodule
module counter


#( parameter busWidth = 4 )
(


	input clock,
	input [ ( busWidth - 1 ) : 0 ] D,

	input masterReset_n,
	input countEnable,
	input parallelEnable_n,
	

	output [ ( busWidth - 1 ) : 0 ] Q,
	output terminalCount

);



	reg [ ( busWidth - 1 ) : 0 ] counterValue;
	

	assign Q 				= counterValue;
	assign terminalCount = &( counterValue );
	


	always @( posedge( clock ), negedge( masterReset_n ) )
		begin	
				

			if ( masterReset_n == 1'b0 )
				begin	
					counterValue <= 0;
				end
				

			else if ( parallelEnable_n == 1'b0 )
				begin
					counterValue  <=  D;
				end
				

			else if ( countEnable == 1'b1 )
				begin
					

					if( ( counterValue == ( 2**( busWidth ) - 1 ) ) )
						begin
							counterValue <= 0;
						end
											

					else
						begin
							counterValue <= counterValue + 1'b1;
						end
			
				end
				

			else 
				begin
					counterValue <= counterValue;
				end
				
				
	end
	

endmodule