data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v
 line:128 column:14: Illegal character '"'
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:43: Cannot find include file: tap_defines.v\n`include "tap_defines.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port,data/full_repos/permissive/17099167/tap_defines.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port,data/full_repos/permissive/17099167/tap_defines.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port,data/full_repos/permissive/17099167/tap_defines.v.sv\n             tap_defines.v\n             tap_defines.v.v\n             tap_defines.v.sv\n             obj_dir/tap_defines.v\n             obj_dir/tap_defines.v.v\n             obj_dir/tap_defines.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:44: Cannot find include file: adbg_defines.v\n`include "adbg_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:45: Cannot find include file: adbg_wb_defines.v\n`include "adbg_wb_defines.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n  #1 test_enabled<=#1 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:178: Define or directive not defined: \'`DEBUG\'\n  set_ir(`DEBUG);\n         ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:195: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n   #200\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:202: Unsupported: Ignoring delay on this delayed statement.\n   #1000; \n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:204: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:225: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:235: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n    #1000 \n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:260: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:261: Unsupported: Ignoring delay on this delayed statement.\n   #200\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:268: Unsupported: Ignoring delay on this delayed statement.\n   #1000; \n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:270: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:296: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:298: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n  select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:306: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:308: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:309: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:324: Unsupported: Ignoring delay on this delayed statement.\n    #1000; \n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:326: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:344: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:346: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:347: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:352: Unsupported: Ignoring delay on this delayed statement.\n     #1000\n     ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:354: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:355: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:361: Unsupported: Ignoring delay on this delayed statement.\n      #1000; \n      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:363: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:390: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE); \n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:400: Unsupported: Ignoring delay on this delayed statement.\n  #1000\n  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:402: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:407: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE); \n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:417: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:419: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n  select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:458: Unsupported: Ignoring delay on this delayed statement.\n     #1000\n     ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:460: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:466: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:465: Unsupported: Ignoring delay on this delayed statement.\n  #1000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:468: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:575: Unsupported: Ignoring delay on this delayed statement.\n     #1000\n     ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:577: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:589: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:588: Unsupported: Ignoring delay on this delayed statement.\n  #1000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:622: Unsupported: Ignoring delay on this delayed statement.\n  #1000\n  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:624: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:636: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:635: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:653: Unsupported: Ignoring delay on this delayed statement.\n     #1000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:667: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:675: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:677: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:690: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:689: Unsupported: Ignoring delay on this delayed statement.\n     #1000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:708: Unsupported: Ignoring delay on this delayed statement.\n      #1000\n      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:725: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:723: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:731: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:730: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:732: Unsupported: Ignoring delay on this delayed statement.\n   #500\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:737: Unsupported: Ignoring delay on this delayed statement.\n   #500\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:745: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:743: Unsupported: Ignoring delay on this delayed statement.\n     #1000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:752: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:757: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:756: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:758: Unsupported: Ignoring delay on this delayed statement.\n   #500\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:763: Unsupported: Ignoring delay on this delayed statement.\n   #500\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:771: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:769: Unsupported: Ignoring delay on this delayed statement.\n     #1000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:777: Unsupported: Ignoring delay on this delayed statement.\n   #1000\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:782: Define or directive not defined: \'`DBG_TOP_WISHBONE_DEBUG_MODULE\'\n   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);\n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:781: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:783: Unsupported: Ignoring delay on this delayed statement.\n   #500\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:788: Unsupported: Ignoring delay on this delayed statement.\n   #500\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:796: Define or directive not defined: \'`DBG_TOP_JSP_DEBUG_MODULE\'\n  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);\n                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:794: Unsupported: Ignoring delay on this delayed statement.\n     #1000\n     ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:953: Define or directive not defined: \'`IDCODE\'\n    set_ir(`IDCODE);\n           ^~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:963: Define or directive not defined: \'`IDCODE_VALUE\'\n    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);\n                                                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:963: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);\n                                                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1007: Define or directive not defined: \'`DBG_WB_CMD_IREG_SEL\'\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);\n                               ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1007: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);\n                                                    ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1050: Define or directive not defined: \'`DBG_WB_CMD_IREG_WR\'\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));\n                               ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1050: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));\n                                                   ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1083: Define or directive not defined: \'`DBG_WB_CMD_BREAD8\'\n       3\'h1: opcode = `DBG_WB_CMD_BREAD8;\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1083: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h1: opcode = `DBG_WB_CMD_BREAD8;\n                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1084: Define or directive not defined: \'`DBG_WB_CMD_BREAD16\'\n       3\'h2: opcode = `DBG_WB_CMD_BREAD16;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1084: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h2: opcode = `DBG_WB_CMD_BREAD16;\n                                         ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1085: Define or directive not defined: \'`DBG_WB_CMD_BREAD32\'\n       3\'h4: opcode = `DBG_WB_CMD_BREAD32;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1085: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h4: opcode = `DBG_WB_CMD_BREAD32;\n                                         ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1089: Define or directive not defined: \'`DBG_WB_CMD_BREAD32\'\n           opcode = `DBG_WB_CMD_BREAD32;\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1089: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n           opcode = `DBG_WB_CMD_BREAD32;\n                                       ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v:1174: Define or directive not defined: \'`DBG_WB_CMD_BWRITE8\'\n       3\'h1: opcode = `DBG_WB_CMD_BWRITE8;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module adv_debug_tb; 


reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;


wire capture_dr;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire dbg_rst;
wire dbg_tdi;
wire dbg_tdo;
wire dbg_sel;


`ifdef DBG_WISHBONE_SUPPORTED
wire [31:0] wb_adr;
wire [31:0] wb_dat_m;
wire [31:0] wb_dat_s;
wire wb_cyc;
wire wb_stb;
wire [3:0] wb_sel;
wire wb_we;
wire wb_ack;
wire wb_err;
reg wb_clk_i;
reg wb_rst_i;
`endif

`ifdef DBG_CPU0_SUPPORTED
wire cpu0_clk;
wire [31:0]cpu0_addr;
wire [31:0] cpu0_data_c;
wire [31:0] cpu0_data_d;
wire cpu0_bp;
wire cpu0_stall;
wire cpu0_stb;
wire cpu0_we;
wire cpu0_ack;
wire cpu0_rst;
`endif

wire jsp_int;
   
reg test_enabled;


reg [31:0] static_data32 [0:15]; 
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];


reg [31:0] input_data32 [0:15]; 
reg [15:0] input_data16 [0:15];
reg [7:0]  input_data8 [0:15];                                

reg [32:0] err_data;

reg failed;
integer i;

reg [63:0] jsp_data8;
    
initial
begin
   jtag_tck_o = 1'b0;
   jtag_tms_o = 1'b0;
   jtag_tdo_o = 1'b0;
end


`ifdef DBG_WISHBONE_SUPPORTED
initial
begin
  wb_clk_i = 1'b0;
  forever #7 wb_clk_i = ~wb_clk_i;
end
`endif




initial
begin
  test_enabled = 1'b0;
  wb_rst_i = 1'b0;
  #100;
  wb_rst_i = 1'b1;
  #100;
  wb_rst_i = 1'b0;


  initialize_memory(32'h0,32'h16);

  #1 test_enabled<=#1 1'b1;
end


always @ (posedge test_enabled)
begin

  $display("Starting advanced debug JTAG serial port test");
  
  reset_jtag;
  #1000;
  check_idcode;
  #1000;
  

  set_ir(`DEBUG);
  #1000;

  







  
  $display("-------------------------------------------");
  $display("--- Test 1: 8 bytes JSP->WB");
  

    $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #200
   $display("JTAG putting 8 bytes to JSP module at time %t", $time);
   do_jsp_read_write(4'h8,jsp_data8);

    

   #1000; 
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  failed <= 1'b0;
   for(i = 0; i < 8; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);

      if(input_data8[0] != i) begin 
        failed = 1;
        $display("JSP-to-WB data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);

      end

    end
    if(!failed) $display("WB-to-JSP data: 8 bytes OK! Test 1 passed!");



 
   $display("-------------------------------------------");
  $display("--- Test 2: 8 bytes WB->JSP");
  

   #1000
  $display("WB putting 8 bytes to JSP module at time %t", $time);
  for(i = 0; i < 8; i=i+1) begin
     static_data8[0] = i;
     do_module_burst_write(3'h1, 16'd1, 32'h0);
  end


   #1000
   $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #1000
   $display("JTAG getting 8 bytes from JSP module at time %t", $time);
   do_jsp_read_write(4'h0,jsp_data8);


   failed <= 1'b0;
   for(i = 0; i < 8; i=i+1) begin
     if(i != input_data8[i]) begin 
        failed = 1;
        $display("WB-to-JSP data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);

    end
  end
    if(!failed) $display("WB-to-JSP data: 8 bytes OK!  Test 2 passed!");
 


 
   $display("-------------------------------------------");
  $display("--- Test 3: 4+4 bytes, JSP->WB");
 

    #1000 
    $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #200
   $display("JTAG putting 4 bytes to JSP module at time %t", $time);
   do_jsp_read_write(4'h4,jsp_data8);
  do_jsp_read_write(4'h4,jsp_data8);

    

   #1000; 
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  failed <= 1'b0;
   for(i = 0; i < 4; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);
      if(input_data8[0] != i) begin 
        failed = 1;
        $display("JSP-to-WB 4+4 data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
      end
    end
   for(i = 0; i < 4; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);
      if(input_data8[0] != i) begin 
        failed = 1;
        $display("JSP-to-WB 4+4 data mismatch at index %d, wrote 0x%x, read 0x%x", i+4, i, input_data8[i]);
      end
    end    
    
    if(!failed) $display("WB-to-JSP 4+4 data: 8 bytes OK! Test 3 passed!");
 


 
   $display("-------------------------------------------");
  $display("--- Test 4: 8 bytes WB->JSP, 4 bytes JSP->WB");
 

   #1000
  $display("Selecting Wishbone module at time %t", $time);
  select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  $display("WB putting 8 bytes to JSP module for R8W4 read at time %t", $time);
  for(i = 0; i < 8; i=i+1) begin
     static_data8[0] = i;
     do_module_burst_write(3'h1, 16'd1, 32'h0);
  end


   #1000
   $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #1000
   $display("JTAG getting 8 and putting 4 at time %t", $time);
   do_jsp_read_write(4'h4,jsp_data8);


   failed <= 1'b0;
   for(i = 0; i < 8; i=i+1) begin
     if(i != input_data8[i]) begin 
        failed = 1;
        $display("R8W4 data mismatch getting JSP data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
    end
  end
    if(!failed) $display("R8W4: 8 JSP bytes OK!");
 

    #1000; 
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  failed <= 1'b0;
   for(i = 0; i < 4; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);
      if(input_data8[0] != i) begin 
        failed = 1;
        $display("R8W4 data mismatch clearing WB data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
      end
    end
    if(!failed) $display("R8W4: 4 WB bytes OK!");
      


 
   $display("-------------------------------------------");
  $display("--- Test 5: Put 6 JSP->WB, then 6 more");
 

   #1000
   $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #1000
   $display("JTAG putting 6 at time %t", $time);
   do_jsp_read_write(4'h6,jsp_data8);
 

     #1000
   $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #1000
   $display("JTAG putting 6 at time %t", $time);
   do_jsp_read_write(4'h6,jsp_data8);
   
   

      #1000; 
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  failed <= 1'b0;
   for(i = 0; i < 6; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);
      if(input_data8[0] != i) begin 
        failed = 1;
        $display("W6W6 data mismatch reading WB data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
      end
    end
   for(i = 0; i < 2; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);
      if(input_data8[0] != i) begin 
        failed = 1;
        $display("W6W6 data mismatch reading WB data at index %d, wrote 0x%x, read 0x%x", i+6, i, input_data8[i]);
      end
    end
    if(!failed) $display("W6W6: 8 WB bytes OK!");

 


 

    $display("-------------------------------------------");
  $display("--- Test 6a: Check LSR with both FIFOs empty");
  
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE); 
   do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h60) begin 
        $display("LSR mismatch with both FIFOs empty, read 0x%x, expected 0x60", input_data8[0]);
   end
  else $display("LSR with both FIFOs empty OK!");

    $display("-------------------------------------------");
  $display("--- Test 6b: Check LSR with WB read data available");
 
  #1000
  $display("Selecting JSP module at time %t", $time);
  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("JTAG putting 1 at time %t", $time);
   do_jsp_read_write(4'h1,jsp_data8);
   
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE); 
   do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h61) begin 
        $display("LSR mismatch with WB read data available, read 0x%x, expected 0x61", input_data8[0]);
   end
  else $display("LSR with WB read data available OK!");   
   
  $display("-------------------------------------------");
  $display("--- Test 6c: Check LSR with WB read data available and write FIFO not empty / full");
   
   #1000
  $display("Selecting Wishbone module at time %t", $time);
  select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  $display("WB putting 1 bytes to JSP module for LSR test at time %t", $time);
  do_module_burst_write(3'h1, 16'd1, 32'h0); 
   
  do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h61) begin 
        $display("LSR mismatch with WB read data available and write FIFO not empty, read 0x%x, expected 0x61", input_data8[0]);
   end
  else $display("LSR with WB read data available and write FIFO not empty OK!");   
   

   for(i = 0; i < 7; i = i + 1) begin
    do_module_burst_write(3'h1, 16'd1, 32'h0);      
   end
   
  do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h01) begin 
        $display("LSR mismatch with WB read data available and write FIFO full, read 0x%x, expected 0x01", input_data8[0]);
   end
  else $display("LSR with WB read data available and write FIFO full OK!");   
   
  $display("-------------------------------------------");
  $display("--- Test 6d: Check LSR with write FIFO full");
  
  do_module_burst_read(3'h1, 16'd1, 32'h0);
   
  do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h00) begin 
        $display("LSR mismatch with WB write FIFO full, read 0x%x, expected 0x00", input_data8[0]);
   end
  else $display("LSR with WB write FIFO full OK!");   
   




  $display("-------------------------------------------");
  $display("--- Test 7: test DLAB bit");
   
     #1000
  $display("Selecting JSP module at time %t", $time);
  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("JTAG putting 1 (and getting 8) at time %t", $time);
   do_jsp_read_write(4'h1,jsp_data8);
   

  #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   
   #1000
   $display("Setting DLAB bit it time %t", $time);  
   static_data8[0] = 8'h80;
   do_module_burst_write(3'h1, 16'd1, 32'h00000003); 
   

   do_module_burst_read(3'h1, 16'd1, 32'h0);
   

   for(i = 0; i < 8; i = i + 1) begin
      do_module_burst_write(3'h1, 16'd1, 32'h0);    
    end
    

   $display("Checking LSR");
  do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h61) begin 
        $display("LSR mismatch in DLAB inhibit test, read 0x%x, expected 0x61", input_data8[0]);
   end
  else $display("DLAB inhibit test OK!");   
   

   $display("Clearing DLAB at time %t", $time);
   static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h3);
   
   do_module_burst_read(3'h1, 16'd1, 32'h0);
   for(i = 0; i < 8; i = i + 1) begin
    do_module_burst_write(3'h1, 16'd1, 32'h0);
   end
 

  do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h00) begin 
        $display("LSR mismatch in DLAB test 2, read 0x%x, expected 0x00", input_data8[0]);
   end
  else $display("DLAB un-inhibit test OK!");   
   

   


   
     $display("-------------------------------------------");
  $display("--- Test 8a:  IER write");
   

  static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h1);
   

   do_module_burst_read(3'h1, 16'd1, 32'h1);
   if(input_data8[0] != 8'h00) begin 
        $display("Failed to set IER to 0x00, read 0x%x", input_data8[0]);
   end
  else $display("Set IER to 0: pass"); 
 

  if(jsp_int) begin
    $display("JSP Interrupt set when no interrupts enabled: FAIL");
  end
  else $display("JSP interrupt not set, interrupts disabled: OK");
 

  static_data8[0] = 8'h0F;
   do_module_burst_write(3'h1, 16'd1, 32'h1);
   

   do_module_burst_read(3'h1, 16'd1, 32'h1);
   if(input_data8[0] != 8'h0F) begin 
        $display("Failed to set IER to 0x0F, read 0x%x", input_data8[0]);
   end
  else $display("Set IER to 0x0F: pass");   
   


  static_data8[0] = 8'h03;
   do_module_burst_write(3'h1, 16'd1, 32'h1);
   

   do_module_burst_read(3'h1, 16'd1, 32'h1);
   if(input_data8[0] != 8'h03) begin 
        $display("Failed to set IER to 0x03, read 0x%x", input_data8[0]);
   end
  else $display("Set IER to 0x03: pass");     




     $display("-------------------------------------------");
  $display("--- Test 8b: int_o output");
  

  if(jsp_int) begin
    $display("JSP Interrupt set when no int condition: FAIL");
  end
  else $display("JSP interrupt not set, no INT condition: OK");
 

    do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h01) begin 
        $display("Wrong value for IIR with no active interrupt, read 0x%x, expected 0x01", input_data8[0]);
   end
  else $display("IIR is 0x01 with no active interrupt: pass");  
    
    

     #1000
  $display("Selecting JSP module at time %t", $time);
  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("JTAG getting 8 at time %t", $time);
   do_jsp_read_write(4'h0,jsp_data8);



  if(!jsp_int) begin
    $display("JSP Interrupt not set when THR empty: FAIL");
  end
  else $display("JSP interrupt set for THR empty: OK");   
 
  #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   

    do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h02) begin 
        $display("Wrong value for IIR with no active interrupt, read 0x%x, expected 0x02", input_data8[0]);
   end
  else $display("IIR is 0x02 with THR empty: pass");  
 

  if(jsp_int) begin
    $display("JSP Interrupt set after IIR read: FAIL");
  end
  else $display("JSP interrupt not set after clearing THR INT with IIR read: OK");
    

    do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h01) begin 
        $display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x01", input_data8[0]);
   end
  else $display("IIR is 0x01 after clearing THR INT with IIR read: pass");  
    

    static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h0);
   

    if(!jsp_int) begin
    $display("JSP Interrupt not set when THR not full: FAIL");
  end
  else $display("JSP interrupt set for THR not full: OK");  
    

  #1000
  $display("Selecting JSP module at time %t", $time);
  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("JTAG putting 1 at time %t", $time);
   do_jsp_read_write(4'h1,jsp_data8);
  

    if(!jsp_int) begin
    $display("JSP Interrupt not set when read data available: FAIL");
  end
  else $display("JSP interrupt set for read data available: OK");  
    

   #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h4) begin 
        $display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x04", input_data8[0]);
   end
  else $display("IIR is 0x04 after putting a JSP byte: pass"); 
   

    do_module_burst_read(3'h1, 16'd1, 32'h0);
    

      if(!jsp_int) begin
    $display("JSP Interrupt not set when THR not full: FAIL");
  end
  else $display("JSP interrupt set for THR not full: OK"); 
  

     #1000
   do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h02) begin 
        $display("Wrong value for IIR after clearing RDA INT with WB read (THRE), read 0x%x, expected 0x02", input_data8[0]);
   end
    else $display("IIR is 0x02 after reading data with THRE: pass"); 
  

    if(jsp_int) begin
    $display("JSP Interrupt set after clearing THRE with IIR read: FAIL");
  end
  else $display("JSP interrupt not set, THRE cleared with IIR read: OK");
  

   #1000
   do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h01) begin 
        $display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x01", input_data8[0]);
   end
    else $display("IIR is 0x01 after reading data with THRE: pass"); 
  

   #1000
  $display("Selecting JSP module at time %t", $time);
  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("JTAG putting 1 at time %t", $time);
   do_jsp_read_write(4'h1,jsp_data8);
  
  

      if(!jsp_int) begin
    $display("JSP Interrupt not set when read data available: FAIL");
  end
  else $display("JSP interrupt set for read data available: OK"); 
    

     #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h4) begin 
        $display("Wrong value for IIR with RDA, read 0x%x, expected 0x04", input_data8[0]);
   end
  else $display("IIR is 0x04 after putting a JSP byte: pass"); 
  

   do_module_burst_read(3'h1, 16'd1, 32'h0);
   
    

    if(jsp_int) begin
    $display("JSP Interrupt set when no int condition: FAIL");
  end
  else $display("JSP interrupt not set, no INT condition: OK");
    

      #1000
   do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h1) begin 
        $display("Wrong value for IIR with no active int, read 0x%x, expected 0x01", input_data8[0]);
   end
  else $display("IIR is 0x01 with no active interrupts: pass"); 
   



  $display("-------------------------------------------");
  $display("--- Test 9: Software WB/UART FIFO reset");
  


   #1000

  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);

   do_jsp_read_write(4'h1,jsp_data8);
   

    #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   #500
  static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h0);
   

   #500
   static_data8[0] = 8'h02;
  do_module_burst_write(3'h1, 16'd1, 32'h2);



     #1000

  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("Next line should show 1 byte available, 8 bytes free:");
   do_jsp_read_write(4'h0,jsp_data8);
 
 


   #1000
   do_jsp_read_write(4'h1,jsp_data8);
   

    #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   #500
  static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h0);
   

   #500
   static_data8[0] = 8'h04;
  do_module_burst_write(3'h1, 16'd1, 32'h2);



     #1000

  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("Next line should show 0 byte available, 7 bytes free:");
   do_jsp_read_write(4'h0,jsp_data8);
     


   #1000
   do_jsp_read_write(4'h1,jsp_data8);
   

    #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   #500
  static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h0);
   

   #500
   static_data8[0] = 8'h06;
  do_module_burst_write(3'h1, 16'd1, 32'h2);



     #1000

  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("Next line should show 0 byte available, 8 bytes free:");
   do_jsp_read_write(4'h0,jsp_data8);
     


  
  $display("----------------------------------"); 
  $display("--- ALL TESTS COMPLETE ---"); 
  
  end

task initialize_memory;
  input [31:0] start_addr;
  input [31:0] length;
  integer i;
  reg [31:0] addr;
  begin

  jsp_data8 <= 64'h0706050403020100;

    for (i=0; i<length; i=i+1)
      begin
        static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
        static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
        static_data8[i] <= i[7:0];
      end
  end
endtask





tap_top  i_tap (

                .tms_pad_i(jtag_tms_o), 
                .tck_pad_i(jtag_tck_o), 
                .trstn_pad_i(1'b1), 
                .tdi_pad_i(jtag_tdo_o), 
                .tdo_pad_o(jtag_tdi_i), 
                .tdo_padoe_o(),


		.test_logic_reset_o(dbg_rst),
		.run_test_idle_o(),
                .shift_dr_o(shift_dr),
                .pause_dr_o(pause_dr), 
                .update_dr_o(update_dr),
                .capture_dr_o(capture_dr),
                

                .extest_select_o(), 
                .sample_preload_select_o(),
                .mbist_select_o(),
                .debug_select_o(dbg_sel),
                

                .tdi_o(dbg_tdo), 
                

                .debug_tdo_i(dbg_tdi),
                .bs_chain_tdo_i(1'b0),
                .mbist_tdo_i(1'b0)
              );



adbg_top i_dbg_module(

                .tck_i(jtag_tck_o),
                .tdi_i(dbg_tdo),
                .tdo_o(dbg_tdi),
                .rst_i(dbg_rst),


                .shift_dr_i(shift_dr),
                .pause_dr_i(pause_dr),
                .update_dr_i(update_dr),
                .capture_dr_i(capture_dr),


                .debug_select_i(dbg_sel)


                `ifdef DBG_WISHBONE_SUPPORTED

                ,
                .wb_clk_i(wb_clk_i),
                .wb_rst_i(wb_rst_i),
                                                                                

                .wb_adr_o(wb_adr),
                .wb_dat_o(wb_dat_m),
                .wb_dat_i(wb_dat_s),
                .wb_cyc_o(wb_cyc),
                .wb_stb_o(wb_stb),
                .wb_sel_o(wb_sel),
                .wb_we_o(wb_we),
                .wb_ack_i(wb_ack),
                .wb_cab_o(),
                .wb_err_i(wb_err),
                .wb_cti_o(),
                .wb_bte_o()
                `endif

		 `ifdef DBG_JSP_SUPPORTED

		 ,
                .wb_jsp_adr_i(wb_adr),
                .wb_jsp_dat_o(wb_dat_s),
                .wb_jsp_dat_i(wb_dat_m),
                .wb_jsp_cyc_i(wb_cyc),
                .wb_jsp_stb_i(wb_stb),
                .wb_jsp_sel_i(wb_sel),
                .wb_jsp_we_i(wb_we),
                .wb_jsp_ack_o(wb_ack),
                .wb_jsp_cab_i(),
                .wb_jsp_err_o(wb_err),
                .wb_jsp_cti_i(),
                .wb_jsp_bte_i(),
		.int_o(jsp_int)
		`endif

              );


   




task compute_crc;
    input [31:0] crc_in;
    input [31:0] data_in;
    input [5:0] length_bits;
    output [31:0] crc_out;
    integer i;
    reg [31:0] d;
    reg [31:0] c;
    begin
        crc_out = crc_in;
        for(i = 0; i < length_bits; i = i+1) begin
           d = (data_in[i]) ? 32'hffffffff : 32'h0;
           c = (crc_out[0]) ? 32'hffffffff : 32'h0;

           crc_out = crc_out >> 1;
           crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);

        end
    end
endtask

task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
    set_ir(`IDCODE);
    

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_read_write_stream(64'h0, 8'd32, 1, readdata);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    idcode = readdata[31:0];
    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;

task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({1'b1,moduleid}, 8'h3, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    
    $display("Selecting module (%0x)", moduleid);
    
end
endtask


task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
    streamdata = {11'h0,1'b0,opcode,address,burstlength};
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, 8'd53, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask

task select_module_internal_register;
    input [31:0] regidx;
    input [7:0] len;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | regidx;
    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (len+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask
        

task read_module_internal_register;

    input [7:0] len;
    output [63:0] instream;
    reg [63:0] bitmask;
begin
    instream = 64'h0;

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);

    jtag_read_write_stream(64'h0, len+4,1,instream);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    bitmask = 64'hffffffffffffffff;
    bitmask = bitmask << len;
    bitmask = ~bitmask;
    instream = instream & bitmask;
end
endtask

task write_module_internal_register;
    input [31:0] regidx;
    input [7:0] idxlen;
    input [63:0] writedata;
    input [7:0] datalen;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | writedata;
    streamdata = streamdata | (regidx << datalen);
    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
    
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (idxlen+datalen+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin

    instream = 64'h0;
    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BREAD8;
       3'h2: opcode = `DBG_WB_CMD_BREAD16;
       3'h4: opcode = `DBG_WB_CMD_BREAD32;
       default:
          begin
           $display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BREAD32;
          end
   endcase
   
   send_module_burst_command(opcode,start_address, word_count);
   

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);

`ifdef ADBG_USE_HISPEED

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      



`endif
   

   for(i = 0; i < word_count; i=i+1) begin
     
`ifndef ADBG_USE_HISPEED     

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      



`endif
  
     jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);

     compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
     crc_calc_i = crc_calc_o;
     if(word_size_bytes == 1) input_data8[i] = instream[7:0];
     else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
     else input_data32[i] = instream[31:0];
   end
    

   jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
   if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);

    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end
endtask


task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin

    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BWRITE8;
       3'h2: opcode = `DBG_WB_CMD_BWRITE16;
       3'h4: opcode = `DBG_WB_CMD_BWRITE32;
       default:
          begin
           $display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BWRITE32;
          end
   endcase
   
   send_module_burst_command(opcode, start_address, word_count);
   

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);
   


   write_bit(`JTAG_TDO_bit);


   for(i = 0; i < word_count; i=i+1) begin

      if(word_size_bytes == 4)      dataword = {32'h0, static_data32[i]};
      else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
      else                          dataword = {56'h0, static_data8[i]};
      
      
      jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
      compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
      crc_calc_i = crc_calc_o;
      
      
`ifndef ADBG_USE_HISPEED


      status = 1'b0;
      read_write_bit(3'h0, status);
      
      if(!status) begin
         $display("Bad status bit during burst write, index %d", i);
      end
`endif      
  

   end
    

   jtag_write_stream(crc_calc_o, 6'd32,0);
   

   read_write_bit(`JTAG_TMS_bit, crc_match);
   if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);

    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end

endtask

   task do_jsp_read_write;
      input [3:0] words_to_put;
      input [63:0] outstream;
      reg [63:0] instream;
      integer i;
      integer j;
      integer snd;
      integer rcv;
      integer xfer_size;
      reg inbit;

      begin


	 write_bit(`JTAG_TMS_bit);
	 write_bit(3'h0);
	 write_bit(3'h0);

`ifdef ADBG_JSP_SUPPORT_MULTI
	 read_write_bit(`JTAG_TDO_bit,inbit);
`endif


	 jtag_read_write_stream({56'h0,words_to_put, 4'b0000}, 8'h8,0,instream);
	 
`ifdef ADBG_JSP_SUPPORT_MULTI

  instream = (instream << 1);
  instream[0] = inbit;
  inbit = instream[8];
`endif

	 $display("JSP got %d bytes available, %d bytes free", instream[7:4], instream[3:0]);


	 rcv = instream[7:4];
	 snd = words_to_put;
	 if(instream[3:0] < words_to_put) snd = instream[3:0];
	 xfer_size = snd;
	 if(rcv > snd) xfer_size = rcv;
	 



	 
	 $display("Doing JSP transfer of %d bytes", xfer_size);
	 

	 for(i = 0; i < xfer_size; i=i+1) begin
	   #100
	    jtag_read_write_stream(outstream>>(i*8), 8'h8,0,instream);
`ifdef ADBG_JSP_SUPPORT_MULTI	    
      input_data8[i] = {instream[6:0], inbit};
      inbit = instream[7];
`else
	    input_data8[i] = instream[7:0];
`endif
	 end




	 write_bit(`JTAG_TMS_bit);
	 

	 write_bit(`JTAG_TMS_bit);
	 write_bit(3'h0);
	 
	 end
      endtask
   
   



task set_ir;
input [3:0] irval;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({60'h0,irval}, 8'h4, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task reset_jtag;
integer i;
begin
   for(i = 0; i < 8; i=i+1) begin
      write_bit(`JTAG_TMS_bit);
   end
   write_bit(3'h0);
end
endtask





task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       write_bit(bits);
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   write_bit(bits);
    
end
endtask


task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
    instream = 64'h0;
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       read_write_bit(bits, inbit);
       instream = (instream | (inbit << i));
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   read_write_bit(bits, inbit);
   instream = (instream | (inbit << (len-1)));
end
endtask




task write_bit;
   input [2:0] bitvals;
   begin
       

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask

task read_write_bit;
   input [2:0] bitvals;
   output l_tdi_val;
   begin
       

   l_tdi_val <= jtag_tdi_i;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask




task jtag_out;
  input   [2:0]   bitvals;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 
   end
endtask


task jtag_inout;
  input   [2:0]   bitvals;
  output l_tdi_val;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 

   l_tdi_val <= jtag_tdi_i;
   end
endtask

endmodule
module adv_debug_tb;
 


reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;


wire capture_dr;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire dbg_rst;
wire dbg_tdi;
wire dbg_tdo;
wire dbg_sel;


`ifdef DBG_WISHBONE_SUPPORTED
wire [31:0] wb_adr;
wire [31:0] wb_dat_m;
wire [31:0] wb_dat_s;
wire wb_cyc;
wire wb_stb;
wire [3:0] wb_sel;
wire wb_we;
wire wb_ack;
wire wb_err;
reg wb_clk_i;
reg wb_rst_i;
`endif

`ifdef DBG_CPU0_SUPPORTED
wire cpu0_clk;
wire [31:0]cpu0_addr;
wire [31:0] cpu0_data_c;
wire [31:0] cpu0_data_d;
wire cpu0_bp;
wire cpu0_stall;
wire cpu0_stb;
wire cpu0_we;
wire cpu0_ack;
wire cpu0_rst;
`endif

wire jsp_int;
   
reg test_enabled;


reg [31:0] static_data32 [0:15]; 
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];


reg [31:0] input_data32 [0:15]; 
reg [15:0] input_data16 [0:15];
reg [7:0]  input_data8 [0:15];                                

reg [32:0] err_data;

reg failed;
integer i;

reg [63:0] jsp_data8;
    
initial
begin
   jtag_tck_o = 1'b0;
   jtag_tms_o = 1'b0;
   jtag_tdo_o = 1'b0;
end


`ifdef DBG_WISHBONE_SUPPORTED
initial
begin
  wb_clk_i = 1'b0;
  forever #7 wb_clk_i = ~wb_clk_i;
end
`endif




initial
begin
  test_enabled = 1'b0;
  wb_rst_i = 1'b0;
  #100;
  wb_rst_i = 1'b1;
  #100;
  wb_rst_i = 1'b0;


  initialize_memory(32'h0,32'h16);

  #1 test_enabled<=#1 1'b1;
end


always @ (posedge test_enabled)
begin

  $display("Starting advanced debug JTAG serial port test");
  
  reset_jtag;
  #1000;
  check_idcode;
  #1000;
  

  set_ir(`DEBUG);
  #1000;

  







  
  $display("-------------------------------------------");
  $display("--- Test 1: 8 bytes JSP->WB");
  

    $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #200
   $display("JTAG putting 8 bytes to JSP module at time %t", $time);
   do_jsp_read_write(4'h8,jsp_data8);

    

   #1000; 
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  failed <= 1'b0;
   for(i = 0; i < 8; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);

      if(input_data8[0] != i) begin 
        failed = 1;
        $display("JSP-to-WB data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);

      end

    end
    if(!failed) $display("WB-to-JSP data: 8 bytes OK! Test 1 passed!");



 
   $display("-------------------------------------------");
  $display("--- Test 2: 8 bytes WB->JSP");
  

   #1000
  $display("WB putting 8 bytes to JSP module at time %t", $time);
  for(i = 0; i < 8; i=i+1) begin
     static_data8[0] = i;
     do_module_burst_write(3'h1, 16'd1, 32'h0);
  end


   #1000
   $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #1000
   $display("JTAG getting 8 bytes from JSP module at time %t", $time);
   do_jsp_read_write(4'h0,jsp_data8);


   failed <= 1'b0;
   for(i = 0; i < 8; i=i+1) begin
     if(i != input_data8[i]) begin 
        failed = 1;
        $display("WB-to-JSP data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);

    end
  end
    if(!failed) $display("WB-to-JSP data: 8 bytes OK!  Test 2 passed!");
 


 
   $display("-------------------------------------------");
  $display("--- Test 3: 4+4 bytes, JSP->WB");
 

    #1000 
    $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #200
   $display("JTAG putting 4 bytes to JSP module at time %t", $time);
   do_jsp_read_write(4'h4,jsp_data8);
  do_jsp_read_write(4'h4,jsp_data8);

    

   #1000; 
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  failed <= 1'b0;
   for(i = 0; i < 4; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);
      if(input_data8[0] != i) begin 
        failed = 1;
        $display("JSP-to-WB 4+4 data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
      end
    end
   for(i = 0; i < 4; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);
      if(input_data8[0] != i) begin 
        failed = 1;
        $display("JSP-to-WB 4+4 data mismatch at index %d, wrote 0x%x, read 0x%x", i+4, i, input_data8[i]);
      end
    end    
    
    if(!failed) $display("WB-to-JSP 4+4 data: 8 bytes OK! Test 3 passed!");
 


 
   $display("-------------------------------------------");
  $display("--- Test 4: 8 bytes WB->JSP, 4 bytes JSP->WB");
 

   #1000
  $display("Selecting Wishbone module at time %t", $time);
  select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  $display("WB putting 8 bytes to JSP module for R8W4 read at time %t", $time);
  for(i = 0; i < 8; i=i+1) begin
     static_data8[0] = i;
     do_module_burst_write(3'h1, 16'd1, 32'h0);
  end


   #1000
   $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #1000
   $display("JTAG getting 8 and putting 4 at time %t", $time);
   do_jsp_read_write(4'h4,jsp_data8);


   failed <= 1'b0;
   for(i = 0; i < 8; i=i+1) begin
     if(i != input_data8[i]) begin 
        failed = 1;
        $display("R8W4 data mismatch getting JSP data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
    end
  end
    if(!failed) $display("R8W4: 8 JSP bytes OK!");
 

    #1000; 
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  failed <= 1'b0;
   for(i = 0; i < 4; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);
      if(input_data8[0] != i) begin 
        failed = 1;
        $display("R8W4 data mismatch clearing WB data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
      end
    end
    if(!failed) $display("R8W4: 4 WB bytes OK!");
      


 
   $display("-------------------------------------------");
  $display("--- Test 5: Put 6 JSP->WB, then 6 more");
 

   #1000
   $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #1000
   $display("JTAG putting 6 at time %t", $time);
   do_jsp_read_write(4'h6,jsp_data8);
 

     #1000
   $display("Selecting JSP module at time %t", $time);
   select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
   #1000
   $display("JTAG putting 6 at time %t", $time);
   do_jsp_read_write(4'h6,jsp_data8);
   
   

      #1000; 
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  failed <= 1'b0;
   for(i = 0; i < 6; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);
      if(input_data8[0] != i) begin 
        failed = 1;
        $display("W6W6 data mismatch reading WB data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
      end
    end
   for(i = 0; i < 2; i=i+1) begin
      do_module_burst_read(3'h1, 16'd1, 32'h0);
      if(input_data8[0] != i) begin 
        failed = 1;
        $display("W6W6 data mismatch reading WB data at index %d, wrote 0x%x, read 0x%x", i+6, i, input_data8[i]);
      end
    end
    if(!failed) $display("W6W6: 8 WB bytes OK!");

 


 

    $display("-------------------------------------------");
  $display("--- Test 6a: Check LSR with both FIFOs empty");
  
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE); 
   do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h60) begin 
        $display("LSR mismatch with both FIFOs empty, read 0x%x, expected 0x60", input_data8[0]);
   end
  else $display("LSR with both FIFOs empty OK!");

    $display("-------------------------------------------");
  $display("--- Test 6b: Check LSR with WB read data available");
 
  #1000
  $display("Selecting JSP module at time %t", $time);
  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("JTAG putting 1 at time %t", $time);
   do_jsp_read_write(4'h1,jsp_data8);
   
   $display("Selecting Wishbone module at time %t", $time);
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE); 
   do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h61) begin 
        $display("LSR mismatch with WB read data available, read 0x%x, expected 0x61", input_data8[0]);
   end
  else $display("LSR with WB read data available OK!");   
   
  $display("-------------------------------------------");
  $display("--- Test 6c: Check LSR with WB read data available and write FIFO not empty / full");
   
   #1000
  $display("Selecting Wishbone module at time %t", $time);
  select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  $display("WB putting 1 bytes to JSP module for LSR test at time %t", $time);
  do_module_burst_write(3'h1, 16'd1, 32'h0); 
   
  do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h61) begin 
        $display("LSR mismatch with WB read data available and write FIFO not empty, read 0x%x, expected 0x61", input_data8[0]);
   end
  else $display("LSR with WB read data available and write FIFO not empty OK!");   
   

   for(i = 0; i < 7; i = i + 1) begin
    do_module_burst_write(3'h1, 16'd1, 32'h0);      
   end
   
  do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h01) begin 
        $display("LSR mismatch with WB read data available and write FIFO full, read 0x%x, expected 0x01", input_data8[0]);
   end
  else $display("LSR with WB read data available and write FIFO full OK!");   
   
  $display("-------------------------------------------");
  $display("--- Test 6d: Check LSR with write FIFO full");
  
  do_module_burst_read(3'h1, 16'd1, 32'h0);
   
  do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h00) begin 
        $display("LSR mismatch with WB write FIFO full, read 0x%x, expected 0x00", input_data8[0]);
   end
  else $display("LSR with WB write FIFO full OK!");   
   




  $display("-------------------------------------------");
  $display("--- Test 7: test DLAB bit");
   
     #1000
  $display("Selecting JSP module at time %t", $time);
  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("JTAG putting 1 (and getting 8) at time %t", $time);
   do_jsp_read_write(4'h1,jsp_data8);
   

  #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   
   #1000
   $display("Setting DLAB bit it time %t", $time);  
   static_data8[0] = 8'h80;
   do_module_burst_write(3'h1, 16'd1, 32'h00000003); 
   

   do_module_burst_read(3'h1, 16'd1, 32'h0);
   

   for(i = 0; i < 8; i = i + 1) begin
      do_module_burst_write(3'h1, 16'd1, 32'h0);    
    end
    

   $display("Checking LSR");
  do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h61) begin 
        $display("LSR mismatch in DLAB inhibit test, read 0x%x, expected 0x61", input_data8[0]);
   end
  else $display("DLAB inhibit test OK!");   
   

   $display("Clearing DLAB at time %t", $time);
   static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h3);
   
   do_module_burst_read(3'h1, 16'd1, 32'h0);
   for(i = 0; i < 8; i = i + 1) begin
    do_module_burst_write(3'h1, 16'd1, 32'h0);
   end
 

  do_module_burst_read(3'h1, 16'd1, 32'h5);
   if(input_data8[0] != 8'h00) begin 
        $display("LSR mismatch in DLAB test 2, read 0x%x, expected 0x00", input_data8[0]);
   end
  else $display("DLAB un-inhibit test OK!");   
   

   


   
     $display("-------------------------------------------");
  $display("--- Test 8a:  IER write");
   

  static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h1);
   

   do_module_burst_read(3'h1, 16'd1, 32'h1);
   if(input_data8[0] != 8'h00) begin 
        $display("Failed to set IER to 0x00, read 0x%x", input_data8[0]);
   end
  else $display("Set IER to 0: pass"); 
 

  if(jsp_int) begin
    $display("JSP Interrupt set when no interrupts enabled: FAIL");
  end
  else $display("JSP interrupt not set, interrupts disabled: OK");
 

  static_data8[0] = 8'h0F;
   do_module_burst_write(3'h1, 16'd1, 32'h1);
   

   do_module_burst_read(3'h1, 16'd1, 32'h1);
   if(input_data8[0] != 8'h0F) begin 
        $display("Failed to set IER to 0x0F, read 0x%x", input_data8[0]);
   end
  else $display("Set IER to 0x0F: pass");   
   


  static_data8[0] = 8'h03;
   do_module_burst_write(3'h1, 16'd1, 32'h1);
   

   do_module_burst_read(3'h1, 16'd1, 32'h1);
   if(input_data8[0] != 8'h03) begin 
        $display("Failed to set IER to 0x03, read 0x%x", input_data8[0]);
   end
  else $display("Set IER to 0x03: pass");     




     $display("-------------------------------------------");
  $display("--- Test 8b: int_o output");
  

  if(jsp_int) begin
    $display("JSP Interrupt set when no int condition: FAIL");
  end
  else $display("JSP interrupt not set, no INT condition: OK");
 

    do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h01) begin 
        $display("Wrong value for IIR with no active interrupt, read 0x%x, expected 0x01", input_data8[0]);
   end
  else $display("IIR is 0x01 with no active interrupt: pass");  
    
    

     #1000
  $display("Selecting JSP module at time %t", $time);
  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("JTAG getting 8 at time %t", $time);
   do_jsp_read_write(4'h0,jsp_data8);



  if(!jsp_int) begin
    $display("JSP Interrupt not set when THR empty: FAIL");
  end
  else $display("JSP interrupt set for THR empty: OK");   
 
  #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   

    do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h02) begin 
        $display("Wrong value for IIR with no active interrupt, read 0x%x, expected 0x02", input_data8[0]);
   end
  else $display("IIR is 0x02 with THR empty: pass");  
 

  if(jsp_int) begin
    $display("JSP Interrupt set after IIR read: FAIL");
  end
  else $display("JSP interrupt not set after clearing THR INT with IIR read: OK");
    

    do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h01) begin 
        $display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x01", input_data8[0]);
   end
  else $display("IIR is 0x01 after clearing THR INT with IIR read: pass");  
    

    static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h0);
   

    if(!jsp_int) begin
    $display("JSP Interrupt not set when THR not full: FAIL");
  end
  else $display("JSP interrupt set for THR not full: OK");  
    

  #1000
  $display("Selecting JSP module at time %t", $time);
  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("JTAG putting 1 at time %t", $time);
   do_jsp_read_write(4'h1,jsp_data8);
  

    if(!jsp_int) begin
    $display("JSP Interrupt not set when read data available: FAIL");
  end
  else $display("JSP interrupt set for read data available: OK");  
    

   #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h4) begin 
        $display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x04", input_data8[0]);
   end
  else $display("IIR is 0x04 after putting a JSP byte: pass"); 
   

    do_module_burst_read(3'h1, 16'd1, 32'h0);
    

      if(!jsp_int) begin
    $display("JSP Interrupt not set when THR not full: FAIL");
  end
  else $display("JSP interrupt set for THR not full: OK"); 
  

     #1000
   do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h02) begin 
        $display("Wrong value for IIR after clearing RDA INT with WB read (THRE), read 0x%x, expected 0x02", input_data8[0]);
   end
    else $display("IIR is 0x02 after reading data with THRE: pass"); 
  

    if(jsp_int) begin
    $display("JSP Interrupt set after clearing THRE with IIR read: FAIL");
  end
  else $display("JSP interrupt not set, THRE cleared with IIR read: OK");
  

   #1000
   do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h01) begin 
        $display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x01", input_data8[0]);
   end
    else $display("IIR is 0x01 after reading data with THRE: pass"); 
  

   #1000
  $display("Selecting JSP module at time %t", $time);
  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("JTAG putting 1 at time %t", $time);
   do_jsp_read_write(4'h1,jsp_data8);
  
  

      if(!jsp_int) begin
    $display("JSP Interrupt not set when read data available: FAIL");
  end
  else $display("JSP interrupt set for read data available: OK"); 
    

     #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h4) begin 
        $display("Wrong value for IIR with RDA, read 0x%x, expected 0x04", input_data8[0]);
   end
  else $display("IIR is 0x04 after putting a JSP byte: pass"); 
  

   do_module_burst_read(3'h1, 16'd1, 32'h0);
   
    

    if(jsp_int) begin
    $display("JSP Interrupt set when no int condition: FAIL");
  end
  else $display("JSP interrupt not set, no INT condition: OK");
    

      #1000
   do_module_burst_read(3'h1, 16'd1, 32'h2);
   if(input_data8[0] != 8'h1) begin 
        $display("Wrong value for IIR with no active int, read 0x%x, expected 0x01", input_data8[0]);
   end
  else $display("IIR is 0x01 with no active interrupts: pass"); 
   



  $display("-------------------------------------------");
  $display("--- Test 9: Software WB/UART FIFO reset");
  


   #1000

  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);

   do_jsp_read_write(4'h1,jsp_data8);
   

    #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   #500
  static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h0);
   

   #500
   static_data8[0] = 8'h02;
  do_module_burst_write(3'h1, 16'd1, 32'h2);



     #1000

  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("Next line should show 1 byte available, 8 bytes free:");
   do_jsp_read_write(4'h0,jsp_data8);
 
 


   #1000
   do_jsp_read_write(4'h1,jsp_data8);
   

    #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   #500
  static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h0);
   

   #500
   static_data8[0] = 8'h04;
  do_module_burst_write(3'h1, 16'd1, 32'h2);



     #1000

  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("Next line should show 0 byte available, 7 bytes free:");
   do_jsp_read_write(4'h0,jsp_data8);
     


   #1000
   do_jsp_read_write(4'h1,jsp_data8);
   

    #1000
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   #500
  static_data8[0] = 8'h00;
   do_module_burst_write(3'h1, 16'd1, 32'h0);
   

   #500
   static_data8[0] = 8'h06;
  do_module_burst_write(3'h1, 16'd1, 32'h2);



     #1000

  select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
    $display("Next line should show 0 byte available, 8 bytes free:");
   do_jsp_read_write(4'h0,jsp_data8);
     


  
  $display("----------------------------------"); 
  $display("--- ALL TESTS COMPLETE ---"); 
  
  end

task initialize_memory;
  input [31:0] start_addr;
  input [31:0] length;
  integer i;
  reg [31:0] addr;
  begin

  jsp_data8 <= 64'h0706050403020100;

    for (i=0; i<length; i=i+1)
      begin
        static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
        static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
        static_data8[i] <= i[7:0];
      end
  end
endtask





tap_top  i_tap (

                .tms_pad_i(jtag_tms_o), 
                .tck_pad_i(jtag_tck_o), 
                .trstn_pad_i(1'b1), 
                .tdi_pad_i(jtag_tdo_o), 
                .tdo_pad_o(jtag_tdi_i), 
                .tdo_padoe_o(),


		.test_logic_reset_o(dbg_rst),
		.run_test_idle_o(),
                .shift_dr_o(shift_dr),
                .pause_dr_o(pause_dr), 
                .update_dr_o(update_dr),
                .capture_dr_o(capture_dr),
                

                .extest_select_o(), 
                .sample_preload_select_o(),
                .mbist_select_o(),
                .debug_select_o(dbg_sel),
                

                .tdi_o(dbg_tdo), 
                

                .debug_tdo_i(dbg_tdi),
                .bs_chain_tdo_i(1'b0),
                .mbist_tdo_i(1'b0)
              );



adbg_top i_dbg_module(

                .tck_i(jtag_tck_o),
                .tdi_i(dbg_tdo),
                .tdo_o(dbg_tdi),
                .rst_i(dbg_rst),


                .shift_dr_i(shift_dr),
                .pause_dr_i(pause_dr),
                .update_dr_i(update_dr),
                .capture_dr_i(capture_dr),


                .debug_select_i(dbg_sel)


                `ifdef DBG_WISHBONE_SUPPORTED

                ,
                .wb_clk_i(wb_clk_i),
                .wb_rst_i(wb_rst_i),
                                                                                

                .wb_adr_o(wb_adr),
                .wb_dat_o(wb_dat_m),
                .wb_dat_i(wb_dat_s),
                .wb_cyc_o(wb_cyc),
                .wb_stb_o(wb_stb),
                .wb_sel_o(wb_sel),
                .wb_we_o(wb_we),
                .wb_ack_i(wb_ack),
                .wb_cab_o(),
                .wb_err_i(wb_err),
                .wb_cti_o(),
                .wb_bte_o()
                `endif

		 `ifdef DBG_JSP_SUPPORTED

		 ,
                .wb_jsp_adr_i(wb_adr),
                .wb_jsp_dat_o(wb_dat_s),
                .wb_jsp_dat_i(wb_dat_m),
                .wb_jsp_cyc_i(wb_cyc),
                .wb_jsp_stb_i(wb_stb),
                .wb_jsp_sel_i(wb_sel),
                .wb_jsp_we_i(wb_we),
                .wb_jsp_ack_o(wb_ack),
                .wb_jsp_cab_i(),
                .wb_jsp_err_o(wb_err),
                .wb_jsp_cti_i(),
                .wb_jsp_bte_i(),
		.int_o(jsp_int)
		`endif

              );


   




task compute_crc;
    input [31:0] crc_in;
    input [31:0] data_in;
    input [5:0] length_bits;
    output [31:0] crc_out;
    integer i;
    reg [31:0] d;
    reg [31:0] c;
    begin
        crc_out = crc_in;
        for(i = 0; i < length_bits; i = i+1) begin
           d = (data_in[i]) ? 32'hffffffff : 32'h0;
           c = (crc_out[0]) ? 32'hffffffff : 32'h0;

           crc_out = crc_out >> 1;
           crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);

        end
    end
endtask

task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
    set_ir(`IDCODE);
    

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_read_write_stream(64'h0, 8'd32, 1, readdata);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    idcode = readdata[31:0];
    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;

task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({1'b1,moduleid}, 8'h3, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    
    $display("Selecting module (%0x)", moduleid);
    
end
endtask


task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
    streamdata = {11'h0,1'b0,opcode,address,burstlength};
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, 8'd53, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask

task select_module_internal_register;
    input [31:0] regidx;
    input [7:0] len;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | regidx;
    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (len+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask
        

task read_module_internal_register;

    input [7:0] len;
    output [63:0] instream;
    reg [63:0] bitmask;
begin
    instream = 64'h0;

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);

    jtag_read_write_stream(64'h0, len+4,1,instream);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    bitmask = 64'hffffffffffffffff;
    bitmask = bitmask << len;
    bitmask = ~bitmask;
    instream = instream & bitmask;
end
endtask

task write_module_internal_register;
    input [31:0] regidx;
    input [7:0] idxlen;
    input [63:0] writedata;
    input [7:0] datalen;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | writedata;
    streamdata = streamdata | (regidx << datalen);
    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
    
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (idxlen+datalen+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin

    instream = 64'h0;
    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BREAD8;
       3'h2: opcode = `DBG_WB_CMD_BREAD16;
       3'h4: opcode = `DBG_WB_CMD_BREAD32;
       default:
          begin
           $display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BREAD32;
          end
   endcase
   
   send_module_burst_command(opcode,start_address, word_count);
   

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);

`ifdef ADBG_USE_HISPEED

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      



`endif
   

   for(i = 0; i < word_count; i=i+1) begin
     
`ifndef ADBG_USE_HISPEED     

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      



`endif
  
     jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);

     compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
     crc_calc_i = crc_calc_o;
     if(word_size_bytes == 1) input_data8[i] = instream[7:0];
     else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
     else input_data32[i] = instream[31:0];
   end
    

   jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
   if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);

    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end
endtask


task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin

    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BWRITE8;
       3'h2: opcode = `DBG_WB_CMD_BWRITE16;
       3'h4: opcode = `DBG_WB_CMD_BWRITE32;
       default:
          begin
           $display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BWRITE32;
          end
   endcase
   
   send_module_burst_command(opcode, start_address, word_count);
   

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);
   


   write_bit(`JTAG_TDO_bit);


   for(i = 0; i < word_count; i=i+1) begin

      if(word_size_bytes == 4)      dataword = {32'h0, static_data32[i]};
      else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
      else                          dataword = {56'h0, static_data8[i]};
      
      
      jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
      compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
      crc_calc_i = crc_calc_o;
      
      
`ifndef ADBG_USE_HISPEED


      status = 1'b0;
      read_write_bit(3'h0, status);
      
      if(!status) begin
         $display("Bad status bit during burst write, index %d", i);
      end
`endif      
  

   end
    

   jtag_write_stream(crc_calc_o, 6'd32,0);
   

   read_write_bit(`JTAG_TMS_bit, crc_match);
   if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);

    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end

endtask

   task do_jsp_read_write;
      input [3:0] words_to_put;
      input [63:0] outstream;
      reg [63:0] instream;
      integer i;
      integer j;
      integer snd;
      integer rcv;
      integer xfer_size;
      reg inbit;

      begin


	 write_bit(`JTAG_TMS_bit);
	 write_bit(3'h0);
	 write_bit(3'h0);

`ifdef ADBG_JSP_SUPPORT_MULTI
	 read_write_bit(`JTAG_TDO_bit,inbit);
`endif


	 jtag_read_write_stream({56'h0,words_to_put, 4'b0000}, 8'h8,0,instream);
	 
`ifdef ADBG_JSP_SUPPORT_MULTI

  instream = (instream << 1);
  instream[0] = inbit;
  inbit = instream[8];
`endif

	 $display("JSP got %d bytes available, %d bytes free", instream[7:4], instream[3:0]);


	 rcv = instream[7:4];
	 snd = words_to_put;
	 if(instream[3:0] < words_to_put) snd = instream[3:0];
	 xfer_size = snd;
	 if(rcv > snd) xfer_size = rcv;
	 



	 
	 $display("Doing JSP transfer of %d bytes", xfer_size);
	 

	 for(i = 0; i < xfer_size; i=i+1) begin
	   #100
	    jtag_read_write_stream(outstream>>(i*8), 8'h8,0,instream);
`ifdef ADBG_JSP_SUPPORT_MULTI	    
      input_data8[i] = {instream[6:0], inbit};
      inbit = instream[7];
`else
	    input_data8[i] = instream[7:0];
`endif
	 end




	 write_bit(`JTAG_TMS_bit);
	 

	 write_bit(`JTAG_TMS_bit);
	 write_bit(3'h0);
	 
	 end
      endtask
   
   



task set_ir;
input [3:0] irval;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({60'h0,irval}, 8'h4, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task reset_jtag;
integer i;
begin
   for(i = 0; i < 8; i=i+1) begin
      write_bit(`JTAG_TMS_bit);
   end
   write_bit(3'h0);
end
endtask





task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       write_bit(bits);
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   write_bit(bits);
    
end
endtask


task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
    instream = 64'h0;
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       read_write_bit(bits, inbit);
       instream = (instream | (inbit << i));
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   read_write_bit(bits, inbit);
   instream = (instream | (inbit << (len-1)));
end
endtask




task write_bit;
   input [2:0] bitvals;
   begin
       

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask

task read_write_bit;
   input [2:0] bitvals;
   output l_tdi_val;
   begin
       

   l_tdi_val <= jtag_tdi_i;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask




task jtag_out;
  input   [2:0]   bitvals;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 
   end
endtask


task jtag_inout;
  input   [2:0]   bitvals;
  output l_tdi_val;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 

   l_tdi_val <= jtag_tdi_i;
   end
endtask

endmodule