data/full_repos/permissive/170693225/ad_avg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170693225/ad_avg.v:49: Operator ADD expects 16 bits on the RHS, but RHS\'s SIGNED generates 12 bits.\n                                                                : ... In instance ad_avg\n       sum <= $signed(sum) + $signed(ad_ch1_in);  \n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/170693225/ad_avg.v:55: Operator ADD expects 16 bits on the RHS, but RHS\'s SIGNED generates 12 bits.\n                                                                : ... In instance ad_avg\n       sum <= $signed(sum) + $signed(ad_ch1_in);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/170693225/ad_avg.v:61: Operator ADD expects 16 bits on the RHS, but RHS\'s SIGNED generates 12 bits.\n                                                                : ... In instance ad_avg\n       sum <= $signed(sum) + $signed(ad_ch1_in);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/170693225/ad_avg.v:67: Operator ADD expects 16 bits on the RHS, but RHS\'s SIGNED generates 12 bits.\n                                                                : ... In instance ad_avg\n       sum <= $signed(sum) + $signed(ad_ch1_in);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/170693225/ad_avg.v:73: Operator ADD expects 16 bits on the RHS, but RHS\'s SIGNED generates 12 bits.\n                                                                : ... In instance ad_avg\n       sum <= $signed(sum) + $signed(ad_ch1_in);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/170693225/ad_avg.v:79: Operator ADD expects 16 bits on the RHS, but RHS\'s SIGNED generates 12 bits.\n                                                                : ... In instance ad_avg\n       sum <= $signed(sum) + $signed(ad_ch1_in);\n                           ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/170693225/ad_avg.v:116: Unsized numbers/parameters not allowed in concatenations.\n                                                                       : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/3};  \n                                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/170693225/ad_avg.v:116: Unsized numbers/parameters not allowed in replications.\n                                                                       : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/3};  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/170693225/ad_avg.v:116: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 36 or 20 bits.\n                                                                 : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/3};  \n               ^~\n%Warning-WIDTH: data/full_repos/permissive/170693225/ad_avg.v:123: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 12 bits.\n                                                                 : ... In instance ad_avg\n       sum <= $signed(ad_ch1_in);  \n           ^~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/170693225/ad_avg.v:135: Unsized numbers/parameters not allowed in concatenations.\n                                                                       : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/5}; \n                                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/170693225/ad_avg.v:135: Unsized numbers/parameters not allowed in replications.\n                                                                       : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/5}; \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/170693225/ad_avg.v:135: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 36 or 20 bits.\n                                                                 : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/5}; \n               ^~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/170693225/ad_avg.v:144: Unsized numbers/parameters not allowed in concatenations.\n                                                                       : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/6};\n                                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/170693225/ad_avg.v:144: Unsized numbers/parameters not allowed in replications.\n                                                                       : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/6};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/170693225/ad_avg.v:144: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 36 or 20 bits.\n                                                                 : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/6};\n               ^~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/170693225/ad_avg.v:153: Unsized numbers/parameters not allowed in concatenations.\n                                                                       : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/7};\n                                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/170693225/ad_avg.v:153: Unsized numbers/parameters not allowed in replications.\n                                                                       : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/7};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/170693225/ad_avg.v:153: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 36 or 20 bits.\n                                                                 : ... In instance ad_avg\n       ad_data <= {cs_bef[3:0],sum[15:0]/7};\n               ^~\n%Error: Exiting due to 19 warning(s)\n'
module ad_avg(
          input ad_clk,
			 input signed [11:0] ad_ch1_in,
			 input [3:0] cs_now,
 			 
			 output reg set_data,
			 
			 output reg [15:0] ad_data,
			 output reg [3:0] runinhere,
			 output reg [3:0] ad_num,
			 output reg [11:0] avg_data
    );
	 

	 reg signed[15:0] sum;
	 reg [3:0] cs_bef;
	 
	initial
		begin
			sum <= 0;
			cs_bef <= 4'd2;
			set_data <= 0;
			ad_num <= 4'b0;
		end
	 
	always@(posedge ad_clk)
	begin

		runinhere = 4'd3;
		if(cs_bef == cs_now)
			begin
			runinhere = 4'd1;
			case(ad_num)
					4'd0:	
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd1;
							set_data <= 1'b0;
						end
					4'd1:	
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd2;
							set_data <= 1'b0;
						end
					4'd2:
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd3;
							set_data <= 1'b0;
						end
					4'd3:
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd4;
							set_data <= 1'b0;
						end
					4'd4:
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd5;
							set_data <= 1'b0;
						end
					4'd5:
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd6;
							set_data <= 1'b0;
						end
					default:
						begin
							sum <=16'b1010101010101010;
							ad_data <= 16'b1010101010101010;
						end
				endcase
			end
		else if(cs_bef != cs_now)
			begin
				runinhere = 4'd2;
				case(ad_num)
					4'd0:
						begin
							sum <= {4'b0,ad_ch1_in[11:0]};

							ad_data <= {cs_bef[3:0],sum[11:0]};
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd1:	
						begin
							sum <= {4'b0,ad_ch1_in[11:0]}; 

							ad_data <= {cs_bef[3:0],sum[12:1]};
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd2:
						begin
							sum <= {4'b0,ad_ch1_in[11:0]};

							ad_data <= {cs_bef[3:0],sum[15:0]/3};
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd3:
						begin
							sum <= $signed(ad_ch1_in);

							ad_data <= {cs_bef[3:0],sum[13:2]};
							avg_data <= ad_data[11:0];
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd4:
						begin
							sum <= {4'b0,ad_ch1_in[11:0]};

							ad_data <= {cs_bef[3:0],sum[15:0]/5}; 
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd5:
						begin
							sum <= {4'b0,ad_ch1_in[11:0]};

							ad_data <= {cs_bef[3:0],sum[15:0]/6};
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd6:
						begin
							sum <= {4'b0,ad_ch1_in[11:0]};

							ad_data <= {cs_bef[3:0],sum[15:0]/7};
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					default: 
						begin
							sum <=16'b1010101010101010;
							ad_data <= 16'b1010101010101010;
						end
				endcase
			end
	end

endmodule
module ad_avg(
          input ad_clk,
			 input signed [11:0] ad_ch1_in,
			 input [3:0] cs_now,
 			 
			 output reg set_data,
			 
			 output reg [15:0] ad_data,
			 output reg [3:0] runinhere,
			 output reg [3:0] ad_num,
			 output reg [11:0] avg_data
    );

	 

	 reg signed[15:0] sum;
	 reg [3:0] cs_bef;
	 
	initial
		begin
			sum <= 0;
			cs_bef <= 4'd2;
			set_data <= 0;
			ad_num <= 4'b0;
		end
	 
	always@(posedge ad_clk)
	begin

		runinhere = 4'd3;
		if(cs_bef == cs_now)
			begin
			runinhere = 4'd1;
			case(ad_num)
					4'd0:	
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd1;
							set_data <= 1'b0;
						end
					4'd1:	
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd2;
							set_data <= 1'b0;
						end
					4'd2:
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd3;
							set_data <= 1'b0;
						end
					4'd3:
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd4;
							set_data <= 1'b0;
						end
					4'd4:
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd5;
							set_data <= 1'b0;
						end
					4'd5:
						begin
							sum <= $signed(sum) + $signed(ad_ch1_in);
							ad_num <= 4'd6;
							set_data <= 1'b0;
						end
					default:
						begin
							sum <=16'b1010101010101010;
							ad_data <= 16'b1010101010101010;
						end
				endcase
			end
		else if(cs_bef != cs_now)
			begin
				runinhere = 4'd2;
				case(ad_num)
					4'd0:
						begin
							sum <= {4'b0,ad_ch1_in[11:0]};

							ad_data <= {cs_bef[3:0],sum[11:0]};
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd1:	
						begin
							sum <= {4'b0,ad_ch1_in[11:0]}; 

							ad_data <= {cs_bef[3:0],sum[12:1]};
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd2:
						begin
							sum <= {4'b0,ad_ch1_in[11:0]};

							ad_data <= {cs_bef[3:0],sum[15:0]/3};
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd3:
						begin
							sum <= $signed(ad_ch1_in);

							ad_data <= {cs_bef[3:0],sum[13:2]};
							avg_data <= ad_data[11:0];
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd4:
						begin
							sum <= {4'b0,ad_ch1_in[11:0]};

							ad_data <= {cs_bef[3:0],sum[15:0]/5}; 
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd5:
						begin
							sum <= {4'b0,ad_ch1_in[11:0]};

							ad_data <= {cs_bef[3:0],sum[15:0]/6};
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					4'd6:
						begin
							sum <= {4'b0,ad_ch1_in[11:0]};

							ad_data <= {cs_bef[3:0],sum[15:0]/7};
							ad_num <= 4'd0;
							cs_bef <= cs_now;
							set_data <= 1'b1;
						end
					default: 
						begin
							sum <=16'b1010101010101010;
							ad_data <= 16'b1010101010101010;
						end
				endcase
			end
	end

endmodule