data/full_repos/permissive/101548714/Array_Dataflow.v
data/verilator_xmls/f4024878-dec3-4596-9533-f3b39e2d567d.xml
module Array_Mult_Dataflow(a,b,out);
  input [1:0] a,b;
  output [3:0] out;
  
  assign out[0] = a[0] & b[0];
  assign out[1] = (a[0] & b[1]) ^ (a[1] & b[0]);
  assign out[2] = (a[1] & b[1]) ^ ((a[0] & b[1]) & (a[1] & b[0]));
  assign out[3] = (a[1] & b[1]) & ((a[0] & b[1]) & (a[1] & b[0]));
endmodule
module Array_Mult_Dataflow(a,b,out);

  input [1:0] a,b;
  output [3:0] out;
  
  assign out[0] = a[0] & b[0];
  assign out[1] = (a[0] & b[1]) ^ (a[1] & b[0]);
  assign out[2] = (a[1] & b[1]) ^ ((a[0] & b[1]) & (a[1] & b[0]));
  assign out[3] = (a[1] & b[1]) & ((a[0] & b[1]) & (a[1] & b[0]));
endmodule