data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v
 line:25: before: "while"
1: b'%Warning-STMTDLY: data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #50 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #1001 while(!full) begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #10 wr_en = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10 wr_en = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10 wr_en = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10 wr_en = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    initial #10000 $finish;\n            ^\n%Error: data/full_repos/permissive/19478345/reorder_queue/reorder_queue_tb.v:12: Cannot find file containing module: \'reorder_queue\'\n    reorder_queue dut(rst, clk, increment, index_tag, full, wr_en, d, q, valid, stall);\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19478345/reorder_queue,data/full_repos/permissive/19478345/reorder_queue\n             data/full_repos/permissive/19478345/reorder_queue,data/full_repos/permissive/19478345/reorder_queue.v\n             data/full_repos/permissive/19478345/reorder_queue,data/full_repos/permissive/19478345/reorder_queue.sv\n             reorder_queue\n             reorder_queue.v\n             reorder_queue.sv\n             obj_dir/reorder_queue\n             obj_dir/reorder_queue.v\n             obj_dir/reorder_queue.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reorder_queue_tb;
    reg rst, clk;
    reg increment;
    wire [5:0] index_tag;
    wire full;
    reg wr_en;
    reg [7:0] d;
    wire [7:0] q;
    wire valid;
    reg stall;
    
    reorder_queue dut(rst, clk, increment, index_tag, full, wr_en, d, q, valid, stall);
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    initial begin
        rst = 1;
        increment = 0;
        wr_en = 0;
        d = 0;
        stall = 0;
        #50 rst = 0;
        #1001 while(!full) begin
            increment = 1;
            #10;
        end
        wr_en = 1;
        d = 0;
        #10 wr_en = 0;
        #10 wr_en = 1;
        d = 2;
        #10 wr_en = 1;
        d = 1;
        #10 wr_en = 0;

        increment = 0;
        #100 $finish;
    end

    always @(posedge clk) begin
        if(valid)
            $display("output: q:%d time:%d", q, $time);
    end

    initial #10000 $finish;

endmodule
module reorder_queue_tb;

    reg rst, clk;
    reg increment;
    wire [5:0] index_tag;
    wire full;
    reg wr_en;
    reg [7:0] d;
    wire [7:0] q;
    wire valid;
    reg stall;
    
    reorder_queue dut(rst, clk, increment, index_tag, full, wr_en, d, q, valid, stall);
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    initial begin
        rst = 1;
        increment = 0;
        wr_en = 0;
        d = 0;
        stall = 0;
        #50 rst = 0;
        #1001 while(!full) begin
            increment = 1;
            #10;
        end
        wr_en = 1;
        d = 0;
        #10 wr_en = 0;
        #10 wr_en = 1;
        d = 2;
        #10 wr_en = 1;
        d = 1;
        #10 wr_en = 0;

        increment = 0;
        #100 $finish;
    end

    always @(posedge clk) begin
        if(valid)
            $display("output: q:%d time:%d", q, $time);
    end

    initial #10000 $finish;

endmodule