data/full_repos/permissive/115837888/source-7400/74163-tb.v
 line:5: before: "tbassert"
1: b'%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:6: Define or directive not defined: \'`TBASSERT_2_METHOD\'\n`TBASSERT_2_METHOD(tbassert2)\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:7: Define or directive not defined: \'`TBCLK_WAIT_TICK_METHOD\'\n`TBCLK_WAIT_TICK_METHOD(wait_tick)\n^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:37: Unsupported: Ignoring delay on this delayed statement.\nalways #50 Clk = ~Clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:42: syntax error, unexpected \'@\'\n  repeat (2) @(posedge Clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:53: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("74163-tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74163-tb.v:54: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n#225\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n#110\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n#105\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n#95\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n#22\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:199: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:207: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n#97\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:214: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:217: Unsupported: Ignoring delay on this delayed statement.\n#97\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:230: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:245: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:251: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:255: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:261: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:267: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:270: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:272: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:275: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:278: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:281: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:284: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:287: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:289: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:292: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:295: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:298: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:304: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:301: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:307: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:309: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:312: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:315: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:318: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:321: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:323: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:326: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:329: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:332: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:335: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:338: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:340: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:343: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:346: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:349: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:354: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:358: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:361: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:364: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:367: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:371: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:374: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:378: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:381: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:384: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:387: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:391: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:395: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:399: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:402: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:405: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:408: Unsupported: Ignoring delay on this delayed statement.\n#200\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:411: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:414: Unsupported: Ignoring delay on this delayed statement.\n#85\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:417: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:420: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:424: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:427: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:430: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:433: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:436: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:439: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:442: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:445: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:448: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:452: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:455: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:459: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:462: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:464: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:467: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:470: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:478: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:480: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:482: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:485: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:487: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:489: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74163-tb.v:491: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: Exiting due to 7 error(s), 124 warning(s)\n'
module test;

`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
`TBCLK_WAIT_TICK_METHOD(wait_tick)

localparam WIDTH = 3;


reg Clear_bar;
reg Load_bar;
reg ENT;
reg ENP;
reg [WIDTH-1:0] D;
reg Clk;


wire RCO;
wire [WIDTH-1:0] Q;


ttl_74163 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .Clear_bar(Clear_bar),
  .Load_bar(Load_bar),
  .ENT(ENT),
  .ENP(ENP),
  .D(D),
  .Clk(Clk),
  .RCO(RCO),
  .Q(Q)
);

initial Clk = 1'b0;

always #50 Clk = ~Clk;

task parallel_load_and_tick(input [WIDTH-1:0] D_next);
  Load_bar = 1'b0;
  D = D_next;
  repeat (2) @(posedge Clk);
#7
  Load_bar = 1'b1;
endtask

initial
begin
  reg [WIDTH-1:0] D_next;
  reg [WIDTH-1:0] Q_expected;
  integer i;

  $dumpfile("74163-tb.vcd");
  $dumpvars;



#225

  tbassert(Q === 3'bxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#0

  Load_bar = 1'b0;
  D = 3'b000;
#25
  tbassert(Q === 3'bxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#2

  tbassert(Q === 3'bxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#2

  tbassert(Q == 3'b000, "Test 1");
  tbassert(RCO == 1'b0, "Test 1");
#140

  Load_bar = 1'b1;
#175
  tbassert(Q == 3'b000, "Test 2");
  tbassert(RCO == 1'b0, "Test 2");
#0

  Load_bar = 1'b0;
  ENT = 1'b1;
  D = 3'b111;
#125
  Load_bar = 1'b1;
#110
  tbassert(Q == 3'b111, "Test 3");
  tbassert(RCO == 1'b1, "Test 3");
#0
  ENT = 1'b0;
#0



  D_next = 3'b111;

  for (i = 1; i <= 6; i++)
  begin
    Q_expected = D_next;
    D_next = (Q_expected + 2) ^ 5;

    case (i)
      1:
      begin
        ENT = 1'b0;
      end
      2:
      begin
        ENT = 1'b0;
        ENP = 1'b0;
      end
      3:
      begin
        ENT = 1'b1;
        ENP = 1'b0;
      end
      4:
      begin
        ENT = 1'b0;
        ENP = 1'b1;
      end
      5:
      begin
        Clear_bar = 1'b1;
        ENT = 1'b0;
        ENP = 1'b1;
      end
      6:
      begin
        Clear_bar = 1'b1;
        ENT = 1'b1;
        ENP = 1'b0;
      end
    endcase
#75
    tbassert2(Q == Q_expected, "Test", i, "4");
    tbassert2(RCO == 1'b0, "Test", i, "4");
#0

    Load_bar = 1'b0;
    D = D_next;
#100
    tbassert2(Q == D_next, "Test", i, "4");
    tbassert2(RCO == 1'b0, "Test", i, "4");
#0

    Load_bar = 1'b1;
#105
    tbassert2(Q == D_next, "Test", i, "4");
    tbassert2(RCO == 1'b0, "Test", i, "4");

  end



  tbassert2(Q == 3'b011, "Test", 6, "4");
#175



  wait_tick();
#7

  Clear_bar = 1'b0;
#95

  tbassert(Q == 3'b011, "Test 5");
  tbassert(RCO == 1'b0, "Test 5");
#2

  tbassert(Q == 3'b000, "Test 5");
  tbassert(RCO == 1'b0, "Test 5");
#150
  Clear_bar = 1'b1;
#50
  ENT = 1'b1;
  parallel_load_and_tick(3'b111);
#70

  Clear_bar = 1'b0;
#22

  tbassert(Q == 3'b111, "Test 6");
  tbassert(RCO == 1'b1, "Test 6");
#5

  tbassert(Q == 3'b000, "Test 6");
  tbassert(RCO == 1'b0, "Test 6");
#10

  Clear_bar = 1'b1;
#120
  tbassert(Q == 3'b000, "Test 7");
  tbassert(RCO == 1'b0, "Test 7");
#50



  Clear_bar = 1'bx;
  Load_bar = 1'bx;
  ENT = 1'bx;
  ENP = 1'bx;
#15
  parallel_load_and_tick(3'bxxx);
#0
  Load_bar = 1'bx;
#97
  tbassert(Q === 3'bxxx, "Test 8");
  tbassert(RCO === 1'bx, "Test 8");
#0

  Clear_bar = 1'b0;
#97
  tbassert(Q === 3'bxxx, "Test 8");
  tbassert(RCO === 1'bx, "Test 8");
#2

  tbassert(Q == 3'b000, "Test 8");
  tbassert(RCO == 1'b0, "Test 8");
#15

  Clear_bar = 1'b1;
#120
  tbassert(Q == 3'b000, "Test 9");
  tbassert(RCO == 1'b0, "Test 9");
#0
  Load_bar = 1'b1;
#80
  tbassert(Q == 3'b000, "Test 9");
  tbassert(RCO == 1'b0, "Test 9");
#0




  ENT = 1'b0;
  ENP = 1'b1;
#7
  tbassert(Q == 3'b000, "Test 10");
  tbassert(RCO == 1'b0, "Test 10");
#50
  tbassert(Q == 3'b000, "Test 10");
  tbassert(RCO == 1'b0, "Test 10");
#100
  tbassert(Q == 3'b000, "Test 10");
  tbassert(RCO == 1'b0, "Test 10");
#15

  ENT = 1'b1;
  ENP = 1'b0;
#7
  tbassert(Q == 3'b000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#50
  tbassert(Q == 3'b000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#100
  tbassert(Q == 3'b000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#0

  wait_tick();
#15
  Load_bar = 1'b0;
  D = 3'b111;
#15
  Load_bar = 1'b1;
#7
  tbassert(Q == 3'b000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#50
  tbassert(Q == 3'b000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#100
  tbassert(Q == 3'b000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#0

  wait_tick();
#20
  ENT = 1'b1;
  ENP = 1'b1;
#15
  ENT = 1'b0;
#15
  tbassert(Q == 3'b000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#50
  tbassert(Q == 3'b000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#100
  tbassert(Q == 3'b000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#20

  parallel_load_and_tick(3'b111);
#50


#175
  tbassert(Q == 3'b111, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#0
  ENP = 1'b0;
#50
  tbassert(Q == 3'b111, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#100
  tbassert(Q == 3'b111, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#0

  wait_tick();
#25
  Load_bar = 1'b0;
  D = 3'b010;
#15
  Load_bar = 1'b1;
#7
  tbassert(Q == 3'b111, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#50
  tbassert(Q == 3'b111, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#100
  tbassert(Q == 3'b111, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#0

  wait_tick();
#15
  ENT = 1'b1;
  ENP = 1'b1;
#15
  ENT = 1'b0;
#7
  tbassert(Q == 3'b111, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#50
  tbassert(Q == 3'b111, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#100
  tbassert(Q == 3'b111, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#0



  wait_tick();
#10

  ENT = 1'b1;
  ENP = 1'b1;
#40
  tbassert(Q == 3'b111, "Test 17");
  tbassert(RCO == 1'b1, "Test 17");
#50
  tbassert(Q == 3'b111, "Test 17");
  tbassert(RCO == 1'b1, "Test 17");
#7
  tbassert(Q == 3'b000, "Test 17");
  tbassert(RCO == 1'b0, "Test 17");
#90

  tbassert(Q == 3'b000, "Test 18");
  tbassert(RCO == 1'b0, "Test 18");
#10
  tbassert(Q == 3'b001, "Test 18");
  tbassert(RCO == 1'b0, "Test 18");
#90

  tbassert(Q == 3'b001, "Test 19");
  tbassert(RCO == 1'b0, "Test 19");
#10
  tbassert(Q == 3'b010, "Test 19");
  tbassert(RCO == 1'b0, "Test 19");
#7

  parallel_load_and_tick(3'b110);
#0
  tbassert(Q == 3'b110, "Test 20");
  tbassert(RCO == 1'b0, "Test 20");
#100

  tbassert(Q == 3'b111, "Test 21");
  tbassert(RCO == 1'b1, "Test 21");
#100

  tbassert(Q == 3'b000, "Test 22");
  tbassert(RCO == 1'b0, "Test 22");
#100

  tbassert(Q == 3'b001, "Test 23");
  tbassert(RCO == 1'b0, "Test 23");
#0

  ENP = 1'b0;
#50
  tbassert(Q == 3'b001, "Test 24");
  tbassert(RCO == 1'b0, "Test 24");
#50
  tbassert(Q == 3'b001, "Test 24");
  tbassert(RCO == 1'b0, "Test 24");
#200
  tbassert(Q == 3'b001, "Test 24");
  tbassert(RCO == 1'b0, "Test 24");
#0

  ENP = 1'b1;
#85
  tbassert(Q == 3'b001, "Test 25");
  tbassert(RCO == 1'b0, "Test 25");
#15
  tbassert(Q == 3'b010, "Test 25");
  tbassert(RCO == 1'b0, "Test 25");
#100

  tbassert(Q == 3'b011, "Test 26");
  tbassert(RCO == 1'b0, "Test 26");
#0

  Clear_bar = 1'b0;
#90
  tbassert(Q == 3'b011, "Test 27");
  tbassert(RCO == 1'b0, "Test 27");
#10
  tbassert(Q == 3'b000, "Test 27");
  tbassert(RCO == 1'b0, "Test 27");
#0

  Clear_bar = 1'b1;
#90
  tbassert(Q == 3'b000, "Test 28");
  tbassert(RCO == 1'b0, "Test 28");
#10
  tbassert(Q == 3'b001, "Test 28");
  tbassert(RCO == 1'b0, "Test 28");
#50

  Clear_bar = 1'b0;
#50
  Clear_bar = 1'b1;
  parallel_load_and_tick(3'b011);
#90

  tbassert(Q == 3'b011, "Test 29");
  tbassert(RCO == 1'b0, "Test 29");
#10
  tbassert(Q == 3'b100, "Test 29");
  tbassert(RCO == 1'b0, "Test 29");
#20


  ENP = 1'b0;
#50
  tbassert(Q == 3'b100, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#0
  ENP = 1'b1;
#2
  tbassert(Q == 3'b100, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#50
  tbassert(Q == 3'b101, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#0




  ENT = 1'b0;
  ENP = 1'b1;
  parallel_load_and_tick(3'b111);
#100
  tbassert(RCO == 1'b0, "Test 31");
#10
  ENT = 1'b1;
#15
  tbassert(Q == 3'b111, "Test 31");
  tbassert(RCO == 1'b1, "Test 31");
#0
  ENT = 1'b0;
#15
  tbassert(RCO == 1'b0, "Test 31");
#0
  wait_tick();
#50
  $finish;
end

endmodule
module test;


`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
`TBCLK_WAIT_TICK_METHOD(wait_tick)

localparam WIDTH = 3;


reg Clear_bar;
reg Load_bar;
reg ENT;
reg ENP;
reg [WIDTH-1:0] D;
reg Clk;


wire RCO;
wire [WIDTH-1:0] Q;


ttl_74163 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .Clear_bar(Clear_bar),
  .Load_bar(Load_bar),
  .ENT(ENT),
  .ENP(ENP),
  .D(D),
  .Clk(Clk),
  .RCO(RCO),
  .Q(Q)
);

initial Clk = 1'b0;

always #50 Clk = ~Clk;

task parallel_load_and_tick(input [WIDTH-1:0] D_next);
  Load_bar = 1'b0;
  D = D_next;
  repeat (2) @(posedge Clk);
#7
  Load_bar = 1'b1;
endtask

initial
begin
  reg [WIDTH-1:0] D_next;
  reg [WIDTH-1:0] Q_expected;
  integer i;

  $dumpfile("74163-tb.vcd");
  $dumpvars;



#225

  tbassert(Q === 3'bxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#0

  Load_bar = 1'b0;
  D = 3'b000;
#25
  tbassert(Q === 3'bxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#2

  tbassert(Q === 3'bxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#2

  tbassert(Q == 3'b000, "Test 1");
  tbassert(RCO == 1'b0, "Test 1");
#140

  Load_bar = 1'b1;
#175
  tbassert(Q == 3'b000, "Test 2");
  tbassert(RCO == 1'b0, "Test 2");
#0

  Load_bar = 1'b0;
  ENT = 1'b1;
  D = 3'b111;
#125
  Load_bar = 1'b1;
#110
  tbassert(Q == 3'b111, "Test 3");
  tbassert(RCO == 1'b1, "Test 3");
#0
  ENT = 1'b0;
#0



  D_next = 3'b111;

  for (i = 1; i <= 6; i++)
  begin
    Q_expected = D_next;
    D_next = (Q_expected + 2) ^ 5;

    case (i)
      1:
      begin
        ENT = 1'b0;
      end
      2:
      begin
        ENT = 1'b0;
        ENP = 1'b0;
      end
      3:
      begin
        ENT = 1'b1;
        ENP = 1'b0;
      end
      4:
      begin
        ENT = 1'b0;
        ENP = 1'b1;
      end
      5:
      begin
        Clear_bar = 1'b1;
        ENT = 1'b0;
        ENP = 1'b1;
      end
      6:
      begin
        Clear_bar = 1'b1;
        ENT = 1'b1;
        ENP = 1'b0;
      end
    endcase
#75
    tbassert2(Q == Q_expected, "Test", i, "4");
    tbassert2(RCO == 1'b0, "Test", i, "4");
#0

    Load_bar = 1'b0;
    D = D_next;
#100
    tbassert2(Q == D_next, "Test", i, "4");
    tbassert2(RCO == 1'b0, "Test", i, "4");
#0

    Load_bar = 1'b1;
#105
    tbassert2(Q == D_next, "Test", i, "4");
    tbassert2(RCO == 1'b0, "Test", i, "4");

  end



  tbassert2(Q == 3'b011, "Test", 6, "4");
#175



  wait_tick();
#7

  Clear_bar = 1'b0;
#95

  tbassert(Q == 3'b011, "Test 5");
  tbassert(RCO == 1'b0, "Test 5");
#2

  tbassert(Q == 3'b000, "Test 5");
  tbassert(RCO == 1'b0, "Test 5");
#150
  Clear_bar = 1'b1;
#50
  ENT = 1'b1;
  parallel_load_and_tick(3'b111);
#70

  Clear_bar = 1'b0;
#22

  tbassert(Q == 3'b111, "Test 6");
  tbassert(RCO == 1'b1, "Test 6");
#5

  tbassert(Q == 3'b000, "Test 6");
  tbassert(RCO == 1'b0, "Test 6");
#10

  Clear_bar = 1'b1;
#120
  tbassert(Q == 3'b000, "Test 7");
  tbassert(RCO == 1'b0, "Test 7");
#50



  Clear_bar = 1'bx;
  Load_bar = 1'bx;
  ENT = 1'bx;
  ENP = 1'bx;
#15
  parallel_load_and_tick(3'bxxx);
#0
  Load_bar = 1'bx;
#97
  tbassert(Q === 3'bxxx, "Test 8");
  tbassert(RCO === 1'bx, "Test 8");
#0

  Clear_bar = 1'b0;
#97
  tbassert(Q === 3'bxxx, "Test 8");
  tbassert(RCO === 1'bx, "Test 8");
#2

  tbassert(Q == 3'b000, "Test 8");
  tbassert(RCO == 1'b0, "Test 8");
#15

  Clear_bar = 1'b1;
#120
  tbassert(Q == 3'b000, "Test 9");
  tbassert(RCO == 1'b0, "Test 9");
#0
  Load_bar = 1'b1;
#80
  tbassert(Q == 3'b000, "Test 9");
  tbassert(RCO == 1'b0, "Test 9");
#0




  ENT = 1'b0;
  ENP = 1'b1;
#7
  tbassert(Q == 3'b000, "Test 10");
  tbassert(RCO == 1'b0, "Test 10");
#50
  tbassert(Q == 3'b000, "Test 10");
  tbassert(RCO == 1'b0, "Test 10");
#100
  tbassert(Q == 3'b000, "Test 10");
  tbassert(RCO == 1'b0, "Test 10");
#15

  ENT = 1'b1;
  ENP = 1'b0;
#7
  tbassert(Q == 3'b000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#50
  tbassert(Q == 3'b000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#100
  tbassert(Q == 3'b000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#0

  wait_tick();
#15
  Load_bar = 1'b0;
  D = 3'b111;
#15
  Load_bar = 1'b1;
#7
  tbassert(Q == 3'b000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#50
  tbassert(Q == 3'b000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#100
  tbassert(Q == 3'b000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#0

  wait_tick();
#20
  ENT = 1'b1;
  ENP = 1'b1;
#15
  ENT = 1'b0;
#15
  tbassert(Q == 3'b000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#50
  tbassert(Q == 3'b000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#100
  tbassert(Q == 3'b000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#20

  parallel_load_and_tick(3'b111);
#50


#175
  tbassert(Q == 3'b111, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#0
  ENP = 1'b0;
#50
  tbassert(Q == 3'b111, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#100
  tbassert(Q == 3'b111, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#0

  wait_tick();
#25
  Load_bar = 1'b0;
  D = 3'b010;
#15
  Load_bar = 1'b1;
#7
  tbassert(Q == 3'b111, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#50
  tbassert(Q == 3'b111, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#100
  tbassert(Q == 3'b111, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#0

  wait_tick();
#15
  ENT = 1'b1;
  ENP = 1'b1;
#15
  ENT = 1'b0;
#7
  tbassert(Q == 3'b111, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#50
  tbassert(Q == 3'b111, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#100
  tbassert(Q == 3'b111, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#0



  wait_tick();
#10

  ENT = 1'b1;
  ENP = 1'b1;
#40
  tbassert(Q == 3'b111, "Test 17");
  tbassert(RCO == 1'b1, "Test 17");
#50
  tbassert(Q == 3'b111, "Test 17");
  tbassert(RCO == 1'b1, "Test 17");
#7
  tbassert(Q == 3'b000, "Test 17");
  tbassert(RCO == 1'b0, "Test 17");
#90

  tbassert(Q == 3'b000, "Test 18");
  tbassert(RCO == 1'b0, "Test 18");
#10
  tbassert(Q == 3'b001, "Test 18");
  tbassert(RCO == 1'b0, "Test 18");
#90

  tbassert(Q == 3'b001, "Test 19");
  tbassert(RCO == 1'b0, "Test 19");
#10
  tbassert(Q == 3'b010, "Test 19");
  tbassert(RCO == 1'b0, "Test 19");
#7

  parallel_load_and_tick(3'b110);
#0
  tbassert(Q == 3'b110, "Test 20");
  tbassert(RCO == 1'b0, "Test 20");
#100

  tbassert(Q == 3'b111, "Test 21");
  tbassert(RCO == 1'b1, "Test 21");
#100

  tbassert(Q == 3'b000, "Test 22");
  tbassert(RCO == 1'b0, "Test 22");
#100

  tbassert(Q == 3'b001, "Test 23");
  tbassert(RCO == 1'b0, "Test 23");
#0

  ENP = 1'b0;
#50
  tbassert(Q == 3'b001, "Test 24");
  tbassert(RCO == 1'b0, "Test 24");
#50
  tbassert(Q == 3'b001, "Test 24");
  tbassert(RCO == 1'b0, "Test 24");
#200
  tbassert(Q == 3'b001, "Test 24");
  tbassert(RCO == 1'b0, "Test 24");
#0

  ENP = 1'b1;
#85
  tbassert(Q == 3'b001, "Test 25");
  tbassert(RCO == 1'b0, "Test 25");
#15
  tbassert(Q == 3'b010, "Test 25");
  tbassert(RCO == 1'b0, "Test 25");
#100

  tbassert(Q == 3'b011, "Test 26");
  tbassert(RCO == 1'b0, "Test 26");
#0

  Clear_bar = 1'b0;
#90
  tbassert(Q == 3'b011, "Test 27");
  tbassert(RCO == 1'b0, "Test 27");
#10
  tbassert(Q == 3'b000, "Test 27");
  tbassert(RCO == 1'b0, "Test 27");
#0

  Clear_bar = 1'b1;
#90
  tbassert(Q == 3'b000, "Test 28");
  tbassert(RCO == 1'b0, "Test 28");
#10
  tbassert(Q == 3'b001, "Test 28");
  tbassert(RCO == 1'b0, "Test 28");
#50

  Clear_bar = 1'b0;
#50
  Clear_bar = 1'b1;
  parallel_load_and_tick(3'b011);
#90

  tbassert(Q == 3'b011, "Test 29");
  tbassert(RCO == 1'b0, "Test 29");
#10
  tbassert(Q == 3'b100, "Test 29");
  tbassert(RCO == 1'b0, "Test 29");
#20


  ENP = 1'b0;
#50
  tbassert(Q == 3'b100, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#0
  ENP = 1'b1;
#2
  tbassert(Q == 3'b100, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#50
  tbassert(Q == 3'b101, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#0




  ENT = 1'b0;
  ENP = 1'b1;
  parallel_load_and_tick(3'b111);
#100
  tbassert(RCO == 1'b0, "Test 31");
#10
  ENT = 1'b1;
#15
  tbassert(Q == 3'b111, "Test 31");
  tbassert(RCO == 1'b1, "Test 31");
#0
  ENT = 1'b0;
#15
  tbassert(RCO == 1'b0, "Test 31");
#0
  wait_tick();
#50
  $finish;
end

endmodule