data/full_repos/permissive/167489907/Testbenches/regfile32x64_under_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_under_test.v:12: Unsupported: Ignoring delay on this delayed statement.\n #5; clock = ~clock;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_under_test.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_under_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_under_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_under_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_under_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_under_test.v:56: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_under_test.v:63: Unsupported: Ignoring delay on this delayed statement.\n #10; $stop;\n ^\n%Error: data/full_repos/permissive/167489907/Testbenches/regfile32x64_under_test.v:9: Cannot find file containing module: \'regfile32x64\'\nregfile32x64 dut (.rdDataA(rdDataA), .rdDataB(rdDataB), .rdAddrA(rdAddrA), .rdAddrB(rdAddrB), .wrData(wrData), .wrAddr(wrAddr), .write(write), .reset(reset), .clk(clock));\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/regfile32x64\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/regfile32x64.v\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/regfile32x64.sv\n             regfile32x64\n             regfile32x64.v\n             regfile32x64.sv\n             obj_dir/regfile32x64\n             obj_dir/regfile32x64.v\n             obj_dir/regfile32x64.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regfile32x64_under_test;

	reg [4:0]rdAddrA, rdAddrB, wrAddr;
	reg [63:0]wrData;
	reg write, reset, clock;

	wire [63:0]rdDataA, rdDataB;
	
regfile32x64 dut (.rdDataA(rdDataA), .rdDataB(rdDataB), .rdAddrA(rdAddrA), .rdAddrB(rdAddrB), .wrData(wrData), .wrAddr(wrAddr), .write(write), .reset(reset), .clk(clock));

always begin
	#5; clock = ~clock;
end

initial begin
	clock = 1'b0;
	reset = 1'b1;
	write = 1'b0;
	wrAddr = 5'b0;
	wrData = 64'b0;
	#10;
	reset = 1'b0;
	rdAddrA = 5'b0;
	wrAddr = 5'b00000;
	wrData = 64'hFFFFFFFFFFFFFFFF;
	#20;
	
	#5;
	write = 1'b1;
	#5;
	wrAddr = 5'b00001;
	wrData = 64'hAAAAAAAAAAAAAAAA;
	#20;

	write = 1'b0;
	rdAddrA = 5'b00000;
	rdAddrB = 5'b00001;
	#10;



	reset = 1'b1;
	rdAddrA = 5'b0;
	rdAddrB = 5'b00001;
	#10; $stop;
end
endmodule
module regfile32x64_under_test;


	reg [4:0]rdAddrA, rdAddrB, wrAddr;
	reg [63:0]wrData;
	reg write, reset, clock;

	wire [63:0]rdDataA, rdDataB;
	
regfile32x64 dut (.rdDataA(rdDataA), .rdDataB(rdDataB), .rdAddrA(rdAddrA), .rdAddrB(rdAddrB), .wrData(wrData), .wrAddr(wrAddr), .write(write), .reset(reset), .clk(clock));

always begin
	#5; clock = ~clock;
end

initial begin
	clock = 1'b0;
	reset = 1'b1;
	write = 1'b0;
	wrAddr = 5'b0;
	wrData = 64'b0;
	#10;
	reset = 1'b0;
	rdAddrA = 5'b0;
	wrAddr = 5'b00000;
	wrData = 64'hFFFFFFFFFFFFFFFF;
	#20;
	
	#5;
	write = 1'b1;
	#5;
	wrAddr = 5'b00001;
	wrData = 64'hAAAAAAAAAAAAAAAA;
	#20;

	write = 1'b0;
	rdAddrA = 5'b00000;
	rdAddrB = 5'b00001;
	#10;



	reset = 1'b1;
	rdAddrA = 5'b0;
	rdAddrB = 5'b00001;
	#10; $stop;
end
endmodule