data/full_repos/permissive/136794488/source/ledmodule.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136794488/source/ledmodule.v:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                          : ... In instance ledmodule\n  in0 = 4\'b0;\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136794488/source/ledmodule.v:18: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                          : ... In instance ledmodule\n  in1 = 4\'b0;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module ledmodule(clock,in0,in1,out0,out1,out2,
						reset,sw,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5);
						
	input         clock;
	input [31:0]  out0,out1,out2;
	input         reset;
	input [7:0]   sw;
 	
	output [31:0] in0,in1;
	output [6:0]  HEX0,HEX1,HEX2,HEX3,HEX4,HEX5;
	
	wire [31:0]  out0,out1,out2;
	reg [31:0]   in0,in1;
	
	initial
	begin
		in0 = 4'b0;
		in1 = 4'b0;
	end
	
	always @(posedge clock or negedge reset)
	begin
		if(reset == 0)
		begin
			in0 <= 32'b0;
			in1 <= 32'b0;
		end 
		else 
		begin
			in0 <= {28'b0,sw[3:0]};
			in1 <= {28'b0,sw[7:4]};
		end
	end
	
	sevenseg  LED8_0 ( in0[3:0], HEX0 );   
	sevenseg  LED8_1 ( in1[3:0], HEX1 );        
	sevenseg  LED8_2 ( out0[3:0], HEX2 );   
	sevenseg  LED8_4 ( out0[7:4], HEX3 );
	sevenseg  LED8_5 ( out1[3:0], HEX4 );
	sevenseg  LED8_6 ( out2[3:0], HEX5 );
	
endmodule
module ledmodule(clock,in0,in1,out0,out1,out2,
						reset,sw,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5);

						
	input         clock;
	input [31:0]  out0,out1,out2;
	input         reset;
	input [7:0]   sw;
 	
	output [31:0] in0,in1;
	output [6:0]  HEX0,HEX1,HEX2,HEX3,HEX4,HEX5;
	
	wire [31:0]  out0,out1,out2;
	reg [31:0]   in0,in1;
	
	initial
	begin
		in0 = 4'b0;
		in1 = 4'b0;
	end
	
	always @(posedge clock or negedge reset)
	begin
		if(reset == 0)
		begin
			in0 <= 32'b0;
			in1 <= 32'b0;
		end 
		else 
		begin
			in0 <= {28'b0,sw[3:0]};
			in1 <= {28'b0,sw[7:4]};
		end
	end
	
	sevenseg  LED8_0 ( in0[3:0], HEX0 );   
	sevenseg  LED8_1 ( in1[3:0], HEX1 );        
	sevenseg  LED8_2 ( out0[3:0], HEX2 );   
	sevenseg  LED8_4 ( out0[7:4], HEX3 );
	sevenseg  LED8_5 ( out1[3:0], HEX4 );
	sevenseg  LED8_6 ( out2[3:0], HEX5 );
	
endmodule