data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Error: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_rconst2in1.v:30: Cannot find file containing module: \'rconst2in1\'\n    rconst2in1 uut (\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21918028/high_throughput_core/testbench,data/full_repos/permissive/21918028/rconst2in1\n             data/full_repos/permissive/21918028/high_throughput_core/testbench,data/full_repos/permissive/21918028/rconst2in1.v\n             data/full_repos/permissive/21918028/high_throughput_core/testbench,data/full_repos/permissive/21918028/rconst2in1.sv\n             rconst2in1\n             rconst2in1.v\n             rconst2in1.sv\n             obj_dir/rconst2in1\n             obj_dir/rconst2in1.v\n             obj_dir/rconst2in1.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_rconst2in1;


    reg [11:0] i;


    wire [63:0] rc1;
    wire [63:0] rc2;


    rconst2in1 uut (
        .i(i), 
        .rc1(rc1), 
        .rc2(rc2)
    );

    initial begin

        i = 0;


        #100;
        

        i=0; i[0] = 1;
        #(`P/2);
        if(rc1 !== 64'h1) begin $display("E"); $finish; end
        if(rc2 !== 64'h8082) begin $display("E"); $finish; end
        i=0; i[1] = 1;
        #(`P/2);
        if(rc1 !== 64'h800000000000808a) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000080008000) begin $display("E"); $finish; end
        i=0; i[2] = 1;
        #(`P/2);
        if(rc1 !== 64'h808b) begin $display("E"); $finish; end
        if(rc2 !== 64'h80000001) begin $display("E"); $finish; end
        i=0; i[3] = 1;
        #(`P/2);
        if(rc1 !== 64'h8000000080008081) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000000008009) begin $display("E"); $finish; end
        i=0; i[4] = 1;
        #(`P/2);
        if(rc1 !== 64'h8a) begin $display("E"); $finish; end
        if(rc2 !== 64'h88) begin $display("E"); $finish; end
        i=0; i[5] = 1;
        #(`P/2);
        if(rc1 !== 64'h80008009) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000a) begin $display("E"); $finish; end
        i=0; i[6] = 1;
        #(`P/2);
        if(rc1 !== 64'h8000808b) begin $display("E"); $finish; end
        if(rc2 !== 64'h800000000000008b) begin $display("E"); $finish; end
        i=0; i[7] = 1;
        #(`P/2);
        if(rc1 !== 64'h8000000000008089) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000000008003) begin $display("E"); $finish; end
        i=0; i[8] = 1;
        #(`P/2);
        if(rc1 !== 64'h8000000000008002) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000000000080) begin $display("E"); $finish; end
        i=0; i[9] = 1;
        #(`P/2);
        if(rc1 !== 64'h800a) begin $display("E"); $finish; end
        if(rc2 !== 64'h800000008000000a) begin $display("E"); $finish; end
        i=0; i[10] = 1;
        #(`P/2);
        if(rc1 !== 64'h8000000080008081) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000000008080) begin $display("E"); $finish; end
        i=0; i[11] = 1;
        #(`P/2);
        if(rc1 !== 64'h80000001) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000080008008) begin $display("E"); $finish; end
        $display("Good!");
        $finish;
    end
      
endmodule
module test_rconst2in1;



    reg [11:0] i;


    wire [63:0] rc1;
    wire [63:0] rc2;


    rconst2in1 uut (
        .i(i), 
        .rc1(rc1), 
        .rc2(rc2)
    );

    initial begin

        i = 0;


        #100;
        

        i=0; i[0] = 1;
        #(`P/2);
        if(rc1 !== 64'h1) begin $display("E"); $finish; end
        if(rc2 !== 64'h8082) begin $display("E"); $finish; end
        i=0; i[1] = 1;
        #(`P/2);
        if(rc1 !== 64'h800000000000808a) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000080008000) begin $display("E"); $finish; end
        i=0; i[2] = 1;
        #(`P/2);
        if(rc1 !== 64'h808b) begin $display("E"); $finish; end
        if(rc2 !== 64'h80000001) begin $display("E"); $finish; end
        i=0; i[3] = 1;
        #(`P/2);
        if(rc1 !== 64'h8000000080008081) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000000008009) begin $display("E"); $finish; end
        i=0; i[4] = 1;
        #(`P/2);
        if(rc1 !== 64'h8a) begin $display("E"); $finish; end
        if(rc2 !== 64'h88) begin $display("E"); $finish; end
        i=0; i[5] = 1;
        #(`P/2);
        if(rc1 !== 64'h80008009) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000a) begin $display("E"); $finish; end
        i=0; i[6] = 1;
        #(`P/2);
        if(rc1 !== 64'h8000808b) begin $display("E"); $finish; end
        if(rc2 !== 64'h800000000000008b) begin $display("E"); $finish; end
        i=0; i[7] = 1;
        #(`P/2);
        if(rc1 !== 64'h8000000000008089) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000000008003) begin $display("E"); $finish; end
        i=0; i[8] = 1;
        #(`P/2);
        if(rc1 !== 64'h8000000000008002) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000000000080) begin $display("E"); $finish; end
        i=0; i[9] = 1;
        #(`P/2);
        if(rc1 !== 64'h800a) begin $display("E"); $finish; end
        if(rc2 !== 64'h800000008000000a) begin $display("E"); $finish; end
        i=0; i[10] = 1;
        #(`P/2);
        if(rc1 !== 64'h8000000080008081) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000000008080) begin $display("E"); $finish; end
        i=0; i[11] = 1;
        #(`P/2);
        if(rc1 !== 64'h80000001) begin $display("E"); $finish; end
        if(rc2 !== 64'h8000000080008008) begin $display("E"); $finish; end
        $display("Good!");
        $finish;
    end
      
endmodule