data/full_repos/permissive/188421373/src/tb/tb_xtea.v
 line:135: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:118: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_HALF_PERIOD;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:132: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:165: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:232: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:251: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Error: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:98: Cannot find file containing module: \'xtea\'\n  xtea dut(\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/188421373/src/tb,data/full_repos/permissive/188421373/xtea\n             data/full_repos/permissive/188421373/src/tb,data/full_repos/permissive/188421373/xtea.v\n             data/full_repos/permissive/188421373/src/tb,data/full_repos/permissive/188421373/xtea.sv\n             xtea\n             xtea.v\n             xtea.sv\n             obj_dir/xtea\n             obj_dir/xtea.v\n             obj_dir/xtea.sv\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:228: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'address\' generates 12 bits.\n                                                                         : ... In instance tb_xtea\n      tb_address = address;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:248: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'address\' generates 12 bits.\n                                                                         : ... In instance tb_xtea\n      tb_address = address;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:271: Operator TASKREF \'read_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_STATUS\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      read_word(ADDR_STATUS);\n      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:273: Operator TASKREF \'read_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_STATUS\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n        read_word(ADDR_STATUS);\n        ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:290: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_KEY0\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_KEY0, 32\'h00010203);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:291: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_KEY1\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_KEY1, 32\'h04050607);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:292: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_KEY2\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_KEY2, 32\'h08090a0b);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:293: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_KEY3\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_KEY3, 32\'h0c0d0e0f);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:295: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_BLOCK0\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_BLOCK0, 32\'h41424344);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:296: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_BLOCK1\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_BLOCK1, 32\'h45464748);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:298: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_CONFIG\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_CONFIG, 32\'h1);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:299: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_CTRL\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_CTRL, 32\'h2);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:303: Operator TASKREF \'read_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_RESULT0\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      read_word(ADDR_RESULT0);\n      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:305: Operator TASKREF \'read_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_RESULT1\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      read_word(ADDR_RESULT1);\n      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:336: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_KEY0\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_KEY0, 32\'h00010203);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:337: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_KEY1\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_KEY1, 32\'h04050607);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:338: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_KEY2\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_KEY2, 32\'h08090a0b);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:339: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_KEY3\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_KEY3, 32\'h0c0d0e0f);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:341: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_BLOCK0\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_BLOCK0, 32\'h497df3d0);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:342: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_BLOCK1\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_BLOCK1, 32\'h72612cb5);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:344: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_CONFIG\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_CONFIG, 32\'h0);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:345: Operator TASKREF \'write_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_CTRL\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      write_word(ADDR_CTRL, 32\'h2);\n      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:349: Operator TASKREF \'read_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_RESULT0\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      read_word(ADDR_RESULT0);\n      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188421373/src/tb/tb_xtea.v:351: Operator TASKREF \'read_word\' expects 12 bits on the Function Argument, but Function Argument\'s VARREF \'ADDR_RESULT1\' generates 8 bits.\n                                                                         : ... In instance tb_xtea\n      read_word(ADDR_RESULT1);\n      ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 29 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_xtea();




  parameter DEBUG     = 0;
  parameter DUMP_WAIT = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;

  localparam ADDR_NAME0        = 8'h00;
  localparam ADDR_NAME1        = 8'h01;
  localparam ADDR_VERSION      = 8'h02;

  localparam ADDR_CTRL         = 8'h08;
  localparam CTRL_NEXT_BIT     = 1;

  localparam ADDR_STATUS       = 8'h09;
  localparam STATUS_READY_BIT  = 0;

  localparam ADDR_CONFIG       = 8'h0a;
  localparam CONFIG_ENCDEC_BIT = 0;

  localparam ADDR_KEY0         = 8'h10;
  localparam ADDR_KEY1         = 8'h11;
  localparam ADDR_KEY2         = 8'h12;
  localparam ADDR_KEY3         = 8'h13;

  localparam ADDR_BLOCK0       = 8'h20;
  localparam ADDR_BLOCK1       = 8'h21;

  localparam ADDR_RESULT0      = 8'h30;
  localparam ADDR_RESULT1      = 8'h31;




  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;
  reg          tb_monitor;

  reg           tb_clk;
  reg           tb_reset_n;
  reg           tb_cs;
  reg           tb_we;
  reg [7 : 0]   tb_address;
  reg [31 : 0]  tb_write_data;
  wire [31 : 0] tb_read_data;

  reg [31 : 0] read_data;





  xtea dut(
           .clk(tb_clk),
           .reset_n(tb_reset_n),

           .cs(tb_cs),
           .we(tb_we),

           .address(tb_address),
           .write_data(tb_write_data),
           .read_data(tb_read_data)
           );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD;
      tb_clk = !tb_clk;
    end








  always
    begin : sys_monitor
      cycle_ctr = cycle_ctr + 1;
      #(CLK_PERIOD);
      if (tb_monitor)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state;
    begin
      $display("State of DUT");
      $display("------------");
      $display("Cycle: %08d", cycle_ctr);
      $display("Inputs and outputs:");
      $display("");
    end
  endtask







  task reset_dut;
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(2 * CLK_PERIOD);
      tb_reset_n = 1;
    end
  endtask







  task display_test_result;
    begin
      if (error_ctr == 0)
        begin
          $display("*** All %02d test cases completed successfully", tc_ctr);
        end
      else
        begin
          $display("*** %02d tests completed - %02d test cases did not complete successfully.",
                   tc_ctr, error_ctr);
        end
    end
  endtask








  task init_sim;
    begin
      cycle_ctr  = 0;
      error_ctr  = 0;
      tc_ctr     = 0;
      tb_monitor = 0;

      tb_clk        = 1'h0;
      tb_reset_n    = 1'h1;
      tb_cs         = 1'h0;
      tb_we         = 1'h0;
      tb_address    = 8'h0;
      tb_write_data = 32'h0;
    end
  endtask







  task write_word(input [11 : 0] address,
                  input [31 : 0] word);
    begin
      if (DEBUG)
        begin
          $display("*** Writing 0x%08x to 0x%02x.", word, address);
          $display("");
        end

      tb_address = address;
      tb_write_data = word;
      tb_cs = 1;
      tb_we = 1;
      #(2 * CLK_PERIOD);
      tb_cs = 0;
      tb_we = 0;
    end
  endtask









  task read_word(input [11 : 0]  address);
    begin
      tb_address = address;
      tb_cs = 1;
      tb_we = 0;
      #(CLK_PERIOD);
      read_data = tb_read_data;
      tb_cs = 0;

      if (DEBUG)
        begin
          $display("*** Reading 0x%08x from 0x%02x.", read_data, address);
          $display("");
        end
    end
  endtask







  task wait_ready;
    begin : wready
      read_word(ADDR_STATUS);
      while (read_data == 0)
        read_word(ADDR_STATUS);
    end
  endtask





  task tc1;
    begin : tc1
      reg [31 : 0] res0;
      reg [31 : 0] res1;

      tc_ctr = tc_ctr + 1;

      $display("*** TC1 - encryption started.");

      write_word(ADDR_KEY0, 32'h00010203);
      write_word(ADDR_KEY1, 32'h04050607);
      write_word(ADDR_KEY2, 32'h08090a0b);
      write_word(ADDR_KEY3, 32'h0c0d0e0f);

      write_word(ADDR_BLOCK0, 32'h41424344);
      write_word(ADDR_BLOCK1, 32'h45464748);

      write_word(ADDR_CONFIG, 32'h1);
      write_word(ADDR_CTRL, 32'h2);

      wait_ready();

      read_word(ADDR_RESULT0);
      res0 = read_data;
      read_word(ADDR_RESULT1);
      res1 = read_data;

      if ({res0, res1} == 64'h497df3d072612cb5)
        begin
          $display("*** Correct result received.");
        end
      else
        begin
          $display("*** Incorrect result received. Expexted 64'h497df3d072612cb5, got 0x%016x", {res0, res1});
          error_ctr = error_ctr + 1;
        end

      $display("*** TC1 completed.");
      $display("");
    end
  endtask





  task tc2;
    begin : tc2
      reg [31 : 0] res0;
      reg [31 : 0] res1;

      tc_ctr = tc_ctr + 1;

      $display("*** TC2 - decryption started.");

      write_word(ADDR_KEY0, 32'h00010203);
      write_word(ADDR_KEY1, 32'h04050607);
      write_word(ADDR_KEY2, 32'h08090a0b);
      write_word(ADDR_KEY3, 32'h0c0d0e0f);

      write_word(ADDR_BLOCK0, 32'h497df3d0);
      write_word(ADDR_BLOCK1, 32'h72612cb5);

      write_word(ADDR_CONFIG, 32'h0);
      write_word(ADDR_CTRL, 32'h2);

      wait_ready();

      read_word(ADDR_RESULT0);
      res0 = read_data;
      read_word(ADDR_RESULT1);
      res1 = read_data;

      if ({res0, res1} == 64'h4142434445464748)
        begin
          $display("*** Correct result received.");
        end
      else
        begin
          $display("*** Incorrect result received. Expexted 64'h4142434445464748, got 0x%016x", {res0, res1});
          error_ctr = error_ctr + 1;
        end

      $display("*** TC2 completed.");
      $display("");
    end
  endtask







  initial
    begin : xtea_test
      $display("   -= Testbench for xtea started =-");
      $display("     ============================");
      $display("");

      init_sim();
      reset_dut();

      tc1();
      tc2();

      display_test_result();
      $display("");
      $display("*** xtea simulation done. ***");
      $finish;
    end
endmodule
module tb_xtea();





  parameter DEBUG     = 0;
  parameter DUMP_WAIT = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;

  localparam ADDR_NAME0        = 8'h00;
  localparam ADDR_NAME1        = 8'h01;
  localparam ADDR_VERSION      = 8'h02;

  localparam ADDR_CTRL         = 8'h08;
  localparam CTRL_NEXT_BIT     = 1;

  localparam ADDR_STATUS       = 8'h09;
  localparam STATUS_READY_BIT  = 0;

  localparam ADDR_CONFIG       = 8'h0a;
  localparam CONFIG_ENCDEC_BIT = 0;

  localparam ADDR_KEY0         = 8'h10;
  localparam ADDR_KEY1         = 8'h11;
  localparam ADDR_KEY2         = 8'h12;
  localparam ADDR_KEY3         = 8'h13;

  localparam ADDR_BLOCK0       = 8'h20;
  localparam ADDR_BLOCK1       = 8'h21;

  localparam ADDR_RESULT0      = 8'h30;
  localparam ADDR_RESULT1      = 8'h31;




  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;
  reg          tb_monitor;

  reg           tb_clk;
  reg           tb_reset_n;
  reg           tb_cs;
  reg           tb_we;
  reg [7 : 0]   tb_address;
  reg [31 : 0]  tb_write_data;
  wire [31 : 0] tb_read_data;

  reg [31 : 0] read_data;





  xtea dut(
           .clk(tb_clk),
           .reset_n(tb_reset_n),

           .cs(tb_cs),
           .we(tb_we),

           .address(tb_address),
           .write_data(tb_write_data),
           .read_data(tb_read_data)
           );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD;
      tb_clk = !tb_clk;
    end








  always
    begin : sys_monitor
      cycle_ctr = cycle_ctr + 1;
      #(CLK_PERIOD);
      if (tb_monitor)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state;
    begin
      $display("State of DUT");
      $display("------------");
      $display("Cycle: %08d", cycle_ctr);
      $display("Inputs and outputs:");
      $display("");
    end
  endtask







  task reset_dut;
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(2 * CLK_PERIOD);
      tb_reset_n = 1;
    end
  endtask







  task display_test_result;
    begin
      if (error_ctr == 0)
        begin
          $display("*** All %02d test cases completed successfully", tc_ctr);
        end
      else
        begin
          $display("*** %02d tests completed - %02d test cases did not complete successfully.",
                   tc_ctr, error_ctr);
        end
    end
  endtask








  task init_sim;
    begin
      cycle_ctr  = 0;
      error_ctr  = 0;
      tc_ctr     = 0;
      tb_monitor = 0;

      tb_clk        = 1'h0;
      tb_reset_n    = 1'h1;
      tb_cs         = 1'h0;
      tb_we         = 1'h0;
      tb_address    = 8'h0;
      tb_write_data = 32'h0;
    end
  endtask







  task write_word(input [11 : 0] address,
                  input [31 : 0] word);
    begin
      if (DEBUG)
        begin
          $display("*** Writing 0x%08x to 0x%02x.", word, address);
          $display("");
        end

      tb_address = address;
      tb_write_data = word;
      tb_cs = 1;
      tb_we = 1;
      #(2 * CLK_PERIOD);
      tb_cs = 0;
      tb_we = 0;
    end
  endtask









  task read_word(input [11 : 0]  address);
    begin
      tb_address = address;
      tb_cs = 1;
      tb_we = 0;
      #(CLK_PERIOD);
      read_data = tb_read_data;
      tb_cs = 0;

      if (DEBUG)
        begin
          $display("*** Reading 0x%08x from 0x%02x.", read_data, address);
          $display("");
        end
    end
  endtask







  task wait_ready;
    begin : wready
      read_word(ADDR_STATUS);
      while (read_data == 0)
        read_word(ADDR_STATUS);
    end
  endtask





  task tc1;
    begin : tc1
      reg [31 : 0] res0;
      reg [31 : 0] res1;

      tc_ctr = tc_ctr + 1;

      $display("*** TC1 - encryption started.");

      write_word(ADDR_KEY0, 32'h00010203);
      write_word(ADDR_KEY1, 32'h04050607);
      write_word(ADDR_KEY2, 32'h08090a0b);
      write_word(ADDR_KEY3, 32'h0c0d0e0f);

      write_word(ADDR_BLOCK0, 32'h41424344);
      write_word(ADDR_BLOCK1, 32'h45464748);

      write_word(ADDR_CONFIG, 32'h1);
      write_word(ADDR_CTRL, 32'h2);

      wait_ready();

      read_word(ADDR_RESULT0);
      res0 = read_data;
      read_word(ADDR_RESULT1);
      res1 = read_data;

      if ({res0, res1} == 64'h497df3d072612cb5)
        begin
          $display("*** Correct result received.");
        end
      else
        begin
          $display("*** Incorrect result received. Expexted 64'h497df3d072612cb5, got 0x%016x", {res0, res1});
          error_ctr = error_ctr + 1;
        end

      $display("*** TC1 completed.");
      $display("");
    end
  endtask





  task tc2;
    begin : tc2
      reg [31 : 0] res0;
      reg [31 : 0] res1;

      tc_ctr = tc_ctr + 1;

      $display("*** TC2 - decryption started.");

      write_word(ADDR_KEY0, 32'h00010203);
      write_word(ADDR_KEY1, 32'h04050607);
      write_word(ADDR_KEY2, 32'h08090a0b);
      write_word(ADDR_KEY3, 32'h0c0d0e0f);

      write_word(ADDR_BLOCK0, 32'h497df3d0);
      write_word(ADDR_BLOCK1, 32'h72612cb5);

      write_word(ADDR_CONFIG, 32'h0);
      write_word(ADDR_CTRL, 32'h2);

      wait_ready();

      read_word(ADDR_RESULT0);
      res0 = read_data;
      read_word(ADDR_RESULT1);
      res1 = read_data;

      if ({res0, res1} == 64'h4142434445464748)
        begin
          $display("*** Correct result received.");
        end
      else
        begin
          $display("*** Incorrect result received. Expexted 64'h4142434445464748, got 0x%016x", {res0, res1});
          error_ctr = error_ctr + 1;
        end

      $display("*** TC2 completed.");
      $display("");
    end
  endtask







  initial
    begin : xtea_test
      $display("   -= Testbench for xtea started =-");
      $display("     ============================");
      $display("");

      init_sim();
      reset_dut();

      tc1();
      tc2();

      display_test_result();
      $display("");
      $display("*** xtea simulation done. ***");
      $finish;
    end
endmodule