data/full_repos/permissive/203526788/GoBoard/ClickCounter/ClickCounter.v
1: b'%Error: data/full_repos/permissive/203526788/GoBoard/ClickCounter/ClickCounter.v:1: Cannot find include file: ../SevenSegment/SevenSegment.v\n`include "../SevenSegment/SevenSegment.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203526788/GoBoard/ClickCounter,data/full_repos/permissive/203526788/../SevenSegment/SevenSegment.v\n             data/full_repos/permissive/203526788/GoBoard/ClickCounter,data/full_repos/permissive/203526788/../SevenSegment/SevenSegment.v.v\n             data/full_repos/permissive/203526788/GoBoard/ClickCounter,data/full_repos/permissive/203526788/../SevenSegment/SevenSegment.v.sv\n             ../SevenSegment/SevenSegment.v\n             ../SevenSegment/SevenSegment.v.v\n             ../SevenSegment/SevenSegment.v.sv\n             obj_dir/../SevenSegment/SevenSegment.v\n             obj_dir/../SevenSegment/SevenSegment.v.v\n             obj_dir/../SevenSegment/SevenSegment.v.sv\n%Error: data/full_repos/permissive/203526788/GoBoard/ClickCounter/ClickCounter.v:2: Cannot find include file: ../Debouncer/Debouncer.v\n`include "../Debouncer/Debouncer.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module top (
	input CLK,
	input SW1,
	input SW3,
	output [6:0] SEG,
	output [3:0] LED
);


assign LED[3:0]= 4'b0000;


reg outSW1, outSW3;
Debouncer d1 (CLK, SW1, outSW1);
Debouncer d3 (CLK, SW3, outSW3);
reg state = outSW1 || outSW3;


reg [3:0] number = 0;
SevenSegment s ( CLK, SEG, number );


always @(posedge state)
begin
	if (outSW1) begin
		if (number == 4'd9 ) begin
			number <= 0;
		end else begin
			number <= number + 1;
		end
	end else if (outSW3) begin
		if (number == 4'd0 ) begin
			number <= 4'd9;
		end else begin
			number <= number - 1;
		end
	end
end




endmodule
module top (
	input CLK,
	input SW1,
	input SW3,
	output [6:0] SEG,
	output [3:0] LED
);



assign LED[3:0]= 4'b0000;


reg outSW1, outSW3;
Debouncer d1 (CLK, SW1, outSW1);
Debouncer d3 (CLK, SW3, outSW3);
reg state = outSW1 || outSW3;


reg [3:0] number = 0;
SevenSegment s ( CLK, SEG, number );


always @(posedge state)
begin
	if (outSW1) begin
		if (number == 4'd9 ) begin
			number <= 0;
		end else begin
			number <= number + 1;
		end
	end else if (outSW3) begin
		if (number == 4'd0 ) begin
			number <= 4'd9;
		end else begin
			number <= number - 1;
		end
	end
end




endmodule