data/full_repos/permissive/128426084/src/sources_1/new/gremlins_position.v
1: b'%Error: data/full_repos/permissive/128426084/src/sources_1/new/gremlins_position.v:3: Cannot find include file: verilog_macro_bus.vh\n`include "verilog_macro_bus.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.v\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.sv\n             verilog_macro_bus.vh\n             verilog_macro_bus.vh.v\n             verilog_macro_bus.vh.sv\n             obj_dir/verilog_macro_bus.vh\n             obj_dir/verilog_macro_bus.vh.v\n             obj_dir/verilog_macro_bus.vh.sv\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/gremlins_position.v:8: Define or directive not defined: \'`VGA_BUS_SIZE\'\n    input wire [`VGA_BUS_SIZE-1:0] vga_in,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/gremlins_position.v:9: Define or directive not defined: \'`VGA_BUS_SIZE\'\n    output wire [`VGA_BUS_SIZE-1:0] vga_out,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/gremlins_position.v:13: Define or directive not defined: \'`VGA_SPLIT_INPUT\'\n    `VGA_SPLIT_INPUT(vga_in)\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/gremlins_position.v:13: syntax error, unexpected \'(\'\n    `VGA_SPLIT_INPUT(vga_in)\n                     ^~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/gremlins_position.v:14: Define or directive not defined: \'`VGA_OUT_REG\'\n    `VGA_OUT_REG\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/gremlins_position.v:15: Define or directive not defined: \'`VGA_MERGE_AT_OUTPUT\'\n    `VGA_MERGE_AT_OUTPUT(vga_out)\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module gremlins_position(
    input wire clk,
    input wire grem0_enable, grem1_enable,
    input wire [`VGA_BUS_SIZE-1:0] vga_in,
    output wire [`VGA_BUS_SIZE-1:0] vga_out,
    output wire [23:0] grem0_out, grem1_out
    );
    
    `VGA_SPLIT_INPUT(vga_in)
    `VGA_OUT_REG
    `VGA_MERGE_AT_OUTPUT(vga_out)

wire addr1, addr1_1;
wire [4:0] addr2, addr2_1;
wire [15:0] char_line_pix, char_line_pix_1; 
    
localparam GREMH = 32;
localparam GREMW = 16;

reg [11:0] rgb_nxt;
reg en, st;

  gremlin #(.I(217),.J(0),.XPOS_INIT(200),.YPOS_INIT(300)) my_gremlin0 (
    .clk(clk),
    .en(en),
    .grem_enable(grem0_enable),
    .vga_in(vga_in),
    .char_pixels(char_line_pix),
    .char_xy(addr1),
    .char_line(addr2),
    .xpos(grem0_out[22:12]),
    .ypos(grem0_out[11:1]),
    .color(grem0_out[23]),
    .grem_out(grem0_out[0])
  );
  
  gremlin_rom my_gremlin0_rom(
    .addr1(addr1),
    .addr2(addr2),
    .char_line_pixels(char_line_pix)
  );

  gremlin #(.I(263),.J(3),.XPOS_INIT(600),.YPOS_INIT(300)) my_gremlin1(
    .clk(clk),
    .en(en),
    .grem_enable(grem1_enable),
    .vga_in(vga_in),
    .char_pixels(char_line_pix_1),
    .char_xy(addr1_1),
    .char_line(addr2_1),
    .xpos(grem1_out[22:12]),
    .ypos(grem1_out[11:1]),
    .color(grem1_out[23]),
    .grem_out(grem1_out[0])
  );
  
  gremlin_rom my_gremlin1_rom(
    .addr1(addr1_1),
    .addr2(addr2_1),
    .char_line_pixels(char_line_pix_1)
  );  

    
always @(posedge clk)
begin
    if ((vsync_in == 1) && (en == 1) )
        begin             
            en <= 0;
            st <= 1; 
        end
    else if ((vsync_in == 1) && (en == 0) && (st == 0))
        en <= 1;
    else if (vsync_in == 0)
        begin
            en <= 0;
            st <= 0;
        end        
end

always @*
    if((grem0_out[0] & grem0_out[23]) || (grem1_out[0] & grem1_out[23]))
        rgb_nxt = 12'hfff;
    else 
        rgb_nxt = rgb_in;

 always @(posedge clk)
 begin
    hcount_out <= hcount_in;
     hsync_out <= hsync_in;
     hblnk_out <= hblnk_in;
     vcount_out <= vcount_in;
     vsync_out <= vsync_in;
     vblnk_out <= vblnk_in;
     rgb_out <= rgb_nxt;
 end      
    
endmodule
module gremlins_position(
    input wire clk,
    input wire grem0_enable, grem1_enable,
    input wire [`VGA_BUS_SIZE-1:0] vga_in,
    output wire [`VGA_BUS_SIZE-1:0] vga_out,
    output wire [23:0] grem0_out, grem1_out
    );

    
    `VGA_SPLIT_INPUT(vga_in)
    `VGA_OUT_REG
    `VGA_MERGE_AT_OUTPUT(vga_out)

wire addr1, addr1_1;
wire [4:0] addr2, addr2_1;
wire [15:0] char_line_pix, char_line_pix_1; 
    
localparam GREMH = 32;
localparam GREMW = 16;

reg [11:0] rgb_nxt;
reg en, st;

  gremlin #(.I(217),.J(0),.XPOS_INIT(200),.YPOS_INIT(300)) my_gremlin0 (
    .clk(clk),
    .en(en),
    .grem_enable(grem0_enable),
    .vga_in(vga_in),
    .char_pixels(char_line_pix),
    .char_xy(addr1),
    .char_line(addr2),
    .xpos(grem0_out[22:12]),
    .ypos(grem0_out[11:1]),
    .color(grem0_out[23]),
    .grem_out(grem0_out[0])
  );
  
  gremlin_rom my_gremlin0_rom(
    .addr1(addr1),
    .addr2(addr2),
    .char_line_pixels(char_line_pix)
  );

  gremlin #(.I(263),.J(3),.XPOS_INIT(600),.YPOS_INIT(300)) my_gremlin1(
    .clk(clk),
    .en(en),
    .grem_enable(grem1_enable),
    .vga_in(vga_in),
    .char_pixels(char_line_pix_1),
    .char_xy(addr1_1),
    .char_line(addr2_1),
    .xpos(grem1_out[22:12]),
    .ypos(grem1_out[11:1]),
    .color(grem1_out[23]),
    .grem_out(grem1_out[0])
  );
  
  gremlin_rom my_gremlin1_rom(
    .addr1(addr1_1),
    .addr2(addr2_1),
    .char_line_pixels(char_line_pix_1)
  );  

    
always @(posedge clk)
begin
    if ((vsync_in == 1) && (en == 1) )
        begin             
            en <= 0;
            st <= 1; 
        end
    else if ((vsync_in == 1) && (en == 0) && (st == 0))
        en <= 1;
    else if (vsync_in == 0)
        begin
            en <= 0;
            st <= 0;
        end        
end

always @*
    if((grem0_out[0] & grem0_out[23]) || (grem1_out[0] & grem1_out[23]))
        rgb_nxt = 12'hfff;
    else 
        rgb_nxt = rgb_in;

 always @(posedge clk)
 begin
    hcount_out <= hcount_in;
     hsync_out <= hsync_in;
     hblnk_out <= hblnk_in;
     vcount_out <= vcount_in;
     vsync_out <= vsync_in;
     vblnk_out <= vblnk_in;
     rgb_out <= rgb_nxt;
 end      
    
endmodule