data/full_repos/permissive/174323821/hdl/jtframe_uart.v
data/verilator_xmls/2dab294c-2f2f-4c99-bbb7-979071489b8e.xml
module jtframe_uart(
    input            rst,
    input            clk,

    input            uart_rx,
    output reg       uart_tx,

    output reg [7:0] rx_data,
    output reg       rx_error,
    output reg       rx_rdy,
    input            rx_clr,

    output reg       tx_busy,
    input      [7:0] tx_data,
    input            tx_wr
);


parameter [4:0] CLK_DIVIDER  = 28,
                UART_DIVIDER = CLK_DIVIDER;




reg  [4:0] clk_cnt;
reg zero;

always @(posedge clk or posedge rst) begin : clock_divider
    if(rst) begin
        clk_cnt <= CLK_DIVIDER - 5'b1;
        zero    <= 1'b0;
    end else begin
        clk_cnt <= clk_cnt - 5'd1;
        zero <= clk_cnt==5'd1;
        if(zero)
            clk_cnt <= CLK_DIVIDER - 5'b1;
    end
end




reg uart_rx1;
reg uart_rx2;

always @(posedge clk) begin : synchronizer
    uart_rx1 <= uart_rx;
    uart_rx2 <= uart_rx1;
end


reg rx_busy;
reg [4:0] rx_divcnt;
reg [3:0] rx_bitcnt;
reg [7:0] rx_reg;

always @(posedge clk or posedge rst) begin : rx_logic
    if(rst) begin
        rx_rdy    <= 0;
        rx_busy   <= 0;
        rx_divcnt <= 0;
        rx_bitcnt <= 0;
        rx_data   <= 0;
        rx_reg    <= 0;
        rx_error  <= 0;
    end else begin
        if( rx_clr ) begin
            rx_rdy   <= 0;
            rx_error <= 0;
        end

        if( zero ) begin
            if(!rx_busy && !uart_rx2) begin
                rx_busy    <= 1;
                rx_divcnt  <= UART_DIVIDER>>1;
                rx_bitcnt  <= 0;
                rx_reg     <= 0;
            end else if( rx_busy ) begin
                rx_divcnt <= rx_divcnt==0 ? UART_DIVIDER : rx_divcnt - 1'b1;
                if( rx_divcnt==0 ) begin
                    rx_bitcnt  <= rx_bitcnt + 4'd1;
                    if( rx_bitcnt<9 ) begin
                        rx_reg <= {uart_rx2, rx_reg[7:1]};
                    end else begin
                        rx_busy  <= 0;
                        rx_rdy   <= 1;
                        rx_data  <= rx_reg;
                        rx_error <= !uart_rx2;
                    end
                end
            end
        end
    end
end


reg [3:0] tx_bitcnt;
reg [4:0] tx_divcnt;
reg [7:0] tx_reg;

always @(posedge clk or posedge rst) begin :tx_logic
    if(rst) begin
        tx_busy   <= 0;
        uart_tx   <= 1;
        tx_divcnt <= 0;
        tx_reg    <= 0;
    end else begin
        if( tx_wr && !tx_busy ) begin
            tx_reg    <= tx_data;
            tx_bitcnt <= 0;
            tx_divcnt <= UART_DIVIDER;
            tx_busy   <= 1;
            uart_tx   <= 0;
        end else if(zero && tx_busy) begin
            tx_divcnt <= tx_divcnt==0 ? UART_DIVIDER : tx_divcnt-1'd1;
            if( tx_divcnt==0 ) begin
                tx_bitcnt <= tx_bitcnt + 4'd1;
                if( tx_bitcnt < 8 ) begin
                    uart_tx <= tx_reg[0];
                    tx_reg  <= tx_reg>>1;
                end else begin
                    uart_tx <= 1;
                    if(tx_bitcnt==9) tx_busy <= 0;
                end
            end
        end
    end
end

endmodule
module jtframe_uart(
    input            rst,
    input            clk,

    input            uart_rx,
    output reg       uart_tx,

    output reg [7:0] rx_data,
    output reg       rx_error,
    output reg       rx_rdy,
    input            rx_clr,

    output reg       tx_busy,
    input      [7:0] tx_data,
    input            tx_wr
);



parameter [4:0] CLK_DIVIDER  = 28,
                UART_DIVIDER = CLK_DIVIDER;




reg  [4:0] clk_cnt;
reg zero;

always @(posedge clk or posedge rst) begin : clock_divider
    if(rst) begin
        clk_cnt <= CLK_DIVIDER - 5'b1;
        zero    <= 1'b0;
    end else begin
        clk_cnt <= clk_cnt - 5'd1;
        zero <= clk_cnt==5'd1;
        if(zero)
            clk_cnt <= CLK_DIVIDER - 5'b1;
    end
end




reg uart_rx1;
reg uart_rx2;

always @(posedge clk) begin : synchronizer
    uart_rx1 <= uart_rx;
    uart_rx2 <= uart_rx1;
end


reg rx_busy;
reg [4:0] rx_divcnt;
reg [3:0] rx_bitcnt;
reg [7:0] rx_reg;

always @(posedge clk or posedge rst) begin : rx_logic
    if(rst) begin
        rx_rdy    <= 0;
        rx_busy   <= 0;
        rx_divcnt <= 0;
        rx_bitcnt <= 0;
        rx_data   <= 0;
        rx_reg    <= 0;
        rx_error  <= 0;
    end else begin
        if( rx_clr ) begin
            rx_rdy   <= 0;
            rx_error <= 0;
        end

        if( zero ) begin
            if(!rx_busy && !uart_rx2) begin
                rx_busy    <= 1;
                rx_divcnt  <= UART_DIVIDER>>1;
                rx_bitcnt  <= 0;
                rx_reg     <= 0;
            end else if( rx_busy ) begin
                rx_divcnt <= rx_divcnt==0 ? UART_DIVIDER : rx_divcnt - 1'b1;
                if( rx_divcnt==0 ) begin
                    rx_bitcnt  <= rx_bitcnt + 4'd1;
                    if( rx_bitcnt<9 ) begin
                        rx_reg <= {uart_rx2, rx_reg[7:1]};
                    end else begin
                        rx_busy  <= 0;
                        rx_rdy   <= 1;
                        rx_data  <= rx_reg;
                        rx_error <= !uart_rx2;
                    end
                end
            end
        end
    end
end


reg [3:0] tx_bitcnt;
reg [4:0] tx_divcnt;
reg [7:0] tx_reg;

always @(posedge clk or posedge rst) begin :tx_logic
    if(rst) begin
        tx_busy   <= 0;
        uart_tx   <= 1;
        tx_divcnt <= 0;
        tx_reg    <= 0;
    end else begin
        if( tx_wr && !tx_busy ) begin
            tx_reg    <= tx_data;
            tx_bitcnt <= 0;
            tx_divcnt <= UART_DIVIDER;
            tx_busy   <= 1;
            uart_tx   <= 0;
        end else if(zero && tx_busy) begin
            tx_divcnt <= tx_divcnt==0 ? UART_DIVIDER : tx_divcnt-1'd1;
            if( tx_divcnt==0 ) begin
                tx_bitcnt <= tx_bitcnt + 4'd1;
                if( tx_bitcnt < 8 ) begin
                    uart_tx <= tx_reg[0];
                    tx_reg  <= tx_reg>>1;
                end else begin
                    uart_tx <= 1;
                    if(tx_bitcnt==9) tx_busy <= 0;
                end
            end
        end
    end
end

endmodule