data/full_repos/permissive/154804262/src/UartTx.v
1: b'%Error: data/full_repos/permissive/154804262/src/UartTx.v:22: Cannot find file containing module: \'BpsClkGen\'\n BpsClkGen #(\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154804262/src,data/full_repos/permissive/154804262/BpsClkGen\n             data/full_repos/permissive/154804262/src,data/full_repos/permissive/154804262/BpsClkGen.v\n             data/full_repos/permissive/154804262/src,data/full_repos/permissive/154804262/BpsClkGen.sv\n             BpsClkGen\n             BpsClkGen.v\n             BpsClkGen.sv\n             obj_dir/BpsClkGen\n             obj_dir/BpsClkGen.v\n             obj_dir/BpsClkGen.sv\n%Warning-WIDTH: data/full_repos/permissive/154804262/src/UartTx.v:38: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance UartTx\n   bpsFrameNum <= 1\'d0;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154804262/src/UartTx.v:40: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance UartTx\n   bpsFrameNum <= 1\'d0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154804262/src/UartTx.v:47: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance UartTx\n   bpsFrameNum <= 1\'d0;\n               ^~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module UartTx

#(
	parameter CLKFREQ = 100_000_000,
	parameter BAUDRATE = 115200
)

(
	input clk,
	input reset,
	input txEnable,
	input [7:0] uartInByte,

	output uartTxBit,
	output uartTxDone
);

	wire countEnable;
	wire bpsClk;
	
	parameter bpsWIDTH = 14;
	BpsClkGen #(
		.CLKFREQ(CLKFREQ),
		.BAUDRATE(BAUDRATE),
		.bpsWIDTH(bpsWIDTH)
		)
		U_bpsClkGen (
			.clk(clk),
			.reset(reset),
			.countEnable(countEnable),
			.bpsClk(bpsClk)
			);
	
	reg [3:0] bpsFrameNum;
	always @ (posedge clk or negedge reset)
	begin
		if (!reset)
			bpsFrameNum <= 1'd0;
		else if (bpsFrameNum == 4'd11)
			bpsFrameNum <= 1'd0;
		else if (txEnable)
			begin
				if (bpsClk)
					bpsFrameNum <= bpsFrameNum + 1'd1;
			end
		else
			bpsFrameNum <= 1'd0;
	end

	reg isCount;
	always @(posedge clk or negedge reset)
	begin
		if (!reset)
			isCount <= 1'b0;
		else if (txEnable)
			begin
				if (bpsFrameNum == 4'd0)
					isCount <= 1'b1;
				else if (bpsFrameNum == 4'd11)
					isCount <= 1'b0;
			end
		else
			isCount <= 1'b0;
	end
	assign countEnable = isCount;
	

	reg isDone;
	always @(posedge clk or negedge reset)
	begin
		if (!reset)
			isDone <= 1'b0;
		else if (bpsFrameNum == 4'd11)
			isDone <= 1'b1;
		else
			isDone <= 1'b0;
	end
	assign uartTxDone = isDone;
	

	reg uartTxReg;
	always @ (posedge clk or posedge reset)
	begin
		if (!reset)
			uartTxReg <= 1'b1;
		else if (txEnable)
			case (bpsFrameNum)
				4'd0: uartTxReg <= 1'b1; 
				4'd1: uartTxReg <= 1'b0;
				4'd2: uartTxReg <= uartInByte[0];
				4'd3: uartTxReg <= uartInByte[1];
				4'd4: uartTxReg <= uartInByte[2];
				4'd5: uartTxReg <= uartInByte[3];
				4'd6: uartTxReg <= uartInByte[4];
				4'd7: uartTxReg <= uartInByte[5];
				4'd8: uartTxReg <= uartInByte[6];
				4'd9: uartTxReg <= uartInByte[7];
				4'd10: uartTxReg <= 1'b1;
				default: uartTxReg <= 1'b1;
			endcase
	end
	assign uartTxBit = uartTxReg;

endmodule
module UartTx

#(
	parameter CLKFREQ = 100_000_000,
	parameter BAUDRATE = 115200
)

(
	input clk,
	input reset,
	input txEnable,
	input [7:0] uartInByte,

	output uartTxBit,
	output uartTxDone
);


	wire countEnable;
	wire bpsClk;
	
	parameter bpsWIDTH = 14;
	BpsClkGen #(
		.CLKFREQ(CLKFREQ),
		.BAUDRATE(BAUDRATE),
		.bpsWIDTH(bpsWIDTH)
		)
		U_bpsClkGen (
			.clk(clk),
			.reset(reset),
			.countEnable(countEnable),
			.bpsClk(bpsClk)
			);
	
	reg [3:0] bpsFrameNum;
	always @ (posedge clk or negedge reset)
	begin
		if (!reset)
			bpsFrameNum <= 1'd0;
		else if (bpsFrameNum == 4'd11)
			bpsFrameNum <= 1'd0;
		else if (txEnable)
			begin
				if (bpsClk)
					bpsFrameNum <= bpsFrameNum + 1'd1;
			end
		else
			bpsFrameNum <= 1'd0;
	end

	reg isCount;
	always @(posedge clk or negedge reset)
	begin
		if (!reset)
			isCount <= 1'b0;
		else if (txEnable)
			begin
				if (bpsFrameNum == 4'd0)
					isCount <= 1'b1;
				else if (bpsFrameNum == 4'd11)
					isCount <= 1'b0;
			end
		else
			isCount <= 1'b0;
	end
	assign countEnable = isCount;
	

	reg isDone;
	always @(posedge clk or negedge reset)
	begin
		if (!reset)
			isDone <= 1'b0;
		else if (bpsFrameNum == 4'd11)
			isDone <= 1'b1;
		else
			isDone <= 1'b0;
	end
	assign uartTxDone = isDone;
	

	reg uartTxReg;
	always @ (posedge clk or posedge reset)
	begin
		if (!reset)
			uartTxReg <= 1'b1;
		else if (txEnable)
			case (bpsFrameNum)
				4'd0: uartTxReg <= 1'b1; 
				4'd1: uartTxReg <= 1'b0;
				4'd2: uartTxReg <= uartInByte[0];
				4'd3: uartTxReg <= uartInByte[1];
				4'd4: uartTxReg <= uartInByte[2];
				4'd5: uartTxReg <= uartInByte[3];
				4'd6: uartTxReg <= uartInByte[4];
				4'd7: uartTxReg <= uartInByte[5];
				4'd8: uartTxReg <= uartInByte[6];
				4'd9: uartTxReg <= uartInByte[7];
				4'd10: uartTxReg <= 1'b1;
				default: uartTxReg <= 1'b1;
			endcase
	end
	assign uartTxBit = uartTxReg;

endmodule