data/full_repos/permissive/139213403/FPGA/reset_controller.v
1: b"%Error: data/full_repos/permissive/139213403/FPGA/reset_controller.v:20: Cannot find file containing module: 'mod_m_counter'\n mod_m_counter #(.M_BITS(M_BITS)) tick_counter(.clk(clk), .reset(ready), .m(m_reg), .max_tick(reset_tick), .q());\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/mod_m_counter\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/mod_m_counter.v\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/mod_m_counter.sv\n             mod_m_counter\n             mod_m_counter.v\n             mod_m_counter.sv\n             obj_dir/mod_m_counter\n             obj_dir/mod_m_counter.v\n             obj_dir/mod_m_counter.sv\n%Error: Exiting due to 1 error(s)\n"
module reset_controller
#(
	parameter M_BITS=8
)
(
	input wire clk, reset,
	input wire start,
	input wire [M_BITS-1:0] m,
	output wire en, ready
);

	reg [1:0] state_reg, state_next;
	reg [M_BITS-1:0] m_reg, m_next;
	wire reset_tick;
		
	localparam START = 2'd0,
	           RESET = 2'b1;
		
	mod_m_counter #(.M_BITS(M_BITS)) tick_counter(.clk(clk), .reset(ready), .m(m_reg), .max_tick(reset_tick), .q());
	
	always @(posedge clk)
		if (reset)
			begin
				state_reg <= 0;
				m_reg <= 0;
			end
		else
			begin
				state_reg <= state_next;
				m_reg <= m_next;
			end
		
	always @*
		begin
			state_next = state_reg;
			m_next = m_reg;
			if (start && m > 0)
				begin
					m_next = m;
					state_next = RESET;
				end
			if (reset_tick)
				begin
					m_next = 0;
					state_next = START;
				end
		end
	
	assign en = state_reg == RESET;
	assign ready = ~en;
	
	always @*
		$display("ready: %d m: %d max_tick: %d state_reg: %d", ready, m, reset_tick, state_reg);
	
endmodule
module reset_controller
#(
	parameter M_BITS=8
)
(
	input wire clk, reset,
	input wire start,
	input wire [M_BITS-1:0] m,
	output wire en, ready
);


	reg [1:0] state_reg, state_next;
	reg [M_BITS-1:0] m_reg, m_next;
	wire reset_tick;
		
	localparam START = 2'd0,
	           RESET = 2'b1;
		
	mod_m_counter #(.M_BITS(M_BITS)) tick_counter(.clk(clk), .reset(ready), .m(m_reg), .max_tick(reset_tick), .q());
	
	always @(posedge clk)
		if (reset)
			begin
				state_reg <= 0;
				m_reg <= 0;
			end
		else
			begin
				state_reg <= state_next;
				m_reg <= m_next;
			end
		
	always @*
		begin
			state_next = state_reg;
			m_next = m_reg;
			if (start && m > 0)
				begin
					m_next = m;
					state_next = RESET;
				end
			if (reset_tick)
				begin
					m_next = 0;
					state_next = START;
				end
		end
	
	assign en = state_reg == RESET;
	assign ready = ~en;
	
	always @*
		$display("ready: %d m: %d max_tick: %d state_reg: %d", ready, m, reset_tick, state_reg);
	
endmodule