data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_utils.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_utils.v:65: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                       : ... Top module \'dsi_parity\'\nmodule dsi_parity \n       ^~~~~~~~~~\n                                                                                       : ... Top module \'dsi_crc\'\nmodule dsi_crc\n       ^~~~~~~\n                                                                                       : ... Top module \'dsi_wishbone_async_bridge\'\nmodule dsi_wishbone_async_bridge\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module dsi_sync_chain
  #( parameter length = 2)
   (
    input  clk_i,
    input  rst_n_i,
    input  d_i,
    output q_o );

   reg [length-1:0] sync;

   
   always@(posedge clk_i)
     begin
        sync[0] <= d_i;
        sync[length-1:1] <= sync[length-2:0];
     end
   assign q_o = sync[length-1];
   
endmodule
module dsi_sync_chain
  #( parameter length = 2)
   (
    input  clk_i,
    input  rst_n_i,
    input  d_i,
    output q_o );


   reg [length-1:0] sync;

   
   always@(posedge clk_i)
     begin
        sync[0] <= d_i;
        sync[length-1:1] <= sync[length-2:0];
     end
   assign q_o = sync[length-1];
   
endmodule