data/full_repos/permissive/211316121/lab1/sim_1/new/sim_priority_encoder83.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_priority_encoder83.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=8\'b00000001;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_priority_encoder83.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=8\'b00000010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_priority_encoder83.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=8\'b00000100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_priority_encoder83.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=8\'b00001000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_priority_encoder83.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=8\'b00010000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_priority_encoder83.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=8\'b00100000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_priority_encoder83.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=8\'b01000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_priority_encoder83.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=8\'b10000000;\n        ^\n%Error: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_priority_encoder83.v:26: Cannot find file containing module: \'Top_priority_encoder83\'\n    Top_priority_encoder83 sim_pri83(in,out);\n    ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab1/sim_1/new,data/full_repos/permissive/211316121/Top_priority_encoder83\n             data/full_repos/permissive/211316121/lab1/sim_1/new,data/full_repos/permissive/211316121/Top_priority_encoder83.v\n             data/full_repos/permissive/211316121/lab1/sim_1/new,data/full_repos/permissive/211316121/Top_priority_encoder83.sv\n             Top_priority_encoder83\n             Top_priority_encoder83.v\n             Top_priority_encoder83.sv\n             obj_dir/Top_priority_encoder83\n             obj_dir/Top_priority_encoder83.v\n             obj_dir/Top_priority_encoder83.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_priority_encoder83();
    reg [7:0] in;
    wire [3:0] out;
    Top_priority_encoder83 sim_pri83(in,out);
    initial
        begin
            in=8'b11111111;
        #10 in=8'b00000001;
        #10 in=8'b00000010;
        #10 in=8'b00000100;
        #10 in=8'b00001000;
        #10 in=8'b00010000;
        #10 in=8'b00100000;
        #10 in=8'b01000000;
        #10 in=8'b10000000;
        end
endmodule
module sim_priority_encoder83();

    reg [7:0] in;
    wire [3:0] out;
    Top_priority_encoder83 sim_pri83(in,out);
    initial
        begin
            in=8'b11111111;
        #10 in=8'b00000001;
        #10 in=8'b00000010;
        #10 in=8'b00000100;
        #10 in=8'b00001000;
        #10 in=8'b00010000;
        #10 in=8'b00100000;
        #10 in=8'b01000000;
        #10 in=8'b10000000;
        end
endmodule