data/full_repos/permissive/193419875/src/Clock.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193419875/src/Clock.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #0.07\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/193419875/src/Clock.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #0.03\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193419875/src/Clock.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Clock(
	output reg CLOCK
);

	always @(posedge CLOCK)
	begin
		#0.07
		CLOCK <= ~CLOCK;
	end

	always @(negedge CLOCK)
	begin
		#0.03
		CLOCK <= ~CLOCK;
	end

	initial begin
		CLOCK <= 1;
		#5;

		$finish;
	end
endmodule
module Clock(
	output reg CLOCK
);


	always @(posedge CLOCK)
	begin
		#0.07
		CLOCK <= ~CLOCK;
	end

	always @(negedge CLOCK)
	begin
		#0.03
		CLOCK <= ~CLOCK;
	end

	initial begin
		CLOCK <= 1;
		#5;

		$finish;
	end
endmodule