data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v
 line:67: before: "$"
1: b'%Error: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:20: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("memory_wave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:21: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #4;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #6;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/memory/memory_tester.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: Exiting due to 2 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_tester #(parameter DATA_WIDTH = 8, parameter ADDRESS_WIDTH = 3, parameter BUFFER_DEPTH = 8)(
  output reg CLK,
  output reg ENB,
  output reg sRead,
  output reg sWrite,


  output reg [ADDRESS_WIDTH-1:0] addressRead,
  output reg [ADDRESS_WIDTH-1:0] addressWrite,

  output reg [DATA_WIDTH-1:0] inputData
  );

  reg [2:0] i;
  initial begin
    CLK <= 0;
  end

  initial begin
    $dumpfile("memory_wave.vcd");
    $dumpvars;
    #0;
    ENB <= 1;
    inputData <= 8'b1;
    sRead <= 0;
    sWrite <= 1;
    addressWrite <= 3'd0;
    addressRead <= 3'd0;

    #10;
    inputData <= 8'd2;
    addressWrite <= 3'd1;

    #4;
    sRead <=1;
    #6;
    inputData <= 8'd4;
    addressWrite <= 3'd2;
    addressRead <= addressWrite - 1;

    #10;
    inputData <= 8'd8;
    addressWrite <= 3'd3;
    addressRead <= addressWrite - 1;

    #10;
    inputData <= 8'd16;
    addressWrite <= 3'd4;
    addressRead <= addressWrite - 1;

    #10;
    inputData <= 8'd32;
    addressWrite <= 3'd5;
    addressRead <= addressWrite - 1;

    #10;
    inputData <= 8'd64;
    addressWrite <= 3'd6;
    addressRead <= addressWrite - 1;

    #10;
    inputData <= 8'd128;
    addressWrite <= 3'd7;
    addressRead <= addressWrite - 1;
    #10

    $finish;
  end

  always begin
    #5;
    CLK <= ~CLK;
  end
endmodule
module memory_tester #(parameter DATA_WIDTH = 8, parameter ADDRESS_WIDTH = 3, parameter BUFFER_DEPTH = 8)(
  output reg CLK,
  output reg ENB,
  output reg sRead,
  output reg sWrite,


  output reg [ADDRESS_WIDTH-1:0] addressRead,
  output reg [ADDRESS_WIDTH-1:0] addressWrite,

  output reg [DATA_WIDTH-1:0] inputData
  );


  reg [2:0] i;
  initial begin
    CLK <= 0;
  end

  initial begin
    $dumpfile("memory_wave.vcd");
    $dumpvars;
    #0;
    ENB <= 1;
    inputData <= 8'b1;
    sRead <= 0;
    sWrite <= 1;
    addressWrite <= 3'd0;
    addressRead <= 3'd0;

    #10;
    inputData <= 8'd2;
    addressWrite <= 3'd1;

    #4;
    sRead <=1;
    #6;
    inputData <= 8'd4;
    addressWrite <= 3'd2;
    addressRead <= addressWrite - 1;

    #10;
    inputData <= 8'd8;
    addressWrite <= 3'd3;
    addressRead <= addressWrite - 1;

    #10;
    inputData <= 8'd16;
    addressWrite <= 3'd4;
    addressRead <= addressWrite - 1;

    #10;
    inputData <= 8'd32;
    addressWrite <= 3'd5;
    addressRead <= addressWrite - 1;

    #10;
    inputData <= 8'd64;
    addressWrite <= 3'd6;
    addressRead <= addressWrite - 1;

    #10;
    inputData <= 8'd128;
    addressWrite <= 3'd7;
    addressRead <= addressWrite - 1;
    #10

    $finish;
  end

  always begin
    #5;
    CLK <= ~CLK;
  end
endmodule