data/full_repos/permissive/131473143/src/led_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/131473143/src/led_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/131473143/src/led_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n   #100\n   ^\n%Error: data/full_repos/permissive/131473143/src/led_tb.v:34: Cannot find file containing module: \'led\'\n led uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/131473143/src,data/full_repos/permissive/131473143/led\n             data/full_repos/permissive/131473143/src,data/full_repos/permissive/131473143/led.v\n             data/full_repos/permissive/131473143/src,data/full_repos/permissive/131473143/led.sv\n             led\n             led.v\n             led.sv\n             obj_dir/led\n             obj_dir/led.v\n             obj_dir/led.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module led_tb;


	reg clk;


	wire [7:0] leds;


	led uut (
		.clk(clk), 
		.leds(leds)
	);

	initial begin

		clk = 0;


		#100;
        

		forever begin
			#100
			clk = ~ clk;
		end

	end
      
endmodule
module led_tb;



	reg clk;


	wire [7:0] leds;


	led uut (
		.clk(clk), 
		.leds(leds)
	);

	initial begin

		clk = 0;


		#100;
        

		forever begin
			#100
			clk = ~ clk;
		end

	end
      
endmodule