data/full_repos/permissive/19340845/src/OnewordRegister.v
None: at end of input
data/verilator_xmls/e76fc903-39be-476e-a929-82552dda0cc0.xml
module OnewordRegister(
   input [15:0]  IN,
   input         CLK,
   output [15:0] OUT);

   reg [15:0]    REG;

   always @ (posedge CLK) begin
      REG <= IN;
   end
   
   assign OUT = REG;
   
endmodule
module OnewordRegister(
   input [15:0]  IN,
   input         CLK,
   output [15:0] OUT);


   reg [15:0]    REG;

   always @ (posedge CLK) begin
      REG <= IN;
   end
   
   assign OUT = REG;
   
endmodule