data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v
 line:28: before: "$"
1: b'%Error: data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v:1: Cannot find include file: top.vh\n`include "top.vh" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105546923/projects/mandlebrot/sim,data/full_repos/permissive/105546923/top.vh\n             data/full_repos/permissive/105546923/projects/mandlebrot/sim,data/full_repos/permissive/105546923/top.vh.v\n             data/full_repos/permissive/105546923/projects/mandlebrot/sim,data/full_repos/permissive/105546923/top.vh.sv\n             top.vh\n             top.vh.v\n             top.vh.sv\n             obj_dir/top.vh\n             obj_dir/top.vh.v\n             obj_dir/top.vh.sv\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./build/iverilog/mandlebrot.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,top_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n # 1000 $finish;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/mandlebrot/sim/top_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk_i = ~clk_i;\n          ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module top_tb;

   reg clk_i = 0;

   wire [7:0] led_o;
   wire       vs;
   wire       hs;
   wire [3 : 0] red;
   wire [3 : 0] blue;
   wire [3 : 0] green;
   integer	j = 0;

   initial
     begin

	$dumpfile("./build/iverilog/mandlebrot.vcd");
	$dumpvars(0,top_tb);

	# 1000 $finish;

     end

   always #1 clk_i = ~clk_i;

   top tb (
	   .ice_clk_i (clk_i),
	   .led_o (led_o),
	   .vs_o(vs),
	   .hs_o(hs),
	   .red_o(red),
	   .blue_o(blue),
	   .green_o(green)
	   );

endmodule
module top_tb;


   reg clk_i = 0;

   wire [7:0] led_o;
   wire       vs;
   wire       hs;
   wire [3 : 0] red;
   wire [3 : 0] blue;
   wire [3 : 0] green;
   integer	j = 0;

   initial
     begin

	$dumpfile("./build/iverilog/mandlebrot.vcd");
	$dumpvars(0,top_tb);

	# 1000 $finish;

     end

   always #1 clk_i = ~clk_i;

   top tb (
	   .ice_clk_i (clk_i),
	   .led_o (led_o),
	   .vs_o(vs),
	   .hs_o(hs),
	   .red_o(red),
	   .blue_o(blue),
	   .green_o(green)
	   );

endmodule