data/full_repos/permissive/201488448/1_verilog/26_addsub.v
1: b"%Error: data/full_repos/permissive/201488448/1_verilog/26_addsub.v:10: Cannot find file containing module: 'add16'\n    add16 a1(a[15:0], bsub[15:0], sub, result[15:0], mid);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/add16\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/add16.v\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/201488448/1_verilog/26_addsub.v:11: Cannot find file containing module: 'add16'\n    add16 a2(a[31:16], bsub[31:16], mid, result[31:16], bot);\n    ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] result
);
    wire mid,bot;
    wire [31:0] bsub;
    assign	bsub = b^{32{sub}};
    add16 a1(a[15:0], bsub[15:0], sub, result[15:0], mid);
    add16 a2(a[31:16], bsub[31:16], mid, result[31:16], bot);
    
endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] result
);

    wire mid,bot;
    wire [31:0] bsub;
    assign	bsub = b^{32{sub}};
    add16 a1(a[15:0], bsub[15:0], sub, result[15:0], mid);
    add16 a2(a[31:16], bsub[31:16], mid, result[31:16], bot);
    
endmodule