data/full_repos/permissive/207111076/my_osd.v
 line:25: before: "="
1: b'%Warning-PINMISSING: data/full_repos/permissive/207111076/my_osd.v:578: Cell has missing pin: \'load_late\'\nspi8 spi0\n     ^~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/207111076/my_osd.v:210: Signal definition not found, creating implicitly: \'COLDRESET_N\'\nassign COLDRESET_N = int_mask[7];\n       ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/207111076/my_osd.v:541: Signal definition not found, creating implicitly: \'audio_fifo_reset\'\nassign audio_fifo_reset = (rx && cmd && spicmd==4\'b1010);\n       ^~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/207111076/my_osd.v:542: Signal definition not found, creating implicitly: \'audio_wrreq\'\nassign audio_wrreq = (rx && ~cmd && spicmd==4\'b1010);\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/207111076/my_osd.v:259: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s SEL generates 10 bits.\n                                                                 : ... In instance my_osd\nwire [11:0] frame_x_scroll = frame_x[11:2] ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/my_osd.v:260: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s SEL generates 10 bits.\n                                                                 : ... In instance my_osd\nwire [11:0] frame_y_scroll = frame_y[11:2] ;\n                           ^\n%Error: data/full_repos/permissive/207111076/my_osd.v:272: Cannot find file containing module: \'scroll_buf\'\nscroll_buf scroll_buf_a (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207111076,data/full_repos/permissive/207111076/scroll_buf\n             data/full_repos/permissive/207111076,data/full_repos/permissive/207111076/scroll_buf.v\n             data/full_repos/permissive/207111076,data/full_repos/permissive/207111076/scroll_buf.sv\n             scroll_buf\n             scroll_buf.v\n             scroll_buf.sv\n             obj_dir/scroll_buf\n             obj_dir/scroll_buf.v\n             obj_dir/scroll_buf.sv\n%Warning-WIDTH: data/full_repos/permissive/207111076/my_osd.v:326: Operator ASSIGNW expects 14 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                                 : ... In instance my_osd\nwire [13:0] patt_addr = { frame_y_scroll[8:0], frame_x_scroll[5:1],3\'b000 };\n                      ^\n%Error: data/full_repos/permissive/207111076/my_osd.v:340: Cannot find file containing module: \'osdbuf\'\nosdbuf osdbuf_inst (\n^~~~~~\n%Error: data/full_repos/permissive/207111076/my_osd.v:351: Cannot find file containing module: \'att_buf\'\natt_buf att_buf_inst (\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/207111076/my_osd.v:430: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'rgb_in\' generates 24 bits.\n                                                                 : ... In instance my_osd\nalways @(*) rgb_out = (osdframe | scrollframe) ? pal_pixel : rgb_in;\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/my_osd.v:430: Operator ASSIGN expects 24 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                 : ... In instance my_osd\nalways @(*) rgb_out = (osdframe | scrollframe) ? pal_pixel : rgb_in;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/my_osd.v:497: Operator ADD expects 8 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                 : ... In instance my_osd\n  paladdr <= paladdr + 4\'d1;\n                     ^\n%Error: Exiting due to 3 error(s), 10 warning(s)\n'
module spi8
(
	input clk,
	input	_scs,
	input	sdi,
	inout sdo,
	input	sck,
	input	[7:0] in,
	output [7:0] out,
	output reg rx,
	output reg cmd,
	output wire load_late
);


reg [2:0] bit_cnt;
reg [7:0] sdi_reg;
reg [7:0] sdo_reg;

reg new_byte;
reg rx_sync;
reg first_byte;


always @(posedge sck) sdi_reg <= {sdi_reg[6:0],sdi};

assign out = sdi_reg;


always @(posedge sck or posedge _scs)
	if (_scs) bit_cnt <= 0;
	else bit_cnt <= bit_cnt + 3'd1;




always @(posedge sck or posedge rx)
	if (rx) new_byte <= 0;
	else if (bit_cnt == 3'd7) new_byte <= 1;

always @(negedge clk) rx_sync <= new_byte;

	
reg sck_1, sck_2;
wire sck_falling = (sck_2 & !sck_1);
always @(posedge clk) begin
	sck_1 <= sck;
	sck_2 <= sck_1;

	rx <= rx_sync;

	if (sck_falling | load_late) begin
		if (bit_cnt == 3'd0) sdo_reg <= in;
		else sdo_reg <= {sdo_reg[6:0],1'b0};
	end
end




always @(posedge sck or posedge _scs)
	if (_scs) first_byte <= 1'b1;
	else if (bit_cnt == 3'd7) first_byte <= 1'b0;

always @(posedge sck)
	if (bit_cnt == 3'd7) cmd <= first_byte;
	







assign sdo = (!_scs) ? sdo_reg[7] : 1'bz;

endmodule
module spi8
(
	input clk,
	input	_scs,
	input	sdi,
	inout sdo,
	input	sck,
	input	[7:0] in,
	output [7:0] out,
	output reg rx,
	output reg cmd,
	output wire load_late
);



reg [2:0] bit_cnt;
reg [7:0] sdi_reg;
reg [7:0] sdo_reg;

reg new_byte;
reg rx_sync;
reg first_byte;


always @(posedge sck) sdi_reg <= {sdi_reg[6:0],sdi};

assign out = sdi_reg;


always @(posedge sck or posedge _scs)
	if (_scs) bit_cnt <= 0;
	else bit_cnt <= bit_cnt + 3'd1;




always @(posedge sck or posedge rx)
	if (rx) new_byte <= 0;
	else if (bit_cnt == 3'd7) new_byte <= 1;

always @(negedge clk) rx_sync <= new_byte;

	
reg sck_1, sck_2;
wire sck_falling = (sck_2 & !sck_1);
always @(posedge clk) begin
	sck_1 <= sck;
	sck_2 <= sck_1;

	rx <= rx_sync;

	if (sck_falling | load_late) begin
		if (bit_cnt == 3'd0) sdo_reg <= in;
		else sdo_reg <= {sdo_reg[6:0],1'b0};
	end
end




always @(posedge sck or posedge _scs)
	if (_scs) first_byte <= 1'b1;
	else if (bit_cnt == 3'd7) first_byte <= 1'b0;

always @(posedge sck)
	if (bit_cnt == 3'd7) cmd <= first_byte;
	







assign sdo = (!_scs) ? sdo_reg[7] : 1'bz;

endmodule