data/full_repos/permissive/203526788/GoBoard/D-FlipFlop/DFF.v
data/verilator_xmls/0d10a7ac-22d8-4c4d-a97e-5c45a97df907.xml
module DFF (input CLK, D, output reg Q);

    always @ (posedge CLK) begin
        Q <= D;
    end

endmodule
module DFF (input CLK, D, output reg Q);


    always @ (posedge CLK) begin
        Q <= D;
    end

endmodule