data/full_repos/permissive/159954591/rtl/fmSigMix.v
1: b'%Error: data/full_repos/permissive/159954591/rtl/fmSigMix.v:32: Cannot find file containing module: \'fm38_19kHz_gen\'\n    fm38_19kHz_gen fm38_19kHz_gen_inst (\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159954591/rtl,data/full_repos/permissive/159954591/fm38_19kHz_gen\n             data/full_repos/permissive/159954591/rtl,data/full_repos/permissive/159954591/fm38_19kHz_gen.v\n             data/full_repos/permissive/159954591/rtl,data/full_repos/permissive/159954591/fm38_19kHz_gen.sv\n             fm38_19kHz_gen\n             fm38_19kHz_gen.v\n             fm38_19kHz_gen.sv\n             obj_dir/fm38_19kHz_gen\n             obj_dir/fm38_19kHz_gen.v\n             obj_dir/fm38_19kHz_gen.sv\n%Warning-WIDTH: data/full_repos/permissive/159954591/rtl/fmSigMix.v:47: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 27 bits.\n                                                                      : ... In instance fmSigMix\n            r_rf_mod_sig <= i_rf_freq[31:0] + rf_mod[26:0];\n                                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module fmSigMix (
    input           i_clk,
    input           i_clk_rf,
    input           i_rst_n,
    
    input   [ 9:0]   i_audio_l,
    input   [ 9:0]   i_audio_r,
    
    input   [15:0]  i_audio_gain,
    input   [15:0]  i_pilot_gain,
    input   [31:0]  i_rf_freq,
    
    output  [31:0]  o_rf_mod_sig
    );

    wire    [26:0]  rf_mod;
    wire    [ 9:0]  mpx_data;
    wire            sw38kHz;
    wire            sw19kHz;
    reg     [31:0]  r_rf_mod_sig;
    

    fm38_19kHz_gen fm38_19kHz_gen_inst (
        .i_clk ( i_clk ),
        .i_rst_n ( i_rst_n ),
        .o_38kHz ( sw38kHz ),
        .o_19kHz ( sw19kHz )
    );
    

    assign mpx_data = sw38kHz ? i_audio_l[9:0] : i_audio_r[9:0];
    assign rf_mod[26:0] = (sw19kHz * {i_pilot_gain[15:0], 1'b0}) + (mpx_data[9:0] * i_audio_gain[15:0]);
    
    always @(posedge i_clk or negedge i_rst_n) begin
        if (~i_rst_n) begin
            r_rf_mod_sig <= 32'd0;
        end else begin
            r_rf_mod_sig <= i_rf_freq[31:0] + rf_mod[26:0];
        end
    end
    
    assign o_rf_mod_sig = r_rf_mod_sig;
    
endmodule
module fmSigMix (
    input           i_clk,
    input           i_clk_rf,
    input           i_rst_n,
    
    input   [ 9:0]   i_audio_l,
    input   [ 9:0]   i_audio_r,
    
    input   [15:0]  i_audio_gain,
    input   [15:0]  i_pilot_gain,
    input   [31:0]  i_rf_freq,
    
    output  [31:0]  o_rf_mod_sig
    );


    wire    [26:0]  rf_mod;
    wire    [ 9:0]  mpx_data;
    wire            sw38kHz;
    wire            sw19kHz;
    reg     [31:0]  r_rf_mod_sig;
    

    fm38_19kHz_gen fm38_19kHz_gen_inst (
        .i_clk ( i_clk ),
        .i_rst_n ( i_rst_n ),
        .o_38kHz ( sw38kHz ),
        .o_19kHz ( sw19kHz )
    );
    

    assign mpx_data = sw38kHz ? i_audio_l[9:0] : i_audio_r[9:0];
    assign rf_mod[26:0] = (sw19kHz * {i_pilot_gain[15:0], 1'b0}) + (mpx_data[9:0] * i_audio_gain[15:0]);
    
    always @(posedge i_clk or negedge i_rst_n) begin
        if (~i_rst_n) begin
            r_rf_mod_sig <= 32'd0;
        end else begin
            r_rf_mod_sig <= i_rf_freq[31:0] + rf_mod[26:0];
        end
    end
    
    assign o_rf_mod_sig = r_rf_mod_sig;
    
endmodule