data/full_repos/permissive/143278/ivltests/vhdl_unary_minus.v
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_unary_minus.v:29: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_unary_minus.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_unary_minus.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_unary_minus.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_unary_minus.v:27: Cannot find file containing module: \'vhdl_unary_minus\'\nvhdl_unary_minus dut(data_in, clk, data_out);\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_unary_minus\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_unary_minus.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_unary_minus.sv\n             vhdl_unary_minus\n             vhdl_unary_minus.v\n             vhdl_unary_minus.sv\n             obj_dir/vhdl_unary_minus\n             obj_dir/vhdl_unary_minus.v\n             obj_dir/vhdl_unary_minus.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vhdl_unary_minus_test;
logic signed [7:0] data_in;
logic signed [7:0] data_out;
logic clk = 1'b0;

vhdl_unary_minus dut(data_in, clk, data_out);

always #10 clk = ~clk;

initial begin
    #5;

    data_in = -12;
    #20;
    if(data_out !== 12) begin
        $display("FAILED 1");
        $finish();
    end

    data_in = 33;
    #20;
    if(data_out !== -33) begin
        $display("FAILED 2");
        $finish();
    end

    $display("PASSED");
    $finish();
end

endmodule
module vhdl_unary_minus_test;

logic signed [7:0] data_in;
logic signed [7:0] data_out;
logic clk = 1'b0;

vhdl_unary_minus dut(data_in, clk, data_out);

always #10 clk = ~clk;

initial begin
    #5;

    data_in = -12;
    #20;
    if(data_out !== 12) begin
        $display("FAILED 1");
        $finish();
    end

    data_in = 33;
    #20;
    if(data_out !== -33) begin
        $display("FAILED 2");
        $finish();
    end

    $display("PASSED");
    $finish();
end

endmodule