data/full_repos/permissive/100918256/One-ShotTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/100918256/One-ShotTest.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100918256/One-ShotTest.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/One-ShotTest.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #100; $stop;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/One-ShotTest.v:58: Unsupported: Ignoring delay on this delayed statement.\n always #1.25 clk=~clk;\n        ^\n%Error: data/full_repos/permissive/100918256/One-ShotTest.v:36: Cannot find file containing module: \'OneShot\'\n OneShot uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/OneShot\n             data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/OneShot.v\n             data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/OneShot.sv\n             OneShot\n             OneShot.v\n             OneShot.sv\n             obj_dir/OneShot\n             obj_dir/OneShot.v\n             obj_dir/OneShot.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module OneShotTest;


	reg pulse;
	reg clk;
	reg rst;


	wire out;


	OneShot uut (
		.pulse(pulse), 
		.clk(clk), 
		.rst(rst), 
		.out(out)
	);

	initial begin

		pulse = 0;
		clk = 0;
		rst = 1;


		#100;
        rst = 0;
		#10;
		pulse = 1;
		#100; $stop;


	end
	always #1.25 clk=~clk;
      
endmodule
module OneShotTest;



	reg pulse;
	reg clk;
	reg rst;


	wire out;


	OneShot uut (
		.pulse(pulse), 
		.clk(clk), 
		.rst(rst), 
		.out(out)
	);

	initial begin

		pulse = 0;
		clk = 0;
		rst = 1;


		#100;
        rst = 0;
		#10;
		pulse = 1;
		#100; $stop;


	end
	always #1.25 clk=~clk;
      
endmodule