data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv
 line:18: before: "*"
1: b'%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:22: Unsupported: Ignoring delay on this delayed statement.\n always  #1 clk=~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:28: Unsupported: Ignoring delay on this delayed statement.\n  #60 rst = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:29: Unsupported: Ignoring delay on this delayed statement.\n        #30 rst = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:30: Unsupported: Ignoring delay on this delayed statement.\n  #50 PB = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:31: Unsupported: Ignoring delay on this delayed statement.\n  #100 PB = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:32: Unsupported: Ignoring delay on this delayed statement.\n  #50 PB = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:33: Unsupported: Ignoring delay on this delayed statement.\n  #3  PB = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:34: Unsupported: Ignoring delay on this delayed statement.\n  #20 PB = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:35: Unsupported: Ignoring delay on this delayed statement.\n  #80 PB = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:17: Cannot find file containing module: \'PB_Debouncer_counter\'\n    PB_Debouncer_counter DUT(\n    ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new,data/full_repos/permissive/104660645/PB_Debouncer_counter\n             data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new,data/full_repos/permissive/104660645/PB_Debouncer_counter.v\n             data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new,data/full_repos/permissive/104660645/PB_Debouncer_counter.sv\n             PB_Debouncer_counter\n             PB_Debouncer_counter.v\n             PB_Debouncer_counter.sv\n             obj_dir/PB_Debouncer_counter\n             obj_dir/PB_Debouncer_counter.v\n             obj_dir/PB_Debouncer_counter.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module debouncer_testbench();
  

	logic clk, rst, PB, PB_pressed_status, PB_pressed_pulse, PB_released_pulse;
	




        
    PB_Debouncer_counter DUT(
            .*
            );
            

	always  #1 clk=~clk;
	

	initial begin
		clk = 1'b0;
		rst = 1'b0;
		#60 rst = 1'b1;
        #30 rst = 1'b0;
		#50 PB = 1'b1;
		#100 PB = 1'b0;
		#50 PB = 1'b1;
		#3  PB = 1'b0;
		#20 PB = 1'b1;
		#80 PB = 1'b0;
	end

endmodule
module debouncer_testbench();

  

	logic clk, rst, PB, PB_pressed_status, PB_pressed_pulse, PB_released_pulse;
	




        
    PB_Debouncer_counter DUT(
            .*
            );
            

	always  #1 clk=~clk;
	

	initial begin
		clk = 1'b0;
		rst = 1'b0;
		#60 rst = 1'b1;
        #30 rst = 1'b0;
		#50 PB = 1'b1;
		#100 PB = 1'b0;
		#50 PB = 1'b1;
		#3  PB = 1'b0;
		#20 PB = 1'b1;
		#80 PB = 1'b0;
	end

endmodule