data/full_repos/permissive/180199545/MainGame/read_potentiometer.v
data/verilator_xmls/538feebf-b56c-44ee-8f55-85f4a9b2c403.xml
module read_potentiometer (
	input reset,
	input sys_clk,
	input [7:0] JPorts,
	output [7:0] Value
	);
	
	reg [7:0] val_out;
	

	always @ (posedge sys_clk)
	begin
		if(reset)
		begin
			val_out <= 8'b00000000;
		end
		else
		begin
			val_out[7:1] <= JPorts[6:0];
			val_out[0] <= 0;
		end
	end
	
	assign Value[7:0] = val_out[7:0];

endmodule
module read_potentiometer (
	input reset,
	input sys_clk,
	input [7:0] JPorts,
	output [7:0] Value
	);

	
	reg [7:0] val_out;
	

	always @ (posedge sys_clk)
	begin
		if(reset)
		begin
			val_out <= 8'b00000000;
		end
		else
		begin
			val_out[7:1] <= JPorts[6:0];
			val_out[0] <= 0;
		end
	end
	
	assign Value[7:0] = val_out[7:0];

endmodule