data/full_repos/permissive/129155059/proyecto-01/tester.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/tester.v:11: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("pcie.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/tester.v:12: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:21: Unsupported: Ignoring delay on this delayed statement.\n    repeat(2) #250 CLK_2MHz = ~CLK_2MHz;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #500\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:24: Unsupported: Ignoring delay on this delayed statement.\n    forever #250 CLK_2MHz = ~CLK_2MHz;\n            ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/tester.v:40: syntax error, unexpected \'@\'\n    @(posedge ENB)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:108: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:111: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:114: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:121: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:125: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:129: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:133: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:141: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:145: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:148: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:151: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:158: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:162: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:166: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:170: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:174: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:178: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:182: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:185: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:188: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/tester.v:192: Unsupported: Ignoring delay on this delayed statement.\n    #1000 $finish;\n    ^\n%Error: Exiting due to 3 error(s), 40 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester(      output reg  [7:0]   IN_COM, IN_PAD, IN_SKP, IN_STP, IN_SDP, IN_END, IN_EDB, IN_FTS, IN_IDL, IN_TLP,
                    output reg          CLK_2MHz,
                    output reg  [3:0]   IN_CTRL,
                    output reg          ENB,
                    output reg          reset
                    );

  initial begin
    $dumpfile("pcie.vcd");
    $dumpvars;
  end

  initial begin
    CLK_2MHz = 1'b0;
    ENB = 1'b0;
    reset = 1'b0;

    #500
    repeat(2) #250 CLK_2MHz = ~CLK_2MHz;
    ENB = 1'b1;
    reset = 1'b1;
    forever #250 CLK_2MHz = ~CLK_2MHz;
  end

  initial begin
    IN_CTRL = 0;
    IN_TLP = 8'hFF;
    IN_COM = 8'hBC;
    IN_PAD = 8'hC7;
    IN_SKP = 8'hAC;
    IN_STP = 8'hAA;
    IN_SDP = 8'hE5;
    IN_END = 8'hF6;
    IN_EDB = 8'hDF;
    IN_FTS = 8'hA8;
    IN_IDL = 8'hAE;

    @(posedge ENB)

    IN_CTRL = 0;


    #1000
    IN_CTRL = 1;


    #1000
    IN_CTRL = 2;



    #1000
    IN_CTRL = 3;


    #1000
    IN_CTRL = 4;


    #1000
    IN_CTRL = 5;


    #1000
    IN_CTRL = 6;


    #1000
    IN_CTRL = 7;

    #1000
    IN_CTRL = 8;

    #1000
    IN_CTRL = 9;


    IN_CTRL = 0;


    #1000
    IN_CTRL = 1;


    #1000
    IN_CTRL = 2;



    #1000
    IN_CTRL = 3;


    #1000
    IN_CTRL = 4;


    #1000
    IN_CTRL = 5;


    #1000
    IN_CTRL = 6;


    #1000
    IN_CTRL = 7;

    #1000
    IN_CTRL = 8;

    #1000
    IN_CTRL = 9;


    IN_CTRL = 0;


    #1000
    IN_CTRL = 1;


    #1000
    IN_CTRL = 2;


    #1000
    IN_CTRL = 3;


    #1000
    IN_CTRL = 4;


    #1000
    IN_CTRL = 5;


    #1000
    IN_CTRL = 6;


    #1000
    IN_CTRL = 7;

    #1000
    IN_CTRL = 8;

    #1000
    IN_CTRL = 9;


    IN_CTRL = 0;


    #1000
    IN_CTRL = 1;


    #1000
    IN_CTRL = 2;


    #1000
    IN_CTRL = 3;


    #1000
    IN_CTRL = 4;


    #1000
    IN_CTRL = 5;


    #1000
    IN_CTRL = 6;


    #1000
    IN_CTRL = 7;

    #1000
    IN_CTRL = 8;

    #1000
    IN_CTRL = 9;


    #1000 $finish;
  end

endmodule
module tester(      output reg  [7:0]   IN_COM, IN_PAD, IN_SKP, IN_STP, IN_SDP, IN_END, IN_EDB, IN_FTS, IN_IDL, IN_TLP,
                    output reg          CLK_2MHz,
                    output reg  [3:0]   IN_CTRL,
                    output reg          ENB,
                    output reg          reset
                    );


  initial begin
    $dumpfile("pcie.vcd");
    $dumpvars;
  end

  initial begin
    CLK_2MHz = 1'b0;
    ENB = 1'b0;
    reset = 1'b0;

    #500
    repeat(2) #250 CLK_2MHz = ~CLK_2MHz;
    ENB = 1'b1;
    reset = 1'b1;
    forever #250 CLK_2MHz = ~CLK_2MHz;
  end

  initial begin
    IN_CTRL = 0;
    IN_TLP = 8'hFF;
    IN_COM = 8'hBC;
    IN_PAD = 8'hC7;
    IN_SKP = 8'hAC;
    IN_STP = 8'hAA;
    IN_SDP = 8'hE5;
    IN_END = 8'hF6;
    IN_EDB = 8'hDF;
    IN_FTS = 8'hA8;
    IN_IDL = 8'hAE;

    @(posedge ENB)

    IN_CTRL = 0;


    #1000
    IN_CTRL = 1;


    #1000
    IN_CTRL = 2;



    #1000
    IN_CTRL = 3;


    #1000
    IN_CTRL = 4;


    #1000
    IN_CTRL = 5;


    #1000
    IN_CTRL = 6;


    #1000
    IN_CTRL = 7;

    #1000
    IN_CTRL = 8;

    #1000
    IN_CTRL = 9;


    IN_CTRL = 0;


    #1000
    IN_CTRL = 1;


    #1000
    IN_CTRL = 2;



    #1000
    IN_CTRL = 3;


    #1000
    IN_CTRL = 4;


    #1000
    IN_CTRL = 5;


    #1000
    IN_CTRL = 6;


    #1000
    IN_CTRL = 7;

    #1000
    IN_CTRL = 8;

    #1000
    IN_CTRL = 9;


    IN_CTRL = 0;


    #1000
    IN_CTRL = 1;


    #1000
    IN_CTRL = 2;


    #1000
    IN_CTRL = 3;


    #1000
    IN_CTRL = 4;


    #1000
    IN_CTRL = 5;


    #1000
    IN_CTRL = 6;


    #1000
    IN_CTRL = 7;

    #1000
    IN_CTRL = 8;

    #1000
    IN_CTRL = 9;


    IN_CTRL = 0;


    #1000
    IN_CTRL = 1;


    #1000
    IN_CTRL = 2;


    #1000
    IN_CTRL = 3;


    #1000
    IN_CTRL = 4;


    #1000
    IN_CTRL = 5;


    #1000
    IN_CTRL = 6;


    #1000
    IN_CTRL = 7;

    #1000
    IN_CTRL = 8;

    #1000
    IN_CTRL = 9;


    #1000 $finish;
  end

endmodule