data/full_repos/permissive/181665138/verilog/capitolo_v/Elemento_Contatore_Base_10.v
 line:50: before: "=="
1: b'%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Elemento_Contatore_Base_10.v:50: syntax error, unexpected ==, expecting \')\' or \',\' or or\n    always @(reset_ == 0) #1 OUTR<=\'H0;\n                    ^~\n%Warning-STMTDLY: data/full_repos/permissive/181665138/verilog/capitolo_v/Elemento_Contatore_Base_10.v:51: Unsupported: Ignoring delay on this delayed statement.\n    always @(posedge clock) if (reset_ == 1) #3 OUTR <= a3_a0;\n                                             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module Elemento_Contatore_Base_3(eu, q3_q0, ei, clock, reset_);
    input clock, reset_;
    input ei;
    output eu;
    output [3:0] q3_q0;

    reg [3:0] OUTR;
    assign q=OUTR;

    wire [3:0] a1_a0;

    assign {a1_a0, eu} = ({q3_q0, ei} == 'B00000)?'B00000:
                         ({q3_q0, ei} == 'B00010)?'B00010:
                         ({q3_q0, ei} == 'B00100)?'B00100:
                         ({q3_q0, ei} == 'B00110)?'B00110:
                         ({q3_q0, ei} == 'B01000)?'B01000:
                         ({q3_q0, ei} == 'B01010)?'B01010:
                         ({q3_q0, ei} == 'B01100)?'B01100:
                         ({q3_q0, ei} == 'B01110)?'B01110:
                         ({q3_q0, ei} == 'B10000)?'B10000:
                         ({q3_q0, ei} == 'B10010)?'B10010:
                         ({q3_q0, ei} == 'B00001)?'B00010:
                         ({q3_q0, ei} == 'B00011)?'B00100:
                         ({q3_q0, ei} == 'B00101)?'B00110:
                         ({q3_q0, ei} == 'B00111)?'B01000:
                         ({q3_q0, ei} == 'B01001)?'B01010:
                         ({q3_q0, ei} == 'B01011)?'B01100:
                         ({q3_q0, ei} == 'B01101)?'B01110:
                         ({q3_q0, ei} == 'B01111)?'B10000:
                         ({q3_q0, ei} == 'B10001)?'B10010:
                         ({q3_q0, ei} == 'B10011)?'B00001:
'BXXXXX;

    always @(reset_ == 0) #1 OUTR<='H0;
    always @(posedge clock) if (reset_ == 1) #3 OUTR <= a3_a0;
endmodule
module Elemento_Contatore_Base_3(eu, q3_q0, ei, clock, reset_);

    input clock, reset_;
    input ei;
    output eu;
    output [3:0] q3_q0;

    reg [3:0] OUTR;
    assign q=OUTR;

    wire [3:0] a1_a0;

    assign {a1_a0, eu} = ({q3_q0, ei} == 'B00000)?'B00000:
                         ({q3_q0, ei} == 'B00010)?'B00010:
                         ({q3_q0, ei} == 'B00100)?'B00100:
                         ({q3_q0, ei} == 'B00110)?'B00110:
                         ({q3_q0, ei} == 'B01000)?'B01000:
                         ({q3_q0, ei} == 'B01010)?'B01010:
                         ({q3_q0, ei} == 'B01100)?'B01100:
                         ({q3_q0, ei} == 'B01110)?'B01110:
                         ({q3_q0, ei} == 'B10000)?'B10000:
                         ({q3_q0, ei} == 'B10010)?'B10010:
                         ({q3_q0, ei} == 'B00001)?'B00010:
                         ({q3_q0, ei} == 'B00011)?'B00100:
                         ({q3_q0, ei} == 'B00101)?'B00110:
                         ({q3_q0, ei} == 'B00111)?'B01000:
                         ({q3_q0, ei} == 'B01001)?'B01010:
                         ({q3_q0, ei} == 'B01011)?'B01100:
                         ({q3_q0, ei} == 'B01101)?'B01110:
                         ({q3_q0, ei} == 'B01111)?'B10000:
                         ({q3_q0, ei} == 'B10001)?'B10010:
                         ({q3_q0, ei} == 'B10011)?'B00001:
'BXXXXX;

    always @(reset_ == 0) #1 OUTR<='H0;
    always @(posedge clock) if (reset_ == 1) #3 OUTR <= a3_a0;
endmodule