data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v
 line:93: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000000;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000001000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000001001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000001010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000001011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000001100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000001101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000001110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000001111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_addr  = 11\'b00000000100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #1 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:98: Unsupported: Ignoring delay on this delayed statement.\n    always #1 i_clk = ~i_clk;                      \n           ^\n%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_data_mem.v:100: Cannot find file containing module: \'data_mem\'\n    data_mem #(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/data_mem\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/data_mem.v\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/data_mem.sv\n             data_mem\n             data_mem.v\n             data_mem.sv\n             obj_dir/data_mem\n             obj_dir/data_mem.v\n             obj_dir/data_mem.sv\n%Error: Exiting due to 1 error(s), 29 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_data_mem();
    parameter   RAM_WIDTH = 16;
    parameter   RAM_DEPTH = 1024;
    parameter   RAM_PERFORMANCE = "LOW_LATENCY";
    parameter   INIT_FILE = "";





    reg [11-1:0]                    i_addr;
    reg [RAM_WIDTH-1:0]             i_data;
    reg i_clk;
    reg wea;


    wire [RAM_WIDTH-1:0]            o_data;

    initial begin
        i_clk   = 1'b0;
        wea     = 1'b0;
        i_addr  = 0;
        i_data  = 0;


        #2 i_addr  = 11'b00000000000;
        #2 i_addr  = 11'b00000000001;
        #2 i_addr  = 11'b00000000010;
        #2 i_addr  = 11'b00000000011;
        #2 i_addr  = 11'b00000000100;
        #2 i_addr  = 11'b00000000101;
        #2 i_addr  = 11'b00000000110;
        #2 i_addr  = 11'b00000000111;
        #2 i_addr  = 11'b00000001000;
        #2 i_addr  = 11'b00000001001;
        #2 i_addr  = 11'b00000001010;
        #2 i_addr  = 11'b00000001011;
        #2 i_addr  = 11'b00000001100;
        #2 i_addr  = 11'b00000001101;
        #2 i_addr  = 11'b00000001110;
        #2 i_addr  = 11'b00000001111;
        

        #2
        i_addr  = 11'b00000000000;
        i_data  = 16'h0fff;
        wea     = 1;
        #2
        wea     = 0;
        
        #2
        i_addr  = 11'b00000000001;
        i_data  = 16'h0f0f;
        wea     = 1;
        #2
        wea     = 0;
        
        #2
        i_addr  = 11'b00000000010;
        i_data  = 16'h0f05;
        wea     = 1;
        #2
        wea     = 0;
        
        #2 i_addr  = 11'b00000000000;
        #2 i_addr  = 11'b00000000001;
        #2 i_addr  = 11'b00000000010;
        #2 i_addr  = 11'b00000000011;
        #2 i_addr  = 11'b00000000100;
        
        #1 $finish;
        
        
    end
    
    always #1 i_clk = ~i_clk;

    data_mem #(
        .RAM_WIDTH          (RAM_WIDTH),
        .RAM_DEPTH          (RAM_DEPTH),
        .RAM_PERFORMANCE    (RAM_PERFORMANCE),
        .INIT_FILE          (INIT_FILE)
    )
    u_data_mem
    (
        .i_addr     (i_addr),
        .i_data     (i_data),
        .i_clk      (i_clk),
        .wea        (wea),
        .o_data     (o_data)
    );
    
       
endmodule
module tb_data_mem();

    parameter   RAM_WIDTH = 16;
    parameter   RAM_DEPTH = 1024;
    parameter   RAM_PERFORMANCE = "LOW_LATENCY";
    parameter   INIT_FILE = "";





    reg [11-1:0]                    i_addr;
    reg [RAM_WIDTH-1:0]             i_data;
    reg i_clk;
    reg wea;


    wire [RAM_WIDTH-1:0]            o_data;

    initial begin
        i_clk   = 1'b0;
        wea     = 1'b0;
        i_addr  = 0;
        i_data  = 0;


        #2 i_addr  = 11'b00000000000;
        #2 i_addr  = 11'b00000000001;
        #2 i_addr  = 11'b00000000010;
        #2 i_addr  = 11'b00000000011;
        #2 i_addr  = 11'b00000000100;
        #2 i_addr  = 11'b00000000101;
        #2 i_addr  = 11'b00000000110;
        #2 i_addr  = 11'b00000000111;
        #2 i_addr  = 11'b00000001000;
        #2 i_addr  = 11'b00000001001;
        #2 i_addr  = 11'b00000001010;
        #2 i_addr  = 11'b00000001011;
        #2 i_addr  = 11'b00000001100;
        #2 i_addr  = 11'b00000001101;
        #2 i_addr  = 11'b00000001110;
        #2 i_addr  = 11'b00000001111;
        

        #2
        i_addr  = 11'b00000000000;
        i_data  = 16'h0fff;
        wea     = 1;
        #2
        wea     = 0;
        
        #2
        i_addr  = 11'b00000000001;
        i_data  = 16'h0f0f;
        wea     = 1;
        #2
        wea     = 0;
        
        #2
        i_addr  = 11'b00000000010;
        i_data  = 16'h0f05;
        wea     = 1;
        #2
        wea     = 0;
        
        #2 i_addr  = 11'b00000000000;
        #2 i_addr  = 11'b00000000001;
        #2 i_addr  = 11'b00000000010;
        #2 i_addr  = 11'b00000000011;
        #2 i_addr  = 11'b00000000100;
        
        #1 $finish;
        
        
    end
    
    always #1 i_clk = ~i_clk;

    data_mem #(
        .RAM_WIDTH          (RAM_WIDTH),
        .RAM_DEPTH          (RAM_DEPTH),
        .RAM_PERFORMANCE    (RAM_PERFORMANCE),
        .INIT_FILE          (INIT_FILE)
    )
    u_data_mem
    (
        .i_addr     (i_addr),
        .i_data     (i_data),
        .i_clk      (i_clk),
        .wea        (wea),
        .o_data     (o_data)
    );
    
       
endmodule