data/full_repos/permissive/139213403/FPGA/uart.v
1: b"%Error: data/full_repos/permissive/139213403/FPGA/uart.v:31: Cannot find file containing module: 'mod_m_counter'\nmod_m_counter #(.M_BITS(DVSR_BIT)) baud_gen_unit(.clk(clk), .reset(reset), .m(dvsr), .q(), .max_tick(tick)); \n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/mod_m_counter\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/mod_m_counter.v\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/mod_m_counter.sv\n             mod_m_counter\n             mod_m_counter.v\n             mod_m_counter.sv\n             obj_dir/mod_m_counter\n             obj_dir/mod_m_counter.v\n             obj_dir/mod_m_counter.sv\n%Error: data/full_repos/permissive/139213403/FPGA/uart.v:32: Cannot find file containing module: 'edge_trigger'\nedge_trigger uart_rx_trigger(.clk(clk), .reset(reset), .in(rd_uart), .en(1'b1), .tick(rd_uart_tick));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/139213403/FPGA/uart.v:33: Cannot find file containing module: 'fifo'\nfifo #(.B(DBIT), .W(FIFO_R)) fifo_rx_unit(.clk(clk), .reset(reset), .rd(rd_uart_tick), .wr(rx_done_tick), .w_data(rx_data_out), .empty(rx_empty), .full(rx_full), .r_data(fifo_r_data), .of(e_rxof), .uf(e_rxuf));\n^~~~\n%Error: data/full_repos/permissive/139213403/FPGA/uart.v:34: Cannot find file containing module: 'uart_rx'\nuart_rx #(.DBIT(DBIT)) uart_rx_unit(.clk(clk), .reset(reset), .dbit(dbit), .pbit(pbit), .sb_tick(sb_tick), .os_tick(os_tick), .rx(rx), .s_tick(tick), .rx_done_tick(rx_done_tick), .dout(rx_data_out), .e_parity(e_parity), .e_frame(e_frame));\n^~~~~~~\n%Error: data/full_repos/permissive/139213403/FPGA/uart.v:35: Cannot find file containing module: 'edge_trigger'\nedge_trigger uart_tx_trigger(.clk(clk), .reset(reset), .in(wr_uart), .en(1'b1), .tick(wr_uart_tick));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/139213403/FPGA/uart.v:36: Cannot find file containing module: 'fifo'\nfifo #(.B(DBIT), .W(FIFO_W)) fifo_tx_unit(.clk(clk), .reset(reset), .rd(tx_done_tick), .wr(wr_uart_tick), .w_data(w_data), .empty(tx_empty), .full(tx_full), .r_data(tx_fifo_out), .of(e_txof), .uf(e_txuf));\n^~~~\n%Error: data/full_repos/permissive/139213403/FPGA/uart.v:37: Cannot find file containing module: 'uart_tx'\nuart_tx #(.DBIT(DBIT)) uart_tx_unit(.clk(clk), .reset(reset), .dbit(dbit), .pbit(pbit), .sb_tick(sb_tick), .os_tick(os_tick), .tx_start(tx_fifo_not_empty), .s_tick(tick), .din(tx_fifo_out), .tx_done_tick(tx_done_tick), .tx(tx));\n^~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module uart
#(
	parameter FIFO_R = 2,
	          FIFO_W = 2,
			    DVSR_BIT = 8,
             DBIT = 8
)
(
	input wire clk, reset,
	input wire rd_uart, wr_uart, rx,
	input wire [3:0] dbit,
	input wire [1:0] pbit,
	input wire [7:0] sb_tick,
	input wire [7:0] os_tick,
	input wire [DVSR_BIT-1:0] dvsr,
	input wire [DBIT-1:0] w_data,
	output wire tx_full, rx_empty, tx,
	output wire [DBIT-1:0] r_data,
	output wire tx_done_tick, rx_done_tick,
	output wire e_parity, e_frame, e_rxof, e_txof, e_rxuf, e_txuf,
	output wire rx_full, tx_empty
);


wire tick;
wire tx_fifo_not_empty;
wire [DBIT-1:0] tx_fifo_out, rx_data_out, fifo_r_data;
wire rd_uart_tick, wr_uart_tick;


mod_m_counter #(.M_BITS(DVSR_BIT)) baud_gen_unit(.clk(clk), .reset(reset), .m(dvsr), .q(), .max_tick(tick)); 
edge_trigger uart_rx_trigger(.clk(clk), .reset(reset), .in(rd_uart), .en(1'b1), .tick(rd_uart_tick));
fifo #(.B(DBIT), .W(FIFO_R)) fifo_rx_unit(.clk(clk), .reset(reset), .rd(rd_uart_tick), .wr(rx_done_tick), .w_data(rx_data_out), .empty(rx_empty), .full(rx_full), .r_data(fifo_r_data), .of(e_rxof), .uf(e_rxuf));
uart_rx #(.DBIT(DBIT)) uart_rx_unit(.clk(clk), .reset(reset), .dbit(dbit), .pbit(pbit), .sb_tick(sb_tick), .os_tick(os_tick), .rx(rx), .s_tick(tick), .rx_done_tick(rx_done_tick), .dout(rx_data_out), .e_parity(e_parity), .e_frame(e_frame));
edge_trigger uart_tx_trigger(.clk(clk), .reset(reset), .in(wr_uart), .en(1'b1), .tick(wr_uart_tick));
fifo #(.B(DBIT), .W(FIFO_W)) fifo_tx_unit(.clk(clk), .reset(reset), .rd(tx_done_tick), .wr(wr_uart_tick), .w_data(w_data), .empty(tx_empty), .full(tx_full), .r_data(tx_fifo_out), .of(e_txof), .uf(e_txuf));
uart_tx #(.DBIT(DBIT)) uart_tx_unit(.clk(clk), .reset(reset), .dbit(dbit), .pbit(pbit), .sb_tick(sb_tick), .os_tick(os_tick), .tx_start(tx_fifo_not_empty), .s_tick(tick), .din(tx_fifo_out), .tx_done_tick(tx_done_tick), .tx(tx));

assign tx_fifo_not_empty = ~tx_empty;
assign r_data = fifo_r_data;

endmodule
module uart
#(
	parameter FIFO_R = 2,
	          FIFO_W = 2,
			    DVSR_BIT = 8,
             DBIT = 8
)
(
	input wire clk, reset,
	input wire rd_uart, wr_uart, rx,
	input wire [3:0] dbit,
	input wire [1:0] pbit,
	input wire [7:0] sb_tick,
	input wire [7:0] os_tick,
	input wire [DVSR_BIT-1:0] dvsr,
	input wire [DBIT-1:0] w_data,
	output wire tx_full, rx_empty, tx,
	output wire [DBIT-1:0] r_data,
	output wire tx_done_tick, rx_done_tick,
	output wire e_parity, e_frame, e_rxof, e_txof, e_rxuf, e_txuf,
	output wire rx_full, tx_empty
);



wire tick;
wire tx_fifo_not_empty;
wire [DBIT-1:0] tx_fifo_out, rx_data_out, fifo_r_data;
wire rd_uart_tick, wr_uart_tick;


mod_m_counter #(.M_BITS(DVSR_BIT)) baud_gen_unit(.clk(clk), .reset(reset), .m(dvsr), .q(), .max_tick(tick)); 
edge_trigger uart_rx_trigger(.clk(clk), .reset(reset), .in(rd_uart), .en(1'b1), .tick(rd_uart_tick));
fifo #(.B(DBIT), .W(FIFO_R)) fifo_rx_unit(.clk(clk), .reset(reset), .rd(rd_uart_tick), .wr(rx_done_tick), .w_data(rx_data_out), .empty(rx_empty), .full(rx_full), .r_data(fifo_r_data), .of(e_rxof), .uf(e_rxuf));
uart_rx #(.DBIT(DBIT)) uart_rx_unit(.clk(clk), .reset(reset), .dbit(dbit), .pbit(pbit), .sb_tick(sb_tick), .os_tick(os_tick), .rx(rx), .s_tick(tick), .rx_done_tick(rx_done_tick), .dout(rx_data_out), .e_parity(e_parity), .e_frame(e_frame));
edge_trigger uart_tx_trigger(.clk(clk), .reset(reset), .in(wr_uart), .en(1'b1), .tick(wr_uart_tick));
fifo #(.B(DBIT), .W(FIFO_W)) fifo_tx_unit(.clk(clk), .reset(reset), .rd(tx_done_tick), .wr(wr_uart_tick), .w_data(w_data), .empty(tx_empty), .full(tx_full), .r_data(tx_fifo_out), .of(e_txof), .uf(e_txuf));
uart_tx #(.DBIT(DBIT)) uart_tx_unit(.clk(clk), .reset(reset), .dbit(dbit), .pbit(pbit), .sb_tick(sb_tick), .os_tick(os_tick), .tx_start(tx_fifo_not_empty), .s_tick(tick), .din(tx_fifo_out), .tx_done_tick(tx_done_tick), .tx(tx));

assign tx_fifo_not_empty = ~tx_empty;
assign r_data = fifo_r_data;

endmodule