data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #HALF_PERIOD;\n  ^\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter #(
	parameter WIDTH = 8,
	parameter LOAD_VALUE = 8'h45
) (
	input clk,
	input rst,
	input load,
	output [WIDTH-1:0] cnt_out
);
	reg [WIDTH-1:0] counter = 0;
	always @(posedge clk) begin
		if (~rst) begin
			counter <= 0;
		end else if (load) begin
			counter <= LOAD_VALUE;
		end else begin
			counter <= counter + 1'b1;
		end
	end
	assign cnt_out = counter;
endmodule
module counter #(
	parameter WIDTH = 8,
	parameter LOAD_VALUE = 8'h45
) (
	input clk,
	input rst,
	input load,
	output [WIDTH-1:0] cnt_out
);

	reg [WIDTH-1:0] counter = 0;
	always @(posedge clk) begin
		if (~rst) begin
			counter <= 0;
		end else if (load) begin
			counter <= LOAD_VALUE;
		end else begin
			counter <= counter + 1'b1;
		end
	end
	assign cnt_out = counter;
endmodule