data/full_repos/permissive/119715647/sim/gameFunct/BlockShiftTop_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/BlockShiftTop_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/BlockShiftTop_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: data/full_repos/permissive/119715647/sim/gameFunct/BlockShiftTop_tb.v:7: Cannot find file containing module: \'BlockShiftTop\'\n  BlockShiftTop DUT_BSTop(blockLoc, stopBtn, adjClkPulse, newBlockLoc);\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119715647/sim/gameFunct,data/full_repos/permissive/119715647/BlockShiftTop\n             data/full_repos/permissive/119715647/sim/gameFunct,data/full_repos/permissive/119715647/BlockShiftTop.v\n             data/full_repos/permissive/119715647/sim/gameFunct,data/full_repos/permissive/119715647/BlockShiftTop.sv\n             BlockShiftTop\n             BlockShiftTop.v\n             BlockShiftTop.sv\n             obj_dir/BlockShiftTop\n             obj_dir/BlockShiftTop.v\n             obj_dir/BlockShiftTop.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module BlockShiftTop_tb();
  reg [7:0] blockLoc;
  reg stopBtn;
  reg adjClkPulse;
  wire [7:0] newBlockLoc;

  BlockShiftTop DUT_BSTop(blockLoc, stopBtn, adjClkPulse, newBlockLoc);

  always begin
    adjClkPulse = 1;
    #10;
    adjClkPulse = 0;
    #10;
  end

  initial begin
    blockLoc = 8'b10000000;
  end
endmodule
module BlockShiftTop_tb();

  reg [7:0] blockLoc;
  reg stopBtn;
  reg adjClkPulse;
  wire [7:0] newBlockLoc;

  BlockShiftTop DUT_BSTop(blockLoc, stopBtn, adjClkPulse, newBlockLoc);

  always begin
    adjClkPulse = 1;
    #10;
    adjClkPulse = 0;
    #10;
  end

  initial begin
    blockLoc = 8'b10000000;
  end
endmodule