data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v
 line:1: before: "function"
1: b'%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:4: syntax error, unexpected ::, expecting \'(\' or \';\'\nfunction void UNI_cell::post_randomize();\n                      ^~\n                                                                   : ... Perhaps \'UNI_cell\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:13: Unsupported: virtual classes\nvirtual class BaseTr;\n^~~~~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:13: Unsupported: classes\nvirtual class BaseTr;\n        ^~~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:14: Unsupported: new constructor\n  function new();\n           ^~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:15: syntax error, unexpected ++, expecting \';\'\n    id = count++;\n              ^~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:18: Unsupported: pure virtual class method\n  pure virtual function bit compare(input BaseTr to);\n  ^~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:19: Unsupported: pure virtual class method\n  pure virtual function BaseTr copy(input BaseTr to=null);\n  ^~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:20: Unsupported: pure virtual class method\n  pure virtual function void display(input string prefix="");\n  ^~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:26: syntax error, unexpected "\'", expecting TYPE-IDENTIFIER\ninteger threes[4] = \' { 3, 6, 9, 12 };\n                    ^\n%Error: Exiting due to 9 error(s)\n'
module zmuxi31d_prim (z, d0, d1, d2, s0, s1, s2);
output z;
input  d0, d1, d2, s0, s1, s2;

              
                                              
      
wire [2:0] sel = {s0,s1,s2};
assign cwp_no_change_m = ~|(cwp_xor_m[3-1:0]);
reg z;
    always @ (s2 or d2 or s1 or d1 or s0 or d0)
        casez ({s2,d2,s1,d1,s0,d0})
            6'b0?0?10: z = 1'b1;
            6'b0?0?11: z = 1'b0;
            6'b0?100?: z = 1'b1;
            6'b0?110?: z = 1'b0;
            6'b0?1010: z = 1'b1;
            6'b0?1111: z = 1'b0;
            6'b100?0?: z = 1'b1;
            6'b110?0?: z = 1'b0;
            6'b100?10: z = 1'b1;
            6'b110?11: z = 1'b0;
            6'b10100?: z = 1'b1;
            6'b11110?: z = 1'b0;
            6'b101010: z = 1'b1;
            6'b111111: z = 1'b0;
            default: z = 1'bx;
        endcase

    m2 #(1) u2(.c(a), .d    ({a,b,c}));
    m1 #(1) u1(.c(w));
endmodule
module zmuxi31d_prim (z, d0, d1, d2, s0, s1, s2);

output z;
input  d0, d1, d2, s0, s1, s2;

              
                                              
      
wire [2:0] sel = {s0,s1,s2};
assign cwp_no_change_m = ~|(cwp_xor_m[3-1:0]);
reg z;
    always @ (s2 or d2 or s1 or d1 or s0 or d0)
        casez ({s2,d2,s1,d1,s0,d0})
            6'b0?0?10: z = 1'b1;
            6'b0?0?11: z = 1'b0;
            6'b0?100?: z = 1'b1;
            6'b0?110?: z = 1'b0;
            6'b0?1010: z = 1'b1;
            6'b0?1111: z = 1'b0;
            6'b100?0?: z = 1'b1;
            6'b110?0?: z = 1'b0;
            6'b100?10: z = 1'b1;
            6'b110?11: z = 1'b0;
            6'b10100?: z = 1'b1;
            6'b11110?: z = 1'b0;
            6'b101010: z = 1'b1;
            6'b111111: z = 1'b0;
            default: z = 1'bx;
        endcase

    m2 #(1) u2(.c(a), .d    ({a,b,c}));
    m1 #(1) u1(.c(w));
endmodule