data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v:111: Cannot find include file: mc_defines.v\n`include "mc_defines.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl,data/full_repos/permissive/137416811/mc_defines.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl,data/full_repos/permissive/137416811/mc_defines.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl,data/full_repos/permissive/137416811/mc_defines.v.sv\n             mc_defines.v\n             mc_defines.v.v\n             mc_defines.v.sv\n             obj_dir/mc_defines.v\n             obj_dir/mc_defines.v.v\n             obj_dir/mc_defines.v.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v:181: Define or directive not defined: \'`MC_DEF_SEL\'\n if(rst_r2)   csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? \n                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v:181: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(rst_r2)   csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? \n                                                    ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v:187: Define or directive not defined: \'`MC_DEF_SEL\'\n if(rst_r2)   tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?\n                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v:187: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(rst_r2)   tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?\n                                                    ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v:188: Define or directive not defined: \'`MC_DEF_POR_TMS\'\n      `MC_DEF_POR_TMS : 32\'h0;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v:203: Define or directive not defined: \'`MC_MEM_TYPE_SDRAM\'\n if(lmr_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM))\n                              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v:203: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(lmr_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM))\n                                                ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v:219: Define or directive not defined: \'`MC_MEM_TYPE_SDRAM\'\n if(init_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM) & csc[0] & !inited)\n                               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v:219: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(init_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM) & csc[0] & !inited)\n                                                 ^\n%Error: Exiting due to 10 error(s)\n'
module mc_cs_rf_dummy(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs,
		wp_err, lmr_req, lmr_ack, init_req, init_ack );

parameter	[2:0]	this_cs = 0;

input		clk, rst;
input		wb_we_i;
input	[31:0]	din;
input		rf_we;
input	[31:0]	addr;

output	[31:0]	csc;
output	[31:0]	tms;
input	[31:0]	poc;
input	[31:0]	csc_mask;
output		cs;
output		wp_err;

output		lmr_req;
input		lmr_ack;
output		init_req;
input		init_ack;

assign csc = 32'h0;
assign tms = 32'h0;
assign cs = 1'b0;
assign wp_err = 1'b0;
assign lmr_req = 1'b0;
assign init_req = 1'b0;

endmodule
module mc_cs_rf_dummy(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs,
		wp_err, lmr_req, lmr_ack, init_req, init_ack );


parameter	[2:0]	this_cs = 0;

input		clk, rst;
input		wb_we_i;
input	[31:0]	din;
input		rf_we;
input	[31:0]	addr;

output	[31:0]	csc;
output	[31:0]	tms;
input	[31:0]	poc;
input	[31:0]	csc_mask;
output		cs;
output		wp_err;

output		lmr_req;
input		lmr_ack;
output		init_req;
input		init_ack;

assign csc = 32'h0;
assign tms = 32'h0;
assign cs = 1'b0;
assign wp_err = 1'b0;
assign lmr_req = 1'b0;
assign init_req = 1'b0;

endmodule