data/full_repos/permissive/154123726/3rdParty/luffa/Luffa_Chaining.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/154123726/3rdParty/luffa/Luffa_Chaining.v:113: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                           : ... Top module \'MESSAGE_INJECTION\'\nmodule MESSAGE_INJECTION(\n       ^~~~~~~~~~~~~~~~~\n                                                                                           : ... Top module \'PERMUTATION_Q\'\nmodule PERMUTATION_Q(\n       ^~~~~~~~~~~~~\n                                                                                           : ... Top module \'GEN_CONST\'\nmodule GEN_CONST(\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module GEN_CONST(
	tl, tr,
	const_0, const_4, new_tl, new_tr
);

input  [31:0] tl, tr;
output [31:0] const_0, const_4, new_tl, new_tr;

parameter GL = 32'hc4d6496c;
parameter GR = 32'h55c61c8d;

wire [31:0] tl_0, tr_0, mid_tl, mid_tr, tl_1, tr_1;
wire        c0, c1;


assign c0 = tl[31];
assign tl_0 = {tl[30:0],1'h0} | {31'h0,tr[31]};
assign tr_0 = {tr[30:0],1'h0};
assign mid_tl = (c0 == 1'b1)? (tr_0 ^ GR) : tr_0;
assign mid_tr = (c0 == 1'b1)? (tl_0 ^ GL) : tl_0;
assign const_0 = mid_tr;
assign c1 = mid_tl[31];
assign tl_1 = {mid_tl[30:0],1'h0} | {31'h0,mid_tr[31]};
assign tr_1 = {mid_tr[30:0],1'h0};
assign new_tl = (c1 == 1'b1)? (tr_1 ^ GR) : tr_1;
assign new_tr = (c1 == 1'b1)? (tl_1 ^ GL) : tl_1;
assign const_4 = new_tr;

endmodule
module GEN_CONST(
	tl, tr,
	const_0, const_4, new_tl, new_tr
);


input  [31:0] tl, tr;
output [31:0] const_0, const_4, new_tl, new_tr;

parameter GL = 32'hc4d6496c;
parameter GR = 32'h55c61c8d;

wire [31:0] tl_0, tr_0, mid_tl, mid_tr, tl_1, tr_1;
wire        c0, c1;


assign c0 = tl[31];
assign tl_0 = {tl[30:0],1'h0} | {31'h0,tr[31]};
assign tr_0 = {tr[30:0],1'h0};
assign mid_tl = (c0 == 1'b1)? (tr_0 ^ GR) : tr_0;
assign mid_tr = (c0 == 1'b1)? (tl_0 ^ GL) : tl_0;
assign const_0 = mid_tr;
assign c1 = mid_tl[31];
assign tl_1 = {mid_tl[30:0],1'h0} | {31'h0,mid_tr[31]};
assign tr_1 = {mid_tr[30:0],1'h0};
assign new_tl = (c1 == 1'b1)? (tr_1 ^ GR) : tr_1;
assign new_tr = (c1 == 1'b1)? (tl_1 ^ GL) : tl_1;
assign const_4 = new_tr;

endmodule