data/full_repos/permissive/177038316/project.v
1: b'%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:457: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'HUNDREDS\' generates 2 bits.\n                                                                  : ... In instance top.m3\n    case(HUNDREDS)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Error: Exiting due to 5 warning(s)\n'
module binary_to_BCD(data,seg1, seg2, seg3, sinal_out);
input [7:0] data;
wire [6:0]A;
output reg [6:0] seg1, seg2, seg3;
output reg sinal_out;
wire sinal;
wire [3:0] ONES, TENS;
wire [1:0] HUNDREDS;
wire [3:0] c1,c2,c3,c4,c5,c6,c7;
wire [3:0] d1,d2,d3,d4,d5,d6,d7;
complemento m0(data, A, sinal);
assign d1 = {2'b0,A[6:5]};
assign d2 = {c1[2:0],A[4]};
assign d3 = {c2[2:0],A[3]};
assign d4 = {c3[2:0],A[2]};
assign d5 = {c4[2:0],A[1]};
assign d6 = {1'b0,c1[3],c2[3],c3[3]};
assign d7 = {c6[2:0],c4[3]};
add3 m1(d1,c1);
add3 m2(d2,c2);
add3 m3(d3,c3);
add3 m4(d4,c4);
add3 m5(d5,c5);
add3 m6(d6,c6);
add3 m7(d7,c7);
assign ONES = {c5[2:0],A[0]};
assign TENS = {c7[2:0],c5[3]};
assign HUNDREDS = {c6[3],c7[3]};
always @ (*)
		 begin
		 sinal_out <= ~sinal;
		  case(ONES)
		   4'd0 : seg1 = 7'b1000000;
		   4'd1 : seg1 = 7'b1111001;
		   4'd2 : seg1 = 7'b0100100;
		   4'd3 : seg1 = 7'b0110000;
		   4'd4 : seg1 = 7'b0011001;
		   4'd5 : seg1 = 7'b0010010;
		   4'd6 : seg1 = 7'b0000010;
		   4'd7 : seg1 = 7'b1111000;
		   4'd8 : seg1 = 7'b0000000;
		   4'd9 : seg1 = 7'b0010000;
		   default : seg1 = 7'b0111111;
		  endcase
		 case(TENS)
		   4'd0 : seg2 = 7'b1000000;
		   4'd1 : seg2 = 7'b1111001;
		   4'd2 : seg2 = 7'b0100100;
		   4'd3 : seg2 = 7'b0110000;
		   4'd4 : seg2 = 7'b0011001;
		   4'd5 : seg2 = 7'b0010010;
		   4'd6 : seg2 = 7'b0000010;
		   4'd7 : seg2 = 7'b1111000;
		   4'd8 : seg2 = 7'b0000000;
		   4'd9 : seg2 = 7'b0010000;
		   default : seg2 = 7'b0111111;
		  endcase
		  case(HUNDREDS)
		   4'd0 : seg3 = 7'b1000000;
		   4'd1 : seg3 = 7'b1111001;
		   4'd2 : seg3 = 7'b0100100;
		   4'd3 : seg3 = 7'b0110000;
		   4'd4 : seg3 = 7'b0011001;
		   4'd5 : seg3 = 7'b0010010;
		   4'd6 : seg3 = 7'b0000010;
		   4'd7 : seg3 = 7'b1111000;
		   4'd8 : seg3 = 7'b0000000;
		   4'd9 : seg3 = 7'b0010000;
		   default : seg3 = 7'b0111111;
		  endcase
		end
endmodule
module binary_to_BCD(data,seg1, seg2, seg3, sinal_out);

input [7:0] data;
wire [6:0]A;
output reg [6:0] seg1, seg2, seg3;
output reg sinal_out;
wire sinal;
wire [3:0] ONES, TENS;
wire [1:0] HUNDREDS;
wire [3:0] c1,c2,c3,c4,c5,c6,c7;
wire [3:0] d1,d2,d3,d4,d5,d6,d7;
complemento m0(data, A, sinal);
assign d1 = {2'b0,A[6:5]};
assign d2 = {c1[2:0],A[4]};
assign d3 = {c2[2:0],A[3]};
assign d4 = {c3[2:0],A[2]};
assign d5 = {c4[2:0],A[1]};
assign d6 = {1'b0,c1[3],c2[3],c3[3]};
assign d7 = {c6[2:0],c4[3]};
add3 m1(d1,c1);
add3 m2(d2,c2);
add3 m3(d3,c3);
add3 m4(d4,c4);
add3 m5(d5,c5);
add3 m6(d6,c6);
add3 m7(d7,c7);
assign ONES = {c5[2:0],A[0]};
assign TENS = {c7[2:0],c5[3]};
assign HUNDREDS = {c6[3],c7[3]};
always @ (*)
		 begin
		 sinal_out <= ~sinal;
		  case(ONES)
		   4'd0 : seg1 = 7'b1000000;
		   4'd1 : seg1 = 7'b1111001;
		   4'd2 : seg1 = 7'b0100100;
		   4'd3 : seg1 = 7'b0110000;
		   4'd4 : seg1 = 7'b0011001;
		   4'd5 : seg1 = 7'b0010010;
		   4'd6 : seg1 = 7'b0000010;
		   4'd7 : seg1 = 7'b1111000;
		   4'd8 : seg1 = 7'b0000000;
		   4'd9 : seg1 = 7'b0010000;
		   default : seg1 = 7'b0111111;
		  endcase
		 case(TENS)
		   4'd0 : seg2 = 7'b1000000;
		   4'd1 : seg2 = 7'b1111001;
		   4'd2 : seg2 = 7'b0100100;
		   4'd3 : seg2 = 7'b0110000;
		   4'd4 : seg2 = 7'b0011001;
		   4'd5 : seg2 = 7'b0010010;
		   4'd6 : seg2 = 7'b0000010;
		   4'd7 : seg2 = 7'b1111000;
		   4'd8 : seg2 = 7'b0000000;
		   4'd9 : seg2 = 7'b0010000;
		   default : seg2 = 7'b0111111;
		  endcase
		  case(HUNDREDS)
		   4'd0 : seg3 = 7'b1000000;
		   4'd1 : seg3 = 7'b1111001;
		   4'd2 : seg3 = 7'b0100100;
		   4'd3 : seg3 = 7'b0110000;
		   4'd4 : seg3 = 7'b0011001;
		   4'd5 : seg3 = 7'b0010010;
		   4'd6 : seg3 = 7'b0000010;
		   4'd7 : seg3 = 7'b1111000;
		   4'd8 : seg3 = 7'b0000000;
		   4'd9 : seg3 = 7'b0010000;
		   default : seg3 = 7'b0111111;
		  endcase
		end
endmodule