data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new/CPU.v
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1: b"%Error: data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new/CPU.v:50: Cannot find file containing module: 'IFU'\n    IFU ifu0(clk,rst,alu_zero,ct_branch, ct_jump, inst);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new,data/full_repos/permissive/141745123/IFU\n             data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new,data/full_repos/permissive/141745123/IFU.v\n             data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new,data/full_repos/permissive/141745123/IFU.sv\n             IFU\n             IFU.v\n             IFU.sv\n             obj_dir/IFU\n             obj_dir/IFU.v\n             obj_dir/IFU.sv\n%Error: data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new/CPU.v:51: Cannot find file containing module: 'Control'\n    Control ct0(rst, inst[31:26], inst[5:0], ct_rf_dst, ct_rf_wen, ct_alu_src, ct_alu, ct_mem_wen, ct_mem_ren,ct_data_rf, ct_branch, ct_jump);\n    ^~~~~~~\n%Error: data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new/CPU.v:52: Cannot find file containing module: 'RegFile'\n    RegFile rf0(clk, ct_rf_wen, inst[25:21], inst[20:16], rf_addr_w, rf_data_w, rf_data_r1, rf_data_r2);\n    ^~~~~~~\n%Error: data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new/CPU.v:53: Cannot find file containing module: 'ALU'\n    ALU alu0(rst,ct_alu,rf_data_r1,alu_src2,alu_zero,alu_res);\n    ^~~\n%Error: data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new/CPU.v:54: Cannot find file containing module: 'DataMem'\n    DataMem datamem0(clk,ct_mem_wen, ct_mem_ren, alu_res, rf_data_r2, mem_data_o);\n    ^~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module CPU(
    input clk,rst
    );

    wire[31:0] inst;

    wire ct_rf_dst, ct_rf_wen, ct_alu_src, ct_data_rf, ct_branch, ct_jump, ct_mem_wen, ct_mem_ren;
    wire [3:0] ct_alu;

    wire[4:0] rf_addr_w;
    wire[31:0] rf_data_r1, rf_data_r2, rf_data_w;

    wire alu_zero;
    wire [31:0] alu_src2;
    wire [31:0] alu_res;

    wire [31:0] ext_data;

    wire [31:0] mem_data_o;

    assign rf_addr_w = ct_rf_dst?inst[15:11]:inst[20:16];

    assign rf_data_w = ct_data_rf?mem_data_o:alu_res;

    assign ext_data = {{16{inst[15]}},inst[15:0]};
    assign alu_src2 = ct_alu_src?ext_data:rf_data_r2;
    
    IFU ifu0(clk,rst,alu_zero,ct_branch, ct_jump, inst);
    Control ct0(rst, inst[31:26], inst[5:0], ct_rf_dst, ct_rf_wen, ct_alu_src, ct_alu, ct_mem_wen, ct_mem_ren,ct_data_rf, ct_branch, ct_jump);
    RegFile rf0(clk, ct_rf_wen, inst[25:21], inst[20:16], rf_addr_w, rf_data_w, rf_data_r1, rf_data_r2);
    ALU alu0(rst,ct_alu,rf_data_r1,alu_src2,alu_zero,alu_res);
    DataMem datamem0(clk,ct_mem_wen, ct_mem_ren, alu_res, rf_data_r2, mem_data_o);
endmodule
module CPU(
    input clk,rst
    );


    wire[31:0] inst;

    wire ct_rf_dst, ct_rf_wen, ct_alu_src, ct_data_rf, ct_branch, ct_jump, ct_mem_wen, ct_mem_ren;
    wire [3:0] ct_alu;

    wire[4:0] rf_addr_w;
    wire[31:0] rf_data_r1, rf_data_r2, rf_data_w;

    wire alu_zero;
    wire [31:0] alu_src2;
    wire [31:0] alu_res;

    wire [31:0] ext_data;

    wire [31:0] mem_data_o;

    assign rf_addr_w = ct_rf_dst?inst[15:11]:inst[20:16];

    assign rf_data_w = ct_data_rf?mem_data_o:alu_res;

    assign ext_data = {{16{inst[15]}},inst[15:0]};
    assign alu_src2 = ct_alu_src?ext_data:rf_data_r2;
    
    IFU ifu0(clk,rst,alu_zero,ct_branch, ct_jump, inst);
    Control ct0(rst, inst[31:26], inst[5:0], ct_rf_dst, ct_rf_wen, ct_alu_src, ct_alu, ct_mem_wen, ct_mem_ren,ct_data_rf, ct_branch, ct_jump);
    RegFile rf0(clk, ct_rf_wen, inst[25:21], inst[20:16], rf_addr_w, rf_data_w, rf_data_r1, rf_data_r2);
    ALU alu0(rst,ct_alu,rf_data_r1,alu_src2,alu_zero,alu_res);
    DataMem datamem0(clk,ct_mem_wen, ct_mem_ren, alu_res, rf_data_r2, mem_data_o);
endmodule