data/full_repos/permissive/152986713/ice40/tile_renderer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152986713/ice40/tile_renderer.v:69: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                             : ... In instance tile_renderer\n        ram_addr <= row_base + hpos[4:0];\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module tile_renderer(clk, reset, hpos, vpos,
                     rgb,
                     ram_addr, ram_read, ram_busy,
                     rom_addr, rom_data);

  input clk, reset;
  input [8:0] hpos;
  input [8:0] vpos;
  output [3:0] rgb;
  


  parameter HLOAD = 272;

  output reg [15:0] ram_addr;
  input [15:0] ram_read;
  output reg ram_busy;

  output [10:0] rom_addr;
  input [7:0] rom_data;
  
  reg [7:0] page_base = 8'h7e;
  reg [15:0] row_base;
  reg [4:0] row;

  wire [4:0] col = hpos[7:3];
  wire [2:0] yofs = vpos[2:0];
  wire [2:0] xofs = hpos[2:0];
  
  reg [15:0] cur_cell;
  wire [7:0] cur_char = cur_cell[7:0];
  wire [7:0] cur_attr = cur_cell[15:8];


  assign rom_addr = {cur_char, yofs};
  
  reg [15:0] row_buffer[0:31];
  

  always @(posedge clk) begin

    if (vpos == 248) begin
      row <= 0;
    end

    if (vpos[2:0] == 7) begin

      case (hpos)

        HLOAD-8: ram_busy <= 1;

        HLOAD-3: ram_addr <= {page_base, 3'b000, row};
        HLOAD-1: row_base <= ram_read;

        HLOAD+34: begin
          ram_busy <= 0;
          row <= row + 1;
        end
      endcase


      if (hpos >= HLOAD && hpos < HLOAD+34) begin
        ram_addr <= row_base + hpos[4:0];
        row_buffer[hpos[4:0] - 5'd2] <= ram_read;
      end
    end

    if (hpos < 256) begin
      case (hpos[2:0])
        7: begin
          cur_cell <= row_buffer[col+1];
        end
      endcase
    end else if (hpos == 308) begin
      cur_cell <= row_buffer[0];
    end
  end
      

  assign rgb = rom_data[~xofs] ? cur_attr[3:0] : cur_attr[7:4];
  
endmodule
module tile_renderer(clk, reset, hpos, vpos,
                     rgb,
                     ram_addr, ram_read, ram_busy,
                     rom_addr, rom_data);


  input clk, reset;
  input [8:0] hpos;
  input [8:0] vpos;
  output [3:0] rgb;
  


  parameter HLOAD = 272;

  output reg [15:0] ram_addr;
  input [15:0] ram_read;
  output reg ram_busy;

  output [10:0] rom_addr;
  input [7:0] rom_data;
  
  reg [7:0] page_base = 8'h7e;
  reg [15:0] row_base;
  reg [4:0] row;

  wire [4:0] col = hpos[7:3];
  wire [2:0] yofs = vpos[2:0];
  wire [2:0] xofs = hpos[2:0];
  
  reg [15:0] cur_cell;
  wire [7:0] cur_char = cur_cell[7:0];
  wire [7:0] cur_attr = cur_cell[15:8];


  assign rom_addr = {cur_char, yofs};
  
  reg [15:0] row_buffer[0:31];
  

  always @(posedge clk) begin

    if (vpos == 248) begin
      row <= 0;
    end

    if (vpos[2:0] == 7) begin

      case (hpos)

        HLOAD-8: ram_busy <= 1;

        HLOAD-3: ram_addr <= {page_base, 3'b000, row};
        HLOAD-1: row_base <= ram_read;

        HLOAD+34: begin
          ram_busy <= 0;
          row <= row + 1;
        end
      endcase


      if (hpos >= HLOAD && hpos < HLOAD+34) begin
        ram_addr <= row_base + hpos[4:0];
        row_buffer[hpos[4:0] - 5'd2] <= ram_read;
      end
    end

    if (hpos < 256) begin
      case (hpos[2:0])
        7: begin
          cur_cell <= row_buffer[col+1];
        end
      endcase
    end else if (hpos == 308) begin
      cur_cell <= row_buffer[0];
    end
  end
      

  assign rgb = rom_data[~xofs] ? cur_attr[3:0] : cur_attr[7:4];
  
endmodule