data/full_repos/permissive/173099254/lab5/nbcd.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173099254/lab5/nbcd.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10 Cin=1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab5/nbcd.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 A=14;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab5/nbcd.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #10 A=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab5/nbcd.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #10 B=3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab5/nbcd.v:119: Unsupported: Ignoring delay on this delayed statement.\n   #10 N=i;\n   ^\n%Warning-MULTITOP: data/full_repos/permissive/173099254/lab5/nbcd.v:60: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                      : ... Top module \'test_sum4\'\nmodule test_sum4();\n       ^~~~~~~~~\n                                                                      : ... Top module \'comparator4_test\'\nmodule comparator4_test();\n       ^~~~~~~~~~~~~~~~\n                                                                      : ... Top module \'NBCD_exces_3_test\'\nmodule NBCD_exces_3_test();\n       ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab5/nbcd.v:13: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'Cin\' generates 1 bits.\n                                                                   : ... In instance NBCD_exces_3_test.NBCD_exces_3_instance.sumator\n    S=A+B+Cin;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab5/nbcd.v:18: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'Cin\' generates 1 bits.\n                                                                   : ... In instance NBCD_exces_3_test.NBCD_exces_3_instance.sumator\n   S=A+B+Cin;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab5/nbcd.v:10: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'Cin\' generates 1 bits.\n                                                                   : ... In instance NBCD_exces_3_test.NBCD_exces_3_instance.sumator\n  if(A+B+Cin <=15)\n        ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab5/nbcd.v:119: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                    : ... In instance NBCD_exces_3_test\n   #10 N=i;\n        ^\n%Error: Exiting due to 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module NBCD_exces_3(N, VCC, GND, Cout, Y, egal, mare);
input [3:0] N;
input VCC;
input GND;
output Cout;
output [3:0] Y;
output egal;
output mare;

wire [3:0] S;
wire mic;

comparator4 comparator(N, {VCC,GND,VCC,GND}, mic, egal, mare);
sum4 sumator(N, {GND, GND,VCC,VCC}, GND, S, Cout);

and p1(Y[0], S[0], mic);
and p2(Y[1], S[1], mic);
and p3(Y[2], S[2], mic);
and p4(Y[3], S[3], mic);

endmodule
module NBCD_exces_3(N, VCC, GND, Cout, Y, egal, mare);

input [3:0] N;
input VCC;
input GND;
output Cout;
output [3:0] Y;
output egal;
output mare;

wire [3:0] S;
wire mic;

comparator4 comparator(N, {VCC,GND,VCC,GND}, mic, egal, mare);
sum4 sumator(N, {GND, GND,VCC,VCC}, GND, S, Cout);

and p1(Y[0], S[0], mic);
and p2(Y[1], S[1], mic);
and p3(Y[2], S[2], mic);
and p4(Y[3], S[3], mic);

endmodule