data/full_repos/permissive/15431697/src/rx_engine.v
 line:107: before: "end"
1: b"%Error: data/full_repos/permissive/15431697/src/rx_engine.v:11: syntax error, unexpected input\n    input wire                      rx_reset,\n    ^~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                      rx_enable,\n    ^~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                      rx_clk,\n    ^~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                      rx_valid,\n    ^~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire  [axi_width - 1:0]   rx_data,\n    ^~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire  [keep_width - 1:0]  rx_keep,\n    ^~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                      rx_last,\n    ^~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                     rx_ready,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                      tx_header_fifo_ready,\n    ^~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                     tx_header_fifo_valid,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                     tx_header_fifo_last,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [keep_width - 1:0]  tx_header_fifo_keep,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:29: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [axi_width - 1:0]   tx_header_fifo_data,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                       ocp_ready,\n    ^~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:34: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`addr_wdth - 1:0]   address,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:34: Define or directive not defined: '`addr_wdth'\n    output wire [`addr_wdth - 1:0]   address,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                      enable,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:36: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [2:0]                burst_seq,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:37: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                      burst_single_req,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:38: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [9:0]                burst_length,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:39: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                      data_valid,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:40: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                      read_request,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:41: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [axi_width - 1:0]    write_data,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:42: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                      write_request,\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:43: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                      writeresp_enable\n    ^~~~~~\n%Error: data/full_repos/permissive/15431697/src/rx_engine.v:88: syntax error, unexpected assign\n    assign rx_vld_en = rx_valid & rx_enable;         \n    ^~~~~~\n%Error: Exiting due to 26 error(s)\n"
module rx_engine(


    input wire                      rx_reset,
    input wire                      rx_enable,



    input wire                      rx_clk,
    input wire                      rx_valid,
    input wire  [axi_width - 1:0]   rx_data,
    input wire  [keep_width - 1:0]  rx_keep,
    input wire                      rx_last,
    output wire                     rx_ready,



    input wire                      tx_header_fifo_ready,
    output wire                     tx_header_fifo_valid,
    output wire                     tx_header_fifo_last,
    output wire [keep_width - 1:0]  tx_header_fifo_keep,
    output wire [axi_width - 1:0]   tx_header_fifo_data,



    input wire                       ocp_ready,
    output wire [`addr_wdth - 1:0]   address,
    output wire                      enable,
    output wire [2:0]                burst_seq,
    output wire                      burst_single_req,
    output wire [9:0]                burst_length,
    output wire                      data_valid,
    output wire                      read_request,
    output wire [axi_width - 1:0]    write_data,
    output wire                      write_request,
    output wire                      writeresp_enable


    );



    

    parameter axi_width     = 64;
    parameter ocp_addr_size = 32;
    parameter keep_width    = 8;



    localparam IDLE     = 3'b000;
    localparam H1       = 3'b001;
    localparam H2       = 3'b010;
    localparam DATA3    = 3'b011;
    localparam DATA4    = 3'b100;



    localparam INCR  = 3'b000;
    localparam DFLT1 = 3'b001;
    localparam WRAP  = 3'b010;
    localparam DFLT2 = 3'b011;
    localparam XOR   = 3'b100;
    localparam STRM  = 3'b101;
    localparam UNKN  = 3'b110;
    localparam BLCK  = 3'b111;



    wire [2:0] ocp_reg_ctl;
    reg [axi_width - 1:0]   header1;
    reg [axi_width - 1:0]   header2;
    reg [96 - 1:0]          data_shift_register;


    wire [1:0] optype;
    wire rx_vld_en;



    assign rx_vld_en = rx_valid & rx_enable;

    

    rx_fsm rx_control(rx_reset, rx_clk, rx_vld_en, rx_keep, rx_last,
                      rx_ready, tx_header_fifo_ready, tx_header_fifo_valid,
                      ocp_ready, optype, ocp_reg_ctl, read_request, write_request);



    initial begin
        address             <=  {header2 [ocp_addr_size - 1:2], 2'b00};
        enable              <=  1'b1;
        burst_seq           <=  
        burst_single_req    <=  
        burst_length        <= header1 [9:0]; 
        data_valid          <=  
        write_data          <= data_shft_register [64 - 1:0]; 
        writeresp_enable    <=  
    end




    always @(posedge rx_clk) begin
        case (ocp_reg_ctl)
            IDLE:   begin end
            
            H1:     begin
                if (rx_ready) begin
                    header1                     <= rx_data; end
                else begin
                    header1                     <= header1; end
            end

            H2:     begin
                if (rx_ready) begin
                    header2                     <= rx_data;
                    data_shift_register [95:64] <= rx_data [63:32];
                end
                else begin
                    header2                     <= header2;
                    data_shift_register [95:64] <= data_shift_register[95:64]
                end   
            end   

            DATA3:  begin
                if (rx_ready) begin
                    data_shift_register [31:0]  <= data_shift_register [95:64];
                    data_shift_register [95:32] <= rx_data;
                end
                else begin
                    data_shift_register [31:0]  <= data_shift_register [31:0];
                    data_shift_register [95:32] <= data_shift_register [95:32];
                end

            end

            DATA4:  begin
                if (rx_ready) begin
                    data_shift_register [63:0]  <= rx_data; end
                else begin
                    data_shift_register [63:0]  <= data_shift_register [63:0]; end
            end
        endcase
    end

endmodule
module rx_engine(


    input wire                      rx_reset,
    input wire                      rx_enable,



    input wire                      rx_clk,
    input wire                      rx_valid,
    input wire  [axi_width - 1:0]   rx_data,
    input wire  [keep_width - 1:0]  rx_keep,
    input wire                      rx_last,
    output wire                     rx_ready,



    input wire                      tx_header_fifo_ready,
    output wire                     tx_header_fifo_valid,
    output wire                     tx_header_fifo_last,
    output wire [keep_width - 1:0]  tx_header_fifo_keep,
    output wire [axi_width - 1:0]   tx_header_fifo_data,



    input wire                       ocp_ready,
    output wire [`addr_wdth - 1:0]   address,
    output wire                      enable,
    output wire [2:0]                burst_seq,
    output wire                      burst_single_req,
    output wire [9:0]                burst_length,
    output wire                      data_valid,
    output wire                      read_request,
    output wire [axi_width - 1:0]    write_data,
    output wire                      write_request,
    output wire                      writeresp_enable


    );




    

    parameter axi_width     = 64;
    parameter ocp_addr_size = 32;
    parameter keep_width    = 8;



    localparam IDLE     = 3'b000;
    localparam H1       = 3'b001;
    localparam H2       = 3'b010;
    localparam DATA3    = 3'b011;
    localparam DATA4    = 3'b100;



    localparam INCR  = 3'b000;
    localparam DFLT1 = 3'b001;
    localparam WRAP  = 3'b010;
    localparam DFLT2 = 3'b011;
    localparam XOR   = 3'b100;
    localparam STRM  = 3'b101;
    localparam UNKN  = 3'b110;
    localparam BLCK  = 3'b111;



    wire [2:0] ocp_reg_ctl;
    reg [axi_width - 1:0]   header1;
    reg [axi_width - 1:0]   header2;
    reg [96 - 1:0]          data_shift_register;


    wire [1:0] optype;
    wire rx_vld_en;



    assign rx_vld_en = rx_valid & rx_enable;

    

    rx_fsm rx_control(rx_reset, rx_clk, rx_vld_en, rx_keep, rx_last,
                      rx_ready, tx_header_fifo_ready, tx_header_fifo_valid,
                      ocp_ready, optype, ocp_reg_ctl, read_request, write_request);



    initial begin
        address             <=  {header2 [ocp_addr_size - 1:2], 2'b00};
        enable              <=  1'b1;
        burst_seq           <=  
        burst_single_req    <=  
        burst_length        <= header1 [9:0]; 
        data_valid          <=  
        write_data          <= data_shft_register [64 - 1:0]; 
        writeresp_enable    <=  
    end




    always @(posedge rx_clk) begin
        case (ocp_reg_ctl)
            IDLE:   begin end
            
            H1:     begin
                if (rx_ready) begin
                    header1                     <= rx_data; end
                else begin
                    header1                     <= header1; end
            end

            H2:     begin
                if (rx_ready) begin
                    header2                     <= rx_data;
                    data_shift_register [95:64] <= rx_data [63:32];
                end
                else begin
                    header2                     <= header2;
                    data_shift_register [95:64] <= data_shift_register[95:64]
                end   
            end   

            DATA3:  begin
                if (rx_ready) begin
                    data_shift_register [31:0]  <= data_shift_register [95:64];
                    data_shift_register [95:32] <= rx_data;
                end
                else begin
                    data_shift_register [31:0]  <= data_shift_register [31:0];
                    data_shift_register [95:32] <= data_shift_register [95:32];
                end

            end

            DATA4:  begin
                if (rx_ready) begin
                    data_shift_register [63:0]  <= rx_data; end
                else begin
                    data_shift_register [63:0]  <= data_shift_register [63:0]; end
            end
        endcase
    end

endmodule