data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:127: Operator VAR \'ADDR_MASK\' expects 32 bits on the Initial value, but Initial value\'s NOT generates 64 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n    localparam  [AXI4_ADDR_WIDTH-1:0]   ADDR_MASK = ~((64\'d1 << AXI4_DATA_SIZE) - 1);\n                                        ^~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:198: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n            reg_param_stride <= INIT_PARAM_STRIDE & ADDR_MASK;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:210: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_ctl_control\' generates 3 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_CTL_CONTROL:  reg_ctl_control  <= reg_mask(reg_ctl_control,  s_wb_dat_i, s_wb_sel_i);\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:210: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_CTL_CONTROL:  reg_ctl_control  <= reg_mask(reg_ctl_control,  s_wb_dat_i, s_wb_sel_i);\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:212: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_stride\' generates 14 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_PARAM_STRIDE: reg_param_stride <= reg_mask(reg_param_stride, s_wb_dat_i, s_wb_sel_i) & ADDR_MASK;\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:212: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_PARAM_STRIDE: reg_param_stride <= reg_mask(reg_param_stride, s_wb_dat_i, s_wb_sel_i) & ADDR_MASK;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:213: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_width\' generates 10 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_PARAM_WIDTH:  reg_param_width  <= reg_mask(reg_param_width,  s_wb_dat_i, s_wb_sel_i);\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:213: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_PARAM_WIDTH:  reg_param_width  <= reg_mask(reg_param_width,  s_wb_dat_i, s_wb_sel_i);\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:214: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_height\' generates 10 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_PARAM_HEIGHT: reg_param_height <= reg_mask(reg_param_height, s_wb_dat_i, s_wb_sel_i);\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:214: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_PARAM_HEIGHT: reg_param_height <= reg_mask(reg_param_height, s_wb_dat_i, s_wb_sel_i);\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:215: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_size\' generates 20 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_PARAM_SIZE:   reg_param_size   <= reg_mask(reg_param_size,   s_wb_dat_i, s_wb_sel_i);\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:215: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_PARAM_SIZE:   reg_param_size   <= reg_mask(reg_param_size,   s_wb_dat_i, s_wb_sel_i);\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:216: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_awlen\' generates 8 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_PARAM_AWLEN:  reg_param_awlen  <= reg_mask(reg_param_awlen,  s_wb_dat_i, s_wb_sel_i);\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:216: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                ADR_PARAM_AWLEN:  reg_param_awlen  <= reg_mask(reg_param_awlen,  s_wb_dat_i, s_wb_sel_i);\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:245: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_control\' generates 3 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_CTL_CONTROL)    ? reg_ctl_control    :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:246: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_ctl_status\' generates 1 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_CTL_STATUS)     ? sig_ctl_status     :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:247: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_ctl_index\' generates 8 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_CTL_INDEX)      ? sig_ctl_index      :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:249: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_stride\' generates 14 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_PARAM_STRIDE)   ? reg_param_stride   :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:250: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_width\' generates 10 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_PARAM_WIDTH)    ? reg_param_width    :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:251: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_height\' generates 10 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_PARAM_HEIGHT)   ? reg_param_height   :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:252: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_size\' generates 20 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_PARAM_SIZE)     ? reg_param_size     :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:253: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_awlen\' generates 8 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_PARAM_AWLEN)    ? reg_param_awlen    :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:255: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_monitor_stride\' generates 14 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_MONITOR_STRIDE) ? sig_monitor_stride :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:256: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_monitor_width\' generates 10 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_MONITOR_WIDTH)  ? sig_monitor_width  :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:257: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_monitor_height\' generates 10 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_MONITOR_HEIGHT) ? sig_monitor_height :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:258: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_monitor_size\' generates 20 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_MONITOR_SIZE)   ? sig_monitor_size   :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:259: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_monitor_awlen\' generates 8 bits.\n                                                                                           : ... In instance jelly_vdma_axi4s_to_axi4\n                        (s_wb_adr_i == ADR_MONITOR_AWLEN)  ? sig_monitor_awlen  :\n                                                           ^\n%Error: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4.v:302: Cannot find file containing module: \'jelly_vdma_axi4s_to_axi4_core\'\n    jelly_vdma_axi4s_to_axi4_core\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/video,data/full_repos/permissive/2084115/jelly_vdma_axi4s_to_axi4_core\n             data/full_repos/permissive/2084115/rtl/video,data/full_repos/permissive/2084115/jelly_vdma_axi4s_to_axi4_core.v\n             data/full_repos/permissive/2084115/rtl/video,data/full_repos/permissive/2084115/jelly_vdma_axi4s_to_axi4_core.sv\n             jelly_vdma_axi4s_to_axi4_core\n             jelly_vdma_axi4s_to_axi4_core.v\n             jelly_vdma_axi4s_to_axi4_core.sv\n             obj_dir/jelly_vdma_axi4s_to_axi4_core\n             obj_dir/jelly_vdma_axi4s_to_axi4_core.v\n             obj_dir/jelly_vdma_axi4s_to_axi4_core.sv\n%Error: Exiting due to 1 error(s), 27 warning(s)\n'
function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );
    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction
function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );

    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction