data/full_repos/permissive/152986713/ice40/cpu8.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:139: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'write'\n                                                                         : ... In instance CPU\n      write <= 0;\n      ^~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:145: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'write'\n                                                                         : ... In instance CPU\n          write <= 0;\n          ^~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:150: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'address'\n                                                                         : ... In instance CPU\n          address <= IP;\n          ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:152: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'write'\n                                                                         : ... In instance CPU\n          write <= 0;\n          ^~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:165: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'address'\n                                                                         : ... In instance CPU\n       address <= IP;\n       ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:171: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'address'\n                                                                         : ... In instance CPU\n              address <= B;\n              ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:176: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'address'\n                                                                         : ... In instance CPU\n              address <= {4'b0, data_in[3:0]};\n              ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:177: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_out'\n                                                                         : ... In instance CPU\n              data_out <= A;\n              ^~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:178: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'write'\n                                                                         : ... In instance CPU\n              write <= 1;\n              ^~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:193: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'address'\n                                                                         : ... In instance CPU\n                address <= IP;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:36: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h0:  Y = 0;\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:37: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h1: Y = {1'b0, A};\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:38: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h2:  Y = A + 1;\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:39: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h3:  Y = A - 1;\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:41: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h4:  Y = {A, 1'b0};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:42: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h5:  Y = {A[0], 1'b0, A[N-1:1]};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:43: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h6:  Y = {A, carry};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:44: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h7:  Y = {A[0], carry, A[N-1:1]};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:46: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h8:  Y = {1'b0, A | B};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:47: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h9:  Y = {1'b0, A & B};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:48: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'ha:  Y = {1'b0, A ^ B};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:49: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'hb: Y = {1'b0, B};\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:51: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'hc:  Y = A + B;\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:52: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'hd:  Y = A - B;\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:53: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'he:  Y = A + B + (carry?1:0);\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:54: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'hf:  Y = A - B - (carry?1:0);\n             ^\n%Error: Exiting due to 26 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module CPU(clk, reset, address, data_in, data_out, write);

  input        clk;
  input        reset;
  output [7:0] address;
  input  [7:0] data_in;
  output [7:0] data_out;
  output       write;
  
  reg [7:0] IP;
  reg [7:0] A, B;
  reg [8:0] Y;
  reg [2:0] state;
  
  reg carry;
  reg zero;
  wire [1:0] flags = { zero, carry };

  reg [7:0] opcode;
  wire [3:0] aluop = opcode[3:0];
  wire [1:0] opdest = opcode[5:4];
  wire B_or_data = opcode[6];

  localparam S_RESET = 0;
  localparam S_SELECT = 1;
  localparam S_DECODE = 2;
  localparam S_COMPUTE = 3;
  localparam S_READ_IP = 4;

  ALU alu(
    .A(A), 
    .B(B_or_data ? data_in : B), 
    .Y(Y), 
    .aluop(aluop), 
    .carry(carry));
  
  always @(posedge clk)
    if (reset) begin
      state <= 0;
      write <= 0;
    end else begin
      case (state)

        S_RESET: begin
          IP <= 8'h80;
          write <= 0;
          state <= S_SELECT;
        end

        S_SELECT: begin
          address <= IP;
          IP <= IP + 1;
          write <= 0;
          state <= S_DECODE;
        end

        S_DECODE: begin
          opcode <= data_in;
          casez (data_in)

            8'b00??????: begin
              state <= S_COMPUTE;
            end

            8'b01??????: begin
	      address <= IP;
       	      IP <= IP + 1;
              state <= S_COMPUTE;
            end

            8'b11??????: begin
              address <= B;
              state <= S_COMPUTE;
            end

            8'b1001????: begin
              address <= {4'b0, data_in[3:0]};
              data_out <= A;
              write <= 1;
              state <= S_SELECT;
            end

            8'b10000001: begin
              A <= B;
              B <= A;
              state <= S_SELECT;
            end

            8'b1010????: begin
              if (
                (data_in[0] && (data_in[1] == carry)) ||
                (data_in[2] && (data_in[3] == zero))) 
              begin
                address <= IP;
                state <= S_READ_IP;
              end else begin
                state <= S_SELECT;
              end
              IP <= IP + 1;
            end

            default: begin
              state <= S_RESET;
            end
          endcase
        end

        S_COMPUTE: begin

          case (opdest)
            `DEST_A: A <= Y[7:0];
            `DEST_B: B <= Y[7:0];
            `DEST_IP: IP <= Y[7:0];
            `DEST_NOP: ;
          endcase

          if (aluop[2]) carry <= Y[8];

          zero <= ~|Y[7:0];

          state <= S_SELECT;
        end

        S_READ_IP: begin
          IP <= data_in;
          state <= S_SELECT;
        end
      endcase
    end

endmodule
module CPU(clk, reset, address, data_in, data_out, write);


  input        clk;
  input        reset;
  output [7:0] address;
  input  [7:0] data_in;
  output [7:0] data_out;
  output       write;
  
  reg [7:0] IP;
  reg [7:0] A, B;
  reg [8:0] Y;
  reg [2:0] state;
  
  reg carry;
  reg zero;
  wire [1:0] flags = { zero, carry };

  reg [7:0] opcode;
  wire [3:0] aluop = opcode[3:0];
  wire [1:0] opdest = opcode[5:4];
  wire B_or_data = opcode[6];

  localparam S_RESET = 0;
  localparam S_SELECT = 1;
  localparam S_DECODE = 2;
  localparam S_COMPUTE = 3;
  localparam S_READ_IP = 4;

  ALU alu(
    .A(A), 
    .B(B_or_data ? data_in : B), 
    .Y(Y), 
    .aluop(aluop), 
    .carry(carry));
  
  always @(posedge clk)
    if (reset) begin
      state <= 0;
      write <= 0;
    end else begin
      case (state)

        S_RESET: begin
          IP <= 8'h80;
          write <= 0;
          state <= S_SELECT;
        end

        S_SELECT: begin
          address <= IP;
          IP <= IP + 1;
          write <= 0;
          state <= S_DECODE;
        end

        S_DECODE: begin
          opcode <= data_in;
          casez (data_in)

            8'b00??????: begin
              state <= S_COMPUTE;
            end

            8'b01??????: begin
	      address <= IP;
       	      IP <= IP + 1;
              state <= S_COMPUTE;
            end

            8'b11??????: begin
              address <= B;
              state <= S_COMPUTE;
            end

            8'b1001????: begin
              address <= {4'b0, data_in[3:0]};
              data_out <= A;
              write <= 1;
              state <= S_SELECT;
            end

            8'b10000001: begin
              A <= B;
              B <= A;
              state <= S_SELECT;
            end

            8'b1010????: begin
              if (
                (data_in[0] && (data_in[1] == carry)) ||
                (data_in[2] && (data_in[3] == zero))) 
              begin
                address <= IP;
                state <= S_READ_IP;
              end else begin
                state <= S_SELECT;
              end
              IP <= IP + 1;
            end

            default: begin
              state <= S_RESET;
            end
          endcase
        end

        S_COMPUTE: begin

          case (opdest)
            `DEST_A: A <= Y[7:0];
            `DEST_B: B <= Y[7:0];
            `DEST_IP: IP <= Y[7:0];
            `DEST_NOP: ;
          endcase

          if (aluop[2]) carry <= Y[8];

          zero <= ~|Y[7:0];

          state <= S_SELECT;
        end

        S_READ_IP: begin
          IP <= data_in;
          state <= S_SELECT;
        end
      endcase
    end

endmodule