data/full_repos/permissive/156417892/hdl/InstructionFetch/InsFetch_test.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsFetch_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsFetch_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsFetch_test.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #200;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsFetch_test.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsFetch_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #250;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsFetch_test.v:60: Unsupported: Ignoring delay on this delayed statement.\n #25 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsFetch_test.v:65: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("./main_test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsFetch_test.v:66: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;


   reg iSIG_PCSrc;
   reg [127:0] imem_in;
   reg [31:0] iaddr4branch;
   reg icacheHit;


   wire [31:0] oins, obranch_adder;
   wire ocacheHit;

   reg clk, rstn = 1;
   integer    i;


InsFetch uut(
               iSIG_PCSrc,
               imem_in,
               iaddr4branch,
               icacheHit,
               obranch_adder,
               oins,
               ocacheHit,
               clk,
               rstn);

   initial begin

      #10;
      rstn = 0;
      #10;
      icacheHit = 1 & ocacheHit;
      iSIG_PCSrc = 1;
      iaddr4branch = 32'h00000100;
      imem_in = {32'hDEADBEEF ,32'hABABABAB,
                 32'hCDCDCDCD, 32'hEFEFEFEF};

      #200;
      iaddr4branch = 32'h00000000;

      #50;
      icacheHit = 1 & ocacheHit;
      iSIG_PCSrc = 0;

      imem_in = {32'hDEADBEEF ,32'hABABABAB,
                 32'hCDCDCDCD, 32'hEFEFEFEF};
      #250;
      icacheHit = 0;
      iSIG_PCSrc = 1;
      iaddr4branch = 32'h00000000;
      imem_in = {32'hDEADBEEF, 32'h12345678, 32'hAAAAAAAA, 32'hBADA881E};
   end

   initial begin
      clk = 0;
      for (i = 0; i < 30; i = i + 1)
	#25 clk = ~clk;
   end


   initial begin
      $dumpfile("./main_test.vcd");
      $dumpvars;
   end

endmodule
module main_test;



   reg iSIG_PCSrc;
   reg [127:0] imem_in;
   reg [31:0] iaddr4branch;
   reg icacheHit;


   wire [31:0] oins, obranch_adder;
   wire ocacheHit;

   reg clk, rstn = 1;
   integer    i;


InsFetch uut(
               iSIG_PCSrc,
               imem_in,
               iaddr4branch,
               icacheHit,
               obranch_adder,
               oins,
               ocacheHit,
               clk,
               rstn);

   initial begin

      #10;
      rstn = 0;
      #10;
      icacheHit = 1 & ocacheHit;
      iSIG_PCSrc = 1;
      iaddr4branch = 32'h00000100;
      imem_in = {32'hDEADBEEF ,32'hABABABAB,
                 32'hCDCDCDCD, 32'hEFEFEFEF};

      #200;
      iaddr4branch = 32'h00000000;

      #50;
      icacheHit = 1 & ocacheHit;
      iSIG_PCSrc = 0;

      imem_in = {32'hDEADBEEF ,32'hABABABAB,
                 32'hCDCDCDCD, 32'hEFEFEFEF};
      #250;
      icacheHit = 0;
      iSIG_PCSrc = 1;
      iaddr4branch = 32'h00000000;
      imem_in = {32'hDEADBEEF, 32'h12345678, 32'hAAAAAAAA, 32'hBADA881E};
   end

   initial begin
      clk = 0;
      for (i = 0; i < 30; i = i + 1)
	#25 clk = ~clk;
   end


   initial begin
      $dumpfile("./main_test.vcd");
      $dumpvars;
   end

endmodule