data/full_repos/permissive/166558975/rtl/svga/CHAR_GEN.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/166558975/rtl/svga/CHAR_GEN.v:30: Cannot find file containing module: 'CHAR_GEN_ROM'\nCHAR_GEN_ROM CHAR_GEN_ROM\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166558975/rtl/svga,data/full_repos/permissive/166558975/CHAR_GEN_ROM\n             data/full_repos/permissive/166558975/rtl/svga,data/full_repos/permissive/166558975/CHAR_GEN_ROM.v\n             data/full_repos/permissive/166558975/rtl/svga,data/full_repos/permissive/166558975/CHAR_GEN_ROM.sv\n             CHAR_GEN_ROM\n             CHAR_GEN_ROM.v\n             CHAR_GEN_ROM.sv\n             obj_dir/CHAR_GEN_ROM\n             obj_dir/CHAR_GEN_ROM.v\n             obj_dir/CHAR_GEN_ROM.sv\n%Error: Exiting due to 1 error(s)\n"
module CHAR_GEN(

	reset,

	char_code,
	subchar_line,
	subchar_pixel,

	pixel_clock,
	pixel_on
);

input			pixel_clock;
input			reset;

input	[7:0]	char_code;
input	[4:0]	subchar_line;
input	[3:0]	subchar_pixel;

output			pixel_on;

reg		[7:0]	latched_data;
reg				pixel_on;

wire	[11:0]	rom_addr = {char_code[7:0], subchar_line[4:1]};
wire	[7:0]	rom_data;
 


CHAR_GEN_ROM CHAR_GEN_ROM
(
	pixel_clock,
	rom_addr,
	rom_data
);


always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin
			pixel_on = 1'b0;
			latched_data  = 8'h00;
		end

	else begin
		case(subchar_pixel)
			4'b0101:
				latched_data [7:0] = {rom_data[0],rom_data[1],rom_data[2],rom_data[3],rom_data[4],rom_data[5],rom_data[6],rom_data[7]};
			default:
			if(subchar_pixel[0]==1'b0)
				{pixel_on,latched_data [7:1]} <= latched_data [7:0];
		endcase
		end

	end

endmodule
module CHAR_GEN(

	reset,

	char_code,
	subchar_line,
	subchar_pixel,

	pixel_clock,
	pixel_on
);


input			pixel_clock;
input			reset;

input	[7:0]	char_code;
input	[4:0]	subchar_line;
input	[3:0]	subchar_pixel;

output			pixel_on;

reg		[7:0]	latched_data;
reg				pixel_on;

wire	[11:0]	rom_addr = {char_code[7:0], subchar_line[4:1]};
wire	[7:0]	rom_data;
 


CHAR_GEN_ROM CHAR_GEN_ROM
(
	pixel_clock,
	rom_addr,
	rom_data
);


always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin
			pixel_on = 1'b0;
			latched_data  = 8'h00;
		end

	else begin
		case(subchar_pixel)
			4'b0101:
				latched_data [7:0] = {rom_data[0],rom_data[1],rom_data[2],rom_data[3],rom_data[4],rom_data[5],rom_data[6],rom_data[7]};
			default:
			if(subchar_pixel[0]==1'b0)
				{pixel_on,latched_data [7:1]} <= latched_data [7:0];
		endcase
		end

	end

endmodule