data/full_repos/permissive/136009613/state_machineTB.v
1: b'%Error: data/full_repos/permissive/136009613/state_machineTB.v:3: syntax error, unexpected \'=\', expecting IDENTIFIER\n parameter byte = 8;\n                ^\n%Error: data/full_repos/permissive/136009613/state_machineTB.v:4: syntax error, unexpected \';\', expecting "\'{"\n parameter width_in = 1 * byte;\n                              ^\n%Error: data/full_repos/permissive/136009613/state_machineTB.v:5: syntax error, unexpected \';\', expecting "\'{"\n parameter width_out = 1 * byte;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/state_machineTB.v:28: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136009613/state_machineTB.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 1; ready_from_decoder = 1; data_from_rom = 8\'b00000011;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/state_machineTB.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #30 data_from_rom = 8\'b00000100;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/state_machineTB.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #30 ready_from_decoder = 0; data_from_rom = 8\'b01101111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/state_machineTB.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #30 ready_from_decoder = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/state_machineTB.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #30 data_from_rom = 8\'b10010001;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/state_machineTB.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #30 data_from_rom = 8\'b01010000;  \n  ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n'
module state_machineTB;

	parameter byte = 8;
	parameter width_in = 1 * byte;
	parameter width_out = 1 * byte;
	parameter memory_size = 8;

	reg clk;
	reg reset;
	reg ready_from_decoder;
	wire start_for_decoder;
	reg [width_in - 1:0] data_from_rom;
	wire [width_out - 1:0] data_for_decoder;
	
	wire [memory_size - 1:0] rom_address;
	
	state_machine TB(
		.clk(clk), 
		.reset(reset), 
		.ready_from_decoder(ready_from_decoder), 
		.start_for_decoder(start_for_decoder), 
		.data_from_rom(data_from_rom), 
		.data_for_decoder(data_for_decoder),
		.rom_address(rom_address)
	);
	
	initial clk = 0;
	always #5 clk = !clk;
	
	initial reset = 0;
	
	initial
	begin
	
		#10 reset = 1; ready_from_decoder = 1; data_from_rom = 8'b00000011;
		
		#30 data_from_rom = 8'b00000100;
		
		#30 ready_from_decoder = 0; data_from_rom = 8'b01101111;
		
		#30 ready_from_decoder = 1;
		
		#30 data_from_rom = 8'b10010001;
				
		#30 data_from_rom = 8'b01010000;
		
	end
	
endmodule
module state_machineTB;


	parameter byte = 8;
	parameter width_in = 1 * byte;
	parameter width_out = 1 * byte;
	parameter memory_size = 8;

	reg clk;
	reg reset;
	reg ready_from_decoder;
	wire start_for_decoder;
	reg [width_in - 1:0] data_from_rom;
	wire [width_out - 1:0] data_for_decoder;
	
	wire [memory_size - 1:0] rom_address;
	
	state_machine TB(
		.clk(clk), 
		.reset(reset), 
		.ready_from_decoder(ready_from_decoder), 
		.start_for_decoder(start_for_decoder), 
		.data_from_rom(data_from_rom), 
		.data_for_decoder(data_for_decoder),
		.rom_address(rom_address)
	);
	
	initial clk = 0;
	always #5 clk = !clk;
	
	initial reset = 0;
	
	initial
	begin
	
		#10 reset = 1; ready_from_decoder = 1; data_from_rom = 8'b00000011;
		
		#30 data_from_rom = 8'b00000100;
		
		#30 ready_from_decoder = 0; data_from_rom = 8'b01101111;
		
		#30 ready_from_decoder = 1;
		
		#30 data_from_rom = 8'b10010001;
				
		#30 data_from_rom = 8'b01010000;
		
	end
	
endmodule