data/full_repos/permissive/192147978/mux_2_1.v
data/verilator_xmls/1b153af4-700f-4818-82f7-607954422e82.xml
module mux_2_1( select_in, datain1, datain2, data_out   );


parameter WORD_SIZE = 32 ; 




input  wire select_in ;  
input  wire [WORD_SIZE-1:0] datain1 ; 
input  wire [WORD_SIZE-1:0] datain2 ; 
output wire [WORD_SIZE-1:0] data_out ;

assign data_out = (select_in) ? datain2 : datain1;

endmodule
module mux_2_1( select_in, datain1, datain2, data_out   );



parameter WORD_SIZE = 32 ; 




input  wire select_in ;  
input  wire [WORD_SIZE-1:0] datain1 ; 
input  wire [WORD_SIZE-1:0] datain2 ; 
output wire [WORD_SIZE-1:0] data_out ;

assign data_out = (select_in) ? datain2 : datain1;

endmodule