data/full_repos/permissive/196705942/src/adder24in36out.v
data/verilator_xmls/d03847cb-41e0-45c7-b248-085b120da097.xml
module ADDER24IN36OUT(input [23:0]X, input [23:0]Y, output [35:0]W);
wire [35:0]XM = { 12'b0,X };
wire [35:0]YM = { Y,12'b0};
assign W = XM + YM;
endmodule
module ADDER24IN36OUT(input [23:0]X, input [23:0]Y, output [35:0]W);

wire [35:0]XM = { 12'b0,X };
wire [35:0]YM = { Y,12'b0};
assign W = XM + YM;
endmodule