data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sources_1/new/MultithreadedInstructionUnit.v
1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n        ... Looked in:\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new/MultithreadedInstructionUnit.v\n%Error: Exiting due to 3 error(s)\n'
module MultithreadInstructionUnit(
    input wire clk,
    input wire [7:0] validVectorOri,

    input wire [64*8-1:0] Ins,
    output reg  [64*8-1:0] instructions,
    output reg [7:0] validVectorTo
);

integer i;

always @(posedge clk) begin
    for(i = 0; i < 64*8; i = i + 1) begin
        instructions[i] <= Ins[i];
    end
end

always @(negedge clk) begin
    validVectorTo = validVectorOri;
end

endmodule
module MultithreadInstructionUnit(
    input wire clk,
    input wire [7:0] validVectorOri,

    input wire [64*8-1:0] Ins,
    output reg  [64*8-1:0] instructions,
    output reg [7:0] validVectorTo
);


integer i;

always @(posedge clk) begin
    for(i = 0; i < 64*8; i = i + 1) begin
        instructions[i] <= Ins[i];
    end
end

always @(negedge clk) begin
    validVectorTo = validVectorOri;
end

endmodule