data/full_repos/permissive/143278/ivltests/module3.12A.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/module3.12A.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(out1 != 32\'h11223344)\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/module3.12A.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(out2 != 32\'h44332211)\n    ^\n%Warning-MULTITOP: data/full_repos/permissive/143278/ivltests/module3.12A.v:28: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                              : ... Top module \'mod1\'\nmodule mod1 ;\n       ^~~~\n                                                                              : ... Top module \'mod2\'\nmodule mod2 ();\n       ^~~~\n                                                                              : ... Top module \'mod3\'\nmodule mod3 (a,b);\n       ^~~~\n                                                                              : ... Top module \'main\'\nmodule main ();\n       ^~~~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mod1 ;
endmodule
module mod1 ;

endmodule