data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v
1: b'%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:76: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'cfg_paddr\' generates 6 bits.\n                                                                                                    : ... In instance frame_source\n    addr_i = cfg_paddr >> 2;  \n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:85: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_pwdata\' generates 32 bits.\n                                                                                                    : ... In instance frame_source\n          FrameLenAddr:   cfg_frame_len <= cfg_pwdata;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:86: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_pwdata\' generates 32 bits.\n                                                                                                    : ... In instance frame_source\n          GapLenAddr:     cfg_gap_len   <= cfg_pwdata;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:88: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_pwdata\' generates 32 bits.\n                                                                                                    : ... In instance frame_source\n          CycleCountAddr: cycle_count   <= cfg_pwdata;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:95: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                                    : ... In instance frame_source\n          StatusAddr:     cfg_prdata <= {dout_ready, dout_valid};\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:96: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_frame_len\' generates 16 bits.\n                                                                                                    : ... In instance frame_source\n          FrameLenAddr:   cfg_prdata <= cfg_frame_len;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:97: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_gap_len\' generates 16 bits.\n                                                                                                    : ... In instance frame_source\n          GapLenAddr:     cfg_prdata <= cfg_gap_len;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:98: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_go\' generates 1 bits.\n                                                                                                    : ... In instance frame_source\n          GoAddr:         cfg_prdata <= cfg_go;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:100: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'pos\' generates 16 bits.\n                                                                                                     : ... In instance frame_source\n          PosCountAddr:   cfg_prdata <= pos;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:101: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'frame_count\' generates 16 bits.\n                                                                                                     : ... In instance frame_source\n          FrameCountAddr: cfg_prdata <= frame_count;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:102: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cycle_count\' generates 16 bits.\n                                                                                                     : ... In instance frame_source\n          CycleCountAddr: cfg_prdata <= cycle_count;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:103: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_irq\' generates 1 bits.\n                                                                                                     : ... In instance frame_source\n          IrqAddr:        cfg_prdata <= cfg_irq;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:149: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'gen_data\' generates 8 bits.\n                                                                                                     : ... In instance frame_source\n          checksum      <= checksum + gen_data;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:153: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'gen_data\' generates 8 bits.\n                                                                                                     : ... In instance frame_source\n            checksum_r  <= checksum + gen_data;\n                                    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_source.v:185: Cannot find file containing module: \'stream_buf_v\'\n  stream_buf_v #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern,data/full_repos/permissive/181738725/stream_buf_v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern,data/full_repos/permissive/181738725/stream_buf_v.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern,data/full_repos/permissive/181738725/stream_buf_v.sv\n             stream_buf_v\n             stream_buf_v.v\n             stream_buf_v.sv\n             obj_dir/stream_buf_v\n             obj_dir/stream_buf_v.v\n             obj_dir/stream_buf_v.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n'
module frame_source #(
  parameter DataBits = 8,
  parameter GoDefault = 0)
(
  input                 clk,
  input                 rst,

  input [5:0]           cfg_paddr,
  input                 cfg_pwrite,
  input [31:0]          cfg_pwdata,
  input                 cfg_psel,
  input                 cfg_penable,
  output                cfg_pready,
  output reg [31:0]     cfg_prdata,
  output                cfg_pslverr,
  output reg            cfg_irq,

  output                dout_valid,
  input                 dout_ready,
  output [DataBits-1:0] dout_data,
  output                dout_eof
);




  localparam StatusAddr     = 0,
             FrameLenAddr   = 1,
             GapLenAddr     = 2,
             GoAddr         = 3,
             ChecksumAddr   = 4,
             PosCountAddr   = 5,
             FrameCountAddr = 6,
             CycleCountAddr = 7,
             IrqAddr        = 8;




  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;

  reg        cfg_go;
  reg [15:0] cfg_frame_len, cfg_gap_len, pos;
  reg [15:0] frame_count, cycle_count;
  reg [31:0] checksum, checksum_r;
  wire       gen_valid, gen_ready, gen_eof;

  always @(posedge clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;


    cycle_count <= cycle_count + 1;

    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        case (addr_i)
          FrameLenAddr:   cfg_frame_len <= cfg_pwdata;
          GapLenAddr:     cfg_gap_len   <= cfg_pwdata;
          GoAddr:         cfg_go        <= cfg_pwdata[0];
          CycleCountAddr: cycle_count   <= cfg_pwdata;
          IrqAddr:        cfg_irq       <= cfg_pwdata[0];
        endcase


      end else begin
        case (addr_i)
          StatusAddr:     cfg_prdata <= {dout_ready, dout_valid};
          FrameLenAddr:   cfg_prdata <= cfg_frame_len;
          GapLenAddr:     cfg_prdata <= cfg_gap_len;
          GoAddr:         cfg_prdata <= cfg_go;
          ChecksumAddr:   cfg_prdata <= checksum_r;
          PosCountAddr:   cfg_prdata <= pos;
          FrameCountAddr: cfg_prdata <= frame_count;
          CycleCountAddr: cfg_prdata <= cycle_count;
          IrqAddr:        cfg_prdata <= cfg_irq;
        endcase
      end
    end


    if (gen_valid & gen_ready & gen_eof)
      cfg_irq <= 1;

    if (rst) begin
      cfg_go         <= GoDefault;
      cfg_frame_len  <= 2230;
      cfg_gap_len    <= 100;
      cfg_irq        <= 0;
      cycle_count    <= 0;
    end
  end




  localparam Idle   = 0,
             Active = 1,
             Gap    = 2;

  reg [2:0]          state;
  reg [DataBits-1:0] gen_data, incr;
  reg [15:0]         gap_count;
  reg [15:0]         frame_len_m1;

  always @(posedge clk) begin

    case (state)

      Idle:
        if (cfg_go) begin
          state    <= Active;
          checksum <= 0;
          gen_data <= frame_count[DataBits-1:0];

          frame_len_m1 <= cfg_frame_len - 1;
        end

      Active:
        if (gen_ready) begin
          pos           <= pos + 1;
          checksum      <= checksum + gen_data;
          gen_data      <= gen_data + incr;
          if (gen_eof) begin
            pos         <= 0;
            checksum_r  <= checksum + gen_data;
            frame_count <= frame_count + 1;
            incr        <= incr + 1;
            gap_count   <= 0;
            state       <= Gap;
          end
        end

      Gap: begin
        gap_count <= gap_count + 1;
        if (gap_count >= cfg_gap_len) begin
          state    <= Idle;
        end
      end
    endcase

    if (rst) begin
      state       <= Idle;
      pos         <= 0;
      frame_count <= 0;
      incr        <= 1;
    end

  end

  assign  gen_valid  = state == Active;

  assign  gen_eof    = (pos == frame_len_m1);




  stream_buf_v #(
    .DataBits(DataBits+1))
  obuf (
    .clk       (clk),
    .rst       (rst),
    .in_valid  (gen_valid),
    .in_ready  (gen_ready),
    .in_data   ({gen_eof, gen_data}),
    .out_valid (dout_valid),
    .out_ready (dout_ready),
    .out_data  ({dout_eof, dout_data}));

endmodule
module frame_source #(
  parameter DataBits = 8,
  parameter GoDefault = 0)
(
  input                 clk,
  input                 rst,

  input [5:0]           cfg_paddr,
  input                 cfg_pwrite,
  input [31:0]          cfg_pwdata,
  input                 cfg_psel,
  input                 cfg_penable,
  output                cfg_pready,
  output reg [31:0]     cfg_prdata,
  output                cfg_pslverr,
  output reg            cfg_irq,

  output                dout_valid,
  input                 dout_ready,
  output [DataBits-1:0] dout_data,
  output                dout_eof
);





  localparam StatusAddr     = 0,
             FrameLenAddr   = 1,
             GapLenAddr     = 2,
             GoAddr         = 3,
             ChecksumAddr   = 4,
             PosCountAddr   = 5,
             FrameCountAddr = 6,
             CycleCountAddr = 7,
             IrqAddr        = 8;




  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;

  reg        cfg_go;
  reg [15:0] cfg_frame_len, cfg_gap_len, pos;
  reg [15:0] frame_count, cycle_count;
  reg [31:0] checksum, checksum_r;
  wire       gen_valid, gen_ready, gen_eof;

  always @(posedge clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;


    cycle_count <= cycle_count + 1;

    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        case (addr_i)
          FrameLenAddr:   cfg_frame_len <= cfg_pwdata;
          GapLenAddr:     cfg_gap_len   <= cfg_pwdata;
          GoAddr:         cfg_go        <= cfg_pwdata[0];
          CycleCountAddr: cycle_count   <= cfg_pwdata;
          IrqAddr:        cfg_irq       <= cfg_pwdata[0];
        endcase


      end else begin
        case (addr_i)
          StatusAddr:     cfg_prdata <= {dout_ready, dout_valid};
          FrameLenAddr:   cfg_prdata <= cfg_frame_len;
          GapLenAddr:     cfg_prdata <= cfg_gap_len;
          GoAddr:         cfg_prdata <= cfg_go;
          ChecksumAddr:   cfg_prdata <= checksum_r;
          PosCountAddr:   cfg_prdata <= pos;
          FrameCountAddr: cfg_prdata <= frame_count;
          CycleCountAddr: cfg_prdata <= cycle_count;
          IrqAddr:        cfg_prdata <= cfg_irq;
        endcase
      end
    end


    if (gen_valid & gen_ready & gen_eof)
      cfg_irq <= 1;

    if (rst) begin
      cfg_go         <= GoDefault;
      cfg_frame_len  <= 2230;
      cfg_gap_len    <= 100;
      cfg_irq        <= 0;
      cycle_count    <= 0;
    end
  end




  localparam Idle   = 0,
             Active = 1,
             Gap    = 2;

  reg [2:0]          state;
  reg [DataBits-1:0] gen_data, incr;
  reg [15:0]         gap_count;
  reg [15:0]         frame_len_m1;

  always @(posedge clk) begin

    case (state)

      Idle:
        if (cfg_go) begin
          state    <= Active;
          checksum <= 0;
          gen_data <= frame_count[DataBits-1:0];

          frame_len_m1 <= cfg_frame_len - 1;
        end

      Active:
        if (gen_ready) begin
          pos           <= pos + 1;
          checksum      <= checksum + gen_data;
          gen_data      <= gen_data + incr;
          if (gen_eof) begin
            pos         <= 0;
            checksum_r  <= checksum + gen_data;
            frame_count <= frame_count + 1;
            incr        <= incr + 1;
            gap_count   <= 0;
            state       <= Gap;
          end
        end

      Gap: begin
        gap_count <= gap_count + 1;
        if (gap_count >= cfg_gap_len) begin
          state    <= Idle;
        end
      end
    endcase

    if (rst) begin
      state       <= Idle;
      pos         <= 0;
      frame_count <= 0;
      incr        <= 1;
    end

  end

  assign  gen_valid  = state == Active;

  assign  gen_eof    = (pos == frame_len_m1);




  stream_buf_v #(
    .DataBits(DataBits+1))
  obuf (
    .clk       (clk),
    .rst       (rst),
    .in_valid  (gen_valid),
    .in_ready  (gen_ready),
    .in_data   ({gen_eof, gen_data}),
    .out_valid (dout_valid),
    .out_ready (dout_ready),
    .out_data  ({dout_eof, dout_data}));

endmodule