data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/ff_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/ff_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #clk_period reset = ~reset;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/ff_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #reset_period reset = ~reset;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/ff_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #half_clk_period clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/ff_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #d_period D = ~D;\n  ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/ff_tb.v:24: Cannot find file containing module: \'static_dff\'\nstatic_dff U0 (set, reset, clk, D, Q);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench,data/full_repos/permissive/137416811/static_dff\n             data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench,data/full_repos/permissive/137416811/static_dff.v\n             data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench,data/full_repos/permissive/137416811/static_dff.sv\n             static_dff\n             static_dff.v\n             static_dff.sv\n             obj_dir/static_dff\n             obj_dir/static_dff.v\n             obj_dir/static_dff.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module static_dff_tb;

wire set;
reg reset;
reg clk;
reg D;
wire Q;

parameter clk_period = 2;
parameter half_clk_period = clk_period / 2;
parameter d_period = 2 * clk_period;
parameter reset_period = 8 * clk_period;


static_dff U0 (set, reset, clk, D, Q);



initial 
begin
  reset = 1'b1;
  #clk_period reset = ~reset;
end
always 
begin
  #reset_period reset = ~reset;
end
 

assign set = 1'b0;


initial 
begin
  clk = 1'b0;
end
always 
begin
  #half_clk_period clk = ~clk;
end


initial 
begin
  D = 1'b0;
end
always 
begin
  #d_period D = ~D;
end




endmodule
module static_dff_tb;


wire set;
reg reset;
reg clk;
reg D;
wire Q;

parameter clk_period = 2;
parameter half_clk_period = clk_period / 2;
parameter d_period = 2 * clk_period;
parameter reset_period = 8 * clk_period;


static_dff U0 (set, reset, clk, D, Q);



initial 
begin
  reset = 1'b1;
  #clk_period reset = ~reset;
end
always 
begin
  #reset_period reset = ~reset;
end
 

assign set = 1'b0;


initial 
begin
  clk = 1'b0;
end
always 
begin
  #half_clk_period clk = ~clk;
end


initial 
begin
  D = 1'b0;
end
always 
begin
  #d_period D = ~D;
end




endmodule