data/full_repos/permissive/146399661/src/vedic/vedic8.v
1: b'%Warning-WIDTH: data/full_repos/permissive/146399661/src/vedic/vedic8.v:31: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                          : ... In instance vedic8\nvedic4 z1(a[3:0],b[3:0],q0[15:0]);\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/146399661/src/vedic/vedic8.v:32: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                          : ... In instance vedic8\nvedic4 z2(a[7:4],b[3:0],q1[15:0]);\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/146399661/src/vedic/vedic8.v:33: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                          : ... In instance vedic8\nvedic4 z3(a[3:0],b[7:4],q2[15:0]);\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/146399661/src/vedic/vedic8.v:34: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                          : ... In instance vedic8\nvedic4 z4(a[7:4],b[7:4],q3[15:0]);\n                          ^\n%Error: Exiting due to 4 warning(s)\n'
module add12bit(a,b,sum,carry);
input [11:0] a ;
input [11:0] b ;
output [11:0]sum ;
output carry;
wire [10:0]s;
fa z0(a[0],b[0],1'b0,sum[0],s[0]);
fa z1(a[1],b[1],s[0],sum[1],s[1]);
fa z2(a[2],b[2],s[1],sum[2],s[2]);
fa z3(a[3],b[3],s[2],sum[3],s[3]);
fa z4(a[4],b[4],s[3],sum[4],s[4]);
fa z5(a[5],b[5],s[4],sum[5],s[5]);
fa z6(a[6],b[6],s[5],sum[6],s[6]);
fa z7(a[7],b[7],s[6],sum[7],s[7]);
fa z8(a[8],b[8],s[7],sum[8],s[8]);
fa z9(a[9],b[9],s[8],sum[9],s[9]);
fa z10(a[10],b[10],s[9],sum[10],s[10]);
fa z11(a[11],b[11],s[10],sum[11],carry);
endmodule
module add12bit(a,b,sum,carry);

input [11:0] a ;
input [11:0] b ;
output [11:0]sum ;
output carry;
wire [10:0]s;
fa z0(a[0],b[0],1'b0,sum[0],s[0]);
fa z1(a[1],b[1],s[0],sum[1],s[1]);
fa z2(a[2],b[2],s[1],sum[2],s[2]);
fa z3(a[3],b[3],s[2],sum[3],s[3]);
fa z4(a[4],b[4],s[3],sum[4],s[4]);
fa z5(a[5],b[5],s[4],sum[5],s[5]);
fa z6(a[6],b[6],s[5],sum[6],s[6]);
fa z7(a[7],b[7],s[6],sum[7],s[7]);
fa z8(a[8],b[8],s[7],sum[8],s[8]);
fa z9(a[9],b[9],s[8],sum[9],s[9]);
fa z10(a[10],b[10],s[9],sum[10],s[10]);
fa z11(a[11],b[11],s[10],sum[11],carry);
endmodule