data/full_repos/permissive/164484080/testbench/mimasv2_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/mimasv2_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #5 Mv2_CLK = ~Mv2_CLK;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/mimasv2_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/mimasv2_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Error: data/full_repos/permissive/164484080/testbench/mimasv2_tb.v:34: Cannot find file containing module: \'mimasv2\'\n mimasv2 uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164484080/testbench,data/full_repos/permissive/164484080/mimasv2\n             data/full_repos/permissive/164484080/testbench,data/full_repos/permissive/164484080/mimasv2.v\n             data/full_repos/permissive/164484080/testbench,data/full_repos/permissive/164484080/mimasv2.sv\n             mimasv2\n             mimasv2.v\n             mimasv2.sv\n             obj_dir/mimasv2\n             obj_dir/mimasv2.v\n             obj_dir/mimasv2.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mimasv2_tb;


	reg Mv2_CLK;


	wire [7:0] Mv2_LED;


	mimasv2 uut (
		.Mv2_CLK(Mv2_CLK),
		.Mv2_LED(Mv2_LED)
	);

	always begin
		#5 Mv2_CLK = ~Mv2_CLK;
	end

	initial begin

		Mv2_CLK = 0;


		#100;


		#2000;
	end

endmodule
module mimasv2_tb;



	reg Mv2_CLK;


	wire [7:0] Mv2_LED;


	mimasv2 uut (
		.Mv2_CLK(Mv2_CLK),
		.Mv2_LED(Mv2_LED)
	);

	always begin
		#5 Mv2_CLK = ~Mv2_CLK;
	end

	initial begin

		Mv2_CLK = 0;


		#100;


		#2000;
	end

endmodule