data/full_repos/permissive/112219256/execute_stage.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/112219256/execute_stage.v:305: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'execute_stage\'\nmodule execute_stage(\n       ^~~~~~~~~~~~~\n                                                                           : ... Top module \'MUX_3_5\'\nmodule MUX_3_5(\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112219256/execute_stage.v:409: Operator NOT expects 3 bits on the LHS, but LHS\'s VARREF \'vaddr\' generates 2 bits.\n                                                                        : ... In instance execute_stage.Store\n  assign size_r = &(~vaddr) ? 3\'b010 : ~vaddr;  \n                                       ^\n%Error: data/full_repos/permissive/112219256/execute_stage.v:241: Cannot find file containing module: \'MUX_4_32\'\n    MUX_4_32 ALUA_MUX(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.v\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.sv\n             MUX_4_32\n             MUX_4_32.v\n             MUX_4_32.sv\n             obj_dir/MUX_4_32\n             obj_dir/MUX_4_32.v\n             obj_dir/MUX_4_32.sv\n%Error: data/full_repos/permissive/112219256/execute_stage.v:250: Cannot find file containing module: \'MUX_4_32\'\n    MUX_4_32 ALUB_MUX(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/execute_stage.v:259: Cannot find file containing module: \'ALU\'\n    ALU ALU(\n    ^~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module Addr_error(
    input  wire        is_lh   ,  
    input  wire        is_lw   ,
    input  wire        is_sh   ,
    input  wire        is_sw   ,
    input  wire [ 1:0] address ,
    output wire        AdEL_EXE,
    output wire        AdES_EXE
  );
  wire   AdEL_LH, AdEL_LW, AdES_SH, AdES_SW;
  assign AdEL_LH = address[0] & is_lh;
  assign AdEL_LW = (|address) & is_lw;

  assign AdES_SH = address[0] & is_sh;
  assign AdES_SW = (|address) & is_sw;

  assign AdEL_EXE = AdEL_LH | AdEL_LW;
  assign AdES_EXE = AdES_SH | AdES_SW;

endmodule
module Addr_error(
    input  wire        is_lh   ,  
    input  wire        is_lw   ,
    input  wire        is_sh   ,
    input  wire        is_sw   ,
    input  wire [ 1:0] address ,
    output wire        AdEL_EXE,
    output wire        AdES_EXE
  );

  wire   AdEL_LH, AdEL_LW, AdES_SH, AdES_SW;
  assign AdEL_LH = address[0] & is_lh;
  assign AdEL_LW = (|address) & is_lw;

  assign AdES_SH = address[0] & is_sh;
  assign AdES_SW = (|address) & is_sw;

  assign AdEL_EXE = AdEL_LH | AdEL_LW;
  assign AdES_EXE = AdES_SH | AdES_SW;

endmodule