data/full_repos/permissive/202776140/bidi_register.v
data/verilator_xmls/92929195-2fb4-49e6-b7fa-e3062795bab2.xml
module bidi_register (
RESET,
CLOCK,
RW,
ENABLE,
COUNT,

DATA
);

parameter BUS_WIDTH = 16;
parameter COUNT_EN = 1;

input wire RESET;
input wire CLOCK;
input wire RW;
input wire ENABLE;
input wire COUNT;

inout wire [BUS_WIDTH-1:0] DATA;

reg [BUS_WIDTH-1:0] INTERNAL_DATA;

always @(posedge CLOCK) begin
    if (!RESET) begin

        INTERNAL_DATA <= {BUS_WIDTH{1'b0}};
    end


    else if (ENABLE && RW == 0) begin
        INTERNAL_DATA <= DATA;
    end 
    else if ((!ENABLE || ENABLE && !RW) && COUNT_EN && COUNT) begin
        INTERNAL_DATA <= INTERNAL_DATA + 1;
    end
end

assign DATA = (ENABLE && RW == 1) ? INTERNAL_DATA : {BUS_WIDTH{1'bz}};

endmodule
module bidi_register (
RESET,
CLOCK,
RW,
ENABLE,
COUNT,

DATA
);


parameter BUS_WIDTH = 16;
parameter COUNT_EN = 1;

input wire RESET;
input wire CLOCK;
input wire RW;
input wire ENABLE;
input wire COUNT;

inout wire [BUS_WIDTH-1:0] DATA;

reg [BUS_WIDTH-1:0] INTERNAL_DATA;

always @(posedge CLOCK) begin
    if (!RESET) begin

        INTERNAL_DATA <= {BUS_WIDTH{1'b0}};
    end


    else if (ENABLE && RW == 0) begin
        INTERNAL_DATA <= DATA;
    end 
    else if ((!ENABLE || ENABLE && !RW) && COUNT_EN && COUNT) begin
        INTERNAL_DATA <= INTERNAL_DATA + 1;
    end
end

assign DATA = (ENABLE && RW == 1) ? INTERNAL_DATA : {BUS_WIDTH{1'bz}};

endmodule