data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/serial_transmitter_wrapper.v
 line:109: before: "data"
1: b"%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/serial_transmitter_wrapper.v:57: Cannot find file containing module: 'buslayer_slave'\nbuslayer_slave slave_interface (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/buslayer_slave\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/buslayer_slave.v\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/buslayer_slave.sv\n             buslayer_slave\n             buslayer_slave.v\n             buslayer_slave.sv\n             obj_dir/buslayer_slave\n             obj_dir/buslayer_slave.v\n             obj_dir/buslayer_slave.sv\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/serial_transmitter_wrapper.v:86: Cannot find file containing module: 'serial_transmitter'\nserial_transmitter transmitter (\n^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module serial_transmitter_wrapper(

    input  logic        wb_clk,
    input  logic        wb_rst,
    input  logic        wb_cyc,
    input  logic        wb_stb,
    input  logic        wb_we,
    input  logic  [3:0] wb_sel,
    input  logic [31:0] wb_dat_i,
    input  logic [31:0] wb_adr,
    output logic        wb_ack,
    output logic        wb_err,
    output logic        wb_stall,
    output logic [31:0] wb_dat_o

);


logic clk, rst;

logic  [3:0] byte_sel;

logic [31:0] data_from_bus;

logic request, write, done, err;

logic [7:0] data;

buslayer_slave slave_interface (

    .wb_clk(wb_clk),
    .wb_rst(wb_rst),
    .wb_cyc(wb_cyc),
    .wb_stb(wb_stb),
    .wb_we(wb_we),
    .wb_sel(wb_sel),
    .wb_dat_i(wb_dat_i),
    .wb_adr(wb_adr),
    .wb_ack(wb_ack),
    .wb_err(wb_err),
    .wb_stall(wb_stall),
    .wb_dat_o(wb_dat_o),

    

    .request(request),
    .write(write),
    .reset(rst),
    .address(),
    .data_from_bus(data_from_bus),
    .byte_sel(byte_sel),
    .data_to_bus(32'b0),
    .done(done),
    .err(err)

);

serial_transmitter transmitter (
    .clk(wb_clk),
    .rst(rst),
    .data(data),
    .send(request && !err),
    .done(done),
    .val()
);


always_comb begin
   err = (request == 1'b1) && 
             (write == 1'b0 || 
                (byte_sel[3:0] != 4'b0001 && 
                 byte_sel[3:0] != 4'b0010 &&
                 byte_sel[3:0] != 4'b0100 &&
                 byte_sel[3:0] != 4'b1000)); 
                 
   case (byte_sel)
    4'b0001: data = data_from_bus[7:0];
    4'b0010: data = data_from_bus[15:8];
    4'b0100: data = data_from_bus[23:16];
    4'b1000: data = data_from_bus[31:24];
    default data = 8'b0;
   endcase
end
 
endmodule
module serial_transmitter_wrapper(

    input  logic        wb_clk,
    input  logic        wb_rst,
    input  logic        wb_cyc,
    input  logic        wb_stb,
    input  logic        wb_we,
    input  logic  [3:0] wb_sel,
    input  logic [31:0] wb_dat_i,
    input  logic [31:0] wb_adr,
    output logic        wb_ack,
    output logic        wb_err,
    output logic        wb_stall,
    output logic [31:0] wb_dat_o

);



logic clk, rst;

logic  [3:0] byte_sel;

logic [31:0] data_from_bus;

logic request, write, done, err;

logic [7:0] data;

buslayer_slave slave_interface (

    .wb_clk(wb_clk),
    .wb_rst(wb_rst),
    .wb_cyc(wb_cyc),
    .wb_stb(wb_stb),
    .wb_we(wb_we),
    .wb_sel(wb_sel),
    .wb_dat_i(wb_dat_i),
    .wb_adr(wb_adr),
    .wb_ack(wb_ack),
    .wb_err(wb_err),
    .wb_stall(wb_stall),
    .wb_dat_o(wb_dat_o),

    

    .request(request),
    .write(write),
    .reset(rst),
    .address(),
    .data_from_bus(data_from_bus),
    .byte_sel(byte_sel),
    .data_to_bus(32'b0),
    .done(done),
    .err(err)

);

serial_transmitter transmitter (
    .clk(wb_clk),
    .rst(rst),
    .data(data),
    .send(request && !err),
    .done(done),
    .val()
);


always_comb begin
   err = (request == 1'b1) && 
             (write == 1'b0 || 
                (byte_sel[3:0] != 4'b0001 && 
                 byte_sel[3:0] != 4'b0010 &&
                 byte_sel[3:0] != 4'b0100 &&
                 byte_sel[3:0] != 4'b1000)); 
                 
   case (byte_sel)
    4'b0001: data = data_from_bus[7:0];
    4'b0010: data = data_from_bus[15:8];
    4'b0100: data = data_from_bus[23:16];
    4'b1000: data = data_from_bus[31:24];
    default data = 8'b0;
   endcase
end
 
endmodule