data/full_repos/permissive/202237519/verilog/digitalsystem project/score.v
1: b'%Error: Cannot find file containing module: project,data/full_repos/permissive/202237519\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519.sv\n             project,data/full_repos/permissive/202237519\n             project,data/full_repos/permissive/202237519.v\n             project,data/full_repos/permissive/202237519.sv\n             obj_dir/project,data/full_repos/permissive/202237519\n             obj_dir/project,data/full_repos/permissive/202237519.v\n             obj_dir/project,data/full_repos/permissive/202237519.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/202237519/verilog/digitalsystem\n%Error: Cannot find file containing module: project/score.v\n%Error: Exiting due to 3 error(s)\n'
module score(clk,reset,a,b,light,en);
   
input clk,en,reset;
input [7:0]a,b;
output [5:0]light;
reg [7:0]r;
reg [5:0]q = 0;
reg [5:0]rgb;

assign light = rgb;

always@(posedge clk) begin
    if(reset) begin
        q = 0;
        end
    else if(en == 1'b1 )begin
        r = a^b;   
        if(r == 8'b00000000)   
            q = q + 1'b1;
        else
            q = q;
    end
end

always @(posedge clk) begin
    if(q>=60) begin
        rgb = 6'b001100;
        end

    else if(q>=30 && q <60) begin
        rgb = 6'b000011;
        end

    else if(q>=0 && q <30) begin
        rgb = 6'b110000;
        end
end

endmodule
module score(clk,reset,a,b,light,en);

   
input clk,en,reset;
input [7:0]a,b;
output [5:0]light;
reg [7:0]r;
reg [5:0]q = 0;
reg [5:0]rgb;

assign light = rgb;

always@(posedge clk) begin
    if(reset) begin
        q = 0;
        end
    else if(en == 1'b1 )begin
        r = a^b;   
        if(r == 8'b00000000)   
            q = q + 1'b1;
        else
            q = q;
    end
end

always @(posedge clk) begin
    if(q>=60) begin
        rgb = 6'b001100;
        end

    else if(q>=30 && q <60) begin
        rgb = 6'b000011;
        end

    else if(q>=0 && q <30) begin
        rgb = 6'b110000;
        end
end

endmodule