data/full_repos/permissive/19572582/Lab3/lab3_part1.v
data/verilator_xmls/c9637346-8e36-41e5-badc-afa050e6c97f.xml
module lab3_part1 (Clk, R, S, Q);
  input Clk, R, S;
  output Q;

  wire R_g, S_g, Qa, Qb;

  assign R_g = R & Clk;
  assign S_g = S & Clk;
  assign Qa = ~(R_g | Qb);
  assign Qb = ~(S_g | Qa);

  assign Q = Qa;
endmodule
module lab3_part1 (Clk, R, S, Q);

  input Clk, R, S;
  output Q;

  wire R_g, S_g, Qa, Qb;

  assign R_g = R & Clk;
  assign S_g = S & Clk;
  assign Qa = ~(R_g | Qb);
  assign Qb = ~(S_g | Qa);

  assign Q = Qa;
endmodule