data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v
1: b'%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:1: Cannot find include file: ../defs.v\n`include "../defs.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161029703/src/cpu/stage_mm,data/full_repos/permissive/161029703/../defs.v\n             data/full_repos/permissive/161029703/src/cpu/stage_mm,data/full_repos/permissive/161029703/../defs.v.v\n             data/full_repos/permissive/161029703/src/cpu/stage_mm,data/full_repos/permissive/161029703/../defs.v.sv\n             ../defs.v\n             ../defs.v.v\n             ../defs.v.sv\n             obj_dir/../defs.v\n             obj_dir/../defs.v.v\n             obj_dir/../defs.v.sv\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:40: Define or directive not defined: \'`ACCESS_OP_M2R\'\nassign alignment_err = (mem_access_op==`ACCESS_OP_M2R || mem_access_op==`ACCESS_OP_R2M) &&\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:40: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\nassign alignment_err = (mem_access_op==`ACCESS_OP_M2R || mem_access_op==`ACCESS_OP_R2M) &&\n                                                      ^~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:40: Define or directive not defined: \'`ACCESS_OP_R2M\'\nassign alignment_err = (mem_access_op==`ACCESS_OP_M2R || mem_access_op==`ACCESS_OP_R2M) &&\n                                                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:41: Define or directive not defined: \'`ACCESS_SZ_HALF\'\n                        ((mem_access_sz == `ACCESS_SZ_HALF && addr_i[0]!=1\'b0) ||\n                                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:42: Define or directive not defined: \'`ACCESS_SZ_WORD\'\n                            (mem_access_sz == `ACCESS_SZ_WORD && addr_i[1:0]!=2\'b0));\n                                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:50: Define or directive not defined: \'`ACCESS_SZ_HALF\'\n    if(mem_access_sz == `ACCESS_SZ_HALF) begin\n                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:50: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if(mem_access_sz == `ACCESS_SZ_HALF) begin\n                                       ^\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:52: Define or directive not defined: \'`ACCESS_SZ_BYTE\'\n    end else if(mem_access_sz == `ACCESS_SZ_BYTE) begin\n                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:59: Define or directive not defined: \'`ACCESS_SZ_LEFT\'\n    end else if(mem_access_sz == `ACCESS_SZ_LEFT) begin\n                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:61: Define or directive not defined: \'`ACCESS_SZ_RIGHT\'\n    end else if(mem_access_sz == `ACCESS_SZ_RIGHT) begin\n                                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:70: Define or directive not defined: \'`ACCESS_OP_M2R\'\n    `ACCESS_OP_M2R: begin\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:75: Define or directive not defined: \'`ACCESS_OP_R2M\'\n    `ACCESS_OP_R2M: begin\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:78: Define or directive not defined: \'`ACCESS_SZ_WORD\'\n        if(mem_access_sz==`ACCESS_SZ_WORD)\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:78: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if(mem_access_sz==`ACCESS_SZ_WORD)\n                                         ^\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:80: Define or directive not defined: \'`ACCESS_SZ_HALF\'\n        else if(mem_access_sz==`ACCESS_SZ_HALF)\n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:82: Define or directive not defined: \'`ACCESS_SZ_LEFT\'\n        else if(mem_access_sz==`ACCESS_SZ_LEFT) \n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:84: Define or directive not defined: \'`ACCESS_SZ_RIGHT\'\n        else if(mem_access_sz==`ACCESS_SZ_RIGHT)\n                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_mm/mm.v:86: Define or directive not defined: \'`ACCESS_SZ_BYTE\'\n        else if(mem_access_sz==`ACCESS_SZ_BYTE)\n                               ^~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module mm(

          data_o,
          mem_address,
          mem_data_o,
          mem_rd,
          mem_wr,
          mem_byte_en,
          alignment_err,

          mem_access_op,
          mem_access_sz,
          data_i,
          reg_addr_i,
          addr_i,
          flag_unsigned,
          exception_flush);

input wire[1:0] mem_access_op;
input wire[2:0] mem_access_sz;
input wire[31:0] data_i;
input wire[4:0] reg_addr_i;
input wire[31:0] addr_i;
input wire flag_unsigned;
input wire exception_flush;

output wire[31:0] data_o;

output wire[31:0] mem_address;
output reg[31:0] mem_data_o;
output reg mem_rd;
output reg mem_wr;
output reg[3:0] mem_byte_en;
output wire alignment_err;

wire[4:0] left_shift, right_shift;

assign alignment_err = (mem_access_op==`ACCESS_OP_M2R || mem_access_op==`ACCESS_OP_R2M) &&
                        ((mem_access_sz == `ACCESS_SZ_HALF && addr_i[0]!=1'b0) ||
                            (mem_access_sz == `ACCESS_SZ_WORD && addr_i[1:0]!=2'b0));

assign mem_address = addr_i;
assign left_shift = ((2'd3 - addr_i[1:0])<<3);
assign right_shift = (addr_i[1:0]<<3);
assign data_o = data_i;

always @(*) begin
    if(mem_access_sz == `ACCESS_SZ_HALF) begin
        mem_byte_en <= {addr_i[1],addr_i[1],~addr_i[1],~addr_i[1]};
    end else if(mem_access_sz == `ACCESS_SZ_BYTE) begin
        case(addr_i[1:0])
        2'b11: begin mem_byte_en <= 4'b1000; end
        2'b10: begin mem_byte_en <= 4'b0100; end
        2'b01: begin mem_byte_en <= 4'b0010; end
        2'b00: begin mem_byte_en <= 4'b0001; end
        endcase
    end else if(mem_access_sz == `ACCESS_SZ_LEFT) begin
        mem_byte_en <= {addr_i[1]&addr_i[0], addr_i[1], addr_i[1]|addr_i[0], 1'b1};
    end else if(mem_access_sz == `ACCESS_SZ_RIGHT) begin
        mem_byte_en <= {1'b1, ~(addr_i[1]&addr_i[0]), ~addr_i[1], ~(addr_i[1]|addr_i[0])};
    end else begin
        mem_byte_en <= 4'b1111;
    end
end

always @(*) begin
    case(mem_access_op)
    `ACCESS_OP_M2R: begin
        mem_rd <= 1'b1;
        mem_wr <= 1'b0;
        mem_data_o <= 32'b0;
    end
    `ACCESS_OP_R2M: begin
        mem_rd <= 1'b0;
        mem_wr <= 1'b1;
        if(mem_access_sz==`ACCESS_SZ_WORD)
            mem_data_o <= data_i;
        else if(mem_access_sz==`ACCESS_SZ_HALF)
            mem_data_o <= {data_i[15:0], data_i[15:0]};
        else if(mem_access_sz==`ACCESS_SZ_LEFT) 
            mem_data_o <= data_i>>left_shift;
        else if(mem_access_sz==`ACCESS_SZ_RIGHT)
            mem_data_o <= data_i<<right_shift;
        else if(mem_access_sz==`ACCESS_SZ_BYTE)
            mem_data_o <= {data_i[7:0], data_i[7:0], data_i[7:0], data_i[7:0]};
        else
            mem_data_o <= 32'b0;
    end

    default: begin
        mem_rd <= 1'b0;
        mem_wr <= 1'b0;
        mem_data_o <= 32'b0;
    end
    endcase
end

endmodule
module mm(

          data_o,
          mem_address,
          mem_data_o,
          mem_rd,
          mem_wr,
          mem_byte_en,
          alignment_err,

          mem_access_op,
          mem_access_sz,
          data_i,
          reg_addr_i,
          addr_i,
          flag_unsigned,
          exception_flush);


input wire[1:0] mem_access_op;
input wire[2:0] mem_access_sz;
input wire[31:0] data_i;
input wire[4:0] reg_addr_i;
input wire[31:0] addr_i;
input wire flag_unsigned;
input wire exception_flush;

output wire[31:0] data_o;

output wire[31:0] mem_address;
output reg[31:0] mem_data_o;
output reg mem_rd;
output reg mem_wr;
output reg[3:0] mem_byte_en;
output wire alignment_err;

wire[4:0] left_shift, right_shift;

assign alignment_err = (mem_access_op==`ACCESS_OP_M2R || mem_access_op==`ACCESS_OP_R2M) &&
                        ((mem_access_sz == `ACCESS_SZ_HALF && addr_i[0]!=1'b0) ||
                            (mem_access_sz == `ACCESS_SZ_WORD && addr_i[1:0]!=2'b0));

assign mem_address = addr_i;
assign left_shift = ((2'd3 - addr_i[1:0])<<3);
assign right_shift = (addr_i[1:0]<<3);
assign data_o = data_i;

always @(*) begin
    if(mem_access_sz == `ACCESS_SZ_HALF) begin
        mem_byte_en <= {addr_i[1],addr_i[1],~addr_i[1],~addr_i[1]};
    end else if(mem_access_sz == `ACCESS_SZ_BYTE) begin
        case(addr_i[1:0])
        2'b11: begin mem_byte_en <= 4'b1000; end
        2'b10: begin mem_byte_en <= 4'b0100; end
        2'b01: begin mem_byte_en <= 4'b0010; end
        2'b00: begin mem_byte_en <= 4'b0001; end
        endcase
    end else if(mem_access_sz == `ACCESS_SZ_LEFT) begin
        mem_byte_en <= {addr_i[1]&addr_i[0], addr_i[1], addr_i[1]|addr_i[0], 1'b1};
    end else if(mem_access_sz == `ACCESS_SZ_RIGHT) begin
        mem_byte_en <= {1'b1, ~(addr_i[1]&addr_i[0]), ~addr_i[1], ~(addr_i[1]|addr_i[0])};
    end else begin
        mem_byte_en <= 4'b1111;
    end
end

always @(*) begin
    case(mem_access_op)
    `ACCESS_OP_M2R: begin
        mem_rd <= 1'b1;
        mem_wr <= 1'b0;
        mem_data_o <= 32'b0;
    end
    `ACCESS_OP_R2M: begin
        mem_rd <= 1'b0;
        mem_wr <= 1'b1;
        if(mem_access_sz==`ACCESS_SZ_WORD)
            mem_data_o <= data_i;
        else if(mem_access_sz==`ACCESS_SZ_HALF)
            mem_data_o <= {data_i[15:0], data_i[15:0]};
        else if(mem_access_sz==`ACCESS_SZ_LEFT) 
            mem_data_o <= data_i>>left_shift;
        else if(mem_access_sz==`ACCESS_SZ_RIGHT)
            mem_data_o <= data_i<<right_shift;
        else if(mem_access_sz==`ACCESS_SZ_BYTE)
            mem_data_o <= {data_i[7:0], data_i[7:0], data_i[7:0], data_i[7:0]};
        else
            mem_data_o <= 32'b0;
    end

    default: begin
        mem_rd <= 1'b0;
        mem_wr <= 1'b0;
        mem_data_o <= 32'b0;
    end
    endcase
end

endmodule