data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:116: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdptr_b_rd  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:117: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdptr_g_rd  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:118: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrptr_g_rd1 <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:119: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrptr_g_rd2 <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:120: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrptr_b_rd  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:121: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdusedw     <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:131: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  rdptr_g_rd  <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:132: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  wrptr_g_rd1 <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:133: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  wrptr_g_rd2 <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:204: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrptr_b_wr  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:205: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrptr_g_wr  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:206: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdptr_g_wr1 <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:207: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdptr_g_wr2 <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:208: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdptr_b_wr  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:209: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrusedw     <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:219: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  wrptr_g_wr  <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:220: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  rdptr_g_wr1 <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:221: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  rdptr_g_wr2 <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:222: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  rdptr_b_wr  <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Error: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:377: Cannot find file containing module: \'dp_ram\'\ndp_ram\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141582589/src/common_rtl,data/full_repos/permissive/141582589/dp_ram\n             data/full_repos/permissive/141582589/src/common_rtl,data/full_repos/permissive/141582589/dp_ram.v\n             data/full_repos/permissive/141582589/src/common_rtl,data/full_repos/permissive/141582589/dp_ram.sv\n             dp_ram\n             dp_ram.v\n             dp_ram.sv\n             obj_dir/dp_ram\n             obj_dir/dp_ram.v\n             obj_dir/dp_ram.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n'
module lite_fifo
  #(
    parameter COMMON_CLOCK = 0 ,
    parameter ADDR_WIDTH = 8 ,
    parameter DATA_WIDTH = 32 ,
    parameter USE_RAM_OUTPUT_REGISTER = 0
    )
    (
     input rdclk ,
     input wrclk ,
     input aclr ,
     input wrreq ,
     input rdreq ,
     input [DATA_WIDTH-1 : 0] data ,
     output reg rdempty ,
     output reg wrfull ,
     output reg rdvalid ,
     output reg [ADDR_WIDTH : 0] rdusedw ,
     output reg [ADDR_WIDTH : 0] wrusedw ,
     output [DATA_WIDTH-1 : 0] q
     ) ;


   localparam                   OUTDATA_REG_B = (USE_RAM_OUTPUT_REGISTER == 1) ?
                               "CLOCK1" : "UNREGISTERED" ;

   reg [ADDR_WIDTH:0]          wrptr_b_wr_next ;
   reg [ADDR_WIDTH:0]          wrptr_b_wr ;
   reg [ADDR_WIDTH:0]          wrptr_g_wr ;
   reg [ADDR_WIDTH:0]          wrptr_g_rd1 ;
   reg [ADDR_WIDTH:0]          wrptr_g_rd2 ;
   reg [ADDR_WIDTH:0]          wrptr_b_rd_next ;
   reg [ADDR_WIDTH:0]          wrptr_b_rd ;
   reg [ADDR_WIDTH:0]          rdptr_b_rd_next ;
   reg [ADDR_WIDTH:0]          rdptr_b_rd ;
   reg [ADDR_WIDTH:0]          rdptr_g_rd ;
   reg [ADDR_WIDTH:0]          rdptr_g_wr1 ;
   reg [ADDR_WIDTH:0]          rdptr_g_wr2 ;
   reg [ADDR_WIDTH:0]          rdptr_b_wr ;
   reg                         wrreq_allow ;
   reg                         rdvalid_next ;
   reg                         rdclocken ;
   reg [ADDR_WIDTH-1:0]        rdaddress ;
   wire [DATA_WIDTH-1:0]       q_ram ;
   reg  [DATA_WIDTH-1:0]       q_reg ;

   reg                         ra_held ;
   reg                         ra_held_next ;

   function [ADDR_WIDTH:0] gray2bin
     ( input [ADDR_WIDTH:0] gray ) ;
      reg [ADDR_WIDTH:0] temp ;
      integer i ;
      begin
         temp[ADDR_WIDTH] = gray[ADDR_WIDTH] ;
         for (i = (ADDR_WIDTH-1); i >= 0 ; i = i - 1)
           begin
              temp[i] = temp[i+1] ^ gray[i] ;
           end
         gray2bin = temp ;
      end
   endfunction

   function [ADDR_WIDTH:0] bin2gray
     (input [ADDR_WIDTH:0] bin ) ;
      integer i ;
      begin
         bin2gray[ADDR_WIDTH] = bin[ADDR_WIDTH] ;
         for (i = 0 ; i < (ADDR_WIDTH) ; i = i + 1)
           begin
             bin2gray[i] = bin[i+1] ^ bin[i] ;
           end
      end
   endfunction

   


   always @(rdptr_b_rd,wrptr_b_rd,rdreq,ra_held)
     begin


        if ( (rdreq == 1'b1) && (rdptr_b_rd != wrptr_b_rd) && (ra_held == 1'b0) )
          begin

             rdptr_b_rd_next = rdptr_b_rd + 1'b1 ;
             rdvalid_next = 1'b1 ;
          end
        else
          begin

             rdptr_b_rd_next = rdptr_b_rd ;
             rdvalid_next = 1'b0 ;
          end
     end


   always @(wrptr_b_wr,wrptr_g_rd2)
     begin
        if (COMMON_CLOCK == 1)
          begin


             wrptr_b_rd_next  = wrptr_b_wr ;
          end
        else
          begin
             wrptr_b_rd_next = gray2bin(wrptr_g_rd2) ;
          end
     end

   always @(posedge rdclk or posedge aclr)
     begin
        if (aclr)
          begin
             rdptr_b_rd  <= {ADDR_WIDTH{1'b0}} ;
             rdptr_g_rd  <= {ADDR_WIDTH{1'b0}} ;
             wrptr_g_rd1 <= {ADDR_WIDTH{1'b0}} ;
             wrptr_g_rd2 <= {ADDR_WIDTH{1'b0}} ;
             wrptr_b_rd  <= {ADDR_WIDTH{1'b0}} ;
             rdusedw     <= {ADDR_WIDTH{1'b0}} ;
             rdempty     <= 1'b1 ;
             rdvalid     <= 1'b0 ;
          end
        else
          begin
             rdptr_b_rd <= rdptr_b_rd_next ;
             if (COMMON_CLOCK == 1)
               begin

                  rdptr_g_rd  <= {ADDR_WIDTH{1'b0}} ;
                  wrptr_g_rd1 <= {ADDR_WIDTH{1'b0}} ;
                  wrptr_g_rd2 <= {ADDR_WIDTH{1'b0}} ;
               end
             else
               begin
                  rdptr_g_rd <= bin2gray(rdptr_b_rd) ;
                  wrptr_b_rd <= gray2bin(wrptr_g_rd2) ;
                  wrptr_g_rd2 <= wrptr_g_rd1 ;
                  wrptr_g_rd1 <= wrptr_g_wr ;
               end

             wrptr_b_rd <= wrptr_b_rd_next ;



             if (ra_held == 1'b1)
               rdusedw <= {(ADDR_WIDTH+1){1'b0}} ;
             else
               rdusedw <= wrptr_b_rd[ADDR_WIDTH:0] - rdptr_b_rd_next[ADDR_WIDTH:0] ;
             if (wrptr_b_rd == rdptr_b_rd_next)
               rdempty <= 1'b1 ;
             else
               rdempty <= ra_held ;
             rdvalid <= rdvalid_next ;
          end
     end


   always @(rdptr_b_wr,rdptr_b_rd,wrptr_b_wr,wrreq)
     begin
        if (COMMON_CLOCK == 0)
          begin
             if ( (wrreq == 1'b1) &&
                  ( (rdptr_b_wr[ADDR_WIDTH-1:0] != wrptr_b_wr[ADDR_WIDTH-1:0]) ||
                    (rdptr_b_wr[ADDR_WIDTH]     == wrptr_b_wr[ADDR_WIDTH]) ) )
               begin

                  wrptr_b_wr_next = wrptr_b_wr + 1'b1 ;
                  wrreq_allow = 1'b1 ;
               end
             else
               begin

                  wrptr_b_wr_next = wrptr_b_wr ;
                  wrreq_allow = 1'b0 ;
               end
          end
        else
          begin


             if ( (wrreq == 1'b1) &&
                  ( (rdptr_b_rd[ADDR_WIDTH-1:0] != wrptr_b_wr[ADDR_WIDTH-1:0]) ||
                    (rdptr_b_rd[ADDR_WIDTH]     == wrptr_b_wr[ADDR_WIDTH]) ) )
               begin

                  wrptr_b_wr_next = wrptr_b_wr + 1'b1 ;
                  wrreq_allow = 1'b1 ;
               end
             else
               begin

                  wrptr_b_wr_next = wrptr_b_wr ;
                  wrreq_allow = 1'b0 ;
               end
          end
     end

   always @(posedge wrclk or posedge aclr)
     begin
        if (aclr)
          begin
             wrptr_b_wr  <= {ADDR_WIDTH{1'b0}} ;
             wrptr_g_wr  <= {ADDR_WIDTH{1'b0}} ;
             rdptr_g_wr1 <= {ADDR_WIDTH{1'b0}} ;
             rdptr_g_wr2 <= {ADDR_WIDTH{1'b0}} ;
             rdptr_b_wr  <= {ADDR_WIDTH{1'b0}} ;
             wrusedw     <= {ADDR_WIDTH{1'b0}} ;
             wrfull      <= 1'b0 ;
          end
        else
          begin
             wrptr_b_wr <= wrptr_b_wr_next ;
             if (COMMON_CLOCK == 1)
               begin


                  wrptr_g_wr  <= {ADDR_WIDTH{1'b0}} ;
                  rdptr_g_wr1 <= {ADDR_WIDTH{1'b0}} ;
                  rdptr_g_wr2 <= {ADDR_WIDTH{1'b0}} ;
                  rdptr_b_wr  <= {ADDR_WIDTH{1'b0}} ;


                  wrusedw <= wrptr_b_wr_next[ADDR_WIDTH:0] - rdptr_b_rd[ADDR_WIDTH:0] ;

                  if ( (rdptr_b_rd[ADDR_WIDTH-1:0] == wrptr_b_wr_next[ADDR_WIDTH-1:0]) &&
                       (rdptr_b_rd[ADDR_WIDTH] != wrptr_b_wr_next[ADDR_WIDTH]) )
                    wrfull <= 1'b1 ;
                  else
                    wrfull <= 1'b0 ;
               end
             else
               begin
                  wrptr_g_wr  <= bin2gray(wrptr_b_wr) ;
                  rdptr_b_wr  <= gray2bin(rdptr_g_wr2) ;
                  rdptr_g_wr2 <= rdptr_g_wr1 ;
                  rdptr_g_wr1 <= rdptr_g_rd ;
                  wrusedw <= wrptr_b_wr_next[ADDR_WIDTH:0] - rdptr_b_wr[ADDR_WIDTH:0] ;

                  if ( (rdptr_b_wr[ADDR_WIDTH-1:0] == wrptr_b_wr_next[ADDR_WIDTH-1:0]) &&
                       (rdptr_b_wr[ADDR_WIDTH] != wrptr_b_wr_next[ADDR_WIDTH]) )
                    wrfull <= 1'b1 ;
                  else
                    wrfull <= 1'b0 ;
               end
          end
     end


   always @(posedge rdclk)
     begin
        if (rdvalid_next)
          q_reg <= q_ram ;
        else
          q_reg <= q_reg ;
     end

   assign q = (USE_RAM_OUTPUT_REGISTER == 1) ? q_ram : q_reg ;














































   always @(posedge rdclk or posedge aclr)
     begin
        if (aclr)
          ra_held <= 1'b1 ;
        else
          ra_held <= ra_held_next ;
     end


   always @(wrptr_b_rd,rdptr_b_rd,rdptr_b_rd_next,rdvalid_next,ra_held)
     begin
        if (USE_RAM_OUTPUT_REGISTER == 1)
          begin


             if (rdvalid_next == 1'b1)
               begin


                  if (wrptr_b_rd == rdptr_b_rd_next)
                    begin

                       rdaddress = rdptr_b_rd[ADDR_WIDTH-1:0] ;
                       ra_held_next = 1'b1 ;
                    end
                  else
                    begin

                       rdaddress = rdptr_b_rd_next[ADDR_WIDTH-1:0] ;
                       ra_held_next = 1'b0 ;
                    end

                  rdclocken = 1'b1 ;
               end
             else
               begin



                  if ( (wrptr_b_rd != rdptr_b_rd) &&
                       (ra_held == 1'b1) )
                    begin





                       ra_held_next = 1'b0 ;
                       rdaddress = rdptr_b_rd_next[ADDR_WIDTH-1:0] ;
                       rdclocken = 1'b1 ;
                    end
                  else
                    begin

                       ra_held_next = ra_held ;
                       rdaddress = rdptr_b_rd_next[ADDR_WIDTH-1:0] ;
                       rdclocken = 1'b0 ;
                    end
               end
          end
        else
          begin



             rdaddress    = rdptr_b_rd_next[ADDR_WIDTH-1:0] ;
             rdclocken    = 1'b1 ;
             ra_held_next = 1'b0 ;
          end
     end

dp_ram
#
(
	.DATA_WIDTH(DATA_WIDTH),
	.MEM_SIZE(1<<ADDR_WIDTH)
)
fifo_ram
(
	.data(data),
	.rdaddress(rdaddress),
	.rdclock(rdclk),
	.wraddress(wrptr_b_wr[ADDR_WIDTH-1:0]),
	.wrclock(wrclk),
	.wren(wrreq_allow),
	.q(q_ram)
);
endmodule
module lite_fifo
  #(
    parameter COMMON_CLOCK = 0 ,
    parameter ADDR_WIDTH = 8 ,
    parameter DATA_WIDTH = 32 ,
    parameter USE_RAM_OUTPUT_REGISTER = 0
    )
    (
     input rdclk ,
     input wrclk ,
     input aclr ,
     input wrreq ,
     input rdreq ,
     input [DATA_WIDTH-1 : 0] data ,
     output reg rdempty ,
     output reg wrfull ,
     output reg rdvalid ,
     output reg [ADDR_WIDTH : 0] rdusedw ,
     output reg [ADDR_WIDTH : 0] wrusedw ,
     output [DATA_WIDTH-1 : 0] q
     ) ;



   localparam                   OUTDATA_REG_B = (USE_RAM_OUTPUT_REGISTER == 1) ?
                               "CLOCK1" : "UNREGISTERED" ;

   reg [ADDR_WIDTH:0]          wrptr_b_wr_next ;
   reg [ADDR_WIDTH:0]          wrptr_b_wr ;
   reg [ADDR_WIDTH:0]          wrptr_g_wr ;
   reg [ADDR_WIDTH:0]          wrptr_g_rd1 ;
   reg [ADDR_WIDTH:0]          wrptr_g_rd2 ;
   reg [ADDR_WIDTH:0]          wrptr_b_rd_next ;
   reg [ADDR_WIDTH:0]          wrptr_b_rd ;
   reg [ADDR_WIDTH:0]          rdptr_b_rd_next ;
   reg [ADDR_WIDTH:0]          rdptr_b_rd ;
   reg [ADDR_WIDTH:0]          rdptr_g_rd ;
   reg [ADDR_WIDTH:0]          rdptr_g_wr1 ;
   reg [ADDR_WIDTH:0]          rdptr_g_wr2 ;
   reg [ADDR_WIDTH:0]          rdptr_b_wr ;
   reg                         wrreq_allow ;
   reg                         rdvalid_next ;
   reg                         rdclocken ;
   reg [ADDR_WIDTH-1:0]        rdaddress ;
   wire [DATA_WIDTH-1:0]       q_ram ;
   reg  [DATA_WIDTH-1:0]       q_reg ;

   reg                         ra_held ;
   reg                         ra_held_next ;

   function [ADDR_WIDTH:0] gray2bin
     ( input [ADDR_WIDTH:0] gray ) ;
      reg [ADDR_WIDTH:0] temp ;
      integer i ;
      begin
         temp[ADDR_WIDTH] = gray[ADDR_WIDTH] ;
         for (i = (ADDR_WIDTH-1); i >= 0 ; i = i - 1)
           begin
              temp[i] = temp[i+1] ^ gray[i] ;
           end
         gray2bin = temp ;
      end
   endfunction

   function [ADDR_WIDTH:0] bin2gray
     (input [ADDR_WIDTH:0] bin ) ;
      integer i ;
      begin
         bin2gray[ADDR_WIDTH] = bin[ADDR_WIDTH] ;
         for (i = 0 ; i < (ADDR_WIDTH) ; i = i + 1)
           begin
             bin2gray[i] = bin[i+1] ^ bin[i] ;
           end
      end
   endfunction

   


   always @(rdptr_b_rd,wrptr_b_rd,rdreq,ra_held)
     begin


        if ( (rdreq == 1'b1) && (rdptr_b_rd != wrptr_b_rd) && (ra_held == 1'b0) )
          begin

             rdptr_b_rd_next = rdptr_b_rd + 1'b1 ;
             rdvalid_next = 1'b1 ;
          end
        else
          begin

             rdptr_b_rd_next = rdptr_b_rd ;
             rdvalid_next = 1'b0 ;
          end
     end


   always @(wrptr_b_wr,wrptr_g_rd2)
     begin
        if (COMMON_CLOCK == 1)
          begin


             wrptr_b_rd_next  = wrptr_b_wr ;
          end
        else
          begin
             wrptr_b_rd_next = gray2bin(wrptr_g_rd2) ;
          end
     end

   always @(posedge rdclk or posedge aclr)
     begin
        if (aclr)
          begin
             rdptr_b_rd  <= {ADDR_WIDTH{1'b0}} ;
             rdptr_g_rd  <= {ADDR_WIDTH{1'b0}} ;
             wrptr_g_rd1 <= {ADDR_WIDTH{1'b0}} ;
             wrptr_g_rd2 <= {ADDR_WIDTH{1'b0}} ;
             wrptr_b_rd  <= {ADDR_WIDTH{1'b0}} ;
             rdusedw     <= {ADDR_WIDTH{1'b0}} ;
             rdempty     <= 1'b1 ;
             rdvalid     <= 1'b0 ;
          end
        else
          begin
             rdptr_b_rd <= rdptr_b_rd_next ;
             if (COMMON_CLOCK == 1)
               begin

                  rdptr_g_rd  <= {ADDR_WIDTH{1'b0}} ;
                  wrptr_g_rd1 <= {ADDR_WIDTH{1'b0}} ;
                  wrptr_g_rd2 <= {ADDR_WIDTH{1'b0}} ;
               end
             else
               begin
                  rdptr_g_rd <= bin2gray(rdptr_b_rd) ;
                  wrptr_b_rd <= gray2bin(wrptr_g_rd2) ;
                  wrptr_g_rd2 <= wrptr_g_rd1 ;
                  wrptr_g_rd1 <= wrptr_g_wr ;
               end

             wrptr_b_rd <= wrptr_b_rd_next ;



             if (ra_held == 1'b1)
               rdusedw <= {(ADDR_WIDTH+1){1'b0}} ;
             else
               rdusedw <= wrptr_b_rd[ADDR_WIDTH:0] - rdptr_b_rd_next[ADDR_WIDTH:0] ;
             if (wrptr_b_rd == rdptr_b_rd_next)
               rdempty <= 1'b1 ;
             else
               rdempty <= ra_held ;
             rdvalid <= rdvalid_next ;
          end
     end


   always @(rdptr_b_wr,rdptr_b_rd,wrptr_b_wr,wrreq)
     begin
        if (COMMON_CLOCK == 0)
          begin
             if ( (wrreq == 1'b1) &&
                  ( (rdptr_b_wr[ADDR_WIDTH-1:0] != wrptr_b_wr[ADDR_WIDTH-1:0]) ||
                    (rdptr_b_wr[ADDR_WIDTH]     == wrptr_b_wr[ADDR_WIDTH]) ) )
               begin

                  wrptr_b_wr_next = wrptr_b_wr + 1'b1 ;
                  wrreq_allow = 1'b1 ;
               end
             else
               begin

                  wrptr_b_wr_next = wrptr_b_wr ;
                  wrreq_allow = 1'b0 ;
               end
          end
        else
          begin


             if ( (wrreq == 1'b1) &&
                  ( (rdptr_b_rd[ADDR_WIDTH-1:0] != wrptr_b_wr[ADDR_WIDTH-1:0]) ||
                    (rdptr_b_rd[ADDR_WIDTH]     == wrptr_b_wr[ADDR_WIDTH]) ) )
               begin

                  wrptr_b_wr_next = wrptr_b_wr + 1'b1 ;
                  wrreq_allow = 1'b1 ;
               end
             else
               begin

                  wrptr_b_wr_next = wrptr_b_wr ;
                  wrreq_allow = 1'b0 ;
               end
          end
     end

   always @(posedge wrclk or posedge aclr)
     begin
        if (aclr)
          begin
             wrptr_b_wr  <= {ADDR_WIDTH{1'b0}} ;
             wrptr_g_wr  <= {ADDR_WIDTH{1'b0}} ;
             rdptr_g_wr1 <= {ADDR_WIDTH{1'b0}} ;
             rdptr_g_wr2 <= {ADDR_WIDTH{1'b0}} ;
             rdptr_b_wr  <= {ADDR_WIDTH{1'b0}} ;
             wrusedw     <= {ADDR_WIDTH{1'b0}} ;
             wrfull      <= 1'b0 ;
          end
        else
          begin
             wrptr_b_wr <= wrptr_b_wr_next ;
             if (COMMON_CLOCK == 1)
               begin


                  wrptr_g_wr  <= {ADDR_WIDTH{1'b0}} ;
                  rdptr_g_wr1 <= {ADDR_WIDTH{1'b0}} ;
                  rdptr_g_wr2 <= {ADDR_WIDTH{1'b0}} ;
                  rdptr_b_wr  <= {ADDR_WIDTH{1'b0}} ;


                  wrusedw <= wrptr_b_wr_next[ADDR_WIDTH:0] - rdptr_b_rd[ADDR_WIDTH:0] ;

                  if ( (rdptr_b_rd[ADDR_WIDTH-1:0] == wrptr_b_wr_next[ADDR_WIDTH-1:0]) &&
                       (rdptr_b_rd[ADDR_WIDTH] != wrptr_b_wr_next[ADDR_WIDTH]) )
                    wrfull <= 1'b1 ;
                  else
                    wrfull <= 1'b0 ;
               end
             else
               begin
                  wrptr_g_wr  <= bin2gray(wrptr_b_wr) ;
                  rdptr_b_wr  <= gray2bin(rdptr_g_wr2) ;
                  rdptr_g_wr2 <= rdptr_g_wr1 ;
                  rdptr_g_wr1 <= rdptr_g_rd ;
                  wrusedw <= wrptr_b_wr_next[ADDR_WIDTH:0] - rdptr_b_wr[ADDR_WIDTH:0] ;

                  if ( (rdptr_b_wr[ADDR_WIDTH-1:0] == wrptr_b_wr_next[ADDR_WIDTH-1:0]) &&
                       (rdptr_b_wr[ADDR_WIDTH] != wrptr_b_wr_next[ADDR_WIDTH]) )
                    wrfull <= 1'b1 ;
                  else
                    wrfull <= 1'b0 ;
               end
          end
     end


   always @(posedge rdclk)
     begin
        if (rdvalid_next)
          q_reg <= q_ram ;
        else
          q_reg <= q_reg ;
     end

   assign q = (USE_RAM_OUTPUT_REGISTER == 1) ? q_ram : q_reg ;














































   always @(posedge rdclk or posedge aclr)
     begin
        if (aclr)
          ra_held <= 1'b1 ;
        else
          ra_held <= ra_held_next ;
     end


   always @(wrptr_b_rd,rdptr_b_rd,rdptr_b_rd_next,rdvalid_next,ra_held)
     begin
        if (USE_RAM_OUTPUT_REGISTER == 1)
          begin


             if (rdvalid_next == 1'b1)
               begin


                  if (wrptr_b_rd == rdptr_b_rd_next)
                    begin

                       rdaddress = rdptr_b_rd[ADDR_WIDTH-1:0] ;
                       ra_held_next = 1'b1 ;
                    end
                  else
                    begin

                       rdaddress = rdptr_b_rd_next[ADDR_WIDTH-1:0] ;
                       ra_held_next = 1'b0 ;
                    end

                  rdclocken = 1'b1 ;
               end
             else
               begin



                  if ( (wrptr_b_rd != rdptr_b_rd) &&
                       (ra_held == 1'b1) )
                    begin





                       ra_held_next = 1'b0 ;
                       rdaddress = rdptr_b_rd_next[ADDR_WIDTH-1:0] ;
                       rdclocken = 1'b1 ;
                    end
                  else
                    begin

                       ra_held_next = ra_held ;
                       rdaddress = rdptr_b_rd_next[ADDR_WIDTH-1:0] ;
                       rdclocken = 1'b0 ;
                    end
               end
          end
        else
          begin



             rdaddress    = rdptr_b_rd_next[ADDR_WIDTH-1:0] ;
             rdclocken    = 1'b1 ;
             ra_held_next = 1'b0 ;
          end
     end

dp_ram
#
(
	.DATA_WIDTH(DATA_WIDTH),
	.MEM_SIZE(1<<ADDR_WIDTH)
)
fifo_ram
(
	.data(data),
	.rdaddress(rdaddress),
	.rdclock(rdclk),
	.wraddress(wrptr_b_wr[ADDR_WIDTH-1:0]),
	.wrclock(wrclk),
	.wren(wrreq_allow),
	.q(q_ram)
);
endmodule