data/full_repos/permissive/201488448/2_circuits/2_sequential/25_countbcd.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/25_countbcd.v:42: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                 : ... In instance top_module.c1000\n            q <= 4'd0;\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/25_countbcd.v:45: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                 : ... In instance top_module.c1000\n                q <= 4'd0;\n                ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/25_countbcd.v:47: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                 : ... In instance top_module.c1000\n                q <= q + 1'b1;\n                ^\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module bcd(input clk, input reset, input enable, output [3:0]	q);
    always@(posedge clk) begin
        if(reset)
            q <= 4'd0;
        else if(enable) begin
            if(q == 9)
                q <= 4'd0;
            else
                q <= q + 1'b1;
        end
    end
    
endmodule
module bcd(input clk, input reset, input enable, output [3:0]	q);

    always@(posedge clk) begin
        if(reset)
            q <= 4'd0;
        else if(enable) begin
            if(q == 9)
                q <= 4'd0;
            else
                q <= q + 1'b1;
        end
    end
    
endmodule