data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v
1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n             MBScore_const.v\n             MBScore_const.v.v\n             MBScore_const.v.sv\n             obj_dir/MBScore_const.v\n             obj_dir/MBScore_const.v.v\n             obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:6: Define or directive not defined: \'`IMM_WIDTH\'\n    input [`IMM_WIDTH-1:0]              imm,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:7: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n    input [`ALU_SEL_WIDTH-1:0]   alu_sel_a,\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:8: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n input [`ALU_SEL_WIDTH-1:0]   alu_sel_b,\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:9: Define or directive not defined: \'`DATA_WIDTH\'\n    input [`DATA_WIDTH-1:0]             rs,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:10: Define or directive not defined: \'`DATA_WIDTH\'\n    input [`DATA_WIDTH-1:0]             rt,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:11: Define or directive not defined: \'`DATA_WIDTH\'\n    output [`DATA_WIDTH-1:0]            alu_a,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:12: Define or directive not defined: \'`DATA_WIDTH\'\n    output [`DATA_WIDTH-1:0]            alu_b\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:15: Define or directive not defined: \'`DATA_WIDTH\'\n    reg [`DATA_WIDTH-1:0]               alu_a_r,alu_b_r;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:21: Define or directive not defined: \'`ALU_SEL_IMM\'\n            alu_a_r <= (alu_sel_a == `ALU_SEL_IMM)? {16\'b0,imm} : rs;\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:21: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            alu_a_r <= (alu_sel_a == `ALU_SEL_IMM)? {16\'b0,imm} : rs;\n                                                 ^\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:22: Define or directive not defined: \'`ALU_SEL_IMM\'\n            alu_b_r <= (alu_sel_b == `ALU_SEL_IMM)? {16\'b0,imm} : rt;\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:22: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            alu_b_r <= (alu_sel_b == `ALU_SEL_IMM)? {16\'b0,imm} : rt;\n                                                 ^\n%Error: Exiting due to 13 error(s)\n'
module MBScore_alu_operator_mux(
    input                               clk,
    input                               alu_mux_ack,
    input [`IMM_WIDTH-1:0]              imm,
    input [`ALU_SEL_WIDTH-1:0]			alu_sel_a,
	input [`ALU_SEL_WIDTH-1:0]			alu_sel_b,
    input [`DATA_WIDTH-1:0]             rs,
    input [`DATA_WIDTH-1:0]             rt,
    output [`DATA_WIDTH-1:0]            alu_a,
    output [`DATA_WIDTH-1:0]            alu_b
);

    reg [`DATA_WIDTH-1:0]               alu_a_r,alu_b_r;

    always @(negedge clk)
    begin
        if(alu_mux_ack)
        begin
            alu_a_r <= (alu_sel_a == `ALU_SEL_IMM)? {16'b0,imm} : rs;
            alu_b_r <= (alu_sel_b == `ALU_SEL_IMM)? {16'b0,imm} : rt;
        end
    end

    assign alu_a = alu_a_r;
    assign alu_b = alu_b_r;

endmodule
module MBScore_alu_operator_mux(
    input                               clk,
    input                               alu_mux_ack,
    input [`IMM_WIDTH-1:0]              imm,
    input [`ALU_SEL_WIDTH-1:0]			alu_sel_a,
	input [`ALU_SEL_WIDTH-1:0]			alu_sel_b,
    input [`DATA_WIDTH-1:0]             rs,
    input [`DATA_WIDTH-1:0]             rt,
    output [`DATA_WIDTH-1:0]            alu_a,
    output [`DATA_WIDTH-1:0]            alu_b
);


    reg [`DATA_WIDTH-1:0]               alu_a_r,alu_b_r;

    always @(negedge clk)
    begin
        if(alu_mux_ack)
        begin
            alu_a_r <= (alu_sel_a == `ALU_SEL_IMM)? {16'b0,imm} : rs;
            alu_b_r <= (alu_sel_b == `ALU_SEL_IMM)? {16'b0,imm} : rt;
        end
    end

    assign alu_a = alu_a_r;
    assign alu_b = alu_b_r;

endmodule