data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:60: Cannot find include file: tap_defines.v\n`include "tap_defines.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system,data/full_repos/permissive/17099167/tap_defines.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system,data/full_repos/permissive/17099167/tap_defines.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system,data/full_repos/permissive/17099167/tap_defines.v.sv\n             tap_defines.v\n             tap_defines.v.v\n             tap_defines.v.sv\n             obj_dir/tap_defines.v\n             obj_dir/tap_defines.v.v\n             obj_dir/tap_defines.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:61: Cannot find include file: adbg_defines.v\n`include "adbg_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:62: Cannot find include file: adbg_wb_defines.v\n`include "adbg_wb_defines.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:63: Cannot find include file: wb_model_defines.v\n`include "wb_model_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:198: Define or directive not defined: \'`ACK_RESPONSE\'\n  i_wb.cycle_response(`ACK_RESPONSE, 2, 0);   \n                      ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n  #1 test_enabled<=#1 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:210: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:212: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:215: Define or directive not defined: \'`DEBUG\'\n  set_ir(`DEBUG);\n         ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:216: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:640: Define or directive not defined: \'`IDCODE\'\n    set_ir(`IDCODE);\n           ^~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:650: Define or directive not defined: \'`IDCODE_VALUE\'\n    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);\n                                                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:650: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);\n                                                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:706: Define or directive not defined: \'`DBG_WB_CMD_IREG_SEL\'\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);\n                               ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:706: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);\n                                                    ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:749: Define or directive not defined: \'`DBG_WB_CMD_IREG_WR\'\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));\n                               ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:749: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));\n                                                   ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:782: Define or directive not defined: \'`DBG_WB_CMD_BREAD8\'\n       3\'h1: opcode = `DBG_WB_CMD_BREAD8;\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:782: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h1: opcode = `DBG_WB_CMD_BREAD8;\n                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:783: Define or directive not defined: \'`DBG_WB_CMD_BREAD16\'\n       3\'h2: opcode = `DBG_WB_CMD_BREAD16;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:783: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h2: opcode = `DBG_WB_CMD_BREAD16;\n                                         ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:784: Define or directive not defined: \'`DBG_WB_CMD_BREAD32\'\n       3\'h4: opcode = `DBG_WB_CMD_BREAD32;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:784: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h4: opcode = `DBG_WB_CMD_BREAD32;\n                                         ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:788: Define or directive not defined: \'`DBG_WB_CMD_BREAD32\'\n           opcode = `DBG_WB_CMD_BREAD32;\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:788: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n           opcode = `DBG_WB_CMD_BREAD32;\n                                       ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:873: Define or directive not defined: \'`DBG_WB_CMD_BWRITE8\'\n       3\'h1: opcode = `DBG_WB_CMD_BWRITE8;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:873: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h1: opcode = `DBG_WB_CMD_BWRITE8;\n                                         ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:874: Define or directive not defined: \'`DBG_WB_CMD_BWRITE16\'\n       3\'h2: opcode = `DBG_WB_CMD_BWRITE16;\n                      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:874: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h2: opcode = `DBG_WB_CMD_BWRITE16;\n                                          ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:875: Define or directive not defined: \'`DBG_WB_CMD_BWRITE32\'\n       3\'h4: opcode = `DBG_WB_CMD_BWRITE32;\n                      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:875: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h4: opcode = `DBG_WB_CMD_BWRITE32;\n                                          ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:879: Define or directive not defined: \'`DBG_WB_CMD_BWRITE32\'\n           opcode = `DBG_WB_CMD_BWRITE32;\n                    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:879: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n           opcode = `DBG_WB_CMD_BWRITE32;\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:1027: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:1031: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:1035: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:1049: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:1053: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/simulated_system/adv_dbg_tb.v:1057: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Error: Exiting due to 29 error(s), 12 warning(s)\n'
module adv_debug_tb; 


reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;


wire capture_dr;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire dbg_rst;
wire dbg_tdi;
wire dbg_tdo;
wire dbg_sel;


`ifdef DBG_WISHBONE_SUPPORTED
wire [31:0] wb_adr;
wire [31:0] wb_dat_m;
wire [31:0] wb_dat_s;
wire wb_cyc;
wire wb_stb;
wire [3:0] wb_sel;
wire wb_we;
wire wb_ack;
wire wb_err;
reg wb_clk_i;
reg wb_rst_i;
`endif

`ifdef DBG_CPU0_SUPPORTED
wire cpu0_clk;
wire [31:0]cpu0_addr;
wire [31:0] cpu0_data_c;
wire [31:0] cpu0_data_d;
wire cpu0_bp;
wire cpu0_stall;
wire cpu0_stb;
wire cpu0_we;
wire cpu0_ack;
wire cpu0_rst;
`endif

`ifdef DBG_CPU1_SUPPORTED
reg cpu1_clk;
wire [31:0]cpu1_addr;
wire [31:0] cpu1_data_c;
wire [31:0] cpu1_data_d;
wire cpu1_bp;
wire cpu1_stall;
wire cpu1_stb;
wire cpu1_we;
wire cpu1_ack;
wire cpu1_rst;
`endif
   
reg test_enabled;


reg [31:0] static_data32 [0:15]; 
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];


reg [31:0] input_data32 [0:15]; 
reg [15:0] input_data16 [0:15];
reg [7:0]  input_data8 [0:15];                                

reg [32:0] err_data;

reg failed;
integer i;

initial
begin
   jtag_tck_o = 1'b0;
   jtag_tms_o = 1'b0;
   jtag_tdo_o = 1'b0;
end


`ifdef DBG_WISHBONE_SUPPORTED
initial
begin
  wb_clk_i = 1'b0;
  forever #7 wb_clk_i = ~wb_clk_i;
end
`endif











initial
begin
  test_enabled = 1'b0;
  wb_rst_i = 1'b0;
  #100;
  wb_rst_i = 1'b1;
  #100;
  wb_rst_i = 1'b0;


  initialize_memory(32'h0,32'h16);
  

  i_wb.cycle_response(`ACK_RESPONSE, 2, 0);

  #1 test_enabled<=#1 1'b1;
end


always @ (posedge test_enabled)
begin

  $display("Starting advanced debug test");
  
  reset_jtag;
  #1000;
  check_idcode;
  #1000;
  

  set_ir(`DEBUG);
  #1000;
  
  



`ifdef DBG_CPU0_SUPPORTED

  #1000; 
  $display("Selecting CPU0 module at time %t", $time);
  select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);


   #1000;
   $display("Testing CPU0 intreg select at time %t", $time);
   select_module_internal_register(32'h1, 1);
   #1000;
   select_module_internal_register(32'h0, 1);
   #1000;
    

   $display("Testing reset and stall bits at time %t", $time);
   read_module_internal_register(8'd2, err_data);
   $display("Reset and stall bits are %x", err_data);
   #1000;
    

   $display("Setting reset and stall bits at time %t", $time);    
    write_module_internal_register(32'h0, 8'h1, 32'h3, 8'h2);
   #1000;
   

   $display("Testing reset and stall bits again at time %t", $time);
   read_module_internal_register(8'd2, err_data);
   $display("Reset and stall bits are %x", err_data);
   #1000;
   

      $display("Clearing reset and stall bits at time %t", $time);    
    write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2);
   #1000;
   

   $display("Testing reset and stall bits again at time %t", $time);
   read_module_internal_register(8'd2, err_data);
   $display("Reset and stall bits are %x", err_data);
   #1000;
   


   write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2);
   #1000;
   

  $display("Testing CPU0 32-bit burst write at time %t", $time);
  do_module_burst_write(3'h4, 16'd16, 32'h10);
  #1000;
  $display("Testing CPU0 32-bit burst read at time %t", $time);
  do_module_burst_read(3'h4, 16'd16, 32'h0);
  #1000;

`endif

  



  
`ifdef DBG_WISHBONE_SUPPORTED

  #1000; 
  $display("Selecting Wishbone module at time %t", $time);
  select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  

    

    


  failed = 0;
  $display("Testing WB 8-bit burst write at time %t: resetting ", $time);
  do_module_burst_write(3'h1, 16'd16, 32'h0);
  #1000;
  $display("Testing WB 8-bit burst read at time %t", $time);
  do_module_burst_read(3'h1, 16'd16, 32'h0);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data8[i] != input_data8[i]) begin 
        failed = 1;
        $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]);
    end
  end
  if(!failed) $display("8-bit read/write OK!");
  

  


  failed = 0;
  $display("Testing WB 16-bit burst write at time %t", $time);
  do_module_burst_write(3'h2, 16'd16, 32'h0);
  #1000;
  $display("Testing WB 16-bit burst read at time %t", $time);
  do_module_burst_read(3'h2, 16'd16, 32'h0);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data16[i] != input_data16[i]) begin 
        failed = 1;
        $display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]);
    end
  end
  if(!failed) $display("16-bit read/write OK!");
  

  


  failed = 0;
  $display("Testing WB 32-bit burst write at time %t", $time);
  do_module_burst_write(3'h4, 16'd16, 32'h0);
  #1000;
  $display("Testing WB 32-bit burst read at time %t", $time);
  do_module_burst_read(3'h4, 16'd16, 32'h0);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data32[i] != input_data32[i]) begin 
        failed = 1;
        $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]);
    end
  end
  if(!failed) $display("32-bit read/write OK!");
    

  


  err_data = 33'h0;

  write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1);
  i_wb.cycle_response(`ERR_RESPONSE, 2, 0);
  do_module_burst_write(3'h4, 16'd4, 32'hdeaddead);
  read_module_internal_register(8'd33, err_data);
  $display("Error bit is %d, error address is %x", err_data[0], err_data>>1);

`endif
  
end

task initialize_memory;
  input [31:0] start_addr;
  input [31:0] length;
  integer i;
  reg [31:0] addr;
  begin

    for (i=0; i<length; i=i+1)
      begin
        static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
        static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
        static_data8[i] <= i[7:0];
      end
  end
endtask





tap_top  i_tap (

                .tms_pad_i(jtag_tms_o), 
                .tck_pad_i(jtag_tck_o), 
                .trstn_pad_i(1'b1), 
                .tdi_pad_i(jtag_tdo_o), 
                .tdo_pad_o(jtag_tdi_i), 
                .tdo_padoe_o(),


				    .test_logic_reset_o(dbg_rst),
				    .run_test_idle_o(),
                .shift_dr_o(shift_dr),
                .pause_dr_o(pause_dr), 
                .update_dr_o(update_dr),
                .capture_dr_o(capture_dr),
                

                .extest_select_o(), 
                .sample_preload_select_o(),
                .mbist_select_o(),
                .debug_select_o(dbg_sel),
                

                .tdi_o(dbg_tdo), 
                

                .debug_tdo_i(dbg_tdi),
                .bs_chain_tdo_i(1'b0),
                .mbist_tdo_i(1'b0)
              );



adbg_top i_dbg_module(

                .tck_i(jtag_tck_o),
                .tdi_i(dbg_tdo),
                .tdo_o(dbg_tdi),
                .rst_i(dbg_rst),


                .shift_dr_i(shift_dr),
                .pause_dr_i(pause_dr),
                .update_dr_i(update_dr),
                .capture_dr_i(capture_dr),


                .debug_select_i(dbg_sel)


                `ifdef DBG_WISHBONE_SUPPORTED

                ,
                .wb_clk_i(wb_clk_i),
                                                                                

                .wb_adr_o(wb_adr),
                .wb_dat_o(wb_dat_m),
                .wb_dat_i(wb_dat_s),
                .wb_cyc_o(wb_cyc),
                .wb_stb_o(wb_stb),
                .wb_sel_o(wb_sel),
                .wb_we_o(wb_we),
                .wb_ack_i(wb_ack),
                .wb_cab_o(),
                .wb_err_i(wb_err),
                .wb_cti_o(),
                .wb_bte_o()
                `endif

                `ifdef DBG_CPU0_SUPPORTED

                ,
                .cpu0_clk_i(cpu0_clk),
                .cpu0_addr_o(cpu0_addr), 
                .cpu0_data_i(cpu0_data_c),
                .cpu0_data_o(cpu0_data_d),
                .cpu0_bp_i(cpu0_bp),
                .cpu0_stall_o(cpu0_stall),
                .cpu0_stb_o(cpu0_stb),
                .cpu0_we_o(cpu0_we),
                .cpu0_ack_i(cpu0_ack),
                .cpu0_rst_o(cpu0_rst)
                `endif

                `ifdef DBG_CPU1_SUPPORTED

                ,
                .cpu1_clk_i(cpu1_clk), 
                .cpu1_addr_o(cpu1_addr), 
                .cpu1_data_i(cpu1_data_c),
                .cpu1_data_o(cpu1_data_d),
                .cpu1_bp_i(cpu1_bp),
                .cpu1_stall_o(cpu1_stall),
                .cpu1_stb_o(cpu1_stb),
                .cpu1_we_o(cpu1_we),
                .cpu1_ack_i(cpu1_ack),
                .cpu1_rst_o(cpu1_rst)
                `endif

              );


`ifdef DBG_WISHBONE_SUPPORTED



wb_slave_behavioral i_wb
(
	.CLK_I(wb_clk_i),
	.RST_I(wb_rst_i),
	.ACK_O(wb_ack),
	.ADR_I(wb_adr),
	.CYC_I(wb_cyc),
	.DAT_O(wb_dat_s),
	.DAT_I(wb_dat_m),
	.ERR_O(wb_err),
	.RTY_O(),
	.SEL_I(wb_sel),
	.STB_I(wb_stb),
	.WE_I(wb_we),
	.CAB_I(1'b0)
);
`endif


`ifdef DBG_CPU0_SUPPORTED

cpu_behavioral cpu0_i  (
   .cpu_rst_i(cpu0_rst),
   .cpu_clk_o(cpu0_clk),
   .cpu_addr_i(cpu0_addr),
   .cpu_data_o(cpu0_data_c),
   .cpu_data_i(cpu0_data_d),
   .cpu_bp_o(cpu0_bp),
   .cpu_stall_i(cpu0_stall),
   .cpu_stb_i(cpu0_stb),
   .cpu_we_i(cpu0_we),
   .cpu_ack_o(cpu0_ack),
   .cpu_rst_o(cpu0_rst)
);

`endif


`ifdef DBG_CPU1_SUPPORTED

cpu_behavioral cpu1_i  (
		    .cpu_rst_i(cpu1_rst),
                    .cpu_clk_o(cpu1_clk),
                    .cpu_addr_i(cpu1_addr),
                    .cpu_data_o(cpu1_data_c),
                    .cpu_data_i(cpu1_data_d),
                    .cpu_bp_o(cpu1_bp),
                    .cpu_stall_i(cpu1_stall),
                    .cpu_stb_i(cpu1_stb),
                    .cpu_we_i(cpu1_we),
                    .cpu_ack_o(cpu1_ack),
                    .cpu_rst_o(cpu1_rst)
);
`endif
   




task compute_crc;
    input [31:0] crc_in;
    input [31:0] data_in;
    input [5:0] length_bits;
    output [31:0] crc_out;
    integer i;
    reg [31:0] d;
    reg [31:0] c;
    begin
        crc_out = crc_in;
        for(i = 0; i < length_bits; i = i+1) begin
           d = (data_in[i]) ? 32'hffffffff : 32'h0;
           c = (crc_out[0]) ? 32'hffffffff : 32'h0;

           crc_out = crc_out >> 1;
           crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);

        end
    end
endtask

task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
    set_ir(`IDCODE);
    

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_read_write_stream(64'h0, 8'd32, 1, readdata);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    idcode = readdata[31:0];
    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;

task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({1'b1,moduleid}, 8'h3, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    
    $display("Selecting module (%0x)", moduleid);
    


end
endtask


task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
    streamdata = {11'h0,1'b0,opcode,address,burstlength};
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, 8'd53, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask

task select_module_internal_register;
    input [31:0] regidx;
    input [7:0] len;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | regidx;
    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (len+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask
        

task read_module_internal_register;

    input [7:0] len;
    output [63:0] instream;
    reg [63:0] bitmask;
begin
    instream = 64'h0;

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);

    jtag_read_write_stream(64'h0, len+4,1,instream);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    bitmask = 64'hffffffffffffffff;
    bitmask = bitmask << len;
    bitmask = ~bitmask;
    instream = instream & bitmask;
end
endtask

task write_module_internal_register;
    input [31:0] regidx;
    input [7:0] idxlen;
    input [63:0] writedata;
    input [7:0] datalen;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | writedata;
    streamdata = streamdata | (regidx << datalen);
    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
    
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (idxlen+datalen+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin
    $display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
    instream = 64'h0;
    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BREAD8;
       3'h2: opcode = `DBG_WB_CMD_BREAD16;
       3'h4: opcode = `DBG_WB_CMD_BREAD32;
       default:
          begin
           $display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BREAD32;
          end
   endcase
   
   send_module_burst_command(opcode,start_address, word_count);
   

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);

`ifdef ADBG_USE_HISPEED

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      
      if(j > 1) begin
         $display("Took %0d tries before good status bit during burst read", j);
      end
`endif
   

   for(i = 0; i < word_count; i=i+1) begin
     
`ifndef ADBG_USE_HISPEED     

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      
      if(j > 1) begin
         $display("Took %0d tries before good status bit during burst read", j);
      end
`endif
  
     jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);

     compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
     crc_calc_i = crc_calc_o;
     if(word_size_bytes == 1) input_data8[i] = instream[7:0];
     else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
     else input_data32[i] = instream[31:0];
   end
    

   jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
   if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
   else $display("CRC OK!");
    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end
endtask


task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin
    $display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BWRITE8;
       3'h2: opcode = `DBG_WB_CMD_BWRITE16;
       3'h4: opcode = `DBG_WB_CMD_BWRITE32;
       default:
          begin
           $display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BWRITE32;
          end
   endcase
   
   send_module_burst_command(opcode, start_address, word_count);
   

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);
   


   write_bit(`JTAG_TDO_bit);


   for(i = 0; i < word_count; i=i+1) begin

      if(word_size_bytes == 4)      dataword = {32'h0, static_data32[i]};
      else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
      else                          dataword = {56'h0, static_data8[i]};
      
      
      jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
      compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
      crc_calc_i = crc_calc_o;
      
      
`ifndef ADBG_USE_HISPEED


      status = 1'b0;
      read_write_bit(3'h0, status);
      
      if(!status) begin
         $display("Bad status bit during burst write, index %d", i);
      end
`endif      
  

   end
    

   jtag_write_stream(crc_calc_o, 6'd32,0);
   

   read_write_bit(`JTAG_TMS_bit, crc_match);
   if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
   else $display("CRC OK!");
    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end

endtask




task set_ir;
input [3:0] irval;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({60'h0,irval}, 8'h4, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task reset_jtag;
integer i;
begin
   for(i = 0; i < 8; i=i+1) begin
      write_bit(`JTAG_TMS_bit);
   end
   write_bit(3'h0);
end
endtask





task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       write_bit(bits);
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   write_bit(bits);
    
end
endtask


task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
    instream = 64'h0;
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       read_write_bit(bits, inbit);
       instream = (instream | (inbit << i));
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   read_write_bit(bits, inbit);
   instream = (instream | (inbit << (len-1)));
end
endtask




task write_bit;
   input [2:0] bitvals;
   begin
       

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask

task read_write_bit;
   input [2:0] bitvals;
   output l_tdi_val;
   begin
       

   l_tdi_val <= jtag_tdi_i;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask




task jtag_out;
  input   [2:0]   bitvals;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 
   end
endtask


task jtag_inout;
  input   [2:0]   bitvals;
  output l_tdi_val;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 

   l_tdi_val <= jtag_tdi_i;
   end
endtask

endmodule
module adv_debug_tb;
 


reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;


wire capture_dr;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire dbg_rst;
wire dbg_tdi;
wire dbg_tdo;
wire dbg_sel;


`ifdef DBG_WISHBONE_SUPPORTED
wire [31:0] wb_adr;
wire [31:0] wb_dat_m;
wire [31:0] wb_dat_s;
wire wb_cyc;
wire wb_stb;
wire [3:0] wb_sel;
wire wb_we;
wire wb_ack;
wire wb_err;
reg wb_clk_i;
reg wb_rst_i;
`endif

`ifdef DBG_CPU0_SUPPORTED
wire cpu0_clk;
wire [31:0]cpu0_addr;
wire [31:0] cpu0_data_c;
wire [31:0] cpu0_data_d;
wire cpu0_bp;
wire cpu0_stall;
wire cpu0_stb;
wire cpu0_we;
wire cpu0_ack;
wire cpu0_rst;
`endif

`ifdef DBG_CPU1_SUPPORTED
reg cpu1_clk;
wire [31:0]cpu1_addr;
wire [31:0] cpu1_data_c;
wire [31:0] cpu1_data_d;
wire cpu1_bp;
wire cpu1_stall;
wire cpu1_stb;
wire cpu1_we;
wire cpu1_ack;
wire cpu1_rst;
`endif
   
reg test_enabled;


reg [31:0] static_data32 [0:15]; 
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];


reg [31:0] input_data32 [0:15]; 
reg [15:0] input_data16 [0:15];
reg [7:0]  input_data8 [0:15];                                

reg [32:0] err_data;

reg failed;
integer i;

initial
begin
   jtag_tck_o = 1'b0;
   jtag_tms_o = 1'b0;
   jtag_tdo_o = 1'b0;
end


`ifdef DBG_WISHBONE_SUPPORTED
initial
begin
  wb_clk_i = 1'b0;
  forever #7 wb_clk_i = ~wb_clk_i;
end
`endif











initial
begin
  test_enabled = 1'b0;
  wb_rst_i = 1'b0;
  #100;
  wb_rst_i = 1'b1;
  #100;
  wb_rst_i = 1'b0;


  initialize_memory(32'h0,32'h16);
  

  i_wb.cycle_response(`ACK_RESPONSE, 2, 0);

  #1 test_enabled<=#1 1'b1;
end


always @ (posedge test_enabled)
begin

  $display("Starting advanced debug test");
  
  reset_jtag;
  #1000;
  check_idcode;
  #1000;
  

  set_ir(`DEBUG);
  #1000;
  
  



`ifdef DBG_CPU0_SUPPORTED

  #1000; 
  $display("Selecting CPU0 module at time %t", $time);
  select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);


   #1000;
   $display("Testing CPU0 intreg select at time %t", $time);
   select_module_internal_register(32'h1, 1);
   #1000;
   select_module_internal_register(32'h0, 1);
   #1000;
    

   $display("Testing reset and stall bits at time %t", $time);
   read_module_internal_register(8'd2, err_data);
   $display("Reset and stall bits are %x", err_data);
   #1000;
    

   $display("Setting reset and stall bits at time %t", $time);    
    write_module_internal_register(32'h0, 8'h1, 32'h3, 8'h2);
   #1000;
   

   $display("Testing reset and stall bits again at time %t", $time);
   read_module_internal_register(8'd2, err_data);
   $display("Reset and stall bits are %x", err_data);
   #1000;
   

      $display("Clearing reset and stall bits at time %t", $time);    
    write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2);
   #1000;
   

   $display("Testing reset and stall bits again at time %t", $time);
   read_module_internal_register(8'd2, err_data);
   $display("Reset and stall bits are %x", err_data);
   #1000;
   


   write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2);
   #1000;
   

  $display("Testing CPU0 32-bit burst write at time %t", $time);
  do_module_burst_write(3'h4, 16'd16, 32'h10);
  #1000;
  $display("Testing CPU0 32-bit burst read at time %t", $time);
  do_module_burst_read(3'h4, 16'd16, 32'h0);
  #1000;

`endif

  



  
`ifdef DBG_WISHBONE_SUPPORTED

  #1000; 
  $display("Selecting Wishbone module at time %t", $time);
  select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
  

    

    


  failed = 0;
  $display("Testing WB 8-bit burst write at time %t: resetting ", $time);
  do_module_burst_write(3'h1, 16'd16, 32'h0);
  #1000;
  $display("Testing WB 8-bit burst read at time %t", $time);
  do_module_burst_read(3'h1, 16'd16, 32'h0);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data8[i] != input_data8[i]) begin 
        failed = 1;
        $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]);
    end
  end
  if(!failed) $display("8-bit read/write OK!");
  

  


  failed = 0;
  $display("Testing WB 16-bit burst write at time %t", $time);
  do_module_burst_write(3'h2, 16'd16, 32'h0);
  #1000;
  $display("Testing WB 16-bit burst read at time %t", $time);
  do_module_burst_read(3'h2, 16'd16, 32'h0);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data16[i] != input_data16[i]) begin 
        failed = 1;
        $display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]);
    end
  end
  if(!failed) $display("16-bit read/write OK!");
  

  


  failed = 0;
  $display("Testing WB 32-bit burst write at time %t", $time);
  do_module_burst_write(3'h4, 16'd16, 32'h0);
  #1000;
  $display("Testing WB 32-bit burst read at time %t", $time);
  do_module_burst_read(3'h4, 16'd16, 32'h0);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data32[i] != input_data32[i]) begin 
        failed = 1;
        $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]);
    end
  end
  if(!failed) $display("32-bit read/write OK!");
    

  


  err_data = 33'h0;

  write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1);
  i_wb.cycle_response(`ERR_RESPONSE, 2, 0);
  do_module_burst_write(3'h4, 16'd4, 32'hdeaddead);
  read_module_internal_register(8'd33, err_data);
  $display("Error bit is %d, error address is %x", err_data[0], err_data>>1);

`endif
  
end

task initialize_memory;
  input [31:0] start_addr;
  input [31:0] length;
  integer i;
  reg [31:0] addr;
  begin

    for (i=0; i<length; i=i+1)
      begin
        static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
        static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
        static_data8[i] <= i[7:0];
      end
  end
endtask





tap_top  i_tap (

                .tms_pad_i(jtag_tms_o), 
                .tck_pad_i(jtag_tck_o), 
                .trstn_pad_i(1'b1), 
                .tdi_pad_i(jtag_tdo_o), 
                .tdo_pad_o(jtag_tdi_i), 
                .tdo_padoe_o(),


				    .test_logic_reset_o(dbg_rst),
				    .run_test_idle_o(),
                .shift_dr_o(shift_dr),
                .pause_dr_o(pause_dr), 
                .update_dr_o(update_dr),
                .capture_dr_o(capture_dr),
                

                .extest_select_o(), 
                .sample_preload_select_o(),
                .mbist_select_o(),
                .debug_select_o(dbg_sel),
                

                .tdi_o(dbg_tdo), 
                

                .debug_tdo_i(dbg_tdi),
                .bs_chain_tdo_i(1'b0),
                .mbist_tdo_i(1'b0)
              );



adbg_top i_dbg_module(

                .tck_i(jtag_tck_o),
                .tdi_i(dbg_tdo),
                .tdo_o(dbg_tdi),
                .rst_i(dbg_rst),


                .shift_dr_i(shift_dr),
                .pause_dr_i(pause_dr),
                .update_dr_i(update_dr),
                .capture_dr_i(capture_dr),


                .debug_select_i(dbg_sel)


                `ifdef DBG_WISHBONE_SUPPORTED

                ,
                .wb_clk_i(wb_clk_i),
                                                                                

                .wb_adr_o(wb_adr),
                .wb_dat_o(wb_dat_m),
                .wb_dat_i(wb_dat_s),
                .wb_cyc_o(wb_cyc),
                .wb_stb_o(wb_stb),
                .wb_sel_o(wb_sel),
                .wb_we_o(wb_we),
                .wb_ack_i(wb_ack),
                .wb_cab_o(),
                .wb_err_i(wb_err),
                .wb_cti_o(),
                .wb_bte_o()
                `endif

                `ifdef DBG_CPU0_SUPPORTED

                ,
                .cpu0_clk_i(cpu0_clk),
                .cpu0_addr_o(cpu0_addr), 
                .cpu0_data_i(cpu0_data_c),
                .cpu0_data_o(cpu0_data_d),
                .cpu0_bp_i(cpu0_bp),
                .cpu0_stall_o(cpu0_stall),
                .cpu0_stb_o(cpu0_stb),
                .cpu0_we_o(cpu0_we),
                .cpu0_ack_i(cpu0_ack),
                .cpu0_rst_o(cpu0_rst)
                `endif

                `ifdef DBG_CPU1_SUPPORTED

                ,
                .cpu1_clk_i(cpu1_clk), 
                .cpu1_addr_o(cpu1_addr), 
                .cpu1_data_i(cpu1_data_c),
                .cpu1_data_o(cpu1_data_d),
                .cpu1_bp_i(cpu1_bp),
                .cpu1_stall_o(cpu1_stall),
                .cpu1_stb_o(cpu1_stb),
                .cpu1_we_o(cpu1_we),
                .cpu1_ack_i(cpu1_ack),
                .cpu1_rst_o(cpu1_rst)
                `endif

              );


`ifdef DBG_WISHBONE_SUPPORTED



wb_slave_behavioral i_wb
(
	.CLK_I(wb_clk_i),
	.RST_I(wb_rst_i),
	.ACK_O(wb_ack),
	.ADR_I(wb_adr),
	.CYC_I(wb_cyc),
	.DAT_O(wb_dat_s),
	.DAT_I(wb_dat_m),
	.ERR_O(wb_err),
	.RTY_O(),
	.SEL_I(wb_sel),
	.STB_I(wb_stb),
	.WE_I(wb_we),
	.CAB_I(1'b0)
);
`endif


`ifdef DBG_CPU0_SUPPORTED

cpu_behavioral cpu0_i  (
   .cpu_rst_i(cpu0_rst),
   .cpu_clk_o(cpu0_clk),
   .cpu_addr_i(cpu0_addr),
   .cpu_data_o(cpu0_data_c),
   .cpu_data_i(cpu0_data_d),
   .cpu_bp_o(cpu0_bp),
   .cpu_stall_i(cpu0_stall),
   .cpu_stb_i(cpu0_stb),
   .cpu_we_i(cpu0_we),
   .cpu_ack_o(cpu0_ack),
   .cpu_rst_o(cpu0_rst)
);

`endif


`ifdef DBG_CPU1_SUPPORTED

cpu_behavioral cpu1_i  (
		    .cpu_rst_i(cpu1_rst),
                    .cpu_clk_o(cpu1_clk),
                    .cpu_addr_i(cpu1_addr),
                    .cpu_data_o(cpu1_data_c),
                    .cpu_data_i(cpu1_data_d),
                    .cpu_bp_o(cpu1_bp),
                    .cpu_stall_i(cpu1_stall),
                    .cpu_stb_i(cpu1_stb),
                    .cpu_we_i(cpu1_we),
                    .cpu_ack_o(cpu1_ack),
                    .cpu_rst_o(cpu1_rst)
);
`endif
   




task compute_crc;
    input [31:0] crc_in;
    input [31:0] data_in;
    input [5:0] length_bits;
    output [31:0] crc_out;
    integer i;
    reg [31:0] d;
    reg [31:0] c;
    begin
        crc_out = crc_in;
        for(i = 0; i < length_bits; i = i+1) begin
           d = (data_in[i]) ? 32'hffffffff : 32'h0;
           c = (crc_out[0]) ? 32'hffffffff : 32'h0;

           crc_out = crc_out >> 1;
           crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);

        end
    end
endtask

task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
    set_ir(`IDCODE);
    

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_read_write_stream(64'h0, 8'd32, 1, readdata);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    idcode = readdata[31:0];
    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;

task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({1'b1,moduleid}, 8'h3, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    
    $display("Selecting module (%0x)", moduleid);
    


end
endtask


task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
    streamdata = {11'h0,1'b0,opcode,address,burstlength};
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, 8'd53, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask

task select_module_internal_register;
    input [31:0] regidx;
    input [7:0] len;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | regidx;
    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (len+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask
        

task read_module_internal_register;

    input [7:0] len;
    output [63:0] instream;
    reg [63:0] bitmask;
begin
    instream = 64'h0;

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);

    jtag_read_write_stream(64'h0, len+4,1,instream);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    bitmask = 64'hffffffffffffffff;
    bitmask = bitmask << len;
    bitmask = ~bitmask;
    instream = instream & bitmask;
end
endtask

task write_module_internal_register;
    input [31:0] regidx;
    input [7:0] idxlen;
    input [63:0] writedata;
    input [7:0] datalen;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | writedata;
    streamdata = streamdata | (regidx << datalen);
    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
    
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (idxlen+datalen+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin
    $display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
    instream = 64'h0;
    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BREAD8;
       3'h2: opcode = `DBG_WB_CMD_BREAD16;
       3'h4: opcode = `DBG_WB_CMD_BREAD32;
       default:
          begin
           $display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BREAD32;
          end
   endcase
   
   send_module_burst_command(opcode,start_address, word_count);
   

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);

`ifdef ADBG_USE_HISPEED

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      
      if(j > 1) begin
         $display("Took %0d tries before good status bit during burst read", j);
      end
`endif
   

   for(i = 0; i < word_count; i=i+1) begin
     
`ifndef ADBG_USE_HISPEED     

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      
      if(j > 1) begin
         $display("Took %0d tries before good status bit during burst read", j);
      end
`endif
  
     jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);

     compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
     crc_calc_i = crc_calc_o;
     if(word_size_bytes == 1) input_data8[i] = instream[7:0];
     else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
     else input_data32[i] = instream[31:0];
   end
    

   jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
   if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
   else $display("CRC OK!");
    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end
endtask


task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin
    $display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BWRITE8;
       3'h2: opcode = `DBG_WB_CMD_BWRITE16;
       3'h4: opcode = `DBG_WB_CMD_BWRITE32;
       default:
          begin
           $display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BWRITE32;
          end
   endcase
   
   send_module_burst_command(opcode, start_address, word_count);
   

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);
   


   write_bit(`JTAG_TDO_bit);


   for(i = 0; i < word_count; i=i+1) begin

      if(word_size_bytes == 4)      dataword = {32'h0, static_data32[i]};
      else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
      else                          dataword = {56'h0, static_data8[i]};
      
      
      jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
      compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
      crc_calc_i = crc_calc_o;
      
      
`ifndef ADBG_USE_HISPEED


      status = 1'b0;
      read_write_bit(3'h0, status);
      
      if(!status) begin
         $display("Bad status bit during burst write, index %d", i);
      end
`endif      
  

   end
    

   jtag_write_stream(crc_calc_o, 6'd32,0);
   

   read_write_bit(`JTAG_TMS_bit, crc_match);
   if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
   else $display("CRC OK!");
    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end

endtask




task set_ir;
input [3:0] irval;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({60'h0,irval}, 8'h4, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task reset_jtag;
integer i;
begin
   for(i = 0; i < 8; i=i+1) begin
      write_bit(`JTAG_TMS_bit);
   end
   write_bit(3'h0);
end
endtask





task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       write_bit(bits);
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   write_bit(bits);
    
end
endtask


task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
    instream = 64'h0;
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       read_write_bit(bits, inbit);
       instream = (instream | (inbit << i));
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   read_write_bit(bits, inbit);
   instream = (instream | (inbit << (len-1)));
end
endtask




task write_bit;
   input [2:0] bitvals;
   begin
       

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask

task read_write_bit;
   input [2:0] bitvals;
   output l_tdi_val;
   begin
       

   l_tdi_val <= jtag_tdi_i;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask




task jtag_out;
  input   [2:0]   bitvals;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 
   end
endtask


task jtag_inout;
  input   [2:0]   bitvals;
  output l_tdi_val;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 

   l_tdi_val <= jtag_tdi_i;
   end
endtask

endmodule