data/full_repos/permissive/210844779/lab1/1.4/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.4/tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.4/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.4/tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.4/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.4/tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.4/tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.4/tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.4/tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.4/tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.4/tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/210844779/lab1/1.4/tb.v:6: Cannot find file containing module: \'T_ff\'\nT_ff u0(.T(T),.clk(clk),.Pre(Pre),.Rst(Rst),.Q(Q));\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab1/1.4,data/full_repos/permissive/210844779/T_ff\n             data/full_repos/permissive/210844779/lab1/1.4,data/full_repos/permissive/210844779/T_ff.v\n             data/full_repos/permissive/210844779/lab1/1.4,data/full_repos/permissive/210844779/T_ff.sv\n             T_ff\n             T_ff.v\n             T_ff.sv\n             obj_dir/T_ff\n             obj_dir/T_ff.v\n             obj_dir/T_ff.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module d();

reg T,clk,Pre,Rst;
wire Q;

T_ff u0(.T(T),.clk(clk),.Pre(Pre),.Rst(Rst),.Q(Q));

always 
begin
  
  clk=1'b0; 
  #5
  clk=1'b1; 
  #5;
end

always
begin
  Rst= 1'b1;
  Pre= 1'b0;
  T=1'b1;
  #10
  
  Rst= 1'b0;
  Pre= 1'b0;
  T=1'b1;
  #10
  
  Rst= 1'b0;
  Pre= 1'b0;
  T=1'b0;
  #10
  
  Rst= 1'b0;
  Pre= 1'b0;
  T=1'b1;
  #10
  
  Rst= 1'b0;
  Pre= 1'b1;
  T=1'b1;
  #10
  
  Rst= 1'b0;
  Pre= 1'b0;
  T=1'b0;
  #10
  
  Rst= 1'b1;
  Pre= 1'b0;
  T=1'b0;
  #10
  
  Rst= 1'b0;
  Pre= 1'b0;
  T=1'b1;
  #10;

end

endmodule
module d();


reg T,clk,Pre,Rst;
wire Q;

T_ff u0(.T(T),.clk(clk),.Pre(Pre),.Rst(Rst),.Q(Q));

always 
begin
  
  clk=1'b0; 
  #5
  clk=1'b1; 
  #5;
end

always
begin
  Rst= 1'b1;
  Pre= 1'b0;
  T=1'b1;
  #10
  
  Rst= 1'b0;
  Pre= 1'b0;
  T=1'b1;
  #10
  
  Rst= 1'b0;
  Pre= 1'b0;
  T=1'b0;
  #10
  
  Rst= 1'b0;
  Pre= 1'b0;
  T=1'b1;
  #10
  
  Rst= 1'b0;
  Pre= 1'b1;
  T=1'b1;
  #10
  
  Rst= 1'b0;
  Pre= 1'b0;
  T=1'b0;
  #10
  
  Rst= 1'b1;
  Pre= 1'b0;
  T=1'b0;
  #10
  
  Rst= 1'b0;
  Pre= 1'b0;
  T=1'b1;
  #10;

end

endmodule