data/full_repos/permissive/156600739/rtl/dmi_arbiter.sv
 line:37: before: "DBUS_REQ_BITS"
data/verilator_xmls/c067e058-b371-4b5e-a932-1f9ce5f781a6.xml
module dmi_arbiter #(

    parameter int DBUS_REQ_BITS = 41,

    parameter int DBUS_RSP_BITS = 34
)(


    input  logic clk,


    input  logic rst_n,


    input  logic                     dtm0_req_vld,
    output logic                     dtm0_req_rdy,
    input  logic [DBUS_REQ_BITS-1:0] dtm0_req_bits,
    output logic                     dtm0_rsp_vld,
    input  logic                     dtm0_rsp_rdy,
    output logic [DBUS_RSP_BITS-1:0] dtm0_rsp_bits,


    input  logic                     dtm1_req_vld,
    output logic                     dtm1_req_rdy,
    input  logic [DBUS_REQ_BITS-1:0] dtm1_req_bits,
    output logic                     dtm1_rsp_vld,
    input  logic                     dtm1_rsp_rdy,
    output logic [DBUS_RSP_BITS-1:0] dtm1_rsp_bits,


    output logic                     dm_req_vld,
    input  logic                     dm_req_rdy,
    output logic [DBUS_REQ_BITS-1:0] dm_req_bits,
    input  logic                     dm_rsp_vld,
    output logic                     dm_rsp_rdy,
    input  logic [DBUS_RSP_BITS-1:0] dm_rsp_bits
);







logic dtm0_req_allow;

logic dtm0_req_accept;

logic dtm0_req_done;


logic dtm1_req_allow;
logic dtm1_req_accept;
logic dtm1_req_done;


logic dm_req_done;







always_ff @(posedge clk or negedge rst_n) begin: p_dm_req_bits
    if (!rst_n)
        dm_req_bits <= '0;
    else if (dtm0_req_accept)
        dm_req_bits <= dtm0_req_bits;
    else if (dtm1_req_accept)
        dm_req_bits <= dtm1_req_bits;
end: p_dm_req_bits


assign dm_req_done = dm_req_vld & dm_req_rdy;



always_ff @(posedge clk or negedge rst_n) begin: p_dm_req_vld
    if (!rst_n)
        dm_req_vld <= 1'b0;
    else if (dtm0_req_accept | dtm1_req_accept | dm_req_done)
        dm_req_vld <= dtm0_req_accept | dtm1_req_accept | (~dm_req_done);
end: p_dm_req_vld






assign dtm0_req_accept = dtm0_req_vld & dtm0_req_rdy & dtm0_req_allow;



assign dtm0_req_done = dm_req_done & ~dtm0_req_rdy;


always_ff @(posedge clk or negedge rst_n) begin: p_dtm0_req_rdy
    if (!rst_n) begin
        dtm0_req_rdy <= 1'b1;
    end
    else if (dtm0_req_accept | dtm0_req_done) begin
        dtm0_req_rdy <= ~dtm0_req_accept | dtm0_req_done;
    end
end: p_dtm0_req_rdy







assign dtm1_req_accept = dtm1_req_vld & dtm1_req_rdy & dtm1_req_allow;

assign dtm1_req_done = dm_req_done & ~dtm1_req_rdy;

always_ff @(posedge clk or negedge rst_n) begin: p_dtm1_req_rdy
    if (!rst_n) begin
        dtm1_req_rdy <= 1'b1;
    end
    else if (dtm1_req_accept | dtm1_req_done) begin
        dtm1_req_rdy <= ~dtm1_req_accept | dtm1_req_done;
    end
end: p_dtm1_req_rdy







logic dm_rsp_allow;

logic dm_rsp_accept;

logic dm_rsp_done;


logic [DBUS_RSP_BITS-1:0] dtm_rsp_bits;


logic dtm0_rsp_accept;

logic dtm0_rsp_clr;


logic dtm1_rsp_accept;
logic dtm1_rsp_clr;




always_ff @(posedge clk or negedge rst_n) begin: p_dtm_rsp_bits
    if (!rst_n)
        dtm_rsp_bits <= '0;
    else if (dm_rsp_accept)
        dtm_rsp_bits <= dm_rsp_bits;
end: p_dtm_rsp_bits

assign dtm0_rsp_bits = dtm_rsp_bits;
assign dtm1_rsp_bits = dtm_rsp_bits;






always_ff @(posedge clk or negedge rst_n) begin: p_dm_rsp_rdy
    if (!rst_n) begin
        dm_rsp_rdy <= 1'b1;
    end
    else if (dm_rsp_accept | dm_rsp_done) begin
        dm_rsp_rdy <= ~dm_rsp_accept | dm_rsp_done;
    end
end: p_dm_rsp_rdy






assign dtm0_rsp_clr = dtm0_rsp_vld & dtm0_rsp_rdy;


always_ff @(posedge clk or negedge rst_n) begin: p_dtm0_rsp_vld
    if (!rst_n)
        dtm0_rsp_vld <= 1'b0;
    else if (dtm0_rsp_accept | dtm0_rsp_clr)
        dtm0_rsp_vld <= dtm0_rsp_accept | (~dtm0_rsp_clr);
end: p_dtm0_rsp_vld







assign dtm1_rsp_clr = dtm1_rsp_vld & dtm1_rsp_rdy;

always_ff @(posedge clk or negedge rst_n) begin: p_dtm1_rsp_vld
    if (!rst_n)
        dtm1_rsp_vld <= 1'b0;
    else if (dtm1_rsp_accept | dtm1_rsp_clr)
        dtm1_rsp_vld <= dtm1_rsp_accept | (~dtm1_rsp_clr);
end: p_dtm1_rsp_vld












logic dtm_src_last;






typedef enum bit {


    Q_REQ = 1'b0,



    Q_RSP = 1'b1
} t_transaction_fsm;


t_transaction_fsm trans_fsm_q;
t_transaction_fsm trans_fsm_n;






















always_ff @(posedge clk or negedge rst_n) begin: p_dtm_src_last
    if (!rst_n)
        dtm_src_last <= 1'b0;
    else begin

        assert( ~(dtm0_req_accept & dtm1_req_accept) );
        if (dtm0_req_accept | dtm1_req_accept) begin
            dtm_src_last <= dtm1_req_accept;
        end
    end
end: p_dtm_src_last



assign dtm0_req_allow = (trans_fsm_q == Q_REQ) & ( dtm_src_last | ~dtm1_req_vld);
assign dtm1_req_allow = (trans_fsm_q == Q_REQ) & (~dtm_src_last | ~dtm0_req_vld);



assign dm_rsp_accept = (trans_fsm_q == Q_RSP) & dm_rsp_vld & dm_rsp_rdy;



assign dtm0_rsp_accept = dm_rsp_accept & ~dtm_src_last;
assign dtm1_rsp_accept = dm_rsp_accept &  dtm_src_last;



assign dm_rsp_done = dtm_src_last ? dtm1_rsp_clr : dtm0_rsp_clr;



always_ff @(posedge clk or negedge rst_n) begin: p_trans_fsm_q
    if (!rst_n)
        trans_fsm_q <= Q_REQ;
    else
        trans_fsm_q <= trans_fsm_n;
end: p_trans_fsm_q




always_comb begin: p_trans_fsm_n
    trans_fsm_n = trans_fsm_q;

    case (trans_fsm_q)
        Q_REQ: begin
            if (dtm0_req_accept | dtm1_req_accept) begin
                trans_fsm_n = Q_RSP;
            end
        end

        Q_RSP: begin
            if (dm_rsp_done) begin
                trans_fsm_n = Q_REQ;
            end
        end

        default: begin
            $error("Unexpected FSM state: %0s", trans_fsm_q);
        end
    endcase
end: p_trans_fsm_n


endmodule
module dmi_arbiter #(

    parameter int DBUS_REQ_BITS = 41,

    parameter int DBUS_RSP_BITS = 34
)(


    input  logic clk,


    input  logic rst_n,


    input  logic                     dtm0_req_vld,
    output logic                     dtm0_req_rdy,
    input  logic [DBUS_REQ_BITS-1:0] dtm0_req_bits,
    output logic                     dtm0_rsp_vld,
    input  logic                     dtm0_rsp_rdy,
    output logic [DBUS_RSP_BITS-1:0] dtm0_rsp_bits,


    input  logic                     dtm1_req_vld,
    output logic                     dtm1_req_rdy,
    input  logic [DBUS_REQ_BITS-1:0] dtm1_req_bits,
    output logic                     dtm1_rsp_vld,
    input  logic                     dtm1_rsp_rdy,
    output logic [DBUS_RSP_BITS-1:0] dtm1_rsp_bits,


    output logic                     dm_req_vld,
    input  logic                     dm_req_rdy,
    output logic [DBUS_REQ_BITS-1:0] dm_req_bits,
    input  logic                     dm_rsp_vld,
    output logic                     dm_rsp_rdy,
    input  logic [DBUS_RSP_BITS-1:0] dm_rsp_bits
);








logic dtm0_req_allow;

logic dtm0_req_accept;

logic dtm0_req_done;


logic dtm1_req_allow;
logic dtm1_req_accept;
logic dtm1_req_done;


logic dm_req_done;







always_ff @(posedge clk or negedge rst_n) begin: p_dm_req_bits
    if (!rst_n)
        dm_req_bits <= '0;
    else if (dtm0_req_accept)
        dm_req_bits <= dtm0_req_bits;
    else if (dtm1_req_accept)
        dm_req_bits <= dtm1_req_bits;
end: p_dm_req_bits


assign dm_req_done = dm_req_vld & dm_req_rdy;



always_ff @(posedge clk or negedge rst_n) begin: p_dm_req_vld
    if (!rst_n)
        dm_req_vld <= 1'b0;
    else if (dtm0_req_accept | dtm1_req_accept | dm_req_done)
        dm_req_vld <= dtm0_req_accept | dtm1_req_accept | (~dm_req_done);
end: p_dm_req_vld






assign dtm0_req_accept = dtm0_req_vld & dtm0_req_rdy & dtm0_req_allow;



assign dtm0_req_done = dm_req_done & ~dtm0_req_rdy;


always_ff @(posedge clk or negedge rst_n) begin: p_dtm0_req_rdy
    if (!rst_n) begin
        dtm0_req_rdy <= 1'b1;
    end
    else if (dtm0_req_accept | dtm0_req_done) begin
        dtm0_req_rdy <= ~dtm0_req_accept | dtm0_req_done;
    end
end: p_dtm0_req_rdy







assign dtm1_req_accept = dtm1_req_vld & dtm1_req_rdy & dtm1_req_allow;

assign dtm1_req_done = dm_req_done & ~dtm1_req_rdy;

always_ff @(posedge clk or negedge rst_n) begin: p_dtm1_req_rdy
    if (!rst_n) begin
        dtm1_req_rdy <= 1'b1;
    end
    else if (dtm1_req_accept | dtm1_req_done) begin
        dtm1_req_rdy <= ~dtm1_req_accept | dtm1_req_done;
    end
end: p_dtm1_req_rdy







logic dm_rsp_allow;

logic dm_rsp_accept;

logic dm_rsp_done;


logic [DBUS_RSP_BITS-1:0] dtm_rsp_bits;


logic dtm0_rsp_accept;

logic dtm0_rsp_clr;


logic dtm1_rsp_accept;
logic dtm1_rsp_clr;




always_ff @(posedge clk or negedge rst_n) begin: p_dtm_rsp_bits
    if (!rst_n)
        dtm_rsp_bits <= '0;
    else if (dm_rsp_accept)
        dtm_rsp_bits <= dm_rsp_bits;
end: p_dtm_rsp_bits

assign dtm0_rsp_bits = dtm_rsp_bits;
assign dtm1_rsp_bits = dtm_rsp_bits;






always_ff @(posedge clk or negedge rst_n) begin: p_dm_rsp_rdy
    if (!rst_n) begin
        dm_rsp_rdy <= 1'b1;
    end
    else if (dm_rsp_accept | dm_rsp_done) begin
        dm_rsp_rdy <= ~dm_rsp_accept | dm_rsp_done;
    end
end: p_dm_rsp_rdy






assign dtm0_rsp_clr = dtm0_rsp_vld & dtm0_rsp_rdy;


always_ff @(posedge clk or negedge rst_n) begin: p_dtm0_rsp_vld
    if (!rst_n)
        dtm0_rsp_vld <= 1'b0;
    else if (dtm0_rsp_accept | dtm0_rsp_clr)
        dtm0_rsp_vld <= dtm0_rsp_accept | (~dtm0_rsp_clr);
end: p_dtm0_rsp_vld







assign dtm1_rsp_clr = dtm1_rsp_vld & dtm1_rsp_rdy;

always_ff @(posedge clk or negedge rst_n) begin: p_dtm1_rsp_vld
    if (!rst_n)
        dtm1_rsp_vld <= 1'b0;
    else if (dtm1_rsp_accept | dtm1_rsp_clr)
        dtm1_rsp_vld <= dtm1_rsp_accept | (~dtm1_rsp_clr);
end: p_dtm1_rsp_vld












logic dtm_src_last;






typedef enum bit {


    Q_REQ = 1'b0,



    Q_RSP = 1'b1
} t_transaction_fsm;


t_transaction_fsm trans_fsm_q;
t_transaction_fsm trans_fsm_n;






















always_ff @(posedge clk or negedge rst_n) begin: p_dtm_src_last
    if (!rst_n)
        dtm_src_last <= 1'b0;
    else begin

        assert( ~(dtm0_req_accept & dtm1_req_accept) );
        if (dtm0_req_accept | dtm1_req_accept) begin
            dtm_src_last <= dtm1_req_accept;
        end
    end
end: p_dtm_src_last



assign dtm0_req_allow = (trans_fsm_q == Q_REQ) & ( dtm_src_last | ~dtm1_req_vld);
assign dtm1_req_allow = (trans_fsm_q == Q_REQ) & (~dtm_src_last | ~dtm0_req_vld);



assign dm_rsp_accept = (trans_fsm_q == Q_RSP) & dm_rsp_vld & dm_rsp_rdy;



assign dtm0_rsp_accept = dm_rsp_accept & ~dtm_src_last;
assign dtm1_rsp_accept = dm_rsp_accept &  dtm_src_last;



assign dm_rsp_done = dtm_src_last ? dtm1_rsp_clr : dtm0_rsp_clr;



always_ff @(posedge clk or negedge rst_n) begin: p_trans_fsm_q
    if (!rst_n)
        trans_fsm_q <= Q_REQ;
    else
        trans_fsm_q <= trans_fsm_n;
end: p_trans_fsm_q




always_comb begin: p_trans_fsm_n
    trans_fsm_n = trans_fsm_q;

    case (trans_fsm_q)
        Q_REQ: begin
            if (dtm0_req_accept | dtm1_req_accept) begin
                trans_fsm_n = Q_RSP;
            end
        end

        Q_RSP: begin
            if (dm_rsp_done) begin
                trans_fsm_n = Q_REQ;
            end
        end

        default: begin
            $error("Unexpected FSM state: %0s", trans_fsm_q);
        end
    endcase
end: p_trans_fsm_n


endmodule