data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v
 line:304: before: "if"
1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:6: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/generic.v.sv\n             lib/generic.v\n             lib/generic.v.v\n             lib/generic.v.sv\n             obj_dir/lib/generic.v\n             obj_dir/lib/generic.v.v\n             obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:7: Cannot find include file: lib/RAM8.v\n`include "lib/RAM8.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:9: Cannot find include file: lib/plldcm.v\n`include "lib/plldcm.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:10: Cannot find include file: lib/serdes_pll.v\n`include "lib/serdes_pll.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:11: Cannot find include file: lib/half_duplex_rpi_bus.v\n`include "lib/half_duplex_rpi_bus.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:12: Cannot find include file: lib/sequencer.v\n`include "lib/sequencer.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:13: Cannot find include file: lib/reset.v\n`include "lib/reset.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:14: Cannot find include file: lib/edge_to_pulse.v\n`include "lib/edge_to_pulse.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:49: syntax error, unexpected null, expecting IDENTIFIER or do or final\n wire [7:0] null = 0;\n            ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:51: syntax error, unexpected \'=\', expecting \',\' or \';\'\n wire [7:0] pat [COUNTER_SIZE-COUNTER_PICKOFF-1:0] = { 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111, 8\'b11111111 };\n                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:215: Unsupported: Ignoring delay on this delayed statement.\n  #512;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:216: Unsupported: Ignoring delay on this delayed statement.\n  #512;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:222: Unsupported: Ignoring delay on this delayed statement.\n  #HALF_PERIOD_OF_PERIPHERAL;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test056.palimpsest.cylon.althea.revA.v:227: Unsupported: Ignoring delay on this delayed statement.\n  #HALF_PERIOD_OF_CONTROLLER;\n  ^\n%Error: Exiting due to 10 error(s), 5 warning(s)\n'
module myalthea #(
	) (
	input clock50_p, clock50_n,
	inout coax4,













	a_p, b_p, c_p, d_p, e_p, f_p,
	g_p, h_p, j_p, k_p, l_p, m_p,







	output [7:0] led

);
	wire [3:0] internal_coax_led;
	wire [7:0] internal_led;
	assign led = internal_led;

	wire [5:0] diff_pair_left;
	assign { a_n, c_n, d_n, f_n, b_n, e_n } = diff_pair_left;
	wire coax5, coax3, coax2, coax1, coax0;
	wire [12:1] signal;


	assign { b_p, d_p, f_p, h_p, l_p, m_p, a_p, c_p, e_p, g_p, j_p, k_p } = signal;

	top #(
		.TESTBENCH(0)
	) althea (
		.clock50_p(clock50_p), .clock50_n(clock50_n),
		.coax({coax5, coax4, coax3, coax2, coax1, coax0}),
		.signal(signal),






		.led(internal_led),
		.coax_led(internal_coax_led)
	);
endmodule
module myalthea #(
	) (
	input clock50_p, clock50_n,
	inout coax4,













	a_p, b_p, c_p, d_p, e_p, f_p,
	g_p, h_p, j_p, k_p, l_p, m_p,







	output [7:0] led

);

	wire [3:0] internal_coax_led;
	wire [7:0] internal_led;
	assign led = internal_led;

	wire [5:0] diff_pair_left;
	assign { a_n, c_n, d_n, f_n, b_n, e_n } = diff_pair_left;
	wire coax5, coax3, coax2, coax1, coax0;
	wire [12:1] signal;


	assign { b_p, d_p, f_p, h_p, l_p, m_p, a_p, c_p, e_p, g_p, j_p, k_p } = signal;

	top #(
		.TESTBENCH(0)
	) althea (
		.clock50_p(clock50_p), .clock50_n(clock50_n),
		.coax({coax5, coax4, coax3, coax2, coax1, coax0}),
		.signal(signal),






		.led(internal_led),
		.coax_led(internal_coax_led)
	);
endmodule