data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n    always #(clk_period/2) clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:41: Cannot find file containing module: \'filter1\'\n    filter1 filter_uut\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new,data/full_repos/permissive/17656033/filter1\n             data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new,data/full_repos/permissive/17656033/filter1.v\n             data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new,data/full_repos/permissive/17656033/filter1.sv\n             filter1\n             filter1.v\n             filter1.sv\n             obj_dir/filter1\n             obj_dir/filter1.v\n             obj_dir/filter1.sv\n%Warning-WIDTH: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:118: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                : ... In instance filter_tb\n                din00 <= {$random%128};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:119: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                : ... In instance filter_tb\n                din01 <= {$random%128};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:120: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                : ... In instance filter_tb\n                din02 <= {$random%128};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:121: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                : ... In instance filter_tb\n                din10 <= {$random%128};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:122: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                : ... In instance filter_tb\n                din11 <= {$random%128};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:123: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                : ... In instance filter_tb\n                din12 <= {$random%128};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:124: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                : ... In instance filter_tb\n                din20 <= {$random%128};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:125: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                : ... In instance filter_tb\n                din21 <= {$random%128};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/17656033/filter/filter.srcs/sim_1/new/filter_tb.v:126: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                : ... In instance filter_tb\n                din22 <= {$random%128};\n                      ^~\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module filter_tb;

    reg	clk;
    reg	resetn;
    reg	[7:0]	din00;
    reg	[7:0]	din01;
    reg	[7:0]	din02;
    reg	[7:0]	din10;
    reg	[7:0]	din11;
    reg	[7:0]	din12;
    reg	[7:0]	din20;
    reg	[7:0]	din21;
    reg	[7:0]	din22;
    reg	din_valid;
    wire	[7:0]	dout;				
    wire	dout_valid;


    filter1 filter_uut
	(
        .clk(clk),
        .resetn(resetn),
        .din00(din00),
        .din01(din01),
        .din02(din02),
        .din10(din10),
        .din11(din11),
        .din12(din12),
        .din20(din20),
        .din21(din21),
        .din22(din22),
        .din_valid(din_valid),
        .dout(dout),
        .dout_valid(dout_valid)
    );

    reg [7:0] counter1;
    reg [7:0] counter2;
        
    parameter clk_period = 10;
    initial clk = 1'b0;
    always #(clk_period/2) clk = ~clk;
    
    initial begin
        
        resetn = 1'b0;
        
        #100
        
        resetn = 1'b1;
    end
        
    always@(posedge clk) begin
    
        if(resetn == 1'b0) begin
        
            counter1 <= 0;
            counter2 <= 0;
        end
        else begin
                                
            if(counter1 == counter2) begin
            
                counter1 <= 0;
                counter2 <= counter2 + 1;
            end
            else begin
            
                counter1 <= counter1 + 1;
            end
        end
    end
    always@(posedge clk) begin
    
        if(resetn == 1'b0) begin
        
            din_valid <= 1'b0;
            
            din00 <= 0;
            din01 <= 0;
            din02 <= 0;
            
            din10 <= 0;
            din11 <= 0;
            din12 <= 0;
            
            din20 <= 0;
            din21 <= 0;
            din22 <= 0;
        end
        else begin
        
            if($random%2 == 1 ) begin
                din_valid <= 1'b1;
                
                din00 <= {$random%128};
                din01 <= {$random%128};
                din02 <= {$random%128};
                din10 <= {$random%128};
                din11 <= {$random%128};
                din12 <= {$random%128};
                din20 <= {$random%128};
                din21 <= {$random%128};
                din22 <= {$random%128};
            end
            else begin
            
                din_valid <= 1'b0;
            end
        end        
    end
endmodule
module filter_tb;


    reg	clk;
    reg	resetn;
    reg	[7:0]	din00;
    reg	[7:0]	din01;
    reg	[7:0]	din02;
    reg	[7:0]	din10;
    reg	[7:0]	din11;
    reg	[7:0]	din12;
    reg	[7:0]	din20;
    reg	[7:0]	din21;
    reg	[7:0]	din22;
    reg	din_valid;
    wire	[7:0]	dout;				
    wire	dout_valid;


    filter1 filter_uut
	(
        .clk(clk),
        .resetn(resetn),
        .din00(din00),
        .din01(din01),
        .din02(din02),
        .din10(din10),
        .din11(din11),
        .din12(din12),
        .din20(din20),
        .din21(din21),
        .din22(din22),
        .din_valid(din_valid),
        .dout(dout),
        .dout_valid(dout_valid)
    );

    reg [7:0] counter1;
    reg [7:0] counter2;
        
    parameter clk_period = 10;
    initial clk = 1'b0;
    always #(clk_period/2) clk = ~clk;
    
    initial begin
        
        resetn = 1'b0;
        
        #100
        
        resetn = 1'b1;
    end
        
    always@(posedge clk) begin
    
        if(resetn == 1'b0) begin
        
            counter1 <= 0;
            counter2 <= 0;
        end
        else begin
                                
            if(counter1 == counter2) begin
            
                counter1 <= 0;
                counter2 <= counter2 + 1;
            end
            else begin
            
                counter1 <= counter1 + 1;
            end
        end
    end
    always@(posedge clk) begin
    
        if(resetn == 1'b0) begin
        
            din_valid <= 1'b0;
            
            din00 <= 0;
            din01 <= 0;
            din02 <= 0;
            
            din10 <= 0;
            din11 <= 0;
            din12 <= 0;
            
            din20 <= 0;
            din21 <= 0;
            din22 <= 0;
        end
        else begin
        
            if($random%2 == 1 ) begin
                din_valid <= 1'b1;
                
                din00 <= {$random%128};
                din01 <= {$random%128};
                din02 <= {$random%128};
                din10 <= {$random%128};
                din11 <= {$random%128};
                din12 <= {$random%128};
                din20 <= {$random%128};
                din21 <= {$random%128};
                din22 <= {$random%128};
            end
            else begin
            
                din_valid <= 1'b0;
            end
        end        
    end
endmodule