data/full_repos/permissive/174783592/IFU/inc4bit.sv
data/verilator_xmls/74a258b5-943e-4f5d-8115-905e4a44930c.xml
module inc4bit(in,out);

	input [3:0] in;
	output [3:0] out;

	assign out[0] = ~in[0];
	assign out[1] = in[1] ^ in[0];
	assign out[2] = (~(in[2]) & in[1] & in[0]) | (in[2] & ~in[1]) | (in[2] & ~in[0]);
       assign out[3] =(~in[3] & in[2] & in[1] & in[0]) | (in[3] & ~in[2]) | (in[3] & ~in[1]) | (in[3] &~in[0]);

       endmodule
module inc4bit(in,out);


	input [3:0] in;
	output [3:0] out;

	assign out[0] = ~in[0];
	assign out[1] = in[1] ^ in[0];
	assign out[2] = (~(in[2]) & in[1] & in[0]) | (in[2] & ~in[1]) | (in[2] & ~in[0]);
       assign out[3] =(~in[3] & in[2] & in[1] & in[0]) | (in[3] & ~in[2]) | (in[3] & ~in[1]) | (in[3] &~in[0]);

       endmodule