data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display_top_tb.v
 line:37: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display_top_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display_top_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #73 rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display_top_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display_top_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #40 dataIn = 8\'hFF;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display_top_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #40 dataIn = 8\'h87;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display_top_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #40 dataIn = 8\'hAB;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display_top_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #40 dataIn = 8\'h32;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display_top_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #40 $finish;\n ^\n%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display_top_tb.v:17: Cannot find file containing module: \'display_top\'\ndisplay_top #(SCWIDTH) uut(.clk(clk), .rst(rst), .dataIn(dataIn), .sevenSeg(sevenSeg), .anode(anode));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display1,data/full_repos/permissive/214278225/display_top\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display1,data/full_repos/permissive/214278225/display_top.v\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display1,data/full_repos/permissive/214278225/display_top.sv\n             display_top\n             display_top.v\n             display_top.sv\n             obj_dir/display_top\n             obj_dir/display_top.v\n             obj_dir/display_top.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module display_top_tb;

parameter SCWIDTH = 1;



reg clk;
reg rst;
reg [7:0] dataIn;


wire [7:0] sevenSeg;
wire [3:0] anode;


display_top #(SCWIDTH) uut(.clk(clk), .rst(rst), .dataIn(dataIn), .sevenSeg(sevenSeg), .anode(anode));

initial begin
	clk = 0;
	forever
		#5 clk = ~clk;
end

initial begin
	rst = 1;
	#73 rst = 0;
end

initial begin
	dataIn = 0;
	#3;
	#40 dataIn = 8'hFF;
	#40 dataIn = 8'h87;
	#40 dataIn = 8'hAB;
	#40 dataIn = 8'h32;
	#40 $finish;
end
      
endmodule
module display_top_tb;


parameter SCWIDTH = 1;



reg clk;
reg rst;
reg [7:0] dataIn;


wire [7:0] sevenSeg;
wire [3:0] anode;


display_top #(SCWIDTH) uut(.clk(clk), .rst(rst), .dataIn(dataIn), .sevenSeg(sevenSeg), .anode(anode));

initial begin
	clk = 0;
	forever
		#5 clk = ~clk;
end

initial begin
	rst = 1;
	#73 rst = 0;
end

initial begin
	dataIn = 0;
	#3;
	#40 dataIn = 8'hFF;
	#40 dataIn = 8'h87;
	#40 dataIn = 8'hAB;
	#40 dataIn = 8'h32;
	#40 $finish;
end
      
endmodule