data/full_repos/permissive/218463548/hardware/hdl/oc/brdg_retry_queue.v
None: at end of input
1: b'%Error: data/full_repos/permissive/218463548/hardware/hdl/oc/brdg_retry_queue.v:18: Cannot find include file: snap_global_vars.v\n`include "snap_global_vars.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/218463548/hardware/hdl/oc,data/full_repos/permissive/218463548/snap_global_vars.v\n             data/full_repos/permissive/218463548/hardware/hdl/oc,data/full_repos/permissive/218463548/snap_global_vars.v.v\n             data/full_repos/permissive/218463548/hardware/hdl/oc,data/full_repos/permissive/218463548/snap_global_vars.v.sv\n             snap_global_vars.v\n             snap_global_vars.v.v\n             snap_global_vars.v.sv\n             obj_dir/snap_global_vars.v\n             obj_dir/snap_global_vars.v.v\n             obj_dir/snap_global_vars.v.sv\n%Error: data/full_repos/permissive/218463548/hardware/hdl/oc/brdg_retry_queue.v:37: Define or directive not defined: \'`TAGW\'\n                         input      [`TAGW-1:0]rsp_tag      ,\n                                     ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/oc/brdg_retry_queue.v:44: Define or directive not defined: \'`TAGW\'\n                         output reg [`TAGW-1:0]rty_tag      ,\n                                     ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/oc/brdg_retry_queue.v:67: Define or directive not defined: \'`TAGW\'\n reg [`TAGW-1:00] ram_xlate_done_addra;\n      ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/oc/brdg_retry_queue.v:72: Define or directive not defined: \'`TAGW\'\n reg [`TAGW-1:00]ram_xlate_done_addrb;\n      ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/oc/brdg_retry_queue.v:74: Define or directive not defined: \'`TAGW\'\n reg [`TAGW-1:00]last_rty_tag;\n      ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/oc/brdg_retry_queue.v:277: Define or directive not defined: \'`TAGW\'\n ram_simple_dual #(4,`TAGW) mram_xlate_done ( \n                     ^~~~~\n%Error: Exiting due to 7 error(s)\n'
module brdg_retry_queue 
                        (
                         input                 clk          ,
                         input                 rst_n        ,


                         input      [003:0]    backoff_limit,


                         input                 prt_cmd_start,


                         output                rty_busy     ,


                         input                 rsp_den      ,
                         input      [001:0]    rsp_pos      ,
                         input      [`TAGW-1:0]rsp_tag      ,
                         input      [004:0]    rsp_typ      ,


                         input                 rty_rdy      ,
                         output                rty_valid    ,
                         output reg [001:0]    rty_pos      ,
                         output reg [`TAGW-1:0]rty_tag      ,


                         output                overflow
                         );



 reg             fifo_retry_den;
 reg [11:00]     fifo_retry_din;
 wire            fifo_retry_rdrq;
 wire            fifo_retry_dv;
 wire            fifo_retry_empty;
 reg             rsp_is_retry_backoff;
 reg [23:00]     cfg_short_backoff_timer;
 reg             rsp_is_xlate_pending;
 reg             rsp_is_partial;
 wire[11:00]     fifo_retry_dout;
 reg [23:00]     backoff_countdown;
 reg [04:00]     xlate_pending_cnt;
 wire            retry_check_done;
 reg [04:00]     cstate, nstate;
 reg             ram_xlate_done_wena;
 reg [`TAGW-1:00] ram_xlate_done_addra;
 reg [03:00]     ram_xlate_done_dina;
 reg [02:00]     retry_check_done_slide;
 wire            rsp_is_xlate_done_retry_backoff;
 wire            rsp_is_xlate_done_retry_immediate;
 reg [`TAGW-1:00]ram_xlate_done_addrb;
 wire[03:00]     ram_xlate_done_doutb;
 reg [`TAGW-1:00]last_rty_tag;
 reg [01:00]     last_rty_pos;
 reg             rep_retry_enable;


 parameter IDLE          = 5'b00001,
           RETRY_RELEASE = 5'b00010,    
           RETRY_CHECK   = 5'b00100,    
           RETRY_BACKOFF = 5'b01000,    
           RETRY_NOW     = 5'b10000;    























 wire rsp_xlate_pending              = rsp_typ[0];
 wire rsp_xlate_done_retry_backoff   = rsp_typ[1];
 wire rsp_xlate_done_retry_immediate = rsp_typ[2];
 wire rsp_retry_backoff              = rsp_typ[3];
 wire rsp_partial                    = rsp_typ[4];


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       fifo_retry_den  <= 1'b0;
       fifo_retry_din  <= 12'd0;
     end
   else
     begin
       fifo_retry_den  <= rsp_den && (rsp_xlate_pending || rsp_retry_backoff);
       fifo_retry_din  <= {rsp_partial, rsp_retry_backoff, rsp_xlate_pending, rsp_pos, rsp_tag};
     end


 fifo_sync #(
             .DATA_WIDTH (12),
             .ADDR_WIDTH (7),
             .FWFT       (0)
             ) mfifo_rty_tag (
                              .clk          (clk             ),
                              .rst_n        (rst_n           ),
                              .din          (fifo_retry_din  ),
                              .wr_en        (fifo_retry_den  ),
                              .rd_en        (fifo_retry_rdrq ),
                              .dout         (fifo_retry_dout ),
                              .valid        (fifo_retry_dv   ),
                              .empty        (fifo_retry_empty),
                              .overflow     (overflow        )
                              );


 assign fifo_retry_rdrq = (cstate == RETRY_RELEASE);


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     {rsp_is_partial, rsp_is_retry_backoff, rsp_is_xlate_pending, rty_pos, rty_tag} <= 12'd0;
   else if(fifo_retry_dv)
     {rsp_is_partial, rsp_is_retry_backoff, rsp_is_xlate_pending, rty_pos, rty_tag} <= fifo_retry_dout;



  always @*
    begin
      case (backoff_limit[3:0])
        4'b0000:  cfg_short_backoff_timer[23:0] =  24'h00_0014;
        4'b0001:  cfg_short_backoff_timer[23:0] =  24'h00_0028;
        4'b0010:  cfg_short_backoff_timer[23:0] =  24'h00_0050;
        4'b0011:  cfg_short_backoff_timer[23:0] =  24'h00_00A0;
        4'b0100:  cfg_short_backoff_timer[23:0] =  24'h00_0140;
        4'b0101:  cfg_short_backoff_timer[23:0] =  24'h00_0280;
        4'b0110:  cfg_short_backoff_timer[23:0] =  24'h00_0500;
        4'b0111:  cfg_short_backoff_timer[23:0] =  24'h00_0A00;
        4'b1000:  cfg_short_backoff_timer[23:0] =  24'h00_1400;
        4'b1001:  cfg_short_backoff_timer[23:0] =  24'h00_2800;
        4'b1010:  cfg_short_backoff_timer[23:0] =  24'h00_5000;
        4'b1011:  cfg_short_backoff_timer[23:0] =  24'h00_A000;
        4'b1100:  cfg_short_backoff_timer[23:0] =  24'h01_4000;
        4'b1101:  cfg_short_backoff_timer[23:0] =  24'h02_8000;
        4'b1110:  cfg_short_backoff_timer[23:0] =  24'h05_0000;
        4'b1111:  cfg_short_backoff_timer[23:0] =  24'h0A_0000;
      endcase
    end



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     backoff_countdown <= 24'd0;
   else if(cstate == RETRY_BACKOFF)
     backoff_countdown <= backoff_countdown - 24'd1;
   else
     backoff_countdown <= cfg_short_backoff_timer;



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     xlate_pending_cnt <= 5'd0;
   else if(rsp_den)
     case(rsp_typ[3:0])
       4'b0001 : xlate_pending_cnt <= xlate_pending_cnt + 5'd1;
       4'b0010 : xlate_pending_cnt <= xlate_pending_cnt - 5'd1;
       4'b0100 : xlate_pending_cnt <= xlate_pending_cnt - 5'd1;
       default:;
     endcase



 always@(posedge clk or negedge rst_n)
   if(~rst_n) 
     cstate <= IDLE;
   else
     cstate <= nstate;

 always@*
   case(cstate)
     IDLE               :
                          if (~fifo_retry_empty && ~|xlate_pending_cnt)
                            nstate = RETRY_RELEASE;
                          else
                            nstate = IDLE;
     RETRY_RELEASE      :
                            nstate = RETRY_CHECK;
     RETRY_CHECK        :
                          if (retry_check_done)
                            begin
                              if ((rty_tag == last_rty_tag) && (rty_pos == last_rty_pos) && ~rep_retry_enable)
                                nstate = IDLE;
                              else if (rsp_is_retry_backoff)
                                nstate = RETRY_BACKOFF;
                              else if (rsp_is_xlate_pending && rsp_is_xlate_done_retry_immediate)
                                nstate = RETRY_NOW;
                              else if (rsp_is_xlate_pending && rsp_is_xlate_done_retry_backoff)
                                nstate = RETRY_BACKOFF;
                              else
                                nstate = RETRY_CHECK;
                            end
                          else
                            nstate = RETRY_CHECK;
     RETRY_BACKOFF     :
                          if (~|backoff_countdown)
                            nstate = RETRY_NOW;
                          else
                            nstate = RETRY_BACKOFF;
     RETRY_NOW         :
                          if (rty_rdy)
                            nstate = IDLE;
                          else
                            nstate = RETRY_NOW;
     default           :
                            nstate = IDLE;
   endcase




 always@(posedge clk or negedge rst_n)
   if(~rst_n) 
     retry_check_done_slide <= 3'b001;
   else 
     case(cstate)
       RETRY_CHECK : retry_check_done_slide <= retry_check_done_slide << 1;
       default     : retry_check_done_slide <= 3'b001;
     endcase

 assign retry_check_done = retry_check_done_slide[2];


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       ram_xlate_done_wena  <= 1'b0;
       ram_xlate_done_addra <= 6'd0;
       ram_xlate_done_dina  <= 4'd0;
     end
   else 
     begin
       ram_xlate_done_wena  <= rsp_den && (rsp_xlate_done_retry_backoff || rsp_xlate_done_retry_immediate);
       ram_xlate_done_addra <= rsp_tag;
       ram_xlate_done_dina  <= {rsp_xlate_done_retry_backoff, rsp_xlate_done_retry_immediate, rsp_pos};
     end


 ram_simple_dual #(4,`TAGW) mram_xlate_done ( 
                                         .clk   (clk                 ), 
                                         .ena   (1'b1                ),
                                         .enb   (1'b1                ),
                                         .wea   (ram_xlate_done_wena ), 
                                         .addra (ram_xlate_done_addra), 
                                         .dia   (ram_xlate_done_dina ), 
                                         .addrb (ram_xlate_done_addrb), 
                                         .dob   (ram_xlate_done_doutb)  
                                         );



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     ram_xlate_done_addrb <= 6'd0;
   else
     ram_xlate_done_addrb <= fifo_retry_dout[6:0];

 assign rsp_is_xlate_done_retry_backoff   = ram_xlate_done_doutb[3];
 assign rsp_is_xlate_done_retry_immediate = ram_xlate_done_doutb[2];



 assign rty_valid = rty_rdy && (cstate == RETRY_NOW);


 always@(posedge clk or negedge rst_n)
   if(~rst_n) 
     begin
       last_rty_tag <= 7'd0;
       last_rty_pos <= 2'd0;
     end
   else if(rty_valid)
     begin
       last_rty_tag <= rty_tag;  
       last_rty_pos <= rty_pos;
     end






 always@(posedge clk or negedge rst_n)
   if(~rst_n) 
     rep_retry_enable <= 1'b0;
   else if(rty_valid)
     rep_retry_enable <= 1'b0;
   else if(prt_cmd_start || (fifo_retry_empty && ~rsp_is_partial))  
     rep_retry_enable <= 1'b1;



 assign rty_busy = ~fifo_retry_empty;
        

 wire cstate_h01_h02 = ((cstate == IDLE) && (nstate == RETRY_RELEASE));
 wire cstate_h02_h04 = ((cstate == RETRY_RELEASE) && (nstate == RETRY_CHECK));
 wire cstate_h04_h01 = ((cstate == RETRY_CHECK) && (nstate == IDLE));
 wire cstate_h04_h08 = ((cstate == RETRY_CHECK) && (nstate == RETRY_BACKOFF));
 wire cstate_h04_h10 = ((cstate == RETRY_CHECK) && (nstate == RETRY_NOW));
 wire cstate_h10_h01 = ((cstate == RETRY_NOW) && (nstate == IDLE));















endmodule
module brdg_retry_queue 
                        (
                         input                 clk          ,
                         input                 rst_n        ,


                         input      [003:0]    backoff_limit,


                         input                 prt_cmd_start,


                         output                rty_busy     ,


                         input                 rsp_den      ,
                         input      [001:0]    rsp_pos      ,
                         input      [`TAGW-1:0]rsp_tag      ,
                         input      [004:0]    rsp_typ      ,


                         input                 rty_rdy      ,
                         output                rty_valid    ,
                         output reg [001:0]    rty_pos      ,
                         output reg [`TAGW-1:0]rty_tag      ,


                         output                overflow
                         );




 reg             fifo_retry_den;
 reg [11:00]     fifo_retry_din;
 wire            fifo_retry_rdrq;
 wire            fifo_retry_dv;
 wire            fifo_retry_empty;
 reg             rsp_is_retry_backoff;
 reg [23:00]     cfg_short_backoff_timer;
 reg             rsp_is_xlate_pending;
 reg             rsp_is_partial;
 wire[11:00]     fifo_retry_dout;
 reg [23:00]     backoff_countdown;
 reg [04:00]     xlate_pending_cnt;
 wire            retry_check_done;
 reg [04:00]     cstate, nstate;
 reg             ram_xlate_done_wena;
 reg [`TAGW-1:00] ram_xlate_done_addra;
 reg [03:00]     ram_xlate_done_dina;
 reg [02:00]     retry_check_done_slide;
 wire            rsp_is_xlate_done_retry_backoff;
 wire            rsp_is_xlate_done_retry_immediate;
 reg [`TAGW-1:00]ram_xlate_done_addrb;
 wire[03:00]     ram_xlate_done_doutb;
 reg [`TAGW-1:00]last_rty_tag;
 reg [01:00]     last_rty_pos;
 reg             rep_retry_enable;


 parameter IDLE          = 5'b00001,
           RETRY_RELEASE = 5'b00010,    
           RETRY_CHECK   = 5'b00100,    
           RETRY_BACKOFF = 5'b01000,    
           RETRY_NOW     = 5'b10000;    























 wire rsp_xlate_pending              = rsp_typ[0];
 wire rsp_xlate_done_retry_backoff   = rsp_typ[1];
 wire rsp_xlate_done_retry_immediate = rsp_typ[2];
 wire rsp_retry_backoff              = rsp_typ[3];
 wire rsp_partial                    = rsp_typ[4];


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       fifo_retry_den  <= 1'b0;
       fifo_retry_din  <= 12'd0;
     end
   else
     begin
       fifo_retry_den  <= rsp_den && (rsp_xlate_pending || rsp_retry_backoff);
       fifo_retry_din  <= {rsp_partial, rsp_retry_backoff, rsp_xlate_pending, rsp_pos, rsp_tag};
     end


 fifo_sync #(
             .DATA_WIDTH (12),
             .ADDR_WIDTH (7),
             .FWFT       (0)
             ) mfifo_rty_tag (
                              .clk          (clk             ),
                              .rst_n        (rst_n           ),
                              .din          (fifo_retry_din  ),
                              .wr_en        (fifo_retry_den  ),
                              .rd_en        (fifo_retry_rdrq ),
                              .dout         (fifo_retry_dout ),
                              .valid        (fifo_retry_dv   ),
                              .empty        (fifo_retry_empty),
                              .overflow     (overflow        )
                              );


 assign fifo_retry_rdrq = (cstate == RETRY_RELEASE);


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     {rsp_is_partial, rsp_is_retry_backoff, rsp_is_xlate_pending, rty_pos, rty_tag} <= 12'd0;
   else if(fifo_retry_dv)
     {rsp_is_partial, rsp_is_retry_backoff, rsp_is_xlate_pending, rty_pos, rty_tag} <= fifo_retry_dout;



  always @*
    begin
      case (backoff_limit[3:0])
        4'b0000:  cfg_short_backoff_timer[23:0] =  24'h00_0014;
        4'b0001:  cfg_short_backoff_timer[23:0] =  24'h00_0028;
        4'b0010:  cfg_short_backoff_timer[23:0] =  24'h00_0050;
        4'b0011:  cfg_short_backoff_timer[23:0] =  24'h00_00A0;
        4'b0100:  cfg_short_backoff_timer[23:0] =  24'h00_0140;
        4'b0101:  cfg_short_backoff_timer[23:0] =  24'h00_0280;
        4'b0110:  cfg_short_backoff_timer[23:0] =  24'h00_0500;
        4'b0111:  cfg_short_backoff_timer[23:0] =  24'h00_0A00;
        4'b1000:  cfg_short_backoff_timer[23:0] =  24'h00_1400;
        4'b1001:  cfg_short_backoff_timer[23:0] =  24'h00_2800;
        4'b1010:  cfg_short_backoff_timer[23:0] =  24'h00_5000;
        4'b1011:  cfg_short_backoff_timer[23:0] =  24'h00_A000;
        4'b1100:  cfg_short_backoff_timer[23:0] =  24'h01_4000;
        4'b1101:  cfg_short_backoff_timer[23:0] =  24'h02_8000;
        4'b1110:  cfg_short_backoff_timer[23:0] =  24'h05_0000;
        4'b1111:  cfg_short_backoff_timer[23:0] =  24'h0A_0000;
      endcase
    end



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     backoff_countdown <= 24'd0;
   else if(cstate == RETRY_BACKOFF)
     backoff_countdown <= backoff_countdown - 24'd1;
   else
     backoff_countdown <= cfg_short_backoff_timer;



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     xlate_pending_cnt <= 5'd0;
   else if(rsp_den)
     case(rsp_typ[3:0])
       4'b0001 : xlate_pending_cnt <= xlate_pending_cnt + 5'd1;
       4'b0010 : xlate_pending_cnt <= xlate_pending_cnt - 5'd1;
       4'b0100 : xlate_pending_cnt <= xlate_pending_cnt - 5'd1;
       default:;
     endcase



 always@(posedge clk or negedge rst_n)
   if(~rst_n) 
     cstate <= IDLE;
   else
     cstate <= nstate;

 always@*
   case(cstate)
     IDLE               :
                          if (~fifo_retry_empty && ~|xlate_pending_cnt)
                            nstate = RETRY_RELEASE;
                          else
                            nstate = IDLE;
     RETRY_RELEASE      :
                            nstate = RETRY_CHECK;
     RETRY_CHECK        :
                          if (retry_check_done)
                            begin
                              if ((rty_tag == last_rty_tag) && (rty_pos == last_rty_pos) && ~rep_retry_enable)
                                nstate = IDLE;
                              else if (rsp_is_retry_backoff)
                                nstate = RETRY_BACKOFF;
                              else if (rsp_is_xlate_pending && rsp_is_xlate_done_retry_immediate)
                                nstate = RETRY_NOW;
                              else if (rsp_is_xlate_pending && rsp_is_xlate_done_retry_backoff)
                                nstate = RETRY_BACKOFF;
                              else
                                nstate = RETRY_CHECK;
                            end
                          else
                            nstate = RETRY_CHECK;
     RETRY_BACKOFF     :
                          if (~|backoff_countdown)
                            nstate = RETRY_NOW;
                          else
                            nstate = RETRY_BACKOFF;
     RETRY_NOW         :
                          if (rty_rdy)
                            nstate = IDLE;
                          else
                            nstate = RETRY_NOW;
     default           :
                            nstate = IDLE;
   endcase




 always@(posedge clk or negedge rst_n)
   if(~rst_n) 
     retry_check_done_slide <= 3'b001;
   else 
     case(cstate)
       RETRY_CHECK : retry_check_done_slide <= retry_check_done_slide << 1;
       default     : retry_check_done_slide <= 3'b001;
     endcase

 assign retry_check_done = retry_check_done_slide[2];


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       ram_xlate_done_wena  <= 1'b0;
       ram_xlate_done_addra <= 6'd0;
       ram_xlate_done_dina  <= 4'd0;
     end
   else 
     begin
       ram_xlate_done_wena  <= rsp_den && (rsp_xlate_done_retry_backoff || rsp_xlate_done_retry_immediate);
       ram_xlate_done_addra <= rsp_tag;
       ram_xlate_done_dina  <= {rsp_xlate_done_retry_backoff, rsp_xlate_done_retry_immediate, rsp_pos};
     end


 ram_simple_dual #(4,`TAGW) mram_xlate_done ( 
                                         .clk   (clk                 ), 
                                         .ena   (1'b1                ),
                                         .enb   (1'b1                ),
                                         .wea   (ram_xlate_done_wena ), 
                                         .addra (ram_xlate_done_addra), 
                                         .dia   (ram_xlate_done_dina ), 
                                         .addrb (ram_xlate_done_addrb), 
                                         .dob   (ram_xlate_done_doutb)  
                                         );



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     ram_xlate_done_addrb <= 6'd0;
   else
     ram_xlate_done_addrb <= fifo_retry_dout[6:0];

 assign rsp_is_xlate_done_retry_backoff   = ram_xlate_done_doutb[3];
 assign rsp_is_xlate_done_retry_immediate = ram_xlate_done_doutb[2];



 assign rty_valid = rty_rdy && (cstate == RETRY_NOW);


 always@(posedge clk or negedge rst_n)
   if(~rst_n) 
     begin
       last_rty_tag <= 7'd0;
       last_rty_pos <= 2'd0;
     end
   else if(rty_valid)
     begin
       last_rty_tag <= rty_tag;  
       last_rty_pos <= rty_pos;
     end






 always@(posedge clk or negedge rst_n)
   if(~rst_n) 
     rep_retry_enable <= 1'b0;
   else if(rty_valid)
     rep_retry_enable <= 1'b0;
   else if(prt_cmd_start || (fifo_retry_empty && ~rsp_is_partial))  
     rep_retry_enable <= 1'b1;



 assign rty_busy = ~fifo_retry_empty;
        

 wire cstate_h01_h02 = ((cstate == IDLE) && (nstate == RETRY_RELEASE));
 wire cstate_h02_h04 = ((cstate == RETRY_RELEASE) && (nstate == RETRY_CHECK));
 wire cstate_h04_h01 = ((cstate == RETRY_CHECK) && (nstate == IDLE));
 wire cstate_h04_h08 = ((cstate == RETRY_CHECK) && (nstate == RETRY_BACKOFF));
 wire cstate_h04_h10 = ((cstate == RETRY_CHECK) && (nstate == RETRY_NOW));
 wire cstate_h10_h01 = ((cstate == RETRY_NOW) && (nstate == IDLE));















endmodule