data/full_repos/permissive/128659832/verilog/ControlUnit_tb.v
 line:29 column:20: Illegal character "'"
1: b'%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ControlUnit_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/128659832/verilog/ControlUnit_tb.v:77: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile(  "ControlUnit_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/128659832/verilog/ControlUnit_tb.v:78: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, ControlUnit_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ControlUnit_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #0  i_rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ControlUnit_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ControlUnit_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #15 inEmpty = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ControlUnit_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #30 INSTR = o_HALT<<4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ControlUnit_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #1000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ControlUnit_tb;


    reg  [7:0] INSTR    = 0;
    reg        inEmpty  = 0;
    reg        outFull  = 0;
    reg        debug    = 0;
    reg        nxtInstr = 0;

    wire       wIR;
    wire [1:0] muxR;
    wire       wR;
    wire       srcA;
    wire       wM;
    wire       wAR;
    wire [2:0] aluCtl;
    wire       wPC;
    wire       rIn;
    wire       wO;
    wire       ijump;
    wire       branch;
    wire       rst;
    wire       halt;

    reg        clk     = 0;
    reg        i_rst   = 0;

    localparam
    o_INBOX    = 4'b 0000,
    o_OUTBOX   = 4'b 0001,
    o_COPYFROM = 4'b 0010,
    o_COPYTO   = 4'b 0011,
    o_ADD      = 4'b 0100,
    o_SUB      = 4'b 0101,
    o_BUMPP    = 4'b 0110,
    o_BUMPN    = 4'b 0111,
    o_JUMP     = 4'b 1000,
    o_JUMPZ    = 4'b 1001,
    o_JUMPN    = 4'b 1010,




    o_HALT     = 4'b 1111;


    ControlUnit ControlUnit0 (
        .INSTR(INSTR),
        .inEmpty(inEmpty),
        .outFull(outFull),
        .debug(debug),
        .nxtInstr(nxtInstr),
        .wIR(wIR),
        .muxR(muxR),
        .wR(wR),
        .srcA(srcA),
        .wM(wM),
        .wAR(wAR),
        .aluCtl(aluCtl),
        .wPC(wPC),
        .rIn(rIn),
        .wO(wO),
        .ijump(ijump),
        .branch(branch),
        .rst(rst),
        .halt(halt),
        .clk(clk),
        .i_rst(i_rst)
    );


    always #1 clk = ~clk;


    initial begin

        $dumpfile(  "ControlUnit_tb.vcd");
        $dumpvars(0, ControlUnit_tb);

        #0  i_rst = 0;
            inEmpty = 1;
        #2 i_rst = 0;
         
        #15 inEmpty = 0;

        #30 INSTR = o_HALT<<4;

        #1000 $finish;
    end


endmodule
module ControlUnit_tb;



    reg  [7:0] INSTR    = 0;
    reg        inEmpty  = 0;
    reg        outFull  = 0;
    reg        debug    = 0;
    reg        nxtInstr = 0;

    wire       wIR;
    wire [1:0] muxR;
    wire       wR;
    wire       srcA;
    wire       wM;
    wire       wAR;
    wire [2:0] aluCtl;
    wire       wPC;
    wire       rIn;
    wire       wO;
    wire       ijump;
    wire       branch;
    wire       rst;
    wire       halt;

    reg        clk     = 0;
    reg        i_rst   = 0;

    localparam
    o_INBOX    = 4'b 0000,
    o_OUTBOX   = 4'b 0001,
    o_COPYFROM = 4'b 0010,
    o_COPYTO   = 4'b 0011,
    o_ADD      = 4'b 0100,
    o_SUB      = 4'b 0101,
    o_BUMPP    = 4'b 0110,
    o_BUMPN    = 4'b 0111,
    o_JUMP     = 4'b 1000,
    o_JUMPZ    = 4'b 1001,
    o_JUMPN    = 4'b 1010,




    o_HALT     = 4'b 1111;


    ControlUnit ControlUnit0 (
        .INSTR(INSTR),
        .inEmpty(inEmpty),
        .outFull(outFull),
        .debug(debug),
        .nxtInstr(nxtInstr),
        .wIR(wIR),
        .muxR(muxR),
        .wR(wR),
        .srcA(srcA),
        .wM(wM),
        .wAR(wAR),
        .aluCtl(aluCtl),
        .wPC(wPC),
        .rIn(rIn),
        .wO(wO),
        .ijump(ijump),
        .branch(branch),
        .rst(rst),
        .halt(halt),
        .clk(clk),
        .i_rst(i_rst)
    );


    always #1 clk = ~clk;


    initial begin

        $dumpfile(  "ControlUnit_tb.vcd");
        $dumpvars(0, ControlUnit_tb);

        #0  i_rst = 0;
            inEmpty = 1;
        #2 i_rst = 0;
         
        #15 inEmpty = 0;

        #30 INSTR = o_HALT<<4;

        #1000 $finish;
    end


endmodule