data/full_repos/permissive/158922207/Verilog Design/modules/ControlRegisters.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/ControlRegisters.v\n%Error: Exiting due to 3 error(s)\n'
module MEMControlReg(MEM_MemWrite, MEM_MemRead,  MemWrite, MemRead, W_en, reset, clock);
input W_en, reset, clock,MemWrite, MemRead;
output MEM_MemWrite, MEM_MemRead;
reg [1:0] mem;

assign MEM_MemWrite = mem[1];
assign MEM_MemRead = mem[0];

always @(posedge clock or posedge reset) begin
if (reset)
    mem <= 2'd0;
else begin
    if(W_en)
       mem <= {MemWrite, MemRead};
end
end
endmodule
module MEMControlReg(MEM_MemWrite, MEM_MemRead,  MemWrite, MemRead, W_en, reset, clock);

input W_en, reset, clock,MemWrite, MemRead;
output MEM_MemWrite, MEM_MemRead;
reg [1:0] mem;

assign MEM_MemWrite = mem[1];
assign MEM_MemRead = mem[0];

always @(posedge clock or posedge reset) begin
if (reset)
    mem <= 2'd0;
else begin
    if(W_en)
       mem <= {MemWrite, MemRead};
end
end
endmodule