data/full_repos/permissive/14432793/rfid-verilog/tag/txclkdivide.v
1: b'%Warning-WIDTH: data/full_repos/permissive/14432793/rfid-verilog/tag/txclkdivide.v:30: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'trcal\' generates 10 bits.\n                                                                                     : ... In instance txclkdivide\nassign trcal3 = trcal2 + trcal;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/14432793/rfid-verilog/tag/txclkdivide.v:35: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'trcal\' generates 10 bits.\n                                                                                     : ... In instance txclkdivide\nassign      dr0numerator = (11\'d4+trcal);  \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/14432793/rfid-verilog/tag/txclkdivide.v:38: Operator COND expects 7 bits on the Conditional True, but Conditional True\'s REPLICATE generates 6 bits.\n                                                                                     : ... In instance txclkdivide\nassign      tempdivider = dr ? ({1\'b0, dr1numerator[11:7]}) : (dr0numerator[9:4]);  \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/14432793/rfid-verilog/tag/txclkdivide.v:38: Operator COND expects 7 bits on the Conditional False, but Conditional False\'s SEL generates 6 bits.\n                                                                                     : ... In instance txclkdivide\nassign      tempdivider = dr ? ({1\'b0, dr1numerator[11:7]}) : (dr0numerator[9:4]);  \n                             ^\n%Error: Exiting due to 4 warning(s)\n'
module txclkdivide(reset, oscclk, trcal, dr, txclk);
input reset, oscclk, dr;
input [9:0] trcal;
output txclk;
reg    txclk;
reg  [6:0]  counter;


wire [10:0] trcal2;
assign trcal2[10:1] = trcal;
assign trcal2[0] = 1'b0;
wire [11:0] trcal3;
assign trcal3 = trcal2 + trcal;

wire [11:0] dr1numerator;
assign      dr1numerator = (11'd75+trcal3);
wire [11:0] dr0numerator;
assign      dr0numerator = (11'd4+trcal);

wire [6:0]  tempdivider;
assign      tempdivider = dr ? ({1'b0, dr1numerator[11:7]}) : (dr0numerator[9:4]);
wire [6:0]  divider;
assign      divider = (tempdivider >= 7'd2) ? tempdivider : 7'd2;

always @ (posedge oscclk or posedge reset) begin
  if (reset) begin
    txclk   = 0;
    counter = 0;
  end else if (counter >= (divider-1)) begin
    txclk   = 1;
    counter = 0;
  end else if (counter == ((divider-1) >> 1)) begin
    counter = counter + 7'd1;
    txclk   = 0;
  end else begin
    counter = counter + 7'd1;
  end
end

endmodule
module txclkdivide(reset, oscclk, trcal, dr, txclk);

input reset, oscclk, dr;
input [9:0] trcal;
output txclk;
reg    txclk;
reg  [6:0]  counter;


wire [10:0] trcal2;
assign trcal2[10:1] = trcal;
assign trcal2[0] = 1'b0;
wire [11:0] trcal3;
assign trcal3 = trcal2 + trcal;

wire [11:0] dr1numerator;
assign      dr1numerator = (11'd75+trcal3);
wire [11:0] dr0numerator;
assign      dr0numerator = (11'd4+trcal);

wire [6:0]  tempdivider;
assign      tempdivider = dr ? ({1'b0, dr1numerator[11:7]}) : (dr0numerator[9:4]);
wire [6:0]  divider;
assign      divider = (tempdivider >= 7'd2) ? tempdivider : 7'd2;

always @ (posedge oscclk or posedge reset) begin
  if (reset) begin
    txclk   = 0;
    counter = 0;
  end else if (counter >= (divider-1)) begin
    txclk   = 1;
    counter = 0;
  end else if (counter == ((divider-1) >> 1)) begin
    counter = counter + 7'd1;
    txclk   = 0;
  end else begin
    counter = counter + 7'd1;
  end
end

endmodule