data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v
 line:106: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #300;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n   #(period/2) clk <= ~clk;\n   ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:194: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:199: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:201: Unsupported: wait statements\n   wait(nfc_done);\n   ^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:202: syntax error, unexpected \'@\'\n   @(posedge clk) ;\n   ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:214: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:220: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:223: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:225: Unsupported: wait statements\n   wait(nfc_done);\n   ^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:226: syntax error, unexpected \'@\'\n   @(posedge clk) ;\n   ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:249: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:250: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:255: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:260: syntax error, unexpected \'@\'\n       @(posedge clk) ; \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:261: Unsupported: Ignoring delay on this delayed statement.\n       #3;      \n       ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:267: syntax error, unexpected \'@\'\n   @(posedge clk) ;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:269: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:271: Unsupported: wait statements\n   wait(nfc_done);\n   ^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:272: syntax error, unexpected \'@\'\n   @(posedge clk) ;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:273: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:296: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:297: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:304: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:305: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:307: syntax error, unexpected \'@\'\n    @(posedge clk) ;  \n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:308: Unsupported: wait statements\n   wait(nfc_done);\n   ^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:309: syntax error, unexpected \'@\'\n   @(posedge clk) ;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:310: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:314: syntax error, unexpected \'@\'\n       @(posedge clk) ;\n       ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:332: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:333: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:338: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:339: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:341: syntax error, unexpected \'@\'\n    @(posedge clk) ;\n    ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:342: Unsupported: wait statements\n   wait(nfc_done);\n   ^~~~\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:343: syntax error, unexpected \'@\'\n   @(posedge clk) ;\n   ^\n%Error: data/full_repos/permissive/109400221/originals/NAND_LAT/testbench/verilog/nfcm_tb.v:357: syntax error, unexpected \'@\'\n    @(posedge clk);                                                 \n    ^\n%Error: Exiting due to 27 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module nfcm_tb();

 reg clk,rst;


 wire [7:0] DIO;
 wire CLE;
 wire ALE;
 wire WE_n;
 wire RE_n;
 wire CE_n;
 wire R_nB;

 reg BF_sel;
 reg [10:0] BF_ad;
 reg [7:0] BF_din;
 reg BF_we;
 reg [15:0] RWA;
 wire [7:0] BF_dou;

 wire PErr ;
 wire EErr ;
 wire RErr ;

 reg [2:0] nfc_cmd;
 reg nfc_strt;
 wire nfc_done;

  
reg[7:0] memory[0:2047];

reg [7:0] temp;
  
GSR GSR_INST(.GSR(1'b1));
PUR PUR_INST(.PUR(1'b1));  

parameter period=16;


initial begin
  clk <= 1'b0;
	rst  <= 1'b1;
	BF_sel<=1'b0;                   
	BF_ad<=0;            
	BF_din<=0;            
	BF_we<=0;                   
	RWA<=0; 
	nfc_cmd<=3'b111;
	nfc_strt<=1'b0; 
	temp<=8'h24;



	#300;
	rst<=1'b0;

	kill_time; 
	kill_time; 

	reset_cycle;

	kill_time; 
	kill_time; 
	
	erase_cycle(16'h1234);
	
	kill_time; 
	kill_time;
	
	write_cycle(16'h1234);
	
	kill_time; 
	kill_time;
	
	read_cycle(16'h1234);
	
	kill_time; 
	kill_time;

	read_id_cycle(16'h0000);
	
	kill_time; 
	kill_time;
	
        #1000;
	$stop;
	
	end

always
   #(period/2) clk <= ~clk;
   

nfcm_top nfcm(
 .DIO(DIO),
 .CLE(CLE),
 .ALE(ALE),
 .WE_n(WE_n),
 .RE_n(RE_n),
 .CE_n(CE_n),
 .R_nB(R_nB),

 .CLK(clk),
 .RES(rst),

 .BF_sel(BF_sel),
 .BF_ad (BF_ad ),
 .BF_din(BF_din),
 .BF_we (BF_we ),
 .RWA   (RWA   ), 

 .BF_dou(BF_dou),
 .PErr(PErr), 
 .EErr(EErr), 
 .RErr(RErr),
      
 .nfc_cmd (nfc_cmd ), 
 .nfc_strt(nfc_strt),  
 .nfc_done(nfc_done)
);


flash_interface nand_flash(
    .DIO(DIO),
    .CLE(CLE),
    .ALE(ALE),
    .WE_n(WE_n),
    .RE_n(RE_n),
    .CE_n(CE_n),
    .R_nB(R_nB),
    .rst(rst)
);










task reset_cycle;    
begin
    @(posedge clk) ;

    nfc_cmd=3'b011;
    nfc_strt=1'b1;

    @(posedge clk) ;
    nfc_strt=1'b0;    
   wait(nfc_done);
   @(posedge clk) ;
   nfc_cmd=3'b111;                                           
   $display($time,"  %m  \t \t  << reset function over >>"); 
    
end      
endtask 


task erase_cycle;
    input [15:0]  address; 
begin

    @(posedge clk) ;
    #3;
    RWA=address;
    nfc_cmd=3'b100;
    nfc_strt=1'b1;

    @(posedge clk) ;
    #3;
    nfc_strt=1'b0; 
    @(posedge clk) ;

   wait(nfc_done);
   @(posedge clk) ;
   nfc_cmd=3'b111;

   if(EErr)                                         
     $display($time,"  %m  \t \t  << erase error >>");    
   else                                             
     $display($time,"  %m  \t \t  << erase no error >>"); 
    
end      
endtask 








task write_cycle;
    input [15:0]  address; 
    integer i;
begin

    @(posedge clk) ;
    #3;
    RWA=address;
    nfc_cmd=3'b001;
    nfc_strt=1'b1;
    BF_sel=1'b1;
    @(posedge clk) ;
    #3;
    nfc_strt=1'b0; 
    BF_ad=0;
    for(i=0;i<2048;i=i+1) begin    
       @(posedge clk) ; 
       #3;      
       BF_we=1'b1;
       memory[i]=$random % 256; 
       BF_din<=memory[i];
       BF_ad<=#3 i; 
    end 
   @(posedge clk) ;
   @(posedge clk) ;
   #3;
   BF_we=1'b0;  
   wait(nfc_done);
   @(posedge clk) ;
   #3;
   nfc_cmd=3'b111;
   BF_sel=1'b0;
   if(PErr)                                         
     $display($time,"  %m  \t \t  << Writing error >>");    
   else                                             
     $display($time,"  %m  \t \t  << Writing no error >>"); 
    
end      
endtask 








task read_cycle;
    input [15:0]  address; 
    integer i;
    
begin
    @(posedge clk) ;
    #3;
    RWA=address;
    nfc_cmd=3'b010;
    nfc_strt=1'b1;
    BF_sel=1'b1;
    BF_we=1'b0;
    BF_ad=#3 0;
    @(posedge clk) ;
    #3;
    nfc_strt=1'b0;  
    @(posedge clk) ;  
   wait(nfc_done);
   @(posedge clk) ;
   #3;
   nfc_cmd=3'b111;
   BF_ad<=#3 BF_ad+1;
   for(i=0;i<2048;i=i+1) begin       
       @(posedge clk) ;
       temp<=memory[i];    
       BF_ad<=#3 BF_ad+1; 
    end 
   
   if(RErr)                                         
     $display($time,"  %m  \t \t  << ecc error >>");    
   else                                             
     $display($time,"  %m  \t \t  << ecc no error >>"); 
    
end      
endtask 


task read_id_cycle;
    input [15:0]  address; 
    
begin
    @(posedge clk) ;
    #3;
    RWA=address;
    nfc_cmd=3'b101;
    nfc_strt=1'b1;
    BF_sel=1'b1;
    @(posedge clk) ;
    #3;
    nfc_strt=1'b0;    
    @(posedge clk) ;
   wait(nfc_done);
   @(posedge clk) ;
   nfc_cmd=3'b111;
      $display($time,"  %m  \t \t  << read id function over >>"); 
    
end      
endtask 





                                                                        
task kill_time;                                                         
  begin                                                                 
    @(posedge clk);                                                 
    @(posedge clk);                                                 
    @(posedge clk);                                                 
    @(posedge clk);                                                 
    @(posedge clk);                                                 
  end                                                                   
endtask
                                                                        


 
endmodule
module nfcm_tb();


 reg clk,rst;


 wire [7:0] DIO;
 wire CLE;
 wire ALE;
 wire WE_n;
 wire RE_n;
 wire CE_n;
 wire R_nB;

 reg BF_sel;
 reg [10:0] BF_ad;
 reg [7:0] BF_din;
 reg BF_we;
 reg [15:0] RWA;
 wire [7:0] BF_dou;

 wire PErr ;
 wire EErr ;
 wire RErr ;

 reg [2:0] nfc_cmd;
 reg nfc_strt;
 wire nfc_done;

  
reg[7:0] memory[0:2047];

reg [7:0] temp;
  
GSR GSR_INST(.GSR(1'b1));
PUR PUR_INST(.PUR(1'b1));  

parameter period=16;


initial begin
  clk <= 1'b0;
	rst  <= 1'b1;
	BF_sel<=1'b0;                   
	BF_ad<=0;            
	BF_din<=0;            
	BF_we<=0;                   
	RWA<=0; 
	nfc_cmd<=3'b111;
	nfc_strt<=1'b0; 
	temp<=8'h24;



	#300;
	rst<=1'b0;

	kill_time; 
	kill_time; 

	reset_cycle;

	kill_time; 
	kill_time; 
	
	erase_cycle(16'h1234);
	
	kill_time; 
	kill_time;
	
	write_cycle(16'h1234);
	
	kill_time; 
	kill_time;
	
	read_cycle(16'h1234);
	
	kill_time; 
	kill_time;

	read_id_cycle(16'h0000);
	
	kill_time; 
	kill_time;
	
        #1000;
	$stop;
	
	end

always
   #(period/2) clk <= ~clk;
   

nfcm_top nfcm(
 .DIO(DIO),
 .CLE(CLE),
 .ALE(ALE),
 .WE_n(WE_n),
 .RE_n(RE_n),
 .CE_n(CE_n),
 .R_nB(R_nB),

 .CLK(clk),
 .RES(rst),

 .BF_sel(BF_sel),
 .BF_ad (BF_ad ),
 .BF_din(BF_din),
 .BF_we (BF_we ),
 .RWA   (RWA   ), 

 .BF_dou(BF_dou),
 .PErr(PErr), 
 .EErr(EErr), 
 .RErr(RErr),
      
 .nfc_cmd (nfc_cmd ), 
 .nfc_strt(nfc_strt),  
 .nfc_done(nfc_done)
);


flash_interface nand_flash(
    .DIO(DIO),
    .CLE(CLE),
    .ALE(ALE),
    .WE_n(WE_n),
    .RE_n(RE_n),
    .CE_n(CE_n),
    .R_nB(R_nB),
    .rst(rst)
);










task reset_cycle;    
begin
    @(posedge clk) ;

    nfc_cmd=3'b011;
    nfc_strt=1'b1;

    @(posedge clk) ;
    nfc_strt=1'b0;    
   wait(nfc_done);
   @(posedge clk) ;
   nfc_cmd=3'b111;                                           
   $display($time,"  %m  \t \t  << reset function over >>"); 
    
end      
endtask 


task erase_cycle;
    input [15:0]  address; 
begin

    @(posedge clk) ;
    #3;
    RWA=address;
    nfc_cmd=3'b100;
    nfc_strt=1'b1;

    @(posedge clk) ;
    #3;
    nfc_strt=1'b0; 
    @(posedge clk) ;

   wait(nfc_done);
   @(posedge clk) ;
   nfc_cmd=3'b111;

   if(EErr)                                         
     $display($time,"  %m  \t \t  << erase error >>");    
   else                                             
     $display($time,"  %m  \t \t  << erase no error >>"); 
    
end      
endtask 








task write_cycle;
    input [15:0]  address; 
    integer i;
begin

    @(posedge clk) ;
    #3;
    RWA=address;
    nfc_cmd=3'b001;
    nfc_strt=1'b1;
    BF_sel=1'b1;
    @(posedge clk) ;
    #3;
    nfc_strt=1'b0; 
    BF_ad=0;
    for(i=0;i<2048;i=i+1) begin    
       @(posedge clk) ; 
       #3;      
       BF_we=1'b1;
       memory[i]=$random % 256; 
       BF_din<=memory[i];
       BF_ad<=#3 i; 
    end 
   @(posedge clk) ;
   @(posedge clk) ;
   #3;
   BF_we=1'b0;  
   wait(nfc_done);
   @(posedge clk) ;
   #3;
   nfc_cmd=3'b111;
   BF_sel=1'b0;
   if(PErr)                                         
     $display($time,"  %m  \t \t  << Writing error >>");    
   else                                             
     $display($time,"  %m  \t \t  << Writing no error >>"); 
    
end      
endtask 








task read_cycle;
    input [15:0]  address; 
    integer i;
    
begin
    @(posedge clk) ;
    #3;
    RWA=address;
    nfc_cmd=3'b010;
    nfc_strt=1'b1;
    BF_sel=1'b1;
    BF_we=1'b0;
    BF_ad=#3 0;
    @(posedge clk) ;
    #3;
    nfc_strt=1'b0;  
    @(posedge clk) ;  
   wait(nfc_done);
   @(posedge clk) ;
   #3;
   nfc_cmd=3'b111;
   BF_ad<=#3 BF_ad+1;
   for(i=0;i<2048;i=i+1) begin       
       @(posedge clk) ;
       temp<=memory[i];    
       BF_ad<=#3 BF_ad+1; 
    end 
   
   if(RErr)                                         
     $display($time,"  %m  \t \t  << ecc error >>");    
   else                                             
     $display($time,"  %m  \t \t  << ecc no error >>"); 
    
end      
endtask 


task read_id_cycle;
    input [15:0]  address; 
    
begin
    @(posedge clk) ;
    #3;
    RWA=address;
    nfc_cmd=3'b101;
    nfc_strt=1'b1;
    BF_sel=1'b1;
    @(posedge clk) ;
    #3;
    nfc_strt=1'b0;    
    @(posedge clk) ;
   wait(nfc_done);
   @(posedge clk) ;
   nfc_cmd=3'b111;
      $display($time,"  %m  \t \t  << read id function over >>"); 
    
end      
endtask 





                                                                        
task kill_time;                                                         
  begin                                                                 
    @(posedge clk);                                                 
    @(posedge clk);                                                 
    @(posedge clk);                                                 
    @(posedge clk);                                                 
    @(posedge clk);                                                 
  end                                                                   
endtask
                                                                        


 
endmodule