data/full_repos/permissive/103842408/rtl/test/sram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/103842408/rtl/test/sram.v:49: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'b_en\' generates 4 bits.\n                                                                       : ... In instance sram\n  if(b_en) begin\n  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sram(
    input   wire    [255*8:0] memfile,
    input   wire              gclk,
    input   wire              resetn,
    input   wire [addr_w-1:0] addr,
    output  reg  [data_w-1:0] rdata,
    input   wire [data_w-1:0] wdata,
    input   wire  [3:0]       b_en,
    input   wire              w_en,
    output  wire              stall,
    output  reg               error
);

parameter   addr_w  = 32;
parameter   data_w  = 32;
parameter   size    = 8192;


wire [addr_w-1:0] addr_idx;

assign addr_idx = addr >> (data_w <= 32? 2 : 3);


integer i;


reg  [data_w-1:0] memory [0: size-1];


reg  [data_w-1:0] n_output_data;


assign stall = 1'b0;


always @(posedge gclk) begin
    
  error = 1'b0;
    
  if(b_en) begin

    if(addr < size) begin
        n_output_data = memory[addr_idx];
    end else if(resetn) begin

        $display("ERROR: Requested read addr %h out of range.", addr);
        error = 1'b1;
    end

  end
end

always @(posedge gclk) begin : do_writes
if(|b_en && w_en == 1'b1) begin
  if(addr < size) begin
    memory[addr_idx][31:24] = b_en[3] ? wdata[31:24] : memory[addr_idx][31:24];
    memory[addr_idx][23:16] = b_en[2] ? wdata[23:16] : memory[addr_idx][23:16];
    memory[addr_idx][15: 8] = b_en[1] ? wdata[15: 8] : memory[addr_idx][15: 8];
    memory[addr_idx][ 7: 0] = b_en[0] ? wdata[ 7: 0] : memory[addr_idx][ 7: 0];
  end else if(resetn) begin

      $display("ERROR: Requested write addr %h out of range.", addr);
      error = 1'b1;
  end
end
end



always @(posedge gclk, negedge resetn) begin
    if(resetn == 1'b0) begin
        rdata = {data_w{1'b0}};
    end else if(|b_en == 1'b1) begin

        rdata = n_output_data;
    end
end



initial begin
    n_output_data = 32'b0;
    
    for(i = 0; i < size; i = i + 1) begin
        memory[i] = {data_w{1'bx}};
    end

end


always @(posedge resetn) begin
    if(memfile != "") begin
        $display("In Reset -> Loading memory file: %s", memfile);
        $readmemh(memfile, memory, 0, size-1);
    end else begin
        $display("No memory file specified: Memory will be blank.");
    end
end


endmodule
module sram(
    input   wire    [255*8:0] memfile,
    input   wire              gclk,
    input   wire              resetn,
    input   wire [addr_w-1:0] addr,
    output  reg  [data_w-1:0] rdata,
    input   wire [data_w-1:0] wdata,
    input   wire  [3:0]       b_en,
    input   wire              w_en,
    output  wire              stall,
    output  reg               error
);


parameter   addr_w  = 32;
parameter   data_w  = 32;
parameter   size    = 8192;


wire [addr_w-1:0] addr_idx;

assign addr_idx = addr >> (data_w <= 32? 2 : 3);


integer i;


reg  [data_w-1:0] memory [0: size-1];


reg  [data_w-1:0] n_output_data;


assign stall = 1'b0;


always @(posedge gclk) begin
    
  error = 1'b0;
    
  if(b_en) begin

    if(addr < size) begin
        n_output_data = memory[addr_idx];
    end else if(resetn) begin

        $display("ERROR: Requested read addr %h out of range.", addr);
        error = 1'b1;
    end

  end
end

always @(posedge gclk) begin : do_writes
if(|b_en && w_en == 1'b1) begin
  if(addr < size) begin
    memory[addr_idx][31:24] = b_en[3] ? wdata[31:24] : memory[addr_idx][31:24];
    memory[addr_idx][23:16] = b_en[2] ? wdata[23:16] : memory[addr_idx][23:16];
    memory[addr_idx][15: 8] = b_en[1] ? wdata[15: 8] : memory[addr_idx][15: 8];
    memory[addr_idx][ 7: 0] = b_en[0] ? wdata[ 7: 0] : memory[addr_idx][ 7: 0];
  end else if(resetn) begin

      $display("ERROR: Requested write addr %h out of range.", addr);
      error = 1'b1;
  end
end
end



always @(posedge gclk, negedge resetn) begin
    if(resetn == 1'b0) begin
        rdata = {data_w{1'b0}};
    end else if(|b_en == 1'b1) begin

        rdata = n_output_data;
    end
end



initial begin
    n_output_data = 32'b0;
    
    for(i = 0; i < size; i = i + 1) begin
        memory[i] = {data_w{1'bx}};
    end

end


always @(posedge resetn) begin
    if(memfile != "") begin
        $display("In Reset -> Loading memory file: %s", memfile);
        $readmemh(memfile, memory, 0, size-1);
    end else begin
        $display("No memory file specified: Memory will be blank.");
    end
end


endmodule