data/full_repos/permissive/148201731/fpga/rtl/42s16320.v
 line:58: before: "["
1: b'%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:144: Unsupported or unknown PLI call: $timeformat\n        $timeformat (-9, 1, " ns", 12);\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:149: syntax error, unexpected \'@\'\n        @ (posedge Clk) begin\n        ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:153: syntax error, unexpected \'@\'\n        @ (negedge Clk) begin\n        ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:191: syntax error, unexpected \'[\', expecting IDENTIFIER\n            Count_precharge[0] = Count_precharge[0] + 1;\n                           ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:194: syntax error, unexpected \'[\', expecting IDENTIFIER\n            Count_precharge[1] = Count_precharge[1] + 1;\n                           ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:197: syntax error, unexpected \'[\', expecting IDENTIFIER\n            Count_precharge[2] = Count_precharge[2] + 1;\n                           ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:200: syntax error, unexpected \'[\', expecting IDENTIFIER\n            Count_precharge[3] = Count_precharge[3] + 1;\n                           ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:205: syntax error, unexpected \'[\', expecting IDENTIFIER\n            RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;\n                                ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:208: syntax error, unexpected \'[\', expecting IDENTIFIER\n            RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;\n                                ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:211: syntax error, unexpected \'[\', expecting IDENTIFIER\n            RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;\n                                ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:214: syntax error, unexpected \'[\', expecting IDENTIFIER\n            RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;\n                                ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:218: syntax error, unexpected \'=\', expecting IDENTIFIER\n        MRD_chk = MRD_chk + 1;\n                ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:225: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: tRC violation during Auto Refresh", $time);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:231: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:236: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:241: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:245: syntax error, unexpected \'=\', expecting IDENTIFIER\n            RC_chk = $time;\n                   ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:251: syntax error, unexpected \'=\', expecting IDENTIFIER\n            Mode_reg = Addr;\n                     ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:255: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:261: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:266: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: tRC violation during Load Mode Register", $time);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:271: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:275: syntax error, unexpected \'=\', expecting IDENTIFIER\n            MRD_chk = 0;\n                    ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:286: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:291: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:295: syntax error, unexpected \'=\', expecting IDENTIFIER\n                Act_b0 = 1\'b1;\n                       ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:306: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:311: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:315: syntax error, unexpected \'=\', expecting IDENTIFIER\n                Act_b1 = 1\'b1;\n                       ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:326: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:331: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:335: syntax error, unexpected \'=\', expecting IDENTIFIER\n                Act_b2 = 1\'b1;\n                       ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:347: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:352: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:356: syntax error, unexpected \'=\', expecting IDENTIFIER\n                Act_b3 = 1\'b1;\n                       ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:366: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:371: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:376: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:380: syntax error, unexpected \'=\', expecting IDENTIFIER\n            RRD_chk = $time;\n                    ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:388: syntax error, unexpected $display\n                $display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:393: syntax error, unexpected \'=\', expecting IDENTIFIER\n                Act_b0 = 1\'b0;\n                       ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:399: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:404: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tDPL violation during Precharge", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:410: syntax error, unexpected \'=\', expecting IDENTIFIER\n                Act_b1 = 1\'b0;\n                       ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:416: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:421: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tDPL violation during Precharge", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:427: syntax error, unexpected \'=\', expecting IDENTIFIER\n                Act_b2 = 1\'b0;\n                       ^\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:433: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:438: syntax error, unexpected $display\n                    $display ("%m : at time %t ERROR: tDPL violation during Precharge", $time);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/148201731/fpga/rtl/42s16320.v:444: syntax error, unexpected \'=\', expecting IDENTIFIER\n                Act_b3 = 1\'b0;\n                       ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
module IS42S16320 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);

    parameter addr_bits =      13;
    parameter data_bits =      16;
    parameter col_bits  =       10;
    parameter mem_sizes = 8388608;

    inout     [data_bits - 1 : 0] Dq;
    input     [addr_bits - 1 : 0] Addr;
    input                 [1 : 0] Ba;
    input                         Clk;
    input                         Cke;
    input                         Cs_n;
    input                         Ras_n;
    input                         Cas_n;
    input                         We_n;
    input                 [1 : 0] Dqm;
    
    reg       [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank3 [0 : mem_sizes];

    reg                   [1 : 0] Bank_addr [0 : 3];
    reg        [col_bits - 1 : 0] Col_addr [0 : 3];
    reg                   [3 : 0] Command [0 : 3];
    reg                   [1 : 0] Dqm_reg0, Dqm_reg1;
    reg       [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;

    reg       [addr_bits - 1 : 0] Mode_reg;
    reg       [data_bits - 1 : 0] Dq_reg, Dq_dqm;
    reg        [col_bits - 1 : 0] Col_temp, Burst_counter;

    reg                           Act_b0, Act_b1, Act_b2, Act_b3;
    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;

    reg                   [1 : 0] Bank_precharge       [0 : 3];
    reg                           A10_precharge        [0 : 3];
    reg                           Auto_precharge       [0 : 3];
    reg                           Read_precharge       [0 : 3];
    reg                           Write_precharge      [0 : 3];
    reg                           RW_interrupt_read    [0 : 3];
    reg                           RW_interrupt_write   [0 : 3];
    reg                   [1 : 0] RW_interrupt_bank;
    integer                       RW_interrupt_counter [0 : 3];
    integer                       Count_precharge      [0 : 3];

    reg                           Data_in_enable;
    reg                           Data_out_enable;

    reg                   [1 : 0] Bank, Prev_bank;
    reg       [addr_bits - 1 : 0] Row;
    reg        [col_bits - 1 : 0] Col, Col_brst;


    reg                           CkeZ, Sys_clk;


    wire      Active_enable    = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
    wire      Aref_enable      = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;
    wire      Burst_term       = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
    wire      Mode_reg_enable  = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
    wire      Prech_enable     = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
    wire      Read_enable      = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
    wire      Write_enable     = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;


    wire      Burst_length_1   = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
    wire      Burst_length_2   = ~Mode_reg[2] & ~Mode_reg[1] &  Mode_reg[0];
    wire      Burst_length_4   = ~Mode_reg[2] &  Mode_reg[1] & ~Mode_reg[0];
    wire      Burst_length_8   = ~Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
    wire      Burst_length_f   =  Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];


    wire      Cas_latency_2    = ~Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
    wire      Cas_latency_3    = ~Mode_reg[6] &  Mode_reg[5] &  Mode_reg[4];


    wire      Write_burst_mode = Mode_reg[9];

    wire      Dq_chk           = Sys_clk & Data_in_enable;

    assign    Dq               = Dq_reg;


    `define   ACT       0
    `define   NOP       1
    `define   READ      2
    `define   WRITE     3
    `define   PRECH     4
    `define   A_REF     5
    `define   BST       6
    `define   LMR       7
/
        if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) 
begin
            if ((($time - RAS_chk0 >= tRAS) &&                               

               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) ||
                 (Burst_length_2 == 1'b1                              && Count_precharge [0] >= 2) ||
                 (Burst_length_4 == 1'b1                              && Count_precharge [0] >= 4) ||
                 (Burst_length_8 == 1'b1                              && Count_precharge [0] >= 8))) ||
                 (RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0]  >= 1)) begin
                    Auto_precharge[0] = 1'b0;
                    Write_precharge[0] = 1'b0;
                    RW_interrupt_write[0] = 1'b0;
                    Pc_b0 = 1'b1;
                    Act_b0 = 1'b0;
                    RP_chk0 = $time + tDPL;
            end
        end
        if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) 
begin
            if ((($time - RAS_chk1 >= tRAS) &&                               

               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) ||
                 (Burst_length_2 == 1'b1                              && Count_precharge [1] >= 2) ||
                 (Burst_length_4 == 1'b1                              && Count_precharge [1] >= 4) ||
                 (Burst_length_8 == 1'b1                              && Count_precharge [1] >= 8))) ||
                 (RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1]  >= 1)) begin
                    Auto_precharge[1] = 1'b0;
                    Write_precharge[1] = 1'b0;
                    RW_interrupt_write[1] = 1'b0;
                    Pc_b1 = 1'b1;
                    Act_b1 = 1'b0;
                    RP_chk1 = $time + tDPL;
            end
        end
        if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) 
begin
            if ((($time - RAS_chk2 >= tRAS) &&                               

               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) ||
                 (Burst_length_2 == 1'b1                              && Count_precharge [2] >= 2) ||
                 (Burst_length_4 == 1'b1                              && Count_precharge [2] >= 4) ||
                 (Burst_length_8 == 1'b1                              && Count_precharge [2] >= 8))) ||
                 (RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2]  >= 1)) begin
                    Auto_precharge[2] = 1'b0;
                    Write_precharge[2] = 1'b0;
                    RW_interrupt_write[2] = 1'b0;
                    Pc_b2 = 1'b1;
                    Act_b2 = 1'b0;
                    RP_chk2 = $time + tDPL;
                    end

        end
        if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) 
begin
            if ((($time - RAS_chk3 >= tRAS) &&                               

               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) ||
                 (Burst_length_2 == 1'b1                              && Count_precharge [3] >= 2) ||
                 (Burst_length_4 == 1'b1                              && Count_precharge [3] >= 4) ||
                 (Burst_length_8 == 1'b1                              && Count_precharge [3] >= 8))) ||
                 (RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3]  >= 1)) begin
                    Auto_precharge[3] = 1'b0;
                    Write_precharge[3] = 1'b0;
                    RW_interrupt_write[3] = 1'b0;
                    Pc_b3 = 1'b1;
                    Act_b3 = 1'b0;
                    RP_chk3 = $time + tDPL;
            end
        end






        if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) 
begin
            if ((($time - RAS_chk0 >= tRAS) &&                               

                ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) ||      

                 (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
                 (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
                 (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
                 (RW_interrupt_read[0] == 1'b1)) begin                       

                    Pc_b0 = 1'b1;
                    Act_b0 = 1'b0;
                    RP_chk0 = $time;
                    Auto_precharge[0] = 1'b0;
                    Read_precharge[0] = 1'b0;
                    RW_interrupt_read[0] = 1'b0;
            end
        end
        if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) 
begin
            if ((($time - RAS_chk1 >= tRAS) &&
                ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
                 (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
                 (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
                 (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
                 (RW_interrupt_read[1] == 1'b1)) begin
                    Pc_b1 = 1'b1;
                    Act_b1 = 1'b0;
                    RP_chk1 = $time;
                    Auto_precharge[1] = 1'b0;
                    Read_precharge[1] = 1'b0;
                    RW_interrupt_read[1] = 1'b0;
            end
        end
        if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) 
begin
            if ((($time - RAS_chk2 >= tRAS) &&
                ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
                 (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
                 (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
                 (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
                 (RW_interrupt_read[2] == 1'b1)) begin
                    Pc_b2 = 1'b1;
                    Act_b2 = 1'b0;
                    RP_chk2 = $time;
                    Auto_precharge[2] = 1'b0;
                    Read_precharge[2] = 1'b0;
                    RW_interrupt_read[2] = 1'b0;
            end
        end
        if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) 
begin
            if ((($time - RAS_chk3 >= tRAS) &&
                ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
                 (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
                 (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
                 (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
                 (RW_interrupt_read[3] == 1'b1)) begin
                    Pc_b3 = 1'b1;
                    Act_b3 = 1'b0;
                    RP_chk3 = $time;
                    Auto_precharge[3] = 1'b0;
                    Read_precharge[3] = 1'b0;
                    RW_interrupt_read[3] = 1'b0;
            end
        end


        if (Command[0] == `PRECH) begin
            if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
                if (Data_out_enable == 1'b1) begin
                    Data_out_enable = 1'b0;
                end
            end
        end else if (Command[0] == `BST) begin
            if (Data_out_enable == 1'b1) begin
                Data_out_enable = 1'b0;
            end
        end

        if (Data_out_enable == 1'b0) begin
            Dq_reg <= #tOH {data_bits{1'bz}};
        end


        if (Command[0] == `READ) begin
            Bank = Bank_addr[0];
            Col = Col_addr[0];
            Col_brst = Col_addr[0];
            case (Bank_addr[0])
                2'b00 : Row = B0_row_addr;
                2'b01 : Row = B1_row_addr;
                2'b10 : Row = B2_row_addr;
                2'b11 : Row = B3_row_addr;
            endcase
            Burst_counter = 0;
            Data_in_enable = 1'b0;
            Data_out_enable = 1'b1;
        end else if (Command[0] == `WRITE) begin
            Bank = Bank_addr[0];
            Col = Col_addr[0];
            Col_brst = Col_addr[0];
            case (Bank_addr[0])
                2'b00 : Row = B0_row_addr;
                2'b01 : Row = B1_row_addr;
                2'b10 : Row = B2_row_addr;
                2'b11 : Row = B3_row_addr;
            endcase
            Burst_counter = 0;
            Data_in_enable = 1'b1;
            Data_out_enable = 1'b0;
        end


        if (Data_in_enable == 1'b1) begin                                   


            case (Bank)
                2'b00 : Dq_dqm = Bank0 [{Row, Col}];
                2'b01 : Dq_dqm = Bank1 [{Row, Col}];
                2'b10 : Dq_dqm = Bank2 [{Row, Col}];
                2'b11 : Dq_dqm = Bank3 [{Row, Col}];
            endcase


            if (Dqm[0] == 1'b0) begin
                Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
            end
            if (Dqm[1] == 1'b0) begin
                Dq_dqm [15 : 8] = Dq [15 : 8];
             end
 


            case (Bank)
                2'b00 : Bank0 [{Row, Col}] = Dq_dqm;
                2'b01 : Bank1 [{Row, Col}] = Dq_dqm;
                2'b10 : Bank2 [{Row, Col}] = Dq_dqm;
                2'b11 : Bank3 [{Row, Col}] = Dq_dqm;
            endcase

            if (Dqm !== 2'b11) begin

                DPL_chkm [Bank] = $time;
            end


            #tHZ Burst_decode;

        end else if (Data_out_enable == 1'b1) begin                         


            case (Bank)
                2'b00 : Dq_dqm = Bank0[{Row, Col}];
                2'b01 : Dq_dqm = Bank1[{Row, Col}];
                2'b10 : Dq_dqm = Bank2[{Row, Col}];
                2'b11 : Dq_dqm = Bank3[{Row, Col}];
            endcase


            if (Dqm_reg0 [0] == 1'b1) begin
                Dq_dqm [ 7 : 0] = 8'bz;
            end
            if (Dqm_reg0 [1] == 1'b1) begin
                Dq_dqm [15 : 8] = 8'bz;
            end
  
            if (Dqm_reg0 !== 2'b11) begin
                Dq_reg = #tAC Dq_dqm;
            end else begin
                Dq_reg = #tHZ {data_bits{1'bz}};
            end


            Burst_decode;
        end
    end


    task Burst_decode;
        begin

            Burst_counter = Burst_counter + 1;


            if (Mode_reg[3] == 1'b0) begin                                  

                Col_temp = Col + 1;
            end else if (Mode_reg[3] == 1'b1) begin                         

                Col_temp[2] =  Burst_counter[2] ^  Col_brst[2];
                Col_temp[1] =  Burst_counter[1] ^  Col_brst[1];
                Col_temp[0] =  Burst_counter[0] ^  Col_brst[0];
            end


            if (Burst_length_2) begin                                       

                Col [0] = Col_temp [0];
            end else if (Burst_length_4) begin                              

                Col [1 : 0] = Col_temp [1 : 0];
            end else if (Burst_length_8) begin                              

                Col [2 : 0] = Col_temp [2 : 0];
            end else begin                                                  

                Col = Col_temp;
            end


            if (Write_burst_mode == 1'b1) begin
                Data_in_enable = 1'b0;
            end


            if (Burst_length_1 == 1'b1) begin
                if (Burst_counter >= 1) begin
                    Data_in_enable = 1'b0;
                    Data_out_enable = 1'b0;
                end
            end else if (Burst_length_2 == 1'b1) begin
                if (Burst_counter >= 2) begin
                    Data_in_enable = 1'b0;
                    Data_out_enable = 1'b0;
                end
            end else if (Burst_length_4 == 1'b1) begin
                if (Burst_counter >= 4) begin
                    Data_in_enable = 1'b0;
                    Data_out_enable = 1'b0;
                end
            end else if (Burst_length_8 == 1'b1) begin
                if (Burst_counter >= 8) begin
                    Data_in_enable = 1'b0;
                    Data_out_enable = 1'b0;
                end
            end
        end
    endtask


    specify
        specparam
            tAH  =  0.8,
            tAS  =  1.5,
            tCH  =  2.5,
            tCL  =  2.5,
            tCK  =  7.0,
            tDH  =  0.8,
            tDS  =  1.5,
            tCKH =  0.8,
            tCKS =  1.5,
            tCMH =  0.8,
            tCMS =  1.5;

        $width    (posedge Clk,           tCH);
        $width    (negedge Clk,           tCL);
        $period   (negedge Clk,           tCK);
        $period   (posedge Clk,           tCK);
        $setuphold(posedge Clk,    Cke,   tCKS, tCKH);
        $setuphold(posedge Clk,    Cs_n,  tCMS, tCMH);
        $setuphold(posedge Clk,    Cas_n, tCMS, tCMH);
        $setuphold(posedge Clk,    Ras_n, tCMS, tCMH);
        $setuphold(posedge Clk,    We_n,  tCMS, tCMH);
        $setuphold(posedge Clk,    Addr,  tAS,  tAH);
        $setuphold(posedge Clk,    Ba,    tAS,  tAH);
        $setuphold(posedge Clk,    Dqm,   tCMS, tCMH);
        $setuphold(posedge Dq_chk, Dq,    tDS,  tDH);
    endspecify

endmodule
module IS42S16320 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);


    parameter addr_bits =      13;
    parameter data_bits =      16;
    parameter col_bits  =       10;
    parameter mem_sizes = 8388608;

    inout     [data_bits - 1 : 0] Dq;
    input     [addr_bits - 1 : 0] Addr;
    input                 [1 : 0] Ba;
    input                         Clk;
    input                         Cke;
    input                         Cs_n;
    input                         Ras_n;
    input                         Cas_n;
    input                         We_n;
    input                 [1 : 0] Dqm;
    
    reg       [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank3 [0 : mem_sizes];

    reg                   [1 : 0] Bank_addr [0 : 3];
    reg        [col_bits - 1 : 0] Col_addr [0 : 3];
    reg                   [3 : 0] Command [0 : 3];
    reg                   [1 : 0] Dqm_reg0, Dqm_reg1;
    reg       [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;

    reg       [addr_bits - 1 : 0] Mode_reg;
    reg       [data_bits - 1 : 0] Dq_reg, Dq_dqm;
    reg        [col_bits - 1 : 0] Col_temp, Burst_counter;

    reg                           Act_b0, Act_b1, Act_b2, Act_b3;
    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;

    reg                   [1 : 0] Bank_precharge       [0 : 3];
    reg                           A10_precharge        [0 : 3];
    reg                           Auto_precharge       [0 : 3];
    reg                           Read_precharge       [0 : 3];
    reg                           Write_precharge      [0 : 3];
    reg                           RW_interrupt_read    [0 : 3];
    reg                           RW_interrupt_write   [0 : 3];
    reg                   [1 : 0] RW_interrupt_bank;
    integer                       RW_interrupt_counter [0 : 3];
    integer                       Count_precharge      [0 : 3];

    reg                           Data_in_enable;
    reg                           Data_out_enable;

    reg                   [1 : 0] Bank, Prev_bank;
    reg       [addr_bits - 1 : 0] Row;
    reg        [col_bits - 1 : 0] Col, Col_brst;


    reg                           CkeZ, Sys_clk;


    wire      Active_enable    = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
    wire      Aref_enable      = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;
    wire      Burst_term       = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
    wire      Mode_reg_enable  = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
    wire      Prech_enable     = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
    wire      Read_enable      = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
    wire      Write_enable     = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;


    wire      Burst_length_1   = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
    wire      Burst_length_2   = ~Mode_reg[2] & ~Mode_reg[1] &  Mode_reg[0];
    wire      Burst_length_4   = ~Mode_reg[2] &  Mode_reg[1] & ~Mode_reg[0];
    wire      Burst_length_8   = ~Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
    wire      Burst_length_f   =  Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];


    wire      Cas_latency_2    = ~Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
    wire      Cas_latency_3    = ~Mode_reg[6] &  Mode_reg[5] &  Mode_reg[4];


    wire      Write_burst_mode = Mode_reg[9];

    wire      Dq_chk           = Sys_clk & Data_in_enable;

    assign    Dq               = Dq_reg;


    `define   ACT       0
    `define   NOP       1
    `define   READ      2
    `define   WRITE     3
    `define   PRECH     4
    `define   A_REF     5
    `define   BST       6
    `define   LMR       7
/
        if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) 
begin
            if ((($time - RAS_chk0 >= tRAS) &&                               

               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) ||
                 (Burst_length_2 == 1'b1                              && Count_precharge [0] >= 2) ||
                 (Burst_length_4 == 1'b1                              && Count_precharge [0] >= 4) ||
                 (Burst_length_8 == 1'b1                              && Count_precharge [0] >= 8))) ||
                 (RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0]  >= 1)) begin
                    Auto_precharge[0] = 1'b0;
                    Write_precharge[0] = 1'b0;
                    RW_interrupt_write[0] = 1'b0;
                    Pc_b0 = 1'b1;
                    Act_b0 = 1'b0;
                    RP_chk0 = $time + tDPL;
            end
        end
        if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) 
begin
            if ((($time - RAS_chk1 >= tRAS) &&                               

               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) ||
                 (Burst_length_2 == 1'b1                              && Count_precharge [1] >= 2) ||
                 (Burst_length_4 == 1'b1                              && Count_precharge [1] >= 4) ||
                 (Burst_length_8 == 1'b1                              && Count_precharge [1] >= 8))) ||
                 (RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1]  >= 1)) begin
                    Auto_precharge[1] = 1'b0;
                    Write_precharge[1] = 1'b0;
                    RW_interrupt_write[1] = 1'b0;
                    Pc_b1 = 1'b1;
                    Act_b1 = 1'b0;
                    RP_chk1 = $time + tDPL;
            end
        end
        if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) 
begin
            if ((($time - RAS_chk2 >= tRAS) &&                               

               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) ||
                 (Burst_length_2 == 1'b1                              && Count_precharge [2] >= 2) ||
                 (Burst_length_4 == 1'b1                              && Count_precharge [2] >= 4) ||
                 (Burst_length_8 == 1'b1                              && Count_precharge [2] >= 8))) ||
                 (RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2]  >= 1)) begin
                    Auto_precharge[2] = 1'b0;
                    Write_precharge[2] = 1'b0;
                    RW_interrupt_write[2] = 1'b0;
                    Pc_b2 = 1'b1;
                    Act_b2 = 1'b0;
                    RP_chk2 = $time + tDPL;
                    end

        end
        if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) 
begin
            if ((($time - RAS_chk3 >= tRAS) &&                               

               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) ||
                 (Burst_length_2 == 1'b1                              && Count_precharge [3] >= 2) ||
                 (Burst_length_4 == 1'b1                              && Count_precharge [3] >= 4) ||
                 (Burst_length_8 == 1'b1                              && Count_precharge [3] >= 8))) ||
                 (RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3]  >= 1)) begin
                    Auto_precharge[3] = 1'b0;
                    Write_precharge[3] = 1'b0;
                    RW_interrupt_write[3] = 1'b0;
                    Pc_b3 = 1'b1;
                    Act_b3 = 1'b0;
                    RP_chk3 = $time + tDPL;
            end
        end






        if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) 
begin
            if ((($time - RAS_chk0 >= tRAS) &&                               

                ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) ||      

                 (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
                 (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
                 (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
                 (RW_interrupt_read[0] == 1'b1)) begin                       

                    Pc_b0 = 1'b1;
                    Act_b0 = 1'b0;
                    RP_chk0 = $time;
                    Auto_precharge[0] = 1'b0;
                    Read_precharge[0] = 1'b0;
                    RW_interrupt_read[0] = 1'b0;
            end
        end
        if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) 
begin
            if ((($time - RAS_chk1 >= tRAS) &&
                ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
                 (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
                 (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
                 (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
                 (RW_interrupt_read[1] == 1'b1)) begin
                    Pc_b1 = 1'b1;
                    Act_b1 = 1'b0;
                    RP_chk1 = $time;
                    Auto_precharge[1] = 1'b0;
                    Read_precharge[1] = 1'b0;
                    RW_interrupt_read[1] = 1'b0;
            end
        end
        if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) 
begin
            if ((($time - RAS_chk2 >= tRAS) &&
                ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
                 (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
                 (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
                 (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
                 (RW_interrupt_read[2] == 1'b1)) begin
                    Pc_b2 = 1'b1;
                    Act_b2 = 1'b0;
                    RP_chk2 = $time;
                    Auto_precharge[2] = 1'b0;
                    Read_precharge[2] = 1'b0;
                    RW_interrupt_read[2] = 1'b0;
            end
        end
        if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) 
begin
            if ((($time - RAS_chk3 >= tRAS) &&
                ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
                 (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
                 (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
                 (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
                 (RW_interrupt_read[3] == 1'b1)) begin
                    Pc_b3 = 1'b1;
                    Act_b3 = 1'b0;
                    RP_chk3 = $time;
                    Auto_precharge[3] = 1'b0;
                    Read_precharge[3] = 1'b0;
                    RW_interrupt_read[3] = 1'b0;
            end
        end


        if (Command[0] == `PRECH) begin
            if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
                if (Data_out_enable == 1'b1) begin
                    Data_out_enable = 1'b0;
                end
            end
        end else if (Command[0] == `BST) begin
            if (Data_out_enable == 1'b1) begin
                Data_out_enable = 1'b0;
            end
        end

        if (Data_out_enable == 1'b0) begin
            Dq_reg <= #tOH {data_bits{1'bz}};
        end


        if (Command[0] == `READ) begin
            Bank = Bank_addr[0];
            Col = Col_addr[0];
            Col_brst = Col_addr[0];
            case (Bank_addr[0])
                2'b00 : Row = B0_row_addr;
                2'b01 : Row = B1_row_addr;
                2'b10 : Row = B2_row_addr;
                2'b11 : Row = B3_row_addr;
            endcase
            Burst_counter = 0;
            Data_in_enable = 1'b0;
            Data_out_enable = 1'b1;
        end else if (Command[0] == `WRITE) begin
            Bank = Bank_addr[0];
            Col = Col_addr[0];
            Col_brst = Col_addr[0];
            case (Bank_addr[0])
                2'b00 : Row = B0_row_addr;
                2'b01 : Row = B1_row_addr;
                2'b10 : Row = B2_row_addr;
                2'b11 : Row = B3_row_addr;
            endcase
            Burst_counter = 0;
            Data_in_enable = 1'b1;
            Data_out_enable = 1'b0;
        end


        if (Data_in_enable == 1'b1) begin                                   


            case (Bank)
                2'b00 : Dq_dqm = Bank0 [{Row, Col}];
                2'b01 : Dq_dqm = Bank1 [{Row, Col}];
                2'b10 : Dq_dqm = Bank2 [{Row, Col}];
                2'b11 : Dq_dqm = Bank3 [{Row, Col}];
            endcase


            if (Dqm[0] == 1'b0) begin
                Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
            end
            if (Dqm[1] == 1'b0) begin
                Dq_dqm [15 : 8] = Dq [15 : 8];
             end
 


            case (Bank)
                2'b00 : Bank0 [{Row, Col}] = Dq_dqm;
                2'b01 : Bank1 [{Row, Col}] = Dq_dqm;
                2'b10 : Bank2 [{Row, Col}] = Dq_dqm;
                2'b11 : Bank3 [{Row, Col}] = Dq_dqm;
            endcase

            if (Dqm !== 2'b11) begin

                DPL_chkm [Bank] = $time;
            end


            #tHZ Burst_decode;

        end else if (Data_out_enable == 1'b1) begin                         


            case (Bank)
                2'b00 : Dq_dqm = Bank0[{Row, Col}];
                2'b01 : Dq_dqm = Bank1[{Row, Col}];
                2'b10 : Dq_dqm = Bank2[{Row, Col}];
                2'b11 : Dq_dqm = Bank3[{Row, Col}];
            endcase


            if (Dqm_reg0 [0] == 1'b1) begin
                Dq_dqm [ 7 : 0] = 8'bz;
            end
            if (Dqm_reg0 [1] == 1'b1) begin
                Dq_dqm [15 : 8] = 8'bz;
            end
  
            if (Dqm_reg0 !== 2'b11) begin
                Dq_reg = #tAC Dq_dqm;
            end else begin
                Dq_reg = #tHZ {data_bits{1'bz}};
            end


            Burst_decode;
        end
    end


    task Burst_decode;
        begin

            Burst_counter = Burst_counter + 1;


            if (Mode_reg[3] == 1'b0) begin                                  

                Col_temp = Col + 1;
            end else if (Mode_reg[3] == 1'b1) begin                         

                Col_temp[2] =  Burst_counter[2] ^  Col_brst[2];
                Col_temp[1] =  Burst_counter[1] ^  Col_brst[1];
                Col_temp[0] =  Burst_counter[0] ^  Col_brst[0];
            end


            if (Burst_length_2) begin                                       

                Col [0] = Col_temp [0];
            end else if (Burst_length_4) begin                              

                Col [1 : 0] = Col_temp [1 : 0];
            end else if (Burst_length_8) begin                              

                Col [2 : 0] = Col_temp [2 : 0];
            end else begin                                                  

                Col = Col_temp;
            end


            if (Write_burst_mode == 1'b1) begin
                Data_in_enable = 1'b0;
            end


            if (Burst_length_1 == 1'b1) begin
                if (Burst_counter >= 1) begin
                    Data_in_enable = 1'b0;
                    Data_out_enable = 1'b0;
                end
            end else if (Burst_length_2 == 1'b1) begin
                if (Burst_counter >= 2) begin
                    Data_in_enable = 1'b0;
                    Data_out_enable = 1'b0;
                end
            end else if (Burst_length_4 == 1'b1) begin
                if (Burst_counter >= 4) begin
                    Data_in_enable = 1'b0;
                    Data_out_enable = 1'b0;
                end
            end else if (Burst_length_8 == 1'b1) begin
                if (Burst_counter >= 8) begin
                    Data_in_enable = 1'b0;
                    Data_out_enable = 1'b0;
                end
            end
        end
    endtask


    specify
        specparam
            tAH  =  0.8,
            tAS  =  1.5,
            tCH  =  2.5,
            tCL  =  2.5,
            tCK  =  7.0,
            tDH  =  0.8,
            tDS  =  1.5,
            tCKH =  0.8,
            tCKS =  1.5,
            tCMH =  0.8,
            tCMS =  1.5;

        $width    (posedge Clk,           tCH);
        $width    (negedge Clk,           tCL);
        $period   (negedge Clk,           tCK);
        $period   (posedge Clk,           tCK);
        $setuphold(posedge Clk,    Cke,   tCKS, tCKH);
        $setuphold(posedge Clk,    Cs_n,  tCMS, tCMH);
        $setuphold(posedge Clk,    Cas_n, tCMS, tCMH);
        $setuphold(posedge Clk,    Ras_n, tCMS, tCMH);
        $setuphold(posedge Clk,    We_n,  tCMS, tCMH);
        $setuphold(posedge Clk,    Addr,  tAS,  tAH);
        $setuphold(posedge Clk,    Ba,    tAS,  tAH);
        $setuphold(posedge Clk,    Dqm,   tCMS, tCMH);
        $setuphold(posedge Dq_chk, Dq,    tDS,  tDH);
    endspecify

endmodule