data/full_repos/permissive/132304455/src/clock_divider.v
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data/verilator_xmls/8ac46796-9762-4f97-a464-c5ed203a2638.xml
module clock_divider(
    output clkout,
    input clkin
    );
    parameter
        rate = 1;
    reg [31:0] counter = 1;
    reg temp_clk = 0;
    always @(posedge(clkin))
    begin
        if(counter == rate)
        begin
            counter <= 1;
            temp_clk <= ~temp_clk;
        end
        else
        begin
            counter <= counter + 1;
        end
    end
    assign clkout = temp_clk;
endmodule
module clock_divider(
    output clkout,
    input clkin
    );

    parameter
        rate = 1;
    reg [31:0] counter = 1;
    reg temp_clk = 0;
    always @(posedge(clkin))
    begin
        if(counter == rate)
        begin
            counter <= 1;
            temp_clk <= ~temp_clk;
        end
        else
        begin
            counter <= counter + 1;
        end
    end
    assign clkout = temp_clk;
endmodule