data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/zynq_fifo/zf_slave_settings.v
data/verilator_xmls/31f3873f-d26f-42df-bcd2-1ddfe27f9a95.xml
module zf_slave_settings
#(
    parameter CONFIG_BASE = 32'h40000000
)
(
    input clk,
    input rst,




    input [31:0] AXI_AWADDR,
    input AXI_AWVALID,
    output AXI_AWREADY,
    input [31:0] AXI_WDATA,
    input [3:0] AXI_WSTRB,
    input AXI_WVALID,
    output AXI_WREADY,
    output [1:0] AXI_BRESP,
    output AXI_BVALID,
    input AXI_BREADY,




    output reg [31:0] addr,
    output reg [31:0] data,
    output strobe,

    output [31:0] debug
);









    localparam STATE_ADDR = 0;
    localparam STATE_DATA = 1;
    localparam STATE_WRITE = 2;

    reg [1:0] state;

    always @(posedge clk) begin
        if (rst) begin
            state <= STATE_ADDR;
            addr <= 0;
            data <= 0;
        end
        else case (state)

        STATE_ADDR: begin
            if (AXI_AWVALID && AXI_AWREADY) begin
                addr <= (AXI_AWADDR - CONFIG_BASE);
                state <= STATE_DATA;
            end
        end

        STATE_DATA: begin
            if (AXI_WVALID && AXI_WREADY) begin
                data <= AXI_WDATA;
                state <= STATE_WRITE;
            end
        end

        STATE_WRITE: begin
            state <= STATE_ADDR;
        end

        default: state <= STATE_ADDR;

        endcase
    end

    assign strobe = (state == STATE_WRITE);


    assign AXI_AWREADY = (state == STATE_ADDR);
    assign AXI_WREADY = (state == STATE_DATA);
    assign AXI_BRESP = 0;
    assign AXI_BVALID = AXI_BREADY;

endmodule
module zf_slave_settings
#(
    parameter CONFIG_BASE = 32'h40000000
)
(
    input clk,
    input rst,




    input [31:0] AXI_AWADDR,
    input AXI_AWVALID,
    output AXI_AWREADY,
    input [31:0] AXI_WDATA,
    input [3:0] AXI_WSTRB,
    input AXI_WVALID,
    output AXI_WREADY,
    output [1:0] AXI_BRESP,
    output AXI_BVALID,
    input AXI_BREADY,




    output reg [31:0] addr,
    output reg [31:0] data,
    output strobe,

    output [31:0] debug
);










    localparam STATE_ADDR = 0;
    localparam STATE_DATA = 1;
    localparam STATE_WRITE = 2;

    reg [1:0] state;

    always @(posedge clk) begin
        if (rst) begin
            state <= STATE_ADDR;
            addr <= 0;
            data <= 0;
        end
        else case (state)

        STATE_ADDR: begin
            if (AXI_AWVALID && AXI_AWREADY) begin
                addr <= (AXI_AWADDR - CONFIG_BASE);
                state <= STATE_DATA;
            end
        end

        STATE_DATA: begin
            if (AXI_WVALID && AXI_WREADY) begin
                data <= AXI_WDATA;
                state <= STATE_WRITE;
            end
        end

        STATE_WRITE: begin
            state <= STATE_ADDR;
        end

        default: state <= STATE_ADDR;

        endcase
    end

    assign strobe = (state == STATE_WRITE);


    assign AXI_AWREADY = (state == STATE_ADDR);
    assign AXI_WREADY = (state == STATE_DATA);
    assign AXI_BRESP = 0;
    assign AXI_BVALID = AXI_BREADY;

endmodule