data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv
Syntax Error
1: b'%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:264: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'shift_amt\' generates 7 bits.\n                                                                                         : ... In instance BSW_KernelControl\n        if(inn == shift_amt) begin\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:276: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'shift_amt\' generates 7 bits.\n                                                                                         : ... In instance BSW_KernelControl\n        if(inn == shift_amt) begin\n               ^~\n%Error: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:288: Cannot find file containing module: \'FIFO\'\nFIFO#(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/160991228/src/hdl/BSW,data/full_repos/permissive/160991228/FIFO\n             data/full_repos/permissive/160991228/src/hdl/BSW,data/full_repos/permissive/160991228/FIFO.v\n             data/full_repos/permissive/160991228/src/hdl/BSW,data/full_repos/permissive/160991228/FIFO.sv\n             FIFO\n             FIFO.v\n             FIFO.sv\n             obj_dir/FIFO\n             obj_dir/FIFO.v\n             obj_dir/FIFO.sv\n%Error: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:302: Cannot find file containing module: \'FIFO\'\nFIFO#(\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:404: Operator ASSIGNDLY expects 512 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n            data1[j] <= {C_M_AXI_DATA_WIDTH{1\'b0}};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:417: Operator ASSIGNDLY expects 512 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    data1[j] <= {C_M_AXI_DATA_WIDTH{1\'b0}};\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:418: Operator ASSIGNDLY expects 512 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    data2[j] <= {C_M_AXI_DATA_WIDTH{1\'b0}};\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:419: Operator ASSIGNDLY expects 512 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    data_reg[j] <= {C_M_AXI_DATA_WIDTH{1\'b0}};\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:423: Operator ASSIGNDLY expects 512 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    data1[j] <= {C_M_AXI_DATA_WIDTH{1\'b0}};\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:424: Operator ASSIGNDLY expects 512 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    data2[j] <= {C_M_AXI_DATA_WIDTH{1\'b0}};\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:425: Operator ASSIGNDLY expects 512 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    data_reg[j] <= {C_M_AXI_DATA_WIDTH{1\'b0}};\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:446: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                        right_shift_num[j] <= (axi_ref_off[j] & MASK);\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:458: Operator SUB expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 7 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    left_shift_num[j] <= DATA_WIDTH_BYTE - right_shift_num[j];\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:458: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    left_shift_num[j] <= DATA_WIDTH_BYTE - right_shift_num[j];\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:516: Operator ASSIGNDLY expects 512 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    data2[j] <= {C_M_AXI_DATA_WIDTH{1\'b0}};\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:525: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    right_shift_num[j] <= (axi_query_off[j] & MASK);\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:530: Operator SUB expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 7 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    left_shift_num[j] <= DATA_WIDTH_BYTE - right_shift_num[j];\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:530: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    left_shift_num[j] <= DATA_WIDTH_BYTE - right_shift_num[j];\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:676: Operator EQ expects 32 bits on the LHS, but LHS\'s ARRAYSEL generates 4 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    if(iter_ref[j] == NUM_BRAM_LOOPS-1) begin\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:734: Operator EQ expects 32 bits on the LHS, but LHS\'s ARRAYSEL generates 4 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    if(iter_query[j] == NUM_BRAM_LOOPS-1) begin\n                                     ^~\n%Error: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:772: Cannot find file containing module: \'BSW_Array\'\nBSW_Array #(\n^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:913: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n            read_byte_length_params[j] <= 32\'d0;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:921: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    read_byte_length_params[j] <= 32\'d0;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:930: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    read_byte_length_params[j] <= 32\'d0;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:936: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h40\' generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    read_byte_length_params[j] <= 32\'d64;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:937: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'j\' generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    read_addr_offset_params[j] <= batch_id + (j << 6) + (tile_iter << 8);\n                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:937: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'tile_iter\' generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    read_addr_offset_params[j] <= batch_id + (j << 6) + (tile_iter << 8);\n                                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:942: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    read_byte_length_params[j] <= 32\'d0;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:957: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h40\' generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    read_byte_length_params[j] <= 32\'d64;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:958: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'j\' generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    read_addr_offset_params[j] <= batch_params + (j << 6) + (tile_iter << 8);\n                                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:958: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'tile_iter\' generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    read_addr_offset_params[j] <= batch_params + (j << 6) + (tile_iter << 8);\n                                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:963: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                         : ... In instance BSW_KernelControl\n                    read_byte_length_params[j] <= 32\'d0;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1078: Operator ADD expects 64 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                    read_byte_length_logic[j] <= axi_ref_len[j] + (axi_ref_off[j] & MASK);\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1078: Operator AND expects 64 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                    read_byte_length_logic[j] <= axi_ref_len[j] + (axi_ref_off[j] & MASK);\n                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1078: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'MASK\' generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                    read_byte_length_logic[j] <= axi_ref_len[j] + (axi_ref_off[j] & MASK);\n                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1079: Operator ADD expects 64 bits on the RHS, but RHS\'s ARRAYSEL generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                    read_addr_offset_reg[j] <= ref_seq + axi_ref_off[j];\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1084: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                    read_byte_length_logic[j] <= 32\'d0;\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1109: Operator ADD expects 64 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                    read_byte_length_logic[j] <= axi_query_len[j] + (axi_query_off[j] & MASK);\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1109: Operator AND expects 64 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                    read_byte_length_logic[j] <= axi_query_len[j] + (axi_query_off[j] & MASK);\n                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1109: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'MASK\' generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                    read_byte_length_logic[j] <= axi_query_len[j] + (axi_query_off[j] & MASK);\n                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1110: Operator ADD expects 64 bits on the RHS, but RHS\'s ARRAYSEL generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                    read_addr_offset_reg[j] <= query_seq + axi_query_off[j];\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1116: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                    read_byte_length_logic[j] <= 32\'d0;\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1262: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'batch_size\' generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                write_byte_length_logic[0] <= batch_size << 6;\n                                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/BSW/BSW_KernelControl.sv:1268: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                          : ... In instance BSW_KernelControl\n                write_byte_length_logic[0] <= 32\'d0;\n                                           ^~\n%Error: Exiting due to 3 error(s), 41 warning(s)\n'
function [C_AXIS_TDATA_WIDTH-1:0] left_shift(input [C_AXIS_TDATA_WIDTH-1:0] inp, input [6:0] shift_amt);
    logic  [C_AXIS_TDATA_WIDTH-1:0] outp;

    for(inn = 0; inn < 64; inn = inn+1) begin
        if(inn == shift_amt) begin
            outp = (inp << (BYTE_WIDTH*inn));
        end
    end

    return outp;
endfunction
function [C_AXIS_TDATA_WIDTH-1:0] left_shift(input [C_AXIS_TDATA_WIDTH-1:0] inp, input [6:0] shift_amt);

    logic  [C_AXIS_TDATA_WIDTH-1:0] outp;

    for(inn = 0; inn < 64; inn = inn+1) begin
        if(inn == shift_amt) begin
            outp = (inp << (BYTE_WIDTH*inn));
        end
    end

    return outp;
endfunction