data/full_repos/permissive/123304708/src/common/dmr_ext.v
None: at end of input
1: b'%Error: data/full_repos/permissive/123304708/src/common/dmr_ext.v:2: Cannot find include file: ././define/instr_def.v\n`include "././define/instr_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123304708/src/common,data/full_repos/permissive/123304708/././define/instr_def.v\n             data/full_repos/permissive/123304708/src/common,data/full_repos/permissive/123304708/././define/instr_def.v.v\n             data/full_repos/permissive/123304708/src/common,data/full_repos/permissive/123304708/././define/instr_def.v.sv\n             ././define/instr_def.v\n             ././define/instr_def.v.v\n             ././define/instr_def.v.sv\n             obj_dir/././define/instr_def.v\n             obj_dir/././define/instr_def.v.v\n             obj_dir/././define/instr_def.v.sv\n%Error: data/full_repos/permissive/123304708/src/common/dmr_ext.v:14: Define or directive not defined: \'`OP_LB\'\n      `OP_LB: \n      ^~~~~~\n%Error: data/full_repos/permissive/123304708/src/common/dmr_ext.v:14: syntax error, unexpected \':\', expecting endcase\n      `OP_LB: \n            ^\n%Error: data/full_repos/permissive/123304708/src/common/dmr_ext.v:23: Define or directive not defined: \'`OP_LBU\'\n      `OP_LBU:\n      ^~~~~~~\n%Error: data/full_repos/permissive/123304708/src/common/dmr_ext.v:32: Define or directive not defined: \'`OP_LH\'\n      `OP_LH:\n      ^~~~~~\n%Error: data/full_repos/permissive/123304708/src/common/dmr_ext.v:39: Define or directive not defined: \'`OP_LHU\'\n      `OP_LHU: \n      ^~~~~~~\n%Error: data/full_repos/permissive/123304708/src/common/dmr_ext.v:40: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      begin\n      ^~~~~\n%Error: data/full_repos/permissive/123304708/src/common/dmr_ext.v:46: Define or directive not defined: \'`OP_LW\'\n      `OP_LW: dout = din;\n      ^~~~~~\n%Warning-ENDLABEL: data/full_repos/permissive/123304708/src/common/dmr_ext.v:46: End label \'dout\' does not match begin label \'\'\n      `OP_LW: dout = din;\n              ^~~~\n                   ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/123304708/src/common/dmr_ext.v:46: syntax error, unexpected \'=\'\n      `OP_LW: dout = din;\n                   ^\n%Error: Cannot continue\n'
module dmr_ext(
  input [1:0] control,
  input [5:0] OP,
  input [31:0] din,
  output reg[31:0] dout
  );
  
  always@(*)
  begin
    case(OP)
      `OP_LB: 
      begin
        case(control)
          2'b00: dout = {{24{din[7]}},din[7:0]};
          2'b01: dout = {{24{din[15]}},din[15:8]};
          2'b10: dout = {{24{din[23]}},din[23:16]};
          2'b11: dout = {{24{din[31]}},din[31:24]};
        endcase
      end
      `OP_LBU:
      begin
        case(control)
          2'b00: dout = {24'b0,din[7:0]};
          2'b01: dout = {24'b0,din[15:8]};
          2'b10: dout = {24'b0,din[23:16]};
          2'b11: dout = {24'b0,din[31:24]};
        endcase
      end
      `OP_LH:
      begin
        if(control[1])
          dout = {{16{din[31]}},din[31:16]};
        else
          dout = {{16{din[15]}},din[15:0]};
      end
      `OP_LHU: 
      begin
        if(control[1])
          dout = {16'b0,din[31:16]};
        else
          dout = {16'b0,din[15:0]};
      end
      `OP_LW: dout = din;
    endcase
  end
  
endmodule
module dmr_ext(
  input [1:0] control,
  input [5:0] OP,
  input [31:0] din,
  output reg[31:0] dout
  );

  
  always@(*)
  begin
    case(OP)
      `OP_LB: 
      begin
        case(control)
          2'b00: dout = {{24{din[7]}},din[7:0]};
          2'b01: dout = {{24{din[15]}},din[15:8]};
          2'b10: dout = {{24{din[23]}},din[23:16]};
          2'b11: dout = {{24{din[31]}},din[31:24]};
        endcase
      end
      `OP_LBU:
      begin
        case(control)
          2'b00: dout = {24'b0,din[7:0]};
          2'b01: dout = {24'b0,din[15:8]};
          2'b10: dout = {24'b0,din[23:16]};
          2'b11: dout = {24'b0,din[31:24]};
        endcase
      end
      `OP_LH:
      begin
        if(control[1])
          dout = {{16{din[31]}},din[31:16]};
        else
          dout = {{16{din[15]}},din[15:0]};
      end
      `OP_LHU: 
      begin
        if(control[1])
          dout = {16'b0,din[31:16]};
        else
          dout = {16'b0,din[15:0]};
      end
      `OP_LW: dout = din;
    endcase
  end
  
endmodule