data/full_repos/permissive/174783592/WallacePL/Wallace16BitPL.v
1: b'%Error: data/full_repos/permissive/174783592/WallacePL/Wallace16BitPL.v:2: Cannot find include file: Wallace8BitPL.v\n`include "Wallace8BitPL.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174783592/WallacePL,data/full_repos/permissive/174783592/Wallace8BitPL.v\n             data/full_repos/permissive/174783592/WallacePL,data/full_repos/permissive/174783592/Wallace8BitPL.v.v\n             data/full_repos/permissive/174783592/WallacePL,data/full_repos/permissive/174783592/Wallace8BitPL.v.sv\n             Wallace8BitPL.v\n             Wallace8BitPL.v.v\n             Wallace8BitPL.v.sv\n             obj_dir/Wallace8BitPL.v\n             obj_dir/Wallace8BitPL.v.v\n             obj_dir/Wallace8BitPL.v.sv\n%Error: data/full_repos/permissive/174783592/WallacePL/Wallace16BitPL.v:3: Cannot find include file: CarrySave8bit.v\n`include "CarrySave8bit.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/174783592/WallacePL/Wallace16BitPL.v:4: Cannot find include file: Adder/sum24bit.sv\n`include "Adder/sum24bit.sv" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module Wallace16BitPL(a,b,p,clk);

	input [15:0] a;
	input [15:0] b;
	input clk;
	output reg [32:0] p;
	

	wire [16:0] prodLowLow;
	wire [24:8] prodHighLow;
	wire [24:8] prodLowHigh;
	wire [32:16] prodHighHigh;

	reg [16:0] prodLowLow_reg;
	reg [24:8] prodHighLow_reg;
	reg [24:8] prodLowHigh_reg;
	reg [32:16] prodHighHigh_reg;
	reg [32:16] prodHighHigh_reg_2;

	Wallace8BitPL w1(a[7:0],b[7:0],prodLowLow,clk);
	Wallace8BitPL w2(a[15:8],b[7:0],prodHighLow,clk);
	Wallace8BitPL w3(a[7:0],b[15:8],prodLowHigh,clk);
	Wallace8BitPL w4(a[15:8],b[15:8],prodHighHigh,clk);

	wire [32:0] outu;


	wire [15:8] u1;
	wire [16:9] v1;
	wire [23:16] u2;
	wire [24:17] v2;

	reg [15:8] u1_reg;
	reg [16:9] v1_reg;
	reg [23:16] u2_reg;
	reg [24:17] v2_reg;











	reg [7:0]prodLowLow_reg_2;
	

	assign outu[7:0] = prodLowLow_reg_2;
	
	

	
        CarrySave8Bit c1(prodLowLow_reg[15:8],prodHighLow_reg[15:8],prodLowHigh_reg[15:8],u1,v1);
        CarrySave8Bit c2(prodHighLow_reg[23:16],prodLowHigh_reg[23:16],prodHighHigh_reg[23:16],u2,v2);



       sum24bit s1({prodHighHigh_reg_2[31:24],u2_reg,u1_reg},{{7{1'b0}},v2_reg,v1_reg,{1'b0}},2'b00,outu[32:8]);


always @ clk
begin


	prodHighHigh_reg <=prodHighHigh;
	prodHighLow_reg <= prodHighLow;
	prodLowHigh_reg <= prodLowHigh;
	prodLowLow_reg <= prodLowLow;



	prodHighHigh_reg_2<= prodHighHigh_reg; 

	u1_reg<=u1;
	u2_reg<=u2;

	v1_reg<=v1;
	v2_reg<=v2;


	prodLowLow_reg_2 <=prodLowLow_reg;




	
    p<= outu; 
end
endmodule
module Wallace16BitPL(a,b,p,clk);


	input [15:0] a;
	input [15:0] b;
	input clk;
	output reg [32:0] p;
	

	wire [16:0] prodLowLow;
	wire [24:8] prodHighLow;
	wire [24:8] prodLowHigh;
	wire [32:16] prodHighHigh;

	reg [16:0] prodLowLow_reg;
	reg [24:8] prodHighLow_reg;
	reg [24:8] prodLowHigh_reg;
	reg [32:16] prodHighHigh_reg;
	reg [32:16] prodHighHigh_reg_2;

	Wallace8BitPL w1(a[7:0],b[7:0],prodLowLow,clk);
	Wallace8BitPL w2(a[15:8],b[7:0],prodHighLow,clk);
	Wallace8BitPL w3(a[7:0],b[15:8],prodLowHigh,clk);
	Wallace8BitPL w4(a[15:8],b[15:8],prodHighHigh,clk);

	wire [32:0] outu;


	wire [15:8] u1;
	wire [16:9] v1;
	wire [23:16] u2;
	wire [24:17] v2;

	reg [15:8] u1_reg;
	reg [16:9] v1_reg;
	reg [23:16] u2_reg;
	reg [24:17] v2_reg;











	reg [7:0]prodLowLow_reg_2;
	

	assign outu[7:0] = prodLowLow_reg_2;
	
	

	
        CarrySave8Bit c1(prodLowLow_reg[15:8],prodHighLow_reg[15:8],prodLowHigh_reg[15:8],u1,v1);
        CarrySave8Bit c2(prodHighLow_reg[23:16],prodLowHigh_reg[23:16],prodHighHigh_reg[23:16],u2,v2);



       sum24bit s1({prodHighHigh_reg_2[31:24],u2_reg,u1_reg},{{7{1'b0}},v2_reg,v1_reg,{1'b0}},2'b00,outu[32:8]);


always @ clk
begin


	prodHighHigh_reg <=prodHighHigh;
	prodHighLow_reg <= prodHighLow;
	prodLowHigh_reg <= prodLowHigh;
	prodLowLow_reg <= prodLowLow;



	prodHighHigh_reg_2<= prodHighHigh_reg; 

	u1_reg<=u1;
	u2_reg<=u2;

	v1_reg<=v1;
	v2_reg<=v2;


	prodLowLow_reg_2 <=prodLowLow_reg;




	
    p<= outu; 
end
endmodule