data/full_repos/permissive/181738725/wavetrace/verilog/uart.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/uart.v:46: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module uart #(
  parameter ClockHz = 80000000,
  parameter Baud    = 115200)
(
  input            clk,
  input            rst,

  input            uart_rx,
  output reg       uart_tx,

  input            din_valid,
  output           din_ready,
  input [7:0]      din_data,

  output reg       dout_valid,
  input            dout_ready,
  output reg [7:0] dout_data
);

`include "util.vh"

  localparam Period      = ClockHz / Baud,
             HalfPeriod  = Period / 2;

  localparam Idle    = 0,
             Active  = 1,
             Error   = 2;

  reg [1:0]                rx_state;
  reg                      rx_sync, uart_rx_d;
  reg [clog2(Period)-1:0]  rx_divider;
  reg [3:0]                rx_count;
  reg [7:0]                rx_data;
  reg                      rx_valid;

  reg [1:0]                tx_state;
  reg [3:0]                tx_count;
  reg [clog2(Period)-1:0]  tx_divider;
  reg [7:0]                tx_data;

  always @(posedge clk) begin


    {rx_sync, uart_rx_d} <= {uart_rx_d, uart_rx};


    rx_valid <= 0;




    case (rx_state)

      Idle:

        if (!rx_sync) begin
          rx_divider <= rx_divider + 1;
          if (rx_divider == HalfPeriod-1) begin
            rx_count   <= 0;
            rx_divider <= 0;
            rx_state   <= Active;
          end
        end else begin

          rx_divider <= 0;
        end

      Active:
        if (rx_divider == Period-1) begin

          rx_data    <= {rx_sync, rx_data[7:1]};
          rx_divider <= 0;
          rx_count   <= rx_count + 1;
          if (rx_count == 7) begin

            rx_valid <= 1;
          end else if (rx_count == 8) begin

            rx_state <= (rx_sync) ? Idle : Error;
          end
        end else begin
          rx_divider <= rx_divider + 1;
        end

      Error:

        if (rx_sync) begin
          rx_state <= Idle;
        end
    endcase


    if (rx_valid) begin
      dout_data  <= rx_data;
    end

    if (rx_valid) begin
      dout_valid <= 1;
    end else if (dout_ready) begin
      dout_valid <= 0;
    end





    case (tx_state)

      Idle:
        if (din_valid) begin

          tx_data    <= din_data;
          uart_tx    <= 0;
          tx_count   <= 0;
          tx_divider <= 0;
          tx_state   <= Active;
        end

      Active:
        if (tx_divider == Period-1) begin
          tx_divider <= 0;
          tx_count   <= tx_count + 1;
          if (tx_count == 9) begin

            tx_state   <= Idle;
          end else if (tx_count == 8) begin

            uart_tx    <= 1;
          end else begin

            {tx_data, uart_tx} <= tx_data;
          end
        end else begin
          tx_divider <= tx_divider + 1;
        end

    endcase

    if (rst) begin
      rx_state   <= Idle;
      tx_state   <= Idle;
      uart_tx    <= 1;
      rx_valid   <= 0;
      dout_valid <= 0;
    end
  end

  assign din_ready = (tx_state == Idle);

endmodule
module uart #(
  parameter ClockHz = 80000000,
  parameter Baud    = 115200)
(
  input            clk,
  input            rst,

  input            uart_rx,
  output reg       uart_tx,

  input            din_valid,
  output           din_ready,
  input [7:0]      din_data,

  output reg       dout_valid,
  input            dout_ready,
  output reg [7:0] dout_data
);


`include "util.vh"

  localparam Period      = ClockHz / Baud,
             HalfPeriod  = Period / 2;

  localparam Idle    = 0,
             Active  = 1,
             Error   = 2;

  reg [1:0]                rx_state;
  reg                      rx_sync, uart_rx_d;
  reg [clog2(Period)-1:0]  rx_divider;
  reg [3:0]                rx_count;
  reg [7:0]                rx_data;
  reg                      rx_valid;

  reg [1:0]                tx_state;
  reg [3:0]                tx_count;
  reg [clog2(Period)-1:0]  tx_divider;
  reg [7:0]                tx_data;

  always @(posedge clk) begin


    {rx_sync, uart_rx_d} <= {uart_rx_d, uart_rx};


    rx_valid <= 0;




    case (rx_state)

      Idle:

        if (!rx_sync) begin
          rx_divider <= rx_divider + 1;
          if (rx_divider == HalfPeriod-1) begin
            rx_count   <= 0;
            rx_divider <= 0;
            rx_state   <= Active;
          end
        end else begin

          rx_divider <= 0;
        end

      Active:
        if (rx_divider == Period-1) begin

          rx_data    <= {rx_sync, rx_data[7:1]};
          rx_divider <= 0;
          rx_count   <= rx_count + 1;
          if (rx_count == 7) begin

            rx_valid <= 1;
          end else if (rx_count == 8) begin

            rx_state <= (rx_sync) ? Idle : Error;
          end
        end else begin
          rx_divider <= rx_divider + 1;
        end

      Error:

        if (rx_sync) begin
          rx_state <= Idle;
        end
    endcase


    if (rx_valid) begin
      dout_data  <= rx_data;
    end

    if (rx_valid) begin
      dout_valid <= 1;
    end else if (dout_ready) begin
      dout_valid <= 0;
    end





    case (tx_state)

      Idle:
        if (din_valid) begin

          tx_data    <= din_data;
          uart_tx    <= 0;
          tx_count   <= 0;
          tx_divider <= 0;
          tx_state   <= Active;
        end

      Active:
        if (tx_divider == Period-1) begin
          tx_divider <= 0;
          tx_count   <= tx_count + 1;
          if (tx_count == 9) begin

            tx_state   <= Idle;
          end else if (tx_count == 8) begin

            uart_tx    <= 1;
          end else begin

            {tx_data, uart_tx} <= tx_data;
          end
        end else begin
          tx_divider <= tx_divider + 1;
        end

    endcase

    if (rst) begin
      rx_state   <= Idle;
      tx_state   <= Idle;
      uart_tx    <= 1;
      rx_valid   <= 0;
      dout_valid <= 0;
    end
  end

  assign din_ready = (tx_state == Idle);

endmodule