data/full_repos/permissive/105546923/infra/hdl/ram.v
 line:221: before: "for"
1: b'%Warning-MULTITOP: data/full_repos/permissive/105546923/infra/hdl/ram.v:36: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                          : ... Top module \'ram\'\nmodule ram(\n       ^~~\n                                                                          : ... Top module \'dram_256x16\'\nmodule dram_256x16(\n       ^~~~~~~~~~~\n                                                                          : ... Top module \'dram_512x8\'\nmodule dram_512x8(\n       ^~~~~~~~~~\n                                                                          : ... Top module \'dram_1024x4\'\nmodule dram_1024x4(\n       ^~~~~~~~~~~\n                                                                          : ... Top module \'dram_2048x2\'\nmodule dram_2048x2(\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/ram.v:266: Cannot find file containing module: \'SB_RAM40_4K\'\n   SB_RAM40_4K #(\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K\n             data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.v\n             data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.sv\n             SB_RAM40_4K\n             SB_RAM40_4K.v\n             SB_RAM40_4K.sv\n             obj_dir/SB_RAM40_4K\n             obj_dir/SB_RAM40_4K.v\n             obj_dir/SB_RAM40_4K.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module ram(
	   input 		       clk,
	   input 		       we,
	   input [ADDR_WIDTH - 1 : 0]  waddr,
	   input [DATA_WIDTH - 1 : 0]  d,
	   input 		       re,
	   input [ADDR_WIDTH - 1 : 0]  raddr,
	   output [DATA_WIDTH - 1 : 0] q
	   );
   
   parameter ADDR_WIDTH = 8;
   parameter DATA_WIDTH = 16;
   
   localparam DEPTH = 1  << ADDR_WIDTH;
   
   reg [DATA_WIDTH - 1 : 0] 	       mem [DEPTH - 1 : 0];
   reg [DATA_WIDTH - 1 : 0] 	       _q = 0;
   
   assign q = _q;
   
   always @ (posedge clk)
     begin
	if (we)
	  begin
	     mem[waddr] <= d;
	  end

	if (re)
	  begin
	     _q <= mem[raddr];
	  end
     end
   
endmodule
module ram(
	   input 		       clk,
	   input 		       we,
	   input [ADDR_WIDTH - 1 : 0]  waddr,
	   input [DATA_WIDTH - 1 : 0]  d,
	   input 		       re,
	   input [ADDR_WIDTH - 1 : 0]  raddr,
	   output [DATA_WIDTH - 1 : 0] q
	   );

   
   parameter ADDR_WIDTH = 8;
   parameter DATA_WIDTH = 16;
   
   localparam DEPTH = 1  << ADDR_WIDTH;
   
   reg [DATA_WIDTH - 1 : 0] 	       mem [DEPTH - 1 : 0];
   reg [DATA_WIDTH - 1 : 0] 	       _q = 0;
   
   assign q = _q;
   
   always @ (posedge clk)
     begin
	if (we)
	  begin
	     mem[waddr] <= d;
	  end

	if (re)
	  begin
	     _q <= mem[raddr];
	  end
     end
   
endmodule