data/full_repos/permissive/146975244/Extender14.v
1: b'%Warning-WIDTH: data/full_repos/permissive/146975244/Extender14.v:10: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'IMM15\' generates 15 bits.\n                                                                    : ... In instance Extender14\n  result = IMM15;\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Extender14 (IMM15, result, clock);

input [14:0] IMM15;
input clock;


output reg [31:0] result;

always @ (*) begin
		result = IMM15;
		if(IMM15[14]==1'b1) result = {{17{IMM15[14]}}, IMM15};;
end

endmodule
module Extender14 (IMM15, result, clock);


input [14:0] IMM15;
input clock;


output reg [31:0] result;

always @ (*) begin
		result = IMM15;
		if(IMM15[14]==1'b1) result = {{17{IMM15[14]}}, IMM15};;
end

endmodule