data/full_repos/permissive/143278/ivltests/br965.v
 line:22: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br965.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display(value);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

wire [2:0] value = 2;

shim shim(
  .bit0(value[0]),
  .bit1(value[1]),
  .bit2(value[2])
);

endmodule
module top;


wire [2:0] value = 2;

shim shim(
  .bit0(value[0]),
  .bit1(value[1]),
  .bit2(value[2])
);

endmodule