data/full_repos/permissive/156609923/Arbitraje/testbench.v
 line:4: before: "clk"
1: b'%Error: data/full_repos/permissive/156609923/Arbitraje/testbench.v:2: Cannot find include file: probador.v\n`include "probador.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156609923/Arbitraje,data/full_repos/permissive/156609923/probador.v\n             data/full_repos/permissive/156609923/Arbitraje,data/full_repos/permissive/156609923/probador.v.v\n             data/full_repos/permissive/156609923/Arbitraje,data/full_repos/permissive/156609923/probador.v.sv\n             probador.v\n             probador.v.v\n             probador.v.sv\n             obj_dir/probador.v\n             obj_dir/probador.v.v\n             obj_dir/probador.v.sv\n%Error: data/full_repos/permissive/156609923/Arbitraje/testbench.v:3: Cannot find include file: arbitroEstructural.v\n`include "arbitroEstructural.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156609923/Arbitraje/testbench.v:4: Cannot find include file: arbitro.v\n`include "arbitro.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156609923/Arbitraje/testbench.v:5: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module testbench;

   wire [4:0] VC0_p0, VC1_p0, VC0_p1, VC1_p1;
   wire [3:0] validBits;
   wire [4:0] dataOut_0_condu, dataOut_1_condu, dataOut_0_estru, dataOut_1_estru;
   wire [1:0] validBitsOut_condu, validBitsOut_estru;
   arbitro arbitroCondu(	.clk(clk),
				.reset_L(reset_L),
				.VC0_p0(VC0_p0),
				.VC1_p0(VC1_p0),
				.VC0_p1(VC0_p1),
				.VC1_p1(VC1_p1),
        .validBits(validBits),
        .emptyVC0_p0(emptyVC0_p0),
        .emptyVC1_p0(emptyVC1_p0),
        .emptyVC0_p1(emptyVC0_p1),
        .emptyVC1_p1(emptyVC1_p1),
				.popVC0_0(popVC0_0_condu),
        .popVC1_0(popVC1_0_condu),
        .popVC0_1(popVC0_1_condu),
        .popVC1_1(popVC1_1_condu),
        .dataOut_0(dataOut_0_condu),
        .dataOut_1(dataOut_1_condu),
        .validBitsOut(validBitsOut_condu));


   arbitroEstructural arbitroEstru(	.clk(clk),
       .reset_L(reset_L),
       .VC0_p0(VC0_p0),
       .VC1_p0(VC1_p0),
       .VC0_p1(VC0_p1),
       .VC1_p1(VC1_p1),
        .validBits(validBits),
        .emptyVC0_p0(emptyVC0_p0),
        .emptyVC1_p0(emptyVC1_p0),
        .emptyVC0_p1(emptyVC0_p1),
        .emptyVC1_p1(emptyVC1_p1),
        .popVC0_0(popVC0_0_estru),
        .popVC1_0(popVC1_0_estru),
        .popVC0_1(popVC0_1_estru),
        .popVC1_1(popVC1_1_estru),
        .dataOut_0(dataOut_0_estru),
        .dataOut_1(dataOut_1_estru),
        .validBitsOut(validBitsOut_estru));



   probador prob(	.popVC0_0_condu(popVC0_0_condu),
			.popVC1_0_condu(popVC1_0_condu),
			.popVC0_1_condu(popVC0_1_condu),
      .popVC1_1_condu(popVC1_1_condu),
      .dataOut0_condu(dataOut_0_condu),
      .dataOut1_condu(dataOut_1_condu),
      .validBitsOut_condu(validBitsOut_condu),
      .popVC0_0_estru(popVC0_0_estru),
   		.popVC1_0_estru(popVC1_0_estru),
   		.popVC0_1_estru(popVC0_1_estru),
      .popVC1_1_estru(popVC1_1_estru),
      .dataOut0_estru(dataOut_0_estru),
      .dataOut1_estru(dataOut_1_estru),
      .validBitsOut_estru(validBitsOut_estru),
		 	.clk(clk),
		 	.reset_L(reset_L),
			.VC0_p0(VC0_p0),
      .VC1_p0(VC1_p0),
      .VC0_p1(VC0_p1),
      .VC1_p1(VC1_p1),
      .validBits(validBits),
      .emptyVC0_p0(emptyVC0_p0),
      .emptyVC1_p0(emptyVC1_p0),
      .emptyVC0_p1(emptyVC0_p1),
      .emptyVC1_p1(emptyVC1_p1));

endmodule
module testbench;


   wire [4:0] VC0_p0, VC1_p0, VC0_p1, VC1_p1;
   wire [3:0] validBits;
   wire [4:0] dataOut_0_condu, dataOut_1_condu, dataOut_0_estru, dataOut_1_estru;
   wire [1:0] validBitsOut_condu, validBitsOut_estru;
   arbitro arbitroCondu(	.clk(clk),
				.reset_L(reset_L),
				.VC0_p0(VC0_p0),
				.VC1_p0(VC1_p0),
				.VC0_p1(VC0_p1),
				.VC1_p1(VC1_p1),
        .validBits(validBits),
        .emptyVC0_p0(emptyVC0_p0),
        .emptyVC1_p0(emptyVC1_p0),
        .emptyVC0_p1(emptyVC0_p1),
        .emptyVC1_p1(emptyVC1_p1),
				.popVC0_0(popVC0_0_condu),
        .popVC1_0(popVC1_0_condu),
        .popVC0_1(popVC0_1_condu),
        .popVC1_1(popVC1_1_condu),
        .dataOut_0(dataOut_0_condu),
        .dataOut_1(dataOut_1_condu),
        .validBitsOut(validBitsOut_condu));


   arbitroEstructural arbitroEstru(	.clk(clk),
       .reset_L(reset_L),
       .VC0_p0(VC0_p0),
       .VC1_p0(VC1_p0),
       .VC0_p1(VC0_p1),
       .VC1_p1(VC1_p1),
        .validBits(validBits),
        .emptyVC0_p0(emptyVC0_p0),
        .emptyVC1_p0(emptyVC1_p0),
        .emptyVC0_p1(emptyVC0_p1),
        .emptyVC1_p1(emptyVC1_p1),
        .popVC0_0(popVC0_0_estru),
        .popVC1_0(popVC1_0_estru),
        .popVC0_1(popVC0_1_estru),
        .popVC1_1(popVC1_1_estru),
        .dataOut_0(dataOut_0_estru),
        .dataOut_1(dataOut_1_estru),
        .validBitsOut(validBitsOut_estru));



   probador prob(	.popVC0_0_condu(popVC0_0_condu),
			.popVC1_0_condu(popVC1_0_condu),
			.popVC0_1_condu(popVC0_1_condu),
      .popVC1_1_condu(popVC1_1_condu),
      .dataOut0_condu(dataOut_0_condu),
      .dataOut1_condu(dataOut_1_condu),
      .validBitsOut_condu(validBitsOut_condu),
      .popVC0_0_estru(popVC0_0_estru),
   		.popVC1_0_estru(popVC1_0_estru),
   		.popVC0_1_estru(popVC0_1_estru),
      .popVC1_1_estru(popVC1_1_estru),
      .dataOut0_estru(dataOut_0_estru),
      .dataOut1_estru(dataOut_1_estru),
      .validBitsOut_estru(validBitsOut_estru),
		 	.clk(clk),
		 	.reset_L(reset_L),
			.VC0_p0(VC0_p0),
      .VC1_p0(VC1_p0),
      .VC0_p1(VC0_p1),
      .VC1_p1(VC1_p1),
      .validBits(validBits),
      .emptyVC0_p0(emptyVC0_p0),
      .emptyVC1_p0(emptyVC1_p0),
      .emptyVC0_p1(emptyVC0_p1),
      .emptyVC1_p1(emptyVC1_p1));

endmodule