data/full_repos/permissive/184332405/mux_tb.v
 line:7: before: "ctrl"
1: b'%Error: data/full_repos/permissive/184332405/mux_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("mux.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/184332405/mux_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,DUT);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/184332405/mux_tb.v:15: Unsupported or unknown PLI call: $monitor\n  $monitor("%d %d %d %d | %d", a, b, c, ctrl, s);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/184332405/mux_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #0  a = 8\'b101; b = 8\'d10;  c = 8\'d15; ctrl = 2\'b00;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184332405/mux_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = 8\'b101; b = 8\'d10;  c = 8\'d15; ctrl = 2\'b01;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/mux_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = 8\'b101; b = 8\'d10;  c = 8\'d15; ctrl = 2\'b10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/mux_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = 8\'b101; b = 8\'d10;  c = 8\'d15; ctrl = 2\'b11;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/mux_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #50 $finish;\n  ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_tb;
reg signed [7:0] a;
reg signed [7:0] b;
reg signed [7:0] c;
reg unsigned [1:0] ctrl;
wire signed [7:0] s;

initial
	begin
		$dumpfile("mux.vcd");
		$dumpvars(0,DUT);
		$display("   a    b   c  ctrl   s");
		$monitor("%d %d %d %d | %d", a, b, c, ctrl, s);
		
		#0  a = 8'b101; b = 8'd10;  c = 8'd15; ctrl = 2'b00;
		#50 a = 8'b101; b = 8'd10;  c = 8'd15; ctrl = 2'b01;
		#50 a = 8'b101; b = 8'd10;  c = 8'd15; ctrl = 2'b10;
		#50 a = 8'b101; b = 8'd10;  c = 8'd15; ctrl = 2'b11;
		
		#50 $finish;
	end

mux DUT( s, ctrl, a, b, c );

endmodule
module mux_tb;

reg signed [7:0] a;
reg signed [7:0] b;
reg signed [7:0] c;
reg unsigned [1:0] ctrl;
wire signed [7:0] s;

initial
	begin
		$dumpfile("mux.vcd");
		$dumpvars(0,DUT);
		$display("   a    b   c  ctrl   s");
		$monitor("%d %d %d %d | %d", a, b, c, ctrl, s);
		
		#0  a = 8'b101; b = 8'd10;  c = 8'd15; ctrl = 2'b00;
		#50 a = 8'b101; b = 8'd10;  c = 8'd15; ctrl = 2'b01;
		#50 a = 8'b101; b = 8'd10;  c = 8'd15; ctrl = 2'b10;
		#50 a = 8'b101; b = 8'd10;  c = 8'd15; ctrl = 2'b11;
		
		#50 $finish;
	end

mux DUT( s, ctrl, a, b, c );

endmodule