data/full_repos/permissive/139767240/CodeSnippetsExamples/Function-Mux-16to1-1.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/139767240/CodeSnippetsExamples/Function-Mux-16to1-1.v:18: Little bit endian vector: MSB < LSB of bit range: 0:15\n    input [0:15]W;\n          ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/139767240/CodeSnippetsExamples/Function-Mux-16to1-1.v:24: Little bit endian vector: MSB < LSB of bit range: 0:3\n        input [0:3] X;\n              ^\n%Error: Exiting due to 2 warning(s)\n'
module mux16to1 (W, S16, f);
    input [0:15]W;
    input [3:0] S16;
    output reg f;
    

    function mux4to1;
        input [0:3] X;
        input [1:0] S4;
        
        case (S4)
            0: mux4to1 = X[0];
            1: mux4to1 = X[1];
            2: mux4to1 = X[2];
            3: mux4to1 = X[3];
        endcase
    endfunction
    
    always @(W, S16)
        case (S16[3:2])
            0: f = mux4to1 (W[0:3], S16[1:0]);
            1: f = mux4to1 (W[4:7], S16[1:0]);
            2: f = mux4to1 (W[8:11], S16[1:0]);
            3: f = mux4to1 (W[12:15], S16[1:0]);
        endcase
    
endmodule
module mux16to1 (W, S16, f);

    input [0:15]W;
    input [3:0] S16;
    output reg f;
    

    function mux4to1;
        input [0:3] X;
        input [1:0] S4;
        
        case (S4)
            0: mux4to1 = X[0];
            1: mux4to1 = X[1];
            2: mux4to1 = X[2];
            3: mux4to1 = X[3];
        endcase
    endfunction
    
    always @(W, S16)
        case (S16[3:2])
            0: f = mux4to1 (W[0:3], S16[1:0]);
            1: f = mux4to1 (W[4:7], S16[1:0]);
            2: f = mux4to1 (W[8:11], S16[1:0]);
            3: f = mux4to1 (W[12:15], S16[1:0]);
        endcase
    
endmodule