data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:151: Signal definition not found, creating implicitly: \'ASDLY\'\n                                                                                    : ... Suggested alternative: \'AS20DLY\'\nwire DTACKMOO = AS | ASDLY | DTACK | ~IDEWAIT;\n                     ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:199: Signal definition not found, creating implicitly: \'DSACK1INT\'\n SYSDSACK1 <= DSACK1INT | FPUOP ;\n              ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:284: Signal definition not found, creating implicitly: \'DTACK_INT3\'\n                                                                                    : ... Suggested alternative: \'DSACK1INT\'\nassign DTRIG = (DTACK_INT3| DTQUAL) & DTRIG_SYNC_D5;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:113: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n        ... Looked in:\n             data/full_repos/permissive/132486588/rtl/tf530bus,data/full_repos/permissive/132486588/FDCP\n             data/full_repos/permissive/132486588/rtl/tf530bus,data/full_repos/permissive/132486588/FDCP.v\n             data/full_repos/permissive/132486588/rtl/tf530bus,data/full_repos/permissive/132486588/FDCP.sv\n             FDCP\n             FDCP.v\n             FDCP.sv\n             obj_dir/FDCP\n             obj_dir/FDCP.v\n             obj_dir/FDCP.sv\n%Error: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:123: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:132: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:141: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:152: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:161: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:170: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:179: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:254: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: data/full_repos/permissive/132486588/rtl/tf530bus/tf530_bus.v:263: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: Exiting due to 10 error(s), 3 warning(s)\n'
module tf530_bus(


		input 	 CLKCPU,
		input 	 CLK7M,
        

        
        input     INTSIG,


		input [2:0] 	 FC,
		input [1:0] 	 SIZ,
		input         A0,   
		input [23:12] A,
		

		input 	 AS20,
		input 	 DS20,
		input 	 RW20,
		output 	 [1:0] DSACK,
		

		
		output 	 AVEC,
		output   BERR,
		

		output	 CPCS,
		input    CPSENSE,
        


        input        IDEWAIT,
        output [1:0] IDECS,
        output       IOR,
        output       IOW,
        output       OVR,


		output 	 AS,
		output 	 LDS,
		output 	 UDS,
		output 	 RW00,
		input 	 DTACK,


		input 	 BG20,
		output 	 BG,
		input 	 BGACK,


		output 	 VMA,
		input 	 VPA,
		output reg E

       );

wire DS20DLY;
wire AS20DLY;

reg SYSDSACK1 = 1'b1;
reg RW20DLY = 1'b1;
reg CLK7MB2 = 1'b1;
reg BGACKD1 = 1'b1;
reg BGACKD2 = 1'b1;
reg DTQUAL = 1'b1;

reg [3:0] Q = 'hF;

reg VMA_SYNC = 1'b1;

initial begin 

	E = 'b0;
	
end

wire DTRIG;

wire CPUSPACE = &FC;


wire FPUOP = CPUSPACE & ({A[19:16]} === {4'b0010});
wire BKPT = CPUSPACE & ({A[19:16]} === {4'b0000});
wire IACK = CPUSPACE & ({A[19:16]} === {4'b1111});
wire DTACKPRELIM = CLK7M | CLK7MB2;
wire GAYLE_IDE = ({A[23:15]} != {8'hDA,1'b0}) | AS20 | FPUOP;

assign CPCS = ~FPUOP | AS20;

FDCP #(.INIT(1'b1)) 
	AS20DLY_FF (
		.Q(AS20DLY),
		.C(CLK7M),
		.CLR(1'b0),
		.D(AS20),
		.PRE(AS20 | FPUOP | ~INTSIG)
);


FDCP #(.INIT(1'b1)) 
	ASDLY_FF (
		.Q(ASDLY),
		.C(CLK7M),
		.CLR(1'b0),
		.D(AS),
		.PRE(AS20)
);

FDCP #(.INIT(1'b1)) 
	DS20DLY_FF (
		.Q(DS20DLY),
		.C(CLK7M),
		.CLR(1'b0),
		.D(DS20),
		.PRE(DS20 | FPUOP | ~INTSIG)
);

FDCP #(.INIT(1'b1)) 
	DTTRIG1_FF (
		.Q(DSACK1INT),
		.C(~DTRIG),
		.CLR(1'b0),
		.D(AS | ~INTSIG),
		.PRE(AS)
);


wire DTACKMOO = AS | ASDLY | DTACK | ~IDEWAIT;
FDCP #(.INIT(1'b1)) 
	DTTACK1_FF (
		.Q(DTACK_INT1),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(DTACKMOO),
		.PRE(DTACKMOO | ~INTSIG)
);

FDCP #(.INIT(1'b1)) 
	DTTACK2_FF (
		.Q(DTACK_INT2),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(DTACK_INT1),
		.PRE(DTACK_INT1)
);

FDCP #(.INIT(1'b1)) 
	DTTACK3_FF (
		.Q(DTACK_INT3),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(DTACK_INT2),
		.PRE(DTACK_INT2)
);

FDCP #(.INIT(1'b1)) 
	DTTACK4_FF (
		.Q(DTACK_INT4),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(DTACK_INT3),
		.PRE(DTACK_INT3)
);



reg DTRIG_SYNC = 1'b1;
reg DTRIG_SYNC_D = 1'b1;
reg DTRIG_SYNC_D2 = 1'b1;
reg DTRIG_SYNC_D3 = 1'b1;
reg DTRIG_SYNC_D4 = 1'b1;
reg DTRIG_SYNC_D5 = 1'b1;

always @(posedge CLKCPU) begin 

	SYSDSACK1 <= DSACK1INT | FPUOP ;
    DTRIG_SYNC <= ~Q[3] | VMA_SYNC | ~DTRIG_SYNC | ~DTRIG_SYNC_D |  ~DTRIG_SYNC_D2 | ~DTRIG_SYNC_D3 | ~DTRIG_SYNC_D4 | ~DTRIG_SYNC_D5;
    DTRIG_SYNC_D <= DTRIG_SYNC;
    DTRIG_SYNC_D2 <= DTRIG_SYNC_D;
    DTRIG_SYNC_D3 <= DTRIG_SYNC_D2;
    DTRIG_SYNC_D4 <= DTRIG_SYNC_D3;
    DTRIG_SYNC_D5 <= DTRIG_SYNC_D4;
    
end

always @(posedge CLK7M) begin
     
	DTQUAL 	<= AS20 | FPUOP;
	RW20DLY <= RW20;
     
    BGACKD1 <= BGACK;
    BGACKD2 <= BGACKD1;
    

    CLK7MB2 <= ~CLK7MB2;
    
   if (Q == 'd9) begin

      VMA_SYNC <= 1'b1;
      Q <= 'd0;

   end else begin

      Q <= Q + 'd1;

      if (Q == 'd4) begin
            E <= 'b1;       
      end

      if (Q == 'd8) begin
            E <= 'b0;
      end

      if (Q == 'd2) begin

         VMA_SYNC <=  (VPA | CPUSPACE);
		 
      end 
      
   end
 
end


   

wire DSHOLD = {ASDLY,AS, RW00} == {1'b1,1'b0,1'b0};
wire IOR_INT = ~RW00 | GAYLE_IDE | DSHOLD;
wire IOW_INT = RW00 | GAYLE_IDE | DSHOLD; 

FDCP #(.INIT(1'b1)) 
	IOR_FF (
		.Q(IOR),
		.C(~CLK7M),
		.CLR(1'b0),
		.D(IOR_INT),
		.PRE(AS20)
);

FDCP #(.INIT(1'b1)) 
	IOW_FF (
		.Q(IOW),
		.C(~CLK7M),
		.CLR(1'b0),
		.D(IOW_INT),
		.PRE(AS20)
);

wire HIGHZ = ~BGACK;
wire AS_INT = AS20DLY | AS20;
wire UDS_INT = DS20 | AS | DSHOLD | A0;
wire LDS_INT = DS20 | AS | DSHOLD | ({A0, SIZ[1:0]} == 3'b001);  
wire VMA_INT = VMA_SYNC;  
 
assign RW00 = HIGHZ ? 1'bz : AS | RW20;      
assign AS =   HIGHZ ? 1'bz : AS_INT;   
assign UDS =  HIGHZ ? 1'bz : UDS_INT;
assign LDS =  HIGHZ ? 1'bz : LDS_INT;
assign VMA =  HIGHZ ? 1'bz : VMA_INT;

assign DTRIG = (DTACK_INT3| DTQUAL) & DTRIG_SYNC_D5;
assign DSACK[1] = (AS20DLY |  AS20 | SYSDSACK1);
assign DSACK[0] = 1'b1;

assign BG = AS ? BG20 : 1'bz;
assign BERR =  CPCS | ~CPSENSE;
assign AVEC = ~IACK | VPA;

assign IDECS = A[12] ? {GAYLE_IDE, 1'b1} : {1'b1, GAYLE_IDE}; 
assign OVR =  INTSIG;
   
endmodule
module tf530_bus(


		input 	 CLKCPU,
		input 	 CLK7M,
        

        
        input     INTSIG,


		input [2:0] 	 FC,
		input [1:0] 	 SIZ,
		input         A0,   
		input [23:12] A,
		

		input 	 AS20,
		input 	 DS20,
		input 	 RW20,
		output 	 [1:0] DSACK,
		

		
		output 	 AVEC,
		output   BERR,
		

		output	 CPCS,
		input    CPSENSE,
        


        input        IDEWAIT,
        output [1:0] IDECS,
        output       IOR,
        output       IOW,
        output       OVR,


		output 	 AS,
		output 	 LDS,
		output 	 UDS,
		output 	 RW00,
		input 	 DTACK,


		input 	 BG20,
		output 	 BG,
		input 	 BGACK,


		output 	 VMA,
		input 	 VPA,
		output reg E

       );


wire DS20DLY;
wire AS20DLY;

reg SYSDSACK1 = 1'b1;
reg RW20DLY = 1'b1;
reg CLK7MB2 = 1'b1;
reg BGACKD1 = 1'b1;
reg BGACKD2 = 1'b1;
reg DTQUAL = 1'b1;

reg [3:0] Q = 'hF;

reg VMA_SYNC = 1'b1;

initial begin 

	E = 'b0;
	
end

wire DTRIG;

wire CPUSPACE = &FC;


wire FPUOP = CPUSPACE & ({A[19:16]} === {4'b0010});
wire BKPT = CPUSPACE & ({A[19:16]} === {4'b0000});
wire IACK = CPUSPACE & ({A[19:16]} === {4'b1111});
wire DTACKPRELIM = CLK7M | CLK7MB2;
wire GAYLE_IDE = ({A[23:15]} != {8'hDA,1'b0}) | AS20 | FPUOP;

assign CPCS = ~FPUOP | AS20;

FDCP #(.INIT(1'b1)) 
	AS20DLY_FF (
		.Q(AS20DLY),
		.C(CLK7M),
		.CLR(1'b0),
		.D(AS20),
		.PRE(AS20 | FPUOP | ~INTSIG)
);


FDCP #(.INIT(1'b1)) 
	ASDLY_FF (
		.Q(ASDLY),
		.C(CLK7M),
		.CLR(1'b0),
		.D(AS),
		.PRE(AS20)
);

FDCP #(.INIT(1'b1)) 
	DS20DLY_FF (
		.Q(DS20DLY),
		.C(CLK7M),
		.CLR(1'b0),
		.D(DS20),
		.PRE(DS20 | FPUOP | ~INTSIG)
);

FDCP #(.INIT(1'b1)) 
	DTTRIG1_FF (
		.Q(DSACK1INT),
		.C(~DTRIG),
		.CLR(1'b0),
		.D(AS | ~INTSIG),
		.PRE(AS)
);


wire DTACKMOO = AS | ASDLY | DTACK | ~IDEWAIT;
FDCP #(.INIT(1'b1)) 
	DTTACK1_FF (
		.Q(DTACK_INT1),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(DTACKMOO),
		.PRE(DTACKMOO | ~INTSIG)
);

FDCP #(.INIT(1'b1)) 
	DTTACK2_FF (
		.Q(DTACK_INT2),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(DTACK_INT1),
		.PRE(DTACK_INT1)
);

FDCP #(.INIT(1'b1)) 
	DTTACK3_FF (
		.Q(DTACK_INT3),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(DTACK_INT2),
		.PRE(DTACK_INT2)
);

FDCP #(.INIT(1'b1)) 
	DTTACK4_FF (
		.Q(DTACK_INT4),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(DTACK_INT3),
		.PRE(DTACK_INT3)
);



reg DTRIG_SYNC = 1'b1;
reg DTRIG_SYNC_D = 1'b1;
reg DTRIG_SYNC_D2 = 1'b1;
reg DTRIG_SYNC_D3 = 1'b1;
reg DTRIG_SYNC_D4 = 1'b1;
reg DTRIG_SYNC_D5 = 1'b1;

always @(posedge CLKCPU) begin 

	SYSDSACK1 <= DSACK1INT | FPUOP ;
    DTRIG_SYNC <= ~Q[3] | VMA_SYNC | ~DTRIG_SYNC | ~DTRIG_SYNC_D |  ~DTRIG_SYNC_D2 | ~DTRIG_SYNC_D3 | ~DTRIG_SYNC_D4 | ~DTRIG_SYNC_D5;
    DTRIG_SYNC_D <= DTRIG_SYNC;
    DTRIG_SYNC_D2 <= DTRIG_SYNC_D;
    DTRIG_SYNC_D3 <= DTRIG_SYNC_D2;
    DTRIG_SYNC_D4 <= DTRIG_SYNC_D3;
    DTRIG_SYNC_D5 <= DTRIG_SYNC_D4;
    
end

always @(posedge CLK7M) begin
     
	DTQUAL 	<= AS20 | FPUOP;
	RW20DLY <= RW20;
     
    BGACKD1 <= BGACK;
    BGACKD2 <= BGACKD1;
    

    CLK7MB2 <= ~CLK7MB2;
    
   if (Q == 'd9) begin

      VMA_SYNC <= 1'b1;
      Q <= 'd0;

   end else begin

      Q <= Q + 'd1;

      if (Q == 'd4) begin
            E <= 'b1;       
      end

      if (Q == 'd8) begin
            E <= 'b0;
      end

      if (Q == 'd2) begin

         VMA_SYNC <=  (VPA | CPUSPACE);
		 
      end 
      
   end
 
end


   

wire DSHOLD = {ASDLY,AS, RW00} == {1'b1,1'b0,1'b0};
wire IOR_INT = ~RW00 | GAYLE_IDE | DSHOLD;
wire IOW_INT = RW00 | GAYLE_IDE | DSHOLD; 

FDCP #(.INIT(1'b1)) 
	IOR_FF (
		.Q(IOR),
		.C(~CLK7M),
		.CLR(1'b0),
		.D(IOR_INT),
		.PRE(AS20)
);

FDCP #(.INIT(1'b1)) 
	IOW_FF (
		.Q(IOW),
		.C(~CLK7M),
		.CLR(1'b0),
		.D(IOW_INT),
		.PRE(AS20)
);

wire HIGHZ = ~BGACK;
wire AS_INT = AS20DLY | AS20;
wire UDS_INT = DS20 | AS | DSHOLD | A0;
wire LDS_INT = DS20 | AS | DSHOLD | ({A0, SIZ[1:0]} == 3'b001);  
wire VMA_INT = VMA_SYNC;  
 
assign RW00 = HIGHZ ? 1'bz : AS | RW20;      
assign AS =   HIGHZ ? 1'bz : AS_INT;   
assign UDS =  HIGHZ ? 1'bz : UDS_INT;
assign LDS =  HIGHZ ? 1'bz : LDS_INT;
assign VMA =  HIGHZ ? 1'bz : VMA_INT;

assign DTRIG = (DTACK_INT3| DTQUAL) & DTRIG_SYNC_D5;
assign DSACK[1] = (AS20DLY |  AS20 | SYSDSACK1);
assign DSACK[0] = 1'b1;

assign BG = AS ? BG20 : 1'bz;
assign BERR =  CPCS | ~CPSENSE;
assign AVEC = ~IACK | VPA;

assign IDECS = A[12] ? {GAYLE_IDE, 1'b1} : {1'b1, GAYLE_IDE}; 
assign OVR =  INTSIG;
   
endmodule