data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/simple_platform.sv
1: b"%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/simple_platform.sv:53: Cannot find file containing module: 'syscon'\nsyscon sys (\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/syscon\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/syscon.v\n             data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new,data/full_repos/permissive/181158585/syscon.sv\n             syscon\n             syscon.v\n             syscon.sv\n             obj_dir/syscon\n             obj_dir/syscon.v\n             obj_dir/syscon.sv\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/simple_platform.sv:59: Cannot find file containing module: 'camellia_wrapper'\ncamellia_wrapper slave_0(\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/simple_platform.sv:75: Cannot find file containing module: 'serial_transmitter_wrapper'\nserial_transmitter_wrapper slave_1(\n^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/simple_platform.sv:91: Cannot find file containing module: 'core_wrapper'\ncore_wrapper core(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/simple_platform.sv:106: Cannot find file containing module: 'wishbone_bus'\nwishbone_bus #(.SLAVES(NUM_SLAVE)) bus(\n^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module simple_platform();

localparam NUM_SLAVE = 2'd2;


logic         clk           [NUM_SLAVE:0];
logic         rst           [NUM_SLAVE:0];
logic         ack           [NUM_SLAVE:0];
logic         err           [NUM_SLAVE:0];
logic         stall         [NUM_SLAVE:0];
logic         cyc           [NUM_SLAVE:0];
logic         stb           [NUM_SLAVE:0];
logic [31:0]  data_from_bus [NUM_SLAVE:0];
logic         we            [NUM_SLAVE:0];
logic  [3:0]  sel           [NUM_SLAVE:0];
logic [31:0]  adr           [NUM_SLAVE:0];  
logic [31:0]  data_to_bus   [NUM_SLAVE:0];


logic sysClk, sysRst;


syscon sys (
    .clk_o(sysClk),
    .rst_o(sysRst)
);


camellia_wrapper slave_0(
    .wb_clk   (clk[0]),
    .wb_rst   (rst[0]),
    .wb_cyc   (cyc[0]),
    .wb_stb   (stb[0]),
    .wb_we    (we[0]),
    .wb_sel   (sel[0]),
    .wb_dat_i (data_from_bus[0]), 
    .wb_adr   (adr[0]),
    .wb_ack   (ack[0]),
    .wb_err   (err[0]),
    .wb_stall (stall[0]),
    .wb_dat_o (data_to_bus[0])
);


serial_transmitter_wrapper slave_1(
    .wb_clk   (clk[1]),
    .wb_rst   (rst[1]),
    .wb_cyc   (cyc[1]),
    .wb_stb   (stb[1]),
    .wb_we    (we[1]),
    .wb_sel   (sel[1]),
    .wb_dat_i (data_from_bus[1]),
    .wb_adr   (adr[1]),
    .wb_ack   (ack[1]),
    .wb_err   (err[1]),
    .wb_stall (stall[1]),
    .wb_dat_o (data_to_bus[1])
);


core_wrapper core(
    .wb_clk   (clk[NUM_SLAVE]),
    .wb_rst   (rst[NUM_SLAVE]),
    .wb_ack   (ack[NUM_SLAVE]),
    .wb_err   (err[NUM_SLAVE]),
    .wb_stall (stall[NUM_SLAVE]),
    .wb_cyc   (cyc[NUM_SLAVE]),
    .wb_stb   (stb[NUM_SLAVE]),
    .wb_dat_i (data_from_bus[NUM_SLAVE]),
    .wb_we    (we[NUM_SLAVE]),
    .wb_sel   (sel[NUM_SLAVE]),
    .wb_adr   (adr[NUM_SLAVE]),
    .wb_dat_o (data_to_bus[NUM_SLAVE])
);

wishbone_bus #(.SLAVES(NUM_SLAVE)) bus(

    .sysClk(sysClk),
    .sysRst(sysRst),

    

    .wb_clk_m   (clk[NUM_SLAVE]),
    .wb_rst_m   (rst[NUM_SLAVE]),
    .wb_ack_m   (ack[NUM_SLAVE]),
    .wb_err_m   (err[NUM_SLAVE]),
    .wb_stall_m (stall[NUM_SLAVE]),
    .wb_cyc_m   (cyc[NUM_SLAVE]),
    .wb_stb_m   (stb[NUM_SLAVE]),
    .wb_dat_i_m (data_from_bus[NUM_SLAVE]),
    .wb_we_m    (we[NUM_SLAVE]),
    .wb_sel_m   (sel[NUM_SLAVE]),
    .wb_adr_m   (adr[NUM_SLAVE]),
    .wb_dat_o_m (data_to_bus[NUM_SLAVE]),

    

    .wb_clk_s   (clk[NUM_SLAVE-1:0]),
    .wb_rst_s   (rst[NUM_SLAVE-1:0]),
    .wb_ack_s   (ack[NUM_SLAVE-1:0]),
    .wb_err_s   (err[NUM_SLAVE-1:0]),
    .wb_stall_s (stall[NUM_SLAVE-1:0]),
    .wb_cyc_s   (cyc[NUM_SLAVE-1:0]),
    .wb_stb_s   (stb[NUM_SLAVE-1:0]),
    .wb_dat_i_s (data_from_bus[NUM_SLAVE-1:0]),
    .wb_we_s    (we[NUM_SLAVE-1:0]),
    .wb_sel_s   (sel[NUM_SLAVE-1:0]),
    .wb_adr_s   (adr[NUM_SLAVE-1:0]),
    .wb_dat_o_s (data_to_bus[NUM_SLAVE-1:0])

);

endmodule
module simple_platform();


localparam NUM_SLAVE = 2'd2;


logic         clk           [NUM_SLAVE:0];
logic         rst           [NUM_SLAVE:0];
logic         ack           [NUM_SLAVE:0];
logic         err           [NUM_SLAVE:0];
logic         stall         [NUM_SLAVE:0];
logic         cyc           [NUM_SLAVE:0];
logic         stb           [NUM_SLAVE:0];
logic [31:0]  data_from_bus [NUM_SLAVE:0];
logic         we            [NUM_SLAVE:0];
logic  [3:0]  sel           [NUM_SLAVE:0];
logic [31:0]  adr           [NUM_SLAVE:0];  
logic [31:0]  data_to_bus   [NUM_SLAVE:0];


logic sysClk, sysRst;


syscon sys (
    .clk_o(sysClk),
    .rst_o(sysRst)
);


camellia_wrapper slave_0(
    .wb_clk   (clk[0]),
    .wb_rst   (rst[0]),
    .wb_cyc   (cyc[0]),
    .wb_stb   (stb[0]),
    .wb_we    (we[0]),
    .wb_sel   (sel[0]),
    .wb_dat_i (data_from_bus[0]), 
    .wb_adr   (adr[0]),
    .wb_ack   (ack[0]),
    .wb_err   (err[0]),
    .wb_stall (stall[0]),
    .wb_dat_o (data_to_bus[0])
);


serial_transmitter_wrapper slave_1(
    .wb_clk   (clk[1]),
    .wb_rst   (rst[1]),
    .wb_cyc   (cyc[1]),
    .wb_stb   (stb[1]),
    .wb_we    (we[1]),
    .wb_sel   (sel[1]),
    .wb_dat_i (data_from_bus[1]),
    .wb_adr   (adr[1]),
    .wb_ack   (ack[1]),
    .wb_err   (err[1]),
    .wb_stall (stall[1]),
    .wb_dat_o (data_to_bus[1])
);


core_wrapper core(
    .wb_clk   (clk[NUM_SLAVE]),
    .wb_rst   (rst[NUM_SLAVE]),
    .wb_ack   (ack[NUM_SLAVE]),
    .wb_err   (err[NUM_SLAVE]),
    .wb_stall (stall[NUM_SLAVE]),
    .wb_cyc   (cyc[NUM_SLAVE]),
    .wb_stb   (stb[NUM_SLAVE]),
    .wb_dat_i (data_from_bus[NUM_SLAVE]),
    .wb_we    (we[NUM_SLAVE]),
    .wb_sel   (sel[NUM_SLAVE]),
    .wb_adr   (adr[NUM_SLAVE]),
    .wb_dat_o (data_to_bus[NUM_SLAVE])
);

wishbone_bus #(.SLAVES(NUM_SLAVE)) bus(

    .sysClk(sysClk),
    .sysRst(sysRst),

    

    .wb_clk_m   (clk[NUM_SLAVE]),
    .wb_rst_m   (rst[NUM_SLAVE]),
    .wb_ack_m   (ack[NUM_SLAVE]),
    .wb_err_m   (err[NUM_SLAVE]),
    .wb_stall_m (stall[NUM_SLAVE]),
    .wb_cyc_m   (cyc[NUM_SLAVE]),
    .wb_stb_m   (stb[NUM_SLAVE]),
    .wb_dat_i_m (data_from_bus[NUM_SLAVE]),
    .wb_we_m    (we[NUM_SLAVE]),
    .wb_sel_m   (sel[NUM_SLAVE]),
    .wb_adr_m   (adr[NUM_SLAVE]),
    .wb_dat_o_m (data_to_bus[NUM_SLAVE]),

    

    .wb_clk_s   (clk[NUM_SLAVE-1:0]),
    .wb_rst_s   (rst[NUM_SLAVE-1:0]),
    .wb_ack_s   (ack[NUM_SLAVE-1:0]),
    .wb_err_s   (err[NUM_SLAVE-1:0]),
    .wb_stall_s (stall[NUM_SLAVE-1:0]),
    .wb_cyc_s   (cyc[NUM_SLAVE-1:0]),
    .wb_stb_s   (stb[NUM_SLAVE-1:0]),
    .wb_dat_i_s (data_from_bus[NUM_SLAVE-1:0]),
    .wb_we_s    (we[NUM_SLAVE-1:0]),
    .wb_sel_s   (sel[NUM_SLAVE-1:0]),
    .wb_adr_s   (adr[NUM_SLAVE-1:0]),
    .wb_dat_o_s (data_to_bus[NUM_SLAVE-1:0])

);

endmodule