data/full_repos/permissive/127511545/src/Adder.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Adder.v:55: Signal definition not found, creating implicitly: \'C1\'\n and #(50) a1(C1, A, B);\n              ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Adder.v:56: Signal definition not found, creating implicitly: \'C2\'\n                                                                      : ... Suggested alternative: \'C1\'\n or #(50) o1(C2, A, B);\n             ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Adder.v:57: Signal definition not found, creating implicitly: \'C3\'\n                                                                      : ... Suggested alternative: \'C1\'\n and #(50) a2(C3, C2, Cin);\n              ^~\n%Error: Exiting due to 3 warning(s)\n'
module Adder1Bit(Sum, Cout, A, B, Cin);

	output Cout, Sum;
	input A, B, Cin;

	xor #(50) (Sum, A, B, Cin);
	and #(50) a1(C1, A, B);
	or #(50) o1(C2, A, B);
	and #(50) a2(C3, C2, Cin);
	or #(50) o2(Cout, C1, C3);

endmodule
module Adder1Bit(Sum, Cout, A, B, Cin);


	output Cout, Sum;
	input A, B, Cin;

	xor #(50) (Sum, A, B, Cin);
	and #(50) a1(C1, A, B);
	or #(50) o1(C2, A, B);
	and #(50) a2(C3, C2, Cin);
	or #(50) o2(Cout, C1, C3);

endmodule