data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 0; \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 0; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 0; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10 G = 1; D = 1; \n    ^\n%Error: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/testDlatch.v:5: Cannot find file containing module: \'Dlatch\'\n  Dlatch d1(G, D, Q, Q1);\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch,data/full_repos/permissive/172602559/Dlatch\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch,data/full_repos/permissive/172602559/Dlatch.v\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch,data/full_repos/permissive/172602559/Dlatch.sv\n             Dlatch\n             Dlatch.v\n             Dlatch.sv\n             obj_dir/Dlatch\n             obj_dir/Dlatch.v\n             obj_dir/Dlatch.sv\n%Error: Exiting due to 1 error(s), 32 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testDlatch();
  
  wire Q, Q1;
  reg G, D;
  Dlatch d1(G, D, Q, Q1);
  
  initial
  begin
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
end
endmodule
module testDlatch();

  
  wire Q, Q1;
  reg G, D;
  Dlatch d1(G, D, Q, Q1);
  
  initial
  begin
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    #10 G = 0; D = 0; 
    #10 G = 0; D = 1; 
    
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
    #10 G = 1; D = 0; 
    #10 G = 1; D = 1; 
end
endmodule