data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot16_alm.sv
 line:33: before: "DATA_WIDTH"
1: b'%Error: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot16_alm.sv:127: Cannot find file containing module: \'dot8_alm\'\n   dot8_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot8_1 (clk, rst, ena, a1_in, a2_in, a3_in, a4_in, a5_in, a6_in, a7_in, a8_in, b1_in, b2_in, b3_in, b4_in, b5_in, b6_in, b7_in, b8_in, dot8_res[0]);\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/dot8_alm\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/dot8_alm.v\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/dot8_alm.sv\n             dot8_alm\n             dot8_alm.v\n             dot8_alm.sv\n             obj_dir/dot8_alm\n             obj_dir/dot8_alm.v\n             obj_dir/dot8_alm.sv\n%Error: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot16_alm.sv:129: Cannot find file containing module: \'dot8_alm\'\n   dot8_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot8_2 (clk, rst, ena, a9_in, a10_in, a11_in, a12_in, a13_in, a14_in, a15_in, a16_in, b9_in, b10_in, b11_in, b12_in, b13_in, b14_in, b15_in, b16_in, dot8_res[1]);\n   ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot16_alm.sv:134: Operator ASSIGNW expects 20 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 19 bits.\n                                                                                                  : ... In instance top\n   assign dot8_res_e[0] = $signed(dot8_res[0]);\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot16_alm.sv:135: Operator ASSIGNW expects 20 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 19 bits.\n                                                                                                  : ... In instance top\n   assign dot8_res_e[1] = $signed(dot8_res[1]);\n                        ^\n%Error: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot16_alm.sv:138: Cannot find file containing module: \'nBit_mLength_shiftRegister\'\n   nBit_mLength_shiftRegister # ( DATA_WIDTH*2+4, TREE_DELAY ) dot16_q (clk, rst, ena, dot8_res_e[0] + dot8_res_e[1], res_out);\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module top # (
		    DATA_WIDTH = 8,
		    MULT_LATENCY = 4,
		    TREE_DELAY = 1
		    ) (
		       clk,
		       rst,
		       ena,

		       a1_in,
		       a2_in,
		       a3_in,
		       a4_in,
		       a5_in,
		       a6_in,
		       a7_in,
		       a8_in,
		       a9_in,
		       a10_in,
		       a11_in,
		       a12_in,
		       a13_in,
		       a14_in,
		       a15_in,
		       a16_in,

		       b1_in,
		       b2_in,
		       b3_in,
		       b4_in,
		       b5_in,
		       b6_in,
		       b7_in,
		       b8_in,
		       b9_in,
		       b10_in,
		       b11_in,
		       b12_in,
		       b13_in,
		       b14_in,
		       b15_in,
		       b16_in,

		       res_out
		       );



   input   wire                        clk;
   input   wire                        rst;
   input   wire                        ena;

   input   wire [DATA_WIDTH-1:0]       a1_in;
   input   wire [DATA_WIDTH-1:0]       a2_in;
   input   wire [DATA_WIDTH-1:0]       a3_in;
   input   wire [DATA_WIDTH-1:0]       a4_in;
   input   wire [DATA_WIDTH-1:0]       a5_in;
   input   wire [DATA_WIDTH-1:0]       a6_in;
   input   wire [DATA_WIDTH-1:0]       a7_in;
   input   wire [DATA_WIDTH-1:0]       a8_in;
   input   wire [DATA_WIDTH-1:0]       a9_in;
   input   wire [DATA_WIDTH-1:0]       a10_in;
   input   wire [DATA_WIDTH-1:0]       a11_in;
   input   wire [DATA_WIDTH-1:0]       a12_in;
   input   wire [DATA_WIDTH-1:0]       a13_in;
   input   wire [DATA_WIDTH-1:0]       a14_in;
   input   wire [DATA_WIDTH-1:0]       a15_in;
   input   wire [DATA_WIDTH-1:0]       a16_in;

   input   wire [DATA_WIDTH-1:0]       b1_in;
   input   wire [DATA_WIDTH-1:0]       b2_in;
   input   wire [DATA_WIDTH-1:0]       b3_in;
   input   wire [DATA_WIDTH-1:0]       b4_in;
   input   wire [DATA_WIDTH-1:0]       b5_in;
   input   wire [DATA_WIDTH-1:0]       b6_in;
   input   wire [DATA_WIDTH-1:0]       b7_in;
   input   wire [DATA_WIDTH-1:0]       b8_in;
   input   wire [DATA_WIDTH-1:0]       b9_in;
   input   wire [DATA_WIDTH-1:0]       b10_in;
   input   wire [DATA_WIDTH-1:0]       b11_in;
   input   wire [DATA_WIDTH-1:0]       b12_in;
   input   wire [DATA_WIDTH-1:0]       b13_in;
   input   wire [DATA_WIDTH-1:0]       b14_in;
   input   wire [DATA_WIDTH-1:0]       b15_in;
   input   wire [DATA_WIDTH-1:0]       b16_in;

   output  wire [DATA_WIDTH*2-1+4:0]   res_out;



   wire [DATA_WIDTH*2-1+3:0] 	       dot8_res [1:0];




   dot8_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot8_1 (clk, rst, ena, a1_in, a2_in, a3_in, a4_in, a5_in, a6_in, a7_in, a8_in, b1_in, b2_in, b3_in, b4_in, b5_in, b6_in, b7_in, b8_in, dot8_res[0]);

   dot8_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot8_2 (clk, rst, ena, a9_in, a10_in, a11_in, a12_in, a13_in, a14_in, a15_in, a16_in, b9_in, b10_in, b11_in, b12_in, b13_in, b14_in, b15_in, b16_in, dot8_res[1]);



   wire [DATA_WIDTH*2-1+4:0] 	       dot8_res_e [1:0];
   assign dot8_res_e[0] = $signed(dot8_res[0]);
   assign dot8_res_e[1] = $signed(dot8_res[1]);


   nBit_mLength_shiftRegister # ( DATA_WIDTH*2+4, TREE_DELAY ) dot16_q (clk, rst, ena, dot8_res_e[0] + dot8_res_e[1], res_out);

endmodule
module top # (
		    DATA_WIDTH = 8,
		    MULT_LATENCY = 4,
		    TREE_DELAY = 1
		    ) (
		       clk,
		       rst,
		       ena,

		       a1_in,
		       a2_in,
		       a3_in,
		       a4_in,
		       a5_in,
		       a6_in,
		       a7_in,
		       a8_in,
		       a9_in,
		       a10_in,
		       a11_in,
		       a12_in,
		       a13_in,
		       a14_in,
		       a15_in,
		       a16_in,

		       b1_in,
		       b2_in,
		       b3_in,
		       b4_in,
		       b5_in,
		       b6_in,
		       b7_in,
		       b8_in,
		       b9_in,
		       b10_in,
		       b11_in,
		       b12_in,
		       b13_in,
		       b14_in,
		       b15_in,
		       b16_in,

		       res_out
		       );




   input   wire                        clk;
   input   wire                        rst;
   input   wire                        ena;

   input   wire [DATA_WIDTH-1:0]       a1_in;
   input   wire [DATA_WIDTH-1:0]       a2_in;
   input   wire [DATA_WIDTH-1:0]       a3_in;
   input   wire [DATA_WIDTH-1:0]       a4_in;
   input   wire [DATA_WIDTH-1:0]       a5_in;
   input   wire [DATA_WIDTH-1:0]       a6_in;
   input   wire [DATA_WIDTH-1:0]       a7_in;
   input   wire [DATA_WIDTH-1:0]       a8_in;
   input   wire [DATA_WIDTH-1:0]       a9_in;
   input   wire [DATA_WIDTH-1:0]       a10_in;
   input   wire [DATA_WIDTH-1:0]       a11_in;
   input   wire [DATA_WIDTH-1:0]       a12_in;
   input   wire [DATA_WIDTH-1:0]       a13_in;
   input   wire [DATA_WIDTH-1:0]       a14_in;
   input   wire [DATA_WIDTH-1:0]       a15_in;
   input   wire [DATA_WIDTH-1:0]       a16_in;

   input   wire [DATA_WIDTH-1:0]       b1_in;
   input   wire [DATA_WIDTH-1:0]       b2_in;
   input   wire [DATA_WIDTH-1:0]       b3_in;
   input   wire [DATA_WIDTH-1:0]       b4_in;
   input   wire [DATA_WIDTH-1:0]       b5_in;
   input   wire [DATA_WIDTH-1:0]       b6_in;
   input   wire [DATA_WIDTH-1:0]       b7_in;
   input   wire [DATA_WIDTH-1:0]       b8_in;
   input   wire [DATA_WIDTH-1:0]       b9_in;
   input   wire [DATA_WIDTH-1:0]       b10_in;
   input   wire [DATA_WIDTH-1:0]       b11_in;
   input   wire [DATA_WIDTH-1:0]       b12_in;
   input   wire [DATA_WIDTH-1:0]       b13_in;
   input   wire [DATA_WIDTH-1:0]       b14_in;
   input   wire [DATA_WIDTH-1:0]       b15_in;
   input   wire [DATA_WIDTH-1:0]       b16_in;

   output  wire [DATA_WIDTH*2-1+4:0]   res_out;



   wire [DATA_WIDTH*2-1+3:0] 	       dot8_res [1:0];




   dot8_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot8_1 (clk, rst, ena, a1_in, a2_in, a3_in, a4_in, a5_in, a6_in, a7_in, a8_in, b1_in, b2_in, b3_in, b4_in, b5_in, b6_in, b7_in, b8_in, dot8_res[0]);

   dot8_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot8_2 (clk, rst, ena, a9_in, a10_in, a11_in, a12_in, a13_in, a14_in, a15_in, a16_in, b9_in, b10_in, b11_in, b12_in, b13_in, b14_in, b15_in, b16_in, dot8_res[1]);



   wire [DATA_WIDTH*2-1+4:0] 	       dot8_res_e [1:0];
   assign dot8_res_e[0] = $signed(dot8_res[0]);
   assign dot8_res_e[1] = $signed(dot8_res[1]);


   nBit_mLength_shiftRegister # ( DATA_WIDTH*2+4, TREE_DELAY ) dot16_q (clk, rst, ena, dot8_res_e[0] + dot8_res_e[1], res_out);

endmodule