data/full_repos/permissive/169526487/verilog-codes/array-multiplication.v
data/verilator_xmls/ad8e1edd-5799-49ba-8456-da96c37ad30f.xml
module fa (input j, input k,
input l,
output wire m, output wire n);

assign m=j^k^l;
assign n=(j*k)+(k*l)+(j*l);
endmodule
module fa (input j, input k,
input l,
output wire m, output wire n);


assign m=j^k^l;
assign n=(j*k)+(k*l)+(j*l);
endmodule