data/full_repos/permissive/167962127/square_wave.v
 line:61: before: "="
data/verilator_xmls/743cd811-e8fc-4cdf-9f60-9e48623fe424.xml
module square_wave(
  input i_clk,
  input [15:0] i_addr,
  output reg [15:0] o_data
);

  always @ (posedge i_clk) begin
    case (i_addr[15])

            0: o_data <= 16'b1000000000000001;
      default: o_data <= 16'b0111111111111111;
    endcase
  end
endmodule
module square_wave(
  input i_clk,
  input [15:0] i_addr,
  output reg [15:0] o_data
);


  always @ (posedge i_clk) begin
    case (i_addr[15])

            0: o_data <= 16'b1000000000000001;
      default: o_data <= 16'b0111111111111111;
    endcase
  end
endmodule