data/full_repos/permissive/136510272/next186/sample/system.v
1: b"%Error: data/full_repos/permissive/136510272/next186/sample/system.v:109: Cannot find file containing module: 'Next186_CPU'\n Next186_CPU CPU186\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/next186/sample,data/full_repos/permissive/136510272/Next186_CPU\n             data/full_repos/permissive/136510272/next186/sample,data/full_repos/permissive/136510272/Next186_CPU.v\n             data/full_repos/permissive/136510272/next186/sample,data/full_repos/permissive/136510272/Next186_CPU.sv\n             Next186_CPU\n             Next186_CPU.v\n             Next186_CPU.sv\n             obj_dir/Next186_CPU\n             obj_dir/Next186_CPU.v\n             obj_dir/Next186_CPU.sv\n%Error: data/full_repos/permissive/136510272/next186/sample/system.v:133: Cannot find file containing module: 'BIU186_32bSync_2T_DelayRead'\n  BIU186_32bSync_2T_DelayRead BIU186 \n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136510272/next186/sample/system.v:159: Cannot find file containing module: 'sram'\n  sram SRAM_ \n  ^~~~\n%Error: data/full_repos/permissive/136510272/next186/sample/system.v:169: Cannot find file containing module: 'dcm'\n dcm system_clock \n ^~~\n%Error: Exiting due to 4 error(s)\n"
module system(




















		
		input CLK_50MHZ,
		input BTN_SOUTH,
		output reg[7:0]LED,	
		output FPGA_AWAKE,
		input RS232_DCE_RXD,
		output reg RS232_DCE_TXD
    );


	wire [19:0]ADDR;
	wire [19:0]IADDR;
	wire [15:0]DIN;
	wire [15:0]DOUT;
	wire [47:0]INSTR;
	wire [2:0]ISIZE;
	wire [31:0]RAM_DIN;
	wire [31:0]RAM_DOUT; 
	wire [17:0]RAM_ADDR; 
	wire [3:0] RAM_WMASK;
	wire RAM_MREQ; 
	wire CE;
	wire MREQ;
	wire WR;
	wire WORD;
	wire IFETCH;
	wire FLUSH;
	wire HALT;
	wire IORQ;
	
	reg s_RS232_DCE_RXD;
	wire CLK;
	reg [4:0]rstcount = 0;

	Next186_CPU CPU186
	(
		 .ADDR(ADDR), 
		 .DIN({DIN[15:1], IORQ ? s_RS232_DCE_RXD : DIN[0]}), 
		 .DOUT(DOUT), 
		 .CLK(CLK), 
		 .CE(CE), 
		 .INTR(1'b0), 
		 .NMI(1'b0), 
		 .RST(BTN_SOUTH || !rstcount[4]), 
		 .MREQ(MREQ), 
		 .IORQ(IORQ), 

		 .WR(WR), 
		 .WORD(WORD), 

		 .IADDR(IADDR), 
		 .INSTR(INSTR), 
		 .IFETCH(IFETCH), 
		 .FLUSH(FLUSH), 
		 .ISIZE(ISIZE),
		 .HALT(FPGA_AWAKE)
	 );
	 
	 BIU186_32bSync_2T_DelayRead BIU186 
	 (
		 .CLK(CLK), 
		 .INSTR(INSTR), 
		 .ISIZE(ISIZE), 
		 .IFETCH(IFETCH), 
		 .FLUSH(FLUSH), 
		 .MREQ(MREQ), 
		 .WR(WR), 
		 .WORD(WORD), 
		 .ADDR(ADDR), 
		 .IADDR(IADDR), 
		 .CE186(CE), 
		 .RAM_DIN(RAM_DIN), 
		 .RAM_DOUT(RAM_DOUT), 
		 .RAM_ADDR(RAM_ADDR), 
		 .RAM_MREQ(RAM_MREQ), 
		 .RAM_WMASK(RAM_WMASK), 
		 .DOUT(DIN), 
		 .DIN(DOUT), 
		 .CE(1'b1)
    );
	 
	 wire block0 = RAM_ADDR[17:9] == 9'b000000000;
	 wire block1 = RAM_ADDR[17:9] == 9'b111111111;
	 
	 sram SRAM_ 
	 (
		  .clka(CLK),
		  .ena(RAM_MREQ && (block0 || block1)),
		  .wea(RAM_WMASK),
		  .addra(RAM_ADDR[9:0]),
		  .dina(RAM_DOUT),
		  .douta(RAM_DIN)
	  );

	dcm system_clock 
	(
    .CLKIN_IN(CLK_50MHZ), 
    .CLKFX_OUT(CLK)


    );


		always @ (posedge CLK) begin
			if(CE && IORQ && WR) begin
				if(ADDR[0]) RS232_DCE_TXD <= DOUT[0];
				else LED <= DOUT[7:0];
			end
			s_RS232_DCE_RXD <= RS232_DCE_RXD;
			if(CE && ~rstcount[4]) rstcount <= rstcount + 1;
		end
endmodule
module system(




















		
		input CLK_50MHZ,
		input BTN_SOUTH,
		output reg[7:0]LED,	
		output FPGA_AWAKE,
		input RS232_DCE_RXD,
		output reg RS232_DCE_TXD
    );



	wire [19:0]ADDR;
	wire [19:0]IADDR;
	wire [15:0]DIN;
	wire [15:0]DOUT;
	wire [47:0]INSTR;
	wire [2:0]ISIZE;
	wire [31:0]RAM_DIN;
	wire [31:0]RAM_DOUT; 
	wire [17:0]RAM_ADDR; 
	wire [3:0] RAM_WMASK;
	wire RAM_MREQ; 
	wire CE;
	wire MREQ;
	wire WR;
	wire WORD;
	wire IFETCH;
	wire FLUSH;
	wire HALT;
	wire IORQ;
	
	reg s_RS232_DCE_RXD;
	wire CLK;
	reg [4:0]rstcount = 0;

	Next186_CPU CPU186
	(
		 .ADDR(ADDR), 
		 .DIN({DIN[15:1], IORQ ? s_RS232_DCE_RXD : DIN[0]}), 
		 .DOUT(DOUT), 
		 .CLK(CLK), 
		 .CE(CE), 
		 .INTR(1'b0), 
		 .NMI(1'b0), 
		 .RST(BTN_SOUTH || !rstcount[4]), 
		 .MREQ(MREQ), 
		 .IORQ(IORQ), 

		 .WR(WR), 
		 .WORD(WORD), 

		 .IADDR(IADDR), 
		 .INSTR(INSTR), 
		 .IFETCH(IFETCH), 
		 .FLUSH(FLUSH), 
		 .ISIZE(ISIZE),
		 .HALT(FPGA_AWAKE)
	 );
	 
	 BIU186_32bSync_2T_DelayRead BIU186 
	 (
		 .CLK(CLK), 
		 .INSTR(INSTR), 
		 .ISIZE(ISIZE), 
		 .IFETCH(IFETCH), 
		 .FLUSH(FLUSH), 
		 .MREQ(MREQ), 
		 .WR(WR), 
		 .WORD(WORD), 
		 .ADDR(ADDR), 
		 .IADDR(IADDR), 
		 .CE186(CE), 
		 .RAM_DIN(RAM_DIN), 
		 .RAM_DOUT(RAM_DOUT), 
		 .RAM_ADDR(RAM_ADDR), 
		 .RAM_MREQ(RAM_MREQ), 
		 .RAM_WMASK(RAM_WMASK), 
		 .DOUT(DIN), 
		 .DIN(DOUT), 
		 .CE(1'b1)
    );
	 
	 wire block0 = RAM_ADDR[17:9] == 9'b000000000;
	 wire block1 = RAM_ADDR[17:9] == 9'b111111111;
	 
	 sram SRAM_ 
	 (
		  .clka(CLK),
		  .ena(RAM_MREQ && (block0 || block1)),
		  .wea(RAM_WMASK),
		  .addra(RAM_ADDR[9:0]),
		  .dina(RAM_DOUT),
		  .douta(RAM_DIN)
	  );

	dcm system_clock 
	(
    .CLKIN_IN(CLK_50MHZ), 
    .CLKFX_OUT(CLK)


    );


		always @ (posedge CLK) begin
			if(CE && IORQ && WR) begin
				if(ADDR[0]) RS232_DCE_TXD <= DOUT[0];
				else LED <= DOUT[7:0];
			end
			s_RS232_DCE_RXD <= RS232_DCE_RXD;
			if(CE && ~rstcount[4]) rstcount <= rstcount + 1;
		end
endmodule