data/full_repos/permissive/159610434/matrix_8x8/top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/159610434/matrix_8x8/top_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159610434/matrix_8x8/top_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2);\n        ^\n%Error: data/full_repos/permissive/159610434/matrix_8x8/top_tb.v:38: Cannot find file containing module: \'top\'\n    top dut(.clk(clk), .bcount(bcount), .a(a), .cs_n(cs_n), .d(d));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/159610434/matrix_8x8,data/full_repos/permissive/159610434/top\n             data/full_repos/permissive/159610434/matrix_8x8,data/full_repos/permissive/159610434/top.v\n             data/full_repos/permissive/159610434/matrix_8x8,data/full_repos/permissive/159610434/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb();

    parameter PERIOD = 10;
     
    reg clk;
    wire [4:0] bcount;
    wire [3:0] a;
    wire cs_n;
    wire d;

    always begin
        clk = 1'b1;
        #(PERIOD/2) clk = ~clk;
        #(PERIOD/2);
    end

    top dut(.clk(clk), .bcount(bcount), .a(a), .cs_n(cs_n), .d(d));

endmodule
module top_tb();


    parameter PERIOD = 10;
     
    reg clk;
    wire [4:0] bcount;
    wire [3:0] a;
    wire cs_n;
    wire d;

    always begin
        clk = 1'b1;
        #(PERIOD/2) clk = ~clk;
        #(PERIOD/2);
    end

    top dut(.clk(clk), .bcount(bcount), .a(a), .cs_n(cs_n), .d(d));

endmodule