data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v
 line:77: before: "("
1: b'%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:34: syntax error, unexpected \'@\'\n            @(posedge clock);\n            ^\n%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:38: syntax error, unexpected \'@\'\n            @(posedge clock);\n            ^\n%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:49: syntax error, unexpected \'@\'\n            @(posedge clock);\n            ^\n%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:53: syntax error, unexpected \'@\'\n            @(posedge clock);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n    initial forever #2.5 clock = ~clock;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:75: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/112823543/Avalon_PwmOut/Simulation/PwmOut_Avalon_tb.v:84: syntax error, unexpected \'@\'\n        @(negedge pwm[3]);\n        ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module PwmOut_Avalon_tb ();


    reg                     clock;
    reg                     reset;
    reg   [31:0]            s0_writedata;
    reg   [4:0]             s0_address;
    wire  [31:0]            s0_readdata;
    reg                     s0_write;
    reg                     s0_read;

    wire  [3:0]             pwm;



    PwmOut_Avalon  #(.NUMBER_OUTPUTS(3)) DUT(
        .clock_clk(clock),
        .reset_reset(reset),

        .s0_command_address(s0_address),
        .s0_command_read(s0_read),
        .s0_command_write(s0_write),
        .s0_command_readdata(s0_readdata),
        .s0_command_writedata(s0_writedata),

        .pwm(pwm)
    );

    task SetPrescaler;
        input [31:0]    prescaler;

        begin
            @(posedge clock);
            s0_address = 17;
            s0_writedata = prescaler;
            s0_write = 1;
            @(posedge clock);
            s0_write = 0;
        end
    endtask

    task SetPwm;
        input [3:0] channel;
        input [15:0] frequency;
        input [15:0] duty_cycle;

        begin
            @(posedge clock);
            s0_address = channel;
            s0_writedata = {duty_cycle, frequency};
            s0_write = 1;
            @(posedge clock);
            s0_write = 0;
        end
    endtask

    initial begin
        clock = 0;
        reset = 0;
    end


    initial forever #2.5 clock = ~clock;


    initial begin
        reset = 1;
        s0_write = 0;
        s0_read = 0;
        s0_writedata = 0;

        #10 reset = 0;

        @(posedge clock);

        SetPrescaler(1);

        SetPwm(0, 1000, 10);
        SetPwm(1, 1000, 20);
        SetPwm(2, 1000, 30);
        SetPwm(3, 1000, 40);

        @(negedge pwm[3]);

        $stop;
    end

endmodule
module PwmOut_Avalon_tb ();



    reg                     clock;
    reg                     reset;
    reg   [31:0]            s0_writedata;
    reg   [4:0]             s0_address;
    wire  [31:0]            s0_readdata;
    reg                     s0_write;
    reg                     s0_read;

    wire  [3:0]             pwm;



    PwmOut_Avalon  #(.NUMBER_OUTPUTS(3)) DUT(
        .clock_clk(clock),
        .reset_reset(reset),

        .s0_command_address(s0_address),
        .s0_command_read(s0_read),
        .s0_command_write(s0_write),
        .s0_command_readdata(s0_readdata),
        .s0_command_writedata(s0_writedata),

        .pwm(pwm)
    );

    task SetPrescaler;
        input [31:0]    prescaler;

        begin
            @(posedge clock);
            s0_address = 17;
            s0_writedata = prescaler;
            s0_write = 1;
            @(posedge clock);
            s0_write = 0;
        end
    endtask

    task SetPwm;
        input [3:0] channel;
        input [15:0] frequency;
        input [15:0] duty_cycle;

        begin
            @(posedge clock);
            s0_address = channel;
            s0_writedata = {duty_cycle, frequency};
            s0_write = 1;
            @(posedge clock);
            s0_write = 0;
        end
    endtask

    initial begin
        clock = 0;
        reset = 0;
    end


    initial forever #2.5 clock = ~clock;


    initial begin
        reset = 1;
        s0_write = 0;
        s0_read = 0;
        s0_writedata = 0;

        #10 reset = 0;

        @(posedge clock);

        SetPrescaler(1);

        SetPwm(0, 1000, 10);
        SetPwm(1, 1000, 20);
        SetPwm(2, 1000, 30);
        SetPwm(3, 1000, 40);

        @(negedge pwm[3]);

        $stop;
    end

endmodule