data/full_repos/permissive/153806190/program1/divider.v
data/verilator_xmls/5df44c56-30dd-4165-8dee-e694233835a8.xml
module divider(
  input clk,
  input rst,
  output reg clk_div
);

  reg [26:0] cnt;

  always @(posedge clk or posedge rst) begin
    if (rst) begin
      cnt <= 27'd0;
      clk_div <= 1'b0;
    end
    else begin

      if (cnt == 125000000) cnt <= 27'd0;
      else cnt <= cnt + 1;

      if (cnt < 62500000) clk_div <= 'b0;
      else clk_div <= 1'b1;
    end
  end

endmodule
module divider(
  input clk,
  input rst,
  output reg clk_div
);


  reg [26:0] cnt;

  always @(posedge clk or posedge rst) begin
    if (rst) begin
      cnt <= 27'd0;
      clk_div <= 1'b0;
    end
    else begin

      if (cnt == 125000000) cnt <= 27'd0;
      else cnt <= cnt + 1;

      if (cnt < 62500000) clk_div <= 'b0;
      else clk_div <= 1'b1;
    end
  end

endmodule