data/full_repos/permissive/119213113/colorbars.v
1: b"%Error: data/full_repos/permissive/119213113/colorbars.v:17: Cannot find file containing module: 'pll160'\n  pll160 pll (.clock_in(clk), .clock_out(clk160), .locked(locked));\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119213113,data/full_repos/permissive/119213113/pll160\n             data/full_repos/permissive/119213113,data/full_repos/permissive/119213113/pll160.v\n             data/full_repos/permissive/119213113,data/full_repos/permissive/119213113/pll160.sv\n             pll160\n             pll160.v\n             pll160.sv\n             obj_dir/pll160\n             obj_dir/pll160.v\n             obj_dir/pll160.sv\n%Error: data/full_repos/permissive/119213113/colorbars.v:26: Cannot find file containing module: 'vga_sync'\n  vga_sync vga_sync (.clk_pixel(clk_svga), .hsync(hsync), .vsync(vsync), .hblank(hblank), .vblank(vblank));\n  ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module colorbars (
  input clk,

  output [3:0] LED,
  output [3:0] red,
  output [3:0] green,
  output [3:0] blue,
  output reg hsync,
  output reg vsync
);

  wire clk160;
  wire locked;
  assign LED = {3'bzzz, locked};


  pll160 pll (.clock_in(clk), .clock_out(clk160), .locked(locked));


  reg [1:0] svga_div;
  wire clk_svga = svga_div[1];
  always @(posedge clk160)
    svga_div <= svga_div + 1;

  reg hblank, vblank;
  vga_sync vga_sync (.clk_pixel(clk_svga), .hsync(hsync), .vsync(vsync), .hblank(hblank), .vblank(vblank));
  wire in_display = ~(hblank | vblank);



  reg [7:0] bar_count;
  reg [2:0] bar;
  always @(posedge clk_svga)
  begin
  if(in_display)
    if(bar_count < 114)
      bar_count <= bar_count + 1;
    else
      begin
        bar <= bar + 1;
        bar_count <= 0;
      end
  else
    begin
      bar <= 0;
      bar_count <= 0;
    end
  end


  always @(posedge clk_svga)
  begin
      if(in_display)
        case(bar)
          0: {red, green, blue} <= 12'b1011_1011_1011;
          1: {red, green, blue} <= 12'b1011_1011_0000;
          2: {red, green, blue} <= 12'b0000_1011_1011;
          3: {red, green, blue} <= 12'b0000_1011_0000;
          4: {red, green, blue} <= 12'b1011_0000_1011;
          5: {red, green, blue} <= 12'b1011_0000_0000;
          6: {red, green, blue} <= 12'b0000_0000_1011;
        endcase
      else
      begin
          {red, green, blue} <= 12'h000;
      end
  end

endmodule
module colorbars (
  input clk,

  output [3:0] LED,
  output [3:0] red,
  output [3:0] green,
  output [3:0] blue,
  output reg hsync,
  output reg vsync
);


  wire clk160;
  wire locked;
  assign LED = {3'bzzz, locked};


  pll160 pll (.clock_in(clk), .clock_out(clk160), .locked(locked));


  reg [1:0] svga_div;
  wire clk_svga = svga_div[1];
  always @(posedge clk160)
    svga_div <= svga_div + 1;

  reg hblank, vblank;
  vga_sync vga_sync (.clk_pixel(clk_svga), .hsync(hsync), .vsync(vsync), .hblank(hblank), .vblank(vblank));
  wire in_display = ~(hblank | vblank);



  reg [7:0] bar_count;
  reg [2:0] bar;
  always @(posedge clk_svga)
  begin
  if(in_display)
    if(bar_count < 114)
      bar_count <= bar_count + 1;
    else
      begin
        bar <= bar + 1;
        bar_count <= 0;
      end
  else
    begin
      bar <= 0;
      bar_count <= 0;
    end
  end


  always @(posedge clk_svga)
  begin
      if(in_display)
        case(bar)
          0: {red, green, blue} <= 12'b1011_1011_1011;
          1: {red, green, blue} <= 12'b1011_1011_0000;
          2: {red, green, blue} <= 12'b0000_1011_1011;
          3: {red, green, blue} <= 12'b0000_1011_0000;
          4: {red, green, blue} <= 12'b1011_0000_1011;
          5: {red, green, blue} <= 12'b1011_0000_0000;
          6: {red, green, blue} <= 12'b0000_0000_1011;
        endcase
      else
      begin
          {red, green, blue} <= 12'h000;
      end
  end

endmodule