data/full_repos/permissive/140927679/Quartus/USB Amplifier/USB/USB_Transceiver.v
 line:105 column:22: Illegal character "'"
1: b'%Error: Cannot find file containing module: Amplifier/USB,data/full_repos/permissive/140927679\n        ... Looked in:\n             data/full_repos/permissive/140927679/Quartus/USB/Amplifier/USB,data/full_repos/permissive/140927679\n             data/full_repos/permissive/140927679/Quartus/USB/Amplifier/USB,data/full_repos/permissive/140927679.v\n             data/full_repos/permissive/140927679/Quartus/USB/Amplifier/USB,data/full_repos/permissive/140927679.sv\n             Amplifier/USB,data/full_repos/permissive/140927679\n             Amplifier/USB,data/full_repos/permissive/140927679.v\n             Amplifier/USB,data/full_repos/permissive/140927679.sv\n             obj_dir/Amplifier/USB,data/full_repos/permissive/140927679\n             obj_dir/Amplifier/USB,data/full_repos/permissive/140927679.v\n             obj_dir/Amplifier/USB,data/full_repos/permissive/140927679.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/140927679/Quartus/USB\n%Error: Cannot find file containing module: Amplifier/USB/USB_Transceiver.v\n%Error: Exiting due to 3 error(s)\n'
module USB_Transceiver(
 input Clk,
 input Reset,


 output           ResetRequest,
 input      [ 6:0]Address,
 output reg [ 3:0]Endpoint,
 output reg [10:0]FrameNumber,
 output reg       Error,




 output reg      OUT_Setup,
 output reg      OUT_SoP,
 output reg      OUT_EoP,
 input           OUT_WaitRequest,
 output reg [7:0]OUT_Data,
 output reg      OUT_Sequence,
 output reg      OUT_Valid,
 input           OUT_Isochronous,
 input           OUT_Stall,
 

 input           IN_Sequence,
 input      [7:0]IN_Data,
 input           IN_Ready,
 input           IN_ZeroLength,
 output reg      IN_WaitRequest,
 output reg      IN_Ack,
 input           IN_Isochronous,
 input           IN_Stall,


 inout DP, DM
);


`include "USB_Constants.vh"


wire StuffError;

wire NRZI_RxData;
wire NRZI_RxStop;
wire NRZI_RxValid;

reg  NRZI_TxData;
reg  NRZI_TxSend;
wire NRZI_TxNext;

USB_NRZI USB_NRZI_inst(
 Clk,
 Reset,


 ResetRequest,
 StuffError,


 NRZI_RxData,
 NRZI_RxStop,
 NRZI_RxValid,


 NRZI_TxData,
 NRZI_TxSend,
 NRZI_TxNext,


 DP, DM
);




reg tReset;
always @(posedge Clk) tReset <= Reset | ResetRequest;


reg [ 3:0]PID;
reg [15:0]Shift;
reg [ 4:0]CRC5;
reg [15:0]CRC16;


reg   [3:0]State;
localparam Idle             = 4'd0;
localparam ReceiveToken     = 4'd1;
localparam WaitForData      = 4'd2;
localparam ReceiveData      = 4'd3;
localparam SendHandshake    = 4'd4;
localparam SendDataHeader   = 4'd5;
localparam SendData         = 4'd6;
localparam SendCRC          = 4'd7;
localparam WaitForHandshake = 4'd8;
localparam Ignore           = 4'd9;


reg [4:0]DataCount;
reg [6:0]TimeoutCount;
reg      OUT_WaitRequest_1;



wire [7:0]SoP_1 =               Shift[ 8:1];
wire [7:0]PID_1 = {NRZI_RxData, Shift[15:9]};


always @(posedge Clk) begin
 if(tReset) begin
  OUT_Valid      <= 1'b0;
  IN_WaitRequest <= 1'b1;
  IN_Ack         <= 1'b0;
  NRZI_TxSend    <= 1'b0;

  Shift <= 16'hFFFF;
  State <= Idle;
  Error <= 0;


 end else begin
  case(State)
   Idle: begin
    OUT_EoP   <= 1'b0;
    OUT_Valid <= 1'b0;
    IN_Ack    <= 1'b0;

    if(NRZI_RxValid) begin
     Shift <= {NRZI_RxData, Shift[15:1]};
     CRC5  <= 5'b11111;

     if(SoP_1 == START) begin
      if(PID_1[7:4] == ~PID_1[3:0]) begin
       PID <= PID_1[3:0];

       if(PID_1[1:0] == TOKEN) begin
        Error <= 0;
        State <= ReceiveToken;
       end else begin
        State <= Ignore;
       end

      end else begin
       Error <= 1'b1;
       State <= Ignore;
      end
     end
    end else if(StuffError) begin
     Error <= 1'b1;
     State <= Ignore;
    end
   end


   ReceiveToken: if(NRZI_RxValid) begin
    CRC16 <= 16'hFFFF;

    if(CRC5[4] ^ NRZI_RxData) CRC5 <= {CRC5[3:0], 1'b0} ^ CRC5POL;
    else                      CRC5 <= {CRC5[3:0], 1'b0};

    if(NRZI_RxStop) begin
     if(CRC5 == CRC5RES) begin
      Endpoint <= Shift[10:7];

      case(PID[3:2])
       2'b11: begin
        OUT_Setup <= 1'b1;
        if(Address == Shift[6:0]) State <= WaitForData;
        else                      State <= Idle;
       end

       2'b00: begin
        OUT_Setup <= 1'b0;
        if(Address == Shift[6:0]) State <= WaitForData;
        else                      State <= Idle;
       end

       2'b10: begin
        if(Address == Shift[6:0]) State <= SendDataHeader;
        else                      State <= Idle;
       end

       2'b01: begin
        FrameNumber <= Shift[10:0];
        State       <= Idle;
       end

       default:;
      endcase
     end else begin
      Error <= 1'b1;
      State <= Idle;
     end
     Shift <= 16'hFFFF;

    end else begin
     Shift <= {NRZI_RxData, Shift[15:1]};
    end

   end else if(StuffError) begin
    Error <= 1'b1;
    State <= Ignore;
   end


   WaitForData: if(NRZI_RxValid) begin
    Shift     <= {NRZI_RxData, Shift[15:1]};
    CRC16     <= 16'hFFFF;
    OUT_SoP   <= 1'b1;
    OUT_EoP   <= 0;
    DataCount <= 0;

    OUT_WaitRequest_1 <= OUT_WaitRequest;

    if(SoP_1 == START) begin
     if(PID_1[7:4] == ~PID_1[3:0]) begin
      PID <= PID_1[3:0];
      if(PID_1[1:0] == DATA) begin
       State <= ReceiveData;

      end else begin
       Error <= 1'b1;
       State <= Ignore;
      end
     end else begin
      Error <= 1'b1;
      State <= Ignore;
     end
    end
   end else if(StuffError) begin
    Error <= 1'b1;
    State <= Ignore;
   end


   ReceiveData: if(NRZI_RxValid) begin
    OUT_Sequence <= PID[3];

    if(CRC16[15] ^ NRZI_RxData) CRC16 <= {CRC16[14:0], 1'b0} ^ CRC16POL;
    else                        CRC16 <= {CRC16[14:0], 1'b0};

    if(NRZI_RxStop) begin
     if(CRC16 == CRC16RES) begin
      OUT_EoP   <= 1'b1;
      OUT_Valid <= ~OUT_WaitRequest_1;

      if(OUT_Isochronous) begin
       Shift <= 16'hFFFF;
       State <= Idle;

      end else if(OUT_WaitRequest_1) begin
       Shift <= {~NACK, NACK, START};
       State <= SendHandshake;

      end else if(OUT_Stall) begin
       Shift <= {~STALL, STALL, START};
       State <= SendHandshake;

      end else begin
       Shift <= {~ACK, ACK, START};
       State <= SendHandshake;
      end
     end else begin
      Error <= 1'b1;
      Shift <= 16'hFFFF;
      State <= Idle;
     end
     
    end else begin
     if(DataCount == 5'd16) begin
      OUT_Data  <= Shift[7:0];
      OUT_Valid <= ~OUT_WaitRequest_1;
      DataCount <= 5'd9;
     end else begin
      OUT_Valid <= 1'b0;
      DataCount <= DataCount + 1'b1;
     end
     Shift <= {NRZI_RxData, Shift[15:1]};
    end

   end else if(StuffError) begin
    Error <= 1'b1;
    State <= Ignore;

   end else begin
    if(OUT_Valid) OUT_SoP <= 0;
    OUT_Valid <= 1'b0;
   end


   SendHandshake: begin
    OUT_EoP   <= 1'b0;
    OUT_Valid <= 1'b0;

    if(NRZI_TxSend) begin
     if(NRZI_TxNext) begin
      if(DataCount == 5'd15) begin
       NRZI_TxSend <= 1'b0;
       Shift       <= 16'hFFFF;
       State       <= Idle;
      end else begin
       {Shift, NRZI_TxData} <= {1'b1, Shift};
      end
      DataCount <= DataCount + 1'b1;
     end

    end else begin
     DataCount <= 0;
     {Shift, NRZI_TxData} <= {1'b1, Shift};
     NRZI_TxSend <= 1'b1;
    end
   end


   SendDataHeader: begin
    if(NRZI_TxSend) begin
     if(NRZI_TxNext) begin
      if(DataCount == 5'd15) begin
       DataCount <= 0;

       if(IN_Ready & ~IN_ZeroLength) begin
        {Shift, NRZI_TxData} <= {9'h1FF, IN_Data};
        if(CRC16[15] ^ IN_Data[0]) CRC16 <= {CRC16[14:0], 1'b0} ^ CRC16POL;
        else                       CRC16 <= {CRC16[14:0], 1'b0};

        DataCount      <= 0;
        IN_WaitRequest <= 1'b0;
        State          <= SendData;

       end else begin
        {NRZI_TxData, CRC16} <= ~{CRC16, 1'b0};
        State <= SendCRC;
       end

      end else begin
       {Shift, NRZI_TxData} <= {1'b1, Shift};
       DataCount <= DataCount + 1'b1;
      end
     end

    end else begin
     if(IN_Ready) begin
      DataCount   <= 0;
      NRZI_TxSend <= 1'b1;

      if(IN_Sequence) {Shift, NRZI_TxData} <= {1'b1, ~DATA1, DATA1, START};
      else            {Shift, NRZI_TxData} <= {1'b1, ~DATA0, DATA0, START};

     end else begin
      if(IN_Isochronous) begin
       Shift <= 16'hFFFF;
       State <= Idle;

      end else if(IN_Stall) begin
       Shift <= {~STALL, STALL, START};
       State <= SendHandshake;

      end else begin
       Shift <= {~NACK, NACK, START};
       State <= SendHandshake;
      end
     end
    end
   end

   
   SendData: begin
    if(NRZI_TxNext) begin
     if(DataCount == 5'd7) begin
      DataCount <= 0;

      if(IN_Ready) begin
       {Shift, NRZI_TxData} <= {9'h1FF, IN_Data};
       if(CRC16[15] ^ IN_Data[0]) CRC16 <= {CRC16[14:0], 1'b0} ^ CRC16POL;
       else                       CRC16 <= {CRC16[14:0], 1'b0};

       DataCount      <= 0;
       IN_WaitRequest <= 1'b0;

      end else begin
       {NRZI_TxData, CRC16} <= ~{CRC16, 1'b0};
       State <= SendCRC;
      end

     end else begin
      {Shift, NRZI_TxData} <= {1'b1, Shift};
      if(CRC16[15] ^ Shift[0]) CRC16 <= {CRC16[14:0], 1'b0} ^ CRC16POL;
      else                     CRC16 <= {CRC16[14:0], 1'b0};
      DataCount      <= DataCount + 1'b1;
      IN_WaitRequest <= 1'b1;
     end

    end else begin
     IN_WaitRequest <= 1'b1;
    end
   end


   SendCRC: if(NRZI_TxNext) begin
    TimeoutCount <= 0;

    {NRZI_TxData, CRC16} <= {CRC16, 1'b0};

    if(DataCount == 5'd15) begin
     DataCount <= 0;
     
     Shift       <= 16'hFFFF;
     NRZI_TxSend <= 1'b0;
     if(IN_Isochronous) begin
      IN_Ack <= 1'b1;
      State  <= Idle;
     end else begin
      State <= WaitForHandshake;
     end

    end else begin
     DataCount <= DataCount + 1'b1;
    end
   end


   WaitForHandshake: begin
    if(NRZI_RxValid) begin
     TimeoutCount <= 0;

     if(Shift[7:0] == START) begin
      if(Shift[15:12] == ~Shift[11:8]) begin
       if(NRZI_RxStop && (Shift[11:8] == ACK)) begin
        IN_Ack <= 1'b1;
        Shift  <= 16'hFFFF;
        State  <= Idle;

       end else begin
        Error <= 1'b1;
        State <= Ignore;
       end
      end else begin
       Error <= 1'b1;
       State <= Ignore;
      end
     end else begin
      Shift <= {NRZI_RxData, Shift[15:1]};
     end

    end else if(StuffError) begin
     Error <= 1'b1;
     State <= Ignore;

    end else begin
     if(TimeoutCount == 7'd76) begin
      Error <= 1'b1;
      Shift <= 16'hFFFF;
      State <= Idle;
     end
     TimeoutCount <= TimeoutCount + 1'b1;
    end
   end


   Ignore: begin
    Shift <= 16'hFFFF;
    if(NRZI_RxStop) State <= Idle;
   end


   default:;
  endcase
 end
end


endmodule
module USB_Transceiver(
 input Clk,
 input Reset,


 output           ResetRequest,
 input      [ 6:0]Address,
 output reg [ 3:0]Endpoint,
 output reg [10:0]FrameNumber,
 output reg       Error,




 output reg      OUT_Setup,
 output reg      OUT_SoP,
 output reg      OUT_EoP,
 input           OUT_WaitRequest,
 output reg [7:0]OUT_Data,
 output reg      OUT_Sequence,
 output reg      OUT_Valid,
 input           OUT_Isochronous,
 input           OUT_Stall,
 

 input           IN_Sequence,
 input      [7:0]IN_Data,
 input           IN_Ready,
 input           IN_ZeroLength,
 output reg      IN_WaitRequest,
 output reg      IN_Ack,
 input           IN_Isochronous,
 input           IN_Stall,


 inout DP, DM
);



`include "USB_Constants.vh"


wire StuffError;

wire NRZI_RxData;
wire NRZI_RxStop;
wire NRZI_RxValid;

reg  NRZI_TxData;
reg  NRZI_TxSend;
wire NRZI_TxNext;

USB_NRZI USB_NRZI_inst(
 Clk,
 Reset,


 ResetRequest,
 StuffError,


 NRZI_RxData,
 NRZI_RxStop,
 NRZI_RxValid,


 NRZI_TxData,
 NRZI_TxSend,
 NRZI_TxNext,


 DP, DM
);




reg tReset;
always @(posedge Clk) tReset <= Reset | ResetRequest;


reg [ 3:0]PID;
reg [15:0]Shift;
reg [ 4:0]CRC5;
reg [15:0]CRC16;


reg   [3:0]State;
localparam Idle             = 4'd0;
localparam ReceiveToken     = 4'd1;
localparam WaitForData      = 4'd2;
localparam ReceiveData      = 4'd3;
localparam SendHandshake    = 4'd4;
localparam SendDataHeader   = 4'd5;
localparam SendData         = 4'd6;
localparam SendCRC          = 4'd7;
localparam WaitForHandshake = 4'd8;
localparam Ignore           = 4'd9;


reg [4:0]DataCount;
reg [6:0]TimeoutCount;
reg      OUT_WaitRequest_1;



wire [7:0]SoP_1 =               Shift[ 8:1];
wire [7:0]PID_1 = {NRZI_RxData, Shift[15:9]};


always @(posedge Clk) begin
 if(tReset) begin
  OUT_Valid      <= 1'b0;
  IN_WaitRequest <= 1'b1;
  IN_Ack         <= 1'b0;
  NRZI_TxSend    <= 1'b0;

  Shift <= 16'hFFFF;
  State <= Idle;
  Error <= 0;


 end else begin
  case(State)
   Idle: begin
    OUT_EoP   <= 1'b0;
    OUT_Valid <= 1'b0;
    IN_Ack    <= 1'b0;

    if(NRZI_RxValid) begin
     Shift <= {NRZI_RxData, Shift[15:1]};
     CRC5  <= 5'b11111;

     if(SoP_1 == START) begin
      if(PID_1[7:4] == ~PID_1[3:0]) begin
       PID <= PID_1[3:0];

       if(PID_1[1:0] == TOKEN) begin
        Error <= 0;
        State <= ReceiveToken;
       end else begin
        State <= Ignore;
       end

      end else begin
       Error <= 1'b1;
       State <= Ignore;
      end
     end
    end else if(StuffError) begin
     Error <= 1'b1;
     State <= Ignore;
    end
   end


   ReceiveToken: if(NRZI_RxValid) begin
    CRC16 <= 16'hFFFF;

    if(CRC5[4] ^ NRZI_RxData) CRC5 <= {CRC5[3:0], 1'b0} ^ CRC5POL;
    else                      CRC5 <= {CRC5[3:0], 1'b0};

    if(NRZI_RxStop) begin
     if(CRC5 == CRC5RES) begin
      Endpoint <= Shift[10:7];

      case(PID[3:2])
       2'b11: begin
        OUT_Setup <= 1'b1;
        if(Address == Shift[6:0]) State <= WaitForData;
        else                      State <= Idle;
       end

       2'b00: begin
        OUT_Setup <= 1'b0;
        if(Address == Shift[6:0]) State <= WaitForData;
        else                      State <= Idle;
       end

       2'b10: begin
        if(Address == Shift[6:0]) State <= SendDataHeader;
        else                      State <= Idle;
       end

       2'b01: begin
        FrameNumber <= Shift[10:0];
        State       <= Idle;
       end

       default:;
      endcase
     end else begin
      Error <= 1'b1;
      State <= Idle;
     end
     Shift <= 16'hFFFF;

    end else begin
     Shift <= {NRZI_RxData, Shift[15:1]};
    end

   end else if(StuffError) begin
    Error <= 1'b1;
    State <= Ignore;
   end


   WaitForData: if(NRZI_RxValid) begin
    Shift     <= {NRZI_RxData, Shift[15:1]};
    CRC16     <= 16'hFFFF;
    OUT_SoP   <= 1'b1;
    OUT_EoP   <= 0;
    DataCount <= 0;

    OUT_WaitRequest_1 <= OUT_WaitRequest;

    if(SoP_1 == START) begin
     if(PID_1[7:4] == ~PID_1[3:0]) begin
      PID <= PID_1[3:0];
      if(PID_1[1:0] == DATA) begin
       State <= ReceiveData;

      end else begin
       Error <= 1'b1;
       State <= Ignore;
      end
     end else begin
      Error <= 1'b1;
      State <= Ignore;
     end
    end
   end else if(StuffError) begin
    Error <= 1'b1;
    State <= Ignore;
   end


   ReceiveData: if(NRZI_RxValid) begin
    OUT_Sequence <= PID[3];

    if(CRC16[15] ^ NRZI_RxData) CRC16 <= {CRC16[14:0], 1'b0} ^ CRC16POL;
    else                        CRC16 <= {CRC16[14:0], 1'b0};

    if(NRZI_RxStop) begin
     if(CRC16 == CRC16RES) begin
      OUT_EoP   <= 1'b1;
      OUT_Valid <= ~OUT_WaitRequest_1;

      if(OUT_Isochronous) begin
       Shift <= 16'hFFFF;
       State <= Idle;

      end else if(OUT_WaitRequest_1) begin
       Shift <= {~NACK, NACK, START};
       State <= SendHandshake;

      end else if(OUT_Stall) begin
       Shift <= {~STALL, STALL, START};
       State <= SendHandshake;

      end else begin
       Shift <= {~ACK, ACK, START};
       State <= SendHandshake;
      end
     end else begin
      Error <= 1'b1;
      Shift <= 16'hFFFF;
      State <= Idle;
     end
     
    end else begin
     if(DataCount == 5'd16) begin
      OUT_Data  <= Shift[7:0];
      OUT_Valid <= ~OUT_WaitRequest_1;
      DataCount <= 5'd9;
     end else begin
      OUT_Valid <= 1'b0;
      DataCount <= DataCount + 1'b1;
     end
     Shift <= {NRZI_RxData, Shift[15:1]};
    end

   end else if(StuffError) begin
    Error <= 1'b1;
    State <= Ignore;

   end else begin
    if(OUT_Valid) OUT_SoP <= 0;
    OUT_Valid <= 1'b0;
   end


   SendHandshake: begin
    OUT_EoP   <= 1'b0;
    OUT_Valid <= 1'b0;

    if(NRZI_TxSend) begin
     if(NRZI_TxNext) begin
      if(DataCount == 5'd15) begin
       NRZI_TxSend <= 1'b0;
       Shift       <= 16'hFFFF;
       State       <= Idle;
      end else begin
       {Shift, NRZI_TxData} <= {1'b1, Shift};
      end
      DataCount <= DataCount + 1'b1;
     end

    end else begin
     DataCount <= 0;
     {Shift, NRZI_TxData} <= {1'b1, Shift};
     NRZI_TxSend <= 1'b1;
    end
   end


   SendDataHeader: begin
    if(NRZI_TxSend) begin
     if(NRZI_TxNext) begin
      if(DataCount == 5'd15) begin
       DataCount <= 0;

       if(IN_Ready & ~IN_ZeroLength) begin
        {Shift, NRZI_TxData} <= {9'h1FF, IN_Data};
        if(CRC16[15] ^ IN_Data[0]) CRC16 <= {CRC16[14:0], 1'b0} ^ CRC16POL;
        else                       CRC16 <= {CRC16[14:0], 1'b0};

        DataCount      <= 0;
        IN_WaitRequest <= 1'b0;
        State          <= SendData;

       end else begin
        {NRZI_TxData, CRC16} <= ~{CRC16, 1'b0};
        State <= SendCRC;
       end

      end else begin
       {Shift, NRZI_TxData} <= {1'b1, Shift};
       DataCount <= DataCount + 1'b1;
      end
     end

    end else begin
     if(IN_Ready) begin
      DataCount   <= 0;
      NRZI_TxSend <= 1'b1;

      if(IN_Sequence) {Shift, NRZI_TxData} <= {1'b1, ~DATA1, DATA1, START};
      else            {Shift, NRZI_TxData} <= {1'b1, ~DATA0, DATA0, START};

     end else begin
      if(IN_Isochronous) begin
       Shift <= 16'hFFFF;
       State <= Idle;

      end else if(IN_Stall) begin
       Shift <= {~STALL, STALL, START};
       State <= SendHandshake;

      end else begin
       Shift <= {~NACK, NACK, START};
       State <= SendHandshake;
      end
     end
    end
   end

   
   SendData: begin
    if(NRZI_TxNext) begin
     if(DataCount == 5'd7) begin
      DataCount <= 0;

      if(IN_Ready) begin
       {Shift, NRZI_TxData} <= {9'h1FF, IN_Data};
       if(CRC16[15] ^ IN_Data[0]) CRC16 <= {CRC16[14:0], 1'b0} ^ CRC16POL;
       else                       CRC16 <= {CRC16[14:0], 1'b0};

       DataCount      <= 0;
       IN_WaitRequest <= 1'b0;

      end else begin
       {NRZI_TxData, CRC16} <= ~{CRC16, 1'b0};
       State <= SendCRC;
      end

     end else begin
      {Shift, NRZI_TxData} <= {1'b1, Shift};
      if(CRC16[15] ^ Shift[0]) CRC16 <= {CRC16[14:0], 1'b0} ^ CRC16POL;
      else                     CRC16 <= {CRC16[14:0], 1'b0};
      DataCount      <= DataCount + 1'b1;
      IN_WaitRequest <= 1'b1;
     end

    end else begin
     IN_WaitRequest <= 1'b1;
    end
   end


   SendCRC: if(NRZI_TxNext) begin
    TimeoutCount <= 0;

    {NRZI_TxData, CRC16} <= {CRC16, 1'b0};

    if(DataCount == 5'd15) begin
     DataCount <= 0;
     
     Shift       <= 16'hFFFF;
     NRZI_TxSend <= 1'b0;
     if(IN_Isochronous) begin
      IN_Ack <= 1'b1;
      State  <= Idle;
     end else begin
      State <= WaitForHandshake;
     end

    end else begin
     DataCount <= DataCount + 1'b1;
    end
   end


   WaitForHandshake: begin
    if(NRZI_RxValid) begin
     TimeoutCount <= 0;

     if(Shift[7:0] == START) begin
      if(Shift[15:12] == ~Shift[11:8]) begin
       if(NRZI_RxStop && (Shift[11:8] == ACK)) begin
        IN_Ack <= 1'b1;
        Shift  <= 16'hFFFF;
        State  <= Idle;

       end else begin
        Error <= 1'b1;
        State <= Ignore;
       end
      end else begin
       Error <= 1'b1;
       State <= Ignore;
      end
     end else begin
      Shift <= {NRZI_RxData, Shift[15:1]};
     end

    end else if(StuffError) begin
     Error <= 1'b1;
     State <= Ignore;

    end else begin
     if(TimeoutCount == 7'd76) begin
      Error <= 1'b1;
      Shift <= 16'hFFFF;
      State <= Idle;
     end
     TimeoutCount <= TimeoutCount + 1'b1;
    end
   end


   Ignore: begin
    Shift <= 16'hFFFF;
    if(NRZI_RxStop) State <= Idle;
   end


   default:;
  endcase
 end
end


endmodule