data/full_repos/permissive/172538466/hw/src/rom.v
None: at end of input
1: b'%Error: data/full_repos/permissive/172538466/hw/src/rom.v:1: Cannot find include file: defs.vh\n`include "defs.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.v\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.sv\n             defs.vh\n             defs.vh.v\n             defs.vh.sv\n             obj_dir/defs.vh\n             obj_dir/defs.vh.v\n             obj_dir/defs.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module rom
  #( parameter AWIDTH = 8 )
   (
    input              HCLK_I,
    input              HRESET_N_I,

    input              HSEL_I,
    input [AWIDTH-1:0] HADDR_I,
    input              HREADY_I,
    output             HRESP_O,
    output [31:0]      HWDATA_O,
    output             HREADY_O
    );


   localparam FILENAME = "../build/rom.hex";
   localparam COUNT = 2 ** (AWIDTH-2);
   reg [31:0]       memory[0:COUNT-1];


   reg [AWIDTH-1:0]    adr_d;
   reg                 enable_d;

   always @(posedge HCLK_I)
     adr_d <= HADDR_I;

   always @(posedge HCLK_I)
     if(!HRESET_N_I)
       enable_d <= 0;
     else
       enable_d <= HSEL_I;


   initial begin
     $readmemh(FILENAME, memory);
   end


   assign HWDATA_O = enable_d ? memory[ adr_d[AWIDTH-1:2]] : 32'd0;
   assign HREADY_O = enable_d;
   assign HRESP_O = 0;

endmodule
module rom
  #( parameter AWIDTH = 8 )
   (
    input              HCLK_I,
    input              HRESET_N_I,

    input              HSEL_I,
    input [AWIDTH-1:0] HADDR_I,
    input              HREADY_I,
    output             HRESP_O,
    output [31:0]      HWDATA_O,
    output             HREADY_O
    );



   localparam FILENAME = "../build/rom.hex";
   localparam COUNT = 2 ** (AWIDTH-2);
   reg [31:0]       memory[0:COUNT-1];


   reg [AWIDTH-1:0]    adr_d;
   reg                 enable_d;

   always @(posedge HCLK_I)
     adr_d <= HADDR_I;

   always @(posedge HCLK_I)
     if(!HRESET_N_I)
       enable_d <= 0;
     else
       enable_d <= HSEL_I;


   initial begin
     $readmemh(FILENAME, memory);
   end


   assign HWDATA_O = enable_d ? memory[ adr_d[AWIDTH-1:2]] : 32'd0;
   assign HREADY_O = enable_d;
   assign HRESP_O = 0;

endmodule