data/full_repos/permissive/115403704/src/mips_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/115403704/src/mips_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #20 clk<=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115403704/src/mips_tb.v:14: Cannot find file containing module: \'mips\'\n    mips my_mips(clk,rst);\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/mips\n             data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/mips.v\n             data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_tb();
    `timescale  1ns/1ps
    reg clk;
    reg rst;
    initial
    begin
        clk=1;
        clk=0;
    end
    always
    begin
        #20 clk<=~clk;
    end
    mips my_mips(clk,rst);
endmodule
module mips_tb();

    `timescale  1ns/1ps
    reg clk;
    reg rst;
    initial
    begin
        clk=1;
        clk=0;
    end
    always
    begin
        #20 clk<=~clk;
    end
    mips my_mips(clk,rst);
endmodule