data/full_repos/permissive/220347822/fpga-shells/xilinx/vcu118/vsrc/vcu118reset.v
1: b'%Warning-WIDTH: data/full_repos/permissive/220347822/fpga-shells/xilinx/vcu118/vsrc/vcu118reset.v:53: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                                    : ... In instance vcu118reset.hold_clock0\n  reg [8:0] debounce_reset = {8{1\'b1}};\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/220347822/fpga-shells/xilinx/vcu118/vsrc/vcu118reset.v:70: Operator SUB expects 9 bits on the RHS, but RHS\'s VARREF \'out_reset\' generates 1 bits.\n                                                                                                    : ... In instance vcu118reset.hold_clock0\n      debounce_reset <= debounce_reset - out_reset;\n                                       ^\n%Error: Exiting due to 2 warning(s)\n'
module vcu118reset(


  input  wire areset,


  input  wire clock1,
  output wire reset1,
  input  wire clock2,
  output wire reset2,
  input  wire clock3,
  output wire reset3,
  input  wire clock4,
  output wire reset4
);
  sifive_reset_hold hold_clock0(areset, clock1, reset1);
  sifive_reset_sync sync_clock2(reset1, clock2, reset2);
  sifive_reset_sync sync_clock3(reset2, clock3, reset3);
  sifive_reset_sync sync_clock4(reset3, clock4, reset4);
endmodule
module vcu118reset(


  input  wire areset,


  input  wire clock1,
  output wire reset1,
  input  wire clock2,
  output wire reset2,
  input  wire clock3,
  output wire reset3,
  input  wire clock4,
  output wire reset4
);

  sifive_reset_hold hold_clock0(areset, clock1, reset1);
  sifive_reset_sync sync_clock2(reset1, clock2, reset2);
  sifive_reset_sync sync_clock3(reset2, clock3, reset3);
  sifive_reset_sync sync_clock4(reset3, clock4, reset4);
endmodule