data/full_repos/permissive/207111076/msm6295.v
1: b'%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:62: Operator ADD expects 22 bits on the LHS, but LHS\'s REPLICATE generates 19 bits.\n                                                                 : ... In instance msm6295\nwire signed [21:0] SOUND_MIX = {V1_SAMP_OUT[17],V1_SAMP_OUT} + {V2_SAMP_OUT[17],V2_SAMP_OUT} + {V3_SAMP_OUT[17],V3_SAMP_OUT} + {V4_SAMP_OUT[17],V4_SAMP_OUT};\n                                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:62: Operator ADD expects 22 bits on the RHS, but RHS\'s REPLICATE generates 19 bits.\n                                                                 : ... In instance msm6295\nwire signed [21:0] SOUND_MIX = {V1_SAMP_OUT[17],V1_SAMP_OUT} + {V2_SAMP_OUT[17],V2_SAMP_OUT} + {V3_SAMP_OUT[17],V3_SAMP_OUT} + {V4_SAMP_OUT[17],V4_SAMP_OUT};\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:62: Operator ADD expects 22 bits on the RHS, but RHS\'s REPLICATE generates 19 bits.\n                                                                 : ... In instance msm6295\nwire signed [21:0] SOUND_MIX = {V1_SAMP_OUT[17],V1_SAMP_OUT} + {V2_SAMP_OUT[17],V2_SAMP_OUT} + {V3_SAMP_OUT[17],V3_SAMP_OUT} + {V4_SAMP_OUT[17],V4_SAMP_OUT};\n                                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:62: Operator ADD expects 22 bits on the RHS, but RHS\'s REPLICATE generates 19 bits.\n                                                                 : ... In instance msm6295\nwire signed [21:0] SOUND_MIX = {V1_SAMP_OUT[17],V1_SAMP_OUT} + {V2_SAMP_OUT[17],V2_SAMP_OUT} + {V3_SAMP_OUT[17],V3_SAMP_OUT} + {V4_SAMP_OUT[17],V4_SAMP_OUT};\n                                                                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:79: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                 : ... In instance msm6295\nwire signed [6:0] V1_VOL_MUL =  (V1_ATTEN==4\'d0) ? 8\'h20 :    \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:90: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                 : ... In instance msm6295\nwire signed [6:0] V2_VOL_MUL =  (V2_ATTEN==4\'d0) ? 8\'h20 :    \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:101: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                  : ... In instance msm6295\nwire signed [6:0] V3_VOL_MUL =  (V3_ATTEN==4\'d0) ? 8\'h20 :    \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:112: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                  : ... In instance msm6295\nwire signed [6:0] V4_VOL_MUL =  (V4_ATTEN==4\'d0) ? 8\'h20 :    \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:246: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                  : ... In instance msm6295\n   V1_INDEX <= {PHRASE_SEL, 4\'b0000};\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:252: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                  : ... In instance msm6295\n   V2_INDEX <= {PHRASE_SEL, 4\'b0000};\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:258: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                  : ... In instance msm6295\n   V3_INDEX <= {PHRASE_SEL, 4\'b0000};\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:264: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                  : ... In instance msm6295\n   V4_INDEX <= {PHRASE_SEL, 4\'b0000};\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:336: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'V1_SIGNAL\' generates 13 bits.\n                                                                  : ... In instance msm6295\n    V1_SIGNAL <= V1_SIGNAL + ADPCM_DATA;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:336: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                  : ... In instance msm6295\n    V1_SIGNAL <= V1_SIGNAL + ADPCM_DATA;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:426: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'V2_SIGNAL\' generates 13 bits.\n                                                                  : ... In instance msm6295\n    V2_SIGNAL <= V2_SIGNAL + ADPCM_DATA;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:426: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                  : ... In instance msm6295\n    V2_SIGNAL <= V2_SIGNAL + ADPCM_DATA;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:517: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'V3_SIGNAL\' generates 13 bits.\n                                                                  : ... In instance msm6295\n    V3_SIGNAL <= V3_SIGNAL + ADPCM_DATA;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:517: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                  : ... In instance msm6295\n    V3_SIGNAL <= V3_SIGNAL + ADPCM_DATA;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:607: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'V4_SIGNAL\' generates 13 bits.\n                                                                  : ... In instance msm6295\n    V4_SIGNAL <= V4_SIGNAL + ADPCM_DATA;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:607: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                  : ... In instance msm6295\n    V4_SIGNAL <= V4_SIGNAL + ADPCM_DATA;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:690: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'V1_NIB\' generates 4 bits.\n                                                                  : ... In instance msm6295\nwire [11:0] ADPCM_ADDR = (MAIN_STATE==0) ? (V1_STEP * 16) + V1_NIB :\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:691: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'V2_NIB\' generates 4 bits.\n                                                                  : ... In instance msm6295\n         (MAIN_STATE==1) ? (V2_STEP * 16) + V2_NIB :\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:692: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'V3_NIB\' generates 4 bits.\n                                                                  : ... In instance msm6295\n         (MAIN_STATE==2) ? (V3_STEP * 16) + V3_NIB :\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/207111076/msm6295.v:693: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'V4_NIB\' generates 4 bits.\n                                                                  : ... In instance msm6295\n               (V4_STEP * 16) + V4_NIB;\n                              ^\n%Error: data/full_repos/permissive/207111076/msm6295.v:697: Cannot find file containing module: \'ADPCM_LUT_ROM\'\nADPCM_LUT_ROM ADPCM_LUT_ROM\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207111076,data/full_repos/permissive/207111076/ADPCM_LUT_ROM\n             data/full_repos/permissive/207111076,data/full_repos/permissive/207111076/ADPCM_LUT_ROM.v\n             data/full_repos/permissive/207111076,data/full_repos/permissive/207111076/ADPCM_LUT_ROM.sv\n             ADPCM_LUT_ROM\n             ADPCM_LUT_ROM.v\n             ADPCM_LUT_ROM.sv\n             obj_dir/ADPCM_LUT_ROM\n             obj_dir/ADPCM_LUT_ROM.v\n             obj_dir/ADPCM_LUT_ROM.sv\n%Error: Exiting due to 1 error(s), 24 warning(s)\n'
module msm6295 (
	input RESET_N,
	
	input CLK,
	
	inout [7:0] CPU_DI,
	
	output [7:0] CPU_DO,
	
	input CS_N,
	
	input RD_N,
	input WR_N,
	
	input SS,
	
	output reg [17:0] ROM_ADDR,
	
	input [7:0] ROM_DATA,
	
	output wire signed [21:0] SOUND_OUT,
	
	output reg [3:0] V1_STATE,
	
	output reg [2:0] MAIN_STATE,
	
	output reg [17:0] V1_SA,
	output reg [17:0] V1_EA,
	
	output reg V1_GATE, V2_GATE, V3_GATE, V4_GATE,
	
	output wire WR_N_RISING,
	
	output reg WRITE_STATE,
	
	output wire [7:0] CPU_DI_DBG,
	
	output wire [3:0] V1_NIB,
	output wire [3:0] V2_NIB,
	output wire [3:0] V3_NIB,
	output wire [3:0] V4_NIB,

	output reg signed [17:0] V1_SAMP_OUT,
	output reg signed [17:0] V2_SAMP_OUT,
	output reg signed [17:0] V3_SAMP_OUT,
	output reg signed [17:0] V4_SAMP_OUT,
	
	output reg signed [12:0] V1_SIGNAL,
	output reg signed [12:0] V2_SIGNAL,
	output reg signed [12:0] V3_SIGNAL,
	output reg signed [12:0] V4_SIGNAL,
	
	output reg SAMP_PULSE
);

wire signed [21:0] SOUND_MIX = {V1_SAMP_OUT[17],V1_SAMP_OUT} + {V2_SAMP_OUT[17],V2_SAMP_OUT} + {V3_SAMP_OUT[17],V3_SAMP_OUT} + {V4_SAMP_OUT[17],V4_SAMP_OUT};
assign SOUND_OUT = SOUND_MIX;


assign CPU_DI_DBG = CPU_DI;



`ifndef VERILATOR 
assign CPU_DO = {4'b1111, V4_GATE, V3_GATE, V2_GATE, V1_GATE};
`endif






wire signed [6:0] V1_VOL_MUL =  (V1_ATTEN==4'd0) ? 8'h20 :
						 (V1_ATTEN==4'd1) ? 8'h16 :
						 (V1_ATTEN==4'd2) ? 8'h10 :
						 (V1_ATTEN==4'd3) ? 8'h0B :
						 (V1_ATTEN==4'd4) ? 8'h08 :
						 (V1_ATTEN==4'd5) ? 8'h06 :
						 (V1_ATTEN==4'd6) ? 8'h04 :
						 (V1_ATTEN==4'd7) ? 8'h03 :
						 (V1_ATTEN==4'd8) ? 8'h02 :
							8'h00;
										
wire signed [6:0] V2_VOL_MUL =  (V2_ATTEN==4'd0) ? 8'h20 :
						 (V2_ATTEN==4'd1) ? 8'h16 :
						 (V2_ATTEN==4'd2) ? 8'h10 :
						 (V2_ATTEN==4'd3) ? 8'h0B :
						 (V2_ATTEN==4'd4) ? 8'h08 :
						 (V2_ATTEN==4'd5) ? 8'h06 :
						 (V2_ATTEN==4'd6) ? 8'h04 :
						 (V2_ATTEN==4'd7) ? 8'h03 :
						 (V2_ATTEN==4'd8) ? 8'h02 :
							8'h00;
										
wire signed [6:0] V3_VOL_MUL =  (V3_ATTEN==4'd0) ? 8'h20 :
						 (V3_ATTEN==4'd1) ? 8'h16 :
						 (V3_ATTEN==4'd2) ? 8'h10 :
						 (V3_ATTEN==4'd3) ? 8'h0B :
						 (V3_ATTEN==4'd4) ? 8'h08 :
						 (V3_ATTEN==4'd5) ? 8'h06 :
						 (V3_ATTEN==4'd6) ? 8'h04 :
						 (V3_ATTEN==4'd7) ? 8'h03 :
						 (V3_ATTEN==4'd8) ? 8'h02 :
							8'h00;
										
wire signed [6:0] V4_VOL_MUL =  (V4_ATTEN==4'd0) ? 8'h20 :
						 (V4_ATTEN==4'd1) ? 8'h16 :
						 (V4_ATTEN==4'd2) ? 8'h10 :
						 (V4_ATTEN==4'd3) ? 8'h0B :
						 (V4_ATTEN==4'd4) ? 8'h08 :
						 (V4_ATTEN==4'd5) ? 8'h06 :
						 (V4_ATTEN==4'd6) ? 8'h04 :
						 (V4_ATTEN==4'd7) ? 8'h03 :
						 (V4_ATTEN==4'd8) ? 8'h02 :
							8'h00;


reg [6:0] PHRASE_SEL;



assign V1_NIB = (!V1_INDEX[0]) ? ROM_DATA[7:4] : ROM_DATA[3:0];
assign V2_NIB = (!V2_INDEX[0]) ? ROM_DATA[7:4] : ROM_DATA[3:0];
assign V3_NIB = (!V3_INDEX[0]) ? ROM_DATA[7:4] : ROM_DATA[3:0];
assign V4_NIB = (!V4_INDEX[0]) ? ROM_DATA[7:4] : ROM_DATA[3:0];


reg WR_N_1;

assign WR_N_RISING = (!WR_N_1 && WR_N);








reg [18:0] V1_INDEX;
reg [18:0] V2_INDEX;
reg [18:0] V3_INDEX;
reg [18:0] V4_INDEX;


reg [17:0] V2_SA;
reg [17:0] V3_SA;
reg [17:0] V4_SA;


reg [17:0] V2_EA;
reg [17:0] V3_EA;
reg [17:0] V4_EA;

reg [3:0] V1_ATTEN;
reg [3:0] V2_ATTEN;
reg [3:0] V3_ATTEN;
reg [3:0] V4_ATTEN;


reg [3:0] V2_STATE;
reg [3:0] V3_STATE;
reg [3:0] V4_STATE;

reg [9:0] COUNTER;

always @(posedge CLK or negedge RESET_N)
if (!RESET_N) begin
	WR_N_1 <= 1'b1;
	WRITE_STATE <= 1'b0;
	
	V1_INDEX <= 0;
	
	V1_GATE <= 1'b0;
	V2_GATE <= 1'b0;
	V3_GATE <= 1'b0;
	V4_GATE <= 1'b0;
	
	V1_ATTEN <= 4'd0;
	V2_ATTEN <= 4'd0;
	V3_ATTEN <= 4'd0;
	V4_ATTEN <= 4'd0;
	
	V1_STATE <= 4'd0;
	V2_STATE <= 4'd0;
	V3_STATE <= 4'd0;
	V4_STATE <= 4'd0;
	
	MAIN_STATE <= 3'd0;
	
	COUNTER <= 10'd1;
end
else begin
	WR_N_1 <= WR_N;
	
	SAMP_PULSE <= 1'b0;	

	if (COUNTER==10'd0) begin
		SAMP_PULSE <= 1'b1;
		


		
		if (!SS) COUNTER <= 10'd492;
		else COUNTER <= 10'd393;
		
	end
	else COUNTER <= COUNTER - 1'b1;


	if (!WRITE_STATE && !CS_N && !WR_N && !CPU_DI[7]) begin
		if (CPU_DI[3]) V1_GATE <= 1'b0;
		if (CPU_DI[4]) V2_GATE <= 1'b0;
		if (CPU_DI[5]) V3_GATE <= 1'b0;
		if (CPU_DI[6]) V4_GATE <= 1'b0;		
	end	
	


	if (!WRITE_STATE && !CS_N && !WR_N && CPU_DI[7]) begin
		PHRASE_SEL <= CPU_DI[6:0];
		WRITE_STATE <= 1'b1;
	end

	if (WRITE_STATE && !CS_N && !WR_N) begin













		if (CPU_DI[4]) begin
			V1_INDEX <= {PHRASE_SEL, 4'b0000};
			V1_ATTEN <= CPU_DI[3:0];
			V1_STATE <= 4'd0;
			V1_GATE <= 1'b1;
		end
		else if (CPU_DI[5]) begin
			V2_INDEX <= {PHRASE_SEL, 4'b0000};
			V2_ATTEN <= CPU_DI[3:0];
			V2_STATE <= 4'd0;
			V2_GATE <= 1'b1;
		end
		else if (CPU_DI[6]) begin
			V3_INDEX <= {PHRASE_SEL, 4'b0000};
			V3_ATTEN <= CPU_DI[3:0];
			V3_STATE <= 4'd0;
			V3_GATE <= 1'b1;
		end
		else if (CPU_DI[7]) begin
			V4_INDEX <= {PHRASE_SEL, 4'b0000};
			V4_ATTEN <= CPU_DI[3:0];
			V4_STATE <= 4'd0;
			V4_GATE <= 1'b1;
		end
		WRITE_STATE <= 1'b0;
	end


	case (MAIN_STATE)

	0: begin
		case (V1_STATE)
		0: begin
			if (V1_GATE) begin
				V1_SIGNAL <= -2;
				V1_STEP <= 0;
				ROM_ADDR <= V1_INDEX[18:1];
				V1_STATE <= V1_STATE + 1;
			end
			else MAIN_STATE <= MAIN_STATE + 3'd1;
		end
	
		1: begin
			V1_SA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V1_STATE <= V1_STATE + 1;
		end

		2: begin
			V1_SA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V1_STATE <= V1_STATE + 1;
		end

		3: begin
			V1_SA[7:0] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V1_STATE <= V1_STATE + 1;
		end

		4: begin
			V1_EA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V1_STATE <= V1_STATE + 1;
		end

		5: begin
			V1_EA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V1_STATE <= V1_STATE + 1;
		end

		6: begin
			V1_EA[7:0] <= ROM_DATA;
			V1_STATE <= V1_STATE + 1;
		end
		
		7: begin
			ROM_ADDR <= V1_SA;
			V1_INDEX <= {V1_SA, 1'b0};
			V1_STATE <= V1_STATE + 1;
		end
		
		8: begin
			ROM_ADDR <= V1_INDEX[18:1];
			V1_STATE <= V1_STATE + 1;
		end
		
		9: begin
			if (V1_GATE && (V1_INDEX[18:1]>18'h3ff) && (V1_INDEX[18:1]>=V1_SA) && (V1_INDEX[18:1]<=V1_EA)) begin
			
				V1_SIGNAL <= V1_SIGNAL + ADPCM_DATA;

				case (V1_NIB[2:0])
				0: V1_STEP <= V1_STEP + -1;
				1: V1_STEP <= V1_STEP + -1;
				2: V1_STEP <= V1_STEP + -1;
				3: V1_STEP <= V1_STEP + -1;
				4: V1_STEP <= V1_STEP + 2;
				5: V1_STEP <= V1_STEP + 4;
				6: V1_STEP <= V1_STEP + 6;
				7: V1_STEP <= V1_STEP + 8;
				default:;
				endcase

				V1_INDEX <= V1_INDEX + 1;
				V1_STATE <= 4'd8;
			end
			else begin
				V1_GATE <= 1'b0;
				V1_STATE <= 4'd0;
			end
			MAIN_STATE <= MAIN_STATE + 3'd1;
		end
		
		default:;
		endcase
	end
	

	1: begin
		case (V2_STATE)
		0: begin
			if (V2_GATE) begin
				V2_SIGNAL <= -2;
				V2_STEP <= 0;
				ROM_ADDR <= V2_INDEX[18:1];
				V2_STATE <= V2_STATE + 1;
			end
			else MAIN_STATE <= MAIN_STATE + 3'd1;
		end
	
		1: begin
			V2_SA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V2_STATE <= V2_STATE + 1;
		end

		2: begin
			V2_SA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V2_STATE <= V2_STATE + 1;
		end

		3: begin
			V2_SA[7:0] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V2_STATE <= V2_STATE + 1;
		end

		4: begin
			V2_EA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V2_STATE <= V2_STATE + 1;
		end

		5: begin
			V2_EA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V2_STATE <= V2_STATE + 1;
		end

		6: begin
			V2_EA[7:0] <= ROM_DATA;
			V2_STATE <= V2_STATE + 1;
		end
		
		7: begin
			ROM_ADDR <= V2_SA;
			V2_INDEX <= {V2_SA, 1'b0};
			V2_STATE <= V2_STATE + 1;
		end
		
		8: begin
			ROM_ADDR <= V2_INDEX[18:1];
			V2_STATE <= V2_STATE + 1;
		end
		
		9: begin
			if (V2_GATE && (V2_INDEX[18:1]>18'h3ff) && (V2_INDEX[18:1]>=V2_SA) && (V2_INDEX[18:1]<=V2_EA)) begin
			
				V2_SIGNAL <= V2_SIGNAL + ADPCM_DATA;

				case (V2_NIB[2:0])
				0: V2_STEP <= V2_STEP + -1;
				1: V2_STEP <= V2_STEP + -1;
				2: V2_STEP <= V2_STEP + -1;
				3: V2_STEP <= V2_STEP + -1;
				4: V2_STEP <= V2_STEP + 2;
				5: V2_STEP <= V2_STEP + 4;
				6: V2_STEP <= V2_STEP + 6;
				7: V2_STEP <= V2_STEP + 8;
				default:;
				endcase

				V2_INDEX <= V2_INDEX + 1;
				V2_STATE <= 4'd8;
			end
			else begin

				V2_GATE <= 1'b0;
				V2_STATE <= 4'd0;
			end
			MAIN_STATE <= MAIN_STATE + 3'd1;
		end
		
		default:;
		endcase
	end
	

	2: begin
		case (V3_STATE)
		0: begin
			if (V3_GATE) begin
				V3_SIGNAL <= -2;
				V3_STEP <= 0;
				ROM_ADDR <= V3_INDEX[18:1];
				V3_STATE <= V3_STATE + 1;
			end
			else MAIN_STATE <= MAIN_STATE + 3'd1;
		end
	
		1: begin
			V3_SA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V3_STATE <= V3_STATE + 1;
		end

		2: begin
			V3_SA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V3_STATE <= V3_STATE + 1;
		end

		3: begin
			V3_SA[7:0] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V3_STATE <= V3_STATE + 1;
		end

		4: begin
			V3_EA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V3_STATE <= V3_STATE + 1;
		end

		5: begin
			V3_EA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V3_STATE <= V3_STATE + 1;
		end

		6: begin
			V3_EA[7:0] <= ROM_DATA;
			V3_STATE <= V3_STATE + 1;
		end
		
		7: begin
			ROM_ADDR <= V3_SA;
			V3_INDEX <= {V3_SA, 1'b0};
			V3_STATE <= V3_STATE + 1;
		end
		
		8: begin
			ROM_ADDR <= V3_INDEX[18:1];
			V3_STATE <= V3_STATE + 1;
		end
		
		9: begin
			if (V3_GATE && (V3_INDEX[18:1]>18'h3ff) && (V3_INDEX[18:1]>=V3_SA) && (V3_INDEX[18:1]<=V3_EA)) begin
			
				V3_SIGNAL <= V3_SIGNAL + ADPCM_DATA;

				case (V3_NIB[2:0])
				0: V3_STEP <= V3_STEP + -1;
				1: V3_STEP <= V3_STEP + -1;
				2: V3_STEP <= V3_STEP + -1;
				3: V3_STEP <= V3_STEP + -1;
				4: V3_STEP <= V3_STEP + 2;
				5: V3_STEP <= V3_STEP + 4;
				6: V3_STEP <= V3_STEP + 6;
				7: V3_STEP <= V3_STEP + 8;
				default:;
				endcase

				V3_INDEX <= V3_INDEX + 1;
				V3_STATE <= 4'd8;
			end
			else begin
				V3_GATE <= 1'b0;
				V3_STATE <= 4'd0;
			end
			MAIN_STATE <= MAIN_STATE + 3'd1;
		end
		
		default:;
		endcase
	end
	

	3: begin
		case (V4_STATE)
		0: begin
			if (V4_GATE) begin
				V4_SIGNAL <= -2;
				V4_STEP <= 0;
				ROM_ADDR <= V4_INDEX[18:1];
				V4_STATE <= V4_STATE + 1;
			end
			else MAIN_STATE <= MAIN_STATE + 3'd1;
		end
	
		1: begin
			V4_SA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V4_STATE <= V4_STATE + 1;
		end

		2: begin
			V4_SA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V4_STATE <= V4_STATE + 1;
		end

		3: begin
			V4_SA[7:0] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V4_STATE <= V4_STATE + 1;
		end

		4: begin
			V4_EA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V4_STATE <= V4_STATE + 1;
		end

		5: begin
			V4_EA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V4_STATE <= V4_STATE + 1;
		end

		6: begin
			V4_EA[7:0] <= ROM_DATA;
			V4_STATE <= V4_STATE + 1;
		end
		
		7: begin
			ROM_ADDR <= V4_SA;
			V4_INDEX <= {V4_SA, 1'b0};
			V4_STATE <= V4_STATE + 1;
		end
		
		8: begin
			ROM_ADDR <= V4_INDEX[18:1];
			V4_STATE <= V4_STATE + 1;
		end
		
		9: begin
			if (V4_GATE && (V4_INDEX[18:1]>18'h3ff) && (V4_INDEX[18:1]>=V4_SA) && (V4_INDEX[18:1]<=V4_EA)) begin
			
				V4_SIGNAL <= V4_SIGNAL + ADPCM_DATA;

				case (V4_NIB[2:0])
				0: V4_STEP <= V4_STEP + -1;
				1: V4_STEP <= V4_STEP + -1;
				2: V4_STEP <= V4_STEP + -1;
				3: V4_STEP <= V4_STEP + -1;
				4: V4_STEP <= V4_STEP + 2;
				5: V4_STEP <= V4_STEP + 4;
				6: V4_STEP <= V4_STEP + 6;
				7: V4_STEP <= V4_STEP + 8;
				default:;
				endcase

				V4_INDEX <= V4_INDEX + 1;
				V4_STATE <= 4'd8;
			end
			else begin
				V4_GATE <= 1'b0;
				V4_STATE <= 4'd0;
			end
			MAIN_STATE <= MAIN_STATE + 3'd1;
		end
		
		default:;
		endcase
	end
	

	4: begin

		if (V1_SIGNAL > 2047) V1_SIGNAL <= 2047;
		else if (V1_SIGNAL < -2048) V1_SIGNAL <= -2048;
		if (V2_SIGNAL > 2047) V2_SIGNAL <= 2047;
		else if (V2_SIGNAL < -2048) V2_SIGNAL <= -2048;
		if (V3_SIGNAL > 2047) V3_SIGNAL <= 2047;
		else if (V3_SIGNAL < -2048) V3_SIGNAL <= -2048;
		if (V4_SIGNAL > 2047) V4_SIGNAL <= 2047;
		else if (V4_SIGNAL < -2048) V4_SIGNAL <= -2048;
		

		if (V1_STEP > 48) V1_STEP <= 48;
		else if (V1_STEP < 0) V1_STEP <= 0;
		if (V2_STEP > 48) V2_STEP <= 48;
		else if (V2_STEP < 0) V2_STEP <= 0;
		if (V3_STEP > 48) V3_STEP <= 48;
		else if (V3_STEP < 0) V3_STEP <= 0;
		if (V4_STEP > 48) V4_STEP <= 48;
		else if (V4_STEP < 0) V4_STEP <= 0;
		
		MAIN_STATE <= MAIN_STATE + 3'd1;
	end
	

	5: begin	
		if (SAMP_PULSE) begin
			V1_SAMP_OUT <= (V1_GATE) ? V1_SIGNAL * V1_VOL_MUL : 18'd0;
			V2_SAMP_OUT <= (V2_GATE) ? V2_SIGNAL * V2_VOL_MUL : 18'd0;
			V3_SAMP_OUT <= (V3_GATE) ? V3_SIGNAL * V3_VOL_MUL : 18'd0;
			V4_SAMP_OUT <= (V4_GATE) ? V4_SIGNAL * V4_VOL_MUL : 18'd0;
			MAIN_STATE <= 3'd0;
		end
	end
	
	default:;
	endcase

end









reg signed [6:0] V1_STEP;
reg signed [6:0] V2_STEP;
reg signed [6:0] V3_STEP;
reg signed [6:0] V4_STEP;


wire [11:0] ADPCM_ADDR = (MAIN_STATE==0) ? (V1_STEP * 16) + V1_NIB :
								 (MAIN_STATE==1) ? (V2_STEP * 16) + V2_NIB :
								 (MAIN_STATE==2) ? (V3_STEP * 16) + V3_NIB :
														 (V4_STEP * 16) + V4_NIB;

wire signed [15:0] ADPCM_DATA;

ADPCM_LUT_ROM ADPCM_LUT_ROM
(
	.ADDR( ADPCM_ADDR ) ,
	.DATA( ADPCM_DATA )
);


endmodule
module msm6295 (
	input RESET_N,
	
	input CLK,
	
	inout [7:0] CPU_DI,
	
	output [7:0] CPU_DO,
	
	input CS_N,
	
	input RD_N,
	input WR_N,
	
	input SS,
	
	output reg [17:0] ROM_ADDR,
	
	input [7:0] ROM_DATA,
	
	output wire signed [21:0] SOUND_OUT,
	
	output reg [3:0] V1_STATE,
	
	output reg [2:0] MAIN_STATE,
	
	output reg [17:0] V1_SA,
	output reg [17:0] V1_EA,
	
	output reg V1_GATE, V2_GATE, V3_GATE, V4_GATE,
	
	output wire WR_N_RISING,
	
	output reg WRITE_STATE,
	
	output wire [7:0] CPU_DI_DBG,
	
	output wire [3:0] V1_NIB,
	output wire [3:0] V2_NIB,
	output wire [3:0] V3_NIB,
	output wire [3:0] V4_NIB,

	output reg signed [17:0] V1_SAMP_OUT,
	output reg signed [17:0] V2_SAMP_OUT,
	output reg signed [17:0] V3_SAMP_OUT,
	output reg signed [17:0] V4_SAMP_OUT,
	
	output reg signed [12:0] V1_SIGNAL,
	output reg signed [12:0] V2_SIGNAL,
	output reg signed [12:0] V3_SIGNAL,
	output reg signed [12:0] V4_SIGNAL,
	
	output reg SAMP_PULSE
);


wire signed [21:0] SOUND_MIX = {V1_SAMP_OUT[17],V1_SAMP_OUT} + {V2_SAMP_OUT[17],V2_SAMP_OUT} + {V3_SAMP_OUT[17],V3_SAMP_OUT} + {V4_SAMP_OUT[17],V4_SAMP_OUT};
assign SOUND_OUT = SOUND_MIX;


assign CPU_DI_DBG = CPU_DI;



`ifndef VERILATOR 
assign CPU_DO = {4'b1111, V4_GATE, V3_GATE, V2_GATE, V1_GATE};
`endif






wire signed [6:0] V1_VOL_MUL =  (V1_ATTEN==4'd0) ? 8'h20 :
						 (V1_ATTEN==4'd1) ? 8'h16 :
						 (V1_ATTEN==4'd2) ? 8'h10 :
						 (V1_ATTEN==4'd3) ? 8'h0B :
						 (V1_ATTEN==4'd4) ? 8'h08 :
						 (V1_ATTEN==4'd5) ? 8'h06 :
						 (V1_ATTEN==4'd6) ? 8'h04 :
						 (V1_ATTEN==4'd7) ? 8'h03 :
						 (V1_ATTEN==4'd8) ? 8'h02 :
							8'h00;
										
wire signed [6:0] V2_VOL_MUL =  (V2_ATTEN==4'd0) ? 8'h20 :
						 (V2_ATTEN==4'd1) ? 8'h16 :
						 (V2_ATTEN==4'd2) ? 8'h10 :
						 (V2_ATTEN==4'd3) ? 8'h0B :
						 (V2_ATTEN==4'd4) ? 8'h08 :
						 (V2_ATTEN==4'd5) ? 8'h06 :
						 (V2_ATTEN==4'd6) ? 8'h04 :
						 (V2_ATTEN==4'd7) ? 8'h03 :
						 (V2_ATTEN==4'd8) ? 8'h02 :
							8'h00;
										
wire signed [6:0] V3_VOL_MUL =  (V3_ATTEN==4'd0) ? 8'h20 :
						 (V3_ATTEN==4'd1) ? 8'h16 :
						 (V3_ATTEN==4'd2) ? 8'h10 :
						 (V3_ATTEN==4'd3) ? 8'h0B :
						 (V3_ATTEN==4'd4) ? 8'h08 :
						 (V3_ATTEN==4'd5) ? 8'h06 :
						 (V3_ATTEN==4'd6) ? 8'h04 :
						 (V3_ATTEN==4'd7) ? 8'h03 :
						 (V3_ATTEN==4'd8) ? 8'h02 :
							8'h00;
										
wire signed [6:0] V4_VOL_MUL =  (V4_ATTEN==4'd0) ? 8'h20 :
						 (V4_ATTEN==4'd1) ? 8'h16 :
						 (V4_ATTEN==4'd2) ? 8'h10 :
						 (V4_ATTEN==4'd3) ? 8'h0B :
						 (V4_ATTEN==4'd4) ? 8'h08 :
						 (V4_ATTEN==4'd5) ? 8'h06 :
						 (V4_ATTEN==4'd6) ? 8'h04 :
						 (V4_ATTEN==4'd7) ? 8'h03 :
						 (V4_ATTEN==4'd8) ? 8'h02 :
							8'h00;


reg [6:0] PHRASE_SEL;



assign V1_NIB = (!V1_INDEX[0]) ? ROM_DATA[7:4] : ROM_DATA[3:0];
assign V2_NIB = (!V2_INDEX[0]) ? ROM_DATA[7:4] : ROM_DATA[3:0];
assign V3_NIB = (!V3_INDEX[0]) ? ROM_DATA[7:4] : ROM_DATA[3:0];
assign V4_NIB = (!V4_INDEX[0]) ? ROM_DATA[7:4] : ROM_DATA[3:0];


reg WR_N_1;

assign WR_N_RISING = (!WR_N_1 && WR_N);








reg [18:0] V1_INDEX;
reg [18:0] V2_INDEX;
reg [18:0] V3_INDEX;
reg [18:0] V4_INDEX;


reg [17:0] V2_SA;
reg [17:0] V3_SA;
reg [17:0] V4_SA;


reg [17:0] V2_EA;
reg [17:0] V3_EA;
reg [17:0] V4_EA;

reg [3:0] V1_ATTEN;
reg [3:0] V2_ATTEN;
reg [3:0] V3_ATTEN;
reg [3:0] V4_ATTEN;


reg [3:0] V2_STATE;
reg [3:0] V3_STATE;
reg [3:0] V4_STATE;

reg [9:0] COUNTER;

always @(posedge CLK or negedge RESET_N)
if (!RESET_N) begin
	WR_N_1 <= 1'b1;
	WRITE_STATE <= 1'b0;
	
	V1_INDEX <= 0;
	
	V1_GATE <= 1'b0;
	V2_GATE <= 1'b0;
	V3_GATE <= 1'b0;
	V4_GATE <= 1'b0;
	
	V1_ATTEN <= 4'd0;
	V2_ATTEN <= 4'd0;
	V3_ATTEN <= 4'd0;
	V4_ATTEN <= 4'd0;
	
	V1_STATE <= 4'd0;
	V2_STATE <= 4'd0;
	V3_STATE <= 4'd0;
	V4_STATE <= 4'd0;
	
	MAIN_STATE <= 3'd0;
	
	COUNTER <= 10'd1;
end
else begin
	WR_N_1 <= WR_N;
	
	SAMP_PULSE <= 1'b0;	

	if (COUNTER==10'd0) begin
		SAMP_PULSE <= 1'b1;
		


		
		if (!SS) COUNTER <= 10'd492;
		else COUNTER <= 10'd393;
		
	end
	else COUNTER <= COUNTER - 1'b1;


	if (!WRITE_STATE && !CS_N && !WR_N && !CPU_DI[7]) begin
		if (CPU_DI[3]) V1_GATE <= 1'b0;
		if (CPU_DI[4]) V2_GATE <= 1'b0;
		if (CPU_DI[5]) V3_GATE <= 1'b0;
		if (CPU_DI[6]) V4_GATE <= 1'b0;		
	end	
	


	if (!WRITE_STATE && !CS_N && !WR_N && CPU_DI[7]) begin
		PHRASE_SEL <= CPU_DI[6:0];
		WRITE_STATE <= 1'b1;
	end

	if (WRITE_STATE && !CS_N && !WR_N) begin













		if (CPU_DI[4]) begin
			V1_INDEX <= {PHRASE_SEL, 4'b0000};
			V1_ATTEN <= CPU_DI[3:0];
			V1_STATE <= 4'd0;
			V1_GATE <= 1'b1;
		end
		else if (CPU_DI[5]) begin
			V2_INDEX <= {PHRASE_SEL, 4'b0000};
			V2_ATTEN <= CPU_DI[3:0];
			V2_STATE <= 4'd0;
			V2_GATE <= 1'b1;
		end
		else if (CPU_DI[6]) begin
			V3_INDEX <= {PHRASE_SEL, 4'b0000};
			V3_ATTEN <= CPU_DI[3:0];
			V3_STATE <= 4'd0;
			V3_GATE <= 1'b1;
		end
		else if (CPU_DI[7]) begin
			V4_INDEX <= {PHRASE_SEL, 4'b0000};
			V4_ATTEN <= CPU_DI[3:0];
			V4_STATE <= 4'd0;
			V4_GATE <= 1'b1;
		end
		WRITE_STATE <= 1'b0;
	end


	case (MAIN_STATE)

	0: begin
		case (V1_STATE)
		0: begin
			if (V1_GATE) begin
				V1_SIGNAL <= -2;
				V1_STEP <= 0;
				ROM_ADDR <= V1_INDEX[18:1];
				V1_STATE <= V1_STATE + 1;
			end
			else MAIN_STATE <= MAIN_STATE + 3'd1;
		end
	
		1: begin
			V1_SA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V1_STATE <= V1_STATE + 1;
		end

		2: begin
			V1_SA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V1_STATE <= V1_STATE + 1;
		end

		3: begin
			V1_SA[7:0] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V1_STATE <= V1_STATE + 1;
		end

		4: begin
			V1_EA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V1_STATE <= V1_STATE + 1;
		end

		5: begin
			V1_EA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V1_STATE <= V1_STATE + 1;
		end

		6: begin
			V1_EA[7:0] <= ROM_DATA;
			V1_STATE <= V1_STATE + 1;
		end
		
		7: begin
			ROM_ADDR <= V1_SA;
			V1_INDEX <= {V1_SA, 1'b0};
			V1_STATE <= V1_STATE + 1;
		end
		
		8: begin
			ROM_ADDR <= V1_INDEX[18:1];
			V1_STATE <= V1_STATE + 1;
		end
		
		9: begin
			if (V1_GATE && (V1_INDEX[18:1]>18'h3ff) && (V1_INDEX[18:1]>=V1_SA) && (V1_INDEX[18:1]<=V1_EA)) begin
			
				V1_SIGNAL <= V1_SIGNAL + ADPCM_DATA;

				case (V1_NIB[2:0])
				0: V1_STEP <= V1_STEP + -1;
				1: V1_STEP <= V1_STEP + -1;
				2: V1_STEP <= V1_STEP + -1;
				3: V1_STEP <= V1_STEP + -1;
				4: V1_STEP <= V1_STEP + 2;
				5: V1_STEP <= V1_STEP + 4;
				6: V1_STEP <= V1_STEP + 6;
				7: V1_STEP <= V1_STEP + 8;
				default:;
				endcase

				V1_INDEX <= V1_INDEX + 1;
				V1_STATE <= 4'd8;
			end
			else begin
				V1_GATE <= 1'b0;
				V1_STATE <= 4'd0;
			end
			MAIN_STATE <= MAIN_STATE + 3'd1;
		end
		
		default:;
		endcase
	end
	

	1: begin
		case (V2_STATE)
		0: begin
			if (V2_GATE) begin
				V2_SIGNAL <= -2;
				V2_STEP <= 0;
				ROM_ADDR <= V2_INDEX[18:1];
				V2_STATE <= V2_STATE + 1;
			end
			else MAIN_STATE <= MAIN_STATE + 3'd1;
		end
	
		1: begin
			V2_SA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V2_STATE <= V2_STATE + 1;
		end

		2: begin
			V2_SA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V2_STATE <= V2_STATE + 1;
		end

		3: begin
			V2_SA[7:0] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V2_STATE <= V2_STATE + 1;
		end

		4: begin
			V2_EA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V2_STATE <= V2_STATE + 1;
		end

		5: begin
			V2_EA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V2_STATE <= V2_STATE + 1;
		end

		6: begin
			V2_EA[7:0] <= ROM_DATA;
			V2_STATE <= V2_STATE + 1;
		end
		
		7: begin
			ROM_ADDR <= V2_SA;
			V2_INDEX <= {V2_SA, 1'b0};
			V2_STATE <= V2_STATE + 1;
		end
		
		8: begin
			ROM_ADDR <= V2_INDEX[18:1];
			V2_STATE <= V2_STATE + 1;
		end
		
		9: begin
			if (V2_GATE && (V2_INDEX[18:1]>18'h3ff) && (V2_INDEX[18:1]>=V2_SA) && (V2_INDEX[18:1]<=V2_EA)) begin
			
				V2_SIGNAL <= V2_SIGNAL + ADPCM_DATA;

				case (V2_NIB[2:0])
				0: V2_STEP <= V2_STEP + -1;
				1: V2_STEP <= V2_STEP + -1;
				2: V2_STEP <= V2_STEP + -1;
				3: V2_STEP <= V2_STEP + -1;
				4: V2_STEP <= V2_STEP + 2;
				5: V2_STEP <= V2_STEP + 4;
				6: V2_STEP <= V2_STEP + 6;
				7: V2_STEP <= V2_STEP + 8;
				default:;
				endcase

				V2_INDEX <= V2_INDEX + 1;
				V2_STATE <= 4'd8;
			end
			else begin

				V2_GATE <= 1'b0;
				V2_STATE <= 4'd0;
			end
			MAIN_STATE <= MAIN_STATE + 3'd1;
		end
		
		default:;
		endcase
	end
	

	2: begin
		case (V3_STATE)
		0: begin
			if (V3_GATE) begin
				V3_SIGNAL <= -2;
				V3_STEP <= 0;
				ROM_ADDR <= V3_INDEX[18:1];
				V3_STATE <= V3_STATE + 1;
			end
			else MAIN_STATE <= MAIN_STATE + 3'd1;
		end
	
		1: begin
			V3_SA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V3_STATE <= V3_STATE + 1;
		end

		2: begin
			V3_SA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V3_STATE <= V3_STATE + 1;
		end

		3: begin
			V3_SA[7:0] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V3_STATE <= V3_STATE + 1;
		end

		4: begin
			V3_EA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V3_STATE <= V3_STATE + 1;
		end

		5: begin
			V3_EA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V3_STATE <= V3_STATE + 1;
		end

		6: begin
			V3_EA[7:0] <= ROM_DATA;
			V3_STATE <= V3_STATE + 1;
		end
		
		7: begin
			ROM_ADDR <= V3_SA;
			V3_INDEX <= {V3_SA, 1'b0};
			V3_STATE <= V3_STATE + 1;
		end
		
		8: begin
			ROM_ADDR <= V3_INDEX[18:1];
			V3_STATE <= V3_STATE + 1;
		end
		
		9: begin
			if (V3_GATE && (V3_INDEX[18:1]>18'h3ff) && (V3_INDEX[18:1]>=V3_SA) && (V3_INDEX[18:1]<=V3_EA)) begin
			
				V3_SIGNAL <= V3_SIGNAL + ADPCM_DATA;

				case (V3_NIB[2:0])
				0: V3_STEP <= V3_STEP + -1;
				1: V3_STEP <= V3_STEP + -1;
				2: V3_STEP <= V3_STEP + -1;
				3: V3_STEP <= V3_STEP + -1;
				4: V3_STEP <= V3_STEP + 2;
				5: V3_STEP <= V3_STEP + 4;
				6: V3_STEP <= V3_STEP + 6;
				7: V3_STEP <= V3_STEP + 8;
				default:;
				endcase

				V3_INDEX <= V3_INDEX + 1;
				V3_STATE <= 4'd8;
			end
			else begin
				V3_GATE <= 1'b0;
				V3_STATE <= 4'd0;
			end
			MAIN_STATE <= MAIN_STATE + 3'd1;
		end
		
		default:;
		endcase
	end
	

	3: begin
		case (V4_STATE)
		0: begin
			if (V4_GATE) begin
				V4_SIGNAL <= -2;
				V4_STEP <= 0;
				ROM_ADDR <= V4_INDEX[18:1];
				V4_STATE <= V4_STATE + 1;
			end
			else MAIN_STATE <= MAIN_STATE + 3'd1;
		end
	
		1: begin
			V4_SA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V4_STATE <= V4_STATE + 1;
		end

		2: begin
			V4_SA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V4_STATE <= V4_STATE + 1;
		end

		3: begin
			V4_SA[7:0] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V4_STATE <= V4_STATE + 1;
		end

		4: begin
			V4_EA[17:16] <= ROM_DATA[1:0];
			ROM_ADDR <= ROM_ADDR + 1;
			V4_STATE <= V4_STATE + 1;
		end

		5: begin
			V4_EA[15:8] <= ROM_DATA;
			ROM_ADDR <= ROM_ADDR + 1;
			V4_STATE <= V4_STATE + 1;
		end

		6: begin
			V4_EA[7:0] <= ROM_DATA;
			V4_STATE <= V4_STATE + 1;
		end
		
		7: begin
			ROM_ADDR <= V4_SA;
			V4_INDEX <= {V4_SA, 1'b0};
			V4_STATE <= V4_STATE + 1;
		end
		
		8: begin
			ROM_ADDR <= V4_INDEX[18:1];
			V4_STATE <= V4_STATE + 1;
		end
		
		9: begin
			if (V4_GATE && (V4_INDEX[18:1]>18'h3ff) && (V4_INDEX[18:1]>=V4_SA) && (V4_INDEX[18:1]<=V4_EA)) begin
			
				V4_SIGNAL <= V4_SIGNAL + ADPCM_DATA;

				case (V4_NIB[2:0])
				0: V4_STEP <= V4_STEP + -1;
				1: V4_STEP <= V4_STEP + -1;
				2: V4_STEP <= V4_STEP + -1;
				3: V4_STEP <= V4_STEP + -1;
				4: V4_STEP <= V4_STEP + 2;
				5: V4_STEP <= V4_STEP + 4;
				6: V4_STEP <= V4_STEP + 6;
				7: V4_STEP <= V4_STEP + 8;
				default:;
				endcase

				V4_INDEX <= V4_INDEX + 1;
				V4_STATE <= 4'd8;
			end
			else begin
				V4_GATE <= 1'b0;
				V4_STATE <= 4'd0;
			end
			MAIN_STATE <= MAIN_STATE + 3'd1;
		end
		
		default:;
		endcase
	end
	

	4: begin

		if (V1_SIGNAL > 2047) V1_SIGNAL <= 2047;
		else if (V1_SIGNAL < -2048) V1_SIGNAL <= -2048;
		if (V2_SIGNAL > 2047) V2_SIGNAL <= 2047;
		else if (V2_SIGNAL < -2048) V2_SIGNAL <= -2048;
		if (V3_SIGNAL > 2047) V3_SIGNAL <= 2047;
		else if (V3_SIGNAL < -2048) V3_SIGNAL <= -2048;
		if (V4_SIGNAL > 2047) V4_SIGNAL <= 2047;
		else if (V4_SIGNAL < -2048) V4_SIGNAL <= -2048;
		

		if (V1_STEP > 48) V1_STEP <= 48;
		else if (V1_STEP < 0) V1_STEP <= 0;
		if (V2_STEP > 48) V2_STEP <= 48;
		else if (V2_STEP < 0) V2_STEP <= 0;
		if (V3_STEP > 48) V3_STEP <= 48;
		else if (V3_STEP < 0) V3_STEP <= 0;
		if (V4_STEP > 48) V4_STEP <= 48;
		else if (V4_STEP < 0) V4_STEP <= 0;
		
		MAIN_STATE <= MAIN_STATE + 3'd1;
	end
	

	5: begin	
		if (SAMP_PULSE) begin
			V1_SAMP_OUT <= (V1_GATE) ? V1_SIGNAL * V1_VOL_MUL : 18'd0;
			V2_SAMP_OUT <= (V2_GATE) ? V2_SIGNAL * V2_VOL_MUL : 18'd0;
			V3_SAMP_OUT <= (V3_GATE) ? V3_SIGNAL * V3_VOL_MUL : 18'd0;
			V4_SAMP_OUT <= (V4_GATE) ? V4_SIGNAL * V4_VOL_MUL : 18'd0;
			MAIN_STATE <= 3'd0;
		end
	end
	
	default:;
	endcase

end









reg signed [6:0] V1_STEP;
reg signed [6:0] V2_STEP;
reg signed [6:0] V3_STEP;
reg signed [6:0] V4_STEP;


wire [11:0] ADPCM_ADDR = (MAIN_STATE==0) ? (V1_STEP * 16) + V1_NIB :
								 (MAIN_STATE==1) ? (V2_STEP * 16) + V2_NIB :
								 (MAIN_STATE==2) ? (V3_STEP * 16) + V3_NIB :
														 (V4_STEP * 16) + V4_NIB;

wire signed [15:0] ADPCM_DATA;

ADPCM_LUT_ROM ADPCM_LUT_ROM
(
	.ADDR( ADPCM_ADDR ) ,
	.DATA( ADPCM_DATA )
);


endmodule