data/full_repos/permissive/210844779/lab5/5.4/multiplier.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/210844779/lab5/5.4/multiplier.v:9: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                            : ... In instance multiplier\n  reg [15:0]temp=8\'b00;\n                 ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab5/5.4/multiplier.v:35: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'temp_and\' generates 8 bits.\n                                                                             : ... In instance multiplier\n      temp=temp_and;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab5/5.4/multiplier.v:49: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'tempb\' generates 8 bits.\n                                                                             : ... In instance multiplier\n       if(tempb)\n       ^~\n%Error: Exiting due to 3 warning(s)\n'
module multiplier(a,b,load,rst,clk,q,valid);
  input [7:0]a,b;
  input load,rst,clk;
  output reg [16:0]q;
  output reg valid;
  
  reg [7:0]tempa=8'b00,tempb=8'b00;
  wire [7:0]temp_and;
  reg [15:0]temp=8'b00;
  
  integer i;
  
  assign temp_and=tempb[0]?tempa:8'b00;
  always@(posedge clk,posedge rst)
  if (rst)
    begin
    tempa=0;
    tempb=0;
    q=0;
    valid=0;
    i=0;
    end
  else
    if(load)
    begin
      tempa=a;
      tempb=b;
      temp=16'b00;
      i=0;
      q=0;
    end
    
  else
    begin
      temp=temp_and;
      tempb=tempb>>1;
        if(i<=7)
          begin
            temp=temp<<i;
            q=q+temp;
            i=i+1;
          end
        else
          begin
            i=0;
            temp=0;
          end
          
       if(tempb)
         valid=0;
       else
        valid=1'b1;
        
  end
  
endmodule
module multiplier(a,b,load,rst,clk,q,valid);

  input [7:0]a,b;
  input load,rst,clk;
  output reg [16:0]q;
  output reg valid;
  
  reg [7:0]tempa=8'b00,tempb=8'b00;
  wire [7:0]temp_and;
  reg [15:0]temp=8'b00;
  
  integer i;
  
  assign temp_and=tempb[0]?tempa:8'b00;
  always@(posedge clk,posedge rst)
  if (rst)
    begin
    tempa=0;
    tempb=0;
    q=0;
    valid=0;
    i=0;
    end
  else
    if(load)
    begin
      tempa=a;
      tempb=b;
      temp=16'b00;
      i=0;
      q=0;
    end
    
  else
    begin
      temp=temp_and;
      tempb=tempb>>1;
        if(i<=7)
          begin
            temp=temp<<i;
            q=q+temp;
            i=i+1;
          end
        else
          begin
            i=0;
            temp=0;
          end
          
       if(tempb)
         valid=0;
       else
        valid=1'b1;
        
  end
  
endmodule