data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v
 line:79: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v:7: Unsupported: Ignoring delay on this delayed statement.\n always #1 CLOCK100 <= ~CLOCK100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v:8: Unsupported: Ignoring delay on this delayed statement.\n always #1 CLOCK150 <= ~CLOCK150;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v:9: Unsupported: Ignoring delay on this delayed statement.\n always #2 CLOCK65 <= ~CLOCK65;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #0   CLOCK100 = 0; CLOCK150 = 0; CLOCK65 = 0; RESET_N = 0; fp_ln = $fopen("./cordic_ln.txt", "w");\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #100  RESET_N = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #1500000 $stop; $fclose(fp_ln);\n  ^\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v:41: Cannot find file containing module: \'cordic_ln\'\n cordic_ln    cordic_ln_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.r(r_in_),.ln_r(ln_r_out_));\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143584361/projects/aFPGA/02_testbench,data/full_repos/permissive/143584361/cordic_ln\n             data/full_repos/permissive/143584361/projects/aFPGA/02_testbench,data/full_repos/permissive/143584361/cordic_ln.v\n             data/full_repos/permissive/143584361/projects/aFPGA/02_testbench,data/full_repos/permissive/143584361/cordic_ln.sv\n             cordic_ln\n             cordic_ln.v\n             cordic_ln.sv\n             obj_dir/cordic_ln\n             obj_dir/cordic_ln.v\n             obj_dir/cordic_ln.sv\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v:44: Cannot find file containing module: \'cordic_rot\'\n cordic_rot    cordic_rot_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(1024),.src_y(r_in_),.rho(rho),.theta(phase));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v:47: Cannot find file containing module: \'cordic_exp_rtl\'\n cordic_exp_rtl   cordic_exp_rtl_inst(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(r_in_),.rho(rho_exp));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v:50: Cannot find file containing module: \'cordic_tanh_sigm_rtl\'\n cordic_tanh_sigm_rtl cordic_tanh_sigm_rtl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(r_in_), .rho(rho_tanh_sigmoid),.algorithm(2\'B10));\n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cordic.v:63: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_in_\' generates 64 bits.\n                                                                                               : ... In instance tb_cordic\n  r_in_shifter[0] <= r_in_;\n                  ^~\n%Error: Exiting due to 4 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_cordic;
	
	reg			CLOCK100, CLOCK150, CLOCK65, RESET_N;
	
	always #1	CLOCK100 <= ~CLOCK100;
	always #1	CLOCK150 <= ~CLOCK150;
	always #2	CLOCK65 <= ~CLOCK65;


	wire					sys_clk = CLOCK100;
	wire					sys_rst_n = RESET_N;
	reg				[31:0]	mask;
	always @(posedge sys_clk)
		if(!sys_rst_n)
			mask <= 0;
		else if(mask<=200)
			mask <= mask + 1;
	reg		signed 	[63:0]	r_in_;
	reg						r_in_en_;
	always @(posedge sys_clk)
		if(mask<=200)
		begin
			r_in_ <= -65536*256;
			r_in_en_ <= 0;
		end
		else if(r_in_<65536*20000)
		begin
			r_in_ <= r_in_ + 32768;
			r_in_en_ <= 1;
		end
		else
		begin
			r_in_ <= -65536*20000;
			r_in_en_ <= 1;
		end
	
	
	wire	signed	[31:0]	ln_r_out_;
	cordic_ln				cordic_ln_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.r(r_in_),.ln_r(ln_r_out_));
	wire	signed	[31:0]	rho;
	wire	signed	[31:0]	phase;
	cordic_rot				cordic_rot_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(1024),.src_y(r_in_),.rho(rho),.theta(phase));

	wire	signed	[31:0]	rho_exp;
	cordic_exp_rtl			cordic_exp_rtl_inst(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(r_in_),.rho(rho_exp));

	wire	signed	[31:0]	rho_tanh_sigmoid;
	cordic_tanh_sigm_rtl	cordic_tanh_sigm_rtl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(r_in_), .rho(rho_tanh_sigmoid),.algorithm(2'B10));
	


	reg				[15:0]	r_in_en_shifter;
	reg		signed	[31:0]	r_in_shifter	[0:15];
	integer p;
	always @(posedge sys_clk)
	begin
		r_in_en_shifter <= {r_in_en_shifter[14:0], r_in_en_};

		for(p=1; p<16; p=p+1)
			r_in_shifter[p] <= r_in_shifter[p-1];
		r_in_shifter[0] <= r_in_;
	end
	
	wire	signed	[31:0]	r_in_shifter10 = r_in_shifter[10];
		
	integer	fp_ln;
	always @(posedge sys_clk)
		if(r_in_en_shifter[10])
			$fwrite(fp_ln, "%d, %d\n", r_in_shifter[10], ln_r_out_);

	initial
	begin
	
		#0			CLOCK100 = 0; CLOCK150 = 0; CLOCK65 = 0; RESET_N = 0; fp_ln = $fopen("./cordic_ln.txt", "w");
		#100		RESET_N = 1;

		#1500000	$stop; $fclose(fp_ln);
	end
	
endmodule
module tb_cordic;

	
	reg			CLOCK100, CLOCK150, CLOCK65, RESET_N;
	
	always #1	CLOCK100 <= ~CLOCK100;
	always #1	CLOCK150 <= ~CLOCK150;
	always #2	CLOCK65 <= ~CLOCK65;


	wire					sys_clk = CLOCK100;
	wire					sys_rst_n = RESET_N;
	reg				[31:0]	mask;
	always @(posedge sys_clk)
		if(!sys_rst_n)
			mask <= 0;
		else if(mask<=200)
			mask <= mask + 1;
	reg		signed 	[63:0]	r_in_;
	reg						r_in_en_;
	always @(posedge sys_clk)
		if(mask<=200)
		begin
			r_in_ <= -65536*256;
			r_in_en_ <= 0;
		end
		else if(r_in_<65536*20000)
		begin
			r_in_ <= r_in_ + 32768;
			r_in_en_ <= 1;
		end
		else
		begin
			r_in_ <= -65536*20000;
			r_in_en_ <= 1;
		end
	
	
	wire	signed	[31:0]	ln_r_out_;
	cordic_ln				cordic_ln_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.r(r_in_),.ln_r(ln_r_out_));
	wire	signed	[31:0]	rho;
	wire	signed	[31:0]	phase;
	cordic_rot				cordic_rot_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(1024),.src_y(r_in_),.rho(rho),.theta(phase));

	wire	signed	[31:0]	rho_exp;
	cordic_exp_rtl			cordic_exp_rtl_inst(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(r_in_),.rho(rho_exp));

	wire	signed	[31:0]	rho_tanh_sigmoid;
	cordic_tanh_sigm_rtl	cordic_tanh_sigm_rtl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(r_in_), .rho(rho_tanh_sigmoid),.algorithm(2'B10));
	


	reg				[15:0]	r_in_en_shifter;
	reg		signed	[31:0]	r_in_shifter	[0:15];
	integer p;
	always @(posedge sys_clk)
	begin
		r_in_en_shifter <= {r_in_en_shifter[14:0], r_in_en_};

		for(p=1; p<16; p=p+1)
			r_in_shifter[p] <= r_in_shifter[p-1];
		r_in_shifter[0] <= r_in_;
	end
	
	wire	signed	[31:0]	r_in_shifter10 = r_in_shifter[10];
		
	integer	fp_ln;
	always @(posedge sys_clk)
		if(r_in_en_shifter[10])
			$fwrite(fp_ln, "%d, %d\n", r_in_shifter[10], ln_r_out_);

	initial
	begin
	
		#0			CLOCK100 = 0; CLOCK150 = 0; CLOCK65 = 0; RESET_N = 0; fp_ln = $fopen("./cordic_ln.txt", "w");
		#100		RESET_N = 1;

		#1500000	$stop; $fclose(fp_ln);
	end
	
endmodule