data/full_repos/permissive/155713836/src/chiplet_sys.v
1: b"%Error: data/full_repos/permissive/155713836/src/chiplet_sys.v:102: Cannot find file containing module: 'fifos_interface'\n  fifos_interface fifo_interface (\n  ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155713836/src,data/full_repos/permissive/155713836/fifos_interface\n             data/full_repos/permissive/155713836/src,data/full_repos/permissive/155713836/fifos_interface.v\n             data/full_repos/permissive/155713836/src,data/full_repos/permissive/155713836/fifos_interface.sv\n             fifos_interface\n             fifos_interface.v\n             fifos_interface.sv\n             obj_dir/fifos_interface\n             obj_dir/fifos_interface.v\n             obj_dir/fifos_interface.sv\n%Error: data/full_repos/permissive/155713836/src/chiplet_sys.v:132: Cannot find file containing module: 'strawman_rx_fsm'\n  strawman_rx_fsm strawman_s_rx_fsm(\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/155713836/src/chiplet_sys.v:158: Cannot find file containing module: 'strawman_rx_fsm'\n  strawman_rx_fsm strawman_m_rx_fsm(\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/155713836/src/chiplet_sys.v:185: Cannot find file containing module: 'strawman_tx_fsm'\n  strawman_tx_fsm strawman_m_tx_fsm(\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/155713836/src/chiplet_sys.v:195: Cannot find file containing module: 'strawman_tx_fsm'\n  strawman_tx_fsm strawman_s_tx_fsm(\n  ^~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module chiplet_sys (
  clk,

  i_master_tx_packetstream,
  i_master_tx_packetstream_valid,
  o_master_tx_fsm_ready, 

  i_slave_tx_packetstream,
  i_slave_tx_packetstream_wen,
  o_slave_tx_fsm_ready,

  i_slave_rx_ready,
  i_master_rx_ready,

  o_slave_rx_data,
  o_slave_rx_data_valid, 
  o_slave_rx_addr, 
  o_slave_rx_addr_valid, 
  o_slave_rx_cmd,
  o_slave_rx_cmd_valid,
  o_slave_rx_feature0,
  o_slave_rx_feature0_valid,
  o_slave_rx_feature1,
  o_slave_rx_feature1_valid,
  o_slave_rx_length,
  o_slave_rx_length_valid,

  o_master_rx_data,
  o_master_rx_data_valid,
  o_master_rx_addr,
  o_master_rx_addr_valid,
  o_master_rx_cmd,
  o_master_rx_cmd_valid,
  o_master_rx_feature0,
  o_master_rx_feature0_valid,
  o_master_rx_feature1,
  o_master_rx_feature1_valid,
  o_master_rx_length,
  o_master_rx_length_valid

);

  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;
  parameter WORD_SIZE = 32;

  input clk;

  input [1075:0] i_master_tx_packetstream;
  input i_master_tx_packetstream_valid;
  output o_master_tx_fsm_ready;

  input [1075:0] i_slave_tx_packetstream;
  input i_slave_tx_packetstream_wen;
  output o_slave_tx_fsm_ready;

  input i_slave_rx_ready, i_master_rx_ready;

  output [31:0] o_slave_rx_data, o_master_rx_data;
  output o_slave_rx_data_valid, o_master_rx_data_valid;

  output [31:0] o_slave_rx_addr, o_master_rx_addr;
  output o_slave_rx_addr_valid, o_master_rx_addr_valid;

  output [2:0] o_slave_rx_cmd, o_master_rx_cmd;
  output o_slave_rx_cmd_valid, o_master_rx_cmd_valid;

  output [5:0] o_slave_rx_feature0, o_master_rx_feature0;
  output o_slave_rx_feature0_valid, o_master_rx_feature0_valid;

  output [5:0] o_slave_rx_feature1, o_master_rx_feature1;
  output o_slave_rx_feature1_valid, o_master_rx_feature1_valid;

  output [2:0] o_slave_rx_length, o_master_rx_length;
  output o_slave_rx_length_valid, o_master_rx_length_valid;


  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] w_sc_rreq_outbits, w_mc_rreq_outbits;
  wire w_slave_rx_ren, w_master_rx_ren;

  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] w_master_tx_packetstream;

  wire [DATA_LINE_WIDTH-1:0] w_m_tx_fsm_packet, w_s_tx_fsm_packet;
  wire w_m_tx_fsm_packet_valid, w_s_tx_fsm_packet_valid;

  wire [LOG2_FIFO_DEPTH:0] credits_m2s = FIFO_DEPTH;
  wire [LOG2_FIFO_DEPTH:0] credits_s2m = FIFO_DEPTH;

  wire w_mc_sreq_fifo_empty, w_mc_sreq_fifo_full;
  wire w_sc_sresp_fifo_empty, w_sc_sresp_fifo_full;


  fifos_interface fifo_interface (
    .clk(clk),


    .i_mc_sreq_inbits(w_m_tx_fsm_packet),
    .i_mc_sreq_wen(w_m_tx_fsm_packet_valid),
    .o_mc_sreq_fifo_empty(w_mc_sreq_fifo_empty),
    .o_mc_sreq_fifo_full(w_mc_sreq_fifo_full),
  

    .i_sc_rreq_ren(w_slave_rx_ren),
    .o_sc_rreq_outbits(w_sc_rreq_outbits),


    .i_sc_sresp_inbits(w_s_tx_fsm_packet),
    .i_sc_sresp_wen(w_s_tx_fsm_packet_valid),
    .o_sc_sresp_fifo_empty(w_sc_sresp_fifo_empty),
    .o_sc_sresp_fifo_full(w_sc_sresp_fifo_full),


    .i_mc_rresp_ren(w_master_rx_ren),
    .o_mc_rresp_outbits(w_mc_rreq_outbits),


    .o_credits_m2s(credits_m2s),
    .o_credits_s2m(credits_s2m)
  );



  strawman_rx_fsm strawman_s_rx_fsm(
    .clk(clk),
    .i_flit(w_sc_rreq_outbits),
    .i_slave_rx_ready(i_slave_rx_ready),

    .o_slave_rx_ren(w_slave_rx_ren),
    .o_address_valid(o_slave_rx_addr_valid),
    .o_data_valid(o_slave_rx_data_valid),
    .o_data(o_slave_rx_data),
    .o_address(o_slave_rx_addr),

    .o_cmd(o_slave_rx_cmd),
    .o_cmd_valid(o_slave_rx_cmd_valid),

    .o_feature0(o_slave_rx_feature0),
    .o_feature0_valid(o_slave_rx_feature0_valid),

    .o_feature1(o_slave_rx_feature1),
    .o_feature1_valid(o_slave_rx_feature1_valid),

    .o_length(o_slave_rx_length),
    .o_length_valid(o_slave_rx_length_valid)
  );



  strawman_rx_fsm strawman_m_rx_fsm(
    .clk(clk),
    .i_flit(w_mc_rreq_outbits),
    .i_slave_rx_ready(i_master_rx_ready),

    .o_slave_rx_ren(w_master_rx_ren),
    .o_address_valid(o_master_rx_addr_valid),
    .o_data_valid(o_master_rx_data_valid),
    .o_data(o_master_rx_data),
    .o_address(o_master_rx_addr),

    .o_cmd(o_master_rx_cmd),
    .o_cmd_valid(o_master_rx_cmd_valid),

    .o_feature0(o_master_rx_feature0),
    .o_feature0_valid(o_master_rx_feature0_valid),

    .o_feature1(o_master_rx_feature0),
    .o_feature1_valid(o_master_rx_feature1_valid),

    .o_length(o_master_rx_length),
    .o_length_valid(o_master_rx_length_valid)
  );




  strawman_tx_fsm strawman_m_tx_fsm(
    .clk(clk),
    .o_flit(w_m_tx_fsm_packet),
    .o_flit_valid(w_m_tx_fsm_packet_valid),
    .o_ready(o_master_tx_fsm_ready),
    .i_protocol_bus(i_master_tx_packetstream),
    .i_valid(i_master_tx_packetstream_valid)
  );


  strawman_tx_fsm strawman_s_tx_fsm(
    .clk(clk),
    .o_flit(w_s_tx_fsm_packet),
    .o_flit_valid(w_s_tx_fsm_packet_valid),
    .o_ready(o_slave_tx_fsm_ready),
    .i_protocol_bus(i_slave_tx_packetstream),
    .i_valid(i_slave_tx_packetstream_valid)
  );



endmodule
module chiplet_sys (
  clk,

  i_master_tx_packetstream,
  i_master_tx_packetstream_valid,
  o_master_tx_fsm_ready, 

  i_slave_tx_packetstream,
  i_slave_tx_packetstream_wen,
  o_slave_tx_fsm_ready,

  i_slave_rx_ready,
  i_master_rx_ready,

  o_slave_rx_data,
  o_slave_rx_data_valid, 
  o_slave_rx_addr, 
  o_slave_rx_addr_valid, 
  o_slave_rx_cmd,
  o_slave_rx_cmd_valid,
  o_slave_rx_feature0,
  o_slave_rx_feature0_valid,
  o_slave_rx_feature1,
  o_slave_rx_feature1_valid,
  o_slave_rx_length,
  o_slave_rx_length_valid,

  o_master_rx_data,
  o_master_rx_data_valid,
  o_master_rx_addr,
  o_master_rx_addr_valid,
  o_master_rx_cmd,
  o_master_rx_cmd_valid,
  o_master_rx_feature0,
  o_master_rx_feature0_valid,
  o_master_rx_feature1,
  o_master_rx_feature1_valid,
  o_master_rx_length,
  o_master_rx_length_valid

);


  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;
  parameter WORD_SIZE = 32;

  input clk;

  input [1075:0] i_master_tx_packetstream;
  input i_master_tx_packetstream_valid;
  output o_master_tx_fsm_ready;

  input [1075:0] i_slave_tx_packetstream;
  input i_slave_tx_packetstream_wen;
  output o_slave_tx_fsm_ready;

  input i_slave_rx_ready, i_master_rx_ready;

  output [31:0] o_slave_rx_data, o_master_rx_data;
  output o_slave_rx_data_valid, o_master_rx_data_valid;

  output [31:0] o_slave_rx_addr, o_master_rx_addr;
  output o_slave_rx_addr_valid, o_master_rx_addr_valid;

  output [2:0] o_slave_rx_cmd, o_master_rx_cmd;
  output o_slave_rx_cmd_valid, o_master_rx_cmd_valid;

  output [5:0] o_slave_rx_feature0, o_master_rx_feature0;
  output o_slave_rx_feature0_valid, o_master_rx_feature0_valid;

  output [5:0] o_slave_rx_feature1, o_master_rx_feature1;
  output o_slave_rx_feature1_valid, o_master_rx_feature1_valid;

  output [2:0] o_slave_rx_length, o_master_rx_length;
  output o_slave_rx_length_valid, o_master_rx_length_valid;


  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] w_sc_rreq_outbits, w_mc_rreq_outbits;
  wire w_slave_rx_ren, w_master_rx_ren;

  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] w_master_tx_packetstream;

  wire [DATA_LINE_WIDTH-1:0] w_m_tx_fsm_packet, w_s_tx_fsm_packet;
  wire w_m_tx_fsm_packet_valid, w_s_tx_fsm_packet_valid;

  wire [LOG2_FIFO_DEPTH:0] credits_m2s = FIFO_DEPTH;
  wire [LOG2_FIFO_DEPTH:0] credits_s2m = FIFO_DEPTH;

  wire w_mc_sreq_fifo_empty, w_mc_sreq_fifo_full;
  wire w_sc_sresp_fifo_empty, w_sc_sresp_fifo_full;


  fifos_interface fifo_interface (
    .clk(clk),


    .i_mc_sreq_inbits(w_m_tx_fsm_packet),
    .i_mc_sreq_wen(w_m_tx_fsm_packet_valid),
    .o_mc_sreq_fifo_empty(w_mc_sreq_fifo_empty),
    .o_mc_sreq_fifo_full(w_mc_sreq_fifo_full),
  

    .i_sc_rreq_ren(w_slave_rx_ren),
    .o_sc_rreq_outbits(w_sc_rreq_outbits),


    .i_sc_sresp_inbits(w_s_tx_fsm_packet),
    .i_sc_sresp_wen(w_s_tx_fsm_packet_valid),
    .o_sc_sresp_fifo_empty(w_sc_sresp_fifo_empty),
    .o_sc_sresp_fifo_full(w_sc_sresp_fifo_full),


    .i_mc_rresp_ren(w_master_rx_ren),
    .o_mc_rresp_outbits(w_mc_rreq_outbits),


    .o_credits_m2s(credits_m2s),
    .o_credits_s2m(credits_s2m)
  );



  strawman_rx_fsm strawman_s_rx_fsm(
    .clk(clk),
    .i_flit(w_sc_rreq_outbits),
    .i_slave_rx_ready(i_slave_rx_ready),

    .o_slave_rx_ren(w_slave_rx_ren),
    .o_address_valid(o_slave_rx_addr_valid),
    .o_data_valid(o_slave_rx_data_valid),
    .o_data(o_slave_rx_data),
    .o_address(o_slave_rx_addr),

    .o_cmd(o_slave_rx_cmd),
    .o_cmd_valid(o_slave_rx_cmd_valid),

    .o_feature0(o_slave_rx_feature0),
    .o_feature0_valid(o_slave_rx_feature0_valid),

    .o_feature1(o_slave_rx_feature1),
    .o_feature1_valid(o_slave_rx_feature1_valid),

    .o_length(o_slave_rx_length),
    .o_length_valid(o_slave_rx_length_valid)
  );



  strawman_rx_fsm strawman_m_rx_fsm(
    .clk(clk),
    .i_flit(w_mc_rreq_outbits),
    .i_slave_rx_ready(i_master_rx_ready),

    .o_slave_rx_ren(w_master_rx_ren),
    .o_address_valid(o_master_rx_addr_valid),
    .o_data_valid(o_master_rx_data_valid),
    .o_data(o_master_rx_data),
    .o_address(o_master_rx_addr),

    .o_cmd(o_master_rx_cmd),
    .o_cmd_valid(o_master_rx_cmd_valid),

    .o_feature0(o_master_rx_feature0),
    .o_feature0_valid(o_master_rx_feature0_valid),

    .o_feature1(o_master_rx_feature0),
    .o_feature1_valid(o_master_rx_feature1_valid),

    .o_length(o_master_rx_length),
    .o_length_valid(o_master_rx_length_valid)
  );




  strawman_tx_fsm strawman_m_tx_fsm(
    .clk(clk),
    .o_flit(w_m_tx_fsm_packet),
    .o_flit_valid(w_m_tx_fsm_packet_valid),
    .o_ready(o_master_tx_fsm_ready),
    .i_protocol_bus(i_master_tx_packetstream),
    .i_valid(i_master_tx_packetstream_valid)
  );


  strawman_tx_fsm strawman_s_tx_fsm(
    .clk(clk),
    .o_flit(w_s_tx_fsm_packet),
    .o_flit_valid(w_s_tx_fsm_packet_valid),
    .o_ready(o_slave_tx_fsm_ready),
    .i_protocol_bus(i_slave_tx_packetstream),
    .i_valid(i_slave_tx_packetstream_valid)
  );



endmodule