data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v
1: b"%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:119: Cannot find file containing module: 'uartm'\nuartm u_uartm_inst (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/169225814/modules/ccs0101/verif,data/full_repos/permissive/169225814/uartm\n             data/full_repos/permissive/169225814/modules/ccs0101/verif,data/full_repos/permissive/169225814/uartm.v\n             data/full_repos/permissive/169225814/modules/ccs0101/verif,data/full_repos/permissive/169225814/uartm.sv\n             uartm\n             uartm.v\n             uartm.sv\n             obj_dir/uartm\n             obj_dir/uartm.v\n             obj_dir/uartm.sv\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:137: Cannot find file containing module: 'uartm'\nuartm u_spis_inst (\n^~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:157: Cannot find file containing module: 'ahb_ic'\nahb_ic #(\n^~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:186: Cannot find file containing module: 'gpcfg'\ngpcfg   u_gpcfg_inst (\n^~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:255: Cannot find file containing module: 'mod_mul_il'\nmod_mul_il #(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:268: Cannot find file containing module: 'mod_exp'\nmod_exp #(\n^~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:283: Cannot find file containing module: 'bin_ext_gcd'\nbin_ext_gcd #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:297: Cannot find file containing module: 'random_num_gen'\nrandom_num_gen #(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:308: Cannot find file containing module: 'random_num_gen'\nrandom_num_gen #(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:321: Cannot find file containing module: 'gpio'\ngpio u_gpio_inst (\n^~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:336: Cannot find file containing module: 'uarts'\nuarts u_uarts_inst (\n^~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:369: Cannot find file containing module: 'chiplib_mux3'\n    chiplib_mux3 u_uartm_tx_pad_in_mux_inst (.a (uartm_tx),     .b (gpcfg_reg[0][24]), .c (cleq_host_irq),        .s ({gpcfg_reg[0][17], gpcfg_reg[0][16]}), .y (pad_in[3]));   \n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:370: Cannot find file containing module: 'chiplib_mux3'\n    chiplib_mux3 u_uartm_rx_pad_in_mux_inst (.a (1'b0),         .b (gpcfg_reg[1][24]), .c (1'b0),           .s ({gpcfg_reg[1][17], gpcfg_reg[1][16]}), .y (pad_in[4]));   \n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:371: Cannot find file containing module: 'chiplib_mux3'\n    chiplib_mux3 u_uarts_tx_pad_in_mux_inst (.a (uarts_tx),     .b (gpcfg_reg[2][24]), .c (cleq_host_irq),        .s ({gpcfg_reg[2][17], gpcfg_reg[2][16]}), .y (pad_in[5]));   \n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:372: Cannot find file containing module: 'chiplib_mux3'\n    chiplib_mux3 u_uarts_rx_pad_in_mux_inst (.a (1'b0),         .b (gpcfg_reg[3][24]), .c (1'b0),           .s ({gpcfg_reg[3][17], gpcfg_reg[3][16]}), .y (pad_in[6]));   \n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:373: Cannot find file containing module: 'chiplib_mux3'\n    chiplib_mux3 u_gpio0_pad_in_mux_inst    (.a (gpio_out[0]),  .b (gpcfg_reg[4][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[4][17], gpcfg_reg[4][16]}), .y (pad_in[7]));   \n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:374: Cannot find file containing module: 'chiplib_mux3'\n    chiplib_mux3 u_gpio1_pad_in_mux_inst    (.a (gpio_out[1]),  .b (gpcfg_reg[5][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[5][17], gpcfg_reg[5][16]}), .y (pad_in[8]));   \n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:375: Cannot find file containing module: 'chiplib_mux3'\n    chiplib_mux3 u_gpio2_pad_in_mux_inst    (.a (gpio_out[2]),  .b (gpcfg_reg[6][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[6][17], gpcfg_reg[6][16]}), .y (pad_in[9]));   \n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:376: Cannot find file containing module: 'chiplib_mux3'\n    chiplib_mux3 u_gpio3_pad_in_mux_inst    (.a (gpio_out[3]),  .b (gpcfg_reg[7][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[7][17], gpcfg_reg[7][16]}), .y (pad_in[10]));  \n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:405: Cannot find file containing module: 'chiplib_mux3'\n    chiplib_mux3 u_uartm_rx_mux_inst (.a (pad_out[4]), .b (1'b1), .c (pad_out[5]),                   .s ({gpcfg_reg[1][17], gpcfg_reg[1][16]}), .y(uartm_rx));   \n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/ccs0101/verif/chip_core.v:406: Cannot find file containing module: 'chiplib_mux4'\n    chiplib_mux4 u_uarts_rx_mux_inst (.a (pad_out[6]), .b (1'b1), .c (pad_out[3]), .d (pad_out[5]),  .s ({gpcfg_reg[3][17], gpcfg_reg[3][16]}), .y(uarts_rx));   \n    ^~~~~~~~~~~~\n%Error: Exiting due to 21 error(s)\n"
module chip_core #(
  parameter NUM_PADS  = 11,
  parameter PAD_CTL_W = 9
  )(
  output wire [NUM_PADS-1  :3]  pad_in,
  input  wire [NUM_PADS-1  :0]  pad_out,
  output wire [PAD_CTL_W-1 :0]  pad_ctl[NUM_PADS-1   :3]

);






  localparam NUM_MASTERS = 2;
  localparam NUM_SLAVES  = 2;

  localparam SPI_M_ID    = 0;
  localparam UARTM_M_ID  = 1;

  localparam GPCFG_S_ID  = 0;
  localparam GPIO_S_ID   = 1;

  localparam GPCFG_BASE  = 32'h4002_0000;
  localparam GPIO_BASE   = 32'h4003_0000;

  localparam NBITS  = 2048;

wire        hclk;
wire        nreset;

wire        nreset_sync;
reg         nreset_sync0;
reg         nreset_sync1;
reg         nreset_sync2;

wire [1:0]  htrans_m0;
wire [31:0] haddr_m0;
wire [2:0]  hsize_m0;
wire [31:0] hwdata_m0;
wire [31:0] hrdata_m0;
wire [31:0] hrdata_gpcfg;
wire [31:0] hrdata_sram_wrap;

wire [31:0] gpcfg_reg[63:0];

wire [ 1:0] htrans_m[NUM_MASTERS-1 :0];
wire [31:0] haddr_m[NUM_MASTERS-1 :0];
wire [ 2:0] hsize_m[NUM_MASTERS-1 :0];
wire [31:0] hwdata_m[NUM_MASTERS-1 :0];
wire        hwrite_m[NUM_MASTERS-1 :0];
wire [31:0] hrdata_m[NUM_MASTERS-1 :0];
wire        hready_m[NUM_MASTERS-1 :0];
wire        hresp_m[NUM_MASTERS-1 :0];
wire        hsel_s[NUM_SLAVES-1 :0];
wire [31:0] haddr_s[NUM_SLAVES-1 :0];
wire [ 2:0] hsize_s[NUM_SLAVES-1 :0];
wire        hwrite_s[NUM_SLAVES-1 :0];
wire [31:0] hwdata_s[NUM_SLAVES-1 :0];
wire [31:0] hrdata_s[NUM_SLAVES-1 :0];
wire        hready_s[NUM_SLAVES-1 :0];
wire        hresp_s[NUM_SLAVES-1 :0];

wire        gpio_irq;
wire [3:0]  gpio_out;
wire [3:0]  gpio_in;

wire [31:0] uarts_rx_data;

wire enable_p_mod_mul_il;
wire enable_p_mod_exp;
wire enable_p_bin_ext_gcd;
wire done_irq_p_mod_mul_il;
wire done_irq_p_mod_exp;
wire done_irq_p_bin_ext_gcd;
wire [11:0]    maxbits;
wire [2047:0]  arg_a;
wire [2047:0]  arg_b;
wire [2047:0]  modulus;
wire [2047:0]  exp;
wire [2047:0]  r_red_extgcd;
wire [2047:0]  mod_mul_il_y;
wire [2047:0]  mod_exp_y;
wire [2048:0]  x;

wire [2047:0]  gcd;
wire [1023:0]  rng0_y;
wire [1023:0]  rng1_y;



uartm u_uartm_inst (
  .hclk        (hclk),
  .hresetn     (nreset_sync),
  .haddr       (haddr_m[UARTM_M_ID]),
  .hsize       (hsize_m[UARTM_M_ID]),
  .htrans      (htrans_m[UARTM_M_ID]),
  .hwdata      (hwdata_m[UARTM_M_ID]),
  .hwrite      (hwrite_m[UARTM_M_ID]),
  .hrdata      (hrdata_m[UARTM_M_ID]),
  .hready      (hready_m[UARTM_M_ID]),
  .hresp       (hresp_m[UARTM_M_ID]),
  .uartm_baud  (gpcfg_reg[17]),
  .uartm_ctl   (gpcfg_reg[18]),
  .TX          (uartm_tx),
  .RX          (uartm_rx)
);


uartm u_spis_inst (
  .hclk        (hclk),
  .hresetn     (nreset_sync),
  .haddr       (haddr_m[SPI_M_ID]),
  .hsize       (hsize_m[SPI_M_ID]),
  .htrans      (htrans_m[SPI_M_ID]),
  .hwdata      (hwdata_m[SPI_M_ID]),
  .hwrite      (hwrite_m[SPI_M_ID]),
  .hrdata      (hrdata_m[SPI_M_ID]),
  .hready      (hready_m[SPI_M_ID]),
  .hresp       (hresp_m[SPI_M_ID]),
  .uartm_baud  (gpcfg_reg[17]),
  .uartm_ctl   (gpcfg_reg[18]),
  .TX          (),
  .RX          (1'b1)
);




ahb_ic #(
  .NUM_SLAVES  (NUM_SLAVES),
  .NUM_MASTERS (NUM_MASTERS),
  .SLAVE_BASE  ( {GPIO_BASE,
                  GPCFG_BASE})
  ) u_ahb_ic_inst (  
  .hclk      (hclk),
  .hresetn   (nreset_sync),
  .htrans_m  (htrans_m),
  .haddr_m   (haddr_m),
  .hsize_m   (hsize_m),
  .hwdata_m  (hwdata_m),
  .hwrite_m  (hwrite_m),
  .hrdata_m  (hrdata_m),
  .hready_m  (hready_m),
  .hresp_m   (hresp_m),
  .hsel_s    (hsel_s),
  .haddr_s   (haddr_s),
  .hsize_s   (hsize_s),
  .hwrite_s  (hwrite_s),
  .hwdata_s  (hwdata_s),
  .hrdata_s  (hrdata_s),
  .hready_s  (hready_s),
  .hresp_s   (hresp_s)
);




gpcfg   u_gpcfg_inst (
  .hclk                     (hclk),
  .hresetn                  (nreset_sync),
  .hsel                     (hsel_s[GPCFG_S_ID]),
  .haddr                    (haddr_s[GPCFG_S_ID]),
  .hsize                    (hsize_s[GPCFG_S_ID]),
  .hwdata                   (hwdata_s[GPCFG_S_ID]),
  .hwrite                   (hwrite_s[GPCFG_S_ID]),
  .hrdata                   (hrdata_s[GPCFG_S_ID]),
  .hready                   (hready_s[GPCFG_S_ID]),
  .hresp                    (hresp_s[GPCFG_S_ID]),
  .pad03_ctl_reg            (gpcfg_reg[0]),
  .pad04_ctl_reg            (gpcfg_reg[1]),
  .pad05_ctl_reg            (gpcfg_reg[2]),
  .pad06_ctl_reg            (gpcfg_reg[3]),
  .pad07_ctl_reg            (gpcfg_reg[4]),
  .pad08_ctl_reg            (gpcfg_reg[5]),
  .pad09_ctl_reg            (gpcfg_reg[6]),
  .pad10_ctl_reg            (gpcfg_reg[7]),
  .pad11_ctl_reg            (gpcfg_reg[8]),
  .pad12_ctl_reg            (gpcfg_reg[9]),
  .pad13_ctl_reg            (gpcfg_reg[10]),
  .pad14_ctl_reg            (gpcfg_reg[11]),
  .pad15_ctl_reg            (gpcfg_reg[12]),
  .pad16_ctl_reg            (gpcfg_reg[13]),
  .pad17_ctl_reg            (gpcfg_reg[14]),
  .pad18_ctl_reg            (gpcfg_reg[15]),
  .pad19_ctl_reg            (gpcfg_reg[16]),
  .uartm_baud_ctl_reg       (gpcfg_reg[17]),
  .uartm_ctl_reg            (gpcfg_reg[18]),
  .uarts_baud_ctl_reg       (gpcfg_reg[34]),
  .uarts_ctl_reg            (gpcfg_reg[35]),
  .uarts_tx_data_reg        (gpcfg_reg[36]),

  .uarts_rx_data            (uarts_rx_data),
  .uarts_tx_send_reg        (gpcfg_reg[38]),
  .spare0_reg               (gpcfg_reg[39]),
  .spare1_reg               (gpcfg_reg[40]),
  .spare2_reg               (gpcfg_reg[41]),
  .signature_reg            (gpcfg_reg[51]),
  .maxbits                  (maxbits),
  .r_red_extgcd             (r_red_extgcd),
  .arg_a                    (arg_a),
  .arg_b                    (arg_b),
  .exp                      (exp),
  .modulus                        (modulus),
  .x                        (x),
  .gcd                      (gcd),
  .mod_mul_il_y             (mod_mul_il_y),
  .mod_exp_y                (mod_exp_y),
  .rng0_y                   (rng0_y),
  .rng1_y                   (rng1_y),
  .bypass_vn                (bypass_vn),
  .enable_p_mod_mul_il      (enable_p_mod_mul_il),
  .enable_p_mod_exp         (enable_p_mod_exp),
  .enable_p_bin_ext_gcd     (enable_p_bin_ext_gcd),
  .enable_p_rng0            (enable_p_rng0),
  .enable_p_rng1            (enable_p_rng1),
  .cleq_host_irq            (cleq_host_irq),
  .done_irq_p_mod_mul_il    (done_irq_p_mod_mul_il),
  .done_irq_p_mod_exp       (done_irq_p_mod_exp),
  .done_irq_p_bin_ext_gcd   (done_irq_p_bin_ext_gcd),
  .done_irq_p_rng0          (done_irq_p_rng0        ),
  .done_irq_p_rng1          (done_irq_p_rng1        )

);



mod_mul_il #(
  .NBITS (NBITS)
 ) u_mod_mul_il_inst   (
  .clk           (hclk),
  .rst_n         (nreset_sync),
  .enable_p      (enable_p_mod_mul_il),
  .a             (arg_a),
  .b             (arg_b),
  .m             (modulus),
  .y             (mod_mul_il_y),
  .done_irq_p    (done_irq_p_mod_mul_il)
);

mod_exp #(
  .NBITS (NBITS)
 ) u_mod_exp_inst  (
  .clk        (hclk),
  .rst_n      (nreset_sync),
  .enable_p   (enable_p_mod_exp),
  .a          (arg_a),
  .exp        (exp),
  .m          (modulus),
  .m_size     (maxbits),
  .r_red      (r_red_extgcd),
  .y          (mod_exp_y),
  .done_irq_p (done_irq_p_mod_exp)
);

bin_ext_gcd #(
  .NBITS (NBITS)
 ) u_bin_ext_gcd_inst   (
  .clk           (hclk),
  .rst_n         (nreset_sync),
  .enable_p      (enable_p_bin_ext_gcd),
  .x             (arg_a),
  .y             (arg_b),
  .a             (x),
  .b             (),
  .gcd           (gcd),
  .done_irq_p    (done_irq_p_bin_ext_gcd)
);

random_num_gen #(
  .NBITS (NBITS/2) ) u_random_num_gen0_inst (
  .clk            (hclk),
  .rst_n          (nreset_sync),
  .enable_p       (enable_p_rng0),
  .bypass         (bypass_vn),
  .maxbits        (maxbits),
  .done_p         (done_irq_p_rng0),
  .y              (rng0_y)
);

random_num_gen #(
  .NBITS (NBITS/2) ) u_random_num_gen1_inst (
  .clk            (hclk),
  .rst_n          (nreset_sync),
  .enable_p       (enable_p_rng1),
  .bypass         (bypass_vn),
  .maxbits        (maxbits),
  .done_p         (done_irq_p_rng1),
  .y              (rng1_y)
);



gpio u_gpio_inst (
	.hclk        (hclk),
	.hresetn     (nreset_sync),
	.hsel        (hsel_s[GPIO_S_ID]),
	.haddr       (haddr_s[GPIO_S_ID]),
	.hwdata      (hwdata_s[GPIO_S_ID]),
	.hwrite      (hwrite_s[GPIO_S_ID]),
	.hrdata      (hrdata_s[GPIO_S_ID]),
	.hready      (hready_s[GPIO_S_ID]),
	.hresp       (hresp_s[GPIO_S_ID]),
	.intc        (gpio_irq),
	.gpio_out    (gpio_out),
	.gpio_in     (gpio_in )
	);

uarts u_uarts_inst (
  .hclk             (hclk),
  .hresetn          (nreset_sync),
  .rx_data          (uarts_rx_data),
  .rx_irq           (uarts_rx_irq),
  .tx_data          (gpcfg_reg[36]),
  .tx_send          (gpcfg_reg[38][0]),
  .tx_irq           (uarts_tx_irq),
  .uarts_baud       (gpcfg_reg[34]),
  .uarts_ctl        (gpcfg_reg[35]),
  .TX               (uarts_tx),
  .RX               (uarts_rx)

);

genvar i;

















    chiplib_mux3 u_uartm_tx_pad_in_mux_inst (.a (uartm_tx),     .b (gpcfg_reg[0][24]), .c (cleq_host_irq),        .s ({gpcfg_reg[0][17], gpcfg_reg[0][16]}), .y (pad_in[3]));
    chiplib_mux3 u_uartm_rx_pad_in_mux_inst (.a (1'b0),         .b (gpcfg_reg[1][24]), .c (1'b0),           .s ({gpcfg_reg[1][17], gpcfg_reg[1][16]}), .y (pad_in[4]));
    chiplib_mux3 u_uarts_tx_pad_in_mux_inst (.a (uarts_tx),     .b (gpcfg_reg[2][24]), .c (cleq_host_irq),        .s ({gpcfg_reg[2][17], gpcfg_reg[2][16]}), .y (pad_in[5]));
    chiplib_mux3 u_uarts_rx_pad_in_mux_inst (.a (1'b0),         .b (gpcfg_reg[3][24]), .c (1'b0),           .s ({gpcfg_reg[3][17], gpcfg_reg[3][16]}), .y (pad_in[6]));
    chiplib_mux3 u_gpio0_pad_in_mux_inst    (.a (gpio_out[0]),  .b (gpcfg_reg[4][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[4][17], gpcfg_reg[4][16]}), .y (pad_in[7]));
    chiplib_mux3 u_gpio1_pad_in_mux_inst    (.a (gpio_out[1]),  .b (gpcfg_reg[5][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[5][17], gpcfg_reg[5][16]}), .y (pad_in[8]));
    chiplib_mux3 u_gpio2_pad_in_mux_inst    (.a (gpio_out[2]),  .b (gpcfg_reg[6][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[6][17], gpcfg_reg[6][16]}), .y (pad_in[9]));
    chiplib_mux3 u_gpio3_pad_in_mux_inst    (.a (gpio_out[3]),  .b (gpcfg_reg[7][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[7][17], gpcfg_reg[7][16]}), .y (pad_in[10]));

    assign pad_ctl[3][1:0]   = (gpcfg_reg[0][20] == 1'b1) ? gpcfg_reg[0][1:0] : ((gpcfg_reg[0][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[0][17:16] == 2'b10) ? 2'b10 : 2'b10));
    assign pad_ctl[4][1:0]   = (gpcfg_reg[1][20] == 1'b1) ? gpcfg_reg[1][1:0] : ((gpcfg_reg[1][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[1][17:16] == 2'b10) ? 2'b11 : 2'b11));
    assign pad_ctl[5][1:0]   = (gpcfg_reg[2][20] == 1'b1) ? gpcfg_reg[2][1:0] : ((gpcfg_reg[2][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[2][17:16] == 2'b10) ? 2'b10 : 2'b11));
    assign pad_ctl[6][1:0]   = (gpcfg_reg[3][20] == 1'b1) ? gpcfg_reg[3][1:0] : ((gpcfg_reg[3][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[3][17:16] == 2'b10) ? 2'b11 : 2'b11));
    assign pad_ctl[7][1:0]   = (gpcfg_reg[4][20] == 1'b1) ? gpcfg_reg[4][1:0] : ((gpcfg_reg[4][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[4][17:16] == 2'b10) ? 2'b10 : 2'b11));
    assign pad_ctl[8][1:0]   = (gpcfg_reg[5][20] == 1'b1) ? gpcfg_reg[5][1:0] : ((gpcfg_reg[5][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[5][17:16] == 2'b10) ? 2'b10 : 2'b11));
    assign pad_ctl[9][1:0]   = (gpcfg_reg[6][20] == 1'b1) ? gpcfg_reg[6][1:0] : ((gpcfg_reg[6][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[6][17:16] == 2'b10) ? 2'b10 : 2'b11));
    assign pad_ctl[10][1:0]  = (gpcfg_reg[7][20] == 1'b1) ? gpcfg_reg[7][1:0] : ((gpcfg_reg[7][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[7][17:16] == 2'b10) ? 2'b10 : 2'b11));

generate
  for (i=3; i<NUM_PADS; i=i+1) begin
    assign pad_ctl[i][PAD_CTL_W-1:2] = gpcfg_reg[i-3][PAD_CTL_W-1:2];
  end
endgenerate


    assign nreset      = pad_out[1]; 

    `ifdef FPGA_SYNTH
       clock_div u_clk_div4_inst ( 
         .CLK_IN1(pad_out[2]),
         .CLK_OUT1(hclk)
       );
    `else
      assign hclk        = pad_out[2]; 
    `endif

    chiplib_mux3 u_uartm_rx_mux_inst (.a (pad_out[4]), .b (1'b1), .c (pad_out[5]),                   .s ({gpcfg_reg[1][17], gpcfg_reg[1][16]}), .y(uartm_rx));
    chiplib_mux4 u_uarts_rx_mux_inst (.a (pad_out[6]), .b (1'b1), .c (pad_out[3]), .d (pad_out[5]),  .s ({gpcfg_reg[3][17], gpcfg_reg[3][16]}), .y(uarts_rx));

    assign gpio_in[0]  = pad_out[7];
    assign gpio_in[1]  = pad_out[8];
    assign gpio_in[2]  = pad_out[9];
    assign gpio_in[3]  = pad_out[10];


 always @ (posedge hclk or negedge nreset) begin
   if (nreset == 1'b0) begin
     nreset_sync0 <= 1'b0;
     nreset_sync1 <= 1'b0;
     nreset_sync2 <= 1'b0;
   end
   else begin
     nreset_sync0 <= 1'b1;
     nreset_sync1 <= nreset_sync0;
     nreset_sync2 <= nreset_sync1;
   end
 end

 assign nreset_sync = nreset_sync2 & nreset_sync1 & nreset_sync0 & nreset;


endmodule
module chip_core #(
  parameter NUM_PADS  = 11,
  parameter PAD_CTL_W = 9
  )(
  output wire [NUM_PADS-1  :3]  pad_in,
  input  wire [NUM_PADS-1  :0]  pad_out,
  output wire [PAD_CTL_W-1 :0]  pad_ctl[NUM_PADS-1   :3]

);







  localparam NUM_MASTERS = 2;
  localparam NUM_SLAVES  = 2;

  localparam SPI_M_ID    = 0;
  localparam UARTM_M_ID  = 1;

  localparam GPCFG_S_ID  = 0;
  localparam GPIO_S_ID   = 1;

  localparam GPCFG_BASE  = 32'h4002_0000;
  localparam GPIO_BASE   = 32'h4003_0000;

  localparam NBITS  = 2048;

wire        hclk;
wire        nreset;

wire        nreset_sync;
reg         nreset_sync0;
reg         nreset_sync1;
reg         nreset_sync2;

wire [1:0]  htrans_m0;
wire [31:0] haddr_m0;
wire [2:0]  hsize_m0;
wire [31:0] hwdata_m0;
wire [31:0] hrdata_m0;
wire [31:0] hrdata_gpcfg;
wire [31:0] hrdata_sram_wrap;

wire [31:0] gpcfg_reg[63:0];

wire [ 1:0] htrans_m[NUM_MASTERS-1 :0];
wire [31:0] haddr_m[NUM_MASTERS-1 :0];
wire [ 2:0] hsize_m[NUM_MASTERS-1 :0];
wire [31:0] hwdata_m[NUM_MASTERS-1 :0];
wire        hwrite_m[NUM_MASTERS-1 :0];
wire [31:0] hrdata_m[NUM_MASTERS-1 :0];
wire        hready_m[NUM_MASTERS-1 :0];
wire        hresp_m[NUM_MASTERS-1 :0];
wire        hsel_s[NUM_SLAVES-1 :0];
wire [31:0] haddr_s[NUM_SLAVES-1 :0];
wire [ 2:0] hsize_s[NUM_SLAVES-1 :0];
wire        hwrite_s[NUM_SLAVES-1 :0];
wire [31:0] hwdata_s[NUM_SLAVES-1 :0];
wire [31:0] hrdata_s[NUM_SLAVES-1 :0];
wire        hready_s[NUM_SLAVES-1 :0];
wire        hresp_s[NUM_SLAVES-1 :0];

wire        gpio_irq;
wire [3:0]  gpio_out;
wire [3:0]  gpio_in;

wire [31:0] uarts_rx_data;

wire enable_p_mod_mul_il;
wire enable_p_mod_exp;
wire enable_p_bin_ext_gcd;
wire done_irq_p_mod_mul_il;
wire done_irq_p_mod_exp;
wire done_irq_p_bin_ext_gcd;
wire [11:0]    maxbits;
wire [2047:0]  arg_a;
wire [2047:0]  arg_b;
wire [2047:0]  modulus;
wire [2047:0]  exp;
wire [2047:0]  r_red_extgcd;
wire [2047:0]  mod_mul_il_y;
wire [2047:0]  mod_exp_y;
wire [2048:0]  x;

wire [2047:0]  gcd;
wire [1023:0]  rng0_y;
wire [1023:0]  rng1_y;



uartm u_uartm_inst (
  .hclk        (hclk),
  .hresetn     (nreset_sync),
  .haddr       (haddr_m[UARTM_M_ID]),
  .hsize       (hsize_m[UARTM_M_ID]),
  .htrans      (htrans_m[UARTM_M_ID]),
  .hwdata      (hwdata_m[UARTM_M_ID]),
  .hwrite      (hwrite_m[UARTM_M_ID]),
  .hrdata      (hrdata_m[UARTM_M_ID]),
  .hready      (hready_m[UARTM_M_ID]),
  .hresp       (hresp_m[UARTM_M_ID]),
  .uartm_baud  (gpcfg_reg[17]),
  .uartm_ctl   (gpcfg_reg[18]),
  .TX          (uartm_tx),
  .RX          (uartm_rx)
);


uartm u_spis_inst (
  .hclk        (hclk),
  .hresetn     (nreset_sync),
  .haddr       (haddr_m[SPI_M_ID]),
  .hsize       (hsize_m[SPI_M_ID]),
  .htrans      (htrans_m[SPI_M_ID]),
  .hwdata      (hwdata_m[SPI_M_ID]),
  .hwrite      (hwrite_m[SPI_M_ID]),
  .hrdata      (hrdata_m[SPI_M_ID]),
  .hready      (hready_m[SPI_M_ID]),
  .hresp       (hresp_m[SPI_M_ID]),
  .uartm_baud  (gpcfg_reg[17]),
  .uartm_ctl   (gpcfg_reg[18]),
  .TX          (),
  .RX          (1'b1)
);




ahb_ic #(
  .NUM_SLAVES  (NUM_SLAVES),
  .NUM_MASTERS (NUM_MASTERS),
  .SLAVE_BASE  ( {GPIO_BASE,
                  GPCFG_BASE})
  ) u_ahb_ic_inst (  
  .hclk      (hclk),
  .hresetn   (nreset_sync),
  .htrans_m  (htrans_m),
  .haddr_m   (haddr_m),
  .hsize_m   (hsize_m),
  .hwdata_m  (hwdata_m),
  .hwrite_m  (hwrite_m),
  .hrdata_m  (hrdata_m),
  .hready_m  (hready_m),
  .hresp_m   (hresp_m),
  .hsel_s    (hsel_s),
  .haddr_s   (haddr_s),
  .hsize_s   (hsize_s),
  .hwrite_s  (hwrite_s),
  .hwdata_s  (hwdata_s),
  .hrdata_s  (hrdata_s),
  .hready_s  (hready_s),
  .hresp_s   (hresp_s)
);




gpcfg   u_gpcfg_inst (
  .hclk                     (hclk),
  .hresetn                  (nreset_sync),
  .hsel                     (hsel_s[GPCFG_S_ID]),
  .haddr                    (haddr_s[GPCFG_S_ID]),
  .hsize                    (hsize_s[GPCFG_S_ID]),
  .hwdata                   (hwdata_s[GPCFG_S_ID]),
  .hwrite                   (hwrite_s[GPCFG_S_ID]),
  .hrdata                   (hrdata_s[GPCFG_S_ID]),
  .hready                   (hready_s[GPCFG_S_ID]),
  .hresp                    (hresp_s[GPCFG_S_ID]),
  .pad03_ctl_reg            (gpcfg_reg[0]),
  .pad04_ctl_reg            (gpcfg_reg[1]),
  .pad05_ctl_reg            (gpcfg_reg[2]),
  .pad06_ctl_reg            (gpcfg_reg[3]),
  .pad07_ctl_reg            (gpcfg_reg[4]),
  .pad08_ctl_reg            (gpcfg_reg[5]),
  .pad09_ctl_reg            (gpcfg_reg[6]),
  .pad10_ctl_reg            (gpcfg_reg[7]),
  .pad11_ctl_reg            (gpcfg_reg[8]),
  .pad12_ctl_reg            (gpcfg_reg[9]),
  .pad13_ctl_reg            (gpcfg_reg[10]),
  .pad14_ctl_reg            (gpcfg_reg[11]),
  .pad15_ctl_reg            (gpcfg_reg[12]),
  .pad16_ctl_reg            (gpcfg_reg[13]),
  .pad17_ctl_reg            (gpcfg_reg[14]),
  .pad18_ctl_reg            (gpcfg_reg[15]),
  .pad19_ctl_reg            (gpcfg_reg[16]),
  .uartm_baud_ctl_reg       (gpcfg_reg[17]),
  .uartm_ctl_reg            (gpcfg_reg[18]),
  .uarts_baud_ctl_reg       (gpcfg_reg[34]),
  .uarts_ctl_reg            (gpcfg_reg[35]),
  .uarts_tx_data_reg        (gpcfg_reg[36]),

  .uarts_rx_data            (uarts_rx_data),
  .uarts_tx_send_reg        (gpcfg_reg[38]),
  .spare0_reg               (gpcfg_reg[39]),
  .spare1_reg               (gpcfg_reg[40]),
  .spare2_reg               (gpcfg_reg[41]),
  .signature_reg            (gpcfg_reg[51]),
  .maxbits                  (maxbits),
  .r_red_extgcd             (r_red_extgcd),
  .arg_a                    (arg_a),
  .arg_b                    (arg_b),
  .exp                      (exp),
  .modulus                        (modulus),
  .x                        (x),
  .gcd                      (gcd),
  .mod_mul_il_y             (mod_mul_il_y),
  .mod_exp_y                (mod_exp_y),
  .rng0_y                   (rng0_y),
  .rng1_y                   (rng1_y),
  .bypass_vn                (bypass_vn),
  .enable_p_mod_mul_il      (enable_p_mod_mul_il),
  .enable_p_mod_exp         (enable_p_mod_exp),
  .enable_p_bin_ext_gcd     (enable_p_bin_ext_gcd),
  .enable_p_rng0            (enable_p_rng0),
  .enable_p_rng1            (enable_p_rng1),
  .cleq_host_irq            (cleq_host_irq),
  .done_irq_p_mod_mul_il    (done_irq_p_mod_mul_il),
  .done_irq_p_mod_exp       (done_irq_p_mod_exp),
  .done_irq_p_bin_ext_gcd   (done_irq_p_bin_ext_gcd),
  .done_irq_p_rng0          (done_irq_p_rng0        ),
  .done_irq_p_rng1          (done_irq_p_rng1        )

);



mod_mul_il #(
  .NBITS (NBITS)
 ) u_mod_mul_il_inst   (
  .clk           (hclk),
  .rst_n         (nreset_sync),
  .enable_p      (enable_p_mod_mul_il),
  .a             (arg_a),
  .b             (arg_b),
  .m             (modulus),
  .y             (mod_mul_il_y),
  .done_irq_p    (done_irq_p_mod_mul_il)
);

mod_exp #(
  .NBITS (NBITS)
 ) u_mod_exp_inst  (
  .clk        (hclk),
  .rst_n      (nreset_sync),
  .enable_p   (enable_p_mod_exp),
  .a          (arg_a),
  .exp        (exp),
  .m          (modulus),
  .m_size     (maxbits),
  .r_red      (r_red_extgcd),
  .y          (mod_exp_y),
  .done_irq_p (done_irq_p_mod_exp)
);

bin_ext_gcd #(
  .NBITS (NBITS)
 ) u_bin_ext_gcd_inst   (
  .clk           (hclk),
  .rst_n         (nreset_sync),
  .enable_p      (enable_p_bin_ext_gcd),
  .x             (arg_a),
  .y             (arg_b),
  .a             (x),
  .b             (),
  .gcd           (gcd),
  .done_irq_p    (done_irq_p_bin_ext_gcd)
);

random_num_gen #(
  .NBITS (NBITS/2) ) u_random_num_gen0_inst (
  .clk            (hclk),
  .rst_n          (nreset_sync),
  .enable_p       (enable_p_rng0),
  .bypass         (bypass_vn),
  .maxbits        (maxbits),
  .done_p         (done_irq_p_rng0),
  .y              (rng0_y)
);

random_num_gen #(
  .NBITS (NBITS/2) ) u_random_num_gen1_inst (
  .clk            (hclk),
  .rst_n          (nreset_sync),
  .enable_p       (enable_p_rng1),
  .bypass         (bypass_vn),
  .maxbits        (maxbits),
  .done_p         (done_irq_p_rng1),
  .y              (rng1_y)
);



gpio u_gpio_inst (
	.hclk        (hclk),
	.hresetn     (nreset_sync),
	.hsel        (hsel_s[GPIO_S_ID]),
	.haddr       (haddr_s[GPIO_S_ID]),
	.hwdata      (hwdata_s[GPIO_S_ID]),
	.hwrite      (hwrite_s[GPIO_S_ID]),
	.hrdata      (hrdata_s[GPIO_S_ID]),
	.hready      (hready_s[GPIO_S_ID]),
	.hresp       (hresp_s[GPIO_S_ID]),
	.intc        (gpio_irq),
	.gpio_out    (gpio_out),
	.gpio_in     (gpio_in )
	);

uarts u_uarts_inst (
  .hclk             (hclk),
  .hresetn          (nreset_sync),
  .rx_data          (uarts_rx_data),
  .rx_irq           (uarts_rx_irq),
  .tx_data          (gpcfg_reg[36]),
  .tx_send          (gpcfg_reg[38][0]),
  .tx_irq           (uarts_tx_irq),
  .uarts_baud       (gpcfg_reg[34]),
  .uarts_ctl        (gpcfg_reg[35]),
  .TX               (uarts_tx),
  .RX               (uarts_rx)

);

genvar i;

















    chiplib_mux3 u_uartm_tx_pad_in_mux_inst (.a (uartm_tx),     .b (gpcfg_reg[0][24]), .c (cleq_host_irq),        .s ({gpcfg_reg[0][17], gpcfg_reg[0][16]}), .y (pad_in[3]));
    chiplib_mux3 u_uartm_rx_pad_in_mux_inst (.a (1'b0),         .b (gpcfg_reg[1][24]), .c (1'b0),           .s ({gpcfg_reg[1][17], gpcfg_reg[1][16]}), .y (pad_in[4]));
    chiplib_mux3 u_uarts_tx_pad_in_mux_inst (.a (uarts_tx),     .b (gpcfg_reg[2][24]), .c (cleq_host_irq),        .s ({gpcfg_reg[2][17], gpcfg_reg[2][16]}), .y (pad_in[5]));
    chiplib_mux3 u_uarts_rx_pad_in_mux_inst (.a (1'b0),         .b (gpcfg_reg[3][24]), .c (1'b0),           .s ({gpcfg_reg[3][17], gpcfg_reg[3][16]}), .y (pad_in[6]));
    chiplib_mux3 u_gpio0_pad_in_mux_inst    (.a (gpio_out[0]),  .b (gpcfg_reg[4][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[4][17], gpcfg_reg[4][16]}), .y (pad_in[7]));
    chiplib_mux3 u_gpio1_pad_in_mux_inst    (.a (gpio_out[1]),  .b (gpcfg_reg[5][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[5][17], gpcfg_reg[5][16]}), .y (pad_in[8]));
    chiplib_mux3 u_gpio2_pad_in_mux_inst    (.a (gpio_out[2]),  .b (gpcfg_reg[6][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[6][17], gpcfg_reg[6][16]}), .y (pad_in[9]));
    chiplib_mux3 u_gpio3_pad_in_mux_inst    (.a (gpio_out[3]),  .b (gpcfg_reg[7][24]), .c (cleq_host_irq),  .s ({gpcfg_reg[7][17], gpcfg_reg[7][16]}), .y (pad_in[10]));

    assign pad_ctl[3][1:0]   = (gpcfg_reg[0][20] == 1'b1) ? gpcfg_reg[0][1:0] : ((gpcfg_reg[0][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[0][17:16] == 2'b10) ? 2'b10 : 2'b10));
    assign pad_ctl[4][1:0]   = (gpcfg_reg[1][20] == 1'b1) ? gpcfg_reg[1][1:0] : ((gpcfg_reg[1][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[1][17:16] == 2'b10) ? 2'b11 : 2'b11));
    assign pad_ctl[5][1:0]   = (gpcfg_reg[2][20] == 1'b1) ? gpcfg_reg[2][1:0] : ((gpcfg_reg[2][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[2][17:16] == 2'b10) ? 2'b10 : 2'b11));
    assign pad_ctl[6][1:0]   = (gpcfg_reg[3][20] == 1'b1) ? gpcfg_reg[3][1:0] : ((gpcfg_reg[3][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[3][17:16] == 2'b10) ? 2'b11 : 2'b11));
    assign pad_ctl[7][1:0]   = (gpcfg_reg[4][20] == 1'b1) ? gpcfg_reg[4][1:0] : ((gpcfg_reg[4][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[4][17:16] == 2'b10) ? 2'b10 : 2'b11));
    assign pad_ctl[8][1:0]   = (gpcfg_reg[5][20] == 1'b1) ? gpcfg_reg[5][1:0] : ((gpcfg_reg[5][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[5][17:16] == 2'b10) ? 2'b10 : 2'b11));
    assign pad_ctl[9][1:0]   = (gpcfg_reg[6][20] == 1'b1) ? gpcfg_reg[6][1:0] : ((gpcfg_reg[6][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[6][17:16] == 2'b10) ? 2'b10 : 2'b11));
    assign pad_ctl[10][1:0]  = (gpcfg_reg[7][20] == 1'b1) ? gpcfg_reg[7][1:0] : ((gpcfg_reg[7][17:16] == 2'b01) ? 2'b10 : ((gpcfg_reg[7][17:16] == 2'b10) ? 2'b10 : 2'b11));

generate
  for (i=3; i<NUM_PADS; i=i+1) begin
    assign pad_ctl[i][PAD_CTL_W-1:2] = gpcfg_reg[i-3][PAD_CTL_W-1:2];
  end
endgenerate


    assign nreset      = pad_out[1]; 

    `ifdef FPGA_SYNTH
       clock_div u_clk_div4_inst ( 
         .CLK_IN1(pad_out[2]),
         .CLK_OUT1(hclk)
       );
    `else
      assign hclk        = pad_out[2]; 
    `endif

    chiplib_mux3 u_uartm_rx_mux_inst (.a (pad_out[4]), .b (1'b1), .c (pad_out[5]),                   .s ({gpcfg_reg[1][17], gpcfg_reg[1][16]}), .y(uartm_rx));
    chiplib_mux4 u_uarts_rx_mux_inst (.a (pad_out[6]), .b (1'b1), .c (pad_out[3]), .d (pad_out[5]),  .s ({gpcfg_reg[3][17], gpcfg_reg[3][16]}), .y(uarts_rx));

    assign gpio_in[0]  = pad_out[7];
    assign gpio_in[1]  = pad_out[8];
    assign gpio_in[2]  = pad_out[9];
    assign gpio_in[3]  = pad_out[10];


 always @ (posedge hclk or negedge nreset) begin
   if (nreset == 1'b0) begin
     nreset_sync0 <= 1'b0;
     nreset_sync1 <= 1'b0;
     nreset_sync2 <= 1'b0;
   end
   else begin
     nreset_sync0 <= 1'b1;
     nreset_sync1 <= nreset_sync0;
     nreset_sync2 <= nreset_sync1;
   end
 end

 assign nreset_sync = nreset_sync2 & nreset_sync1 & nreset_sync0 & nreset;


endmodule