data/full_repos/permissive/16591284/fifo_with_bram/fifo.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:32: Unsupported: Ignoring delay on this delayed statement.\n    forever #(5) CLK = ~CLK;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Error: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:40: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile(VCD);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:41: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, fifo);\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FIFO_RAM #(parameter               WIDTH = 32,
                  parameter               DEPTH = 4,
                  parameter               W_POS = 2)
                 (input  wire             CLK,
                  input  wire             WE,
                  input  wire [W_POS-1:0] RADDR,
                  input  wire [W_POS-1:0] WADDR,
                  input  wire [WIDTH-1:0] DIN,
                  output reg  [WIDTH-1:0] DOUT);
  
  reg [WIDTH-1:0] mem [DEPTH-1:0];
  
  always @(posedge CLK) begin
    if (WE) mem[WADDR] <= DIN;
    DOUT <= mem[RADDR];
  end
endmodule
module FIFO_RAM #(parameter               WIDTH = 32,
                  parameter               DEPTH = 4,
                  parameter               W_POS = 2)
                 (input  wire             CLK,
                  input  wire             WE,
                  input  wire [W_POS-1:0] RADDR,
                  input  wire [W_POS-1:0] WADDR,
                  input  wire [WIDTH-1:0] DIN,
                  output reg  [WIDTH-1:0] DOUT);

  
  reg [WIDTH-1:0] mem [DEPTH-1:0];
  
  always @(posedge CLK) begin
    if (WE) mem[WADDR] <= DIN;
    DOUT <= mem[RADDR];
  end
endmodule