data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v
None: at end of input
1: b'%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:28: Cannot find include file: spio_spinnaker_link.h\n`include "spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.v\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.sv\n             spio_spinnaker_link.h\n             spio_spinnaker_link.h.v\n             spio_spinnaker_link.h.sv\n             obj_dir/spio_spinnaker_link.h\n             obj_dir/spio_spinnaker_link.h.v\n             obj_dir/spio_spinnaker_link.h.sv\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:44: Define or directive not defined: \'`PKT_BITS\'\n  input      [`PKT_BITS - 1:0] PKT_DATA_IN,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:105: Define or directive not defined: \'`PKT_BITS\'\n  input       [`PKT_BITS - 1:0] PKT_DATA_IN,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:129: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] pkt_buf;    \n         ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module flit_output_if
(
  input            CLK_IN,
  input            RESET_IN,


  output reg       ACK_ERR_OUT,
  output reg       TMO_ERR_OUT,


  input      [6:0] flt_data,
  input            flt_vld,
  output reg       flt_rdy,


  output reg [6:0] SL_DATA_2OF7_OUT,
  input            SL_ACK_IN
);




  localparam STATE_BITS = 2;
  localparam IDLE_ST    = 0;
  localparam TRAN_ST    = IDLE_ST + 1;
  localparam WAIT_ST    = TRAN_ST + 1;





  reg old_ack;
  reg acked;

  reg send_flit;

  reg [STATE_BITS - 1:0] state;





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_rdy <= 1'b0;
    else
      case (state)
        IDLE_ST: if (flt_vld)
                   flt_rdy <= 1'b0;
	         else
                   flt_rdy <= 1'b1;

        default: if (acked)
                   flt_rdy <= 1'b1;
	         else
                   flt_rdy <= 1'b0;
      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      SL_DATA_2OF7_OUT <= 7'd0;
    else
      if (send_flit)
        SL_DATA_2OF7_OUT <= flt_data;





  always @(*)
    if (RESET_IN)
      send_flit = 1'b0;
    else
      case (state)
        IDLE_ST: if (flt_vld)
                   send_flit = 1'b1;
                 else
                   send_flit = 1'b0;

        TRAN_ST: if (acked && flt_vld)
                   send_flit = 1'b1;
                 else
                   send_flit = 1'b0;

        default:   send_flit = 1'b0;
      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      old_ack <= 1'b0;
    else
      if (send_flit)
        old_ack <= SL_ACK_IN;





  always @ (*)
    acked = (old_ack != SL_ACK_IN);






  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      ACK_ERR_OUT <= 1'b0;
    else
      ACK_ERR_OUT <= 1'b0;

  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      TMO_ERR_OUT <= 1'b0;
    else
      TMO_ERR_OUT <= 1'b0;





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      state <= IDLE_ST;
    else
      case (state)
        IDLE_ST: if (flt_vld)
                   state <= TRAN_ST;

        TRAN_ST:
          case ({acked, flt_vld})
            2'b10:   state <= IDLE_ST;
	    2'b11:   state <= WAIT_ST;
            default: state <= TRAN_ST;
          endcase

        default: if (acked)
                   state <= IDLE_ST;
                 else
                   state <= TRAN_ST;
      endcase 
endmodule
module flit_output_if
(
  input            CLK_IN,
  input            RESET_IN,


  output reg       ACK_ERR_OUT,
  output reg       TMO_ERR_OUT,


  input      [6:0] flt_data,
  input            flt_vld,
  output reg       flt_rdy,


  output reg [6:0] SL_DATA_2OF7_OUT,
  input            SL_ACK_IN
);





  localparam STATE_BITS = 2;
  localparam IDLE_ST    = 0;
  localparam TRAN_ST    = IDLE_ST + 1;
  localparam WAIT_ST    = TRAN_ST + 1;





  reg old_ack;
  reg acked;

  reg send_flit;

  reg [STATE_BITS - 1:0] state;





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_rdy <= 1'b0;
    else
      case (state)
        IDLE_ST: if (flt_vld)
                   flt_rdy <= 1'b0;
	         else
                   flt_rdy <= 1'b1;

        default: if (acked)
                   flt_rdy <= 1'b1;
	         else
                   flt_rdy <= 1'b0;
      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      SL_DATA_2OF7_OUT <= 7'd0;
    else
      if (send_flit)
        SL_DATA_2OF7_OUT <= flt_data;





  always @(*)
    if (RESET_IN)
      send_flit = 1'b0;
    else
      case (state)
        IDLE_ST: if (flt_vld)
                   send_flit = 1'b1;
                 else
                   send_flit = 1'b0;

        TRAN_ST: if (acked && flt_vld)
                   send_flit = 1'b1;
                 else
                   send_flit = 1'b0;

        default:   send_flit = 1'b0;
      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      old_ack <= 1'b0;
    else
      if (send_flit)
        old_ack <= SL_ACK_IN;





  always @ (*)
    acked = (old_ack != SL_ACK_IN);






  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      ACK_ERR_OUT <= 1'b0;
    else
      ACK_ERR_OUT <= 1'b0;

  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      TMO_ERR_OUT <= 1'b0;
    else
      TMO_ERR_OUT <= 1'b0;





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      state <= IDLE_ST;
    else
      case (state)
        IDLE_ST: if (flt_vld)
                   state <= TRAN_ST;

        TRAN_ST:
          case ({acked, flt_vld})
            2'b10:   state <= IDLE_ST;
	    2'b11:   state <= WAIT_ST;
            default: state <= TRAN_ST;
          endcase

        default: if (acked)
                   state <= IDLE_ST;
                 else
                   state <= TRAN_ST;
      endcase 
endmodule