data/full_repos/permissive/106029354/verilog_source/pipeline1.v
1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline1.v:11: Cannot find include file: params_proc.v\n`include "params_proc.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n             params_proc.v\n             params_proc.v.v\n             params_proc.v.sv\n             obj_dir/params_proc.v\n             obj_dir/params_proc.v.v\n             obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n'
module pipeline1(
    clk_in,
    RST,
    pc_chg,
    pc_in,
    instr,
    pc_out
);


`include "params_proc.v"



input clk_in, RST, pc_chg;
input [PC_WIDTH-1:0] pc_in;



output [INSTR_WIDTH-1:0] instr;
output [PC_WIDTH-1:0] pc_out;


reg [PC_WIDTH-1:0] new_pc;
wire we, clk_neg;
wire [INSTR_WIDTH-1:0] data;



mem_program rom0(.clk(clk_neg), .we(we), .addr(new_pc), .data_in(data), .data_out(instr));

assign we   = 0;
assign data = 0;
assign clk_neg = ~clk_in;

assign pc_out = new_pc + 1;


always @(posedge clk_in) begin
    if (!RST) begin
        new_pc <= PC_INITIAL;		
    end else if (pc_chg) begin
        new_pc <= pc_in;
    end else begin
        new_pc <= new_pc + 1;
    end
end


endmodule
module pipeline1(
    clk_in,
    RST,
    pc_chg,
    pc_in,
    instr,
    pc_out
);



`include "params_proc.v"



input clk_in, RST, pc_chg;
input [PC_WIDTH-1:0] pc_in;



output [INSTR_WIDTH-1:0] instr;
output [PC_WIDTH-1:0] pc_out;


reg [PC_WIDTH-1:0] new_pc;
wire we, clk_neg;
wire [INSTR_WIDTH-1:0] data;



mem_program rom0(.clk(clk_neg), .we(we), .addr(new_pc), .data_in(data), .data_out(instr));

assign we   = 0;
assign data = 0;
assign clk_neg = ~clk_in;

assign pc_out = new_pc + 1;


always @(posedge clk_in) begin
    if (!RST) begin
        new_pc <= PC_INITIAL;		
    end else if (pc_chg) begin
        new_pc <= pc_in;
    end else begin
        new_pc <= new_pc + 1;
    end
end


endmodule