data/full_repos/permissive/201488448/3_verification/1_sim/06_comb1.v
data/verilator_xmls/fdbf53bc-4f67-4cee-a66b-2e2836554c75.xml
module top_module (
	input a, 
	input b, 
	output q
);



	assign q = a & b;
	
endmodule
module top_module (
	input a, 
	input b, 
	output q
);




	assign q = a & b;
	
endmodule