data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v
 line:98: before: "$"
1: b'%Error: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:27: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("jeff-74x181-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:28: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, jeff_74x181_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0001; A = 4\'b1110; B= 4\'b0110;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0010; A = 4\'b0111; B= 4\'b1001;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0011; A = 4\'b1010; B= 4\'b0011;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0100; A = 4\'b0100; B= 4\'b1100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0101; A = 4\'b0000; B= 4\'b1011;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0110; A = 4\'b0101; B= 4\'b1000;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0111; A = 4\'b1001; B= 4\'b0111;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1000; A = 4\'b0110; B= 4\'b1000;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1001; A = 4\'b0101; B= 4\'b1000;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1010; A = 4\'b1111; B= 4\'b1100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1011; A = 4\'b0011; B= 4\'b0101;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1100; A = 4\'b0011; B= 4\'b0100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1101; A = 4\'b0001; B= 4\'b0110;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1110; A = 4\'b0010; B= 4\'b0001;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1111; A = 4\'b0010; B= 4\'b1010;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0001; A = 4\'b0011; B= 4\'b0110;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0010; A = 4\'b0011; B= 4\'b1001;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0011; A = 4\'b1000; B= 4\'b0100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0100; A = 4\'b0011; B= 4\'b1100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0101; A = 4\'b0011; B= 4\'b1100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0110; A = 4\'b1011; B= 4\'b0111;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0111; A = 4\'b0111; B= 4\'b1011;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1000; A = 4\'b0011; B= 4\'b0010;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1001; A = 4\'b0011; B= 4\'b0011;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1010; A = 4\'b0010; B= 4\'b0010;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1011; A = 4\'b1000; B= 4\'b1000;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1100; A = 4\'b0011; B= 4\'b0011;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1101; A = 4\'b0100; B= 4\'b0100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1110; A = 4\'b0101; B= 4\'b1110;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1111; A = 4\'b1111; B= 4\'b0101;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0001; A = 4\'b0011; B= 4\'b0110;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0010; A = 4\'b0011; B= 4\'b1001;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0011; A = 4\'b1000; B= 4\'b0100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0100; A = 4\'b0011; B= 4\'b1100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0101; A = 4\'b0011; B= 4\'b1100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0110; A = 4\'b1011; B= 4\'b0111;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b0111; A = 4\'b0111; B= 4\'b1011;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1000; A = 4\'b0011; B= 4\'b0010;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1001; A = 4\'b0011; B= 4\'b0011;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1010; A = 4\'b0010; B= 4\'b0010;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1011; A = 4\'b1000; B= 4\'b1000;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1100; A = 4\'b0011; B= 4\'b0011;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1101; A = 4\'b0100; B= 4\'b0100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1110; A = 4\'b0101; B= 4\'b1110;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #20;  S = 4\'b1111; A = 4\'b1111; B= 4\'b0101;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/alus/jeff-74x181/jeff-74x181-tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Error: Exiting due to 2 error(s), 48 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module jeff_74x181_tb;


reg  [3:0]  A, B, S;
reg         M, CI_BAR;
wire [3:0]  F;
wire        CO_BAR, AEQB, X, Y;


jeff_74x181 uut(
    .a3(A[3]), .a2(A[2]), .a1(A[1]), .a0(A[0]),
    .b3(B[3]), .b2(B[2]), .b1(B[1]), .b0(B[0]),
    .s3(S[3]), .s2(S[2]), .s1(S[1]), .s0(S[0]),
    .m(M), .ci_bar(CI_BAR),
    .f3(F[3]), .f2(F[2]), .f1(F[1]), .f0(F[0]),
    .co_bar(CO_BAR), .aeqb(AEQB), .x(X), .y(Y)
);


initial begin
    $dumpfile("jeff-74x181-tb.vcd");
    $dumpvars(0, jeff_74x181_tb);
end


initial begin
    $display("test start");



          M = 1'b1; CI_BAR = 1'b0;
          S = 4'b0000; A = 4'b1011; B= 4'b0100;
    #20;  S = 4'b0001; A = 4'b1110; B= 4'b0110;
    #20;  S = 4'b0010; A = 4'b0111; B= 4'b1001;
    #20;  S = 4'b0011; A = 4'b1010; B= 4'b0011;
    #20;  S = 4'b0100; A = 4'b0100; B= 4'b1100;
    #20;  S = 4'b0101; A = 4'b0000; B= 4'b1011;
    #20;  S = 4'b0110; A = 4'b0101; B= 4'b1000;
    #20;  S = 4'b0111; A = 4'b1001; B= 4'b0111;
    #20;  S = 4'b1000; A = 4'b0110; B= 4'b1000;
    #20;  S = 4'b1001; A = 4'b0101; B= 4'b1000;
    #20;  S = 4'b1010; A = 4'b1111; B= 4'b1100;
    #20;  S = 4'b1011; A = 4'b0011; B= 4'b0101;
    #20;  S = 4'b1100; A = 4'b0011; B= 4'b0100;
    #20;  S = 4'b1101; A = 4'b0001; B= 4'b0110;
    #20;  S = 4'b1110; A = 4'b0010; B= 4'b0001;
    #20;  S = 4'b1111; A = 4'b0010; B= 4'b1010;
    #20



          M = 1'b0; CI_BAR = 1'b1;
          S = 4'b0000; A = 4'b1001; B= 4'b0100;
    #20;  S = 4'b0001; A = 4'b0011; B= 4'b0110;
    #20;  S = 4'b0010; A = 4'b0011; B= 4'b1001;
    #20;  S = 4'b0011; A = 4'b1000; B= 4'b0100;
    #20;  S = 4'b0100; A = 4'b0011; B= 4'b1100;
    #20;  S = 4'b0101; A = 4'b0011; B= 4'b1100;
    #20;  S = 4'b0110; A = 4'b1011; B= 4'b0111;
    #20;  S = 4'b0111; A = 4'b0111; B= 4'b1011;
    #20;  S = 4'b1000; A = 4'b0011; B= 4'b0010;
    #20;  S = 4'b1001; A = 4'b0011; B= 4'b0011;
    #20;  S = 4'b1010; A = 4'b0010; B= 4'b0010;
    #20;  S = 4'b1011; A = 4'b1000; B= 4'b1000;
    #20;  S = 4'b1100; A = 4'b0011; B= 4'b0011;
    #20;  S = 4'b1101; A = 4'b0100; B= 4'b0100;
    #20;  S = 4'b1110; A = 4'b0101; B= 4'b1110;
    #20;  S = 4'b1111; A = 4'b1111; B= 4'b0101;
    #20



          M = 1'b0; CI_BAR = 1'b0;
          S = 4'b0000; A = 4'b1001; B= 4'b0100;
    #20;  S = 4'b0001; A = 4'b0011; B= 4'b0110;
    #20;  S = 4'b0010; A = 4'b0011; B= 4'b1001;
    #20;  S = 4'b0011; A = 4'b1000; B= 4'b0100;
    #20;  S = 4'b0100; A = 4'b0011; B= 4'b1100;
    #20;  S = 4'b0101; A = 4'b0011; B= 4'b1100;
    #20;  S = 4'b0110; A = 4'b1011; B= 4'b0111;
    #20;  S = 4'b0111; A = 4'b0111; B= 4'b1011;
    #20;  S = 4'b1000; A = 4'b0011; B= 4'b0010;
    #20;  S = 4'b1001; A = 4'b0011; B= 4'b0011;
    #20;  S = 4'b1010; A = 4'b0010; B= 4'b0010;
    #20;  S = 4'b1011; A = 4'b1000; B= 4'b1000;
    #20;  S = 4'b1100; A = 4'b0011; B= 4'b0011;
    #20;  S = 4'b1101; A = 4'b0100; B= 4'b0100;
    #20;  S = 4'b1110; A = 4'b0101; B= 4'b1110;
    #20;  S = 4'b1111; A = 4'b1111; B= 4'b0101;
    #20

    $display("test complete");
    $finish;
end

endmodule
module jeff_74x181_tb;



reg  [3:0]  A, B, S;
reg         M, CI_BAR;
wire [3:0]  F;
wire        CO_BAR, AEQB, X, Y;


jeff_74x181 uut(
    .a3(A[3]), .a2(A[2]), .a1(A[1]), .a0(A[0]),
    .b3(B[3]), .b2(B[2]), .b1(B[1]), .b0(B[0]),
    .s3(S[3]), .s2(S[2]), .s1(S[1]), .s0(S[0]),
    .m(M), .ci_bar(CI_BAR),
    .f3(F[3]), .f2(F[2]), .f1(F[1]), .f0(F[0]),
    .co_bar(CO_BAR), .aeqb(AEQB), .x(X), .y(Y)
);


initial begin
    $dumpfile("jeff-74x181-tb.vcd");
    $dumpvars(0, jeff_74x181_tb);
end


initial begin
    $display("test start");



          M = 1'b1; CI_BAR = 1'b0;
          S = 4'b0000; A = 4'b1011; B= 4'b0100;
    #20;  S = 4'b0001; A = 4'b1110; B= 4'b0110;
    #20;  S = 4'b0010; A = 4'b0111; B= 4'b1001;
    #20;  S = 4'b0011; A = 4'b1010; B= 4'b0011;
    #20;  S = 4'b0100; A = 4'b0100; B= 4'b1100;
    #20;  S = 4'b0101; A = 4'b0000; B= 4'b1011;
    #20;  S = 4'b0110; A = 4'b0101; B= 4'b1000;
    #20;  S = 4'b0111; A = 4'b1001; B= 4'b0111;
    #20;  S = 4'b1000; A = 4'b0110; B= 4'b1000;
    #20;  S = 4'b1001; A = 4'b0101; B= 4'b1000;
    #20;  S = 4'b1010; A = 4'b1111; B= 4'b1100;
    #20;  S = 4'b1011; A = 4'b0011; B= 4'b0101;
    #20;  S = 4'b1100; A = 4'b0011; B= 4'b0100;
    #20;  S = 4'b1101; A = 4'b0001; B= 4'b0110;
    #20;  S = 4'b1110; A = 4'b0010; B= 4'b0001;
    #20;  S = 4'b1111; A = 4'b0010; B= 4'b1010;
    #20



          M = 1'b0; CI_BAR = 1'b1;
          S = 4'b0000; A = 4'b1001; B= 4'b0100;
    #20;  S = 4'b0001; A = 4'b0011; B= 4'b0110;
    #20;  S = 4'b0010; A = 4'b0011; B= 4'b1001;
    #20;  S = 4'b0011; A = 4'b1000; B= 4'b0100;
    #20;  S = 4'b0100; A = 4'b0011; B= 4'b1100;
    #20;  S = 4'b0101; A = 4'b0011; B= 4'b1100;
    #20;  S = 4'b0110; A = 4'b1011; B= 4'b0111;
    #20;  S = 4'b0111; A = 4'b0111; B= 4'b1011;
    #20;  S = 4'b1000; A = 4'b0011; B= 4'b0010;
    #20;  S = 4'b1001; A = 4'b0011; B= 4'b0011;
    #20;  S = 4'b1010; A = 4'b0010; B= 4'b0010;
    #20;  S = 4'b1011; A = 4'b1000; B= 4'b1000;
    #20;  S = 4'b1100; A = 4'b0011; B= 4'b0011;
    #20;  S = 4'b1101; A = 4'b0100; B= 4'b0100;
    #20;  S = 4'b1110; A = 4'b0101; B= 4'b1110;
    #20;  S = 4'b1111; A = 4'b1111; B= 4'b0101;
    #20



          M = 1'b0; CI_BAR = 1'b0;
          S = 4'b0000; A = 4'b1001; B= 4'b0100;
    #20;  S = 4'b0001; A = 4'b0011; B= 4'b0110;
    #20;  S = 4'b0010; A = 4'b0011; B= 4'b1001;
    #20;  S = 4'b0011; A = 4'b1000; B= 4'b0100;
    #20;  S = 4'b0100; A = 4'b0011; B= 4'b1100;
    #20;  S = 4'b0101; A = 4'b0011; B= 4'b1100;
    #20;  S = 4'b0110; A = 4'b1011; B= 4'b0111;
    #20;  S = 4'b0111; A = 4'b0111; B= 4'b1011;
    #20;  S = 4'b1000; A = 4'b0011; B= 4'b0010;
    #20;  S = 4'b1001; A = 4'b0011; B= 4'b0011;
    #20;  S = 4'b1010; A = 4'b0010; B= 4'b0010;
    #20;  S = 4'b1011; A = 4'b1000; B= 4'b1000;
    #20;  S = 4'b1100; A = 4'b0011; B= 4'b0011;
    #20;  S = 4'b1101; A = 4'b0100; B= 4'b0100;
    #20;  S = 4'b1110; A = 4'b0101; B= 4'b1110;
    #20;  S = 4'b1111; A = 4'b1111; B= 4'b0101;
    #20

    $display("test complete");
    $finish;
end

endmodule