data/full_repos/permissive/162874044/HDL Files/vsync.v
 line:25: before: "("
1: b'%Error: Cannot find file containing module: Files,data/full_repos/permissive/162874044\n        ... Looked in:\n             data/full_repos/permissive/162874044/HDL/Files,data/full_repos/permissive/162874044\n             data/full_repos/permissive/162874044/HDL/Files,data/full_repos/permissive/162874044.v\n             data/full_repos/permissive/162874044/HDL/Files,data/full_repos/permissive/162874044.sv\n             Files,data/full_repos/permissive/162874044\n             Files,data/full_repos/permissive/162874044.v\n             Files,data/full_repos/permissive/162874044.sv\n             obj_dir/Files,data/full_repos/permissive/162874044\n             obj_dir/Files,data/full_repos/permissive/162874044.v\n             obj_dir/Files,data/full_repos/permissive/162874044.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/162874044/HDL\n%Error: Cannot find file containing module: Files/vsync.v\n%Error: Exiting due to 3 error(s)\n'
module vsync #( 
	parameter busWidth = 11, 
	parameter [ ( busWidth - 1 ) : 0 ] resVertical = 1080
)
(


	input							hSync,
	output 							vSyncPulse

);


	reg pulseReg = 1'b0;
	reg [ ( busWidth - 1 ) : 0 ] vCounter = 1'b0;


	

	assign vSyncPulse = pulseReg;

	
	always @( posedge(hSync) )
	begin

		if( vCounter == resVertical)
			begin

				pulseReg = 1'b1;

				vCounter = 0;
			end
		else
			begin

				pulseReg = 1'b0;

				vCounter = vCounter + 1'b1;

			end
	end
	
endmodule
module vsync #( 
	parameter busWidth = 11, 
	parameter [ ( busWidth - 1 ) : 0 ] resVertical = 1080
)
(


	input							hSync,
	output 							vSyncPulse

);



	reg pulseReg = 1'b0;
	reg [ ( busWidth - 1 ) : 0 ] vCounter = 1'b0;


	

	assign vSyncPulse = pulseReg;

	
	always @( posedge(hSync) )
	begin

		if( vCounter == resVertical)
			begin

				pulseReg = 1'b1;

				vCounter = 0;
			end
		else
			begin

				pulseReg = 1'b0;

				vCounter = vCounter + 1'b1;

			end
	end
	
endmodule