data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v
 line:21: before: "("
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:11: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("multiplexer.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:12: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:21: Unsupported: Ignoring delay on this delayed statement.\n    repeat(2) #250 CLK_1MHz = ~CLK_1MHz;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #500\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:24: Unsupported: Ignoring delay on this delayed statement.\n    forever #250 CLK_1MHz = ~CLK_1MHz;\n            ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:28: syntax error, unexpected \'@\'\n    @(posedge ENB)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:107: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:120: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:169: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:182: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:195: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:208: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:221: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:234: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:247: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:259: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:271: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:296: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:309: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:322: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:335: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:348: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:361: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:374: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:386: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:398: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:423: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:436: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:449: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:462: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:475: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:488: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:501: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:513: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:525: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/multiplexer/tester.v:538: Unsupported: Ignoring delay on this delayed statement.\n    #1000 $finish;\n    ^\n%Error: Exiting due to 3 error(s), 40 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester(      output reg  [7:0]   IN_COM, IN_PAD, IN_SKP, IN_STP, IN_SDP, IN_END, IN_EDB, IN_FTS, IN_IDL, IN_TLP,
                    output reg          CLK_1MHz,
                    output reg  [3:0]   IN_CTRL,
                    output reg          ENB,
                    output reg          reset
                    );

  initial begin
    $dumpfile("multiplexer.vcd");
    $dumpvars;
  end

  initial begin
    CLK_1MHz = 1'b0;
    ENB = 1'b0;
    reset = 1'b0;

    #500
    repeat(2) #250 CLK_1MHz = ~CLK_1MHz;
    ENB = 1'b1;
    reset = 1'b1;
    forever #250 CLK_1MHz = ~CLK_1MHz;
  end

  initial begin
    @(posedge ENB)

    IN_CTRL = 0;
    IN_TLP = 8'hFF;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 1;
    IN_TLP = 8'h0A;
    IN_COM = 8'hF2;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 2;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'hC7;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 3;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'hAC;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 4;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'hAA;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 5;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'hE5;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 6;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'hF6;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 7;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'hDF;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 8;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'hA8;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 9;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'hAE;

    IN_CTRL = 0;
    IN_TLP = 8'hFF;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 1;
    IN_TLP = 8'h0A;
    IN_COM = 8'hF2;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 2;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'hC7;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 3;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'hAC;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 4;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'hAA;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 5;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'hE5;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 6;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'hF6;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 7;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'hDF;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 8;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'hA8;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 9;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'hAE;

    IN_CTRL = 0;
    IN_TLP = 8'hFF;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 1;
    IN_TLP = 8'h0A;
    IN_COM = 8'hF2;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 2;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'hC7;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 3;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'hAC;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 4;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'hAA;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 5;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'hE5;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 6;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'hF6;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 7;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'hDF;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 8;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'hA8;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 9;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'hAE;

    IN_CTRL = 0;
    IN_TLP = 8'hFF;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 1;
    IN_TLP = 8'h0A;
    IN_COM = 8'hF2;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 2;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'hC7;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 3;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'hAC;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 4;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'hAA;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 5;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'hE5;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 6;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'hF6;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 7;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'hDF;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 8;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'hA8;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 9;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'hAE;

    #1000 $finish;
  end

endmodule
module tester(      output reg  [7:0]   IN_COM, IN_PAD, IN_SKP, IN_STP, IN_SDP, IN_END, IN_EDB, IN_FTS, IN_IDL, IN_TLP,
                    output reg          CLK_1MHz,
                    output reg  [3:0]   IN_CTRL,
                    output reg          ENB,
                    output reg          reset
                    );


  initial begin
    $dumpfile("multiplexer.vcd");
    $dumpvars;
  end

  initial begin
    CLK_1MHz = 1'b0;
    ENB = 1'b0;
    reset = 1'b0;

    #500
    repeat(2) #250 CLK_1MHz = ~CLK_1MHz;
    ENB = 1'b1;
    reset = 1'b1;
    forever #250 CLK_1MHz = ~CLK_1MHz;
  end

  initial begin
    @(posedge ENB)

    IN_CTRL = 0;
    IN_TLP = 8'hFF;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 1;
    IN_TLP = 8'h0A;
    IN_COM = 8'hF2;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 2;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'hC7;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 3;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'hAC;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 4;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'hAA;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 5;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'hE5;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 6;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'hF6;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 7;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'hDF;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 8;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'hA8;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 9;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'hAE;

    IN_CTRL = 0;
    IN_TLP = 8'hFF;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 1;
    IN_TLP = 8'h0A;
    IN_COM = 8'hF2;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 2;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'hC7;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 3;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'hAC;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 4;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'hAA;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 5;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'hE5;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 6;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'hF6;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 7;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'hDF;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 8;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'hA8;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 9;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'hAE;

    IN_CTRL = 0;
    IN_TLP = 8'hFF;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 1;
    IN_TLP = 8'h0A;
    IN_COM = 8'hF2;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 2;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'hC7;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 3;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'hAC;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 4;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'hAA;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 5;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'hE5;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 6;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'hF6;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 7;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'hDF;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 8;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'hA8;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 9;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'hAE;

    IN_CTRL = 0;
    IN_TLP = 8'hFF;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 1;
    IN_TLP = 8'h0A;
    IN_COM = 8'hF2;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 2;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'hC7;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 3;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'hAC;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 4;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'hAA;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 5;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'hE5;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 6;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'hF6;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;

    #1000
    IN_CTRL = 7;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'hDF;
    IN_FTS = 8'h0A;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 8;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'hA8;
    IN_IDL = 8'h0A;
    #1000
    IN_CTRL = 9;
    IN_TLP = 8'h0A;
    IN_COM = 8'h0A;
    IN_PAD = 8'h0A;
    IN_SKP = 8'h0A;
    IN_STP = 8'h0A;
    IN_SDP = 8'h0A;
    IN_END = 8'h0A;
    IN_EDB = 8'h0A;
    IN_FTS = 8'h0A;
    IN_IDL = 8'hAE;

    #1000 $finish;
  end

endmodule