data/full_repos/permissive/19572582/Lab2/lab2_part7.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:60: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] SSD;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:21: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] HEX1, HEX0;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:31: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 60;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:34: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 50;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:37: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 40;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:40: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 30;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:43: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 20;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:46: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 10;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:49: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0];\n           ^\n%Error: Exiting due to 9 warning(s)\n'
module b2d_7seg (X, SSD);
  input [3:0] X;
  output [0:6] SSD;

  assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] & ~X[1] & ~X[0]));
  assign SSD[1] = ((~X[3] &  X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] &  X[1] & ~X[0]));
  assign SSD[2] =  (~X[3] & ~X[2] &  X[1] & ~X[0]);
  assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] & ~X[1] & ~X[0]) | (~X[3] &  X[2] & X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]));
  assign SSD[4] = ~((~X[2] & ~X[0]) | (X[1] & ~X[0]));
  assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] & ~X[2] &  X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
  assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] &  X[2] & X[1] & X[0]));
endmodule
module b2d_7seg (X, SSD);

  input [3:0] X;
  output [0:6] SSD;

  assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] & ~X[1] & ~X[0]));
  assign SSD[1] = ((~X[3] &  X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] &  X[1] & ~X[0]));
  assign SSD[2] =  (~X[3] & ~X[2] &  X[1] & ~X[0]);
  assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] & ~X[1] & ~X[0]) | (~X[3] &  X[2] & X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]));
  assign SSD[4] = ~((~X[2] & ~X[0]) | (X[1] & ~X[0]));
  assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] & ~X[2] &  X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
  assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] &  X[2] & X[1] & X[0]));
endmodule