data/full_repos/permissive/146618947/basic_example_tarea1/trace.v
 line:16: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/146618947/basic_example_tarea1/trace.v:9: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/146618947/basic_example_tarea1/trace.v:14: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("trace.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/basic_example_tarea1/trace.v:15: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, trace);  \n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/146618947/basic_example_tarea1/trace.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #10 $finish;\n      ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trace ;

   reg       clk = 0;
   reg [3:0] a = 4'd0;
   reg       b = 0;

   always #1 clk = ~clk;
   always @(posedge clk) begin
      a = a+1; b = a[2]; end

   initial begin
      $dumpfile("trace.vcd");
      $dumpvars(0, trace);
      #10 $finish;

   end endmodule
module trace ;


   reg       clk = 0;
   reg [3:0] a = 4'd0;
   reg       b = 0;

   always #1 clk = ~clk;
   always @(posedge clk) begin
      a = a+1; b = a[2]; end

   initial begin
      $dumpfile("trace.vcd");
      $dumpvars(0, trace);
      #10 $finish;

   end endmodule