data/full_repos/permissive/1840016/lab5/testbench.v
 line:28: before: "assign"
1: b'%Warning-STMTDLY: data/full_repos/permissive/1840016/lab5/testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #100 clk =~clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/1840016/lab5/testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #20 assign reset= 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/1840016/lab5/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #100 assign reset = 1\'b0;\n      ^\n%Error: data/full_repos/permissive/1840016/lab5/testbench.v:32: Cannot find file containing module: \'mips_pipeline\'\n   mips_pipeline A1(clk, reset);\n   ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/1840016/lab5,data/full_repos/permissive/1840016/mips_pipeline\n             data/full_repos/permissive/1840016/lab5,data/full_repos/permissive/1840016/mips_pipeline.v\n             data/full_repos/permissive/1840016/lab5,data/full_repos/permissive/1840016/mips_pipeline.sv\n             mips_pipeline\n             mips_pipeline.v\n             mips_pipeline.sv\n             obj_dir/mips_pipeline\n             obj_dir/mips_pipeline.v\n             obj_dir/mips_pipeline.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    
   reg clk, reset;
   
   always
      #100 clk =~clk;
      
   initial begin
      clk = 1'b0;
      reset = 1'b0;
      #20 assign reset= 1'b1;
      #100 assign reset = 1'b0;
   end
   
   mips_pipeline A1(clk, reset);
   



      
endmodule
module testbench;

    
   reg clk, reset;
   
   always
      #100 clk =~clk;
      
   initial begin
      clk = 1'b0;
      reset = 1'b0;
      #20 assign reset= 1'b1;
      #100 assign reset = 1'b0;
   end
   
   mips_pipeline A1(clk, reset);
   



      
endmodule