data/full_repos/permissive/126791278/assets/registerFile_backup.v
1: b'%Warning-WIDTH: data/full_repos/permissive/126791278/assets/registerFile_backup.v:97: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'bzzzz\' generates 4 bits.\n                                                                                    : ... In instance registerFile.mux2\n   default: out<=4\'bzzzz;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/126791278/assets/registerFile_backup.v:64: Output port connection \'out\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'read_data1\' generates 16 bits.\n                                                                                    : ... In instance registerFile\n mux16to1 mux1 (read_data1, reg_out, read_reg1);\n                ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/126791278/assets/registerFile_backup.v:65: Output port connection \'out\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'read_data2\' generates 16 bits.\n                                                                                    : ... In instance registerFile\n mux16to1 mux2 (read_data2, reg_out, read_reg2);\n                ^~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/126791278/assets/registerFile_backup.v:143: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'out\'\n                                                                                         : ... In instance registerFile.deco\n   default: out<=16\'b0000_0000_0000_0000;\n            ^~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module decoder4to16 (out, in);
	
	output [15:0] out;
	input [3:0] in;

	always @(in)
	begin
		case(in)
			4'b0000: out[0]<=1'b1;
			4'b0001: out[1]<=1'b1;
			4'b0010: out[2]<=1'b1;
			4'b0011: out[3]<=1'b1;
			4'b0100: out[4]<=1'b1;
			4'b0101: out[5]<=1'b1;
			4'b0110: out[6]<=1'b1;
			4'b0111: out[7]<=1'b1;
			4'b1000: out[8]<=1'b1;
			4'b1001: out[9]<=1'b1;
			4'b1010: out[10]<=1'b1;
			4'b1011: out[11]<=1'b1;
			4'b1100: out[12]<=1'b1;
			4'b1101: out[13]<=1'b1;
			4'b1110: out[14]<=1'b1;
			4'b1111: out[15]<=1'b1;
			default: out<=16'b0000_0000_0000_0000;
		endcase
	end

endmodule
module decoder4to16 (out, in);

	
	output [15:0] out;
	input [3:0] in;

	always @(in)
	begin
		case(in)
			4'b0000: out[0]<=1'b1;
			4'b0001: out[1]<=1'b1;
			4'b0010: out[2]<=1'b1;
			4'b0011: out[3]<=1'b1;
			4'b0100: out[4]<=1'b1;
			4'b0101: out[5]<=1'b1;
			4'b0110: out[6]<=1'b1;
			4'b0111: out[7]<=1'b1;
			4'b1000: out[8]<=1'b1;
			4'b1001: out[9]<=1'b1;
			4'b1010: out[10]<=1'b1;
			4'b1011: out[11]<=1'b1;
			4'b1100: out[12]<=1'b1;
			4'b1101: out[13]<=1'b1;
			4'b1110: out[14]<=1'b1;
			4'b1111: out[15]<=1'b1;
			default: out<=16'b0000_0000_0000_0000;
		endcase
	end

endmodule