data/full_repos/permissive/181082280/lab_2/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 0; d = 0;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 1; d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 0; d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 1; d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 0; d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 1; d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 0; d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 1; d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 1; d = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 0; d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 0; d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 1; d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 1; d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 0; d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 0; d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 1; d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 1; d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_2/tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        # 20;\n        ^\n%Error: data/full_repos/permissive/181082280/lab_2/tb.v:41: Unsupported or unknown PLI call: $monitor\n        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/181082280/lab_2/tb.v:45: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;   \n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;


    reg  clk, d;
    wire q;




    d_flip_flop dut (clk, d, q);


    initial begin
        # 20;   clk = 0; d = 0;
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 0;
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0; 
        # 10;   clk = 0; d = 0;
        # 10;   clk = 0; d = 0;
        # 10;   clk = 1; d = 0;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0;
        # 20;
    end



    initial 
        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);


    initial 
        $dumpvars;

endmodule
module tb;



    reg  clk, d;
    wire q;




    d_flip_flop dut (clk, d, q);


    initial begin
        # 20;   clk = 0; d = 0;
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 0;
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0; 
        # 10;   clk = 0; d = 0;
        # 10;   clk = 0; d = 0;
        # 10;   clk = 1; d = 0;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0;
        # 20;
    end



    initial 
        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);


    initial 
        $dumpvars;

endmodule