data/full_repos/permissive/146618947/valid_tarea6/mux_41_estructural.v
 line:38: before: "*"
data/verilator_xmls/4c622534-7f2d-42c7-8056-e8a22983fafa.xml
module mux_41_estructural(clk, reset_L, data_0, data_1, data_2, data_3, valid_0, valid_1, valid_2, valid_3, data_out, valid_out);
  (* src = "mux_41.v:5" *)
  input clk;
  (* src = "mux_41.v:7" *)
  input [3:0] data_0;
  (* src = "mux_41.v:8" *)
  input [3:0] data_1;
  (* src = "mux_41.v:9" *)
  input [3:0] data_2;
  (* src = "mux_41.v:10" *)
  input [3:0] data_3;
  (* src = "mux_41.v:15" *)
  output [3:0] data_out;
  (* src = "mux_41.v:19" *)
  wire [3:0] from_muxA_to_muxC;
  (* src = "mux_41.v:20" *)
  wire [3:0] from_muxB_to_muxC;
  (* src = "mux_41.v:6" *)
  input reset_L;
  (* src = "mux_41.v:11" *)
  input valid_0;
  (* src = "mux_41.v:21" *)
  wire valid_0_muxC;
  (* src = "mux_41.v:12" *)
  input valid_1;
  (* src = "mux_41.v:22" *)
  wire valid_1_muxC;
  (* src = "mux_41.v:13" *)
  input valid_2;
  (* src = "mux_41.v:14" *)
  input valid_3;
  (* src = "mux_41.v:16" *)
  output valid_out;
  (* src = "mux_41.v:24" *)
  mux_estructural muxA (
    .clk(clk),
    .data_0(data_0),
    .data_1(data_1),
    .data_out(from_muxA_to_muxC),
    .reset_L(reset_L),
    .valid_0(valid_0),
    .valid_1(valid_1),
    .valid_out(valid_0_muxC)
  );
  (* src = "mux_41.v:25" *)
  mux_estructural muxB (
    .clk(clk),
    .data_0(data_2),
    .data_1(data_3),
    .data_out(from_muxB_to_muxC),
    .reset_L(reset_L),
    .valid_0(valid_2),
    .valid_1(valid_3),
    .valid_out(valid_1_muxC)
  );
  (* src = "mux_41.v:26" *)
  mux_estructural muxC (
    .clk(clk),
    .data_0(from_muxA_to_muxC),
    .data_1(from_muxB_to_muxC),
    .data_out(data_out),
    .reset_L(reset_L),
    .valid_0(valid_0_muxC),
    .valid_1(valid_1_muxC),
    .valid_out(valid_out)
  );
endmodule
module mux_41_estructural(clk, reset_L, data_0, data_1, data_2, data_3, valid_0, valid_1, valid_2, valid_3, data_out, valid_out);

  (* src = "mux_41.v:5" *)
  input clk;
  (* src = "mux_41.v:7" *)
  input [3:0] data_0;
  (* src = "mux_41.v:8" *)
  input [3:0] data_1;
  (* src = "mux_41.v:9" *)
  input [3:0] data_2;
  (* src = "mux_41.v:10" *)
  input [3:0] data_3;
  (* src = "mux_41.v:15" *)
  output [3:0] data_out;
  (* src = "mux_41.v:19" *)
  wire [3:0] from_muxA_to_muxC;
  (* src = "mux_41.v:20" *)
  wire [3:0] from_muxB_to_muxC;
  (* src = "mux_41.v:6" *)
  input reset_L;
  (* src = "mux_41.v:11" *)
  input valid_0;
  (* src = "mux_41.v:21" *)
  wire valid_0_muxC;
  (* src = "mux_41.v:12" *)
  input valid_1;
  (* src = "mux_41.v:22" *)
  wire valid_1_muxC;
  (* src = "mux_41.v:13" *)
  input valid_2;
  (* src = "mux_41.v:14" *)
  input valid_3;
  (* src = "mux_41.v:16" *)
  output valid_out;
  (* src = "mux_41.v:24" *)
  mux_estructural muxA (
    .clk(clk),
    .data_0(data_0),
    .data_1(data_1),
    .data_out(from_muxA_to_muxC),
    .reset_L(reset_L),
    .valid_0(valid_0),
    .valid_1(valid_1),
    .valid_out(valid_0_muxC)
  );
  (* src = "mux_41.v:25" *)
  mux_estructural muxB (
    .clk(clk),
    .data_0(data_2),
    .data_1(data_3),
    .data_out(from_muxB_to_muxC),
    .reset_L(reset_L),
    .valid_0(valid_2),
    .valid_1(valid_3),
    .valid_out(valid_1_muxC)
  );
  (* src = "mux_41.v:26" *)
  mux_estructural muxC (
    .clk(clk),
    .data_0(from_muxA_to_muxC),
    .data_1(from_muxB_to_muxC),
    .data_out(data_out),
    .reset_L(reset_L),
    .valid_0(valid_0_muxC),
    .valid_1(valid_1_muxC),
    .valid_out(valid_out)
  );
endmodule