data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv
 line:15: before: "CHDR_W"
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:20: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard,data/full_repos/permissive/214858095/test_exec.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard,data/full_repos/permissive/214858095/test_exec.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard,data/full_repos/permissive/214858095/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:27: Cannot find include file: rfnoc_block_switchboard_regs.vh\n  `include "rfnoc_block_switchboard_regs.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:22: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgTestExec::*;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:76: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);\n                                               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:79: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:80: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::item_t      item_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:96: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrPacket #(CHDR_W) ChdrPacket_t;\n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:175: Unsupported: classes\n  class Rand #(WIDTH = 32);\n  ^~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:176: Unsupported: \'static\' class item\n    static function logic [WIDTH-1:0] rand_logic();\n    ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:180: Unsupported or unknown PLI call: $urandom\n        result = {result, $urandom()};\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:187: syntax error, unexpected IDENTIFIER, expecting \'(\' or \';\'\n  function automatic ChdrPacket_t gen_rand_chdr_pkt(int num_samps);\n                                  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:188: syntax error, unexpected \'=\', expecting \',\' or \';\'\n    ChdrPacket_t  packet = new();\n                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n    header = Rand#($bits(header))::rand_logic();\n           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:198: syntax error, unexpected \'=\', expecting IDENTIFIER\n    header.pkt_type  = CHDR_DATA_NO_TS;\n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:199: syntax error, unexpected \'=\', expecting IDENTIFIER\n    header.num_mdata = 0;\n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:200: syntax error, unexpected \'=\', expecting IDENTIFIER\n    header.length    = CHDR_W/8 + num_samps*ITEM_W/8;   \n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:207: syntax error, unexpected \'(\', expecting IDENTIFIER\n      data.push_back(Rand#(CHDR_W)::rand_logic());\n                     ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:210: syntax error, unexpected \'(\', expecting IDENTIFIER\n    packet.write_raw(header, data);\n                     ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:235: syntax error, unexpected \'=\', expecting \',\' or \';\'\n    mailbox #(ChdrPacket_t) packets = new();\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:251: Unsupported or unknown PLI call: $urandom_range\n          packet = gen_rand_chdr_pkt($urandom_range(max_samps));\n                                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:252: syntax error, unexpected \'(\', expecting IDENTIFIER\n          packets.put(packet);\n                      ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:253: syntax error, unexpected \'(\', expecting IDENTIFIER\n          master_bfm.put_chdr(packet); \n                              ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:266: syntax error, unexpected \'(\', expecting IDENTIFIER\n          slave_bfm.get_chdr(packet);\n                             ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:267: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(packet.equal(expected), "Does not match");\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:295: Unsupported or unknown PLI call: $urandom_range\n    int rand_select = $urandom_range(0, limit);\n                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:297: syntax error, unexpected \'(\', expecting IDENTIFIER\n    write_reg(port, offset, 0);\n              ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:299: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(read_output == 0, "Register data does not match");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:303: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(read_output == rand_select, "Register data does not match");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:307: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(read_output == limit, "Register data does not match");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:322: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_tb(tb_name);\n                  ^~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:327: syntax error, unexpected \'(\', expecting IDENTIFIER\n    rfnoc_chdr_clk_gen.start();\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:328: syntax error, unexpected \'(\', expecting IDENTIFIER\n    rfnoc_ctrl_clk_gen.start();\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:331: syntax error, unexpected \'(\', expecting IDENTIFIER\n    blk_ctrl.run();\n                 ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:337: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Flush block then reset it", 10us);\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:338: syntax error, unexpected \'(\', expecting IDENTIFIER\n    blk_ctrl.flush_and_reset();\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:339: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:345: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Verify Block Info", 2us);\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:346: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:347: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:348: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:349: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:350: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:358: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Test Register RW", 10us);\n                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:363: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:367: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Test short packets", 1ms);\n                    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:368: Unsupported or unknown PLI call: $urandom_range\n    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:368: Unsupported or unknown PLI call: $urandom_range\n    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), \n                                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:370: Unsupported or unknown PLI call: $urandom_range\n    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:370: Unsupported or unknown PLI call: $urandom_range\n    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), \n                                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_switchboard/rfnoc_block_switchboard_tb.sv:372: Unsupported or unknown PLI call: $urandom_range\n    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), \n                ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module rfnoc_block_switchboard_tb #(
  parameter int CHDR_W              = 64,
  parameter int NUM_INPUTS          = 1,
  parameter int NUM_OUTPUTS         = 1  
);

  `include "test_exec.svh"

  import PkgTestExec::*;
  import PkgChdrUtils::*;
  import PkgRfnocBlockCtrlBfm::*;
  import PkgRfnocItemUtils::*;

  `include "rfnoc_block_switchboard_regs.vh"





  localparam [31:0] NOC_ID          = 32'hBE110000;
  localparam [ 9:0] THIS_PORTID     = 10'h123;
  localparam int    MTU             = 10;
  localparam int    NUM_PORTS_I     = NUM_INPUTS;
  localparam int    NUM_PORTS_O     = NUM_OUTPUTS;
  localparam int    ITEM_W          = 32;
  localparam int    SPP             = 64;
  localparam int    PKT_SIZE_BYTES  = SPP * (ITEM_W/8);
  localparam int    STALL_PROB      = 25;
  localparam real   CHDR_CLK_PER    = 5.0;
  localparam real   CTRL_CLK_PER    = 8.0;





  bit rfnoc_chdr_clk;
  bit rfnoc_ctrl_clk;




  sim_clock_gen #(.PERIOD(CHDR_CLK_PER), .AUTOSTART(0))
    rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
  sim_clock_gen #(.PERIOD(CTRL_CLK_PER), .AUTOSTART(0))
    rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());






  RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_ctrl_clk);


  AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, 1'b0);
  AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, 1'b0);


  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS_I] (rfnoc_chdr_clk, 1'b0);
  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS_O] (rfnoc_chdr_clk, 1'b0);


  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);


  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_t      item_t;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_bfm_input_connections
    initial begin
      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
    end
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_bfm_output_connections
    initial begin
      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
    end
  end

  typedef ChdrPacket #(CHDR_W) ChdrPacket_t;






  logic [CHDR_W*NUM_PORTS_I-1:0] s_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tready;


  logic [CHDR_W*NUM_PORTS_O-1:0] m_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tready;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_dut_input_connections

    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_dut_output_connections

    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
  end

  rfnoc_block_switchboard #(
    .THIS_PORTID         (THIS_PORTID),
    .CHDR_W              (CHDR_W),
    .MTU                 (MTU),
    .NUM_INPUTS          (NUM_INPUTS),
    .NUM_OUTPUTS         (NUM_OUTPUTS)
  ) dut (
    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
    .rfnoc_core_config   (backend.cfg),
    .rfnoc_core_status   (backend.sts),
    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
    .s_rfnoc_ctrl_tdata  (m_ctrl.tdata),
    .s_rfnoc_ctrl_tlast  (m_ctrl.tlast),
    .s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
    .s_rfnoc_ctrl_tready (m_ctrl.tready),
    .m_rfnoc_ctrl_tdata  (s_ctrl.tdata),
    .m_rfnoc_ctrl_tlast  (s_ctrl.tlast),
    .m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
    .m_rfnoc_ctrl_tready (s_ctrl.tready)
  );






  task automatic write_reg(int port, bit [19:0] addr, bit [31:0] value);
    blk_ctrl.reg_write((2**SWITCH_ADDR_W)*port + addr, value);
  endtask : write_reg


  task automatic read_reg(int port, bit [19:0] addr, output logic [63:0] value);
    blk_ctrl.reg_read((2**SWITCH_ADDR_W)*port + addr, value[31:0]);
  endtask : read_reg



  class Rand #(WIDTH = 32);
    static function logic [WIDTH-1:0] rand_logic();
      logic [WIDTH-1:0] result;
      int num_rand32 = (WIDTH + 31) / 32;
      for (int i = 0; i < num_rand32; i++) begin
        result = {result, $urandom()};
      end
      return result;
    endfunction : rand_logic
  endclass : Rand


  function automatic ChdrPacket_t gen_rand_chdr_pkt(int num_samps);
    ChdrPacket_t  packet = new();
    chdr_header_t header;
    chdr_word_t   data[$];






    header = Rand#($bits(header))::rand_logic();
    header.pkt_type  = CHDR_DATA_NO_TS;
    header.num_mdata = 0;
    header.length    = CHDR_W/8 + num_samps*ITEM_W/8;


    repeat (num_samps * ITEM_W / CHDR_W) 
      data.push_back(Rand#(CHDR_W)::rand_logic());

    if (num_samps * ITEM_W % CHDR_W != 0)
      data.push_back(Rand#(CHDR_W)::rand_logic());


    packet.write_raw(header, data);

    return packet;
  endfunction : gen_rand_chdr_pkt










  task automatic test_stream(
    int input_port    = 0,
    int output_port   = 0,
    int num_packets   = 100,
    int max_samps     = SPP
  );

    ChdrIfaceBfm #(CHDR_W, ITEM_W) master_bfm;
    ChdrIfaceBfm #(CHDR_W, ITEM_W) slave_bfm;


    mailbox #(ChdrPacket_t) packets = new();


    master_bfm = blk_ctrl.get_master_data_bfm(input_port);
    slave_bfm = blk_ctrl.get_slave_data_bfm(output_port);

    write_reg(input_port, REG_DEMUX_SELECT, output_port);
    write_reg(output_port, REG_MUX_SELECT, input_port);

    fork



      begin : master
        ChdrPacket_t packet;
        repeat (num_packets) begin
          packet = gen_rand_chdr_pkt($urandom_range(max_samps));
          packets.put(packet);
          master_bfm.put_chdr(packet); 
        end
      end




      begin : slaves
        ChdrPacket_t expected, packet;

        repeat (num_packets) begin

          packets.get(expected);
          slave_bfm.get_chdr(packet);
          `ASSERT_ERROR(packet.equal(expected), "Does not match");
        end
      end
    join
  endtask : test_stream


  task automatic test_concurrent(
    int num_packets = 100,
    int max_samps = SPP
  );
    fork
      begin : Stream_A
        test_stream(0, 0, num_packets, max_samps);
      end

      begin : Stream_B
        test_stream(NUM_INPUTS-1, NUM_OUTPUTS-1, num_packets, max_samps);
      end
    join
  endtask : test_concurrent


  task automatic test_reg(
    int port = 0,
    int offset = 0,
    int limit = 0
  );
    int rand_select = $urandom_range(0, limit);
    int read_output;
    write_reg(port, offset, 0);
    read_reg(port, offset, read_output);
    `ASSERT_ERROR(read_output == 0, "Register data does not match");

    write_reg(port, offset, rand_select);
    read_reg(port, offset, read_output);
    `ASSERT_ERROR(read_output == rand_select, "Register data does not match");

    write_reg(port, offset, limit);
    read_reg(port, offset, read_output);
    `ASSERT_ERROR(read_output == limit, "Register data does not match");
  endtask : test_reg





  initial begin : tb_main
    string tb_name;


    tb_name = $sformatf(
      "rfnoc_block_switch_tb\nCHDR_W = %0D, NUM_INPUTS = %0D, NUM_OUTPUTS = %0D",
      CHDR_W, NUM_INPUTS, NUM_OUTPUTS
    );
    test.start_tb(tb_name);




    rfnoc_chdr_clk_gen.start();
    rfnoc_ctrl_clk_gen.start();


    blk_ctrl.run();





    test.start_test("Flush block then reset it", 10us);
    blk_ctrl.flush_and_reset();
    test.end_test();





    test.start_test("Verify Block Info", 2us);
    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");
    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
    test.end_test();







    test.start_test("Test Register RW", 10us);
    test_reg(0,             REG_DEMUX_SELECT,   NUM_OUTPUTS-1);
    test_reg(NUM_INPUTS-1,  REG_DEMUX_SELECT,   NUM_OUTPUTS-1);
    test_reg(0,             REG_MUX_SELECT,     NUM_INPUTS-1);
    test_reg(NUM_OUTPUTS-1, REG_MUX_SELECT,     NUM_INPUTS-1);
    test.end_test();



    test.start_test("Test short packets", 1ms);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      1000, 4*CHDR_W/ITEM_W);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      1000, 4*CHDR_W/ITEM_W);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      1000, 4*CHDR_W/ITEM_W);
    test.end_test();

    test.start_test("Test long packets", 1ms);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      100, SPP);
    test.end_test();

    test.start_test("Test short packets, fast source, slow sink", 1ms);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      1000, 4*CHDR_W/ITEM_W);
    test.end_test();

    test.start_test("Test long packets, fast source, slow sink", 1ms);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      200, SPP);
    test.end_test();

    if(NUM_INPUTS > 1 && NUM_OUTPUTS > 1) begin
      test.start_test("Test concurrent streams", 1ms);
      test_concurrent(100, 4*CHDR_W/ITEM_W);
      test.end_test();
    end







    test.end_tb(0);


    rfnoc_chdr_clk_gen.kill();
    rfnoc_ctrl_clk_gen.kill();
  end : tb_main

endmodule
module rfnoc_block_switchboard_tb #(
  parameter int CHDR_W              = 64,
  parameter int NUM_INPUTS          = 1,
  parameter int NUM_OUTPUTS         = 1  
);


  `include "test_exec.svh"

  import PkgTestExec::*;
  import PkgChdrUtils::*;
  import PkgRfnocBlockCtrlBfm::*;
  import PkgRfnocItemUtils::*;

  `include "rfnoc_block_switchboard_regs.vh"





  localparam [31:0] NOC_ID          = 32'hBE110000;
  localparam [ 9:0] THIS_PORTID     = 10'h123;
  localparam int    MTU             = 10;
  localparam int    NUM_PORTS_I     = NUM_INPUTS;
  localparam int    NUM_PORTS_O     = NUM_OUTPUTS;
  localparam int    ITEM_W          = 32;
  localparam int    SPP             = 64;
  localparam int    PKT_SIZE_BYTES  = SPP * (ITEM_W/8);
  localparam int    STALL_PROB      = 25;
  localparam real   CHDR_CLK_PER    = 5.0;
  localparam real   CTRL_CLK_PER    = 8.0;





  bit rfnoc_chdr_clk;
  bit rfnoc_ctrl_clk;




  sim_clock_gen #(.PERIOD(CHDR_CLK_PER), .AUTOSTART(0))
    rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
  sim_clock_gen #(.PERIOD(CTRL_CLK_PER), .AUTOSTART(0))
    rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());






  RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_ctrl_clk);


  AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, 1'b0);
  AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, 1'b0);


  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS_I] (rfnoc_chdr_clk, 1'b0);
  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS_O] (rfnoc_chdr_clk, 1'b0);


  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);


  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_t      item_t;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_bfm_input_connections
    initial begin
      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
    end
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_bfm_output_connections
    initial begin
      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
    end
  end

  typedef ChdrPacket #(CHDR_W) ChdrPacket_t;






  logic [CHDR_W*NUM_PORTS_I-1:0] s_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tready;


  logic [CHDR_W*NUM_PORTS_O-1:0] m_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tready;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_dut_input_connections

    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_dut_output_connections

    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
  end

  rfnoc_block_switchboard #(
    .THIS_PORTID         (THIS_PORTID),
    .CHDR_W              (CHDR_W),
    .MTU                 (MTU),
    .NUM_INPUTS          (NUM_INPUTS),
    .NUM_OUTPUTS         (NUM_OUTPUTS)
  ) dut (
    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
    .rfnoc_core_config   (backend.cfg),
    .rfnoc_core_status   (backend.sts),
    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
    .s_rfnoc_ctrl_tdata  (m_ctrl.tdata),
    .s_rfnoc_ctrl_tlast  (m_ctrl.tlast),
    .s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
    .s_rfnoc_ctrl_tready (m_ctrl.tready),
    .m_rfnoc_ctrl_tdata  (s_ctrl.tdata),
    .m_rfnoc_ctrl_tlast  (s_ctrl.tlast),
    .m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
    .m_rfnoc_ctrl_tready (s_ctrl.tready)
  );






  task automatic write_reg(int port, bit [19:0] addr, bit [31:0] value);
    blk_ctrl.reg_write((2**SWITCH_ADDR_W)*port + addr, value);
  endtask : write_reg


  task automatic read_reg(int port, bit [19:0] addr, output logic [63:0] value);
    blk_ctrl.reg_read((2**SWITCH_ADDR_W)*port + addr, value[31:0]);
  endtask : read_reg



  class Rand #(WIDTH = 32);
    static function logic [WIDTH-1:0] rand_logic();
      logic [WIDTH-1:0] result;
      int num_rand32 = (WIDTH + 31) / 32;
      for (int i = 0; i < num_rand32; i++) begin
        result = {result, $urandom()};
      end
      return result;
    endfunction : rand_logic
  endclass : Rand


  function automatic ChdrPacket_t gen_rand_chdr_pkt(int num_samps);
    ChdrPacket_t  packet = new();
    chdr_header_t header;
    chdr_word_t   data[$];






    header = Rand#($bits(header))::rand_logic();
    header.pkt_type  = CHDR_DATA_NO_TS;
    header.num_mdata = 0;
    header.length    = CHDR_W/8 + num_samps*ITEM_W/8;


    repeat (num_samps * ITEM_W / CHDR_W) 
      data.push_back(Rand#(CHDR_W)::rand_logic());

    if (num_samps * ITEM_W % CHDR_W != 0)
      data.push_back(Rand#(CHDR_W)::rand_logic());


    packet.write_raw(header, data);

    return packet;
  endfunction : gen_rand_chdr_pkt










  task automatic test_stream(
    int input_port    = 0,
    int output_port   = 0,
    int num_packets   = 100,
    int max_samps     = SPP
  );

    ChdrIfaceBfm #(CHDR_W, ITEM_W) master_bfm;
    ChdrIfaceBfm #(CHDR_W, ITEM_W) slave_bfm;


    mailbox #(ChdrPacket_t) packets = new();


    master_bfm = blk_ctrl.get_master_data_bfm(input_port);
    slave_bfm = blk_ctrl.get_slave_data_bfm(output_port);

    write_reg(input_port, REG_DEMUX_SELECT, output_port);
    write_reg(output_port, REG_MUX_SELECT, input_port);

    fork



      begin : master
        ChdrPacket_t packet;
        repeat (num_packets) begin
          packet = gen_rand_chdr_pkt($urandom_range(max_samps));
          packets.put(packet);
          master_bfm.put_chdr(packet); 
        end
      end




      begin : slaves
        ChdrPacket_t expected, packet;

        repeat (num_packets) begin

          packets.get(expected);
          slave_bfm.get_chdr(packet);
          `ASSERT_ERROR(packet.equal(expected), "Does not match");
        end
      end
    join
  endtask : test_stream


  task automatic test_concurrent(
    int num_packets = 100,
    int max_samps = SPP
  );
    fork
      begin : Stream_A
        test_stream(0, 0, num_packets, max_samps);
      end

      begin : Stream_B
        test_stream(NUM_INPUTS-1, NUM_OUTPUTS-1, num_packets, max_samps);
      end
    join
  endtask : test_concurrent


  task automatic test_reg(
    int port = 0,
    int offset = 0,
    int limit = 0
  );
    int rand_select = $urandom_range(0, limit);
    int read_output;
    write_reg(port, offset, 0);
    read_reg(port, offset, read_output);
    `ASSERT_ERROR(read_output == 0, "Register data does not match");

    write_reg(port, offset, rand_select);
    read_reg(port, offset, read_output);
    `ASSERT_ERROR(read_output == rand_select, "Register data does not match");

    write_reg(port, offset, limit);
    read_reg(port, offset, read_output);
    `ASSERT_ERROR(read_output == limit, "Register data does not match");
  endtask : test_reg





  initial begin : tb_main
    string tb_name;


    tb_name = $sformatf(
      "rfnoc_block_switch_tb\nCHDR_W = %0D, NUM_INPUTS = %0D, NUM_OUTPUTS = %0D",
      CHDR_W, NUM_INPUTS, NUM_OUTPUTS
    );
    test.start_tb(tb_name);




    rfnoc_chdr_clk_gen.start();
    rfnoc_ctrl_clk_gen.start();


    blk_ctrl.run();





    test.start_test("Flush block then reset it", 10us);
    blk_ctrl.flush_and_reset();
    test.end_test();





    test.start_test("Verify Block Info", 2us);
    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");
    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
    test.end_test();







    test.start_test("Test Register RW", 10us);
    test_reg(0,             REG_DEMUX_SELECT,   NUM_OUTPUTS-1);
    test_reg(NUM_INPUTS-1,  REG_DEMUX_SELECT,   NUM_OUTPUTS-1);
    test_reg(0,             REG_MUX_SELECT,     NUM_INPUTS-1);
    test_reg(NUM_OUTPUTS-1, REG_MUX_SELECT,     NUM_INPUTS-1);
    test.end_test();



    test.start_test("Test short packets", 1ms);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      1000, 4*CHDR_W/ITEM_W);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      1000, 4*CHDR_W/ITEM_W);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      1000, 4*CHDR_W/ITEM_W);
    test.end_test();

    test.start_test("Test long packets", 1ms);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      100, SPP);
    test.end_test();

    test.start_test("Test short packets, fast source, slow sink", 1ms);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      1000, 4*CHDR_W/ITEM_W);
    test.end_test();

    test.start_test("Test long packets, fast source, slow sink", 1ms);
    test_stream($urandom_range(0, NUM_INPUTS-1), $urandom_range(0, NUM_OUTPUTS-1), 
      200, SPP);
    test.end_test();

    if(NUM_INPUTS > 1 && NUM_OUTPUTS > 1) begin
      test.start_test("Test concurrent streams", 1ms);
      test_concurrent(100, 4*CHDR_W/ITEM_W);
      test.end_test();
    end







    test.end_tb(0);


    rfnoc_chdr_clk_gen.kill();
    rfnoc_ctrl_clk_gen.kill();
  end : tb_main

endmodule