data/full_repos/permissive/135852214/Verilog/revmuxsim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/revmuxsim.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/revmuxsim.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Error: data/full_repos/permissive/135852214/Verilog/revmuxsim.v:40: Cannot find file containing module: \'revMUX12\'\n revMUX12 uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/revMUX12\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/revMUX12.v\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/revMUX12.sv\n             revMUX12\n             revMUX12.v\n             revMUX12.sv\n             obj_dir/revMUX12\n             obj_dir/revMUX12.v\n             obj_dir/revMUX12.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module revmuxsim;


	reg [11:0] a_in;
	reg [11:0] b_in;
	reg s_in;
	reg [11:0] x_in;


	wire [11:0] a_out;
	wire [11:0] b_out;
	wire s_out;
	wire [11:0] x_out;


	revMUX12 uut (
		.a_in(a_in), 
		.b_in(b_in), 
		.s_in(s_in), 
		.x_in(x_in), 
		.a_out(a_out), 
		.b_out(b_out), 
		.s_out(s_out), 
		.x_out(x_out)
	);

	initial begin

		a_in = 0;
		b_in = 0;
		s_in = 0;
		x_in = 0;


		#100;
		
		a_in = 15;
		b_in = 255;
		#100
		s_in = 1;
        


	end
      
endmodule
module revmuxsim;



	reg [11:0] a_in;
	reg [11:0] b_in;
	reg s_in;
	reg [11:0] x_in;


	wire [11:0] a_out;
	wire [11:0] b_out;
	wire s_out;
	wire [11:0] x_out;


	revMUX12 uut (
		.a_in(a_in), 
		.b_in(b_in), 
		.s_in(s_in), 
		.x_in(x_in), 
		.a_out(a_out), 
		.b_out(b_out), 
		.s_out(s_out), 
		.x_out(x_out)
	);

	initial begin

		a_in = 0;
		b_in = 0;
		s_in = 0;
		x_in = 0;


		#100;
		
		a_in = 15;
		b_in = 255;
		#100
		s_in = 1;
        


	end
      
endmodule