data/full_repos/permissive/150329835/src/Multiplexer.v
data/verilator_xmls/4eb50226-8625-4f74-a8d8-1b7b27c76dc2.xml
module MULTIPLEXER(MODE,A,B,C,D,F);
	input [1:0] MODE;
	input [9:0] A,B,C,D;
	output reg [9:0] F;
	
	always @*
		case(MODE)
			2'b00: F = A;
			2'b01: F = B;
			2'b10: F = C;
			2'b11: F = D;
		endcase
endmodule
module MULTIPLEXER(MODE,A,B,C,D,F);

	input [1:0] MODE;
	input [9:0] A,B,C,D;
	output reg [9:0] F;
	
	always @*
		case(MODE)
			2'b00: F = A;
			2'b01: F = B;
			2'b10: F = C;
			2'b11: F = D;
		endcase
endmodule