data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:59: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clock = ~clock;\n           ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:12: Cannot find file containing module: \'DataMemoryInterface\'\n    DataMemoryInterface DataMemory(\n    ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/DataMemoryInterface\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/DataMemoryInterface.v\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/DataMemoryInterface.sv\n             DataMemoryInterface\n             DataMemoryInterface.v\n             DataMemoryInterface.sv\n             obj_dir/DataMemoryInterface\n             obj_dir/DataMemoryInterface.v\n             obj_dir/DataMemoryInterface.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_DataMemoryInterface ();
    reg           clock;
    reg           reset;
    reg [31:0]    address;
    reg           mem_write;
    reg [31:0]    data_write;
    reg           mem_read;
    wire [31:0]   read_data;

    DataMemoryInterface DataMemory(
        .clock          (clock),
        .reset          (reset),
        .address        (address),
        .mem_write      (mem_write),
        .data_write     (data_write),
        .mem_read       (mem_read),
        .read_data      (read_data)
    );


    initial begin
        reset = 0;
        clock = 1;

        #10
        address = 32'd0;
        mem_write = 1;
        data_write = 32'd500;

        #20
        mem_write = 0;
        mem_read = 1;

        #10
        if (read_data == 32'd500)
            $display ("Read and Write 1 - OK");
        else
            $display ("Read and Write 1 - FAIL");

        #20
        address = 32'd0;
        mem_write = 1;
        data_write = 32'd400;

        #20
        mem_write = 0;
        mem_read = 1;

        #10
        if (read_data == 32'd400)
            $display ("Read and Write Override - OK");
        else
            $display ("Read and Write Override - FAIL");

    end

    always #10 clock = ~clock;

endmodule
module TB_DataMemoryInterface ();

    reg           clock;
    reg           reset;
    reg [31:0]    address;
    reg           mem_write;
    reg [31:0]    data_write;
    reg           mem_read;
    wire [31:0]   read_data;

    DataMemoryInterface DataMemory(
        .clock          (clock),
        .reset          (reset),
        .address        (address),
        .mem_write      (mem_write),
        .data_write     (data_write),
        .mem_read       (mem_read),
        .read_data      (read_data)
    );


    initial begin
        reset = 0;
        clock = 1;

        #10
        address = 32'd0;
        mem_write = 1;
        data_write = 32'd500;

        #20
        mem_write = 0;
        mem_read = 1;

        #10
        if (read_data == 32'd500)
            $display ("Read and Write 1 - OK");
        else
            $display ("Read and Write 1 - FAIL");

        #20
        address = 32'd0;
        mem_write = 1;
        data_write = 32'd400;

        #20
        mem_write = 0;
        mem_read = 1;

        #10
        if (read_data == 32'd400)
            $display ("Read and Write Override - OK");
        else
            $display ("Read and Write Override - FAIL");

    end

    always #10 clock = ~clock;

endmodule