data/full_repos/permissive/178106827/verif/tb_top.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/178106827/verif/tb_top.sv:7: Cannot find include file: uvm_macros.svh\n    `include "uvm_macros.svh" \n             ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/178106827/verif,data/full_repos/permissive/178106827/uvm_macros.svh\n             data/full_repos/permissive/178106827/verif,data/full_repos/permissive/178106827/uvm_macros.svh.v\n             data/full_repos/permissive/178106827/verif,data/full_repos/permissive/178106827/uvm_macros.svh.sv\n             uvm_macros.svh\n             uvm_macros.svh.v\n             uvm_macros.svh.sv\n             obj_dir/uvm_macros.svh\n             obj_dir/uvm_macros.svh.v\n             obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/178106827/verif/tb_top.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n    import uvm_pkg::*;    \n           ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/178106827/verif/tb_top.sv:46: Unsupported: Ignoring delay on this delayed statement.\n            #(5ns) clk_100MHz = ~clk_100MHz;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/178106827/verif/tb_top.sv:101: syntax error, unexpected \'#\'\n        uvm_config_db#(virtual apb_interface)::set(null, "*", "APB_INTF", apb_intf);\n                     ^\n%Error: data/full_repos/permissive/178106827/verif/tb_top.sv:108: Unsupported or unknown PLI call: $dumpvars\n    initial $dumpvars(0, tb_top);\n            ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module tb_top();

    `include "uvm_macros.svh"
    import uvm_pkg::*;    
    

    import apb_test_pkg::*;
    

    bit clk_100MHz;

     
    wire                 w_reset;
    wire                 w_scan_en;

    wire                 w_idle;
    wire [1-1:0]         w_INT;
   
    wire [31:1]          w_periph_tx_req;
    wire [31:1]         w_periph_tx_clr;
    wire [31:1]          w_periph_rx_req;
    wire [31:1]         w_periph_rx_clr;

   wire                                w_pclken;
   wire                                w_psel;
   wire                                w_penable;
   wire [12:0]                         w_paddr;
   wire                                w_pwrite;
   wire [31:0]                         w_pwdata;
   wire  [31:0]                        w_prdata;
   wire                                w_pslverr;
   wire                                w_pready;
	
	

    apb_interface   apb_intf(clk_100MHz);
    dma_perf_interface dma_perf_intf(clk_100MHz);
	

    initial begin
        forever begin
            #(5ns) clk_100MHz = ~clk_100MHz;
        end
    end

	assign w_scan_en = 0;
	
	assign w_reset = !apb_intf.PRESETn; 
	assign w_pclken = 1'b1;
	assign w_psel = apb_intf.PSEL;    
	assign w_penable = apb_intf.PENABLE; 
	assign w_pwrite = apb_intf.PWRITE;  
	assign w_paddr = apb_intf.PADDR;   
	assign w_pwdata = apb_intf.PWDATA;  
	assign apb_intf.PRDATA = w_prdata;  
	assign apb_intf.PREADY = w_pready;  
	assign apb_intf.PSLVERR = w_pslverr; 

	assign w_periph_tx_req = 'h7FFF_FFFF;
	assign w_periph_rx_req = 'h7FFF_FFFF;
	
	dma_axi64_wrap u_dma_axi64_wrap(
		.clk(clk_100MHz),
		.reset(w_reset),
		.scan_en(w_scan_en),
	
		.idle(w_idle),
		.INT(w_INT),
		.periph_tx_req(w_periph_tx_req),
		.periph_tx_clr(w_periph_tx_clr),
		.periph_rx_req(w_periph_rx_req),
		.periph_rx_clr(w_periph_rx_clr),
		.pclken(w_pclken),
		.psel(w_psel),
		.penable(w_penable),
		.paddr(w_paddr),
		.pwrite(w_pwrite),
		.pwdata(w_pwdata),
		.prdata(w_prdata),
		.pslverr(w_pslverr),
		.pready(w_pready)
	);		
	
    assign dma_perf_intf.periph_tx_req = w_periph_tx_req[1];
    assign dma_perf_intf.periph_tx_clr = w_periph_tx_clr[1];
    assign dma_perf_intf.periph_rx_req = w_periph_rx_req[1];
    assign dma_perf_intf.periph_rx_clr = w_periph_rx_clr[1];
    assign dma_perf_intf.WSTRB0 = u_dma_axi64_wrap.w_WSTRB0;
    assign dma_perf_intf.WVALID0 = u_dma_axi64_wrap.w_WVALID0;
    assign dma_perf_intf.WREADY0 = u_dma_axi64_wrap.w_WREADY0;
    assign dma_perf_intf.RVALID0 = u_dma_axi64_wrap.w_RVALID0;
    assign dma_perf_intf.RREADY0 = u_dma_axi64_wrap.w_RREADY0;
	
                    

    initial begin
        uvm_config_db#(virtual apb_interface)::set(null, "*", "APB_INTF", apb_intf);
        uvm_config_db#(virtual dma_perf_interface)::set(null, "*", "DMA_PERF_INTF", dma_perf_intf); 

       run_test();
    end
	

    initial $dumpvars(0, tb_top);
    
endmodule
module tb_top();


    `include "uvm_macros.svh"
    import uvm_pkg::*;    
    

    import apb_test_pkg::*;
    

    bit clk_100MHz;

     
    wire                 w_reset;
    wire                 w_scan_en;

    wire                 w_idle;
    wire [1-1:0]         w_INT;
   
    wire [31:1]          w_periph_tx_req;
    wire [31:1]         w_periph_tx_clr;
    wire [31:1]          w_periph_rx_req;
    wire [31:1]         w_periph_rx_clr;

   wire                                w_pclken;
   wire                                w_psel;
   wire                                w_penable;
   wire [12:0]                         w_paddr;
   wire                                w_pwrite;
   wire [31:0]                         w_pwdata;
   wire  [31:0]                        w_prdata;
   wire                                w_pslverr;
   wire                                w_pready;
	
	

    apb_interface   apb_intf(clk_100MHz);
    dma_perf_interface dma_perf_intf(clk_100MHz);
	

    initial begin
        forever begin
            #(5ns) clk_100MHz = ~clk_100MHz;
        end
    end

	assign w_scan_en = 0;
	
	assign w_reset = !apb_intf.PRESETn; 
	assign w_pclken = 1'b1;
	assign w_psel = apb_intf.PSEL;    
	assign w_penable = apb_intf.PENABLE; 
	assign w_pwrite = apb_intf.PWRITE;  
	assign w_paddr = apb_intf.PADDR;   
	assign w_pwdata = apb_intf.PWDATA;  
	assign apb_intf.PRDATA = w_prdata;  
	assign apb_intf.PREADY = w_pready;  
	assign apb_intf.PSLVERR = w_pslverr; 

	assign w_periph_tx_req = 'h7FFF_FFFF;
	assign w_periph_rx_req = 'h7FFF_FFFF;
	
	dma_axi64_wrap u_dma_axi64_wrap(
		.clk(clk_100MHz),
		.reset(w_reset),
		.scan_en(w_scan_en),
	
		.idle(w_idle),
		.INT(w_INT),
		.periph_tx_req(w_periph_tx_req),
		.periph_tx_clr(w_periph_tx_clr),
		.periph_rx_req(w_periph_rx_req),
		.periph_rx_clr(w_periph_rx_clr),
		.pclken(w_pclken),
		.psel(w_psel),
		.penable(w_penable),
		.paddr(w_paddr),
		.pwrite(w_pwrite),
		.pwdata(w_pwdata),
		.prdata(w_prdata),
		.pslverr(w_pslverr),
		.pready(w_pready)
	);		
	
    assign dma_perf_intf.periph_tx_req = w_periph_tx_req[1];
    assign dma_perf_intf.periph_tx_clr = w_periph_tx_clr[1];
    assign dma_perf_intf.periph_rx_req = w_periph_rx_req[1];
    assign dma_perf_intf.periph_rx_clr = w_periph_rx_clr[1];
    assign dma_perf_intf.WSTRB0 = u_dma_axi64_wrap.w_WSTRB0;
    assign dma_perf_intf.WVALID0 = u_dma_axi64_wrap.w_WVALID0;
    assign dma_perf_intf.WREADY0 = u_dma_axi64_wrap.w_WREADY0;
    assign dma_perf_intf.RVALID0 = u_dma_axi64_wrap.w_RVALID0;
    assign dma_perf_intf.RREADY0 = u_dma_axi64_wrap.w_RREADY0;
	
                    

    initial begin
        uvm_config_db#(virtual apb_interface)::set(null, "*", "APB_INTF", apb_intf);
        uvm_config_db#(virtual dma_perf_interface)::set(null, "*", "DMA_PERF_INTF", dma_perf_intf); 

       run_test();
    end
	

    initial $dumpvars(0, tb_top);
    
endmodule