data/full_repos/permissive/143278/ivltests/wild_cmp_net.v
 line:6: before: "?"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:103: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:106: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:116: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wild_cmp_net.v:119: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg [1:0] lv, rv;
  reg pass;
  wire res, resb;

  assign res = lv  ==? rv;
  assign resb = lv  !=? rv;

  initial begin
    pass = 1'b1;

    lv = 2'b00;
    rv = 2'b00;
    #1;
    if (res !== 1'b1) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
      pass = 1'b0;
    end

    if (resb !== 1'b0) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b00;
    rv = 2'b01;
    #1;
    if (res !== 1'b0) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b1) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b10;
    rv = 2'b00;
    #1;
    if (res !== 1'b0) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b1) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b1x;
    rv = 2'b00;
    #1;
    if (res !== 1'b0) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b1) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b0x;
    rv = 2'b00;
    #1;
    if (res !== 1'bx) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'bx", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'bx) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'bx", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b00;
    rv = 2'b0x;
    #1;
    if (res !== 1'b1) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b0) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b01;
    rv = 2'b0x;
    #1;
    if (res !== 1'b1) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b0) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b0z;
    rv = 2'b0x;
    #1;
    if (res !== 1'b1) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b0) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b0x;
    rv = 2'b0x;
    #1;
    if (res !== 1'b1) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b0) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg [1:0] lv, rv;
  reg pass;
  wire res, resb;

  assign res = lv  ==? rv;
  assign resb = lv  !=? rv;

  initial begin
    pass = 1'b1;

    lv = 2'b00;
    rv = 2'b00;
    #1;
    if (res !== 1'b1) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
      pass = 1'b0;
    end

    if (resb !== 1'b0) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b00;
    rv = 2'b01;
    #1;
    if (res !== 1'b0) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b1) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b10;
    rv = 2'b00;
    #1;
    if (res !== 1'b0) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b1) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b1x;
    rv = 2'b00;
    #1;
    if (res !== 1'b0) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b1) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b0x;
    rv = 2'b00;
    #1;
    if (res !== 1'bx) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'bx", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'bx) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'bx", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b00;
    rv = 2'b0x;
    #1;
    if (res !== 1'b1) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b0) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b01;
    rv = 2'b0x;
    #1;
    if (res !== 1'b1) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b0) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b0z;
    rv = 2'b0x;
    #1;
    if (res !== 1'b1) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b0) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb);
      pass = 1'b0;
    end

    #1;
    lv = 2'b0x;
    rv = 2'b0x;
    #1;
    if (res !== 1'b1) begin
      $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
      pass = 1'b0;
    end
    if (resb !== 1'b0) begin
      $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule