data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/Crosslink_DualCSI2toRaw10/source/clarity/dual_camera/pll_double/pll_double_prim.v
 line:29: before: "."
1: b"%Error: data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/Crosslink_DualCSI2toRaw10/source/clarity/dual_camera/pll_double/pll_double_prim.v:22: Cannot find file containing module: 'VLO'\n    VLO scuba_vlo_inst (.Z(scuba_vlo));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/Crosslink_DualCSI2toRaw10/source/clarity/dual_camera/pll_double,data/full_repos/permissive/138208056/VLO\n             data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/Crosslink_DualCSI2toRaw10/source/clarity/dual_camera/pll_double,data/full_repos/permissive/138208056/VLO.v\n             data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/Crosslink_DualCSI2toRaw10/source/clarity/dual_camera/pll_double,data/full_repos/permissive/138208056/VLO.sv\n             VLO\n             VLO.v\n             VLO.sv\n             obj_dir/VLO\n             obj_dir/VLO.v\n             obj_dir/VLO.sv\n%Error: data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/Crosslink_DualCSI2toRaw10/source/clarity/dual_camera/pll_double/pll_double_prim.v:23: Cannot find file containing module: 'EHXPLLM'\n    EHXPLLM PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP), .PHASESEL0(scuba_vlo), \n    ^~~~~~~\n%Error: data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/Crosslink_DualCSI2toRaw10/source/clarity/dual_camera/pll_double/pll_double_prim.v:66: Cannot find file containing module: 'GSR'\n    GSR GSR_INST (.GSR(VCC_net));\n    ^~~\n%Error: data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/Crosslink_DualCSI2toRaw10/source/clarity/dual_camera/pll_double/pll_double_prim.v:67: Cannot find file containing module: 'PUR'\n    PUR PUR_INST (.PUR(VCC_net));\n    ^~~\n%Error: data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/Crosslink_DualCSI2toRaw10/source/clarity/dual_camera/pll_double/pll_double_prim.v:69: Cannot find file containing module: 'VHI'\n    VHI i85 (.Z(VCC_net));\n    ^~~\n%Error: Exiting due to 5 error(s)\n"
module pll_double (CLKI, RST, CLKOP, CLKOS, CLKOS2, LOCK);
    input CLKI;
    input RST;
    output CLKOP;
    output CLKOS;
    output CLKOS2;
    output LOCK;
    
    wire CLKI;
    wire CLKOP;
    wire CLKOS;
    wire CLKOS2;
    
    wire scuba_vlo, VCC_net;
    
    VLO scuba_vlo_inst (.Z(scuba_vlo));
    EHXPLLM PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP), .PHASESEL0(scuba_vlo), 
            .PHASESEL1(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), 
            .PHASELOADREG(scuba_vlo), .USRSTDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), 
            .RST(RST), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), 
            .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP), .CLKOS(CLKOS), .CLKOS2(CLKOS2), 
            .LOCK(LOCK));
    defparam PLLInst_0.FIN = "100.0000";
    defparam PLLInst_0.CLKI_DIV = 5;
    defparam PLLInst_0.CLKFB_DIV = 16;
    defparam PLLInst_0.CLKOP_DIV = 3;
    defparam PLLInst_0.CLKOS_DIV = 3;
    defparam PLLInst_0.CLKOS2_DIV = 1;
    defparam PLLInst_0.CLKOS3_DIV = 1;
    defparam PLLInst_0.CLKOP_ENABLE = "ENABLED";
    defparam PLLInst_0.CLKOS_ENABLE = "ENABLED";
    defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED";
    defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED";
    defparam PLLInst_0.CLKOP_CPHASE = 2;
    defparam PLLInst_0.CLKOS_CPHASE = 2;
    defparam PLLInst_0.CLKOS2_CPHASE = 0;
    defparam PLLInst_0.CLKOS3_CPHASE = 0;
    defparam PLLInst_0.CLKOP_FPHASE = 0;
    defparam PLLInst_0.CLKOS_FPHASE = 6;
    defparam PLLInst_0.CLKOS2_FPHASE = 0;
    defparam PLLInst_0.CLKOS3_FPHASE = 0;
    defparam PLLInst_0.FEEDBK_PATH = "CLKOP";
    defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING";
    defparam PLLInst_0.CLKOP_TRIM_DELAY = 0;
    defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING";
    defparam PLLInst_0.CLKOS_TRIM_DELAY = 0;
    defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA";
    defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB";
    defparam PLLInst_0.OUTDIVIDER_MUXC = "REFCLK";
    defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD";
    defparam PLLInst_0.PLL_LOCK_MODE = 0;
    defparam PLLInst_0.PLL_LOCK_DELAY = 200;
    defparam PLLInst_0.REFIN_RESET = "DISABLED";
    defparam PLLInst_0.SYNC_ENABLE = "DISABLED";
    defparam PLLInst_0.INT_LOCK_STICKY = "ENABLED";
    defparam PLLInst_0.DPHASE_SOURCE = "DISABLED";
    defparam PLLInst_0.STDBY_ENABLE = "DISABLED";
    defparam PLLInst_0.PLLRST_ENA = "ENABLED";
    defparam PLLInst_0.INTFB_WAKE = "DISABLED";
    GSR GSR_INST (.GSR(VCC_net));
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    VHI i85 (.Z(VCC_net));
    
endmodule
module pll_double (CLKI, RST, CLKOP, CLKOS, CLKOS2, LOCK);

    input CLKI;
    input RST;
    output CLKOP;
    output CLKOS;
    output CLKOS2;
    output LOCK;
    
    wire CLKI;
    wire CLKOP;
    wire CLKOS;
    wire CLKOS2;
    
    wire scuba_vlo, VCC_net;
    
    VLO scuba_vlo_inst (.Z(scuba_vlo));
    EHXPLLM PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP), .PHASESEL0(scuba_vlo), 
            .PHASESEL1(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), 
            .PHASELOADREG(scuba_vlo), .USRSTDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), 
            .RST(RST), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), 
            .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP), .CLKOS(CLKOS), .CLKOS2(CLKOS2), 
            .LOCK(LOCK));
    defparam PLLInst_0.FIN = "100.0000";
    defparam PLLInst_0.CLKI_DIV = 5;
    defparam PLLInst_0.CLKFB_DIV = 16;
    defparam PLLInst_0.CLKOP_DIV = 3;
    defparam PLLInst_0.CLKOS_DIV = 3;
    defparam PLLInst_0.CLKOS2_DIV = 1;
    defparam PLLInst_0.CLKOS3_DIV = 1;
    defparam PLLInst_0.CLKOP_ENABLE = "ENABLED";
    defparam PLLInst_0.CLKOS_ENABLE = "ENABLED";
    defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED";
    defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED";
    defparam PLLInst_0.CLKOP_CPHASE = 2;
    defparam PLLInst_0.CLKOS_CPHASE = 2;
    defparam PLLInst_0.CLKOS2_CPHASE = 0;
    defparam PLLInst_0.CLKOS3_CPHASE = 0;
    defparam PLLInst_0.CLKOP_FPHASE = 0;
    defparam PLLInst_0.CLKOS_FPHASE = 6;
    defparam PLLInst_0.CLKOS2_FPHASE = 0;
    defparam PLLInst_0.CLKOS3_FPHASE = 0;
    defparam PLLInst_0.FEEDBK_PATH = "CLKOP";
    defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING";
    defparam PLLInst_0.CLKOP_TRIM_DELAY = 0;
    defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING";
    defparam PLLInst_0.CLKOS_TRIM_DELAY = 0;
    defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA";
    defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB";
    defparam PLLInst_0.OUTDIVIDER_MUXC = "REFCLK";
    defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD";
    defparam PLLInst_0.PLL_LOCK_MODE = 0;
    defparam PLLInst_0.PLL_LOCK_DELAY = 200;
    defparam PLLInst_0.REFIN_RESET = "DISABLED";
    defparam PLLInst_0.SYNC_ENABLE = "DISABLED";
    defparam PLLInst_0.INT_LOCK_STICKY = "ENABLED";
    defparam PLLInst_0.DPHASE_SOURCE = "DISABLED";
    defparam PLLInst_0.STDBY_ENABLE = "DISABLED";
    defparam PLLInst_0.PLLRST_ENA = "ENABLED";
    defparam PLLInst_0.INTFB_WAKE = "DISABLED";
    GSR GSR_INST (.GSR(VCC_net));
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    VHI i85 (.Z(VCC_net));
    
endmodule