data/full_repos/permissive/168395472/labs/05_bin_display/clk_div.v
data/verilator_xmls/457196ea-d60b-4683-b740-ec6b457ae395.xml
module clk_div(
    input clk,

    output clk2
);

reg [11:0]cnt = 0;

assign clk2 = cnt[11];

always @(posedge clk) begin
    cnt <= cnt + 12'b1;
end

endmodule
module clk_div(
    input clk,

    output clk2
);


reg [11:0]cnt = 0;

assign clk2 = cnt[11];

always @(posedge clk) begin
    cnt <= cnt + 12'b1;
end

endmodule