data/full_repos/permissive/154590168/rtl_cpu/RegFile.v
data/verilator_xmls/c72c6625-0b83-468b-b1c6-77a4ab7673be.xml
module  RegFile (
    input           clock,
    input   [4:0]   waddr,
    input   [15:0]  wdata,
    input           we_byte,
    input           we_word,
    input           re_word,
    input   [4:0]   raddr_a,
    input   [4:0]   raddr_b,
    output  [15:0]  rdata_a,
    output  [7:0]   rdata_b
);


reg [7:0]   regf[0:31];
wire        we_l;
wire        we_h;
wire[4:0]   waddr_l;
wire[4:0]   waddr_h;
wire[4:0]   raddr_a_l;
wire[4:0]   raddr_a_h;
wire[7:0]   rdata_a_l;
wire[7:0]   rdata_a_h;


assign  we_l = we_word | (we_byte & (waddr[0] == 1'b0));
assign  we_h = we_word | (we_byte & (waddr[0] == 1'b1));

assign  waddr_l = {waddr[4:1], 1'b0};
assign  waddr_h = {waddr[4:1], 1'b1};

always @(posedge clock) begin
    if (we_l) begin
        regf[waddr_l] <= wdata[7:0];
    end
    if (we_h) begin
        regf[waddr_h] <= we_word ? wdata[15:8] : wdata[7:0];
    end
end


assign  raddr_a_l = {raddr_a[4:1], 1'b0};
assign  raddr_a_h = {raddr_a[4:1], 1'b1};

assign  rdata_a_l = regf[raddr_a_l];
assign  rdata_a_h = regf[raddr_a_h];

assign  rdata_a = re_word              ? {rdata_a_h, rdata_a_l}
                : (raddr_a[0] == 1'b0) ? {8'h00, rdata_a_l}
                :                        {8'h00, rdata_a_h};


assign  rdata_b = regf[raddr_b];

endmodule
module  RegFile (
    input           clock,
    input   [4:0]   waddr,
    input   [15:0]  wdata,
    input           we_byte,
    input           we_word,
    input           re_word,
    input   [4:0]   raddr_a,
    input   [4:0]   raddr_b,
    output  [15:0]  rdata_a,
    output  [7:0]   rdata_b
);



reg [7:0]   regf[0:31];
wire        we_l;
wire        we_h;
wire[4:0]   waddr_l;
wire[4:0]   waddr_h;
wire[4:0]   raddr_a_l;
wire[4:0]   raddr_a_h;
wire[7:0]   rdata_a_l;
wire[7:0]   rdata_a_h;


assign  we_l = we_word | (we_byte & (waddr[0] == 1'b0));
assign  we_h = we_word | (we_byte & (waddr[0] == 1'b1));

assign  waddr_l = {waddr[4:1], 1'b0};
assign  waddr_h = {waddr[4:1], 1'b1};

always @(posedge clock) begin
    if (we_l) begin
        regf[waddr_l] <= wdata[7:0];
    end
    if (we_h) begin
        regf[waddr_h] <= we_word ? wdata[15:8] : wdata[7:0];
    end
end


assign  raddr_a_l = {raddr_a[4:1], 1'b0};
assign  raddr_a_h = {raddr_a[4:1], 1'b1};

assign  rdata_a_l = regf[raddr_a_l];
assign  rdata_a_h = regf[raddr_a_h];

assign  rdata_a = re_word              ? {rdata_a_h, rdata_a_l}
                : (raddr_a[0] == 1'b0) ? {8'h00, rdata_a_l}
                :                        {8'h00, rdata_a_h};


assign  rdata_b = regf[raddr_b];

endmodule