data/full_repos/permissive/177289247/seg7x16.v
1: b'%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:69: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance seg7x16\n            0:  charToDisplay = inputDataReg[3:0];\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:70: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance seg7x16\n            1:  charToDisplay = inputDataReg[7:4];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:71: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance seg7x16\n            2:  charToDisplay = inputDataReg[11:8];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:72: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance seg7x16\n            3:  charToDisplay = inputDataReg[15:12];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:73: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance seg7x16\n            4:  charToDisplay = inputDataReg[19:16];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:74: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance seg7x16\n            5:  charToDisplay = inputDataReg[23:20];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:75: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance seg7x16\n            6:  charToDisplay = inputDataReg[27:24];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:76: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance seg7x16\n            7:  charToDisplay = inputDataReg[31:28];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h5\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h6\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h7\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'ha\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hb\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hd\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'he\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/177289247/seg7x16.v:97: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hf\' generates 4 bits.\n                                                                 : ... In instance seg7x16\n            case(charToDisplay)\n            ^~~~\n%Error: Exiting due to 24 warning(s)\n'
module seg7x16 (
    input CLK,
    input RST,

    input [31:0] inputData,
    output  [7:0] tubeChar,
    output  [7:0] tubeSelect
);

    reg [31:0] inputDataReg;
    reg [14:0] cnt;
    reg [2:0] tubeAddress;
    reg [7:0] tubeSelectReg;
    reg [7:0] charToDisplay;
    reg [7:0] tubeDisplayReg;
    wire tubeClock = cnt[14];
    assign tubeSelect  = tubeSelectReg;
    assign tubeChar = tubeDisplayReg;




    always @ (posedge CLK, posedge RST) begin
        if (RST)
            cnt <= 0;
        else
            cnt <= cnt + 1'b1;
    end



    always @ (posedge CLK, posedge RST) begin
        if(RST)
            inputDataReg <= 0;
        else
            inputDataReg <= inputData;
    end



    always @ (posedge tubeClock, posedge RST) begin
        if(RST)
            tubeAddress <= 0;
        else
            tubeAddress <= tubeAddress + 1'b1;
    end



    always @ (*) begin
        case(tubeAddress)
            7:  tubeSelectReg = 8'b01111111;
            6:  tubeSelectReg = 8'b10111111;
            5:  tubeSelectReg = 8'b11011111;
            4:  tubeSelectReg = 8'b11101111;
            3:  tubeSelectReg = 8'b11110111;
            2:  tubeSelectReg = 8'b11111011;
            1:  tubeSelectReg = 8'b11111101;
            0:  tubeSelectReg = 8'b11111110;
        endcase
    end




    always @ (*) begin
        case(tubeAddress)
            0:  charToDisplay = inputDataReg[3:0];
            1:  charToDisplay = inputDataReg[7:4];
            2:  charToDisplay = inputDataReg[11:8];
            3:  charToDisplay = inputDataReg[15:12];
            4:  charToDisplay = inputDataReg[19:16];
            5:  charToDisplay = inputDataReg[23:20];
            6:  charToDisplay = inputDataReg[27:24];
            7:  charToDisplay = inputDataReg[31:28];
        endcase
    end














    always @ (posedge CLK, posedge RST) begin
        if(RST)
            tubeDisplayReg <= 8'hff;
        else begin
            case(charToDisplay)
                4'h0:   tubeDisplayReg <= 8'hC0;
                4'h1:   tubeDisplayReg <= 8'hF9;
                4'h2:   tubeDisplayReg <= 8'hA4;
                4'h3:   tubeDisplayReg <= 8'hB0;
                4'h4:   tubeDisplayReg <= 8'h99;
                4'h5:   tubeDisplayReg <= 8'h92;
                4'h6:   tubeDisplayReg <= 8'h82;
                4'h7:   tubeDisplayReg <= 8'hF8;
                4'h8:   tubeDisplayReg <= 8'h80;
                4'h9:   tubeDisplayReg <= 8'h90;
                4'hA:   tubeDisplayReg <= 8'h88;
                4'hB:   tubeDisplayReg <= 8'h83;
                4'hC:   tubeDisplayReg <= 8'hC6;
                4'hD:   tubeDisplayReg <= 8'hA1;
                4'hE:   tubeDisplayReg <= 8'h86;
                4'hF:   tubeDisplayReg <= 8'h8E;
            endcase
        end
    end


endmodule
module seg7x16 (
    input CLK,
    input RST,

    input [31:0] inputData,
    output  [7:0] tubeChar,
    output  [7:0] tubeSelect
);


    reg [31:0] inputDataReg;
    reg [14:0] cnt;
    reg [2:0] tubeAddress;
    reg [7:0] tubeSelectReg;
    reg [7:0] charToDisplay;
    reg [7:0] tubeDisplayReg;
    wire tubeClock = cnt[14];
    assign tubeSelect  = tubeSelectReg;
    assign tubeChar = tubeDisplayReg;




    always @ (posedge CLK, posedge RST) begin
        if (RST)
            cnt <= 0;
        else
            cnt <= cnt + 1'b1;
    end



    always @ (posedge CLK, posedge RST) begin
        if(RST)
            inputDataReg <= 0;
        else
            inputDataReg <= inputData;
    end



    always @ (posedge tubeClock, posedge RST) begin
        if(RST)
            tubeAddress <= 0;
        else
            tubeAddress <= tubeAddress + 1'b1;
    end



    always @ (*) begin
        case(tubeAddress)
            7:  tubeSelectReg = 8'b01111111;
            6:  tubeSelectReg = 8'b10111111;
            5:  tubeSelectReg = 8'b11011111;
            4:  tubeSelectReg = 8'b11101111;
            3:  tubeSelectReg = 8'b11110111;
            2:  tubeSelectReg = 8'b11111011;
            1:  tubeSelectReg = 8'b11111101;
            0:  tubeSelectReg = 8'b11111110;
        endcase
    end




    always @ (*) begin
        case(tubeAddress)
            0:  charToDisplay = inputDataReg[3:0];
            1:  charToDisplay = inputDataReg[7:4];
            2:  charToDisplay = inputDataReg[11:8];
            3:  charToDisplay = inputDataReg[15:12];
            4:  charToDisplay = inputDataReg[19:16];
            5:  charToDisplay = inputDataReg[23:20];
            6:  charToDisplay = inputDataReg[27:24];
            7:  charToDisplay = inputDataReg[31:28];
        endcase
    end














    always @ (posedge CLK, posedge RST) begin
        if(RST)
            tubeDisplayReg <= 8'hff;
        else begin
            case(charToDisplay)
                4'h0:   tubeDisplayReg <= 8'hC0;
                4'h1:   tubeDisplayReg <= 8'hF9;
                4'h2:   tubeDisplayReg <= 8'hA4;
                4'h3:   tubeDisplayReg <= 8'hB0;
                4'h4:   tubeDisplayReg <= 8'h99;
                4'h5:   tubeDisplayReg <= 8'h92;
                4'h6:   tubeDisplayReg <= 8'h82;
                4'h7:   tubeDisplayReg <= 8'hF8;
                4'h8:   tubeDisplayReg <= 8'h80;
                4'h9:   tubeDisplayReg <= 8'h90;
                4'hA:   tubeDisplayReg <= 8'h88;
                4'hB:   tubeDisplayReg <= 8'h83;
                4'hC:   tubeDisplayReg <= 8'hC6;
                4'hD:   tubeDisplayReg <= 8'hA1;
                4'hE:   tubeDisplayReg <= 8'h86;
                4'hF:   tubeDisplayReg <= 8'h8E;
            endcase
        end
    end


endmodule