data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v
1: b'%Error: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v:3: Cannot find include file: accelerator.v\n`include "accelerator.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab,data/full_repos/permissive/198139336/accelerator.v\n             data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab,data/full_repos/permissive/198139336/accelerator.v.v\n             data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab,data/full_repos/permissive/198139336/accelerator.v.sv\n             accelerator.v\n             accelerator.v.v\n             accelerator.v.sv\n             obj_dir/accelerator.v\n             obj_dir/accelerator.v.v\n             obj_dir/accelerator.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v:18: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v:21: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("square_wave.fsdb");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v:22: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v:128: Unsupported: Ignoring delay on this delayed statement.\n #12;\n ^\n%Error: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v:132: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v:139: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v:142: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v:146: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v:148: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/198139336/DD_Lab9/Testzone/lab/Acctb.v:154: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 9 error(s), 2 warning(s)\n'
module tb;

reg clk, rst_n;
reg wen, start_run;
wire bsy;
reg [31:0] addr, din;
wire [31:0] dout;

reg [31:0] in [0:63];
reg [31:0] correct_out [0:63];
reg error;
integer i;

initial clk =1;
always #5 clk = ~clk;

initial begin
	$dumpfile("square_wave.fsdb");
	$dumpvars;

end

accelerator accelerator(
  .clk(clk),
  .rst_n(rst_n),
  .wen(wen),
  .start(start_run),
  .addr(addr),
  .din(din),
  .dout(dout),
  .bsy(bsy)


);


initial begin

	for (i=0;i<16;i=i+1) begin


		correct_out[0] = 32'h3e000000;
		
		correct_out[1] = 32'h41000000;
		correct_out[2] = 32'h41d80000;
		correct_out[3] = 32'h42800000;
		correct_out[4] = 32'h42fa0000;
		correct_out[5] = 32'h43580000;
		correct_out[6] = 32'h43ab8000;
		correct_out[7] = 32'h44000000;
		correct_out[8] = 32'h44364000;
		correct_out[9] = 32'h447a0000;
		correct_out[10] = 32'h44a66000;
		correct_out[11] = 32'h44d80000;
		correct_out[12] = 32'h45095000;
		correct_out[13] = 32'h452b8000;
		correct_out[14] = 32'h4552f000;
		correct_out[15] = 32'h45800000;


	end
	

    in[0] = 32'h3f000000;
    in[1] = 32'h40000000;
    in[2] = 32'h40400000;
	in[3] = 32'h40800000;
    in[4] = 32'h40a00000;
    in[5] = 32'h40c00000;
	in[6] = 32'h40e00000;
    in[7] = 32'h41000000;
    in[8] = 32'h41100000;
	in[9] = 32'h41200000;
    in[10] = 32'h41300000;
    in[11] = 32'h41400000;
	in[12] = 32'h41500000;
    in[13] = 32'h41600000;
    in[14] = 32'h41700000;
	in[15] = 32'h41800000;



	error = 0;
	

	$display("input values");
	addr = 1'b0;
	start_run = 1'b0;
	rst_n = 1'b0;
	wen = 1'b0;
	#12;
	rst_n = 1'b1;
	
	for (i=0;i<16;i=i+1) begin
		@(posedge clk);
		din = in[i];
		addr = i*4;
		wen = 1'b1;
	end
	
	$display("start run");
	@(posedge clk);
	wen = 1'b0;
	start_run = 1'b1;
	@(posedge clk);
	start_run = 1'b0;
	
	$display("polling busy");
	@(posedge clk);
	while (bsy!=1'b0) begin
		@(posedge clk);
	end
	
	$display("get output");
	for (i=0;i<16;i=i+1) begin
	    addr = i<<2; 
		@(posedge clk);
		
		@(posedge clk);


        $display("output = %h",dout);
		if(dout!=correct_out[i]) begin
			$display("ERROR at address:%d dout:%h correct:%h",addr,dout,correct_out[i]);
			error =1;
		end
		
	end
	if (!error)  begin
		$display("========================");
		$display("=        PASS          =");
		$display("========================");
	end
	$finish;
end
endmodule
module tb;


reg clk, rst_n;
reg wen, start_run;
wire bsy;
reg [31:0] addr, din;
wire [31:0] dout;

reg [31:0] in [0:63];
reg [31:0] correct_out [0:63];
reg error;
integer i;

initial clk =1;
always #5 clk = ~clk;

initial begin
	$dumpfile("square_wave.fsdb");
	$dumpvars;

end

accelerator accelerator(
  .clk(clk),
  .rst_n(rst_n),
  .wen(wen),
  .start(start_run),
  .addr(addr),
  .din(din),
  .dout(dout),
  .bsy(bsy)


);


initial begin

	for (i=0;i<16;i=i+1) begin


		correct_out[0] = 32'h3e000000;
		
		correct_out[1] = 32'h41000000;
		correct_out[2] = 32'h41d80000;
		correct_out[3] = 32'h42800000;
		correct_out[4] = 32'h42fa0000;
		correct_out[5] = 32'h43580000;
		correct_out[6] = 32'h43ab8000;
		correct_out[7] = 32'h44000000;
		correct_out[8] = 32'h44364000;
		correct_out[9] = 32'h447a0000;
		correct_out[10] = 32'h44a66000;
		correct_out[11] = 32'h44d80000;
		correct_out[12] = 32'h45095000;
		correct_out[13] = 32'h452b8000;
		correct_out[14] = 32'h4552f000;
		correct_out[15] = 32'h45800000;


	end
	

    in[0] = 32'h3f000000;
    in[1] = 32'h40000000;
    in[2] = 32'h40400000;
	in[3] = 32'h40800000;
    in[4] = 32'h40a00000;
    in[5] = 32'h40c00000;
	in[6] = 32'h40e00000;
    in[7] = 32'h41000000;
    in[8] = 32'h41100000;
	in[9] = 32'h41200000;
    in[10] = 32'h41300000;
    in[11] = 32'h41400000;
	in[12] = 32'h41500000;
    in[13] = 32'h41600000;
    in[14] = 32'h41700000;
	in[15] = 32'h41800000;



	error = 0;
	

	$display("input values");
	addr = 1'b0;
	start_run = 1'b0;
	rst_n = 1'b0;
	wen = 1'b0;
	#12;
	rst_n = 1'b1;
	
	for (i=0;i<16;i=i+1) begin
		@(posedge clk);
		din = in[i];
		addr = i*4;
		wen = 1'b1;
	end
	
	$display("start run");
	@(posedge clk);
	wen = 1'b0;
	start_run = 1'b1;
	@(posedge clk);
	start_run = 1'b0;
	
	$display("polling busy");
	@(posedge clk);
	while (bsy!=1'b0) begin
		@(posedge clk);
	end
	
	$display("get output");
	for (i=0;i<16;i=i+1) begin
	    addr = i<<2; 
		@(posedge clk);
		
		@(posedge clk);


        $display("output = %h",dout);
		if(dout!=correct_out[i]) begin
			$display("ERROR at address:%d dout:%h correct:%h",addr,dout,correct_out[i]);
			error =1;
		end
		
	end
	if (!error)  begin
		$display("========================");
		$display("=        PASS          =");
		$display("========================");
	end
	$finish;
end
endmodule