data/full_repos/permissive/158824477/submodules/PulseRain_MCU/memory/lattice/MXO2_4K/dual_port_ram.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/memory/lattice/MXO2_4K/dual_port_ram.v:33: Cannot find file containing module: 'dual_port_ram_lattice'\n    dual_port_ram_lattice #(.ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH)) dual_port_ram_lattice_i (\n    ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/memory/lattice/MXO2_4K,data/full_repos/permissive/158824477/dual_port_ram_lattice\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/memory/lattice/MXO2_4K,data/full_repos/permissive/158824477/dual_port_ram_lattice.v\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/memory/lattice/MXO2_4K,data/full_repos/permissive/158824477/dual_port_ram_lattice.sv\n             dual_port_ram_lattice\n             dual_port_ram_lattice.v\n             dual_port_ram_lattice.sv\n             obj_dir/dual_port_ram_lattice\n             obj_dir/dual_port_ram_lattice.v\n             obj_dir/dual_port_ram_lattice.sv\n%Error: Exiting due to 1 error(s)\n"
module dual_port_ram #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) (
          input wire [ADDR_WIDTH - 1 : 0]       waddr, 
          input wire [ADDR_WIDTH - 1 : 0]       raddr,
          
          input wire [DATA_WIDTH - 1 : 0]       din,
          input wire                            write_en, 
          input wire                            clk, 
          output wire [DATA_WIDTH - 1 : 0]      dout
);


    dual_port_ram_lattice #(.ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH)) dual_port_ram_lattice_i (
            .waddr (waddr),
            .raddr (raddr),
            
            .din (din),
            .write_en (write_en),
            
            .wclk (clk),
            .rclk (clk),
            .dout (dout) );
            
endmodule
module dual_port_ram #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) (
          input wire [ADDR_WIDTH - 1 : 0]       waddr, 
          input wire [ADDR_WIDTH - 1 : 0]       raddr,
          
          input wire [DATA_WIDTH - 1 : 0]       din,
          input wire                            write_en, 
          input wire                            clk, 
          output wire [DATA_WIDTH - 1 : 0]      dout
);



    dual_port_ram_lattice #(.ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH)) dual_port_ram_lattice_i (
            .waddr (waddr),
            .raddr (raddr),
            
            .din (din),
            .write_en (write_en),
            
            .wclk (clk),
            .rclk (clk),
            .dout (dout) );
            
endmodule