data/full_repos/permissive/143278/fpga_tests/ge2.v
data/verilator_xmls/9fb10079-af01-483a-829f-948a5e27b27a.xml
module ge2(output wire out, input wire [1:0] A, input wire [1:0] B);

   assign out = A >= B;

endmodule
module ge2(output wire out, input wire [1:0] A, input wire [1:0] B);


   assign out = A >= B;

endmodule