data/full_repos/permissive/143278/ivltests/signed8.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/signed8.v:46: Unsupported: Ignoring delay on this delayed statement.\n         #1 if(p !== prod[15:0]) begin\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed8.v:26: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 5 bits.\n                                                                       : ... In instance test_mult.dut\nassign ta = a;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed8.v:29: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'pt\' generates 13 bits.\n                                                                       : ... In instance test_mult.dut\nassign p=pt;\n        ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_mult;

integer a,b, prod;

wire [15:0] p;
mult58s dut(a[4:0], b[7:0], p);

initial begin
   for(a = 0; a < (1<<5); a=a+1 )
     for(b=-127; b<128; b=b+1)
       begin
         prod = a * b;
         #1 if(p !== prod[15:0]) begin
            $display("Error Miscompare with a=%h, b=%h expect = %0d (%h) acutal = %h",
					a[4:0], b[7:0], prod, prod[15:0], p);
            $finish;
         end

       end

   $display("PASSED");
end

endmodule
module test_mult;


integer a,b, prod;

wire [15:0] p;
mult58s dut(a[4:0], b[7:0], p);

initial begin
   for(a = 0; a < (1<<5); a=a+1 )
     for(b=-127; b<128; b=b+1)
       begin
         prod = a * b;
         #1 if(p !== prod[15:0]) begin
            $display("Error Miscompare with a=%h, b=%h expect = %0d (%h) acutal = %h",
					a[4:0], b[7:0], prod, prod[15:0], p);
            $finish;
         end

       end

   $display("PASSED");
end

endmodule