data/full_repos/permissive/169225814/modules/uarts/rtl/uarts.v
1: b'%Error: data/full_repos/permissive/169225814/modules/uarts/rtl/uarts.v:59: Cannot find include file: uarts_params.v\n  `include "uarts_params.v" \n           ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169225814/modules/uarts/rtl,data/full_repos/permissive/169225814/uarts_params.v\n             data/full_repos/permissive/169225814/modules/uarts/rtl,data/full_repos/permissive/169225814/uarts_params.v.v\n             data/full_repos/permissive/169225814/modules/uarts/rtl,data/full_repos/permissive/169225814/uarts_params.v.sv\n             uarts_params.v\n             uarts_params.v.v\n             uarts_params.v.sv\n             obj_dir/uarts_params.v\n             obj_dir/uarts_params.v.v\n             obj_dir/uarts_params.v.sv\n%Error: Exiting due to 1 error(s)\n'
module uarts (

  input  wire        hclk,
  input  wire        hresetn,


  output wire [31:0] rx_data,
  output wire        rx_irq,
  input  wire [31:0] tx_data,
  input wire         tx_send,
  output wire        tx_irq,


  input  wire [31:0] uarts_baud,
  input  wire [31:0] uarts_ctl,




  output wire        TX,
  input  wire        RX

);






  `include "uarts_params.v"


wire        start_bit_det;
wire [7:0]  uarts_plw;
wire [7:0]  uarts_dw;

reg [31:0]  baud_clk_cnt;
reg [7:0]   bit_cnt;
reg         poll_start_bit;
reg         sample_data_bit;

reg         rx_d1;
reg         rx_d2;
reg         rx_d3;









assign uarts_dw = (uarts_ctl[1:0] == 2'b10) ?
                                             ((uarts_ctl[1:0] == 2'b01) ?
                                                                          8'b0001_0000
                                                                        : 8'b0010_0000)
                                            : 8'b0000_1000;








assign uarts_plw = (uarts_ctl[1:0] == 2'b10) ?
                                             ((uarts_ctl[1:0] == 2'b01) ?
                                                                          ({7'b0001_001, uarts_ctl[2]})
                                                                        : ({7'b0010_001, uarts_ctl[2]}))
                                            : ({7'b0000_101, uarts_ctl[2]});




   always @ (posedge hclk or negedge hresetn) begin
     if (hresetn == 1'b0) begin
        rx_d1 <= 1'b1;
        rx_d2 <= 1'b1;
        rx_d3 <= 1'b1;
     end
     else begin
        rx_d1 <= RX;
        rx_d2 <= rx_d1;
        rx_d3 <= rx_d2;
     end
   end




   assign start_bit_det = poll_start_bit ? (~rx_d3 & ~RX) : 1'b0;

   always @ (posedge hclk or negedge hresetn) begin
     if (hresetn == 1'b0) begin
       baud_clk_cnt    <= 32'b0;
       poll_start_bit  <= 1'b1;
       sample_data_bit <= 1'b0;
     end
     else begin
       if ((bit_cnt  == 8'b0) && (baud_clk_cnt == {1'b0, uarts_baud[31:1]})) begin
         baud_clk_cnt <= 32'b0;
       end
       else if (start_bit_det == 1'b1) begin
         baud_clk_cnt   <= baud_clk_cnt + 1;
         poll_start_bit <= 1'b0;
       end
       else if ((bit_cnt == uarts_plw[7:0]) || (poll_start_bit == 1'b1)) begin
         baud_clk_cnt    <= 32'b0;
         poll_start_bit  <= 1'b1;
         sample_data_bit <= 1'b0;
       end
       else if ((baud_clk_cnt == uarts_baud)) begin
         baud_clk_cnt    <= 32'b0;
         sample_data_bit <= 1'b1;
       end
       else begin
         baud_clk_cnt    <= baud_clk_cnt + 1;
         sample_data_bit <= 1'b0;
       end
     end
   end

   always @ (posedge hclk or negedge hresetn) begin
     if (hresetn == 1'b0) begin
       bit_cnt <= 8'b0;
     end
     else begin
       if ((bit_cnt  == 8'b0) && (baud_clk_cnt == {1'b0, uarts_baud[31:1]})) begin
         bit_cnt <= bit_cnt + 1;
       end
       else if ((bit_cnt == uarts_plw[7:0]) || (poll_start_bit == 1'b1)) begin
         bit_cnt <= 8'b0;
       end
       else if (sample_data_bit == 1'b1) begin
         bit_cnt <= bit_cnt + 1;
       end
     end
   end
 


uarts_rx u_uarts_rx_inst (
  .hclk             (hclk),
  .hresetn          (hresetn),
  .uarts_baud       (uarts_baud),
  .uarts_ctl        (uarts_ctl),
  .sample_data_bit  (sample_data_bit),
  .bit_cnt          (bit_cnt),
  .uarts_dw         (uarts_dw),
  .uarts_plw        (uarts_plw),
  .RX               (RX),
  .rx_irq           (rx_irq),
  .rx_data          (rx_data)

);

uarts_tx u_uarts_tx_inst (
  .hclk           (hclk),
  .hresetn        (hresetn),
  .tx_send        (tx_send),
  .tx_data        (tx_data),
  .uarts_baud     (uarts_baud),
  .uarts_ctl      (uarts_ctl),
  .uarts_dw       (uarts_dw),
  .uarts_plw      (uarts_plw),
  .tx_irq         (tx_irq),
  .TX             (TX)

);



endmodule
module uarts (

  input  wire        hclk,
  input  wire        hresetn,


  output wire [31:0] rx_data,
  output wire        rx_irq,
  input  wire [31:0] tx_data,
  input wire         tx_send,
  output wire        tx_irq,


  input  wire [31:0] uarts_baud,
  input  wire [31:0] uarts_ctl,




  output wire        TX,
  input  wire        RX

);







  `include "uarts_params.v"


wire        start_bit_det;
wire [7:0]  uarts_plw;
wire [7:0]  uarts_dw;

reg [31:0]  baud_clk_cnt;
reg [7:0]   bit_cnt;
reg         poll_start_bit;
reg         sample_data_bit;

reg         rx_d1;
reg         rx_d2;
reg         rx_d3;









assign uarts_dw = (uarts_ctl[1:0] == 2'b10) ?
                                             ((uarts_ctl[1:0] == 2'b01) ?
                                                                          8'b0001_0000
                                                                        : 8'b0010_0000)
                                            : 8'b0000_1000;








assign uarts_plw = (uarts_ctl[1:0] == 2'b10) ?
                                             ((uarts_ctl[1:0] == 2'b01) ?
                                                                          ({7'b0001_001, uarts_ctl[2]})
                                                                        : ({7'b0010_001, uarts_ctl[2]}))
                                            : ({7'b0000_101, uarts_ctl[2]});




   always @ (posedge hclk or negedge hresetn) begin
     if (hresetn == 1'b0) begin
        rx_d1 <= 1'b1;
        rx_d2 <= 1'b1;
        rx_d3 <= 1'b1;
     end
     else begin
        rx_d1 <= RX;
        rx_d2 <= rx_d1;
        rx_d3 <= rx_d2;
     end
   end




   assign start_bit_det = poll_start_bit ? (~rx_d3 & ~RX) : 1'b0;

   always @ (posedge hclk or negedge hresetn) begin
     if (hresetn == 1'b0) begin
       baud_clk_cnt    <= 32'b0;
       poll_start_bit  <= 1'b1;
       sample_data_bit <= 1'b0;
     end
     else begin
       if ((bit_cnt  == 8'b0) && (baud_clk_cnt == {1'b0, uarts_baud[31:1]})) begin
         baud_clk_cnt <= 32'b0;
       end
       else if (start_bit_det == 1'b1) begin
         baud_clk_cnt   <= baud_clk_cnt + 1;
         poll_start_bit <= 1'b0;
       end
       else if ((bit_cnt == uarts_plw[7:0]) || (poll_start_bit == 1'b1)) begin
         baud_clk_cnt    <= 32'b0;
         poll_start_bit  <= 1'b1;
         sample_data_bit <= 1'b0;
       end
       else if ((baud_clk_cnt == uarts_baud)) begin
         baud_clk_cnt    <= 32'b0;
         sample_data_bit <= 1'b1;
       end
       else begin
         baud_clk_cnt    <= baud_clk_cnt + 1;
         sample_data_bit <= 1'b0;
       end
     end
   end

   always @ (posedge hclk or negedge hresetn) begin
     if (hresetn == 1'b0) begin
       bit_cnt <= 8'b0;
     end
     else begin
       if ((bit_cnt  == 8'b0) && (baud_clk_cnt == {1'b0, uarts_baud[31:1]})) begin
         bit_cnt <= bit_cnt + 1;
       end
       else if ((bit_cnt == uarts_plw[7:0]) || (poll_start_bit == 1'b1)) begin
         bit_cnt <= 8'b0;
       end
       else if (sample_data_bit == 1'b1) begin
         bit_cnt <= bit_cnt + 1;
       end
     end
   end
 


uarts_rx u_uarts_rx_inst (
  .hclk             (hclk),
  .hresetn          (hresetn),
  .uarts_baud       (uarts_baud),
  .uarts_ctl        (uarts_ctl),
  .sample_data_bit  (sample_data_bit),
  .bit_cnt          (bit_cnt),
  .uarts_dw         (uarts_dw),
  .uarts_plw        (uarts_plw),
  .RX               (RX),
  .rx_irq           (rx_irq),
  .rx_data          (rx_data)

);

uarts_tx u_uarts_tx_inst (
  .hclk           (hclk),
  .hresetn        (hresetn),
  .tx_send        (tx_send),
  .tx_data        (tx_data),
  .uarts_baud     (uarts_baud),
  .uarts_ctl      (uarts_ctl),
  .uarts_dw       (uarts_dw),
  .uarts_plw      (uarts_plw),
  .tx_irq         (tx_irq),
  .TX             (TX)

);



endmodule