data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0403/lab0403.srcs/sources_1/new/signext.v
data/verilator_xmls/82fc237e-7e63-49b1-9dd2-8149a3e061cf.xml
module signext(
    input [15:0] inst,
    output reg [31:0] data
    );
        
    always@(inst)
    begin
        if(inst[15]==1)
        begin
            data[31:16]=16'hffff;
        end
        else
        begin
            data[31:16]=16'h0000;
        end
        data[15:0]=inst[15:0];        
    end    
    
endmodule
module signext(
    input [15:0] inst,
    output reg [31:0] data
    );

        
    always@(inst)
    begin
        if(inst[15]==1)
        begin
            data[31:16]=16'hffff;
        end
        else
        begin
            data[31:16]=16'h0000;
        end
        data[15:0]=inst[15:0];        
    end    
    
endmodule