data/full_repos/permissive/163954962/lab22.v
 line:4: before: "="
1: b'%Warning-IMPLICIT: data/full_repos/permissive/163954962/lab22.v:265: Signal definition not found, creating implicitly: \'CLK_div\'\n divfreq F0 (CLK, CLK_div);\n                  ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/163954962/lab22.v:266: Signal definition not found, creating implicitly: \'CLK_div2\'\n                                                                   : ... Suggested alternative: \'CLK_div\'\n divfreq2 F1 (CLK, CLK_div2);\n                   ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/163954962/lab22.v:267: Signal definition not found, creating implicitly: \'CLK_div_change\'\n divfreq_change F4 (CLK, CLK_div_change);\n                         ^~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:124: Little bit endian vector: MSB < LSB of bit range: 0:3\n parameter logic [0:3] tetris [0:111] = \'{ \n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:10: Little bit endian vector: MSB < LSB of bit range: 0:7\n   output reg [0:7] level = 8\'b00000000,\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:11: Little bit endian vector: MSB < LSB of bit range: 0:6\n   output reg [0:6] z = 7\'b0000001,\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:17: Little bit endian vector: MSB < LSB of bit range: 0:7\n var bit [0:7] blank = 8\'b11111111;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:27: Little bit endian vector: MSB < LSB of bit range: 0:7\n var bit [0:7][0:7] windows_Char = \'{8\'b11111111,\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:27: Little bit endian vector: MSB < LSB of bit range: 0:7\n var bit [0:7][0:7] windows_Char = \'{8\'b11111111,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:35: Little bit endian vector: MSB < LSB of bit range: 0:11\n var bit [0:10][0:11] front_Char = \'{12\'b111111111111,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:35: Little bit endian vector: MSB < LSB of bit range: 0:10\n var bit [0:10][0:11] front_Char = \'{12\'b111111111111,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:46: Little bit endian vector: MSB < LSB of bit range: 0:11\n var bit [0:10][0:11] blank_front_Char = \'{12\'b111111111111,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:46: Little bit endian vector: MSB < LSB of bit range: 0:10\n var bit [0:10][0:11] blank_front_Char = \'{12\'b111111111111,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:57: Little bit endian vector: MSB < LSB of bit range: 0:11\n var bit [0:10][0:11] back_Char = \'{12\'b111111111111,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:57: Little bit endian vector: MSB < LSB of bit range: 0:10\n var bit [0:10][0:11] back_Char = \'{12\'b111111111111,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:68: Little bit endian vector: MSB < LSB of bit range: 0:11\n var bit [0:10][0:11] backup_Char = \'{12\'b111111111111,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:68: Little bit endian vector: MSB < LSB of bit range: 0:10\n var bit [0:10][0:11] backup_Char = \'{12\'b111111111111,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:79: Little bit endian vector: MSB < LSB of bit range: 0:11\n var bit [0:10][0:11] back_test_Char = \'{12\'b111111111111,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:79: Little bit endian vector: MSB < LSB of bit range: 0:10\n var bit [0:10][0:11] back_test_Char = \'{12\'b111111111111,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:90: Little bit endian vector: MSB < LSB of bit range: 0:11\n var bit [0:10][0:11] front_test_Char = \'{12\'b111111111111,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:90: Little bit endian vector: MSB < LSB of bit range: 0:10\n var bit [0:10][0:11] front_test_Char = \'{12\'b111111111111,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:101: Little bit endian vector: MSB < LSB of bit range: 0:11\n var bit [0:10][0:11] back_test_two_Char = \'{12\'b111111111111,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:101: Little bit endian vector: MSB < LSB of bit range: 0:10\n var bit [0:10][0:11] back_test_two_Char = \'{12\'b111111111111,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:112: Little bit endian vector: MSB < LSB of bit range: 0:11\n var bit [0:10][0:11] over_Char = \'{12\'b111111111111,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:112: Little bit endian vector: MSB < LSB of bit range: 0:10\n var bit [0:10][0:11] over_Char = \'{12\'b111111111111,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/163954962/lab22.v:274: Little bit endian vector: MSB < LSB of bit range: 0:1\n reg [0:1] rotate = 2\'b00;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/163954962/lab22.v:304: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'cnt\' generates 8 bits.\n                                                                : ... In instance lab22\n   COMM <= cnt;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/163954962/lab22.v:324: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'clean_flag\' generates 32 bits.\n                                                                : ... In instance lab22\n     if(clean_flag)\n     ^~\n%Warning-WIDTH: data/full_repos/permissive/163954962/lab22.v:346: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 132 bits.\n                                                                : ... In instance lab22\n    if(~over_Char&~back_Char)  \n    ^~\n%Warning-WIDTH: data/full_repos/permissive/163954962/lab22.v:460: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 132 bits.\n                                                                : ... In instance lab22\n     if(~front_test_Char&~back_test_Char)\n     ^~\n%Warning-WIDTH: data/full_repos/permissive/163954962/lab22.v:449: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s NOT generates 132 bits.\n                                                                : ... In instance lab22\n    else if(down && y>0 &&~(~front_test_Char&~back_test_two_Char) && dcount == 0)\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/163954962/lab22.v:483: Logical Operator IF expects 1 bit on the If, but If\'s NOT generates 132 bits.\n                                                                : ... In instance lab22\n   else if(~(~front_test_Char&~back_test_two_Char))\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/163954962/lab22.v:481: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s NOT generates 132 bits.\n                                                                : ... In instance lab22\n   if(dcount>20&&~(~front_test_Char&~back_test_two_Char))\n               ^~\n%Error: Exiting due to 33 warning(s)\n'
module divfreq(input CLK, output reg CLK_div);
reg [24:0] Count;
always @(posedge CLK)
begin
	if(Count > 2000)
		begin
			Count <= 25'b0;
			CLK_div <= ~CLK_div;
		end
		else
			Count <= Count + 1'b1;
end
endmodule
module divfreq(input CLK, output reg CLK_div);

reg [24:0] Count;
always @(posedge CLK)
begin
	if(Count > 2000)
		begin
			Count <= 25'b0;
			CLK_div <= ~CLK_div;
		end
		else
			Count <= Count + 1'b1;
end
endmodule