data/full_repos/permissive/148324174/FIFO/rptr_empty.v
1: b'%Warning-WIDTH: data/full_repos/permissive/148324174/FIFO/rptr_empty.v:26: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'rinc\' generates 1 bits.\n                                                                         : ... In instance rptr_empty\n    rbnext = (!rempty)? (rbin + rinc) : rbin;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module rptr_empty #(
    parameter ADDRSIZE = 4
    )(
    output     [ADDRSIZE-1:0] raddr,
    output reg [ADDRSIZE:0]   rptr,
    output reg                rempty,
    input      [ADDRSIZE:0]   rwptr2,
    input                     rinc, rclk, rrst
    );

reg [ADDRSIZE:0] rbin, rgnext, rbnext;


always @(posedge rclk or posedge rrst) begin
    if (rrst) begin
        rptr <= 0;
        rbin <= 0;
    end
    else begin
        rptr <= rgnext;
        rbin <= rbnext;
    end
end

always @(*) begin
    rbnext = (!rempty)? (rbin + rinc) : rbin;
    rgnext = (rbnext>>1)^rbnext;
end


assign raddr = rbin[ADDRSIZE-1:0];


always @(posedge rclk or posedge rrst) begin
    if (rrst) rempty <= 1'b1;
    else rempty <= (rgnext == rwptr2);
end

endmodule
module rptr_empty #(
    parameter ADDRSIZE = 4
    )(
    output     [ADDRSIZE-1:0] raddr,
    output reg [ADDRSIZE:0]   rptr,
    output reg                rempty,
    input      [ADDRSIZE:0]   rwptr2,
    input                     rinc, rclk, rrst
    );


reg [ADDRSIZE:0] rbin, rgnext, rbnext;


always @(posedge rclk or posedge rrst) begin
    if (rrst) begin
        rptr <= 0;
        rbin <= 0;
    end
    else begin
        rptr <= rgnext;
        rbin <= rbnext;
    end
end

always @(*) begin
    rbnext = (!rempty)? (rbin + rinc) : rbin;
    rgnext = (rbnext>>1)^rbnext;
end


assign raddr = rbin[ADDRSIZE-1:0];


always @(posedge rclk or posedge rrst) begin
    if (rrst) rempty <= 1'b1;
    else rempty <= (rgnext == rwptr2);
end

endmodule