data/full_repos/permissive/202237519/verilog/a/a_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/202237519/verilog/a/a_tb.v:1: Cannot find include file: a.v\n`include "a.v" \n         ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/a,data/full_repos/permissive/202237519/a.v\n             data/full_repos/permissive/202237519/verilog/a,data/full_repos/permissive/202237519/a.v.v\n             data/full_repos/permissive/202237519/verilog/a,data/full_repos/permissive/202237519/a.v.sv\n             a.v\n             a.v.v\n             a.v.sv\n             obj_dir/a.v\n             obj_dir/a.v.v\n             obj_dir/a.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/a/a_tb.v:11: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("a_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/a/a_tb.v:12: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,a_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/a/a_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n #1;   a <= 1\'b0; b <= 1\'b1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/a/a_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1;   a <= 1\'b1; b <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/a/a_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #1;   a <= 1\'b1; b <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/a/a_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module a_tb;

reg a,b;
wire c;

and_module A1(a,b,c);

initial begin
$dumpfile("a_tb.vcd");
$dumpvars(0,a_tb);
       a <= 1'b0; b <= 1'b0;
 #1;   a <= 1'b0; b <= 1'b1;
 #1;   a <= 1'b1; b <= 1'b0;
 #1;   a <= 1'b1; b <= 1'b1;
 #1;
 $finish;
end


endmodule
module a_tb;


reg a,b;
wire c;

and_module A1(a,b,c);

initial begin
$dumpfile("a_tb.vcd");
$dumpvars(0,a_tb);
       a <= 1'b0; b <= 1'b0;
 #1;   a <= 1'b0; b <= 1'b1;
 #1;   a <= 1'b1; b <= 1'b0;
 #1;   a <= 1'b1; b <= 1'b1;
 #1;
 $finish;
end


endmodule