data/full_repos/permissive/20430511/hardware/FPGA/wishbone/rtl/wb_store.v
 line:63: before: "="
data/verilator_xmls/8d727f52-b5e9-4048-b7e3-2dff5586af97.xml
module wb_store
  #(parameter STORE = 24,
    parameter SMAX  = STORE-1,
    parameter SBITS = 5,
    parameter SSB   = SBITS-1,
    parameter PIPED = 1,
    parameter BURST = 1,
    parameter DELAY = 3)
   (
    input          clk_i,
    input          rst_i,
    output reg     cyc_o = 1'b0,
    output reg     stb_o = 1'b0,
    output         we_o,
    input          ack_i,
    input          wat_i,
    input          rty_i,
    input          err_i,
    output [SSB:0] adr_o,

    input          store_i,
    output reg     ready_o = 1'b0
    );

   reg [SSB:0]     adr = {SBITS{1'b0}};
   wire [SBITS:0]  adr_nxt = adr + 1;
   wire            cyc_w = !err_i && !rty_i && (stb_o || !ack_i);
   wire            stb_w = stb_o && (adr < SMAX || wat_i);


   assign we_o  = cyc_o;
   assign adr_o = adr;





   always @(posedge clk_i)
     if (rst_i)
       {cyc_o, stb_o} <= #DELAY 2'b00;
     else if (store_i)
       {cyc_o, stb_o} <= #DELAY 2'b11;
     else if (cyc_o)
       {cyc_o, stb_o} <= #DELAY {cyc_w, stb_w};
     else
       {cyc_o, stb_o} <= #DELAY 2'b00;



   always @(posedge clk_i)
     if (store_i)
       adr <= #DELAY {SBITS{1'b0}};
     else if (cyc_o && !wat_i)
       adr <= #DELAY adr_nxt[SSB:0];





   always @(posedge clk_i)
     ready_o <= #DELAY cyc_o && !stb_o && ack_i;


endmodule
module wb_store
  #(parameter STORE = 24,
    parameter SMAX  = STORE-1,
    parameter SBITS = 5,
    parameter SSB   = SBITS-1,
    parameter PIPED = 1,
    parameter BURST = 1,
    parameter DELAY = 3)
   (
    input          clk_i,
    input          rst_i,
    output reg     cyc_o = 1'b0,
    output reg     stb_o = 1'b0,
    output         we_o,
    input          ack_i,
    input          wat_i,
    input          rty_i,
    input          err_i,
    output [SSB:0] adr_o,

    input          store_i,
    output reg     ready_o = 1'b0
    );


   reg [SSB:0]     adr = {SBITS{1'b0}};
   wire [SBITS:0]  adr_nxt = adr + 1;
   wire            cyc_w = !err_i && !rty_i && (stb_o || !ack_i);
   wire            stb_w = stb_o && (adr < SMAX || wat_i);


   assign we_o  = cyc_o;
   assign adr_o = adr;





   always @(posedge clk_i)
     if (rst_i)
       {cyc_o, stb_o} <= #DELAY 2'b00;
     else if (store_i)
       {cyc_o, stb_o} <= #DELAY 2'b11;
     else if (cyc_o)
       {cyc_o, stb_o} <= #DELAY {cyc_w, stb_w};
     else
       {cyc_o, stb_o} <= #DELAY 2'b00;



   always @(posedge clk_i)
     if (store_i)
       adr <= #DELAY {SBITS{1'b0}};
     else if (cyc_o && !wat_i)
       adr <= #DELAY adr_nxt[SSB:0];





   always @(posedge clk_i)
     ready_o <= #DELAY cyc_o && !stb_o && ack_i;


endmodule