data/full_repos/permissive/148324174/SeqLogic/pattern_det_tb.v
 line:16: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/pattern_det_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n #2 rst = 1\'b1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/pattern_det_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/pattern_det_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #20000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/pattern_det_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\nalways #20 clk = ~clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/pattern_det_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #2 data = {data[22:0], data[23]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/148324174/SeqLogic/pattern_det_tb.v:15: Operator ASSIGN expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'hc9094\' generates 20 bits.\n                                                                                 : ... In instance pattern_det_tb\n data = 20\'b1100_1001_0000_1001_0100;\n      ^\n%Error: data/full_repos/permissive/148324174/SeqLogic/pattern_det_tb.v:23: Cannot find file containing module: \'pattern_det\'\npattern_det U1(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/148324174/SeqLogic,data/full_repos/permissive/148324174/pattern_det\n             data/full_repos/permissive/148324174/SeqLogic,data/full_repos/permissive/148324174/pattern_det.v\n             data/full_repos/permissive/148324174/SeqLogic,data/full_repos/permissive/148324174/pattern_det.sv\n             pattern_det\n             pattern_det.v\n             pattern_det.sv\n             obj_dir/pattern_det\n             obj_dir/pattern_det.v\n             obj_dir/pattern_det.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pattern_det_tb;

reg clk, rst;
reg [23:0] data;
wire in, moore_out, mealy_out;

assign in = data[23];

initial begin
	clk = 1'b0;
	rst = 1'b0;
	#2 rst = 1'b1;
	#30 rst = 1'b0;
	data = 20'b1100_1001_0000_1001_0100;
	#20000 $finish;
end

always #20 clk = ~clk;
always @(posedge clk)
	#2 data = {data[22:0], data[23]};

pattern_det U1(
	.in(in),
	.clk(clk),
	.rst(rst),
	.moore_out(moore_out),
	.mealy_out(mealy_out)
	);

endmodule
module pattern_det_tb;


reg clk, rst;
reg [23:0] data;
wire in, moore_out, mealy_out;

assign in = data[23];

initial begin
	clk = 1'b0;
	rst = 1'b0;
	#2 rst = 1'b1;
	#30 rst = 1'b0;
	data = 20'b1100_1001_0000_1001_0100;
	#20000 $finish;
end

always #20 clk = ~clk;
always @(posedge clk)
	#2 data = {data[22:0], data[23]};

pattern_det U1(
	.in(in),
	.clk(clk),
	.rst(rst),
	.moore_out(moore_out),
	.mealy_out(mealy_out)
	);

endmodule