data/full_repos/permissive/170402453/Split8to2.v
data/verilator_xmls/ec9be4a8-ad7c-4a0c-8133-995da69a98c8.xml
module Split8to2(
		input [7:0] Bus8,
		output [3:0] Bus4_1,
		output [7:4] Bus4_2
    );
		assign Bus4_1 = Bus8[3:0];
		assign Bus4_2 = Bus8[7:4];

endmodule
module Split8to2(
		input [7:0] Bus8,
		output [3:0] Bus4_1,
		output [7:4] Bus4_2
    );

		assign Bus4_1 = Bus8[3:0];
		assign Bus4_2 = Bus8[7:4];

endmodule