data/full_repos/permissive/134057391/cpld/m6502_db/rtl/rs_latch3.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/0b5fbfe3-e6f8-4ecd-bad3-2b415eb6f1ba.xml
module rs_latch3(
    input r1_n,
    input s_n,
    input r2_n,
    output q1_n,
    output q,
    output q2_n
    );

    wire fb1, fb2, fb3;
	 
    nand u1 (fb1, r1_n, fb2);
    nand u2 (fb2, s_n, fb1, fb3);
    nand u3 (fb3, r2_n, fb2);
	 
    assign q1_n = fb1;
    assign q = fb2;
    assign q2_n = fb3;

endmodule
module rs_latch3(
    input r1_n,
    input s_n,
    input r2_n,
    output q1_n,
    output q,
    output q2_n
    );


    wire fb1, fb2, fb3;
	 
    nand u1 (fb1, r1_n, fb2);
    nand u2 (fb2, s_n, fb1, fb3);
    nand u3 (fb3, r2_n, fb2);
	 
    assign q1_n = fb1;
    assign q = fb2;
    assign q2_n = fb3;

endmodule