data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim/stream_spy.v
 line:57: before: "integer"
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim/stream_spy.v:34: Cannot find include file: stream_common.vh\n`include "stream_common.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh.sv\n             stream_common.vh\n             stream_common.vh.v\n             stream_common.vh.sv\n             obj_dir/stream_common.vh\n             obj_dir/stream_common.vh.v\n             obj_dir/stream_common.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module stream_spy (clk, rst, din_ready, din_valid, din_data, done, err);
`include "stream_common.vh"
  parameter FilenameDump  = "undefined";
  parameter FilenameRef   = "undefined";
  parameter CheckData     = 1;
  parameter NumSymbols    = 2;
  parameter SymbolBits    = {32'd8, 32'd2};

  localparam TotalWidth   = calc_total(NumSymbols, SymbolBits);

  input                  clk;
  input                  rst;
  input                  din_ready;
  input                  din_valid;
  input [TotalWidth-1:0] din_data;
  output                 done;
  output                 err;



  wire enable  = din_valid & din_ready;




  file_writer
    #(.Filename   (FilenameDump),
      .NumSymbols (NumSymbols),
      .SymbolBits (SymbolBits))
  writer (
    .clk    (clk),
    .rst    (rst),
    .wr_en  (enable),
    .wr_data(din_data)
    );




  wire [TotalWidth-1:0] rd_data;

  generate
    if (CheckData) begin
      file_reader
        #(.Filename   (FilenameRef),
          .NumSymbols (NumSymbols),
          .SymbolBits (SymbolBits))
      reader (
        .clk     (clk),
        .rst     (rst),
        .rd_en   (enable),
        .rd_valid(),
        .rd_data (rd_data),
        .done    (done)
      );

      integer line_num;
      reg     err_r;
      always @(posedge clk) begin
        if (rst) begin
          line_num <= 1;
          err_r    <= 0;
        end else if (enable) begin
          if (done) begin
            $display("Error: (\"%s\") received data past end of file",
                      FilenameRef);
          end else if (rd_data !== din_data) begin


            $display("Error: (\"%s\", line %0d)", FilenameRef, line_num,
                     " received data does not match reference data",
                     " (received: 0x%x, expected: 0x%x)", din_data, rd_data);
            err_r <= 1;
          end
          line_num <= line_num + 1;
        end
      end
      assign err  = err_r;

    end else begin
      assign done = 1'b0;
      assign err  = 1'b0;
    end

  endgenerate

endmodule
module stream_spy (clk, rst, din_ready, din_valid, din_data, done, err);

`include "stream_common.vh"
  parameter FilenameDump  = "undefined";
  parameter FilenameRef   = "undefined";
  parameter CheckData     = 1;
  parameter NumSymbols    = 2;
  parameter SymbolBits    = {32'd8, 32'd2};

  localparam TotalWidth   = calc_total(NumSymbols, SymbolBits);

  input                  clk;
  input                  rst;
  input                  din_ready;
  input                  din_valid;
  input [TotalWidth-1:0] din_data;
  output                 done;
  output                 err;



  wire enable  = din_valid & din_ready;




  file_writer
    #(.Filename   (FilenameDump),
      .NumSymbols (NumSymbols),
      .SymbolBits (SymbolBits))
  writer (
    .clk    (clk),
    .rst    (rst),
    .wr_en  (enable),
    .wr_data(din_data)
    );




  wire [TotalWidth-1:0] rd_data;

  generate
    if (CheckData) begin
      file_reader
        #(.Filename   (FilenameRef),
          .NumSymbols (NumSymbols),
          .SymbolBits (SymbolBits))
      reader (
        .clk     (clk),
        .rst     (rst),
        .rd_en   (enable),
        .rd_valid(),
        .rd_data (rd_data),
        .done    (done)
      );

      integer line_num;
      reg     err_r;
      always @(posedge clk) begin
        if (rst) begin
          line_num <= 1;
          err_r    <= 0;
        end else if (enable) begin
          if (done) begin
            $display("Error: (\"%s\") received data past end of file",
                      FilenameRef);
          end else if (rd_data !== din_data) begin


            $display("Error: (\"%s\", line %0d)", FilenameRef, line_num,
                     " received data does not match reference data",
                     " (received: 0x%x, expected: 0x%x)", din_data, rd_data);
            err_r <= 1;
          end
          line_num <= line_num + 1;
        end
      end
      assign err  = err_r;

    end else begin
      assign done = 1'b0;
      assign err  = 1'b0;
    end

  endgenerate

endmodule