data/full_repos/permissive/104269513/spring_fifo_v2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:447: Unsupported: Ignoring delay on this delayed statement.\n#30 rst = 0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:451: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:453: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/104269513/spring_fifo_v2.v:103: Cannot find file containing module: \'spring_fifo_mem\'\nspring_fifo_mem mem2(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem.v\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem.sv\n             spring_fifo_mem\n             spring_fifo_mem.v\n             spring_fifo_mem.sv\n             obj_dir/spring_fifo_mem\n             obj_dir/spring_fifo_mem.v\n             obj_dir/spring_fifo_mem.sv\n%Error: data/full_repos/permissive/104269513/spring_fifo_v2.v:432: Cannot find file containing module: \'regfile\'\nregfile op_reg( \n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104269513/spring_fifo_v2.v:462: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n                                                                         : ... In instance spring_fifo_tb\nip_rd_count = 4 ;\n            ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spring_fifo #(	parameter MAX_DEPTH = 256,
						parameter ADDR_WIDTH = 8,
						parameter DATA_WIDTH = 64,
						parameter CTRL_WIDTH = DATA_WIDTH/8
						)
						
						(
						input rd_req,
						input wr_req,
						input out_rdy, 
						input in_wr,
						input [1:0] ip_rd_count,
						output reg out_wr,
						output reg pckt_rd_wr,
						output reg rd_ack,
						output reg wr_ack,
						output reg rd_done,
						output reg wr_done,
						

						output in_rdy,
						output full,
						output empty,
						output nearly_full,
						output nearly_empty,
						output reg [1:0] packet_count,
						output reg [ADDR_WIDTH-1:0] first_word,
						output reg [ADDR_WIDTH-1:0] last_word,
						output fifo_busy,
						


						input [DATA_WIDTH-1:0] fifo_data_in,
						output [DATA_WIDTH-1:0] fifo_data_out,
						input [CTRL_WIDTH-1:0] fifo_ctrl_in,
						output [CTRL_WIDTH-1:0] fifo_ctrl_out,
						output reg [ADDR_WIDTH:0] DEPTH,
						output reg [1:0] wr_state,
						output reg [1:0] state,	
						

						output reg [ADDR_WIDTH-1:0] fifo_wa,
						output reg [ADDR_WIDTH-1:0] fifo_ra,
						output reg fifo_rd_en,
						output reg fifo_wr_en,
						

						input clk,
						input rst
						);
						




reg [1:0] rd_count, rd_count_next, rd_count_prev;
reg [1:0] pckt_rd_out_count;


reg [1:0]wr_state_next;
reg [ADDR_WIDTH-1:0] first_word_next, last_word_next;
reg [1:0] packet_count_next;
reg [ADDR_WIDTH-1:0] packet_size, packet_size_next;


reg [ADDR_WIDTH-1:0]fifo_wa_next;
reg [ADDR_WIDTH-1:0]fifo_ra_next, fifo_ra_prev;
wire fifo_read, fifo_write;
reg [ADDR_WIDTH:0] DEPTH_next;
reg [ADDR_WIDTH:0] DEPTH_prev, DEPTH_prev_next;



reg out_wr_next;
reg pckt_rd_wr_next;

spring_fifo_mem mem2(
				.clka(clk),
				.dina({fifo_ctrl_in,fifo_data_in}),
				.addra(fifo_wa),
				.wea(fifo_write),
				.clkb(clk),
				.addrb(fifo_ra),
				.doutb({fifo_ctrl_out,fifo_data_out})
				);

assign empty = (DEPTH == 'h0) ? 1'b1 : 1'b0;
assign nearly_empty = (DEPTH == 'h1) ? 1'b1 : 1'b0;
assign full = (DEPTH == MAX_DEPTH) ? 1'b1 : 1'b0;
assign nearly_full = (DEPTH == MAX_DEPTH - 1) ? 1'b1 : 1'b0;
assign in_rdy = (!(nearly_full | full)) & fifo_wr_en;
assign fifo_read = (fifo_rd_en & out_rdy & !empty);
assign fifo_write = (fifo_wr_en & in_wr & !full);
assign fifo_busy = (fifo_read | fifo_write);

always @ *
begin


	fifo_ra_next = fifo_ra;
	fifo_wa_next = fifo_wa;
	DEPTH_next = DEPTH;
	DEPTH_prev_next = DEPTH_prev;
	first_word_next = first_word;
	last_word_next = last_word;
	packet_size_next = packet_size;
	pckt_rd_wr_next = pckt_rd_wr;
	packet_count_next = packet_count;
	wr_state_next = wr_state;
	out_wr_next = out_wr;
	rd_count_next = rd_count;
	
	
	if (fifo_read)
		begin
			if (rd_count != rd_count_prev)
				begin
					fifo_ra_next = first_word;
					DEPTH_next = DEPTH_prev;
					pckt_rd_wr_next = 1'b0;
				end
			else if (fifo_ra != last_word)
				begin
					if (fifo_ra == first_word)
					begin
						out_wr_next = 1'b1;
						DEPTH_prev_next = DEPTH;
					end
					fifo_ra_next = fifo_ra + 1;
					DEPTH_next = DEPTH_next -1;
				end
			else if ((fifo_ctrl_out != 0) & out_wr)	
				begin
					packet_count_next = packet_count - 1;
					out_wr_next = 1'b0;
					rd_count_next = rd_count - 1;
					if (rd_count_next == 0)
						pckt_rd_wr_next = 1'b1;
				end
			
		end
	else out_wr_next = 1'b0;
	
	if ((fifo_ra == fifo_ra_prev) & (out_wr))
		begin
		out_wr_next = 1'b0;
		end

	if (fifo_write)
		begin
			

			case (wr_state)
				2'h0: begin
						if(fifo_ctrl_in != 'h0)
							begin
								wr_state_next = 2'h1;
								first_word_next = fifo_wa;	
								packet_size_next = 'h1;
								fifo_wa_next = fifo_wa + 1;
								DEPTH_next = DEPTH_next +1;
							end
					  end
					  
				2'h1: begin
						if(fifo_ctrl_in == 'h0)
						begin
							packet_size_next = packet_size + 1;
							fifo_wa_next = fifo_wa + 1;
							DEPTH_next = DEPTH_next +1;
							if (packet_size == 'h5)
								wr_state_next = 2'h2;
						end		
					  end
					  
				2'h2: begin
						fifo_wa_next = fifo_wa + 1;
						DEPTH_next = DEPTH_next +1;
						packet_size_next = packet_size + 1;
						if(fifo_ctrl_in != 'h0)
						begin
								wr_state_next = 2'h0;
								last_word_next = fifo_wa;
								pckt_rd_wr_next = 1'b0;
								packet_count_next = packet_count + 1;
						end						
					  end
					  
				default: begin
							wr_state_next = wr_state;
							packet_count_next = packet_count;
							pckt_rd_wr_next = pckt_rd_wr;
							packet_size_next = packet_size;
							first_word_next = first_word;
							last_word_next = last_word;
						end
			endcase
		end

end

always @ (posedge clk, posedge rst)
begin
	if (rst)
		begin
			fifo_wa <= 'h0;
			fifo_ra <= 'h0;
			DEPTH <= 'h0;
			DEPTH_prev <= 'h0;
			state <= 'h0;
			wr_state <= 'h0;
			packet_size <= 'h0;
			packet_count <= 'h0;
			first_word <= 'h0;
			last_word <= 'h0;
			out_wr <= 'h0;
			pckt_rd_wr <= 'h1;
			fifo_rd_en <= 'h0;
			fifo_wr_en <= 'h0;
			rd_count <= 'h0;
			rd_ack <= 0;
			wr_ack <= 0;
			rd_done <= 1;
			wr_done <= 0;
			pckt_rd_out_count <= 'h0;
		end
	else
		begin
			fifo_wa <= fifo_wa_next;
			fifo_ra_prev <= fifo_ra;
			fifo_ra <= fifo_ra_next;
			DEPTH <= DEPTH_next;
			DEPTH_prev <= DEPTH_prev_next;
			wr_state <= wr_state_next;
			packet_size <= packet_size_next;
			packet_count <= packet_count_next;
			first_word <= first_word_next;
			last_word <= last_word_next;
			out_wr <= out_wr_next;
			pckt_rd_wr <= pckt_rd_wr_next;
			rd_count <= rd_count_next;
			rd_count_prev <= rd_count;
		


	case (state)
		'h0:begin
				rd_done <= 'h0;
				state <= 'h1;
				if(rd_req)
					begin
						fifo_rd_en <= 'b1;
						rd_ack <= 'b1;
						state <= 'h2;
						if (pckt_rd_out_count == 'h0)
							begin
								rd_count <= 'h1;
								rd_count_prev <= 'h1;
							end
						else
							begin
								rd_count <= 'h1;
								rd_count_prev <= 'h0;
							end
					end
			end
			
		'h1:begin
				wr_done <= 'h0;
				state <= 'h0;
				if(wr_req)
					begin
						fifo_wr_en <= 'b1;
						wr_ack <= 'b1;
						state <= 'h3;
					end
				end
			
		'h2:begin
				rd_ack <= 'b0;
				if(pckt_rd_wr_next)
					begin
						fifo_rd_en <= 'b0;
						state <= 'h0;
						rd_done <= 'h1;
						pckt_rd_out_count <= pckt_rd_out_count + 1;
					end
			end
	
		'h3:begin
				wr_ack <= 'b0;
				if(!pckt_rd_wr_next)
					begin
						fifo_wr_en <= 'b0;
						state <= 'h0;
						wr_done <= 'h1;
						pckt_rd_out_count <= 'h0;
					end			
			end
		default: begin
					fifo_wr_en <= 0;
					fifo_rd_en <= 0;
					rd_ack <= 0;
					wr_ack <= 0;
					rd_done <= 0;
					wr_done <= 0;
					state <= 'h0;
				end
		endcase
	end
end

endmodule
module spring_fifo #(	parameter MAX_DEPTH = 256,
						parameter ADDR_WIDTH = 8,
						parameter DATA_WIDTH = 64,
						parameter CTRL_WIDTH = DATA_WIDTH/8
						)
						
						(
						input rd_req,
						input wr_req,
						input out_rdy, 
						input in_wr,
						input [1:0] ip_rd_count,
						output reg out_wr,
						output reg pckt_rd_wr,
						output reg rd_ack,
						output reg wr_ack,
						output reg rd_done,
						output reg wr_done,
						

						output in_rdy,
						output full,
						output empty,
						output nearly_full,
						output nearly_empty,
						output reg [1:0] packet_count,
						output reg [ADDR_WIDTH-1:0] first_word,
						output reg [ADDR_WIDTH-1:0] last_word,
						output fifo_busy,
						


						input [DATA_WIDTH-1:0] fifo_data_in,
						output [DATA_WIDTH-1:0] fifo_data_out,
						input [CTRL_WIDTH-1:0] fifo_ctrl_in,
						output [CTRL_WIDTH-1:0] fifo_ctrl_out,
						output reg [ADDR_WIDTH:0] DEPTH,
						output reg [1:0] wr_state,
						output reg [1:0] state,	
						

						output reg [ADDR_WIDTH-1:0] fifo_wa,
						output reg [ADDR_WIDTH-1:0] fifo_ra,
						output reg fifo_rd_en,
						output reg fifo_wr_en,
						

						input clk,
						input rst
						);

						




reg [1:0] rd_count, rd_count_next, rd_count_prev;
reg [1:0] pckt_rd_out_count;


reg [1:0]wr_state_next;
reg [ADDR_WIDTH-1:0] first_word_next, last_word_next;
reg [1:0] packet_count_next;
reg [ADDR_WIDTH-1:0] packet_size, packet_size_next;


reg [ADDR_WIDTH-1:0]fifo_wa_next;
reg [ADDR_WIDTH-1:0]fifo_ra_next, fifo_ra_prev;
wire fifo_read, fifo_write;
reg [ADDR_WIDTH:0] DEPTH_next;
reg [ADDR_WIDTH:0] DEPTH_prev, DEPTH_prev_next;



reg out_wr_next;
reg pckt_rd_wr_next;

spring_fifo_mem mem2(
				.clka(clk),
				.dina({fifo_ctrl_in,fifo_data_in}),
				.addra(fifo_wa),
				.wea(fifo_write),
				.clkb(clk),
				.addrb(fifo_ra),
				.doutb({fifo_ctrl_out,fifo_data_out})
				);

assign empty = (DEPTH == 'h0) ? 1'b1 : 1'b0;
assign nearly_empty = (DEPTH == 'h1) ? 1'b1 : 1'b0;
assign full = (DEPTH == MAX_DEPTH) ? 1'b1 : 1'b0;
assign nearly_full = (DEPTH == MAX_DEPTH - 1) ? 1'b1 : 1'b0;
assign in_rdy = (!(nearly_full | full)) & fifo_wr_en;
assign fifo_read = (fifo_rd_en & out_rdy & !empty);
assign fifo_write = (fifo_wr_en & in_wr & !full);
assign fifo_busy = (fifo_read | fifo_write);

always @ *
begin


	fifo_ra_next = fifo_ra;
	fifo_wa_next = fifo_wa;
	DEPTH_next = DEPTH;
	DEPTH_prev_next = DEPTH_prev;
	first_word_next = first_word;
	last_word_next = last_word;
	packet_size_next = packet_size;
	pckt_rd_wr_next = pckt_rd_wr;
	packet_count_next = packet_count;
	wr_state_next = wr_state;
	out_wr_next = out_wr;
	rd_count_next = rd_count;
	
	
	if (fifo_read)
		begin
			if (rd_count != rd_count_prev)
				begin
					fifo_ra_next = first_word;
					DEPTH_next = DEPTH_prev;
					pckt_rd_wr_next = 1'b0;
				end
			else if (fifo_ra != last_word)
				begin
					if (fifo_ra == first_word)
					begin
						out_wr_next = 1'b1;
						DEPTH_prev_next = DEPTH;
					end
					fifo_ra_next = fifo_ra + 1;
					DEPTH_next = DEPTH_next -1;
				end
			else if ((fifo_ctrl_out != 0) & out_wr)	
				begin
					packet_count_next = packet_count - 1;
					out_wr_next = 1'b0;
					rd_count_next = rd_count - 1;
					if (rd_count_next == 0)
						pckt_rd_wr_next = 1'b1;
				end
			
		end
	else out_wr_next = 1'b0;
	
	if ((fifo_ra == fifo_ra_prev) & (out_wr))
		begin
		out_wr_next = 1'b0;
		end

	if (fifo_write)
		begin
			

			case (wr_state)
				2'h0: begin
						if(fifo_ctrl_in != 'h0)
							begin
								wr_state_next = 2'h1;
								first_word_next = fifo_wa;	
								packet_size_next = 'h1;
								fifo_wa_next = fifo_wa + 1;
								DEPTH_next = DEPTH_next +1;
							end
					  end
					  
				2'h1: begin
						if(fifo_ctrl_in == 'h0)
						begin
							packet_size_next = packet_size + 1;
							fifo_wa_next = fifo_wa + 1;
							DEPTH_next = DEPTH_next +1;
							if (packet_size == 'h5)
								wr_state_next = 2'h2;
						end		
					  end
					  
				2'h2: begin
						fifo_wa_next = fifo_wa + 1;
						DEPTH_next = DEPTH_next +1;
						packet_size_next = packet_size + 1;
						if(fifo_ctrl_in != 'h0)
						begin
								wr_state_next = 2'h0;
								last_word_next = fifo_wa;
								pckt_rd_wr_next = 1'b0;
								packet_count_next = packet_count + 1;
						end						
					  end
					  
				default: begin
							wr_state_next = wr_state;
							packet_count_next = packet_count;
							pckt_rd_wr_next = pckt_rd_wr;
							packet_size_next = packet_size;
							first_word_next = first_word;
							last_word_next = last_word;
						end
			endcase
		end

end

always @ (posedge clk, posedge rst)
begin
	if (rst)
		begin
			fifo_wa <= 'h0;
			fifo_ra <= 'h0;
			DEPTH <= 'h0;
			DEPTH_prev <= 'h0;
			state <= 'h0;
			wr_state <= 'h0;
			packet_size <= 'h0;
			packet_count <= 'h0;
			first_word <= 'h0;
			last_word <= 'h0;
			out_wr <= 'h0;
			pckt_rd_wr <= 'h1;
			fifo_rd_en <= 'h0;
			fifo_wr_en <= 'h0;
			rd_count <= 'h0;
			rd_ack <= 0;
			wr_ack <= 0;
			rd_done <= 1;
			wr_done <= 0;
			pckt_rd_out_count <= 'h0;
		end
	else
		begin
			fifo_wa <= fifo_wa_next;
			fifo_ra_prev <= fifo_ra;
			fifo_ra <= fifo_ra_next;
			DEPTH <= DEPTH_next;
			DEPTH_prev <= DEPTH_prev_next;
			wr_state <= wr_state_next;
			packet_size <= packet_size_next;
			packet_count <= packet_count_next;
			first_word <= first_word_next;
			last_word <= last_word_next;
			out_wr <= out_wr_next;
			pckt_rd_wr <= pckt_rd_wr_next;
			rd_count <= rd_count_next;
			rd_count_prev <= rd_count;
		


	case (state)
		'h0:begin
				rd_done <= 'h0;
				state <= 'h1;
				if(rd_req)
					begin
						fifo_rd_en <= 'b1;
						rd_ack <= 'b1;
						state <= 'h2;
						if (pckt_rd_out_count == 'h0)
							begin
								rd_count <= 'h1;
								rd_count_prev <= 'h1;
							end
						else
							begin
								rd_count <= 'h1;
								rd_count_prev <= 'h0;
							end
					end
			end
			
		'h1:begin
				wr_done <= 'h0;
				state <= 'h0;
				if(wr_req)
					begin
						fifo_wr_en <= 'b1;
						wr_ack <= 'b1;
						state <= 'h3;
					end
				end
			
		'h2:begin
				rd_ack <= 'b0;
				if(pckt_rd_wr_next)
					begin
						fifo_rd_en <= 'b0;
						state <= 'h0;
						rd_done <= 'h1;
						pckt_rd_out_count <= pckt_rd_out_count + 1;
					end
			end
	
		'h3:begin
				wr_ack <= 'b0;
				if(!pckt_rd_wr_next)
					begin
						fifo_wr_en <= 'b0;
						state <= 'h0;
						wr_done <= 'h1;
						pckt_rd_out_count <= 'h0;
					end			
			end
		default: begin
					fifo_wr_en <= 0;
					fifo_rd_en <= 0;
					rd_ack <= 0;
					wr_ack <= 0;
					rd_done <= 0;
					wr_done <= 0;
					state <= 'h0;
				end
		endcase
	end
end

endmodule