data/full_repos/permissive/123043192/FPGA/FPGA_FINAL/FPGA_FINAL.srcs/sources_1/new/Top_Block.v
1: b"%Error: data/full_repos/permissive/123043192/FPGA/FPGA_FINAL/FPGA_FINAL.srcs/sources_1/new/Top_Block.v:80: Cannot find file containing module: 'Sync_245_Controller'\n    Sync_245_Controller controller(.D(ftdi_d),\n    ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123043192/FPGA/FPGA_FINAL/FPGA_FINAL.srcs/sources_1/new,data/full_repos/permissive/123043192/Sync_245_Controller\n             data/full_repos/permissive/123043192/FPGA/FPGA_FINAL/FPGA_FINAL.srcs/sources_1/new,data/full_repos/permissive/123043192/Sync_245_Controller.v\n             data/full_repos/permissive/123043192/FPGA/FPGA_FINAL/FPGA_FINAL.srcs/sources_1/new,data/full_repos/permissive/123043192/Sync_245_Controller.sv\n             Sync_245_Controller\n             Sync_245_Controller.v\n             Sync_245_Controller.sv\n             obj_dir/Sync_245_Controller\n             obj_dir/Sync_245_Controller.v\n             obj_dir/Sync_245_Controller.sv\n%Error: data/full_repos/permissive/123043192/FPGA/FPGA_FINAL/FPGA_FINAL.srcs/sources_1/new/Top_Block.v:125: Cannot find file containing module: 'Multiplexer_Packet_Former'\n    Multiplexer_Packet_Former mpf(   \n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Top_Block(

    inout wire[7:0] ftdi_d,
    input wire ftdi_rxf,
    input wire ftdi_txe,
    output wire ftdi_wr,
    output wire ftdi_rd,
    output wire ftdi_oe,
    input wire ftdi_clk,
    output wire ftdi_siwu,
    



    

    input sysClk,

    output[3:0] STATE
    );
    
    assign ftdi_siwu = 1'b0;
    

    reg global_rst;
    

    wire[7:0] dataBus;

    wire mpfClkOut;

    wire mpfDataGood;

    wire mpfReadData;
    

    wire[7:0] hostDataBus;

    wire newHostData;

    reg readHostData;
    

    wire txF;
    

    wire txE;
    

    wire[3:0] sync_state;

    wire[7:0] outData;
    

    assign mpfReadData = ~txF;
    

    Sync_245_Controller controller(.D(ftdi_d),
                                   .RXF(ftdi_rxf),
                                   .TXE(ftdi_txe),
                                   .WR(ftdi_wr),
                                   .RD(ftdi_rd),
                                   .OE(ftdi_oe),
                                   .CLKOUT(ftdi_clk),
                                   
                                   .inputData(dataBus),
                                   .inputClock(mpfClkOut),
                                   .inputDataGood(mpfDataGood),
                                   
                                   .hostData(hostDataBus),
                                   .outputClock(sysClk),
                                   .readData(readHostData),
                                   .hasData(newHostData),
                                   
                                   .reset(global_rst),
                                   .dataSent(outData),
                                   .txFULL(txF),
                                   .txEMPTY(txE),
                                   ._state(sync_state)
                                   );
                                                            
    

    wire [7:0] camera1DataBus;
    wire camera1DataGood;
    wire camera1DataClk;
    

    wire [7:0] camera2DataBus;
    wire camera2DataGood;
    wire camera2DataClk;


    wire [7:0] camera3DataBus;
    wire camera3DataGood;
    wire camera3DataClk;
    

    reg startCameras;
     


    Multiplexer_Packet_Former mpf(
                                    .packetData(dataBus),
                                    .packetDataGood(mpfDataGood),
                                    .packetDataClk(mpfClkOut),
                                    .readData(mpfReadData),
                                    

                                    .camera1PixelData(camera1DataBus),
                                    .camera1PixelDataGood(camera1DataGood),
                                    .camera1PixelDataClk(camera1DataClk),
                                    

                                    .camera2PixelData(camera2DataBus),
                                    .camera2PixelDataGood(camera2DataGood),
                                    .camera2PixelDataClk(camera2DataClk),
                                    

                                    .camera3PixelData(camera3DataBus),
                                    .camera3PixelDataGood(camera3DataGood),
                                    .camera3PixelDataClk(camera3DataClk),
                                    
                                    .sys_clk(sysClk),
                                    .reset(global_rst)
                                    );
                                    
                                    
    reg[3:0] state;
    parameter WAIT_FOR_START = 12,STREAMING=1, READ_HOST_DATA=2,PROCESS_HOST_DATA=3,RESET=4;
    

    reg[9:0] counter;
    

    assign STATE = state;
    
    always@(state) begin
            case(state)

                RESET: begin
                    global_rst <= 1;
                    startCameras <= 0;
                    readHostData <= 0;
                end

                WAIT_FOR_START: begin
                    global_rst <= 0;
                    startCameras <= 0;
                    readHostData <= 0;
                end

                STREAMING: begin
                    global_rst <= 0;
                    startCameras <= 1;
                    readHostData <=0;
                end

                READ_HOST_DATA: begin
                    readHostData <=1;
                end
                

                PROCESS_HOST_DATA: begin
                    readHostData <= 0;
                end
                

                default: begin
                    global_rst <= 1;
                    startCameras <= 0;
                    readHostData <=0;
                end
            endcase
        end
       
        
        always@(posedge sysClk) begin
            case(state)

                default: begin
                    state = RESET;
                    counter = 0;
                end
                

                RESET: begin
                    counter <= counter + 1;
                    if(counter >= 10'h030)
                        state = WAIT_FOR_START;
                end
                

                WAIT_FOR_START: begin
                    if(newHostData)
                        state = READ_HOST_DATA;
                    else
                        state = WAIT_FOR_START;
                end
                

                READ_HOST_DATA: begin
                    state = PROCESS_HOST_DATA;
                end
                

                PROCESS_HOST_DATA: begin
                    if (hostDataBus == 8'b10101010)
                        state = STREAMING;
                    else
                        state = WAIT_FOR_START;
                end
                


                STREAMING: begin
                    state = STREAMING;
                end
                
            endcase
        
        end
    
endmodule
module Top_Block(

    inout wire[7:0] ftdi_d,
    input wire ftdi_rxf,
    input wire ftdi_txe,
    output wire ftdi_wr,
    output wire ftdi_rd,
    output wire ftdi_oe,
    input wire ftdi_clk,
    output wire ftdi_siwu,
    



    

    input sysClk,

    output[3:0] STATE
    );

    
    assign ftdi_siwu = 1'b0;
    

    reg global_rst;
    

    wire[7:0] dataBus;

    wire mpfClkOut;

    wire mpfDataGood;

    wire mpfReadData;
    

    wire[7:0] hostDataBus;

    wire newHostData;

    reg readHostData;
    

    wire txF;
    

    wire txE;
    

    wire[3:0] sync_state;

    wire[7:0] outData;
    

    assign mpfReadData = ~txF;
    

    Sync_245_Controller controller(.D(ftdi_d),
                                   .RXF(ftdi_rxf),
                                   .TXE(ftdi_txe),
                                   .WR(ftdi_wr),
                                   .RD(ftdi_rd),
                                   .OE(ftdi_oe),
                                   .CLKOUT(ftdi_clk),
                                   
                                   .inputData(dataBus),
                                   .inputClock(mpfClkOut),
                                   .inputDataGood(mpfDataGood),
                                   
                                   .hostData(hostDataBus),
                                   .outputClock(sysClk),
                                   .readData(readHostData),
                                   .hasData(newHostData),
                                   
                                   .reset(global_rst),
                                   .dataSent(outData),
                                   .txFULL(txF),
                                   .txEMPTY(txE),
                                   ._state(sync_state)
                                   );
                                                            
    

    wire [7:0] camera1DataBus;
    wire camera1DataGood;
    wire camera1DataClk;
    

    wire [7:0] camera2DataBus;
    wire camera2DataGood;
    wire camera2DataClk;


    wire [7:0] camera3DataBus;
    wire camera3DataGood;
    wire camera3DataClk;
    

    reg startCameras;
     


    Multiplexer_Packet_Former mpf(
                                    .packetData(dataBus),
                                    .packetDataGood(mpfDataGood),
                                    .packetDataClk(mpfClkOut),
                                    .readData(mpfReadData),
                                    

                                    .camera1PixelData(camera1DataBus),
                                    .camera1PixelDataGood(camera1DataGood),
                                    .camera1PixelDataClk(camera1DataClk),
                                    

                                    .camera2PixelData(camera2DataBus),
                                    .camera2PixelDataGood(camera2DataGood),
                                    .camera2PixelDataClk(camera2DataClk),
                                    

                                    .camera3PixelData(camera3DataBus),
                                    .camera3PixelDataGood(camera3DataGood),
                                    .camera3PixelDataClk(camera3DataClk),
                                    
                                    .sys_clk(sysClk),
                                    .reset(global_rst)
                                    );
                                    
                                    
    reg[3:0] state;
    parameter WAIT_FOR_START = 12,STREAMING=1, READ_HOST_DATA=2,PROCESS_HOST_DATA=3,RESET=4;
    

    reg[9:0] counter;
    

    assign STATE = state;
    
    always@(state) begin
            case(state)

                RESET: begin
                    global_rst <= 1;
                    startCameras <= 0;
                    readHostData <= 0;
                end

                WAIT_FOR_START: begin
                    global_rst <= 0;
                    startCameras <= 0;
                    readHostData <= 0;
                end

                STREAMING: begin
                    global_rst <= 0;
                    startCameras <= 1;
                    readHostData <=0;
                end

                READ_HOST_DATA: begin
                    readHostData <=1;
                end
                

                PROCESS_HOST_DATA: begin
                    readHostData <= 0;
                end
                

                default: begin
                    global_rst <= 1;
                    startCameras <= 0;
                    readHostData <=0;
                end
            endcase
        end
       
        
        always@(posedge sysClk) begin
            case(state)

                default: begin
                    state = RESET;
                    counter = 0;
                end
                

                RESET: begin
                    counter <= counter + 1;
                    if(counter >= 10'h030)
                        state = WAIT_FOR_START;
                end
                

                WAIT_FOR_START: begin
                    if(newHostData)
                        state = READ_HOST_DATA;
                    else
                        state = WAIT_FOR_START;
                end
                

                READ_HOST_DATA: begin
                    state = PROCESS_HOST_DATA;
                end
                

                PROCESS_HOST_DATA: begin
                    if (hostDataBus == 8'b10101010)
                        state = STREAMING;
                    else
                        state = WAIT_FOR_START;
                end
                


                STREAMING: begin
                    state = STREAMING;
                end
                
            endcase
        
        end
    
endmodule