data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/DCT.v
 line:30: before: ","
1: b'%Error: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/DCT.v:40: Cannot find file containing module: \'Matrix_Multiplier1_8X8\'\n Matrix_Multiplier1_8X8 DIMG1(DIMGtmp0, DIMGtmp1, DIMGtmp2, DIMGtmp3, DIMGtmp4, DIMGtmp5, DIMGtmp6, DIMGtmp7, counter, IMG_add_a, clk);\n ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/Matrix_Multiplier1_8X8\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/Matrix_Multiplier1_8X8.v\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/Matrix_Multiplier1_8X8.sv\n             Matrix_Multiplier1_8X8\n             Matrix_Multiplier1_8X8.v\n             Matrix_Multiplier1_8X8.sv\n             obj_dir/Matrix_Multiplier1_8X8\n             obj_dir/Matrix_Multiplier1_8X8.v\n             obj_dir/Matrix_Multiplier1_8X8.sv\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/DCT.v:85: Operator LT expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'counterj\' generates 8 bits.\n                                                                                       : ... In instance DCT\n    if(counterj < 256)\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/DCT.v:83: Operator LT expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'counteri\' generates 8 bits.\n                                                                                       : ... In instance DCT\n   if(counteri < 256)\n               ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module DCT(
    input clk
	 );

   reg [15:0] DIMG [65536:0];
	wire [31:0] DIMGtmp0, DIMGtmp1, DIMGtmp2, DIMGtmp3, DIMGtmp4, DIMGtmp5, DIMGtmp6, DIMGtmp7;
	wire [3:0] counter;
	wire [15:0] IMG_add_a;
	wire validtmp;
	reg valid = 0, transpose_valid = 1'b0;
	reg [7:0] counteri = 0, counterj = 0;

	reg [15:0] swaptmp;
	
	



	
	Matrix_Multiplier1_8X8 DIMG1(DIMGtmp0, DIMGtmp1, DIMGtmp2, DIMGtmp3, DIMGtmp4, DIMGtmp5, DIMGtmp6, DIMGtmp7, counter, IMG_add_a, clk);
	


	
	assign validtmp = (IMG_add_a == 16'hfffe) ? 1'b1 : 1'b0;


	
	always@(posedge clk)
	begin
		if(!(validtmp || valid))
		begin

			if(counter == 4)
			begin
				DIMG[IMG_add_a - 16] <= DIMGtmp0[23:8];
				DIMG[IMG_add_a - 15] <= DIMGtmp1[23:8];
				DIMG[IMG_add_a - 14] <= DIMGtmp2[23:8];
				DIMG[IMG_add_a - 13] <= DIMGtmp3[23:8];
				DIMG[IMG_add_a - 12] <= DIMGtmp4[23:8];
				DIMG[IMG_add_a - 11] <= DIMGtmp5[23:8];
				DIMG[IMG_add_a - 10] <= DIMGtmp6[23:8];
				DIMG[IMG_add_a - 9] <= DIMGtmp7[23:8];

			end
		end
		if((validtmp || valid) && !transpose_valid)
		begin


			valid <= 1;
			
			
			if(counteri < 256)
			begin
				if(counterj < 256)
				begin
					swaptmp <= DIMG[(counteri * 256) + counterj];
					DIMG[(counteri * 256) + counterj] <= DIMG[(counterj * 256) + counteri];
					DIMG[(counterj * 256) + counteri] <= swaptmp;


					if(counterj == 255)
					begin
						counteri <= counteri + 1;
						counterj <= counteri + 1;

					end
				end
				if(counterj != 255)
				counterj <= counterj + 1;
			end
	end
		
		if(transpose_valid == 1'b1 || counteri == 255)
			transpose_valid <= 1'b1;










	end
endmodule
module DCT(
    input clk
	 );


   reg [15:0] DIMG [65536:0];
	wire [31:0] DIMGtmp0, DIMGtmp1, DIMGtmp2, DIMGtmp3, DIMGtmp4, DIMGtmp5, DIMGtmp6, DIMGtmp7;
	wire [3:0] counter;
	wire [15:0] IMG_add_a;
	wire validtmp;
	reg valid = 0, transpose_valid = 1'b0;
	reg [7:0] counteri = 0, counterj = 0;

	reg [15:0] swaptmp;
	
	



	
	Matrix_Multiplier1_8X8 DIMG1(DIMGtmp0, DIMGtmp1, DIMGtmp2, DIMGtmp3, DIMGtmp4, DIMGtmp5, DIMGtmp6, DIMGtmp7, counter, IMG_add_a, clk);
	


	
	assign validtmp = (IMG_add_a == 16'hfffe) ? 1'b1 : 1'b0;


	
	always@(posedge clk)
	begin
		if(!(validtmp || valid))
		begin

			if(counter == 4)
			begin
				DIMG[IMG_add_a - 16] <= DIMGtmp0[23:8];
				DIMG[IMG_add_a - 15] <= DIMGtmp1[23:8];
				DIMG[IMG_add_a - 14] <= DIMGtmp2[23:8];
				DIMG[IMG_add_a - 13] <= DIMGtmp3[23:8];
				DIMG[IMG_add_a - 12] <= DIMGtmp4[23:8];
				DIMG[IMG_add_a - 11] <= DIMGtmp5[23:8];
				DIMG[IMG_add_a - 10] <= DIMGtmp6[23:8];
				DIMG[IMG_add_a - 9] <= DIMGtmp7[23:8];

			end
		end
		if((validtmp || valid) && !transpose_valid)
		begin


			valid <= 1;
			
			
			if(counteri < 256)
			begin
				if(counterj < 256)
				begin
					swaptmp <= DIMG[(counteri * 256) + counterj];
					DIMG[(counteri * 256) + counterj] <= DIMG[(counterj * 256) + counteri];
					DIMG[(counterj * 256) + counteri] <= swaptmp;


					if(counterj == 255)
					begin
						counteri <= counteri + 1;
						counterj <= counteri + 1;

					end
				end
				if(counterj != 255)
				counterj <= counterj + 1;
			end
	end
		
		if(transpose_valid == 1'b1 || counteri == 255)
			transpose_valid <= 1'b1;










	end
endmodule