data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/beepdiv.v
data/verilator_xmls/0e7e5cce-c5b2-45f5-9589-fef70d0be03f.xml
module beepdiv(
    input inclk,
output outclk
    );
    
    reg [35:0] q;
    
    initial q<=36'b0;
    
    always@(posedge inclk)
         q<=q+1;
    

    assign outclk=q[26];
    
endmodule
module beepdiv(
    input inclk,
output outclk
    );

    
    reg [35:0] q;
    
    initial q<=36'b0;
    
    always@(posedge inclk)
         q<=q+1;
    

    assign outclk=q[26];
    
endmodule