data/full_repos/permissive/174642777/Experiments/Lab X4/Lab 12 SHREG_4bit/DFF_test.v
1: b'%Error: Cannot find file containing module: X4/Lab\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X4/Lab\n             data/full_repos/permissive/174642777/Experiments/Lab/X4/Lab.v\n             data/full_repos/permissive/174642777/Experiments/Lab/X4/Lab.sv\n             X4/Lab\n             X4/Lab.v\n             X4/Lab.sv\n             obj_dir/X4/Lab\n             obj_dir/X4/Lab.v\n             obj_dir/X4/Lab.sv\n%Error: Cannot find file containing module: 12\n%Error: Cannot find file containing module: SHREG_4bit,data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: SHREG_4bit/DFF_test.v\n%Error: Exiting due to 5 error(s)\n'
module DFF_test;


	reg CLK;
	reg CLR;
	reg EN;
	reg D;


	wire Q;


	DFF uut (
		.CLK(CLK), 
		.CLR(CLR), 
		.EN(EN), 
		.D(D), 
		.Q(Q)
	);

	initial begin

		CLK = 0;
		CLR = 0;
		EN = 0;
		D = 0;


		#100;
    
		

    CLR = 1;
    #50
    CLR = 0;
    #50;
    

    EN <= 1;
    
    D <= 1;
    CLK <= 1;
    #50;
    CLK <= 0;
    #50;
    
    D <= 0;
    CLK <= 1;
    #50;
    CLK <= 0;
    #50;
    
    
    EN <= 0;
    
    D <= 1;
    CLK <= 1;
    #50;
    CLK <= 0;
    #50;
    
    D <= 0;
    CLK <= 1;
    #50;
    CLK <= 0;
    #50;
    
    
    EN <= 1;
    D <= 1;
    CLK <= 1;
    #50;
    CLK <= 0;
    #50;
    CLR <= 1;
    #50;
    CLR <= 0;
    #50;
    
	end
      
endmodule
module DFF_test;



	reg CLK;
	reg CLR;
	reg EN;
	reg D;


	wire Q;


	DFF uut (
		.CLK(CLK), 
		.CLR(CLR), 
		.EN(EN), 
		.D(D), 
		.Q(Q)
	);

	initial begin

		CLK = 0;
		CLR = 0;
		EN = 0;
		D = 0;


		#100;
    
		

    CLR = 1;
    #50
    CLR = 0;
    #50;
    

    EN <= 1;
    
    D <= 1;
    CLK <= 1;
    #50;
    CLK <= 0;
    #50;
    
    D <= 0;
    CLK <= 1;
    #50;
    CLK <= 0;
    #50;
    
    
    EN <= 0;
    
    D <= 1;
    CLK <= 1;
    #50;
    CLK <= 0;
    #50;
    
    D <= 0;
    CLK <= 1;
    #50;
    CLK <= 0;
    #50;
    
    
    EN <= 1;
    D <= 1;
    CLK <= 1;
    #50;
    CLK <= 0;
    #50;
    CLR <= 1;
    #50;
    CLR <= 0;
    #50;
    
	end
      
endmodule