data/full_repos/permissive/109936328/top/dmem_bus.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:11: Define or directive not defined: \'`ADDR_W\'\n  input [`ADDR_W - 1:0] i_mem_req_addr,\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:12: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_mem_req_wr_addr,\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:14: Define or directive not defined: \'`MEM_COUNT_W\'\n  input [`MEM_COUNT_W - 1:0] i_mem_req_count,\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:16: Define or directive not defined: \'`WORD_W\'\n  output reg [`WORD_W - 1:0] o_mem_res_data,\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:17: Define or directive not defined: \'`MEM_COUNT_W\'\n  output reg [`MEM_COUNT_W - 1:0] o_mem_res_code,\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:19: Define or directive not defined: \'`WORD_W\'\n  output reg [`WORD_W - 1:0] peripheral\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:21: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] dmem_req_addr = i_mem_req_addr;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:22: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] dmem_req_wr_data = i_mem_req_wr_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:24: Define or directive not defined: \'`MEM_COUNT_W\'\n  reg [`MEM_COUNT_W - 1:0] dmem_req_count;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:25: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] dmem_res_rd_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:26: Define or directive not defined: \'`MEM_CODE_W\'\n  wire [`MEM_CODE_W - 1:0] dmem_res_code;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:38: Define or directive not defined: \'`MEM_CODE_WRITE\'\n      o_mem_res_code = i_mem_req_wr_en ? `MEM_CODE_WRITE : `MEM_CODE_READ;\n                                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:38: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n      o_mem_res_code = i_mem_req_wr_en ? `MEM_CODE_WRITE : `MEM_CODE_READ;\n                                                         ^\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:38: Define or directive not defined: \'`MEM_CODE_READ\'\n      o_mem_res_code = i_mem_req_wr_en ? `MEM_CODE_WRITE : `MEM_CODE_READ;\n                                                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:40: Define or directive not defined: \'`MEM_COUNT_NONE\'\n      dmem_req_count = `MEM_COUNT_NONE;\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      dmem_req_count = `MEM_COUNT_NONE;\n                                      ^\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:43: Define or directive not defined: \'`MEM_CODE_OUT_OF_BOUNDS\'\n      o_mem_res_code = `MEM_CODE_OUT_OF_BOUNDS;\n                       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/dmem_bus.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      o_mem_res_code = `MEM_CODE_OUT_OF_BOUNDS;\n                                              ^\n%Error: Exiting due to 20 error(s)\n'
module dmem_bus#(
  parameter WORD_COUNT,
  parameter PERIPH_ADDR
)(
  input clk,
  input aresetn,

  input [`ADDR_W - 1:0] i_mem_req_addr,
  input [`WORD_W - 1:0] i_mem_req_wr_addr,
  input i_mem_req_wr_en,
  input [`MEM_COUNT_W - 1:0] i_mem_req_count,
  
  output reg [`WORD_W - 1:0] o_mem_res_data,
  output reg [`MEM_COUNT_W - 1:0] o_mem_res_code,

  output reg [`WORD_W - 1:0] peripheral
);
  reg [`ADDR_W - 1:0] dmem_req_addr = i_mem_req_addr;
  wire [`WORD_W - 1:0] dmem_req_wr_data = i_mem_req_wr_data;
  wire dmem_req_wr_en = i_mem_req_wr_en;
  reg [`MEM_COUNT_W - 1:0] dmem_req_count;
  wire [`WORD_W - 1:0] dmem_res_rd_data;
  wire [`MEM_CODE_W - 1:0] dmem_res_code;

  always @(*) begin
    if(i_mem_req_addr < {WORD_COUNT, 2'b00}) begin
      dmem_req_count = i_mem_req_count;

      o_mem_res_rd_data = dmem_res_rd_data;
      o_mem_res_code = dmem_res_code;
    end else if(i_mem_req_addr == PERIPH_ADDR) begin
      dmem_req_count = i_mem_req_count;

      o_mem_res_rd_data = peripheral;
      o_mem_res_code = i_mem_req_wr_en ? `MEM_CODE_WRITE : `MEM_CODE_READ;
    end else begin
      dmem_req_count = `MEM_COUNT_NONE;

      o_mem_res_rd_data = 0;
      o_mem_res_code = `MEM_CODE_OUT_OF_BOUNDS;
    end
  end

  memory_interface#(
    .WORD_COUNT(WORD_COUNT)
  ) dmem(
    .clk(clk),
    .aresetn(aresetn),

    .i_req_addr(dmem_req_addr),
    .i_req_wr_data(dmem_req_wr_data),
    .i_req_wr_en(dmem_req_wr_en),
    .i_req_count(dmem_req_count),

    .o_res_rd_data(dmem_res_rd_data),
    .o_res_code(dmem_res_code)
  );
endmodule
module dmem_bus#(
  parameter WORD_COUNT,
  parameter PERIPH_ADDR
)(
  input clk,
  input aresetn,

  input [`ADDR_W - 1:0] i_mem_req_addr,
  input [`WORD_W - 1:0] i_mem_req_wr_addr,
  input i_mem_req_wr_en,
  input [`MEM_COUNT_W - 1:0] i_mem_req_count,
  
  output reg [`WORD_W - 1:0] o_mem_res_data,
  output reg [`MEM_COUNT_W - 1:0] o_mem_res_code,

  output reg [`WORD_W - 1:0] peripheral
);

  reg [`ADDR_W - 1:0] dmem_req_addr = i_mem_req_addr;
  wire [`WORD_W - 1:0] dmem_req_wr_data = i_mem_req_wr_data;
  wire dmem_req_wr_en = i_mem_req_wr_en;
  reg [`MEM_COUNT_W - 1:0] dmem_req_count;
  wire [`WORD_W - 1:0] dmem_res_rd_data;
  wire [`MEM_CODE_W - 1:0] dmem_res_code;

  always @(*) begin
    if(i_mem_req_addr < {WORD_COUNT, 2'b00}) begin
      dmem_req_count = i_mem_req_count;

      o_mem_res_rd_data = dmem_res_rd_data;
      o_mem_res_code = dmem_res_code;
    end else if(i_mem_req_addr == PERIPH_ADDR) begin
      dmem_req_count = i_mem_req_count;

      o_mem_res_rd_data = peripheral;
      o_mem_res_code = i_mem_req_wr_en ? `MEM_CODE_WRITE : `MEM_CODE_READ;
    end else begin
      dmem_req_count = `MEM_COUNT_NONE;

      o_mem_res_rd_data = 0;
      o_mem_res_code = `MEM_CODE_OUT_OF_BOUNDS;
    end
  end

  memory_interface#(
    .WORD_COUNT(WORD_COUNT)
  ) dmem(
    .clk(clk),
    .aresetn(aresetn),

    .i_req_addr(dmem_req_addr),
    .i_req_wr_data(dmem_req_wr_data),
    .i_req_wr_en(dmem_req_wr_en),
    .i_req_count(dmem_req_count),

    .o_res_rd_data(dmem_res_rd_data),
    .o_res_code(dmem_res_code)
  );
endmodule