data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v
 line:52: before: ")"
1: b'%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:56: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:62: syntax error, unexpected \'{\', expecting TYPE-IDENTIFIER\n  #(5) assign {control, constant, data} = instr;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #(5) assign {control, constant, data} = instr;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #(10)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #(5)\n  ^\n%Error: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:70: Unsupported or unknown PLI call: $fsdbDumpfile\n $fsdbDumpfile("hw3_t.fsdb");\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:71: Unsupported or unknown PLI call: $fsdbDumpvars\n $fsdbDumpvars;\n ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:75: Unsupported: Ignoring delay on this delayed statement.\n #0 clk = 0; rst_n = 0; constant = 0; control = 0; data = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:76: Unsupported: Ignoring delay on this delayed statement.\n #20 rst_n = 1;\n ^\n%Error: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:79: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n snapshotPT = $fopen("dump1.dat");\n              ^~~~~~\n%Error: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:85: syntax error, unexpected \'{\', expecting TYPE-IDENTIFIER\n  assign {V, C, N, Z, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, BUSA, BUSB} = snapshot;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw3/hw3_t.v:92: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: Exiting due to 5 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hw3_t ;
reg [57:0] test_vector [`TESTSIZE-1:0];
reg [291:0] test_response [`TESTSIZE-1:0];
reg [25:0] control;
reg [15:0] constant;
reg [15:0] data;
reg clk, rst_n;
reg V, C, N, Z;
reg [15:0] R0;
reg [15:0] R1;
reg [15:0] R2;
reg [15:0] R3;
reg [15:0] R4;
reg [15:0] R5;
reg [15:0] R6;
reg [15:0] R7;
reg [15:0] R8;
reg [15:0] R9;
reg [15:0] R10;
reg [15:0] R11;
reg [15:0] R12;
reg [15:0] R13;
reg [15:0] R14;
reg [15:0] R15;
reg [15:0] BUSA;
reg [15:0] BUSB;
wire [291:0] snapshot;
integer error, snapshotPT, descPT, i;
reg cmp;

datapath golden(
				snapshot,
				control,
				constant,
				data,
				clk,
				rst_n,
			   );


always begin
	#`CLOCK_CYCLE clk = ~clk;
end

task simulation;
	input [57:0] instr;
	begin
		#(`HALF_CYCLE) assign {control, constant, data} = instr;
		#(`HALF_CYCLE)
		#(`CLOCK_CYCLE)
		$display("i = %d", i);
	end
endtask

initial begin
	$fsdbDumpfile("hw3_t.fsdb");
	$fsdbDumpvars;
end

initial begin
	#0 clk = 0; rst_n = 0; constant = 0; control = 0; data = 0;
	#20 rst_n = 1;
	$readmemb(`STRINGIFY(`PATTERN), test_vector);
	$readmemb(`STRINGIFY(`GOLDEN), test_response);
	snapshotPT = $fopen(`STRINGIFY(`SNAPSHOT));
	$display("File dump handle in %h", snapshotPT);
	error = 0;
	for (i = 0; i < `TESTSIZE; i++) begin
		simulation(test_vector[i]);
		descPT = snapshotPT;
		assign {V, C, N, Z, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, BUSA, BUSB} = snapshot;
		$fdisplay(descPT, "%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b", V, C, N, Z, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, BUSA, BUSB);
		cmp = (snapshot == test_response[i])?1:0;
		if (cmp == 0) begin
		error++;
		end
	end
	#10
	if (error == 0) begin
		$display("PASS");
	end else begin
		$display("NOT PASS");
	end
	$fclose(snapshotPT);
	$finish;
end
endmodule
module hw3_t ;

reg [57:0] test_vector [`TESTSIZE-1:0];
reg [291:0] test_response [`TESTSIZE-1:0];
reg [25:0] control;
reg [15:0] constant;
reg [15:0] data;
reg clk, rst_n;
reg V, C, N, Z;
reg [15:0] R0;
reg [15:0] R1;
reg [15:0] R2;
reg [15:0] R3;
reg [15:0] R4;
reg [15:0] R5;
reg [15:0] R6;
reg [15:0] R7;
reg [15:0] R8;
reg [15:0] R9;
reg [15:0] R10;
reg [15:0] R11;
reg [15:0] R12;
reg [15:0] R13;
reg [15:0] R14;
reg [15:0] R15;
reg [15:0] BUSA;
reg [15:0] BUSB;
wire [291:0] snapshot;
integer error, snapshotPT, descPT, i;
reg cmp;

datapath golden(
				snapshot,
				control,
				constant,
				data,
				clk,
				rst_n,
			   );


always begin
	#`CLOCK_CYCLE clk = ~clk;
end

task simulation;
	input [57:0] instr;
	begin
		#(`HALF_CYCLE) assign {control, constant, data} = instr;
		#(`HALF_CYCLE)
		#(`CLOCK_CYCLE)
		$display("i = %d", i);
	end
endtask

initial begin
	$fsdbDumpfile("hw3_t.fsdb");
	$fsdbDumpvars;
end

initial begin
	#0 clk = 0; rst_n = 0; constant = 0; control = 0; data = 0;
	#20 rst_n = 1;
	$readmemb(`STRINGIFY(`PATTERN), test_vector);
	$readmemb(`STRINGIFY(`GOLDEN), test_response);
	snapshotPT = $fopen(`STRINGIFY(`SNAPSHOT));
	$display("File dump handle in %h", snapshotPT);
	error = 0;
	for (i = 0; i < `TESTSIZE; i++) begin
		simulation(test_vector[i]);
		descPT = snapshotPT;
		assign {V, C, N, Z, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, BUSA, BUSB} = snapshot;
		$fdisplay(descPT, "%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b", V, C, N, Z, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, BUSA, BUSB);
		cmp = (snapshot == test_response[i])?1:0;
		if (cmp == 0) begin
		error++;
		end
	end
	#10
	if (error == 0) begin
		$display("PASS");
	end else begin
		$display("NOT PASS");
	end
	$fclose(snapshotPT);
	$finish;
end
endmodule