data/full_repos/permissive/108195533/EX_stage.v
1: b"%Error: data/full_repos/permissive/108195533/EX_stage.v:48: Cannot find file containing module: 'signExtend'\n signExtend SE(offsetReg, offSS);\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/signExtend\n             data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/signExtend.v\n             data/full_repos/permissive/108195533,data/full_repos/permissive/108195533/signExtend.sv\n             signExtend\n             signExtend.v\n             signExtend.sv\n             obj_dir/signExtend\n             obj_dir/signExtend.v\n             obj_dir/signExtend.sv\n%Error: data/full_repos/permissive/108195533/EX_stage.v:50: Cannot find file containing module: 'alu'\n alu aluUnit(.operandA(operandAReg), .operandB(operandBSelected), .aluCon(aluConReg), .result(aluRes));\n ^~~\n%Error: Exiting due to 2 error(s)\n"
module EX_stage
	#(parameter RF_WIDTH=3, parameter WIDTH=16, parameter ALU_CON_WIDTH=3, parameter DATA_WIDTH=16, parameter MID_WIDTH=1, parameter OFF_WIDTH=6)
	(clk, reset, instrIn, instrOut, aluCon, aluRes, midSignalIn, midSignalOut, operandA, operandB, operandBReg, operandSel, offset);
	
	input clk, reset;
	input [WIDTH-1:0] instrIn;
	input [ALU_CON_WIDTH-1:0] aluCon;
	input [OFF_WIDTH-1:0] offset;
	reg [OFF_WIDTH-1:0] offsetReg;
	
	input operandSel;
	reg operandSelReg;
	
	always @(posedge clk)
		operandSelReg <= operandSel;
	
	output reg[WIDTH-1:0] instrOut;
	output [DATA_WIDTH-1:0] aluRes;
	
	input [MID_WIDTH-1:0] midSignalIn;
	output reg [MID_WIDTH-1:0] midSignalOut;
	
	always @(posedge clk) begin
		if(reset)
			midSignalOut <= {MID_WIDTH{1'b0}};
		else
			midSignalOut <= midSignalIn;
	end
	
	reg [ALU_CON_WIDTH-1:0] aluConReg;
	
	input [DATA_WIDTH-1:0] operandA, operandB;
	reg [DATA_WIDTH-1:0] operandAReg; 
	output reg [DATA_WIDTH-1:0] operandBReg;
	
	always @(posedge clk) begin
		operandAReg <= operandA;
		operandBReg <= operandB;
	end
	
	
	always @(posedge clk)
		aluConReg<=aluCon;
	
	wire [DATA_WIDTH-1:0] operandBSelected;
	wire [DATA_WIDTH-1:0] offSS;
	
	signExtend SE(offsetReg, offSS);
	assign operandBSelected = operandSelReg?offSS:operandBReg;
	alu aluUnit(.operandA(operandAReg), .operandB(operandBSelected), .aluCon(aluConReg), .result(aluRes));
	
	always@(posedge clk) begin
		if(reset)
			instrOut <= {WIDTH{1'b0}};
		else
			instrOut <= instrIn;
	end
		
	always@(posedge clk)
		offsetReg <= offset;

endmodule
module EX_stage
	#(parameter RF_WIDTH=3, parameter WIDTH=16, parameter ALU_CON_WIDTH=3, parameter DATA_WIDTH=16, parameter MID_WIDTH=1, parameter OFF_WIDTH=6)
	(clk, reset, instrIn, instrOut, aluCon, aluRes, midSignalIn, midSignalOut, operandA, operandB, operandBReg, operandSel, offset);

	
	input clk, reset;
	input [WIDTH-1:0] instrIn;
	input [ALU_CON_WIDTH-1:0] aluCon;
	input [OFF_WIDTH-1:0] offset;
	reg [OFF_WIDTH-1:0] offsetReg;
	
	input operandSel;
	reg operandSelReg;
	
	always @(posedge clk)
		operandSelReg <= operandSel;
	
	output reg[WIDTH-1:0] instrOut;
	output [DATA_WIDTH-1:0] aluRes;
	
	input [MID_WIDTH-1:0] midSignalIn;
	output reg [MID_WIDTH-1:0] midSignalOut;
	
	always @(posedge clk) begin
		if(reset)
			midSignalOut <= {MID_WIDTH{1'b0}};
		else
			midSignalOut <= midSignalIn;
	end
	
	reg [ALU_CON_WIDTH-1:0] aluConReg;
	
	input [DATA_WIDTH-1:0] operandA, operandB;
	reg [DATA_WIDTH-1:0] operandAReg; 
	output reg [DATA_WIDTH-1:0] operandBReg;
	
	always @(posedge clk) begin
		operandAReg <= operandA;
		operandBReg <= operandB;
	end
	
	
	always @(posedge clk)
		aluConReg<=aluCon;
	
	wire [DATA_WIDTH-1:0] operandBSelected;
	wire [DATA_WIDTH-1:0] offSS;
	
	signExtend SE(offsetReg, offSS);
	assign operandBSelected = operandSelReg?offSS:operandBReg;
	alu aluUnit(.operandA(operandAReg), .operandB(operandBSelected), .aluCon(aluConReg), .result(aluRes));
	
	always@(posedge clk) begin
		if(reset)
			instrOut <= {WIDTH{1'b0}};
		else
			instrOut <= instrIn;
	end
		
	always@(posedge clk)
		offsetReg <= offset;

endmodule