data/full_repos/permissive/201267735/rtl/core/frv_pipeline.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201267735/rtl/core/frv_pipeline.v:163: Cannot find include file: frv_common.vh\n`include "frv_common.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201267735/rtl/core,data/full_repos/permissive/201267735/frv_common.vh\n             data/full_repos/permissive/201267735/rtl/core,data/full_repos/permissive/201267735/frv_common.vh.v\n             data/full_repos/permissive/201267735/rtl/core,data/full_repos/permissive/201267735/frv_common.vh.sv\n             frv_common.vh\n             frv_common.vh.v\n             frv_common.vh.sv\n             obj_dir/frv_common.vh\n             obj_dir/frv_common.vh.v\n             obj_dir/frv_common.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module frv_pipeline (

input               g_clk           ,
input               g_resetn        ,

`ifdef RVFI
output [NRET        - 1 : 0] rvfi_valid     ,
output [NRET *   64 - 1 : 0] rvfi_order     ,
output [NRET * ILEN - 1 : 0] rvfi_insn      ,
output [NRET        - 1 : 0] rvfi_trap      ,
output [NRET        - 1 : 0] rvfi_halt      ,
output [NRET        - 1 : 0] rvfi_intr      ,
output [NRET * 2    - 1 : 0] rvfi_mode      ,

output [NRET *    5 - 1 : 0] rvfi_rs1_addr  ,
output [NRET *    5 - 1 : 0] rvfi_rs2_addr  ,
output [NRET *    5 - 1 : 0] rvfi_rs3_addr  ,
output [NRET * XLEN - 1 : 0] rvfi_rs1_rdata ,
output [NRET * XLEN - 1 : 0] rvfi_rs2_rdata ,
output [NRET * XLEN - 1 : 0] rvfi_rs3_rdata ,
output [NRET * XLEN - 1 : 0] rvfi_aux       ,
output [NRET * 32   - 1 : 0] rvfi_rng_data  ,
output [NRET *  3   - 1 : 0] rvfi_rng_stat  ,
output [NRET *    5 - 1 : 0] rvfi_rd_addr   ,
output [NRET        - 1 : 0] rvfi_rd_wide   ,
output [NRET * XLEN - 1 : 0] rvfi_rd_wdata  ,
output [NRET * XLEN - 1 : 0] rvfi_rd_wdatahi,

output [NRET * XLEN - 1 : 0] rvfi_pc_rdata  ,
output [NRET * XLEN - 1 : 0] rvfi_pc_wdata  ,

output [NRET * XLEN  - 1: 0] rvfi_mem_addr  ,
output [NRET * XLEN/8- 1: 0] rvfi_mem_rmask ,
output [NRET * XLEN/8- 1: 0] rvfi_mem_wmask ,
output [NRET * XLEN  - 1: 0] rvfi_mem_rdata ,
output [NRET * XLEN  - 1: 0] rvfi_mem_wdata ,
`endif

output wire [XL:0]  trs_pc          ,
output wire [31:0]  trs_instr       ,
output wire         trs_valid       ,

output wire [XL:0]  leak_prng       ,
output wire         leak_fence_unc0 ,
output wire         leak_fence_unc1 ,
output wire         leak_fence_unc2 ,

output wire         rng_req_valid   ,
output wire [ 2:0]  rng_req_op      ,
output wire [31:0]  rng_req_data    ,
input  wire         rng_req_ready   ,
input  wire         rng_rsp_valid   ,
input  wire [ 2:0]  rng_rsp_status  ,
input  wire [31:0]  rng_rsp_data    ,
output wire         rng_rsp_ready   ,

output wire         instr_ret       ,

output wire         mstatus_mie     ,
output wire         mie_meie        ,
output wire         mie_mtie        ,
output wire         mie_msie        ,

input  wire         mip_meip        ,
input  wire         mip_mtip        ,
input  wire         mip_msip        ,

input  wire [63:0]  ctr_time        ,
input  wire [63:0]  ctr_cycle       ,
input  wire [63:0]  ctr_instret     ,

input  wire         int_trap_req    ,
input  wire [ 5:0]  int_trap_cause  ,
output wire         int_trap_ack    ,

output wire         inhibit_cy      ,
output wire         inhibit_tm      ,
output wire         inhibit_ir      ,

output wire         mmio_en         ,
output wire         mmio_wen        ,
output wire [31:0]  mmio_addr       ,
output wire [31:0]  mmio_wdata      ,
input  wire [31:0]  mmio_rdata      ,
input  wire         mmio_error      ,

output wire         imem_req        ,
output wire         imem_wen        ,
output wire [3:0]   imem_strb       ,
output wire [XL:0]  imem_wdata      ,
output wire [XL:0]  imem_addr       ,
input  wire         imem_gnt        ,
input  wire         imem_recv       ,
output wire         imem_ack        ,
input  wire         imem_error      ,
input  wire [XL:0]  imem_rdata      ,

output wire         dmem_req        ,
output wire         dmem_wen        ,
output wire [3:0]   dmem_strb       ,
output wire [XL:0]  dmem_wdata      ,
output wire [XL:0]  dmem_addr       ,
input  wire         dmem_gnt        ,
input  wire         dmem_recv       ,
output wire         dmem_ack        ,
input  wire         dmem_error      ,
input  wire [XL:0]  dmem_rdata

);


parameter FRV_PC_RESET_VALUE = 32'h8000_0000;


parameter BRAM_REGFILE = 0;


parameter   MMIO_BASE_ADDR        = 32'h0000_1000;
parameter   MMIO_BASE_MASK        = 32'hFFFF_F000;



parameter TRACE_INSTR_WORD = 1'b1;



parameter XC_CLASS_BASELINE   = 1'b1;
parameter XC_CLASS_RANDOMNESS = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_MEMORY     = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_BIT        = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_PACKED     = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_MULTIARITH = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_AES        = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_SHA2       = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_SHA3       = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_LEAK       = 1'b1 && XC_CLASS_BASELINE;


parameter XC_CLASS_LEAK_STRONG= 1'b1 && XC_CLASS_LEAK;


parameter XC_CLASS_LEAK_BUBBLE= 1'b1 && XC_CLASS_LEAK;


parameter AES_SUB_FAST = 1'b1;
parameter AES_MIX_FAST = 1'b1;



parameter BITMANIP_BASELINE   = 1'b1;



parameter  CSR_MIMPID           = 32'b0;


`include "frv_common.vh"




wire        uxcrypto_ct;
wire [ 7:0] uxcrypto_b0;
wire [ 7:0] uxcrypto_b1;



assign      instr_ret = trs_valid;



wire        cf_req     ;
wire [XL:0] cf_target  ;
wire        cf_ack     ;



wire [12:0] leak_lkgcfg   ;
wire        s1_leak_fence ;



wire        csr_en     ;
wire        csr_wr     ;
wire        csr_wr_set ;
wire        csr_wr_clr ;
wire [11:0] csr_addr   ;
wire [XL:0] csr_wdata  ;
wire [XL:0] csr_rdata  ;
wire        csr_error  ;

wire [XL:0] csr_mepc   ;
wire [XL:0] csr_mtvec  ;
wire        vector_intrs;

wire        exec_mret  ;



wire        trap_cpu   ;
wire        trap_int   ;
wire [ 5:0] trap_cause ;
wire [XL:0] trap_mtval ;
wire [XL:0] trap_pc    ;


wire        s0_flush   = cf_req && cf_ack;
wire        s1_flush   = cf_req && cf_ack;
wire        s2_flush   = cf_req && cf_ack;
wire        s3_flush   = cf_req && cf_ack;
wire        s4_flush   = cf_req && cf_ack;

wire        s0_busy       ;

wire        s1_valid      ;
wire        s1_busy       ;
wire [XL:0] s1_data       ;
wire        s1_error      ;

wire [ 4:0] s1_rs1_addr   ;
wire [ 4:0] s1_rs2_addr   ;
wire [ 4:0] s1_rs3_addr   ;
wire [XL:0] s1_rs1_rdata  ;
wire [XL:0] s1_rs2_rdata  ;
wire [XL:0] s1_rs3_rdata  ;

wire        s2_valid      ;
wire        s2_busy       ;
wire [ 4:0] s2_rd         ;
wire [XL:0] s2_opr_a      ;
wire [XL:0] s2_opr_b      ;
wire [XL:0] s2_opr_c      ;
wire [OP:0] s2_uop        ;
wire [FU:0] s2_fu         ;
wire [PW:0] s2_pw         ;
wire        s2_trap       ;
wire [ 1:0] s2_size       ;
wire [31:0] s2_instr      ;

wire [ 4:0] fwd_s2_rd     ;
wire        fwd_s2_wide   ;
wire [XL:0] fwd_s2_wdata  ;
wire [XL:0] fwd_s2_wdata_hi;
wire        fwd_s2_load   ;
wire        fwd_s2_csr    ;

wire [ 4:0] s3_rd         ;
wire [XL:0] s3_opr_a      ;
wire [XL:0] s3_opr_b      ;
wire [OP:0] s3_uop        ;
wire [FU:0] s3_fu         ;
wire        s3_trap       ;
wire [ 1:0] s3_size       ;
wire [31:0] s3_instr      ;
wire        s3_busy       ;
wire        s3_valid      ;

wire [ 4:0] fwd_s3_rd     ;
wire        fwd_s3_wide   ;
wire [XL:0] fwd_s3_wdata  ;
wire [XL:0] fwd_s3_wdata_hi;
wire        fwd_s3_load   ;
wire        fwd_s3_csr    ;

wire [ 4:0] s4_rd         ;
wire [XL:0] s4_opr_a      ;
wire [XL:0] s4_opr_b      ;
wire [OP:0] s4_uop        ;
wire [FU:0] s4_fu         ;
wire        s4_trap       ;
wire [ 1:0] s4_size       ;
wire [31:0] s4_instr      ;
wire        s4_busy       ;
wire        s4_valid      ;

wire [ 4:0] fwd_s4_rd     ;
wire [XL:0] fwd_s4_wdata  ;
wire        fwd_s4_load   ;
wire        fwd_s4_csr    ;

wire        gpr_wen       ;
wire        gpr_wide      ;
wire [ 4:0] gpr_rd        ;
wire [XL:0] gpr_wdata     ;
wire [XL:0] gpr_wdata_hi  ;

wire        hold_lsu_req  ;

`ifdef RVFI
wire [XL:0] rvfi_s2_rs1_rdata;
wire [XL:0] rvfi_s2_rs2_rdata;
wire [XL:0] rvfi_s2_rs3_rdata;
wire [ 4:0] rvfi_s2_rs1_addr ;
wire [ 4:0] rvfi_s2_rs2_addr ;
wire [ 4:0] rvfi_s2_rs3_addr ;
wire [XL:0] rvfi_s3_rs1_rdata;
wire [XL:0] rvfi_s3_rs2_rdata;
wire [XL:0] rvfi_s3_rs3_rdata;
wire [ 4:0] rvfi_s3_rs1_addr ;
wire [ 4:0] rvfi_s3_rs2_addr ;
wire [ 4:0] rvfi_s3_rs3_addr ;
wire [XL:0] rvfi_s3_aux      ;
wire [31:0] rvfi_s3_rng_data ;
wire [ 2:0] rvfi_s3_rng_stat ;
wire [XL:0] rvfi_s4_rs1_rdata;
wire [XL:0] rvfi_s4_rs2_rdata;
wire [XL:0] rvfi_s4_rs3_rdata;
wire [ 4:0] rvfi_s4_rs1_addr ;
wire [ 4:0] rvfi_s4_rs2_addr ;
wire [ 4:0] rvfi_s4_rs3_addr ;
wire [XL:0] rvfi_s4_aux      ;
wire [31:0] rvfi_s4_rng_data ;
wire [ 2:0] rvfi_s4_rng_stat ;
wire [XL:0] rvfi_s4_mem_wdata;
`endif






wire nz_s1_rs1     = |s1_rs1_addr;
wire nz_s1_rs2     = |s1_rs2_addr;
wire nz_s1_rs3     = |s1_rs3_addr;




`define HAZARD(A, F, NZ, W) (               \
    (A[4:1] == F[4:1]) &&                   \
    (NZ || !NZ && A[0] && !F[0] && W  ) &&  \
    (A[0] == F[0] || A[0] && !F[0] && W)    \
)

wire hzd_rs1_s4 = `HAZARD(s1_rs1_addr, fwd_s4_rd, nz_s1_rs1, gpr_wide   );
wire hzd_rs1_s3 = `HAZARD(s1_rs1_addr, fwd_s3_rd, nz_s1_rs1, fwd_s3_wide);
wire hzd_rs1_s2 = `HAZARD(s1_rs1_addr, fwd_s2_rd, nz_s1_rs1, fwd_s2_wide);

wire hzd_rs2_s4 = `HAZARD(s1_rs2_addr, fwd_s4_rd, nz_s1_rs2, gpr_wide   );
wire hzd_rs2_s3 = `HAZARD(s1_rs2_addr, fwd_s3_rd, nz_s1_rs2, fwd_s3_wide);
wire hzd_rs2_s2 = `HAZARD(s1_rs2_addr, fwd_s2_rd, nz_s1_rs2, fwd_s2_wide);

wire hzd_rs3_s4 = `HAZARD(s1_rs3_addr, fwd_s4_rd, nz_s1_rs3, gpr_wide   );
wire hzd_rs3_s3 = `HAZARD(s1_rs3_addr, fwd_s3_rd, nz_s1_rs3, fwd_s3_wide);
wire hzd_rs3_s2 = `HAZARD(s1_rs3_addr, fwd_s2_rd, nz_s1_rs3, fwd_s2_wide);

`undef HAZARD

wire fwd_s2_rs1_hi = s1_rs1_addr[0] && fwd_s2_wide;
wire fwd_s3_rs1_hi = s1_rs1_addr[0] && fwd_s3_wide;
wire fwd_s4_rs1_hi = s1_rs1_addr[0] && gpr_wide   ;

wire fwd_s2_rs2_hi = s1_rs2_addr[0] && fwd_s2_wide;
wire fwd_s3_rs2_hi = s1_rs2_addr[0] && fwd_s3_wide;
wire fwd_s4_rs2_hi = s1_rs2_addr[0] && gpr_wide   ;

wire fwd_s2_rs3_hi = s1_rs3_addr[0] && fwd_s2_wide;
wire fwd_s3_rs3_hi = s1_rs3_addr[0] && fwd_s3_wide;
wire fwd_s4_rs3_hi = s1_rs3_addr[0] && gpr_wide   ;






wire   s1_bubble_no_instr = !s1_valid && !s2_busy ;
wire   s1_bubble_from_s4  = fwd_s4_csr||(fwd_s4_load && (hzd_rs1_s4 || hzd_rs2_s4 || hzd_rs3_s4));
wire   s1_bubble_from_s3  = fwd_s3_csr||(fwd_s3_load && (hzd_rs1_s3 || hzd_rs2_s3 || hzd_rs3_s3));
wire   s1_bubble_from_s2  = fwd_s2_csr||(fwd_s2_load && (hzd_rs1_s2 || hzd_rs2_s2 || hzd_rs3_s2));
wire   s1_bubble   =
     s1_bubble_no_instr     ||
     s1_bubble_from_s4      ||
     s1_bubble_from_s3      ||
     s1_bubble_from_s2      ;


wire [XL:0] fwd_rs1_rdata =
     hzd_rs1_s2 ? (fwd_s2_rs1_hi ? fwd_s2_wdata_hi : fwd_s2_wdata)  :
     hzd_rs1_s3 ? (fwd_s3_rs1_hi ? fwd_s3_wdata_hi : fwd_s3_wdata)  :
     hzd_rs1_s4 ? (fwd_s4_rs1_hi ? gpr_wdata_hi    : gpr_wdata   )  :
                  s1_rs1_rdata   ;

wire [XL:0] fwd_rs2_rdata =
     hzd_rs2_s2 ? (fwd_s2_rs2_hi ? fwd_s2_wdata_hi : fwd_s2_wdata)  :
     hzd_rs2_s3 ? (fwd_s3_rs2_hi ? fwd_s3_wdata_hi : fwd_s3_wdata)  :
     hzd_rs2_s4 ? (fwd_s4_rs2_hi ? gpr_wdata_hi    : gpr_wdata   )  :
                  s1_rs2_rdata   ;

wire [XL:0] fwd_rs3_rdata =
     hzd_rs3_s2 ? (fwd_s2_rs3_hi ? fwd_s2_wdata_hi : fwd_s2_wdata)  :
     hzd_rs3_s3 ? (fwd_s3_rs3_hi ? fwd_s3_wdata_hi : fwd_s3_wdata)  :
     hzd_rs3_s4 ? (fwd_s4_rs3_hi ? gpr_wdata_hi    : gpr_wdata   )  :
                  s1_rs3_rdata   ;











frv_pipeline_fetch #(
.FRV_PC_RESET_VALUE(FRV_PC_RESET_VALUE)
) i_pipeline_s0_fetch (
.g_clk              (g_clk              ),
.g_resetn           (g_resetn           ),
.cf_req             (cf_req             ),
.cf_target          (cf_target          ),
.cf_ack             (cf_ack             ),
.imem_req           (imem_req           ),
.imem_wen           (imem_wen           ),
.imem_strb          (imem_strb          ),
.imem_wdata         (imem_wdata         ),
.imem_addr          (imem_addr          ),
.imem_gnt           (imem_gnt           ),
.imem_ack           (imem_ack           ),
.imem_recv          (imem_recv          ),
.imem_error         (imem_error         ),
.imem_rdata         (imem_rdata         ),
.s0_flush           (s0_flush           ),
.s1_busy            (s1_busy            ),
.s1_valid           (s1_valid           ),
.s1_data            (s1_data            ),
.s1_error           (s1_error           )
);







frv_pipeline_decode #(
.FRV_PC_RESET_VALUE (FRV_PC_RESET_VALUE ),
.TRACE_INSTR_WORD   (TRACE_INSTR_WORD   ),
.XC_CLASS_BASELINE  (XC_CLASS_BASELINE  ),
.XC_CLASS_RANDOMNESS(XC_CLASS_RANDOMNESS),
.XC_CLASS_MEMORY    (XC_CLASS_MEMORY    ),
.XC_CLASS_BIT       (XC_CLASS_BIT       ),
.XC_CLASS_PACKED    (XC_CLASS_PACKED    ),
.XC_CLASS_MULTIARITH(XC_CLASS_MULTIARITH),
.XC_CLASS_AES       (XC_CLASS_AES       ),
.XC_CLASS_SHA2      (XC_CLASS_SHA2      ),
.XC_CLASS_SHA3      (XC_CLASS_SHA3      ),
.XC_CLASS_LEAK      (XC_CLASS_LEAK      ),
.XC_CLASS_LEAK_STRONG(XC_CLASS_LEAK_STRONG),
.XC_CLASS_LEAK_BUBBLE(XC_CLASS_LEAK_BUBBLE),
.BITMANIP_BASELINE  (BITMANIP_BASELINE  ) 
) i_pipeline_s1_decode (
.g_clk              (g_clk              ),
.g_resetn           (g_resetn           ),
.s1_valid           (s1_valid           ),
.s1_busy            (s1_busy            ),
.s1_data            (s1_data            ),
.s1_error           (s1_error           ),
.s1_flush           (s1_flush           ),
.s1_bubble          (s1_bubble          ),
.s1_rs1_addr        (s1_rs1_addr        ),
.s1_rs2_addr        (s1_rs2_addr        ),
.s1_rs3_addr        (s1_rs3_addr        ),
.s1_rs1_rdata       (fwd_rs1_rdata      ),
.s1_rs2_rdata       (fwd_rs2_rdata      ),
.s1_rs3_rdata       (fwd_rs3_rdata      ),
.leak_prng          (leak_prng          ),
.leak_lkgcfg        (leak_lkgcfg        ),
.s1_leak_fence      (s1_leak_fence      ),
.cf_req             (cf_req             ),
.cf_target          (cf_target          ),
.cf_ack             (cf_ack             ),
`ifdef RVFI
.rvfi_s2_rs1_addr   (rvfi_s2_rs1_addr   ),
.rvfi_s2_rs2_addr   (rvfi_s2_rs2_addr   ),
.rvfi_s2_rs3_addr   (rvfi_s2_rs3_addr   ),
.rvfi_s2_rs1_data   (rvfi_s2_rs1_rdata  ),
.rvfi_s2_rs2_data   (rvfi_s2_rs2_rdata  ),
.rvfi_s2_rs3_data   (rvfi_s2_rs3_rdata  ),
`endif
.s2_valid           (s2_valid           ),
.s2_busy            (s2_busy            ),
.s2_rd              (s2_rd              ),
.s2_opr_a           (s2_opr_a           ),
.s2_opr_b           (s2_opr_b           ),
.s2_opr_c           (s2_opr_c           ),
.s2_uop             (s2_uop             ),
.s2_fu              (s2_fu              ),
.s2_pw              (s2_pw              ),
.s2_trap            (s2_trap            ),
.s2_size            (s2_size            ),
.s2_instr           (s2_instr           )
);






frv_pipeline_execute #(
.XC_CLASS_RANDOMNESS(XC_CLASS_RANDOMNESS),
.XC_CLASS_MEMORY    (XC_CLASS_MEMORY    ),
.XC_CLASS_BIT       (XC_CLASS_BIT       ),
.XC_CLASS_PACKED    (XC_CLASS_PACKED    ),
.XC_CLASS_MULTIARITH(XC_CLASS_MULTIARITH),
.XC_CLASS_AES       (XC_CLASS_AES       ),
.XC_CLASS_SHA2      (XC_CLASS_SHA2      ),
.XC_CLASS_SHA3      (XC_CLASS_SHA3      ),
.AES_SUB_FAST       (AES_SUB_FAST       ),
.AES_MIX_FAST       (AES_MIX_FAST       ),
.BITMANIP_BASELINE  (BITMANIP_BASELINE  ) 
) i_pipeline_s2_execute (
.g_clk            (g_clk            ),
.g_resetn         (g_resetn         ),
.s2_rd            (s2_rd            ),
.s2_opr_a         (s2_opr_a         ),
.s2_opr_b         (s2_opr_b         ),
.s2_opr_c         (s2_opr_c         ),
.s2_uop           (s2_uop           ),
.s2_fu            (s2_fu            ),
.s2_pw            (s2_pw            ),
.s2_trap          (s2_trap          ),
.s2_size          (s2_size          ),
.s2_instr         (s2_instr         ),
.s2_busy          (s2_busy          ),
.s2_valid         (s2_valid         ),
.leak_prng        (leak_prng        ),
.leak_lkgcfg       (leak_lkgcfg       ),
.rng_req_valid    (rng_req_valid    ),
.rng_req_op       (rng_req_op       ),
.rng_req_data     (rng_req_data     ),
.rng_req_ready    (rng_req_ready    ),
.rng_rsp_valid    (rng_rsp_valid    ),
.rng_rsp_status   (rng_rsp_status   ),
.rng_rsp_data     (rng_rsp_data     ),
.rng_rsp_ready    (rng_rsp_ready    ),
.uxcrypto_ct      (uxcrypto_ct      ),
.uxcrypto_b0      (uxcrypto_b0      ),
.uxcrypto_b1      (uxcrypto_b1      ),
.flush            (s2_flush         ),
.fwd_s2_rd        (fwd_s2_rd        ),
.fwd_s2_wide      (fwd_s2_wide      ),
.fwd_s2_wdata     (fwd_s2_wdata     ),
.fwd_s2_wdata_hi  (fwd_s2_wdata_hi  ),
.fwd_s2_load      (fwd_s2_load      ),
.fwd_s2_csr       (fwd_s2_csr       ),
`ifdef RVFI
.rvfi_s2_rs1_rdata(rvfi_s2_rs1_rdata),
.rvfi_s2_rs2_rdata(rvfi_s2_rs2_rdata),
.rvfi_s2_rs3_rdata(rvfi_s2_rs3_rdata),
.rvfi_s2_rs1_addr (rvfi_s2_rs1_addr ),
.rvfi_s2_rs2_addr (rvfi_s2_rs2_addr ),
.rvfi_s2_rs3_addr (rvfi_s2_rs3_addr ),
.rvfi_s3_rs1_rdata(rvfi_s3_rs1_rdata),
.rvfi_s3_rs2_rdata(rvfi_s3_rs2_rdata),
.rvfi_s3_rs3_rdata(rvfi_s3_rs3_rdata),
.rvfi_s3_rs1_addr (rvfi_s3_rs1_addr ),
.rvfi_s3_rs2_addr (rvfi_s3_rs2_addr ),
.rvfi_s3_rs3_addr (rvfi_s3_rs3_addr ),
.rvfi_s3_aux      (rvfi_s3_aux      ),
.rvfi_s3_rng_data (rvfi_s3_rng_data ), 
.rvfi_s3_rng_stat (rvfi_s3_rng_stat ), 
`endif
.s3_rd            (s3_rd            ),
.s3_opr_a         (s3_opr_a         ),
.s3_opr_b         (s3_opr_b         ),
.s3_uop           (s3_uop           ),
.s3_fu            (s3_fu            ),
.s3_trap          (s3_trap          ),
.s3_size          (s3_size          ),
.s3_instr         (s3_instr         ),
.s3_busy          (s3_busy          ),
.s3_valid         (s3_valid         )
);







frv_pipeline_memory #(
.MMIO_BASE_ADDR(MMIO_BASE_ADDR),
.MMIO_BASE_MASK(MMIO_BASE_MASK)
) i_pipeline_s3_memory(
.g_clk            (g_clk            ),
.g_resetn         (g_resetn         ),
.flush            (s3_flush         ),
.s3_rd            (s3_rd            ),
.s3_opr_a         (s3_opr_a         ),
.s3_opr_b         (s3_opr_b         ),
.s3_uop           (s3_uop           ),
.s3_fu            (s3_fu            ),
.s3_trap          (s3_trap          ),
.s3_size          (s3_size          ),
.s3_instr         (s3_instr         ),
.s3_busy          (s3_busy          ),
.s3_valid         (s3_valid         ),
.leak_prng        (leak_prng        ),
.leak_lkgcfg       (leak_lkgcfg       ),
.leak_fence_unc0  (leak_fence_unc0  ),
.leak_fence_unc1  (leak_fence_unc1  ),
.leak_fence_unc2  (leak_fence_unc2  ),
.fwd_s3_rd        (fwd_s3_rd        ),
.fwd_s3_wide      (fwd_s3_wide      ),
.fwd_s3_wdata     (fwd_s3_wdata     ),
.fwd_s3_wdata_hi  (fwd_s3_wdata_hi  ),
.fwd_s3_load      (fwd_s3_load      ),
.fwd_s3_csr       (fwd_s3_csr       ),
`ifdef RVFI
.rvfi_s3_rs1_rdata(rvfi_s3_rs1_rdata),
.rvfi_s3_rs2_rdata(rvfi_s3_rs2_rdata),
.rvfi_s3_rs3_rdata(rvfi_s3_rs3_rdata),
.rvfi_s3_rs1_addr (rvfi_s3_rs1_addr ),
.rvfi_s3_rs2_addr (rvfi_s3_rs2_addr ),
.rvfi_s3_rs3_addr (rvfi_s3_rs3_addr ),
.rvfi_s3_aux      (rvfi_s3_aux      ),
.rvfi_s3_rng_data (rvfi_s3_rng_data ), 
.rvfi_s3_rng_stat (rvfi_s3_rng_stat ), 
.rvfi_s4_rs1_rdata(rvfi_s4_rs1_rdata),
.rvfi_s4_rs2_rdata(rvfi_s4_rs2_rdata),
.rvfi_s4_rs3_rdata(rvfi_s4_rs3_rdata),
.rvfi_s4_rs1_addr (rvfi_s4_rs1_addr ),
.rvfi_s4_rs2_addr (rvfi_s4_rs2_addr ),
.rvfi_s4_rs3_addr (rvfi_s4_rs3_addr ),
.rvfi_s4_aux      (rvfi_s4_aux      ),
.rvfi_s4_rng_data (rvfi_s4_rng_data ), 
.rvfi_s4_rng_stat (rvfi_s4_rng_stat ), 
.rvfi_s4_mem_wdata(rvfi_s4_mem_wdata),
`endif
.hold_lsu_req     (hold_lsu_req     ),
.mmio_en          (mmio_en          ),
.mmio_wen         (mmio_wen         ),
.mmio_addr        (mmio_addr        ),
.mmio_wdata       (mmio_wdata       ),
.dmem_req         (dmem_req         ),
.dmem_wen         (dmem_wen         ),
.dmem_strb        (dmem_strb        ),
.dmem_wdata       (dmem_wdata       ),
.dmem_addr        (dmem_addr        ),
.dmem_gnt         (dmem_gnt         ),
.s4_rd            (s4_rd            ),
.s4_opr_a         (s4_opr_a         ),
.s4_opr_b         (s4_opr_b         ),
.s4_uop           (s4_uop           ),
.s4_fu            (s4_fu            ),
.s4_trap          (s4_trap          ),
.s4_size          (s4_size          ),
.s4_instr         (s4_instr         ),
.s4_busy          (s4_busy          ),
.s4_valid         (s4_valid         )
);










frv_pipeline_writeback #(
.FRV_PC_RESET_VALUE(FRV_PC_RESET_VALUE)
) i_pipeline_s4_writeback(
.g_clk            (g_clk            ),
.g_resetn         (g_resetn         ),
`ifdef RVFI
.rvfi_valid       (rvfi_valid       ),
.rvfi_order       (rvfi_order       ),
.rvfi_insn        (rvfi_insn        ),
.rvfi_trap        (rvfi_trap        ),
.rvfi_halt        (rvfi_halt        ),
.rvfi_intr        (rvfi_intr        ),
.rvfi_mode        (rvfi_mode        ),
.rvfi_rs1_addr    (rvfi_rs1_addr    ),
.rvfi_rs2_addr    (rvfi_rs2_addr    ),
.rvfi_rs3_addr    (rvfi_rs3_addr    ),
.rvfi_rs1_rdata   (rvfi_rs1_rdata   ),
.rvfi_rs2_rdata   (rvfi_rs2_rdata   ),
.rvfi_rs3_rdata   (rvfi_rs3_rdata   ),
.rvfi_aux         (rvfi_aux         ),
.rvfi_rng_data    (rvfi_rng_data    ), 
.rvfi_rng_stat    (rvfi_rng_stat    ), 
.rvfi_rd_addr     (rvfi_rd_addr     ),
.rvfi_rd_wide     (rvfi_rd_wide     ),
.rvfi_rd_wdata    (rvfi_rd_wdata    ),
.rvfi_rd_wdatahi  (rvfi_rd_wdatahi  ),
.rvfi_pc_rdata    (rvfi_pc_rdata    ),
.rvfi_pc_wdata    (rvfi_pc_wdata    ),
.rvfi_mem_addr    (rvfi_mem_addr    ),
.rvfi_mem_rmask   (rvfi_mem_rmask   ),
.rvfi_mem_wmask   (rvfi_mem_wmask   ),
.rvfi_mem_rdata   (rvfi_mem_rdata   ),
.rvfi_mem_wdata   (rvfi_mem_wdata   ),
.rvfi_s4_rs1_rdata(rvfi_s4_rs1_rdata),
.rvfi_s4_rs2_rdata(rvfi_s4_rs2_rdata),
.rvfi_s4_rs3_rdata(rvfi_s4_rs3_rdata),
.rvfi_s4_rs1_addr (rvfi_s4_rs1_addr ),
.rvfi_s4_rs2_addr (rvfi_s4_rs2_addr ),
.rvfi_s4_rs3_addr (rvfi_s4_rs3_addr ),
.rvfi_s4_aux      (rvfi_s4_aux      ),
.rvfi_s4_rng_data (rvfi_s4_rng_data ), 
.rvfi_s4_rng_stat (rvfi_s4_rng_stat ), 
.rvfi_s4_mem_wdata(rvfi_s4_mem_wdata),
`endif
.s4_rd            (s4_rd            ),
.s4_opr_a         (s4_opr_a         ),
.s4_opr_b         (s4_opr_b         ),
.s4_uop           (s4_uop           ),
.s4_fu            (s4_fu            ),
.s4_trap          (s4_trap          ),
.s4_size          (s4_size          ),
.s4_instr         (s4_instr         ),
.s4_busy          (s4_busy          ),
.s4_valid         (s4_valid         ),
.fwd_s4_rd        (fwd_s4_rd        ),
.fwd_s4_wdata     (fwd_s4_wdata     ),
.fwd_s4_load      (fwd_s4_load      ),
.fwd_s4_csr       (fwd_s4_csr       ),
.gpr_wen          (gpr_wen          ),
.gpr_wide         (gpr_wide         ),
.gpr_rd           (gpr_rd           ),
.gpr_wdata        (gpr_wdata        ),
.gpr_wdata_hi     (gpr_wdata_hi     ),
.int_trap_req     (int_trap_req     ),
.int_trap_cause   (int_trap_cause   ),
.int_trap_ack     (int_trap_ack     ),
.trap_cpu         (trap_cpu         ),
.trap_int         (trap_int         ),
.trap_cause       (trap_cause       ),
.trap_mtval       (trap_mtval       ),
.trap_pc          (trap_pc          ),
.exec_mret        (exec_mret        ),
.csr_mepc         (csr_mepc         ),
.csr_mtvec        (csr_mtvec        ),
.vector_intrs     (vector_intrs     ),
.trs_pc           (trs_pc           ),
.trs_instr        (trs_instr        ),
.trs_valid        (trs_valid        ),
.csr_en           (csr_en           ),
.csr_wr           (csr_wr           ),
.csr_wr_set       (csr_wr_set       ),
.csr_wr_clr       (csr_wr_clr       ),
.csr_addr         (csr_addr         ),
.csr_wdata        (csr_wdata        ),
.csr_rdata        (csr_rdata        ),
.csr_error        (csr_error        ),
.cf_req           (cf_req           ),
.cf_target        (cf_target        ),
.cf_ack           (cf_ack           ),
.hold_lsu_req     (hold_lsu_req     ),
.mmio_rdata       (mmio_rdata       ),
.mmio_error       (mmio_error       ),
.dmem_recv        (dmem_recv        ),
.dmem_ack         (dmem_ack         ),
.dmem_error       (dmem_error       ),
.dmem_rdata       (dmem_rdata       )
);






frv_csrs #(
.XC_CLASS_BASELINE  (XC_CLASS_BASELINE  ),
.XC_CLASS_RANDOMNESS(XC_CLASS_RANDOMNESS),
.XC_CLASS_MEMORY    (XC_CLASS_MEMORY    ),
.XC_CLASS_BIT       (XC_CLASS_BIT       ),
.XC_CLASS_PACKED    (XC_CLASS_PACKED    ),
.XC_CLASS_MULTIARITH(XC_CLASS_MULTIARITH),
.XC_CLASS_AES       (XC_CLASS_AES       ),
.XC_CLASS_SHA2      (XC_CLASS_SHA2      ),
.XC_CLASS_SHA3      (XC_CLASS_SHA3      ),
.XC_CLASS_LEAK      (XC_CLASS_LEAK      ),
.BITMANIP_BASELINE  (BITMANIP_BASELINE  ),
.CSR_MIMPID         (CSR_MIMPID         )
) i_csrs (
.g_clk            (g_clk            ),
.g_resetn         (g_resetn         ),
.csr_en           (csr_en           ),
.csr_wr           (csr_wr           ),
.csr_wr_set       (csr_wr_set       ),
.csr_wr_clr       (csr_wr_clr       ),
.csr_addr         (csr_addr         ),
.csr_wdata        (csr_wdata        ),
.csr_rdata        (csr_rdata        ),
.csr_error        (csr_error        ),
.csr_mepc         (csr_mepc         ),
.csr_mtvec        (csr_mtvec        ),
.vector_intrs     (vector_intrs     ),
.exec_mret        (exec_mret        ),
.mstatus_mie      (mstatus_mie      ),
.mie_meie         (mie_meie         ),
.mie_mtie         (mie_mtie         ),
.mie_msie         (mie_msie         ),
.mip_meip         (mip_meip         ),
.mip_mtip         (mip_mtip         ),
.mip_msip         (mip_msip         ),
.ctr_time         (ctr_time         ),
.ctr_cycle        (ctr_cycle        ),
.ctr_instret      (ctr_instret      ),
.inhibit_cy       (inhibit_cy       ),
.inhibit_tm       (inhibit_tm       ),
.inhibit_ir       (inhibit_ir       ),
.uxcrypto_ct      (uxcrypto_ct      ),
.uxcrypto_b0      (uxcrypto_b0      ),
.uxcrypto_b1      (uxcrypto_b1      ),
.leak_lkgcfg      (leak_lkgcfg      ),
.trap_cpu         (trap_cpu         ),
.trap_int         (trap_int         ),
.trap_cause       (trap_cause       ),
.trap_mtval       (trap_mtval       ),
.trap_pc          (trap_pc          )
);







frv_gprs #(
.BRAM_REGFILE(BRAM_REGFILE)
) i_gprs (
.g_clk      (g_clk          ),
.g_resetn   (g_resetn       ),
.rs1_addr   (s1_rs1_addr    ),
.rs1_data   (s1_rs1_rdata   ),
.rs2_addr   (s1_rs2_addr    ),
.rs2_data   (s1_rs2_rdata   ),
.rs3_addr   (s1_rs3_addr    ),
.rs3_data   (s1_rs3_rdata   ),
.rd_wen     (gpr_wen        ),
.rd_wide    (gpr_wide       ),
.rd_addr    (gpr_rd         ),
.rd_wdata   (gpr_wdata      ),
.rd_wdata_hi(gpr_wdata_hi   )
);

endmodule
module frv_pipeline (

input               g_clk           ,
input               g_resetn        ,

`ifdef RVFI
output [NRET        - 1 : 0] rvfi_valid     ,
output [NRET *   64 - 1 : 0] rvfi_order     ,
output [NRET * ILEN - 1 : 0] rvfi_insn      ,
output [NRET        - 1 : 0] rvfi_trap      ,
output [NRET        - 1 : 0] rvfi_halt      ,
output [NRET        - 1 : 0] rvfi_intr      ,
output [NRET * 2    - 1 : 0] rvfi_mode      ,

output [NRET *    5 - 1 : 0] rvfi_rs1_addr  ,
output [NRET *    5 - 1 : 0] rvfi_rs2_addr  ,
output [NRET *    5 - 1 : 0] rvfi_rs3_addr  ,
output [NRET * XLEN - 1 : 0] rvfi_rs1_rdata ,
output [NRET * XLEN - 1 : 0] rvfi_rs2_rdata ,
output [NRET * XLEN - 1 : 0] rvfi_rs3_rdata ,
output [NRET * XLEN - 1 : 0] rvfi_aux       ,
output [NRET * 32   - 1 : 0] rvfi_rng_data  ,
output [NRET *  3   - 1 : 0] rvfi_rng_stat  ,
output [NRET *    5 - 1 : 0] rvfi_rd_addr   ,
output [NRET        - 1 : 0] rvfi_rd_wide   ,
output [NRET * XLEN - 1 : 0] rvfi_rd_wdata  ,
output [NRET * XLEN - 1 : 0] rvfi_rd_wdatahi,

output [NRET * XLEN - 1 : 0] rvfi_pc_rdata  ,
output [NRET * XLEN - 1 : 0] rvfi_pc_wdata  ,

output [NRET * XLEN  - 1: 0] rvfi_mem_addr  ,
output [NRET * XLEN/8- 1: 0] rvfi_mem_rmask ,
output [NRET * XLEN/8- 1: 0] rvfi_mem_wmask ,
output [NRET * XLEN  - 1: 0] rvfi_mem_rdata ,
output [NRET * XLEN  - 1: 0] rvfi_mem_wdata ,
`endif

output wire [XL:0]  trs_pc          ,
output wire [31:0]  trs_instr       ,
output wire         trs_valid       ,

output wire [XL:0]  leak_prng       ,
output wire         leak_fence_unc0 ,
output wire         leak_fence_unc1 ,
output wire         leak_fence_unc2 ,

output wire         rng_req_valid   ,
output wire [ 2:0]  rng_req_op      ,
output wire [31:0]  rng_req_data    ,
input  wire         rng_req_ready   ,
input  wire         rng_rsp_valid   ,
input  wire [ 2:0]  rng_rsp_status  ,
input  wire [31:0]  rng_rsp_data    ,
output wire         rng_rsp_ready   ,

output wire         instr_ret       ,

output wire         mstatus_mie     ,
output wire         mie_meie        ,
output wire         mie_mtie        ,
output wire         mie_msie        ,

input  wire         mip_meip        ,
input  wire         mip_mtip        ,
input  wire         mip_msip        ,

input  wire [63:0]  ctr_time        ,
input  wire [63:0]  ctr_cycle       ,
input  wire [63:0]  ctr_instret     ,

input  wire         int_trap_req    ,
input  wire [ 5:0]  int_trap_cause  ,
output wire         int_trap_ack    ,

output wire         inhibit_cy      ,
output wire         inhibit_tm      ,
output wire         inhibit_ir      ,

output wire         mmio_en         ,
output wire         mmio_wen        ,
output wire [31:0]  mmio_addr       ,
output wire [31:0]  mmio_wdata      ,
input  wire [31:0]  mmio_rdata      ,
input  wire         mmio_error      ,

output wire         imem_req        ,
output wire         imem_wen        ,
output wire [3:0]   imem_strb       ,
output wire [XL:0]  imem_wdata      ,
output wire [XL:0]  imem_addr       ,
input  wire         imem_gnt        ,
input  wire         imem_recv       ,
output wire         imem_ack        ,
input  wire         imem_error      ,
input  wire [XL:0]  imem_rdata      ,

output wire         dmem_req        ,
output wire         dmem_wen        ,
output wire [3:0]   dmem_strb       ,
output wire [XL:0]  dmem_wdata      ,
output wire [XL:0]  dmem_addr       ,
input  wire         dmem_gnt        ,
input  wire         dmem_recv       ,
output wire         dmem_ack        ,
input  wire         dmem_error      ,
input  wire [XL:0]  dmem_rdata

);



parameter FRV_PC_RESET_VALUE = 32'h8000_0000;


parameter BRAM_REGFILE = 0;


parameter   MMIO_BASE_ADDR        = 32'h0000_1000;
parameter   MMIO_BASE_MASK        = 32'hFFFF_F000;



parameter TRACE_INSTR_WORD = 1'b1;



parameter XC_CLASS_BASELINE   = 1'b1;
parameter XC_CLASS_RANDOMNESS = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_MEMORY     = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_BIT        = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_PACKED     = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_MULTIARITH = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_AES        = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_SHA2       = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_SHA3       = 1'b1 && XC_CLASS_BASELINE;
parameter XC_CLASS_LEAK       = 1'b1 && XC_CLASS_BASELINE;


parameter XC_CLASS_LEAK_STRONG= 1'b1 && XC_CLASS_LEAK;


parameter XC_CLASS_LEAK_BUBBLE= 1'b1 && XC_CLASS_LEAK;


parameter AES_SUB_FAST = 1'b1;
parameter AES_MIX_FAST = 1'b1;



parameter BITMANIP_BASELINE   = 1'b1;



parameter  CSR_MIMPID           = 32'b0;


`include "frv_common.vh"




wire        uxcrypto_ct;
wire [ 7:0] uxcrypto_b0;
wire [ 7:0] uxcrypto_b1;



assign      instr_ret = trs_valid;



wire        cf_req     ;
wire [XL:0] cf_target  ;
wire        cf_ack     ;



wire [12:0] leak_lkgcfg   ;
wire        s1_leak_fence ;



wire        csr_en     ;
wire        csr_wr     ;
wire        csr_wr_set ;
wire        csr_wr_clr ;
wire [11:0] csr_addr   ;
wire [XL:0] csr_wdata  ;
wire [XL:0] csr_rdata  ;
wire        csr_error  ;

wire [XL:0] csr_mepc   ;
wire [XL:0] csr_mtvec  ;
wire        vector_intrs;

wire        exec_mret  ;



wire        trap_cpu   ;
wire        trap_int   ;
wire [ 5:0] trap_cause ;
wire [XL:0] trap_mtval ;
wire [XL:0] trap_pc    ;


wire        s0_flush   = cf_req && cf_ack;
wire        s1_flush   = cf_req && cf_ack;
wire        s2_flush   = cf_req && cf_ack;
wire        s3_flush   = cf_req && cf_ack;
wire        s4_flush   = cf_req && cf_ack;

wire        s0_busy       ;

wire        s1_valid      ;
wire        s1_busy       ;
wire [XL:0] s1_data       ;
wire        s1_error      ;

wire [ 4:0] s1_rs1_addr   ;
wire [ 4:0] s1_rs2_addr   ;
wire [ 4:0] s1_rs3_addr   ;
wire [XL:0] s1_rs1_rdata  ;
wire [XL:0] s1_rs2_rdata  ;
wire [XL:0] s1_rs3_rdata  ;

wire        s2_valid      ;
wire        s2_busy       ;
wire [ 4:0] s2_rd         ;
wire [XL:0] s2_opr_a      ;
wire [XL:0] s2_opr_b      ;
wire [XL:0] s2_opr_c      ;
wire [OP:0] s2_uop        ;
wire [FU:0] s2_fu         ;
wire [PW:0] s2_pw         ;
wire        s2_trap       ;
wire [ 1:0] s2_size       ;
wire [31:0] s2_instr      ;

wire [ 4:0] fwd_s2_rd     ;
wire        fwd_s2_wide   ;
wire [XL:0] fwd_s2_wdata  ;
wire [XL:0] fwd_s2_wdata_hi;
wire        fwd_s2_load   ;
wire        fwd_s2_csr    ;

wire [ 4:0] s3_rd         ;
wire [XL:0] s3_opr_a      ;
wire [XL:0] s3_opr_b      ;
wire [OP:0] s3_uop        ;
wire [FU:0] s3_fu         ;
wire        s3_trap       ;
wire [ 1:0] s3_size       ;
wire [31:0] s3_instr      ;
wire        s3_busy       ;
wire        s3_valid      ;

wire [ 4:0] fwd_s3_rd     ;
wire        fwd_s3_wide   ;
wire [XL:0] fwd_s3_wdata  ;
wire [XL:0] fwd_s3_wdata_hi;
wire        fwd_s3_load   ;
wire        fwd_s3_csr    ;

wire [ 4:0] s4_rd         ;
wire [XL:0] s4_opr_a      ;
wire [XL:0] s4_opr_b      ;
wire [OP:0] s4_uop        ;
wire [FU:0] s4_fu         ;
wire        s4_trap       ;
wire [ 1:0] s4_size       ;
wire [31:0] s4_instr      ;
wire        s4_busy       ;
wire        s4_valid      ;

wire [ 4:0] fwd_s4_rd     ;
wire [XL:0] fwd_s4_wdata  ;
wire        fwd_s4_load   ;
wire        fwd_s4_csr    ;

wire        gpr_wen       ;
wire        gpr_wide      ;
wire [ 4:0] gpr_rd        ;
wire [XL:0] gpr_wdata     ;
wire [XL:0] gpr_wdata_hi  ;

wire        hold_lsu_req  ;

`ifdef RVFI
wire [XL:0] rvfi_s2_rs1_rdata;
wire [XL:0] rvfi_s2_rs2_rdata;
wire [XL:0] rvfi_s2_rs3_rdata;
wire [ 4:0] rvfi_s2_rs1_addr ;
wire [ 4:0] rvfi_s2_rs2_addr ;
wire [ 4:0] rvfi_s2_rs3_addr ;
wire [XL:0] rvfi_s3_rs1_rdata;
wire [XL:0] rvfi_s3_rs2_rdata;
wire [XL:0] rvfi_s3_rs3_rdata;
wire [ 4:0] rvfi_s3_rs1_addr ;
wire [ 4:0] rvfi_s3_rs2_addr ;
wire [ 4:0] rvfi_s3_rs3_addr ;
wire [XL:0] rvfi_s3_aux      ;
wire [31:0] rvfi_s3_rng_data ;
wire [ 2:0] rvfi_s3_rng_stat ;
wire [XL:0] rvfi_s4_rs1_rdata;
wire [XL:0] rvfi_s4_rs2_rdata;
wire [XL:0] rvfi_s4_rs3_rdata;
wire [ 4:0] rvfi_s4_rs1_addr ;
wire [ 4:0] rvfi_s4_rs2_addr ;
wire [ 4:0] rvfi_s4_rs3_addr ;
wire [XL:0] rvfi_s4_aux      ;
wire [31:0] rvfi_s4_rng_data ;
wire [ 2:0] rvfi_s4_rng_stat ;
wire [XL:0] rvfi_s4_mem_wdata;
`endif






wire nz_s1_rs1     = |s1_rs1_addr;
wire nz_s1_rs2     = |s1_rs2_addr;
wire nz_s1_rs3     = |s1_rs3_addr;




`define HAZARD(A, F, NZ, W) (               \
    (A[4:1] == F[4:1]) &&                   \
    (NZ || !NZ && A[0] && !F[0] && W  ) &&  \
    (A[0] == F[0] || A[0] && !F[0] && W)    \
)

wire hzd_rs1_s4 = `HAZARD(s1_rs1_addr, fwd_s4_rd, nz_s1_rs1, gpr_wide   );
wire hzd_rs1_s3 = `HAZARD(s1_rs1_addr, fwd_s3_rd, nz_s1_rs1, fwd_s3_wide);
wire hzd_rs1_s2 = `HAZARD(s1_rs1_addr, fwd_s2_rd, nz_s1_rs1, fwd_s2_wide);

wire hzd_rs2_s4 = `HAZARD(s1_rs2_addr, fwd_s4_rd, nz_s1_rs2, gpr_wide   );
wire hzd_rs2_s3 = `HAZARD(s1_rs2_addr, fwd_s3_rd, nz_s1_rs2, fwd_s3_wide);
wire hzd_rs2_s2 = `HAZARD(s1_rs2_addr, fwd_s2_rd, nz_s1_rs2, fwd_s2_wide);

wire hzd_rs3_s4 = `HAZARD(s1_rs3_addr, fwd_s4_rd, nz_s1_rs3, gpr_wide   );
wire hzd_rs3_s3 = `HAZARD(s1_rs3_addr, fwd_s3_rd, nz_s1_rs3, fwd_s3_wide);
wire hzd_rs3_s2 = `HAZARD(s1_rs3_addr, fwd_s2_rd, nz_s1_rs3, fwd_s2_wide);

`undef HAZARD

wire fwd_s2_rs1_hi = s1_rs1_addr[0] && fwd_s2_wide;
wire fwd_s3_rs1_hi = s1_rs1_addr[0] && fwd_s3_wide;
wire fwd_s4_rs1_hi = s1_rs1_addr[0] && gpr_wide   ;

wire fwd_s2_rs2_hi = s1_rs2_addr[0] && fwd_s2_wide;
wire fwd_s3_rs2_hi = s1_rs2_addr[0] && fwd_s3_wide;
wire fwd_s4_rs2_hi = s1_rs2_addr[0] && gpr_wide   ;

wire fwd_s2_rs3_hi = s1_rs3_addr[0] && fwd_s2_wide;
wire fwd_s3_rs3_hi = s1_rs3_addr[0] && fwd_s3_wide;
wire fwd_s4_rs3_hi = s1_rs3_addr[0] && gpr_wide   ;






wire   s1_bubble_no_instr = !s1_valid && !s2_busy ;
wire   s1_bubble_from_s4  = fwd_s4_csr||(fwd_s4_load && (hzd_rs1_s4 || hzd_rs2_s4 || hzd_rs3_s4));
wire   s1_bubble_from_s3  = fwd_s3_csr||(fwd_s3_load && (hzd_rs1_s3 || hzd_rs2_s3 || hzd_rs3_s3));
wire   s1_bubble_from_s2  = fwd_s2_csr||(fwd_s2_load && (hzd_rs1_s2 || hzd_rs2_s2 || hzd_rs3_s2));
wire   s1_bubble   =
     s1_bubble_no_instr     ||
     s1_bubble_from_s4      ||
     s1_bubble_from_s3      ||
     s1_bubble_from_s2      ;


wire [XL:0] fwd_rs1_rdata =
     hzd_rs1_s2 ? (fwd_s2_rs1_hi ? fwd_s2_wdata_hi : fwd_s2_wdata)  :
     hzd_rs1_s3 ? (fwd_s3_rs1_hi ? fwd_s3_wdata_hi : fwd_s3_wdata)  :
     hzd_rs1_s4 ? (fwd_s4_rs1_hi ? gpr_wdata_hi    : gpr_wdata   )  :
                  s1_rs1_rdata   ;

wire [XL:0] fwd_rs2_rdata =
     hzd_rs2_s2 ? (fwd_s2_rs2_hi ? fwd_s2_wdata_hi : fwd_s2_wdata)  :
     hzd_rs2_s3 ? (fwd_s3_rs2_hi ? fwd_s3_wdata_hi : fwd_s3_wdata)  :
     hzd_rs2_s4 ? (fwd_s4_rs2_hi ? gpr_wdata_hi    : gpr_wdata   )  :
                  s1_rs2_rdata   ;

wire [XL:0] fwd_rs3_rdata =
     hzd_rs3_s2 ? (fwd_s2_rs3_hi ? fwd_s2_wdata_hi : fwd_s2_wdata)  :
     hzd_rs3_s3 ? (fwd_s3_rs3_hi ? fwd_s3_wdata_hi : fwd_s3_wdata)  :
     hzd_rs3_s4 ? (fwd_s4_rs3_hi ? gpr_wdata_hi    : gpr_wdata   )  :
                  s1_rs3_rdata   ;











frv_pipeline_fetch #(
.FRV_PC_RESET_VALUE(FRV_PC_RESET_VALUE)
) i_pipeline_s0_fetch (
.g_clk              (g_clk              ),
.g_resetn           (g_resetn           ),
.cf_req             (cf_req             ),
.cf_target          (cf_target          ),
.cf_ack             (cf_ack             ),
.imem_req           (imem_req           ),
.imem_wen           (imem_wen           ),
.imem_strb          (imem_strb          ),
.imem_wdata         (imem_wdata         ),
.imem_addr          (imem_addr          ),
.imem_gnt           (imem_gnt           ),
.imem_ack           (imem_ack           ),
.imem_recv          (imem_recv          ),
.imem_error         (imem_error         ),
.imem_rdata         (imem_rdata         ),
.s0_flush           (s0_flush           ),
.s1_busy            (s1_busy            ),
.s1_valid           (s1_valid           ),
.s1_data            (s1_data            ),
.s1_error           (s1_error           )
);







frv_pipeline_decode #(
.FRV_PC_RESET_VALUE (FRV_PC_RESET_VALUE ),
.TRACE_INSTR_WORD   (TRACE_INSTR_WORD   ),
.XC_CLASS_BASELINE  (XC_CLASS_BASELINE  ),
.XC_CLASS_RANDOMNESS(XC_CLASS_RANDOMNESS),
.XC_CLASS_MEMORY    (XC_CLASS_MEMORY    ),
.XC_CLASS_BIT       (XC_CLASS_BIT       ),
.XC_CLASS_PACKED    (XC_CLASS_PACKED    ),
.XC_CLASS_MULTIARITH(XC_CLASS_MULTIARITH),
.XC_CLASS_AES       (XC_CLASS_AES       ),
.XC_CLASS_SHA2      (XC_CLASS_SHA2      ),
.XC_CLASS_SHA3      (XC_CLASS_SHA3      ),
.XC_CLASS_LEAK      (XC_CLASS_LEAK      ),
.XC_CLASS_LEAK_STRONG(XC_CLASS_LEAK_STRONG),
.XC_CLASS_LEAK_BUBBLE(XC_CLASS_LEAK_BUBBLE),
.BITMANIP_BASELINE  (BITMANIP_BASELINE  ) 
) i_pipeline_s1_decode (
.g_clk              (g_clk              ),
.g_resetn           (g_resetn           ),
.s1_valid           (s1_valid           ),
.s1_busy            (s1_busy            ),
.s1_data            (s1_data            ),
.s1_error           (s1_error           ),
.s1_flush           (s1_flush           ),
.s1_bubble          (s1_bubble          ),
.s1_rs1_addr        (s1_rs1_addr        ),
.s1_rs2_addr        (s1_rs2_addr        ),
.s1_rs3_addr        (s1_rs3_addr        ),
.s1_rs1_rdata       (fwd_rs1_rdata      ),
.s1_rs2_rdata       (fwd_rs2_rdata      ),
.s1_rs3_rdata       (fwd_rs3_rdata      ),
.leak_prng          (leak_prng          ),
.leak_lkgcfg        (leak_lkgcfg        ),
.s1_leak_fence      (s1_leak_fence      ),
.cf_req             (cf_req             ),
.cf_target          (cf_target          ),
.cf_ack             (cf_ack             ),
`ifdef RVFI
.rvfi_s2_rs1_addr   (rvfi_s2_rs1_addr   ),
.rvfi_s2_rs2_addr   (rvfi_s2_rs2_addr   ),
.rvfi_s2_rs3_addr   (rvfi_s2_rs3_addr   ),
.rvfi_s2_rs1_data   (rvfi_s2_rs1_rdata  ),
.rvfi_s2_rs2_data   (rvfi_s2_rs2_rdata  ),
.rvfi_s2_rs3_data   (rvfi_s2_rs3_rdata  ),
`endif
.s2_valid           (s2_valid           ),
.s2_busy            (s2_busy            ),
.s2_rd              (s2_rd              ),
.s2_opr_a           (s2_opr_a           ),
.s2_opr_b           (s2_opr_b           ),
.s2_opr_c           (s2_opr_c           ),
.s2_uop             (s2_uop             ),
.s2_fu              (s2_fu              ),
.s2_pw              (s2_pw              ),
.s2_trap            (s2_trap            ),
.s2_size            (s2_size            ),
.s2_instr           (s2_instr           )
);






frv_pipeline_execute #(
.XC_CLASS_RANDOMNESS(XC_CLASS_RANDOMNESS),
.XC_CLASS_MEMORY    (XC_CLASS_MEMORY    ),
.XC_CLASS_BIT       (XC_CLASS_BIT       ),
.XC_CLASS_PACKED    (XC_CLASS_PACKED    ),
.XC_CLASS_MULTIARITH(XC_CLASS_MULTIARITH),
.XC_CLASS_AES       (XC_CLASS_AES       ),
.XC_CLASS_SHA2      (XC_CLASS_SHA2      ),
.XC_CLASS_SHA3      (XC_CLASS_SHA3      ),
.AES_SUB_FAST       (AES_SUB_FAST       ),
.AES_MIX_FAST       (AES_MIX_FAST       ),
.BITMANIP_BASELINE  (BITMANIP_BASELINE  ) 
) i_pipeline_s2_execute (
.g_clk            (g_clk            ),
.g_resetn         (g_resetn         ),
.s2_rd            (s2_rd            ),
.s2_opr_a         (s2_opr_a         ),
.s2_opr_b         (s2_opr_b         ),
.s2_opr_c         (s2_opr_c         ),
.s2_uop           (s2_uop           ),
.s2_fu            (s2_fu            ),
.s2_pw            (s2_pw            ),
.s2_trap          (s2_trap          ),
.s2_size          (s2_size          ),
.s2_instr         (s2_instr         ),
.s2_busy          (s2_busy          ),
.s2_valid         (s2_valid         ),
.leak_prng        (leak_prng        ),
.leak_lkgcfg       (leak_lkgcfg       ),
.rng_req_valid    (rng_req_valid    ),
.rng_req_op       (rng_req_op       ),
.rng_req_data     (rng_req_data     ),
.rng_req_ready    (rng_req_ready    ),
.rng_rsp_valid    (rng_rsp_valid    ),
.rng_rsp_status   (rng_rsp_status   ),
.rng_rsp_data     (rng_rsp_data     ),
.rng_rsp_ready    (rng_rsp_ready    ),
.uxcrypto_ct      (uxcrypto_ct      ),
.uxcrypto_b0      (uxcrypto_b0      ),
.uxcrypto_b1      (uxcrypto_b1      ),
.flush            (s2_flush         ),
.fwd_s2_rd        (fwd_s2_rd        ),
.fwd_s2_wide      (fwd_s2_wide      ),
.fwd_s2_wdata     (fwd_s2_wdata     ),
.fwd_s2_wdata_hi  (fwd_s2_wdata_hi  ),
.fwd_s2_load      (fwd_s2_load      ),
.fwd_s2_csr       (fwd_s2_csr       ),
`ifdef RVFI
.rvfi_s2_rs1_rdata(rvfi_s2_rs1_rdata),
.rvfi_s2_rs2_rdata(rvfi_s2_rs2_rdata),
.rvfi_s2_rs3_rdata(rvfi_s2_rs3_rdata),
.rvfi_s2_rs1_addr (rvfi_s2_rs1_addr ),
.rvfi_s2_rs2_addr (rvfi_s2_rs2_addr ),
.rvfi_s2_rs3_addr (rvfi_s2_rs3_addr ),
.rvfi_s3_rs1_rdata(rvfi_s3_rs1_rdata),
.rvfi_s3_rs2_rdata(rvfi_s3_rs2_rdata),
.rvfi_s3_rs3_rdata(rvfi_s3_rs3_rdata),
.rvfi_s3_rs1_addr (rvfi_s3_rs1_addr ),
.rvfi_s3_rs2_addr (rvfi_s3_rs2_addr ),
.rvfi_s3_rs3_addr (rvfi_s3_rs3_addr ),
.rvfi_s3_aux      (rvfi_s3_aux      ),
.rvfi_s3_rng_data (rvfi_s3_rng_data ), 
.rvfi_s3_rng_stat (rvfi_s3_rng_stat ), 
`endif
.s3_rd            (s3_rd            ),
.s3_opr_a         (s3_opr_a         ),
.s3_opr_b         (s3_opr_b         ),
.s3_uop           (s3_uop           ),
.s3_fu            (s3_fu            ),
.s3_trap          (s3_trap          ),
.s3_size          (s3_size          ),
.s3_instr         (s3_instr         ),
.s3_busy          (s3_busy          ),
.s3_valid         (s3_valid         )
);







frv_pipeline_memory #(
.MMIO_BASE_ADDR(MMIO_BASE_ADDR),
.MMIO_BASE_MASK(MMIO_BASE_MASK)
) i_pipeline_s3_memory(
.g_clk            (g_clk            ),
.g_resetn         (g_resetn         ),
.flush            (s3_flush         ),
.s3_rd            (s3_rd            ),
.s3_opr_a         (s3_opr_a         ),
.s3_opr_b         (s3_opr_b         ),
.s3_uop           (s3_uop           ),
.s3_fu            (s3_fu            ),
.s3_trap          (s3_trap          ),
.s3_size          (s3_size          ),
.s3_instr         (s3_instr         ),
.s3_busy          (s3_busy          ),
.s3_valid         (s3_valid         ),
.leak_prng        (leak_prng        ),
.leak_lkgcfg       (leak_lkgcfg       ),
.leak_fence_unc0  (leak_fence_unc0  ),
.leak_fence_unc1  (leak_fence_unc1  ),
.leak_fence_unc2  (leak_fence_unc2  ),
.fwd_s3_rd        (fwd_s3_rd        ),
.fwd_s3_wide      (fwd_s3_wide      ),
.fwd_s3_wdata     (fwd_s3_wdata     ),
.fwd_s3_wdata_hi  (fwd_s3_wdata_hi  ),
.fwd_s3_load      (fwd_s3_load      ),
.fwd_s3_csr       (fwd_s3_csr       ),
`ifdef RVFI
.rvfi_s3_rs1_rdata(rvfi_s3_rs1_rdata),
.rvfi_s3_rs2_rdata(rvfi_s3_rs2_rdata),
.rvfi_s3_rs3_rdata(rvfi_s3_rs3_rdata),
.rvfi_s3_rs1_addr (rvfi_s3_rs1_addr ),
.rvfi_s3_rs2_addr (rvfi_s3_rs2_addr ),
.rvfi_s3_rs3_addr (rvfi_s3_rs3_addr ),
.rvfi_s3_aux      (rvfi_s3_aux      ),
.rvfi_s3_rng_data (rvfi_s3_rng_data ), 
.rvfi_s3_rng_stat (rvfi_s3_rng_stat ), 
.rvfi_s4_rs1_rdata(rvfi_s4_rs1_rdata),
.rvfi_s4_rs2_rdata(rvfi_s4_rs2_rdata),
.rvfi_s4_rs3_rdata(rvfi_s4_rs3_rdata),
.rvfi_s4_rs1_addr (rvfi_s4_rs1_addr ),
.rvfi_s4_rs2_addr (rvfi_s4_rs2_addr ),
.rvfi_s4_rs3_addr (rvfi_s4_rs3_addr ),
.rvfi_s4_aux      (rvfi_s4_aux      ),
.rvfi_s4_rng_data (rvfi_s4_rng_data ), 
.rvfi_s4_rng_stat (rvfi_s4_rng_stat ), 
.rvfi_s4_mem_wdata(rvfi_s4_mem_wdata),
`endif
.hold_lsu_req     (hold_lsu_req     ),
.mmio_en          (mmio_en          ),
.mmio_wen         (mmio_wen         ),
.mmio_addr        (mmio_addr        ),
.mmio_wdata       (mmio_wdata       ),
.dmem_req         (dmem_req         ),
.dmem_wen         (dmem_wen         ),
.dmem_strb        (dmem_strb        ),
.dmem_wdata       (dmem_wdata       ),
.dmem_addr        (dmem_addr        ),
.dmem_gnt         (dmem_gnt         ),
.s4_rd            (s4_rd            ),
.s4_opr_a         (s4_opr_a         ),
.s4_opr_b         (s4_opr_b         ),
.s4_uop           (s4_uop           ),
.s4_fu            (s4_fu            ),
.s4_trap          (s4_trap          ),
.s4_size          (s4_size          ),
.s4_instr         (s4_instr         ),
.s4_busy          (s4_busy          ),
.s4_valid         (s4_valid         )
);










frv_pipeline_writeback #(
.FRV_PC_RESET_VALUE(FRV_PC_RESET_VALUE)
) i_pipeline_s4_writeback(
.g_clk            (g_clk            ),
.g_resetn         (g_resetn         ),
`ifdef RVFI
.rvfi_valid       (rvfi_valid       ),
.rvfi_order       (rvfi_order       ),
.rvfi_insn        (rvfi_insn        ),
.rvfi_trap        (rvfi_trap        ),
.rvfi_halt        (rvfi_halt        ),
.rvfi_intr        (rvfi_intr        ),
.rvfi_mode        (rvfi_mode        ),
.rvfi_rs1_addr    (rvfi_rs1_addr    ),
.rvfi_rs2_addr    (rvfi_rs2_addr    ),
.rvfi_rs3_addr    (rvfi_rs3_addr    ),
.rvfi_rs1_rdata   (rvfi_rs1_rdata   ),
.rvfi_rs2_rdata   (rvfi_rs2_rdata   ),
.rvfi_rs3_rdata   (rvfi_rs3_rdata   ),
.rvfi_aux         (rvfi_aux         ),
.rvfi_rng_data    (rvfi_rng_data    ), 
.rvfi_rng_stat    (rvfi_rng_stat    ), 
.rvfi_rd_addr     (rvfi_rd_addr     ),
.rvfi_rd_wide     (rvfi_rd_wide     ),
.rvfi_rd_wdata    (rvfi_rd_wdata    ),
.rvfi_rd_wdatahi  (rvfi_rd_wdatahi  ),
.rvfi_pc_rdata    (rvfi_pc_rdata    ),
.rvfi_pc_wdata    (rvfi_pc_wdata    ),
.rvfi_mem_addr    (rvfi_mem_addr    ),
.rvfi_mem_rmask   (rvfi_mem_rmask   ),
.rvfi_mem_wmask   (rvfi_mem_wmask   ),
.rvfi_mem_rdata   (rvfi_mem_rdata   ),
.rvfi_mem_wdata   (rvfi_mem_wdata   ),
.rvfi_s4_rs1_rdata(rvfi_s4_rs1_rdata),
.rvfi_s4_rs2_rdata(rvfi_s4_rs2_rdata),
.rvfi_s4_rs3_rdata(rvfi_s4_rs3_rdata),
.rvfi_s4_rs1_addr (rvfi_s4_rs1_addr ),
.rvfi_s4_rs2_addr (rvfi_s4_rs2_addr ),
.rvfi_s4_rs3_addr (rvfi_s4_rs3_addr ),
.rvfi_s4_aux      (rvfi_s4_aux      ),
.rvfi_s4_rng_data (rvfi_s4_rng_data ), 
.rvfi_s4_rng_stat (rvfi_s4_rng_stat ), 
.rvfi_s4_mem_wdata(rvfi_s4_mem_wdata),
`endif
.s4_rd            (s4_rd            ),
.s4_opr_a         (s4_opr_a         ),
.s4_opr_b         (s4_opr_b         ),
.s4_uop           (s4_uop           ),
.s4_fu            (s4_fu            ),
.s4_trap          (s4_trap          ),
.s4_size          (s4_size          ),
.s4_instr         (s4_instr         ),
.s4_busy          (s4_busy          ),
.s4_valid         (s4_valid         ),
.fwd_s4_rd        (fwd_s4_rd        ),
.fwd_s4_wdata     (fwd_s4_wdata     ),
.fwd_s4_load      (fwd_s4_load      ),
.fwd_s4_csr       (fwd_s4_csr       ),
.gpr_wen          (gpr_wen          ),
.gpr_wide         (gpr_wide         ),
.gpr_rd           (gpr_rd           ),
.gpr_wdata        (gpr_wdata        ),
.gpr_wdata_hi     (gpr_wdata_hi     ),
.int_trap_req     (int_trap_req     ),
.int_trap_cause   (int_trap_cause   ),
.int_trap_ack     (int_trap_ack     ),
.trap_cpu         (trap_cpu         ),
.trap_int         (trap_int         ),
.trap_cause       (trap_cause       ),
.trap_mtval       (trap_mtval       ),
.trap_pc          (trap_pc          ),
.exec_mret        (exec_mret        ),
.csr_mepc         (csr_mepc         ),
.csr_mtvec        (csr_mtvec        ),
.vector_intrs     (vector_intrs     ),
.trs_pc           (trs_pc           ),
.trs_instr        (trs_instr        ),
.trs_valid        (trs_valid        ),
.csr_en           (csr_en           ),
.csr_wr           (csr_wr           ),
.csr_wr_set       (csr_wr_set       ),
.csr_wr_clr       (csr_wr_clr       ),
.csr_addr         (csr_addr         ),
.csr_wdata        (csr_wdata        ),
.csr_rdata        (csr_rdata        ),
.csr_error        (csr_error        ),
.cf_req           (cf_req           ),
.cf_target        (cf_target        ),
.cf_ack           (cf_ack           ),
.hold_lsu_req     (hold_lsu_req     ),
.mmio_rdata       (mmio_rdata       ),
.mmio_error       (mmio_error       ),
.dmem_recv        (dmem_recv        ),
.dmem_ack         (dmem_ack         ),
.dmem_error       (dmem_error       ),
.dmem_rdata       (dmem_rdata       )
);






frv_csrs #(
.XC_CLASS_BASELINE  (XC_CLASS_BASELINE  ),
.XC_CLASS_RANDOMNESS(XC_CLASS_RANDOMNESS),
.XC_CLASS_MEMORY    (XC_CLASS_MEMORY    ),
.XC_CLASS_BIT       (XC_CLASS_BIT       ),
.XC_CLASS_PACKED    (XC_CLASS_PACKED    ),
.XC_CLASS_MULTIARITH(XC_CLASS_MULTIARITH),
.XC_CLASS_AES       (XC_CLASS_AES       ),
.XC_CLASS_SHA2      (XC_CLASS_SHA2      ),
.XC_CLASS_SHA3      (XC_CLASS_SHA3      ),
.XC_CLASS_LEAK      (XC_CLASS_LEAK      ),
.BITMANIP_BASELINE  (BITMANIP_BASELINE  ),
.CSR_MIMPID         (CSR_MIMPID         )
) i_csrs (
.g_clk            (g_clk            ),
.g_resetn         (g_resetn         ),
.csr_en           (csr_en           ),
.csr_wr           (csr_wr           ),
.csr_wr_set       (csr_wr_set       ),
.csr_wr_clr       (csr_wr_clr       ),
.csr_addr         (csr_addr         ),
.csr_wdata        (csr_wdata        ),
.csr_rdata        (csr_rdata        ),
.csr_error        (csr_error        ),
.csr_mepc         (csr_mepc         ),
.csr_mtvec        (csr_mtvec        ),
.vector_intrs     (vector_intrs     ),
.exec_mret        (exec_mret        ),
.mstatus_mie      (mstatus_mie      ),
.mie_meie         (mie_meie         ),
.mie_mtie         (mie_mtie         ),
.mie_msie         (mie_msie         ),
.mip_meip         (mip_meip         ),
.mip_mtip         (mip_mtip         ),
.mip_msip         (mip_msip         ),
.ctr_time         (ctr_time         ),
.ctr_cycle        (ctr_cycle        ),
.ctr_instret      (ctr_instret      ),
.inhibit_cy       (inhibit_cy       ),
.inhibit_tm       (inhibit_tm       ),
.inhibit_ir       (inhibit_ir       ),
.uxcrypto_ct      (uxcrypto_ct      ),
.uxcrypto_b0      (uxcrypto_b0      ),
.uxcrypto_b1      (uxcrypto_b1      ),
.leak_lkgcfg      (leak_lkgcfg      ),
.trap_cpu         (trap_cpu         ),
.trap_int         (trap_int         ),
.trap_cause       (trap_cause       ),
.trap_mtval       (trap_mtval       ),
.trap_pc          (trap_pc          )
);







frv_gprs #(
.BRAM_REGFILE(BRAM_REGFILE)
) i_gprs (
.g_clk      (g_clk          ),
.g_resetn   (g_resetn       ),
.rs1_addr   (s1_rs1_addr    ),
.rs1_data   (s1_rs1_rdata   ),
.rs2_addr   (s1_rs2_addr    ),
.rs2_data   (s1_rs2_rdata   ),
.rs3_addr   (s1_rs3_addr    ),
.rs3_data   (s1_rs3_rdata   ),
.rd_wen     (gpr_wen        ),
.rd_wide    (gpr_wide       ),
.rd_addr    (gpr_rd         ),
.rd_wdata   (gpr_wdata      ),
.rd_wdata_hi(gpr_wdata_hi   )
);

endmodule