data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:37: Signal definition not found, creating implicitly: \'tx_spi_sclk_wire\'\n                                                                                      : ... Suggested alternative: \'tx_spi_sclk\'\nassign tx_spi_sclk = tx_spi_sclk_wire;     \n                     ^~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:85: Signal definition not found, creating implicitly: \'uart_tx_wire\'\n                                                                                      : ... Suggested alternative: \'uart_counter_wire\'\nalways@(*) uart_tx = uart_tx_wire;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:19: Cannot find file containing module: \'clockpll\'\nclockpll pll(.globalclock(globalclock),  \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114379717/bjt_encapsulated,data/full_repos/permissive/114379717/clockpll\n             data/full_repos/permissive/114379717/bjt_encapsulated,data/full_repos/permissive/114379717/clockpll.v\n             data/full_repos/permissive/114379717/bjt_encapsulated,data/full_repos/permissive/114379717/clockpll.sv\n             clockpll\n             clockpll.v\n             clockpll.sv\n             obj_dir/clockpll\n             obj_dir/clockpll.v\n             obj_dir/clockpll.sv\n%Error: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:27: Cannot find file containing module: \'DAC_control\'\nDAC_control DAC_control_inst(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:43: Cannot find file containing module: \'ADC_control\'\nADC_control ADC_control_inst(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:64: Cannot find file containing module: \'FIFO_control\'\nFIFO_control FIFO_control_inst(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:76: Cannot find file containing module: \'uart_control\'\nuart_control uart_control_inst(\n^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module bjt(input globalclock,
	input rst,
	output tx_spi_sclk,
	output tx_spi_sync,
	output tx_spi_din,
	output ADC_CONVST,
	output ADC_SCK,
	output ADC_SDI,
	input wire ADC_SDO,
	output reg uart_tx
	);

wire [31:0] verti_counter;
wire [3:0] serial_counter;

clockpll pll(.globalclock(globalclock),
	.rst(rst),
	.dac_clk(tx_spi_sclk_wire),
	.adc_clk(adc_clk),
	.adc_clk_delay(adc_clk_delay),
	.uart_clk(UART_CLK)
	);

DAC_control DAC_control_inst(
	.tx_spi_sclk_wire(tx_spi_sclk_wire),
	.rst(rst),
	.tx_spi_sync(tx_spi_sync),
	.tx_spi_din(tx_spi_din),
	.adc_start(adc_start),
	.verti_counter(verti_counter),
	.serial_counter(serial_counter),
	.loop(loop)
	);
assign	tx_spi_sclk = tx_spi_sclk_wire;


wire [23:0] fifo_data;
wire [11:0] measure_count;

ADC_control ADC_control_inst(
	.adc_clk(adc_clk),
	.adc_clk_delay(adc_clk_delay),
	.adc_start(adc_start),
	.ADC_CONVST(ADC_CONVST),
	.ADC_SCK(ADC_SCK),
	.ADC_SDI(ADC_SDI),
	.ADC_SDO(ADC_SDO),
	.rst(rst),
	.loop(loop),
	.serial_counter(serial_counter),
	.verti_counter(verti_counter),
	.fifo_data(fifo_data),
	.measure_count(measure_count),
	.measure_done(measure_done));


wire [1:0] uart_counter_wire; 
wire [23:0] q_sig_wire;

wire idle;
FIFO_control FIFO_control_inst(
	.tx_spi_sclk_wire(tx_spi_sclk_wire),
	.rst(rst),
	.idle(idle),
	.uart_counter(uart_counter_wire),
	.serial_counter(serial_counter),
	.measure_count(measure_count),
	.fifo_data(fifo_data),
	.measure_done(measure_done),
	.q_sig_wire(q_sig_wire));


uart_control uart_control_inst(
	.globalclock(globalclock),
	.verti_counter(verti_counter),
	.UART_CLK(UART_CLK),
	.rst(rst),
	.q_sig(q_sig_wire),
	.uart_tx_wire(uart_tx_wire),
	.idle(idle),
	.uart_counter(uart_counter_wire));
always@(*) uart_tx = uart_tx_wire;
endmodule
module bjt(input globalclock,
	input rst,
	output tx_spi_sclk,
	output tx_spi_sync,
	output tx_spi_din,
	output ADC_CONVST,
	output ADC_SCK,
	output ADC_SDI,
	input wire ADC_SDO,
	output reg uart_tx
	);


wire [31:0] verti_counter;
wire [3:0] serial_counter;

clockpll pll(.globalclock(globalclock),
	.rst(rst),
	.dac_clk(tx_spi_sclk_wire),
	.adc_clk(adc_clk),
	.adc_clk_delay(adc_clk_delay),
	.uart_clk(UART_CLK)
	);

DAC_control DAC_control_inst(
	.tx_spi_sclk_wire(tx_spi_sclk_wire),
	.rst(rst),
	.tx_spi_sync(tx_spi_sync),
	.tx_spi_din(tx_spi_din),
	.adc_start(adc_start),
	.verti_counter(verti_counter),
	.serial_counter(serial_counter),
	.loop(loop)
	);
assign	tx_spi_sclk = tx_spi_sclk_wire;


wire [23:0] fifo_data;
wire [11:0] measure_count;

ADC_control ADC_control_inst(
	.adc_clk(adc_clk),
	.adc_clk_delay(adc_clk_delay),
	.adc_start(adc_start),
	.ADC_CONVST(ADC_CONVST),
	.ADC_SCK(ADC_SCK),
	.ADC_SDI(ADC_SDI),
	.ADC_SDO(ADC_SDO),
	.rst(rst),
	.loop(loop),
	.serial_counter(serial_counter),
	.verti_counter(verti_counter),
	.fifo_data(fifo_data),
	.measure_count(measure_count),
	.measure_done(measure_done));


wire [1:0] uart_counter_wire; 
wire [23:0] q_sig_wire;

wire idle;
FIFO_control FIFO_control_inst(
	.tx_spi_sclk_wire(tx_spi_sclk_wire),
	.rst(rst),
	.idle(idle),
	.uart_counter(uart_counter_wire),
	.serial_counter(serial_counter),
	.measure_count(measure_count),
	.fifo_data(fifo_data),
	.measure_done(measure_done),
	.q_sig_wire(q_sig_wire));


uart_control uart_control_inst(
	.globalclock(globalclock),
	.verti_counter(verti_counter),
	.UART_CLK(UART_CLK),
	.rst(rst),
	.q_sig(q_sig_wire),
	.uart_tx_wire(uart_tx_wire),
	.idle(idle),
	.uart_counter(uart_counter_wire));
always@(*) uart_tx = uart_tx_wire;
endmodule