data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/fifo_1clk.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/fifo_1clk.v:25: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
function automatic [AddrBits:0] inc(input en, input phase,
                                      input [AddrBits-1:0] addr);
    reg [AddrBits-1:0] addr_n;
    reg                phase_n;
    begin
      addr_n  = addr;
      phase_n = phase;
      if (en) begin
        if (addr == Depth-1) begin
          addr_n  = 0;
          phase_n = ~phase;
        end else begin
          addr_n = addr + 1;
        end
      end
      inc = {phase_n, addr_n};
    end
  endfunction
function automatic [AddrBits:0] inc(input en, input phase,
                                      input [AddrBits-1:0] addr);

    reg [AddrBits-1:0] addr_n;
    reg                phase_n;
    begin
      addr_n  = addr;
      phase_n = phase;
      if (en) begin
        if (addr == Depth-1) begin
          addr_n  = 0;
          phase_n = ~phase;
        end else begin
          addr_n = addr + 1;
        end
      end
      inc = {phase_n, addr_n};
    end
  endfunction