data/full_repos/permissive/20401628/TESTBENCH.v
 line:146: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_mosi = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10 cs = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #40 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #20 cs = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_mosi = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10 cs = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #40 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #50 spi_clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #20 cs = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #16 pclk = ~pclk;\n  ^\n%Error: data/full_repos/permissive/20401628/TESTBENCH.v:142: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/20401628/TESTBENCH.v:143: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/20401628/TESTBENCH.v:149: syntax error, unexpected \'@\'\n  repeat (1 * Tline) @(negedge pclk);\n                     ^\n%Error: data/full_repos/permissive/20401628/TESTBENCH.v:151: syntax error, unexpected \'@\'\n  repeat (3 * Tline) @(negedge pclk);\n                     ^\n%Error: data/full_repos/permissive/20401628/TESTBENCH.v:155: syntax error, unexpected \'@\'\n   repeat (640 * 2) @(negedge pclk);\n                    ^\n%Error: data/full_repos/permissive/20401628/TESTBENCH.v:157: syntax error, unexpected \'@\'\n   repeat (144 * 2) @(negedge pclk);\n                    ^\n%Error: data/full_repos/permissive/20401628/TESTBENCH.v:160: syntax error, unexpected \'@\'\n  repeat (10 * Tline) @(negedge pclk);\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:144: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/20401628/TESTBENCH.v:163: Unsupported: Ignoring delay on this delayed statement.\n #100 $stop;\n ^\n%Error: Exiting due to 7 error(s), 42 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

wire button;
reg clk;


reg href;
reg vsync;
reg pclk;
reg [7:0] data;


parameter Tline = 786 * 2;

reg spi_clk,
		spi_mosi,
		cs;

initial begin
	forever begin
		spi_clk = 0;
		spi_mosi = 0;
		cs = 1;

		#50 spi_mosi = 1;
		#10 cs = 0;
		#40 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;
		#20 cs = 1;

		spi_clk = 0;
		spi_mosi = 0;
		cs = 1;

		#50 spi_mosi = 0;
		#10 cs = 0;
		#40 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;
		#20 cs = 1;
	end
end

initial begin
	clk = 0;
	data = 0;
	forever begin
		#1 clk = ~clk;
	end
end

initial begin
	pclk = 1;
	forever begin
		#16 pclk = ~pclk;
	end
end

always @(negedge pclk) begin
		data <= data + 8'b1;
end

always @(posedge href) begin
		data <= 8'h00;
end

always @(negedge href) begin
		data <= 8'hxx;
end

initial begin
	$dumpfile("test.vcd");
	$dumpvars(0, test);
#10

	repeat (10) begin
		vsync = 1;
		href = 0;
		repeat (1 * Tline) @(negedge pclk);
		vsync <= 0;
		repeat (3 * Tline) @(negedge pclk);

		repeat (480) begin
			href <= 1;
			repeat (640 * 2) @(negedge pclk);
			href <= 0;
			repeat (144 * 2) @(negedge pclk);
		end

		repeat (10 * Tline) @(negedge pclk);
	end

	#100 $stop;
end

wire capture;
wire [7:0] led;
wire busy;
wire locked;

balldetector bd0 (
	.inclk(clk),
	.ahref(href),
	.avsync(vsync),
	.apclk(pclk),
	.xclk(xclk),
	.adata(data),
	.spi_clk(spi_clk),
	.spi_miso(spi_miso),
	.spi_mosi(spi_mosi),
	.cs(cs),
	.led(led),
	.i2c_clk(i2c_clk),
	.i2c_sda(i2c_sda),
	.busy(busy),
	.pwm0(pwm)
);

endmodule
module test;


wire button;
reg clk;


reg href;
reg vsync;
reg pclk;
reg [7:0] data;


parameter Tline = 786 * 2;

reg spi_clk,
		spi_mosi,
		cs;

initial begin
	forever begin
		spi_clk = 0;
		spi_mosi = 0;
		cs = 1;

		#50 spi_mosi = 1;
		#10 cs = 0;
		#40 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;
		#20 cs = 1;

		spi_clk = 0;
		spi_mosi = 0;
		cs = 1;

		#50 spi_mosi = 0;
		#10 cs = 0;
		#40 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 0;
		#50 spi_clk = 1;
		#50 spi_clk = 0;


		spi_mosi = 1;
		#50 spi_clk = 1;
		#50 spi_clk = 0;
		#20 cs = 1;
	end
end

initial begin
	clk = 0;
	data = 0;
	forever begin
		#1 clk = ~clk;
	end
end

initial begin
	pclk = 1;
	forever begin
		#16 pclk = ~pclk;
	end
end

always @(negedge pclk) begin
		data <= data + 8'b1;
end

always @(posedge href) begin
		data <= 8'h00;
end

always @(negedge href) begin
		data <= 8'hxx;
end

initial begin
	$dumpfile("test.vcd");
	$dumpvars(0, test);
#10

	repeat (10) begin
		vsync = 1;
		href = 0;
		repeat (1 * Tline) @(negedge pclk);
		vsync <= 0;
		repeat (3 * Tline) @(negedge pclk);

		repeat (480) begin
			href <= 1;
			repeat (640 * 2) @(negedge pclk);
			href <= 0;
			repeat (144 * 2) @(negedge pclk);
		end

		repeat (10 * Tline) @(negedge pclk);
	end

	#100 $stop;
end

wire capture;
wire [7:0] led;
wire busy;
wire locked;

balldetector bd0 (
	.inclk(clk),
	.ahref(href),
	.avsync(vsync),
	.apclk(pclk),
	.xclk(xclk),
	.adata(data),
	.spi_clk(spi_clk),
	.spi_miso(spi_miso),
	.spi_mosi(spi_mosi),
	.cs(cs),
	.led(led),
	.i2c_clk(i2c_clk),
	.i2c_sda(i2c_sda),
	.busy(busy),
	.pwm0(pwm)
);

endmodule