data/full_repos/permissive/157049472/Verilog Test Benches/Register_Bank_tb.v
1: b'%Error: Cannot find file containing module: Test\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Test\n             data/full_repos/permissive/157049472/Verilog/Test.v\n             data/full_repos/permissive/157049472/Verilog/Test.sv\n             Test\n             Test.v\n             Test.sv\n             obj_dir/Test\n             obj_dir/Test.v\n             obj_dir/Test.sv\n%Error: Cannot find file containing module: Benches,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Benches/Register_Bank_tb.v\n%Error: Exiting due to 4 error(s)\n'
module Register_Bank_tb;


	reg clk;
	reg rst;
	reg regWriteEnable;
	reg [31:0] regWriteData;
	reg [4:0] regAddr_1;
	reg [4:0] regAddr_2;


	wire [31:0] regReadData_1;
	wire [31:0] regReadData_2;


	RegisterBank uut (
		.clk(clk), 
		.rst(rst), 
		.regWriteEnable(regWriteEnable), 
		.regWriteData(regWriteData), 
		.regAddr_1(regAddr_1), 
		.regReadData_1(regReadData_1), 
		.regAddr_2(regAddr_2), 
		.regReadData_2(regReadData_2)
	);

	initial begin

		clk = 0;
		rst = 0;
		regWriteEnable = 0;
		regWriteData = 0;
		regAddr_1 = 0;
		regAddr_2 = 0;


		#100;
      rst = 1;
		#10;
		rst = 0;
		
		#10;
		regWriteEnable = 0;
		regWriteData = 143434;
		regAddr_1 = 28;
		regAddr_2 = 30;
		
		#10;
		regWriteEnable = 1;
		regWriteData = 143434;
		regAddr_1 = 28;	
		regAddr_2 = 30;
		
		#10
		regWriteEnable = 1;
		regWriteData = 143434;
		regAddr_1 = 30;
		regAddr_2 = 28;


	end
    always begin
		#5 clk = ~clk;
	end
endmodule
module Register_Bank_tb;



	reg clk;
	reg rst;
	reg regWriteEnable;
	reg [31:0] regWriteData;
	reg [4:0] regAddr_1;
	reg [4:0] regAddr_2;


	wire [31:0] regReadData_1;
	wire [31:0] regReadData_2;


	RegisterBank uut (
		.clk(clk), 
		.rst(rst), 
		.regWriteEnable(regWriteEnable), 
		.regWriteData(regWriteData), 
		.regAddr_1(regAddr_1), 
		.regReadData_1(regReadData_1), 
		.regAddr_2(regAddr_2), 
		.regReadData_2(regReadData_2)
	);

	initial begin

		clk = 0;
		rst = 0;
		regWriteEnable = 0;
		regWriteData = 0;
		regAddr_1 = 0;
		regAddr_2 = 0;


		#100;
      rst = 1;
		#10;
		rst = 0;
		
		#10;
		regWriteEnable = 0;
		regWriteData = 143434;
		regAddr_1 = 28;
		regAddr_2 = 30;
		
		#10;
		regWriteEnable = 1;
		regWriteData = 143434;
		regAddr_1 = 28;	
		regAddr_2 = 30;
		
		#10
		regWriteEnable = 1;
		regWriteData = 143434;
		regAddr_1 = 30;
		regAddr_2 = 28;


	end
    always begin
		#5 clk = ~clk;
	end
endmodule