data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:71: Multiple top level modules\n                                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                             : ... Top module \'simd_mult_explicit_ports\'\nmodule simd_mult_explicit_ports (\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                             : ... Top module \'simd_mult_explicit_params\'\nmodule simd_mult_explicit_params (\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                             : ... Top module \'simd_mult_inferred\'\nmodule simd_mult_inferred (\n       ^~~~~~~~~~~~~~~~~~\n                                                                                                             : ... Top module \'simd_mult_odd_ports\'\nmodule simd_mult_odd_ports (\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                                             : ... Top module \'simd_mult_odd_params\'\nmodule simd_mult_odd_params (\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                                             : ... Top module \'simd_mult_conflict_ports\'\nmodule simd_mult_conflict_ports (\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                             : ... Top module \'simd_mult_conflict_config\'\nmodule simd_mult_conflict_config (\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:374: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_ports\'\n    dsp_t1_10x9x32_cfg_ports dsp_0 (\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd,data/full_repos/permissive/220229160/dsp_t1_10x9x32_cfg_ports\n             data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd,data/full_repos/permissive/220229160/dsp_t1_10x9x32_cfg_ports.v\n             data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd,data/full_repos/permissive/220229160/dsp_t1_10x9x32_cfg_ports.sv\n             dsp_t1_10x9x32_cfg_ports\n             dsp_t1_10x9x32_cfg_ports.v\n             dsp_t1_10x9x32_cfg_ports.sv\n             obj_dir/dsp_t1_10x9x32_cfg_ports\n             obj_dir/dsp_t1_10x9x32_cfg_ports.v\n             obj_dir/dsp_t1_10x9x32_cfg_ports.sv\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:394: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_ports\'\n    dsp_t1_10x9x32_cfg_ports dsp_1 (\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:319: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_ports\'\n    dsp_t1_10x9x32_cfg_ports dsp_0 (\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:339: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_ports\'\n    dsp_t1_10x9x32_cfg_ports dsp_1 (\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:241: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_params\'\n    dsp_t1_10x9x32_cfg_params #(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:262: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_params\'\n    dsp_t1_10x9x32_cfg_params #(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:283: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_params\'\n    dsp_t1_10x9x32_cfg_params #(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:163: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_ports\'\n    dsp_t1_10x9x32_cfg_ports dsp_0 (\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:183: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_ports\'\n    dsp_t1_10x9x32_cfg_ports dsp_1 (\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:203: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_ports\'\n    dsp_t1_10x9x32_cfg_ports dsp_2 (\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:83: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_params\'\n    dsp_t1_10x9x32_cfg_params #(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:104: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_params\'\n    dsp_t1_10x9x32_cfg_params #(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:29: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_ports\'\n    dsp_t1_10x9x32_cfg_ports dsp_0 (\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v:49: Cannot find file containing module: \'dsp_t1_10x9x32_cfg_ports\'\n    dsp_t1_10x9x32_cfg_ports dsp_1 (\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s), 1 warning(s)\n'
module simd_mult_odd_params (
    input  wire         clk,

    input  wire [ 7:0]  a0,
    input  wire [ 7:0]  b0,
    output wire [15:0]  z0,

    input  wire [ 7:0]  a1,
    input  wire [ 7:0]  b1,
    output wire [15:0]  z1,

    input  wire [ 7:0]  a2,
    input  wire [ 7:0]  b2,
    output wire [15:0]  z2
);

    dsp_t1_10x9x32_cfg_params #(
        .OUTPUT_SELECT      (3'd0),
        .SATURATE_ENABLE    (1'b0),
        .SHIFT_RIGHT        (6'd0),
        .ROUND              (1'b0),
        .REGISTER_INPUTS    (1'b1)
    ) dsp_0 (
        .a_i    (a0),
        .b_i    (b0),
        .z_o    (z0),

        .clock_i            (clk),

        .feedback_i         (3'd0),
        .load_acc_i         (1'b0),
        .unsigned_a_i       (1'b1),
        .unsigned_b_i       (1'b1),

        .subtract_i         (1'b0)
    );

    dsp_t1_10x9x32_cfg_params #(
        .OUTPUT_SELECT      (3'd0),
        .SATURATE_ENABLE    (1'b0),
        .SHIFT_RIGHT        (6'd0),
        .ROUND              (1'b0),
        .REGISTER_INPUTS    (1'b1)
    ) dsp_1 (
        .a_i    (a1),
        .b_i    (b1),
        .z_o    (z1),

        .clock_i            (clk),

        .feedback_i         (3'd0),
        .load_acc_i         (1'b0),
        .unsigned_a_i       (1'b1),
        .unsigned_b_i       (1'b1),

        .subtract_i         (1'b0)
    );

    dsp_t1_10x9x32_cfg_params #(
        .OUTPUT_SELECT      (3'd0),
        .SATURATE_ENABLE    (1'b0),
        .SHIFT_RIGHT        (6'd0),
        .ROUND              (1'b0),
        .REGISTER_INPUTS    (1'b1)
    ) dsp_2 (
        .a_i    (a2),
        .b_i    (b2),
        .z_o    (z2),

        .clock_i            (clk),

        .feedback_i         (3'd0),
        .load_acc_i         (1'b0),
        .unsigned_a_i       (1'b1),
        .unsigned_b_i       (1'b1),

        .subtract_i         (1'b0)
    );

endmodule
module simd_mult_odd_params (
    input  wire         clk,

    input  wire [ 7:0]  a0,
    input  wire [ 7:0]  b0,
    output wire [15:0]  z0,

    input  wire [ 7:0]  a1,
    input  wire [ 7:0]  b1,
    output wire [15:0]  z1,

    input  wire [ 7:0]  a2,
    input  wire [ 7:0]  b2,
    output wire [15:0]  z2
);


    dsp_t1_10x9x32_cfg_params #(
        .OUTPUT_SELECT      (3'd0),
        .SATURATE_ENABLE    (1'b0),
        .SHIFT_RIGHT        (6'd0),
        .ROUND              (1'b0),
        .REGISTER_INPUTS    (1'b1)
    ) dsp_0 (
        .a_i    (a0),
        .b_i    (b0),
        .z_o    (z0),

        .clock_i            (clk),

        .feedback_i         (3'd0),
        .load_acc_i         (1'b0),
        .unsigned_a_i       (1'b1),
        .unsigned_b_i       (1'b1),

        .subtract_i         (1'b0)
    );

    dsp_t1_10x9x32_cfg_params #(
        .OUTPUT_SELECT      (3'd0),
        .SATURATE_ENABLE    (1'b0),
        .SHIFT_RIGHT        (6'd0),
        .ROUND              (1'b0),
        .REGISTER_INPUTS    (1'b1)
    ) dsp_1 (
        .a_i    (a1),
        .b_i    (b1),
        .z_o    (z1),

        .clock_i            (clk),

        .feedback_i         (3'd0),
        .load_acc_i         (1'b0),
        .unsigned_a_i       (1'b1),
        .unsigned_b_i       (1'b1),

        .subtract_i         (1'b0)
    );

    dsp_t1_10x9x32_cfg_params #(
        .OUTPUT_SELECT      (3'd0),
        .SATURATE_ENABLE    (1'b0),
        .SHIFT_RIGHT        (6'd0),
        .ROUND              (1'b0),
        .REGISTER_INPUTS    (1'b1)
    ) dsp_2 (
        .a_i    (a2),
        .b_i    (b2),
        .z_o    (z2),

        .clock_i            (clk),

        .feedback_i         (3'd0),
        .load_acc_i         (1'b0),
        .unsigned_a_i       (1'b1),
        .unsigned_b_i       (1'b1),

        .subtract_i         (1'b0)
    );

endmodule