data/full_repos/permissive/216192770/Ram.v
data/verilator_xmls/e0d6eac3-ed71-42f5-ac7a-990cf753d510.xml
module Ram
(
	input [15:0] data,
    output reg [15:0] q,
	input [7:0] addr,
    input cs,
	input we, 
    input re
);


	reg [15:0] ram[0:255];


    always@(posedge we) 
        if(cs)
            ram[addr] <= data;
        else
            ram[addr] <= ram[addr];

    always@(posedge re)
        if(cs)
            q <= ram[addr];
        else
            q <= q;


endmodule
module Ram
(
	input [15:0] data,
    output reg [15:0] q,
	input [7:0] addr,
    input cs,
	input we, 
    input re
);



	reg [15:0] ram[0:255];


    always@(posedge we) 
        if(cs)
            ram[addr] <= data;
        else
            ram[addr] <= ram[addr];

    always@(posedge re)
        if(cs)
            q <= ram[addr];
        else
            q <= q;


endmodule