data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/ddr_io.v
None: at end of input
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/ddr_io.v:54: Cannot find file containing module: 'FDDRRSE'\n FDDRRSE odata_fddr0 (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/FDDRRSE\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/FDDRRSE.v\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/FDDRRSE.sv\n             FDDRRSE\n             FDDRRSE.v\n             FDDRRSE.sv\n             obj_dir/FDDRRSE\n             obj_dir/FDDRRSE.v\n             obj_dir/FDDRRSE.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/ddr_io.v:66: Cannot find file containing module: 'IFDDRRSE'\n IFDDRRSE idata_fddr0 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/ddr_io.v:81: Cannot find file containing module: 'OBUFT'\n OBUFT #(4.0) data_obuf0 (\n ^~~~~\n%Error: Exiting due to 3 error(s)\n"
module ddr_io (
		clk_i,
		clk_ni,
		
		send_i,
		cap_i,
		dqs_i,
		data_i,
		data_o,
		
		ddr_io
	);
	
	input	clk_i;
	input	clk_ni;
	
	input	send_i;
	input	cap_i;
	input	dqs_i;
	input	[1:0]	data_i;
	output	[1:0]	data_o;
	
	inout	ddr_io;
	
	
	wire	ddr_dq_w;
	
	

	FDDRRSE odata_fddr0 (
		.C0	(clk_ni),
		.C1	(clk_i),
		.CE	(1'b1),
		.D0	(data_i [0]),
		.D1	(data_i [1]),
		.R	(1'b0),
		.S	(1'b0),
		.Q	(ddr_dq_w)
	);
	

	IFDDRRSE idata_fddr0 (
		.C0	(dqs_i),
		.C1	(~dqs_i),
		.CE	(cap_i),
		.D	(ddr_io),
		.R	(1'b0),
		.S	(1'b0),
		.Q0	(data_o [0]),
		.Q1	(data_o [1])
	);
	

	


	OBUFT #(4.0) data_obuf0 (
		.T	(send_i),
		.I	(ddr_dq_w),
		.O	(ddr_io)
	);
	
endmodule
module ddr_io (
		clk_i,
		clk_ni,
		
		send_i,
		cap_i,
		dqs_i,
		data_i,
		data_o,
		
		ddr_io
	);

	
	input	clk_i;
	input	clk_ni;
	
	input	send_i;
	input	cap_i;
	input	dqs_i;
	input	[1:0]	data_i;
	output	[1:0]	data_o;
	
	inout	ddr_io;
	
	
	wire	ddr_dq_w;
	
	

	FDDRRSE odata_fddr0 (
		.C0	(clk_ni),
		.C1	(clk_i),
		.CE	(1'b1),
		.D0	(data_i [0]),
		.D1	(data_i [1]),
		.R	(1'b0),
		.S	(1'b0),
		.Q	(ddr_dq_w)
	);
	

	IFDDRRSE idata_fddr0 (
		.C0	(dqs_i),
		.C1	(~dqs_i),
		.CE	(cap_i),
		.D	(ddr_io),
		.R	(1'b0),
		.S	(1'b0),
		.Q0	(data_o [0]),
		.Q1	(data_o [1])
	);
	

	


	OBUFT #(4.0) data_obuf0 (
		.T	(send_i),
		.I	(ddr_dq_w),
		.O	(ddr_io)
	);
	
endmodule