data/full_repos/permissive/123075301/welcome_text.v
1: b'%Error: data/full_repos/permissive/123075301/welcome_text.v:45: Cannot find file containing module: \'Font_ROM\'\n Font_ROM font_unit( .pixel_clock(clk),\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123075301,data/full_repos/permissive/123075301/Font_ROM\n             data/full_repos/permissive/123075301,data/full_repos/permissive/123075301/Font_ROM.v\n             data/full_repos/permissive/123075301,data/full_repos/permissive/123075301/Font_ROM.sv\n             Font_ROM\n             Font_ROM.v\n             Font_ROM.sv\n             obj_dir/Font_ROM\n             obj_dir/Font_ROM.v\n             obj_dir/Font_ROM.sv\n%Warning-LITENDIAN: data/full_repos/permissive/123075301/welcome_text.v:54: Little bit endian vector: MSB < LSB of bit range: 0:79\n wire [0:8*10-1] welcome_text = " WELCOME ";\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/123075301/welcome_text.v:61: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                      : ... In instance welcome_text\n      i=pix_x[9:6];\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/123075301/welcome_text.v:72: Little bit endian vector: MSB < LSB of bit range: 0:159\n wire [0:8*20-1] minor_text = "   MINOR  PROJECT   ";\n      ^\n%Warning-WIDTH: data/full_repos/permissive/123075301/welcome_text.v:79: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                      : ... In instance welcome_text\n      j=pix_x[9:5];\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/123075301/welcome_text.v:92: Little bit endian vector: MSB < LSB of bit range: 0:255\n wire [0:8*32-1] aman_text   = "AMAN KANDOI       - 403";\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/123075301/welcome_text.v:93: Little bit endian vector: MSB < LSB of bit range: 0:255\n wire [0:8*32-1] bibek_text  = "BIBEK BHATTARAI   - 409";\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/123075301/welcome_text.v:94: Little bit endian vector: MSB < LSB of bit range: 0:255\n wire [0:8*32-1] bipin_text  = "BIPIN THAPA MAGAR - 413";\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/123075301/welcome_text.v:95: Little bit endian vector: MSB < LSB of bit range: 0:255\n wire [0:8*32-1] naresh_text = "NARESH KUMAR GIRI - 416";\n      ^\n%Warning-WIDTH: data/full_repos/permissive/123075301/welcome_text.v:102: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                       : ... In instance welcome_text\n     k=pix_x[8:4];\n      ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n'
module welcome_text
	(
	input wire clk,
	input wire [9:0] pix_x, pix_y,
	input wire video_on,
	output reg [2:0] text_rgb
	);
	
	wire [10:0] rom_addr;
	reg [7:0] char_addr, char_addr_w, char_addr_m, char_addr_nam;
	reg [2:0] row_addr;
	wire [2:0] row_addr_w, row_addr_m, row_addr_nam;
	
	reg [2:0] bit_addr;
	wire [2:0] bit_addr_w, bit_addr_m, bit_addr_nam;
	wire [7:0] font_word;
	wire font_bit, wel_on, min_on, nam_on;
	wire [6:0]rom_addr_nam;
	
			
	assign  rom_addr = {char_addr,row_addr};
	assign  font_bit = font_word[~bit_addr];
	

	Font_ROM font_unit( .pixel_clock(clk),
								.address(rom_addr),
								.data(font_word)
								);

	assign wel_on = (pix_y[9:6] == 1);
	assign row_addr_w = pix_y[5:3];
	assign bit_addr_w = pix_x[5:3];
	integer i =0;
	wire [0:8*10-1] welcome_text = " WELCOME ";
	always@(posedge clk)
	begin
		if(pix_y[9:6] == 1)
			begin
				if((pix_x[9:6] >=0)&& (pix_x[9:6]<=9))
				begin
						i=pix_x[9:6];
						char_addr_w = welcome_text[i*8+:8];
				end
				else  char_addr_w = 8'b0;
			end
	end

	assign min_on = (pix_y[9:5] == 6) ;
	assign row_addr_m = pix_y[4:2];
	assign bit_addr_m = pix_x[4:2];
	integer j =0;
	wire [0:8*20-1] minor_text = "   MINOR  PROJECT   ";
	always@(posedge clk)
	begin
		if(pix_y[9:5] == 6)
			begin
				if((pix_x[9:5] >=0)&& (pix_x[9:5]<=19))
				begin
						j=pix_x[9:5];
						char_addr_m = minor_text[j*8+:8];
				end
				else 	char_addr_m = 8'b0;
			end
	end


	assign nam_on = ((pix_y[9:6] == 5) && (pix_x[9] == 0));
	assign row_addr_nam = pix_y[3:1];
	assign bit_addr_nam = pix_x[3:1];

	integer k =0;
	wire [0:8*32-1] aman_text   = "AMAN KANDOI       - 403";
	wire [0:8*32-1] bibek_text  = "BIBEK BHATTARAI   - 409";
	wire [0:8*32-1] bipin_text  = "BIPIN THAPA MAGAR - 413";
	wire [0:8*32-1] naresh_text = "NARESH KUMAR GIRI - 416";
	always@(posedge clk)
	begin
		if(pix_y[9:6] == 5)
			begin
				if(pix_x[9] == 0)
				begin
					k=pix_x[8:4];
					if(pix_y[5:4]==2'b00)
							char_addr_nam = aman_text[k*8+:8];
					else if(pix_y[5:4]== 2'b01)
							char_addr_nam = bibek_text[k*8+:8];
					else if(pix_y[5:4]==2'b10)
							char_addr_nam = bipin_text[k*8+:8];
					else if(pix_y[5:4] == 2'b11)
							char_addr_nam = naresh_text[k*8+:8];
					else
							char_addr_nam = 8'h0;
					
				end
			end
	end



		always @(posedge clk)
			begin
			if(video_on)
				begin
				text_rgb	= 3'b111;
				if(wel_on)
					begin
						char_addr = char_addr_w;
						row_addr  = row_addr_w;
						bit_addr  = bit_addr_w;
						if(font_bit)
							text_rgb = 3'b100;
					end
				else if(min_on)
					begin
						char_addr = char_addr_m;
						row_addr  = row_addr_m;
						bit_addr  = bit_addr_m;
						if(font_bit)
							text_rgb = 3'b110;
					end
				else if(nam_on)
					begin
						char_addr = char_addr_nam;
						row_addr  = row_addr_nam;
						bit_addr  = bit_addr_nam;
						if(font_bit)
							text_rgb = 3'b000;
					end
				else;
				end
				
				else
					text_rgb = 3'b000;
		end

endmodule
module welcome_text
	(
	input wire clk,
	input wire [9:0] pix_x, pix_y,
	input wire video_on,
	output reg [2:0] text_rgb
	);

	
	wire [10:0] rom_addr;
	reg [7:0] char_addr, char_addr_w, char_addr_m, char_addr_nam;
	reg [2:0] row_addr;
	wire [2:0] row_addr_w, row_addr_m, row_addr_nam;
	
	reg [2:0] bit_addr;
	wire [2:0] bit_addr_w, bit_addr_m, bit_addr_nam;
	wire [7:0] font_word;
	wire font_bit, wel_on, min_on, nam_on;
	wire [6:0]rom_addr_nam;
	
			
	assign  rom_addr = {char_addr,row_addr};
	assign  font_bit = font_word[~bit_addr];
	

	Font_ROM font_unit( .pixel_clock(clk),
								.address(rom_addr),
								.data(font_word)
								);

	assign wel_on = (pix_y[9:6] == 1);
	assign row_addr_w = pix_y[5:3];
	assign bit_addr_w = pix_x[5:3];
	integer i =0;
	wire [0:8*10-1] welcome_text = " WELCOME ";
	always@(posedge clk)
	begin
		if(pix_y[9:6] == 1)
			begin
				if((pix_x[9:6] >=0)&& (pix_x[9:6]<=9))
				begin
						i=pix_x[9:6];
						char_addr_w = welcome_text[i*8+:8];
				end
				else  char_addr_w = 8'b0;
			end
	end

	assign min_on = (pix_y[9:5] == 6) ;
	assign row_addr_m = pix_y[4:2];
	assign bit_addr_m = pix_x[4:2];
	integer j =0;
	wire [0:8*20-1] minor_text = "   MINOR  PROJECT   ";
	always@(posedge clk)
	begin
		if(pix_y[9:5] == 6)
			begin
				if((pix_x[9:5] >=0)&& (pix_x[9:5]<=19))
				begin
						j=pix_x[9:5];
						char_addr_m = minor_text[j*8+:8];
				end
				else 	char_addr_m = 8'b0;
			end
	end


	assign nam_on = ((pix_y[9:6] == 5) && (pix_x[9] == 0));
	assign row_addr_nam = pix_y[3:1];
	assign bit_addr_nam = pix_x[3:1];

	integer k =0;
	wire [0:8*32-1] aman_text   = "AMAN KANDOI       - 403";
	wire [0:8*32-1] bibek_text  = "BIBEK BHATTARAI   - 409";
	wire [0:8*32-1] bipin_text  = "BIPIN THAPA MAGAR - 413";
	wire [0:8*32-1] naresh_text = "NARESH KUMAR GIRI - 416";
	always@(posedge clk)
	begin
		if(pix_y[9:6] == 5)
			begin
				if(pix_x[9] == 0)
				begin
					k=pix_x[8:4];
					if(pix_y[5:4]==2'b00)
							char_addr_nam = aman_text[k*8+:8];
					else if(pix_y[5:4]== 2'b01)
							char_addr_nam = bibek_text[k*8+:8];
					else if(pix_y[5:4]==2'b10)
							char_addr_nam = bipin_text[k*8+:8];
					else if(pix_y[5:4] == 2'b11)
							char_addr_nam = naresh_text[k*8+:8];
					else
							char_addr_nam = 8'h0;
					
				end
			end
	end



		always @(posedge clk)
			begin
			if(video_on)
				begin
				text_rgb	= 3'b111;
				if(wel_on)
					begin
						char_addr = char_addr_w;
						row_addr  = row_addr_w;
						bit_addr  = bit_addr_w;
						if(font_bit)
							text_rgb = 3'b100;
					end
				else if(min_on)
					begin
						char_addr = char_addr_m;
						row_addr  = row_addr_m;
						bit_addr  = bit_addr_m;
						if(font_bit)
							text_rgb = 3'b110;
					end
				else if(nam_on)
					begin
						char_addr = char_addr_nam;
						row_addr  = row_addr_nam;
						bit_addr  = bit_addr_nam;
						if(font_bit)
							text_rgb = 3'b000;
					end
				else;
				end
				
				else
					text_rgb = 3'b000;
		end

endmodule