data/full_repos/permissive/192346182/Program_Counter.v
data/verilator_xmls/ebf0d229-2ec9-46ff-a7b4-e6c38f4d97b9.xml
module Program_Counter (
	input Interrupt,
	input Reset,
	input Slow_Clock,
	input Halt,
	input [12:0] NextPC,
	output reg [12:0] PC
);

reg Lock = 0;

always @ (Halt)
begin
	if (Halt)
		Lock = 1;
	else
		Lock = 0;
end

always @(posedge Slow_Clock) begin
	if (Reset)
	begin
		PC = 0;
	end
	else if (!Lock && !Interrupt)
	begin
		PC = NextPC[12:0];
	end
end


endmodule
module Program_Counter (
	input Interrupt,
	input Reset,
	input Slow_Clock,
	input Halt,
	input [12:0] NextPC,
	output reg [12:0] PC
);


reg Lock = 0;

always @ (Halt)
begin
	if (Halt)
		Lock = 1;
	else
		Lock = 0;
end

always @(posedge Slow_Clock) begin
	if (Reset)
	begin
		PC = 0;
	end
	else if (!Lock && !Interrupt)
	begin
		PC = NextPC[12:0];
	end
end


endmodule