data/full_repos/permissive/208741034/eeprom/rtl/i2c_eeprom_wr.v
data/verilator_xmls/773999de-42c0-49f5-9b9c-586f5efa04d6.xml
module eeprom_rw(

    input                 clk        ,
    input                 rst_n      ,


    output                i2c_rh_wl  ,
    output   reg          i2c_exec   ,
    output   reg  [15:0]  i2c_addr   ,
    output   reg  [ 7:0]  i2c_data_w ,
    input         [ 7:0]  i2c_data_r ,
    input                 i2c_done   ,


    output   reg          error_flag
);


parameter      WAIT    = 14'd5000    ;
parameter      BYTE_N  = 16'd255     ;


reg            addr_over ;
reg            rom_w_done;
reg   [ 1:0]   flow_cnt  ;
reg   [13:0]   wait_cnt  ;






assign i2c_rh_wl = addr_over & rom_w_done;


always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
        i2c_addr <= 16'd0;
        addr_over<=  1'b0;
    end
    else if(i2c_done  == 1'b1) begin
         if(i2c_rh_wl == 1'b1) begin
             if(i2c_addr  < BYTE_N)
                 i2c_addr <= i2c_addr + 1'd1;
             else
                 i2c_addr <= i2c_addr;
         end
         else begin
             if(i2c_addr == BYTE_N) begin
                 i2c_addr <= 16'd0;
                 addr_over<=  1'b1;
             end
             else
                 i2c_addr <= i2c_addr + 1'd1;
         end
    end
    else
        i2c_addr <= i2c_addr;
end


always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
        flow_cnt   <=  2'b0;
        wait_cnt   <= 14'b0;
        i2c_exec   <=  1'b0;
        i2c_data_w <=  8'd0;
        rom_w_done <=  1'b0;
        error_flag <=  1'b1;
    end
    else begin
        i2c_exec <= 1'b0;

        if(i2c_rh_wl == 1'b0) begin
            case(flow_cnt)
                2'd0: begin
                    rom_w_done  <=  1'b0;
                    wait_cnt    <= wait_cnt + 1'b1;
                    if(wait_cnt == 14'd100) begin
                        wait_cnt <= 14'd0;
                        flow_cnt <= flow_cnt + 1'b1;
                    end
                end
                2'd1: begin
                    i2c_exec   <= 1'b1;
                    i2c_data_w <= i2c_addr[7:0];
                    flow_cnt   <= flow_cnt + 1'b1;
                end
                2'd2: begin
                    if(i2c_done == 1'b1)
                        flow_cnt   <= flow_cnt + 1'b1;
                end
                2'd3:begin
                    if(wait_cnt == WAIT) begin
                        flow_cnt   <=  2'b0;
                        wait_cnt   <= 14'd0;
                        rom_w_done <=  1'b1;
                    end
                    else
                        wait_cnt <= wait_cnt + 1'b1;
                end
            endcase
        end

        else begin
            case(flow_cnt)
                2'd0: begin
                    wait_cnt <= wait_cnt + 1'b1;
                    if(wait_cnt == 14'd100) begin
                        flow_cnt <= flow_cnt + 1'b1;
                        wait_cnt <= 14'd0;
                    end
                end
                2'd1: begin
                    i2c_exec <= 1'b1;
                    flow_cnt <= flow_cnt + 1'b1;
                end
                2'd2: begin
                    if(i2c_done == 1'b1) begin
                        if(i2c_addr[7:0] == i2c_data_r) begin
                            error_flag   <= 1'b0;
                            flow_cnt     <= 2'b0;
                        end
                        else begin
                            error_flag <= 1'b1;
                        end
                    end
                end
                default: flow_cnt <= 2'b0;
            endcase
        end
    end
end

endmodule
module eeprom_rw(

    input                 clk        ,
    input                 rst_n      ,


    output                i2c_rh_wl  ,
    output   reg          i2c_exec   ,
    output   reg  [15:0]  i2c_addr   ,
    output   reg  [ 7:0]  i2c_data_w ,
    input         [ 7:0]  i2c_data_r ,
    input                 i2c_done   ,


    output   reg          error_flag
);



parameter      WAIT    = 14'd5000    ;
parameter      BYTE_N  = 16'd255     ;


reg            addr_over ;
reg            rom_w_done;
reg   [ 1:0]   flow_cnt  ;
reg   [13:0]   wait_cnt  ;






assign i2c_rh_wl = addr_over & rom_w_done;


always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
        i2c_addr <= 16'd0;
        addr_over<=  1'b0;
    end
    else if(i2c_done  == 1'b1) begin
         if(i2c_rh_wl == 1'b1) begin
             if(i2c_addr  < BYTE_N)
                 i2c_addr <= i2c_addr + 1'd1;
             else
                 i2c_addr <= i2c_addr;
         end
         else begin
             if(i2c_addr == BYTE_N) begin
                 i2c_addr <= 16'd0;
                 addr_over<=  1'b1;
             end
             else
                 i2c_addr <= i2c_addr + 1'd1;
         end
    end
    else
        i2c_addr <= i2c_addr;
end


always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
        flow_cnt   <=  2'b0;
        wait_cnt   <= 14'b0;
        i2c_exec   <=  1'b0;
        i2c_data_w <=  8'd0;
        rom_w_done <=  1'b0;
        error_flag <=  1'b1;
    end
    else begin
        i2c_exec <= 1'b0;

        if(i2c_rh_wl == 1'b0) begin
            case(flow_cnt)
                2'd0: begin
                    rom_w_done  <=  1'b0;
                    wait_cnt    <= wait_cnt + 1'b1;
                    if(wait_cnt == 14'd100) begin
                        wait_cnt <= 14'd0;
                        flow_cnt <= flow_cnt + 1'b1;
                    end
                end
                2'd1: begin
                    i2c_exec   <= 1'b1;
                    i2c_data_w <= i2c_addr[7:0];
                    flow_cnt   <= flow_cnt + 1'b1;
                end
                2'd2: begin
                    if(i2c_done == 1'b1)
                        flow_cnt   <= flow_cnt + 1'b1;
                end
                2'd3:begin
                    if(wait_cnt == WAIT) begin
                        flow_cnt   <=  2'b0;
                        wait_cnt   <= 14'd0;
                        rom_w_done <=  1'b1;
                    end
                    else
                        wait_cnt <= wait_cnt + 1'b1;
                end
            endcase
        end

        else begin
            case(flow_cnt)
                2'd0: begin
                    wait_cnt <= wait_cnt + 1'b1;
                    if(wait_cnt == 14'd100) begin
                        flow_cnt <= flow_cnt + 1'b1;
                        wait_cnt <= 14'd0;
                    end
                end
                2'd1: begin
                    i2c_exec <= 1'b1;
                    flow_cnt <= flow_cnt + 1'b1;
                end
                2'd2: begin
                    if(i2c_done == 1'b1) begin
                        if(i2c_addr[7:0] == i2c_data_r) begin
                            error_flag   <= 1'b0;
                            flow_cnt     <= 2'b0;
                        end
                        else begin
                            error_flag <= 1'b1;
                        end
                    end
                end
                default: flow_cnt <= 2'b0;
            endcase
        end
    end
end

endmodule