data/full_repos/permissive/116266634/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/116266634/ALU.v:42: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                             : ... In instance ALU\n  4\'b0111:   result = (data1 < data2);\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116266634/ALU.v:43: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                             : ... In instance ALU\n  4\'b0110:  result = (data1 < data2);\n                   ^\n%Error: Exiting due to 2 warning(s)\n'
module ALU
(
	input [31:0] data1, data2,
	input [3:0] ALUOp,
	input [4:0] shamt,
	output reg [31:0] result,
	output reg zero,
	output reg overflow
);

always @ (*) begin

	case (ALUOp)
		`ADD:		
				begin
				result = $signed(data1) + $signed(data2);
				overflow = (data1[31] && data2[31] && ~result[31]) || (~data1[31] && ~data2[31] && result[31]);
				end
					
		`ADDU:		begin
				result = $unsigned(data1) + $unsigned(data2);
				end
		`AND:		result = data1 & data2;
		`NOR:		result = ~(data1 | data2);
		`OR:		result = data1 | data2;
		`SLL:		result = data2 << shamt;
		`SRL:		result = data2 >> shamt;
		`SLT: 		result = (data1 < data2);
		`SLTU:		result = (data1 < data2);
		
		`SUB:		begin
				result = $signed(data1) - $signed(data2);
				overflow = (data1[31] && data2[31] && ~result[31]) || (~data1[31] && ~data2[31] && result[31]);
				end
		`SUBU:		result = $unsigned(data1) - $unsigned(data2);
		`SRA:		result = data2 >>> shamt;
		
		`LUI:		begin
				result[31:16] = data1[15:0];
				result[15:0] = 16'b0000000000000000;
				end
	
	endcase
	zero = (result == 32'b0) && (~overflow);
end

endmodule
module ALU
(
	input [31:0] data1, data2,
	input [3:0] ALUOp,
	input [4:0] shamt,
	output reg [31:0] result,
	output reg zero,
	output reg overflow
);


always @ (*) begin

	case (ALUOp)
		`ADD:		
				begin
				result = $signed(data1) + $signed(data2);
				overflow = (data1[31] && data2[31] && ~result[31]) || (~data1[31] && ~data2[31] && result[31]);
				end
					
		`ADDU:		begin
				result = $unsigned(data1) + $unsigned(data2);
				end
		`AND:		result = data1 & data2;
		`NOR:		result = ~(data1 | data2);
		`OR:		result = data1 | data2;
		`SLL:		result = data2 << shamt;
		`SRL:		result = data2 >> shamt;
		`SLT: 		result = (data1 < data2);
		`SLTU:		result = (data1 < data2);
		
		`SUB:		begin
				result = $signed(data1) - $signed(data2);
				overflow = (data1[31] && data2[31] && ~result[31]) || (~data1[31] && ~data2[31] && result[31]);
				end
		`SUBU:		result = $unsigned(data1) - $unsigned(data2);
		`SRA:		result = data2 >>> shamt;
		
		`LUI:		begin
				result[31:16] = data1[15:0];
				result[15:0] = 16'b0000000000000000;
				end
	
	endcase
	zero = (result == 32'b0) && (~overflow);
end

endmodule