data/full_repos/permissive/211316121/lab5_1/FlipFlop.v
data/verilator_xmls/d8ef6967-f9c6-4ff4-9a6d-83398a96c8b5.xml
module TFF(
	input t,
	input clk,
	input clr,
	input set,
	output reg q,
	output nq
);

always@(posedge clk,posedge set,posedge clr)
begin
	if(set)
		q<=1;
	else if(clr)
		q<=0;
	else
		q<=q^t;
end
assign nq=~q;

endmodule
module TFF(
	input t,
	input clk,
	input clr,
	input set,
	output reg q,
	output nq
);


always@(posedge clk,posedge set,posedge clr)
begin
	if(set)
		q<=1;
	else if(clr)
		q<=0;
	else
		q<=q^t;
end
assign nq=~q;

endmodule