data/full_repos/permissive/174263347/JamaOneChip/hdl/memory.v
data/verilator_xmls/f77f22f2-5d56-44eb-b1a6-997ff3d69505.xml
module memory(  clk, reset, wrVga, dVga, aVga, dCga, aCga, 
                dMemIn, dMemOut, aMem, dirout, nCsMem, nOeMem, nWeMem, t3, halfclk, wrVgaReq );

    input   clk;
    input   reset;

    input   wrVga;
    input   [7:0]  dVga;
    input   [15:0] aVga;

    output  [7:0]  dCga;
    input   [15:0] aCga;

    input   [7:0]  dMemIn;
    output  [7:0]  dMemOut;
    output  [15:0] aMem;
    output  dirout;
    output  nCsMem, nOeMem, nWeMem;

    output  t3;
	output	halfclk;
    output  wrVgaReq;

    reg wrRequest;
    reg wrCycle;
    




    reg     [1:0] state;
    wire    t0, t1, t2;

    always @ ( posedge clk )
    begin
            state <= state + 1;
    end

    assign  t0 = (state == 2'b00);
    assign  t1 = (state == 2'b01);
    assign  t2 = (state == 2'b10);
    assign  t3 = (state == 2'b11);
    assign halfclk = state[0];
    assign  wrVgaReq = t3 & wrCycle;





    reg [7:0] wrBuf;

    always @ ( posedge clk )
    begin
        if (wrVga)
            wrBuf <= dVga;
    end

    assign dMemOut = wrBuf; 





    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            wrRequest <= 0;
        else        
            if (wrVga & ~wrCycle)
                wrRequest <= 1;
            else if (~wrVga & wrCycle)
                wrRequest <= 0;
    end





    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            wrCycle <= 0;
        else if (t3)
            wrCycle <= wrRequest;
    end
	
	assign dirout = wrCycle;





    assign aMem = wrCycle ? aVga : aCga;





    reg [7:0] rdBuf;

    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            rdBuf <= 0;
        else if (t3 & ~wrCycle)
            rdBuf <= dMemIn;
    end
    
    assign dCga = rdBuf;





    reg csMem, oeMem, weMem;

    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            csMem <= 1;
        else if (t0)
            csMem <= 0;
        else if (t3)
            csMem <= 1;
    end

    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            oeMem <= 1;
        else if (t0 & ~wrCycle)
            oeMem <= 0;
        else if (t3)
            oeMem <= 1;
    end

    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            weMem <= 1;
        else if (t0 & wrCycle)
            weMem <= 0;
        else if (t3)
            weMem <= 1;
    end

    assign nOeMem = oeMem;
    assign nWeMem = weMem;
    assign nCsMem = csMem;

endmodule
module memory(  clk, reset, wrVga, dVga, aVga, dCga, aCga, 
                dMemIn, dMemOut, aMem, dirout, nCsMem, nOeMem, nWeMem, t3, halfclk, wrVgaReq );


    input   clk;
    input   reset;

    input   wrVga;
    input   [7:0]  dVga;
    input   [15:0] aVga;

    output  [7:0]  dCga;
    input   [15:0] aCga;

    input   [7:0]  dMemIn;
    output  [7:0]  dMemOut;
    output  [15:0] aMem;
    output  dirout;
    output  nCsMem, nOeMem, nWeMem;

    output  t3;
	output	halfclk;
    output  wrVgaReq;

    reg wrRequest;
    reg wrCycle;
    




    reg     [1:0] state;
    wire    t0, t1, t2;

    always @ ( posedge clk )
    begin
            state <= state + 1;
    end

    assign  t0 = (state == 2'b00);
    assign  t1 = (state == 2'b01);
    assign  t2 = (state == 2'b10);
    assign  t3 = (state == 2'b11);
    assign halfclk = state[0];
    assign  wrVgaReq = t3 & wrCycle;





    reg [7:0] wrBuf;

    always @ ( posedge clk )
    begin
        if (wrVga)
            wrBuf <= dVga;
    end

    assign dMemOut = wrBuf; 





    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            wrRequest <= 0;
        else        
            if (wrVga & ~wrCycle)
                wrRequest <= 1;
            else if (~wrVga & wrCycle)
                wrRequest <= 0;
    end





    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            wrCycle <= 0;
        else if (t3)
            wrCycle <= wrRequest;
    end
	
	assign dirout = wrCycle;





    assign aMem = wrCycle ? aVga : aCga;





    reg [7:0] rdBuf;

    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            rdBuf <= 0;
        else if (t3 & ~wrCycle)
            rdBuf <= dMemIn;
    end
    
    assign dCga = rdBuf;





    reg csMem, oeMem, weMem;

    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            csMem <= 1;
        else if (t0)
            csMem <= 0;
        else if (t3)
            csMem <= 1;
    end

    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            oeMem <= 1;
        else if (t0 & ~wrCycle)
            oeMem <= 0;
        else if (t3)
            oeMem <= 1;
    end

    always @ ( posedge clk or posedge reset )
    begin
        if (reset)
            weMem <= 1;
        else if (t0 & wrCycle)
            weMem <= 0;
        else if (t3)
            weMem <= 1;
    end

    assign nOeMem = oeMem;
    assign nWeMem = weMem;
    assign nCsMem = csMem;

endmodule