data/full_repos/permissive/129155059/proyecto-02/all/fifo_cond.v
1: b'%Warning-WIDTH: data/full_repos/permissive/129155059/proyecto-02/all/fifo_cond.v:59: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'cantWr\' generates 3 bits.\n                                                                                   : ... In instance fifo_cond\n            if (cantWr == DATA_WIDTH-1) begin  \n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/129155059/proyecto-02/all/fifo_cond.v:99: Operator LT expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'cantWr\' generates 3 bits.\n                                                                                   : ... In instance fifo_cond\n      if ((umbFull <= cantWr)&&(cantWr < DATA_WIDTH-1)) begin\n                                       ^\n%Error: Exiting due to 2 warning(s)\n'
module fifo_cond #(parameter DATA_WIDTH = 8, parameter ADDRESS_WIDTH = 3, parameter BUFFER_DEPTH = 8
)(
  input CLK,
  input ENB,
  input RST,
  input sRead,
  input sWrite,


  input [ADDRESS_WIDTH-1:0] umbEmpty,
  input [ADDRESS_WIDTH-1:0] umbFull,

  input [DATA_WIDTH-1:0] inputData,

  output reg almostEmpty,
  output reg almostFull,
  output reg outEmpty,
  output reg outFull,
  output reg errorEmpty,
  output reg errorFull,

  output reg [DATA_WIDTH-1:0] outputData
  );

  reg [ADDRESS_WIDTH-1:0] ptrWr;
  reg [ADDRESS_WIDTH-1:0] ptrRd;
  reg [ADDRESS_WIDTH-1:0] cantWr;

  reg [DATA_WIDTH-1:0] buffer [BUFFER_DEPTH-1:0];

  always @ ( posedge CLK ) begin
    if (RST) begin
      almostEmpty <= 1;
      almostFull <= 0;
      outEmpty <= 1;
      outFull <= 0;
      errorEmpty <= 0;
      errorFull <= 0;
      outputData <= 0;

      ptrWr <= 0;
      ptrRd <= 0;
      cantWr <= 0;
    end
    else begin
    if (ENB) begin
      if (sWrite) begin
        buffer[ptrWr] <= inputData;
        ptrWr <= ptrWr + 1;

        if (!sRead) begin
          if(outEmpty) begin
            outEmpty <= 0;
          end
          if (outFull) begin
            errorFull <= 1;
          end
          else begin
            if (cantWr == DATA_WIDTH-1) begin
              outFull <= 1;
            end
          end
          cantWr <= cantWr + 1;
        end
      end

      if (sRead) begin
        outputData <= buffer[ptrRd];
        ptrRd <= ptrRd + 1;

        if (!sWrite) begin
          if (outFull) begin
            outFull <= 0;
          end
          if (outEmpty) begin
            errorEmpty <= 1;
          end
          else begin
            if (cantWr == 1) begin
              outEmpty <= 1;
            end
          end
          cantWr <= cantWr - 1;
          end
        end
      end

      if ((1 < cantWr)&&(cantWr <= umbEmpty)) begin
        outEmpty <= 0;
        almostEmpty <= 1;
        almostFull <= 0;
      end

      if ((umbEmpty<=cantWr)&&(cantWr<=umbFull-1)) begin
        almostEmpty <= 0;
        almostFull <= 0;
      end

      if ((umbFull <= cantWr)&&(cantWr < DATA_WIDTH-1)) begin
        outFull <=0 ;
        almostEmpty <= 0;
        almostFull <= 1;
      end
    end
  end
endmodule
module fifo_cond #(parameter DATA_WIDTH = 8, parameter ADDRESS_WIDTH = 3, parameter BUFFER_DEPTH = 8
)(
  input CLK,
  input ENB,
  input RST,
  input sRead,
  input sWrite,


  input [ADDRESS_WIDTH-1:0] umbEmpty,
  input [ADDRESS_WIDTH-1:0] umbFull,

  input [DATA_WIDTH-1:0] inputData,

  output reg almostEmpty,
  output reg almostFull,
  output reg outEmpty,
  output reg outFull,
  output reg errorEmpty,
  output reg errorFull,

  output reg [DATA_WIDTH-1:0] outputData
  );


  reg [ADDRESS_WIDTH-1:0] ptrWr;
  reg [ADDRESS_WIDTH-1:0] ptrRd;
  reg [ADDRESS_WIDTH-1:0] cantWr;

  reg [DATA_WIDTH-1:0] buffer [BUFFER_DEPTH-1:0];

  always @ ( posedge CLK ) begin
    if (RST) begin
      almostEmpty <= 1;
      almostFull <= 0;
      outEmpty <= 1;
      outFull <= 0;
      errorEmpty <= 0;
      errorFull <= 0;
      outputData <= 0;

      ptrWr <= 0;
      ptrRd <= 0;
      cantWr <= 0;
    end
    else begin
    if (ENB) begin
      if (sWrite) begin
        buffer[ptrWr] <= inputData;
        ptrWr <= ptrWr + 1;

        if (!sRead) begin
          if(outEmpty) begin
            outEmpty <= 0;
          end
          if (outFull) begin
            errorFull <= 1;
          end
          else begin
            if (cantWr == DATA_WIDTH-1) begin
              outFull <= 1;
            end
          end
          cantWr <= cantWr + 1;
        end
      end

      if (sRead) begin
        outputData <= buffer[ptrRd];
        ptrRd <= ptrRd + 1;

        if (!sWrite) begin
          if (outFull) begin
            outFull <= 0;
          end
          if (outEmpty) begin
            errorEmpty <= 1;
          end
          else begin
            if (cantWr == 1) begin
              outEmpty <= 1;
            end
          end
          cantWr <= cantWr - 1;
          end
        end
      end

      if ((1 < cantWr)&&(cantWr <= umbEmpty)) begin
        outEmpty <= 0;
        almostEmpty <= 1;
        almostFull <= 0;
      end

      if ((umbEmpty<=cantWr)&&(cantWr<=umbFull-1)) begin
        almostEmpty <= 0;
        almostFull <= 0;
      end

      if ((umbFull <= cantWr)&&(cantWr < DATA_WIDTH-1)) begin
        outFull <=0 ;
        almostEmpty <= 0;
        almostFull <= 1;
      end
    end
  end
endmodule