data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/COMPARATOR/comparator.v
data/verilator_xmls/7e106b62-a0f6-4971-8086-c5a290cd23ff.xml
module comparator #(

    parameter DATA_WIDTH = 16
)
(

    input  wire                             CLK,
    input  wire                             RESET,
    input  wire [ DATA_WIDTH   -1 : 0]      DATA_IN_0,
    input  wire [ DATA_WIDTH   -1 : 0]      DATA_IN_1,
    output reg  [ DATA_WIDTH   -1 : 0]      COMP_OUT
);








always @ (posedge CLK)
begin: COMPARISON
    if (RESET)
        COMP_OUT <= 0;
    else
        COMP_OUT <= DATA_IN_0 < DATA_IN_1 ? DATA_IN_0 : DATA_IN_1;
end

endmodule
module comparator #(

    parameter DATA_WIDTH = 16
)
(

    input  wire                             CLK,
    input  wire                             RESET,
    input  wire [ DATA_WIDTH   -1 : 0]      DATA_IN_0,
    input  wire [ DATA_WIDTH   -1 : 0]      DATA_IN_1,
    output reg  [ DATA_WIDTH   -1 : 0]      COMP_OUT
);









always @ (posedge CLK)
begin: COMPARISON
    if (RESET)
        COMP_OUT <= 0;
    else
        COMP_OUT <= DATA_IN_0 < DATA_IN_1 ? DATA_IN_0 : DATA_IN_1;
end

endmodule