data/full_repos/permissive/175132042/rtl/tools/edge_detection.v
None: at end of input
1: b'%Error: data/full_repos/permissive/175132042/rtl/tools/edge_detection.v:11: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/rtl/tools,data/full_repos/permissive/175132042/timescale.v\n             data/full_repos/permissive/175132042/rtl/tools,data/full_repos/permissive/175132042/timescale.v.v\n             data/full_repos/permissive/175132042/rtl/tools,data/full_repos/permissive/175132042/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n'
module edge_detection (

   rising, failling,

   clk_i, rst_i, signal
   ) ;
   input wire clk_i;
   input wire rst_i;
   input wire signal;
   output wire rising;
   output wire failling;
   
   reg         hold;
   
   assign rising  = ((hold == 1) & (signal == 0));
   assign falling = ((hold == 0) & (signal == 1));






   always @(posedge clk_i)
     if (rst_i) begin
        hold <= 0;        
     end else begin
        hold <= signal;        
     end
   
endmodule
module edge_detection (

   rising, failling,

   clk_i, rst_i, signal
   ) ;

   input wire clk_i;
   input wire rst_i;
   input wire signal;
   output wire rising;
   output wire failling;
   
   reg         hold;
   
   assign rising  = ((hold == 1) & (signal == 0));
   assign falling = ((hold == 0) & (signal == 1));






   always @(posedge clk_i)
     if (rst_i) begin
        hold <= 0;        
     end else begin
        hold <= signal;        
     end
   
endmodule