data/full_repos/permissive/167424617/black_parrot_2019_03_28/harden_me.v
 line:30: before: "processing_system7_bfm_v2_0_5_axi_master"
1: b'%Warning-MULTITOP: data/full_repos/permissive/167424617/black_parrot_2019_03_28/harden_me.v:62: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'hard_mem_1rw_bit_mask_d64_w15_wrapper\'\nmodule hard_mem_1rw_bit_mask_d64_w15_wrapper #( parameter width_p = 15\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hard_mem_1rw_bit_mask_d64_w7_wrapper\'\nmodule hard_mem_1rw_bit_mask_d64_w7_wrapper #( parameter width_p = 7\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hard_mem_1rw_bit_mask_d64_w96_wrapper\'\nmodule hard_mem_1rw_bit_mask_d64_w96_wrapper #( parameter width_p = 96\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hard_mem_1rw_byte_mask_d512_w64_wrapper\'\nmodule hard_mem_1rw_byte_mask_d512_w64_wrapper #( parameter width_p = 64\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hard_mem_1rw_d256_w96_wrapper\'\nmodule hard_mem_1rw_d256_w96_wrapper #( parameter width_p = 96\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hard_mem_1rw_d512_w64_wrapper\'\nmodule hard_mem_1rw_d512_w64_wrapper #( parameter width_p = 64\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'hard_mem_1r1w_d32_w64_wrapper\'\nmodule hard_mem_1r1w_d32_w64_wrapper #( parameter width_p = 64\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module hard_mem_1rw_bit_mask_d64_w96_wrapper #( parameter width_p = 96
					                                    , parameter els_p   = 64
					                                    , parameter addr_width_lp = $clog2(els_p)
                                              )
  ( input                      clk_i
  , input                      reset_i
  , input [width_p-1:0]        data_i
  , input [addr_width_lp-1:0]  addr_i
  , input                      v_i
  , input [width_p-1:0]        w_mask_i
  , input                      w_i
  , output wire [width_p-1:0]  data_o
  );















  initial
    begin
      $display("## %m: to get the expect quality of results, this module should be replaced with the hardened equivalent.");
    end


  wire unused = reset_i;
  reg [addr_width_lp-1:0] addr_r;
  reg [width_p-1:0] mem [els_p-1:0];
  int i;

  always @(posedge clk_i)
    if (v_i & ~w_i)
      addr_r <= addr_i;
    else
      addr_r <= 'X;

  assign data_o = mem[addr_r];

  always @(posedge clk_i)
    if (v_i & w_i)
      for (i = 0; i < width_p; i=i+1)
        if (w_mask_i[i])
          mem[addr_i][i] <= data_i[i];



endmodule
module hard_mem_1rw_bit_mask_d64_w96_wrapper #( parameter width_p = 96
					                                    , parameter els_p   = 64
					                                    , parameter addr_width_lp = $clog2(els_p)
                                              )
  ( input                      clk_i
  , input                      reset_i
  , input [width_p-1:0]        data_i
  , input [addr_width_lp-1:0]  addr_i
  , input                      v_i
  , input [width_p-1:0]        w_mask_i
  , input                      w_i
  , output wire [width_p-1:0]  data_o
  );
















  initial
    begin
      $display("## %m: to get the expect quality of results, this module should be replaced with the hardened equivalent.");
    end


  wire unused = reset_i;
  reg [addr_width_lp-1:0] addr_r;
  reg [width_p-1:0] mem [els_p-1:0];
  int i;

  always @(posedge clk_i)
    if (v_i & ~w_i)
      addr_r <= addr_i;
    else
      addr_r <= 'X;

  assign data_o = mem[addr_r];

  always @(posedge clk_i)
    if (v_i & w_i)
      for (i = 0; i < width_p; i=i+1)
        if (w_mask_i[i])
          mem[addr_i][i] <= data_i[i];



endmodule