data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/sort_module.v
 line:516: before: "/"
1: b"%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/sort_module.v:77: Cannot find file containing module: 'sort_cell'\n  sort_cell #(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0,data/full_repos/permissive/13196823/sort_cell\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0,data/full_repos/permissive/13196823/sort_cell.v\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0,data/full_repos/permissive/13196823/sort_cell.sv\n             sort_cell\n             sort_cell.v\n             sort_cell.sv\n             obj_dir/sort_cell\n             obj_dir/sort_cell.v\n             obj_dir/sort_cell.sv\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/sort_module.v:124: Cannot find file containing module: 'sort_cell'\n  sort_cell #(\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/sort_module.v:102: Cannot find file containing module: 'sort_cell'\n  sort_cell #(\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module sort_module #(
	parameter K = 128,
	parameter SORT_WIDTH=32,
	parameter PRI_POS_START = 0,
	parameter PRI_POS_END = 32

)(
	input clk,
	input reset,
	
	input sort_en,
	input place_en,
	input wren,
	input order,
	input [SORT_WIDTH-1:0] data_in,
	output [SORT_WIDTH-1:0] dataout_sig,

	input [31:0] accum_key,



	
	input shift_out,
	output [31:0] threshold
);


wire [SORT_WIDTH-1:0] prev_data[K-1:0];

wire [K-1:0] i_am_lower;

wire [K-1:0] is_equal;

wire write_en;
assign write_en = wren & sort_en;







assign threshold = prev_data[K-1][31:0];

genvar i;
generate
	for(i=0;i<K;i=i+1) begin:sort
	if(i==0) begin
		sort_cell #(
        	.SORT_WIDTH(SORT_WIDTH),
			.PRI_POS_START(PRI_POS_START),
			.PRI_POS_END(PRI_POS_END)
		) scell (
        	.clk	(clk),
        	.reset	(reset),





		.prev_data	(32'h7F800000),
        	.data_out	(prev_data[0]),

        	.datain		(data_in),
		.place_en	(place_en),
        	.wren		(write_en),
		.order		(order),

        	.left_is_lower	(1'b0),
        	.i_am_lower	(i_am_lower[0])
	);
	end
	else if(i==K-1) begin
		sort_cell #(
        		.SORT_WIDTH(SORT_WIDTH),
			.PRI_POS_START(PRI_POS_START),
			.PRI_POS_END(PRI_POS_END)
		) scell (
        	.clk	(clk),
        	.reset	(reset),


        	.prev_data	(prev_data[i-1]),
        	.data_out	(prev_data[i]),

        	.datain		(data_in),
		.place_en	(place_en),
        	.wren		(write_en),
		.order		(order),

        	.left_is_lower	(i_am_lower[i-1]),
        	.i_am_lower	(i_am_lower[i])
	);
	end
	else begin
		sort_cell #(
        	.SORT_WIDTH(SORT_WIDTH),
			.PRI_POS_START(PRI_POS_START),
			.PRI_POS_END(PRI_POS_END)
		) scell (
        	.clk	(clk),
        	.reset	(reset),


        	.prev_data	(prev_data[i-1]),
        	.data_out	(prev_data[i]),

		.datain		(data_in),
		.place_en	(place_en),
        	.wren		(write_en),
		.order		(order),

        	.left_is_lower	(i_am_lower[i-1]),
        	.i_am_lower	(i_am_lower[i])
		  
	);
	end
	end
endgenerate

endmodule
module sort_module #(
	parameter K = 128,
	parameter SORT_WIDTH=32,
	parameter PRI_POS_START = 0,
	parameter PRI_POS_END = 32

)(
	input clk,
	input reset,
	
	input sort_en,
	input place_en,
	input wren,
	input order,
	input [SORT_WIDTH-1:0] data_in,
	output [SORT_WIDTH-1:0] dataout_sig,

	input [31:0] accum_key,



	
	input shift_out,
	output [31:0] threshold
);



wire [SORT_WIDTH-1:0] prev_data[K-1:0];

wire [K-1:0] i_am_lower;

wire [K-1:0] is_equal;

wire write_en;
assign write_en = wren & sort_en;







assign threshold = prev_data[K-1][31:0];

genvar i;
generate
	for(i=0;i<K;i=i+1) begin:sort
	if(i==0) begin
		sort_cell #(
        	.SORT_WIDTH(SORT_WIDTH),
			.PRI_POS_START(PRI_POS_START),
			.PRI_POS_END(PRI_POS_END)
		) scell (
        	.clk	(clk),
        	.reset	(reset),





		.prev_data	(32'h7F800000),
        	.data_out	(prev_data[0]),

        	.datain		(data_in),
		.place_en	(place_en),
        	.wren		(write_en),
		.order		(order),

        	.left_is_lower	(1'b0),
        	.i_am_lower	(i_am_lower[0])
	);
	end
	else if(i==K-1) begin
		sort_cell #(
        		.SORT_WIDTH(SORT_WIDTH),
			.PRI_POS_START(PRI_POS_START),
			.PRI_POS_END(PRI_POS_END)
		) scell (
        	.clk	(clk),
        	.reset	(reset),


        	.prev_data	(prev_data[i-1]),
        	.data_out	(prev_data[i]),

        	.datain		(data_in),
		.place_en	(place_en),
        	.wren		(write_en),
		.order		(order),

        	.left_is_lower	(i_am_lower[i-1]),
        	.i_am_lower	(i_am_lower[i])
	);
	end
	else begin
		sort_cell #(
        	.SORT_WIDTH(SORT_WIDTH),
			.PRI_POS_START(PRI_POS_START),
			.PRI_POS_END(PRI_POS_END)
		) scell (
        	.clk	(clk),
        	.reset	(reset),


        	.prev_data	(prev_data[i-1]),
        	.data_out	(prev_data[i]),

		.datain		(data_in),
		.place_en	(place_en),
        	.wren		(write_en),
		.order		(order),

        	.left_is_lower	(i_am_lower[i-1]),
        	.i_am_lower	(i_am_lower[i])
		  
	);
	end
	end
endgenerate

endmodule