data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/split_complex.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/f971c37b-69f3-4dbb-897d-76d8aba4c2dc.xml
module split_complex
  #(parameter WIDTH=16)
   (input [WIDTH*2-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
    output [WIDTH-1:0] oi_tdata, output oi_tlast, output oi_tvalid, input oi_tready,
    output [WIDTH-1:0] oq_tdata, output oq_tlast, output oq_tvalid, input oq_tready,
    output error);

   assign oi_tdata = i_tdata[WIDTH*2-1:WIDTH];
   assign oq_tdata = i_tdata[WIDTH-1:0];

   assign oi_tlast = i_tlast;
   assign oq_tlast = i_tlast;

   assign oi_tvalid = i_tvalid;
   assign oq_tvalid = i_tvalid;

   assign i_tready = oi_tready;

   assign  error = oi_tready ^ oq_tready;
   
endmodule
module split_complex
  #(parameter WIDTH=16)
   (input [WIDTH*2-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
    output [WIDTH-1:0] oi_tdata, output oi_tlast, output oi_tvalid, input oi_tready,
    output [WIDTH-1:0] oq_tdata, output oq_tlast, output oq_tvalid, input oq_tready,
    output error);


   assign oi_tdata = i_tdata[WIDTH*2-1:WIDTH];
   assign oq_tdata = i_tdata[WIDTH-1:0];

   assign oi_tlast = i_tlast;
   assign oq_tlast = i_tlast;

   assign oi_tvalid = i_tvalid;
   assign oq_tvalid = i_tvalid;

   assign i_tready = oi_tready;

   assign  error = oi_tready ^ oq_tready;
   
endmodule