data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #10 \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100110;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100111;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101010;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:110: Unsupported: Ignoring delay on this delayed statement.\n    always #1 i_clk = ~i_clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:112: Unsupported: Ignoring delay on this delayed statement.\n    always #2 i_PC = i_PC + 1;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:45: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                                           : ... In instance tb_seg_execute\n        i_PC    = {NB_ADDR{1\'b0}};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:71: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100000;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:72: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100010;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:73: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100100;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:74: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100101;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:75: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100110;   \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:76: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100111;   \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:77: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101010;   \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:82: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100000;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:83: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100001;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:84: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100010;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:85: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100011;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:87: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100100;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:88: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100101;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:89: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100110;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:90: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b100111;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:92: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101000;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:93: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101001;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:94: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101010;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:95: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101011;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:97: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101100;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:98: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101101;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:99: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101110;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:100: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb_seg_execute\n        #10 instruction[31:6] = $random; instruction[5:0] = 6\'b101111;\n                              ^\n%Error: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute.v:114: Cannot find file containing module: \'seg_execute\'\n    seg_execute \n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_execute\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_execute.v\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_execute.sv\n             seg_execute\n             seg_execute.v\n             seg_execute.sv\n             obj_dir/seg_execute\n             obj_dir/seg_execute.v\n             obj_dir/seg_execute.sv\n%Error: Exiting due to 1 error(s), 65 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_seg_execute();
    localparam    LEN             = 32;
    localparam    NB_ALUOP        = 2;
    localparam    NB_ALUCTL       = 4;
    localparam    NB_ADDR         = 5;
    localparam    NB_FUNC         = 6;
    localparam    NB_CTRL_WB      = 2;
    localparam    NB_CTRL_M       = 3;
    localparam    NB_CTRL_EX      = 4;


    reg                           i_clk;
    reg                           i_rst;
    reg  [LEN - 1 : 0]            i_PC;
    reg  [LEN - 1 : 0]            i_read_data_1;
    reg  [LEN - 1 : 0]            i_read_data_2;
    wire [LEN - 1 : 0]            i_addr_ext;
    wire [NB_ADDR - 1 : 0]        i_rt;
    wire [NB_ADDR - 1 : 0]        i_rd;

    reg  [NB_CTRL_WB - 1 : 0]     i_ctrl_wb_bus;
    reg  [NB_CTRL_M - 1 :  0]     i_ctrl_mem_bus;
    reg  [NB_CTRL_EX - 1 : 0]     i_ctrl_exc_bus;

    wire [LEN - 1 : 0]            o_PC_branch;
    wire [LEN - 1 : 0]            o_ALU_result;
    wire [LEN - 1 : 0]            o_write_data;
    wire [NB_ADDR - 1 : 0]        o_write_register;
    wire                          o_ALU_zero;

    wire [NB_CTRL_WB - 1 : 0]     o_ctrl_wb_bus;
    wire [NB_CTRL_M - 1 : 0]      o_ctrl_mem_bus;

    reg [LEN - 1 : 0] instruction;

    assign i_rt = instruction[20:16];
    assign i_rd = instruction[15:11];
    assign i_addr_ext = {{16{instruction[15]}}, instruction[15:0]};
    
    initial begin
        i_clk   = 1'b0;
        i_rst   = 1'b0;
        i_PC    = {NB_ADDR{1'b0}};
        i_read_data_1 = {LEN{1'b0}};
        i_read_data_2 = {LEN{1'b0}};
        instruction =  {LEN{1'b0}};
        i_ctrl_wb_bus = {NB_CTRL_WB{1'b0}};
        i_ctrl_mem_bus = {NB_CTRL_M{1'b0}};
        i_ctrl_exc_bus = {NB_CTRL_EX{1'b0}};

        #10 
        i_rst = 1'b1;
        instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;

        #10
        i_ctrl_exc_bus = 4'b0010;
        #10 instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;

        #10
        i_ctrl_exc_bus = 4'b0100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100000;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100010;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100101;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100110;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100111;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101010;
        #10
        i_ctrl_exc_bus = 4'b0110;
        #10
        i_ctrl_exc_bus = 4'b0100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100000;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100001;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100010;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100011;
        i_ctrl_exc_bus = 4'b0101;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100101;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100110;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100111;
        i_ctrl_exc_bus = 4'b1100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101000;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101001;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101010;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101011;
        i_ctrl_exc_bus = 4'b1101;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101101;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101110;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101111;
        #10 $finish;
    end

    always begin
    #5
        i_read_data_1 = $random;
        i_read_data_2 = $random;
    end

    always #1 i_clk = ~i_clk;

    always #2 i_PC = i_PC + 1;

    seg_execute 
    #(
        .LEN        (LEN        ),
        .NB_ALUOP   (NB_ALUOP   ),
        .NB_ALUCTL  (NB_ALUCTL  ),
        .NB_ADDR    (NB_ADDR    ),
        .NB_FUNC    (NB_FUNC    ),
        .NB_CTRL_WB (NB_CTRL_WB ),
        .NB_CTRL_M  (NB_CTRL_M  ),
        .NB_CTRL_EX (NB_CTRL_EX )
    )
    u_seg_execute(
    	.i_clk            (i_clk            ),
        .i_rst            (i_rst            ),
        .i_PC             (i_PC             ),
        .i_read_data_1    (i_read_data_1    ),
        .i_read_data_2    (i_read_data_2    ),
        .i_addr_ext       (i_addr_ext       ),
        .i_rt             (i_rt             ),
        .i_rd             (i_rd             ),
        .i_ctrl_wb_bus    (i_ctrl_wb_bus    ),
        .i_ctrl_mem_bus   (i_ctrl_mem_bus   ),
        .i_ctrl_exc_bus   (i_ctrl_exc_bus   ),
        .o_PC_branch      (o_PC_branch      ),
        .o_ALU_result     (o_ALU_result     ),
        .o_write_data     (o_write_data     ),
        .o_write_register (o_write_register ),
        .o_ALU_zero       (o_ALU_zero       ),
        .o_ctrl_wb_bus    (o_ctrl_wb_bus    ),
        .o_ctrl_mem_bus   (o_ctrl_mem_bus   )
    );

endmodule
module tb_seg_execute();

    localparam    LEN             = 32;
    localparam    NB_ALUOP        = 2;
    localparam    NB_ALUCTL       = 4;
    localparam    NB_ADDR         = 5;
    localparam    NB_FUNC         = 6;
    localparam    NB_CTRL_WB      = 2;
    localparam    NB_CTRL_M       = 3;
    localparam    NB_CTRL_EX      = 4;


    reg                           i_clk;
    reg                           i_rst;
    reg  [LEN - 1 : 0]            i_PC;
    reg  [LEN - 1 : 0]            i_read_data_1;
    reg  [LEN - 1 : 0]            i_read_data_2;
    wire [LEN - 1 : 0]            i_addr_ext;
    wire [NB_ADDR - 1 : 0]        i_rt;
    wire [NB_ADDR - 1 : 0]        i_rd;

    reg  [NB_CTRL_WB - 1 : 0]     i_ctrl_wb_bus;
    reg  [NB_CTRL_M - 1 :  0]     i_ctrl_mem_bus;
    reg  [NB_CTRL_EX - 1 : 0]     i_ctrl_exc_bus;

    wire [LEN - 1 : 0]            o_PC_branch;
    wire [LEN - 1 : 0]            o_ALU_result;
    wire [LEN - 1 : 0]            o_write_data;
    wire [NB_ADDR - 1 : 0]        o_write_register;
    wire                          o_ALU_zero;

    wire [NB_CTRL_WB - 1 : 0]     o_ctrl_wb_bus;
    wire [NB_CTRL_M - 1 : 0]      o_ctrl_mem_bus;

    reg [LEN - 1 : 0] instruction;

    assign i_rt = instruction[20:16];
    assign i_rd = instruction[15:11];
    assign i_addr_ext = {{16{instruction[15]}}, instruction[15:0]};
    
    initial begin
        i_clk   = 1'b0;
        i_rst   = 1'b0;
        i_PC    = {NB_ADDR{1'b0}};
        i_read_data_1 = {LEN{1'b0}};
        i_read_data_2 = {LEN{1'b0}};
        instruction =  {LEN{1'b0}};
        i_ctrl_wb_bus = {NB_CTRL_WB{1'b0}};
        i_ctrl_mem_bus = {NB_CTRL_M{1'b0}};
        i_ctrl_exc_bus = {NB_CTRL_EX{1'b0}};

        #10 
        i_rst = 1'b1;
        instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;

        #10
        i_ctrl_exc_bus = 4'b0010;
        #10 instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;
        #10 instruction = $random;

        #10
        i_ctrl_exc_bus = 4'b0100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100000;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100010;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100101;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100110;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100111;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101010;
        #10
        i_ctrl_exc_bus = 4'b0110;
        #10
        i_ctrl_exc_bus = 4'b0100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100000;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100001;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100010;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100011;
        i_ctrl_exc_bus = 4'b0101;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100101;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100110;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b100111;
        i_ctrl_exc_bus = 4'b1100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101000;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101001;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101010;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101011;
        i_ctrl_exc_bus = 4'b1101;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101100;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101101;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101110;
        #10 instruction[31:6] = $random; instruction[5:0] = 6'b101111;
        #10 $finish;
    end

    always begin
    #5
        i_read_data_1 = $random;
        i_read_data_2 = $random;
    end

    always #1 i_clk = ~i_clk;

    always #2 i_PC = i_PC + 1;

    seg_execute 
    #(
        .LEN        (LEN        ),
        .NB_ALUOP   (NB_ALUOP   ),
        .NB_ALUCTL  (NB_ALUCTL  ),
        .NB_ADDR    (NB_ADDR    ),
        .NB_FUNC    (NB_FUNC    ),
        .NB_CTRL_WB (NB_CTRL_WB ),
        .NB_CTRL_M  (NB_CTRL_M  ),
        .NB_CTRL_EX (NB_CTRL_EX )
    )
    u_seg_execute(
    	.i_clk            (i_clk            ),
        .i_rst            (i_rst            ),
        .i_PC             (i_PC             ),
        .i_read_data_1    (i_read_data_1    ),
        .i_read_data_2    (i_read_data_2    ),
        .i_addr_ext       (i_addr_ext       ),
        .i_rt             (i_rt             ),
        .i_rd             (i_rd             ),
        .i_ctrl_wb_bus    (i_ctrl_wb_bus    ),
        .i_ctrl_mem_bus   (i_ctrl_mem_bus   ),
        .i_ctrl_exc_bus   (i_ctrl_exc_bus   ),
        .o_PC_branch      (o_PC_branch      ),
        .o_ALU_result     (o_ALU_result     ),
        .o_write_data     (o_write_data     ),
        .o_write_register (o_write_register ),
        .o_ALU_zero       (o_ALU_zero       ),
        .o_ctrl_wb_bus    (o_ctrl_wb_bus    ),
        .o_ctrl_mem_bus   (o_ctrl_mem_bus   )
    );

endmodule