data/full_repos/permissive/143278/ivltests/ldelay3.v
 line:50: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:50: Unsupported: Ignoring delay on this delayed statement.\n #5.5 ok(1\'b x);\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:51: Unsupported: Ignoring delay on this delayed statement.\n #0.1 ok(1\'b 0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:53: Unsupported: Ignoring delay on this delayed statement.\n #5.5 ok(1\'b 0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:54: Unsupported: Ignoring delay on this delayed statement.\n #0.1 ok(1\'b 1);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:56: Unsupported: Ignoring delay on this delayed statement.\n #3 ok(1\'b 1);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:58: Unsupported: Ignoring delay on this delayed statement.\n #1 ok(1\'b 1);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:59: Unsupported: Ignoring delay on this delayed statement.\n #1 ok(1\'b 1);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:60: Unsupported: Ignoring delay on this delayed statement.\n #1 ok(1\'b 1);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:61: Unsupported: Ignoring delay on this delayed statement.\n #1 ok(1\'b 1);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:62: Unsupported: Ignoring delay on this delayed statement.\n #1 ok(1\'b 1);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:63: Unsupported: Ignoring delay on this delayed statement.\n #1 ok(1\'b 1);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ldelay3.v:64: Unsupported: Ignoring delay on this delayed statement.\n #1 ok(1\'b 1);\n ^\n%Error: data/full_repos/permissive/143278/ivltests/ldelay3.v:46: Found definition of \'ok\' as a TASK but expected a scope/variable\n ok.error = 0;\n ^~\n%Error: data/full_repos/permissive/143278/ivltests/ldelay3.v:65: Found definition of \'ok\' as a TASK but expected a scope/variable\n if (!ok.error)\n      ^~\n%Error: Exiting due to 2 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   wire q;
   reg  a, b;
   gate gg (q, a, b);

   task ok;
      input qq;
      reg error;
      begin
	 if (q !== qq)
	   begin
	      error = 1;
	      $display("%0d: FAILED: q=%b, expect %b", $time, q, qq);
	   end
      end
   endtask

   initial
     begin
	ok.error = 0;

	a <= 0;
	b <= 1;
	#5.5 ok(1'b x);
	#0.1 ok(1'b 0);
	a <= 1;
	#5.5 ok(1'b 0);
	#0.1 ok(1'b 1);
	a <= 0;
	#3 ok(1'b 1);
	a <= 1;
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	if (!ok.error)
	  $display("PASSED");
     end

endmodule
module test;


   wire q;
   reg  a, b;
   gate gg (q, a, b);

   task ok;
      input qq;
      reg error;
      begin
	 if (q !== qq)
	   begin
	      error = 1;
	      $display("%0d: FAILED: q=%b, expect %b", $time, q, qq);
	   end
      end
   endtask

   initial
     begin
	ok.error = 0;

	a <= 0;
	b <= 1;
	#5.5 ok(1'b x);
	#0.1 ok(1'b 0);
	a <= 1;
	#5.5 ok(1'b 0);
	#0.1 ok(1'b 1);
	a <= 0;
	#3 ok(1'b 1);
	a <= 1;
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	#1 ok(1'b 1);
	if (!ok.error)
	  $display("PASSED");
     end

endmodule