data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6.v
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data/verilator_xmls/8da96748-135e-4ee3-b6b2-309749f85b24.xml
module stage1_3is2 (
input [5:0] in1,
input [5:0] in2,
input [5:0] in3,
output [5:0] cout_stage1,
output [5:0] sum_stage1
);
FullAdder FA2 (in1[0],in2[0],in3[0],sum_stage1[0],cout_stage1[0]);
FullAdder FA3 (in1[1],in2[1],in3[1],sum_stage1[1],cout_stage1[1]);
FullAdder FA4 (in1[2],in2[2],in3[2],sum_stage1[2],cout_stage1[2]);
FullAdder FA5 (in1[3],in2[3],in3[3],sum_stage1[3],cout_stage1[3]);
FullAdder FA12 (in1[4],in2[4],in3[4],sum_stage1[4],cout_stage1[4]);
FullAdder FA13 (in1[5],in2[5],in3[5],sum_stage1[5],cout_stage1[5]);
endmodule
module stage1_3is2 (
input [5:0] in1,
input [5:0] in2,
input [5:0] in3,
output [5:0] cout_stage1,
output [5:0] sum_stage1
);

FullAdder FA2 (in1[0],in2[0],in3[0],sum_stage1[0],cout_stage1[0]);
FullAdder FA3 (in1[1],in2[1],in3[1],sum_stage1[1],cout_stage1[1]);
FullAdder FA4 (in1[2],in2[2],in3[2],sum_stage1[2],cout_stage1[2]);
FullAdder FA5 (in1[3],in2[3],in3[3],sum_stage1[3],cout_stage1[3]);
FullAdder FA12 (in1[4],in2[4],in3[4],sum_stage1[4],cout_stage1[4]);
FullAdder FA13 (in1[5],in2[5],in3[5],sum_stage1[5],cout_stage1[5]);
endmodule