data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc/clk_mux.v
None: at end of input
data/verilator_xmls/fcff9ea2-0c07-4cc6-a422-6bbc92b9fea6.xml
module clk_mux (
  input  in0_clk,
  input  in0_arst,
  input  in1_clk,
  input  in1_arst,
  input  sel,
  output out_clk);

  reg    sync0_p, sync0_n;
  reg    sync1_p, sync1_n;

  always @(posedge in0_clk or posedge in0_arst) begin
    if (in0_arst)
      sync0_p <= 1'b0;
    else
      sync0_p <= ~sel & ~sync1_n;
  end
  always @(negedge in0_clk or posedge in0_arst) begin
    if (in0_arst)
      sync0_n <= 1'b0;
    else
      sync0_n <= sync0_p;
  end

  always @(posedge in1_clk or posedge in1_arst) begin
    if (in1_arst)
      sync1_p <= 1'b0;
    else
      sync1_p <= sel & ~sync0_n;
  end
  always @(negedge in1_clk or posedge in1_arst) begin
    if (in1_arst)
      sync1_n <= 1'b0;
    else
      sync1_n <= sync1_p;
  end

  assign out_clk = (in0_clk & sync0_n) | (in1_clk & sync1_n);

endmodule
module clk_mux (
  input  in0_clk,
  input  in0_arst,
  input  in1_clk,
  input  in1_arst,
  input  sel,
  output out_clk);


  reg    sync0_p, sync0_n;
  reg    sync1_p, sync1_n;

  always @(posedge in0_clk or posedge in0_arst) begin
    if (in0_arst)
      sync0_p <= 1'b0;
    else
      sync0_p <= ~sel & ~sync1_n;
  end
  always @(negedge in0_clk or posedge in0_arst) begin
    if (in0_arst)
      sync0_n <= 1'b0;
    else
      sync0_n <= sync0_p;
  end

  always @(posedge in1_clk or posedge in1_arst) begin
    if (in1_arst)
      sync1_p <= 1'b0;
    else
      sync1_p <= sel & ~sync0_n;
  end
  always @(negedge in1_clk or posedge in1_arst) begin
    if (in1_arst)
      sync1_n <= 1'b0;
    else
      sync1_n <= sync1_p;
  end

  assign out_clk = (in0_clk & sync0_n) | (in1_clk & sync1_n);

endmodule