data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux4to1_module.v
 line:31: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux4to1_module.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #5 s=2\'b01;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux4to1_module.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #5 s=2\'b10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux4to1_module.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #5 s=2\'b11;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux4to1_module.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux4to1_module.v:40: Unsupported: Ignoring delay on this delayed statement.\nalways #5 begin\n       ^\n%Error: data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches/tb_mux4to1_module.v:20: Cannot find file containing module: \'mux4to1_module\'\nmux4to1_module utt\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches,data/full_repos/permissive/212763527/mux4to1_module\n             data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches,data/full_repos/permissive/212763527/mux4to1_module.v\n             data/full_repos/permissive/212763527/school_project/3_mux4_1/testbenches,data/full_repos/permissive/212763527/mux4to1_module.sv\n             mux4to1_module\n             mux4to1_module.v\n             mux4to1_module.sv\n             obj_dir/mux4to1_module\n             obj_dir/mux4to1_module.v\n             obj_dir/mux4to1_module.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mux4to1_module;

reg [2:0] w0;
reg [2:0] w1;
reg [2:0] w2;
reg [2:0] w3;
reg [1:0] s;
wire [2:0] f;

initial begin
    w0 = 3'b001;
    w1 = 3'b010;
    w2 = 3'b011;
    w3 = 3'b100;
    s = 2'b00;
end

mux4to1_module utt
(
    .s(s),
    .w0(w0),
    .w1(w1),
    .w2(w2),
    .w3(w3),
    .f(f)
);

initial begin
    repeat(2)begin
        #5 s=2'b01;
        #5 s=2'b10;
        #5 s=2'b11;
        #5;
    end
    $finish;
end

always #5 begin
    w0 = w0 + 1;
    w1 = w1 + 1;
    w2 = w2 + 1;
    w3 = w3 + 1;
end

endmodule
module tb_mux4to1_module;


reg [2:0] w0;
reg [2:0] w1;
reg [2:0] w2;
reg [2:0] w3;
reg [1:0] s;
wire [2:0] f;

initial begin
    w0 = 3'b001;
    w1 = 3'b010;
    w2 = 3'b011;
    w3 = 3'b100;
    s = 2'b00;
end

mux4to1_module utt
(
    .s(s),
    .w0(w0),
    .w1(w1),
    .w2(w2),
    .w3(w3),
    .f(f)
);

initial begin
    repeat(2)begin
        #5 s=2'b01;
        #5 s=2'b10;
        #5 s=2'b11;
        #5;
    end
    $finish;
end

always #5 begin
    w0 = w0 + 1;
    w1 = w1 + 1;
    w2 = w2 + 1;
    w3 = w3 + 1;
end

endmodule