data/full_repos/permissive/161029703/altera_de1_soc/ghrd_top.v
 line:399: before: ")"
1: b'%Error: data/full_repos/permissive/161029703/altera_de1_soc/ghrd_top.v:232: Cannot find file containing module: \'sys_pll\'\nsys_pll pll1(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161029703/altera_de1_soc,data/full_repos/permissive/161029703/sys_pll\n             data/full_repos/permissive/161029703/altera_de1_soc,data/full_repos/permissive/161029703/sys_pll.v\n             data/full_repos/permissive/161029703/altera_de1_soc,data/full_repos/permissive/161029703/sys_pll.sv\n             sys_pll\n             sys_pll.v\n             sys_pll.sv\n             obj_dir/sys_pll\n             obj_dir/sys_pll.v\n             obj_dir/sys_pll.sv\n%Error: data/full_repos/permissive/161029703/altera_de1_soc/ghrd_top.v:240: Cannot find file containing module: \'pll_hf\'\npll_hf pll2(\n^~~~~~\n%Error: data/full_repos/permissive/161029703/altera_de1_soc/ghrd_top.v:247: Cannot find file containing module: \'soc_system\'\nsoc_system u0 (      \n^~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/altera_de1_soc/ghrd_top.v:423: Cannot find file containing module: \'SEG7_LUT_6\'\nSEG7_LUT_6    seg_disp ( .oSEG0(HEX0),\n^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161029703/altera_de1_soc/ghrd_top.v:430: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'led_export\' generates 32 bits.\n                                                                                  : ... In instance ghrd_top\nassign LEDR = led_export;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module ghrd_top(

      

      inout              ADC_CS_N,
      output             ADC_DIN,
      input              ADC_DOUT,
      output             ADC_SCLK,


      input              AUD_ADCDAT,
      inout              AUD_ADCLRCK,
      inout              AUD_BCLK,
      output             AUD_DACDAT,
      inout              AUD_DACLRCK,
      output             AUD_XCK,


      input              CLOCK2_50,


      input              CLOCK3_50,


      input              CLOCK4_50,


      input              CLOCK_50,


      output      [12:0] DRAM_ADDR,
      output      [1:0]  DRAM_BA,
      output             DRAM_CAS_N,
      output             DRAM_CKE,
      output             DRAM_CLK,
      output             DRAM_CS_N,
      inout       [15:0] DRAM_DQ,
      output             DRAM_LDQM,
      output             DRAM_RAS_N,
      output             DRAM_UDQM,
      output             DRAM_WE_N,


      output             FAN_CTRL,


      output             FPGA_I2C_SCLK,
      inout              FPGA_I2C_SDAT,


      inout     [35:0]         GPIO_0,
      inout     [35:0]         GPIO_1,
 


      output      [6:0]  HEX0,


      output      [6:0]  HEX1,


      output      [6:0]  HEX2,


      output      [6:0]  HEX3,


      output      [6:0]  HEX4,


      output      [6:0]  HEX5,

`ifdef ENABLE_HPS

      inout              HPS_CONV_USB_N,
      output      [14:0] HPS_DDR3_ADDR,
      output      [2:0]  HPS_DDR3_BA,
      output             HPS_DDR3_CAS_N,
      output             HPS_DDR3_CKE,
      output             HPS_DDR3_CK_N,
      output             HPS_DDR3_CK_P,
      output             HPS_DDR3_CS_N,
      output      [3:0]  HPS_DDR3_DM,
      inout       [31:0] HPS_DDR3_DQ,
      inout       [3:0]  HPS_DDR3_DQS_N,
      inout       [3:0]  HPS_DDR3_DQS_P,
      output             HPS_DDR3_ODT,
      output             HPS_DDR3_RAS_N,
      output             HPS_DDR3_RESET_N,
      input              HPS_DDR3_RZQ,
      output             HPS_DDR3_WE_N,
      output             HPS_ENET_GTX_CLK,
      inout              HPS_ENET_INT_N,
      output             HPS_ENET_MDC,
      inout              HPS_ENET_MDIO,
      input              HPS_ENET_RX_CLK,
      input       [3:0]  HPS_ENET_RX_DATA,
      input              HPS_ENET_RX_DV,
      output      [3:0]  HPS_ENET_TX_DATA,
      output             HPS_ENET_TX_EN,
      inout       [3:0]  HPS_FLASH_DATA,
      output             HPS_FLASH_DCLK,
      output             HPS_FLASH_NCSO,
      inout              HPS_GSENSOR_INT,
      inout              HPS_I2C1_SCLK,
      inout              HPS_I2C1_SDAT,
      inout              HPS_I2C2_SCLK,
      inout              HPS_I2C2_SDAT,
      inout              HPS_I2C_CONTROL,
      inout              HPS_KEY,
      inout              HPS_LED,
      inout              HPS_LTC_GPIO,
      output             HPS_SD_CLK,
      inout              HPS_SD_CMD,
      inout       [3:0]  HPS_SD_DATA,
      output             HPS_SPIM_CLK,
      input              HPS_SPIM_MISO,
      output             HPS_SPIM_MOSI,
      inout              HPS_SPIM_SS,
      input              HPS_UART_RX,
      output             HPS_UART_TX,
      input              HPS_USB_CLKOUT,
      inout       [7:0]  HPS_USB_DATA,
      input              HPS_USB_DIR,
      input              HPS_USB_NXT,
      output             HPS_USB_STP,
`endif


      input              IRDA_RXD,
      output             IRDA_TXD,


      input       [3:0]  KEY,


      output      [9:0]  LEDR,


      inout              PS2_CLK,
      inout              PS2_CLK2,
      inout              PS2_DAT,
      inout              PS2_DAT2,


      input       [9:0]  SW,


      input              TD_CLK27,
      input      [7:0]  TD_DATA,
      input             TD_HS,
      output             TD_RESET_N,
      input             TD_VS,



      output      [7:0]  VGA_B,
      output             VGA_BLANK_N,
      output             VGA_CLK,
      output      [7:0]  VGA_G,
      output             VGA_HS,
      output      [7:0]  VGA_R,
      output             VGA_SYNC_N,
      output             VGA_VS
);





wire clk2x,clk,locked1, locked2 ,clk_uart_pll;
wire [31:0] led_export;
wire [23:0] dummy24;
wire [1:0] dummy2;
wire fpga_reset_n, fpga_other_reset_n;
wire uart_rxd, uart_txd;
wire clk2x_shift;
wire [7:0] hps2pio;


  wire  hps_fpga_reset_n;







  wire        fpga_clk_50;



  assign fpga_clk_50=CLOCK_50;



sys_pll pll1(
    .rst(1'b0),
    .refclk(CLOCK_50),
    .outclk_0(clk),

    .outclk_2(clk_uart_pll),

    .locked(locked1));
pll_hf pll2(
    .rst(1'b0),
    .refclk(CLOCK_50),
    .outclk_0(clk2x),
	 .outclk_1(clk2x_shift),
    .locked(locked2));
	 
soc_system u0 (      
		  .clk_clk                               (CLOCK_50),
		  .reset_reset_n                         (hps_fpga_reset_n & KEY[0]),

		  .memory_mem_a                          ( HPS_DDR3_ADDR),
        .memory_mem_ba                         ( HPS_DDR3_BA),
        .memory_mem_ck                         ( HPS_DDR3_CK_P),
        .memory_mem_ck_n                       ( HPS_DDR3_CK_N),
        .memory_mem_cke                        ( HPS_DDR3_CKE),
        .memory_mem_cs_n                       ( HPS_DDR3_CS_N),
        .memory_mem_ras_n                      ( HPS_DDR3_RAS_N),
        .memory_mem_cas_n                      ( HPS_DDR3_CAS_N),
        .memory_mem_we_n                       ( HPS_DDR3_WE_N),
        .memory_mem_reset_n                    ( HPS_DDR3_RESET_N),
        .memory_mem_dq                         ( HPS_DDR3_DQ),
        .memory_mem_dqs                        ( HPS_DDR3_DQS_P),
        .memory_mem_dqs_n                      ( HPS_DDR3_DQS_N),
        .memory_mem_odt                        ( HPS_DDR3_ODT),
        .memory_mem_dm                         ( HPS_DDR3_DM),
        .memory_oct_rzqin                      ( HPS_DDR3_RZQ),

	     .hps_0_hps_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK),
        .hps_0_hps_io_hps_io_emac1_inst_TXD0   ( HPS_ENET_TX_DATA[0] ),
        .hps_0_hps_io_hps_io_emac1_inst_TXD1   ( HPS_ENET_TX_DATA[1] ),
        .hps_0_hps_io_hps_io_emac1_inst_TXD2   ( HPS_ENET_TX_DATA[2] ),
        .hps_0_hps_io_hps_io_emac1_inst_TXD3   ( HPS_ENET_TX_DATA[3] ),
        .hps_0_hps_io_hps_io_emac1_inst_RXD0   ( HPS_ENET_RX_DATA[0] ),
        .hps_0_hps_io_hps_io_emac1_inst_MDIO   ( HPS_ENET_MDIO ),
        .hps_0_hps_io_hps_io_emac1_inst_MDC    ( HPS_ENET_MDC  ),
        .hps_0_hps_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV),
        .hps_0_hps_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN),
        .hps_0_hps_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK),
        .hps_0_hps_io_hps_io_emac1_inst_RXD1   ( HPS_ENET_RX_DATA[1] ),
        .hps_0_hps_io_hps_io_emac1_inst_RXD2   ( HPS_ENET_RX_DATA[2] ),
        .hps_0_hps_io_hps_io_emac1_inst_RXD3   ( HPS_ENET_RX_DATA[3] ),

		  .hps_0_hps_io_hps_io_qspi_inst_IO0     ( HPS_FLASH_DATA[0]    ),
        .hps_0_hps_io_hps_io_qspi_inst_IO1     ( HPS_FLASH_DATA[1]    ),
        .hps_0_hps_io_hps_io_qspi_inst_IO2     ( HPS_FLASH_DATA[2]    ),
        .hps_0_hps_io_hps_io_qspi_inst_IO3     ( HPS_FLASH_DATA[3]    ),
        .hps_0_hps_io_hps_io_qspi_inst_SS0     ( HPS_FLASH_NCSO    ),
        .hps_0_hps_io_hps_io_qspi_inst_CLK     ( HPS_FLASH_DCLK    ),

		  .hps_0_hps_io_hps_io_sdio_inst_CMD     ( HPS_SD_CMD    ),
        .hps_0_hps_io_hps_io_sdio_inst_D0      ( HPS_SD_DATA[0]     ),
        .hps_0_hps_io_hps_io_sdio_inst_D1      ( HPS_SD_DATA[1]     ),
        .hps_0_hps_io_hps_io_sdio_inst_CLK     ( HPS_SD_CLK   ),
        .hps_0_hps_io_hps_io_sdio_inst_D2      ( HPS_SD_DATA[2]     ),
        .hps_0_hps_io_hps_io_sdio_inst_D3      ( HPS_SD_DATA[3]     ),

		  .hps_0_hps_io_hps_io_usb1_inst_D0      ( HPS_USB_DATA[0]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D1      ( HPS_USB_DATA[1]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D2      ( HPS_USB_DATA[2]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D3      ( HPS_USB_DATA[3]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D4      ( HPS_USB_DATA[4]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D5      ( HPS_USB_DATA[5]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D6      ( HPS_USB_DATA[6]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D7      ( HPS_USB_DATA[7]    ),
        .hps_0_hps_io_hps_io_usb1_inst_CLK     ( HPS_USB_CLKOUT    ),
        .hps_0_hps_io_hps_io_usb1_inst_STP     ( HPS_USB_STP    ),
        .hps_0_hps_io_hps_io_usb1_inst_DIR     ( HPS_USB_DIR    ),
        .hps_0_hps_io_hps_io_usb1_inst_NXT     ( HPS_USB_NXT    ),

		  .hps_0_hps_io_hps_io_spim1_inst_CLK    ( HPS_SPIM_CLK  ),
        .hps_0_hps_io_hps_io_spim1_inst_MOSI   ( HPS_SPIM_MOSI ),
        .hps_0_hps_io_hps_io_spim1_inst_MISO   ( HPS_SPIM_MISO ),
        .hps_0_hps_io_hps_io_spim1_inst_SS0    ( HPS_SPIM_SS ),

		  .hps_0_hps_io_hps_io_uart0_inst_RX     ( HPS_UART_RX    ),
        .hps_0_hps_io_hps_io_uart0_inst_TX     ( HPS_UART_TX    ),

		  .hps_0_hps_io_hps_io_i2c0_inst_SDA     ( HPS_I2C1_SDAT    ),
        .hps_0_hps_io_hps_io_i2c0_inst_SCL     ( HPS_I2C1_SCLK    ),

		  .hps_0_hps_io_hps_io_i2c1_inst_SDA     ( HPS_I2C2_SDAT    ),
        .hps_0_hps_io_hps_io_i2c1_inst_SCL     ( HPS_I2C2_SCLK    ),

		  .hps_0_hps_io_hps_io_gpio_inst_GPIO09  ( HPS_CONV_USB_N),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO35  ( HPS_ENET_INT_N),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO40  ( HPS_LTC_GPIO),

        .hps_0_hps_io_hps_io_gpio_inst_GPIO48  ( HPS_I2C_CONTROL),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO53  ( HPS_LED),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO54  ( HPS_KEY),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO61  ( HPS_GSENSOR_INT),




	  .hps_0_h2f_reset_reset_n               ( hps_fpga_reset_n ),















 
 		.clk_cpu_clk(clk),
		.clk_other_clk(clk2x),
		.clk_uart_clk(clk_uart_pll),
		.debugger_dbg_txd(GPIO_0[0]),
		.debugger_dbg_rxd(GPIO_0[1]),

		.led_export(led_export),

		.usb_bus_tcm_address_out({GPIO_0[17],dummy2}),
		.usb_bus_tcm_read_n_out(GPIO_0[23]),
		.usb_bus_tcm_reset_n_out(GPIO_0[15]),
		.usb_bus_tcm_write_n_out(GPIO_0[21]),
		.usb_bus_tcm_data_out({dummy24,GPIO_0[10],GPIO_0[12],GPIO_0[14],GPIO_0[16],GPIO_0[18],GPIO_0[20],GPIO_0[22],GPIO_0[24]}),
		.usb_bus_tcm_chipselect_n_out(GPIO_0[25]),
		
 
 		.rst_cpu_reset_n(fpga_reset_n),
		.rst_other_reset_n(fpga_other_reset_n),
		.sdram_addr(DRAM_ADDR),
		.sdram_ba(DRAM_BA),
		.sdram_cas_n(DRAM_CAS_N),
		.sdram_cke(DRAM_CKE),
		.sdram_cs_n(DRAM_CS_N),
		.sdram_dq(DRAM_DQ),
		.sdram_dqm({DRAM_UDQM,DRAM_LDQM}),
		.sdram_ras_n(DRAM_RAS_N),
		.sdram_we_n(DRAM_WE_N),

		.sw_export({1'b0,GPIO_0[19],20'b0,SW}),
		.uart_rxd(uart_rxd),
		.uart_txd(uart_txd),
		
	  .hps_0_uart1_cts                       (1),
	  .hps_0_uart1_dsr                       (1),
	  .hps_0_uart1_dcd                       (1),
	  .hps_0_uart1_ri                        (0),
	  .hps_0_uart1_dtr                       (),
	  .hps_0_uart1_rts                       (),
	  .hps_0_uart1_out1_n                    (),
	  .hps_0_uart1_out2_n                    (),
	  .hps_0_uart1_rxd                       (uart_txd),
	  .hps_0_uart1_txd                       (uart_rxd),  
	  	                 
	  .hps2pio_export                        (hps2pio),
     .logger_rst_reset_n                    (~hps2pio[0]),  

    );
assign DRAM_CLK=clk2x_shift;
	 
	 


SEG7_LUT_6 			seg_disp	(	.oSEG0(HEX0),
							   .oSEG1(HEX1),
							   .oSEG2(HEX2),
							   .oSEG3(HEX3),
								.oSEG4(HEX4),
								.oSEG5(HEX5),
							   .iDIG(led_export) );
assign LEDR = led_export;
assign GPIO_0[13] = 1'b1;

assign fpga_reset_n = hps_fpga_reset_n & locked1 & KEY[0];
assign fpga_other_reset_n = hps_fpga_reset_n & locked2 & KEY[0];


endmodule
module ghrd_top(

      

      inout              ADC_CS_N,
      output             ADC_DIN,
      input              ADC_DOUT,
      output             ADC_SCLK,


      input              AUD_ADCDAT,
      inout              AUD_ADCLRCK,
      inout              AUD_BCLK,
      output             AUD_DACDAT,
      inout              AUD_DACLRCK,
      output             AUD_XCK,


      input              CLOCK2_50,


      input              CLOCK3_50,


      input              CLOCK4_50,


      input              CLOCK_50,


      output      [12:0] DRAM_ADDR,
      output      [1:0]  DRAM_BA,
      output             DRAM_CAS_N,
      output             DRAM_CKE,
      output             DRAM_CLK,
      output             DRAM_CS_N,
      inout       [15:0] DRAM_DQ,
      output             DRAM_LDQM,
      output             DRAM_RAS_N,
      output             DRAM_UDQM,
      output             DRAM_WE_N,


      output             FAN_CTRL,


      output             FPGA_I2C_SCLK,
      inout              FPGA_I2C_SDAT,


      inout     [35:0]         GPIO_0,
      inout     [35:0]         GPIO_1,
 


      output      [6:0]  HEX0,


      output      [6:0]  HEX1,


      output      [6:0]  HEX2,


      output      [6:0]  HEX3,


      output      [6:0]  HEX4,


      output      [6:0]  HEX5,

`ifdef ENABLE_HPS

      inout              HPS_CONV_USB_N,
      output      [14:0] HPS_DDR3_ADDR,
      output      [2:0]  HPS_DDR3_BA,
      output             HPS_DDR3_CAS_N,
      output             HPS_DDR3_CKE,
      output             HPS_DDR3_CK_N,
      output             HPS_DDR3_CK_P,
      output             HPS_DDR3_CS_N,
      output      [3:0]  HPS_DDR3_DM,
      inout       [31:0] HPS_DDR3_DQ,
      inout       [3:0]  HPS_DDR3_DQS_N,
      inout       [3:0]  HPS_DDR3_DQS_P,
      output             HPS_DDR3_ODT,
      output             HPS_DDR3_RAS_N,
      output             HPS_DDR3_RESET_N,
      input              HPS_DDR3_RZQ,
      output             HPS_DDR3_WE_N,
      output             HPS_ENET_GTX_CLK,
      inout              HPS_ENET_INT_N,
      output             HPS_ENET_MDC,
      inout              HPS_ENET_MDIO,
      input              HPS_ENET_RX_CLK,
      input       [3:0]  HPS_ENET_RX_DATA,
      input              HPS_ENET_RX_DV,
      output      [3:0]  HPS_ENET_TX_DATA,
      output             HPS_ENET_TX_EN,
      inout       [3:0]  HPS_FLASH_DATA,
      output             HPS_FLASH_DCLK,
      output             HPS_FLASH_NCSO,
      inout              HPS_GSENSOR_INT,
      inout              HPS_I2C1_SCLK,
      inout              HPS_I2C1_SDAT,
      inout              HPS_I2C2_SCLK,
      inout              HPS_I2C2_SDAT,
      inout              HPS_I2C_CONTROL,
      inout              HPS_KEY,
      inout              HPS_LED,
      inout              HPS_LTC_GPIO,
      output             HPS_SD_CLK,
      inout              HPS_SD_CMD,
      inout       [3:0]  HPS_SD_DATA,
      output             HPS_SPIM_CLK,
      input              HPS_SPIM_MISO,
      output             HPS_SPIM_MOSI,
      inout              HPS_SPIM_SS,
      input              HPS_UART_RX,
      output             HPS_UART_TX,
      input              HPS_USB_CLKOUT,
      inout       [7:0]  HPS_USB_DATA,
      input              HPS_USB_DIR,
      input              HPS_USB_NXT,
      output             HPS_USB_STP,
`endif


      input              IRDA_RXD,
      output             IRDA_TXD,


      input       [3:0]  KEY,


      output      [9:0]  LEDR,


      inout              PS2_CLK,
      inout              PS2_CLK2,
      inout              PS2_DAT,
      inout              PS2_DAT2,


      input       [9:0]  SW,


      input              TD_CLK27,
      input      [7:0]  TD_DATA,
      input             TD_HS,
      output             TD_RESET_N,
      input             TD_VS,



      output      [7:0]  VGA_B,
      output             VGA_BLANK_N,
      output             VGA_CLK,
      output      [7:0]  VGA_G,
      output             VGA_HS,
      output      [7:0]  VGA_R,
      output             VGA_SYNC_N,
      output             VGA_VS
);






wire clk2x,clk,locked1, locked2 ,clk_uart_pll;
wire [31:0] led_export;
wire [23:0] dummy24;
wire [1:0] dummy2;
wire fpga_reset_n, fpga_other_reset_n;
wire uart_rxd, uart_txd;
wire clk2x_shift;
wire [7:0] hps2pio;


  wire  hps_fpga_reset_n;







  wire        fpga_clk_50;



  assign fpga_clk_50=CLOCK_50;



sys_pll pll1(
    .rst(1'b0),
    .refclk(CLOCK_50),
    .outclk_0(clk),

    .outclk_2(clk_uart_pll),

    .locked(locked1));
pll_hf pll2(
    .rst(1'b0),
    .refclk(CLOCK_50),
    .outclk_0(clk2x),
	 .outclk_1(clk2x_shift),
    .locked(locked2));
	 
soc_system u0 (      
		  .clk_clk                               (CLOCK_50),
		  .reset_reset_n                         (hps_fpga_reset_n & KEY[0]),

		  .memory_mem_a                          ( HPS_DDR3_ADDR),
        .memory_mem_ba                         ( HPS_DDR3_BA),
        .memory_mem_ck                         ( HPS_DDR3_CK_P),
        .memory_mem_ck_n                       ( HPS_DDR3_CK_N),
        .memory_mem_cke                        ( HPS_DDR3_CKE),
        .memory_mem_cs_n                       ( HPS_DDR3_CS_N),
        .memory_mem_ras_n                      ( HPS_DDR3_RAS_N),
        .memory_mem_cas_n                      ( HPS_DDR3_CAS_N),
        .memory_mem_we_n                       ( HPS_DDR3_WE_N),
        .memory_mem_reset_n                    ( HPS_DDR3_RESET_N),
        .memory_mem_dq                         ( HPS_DDR3_DQ),
        .memory_mem_dqs                        ( HPS_DDR3_DQS_P),
        .memory_mem_dqs_n                      ( HPS_DDR3_DQS_N),
        .memory_mem_odt                        ( HPS_DDR3_ODT),
        .memory_mem_dm                         ( HPS_DDR3_DM),
        .memory_oct_rzqin                      ( HPS_DDR3_RZQ),

	     .hps_0_hps_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK),
        .hps_0_hps_io_hps_io_emac1_inst_TXD0   ( HPS_ENET_TX_DATA[0] ),
        .hps_0_hps_io_hps_io_emac1_inst_TXD1   ( HPS_ENET_TX_DATA[1] ),
        .hps_0_hps_io_hps_io_emac1_inst_TXD2   ( HPS_ENET_TX_DATA[2] ),
        .hps_0_hps_io_hps_io_emac1_inst_TXD3   ( HPS_ENET_TX_DATA[3] ),
        .hps_0_hps_io_hps_io_emac1_inst_RXD0   ( HPS_ENET_RX_DATA[0] ),
        .hps_0_hps_io_hps_io_emac1_inst_MDIO   ( HPS_ENET_MDIO ),
        .hps_0_hps_io_hps_io_emac1_inst_MDC    ( HPS_ENET_MDC  ),
        .hps_0_hps_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV),
        .hps_0_hps_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN),
        .hps_0_hps_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK),
        .hps_0_hps_io_hps_io_emac1_inst_RXD1   ( HPS_ENET_RX_DATA[1] ),
        .hps_0_hps_io_hps_io_emac1_inst_RXD2   ( HPS_ENET_RX_DATA[2] ),
        .hps_0_hps_io_hps_io_emac1_inst_RXD3   ( HPS_ENET_RX_DATA[3] ),

		  .hps_0_hps_io_hps_io_qspi_inst_IO0     ( HPS_FLASH_DATA[0]    ),
        .hps_0_hps_io_hps_io_qspi_inst_IO1     ( HPS_FLASH_DATA[1]    ),
        .hps_0_hps_io_hps_io_qspi_inst_IO2     ( HPS_FLASH_DATA[2]    ),
        .hps_0_hps_io_hps_io_qspi_inst_IO3     ( HPS_FLASH_DATA[3]    ),
        .hps_0_hps_io_hps_io_qspi_inst_SS0     ( HPS_FLASH_NCSO    ),
        .hps_0_hps_io_hps_io_qspi_inst_CLK     ( HPS_FLASH_DCLK    ),

		  .hps_0_hps_io_hps_io_sdio_inst_CMD     ( HPS_SD_CMD    ),
        .hps_0_hps_io_hps_io_sdio_inst_D0      ( HPS_SD_DATA[0]     ),
        .hps_0_hps_io_hps_io_sdio_inst_D1      ( HPS_SD_DATA[1]     ),
        .hps_0_hps_io_hps_io_sdio_inst_CLK     ( HPS_SD_CLK   ),
        .hps_0_hps_io_hps_io_sdio_inst_D2      ( HPS_SD_DATA[2]     ),
        .hps_0_hps_io_hps_io_sdio_inst_D3      ( HPS_SD_DATA[3]     ),

		  .hps_0_hps_io_hps_io_usb1_inst_D0      ( HPS_USB_DATA[0]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D1      ( HPS_USB_DATA[1]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D2      ( HPS_USB_DATA[2]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D3      ( HPS_USB_DATA[3]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D4      ( HPS_USB_DATA[4]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D5      ( HPS_USB_DATA[5]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D6      ( HPS_USB_DATA[6]    ),
        .hps_0_hps_io_hps_io_usb1_inst_D7      ( HPS_USB_DATA[7]    ),
        .hps_0_hps_io_hps_io_usb1_inst_CLK     ( HPS_USB_CLKOUT    ),
        .hps_0_hps_io_hps_io_usb1_inst_STP     ( HPS_USB_STP    ),
        .hps_0_hps_io_hps_io_usb1_inst_DIR     ( HPS_USB_DIR    ),
        .hps_0_hps_io_hps_io_usb1_inst_NXT     ( HPS_USB_NXT    ),

		  .hps_0_hps_io_hps_io_spim1_inst_CLK    ( HPS_SPIM_CLK  ),
        .hps_0_hps_io_hps_io_spim1_inst_MOSI   ( HPS_SPIM_MOSI ),
        .hps_0_hps_io_hps_io_spim1_inst_MISO   ( HPS_SPIM_MISO ),
        .hps_0_hps_io_hps_io_spim1_inst_SS0    ( HPS_SPIM_SS ),

		  .hps_0_hps_io_hps_io_uart0_inst_RX     ( HPS_UART_RX    ),
        .hps_0_hps_io_hps_io_uart0_inst_TX     ( HPS_UART_TX    ),

		  .hps_0_hps_io_hps_io_i2c0_inst_SDA     ( HPS_I2C1_SDAT    ),
        .hps_0_hps_io_hps_io_i2c0_inst_SCL     ( HPS_I2C1_SCLK    ),

		  .hps_0_hps_io_hps_io_i2c1_inst_SDA     ( HPS_I2C2_SDAT    ),
        .hps_0_hps_io_hps_io_i2c1_inst_SCL     ( HPS_I2C2_SCLK    ),

		  .hps_0_hps_io_hps_io_gpio_inst_GPIO09  ( HPS_CONV_USB_N),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO35  ( HPS_ENET_INT_N),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO40  ( HPS_LTC_GPIO),

        .hps_0_hps_io_hps_io_gpio_inst_GPIO48  ( HPS_I2C_CONTROL),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO53  ( HPS_LED),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO54  ( HPS_KEY),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO61  ( HPS_GSENSOR_INT),




	  .hps_0_h2f_reset_reset_n               ( hps_fpga_reset_n ),















 
 		.clk_cpu_clk(clk),
		.clk_other_clk(clk2x),
		.clk_uart_clk(clk_uart_pll),
		.debugger_dbg_txd(GPIO_0[0]),
		.debugger_dbg_rxd(GPIO_0[1]),

		.led_export(led_export),

		.usb_bus_tcm_address_out({GPIO_0[17],dummy2}),
		.usb_bus_tcm_read_n_out(GPIO_0[23]),
		.usb_bus_tcm_reset_n_out(GPIO_0[15]),
		.usb_bus_tcm_write_n_out(GPIO_0[21]),
		.usb_bus_tcm_data_out({dummy24,GPIO_0[10],GPIO_0[12],GPIO_0[14],GPIO_0[16],GPIO_0[18],GPIO_0[20],GPIO_0[22],GPIO_0[24]}),
		.usb_bus_tcm_chipselect_n_out(GPIO_0[25]),
		
 
 		.rst_cpu_reset_n(fpga_reset_n),
		.rst_other_reset_n(fpga_other_reset_n),
		.sdram_addr(DRAM_ADDR),
		.sdram_ba(DRAM_BA),
		.sdram_cas_n(DRAM_CAS_N),
		.sdram_cke(DRAM_CKE),
		.sdram_cs_n(DRAM_CS_N),
		.sdram_dq(DRAM_DQ),
		.sdram_dqm({DRAM_UDQM,DRAM_LDQM}),
		.sdram_ras_n(DRAM_RAS_N),
		.sdram_we_n(DRAM_WE_N),

		.sw_export({1'b0,GPIO_0[19],20'b0,SW}),
		.uart_rxd(uart_rxd),
		.uart_txd(uart_txd),
		
	  .hps_0_uart1_cts                       (1),
	  .hps_0_uart1_dsr                       (1),
	  .hps_0_uart1_dcd                       (1),
	  .hps_0_uart1_ri                        (0),
	  .hps_0_uart1_dtr                       (),
	  .hps_0_uart1_rts                       (),
	  .hps_0_uart1_out1_n                    (),
	  .hps_0_uart1_out2_n                    (),
	  .hps_0_uart1_rxd                       (uart_txd),
	  .hps_0_uart1_txd                       (uart_rxd),  
	  	                 
	  .hps2pio_export                        (hps2pio),
     .logger_rst_reset_n                    (~hps2pio[0]),  

    );
assign DRAM_CLK=clk2x_shift;
	 
	 


SEG7_LUT_6 			seg_disp	(	.oSEG0(HEX0),
							   .oSEG1(HEX1),
							   .oSEG2(HEX2),
							   .oSEG3(HEX3),
								.oSEG4(HEX4),
								.oSEG5(HEX5),
							   .iDIG(led_export) );
assign LEDR = led_export;
assign GPIO_0[13] = 1'b1;

assign fpga_reset_n = hps_fpga_reset_n & locked1 & KEY[0];
assign fpga_other_reset_n = hps_fpga_reset_n & locked2 & KEY[0];


endmodule