data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v
 line:178: before: "integer"
1: b'%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:38: Cannot find include file: ../command_defines.v\n`include "../command_defines.v"\n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src,data/full_repos/permissive/13196823/../command_defines.v\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src,data/full_repos/permissive/13196823/../command_defines.v.v\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src,data/full_repos/permissive/13196823/../command_defines.v.sv\n             ../command_defines.v\n             ../command_defines.v.v\n             ../command_defines.v.sv\n             obj_dir/../command_defines.v\n             obj_dir/../command_defines.v.v\n             obj_dir/../command_defines.v.sv\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:362: Define or directive not defined: \'`START_LOAD\'\n       if(in_fifo_data[47:40]==`START_LOAD) begin\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:362: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n       if(in_fifo_data[47:40]==`START_LOAD) begin\n                                          ^\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:366: Define or directive not defined: \'`LOAD_DATA\'\n       else if(in_fifo_data[47:40]==`LOAD_DATA) begin\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:366: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n       else if(in_fifo_data[47:40]==`LOAD_DATA) begin\n                                              ^\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:369: Define or directive not defined: \'`END_LOAD\'\n       else if(in_fifo_data[47:40]==`END_LOAD) begin\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:374: syntax error, unexpected else\n       else if(in_fifo_data[47:40]==`FPGA_TO_WORKER_PUT_REQUEST) begin  \n       ^~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:374: Define or directive not defined: \'`FPGA_TO_WORKER_PUT_REQUEST\'\n       else if(in_fifo_data[47:40]==`FPGA_TO_WORKER_PUT_REQUEST) begin  \n                                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:377: Define or directive not defined: \'`WORKER_TO_FPGA_PUT_REQUEST\'\n       else if(in_fifo_data[47:40]==`WORKER_TO_FPGA_PUT_REQUEST) begin  \n                                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:380: Define or directive not defined: \'`START_UPDATE\'\n       else if(in_fifo_data[47:40]==`START_UPDATE) begin\n                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:384: Define or directive not defined: \'`END_UPDATE\'\n       else if(in_fifo_data[47:40]==`END_UPDATE) begin\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:388: Define or directive not defined: \'`START_CHECK_TERMINATE\'\n       else if(in_fifo_data[47:40]==`START_CHECK_TERMINATE) begin\n                                    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:392: Define or directive not defined: \'`START_FLUSH_DATA\'\n       else if(in_fifo_data[47:40]==`START_FLUSH_DATA) begin\n                                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:424: syntax error, unexpected \'=\', expecting IDENTIFIER\n   state_next = WAIT_PREPROCESS_RDY;\n              ^\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:428: syntax error, unexpected \'=\', expecting IDENTIFIER\n   state_next = ACCUM_KEY_VALUE;\n              ^\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/op_lut_process_sm.v:437: syntax error, unexpected \'=\', expecting IDENTIFIER\n                 state_next = WAIT_PREPROCESS_RDY;\n                            ^\n%Error: Cannot continue\n'
function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction
function integer log2;

      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction