data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_aes_256.v
 line:67: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_aes_256.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #(10*(1000.00/200));\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_aes_256.v:66: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_aes_256.v:120: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_aes_256.v:133: syntax error, unexpected $display\n     $display("Error @ %d", j+1);\n     ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_aes_256.v:135: syntax error, unexpected $stop\n                    $stop;\n                    ^~~~~\n%Error: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_aes_256.v:145: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("aes_256_wrapper.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_aes_256.v:146: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, uut);\n ^~~~~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_aes_256;


	reg clk;
	reg [127:0] state;
	reg [255:0] key;


	wire [127:0] out;

	reg [127:0] plaintext[0:499];
	reg [255:0] keytext[0:499];
	reg [127:0] ciphertext[0:499];

	integer i, j;

	initial
	begin
		$readmemh("plaintext", plaintext);
		$readmemh("key", keytext);
		$readmemh("cipher", ciphertext);
	end


	top uut (
		.CLK(clk), 
		.STATE(state), 
		.KEY(key), 
		.OUT(out)
	);

	initial begin
		clk = 0;
		state = 0;
		key = 0;

		#(10*`CLK_P);

	for (i = 0; i < 500; i = i + 1)
	begin
		@(posedge clk)
		begin
			state = plaintext[i];
			key = keytext[i];
		end
	end

	end

	initial
	begin
		#(10*`CLK_P)
		#((`LATENCY+1)*`CLK_P)
		for (j = 0; j < 500; j = j + 1)
		begin
			@(posedge clk)
			begin
				$display("out=%x", out);
				if (out !== ciphertext[j])
				begin
					$display("Error @ %d", j+1);
                    $error;
                    $stop;
				end
			end
		end
		$display("All good!");
		$finish;
	end

    initial
    begin
	$dumpfile("aes_256_wrapper.vcd");
	$dumpvars(0, uut);
    end

    always #(`CLK_P/2) clk = ~clk;
endmodule
module test_aes_256;



	reg clk;
	reg [127:0] state;
	reg [255:0] key;


	wire [127:0] out;

	reg [127:0] plaintext[0:499];
	reg [255:0] keytext[0:499];
	reg [127:0] ciphertext[0:499];

	integer i, j;

	initial
	begin
		$readmemh("plaintext", plaintext);
		$readmemh("key", keytext);
		$readmemh("cipher", ciphertext);
	end


	top uut (
		.CLK(clk), 
		.STATE(state), 
		.KEY(key), 
		.OUT(out)
	);

	initial begin
		clk = 0;
		state = 0;
		key = 0;

		#(10*`CLK_P);

	for (i = 0; i < 500; i = i + 1)
	begin
		@(posedge clk)
		begin
			state = plaintext[i];
			key = keytext[i];
		end
	end

	end

	initial
	begin
		#(10*`CLK_P)
		#((`LATENCY+1)*`CLK_P)
		for (j = 0; j < 500; j = j + 1)
		begin
			@(posedge clk)
			begin
				$display("out=%x", out);
				if (out !== ciphertext[j])
				begin
					$display("Error @ %d", j+1);
                    $error;
                    $stop;
				end
			end
		end
		$display("All good!");
		$finish;
	end

    initial
    begin
	$dumpfile("aes_256_wrapper.vcd");
	$dumpvars(0, uut);
    end

    always #(`CLK_P/2) clk = ~clk;
endmodule