data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_サンプル回路/FPGA-CPU/FPGA_counter/time_display.v
1: b"%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/time_display.v:25: Cannot find file containing module: 'display_module'\ndisplay_module dm1(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter,data/full_repos/permissive/183580645/display_module\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter,data/full_repos/permissive/183580645/display_module.v\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter,data/full_repos/permissive/183580645/display_module.sv\n             display_module\n             display_module.v\n             display_module.sv\n             obj_dir/display_module\n             obj_dir/display_module.v\n             obj_dir/display_module.sv\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/time_display.v:32: Cannot find file containing module: 'display_module'\ndisplay_module dm2(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/time_display.v:39: Cannot find file containing module: 'display_module'\ndisplay_module dm3(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/time_display.v:46: Cannot find file containing module: 'display_module'\ndisplay_module dm4(\n^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module time_display(

CLK,RSTN,
SEG_A_VAL,SEG_B_VAL,SEG_C_VAL,SEG_D_VAL,

SEG_A,SEG_B,SEG_C,SEG_D
);


input  CLK , RSTN;
input  [3:0] SEG_A_VAL,SEG_B_VAL,SEG_C_VAL,SEG_D_VAL;

output [7:0] SEG_A,SEG_B,SEG_C,SEG_D;

wire    [7:0] SEG_A,SEG_B,SEG_C,SEG_D;

display_module dm1(
				.CLK(CLK),
				.RSTN(RSTN),
				.SEG_VAL(SEG_A_VAL),
				.SEG(SEG_A)
				);
				
display_module dm2(
				.CLK(CLK),
				.RSTN(RSTN),
				.SEG_VAL(SEG_B_VAL),
				.SEG(SEG_B)
				);

display_module dm3(
				.CLK(CLK),
				.RSTN(RSTN),
				.SEG_VAL(SEG_C_VAL),
				.SEG(SEG_C)
				);

display_module dm4(
				.CLK(CLK),
				.RSTN(RSTN),
				.SEG_VAL(SEG_D_VAL),
				.SEG(SEG_D)
				);

endmodule
module time_display(

CLK,RSTN,
SEG_A_VAL,SEG_B_VAL,SEG_C_VAL,SEG_D_VAL,

SEG_A,SEG_B,SEG_C,SEG_D
);



input  CLK , RSTN;
input  [3:0] SEG_A_VAL,SEG_B_VAL,SEG_C_VAL,SEG_D_VAL;

output [7:0] SEG_A,SEG_B,SEG_C,SEG_D;

wire    [7:0] SEG_A,SEG_B,SEG_C,SEG_D;

display_module dm1(
				.CLK(CLK),
				.RSTN(RSTN),
				.SEG_VAL(SEG_A_VAL),
				.SEG(SEG_A)
				);
				
display_module dm2(
				.CLK(CLK),
				.RSTN(RSTN),
				.SEG_VAL(SEG_B_VAL),
				.SEG(SEG_B)
				);

display_module dm3(
				.CLK(CLK),
				.RSTN(RSTN),
				.SEG_VAL(SEG_C_VAL),
				.SEG(SEG_C)
				);

display_module dm4(
				.CLK(CLK),
				.RSTN(RSTN),
				.SEG_VAL(SEG_D_VAL),
				.SEG(SEG_D)
				);

endmodule