data/full_repos/permissive/200478172/source/MUXHL.v
data/verilator_xmls/f79d1816-d376-4910-835e-de47310d5852.xml
module MUXHL(
    input [31:0]a,
    input [31:0]b,
    input [31:0]c,
    input [31:0]d,
    input [31:0]e,
    input [2:0]ctr,
   
    output [31:0] z
    );
    reg [31:0] temp;
    always@(*)begin
        case(ctr)
            3'b000:temp<=a;
            3'b001:temp<=b;
            3'b010:temp<=c;
            3'b011:temp<=d;
            3'b100:temp<=e;

        endcase
    end
    assign z=temp;
endmodule
module MUXHL(
    input [31:0]a,
    input [31:0]b,
    input [31:0]c,
    input [31:0]d,
    input [31:0]e,
    input [2:0]ctr,
   
    output [31:0] z
    );

    reg [31:0] temp;
    always@(*)begin
        case(ctr)
            3'b000:temp<=a;
            3'b001:temp<=b;
            3'b010:temp<=c;
            3'b011:temp<=d;
            3'b100:temp<=e;

        endcase
    end
    assign z=temp;
endmodule