data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog/hazard_detection_unit.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/1108bd0b-330f-4a30-941d-74e7e91e9f49.xml
module hazard_detection_unit
#(
    parameter NB_ADDR   = 5
)
(
    input                   i_MemRead,
    input [NB_ADDR - 1 : 0] i_rs_id,
    input [NB_ADDR - 1 : 0] i_rt_id,
    input [NB_ADDR - 1 : 0] i_rt_ex,
    output                  o_stall_flag    
);

    assign o_stall_flag = ((i_MemRead == 1) & ((i_rs_id == i_rt_ex) | (i_rt_id == i_rt_ex))) ? 1'b1 : 1'b0; 

endmodule
module hazard_detection_unit
#(
    parameter NB_ADDR   = 5
)
(
    input                   i_MemRead,
    input [NB_ADDR - 1 : 0] i_rs_id,
    input [NB_ADDR - 1 : 0] i_rt_id,
    input [NB_ADDR - 1 : 0] i_rt_ex,
    output                  o_stall_flag    
);


    assign o_stall_flag = ((i_MemRead == 1) & ((i_rs_id == i_rt_ex) | (i_rt_id == i_rt_ex))) ? 1'b1 : 1'b0; 

endmodule