data/full_repos/permissive/167274925/PCAdder.v
data/verilator_xmls/d08dc121-ba85-480c-a85e-3d7ac15fc0c0.xml
module PCAdder(PCResult, PCAddResult);

    input [31:0] PCResult;

    output [31:0] PCAddResult;
    reg [31:0]  PCAddResult;
     
     always@(PCResult)begin 
      PCAddResult<=PCResult+32'd4;
     end 

endmodule
module PCAdder(PCResult, PCAddResult);


    input [31:0] PCResult;

    output [31:0] PCAddResult;
    reg [31:0]  PCAddResult;
     
     always@(PCResult)begin 
      PCAddResult<=PCResult+32'd4;
     end 

endmodule