data/full_repos/permissive/140572461/hdl/ram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/140572461/hdl/ram.v:22: Bit extraction of array[1023:0] requires 10 bit index, not 16 bits.\n                                                                 : ... In instance ram\n            memory_array[addr] <= data_in;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/140572461/hdl/ram.v:24: Bit extraction of array[1023:0] requires 10 bit index, not 16 bits.\n                                                                 : ... In instance ram\n        data_out <= memory_array[addr];\n                                ^\n%Error: Exiting due to 2 warning(s)\n'
module ram #(parameter
    ADDR_WIDTH = 16,
    DATA_WIDTH = 8,
    DEPTH = 1024)
(
    input wire clk,
    input wire cs,
    input wire [ADDR_WIDTH-1:0] addr, 
    input wire we,
    input wire [DATA_WIDTH-1:0] data_in,
    output reg [DATA_WIDTH-1:0] data_out 
);

reg [DATA_WIDTH-1:0] memory_array [0:DEPTH-1]; 

always @(posedge clk) begin
    if (cs) begin
        if (we) begin
            memory_array[addr] <= data_in;
        end
        data_out <= memory_array[addr];
    end
end

endmodule
module ram #(parameter
    ADDR_WIDTH = 16,
    DATA_WIDTH = 8,
    DEPTH = 1024)
(
    input wire clk,
    input wire cs,
    input wire [ADDR_WIDTH-1:0] addr, 
    input wire we,
    input wire [DATA_WIDTH-1:0] data_in,
    output reg [DATA_WIDTH-1:0] data_out 
);


reg [DATA_WIDTH-1:0] memory_array [0:DEPTH-1]; 

always @(posedge clk) begin
    if (cs) begin
        if (we) begin
            memory_array[addr] <= data_in;
        end
        data_out <= memory_array[addr];
    end
end

endmodule