data/full_repos/permissive/101423580/v/PIO.v
data/verilator_xmls/ff8cd673-fcb4-42a9-a343-49581b5b97d8.xml
module PIO(	input wire clk,
				input wire rst,
				input wire EN,
				input wire[31:0] PData_in,
				output wire[7:0] LED,
				output reg[31:0] GPIOf0
				);


	assign LED = ~GPIOf0[7:0];
	
	always @ (negedge clk or posedge rst) begin
		if(rst) GPIOf0 <= 32'h00000000;
		else 	if(EN)		GPIOf0 <= PData_in;
				else 			GPIOf0 <= GPIOf0;
	end

endmodule
module PIO(	input wire clk,
				input wire rst,
				input wire EN,
				input wire[31:0] PData_in,
				output wire[7:0] LED,
				output reg[31:0] GPIOf0
				);



	assign LED = ~GPIOf0[7:0];
	
	always @ (negedge clk or posedge rst) begin
		if(rst) GPIOf0 <= 32'h00000000;
		else 	if(EN)		GPIOf0 <= PData_in;
				else 			GPIOf0 <= GPIOf0;
	end

endmodule