data/full_repos/permissive/216615048/src/simulation/inst_mem_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/inst_mem_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/inst_mem_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/inst_mem_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/inst_mem_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Error: data/full_repos/permissive/216615048/src/simulation/inst_mem_tb.v:8: Cannot find file containing module: \'InstMem\'\nInstMem IM(addr,inst);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/InstMem\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/InstMem.v\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/InstMem.sv\n             InstMem\n             InstMem.v\n             InstMem.sv\n             obj_dir/InstMem\n             obj_dir/InstMem.v\n             obj_dir/InstMem.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module inst_mem_tb();
reg [5:0]addr;
wire [31:0]inst;

InstMem IM(addr,inst);

initial begin

addr=1;
#100
addr=5;
#100
addr=7;
#100
addr=10;
#100
addr=12;



end
endmodule
module inst_mem_tb();

reg [5:0]addr;
wire [31:0]inst;

InstMem IM(addr,inst);

initial begin

addr=1;
#100
addr=5;
#100
addr=7;
#100
addr=10;
#100
addr=12;



end
endmodule