data/full_repos/permissive/188868339/src/ALU/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/188868339/src/ALU/ALU.v:37: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 8 bits.\n                                                                     : ... In instance ALU\n assign RESULT_AND = A & B;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/188868339/src/ALU/ALU.v:41: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s OR generates 8 bits.\n                                                                     : ... In instance ALU\n assign RESULT_OR = A | B;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/188868339/src/ALU/ALU.v:45: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s XOR generates 8 bits.\n                                                                     : ... In instance ALU\n assign RESULT_EOR = A ^ B;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/188868339/src/ALU/ALU.v:49: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 8 bits.\n                                                                     : ... In instance ALU\n assign RESULT_SR = A >> B;\n                  ^\n%Error: data/full_repos/permissive/188868339/src/ALU/ALU.v:54: Cannot find file containing module: \'CLA8\'\n CLA8 U0_CLA8(A, B, Cin, RESULT_BIN_SUM, SUM_Cout, SUM_C6);\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/188868339/src/ALU,data/full_repos/permissive/188868339/CLA8\n             data/full_repos/permissive/188868339/src/ALU,data/full_repos/permissive/188868339/CLA8.v\n             data/full_repos/permissive/188868339/src/ALU,data/full_repos/permissive/188868339/CLA8.sv\n             CLA8\n             CLA8.v\n             CLA8.sv\n             obj_dir/CLA8\n             obj_dir/CLA8.v\n             obj_dir/CLA8.sv\n%Error: data/full_repos/permissive/188868339/src/ALU/ALU.v:59: Cannot find file containing module: \'BCD_CLA\'\n BCD_CLA U1_BCD_CLA(A, B, Cin, RESULT_BCD_SUM, BCD_Cout, BCD_HCout);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/188868339/src/ALU/ALU.v:70: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESULT_AND\' generates 1 bits.\n                                                                     : ... In instance ALU\n    RESULT <= RESULT_AND;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/188868339/src/ALU/ALU.v:72: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESULT_OR\' generates 1 bits.\n                                                                     : ... In instance ALU\n    RESULT <= RESULT_OR;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/188868339/src/ALU/ALU.v:74: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESULT_EOR\' generates 1 bits.\n                                                                     : ... In instance ALU\n    RESULT <= RESULT_EOR;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/188868339/src/ALU/ALU.v:76: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESULT_SR\' generates 1 bits.\n                                                                     : ... In instance ALU\n    RESULT <= RESULT_SR;\n           ^~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module ALU(
    input [7:0]A,
    input [7:0]B,
    input SUMS,
    input ANDS,
    input ORS,
    input EORS,
    input SRS,
    input DEC_En,
    input Cin,
    output reg [7:0]RESULT,
    output OF,
    output Cout,
    output HCout
);
	

	wire [5:0]Control = {DEC_En, SUMS, ANDS, ORS, EORS, SRS};
	
	

	wire RESULT_AND;
	assign RESULT_AND = A & B;
	

	wire RESULT_OR;
	assign RESULT_OR = A | B;
	

	wire RESULT_EOR;
	assign RESULT_EOR = A ^ B;
	

	wire RESULT_SR;
	assign RESULT_SR = A >> B;
	

	wire [7:0]RESULT_BIN_SUM;
	wire SUM_Cout, SUM_C6;
	CLA8 U0_CLA8(A, B, Cin, RESULT_BIN_SUM, SUM_Cout, SUM_C6);
	

	wire [7:0]RESULT_BCD_SUM;
	wire BCD_Cout, BCD_HCout;
	BCD_CLA U1_BCD_CLA(A, B, Cin, RESULT_BCD_SUM, BCD_Cout, BCD_HCout);
	


	

	

always @(Control) begin
    case (Control)
        6'b000001: 
				RESULT <= RESULT_AND;
        6'b000010:
				RESULT <= RESULT_OR;
        6'b000100:
				RESULT <= RESULT_EOR;
        6'b001000:
				RESULT <= RESULT_SR;
        6'b010000:
            RESULT <= RESULT_BIN_SUM;
        6'b110000:
            RESULT <= RESULT_BCD_SUM;
        default:
				RESULT <= 8'b00000000;
    endcase
end
endmodule
module ALU(
    input [7:0]A,
    input [7:0]B,
    input SUMS,
    input ANDS,
    input ORS,
    input EORS,
    input SRS,
    input DEC_En,
    input Cin,
    output reg [7:0]RESULT,
    output OF,
    output Cout,
    output HCout
);

	

	wire [5:0]Control = {DEC_En, SUMS, ANDS, ORS, EORS, SRS};
	
	

	wire RESULT_AND;
	assign RESULT_AND = A & B;
	

	wire RESULT_OR;
	assign RESULT_OR = A | B;
	

	wire RESULT_EOR;
	assign RESULT_EOR = A ^ B;
	

	wire RESULT_SR;
	assign RESULT_SR = A >> B;
	

	wire [7:0]RESULT_BIN_SUM;
	wire SUM_Cout, SUM_C6;
	CLA8 U0_CLA8(A, B, Cin, RESULT_BIN_SUM, SUM_Cout, SUM_C6);
	

	wire [7:0]RESULT_BCD_SUM;
	wire BCD_Cout, BCD_HCout;
	BCD_CLA U1_BCD_CLA(A, B, Cin, RESULT_BCD_SUM, BCD_Cout, BCD_HCout);
	


	

	

always @(Control) begin
    case (Control)
        6'b000001: 
				RESULT <= RESULT_AND;
        6'b000010:
				RESULT <= RESULT_OR;
        6'b000100:
				RESULT <= RESULT_EOR;
        6'b001000:
				RESULT <= RESULT_SR;
        6'b010000:
            RESULT <= RESULT_BIN_SUM;
        6'b110000:
            RESULT <= RESULT_BCD_SUM;
        default:
				RESULT <= 8'b00000000;
    endcase
end
endmodule