data/full_repos/permissive/174546493/ControlUnitTopModule.v
1: b'%Warning-WIDTH: data/full_repos/permissive/174546493/ControlUnitTopModule.v:104: Value too large for 5 bit number: 32\n       5\'d32,  \n       ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/174546493/ControlUnitTopModule.v:56: Cannot find file containing module: \'dispatch1\'\n      dispatch1 dTable1(opcode,\n      ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174546493,data/full_repos/permissive/174546493/dispatch1\n             data/full_repos/permissive/174546493,data/full_repos/permissive/174546493/dispatch1.v\n             data/full_repos/permissive/174546493,data/full_repos/permissive/174546493/dispatch1.sv\n             dispatch1\n             dispatch1.v\n             dispatch1.sv\n             obj_dir/dispatch1\n             obj_dir/dispatch1.v\n             obj_dir/dispatch1.sv\n%Error: data/full_repos/permissive/174546493/ControlUnitTopModule.v:59: Cannot find file containing module: \'dispatch2\'\n   dispatch2 dTable2(opcode,\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/174546493/ControlUnitTopModule.v:62: Cannot find file containing module: \'dispatch3\'\n   dispatch3 dTable3(opcode,\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/174546493/ControlUnitTopModule.v:66: Cannot find file containing module: \'MUX2X1\'\n  MUX2X1 MUX1(next_address,\n  ^~~~~~\n%Error: data/full_repos/permissive/174546493/ControlUnitTopModule.v:71: Cannot find file containing module: \'controlmemory\'\n   controlmemory controlMem(current_state,\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/174546493/ControlUnitTopModule.v:97: Cannot find file containing module: \'MUX_6X1\'\n    MUX_6X1 MUX(zero,\n    ^~~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module ControlUnit(input clk,
                   input reset,
				   input [5:0] funct,
				   input [5:0] opcode,
				   input overflow
				    );
					
      wire [4:0] next_stateDT1;
	  wire [4:0] next_stateDT2;
	  wire [4:0] next_stateDT3;
	  wire [4:0] current_state;
	  
	  wire iorD, memRd, memWr, irWr;
	  wire [1:0] AluSrcA;
	  wire [2:0] AluSrcB;
	  wire [2:0] AluCtrl;
	  wire [1:0] HiSel;
	  wire [1:0] LoSel;
	  wire HiWr, LoWr, MAluOp;
	  wire [2:0] MemToReg;
	  wire [1:0] RegDst;
	  wire RegWr,PcWr,PcWrCon;
	  wire [2:0] PcSrc;
	  wire intCause;
	  wire causeWrite;
	  wire EPCwrite;
	  
	  reg [2:0] next_address;
	  wire[2:0] next_address1;
	  
	  reg [4:0] zero;
	  reg [4:0] WriteBack;
	  
	  wire[2:0] address_select;
	  


	   
	   initial 
	      begin
		     next_address = 3'd0;
		     WriteBack = 5'd19;
			 zero = 5'd0;
	      end
always@(posedge clk)
	  begin
	   if(!reset)begin
	     next_address = next_address1;
	    end



	  end
	  
      dispatch1 dTable1(opcode,
                        funct,
				        next_stateDT1);
	  dispatch2 dTable2(opcode,
                        funct,
				        next_stateDT2);
	  dispatch3 dTable3(opcode,
                        funct,
				        next_stateDT3);
						
		MUX2X1 MUX1(next_address,
		            overflow,
					current_state,
					address_select);
					
	  controlmemory controlMem(current_state,
				               iorD,
				               memRd,
				               memWr,
				               irWr,
				               AluSrcA,
				               AluSrcB,
				               AluCtrl,
				               HiSel,
				               LoSel,
				               HiWr,
				               LoWr,
				               MAluOp,
				               MemToReg,
				               RegDst,
				               RegWr,
				               PcWr,
				               PcWrCon,
				               PcSrc,
							   
							   intCause,
							   causeWrite,
							   EPCwrite,
							   
				               next_address1);
							   				   
	   MUX_6X1 MUX(zero,
                   next_stateDT1,
                   next_stateDT2,
			       next_stateDT3,
			       5'd1,
				   address_select,
			       WriteBack,
				   5'd32,
			       current_state);

endmodule
module ControlUnit(input clk,
                   input reset,
				   input [5:0] funct,
				   input [5:0] opcode,
				   input overflow
				    );

					
      wire [4:0] next_stateDT1;
	  wire [4:0] next_stateDT2;
	  wire [4:0] next_stateDT3;
	  wire [4:0] current_state;
	  
	  wire iorD, memRd, memWr, irWr;
	  wire [1:0] AluSrcA;
	  wire [2:0] AluSrcB;
	  wire [2:0] AluCtrl;
	  wire [1:0] HiSel;
	  wire [1:0] LoSel;
	  wire HiWr, LoWr, MAluOp;
	  wire [2:0] MemToReg;
	  wire [1:0] RegDst;
	  wire RegWr,PcWr,PcWrCon;
	  wire [2:0] PcSrc;
	  wire intCause;
	  wire causeWrite;
	  wire EPCwrite;
	  
	  reg [2:0] next_address;
	  wire[2:0] next_address1;
	  
	  reg [4:0] zero;
	  reg [4:0] WriteBack;
	  
	  wire[2:0] address_select;
	  


	   
	   initial 
	      begin
		     next_address = 3'd0;
		     WriteBack = 5'd19;
			 zero = 5'd0;
	      end
always@(posedge clk)
	  begin
	   if(!reset)begin
	     next_address = next_address1;
	    end



	  end
	  
      dispatch1 dTable1(opcode,
                        funct,
				        next_stateDT1);
	  dispatch2 dTable2(opcode,
                        funct,
				        next_stateDT2);
	  dispatch3 dTable3(opcode,
                        funct,
				        next_stateDT3);
						
		MUX2X1 MUX1(next_address,
		            overflow,
					current_state,
					address_select);
					
	  controlmemory controlMem(current_state,
				               iorD,
				               memRd,
				               memWr,
				               irWr,
				               AluSrcA,
				               AluSrcB,
				               AluCtrl,
				               HiSel,
				               LoSel,
				               HiWr,
				               LoWr,
				               MAluOp,
				               MemToReg,
				               RegDst,
				               RegWr,
				               PcWr,
				               PcWrCon,
				               PcSrc,
							   
							   intCause,
							   causeWrite,
							   EPCwrite,
							   
				               next_address1);
							   				   
	   MUX_6X1 MUX(zero,
                   next_stateDT1,
                   next_stateDT2,
			       next_stateDT3,
			       5'd1,
				   address_select,
			       WriteBack,
				   5'd32,
			       current_state);

endmodule