data/full_repos/permissive/112219256/decode_stage.v
1: b'%Error: data/full_repos/permissive/112219256/decode_stage.v:272: Cannot find file containing module: \'Control_Unit\'\n    Control_Unit Control(\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/Control_Unit\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/Control_Unit.v\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/Control_Unit.sv\n             Control_Unit\n             Control_Unit.v\n             Control_Unit.sv\n             obj_dir/Control_Unit\n             obj_dir/Control_Unit.v\n             obj_dir/Control_Unit.sv\n%Error: data/full_repos/permissive/112219256/decode_stage.v:314: Cannot find file containing module: \'MUX_4_32\'\n    MUX_4_32 RegRdata1_MUX(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/decode_stage.v:322: Cannot find file containing module: \'MUX_4_32\'\n    MUX_4_32 RegRdata2_MUX(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/decode_stage.v:330: Cannot find file containing module: \'MUX_3_5\'\n    MUX_3_5 RegWaddr_MUX(\n    ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112219256/decode_stage.v:346: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'MULT_EXE_MEM\' generates 2 bits.\n                                                                       : ... In instance decode_stage\n  assign ID_EXE_data  =  |MFHL_ID_EXE  ? (MULT_EXE_MEM ? MULT_HI_LO : EXE_HI_LO) : Bypass_EXE;\n                                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module Branch_Cond(
    input [31:0] A,
    input [31:0] B,
    input [ 5:0] B_Type,
    output       Cond
);
	wire zero, ge, gt, le, lt;
  assign zero = ~(|(A - B));
  assign ge = ~A[31];
  assign gt = ~A[31] &    |A[30:0];
  assign le =  A[31] | (&(~A[31:0]));
  assign lt =  A[31];

  assign Cond = ((B_Type[0] & ~zero | B_Type[1] & zero) | 
                 (B_Type[2] & ge    | B_Type[3] & gt    ))  | 
                 (B_Type[4] & le    | B_Type[5] & lt    );

endmodule
module Branch_Cond(
    input [31:0] A,
    input [31:0] B,
    input [ 5:0] B_Type,
    output       Cond
);

	wire zero, ge, gt, le, lt;
  assign zero = ~(|(A - B));
  assign ge = ~A[31];
  assign gt = ~A[31] &    |A[30:0];
  assign le =  A[31] | (&(~A[31:0]));
  assign lt =  A[31];

  assign Cond = ((B_Type[0] & ~zero | B_Type[1] & zero) | 
                 (B_Type[2] & ge    | B_Type[3] & gt    ))  | 
                 (B_Type[4] & le    | B_Type[5] & lt    );

endmodule