data/full_repos/permissive/169496369/output_reg.v
data/verilator_xmls/5fca12bd-36ee-48a6-ae6a-b6c893150a16.xml
module output_reg(clk, ready, reset, signin, ie, im, sign, e, m);
    input clk, ready, reset;
    
    input signin;
    input [7:0]ie;
    input [24:0]im;
    
    output logic sign;
    output logic [7:0]e;
    output logic [24:0]m;
    
    always_ff@(posedge clk)
    begin
        if(reset)
        begin
            sign <= 0;
            e <= 8'd0;
            m <= 25'd0;
        end
        else if(ready)
        begin
            sign <= signin;
            e <= ie;
            m <= im;
        end
        else
        begin
            sign <= sign;
            e <= e;
            m <= m;
        end
    end
endmodule
module output_reg(clk, ready, reset, signin, ie, im, sign, e, m);

    input clk, ready, reset;
    
    input signin;
    input [7:0]ie;
    input [24:0]im;
    
    output logic sign;
    output logic [7:0]e;
    output logic [24:0]m;
    
    always_ff@(posedge clk)
    begin
        if(reset)
        begin
            sign <= 0;
            e <= 8'd0;
            m <= 25'd0;
        end
        else if(ready)
        begin
            sign <= signin;
            e <= ie;
            m <= im;
        end
        else
        begin
            sign <= sign;
            e <= e;
            m <= m;
        end
    end
endmodule