data/full_repos/permissive/115403704/src/BE.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/4330f8df-3fd5-43ff-8b4e-00a95c264e82.xml
module BEUnit(addr,instr,beout);
    input [1:0]addr;
    input [5:0]instr;
    output [3:0]beout;

    assign beout[3] = (instr==6'h2b) || (instr==6'h29&&addr[1]==1) || (instr==6'h28&&addr==2'b11);
    assign beout[2] = (instr==6'h2b) || (instr==6'h29&&addr[1]==1) || (instr==6'h28&&addr==2'b10);
    assign beout[1] = (instr==6'h2b) || (instr==6'h29&&addr[1]==0) || (instr==6'h28&&addr==2'b01);
    assign beout[0] = (instr==6'h2b) || (instr==6'h29&&addr[1]==0) || (instr==6'h28&&addr==2'b00);
endmodule
module BEUnit(addr,instr,beout);

    input [1:0]addr;
    input [5:0]instr;
    output [3:0]beout;

    assign beout[3] = (instr==6'h2b) || (instr==6'h29&&addr[1]==1) || (instr==6'h28&&addr==2'b11);
    assign beout[2] = (instr==6'h2b) || (instr==6'h29&&addr[1]==1) || (instr==6'h28&&addr==2'b10);
    assign beout[1] = (instr==6'h2b) || (instr==6'h29&&addr[1]==0) || (instr==6'h28&&addr==2'b01);
    assign beout[0] = (instr==6'h2b) || (instr==6'h29&&addr[1]==0) || (instr==6'h28&&addr==2'b00);
endmodule