data/full_repos/permissive/105729015/Testbench_2.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:57: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:59: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:65: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:67: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:111: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:120: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:122: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:126: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:129: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Testbench_2.v:139: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Error: data/full_repos/permissive/105729015/Testbench_2.v:20: Cannot find file containing module: \'lab7_multi\'\n lab7_multi UUT(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/lab7_multi\n             data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/lab7_multi.v\n             data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/lab7_multi.sv\n             lab7_multi\n             lab7_multi.v\n             lab7_multi.sv\n             obj_dir/lab7_multi\n             obj_dir/lab7_multi.v\n             obj_dir/lab7_multi.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lab7_tb2();

	reg ADC_CLK_10;
	wire MAX10_CLK1_50, MAX10_CLK2_50;
	wire [7:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
	reg [1:0] KEY;
	wire [9:0] LEDR;
	reg [9:0] SW;
	wire [31:0] count, orig_val, prime_val;
	reg [31:0] test_number;
	wire [2:0] state;
	wire LED_done, LED_prime;
	reg clk, rst;
	wire [7:0] done;
	wire [7:0] is_prime;
	integer i;
	
	lab7_multi UUT(
					.ADC_CLK_10(ADC_CLK_10),
					.MAX10_CLK1_50(MAX10_CLK1_50),
					.MAX10_CLK2_50(MAX10_CLK2_50),
					.HEX0(HEX0),
					.HEX1(HEX1),
					.HEX2(HEX2),
					.HEX3(HEX3),
					.HEX4(HEX4),
					.HEX5(HEX5),
					.KEY(KEY),
					.LEDR(LEDR),
					.SW(SW),
					.count(count),
					.orig_val(orig_val),
					.prime_val(prime_val),
					.test_number(test_number),
					.state(state),
					.LED_done(LED_done),
					.LED_prime(LED_prime),
					.done(done),
					.is_prime(is_prime)
					);
					
	assign MAX10_CLK1_50 = clk;
	
					
	initial begin
	

		test_number = 32'd1000;
		clk = 1'b0;
		SW[9:0] = 10'b0000000000;
		KEY[1:0] = 2'b11;
		

		repeat (100) begin
			#3;
			clk = ~clk;
			#3;
		end
		
		SW[9] = 1'b1;
		
		repeat (100) begin
			#3;
			clk = ~clk;
			#3;
		end
		
		SW[9] = 1'b0;

		
			repeat (100) begin
				#3;
				clk = ~clk;
				#3;

			end
			
			KEY[1] = 1'b1;
			
			repeat (100) begin
				#3;
				clk = ~clk;
				#3;
			end
			
			KEY[1] = 1'b0;
			
			while(LED_done != 1'b1) begin
				#3;
				clk = ~clk;
				#3;
				if (clk == 1'b1) begin
					$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
				end
			end

			$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
			
			
			repeat (100) begin
				#3;
				clk = ~clk;
				#3;

			end
			
			$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
			
			KEY[1] = 1'b1;
			
			repeat (100) begin
				#3;
				clk = ~clk;
				#3;
			end
			test_number = 32'd1164;
			KEY[1] = 1'b0;
			#3;
			
			repeat (10) begin
				#3;
				clk = ~clk;
				#3;
			end
			$display("Here");
			$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);

			while (LED_done != 1'b1) begin
				#3;
				clk = ~clk;
				#3;
				if(clk == 1'b1) begin
					$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
				end
			end
			$display("Here2");
			

	end

endmodule
module lab7_tb2();


	reg ADC_CLK_10;
	wire MAX10_CLK1_50, MAX10_CLK2_50;
	wire [7:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
	reg [1:0] KEY;
	wire [9:0] LEDR;
	reg [9:0] SW;
	wire [31:0] count, orig_val, prime_val;
	reg [31:0] test_number;
	wire [2:0] state;
	wire LED_done, LED_prime;
	reg clk, rst;
	wire [7:0] done;
	wire [7:0] is_prime;
	integer i;
	
	lab7_multi UUT(
					.ADC_CLK_10(ADC_CLK_10),
					.MAX10_CLK1_50(MAX10_CLK1_50),
					.MAX10_CLK2_50(MAX10_CLK2_50),
					.HEX0(HEX0),
					.HEX1(HEX1),
					.HEX2(HEX2),
					.HEX3(HEX3),
					.HEX4(HEX4),
					.HEX5(HEX5),
					.KEY(KEY),
					.LEDR(LEDR),
					.SW(SW),
					.count(count),
					.orig_val(orig_val),
					.prime_val(prime_val),
					.test_number(test_number),
					.state(state),
					.LED_done(LED_done),
					.LED_prime(LED_prime),
					.done(done),
					.is_prime(is_prime)
					);
					
	assign MAX10_CLK1_50 = clk;
	
					
	initial begin
	

		test_number = 32'd1000;
		clk = 1'b0;
		SW[9:0] = 10'b0000000000;
		KEY[1:0] = 2'b11;
		

		repeat (100) begin
			#3;
			clk = ~clk;
			#3;
		end
		
		SW[9] = 1'b1;
		
		repeat (100) begin
			#3;
			clk = ~clk;
			#3;
		end
		
		SW[9] = 1'b0;

		
			repeat (100) begin
				#3;
				clk = ~clk;
				#3;

			end
			
			KEY[1] = 1'b1;
			
			repeat (100) begin
				#3;
				clk = ~clk;
				#3;
			end
			
			KEY[1] = 1'b0;
			
			while(LED_done != 1'b1) begin
				#3;
				clk = ~clk;
				#3;
				if (clk == 1'b1) begin
					$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
				end
			end

			$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
			
			
			repeat (100) begin
				#3;
				clk = ~clk;
				#3;

			end
			
			$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
			
			KEY[1] = 1'b1;
			
			repeat (100) begin
				#3;
				clk = ~clk;
				#3;
			end
			test_number = 32'd1164;
			KEY[1] = 1'b0;
			#3;
			
			repeat (10) begin
				#3;
				clk = ~clk;
				#3;
			end
			$display("Here");
			$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);

			while (LED_done != 1'b1) begin
				#3;
				clk = ~clk;
				#3;
				if(clk == 1'b1) begin
					$display("test_number: %d, state: %b, testing: %d, done: %b, orig: %d, is_prime: %b, prime_val: %d, LED_done: %b, LED_prime: %b", test_number, state, count, done, orig_val, is_prime, prime_val, LED_done, LED_prime);
				end
			end
			$display("Here2");
			

	end

endmodule