data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v
 line:93: before: "("
1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:1: Cannot find include file: def.vh\n`include "def.vh" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.v\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.sv\n             def.vh\n             def.vh.v\n             def.vh.sv\n             obj_dir/def.vh\n             obj_dir/def.vh.v\n             obj_dir/def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:6: Define or directive not defined: \'`ERRC_BITDEF\'\n output [`ERRC_BITDEF] errno,\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n output [`ERRC_BITDEF] errno,\n                     ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:11: Define or directive not defined: \'`OPTYPE_BITDEF\'\n output [`OPTYPE_BITDEF] optype,  \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:23: Define or directive not defined: \'`ERRC_BITDEF\'\n reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;\n                  ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:24: syntax error, unexpected assign\n reg [31:0] Rnpc; assign out_npc = Rnpc;\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:25: syntax error, unexpected assign\n reg [5:0] Ropc; assign opcode = Ropc;\n                 ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:26: Define or directive not defined: \'`OPTYPE_BITDEF\'\n reg [`OPTYPE_BITDEF] Ropt; assign optype = Ropt;\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:26: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`OPTYPE_BITDEF] Ropt; assign optype = Ropt;\n                    ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:27: syntax error, unexpected assign\n reg [4:0] Rrar; assign rar = Rrar;\n                 ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:28: syntax error, unexpected assign\n reg [31:0] Rrav; assign rav = Rrav;\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:29: syntax error, unexpected assign\n reg [4:0] Rrbr; assign rbr = Rrbr;\n                 ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:30: syntax error, unexpected assign\n reg [31:0] Rrbv; assign rbv = Rrbv;\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:31: syntax error, unexpected assign\n reg [4:0] Rrout; assign rout = Rrout;\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:32: syntax error, unexpected assign\n reg [10:0] Raux; assign aux = Raux;\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:33: syntax error, unexpected assign\n reg [15:0] Rimm; assign imm = Rimm;\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:34: syntax error, unexpected assign\n reg [25:0] Raddr; assign addr = Raddr;\n                   ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:35: syntax error, unexpected assign\n reg [31:0] Rmem_read_addr; assign mem_read_addr = Rmem_read_addr;\n                            ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:37: syntax error, unexpected assign\n wire [5:0] WOopc; assign WOopc = instruction[31:26];\n                   ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:38: syntax error, unexpected assign\n wire [4:0] WOrs; assign WOrs = instruction[25:21];\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:39: syntax error, unexpected assign\n wire [4:0] WOrt; assign WOrt = instruction[20:16];\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:40: syntax error, unexpected assign\n wire [4:0] WOrd; assign WOrd = instruction[15:11];\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:41: syntax error, unexpected assign\n wire [10:0]WOaux; assign WOaux = instruction[10:0];\n                   ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:42: syntax error, unexpected assign\n wire [15:0]WOimm; assign WOimm = instruction[15:0];\n                   ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:43: syntax error, unexpected assign\n wire [25:0]WOaddr; assign WOaddr = instruction[25:0];\n                    ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:45: syntax error, unexpected assign\n wire [4:0] Wshift; assign Wshift = Raux[10:6];\n                    ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:46: syntax error, unexpected assign\n wire [5:0] WauxV; assign WauxV = Raux[5:0];\n                   ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:58: Define or directive not defined: \'`OPTYPE_R\'\n   Ropc <= Aopc; Ropt <= `OPTYPE_R;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:58: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   Ropc <= Aopc; Ropt <= `OPTYPE_R;\n                                  ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:65: Define or directive not defined: \'`OPTYPE_I\'\n   Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arar, 0, 0, 0);\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arar, 0, 0, 0);\n                                  ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:71: Define or directive not defined: \'`OPTYPE_I\'\n   Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arsrc, 0, Araddr, 0);\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:71: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arsrc, 0, Araddr, 0);\n                                  ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:75: Define or directive not defined: \'`OPTYPE_BITDEF\'\n task TopIpass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:75: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n task TopIpass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);\n                                                      ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:81: Define or directive not defined: \'`OPTYPE_BITDEF\'\n task TopApass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:81: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n task TopApass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);\n                                                      ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:93: Define or directive not defined: \'`PC_ILLEGAL\'\n   Rnpc <= `PC_ILLEGAL;\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:98: Define or directive not defined: \'`OPCODE_AUX\'\n   if(WOopc == `OPCODE_AUX) begin\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:100: Define or directive not defined: \'`OPCODE_ADDI\'\n   end else if(WOopc == `OPCODE_ADDI) begin\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:101: Define or directive not defined: \'`OPCODE_AUX\'\n    TopR(`OPCODE_AUX, WOrs, 0, 0,\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:102: Define or directive not defined: \'`EXTSGN16to32\'\n       `EXTSGN16to32(WOimm),\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:103: Define or directive not defined: \'`ALUC_ADD\'\n     WOrt, `ALUC_ADD);\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:104: Define or directive not defined: \'`OPCODE_LUI\'\n   end else if(WOopc == `OPCODE_LUI) begin\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:105: Define or directive not defined: \'`OPCODE_AUX\'\n    TopR(`OPCODE_AUX, 0, 0, 0,\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:107: Define or directive not defined: \'`ALUC_OR\'\n     WOrt, `ALUC_OR);\n           ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:108: Define or directive not defined: \'`OPCODE_ANDI\'\n   end else if(WOopc == `OPCODE_ANDI) begin\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:109: Define or directive not defined: \'`OPCODE_AUX\'\n    TopR(`OPCODE_AUX, WOrs, 0, 0,\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/predecoder.v:110: Define or directive not defined: \'`EXTZER16to32\'\n       `EXTZER16to32(WOimm),\n       ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module predecoder(
	input clk,
	input rst,
	output [`ERRC_BITDEF] errno,
	input [31:0] in_npc,
	input [31:0] instruction,
	output [31:0] out_npc,
	output [5:0] opcode,
	output [`OPTYPE_BITDEF] optype,
	output [4:0] rar,
	output [31:0] rav,
	output [4:0] rbr,
	output [31:0] rbv,
	output [4:0] rout,
	output [10:0] aux,
	output [15:0] imm,
	output [25:0] addr,
	output [31:0] mem_read_addr
	);

	reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;
	reg [31:0] Rnpc; assign out_npc = Rnpc;
	reg [5:0] Ropc; assign opcode = Ropc;
	reg [`OPTYPE_BITDEF] Ropt; assign optype = Ropt;
	reg [4:0] Rrar; assign rar = Rrar;
	reg [31:0] Rrav; assign rav = Rrav;
	reg [4:0] Rrbr; assign rbr = Rrbr;
	reg [31:0] Rrbv; assign rbv = Rrbv;
	reg [4:0] Rrout; assign rout = Rrout;
	reg [10:0] Raux; assign aux = Raux;
	reg [15:0] Rimm; assign imm = Rimm;
	reg [25:0] Raddr; assign addr = Raddr;
	reg [31:0] Rmem_read_addr; assign mem_read_addr = Rmem_read_addr;

	wire [5:0] WOopc; assign WOopc = instruction[31:26];
	wire [4:0] WOrs; assign WOrs = instruction[25:21];
	wire [4:0] WOrt; assign WOrt = instruction[20:16];
	wire [4:0] WOrd; assign WOrd = instruction[15:11];
	wire [10:0]WOaux; assign WOaux = instruction[10:0];
	wire [15:0]WOimm; assign WOimm = instruction[15:0];
	wire [25:0]WOaddr; assign WOaddr = instruction[25:0];

	wire [4:0] Wshift; assign Wshift = Raux[10:6];
	wire [5:0] WauxV; assign WauxV = Raux[5:0];

	task Tset_register(input [4:0] Arar, input [31:0] Arav, input[4:0] Arbr, input [31:0] Arbv);
		begin
			Rrar <= Arar; Rrav <= Arav; Rrbr <= Arbr; Rrbv <= Arbv;
		end
	endtask
	task TopR(
		input [5:0] Aopc,
		input [4:0] Arar, input [31:0] Arav, input[4:0] Arbr, input [31:0] Arbv,
		input [4:0] Arout, input [10:0] Aaux);
		begin
			Ropc <= Aopc; Ropt <= `OPTYPE_R;
			Tset_register(Arar, Arav, Arbr, Arbv);
			Rrout <= Arout; Raux <= Aaux; Rimm <= 0; Raddr <= 0; Rmem_read_addr <= 0;
		end
	endtask
	task TopImemread_offset(input [5:0] Aopc, input [5:0] Arar, input [4:0] Arout);
		begin
			Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arar, 0, 0, 0);
			Rrout <= Arout; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
		end
	endtask
	task TopImemwrite_offset(input [5:0] Aopc, input [5:0] Arsrc, input [4:0] Araddr);
		begin
			Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arsrc, 0, Araddr, 0);
			Rrout <= 0; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
		end
	endtask
	task TopIpass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);
		begin
			Ropc <= Aopc; Ropt <= Aopt; Tset_register(WOrs, 0, WOrt, 0);
			Rrout <= 0; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
		end
	endtask
	task TopApass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);
		begin
			Ropc <= Aopc; Ropt <= Aopt; Tset_register(0, 0, 0, 0);
			Rrout <= 0; Raux <= 0; Rimm <= 0; Raddr <= WOaddr;
		end
	endtask

	always @ (posedge clk or posedge rst) begin
		if (rst || Rerrno) begin
			if (rst) begin
				Rerrno <= 0;
			end
			Rnpc <= `PC_ILLEGAL;
			Ropc <= 0; Ropt <= 0; Rrar <= 0; Rrav <= 0; Rrbr <= 0; Rrbv <= 0;
			Rrout <= 0; Raux <= 0; Rmem_read_addr <= 0;
		end else if(Rerrno == 0) begin
			Rnpc <= in_npc;
			if(WOopc == `OPCODE_AUX) begin
				TopR(WOopc, WOrs, 0, WOrt, 0, WOrd, WOaux);
			end else if(WOopc == `OPCODE_ADDI) begin
				TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTSGN16to32(WOimm),
					WOrt, `ALUC_ADD);
			end else if(WOopc == `OPCODE_LUI) begin
				TopR(`OPCODE_AUX, 0, 0, 0,
WOimm << 16,
					WOrt, `ALUC_OR);
			end else if(WOopc == `OPCODE_ANDI) begin
				TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
					WOrt, `ALUC_AND);
			end else if(WOopc == `OPCODE_ORI) begin
				TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
					WOrt, `ALUC_OR);
			end else if(WOopc == `OPCODE_XORI) begin
				TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
					WOrt, `ALUC_XOR);
			end else if(WOopc == `OPCODE_HALT) begin
				Ropc <= WOopc;
				Ropt <= `OPTYPE_A;
				Rrar <= 0; Rrav <= 0; Rrbv <= 0; Rrbr <= 0; Rrout <= 0;
			end else if(WOopc == `OPCODE_LW) begin
				TopImemread_offset(WOopc, WOrs, WOrt);
			end else if(WOopc == `OPCODE_SW) begin
				TopImemwrite_offset(WOopc, WOrt, WOrs);
			end else if(WOopc == `OPCODE_BEQ || WOopc == `OPCODE_BNE
				|| WOopc == `OPCODE_BLT || WOopc == `OPCODE_BLE) begin
				TopIpass(WOopc, `OPTYPE_VJ);
			end else if(WOopc == `OPCODE_J) begin
				TopApass(WOopc, `OPTYPE_VJ);
			end else if(WOopc == `OPCODE_JAL) begin
				TopApass(WOopc, `OPTYPE_A);
			end else if(WOopc == `OPCODE_JR) begin
				TopR(WOopc, WOrs, 0, 0, 0, 0, `ALUC_NONE);
			end else begin

				Rerrno <= `ERRC_ILL;
			end
		end
	end
endmodule
module predecoder(
	input clk,
	input rst,
	output [`ERRC_BITDEF] errno,
	input [31:0] in_npc,
	input [31:0] instruction,
	output [31:0] out_npc,
	output [5:0] opcode,
	output [`OPTYPE_BITDEF] optype,
	output [4:0] rar,
	output [31:0] rav,
	output [4:0] rbr,
	output [31:0] rbv,
	output [4:0] rout,
	output [10:0] aux,
	output [15:0] imm,
	output [25:0] addr,
	output [31:0] mem_read_addr
	);


	reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;
	reg [31:0] Rnpc; assign out_npc = Rnpc;
	reg [5:0] Ropc; assign opcode = Ropc;
	reg [`OPTYPE_BITDEF] Ropt; assign optype = Ropt;
	reg [4:0] Rrar; assign rar = Rrar;
	reg [31:0] Rrav; assign rav = Rrav;
	reg [4:0] Rrbr; assign rbr = Rrbr;
	reg [31:0] Rrbv; assign rbv = Rrbv;
	reg [4:0] Rrout; assign rout = Rrout;
	reg [10:0] Raux; assign aux = Raux;
	reg [15:0] Rimm; assign imm = Rimm;
	reg [25:0] Raddr; assign addr = Raddr;
	reg [31:0] Rmem_read_addr; assign mem_read_addr = Rmem_read_addr;

	wire [5:0] WOopc; assign WOopc = instruction[31:26];
	wire [4:0] WOrs; assign WOrs = instruction[25:21];
	wire [4:0] WOrt; assign WOrt = instruction[20:16];
	wire [4:0] WOrd; assign WOrd = instruction[15:11];
	wire [10:0]WOaux; assign WOaux = instruction[10:0];
	wire [15:0]WOimm; assign WOimm = instruction[15:0];
	wire [25:0]WOaddr; assign WOaddr = instruction[25:0];

	wire [4:0] Wshift; assign Wshift = Raux[10:6];
	wire [5:0] WauxV; assign WauxV = Raux[5:0];

	task Tset_register(input [4:0] Arar, input [31:0] Arav, input[4:0] Arbr, input [31:0] Arbv);
		begin
			Rrar <= Arar; Rrav <= Arav; Rrbr <= Arbr; Rrbv <= Arbv;
		end
	endtask
	task TopR(
		input [5:0] Aopc,
		input [4:0] Arar, input [31:0] Arav, input[4:0] Arbr, input [31:0] Arbv,
		input [4:0] Arout, input [10:0] Aaux);
		begin
			Ropc <= Aopc; Ropt <= `OPTYPE_R;
			Tset_register(Arar, Arav, Arbr, Arbv);
			Rrout <= Arout; Raux <= Aaux; Rimm <= 0; Raddr <= 0; Rmem_read_addr <= 0;
		end
	endtask
	task TopImemread_offset(input [5:0] Aopc, input [5:0] Arar, input [4:0] Arout);
		begin
			Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arar, 0, 0, 0);
			Rrout <= Arout; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
		end
	endtask
	task TopImemwrite_offset(input [5:0] Aopc, input [5:0] Arsrc, input [4:0] Araddr);
		begin
			Ropc <= Aopc; Ropt <= `OPTYPE_I; Tset_register(Arsrc, 0, Araddr, 0);
			Rrout <= 0; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
		end
	endtask
	task TopIpass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);
		begin
			Ropc <= Aopc; Ropt <= Aopt; Tset_register(WOrs, 0, WOrt, 0);
			Rrout <= 0; Raux <= 0; Rimm <= WOimm; Raddr <= 0;
		end
	endtask
	task TopApass(input [5:0] Aopc, input [`OPTYPE_BITDEF] Aopt);
		begin
			Ropc <= Aopc; Ropt <= Aopt; Tset_register(0, 0, 0, 0);
			Rrout <= 0; Raux <= 0; Rimm <= 0; Raddr <= WOaddr;
		end
	endtask

	always @ (posedge clk or posedge rst) begin
		if (rst || Rerrno) begin
			if (rst) begin
				Rerrno <= 0;
			end
			Rnpc <= `PC_ILLEGAL;
			Ropc <= 0; Ropt <= 0; Rrar <= 0; Rrav <= 0; Rrbr <= 0; Rrbv <= 0;
			Rrout <= 0; Raux <= 0; Rmem_read_addr <= 0;
		end else if(Rerrno == 0) begin
			Rnpc <= in_npc;
			if(WOopc == `OPCODE_AUX) begin
				TopR(WOopc, WOrs, 0, WOrt, 0, WOrd, WOaux);
			end else if(WOopc == `OPCODE_ADDI) begin
				TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTSGN16to32(WOimm),
					WOrt, `ALUC_ADD);
			end else if(WOopc == `OPCODE_LUI) begin
				TopR(`OPCODE_AUX, 0, 0, 0,
WOimm << 16,
					WOrt, `ALUC_OR);
			end else if(WOopc == `OPCODE_ANDI) begin
				TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
					WOrt, `ALUC_AND);
			end else if(WOopc == `OPCODE_ORI) begin
				TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
					WOrt, `ALUC_OR);
			end else if(WOopc == `OPCODE_XORI) begin
				TopR(`OPCODE_AUX, WOrs, 0, 0,
`EXTZER16to32(WOimm),
					WOrt, `ALUC_XOR);
			end else if(WOopc == `OPCODE_HALT) begin
				Ropc <= WOopc;
				Ropt <= `OPTYPE_A;
				Rrar <= 0; Rrav <= 0; Rrbv <= 0; Rrbr <= 0; Rrout <= 0;
			end else if(WOopc == `OPCODE_LW) begin
				TopImemread_offset(WOopc, WOrs, WOrt);
			end else if(WOopc == `OPCODE_SW) begin
				TopImemwrite_offset(WOopc, WOrt, WOrs);
			end else if(WOopc == `OPCODE_BEQ || WOopc == `OPCODE_BNE
				|| WOopc == `OPCODE_BLT || WOopc == `OPCODE_BLE) begin
				TopIpass(WOopc, `OPTYPE_VJ);
			end else if(WOopc == `OPCODE_J) begin
				TopApass(WOopc, `OPTYPE_VJ);
			end else if(WOopc == `OPCODE_JAL) begin
				TopApass(WOopc, `OPTYPE_A);
			end else if(WOopc == `OPCODE_JR) begin
				TopR(WOopc, WOrs, 0, 0, 0, 0, `ALUC_NONE);
			end else begin

				Rerrno <= `ERRC_ILL;
			end
		end
	end
endmodule