data/full_repos/permissive/161275071/sys/spdif.v
 line:67: before: "reg"
1: b'%Warning-WIDTH: data/full_repos/permissive/161275071/sys/spdif.v:72: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'div\' generates 4 bits.\n                                                                   : ... In instance spdif\n lpf_ce <= !div;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/161275071/sys/spdif.v:77: Cannot find file containing module: \'lpf48k\'\nlpf48k #(15) lpf_l\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161275071/sys,data/full_repos/permissive/161275071/lpf48k\n             data/full_repos/permissive/161275071/sys,data/full_repos/permissive/161275071/lpf48k.v\n             data/full_repos/permissive/161275071/sys,data/full_repos/permissive/161275071/lpf48k.sv\n             lpf48k\n             lpf48k.v\n             lpf48k.sv\n             obj_dir/lpf48k\n             obj_dir/lpf48k.v\n             obj_dir/lpf48k.sv\n%Error: data/full_repos/permissive/161275071/sys/spdif.v:88: Cannot find file containing module: \'lpf48k\'\nlpf48k #(15) lpf_r\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161275071/sys/spdif.v:116: Operator LT expects 64 bits on the LHS, but LHS\'s VARREF \'error_q\' generates 32 bits.\n                                                                    : ... In instance spdif\n   if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin\n               ^\n%Warning-WIDTH: data/full_repos/permissive/161275071/sys/spdif.v:130: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'count_q\' generates 32 bits.\n                                                                    : ... In instance spdif\n  if(!count_q) begin\n     ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module spdif




#(
    parameter CLK_RATE              = 50000000,
    parameter AUDIO_RATE            = 48000,


    parameter WHOLE_CYCLES          = (CLK_RATE) / (AUDIO_RATE*128),
    parameter ERROR_BASE            = 10000,
    parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE)
)




(
    input        clk_i,
    input        rst_i,
    input        half_rate,


    output       spdif_o,


    input [15:0] audio_r,
    input [15:0] audio_l,
    output       sample_req_o
);

reg lpf_ce;
always @(negedge clk_i) begin
	reg [3:0] div;

	div <= div + 1'd1;
	if(div == 13) div <= 0;

	lpf_ce <= !div;
end

wire [15:0] al, ar;

lpf48k #(15) lpf_l
(
   .RESET(rst_i),
   .CLK(clk_i),
   .CE(lpf_ce),
	.ENABLE(1),

   .IDATA(audio_l),
   .ODATA(al)
);

lpf48k #(15) lpf_r
(
   .RESET(rst_i),
   .CLK(clk_i),
   .CE(lpf_ce),
	.ENABLE(1),

   .IDATA(audio_r),
   .ODATA(ar)
);

reg         bit_clk_q;


always @ (posedge rst_i or posedge clk_i) begin
	reg [31:0]  count_q;
	reg [31:0]  error_q;
	reg ce;

	if (rst_i) begin
		count_q   <= 0;
		error_q   <= 0;
		bit_clk_q <= 1;
		ce        <= 0;
	end
	else
	begin
		if(count_q == WHOLE_CYCLES-1) begin
			if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
				error_q <= error_q + ERRORS_PER_BIT[31:0];
				count_q <= 0;
			end else begin
				error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
				count_q <= count_q + 1;
			end
		end else if(count_q == WHOLE_CYCLES) begin
			count_q <= 0;
		end else begin
			count_q <= count_q + 1;
		end

		bit_clk_q <= 0;
		if(!count_q) begin
			ce <= ~ce;
			if(~half_rate || ce) bit_clk_q <= 1;
		end
	end
end





wire [31:0] sample_i = {ar, al};

spdif_core
u_core
(
    .clk_i(clk_i),
    .rst_i(rst_i),

    .bit_out_en_i(bit_clk_q),

    .spdif_o(spdif_o),

    .sample_i(sample_i),
    .sample_req_o(sample_req_o)
);

endmodule
module spdif




#(
    parameter CLK_RATE              = 50000000,
    parameter AUDIO_RATE            = 48000,


    parameter WHOLE_CYCLES          = (CLK_RATE) / (AUDIO_RATE*128),
    parameter ERROR_BASE            = 10000,
    parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE)
)




(
    input        clk_i,
    input        rst_i,
    input        half_rate,


    output       spdif_o,


    input [15:0] audio_r,
    input [15:0] audio_l,
    output       sample_req_o
);


reg lpf_ce;
always @(negedge clk_i) begin
	reg [3:0] div;

	div <= div + 1'd1;
	if(div == 13) div <= 0;

	lpf_ce <= !div;
end

wire [15:0] al, ar;

lpf48k #(15) lpf_l
(
   .RESET(rst_i),
   .CLK(clk_i),
   .CE(lpf_ce),
	.ENABLE(1),

   .IDATA(audio_l),
   .ODATA(al)
);

lpf48k #(15) lpf_r
(
   .RESET(rst_i),
   .CLK(clk_i),
   .CE(lpf_ce),
	.ENABLE(1),

   .IDATA(audio_r),
   .ODATA(ar)
);

reg         bit_clk_q;


always @ (posedge rst_i or posedge clk_i) begin
	reg [31:0]  count_q;
	reg [31:0]  error_q;
	reg ce;

	if (rst_i) begin
		count_q   <= 0;
		error_q   <= 0;
		bit_clk_q <= 1;
		ce        <= 0;
	end
	else
	begin
		if(count_q == WHOLE_CYCLES-1) begin
			if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
				error_q <= error_q + ERRORS_PER_BIT[31:0];
				count_q <= 0;
			end else begin
				error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
				count_q <= count_q + 1;
			end
		end else if(count_q == WHOLE_CYCLES) begin
			count_q <= 0;
		end else begin
			count_q <= count_q + 1;
		end

		bit_clk_q <= 0;
		if(!count_q) begin
			ce <= ~ce;
			if(~half_rate || ce) bit_clk_q <= 1;
		end
	end
end





wire [31:0] sample_i = {ar, al};

spdif_core
u_core
(
    .clk_i(clk_i),
    .rst_i(rst_i),

    .bit_out_en_i(bit_clk_q),

    .spdif_o(spdif_o),

    .sample_i(sample_i),
    .sample_req_o(sample_req_o)
);

endmodule