data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:358: Cannot find file containing module: 'NOR3A'\n    NOR3A \\SM_8S_1_i_0_a3[3]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .C(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A.sv\n             NOR3A\n             NOR3A.v\n             NOR3A.sv\n             obj_dir/NOR3A\n             obj_dir/NOR3A.v\n             obj_dir/NOR3A.sv\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:360: Cannot find file containing module: 'NOR2A'\n    NOR2A \\SM_8S_1_i_0_1[3]  (.A(SM_8S_1_i_0_a3_0_0), .B(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:362: Cannot find file containing module: 'NOR2B'\n    NOR2B \\SM_8S_1_i_0_o2[1]  (.A(Disp_dat[3]), .B(Disp_dat[1]), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:364: Cannot find file containing module: 'NOR3B'\n    NOR3B \\SM_8S_1_i_i_a2[6]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:366: Cannot find file containing module: 'AX1C'\n    AX1C \\SM_8S_1_i_i_x2[6]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:368: Cannot find file containing module: 'GND'\n    GND GND_i_0 (.Y(GND_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:369: Cannot find file containing module: 'NOR2'\n    NOR2 \\SM_8S_1_0_0_o2[5]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:371: Cannot find file containing module: 'OR2B'\n    OR2B \\SM_8S_1_i_0_a3_0[1]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:373: Cannot find file containing module: 'AO1C'\n    AO1C \\SM_8S_1_0_0[5]  (.A(N_17), .B(Disp_dat[0]), .C(N_15_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:375: Cannot find file containing module: 'VCC'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:376: Cannot find file containing module: 'OR3C'\n    OR3C \\SM_8S_1_0_i_a3_0[2]  (.A(Disp_dat[3]), .B(Disp_dat[0]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:378: Cannot find file containing module: 'AO1A'\n    AO1A \\SM_8S_1_i_i_a3[6]  (.A(Disp_dat[0]), .B(Disp_dat[2]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:380: Cannot find file containing module: 'AOI1B'\n    AOI1B \\SM_8S_1_i_i_a3_0[4]  (.A(Disp_dat[2]), .B(Disp_dat[1]), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:382: Cannot find file containing module: 'GND'\n    GND GND_i (.Y(GND));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:383: Cannot find file containing module: 'XOR2'\n    XOR2 \\SM_8S_1_i_0_x2[0]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:385: Cannot find file containing module: 'OA1B'\n    OA1B \\SM_8S_1_i_0[1]  (.A(N_19), .B(\\SM_8S_1_i_0_a3_0[1]_net_1 ), \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:387: Cannot find file containing module: 'VCC'\n    VCC VCC_i_0 (.Y(VCC_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:388: Cannot find file containing module: 'OR2B'\n    OR2B \\SM_8S_1_i_i_1[6]  (.A(N_70), .B(N_15_i), .Y(Seg_c[6]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:389: Cannot find file containing module: 'OR2A'\n    OR2A \\SM_8S_1_i_0_a3_0[0]  (.A(N_19), .B(N_14_i_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:683: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_3[2]  (.A(Q_NS_e2_0_a2_1_0), .B(N_30), .Y(N_40));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:684: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_2[2]  (.A(Q_NS[2]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:686: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[1]  (.A(N_34), .B(Q_NS_e1_0_0), .C(N_39_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:688: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_0[4]  (.A(Q_NS[4]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:690: Cannot find file containing module: 'OR2B'\n    OR2B Q_NS_e1_0_a2_4 (.A(N_30), .B(one_seond_clk_0_Cout), .Y(N_62));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:691: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_1[7]  (.A(Q_NS[7]), .B(Q_NSlde_i_o2tt_m1_0_a2), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:693: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[7]  (.A(N_56), .B(N_58), .C(N_57), .Y(Q_NS_e7));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:694: Cannot find file containing module: 'OR3'\n    OR3 \\Q_NS_RNO_2[3]  (.A(N_19), .B(Q_NS[3]), .C(N_62), .Y(N_44));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:695: Cannot find file containing module: 'OA1'\n    OA1 \\Q_NS_RNO_2[6]  (.A(N_22), .B(Q_NS[5]), .C(Q_NS[6]), .Y(\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:697: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_0[3]  (.A(Q_NS_e3_0_a2_0), .B(N_30), .Y(N_43));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:698: Cannot find file containing module: 'NOR2B'\n    NOR2B \\Q_NS_RNO_3[3]  (.A(Q_NS[3]), .B(N_19), .Y(Q_NS_e3_0_a2_0));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:699: Cannot find file containing module: 'VCC'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:700: Cannot find file containing module: 'NOR2B'\n    NOR2B \\Q_NS_RNO_3[5]  (.A(Q_NS[5]), .B(N_22), .Y(Q_NS_e5_0_a2_0_0));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:701: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNO_0[7]  (.A(N_30), .B(Q_NS[7]), .C(N_26), .Y(N_56));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:702: Cannot find file containing module: 'NOR3'\n    NOR3 \\Q_NS_RNISBRL[6]  (.A(N_22), .B(Q_NS[5]), .C(Q_NS[6]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:704: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[0]  (.D(Q_NS_e0), .CLK(Clk_c), .Q(Q_NS[0]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:705: Cannot find file containing module: 'AO1C'\n    AO1C \\Q_NS_RNO[2]  (.A(N_19), .B(N_24), .C(Q_NS_e2_0_2), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:707: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNIF75S[7]  (.A(one_seond_clk_0_Cout), .B(N_26), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:709: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNO_1[2]  (.A(Green2_c), .B(N_16), .C(N_30), .Y(N_41));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:710: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[7]  (.D(Q_NS_e7), .CLK(Clk_c), .Q(Q_NS[7]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:711: Cannot find file containing module: 'NOR2A'\n    NOR2A Q_NS_e2_0_a2_4_1 (.A(current_state[0]), .B(Red1_c), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:713: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[5]  (.D(Q_NS_e5), .CLK(Clk_c), .Q(Q_NS[5]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:714: Cannot find file containing module: 'NOR3C'\n    NOR3C \\Q_NS_RNO_0[2]  (.A(N_41), .B(Q_NS_e2_0_0), .C(N_39_i), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:716: Cannot find file containing module: 'NOR2'\n    NOR2 un1_Reset_1_i_i_a2 (.A(Ld_i), .B(Reset_c), .Y(N_30));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:717: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[3]  (.A(N_43), .B(N_45), .C(N_44), .Y(Q_NS_e3));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:718: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_0[6]  (.A(Q_NS[6]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:720: Cannot find file containing module: 'OR3A'\n    OR3A \\Q_NS_RNO_2[7]  (.A(N_26), .B(N_62), .C(Q_NS[7]), .Y(N_57));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:721: Cannot find file containing module: 'OA1'\n    OA1 \\Q_NS_RNO_4[2]  (.A(Q_NS[0]), .B(Q_NS[1]), .C(Q_NS[2]), .Y(\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:723: Cannot find file containing module: 'OR3A'\n    OR3A \\Q_NS_RNO_1[5]  (.A(N_24), .B(N_22), .C(Q_NS[5]), .Y(N_51));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:724: Cannot find file containing module: 'AO1C'\n    AO1C \\Q_NS_RNO[6]  (.A(N_62), .B(N_26), .C(Q_NS_e6_0_0), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:726: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_1[6]  (.A(Q_NS_e6_0_a2_0), .B(N_30), .Y(N_54));\n    ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module one_seond_clk(
       Clk_c,
       one_seond_clk_0_Cout,
       Reset_c
    );
input  Clk_c;
output one_seond_clk_0_Cout;
input  Reset_c;

    wire Count_19_0, \Count[8]_net_1 , un1_Reset_1, un1_Count_2_6, 
        un1_Count_2_1, un1_Count_2_0, Count_c1, un1_Count_2_5, 
        \Count[7]_net_1 , un1_Count_2_3, \Count[3]_net_1 , 
        \Count[4]_net_1 , \Count[5]_net_1 , \Count[6]_net_1 , 
        \Count[9]_net_1 , \Count[2]_net_1 , Count_n2, Count_n3, 
        Count_c2, Count_n4, Count_c3, Count_n5, Count_c4, Count_n6, 
        Count_c5, Count_n7, Count_c6, Count_n8, Count_c7, Count13, 
        \Count[1]_net_1 , \Count[0]_net_1 , N_49, Count_n0, Count_n1, 
        Count_n9, GND, VCC, GND_0, VCC_0;
    
    DFN1 \Count[5]  (.D(Count_n5), .CLK(Clk_c), .Q(\Count[5]_net_1 ));
    DFN1 \Count[1]  (.D(Count_n1), .CLK(Clk_c), .Q(\Count[1]_net_1 ));
    DFN1 \Count[0]  (.D(Count_n0), .CLK(Clk_c), .Q(\Count[0]_net_1 ));
    NOR3B Cout_RNO (.A(un1_Count_2_5), .B(un1_Count_2_6), .C(Reset_c), 
        .Y(Count13));
    XA1B \Count_RNO[7]  (.A(Count_c6), .B(\Count[7]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n7));
    NOR2B \Count_RNIA98M[3]  (.A(\Count[3]_net_1 ), .B(Count_c2), .Y(
        Count_c3));
    NOR2B \Count_RNIKQV61[6]  (.A(\Count[6]_net_1 ), .B(Count_c5), .Y(
        Count_c6));
    XA1B \Count_RNO[2]  (.A(Count_c1), .B(\Count[2]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n2));
    NOR3C \Count_RNIQ9AM[7]  (.A(\Count[8]_net_1 ), .B(
        \Count[7]_net_1 ), .C(un1_Count_2_3), .Y(un1_Count_2_5));
    AX1E \Count_RNO[9]  (.A(Count_c7), .B(Count_19_0), .C(N_49), .Y(
        Count_n9));
    VCC VCC_i (.Y(VCC));
    XA1B \Count_RNO[4]  (.A(Count_c3), .B(\Count[4]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n4));
    NOR2B \Count_RNIT45B[9]  (.A(\Count[9]_net_1 ), .B(
        \Count[2]_net_1 ), .Y(un1_Count_2_0));
    NOR2B \Count_RNIJS3B[1]  (.A(\Count[1]_net_1 ), .B(
        \Count[0]_net_1 ), .Y(Count_c1));
    DFN1 \Count[8]  (.D(Count_n8), .CLK(Clk_c), .Q(\Count[8]_net_1 ));
    XA1B \Count_RNO[3]  (.A(Count_c2), .B(\Count[3]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n3));
    NOR2A \Count_RNO_0[9]  (.A(\Count[8]_net_1 ), .B(un1_Reset_1), .Y(
        Count_19_0));
    XA1B \Count_RNO[8]  (.A(Count_c7), .B(\Count[8]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n8));
    XA1B \Count_RNO[5]  (.A(Count_c4), .B(\Count[5]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n5));
    XA1B \Count_RNO[1]  (.A(\Count[1]_net_1 ), .B(\Count[0]_net_1 ), 
        .C(un1_Reset_1), .Y(Count_n1));
    DFN1 \Count[2]  (.D(Count_n2), .CLK(Clk_c), .Q(\Count[2]_net_1 ));
    NOR2B \Count_RNI4JIC1[7]  (.A(\Count[7]_net_1 ), .B(Count_c6), .Y(
        Count_c7));
    GND GND_i (.Y(GND));
    NOR2B \Count_RNIT45B[5]  (.A(\Count[5]_net_1 ), .B(
        \Count[6]_net_1 ), .Y(un1_Count_2_1));
    DFN1 \Count[9]  (.D(Count_n9), .CLK(Clk_c), .Q(\Count[9]_net_1 ));
    XA1B \Count_RNO[6]  (.A(Count_c5), .B(\Count[6]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n6));
    NOR2 \Count_RNO[0]  (.A(\Count[0]_net_1 ), .B(un1_Reset_1), .Y(
        Count_n0));
    NOR2B \Count_RNINLQR[4]  (.A(\Count[4]_net_1 ), .B(Count_c3), .Y(
        Count_c4));
    NOR2B \Count_RNIU0MG[2]  (.A(\Count[2]_net_1 ), .B(Count_c1), .Y(
        Count_c2));
    DFN1 \Count[6]  (.D(Count_n6), .CLK(Clk_c), .Q(\Count[6]_net_1 ));
    NOR2B \Count_RNI56D11[5]  (.A(\Count[5]_net_1 ), .B(Count_c4), .Y(
        Count_c5));
    DFN1 \Count[3]  (.D(Count_n3), .CLK(Clk_c), .Q(\Count[3]_net_1 ));
    DFN1 Cout (.D(Count13), .CLK(Clk_c), .Q(one_seond_clk_0_Cout));
    NOR3C \Count_RNID6E11[5]  (.A(un1_Count_2_1), .B(un1_Count_2_0), 
        .C(Count_c1), .Y(un1_Count_2_6));
    NOR2 \Count_RNIPK4B[3]  (.A(\Count[3]_net_1 ), .B(\Count[4]_net_1 )
        , .Y(un1_Count_2_3));
    OR2A \Count_RNO_1[9]  (.A(\Count[9]_net_1 ), .B(un1_Reset_1), .Y(
        N_49));
    DFN1 \Count[4]  (.D(Count_n4), .CLK(Clk_c), .Q(\Count[4]_net_1 ));
    AO1 \Count_RNICN0T1[7]  (.A(un1_Count_2_6), .B(un1_Count_2_5), .C(
        Reset_c), .Y(un1_Reset_1));
    DFN1 \Count[7]  (.D(Count_n7), .CLK(Clk_c), .Q(\Count[7]_net_1 ));
    VCC VCC_i_0 (.Y(VCC_0));
    GND GND_i_0 (.Y(GND_0));
    
endmodule
module one_seond_clk(
       Clk_c,
       one_seond_clk_0_Cout,
       Reset_c
    );

input  Clk_c;
output one_seond_clk_0_Cout;
input  Reset_c;

    wire Count_19_0, \Count[8]_net_1 , un1_Reset_1, un1_Count_2_6, 
        un1_Count_2_1, un1_Count_2_0, Count_c1, un1_Count_2_5, 
        \Count[7]_net_1 , un1_Count_2_3, \Count[3]_net_1 , 
        \Count[4]_net_1 , \Count[5]_net_1 , \Count[6]_net_1 , 
        \Count[9]_net_1 , \Count[2]_net_1 , Count_n2, Count_n3, 
        Count_c2, Count_n4, Count_c3, Count_n5, Count_c4, Count_n6, 
        Count_c5, Count_n7, Count_c6, Count_n8, Count_c7, Count13, 
        \Count[1]_net_1 , \Count[0]_net_1 , N_49, Count_n0, Count_n1, 
        Count_n9, GND, VCC, GND_0, VCC_0;
    
    DFN1 \Count[5]  (.D(Count_n5), .CLK(Clk_c), .Q(\Count[5]_net_1 ));
    DFN1 \Count[1]  (.D(Count_n1), .CLK(Clk_c), .Q(\Count[1]_net_1 ));
    DFN1 \Count[0]  (.D(Count_n0), .CLK(Clk_c), .Q(\Count[0]_net_1 ));
    NOR3B Cout_RNO (.A(un1_Count_2_5), .B(un1_Count_2_6), .C(Reset_c), 
        .Y(Count13));
    XA1B \Count_RNO[7]  (.A(Count_c6), .B(\Count[7]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n7));
    NOR2B \Count_RNIA98M[3]  (.A(\Count[3]_net_1 ), .B(Count_c2), .Y(
        Count_c3));
    NOR2B \Count_RNIKQV61[6]  (.A(\Count[6]_net_1 ), .B(Count_c5), .Y(
        Count_c6));
    XA1B \Count_RNO[2]  (.A(Count_c1), .B(\Count[2]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n2));
    NOR3C \Count_RNIQ9AM[7]  (.A(\Count[8]_net_1 ), .B(
        \Count[7]_net_1 ), .C(un1_Count_2_3), .Y(un1_Count_2_5));
    AX1E \Count_RNO[9]  (.A(Count_c7), .B(Count_19_0), .C(N_49), .Y(
        Count_n9));
    VCC VCC_i (.Y(VCC));
    XA1B \Count_RNO[4]  (.A(Count_c3), .B(\Count[4]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n4));
    NOR2B \Count_RNIT45B[9]  (.A(\Count[9]_net_1 ), .B(
        \Count[2]_net_1 ), .Y(un1_Count_2_0));
    NOR2B \Count_RNIJS3B[1]  (.A(\Count[1]_net_1 ), .B(
        \Count[0]_net_1 ), .Y(Count_c1));
    DFN1 \Count[8]  (.D(Count_n8), .CLK(Clk_c), .Q(\Count[8]_net_1 ));
    XA1B \Count_RNO[3]  (.A(Count_c2), .B(\Count[3]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n3));
    NOR2A \Count_RNO_0[9]  (.A(\Count[8]_net_1 ), .B(un1_Reset_1), .Y(
        Count_19_0));
    XA1B \Count_RNO[8]  (.A(Count_c7), .B(\Count[8]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n8));
    XA1B \Count_RNO[5]  (.A(Count_c4), .B(\Count[5]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n5));
    XA1B \Count_RNO[1]  (.A(\Count[1]_net_1 ), .B(\Count[0]_net_1 ), 
        .C(un1_Reset_1), .Y(Count_n1));
    DFN1 \Count[2]  (.D(Count_n2), .CLK(Clk_c), .Q(\Count[2]_net_1 ));
    NOR2B \Count_RNI4JIC1[7]  (.A(\Count[7]_net_1 ), .B(Count_c6), .Y(
        Count_c7));
    GND GND_i (.Y(GND));
    NOR2B \Count_RNIT45B[5]  (.A(\Count[5]_net_1 ), .B(
        \Count[6]_net_1 ), .Y(un1_Count_2_1));
    DFN1 \Count[9]  (.D(Count_n9), .CLK(Clk_c), .Q(\Count[9]_net_1 ));
    XA1B \Count_RNO[6]  (.A(Count_c5), .B(\Count[6]_net_1 ), .C(
        un1_Reset_1), .Y(Count_n6));
    NOR2 \Count_RNO[0]  (.A(\Count[0]_net_1 ), .B(un1_Reset_1), .Y(
        Count_n0));
    NOR2B \Count_RNINLQR[4]  (.A(\Count[4]_net_1 ), .B(Count_c3), .Y(
        Count_c4));
    NOR2B \Count_RNIU0MG[2]  (.A(\Count[2]_net_1 ), .B(Count_c1), .Y(
        Count_c2));
    DFN1 \Count[6]  (.D(Count_n6), .CLK(Clk_c), .Q(\Count[6]_net_1 ));
    NOR2B \Count_RNI56D11[5]  (.A(\Count[5]_net_1 ), .B(Count_c4), .Y(
        Count_c5));
    DFN1 \Count[3]  (.D(Count_n3), .CLK(Clk_c), .Q(\Count[3]_net_1 ));
    DFN1 Cout (.D(Count13), .CLK(Clk_c), .Q(one_seond_clk_0_Cout));
    NOR3C \Count_RNID6E11[5]  (.A(un1_Count_2_1), .B(un1_Count_2_0), 
        .C(Count_c1), .Y(un1_Count_2_6));
    NOR2 \Count_RNIPK4B[3]  (.A(\Count[3]_net_1 ), .B(\Count[4]_net_1 )
        , .Y(un1_Count_2_3));
    OR2A \Count_RNO_1[9]  (.A(\Count[9]_net_1 ), .B(un1_Reset_1), .Y(
        N_49));
    DFN1 \Count[4]  (.D(Count_n4), .CLK(Clk_c), .Q(\Count[4]_net_1 ));
    AO1 \Count_RNICN0T1[7]  (.A(un1_Count_2_6), .B(un1_Count_2_5), .C(
        Reset_c), .Y(un1_Reset_1));
    DFN1 \Count[7]  (.D(Count_n7), .CLK(Clk_c), .Q(\Count[7]_net_1 ));
    VCC VCC_i_0 (.Y(VCC_0));
    GND GND_i_0 (.Y(GND_0));
    
endmodule