data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v
None: at end of input
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:49: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/or1200_defines.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/or1200_defines.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/or1200_defines.v.sv\n             or1200_defines.v\n             or1200_defines.v.v\n             or1200_defines.v.sv\n             obj_dir/or1200_defines.v\n             obj_dir/or1200_defines.v.v\n             obj_dir/or1200_defines.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:73: Define or directive not defined: \'`OR1200_SR_WIDTH\'\n   input [`OR1200_SR_WIDTH-1:0] sr;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:74: Define or directive not defined: \'`OR1200_SR_WIDTH\'\n   input [`OR1200_SR_WIDTH-1:0] esr;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:100: Define or directive not defined: \'`OR1200_SR_SM\'\n .test_expr(sr[`OR1200_SR_SM] == 1\'b1),\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:100: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n .test_expr(sr[`OR1200_SR_SM] == 1\'b1),\n                            ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:118: Define or directive not defined: \'`OR1200_SR_SM\'\n .test_expr(sr[`OR1200_SR_SM] == 1\'b0),\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n .test_expr(sr[`OR1200_SR_SM] == 1\'b0),\n                            ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:158: Define or directive not defined: \'`OR1200_RST_VALUE\'\n     if(rst == `OR1200_RST_VALUE)begin\n               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:158: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     if(rst == `OR1200_RST_VALUE)begin\n                                ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:162: syntax error, unexpected else\n     else if(enable)begin\n     ^~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:197: Define or directive not defined: \'`OR1200_RST_VALUE\'\n   if(rst == `OR1200_RST_VALUE)begin\n             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:197: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   if(rst == `OR1200_RST_VALUE)begin\n                              ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:237: Define or directive not defined: \'`OR1200_SR_DSX\'\n .test_expr(sr[`OR1200_SR_DSX] == 1\'b0),\n               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:237: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n .test_expr(sr[`OR1200_SR_DSX] == 1\'b0),\n                             ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:267: Define or directive not defined: \'`OR1200_SR_DSX\'\n .test_expr(sr[`OR1200_SR_DSX] == 1\'b1),\n               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:267: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n .test_expr(sr[`OR1200_SR_DSX] == 1\'b1),\n                             ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:327: Define or directive not defined: \'`OR1200_SR_SM\'\n .sampling_event(sr[`OR1200_SR_SM]),\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:327: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n .sampling_event(sr[`OR1200_SR_SM]),\n                                 ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:337: Define or directive not defined: \'`OR1200_SR_SM\'\n .sampling_event(sr[`OR1200_SR_SM]),\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:337: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n .sampling_event(sr[`OR1200_SR_SM]),\n                                 ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:352: Define or directive not defined: \'`OR1200_OR32_RFE\'\n        .sampling_event((ex_insn & 32\'hFC000000) == {`OR1200_OR32_RFE, 26\'h0}),\n                                                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:352: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        .sampling_event((ex_insn & 32\'hFC000000) == {`OR1200_OR32_RFE, 26\'h0}),\n                                                                     ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:353: Define or directive not defined: \'`OR1200_SR_SM\'\n        .test_expr(sr[`OR1200_SR_SM] == esr[`OR1200_SR_SM]),\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:353: Define or directive not defined: \'`OR1200_SR_SM\'\n        .test_expr(sr[`OR1200_SR_SM] == esr[`OR1200_SR_SM]),\n                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:362: Define or directive not defined: \'`OR1200_OR32_MTSPR\'\n        .sampling_event((ex_insn & (32\'hFC000000 | 32\'h000007FF)) == {`OR1200_OR32_MTSPR, 15\'h0, `OR1200_SPR_SR}),\n                                                                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:362: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        .sampling_event((ex_insn & (32\'hFC000000 | 32\'h000007FF)) == {`OR1200_OR32_MTSPR, 15\'h0, `OR1200_SPR_SR}),\n                                                                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:362: Define or directive not defined: \'`OR1200_SPR_SR\'\n        .sampling_event((ex_insn & (32\'hFC000000 | 32\'h000007FF)) == {`OR1200_OR32_MTSPR, 15\'h0, `OR1200_SPR_SR}),\n                                                                                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:363: Define or directive not defined: \'`OR1200_SR_SM\'\n        .test_expr(sr[`OR1200_SR_SM] == operand_b[`OR1200_SR_SM]),\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:363: Define or directive not defined: \'`OR1200_SR_SM\'\n        .test_expr(sr[`OR1200_SR_SM] == operand_b[`OR1200_SR_SM]),\n                                                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:401: Define or directive not defined: \'`OR1200_RST_VALUE\'\n   if(rst == `OR1200_RST_VALUE)begin\n             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:401: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   if(rst == `OR1200_RST_VALUE)begin\n                              ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/BakedInAssertions.v:409: syntax error, unexpected else\n   end else if(enable) begin\n       ^~~~\n%Error: Exiting due to 32 error(s)\n'
module BakedInAssertions(
	clk, rst, enable,
	ex_pc, ex_insn, spr_dat_ppc, spr_dat_npc,
	eear, sr,esr, epcr,
	immu_sxe, immu_uxe, immu_en,	
        gpr_written_to, gpr_written_addr, gpr_written_data,
	dcpu_adr_o, dcpu_dat_i, operand_b,
	checkersFired
);
   input clk;
   input rst;
   input enable;
   input [31:0] ex_pc;
   input [31:0] ex_insn;
   input [31:0] spr_dat_ppc;
   input [31:0] spr_dat_npc;
   input [31:0] eear;
   input [`OR1200_SR_WIDTH-1:0]	sr;
   input [`OR1200_SR_WIDTH-1:0] esr;
   input [31:0] epcr;
   input 	immu_sxe;
   input 	immu_uxe;
   input 	immu_en;
   input	gpr_written_to;
   input [4:0] gpr_written_addr;
   input [31:0] gpr_written_data;
   input [31:0] dcpu_adr_o;
   input [31:0]	dcpu_dat_i;
   input [31:0] operand_b;
   output [31:0] checkersFired;



   wire      checker_1_1;
   wire      checker_1_2;
   wire      checker_1_3;
   wire      checker_1_4;
   wire      checker_1_5;
   wire      checker_1 = (checker_1_1 | checker_1_2) & (checker_1_3 | checker_1_4) & checker_1_5;
   
ovl_always_wrapped oaw_1_1(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(sr[`OR1200_SR_SM] == 1'b1),
	.prevConfigInvalid(1'b0),
	.out(checker_1_1)
);

ovl_always_wrapped oaw_1_2(
	.clk(clk),
	.rst(rst),
	.enable(enable & immu_en),
	.test_expr(immu_sxe == 1'b1),
	.prevConfigInvalid(1'b0),
	.out(checker_1_2)
);

ovl_always_wrapped oaw_1_3(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(sr[`OR1200_SR_SM] == 1'b0),
	.prevConfigInvalid(1'b0),
	.out(checker_1_3)
);

ovl_always_wrapped oaw_1_4(
	.clk(clk),
	.rst(rst),
	.enable(enable & immu_en),
	.test_expr(immu_uxe == 1'b1),
	.prevConfigInvalid(1'b0),
	.out(checker_1_4)
);

ovl_always_wrapped oaw_1_5(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(immu_en == 1'b0),
	.prevConfigInvalid(1'b0),
	.out(checker_1_5)
);


   wire      checker_3_1;
   wire      checker_3_2;
   wire      checker_3_3a;
   wire      checker_3_3b;
   reg 	     checker_3_3b_1;
   wire      checker_3_3c;
   wire      checker_3_4;
   wire      checker_3_5;
   wire      checker_3_5b;
   wire      checker_3_6;
   wire      checker_3_7;
   wire      checker_3 = checker_3_1 | checker_3_2 | (checker_3_3a & checker_3_3b_1 & checker_3_3c) | ((checker_3_4 | (checker_3_5 & checker_3_5b)) & (checker_3_6 | checker_3_7));

   reg [31:0] checker_3_counter;
   reg [31:0] insn_counter;
   always @(posedge clk)begin
     if(rst == `OR1200_RST_VALUE)begin
	insn_counter <= 32'h0;
	checker_3_counter <= 32'h0;
     end   
     else if(enable)begin
	insn_counter <= insn_counter + 1'h1;
	checker_3_counter <= checker_3 ? checker_3_counter + 1'h1 : checker_3_counter;
     end
   end
   





ovl_always_on_edge_wrapped oaoew3_1(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event(ex_pc == 32'h00000A00),
	.test_expr(eear == spr_dat_npc),
	.prevConfigInvalid(1'b0),
	.out(checker_3_1)
);


assign checker_3_2 = 0;   


always @(posedge clk)begin
   if(rst == `OR1200_RST_VALUE)begin
      checker_3_3b_1 <= 1'b0;
   end else begin
      checker_3_3b_1 <= checker_3_3b;
   end
end

ovl_always_on_edge_wrapped oaoew3_3a(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.test_expr(1'b0),
	.prevConfigInvalid(1'b0),
	.out(checker_3_3a)
);

ovl_always_wrapped oaw3_3b(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(sr[0] == 1'b1),
	.prevConfigInvalid(1'b0),
	.out(checker_3_3b)
);

ovl_always_wrapped oaw3_3c(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(esr[0] == 1'b0),
	.prevConfigInvalid(1'b0),
	.out(checker_3_3c)
);


ovl_always_wrapped oaw_3_4(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(sr[`OR1200_SR_DSX] == 1'b0),
	.prevConfigInvalid(1'b0),
        .out(checker_3_4)
);


ovl_always_on_edge_wrapped oaoew3_5(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.test_expr(epcr == spr_dat_ppc+32'h4),
	.prevConfigInvalid(1'b0),
	.out(checker_3_5)
);

ovl_always_on_edge_wrapped oaoew3_5b(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event(ex_pc == 32'h00000A00),
	.test_expr(epcr == spr_dat_npc),
	.prevConfigInvalid(1'b0),
	.out(checker_3_5b)
);

ovl_always_wrapped oaw_3_6(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(sr[`OR1200_SR_DSX] == 1'b1),
	.prevConfigInvalid(1'b0),
	.out(checker_3_6)
);


ovl_always_on_edge_wrapped oaoew3_7(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.test_expr(epcr == spr_dat_ppc),
	.prevConfigInvalid(1'b0),
	.out(checker_3_7)
);


wire checker_5_1;
wire checker_5_2;
reg [31:0] spec_xor_reg;
wire [31:0] spec_xor_comb = gpr_written_data ^ dcpu_dat_i;
wire spec_xor_comb_one = |spec_xor_comb;
wire spec_xor_reg_one = |spec_xor_reg;
wire spec_xor_small = spec_xor_reg_one & spec_xor_comb_one;
wire checker_5 = checker_5_1 & checker_5_2;

always @(posedge clk)begin
   spec_xor_reg <= gpr_written_data ^ dcpu_dat_i;
end


ovl_always_on_edge_wrapped oaoew5_1(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event((ex_insn & 32'hF0000000) == 32'h80000000),
	.test_expr(~spec_xor_small),
	.prevConfigInvalid(1'b0),
	.out(checker_5_1)
);


ovl_always_wrapped oaw5_2(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h8C000000),
	.prevConfigInvalid(1'b0),
	.out(checker_5_2)
);


   wire      checker_8_1;
   wire      checker_8_2;
   wire      checker_8 = checker_8_1 & checker_8_2;

ovl_always_on_edge_wrapped oaoew8_1(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event(sr[`OR1200_SR_SM]),
	.test_expr(rst != 0),
	.prevConfigInvalid(1'b0),
	.out(checker_8_1)
);

ovl_always_on_edge_wrapped oaoew8_2(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event(sr[`OR1200_SR_SM]),
	.test_expr((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.prevConfigInvalid(1'b0),
	.out(checker_8_2)
);


   wire      checker_9_1;
   wire      checker_9_2;
   wire      checker_9 = checker_9_1 | checker_9_2;      

ovl_always_on_edge_wrapped oaoew9_1(
        .clk(clk),
        .rst(rst),
	.enable(enable),
        .sampling_event((ex_insn & `OR1200_OPCODE_MASK) == {`OR1200_OR32_RFE, 26'h0}),
        .test_expr(sr[`OR1200_SR_SM] == esr[`OR1200_SR_SM]),
        .prevConfigInvalid(1'b0),
        .out(checker_9_1)
);
   
ovl_always_on_edge_wrapped oaoew9_2(
        .clk(clk),
        .rst(rst),
	.enable(enable),
        .sampling_event((ex_insn & (`OR1200_OPCODE_MASK | `OR1200_K_MASK)) == {`OR1200_OR32_MTSPR, 15'h0, `OR1200_SPR_SR}),
        .test_expr(sr[`OR1200_SR_SM] == operand_b[`OR1200_SR_SM]),
        .prevConfigInvalid(1'b0),
        .out(checker_9_2)
);


  wire checker_13_1;
  wire checker_13_2;
  reg checker_13_2_1;
  reg checker_13_2_2;
  wire checker_13_3;
  reg checker_13_3_1;
  reg checker_13_3_2;
  wire checker_13_4;
  reg checker_13_4_1;
  reg checker_13_4_2;
  wire checker_13_5;
  reg checker_13_5_1;
  wire checker_13_6;
  wire checker_13 = checker_13_1 & checker_13_2_1 & checker_13_3_1 & checker_13_4_1 & checker_13_5 & checker_13_6;
   

ovl_delta_wrapped #(
  .width(32),
  .limit_width(4)
) odw_13_1(
        .clk(clk & enable),
        .rst(rst),
        .min(4'd0),
        .max(4'd4),
        .test_expr(ex_pc),
        .prevConfigInvalid(1'b0),
        .out(checker_13_1)
);



always @(posedge clk)begin
   if(rst == `OR1200_RST_VALUE)begin
      checker_13_2_1 <= 1'b0;
      checker_13_2_2 <= 1'b0;
      checker_13_3_1 <= 1'b0;
      checker_13_3_2 <= 1'b0;
      checker_13_4_1 <= 1'b0;
      checker_13_4_2 <= 1'b0;
      checker_13_5_1 <= 1'b0;
   end else if(enable) begin
      checker_13_2_1 <= checker_13_2;
      checker_13_2_2 <= checker_13_2_1;
      checker_13_3_1 <= checker_13_3;
      checker_13_3_2 <= checker_13_3_1;
      checker_13_4_1 <= checker_13_4;
      checker_13_4_2 <= checker_13_4_1;
      checker_13_5_1 <= checker_13_5;
   end
end
   
   

ovl_always_wrapped oaw_13_2(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(ex_insn[31:28] == 4'h0),
	.prevConfigInvalid(1'b0),
	.out(checker_13_2)
);


ovl_always_wrapped oaw_13_3(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(ex_insn[31:28] == 4'h4),
	.prevConfigInvalid(1'b0),
	.out(checker_13_3)
);


ovl_always_wrapped oaw_13_4(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(ex_insn[31:26] == 6'h04),
	.prevConfigInvalid(1'b0),
	.out(checker_13_4)
);


ovl_always_wrapped oaw_13_5(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(ex_insn[31:26] == 6'h09),
	.prevConfigInvalid(1'b0),
	.out(checker_13_5)
);



ovl_proposition_wrapped opw_13_6(
	.rst(rst),
	.enable(enable),
	.test_expr((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.prevConfigInvalid(1'b0),
	.out(checker_13_6)
);


wire checker_15_1;
wire checker_15_2;
wire checker_15_3;
wire checker_15 = checker_15_1 | (checker_15_2 & checker_15_3);

ovl_always_on_edge_wrapped oaoew15_1(
        .clk(clk),
        .rst(rst),
	.enable(enable),
        .sampling_event((ex_insn & `OR1200_OPCODE_MASK) == 32'h24000000),
        .test_expr(sr == esr),
        .prevConfigInvalid(1'b0),
        .out(checker_15_1)
);


ovl_next_wrapped onw15_2(
        .clk(clk),
        .rst(rst),
	.enable(enable),
	.num_cks(3'd1),
        .start_event((ex_insn & `OR1200_OPCODE_MASK) == 32'h24000000),
        .test_expr(ex_pc == epcr),
        .prevConfigInvalid(1'b0),
        .out(checker_15_2)
);

ovl_always_wrapped oaw15_3(
        .clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.prevConfigInvalid(1'b0),
	.out(checker_15_3)
);


wire checker_16_1;
wire checker_16_2;
wire checker_16_3;
wire checker_16_4;
wire checker_16_5;
wire checker_16_6;
wire checker_16_7;
wire checker_16 = ((checker_16_1 & checker_16_2 & checker_16_3) | checker_16_4) & (checker_16_5 | (checker_16_6 & checker_16_7));
   

ovl_always_on_edge_wrapped oaoew16_1(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .sampling_event(gpr_written_to),
        .test_expr((ex_insn & 32'hC0000000) == 32'h80000000),
        .prevConfigInvalid(1'b0),
        .out(checker_16_1)
);

ovl_always_on_edge_wrapped oaoew16_2(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .sampling_event(gpr_written_to),
        .test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h18000000),
        .prevConfigInvalid(1'b0),
        .out(checker_16_2)
);

ovl_always_on_edge_wrapped oaoew16_3(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .sampling_event(gpr_written_to),
        .test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'hE0000000),
        .prevConfigInvalid(1'b0),
        .out(checker_16_3)
);
   


ovl_always_on_edge_wrapped oaoew16_4(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .sampling_event(gpr_written_to),
        .test_expr((ex_insn & `OR1200_TARGET_MASK) == {6'h0, gpr_written_addr, 21'h0}),
        .prevConfigInvalid(1'b0),
        .out(checker_16_4)
);


ovl_always_on_edge_wrapped oaoew16_5(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .sampling_event(gpr_written_to),
        .test_expr(gpr_written_addr == 5'h9),
        .prevConfigInvalid(1'b0),
        .out(checker_16_5)
);

ovl_always_wrapped oaw16_6(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h04000000),
        .prevConfigInvalid(1'b0),
        .out(checker_16_6)
);

ovl_always_wrapped oaw16_7(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h48000000),
        .prevConfigInvalid(1'b0),
        .out(checker_16_7)
);


   wire checker_18_1;
   wire checker_18_2;
   wire checker_18 = checker_18_1 | checker_18_2;

   ovl_next_wrapped onw18_1(
        .clk(clk),
        .rst(rst),
	.enable(enable),
	.num_cks(3'd1),
        .start_event((ex_insn & 32'hFFFF0000) == 32'h20000000),
        .test_expr(ex_pc == 32'h00000C00),
        .prevConfigInvalid(1'b0),
        .out(checker_18_1)
   );

   ovl_next_wrapped onw18_2(
        .clk(clk),
        .rst(rst),
	.enable(enable),
	.num_cks(3'd1),
        .start_event((ex_insn & 32'hFFFF0000) == 32'h21000000),
        .test_expr(ex_pc == 32'h00000E00),
        .prevConfigInvalid(1'b0),
        .out(checker_18_2)
   );


   wire checker_19 = checker_3 & checker_13_1;

   assign checkersFired = {12'b0, checker_19, checker_18, 1'b0, checker_16, checker_15, 1'b0, checker_13, 3'b0, checker_9, checker_8, 2'b0, checker_5, 1'b0, checker_3, 1'b0, checker_1, 1'b0};

   reg [31:0] checkersFired_reg;
   always @(posedge clk)
     checkersFired_reg <= checkersFired;

endmodule
module BakedInAssertions(
	clk, rst, enable,
	ex_pc, ex_insn, spr_dat_ppc, spr_dat_npc,
	eear, sr,esr, epcr,
	immu_sxe, immu_uxe, immu_en,	
        gpr_written_to, gpr_written_addr, gpr_written_data,
	dcpu_adr_o, dcpu_dat_i, operand_b,
	checkersFired
);

   input clk;
   input rst;
   input enable;
   input [31:0] ex_pc;
   input [31:0] ex_insn;
   input [31:0] spr_dat_ppc;
   input [31:0] spr_dat_npc;
   input [31:0] eear;
   input [`OR1200_SR_WIDTH-1:0]	sr;
   input [`OR1200_SR_WIDTH-1:0] esr;
   input [31:0] epcr;
   input 	immu_sxe;
   input 	immu_uxe;
   input 	immu_en;
   input	gpr_written_to;
   input [4:0] gpr_written_addr;
   input [31:0] gpr_written_data;
   input [31:0] dcpu_adr_o;
   input [31:0]	dcpu_dat_i;
   input [31:0] operand_b;
   output [31:0] checkersFired;



   wire      checker_1_1;
   wire      checker_1_2;
   wire      checker_1_3;
   wire      checker_1_4;
   wire      checker_1_5;
   wire      checker_1 = (checker_1_1 | checker_1_2) & (checker_1_3 | checker_1_4) & checker_1_5;
   
ovl_always_wrapped oaw_1_1(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(sr[`OR1200_SR_SM] == 1'b1),
	.prevConfigInvalid(1'b0),
	.out(checker_1_1)
);

ovl_always_wrapped oaw_1_2(
	.clk(clk),
	.rst(rst),
	.enable(enable & immu_en),
	.test_expr(immu_sxe == 1'b1),
	.prevConfigInvalid(1'b0),
	.out(checker_1_2)
);

ovl_always_wrapped oaw_1_3(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(sr[`OR1200_SR_SM] == 1'b0),
	.prevConfigInvalid(1'b0),
	.out(checker_1_3)
);

ovl_always_wrapped oaw_1_4(
	.clk(clk),
	.rst(rst),
	.enable(enable & immu_en),
	.test_expr(immu_uxe == 1'b1),
	.prevConfigInvalid(1'b0),
	.out(checker_1_4)
);

ovl_always_wrapped oaw_1_5(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(immu_en == 1'b0),
	.prevConfigInvalid(1'b0),
	.out(checker_1_5)
);


   wire      checker_3_1;
   wire      checker_3_2;
   wire      checker_3_3a;
   wire      checker_3_3b;
   reg 	     checker_3_3b_1;
   wire      checker_3_3c;
   wire      checker_3_4;
   wire      checker_3_5;
   wire      checker_3_5b;
   wire      checker_3_6;
   wire      checker_3_7;
   wire      checker_3 = checker_3_1 | checker_3_2 | (checker_3_3a & checker_3_3b_1 & checker_3_3c) | ((checker_3_4 | (checker_3_5 & checker_3_5b)) & (checker_3_6 | checker_3_7));

   reg [31:0] checker_3_counter;
   reg [31:0] insn_counter;
   always @(posedge clk)begin
     if(rst == `OR1200_RST_VALUE)begin
	insn_counter <= 32'h0;
	checker_3_counter <= 32'h0;
     end   
     else if(enable)begin
	insn_counter <= insn_counter + 1'h1;
	checker_3_counter <= checker_3 ? checker_3_counter + 1'h1 : checker_3_counter;
     end
   end
   





ovl_always_on_edge_wrapped oaoew3_1(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event(ex_pc == 32'h00000A00),
	.test_expr(eear == spr_dat_npc),
	.prevConfigInvalid(1'b0),
	.out(checker_3_1)
);


assign checker_3_2 = 0;   


always @(posedge clk)begin
   if(rst == `OR1200_RST_VALUE)begin
      checker_3_3b_1 <= 1'b0;
   end else begin
      checker_3_3b_1 <= checker_3_3b;
   end
end

ovl_always_on_edge_wrapped oaoew3_3a(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.test_expr(1'b0),
	.prevConfigInvalid(1'b0),
	.out(checker_3_3a)
);

ovl_always_wrapped oaw3_3b(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(sr[0] == 1'b1),
	.prevConfigInvalid(1'b0),
	.out(checker_3_3b)
);

ovl_always_wrapped oaw3_3c(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(esr[0] == 1'b0),
	.prevConfigInvalid(1'b0),
	.out(checker_3_3c)
);


ovl_always_wrapped oaw_3_4(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(sr[`OR1200_SR_DSX] == 1'b0),
	.prevConfigInvalid(1'b0),
        .out(checker_3_4)
);


ovl_always_on_edge_wrapped oaoew3_5(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.test_expr(epcr == spr_dat_ppc+32'h4),
	.prevConfigInvalid(1'b0),
	.out(checker_3_5)
);

ovl_always_on_edge_wrapped oaoew3_5b(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event(ex_pc == 32'h00000A00),
	.test_expr(epcr == spr_dat_npc),
	.prevConfigInvalid(1'b0),
	.out(checker_3_5b)
);

ovl_always_wrapped oaw_3_6(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(sr[`OR1200_SR_DSX] == 1'b1),
	.prevConfigInvalid(1'b0),
	.out(checker_3_6)
);


ovl_always_on_edge_wrapped oaoew3_7(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.test_expr(epcr == spr_dat_ppc),
	.prevConfigInvalid(1'b0),
	.out(checker_3_7)
);


wire checker_5_1;
wire checker_5_2;
reg [31:0] spec_xor_reg;
wire [31:0] spec_xor_comb = gpr_written_data ^ dcpu_dat_i;
wire spec_xor_comb_one = |spec_xor_comb;
wire spec_xor_reg_one = |spec_xor_reg;
wire spec_xor_small = spec_xor_reg_one & spec_xor_comb_one;
wire checker_5 = checker_5_1 & checker_5_2;

always @(posedge clk)begin
   spec_xor_reg <= gpr_written_data ^ dcpu_dat_i;
end


ovl_always_on_edge_wrapped oaoew5_1(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event((ex_insn & 32'hF0000000) == 32'h80000000),
	.test_expr(~spec_xor_small),
	.prevConfigInvalid(1'b0),
	.out(checker_5_1)
);


ovl_always_wrapped oaw5_2(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h8C000000),
	.prevConfigInvalid(1'b0),
	.out(checker_5_2)
);


   wire      checker_8_1;
   wire      checker_8_2;
   wire      checker_8 = checker_8_1 & checker_8_2;

ovl_always_on_edge_wrapped oaoew8_1(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event(sr[`OR1200_SR_SM]),
	.test_expr(rst != 0),
	.prevConfigInvalid(1'b0),
	.out(checker_8_1)
);

ovl_always_on_edge_wrapped oaoew8_2(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.sampling_event(sr[`OR1200_SR_SM]),
	.test_expr((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.prevConfigInvalid(1'b0),
	.out(checker_8_2)
);


   wire      checker_9_1;
   wire      checker_9_2;
   wire      checker_9 = checker_9_1 | checker_9_2;      

ovl_always_on_edge_wrapped oaoew9_1(
        .clk(clk),
        .rst(rst),
	.enable(enable),
        .sampling_event((ex_insn & `OR1200_OPCODE_MASK) == {`OR1200_OR32_RFE, 26'h0}),
        .test_expr(sr[`OR1200_SR_SM] == esr[`OR1200_SR_SM]),
        .prevConfigInvalid(1'b0),
        .out(checker_9_1)
);
   
ovl_always_on_edge_wrapped oaoew9_2(
        .clk(clk),
        .rst(rst),
	.enable(enable),
        .sampling_event((ex_insn & (`OR1200_OPCODE_MASK | `OR1200_K_MASK)) == {`OR1200_OR32_MTSPR, 15'h0, `OR1200_SPR_SR}),
        .test_expr(sr[`OR1200_SR_SM] == operand_b[`OR1200_SR_SM]),
        .prevConfigInvalid(1'b0),
        .out(checker_9_2)
);


  wire checker_13_1;
  wire checker_13_2;
  reg checker_13_2_1;
  reg checker_13_2_2;
  wire checker_13_3;
  reg checker_13_3_1;
  reg checker_13_3_2;
  wire checker_13_4;
  reg checker_13_4_1;
  reg checker_13_4_2;
  wire checker_13_5;
  reg checker_13_5_1;
  wire checker_13_6;
  wire checker_13 = checker_13_1 & checker_13_2_1 & checker_13_3_1 & checker_13_4_1 & checker_13_5 & checker_13_6;
   

ovl_delta_wrapped #(
  .width(32),
  .limit_width(4)
) odw_13_1(
        .clk(clk & enable),
        .rst(rst),
        .min(4'd0),
        .max(4'd4),
        .test_expr(ex_pc),
        .prevConfigInvalid(1'b0),
        .out(checker_13_1)
);



always @(posedge clk)begin
   if(rst == `OR1200_RST_VALUE)begin
      checker_13_2_1 <= 1'b0;
      checker_13_2_2 <= 1'b0;
      checker_13_3_1 <= 1'b0;
      checker_13_3_2 <= 1'b0;
      checker_13_4_1 <= 1'b0;
      checker_13_4_2 <= 1'b0;
      checker_13_5_1 <= 1'b0;
   end else if(enable) begin
      checker_13_2_1 <= checker_13_2;
      checker_13_2_2 <= checker_13_2_1;
      checker_13_3_1 <= checker_13_3;
      checker_13_3_2 <= checker_13_3_1;
      checker_13_4_1 <= checker_13_4;
      checker_13_4_2 <= checker_13_4_1;
      checker_13_5_1 <= checker_13_5;
   end
end
   
   

ovl_always_wrapped oaw_13_2(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(ex_insn[31:28] == 4'h0),
	.prevConfigInvalid(1'b0),
	.out(checker_13_2)
);


ovl_always_wrapped oaw_13_3(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(ex_insn[31:28] == 4'h4),
	.prevConfigInvalid(1'b0),
	.out(checker_13_3)
);


ovl_always_wrapped oaw_13_4(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(ex_insn[31:26] == 6'h04),
	.prevConfigInvalid(1'b0),
	.out(checker_13_4)
);


ovl_always_wrapped oaw_13_5(
	.clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr(ex_insn[31:26] == 6'h09),
	.prevConfigInvalid(1'b0),
	.out(checker_13_5)
);



ovl_proposition_wrapped opw_13_6(
	.rst(rst),
	.enable(enable),
	.test_expr((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.prevConfigInvalid(1'b0),
	.out(checker_13_6)
);


wire checker_15_1;
wire checker_15_2;
wire checker_15_3;
wire checker_15 = checker_15_1 | (checker_15_2 & checker_15_3);

ovl_always_on_edge_wrapped oaoew15_1(
        .clk(clk),
        .rst(rst),
	.enable(enable),
        .sampling_event((ex_insn & `OR1200_OPCODE_MASK) == 32'h24000000),
        .test_expr(sr == esr),
        .prevConfigInvalid(1'b0),
        .out(checker_15_1)
);


ovl_next_wrapped onw15_2(
        .clk(clk),
        .rst(rst),
	.enable(enable),
	.num_cks(3'd1),
        .start_event((ex_insn & `OR1200_OPCODE_MASK) == 32'h24000000),
        .test_expr(ex_pc == epcr),
        .prevConfigInvalid(1'b0),
        .out(checker_15_2)
);

ovl_always_wrapped oaw15_3(
        .clk(clk),
	.rst(rst),
	.enable(enable),
	.test_expr((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
	.prevConfigInvalid(1'b0),
	.out(checker_15_3)
);


wire checker_16_1;
wire checker_16_2;
wire checker_16_3;
wire checker_16_4;
wire checker_16_5;
wire checker_16_6;
wire checker_16_7;
wire checker_16 = ((checker_16_1 & checker_16_2 & checker_16_3) | checker_16_4) & (checker_16_5 | (checker_16_6 & checker_16_7));
   

ovl_always_on_edge_wrapped oaoew16_1(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .sampling_event(gpr_written_to),
        .test_expr((ex_insn & 32'hC0000000) == 32'h80000000),
        .prevConfigInvalid(1'b0),
        .out(checker_16_1)
);

ovl_always_on_edge_wrapped oaoew16_2(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .sampling_event(gpr_written_to),
        .test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h18000000),
        .prevConfigInvalid(1'b0),
        .out(checker_16_2)
);

ovl_always_on_edge_wrapped oaoew16_3(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .sampling_event(gpr_written_to),
        .test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'hE0000000),
        .prevConfigInvalid(1'b0),
        .out(checker_16_3)
);
   


ovl_always_on_edge_wrapped oaoew16_4(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .sampling_event(gpr_written_to),
        .test_expr((ex_insn & `OR1200_TARGET_MASK) == {6'h0, gpr_written_addr, 21'h0}),
        .prevConfigInvalid(1'b0),
        .out(checker_16_4)
);


ovl_always_on_edge_wrapped oaoew16_5(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .sampling_event(gpr_written_to),
        .test_expr(gpr_written_addr == 5'h9),
        .prevConfigInvalid(1'b0),
        .out(checker_16_5)
);

ovl_always_wrapped oaw16_6(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h04000000),
        .prevConfigInvalid(1'b0),
        .out(checker_16_6)
);

ovl_always_wrapped oaw16_7(
        .clk(clk),
        .rst(rst),
	.enable(1'b1),
        .test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h48000000),
        .prevConfigInvalid(1'b0),
        .out(checker_16_7)
);


   wire checker_18_1;
   wire checker_18_2;
   wire checker_18 = checker_18_1 | checker_18_2;

   ovl_next_wrapped onw18_1(
        .clk(clk),
        .rst(rst),
	.enable(enable),
	.num_cks(3'd1),
        .start_event((ex_insn & 32'hFFFF0000) == 32'h20000000),
        .test_expr(ex_pc == 32'h00000C00),
        .prevConfigInvalid(1'b0),
        .out(checker_18_1)
   );

   ovl_next_wrapped onw18_2(
        .clk(clk),
        .rst(rst),
	.enable(enable),
	.num_cks(3'd1),
        .start_event((ex_insn & 32'hFFFF0000) == 32'h21000000),
        .test_expr(ex_pc == 32'h00000E00),
        .prevConfigInvalid(1'b0),
        .out(checker_18_2)
   );


   wire checker_19 = checker_3 & checker_13_1;

   assign checkersFired = {12'b0, checker_19, checker_18, 1'b0, checker_16, checker_15, 1'b0, checker_13, 3'b0, checker_9, checker_8, 2'b0, checker_5, 1'b0, checker_3, 1'b0, checker_1, 1'b0};

   reg [31:0] checkersFired_reg;
   always @(posedge clk)
     checkersFired_reg <= checkersFired;

endmodule