data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_core.v
1: b'%Error: data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_core.v:171: Cannot find file containing module: \'sha1_w_mem\'\n  sha1_w_mem w_mem_inst(\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150152921/apps/sha1/step3/rtl,data/full_repos/permissive/150152921/sha1_w_mem\n             data/full_repos/permissive/150152921/apps/sha1/step3/rtl,data/full_repos/permissive/150152921/sha1_w_mem.v\n             data/full_repos/permissive/150152921/apps/sha1/step3/rtl,data/full_repos/permissive/150152921/sha1_w_mem.sv\n             sha1_w_mem\n             sha1_w_mem.v\n             sha1_w_mem.sv\n             obj_dir/sha1_w_mem\n             obj_dir/sha1_w_mem.v\n             obj_dir/sha1_w_mem.sv\n%Error: data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_core.v:372: Cannot find file containing module: \'regchain\'\n    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_a  (.CLK(clk), .IN(a_reg[i]),  .OUT(a_reg_hp[i])); \n    ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_core.v:373: Cannot find file containing module: \'regchain\'\n    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_b  (.CLK(clk), .IN(b_reg[i]),  .OUT(b_reg_hp[i])); \n    ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_core.v:374: Cannot find file containing module: \'regchain\'\n    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_c  (.CLK(clk), .IN(c_reg[i]),  .OUT(c_reg_hp[i])); \n    ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_core.v:375: Cannot find file containing module: \'regchain\'\n    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_d  (.CLK(clk), .IN(d_reg[i]),  .OUT(d_reg_hp[i])); \n    ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_core.v:376: Cannot find file containing module: \'regchain\'\n    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_e  (.CLK(clk), .IN(e_reg[i]),  .OUT(e_reg_hp[i])); \n    ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_core.v:377: Cannot find file containing module: \'regchain\'\n    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_ek (.CLK(clk), .IN(ek_reg[i]), .OUT(ek_reg_hp[i])); \n    ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_core.v:378: Cannot find file containing module: \'regchain\'\n    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_w  (.CLK(clk), .IN(w[i]),      .OUT(w_hp[i])); \n    ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_core.v:379: Cannot find file containing module: \'regchain\'\n    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_f  (.CLK(clk), .IN(f_reg[i]), .OUT(f_reg_hp[i])); \n    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_core.v:636: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance sha1_core\n            next_stage_cnt   = 1\'b0;\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 9 error(s), 1 warning(s)\n'
module sha1_core(
                 input wire            clk,
                 input wire            reset_n,

                 input wire            init,
                 input wire            next,

                 input wire [511 : 0]  block,

                 output wire           ready,

                 output wire [159 : 0] digest,
                 output wire           digest_valid
                );





  parameter H0_0 = 32'h67452301;
  parameter H0_1 = 32'hefcdab89;
  parameter H0_2 = 32'h98badcfe;
  parameter H0_3 = 32'h10325476;
  parameter H0_4 = 32'hc3d2e1f0;

  parameter SHA1_ROUNDS = 79; 

  parameter CTRL_IDLE   = 0;
  parameter CTRL_ROUNDS = 1;
  parameter CTRL_DONE   = 2;
  
  parameter NUM_DELAY = 10; 




  reg [31 : 0] a_reg[0:SHA1_ROUNDS];
  reg [31 : 0] a_new;
  reg [31 : 0] b_reg[0:SHA1_ROUNDS];
  reg [31 : 0] b_new;
  reg [31 : 0] c_reg[0:SHA1_ROUNDS];
  reg [31 : 0] c_new;
  reg [31 : 0] d_reg[0:SHA1_ROUNDS];
  reg [31 : 0] d_new;
  reg [31 : 0] e_reg[0:SHA1_ROUNDS];
  reg [31 : 0] e_new;
  reg          a_e_we;
  reg [31 : 0] f_reg[0:SHA1_ROUNDS];
  reg [31 : 0] ek_reg[0:SHA1_ROUNDS];
  reg [31 : 0] a_reg_final;
  reg [31 : 0] b_reg_final;
  reg [31 : 0] c_reg_final;
  reg [31 : 0] d_reg_final;
  reg [31 : 0] e_reg_final;
  reg [31 : 0] f_reg_final;
  reg [31 : 0] ek_reg_final;

  wire [31 : 0] a_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] b_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] c_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] d_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] e_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] ek_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] f_reg_hp[0:SHA1_ROUNDS];

  reg [31 : 0] H0_reg;
  reg [31 : 0] H0_new;
  reg [31 : 0] H1_reg;
  reg [31 : 0] H1_new;
  reg [31 : 0] H2_reg;
  reg [31 : 0] H2_new;
  reg [31 : 0] H3_reg;
  reg [31 : 0] H3_new;
  reg [31 : 0] H4_reg;
  reg [31 : 0] H4_new;
  reg          H_we;

  reg [6 : 0] round_ctr_reg;
  reg [6 : 0] round_ctr_new;
  reg         round_ctr_we;
  reg         round_ctr_inc;
  reg         round_ctr_rst;

  reg digest_valid_reg;
  reg digest_valid_new;
  reg digest_valid_we;

  reg [1 : 0] sha1_ctrl_reg;
  reg [1 : 0] sha1_ctrl_new;
  reg         sha1_ctrl_we;





  reg           digest_init;
  reg           digest_update;
  reg           state_init;
  reg           state_update;
  reg           first_block;
  reg           ready_flag;
  reg           w_init;
  reg           w_next;

  wire [31 : 0] w [0:SHA1_ROUNDS];
  wire [31 : 0] w_hp [0:SHA1_ROUNDS];

  wire [31 : 0] w_mem00;
  wire [31 : 0] w_mem01;
  wire [31 : 0] w_mem02;
  wire [31 : 0] w_mem03;
  wire [31 : 0] w_mem04;
  wire [31 : 0] w_mem05;
  wire [31 : 0] w_mem06;
  wire [31 : 0] w_mem07;
  wire [31 : 0] w_mem08;
  wire [31 : 0] w_mem09;
  wire [31 : 0] w_mem10;
  wire [31 : 0] w_mem11;
  wire [31 : 0] w_mem12;
  wire [31 : 0] w_mem13;
  wire [31 : 0] w_mem14;
  wire [31 : 0] w_mem15;
  wire [31 : 0] w_mem16;
  wire [31 : 0] w_mem16_dup1;
  wire [31 : 0] w_mem16_dup2;
  wire [31 : 0] w_mem16_dup3;





  sha1_w_mem w_mem_inst(
                        .clk(clk),
                        .reset_n(reset_n),

                        .block(block),

                        .init(w_init),
                        .next(w_next),

                        .w_mem00(w_mem00), 
                        .w_mem01(w_mem01), 
                        .w_mem02(w_mem02), 
                        .w_mem03(w_mem03), 
                        .w_mem04(w_mem04), 
                        .w_mem05(w_mem05), 
                        .w_mem06(w_mem06), 
                        .w_mem07(w_mem07), 
                        .w_mem08(w_mem08), 
                        .w_mem09(w_mem09), 
                        .w_mem10(w_mem10), 
                        .w_mem11(w_mem11), 
                        .w_mem12(w_mem12), 
                        .w_mem13(w_mem13), 
                        .w_mem14(w_mem14), 
                        .w_mem15(w_mem15), 
                        .w_mem16(w_mem16), 
                        .w_mem16_dup1(w_mem16_dup1), 
                        .w_mem16_dup2(w_mem16_dup2), 
                        .w_mem16_dup3(w_mem16_dup3), 

                        .w()
                       );

assign w[0] = w_mem00;
assign w[1] = w_mem01;
assign w[2] = w_mem02;
assign w[3] = w_mem03;
assign w[4] = w_mem04;
assign w[5] = w_mem05;
assign w[6] = w_mem06;
assign w[7] = w_mem07;
assign w[8] = w_mem08;
assign w[9] = w_mem09;
assign w[10] = w_mem10;
assign w[11] = w_mem11;
assign w[12] = w_mem12;
assign w[13] = w_mem13;
assign w[14] = w_mem14;
assign w[15] = w_mem15;

genvar j;
generate
  for(j=16; j<20; j=j+1) begin
    assign w[j] = w_mem16;
  end 
  for(j=20; j<40; j=j+1) begin
    assign w[j] = w_mem16_dup1;
  end 
  for(j=40; j<60; j=j+1) begin
    assign w[j] = w_mem16_dup2;
  end 
  for(j=60; j<80; j=j+1) begin
    assign w[j] = w_mem16_dup3;
  end 
endgenerate 





  assign ready        = ready_flag;
  assign digest       = {H0_reg, H1_reg, H2_reg, H3_reg, H4_reg};
  assign digest_valid = digest_valid_reg;








  always @ (posedge clk)
    begin : reg_update
      if (!reset_n)
        begin





          H0_reg           <= 32'h0;
          H1_reg           <= 32'h0;
          H2_reg           <= 32'h0;
          H3_reg           <= 32'h0;
          H4_reg           <= 32'h0;
          digest_valid_reg <= 0;
          round_ctr_reg    <= 7'b0;
          sha1_ctrl_reg    <= CTRL_IDLE;
        end
      else
        begin


          if (H_we)
            begin
              H0_reg <= H0_new;
              H1_reg <= H1_new;
              H2_reg <= H2_new;
              H3_reg <= H3_new;
              H4_reg <= H4_new;
            end

          if (round_ctr_we)
            round_ctr_reg <= round_ctr_new;

          if (digest_valid_we)
            digest_valid_reg <= digest_valid_new;

          if (sha1_ctrl_we)
            sha1_ctrl_reg <= sha1_ctrl_new;
        end
    end



  always@(posedge clk) begin
    if(state_init) begin
      if(first_block) begin
         a_reg[0] <= H0_0; 
         b_reg[0] <= H0_1; 
         c_reg[0] <= H0_2; 
         d_reg[0] <= H0_3; 
         e_reg[0] <= H0_4; 
         f_reg[0] <= (H0_1 & H0_2) ^ (~H0_1 & H0_3);
         f_reg[1] <= (H0_0 & {H0_1[1:0],H0_1[31:2]}) ^ (~H0_0 & H0_2);
         ek_reg[0] <= H0_4 + 32'h5a827999;
      end else begin
         a_reg[0] <= H0_reg; 
         b_reg[0] <= H1_reg; 
         c_reg[0] <= H2_reg; 
         d_reg[0] <= H3_reg; 
         e_reg[0] <= H4_reg; 
         f_reg[0] <= ((H1_reg & H2_reg) ^ (~H1_reg & H3_reg)); 
         f_reg[1] <= ((H0_reg & {H1_reg[1:0],H1_reg[31:2]}) ^ (~H0_reg & H2_reg)); 
         ek_reg[0] <= H4_reg + 32'h5a827999;
      end 
    end 
  end 

genvar i; 
generate
  for(i=1; i<20; i=i+1) begin
    always@(posedge clk) begin
      ek_reg[i] <= d_reg_hp[i-1] + 32'h5a827999; 

      if(i>1)
        f_reg[i] <= ((a_reg_hp[i-1] & {b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]}) ^ (~a_reg_hp[i-1] & c_reg_hp[i-1])); 
    end 
  end 
  for(i=20; i<40; i=i+1) begin
    always@(posedge clk) begin

      f_reg[i] <= a_reg_hp[i-1] ^ {b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]} ^ c_reg_hp[i-1];
      ek_reg[i] <= d_reg_hp[i-1] + 32'h6ed9eba1; 
    end 
  end 
  for(i=40; i<60; i=i+1) begin
    always@(posedge clk) begin

      f_reg[i] <= (a_reg_hp[i-1] | {b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]}) ^ 
                  (a_reg_hp[i-1] | c_reg_hp[i-1]) ^ 
                  ({b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]} | c_reg_hp[i-1]); 
      ek_reg[i] <= d_reg_hp[i-1] + 32'h8f1bbcdc; 
    end 
  end 
  for(i=60; i<80; i=i+1) begin
    always@(posedge clk) begin

      f_reg[i] <= a_reg_hp[i-1] ^ {b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]} ^ c_reg_hp[i-1];
      ek_reg[i] <= d_reg_hp[i-1] + 32'hca62c1d6; 
    end 
  end 
  for(i=1; i<80; i=i+1) begin
    always@(posedge clk) begin
      a_reg[i] <= {a_reg_hp[i-1][26:0],a_reg_hp[i-1][31:27]} + ek_reg_hp[i-1] + w_hp[i-1] + f_reg_hp[i-1];
      b_reg[i] <= a_reg_hp[i-1]; 
      c_reg[i] <= {b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]}; 
      d_reg[i] <= c_reg_hp[i-1];
      e_reg[i] <= d_reg_hp[i-1];
    end 
  end 
  for(i=0; i<80; i=i+1) begin
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_a  (.CLK(clk), .IN(a_reg[i]),  .OUT(a_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_b  (.CLK(clk), .IN(b_reg[i]),  .OUT(b_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_c  (.CLK(clk), .IN(c_reg[i]),  .OUT(c_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_d  (.CLK(clk), .IN(d_reg[i]),  .OUT(d_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_e  (.CLK(clk), .IN(e_reg[i]),  .OUT(e_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_ek (.CLK(clk), .IN(ek_reg[i]), .OUT(ek_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_w  (.CLK(clk), .IN(w[i]),      .OUT(w_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_f  (.CLK(clk), .IN(f_reg[i]), .OUT(f_reg_hp[i])); 
  end 
endgenerate

always@(posedge clk) begin
  a_reg_final <= {a_reg_hp[79][26:0],a_reg_hp[79][31:27]} + ek_reg_hp[79] + w_hp[79] + f_reg_hp[79];
  b_reg_final <= a_reg_hp[79]; 
  c_reg_final <= {b_reg_hp[79][1:0],b_reg_hp[79][31:2]}; 
  d_reg_final <= c_reg_hp[79];
  e_reg_final <= d_reg_hp[79];
end 

reg [3:0] stage_cnt0q; 
reg [3:0] next_stage_cnt; 

always@(posedge clk) begin
  if(!reset_n) 
    stage_cnt0q <= 'd0;
  else
    stage_cnt0q <= next_stage_cnt;
end 






  always @*
    begin : digest_logic
      H0_new = 32'h0;
      H1_new = 32'h0;
      H2_new = 32'h0;
      H3_new = 32'h0;
      H4_new = 32'h0;
      H_we = 0;

      if (digest_init)
        begin
          H0_new = H0_0;
          H1_new = H0_1;
          H2_new = H0_2;
          H3_new = H0_3;
          H4_new = H0_4;
          H_we = 1;
        end

      if (digest_update)
        begin
          H0_new = H0_reg + a_reg_final;
          H1_new = H1_reg + b_reg_final;
          H2_new = H2_reg + c_reg_final;
          H3_new = H3_reg + d_reg_final;
          H4_new = H4_reg + e_reg_final;
          H_we = 1;
        end
    end

















  always @*
    begin : round_ctr
      round_ctr_new = 0;
      round_ctr_we  = 0;

      if (round_ctr_rst)
        begin
          round_ctr_new = 0;
          round_ctr_we  = 1;
        end

      if (round_ctr_inc)
        begin
          round_ctr_new = round_ctr_reg + 1'b1;
          round_ctr_we  = 1;
        end
    end






  always @*
    begin : sha1_ctrl_fsm
      digest_init      = 0;
      digest_update    = 0;
      state_init       = 0;
      state_update     = 0;
      first_block      = 0;
      ready_flag       = 0;
      w_init           = 0;
      w_next           = 0;
      round_ctr_inc    = 0;
      round_ctr_rst    = 0;
      digest_valid_new = 0;
      digest_valid_we  = 0;
      sha1_ctrl_new    = CTRL_IDLE;
      sha1_ctrl_we     = 0;
      next_stage_cnt   = 0; 

      case (sha1_ctrl_reg)
        CTRL_IDLE:
          begin
            ready_flag = 1;

            if (init)
              begin
                digest_init      = 1;
                w_init           = 1;
                state_init       = 1;
                first_block      = 1;
                round_ctr_rst    = 1;
                digest_valid_new = 0;
                digest_valid_we  = 1;
                sha1_ctrl_new    = CTRL_ROUNDS;
                sha1_ctrl_we     = 1;
                next_stage_cnt   = 0; 
              end

            if (next)
              begin
                w_init           = 1;
                state_init       = 1;
                round_ctr_rst    = 1;
                digest_valid_new = 0;
                digest_valid_we  = 1;
                sha1_ctrl_new    = CTRL_ROUNDS;
                sha1_ctrl_we     = 1;
                next_stage_cnt   = 0; 
              end
          end


        CTRL_ROUNDS:
          begin
            state_update  = 1;




            if(stage_cnt0q == NUM_DELAY) begin
              round_ctr_inc = 1;
              w_next        = 1;
               next_stage_cnt= 'd0;
            end 
            else 
              next_stage_cnt= stage_cnt0q + 1'b1; 

            if (round_ctr_reg == SHA1_ROUNDS)
              begin
                if(stage_cnt0q == NUM_DELAY) begin
                  sha1_ctrl_new = CTRL_DONE;
                  sha1_ctrl_we  = 1;
                end 
              end
          end


        CTRL_DONE:
          begin
            digest_update    = 1;
            digest_valid_new = 1;
            digest_valid_we  = 1;
            sha1_ctrl_new    = CTRL_IDLE;
            sha1_ctrl_we     = 1;
            next_stage_cnt   = 1'b0;
          end
      endcase
    end

endmodule
module sha1_core(
                 input wire            clk,
                 input wire            reset_n,

                 input wire            init,
                 input wire            next,

                 input wire [511 : 0]  block,

                 output wire           ready,

                 output wire [159 : 0] digest,
                 output wire           digest_valid
                );






  parameter H0_0 = 32'h67452301;
  parameter H0_1 = 32'hefcdab89;
  parameter H0_2 = 32'h98badcfe;
  parameter H0_3 = 32'h10325476;
  parameter H0_4 = 32'hc3d2e1f0;

  parameter SHA1_ROUNDS = 79; 

  parameter CTRL_IDLE   = 0;
  parameter CTRL_ROUNDS = 1;
  parameter CTRL_DONE   = 2;
  
  parameter NUM_DELAY = 10; 




  reg [31 : 0] a_reg[0:SHA1_ROUNDS];
  reg [31 : 0] a_new;
  reg [31 : 0] b_reg[0:SHA1_ROUNDS];
  reg [31 : 0] b_new;
  reg [31 : 0] c_reg[0:SHA1_ROUNDS];
  reg [31 : 0] c_new;
  reg [31 : 0] d_reg[0:SHA1_ROUNDS];
  reg [31 : 0] d_new;
  reg [31 : 0] e_reg[0:SHA1_ROUNDS];
  reg [31 : 0] e_new;
  reg          a_e_we;
  reg [31 : 0] f_reg[0:SHA1_ROUNDS];
  reg [31 : 0] ek_reg[0:SHA1_ROUNDS];
  reg [31 : 0] a_reg_final;
  reg [31 : 0] b_reg_final;
  reg [31 : 0] c_reg_final;
  reg [31 : 0] d_reg_final;
  reg [31 : 0] e_reg_final;
  reg [31 : 0] f_reg_final;
  reg [31 : 0] ek_reg_final;

  wire [31 : 0] a_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] b_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] c_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] d_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] e_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] ek_reg_hp[0:SHA1_ROUNDS];
  wire [31 : 0] f_reg_hp[0:SHA1_ROUNDS];

  reg [31 : 0] H0_reg;
  reg [31 : 0] H0_new;
  reg [31 : 0] H1_reg;
  reg [31 : 0] H1_new;
  reg [31 : 0] H2_reg;
  reg [31 : 0] H2_new;
  reg [31 : 0] H3_reg;
  reg [31 : 0] H3_new;
  reg [31 : 0] H4_reg;
  reg [31 : 0] H4_new;
  reg          H_we;

  reg [6 : 0] round_ctr_reg;
  reg [6 : 0] round_ctr_new;
  reg         round_ctr_we;
  reg         round_ctr_inc;
  reg         round_ctr_rst;

  reg digest_valid_reg;
  reg digest_valid_new;
  reg digest_valid_we;

  reg [1 : 0] sha1_ctrl_reg;
  reg [1 : 0] sha1_ctrl_new;
  reg         sha1_ctrl_we;





  reg           digest_init;
  reg           digest_update;
  reg           state_init;
  reg           state_update;
  reg           first_block;
  reg           ready_flag;
  reg           w_init;
  reg           w_next;

  wire [31 : 0] w [0:SHA1_ROUNDS];
  wire [31 : 0] w_hp [0:SHA1_ROUNDS];

  wire [31 : 0] w_mem00;
  wire [31 : 0] w_mem01;
  wire [31 : 0] w_mem02;
  wire [31 : 0] w_mem03;
  wire [31 : 0] w_mem04;
  wire [31 : 0] w_mem05;
  wire [31 : 0] w_mem06;
  wire [31 : 0] w_mem07;
  wire [31 : 0] w_mem08;
  wire [31 : 0] w_mem09;
  wire [31 : 0] w_mem10;
  wire [31 : 0] w_mem11;
  wire [31 : 0] w_mem12;
  wire [31 : 0] w_mem13;
  wire [31 : 0] w_mem14;
  wire [31 : 0] w_mem15;
  wire [31 : 0] w_mem16;
  wire [31 : 0] w_mem16_dup1;
  wire [31 : 0] w_mem16_dup2;
  wire [31 : 0] w_mem16_dup3;





  sha1_w_mem w_mem_inst(
                        .clk(clk),
                        .reset_n(reset_n),

                        .block(block),

                        .init(w_init),
                        .next(w_next),

                        .w_mem00(w_mem00), 
                        .w_mem01(w_mem01), 
                        .w_mem02(w_mem02), 
                        .w_mem03(w_mem03), 
                        .w_mem04(w_mem04), 
                        .w_mem05(w_mem05), 
                        .w_mem06(w_mem06), 
                        .w_mem07(w_mem07), 
                        .w_mem08(w_mem08), 
                        .w_mem09(w_mem09), 
                        .w_mem10(w_mem10), 
                        .w_mem11(w_mem11), 
                        .w_mem12(w_mem12), 
                        .w_mem13(w_mem13), 
                        .w_mem14(w_mem14), 
                        .w_mem15(w_mem15), 
                        .w_mem16(w_mem16), 
                        .w_mem16_dup1(w_mem16_dup1), 
                        .w_mem16_dup2(w_mem16_dup2), 
                        .w_mem16_dup3(w_mem16_dup3), 

                        .w()
                       );

assign w[0] = w_mem00;
assign w[1] = w_mem01;
assign w[2] = w_mem02;
assign w[3] = w_mem03;
assign w[4] = w_mem04;
assign w[5] = w_mem05;
assign w[6] = w_mem06;
assign w[7] = w_mem07;
assign w[8] = w_mem08;
assign w[9] = w_mem09;
assign w[10] = w_mem10;
assign w[11] = w_mem11;
assign w[12] = w_mem12;
assign w[13] = w_mem13;
assign w[14] = w_mem14;
assign w[15] = w_mem15;

genvar j;
generate
  for(j=16; j<20; j=j+1) begin
    assign w[j] = w_mem16;
  end 
  for(j=20; j<40; j=j+1) begin
    assign w[j] = w_mem16_dup1;
  end 
  for(j=40; j<60; j=j+1) begin
    assign w[j] = w_mem16_dup2;
  end 
  for(j=60; j<80; j=j+1) begin
    assign w[j] = w_mem16_dup3;
  end 
endgenerate 





  assign ready        = ready_flag;
  assign digest       = {H0_reg, H1_reg, H2_reg, H3_reg, H4_reg};
  assign digest_valid = digest_valid_reg;








  always @ (posedge clk)
    begin : reg_update
      if (!reset_n)
        begin





          H0_reg           <= 32'h0;
          H1_reg           <= 32'h0;
          H2_reg           <= 32'h0;
          H3_reg           <= 32'h0;
          H4_reg           <= 32'h0;
          digest_valid_reg <= 0;
          round_ctr_reg    <= 7'b0;
          sha1_ctrl_reg    <= CTRL_IDLE;
        end
      else
        begin


          if (H_we)
            begin
              H0_reg <= H0_new;
              H1_reg <= H1_new;
              H2_reg <= H2_new;
              H3_reg <= H3_new;
              H4_reg <= H4_new;
            end

          if (round_ctr_we)
            round_ctr_reg <= round_ctr_new;

          if (digest_valid_we)
            digest_valid_reg <= digest_valid_new;

          if (sha1_ctrl_we)
            sha1_ctrl_reg <= sha1_ctrl_new;
        end
    end



  always@(posedge clk) begin
    if(state_init) begin
      if(first_block) begin
         a_reg[0] <= H0_0; 
         b_reg[0] <= H0_1; 
         c_reg[0] <= H0_2; 
         d_reg[0] <= H0_3; 
         e_reg[0] <= H0_4; 
         f_reg[0] <= (H0_1 & H0_2) ^ (~H0_1 & H0_3);
         f_reg[1] <= (H0_0 & {H0_1[1:0],H0_1[31:2]}) ^ (~H0_0 & H0_2);
         ek_reg[0] <= H0_4 + 32'h5a827999;
      end else begin
         a_reg[0] <= H0_reg; 
         b_reg[0] <= H1_reg; 
         c_reg[0] <= H2_reg; 
         d_reg[0] <= H3_reg; 
         e_reg[0] <= H4_reg; 
         f_reg[0] <= ((H1_reg & H2_reg) ^ (~H1_reg & H3_reg)); 
         f_reg[1] <= ((H0_reg & {H1_reg[1:0],H1_reg[31:2]}) ^ (~H0_reg & H2_reg)); 
         ek_reg[0] <= H4_reg + 32'h5a827999;
      end 
    end 
  end 

genvar i; 
generate
  for(i=1; i<20; i=i+1) begin
    always@(posedge clk) begin
      ek_reg[i] <= d_reg_hp[i-1] + 32'h5a827999; 

      if(i>1)
        f_reg[i] <= ((a_reg_hp[i-1] & {b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]}) ^ (~a_reg_hp[i-1] & c_reg_hp[i-1])); 
    end 
  end 
  for(i=20; i<40; i=i+1) begin
    always@(posedge clk) begin

      f_reg[i] <= a_reg_hp[i-1] ^ {b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]} ^ c_reg_hp[i-1];
      ek_reg[i] <= d_reg_hp[i-1] + 32'h6ed9eba1; 
    end 
  end 
  for(i=40; i<60; i=i+1) begin
    always@(posedge clk) begin

      f_reg[i] <= (a_reg_hp[i-1] | {b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]}) ^ 
                  (a_reg_hp[i-1] | c_reg_hp[i-1]) ^ 
                  ({b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]} | c_reg_hp[i-1]); 
      ek_reg[i] <= d_reg_hp[i-1] + 32'h8f1bbcdc; 
    end 
  end 
  for(i=60; i<80; i=i+1) begin
    always@(posedge clk) begin

      f_reg[i] <= a_reg_hp[i-1] ^ {b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]} ^ c_reg_hp[i-1];
      ek_reg[i] <= d_reg_hp[i-1] + 32'hca62c1d6; 
    end 
  end 
  for(i=1; i<80; i=i+1) begin
    always@(posedge clk) begin
      a_reg[i] <= {a_reg_hp[i-1][26:0],a_reg_hp[i-1][31:27]} + ek_reg_hp[i-1] + w_hp[i-1] + f_reg_hp[i-1];
      b_reg[i] <= a_reg_hp[i-1]; 
      c_reg[i] <= {b_reg_hp[i-1][1:0],b_reg_hp[i-1][31:2]}; 
      d_reg[i] <= c_reg_hp[i-1];
      e_reg[i] <= d_reg_hp[i-1];
    end 
  end 
  for(i=0; i<80; i=i+1) begin
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_a  (.CLK(clk), .IN(a_reg[i]),  .OUT(a_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_b  (.CLK(clk), .IN(b_reg[i]),  .OUT(b_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_c  (.CLK(clk), .IN(c_reg[i]),  .OUT(c_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_d  (.CLK(clk), .IN(d_reg[i]),  .OUT(d_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_e  (.CLK(clk), .IN(e_reg[i]),  .OUT(e_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_ek (.CLK(clk), .IN(ek_reg[i]), .OUT(ek_reg_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_w  (.CLK(clk), .IN(w[i]),      .OUT(w_hp[i])); 
    regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_f  (.CLK(clk), .IN(f_reg[i]), .OUT(f_reg_hp[i])); 
  end 
endgenerate

always@(posedge clk) begin
  a_reg_final <= {a_reg_hp[79][26:0],a_reg_hp[79][31:27]} + ek_reg_hp[79] + w_hp[79] + f_reg_hp[79];
  b_reg_final <= a_reg_hp[79]; 
  c_reg_final <= {b_reg_hp[79][1:0],b_reg_hp[79][31:2]}; 
  d_reg_final <= c_reg_hp[79];
  e_reg_final <= d_reg_hp[79];
end 

reg [3:0] stage_cnt0q; 
reg [3:0] next_stage_cnt; 

always@(posedge clk) begin
  if(!reset_n) 
    stage_cnt0q <= 'd0;
  else
    stage_cnt0q <= next_stage_cnt;
end 






  always @*
    begin : digest_logic
      H0_new = 32'h0;
      H1_new = 32'h0;
      H2_new = 32'h0;
      H3_new = 32'h0;
      H4_new = 32'h0;
      H_we = 0;

      if (digest_init)
        begin
          H0_new = H0_0;
          H1_new = H0_1;
          H2_new = H0_2;
          H3_new = H0_3;
          H4_new = H0_4;
          H_we = 1;
        end

      if (digest_update)
        begin
          H0_new = H0_reg + a_reg_final;
          H1_new = H1_reg + b_reg_final;
          H2_new = H2_reg + c_reg_final;
          H3_new = H3_reg + d_reg_final;
          H4_new = H4_reg + e_reg_final;
          H_we = 1;
        end
    end

















  always @*
    begin : round_ctr
      round_ctr_new = 0;
      round_ctr_we  = 0;

      if (round_ctr_rst)
        begin
          round_ctr_new = 0;
          round_ctr_we  = 1;
        end

      if (round_ctr_inc)
        begin
          round_ctr_new = round_ctr_reg + 1'b1;
          round_ctr_we  = 1;
        end
    end






  always @*
    begin : sha1_ctrl_fsm
      digest_init      = 0;
      digest_update    = 0;
      state_init       = 0;
      state_update     = 0;
      first_block      = 0;
      ready_flag       = 0;
      w_init           = 0;
      w_next           = 0;
      round_ctr_inc    = 0;
      round_ctr_rst    = 0;
      digest_valid_new = 0;
      digest_valid_we  = 0;
      sha1_ctrl_new    = CTRL_IDLE;
      sha1_ctrl_we     = 0;
      next_stage_cnt   = 0; 

      case (sha1_ctrl_reg)
        CTRL_IDLE:
          begin
            ready_flag = 1;

            if (init)
              begin
                digest_init      = 1;
                w_init           = 1;
                state_init       = 1;
                first_block      = 1;
                round_ctr_rst    = 1;
                digest_valid_new = 0;
                digest_valid_we  = 1;
                sha1_ctrl_new    = CTRL_ROUNDS;
                sha1_ctrl_we     = 1;
                next_stage_cnt   = 0; 
              end

            if (next)
              begin
                w_init           = 1;
                state_init       = 1;
                round_ctr_rst    = 1;
                digest_valid_new = 0;
                digest_valid_we  = 1;
                sha1_ctrl_new    = CTRL_ROUNDS;
                sha1_ctrl_we     = 1;
                next_stage_cnt   = 0; 
              end
          end


        CTRL_ROUNDS:
          begin
            state_update  = 1;




            if(stage_cnt0q == NUM_DELAY) begin
              round_ctr_inc = 1;
              w_next        = 1;
               next_stage_cnt= 'd0;
            end 
            else 
              next_stage_cnt= stage_cnt0q + 1'b1; 

            if (round_ctr_reg == SHA1_ROUNDS)
              begin
                if(stage_cnt0q == NUM_DELAY) begin
                  sha1_ctrl_new = CTRL_DONE;
                  sha1_ctrl_we  = 1;
                end 
              end
          end


        CTRL_DONE:
          begin
            digest_update    = 1;
            digest_valid_new = 1;
            digest_valid_we  = 1;
            sha1_ctrl_new    = CTRL_IDLE;
            sha1_ctrl_we     = 1;
            next_stage_cnt   = 1'b0;
          end
      endcase
    end

endmodule