data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v
1: b'%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:143: Cannot find file containing module: \'ALU\'\nALU u_ALU(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/ALU\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/ALU.v\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:176: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'to_optype\' generates 6 bits.\n                                                                                                            : ... In instance ALUmodule\n  local_optype=to_optype;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:180: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h3f\' generates 6 bits.\n                                                                                                            : ... In instance ALUmodule\n  local_optype=6\'h3F;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:185: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'optype\' generates 6 bits.\n                                                                                                            : ... In instance ALUmodule\n  local_optype=optype;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:203: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'local_optype\' generates 32 bits.\n                                                                                                            : ... In instance ALUmodule\n  to_optype<=local_optype;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:217: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                                                            : ... In instance ALUmodule\n  if(local_optype==6\'h00 || local_optype==6\'h01 || local_optype==6\'h02\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:217: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1\' generates 6 bits.\n                                                                                                            : ... In instance ALUmodule\n  if(local_optype==6\'h00 || local_optype==6\'h01 || local_optype==6\'h02\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:217: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n                                                                                                            : ... In instance ALUmodule\n  if(local_optype==6\'h00 || local_optype==6\'h01 || local_optype==6\'h02\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:218: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n                                                                                                            : ... In instance ALUmodule\n  || local_optype==6\'h04 || local_optype==6\'h05 || local_optype==6\'h06 || local_optype==6\'h13)\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:218: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h5\' generates 6 bits.\n                                                                                                            : ... In instance ALUmodule\n  || local_optype==6\'h04 || local_optype==6\'h05 || local_optype==6\'h06 || local_optype==6\'h13)\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:218: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n                                                                                                            : ... In instance ALUmodule\n  || local_optype==6\'h04 || local_optype==6\'h05 || local_optype==6\'h06 || local_optype==6\'h13)\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/ALUmodule.v:218: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'6\'h13\' generates 6 bits.\n                                                                                                            : ... In instance ALUmodule\n  || local_optype==6\'h04 || local_optype==6\'h05 || local_optype==6\'h06 || local_optype==6\'h13)\n                                                                                      ^~\n%Error: Exiting due to 1 error(s), 11 warning(s)\n'
module ALUmodule(
	input clk,
	input rst_n,
	
	input alu_stall,
	input alu_bubble,

	input [31:0] pc,
	input [31:0] ir,
	input [4:0] regaddr1,
	input [4:0] regaddr2,
	input [4:0] regaddr3,
	input [31:0] alu_a,
	input [31:0] alu_b,
	input [4:0] op,
	input [5:0] optype,
	
	input [31:0] swdata,
	

	input [4:0] a_bwregaddr,
	input [31:0] a_bw_data,
	input a_valid,

	input [4:0] b_bwregaddr,
	input [31:0] b_bw_data,
	input b_valid,
	
	

	output [31:0] walu_out,
	output wflag,
	

	output reg to_valid,
	output reg [4:0] to_regaddr3,
	output reg [31:0] alu_out,
	output reg flag,
	output reg [31:0] to_swdata,


	output reg [31:0] to_pc,
	output reg [31:0] to_ir,
	output reg [5:0] to_optype
	
);

reg [31:0] local_d1;
reg [31:0] local_d2;



always@(*)
begin
	local_d1=alu_a;
	local_d2=alu_b;
	if(optype==6'h00 || optype==6'h12)
	begin
		if(a_bwregaddr==regaddr1 && a_valid)
		begin
			local_d1=a_bw_data;
		end
		else if(b_bwregaddr==regaddr1 && b_valid)
		begin
			local_d1=b_bw_data;
		end
		else
		begin
			local_d1=alu_a;
		end
				
		if(a_bwregaddr==regaddr2 && a_valid)
		begin
			local_d2=a_bw_data;
		end
		else if(b_bwregaddr==regaddr2 && b_valid)
		begin
			local_d2=b_bw_data;
		end
		else
		begin
			local_d2=alu_b;
		end
	end
	
	else if(optype==6'h01 || optype==6'h02 || optype==6'h04 || optype==6'h05
		|| optype==6'h10 || optype==6'h13 || optype==6'h14)
	begin
		if(a_bwregaddr==regaddr1 && a_valid)
		begin
			local_d1=a_bw_data;
		end
		else if(b_bwregaddr==regaddr1 && b_valid)
		begin
			local_d1=b_bw_data;
		end
		else
		begin
			local_d1=alu_a;
		end
		
		if(a_bwregaddr==regaddr2 && a_valid)
		begin
			local_swdata=a_bw_data;
		end
		else if(b_bwregaddr==regaddr2 && b_valid)
		begin
			local_swdata=b_bw_data;
		end
		else
		begin
			local_swdata=swdata;
		end
		
	end
	else
	begin
	end
end



ALU u_ALU(
	.alu_a(local_d1),
	.alu_b(local_d2),
	.alu_op(op),
	.alu_out(walu_out),
	.flag(wflag)
);

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		alu_out<=32'hCCCC_CCCC;
		flag<=0;
	end
	else
	begin
		alu_out<=walu_out;
		flag<=wflag;
	end
end

reg [31:0] local_pc;
reg [31:0] local_ir;
reg [31:0] local_optype;
reg [31:0] local_swdata;

always@(*)
begin
	if(alu_stall)
	begin
		local_pc=to_pc;
		local_ir=to_ir;
		local_optype=to_optype;
	end
	else if(alu_bubble)
	begin
		local_optype=6'h3F;
	end
	begin
		local_pc=pc;
		local_ir=ir;
		local_optype=optype;
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		to_pc<=32'h0;
		to_ir<=32'h0;
		to_optype<=6'h3F;
		to_regaddr3<=5'h0;
		to_valid<=0;
	end
	else if(alu_stall)
	begin
		to_pc<=local_pc;
		to_ir<=local_ir;
		to_optype<=local_optype;
		to_swdata<=local_swdata;
	end
	else
	begin
		to_pc<=pc;
		to_ir<=ir;
		to_optype<=optype;


		to_swdata<=local_swdata;
		
		to_regaddr3<=regaddr3;
		
		if(local_optype==6'h00 || local_optype==6'h01 || local_optype==6'h02
		|| local_optype==6'h04 || local_optype==6'h05 || local_optype==6'h06 || local_optype==6'h13)
			to_valid<=1;
		else
			to_valid<=0;
	end
end


endmodule
module ALUmodule(
	input clk,
	input rst_n,
	
	input alu_stall,
	input alu_bubble,

	input [31:0] pc,
	input [31:0] ir,
	input [4:0] regaddr1,
	input [4:0] regaddr2,
	input [4:0] regaddr3,
	input [31:0] alu_a,
	input [31:0] alu_b,
	input [4:0] op,
	input [5:0] optype,
	
	input [31:0] swdata,
	

	input [4:0] a_bwregaddr,
	input [31:0] a_bw_data,
	input a_valid,

	input [4:0] b_bwregaddr,
	input [31:0] b_bw_data,
	input b_valid,
	
	

	output [31:0] walu_out,
	output wflag,
	

	output reg to_valid,
	output reg [4:0] to_regaddr3,
	output reg [31:0] alu_out,
	output reg flag,
	output reg [31:0] to_swdata,


	output reg [31:0] to_pc,
	output reg [31:0] to_ir,
	output reg [5:0] to_optype
	
);


reg [31:0] local_d1;
reg [31:0] local_d2;



always@(*)
begin
	local_d1=alu_a;
	local_d2=alu_b;
	if(optype==6'h00 || optype==6'h12)
	begin
		if(a_bwregaddr==regaddr1 && a_valid)
		begin
			local_d1=a_bw_data;
		end
		else if(b_bwregaddr==regaddr1 && b_valid)
		begin
			local_d1=b_bw_data;
		end
		else
		begin
			local_d1=alu_a;
		end
				
		if(a_bwregaddr==regaddr2 && a_valid)
		begin
			local_d2=a_bw_data;
		end
		else if(b_bwregaddr==regaddr2 && b_valid)
		begin
			local_d2=b_bw_data;
		end
		else
		begin
			local_d2=alu_b;
		end
	end
	
	else if(optype==6'h01 || optype==6'h02 || optype==6'h04 || optype==6'h05
		|| optype==6'h10 || optype==6'h13 || optype==6'h14)
	begin
		if(a_bwregaddr==regaddr1 && a_valid)
		begin
			local_d1=a_bw_data;
		end
		else if(b_bwregaddr==regaddr1 && b_valid)
		begin
			local_d1=b_bw_data;
		end
		else
		begin
			local_d1=alu_a;
		end
		
		if(a_bwregaddr==regaddr2 && a_valid)
		begin
			local_swdata=a_bw_data;
		end
		else if(b_bwregaddr==regaddr2 && b_valid)
		begin
			local_swdata=b_bw_data;
		end
		else
		begin
			local_swdata=swdata;
		end
		
	end
	else
	begin
	end
end



ALU u_ALU(
	.alu_a(local_d1),
	.alu_b(local_d2),
	.alu_op(op),
	.alu_out(walu_out),
	.flag(wflag)
);

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		alu_out<=32'hCCCC_CCCC;
		flag<=0;
	end
	else
	begin
		alu_out<=walu_out;
		flag<=wflag;
	end
end

reg [31:0] local_pc;
reg [31:0] local_ir;
reg [31:0] local_optype;
reg [31:0] local_swdata;

always@(*)
begin
	if(alu_stall)
	begin
		local_pc=to_pc;
		local_ir=to_ir;
		local_optype=to_optype;
	end
	else if(alu_bubble)
	begin
		local_optype=6'h3F;
	end
	begin
		local_pc=pc;
		local_ir=ir;
		local_optype=optype;
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		to_pc<=32'h0;
		to_ir<=32'h0;
		to_optype<=6'h3F;
		to_regaddr3<=5'h0;
		to_valid<=0;
	end
	else if(alu_stall)
	begin
		to_pc<=local_pc;
		to_ir<=local_ir;
		to_optype<=local_optype;
		to_swdata<=local_swdata;
	end
	else
	begin
		to_pc<=pc;
		to_ir<=ir;
		to_optype<=optype;


		to_swdata<=local_swdata;
		
		to_regaddr3<=regaddr3;
		
		if(local_optype==6'h00 || local_optype==6'h01 || local_optype==6'h02
		|| local_optype==6'h04 || local_optype==6'h05 || local_optype==6'h06 || local_optype==6'h13)
			to_valid<=1;
		else
			to_valid<=0;
	end
end


endmodule