data/full_repos/permissive/188795755/elec_design/beta1/sim/tb_state.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/188795755/elec_design/beta1/sim/tb_state.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/188795755/elec_design/beta1/sim/tb_state.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/188795755/elec_design/beta1/sim/tb_state.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/188795755/elec_design/beta1/sim/tb_state.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/188795755/elec_design/beta1/sim/tb_state.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/188795755/elec_design/beta1/sim/tb_state.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/188795755/elec_design/beta1/sim/tb_state.v:38: Unsupported: Ignoring delay on this delayed statement.\nalways  #10     sclk    =       ~sclk;\n        ^\n%Error: data/full_repos/permissive/188795755/elec_design/beta1/sim/tb_state.v:40: Cannot find file containing module: \'state\'\nstate   state_inst(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/188795755/elec_design/beta1/sim,data/full_repos/permissive/188795755/state\n             data/full_repos/permissive/188795755/elec_design/beta1/sim,data/full_repos/permissive/188795755/state.v\n             data/full_repos/permissive/188795755/elec_design/beta1/sim,data/full_repos/permissive/188795755/state.sv\n             state\n             state.v\n             state.sv\n             obj_dir/state\n             obj_dir/state.v\n             obj_dir/state.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module  tb_state();

reg                     sclk                    ;
reg                     s_rst_n                 ;
reg                     catcher                 ;
reg                     jockey_r                ;
reg                     jockey_l                ;
reg                     key                     ;

wire                    direct                  ;
wire                    stepenable              ;

initial begin
        sclk    =       1'b1;
        s_rst_n <=      1'b0;
        catcher <=      1'b1;
        jockey_l<=      1'b1;
        jockey_r<=      1'b1;
        key     <=      1'b0;
        #100
        s_rst_n <=      1'b1;
        #100
        key     <=      1'b1;
        #20
        key     <=      1'b0;
        #100
        catcher <=      1'b0;
        jockey_l<=      1'b0;
        #100
        key     <=      1'b1;
        #20
        key     <=      1'b0;
        
end

always  #10     sclk    =       ~sclk;

state   state_inst(
        .sclk                   (sclk                   ),
        .s_rst_n                (s_rst_n                ),
        .catcher                (catcher                ),
        .jockey_r               (jockey_r               ),
        .jockey_l               (jockey_l               ),
        .key                    (key                    ),
        .direct                 (direct                 ),
        .stepenable             (stepenable             )
);

endmodule
module  tb_state();


reg                     sclk                    ;
reg                     s_rst_n                 ;
reg                     catcher                 ;
reg                     jockey_r                ;
reg                     jockey_l                ;
reg                     key                     ;

wire                    direct                  ;
wire                    stepenable              ;

initial begin
        sclk    =       1'b1;
        s_rst_n <=      1'b0;
        catcher <=      1'b1;
        jockey_l<=      1'b1;
        jockey_r<=      1'b1;
        key     <=      1'b0;
        #100
        s_rst_n <=      1'b1;
        #100
        key     <=      1'b1;
        #20
        key     <=      1'b0;
        #100
        catcher <=      1'b0;
        jockey_l<=      1'b0;
        #100
        key     <=      1'b1;
        #20
        key     <=      1'b0;
        
end

always  #10     sclk    =       ~sclk;

state   state_inst(
        .sclk                   (sclk                   ),
        .s_rst_n                (s_rst_n                ),
        .catcher                (catcher                ),
        .jockey_r               (jockey_r               ),
        .jockey_l               (jockey_l               ),
        .key                    (key                    ),
        .direct                 (direct                 ),
        .stepenable             (stepenable             )
);

endmodule