data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:40: Cannot find include file: tartcfg.v\n`include "tartcfg.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:50: Define or directive not defined: \'`NUM_ANTENNA\'\n   parameter AXNUM = `NUM_ANTENNA;  \n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:50: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter AXNUM = `NUM_ANTENNA;  \n                                 ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:52: Define or directive not defined: \'`ACCUM_BITS\'\n   parameter ACCUM = `ACCUM_BITS;   \n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:52: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter ACCUM = `ACCUM_BITS;   \n                                ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:55: Define or directive not defined: \'`TMUX_RATE\'\n   parameter TRATE = `TMUX_RATE;    \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:55: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter TRATE = `TMUX_RATE;    \n                               ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:56: Define or directive not defined: \'`TMUX_BITS\'\n   parameter TBITS = `TMUX_BITS;    \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter TBITS = `TMUX_BITS;    \n                               ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:61: Define or directive not defined: \'`BANK_BITS\'\n   parameter XBITS = `BANK_BITS;  \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:61: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter XBITS = `BANK_BITS;  \n                               ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:69: Define or directive not defined: \'`WBADR_BITS\'\n   parameter ABITS = `WBADR_BITS;   \n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:69: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter ABITS = `WBADR_BITS;   \n                                ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:71: Define or directive not defined: \'`WBBUS_BITS\'\n   parameter BBITS = `WBBUS_BITS;   \n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:71: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter BBITS = `WBBUS_BITS;   \n                                ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:75: Define or directive not defined: \'`READ_BITS\'\n   parameter FBITS = `READ_BITS;  \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter FBITS = `READ_BITS;  \n                               ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:96: Define or directive not defined: \'`DELAY\'\n   parameter DELAY = `DELAY;        \n                     ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter DELAY = `DELAY;        \n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n      #LIMIT $display ("\\nTIMEOUT!\\n");\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:175: Define or directive not defined: \'`CLK_X\'\n   always #`CLK_X  clk_x <= ~clk_x;\n           ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:175: syntax error, unexpected <=\n   always #`CLK_X  clk_x <= ~clk_x;\n                         ^~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n   always #`CLK_X  clk_x <= ~clk_x;\n          ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:176: Define or directive not defined: \'`CLK_B\'\n   always #`CLK_B  b_clk <= ~b_clk;\n           ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:176: syntax error, unexpected <=\n   always #`CLK_B  b_clk <= ~b_clk;\n                         ^~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n   always #`CLK_B  b_clk <= ~b_clk;\n          ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:177: Define or directive not defined: \'`CLK_E\'\n   always #`CLK_E  clk_e <= ~clk_e;\n           ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:177: syntax error, unexpected <=\n   always #`CLK_E  clk_e <= ~clk_e;\n                         ^~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n   always #`CLK_E  clk_e <= ~clk_e;\n          ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:199: Unsupported or unknown PLI call: $dumpfile\n         $dumpfile("vcd/dsp_tb.vcd");\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:200: Unsupported or unknown PLI call: $dumpvars\n         $dumpvars;\n         ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n      #20 $display("\\n%12t: Issuing RESET.", $time);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:234: Unsupported: Ignoring delay on this delayed statement.\n      #13 rst <= 1; #40 rst <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:234: Unsupported: Ignoring delay on this delayed statement.\n      #13 rst <= 1; #40 rst <= 0;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:240: Unsupported: Ignoring delay on this delayed statement.\n      #40 set <= 1; num <= 1; dtx <= {1\'b1, 2\'b00, log_bsize}; adr <= 2\'b11;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:241: Unsupported: Ignoring delay on this delayed statement.\n      while (!fin) #10;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:247: Unsupported: Ignoring delay on this delayed statement.\n      while (viz_bank < READS) #10;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:249: Unsupported: Ignoring delay on this delayed statement.\n      while (bsy) #10;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:251: Unsupported: Ignoring delay on this delayed statement.\n      #10 set <= 1; num <= 1; dtx <= 8\'h00; adr <= 2\'b11;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n      while (!fin) #10;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n      #10 while (dsp_bank < READS) #80;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n      #10 while (dsp_bank < READS) #80;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:262: Unsupported: Ignoring delay on this delayed statement.\n      #80 $display("%12t: Simulation finished:", $time);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:271: Unsupported: Ignoring delay on this delayed statement.\n      #83;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:273: Unsupported: Ignoring delay on this delayed statement.\n         while (!newblock) #10;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:274: Unsupported: Ignoring delay on this delayed statement.\n         while (bsy) #10;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:275: Unsupported: Ignoring delay on this delayed statement.\n         #10 $display("%12t: Reading back visibilities (bank %1d)", $time, dsp_bank);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:276: Unsupported: Ignoring delay on this delayed statement.\n         #10 get <= 1; num <= BREAD; adr <= 2\'b00;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:277: Unsupported: Ignoring delay on this delayed statement.\n         while (!fin) #10;\n                      ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:737: Define or directive not defined: \'`DELAY\'\n    parameter DELAY = `DELAY\n                      ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:738: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    )\n    ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_dsp_tb.v:750: syntax error, unexpected assign\n   assign ddr = dly[0] ? neg : pos;\n   ^~~~~~\n%Error: Exiting due to 30 error(s), 22 warning(s)\n'
module iobs
  #(parameter WIDTH = 24,
    parameter MSB   = WIDTH-1,
    parameter DELAY = `DELAY
    )
   (
    input          clk,
    input          rst,
    input          en,
    input [3:0]    dly,
    input [MSB:0]  raw,
    output [MSB:0] sig
   );

   wire [MSB:0]    ddr, neg, pos;

   assign ddr = dly[0] ? neg : pos;



   IDDR2
     #( .DDR_ALIGNMENT("C0"),
        .SRTYPE("SYNC")
        ) IOBS [MSB:0]
     ( .C0(clk),
       .C1(~clk),
       .R (rst),
       .S ({WIDTH{1'b0}}),
       .CE(en),
       .D (raw),
       .Q0(pos),
       .Q1(neg)
       );





   shift_reg
     #(  .DEPTH(8),
         .ABITS(3),
         .DELAY(DELAY)
         ) SHREG [MSB:0]
       ( .clk(clk),
         .ce (en),
         .a  (dly[3:1]),
         .d  (ddr),
         .q  (sig)
         );

   
endmodule
module iobs
  #(parameter WIDTH = 24,
    parameter MSB   = WIDTH-1,
    parameter DELAY = `DELAY
    )
   (
    input          clk,
    input          rst,
    input          en,
    input [3:0]    dly,
    input [MSB:0]  raw,
    output [MSB:0] sig
   );


   wire [MSB:0]    ddr, neg, pos;

   assign ddr = dly[0] ? neg : pos;



   IDDR2
     #( .DDR_ALIGNMENT("C0"),
        .SRTYPE("SYNC")
        ) IOBS [MSB:0]
     ( .C0(clk),
       .C1(~clk),
       .R (rst),
       .S ({WIDTH{1'b0}}),
       .CE(en),
       .D (raw),
       .Q0(pos),
       .Q1(neg)
       );





   shift_reg
     #(  .DEPTH(8),
         .ABITS(3),
         .DELAY(DELAY)
         ) SHREG [MSB:0]
       ( .clk(clk),
         .ce (en),
         .a  (dly[3:1]),
         .d  (ddr),
         .q  (sig)
         );

   
endmodule