data/full_repos/permissive/159001439/src/rgmii_tx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/159001439/src/rgmii_tx.v:44: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                      : ... In instance rgmii_tx\n  rst_sync <= {rst_sync, 1\'b1};\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/rgmii_tx.v:55: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                      : ... In instance rgmii_tx\n  data_r <= \'bx;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/rgmii_tx.v:56: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                      : ... In instance rgmii_tx\n  data_f <= \'bx;\n         ^~\n%Error: data/full_repos/permissive/159001439/src/rgmii_tx.v:84: Cannot find file containing module: \'ODDR\'\nODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d0_oddr_i(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/159001439/src,data/full_repos/permissive/159001439/ODDR\n             data/full_repos/permissive/159001439/src,data/full_repos/permissive/159001439/ODDR.v\n             data/full_repos/permissive/159001439/src,data/full_repos/permissive/159001439/ODDR.sv\n             ODDR\n             ODDR.v\n             ODDR.sv\n             obj_dir/ODDR\n             obj_dir/ODDR.v\n             obj_dir/ODDR.sv\n%Error: data/full_repos/permissive/159001439/src/rgmii_tx.v:87: Cannot find file containing module: \'ODDR\'\nODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d1_oddr_i(\n^~~~\n%Error: data/full_repos/permissive/159001439/src/rgmii_tx.v:90: Cannot find file containing module: \'ODDR\'\nODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d2_oddr_i(\n^~~~\n%Error: data/full_repos/permissive/159001439/src/rgmii_tx.v:93: Cannot find file containing module: \'ODDR\'\nODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d3_oddr_i(\n^~~~\n%Error: data/full_repos/permissive/159001439/src/rgmii_tx.v:96: Cannot find file containing module: \'ODDR\'\nODDR #(.DDR_CLK_EDGE("SAME_EDGE")) ctl_oddr_i(\n^~~~\n%Error: data/full_repos/permissive/159001439/src/rgmii_tx.v:102: Cannot find file containing module: \'ODDR\'\n ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) clk_oddr_i(\n ^~~~\n%Error: Exiting due to 6 error(s), 3 warning(s)\n'
module rgmii_tx(
	input reset,
	input speed,


	input txclk_x2,
	input txclk,
	input [7:0] txd,
	input txen,
	input txer,


	output rgmii_gtxclk,
	output [3:0] rgmii_txdat,
	output rgmii_txctl
);




parameter MODE = "ALIGNED"; 

(* ASYNC_REG = "TRUE" *)
reg [3:0] rst_sync;
wire rst_in;
wire clk_out;

reg txctl_r;
reg txctl_f;

reg [3:0] data_r;
reg [3:0] data_f;

reg odd_flag;

assign rst_in = !rst_sync[3];

always @(posedge txclk_x2, posedge reset)
begin
	if(reset)
		rst_sync <= 'b0;
	else
		rst_sync <= {rst_sync, 1'b1};
end



assign clk_out = txclk_x2;

always @(negedge clk_out, posedge rst_in)
begin
	if(rst_in) begin
		odd_flag <= 1'b0;
		data_r <= 'bx;
		data_f <= 'bx;
		txctl_r <= 1'b0;
		txctl_f <= 1'b0;
	end
	else if(speed) begin
		data_r <= txd[3:0];
		data_f <= txd[7:4];
		txctl_r = txen;
		txctl_f = txen^txer;
	end
	else begin
		if(!odd_flag) begin
			data_r <= txd[3:0];
			data_f <= txd[3:0];
			txctl_r <= txen;
			txctl_f <= txen^txer;
			if(txen) begin
				odd_flag <= 1'b1;
			end
		end
		else begin
			data_r <= txd[7:4];
			data_f <= txd[7:4];
			odd_flag <= 1'b0;
		end
	end
end

ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d0_oddr_i(
	.D1(data_r[0]), .D2(data_f[0]), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_txdat[0]));

ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d1_oddr_i(
	.D1(data_r[1]), .D2(data_f[1]), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_txdat[1]));

ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d2_oddr_i(
	.D1(data_r[2]), .D2(data_f[2]), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_txdat[2]));

ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d3_oddr_i(
	.D1(data_r[3]), .D2(data_f[3]), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_txdat[3]));

ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) ctl_oddr_i(
	.D1(txctl_r), .D2(txctl_f), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_txctl));


generate
if(MODE=="ALIGNED") begin
	ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) clk_oddr_i(
		.D1(1'b1), .D2(1'b0), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_gtxclk));
end
else if(MODE=="DELAYED") begin
	wire rgmii_gtxclk_d;
	wire clk_dly;
	(* DONT_TOUCH = "TRUE" *) 
	LUT1 #(.INIT(2'b10)) d1(.I0(clk_out),.O(clk_dly));


	OBUF clk_obuf_i(.I(clk_dly), .O(rgmii_gtxclk_d));
	assign #2 rgmii_gtxclk = rgmii_gtxclk_d;
end
else if(MODE=="SYSTEM") begin
	wire rgmii_gtxclk_d;
	OBUF clk_obuf_i(.I(!clk_out), .O(rgmii_gtxclkd));
	assign #2 rgmii_gtxclk = rgmii_gtxclk_d;
end
endgenerate

endmodule
module rgmii_tx(
	input reset,
	input speed,


	input txclk_x2,
	input txclk,
	input [7:0] txd,
	input txen,
	input txer,


	output rgmii_gtxclk,
	output [3:0] rgmii_txdat,
	output rgmii_txctl
);





parameter MODE = "ALIGNED"; 

(* ASYNC_REG = "TRUE" *)
reg [3:0] rst_sync;
wire rst_in;
wire clk_out;

reg txctl_r;
reg txctl_f;

reg [3:0] data_r;
reg [3:0] data_f;

reg odd_flag;

assign rst_in = !rst_sync[3];

always @(posedge txclk_x2, posedge reset)
begin
	if(reset)
		rst_sync <= 'b0;
	else
		rst_sync <= {rst_sync, 1'b1};
end



assign clk_out = txclk_x2;

always @(negedge clk_out, posedge rst_in)
begin
	if(rst_in) begin
		odd_flag <= 1'b0;
		data_r <= 'bx;
		data_f <= 'bx;
		txctl_r <= 1'b0;
		txctl_f <= 1'b0;
	end
	else if(speed) begin
		data_r <= txd[3:0];
		data_f <= txd[7:4];
		txctl_r = txen;
		txctl_f = txen^txer;
	end
	else begin
		if(!odd_flag) begin
			data_r <= txd[3:0];
			data_f <= txd[3:0];
			txctl_r <= txen;
			txctl_f <= txen^txer;
			if(txen) begin
				odd_flag <= 1'b1;
			end
		end
		else begin
			data_r <= txd[7:4];
			data_f <= txd[7:4];
			odd_flag <= 1'b0;
		end
	end
end

ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d0_oddr_i(
	.D1(data_r[0]), .D2(data_f[0]), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_txdat[0]));

ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d1_oddr_i(
	.D1(data_r[1]), .D2(data_f[1]), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_txdat[1]));

ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d2_oddr_i(
	.D1(data_r[2]), .D2(data_f[2]), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_txdat[2]));

ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) d3_oddr_i(
	.D1(data_r[3]), .D2(data_f[3]), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_txdat[3]));

ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) ctl_oddr_i(
	.D1(txctl_r), .D2(txctl_f), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_txctl));


generate
if(MODE=="ALIGNED") begin
	ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) clk_oddr_i(
		.D1(1'b1), .D2(1'b0), .CE(1'b1), .C(clk_out), .S(1'b0), .R(1'b0), .Q(rgmii_gtxclk));
end
else if(MODE=="DELAYED") begin
	wire rgmii_gtxclk_d;
	wire clk_dly;
	(* DONT_TOUCH = "TRUE" *) 
	LUT1 #(.INIT(2'b10)) d1(.I0(clk_out),.O(clk_dly));


	OBUF clk_obuf_i(.I(clk_dly), .O(rgmii_gtxclk_d));
	assign #2 rgmii_gtxclk = rgmii_gtxclk_d;
end
else if(MODE=="SYSTEM") begin
	wire rgmii_gtxclk_d;
	OBUF clk_obuf_i(.I(!clk_out), .O(rgmii_gtxclkd));
	assign #2 rgmii_gtxclk = rgmii_gtxclk_d;
end
endgenerate

endmodule