data/full_repos/permissive/206842334/src/sig_altmult_accum.v
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data/verilator_xmls/25fed2d8-611b-4599-b616-ea8b44746c27.xml
module sig_altmult_accum
(
	input [7:0] dataa,
	input [7:0] datab,
	input clk, aclr, clken, sload,
	output signed [17:0] adder_out
);


	reg	signed [17:0] old_result;
	reg signed [17:0] accum_out;
	wire signed [17:0] multa;
	reg sload_reg;
	

	assign multa = $signed(dataa) * $signed(datab);
	

	always @ (accum_out, sload_reg)
	begin
		if (sload_reg)
			old_result <= 0;
		else
			old_result <= accum_out;
	end

	assign adder_out = accum_out;
	

	always @ (posedge clk or posedge aclr)
	begin
		if (aclr)
		begin


			sload_reg <= 0;
			accum_out <= 0;
		end
		
		else if (clken)
		begin


			sload_reg <= sload;
			accum_out <= old_result + multa;
		end

	end
endmodule
module sig_altmult_accum
(
	input [7:0] dataa,
	input [7:0] datab,
	input clk, aclr, clken, sload,
	output signed [17:0] adder_out
);



	reg	signed [17:0] old_result;
	reg signed [17:0] accum_out;
	wire signed [17:0] multa;
	reg sload_reg;
	

	assign multa = $signed(dataa) * $signed(datab);
	

	always @ (accum_out, sload_reg)
	begin
		if (sload_reg)
			old_result <= 0;
		else
			old_result <= accum_out;
	end

	assign adder_out = accum_out;
	

	always @ (posedge clk or posedge aclr)
	begin
		if (aclr)
		begin


			sload_reg <= 0;
			accum_out <= 0;
		end
		
		else if (clken)
		begin


			sload_reg <= sload;
			accum_out <= old_result + multa;
		end

	end
endmodule