data/full_repos/permissive/104269513/ALU_final_smaller.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:416: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:422: Unsupported: Ignoring delay on this delayed statement.\n#99\n^\n%Error: data/full_repos/permissive/104269513/ALU_final_smaller.v:424: Too many digits for 32 bit number: \'hFFFF_FFFF_FFFF_FFFF\nA=\'hFFFF_FFFF_FFFF_FFFF;\n  ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:428: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:431: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:434: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:437: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:440: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:443: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:446: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module one_bit_add_Sub (input A,
						input B,
						input Cin,
						input b_invert,
						output Cout,
						output Sum);

						



wire Bin;


assign Bin = b_invert ^ B;

	xor(Sum, A, Cin, Bin);
    and(w1, A, Bin);   
    and(w2, A, Cin);
    and(w3, Bin, Cin);   
    or(Cout, w1, w2, w3);
	



endmodule
module one_bit_add_Sub (input A,
						input B,
						input Cin,
						input b_invert,
						output Cout,
						output Sum);


						



wire Bin;


assign Bin = b_invert ^ B;

	xor(Sum, A, Cin, Bin);
    and(w1, A, Bin);   
    and(w2, A, Cin);
    and(w3, Bin, Cin);   
    or(Cout, w1, w2, w3);
	



endmodule