data/full_repos/permissive/143278/ivltests/pr1833024.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr1833024.v:30: Unsupported: Verilog 1995 gate primitive: tran\n  tran(wsbstr[0], wsarr[1]);\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1833024.v:31: Unsupported: Verilog 1995 gate primitive: tran\n  tran(wspstr[0:0], wsarr[1]);\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1833024.v:32: Unsupported: Verilog 1995 gate primitive: tran\n  tran(wsuptr[0+:1], wsarr[1]);\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1833024.v:33: Unsupported: Verilog 1995 gate primitive: tran\n  tran(wsdotr[0-:1], wsarr[1]);\n      ^\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module submod3(arg1, arg2, arg3, arg4);
  inout arg1, arg2, arg3, arg4;
  wire arg1, arg2, arg3, arg4;

  initial $display("In submod3 with %b, %b, %b, %b", arg1, arg2, arg3, arg4);
endmodule
module submod3(arg1, arg2, arg3, arg4);

  inout arg1, arg2, arg3, arg4;
  wire arg1, arg2, arg3, arg4;

  initial $display("In submod3 with %b, %b, %b, %b", arg1, arg2, arg3, arg4);
endmodule