data/full_repos/permissive/196705942/src/EXPONENTADDITION.v
1: b'%Warning-WIDTH: data/full_repos/permissive/196705942/src/EXPONENTADDITION.v:27: Operator ADD expects 11 bits on the LHS, but LHS\'s VARREF \'X\' generates 9 bits.\n                                                                              : ... In instance EXPONENTADDITION\n    wire [10:0]Z = X + Y;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module EXPONENTADDITION(input [7:0]A, input [7:0]B, output [7:0]E);


    wire [8:0]X = A + B;
    parameter Y =10'b1110000001;
    wire [10:0]Z = X + Y;

    assign E = Z [7:0];
endmodule
module EXPONENTADDITION(input [7:0]A, input [7:0]B, output [7:0]E);



    wire [8:0]X = A + B;
    parameter Y =10'b1110000001;
    wire [10:0]Z = X + Y;

    assign E = Z [7:0];
endmodule