data/full_repos/permissive/181665138/verilog/capitolo_i/Rete_Totale_2.v
data/verilator_xmls/6f430daa-1b0f-496a-bb10-813e63c98d02.xml
module Rete_Totale_2(z3_z0, x7_x0);
    input   [7:0]   x7_x0;
    output  [3:0]   z3_z0;
    wire    [15:0]  a_R3;

    Rete_di_Tipo_A R1(a_R3[15:8], x7_x0[7:4], z3_z0[0]),
                   R2(a_R3[7:0], x7_x0[3:0], z3_z0[0]);

    Rete_di_Tipo_B R3(z3_z0, a_R3);
endmodule
module Rete_Totale_2(z3_z0, x7_x0);

    input   [7:0]   x7_x0;
    output  [3:0]   z3_z0;
    wire    [15:0]  a_R3;

    Rete_di_Tipo_A R1(a_R3[15:8], x7_x0[7:4], z3_z0[0]),
                   R2(a_R3[7:0], x7_x0[3:0], z3_z0[0]);

    Rete_di_Tipo_B R3(z3_z0, a_R3);
endmodule