data/full_repos/permissive/174369527/UART/Pynq_Z2/test_module.v
 line:15: before: "vector"
data/verilator_xmls/cb556928-dd02-4e17-a500-6f04356e2f91.xml
module test_module
	(
		in,
		out
	);
	
	input wire [3:0] in;
	output wire [3:0] out;

	assign out = in;

endmodule
module test_module
	(
		in,
		out
	);

	
	input wire [3:0] in;
	output wire [3:0] out;

	assign out = in;

endmodule