data/full_repos/permissive/108382235/Pipelined.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC,  SwitchClk_10, reset);\n       ^~~~~~~~~\n                                                                       : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  if (MemRead) ReadData=Dmemory[Address[31:2]];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n                                                                    : ... In instance Pipelined\n   IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n                ^~\n%Error: Exiting due to 5 warning(s)\n'
module EXStage(BranchAddr, Zero, ALUResult, ReadData2, RegDst, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, IDEX_Rt, IDEX_Rd, IDEX_Rs, WriteData, EXMEM_ALUResult, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite, IDEX_EX);
	input [31:0] IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, WriteData, EXMEM_ALUResult;
	input [4:0] IDEX_Rt, IDEX_Rd, IDEX_Rs, EXMEM_RegDst, MEMWB_RegDst;
	input [3:0] IDEX_EX;
	input EXMEM_RegWrite, MEMWB_RegWrite;
	output [31:0] BranchAddr, ALUResult, ReadData2;
	output Zero;
	output [4:0] RegDst;
	
	wire [31:0] BranchAddr, ALUResult, ReadData2, BranchOffset, ALUInput1, ALUInput2;
	wire Zero;
	wire [4:0] RegDst;
	wire [1:0] ForwardA, ForwardB;
	wire [3:0] ALUControlSignal;
	
	Mux_5bit_2to1 M_Mux_RegDst(RegDst, IDEX_Rt, IDEX_Rd, IDEX_EX[3]);
	ForwardingUnit M_Forward(ForwardA, ForwardB, IDEX_Rs, IDEX_Rt, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite);
	Alucontrol M_Alucontrol(ALUControlSignal,IDEX_EX[1:0],IDEX_Immediate_32[5:0]);
	ShiftLeftTwo_32to32 M_Shift_Immediate(BranchOffset, IDEX_Immediate_32);
	Adder_32bit M_Adder(BranchAddr, IDEX_PC, BranchOffset);
	Mux_32bit_3to1 M_Mux_ForwardA(ALUInput1, IDEX_ReadData1, WriteData, EXMEM_ALUResult, ForwardA);
	Mux_32bit_3to1 M_Mux_ForwardB(ReadData2, IDEX_ReadData2, WriteData, EXMEM_ALUResult, ForwardB);
	Mux_32bit_2to1 M_Mux_ALUSrc(ALUInput2, IDEX_Immediate_32, ReadData2, IDEX_EX[2]);
	ALU M_ALU(ALUResult,Zero,ALUControlSignal,ALUInput1,ALUInput2);
endmodule
module EXStage(BranchAddr, Zero, ALUResult, ReadData2, RegDst, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, IDEX_Rt, IDEX_Rd, IDEX_Rs, WriteData, EXMEM_ALUResult, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite, IDEX_EX);

	input [31:0] IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, WriteData, EXMEM_ALUResult;
	input [4:0] IDEX_Rt, IDEX_Rd, IDEX_Rs, EXMEM_RegDst, MEMWB_RegDst;
	input [3:0] IDEX_EX;
	input EXMEM_RegWrite, MEMWB_RegWrite;
	output [31:0] BranchAddr, ALUResult, ReadData2;
	output Zero;
	output [4:0] RegDst;
	
	wire [31:0] BranchAddr, ALUResult, ReadData2, BranchOffset, ALUInput1, ALUInput2;
	wire Zero;
	wire [4:0] RegDst;
	wire [1:0] ForwardA, ForwardB;
	wire [3:0] ALUControlSignal;
	
	Mux_5bit_2to1 M_Mux_RegDst(RegDst, IDEX_Rt, IDEX_Rd, IDEX_EX[3]);
	ForwardingUnit M_Forward(ForwardA, ForwardB, IDEX_Rs, IDEX_Rt, EXMEM_RegDst, EXMEM_RegWrite, MEMWB_RegDst, MEMWB_RegWrite);
	Alucontrol M_Alucontrol(ALUControlSignal,IDEX_EX[1:0],IDEX_Immediate_32[5:0]);
	ShiftLeftTwo_32to32 M_Shift_Immediate(BranchOffset, IDEX_Immediate_32);
	Adder_32bit M_Adder(BranchAddr, IDEX_PC, BranchOffset);
	Mux_32bit_3to1 M_Mux_ForwardA(ALUInput1, IDEX_ReadData1, WriteData, EXMEM_ALUResult, ForwardA);
	Mux_32bit_3to1 M_Mux_ForwardB(ReadData2, IDEX_ReadData2, WriteData, EXMEM_ALUResult, ForwardB);
	Mux_32bit_2to1 M_Mux_ALUSrc(ALUInput2, IDEX_Immediate_32, ReadData2, IDEX_EX[2]);
	ALU M_ALU(ALUResult,Zero,ALUControlSignal,ALUInput1,ALUInput2);
endmodule