data/full_repos/permissive/172908596/BEQ instruction/beq.v
1: b'%Error: Cannot find file containing module: instruction,data/full_repos/permissive/172908596\n        ... Looked in:\n             data/full_repos/permissive/172908596/BEQ/instruction,data/full_repos/permissive/172908596\n             data/full_repos/permissive/172908596/BEQ/instruction,data/full_repos/permissive/172908596.v\n             data/full_repos/permissive/172908596/BEQ/instruction,data/full_repos/permissive/172908596.sv\n             instruction,data/full_repos/permissive/172908596\n             instruction,data/full_repos/permissive/172908596.v\n             instruction,data/full_repos/permissive/172908596.sv\n             obj_dir/instruction,data/full_repos/permissive/172908596\n             obj_dir/instruction,data/full_repos/permissive/172908596.v\n             obj_dir/instruction,data/full_repos/permissive/172908596.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/172908596/BEQ\n%Error: Cannot find file containing module: instruction/beq.v\n%Error: Exiting due to 3 error(s)\n'
module beq_ins(r1,r2,imm,clk,ctrl,pc,npc);
input [4:0] r1;
input [4:0] r2;
input [11:0] imm;
input [5:0] ctrl;
input clk;
input [31:0] pc;
reg [63:0] regFile[0:31];
wire [63:0] a;
wire [63:0] b;
reg [63:0] x;
output wire [63:0] rd;
output reg [31:0] npc;
wire cout, zero, overflow;
wire [12:0] offset;   
assign offset = imm << 1;
integer i;
initial
begin
	for(i=0;i<16;i=i+1)
	begin
		regFile[i] <= i;
	end
end
initial
begin
	for(i=16;i<32;i=i+1)
	begin
		regFile[i] <= 32-i;
	end
end

	always@(*)
	begin
		x[11:0]= offset[12:0];
		x[63:12]={52{offset[12]}};
	end
	

	assign a=regFile[r1];
	assign b=regFile[r2];
ALU m1(a,b,ctrl[3:0],ctrl[5:4],rd,cout,zero,overflow);

	always@(posedge clk)
	begin	
		npc = (zero == 1)? (pc+x):(pc+64'b100); 
	end

endmodule
module beq_ins(r1,r2,imm,clk,ctrl,pc,npc);

input [4:0] r1;
input [4:0] r2;
input [11:0] imm;
input [5:0] ctrl;
input clk;
input [31:0] pc;
reg [63:0] regFile[0:31];
wire [63:0] a;
wire [63:0] b;
reg [63:0] x;
output wire [63:0] rd;
output reg [31:0] npc;
wire cout, zero, overflow;
wire [12:0] offset;   
assign offset = imm << 1;
integer i;
initial
begin
	for(i=0;i<16;i=i+1)
	begin
		regFile[i] <= i;
	end
end
initial
begin
	for(i=16;i<32;i=i+1)
	begin
		regFile[i] <= 32-i;
	end
end

	always@(*)
	begin
		x[11:0]= offset[12:0];
		x[63:12]={52{offset[12]}};
	end
	

	assign a=regFile[r1];
	assign b=regFile[r2];
ALU m1(a,b,ctrl[3:0],ctrl[5:4],rd,cout,zero,overflow);

	always@(posedge clk)
	begin	
		npc = (zero == 1)? (pc+x):(pc+64'b100); 
	end

endmodule