data/full_repos/permissive/210918583/boards/tf530r3/tf530r3_bus_top.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/210918583/boards/tf530r3/tf530r3_bus_top.v:146: Signal definition not found, creating implicitly: \'SLOWCYCLE\'\n                                                                                            : ... Suggested alternative: \'SLOWCYCLE_D\'\nassign SLOWCYCLE = SLOWCYCLE_D[3];\n       ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210918583/boards/tf530r3/tf530r3_bus_top.v:77: Cannot find file containing module: \'bus_top\'\nbus_top BUSTOP(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210918583/boards/tf530r3,data/full_repos/permissive/210918583/bus_top\n             data/full_repos/permissive/210918583/boards/tf530r3,data/full_repos/permissive/210918583/bus_top.v\n             data/full_repos/permissive/210918583/boards/tf530r3,data/full_repos/permissive/210918583/bus_top.sv\n             bus_top\n             bus_top.v\n             bus_top.sv\n             obj_dir/bus_top\n             obj_dir/bus_top.v\n             obj_dir/bus_top.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module tf530r3_bus_top(

           input 	CLKCPU,
           input 	CLK7M,

           output HALT,
           output RESET,

           input 	BG20,
           input 	AS20,
           input 	DS20,
           input 	RW20,
           output 	RW,


           input [2:0] 	FC,
           input [1:0] 	SIZ,

           input [23:0] A,

           input 	BGACK,
           input 	VPA,
           input 	DTACK,
           output    INT2,

           output 	BG,
           output 	LDS,
           output 	UDS,
           output 	VMA,
           output 	E,
           output 	AS,
           output 	BERR,

           output   OVR,
           input 	IDEWAIT,
           input 	INTCYCLE,

           output [1:0] DSACK,
           output 	AVEC,
           output 	CPCS,
           input 	CPSENSE,

           output [2:1] IPL,

           output 	IOR,
           output 	IOW,
           output [1:0] IDECS
       );

wire [23:0] ADDRESS_MAP;

assign ADDRESS_MAP[0] = A[0];
assign ADDRESS_MAP[23:15] = {A[23:15]};
assign ADDRESS_MAP[13:12] = {A[13:12]};

bus_top BUSTOP(

    .CLKCPU     ( CLKCPU        ), 
    .CLK7M      ( CLK7M         ),

    .INTCYCLE   ( INTCYCLE      ),
    .SLOWCYCLE  ( SLOWCYCLE     ),
    .IDEWAIT    ( IDEWAIT       ),
    
    .CPSENSE    ( CPSENSE       ), 
    .CPCS       ( CPCS          ),

    .BG20       ( BG20          ),
    .BG         ( BG            ),
    .BGACK      ( BGACK         ),

    .AS20       ( AS20          ), 
    .DS20       ( DS20          ), 
    .RW20       ( RW20          ), 
    .DSACK1     ( DSACK[1]      ), 
    .AVEC       ( AVEC          ),

    .AS         ( AS            ), 
    .RW         ( RW            ),
    .LDS        ( LDS           ), 
    .UDS        ( UDS           ), 
    .FC         ( FC            ), 

    .INT2       ( 1'b1          ),
    .SIZ        ( SIZ           ),

    .A          ( ADDRESS_MAP   ), 
	       
    .VPA        ( VPA           ), 
    .DTACK      ( DTACK         ), 

    .VMA        ( VMA           ), 
    .E          ( E             ), 
    .BERR       ( BERR          ), 

    .IOR        ( IOR           ),
    .IOW        ( IOW           ),
    .IDECS      ( IDECS         )
);


assign DSACK[0] = 1'bz;
assign RESET = 1'bz;
assign HALT = 1'bz;
assign OVR = 1'bz;
assign INT2 = 1'bz;
assign IPL[2:1] = {2'bzz};
       
reg [3:0] SLOWCYCLE_D;

always @(posedge CLK7M or posedge AS20) begin 

    if (AS20 == 1'b1) begin
    
        SLOWCYCLE_D <= 4'b1111;

    end else begin 

        SLOWCYCLE_D <= {SLOWCYCLE_D[2:0], INTCYCLE};

    end

end

assign SLOWCYCLE = SLOWCYCLE_D[3];
      
endmodule
module tf530r3_bus_top(

           input 	CLKCPU,
           input 	CLK7M,

           output HALT,
           output RESET,

           input 	BG20,
           input 	AS20,
           input 	DS20,
           input 	RW20,
           output 	RW,


           input [2:0] 	FC,
           input [1:0] 	SIZ,

           input [23:0] A,

           input 	BGACK,
           input 	VPA,
           input 	DTACK,
           output    INT2,

           output 	BG,
           output 	LDS,
           output 	UDS,
           output 	VMA,
           output 	E,
           output 	AS,
           output 	BERR,

           output   OVR,
           input 	IDEWAIT,
           input 	INTCYCLE,

           output [1:0] DSACK,
           output 	AVEC,
           output 	CPCS,
           input 	CPSENSE,

           output [2:1] IPL,

           output 	IOR,
           output 	IOW,
           output [1:0] IDECS
       );


wire [23:0] ADDRESS_MAP;

assign ADDRESS_MAP[0] = A[0];
assign ADDRESS_MAP[23:15] = {A[23:15]};
assign ADDRESS_MAP[13:12] = {A[13:12]};

bus_top BUSTOP(

    .CLKCPU     ( CLKCPU        ), 
    .CLK7M      ( CLK7M         ),

    .INTCYCLE   ( INTCYCLE      ),
    .SLOWCYCLE  ( SLOWCYCLE     ),
    .IDEWAIT    ( IDEWAIT       ),
    
    .CPSENSE    ( CPSENSE       ), 
    .CPCS       ( CPCS          ),

    .BG20       ( BG20          ),
    .BG         ( BG            ),
    .BGACK      ( BGACK         ),

    .AS20       ( AS20          ), 
    .DS20       ( DS20          ), 
    .RW20       ( RW20          ), 
    .DSACK1     ( DSACK[1]      ), 
    .AVEC       ( AVEC          ),

    .AS         ( AS            ), 
    .RW         ( RW            ),
    .LDS        ( LDS           ), 
    .UDS        ( UDS           ), 
    .FC         ( FC            ), 

    .INT2       ( 1'b1          ),
    .SIZ        ( SIZ           ),

    .A          ( ADDRESS_MAP   ), 
	       
    .VPA        ( VPA           ), 
    .DTACK      ( DTACK         ), 

    .VMA        ( VMA           ), 
    .E          ( E             ), 
    .BERR       ( BERR          ), 

    .IOR        ( IOR           ),
    .IOW        ( IOW           ),
    .IDECS      ( IDECS         )
);


assign DSACK[0] = 1'bz;
assign RESET = 1'bz;
assign HALT = 1'bz;
assign OVR = 1'bz;
assign INT2 = 1'bz;
assign IPL[2:1] = {2'bzz};
       
reg [3:0] SLOWCYCLE_D;

always @(posedge CLK7M or posedge AS20) begin 

    if (AS20 == 1'b1) begin
    
        SLOWCYCLE_D <= 4'b1111;

    end else begin 

        SLOWCYCLE_D <= {SLOWCYCLE_D[2:0], INTCYCLE};

    end

end

assign SLOWCYCLE = SLOWCYCLE_D[3];
      
endmodule