data/full_repos/permissive/129155059/06-fsm/tester.v
 line:47: before: "("
1: b'%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:1: Cannot find include file: definitions.v\n`include "definitions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/06-fsm,data/full_repos/permissive/129155059/definitions.v\n             data/full_repos/permissive/129155059/06-fsm,data/full_repos/permissive/129155059/definitions.v.v\n             data/full_repos/permissive/129155059/06-fsm,data/full_repos/permissive/129155059/definitions.v.sv\n             definitions.v\n             definitions.v.v\n             definitions.v.sv\n             obj_dir/definitions.v\n             obj_dir/definitions.v.v\n             obj_dir/definitions.v.sv\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:22: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("fsm.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:23: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1, tester);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:24: Unsupported or unknown PLI call: $monitor\n      $monitor("\\nAt time %t\\ntop_lim_cond = %h, top_lim_synth = %h, top_lim_synth_delay = %h\\nbott_lim_cond = %h, bott_lim_synth = %h, bott_lim_synth_delay = %h\\nestado_cond = %h, prox_estado_cond = %h, estado_synth = %h, prox_estado_synth = %h, estado_synth_delay = %h, prox_estado_synth_delay = %h\\n",\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/06-fsm/tester.v:34: Unsupported: Ignoring delay on this delayed statement.\n      repeat(2) #100 CLK = ~CLK;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/06-fsm/tester.v:37: Unsupported: Ignoring delay on this delayed statement.\n      forever #100 CLK = ~CLK;\n              ^\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:41: syntax error, unexpected \'@\'\n      @(negedge halt);\n      ^\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:43: syntax error, unexpected \'@\'\n      repeat(6) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:45: syntax error, unexpected \'@\'\n      repeat(6) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:48: syntax error, unexpected \'@\'\n      repeat(6) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:51: syntax error, unexpected \'@\'\n      repeat(6) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:53: syntax error, unexpected \'@\'\n      repeat(6) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:56: syntax error, unexpected \'@\'\n      repeat(6) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:59: syntax error, unexpected \'@\'\n      repeat(6) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/06-fsm/tester.v:63: syntax error, unexpected \'@\'\n      repeat(6) @(posedge CLK);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/06-fsm/tester.v:65: Unsupported: Ignoring delay on this delayed statement.\n      #10 $finish;\n      ^\n%Error: Exiting due to 13 error(s), 3 warning(s)\n'
module tester(  output reg CLK,
                output reg go_down,
                output reg go_up,
                output reg halt,
                output reg reset,
                input      top_lim_cond,
                input      bott_lim_cond,
                input      top_lim_synth,
                input      bott_lim_synth,
                input      top_lim_synth_delay,
                input      bott_lim_synth_delay,
                input [4:0] estado_cond,
                input [4:0] prox_estado_cond,
                input [4:0] estado_synth,
                input [4:0] prox_estado_synth,
                input [4:0] estado_synth_delay,
                input [4:0] prox_estado_synth_delay
                );

   initial begin
      $dumpfile("fsm.vcd");
      $dumpvars(1, tester);
      $monitor("\nAt time %t\ntop_lim_cond = %h, top_lim_synth = %h, top_lim_synth_delay = %h\nbott_lim_cond = %h, bott_lim_synth = %h, bott_lim_synth_delay = %h\nestado_cond = %h, prox_estado_cond = %h, estado_synth = %h, prox_estado_synth = %h, estado_synth_delay = %h, prox_estado_synth_delay = %h\n",
               $time, top_lim_cond, top_lim_synth, top_lim_synth_delay, bott_lim_cond, bott_lim_synth, bott_lim_synth_delay, estado_cond, prox_estado_cond, estado_synth, prox_estado_synth, estado_synth_delay, prox_estado_synth_delay);
   end

   initial begin
      reset = 1'b0;
      CLK = 1'b0;
      go_down = 1'b0;
      go_up = 1'b0;
      halt = 1'b1;
      repeat(2) #100 CLK = ~CLK;
      reset = 1'b1;
      halt = 1'b0;
      forever #100 CLK = ~CLK;
   end

    initial begin
      @(negedge halt);
      go_down = 1'b1;
      repeat(6) @(posedge CLK);
      go_down = 1'b1;
      repeat(6) @(posedge CLK);
      go_down = 1'b0;
      go_up = 1'b1;
      repeat(6) @(posedge CLK);
      go_down = 1'b1;
      go_up = 1'b0;
      repeat(6) @(posedge CLK);
      halt = 1'b1;
      repeat(6) @(posedge CLK);
      go_down = 1'b0;
      go_up = 1'b1;
      repeat(6) @(posedge CLK);
      go_down = 1'b1;
      go_up = 1'b0;
      repeat(6) @(posedge CLK);
      halt = 1'b0;
      go_down = 1'b1;
      go_up = 1'b1;
      repeat(6) @(posedge CLK);
      halt = 1'b1;
      #10 $finish;
   end

endmodule
module tester(  output reg CLK,
                output reg go_down,
                output reg go_up,
                output reg halt,
                output reg reset,
                input      top_lim_cond,
                input      bott_lim_cond,
                input      top_lim_synth,
                input      bott_lim_synth,
                input      top_lim_synth_delay,
                input      bott_lim_synth_delay,
                input [4:0] estado_cond,
                input [4:0] prox_estado_cond,
                input [4:0] estado_synth,
                input [4:0] prox_estado_synth,
                input [4:0] estado_synth_delay,
                input [4:0] prox_estado_synth_delay
                );


   initial begin
      $dumpfile("fsm.vcd");
      $dumpvars(1, tester);
      $monitor("\nAt time %t\ntop_lim_cond = %h, top_lim_synth = %h, top_lim_synth_delay = %h\nbott_lim_cond = %h, bott_lim_synth = %h, bott_lim_synth_delay = %h\nestado_cond = %h, prox_estado_cond = %h, estado_synth = %h, prox_estado_synth = %h, estado_synth_delay = %h, prox_estado_synth_delay = %h\n",
               $time, top_lim_cond, top_lim_synth, top_lim_synth_delay, bott_lim_cond, bott_lim_synth, bott_lim_synth_delay, estado_cond, prox_estado_cond, estado_synth, prox_estado_synth, estado_synth_delay, prox_estado_synth_delay);
   end

   initial begin
      reset = 1'b0;
      CLK = 1'b0;
      go_down = 1'b0;
      go_up = 1'b0;
      halt = 1'b1;
      repeat(2) #100 CLK = ~CLK;
      reset = 1'b1;
      halt = 1'b0;
      forever #100 CLK = ~CLK;
   end

    initial begin
      @(negedge halt);
      go_down = 1'b1;
      repeat(6) @(posedge CLK);
      go_down = 1'b1;
      repeat(6) @(posedge CLK);
      go_down = 1'b0;
      go_up = 1'b1;
      repeat(6) @(posedge CLK);
      go_down = 1'b1;
      go_up = 1'b0;
      repeat(6) @(posedge CLK);
      halt = 1'b1;
      repeat(6) @(posedge CLK);
      go_down = 1'b0;
      go_up = 1'b1;
      repeat(6) @(posedge CLK);
      go_down = 1'b1;
      go_up = 1'b0;
      repeat(6) @(posedge CLK);
      halt = 1'b0;
      go_down = 1'b1;
      go_up = 1'b1;
      repeat(6) @(posedge CLK);
      halt = 1'b1;
      #10 $finish;
   end

endmodule