data/full_repos/permissive/146618947/clase3_onoffswitch/switch_tester.v
 line:19: before: "@"
1: b'%Error: data/full_repos/permissive/146618947/clase3_onoffswitch/switch_tester.v:13: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("switch.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/clase3_onoffswitch/switch_tester.v:14: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/clase3_onoffswitch/switch_tester.v:16: syntax error, unexpected \'@\'\n      @(posedge sClk);\n      ^\n%Error: data/full_repos/permissive/146618947/clase3_onoffswitch/switch_tester.v:19: syntax error, unexpected \'@\'\n      #10 @(posedge sClk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/clase3_onoffswitch/switch_tester.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #10 @(posedge sClk);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/146618947/clase3_onoffswitch/switch_tester.v:22: syntax error, unexpected \'@\'\n      #20 @(posedge sClk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/clase3_onoffswitch/switch_tester.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #20 @(posedge sClk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/clase3_onoffswitch/switch_tester.v:34: Unsupported: Ignoring delay on this delayed statement.\n   always #2 sClk <= ~sClk;\n          ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module switch_tester (
               output reg sButton,
               output reg sReset,
               output reg sClk,
               input      sLuz_conductual,
               input      sLuz_estructural
               );

   reg                   estructural, conductual;


   initial begin
      $dumpfile("switch.vcd");
      $dumpvars;
      {sButton, sReset} <= 2'b0;
      @(posedge sClk);
      sButton <= 1'b0;
      sReset <= 1'b1;
      #10 @(posedge sClk);
      sReset <= 1'b0;
      sButton <= 1'b1;
      #20 @(posedge sClk);
      sReset <= 1'b0;
      $finish;
   end

   always @ (posedge sClk) begin
      estructural <= sLuz_estructural;
      conductual <= sLuz_conductual;
   end

   initial sClk <= 0;

   always #2 sClk <= ~sClk;

   always @ (posedge sClk) begin
      if (!sReset) begin
         if (conductual == estructural) begin
            $display("MIEDO_PA");
            end
      end
   end


endmodule
module switch_tester (
               output reg sButton,
               output reg sReset,
               output reg sClk,
               input      sLuz_conductual,
               input      sLuz_estructural
               );


   reg                   estructural, conductual;


   initial begin
      $dumpfile("switch.vcd");
      $dumpvars;
      {sButton, sReset} <= 2'b0;
      @(posedge sClk);
      sButton <= 1'b0;
      sReset <= 1'b1;
      #10 @(posedge sClk);
      sReset <= 1'b0;
      sButton <= 1'b1;
      #20 @(posedge sClk);
      sReset <= 1'b0;
      $finish;
   end

   always @ (posedge sClk) begin
      estructural <= sLuz_estructural;
      conductual <= sLuz_conductual;
   end

   initial sClk <= 0;

   always #2 sClk <= ~sClk;

   always @ (posedge sClk) begin
      if (!sReset) begin
         if (conductual == estructural) begin
            $display("MIEDO_PA");
            end
      end
   end


endmodule