data/full_repos/permissive/201770113/test/i2s_interface_tb.v
 line:40: before: "begin"
1: b'%Error: data/full_repos/permissive/201770113/test/i2s_interface_tb.v:15: syntax error, unexpected interface, expecting IDENTIFIER\ni2s_interface interface (.BCLK(clk),    \n              ^~~~~~~~~\n%Error: data/full_repos/permissive/201770113/test/i2s_interface_tb.v:23: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n    file_handle = $fopen("sobel_module_tb_out.log");  \n                  ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/201770113/test/i2s_interface_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #200 \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/201770113/test/i2s_interface_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\nalways #1\n       ^\n%Error: data/full_repos/permissive/201770113/test/i2s_interface_tb.v:46: Unsupported or unknown PLI call: $urandom\n    data <= $urandom;\n            ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/201770113/test/i2s_interface_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #100000\n  ^\n%Error: data/full_repos/permissive/201770113/test/i2s_interface_tb.v:67: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("i2s_interface_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/201770113/test/i2s_interface_tb.v:68: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, i2s_interface_tb);\n  ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 3 warning(s)\n'
module i2s_interface_tb ();

integer file_handle;

reg clk;
reg lr_select;
reg data;
integer lr_counter;
integer sample_rate_pot;

i2s_interface interface (.BCLK(clk),
                         .LRCLK(lr_select),
                         .SDATA(data),
                         .SAMPLE_RATE_POT(sample_rate_pot));



initial begin
    file_handle = $fopen("sobel_module_tb_out.log");
    $fdisplay(file_handle, "Outcome from Sobel Module tests\n");
  
    clk = 0;
    data = 0;
    lr_select = 0;
    lr_counter = 0;
    #200 
    sample_rate_pot = 2000;

    $display(file_handle, "Set up input signals.");
end




always #1
    begin
    clk = ~clk;
end

always @(posedge clk) begin

    data <= $urandom;
    lr_counter <= lr_counter + 1;

    if (lr_counter == 24) begin
        lr_select <= !lr_select;
        lr_counter <= 0;
    end
end




initial begin
  #100000
  $fclose(file_handle);
  $stop;
end



initial begin
  $dumpfile ("i2s_interface_tb.vcd");
  $dumpvars(0, i2s_interface_tb);
end

endmodule
module i2s_interface_tb ();


integer file_handle;

reg clk;
reg lr_select;
reg data;
integer lr_counter;
integer sample_rate_pot;

i2s_interface interface (.BCLK(clk),
                         .LRCLK(lr_select),
                         .SDATA(data),
                         .SAMPLE_RATE_POT(sample_rate_pot));



initial begin
    file_handle = $fopen("sobel_module_tb_out.log");
    $fdisplay(file_handle, "Outcome from Sobel Module tests\n");
  
    clk = 0;
    data = 0;
    lr_select = 0;
    lr_counter = 0;
    #200 
    sample_rate_pot = 2000;

    $display(file_handle, "Set up input signals.");
end




always #1
    begin
    clk = ~clk;
end

always @(posedge clk) begin

    data <= $urandom;
    lr_counter <= lr_counter + 1;

    if (lr_counter == 24) begin
        lr_select <= !lr_select;
        lr_counter <= 0;
    end
end




initial begin
  #100000
  $fclose(file_handle);
  $stop;
end



initial begin
  $dumpfile ("i2s_interface_tb.vcd");
  $dumpvars(0, i2s_interface_tb);
end

endmodule