data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v
1: b'%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:2: Cannot find include file: xdefs.vh\n`include "xdefs.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh.v\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh.sv\n             xdefs.vh\n             xdefs.vh.v\n             xdefs.vh.sv\n             obj_dir/xdefs.vh\n             obj_dir/xdefs.vh.v\n             obj_dir/xdefs.vh.sv\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:3: Cannot find include file: xprogdefs.vh\n`include "xprogdefs.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:4: Cannot find include file: xctrldefs.vh\n`include "xctrldefs.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:8: Define or directive not defined: \'`PROG_RAM_ADDR_W\'\n   input [`PROG_RAM_ADDR_W-1:0] pc,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:9: Define or directive not defined: \'`INSTR_W\'\n   output reg [`INSTR_W-1:0]    instruction,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:14: Define or directive not defined: \'`PROG_RAM_ADDR_W\'\n   input [`PROG_RAM_ADDR_W-1:0] data_addr,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:15: Define or directive not defined: \'`DATA_W\'\n   input [`DATA_W-1:0]        data_in,\n          ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:16: Define or directive not defined: \'`DATA_W\'\n   output [`DATA_W-1:0]        data_out,\n           ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:32: Define or directive not defined: \'`INSTR_W\'\n   reg [`INSTR_W-1:0]        mem [2**`PROG_RAM_ADDR_W-1:0];\n        ^~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:32: Define or directive not defined: \'`PROG_RAM_ADDR_W\'\n   reg [`INSTR_W-1:0]        mem [2**`PROG_RAM_ADDR_W-1:0];\n                                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:38: Define or directive not defined: \'`DATA_W\'\n   wire [`DATA_W-1:0]        data_in_int;\n         ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:41: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0]        data_out_int;\n        ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:44: Define or directive not defined: \'`PROG_RAM_ADDR_W\'\n   wire [`PROG_RAM_ADDR_W-1:0]       data_addr_int;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xprog_ram.v:73: Define or directive not defined: \'`PROG_RAM_ADDR_W\'\n      $readmemh("./program.hex",mem,0,2**`PROG_RAM_ADDR_W-1);\n                                         ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module xprog_ram (

		 input [`PROG_RAM_ADDR_W-1:0] pc,
		 output reg [`INSTR_W-1:0]    instruction,
	

		 input 			      data_sel,
		 input 			      data_we,
		 input [`PROG_RAM_ADDR_W-1:0] data_addr,
		 input [`DATA_W-1:0] 	      data_in,
		 output [`DATA_W-1:0] 	      data_out,
					    
`ifdef DMA_USE

		 input 			      dma_sel,
		 input 			      dma_we,
		 input [`PROG_ADDR_W-1:0]     dma_addr,
		 input [`DATA_W-1:0] 	      dma_data_in,
		 output [`DATA_W-1:0] 	      dma_data_out
`endif
		 input 			      clk
		 );




   reg [`INSTR_W-1:0] 			    mem [2**`PROG_RAM_ADDR_W-1:0];


   wire 				    instr_en;
   

   wire [`DATA_W-1:0] 			    data_in_int;


   reg [`DATA_W-1:0] 			    data_out_int;


   wire [`PROG_RAM_ADDR_W-1:0] 		    data_addr_int;


   wire 				    data_en_int;
   

   wire 				    data_we_int;
   
   

   assign instr_en = 1'b1;


`ifdef DMA_USE
   assign data_addr_int = (data_sel)? data_addr : dma_addr;
   assign data_we_int = (data_sel)? data_we : dma_we;
   assign data_in_int = (data_sel)? data_in : dma_data_in;
   assign dma_data_out = data_out_int;
   assign data_en_int = (data_sel)? data_sel : dma_sel;
`else
   assign data_addr_int = data_addr;
   assign data_we_int = data_we;
   assign data_in_int = data_in;
   assign data_en_int = data_sel;
`endif
   assign data_out = data_out_int;
   

   initial begin
      $readmemh("./program.hex",mem,0,2**`PROG_RAM_ADDR_W-1);
    end


   always @(posedge clk) begin			
      if (instr_en) begin
	 instruction <= mem[pc];
      end
   end
   

   always @(posedge clk) begin			
      if (data_en_int) begin
	 if (data_we_int)
           mem[data_addr_int] <= data_in_int;
	 data_out_int <= mem[data_addr_int];
      end
   end

endmodule
module xprog_ram (

		 input [`PROG_RAM_ADDR_W-1:0] pc,
		 output reg [`INSTR_W-1:0]    instruction,
	

		 input 			      data_sel,
		 input 			      data_we,
		 input [`PROG_RAM_ADDR_W-1:0] data_addr,
		 input [`DATA_W-1:0] 	      data_in,
		 output [`DATA_W-1:0] 	      data_out,
					    
`ifdef DMA_USE

		 input 			      dma_sel,
		 input 			      dma_we,
		 input [`PROG_ADDR_W-1:0]     dma_addr,
		 input [`DATA_W-1:0] 	      dma_data_in,
		 output [`DATA_W-1:0] 	      dma_data_out
`endif
		 input 			      clk
		 );





   reg [`INSTR_W-1:0] 			    mem [2**`PROG_RAM_ADDR_W-1:0];


   wire 				    instr_en;
   

   wire [`DATA_W-1:0] 			    data_in_int;


   reg [`DATA_W-1:0] 			    data_out_int;


   wire [`PROG_RAM_ADDR_W-1:0] 		    data_addr_int;


   wire 				    data_en_int;
   

   wire 				    data_we_int;
   
   

   assign instr_en = 1'b1;


`ifdef DMA_USE
   assign data_addr_int = (data_sel)? data_addr : dma_addr;
   assign data_we_int = (data_sel)? data_we : dma_we;
   assign data_in_int = (data_sel)? data_in : dma_data_in;
   assign dma_data_out = data_out_int;
   assign data_en_int = (data_sel)? data_sel : dma_sel;
`else
   assign data_addr_int = data_addr;
   assign data_we_int = data_we;
   assign data_in_int = data_in;
   assign data_en_int = data_sel;
`endif
   assign data_out = data_out_int;
   

   initial begin
      $readmemh("./program.hex",mem,0,2**`PROG_RAM_ADDR_W-1);
    end


   always @(posedge clk) begin			
      if (instr_en) begin
	 instruction <= mem[pc];
      end
   end
   

   always @(posedge clk) begin			
      if (data_en_int) begin
	 if (data_we_int)
           mem[data_addr_int] <= data_in_int;
	 data_out_int <= mem[data_addr_int];
      end
   end

endmodule