data/full_repos/permissive/129447112/pratica2/contador.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/129447112/pratica2/contador.v:14: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'contador\'\nmodule contador(Clear, Clock, Q);\n       ^~~~~~~~\n                                                                              : ... Top module \'regn\'\nmodule regn(R, Rin, Clock, Q);\n       ^~~~\n                                                                              : ... Top module \'Pratica2\'\nmodule Pratica2(SW, LEDG);\n       ^~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/129447112/pratica2/contador.v:30: Little bit endian vector: MSB < LSB of bit range: 0:7\n output [0:7] Y;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/129447112/pratica2/contador.v:36: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh989680\' generates 32 or 24 bits.\n                                                                           : ... In instance Pratica2.conversor\n     000: Y = 10000000;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/129447112/pratica2/contador.v:37: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shf4240\' generates 32 or 20 bits.\n                                                                           : ... In instance Pratica2.conversor\n     001: Y = 01000000;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/129447112/pratica2/contador.v:38: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh186a0\' generates 32 or 17 bits.\n                                                                           : ... In instance Pratica2.conversor\n     010: Y = 00100000;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/129447112/pratica2/contador.v:39: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh2710\' generates 32 or 14 bits.\n                                                                           : ... In instance Pratica2.conversor\n     011: Y = 00010000;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/129447112/pratica2/contador.v:40: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh3e8\' generates 32 or 10 bits.\n                                                                           : ... In instance Pratica2.conversor\n     100: Y = 00001000;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/129447112/pratica2/contador.v:35: Operator CASE expects 32 or 7 bits on the Case expression, but Case expression\'s VARREF \'W\' generates 3 bits.\n                                                                           : ... In instance Pratica2.conversor\n    case (W)\n    ^~~~\n%Error: Exiting due to 8 warning(s)\n'
module contador(Clear, Clock, Q);
	input Clear, Clock;
	output [1:0] Q;
	reg [1:0] Q;

	always @(posedge Clock)
		if (Clear)
			Q <= 0;
		else
			Q <= Q + 1;
			
endmodule
module contador(Clear, Clock, Q);

	input Clear, Clock;
	output [1:0] Q;
	reg [1:0] Q;

	always @(posedge Clock)
		if (Clear)
			Q <= 0;
		else
			Q <= Q + 1;
			
endmodule