data/full_repos/permissive/210844779/lab6/6.3/xor.v
 line:7: before: "4"
data/verilator_xmls/93831f1a-e310-47f9-945e-9b3841ce0977.xml
module xor_1(a,b,c);
  input a,b;
  output c;
  
  wire temp1,temp2;
  
  and #4 u0(temp1,a,~b);
  and #4 u1(temp2,~a,b);
  or #3 u2(c,temp1,temp2);
  
endmodule
module xor_1(a,b,c);

  input a,b;
  output c;
  
  wire temp1,temp2;
  
  and #4 u0(temp1,a,~b);
  and #4 u1(temp2,~a,b);
  or #3 u2(c,temp1,temp2);
  
endmodule