data/full_repos/permissive/117436613/testbench/lsu_test.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/117436613/testbench/lsu_test.sv:1: Cannot find include file: mmix_defs.sv\n`include "mmix_defs.sv" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117436613/testbench,data/full_repos/permissive/117436613/mmix_defs.sv\n             data/full_repos/permissive/117436613/testbench,data/full_repos/permissive/117436613/mmix_defs.sv.v\n             data/full_repos/permissive/117436613/testbench,data/full_repos/permissive/117436613/mmix_defs.sv.sv\n             mmix_defs.sv\n             mmix_defs.sv.v\n             mmix_defs.sv.sv\n             obj_dir/mmix_defs.sv\n             obj_dir/mmix_defs.sv.v\n             obj_dir/mmix_defs.sv.sv\n%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/lsu_test.sv:69: Unsupported: Ignoring delay on this delayed statement.\n always #20\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/lsu_test.sv:80: Unsupported: Ignoring delay on this delayed statement.\n  #80 reset_n <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/lsu_test.sv:81: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/lsu_test.sv:83: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/lsu_test.sv:89: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/lsu_test.sv:93: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/lsu_test.sv:96: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/lsu_test.sv:98: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/lsu_test.sv:102: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/117436613/testbench/lsu_test.sv:108: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/lsu_test.sv:117: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/lsu_test.sv:119: Too many digits for 32 bit number: \'h200000000000ffff\n  mem_readdata <= \'h200000000000ffff;\n                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117436613/testbench/lsu_test.sv:121: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 11 error(s), 3 warning(s)\n'
module lsu_test(
	);

	logic			clk;
	logic			reset_n;

	logic		enable;
	
	control			data;
	
	logic[63:0]		y, z, b;
	logic				y_valid, z_valid, b_valid;
	

	logic			gregwe;
	logic			lregwe;
	logic[7:0]		regwa;
	logic[63:0]	regwd;
	

	logic[63:0]	mem_address;
	logic[1:0]		mem_datasize;
	logic			mem_read;
	logic[63:0]	mem_readdata;
	logic			mem_write;
	logic[63:0]	mem_writedata;
	logic			mem_done;
	

	logic        we_G;
	logic[7:0]		new_G;
	logic[18:0]	interrupt;
	logic			done;
	
	ld_st_unit dut(
		.clk,
		.reset_n,
		.enable,
		
		.data,
		
		.y, .z, .b,
		.y_valid, .z_valid, .b_valid,
		

		.gregwe,
		.lregwe,
		.regwa,
		.regwd,
		

		.mem_address,
		.mem_datasize,
		.mem_read,
		.mem_readdata,
		.mem_write,
		.mem_writedata,
		.mem_done,
		

		.we_G,
		.new_G,
		.interrupt,
		.done
		);
		
	always #20
		clk <= ~clk;
	
	initial begin
		clk <= 0;
		reset_n <= 0;
		enable <= 0;
		mem_done <= 0;
		y_valid <= 0;
		z_valid <= 0;
		b_valid <= 0;
		#80 reset_n <= 1;
		#40;

		@(posedge clk);
		enable <= 1;
		data.i <= incgamma;
		y <= 10;
		z <= 32;
		y_valid <= 1;
		@(posedge clk);
		b <= 'h1234;
		z_valid <= 1;
		b_valid <= 1;
		@(posedge clk);
		enable <= 0;
		
		@(posedge clk);
		mem_done <= 1;
		@(posedge clk);
		mem_done <= 0;

		while (done == 0)
			@(posedge clk);
			
		y_valid <= 0;
		z_valid <= 0;
		b_valid <= 0;
		
		@(posedge clk);
		data.i <= unsav;
		data.op <= UNSAVE;
		data.xx <= 0;
		enable <= 1;
		y <= 1;
		z <= 16;
		y_valid <= 1;
		z_valid <= 1;
		@(posedge clk);
		mem_done <= 1;
		mem_readdata <= 'h200000000000ffff;
		enable <= 0;
		@(posedge clk);
		mem_done <= 0;
		

	end
	
endmodule
module lsu_test(
	);


	logic			clk;
	logic			reset_n;

	logic		enable;
	
	control			data;
	
	logic[63:0]		y, z, b;
	logic				y_valid, z_valid, b_valid;
	

	logic			gregwe;
	logic			lregwe;
	logic[7:0]		regwa;
	logic[63:0]	regwd;
	

	logic[63:0]	mem_address;
	logic[1:0]		mem_datasize;
	logic			mem_read;
	logic[63:0]	mem_readdata;
	logic			mem_write;
	logic[63:0]	mem_writedata;
	logic			mem_done;
	

	logic        we_G;
	logic[7:0]		new_G;
	logic[18:0]	interrupt;
	logic			done;
	
	ld_st_unit dut(
		.clk,
		.reset_n,
		.enable,
		
		.data,
		
		.y, .z, .b,
		.y_valid, .z_valid, .b_valid,
		

		.gregwe,
		.lregwe,
		.regwa,
		.regwd,
		

		.mem_address,
		.mem_datasize,
		.mem_read,
		.mem_readdata,
		.mem_write,
		.mem_writedata,
		.mem_done,
		

		.we_G,
		.new_G,
		.interrupt,
		.done
		);
		
	always #20
		clk <= ~clk;
	
	initial begin
		clk <= 0;
		reset_n <= 0;
		enable <= 0;
		mem_done <= 0;
		y_valid <= 0;
		z_valid <= 0;
		b_valid <= 0;
		#80 reset_n <= 1;
		#40;

		@(posedge clk);
		enable <= 1;
		data.i <= incgamma;
		y <= 10;
		z <= 32;
		y_valid <= 1;
		@(posedge clk);
		b <= 'h1234;
		z_valid <= 1;
		b_valid <= 1;
		@(posedge clk);
		enable <= 0;
		
		@(posedge clk);
		mem_done <= 1;
		@(posedge clk);
		mem_done <= 0;

		while (done == 0)
			@(posedge clk);
			
		y_valid <= 0;
		z_valid <= 0;
		b_valid <= 0;
		
		@(posedge clk);
		data.i <= unsav;
		data.op <= UNSAVE;
		data.xx <= 0;
		enable <= 1;
		y <= 1;
		z <= 16;
		y_valid <= 1;
		z_valid <= 1;
		@(posedge clk);
		mem_done <= 1;
		mem_readdata <= 'h200000000000ffff;
		enable <= 0;
		@(posedge clk);
		mem_done <= 0;
		

	end
	
endmodule