data/full_repos/permissive/16552133/src/verilog/memory_address_register.v
data/verilator_xmls/49a9c145-eb03-4e67-83e7-42520fc1c51d.xml
module memory_address_register(clk,in,out,ls);
	input clk,ls;
	input [5:0]in;
	output reg [5:0]out;
	
	initial begin out = 6'bZZZZZZ; end
	
	always @(posedge clk)
	begin
		if(ls) begin

			out <= in;
		end
	end
endmodule
module memory_address_register(clk,in,out,ls);

	input clk,ls;
	input [5:0]in;
	output reg [5:0]out;
	
	initial begin out = 6'bZZZZZZ; end
	
	always @(posedge clk)
	begin
		if(ls) begin

			out <= in;
		end
	end
endmodule