data/full_repos/permissive/174263347/scanconv/hdl/vga.v
data/verilator_xmls/9ad79bcc-ffa1-4845-8d9c-2c0bd4cddaf1.xml
module vga ( clk, reset, video, ivsync, ihsync, dVga, aVga, wrVga, wrVgaReq, notVga, lines350 );
    

    input   clk;
    input   reset;
    input   ivsync;
    input	ihsync;
	output  wrVga;
    input   wrVgaReq;
    input   video;
    output  [7:0] dVga;
    output  [15:0] aVga;
	output	notVga;
	output	lines350;


    reg     [6:0] h;
    reg     [8:0] v;
    reg     [3:0] pixel;
    reg     [7:0] shifter;
	reg		notVgaSig;
	reg		lines350Sig;





wire hsync;
wire vsync;

myFAILINGEX vFrontExt(clk, reset, 1'b1, ivsync, vsync);
myFAILINGEX hFrontExt(clk, reset, 1'b1, ihsync, hsync);





always @ ( posedge clk or posedge hsync)        
begin
    if (hsync)
        pixel <= 0;
    else 
        pixel <= pixel + 1;
end

reg pixel8;

always @ ( posedge clk or posedge hsync)
begin
    if (hsync)                                  
    	pixel8 <= 0;                            
    else 
		pixel8 <= (pixel == 6);
end








reg [2:0] hdelay;
reg line;

always @ ( posedge clk or posedge reset)
begin
    if (reset)
        hdelay <= 3'd5;
    else if (hsync)
            hdelay <= 3'd5;
    else if (pixel8)
        if (hdelay != 3'd0)
            hdelay <= hdelay - 1;
end







reg [4:0] vdelay;
reg frame;

always @ ( posedge clk or posedge reset)
begin
    if (reset)
        vdelay  <= 5'd25;
    else if (vsync)
        vdelay  <= 5'd25;
    else if (hsync)
        if (vdelay != 5'd00)
            vdelay <= vdelay - 1;
end





reg [2:0] nline;
wire	  skipline;

always @ ( posedge clk or posedge reset)
begin
    if (reset)
        nline   <= 3'b001;
	else if (vsync)		
        nline   <= 3'b001;
    else if (hsync)
		if (lines350)
			nline <= { nline[1], nline[0], nline[2] };
		else 
			nline <= ~nline;
end

assign skipline = nline[0];





always @ ( posedge clk or posedge reset)
begin
    if (reset)
        line    <= 1'b0;
    else if (hsync)
        line    <= 1'b0;
    else if (pixel8)
        if (hdelay == 3'd0)
            line    <= skipline;
end

always @ ( posedge clk or posedge reset)
begin
    if (reset)
        frame   <= 1'b0;
    else if (vsync)
        frame   <= 1'b0;
    else if (hsync)
        if (vdelay == 5'b00000)
            frame <= 1'b1;
end

assign wrVga = pixel8 & line & frame;




     
always @ (posedge clk or posedge reset)
begin
    if (reset)
        h <= 0;
    else if (hsync)
        h <= 0;
    else if (wrVgaReq)
        if( h != 7'b1111111 )
        	h <= h + 1;
end

assign aVga[6:0] = h;

always @ (posedge clk) 
begin
	if (hsync)
	    if (h > 80)
	        notVgaSig <= 0;
		else
        	notVgaSig <= 1;
end

assign notVga = notVgaSig;





always @ (posedge clk or posedge reset)
begin
    if (reset)
        v <= 0;
    else if (vsync)
        v <= 0;
    else if (hsync)
        if (frame & ~skipline)
    		if (v != 9'b111111111)
            	v <= v + 1;
end

assign aVga[15:7] = v;

always @ (posedge clk)
begin
	if (hsync)
	    if (v < 500)
	        lines350Sig <= 1;
		else
	        lines350Sig <= 0;
end

assign lines350 = lines350Sig;





always @ ( posedge clk )
begin
    shifter <= { shifter[6:0], video };
end

assign dVga = shifter;

endmodule
module vga ( clk, reset, video, ivsync, ihsync, dVga, aVga, wrVga, wrVgaReq, notVga, lines350 );

    

    input   clk;
    input   reset;
    input   ivsync;
    input	ihsync;
	output  wrVga;
    input   wrVgaReq;
    input   video;
    output  [7:0] dVga;
    output  [15:0] aVga;
	output	notVga;
	output	lines350;


    reg     [6:0] h;
    reg     [8:0] v;
    reg     [3:0] pixel;
    reg     [7:0] shifter;
	reg		notVgaSig;
	reg		lines350Sig;





wire hsync;
wire vsync;

myFAILINGEX vFrontExt(clk, reset, 1'b1, ivsync, vsync);
myFAILINGEX hFrontExt(clk, reset, 1'b1, ihsync, hsync);





always @ ( posedge clk or posedge hsync)        
begin
    if (hsync)
        pixel <= 0;
    else 
        pixel <= pixel + 1;
end

reg pixel8;

always @ ( posedge clk or posedge hsync)
begin
    if (hsync)                                  
    	pixel8 <= 0;                            
    else 
		pixel8 <= (pixel == 6);
end








reg [2:0] hdelay;
reg line;

always @ ( posedge clk or posedge reset)
begin
    if (reset)
        hdelay <= 3'd5;
    else if (hsync)
            hdelay <= 3'd5;
    else if (pixel8)
        if (hdelay != 3'd0)
            hdelay <= hdelay - 1;
end







reg [4:0] vdelay;
reg frame;

always @ ( posedge clk or posedge reset)
begin
    if (reset)
        vdelay  <= 5'd25;
    else if (vsync)
        vdelay  <= 5'd25;
    else if (hsync)
        if (vdelay != 5'd00)
            vdelay <= vdelay - 1;
end





reg [2:0] nline;
wire	  skipline;

always @ ( posedge clk or posedge reset)
begin
    if (reset)
        nline   <= 3'b001;
	else if (vsync)		
        nline   <= 3'b001;
    else if (hsync)
		if (lines350)
			nline <= { nline[1], nline[0], nline[2] };
		else 
			nline <= ~nline;
end

assign skipline = nline[0];





always @ ( posedge clk or posedge reset)
begin
    if (reset)
        line    <= 1'b0;
    else if (hsync)
        line    <= 1'b0;
    else if (pixel8)
        if (hdelay == 3'd0)
            line    <= skipline;
end

always @ ( posedge clk or posedge reset)
begin
    if (reset)
        frame   <= 1'b0;
    else if (vsync)
        frame   <= 1'b0;
    else if (hsync)
        if (vdelay == 5'b00000)
            frame <= 1'b1;
end

assign wrVga = pixel8 & line & frame;




     
always @ (posedge clk or posedge reset)
begin
    if (reset)
        h <= 0;
    else if (hsync)
        h <= 0;
    else if (wrVgaReq)
        if( h != 7'b1111111 )
        	h <= h + 1;
end

assign aVga[6:0] = h;

always @ (posedge clk) 
begin
	if (hsync)
	    if (h > 80)
	        notVgaSig <= 0;
		else
        	notVgaSig <= 1;
end

assign notVga = notVgaSig;





always @ (posedge clk or posedge reset)
begin
    if (reset)
        v <= 0;
    else if (vsync)
        v <= 0;
    else if (hsync)
        if (frame & ~skipline)
    		if (v != 9'b111111111)
            	v <= v + 1;
end

assign aVga[15:7] = v;

always @ (posedge clk)
begin
	if (hsync)
	    if (v < 500)
	        lines350Sig <= 1;
		else
	        lines350Sig <= 0;
end

assign lines350 = lines350Sig;





always @ ( posedge clk )
begin
    shifter <= { shifter[6:0], video };
end

assign dVga = shifter;

endmodule