data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v
None: at end of input
1: b'%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:2: Cannot find include file: ./modulos/bitHolder.v\n  `include "./modulos/bitHolder.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/bitHolder.v\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/bitHolder.v.v\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/bitHolder.v.sv\n             ./modulos/bitHolder.v\n             ./modulos/bitHolder.v.v\n             ./modulos/bitHolder.v.sv\n             obj_dir/./modulos/bitHolder.v\n             obj_dir/./modulos/bitHolder.v.v\n             obj_dir/./modulos/bitHolder.v.sv\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:5: Cannot find include file: ../tarea3/modulos/notGate.v\n  `include "../tarea3/modulos/notGate.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:8: Cannot find include file: ../tarea3/modulos/norGate.v\n  `include "../tarea3/modulos/norGate.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:11: Cannot find include file: ../tarea3/modulos/mux.v\n  `include "../tarea3/modulos/mux.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:14: Cannot find include file: ../tarea3/modulos/ffD.v\n  `include "../tarea3/modulos/ffD.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:17: Cannot find include file: ./modulos/ternarioDoble.v\n  `include "./modulos/ternarioDoble.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:45: Unsupported: Ignoring delay on this delayed statement.\n  initial # 50 clk = 0;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:53: Unsupported: Ignoring delay on this delayed statement.\n  always # 37 clk = ~clk;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:67: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:70: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:78: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:80: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:88: Unsupported: Ignoring delay on this delayed statement.\n    # 70\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:92: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:99: Unsupported: Ignoring delay on this delayed statement.\n    # 70\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:101: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:110: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:117: Unsupported: Ignoring delay on this delayed statement.\n    # 70\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:119: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:127: Unsupported: Ignoring delay on this delayed statement.\n    # 70\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:131: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:138: Unsupported: Ignoring delay on this delayed statement.\n    # 70\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:140: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:149: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:156: Unsupported: Ignoring delay on this delayed statement.\n    # 70\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:158: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:166: Unsupported: Ignoring delay on this delayed statement.\n    # 150;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:167: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:173: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./tests/testbitHolder.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:174: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:179: Unsupported or unknown PLI call: $monitor\n    $monitor            ("%t| %b     | %b     | %b   | %b   | %b       | %b     | %f ns",\n    ^~~~~~~~\n%Error: Exiting due to 20 error(s), 11 warning(s)\n'
module testbitHolder ();

  reg s_der, s_izq, d_n, dir, clk, enb;
  reg [1:0] modo;
  wire clkenb, y;

  assign clkenb = clk & enb;

  bitHolder tester(
    .s_der(s_der),
    .s_izq(s_izq),
    .d_n(d_n),
    .dir(dir),
    .modo(modo),
    .clkenb(clkenb),
    .s_out(s_out)
  );


  initial # 50 clk = 0;







  always # 37 clk = ~clk;

  initial begin











    # 50;
    enb <= 1;
    $display("se carga un 0");
    @(posedge clk);
      modo <= 2'b1x;
      s_der <= 1'bx;
      s_izq <= 1'bx;
      d_n <= 1'b0;
      dir <= 1'bx;


    # 50;
    $display("se carga un 1");
    @(posedge clk);
      modo <= 2'b1x;
      s_der <= 1'bx;
      s_izq <= 1'bx;
      d_n <= 1'b1;
      dir <= 1'bx;


    # 70
    $display("---\nModo de Carga en Serie\n---");
    $display("Hacia la izquierda");
    $display("con s_der = 0");
    @(posedge clk);
      modo <= 2'b00;
      s_izq <= 1'bx;
      dir <= 1'b0;
      s_der <= 1'b0;
      d_n <= 1'bx;

    # 70
    $display("con s_der = 1");
    @(posedge clk);
      modo <= 2'b00;
      s_izq <= 1'bx;
      dir <= 1'b0;
      s_der <= 1'b1;
      d_n <= 1'bx;

    $display("Hacia la derecha");
    $display("con s_izq = 0");
    @(posedge clk);
      modo <= 2'b00;
      s_izq <= 1'b0;
      dir <= 1'b1;
      s_der <= 1'bx;
      d_n <= 1'bx;

    # 70
    $display("con s_izq = 1");
    @(posedge clk);
      modo <= 2'b00;
      s_izq <= 1'b1;
      dir <= 1'b1;
      s_der <= 1'bx;
      d_n <= 1'bx;


    # 70
    $display("---\nModo de rotacion\n---");
    $display("Hacia la izquierda");
    $display("con s_der = 0");
    @(posedge clk);
      modo <= 2'b01;
      s_izq <= 1'bx;
      dir <= 1'b0;
      s_der <= 1'b0;
      d_n <= 1'bx;

    # 70
    $display("con s_der = 1");
    @(posedge clk);
      modo <= 2'b01;
      s_izq <= 1'bx;
      dir <= 1'b0;
      s_der <= 1'b1;
      d_n <= 1'bx;

    $display("Hacia la derecha");
    $display("con s_izq = 0");
    @(posedge clk);
      modo <= 2'b01;
      s_izq <= 1'b0;
      dir <= 1'b1;
      s_der <= 1'bx;
      d_n <= 1'bx;

    # 70
    $display("con s_izq = 1");
    @(posedge clk);
      modo <= 2'b01;
      s_izq <= 1'b1;
      dir <= 1'b1;
      s_der <= 1'bx;
      d_n <= 1'bx;


    # 150;
    @(posedge clk);
    $finish;
  end

  initial
    begin
    $dumpfile("./tests/testbitHolder.vcd");
    $dumpvars;
    $display("------------------------------------");
    $display("-- Test para modulo bitHolder     --");
    $display("------------------------------------");
    $display ("\t     tiempo | s_der | s_izq | d_n | dir | modo[1] | s_out | tiempo");
    $monitor            ("%t| %b     | %b     | %b   | %b   | %b       | %b     | %f ns",
                          $time, s_der, s_izq, d_n, dir, modo[1], s_out, $realtime);
  end
endmodule
module testbitHolder ();


  reg s_der, s_izq, d_n, dir, clk, enb;
  reg [1:0] modo;
  wire clkenb, y;

  assign clkenb = clk & enb;

  bitHolder tester(
    .s_der(s_der),
    .s_izq(s_izq),
    .d_n(d_n),
    .dir(dir),
    .modo(modo),
    .clkenb(clkenb),
    .s_out(s_out)
  );


  initial # 50 clk = 0;







  always # 37 clk = ~clk;

  initial begin











    # 50;
    enb <= 1;
    $display("se carga un 0");
    @(posedge clk);
      modo <= 2'b1x;
      s_der <= 1'bx;
      s_izq <= 1'bx;
      d_n <= 1'b0;
      dir <= 1'bx;


    # 50;
    $display("se carga un 1");
    @(posedge clk);
      modo <= 2'b1x;
      s_der <= 1'bx;
      s_izq <= 1'bx;
      d_n <= 1'b1;
      dir <= 1'bx;


    # 70
    $display("---\nModo de Carga en Serie\n---");
    $display("Hacia la izquierda");
    $display("con s_der = 0");
    @(posedge clk);
      modo <= 2'b00;
      s_izq <= 1'bx;
      dir <= 1'b0;
      s_der <= 1'b0;
      d_n <= 1'bx;

    # 70
    $display("con s_der = 1");
    @(posedge clk);
      modo <= 2'b00;
      s_izq <= 1'bx;
      dir <= 1'b0;
      s_der <= 1'b1;
      d_n <= 1'bx;

    $display("Hacia la derecha");
    $display("con s_izq = 0");
    @(posedge clk);
      modo <= 2'b00;
      s_izq <= 1'b0;
      dir <= 1'b1;
      s_der <= 1'bx;
      d_n <= 1'bx;

    # 70
    $display("con s_izq = 1");
    @(posedge clk);
      modo <= 2'b00;
      s_izq <= 1'b1;
      dir <= 1'b1;
      s_der <= 1'bx;
      d_n <= 1'bx;


    # 70
    $display("---\nModo de rotacion\n---");
    $display("Hacia la izquierda");
    $display("con s_der = 0");
    @(posedge clk);
      modo <= 2'b01;
      s_izq <= 1'bx;
      dir <= 1'b0;
      s_der <= 1'b0;
      d_n <= 1'bx;

    # 70
    $display("con s_der = 1");
    @(posedge clk);
      modo <= 2'b01;
      s_izq <= 1'bx;
      dir <= 1'b0;
      s_der <= 1'b1;
      d_n <= 1'bx;

    $display("Hacia la derecha");
    $display("con s_izq = 0");
    @(posedge clk);
      modo <= 2'b01;
      s_izq <= 1'b0;
      dir <= 1'b1;
      s_der <= 1'bx;
      d_n <= 1'bx;

    # 70
    $display("con s_izq = 1");
    @(posedge clk);
      modo <= 2'b01;
      s_izq <= 1'b1;
      dir <= 1'b1;
      s_der <= 1'bx;
      d_n <= 1'bx;


    # 150;
    @(posedge clk);
    $finish;
  end

  initial
    begin
    $dumpfile("./tests/testbitHolder.vcd");
    $dumpvars;
    $display("------------------------------------");
    $display("-- Test para modulo bitHolder     --");
    $display("------------------------------------");
    $display ("\t     tiempo | s_der | s_izq | d_n | dir | modo[1] | s_out | tiempo");
    $monitor            ("%t| %b     | %b     | %b   | %b   | %b       | %b     | %f ns",
                          $time, s_der, s_izq, d_n, dir, modo[1], s_out, $realtime);
  end
endmodule