data/full_repos/permissive/169738435/Cells/fs2.v
 line:7: before: "="
data/verilator_xmls/83d419bf-db68-44f4-94e1-74027302a648.xml
module FS2(
	input CK,
	input [3:0] P,
	input SD, L,
	output reg [3:0] Q = 4'd0
);

	always @(negedge CK)
	begin
		if (L)
			Q <= #1 P;
		else
			Q <= #1 {Q[2:0], SD};
	end

endmodule
module FS2(
	input CK,
	input [3:0] P,
	input SD, L,
	output reg [3:0] Q = 4'd0
);


	always @(negedge CK)
	begin
		if (L)
			Q <= #1 P;
		else
			Q <= #1 {Q[2:0], SD};
	end

endmodule