data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs/sources_1/new/flag_sync.v
data/verilator_xmls/3e7b8eb5-f771-42d7-b8c6-8aec9d3446f6.xml
module flag_sync(
    input a_rst_n,
    input a_clk,
    input a_flag,
    input b_rst_n,
    input b_clk,
    output b_flag
    );

    reg flag;
    always @(posedge a_clk or negedge a_rst_n) begin
        if(~a_rst_n) flag <= 0;
	else flag <= flag ^ a_flag;
    end

    (* ASYNC_REG = "TRUE" *) reg[2:0] flag_sync;
    always @(posedge b_clk or negedge b_rst_n) begin
        if(~b_rst_n) flag_sync <= 3'h0;
	else flag_sync <= {flag_sync[1:0], flag};
    end

    assign b_flag = flag_sync[1] ^ flag_sync[2];

endmodule
module flag_sync(
    input a_rst_n,
    input a_clk,
    input a_flag,
    input b_rst_n,
    input b_clk,
    output b_flag
    );


    reg flag;
    always @(posedge a_clk or negedge a_rst_n) begin
        if(~a_rst_n) flag <= 0;
	else flag <= flag ^ a_flag;
    end

    (* ASYNC_REG = "TRUE" *) reg[2:0] flag_sync;
    always @(posedge b_clk or negedge b_rst_n) begin
        if(~b_rst_n) flag_sync <= 3'h0;
	else flag_sync <= {flag_sync[1:0], flag};
    end

    assign b_flag = flag_sync[1] ^ flag_sync[2];

endmodule