data/full_repos/permissive/173670949/upduino/blink_led/pwm.v
data/verilator_xmls/8a8ec543-745a-48e7-9718-bbcf7e182133.xml
module PWM #(parameter BITS = 8)
(
    input            clk,
    input [BITS-1:0] level,
    output           pwm
);
    reg [BITS-1:0] counter = 0;

    always @(posedge clk) begin
        counter <= counter + 1;
    end

    assign pwm = (counter < level);


endmodule
module PWM #(parameter BITS = 8)
(
    input            clk,
    input [BITS-1:0] level,
    output           pwm
);

    reg [BITS-1:0] counter = 0;

    always @(posedge clk) begin
        counter <= counter + 1;
    end

    assign pwm = (counter < level);


endmodule