data/full_repos/permissive/143278/ivltests/br1008.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/0f00e3b4-2598-48d2-b3c5-cfecd6ea004c.xml
module test();

   wire [3:0] a = 4'd0;

   wire signed [3:0] b[1:0];

   assign b[0] = $signed(a);

   initial begin
      $display("b = [%b %b]", b[1], b[0]);
   end

endmodule
module test();


   wire [3:0] a = 4'd0;

   wire signed [3:0] b[1:0];

   assign b[0] = $signed(a);

   initial begin
      $display("b = [%b %b]", b[1], b[0]);
   end

endmodule