data/full_repos/permissive/167489907/ALU/ALU_LEGv8.v
None: at end of input
1: b"%Error: data/full_repos/permissive/167489907/ALU/ALU_LEGv8.v:39: Cannot find file containing module: 'CLA_adder64bit'\n CLA_adder64bit adder_inst (C0, A_Signal, B_Signal, add_output, C);\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167489907/ALU,data/full_repos/permissive/167489907/CLA_adder64bit\n             data/full_repos/permissive/167489907/ALU,data/full_repos/permissive/167489907/CLA_adder64bit.v\n             data/full_repos/permissive/167489907/ALU,data/full_repos/permissive/167489907/CLA_adder64bit.sv\n             CLA_adder64bit\n             CLA_adder64bit.v\n             CLA_adder64bit.sv\n             obj_dir/CLA_adder64bit\n             obj_dir/CLA_adder64bit.v\n             obj_dir/CLA_adder64bit.sv\n%Error: data/full_repos/permissive/167489907/ALU/ALU_LEGv8.v:42: Cannot find file containing module: 'Mux8to1Nbit'\n Mux8to1Nbit #(64) main_mux (F, FS[4:2], 64'b0, 64'b0, shift_right, shift_left, xor_output, add_output, or_output, and_output);\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ALU_LEGv8(A, B, FS, C0, F, status);
	input [63:0] A, B;
	input [4:0]FS;











	input C0;
	output [63:0]F;
	output [3:0]status;
	
	wire Z, N, C, V;
	assign status = {V, C, N, Z};
	
	
	wire [63:0] A_Signal, B_Signal;

	assign A_Signal = FS[1] ? ~A : A;

	assign B_Signal = FS[0] ? ~B : B;
	
	assign N = F[63];
	
	assign Z = (F == 64'b0) ? 1'b1 : 1'b0;
	
	assign V = ~(A_Signal[63] ^ B_Signal[63]) &  (F[63] ^ A_Signal[63]);
	
	wire [63:0]and_output, or_output, xor_output, add_output, shift_left, shift_right;
	assign and_output = A_Signal & B_Signal;
	assign or_output = A_Signal | B_Signal;
	assign xor_output = A_Signal ^ B_Signal;
	CLA_adder64bit adder_inst (C0, A_Signal, B_Signal, add_output, C);
	Shifter shift_inst (shift_left, shift_right, A, B[5:0]);
	
	Mux8to1Nbit #(64) main_mux (F, FS[4:2], 64'b0, 64'b0, shift_right, shift_left, xor_output, add_output, or_output, and_output);
endmodule
module ALU_LEGv8(A, B, FS, C0, F, status);

	input [63:0] A, B;
	input [4:0]FS;











	input C0;
	output [63:0]F;
	output [3:0]status;
	
	wire Z, N, C, V;
	assign status = {V, C, N, Z};
	
	
	wire [63:0] A_Signal, B_Signal;

	assign A_Signal = FS[1] ? ~A : A;

	assign B_Signal = FS[0] ? ~B : B;
	
	assign N = F[63];
	
	assign Z = (F == 64'b0) ? 1'b1 : 1'b0;
	
	assign V = ~(A_Signal[63] ^ B_Signal[63]) &  (F[63] ^ A_Signal[63]);
	
	wire [63:0]and_output, or_output, xor_output, add_output, shift_left, shift_right;
	assign and_output = A_Signal & B_Signal;
	assign or_output = A_Signal | B_Signal;
	assign xor_output = A_Signal ^ B_Signal;
	CLA_adder64bit adder_inst (C0, A_Signal, B_Signal, add_output, C);
	Shifter shift_inst (shift_left, shift_right, A, B[5:0]);
	
	Mux8to1Nbit #(64) main_mux (F, FS[4:2], 64'b0, 64'b0, shift_right, shift_left, xor_output, add_output, or_output, and_output);
endmodule