data/full_repos/permissive/208325333/Files/control_RAM.v
 line:41: before: ","
1: b'%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:128: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h15\' generates 6 bits.\n                                                                            : ... In instance control_RAM\n outu_rw<=6\'b010_101;\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:190: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write0<=addr;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:196: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write1<=addr;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:202: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write2<=addr;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:214: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write3<=addr;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:220: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write4<=addr;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:226: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write5<=addr;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:237: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write6<=addr;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:243: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write7<=addr;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:249: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write8<=addr;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:260: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write9<=addr;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:266: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write10<=addr;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:272: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n    addru_write11<=addr;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:313: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read5<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:314: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read8<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:315: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read11<=addr_sobel;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:321: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read3<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:322: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read6<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:323: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read9<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:327: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read4<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:328: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read7<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:329: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read10<=addr_sobel;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:350: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read2<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:351: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read8<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:352: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read11<=addr_sobel;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:357: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read0<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:358: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read6<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:359: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read9<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:364: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read1<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:365: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read7<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:366: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read10<=addr_sobel;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:386: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read2<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:387: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read5<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:388: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read11<=addr_sobel;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:393: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read0<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:394: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read3<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:395: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read9<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:400: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read1<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:401: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read4<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:402: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read10<=addr_sobel;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:421: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read2<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:422: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read5<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:423: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read8<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:429: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read0<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:430: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read3<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:431: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read6<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:436: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read1<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:437: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read4<=addr_sobel;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/208325333/Files/control_RAM.v:438: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_sobel\' generates 12 bits.\n                                                                            : ... In instance control_RAM\n      addru_read7<=addr_sobel;\n                 ^~\n%Error: Exiting due to 49 warning(s)\n'
module control_RAM
         (
	input wire clk,rst,
	
	input wire [7:0] in_pixel,
	
	input wire PCLK,
	input wire Href,
	input wire VSYNC,
					 
	output wire [7:0] r0,r1,r2,
					  r3,r4,r5,
					  r6,r7,r8,
					  r9,r10,r11,
					  
	output wire[6:0] addr_write0,addr_write1,addr_write2,
					addr_write3,addr_write4,addr_write5,
					addr_write6,addr_write7,addr_write8,
					addr_write9,addr_write10,addr_write11,
					  
	output wire[6:0] addr_read0,addr_read1,addr_read2,
					addr_read3,addr_read4,addr_read5,
					addr_read6,addr_read7,addr_read8,
					addr_read9,addr_read10,addr_read11,  
	
	output wire [11:0] out_rw,
	output wire RAM_flag
					 
	);



reg [7:0] ru0=0 ,ru1=0 ,ru2=0 ,
		  ru3=0 ,ru4=0 ,ru5=0,
		  ru6=0 ,ru7=0 ,ru8=0 ,
		  ru9=0 ,ru10=0 ,ru11=0;
					  
reg[6:0] addru_write0=0 ,addru_write1=0 ,addru_write2=0 ,
		 addru_write3=0 ,addru_write4=0 ,addru_write5=0,
		 addru_write6=0 ,addru_write7=0 ,addru_write8=0 ,
		 addru_write9=0 ,addru_write10=0 ,addru_write11=0;
					  
reg[6:0] addru_read0=0 ,addru_read1=0 ,addru_read2=0 ,
		 addru_read3=0 ,addru_read4=0 ,addru_read5=0, 
		 addru_read6=0 ,addru_read7=0 ,addru_read8=0 ,
		 addru_read9=0 ,addru_read10=0 ,addru_read11=0; 

reg [11:0] addr=0; 
reg [11:0] addr_sobel=0; 

assign r0[7:0] = ru0[7:0];
assign r1[7:0] = ru1[7:0];
assign r2[7:0] = ru2[7:0];
assign r3[7:0] = ru3[7:0];
assign r4[7:0] = ru4[7:0];
assign r5[7:0] = ru5[7:0];
assign r6[7:0] = ru6[7:0];
assign r7[7:0] = ru7[7:0];
assign r8[7:0] = ru8[7:0];
assign r9[7:0] = ru9[7:0];
assign r10[7:0] = ru10[7:0];
assign r11[7:0] = ru11[7:0];

assign addr_write0 = addru_write0;
assign addr_write1 = addru_write1;
assign addr_write2 = addru_write2;
assign addr_write3 = addru_write3;
assign addr_write4 = addru_write4;
assign addr_write5 = addru_write5;
assign addr_write6 = addru_write6;
assign addr_write7 = addru_write7;
assign addr_write8 = addru_write8;
assign addr_write9 = addru_write9;
assign addr_write10 = addru_write10;
assign addr_write11 = addru_write11;

assign addr_read0 = addru_read0;
assign addr_read1 = addru_read1;
assign addr_read2 = addru_read2;
assign addr_read3 = addru_read3;
assign addr_read4 = addru_read4;
assign addr_read5 = addru_read5;
assign addr_read6 = addru_read6;
assign addr_read7 = addru_read7;
assign addr_read8 = addru_read8;
assign addr_read9 = addru_read9;
assign addr_read10 = addru_read10;
assign addr_read11 = addru_read11;

reg [11:0] outu_rw=0;
reg RAM_flag_reg=0;
	  
assign out_rw = outu_rw;
	  
assign RAM_flag = RAM_flag_reg;

reg PCLK_ant=0;
reg PCLK_ant2=0;
reg getting_img=0;
reg VSYNC_ant=0;
reg Href_ant=0;
		 
reg [1:0] state=0;
reg [1:0] state_sobel=0;

reg [2:0] fila=0;


localparam FIRST_STATE = 0;
localparam LEFT_STATE  = 1;
localparam CENTER_STATE= 2;
localparam RIGHT_STATE = 3;


always @(posedge clk) begin

VSYNC_ant <= VSYNC;

  if(rst || VSYNC) begin
	outu_rw<=6'b010_101;
	fila<=4;
	getting_img<=0;
  end

  else begin
	Href_ant <= Href;
  
	if(VSYNC_ant && !VSYNC) begin
		outu_rw<=12'b000_000_000_000;
		getting_img<=1;	
	end
			
	if (!Href_ant && Href && getting_img) begin
	
		if(fila==4) begin
		outu_rw<=12'b000_000_000_000;
			fila<=1;
		end
		else if(fila==0) begin
			outu_rw<=12'b111_111_111_000;
			fila<=1;
		end  
		else if(fila==1) begin
			outu_rw<=12'b111_111_000_111;
			fila<=2;
		end
		else if(fila==2) begin
			outu_rw<=12'b111_000_111_111;
			fila<=3;
		end
		else if(fila==3) begin
			outu_rw<=12'b000_111_111_111;
			fila<=0;
		end
	end
  end
end


always @(posedge clk) begin

 if(rst ||!Href) begin
    RAM_flag_reg<=0;
	addr<=0;
	state<=0;
 end

 else begin
  PCLK_ant<=PCLK;
  RAM_flag_reg<=0;
 
 
  if (!PCLK_ant2 && PCLK && Href && getting_img) begin
 	RAM_flag_reg<=1;
	case (fila) 
	
		1: begin
		
		  case (state)
		  	0: begin
				ru0<= in_pixel;
				addru_write0<=addr;
				state<=1;
			end
			
		  	1: begin
				ru1<=in_pixel;
				addru_write1<=addr;
				state<=2;
			end
			
		  	2 : begin
				ru2<=in_pixel;
				addru_write2<=addr;
				addr<=addr+1;
				state<=0;
		  	end 
			
		  endcase
		end
		
		2: begin
		  case (state)
		  	0: begin
				ru3<= in_pixel;
				addru_write3<=addr;
				state<=1;
			end
			
		  	1: begin
				ru4<=in_pixel;
				addru_write4<=addr;
				state<=2;
			end
			
		  	2 : begin
				ru5<=in_pixel;
				addru_write5<=addr;
				addr<=addr+1;
				state<=0;
			end
		  endcase
		end 
		
		3: begin
		  case (state)
		  	0: begin
				ru6<= in_pixel;
				addru_write6<=addr;
				state<=1;
			end
			
		  	1: begin
				ru7<=in_pixel;
				addru_write7<=addr;
				state<=2;
			end
			
		  	2 : begin
				ru8<=in_pixel;
				addru_write8<=addr;
				addr<=addr+1;
				state<=0;
			end
		  endcase
		end 
		
		0: begin
		  case (state)
		  	0: begin
				ru9<= in_pixel;
				addru_write9<=addr;
				state<=1;
			end
			
		  	1: begin
				ru10<=in_pixel;
				addru_write10<=addr;
				state<=2;
			end
			
		  	2 : begin
				ru11<=in_pixel;
				addru_write11<=addr;
				addr<=addr+1;
				state<=0;
			end
		  endcase
		end 
	endcase
  	
  end
  
 end
 
end


always @(posedge clk) begin

 if(rst ||!Href) begin
	state_sobel<=0;
	addr_sobel<=0;
 end

 else begin
	PCLK_ant2<=PCLK;
 
  if (!PCLK_ant2 && PCLK && Href && getting_img) begin
	case (fila) 
	
      1: begin
		case (state_sobel)
				
		  FIRST_STATE: begin
    		state_sobel<=CENTER_STATE;
    		addr_sobel<=1;
    		addru_read3<=0;addru_read4<=0;addru_read5<=0;
    		addru_read6<=0;addru_read7<=0;addru_read8<=0;
    		addru_read9<=0;addru_read10<=0;addru_read11<=0;
    	  end
				
		  LEFT_STATE: begin
    		addr_sobel<=addr_sobel+1;
    		addru_read5<=addr_sobel;
    		addru_read8<=addr_sobel;
    		addru_read11<=addr_sobel;
    		state_sobel<=CENTER_STATE;
    	  end
				
		  CENTER_STATE: begin
    		state_sobel<=RIGHT_STATE;
    		addru_read3<=addr_sobel;
    		addru_read6<=addr_sobel;
    		addru_read9<=addr_sobel;
    	  end
				
		  RIGHT_STATE: begin
    		addru_read4<=addr_sobel;
    		addru_read7<=addr_sobel;
    		addru_read10<=addr_sobel;
    		state_sobel<=LEFT_STATE;
    	  end
			  
		endcase
      end
	
      2: begin
		case (state_sobel)
				
		  FIRST_STATE: begin
    		state_sobel<=CENTER_STATE;
    		addru_read0<=0;addru_read1<=0;addru_read2<=0;
    		addru_read6<=0;addru_read7<=0;addru_read8<=0;
    		addru_read9<=0;addru_read10<=0;addru_read11<=0;
    		addr_sobel<=1;
    	  end
				
		  LEFT_STATE: begin
    		addr_sobel<=addr_sobel+1;
    		state_sobel<=CENTER_STATE;
    		addru_read2<=addr_sobel;
    		addru_read8<=addr_sobel;
    		addru_read11<=addr_sobel;
    	  end
				
		  CENTER_STATE: begin
    		state_sobel<=RIGHT_STATE;
    		addru_read0<=addr_sobel;
    		addru_read6<=addr_sobel;
    		addru_read9<=addr_sobel;
    	  end
				
		  RIGHT_STATE: begin
    		state_sobel<=LEFT_STATE;
    		addru_read1<=addr_sobel;
    		addru_read7<=addr_sobel;
    		addru_read10<=addr_sobel;
    	  end
			  
		endcase
 	  end
	
      3: begin
		case (state_sobel)
				
		  FIRST_STATE: begin
    		state_sobel<=CENTER_STATE;
    		addru_read0<=0;addru_read1<=0;addru_read2<=0;
    		addru_read3<=0;addru_read4<=0;addru_read5<=0;
    		addru_read9<=0;addru_read10<=0;addru_read11<=0;
    		addr_sobel<=1;
    	  end
				
		  LEFT_STATE: begin
    		addr_sobel<=addr_sobel+1;
    		state_sobel<=CENTER_STATE;
    		addru_read2<=addr_sobel;
    		addru_read5<=addr_sobel;
    		addru_read11<=addr_sobel;
    	  end
				
		  CENTER_STATE: begin
    		state_sobel<=RIGHT_STATE;
    		addru_read0<=addr_sobel;
    		addru_read3<=addr_sobel;
    		addru_read9<=addr_sobel;
    	  end
				
		  RIGHT_STATE: begin
    		state_sobel<=LEFT_STATE;
    		addru_read1<=addr_sobel;
    		addru_read4<=addr_sobel;
    		addru_read10<=addr_sobel;
    	  end
			  
		endcase
 	  end
	
      0: begin
		case (state_sobel)
				
		  FIRST_STATE: begin
    		state_sobel<=CENTER_STATE;
    		addru_read0<=0;addru_read1<=0;addru_read2<=0;
    		addru_read3<=0;addru_read4<=0;addru_read5<=0;
    		addru_read6<=0;addru_read7<=0;addru_read8<=0;
    		addr_sobel<=1;
    	  end
				
		  LEFT_STATE: begin
    		addr_sobel<=addr_sobel+1;
    		addru_read2<=addr_sobel;
    		addru_read5<=addr_sobel;
    		addru_read8<=addr_sobel;
    		state_sobel<=CENTER_STATE;
    	  end
				
		  CENTER_STATE: begin
    		state_sobel<=RIGHT_STATE;
    		addru_read0<=addr_sobel;
    		addru_read3<=addr_sobel;
    		addru_read6<=addr_sobel;
    	  end
				
		  RIGHT_STATE: begin
    		state_sobel<=LEFT_STATE;
    		addru_read1<=addr_sobel;
    		addru_read4<=addr_sobel;
    		addru_read7<=addr_sobel;
    	  end
			  
		endcase
 	  end
	endcase
  	
  end
  
 end
 
end

endmodule
module control_RAM
         (
	input wire clk,rst,
	
	input wire [7:0] in_pixel,
	
	input wire PCLK,
	input wire Href,
	input wire VSYNC,
					 
	output wire [7:0] r0,r1,r2,
					  r3,r4,r5,
					  r6,r7,r8,
					  r9,r10,r11,
					  
	output wire[6:0] addr_write0,addr_write1,addr_write2,
					addr_write3,addr_write4,addr_write5,
					addr_write6,addr_write7,addr_write8,
					addr_write9,addr_write10,addr_write11,
					  
	output wire[6:0] addr_read0,addr_read1,addr_read2,
					addr_read3,addr_read4,addr_read5,
					addr_read6,addr_read7,addr_read8,
					addr_read9,addr_read10,addr_read11,  
	
	output wire [11:0] out_rw,
	output wire RAM_flag
					 
	);




reg [7:0] ru0=0 ,ru1=0 ,ru2=0 ,
		  ru3=0 ,ru4=0 ,ru5=0,
		  ru6=0 ,ru7=0 ,ru8=0 ,
		  ru9=0 ,ru10=0 ,ru11=0;
					  
reg[6:0] addru_write0=0 ,addru_write1=0 ,addru_write2=0 ,
		 addru_write3=0 ,addru_write4=0 ,addru_write5=0,
		 addru_write6=0 ,addru_write7=0 ,addru_write8=0 ,
		 addru_write9=0 ,addru_write10=0 ,addru_write11=0;
					  
reg[6:0] addru_read0=0 ,addru_read1=0 ,addru_read2=0 ,
		 addru_read3=0 ,addru_read4=0 ,addru_read5=0, 
		 addru_read6=0 ,addru_read7=0 ,addru_read8=0 ,
		 addru_read9=0 ,addru_read10=0 ,addru_read11=0; 

reg [11:0] addr=0; 
reg [11:0] addr_sobel=0; 

assign r0[7:0] = ru0[7:0];
assign r1[7:0] = ru1[7:0];
assign r2[7:0] = ru2[7:0];
assign r3[7:0] = ru3[7:0];
assign r4[7:0] = ru4[7:0];
assign r5[7:0] = ru5[7:0];
assign r6[7:0] = ru6[7:0];
assign r7[7:0] = ru7[7:0];
assign r8[7:0] = ru8[7:0];
assign r9[7:0] = ru9[7:0];
assign r10[7:0] = ru10[7:0];
assign r11[7:0] = ru11[7:0];

assign addr_write0 = addru_write0;
assign addr_write1 = addru_write1;
assign addr_write2 = addru_write2;
assign addr_write3 = addru_write3;
assign addr_write4 = addru_write4;
assign addr_write5 = addru_write5;
assign addr_write6 = addru_write6;
assign addr_write7 = addru_write7;
assign addr_write8 = addru_write8;
assign addr_write9 = addru_write9;
assign addr_write10 = addru_write10;
assign addr_write11 = addru_write11;

assign addr_read0 = addru_read0;
assign addr_read1 = addru_read1;
assign addr_read2 = addru_read2;
assign addr_read3 = addru_read3;
assign addr_read4 = addru_read4;
assign addr_read5 = addru_read5;
assign addr_read6 = addru_read6;
assign addr_read7 = addru_read7;
assign addr_read8 = addru_read8;
assign addr_read9 = addru_read9;
assign addr_read10 = addru_read10;
assign addr_read11 = addru_read11;

reg [11:0] outu_rw=0;
reg RAM_flag_reg=0;
	  
assign out_rw = outu_rw;
	  
assign RAM_flag = RAM_flag_reg;

reg PCLK_ant=0;
reg PCLK_ant2=0;
reg getting_img=0;
reg VSYNC_ant=0;
reg Href_ant=0;
		 
reg [1:0] state=0;
reg [1:0] state_sobel=0;

reg [2:0] fila=0;


localparam FIRST_STATE = 0;
localparam LEFT_STATE  = 1;
localparam CENTER_STATE= 2;
localparam RIGHT_STATE = 3;


always @(posedge clk) begin

VSYNC_ant <= VSYNC;

  if(rst || VSYNC) begin
	outu_rw<=6'b010_101;
	fila<=4;
	getting_img<=0;
  end

  else begin
	Href_ant <= Href;
  
	if(VSYNC_ant && !VSYNC) begin
		outu_rw<=12'b000_000_000_000;
		getting_img<=1;	
	end
			
	if (!Href_ant && Href && getting_img) begin
	
		if(fila==4) begin
		outu_rw<=12'b000_000_000_000;
			fila<=1;
		end
		else if(fila==0) begin
			outu_rw<=12'b111_111_111_000;
			fila<=1;
		end  
		else if(fila==1) begin
			outu_rw<=12'b111_111_000_111;
			fila<=2;
		end
		else if(fila==2) begin
			outu_rw<=12'b111_000_111_111;
			fila<=3;
		end
		else if(fila==3) begin
			outu_rw<=12'b000_111_111_111;
			fila<=0;
		end
	end
  end
end


always @(posedge clk) begin

 if(rst ||!Href) begin
    RAM_flag_reg<=0;
	addr<=0;
	state<=0;
 end

 else begin
  PCLK_ant<=PCLK;
  RAM_flag_reg<=0;
 
 
  if (!PCLK_ant2 && PCLK && Href && getting_img) begin
 	RAM_flag_reg<=1;
	case (fila) 
	
		1: begin
		
		  case (state)
		  	0: begin
				ru0<= in_pixel;
				addru_write0<=addr;
				state<=1;
			end
			
		  	1: begin
				ru1<=in_pixel;
				addru_write1<=addr;
				state<=2;
			end
			
		  	2 : begin
				ru2<=in_pixel;
				addru_write2<=addr;
				addr<=addr+1;
				state<=0;
		  	end 
			
		  endcase
		end
		
		2: begin
		  case (state)
		  	0: begin
				ru3<= in_pixel;
				addru_write3<=addr;
				state<=1;
			end
			
		  	1: begin
				ru4<=in_pixel;
				addru_write4<=addr;
				state<=2;
			end
			
		  	2 : begin
				ru5<=in_pixel;
				addru_write5<=addr;
				addr<=addr+1;
				state<=0;
			end
		  endcase
		end 
		
		3: begin
		  case (state)
		  	0: begin
				ru6<= in_pixel;
				addru_write6<=addr;
				state<=1;
			end
			
		  	1: begin
				ru7<=in_pixel;
				addru_write7<=addr;
				state<=2;
			end
			
		  	2 : begin
				ru8<=in_pixel;
				addru_write8<=addr;
				addr<=addr+1;
				state<=0;
			end
		  endcase
		end 
		
		0: begin
		  case (state)
		  	0: begin
				ru9<= in_pixel;
				addru_write9<=addr;
				state<=1;
			end
			
		  	1: begin
				ru10<=in_pixel;
				addru_write10<=addr;
				state<=2;
			end
			
		  	2 : begin
				ru11<=in_pixel;
				addru_write11<=addr;
				addr<=addr+1;
				state<=0;
			end
		  endcase
		end 
	endcase
  	
  end
  
 end
 
end


always @(posedge clk) begin

 if(rst ||!Href) begin
	state_sobel<=0;
	addr_sobel<=0;
 end

 else begin
	PCLK_ant2<=PCLK;
 
  if (!PCLK_ant2 && PCLK && Href && getting_img) begin
	case (fila) 
	
      1: begin
		case (state_sobel)
				
		  FIRST_STATE: begin
    		state_sobel<=CENTER_STATE;
    		addr_sobel<=1;
    		addru_read3<=0;addru_read4<=0;addru_read5<=0;
    		addru_read6<=0;addru_read7<=0;addru_read8<=0;
    		addru_read9<=0;addru_read10<=0;addru_read11<=0;
    	  end
				
		  LEFT_STATE: begin
    		addr_sobel<=addr_sobel+1;
    		addru_read5<=addr_sobel;
    		addru_read8<=addr_sobel;
    		addru_read11<=addr_sobel;
    		state_sobel<=CENTER_STATE;
    	  end
				
		  CENTER_STATE: begin
    		state_sobel<=RIGHT_STATE;
    		addru_read3<=addr_sobel;
    		addru_read6<=addr_sobel;
    		addru_read9<=addr_sobel;
    	  end
				
		  RIGHT_STATE: begin
    		addru_read4<=addr_sobel;
    		addru_read7<=addr_sobel;
    		addru_read10<=addr_sobel;
    		state_sobel<=LEFT_STATE;
    	  end
			  
		endcase
      end
	
      2: begin
		case (state_sobel)
				
		  FIRST_STATE: begin
    		state_sobel<=CENTER_STATE;
    		addru_read0<=0;addru_read1<=0;addru_read2<=0;
    		addru_read6<=0;addru_read7<=0;addru_read8<=0;
    		addru_read9<=0;addru_read10<=0;addru_read11<=0;
    		addr_sobel<=1;
    	  end
				
		  LEFT_STATE: begin
    		addr_sobel<=addr_sobel+1;
    		state_sobel<=CENTER_STATE;
    		addru_read2<=addr_sobel;
    		addru_read8<=addr_sobel;
    		addru_read11<=addr_sobel;
    	  end
				
		  CENTER_STATE: begin
    		state_sobel<=RIGHT_STATE;
    		addru_read0<=addr_sobel;
    		addru_read6<=addr_sobel;
    		addru_read9<=addr_sobel;
    	  end
				
		  RIGHT_STATE: begin
    		state_sobel<=LEFT_STATE;
    		addru_read1<=addr_sobel;
    		addru_read7<=addr_sobel;
    		addru_read10<=addr_sobel;
    	  end
			  
		endcase
 	  end
	
      3: begin
		case (state_sobel)
				
		  FIRST_STATE: begin
    		state_sobel<=CENTER_STATE;
    		addru_read0<=0;addru_read1<=0;addru_read2<=0;
    		addru_read3<=0;addru_read4<=0;addru_read5<=0;
    		addru_read9<=0;addru_read10<=0;addru_read11<=0;
    		addr_sobel<=1;
    	  end
				
		  LEFT_STATE: begin
    		addr_sobel<=addr_sobel+1;
    		state_sobel<=CENTER_STATE;
    		addru_read2<=addr_sobel;
    		addru_read5<=addr_sobel;
    		addru_read11<=addr_sobel;
    	  end
				
		  CENTER_STATE: begin
    		state_sobel<=RIGHT_STATE;
    		addru_read0<=addr_sobel;
    		addru_read3<=addr_sobel;
    		addru_read9<=addr_sobel;
    	  end
				
		  RIGHT_STATE: begin
    		state_sobel<=LEFT_STATE;
    		addru_read1<=addr_sobel;
    		addru_read4<=addr_sobel;
    		addru_read10<=addr_sobel;
    	  end
			  
		endcase
 	  end
	
      0: begin
		case (state_sobel)
				
		  FIRST_STATE: begin
    		state_sobel<=CENTER_STATE;
    		addru_read0<=0;addru_read1<=0;addru_read2<=0;
    		addru_read3<=0;addru_read4<=0;addru_read5<=0;
    		addru_read6<=0;addru_read7<=0;addru_read8<=0;
    		addr_sobel<=1;
    	  end
				
		  LEFT_STATE: begin
    		addr_sobel<=addr_sobel+1;
    		addru_read2<=addr_sobel;
    		addru_read5<=addr_sobel;
    		addru_read8<=addr_sobel;
    		state_sobel<=CENTER_STATE;
    	  end
				
		  CENTER_STATE: begin
    		state_sobel<=RIGHT_STATE;
    		addru_read0<=addr_sobel;
    		addru_read3<=addr_sobel;
    		addru_read6<=addr_sobel;
    	  end
				
		  RIGHT_STATE: begin
    		state_sobel<=LEFT_STATE;
    		addru_read1<=addr_sobel;
    		addru_read4<=addr_sobel;
    		addru_read7<=addr_sobel;
    	  end
			  
		endcase
 	  end
	endcase
  	
  end
  
 end
 
end

endmodule