data/full_repos/permissive/201488448/2_circuits/2_sequential/12_muxdff.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/12_muxdff.v:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q'\n                                                                                               : ... In instance top_module\n        Q <= D; \n        ^\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    
    wire D;
    assign	D = L?R:(E?w:Q);
    always@(posedge clk) begin
       	Q <= D; 
    end

endmodule
module top_module (
    input clk,
    input w, R, E, L,
    output Q
);

    
    wire D;
    assign	D = L?R:(E?w:Q);
    always@(posedge clk) begin
       	Q <= D; 
    end

endmodule