data/full_repos/permissive/141770060/src/Components/Clock.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/141770060/src/Components/Clock.v:57: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                 : ... Top module \'CLOCK_GENERATOR\'\nmodule CLOCK_GENERATOR #(parameter DIVIDE = 2)\n       ^~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'ONESHOT\'\nmodule ONESHOT(\n       ^~~~~~~\n                                                                                 : ... Top module \'Syncronizer\'\nmodule Syncronizer #(\n       ^~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module ONESHOT(
    input wire clk,
    input wire rst,
    input wire signal,
    output reg out
);

reg previously_high;

always @(posedge clk or posedge rst)
begin
    if(rst)
    begin
        out <= 0;
        previously_high <= 0;
    end
    else
    begin
        if(signal && !previously_high)
        begin
            out <= 1;
            previously_high <= 1;
        end
        else if(signal && previously_high)
        begin
            out <= 0;
            previously_high <= 1;
        end
        else
        begin
            out <= 0;
            previously_high <= 0;
        end
    end
end

endmodule
module ONESHOT(
    input wire clk,
    input wire rst,
    input wire signal,
    output reg out
);


reg previously_high;

always @(posedge clk or posedge rst)
begin
    if(rst)
    begin
        out <= 0;
        previously_high <= 0;
    end
    else
    begin
        if(signal && !previously_high)
        begin
            out <= 1;
            previously_high <= 1;
        end
        else if(signal && previously_high)
        begin
            out <= 0;
            previously_high <= 1;
        end
        else
        begin
            out <= 0;
            previously_high <= 0;
        end
    end
end

endmodule