data/full_repos/permissive/106408053/verilog/spi_transmitter.v
'utf-8' codec can't decode byte 0xbd in position 1817: invalid start byte
1: b'%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:78: syntax error, unexpected byte, expecting IDENTIFIER or \'=\' or do or final\nreg [7:0] byte;\n          ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:83: syntax error, unexpected \'=\', expecting "\'{"\n  byte = 0;\n       ^\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:86: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n    2\'h0 : begin byte = sampled_send_data[7:0]; disabled = !sampled_send_valid[0]; end\n                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:87: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n    2\'h1 : begin byte = sampled_send_data[15:8]; disabled = !sampled_send_valid[1]; end\n                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:88: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n    2\'h2 : begin byte = sampled_send_data[23:16]; disabled = !sampled_send_valid[2]; end\n                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:89: syntax error, unexpected IDENTIFIER, expecting new or new-then-paren\n    2\'h3 : begin byte = sampled_send_data[31:24]; disabled = !sampled_send_valid[3]; end\n                        ^~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:126: syntax error, unexpected \';\', expecting "\'{"\n      next_txBuffer = byte;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/spi_transmitter.v:181: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 7 error(s), 3 warning(s)\n'
module spi_transmitter(
  clock, sclk, extReset,
  send, send_data, send_valid,
  writeMeta, meta_data,
  cs, query_id, query_dataIn, dataIn,

  tx, busy, byteDone);

input clock;
input sclk;
input extReset;

input send;
input [31:0] send_data;
input [3:0] send_valid;
input writeMeta;
input [7:0] meta_data;
input cs;
input query_id;
input query_dataIn;
input [31:0] dataIn;
output tx;
output busy;
output byteDone;

reg [31:0] sampled_send_data, next_sampled_send_data;
reg [3:0] sampled_send_valid, next_sampled_send_valid;
reg [2:0] bits, next_bits;
reg [1:0] bytesel, next_bytesel;
reg byteDone, next_byteDone;
reg dly_sclk, next_dly_sclk; 
reg busy, next_busy;

reg [7:0] txBuffer, next_txBuffer;
reg tx, next_tx;


reg writeReset, writeByte; 





reg [7:0] byte;
reg disabled;
always @*
begin
  #1;
  byte = 0;
  disabled = 0;
  case (bytesel)
    2'h0 : begin byte = sampled_send_data[7:0]; disabled = !sampled_send_valid[0]; end
    2'h1 : begin byte = sampled_send_data[15:8]; disabled = !sampled_send_valid[1]; end
    2'h2 : begin byte = sampled_send_data[23:16]; disabled = !sampled_send_valid[2]; end
    2'h3 : begin byte = sampled_send_data[31:24]; disabled = !sampled_send_valid[3]; end
  endcase
end






always @(posedge clock)
begin
  dly_sclk = next_dly_sclk;
  bits = next_bits;
  byteDone = next_byteDone;
  txBuffer = next_txBuffer;
  tx = next_tx;
end

always @*
begin
  #1;
  next_dly_sclk = sclk;
  next_bits = bits;
  next_byteDone = byteDone;
  next_txBuffer = txBuffer;
  next_tx = tx;

  if (writeReset)
    begin
      next_bits = 0;
      next_byteDone = 1'b1;
      next_txBuffer = 8'hFF;
    end
  else if (writeByte) 
    begin
      next_bits = 0;
      next_byteDone = disabled;
      next_txBuffer = byte;
    end
  else if (writeMeta)
    begin
      next_bits = 0;
      next_byteDone = 0;
      next_txBuffer = meta_data;
    end
 



  if (cs) next_bits = 0;


  if (!cs && dly_sclk && !sclk && !byteDone)
    begin

      next_bits = bits + 1'b1;
      next_byteDone = &bits;
    end

  next_tx = (cs || byteDone) ? 1'b1 : next_txBuffer[~bits];
end





parameter [1:0] INIT = 0, IDLE = 1, SEND = 2, POLL = 3;
reg [1:0] state, next_state;

initial state = INIT;
always @(posedge clock or posedge extReset) 
begin
  if (extReset) 
    begin
      state = INIT;
      sampled_send_data = 32'h0;
      sampled_send_valid = 4'h0;
      bytesel = 3'h0;
      busy = 1'b0;
    end 
  else 
    begin
      state = next_state;
      sampled_send_data = next_sampled_send_data;
      sampled_send_valid = next_sampled_send_valid;
      bytesel = next_bytesel;
      busy = next_busy;
    end
end

always @*
begin
  #1;
  next_state = state;
  next_sampled_send_data = sampled_send_data;
  next_sampled_send_valid = sampled_send_valid;
  next_bytesel = bytesel;

  next_busy = (state != IDLE) || send || !byteDone;

  writeReset = 1'b0;
  writeByte = 1'b0;

  case (state)
    INIT :
      begin
	writeReset = 1'b1;
        next_sampled_send_data = 32'h0;
        next_sampled_send_valid = 4'hF;
        next_bytesel = 3'h0;
        next_busy = 1'b0;
	next_state = IDLE;
      end

    IDLE : 
      begin
        next_sampled_send_data = send_data;
        next_sampled_send_valid = send_valid;
	next_bytesel = 0;

        if (send) 
          next_state = SEND;
        else if (query_id)
	  begin
            next_sampled_send_data = 32'h534c4131;
            next_sampled_send_valid = 4'hF;
            next_state = SEND;
          end
        else if (query_dataIn)
	  begin
            next_sampled_send_data = dataIn;
            next_sampled_send_valid = 4'hF;
            next_state = SEND;
	  end
      end

    SEND :
      begin
        writeByte = 1'b1;
        next_bytesel = bytesel + 1'b1;
	next_state = POLL;
      end

    POLL : 
      begin
        if (byteDone)
	  next_state = (~|bytesel) ? IDLE : SEND;
      end

    default : next_state = INIT;
  endcase
end
endmodule
module spi_transmitter(
  clock, sclk, extReset,
  send, send_data, send_valid,
  writeMeta, meta_data,
  cs, query_id, query_dataIn, dataIn,

  tx, busy, byteDone);


input clock;
input sclk;
input extReset;

input send;
input [31:0] send_data;
input [3:0] send_valid;
input writeMeta;
input [7:0] meta_data;
input cs;
input query_id;
input query_dataIn;
input [31:0] dataIn;
output tx;
output busy;
output byteDone;

reg [31:0] sampled_send_data, next_sampled_send_data;
reg [3:0] sampled_send_valid, next_sampled_send_valid;
reg [2:0] bits, next_bits;
reg [1:0] bytesel, next_bytesel;
reg byteDone, next_byteDone;
reg dly_sclk, next_dly_sclk; 
reg busy, next_busy;

reg [7:0] txBuffer, next_txBuffer;
reg tx, next_tx;


reg writeReset, writeByte; 





reg [7:0] byte;
reg disabled;
always @*
begin
  #1;
  byte = 0;
  disabled = 0;
  case (bytesel)
    2'h0 : begin byte = sampled_send_data[7:0]; disabled = !sampled_send_valid[0]; end
    2'h1 : begin byte = sampled_send_data[15:8]; disabled = !sampled_send_valid[1]; end
    2'h2 : begin byte = sampled_send_data[23:16]; disabled = !sampled_send_valid[2]; end
    2'h3 : begin byte = sampled_send_data[31:24]; disabled = !sampled_send_valid[3]; end
  endcase
end






always @(posedge clock)
begin
  dly_sclk = next_dly_sclk;
  bits = next_bits;
  byteDone = next_byteDone;
  txBuffer = next_txBuffer;
  tx = next_tx;
end

always @*
begin
  #1;
  next_dly_sclk = sclk;
  next_bits = bits;
  next_byteDone = byteDone;
  next_txBuffer = txBuffer;
  next_tx = tx;

  if (writeReset)
    begin
      next_bits = 0;
      next_byteDone = 1'b1;
      next_txBuffer = 8'hFF;
    end
  else if (writeByte) 
    begin
      next_bits = 0;
      next_byteDone = disabled;
      next_txBuffer = byte;
    end
  else if (writeMeta)
    begin
      next_bits = 0;
      next_byteDone = 0;
      next_txBuffer = meta_data;
    end
 



  if (cs) next_bits = 0;


  if (!cs && dly_sclk && !sclk && !byteDone)
    begin

      next_bits = bits + 1'b1;
      next_byteDone = &bits;
    end

  next_tx = (cs || byteDone) ? 1'b1 : next_txBuffer[~bits];
end





parameter [1:0] INIT = 0, IDLE = 1, SEND = 2, POLL = 3;
reg [1:0] state, next_state;

initial state = INIT;
always @(posedge clock or posedge extReset) 
begin
  if (extReset) 
    begin
      state = INIT;
      sampled_send_data = 32'h0;
      sampled_send_valid = 4'h0;
      bytesel = 3'h0;
      busy = 1'b0;
    end 
  else 
    begin
      state = next_state;
      sampled_send_data = next_sampled_send_data;
      sampled_send_valid = next_sampled_send_valid;
      bytesel = next_bytesel;
      busy = next_busy;
    end
end

always @*
begin
  #1;
  next_state = state;
  next_sampled_send_data = sampled_send_data;
  next_sampled_send_valid = sampled_send_valid;
  next_bytesel = bytesel;

  next_busy = (state != IDLE) || send || !byteDone;

  writeReset = 1'b0;
  writeByte = 1'b0;

  case (state)
    INIT :
      begin
	writeReset = 1'b1;
        next_sampled_send_data = 32'h0;
        next_sampled_send_valid = 4'hF;
        next_bytesel = 3'h0;
        next_busy = 1'b0;
	next_state = IDLE;
      end

    IDLE : 
      begin
        next_sampled_send_data = send_data;
        next_sampled_send_valid = send_valid;
	next_bytesel = 0;

        if (send) 
          next_state = SEND;
        else if (query_id)
	  begin
            next_sampled_send_data = 32'h534c4131;
            next_sampled_send_valid = 4'hF;
            next_state = SEND;
          end
        else if (query_dataIn)
	  begin
            next_sampled_send_data = dataIn;
            next_sampled_send_valid = 4'hF;
            next_state = SEND;
	  end
      end

    SEND :
      begin
        writeByte = 1'b1;
        next_bytesel = bytesel + 1'b1;
	next_state = POLL;
      end

    POLL : 
      begin
        if (byteDone)
	  next_state = (~|bytesel) ? IDLE : SEND;
      end

    default : next_state = INIT;
  endcase
end
endmodule