data/full_repos/permissive/204937464/lib/verilog/vector_ave.v
1: b"%Error: data/full_repos/permissive/204937464/lib/verilog/vector_ave.v:33: Cannot find file containing module: 'mul16_signed'\nmul16_signed u_mul16_signed_1 (\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/204937464/lib/verilog,data/full_repos/permissive/204937464/mul16_signed\n             data/full_repos/permissive/204937464/lib/verilog,data/full_repos/permissive/204937464/mul16_signed.v\n             data/full_repos/permissive/204937464/lib/verilog,data/full_repos/permissive/204937464/mul16_signed.sv\n             mul16_signed\n             mul16_signed.v\n             mul16_signed.sv\n             obj_dir/mul16_signed\n             obj_dir/mul16_signed.v\n             obj_dir/mul16_signed.sv\n%Error: data/full_repos/permissive/204937464/lib/verilog/vector_ave.v:56: Cannot find file containing module: 'delay'\ndelay #(2)u_delay_1(\n^~~~~\n%Error: data/full_repos/permissive/204937464/lib/verilog/vector_ave.v:82: Cannot find file containing module: 'bit_trunc'\nbit_trunc #(\n^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module vector_ave(
  clk,
  rst,
  op_din_en,
  op_din_eop,
  op_din,
  fraction,
  op_dout
 );
 



input clk;
input rst;
input op_din_en;
input op_din_eop;
input [15:0] op_din;
input [15:0] fraction;
output [15:0] op_dout; 




parameter RELU = 0;

parameter Q = 8;




wire [31:0] a1;
mul16_signed u_mul16_signed_1 (
  .CLK(clk),
  .A(op_din),
  .B(fraction),
  .P(a1)
);




reg op_din_en_d1;
always @ (posedge clk)
begin
  if(rst)
    op_din_en_d1 <= 1'b0;
  else
    op_din_en_d1 <= op_din_en;
end




wire op_din_eop_d2;
delay #(2)u_delay_1(
  .clk(clk),
  .rst(rst),
  .in(op_din_eop),
  .out(op_din_eop_d2)
);




reg [31:0] sum;
always @ (posedge clk)
begin
  if(rst)
    sum <= 32'b0;
  else if ((op_din_eop_d2 == 1) && (op_din_en_d1 == 1))
    sum <= a1;
  else if ((op_din_eop_d2 == 1) && (op_din_en_d1 == 0))
    sum <= 32'b0;
  else if ((op_din_eop_d2 == 0) && (op_din_en_d1 == 1))
    sum <= sum + a1;
  else  
    sum <= sum;	
end

wire [15:0] op_dout_tmp;
bit_trunc #(
  .WIDTH(32),
  .MSB(Q+15),
  .LSB(Q)
) 
u_bit_trunc_2(
  .din(sum),
  .dout(op_dout_tmp)
);

assign op_dout = RELU ? (op_dout_tmp[15] ? 0 : op_dout_tmp) : op_dout_tmp;

endmodule
module vector_ave(
  clk,
  rst,
  op_din_en,
  op_din_eop,
  op_din,
  fraction,
  op_dout
 );

 



input clk;
input rst;
input op_din_en;
input op_din_eop;
input [15:0] op_din;
input [15:0] fraction;
output [15:0] op_dout; 




parameter RELU = 0;

parameter Q = 8;




wire [31:0] a1;
mul16_signed u_mul16_signed_1 (
  .CLK(clk),
  .A(op_din),
  .B(fraction),
  .P(a1)
);




reg op_din_en_d1;
always @ (posedge clk)
begin
  if(rst)
    op_din_en_d1 <= 1'b0;
  else
    op_din_en_d1 <= op_din_en;
end




wire op_din_eop_d2;
delay #(2)u_delay_1(
  .clk(clk),
  .rst(rst),
  .in(op_din_eop),
  .out(op_din_eop_d2)
);




reg [31:0] sum;
always @ (posedge clk)
begin
  if(rst)
    sum <= 32'b0;
  else if ((op_din_eop_d2 == 1) && (op_din_en_d1 == 1))
    sum <= a1;
  else if ((op_din_eop_d2 == 1) && (op_din_en_d1 == 0))
    sum <= 32'b0;
  else if ((op_din_eop_d2 == 0) && (op_din_en_d1 == 1))
    sum <= sum + a1;
  else  
    sum <= sum;	
end

wire [15:0] op_dout_tmp;
bit_trunc #(
  .WIDTH(32),
  .MSB(Q+15),
  .LSB(Q)
) 
u_bit_trunc_2(
  .din(sum),
  .dout(op_dout_tmp)
);

assign op_dout = RELU ? (op_dout_tmp[15] ? 0 : op_dout_tmp) : op_dout_tmp;

endmodule