data/full_repos/permissive/132220215/testbenches/ram_module_tb.v
 line:65: before: "$"
1: b'%Error: data/full_repos/permissive/132220215/testbenches/ram_module_tb.v:4: Cannot find include file: ../ram_module.v\n`include "../ram_module.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../ram_module.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../ram_module.v.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../ram_module.v.sv\n             ../ram_module.v\n             ../ram_module.v.v\n             ../ram_module.v.sv\n             obj_dir/../ram_module.v\n             obj_dir/../ram_module.v.v\n             obj_dir/../ram_module.v.sv\n%Error: data/full_repos/permissive/132220215/testbenches/ram_module_tb.v:29: Unsupported or unknown PLI call: $dumpfile\n addr_sel = 512;  $dumpfile("ram.vcd");\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/132220215/testbenches/ram_module_tb.v:30: Unsupported or unknown PLI call: $dumpvars\n    data = 8\'h7F;  $dumpvars(0,ram_3_tb);\n                   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/ram_module_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n       #10 addr_sel = 32;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/ram_module_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n       #10 addr_sel = 64;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/ram_module_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n       #10 addr_sel = 128;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/ram_module_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n       #10 addr_sel = 256;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/ram_module_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n       #10 addr_sel = 512;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/ram_module_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n       #60 $finish;\n       ^\n%Error: data/full_repos/permissive/132220215/testbenches/ram_module_tb.v:45: Unsupported or unknown PLI call: $monitor\n  $monitor(" addr = %d ram[addr] = %h",addr_sel,inter);\n  ^~~~~~~~\n%Error: Exiting due to 4 error(s), 6 warning(s)\n'
module ram_3_tb;
 output reg [9:0] addr_sel;
 output reg [7:0] data;
 input [7:0] mod_output;
 output reg wr_sel,cs_inp;
 wire [7:0] inter;


 ram_3 RAM0(.data_out(mod_output),.addr(addr_sel),.wr(wr_sel),.cs(cs_inp),.data_in(data));
 assign inter = RAM0.mem[addr_sel];
 initial
 begin
	 cs_inp = 1'b1;
	 wr_sel = 1'b1;
        addr_sel = 32;
	data = 8'hFF;   
	addr_sel = 64; 
       	data = 8'hAC; 
	addr_sel = 128;
       	data = 8'h9B; 
	addr_sel = 256;
	data = 8'h8F;
	addr_sel = 512;	 $dumpfile("ram.vcd");
   	data = 8'h7F;	 $dumpvars(0,ram_3_tb);
 end

 initial
 begin
       #10 addr_sel = 32;
       #10 addr_sel = 64;
       #10 addr_sel = 128;
       #10 addr_sel = 256;
       #10 addr_sel = 512;
       #60 $finish;
 end
 
 initial
 begin
	 $monitor(" addr = %d ram[addr] = %h",addr_sel,inter);
 end

endmodule
module ram_3_tb;

 output reg [9:0] addr_sel;
 output reg [7:0] data;
 input [7:0] mod_output;
 output reg wr_sel,cs_inp;
 wire [7:0] inter;


 ram_3 RAM0(.data_out(mod_output),.addr(addr_sel),.wr(wr_sel),.cs(cs_inp),.data_in(data));
 assign inter = RAM0.mem[addr_sel];
 initial
 begin
	 cs_inp = 1'b1;
	 wr_sel = 1'b1;
        addr_sel = 32;
	data = 8'hFF;   
	addr_sel = 64; 
       	data = 8'hAC; 
	addr_sel = 128;
       	data = 8'h9B; 
	addr_sel = 256;
	data = 8'h8F;
	addr_sel = 512;	 $dumpfile("ram.vcd");
   	data = 8'h7F;	 $dumpvars(0,ram_3_tb);
 end

 initial
 begin
       #10 addr_sel = 32;
       #10 addr_sel = 64;
       #10 addr_sel = 128;
       #10 addr_sel = 256;
       #10 addr_sel = 512;
       #60 $finish;
 end
 
 initial
 begin
	 $monitor(" addr = %d ram[addr] = %h",addr_sel,inter);
 end

endmodule