data/full_repos/permissive/122005899/Vivado/CPU.srcs/sim_1/new/cpu_tb.v
 line:15: before: "$"
1: b'%Error: data/full_repos/permissive/122005899/Vivado/CPU.srcs/sim_1/new/cpu_tb.v:9: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/122005899/Vivado/CPU.srcs/sim_1/new/cpu_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #80 rst = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/122005899/Vivado/CPU.srcs/sim_1/new/cpu_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #9000 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122005899/Vivado/CPU.srcs/sim_1/new/cpu_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n always #20 clk = !clk;\n        ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPU_tb ();

	reg clk;
	reg rst;

	initial begin
		$dumpvars;

		clk = 0;
		rst = 1;

		#80 rst = 0;
		#9000 $finish;
	end

	always #20 clk = !clk;

	CPU cpu_dut(.clk(clk), .rst(rst));
endmodule
module CPU_tb ();


	reg clk;
	reg rst;

	initial begin
		$dumpvars;

		clk = 0;
		rst = 1;

		#80 rst = 0;
		#9000 $finish;
	end

	always #20 clk = !clk;

	CPU cpu_dut(.clk(clk), .rst(rst));
endmodule