data/full_repos/permissive/143278/ivltests/sv_unpacked_wire.v
 line:29: before: "+"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_unpacked_wire.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1 addr = idx[1:0];\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_unpacked_wire.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_unpacked_wire.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (Q !== data[addr]) begin\n  ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   localparam width = 8;

   reg clk;
   reg [1:0] addr;
   logic [width-1:0] data [0:3];

   reg [width-1:0]  Q;




   wire [width-1:0]  data_x[0:3];
   assign data_x = data;
   always @(posedge clk)
     Q <= data_x[addr];

   reg [2:0]	   idx;
   initial begin
      clk = 0;
      data[0] = 0;
      data[1] = 1;
      data[2] = 2;
      data[3] = 3;
      addr = 0;

      for (idx = 0 ; idx < 4 ; idx += 1) begin
	 clk = 0;
	 #1 addr = idx[1:0];
	 #1 clk = 1;
	 #1 if (Q !== data[addr]) begin
	    $display("FAILED -- data[%0d]==%h, Q==%h", addr, data[addr], Q);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule
module main;


   localparam width = 8;

   reg clk;
   reg [1:0] addr;
   logic [width-1:0] data [0:3];

   reg [width-1:0]  Q;




   wire [width-1:0]  data_x[0:3];
   assign data_x = data;
   always @(posedge clk)
     Q <= data_x[addr];

   reg [2:0]	   idx;
   initial begin
      clk = 0;
      data[0] = 0;
      data[1] = 1;
      data[2] = 2;
      data[3] = 3;
      addr = 0;

      for (idx = 0 ; idx < 4 ; idx += 1) begin
	 clk = 0;
	 #1 addr = idx[1:0];
	 #1 clk = 1;
	 #1 if (Q !== data[addr]) begin
	    $display("FAILED -- data[%0d]==%h, Q==%h", addr, data[addr], Q);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule