data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v:12: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("sim/waveform/out.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v:13: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,simple_sim);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v:17: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clock = ~ clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v:34: syntax error, unexpected \'@\'\n  @(posedge clock)\n  ^\n%Error: data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v:36: syntax error, unexpected \'@\'\n  repeat(12)@(posedge clock)\n            ^\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simple_sim ();
reg         clock;
reg         reset;
reg         pause;
reg         reverse;
wire [6:0]  data;

Counter7SD C7SD(clock,reset,pause,reverse,data);

initial
begin
  $dumpfile("sim/waveform/out.vcd");
  $dumpvars(0,simple_sim);
  $display("clock\treset\tpause\treverse\tdata");
end

always #5 clock = ~ clock;
always @ ( clock ) begin
  $display("%b\t%b\t%b\t%b\t%b",clock,reset,pause,reverse,data);
end

initial begin

  start;
  simple_flow;
  $finish;
end

task start;
  clock = 1;
endtask

task simple_flow; begin
  @(posedge clock)
    reset = 0;
  repeat(12)@(posedge clock)
    reset = 1;
  @(posedge clock)
    #10;
end
endtask

endmodule
module simple_sim ();

reg         clock;
reg         reset;
reg         pause;
reg         reverse;
wire [6:0]  data;

Counter7SD C7SD(clock,reset,pause,reverse,data);

initial
begin
  $dumpfile("sim/waveform/out.vcd");
  $dumpvars(0,simple_sim);
  $display("clock\treset\tpause\treverse\tdata");
end

always #5 clock = ~ clock;
always @ ( clock ) begin
  $display("%b\t%b\t%b\t%b\t%b",clock,reset,pause,reverse,data);
end

initial begin

  start;
  simple_flow;
  $finish;
end

task start;
  clock = 1;
endtask

task simple_flow; begin
  @(posedge clock)
    reset = 0;
  repeat(12)@(posedge clock)
    reset = 1;
  @(posedge clock)
    #10;
end
endtask

endmodule