data/full_repos/permissive/174242803/datapath/src/datapath.v
1: b"%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:50: Cannot find file containing module: 'dff8bit'\n   dff8bit instr_dtf1(.d(memdata),\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174242803/datapath/src,data/full_repos/permissive/174242803/dff8bit\n             data/full_repos/permissive/174242803/datapath/src,data/full_repos/permissive/174242803/dff8bit.v\n             data/full_repos/permissive/174242803/datapath/src,data/full_repos/permissive/174242803/dff8bit.sv\n             dff8bit\n             dff8bit.v\n             dff8bit.sv\n             obj_dir/dff8bit\n             obj_dir/dff8bit.v\n             obj_dir/dff8bit.sv\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:57: Cannot find file containing module: 'dff8bit'\n   dff8bit instr_dtf2(.d(memdata),\n   ^~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:64: Cannot find file containing module: 'dff8bit'\n   dff8bit instr_dtf3(.d(memdata),\n   ^~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:71: Cannot find file containing module: 'dff8bit'\n   dff8bit instr_dtf4(.d(memdata),\n   ^~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:80: Cannot find file containing module: 'dff8bit'\n   dff8bit rd_dtf1(.d(rd1),\n   ^~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:87: Cannot find file containing module: 'dff8bit'\n   dff8bit rd_dtf2(.d(rd2),\n   ^~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:94: Cannot find file containing module: 'dff8bit'\n   dff8bit aluout_dtf(.d(aluresult),\n   ^~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:101: Cannot find file containing module: 'dff8bit'\n   dff8bit pc_dtf(.d(nextpc),\n   ^~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:108: Cannot find file containing module: 'dff8bit'\n   dff8bit data_dtf(.d(memdata),\n   ^~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:118: Cannot find file containing module: 'mux'\n   mux rd1_mux(.a(to_mux_to_srca),\n   ^~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:124: Cannot find file containing module: 'mux4'\n   mux4 rd2_mux(.a(writedata),\n   ^~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:132: Cannot find file containing module: 'mux4'\n   mux4 nextpc_mux(.a(aluresult),\n   ^~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:140: Cannot find file containing module: 'mux'\n   mux adr_mux(.a(aluout),\n   ^~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:146: Cannot find file containing module: 'mux'\n   mux wd_mux(.a(data),\n   ^~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:152: Cannot find file containing module: 'mux_smallData'\n   mux_smallData wa_mux(.a(instr[13:11]),\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:160: Cannot find file containing module: 'regfile'\n   regfile test_reg(.rd1(rd1),\n   ^~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath.v:172: Cannot find file containing module: 'alu'\n   alu inst_alu(.result(aluresult),\n   ^~~\n%Error: Exiting due to 17 error(s)\n"
module datapath (adr, instr, writedata, zero, 
                 alucontrol, alusrca, alusrcb, iord, irwrite, memdata, 
		           memtoreg, pcen, pcsource, regdst, regwrite,
		           clk, reset, const_gnd) ;


   input  [2:0]  alucontrol ;
   input         alusrca    ;
   input  [1:0]  alusrcb    ;
   input 	       iord       ;
   input  [3:0]  irwrite    ;
   input  [7:0]  memdata    ;
   input 	       memtoreg   ;
   input         pcen       ;
   input 	       regdst     ;
   input 	       regwrite   ;
   input  [1:0]  pcsource   ;
   input         clk, reset ; 
   input         const_gnd  ;


   output [ 7:0] adr        ;
   output [31:0] instr      ;
   output [ 7:0] writedata  ;
   output        zero       ;


   wire   [2:0]  ra1, ra2, wa ;
   wire   [7:0]  rd1, rd2, wd ;
   wire   [7:0]  pc, nextpc   ;
   wire   [7:0]  data         ;
   wire   [7:0]  to_mux_to_srca, srca, srcb, aluresult, aluout ;
   wire   [7:0]  constx4      ;





   assign constx4 = {instr[5:0], {2{const_gnd}}};



   assign ra1 = instr[23:21];
   assign ra2 = instr[18:16];



   dff8bit instr_dtf1(.d(memdata),
           .clk(clk),
           .rst(reset),
           .en(irwrite[0]),
           .q(instr[31:24])
           );

   dff8bit instr_dtf2(.d(memdata),
           .clk(clk),
           .rst(reset),
           .en(irwrite[1]),
           .q(instr[23:16])
           );

   dff8bit instr_dtf3(.d(memdata),
           .clk(clk),
           .rst(reset),
           .en(irwrite[2]),
           .q(instr[15:8])
           );

   dff8bit instr_dtf4(.d(memdata),
           .clk(clk),
           .rst(reset),
           .en(irwrite[3]),
           .q(instr[7:0])
           );



   dff8bit rd_dtf1(.d(rd1),
           .clk(clk),
           .rst(reset),
           .en(~const_gnd),
           .q(to_mux_to_srca)
           ); 

   dff8bit rd_dtf2(.d(rd2),
         .clk(clk),
         .rst(reset),
         .en(~const_gnd),
         .q(writedata)
         );

   dff8bit aluout_dtf(.d(aluresult),
         .clk(clk),
         .rst(reset),
         .en(~const_gnd),
         .q(aluout)
         );

   dff8bit pc_dtf(.d(nextpc),
         .clk(clk),
         .rst(reset),
         .en(pcen),
         .q(pc)
         );

   dff8bit data_dtf(.d(memdata),
         .clk(clk),
         .rst(reset),
         .en(~const_gnd),
         .q(data)
         );
   



   mux rd1_mux(.a(to_mux_to_srca),
        .b(pc),
        .sel(alusrca),
        .out(srca)
        );

   mux4 rd2_mux(.a(writedata),
        .b({{7{const_gnd}}, ~const_gnd}),
        .c(instr[7:0]),
        .d(constx4),
        .sel(alusrcb),
        .out(srcb)
        );

   mux4 nextpc_mux(.a(aluresult),
        .b(aluout),
        .c(constx4),
        .d({8{const_gnd}}),
        .sel(pcsource),
        .out(nextpc)
        );

   mux adr_mux(.a(aluout),
        .b(pc),
        .sel(iord),
        .out(adr)
        );
      
   mux wd_mux(.a(data),
        .b(aluout),
        .sel(memtoreg),
        .out(wd)
        );
   
   mux_smallData wa_mux(.a(instr[13:11]),
        .b(instr[18:16]),
        .sel(regdst),
        .out(wa)
        );



   regfile test_reg(.rd1(rd1),
                    .rd2(rd2),
                    .clk(clk),
                    .regwrite(regwrite),
                    .ra1(ra1),
                    .ra2(ra2),
                    .wa(wa),
                    .wd(wd)
                    );



   alu inst_alu(.result(aluresult),
                .a(srca),
                .b(srcb),
                .alucont(alucontrol)
                );
   


   assign zero = (aluresult == 0);

endmodule
module datapath (adr, instr, writedata, zero, 
                 alucontrol, alusrca, alusrcb, iord, irwrite, memdata, 
		           memtoreg, pcen, pcsource, regdst, regwrite,
		           clk, reset, const_gnd) ;



   input  [2:0]  alucontrol ;
   input         alusrca    ;
   input  [1:0]  alusrcb    ;
   input 	       iord       ;
   input  [3:0]  irwrite    ;
   input  [7:0]  memdata    ;
   input 	       memtoreg   ;
   input         pcen       ;
   input 	       regdst     ;
   input 	       regwrite   ;
   input  [1:0]  pcsource   ;
   input         clk, reset ; 
   input         const_gnd  ;


   output [ 7:0] adr        ;
   output [31:0] instr      ;
   output [ 7:0] writedata  ;
   output        zero       ;


   wire   [2:0]  ra1, ra2, wa ;
   wire   [7:0]  rd1, rd2, wd ;
   wire   [7:0]  pc, nextpc   ;
   wire   [7:0]  data         ;
   wire   [7:0]  to_mux_to_srca, srca, srcb, aluresult, aluout ;
   wire   [7:0]  constx4      ;





   assign constx4 = {instr[5:0], {2{const_gnd}}};



   assign ra1 = instr[23:21];
   assign ra2 = instr[18:16];



   dff8bit instr_dtf1(.d(memdata),
           .clk(clk),
           .rst(reset),
           .en(irwrite[0]),
           .q(instr[31:24])
           );

   dff8bit instr_dtf2(.d(memdata),
           .clk(clk),
           .rst(reset),
           .en(irwrite[1]),
           .q(instr[23:16])
           );

   dff8bit instr_dtf3(.d(memdata),
           .clk(clk),
           .rst(reset),
           .en(irwrite[2]),
           .q(instr[15:8])
           );

   dff8bit instr_dtf4(.d(memdata),
           .clk(clk),
           .rst(reset),
           .en(irwrite[3]),
           .q(instr[7:0])
           );



   dff8bit rd_dtf1(.d(rd1),
           .clk(clk),
           .rst(reset),
           .en(~const_gnd),
           .q(to_mux_to_srca)
           ); 

   dff8bit rd_dtf2(.d(rd2),
         .clk(clk),
         .rst(reset),
         .en(~const_gnd),
         .q(writedata)
         );

   dff8bit aluout_dtf(.d(aluresult),
         .clk(clk),
         .rst(reset),
         .en(~const_gnd),
         .q(aluout)
         );

   dff8bit pc_dtf(.d(nextpc),
         .clk(clk),
         .rst(reset),
         .en(pcen),
         .q(pc)
         );

   dff8bit data_dtf(.d(memdata),
         .clk(clk),
         .rst(reset),
         .en(~const_gnd),
         .q(data)
         );
   



   mux rd1_mux(.a(to_mux_to_srca),
        .b(pc),
        .sel(alusrca),
        .out(srca)
        );

   mux4 rd2_mux(.a(writedata),
        .b({{7{const_gnd}}, ~const_gnd}),
        .c(instr[7:0]),
        .d(constx4),
        .sel(alusrcb),
        .out(srcb)
        );

   mux4 nextpc_mux(.a(aluresult),
        .b(aluout),
        .c(constx4),
        .d({8{const_gnd}}),
        .sel(pcsource),
        .out(nextpc)
        );

   mux adr_mux(.a(aluout),
        .b(pc),
        .sel(iord),
        .out(adr)
        );
      
   mux wd_mux(.a(data),
        .b(aluout),
        .sel(memtoreg),
        .out(wd)
        );
   
   mux_smallData wa_mux(.a(instr[13:11]),
        .b(instr[18:16]),
        .sel(regdst),
        .out(wa)
        );



   regfile test_reg(.rd1(rd1),
                    .rd2(rd2),
                    .clk(clk),
                    .regwrite(regwrite),
                    .ra1(ra1),
                    .ra2(ra2),
                    .wa(wa),
                    .wd(wd)
                    );



   alu inst_alu(.result(aluresult),
                .a(srca),
                .b(srcb),
                .alucont(alucontrol)
                );
   


   assign zero = (aluresult == 0);

endmodule