data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/multiply_28.v
1: b'%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/multiply_28.v:17: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                    : ... In instance multiply_28\n    out = 1\'h0;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module multiply_28 (
    input [5:0] alufn,
    input [15:0] a,
    input [15:0] b,
    output reg [15:0] out
  );
  
  
  
  always @* begin
    out = 1'h0;
    
    case (alufn[0+5-:6])
      6'h02: begin
        out = $signed(a) * $signed(b);
      end
      6'h03: begin
        out = $signed(a) / $signed(b);
      end
    endcase
  end
endmodule
module multiply_28 (
    input [5:0] alufn,
    input [15:0] a,
    input [15:0] b,
    output reg [15:0] out
  );

  
  
  
  always @* begin
    out = 1'h0;
    
    case (alufn[0+5-:6])
      6'h02: begin
        out = $signed(a) * $signed(b);
      end
      6'h03: begin
        out = $signed(a) / $signed(b);
      end
    endcase
  end
endmodule