data/full_repos/permissive/123690745/clkmips.v
1: b"%Error: data/full_repos/permissive/123690745/clkmips.v:48: Cannot find file containing module: 'Clock'\n Clock Clock\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/Clock\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/Clock.v\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/Clock.sv\n             Clock\n             Clock.v\n             Clock.sv\n             obj_dir/Clock\n             obj_dir/Clock.v\n             obj_dir/Clock.sv\n%Error: data/full_repos/permissive/123690745/clkmips.v:58: Cannot find file containing module: 'mips'\n mips mips (\n ^~~~\n%Error: Exiting due to 2 error(s)\n"
module clkmips(
    input clk_in,
    input reset,
	 output [7:0] digital_tube0,
	 output [7:0] digital_tube1,
	 output [7:0] digital_tube2,
	 output [3:0] digital_tube_sel0,
	 output [3:0] digital_tube_sel1,
	 output digital_tube_sel2,
	 
	 output [31:0] led_light,
	 
	 input [7:0] dip_switch0,
	 input [7:0] dip_switch1,
	 input [7:0] dip_switch2,
	 input [7:0] dip_switch3,
	 input [7:0] dip_switch4,
	 input [7:0] dip_switch5,
	 input [7:0] dip_switch6,
	 input [7:0] dip_switch7,
	 
	 input [7:0] user_key
	 
    );


	Clock Clock
   (
    .CLK_IN1(clk_in),

    .CLK_OUT1(clk1),
	 .CLK_OUT2(clk2)
    );
	 
	 
	 
	mips mips (
    .clk(clk1), 
    .clk2(clk2), 
    .reset(~reset), 
    .digital_tube0(digital_tube0), 
    .digital_tube1(digital_tube1), 
    .digital_tube2(digital_tube2), 
    .digital_tube_sel0(digital_tube_sel0), 
    .digital_tube_sel1(digital_tube_sel1), 
    .digital_tube_sel2(digital_tube_sel2),
	 
	 .led_light(led_light),
	 
	 .dip_switch0(dip_switch0), 
    .dip_switch1(dip_switch1), 
    .dip_switch2(dip_switch2), 
    .dip_switch3(dip_switch3), 
    .dip_switch4(dip_switch4), 
    .dip_switch5(dip_switch5), 
    .dip_switch6(dip_switch6), 
    .dip_switch7(dip_switch7),
	 
	 .user_key(user_key)
    );
	 

endmodule
module clkmips(
    input clk_in,
    input reset,
	 output [7:0] digital_tube0,
	 output [7:0] digital_tube1,
	 output [7:0] digital_tube2,
	 output [3:0] digital_tube_sel0,
	 output [3:0] digital_tube_sel1,
	 output digital_tube_sel2,
	 
	 output [31:0] led_light,
	 
	 input [7:0] dip_switch0,
	 input [7:0] dip_switch1,
	 input [7:0] dip_switch2,
	 input [7:0] dip_switch3,
	 input [7:0] dip_switch4,
	 input [7:0] dip_switch5,
	 input [7:0] dip_switch6,
	 input [7:0] dip_switch7,
	 
	 input [7:0] user_key
	 
    );



	Clock Clock
   (
    .CLK_IN1(clk_in),

    .CLK_OUT1(clk1),
	 .CLK_OUT2(clk2)
    );
	 
	 
	 
	mips mips (
    .clk(clk1), 
    .clk2(clk2), 
    .reset(~reset), 
    .digital_tube0(digital_tube0), 
    .digital_tube1(digital_tube1), 
    .digital_tube2(digital_tube2), 
    .digital_tube_sel0(digital_tube_sel0), 
    .digital_tube_sel1(digital_tube_sel1), 
    .digital_tube_sel2(digital_tube_sel2),
	 
	 .led_light(led_light),
	 
	 .dip_switch0(dip_switch0), 
    .dip_switch1(dip_switch1), 
    .dip_switch2(dip_switch2), 
    .dip_switch3(dip_switch3), 
    .dip_switch4(dip_switch4), 
    .dip_switch5(dip_switch5), 
    .dip_switch6(dip_switch6), 
    .dip_switch7(dip_switch7),
	 
	 .user_key(user_key)
    );
	 

endmodule