data/full_repos/permissive/162533945/regfile.v
1: b"%Error: data/full_repos/permissive/162533945/regfile.v:58: Cannot find file containing module: 'reg_32'\n reg_32 reg0(.in(32'b0), .out(w32), .write_enable(w0), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/reg_32\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/reg_32.v\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/reg_32.sv\n             reg_32\n             reg_32.v\n             reg_32.sv\n             obj_dir/reg_32\n             obj_dir/reg_32.v\n             obj_dir/reg_32.sv\n%Error: data/full_repos/permissive/162533945/regfile.v:59: Cannot find file containing module: 'reg_32'\n reg_32 reg1(.in(data_writeReg), .out(w33), .write_enable(w1), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:60: Cannot find file containing module: 'reg_32'\n reg_32 reg2(.in(data_writeReg), .out(w34), .write_enable(w2), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:61: Cannot find file containing module: 'reg_32'\n reg_32 reg3(.in(data_writeReg), .out(w35), .write_enable(w3), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:62: Cannot find file containing module: 'reg_32'\n reg_32 reg4(.in(data_writeReg), .out(w36), .write_enable(w4), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:63: Cannot find file containing module: 'reg_32'\n reg_32 reg5(.in(data_writeReg), .out(w37), .write_enable(w5), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:64: Cannot find file containing module: 'reg_32'\n reg_32 reg6(.in(data_writeReg), .out(w38), .write_enable(w6), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:65: Cannot find file containing module: 'reg_32'\n reg_32 reg7(.in(data_writeReg), .out(w39), .write_enable(w7), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:66: Cannot find file containing module: 'reg_32'\n reg_32 reg8(.in(data_writeReg), .out(w40), .write_enable(w8), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:67: Cannot find file containing module: 'reg_32'\n reg_32 reg9(.in(data_writeReg), .out(w41), .write_enable(w9), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:68: Cannot find file containing module: 'reg_32'\n reg_32 reg10(.in(data_writeReg), .out(w42), .write_enable(w10), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:69: Cannot find file containing module: 'reg_32'\n reg_32 reg11(.in(data_writeReg), .out(w43), .write_enable(w11), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:70: Cannot find file containing module: 'reg_32'\n reg_32 reg12(.in(data_writeReg), .out(w44), .write_enable(w12), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:71: Cannot find file containing module: 'reg_32'\n reg_32 reg13(.in(data_writeReg), .out(w45), .write_enable(w13), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:72: Cannot find file containing module: 'reg_32'\n reg_32 reg14(.in(data_writeReg), .out(w46), .write_enable(w14), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:73: Cannot find file containing module: 'reg_32'\n reg_32 reg15(.in(data_writeReg), .out(w47), .write_enable(w15), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:74: Cannot find file containing module: 'reg_32'\n reg_32 reg16(.in(data_writeReg), .out(w48), .write_enable(w16), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:75: Cannot find file containing module: 'reg_32'\n reg_32 reg17(.in(data_writeReg), .out(w49), .write_enable(w17), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:76: Cannot find file containing module: 'reg_32'\n reg_32 reg18(.in(data_writeReg), .out(w50), .write_enable(w18), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:77: Cannot find file containing module: 'reg_32'\n reg_32 reg19(.in(data_writeReg), .out(w51), .write_enable(w19), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:78: Cannot find file containing module: 'reg_32'\n reg_32 reg20(.in(data_writeReg), .out(w52), .write_enable(w20), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:79: Cannot find file containing module: 'reg_32'\n reg_32 reg21(.in(data_writeReg), .out(w53), .write_enable(w21), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:80: Cannot find file containing module: 'reg_32'\n reg_32 reg22(.in(data_writeReg), .out(w54), .write_enable(w22), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:81: Cannot find file containing module: 'reg_32'\n reg_32 reg23(.in(data_writeReg), .out(w55), .write_enable(w23), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:82: Cannot find file containing module: 'reg_32'\n reg_32 reg24(.in(data_writeReg), .out(w56), .write_enable(w24), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:83: Cannot find file containing module: 'reg_32'\n reg_32 reg25(.in(data_writeReg), .out(w57), .write_enable(w25), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:84: Cannot find file containing module: 'reg_32'\n reg_32 reg26(.in(data_writeReg), .out(w58), .write_enable(w26), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:85: Cannot find file containing module: 'reg_32'\n reg_32 reg27(.in(data_writeReg), .out(w59), .write_enable(w27), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:86: Cannot find file containing module: 'reg_32'\n reg_32 reg28(.in(data_writeReg), .out(w60), .write_enable(w28), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:87: Cannot find file containing module: 'reg_32'\n reg_32 reg29(.in(data_writeReg), .out(w61), .write_enable(w29), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:88: Cannot find file containing module: 'reg_32'\n reg_32 reg30(.in(data_writeReg), .out(w62), .write_enable(w30), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/regfile.v:89: Cannot find file containing module: 'reg_32'\n reg_32 reg31(.in(data_writeReg), .out(w63), .write_enable(w31), .clk(~clock), .reset(ctrl_reset));\n ^~~~~~\n%Error: Exiting due to 32 error(s)\n"
module decoder5to32(c0, c1, c2, c3, c4, out);

	input c0, c1, c2, c3, c4;
	output [31:0] out;
	
	wire c0n;
	wire c1n;
	wire c2n;
	wire c3n;
	wire c4n;
	
	not not0(c0n, c0);
	not not1(c1n, c1);
	not not2(c2n, c2);
	not not3(c3n, c3);
	not not4(c4n, c4);

	and and0(out[0], c4n, c3n, c2n, c1n, c0n);
	and and1(out[1], c4n, c3n, c2n, c1n, c0);
	and and2(out[2], c4n, c3n, c2n, c1, c0n);
	and and3(out[3], c4n, c3n, c2n, c1, c0);
	and and4(out[4], c4n, c3n, c2, c1n, c0n);
	and and5(out[5], c4n, c3n, c2, c1n, c0);
	and and6(out[6], c4n, c3n, c2, c1, c0n);
	and and7(out[7], c4n, c3n, c2, c1, c0);
	and and8(out[8], c4n, c3, c2n, c1n, c0n);
	and and9(out[9], c4n, c3, c2n, c1n, c0);
	and and10(out[10], c4n, c3, c2n, c1, c0n);
	and and11(out[11], c4n, c3, c2n, c1, c0);
	and and12(out[12], c4n, c3, c2, c1n, c0n);
	and and13(out[13], c4n, c3, c2, c1n, c0);
	and and14(out[14], c4n, c3, c2, c1, c0n);
	and and15(out[15], c4n, c3, c2, c1, c0);
	and and16(out[16], c4, c3n, c2n, c1n, c0n);
	and and17(out[17], c4, c3n, c2n, c1n, c0);
	and and18(out[18], c4, c3n, c2n, c1, c0n);
	and and19(out[19], c4, c3n, c2n, c1, c0);
	and and20(out[20], c4, c3n, c2, c1n, c0n);
	and and21(out[21], c4, c3n, c2, c1n, c0);
	and and22(out[22], c4, c3n, c2, c1, c0n);
	and and23(out[23], c4, c3n, c2, c1, c0);
	and and24(out[24], c4, c3, c2n, c1n, c0n);
	and and25(out[25], c4, c3, c2n, c1n, c0);
	and and26(out[26], c4, c3, c2n, c1, c0n);
	and and27(out[27], c4, c3, c2n, c1, c0);
	and and28(out[28], c4, c3, c2, c1n, c0n);
	and and29(out[29], c4, c3, c2, c1n, c0);
	and and30(out[30], c4, c3, c2, c1, c0n);
	and and31(out[31], c4, c3, c2, c1, c0);

endmodule
module decoder5to32(c0, c1, c2, c3, c4, out);


	input c0, c1, c2, c3, c4;
	output [31:0] out;
	
	wire c0n;
	wire c1n;
	wire c2n;
	wire c3n;
	wire c4n;
	
	not not0(c0n, c0);
	not not1(c1n, c1);
	not not2(c2n, c2);
	not not3(c3n, c3);
	not not4(c4n, c4);

	and and0(out[0], c4n, c3n, c2n, c1n, c0n);
	and and1(out[1], c4n, c3n, c2n, c1n, c0);
	and and2(out[2], c4n, c3n, c2n, c1, c0n);
	and and3(out[3], c4n, c3n, c2n, c1, c0);
	and and4(out[4], c4n, c3n, c2, c1n, c0n);
	and and5(out[5], c4n, c3n, c2, c1n, c0);
	and and6(out[6], c4n, c3n, c2, c1, c0n);
	and and7(out[7], c4n, c3n, c2, c1, c0);
	and and8(out[8], c4n, c3, c2n, c1n, c0n);
	and and9(out[9], c4n, c3, c2n, c1n, c0);
	and and10(out[10], c4n, c3, c2n, c1, c0n);
	and and11(out[11], c4n, c3, c2n, c1, c0);
	and and12(out[12], c4n, c3, c2, c1n, c0n);
	and and13(out[13], c4n, c3, c2, c1n, c0);
	and and14(out[14], c4n, c3, c2, c1, c0n);
	and and15(out[15], c4n, c3, c2, c1, c0);
	and and16(out[16], c4, c3n, c2n, c1n, c0n);
	and and17(out[17], c4, c3n, c2n, c1n, c0);
	and and18(out[18], c4, c3n, c2n, c1, c0n);
	and and19(out[19], c4, c3n, c2n, c1, c0);
	and and20(out[20], c4, c3n, c2, c1n, c0n);
	and and21(out[21], c4, c3n, c2, c1n, c0);
	and and22(out[22], c4, c3n, c2, c1, c0n);
	and and23(out[23], c4, c3n, c2, c1, c0);
	and and24(out[24], c4, c3, c2n, c1n, c0n);
	and and25(out[25], c4, c3, c2n, c1n, c0);
	and and26(out[26], c4, c3, c2n, c1, c0n);
	and and27(out[27], c4, c3, c2n, c1, c0);
	and and28(out[28], c4, c3, c2, c1n, c0n);
	and and29(out[29], c4, c3, c2, c1n, c0);
	and and30(out[30], c4, c3, c2, c1, c0n);
	and and31(out[31], c4, c3, c2, c1, c0);

endmodule