data/full_repos/permissive/113002755/verilog/Hex2BCD.v
1: b'%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:40: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 20 bits.\n                                                                         : ... In instance Hex2BCD\nassign oDigit6 = iHexPoints / 100000;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:41: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 20 bits.\n                                                                         : ... In instance Hex2BCD\nassign oDigit5 = (iHexPoints % 100000) / 10000;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:42: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 20 bits.\n                                                                         : ... In instance Hex2BCD\nassign oDigit4 = (iHexPoints % 10000) / 1000;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:43: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 20 bits.\n                                                                         : ... In instance Hex2BCD\nassign oDigit3 = (iHexPoints % 1000) / 100;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:44: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 20 bits.\n                                                                         : ... In instance Hex2BCD\nassign oDigit2 = (iHexPoints % 100) / 10;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Hex2BCD.v:45: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 20 bits.\n                                                                         : ... In instance Hex2BCD\nassign oDigit1 = (iHexPoints % 10);\n               ^\n%Error: Exiting due to 6 warning(s)\n'
module Hex2BCD(
	iClk,
	iHexPoints,
	oDigit1,
	oDigit2,
	oDigit3,
	oDigit4,
	oDigit5,
	oDigit6
);

input iClk;
input [19:0] iHexPoints;

output [3:0] oDigit1;
output [3:0] oDigit2;
output [3:0] oDigit3;
output [3:0] oDigit4;
output [3:0] oDigit5;
output [3:0] oDigit6;

wire [3:0] oDigit1;
wire [3:0] oDigit2;
wire [3:0] oDigit3;
wire [3:0] oDigit4;
wire [3:0] oDigit5;
wire [3:0] oDigit6;

assign oDigit6 = iHexPoints / 100000;
assign oDigit5 = (iHexPoints % 100000) / 10000;
assign oDigit4 = (iHexPoints % 10000) / 1000;
assign oDigit3 = (iHexPoints % 1000) / 100;
assign oDigit2 = (iHexPoints % 100) / 10;
assign oDigit1 = (iHexPoints % 10);


endmodule
module Hex2BCD(
	iClk,
	iHexPoints,
	oDigit1,
	oDigit2,
	oDigit3,
	oDigit4,
	oDigit5,
	oDigit6
);


input iClk;
input [19:0] iHexPoints;

output [3:0] oDigit1;
output [3:0] oDigit2;
output [3:0] oDigit3;
output [3:0] oDigit4;
output [3:0] oDigit5;
output [3:0] oDigit6;

wire [3:0] oDigit1;
wire [3:0] oDigit2;
wire [3:0] oDigit3;
wire [3:0] oDigit4;
wire [3:0] oDigit5;
wire [3:0] oDigit6;

assign oDigit6 = iHexPoints / 100000;
assign oDigit5 = (iHexPoints % 100000) / 10000;
assign oDigit4 = (iHexPoints % 10000) / 1000;
assign oDigit3 = (iHexPoints % 1000) / 100;
assign oDigit2 = (iHexPoints % 100) / 10;
assign oDigit1 = (iHexPoints % 10);


endmodule