data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/CacheSimulation.v
1: b"%Error: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/CacheSimulation.v:43: Cannot find file containing module: 'DATA_CACHE'\n DATA_CACHE d_cache(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source,data/full_repos/permissive/153690221/DATA_CACHE\n             data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source,data/full_repos/permissive/153690221/DATA_CACHE.v\n             data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source,data/full_repos/permissive/153690221/DATA_CACHE.sv\n             DATA_CACHE\n             DATA_CACHE.v\n             DATA_CACHE.sv\n             obj_dir/DATA_CACHE\n             obj_dir/DATA_CACHE.v\n             obj_dir/DATA_CACHE.sv\n%Error: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/CacheSimulation.v:57: Cannot find file containing module: 'INSTRUCTION_CACHE'\n INSTRUCTION_CACHE i_cache(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/CacheSimulation.v:68: Cannot find file containing module: 'STATISTICS'\n STATISTICS stats(\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module CACHE_SIMULATION(
	input clk,
	input [3:0] command,

	input [`AddressBits-1:0] address,
	input mode,
	input done
	);
	

	parameter READ = 4'd0;
	parameter WRITE = 4'd1;
	parameter INSTRUCTION_FETCH = 4'd2;
	parameter INVALIDATE = 4'd3;
	parameter SNOOP = 4'd4;
	parameter RESET = 4'd8;
	parameter PRINT = 4'd9;
		

	wire [31:0]
		d_read_hit,
		d_read_miss,
		d_reads,
		d_write_hit,
		d_write_miss,
		d_writes,
		i_hit,	
		i_miss,
		i_reads;
	

	DATA_CACHE d_cache(
		.clk(clk),
		.command(command),
		.address(address),
		.mode(mode),
		.DC_Read_Hit(d_read_hit),
		.DC_Read_Miss(d_read_miss),
		.DC_Reads(d_reads),
		.DC_Write_Hit(d_write_hit),
		.DC_Write_Miss(d_write_miss),
		.DC_Writes(d_writes)
		);
	

	INSTRUCTION_CACHE i_cache(
		.clk(clk),
		.command(command),
		.address(address),
		.mode(mode),
		.IC_Read_Hit(i_hit),
		.IC_Read_Miss(i_miss),
		.IC_Reads(i_reads)
		);
	

	STATISTICS stats(
		.done(done),
		.DC_Read_Hit(d_read_hit),
		.DC_Read_Miss(d_read_miss),
		.DC_Reads(d_reads),
		.DC_Write_Hit(d_write_hit),
		.DC_Write_Miss(d_write_miss),
		.DC_Writes(d_writes),
		.IC_Read_Hit(i_hit),
		.IC_Read_Miss(i_miss),
		.IC_Reads(i_reads)
		);

endmodule
module CACHE_SIMULATION(
	input clk,
	input [3:0] command,

	input [`AddressBits-1:0] address,
	input mode,
	input done
	);

	

	parameter READ = 4'd0;
	parameter WRITE = 4'd1;
	parameter INSTRUCTION_FETCH = 4'd2;
	parameter INVALIDATE = 4'd3;
	parameter SNOOP = 4'd4;
	parameter RESET = 4'd8;
	parameter PRINT = 4'd9;
		

	wire [31:0]
		d_read_hit,
		d_read_miss,
		d_reads,
		d_write_hit,
		d_write_miss,
		d_writes,
		i_hit,	
		i_miss,
		i_reads;
	

	DATA_CACHE d_cache(
		.clk(clk),
		.command(command),
		.address(address),
		.mode(mode),
		.DC_Read_Hit(d_read_hit),
		.DC_Read_Miss(d_read_miss),
		.DC_Reads(d_reads),
		.DC_Write_Hit(d_write_hit),
		.DC_Write_Miss(d_write_miss),
		.DC_Writes(d_writes)
		);
	

	INSTRUCTION_CACHE i_cache(
		.clk(clk),
		.command(command),
		.address(address),
		.mode(mode),
		.IC_Read_Hit(i_hit),
		.IC_Read_Miss(i_miss),
		.IC_Reads(i_reads)
		);
	

	STATISTICS stats(
		.done(done),
		.DC_Read_Hit(d_read_hit),
		.DC_Read_Miss(d_read_miss),
		.DC_Reads(d_reads),
		.DC_Write_Hit(d_write_hit),
		.DC_Write_Miss(d_write_miss),
		.DC_Writes(d_writes),
		.IC_Read_Hit(i_hit),
		.IC_Read_Miss(i_miss),
		.IC_Reads(i_reads)
		);

endmodule