data/full_repos/permissive/213507744/crc/encoder.v
 line:17: before: "<<"
data/verilator_xmls/8e46b779-2b51-42d6-b41d-c8f0ce715054.xml
module CRCEncoder(
  input wire clk,
  input wire [CRC_LENGTH-1:0] in,
  input wire [CRC_LENGTH-1:0] generator,
  output wire [CRC_LENGTH-1:0] out
);
  parameter CRC_LENGTH = 8;
  reg [CRC_LENGTH-1:0] crc_register = {CRC_LENGTH{1'b0}};
  assign out = crc_register;
  integer i=0;
  always @(posedge clk) begin
    crc_register = crc_register ^ in;
    for (i = 0; i < 8; i = i + 1) begin
      if (crc_register[7]) begin
        crc_register = (crc_register << 1) ^ generator;
      end else begin 
        crc_register <<= 1;
      end
    end
  end
endmodule
module CRCEncoder(
  input wire clk,
  input wire [CRC_LENGTH-1:0] in,
  input wire [CRC_LENGTH-1:0] generator,
  output wire [CRC_LENGTH-1:0] out
);

  parameter CRC_LENGTH = 8;
  reg [CRC_LENGTH-1:0] crc_register = {CRC_LENGTH{1'b0}};
  assign out = crc_register;
  integer i=0;
  always @(posedge clk) begin
    crc_register = crc_register ^ in;
    for (i = 0; i < 8; i = i + 1) begin
      if (crc_register[7]) begin
        crc_register = (crc_register << 1) ^ generator;
      end else begin 
        crc_register <<= 1;
      end
    end
  end
endmodule