data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v
1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n             char_def.vh\n             char_def.vh.v\n             char_def.vh.sv\n             obj_dir/char_def.vh\n             obj_dir/char_def.vh.v\n             obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:46: Define or directive not defined: \'`Octrl_init\'\n    assign cs   = (current_state == `Octrl_init) ? init_cs : exam_cs;\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign cs   = (current_state == `Octrl_init) ? init_cs : exam_cs;\n                                               ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:47: Define or directive not defined: \'`Octrl_init\'\n    assign sdo  = (current_state == `Octrl_init) ? init_sdo : exam_sdo;\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:47: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign sdo  = (current_state == `Octrl_init) ? init_sdo : exam_sdo;\n                                               ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:48: Define or directive not defined: \'`Octrl_init\'\n    assign sclk = (current_state == `Octrl_init) ? init_sclk : exam_sclk;\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:48: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign sclk = (current_state == `Octrl_init) ? init_sclk : exam_sclk;\n                                               ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:49: Define or directive not defined: \'`Octrl_init\'\n    assign dc   = (current_state == `Octrl_init) ? init_dc : exam_dc;\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign dc   = (current_state == `Octrl_init) ? init_dc : exam_dc;\n                                               ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:52: Define or directive not defined: \'`Octrl_init\'\n    assign init_en = (current_state == `Octrl_init) ? 1 : 0;\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign init_en = (current_state == `Octrl_init) ? 1 : 0;\n                                                  ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:53: Define or directive not defined: \'`Octrl_exam\'\n    assign exam_en = (current_state == `Octrl_exam) ? 1 : 0;\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:53: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign exam_en = (current_state == `Octrl_exam) ? 1 : 0;\n                                                  ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:83: Define or directive not defined: \'`Octrl_idle\'\n            current_state <= `Octrl_idle;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            current_state <= `Octrl_idle;\n                                        ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:86: Define or directive not defined: \'`Octrl_idle\'\n                `Octrl_idle: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:86: syntax error, unexpected \':\', expecting endcase\n                `Octrl_idle: begin\n                           ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:87: Define or directive not defined: \'`Octrl_init\'\n                    current_state <= `Octrl_init;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:89: Define or directive not defined: \'`Octrl_init\'\n                `Octrl_init: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:89: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `Octrl_init: begin\n                             ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:91: Define or directive not defined: \'`Octrl_exam\'\n                        current_state <= `Octrl_exam;\n                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:94: Define or directive not defined: \'`Octrl_exam\'\n                `Octrl_exam: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:94: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `Octrl_exam: begin\n                             ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:97: Define or directive not defined: \'`Octrl_exam\'\n                        current_state <= `Octrl_exam;\n                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:100: Define or directive not defined: \'`Octrl_done\'\n                `Octrl_done: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:101: Define or directive not defined: \'`Octrl_done\'\n                    current_state <= `Octrl_done;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_ctrl.v:104: Define or directive not defined: \'`Octrl_idle\'\n                    current_state <= `Octrl_idle;\n                                     ^~~~~~~~~~~\n%Error: Cannot continue\n'
module oled_ctrl(
    clk,
    rst,
    cs,
    sdo,
    sclk,
    dc,
    res,
    vbat,
    vdd,
    char_data,
    print_fin
    );
    input clk, rst;
    output cs, sdo, sclk, dc, res, vbat, vdd;
    input [64*8-1:0] char_data;
    output print_fin;

    wire init_cs, init_sdo, init_sclk, init_dc, init_en, init_done;
    wire exam_cs, exam_sdo, exam_sclk, exam_dc, exam_en, exam_done;
    reg [1:0] current_state;

    assign cs   = (current_state == `Octrl_init) ? init_cs : exam_cs;
    assign sdo  = (current_state == `Octrl_init) ? init_sdo : exam_sdo;
    assign sclk = (current_state == `Octrl_init) ? init_sclk : exam_sclk;
    assign dc   = (current_state == `Octrl_init) ? init_dc : exam_dc;
    assign print_fin = exam_done;

    assign init_en = (current_state == `Octrl_init) ? 1 : 0;
    assign exam_en = (current_state == `Octrl_exam) ? 1 : 0;

    oled_init o_init(
    .clk(clk),
    .rst(rst),
    .en(init_en),
    .cs(init_cs),
    .sdo(init_sdo),
    .sclk(init_sclk),
    .dc(init_dc),
    .res(res),
    .vbat(vbat),
    .vdd(vdd),
    .fin(init_done)
    );

    oled_exam o_exam(
    .clk(clk),
    .rst(rst),
    .en(exam_en),
    .cs(exam_cs),
    .sdo(exam_sdo),
    .sclk(exam_sclk),
    .dc(exam_dc),
    .fin(exam_done),
    .char_data(char_data)
    );

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            current_state <= `Octrl_idle;
        end else begin
            case(current_state)
                `Octrl_idle: begin
                    current_state <= `Octrl_init;
                end
                `Octrl_init: begin
                    if(init_done) begin
                        current_state <= `Octrl_exam;
                    end
                end
                `Octrl_exam: begin
                    if(exam_done) begin

                        current_state <= `Octrl_exam;
                    end
                end
                `Octrl_done: begin
                    current_state <= `Octrl_done;
                end
                default: begin
                    current_state <= `Octrl_idle;
                end
            endcase
        end
    end

endmodule
module oled_ctrl(
    clk,
    rst,
    cs,
    sdo,
    sclk,
    dc,
    res,
    vbat,
    vdd,
    char_data,
    print_fin
    );

    input clk, rst;
    output cs, sdo, sclk, dc, res, vbat, vdd;
    input [64*8-1:0] char_data;
    output print_fin;

    wire init_cs, init_sdo, init_sclk, init_dc, init_en, init_done;
    wire exam_cs, exam_sdo, exam_sclk, exam_dc, exam_en, exam_done;
    reg [1:0] current_state;

    assign cs   = (current_state == `Octrl_init) ? init_cs : exam_cs;
    assign sdo  = (current_state == `Octrl_init) ? init_sdo : exam_sdo;
    assign sclk = (current_state == `Octrl_init) ? init_sclk : exam_sclk;
    assign dc   = (current_state == `Octrl_init) ? init_dc : exam_dc;
    assign print_fin = exam_done;

    assign init_en = (current_state == `Octrl_init) ? 1 : 0;
    assign exam_en = (current_state == `Octrl_exam) ? 1 : 0;

    oled_init o_init(
    .clk(clk),
    .rst(rst),
    .en(init_en),
    .cs(init_cs),
    .sdo(init_sdo),
    .sclk(init_sclk),
    .dc(init_dc),
    .res(res),
    .vbat(vbat),
    .vdd(vdd),
    .fin(init_done)
    );

    oled_exam o_exam(
    .clk(clk),
    .rst(rst),
    .en(exam_en),
    .cs(exam_cs),
    .sdo(exam_sdo),
    .sclk(exam_sclk),
    .dc(exam_dc),
    .fin(exam_done),
    .char_data(char_data)
    );

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            current_state <= `Octrl_idle;
        end else begin
            case(current_state)
                `Octrl_idle: begin
                    current_state <= `Octrl_init;
                end
                `Octrl_init: begin
                    if(init_done) begin
                        current_state <= `Octrl_exam;
                    end
                end
                `Octrl_exam: begin
                    if(exam_done) begin

                        current_state <= `Octrl_exam;
                    end
                end
                `Octrl_done: begin
                    current_state <= `Octrl_done;
                end
                default: begin
                    current_state <= `Octrl_idle;
                end
            endcase
        end
    end

endmodule