data/full_repos/permissive/143278/ivltests/pr1992244.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1992244.v:6: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  wire [15:0] number =16'h20;
  wire shift_cmp = (number == (1 << 5));

  initial begin
    #1;
    if (shift_cmp === 1'b1) $display("PASSED");
    else $display("FAILED, got %b expected 1'b1", shift_cmp);
  end
endmodule
module top;

  wire [15:0] number =16'h20;
  wire shift_cmp = (number == (1 << 5));

  initial begin
    #1;
    if (shift_cmp === 1'b1) $display("PASSED");
    else $display("FAILED, got %b expected 1'b1", shift_cmp);
  end
endmodule