data/full_repos/permissive/165663914/firmware/SPI.v
data/verilator_xmls/077c53cd-ef07-4413-8bf4-3c55018a6b5c.xml
module SPI(Alex_data, SPI_data, SPI_clock, Rx_load_strobe, Tx_load_strobe, spi_clock);

input wire[31:0]Alex_data;
output reg SPI_data;
output reg SPI_clock;
output reg Rx_load_strobe;
output reg Tx_load_strobe;
input wire spi_clock;

reg [3:0]spi_state;
reg [4:0]data_count;
reg [31:0]previous_Alex_data;


always @ (posedge spi_clock)
begin
case (spi_state)
0:	begin
		if (Alex_data != previous_Alex_data)begin
			data_count <= 31;
			spi_state <= 1;
		end
		else spi_state <= 0;
	end		
1:	begin
	SPI_data <= Alex_data[data_count];
	spi_state <= 2;
	end
2:	begin
	SPI_clock <= 1'b1;
	spi_state <= 3;
	end
3:	begin
	SPI_clock <= 1'b0;
	spi_state <= 4;
	end
4:	begin
		if (data_count == 16)begin
			Tx_load_strobe <= 1'b1;
			spi_state <= 5;
		end
		else if(data_count == 0) begin
			Rx_load_strobe <= 1'b1;
			spi_state <= 6;
		end 
		else spi_state  <= 1;
	data_count <= data_count - 1'b1;
	end
5:	begin
	Tx_load_strobe <= 1'b0;
	spi_state <= 1;
	end
6:	begin
	Rx_load_strobe <= 1'b0;
	previous_Alex_data <= Alex_data;
	spi_state <= 0;
	end
	
endcase
end

endmodule
module SPI(Alex_data, SPI_data, SPI_clock, Rx_load_strobe, Tx_load_strobe, spi_clock);


input wire[31:0]Alex_data;
output reg SPI_data;
output reg SPI_clock;
output reg Rx_load_strobe;
output reg Tx_load_strobe;
input wire spi_clock;

reg [3:0]spi_state;
reg [4:0]data_count;
reg [31:0]previous_Alex_data;


always @ (posedge spi_clock)
begin
case (spi_state)
0:	begin
		if (Alex_data != previous_Alex_data)begin
			data_count <= 31;
			spi_state <= 1;
		end
		else spi_state <= 0;
	end		
1:	begin
	SPI_data <= Alex_data[data_count];
	spi_state <= 2;
	end
2:	begin
	SPI_clock <= 1'b1;
	spi_state <= 3;
	end
3:	begin
	SPI_clock <= 1'b0;
	spi_state <= 4;
	end
4:	begin
		if (data_count == 16)begin
			Tx_load_strobe <= 1'b1;
			spi_state <= 5;
		end
		else if(data_count == 0) begin
			Rx_load_strobe <= 1'b1;
			spi_state <= 6;
		end 
		else spi_state  <= 1;
	data_count <= data_count - 1'b1;
	end
5:	begin
	Tx_load_strobe <= 1'b0;
	spi_state <= 1;
	end
6:	begin
	Rx_load_strobe <= 1'b0;
	previous_Alex_data <= Alex_data;
	spi_state <= 0;
	end
	
endcase
end

endmodule