data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv
 line:255: before: "]"
1: b'%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:32: Cannot find include file: nvme_defines.sv\n`include "nvme_defines.sv" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/218463548/hardware/hdl/nvme,data/full_repos/permissive/218463548/nvme_defines.sv\n             data/full_repos/permissive/218463548/hardware/hdl/nvme,data/full_repos/permissive/218463548/nvme_defines.sv.v\n             data/full_repos/permissive/218463548/hardware/hdl/nvme,data/full_repos/permissive/218463548/nvme_defines.sv.sv\n             nvme_defines.sv\n             nvme_defines.sv.v\n             nvme_defines.sv.sv\n             obj_dir/nvme_defines.sv\n             obj_dir/nvme_defines.sv.v\n             obj_dir/nvme_defines.sv.sv\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:59: Define or directive not defined: \'`PCIE_S_ID_BITS\'\n  input  wire [`PCIE_S_ID_BITS-1:0]     pcie_s_axi_awid,\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:60: Define or directive not defined: \'`PCIE_S_ADDR_BITS\'\n  input  wire [`PCIE_S_ADDR_BITS-1:0]   pcie_s_axi_awaddr,\n               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:73: Define or directive not defined: \'`PCIE_S_ID_BITS\'\n  output logic [`PCIE_S_ID_BITS-1:0]    pcie_s_axi_bid,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:78: Define or directive not defined: \'`PCIE_S_ID_BITS\'\n  input  wire [`PCIE_S_ID_BITS-1:0]     pcie_s_axi_arid,\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:79: Define or directive not defined: \'`PCIE_S_ADDR_BITS\'\n  input  wire [`PCIE_S_ADDR_BITS-1:0]   pcie_s_axi_araddr,\n               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:86: Define or directive not defined: \'`PCIE_S_ID_BITS\'\n  output logic [`PCIE_S_ID_BITS-1:0]    pcie_s_axi_rid,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:95: Define or directive not defined: \'`TOTAL_NUM_QUEUES\'\n  logic [TX_ADDR_BITS-1:0] sq_base[`TOTAL_NUM_QUEUES+1];\n                                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:96: Define or directive not defined: \'`CMD_SSD0_Q0\'\n  assign sq_base[`CMD_SSD0_Q0] = 0;                                    \n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:96: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign sq_base[`CMD_SSD0_Q0] = 0;                                    \n                             ^\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:97: Define or directive not defined: \'`CMD_SSD0_Q1\'\n  assign sq_base[`CMD_SSD0_Q1] = `ADM_SQ_NUM * 4;                      \n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:97: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign sq_base[`CMD_SSD0_Q1] = `ADM_SQ_NUM * 4;                      \n                             ^\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:97: Define or directive not defined: \'`ADM_SQ_NUM\'\n  assign sq_base[`CMD_SSD0_Q1] = `ADM_SQ_NUM * 4;                      \n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:98: Define or directive not defined: \'`CMD_SSD1_Q0\'\n  assign sq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 4;       \n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:98: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign sq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 4;       \n                             ^\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:98: Define or directive not defined: \'`IO_SQ_NUM\'\n  assign sq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 4;       \n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:98: Define or directive not defined: \'`ADM_SQ_NUM\'\n  assign sq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 4;       \n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:99: Define or directive not defined: \'`CMD_SSD1_Q1\'\n  assign sq_base[`CMD_SSD1_Q1] = (`IO_SQ_NUM + `ADM_SQ_NUM * 2) * 4;   \n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:99: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign sq_base[`CMD_SSD1_Q1] = (`IO_SQ_NUM + `ADM_SQ_NUM * 2) * 4;   \n                             ^\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:99: Define or directive not defined: \'`IO_SQ_NUM\'\n  assign sq_base[`CMD_SSD1_Q1] = (`IO_SQ_NUM + `ADM_SQ_NUM * 2) * 4;   \n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:99: Define or directive not defined: \'`ADM_SQ_NUM\'\n  assign sq_base[`CMD_SSD1_Q1] = (`IO_SQ_NUM + `ADM_SQ_NUM * 2) * 4;   \n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:100: Define or directive not defined: \'`TOTAL_NUM_QUEUES\'\n  assign sq_base[`TOTAL_NUM_QUEUES] =  (`IO_SQ_NUM + `ADM_SQ_NUM) * 2 * 4;\n                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:100: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign sq_base[`TOTAL_NUM_QUEUES] =  (`IO_SQ_NUM + `ADM_SQ_NUM) * 2 * 4;\n                                  ^\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:100: Define or directive not defined: \'`IO_SQ_NUM\'\n  assign sq_base[`TOTAL_NUM_QUEUES] =  (`IO_SQ_NUM + `ADM_SQ_NUM) * 2 * 4;\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:100: Define or directive not defined: \'`ADM_SQ_NUM\'\n  assign sq_base[`TOTAL_NUM_QUEUES] =  (`IO_SQ_NUM + `ADM_SQ_NUM) * 2 * 4;\n                                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:108: Define or directive not defined: \'`PCIE_SSD0_SQ0_ADDR\'\n      `PCIE_SSD0_SQ0_ADDR: begin\n      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:108: syntax error, unexpected \':\', expecting endcase\n      `PCIE_SSD0_SQ0_ADDR: begin\n                         ^\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:109: Define or directive not defined: \'`CMD_SSD0_Q0\'\n        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD0_Q0];\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:111: Define or directive not defined: \'`PCIE_SSD0_SQ1_ADDR\'\n      `PCIE_SSD0_SQ1_ADDR: begin\n      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:111: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      `PCIE_SSD0_SQ1_ADDR: begin\n                           ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:112: Define or directive not defined: \'`CMD_SSD0_Q1\'\n        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD0_Q1];\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:114: Define or directive not defined: \'`PCIE_SSD1_SQ0_ADDR\'\n      `PCIE_SSD1_SQ0_ADDR: begin\n      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:114: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      `PCIE_SSD1_SQ0_ADDR: begin\n                           ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:115: Define or directive not defined: \'`CMD_SSD1_Q0\'\n        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD1_Q0];\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:117: Define or directive not defined: \'`PCIE_SSD1_SQ1_ADDR\'\n      `PCIE_SSD1_SQ1_ADDR: begin\n      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:117: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      `PCIE_SSD1_SQ1_ADDR: begin\n                           ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:118: Define or directive not defined: \'`CMD_SSD1_Q1\'\n        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD1_Q1];\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:122: syntax error, unexpected \':\', expecting clocking\n      default: begin\n             ^\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:123: Define or directive not defined: \'`TOTAL_NUM_QUEUES\'\n        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`TOTAL_NUM_QUEUES];\n                                                            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:199: Define or directive not defined: \'`TOTAL_NUM_QUEUES\'\n  logic [RX_ADDR_BITS-1:0] cq_base[`TOTAL_NUM_QUEUES+1];\n                                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:200: Define or directive not defined: \'`CMD_SSD0_Q0\'\n  assign cq_base[`CMD_SSD0_Q0] = 0;                                    \n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:200: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign cq_base[`CMD_SSD0_Q0] = 0;                                    \n                             ^\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:201: Define or directive not defined: \'`CMD_SSD0_Q1\'\n  assign cq_base[`CMD_SSD0_Q1] = `ADM_SQ_NUM * 1;                      \n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:201: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign cq_base[`CMD_SSD0_Q1] = `ADM_SQ_NUM * 1;                      \n                             ^\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:201: Define or directive not defined: \'`ADM_SQ_NUM\'\n  assign cq_base[`CMD_SSD0_Q1] = `ADM_SQ_NUM * 1;                      \n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:202: Define or directive not defined: \'`CMD_SSD1_Q0\'\n  assign cq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 1;       \n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:202: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign cq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 1;       \n                             ^\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:202: Define or directive not defined: \'`IO_SQ_NUM\'\n  assign cq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 1;       \n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:202: Define or directive not defined: \'`ADM_SQ_NUM\'\n  assign cq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 1;       \n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/hdl/nvme/nvme_pcie_slave.sv:203: Define or directive not defined: \'`CMD_SSD1_Q1\'\n  assign cq_base[`CMD_SSD1_Q1] = (`IO_SQ_NUM + `ADM_SQ_NUM * 2) * 1;   \n                 ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module nvme_pcie_slave #
(
  parameter integer TX_ADDR_BITS = 12,
  parameter integer RX_ADDR_BITS = 10
)
(
  input wire                            axi_aclk,
  input wire                            axi_aresetn,
  output logic                          init_done,


  output logic                          tx_read,
  output logic [TX_ADDR_BITS-1:0]       tx_raddr,
  input wire [127:0]                    tx_rdata,


  output logic                          rx_write_valid,
  output logic [3:0]                    rx_write,
  output logic [RX_ADDR_BITS-1:0]       rx_waddr,
  output logic [127:0]                  rx_wdata,


  input  wire [`PCIE_S_ID_BITS-1:0]     pcie_s_axi_awid,
  input  wire [`PCIE_S_ADDR_BITS-1:0]   pcie_s_axi_awaddr,
  input  wire [7:0]                     pcie_s_axi_awlen,
  input  wire [2:0]                     pcie_s_axi_awsize,
  input  wire [1:0]                     pcie_s_axi_awburst,
  input  wire                           pcie_s_axi_awvalid,
  output logic                          pcie_s_axi_awready,

  input  wire [127:0]                   pcie_s_axi_wdata,
  input  wire [15:0]                    pcie_s_axi_wstrb,
  input  wire                           pcie_s_axi_wlast,
  input  wire                           pcie_s_axi_wvalid,
  output logic                          pcie_s_axi_wready,

  output logic [`PCIE_S_ID_BITS-1:0]    pcie_s_axi_bid,
  output logic [1:0]                    pcie_s_axi_bresp,
  output logic                          pcie_s_axi_bvalid,
  input  wire                           pcie_s_axi_bready,

  input  wire [`PCIE_S_ID_BITS-1:0]     pcie_s_axi_arid,
  input  wire [`PCIE_S_ADDR_BITS-1:0]   pcie_s_axi_araddr,
  input  wire [7:0]                     pcie_s_axi_arlen,
  input  wire [2:0]                     pcie_s_axi_arsize,
  input  wire [1:0]                     pcie_s_axi_arburst,
  input  wire                           pcie_s_axi_arvalid,
  output logic                          pcie_s_axi_arready,

  output logic [`PCIE_S_ID_BITS-1:0]    pcie_s_axi_rid,
  output logic [127:0]                  pcie_s_axi_rdata,
  output logic [1:0]                    pcie_s_axi_rresp,
  output logic                          pcie_s_axi_rlast,
  output logic                          pcie_s_axi_rvalid,
  input  wire                           pcie_s_axi_rready
);


  logic [TX_ADDR_BITS-1:0] sq_base[`TOTAL_NUM_QUEUES+1];
  assign sq_base[`CMD_SSD0_Q0] = 0;
  assign sq_base[`CMD_SSD0_Q1] = `ADM_SQ_NUM * 4;
  assign sq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 4;
  assign sq_base[`CMD_SSD1_Q1] = (`IO_SQ_NUM + `ADM_SQ_NUM * 2) * 4;
  assign sq_base[`TOTAL_NUM_QUEUES] =  (`IO_SQ_NUM + `ADM_SQ_NUM) * 2 * 4;
  logic [TX_ADDR_BITS-1:0]       decode_raddr;

  always @(pcie_s_axi_araddr)
  begin : READ_DECODE_P


    unique case ({pcie_s_axi_araddr[27 +: 4], 27'h000_0000})
      `PCIE_SSD0_SQ0_ADDR: begin
        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD0_Q0];
      end
      `PCIE_SSD0_SQ1_ADDR: begin
        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD0_Q1];
      end
      `PCIE_SSD1_SQ0_ADDR: begin
        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD1_Q0];
      end
      `PCIE_SSD1_SQ1_ADDR: begin
        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD1_Q1];
      end


      default: begin
        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`TOTAL_NUM_QUEUES];
      end
    endcase
  end


  logic read_busy;
  logic read_burst;
  logic [7:0] read_count;
  logic tx_readd;

  always @(posedge axi_aclk, negedge axi_aresetn)
  begin : READ_P
    if (!axi_aresetn) begin
      pcie_s_axi_arready <= 1'b0;
      pcie_s_axi_rid <= 'd0;
      pcie_s_axi_rdata <= 128'h0000000000000000;
      pcie_s_axi_rresp <= 2'b00;
      pcie_s_axi_rlast <= 1'b0;
      pcie_s_axi_rvalid <= 1'b0;
      tx_read <= 1'b0;
      tx_readd <= 1'b0;
      tx_raddr <= 'd0;
      read_busy <= 1'b0;
      read_burst <= 1'b0;
      read_count <= 'd0;
    end else begin
      tx_read <= 1'b0;
      tx_readd <= tx_read;
      if ((pcie_s_axi_arvalid && pcie_s_axi_arready) || tx_read || read_busy) begin
        pcie_s_axi_arready <= 1'b0;
      end else begin
        pcie_s_axi_arready <= 1'b1;
      end

      if (tx_read && !read_busy) begin
        read_busy <= 1'b1;
      end else if (pcie_s_axi_rvalid && pcie_s_axi_rlast && pcie_s_axi_rready) begin
        read_busy <= 1'b0;
      end

      if (pcie_s_axi_arvalid && pcie_s_axi_arready) begin
        read_burst <= (pcie_s_axi_arburst==2'b01);
        read_count <= pcie_s_axi_arlen;
        tx_read <= 1'b1;

        tx_raddr <= decode_raddr;
        pcie_s_axi_rid <= pcie_s_axi_arid;

        pcie_s_axi_rresp <= 2'b00;
      end else if (pcie_s_axi_rready && read_count > 0) begin
        if (!tx_read) begin
          tx_read <= 1'b1;

          tx_raddr <= tx_raddr + 1;
          read_count <= read_count - 1;
        end
      end

      if (read_busy) begin
        if (tx_readd) begin
          pcie_s_axi_rvalid <= 1'b1;
          pcie_s_axi_rdata <= tx_rdata;
          if (read_count==0) begin
            pcie_s_axi_rlast <= 1'b1;
          end else begin
            pcie_s_axi_rlast <= 1'b0;
          end
        end else if (pcie_s_axi_rready) begin
          pcie_s_axi_rvalid <= 1'b0;
        end
      end
    end
  end


  logic [RX_ADDR_BITS-1:0] cq_base[`TOTAL_NUM_QUEUES+1];
  assign cq_base[`CMD_SSD0_Q0] = 0;
  assign cq_base[`CMD_SSD0_Q1] = `ADM_SQ_NUM * 1;
  assign cq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 1;
  assign cq_base[`CMD_SSD1_Q1] = (`IO_SQ_NUM + `ADM_SQ_NUM * 2) * 1;
  assign cq_base[`TOTAL_NUM_QUEUES] =  (`IO_SQ_NUM + `ADM_SQ_NUM) * 2 * 1;
  logic [RX_ADDR_BITS-1:0]       decode_waddr;

  always @(pcie_s_axi_awaddr)
  begin : WRITE_DECODE_P


    unique case ({pcie_s_axi_awaddr[27 +: 4], 27'h000_0000})
      `PCIE_SSD0_CQ0_ADDR: begin
        decode_waddr = pcie_s_axi_awaddr[4 +: 12] + cq_base[`CMD_SSD0_Q0];
      end
      `PCIE_SSD0_CQ1_ADDR: begin
        decode_waddr = pcie_s_axi_awaddr[4 +: 12] + cq_base[`CMD_SSD0_Q1];
      end
      `PCIE_SSD1_CQ0_ADDR: begin
        decode_waddr = pcie_s_axi_awaddr[4 +: 12] + cq_base[`CMD_SSD1_Q0];
      end
      `PCIE_SSD1_CQ1_ADDR: begin
        decode_waddr = pcie_s_axi_awaddr[4 +: 12] + cq_base[`CMD_SSD1_Q1];
      end


      default: begin
        decode_waddr = pcie_s_axi_awaddr[4 +: 12] + cq_base[`TOTAL_NUM_QUEUES];
      end
    endcase
  end


  localparam integer RX_DEPTH = (`ADM_CQ_NUM * 2 + `IO_CQ_NUM * 2 + `DATA_CQ_NUM) * 1;

  logic write_busy;
  logic write_burst;
  logic [7:0] write_count;
  logic write_first;

  always @(posedge axi_aclk, negedge axi_aresetn)
  begin : WRITE_P
    if (!axi_aresetn) begin
      init_done <= 1'b0;
      write_busy <= 1'b0;
      write_burst <= 1'b0;
      write_count <= 'd0;
      write_first <= 1'b0;
      rx_write_valid <= 1'b0;
      rx_write <= 'd0;
      rx_waddr <= 'd0;
      rx_wdata <= 'd0;
      pcie_s_axi_awready <= 1'b0;
      pcie_s_axi_wready <= 1'b0;
      pcie_s_axi_bid <= 'd0;
      pcie_s_axi_bresp <= 2'b00;
      pcie_s_axi_bvalid <= 1'b0;
    end else begin
      rx_write_valid <= 1'b0;
      rx_write <= 'd0;

      if (!init_done) begin
        pcie_s_axi_wready <= 1'b0;
        rx_write <= 4'hf;
        rx_wdata <= 'd0;
        if (|rx_write) begin
          rx_waddr <= rx_waddr + 1;
        end else begin
          rx_waddr <= 'd0;
        end
        if (rx_waddr==RX_DEPTH-2) begin
          init_done <= 1'b1;
        end
      end else begin

        if ((pcie_s_axi_awvalid && pcie_s_axi_awready) && !write_busy) begin
          write_busy <= 1'b1;
        end else if (pcie_s_axi_bvalid && pcie_s_axi_bready) begin
          write_busy <= 1'b0;
        end
        if ((pcie_s_axi_awvalid && pcie_s_axi_awready) || write_busy) begin
          pcie_s_axi_awready <= 1'b0;
        end else if (!write_busy) begin
          pcie_s_axi_awready <= 1'b1;
        end

        if (pcie_s_axi_awvalid && pcie_s_axi_awready) begin
          write_burst <= (pcie_s_axi_awburst==2'b01);
          write_count <= pcie_s_axi_awlen;
          write_first <= ~(pcie_s_axi_wvalid & pcie_s_axi_wready);
          rx_waddr <= decode_waddr;
          pcie_s_axi_bid <= pcie_s_axi_awid;
        end else if (write_busy && (pcie_s_axi_wvalid & pcie_s_axi_wready) && (write_count > 0 || write_first)) begin
          write_first <= 1'b0;

          if (!write_first) begin
            if (write_burst) begin
              rx_waddr <= rx_waddr + 1;
            end
            write_count <= write_count - 1;
          end
        end

        if (pcie_s_axi_awvalid && pcie_s_axi_awready) begin
          pcie_s_axi_wready <= 1'b1;
        end else if (pcie_s_axi_wvalid && pcie_s_axi_wlast && pcie_s_axi_wready) begin
          pcie_s_axi_wready <= 1'b0;
        end

        if (pcie_s_axi_wvalid && pcie_s_axi_wready) begin

          for (int i=0; i<4; i++) begin
            if (&pcie_s_axi_wstrb[i*4 +: 4]) begin
              rx_write[i] <= 1'b1;
              rx_wdata[i*32 +: 32] <= pcie_s_axi_wdata[i*32 +: 32];
            end
          end

          if (&pcie_s_axi_wstrb[3*4 +: 4]) begin
            rx_write_valid <= 1'b1;
          end
        end
      end

      if (pcie_s_axi_wvalid && pcie_s_axi_wlast && pcie_s_axi_wready) begin
        pcie_s_axi_bvalid <= 1'b1;

        pcie_s_axi_bresp <= 2'b00;
      end else if (pcie_s_axi_bready) begin
        pcie_s_axi_bvalid <= 1'b0;
      end
    end
  end

endmodule
module nvme_pcie_slave #
(
  parameter integer TX_ADDR_BITS = 12,
  parameter integer RX_ADDR_BITS = 10
)
(
  input wire                            axi_aclk,
  input wire                            axi_aresetn,
  output logic                          init_done,


  output logic                          tx_read,
  output logic [TX_ADDR_BITS-1:0]       tx_raddr,
  input wire [127:0]                    tx_rdata,


  output logic                          rx_write_valid,
  output logic [3:0]                    rx_write,
  output logic [RX_ADDR_BITS-1:0]       rx_waddr,
  output logic [127:0]                  rx_wdata,


  input  wire [`PCIE_S_ID_BITS-1:0]     pcie_s_axi_awid,
  input  wire [`PCIE_S_ADDR_BITS-1:0]   pcie_s_axi_awaddr,
  input  wire [7:0]                     pcie_s_axi_awlen,
  input  wire [2:0]                     pcie_s_axi_awsize,
  input  wire [1:0]                     pcie_s_axi_awburst,
  input  wire                           pcie_s_axi_awvalid,
  output logic                          pcie_s_axi_awready,

  input  wire [127:0]                   pcie_s_axi_wdata,
  input  wire [15:0]                    pcie_s_axi_wstrb,
  input  wire                           pcie_s_axi_wlast,
  input  wire                           pcie_s_axi_wvalid,
  output logic                          pcie_s_axi_wready,

  output logic [`PCIE_S_ID_BITS-1:0]    pcie_s_axi_bid,
  output logic [1:0]                    pcie_s_axi_bresp,
  output logic                          pcie_s_axi_bvalid,
  input  wire                           pcie_s_axi_bready,

  input  wire [`PCIE_S_ID_BITS-1:0]     pcie_s_axi_arid,
  input  wire [`PCIE_S_ADDR_BITS-1:0]   pcie_s_axi_araddr,
  input  wire [7:0]                     pcie_s_axi_arlen,
  input  wire [2:0]                     pcie_s_axi_arsize,
  input  wire [1:0]                     pcie_s_axi_arburst,
  input  wire                           pcie_s_axi_arvalid,
  output logic                          pcie_s_axi_arready,

  output logic [`PCIE_S_ID_BITS-1:0]    pcie_s_axi_rid,
  output logic [127:0]                  pcie_s_axi_rdata,
  output logic [1:0]                    pcie_s_axi_rresp,
  output logic                          pcie_s_axi_rlast,
  output logic                          pcie_s_axi_rvalid,
  input  wire                           pcie_s_axi_rready
);



  logic [TX_ADDR_BITS-1:0] sq_base[`TOTAL_NUM_QUEUES+1];
  assign sq_base[`CMD_SSD0_Q0] = 0;
  assign sq_base[`CMD_SSD0_Q1] = `ADM_SQ_NUM * 4;
  assign sq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 4;
  assign sq_base[`CMD_SSD1_Q1] = (`IO_SQ_NUM + `ADM_SQ_NUM * 2) * 4;
  assign sq_base[`TOTAL_NUM_QUEUES] =  (`IO_SQ_NUM + `ADM_SQ_NUM) * 2 * 4;
  logic [TX_ADDR_BITS-1:0]       decode_raddr;

  always @(pcie_s_axi_araddr)
  begin : READ_DECODE_P


    unique case ({pcie_s_axi_araddr[27 +: 4], 27'h000_0000})
      `PCIE_SSD0_SQ0_ADDR: begin
        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD0_Q0];
      end
      `PCIE_SSD0_SQ1_ADDR: begin
        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD0_Q1];
      end
      `PCIE_SSD1_SQ0_ADDR: begin
        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD1_Q0];
      end
      `PCIE_SSD1_SQ1_ADDR: begin
        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`CMD_SSD1_Q1];
      end


      default: begin
        decode_raddr = pcie_s_axi_araddr[4 +: 12] + sq_base[`TOTAL_NUM_QUEUES];
      end
    endcase
  end


  logic read_busy;
  logic read_burst;
  logic [7:0] read_count;
  logic tx_readd;

  always @(posedge axi_aclk, negedge axi_aresetn)
  begin : READ_P
    if (!axi_aresetn) begin
      pcie_s_axi_arready <= 1'b0;
      pcie_s_axi_rid <= 'd0;
      pcie_s_axi_rdata <= 128'h0000000000000000;
      pcie_s_axi_rresp <= 2'b00;
      pcie_s_axi_rlast <= 1'b0;
      pcie_s_axi_rvalid <= 1'b0;
      tx_read <= 1'b0;
      tx_readd <= 1'b0;
      tx_raddr <= 'd0;
      read_busy <= 1'b0;
      read_burst <= 1'b0;
      read_count <= 'd0;
    end else begin
      tx_read <= 1'b0;
      tx_readd <= tx_read;
      if ((pcie_s_axi_arvalid && pcie_s_axi_arready) || tx_read || read_busy) begin
        pcie_s_axi_arready <= 1'b0;
      end else begin
        pcie_s_axi_arready <= 1'b1;
      end

      if (tx_read && !read_busy) begin
        read_busy <= 1'b1;
      end else if (pcie_s_axi_rvalid && pcie_s_axi_rlast && pcie_s_axi_rready) begin
        read_busy <= 1'b0;
      end

      if (pcie_s_axi_arvalid && pcie_s_axi_arready) begin
        read_burst <= (pcie_s_axi_arburst==2'b01);
        read_count <= pcie_s_axi_arlen;
        tx_read <= 1'b1;

        tx_raddr <= decode_raddr;
        pcie_s_axi_rid <= pcie_s_axi_arid;

        pcie_s_axi_rresp <= 2'b00;
      end else if (pcie_s_axi_rready && read_count > 0) begin
        if (!tx_read) begin
          tx_read <= 1'b1;

          tx_raddr <= tx_raddr + 1;
          read_count <= read_count - 1;
        end
      end

      if (read_busy) begin
        if (tx_readd) begin
          pcie_s_axi_rvalid <= 1'b1;
          pcie_s_axi_rdata <= tx_rdata;
          if (read_count==0) begin
            pcie_s_axi_rlast <= 1'b1;
          end else begin
            pcie_s_axi_rlast <= 1'b0;
          end
        end else if (pcie_s_axi_rready) begin
          pcie_s_axi_rvalid <= 1'b0;
        end
      end
    end
  end


  logic [RX_ADDR_BITS-1:0] cq_base[`TOTAL_NUM_QUEUES+1];
  assign cq_base[`CMD_SSD0_Q0] = 0;
  assign cq_base[`CMD_SSD0_Q1] = `ADM_SQ_NUM * 1;
  assign cq_base[`CMD_SSD1_Q0] = (`IO_SQ_NUM + `ADM_SQ_NUM) * 1;
  assign cq_base[`CMD_SSD1_Q1] = (`IO_SQ_NUM + `ADM_SQ_NUM * 2) * 1;
  assign cq_base[`TOTAL_NUM_QUEUES] =  (`IO_SQ_NUM + `ADM_SQ_NUM) * 2 * 1;
  logic [RX_ADDR_BITS-1:0]       decode_waddr;

  always @(pcie_s_axi_awaddr)
  begin : WRITE_DECODE_P


    unique case ({pcie_s_axi_awaddr[27 +: 4], 27'h000_0000})
      `PCIE_SSD0_CQ0_ADDR: begin
        decode_waddr = pcie_s_axi_awaddr[4 +: 12] + cq_base[`CMD_SSD0_Q0];
      end
      `PCIE_SSD0_CQ1_ADDR: begin
        decode_waddr = pcie_s_axi_awaddr[4 +: 12] + cq_base[`CMD_SSD0_Q1];
      end
      `PCIE_SSD1_CQ0_ADDR: begin
        decode_waddr = pcie_s_axi_awaddr[4 +: 12] + cq_base[`CMD_SSD1_Q0];
      end
      `PCIE_SSD1_CQ1_ADDR: begin
        decode_waddr = pcie_s_axi_awaddr[4 +: 12] + cq_base[`CMD_SSD1_Q1];
      end


      default: begin
        decode_waddr = pcie_s_axi_awaddr[4 +: 12] + cq_base[`TOTAL_NUM_QUEUES];
      end
    endcase
  end


  localparam integer RX_DEPTH = (`ADM_CQ_NUM * 2 + `IO_CQ_NUM * 2 + `DATA_CQ_NUM) * 1;

  logic write_busy;
  logic write_burst;
  logic [7:0] write_count;
  logic write_first;

  always @(posedge axi_aclk, negedge axi_aresetn)
  begin : WRITE_P
    if (!axi_aresetn) begin
      init_done <= 1'b0;
      write_busy <= 1'b0;
      write_burst <= 1'b0;
      write_count <= 'd0;
      write_first <= 1'b0;
      rx_write_valid <= 1'b0;
      rx_write <= 'd0;
      rx_waddr <= 'd0;
      rx_wdata <= 'd0;
      pcie_s_axi_awready <= 1'b0;
      pcie_s_axi_wready <= 1'b0;
      pcie_s_axi_bid <= 'd0;
      pcie_s_axi_bresp <= 2'b00;
      pcie_s_axi_bvalid <= 1'b0;
    end else begin
      rx_write_valid <= 1'b0;
      rx_write <= 'd0;

      if (!init_done) begin
        pcie_s_axi_wready <= 1'b0;
        rx_write <= 4'hf;
        rx_wdata <= 'd0;
        if (|rx_write) begin
          rx_waddr <= rx_waddr + 1;
        end else begin
          rx_waddr <= 'd0;
        end
        if (rx_waddr==RX_DEPTH-2) begin
          init_done <= 1'b1;
        end
      end else begin

        if ((pcie_s_axi_awvalid && pcie_s_axi_awready) && !write_busy) begin
          write_busy <= 1'b1;
        end else if (pcie_s_axi_bvalid && pcie_s_axi_bready) begin
          write_busy <= 1'b0;
        end
        if ((pcie_s_axi_awvalid && pcie_s_axi_awready) || write_busy) begin
          pcie_s_axi_awready <= 1'b0;
        end else if (!write_busy) begin
          pcie_s_axi_awready <= 1'b1;
        end

        if (pcie_s_axi_awvalid && pcie_s_axi_awready) begin
          write_burst <= (pcie_s_axi_awburst==2'b01);
          write_count <= pcie_s_axi_awlen;
          write_first <= ~(pcie_s_axi_wvalid & pcie_s_axi_wready);
          rx_waddr <= decode_waddr;
          pcie_s_axi_bid <= pcie_s_axi_awid;
        end else if (write_busy && (pcie_s_axi_wvalid & pcie_s_axi_wready) && (write_count > 0 || write_first)) begin
          write_first <= 1'b0;

          if (!write_first) begin
            if (write_burst) begin
              rx_waddr <= rx_waddr + 1;
            end
            write_count <= write_count - 1;
          end
        end

        if (pcie_s_axi_awvalid && pcie_s_axi_awready) begin
          pcie_s_axi_wready <= 1'b1;
        end else if (pcie_s_axi_wvalid && pcie_s_axi_wlast && pcie_s_axi_wready) begin
          pcie_s_axi_wready <= 1'b0;
        end

        if (pcie_s_axi_wvalid && pcie_s_axi_wready) begin

          for (int i=0; i<4; i++) begin
            if (&pcie_s_axi_wstrb[i*4 +: 4]) begin
              rx_write[i] <= 1'b1;
              rx_wdata[i*32 +: 32] <= pcie_s_axi_wdata[i*32 +: 32];
            end
          end

          if (&pcie_s_axi_wstrb[3*4 +: 4]) begin
            rx_write_valid <= 1'b1;
          end
        end
      end

      if (pcie_s_axi_wvalid && pcie_s_axi_wlast && pcie_s_axi_wready) begin
        pcie_s_axi_bvalid <= 1'b1;

        pcie_s_axi_bresp <= 2'b00;
      end else if (pcie_s_axi_bready) begin
        pcie_s_axi_bvalid <= 1'b0;
      end
    end
  end

endmodule