data/full_repos/permissive/109231608/bitrev_files/per_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #3.0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #CLOCK_TIME;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #CLOCK_TIME;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:111: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #3.0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #CLOCK_TIME;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:145: Unsupported: Ignoring delay on this delayed statement.\n    #CLOCK_TIME;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:204: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_TIME/2) clk=~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:221: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:222: Unsupported: Ignoring delay on this delayed statement.\n  #3.0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:235: Unsupported: Ignoring delay on this delayed statement.\n    #CLOCK_TIME;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:250: Unsupported: Ignoring delay on this delayed statement.\n    #CLOCK_TIME;\n    ^\n%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:75: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                       : ... Top module \'per_p2_test\'\nmodule per_p2_test;\n       ^~~~~~~~~~~\n                                                                                       : ... Top module \'per_p4_test\'\nmodule per_p4_test;\n       ^~~~~~~~~~~\n                                                                                       : ... Top module \'per_p8_test\'\nmodule per_p8_test;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:176: Cannot find file containing module: \'per_dp8_888_r\'\n per_dp8_888_r per_instance(\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r\n             data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r.v\n             data/full_repos/permissive/109231608/bitrev_files,data/full_repos/permissive/109231608/per_dp8_888_r.sv\n             per_dp8_888_r\n             per_dp8_888_r.v\n             per_dp8_888_r.sv\n             obj_dir/per_dp8_888_r\n             obj_dir/per_dp8_888_r.v\n             obj_dir/per_dp8_888_r.sv\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:236: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n    data_in[0] = DP*i;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:237: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[1] = DP*i+1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:238: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[2] = DP*i+2;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:239: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[3] = DP*i+3;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:240: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[4] = DP*i+4;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:241: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[5] = DP*i+5;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:242: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[6] = DP*i+6;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:243: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[7] = DP*i+7;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:251: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n    data_in[0] = DP*i;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:252: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[1] = DP*i+1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:253: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[2] = DP*i+2;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:254: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[3] = DP*i+3;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:255: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[4] = DP*i+4;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:256: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[5] = DP*i+5;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:257: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[6] = DP*i+6;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:258: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p8_test\n          data_in[7] = DP*i+7;\n                     ^\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:91: Cannot find file containing module: \'per_dp4_0_r\'\n per_dp4_0_r per_instance(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:135: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n                                                                                     : ... In instance per_p4_test\n    data_in[0] = 4*i;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:136: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p4_test\n    data_in[1] = 4*i+1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:137: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p4_test\n    data_in[2] = 4*i+2;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:138: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p4_test\n    data_in[3] = 4*i+3;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:146: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n                                                                                     : ... In instance per_p4_test\n    data_in[0] = 4*i;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:147: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p4_test\n    data_in[1] = 4*i+1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:148: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p4_test\n    data_in[2] = 4*i+2;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:149: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                     : ... In instance per_p4_test\n    data_in[3] = 4*i+3;\n               ^\n%Error: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:19: Cannot find file containing module: \'per_dp2_0_r\'\n    per_dp2_0_r per_instance(\n    ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:54: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n                                                                                    : ... In instance per_p2_test\n    data_in[0] = 2*i;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:55: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                    : ... In instance per_p2_test\n    data_in[1] = 2*i+1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:64: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                    : ... In instance per_p2_test\n    data_in[0] = 2*i+0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_testbench.v:65: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                    : ... In instance per_p2_test\n    data_in[1] = 2*i+1;\n               ^\n%Error: Exiting due to 3 error(s), 44 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module per_p4_test;
    parameter CLOCK_TIME = 5.0;
    parameter DATA_WIDTH = 16;
    parameter SIZE = 256;
    parameter DP = 4;

	reg clk;
	reg rst;
	reg [DATA_WIDTH-1:0] data_in [DP-1:0];
	reg ctrl_in;


	wire [DATA_WIDTH-1:0] data_out [DP-1:0];
	wire ctrl_out;


	per_dp4_0_r per_instance(




    .inData_0(data_in[0]),
    .inData_1(data_in[1]),
	.inData_2(data_in[2]),
    .inData_3(data_in[3]),
    .outData_0(data_out[0]),
    .outData_1(data_out[1]),
	.outData_2(data_out[2]),
    .outData_3(data_out[3]),
    .in_start(ctrl_in),                        
    .out_start(ctrl_out),                       
    .clk(clk),                             
    .rst(rst)                              
    );  
    
	integer i;
	always #(CLOCK_TIME/2) clk=~clk;
	
	initial begin

		clk = 0;
		rst = 1;
		data_in[0] = {DATA_WIDTH{1'b0}};
		data_in[1] = {DATA_WIDTH{1'b0}};
		data_in[2] = {DATA_WIDTH{1'b0}};
		data_in[3] = {DATA_WIDTH{1'b0}};
		ctrl_in = 0;


		#100;
		#3.0;
		rst = 0;
		data_in[0] = 0;
		data_in[1] = 0;
		data_in[2] = {DATA_WIDTH{1'b0}};
		data_in[3] = {DATA_WIDTH{1'b0}};
		ctrl_in = 1;
		
		for(i=0; i<SIZE/DP; i=i+1)begin
		  #CLOCK_TIME;
		  data_in[0] = 4*i;
		  data_in[1] = 4*i+1;
		  data_in[2] = 4*i+2;
		  data_in[3] = 4*i+3;
		  ctrl_in = 0;
		end
		  
		ctrl_in = 1;		  
        
		for(i=0; i<SIZE/DP; i=i+1)begin
		  #CLOCK_TIME;
		  data_in[0] = 4*i;
		  data_in[1] = 4*i+1;
		  data_in[2] = 4*i+2;
		  data_in[3] = 4*i+3;
		  ctrl_in = 0;
		end


	end
      
endmodule
module per_p4_test;

    parameter CLOCK_TIME = 5.0;
    parameter DATA_WIDTH = 16;
    parameter SIZE = 256;
    parameter DP = 4;

	reg clk;
	reg rst;
	reg [DATA_WIDTH-1:0] data_in [DP-1:0];
	reg ctrl_in;


	wire [DATA_WIDTH-1:0] data_out [DP-1:0];
	wire ctrl_out;


	per_dp4_0_r per_instance(




    .inData_0(data_in[0]),
    .inData_1(data_in[1]),
	.inData_2(data_in[2]),
    .inData_3(data_in[3]),
    .outData_0(data_out[0]),
    .outData_1(data_out[1]),
	.outData_2(data_out[2]),
    .outData_3(data_out[3]),
    .in_start(ctrl_in),                        
    .out_start(ctrl_out),                       
    .clk(clk),                             
    .rst(rst)                              
    );  
    
	integer i;
	always #(CLOCK_TIME/2) clk=~clk;
	
	initial begin

		clk = 0;
		rst = 1;
		data_in[0] = {DATA_WIDTH{1'b0}};
		data_in[1] = {DATA_WIDTH{1'b0}};
		data_in[2] = {DATA_WIDTH{1'b0}};
		data_in[3] = {DATA_WIDTH{1'b0}};
		ctrl_in = 0;


		#100;
		#3.0;
		rst = 0;
		data_in[0] = 0;
		data_in[1] = 0;
		data_in[2] = {DATA_WIDTH{1'b0}};
		data_in[3] = {DATA_WIDTH{1'b0}};
		ctrl_in = 1;
		
		for(i=0; i<SIZE/DP; i=i+1)begin
		  #CLOCK_TIME;
		  data_in[0] = 4*i;
		  data_in[1] = 4*i+1;
		  data_in[2] = 4*i+2;
		  data_in[3] = 4*i+3;
		  ctrl_in = 0;
		end
		  
		ctrl_in = 1;		  
        
		for(i=0; i<SIZE/DP; i=i+1)begin
		  #CLOCK_TIME;
		  data_in[0] = 4*i;
		  data_in[1] = 4*i+1;
		  data_in[2] = 4*i+2;
		  data_in[3] = 4*i+3;
		  ctrl_in = 0;
		end


	end
      
endmodule