data/full_repos/permissive/104305228/code/mem_wb.v
1: b'%Error: data/full_repos/permissive/104305228/code/mem_wb.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:15: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:15: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n  if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin\n                        ^~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:15: Define or directive not defined: \'`StallEnable\'\n  if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin\n                                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:15: Define or directive not defined: \'`StallDisable\'\n  if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin\n                                                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:16: Define or directive not defined: \'`WriteDisable\'\n   wb_we <= `WriteDisable;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:20: syntax error, unexpected else\n  else if (stall[4] == `StallDisable) begin\n  ^~~~\n%Error: data/full_repos/permissive/104305228/code/mem_wb.v:20: Define or directive not defined: \'`StallDisable\'\n  else if (stall[4] == `StallDisable) begin\n                       ^~~~~~~~~~~~~\n%Error: Cannot continue\n'
module mem_wb(
	input clk,
	input rst,
	input [5:0] stall,
	input mem_we,
	input [4:0] mem_write_addr,
	input [31:0] mem_write_instr,
	
	output reg wb_we,
	output reg[4:0] wb_write_addr,
	output reg[31:0] wb_write_instr
);
	always @ (posedge clk) begin
		if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin
			wb_we <= `WriteDisable;
			wb_write_addr <= 5'b0;
			wb_write_instr <= 32'b0;
		end
		else if (stall[4] == `StallDisable) begin
			wb_we <= mem_we;
			wb_write_addr <= mem_write_addr;
			wb_write_instr <= mem_write_instr;
		end
	end
endmodule
module mem_wb(
	input clk,
	input rst,
	input [5:0] stall,
	input mem_we,
	input [4:0] mem_write_addr,
	input [31:0] mem_write_instr,
	
	output reg wb_we,
	output reg[4:0] wb_write_addr,
	output reg[31:0] wb_write_instr
);

	always @ (posedge clk) begin
		if (rst == `RstEnable || (stall[4] == `StallEnable && stall[5] == `StallDisable)) begin
			wb_we <= `WriteDisable;
			wb_write_addr <= 5'b0;
			wb_write_instr <= 32'b0;
		end
		else if (stall[4] == `StallDisable) begin
			wb_we <= mem_we;
			wb_write_addr <= mem_write_addr;
			wb_write_instr <= mem_write_instr;
		end
	end
endmodule