data/full_repos/permissive/143278/vhdl_tests/pr2554124.v
data/verilator_xmls/82e86d3d-4e9e-4de8-8469-9a35439f9f41.xml
module test();
  wire b;
  a a( .b_buf(b),
       .b (b));
endmodule
module test();

  wire b;
  a a( .b_buf(b),
       .b (b));
endmodule