data/full_repos/permissive/20951436/Code/fpga code/advanced code/Advanced code.v
1: b'%Error: Cannot find file containing module: code/advanced\n        ... Looked in:\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.v\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.sv\n             code/advanced\n             code/advanced.v\n             code/advanced.sv\n             obj_dir/code/advanced\n             obj_dir/code/advanced.v\n             obj_dir/code/advanced.sv\n%Error: Cannot find file containing module: code,data/full_repos/permissive/20951436\n%Error: Cannot find file containing module: data/full_repos/permissive/20951436/Code/fpga\n%Error: Cannot find file containing module: code/Advanced\n%Error: Cannot find file containing module: code.v\n%Error: Exiting due to 5 error(s)\n'
module controller(input clk, input en, input [31:0] des_rot_inp, input dir, input pulses, output reg [4:0] speed, output comp_sig);
	
	initial speed<=0;
	wire [31:0] des_rot_mag; assign des_rot_mag = des_rot_inp;
	wire [31:0] des_rot; assign des_rot = (dir ? ~des_rot_mag + 1 : des_rot_mag);

	reg [31:0] count_pulse; initial count_pulse<=0;
	reg pulses_hist; reg en_hist;

	

	reg clk_debounced; initial clk_debounced<=0;
	reg [15:0] clk_counter; initial clk_counter<=0;
	always @(negedge clk_debounced) begin
		clk_counter<=clk_counter+1;
		if (clk_counter==0) clk_debounced<=~clk_debounced;
	end
	

	wire [31:0] error; assign error=des_rot-count_pulse;
	wire error_sign;
	assign error_sign = error[31];
	always @(negedge clk_debounced) begin
		en_hist<=en; pulses_hist<=pulses;
		if (en && (~en_hist)) count_pulse<=0;
		else if (pulses_hist && (~pulses)) count_pulse<=count_pulse+{{31{error_sign}},1'b1};
	end

	assign comp_sig = ( (error[31:1]==31'h0) | (error[31:1]==31'h7FFFFFFF) );

	wire [31:0] Kp; wire [31:0] Kd; wire [31:0] Ki; wire mult_comp;
	assign Kp=32'h1F222222; assign Kd=32'h0;
	
	reg mult_comp_reg; initial mult_comp_reg<=0; always @(negedge clk) mult_comp_reg<=mult_comp;

	reg [31:0] reg_error;
	always @(posedge mult_comp_reg) begin
		reg_error<=error;
	end
	wire [31:0] der_error; assign der_error=error-reg_error;




	wire [63:0] speed_exact_Kp, speed_exact_Kd, speed_exact;

	reg en_mult; initial en_mult<=0;
	wire mult_comp_Kp;

	assign mult_comp = mult_comp_Kp;
	always @(negedge clk) en_mult <= (en_mult ? ~mult_comp : 1);

	multiplier mult_Kp(clk,1,Kp,error,en_mult,speed_exact_Kp,mult_comp_Kp);

	


	

	wire [63:0] speed_sum; assign speed_sum = speed_exact_Kp;
	wire speed_overshoot; assign speed_overshoot = ((speed_sum[63:33]!=31'h0) & (speed_sum[63:33]!=31'h7FFFFFFF));
	always @(posedge mult_comp_Kp) speed[4:0]<=( en ?
		( speed_overshoot ? {speed_sum[63],{3{~speed_sum[63]}},1'b1} : {speed_sum[63],speed_sum[32:29]} )
		: 5'b0 );


endmodule
module controller(input clk, input en, input [31:0] des_rot_inp, input dir, input pulses, output reg [4:0] speed, output comp_sig);

	
	initial speed<=0;
	wire [31:0] des_rot_mag; assign des_rot_mag = des_rot_inp;
	wire [31:0] des_rot; assign des_rot = (dir ? ~des_rot_mag + 1 : des_rot_mag);

	reg [31:0] count_pulse; initial count_pulse<=0;
	reg pulses_hist; reg en_hist;

	

	reg clk_debounced; initial clk_debounced<=0;
	reg [15:0] clk_counter; initial clk_counter<=0;
	always @(negedge clk_debounced) begin
		clk_counter<=clk_counter+1;
		if (clk_counter==0) clk_debounced<=~clk_debounced;
	end
	

	wire [31:0] error; assign error=des_rot-count_pulse;
	wire error_sign;
	assign error_sign = error[31];
	always @(negedge clk_debounced) begin
		en_hist<=en; pulses_hist<=pulses;
		if (en && (~en_hist)) count_pulse<=0;
		else if (pulses_hist && (~pulses)) count_pulse<=count_pulse+{{31{error_sign}},1'b1};
	end

	assign comp_sig = ( (error[31:1]==31'h0) | (error[31:1]==31'h7FFFFFFF) );

	wire [31:0] Kp; wire [31:0] Kd; wire [31:0] Ki; wire mult_comp;
	assign Kp=32'h1F222222; assign Kd=32'h0;
	
	reg mult_comp_reg; initial mult_comp_reg<=0; always @(negedge clk) mult_comp_reg<=mult_comp;

	reg [31:0] reg_error;
	always @(posedge mult_comp_reg) begin
		reg_error<=error;
	end
	wire [31:0] der_error; assign der_error=error-reg_error;




	wire [63:0] speed_exact_Kp, speed_exact_Kd, speed_exact;

	reg en_mult; initial en_mult<=0;
	wire mult_comp_Kp;

	assign mult_comp = mult_comp_Kp;
	always @(negedge clk) en_mult <= (en_mult ? ~mult_comp : 1);

	multiplier mult_Kp(clk,1,Kp,error,en_mult,speed_exact_Kp,mult_comp_Kp);

	


	

	wire [63:0] speed_sum; assign speed_sum = speed_exact_Kp;
	wire speed_overshoot; assign speed_overshoot = ((speed_sum[63:33]!=31'h0) & (speed_sum[63:33]!=31'h7FFFFFFF));
	always @(posedge mult_comp_Kp) speed[4:0]<=( en ?
		( speed_overshoot ? {speed_sum[63],{3{~speed_sum[63]}},1'b1} : {speed_sum[63],speed_sum[32:29]} )
		: 5'b0 );


endmodule