data/full_repos/permissive/178052224/Tarea8/checker_gray.v
1: b'%Warning-WIDTH: data/full_repos/permissive/178052224/Tarea8/checker_gray.v:25: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'salida_gray_c\' generates 5 bits.\n                                                                             : ... In instance checker_gray\n            out_c = salida_gray_c;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/178052224/Tarea8/checker_gray.v:26: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'salida_gray_e\' generates 5 bits.\n                                                                             : ... In instance checker_gray\n            out_e = salida_gray_e;\n                  ^\n%Error: Exiting due to 2 warning(s)\n'
module checker_gray(
    output reg      gray_checks_out,
    input           clk,
    input          reset_L,
    input   [4:0]  salida_gray_c,
    input   [4:0]   salida_gray_e
);
    reg     out_c, out_e;
    reg     onflag, resetflag;
    always@( * ) begin
        if( !reset_L ) begin
            out_c  =   'b0;
            out_e  =   'b0;
            onflag =   'b0;
            gray_checks_out <= 1;
        end else begin      
            out_c = salida_gray_c;
            out_e = salida_gray_e;
           
            if( reset_L == 1 ) begin
                if( out_c == out_e ) begin
                    gray_checks_out = 1;
                    resetflag =1; 
                end else begin
                    gray_checks_out = 'b0;
                    if ( ( !onflag )  && ( resetflag == 1 ) ) begin
                        $display( $time, " ns, Error: Modules differ!!" );
                        onflag = 1;
                    end
                end
            end 
        end
    end
endmodule
module checker_gray(
    output reg      gray_checks_out,
    input           clk,
    input          reset_L,
    input   [4:0]  salida_gray_c,
    input   [4:0]   salida_gray_e
);

    reg     out_c, out_e;
    reg     onflag, resetflag;
    always@( * ) begin
        if( !reset_L ) begin
            out_c  =   'b0;
            out_e  =   'b0;
            onflag =   'b0;
            gray_checks_out <= 1;
        end else begin      
            out_c = salida_gray_c;
            out_e = salida_gray_e;
           
            if( reset_L == 1 ) begin
                if( out_c == out_e ) begin
                    gray_checks_out = 1;
                    resetflag =1; 
                end else begin
                    gray_checks_out = 'b0;
                    if ( ( !onflag )  && ( resetflag == 1 ) ) begin
                        $display( $time, " ns, Error: Modules differ!!" );
                        onflag = 1;
                    end
                end
            end 
        end
    end
endmodule