data/full_repos/permissive/151116236/ParaMuxTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/151116236/ParaMuxTest.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/151116236/ParaMuxTest.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/151116236/ParaMuxTest.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/151116236/ParaMuxTest.v:33: Cannot find file containing module: \'mux\'\n mux #(D_SIZE,D_COUNT,1) uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/151116236,data/full_repos/permissive/151116236/mux\n             data/full_repos/permissive/151116236,data/full_repos/permissive/151116236/mux.v\n             data/full_repos/permissive/151116236,data/full_repos/permissive/151116236/mux.sv\n             mux\n             mux.v\n             mux.sv\n             obj_dir/mux\n             obj_dir/mux.v\n             obj_dir/mux.sv\n%Warning-WIDTH: data/full_repos/permissive/151116236/ParaMuxTest.v:49: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh2\' generates 32 or 2 bits.\n                                                                     : ... In instance ParaMuxTest\n  addr = 2;\n       ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ParaMuxTest;
	parameter D_SIZE=2,D_COUNT=3;

	wire [D_SIZE-1:0] outdata;
	reg [D_SIZE*D_COUNT-1:0] indata ;
	reg addr;


	mux #(D_SIZE,D_COUNT,1) uut (
		.outdata(outdata),
		.indata(indata),
		.addr(addr)
	);

	initial begin

		#100;
        

		indata = 6;
		addr = 0;
		#100;
		addr = 1;
		#100;
		addr = 2;

	end
      
endmodule
module ParaMuxTest;

	parameter D_SIZE=2,D_COUNT=3;

	wire [D_SIZE-1:0] outdata;
	reg [D_SIZE*D_COUNT-1:0] indata ;
	reg addr;


	mux #(D_SIZE,D_COUNT,1) uut (
		.outdata(outdata),
		.indata(indata),
		.addr(addr)
	);

	initial begin

		#100;
        

		indata = 6;
		addr = 0;
		#100;
		addr = 1;
		#100;
		addr = 2;

	end
      
endmodule