data/full_repos/permissive/112978342/max10_adc_firmware/ring_counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/ring_counter.v:41: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'delay_counter\' generates 32 bits.\n                                                                                         : ... In instance ring_counter\n  else out_delay[7:0] = delay_counter; \n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware/ring_counter.v:75: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                         : ... In instance ring_counter\n  if (delayin[delay_counter2]) out_carry[7:0] = delay_counter2 - 150; \n                                              ^\n%Error: Exiting due to 2 warning(s)\n'
module ring_counter (clk,out_carry,carryin,carryout,delayin,start,out_delay);
input clk;
output reg [7:0] out_carry;
output reg [7:0] out_delay;
input carryin;
output carryout;
input wire [DELAY-1:0] delayin;

parameter DELAY=100;
wire [DELAY-1:0] delay_line;
output reg start;
reg freeze;
assign carryout = freeze;

wire freezeline;

assign freezeline = carryin;


genvar i;
generate
for (i=1; i<DELAY; i=i+1)
	begin : del

		assign delay_line [i] = (freezeline) ? delay_line[i] : delay_line[i-1];
	end
endgenerate
assign delay_line[0] = start;

initial begin
	start<=0;
	freeze<=0;
end


integer delay_counter=0;
always @(posedge clk) begin
	if (freeze) begin

		if (delay_line[delay_counter]) delay_counter=delay_counter+1;
		else out_delay[7:0] = delay_counter;
	end
	else delay_counter=0;
end

integer counter=0;
integer delayer=0;

always @(posedge clk) begin
	counter = counter+1;
	if (counter==200000000) begin
		freeze=0;
		start=0;
	end
	if (counter==200000050) begin
		start=1;
	end
	if (counter==200000050+delayer) begin
		freeze=1;
		





		
	end
	if (counter==200000050+delayer+ 100000) counter=0;
end

integer delay_counter2=1;
always @(posedge clk) begin
	if (counter > 200000050+delayer + 10) begin

		if (delayin[delay_counter2]) out_carry[7:0] = delay_counter2 - 150;
		else delay_counter2=delay_counter2+1;
	end
	else delay_counter2=1;
end

endmodule
module ring_counter (clk,out_carry,carryin,carryout,delayin,start,out_delay);

input clk;
output reg [7:0] out_carry;
output reg [7:0] out_delay;
input carryin;
output carryout;
input wire [DELAY-1:0] delayin;

parameter DELAY=100;
wire [DELAY-1:0] delay_line;
output reg start;
reg freeze;
assign carryout = freeze;

wire freezeline;

assign freezeline = carryin;


genvar i;
generate
for (i=1; i<DELAY; i=i+1)
	begin : del

		assign delay_line [i] = (freezeline) ? delay_line[i] : delay_line[i-1];
	end
endgenerate
assign delay_line[0] = start;

initial begin
	start<=0;
	freeze<=0;
end


integer delay_counter=0;
always @(posedge clk) begin
	if (freeze) begin

		if (delay_line[delay_counter]) delay_counter=delay_counter+1;
		else out_delay[7:0] = delay_counter;
	end
	else delay_counter=0;
end

integer counter=0;
integer delayer=0;

always @(posedge clk) begin
	counter = counter+1;
	if (counter==200000000) begin
		freeze=0;
		start=0;
	end
	if (counter==200000050) begin
		start=1;
	end
	if (counter==200000050+delayer) begin
		freeze=1;
		





		
	end
	if (counter==200000050+delayer+ 100000) counter=0;
end

integer delay_counter2=1;
always @(posedge clk) begin
	if (counter > 200000050+delayer + 10) begin

		if (delayin[delay_counter2]) out_carry[7:0] = delay_counter2 - 150;
		else delay_counter2=delay_counter2+1;
	end
	else delay_counter2=1;
end

endmodule