data/full_repos/permissive/143278/vhdl_tests/pr2555831.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/pr2555831.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ( din, dout);
  input [31:0] din;
  output [31:0] dout;
  buff #(1) d0_1 ( .in(din[0:0]), .out(dout[0:0]));
  buff #(32) d0_32 ( .in(din[31:0]), .out(dout[31:0]));
endmodule
module test ( din, dout);

  input [31:0] din;
  output [31:0] dout;
  buff #(1) d0_1 ( .in(din[0:0]), .out(dout[0:0]));
  buff #(32) d0_32 ( .in(din[31:0]), .out(dout[31:0]));
endmodule