data/full_repos/permissive/124999927/hw_video/vga_640_480.v
data/verilator_xmls/047e4a88-d80a-45c2-a782-c3c04600685e.xml
module vga_640_480(
  clk25,
  reset,

  o_vsync,
  o_hsync
);

  input clk25;
  input reset;

  output reg o_vsync;
  output reg o_hsync;

  reg [10:0] counter_x;
  reg [10:0] counter_y;

  always@(posedge clk25) begin
  end

endmodule
module vga_640_480(
  clk25,
  reset,

  o_vsync,
  o_hsync
);


  input clk25;
  input reset;

  output reg o_vsync;
  output reg o_hsync;

  reg [10:0] counter_x;
  reg [10:0] counter_y;

  always@(posedge clk25) begin
  end

endmodule