data/full_repos/permissive/212763527/school_project/14_memory/sources/FIFO.v
 line:44: before: "="
1: b"%Error: data/full_repos/permissive/212763527/school_project/14_memory/sources/FIFO.v:44: syntax error, unexpected '='\n                if (front = (rear + 2) % maxSize)\n                          ^\n%Error: Exiting due to 1 error(s)\n"
module FIFO #(parameter WIDTH = 8,
              parameter size = 8)
             (input [WIDTH-1:0] data_in,
              input wr_en,
              input rd_en,
              input clk,
              input rst,
              output reg [WIDTH-1:0] data_out,
              output reg empty,
              output reg full
              );

parameter maxSize = size + 1;
reg [WIDTH-1:0] mem [0:maxSize];


integer front;
integer rear;

always @(posedge clk) begin
    
    if (rst) begin

        front <= 1;
        rear <= 0;
        full <= 1'b0;
        empty <= 1'b1;
        data_out <= {(WIDTH-1){1'bx}};
    end else begin


        if (wr_en & rd_en) begin
            if (front == (rear + 1) % maxSize) begin

                empty <= 1'b1;
                data_out <= data_in;
                full <= 1'b0;
            
            end else begin

                empty <= 1'b0;
                if (front = (rear + 2) % maxSize)

                    full <= 1'b1;
                else
                    full <= 1'b0;


                data_out <= mem[front];
                front <= (front + 1) % maxSize;

                mem[(rear + 1) % maxSize] <= data_in;
                rear <= (rear + 1) % maxSize;
            end

        end else if (wr_en) begin



            empty <= 1'b0;

            if (front == (rear + 2) % maxSize) begin


                full <= 1'b1;

            end else begin


                mem[(rear + 1) % maxSize] <= data_in;
                rear <= (rear + 1) % maxSize;
                full <= 1'b0;

            end
        end else if (rd_en) begin



            full <= 1'b0;

            if (front == (rear + 1) % maxSize) begin 


                data_out <= {(WIDTH-1){1'bx}};
                empty <= 1'b1;
                
            end else begin


                data_out <= mem[front];
                front <= (front + 1) % maxSize;
                empty <= 1'b0;
            end

        end
    end
    
end
    
endmodule
module FIFO #(parameter WIDTH = 8,
              parameter size = 8)
             (input [WIDTH-1:0] data_in,
              input wr_en,
              input rd_en,
              input clk,
              input rst,
              output reg [WIDTH-1:0] data_out,
              output reg empty,
              output reg full
              );


parameter maxSize = size + 1;
reg [WIDTH-1:0] mem [0:maxSize];


integer front;
integer rear;

always @(posedge clk) begin
    
    if (rst) begin

        front <= 1;
        rear <= 0;
        full <= 1'b0;
        empty <= 1'b1;
        data_out <= {(WIDTH-1){1'bx}};
    end else begin


        if (wr_en & rd_en) begin
            if (front == (rear + 1) % maxSize) begin

                empty <= 1'b1;
                data_out <= data_in;
                full <= 1'b0;
            
            end else begin

                empty <= 1'b0;
                if (front = (rear + 2) % maxSize)

                    full <= 1'b1;
                else
                    full <= 1'b0;


                data_out <= mem[front];
                front <= (front + 1) % maxSize;

                mem[(rear + 1) % maxSize] <= data_in;
                rear <= (rear + 1) % maxSize;
            end

        end else if (wr_en) begin



            empty <= 1'b0;

            if (front == (rear + 2) % maxSize) begin


                full <= 1'b1;

            end else begin


                mem[(rear + 1) % maxSize] <= data_in;
                rear <= (rear + 1) % maxSize;
                full <= 1'b0;

            end
        end else if (rd_en) begin



            full <= 1'b0;

            if (front == (rear + 1) % maxSize) begin 


                data_out <= {(WIDTH-1){1'bx}};
                empty <= 1'b1;
                
            end else begin


                data_out <= mem[front];
                front <= (front + 1) % maxSize;
                empty <= 1'b0;
            end

        end
    end
    
end
    
endmodule