data/full_repos/permissive/143278/ivltests/pr1625912.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1625912.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (result != cnt) begin\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
   integer cnt;
   real    result, win;

   initial begin
      cnt = -10;
      for (result=-10; result<=10; result=result+2) begin
	 #1 if (result != cnt) begin
	    $display("FAILED -- cnt=%0d, result=%f", cnt, result);
	 end
	 cnt = cnt + 2;
      end
      $display("PASSED");
      $finish;
   end

endmodule
module top;

   integer cnt;
   real    result, win;

   initial begin
      cnt = -10;
      for (result=-10; result<=10; result=result+2) begin
	 #1 if (result != cnt) begin
	    $display("FAILED -- cnt=%0d, result=%f", cnt, result);
	 end
	 cnt = cnt + 2;
      end
      $display("PASSED");
      $finish;
   end

endmodule