data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v:28: Unsupported: Ignoring delay on this delayed statement.\nalways #2 clock = ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/to_dac_TF.v:20: Cannot find file containing module: \'to_dac_test\'\n   to_dac_test UUT (\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/to_dac_test\n             data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/to_dac_test.v\n             data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/to_dac_test.sv\n             to_dac_test\n             to_dac_test.v\n             to_dac_test.sv\n             obj_dir/to_dac_test\n             obj_dir/to_dac_test.v\n             obj_dir/to_dac_test.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module to_dac_test_to_dac_test_sch_tb();


   reg clock;
   reg reset;


   wire MOSI;
   wire sClk;
   wire SPI_CS;
   wire resetDac;




   to_dac_test UUT (
		.MOSI(MOSI), 
		.sClk(sClk), 
		.clock(clock), 
		.SPI_CS(SPI_CS), 
		.reset(reset), 
		.resetDac(resetDac)
   );
always #2 clock = ~clock;
	initial begin

		clock = 0;
		reset = 0;
		#10;
		reset = 1;
		#10;
		reset = 0;

		#100;
        


	end
      
endmodule
module to_dac_test_to_dac_test_sch_tb();



   reg clock;
   reg reset;


   wire MOSI;
   wire sClk;
   wire SPI_CS;
   wire resetDac;




   to_dac_test UUT (
		.MOSI(MOSI), 
		.sClk(sClk), 
		.clock(clock), 
		.SPI_CS(SPI_CS), 
		.reset(reset), 
		.resetDac(resetDac)
   );
always #2 clock = ~clock;
	initial begin

		clock = 0;
		reset = 0;
		#10;
		reset = 1;
		#10;
		reset = 0;

		#100;
        


	end
      
endmodule