data/full_repos/permissive/175132042/rtl/picorv32/scripts/icestorm/example_tb.v
 line:27: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/175132042/rtl/picorv32/scripts/icestorm/example_tb.v:5: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/icestorm/example_tb.v:22: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("example.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/icestorm/example_tb.v:23: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0, testbench);\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/icestorm/example_tb.v:26: Unsupported or unknown PLI call: $monitor\n  $monitor(LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/icestorm/example_tb.v:27: syntax error, unexpected \'@\'\n  repeat (10000) @(posedge clk);\n                 ^\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
	reg clk = 1;
	always #5 clk = ~clk;
	wire LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7;

	top uut (
		.clk(clk),
		.LED0(LED0),
		.LED1(LED1),
		.LED2(LED2),
		.LED3(LED3),
		.LED4(LED4),
		.LED5(LED5),
		.LED6(LED6),
		.LED7(LED7)
	);

	initial begin
		if ($test$plusargs("vcd")) begin
			$dumpfile("example.vcd");
			$dumpvars(0, testbench);
		end

		$monitor(LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0);
		repeat (10000) @(posedge clk);
		$finish;
	end
endmodule
module testbench;

	reg clk = 1;
	always #5 clk = ~clk;
	wire LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7;

	top uut (
		.clk(clk),
		.LED0(LED0),
		.LED1(LED1),
		.LED2(LED2),
		.LED3(LED3),
		.LED4(LED4),
		.LED5(LED5),
		.LED6(LED6),
		.LED7(LED7)
	);

	initial begin
		if ($test$plusargs("vcd")) begin
			$dumpfile("example.vcd");
			$dumpvars(0, testbench);
		end

		$monitor(LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0);
		repeat (10000) @(posedge clk);
		$finish;
	end
endmodule