data/full_repos/permissive/143278/ivltests/unary_minus4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/unary_minus4.v:10: Unsupported: Ignoring delay on this delayed statement.\n     #1 if (result !== 32\'h0000_0064) begin\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/unary_minus4.v:16: Unsupported: Ignoring delay on this delayed statement.\n     #1 if (result !== 32\'h0000_ff9c) begin\n     ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug();

  reg [15 : 0] in;
  reg sel;
  wire [31 : 0] result = { 16'd0, sel ? -in : in };

  initial begin
     in = 100;
     sel = 0;
     #1 if (result !== 32'h0000_0064) begin
	$display("FAILED -- result=%h, sel=%b, in=%h", result, sel, in);
	$finish;
     end

     sel = 1;
     #1 if (result !== 32'h0000_ff9c) begin
	$display("FAILED == result=%h, sel=%b, in=%h, -in=%h",
		 result, sel, in, -in);
	$finish;
     end

     $display("PASSED");
  end

endmodule
module bug();


  reg [15 : 0] in;
  reg sel;
  wire [31 : 0] result = { 16'd0, sel ? -in : in };

  initial begin
     in = 100;
     sel = 0;
     #1 if (result !== 32'h0000_0064) begin
	$display("FAILED -- result=%h, sel=%b, in=%h", result, sel, in);
	$finish;
     end

     sel = 1;
     #1 if (result !== 32'h0000_ff9c) begin
	$display("FAILED == result=%h, sel=%b, in=%h, -in=%h",
		 result, sel, in, -in);
	$finish;
     end

     $display("PASSED");
  end

endmodule