data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v
 line:1 column:1: Illegal character '\x00'
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:60: Cannot find include file: tap_defines.v\n`include "tap_defines.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system,data/full_repos/permissive/17099167/tap_defines.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system,data/full_repos/permissive/17099167/tap_defines.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system,data/full_repos/permissive/17099167/tap_defines.v.sv\n             tap_defines.v\n             tap_defines.v.v\n             tap_defines.v.sv\n             obj_dir/tap_defines.v\n             obj_dir/tap_defines.v.v\n             obj_dir/tap_defines.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:61: Cannot find include file: adbg_defines.v\n`include "adbg_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:62: Cannot find include file: adbg_wb_defines.v\n`include "adbg_wb_defines.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 wb_clk_o = ~wb_clk_o; \n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n   #200 sys_rstn_o = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n   #5000 sys_rstn_o = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #5 test_enabled<= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #6000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:177: Define or directive not defined: \'`DEBUG\'\n  set_ir(`DEBUG);\n         ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:530: Unsupported: Ignoring delay on this delayed statement.\n        #1000;    \n        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:582: Define or directive not defined: \'`IDCODE\'\n    set_ir(`IDCODE);\n           ^~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:592: Define or directive not defined: \'`IDCODE_VALUE\'\n    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);\n                                                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:592: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);\n                                                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:648: Define or directive not defined: \'`DBG_WB_CMD_IREG_SEL\'\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);\n                               ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:648: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);\n                                                    ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:691: Define or directive not defined: \'`DBG_WB_CMD_IREG_WR\'\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));\n                               ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:691: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\n    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));\n                                                   ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:724: Define or directive not defined: \'`DBG_WB_CMD_BREAD8\'\n       3\'h1: opcode = `DBG_WB_CMD_BREAD8;\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:724: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h1: opcode = `DBG_WB_CMD_BREAD8;\n                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:725: Define or directive not defined: \'`DBG_WB_CMD_BREAD16\'\n       3\'h2: opcode = `DBG_WB_CMD_BREAD16;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:725: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h2: opcode = `DBG_WB_CMD_BREAD16;\n                                         ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:726: Define or directive not defined: \'`DBG_WB_CMD_BREAD32\'\n       3\'h4: opcode = `DBG_WB_CMD_BREAD32;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:726: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h4: opcode = `DBG_WB_CMD_BREAD32;\n                                         ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:730: Define or directive not defined: \'`DBG_WB_CMD_BREAD32\'\n           opcode = `DBG_WB_CMD_BREAD32;\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:730: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n           opcode = `DBG_WB_CMD_BREAD32;\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:739: Unsupported: Ignoring delay on this delayed statement.\n   #500;\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:740: Define or directive not defined: \'`IDCODE\'\n   set_ir(`IDCODE);\n          ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:741: Unsupported: Ignoring delay on this delayed statement.\n   #500;\n   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:742: Define or directive not defined: \'`DEBUG\'\n   set_ir(`DEBUG);\n          ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:743: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:824: Define or directive not defined: \'`DBG_WB_CMD_BWRITE8\'\n       3\'h1: opcode = `DBG_WB_CMD_BWRITE8;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:824: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h1: opcode = `DBG_WB_CMD_BWRITE8;\n                                         ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:825: Define or directive not defined: \'`DBG_WB_CMD_BWRITE16\'\n       3\'h2: opcode = `DBG_WB_CMD_BWRITE16;\n                      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:825: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h2: opcode = `DBG_WB_CMD_BWRITE16;\n                                          ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:826: Define or directive not defined: \'`DBG_WB_CMD_BWRITE32\'\n       3\'h4: opcode = `DBG_WB_CMD_BWRITE32;\n                      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:826: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       3\'h4: opcode = `DBG_WB_CMD_BWRITE32;\n                                          ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:830: Define or directive not defined: \'`DBG_WB_CMD_BWRITE32\'\n           opcode = `DBG_WB_CMD_BWRITE32;\n                    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:830: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n           opcode = `DBG_WB_CMD_BWRITE32;\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:977: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:981: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:985: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:999: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:1003: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/adv_dbg_tb.v:1007: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Error: Exiting due to 29 error(s), 17 warning(s)\n'
module adv_debug_tb (

jtag_tck_o,
jtag_tms_o,
jtag_tdo_o,
jtag_tdi_i,

wb_clk_o,
sys_rstn_o


); 

output jtag_tck_o;
output jtag_tms_o;
output jtag_tdo_o;
input jtag_tdi_i;
output wb_clk_o;
output sys_rstn_o;


reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;

reg wb_clk_o;
reg sys_rst_o;
reg sys_rstn_o;
   
reg test_enabled;


reg [31:0] static_data32 [0:15]; 
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];


reg [31:0] input_data32 [0:15]; 
reg [15:0] input_data16 [0:15];
reg [7:0]  input_data8 [0:15];                                

reg [32:0] err_data;

reg [31:0] original_instruction;

reg failed;
integer i;

initial
begin
   jtag_tck_o = 1'b0;
   jtag_tms_o = 1'b0;
   jtag_tdo_o = 1'b0;
end


initial
begin
  wb_clk_o = 1'b0;
  forever #5 wb_clk_o = ~wb_clk_o; 
end

initial
begin
   sys_rstn_o = 1'b1;
   #200 sys_rstn_o = 1'b0;
   #5000 sys_rstn_o = 1'b1;
end



initial
begin
  test_enabled = 1'b0;


  initialize_memory(32'h0,32'h16);

  #5 test_enabled<= 1'b1;
end


always @ (posedge test_enabled)
begin

  $display("Starting advanced debug test");
  
  reset_jtag;
  #6000;
  check_idcode;
  #1000;
  

  set_ir(`DEBUG);
  #1000;
  
  
  `ifdef DBG_CPU0_SUPPORTED


  #1000; 
  $display("Selecting CPU0 module at time %t", $time);
  select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);

    

   $display("Setting reset and stall bits at time %t", $time);    
    write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2);
   #1000;
   `endif
  
  



  
`ifdef DBG_WISHBONE_SUPPORTED

  #1000; 
  $display("Selecting Wishbone module at time %t", $time);
  select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
    

    write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1);
   #1000;
   


  failed = 0;
  $display("Testing WB 8-bit burst write at time %t: resetting ", $time);
  do_module_burst_write(3'h1, 16'd16, 32'h87);
  #1000;
  $display("Testing WB 8-bit burst read at time %t", $time);
  do_module_burst_read(3'h1, 16'd16, 32'h87);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data8[i] != input_data8[i]) begin 
        failed = 1;
        $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]);
    end
  end
  if(!failed) $display("8-bit read/write OK!");
  
  


  failed = 0;
  $display("Testing WB 16-bit burst write at time %t", $time);
  do_module_burst_write(3'h2, 16'd16, 32'h22);
  #1000;
  $display("Testing WB 16-bit burst read at time %t", $time);
  do_module_burst_read(3'h2, 16'd16, 32'h22);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data16[i] != input_data16[i]) begin 
        failed = 1;
        $display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]);
    end
  end
  if(!failed) $display("16-bit read/write OK!");
 
  


  failed = 0;
  $display("Testing WB 32-bit burst write at time %t", $time);
  do_module_burst_write(3'h4, 16'd16, 32'h100);
  #1000;
  $display("Testing WB 32-bit burst read at time %t", $time);
  do_module_burst_read(3'h4, 16'd16, 32'h100);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data32[i] != input_data32[i]) begin 
        failed = 1;
        $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]);
    end
  end
  if(!failed) $display("32-bit read/write OK!");
    
  


  err_data = 33'h0;

  write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1);

  do_module_burst_write(3'h4, 16'd4, 32'hdeaddead);
  read_module_internal_register(8'd33, err_data);
  $display("Error bit is %d, error address is %x", err_data[0], err_data>>1);

`endif
  
  





`ifdef DBG_CPU0_SUPPORTED

  #1000; 
  $display("Selecting CPU0 module at time %t", $time);
  select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);

    

   $display("Setting reset and stall bits at time %t", $time);    
    write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2);
   #1000;
   

   $display("Testing reset and stall bits at time %t", $time);
   read_module_internal_register(8'd2, err_data);
   $display("Reset and stall bits are %x", err_data);
   #1000;
   


   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   $display("Commencing CPU functional test - writing instructions at time %t", $time);
   static_data32[0] = 32'hE0000005;
   static_data32[1] = 32'h9C200000;
   static_data32[2] = 32'h18400000;
   static_data32[3] = 32'hA8420030;
   static_data32[4] = 32'h9C210001;
   static_data32[5] = 32'h9C210001;
   static_data32[6] = 32'hD4020800;
   static_data32[7] = 32'h9C210001;
   static_data32[8] = 32'h84620000;
   static_data32[9] = 32'h03FFFFFB;
   static_data32[10] = 32'hE0211800;
   do_module_burst_write(3'h4, 16'd11, 32'h0);

   #1000;
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);


   #1000;
   $display("Testing step bit at time %t", $time);
   static_data32[0] = 32'h1;
   do_module_burst_write(3'h4, 16'd1, 32'd17);
   static_data32[0] = 32'h00002000;
   do_module_burst_write(3'h4, 16'd1, (6 << 11)+20);
   static_data32[0] = 32'h0;
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   static_data32[0] = (1 << 22);
   do_module_burst_write(3'h4, 16'd1, (6<<11) + 16);


   for(i = 0; i < 11; i = i + 1)
     begin
	#1000;
	$display("Unstall (%d/11) at time %t", i+1, $time);
	unstall();
	wait_for_stall();
     end

   #1000;
   check_results(32'h10, 32'h28, 32'h5);
  
   static_data32[0] = 32'h0;
   do_module_burst_write(3'h4, 16'd1, (6 << 11)+16);
  

   #1000;  
   $display("Put TRAP instruction in the delay slot at time %t", $time);  
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_read(3'h4, 16'd1, 32'h28);
  original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h28);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);


   unstall();
   wait_for_stall();
   check_results(32'h10, 32'h28, 32'd8);
   

   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h28);


   #1000;
   $display("Put TRAP instruction in place of BRANCH instruction at time %t", $time);  
   do_module_burst_read(3'h4, 16'd1, 32'h24);
   original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h24);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   static_data32[0] = 32'h10;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   
   unstall();
   wait_for_stall();
   check_results(32'h28, 32'h24, 32'd11);
   
   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h24);


   #1000;
   $display("Put TRAP instruction before BRANCH instruction at time %t", $time);  
   do_module_burst_read(3'h4, 16'd1, 32'h20);
   original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h20);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   static_data32[0] = 32'h24;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   
   unstall();
   wait_for_stall();
   check_results(32'h24, 32'h20, 32'd24);
   
   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h20);


   #1000;
   $display("Put TRAP instruction behind LSU instruction at time %t", $time);  
   do_module_burst_read(3'h4, 16'd1, 32'h1c);
   original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h1c);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   static_data32[0] = 32'h20;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   
   unstall();
   wait_for_stall();
   check_results(32'h20, 32'h1c, 32'd49);
   
   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h1c);


   #1000;
   $display("Put TRAP instruction very near previous one at time %t", $time);  
   do_module_burst_read(3'h4, 16'd1, 32'h20);
   original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h20);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   static_data32[0] = 32'h1c;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   
   unstall();
   wait_for_stall();
   check_results(32'h24, 32'h20, 32'd50);
   
   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h20);


   #1000;
   $display("Put TRAP at the start at time %t", $time);  
   do_module_burst_read(3'h4, 16'd1, 32'h10);
   original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h10);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   static_data32[0] = 32'h20;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   
   unstall();
   wait_for_stall();
   check_results(32'h14, 32'h10, 32'd99);
   
   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h10);


   #1000;   
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   $display("Set step bit at time %t", $time);
   static_data32[0] = (1 << 22);
   do_module_burst_write(3'h4, 16'd1, (6<<11) + 16);


   for(i = 0; i < 5; i = i + 1)
     begin
	#1000;
	$display("Unstall (%d/5) at time %t", i, $time);
	unstall();
	wait_for_stall();
     end

   check_results(32'h28, 32'h24, 32'd101);

   static_data32[0] = 32'h24;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   

   for(i = 0; i < 2; i = i + 1)
     begin
	#1000;
	$display("Unstall (%d/2) at time %t", i, $time);
	unstall();
	wait_for_stall();
     end
   
  check_results(32'h10, 32'h28, 32'd201);
   
`endif

end

task check_results;      
      input [31:0] expected_npc;
      input [31:0] expected_ppc;
      input [31:0] expected_r1;
      begin

	 do_module_burst_read(3'h4, 16'd3, 32'd16);
  
	 $display("NPC = %x, expected %x", input_data32[0], expected_npc);
	 $display("PPC = %x, expected %x", input_data32[2], expected_ppc);


	 do_module_burst_read(3'h4, 16'd1, 32'h401);
	 $display("R1 = %x, expected %x", input_data32[0], expected_r1);
      end
endtask

task unstall;      
  begin

     write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2);
  end
endtask
   
task wait_for_stall;
  reg[31:0] regstate;
  begin
     regstate = 0;
     while(regstate == 0)
       begin

	       read_module_internal_register(8'd2, regstate);
	       #1000;    
       end
  end
endtask
   
task initialize_memory;
  input [31:0] start_addr;
  input [31:0] length;
  integer i;
  reg [31:0] addr;
  begin

    for (i=0; i<length; i=i+1)
      begin
        static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
        static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
        static_data8[i] <= i[7:0];
      end
  end
endtask


   




task compute_crc;
    input [31:0] crc_in;
    input [31:0] data_in;
    input [5:0] length_bits;
    output [31:0] crc_out;
    integer i;
    reg [31:0] d;
    reg [31:0] c;
    begin
        crc_out = crc_in;
        for(i = 0; i < length_bits; i = i+1) begin
           d = (data_in[i]) ? 32'hffffffff : 32'h0;
           c = (crc_out[0]) ? 32'hffffffff : 32'h0;

           crc_out = crc_out >> 1;
           crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);

        end
    end
endtask

task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
    set_ir(`IDCODE);
    

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_read_write_stream(64'h0, 8'd32, 1, readdata);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    idcode = readdata[31:0];
    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;

task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({1'b1,moduleid}, 8'h3, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    

    


end
endtask


task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
    streamdata = {11'h0,1'b0,opcode,address,burstlength};
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, 8'd53, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask

task select_module_internal_register;
    input [31:0] regidx;
    input [7:0] len;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | regidx;
    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (len+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask
        

task read_module_internal_register;

    input [7:0] len;
    output [63:0] instream;
    reg [63:0] bitmask;
begin
    instream = 64'h0;

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);

    jtag_read_write_stream(64'h0, len+4,1,instream);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    bitmask = 64'hffffffffffffffff;
    bitmask = bitmask << len;
    bitmask = ~bitmask;
    instream = instream & bitmask;
end
endtask

task write_module_internal_register;
    input [31:0] regidx;
    input [7:0] idxlen;
    input [63:0] writedata;
    input [7:0] datalen;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | writedata;
    streamdata = streamdata | (regidx << datalen);
    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
    
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (idxlen+datalen+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin

    instream = 64'h0;
    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BREAD8;
       3'h2: opcode = `DBG_WB_CMD_BREAD16;
       3'h4: opcode = `DBG_WB_CMD_BREAD32;
       default:
          begin
           $display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BREAD32;
          end
   endcase
   
   send_module_burst_command(opcode,start_address, word_count);
   



   #500;
   set_ir(`IDCODE);
   #500;
   set_ir(`DEBUG);
  #500;
  

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);
   
`ifdef ADBG_USE_HISPEED

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      



`endif   
   

   for(i = 0; i < word_count; i=i+1) begin
     
`ifndef ADBG_USE_HISPEED     

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      



`endif
  
     jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);

     compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
     crc_calc_i = crc_calc_o;
     if(word_size_bytes == 1) input_data8[i] = instream[7:0];
     else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
     else input_data32[i] = instream[31:0];
   end
    

   jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
   if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);

    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end
endtask


task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin

    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BWRITE8;
       3'h2: opcode = `DBG_WB_CMD_BWRITE16;
       3'h4: opcode = `DBG_WB_CMD_BWRITE32;
       default:
          begin
           $display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BWRITE32;
          end
   endcase
   
   send_module_burst_command(opcode, start_address, word_count);
   

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);
   


   write_bit(`JTAG_TDO_bit);


   for(i = 0; i < word_count; i=i+1) begin

      if(word_size_bytes == 4)      dataword = {32'h0, static_data32[i]};
      else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
      else                          dataword = {56'h0, static_data8[i]};
      
      
      jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
      compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
      crc_calc_i = crc_calc_o;
      
`ifndef ADBG_USE_HISPEED      


      status = 1'b0;
      read_write_bit(3'h0, status);
      
      if(!status) begin
         $display("Bad status bit during burst write, index %d", i);
      end
`endif      
  

   end
    

   jtag_write_stream(crc_calc_o, 6'd32,0);
   

   read_write_bit(`JTAG_TMS_bit, crc_match);
   if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);

    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end

endtask




task set_ir;
input [3:0] irval;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({60'h0,irval}, 8'h4, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task reset_jtag;
integer i;
begin
   for(i = 0; i < 8; i=i+1) begin
      write_bit(`JTAG_TMS_bit);
   end
   write_bit(3'h0);
end
endtask





task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       write_bit(bits);
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   write_bit(bits);
    
end
endtask


task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
    instream = 64'h0;
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       read_write_bit(bits, inbit);
       instream = (instream | (inbit << i));
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   read_write_bit(bits, inbit);
   instream = (instream | (inbit << (len-1)));
end
endtask




task write_bit;
   input [2:0] bitvals;
   begin
       

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask

task read_write_bit;
   input [2:0] bitvals;
   output l_tdi_val;
   begin
       

   l_tdi_val <= jtag_tdi_i;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask




task jtag_out;
  input   [2:0]   bitvals;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 
   end
endtask


task jtag_inout;
  input   [2:0]   bitvals;
  output l_tdi_val;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 

   l_tdi_val <= jtag_tdi_i;
   end
endtask

endmodule
module adv_debug_tb (

jtag_tck_o,
jtag_tms_o,
jtag_tdo_o,
jtag_tdi_i,

wb_clk_o,
sys_rstn_o


);
 

output jtag_tck_o;
output jtag_tms_o;
output jtag_tdo_o;
input jtag_tdi_i;
output wb_clk_o;
output sys_rstn_o;


reg jtag_tck_o;
reg jtag_tms_o;
reg jtag_tdo_o;
wire jtag_tdi_i;

reg wb_clk_o;
reg sys_rst_o;
reg sys_rstn_o;
   
reg test_enabled;


reg [31:0] static_data32 [0:15]; 
reg [15:0] static_data16 [0:15];
reg [7:0] static_data8 [0:15];


reg [31:0] input_data32 [0:15]; 
reg [15:0] input_data16 [0:15];
reg [7:0]  input_data8 [0:15];                                

reg [32:0] err_data;

reg [31:0] original_instruction;

reg failed;
integer i;

initial
begin
   jtag_tck_o = 1'b0;
   jtag_tms_o = 1'b0;
   jtag_tdo_o = 1'b0;
end


initial
begin
  wb_clk_o = 1'b0;
  forever #5 wb_clk_o = ~wb_clk_o; 
end

initial
begin
   sys_rstn_o = 1'b1;
   #200 sys_rstn_o = 1'b0;
   #5000 sys_rstn_o = 1'b1;
end



initial
begin
  test_enabled = 1'b0;


  initialize_memory(32'h0,32'h16);

  #5 test_enabled<= 1'b1;
end


always @ (posedge test_enabled)
begin

  $display("Starting advanced debug test");
  
  reset_jtag;
  #6000;
  check_idcode;
  #1000;
  

  set_ir(`DEBUG);
  #1000;
  
  
  `ifdef DBG_CPU0_SUPPORTED


  #1000; 
  $display("Selecting CPU0 module at time %t", $time);
  select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);

    

   $display("Setting reset and stall bits at time %t", $time);    
    write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2);
   #1000;
   `endif
  
  



  
`ifdef DBG_WISHBONE_SUPPORTED

  #1000; 
  $display("Selecting Wishbone module at time %t", $time);
  select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
    

    write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1);
   #1000;
   


  failed = 0;
  $display("Testing WB 8-bit burst write at time %t: resetting ", $time);
  do_module_burst_write(3'h1, 16'd16, 32'h87);
  #1000;
  $display("Testing WB 8-bit burst read at time %t", $time);
  do_module_burst_read(3'h1, 16'd16, 32'h87);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data8[i] != input_data8[i]) begin 
        failed = 1;
        $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]);
    end
  end
  if(!failed) $display("8-bit read/write OK!");
  
  


  failed = 0;
  $display("Testing WB 16-bit burst write at time %t", $time);
  do_module_burst_write(3'h2, 16'd16, 32'h22);
  #1000;
  $display("Testing WB 16-bit burst read at time %t", $time);
  do_module_burst_read(3'h2, 16'd16, 32'h22);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data16[i] != input_data16[i]) begin 
        failed = 1;
        $display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]);
    end
  end
  if(!failed) $display("16-bit read/write OK!");
 
  


  failed = 0;
  $display("Testing WB 32-bit burst write at time %t", $time);
  do_module_burst_write(3'h4, 16'd16, 32'h100);
  #1000;
  $display("Testing WB 32-bit burst read at time %t", $time);
  do_module_burst_read(3'h4, 16'd16, 32'h100);
  #1000;
   for(i = 0; i < 16; i = i+1) begin
     if(static_data32[i] != input_data32[i]) begin 
        failed = 1;
        $display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]);
    end
  end
  if(!failed) $display("32-bit read/write OK!");
    
  


  err_data = 33'h0;

  write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1);

  do_module_burst_write(3'h4, 16'd4, 32'hdeaddead);
  read_module_internal_register(8'd33, err_data);
  $display("Error bit is %d, error address is %x", err_data[0], err_data>>1);

`endif
  
  





`ifdef DBG_CPU0_SUPPORTED

  #1000; 
  $display("Selecting CPU0 module at time %t", $time);
  select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);

    

   $display("Setting reset and stall bits at time %t", $time);    
    write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2);
   #1000;
   

   $display("Testing reset and stall bits at time %t", $time);
   read_module_internal_register(8'd2, err_data);
   $display("Reset and stall bits are %x", err_data);
   #1000;
   


   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   $display("Commencing CPU functional test - writing instructions at time %t", $time);
   static_data32[0] = 32'hE0000005;
   static_data32[1] = 32'h9C200000;
   static_data32[2] = 32'h18400000;
   static_data32[3] = 32'hA8420030;
   static_data32[4] = 32'h9C210001;
   static_data32[5] = 32'h9C210001;
   static_data32[6] = 32'hD4020800;
   static_data32[7] = 32'h9C210001;
   static_data32[8] = 32'h84620000;
   static_data32[9] = 32'h03FFFFFB;
   static_data32[10] = 32'hE0211800;
   do_module_burst_write(3'h4, 16'd11, 32'h0);

   #1000;
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);


   #1000;
   $display("Testing step bit at time %t", $time);
   static_data32[0] = 32'h1;
   do_module_burst_write(3'h4, 16'd1, 32'd17);
   static_data32[0] = 32'h00002000;
   do_module_burst_write(3'h4, 16'd1, (6 << 11)+20);
   static_data32[0] = 32'h0;
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   static_data32[0] = (1 << 22);
   do_module_burst_write(3'h4, 16'd1, (6<<11) + 16);


   for(i = 0; i < 11; i = i + 1)
     begin
	#1000;
	$display("Unstall (%d/11) at time %t", i+1, $time);
	unstall();
	wait_for_stall();
     end

   #1000;
   check_results(32'h10, 32'h28, 32'h5);
  
   static_data32[0] = 32'h0;
   do_module_burst_write(3'h4, 16'd1, (6 << 11)+16);
  

   #1000;  
   $display("Put TRAP instruction in the delay slot at time %t", $time);  
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_read(3'h4, 16'd1, 32'h28);
  original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h28);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);


   unstall();
   wait_for_stall();
   check_results(32'h10, 32'h28, 32'd8);
   

   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h28);


   #1000;
   $display("Put TRAP instruction in place of BRANCH instruction at time %t", $time);  
   do_module_burst_read(3'h4, 16'd1, 32'h24);
   original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h24);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   static_data32[0] = 32'h10;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   
   unstall();
   wait_for_stall();
   check_results(32'h28, 32'h24, 32'd11);
   
   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h24);


   #1000;
   $display("Put TRAP instruction before BRANCH instruction at time %t", $time);  
   do_module_burst_read(3'h4, 16'd1, 32'h20);
   original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h20);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   static_data32[0] = 32'h24;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   
   unstall();
   wait_for_stall();
   check_results(32'h24, 32'h20, 32'd24);
   
   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h20);


   #1000;
   $display("Put TRAP instruction behind LSU instruction at time %t", $time);  
   do_module_burst_read(3'h4, 16'd1, 32'h1c);
   original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h1c);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   static_data32[0] = 32'h20;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   
   unstall();
   wait_for_stall();
   check_results(32'h20, 32'h1c, 32'd49);
   
   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h1c);


   #1000;
   $display("Put TRAP instruction very near previous one at time %t", $time);  
   do_module_burst_read(3'h4, 16'd1, 32'h20);
   original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h20);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   static_data32[0] = 32'h1c;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   
   unstall();
   wait_for_stall();
   check_results(32'h24, 32'h20, 32'd50);
   
   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h20);


   #1000;
   $display("Put TRAP at the start at time %t", $time);  
   do_module_burst_read(3'h4, 16'd1, 32'h10);
   original_instruction = input_data32[0];
   static_data32[0] = 32'h21000001;
   do_module_burst_write(3'h4, 16'd1, 32'h10);
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   static_data32[0] = 32'h20;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   
   unstall();
   wait_for_stall();
   check_results(32'h14, 32'h10, 32'd99);
   
   static_data32[0] = original_instruction;
   select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
   do_module_burst_write(3'h4, 16'd1, 32'h10);


   #1000;   
   select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
   $display("Set step bit at time %t", $time);
   static_data32[0] = (1 << 22);
   do_module_burst_write(3'h4, 16'd1, (6<<11) + 16);


   for(i = 0; i < 5; i = i + 1)
     begin
	#1000;
	$display("Unstall (%d/5) at time %t", i, $time);
	unstall();
	wait_for_stall();
     end

   check_results(32'h28, 32'h24, 32'd101);

   static_data32[0] = 32'h24;  
   do_module_burst_write(3'h4, 16'd1, 32'd16);
   

   for(i = 0; i < 2; i = i + 1)
     begin
	#1000;
	$display("Unstall (%d/2) at time %t", i, $time);
	unstall();
	wait_for_stall();
     end
   
  check_results(32'h10, 32'h28, 32'd201);
   
`endif

end

task check_results;      
      input [31:0] expected_npc;
      input [31:0] expected_ppc;
      input [31:0] expected_r1;
      begin

	 do_module_burst_read(3'h4, 16'd3, 32'd16);
  
	 $display("NPC = %x, expected %x", input_data32[0], expected_npc);
	 $display("PPC = %x, expected %x", input_data32[2], expected_ppc);


	 do_module_burst_read(3'h4, 16'd1, 32'h401);
	 $display("R1 = %x, expected %x", input_data32[0], expected_r1);
      end
endtask

task unstall;      
  begin

     write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2);
  end
endtask
   
task wait_for_stall;
  reg[31:0] regstate;
  begin
     regstate = 0;
     while(regstate == 0)
       begin

	       read_module_internal_register(8'd2, regstate);
	       #1000;    
       end
  end
endtask
   
task initialize_memory;
  input [31:0] start_addr;
  input [31:0] length;
  integer i;
  reg [31:0] addr;
  begin

    for (i=0; i<length; i=i+1)
      begin
        static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
        static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
        static_data8[i] <= i[7:0];
      end
  end
endtask


   




task compute_crc;
    input [31:0] crc_in;
    input [31:0] data_in;
    input [5:0] length_bits;
    output [31:0] crc_out;
    integer i;
    reg [31:0] d;
    reg [31:0] c;
    begin
        crc_out = crc_in;
        for(i = 0; i < length_bits; i = i+1) begin
           d = (data_in[i]) ? 32'hffffffff : 32'h0;
           c = (crc_out[0]) ? 32'hffffffff : 32'h0;

           crc_out = crc_out >> 1;
           crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);

        end
    end
endtask

task check_idcode;
reg [63:0] readdata;
reg[31:0] idcode;
begin
    set_ir(`IDCODE);
    

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_read_write_stream(64'h0, 8'd32, 1, readdata);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    idcode = readdata[31:0];
    $display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
end
endtask;

task select_debug_module;
input [1:0] moduleid;
reg validid;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({1'b1,moduleid}, 8'h3, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    

    


end
endtask


task send_module_burst_command;
input [3:0] opcode;
input [31:0] address;
input [15:0] burstlength;
reg [63:0] streamdata;
begin
    streamdata = {11'h0,1'b0,opcode,address,burstlength};
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, 8'd53, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask

task select_module_internal_register;
    input [31:0] regidx;
    input [7:0] len;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | regidx;
    streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (len+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask
        

task read_module_internal_register;

    input [7:0] len;
    output [63:0] instream;
    reg [63:0] bitmask;
begin
    instream = 64'h0;

    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);

    jtag_read_write_stream(64'h0, len+4,1,instream);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    bitmask = 64'hffffffffffffffff;
    bitmask = bitmask << len;
    bitmask = ~bitmask;
    instream = instream & bitmask;
end
endtask

task write_module_internal_register;
    input [31:0] regidx;
    input [7:0] idxlen;
    input [63:0] writedata;
    input [7:0] datalen;
    reg[63:0] streamdata;
begin
    streamdata = 64'h0;
    streamdata = streamdata | writedata;
    streamdata = streamdata | (regidx << datalen);
    streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
    
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream(streamdata, (idxlen+datalen+5), 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task do_module_burst_read;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] instream;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg [31:0] crc_read;
reg [5:0] word_size_bits;
begin

    instream = 64'h0;
    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BREAD8;
       3'h2: opcode = `DBG_WB_CMD_BREAD16;
       3'h4: opcode = `DBG_WB_CMD_BREAD32;
       default:
          begin
           $display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BREAD32;
          end
   endcase
   
   send_module_burst_command(opcode,start_address, word_count);
   



   #500;
   set_ir(`IDCODE);
   #500;
   set_ir(`DEBUG);
  #500;
  

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);
   
`ifdef ADBG_USE_HISPEED

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      



`endif   
   

   for(i = 0; i < word_count; i=i+1) begin
     
`ifndef ADBG_USE_HISPEED     

      status = 1'b0;
      j = 0;
      while(!status) begin
         read_write_bit(3'h0, status);
         j = j + 1;
      end
      



`endif
  
     jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);

     compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
     crc_calc_i = crc_calc_o;
     if(word_size_bytes == 1) input_data8[i] = instream[7:0];
     else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
     else input_data32[i] = instream[31:0];
   end
    

   jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
   if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);

    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end
endtask


task do_module_burst_write;
input [5:0] word_size_bytes;
input [15:0] word_count;
input [31:0] start_address;
reg [3:0] opcode;
reg status;
reg [63:0] dataword;
integer i;
integer j;
reg [31:0] crc_calc_i;
reg [31:0] crc_calc_o;
reg crc_match;
reg [5:0] word_size_bits;
begin

    word_size_bits = word_size_bytes << 3;
    crc_calc_i = 32'hffffffff;
    

    case (word_size_bytes)
       3'h1: opcode = `DBG_WB_CMD_BWRITE8;
       3'h2: opcode = `DBG_WB_CMD_BWRITE16;
       3'h4: opcode = `DBG_WB_CMD_BWRITE32;
       default:
          begin
           $display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
           opcode = `DBG_WB_CMD_BWRITE32;
          end
   endcase
   
   send_module_burst_command(opcode, start_address, word_count);
   

   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
   write_bit(3'h0);
   


   write_bit(`JTAG_TDO_bit);


   for(i = 0; i < word_count; i=i+1) begin

      if(word_size_bytes == 4)      dataword = {32'h0, static_data32[i]};
      else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
      else                          dataword = {56'h0, static_data8[i]};
      
      
      jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
      compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
      crc_calc_i = crc_calc_o;
      
`ifndef ADBG_USE_HISPEED      


      status = 1'b0;
      read_write_bit(3'h0, status);
      
      if(!status) begin
         $display("Bad status bit during burst write, index %d", i);
      end
`endif      
  

   end
    

   jtag_write_stream(crc_calc_o, 6'd32,0);
   

   read_write_bit(`JTAG_TMS_bit, crc_match);
   if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);

    



   write_bit(`JTAG_TMS_bit);
   write_bit(3'h0);
end

endtask




task set_ir;
input [3:0] irval;
begin
    write_bit(`JTAG_TMS_bit);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
    write_bit(3'h0);
    jtag_write_stream({60'h0,irval}, 8'h4, 1);
    write_bit(`JTAG_TMS_bit);
    write_bit(3'h0);
end
endtask


task reset_jtag;
integer i;
begin
   for(i = 0; i < 8; i=i+1) begin
      write_bit(`JTAG_TMS_bit);
   end
   write_bit(3'h0);
end
endtask





task jtag_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
integer i;
integer databit;
reg [2:0] bits;
begin
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       write_bit(bits);
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   write_bit(bits);
    
end
endtask


task jtag_read_write_stream;
input [63:0] stream;
input [7:0] len;
input set_last_bit;
output [63:0] instream;
integer i;
integer databit;
reg [2:0] bits;
reg inbit;
begin
    instream = 64'h0;
    for(i = 0; i < (len-1); i=i+1) begin
       databit = (stream >> i) & 1'h1;
       bits = databit << `JTAG_TDO;
       read_write_bit(bits, inbit);
       instream = (instream | (inbit << i));
   end
   
   databit = (stream >> i) & 1'h1;
   bits = databit << `JTAG_TDO;
   if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
   read_write_bit(bits, inbit);
   instream = (instream | (inbit << (len-1)));
end
endtask




task write_bit;
   input [2:0] bitvals;
   begin
       

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask

task read_write_bit;
   input [2:0] bitvals;
   output l_tdi_val;
   begin
       

   l_tdi_val <= jtag_tdi_i;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   

   jtag_out(bitvals | `JTAG_TCK_bit);
   `wait_jtag_period;
   

   jtag_out(bitvals & ~(`JTAG_TCK_bit));
   `wait_jtag_period;
   end
endtask




task jtag_out;
  input   [2:0]   bitvals;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 
   end
endtask


task jtag_inout;
  input   [2:0]   bitvals;
  output l_tdi_val;
  begin

   jtag_tck_o <= bitvals[`JTAG_TCK]; 
   jtag_tms_o <= bitvals[`JTAG_TMS]; 
   jtag_tdo_o <= bitvals[`JTAG_TDO]; 

   l_tdi_val <= jtag_tdi_i;
   end
endtask

endmodule