data/full_repos/permissive/159166357/tests/main_alu_test.v
1: b'%Error: data/full_repos/permissive/159166357/tests/main_alu_test.v:8: Cannot find file containing module: \'SB_PLL40_CORE\'\n    SB_PLL40_CORE #(\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159166357/tests,data/full_repos/permissive/159166357/SB_PLL40_CORE\n             data/full_repos/permissive/159166357/tests,data/full_repos/permissive/159166357/SB_PLL40_CORE.v\n             data/full_repos/permissive/159166357/tests,data/full_repos/permissive/159166357/SB_PLL40_CORE.sv\n             SB_PLL40_CORE\n             SB_PLL40_CORE.v\n             SB_PLL40_CORE.sv\n             obj_dir/SB_PLL40_CORE\n             obj_dir/SB_PLL40_CORE.v\n             obj_dir/SB_PLL40_CORE.sv\n%Error: data/full_repos/permissive/159166357/tests/main_alu_test.v:27: Cannot find file containing module: \'main_alu\'\n   main_alu ALU0\n   ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/159166357/tests/main_alu_test.v:41: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'opsel\' generates 4 bits.\n                                                                             : ... In instance main_alu_top\n  opsel <= opsel + 32\'b1;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159166357/tests/main_alu_test.v:41: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                             : ... In instance main_alu_top\n  opsel <= opsel + 32\'b1;\n        ^~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module main_alu_top
  (
   input wire clk,
   input wire rst
   );
   wire       lock;
   wire       pll_clk;
    SB_PLL40_CORE #(
        .FEEDBACK_PATH("SIMPLE"),
        .PLLOUT_SELECT("GENCLK"),
        .DIVR(4'b0000),
        .DIVF(7'b0101111),
        .DIVQ(3'b100),
        .FILTER_RANGE(3'b001)
    ) pll0 (
        .LOCK(lock),
        .RESETB(1'b1),
        .BYPASS(1'b0),
        .REFERENCECLK(clk),
        .PLLOUTCORE(pll_clk)
    );
   reg [31:0] op1, op2;
   reg [3:0] opsel;
   wire [31:0] aluout;
   (*keep*)
   reg [31:0]  result;
   main_alu ALU0
     (
      .i_clk(pll_clk),
      .i_op1(op1), .i_op2(op2), .i_opsel(opsel),
      .o_aluout(aluout)
      );

   always @ (posedge pll_clk) begin
      if (rst) begin
	 op1 <= 32'b0;
	 op2 <= 32'hffffffff;
	 opsel <= 4'b0;
      end
      else begin
	 opsel <= opsel + 32'b1;
	 op1 <= op1 + 32'h10000;
	 op2 <= op2 + 32'h100000;
      end
   end
   always @ (posedge pll_clk) begin
	 result <= aluout;
   end
endmodule
module main_alu_top
  (
   input wire clk,
   input wire rst
   );

   wire       lock;
   wire       pll_clk;
    SB_PLL40_CORE #(
        .FEEDBACK_PATH("SIMPLE"),
        .PLLOUT_SELECT("GENCLK"),
        .DIVR(4'b0000),
        .DIVF(7'b0101111),
        .DIVQ(3'b100),
        .FILTER_RANGE(3'b001)
    ) pll0 (
        .LOCK(lock),
        .RESETB(1'b1),
        .BYPASS(1'b0),
        .REFERENCECLK(clk),
        .PLLOUTCORE(pll_clk)
    );
   reg [31:0] op1, op2;
   reg [3:0] opsel;
   wire [31:0] aluout;
   (*keep*)
   reg [31:0]  result;
   main_alu ALU0
     (
      .i_clk(pll_clk),
      .i_op1(op1), .i_op2(op2), .i_opsel(opsel),
      .o_aluout(aluout)
      );

   always @ (posedge pll_clk) begin
      if (rst) begin
	 op1 <= 32'b0;
	 op2 <= 32'hffffffff;
	 opsel <= 4'b0;
      end
      else begin
	 opsel <= opsel + 32'b1;
	 op1 <= op1 + 32'h10000;
	 op2 <= op2 + 32'h100000;
      end
   end
   always @ (posedge pll_clk) begin
	 result <= aluout;
   end
endmodule