data/full_repos/permissive/160991228/src/hdl/common/FIFO.v
1: b"%Error: data/full_repos/permissive/160991228/src/hdl/common/FIFO.v:43: Cannot find file containing module: 'DP_BRAM'\nDP_BRAM #(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160991228/src/hdl/common,data/full_repos/permissive/160991228/DP_BRAM\n             data/full_repos/permissive/160991228/src/hdl/common,data/full_repos/permissive/160991228/DP_BRAM.v\n             data/full_repos/permissive/160991228/src/hdl/common,data/full_repos/permissive/160991228/DP_BRAM.sv\n             DP_BRAM\n             DP_BRAM.v\n             DP_BRAM.sv\n             obj_dir/DP_BRAM\n             obj_dir/DP_BRAM.v\n             obj_dir/DP_BRAM.sv\n%Error: Exiting due to 1 error(s)\n"
module FIFO#(
    parameter integer DATA_WIDTH = 8, 
    parameter integer ADDR_WIDTH = 4
)(    
    input clk, 
    input rst, 
    input [DATA_WIDTH-1:0] in, 
    input wr_en, 
    input rd_en, 
    output [DATA_WIDTH-1:0] out, 
    output full, 
    output empty
);
parameter DEPTH = (2 ** ADDR_WIDTH);

reg [ADDR_WIDTH-1:0] head, tail;
reg [ADDR_WIDTH-1:0] total;

DP_BRAM #(
    .DATA_WIDTH(DATA_WIDTH), 
    .ADDR_WIDTH(ADDR_WIDTH)
) mem(
    .clk(clk), 
    .data_in(in), 
    .waddr(tail),
    .wr_en(wr_en), 
    .data_out(out), 
    .raddr(head)
);

assign full = (total == (DEPTH-1)); 
assign empty = (total==0);

always@(posedge clk) begin
    if(rst) begin
        tail <= {ADDR_WIDTH{1'b0}}; 
        head <= {ADDR_WIDTH{1'b0}}; 
        total <= {ADDR_WIDTH{1'b0}};
    end
    else begin
        if(wr_en) begin
            tail <= tail + 1;
        end

        if(rd_en) begin
            head <= head + 1;
        end

        if(rd_en == 1 && wr_en == 0) begin
            total <= total - 1;
        end

        if(rd_en == 0 && wr_en == 1) begin
            total <= total + 1;
        end
    end
end
endmodule
module FIFO#(
    parameter integer DATA_WIDTH = 8, 
    parameter integer ADDR_WIDTH = 4
)(    
    input clk, 
    input rst, 
    input [DATA_WIDTH-1:0] in, 
    input wr_en, 
    input rd_en, 
    output [DATA_WIDTH-1:0] out, 
    output full, 
    output empty
);

parameter DEPTH = (2 ** ADDR_WIDTH);

reg [ADDR_WIDTH-1:0] head, tail;
reg [ADDR_WIDTH-1:0] total;

DP_BRAM #(
    .DATA_WIDTH(DATA_WIDTH), 
    .ADDR_WIDTH(ADDR_WIDTH)
) mem(
    .clk(clk), 
    .data_in(in), 
    .waddr(tail),
    .wr_en(wr_en), 
    .data_out(out), 
    .raddr(head)
);

assign full = (total == (DEPTH-1)); 
assign empty = (total==0);

always@(posedge clk) begin
    if(rst) begin
        tail <= {ADDR_WIDTH{1'b0}}; 
        head <= {ADDR_WIDTH{1'b0}}; 
        total <= {ADDR_WIDTH{1'b0}};
    end
    else begin
        if(wr_en) begin
            tail <= tail + 1;
        end

        if(rd_en) begin
            head <= head + 1;
        end

        if(rd_en == 1 && wr_en == 0) begin
            total <= total - 1;
        end

        if(rd_en == 0 && wr_en == 1) begin
            total <= total + 1;
        end
    end
end
endmodule