data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:10: Define or directive not defined: \'`BlockAddrWidth\'\n  input wire[`BlockAddrWidth-1:0] addr,  \n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:11: Define or directive not defined: \'`BlockWidth\'\n  input wire[`BlockWidth-1:0] write_data,  \n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:12: Define or directive not defined: \'`BlockWidth\'\n  output reg[`BlockWidth-1:0] read_data,  \n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:19: Define or directive not defined: \'`BlockWidth\'\n reg[`BlockWidth-1:0] next_read_data;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:24: Define or directive not defined: \'`CacheDispWidth\'\n reg[`CacheDispWidth-1:0] data_disp;\n     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:28: Define or directive not defined: \'`CacheDispWidth\'\n reg[`CacheDispWidth-1:0] next_data_disp;\n     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:43: Define or directive not defined: \'`NotBusy\'\n  if(rst || !ce || busy == `NotBusy) begin\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:43: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if(rst || !ce || busy == `NotBusy) begin\n                                   ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:44: Define or directive not defined: \'`ZeroWord\'\n   opaddr <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:46: Define or directive not defined: \'`MemRead\'\n   if(optype == `MemRead) begin\n                ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:47: Define or directive not defined: \'`ReadOpHead\'\n    opaddr <= {`ReadOpHead, addr};\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:49: Define or directive not defined: \'`WriteOpHead\'\n    opaddr <= {`WriteOpHead, addr};\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:55: Define or directive not defined: \'`SendDisable\'\n   uart_send_flag <= `SendDisable;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:56: Define or directive not defined: \'`ZeroByte\'\n   uart_send_data <= `ZeroByte;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:57: Define or directive not defined: \'`RecvDisable\'\n   uart_recv_flag <= `RecvDisable;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:58: Define or directive not defined: \'`NotBusy\'\n   next_busy <= `NotBusy;\n                ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:59: Define or directive not defined: \'`ZeroBlock\'\n   next_read_data <= `ZeroBlock;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:61: Define or directive not defined: \'`ZeroHeadDisp\'\n   next_head_disp <= `ZeroHeadDisp;\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:62: Define or directive not defined: \'`ZeroDataDisp\'\n   next_data_disp <= `ZeroDataDisp;\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:63: Define or directive not defined: \'`NotBusy\'\n  end else if(busy == `NotBusy) begin  \n                      ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:64: Define or directive not defined: \'`SendDisable\'\n   uart_send_flag <= `SendDisable;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:65: Define or directive not defined: \'`ZeroByte\'\n   uart_send_data <= `ZeroByte;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:66: Define or directive not defined: \'`RecvDisable\'\n   uart_recv_flag <= `RecvDisable;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:74: Define or directive not defined: \'`SendDisable\'\n   uart_send_flag <= `SendDisable;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:75: Define or directive not defined: \'`ZeroByte\'\n   uart_send_data <= `ZeroByte;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:76: Define or directive not defined: \'`RecvDisable\'\n   uart_recv_flag <= `RecvDisable;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:83: Define or directive not defined: \'`MemRead\'\n   if(optype == `MemRead) begin  \n                ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:83: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   if(optype == `MemRead) begin  \n                        ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:84: Define or directive not defined: \'`TransAddr\'\n    if(trans_status == `TransAddr) begin  \n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:86: Define or directive not defined: \'`SendEnable\'\n      uart_send_flag <= `SendEnable;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:88: syntax error, unexpected \'[\', expecting IDENTIFIER\n       uart_send_data[idx[2:0]] <= opaddr[{head_disp,idx[2:0]}];\n                     ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:90: syntax error, unexpected <=, expecting IDENTIFIER\n      uart_recv_flag <= `RecvDisable;\n                     ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:90: Define or directive not defined: \'`RecvDisable\'\n      uart_recv_flag <= `RecvDisable;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:91: Define or directive not defined: \'`IsBusy\'\n      next_busy <= `IsBusy;\n                   ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:92: Define or directive not defined: \'`ZeroBlock\'\n      next_read_data <= `ZeroBlock;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:93: Define or directive not defined: \'`FullHeadDisp\'\n      next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);\n                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:93: Define or directive not defined: \'`TransData\'\n      next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:93: Define or directive not defined: \'`TransAddr\'\n      next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);\n                                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:95: Define or directive not defined: \'`ZeroDataDisp\'\n      next_data_disp <= `ZeroDataDisp;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:99: Define or directive not defined: \'`SendDisable\'\n      uart_send_flag <= `SendDisable;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:100: Define or directive not defined: \'`ZeroByte\'\n      uart_send_data <= `ZeroByte;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:101: Define or directive not defined: \'`RecvEnable\'\n      uart_recv_flag <= `RecvEnable;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:102: Define or directive not defined: \'`FullDataDisp\'\n      next_busy <= (data_disp != `FullDataDisp);\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n       next_read_data[{data_disp,idx[2:0]}] <= uart_recv_data[idx[2:0]];\n                     ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:107: syntax error, unexpected <=, expecting IDENTIFIER\n      next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);\n                        ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:107: Define or directive not defined: \'`FullDataDisp\'\n      next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);\n                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:107: Define or directive not defined: \'`TransAddr\'\n      next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:107: Define or directive not defined: \'`TransData\'\n      next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);\n                                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:108: Define or directive not defined: \'`ZeroHeadDisp\'\n      next_head_disp <= `ZeroHeadDisp;\n                        ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module memory_ctrl(
		input wire clk,
		input wire rst,
		input wire ce,
		input wire optype,	

		input wire[`BlockAddrWidth-1:0] addr,
		input wire[`BlockWidth-1:0] write_data,
		output reg[`BlockWidth-1:0] read_data,
		output reg busy,

		output wire Tx,
		input Rx
	);

	reg[`BlockWidth-1:0] next_read_data;
	reg next_busy;

	reg trans_status;
	reg[1:0] head_disp;
	reg[`CacheDispWidth-1:0] data_disp;
	
	reg next_trans_status;
	reg[1:0] next_head_disp;
	reg[`CacheDispWidth-1:0] next_data_disp;


	reg uart_send_flag, uart_recv_flag;
	reg[7:0] uart_send_data;
	wire[7:0] uart_recv_data;
	wire uart_receivable, uart_sendable;

	uart_comm uart0( clk, rst, uart_send_flag, uart_send_data, uart_recv_flag, 
		uart_recv_data, uart_sendable, uart_receivable, Tx, Rx);

	integer idx;

	reg[31:0] opaddr;
	always @ (*) begin
		if(rst || !ce || busy == `NotBusy) begin
			opaddr <= `ZeroWord;
		end else begin
			if(optype == `MemRead) begin
				opaddr <= {`ReadOpHead, addr};
			end else begin
				opaddr <= {`WriteOpHead, addr};
			end
		end
	end
	always @ (*) begin
		if(rst || !ce) begin
			uart_send_flag <= `SendDisable;
			uart_send_data <= `ZeroByte;
			uart_recv_flag <= `RecvDisable;
			next_busy <= `NotBusy;
			next_read_data <= `ZeroBlock;
			next_trans_status <= 1'b0;
			next_head_disp <= `ZeroHeadDisp;
			next_data_disp <= `ZeroDataDisp;
		end else if(busy == `NotBusy) begin
			uart_send_flag <= `SendDisable;
			uart_send_data <= `ZeroByte;
			uart_recv_flag <= `RecvDisable;
			next_busy <= busy;
			next_read_data <= read_data;
			next_trans_status <= trans_status;
			next_head_disp <= head_disp;
			next_data_disp <= data_disp;
		end else begin

			uart_send_flag <= `SendDisable;
			uart_send_data <= `ZeroByte;
			uart_recv_flag <= `RecvDisable;
			next_busy <= busy;
			next_read_data <= read_data;
			next_trans_status <= trans_status;
			next_head_disp <= head_disp;
			next_data_disp <= data_disp;

			if(optype == `MemRead) begin
				if(trans_status == `TransAddr) begin
					if(uart_sendable) begin
						uart_send_flag <= `SendEnable;
						for(idx = 0; idx < 8; idx = idx + 1) begin
							uart_send_data[idx[2:0]] <= opaddr[{head_disp,idx[2:0]}];
						end
						uart_recv_flag <= `RecvDisable;
						next_busy <= `IsBusy;
						next_read_data <= `ZeroBlock;
						next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);
						next_head_disp <= head_disp + 1;
						next_data_disp <= `ZeroDataDisp;
					end 
				end else begin
					if(uart_receivable) begin
						uart_send_flag <= `SendDisable;
						uart_send_data <= `ZeroByte;
						uart_recv_flag <= `RecvEnable;
						next_busy <= (data_disp != `FullDataDisp);
						next_read_data <= read_data;
						for(idx = 0; idx < 8; idx=idx+1) begin
							next_read_data[{data_disp,idx[2:0]}] <= uart_recv_data[idx[2:0]];
						end
						next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);
						next_head_disp <= `ZeroHeadDisp;
						next_data_disp <= data_disp + 1;
					end
				end
			end else begin
				if(trans_status == `TransAddr) begin
					if(uart_sendable) begin
						uart_send_flag <= `SendEnable;
						for(idx = 0; idx < 8; idx = idx + 1) begin
							uart_send_data[idx[2:0]] <= opaddr[{head_disp,idx[2:0]}];
						end
						uart_recv_flag <= `RecvDisable;
						next_busy <= `IsBusy;
						next_read_data <= `ZeroBlock;
						next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);
						next_head_disp <= head_disp + 1;
						next_data_disp <= `ZeroDataDisp;
					end 
				end else begin
					if(uart_sendable) begin
						uart_send_flag <= `SendEnable;
						for(idx = 0; idx < 8; idx = idx + 1) begin
							uart_send_data[idx[2:0]] <= write_data[{data_disp,idx[2:0]}];
						end
						uart_recv_flag <= `RecvDisable;
						next_busy <= (data_disp != `FullDataDisp);
						next_read_data <= `ZeroBlock;
						next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);
						next_head_disp <= `ZeroHeadDisp;
						next_data_disp <= data_disp + 1;
					end
				end
			end
		end
	end
	always @ (posedge clk) begin
		busy <= next_busy;
		read_data <= next_read_data;
		trans_status <= next_trans_status;
		head_disp <= next_head_disp;
		data_disp <= next_data_disp;
	end
endmodule
module memory_ctrl(
		input wire clk,
		input wire rst,
		input wire ce,
		input wire optype,	

		input wire[`BlockAddrWidth-1:0] addr,
		input wire[`BlockWidth-1:0] write_data,
		output reg[`BlockWidth-1:0] read_data,
		output reg busy,

		output wire Tx,
		input Rx
	);


	reg[`BlockWidth-1:0] next_read_data;
	reg next_busy;

	reg trans_status;
	reg[1:0] head_disp;
	reg[`CacheDispWidth-1:0] data_disp;
	
	reg next_trans_status;
	reg[1:0] next_head_disp;
	reg[`CacheDispWidth-1:0] next_data_disp;


	reg uart_send_flag, uart_recv_flag;
	reg[7:0] uart_send_data;
	wire[7:0] uart_recv_data;
	wire uart_receivable, uart_sendable;

	uart_comm uart0( clk, rst, uart_send_flag, uart_send_data, uart_recv_flag, 
		uart_recv_data, uart_sendable, uart_receivable, Tx, Rx);

	integer idx;

	reg[31:0] opaddr;
	always @ (*) begin
		if(rst || !ce || busy == `NotBusy) begin
			opaddr <= `ZeroWord;
		end else begin
			if(optype == `MemRead) begin
				opaddr <= {`ReadOpHead, addr};
			end else begin
				opaddr <= {`WriteOpHead, addr};
			end
		end
	end
	always @ (*) begin
		if(rst || !ce) begin
			uart_send_flag <= `SendDisable;
			uart_send_data <= `ZeroByte;
			uart_recv_flag <= `RecvDisable;
			next_busy <= `NotBusy;
			next_read_data <= `ZeroBlock;
			next_trans_status <= 1'b0;
			next_head_disp <= `ZeroHeadDisp;
			next_data_disp <= `ZeroDataDisp;
		end else if(busy == `NotBusy) begin
			uart_send_flag <= `SendDisable;
			uart_send_data <= `ZeroByte;
			uart_recv_flag <= `RecvDisable;
			next_busy <= busy;
			next_read_data <= read_data;
			next_trans_status <= trans_status;
			next_head_disp <= head_disp;
			next_data_disp <= data_disp;
		end else begin

			uart_send_flag <= `SendDisable;
			uart_send_data <= `ZeroByte;
			uart_recv_flag <= `RecvDisable;
			next_busy <= busy;
			next_read_data <= read_data;
			next_trans_status <= trans_status;
			next_head_disp <= head_disp;
			next_data_disp <= data_disp;

			if(optype == `MemRead) begin
				if(trans_status == `TransAddr) begin
					if(uart_sendable) begin
						uart_send_flag <= `SendEnable;
						for(idx = 0; idx < 8; idx = idx + 1) begin
							uart_send_data[idx[2:0]] <= opaddr[{head_disp,idx[2:0]}];
						end
						uart_recv_flag <= `RecvDisable;
						next_busy <= `IsBusy;
						next_read_data <= `ZeroBlock;
						next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);
						next_head_disp <= head_disp + 1;
						next_data_disp <= `ZeroDataDisp;
					end 
				end else begin
					if(uart_receivable) begin
						uart_send_flag <= `SendDisable;
						uart_send_data <= `ZeroByte;
						uart_recv_flag <= `RecvEnable;
						next_busy <= (data_disp != `FullDataDisp);
						next_read_data <= read_data;
						for(idx = 0; idx < 8; idx=idx+1) begin
							next_read_data[{data_disp,idx[2:0]}] <= uart_recv_data[idx[2:0]];
						end
						next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);
						next_head_disp <= `ZeroHeadDisp;
						next_data_disp <= data_disp + 1;
					end
				end
			end else begin
				if(trans_status == `TransAddr) begin
					if(uart_sendable) begin
						uart_send_flag <= `SendEnable;
						for(idx = 0; idx < 8; idx = idx + 1) begin
							uart_send_data[idx[2:0]] <= opaddr[{head_disp,idx[2:0]}];
						end
						uart_recv_flag <= `RecvDisable;
						next_busy <= `IsBusy;
						next_read_data <= `ZeroBlock;
						next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);
						next_head_disp <= head_disp + 1;
						next_data_disp <= `ZeroDataDisp;
					end 
				end else begin
					if(uart_sendable) begin
						uart_send_flag <= `SendEnable;
						for(idx = 0; idx < 8; idx = idx + 1) begin
							uart_send_data[idx[2:0]] <= write_data[{data_disp,idx[2:0]}];
						end
						uart_recv_flag <= `RecvDisable;
						next_busy <= (data_disp != `FullDataDisp);
						next_read_data <= `ZeroBlock;
						next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);
						next_head_disp <= `ZeroHeadDisp;
						next_data_disp <= data_disp + 1;
					end
				end
			end
		end
	end
	always @ (posedge clk) begin
		busy <= next_busy;
		read_data <= next_read_data;
		trans_status <= next_trans_status;
		head_disp <= next_head_disp;
		data_disp <= next_data_disp;
	end
endmodule