data/full_repos/permissive/200314387/verilog/74423/hct74423.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74423/hct74423.v:46: Unsupported: Ignoring delay on this delayed statement.\n            #TriggerPD\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74423/hct74423.v:48: Unsupported: Ignoring delay on this delayed statement.\n            #PulseWidth\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74423/hct74423.v:55: Unsupported: Ignoring delay on this delayed statement.\n            #TriggerPD\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74423/hct74423.v:57: Unsupported: Ignoring delay on this delayed statement.\n            #PulseWidth\n            ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hct74423 (
    input _A, B, _R, 
    output Q, _Q
);
    
    parameter PulseWidth=100;
    parameter TriggerPD=25;






    reg q;
    assign Q = q;
    assign _Q = !Q;

    always @* begin
        if (_R) begin
            if (_A) 
                q=0;
            else if (!B) 
                q=0;
        end
        else
        begin
            q=0;
        end
    end
    

    always @(posedge B) begin
        if (!_A) begin
            #TriggerPD
            q=1;
            #PulseWidth
            q=0;
        end
    end

    always @(negedge _A) begin
        if (B) begin
            #TriggerPD
            q=1;
            #PulseWidth
            q=0;
        end
    end
    
endmodule
module hct74423 (
    input _A, B, _R, 
    output Q, _Q
);

    
    parameter PulseWidth=100;
    parameter TriggerPD=25;






    reg q;
    assign Q = q;
    assign _Q = !Q;

    always @* begin
        if (_R) begin
            if (_A) 
                q=0;
            else if (!B) 
                q=0;
        end
        else
        begin
            q=0;
        end
    end
    

    always @(posedge B) begin
        if (!_A) begin
            #TriggerPD
            q=1;
            #PulseWidth
            q=0;
        end
    end

    always @(negedge _A) begin
        if (B) begin
            #TriggerPD
            q=1;
            #PulseWidth
            q=0;
        end
    end
    
endmodule