data/full_repos/permissive/143278/ivltests/pr1477190.v
 line:13: before: "b"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1477190.v:8: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (b !== 0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr1477190.v:13: Unsupported: Verilog 1995 force\n      force b = a;\n      ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1477190.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (b !== 1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1477190.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (b !== 0) begin\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1477190.v:26: Unsupported: Verilog 1995 release\n      #1 release b;\n         ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1477190.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #1 release b;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1477190.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 a = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1477190.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (b !== 1) begin\n      ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg b, a;

   initial begin
      b = 0;
      a = 1;
      #1 if (b !== 0) begin
	 $display("FAILED -- b starts out as %b", b);
	 $finish;
      end

      force b = a;
      #1 if (b !== 1) begin
	 $display("FAILED -- b=%b, a=%b", b, a);
	 $finish;
      end

      a = 0;
      #1 if (b !== 0) begin
	 $display("FAILED -- b=%b, a=%b", b, a);
	 $finish;
      end

      a = 1;
      #1 release b;
      #1 a = 0;
      #1 if (b !== 1) begin
	 $display("FAILED -- b=%b didnot hold value after release", b);
	 $finish;
      end

      b = 0;
      if (b !== 0) begin
	 $display("FAILED -- assign failed b=%b", b);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;


   reg b, a;

   initial begin
      b = 0;
      a = 1;
      #1 if (b !== 0) begin
	 $display("FAILED -- b starts out as %b", b);
	 $finish;
      end

      force b = a;
      #1 if (b !== 1) begin
	 $display("FAILED -- b=%b, a=%b", b, a);
	 $finish;
      end

      a = 0;
      #1 if (b !== 0) begin
	 $display("FAILED -- b=%b, a=%b", b, a);
	 $finish;
      end

      a = 1;
      #1 release b;
      #1 a = 0;
      #1 if (b !== 1) begin
	 $display("FAILED -- b=%b didnot hold value after release", b);
	 $finish;
      end

      b = 0;
      if (b !== 0) begin
	 $display("FAILED -- assign failed b=%b", b);
	 $finish;
      end

      $display("PASSED");
   end
endmodule