data/full_repos/permissive/114811571/test/samples/bus_array/bus_array.sv
data/verilator_xmls/4f1dfae5-e123-4bf2-b15e-31dcebe7768a.xml
module   test_pe_comp_unq1  #(
  parameter DataWidth = 16
) (
  input [8:0]                    op_code,

  input  [DataWidth-1:0]         op_a,
  input  [DataWidth-1:0]         op_b,
  input                          op_d_p,


  output logic [DataWidth-1:0]   res,
  output logic                   res_p
);

















































   













































































































































































endmodule
module   test_pe_comp_unq1  #(
  parameter DataWidth = 16
) (
  input [8:0]                    op_code,

  input  [DataWidth-1:0]         op_a,
  input  [DataWidth-1:0]         op_b,
  input                          op_d_p,


  output logic [DataWidth-1:0]   res,
  output logic                   res_p
);


















































   













































































































































































endmodule