data/full_repos/permissive/189013641/src/rama.v
None: at end of input
1: b"%Error: data/full_repos/permissive/189013641/src/rama.v:60: Cannot find file containing module: 'BLKMEMDP_V6_3'\n      BLKMEMDP_V6_3 #(\n      ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/189013641/src,data/full_repos/permissive/189013641/BLKMEMDP_V6_3\n             data/full_repos/permissive/189013641/src,data/full_repos/permissive/189013641/BLKMEMDP_V6_3.v\n             data/full_repos/permissive/189013641/src,data/full_repos/permissive/189013641/BLKMEMDP_V6_3.sv\n             BLKMEMDP_V6_3\n             BLKMEMDP_V6_3.v\n             BLKMEMDP_V6_3.sv\n             obj_dir/BLKMEMDP_V6_3\n             obj_dir/BLKMEMDP_V6_3.v\n             obj_dir/BLKMEMDP_V6_3.sv\n%Error: Exiting due to 1 error(s)\n"
module rama(
	addra,
	addrb,
	clka,
	clkb,
	dinb,
	douta,
	web);


input [8 : 0] addra;
input [8 : 0] addrb;
input clka;
input clkb;
input [12 : 0] dinb;
output [12 : 0] douta;
input web;



      BLKMEMDP_V6_3 #(
		.c_addra_width(9),
		.c_addrb_width(9),
		.c_default_data("0"),
		.c_depth_a(365),
		.c_depth_b(365),
		.c_enable_rlocs(0),
		.c_has_default_data(0),
		.c_has_dina(0),
		.c_has_dinb(1),
		.c_has_douta(1),
		.c_has_doutb(0),
		.c_has_ena(0),
		.c_has_enb(0),
		.c_has_limit_data_pitch(0),
		.c_has_nda(0),
		.c_has_ndb(0),
		.c_has_rdya(0),
		.c_has_rdyb(0),
		.c_has_rfda(0),
		.c_has_rfdb(0),
		.c_has_sinita(0),
		.c_has_sinitb(0),
		.c_has_wea(0),
		.c_has_web(1),
		.c_limit_data_pitch(18),
		.c_mem_init_file("rama.mif"),
		.c_pipe_stages_a(0),
		.c_pipe_stages_b(0),
		.c_reg_inputsa(0),
		.c_reg_inputsb(0),
		.c_sim_collision_check("NONE"),
		.c_sinita_value("0"),
		.c_sinitb_value("0"),
		.c_width_a(13),
		.c_width_b(13),
		.c_write_modea(0),
		.c_write_modeb(0),
		.c_ybottom_addr("0"),
		.c_yclka_is_rising(1),
		.c_yclkb_is_rising(1),
		.c_yena_is_high(1),
		.c_yenb_is_high(1),
		.c_yhierarchy("hierarchy1"),
		.c_ymake_bmm(0),
		.c_yprimitive_type("16kx1"),
		.c_ysinita_is_high(1),
		.c_ysinitb_is_high(1),
		.c_ytop_addr("1024"),
		.c_yuse_single_primitive(0),
		.c_ywea_is_high(1),
		.c_yweb_is_high(1),
		.c_yydisable_warnings(1))
	inst (
		.ADDRA(addra),
		.ADDRB(addrb),
		.CLKA(clka),
		.CLKB(clkb),
		.DINB(dinb),
		.DOUTA(douta),
		.WEB(web),
		.DINA(),
		.DOUTB(),
		.ENA(),
		.ENB(),
		.NDA(),
		.NDB(),
		.RFDA(),
		.RFDB(),
		.RDYA(),
		.RDYB(),
		.SINITA(),
		.SINITB(),
		.WEA());








endmodule
module rama(
	addra,
	addrb,
	clka,
	clkb,
	dinb,
	douta,
	web);



input [8 : 0] addra;
input [8 : 0] addrb;
input clka;
input clkb;
input [12 : 0] dinb;
output [12 : 0] douta;
input web;



      BLKMEMDP_V6_3 #(
		.c_addra_width(9),
		.c_addrb_width(9),
		.c_default_data("0"),
		.c_depth_a(365),
		.c_depth_b(365),
		.c_enable_rlocs(0),
		.c_has_default_data(0),
		.c_has_dina(0),
		.c_has_dinb(1),
		.c_has_douta(1),
		.c_has_doutb(0),
		.c_has_ena(0),
		.c_has_enb(0),
		.c_has_limit_data_pitch(0),
		.c_has_nda(0),
		.c_has_ndb(0),
		.c_has_rdya(0),
		.c_has_rdyb(0),
		.c_has_rfda(0),
		.c_has_rfdb(0),
		.c_has_sinita(0),
		.c_has_sinitb(0),
		.c_has_wea(0),
		.c_has_web(1),
		.c_limit_data_pitch(18),
		.c_mem_init_file("rama.mif"),
		.c_pipe_stages_a(0),
		.c_pipe_stages_b(0),
		.c_reg_inputsa(0),
		.c_reg_inputsb(0),
		.c_sim_collision_check("NONE"),
		.c_sinita_value("0"),
		.c_sinitb_value("0"),
		.c_width_a(13),
		.c_width_b(13),
		.c_write_modea(0),
		.c_write_modeb(0),
		.c_ybottom_addr("0"),
		.c_yclka_is_rising(1),
		.c_yclkb_is_rising(1),
		.c_yena_is_high(1),
		.c_yenb_is_high(1),
		.c_yhierarchy("hierarchy1"),
		.c_ymake_bmm(0),
		.c_yprimitive_type("16kx1"),
		.c_ysinita_is_high(1),
		.c_ysinitb_is_high(1),
		.c_ytop_addr("1024"),
		.c_yuse_single_primitive(0),
		.c_ywea_is_high(1),
		.c_yweb_is_high(1),
		.c_yydisable_warnings(1))
	inst (
		.ADDRA(addra),
		.ADDRB(addrb),
		.CLKA(clka),
		.CLKB(clkb),
		.DINB(dinb),
		.DOUTA(douta),
		.WEB(web),
		.DINA(),
		.DOUTB(),
		.ENA(),
		.ENB(),
		.NDA(),
		.NDB(),
		.RFDA(),
		.RFDB(),
		.RDYA(),
		.RDYB(),
		.SINITA(),
		.SINITB(),
		.WEA());








endmodule