data/full_repos/permissive/204486675/hdl/pll.v
1: b"%Error: data/full_repos/permissive/204486675/hdl/pll.v:23: Cannot find file containing module: 'SB_PLL40_CORE'\nSB_PLL40_CORE #(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/204486675/hdl,data/full_repos/permissive/204486675/SB_PLL40_CORE\n             data/full_repos/permissive/204486675/hdl,data/full_repos/permissive/204486675/SB_PLL40_CORE.v\n             data/full_repos/permissive/204486675/hdl,data/full_repos/permissive/204486675/SB_PLL40_CORE.sv\n             SB_PLL40_CORE\n             SB_PLL40_CORE.v\n             SB_PLL40_CORE.sv\n             obj_dir/SB_PLL40_CORE\n             obj_dir/SB_PLL40_CORE.v\n             obj_dir/SB_PLL40_CORE.sv\n%Error: Exiting due to 1 error(s)\n"
module pll(
	input  clock_in,
	output clock_out,
	output locked
	);

SB_PLL40_CORE #(
		.FEEDBACK_PATH("SIMPLE"),
		.DIVR(4'b0100),
		.DIVF(7'b1000110),
		.DIVQ(3'b110),
		.FILTER_RANGE(3'b010)
	) uut (
		.LOCK(locked),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.REFERENCECLK(clock_in),
		.PLLOUTCORE(clock_out)





		);

endmodule
module pll(
	input  clock_in,
	output clock_out,
	output locked
	);


SB_PLL40_CORE #(
		.FEEDBACK_PATH("SIMPLE"),
		.DIVR(4'b0100),
		.DIVF(7'b1000110),
		.DIVQ(3'b110),
		.FILTER_RANGE(3'b010)
	) uut (
		.LOCK(locked),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.REFERENCECLK(clock_in),
		.PLLOUTCORE(clock_out)





		);

endmodule