data/full_repos/permissive/184721104/test/test_syncgen.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_syncgen.v:29: Unsupported: Ignoring delay on this delayed statement.\n    CLK =0; #(STEP/2);\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_syncgen.v:30: Unsupported: Ignoring delay on this delayed statement.\n    CLK =1; #(STEP/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_syncgen.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP*100) RST=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_syncgen.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP*100) RST=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/184721104/test/test_syncgen.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP*CLKNUM);\n    ^\n%Error: data/full_repos/permissive/184721104/test/test_syncgen.v:16: Cannot find file containing module: \'syncgen\'\nsyncgen syncgen(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/184721104/test,data/full_repos/permissive/184721104/syncgen\n             data/full_repos/permissive/184721104/test,data/full_repos/permissive/184721104/syncgen.v\n             data/full_repos/permissive/184721104/test,data/full_repos/permissive/184721104/syncgen.sv\n             syncgen\n             syncgen.v\n             syncgen.sv\n             obj_dir/syncgen\n             obj_dir/syncgen.v\n             obj_dir/syncgen.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module syncgen_test;

localparam STEP = 8;
localparam CLKNUM = (112*507+12000)*5;

reg CLK;
reg RST;
wire PCK;
wire HS;
wire VS;

wire [9:0]HCNT;
wire [9:0]VCNT;
wire ENABLE_MEM;

syncgen syncgen(
    .CLK(CLK),
    .RST(RST),
    .PCK(PCK),
    .HS(HS),
    .VS(VS),
    .HCNT(HCNT),
    .VCNT(VCNT),
    .ENABLE_MEM(ENABLE_MEM)
);


always begin
    CLK =0; #(STEP/2);
    CLK =1; #(STEP/2);
end

initial begin
    RST = 0;
    #(STEP*100) RST=1;
    #(STEP*100) RST=0;
    #(STEP*CLKNUM);
    $stop;
end

endmodule
module syncgen_test;


localparam STEP = 8;
localparam CLKNUM = (112*507+12000)*5;

reg CLK;
reg RST;
wire PCK;
wire HS;
wire VS;

wire [9:0]HCNT;
wire [9:0]VCNT;
wire ENABLE_MEM;

syncgen syncgen(
    .CLK(CLK),
    .RST(RST),
    .PCK(PCK),
    .HS(HS),
    .VS(VS),
    .HCNT(HCNT),
    .VCNT(VCNT),
    .ENABLE_MEM(ENABLE_MEM)
);


always begin
    CLK =0; #(STEP/2);
    CLK =1; #(STEP/2);
end

initial begin
    RST = 0;
    #(STEP*100) RST=1;
    #(STEP*100) RST=0;
    #(STEP*CLKNUM);
    $stop;
end

endmodule