data/full_repos/permissive/105681119/src/register_file.v
1: b'%Error: data/full_repos/permissive/105681119/src/register_file.v:45: Cannot find include file: definition.v\n`include "definition.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v\n             data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.v\n             data/full_repos/permissive/105681119/src,data/full_repos/permissive/105681119/definition.v.sv\n             definition.v\n             definition.v.v\n             definition.v.sv\n             obj_dir/definition.v\n             obj_dir/definition.v.v\n             obj_dir/definition.v.sv\n%Error: data/full_repos/permissive/105681119/src/register_file.v:50: Define or directive not defined: \'`REG_ADDR_INDEX_LIMIT\'\n input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;\n        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:50: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;\n                             ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:51: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n input [`DATA_INDEX_LIMIT:0] DATA_W;\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:51: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n input [`DATA_INDEX_LIMIT:0] DATA_W;\n                         ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:55: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n output reg [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;\n             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:55: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n output reg [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;\n                              ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:58: Define or directive not defined: \'`DATA_INDEX_LIMIT\'\n reg [`DATA_INDEX_LIMIT:0] reg32x32 [0:`REG_INDEX_LIMIT];\n      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:58: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n reg [`DATA_INDEX_LIMIT:0] reg32x32 [0:`REG_INDEX_LIMIT];\n                       ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:58: Define or directive not defined: \'`REG_INDEX_LIMIT\'\n reg [`DATA_INDEX_LIMIT:0] reg32x32 [0:`REG_INDEX_LIMIT];\n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:64: Define or directive not defined: \'`NUM_OF_REG\'\n   for (i = 0; i < `NUM_OF_REG; i = i + 1) begin\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   for (i = 0; i < `NUM_OF_REG; i = i + 1) begin\n                              ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:64: syntax error, unexpected \')\', expecting \';\'\n   for (i = 0; i < `NUM_OF_REG; i = i + 1) begin\n                                         ^\n%Error: data/full_repos/permissive/105681119/src/register_file.v:68: syntax error, unexpected else\n  else begin \n  ^~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:80: Define or directive not defined: \'`DATA_WIDTH\'\n    DATA_R1 = { `DATA_WIDTH{1\'bx} };\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105681119/src/register_file.v:81: Define or directive not defined: \'`DATA_WIDTH\'\n    DATA_R2 = { `DATA_WIDTH{1\'bx} };\n                ^~~~~~~~~~~\n%Error: Cannot continue\n'
module REGISTER_FILE_32x32(ADDR_R1, ADDR_R2, ADDR_W, DATA_W, READ, WRITE, 
						   CLK, RST, DATA_R1, DATA_R2);

	input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
	input [`DATA_INDEX_LIMIT:0] DATA_W;
	input READ, WRITE, CLK, RST;


	output reg [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;


	reg [`DATA_INDEX_LIMIT:0] reg32x32 [0:`REG_INDEX_LIMIT];
	integer i;

	always @ (negedge RST or posedge CLK) begin

		if (RST === 1'b0) begin
			for (i = 0; i < `NUM_OF_REG; i = i + 1) begin
				reg32x32[i] = i;
			end
		end
		else begin 

			if ((READ === 1'b0) && (WRITE === 1'b1)) begin
				reg32x32[ADDR_W] = DATA_W;
			end

			else if ((READ === 1'b1) && (WRITE === 1'b0)) begin
				DATA_R1 = reg32x32[ADDR_R1];
				DATA_R2 = reg32x32[ADDR_R2];
			end

			else begin 
				DATA_R1 = { `DATA_WIDTH{1'bx} };
				DATA_R2 = { `DATA_WIDTH{1'bx} };
			end
		end
	end
endmodule
module REGISTER_FILE_32x32(ADDR_R1, ADDR_R2, ADDR_W, DATA_W, READ, WRITE, 
						   CLK, RST, DATA_R1, DATA_R2);


	input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
	input [`DATA_INDEX_LIMIT:0] DATA_W;
	input READ, WRITE, CLK, RST;


	output reg [`DATA_INDEX_LIMIT:0] DATA_R1, DATA_R2;


	reg [`DATA_INDEX_LIMIT:0] reg32x32 [0:`REG_INDEX_LIMIT];
	integer i;

	always @ (negedge RST or posedge CLK) begin

		if (RST === 1'b0) begin
			for (i = 0; i < `NUM_OF_REG; i = i + 1) begin
				reg32x32[i] = i;
			end
		end
		else begin 

			if ((READ === 1'b0) && (WRITE === 1'b1)) begin
				reg32x32[ADDR_W] = DATA_W;
			end

			else if ((READ === 1'b1) && (WRITE === 1'b0)) begin
				DATA_R1 = reg32x32[ADDR_R1];
				DATA_R2 = reg32x32[ADDR_R2];
			end

			else begin 
				DATA_R1 = { `DATA_WIDTH{1'bx} };
				DATA_R2 = { `DATA_WIDTH{1'bx} };
			end
		end
	end
endmodule