data/full_repos/permissive/143278/ivltests/pr2146824.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2146824.v:8: Operator AND expects 32 or 10 bits on the RHS, but RHS\'s CONST \'8\'hfe\' generates 8 bits.\n                                                                        : ... In instance bug\n  j = (i / 4) & 8\'hfe;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2146824.v:8: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 10 bits.\n                                                                        : ... In instance bug\n  j = (i / 4) & 8\'hfe;\n    ^\n%Error: Exiting due to 2 warning(s)\n'
module bug();

reg [9:0] i;
reg [7:0] j;

initial begin
  i = 10'h3ff;
  j = (i / 4) & 8'hfe;
  $display("'h%h", j);
end

endmodule
module bug();


reg [9:0] i;
reg [7:0] j;

initial begin
  i = 10'h3ff;
  j = (i / 4) & 8'hfe;
  $display("'h%h", j);
end

endmodule