data/full_repos/permissive/210918583/boards/tf520/tf520r3_bus_top.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/210918583/boards/tf520/tf520r3_bus_top.v:118: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'tf520r3_bus_top\'\nmodule tf520r3_bus_top(\n       ^~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'ata\'\nmodule ata (\n       ^~~\n%Error: data/full_repos/permissive/210918583/boards/tf520/tf520r3_bus_top.v:71: Cannot find file containing module: \'bus_top\'\nbus_top BUSTOP(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210918583/boards/tf520,data/full_repos/permissive/210918583/bus_top\n             data/full_repos/permissive/210918583/boards/tf520,data/full_repos/permissive/210918583/bus_top.v\n             data/full_repos/permissive/210918583/boards/tf520,data/full_repos/permissive/210918583/bus_top.sv\n             bus_top\n             bus_top.v\n             bus_top.sv\n             obj_dir/bus_top\n             obj_dir/bus_top.v\n             obj_dir/bus_top.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module ata (
           input         CLK,
           input         AS,
           input         RW,
           input [23:0] A,
           input        WAIT,

           output [1:0] IDECS,
           output        IOR,
           output        IOW,
           output   DTACK,
           output        ACCESS

       );

assign ACCESS = 1'b1;
assign DTACK = 1'b1;
assign IOR = 1'b1;
assign IOW = 1'b1;
assign IDECS = 2'b11;

endmodule
module ata (
           input         CLK,
           input         AS,
           input         RW,
           input [23:0] A,
           input        WAIT,

           output [1:0] IDECS,
           output        IOR,
           output        IOW,
           output   DTACK,
           output        ACCESS

       );


assign ACCESS = 1'b1;
assign DTACK = 1'b1;
assign IOR = 1'b1;
assign IOW = 1'b1;
assign IDECS = 2'b11;

endmodule