data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/reg_file.v
data/verilator_xmls/b0b14918-9cba-4775-91b1-c1693825f33b.xml
module reg_file (clk, f_we, fsel, fin, regfile_out);

input        clk;
input        f_we;
input  [4:0] fsel;
input  [7:0] fin;
output [7:0] regfile_out;

reg [4:0] addr;

reg[7:0] mem_regfile[31:0];

assign regfile_out = mem_regfile[addr];

always @(posedge clk)
begin
if(f_we )
  addr <= fsel;
else
  mem_regfile[addr] <= fin;
end
endmodule
module reg_file (clk, f_we, fsel, fin, regfile_out);


input        clk;
input        f_we;
input  [4:0] fsel;
input  [7:0] fin;
output [7:0] regfile_out;

reg [4:0] addr;

reg[7:0] mem_regfile[31:0];

assign regfile_out = mem_regfile[addr];

always @(posedge clk)
begin
if(f_we )
  addr <= fsel;
else
  mem_regfile[addr] <= fin;
end
endmodule