data/full_repos/permissive/110056451/plotfour_top.v
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1: b'%Warning-IMPLICIT: data/full_repos/permissive/110056451/plotfour_top.v:531: Signal definition not found, creating implicitly: \'enable_1\'\n                                                                          : ... Suggested alternative: \'enable\'\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n        ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:347: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n            x1 <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:348: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n            y1 <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:353: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh64\' generates 32 or 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    c1 <= 100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:359: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:360: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:363: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:364: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:367: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:368: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:371: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:372: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:375: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:376: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:379: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:380: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:383: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:384: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:387: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:388: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h16\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:391: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:392: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:395: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:396: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:399: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:400: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:403: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:404: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:407: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:408: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:411: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:412: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:415: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:416: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2a\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:419: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:420: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:423: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:424: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:427: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:428: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:431: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:432: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:435: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:436: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:439: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:440: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:443: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:444: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:447: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:448: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:451: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:452: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:455: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:456: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:459: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:460: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:463: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:464: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:467: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:471: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:472: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h51\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1010001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:475: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:476: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:479: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:480: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:483: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:484: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:487: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:491: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:492: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:495: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:496: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:499: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:500: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h65\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:503: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:504: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:507: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:508: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:511: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:512: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:515: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:516: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:519: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:520: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:523: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:524: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:531: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                       : ... In instance plotfour_top.d0\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:534: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'controlA\' generates 4 bits.\n                                                                       : ... In instance plotfour_top.d0\n assign X = x1 + controlA;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:535: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'controlC\' generates 4 bits.\n                                                                       : ... In instance plotfour_top.d0\n assign Y = y1 + controlC;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:170: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   blue   <= 1\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:171: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   red    <= 1\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:286: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:288: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:292: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:294: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b0; p_one_score <= 1\'b0; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:310: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:312: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:314: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:316: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:318: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:320: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b0; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:23: Little bit endian vector: MSB < LSB of bit range: 0:3\n input  [0:3]  KEY;      \n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:31: Little bit endian vector: MSB < LSB of bit range: 0:4\n output  [0:4]  LEDR;      \n         ^\n%Error: data/full_repos/permissive/110056451/plotfour_top.v:59: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter\n             data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.v\n             data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.sv\n             vga_adapter\n             vga_adapter.v\n             vga_adapter.sv\n             obj_dir/vga_adapter\n             obj_dir/vga_adapter.v\n             obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'X\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'x\' generates 8 bits.\n                                                                      : ... In instance plotfour_top\n    datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'Y\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 7 bits.\n                                                                      : ... In instance plotfour_top\n    datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:146: Output port connection \'p_one_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n                                                                       : ... In instance plotfour_top\n  .p_one_score(p_one_score),\n   ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:147: Output port connection \'p_two_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_two_score\' generates 1 bits.\n                                                                       : ... In instance plotfour_top\n  .p_two_score(p_two_score)\n   ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:151: Input port connection \'hex_digit\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n                                                                       : ... In instance plotfour_top\n  .hex_digit(p_one_score),\n   ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 112 warning(s)\n'
module fsm_controller (resetn, p_one, p_two, start, square, p_one_win, p_two_win, blue, red, turn, p_one_score, p_two_score);
	
	input [5:0] square;
	input resetn, p_one, p_two, start;
	output reg [3:0] p_one_score, p_two_score;
	output reg p_one_win, p_two_win;
	output reg turn;
	output reg [41:0] blue, red;
	
	always @(*)
	begin
		if(resetn==1'b1)
		begin
			blue 		<= 1'b0;
			red  		<= 1'b0;


			turn        <= 1'b0;


		end
		else if (start==1'b0)
		begin


			turn      <= 1'b1;
		end
		else if (start==1'b1 && p_one_win==1'b0 && p_two_win==1'b0)
		begin
			if (p_one==1'b1)
			begin
				case(square)
					6'b000000: if(turn == 1 && blue[0]==0  && red[0]==0) 	 begin blue[0]<=1;  turn<=0; end
					6'b000001: if(turn == 1 && blue[1]==0  && red[1]==0) 	 begin blue[1]<=1;  turn<=0; end
					6'b000010: if(turn == 1 && blue[2]==0  && red[2]==0) 	 begin blue[2]<=1;  turn<=0; end
					6'b000011: if(turn == 1 && blue[3]==0  && red[3]==0) 	 begin blue[3]<=1;  turn<=0; end
					6'b000100: if(turn == 1 && blue[4]==0  && red[4]==0) 	 begin blue[4]<=1;  turn<=0; end
					6'b000101: if(turn == 1 && blue[5]==0  && red[5]==0) 	 begin blue[5]<=1;  turn<=0; end
					6'b000110: if(turn == 1 && blue[6]==0  && red[6]==0) 	 begin blue[6]<=1;  turn<=0; end
					6'b000111: if(turn == 1 && blue[7]==0  && red[7]==0) 	 begin blue[7]<=1;  turn<=0; end
					6'b001000: if(turn == 1 && blue[8]==0  && red[8]==0) 	 begin blue[8]<=1;  turn<=0; end
					6'b001001: if(turn == 1 && blue[9]==0  && red[9]==0) 	 begin blue[9]<=1;  turn<=0; end
					6'b001010: if(turn == 1 && blue[10]==0 && red[10]==0) 	 begin blue[10]<=1; turn<=0; end
					6'b001011: if(turn == 1 && blue[11]==0 && red[11]==0) 	 begin blue[11]<=1; turn<=0; end
					6'b001100: if(turn == 1 && blue[12]==0 && red[12]==0) 	 begin blue[12]<=1; turn<=0; end
					6'b001101: if(turn == 1 && blue[13]==0 && red[13]==0) 	 begin blue[13]<=1; turn<=0; end
					6'b001110: if(turn == 1 && blue[14]==0 && red[14]==0) 	 begin blue[14]<=1; turn<=0; end
					6'b001111: if(turn == 1 && blue[15]==0 && red[15]==0) 	 begin blue[15]<=1; turn<=0; end
					6'b010000: if(turn == 1 && blue[16]==0 && red[16]==0) 	 begin blue[16]<=1; turn<=0; end
					6'b010001: if(turn == 1 && blue[17]==0 && red[17]==0) 	 begin blue[17]<=1; turn<=0; end
					6'b010010: if(turn == 1 && blue[18]==0 && red[18]==0) 	 begin blue[18]<=1; turn<=0; end
					6'b010011: if(turn == 1 && blue[19]==0 && red[19]==0) 	 begin blue[19]<=1; turn<=0; end
					6'b010100: if(turn == 1 && blue[20]==0 && red[20]==0) 	 begin blue[20]<=1; turn<=0; end
					6'b010101: if(turn == 1 && blue[21]==0 && red[21]==0) 	 begin blue[21]<=1; turn<=0; end
					6'b010110: if(turn == 1 && blue[22]==0 && red[22]==0) 	 begin blue[22]<=1; turn<=0; end
					6'b010111: if(turn == 1 && blue[23]==0 && red[23]==0) 	 begin blue[23]<=1; turn<=0; end
					6'b011000: if(turn == 1 && blue[24]==0 && red[24]==0) 	 begin blue[24]<=1; turn<=0; end
					6'b011001: if(turn == 1 && blue[25]==0 && red[25]==0) 	 begin blue[25]<=1; turn<=0; end
					6'b011010: if(turn == 1 && blue[26]==0 && red[26]==0) 	 begin blue[26]<=1; turn<=0; end
					6'b011011: if(turn == 1 && blue[27]==0 && red[27]==0) 	 begin blue[27]<=1; turn<=0; end
					6'b011100: if(turn == 1 && blue[28]==0 && red[28]==0) 	 begin blue[28]<=1; turn<=0; end
					6'b011101: if(turn == 1 && blue[29]==0 && red[29]==0) 	 begin blue[29]<=1; turn<=0; end
					6'b011110: if(turn == 1 && blue[30]==0 && red[30]==0) 	 begin blue[30]<=1; turn<=0; end
					6'b011111: if(turn == 1 && blue[31]==0 && red[31]==0) 	 begin blue[31]<=1; turn<=0; end
					6'b100000: if(turn == 1 && blue[32]==0 && red[32]==0) 	 begin blue[32]<=1; turn<=0; end
					6'b100001: if(turn == 1 && blue[33]==0 && red[33]==0) 	 begin blue[33]<=1; turn<=0; end
					6'b100010: if(turn == 1 && blue[34]==0 && red[34]==0) 	 begin blue[34]<=1; turn<=0; end
					6'b100011: if(turn == 1 && blue[35]==0 && red[35]==0) 	 begin blue[35]<=1; turn<=0; end
					6'b100100: if(turn == 1 && blue[36]==0 && red[36]==0) 	 begin blue[36]<=1; turn<=0; end
					6'b100101: if(turn == 1 && blue[37]==0 && red[37]==0) 	 begin blue[37]<=1; turn<=0; end
					6'b100110: if(turn == 1 && blue[38]==0 && red[38]==0) 	 begin blue[38]<=1; turn<=0; end
					6'b100111: if(turn == 1 && blue[39]==0 && red[39]==0) 	 begin blue[39]<=1; turn<=0; end
					6'b101000: if(turn == 1 && blue[40]==0 && red[40]==0) 	 begin blue[40]<=1; turn<=0; end
					6'b101001: if(turn == 1 && blue[41]==0 && red[41]==0) 	 begin blue[41]<=1; turn<=0; end
				endcase
			end
			else
			begin
				case(square)
					6'b000000: if(turn == 1 && blue[0]==0  && red[0]==0) 	 begin red[0]<=1;  turn<=0; end
					6'b000001: if(turn == 1 && blue[1]==0  && red[1]==0) 	 begin red[1]<=1;  turn<=0; end
					6'b000010: if(turn == 1 && blue[2]==0  && red[2]==0) 	 begin red[2]<=1;  turn<=0; end
					6'b000011: if(turn == 1 && blue[3]==0  && red[3]==0) 	 begin red[3]<=1;  turn<=0; end
					6'b000100: if(turn == 1 && blue[4]==0  && red[4]==0) 	 begin red[4]<=1;  turn<=0; end
					6'b000101: if(turn == 1 && blue[5]==0  && red[5]==0) 	 begin red[5]<=1;  turn<=0; end
					6'b000110: if(turn == 1 && blue[6]==0  && red[6]==0) 	 begin red[6]<=1;  turn<=0; end
					6'b000111: if(turn == 1 && blue[7]==0  && red[7]==0) 	 begin red[7]<=1;  turn<=0; end
					6'b001000: if(turn == 1 && blue[8]==0  && red[8]==0) 	 begin red[8]<=1;  turn<=0; end
					6'b001001: if(turn == 1 && blue[9]==0  && red[9]==0) 	 begin red[9]<=1;  turn<=0; end
					6'b001010: if(turn == 1 && blue[10]==0 && red[10]==0) 	 begin red[10]<=1; turn<=0; end
					6'b001011: if(turn == 1 && blue[11]==0 && red[11]==0) 	 begin red[11]<=1; turn<=0; end
					6'b001100: if(turn == 1 && blue[12]==0 && red[12]==0) 	 begin red[12]<=1; turn<=0; end
					6'b001101: if(turn == 1 && blue[13]==0 && red[13]==0) 	 begin red[13]<=1; turn<=0; end
					6'b001110: if(turn == 1 && blue[14]==0 && red[14]==0) 	 begin red[14]<=1; turn<=0; end
					6'b001111: if(turn == 1 && blue[15]==0 && red[15]==0) 	 begin red[15]<=1; turn<=0; end
					6'b010000: if(turn == 1 && blue[16]==0 && red[16]==0) 	 begin red[16]<=1; turn<=0; end
					6'b010001: if(turn == 1 && blue[17]==0 && red[17]==0) 	 begin red[17]<=1; turn<=0; end
					6'b010010: if(turn == 1 && blue[18]==0 && red[18]==0) 	 begin red[18]<=1; turn<=0; end
					6'b010011: if(turn == 1 && blue[19]==0 && red[19]==0) 	 begin red[19]<=1; turn<=0; end
					6'b010100: if(turn == 1 && blue[20]==0 && red[20]==0) 	 begin red[20]<=1; turn<=0; end
					6'b010101: if(turn == 1 && blue[21]==0 && red[21]==0) 	 begin red[21]<=1; turn<=0; end
					6'b010110: if(turn == 1 && blue[22]==0 && red[22]==0) 	 begin red[22]<=1; turn<=0; end
					6'b010111: if(turn == 1 && blue[23]==0 && red[23]==0) 	 begin red[23]<=1; turn<=0; end
					6'b011000: if(turn == 1 && blue[24]==0 && red[24]==0) 	 begin red[24]<=1; turn<=0; end
					6'b011001: if(turn == 1 && blue[25]==0 && red[25]==0) 	 begin red[25]<=1; turn<=0; end
					6'b011010: if(turn == 1 && blue[26]==0 && red[26]==0) 	 begin red[26]<=1; turn<=0; end
					6'b011011: if(turn == 1 && blue[27]==0 && red[27]==0) 	 begin red[27]<=1; turn<=0; end
					6'b011100: if(turn == 1 && blue[28]==0 && red[28]==0) 	 begin red[28]<=1; turn<=0; end
					6'b011101: if(turn == 1 && blue[29]==0 && red[29]==0) 	 begin red[29]<=1; turn<=0; end
					6'b011110: if(turn == 1 && blue[30]==0 && red[30]==0) 	 begin red[30]<=1; turn<=0; end
					6'b011111: if(turn == 1 && blue[31]==0 && red[31]==0) 	 begin red[31]<=1; turn<=0; end
					6'b100000: if(turn == 1 && blue[32]==0 && red[32]==0) 	 begin red[32]<=1; turn<=0; end
					6'b100001: if(turn == 1 && blue[33]==0 && red[33]==0) 	 begin red[33]<=1; turn<=0; end
					6'b100010: if(turn == 1 && blue[34]==0 && red[34]==0) 	 begin red[34]<=1; turn<=0; end
					6'b100011: if(turn == 1 && blue[35]==0 && red[35]==0) 	 begin red[35]<=1; turn<=0; end
					6'b100100: if(turn == 1 && blue[36]==0 && red[36]==0) 	 begin red[36]<=1; turn<=0; end
					6'b100101: if(turn == 1 && blue[37]==0 && red[37]==0) 	 begin red[37]<=1; turn<=0; end
					6'b100110: if(turn == 1 && blue[38]==0 && red[38]==0) 	 begin red[38]<=1; turn<=0; end
					6'b100111: if(turn == 1 && blue[39]==0 && red[39]==0) 	 begin red[39]<=1; turn<=0; end
					6'b101000: if(turn == 1 && blue[40]==0 && red[40]==0) 	 begin red[40]<=1; turn<=0; end
					6'b101001: if(turn == 1 && blue[41]==0 && red[41]==0) 	 begin red[41]<=1; turn<=0; end
				endcase
			end
		end
	end
	
	always @(*)
		begin
			if(blue[0] == 1 && blue[7] == 1 && blue[14] == 1 && blue[21] == 1)
			begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
			else if (blue[7] == 1 && blue[14] == 1 && blue[21] == 1 && blue[28] == 1)
			begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
			else if (blue[14] == 1 && blue[21] == 1 && blue[28] == 1 && blue[35] == 1)
			begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
			else if (blue[0] == 1 && blue[1] == 1 && blue[2] == 1 && blue[3] == 1)
			begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
			else if (blue[0] == 1 && blue[8] == 1 && blue[16] == 1 && blue[24] == 1)
			begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
			else
			begin p_one_win <= 1'b0; p_one_score <= 1'b0; end
		end
	







		
	always @(*)
		begin
			if(red[0] == 1 && red[7] == 1 && red[14] == 1 && red[21] == 1)
			begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
			else if (red[7] == 1 && red[14] == 1 && red[21] == 1 && red[28] == 1)
			begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
			else if (red[14] == 1 && red[21] == 1 && red[28] == 1 && red[35] == 1)
			begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
			else if (red[0] == 1 && red[1] == 1 && red[2] == 1 && red[3] == 1)
			begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
			else if (red[0] == 1 && red[8] == 1 && red[16] == 1 && red[24] == 1)
			begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
			else
			begin p_two_win <= 1'b0; p_two_score <= 1'b1; end
		end
	








	
endmodule
module fsm_controller (resetn, p_one, p_two, start, square, p_one_win, p_two_win, blue, red, turn, p_one_score, p_two_score);

	
	input [5:0] square;
	input resetn, p_one, p_two, start;
	output reg [3:0] p_one_score, p_two_score;
	output reg p_one_win, p_two_win;
	output reg turn;
	output reg [41:0] blue, red;
	
	always @(*)
	begin
		if(resetn==1'b1)
		begin
			blue 		<= 1'b0;
			red  		<= 1'b0;


			turn        <= 1'b0;


		end
		else if (start==1'b0)
		begin


			turn      <= 1'b1;
		end
		else if (start==1'b1 && p_one_win==1'b0 && p_two_win==1'b0)
		begin
			if (p_one==1'b1)
			begin
				case(square)
					6'b000000: if(turn == 1 && blue[0]==0  && red[0]==0) 	 begin blue[0]<=1;  turn<=0; end
					6'b000001: if(turn == 1 && blue[1]==0  && red[1]==0) 	 begin blue[1]<=1;  turn<=0; end
					6'b000010: if(turn == 1 && blue[2]==0  && red[2]==0) 	 begin blue[2]<=1;  turn<=0; end
					6'b000011: if(turn == 1 && blue[3]==0  && red[3]==0) 	 begin blue[3]<=1;  turn<=0; end
					6'b000100: if(turn == 1 && blue[4]==0  && red[4]==0) 	 begin blue[4]<=1;  turn<=0; end
					6'b000101: if(turn == 1 && blue[5]==0  && red[5]==0) 	 begin blue[5]<=1;  turn<=0; end
					6'b000110: if(turn == 1 && blue[6]==0  && red[6]==0) 	 begin blue[6]<=1;  turn<=0; end
					6'b000111: if(turn == 1 && blue[7]==0  && red[7]==0) 	 begin blue[7]<=1;  turn<=0; end
					6'b001000: if(turn == 1 && blue[8]==0  && red[8]==0) 	 begin blue[8]<=1;  turn<=0; end
					6'b001001: if(turn == 1 && blue[9]==0  && red[9]==0) 	 begin blue[9]<=1;  turn<=0; end
					6'b001010: if(turn == 1 && blue[10]==0 && red[10]==0) 	 begin blue[10]<=1; turn<=0; end
					6'b001011: if(turn == 1 && blue[11]==0 && red[11]==0) 	 begin blue[11]<=1; turn<=0; end
					6'b001100: if(turn == 1 && blue[12]==0 && red[12]==0) 	 begin blue[12]<=1; turn<=0; end
					6'b001101: if(turn == 1 && blue[13]==0 && red[13]==0) 	 begin blue[13]<=1; turn<=0; end
					6'b001110: if(turn == 1 && blue[14]==0 && red[14]==0) 	 begin blue[14]<=1; turn<=0; end
					6'b001111: if(turn == 1 && blue[15]==0 && red[15]==0) 	 begin blue[15]<=1; turn<=0; end
					6'b010000: if(turn == 1 && blue[16]==0 && red[16]==0) 	 begin blue[16]<=1; turn<=0; end
					6'b010001: if(turn == 1 && blue[17]==0 && red[17]==0) 	 begin blue[17]<=1; turn<=0; end
					6'b010010: if(turn == 1 && blue[18]==0 && red[18]==0) 	 begin blue[18]<=1; turn<=0; end
					6'b010011: if(turn == 1 && blue[19]==0 && red[19]==0) 	 begin blue[19]<=1; turn<=0; end
					6'b010100: if(turn == 1 && blue[20]==0 && red[20]==0) 	 begin blue[20]<=1; turn<=0; end
					6'b010101: if(turn == 1 && blue[21]==0 && red[21]==0) 	 begin blue[21]<=1; turn<=0; end
					6'b010110: if(turn == 1 && blue[22]==0 && red[22]==0) 	 begin blue[22]<=1; turn<=0; end
					6'b010111: if(turn == 1 && blue[23]==0 && red[23]==0) 	 begin blue[23]<=1; turn<=0; end
					6'b011000: if(turn == 1 && blue[24]==0 && red[24]==0) 	 begin blue[24]<=1; turn<=0; end
					6'b011001: if(turn == 1 && blue[25]==0 && red[25]==0) 	 begin blue[25]<=1; turn<=0; end
					6'b011010: if(turn == 1 && blue[26]==0 && red[26]==0) 	 begin blue[26]<=1; turn<=0; end
					6'b011011: if(turn == 1 && blue[27]==0 && red[27]==0) 	 begin blue[27]<=1; turn<=0; end
					6'b011100: if(turn == 1 && blue[28]==0 && red[28]==0) 	 begin blue[28]<=1; turn<=0; end
					6'b011101: if(turn == 1 && blue[29]==0 && red[29]==0) 	 begin blue[29]<=1; turn<=0; end
					6'b011110: if(turn == 1 && blue[30]==0 && red[30]==0) 	 begin blue[30]<=1; turn<=0; end
					6'b011111: if(turn == 1 && blue[31]==0 && red[31]==0) 	 begin blue[31]<=1; turn<=0; end
					6'b100000: if(turn == 1 && blue[32]==0 && red[32]==0) 	 begin blue[32]<=1; turn<=0; end
					6'b100001: if(turn == 1 && blue[33]==0 && red[33]==0) 	 begin blue[33]<=1; turn<=0; end
					6'b100010: if(turn == 1 && blue[34]==0 && red[34]==0) 	 begin blue[34]<=1; turn<=0; end
					6'b100011: if(turn == 1 && blue[35]==0 && red[35]==0) 	 begin blue[35]<=1; turn<=0; end
					6'b100100: if(turn == 1 && blue[36]==0 && red[36]==0) 	 begin blue[36]<=1; turn<=0; end
					6'b100101: if(turn == 1 && blue[37]==0 && red[37]==0) 	 begin blue[37]<=1; turn<=0; end
					6'b100110: if(turn == 1 && blue[38]==0 && red[38]==0) 	 begin blue[38]<=1; turn<=0; end
					6'b100111: if(turn == 1 && blue[39]==0 && red[39]==0) 	 begin blue[39]<=1; turn<=0; end
					6'b101000: if(turn == 1 && blue[40]==0 && red[40]==0) 	 begin blue[40]<=1; turn<=0; end
					6'b101001: if(turn == 1 && blue[41]==0 && red[41]==0) 	 begin blue[41]<=1; turn<=0; end
				endcase
			end
			else
			begin
				case(square)
					6'b000000: if(turn == 1 && blue[0]==0  && red[0]==0) 	 begin red[0]<=1;  turn<=0; end
					6'b000001: if(turn == 1 && blue[1]==0  && red[1]==0) 	 begin red[1]<=1;  turn<=0; end
					6'b000010: if(turn == 1 && blue[2]==0  && red[2]==0) 	 begin red[2]<=1;  turn<=0; end
					6'b000011: if(turn == 1 && blue[3]==0  && red[3]==0) 	 begin red[3]<=1;  turn<=0; end
					6'b000100: if(turn == 1 && blue[4]==0  && red[4]==0) 	 begin red[4]<=1;  turn<=0; end
					6'b000101: if(turn == 1 && blue[5]==0  && red[5]==0) 	 begin red[5]<=1;  turn<=0; end
					6'b000110: if(turn == 1 && blue[6]==0  && red[6]==0) 	 begin red[6]<=1;  turn<=0; end
					6'b000111: if(turn == 1 && blue[7]==0  && red[7]==0) 	 begin red[7]<=1;  turn<=0; end
					6'b001000: if(turn == 1 && blue[8]==0  && red[8]==0) 	 begin red[8]<=1;  turn<=0; end
					6'b001001: if(turn == 1 && blue[9]==0  && red[9]==0) 	 begin red[9]<=1;  turn<=0; end
					6'b001010: if(turn == 1 && blue[10]==0 && red[10]==0) 	 begin red[10]<=1; turn<=0; end
					6'b001011: if(turn == 1 && blue[11]==0 && red[11]==0) 	 begin red[11]<=1; turn<=0; end
					6'b001100: if(turn == 1 && blue[12]==0 && red[12]==0) 	 begin red[12]<=1; turn<=0; end
					6'b001101: if(turn == 1 && blue[13]==0 && red[13]==0) 	 begin red[13]<=1; turn<=0; end
					6'b001110: if(turn == 1 && blue[14]==0 && red[14]==0) 	 begin red[14]<=1; turn<=0; end
					6'b001111: if(turn == 1 && blue[15]==0 && red[15]==0) 	 begin red[15]<=1; turn<=0; end
					6'b010000: if(turn == 1 && blue[16]==0 && red[16]==0) 	 begin red[16]<=1; turn<=0; end
					6'b010001: if(turn == 1 && blue[17]==0 && red[17]==0) 	 begin red[17]<=1; turn<=0; end
					6'b010010: if(turn == 1 && blue[18]==0 && red[18]==0) 	 begin red[18]<=1; turn<=0; end
					6'b010011: if(turn == 1 && blue[19]==0 && red[19]==0) 	 begin red[19]<=1; turn<=0; end
					6'b010100: if(turn == 1 && blue[20]==0 && red[20]==0) 	 begin red[20]<=1; turn<=0; end
					6'b010101: if(turn == 1 && blue[21]==0 && red[21]==0) 	 begin red[21]<=1; turn<=0; end
					6'b010110: if(turn == 1 && blue[22]==0 && red[22]==0) 	 begin red[22]<=1; turn<=0; end
					6'b010111: if(turn == 1 && blue[23]==0 && red[23]==0) 	 begin red[23]<=1; turn<=0; end
					6'b011000: if(turn == 1 && blue[24]==0 && red[24]==0) 	 begin red[24]<=1; turn<=0; end
					6'b011001: if(turn == 1 && blue[25]==0 && red[25]==0) 	 begin red[25]<=1; turn<=0; end
					6'b011010: if(turn == 1 && blue[26]==0 && red[26]==0) 	 begin red[26]<=1; turn<=0; end
					6'b011011: if(turn == 1 && blue[27]==0 && red[27]==0) 	 begin red[27]<=1; turn<=0; end
					6'b011100: if(turn == 1 && blue[28]==0 && red[28]==0) 	 begin red[28]<=1; turn<=0; end
					6'b011101: if(turn == 1 && blue[29]==0 && red[29]==0) 	 begin red[29]<=1; turn<=0; end
					6'b011110: if(turn == 1 && blue[30]==0 && red[30]==0) 	 begin red[30]<=1; turn<=0; end
					6'b011111: if(turn == 1 && blue[31]==0 && red[31]==0) 	 begin red[31]<=1; turn<=0; end
					6'b100000: if(turn == 1 && blue[32]==0 && red[32]==0) 	 begin red[32]<=1; turn<=0; end
					6'b100001: if(turn == 1 && blue[33]==0 && red[33]==0) 	 begin red[33]<=1; turn<=0; end
					6'b100010: if(turn == 1 && blue[34]==0 && red[34]==0) 	 begin red[34]<=1; turn<=0; end
					6'b100011: if(turn == 1 && blue[35]==0 && red[35]==0) 	 begin red[35]<=1; turn<=0; end
					6'b100100: if(turn == 1 && blue[36]==0 && red[36]==0) 	 begin red[36]<=1; turn<=0; end
					6'b100101: if(turn == 1 && blue[37]==0 && red[37]==0) 	 begin red[37]<=1; turn<=0; end
					6'b100110: if(turn == 1 && blue[38]==0 && red[38]==0) 	 begin red[38]<=1; turn<=0; end
					6'b100111: if(turn == 1 && blue[39]==0 && red[39]==0) 	 begin red[39]<=1; turn<=0; end
					6'b101000: if(turn == 1 && blue[40]==0 && red[40]==0) 	 begin red[40]<=1; turn<=0; end
					6'b101001: if(turn == 1 && blue[41]==0 && red[41]==0) 	 begin red[41]<=1; turn<=0; end
				endcase
			end
		end
	end
	
	always @(*)
		begin
			if(blue[0] == 1 && blue[7] == 1 && blue[14] == 1 && blue[21] == 1)
			begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
			else if (blue[7] == 1 && blue[14] == 1 && blue[21] == 1 && blue[28] == 1)
			begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
			else if (blue[14] == 1 && blue[21] == 1 && blue[28] == 1 && blue[35] == 1)
			begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
			else if (blue[0] == 1 && blue[1] == 1 && blue[2] == 1 && blue[3] == 1)
			begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
			else if (blue[0] == 1 && blue[8] == 1 && blue[16] == 1 && blue[24] == 1)
			begin p_one_win <= 1'b1; p_one_score <= 1'b1; end
			else
			begin p_one_win <= 1'b0; p_one_score <= 1'b0; end
		end
	







		
	always @(*)
		begin
			if(red[0] == 1 && red[7] == 1 && red[14] == 1 && red[21] == 1)
			begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
			else if (red[7] == 1 && red[14] == 1 && red[21] == 1 && red[28] == 1)
			begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
			else if (red[14] == 1 && red[21] == 1 && red[28] == 1 && red[35] == 1)
			begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
			else if (red[0] == 1 && red[1] == 1 && red[2] == 1 && red[3] == 1)
			begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
			else if (red[0] == 1 && red[8] == 1 && red[16] == 1 && red[24] == 1)
			begin p_two_win <= 1'b1; p_two_score <= 1'b1; end
			else
			begin p_two_win <= 1'b0; p_two_score <= 1'b1; end
		end
	








	
endmodule