data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:44: Little bit endian vector: MSB < LSB of bit range: 1:64\nwire [1:64] IP, FP;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:45: Little bit endian vector: MSB < LSB of bit range: 1:64\n(* altera_attribute = "-name DONT_MERGE_REGISTER ON" *) wire [1:64] IP_dup;\n                                                             ^\n%Warning-LITENDIAN: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:50: Little bit endian vector: MSB < LSB of bit range: 1:32\nreg [1:32] L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:51: Little bit endian vector: MSB < LSB of bit range: 1:32\nreg [1:32] R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:52: Little bit endian vector: MSB < LSB of bit range: 1:32\n(* altera_attribute = "-name DONT_MERGE_REGISTER OFF" *) reg [1:32] R0_dup, R1_dup, R2_dup, R3_dup, R4_dup, R5_dup, R6_dup, R7_dup, R8_dup, R9_dup, R10_dup, R11_dup, R12_dup, R13_dup, R14_dup, R15_dup;\n                                                             ^\n%Warning-LITENDIAN: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:53: Little bit endian vector: MSB < LSB of bit range: 1:32\nwire [1:32] out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:54: Little bit endian vector: MSB < LSB of bit range: 1:48\nwire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:55: Little bit endian vector: MSB < LSB of bit range: 1:48\nwire [1:48] K10, K11, K12, K13, K14, K15, K16;\n     ^\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:89: Cannot find file containing module: \'key_sel\'\nkey_sel uk(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150152921/apps/des/step3/rtl,data/full_repos/permissive/150152921/key_sel\n             data/full_repos/permissive/150152921/apps/des/step3/rtl,data/full_repos/permissive/150152921/key_sel.v\n             data/full_repos/permissive/150152921/apps/des/step3/rtl,data/full_repos/permissive/150152921/key_sel.sv\n             key_sel\n             key_sel.v\n             key_sel.sv\n             obj_dir/key_sel\n             obj_dir/key_sel.v\n             obj_dir/key_sel.sv\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:112: Cannot find file containing module: \'crp\'\ncrp u0( .P(out0), .R(IP[33:64]), .K_sub(K1) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:113: Cannot find file containing module: \'crp\'\ncrp u1( .P(out1), .R(R0), .K_sub(K2) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:114: Cannot find file containing module: \'crp\'\ncrp u2( .P(out2), .R(R1), .K_sub(K3) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:115: Cannot find file containing module: \'crp\'\ncrp u3( .P(out3), .R(R2), .K_sub(K4) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:116: Cannot find file containing module: \'crp\'\ncrp u4( .P(out4), .R(R3), .K_sub(K5) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:117: Cannot find file containing module: \'crp\'\ncrp u5( .P(out5), .R(R4), .K_sub(K6) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:118: Cannot find file containing module: \'crp\'\ncrp u6( .P(out6), .R(R5), .K_sub(K7) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:119: Cannot find file containing module: \'crp\'\ncrp u7( .P(out7), .R(R6), .K_sub(K8) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:120: Cannot find file containing module: \'crp\'\ncrp u8( .P(out8), .R(R7), .K_sub(K9) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:121: Cannot find file containing module: \'crp\'\ncrp u9( .P(out9), .R(R8), .K_sub(K10) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:122: Cannot find file containing module: \'crp\'\ncrp u10( .P(out10), .R(R9), .K_sub(K11) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:123: Cannot find file containing module: \'crp\'\ncrp u11( .P(out11), .R(R10), .K_sub(K12) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:124: Cannot find file containing module: \'crp\'\ncrp u12( .P(out12), .R(R11), .K_sub(K13) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:125: Cannot find file containing module: \'crp\'\ncrp u13( .P(out13), .R(R12), .K_sub(K14) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:126: Cannot find file containing module: \'crp\'\ncrp u14( .P(out14), .R(R13), .K_sub(K15) );\n^~~\n%Error: data/full_repos/permissive/150152921/apps/des/step3/rtl/des.v:127: Cannot find file containing module: \'crp\'\ncrp u15( .P(out15), .R(R14), .K_sub(K16) );\n^~~\n%Error: Exiting due to 17 error(s), 8 warning(s)\n'
module des
(
	output	reg	[63:0]	desOut,
	input	[63:0]	desIn,
	input	[55:0]	key,
	input		decrypt,
	input		clk
);

wire	[1:64]	IP, FP;
(* altera_attribute = "-name DONT_MERGE_REGISTER ON" *) wire [1:64] IP_dup;
reg	[63:0]	desIn_r;
(* altera_attribute = "-name DONT_MERGE_REGISTER ON" *) reg	[63:0]	desIn_r_dup;
reg	[55:0]	key_r;
reg		decrypt_r;
reg	[1:32]	L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15;
reg	[1:32]	R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15;
(* altera_attribute = "-name DONT_MERGE_REGISTER OFF" *) reg	[1:32]	R0_dup, R1_dup, R2_dup, R3_dup, R4_dup, R5_dup, R6_dup, R7_dup, R8_dup, R9_dup, R10_dup, R11_dup, R12_dup, R13_dup, R14_dup, R15_dup;
wire	[1:32]	out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15;
wire	[1:48]	K1, K2, K3, K4, K5, K6, K7, K8, K9;
wire	[1:48]	K10, K11, K12, K13, K14, K15, K16;




always @(posedge clk)
	key_r <= key;


always @(posedge clk) begin
	desIn_r <= desIn;
	desIn_r_dup <= desIn;
end


always @(posedge clk)
	decrypt_r <= decrypt;




assign FP = { (out15 ^ L14), R14};



key_sel uk(
	.clk(		clk		),
	.K(		key_r		),
	.decrypt(	decrypt_r	),
	.K1(		K1		),
	.K2(		K2		),
	.K3(		K3		),
	.K4(		K4		),
	.K5(		K5		),
	.K6(		K6		),
	.K7(		K7		),
	.K8(		K8		),
	.K9(		K9		),
	.K10(		K10		),
	.K11(		K11		),
	.K12(		K12		),
	.K13(		K13		),
	.K14(		K14		),
	.K15(		K15		),
	.K16(		K16		)
	);


crp u0( .P(out0), .R(IP[33:64]), .K_sub(K1) );
crp u1( .P(out1), .R(R0), .K_sub(K2) );
crp u2( .P(out2), .R(R1), .K_sub(K3) );
crp u3( .P(out3), .R(R2), .K_sub(K4) );
crp u4( .P(out4), .R(R3), .K_sub(K5) );
crp u5( .P(out5), .R(R4), .K_sub(K6) );
crp u6( .P(out6), .R(R5), .K_sub(K7) );
crp u7( .P(out7), .R(R6), .K_sub(K8) );
crp u8( .P(out8), .R(R7), .K_sub(K9) );
crp u9( .P(out9), .R(R8), .K_sub(K10) );
crp u10( .P(out10), .R(R9), .K_sub(K11) );
crp u11( .P(out11), .R(R10), .K_sub(K12) );
crp u12( .P(out12), .R(R11), .K_sub(K13) );
crp u13( .P(out13), .R(R12), .K_sub(K14) );
crp u14( .P(out14), .R(R13), .K_sub(K15) );
crp u15( .P(out15), .R(R14), .K_sub(K16) );


always @(posedge clk)
        L0 <= IP_dup[33:64];


always @(posedge clk) begin
        R0 <= IP_dup[01:32] ^ out0;
        R0_dup <= IP_dup[01:32] ^ out0;
end


always @(posedge clk)
        L1 <= R0_dup;


always @(posedge clk) begin
        R1 <= L0 ^ out1;
        R1_dup <= L0 ^ out1;
end


always @(posedge clk)
        L2 <= R1_dup;


always @(posedge clk) begin
        R2 <= L1 ^ out2;
        R2_dup <= L1 ^ out2;
end

always @(posedge clk)
        L3 <= R2_dup;

always @(posedge clk) begin
        R3 <= L2 ^ out3;
        R3_dup <= L2 ^ out3;
end

always @(posedge clk)
        L4 <= R3_dup;

always @(posedge clk) begin
        R4 <= L3 ^ out4;
        R4_dup <= L3 ^ out4;
end

always @(posedge clk)
        L5 <= R4_dup;

always @(posedge clk) begin
        R5 <= L4 ^ out5;
				R5_dup <= L4 ^ out5;
end

always @(posedge clk)
        L6 <= R5_dup;

always @(posedge clk) begin
        R6 <= L5 ^ out6;
        R6_dup <= L5 ^ out6;
end

always @(posedge clk)
        L7 <= R6_dup;

always @(posedge clk) begin
        R7 <= L6 ^ out7;
        R7_dup <= L6 ^ out7;
end

always @(posedge clk)
        L8 <= R7_dup;

always @(posedge clk) begin
        R8 <= L7 ^ out8;
        R8_dup <= L7 ^ out8;
end

always @(posedge clk)
        L9 <= R8_dup;

always @(posedge clk) begin
        R9 <= L8 ^ out9;
        R9_dup <= L8 ^ out9;
end

always @(posedge clk)
        L10 <= R9_dup;

always @(posedge clk)
begin
        R10 <= L9 ^ out10;
				R10_dup <= L9 ^ out10;
end

always @(posedge clk)
        L11 <= R10_dup;

always @(posedge clk) begin
        R11 <= L10 ^ out11;
        R11_dup <= L10 ^ out11;
end

always @(posedge clk)
        L12 <= R11_dup;

always @(posedge clk) begin
        R12 <= L11 ^ out12;
        R12_dup <= L11 ^ out12;
end

always @(posedge clk)
        L13 <= R12_dup;

always @(posedge clk) begin
        R13 <= L12 ^ out13;
        R13_dup <= L12 ^ out13;
end

always @(posedge clk)
        L14 <= R13_dup;

always @(posedge clk) begin
        R14 <= L13 ^ out14;
        R14_dup <= L13 ^ out14;
end


always @(posedge clk)
        L15 <= R14_dup;


always @(posedge clk)
        R15 <= L14 ^ out15;


assign IP[1:64] = {	desIn_r[06], desIn_r[14], desIn_r[22], desIn_r[30], desIn_r[38], desIn_r[46],
			desIn_r[54], desIn_r[62], desIn_r[04], desIn_r[12], desIn_r[20], desIn_r[28],
			desIn_r[36], desIn_r[44], desIn_r[52], desIn_r[60], desIn_r[02], desIn_r[10],
			desIn_r[18], desIn_r[26], desIn_r[34], desIn_r[42], desIn_r[50], desIn_r[58],
			desIn_r[00], desIn_r[08], desIn_r[16], desIn_r[24], desIn_r[32], desIn_r[40],
			desIn_r[48], desIn_r[56], desIn_r[07], desIn_r[15], desIn_r[23], desIn_r[31],
			desIn_r[39], desIn_r[47], desIn_r[55], desIn_r[63], desIn_r[05], desIn_r[13],
			desIn_r[21], desIn_r[29], desIn_r[37], desIn_r[45], desIn_r[53], desIn_r[61],
			desIn_r[03], desIn_r[11], desIn_r[19], desIn_r[27], desIn_r[35], desIn_r[43],
			desIn_r[51], desIn_r[59], desIn_r[01], desIn_r[09], desIn_r[17], desIn_r[25],
			desIn_r[33], desIn_r[41], desIn_r[49], desIn_r[57] };

assign IP_dup[1:64] = {	desIn_r_dup[06], desIn_r_dup[14], desIn_r_dup[22], desIn_r_dup[30], desIn_r_dup[38], desIn_r_dup[46],
			desIn_r_dup[54], desIn_r_dup[62], desIn_r_dup[04], desIn_r_dup[12], desIn_r_dup[20], desIn_r_dup[28],
			desIn_r_dup[36], desIn_r_dup[44], desIn_r_dup[52], desIn_r_dup[60], desIn_r_dup[02], desIn_r_dup[10],
			desIn_r_dup[18], desIn_r_dup[26], desIn_r_dup[34], desIn_r_dup[42], desIn_r_dup[50], desIn_r_dup[58],
			desIn_r_dup[00], desIn_r_dup[08], desIn_r_dup[16], desIn_r_dup[24], desIn_r_dup[32], desIn_r_dup[40],
			desIn_r_dup[48], desIn_r_dup[56], desIn_r_dup[07], desIn_r_dup[15], desIn_r_dup[23], desIn_r_dup[31],
			desIn_r_dup[39], desIn_r_dup[47], desIn_r_dup[55], desIn_r_dup[63], desIn_r_dup[05], desIn_r_dup[13],
			desIn_r_dup[21], desIn_r_dup[29], desIn_r_dup[37], desIn_r_dup[45], desIn_r_dup[53], desIn_r_dup[61],
			desIn_r_dup[03], desIn_r_dup[11], desIn_r_dup[19], desIn_r_dup[27], desIn_r_dup[35], desIn_r_dup[43],
			desIn_r_dup[51], desIn_r_dup[59], desIn_r_dup[01], desIn_r_dup[09], desIn_r_dup[17], desIn_r_dup[25],
			desIn_r_dup[33], desIn_r_dup[41], desIn_r_dup[49], desIn_r_dup[57] };


always @(posedge clk)
	desOut <= {	FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
			FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
			FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
			FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
			FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
			FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
			FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
			FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };


endmodule
module des
(
	output	reg	[63:0]	desOut,
	input	[63:0]	desIn,
	input	[55:0]	key,
	input		decrypt,
	input		clk
);


wire	[1:64]	IP, FP;
(* altera_attribute = "-name DONT_MERGE_REGISTER ON" *) wire [1:64] IP_dup;
reg	[63:0]	desIn_r;
(* altera_attribute = "-name DONT_MERGE_REGISTER ON" *) reg	[63:0]	desIn_r_dup;
reg	[55:0]	key_r;
reg		decrypt_r;
reg	[1:32]	L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15;
reg	[1:32]	R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15;
(* altera_attribute = "-name DONT_MERGE_REGISTER OFF" *) reg	[1:32]	R0_dup, R1_dup, R2_dup, R3_dup, R4_dup, R5_dup, R6_dup, R7_dup, R8_dup, R9_dup, R10_dup, R11_dup, R12_dup, R13_dup, R14_dup, R15_dup;
wire	[1:32]	out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15;
wire	[1:48]	K1, K2, K3, K4, K5, K6, K7, K8, K9;
wire	[1:48]	K10, K11, K12, K13, K14, K15, K16;




always @(posedge clk)
	key_r <= key;


always @(posedge clk) begin
	desIn_r <= desIn;
	desIn_r_dup <= desIn;
end


always @(posedge clk)
	decrypt_r <= decrypt;




assign FP = { (out15 ^ L14), R14};



key_sel uk(
	.clk(		clk		),
	.K(		key_r		),
	.decrypt(	decrypt_r	),
	.K1(		K1		),
	.K2(		K2		),
	.K3(		K3		),
	.K4(		K4		),
	.K5(		K5		),
	.K6(		K6		),
	.K7(		K7		),
	.K8(		K8		),
	.K9(		K9		),
	.K10(		K10		),
	.K11(		K11		),
	.K12(		K12		),
	.K13(		K13		),
	.K14(		K14		),
	.K15(		K15		),
	.K16(		K16		)
	);


crp u0( .P(out0), .R(IP[33:64]), .K_sub(K1) );
crp u1( .P(out1), .R(R0), .K_sub(K2) );
crp u2( .P(out2), .R(R1), .K_sub(K3) );
crp u3( .P(out3), .R(R2), .K_sub(K4) );
crp u4( .P(out4), .R(R3), .K_sub(K5) );
crp u5( .P(out5), .R(R4), .K_sub(K6) );
crp u6( .P(out6), .R(R5), .K_sub(K7) );
crp u7( .P(out7), .R(R6), .K_sub(K8) );
crp u8( .P(out8), .R(R7), .K_sub(K9) );
crp u9( .P(out9), .R(R8), .K_sub(K10) );
crp u10( .P(out10), .R(R9), .K_sub(K11) );
crp u11( .P(out11), .R(R10), .K_sub(K12) );
crp u12( .P(out12), .R(R11), .K_sub(K13) );
crp u13( .P(out13), .R(R12), .K_sub(K14) );
crp u14( .P(out14), .R(R13), .K_sub(K15) );
crp u15( .P(out15), .R(R14), .K_sub(K16) );


always @(posedge clk)
        L0 <= IP_dup[33:64];


always @(posedge clk) begin
        R0 <= IP_dup[01:32] ^ out0;
        R0_dup <= IP_dup[01:32] ^ out0;
end


always @(posedge clk)
        L1 <= R0_dup;


always @(posedge clk) begin
        R1 <= L0 ^ out1;
        R1_dup <= L0 ^ out1;
end


always @(posedge clk)
        L2 <= R1_dup;


always @(posedge clk) begin
        R2 <= L1 ^ out2;
        R2_dup <= L1 ^ out2;
end

always @(posedge clk)
        L3 <= R2_dup;

always @(posedge clk) begin
        R3 <= L2 ^ out3;
        R3_dup <= L2 ^ out3;
end

always @(posedge clk)
        L4 <= R3_dup;

always @(posedge clk) begin
        R4 <= L3 ^ out4;
        R4_dup <= L3 ^ out4;
end

always @(posedge clk)
        L5 <= R4_dup;

always @(posedge clk) begin
        R5 <= L4 ^ out5;
				R5_dup <= L4 ^ out5;
end

always @(posedge clk)
        L6 <= R5_dup;

always @(posedge clk) begin
        R6 <= L5 ^ out6;
        R6_dup <= L5 ^ out6;
end

always @(posedge clk)
        L7 <= R6_dup;

always @(posedge clk) begin
        R7 <= L6 ^ out7;
        R7_dup <= L6 ^ out7;
end

always @(posedge clk)
        L8 <= R7_dup;

always @(posedge clk) begin
        R8 <= L7 ^ out8;
        R8_dup <= L7 ^ out8;
end

always @(posedge clk)
        L9 <= R8_dup;

always @(posedge clk) begin
        R9 <= L8 ^ out9;
        R9_dup <= L8 ^ out9;
end

always @(posedge clk)
        L10 <= R9_dup;

always @(posedge clk)
begin
        R10 <= L9 ^ out10;
				R10_dup <= L9 ^ out10;
end

always @(posedge clk)
        L11 <= R10_dup;

always @(posedge clk) begin
        R11 <= L10 ^ out11;
        R11_dup <= L10 ^ out11;
end

always @(posedge clk)
        L12 <= R11_dup;

always @(posedge clk) begin
        R12 <= L11 ^ out12;
        R12_dup <= L11 ^ out12;
end

always @(posedge clk)
        L13 <= R12_dup;

always @(posedge clk) begin
        R13 <= L12 ^ out13;
        R13_dup <= L12 ^ out13;
end

always @(posedge clk)
        L14 <= R13_dup;

always @(posedge clk) begin
        R14 <= L13 ^ out14;
        R14_dup <= L13 ^ out14;
end


always @(posedge clk)
        L15 <= R14_dup;


always @(posedge clk)
        R15 <= L14 ^ out15;


assign IP[1:64] = {	desIn_r[06], desIn_r[14], desIn_r[22], desIn_r[30], desIn_r[38], desIn_r[46],
			desIn_r[54], desIn_r[62], desIn_r[04], desIn_r[12], desIn_r[20], desIn_r[28],
			desIn_r[36], desIn_r[44], desIn_r[52], desIn_r[60], desIn_r[02], desIn_r[10],
			desIn_r[18], desIn_r[26], desIn_r[34], desIn_r[42], desIn_r[50], desIn_r[58],
			desIn_r[00], desIn_r[08], desIn_r[16], desIn_r[24], desIn_r[32], desIn_r[40],
			desIn_r[48], desIn_r[56], desIn_r[07], desIn_r[15], desIn_r[23], desIn_r[31],
			desIn_r[39], desIn_r[47], desIn_r[55], desIn_r[63], desIn_r[05], desIn_r[13],
			desIn_r[21], desIn_r[29], desIn_r[37], desIn_r[45], desIn_r[53], desIn_r[61],
			desIn_r[03], desIn_r[11], desIn_r[19], desIn_r[27], desIn_r[35], desIn_r[43],
			desIn_r[51], desIn_r[59], desIn_r[01], desIn_r[09], desIn_r[17], desIn_r[25],
			desIn_r[33], desIn_r[41], desIn_r[49], desIn_r[57] };

assign IP_dup[1:64] = {	desIn_r_dup[06], desIn_r_dup[14], desIn_r_dup[22], desIn_r_dup[30], desIn_r_dup[38], desIn_r_dup[46],
			desIn_r_dup[54], desIn_r_dup[62], desIn_r_dup[04], desIn_r_dup[12], desIn_r_dup[20], desIn_r_dup[28],
			desIn_r_dup[36], desIn_r_dup[44], desIn_r_dup[52], desIn_r_dup[60], desIn_r_dup[02], desIn_r_dup[10],
			desIn_r_dup[18], desIn_r_dup[26], desIn_r_dup[34], desIn_r_dup[42], desIn_r_dup[50], desIn_r_dup[58],
			desIn_r_dup[00], desIn_r_dup[08], desIn_r_dup[16], desIn_r_dup[24], desIn_r_dup[32], desIn_r_dup[40],
			desIn_r_dup[48], desIn_r_dup[56], desIn_r_dup[07], desIn_r_dup[15], desIn_r_dup[23], desIn_r_dup[31],
			desIn_r_dup[39], desIn_r_dup[47], desIn_r_dup[55], desIn_r_dup[63], desIn_r_dup[05], desIn_r_dup[13],
			desIn_r_dup[21], desIn_r_dup[29], desIn_r_dup[37], desIn_r_dup[45], desIn_r_dup[53], desIn_r_dup[61],
			desIn_r_dup[03], desIn_r_dup[11], desIn_r_dup[19], desIn_r_dup[27], desIn_r_dup[35], desIn_r_dup[43],
			desIn_r_dup[51], desIn_r_dup[59], desIn_r_dup[01], desIn_r_dup[09], desIn_r_dup[17], desIn_r_dup[25],
			desIn_r_dup[33], desIn_r_dup[41], desIn_r_dup[49], desIn_r_dup[57] };


always @(posedge clk)
	desOut <= {	FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
			FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
			FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
			FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
			FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
			FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
			FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
			FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };


endmodule