data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor/f15_histo_mem.v
 line:288 column:2: Illegal character '\x00'
1: b'%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor/f15_histo_mem.v:194: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n                                                                                                                                         : ... In instance f15_histo_mem.mem_even\n assign ramb_dia   = { 16\'h0000, dia[8:1] };\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor/f15_histo_mem.v:195: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n                                                                                                                                         : ... In instance f15_histo_mem.mem_even\n assign ramb_dib   = { 16\'h0000, dib[8:1] };\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor/f15_histo_mem.v:233: Cannot find file containing module: \'RAMB36E1\'\n   RAMB36E1 #(\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor,data/full_repos/permissive/214858095/RAMB36E1\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor,data/full_repos/permissive/214858095/RAMB36E1.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor,data/full_repos/permissive/214858095/RAMB36E1.sv\n             RAMB36E1\n             RAMB36E1.v\n             RAMB36E1.sv\n             obj_dir/RAMB36E1\n             obj_dir/RAMB36E1.v\n             obj_dir/RAMB36E1.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module f15_histo_mem #(
	parameter integer ADDR_WIDTH = 16
)(

	input  wire [ADDR_WIDTH-1:0] addr_AR,
	output reg  [8:0] data_AR,
	input  wire ena_AR,


	input  wire [ADDR_WIDTH-1:0] addr_AW,
	input  wire [8:0] data_AW,
	input  wire ena_AW,


	input  wire [ADDR_WIDTH-1:0] addr_BR,
	output reg  [8:0] data_BR,
	input  wire ena_BR,


	input  wire [ADDR_WIDTH-1:0] addr_BW,
	input  wire [8:0] data_BW,
	input  wire ena_BW,


	output reg  conflict_A,
	output reg  conflict_B,


	input  wire clk,
	input  wire rst
);



	wire [ADDR_WIDTH-2:0] even_addra, odd_addra;
	wire [ADDR_WIDTH-2:0] even_addrb, odd_addrb;
	wire [8:0] even_dia, odd_dia;
	wire [8:0] even_dib, odd_dib;
	wire [8:0] even_doa, odd_doa;
	wire [8:0] even_dob, odd_dob;
	wire even_wea, odd_wea;
	wire even_web, odd_web;
	wire even_rea, odd_rea;
	wire even_reb, odd_reb;


	wire sel_A, sel_B;



	assign sel_A = ena_AR ? addr_AR[0] : ~addr_AW[0];
	assign sel_B = ena_BR ? addr_BR[0] : ~addr_BW[0];


	always @(posedge clk)
	begin
		conflict_A <= !(addr_AR[0] ^ addr_AW[0]) & ena_AR & ena_AW;
		conflict_B <= !(addr_BR[0] ^ addr_BW[0]) & ena_BR & ena_BW;
	end


	assign even_wea =  sel_A & ena_AW;
	assign odd_wea  = !sel_A & ena_AW;
	assign even_web =  sel_B & ena_BW;
	assign odd_web  = !sel_B & ena_BW;
	assign even_rea = !sel_A & ena_AR;
	assign odd_rea  =  sel_A & ena_AR;
	assign even_reb = !sel_B & ena_BR;
	assign odd_reb  =  sel_B & ena_BR;


	assign even_addra = sel_A ? addr_AW[ADDR_WIDTH-1:1] : addr_AR[ADDR_WIDTH-1:1];
	assign even_addrb = sel_B ? addr_BW[ADDR_WIDTH-1:1] : addr_BR[ADDR_WIDTH-1:1];
	assign odd_addra  = sel_A ? addr_AR[ADDR_WIDTH-1:1] : addr_AW[ADDR_WIDTH-1:1];
	assign odd_addrb  = sel_B ? addr_BR[ADDR_WIDTH-1:1] : addr_BW[ADDR_WIDTH-1:1];


	assign even_dia = data_AW;
	assign odd_dia  = data_AW;
	assign even_dib = data_BW;
	assign odd_dib  = data_BW;

	always @(posedge clk)
	begin
		data_AR <= even_doa | odd_doa;
		data_BR <= even_dob | odd_dob;
	end


	f15_histo_mem_bank #(
		.ADDR_WIDTH(ADDR_WIDTH-1)
	) mem_even (
		.addra(even_addra),
		.addrb(even_addrb),
		.dia(even_dia),
		.dib(even_dib),
		.doa(even_doa),
		.dob(even_dob),
		.wea(even_wea),
		.web(even_web),
		.rea(even_rea),
		.reb(even_reb),
		.clk(clk),
		.rst(rst)
	);

	f15_histo_mem_bank #(
		.ADDR_WIDTH(ADDR_WIDTH-1)
	) mem_odd (
		.addra(odd_addra),
		.addrb(odd_addrb),
		.dia(odd_dia),
		.dib(odd_dib),
		.doa(odd_doa),
		.dob(odd_dob),
		.wea(odd_wea),
		.web(odd_web),
		.rea(odd_rea),
		.reb(odd_reb),
		.clk(clk),
		.rst(rst)
	);

endmodule
module f15_histo_mem #(
	parameter integer ADDR_WIDTH = 16
)(

	input  wire [ADDR_WIDTH-1:0] addr_AR,
	output reg  [8:0] data_AR,
	input  wire ena_AR,


	input  wire [ADDR_WIDTH-1:0] addr_AW,
	input  wire [8:0] data_AW,
	input  wire ena_AW,


	input  wire [ADDR_WIDTH-1:0] addr_BR,
	output reg  [8:0] data_BR,
	input  wire ena_BR,


	input  wire [ADDR_WIDTH-1:0] addr_BW,
	input  wire [8:0] data_BW,
	input  wire ena_BW,


	output reg  conflict_A,
	output reg  conflict_B,


	input  wire clk,
	input  wire rst
);




	wire [ADDR_WIDTH-2:0] even_addra, odd_addra;
	wire [ADDR_WIDTH-2:0] even_addrb, odd_addrb;
	wire [8:0] even_dia, odd_dia;
	wire [8:0] even_dib, odd_dib;
	wire [8:0] even_doa, odd_doa;
	wire [8:0] even_dob, odd_dob;
	wire even_wea, odd_wea;
	wire even_web, odd_web;
	wire even_rea, odd_rea;
	wire even_reb, odd_reb;


	wire sel_A, sel_B;



	assign sel_A = ena_AR ? addr_AR[0] : ~addr_AW[0];
	assign sel_B = ena_BR ? addr_BR[0] : ~addr_BW[0];


	always @(posedge clk)
	begin
		conflict_A <= !(addr_AR[0] ^ addr_AW[0]) & ena_AR & ena_AW;
		conflict_B <= !(addr_BR[0] ^ addr_BW[0]) & ena_BR & ena_BW;
	end


	assign even_wea =  sel_A & ena_AW;
	assign odd_wea  = !sel_A & ena_AW;
	assign even_web =  sel_B & ena_BW;
	assign odd_web  = !sel_B & ena_BW;
	assign even_rea = !sel_A & ena_AR;
	assign odd_rea  =  sel_A & ena_AR;
	assign even_reb = !sel_B & ena_BR;
	assign odd_reb  =  sel_B & ena_BR;


	assign even_addra = sel_A ? addr_AW[ADDR_WIDTH-1:1] : addr_AR[ADDR_WIDTH-1:1];
	assign even_addrb = sel_B ? addr_BW[ADDR_WIDTH-1:1] : addr_BR[ADDR_WIDTH-1:1];
	assign odd_addra  = sel_A ? addr_AR[ADDR_WIDTH-1:1] : addr_AW[ADDR_WIDTH-1:1];
	assign odd_addrb  = sel_B ? addr_BR[ADDR_WIDTH-1:1] : addr_BW[ADDR_WIDTH-1:1];


	assign even_dia = data_AW;
	assign odd_dia  = data_AW;
	assign even_dib = data_BW;
	assign odd_dib  = data_BW;

	always @(posedge clk)
	begin
		data_AR <= even_doa | odd_doa;
		data_BR <= even_dob | odd_dob;
	end


	f15_histo_mem_bank #(
		.ADDR_WIDTH(ADDR_WIDTH-1)
	) mem_even (
		.addra(even_addra),
		.addrb(even_addrb),
		.dia(even_dia),
		.dib(even_dib),
		.doa(even_doa),
		.dob(even_dob),
		.wea(even_wea),
		.web(even_web),
		.rea(even_rea),
		.reb(even_reb),
		.clk(clk),
		.rst(rst)
	);

	f15_histo_mem_bank #(
		.ADDR_WIDTH(ADDR_WIDTH-1)
	) mem_odd (
		.addra(odd_addra),
		.addrb(odd_addrb),
		.dia(odd_dia),
		.dib(odd_dib),
		.doa(odd_doa),
		.dob(odd_dob),
		.wea(odd_wea),
		.web(odd_web),
		.rea(odd_rea),
		.reb(odd_reb),
		.clk(clk),
		.rst(rst)
	);

endmodule