data/full_repos/permissive/117026779/src/QuadratureDecoder.v
1: b"%Error: data/full_repos/permissive/117026779/src/QuadratureDecoder.v:59: Cannot find file containing module: 'ExtToIntSync'\nExtToIntSync U0(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/ExtToIntSync\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/ExtToIntSync.v\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/ExtToIntSync.sv\n             ExtToIntSync\n             ExtToIntSync.v\n             ExtToIntSync.sv\n             obj_dir/ExtToIntSync\n             obj_dir/ExtToIntSync.v\n             obj_dir/ExtToIntSync.sv\n%Error: data/full_repos/permissive/117026779/src/QuadratureDecoder.v:65: Cannot find file containing module: 'ExtToIntSync'\nExtToIntSync U1(\n^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module QuadratureDecoder #(
  parameter BUS_WIDTH = 32
)(
    input wire clk,
    input wire rst,
    input wire oe,
    input wire we,
    input wire ext_phase_a,
    input wire ext_phase_b,
    output wire direction,
    inout wire [BUS_WIDTH-1:0] data
);







reg [BUS_WIDTH-1:0] counter;
reg phase_a_prev;




wire phase_a;
wire phase_b;



assign direction  = phase_a ~^ phase_b;
assign data       = oe ? counter : 32'bz;



ExtToIntSync U0(
    .clk(clk),
    .rst(rst),
    .ext_signal(ext_phase_a),
    .int_signal(phase_a)
);
ExtToIntSync U1(
    .clk(clk),
    .rst(rst),
    .ext_signal(ext_phase_b),
    .int_signal(phase_b)
);



always @(posedge clk or posedge rst) begin
    if (rst) begin
        counter = 32'h0;
        phase_a_prev = 0;
    end
    else if(we && !oe) begin
        counter = data;
    end
    else if(phase_a_prev != phase_a) begin
        if(direction == 0)
        begin
            counter = counter - 1;
        end
        if(direction == 1)
        begin
            counter = counter + 1;
        end
        phase_a_prev = phase_a;
    end
end

endmodule
module QuadratureDecoder #(
  parameter BUS_WIDTH = 32
)(
    input wire clk,
    input wire rst,
    input wire oe,
    input wire we,
    input wire ext_phase_a,
    input wire ext_phase_b,
    output wire direction,
    inout wire [BUS_WIDTH-1:0] data
);








reg [BUS_WIDTH-1:0] counter;
reg phase_a_prev;




wire phase_a;
wire phase_b;



assign direction  = phase_a ~^ phase_b;
assign data       = oe ? counter : 32'bz;



ExtToIntSync U0(
    .clk(clk),
    .rst(rst),
    .ext_signal(ext_phase_a),
    .int_signal(phase_a)
);
ExtToIntSync U1(
    .clk(clk),
    .rst(rst),
    .ext_signal(ext_phase_b),
    .int_signal(phase_b)
);



always @(posedge clk or posedge rst) begin
    if (rst) begin
        counter = 32'h0;
        phase_a_prev = 0;
    end
    else if(we && !oe) begin
        counter = data;
    end
    else if(phase_a_prev != phase_a) begin
        if(direction == 0)
        begin
            counter = counter - 1;
        end
        if(direction == 1)
        begin
            counter = counter + 1;
        end
        phase_a_prev = phase_a;
    end
end

endmodule