data/full_repos/permissive/141770060/src/Components/Clock.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/141770060/src/Components/Clock.v:57: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                 : ... Top module \'CLOCK_GENERATOR\'\nmodule CLOCK_GENERATOR #(parameter DIVIDE = 2)\n       ^~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'ONESHOT\'\nmodule ONESHOT(\n       ^~~~~~~\n                                                                                 : ... Top module \'Syncronizer\'\nmodule Syncronizer #(\n       ^~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module Syncronizer #(
	parameter WIDTH = 1,
	parameter DEFAULT_DISABLED = 0
)
(
	input wire clk,
	input wire rst,
	input wire en,
	input wire [WIDTH-1:0] in,
	output reg [WIDTH-1:0] sync_out
);

always@(posedge clk)
begin
	if(en)
	begin
		sync_out = in;
	end
	else
	begin
		sync_out = DEFAULT_DISABLED;
	end
end

endmodule
module Syncronizer #(
	parameter WIDTH = 1,
	parameter DEFAULT_DISABLED = 0
)
(
	input wire clk,
	input wire rst,
	input wire en,
	input wire [WIDTH-1:0] in,
	output reg [WIDTH-1:0] sync_out
);


always@(posedge clk)
begin
	if(en)
	begin
		sync_out = in;
	end
	else
	begin
		sync_out = DEFAULT_DISABLED;
	end
end

endmodule