data/full_repos/permissive/181665138/verilog/capitolo_ii/XNOR.v
data/verilator_xmls/01a1716f-bcc4-4d74-8a67-510b5ea49365.xml
module XNOR(x1, x0, z);
    input x1;
    input x0;
    output z;

    assign z = ~(x1 ^ x0);
endmodule
module XNOR(x1, x0, z);

    input x1;
    input x0;
    output z;

    assign z = ~(x1 ^ x0);
endmodule