data/full_repos/permissive/14657119/seven_sement_decoder.v
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1: b'%Warning-LITENDIAN: data/full_repos/permissive/14657119/seven_sement_decoder.v:4: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX;\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module seven_segment_decoder(bcd[3:0], HEX[0:6]);

	input [3:0] bcd;
	output [0:6] HEX;
	reg [0:6] HEX;
	
	always @ (bcd)
		case(bcd)
			4'b0000:HEX[0:6] = 7'b0000001;
			4'b0001:HEX[0:6] = 7'b1001111;
			4'b0010:HEX[0:6] = 7'b0010010;
			4'b0011:HEX[0:6] = 7'b0000110;
			4'b0100:HEX[0:6] = 7'b1001100;
			4'b0101:HEX[0:6] = 7'b0100100;
			4'b0110:HEX[0:6] = 7'b0100000;
			4'b0111:HEX[0:6] = 7'b0001111;
			4'b1000:HEX[0:6] = 7'b0000000;
			4'b1001:HEX[0:6] = 7'b0001100;
			default: HEX[0:6] = 7'b1111111;
		endcase
endmodule
module seven_segment_decoder(bcd[3:0], HEX[0:6]);


	input [3:0] bcd;
	output [0:6] HEX;
	reg [0:6] HEX;
	
	always @ (bcd)
		case(bcd)
			4'b0000:HEX[0:6] = 7'b0000001;
			4'b0001:HEX[0:6] = 7'b1001111;
			4'b0010:HEX[0:6] = 7'b0010010;
			4'b0011:HEX[0:6] = 7'b0000110;
			4'b0100:HEX[0:6] = 7'b1001100;
			4'b0101:HEX[0:6] = 7'b0100100;
			4'b0110:HEX[0:6] = 7'b0100000;
			4'b0111:HEX[0:6] = 7'b0001111;
			4'b1000:HEX[0:6] = 7'b0000000;
			4'b1001:HEX[0:6] = 7'b0001100;
			default: HEX[0:6] = 7'b1111111;
		endcase
endmodule