data/full_repos/permissive/19572582/Lab4/lab4_part1.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:160: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'lab4_part1\'\nmodule lab4_part1 (SW, LEDG, HEX3, HEX2, HEX1, HEX0, KEY);\n       ^~~~~~~~~~\n                                                                            : ... Top module \'b2d_ssd\'\nmodule b2d_ssd (X, SSD);\n       ^~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:181: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output reg [0:6] SSD;\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:48: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX3, HEX2, HEX1, HEX0;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:55: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H0 (Q[3:0], HEX0);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:56: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H1 (Q[7:4], HEX1);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:57: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H2 (Q[11:8], HEX2);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:58: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H3 (Q[15:12], HEX3);\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:162: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output reg [0:6] SSD;\n             ^\n%Error: Exiting due to 8 warning(s)\n'
module hex_ssd (BIN, SSD);
  input [15:0] BIN;
  output reg [0:6] SSD;

  always begin
    case(BIN)
      0:SSD=7'b0000001;
      1:SSD=7'b1001111;
      2:SSD=7'b0010010;
      3:SSD=7'b0000110;
      4:SSD=7'b1001100;
      5:SSD=7'b0100100;
      6:SSD=7'b0100000;
      7:SSD=7'b0001111;
      8:SSD=7'b0000000;
      9:SSD=7'b0001100;
      10:SSD=7'b0001000;
      11:SSD=7'b1100000;
      12:SSD=7'b0110001;
      13:SSD=7'b1000010;
      14:SSD=7'b0110000;
      15:SSD=7'b0111000;
    endcase
  end
endmodule
module hex_ssd (BIN, SSD);

  input [15:0] BIN;
  output reg [0:6] SSD;

  always begin
    case(BIN)
      0:SSD=7'b0000001;
      1:SSD=7'b1001111;
      2:SSD=7'b0010010;
      3:SSD=7'b0000110;
      4:SSD=7'b1001100;
      5:SSD=7'b0100100;
      6:SSD=7'b0100000;
      7:SSD=7'b0001111;
      8:SSD=7'b0000000;
      9:SSD=7'b0001100;
      10:SSD=7'b0001000;
      11:SSD=7'b1100000;
      12:SSD=7'b0110001;
      13:SSD=7'b1000010;
      14:SSD=7'b0110000;
      15:SSD=7'b0111000;
    endcase
  end
endmodule