data/full_repos/permissive/15946916/Lab6/lab6_5dec.v
 line:76: before: "$"
1: b'%Error: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:58: Unsupported or unknown PLI call: $monitor\n        $monitor ($time,"\\ta=%b\\tb=%b\\tcin=%b\\tsum=%b\\tcarry=%b",a,b,cin, S, Cout);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module full_adder_dec(S, Cout,A,B,Cin);
	input A, B;
    input   Cin;
	output	S;
    output  Cout;
	
	reg [2:0] input1;
	wire	[7:0] output1;
	always @ (A or B or Cin) begin
	input1[0]=Cin;
	input1[1]=B;
	input1[2]=A;
	end
	
	dec_3x8 d1(output1,input1);
	
	or or1(S,output1[1],output1[2],output1[4],output1[7]);
	or or2(Cout,output1[3],output1[5],output1[6],output1[7]);
endmodule
module full_adder_dec(S, Cout,A,B,Cin);

	input A, B;
    input   Cin;
	output	S;
    output  Cout;
	
	reg [2:0] input1;
	wire	[7:0] output1;
	always @ (A or B or Cin) begin
	input1[0]=Cin;
	input1[1]=B;
	input1[2]=A;
	end
	
	dec_3x8 d1(output1,input1);
	
	or or1(S,output1[1],output1[2],output1[4],output1[7]);
	or or2(Cout,output1[3],output1[5],output1[6],output1[7]);
endmodule