data/full_repos/permissive/194781874/phase_accumulator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/194781874/phase_accumulator.v:11: Operator DIV expects 49 bits on the LHS, but LHS\'s VARREF \'FREQ\' generates 32 bits.\n                                                                           : ... In instance phase_accumulator\n    wire [47:0] INCREMENT = (49\'h1000000000000 / 49\'d1000000) * (FREQ / 49\'d1000);\n                                                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/194781874/phase_accumulator.v:11: Operator ASSIGNW expects 48 bits on the Assign RHS, but Assign RHS\'s MUL generates 49 bits.\n                                                                           : ... In instance phase_accumulator\n    wire [47:0] INCREMENT = (49\'h1000000000000 / 49\'d1000000) * (FREQ / 49\'d1000);\n                          ^\n%Error: Exiting due to 2 warning(s)\n'
module phase_accumulator(
    input CLK,
    input RESET,
    input [31:0] FREQ,
    input [11:0] PHASE_MOD,
    output [11:0] PHASE
    );
    
    wire [47:0] INCREMENT = (49'h1000000000000 / 49'd1000000) * (FREQ / 49'd1000);
    reg [47:0] TEMP_PHASE = 48'd0;
    
    always @ (posedge CLK) begin
        if (RESET) TEMP_PHASE <= 48'd0;
        else TEMP_PHASE <= TEMP_PHASE + INCREMENT;
    end
    
    assign PHASE = TEMP_PHASE[47:36] + PHASE_MOD[11:0];
endmodule
module phase_accumulator(
    input CLK,
    input RESET,
    input [31:0] FREQ,
    input [11:0] PHASE_MOD,
    output [11:0] PHASE
    );

    
    wire [47:0] INCREMENT = (49'h1000000000000 / 49'd1000000) * (FREQ / 49'd1000);
    reg [47:0] TEMP_PHASE = 48'd0;
    
    always @ (posedge CLK) begin
        if (RESET) TEMP_PHASE <= 48'd0;
        else TEMP_PHASE <= TEMP_PHASE + INCREMENT;
    end
    
    assign PHASE = TEMP_PHASE[47:36] + PHASE_MOD[11:0];
endmodule