data/full_repos/permissive/202233324/rtl/ascii_input.v
Syntax Error
data/verilator_xmls/6234d5ac-8747-43a2-aa91-ea24cc52e9f4.xml
module ascii_input(
    input       clk25,
    input       rst,


    input       key_clk,
    input ioctl_download,
    input [7:0] textinput_dout,
    input [15:0] textinput_addr,


    input       cs,
    input       address,
    output reg [7:0] dout,
    output  data_ready
);
   wire new_clk;
	Clock_divider_ascii #(4000) cdiv(clk25,new_clk);
	
	


   reg [15:0] ascii_last_byte = 16'b0;
   reg [7:0] ascii_data[0:65535];
   reg [15:0] text_byte = 16'b0;
   reg in_dl = 1'b0;
 
   assign data_ready= in_dl & !ioctl_download;

    reg  prev_ps2_clkdb;
    

    reg [7:0]  ascii;
    reg ascii_rdy;
    reg shift;
    reg [2:0] cur_state;
    reg [2:0] next_state;

    always @(posedge clk25 or posedge rst)
    begin
        if (rst)
        begin
            prev_ps2_clkdb <= 1'b0;
            ascii_rdy   <= 0;
            ascii_last_byte = 16'b0;
        end
        else
        begin


            if ((prev_ps2_clkdb == 1'b1) && (new_clk == 1'b0))
            begin

              if (!ascii_rdy & data_ready& (text_byte<=ascii_last_byte))
		        begin
				     case(ascii_data[text_byte])
					  8'h0A: ascii=8'h0D;
					  default: ascii= ascii_data[text_byte];
					  endcase
                 
            	  ascii_rdy   <= 1;
                 $display("inside a %x text_byte %x ascii_last_byte %x",ascii,text_byte,ascii_last_byte);
                 text_byte = text_byte + 16'b00000001;
		        end
            end
            

            prev_ps2_clkdb <= new_clk;

            
  	         if (ioctl_download)
            begin
                 $display("ioctl_download: %x",textinput_addr);
                 ascii_data[textinput_addr] = textinput_dout;
                 ascii_last_byte = textinput_addr;
                 text_byte = 16'b0;
                 in_dl=1'b1;
            end
            else
            begin


                if (in_dl & text_byte>(ascii_last_byte) )
                    begin
                       in_dl=1'b0;
                       $display("indl %x",in_dl);
                       $display("ascii_rdy %x",ascii_rdy);
                    end
            end


            if (cs == 1'b1)
            begin
                if (address == 1'b0)
                begin

                    dout <= {1'b1, ascii[6:0]};
                 $display("put ascii  %x in_dl %x text_byte %x ascii_last_byte %x ascii_rdy %x",ascii,in_dl,text_byte,ascii_last_byte,ascii_rdy);
                    ascii_rdy <= 1'b0;
                end
                else
                begin

                    dout <= {ascii_rdy, 7'b0};
                end
            end
           
          end
			 end

endmodule
module ascii_input(
    input       clk25,
    input       rst,


    input       key_clk,
    input ioctl_download,
    input [7:0] textinput_dout,
    input [15:0] textinput_addr,


    input       cs,
    input       address,
    output reg [7:0] dout,
    output  data_ready
);

   wire new_clk;
	Clock_divider_ascii #(4000) cdiv(clk25,new_clk);
	
	


   reg [15:0] ascii_last_byte = 16'b0;
   reg [7:0] ascii_data[0:65535];
   reg [15:0] text_byte = 16'b0;
   reg in_dl = 1'b0;
 
   assign data_ready= in_dl & !ioctl_download;

    reg  prev_ps2_clkdb;
    

    reg [7:0]  ascii;
    reg ascii_rdy;
    reg shift;
    reg [2:0] cur_state;
    reg [2:0] next_state;

    always @(posedge clk25 or posedge rst)
    begin
        if (rst)
        begin
            prev_ps2_clkdb <= 1'b0;
            ascii_rdy   <= 0;
            ascii_last_byte = 16'b0;
        end
        else
        begin


            if ((prev_ps2_clkdb == 1'b1) && (new_clk == 1'b0))
            begin

              if (!ascii_rdy & data_ready& (text_byte<=ascii_last_byte))
		        begin
				     case(ascii_data[text_byte])
					  8'h0A: ascii=8'h0D;
					  default: ascii= ascii_data[text_byte];
					  endcase
                 
            	  ascii_rdy   <= 1;
                 $display("inside a %x text_byte %x ascii_last_byte %x",ascii,text_byte,ascii_last_byte);
                 text_byte = text_byte + 16'b00000001;
		        end
            end
            

            prev_ps2_clkdb <= new_clk;

            
  	         if (ioctl_download)
            begin
                 $display("ioctl_download: %x",textinput_addr);
                 ascii_data[textinput_addr] = textinput_dout;
                 ascii_last_byte = textinput_addr;
                 text_byte = 16'b0;
                 in_dl=1'b1;
            end
            else
            begin


                if (in_dl & text_byte>(ascii_last_byte) )
                    begin
                       in_dl=1'b0;
                       $display("indl %x",in_dl);
                       $display("ascii_rdy %x",ascii_rdy);
                    end
            end


            if (cs == 1'b1)
            begin
                if (address == 1'b0)
                begin

                    dout <= {1'b1, ascii[6:0]};
                 $display("put ascii  %x in_dl %x text_byte %x ascii_last_byte %x ascii_rdy %x",ascii,in_dl,text_byte,ascii_last_byte,ascii_rdy);
                    ascii_rdy <= 1'b0;
                end
                else
                begin

                    dout <= {ascii_rdy, 7'b0};
                end
            end
           
          end
			 end

endmodule