data/full_repos/permissive/171279647/hdl/basic/bitonic_sort.v
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1: b"%Error: data/full_repos/permissive/171279647/hdl/basic/bitonic_sort.v:87: Cannot find file containing module: 'bitonic_block'\n  bitonic_block #(\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171279647/hdl/basic,data/full_repos/permissive/171279647/bitonic_block\n             data/full_repos/permissive/171279647/hdl/basic,data/full_repos/permissive/171279647/bitonic_block.v\n             data/full_repos/permissive/171279647/hdl/basic,data/full_repos/permissive/171279647/bitonic_block.sv\n             bitonic_block\n             bitonic_block.v\n             bitonic_block.sv\n             obj_dir/bitonic_block\n             obj_dir/bitonic_block.v\n             obj_dir/bitonic_block.sv\n%Error: Exiting due to 1 error(s)\n"
module bitonic_sort #(
	parameter DATA_WIDTH = 16,
	parameter CHAN_NUM = 8,
	parameter DIR = 0,
	parameter SIGNED = 0
)
(
	input wire clk,
	input wire [DATA_WIDTH*CHAN_NUM-1:0]data_in,
	output wire [DATA_WIDTH*CHAN_NUM-1:0]data_out
);

localparam CHAN_ACT = 2**$clog2(CHAN_NUM);
localparam CHAN_ADD = CHAN_ACT - CHAN_NUM;

localparam STAGES = $clog2(CHAN_ACT);
localparam STAGE_DATA_WIDTH = DATA_WIDTH*CHAN_ACT;

wire [STAGE_DATA_WIDTH-1:0]stage_data[STAGES:0];
wire [STAGE_DATA_WIDTH-1:0]data_out_tmp;

assign stage_data[0] = {data_in, {CHAN_ADD{SIGNED?{1'b1,{(DATA_WIDTH-1){1'b0}}}:{DATA_WIDTH{1'b0}}}}};
assign data_out_tmp = stage_data[STAGES];
assign data_out = DIR ? data_out_tmp[DATA_WIDTH*CHAN_NUM-1:0] : data_out_tmp[DATA_WIDTH*CHAN_ACT-1-:DATA_WIDTH*CHAN_NUM];

genvar stage;
genvar block;

generate for (stage = 0; stage < STAGES; stage = stage + 1) begin: SORT_STAGE
	localparam BLOCKS = CHAN_ACT / 2**(stage+1);
	localparam BLOCK_ORDER = stage;
		
	wire [STAGE_DATA_WIDTH-1:0]stage_data_in;
	wire [STAGE_DATA_WIDTH-1:0]stage_data_out;
		
	assign stage_data_in = stage_data[stage];
	assign stage_data[stage + 1] = stage_data_out;

	for (block = 0; block < BLOCKS; block = block + 1) begin: BLOCK
		localparam BLOCK_DATA_WIDTH = DATA_WIDTH*2**(BLOCK_ORDER+1);
		localparam BLOCK_POLARITY = DIR ? (~block & 1) : (block & 1);
			
		wire [BLOCK_DATA_WIDTH-1:0]block_data_in;
		wire [BLOCK_DATA_WIDTH-1:0]block_data_out;
			
		assign block_data_in = stage_data_in[BLOCK_DATA_WIDTH*(block+1)-1-:BLOCK_DATA_WIDTH];
		assign stage_data_out[BLOCK_DATA_WIDTH*(block+1)-1-:BLOCK_DATA_WIDTH] = block_data_out;
		
		bitonic_block #(
			.DATA_WIDTH(DATA_WIDTH),
			.ORDER(BLOCK_ORDER),
			.POLARITY(BLOCK_POLARITY),
			.SIGNED(SIGNED)
		) bitonic_block_inst (
			.clk(clk),
			.data_in(block_data_in),
			.data_out(block_data_out)
		);
	end
end endgenerate

endmodule
module bitonic_sort #(
	parameter DATA_WIDTH = 16,
	parameter CHAN_NUM = 8,
	parameter DIR = 0,
	parameter SIGNED = 0
)
(
	input wire clk,
	input wire [DATA_WIDTH*CHAN_NUM-1:0]data_in,
	output wire [DATA_WIDTH*CHAN_NUM-1:0]data_out
);


localparam CHAN_ACT = 2**$clog2(CHAN_NUM);
localparam CHAN_ADD = CHAN_ACT - CHAN_NUM;

localparam STAGES = $clog2(CHAN_ACT);
localparam STAGE_DATA_WIDTH = DATA_WIDTH*CHAN_ACT;

wire [STAGE_DATA_WIDTH-1:0]stage_data[STAGES:0];
wire [STAGE_DATA_WIDTH-1:0]data_out_tmp;

assign stage_data[0] = {data_in, {CHAN_ADD{SIGNED?{1'b1,{(DATA_WIDTH-1){1'b0}}}:{DATA_WIDTH{1'b0}}}}};
assign data_out_tmp = stage_data[STAGES];
assign data_out = DIR ? data_out_tmp[DATA_WIDTH*CHAN_NUM-1:0] : data_out_tmp[DATA_WIDTH*CHAN_ACT-1-:DATA_WIDTH*CHAN_NUM];

genvar stage;
genvar block;

generate for (stage = 0; stage < STAGES; stage = stage + 1) begin: SORT_STAGE
	localparam BLOCKS = CHAN_ACT / 2**(stage+1);
	localparam BLOCK_ORDER = stage;
		
	wire [STAGE_DATA_WIDTH-1:0]stage_data_in;
	wire [STAGE_DATA_WIDTH-1:0]stage_data_out;
		
	assign stage_data_in = stage_data[stage];
	assign stage_data[stage + 1] = stage_data_out;

	for (block = 0; block < BLOCKS; block = block + 1) begin: BLOCK
		localparam BLOCK_DATA_WIDTH = DATA_WIDTH*2**(BLOCK_ORDER+1);
		localparam BLOCK_POLARITY = DIR ? (~block & 1) : (block & 1);
			
		wire [BLOCK_DATA_WIDTH-1:0]block_data_in;
		wire [BLOCK_DATA_WIDTH-1:0]block_data_out;
			
		assign block_data_in = stage_data_in[BLOCK_DATA_WIDTH*(block+1)-1-:BLOCK_DATA_WIDTH];
		assign stage_data_out[BLOCK_DATA_WIDTH*(block+1)-1-:BLOCK_DATA_WIDTH] = block_data_out;
		
		bitonic_block #(
			.DATA_WIDTH(DATA_WIDTH),
			.ORDER(BLOCK_ORDER),
			.POLARITY(BLOCK_POLARITY),
			.SIGNED(SIGNED)
		) bitonic_block_inst (
			.clk(clk),
			.data_in(block_data_in),
			.data_out(block_data_out)
		);
	end
end endgenerate

endmodule