data/full_repos/permissive/159902111/PCPU_experiment/BE.v
1: b'%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:1: Cannot find include file: BEOp_def.v\n`include "BEOp_def.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159902111/PCPU_experiment,data/full_repos/permissive/159902111/BEOp_def.v\n             data/full_repos/permissive/159902111/PCPU_experiment,data/full_repos/permissive/159902111/BEOp_def.v.v\n             data/full_repos/permissive/159902111/PCPU_experiment,data/full_repos/permissive/159902111/BEOp_def.v.sv\n             BEOp_def.v\n             BEOp_def.v.v\n             BEOp_def.v.sv\n             obj_dir/BEOp_def.v\n             obj_dir/BEOp_def.v.v\n             obj_dir/BEOp_def.v.sv\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:16: Define or directive not defined: \'`BEOP_SW\'\n      `BEOP_SW: BE <= 4\'b1111;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:16: syntax error, unexpected \':\', expecting endcase\n      `BEOP_SW: BE <= 4\'b1111;\n              ^\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:17: Define or directive not defined: \'`BEOP_SH\'\n      `BEOP_SH: \n      ^~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:24: Define or directive not defined: \'`BEOP_SB\'\n      `BEOP_SB:\n      ^~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:25: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      begin\n      ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:35: Define or directive not defined: \'`BEOP_LW\'\n      `BEOP_LW: BE <= 4\'b1111;\n      ^~~~~~~~\n%Warning-ENDLABEL: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:35: End label \'BE\' does not match begin label \'\'\n      `BEOP_LW: BE <= 4\'b1111;\n                ^~\n                   ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:35: syntax error, unexpected <=\n      `BEOP_LW: BE <= 4\'b1111;\n                   ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:36: Define or directive not defined: \'`BEOP_LHU\'\n      `BEOP_LHU:\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:40: syntax error, unexpected <=, expecting IDENTIFIER\n            BE <= 4\'b0011;\n               ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:42: syntax error, unexpected <=, expecting IDENTIFIER\n            BE <= 4\'b1100;\n               ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:44: Define or directive not defined: \'`BEOP_LH\'\n      `BEOP_LH:\n      ^~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:48: syntax error, unexpected <=, expecting IDENTIFIER\n            BE <= 4\'b0011;\n               ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:50: syntax error, unexpected <=, expecting IDENTIFIER\n            BE <= 4\'b1100;\n               ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:52: Define or directive not defined: \'`BEOP_LBU\'\n      `BEOP_LBU:\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:56: syntax error, unexpected <=, expecting IDENTIFIER\n          BE <= 4\'b0001;\n             ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:58: syntax error, unexpected <=, expecting IDENTIFIER\n          BE <= 4\'b0010;\n             ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:60: syntax error, unexpected <=, expecting IDENTIFIER\n          BE <= 4\'b0100;\n             ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:62: syntax error, unexpected <=, expecting IDENTIFIER\n          BE <= 4\'b1000;\n             ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:64: Define or directive not defined: \'`BEOP_LB\'\n      `BEOP_LB:\n      ^~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:68: syntax error, unexpected <=, expecting IDENTIFIER\n          BE <= 4\'b0001;\n             ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:70: syntax error, unexpected <=, expecting IDENTIFIER\n          BE <= 4\'b0010;\n             ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:72: syntax error, unexpected <=, expecting IDENTIFIER\n          BE <= 4\'b0100;\n             ^~\n%Error: data/full_repos/permissive/159902111/PCPU_experiment/BE.v:74: syntax error, unexpected <=, expecting IDENTIFIER\n          BE <= 4\'b1000;\n             ^~\n%Error: Exiting due to 24 error(s), 1 warning(s)\n'
module BE(
  input [2:0] BEOp,
  input [1:0] A1_0,
  
  output [3:0] BE_o,
  output Sign_o
  );
  reg [3:0] BE;
  reg       Sign;
  
  always@(*)
  begin
    case(BEOp)
      `BEOP_SW: BE <= 4'b1111;
      `BEOP_SH: 
      begin
        if (A1_0[1])
          BE <= 4'b1100;
        else
          BE <= 4'b0011;
      end
      `BEOP_SB:
      begin
        if (A1_0 == 2'b00)
          BE <= 4'b0001;
        else if (A1_0 == 2'b01)
          BE <= 4'b0010;
        else if (A1_0 == 2'b10)
          BE <= 4'b0100;
        else
          BE <= 4'b1000;
      end
      `BEOP_LW: BE <= 4'b1111;
      `BEOP_LHU:
      begin
        Sign <= 1'b0;
        if (A1_0[1] == 0)
            BE <= 4'b0011;
        else
            BE <= 4'b1100;
      end
      `BEOP_LH:
      begin
        Sign <= 1'b1;
        if (A1_0[1] == 1'b0)
            BE <= 4'b0011;
        else
            BE <= 4'b1100;
      end
      `BEOP_LBU:
      begin
        Sign <= 1'b0;
        if (A1_0 == 2'b00)
          BE <= 4'b0001;
        else if (A1_0 == 2'b01)
          BE <= 4'b0010;
        else if (A1_0 == 2'b10)
          BE <= 4'b0100;
        else
          BE <= 4'b1000;
      end
      `BEOP_LB:
      begin
        Sign <= 1'b1;
        if (A1_0 == 2'b00)
          BE <= 4'b0001;
        else if (A1_0 == 2'b01)
          BE <= 4'b0010;
        else if (A1_0 == 2'b10)
          BE <= 4'b0100;
        else
          BE <= 4'b1000;
      end
    endcase
  end
  assign BE_o = BE;
  assign Sign_o = Sign;
endmodule
module BE(
  input [2:0] BEOp,
  input [1:0] A1_0,
  
  output [3:0] BE_o,
  output Sign_o
  );

  reg [3:0] BE;
  reg       Sign;
  
  always@(*)
  begin
    case(BEOp)
      `BEOP_SW: BE <= 4'b1111;
      `BEOP_SH: 
      begin
        if (A1_0[1])
          BE <= 4'b1100;
        else
          BE <= 4'b0011;
      end
      `BEOP_SB:
      begin
        if (A1_0 == 2'b00)
          BE <= 4'b0001;
        else if (A1_0 == 2'b01)
          BE <= 4'b0010;
        else if (A1_0 == 2'b10)
          BE <= 4'b0100;
        else
          BE <= 4'b1000;
      end
      `BEOP_LW: BE <= 4'b1111;
      `BEOP_LHU:
      begin
        Sign <= 1'b0;
        if (A1_0[1] == 0)
            BE <= 4'b0011;
        else
            BE <= 4'b1100;
      end
      `BEOP_LH:
      begin
        Sign <= 1'b1;
        if (A1_0[1] == 1'b0)
            BE <= 4'b0011;
        else
            BE <= 4'b1100;
      end
      `BEOP_LBU:
      begin
        Sign <= 1'b0;
        if (A1_0 == 2'b00)
          BE <= 4'b0001;
        else if (A1_0 == 2'b01)
          BE <= 4'b0010;
        else if (A1_0 == 2'b10)
          BE <= 4'b0100;
        else
          BE <= 4'b1000;
      end
      `BEOP_LB:
      begin
        Sign <= 1'b1;
        if (A1_0 == 2'b00)
          BE <= 4'b0001;
        else if (A1_0 == 2'b01)
          BE <= 4'b0010;
        else if (A1_0 == 2'b10)
          BE <= 4'b0100;
        else
          BE <= 4'b1000;
      end
    endcase
  end
  assign BE_o = BE;
  assign Sign_o = Sign;
endmodule