data/full_repos/permissive/210946536/src/modules/byte_enabled_dual_port.v
 line:137: before: "integer"
data/verilator_xmls/15141563-910b-4311-8528-2ce27033807a.xml
module byte_enabled_dual_port
  #(
    parameter NB_COL = 4,
    parameter COL_WIDTH = 8,
    parameter RAM_DEPTH = 2048,
    parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE",
    parameter INIT_FILE = ""
    )
   (
    output wire [(NB_COL*COL_WIDTH)-1:0] o_data_a,
    output wire [(NB_COL*COL_WIDTH)-1:0] o_data_b,

    input wire [clogb2(RAM_DEPTH-1)-1:0] i_addr_a,
    input wire [clogb2(RAM_DEPTH-1)-1:0] i_addr_b,
    input wire [(NB_COL*COL_WIDTH)-1:0]  i_data_a,
    input wire [(NB_COL*COL_WIDTH)-1:0]  i_data_b,
    input wire                           i_clock,
    input wire [NB_COL-1:0]              wea,
    input wire [NB_COL-1:0]              web,
    input wire                           ena,
    input wire                           enb,
    input wire                           i_reset_a,
    input wire                           i_reset_b,
    input wire                           i_rea,
    input wire                           i_reb
    );



  reg [(NB_COL*COL_WIDTH)-1:0] BRAM [RAM_DEPTH-1:0];
  reg [(NB_COL*COL_WIDTH)-1:0] ram_data_a = {(NB_COL*COL_WIDTH){1'b0}};
  reg [(NB_COL*COL_WIDTH)-1:0] ram_data_b = {(NB_COL*COL_WIDTH){1'b0}};


  generate
    if (INIT_FILE != "") begin: use_init_file
      initial
        $readmemb(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
    end else begin: init_bram_to_zero
      integer ram_index;
      initial
        for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
          BRAM[ram_index] = {(NB_COL*COL_WIDTH){1'b0}};
    end
  endgenerate

  generate
  genvar i;
     for (i = 0; i < NB_COL; i = i+1) begin: byte_write
       always @(posedge i_clock)
         if (ena)
           if (wea[i]) begin
             BRAM[i_addr_a][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= i_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             ram_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= i_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
           end else begin
             ram_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= BRAM[i_addr_a][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
           end

       always @(posedge i_clock)
         if (enb)
           if (web[i]) begin
             BRAM[i_addr_b][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= i_data_b[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             ram_data_b[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= i_data_b[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
           end else begin
             ram_data_b[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= BRAM[i_addr_b][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
           end
     end
  endgenerate


  generate
    if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register


       assign o_data_a = ram_data_a;
       assign o_data_b = ram_data_b;

    end else begin: output_register



      reg [(NB_COL*COL_WIDTH)-1:0] douta_reg = {(NB_COL*COL_WIDTH){1'b0}};
      reg [(NB_COL*COL_WIDTH)-1:0] doutb_reg = {(NB_COL*COL_WIDTH){1'b0}};

      always @(posedge i_clock)
        if (i_reset_a)
          douta_reg <= {(NB_COL*COL_WIDTH){1'b0}};
        else if (i_rea)
          douta_reg <= ram_data_a;

      always @(posedge i_clock)
        if (i_reset_b)
          doutb_reg <= {(NB_COL*COL_WIDTH){1'b0}};
        else if (i_reb)
          doutb_reg <= ram_data_b;

      assign o_data_a = douta_reg;
      assign o_data_b = doutb_reg;

    end
  endgenerate


  function integer clogb2;
    input integer depth;
      for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
  endfunction

endmodule
module byte_enabled_dual_port
  #(
    parameter NB_COL = 4,
    parameter COL_WIDTH = 8,
    parameter RAM_DEPTH = 2048,
    parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE",
    parameter INIT_FILE = ""
    )
   (
    output wire [(NB_COL*COL_WIDTH)-1:0] o_data_a,
    output wire [(NB_COL*COL_WIDTH)-1:0] o_data_b,

    input wire [clogb2(RAM_DEPTH-1)-1:0] i_addr_a,
    input wire [clogb2(RAM_DEPTH-1)-1:0] i_addr_b,
    input wire [(NB_COL*COL_WIDTH)-1:0]  i_data_a,
    input wire [(NB_COL*COL_WIDTH)-1:0]  i_data_b,
    input wire                           i_clock,
    input wire [NB_COL-1:0]              wea,
    input wire [NB_COL-1:0]              web,
    input wire                           ena,
    input wire                           enb,
    input wire                           i_reset_a,
    input wire                           i_reset_b,
    input wire                           i_rea,
    input wire                           i_reb
    );




  reg [(NB_COL*COL_WIDTH)-1:0] BRAM [RAM_DEPTH-1:0];
  reg [(NB_COL*COL_WIDTH)-1:0] ram_data_a = {(NB_COL*COL_WIDTH){1'b0}};
  reg [(NB_COL*COL_WIDTH)-1:0] ram_data_b = {(NB_COL*COL_WIDTH){1'b0}};


  generate
    if (INIT_FILE != "") begin: use_init_file
      initial
        $readmemb(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
    end else begin: init_bram_to_zero
      integer ram_index;
      initial
        for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
          BRAM[ram_index] = {(NB_COL*COL_WIDTH){1'b0}};
    end
  endgenerate

  generate
  genvar i;
     for (i = 0; i < NB_COL; i = i+1) begin: byte_write
       always @(posedge i_clock)
         if (ena)
           if (wea[i]) begin
             BRAM[i_addr_a][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= i_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             ram_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= i_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
           end else begin
             ram_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= BRAM[i_addr_a][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
           end

       always @(posedge i_clock)
         if (enb)
           if (web[i]) begin
             BRAM[i_addr_b][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= i_data_b[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
             ram_data_b[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= i_data_b[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
           end else begin
             ram_data_b[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= BRAM[i_addr_b][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
           end
     end
  endgenerate


  generate
    if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register


       assign o_data_a = ram_data_a;
       assign o_data_b = ram_data_b;

    end else begin: output_register



      reg [(NB_COL*COL_WIDTH)-1:0] douta_reg = {(NB_COL*COL_WIDTH){1'b0}};
      reg [(NB_COL*COL_WIDTH)-1:0] doutb_reg = {(NB_COL*COL_WIDTH){1'b0}};

      always @(posedge i_clock)
        if (i_reset_a)
          douta_reg <= {(NB_COL*COL_WIDTH){1'b0}};
        else if (i_rea)
          douta_reg <= ram_data_a;

      always @(posedge i_clock)
        if (i_reset_b)
          doutb_reg <= {(NB_COL*COL_WIDTH){1'b0}};
        else if (i_reb)
          doutb_reg <= ram_data_b;

      assign o_data_a = douta_reg;
      assign o_data_b = doutb_reg;

    end
  endgenerate


  function integer clogb2;
    input integer depth;
      for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
  endfunction

endmodule