data/full_repos/permissive/121803953/Lab2/lab2.v
data/verilator_xmls/d30f6656-4afb-4621-883b-a3d78d745bea.xml
module part3(a, P);
    input [3:0] a;
    output P;
    wire [3:0] x;
    nand n1(x[0],~a[0],~a[1], a[2]);    
    nand n2(x[1],~a[0], a[2], a[3]);    
    nand n3(x[2], a[1],~a[2], a[3]);
	 nand n4(x[3],~a[1], a[2], a[3]);
    assign P = ~&x;
endmodule
module part3(a, P);

    input [3:0] a;
    output P;
    wire [3:0] x;
    nand n1(x[0],~a[0],~a[1], a[2]);    
    nand n2(x[1],~a[0], a[2], a[3]);    
    nand n3(x[2], a[1],~a[2], a[3]);
	 nand n4(x[3],~a[1], a[2], a[3]);
    assign P = ~&x;
endmodule