data/full_repos/permissive/185824253/rtl/myCPU/multi.v
1: b"%Error: data/full_repos/permissive/185824253/rtl/myCPU/multi.v:91: Cannot find file containing module: 'mux_8'\n   mux_8 #(64) partial_0 (\n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/mux_8\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/mux_8.v\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/mux_8.sv\n             mux_8\n             mux_8.v\n             mux_8.sv\n             obj_dir/mux_8\n             obj_dir/mux_8.v\n             obj_dir/mux_8.sv\n%Error: Exiting due to 1 error(s)\n"
module cra(
	input  [63:0] A,
	input  [63:0] B,
	input  [63:0] C,

	output [63:0] result,
	output [63:0] carry
);

	assign result = A ^ B ^ C;
	assign carry[0] = 1'b0;

	generate
		genvar i;
		for (i = 1; i < 64; i = i + 1)
		begin: carry_o
			assign carry[i] = (A[i-1] & B[i-1]) | (A[i-1] & C[i-1]) | (B[i-1] & C[i-1]);
		end
	endgenerate

endmodule
module cra(
	input  [63:0] A,
	input  [63:0] B,
	input  [63:0] C,

	output [63:0] result,
	output [63:0] carry
);


	assign result = A ^ B ^ C;
	assign carry[0] = 1'b0;

	generate
		genvar i;
		for (i = 1; i < 64; i = i + 1)
		begin: carry_o
			assign carry[i] = (A[i-1] & B[i-1]) | (A[i-1] & C[i-1]) | (B[i-1] & C[i-1]);
		end
	endgenerate

endmodule