data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/prj/RTL/AHB2MEM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/prj/RTL/AHB2MEM.v:58: Bit extraction of array[1023:0] requires 10 bit index, not 11 bits.\n                                                                                                 : ... In instance AHB2MEM\n         memory[buf_hwaddr[MEMWIDTH:2]] <= (HWDATA & hwdata_mask) | (HRDATA & ~hwdata_mask);\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/prj/RTL/AHB2MEM.v:60: Bit extraction of array[1023:0] requires 10 bit index, not 11 bits.\n                                                                                                 : ... In instance AHB2MEM\n      HRDATA = memory[HADDR[MEMWIDTH:2]];\n                     ^\n%Error: Exiting due to 2 warning(s)\n'
module AHB2MEM
   #(parameter MEMWIDTH = 12)
   (
   input wire           HSEL,
   input wire           HCLK,
   input wire           HRESETn,
   input wire           HREADY,
   input wire    [31:0] HADDR,
   input wire     [1:0] HTRANS,
   input wire           HWRITE,
   input wire     [2:0] HSIZE,
   input wire    [31:0] HWDATA,
   output wire          HREADYOUT,
   output reg    [31:0] HRDATA,
   output wire          HRESP
   );

   assign HREADYOUT = 1'b1;
   assign HRESP     = 1'b0;

   reg  [31:0] memory[0:(2**(MEMWIDTH-2)-1)];


   reg  [31:0] hwdata_mask;
   reg         we;
   reg  [31:0] buf_hwaddr;


   always @(posedge HCLK or negedge HRESETn)
   begin
      if(!HRESETn)
      begin
         we <= 1'b0;
         buf_hwaddr <= 32'h0;
      end
      else
         if(HREADY)
         begin
            we <= HSEL & HWRITE & HTRANS[1];
            buf_hwaddr <= HADDR;
   
            casez (HSIZE[1:0])
               2'b1?: hwdata_mask <=  32'hFFFFFFFF;
               2'b01: hwdata_mask <= (32'h0000FFFF << (16 * HADDR[1]));
               2'b00: hwdata_mask <= (32'h000000FF << (8 * HADDR[1:0]));
            endcase
          end
   end
   

   always @ (posedge HCLK)
   begin
      if(we) 
         memory[buf_hwaddr[MEMWIDTH:2]] <= (HWDATA & hwdata_mask) | (HRDATA & ~hwdata_mask);
         
      HRDATA = memory[HADDR[MEMWIDTH:2]];
   end

endmodule
module AHB2MEM
   #(parameter MEMWIDTH = 12)
   (
   input wire           HSEL,
   input wire           HCLK,
   input wire           HRESETn,
   input wire           HREADY,
   input wire    [31:0] HADDR,
   input wire     [1:0] HTRANS,
   input wire           HWRITE,
   input wire     [2:0] HSIZE,
   input wire    [31:0] HWDATA,
   output wire          HREADYOUT,
   output reg    [31:0] HRDATA,
   output wire          HRESP
   );


   assign HREADYOUT = 1'b1;
   assign HRESP     = 1'b0;

   reg  [31:0] memory[0:(2**(MEMWIDTH-2)-1)];


   reg  [31:0] hwdata_mask;
   reg         we;
   reg  [31:0] buf_hwaddr;


   always @(posedge HCLK or negedge HRESETn)
   begin
      if(!HRESETn)
      begin
         we <= 1'b0;
         buf_hwaddr <= 32'h0;
      end
      else
         if(HREADY)
         begin
            we <= HSEL & HWRITE & HTRANS[1];
            buf_hwaddr <= HADDR;
   
            casez (HSIZE[1:0])
               2'b1?: hwdata_mask <=  32'hFFFFFFFF;
               2'b01: hwdata_mask <= (32'h0000FFFF << (16 * HADDR[1]));
               2'b00: hwdata_mask <= (32'h000000FF << (8 * HADDR[1:0]));
            endcase
          end
   end
   

   always @ (posedge HCLK)
   begin
      if(we) 
         memory[buf_hwaddr[MEMWIDTH:2]] <= (HWDATA & hwdata_mask) | (HRDATA & ~hwdata_mask);
         
      HRDATA = memory[HADDR[MEMWIDTH:2]];
   end

endmodule