data/full_repos/permissive/127585421/hardware/rtl/anton_neopixel_raw.v
1: b'%Error: data/full_repos/permissive/127585421/hardware/rtl/anton_neopixel_raw.v:1: Cannot find include file: anton_common.v\n`include "anton_common.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127585421/hardware/rtl,data/full_repos/permissive/127585421/anton_common.v\n             data/full_repos/permissive/127585421/hardware/rtl,data/full_repos/permissive/127585421/anton_common.v.v\n             data/full_repos/permissive/127585421/hardware/rtl,data/full_repos/permissive/127585421/anton_common.v.sv\n             anton_common.v\n             anton_common.v.v\n             anton_common.v.sv\n             obj_dir/anton_common.v\n             obj_dir/anton_common.v.v\n             obj_dir/anton_common.v.sv\n%Error: data/full_repos/permissive/127585421/hardware/rtl/anton_neopixel_raw.v:38: Define or directive not defined: \'`CLOG2\'\n  localparam PIXELS_BITS = `CLOG2(PIXELS_MAX);    \n                           ^~~~~~\n%Error: Exiting due to 2 error(s)\n'
module anton_neopixel_raw (
  input clk10mhz,
  output neoData,
  output neoState,

  input [PIXELS_BITS-1:0]busAddr,
  input [7:0]busDataIn,
  input busClk,
  input busWrite,
  input busRead,
  output [7:0]busDataOut
  );

  parameter  PIXELS_MAX  = 66;
  parameter  RESET_DELAY = 600;
  localparam PIXELS_BITS = `CLOG2(PIXELS_MAX);



  reg [7:0]              busDataOutBuffer;
  reg [7:0]              pixels[PIXELS_MAX-1:0];
  reg [23:0]             pixel_value        = 'd0;
  reg [11:0]             neo_pattern_lookup = 'd0;
            
  reg [9:0]              reset_delay_count  = 'd0;
  reg [3:0]              bit_pattern_index  = 'd0;
  reg [PIXELS_BITS-1:0]  pixel_index        = {PIXELS_BITS{1'b0}};
  reg [4:0]              pixel_bit_index    = 'd0;
  reg                    state              = 'b0;
  reg                    data_int           = 'b0;
  reg [1:0]              cycle              = 'd0;

  localparam  ENUM_STATE_TRANSMIT = 0;
  localparam  ENUM_STATE_RESET    = 1;
  



  always @(*) begin
    case (pixel_value[pixel_bit_index])


      1'b0: neo_pattern_lookup = 12'b000000000111;
      1'b1: neo_pattern_lookup = 12'b000011111111;
    endcase
  end


  always @(*) begin
    `ifdef HARDCODED_PIXELS


      case (pixel_index)
        'd0: pixel_value = 24'hff00d5;
        'd1: pixel_value = 24'h008800;
        'd2: pixel_value = 24'h000090;
        default:  pixel_value = 24'h101010;
      endcase
    `else


      pixel_value = { 
        5'b00000, pixels[pixel_index][6], pixels[pixel_index][7], 1'b0,
        4'b0000,  pixels[pixel_index][0], pixels[pixel_index][1], pixels[pixel_index][2], 1'b0,
        4'b0000,  pixels[pixel_index][3], pixels[pixel_index][4], pixels[pixel_index][5], 1'b0
      };
    `endif
  end


  always @(*) begin
    if (state == ENUM_STATE_TRANSMIT) begin

      data_int = neo_pattern_lookup[bit_pattern_index];
    end else begin

      data_int = 'd0;
    end
  end


  always @(posedge busClk) begin

    if (busWrite) begin
      pixels[busAddr[PIXELS_BITS-1:0]] <= busDataIn;
    end
    if (busRead) begin
      busDataOutBuffer <= pixels[busAddr[PIXELS_BITS-1:0]];
    end
  end


  always @(posedge clk10mhz) begin
    if (state == ENUM_STATE_TRANSMIT) begin

      if (bit_pattern_index < 'd11) begin

        bit_pattern_index <= bit_pattern_index + 'b1;
      end else begin

        bit_pattern_index <= 'b0;

        if (pixel_bit_index < 'd23) begin

          pixel_bit_index <= pixel_bit_index + 'b1;
        end else begin

          pixel_bit_index <= 'b0;

          if (pixel_index < PIXELS_MAX-1) begin

            pixel_index <= pixel_index + 'b1;
          end else begin

            pixel_index <= 'd0;
            state <= ENUM_STATE_RESET;
          end
        end        
      end
    end else begin

      reset_delay_count <= reset_delay_count + 'b1;

      if (reset_delay_count > RESET_DELAY) begin  

        state <= 'd0;
        if (cycle == 'd3) $finish;
        cycle <= cycle + 'd1;
        reset_delay_count <= 'd0;
      end
    end
  end


  assign neoData    = data_int;
  assign neoState   = state;
  assign busDataOut = busDataOutBuffer;
  
endmodule
module anton_neopixel_raw (
  input clk10mhz,
  output neoData,
  output neoState,

  input [PIXELS_BITS-1:0]busAddr,
  input [7:0]busDataIn,
  input busClk,
  input busWrite,
  input busRead,
  output [7:0]busDataOut
  );


  parameter  PIXELS_MAX  = 66;
  parameter  RESET_DELAY = 600;
  localparam PIXELS_BITS = `CLOG2(PIXELS_MAX);



  reg [7:0]              busDataOutBuffer;
  reg [7:0]              pixels[PIXELS_MAX-1:0];
  reg [23:0]             pixel_value        = 'd0;
  reg [11:0]             neo_pattern_lookup = 'd0;
            
  reg [9:0]              reset_delay_count  = 'd0;
  reg [3:0]              bit_pattern_index  = 'd0;
  reg [PIXELS_BITS-1:0]  pixel_index        = {PIXELS_BITS{1'b0}};
  reg [4:0]              pixel_bit_index    = 'd0;
  reg                    state              = 'b0;
  reg                    data_int           = 'b0;
  reg [1:0]              cycle              = 'd0;

  localparam  ENUM_STATE_TRANSMIT = 0;
  localparam  ENUM_STATE_RESET    = 1;
  



  always @(*) begin
    case (pixel_value[pixel_bit_index])


      1'b0: neo_pattern_lookup = 12'b000000000111;
      1'b1: neo_pattern_lookup = 12'b000011111111;
    endcase
  end


  always @(*) begin
    `ifdef HARDCODED_PIXELS


      case (pixel_index)
        'd0: pixel_value = 24'hff00d5;
        'd1: pixel_value = 24'h008800;
        'd2: pixel_value = 24'h000090;
        default:  pixel_value = 24'h101010;
      endcase
    `else


      pixel_value = { 
        5'b00000, pixels[pixel_index][6], pixels[pixel_index][7], 1'b0,
        4'b0000,  pixels[pixel_index][0], pixels[pixel_index][1], pixels[pixel_index][2], 1'b0,
        4'b0000,  pixels[pixel_index][3], pixels[pixel_index][4], pixels[pixel_index][5], 1'b0
      };
    `endif
  end


  always @(*) begin
    if (state == ENUM_STATE_TRANSMIT) begin

      data_int = neo_pattern_lookup[bit_pattern_index];
    end else begin

      data_int = 'd0;
    end
  end


  always @(posedge busClk) begin

    if (busWrite) begin
      pixels[busAddr[PIXELS_BITS-1:0]] <= busDataIn;
    end
    if (busRead) begin
      busDataOutBuffer <= pixels[busAddr[PIXELS_BITS-1:0]];
    end
  end


  always @(posedge clk10mhz) begin
    if (state == ENUM_STATE_TRANSMIT) begin

      if (bit_pattern_index < 'd11) begin

        bit_pattern_index <= bit_pattern_index + 'b1;
      end else begin

        bit_pattern_index <= 'b0;

        if (pixel_bit_index < 'd23) begin

          pixel_bit_index <= pixel_bit_index + 'b1;
        end else begin

          pixel_bit_index <= 'b0;

          if (pixel_index < PIXELS_MAX-1) begin

            pixel_index <= pixel_index + 'b1;
          end else begin

            pixel_index <= 'd0;
            state <= ENUM_STATE_RESET;
          end
        end        
      end
    end else begin

      reset_delay_count <= reset_delay_count + 'b1;

      if (reset_delay_count > RESET_DELAY) begin  

        state <= 'd0;
        if (cycle == 'd3) $finish;
        cycle <= cycle + 'd1;
        reset_delay_count <= 'd0;
      end
    end
  end


  assign neoData    = data_int;
  assign neoState   = state;
  assign busDataOut = busDataOutBuffer;
  
endmodule