data/full_repos/permissive/117736309/sync_test.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/117736309/sync_test.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD / 2) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/117736309/sync_test.v:20: Cannot find file containing module: \'vga_sync\'\n    vga_sync uut (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117736309,data/full_repos/permissive/117736309/vga_sync\n             data/full_repos/permissive/117736309,data/full_repos/permissive/117736309/vga_sync.v\n             data/full_repos/permissive/117736309,data/full_repos/permissive/117736309/vga_sync.sv\n             vga_sync\n             vga_sync.v\n             vga_sync.sv\n             obj_dir/vga_sync\n             obj_dir/vga_sync.v\n             obj_dir/vga_sync.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sync_test;

    wire hsync;
    wire vsync;

    reg clk;
    parameter PERIOD = 10;

    initial
        clk = 0;

    always

        #(PERIOD / 2) clk = ~clk;


    vga_sync uut (
        .clk(clk),
        .hsync(hsync),
        .vsync(vsync)
    );

endmodule
module sync_test;


    wire hsync;
    wire vsync;

    reg clk;
    parameter PERIOD = 10;

    initial
        clk = 0;

    always

        #(PERIOD / 2) clk = ~clk;


    vga_sync uut (
        .clk(clk),
        .hsync(hsync),
        .vsync(vsync)
    );

endmodule