data/full_repos/permissive/136510272/projects/02_text_adapter_80x25/vga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/02_text_adapter_80x25/vga.v:44: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                            : ... In instance vga\nreg [9:0] x = 1\'b0;  \n              ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/02_text_adapter_80x25/vga.v:45: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                            : ... In instance vga\nreg [9:0] y = 1\'b0;\n              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/02_text_adapter_80x25/vga.v:115: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance vga\n        clock_timer <= 1\'b0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/02_text_adapter_80x25/vga.v:129: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance vga\n    x <= x == (horiz_whole - 1) ? 1\'b0 : (x + 1\'b1);\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/02_text_adapter_80x25/vga.v:135: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance vga\n        y <= y == (vert_whole - 1) ? 1\'b0 : (y + 1\'b1);\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/02_text_adapter_80x25/vga.v:145: Operator ADD expects 32 or 12 bits on the LHS, but LHS\'s SEL generates 7 bits.\n                                                                                             : ... In instance vga\n        3\'b000: font_char_addr <= 2*(x_real[9:3] + y_real[9:4] * 80);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/02_text_adapter_80x25/vga.v:203: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance vga\n        red   <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/02_text_adapter_80x25/vga.v:204: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance vga\n        green <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/02_text_adapter_80x25/vga.v:205: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance vga\n        blue  <= 1\'b0;\n              ^~\n%Error: Exiting due to 9 warning(s)\n'
module vga(


    input   wire        clk,


    output  reg  [4:0]  red,
    output  reg  [5:0]  green,
    output  reg  [4:0]  blue,
    output  wire        hs,
    output  wire        vs,

    output  reg  [11:0] adapter_font,
    input   wire [7:0]  adapter_data,

    output  reg  [11:0] font_char_addr,
    input   wire [7:0]  font_char_data

);


parameter horiz_visible = 640;
parameter horiz_back    = 48;
parameter horiz_sync    = 96;
parameter horiz_front   = 16;
parameter horiz_whole   = 800;



parameter vert_visible = 480;
parameter vert_back    = 33;
parameter vert_sync    = 2;
parameter vert_front   = 10;
parameter vert_whole   = 525;



assign hs = x >= (horiz_visible + horiz_front) && x < (horiz_visible + horiz_front + horiz_sync);
assign vs = y >= (vert_visible  + vert_front)  && y < (vert_visible  + vert_front  + vert_sync);


reg [9:0] x = 1'b0;
reg [9:0] y = 1'b0;






wire [9:0] x_real = x > 791 ? x - 792 : x + 8;


wire [9:0] y_real = x > 791 ? y - 39 : y - 40;


reg [7:0] current_char;
reg [7:0] temp_current_attr;
reg [7:0] current_attr;
reg [7:0] current_data;
reg       flash;




wire current_bit = current_data[ 3'h7 ^ x_real[2:0] ];


wire [15:0] fr_color =


    current_attr[3:0] == 4'd0  ? { 5'h03, 6'h03, 5'h03 } :
    current_attr[3:0] == 4'd1  ? { 5'h00, 6'h00, 5'h0F } :
    current_attr[3:0] == 4'd2  ? { 5'h00, 6'h1F, 5'h00 } :
    current_attr[3:0] == 4'd3  ? { 5'h00, 6'h1F, 5'h0F } :
    current_attr[3:0] == 4'd4  ? { 5'h0F, 6'h00, 5'h00 } :
    current_attr[3:0] == 4'd5  ? { 5'h0F, 6'h00, 5'h0F } :
    current_attr[3:0] == 4'd6  ? { 5'h0F, 6'h1F, 5'h00 } :
    current_attr[3:0] == 4'd7  ? { 5'h0F, 6'h1F, 5'h0F } :
    current_attr[3:0] == 4'd8  ? { 5'h07, 6'h0F, 5'h07 } :
    current_attr[3:0] == 4'd9  ? { 5'h00, 6'h00, 5'h1F } :
    current_attr[3:0] == 4'd10 ? { 5'h00, 6'h3F, 5'h00 } :
    current_attr[3:0] == 4'd11 ? { 5'h00, 6'h3F, 5'h1F } :
    current_attr[3:0] == 4'd12 ? { 5'h1F, 6'h00, 5'h00 } :
    current_attr[3:0] == 4'd13 ? { 5'h1F, 6'h00, 5'h1F } :
    current_attr[3:0] == 4'd14 ? { 5'h1F, 6'h3F, 5'h00 } :
                                   { 5'h1F, 6'h3F, 5'h1F };


wire [15:0] bg_color =


    current_attr[6:4] == 3'd0 ? { 5'h03, 6'h03, 5'h03 } :
    current_attr[6:4] == 3'd1 ? { 5'h00, 6'h00, 5'h0F } :
    current_attr[6:4] == 3'd2 ? { 5'h00, 6'h1F, 5'h00 } :
    current_attr[6:4] == 3'd3 ? { 5'h00, 6'h1F, 5'h0F } :
    current_attr[6:4] == 3'd4 ? { 5'h0F, 6'h00, 5'h00 } :
    current_attr[6:4] == 3'd5 ? { 5'h0F, 6'h00, 5'h0F } :
    current_attr[6:4] == 3'd6 ? { 5'h0F, 6'h1F, 5'h00 } :
                                { 5'h0F, 6'h1F, 5'h0F };


reg [1:0]  clock_divider;
reg [23:0] clock_timer;


always @(posedge clk) clock_divider <= clock_divider + 1'b1;


always @(posedge clock_divider[1]) begin


    if (clock_timer == 12500000) begin
        clock_timer <= 1'b0;
        flash <= flash ^ 1'b1;
    end
    else
        clock_timer <= clock_timer + 1;

end



always @(posedge clock_divider[1]) begin



    x <= x == (horiz_whole - 1) ? 1'b0 : (x + 1'b1);


    if (x == (horiz_whole - 1)) begin


        y <= y == (vert_whole - 1) ? 1'b0 : (y + 1'b1);

    end


    case (x_real[2:0])




        3'b000: font_char_addr <= 2*(x_real[9:3] + y_real[9:4] * 80);


        3'b001: begin


            current_char <= font_char_data;




            font_char_addr <= {font_char_addr[11:1], 1'b1};

        end


        3'b010: temp_current_attr <= font_char_data;



        3'b110: adapter_font <= {current_char, y_real[3:0]};



        3'b111: begin

            current_data <= adapter_data;
            current_attr <= temp_current_attr;

        end

    endcase





    if (x < horiz_visible && y < vert_visible) begin






        if (y >= 40 && y < 440)



            {red, green, blue} <= current_bit ? (current_attr[7] & flash ? bg_color : fr_color) : bg_color;
        else

            {red, green, blue} <= {5'h02, 6'h01, 5'h02};

    end


    else begin

        red   <= 1'b0;
        green <= 1'b0;
        blue  <= 1'b0;

    end

end

endmodule
module vga(


    input   wire        clk,


    output  reg  [4:0]  red,
    output  reg  [5:0]  green,
    output  reg  [4:0]  blue,
    output  wire        hs,
    output  wire        vs,

    output  reg  [11:0] adapter_font,
    input   wire [7:0]  adapter_data,

    output  reg  [11:0] font_char_addr,
    input   wire [7:0]  font_char_data

);



parameter horiz_visible = 640;
parameter horiz_back    = 48;
parameter horiz_sync    = 96;
parameter horiz_front   = 16;
parameter horiz_whole   = 800;



parameter vert_visible = 480;
parameter vert_back    = 33;
parameter vert_sync    = 2;
parameter vert_front   = 10;
parameter vert_whole   = 525;



assign hs = x >= (horiz_visible + horiz_front) && x < (horiz_visible + horiz_front + horiz_sync);
assign vs = y >= (vert_visible  + vert_front)  && y < (vert_visible  + vert_front  + vert_sync);


reg [9:0] x = 1'b0;
reg [9:0] y = 1'b0;






wire [9:0] x_real = x > 791 ? x - 792 : x + 8;


wire [9:0] y_real = x > 791 ? y - 39 : y - 40;


reg [7:0] current_char;
reg [7:0] temp_current_attr;
reg [7:0] current_attr;
reg [7:0] current_data;
reg       flash;




wire current_bit = current_data[ 3'h7 ^ x_real[2:0] ];


wire [15:0] fr_color =


    current_attr[3:0] == 4'd0  ? { 5'h03, 6'h03, 5'h03 } :
    current_attr[3:0] == 4'd1  ? { 5'h00, 6'h00, 5'h0F } :
    current_attr[3:0] == 4'd2  ? { 5'h00, 6'h1F, 5'h00 } :
    current_attr[3:0] == 4'd3  ? { 5'h00, 6'h1F, 5'h0F } :
    current_attr[3:0] == 4'd4  ? { 5'h0F, 6'h00, 5'h00 } :
    current_attr[3:0] == 4'd5  ? { 5'h0F, 6'h00, 5'h0F } :
    current_attr[3:0] == 4'd6  ? { 5'h0F, 6'h1F, 5'h00 } :
    current_attr[3:0] == 4'd7  ? { 5'h0F, 6'h1F, 5'h0F } :
    current_attr[3:0] == 4'd8  ? { 5'h07, 6'h0F, 5'h07 } :
    current_attr[3:0] == 4'd9  ? { 5'h00, 6'h00, 5'h1F } :
    current_attr[3:0] == 4'd10 ? { 5'h00, 6'h3F, 5'h00 } :
    current_attr[3:0] == 4'd11 ? { 5'h00, 6'h3F, 5'h1F } :
    current_attr[3:0] == 4'd12 ? { 5'h1F, 6'h00, 5'h00 } :
    current_attr[3:0] == 4'd13 ? { 5'h1F, 6'h00, 5'h1F } :
    current_attr[3:0] == 4'd14 ? { 5'h1F, 6'h3F, 5'h00 } :
                                   { 5'h1F, 6'h3F, 5'h1F };


wire [15:0] bg_color =


    current_attr[6:4] == 3'd0 ? { 5'h03, 6'h03, 5'h03 } :
    current_attr[6:4] == 3'd1 ? { 5'h00, 6'h00, 5'h0F } :
    current_attr[6:4] == 3'd2 ? { 5'h00, 6'h1F, 5'h00 } :
    current_attr[6:4] == 3'd3 ? { 5'h00, 6'h1F, 5'h0F } :
    current_attr[6:4] == 3'd4 ? { 5'h0F, 6'h00, 5'h00 } :
    current_attr[6:4] == 3'd5 ? { 5'h0F, 6'h00, 5'h0F } :
    current_attr[6:4] == 3'd6 ? { 5'h0F, 6'h1F, 5'h00 } :
                                { 5'h0F, 6'h1F, 5'h0F };


reg [1:0]  clock_divider;
reg [23:0] clock_timer;


always @(posedge clk) clock_divider <= clock_divider + 1'b1;


always @(posedge clock_divider[1]) begin


    if (clock_timer == 12500000) begin
        clock_timer <= 1'b0;
        flash <= flash ^ 1'b1;
    end
    else
        clock_timer <= clock_timer + 1;

end



always @(posedge clock_divider[1]) begin



    x <= x == (horiz_whole - 1) ? 1'b0 : (x + 1'b1);


    if (x == (horiz_whole - 1)) begin


        y <= y == (vert_whole - 1) ? 1'b0 : (y + 1'b1);

    end


    case (x_real[2:0])




        3'b000: font_char_addr <= 2*(x_real[9:3] + y_real[9:4] * 80);


        3'b001: begin


            current_char <= font_char_data;




            font_char_addr <= {font_char_addr[11:1], 1'b1};

        end


        3'b010: temp_current_attr <= font_char_data;



        3'b110: adapter_font <= {current_char, y_real[3:0]};



        3'b111: begin

            current_data <= adapter_data;
            current_attr <= temp_current_attr;

        end

    endcase





    if (x < horiz_visible && y < vert_visible) begin






        if (y >= 40 && y < 440)



            {red, green, blue} <= current_bit ? (current_attr[7] & flash ? bg_color : fr_color) : bg_color;
        else

            {red, green, blue} <= {5'h02, 6'h01, 5'h02};

    end


    else begin

        red   <= 1'b0;
        green <= 1'b0;
        blue  <= 1'b0;

    end

end

endmodule