data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Reciprocal/Reciprocal_Pipelined.v
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1: b'%Error: Cannot find file containing module: Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Reciprocal/Reciprocal_Pipelined.v\n%Error: Exiting due to 3 error(s)\n'
module Reciprocal_Pipelined_Hung

		#(parameter 	
						WL = 24,
						LUT_bits = 26,
						LUT_addWidth = 12
		 )

		(
			input CLK,
			input nRST,
			input CE,
			input [WL-1:0] din,

			output [WL-1:0] dout
		);


		reg  [LUT_bits-1 : 0]     LUT 	[2**LUT_addWidth-1 : 0];
		reg  [LUT_bits-1 : 0]	  iniValue;
		reg  [LUT_bits-1 : 0]	  iniValue_delay;
		wire [LUT_addWidth-1:0]   reg_cmp;
		reg  [WL-1:0]	  		  	  xh;
		reg  [WL-1:0]			  	  xl;
		reg  [WL-1:0]			  	  Sub;
		reg  [WL+LUT_bits-1:0]	  Mul;
		wire [WL:0] 			  	  temp_result;
		


		

		assign reg_cmp = din[WL-2 : WL-1-LUT_addWidth];
		always @(posedge CLK) begin
			if(~nRST) begin
					xh <= 0;
					xl <= 0;
					Sub <= 0;
					Mul <= 0;
					iniValue <= 0;
					iniValue_delay <= 0;
			end else begin
				if (CE) begin
					iniValue <= LUT[reg_cmp];
					iniValue_delay <= iniValue;
					xh[WL-1:WL-(LUT_addWidth+1)] <= din[WL-1:WL-(LUT_addWidth+1)];
					xh[WL-(LUT_addWidth+1)-1:0]	<= 0;
					xl[WL-(LUT_addWidth+1)-1:0] <= din[WL-(LUT_addWidth+1)-1:0];
					xl[WL-1:WL-(LUT_addWidth+1)] <= 0;
					Sub <= xh - xl;
					Mul <= Sub * iniValue_delay;

				end
			end
		end
		

		ux_round2nearest
			#(
				.WordLength(WL+LUT_bits),
				.RoundLength(LUT_bits-1)
			 )
		round_0 
			(
				.CLK(CLK),
				.RESET(nRST),
				.CE(CE),
				.x(Mul),
				.y(temp_result)
			 );
		
		assign dout = temp_result[WL-1:0];
		
endmodule
module Reciprocal_Pipelined_Hung

		#(parameter 	
						WL = 24,
						LUT_bits = 26,
						LUT_addWidth = 12
		 )

		(
			input CLK,
			input nRST,
			input CE,
			input [WL-1:0] din,

			output [WL-1:0] dout
		);



		reg  [LUT_bits-1 : 0]     LUT 	[2**LUT_addWidth-1 : 0];
		reg  [LUT_bits-1 : 0]	  iniValue;
		reg  [LUT_bits-1 : 0]	  iniValue_delay;
		wire [LUT_addWidth-1:0]   reg_cmp;
		reg  [WL-1:0]	  		  	  xh;
		reg  [WL-1:0]			  	  xl;
		reg  [WL-1:0]			  	  Sub;
		reg  [WL+LUT_bits-1:0]	  Mul;
		wire [WL:0] 			  	  temp_result;
		


		

		assign reg_cmp = din[WL-2 : WL-1-LUT_addWidth];
		always @(posedge CLK) begin
			if(~nRST) begin
					xh <= 0;
					xl <= 0;
					Sub <= 0;
					Mul <= 0;
					iniValue <= 0;
					iniValue_delay <= 0;
			end else begin
				if (CE) begin
					iniValue <= LUT[reg_cmp];
					iniValue_delay <= iniValue;
					xh[WL-1:WL-(LUT_addWidth+1)] <= din[WL-1:WL-(LUT_addWidth+1)];
					xh[WL-(LUT_addWidth+1)-1:0]	<= 0;
					xl[WL-(LUT_addWidth+1)-1:0] <= din[WL-(LUT_addWidth+1)-1:0];
					xl[WL-1:WL-(LUT_addWidth+1)] <= 0;
					Sub <= xh - xl;
					Mul <= Sub * iniValue_delay;

				end
			end
		end
		

		ux_round2nearest
			#(
				.WordLength(WL+LUT_bits),
				.RoundLength(LUT_bits-1)
			 )
		round_0 
			(
				.CLK(CLK),
				.RESET(nRST),
				.CE(CE),
				.x(Mul),
				.y(temp_result)
			 );
		
		assign dout = temp_result[WL-1:0];
		
endmodule