data/full_repos/permissive/164482394/Verilog/StepperFM.v
data/verilator_xmls/47287c74-7f2a-4f30-a90e-ed66cd36a152.xml
module StepperFM(Clk, Pitch, FM_out, VelIn, VelOut);
	input Clk;
	input [23:0] Pitch;
	input [7:0] VelIn;
	output reg [7:0] VelOut;
	output reg FM_out;
	reg [23:0] counter;
	
	always @ (posedge Clk)
	begin
		VelOut = VelIn;
		if (Pitch != 0)
		begin
			if (counter <= Pitch) 
			begin
				counter <= counter+1;
			end
			else
			begin
				counter <= 0;
				FM_out <= ~FM_out;
			end
		end
	end
	
endmodule
module StepperFM(Clk, Pitch, FM_out, VelIn, VelOut);

	input Clk;
	input [23:0] Pitch;
	input [7:0] VelIn;
	output reg [7:0] VelOut;
	output reg FM_out;
	reg [23:0] counter;
	
	always @ (posedge Clk)
	begin
		VelOut = VelIn;
		if (Pitch != 0)
		begin
			if (counter <= Pitch) 
			begin
				counter <= counter+1;
			end
			else
			begin
				counter <= 0;
				FM_out <= ~FM_out;
			end
		end
	end
	
endmodule