data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v
 line:289: before: "signed"
1: b'%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:726: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                                : ... In instance FFT_128\n  MUL098 = 0 + (op<<1)  + (op<<5)  + (op<<6) ;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:726: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                                : ... In instance FFT_128\n  MUL098 = 0 + (op<<1)  + (op<<5)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:726: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                                : ... In instance FFT_128\n  MUL098 = 0 + (op<<1)  + (op<<5)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:712: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                                : ... In instance FFT_128\n  MUL058 = 0 + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:712: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                                : ... In instance FFT_128\n  MUL058 = 0 + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:712: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                                : ... In instance FFT_128\n  MUL058 = 0 + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:712: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                                : ... In instance FFT_128\n  MUL058 = 0 + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                                   ^~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:58: Cannot find file containing module: \'FFT_64\'\n FFT_64 myFFT64_reuse(.clk(clk), \n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/FFT_64\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/FFT_64.v\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/FFT_64.sv\n             FFT_64\n             FFT_64.v\n             FFT_64.sv\n             obj_dir/FFT_64\n             obj_dir/FFT_64.v\n             obj_dir/FFT_64.sv\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:77: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'load\' generates 4 bits.\n                                                                               : ... In instance FFT_128\n  assign yi64_re = (state==load||state == waitn||state == finish)? yi64_1: yi64_2;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:77: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'waitn\' generates 4 bits.\n                                                                               : ... In instance FFT_128\n  assign yi64_re = (state==load||state == waitn||state == finish)? yi64_1: yi64_2;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:77: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'finish\' generates 4 bits.\n                                                                               : ... In instance FFT_128\n  assign yi64_re = (state==load||state == waitn||state == finish)? yi64_1: yi64_2;\n                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:85: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'finish\' generates 4 bits.\n                                                                               : ... In instance FFT_128\n  else if (state == finish) begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:97: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 4 bits.\n                                                                               : ... In instance FFT_128\n   state <= idle;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:99: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'load\' generates 4 bits.\n                                                                               : ... In instance FFT_128\n   state <= load;  \n         ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:101: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'waitn\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n   state <= waitn;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:103: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'finish\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n   state <= finish;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:105: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'load_ag\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n   state <= load_ag;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:107: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'waitn_ag\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n   state <= waitn_ag;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:109: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'finish_ag\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n   state <= finish_ag;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:111: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n   state <= idle;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:110: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'finish_ag\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n  else if(state == finish_ag)\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:108: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'waitn_ag\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n  else if(state == waitn_ag)\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:106: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'load_ag\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n  else if(state == load_ag)\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:104: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'finish\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n  else if(state == finish)\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:102: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'waitn\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n  else if(state == waitn)\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:100: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'load\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n  else if(state == load)\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:121: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'finish\' generates 4 bits.\n                                                                                : ... In instance FFT_128\n  else if(init||state==finish)\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:143: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[0] <= yi[7:0];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:144: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[1] <= yi[15:8];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:145: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[2] <= yi[23:16];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:146: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[3] <= yi[31:24];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:147: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[4] <= yi[39:32];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:148: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[5] <= yi[47:40];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:149: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[6] <= yi[55:48];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:150: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[7] <= yi[63:56];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:151: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[8] <= yi[71:64];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:152: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[9] <= yi[79:72];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:153: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[10] <= yi[87:80];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:154: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[11] <= yi[95:88];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:155: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[12] <= yi[103:96];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:156: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[13] <= yi[111:104];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:157: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[14] <= yi[119:112];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:158: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[15] <= yi[127:120];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:159: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[16] <= yi[135:128];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:160: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[17] <= yi[143:136];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:161: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[18] <= yi[151:144];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:162: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[19] <= yi[159:152];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:163: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[20] <= yi[167:160];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:164: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[21] <= yi[175:168];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:165: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[22] <= yi[183:176];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:166: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[23] <= yi[191:184];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:167: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[24] <= yi[199:192];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:168: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[25] <= yi[207:200];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:169: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[26] <= yi[215:208];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:170: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[27] <= yi[223:216];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:171: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[28] <= yi[231:224];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:172: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[29] <= yi[239:232];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:173: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[30] <= yi[247:240];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:174: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[31] <= yi[255:248];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:175: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[32] <= yi[263:256];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:176: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[33] <= yi[271:264];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:177: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[34] <= yi[279:272];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:178: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[35] <= yi[287:280];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:179: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[36] <= yi[295:288];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:180: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[37] <= yi[303:296];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:181: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[38] <= yi[311:304];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:182: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[39] <= yi[319:312];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:183: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[40] <= yi[327:320];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:184: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[41] <= yi[335:328];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:185: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[42] <= yi[343:336];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:186: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[43] <= yi[351:344];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:187: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[44] <= yi[359:352];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:188: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[45] <= yi[367:360];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:189: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[46] <= yi[375:368];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:190: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[47] <= yi[383:376];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:191: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[48] <= yi[391:384];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:192: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[49] <= yi[399:392];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:193: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[50] <= yi[407:400];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:194: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[51] <= yi[415:408];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:195: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[52] <= yi[423:416];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:196: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[53] <= yi[431:424];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:197: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[54] <= yi[439:432];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:198: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[55] <= yi[447:440];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:199: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[56] <= yi[455:448];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:200: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[57] <= yi[463:456];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:201: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[58] <= yi[471:464];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:202: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[59] <= yi[479:472];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:203: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[60] <= yi[487:480];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:204: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[61] <= (Final == 1) ? ((((yi[495:488] + 1))&255) - (((yi[495:488] + 1)) >>> 8)) : yi[495:488];\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:204: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[61] <= (Final == 1) ? ((((yi[495:488] + 1))&255) - (((yi[495:488] + 1)) >>> 8)) : yi[495:488];\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:204: Operator COND expects 32 or 10 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[61] <= (Final == 1) ? ((((yi[495:488] + 1))&255) - (((yi[495:488] + 1)) >>> 8)) : yi[495:488];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:205: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[62] <= yi[503:496];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:206: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[63] <= (((yi[511:504] + 1))&255) - (((yi[511:504] + 1)) >>> 8);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:206: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[63] <= (((yi[511:504] + 1))&255) - (((yi[511:504] + 1)) >>> 8);\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:207: Operator AND expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[64] <= ((yi[7:0])&255) - ((yi[7:0]) >>> 8);\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:207: Operator SHIFTR expects 32 or 10 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[64] <= ((yi[7:0])&255) - ((yi[7:0]) >>> 8);\n                                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:292: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL118 = 0 + (op<<1)  + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:292: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL118 = 0 + (op<<1)  + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:292: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL118 = 0 + (op<<1)  + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:292: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL118 = 0 + (op<<1)  + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:292: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL118 = 0 + (op<<1)  + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:208: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[65] <= (-(MUL118(yi[15:8]))&255) - (-(MUL118(yi[15:8])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:299: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL046 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:299: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL046 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:299: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL046 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:299: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL046 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:209: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[66] <= ((MUL046(yi[23:16]))&255) - ((MUL046(yi[23:16])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:306: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL031 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:306: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL031 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:306: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL031 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:306: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL031 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:306: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL031 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:210: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[67] <= (-(MUL031(yi[31:24]))&255) - (-(MUL031(yi[31:24])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:313: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL060 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:313: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL060 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:313: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL060 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:313: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL060 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:211: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[68] <= ((MUL060(yi[39:32]))&255) - ((MUL060(yi[39:32])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:320: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL116 = 0 + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:320: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL116 = 0 + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:320: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL116 = 0 + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:320: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL116 = 0 + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:212: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[69] <= ((MUL116(yi[47:40]))&255) - ((MUL116(yi[47:40])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:327: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL067 = 0 + op     + (op<<1)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:327: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL067 = 0 + op     + (op<<1)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:327: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL067 = 0 + op     + (op<<1)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:213: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[70] <= (-(MUL067(yi[55:48]))&255) - (-(MUL067(yi[55:48])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:334: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL061 = 0 + op     + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:334: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL061 = 0 + op     + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:334: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL061 = 0 + op     + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:334: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL061 = 0 + op     + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:334: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL061 = 0 + op     + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:214: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[71] <= (-(MUL061(yi[63:56]))&255) - (-(MUL061(yi[63:56])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:341: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL002 = 0 + (op<<1) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:215: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[72] <= ((MUL002(yi[71:64]))&255) - ((MUL002(yi[71:64])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:348: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL021 = 0 + op     + (op<<2)  + (op<<4) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:348: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL021 = 0 + op     + (op<<2)  + (op<<4) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:348: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL021 = 0 + op     + (op<<2)  + (op<<4) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:216: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[73] <= ((MUL021(yi[79:72]))&255) - ((MUL021(yi[79:72])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:355: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL092 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:355: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL092 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:355: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL092 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:355: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL092 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:217: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[74] <= ((MUL092(yi[87:80]))&255) - ((MUL092(yi[87:80])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:362: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL062 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:362: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL062 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:362: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL062 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:362: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL062 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:362: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL062 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:218: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[75] <= (-(MUL062(yi[95:88]))&255) - (-(MUL062(yi[95:88])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:369: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL120 = 0 + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:369: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL120 = 0 + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:369: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL120 = 0 + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:369: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL120 = 0 + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:219: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[76] <= ((MUL120(yi[103:96]))&255) - ((MUL120(yi[103:96])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:376: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL025 = 0 + op     + (op<<3)  + (op<<4) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:376: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL025 = 0 + op     + (op<<3)  + (op<<4) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:376: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL025 = 0 + op     + (op<<3)  + (op<<4) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:220: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[77] <= (-(MUL025(yi[111:104]))&255) - (-(MUL025(yi[111:104])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:383: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:383: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:383: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:383: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:383: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:383: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:221: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[78] <= ((MUL123(yi[119:112]))&255) - ((MUL123(yi[119:112])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:390: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL122 = 0 + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:390: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL122 = 0 + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:390: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL122 = 0 + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:390: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL122 = 0 + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:390: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL122 = 0 + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:222: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[79] <= (-(MUL122(yi[127:120]))&255) - (-(MUL122(yi[127:120])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:397: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL004 = 0 + (op<<2) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:223: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[80] <= ((MUL004(yi[135:128]))&255) - ((MUL004(yi[135:128])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:404: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL042 = 0 + (op<<1)  + (op<<3)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:404: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL042 = 0 + (op<<1)  + (op<<3)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:404: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL042 = 0 + (op<<1)  + (op<<3)  + (op<<5) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:224: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[81] <= ((MUL042(yi[143:136]))&255) - ((MUL042(yi[143:136])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:411: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL073 = 0 + op     + (op<<3)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:411: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL073 = 0 + op     + (op<<3)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:411: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL073 = 0 + op     + (op<<3)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:225: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[82] <= (-(MUL073(yi[151:144]))&255) - (-(MUL073(yi[151:144])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:418: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL124 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:418: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL124 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:418: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL124 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:418: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL124 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:418: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL124 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:226: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[83] <= (-(MUL124(yi[159:152]))&255) - (-(MUL124(yi[159:152])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:425: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL017 = 0 + op     + (op<<4) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:425: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL017 = 0 + op     + (op<<4) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:227: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[84] <= (-(MUL017(yi[167:160]))&255) - (-(MUL017(yi[167:160])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:432: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL050 = 0 + (op<<1)  + (op<<4)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:432: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL050 = 0 + (op<<1)  + (op<<4)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:432: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL050 = 0 + (op<<1)  + (op<<4)  + (op<<5) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:228: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[85] <= (-(MUL050(yi[175:168]))&255) - (-(MUL050(yi[175:168])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:439: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL011 = 0 + op     + (op<<1)  + (op<<3) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:439: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL011 = 0 + op     + (op<<1)  + (op<<3) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:439: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL011 = 0 + op     + (op<<1)  + (op<<3) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:229: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[86] <= (-(MUL011(yi[183:176]))&255) - (-(MUL011(yi[183:176])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:446: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL013 = 0 + op     + (op<<2)  + (op<<3) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:446: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL013 = 0 + op     + (op<<2)  + (op<<3) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:446: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL013 = 0 + op     + (op<<2)  + (op<<3) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:230: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[87] <= ((MUL013(yi[191:184]))&255) - ((MUL013(yi[191:184])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:453: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL008 = 0 + (op<<3) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:231: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[88] <= ((MUL008(yi[199:192]))&255) - ((MUL008(yi[199:192])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:460: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL084 = 0 + (op<<2)  + (op<<4)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:460: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL084 = 0 + (op<<2)  + (op<<4)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:460: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL084 = 0 + (op<<2)  + (op<<4)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:232: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[89] <= ((MUL084(yi[207:200]))&255) - ((MUL084(yi[207:200])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:467: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL111 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:467: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL111 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:467: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL111 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:467: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL111 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5)  + (op<<6) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:467: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL111 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5)  + (op<<6) ;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:467: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL111 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5)  + (op<<6) ;\n                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:233: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[90] <= ((MUL111(yi[215:208]))&255) - ((MUL111(yi[215:208])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:474: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL009 = 0 + op     + (op<<3) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:474: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL009 = 0 + op     + (op<<3) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:234: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[91] <= ((MUL009(yi[223:216]))&255) - ((MUL009(yi[223:216])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:481: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL034 = 0 + (op<<1)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:481: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL034 = 0 + (op<<1)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:235: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[92] <= (-(MUL034(yi[231:224]))&255) - (-(MUL034(yi[231:224])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:488: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL100 = 0 + (op<<2)  + (op<<5)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:488: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL100 = 0 + (op<<2)  + (op<<5)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:488: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL100 = 0 + (op<<2)  + (op<<5)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:236: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[93] <= (-(MUL100(yi[239:232]))&255) - (-(MUL100(yi[239:232])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:495: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL022 = 0 + (op<<1)  + (op<<2)  + (op<<4) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:495: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL022 = 0 + (op<<1)  + (op<<2)  + (op<<4) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:495: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL022 = 0 + (op<<1)  + (op<<2)  + (op<<4) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:237: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[94] <= (-(MUL022(yi[247:240]))&255) - (-(MUL022(yi[247:240])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:502: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL026 = 0 + (op<<1)  + (op<<3)  + (op<<4) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:502: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL026 = 0 + (op<<1)  + (op<<3)  + (op<<4) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:502: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL026 = 0 + (op<<1)  + (op<<3)  + (op<<4) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:238: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[95] <= ((MUL026(yi[255:248]))&255) - ((MUL026(yi[255:248])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:509: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL016 = 0 + (op<<4) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:239: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[96] <= ((MUL016(yi[263:256]))&255) - ((MUL016(yi[263:256])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:516: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL089 = 0 + op     + (op<<3)  + (op<<4)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:516: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL089 = 0 + op     + (op<<3)  + (op<<4)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:516: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL089 = 0 + op     + (op<<3)  + (op<<4)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:516: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL089 = 0 + op     + (op<<3)  + (op<<4)  + (op<<6) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:240: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[97] <= (-(MUL089(yi[271:264]))&255) - (-(MUL089(yi[271:264])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:523: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL035 = 0 + op     + (op<<1)  + (op<<5) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:523: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL035 = 0 + op     + (op<<1)  + (op<<5) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:523: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL035 = 0 + op     + (op<<1)  + (op<<5) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:241: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[98] <= (-(MUL035(yi[279:272]))&255) - (-(MUL035(yi[279:272])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:530: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL018 = 0 + (op<<1)  + (op<<4) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:530: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL018 = 0 + (op<<1)  + (op<<4) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:242: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[99] <= ((MUL018(yi[287:280]))&255) - ((MUL018(yi[287:280])) >>> 8);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:537: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL068 = 0 + (op<<2)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:537: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL068 = 0 + (op<<2)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:243: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[100] <= (-(MUL068(yi[295:288]))&255) - (-(MUL068(yi[295:288])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:544: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL057 = 0 + op     + (op<<3)  + (op<<4)  + (op<<5) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:544: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL057 = 0 + op     + (op<<3)  + (op<<4)  + (op<<5) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:544: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL057 = 0 + op     + (op<<3)  + (op<<4)  + (op<<5) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:544: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL057 = 0 + op     + (op<<3)  + (op<<4)  + (op<<5) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:244: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[101] <= ((MUL057(yi[303:296]))&255) - ((MUL057(yi[303:296])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:551: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL044 = 0 + (op<<2)  + (op<<3)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:551: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL044 = 0 + (op<<2)  + (op<<3)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:551: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL044 = 0 + (op<<2)  + (op<<3)  + (op<<5) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:245: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[102] <= (-(MUL044(yi[311:304]))&255) - (-(MUL044(yi[311:304])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:558: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL052 = 0 + (op<<2)  + (op<<4)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:558: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL052 = 0 + (op<<2)  + (op<<4)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:558: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL052 = 0 + (op<<2)  + (op<<4)  + (op<<5) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:246: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[103] <= ((MUL052(yi[319:312]))&255) - ((MUL052(yi[319:312])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:565: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL032 = 0 + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:247: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[104] <= ((MUL032(yi[327:320]))&255) - ((MUL032(yi[327:320])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:572: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL079 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:572: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL079 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:572: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL079 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:572: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL079 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<6) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:572: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL079 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<6) ;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:248: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[105] <= ((MUL079(yi[335:328]))&255) - ((MUL079(yi[335:328])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:579: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL070 = 0 + (op<<1)  + (op<<2)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:579: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL070 = 0 + (op<<1)  + (op<<2)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:579: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL070 = 0 + (op<<1)  + (op<<2)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:249: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[106] <= (-(MUL070(yi[343:336]))&255) - (-(MUL070(yi[343:336])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:586: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL036 = 0 + (op<<2)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:586: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL036 = 0 + (op<<2)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:250: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[107] <= ((MUL036(yi[351:344]))&255) - ((MUL036(yi[351:344])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:593: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL121 = 0 + op     + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:593: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL121 = 0 + op     + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:593: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL121 = 0 + op     + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:593: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL121 = 0 + op     + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:593: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL121 = 0 + op     + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:251: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[108] <= ((MUL121(yi[359:352]))&255) - ((MUL121(yi[359:352])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:600: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL114 = 0 + (op<<1)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:600: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL114 = 0 + (op<<1)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:600: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL114 = 0 + (op<<1)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:600: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL114 = 0 + (op<<1)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:252: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[109] <= ((MUL114(yi[367:360]))&255) - ((MUL114(yi[367:360])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:607: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL088 = 0 + (op<<3)  + (op<<4)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:607: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL088 = 0 + (op<<3)  + (op<<4)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:607: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL088 = 0 + (op<<3)  + (op<<4)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:253: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[110] <= (-(MUL088(yi[375:368]))&255) - (-(MUL088(yi[375:368])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:614: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL104 = 0 + (op<<3)  + (op<<5)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:614: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL104 = 0 + (op<<3)  + (op<<5)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:614: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL104 = 0 + (op<<3)  + (op<<5)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:254: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[111] <= ((MUL104(yi[383:376]))&255) - ((MUL104(yi[383:376])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:621: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL064 = 0 + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:255: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[112] <= ((MUL064(yi[391:384]))&255) - ((MUL064(yi[391:384])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:628: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL099 = 0 + op     + (op<<1)  + (op<<5)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:628: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL099 = 0 + op     + (op<<1)  + (op<<5)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:628: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL099 = 0 + op     + (op<<1)  + (op<<5)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:628: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL099 = 0 + op     + (op<<1)  + (op<<5)  + (op<<6) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:256: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[113] <= (-(MUL099(yi[399:392]))&255) - (-(MUL099(yi[399:392])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:635: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL117 = 0 + op     + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:635: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL117 = 0 + op     + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:635: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL117 = 0 + op     + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:635: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL117 = 0 + op     + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:635: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL117 = 0 + op     + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:257: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[114] <= ((MUL117(yi[407:400]))&255) - ((MUL117(yi[407:400])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:642: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL072 = 0 + (op<<3)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:642: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL072 = 0 + (op<<3)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:258: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[115] <= ((MUL072(yi[415:408]))&255) - ((MUL072(yi[415:408])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:649: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL015 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:649: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL015 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:649: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL015 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:649: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL015 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:259: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[116] <= (-(MUL015(yi[423:416]))&255) - (-(MUL015(yi[423:416])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:656: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL029 = 0 + op     + (op<<2)  + (op<<3)  + (op<<4) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:656: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL029 = 0 + op     + (op<<2)  + (op<<3)  + (op<<4) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:656: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL029 = 0 + op     + (op<<2)  + (op<<3)  + (op<<4) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:656: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL029 = 0 + op     + (op<<2)  + (op<<3)  + (op<<4) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:260: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[117] <= (-(MUL029(yi[431:424]))&255) - (-(MUL029(yi[431:424])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:663: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL081 = 0 + op     + (op<<4)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:663: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL081 = 0 + op     + (op<<4)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:663: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL081 = 0 + op     + (op<<4)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:261: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[118] <= ((MUL081(yi[439:432]))&255) - ((MUL081(yi[439:432])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:670: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL049 = 0 + op     + (op<<4)  + (op<<5) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:670: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL049 = 0 + op     + (op<<4)  + (op<<5) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:670: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL049 = 0 + op     + (op<<4)  + (op<<5) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:262: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[119] <= (-(MUL049(yi[447:440]))&255) - (-(MUL049(yi[447:440])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:677: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL128 = 0 + (op<<7) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:263: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[120] <= ((MUL128(yi[455:448]))&255) - ((MUL128(yi[455:448])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:684: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL059 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:684: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL059 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:684: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL059 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:684: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL059 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:684: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL059 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:264: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[121] <= ((MUL059(yi[463:456]))&255) - ((MUL059(yi[463:456])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:691: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL023 = 0 + op     + (op<<1)  + (op<<2)  + (op<<4) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:691: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL023 = 0 + op     + (op<<1)  + (op<<2)  + (op<<4) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:691: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL023 = 0 + op     + (op<<1)  + (op<<2)  + (op<<4) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:691: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL023 = 0 + op     + (op<<1)  + (op<<2)  + (op<<4) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:265: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[122] <= (-(MUL023(yi[471:464]))&255) - (-(MUL023(yi[471:464])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:698: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL113 = 0 + op     + (op<<4)  + (op<<5)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:698: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL113 = 0 + op     + (op<<4)  + (op<<5)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:698: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL113 = 0 + op     + (op<<4)  + (op<<5)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:698: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL113 = 0 + op     + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:266: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[123] <= (-(MUL113(yi[479:472]))&255) - (-(MUL113(yi[479:472])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:705: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL030 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:705: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL030 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:705: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL030 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:705: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL030 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:267: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[124] <= (-(MUL030(yi[487:480]))&255) - (-(MUL030(yi[487:480])) >>> 8);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:269: Operator SUB expects 32 or 16 bits on the LHS, but LHS\'s REPLICATE generates 10 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[125] <= (Final == 1) ? {2\'b0,yReg128_125_inter[7:0]} - {{2{yReg128_125_inter[15]}},yReg128_125_inter[15:8]} : ((-(MUL058({1\'b0,yi[495:488]}))&255) - (-(MUL058({1\'b0,yi[495:488]})) >>> 8));   \n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:269: Operator SUB expects 32 or 16 bits on the RHS, but RHS\'s REPLICATE generates 10 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[125] <= (Final == 1) ? {2\'b0,yReg128_125_inter[7:0]} - {{2{yReg128_125_inter[15]}},yReg128_125_inter[15:8]} : ((-(MUL058({1\'b0,yi[495:488]}))&255) - (-(MUL058({1\'b0,yi[495:488]})) >>> 8));   \n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:269: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[125] <= (Final == 1) ? {2\'b0,yReg128_125_inter[7:0]} - {{2{yReg128_125_inter[15]}},yReg128_125_inter[15:8]} : ((-(MUL058({1\'b0,yi[495:488]}))&255) - (-(MUL058({1\'b0,yi[495:488]})) >>> 8));   \n                ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:719: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL095 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:719: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL095 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:719: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL095 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:719: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL095 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:719: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL095 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:719: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 8 bits.\n                                                                                : ... In instance FFT_128\n  MUL095 = 0 + op     + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_128.v:270: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                                : ... In instance FFT_128\n   yReg128[126] <= (-(MUL095(yi[503:496]))&255) - (-(MUL095(yi[503:496])) >>> 8);\n                ^~\n%Error: Exiting due to 1 error(s), 364 warning(s)\n'
function signed [15:0] MUL084;
	  input [7:0] op;
	  begin
		MUL084 = 0 + (op<<2)  + (op<<4)  + (op<<6) ;
	  end
	endfunction
function signed [15:0] MUL084;

	  input [7:0] op;
	  begin
		MUL084 = 0 + (op<<2)  + (op<<4)  + (op<<6) ;
	  end
	endfunction