data/full_repos/permissive/161029703/src/cpu/stage_id/reg_val_mux.v
1: b'%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/reg_val_mux.v:1: Cannot find include file: ../defs.v\n`include "../defs.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161029703/src/cpu/stage_id,data/full_repos/permissive/161029703/../defs.v\n             data/full_repos/permissive/161029703/src/cpu/stage_id,data/full_repos/permissive/161029703/../defs.v.v\n             data/full_repos/permissive/161029703/src/cpu/stage_id,data/full_repos/permissive/161029703/../defs.v.sv\n             ../defs.v\n             ../defs.v.v\n             ../defs.v.sv\n             obj_dir/../defs.v\n             obj_dir/../defs.v.v\n             obj_dir/../defs.v.sv\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/reg_val_mux.v:39: Define or directive not defined: \'`ACCESS_OP_D2R\'\n    else if(reg_addr == addr_from_ex && access_op_from_ex == `ACCESS_OP_D2R)\n                                                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/reg_val_mux.v:39: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    else if(reg_addr == addr_from_ex && access_op_from_ex == `ACCESS_OP_D2R)\n                                                                           ^\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/reg_val_mux.v:41: Define or directive not defined: \'`ACCESS_OP_D2R\'\n    else if(reg_addr == addr_from_mm && (access_op_from_mm == `ACCESS_OP_D2R || access_op_from_mm == `ACCESS_OP_M2R))\n                                                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/reg_val_mux.v:41: Define or directive not defined: \'`ACCESS_OP_M2R\'\n    else if(reg_addr == addr_from_mm && (access_op_from_mm == `ACCESS_OP_D2R || access_op_from_mm == `ACCESS_OP_M2R))\n                                                                                                     ^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module reg_val_mux(

         value_o,

         reg_addr,
         value_from_regs,
         addr_from_ex,
         value_from_ex,
         access_op_from_ex,
         addr_from_mm,
         value_from_mm,
         access_op_from_mm,
         addr_from_wb,
         value_from_wb,
         write_enable_from_wb);

input wire[4:0] reg_addr;

input wire[31:0] value_from_regs;

input wire[4:0] addr_from_ex;
input wire[31:0] value_from_ex;
input wire[1:0] access_op_from_ex;

input wire[4:0] addr_from_mm;
input wire[31:0] value_from_mm;
input wire[1:0] access_op_from_mm;

input wire[4:0] addr_from_wb;
input wire[31:0] value_from_wb;
input wire write_enable_from_wb;

output reg[31:0] value_o;

always @(*) begin
    if(reg_addr == 5'b0)
        value_o <= 32'b0;
    else if(reg_addr == addr_from_ex && access_op_from_ex == `ACCESS_OP_D2R)
        value_o <= value_from_ex;
    else if(reg_addr == addr_from_mm && (access_op_from_mm == `ACCESS_OP_D2R || access_op_from_mm == `ACCESS_OP_M2R))
        value_o <= value_from_mm;
    else if(reg_addr == addr_from_wb && write_enable_from_wb)
        value_o <= value_from_wb;
    else
        value_o <= value_from_regs;
end

endmodule
module reg_val_mux(

         value_o,

         reg_addr,
         value_from_regs,
         addr_from_ex,
         value_from_ex,
         access_op_from_ex,
         addr_from_mm,
         value_from_mm,
         access_op_from_mm,
         addr_from_wb,
         value_from_wb,
         write_enable_from_wb);


input wire[4:0] reg_addr;

input wire[31:0] value_from_regs;

input wire[4:0] addr_from_ex;
input wire[31:0] value_from_ex;
input wire[1:0] access_op_from_ex;

input wire[4:0] addr_from_mm;
input wire[31:0] value_from_mm;
input wire[1:0] access_op_from_mm;

input wire[4:0] addr_from_wb;
input wire[31:0] value_from_wb;
input wire write_enable_from_wb;

output reg[31:0] value_o;

always @(*) begin
    if(reg_addr == 5'b0)
        value_o <= 32'b0;
    else if(reg_addr == addr_from_ex && access_op_from_ex == `ACCESS_OP_D2R)
        value_o <= value_from_ex;
    else if(reg_addr == addr_from_mm && (access_op_from_mm == `ACCESS_OP_D2R || access_op_from_mm == `ACCESS_OP_M2R))
        value_o <= value_from_mm;
    else if(reg_addr == addr_from_wb && write_enable_from_wb)
        value_o <= value_from_wb;
    else
        value_o <= value_from_regs;
end

endmodule