data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v
 line:23: before: "("
1: b'%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:10: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wrr.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:11: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:23: Unsupported: Ignoring delay on this delayed statement.\n    repeat(2) #250 CLK_2MHz = ~CLK_2MHz;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #250\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:25: Unsupported: Ignoring delay on this delayed statement.\n    forever #250 CLK_2MHz = ~CLK_2MHz;\n            ^\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:33: syntax error, unexpected \'@\'\n    @(posedge reset)\n    ^\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:38: syntax error, unexpected \'@\'\n    repeat(2) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:42: syntax error, unexpected \'@\'\n    repeat(2) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:46: syntax error, unexpected \'@\'\n    repeat(2) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:50: syntax error, unexpected \'@\'\n    repeat(2) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:53: syntax error, unexpected \'@\'\n    repeat(6) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:56: syntax error, unexpected \'@\'\n    repeat(8) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:59: syntax error, unexpected \'@\'\n    repeat(2) @(posedge CLK_2MHz);\n              ^\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:62: syntax error, unexpected \'@\'\n    repeat(10) @(posedge CLK_2MHz);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/wrr/tester.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #500 $finish;\n    ^\n%Error: Exiting due to 11 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester(      output reg  [2:0]   weight_assign,
                    output reg  [1:0]   vc_assign,
                    output reg          CLK_2MHz, reset, edit_weight,
                    output reg  [3:0]   Data_Word
                    );

  initial begin
    $dumpfile("wrr.vcd");
    $dumpvars;
  end

  initial begin
    vc_assign = 2'b00;
    weight_assign = 3'b000;
    Data_Word = 4'b0000;
    CLK_2MHz = 1'b0;
    reset = 1'b0;
    edit_weight = 1'b0;

    #250
    repeat(2) #250 CLK_2MHz = ~CLK_2MHz;
    reset = 1'b1;
    forever #250 CLK_2MHz = ~CLK_2MHz;
  end

  always @ (posedge CLK_2MHz) begin
    Data_Word = Data_Word + 1;
  end

  initial begin
    @(posedge reset)
    edit_weight = 1'b1;

    vc_assign = 2'b00;
    weight_assign = 3'b011;
    repeat(2) @(posedge CLK_2MHz);

    vc_assign = 2'b01;
    weight_assign = 3'b100;
    repeat(2) @(posedge CLK_2MHz);

    vc_assign = 2'b10;
    weight_assign = 3'b001;
    repeat(2) @(posedge CLK_2MHz);

    vc_assign = 2'b11;
    weight_assign = 3'b010;
    repeat(2) @(posedge CLK_2MHz);
    edit_weight = 1'b0;
    vc_assign = 2'b00;
    repeat(6) @(posedge CLK_2MHz);

    vc_assign = 2'b01;
    repeat(8) @(posedge CLK_2MHz);

    vc_assign = 2'b10;
    repeat(2) @(posedge CLK_2MHz);

    vc_assign = 2'b11;
    repeat(10) @(posedge CLK_2MHz);
    #500 $finish;
  end

endmodule
module tester(      output reg  [2:0]   weight_assign,
                    output reg  [1:0]   vc_assign,
                    output reg          CLK_2MHz, reset, edit_weight,
                    output reg  [3:0]   Data_Word
                    );


  initial begin
    $dumpfile("wrr.vcd");
    $dumpvars;
  end

  initial begin
    vc_assign = 2'b00;
    weight_assign = 3'b000;
    Data_Word = 4'b0000;
    CLK_2MHz = 1'b0;
    reset = 1'b0;
    edit_weight = 1'b0;

    #250
    repeat(2) #250 CLK_2MHz = ~CLK_2MHz;
    reset = 1'b1;
    forever #250 CLK_2MHz = ~CLK_2MHz;
  end

  always @ (posedge CLK_2MHz) begin
    Data_Word = Data_Word + 1;
  end

  initial begin
    @(posedge reset)
    edit_weight = 1'b1;

    vc_assign = 2'b00;
    weight_assign = 3'b011;
    repeat(2) @(posedge CLK_2MHz);

    vc_assign = 2'b01;
    weight_assign = 3'b100;
    repeat(2) @(posedge CLK_2MHz);

    vc_assign = 2'b10;
    weight_assign = 3'b001;
    repeat(2) @(posedge CLK_2MHz);

    vc_assign = 2'b11;
    weight_assign = 3'b010;
    repeat(2) @(posedge CLK_2MHz);
    edit_weight = 1'b0;
    vc_assign = 2'b00;
    repeat(6) @(posedge CLK_2MHz);

    vc_assign = 2'b01;
    repeat(8) @(posedge CLK_2MHz);

    vc_assign = 2'b10;
    repeat(2) @(posedge CLK_2MHz);

    vc_assign = 2'b11;
    repeat(10) @(posedge CLK_2MHz);
    #500 $finish;
  end

endmodule