data/full_repos/permissive/103649428/VendingMachine.v
1: b'%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:359: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hfd\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                            AN[7:0] <= 9\'b11111101;\n                                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:407: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                                        AN[7:0] <= 9\'b11011111;\n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:427: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                                    AN[7:0] <= 9\'b11011111;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:447: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                                    AN[7:0] <= 9\'b11011111;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:467: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                                    AN[7:0] <= 9\'b11011111;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:487: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                                    AN[7:0] <= 9\'b11011111;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:507: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                                    AN[7:0] <= 9\'b11011111;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:532: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                                    AN[7:0] <= 9\'b11011111;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:672: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                                 AN[7:0] <= 9\'b01111111;\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:715: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                                 AN[7:0] <= 9\'b01111111;\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:734: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                                 AN[7:0] = 9\'b01111111;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:753: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n                                                                         : ... In instance VendingMachine.show\n                                 AN[7:0] = 9\'b01111111;\n                                         ^\n%Error: Exiting due to 12 warning(s)\n'
module Time(state, clk, hasBuy, drinktk_ind, over);
    input clk, hasBuy;
    input [2:0]state;
    output reg drinktk_ind, over;
    reg [31:0]cnt;

    initial begin
        drinktk_ind <= 0;
        cnt <= 0;
        over <= 0;
    end

    always@(posedge clk) begin
        if (state == 5) begin
            if(hasBuy)
                drinktk_ind = 1;
            else
                drinktk_ind = 0;
            if(cnt == 300_000_000) begin
                cnt = 0;
                over = 1;
            end
            else begin
                cnt = cnt + 1;
                over = 0;
            end     
        end
        else begin
            drinktk_ind <= 0; 
            over <= 0;
        end
    end 
endmodule
module Time(state, clk, hasBuy, drinktk_ind, over);

    input clk, hasBuy;
    input [2:0]state;
    output reg drinktk_ind, over;
    reg [31:0]cnt;

    initial begin
        drinktk_ind <= 0;
        cnt <= 0;
        over <= 0;
    end

    always@(posedge clk) begin
        if (state == 5) begin
            if(hasBuy)
                drinktk_ind = 1;
            else
                drinktk_ind = 0;
            if(cnt == 300_000_000) begin
                cnt = 0;
                over = 1;
            end
            else begin
                cnt = cnt + 1;
                over = 0;
            end     
        end
        else begin
            drinktk_ind <= 0; 
            over <= 0;
        end
    end 
endmodule