data/full_repos/permissive/139767240/IntelReferenceDesign/counter.v
data/verilator_xmls/3b19818c-9e90-4392-8337-8be8c0e864ee.xml
module counter
(
	clk,
	reset,
	result,
	ena
);

	input clk;
	input reset;
	input ena;
	output [7:0] result;

	reg [7:0] result;

	always @(posedge clk or posedge reset)
	begin
		if (reset) 
			result = 0;		
		else if (ena) 
			result = result + 1;
	end
endmodule
module counter
(
	clk,
	reset,
	result,
	ena
);


	input clk;
	input reset;
	input ena;
	output [7:0] result;

	reg [7:0] result;

	always @(posedge clk or posedge reset)
	begin
		if (reset) 
			result = 0;		
		else if (ena) 
			result = result + 1;
	end
endmodule