data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_decrypted_data.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_decrypted_data.sv:15: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_decrypted_data.sv:17: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_decrypted_data.sv:31: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_decrypted_data.sv:35: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_decrypted_data.sv:40: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_decrypted_data.sv:44: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_decrypted_data.sv:49: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_decrypted_data.sv:53: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_decrypted_data.sv:58: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_decrypted_data.sv:62: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_RC4_CORE_decrypted_data();
	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg tb_enable_write_i;
	reg [1:0] tb_writeLoc_i;
	reg [7:0] tb_data_i;
	reg [31:0] tb_rc4_wdata_o;


	RC4_CORE_decrypted_data DUT (.clk(tb_clk),.enable_write_i(tb_enable_write_i),.writeLoc_i(tb_writeLoc_i),.data_i(tb_data_i),.rc4_wdata_o(tb_rc4_wdata_o));

initial
begin

	@(negedge tb_clk);
	tb_enable_write_i = 0;
	tb_writeLoc_i = 2;
	tb_data_i = "S";
	@(negedge tb_clk);
	tb_enable_write_i = 1;
	tb_writeLoc_i = 0;
	tb_data_i = "D";

	@(negedge tb_clk);
	tb_enable_write_i = 0;
	tb_writeLoc_i = 2;
	tb_data_i = "S";
	@(negedge tb_clk);
	tb_enable_write_i = 1;
	tb_writeLoc_i = 1;
	tb_data_i = "i";

	@(negedge tb_clk);
	tb_enable_write_i = 0;
	tb_writeLoc_i = 2;
	tb_data_i = "m";
	@(negedge tb_clk);
	tb_enable_write_i = 1;
	tb_writeLoc_i = 2;
	tb_data_i = "m";

	@(negedge tb_clk);
	tb_enable_write_i = 1;
	tb_writeLoc_i = 3;
	tb_data_i = "c";
	@(negedge tb_clk);
	tb_enable_write_i = 1;
	tb_writeLoc_i = 0;
	tb_data_i = "D";


end
endmodule
module tb_RC4_CORE_decrypted_data();

	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg tb_enable_write_i;
	reg [1:0] tb_writeLoc_i;
	reg [7:0] tb_data_i;
	reg [31:0] tb_rc4_wdata_o;


	RC4_CORE_decrypted_data DUT (.clk(tb_clk),.enable_write_i(tb_enable_write_i),.writeLoc_i(tb_writeLoc_i),.data_i(tb_data_i),.rc4_wdata_o(tb_rc4_wdata_o));

initial
begin

	@(negedge tb_clk);
	tb_enable_write_i = 0;
	tb_writeLoc_i = 2;
	tb_data_i = "S";
	@(negedge tb_clk);
	tb_enable_write_i = 1;
	tb_writeLoc_i = 0;
	tb_data_i = "D";

	@(negedge tb_clk);
	tb_enable_write_i = 0;
	tb_writeLoc_i = 2;
	tb_data_i = "S";
	@(negedge tb_clk);
	tb_enable_write_i = 1;
	tb_writeLoc_i = 1;
	tb_data_i = "i";

	@(negedge tb_clk);
	tb_enable_write_i = 0;
	tb_writeLoc_i = 2;
	tb_data_i = "m";
	@(negedge tb_clk);
	tb_enable_write_i = 1;
	tb_writeLoc_i = 2;
	tb_data_i = "m";

	@(negedge tb_clk);
	tb_enable_write_i = 1;
	tb_writeLoc_i = 3;
	tb_data_i = "c";
	@(negedge tb_clk);
	tb_enable_write_i = 1;
	tb_writeLoc_i = 0;
	tb_data_i = "D";


end
endmodule