data/full_repos/permissive/140495330/src/hdl/top.v
1: b'%Error: data/full_repos/permissive/140495330/src/hdl/top.v:21: Cannot find file containing module: \'clk_wiz_0\'\n    clk_wiz_0 clk_wiz (\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/140495330/src/hdl,data/full_repos/permissive/140495330/clk_wiz_0\n             data/full_repos/permissive/140495330/src/hdl,data/full_repos/permissive/140495330/clk_wiz_0.v\n             data/full_repos/permissive/140495330/src/hdl,data/full_repos/permissive/140495330/clk_wiz_0.sv\n             clk_wiz_0\n             clk_wiz_0.v\n             clk_wiz_0.sv\n             obj_dir/clk_wiz_0\n             obj_dir/clk_wiz_0.v\n             obj_dir/clk_wiz_0.sv\n%Error: data/full_repos/permissive/140495330/src/hdl/top.v:30: Cannot find file containing module: \'debouncer\'\n    debouncer #(.WIDTH(1)) db (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/140495330/src/hdl/top.v:69: Cannot find file containing module: \'PiSimulator_VGA\'\n    PiSimulator_VGA pisim_vga (\n    ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/140495330/src/hdl/top.v:86: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'21\'h0\' generates 21 bits.\n                                                                     : ... In instance top\n            clk_div <= 21\'b0;\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/140495330/src/hdl/top.v:117: Cannot find file containing module: \'lfsr18\'\n    lfsr18 lfsr (\n    ^~~~~~\n%Error: data/full_repos/permissive/140495330/src/hdl/top.v:134: Cannot find file containing module: \'pixelMemory\'\n    pixelMemory px_mem (\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/140495330/src/hdl/top.v:150: Cannot find file containing module: \'circleChecker\'\n    circleChecker cc (.isInside(isInside), .xCoord(px_x), .yCoord(px_y_inv));\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module top (
   output wire [4:1] ja_p,
   output wire [4:1] ja_n,
   output wire [3:1] jb_p,
   output wire [3:1] jb_n,
   input  wire [1:0] btn,
   output wire [1:0] led,
   input  wire       clk
   
   ,output wire [1:0] led_r
);
    

    wire mem_reset_done;
    wire mem_reset = btn[0];
    wire reset = mem_reset | ~mem_reset_done;



    wire clk25, clk10;
    clk_wiz_0 clk_wiz (
        .clk_out1(clk25),
        .clk_out2(clk10),
        .clk_in1(clk)
    );


    wire db_btn1;
    reg _db_btn1 = 0;
    debouncer #(.WIDTH(1)) db (
        .clk(clk10),
        .din(btn[1]),
        .dout(db_btn1)
    );
    reg [1:0] sw = 0;
    always@(posedge clk10)
        _db_btn1 <= db_btn1;
    
    always@(posedge clk10)
        if (db_btn1 == 1 && _db_btn1 == 0)
            sw <= sw + 1;
    assign led = sw;
    

   wire [3:0] r;
   wire [3:0] g;
   wire [3:0] b;
   wire       HS, VS;

   assign ja_p[1] = r[0];
   assign ja_n[1] = r[1];
   assign ja_p[2] = r[2];
   assign ja_n[2] = r[3];
   assign ja_p[3] = g[0];
   assign ja_n[3] = g[1];
   assign ja_p[4] = g[2];
   assign ja_n[4] = g[3];

   assign jb_p[1] = b[0];
   assign jb_n[1] = b[1];
   assign jb_p[2] = b[2];
   assign jb_n[2] = b[3];
   assign jb_p[3] = HS;
   assign jb_n[3] = VS;


    wire [9:0] px_x, px_y;
    wire vidSel;
    PiSimulator_VGA pisim_vga (
        .HS(HS),
        .VS(VS),
        .px_x(px_x),
        .px_y(px_y),
        .vidSel(vidSel),
        .clk25(clk25)
    );


    reg [15:0] clk_div;
    reg  [3:0] en, en_delay;
    wire [3:0] en_wide;
    assign en_wide = en | en_delay;

    always @ (posedge clk10) begin
        if (reset)
            clk_div <= 21'b0;
        else
            clk_div <= clk_div + 1'b1;
    
        if (clk_div == 16'h8000)
            en[0] <= 1'b1;
        else
            en[0] <= 1'b0;
    
        if (clk_div[13:0] == 14'h2000)
            en[1] <= 1'b1;
        else
            en[1] <= 1'b0;
    
        if (clk_div[11:0] == 12'h800)
            en[2] <= 1'b1;
        else
            en[2] <= 1'b0;
    
        if (clk_div[9:0] == 10'h200)
            en[3] <= 1'b1;
        else
            en[3] <= 1'b0;
    
        en_delay <= en;
    end

    wire en_lfsr = en_wide[sw];
   

    wire [17:0] q;
    lfsr18 lfsr (
        .q(q),
        .seed(18'h0_AACC),
        .enable(en_lfsr & clk_div[0]),
        .clk(clk10),
        .reset(reset)
    );
    wire [8:0] rand_x = q[17:9];
    wire [8:0] rand_y = q[8:0];

    reg [9:0] px_y_inv;
    always @ (*) begin
        px_y_inv = 10'd480 - px_y;
    end
    

    wire color;
    pixelMemory px_mem (
        .read_clk(clk25),
        .read_x(px_x),
        .read_y(px_y_inv),
        .read_color(color),
        
        .write_clk(clk10),
        .write_x(rand_x),
        .write_y(rand_y),
        .wr_enable(1'b1),
        
        .reset(mem_reset),
        .reset_done(mem_reset_done)
    );

    wire isInside;
    circleChecker cc (.isInside(isInside), .xCoord(px_x), .yCoord(px_y_inv));

    reg [11:0] color_sel;
    always@(isInside, color, px_x)
        if (isInside)
            if (color)
                color_sel = 12'hF00;
            else
                color_sel = 12'hCCC;
        else
            if (color && px_x <= 480)
                color_sel = 12'h0F0;
            else
                color_sel = 12'h000;
    assign {r,g,b} = (vidSel) ? (color_sel) : (12'h0);
endmodule
module top (
   output wire [4:1] ja_p,
   output wire [4:1] ja_n,
   output wire [3:1] jb_p,
   output wire [3:1] jb_n,
   input  wire [1:0] btn,
   output wire [1:0] led,
   input  wire       clk
   
   ,output wire [1:0] led_r
);

    

    wire mem_reset_done;
    wire mem_reset = btn[0];
    wire reset = mem_reset | ~mem_reset_done;



    wire clk25, clk10;
    clk_wiz_0 clk_wiz (
        .clk_out1(clk25),
        .clk_out2(clk10),
        .clk_in1(clk)
    );


    wire db_btn1;
    reg _db_btn1 = 0;
    debouncer #(.WIDTH(1)) db (
        .clk(clk10),
        .din(btn[1]),
        .dout(db_btn1)
    );
    reg [1:0] sw = 0;
    always@(posedge clk10)
        _db_btn1 <= db_btn1;
    
    always@(posedge clk10)
        if (db_btn1 == 1 && _db_btn1 == 0)
            sw <= sw + 1;
    assign led = sw;
    

   wire [3:0] r;
   wire [3:0] g;
   wire [3:0] b;
   wire       HS, VS;

   assign ja_p[1] = r[0];
   assign ja_n[1] = r[1];
   assign ja_p[2] = r[2];
   assign ja_n[2] = r[3];
   assign ja_p[3] = g[0];
   assign ja_n[3] = g[1];
   assign ja_p[4] = g[2];
   assign ja_n[4] = g[3];

   assign jb_p[1] = b[0];
   assign jb_n[1] = b[1];
   assign jb_p[2] = b[2];
   assign jb_n[2] = b[3];
   assign jb_p[3] = HS;
   assign jb_n[3] = VS;


    wire [9:0] px_x, px_y;
    wire vidSel;
    PiSimulator_VGA pisim_vga (
        .HS(HS),
        .VS(VS),
        .px_x(px_x),
        .px_y(px_y),
        .vidSel(vidSel),
        .clk25(clk25)
    );


    reg [15:0] clk_div;
    reg  [3:0] en, en_delay;
    wire [3:0] en_wide;
    assign en_wide = en | en_delay;

    always @ (posedge clk10) begin
        if (reset)
            clk_div <= 21'b0;
        else
            clk_div <= clk_div + 1'b1;
    
        if (clk_div == 16'h8000)
            en[0] <= 1'b1;
        else
            en[0] <= 1'b0;
    
        if (clk_div[13:0] == 14'h2000)
            en[1] <= 1'b1;
        else
            en[1] <= 1'b0;
    
        if (clk_div[11:0] == 12'h800)
            en[2] <= 1'b1;
        else
            en[2] <= 1'b0;
    
        if (clk_div[9:0] == 10'h200)
            en[3] <= 1'b1;
        else
            en[3] <= 1'b0;
    
        en_delay <= en;
    end

    wire en_lfsr = en_wide[sw];
   

    wire [17:0] q;
    lfsr18 lfsr (
        .q(q),
        .seed(18'h0_AACC),
        .enable(en_lfsr & clk_div[0]),
        .clk(clk10),
        .reset(reset)
    );
    wire [8:0] rand_x = q[17:9];
    wire [8:0] rand_y = q[8:0];

    reg [9:0] px_y_inv;
    always @ (*) begin
        px_y_inv = 10'd480 - px_y;
    end
    

    wire color;
    pixelMemory px_mem (
        .read_clk(clk25),
        .read_x(px_x),
        .read_y(px_y_inv),
        .read_color(color),
        
        .write_clk(clk10),
        .write_x(rand_x),
        .write_y(rand_y),
        .wr_enable(1'b1),
        
        .reset(mem_reset),
        .reset_done(mem_reset_done)
    );

    wire isInside;
    circleChecker cc (.isInside(isInside), .xCoord(px_x), .yCoord(px_y_inv));

    reg [11:0] color_sel;
    always@(isInside, color, px_x)
        if (isInside)
            if (color)
                color_sel = 12'hF00;
            else
                color_sel = 12'hCCC;
        else
            if (color && px_x <= 480)
                color_sel = 12'h0F0;
            else
                color_sel = 12'h000;
    assign {r,g,b} = (vidSel) ? (color_sel) : (12'h0);
endmodule