data/full_repos/permissive/181665138/verilog/capitolo_v/ContatoreUp_Ncifre_Base2.v
 line:35: before: "=="
1: b'%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/ContatoreUp_Ncifre_Base2.v:35: syntax error, unexpected ==, expecting \')\' or \',\' or or\n    always @(reset_ == 0) #1 OUTR<=0;\n                    ^~\n%Warning-STMTDLY: data/full_repos/permissive/181665138/verilog/capitolo_v/ContatoreUp_Ncifre_Base2.v:37: Unsupported: Ignoring delay on this delayed statement.\n    always @(posedge clock) if (reset_ == 1) #3 OUTR <= numero + 1;\n                                             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module ContatoreUp_Ncifre_Base2(numero, clock, reset_);
    parameter N = 10;

    input clock, reset_;
    output [N-1:0] numero;

    reg [N-1:0] OUTR;
    assign numero=OUTR;

    always @(reset_ == 0) #1 OUTR<=0;

    always @(posedge clock) if (reset_ == 1) #3 OUTR <= numero + 1;
endmodule
module ContatoreUp_Ncifre_Base2(numero, clock, reset_);

    parameter N = 10;

    input clock, reset_;
    output [N-1:0] numero;

    reg [N-1:0] OUTR;
    assign numero=OUTR;

    always @(reset_ == 0) #1 OUTR<=0;

    always @(posedge clock) if (reset_ == 1) #3 OUTR <= numero + 1;
endmodule