data/full_repos/permissive/154448000/src/sram.v
 line:35: before: "["
1: b'%Warning-STMTDLY: data/full_repos/permissive/154448000/src/sram.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #4 read_data   =  (enable && ~write) ? mem [address] :\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/154448000/src/sram.v:68: Unsupported: event data types\n    event loadMemory ;\n    ^~~~~\n%Error: data/full_repos/permissive/154448000/src/sram.v:71: syntax error, unexpected \'@\'\n        @(loadMemory)\n        ^\n%Error: data/full_repos/permissive/154448000/src/sram.v:79: syntax error, unexpected ->\n        -> loadMemory ;\n        ^~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sram     #(parameter  ADDR_WIDTH      = 8   ,
                  parameter  DATA_WIDTH      = 32  ,
                  parameter  MEM_INIT_FILE   = ""  )
                (


                input  wire [ADDR_WIDTH-1:0  ]  address     ,
                input  wire [DATA_WIDTH-1:0  ]  write_data  ,
                output reg  [DATA_WIDTH-1:0  ]  read_data   ,
                input  wire                     enable      , 
                input  wire                     write       ,

                input  clock
                );





    bit  [DATA_WIDTH-1 :0  ]     mem     [int] = '{default: 'X};





    always @(*)
      begin
        #4 read_data   =  (enable && ~write) ? mem [address] :
                                               16'hx         ; 
      end




    always @(posedge clock)
      begin
        if (enable && write)
          mem [address] = write_data ;
      end






    
    string memFile;
    string entry  ;
    int fileDesc ;
    bit [ADDR_WIDTH-1 :0 ]  memory_address ;
    bit [DATA_WIDTH-1 :0 ]  memory_data    ;

    event loadMemory ;
    always
      begin
        @(loadMemory)
          loadInitFile;
      end


    initial
      begin
        memFile = MEM_INIT_FILE ;
        -> loadMemory ;
      end

    task  loadInitFile;
      if (memFile != "")
        begin
          fileDesc = $fopen (memFile, "r");
          if (fileDesc == 0)
            begin
              $display("ERROR::readmem file error : %s ", memFile);
              $finish;
            end
          $display("INFO::readmem : %s ", memFile);
          while (!$feof(fileDesc)) 
            begin 
              void'($fgets(entry, fileDesc)); 
              void'($sscanf(entry, "@%x %x", memory_address, memory_data));

              mem[memory_address] = memory_data ;
            end
          $fclose(fileDesc);
        end
     endtask

endmodule
module sram     #(parameter  ADDR_WIDTH      = 8   ,
                  parameter  DATA_WIDTH      = 32  ,
                  parameter  MEM_INIT_FILE   = ""  )
                (


                input  wire [ADDR_WIDTH-1:0  ]  address     ,
                input  wire [DATA_WIDTH-1:0  ]  write_data  ,
                output reg  [DATA_WIDTH-1:0  ]  read_data   ,
                input  wire                     enable      , 
                input  wire                     write       ,

                input  clock
                );






    bit  [DATA_WIDTH-1 :0  ]     mem     [int] = '{default: 'X};





    always @(*)
      begin
        #4 read_data   =  (enable && ~write) ? mem [address] :
                                               16'hx         ; 
      end




    always @(posedge clock)
      begin
        if (enable && write)
          mem [address] = write_data ;
      end






    
    string memFile;
    string entry  ;
    int fileDesc ;
    bit [ADDR_WIDTH-1 :0 ]  memory_address ;
    bit [DATA_WIDTH-1 :0 ]  memory_data    ;

    event loadMemory ;
    always
      begin
        @(loadMemory)
          loadInitFile;
      end


    initial
      begin
        memFile = MEM_INIT_FILE ;
        -> loadMemory ;
      end

    task  loadInitFile;
      if (memFile != "")
        begin
          fileDesc = $fopen (memFile, "r");
          if (fileDesc == 0)
            begin
              $display("ERROR::readmem file error : %s ", memFile);
              $finish;
            end
          $display("INFO::readmem : %s ", memFile);
          while (!$feof(fileDesc)) 
            begin 
              void'($fgets(entry, fileDesc)); 
              void'($sscanf(entry, "@%x %x", memory_address, memory_data));

              mem[memory_address] = memory_data ;
            end
          $fclose(fileDesc);
        end
     endtask

endmodule