data/full_repos/permissive/204608363/64_8 float/rtable.v
1: b'%Error: Cannot find file containing module: float,data/full_repos/permissive/204608363\n        ... Looked in:\n             data/full_repos/permissive/204608363/64_8/float,data/full_repos/permissive/204608363\n             data/full_repos/permissive/204608363/64_8/float,data/full_repos/permissive/204608363.v\n             data/full_repos/permissive/204608363/64_8/float,data/full_repos/permissive/204608363.sv\n             float,data/full_repos/permissive/204608363\n             float,data/full_repos/permissive/204608363.v\n             float,data/full_repos/permissive/204608363.sv\n             obj_dir/float,data/full_repos/permissive/204608363\n             obj_dir/float,data/full_repos/permissive/204608363.v\n             obj_dir/float,data/full_repos/permissive/204608363.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/204608363/64_8\n%Error: Cannot find file containing module: float/rtable.v\n%Error: Exiting due to 3 error(s)\n'
module rtable #(parameter ADDR_WIDTH = 9, DATA_WIDTH = 32, DEPTH = 512) (
    input wire i_clk,
    input wire [ADDR_WIDTH-1:0] i_addr, 
    input wire i_read,
    output reg [DATA_WIDTH-1:0] o_data);

    always @ (posedge i_clk)
    begin
        casez (i_addr)

            9'b000_???_000: o_data<= 32'b11000011011111110000000000000000;
            9'b000_???_001: o_data<= 32'b11000011011111110000000000000000;
            9'b000_???_111: o_data<= 32'b11000011011111110000000000000000;


            9'b???_000_001: o_data<= 32'b11000011011111110000000000000000;
            9'b???_000_010: o_data<= 32'b11000011011111110000000000000000;
            9'b???_000_011: o_data<= 32'b11000011011111110000000000000000;

            9'b111_???_011: o_data<= 32'b11000011011111110000000000000000;
            9'b111_???_100: o_data<= 32'b11000011011111110000000000000000;
            9'b111_???_101: o_data<= 32'b11000011011111110000000000000000;

            9'b???_111_101: o_data<= 32'b11000011011111110000000000000000;
            9'b???_111_110: o_data<= 32'b11000011011111110000000000000000;
            9'b???_111_111: o_data<= 32'b11000011011111110000000000000000;


            9'b110_111_100: o_data<= 32'b01000011011111110000000000000000;
            9'b111_110_110: o_data<= 32'b01000011011111110000000000000000;
            9'b110_110_101: o_data<= 32'b01000011011111110000000000000000;


            
            default :  o_data<= {DATA_WIDTH{1'b0}};
        endcase    

    end
endmodule
module rtable #(parameter ADDR_WIDTH = 9, DATA_WIDTH = 32, DEPTH = 512) (
    input wire i_clk,
    input wire [ADDR_WIDTH-1:0] i_addr, 
    input wire i_read,
    output reg [DATA_WIDTH-1:0] o_data);


    always @ (posedge i_clk)
    begin
        casez (i_addr)

            9'b000_???_000: o_data<= 32'b11000011011111110000000000000000;
            9'b000_???_001: o_data<= 32'b11000011011111110000000000000000;
            9'b000_???_111: o_data<= 32'b11000011011111110000000000000000;


            9'b???_000_001: o_data<= 32'b11000011011111110000000000000000;
            9'b???_000_010: o_data<= 32'b11000011011111110000000000000000;
            9'b???_000_011: o_data<= 32'b11000011011111110000000000000000;

            9'b111_???_011: o_data<= 32'b11000011011111110000000000000000;
            9'b111_???_100: o_data<= 32'b11000011011111110000000000000000;
            9'b111_???_101: o_data<= 32'b11000011011111110000000000000000;

            9'b???_111_101: o_data<= 32'b11000011011111110000000000000000;
            9'b???_111_110: o_data<= 32'b11000011011111110000000000000000;
            9'b???_111_111: o_data<= 32'b11000011011111110000000000000000;


            9'b110_111_100: o_data<= 32'b01000011011111110000000000000000;
            9'b111_110_110: o_data<= 32'b01000011011111110000000000000000;
            9'b110_110_101: o_data<= 32'b01000011011111110000000000000000;


            
            default :  o_data<= {DATA_WIDTH{1'b0}};
        endcase    

    end
endmodule