data/full_repos/permissive/168578692/Display_Driver.v
data/verilator_xmls/a7673773-ab2a-4eb9-9237-536d0a59ff26.xml
module Display_Driver(

  input clock,
  output reg [1:0] select_State
);


reg [15:0] counter;


initial counter = 16'h0000;

always @ (posedge clock) begin

  if(counter >= 16'hFFFF) begin

    counter = 16'h0000;
  end
  

  counter = counter + 1;
  

  select_State[0] = counter[14];
  select_State[1] = counter[15];
end
endmodule
module Display_Driver(

  input clock,
  output reg [1:0] select_State
);



reg [15:0] counter;


initial counter = 16'h0000;

always @ (posedge clock) begin

  if(counter >= 16'hFFFF) begin

    counter = 16'h0000;
  end
  

  counter = counter + 1;
  

  select_State[0] = counter[14];
  select_State[1] = counter[15];
end
endmodule