data/full_repos/permissive/180413071/nonpipelined/sources/tests/fadder_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/fadder_tb.sv:2: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/constants.vh\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/constants.vh.v\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/fadder_tb.sv:3: Cannot find include file: helpers.vh\n`include "helpers.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/fadder_tb.sv:13: Define or directive not defined: \'`TB_BEGIN\'\n        `TB_BEGIN;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/180413071/nonpipelined/sources/tests/fadder_tb.sv:18: Unsupported: Ignoring delay on this delayed statement.\n        #1 assert(out == 32\'b01000001000010101110000101000110) else $error("[1]");\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/180413071/nonpipelined/sources/tests/fadder_tb.sv:23: Unsupported: Ignoring delay on this delayed statement.\n        #1 assert(out == 32\'b00111100110010100010000100100001) else $error("[2]");\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/180413071/nonpipelined/sources/tests/fadder_tb.sv:28: Unsupported: Ignoring delay on this delayed statement.\n        #1 assert(out == 32\'b00111111001011110001011101011000) else $error("[3]");\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/180413071/nonpipelined/sources/tests/fadder_tb.sv:33: Unsupported: Ignoring delay on this delayed statement.\n        #1 assert(out == 32\'b00111110001110100011111100011011) else $error("[4]");\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/180413071/nonpipelined/sources/tests/fadder_tb.sv:38: Unsupported: Ignoring delay on this delayed statement.\n        #1 assert(out == 32\'b01011000001011110001011101011100) else $error("[5]");\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/180413071/nonpipelined/sources/tests/fadder_tb.sv:43: Unsupported: Ignoring delay on this delayed statement.\n        #1 assert(out == 32\'b11000100101100000111011101101100) else $error("[6]");\n        ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/fadder_tb.sv:45: Define or directive not defined: \'`TB_END\'\n        `TB_END;\n        ^~~~~~~\n%Error: Exiting due to 4 error(s), 6 warning(s)\n'
module fadder_tb;

    reg [31:0] a, b, out;

    fadders UUT(.*);
    
    initial begin
        `TB_BEGIN;
        

        a <= 32'b11000001110110001111010111000011;
        b <= 32'b01000010000011110011001100110011;
        #1 assert(out == 32'b01000001000010101110000101000110) else $error("[1]");
        

        a <= 32'b00111011101010000011101100011101;
        b <= 32'b00111100101000000001001001011010;
        #1 assert(out == 32'b00111100110010100010000100100001) else $error("[2]");
        

        a <= 32'b00111110111100101010001100000101;
        b <= 32'b00111110010101110001011101011001;
        #1 assert(out == 32'b00111111001011110001011101011000) else $error("[3]");
        

        a <= 32'b00111101101011110001011101011000;
        b <= 32'b00111101110001010110011011011111;
        #1 assert(out == 32'b00111110001110100011111100011011) else $error("[4]");
        

        a <= 32'b01011000001011110001011101011100;
        b <= 32'b01000001010110100010011000111110;
        #1 assert(out == 32'b01011000001011110001011101011100) else $error("[5]");
        

        a <= 32'b11000011110101101100111001110111;
        b <= 32'b11000100011101011000011110011110;
        #1 assert(out == 32'b11000100101100000111011101101100) else $error("[6]");
        
        `TB_END;
        $finish;
    end

endmodule
module fadder_tb;


    reg [31:0] a, b, out;

    fadders UUT(.*);
    
    initial begin
        `TB_BEGIN;
        

        a <= 32'b11000001110110001111010111000011;
        b <= 32'b01000010000011110011001100110011;
        #1 assert(out == 32'b01000001000010101110000101000110) else $error("[1]");
        

        a <= 32'b00111011101010000011101100011101;
        b <= 32'b00111100101000000001001001011010;
        #1 assert(out == 32'b00111100110010100010000100100001) else $error("[2]");
        

        a <= 32'b00111110111100101010001100000101;
        b <= 32'b00111110010101110001011101011001;
        #1 assert(out == 32'b00111111001011110001011101011000) else $error("[3]");
        

        a <= 32'b00111101101011110001011101011000;
        b <= 32'b00111101110001010110011011011111;
        #1 assert(out == 32'b00111110001110100011111100011011) else $error("[4]");
        

        a <= 32'b01011000001011110001011101011100;
        b <= 32'b01000001010110100010011000111110;
        #1 assert(out == 32'b01011000001011110001011101011100) else $error("[5]");
        

        a <= 32'b11000011110101101100111001110111;
        b <= 32'b11000100011101011000011110011110;
        #1 assert(out == 32'b11000100101100000111011101101100) else $error("[6]");
        
        `TB_END;
        $finish;
    end

endmodule