data/full_repos/permissive/120142431/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/120142431/alu.v:16: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 16 bits.\n                                                             : ... In instance alu\n   4\'b0110: result <= #1 ! a;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/120142431/alu.v:16: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s LOGNOT generates 1 bits.\n                                                             : ... In instance alu\n   4\'b0110: result <= #1 ! a;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/120142431/alu.v:17: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 16 bits.\n                                                             : ... In instance alu\n   4\'b0111: result <= #1 a && b;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/120142431/alu.v:17: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'b\' generates 16 bits.\n                                                             : ... In instance alu\n   4\'b0111: result <= #1 a && b;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/120142431/alu.v:17: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s LOGAND generates 1 bits.\n                                                             : ... In instance alu\n   4\'b0111: result <= #1 a && b;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/120142431/alu.v:20: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                             : ... In instance alu\n   4\'b1010: result <= #1 a == b;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/120142431/alu.v:21: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s GT generates 1 bits.\n                                                             : ... In instance alu\n   4\'b1011: result <= #1 a > b;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/120142431/alu.v:22: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s GTE generates 1 bits.\n                                                             : ... In instance alu\n   4\'b1100: result <= #1 a >= b;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/120142431/alu.v:23: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 16 bits.\n                                                             : ... In instance alu\n   4\'b1101: result <= #1 a || b;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/120142431/alu.v:23: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s VARREF \'b\' generates 16 bits.\n                                                             : ... In instance alu\n   4\'b1101: result <= #1 a || b;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/120142431/alu.v:23: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s LOGOR generates 1 bits.\n                                                             : ... In instance alu\n   4\'b1101: result <= #1 a || b;\n                   ^~\n%Error: Exiting due to 11 warning(s)\n'
module alu(clk, a, b, result, op);
input [3:0] op;
input clk;
input [15:0] a;
input [15:0] b;
output reg [15:0] result;
always @ (posedge clk)
	begin
		case(op)
			4'b0000: result <= #1 a + b;
			4'b0001: result <= #1 a - b;
			4'b0010: result <= #1 a * b;
			4'b0011: result <= #1 ~ a;
			4'b0100: result <= #1 a | b;
			4'b0101: result <= #1 a & b;
			4'b0110: result <= #1 ! a;
			4'b0111: result <= #1 a && b;
			4'b1000: result <= #1 a >> b;
			4'b1001: result <= #1 a << b;
			4'b1010: result <= #1 a == b;
			4'b1011: result <= #1 a > b;
			4'b1100: result <= #1 a >= b;
			4'b1101: result <= #1 a || b;
			4'b1110: result <= #1 a ^ b;
			default: result <= #1 a;
		endcase
	end	
endmodule
module alu(clk, a, b, result, op);

input [3:0] op;
input clk;
input [15:0] a;
input [15:0] b;
output reg [15:0] result;
always @ (posedge clk)
	begin
		case(op)
			4'b0000: result <= #1 a + b;
			4'b0001: result <= #1 a - b;
			4'b0010: result <= #1 a * b;
			4'b0011: result <= #1 ~ a;
			4'b0100: result <= #1 a | b;
			4'b0101: result <= #1 a & b;
			4'b0110: result <= #1 ! a;
			4'b0111: result <= #1 a && b;
			4'b1000: result <= #1 a >> b;
			4'b1001: result <= #1 a << b;
			4'b1010: result <= #1 a == b;
			4'b1011: result <= #1 a > b;
			4'b1100: result <= #1 a >= b;
			4'b1101: result <= #1 a || b;
			4'b1110: result <= #1 a ^ b;
			default: result <= #1 a;
		endcase
	end	
endmodule