data/full_repos/permissive/205055389/vlib/74xx.v
 line:681: before: "."
1: b"%Error: data/full_repos/permissive/205055389/vlib/74xx.v:681: syntax error, unexpected '.', expecting '['\nmodule H7442 #(.delay(14)) (A0,A1,A2,A3,_Y0,_Y1,_Y2,_Y3,_Y4,_Y5,_Y6,_Y7,_Y8,_Y9);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:686: syntax error, unexpected assign\n  assign c1_0 = ~(~A0 & ~A1);\n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:791: syntax error, unexpected '.', expecting '['\nmodule H74182 #(.delay(4)) (_G0,_G1,_G2,_G3,_P0,_P1,_P2,_P3,_P,_G,Cn,CnPx,CnPy,CnPz);\n                ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:815: syntax error, unexpected '.', expecting '['\nmodule H7474 #(.delay(18)) (CLK,D1,_PRE1,_CLR1,D2,_PRE2,_CLR2,Q1,_Q1,Q2,_Q2);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:820: syntax error, unexpected assign\n  assign #delay _Q1 = ~R1;\n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:858: syntax error, unexpected '.', expecting '['\nmodule H7404 #(.delay(3)) (A1,A2,A3,A4,A5,A6,Y1,Y2,Y3,Y4,Y4,Y6);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:878: syntax error, unexpected '.', expecting '['\nmodule H7411 #(.delay(6)) (A1,A2,A3,B1,B2,B3,C1,C2,C3,Y1,Y2,Y3);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:895: syntax error, unexpected '.', expecting '['\nmodule H7427 #(.delay(6)) (A1,B1,C1,A2,B2,C2,A3,B3,C3,Y1,Y2,Y3);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:912: syntax error, unexpected '.', expecting '['\nmodule H7420 #(.delay(6)) (A1,A2,B1,B2,C1,C2,D1,D2,Y1,Y2);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:928: syntax error, unexpected '.', expecting '['\nmodule H7402 #(.delay(4)) (A1,A2,A3,A4,B1,B2,B3,B4,Y1,Y2,Y3,Y4);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:946: syntax error, unexpected '.', expecting '['\nmodule H74154 #(.delay(20)) (A,B,C,D,_G1,_G2,_Y1,_Y2,_Y3,_Y4,_Y5,_Y6,_Y7,_Y8,\n                ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:952: syntax error, unexpected assign\n  assign #delay {_Y16,_Y15,_Y14,_Y13,_Y12,_Y11,_Y10,_Y9,_Y8,_Y7,_Y6,_Y5,_Y4,_Y3,_Y2,_Y1} = ~R;\n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:976: syntax error, unexpected '.', expecting '['\nmodule H74181 #(.delay(4)) (_A0,_A1,_A2,_A3,_B0,_B1,_B2,_B3,S0,S1,S2,S3,Cn,M,_F0,_F1,_F2,_F3,AEB,CnP4,_G,_P);\n                ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:988: syntax error, unexpected assign\n  assign #delay L1_0 = ~( _A0 | (_B0 & S0) | (~_B0 & S1) );\n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1003: syntax error, unexpected assign\n  assign #delay L2_0 = ~(~M & Cn);\n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1027: syntax error, unexpected '.', expecting '['\nmodule H74157 #(.delay(18)) (S,_G,A1,A2,A3,A4,B1,B2,B3,B4,Y1,Y2,Y3,Y4);\n                ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1046: syntax error, unexpected '.', expecting '['\nmodule H7486 #(.delay(4)) (A1,A2,A3,A4,B1,B2,B3,B4,Y1,Y2,Y3,Y4);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1064: syntax error, unexpected '.', expecting '['\nmodule H7408 #(.delay(4)) (A1,A2,A3,A4,B1,B2,B3,B4,Y1,Y2,Y3,Y4);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1082: syntax error, unexpected '.', expecting '['\nmodule H74163 #(.delay(20)) (_CLR, _LOAD, ENT, ENP, CLK, A, B, C, D, QA, QB, QC, QD, RCO);\n                ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1120: syntax error, unexpected '.', expecting '['\nmodule H7410 #(.delay(6)) (A1,A2,A3,B1,B2,B3,C1,C2,C3,Y1,Y2,Y3);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1137: syntax error, unexpected '.', expecting '['\nmodule H74175 #(.delay(18)) (CLK,_PRE,_CLR,D1,D2,D3,D4,Q1,_Q1,Q2,_Q2,Q3,_Q3,Q4,_Q4);\n                ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1142: syntax error, unexpected assign\n  assign #delay _Q1 = ~R1;\n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1190: syntax error, unexpected '.', expecting '['\nmodule H7421 #(.delay(6)) (A1,A2,B1,B2,C1,C2,D1,D2,Y1,Y2);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1206: syntax error, unexpected '.', expecting '['\nmodule H7430 #(.delay(12)) (A,B,C,D,E,F,G,H,Y);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1221: syntax error, unexpected '.', expecting '['\nmodule H7400 #(.delay(4)) (A1,A2,A3,A4,B1,B2,B3,B4,Y1,Y2,Y3,Y4);\n               ^\n%Error: data/full_repos/permissive/205055389/vlib/74xx.v:1239: syntax error, unexpected '.', expecting '['\nmodule H7432 #(.delay(6)) (A1,A2,A3,A4,B1,B2,B3,B4,Y1,Y2,Y3,Y4);\n               ^\n%Error: Exiting due to 26 error(s)\n"
module H74181 #(.delay(4)) (_A0,_A1,_A2,_A3,_B0,_B1,_B2,_B3,S0,S1,S2,S3,Cn,M,_F0,_F1,_F2,_F3,AEB,CnP4,_G,_P);
  
  input _A0,_A1,_A2,_A3;
  input _B0,_B1,_B2,_B3;
  input Cn,M;
  input S0,S1,S2,S3;
  output _F0,_F1,_F2,_F3;
  output AEB,CnP4,_G,_P;
  

  wire L1_0,L1_1,L1_2,L1_3,L1_4,L1_5,L1_6,L1_7;
  
  assign #delay L1_0 = ~( _A0 | (_B0 & S0) | (~_B0 & S1) );
  assign #delay L1_1 = ~( (_A0 & ~_B0 & S2 ) | (_A0 & _B0 & S3) );
  
  assign #delay L1_2 = ~( _A1 | (_B1 & S0) | (~_B1 & S1) );
  assign #delay L1_3 = ~( (_A1 & ~_B1 & S2 ) | (_A1 & _B1 & S3) );
  
  assign #delay L1_4 = ~( _A2 | (_B2 & S0) | (~_B2 & S1) );
  assign #delay L1_5 = ~( (_A2 & ~_B2 & S2 ) | (_A2 & _B2 & S3) );
  
  assign #delay L1_6 = ~( _A3 | (_B3 & S0) | (~_B3 & S1) );
  assign #delay L1_7 = ~( (_A3 & ~_B3 & S2 ) | (_A3 & _B3 & S3) );
  

  wire L2_0,L2_1,L2_2,L2_3;
  
  assign #delay L2_0 = ~(~M & Cn);
  assign #delay L2_1 = ~( (~M & L1_0) | (~M & L1_1 & Cn) );
  assign #delay L2_2 = ~( (~M & L1_2) | (~M & L1_0 & L1_3) | (~M & L1_1 & L1_3 & Cn)  );
  assign #delay L2_3 = ~( (~M & L1_4) | (~M & L1_2 & L1_5) | (~M & L1_0 & L1_3 & L1_5) | (~M & L1_1 & L1_3 & L1_5 &Cn)  );
  
  assign #delay _F0 = L2_0 ^ (L1_0 ^ L1_1);
  assign #delay _F1 = L2_1 ^ (L1_2 ^ L1_3); 
  assign #delay _F2 = L2_2 ^ (L1_4 ^ L1_5);
  assign #delay _F3 = L2_3 ^ (L1_6 ^ L1_7);
  
  assign #delay AEB = _F0 & _F1 & _F2 & _F3;
  assign #delay _G = ~( L1_6 | (L1_4 & L1_7) | (L1_2 & L1_5 & L1_7) | (L1_0 & L1_3 & L1_5 & L1_7) );
  assign #delay CnP4 = ~_G | ( L1_1 & L1_3 & L1_5 & L1_7 & Cn );
  assign #delay _P = ~( L1_1 & L1_3 & L1_5 & L1_7 );
    
endmodule
module H74181 #(.delay(4)) (_A0,_A1,_A2,_A3,_B0,_B1,_B2,_B3,S0,S1,S2,S3,Cn,M,_F0,_F1,_F2,_F3,AEB,CnP4,_G,_P);

  
  input _A0,_A1,_A2,_A3;
  input _B0,_B1,_B2,_B3;
  input Cn,M;
  input S0,S1,S2,S3;
  output _F0,_F1,_F2,_F3;
  output AEB,CnP4,_G,_P;
  

  wire L1_0,L1_1,L1_2,L1_3,L1_4,L1_5,L1_6,L1_7;
  
  assign #delay L1_0 = ~( _A0 | (_B0 & S0) | (~_B0 & S1) );
  assign #delay L1_1 = ~( (_A0 & ~_B0 & S2 ) | (_A0 & _B0 & S3) );
  
  assign #delay L1_2 = ~( _A1 | (_B1 & S0) | (~_B1 & S1) );
  assign #delay L1_3 = ~( (_A1 & ~_B1 & S2 ) | (_A1 & _B1 & S3) );
  
  assign #delay L1_4 = ~( _A2 | (_B2 & S0) | (~_B2 & S1) );
  assign #delay L1_5 = ~( (_A2 & ~_B2 & S2 ) | (_A2 & _B2 & S3) );
  
  assign #delay L1_6 = ~( _A3 | (_B3 & S0) | (~_B3 & S1) );
  assign #delay L1_7 = ~( (_A3 & ~_B3 & S2 ) | (_A3 & _B3 & S3) );
  

  wire L2_0,L2_1,L2_2,L2_3;
  
  assign #delay L2_0 = ~(~M & Cn);
  assign #delay L2_1 = ~( (~M & L1_0) | (~M & L1_1 & Cn) );
  assign #delay L2_2 = ~( (~M & L1_2) | (~M & L1_0 & L1_3) | (~M & L1_1 & L1_3 & Cn)  );
  assign #delay L2_3 = ~( (~M & L1_4) | (~M & L1_2 & L1_5) | (~M & L1_0 & L1_3 & L1_5) | (~M & L1_1 & L1_3 & L1_5 &Cn)  );
  
  assign #delay _F0 = L2_0 ^ (L1_0 ^ L1_1);
  assign #delay _F1 = L2_1 ^ (L1_2 ^ L1_3); 
  assign #delay _F2 = L2_2 ^ (L1_4 ^ L1_5);
  assign #delay _F3 = L2_3 ^ (L1_6 ^ L1_7);
  
  assign #delay AEB = _F0 & _F1 & _F2 & _F3;
  assign #delay _G = ~( L1_6 | (L1_4 & L1_7) | (L1_2 & L1_5 & L1_7) | (L1_0 & L1_3 & L1_5 & L1_7) );
  assign #delay CnP4 = ~_G | ( L1_1 & L1_3 & L1_5 & L1_7 & Cn );
  assign #delay _P = ~( L1_1 & L1_3 & L1_5 & L1_7 );
    
endmodule