data/full_repos/permissive/143278/ivltests/format.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/format.v:7: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/format.v:12: Missing arguments for $display-like format\n        $display("%d, %d", a);\n        ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   wire [10:0] a = 7'd 16;

   initial
     begin
        #1;
        $display(">%0d<", a);
        $display(">%4d<", a);
        $display(">%h<", a);
        $display(">%4h<", a);
        $display("%d, %d", a);
     end

endmodule
module test;


   wire [10:0] a = 7'd 16;

   initial
     begin
        #1;
        $display(">%0d<", a);
        $display(">%4d<", a);
        $display(">%h<", a);
        $display(">%4h<", a);
        $display("%d, %d", a);
     end

endmodule