data/full_repos/permissive/150266237/parte2.v
1: b'%Error: data/full_repos/permissive/150266237/parte2.v:119: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile ("out.vcd"); \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte2.v:120: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars; \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte2.v:125: Unsupported or unknown PLI call: $monitor\n     $monitor($time," c %b res %b a %b s %d smem %d sporta %d",c,res,a,saida,saida1,saida2);\n     ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:126: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=0; a=0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:127: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:128: Unsupported: Ignoring delay on this delayed statement.\n      #8 a=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:129: Unsupported: Ignoring delay on this delayed statement.\n      #16 a=0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:130: Unsupported: Ignoring delay on this delayed statement.\n      #12 a=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:131: Unsupported: Ignoring delay on this delayed statement.\n      #4;\n      ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stateMem(input clk,input res, input a, output [2:0] saida);
reg [5:0] StateMachine [0:15];
initial
begin

StateMachine[0] = 6'h14;  StateMachine[1] = 6'h24;
StateMachine[2] = 6'h35;  StateMachine[3] = 6'h35;
StateMachine[4] = 6'h20;  StateMachine[5] = 6'h20;
StateMachine[8] = 6'h33;  StateMachine[9] = 6'h0b;
StateMachine[12] = 6'h02;  StateMachine[13] = 6'h02;
end
wire [3:0] address;
wire [5:0] dout;
assign address[0] = a;
assign dout = StateMachine[address];
assign saida = dout[2:0];
ff st0(dout[3],clk,res,address[1]);
ff st1(dout[4],clk,res,address[2]);
ff st2(dout[5],clk,res,address[3]);
endmodule
module stateMem(input clk,input res, input a, output [2:0] saida);

reg [5:0] StateMachine [0:15];
initial
begin

StateMachine[0] = 6'h14;  StateMachine[1] = 6'h24;
StateMachine[2] = 6'h35;  StateMachine[3] = 6'h35;
StateMachine[4] = 6'h20;  StateMachine[5] = 6'h20;
StateMachine[8] = 6'h33;  StateMachine[9] = 6'h0b;
StateMachine[12] = 6'h02;  StateMachine[13] = 6'h02;
end
wire [3:0] address;
wire [5:0] dout;
assign address[0] = a;
assign dout = StateMachine[address];
assign saida = dout[2:0];
ff st0(dout[3],clk,res,address[1]);
ff st1(dout[4],clk,res,address[2]);
ff st2(dout[5],clk,res,address[3]);
endmodule