data/full_repos/permissive/158096953/mem_control.v
data/verilator_xmls/b466e0be-ce04-4509-b91e-ade2ca90e04f.xml
module mem_control(
	m1,
	mreq,

	wr,
	address,
	pram_ce,
	dram_ce,
	dram_wr




);

input        m1;
input        mreq;

input        wr;
input [15:0] address;
output       pram_ce;
output       dram_ce;
output       dram_wr;






parameter PRAM_SIZE = 16'b0000_1111_1111_1111;
parameter DRAM_SIZE = 16'b0000_0001_1111_1111;




wire pram_address_judge_flag;
wire dram_address_judge_flag;
assign pram_address_judge_flag = address > PRAM_SIZE;
assign dram_address_judge_flag = address > DRAM_SIZE;


assign pram_ce = m1 | mreq | pram_address_judge_flag;
assign dram_ce = (~m1) | mreq | dram_address_judge_flag;
assign dram_wr = mreq | wr;









endmodule
module mem_control(
	m1,
	mreq,

	wr,
	address,
	pram_ce,
	dram_ce,
	dram_wr




);


input        m1;
input        mreq;

input        wr;
input [15:0] address;
output       pram_ce;
output       dram_ce;
output       dram_wr;






parameter PRAM_SIZE = 16'b0000_1111_1111_1111;
parameter DRAM_SIZE = 16'b0000_0001_1111_1111;




wire pram_address_judge_flag;
wire dram_address_judge_flag;
assign pram_address_judge_flag = address > PRAM_SIZE;
assign dram_address_judge_flag = address > DRAM_SIZE;


assign pram_ce = m1 | mreq | pram_address_judge_flag;
assign dram_ce = (~m1) | mreq | dram_address_judge_flag;
assign dram_wr = mreq | wr;









endmodule