data/full_repos/permissive/163840441/project/ADD.v
 line:28: before: "ter"
data/verilator_xmls/a7f4c08a-9598-4623-9d69-b6aa47f1eb4e.xml
module ADD(
        input [7:0] a,b,
        output [7:0] r,
        output cout
    );
    assign {cout, r} = a + b;
endmodule
module ADD(
        input [7:0] a,b,
        output [7:0] r,
        output cout
    );

    assign {cout, r} = a + b;
endmodule