data/full_repos/permissive/208556773/src/spi.v
1: b"%Error: data/full_repos/permissive/208556773/src/spi.v:32: Cannot find file containing module: 'rising_edge_detector_tribuf'\n  rising_edge_detector_tribuf sck_rising (.clk(clk), .in(SCK), .out(SCK_risingedge));\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208556773/src,data/full_repos/permissive/208556773/rising_edge_detector_tribuf\n             data/full_repos/permissive/208556773/src,data/full_repos/permissive/208556773/rising_edge_detector_tribuf.v\n             data/full_repos/permissive/208556773/src,data/full_repos/permissive/208556773/rising_edge_detector_tribuf.sv\n             rising_edge_detector_tribuf\n             rising_edge_detector_tribuf.v\n             rising_edge_detector_tribuf.sv\n             obj_dir/rising_edge_detector_tribuf\n             obj_dir/rising_edge_detector_tribuf.v\n             obj_dir/rising_edge_detector_tribuf.sv\n%Error: data/full_repos/permissive/208556773/src/spi.v:33: Cannot find file containing module: 'falling_edge_detector_tribuf'\n  falling_edge_detector_tribuf sck_falling (.clk(clk), .in(SCK), .out(SCK_fallingedge));\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/208556773/src/spi.v:120: Cannot find file containing module: 'rising_edge_detector'\n  rising_edge_detector ready_rising (.clk(clk), .in(rx_byte_ready), .out(rx_byte_ready_rising));\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module SPI (
    input            clk,
    input            resetn,
    input            SCK,
    input            CS,
    input            COPI,
    output           CIPO,
    input      [7:0] tx_byte,
    output reg [7:0] rx_byte,
    output           rx_byte_ready
);


  reg [1:0] COPIr;
  reg [1:0] CSr;


  reg rx_byte_ready_r;
  assign rx_byte_ready = rx_byte_ready_r;


  reg [2:0] rxbitcnt;
  reg [2:0] txbitcnt;


  wire SCK_risingedge;
  wire SCK_fallingedge;
  rising_edge_detector_tribuf sck_rising (.clk(clk), .in(SCK), .out(SCK_risingedge));
  falling_edge_detector_tribuf sck_falling (.clk(clk), .in(SCK), .out(SCK_fallingedge));

  wire CS_active = ~CSr[1];
  wire COPI_data = COPIr[1];

  assign CIPO = (CS_active) ? tx_byte[txbitcnt] : 1'bZ;


  always @(posedge clk) begin
    if (!resetn) begin

      COPIr <= 2'b0;


      rx_byte_ready_r <= 0;
      rx_byte <= 8'b0;


      rxbitcnt <= 3'b000;
      txbitcnt <= 3'b111;
    end else if (resetn) begin


      COPIr <= {COPIr[0], COPI};
      CSr <= {CSr[0], CS};

      if (CS_active) begin

        if (SCK_risingedge) begin
          rxbitcnt <= rxbitcnt + 1'b1;

          rx_byte <= {rx_byte[6:0], COPI_data};
        end else if (SCK_fallingedge) begin
          txbitcnt <= txbitcnt - 1'b1;

          rx_byte_ready_r <= (txbitcnt == 3'b0);
        end




      end else begin

        rxbitcnt <= 3'b000;
        txbitcnt <= 3'b111;
      end
    end
  end

endmodule
module SPI (
    input            clk,
    input            resetn,
    input            SCK,
    input            CS,
    input            COPI,
    output           CIPO,
    input      [7:0] tx_byte,
    output reg [7:0] rx_byte,
    output           rx_byte_ready
);



  reg [1:0] COPIr;
  reg [1:0] CSr;


  reg rx_byte_ready_r;
  assign rx_byte_ready = rx_byte_ready_r;


  reg [2:0] rxbitcnt;
  reg [2:0] txbitcnt;


  wire SCK_risingedge;
  wire SCK_fallingedge;
  rising_edge_detector_tribuf sck_rising (.clk(clk), .in(SCK), .out(SCK_risingedge));
  falling_edge_detector_tribuf sck_falling (.clk(clk), .in(SCK), .out(SCK_fallingedge));

  wire CS_active = ~CSr[1];
  wire COPI_data = COPIr[1];

  assign CIPO = (CS_active) ? tx_byte[txbitcnt] : 1'bZ;


  always @(posedge clk) begin
    if (!resetn) begin

      COPIr <= 2'b0;


      rx_byte_ready_r <= 0;
      rx_byte <= 8'b0;


      rxbitcnt <= 3'b000;
      txbitcnt <= 3'b111;
    end else if (resetn) begin


      COPIr <= {COPIr[0], COPI};
      CSr <= {CSr[0], CS};

      if (CS_active) begin

        if (SCK_risingedge) begin
          rxbitcnt <= rxbitcnt + 1'b1;

          rx_byte <= {rx_byte[6:0], COPI_data};
        end else if (SCK_fallingedge) begin
          txbitcnt <= txbitcnt - 1'b1;

          rx_byte_ready_r <= (txbitcnt == 3'b0);
        end




      end else begin

        rxbitcnt <= 3'b000;
        txbitcnt <= 3'b111;
      end
    end
  end

endmodule