data/full_repos/permissive/143278/ivltests/ga_mod2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #10 C <= 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #10 if (out !== 2\'b00) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #10 C <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #10 if (out !== 2\'b10) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:48: Unsupported: Ignoring delay on this delayed statement.\n      #10 C <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #10 if (out !== 2\'b01) begin\n      ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DFF(output reg Q, input D, input C);

   always @(posedge C)
     Q <= D;

endmodule
module DFF(output reg Q, input D, input C);


   always @(posedge C)
     Q <= D;

endmodule