data/full_repos/permissive/174155074/combinational-logic/decoders-and-encoders/decoder-3-8/decoder-3-8.v
1: b"%Error: data/full_repos/permissive/174155074/combinational-logic/decoders-and-encoders/decoder-3-8/decoder-3-8.v:7: Duplicate declaration of signal: 'out'\n                                                                                                                  : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg  [7:0] out;\n           ^~~\n        data/full_repos/permissive/174155074/combinational-logic/decoders-and-encoders/decoder-3-8/decoder-3-8.v:4: ... Location of original declaration\n    output  [7:0] out        \n                  ^~~\n%Error: Exiting due to 1 error(s)\n"
module decoder_3_8(
    input   [2:0] in,
    output  [7:0] out
);

reg  [7:0] out;

always @ ( * ) begin
    case (in)
        3'b000 : out <= 8'b00000001;
        3'b001 : out <= 8'b00000010;
        3'b010 : out <= 8'b00000100;
        3'b011 : out <= 8'b00001000;
        3'b100 : out <= 8'b00010000;
        3'b101 : out <= 8'b00100000;
        3'b110 : out <= 8'b01000000;
        3'b111 : out <= 8'b10000000;
    endcase
end

endmodule
module decoder_3_8(
    input   [2:0] in,
    output  [7:0] out
);


reg  [7:0] out;

always @ ( * ) begin
    case (in)
        3'b000 : out <= 8'b00000001;
        3'b001 : out <= 8'b00000010;
        3'b010 : out <= 8'b00000100;
        3'b011 : out <= 8'b00001000;
        3'b100 : out <= 8'b00010000;
        3'b101 : out <= 8'b00100000;
        3'b110 : out <= 8'b01000000;
        3'b111 : out <= 8'b10000000;
    endcase
end

endmodule