data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v
 line:187: before: "always"
1: b"%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:187: syntax error, unexpected always\n    always @(posedge rDerivedClock) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:192: syntax error, unexpected else\n        end else begin\n            ^~~~\n%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:197: syntax error, unexpected <=, expecting IDENTIFIER\n                rLockAck <= rLockAck + 5'h1;\n                         ^~\n%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:267: syntax error, unexpected '[', expecting IDENTIFIER\n                rConfig[0] <= 0;\n                       ^\n%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:270: syntax error, unexpected '[', expecting IDENTIFIER\n                rConfig[1] <= 1;\n                       ^\n%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:273: syntax error, unexpected '[', expecting IDENTIFIER\n                rConfig[1] <= 0;\n                       ^\n%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:276: syntax error, unexpected <=, expecting IDENTIFIER\n                rLockSto <= rLockAck;\n                         ^~\n%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:293: syntax error, unexpected <=, expecting IDENTIFIER\n                rTransferCount <= rTransferCount - 8'h1;\n                               ^~\n%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:313: syntax error, unexpected <=, expecting IDENTIFIER\n                rDirectMISO <= rInternalDataMISO;\n                            ^~\n%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:324: syntax error, unexpected '[', expecting IDENTIFIER\n                rInternalDataMISO[15:8] <= iBusMISO;\n                                 ^\n%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:326: syntax error, unexpected '[', expecting IDENTIFIER\n                rInternalDataMISO[23:16] <= iBusMISO;\n                                 ^\n%Error: data/full_repos/permissive/173814379/implementation/core/sysx_v1r0.v:328: syntax error, unexpected '[', expecting IDENTIFIER\n                rInternalDataMISO[31:24] <= iBusMISO;\n                                 ^\n%Error: Cannot continue\n"
module epRISC_sysXBuffer(iAddrA, iAddrB, iClkA, iClkB, iDInA, iDInB, iWriteA, iWriteB, oDOutA, oDOutB);     

    input iClkA, iClkB, iWriteA, iWriteB;
    input [7:0] iAddrA, iAddrB;
    input [31:0] iDInA, iDInB;
    output reg [31:0] oDOutA, oDOutB;
    
    reg [7:0] rClr;
    reg [31:0] rContents[0:255];
        
    always @(posedge iClkA) begin
        if(iWriteA) begin
            rContents[iAddrA] <= iDInA;
        end
    end

    always @(posedge iClkB) begin
        if(iWriteB) begin
            rContents[iAddrB] <= iDInB;
        end
    end
    
    always @(posedge iClkA) begin
        if(!iWriteA) begin
            oDOutA <= rContents[iAddrA];
        end
    end
    
    always @(posedge iClkB) begin
        if(!iWriteB) begin
            oDOutB <= rContents[iAddrB];
        end
    end
            
endmodule
module epRISC_sysXBuffer(iAddrA, iAddrB, iClkA, iClkB, iDInA, iDInB, iWriteA, iWriteB, oDOutA, oDOutB);
     

    input iClkA, iClkB, iWriteA, iWriteB;
    input [7:0] iAddrA, iAddrB;
    input [31:0] iDInA, iDInB;
    output reg [31:0] oDOutA, oDOutB;
    
    reg [7:0] rClr;
    reg [31:0] rContents[0:255];
        
    always @(posedge iClkA) begin
        if(iWriteA) begin
            rContents[iAddrA] <= iDInA;
        end
    end

    always @(posedge iClkB) begin
        if(iWriteB) begin
            rContents[iAddrB] <= iDInB;
        end
    end
    
    always @(posedge iClkA) begin
        if(!iWriteA) begin
            oDOutA <= rContents[iAddrA];
        end
    end
    
    always @(posedge iClkB) begin
        if(!iWriteB) begin
            oDOutB <= rContents[iAddrB];
        end
    end
            
endmodule