data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:15: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:17: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:52: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:56: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:58: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:61: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:64: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:67: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:69: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:74: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:76: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:80: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:83: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:91: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:95: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:98: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:107: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:111: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:114: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:122: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:126: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:129: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:137: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE.sv:140: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: Exiting due to 22 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_RC4_CORE();
	localparam CLK_PERIOD = 35;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg tb_n_rst_i;
	reg tb_rc4_dfb_i;
	reg tb_rc4_start_i;
	reg [31:0] tb_rc4_rdata_i;
	reg tb_sarrGenerated_i;
	reg tb_valReady_i;
	reg [7:0] tb_outputToXor_i;
	reg [19:0] tb_img_width_i;
	reg [19:0] tb_img_hight_i;
	reg [31:0] tb_rc4_wdata_o;
	reg [19:0] tb_rc4_pix_num_o;
	reg [1:0] tb_rc4_mode_o;
	reg tb_rc4_done_o;
	reg tb_genVal_o;
	reg tb_genStateArr_o;

	 RC4_CORE DUT (.clk(tb_clk),.n_rst_i(tb_n_rst_i),.rc4_dfb_i(tb_rc4_dfb_i),.rc4_start_i(tb_rc4_start_i),.rc4_rdata_i(tb_rc4_rdata_i),.sarrGenerated_i(tb_sarrGenerated_i),
			.valReady_i(tb_valReady_i),.outputToXor_i(tb_outputToXor_i),.img_width_i(tb_img_width_i),.img_hight_i(tb_img_hight_i),
			.rc4_wdata_o(tb_rc4_wdata_o),.rc4_pix_num_o(tb_rc4_pix_num_o),.rc4_mode_o(tb_rc4_mode_o),
			.rc4_done_o(tb_rc4_done_o),.genVal_o(tb_genVal_o),.genStateArr_o(tb_genStateArr_o));

initial
begin
	tb_n_rst_i = 0;
	tb_rc4_dfb_i = 0;
	tb_rc4_start_i = 0;
	tb_rc4_rdata_i = 0;
	tb_sarrGenerated_i = 0;
	tb_valReady_i = 0;
	tb_outputToXor_i = 0;;
	tb_img_width_i = 0;
	tb_img_hight_i = 0;
	@(negedge tb_clk);
	tb_n_rst_i = 1;
	tb_img_width_i = 3;
	tb_img_hight_i = 3;
	@(negedge tb_clk);
	tb_rc4_start_i = 1;
	@(negedge tb_clk);
	tb_rc4_start_i = 0;

	@(negedge tb_clk);
	tb_sarrGenerated_i = 1;

	@(negedge tb_clk);
	tb_sarrGenerated_i = 0;

	@(negedge tb_clk);
	tb_rc4_rdata_i = "HiPi";
	@(negedge tb_clk);
	tb_rc4_dfb_i = 1;



	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	@(negedge tb_clk);
	tb_valReady_i = 1;

	tb_outputToXor_i = 55;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);



	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	@(negedge tb_clk);
	tb_valReady_i = 1;

	tb_outputToXor_i = 41;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);




	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	@(negedge tb_clk);
	tb_valReady_i = 1;

	tb_outputToXor_i = 42;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);



	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	@(negedge tb_clk);
	tb_valReady_i = 1;

	tb_outputToXor_i = 55;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);



	@(negedge tb_clk);
	@(negedge tb_clk);
	@(negedge tb_clk);
	tb_rc4_dfb_i = 1;
	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;

	@(negedge tb_clk);
	

end
endmodule
module tb_RC4_CORE();

	localparam CLK_PERIOD = 35;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg tb_n_rst_i;
	reg tb_rc4_dfb_i;
	reg tb_rc4_start_i;
	reg [31:0] tb_rc4_rdata_i;
	reg tb_sarrGenerated_i;
	reg tb_valReady_i;
	reg [7:0] tb_outputToXor_i;
	reg [19:0] tb_img_width_i;
	reg [19:0] tb_img_hight_i;
	reg [31:0] tb_rc4_wdata_o;
	reg [19:0] tb_rc4_pix_num_o;
	reg [1:0] tb_rc4_mode_o;
	reg tb_rc4_done_o;
	reg tb_genVal_o;
	reg tb_genStateArr_o;

	 RC4_CORE DUT (.clk(tb_clk),.n_rst_i(tb_n_rst_i),.rc4_dfb_i(tb_rc4_dfb_i),.rc4_start_i(tb_rc4_start_i),.rc4_rdata_i(tb_rc4_rdata_i),.sarrGenerated_i(tb_sarrGenerated_i),
			.valReady_i(tb_valReady_i),.outputToXor_i(tb_outputToXor_i),.img_width_i(tb_img_width_i),.img_hight_i(tb_img_hight_i),
			.rc4_wdata_o(tb_rc4_wdata_o),.rc4_pix_num_o(tb_rc4_pix_num_o),.rc4_mode_o(tb_rc4_mode_o),
			.rc4_done_o(tb_rc4_done_o),.genVal_o(tb_genVal_o),.genStateArr_o(tb_genStateArr_o));

initial
begin
	tb_n_rst_i = 0;
	tb_rc4_dfb_i = 0;
	tb_rc4_start_i = 0;
	tb_rc4_rdata_i = 0;
	tb_sarrGenerated_i = 0;
	tb_valReady_i = 0;
	tb_outputToXor_i = 0;;
	tb_img_width_i = 0;
	tb_img_hight_i = 0;
	@(negedge tb_clk);
	tb_n_rst_i = 1;
	tb_img_width_i = 3;
	tb_img_hight_i = 3;
	@(negedge tb_clk);
	tb_rc4_start_i = 1;
	@(negedge tb_clk);
	tb_rc4_start_i = 0;

	@(negedge tb_clk);
	tb_sarrGenerated_i = 1;

	@(negedge tb_clk);
	tb_sarrGenerated_i = 0;

	@(negedge tb_clk);
	tb_rc4_rdata_i = "HiPi";
	@(negedge tb_clk);
	tb_rc4_dfb_i = 1;



	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	@(negedge tb_clk);
	tb_valReady_i = 1;

	tb_outputToXor_i = 55;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);



	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	@(negedge tb_clk);
	tb_valReady_i = 1;

	tb_outputToXor_i = 41;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);




	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	@(negedge tb_clk);
	tb_valReady_i = 1;

	tb_outputToXor_i = 42;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);



	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	@(negedge tb_clk);
	tb_valReady_i = 1;

	tb_outputToXor_i = 55;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);



	@(negedge tb_clk);
	@(negedge tb_clk);
	@(negedge tb_clk);
	tb_rc4_dfb_i = 1;
	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;

	@(negedge tb_clk);
	

end
endmodule