data/full_repos/permissive/132220215/bi_shift_reg_w_parallel_load.v
 line:24: before: "clr"
1: b'%Error: data/full_repos/permissive/132220215/bi_shift_reg_w_parallel_load.v:3: Cannot find include file: mux2.v\n`include "mux2.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/mux2.v\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/mux2.v.v\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/mux2.v.sv\n             mux2.v\n             mux2.v.v\n             mux2.v.sv\n             obj_dir/mux2.v\n             obj_dir/mux2.v.v\n             obj_dir/mux2.v.sv\n%Error: data/full_repos/permissive/132220215/bi_shift_reg_w_parallel_load.v:4: Cannot find include file: d_ff_asyn_clr.v\n`include "d_ff_asyn_clr.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module SREG_PARAL_LOAD #(parameter N = 8) (
	input Din_R,
	input Din_L,
	input clk,
	input clr,
	input [1:0] M,
	input [N-1:0] p_load,
	output Dout_R,
	output Dout_L);
 


 assign wr[-1] = Din_R;
 assign Dout_R = wr[N-1];
 assign wr[N] = Din_L;
 assign Dout_L = wr[0]; 
 
 wire [N:-1] wr;
 wire [N-1:0] D_inp;

 genvar i,j;



 generate
	 for(i=0;i<N;i=i+1)
		 mux2to1 #(.n(3)) MUX(.f(D_inp[i]),.sel(M),.in({wr[i-1],wr[i+1],p_load[i]}));

 endgenerate


 generate
	 for(j=0;j<N;j=j+1)
		 D_FF DFF(.clk(clk),.D(D_inp[j]),.clr(clr),.Q(wr[j]));
 endgenerate

endmodule
module SREG_PARAL_LOAD #(parameter N = 8) (
	input Din_R,
	input Din_L,
	input clk,
	input clr,
	input [1:0] M,
	input [N-1:0] p_load,
	output Dout_R,
	output Dout_L);

 


 assign wr[-1] = Din_R;
 assign Dout_R = wr[N-1];
 assign wr[N] = Din_L;
 assign Dout_L = wr[0]; 
 
 wire [N:-1] wr;
 wire [N-1:0] D_inp;

 genvar i,j;



 generate
	 for(i=0;i<N;i=i+1)
		 mux2to1 #(.n(3)) MUX(.f(D_inp[i]),.sel(M),.in({wr[i-1],wr[i+1],p_load[i]}));

 endgenerate


 generate
	 for(j=0;j<N;j=j+1)
		 D_FF DFF(.clk(clk),.D(D_inp[j]),.clr(clr),.Q(wr[j]));
 endgenerate

endmodule