data/full_repos/permissive/117337560/primitive_logic_gates/AND/and_gate_level.v
'utf-8' codec can't decode byte 0xb4 in position 1826: invalid start byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/117337560/primitive_logic_gates/AND/and_gate_level.v:16: Unsupported: Ignoring delay on this delayed statement.\n     #100 a=1;b=0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117337560/primitive_logic_gates/AND/and_gate_level.v:17: Unsupported: Ignoring delay on this delayed statement.\n     #100 a=0;b=1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/primitive_logic_gates/AND/and_gate_level.v:18: Unsupported: Ignoring delay on this delayed statement.\n     #100 a=1;b=1;\n     ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_and_gate_level();
    wire c;
    reg a,b;
    and_gate_level g(c,a,b);
    initial
 	begin
	    a=0;b=0;
	    #100 a=1;b=0;
	    #100 a=0;b=1;
	    #100 a=1;b=1;
	end
endmodule
module test_and_gate_level();

    wire c;
    reg a,b;
    and_gate_level g(c,a,b);
    initial
 	begin
	    a=0;b=0;
	    #100 a=1;b=0;
	    #100 a=0;b=1;
	    #100 a=1;b=1;
	end
endmodule