data/full_repos/permissive/110151336/lab_11/src/board/zeowaa/zeowaa.v
1: b'%Error: data/full_repos/permissive/110151336/lab_11/src/board/zeowaa/zeowaa.v:22: Cannot find file containing module: \'sm_top\'\n    sm_top sm_top\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/lab_11/src/board/zeowaa,data/full_repos/permissive/110151336/sm_top\n             data/full_repos/permissive/110151336/lab_11/src/board/zeowaa,data/full_repos/permissive/110151336/sm_top.v\n             data/full_repos/permissive/110151336/lab_11/src/board/zeowaa,data/full_repos/permissive/110151336/sm_top.sv\n             sm_top\n             sm_top.v\n             sm_top.sv\n             obj_dir/sm_top\n             obj_dir/sm_top.v\n             obj_dir/sm_top.sv\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_11/src/board/zeowaa/zeowaa.v:35: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s NOT generates 12 bits.\n                                                                                        : ... In instance zeowaa\n    assign led[11:1] = ~regData[11:0];\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/zeowaa/zeowaa.v:41: Cannot find file containing module: \'sm_clk_divider\'\n    sm_clk_divider hex_clk_divider\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/zeowaa/zeowaa.v:50: Cannot find file containing module: \'sm_hex_display_8\'\n    sm_hex_display_8 sm_hex_display_8\n    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module zeowaa
(
    input         clk_50,
    input  [ 5:2] key,
    input  [ 7:0] sw,
    output [11:0] led,
    output [ 7:0] hex,
    output [ 7:0] digit,
    output        buzzer
);

    wire          clkCpu;
    wire          clkIn     =  clk_50;
    wire          rst_n     =  key[4];
    wire          clkEnable =   ~sw[  7] | ~key[5];
    wire [  3:0 ] clkDevide = { ~sw[6:5], 2'b00 };
    wire [  4:0 ] regAddr   =   ~sw[4:0];
    wire [ 31:0 ] regData;


    sm_top sm_top
    (
        .clkIn      ( clkIn     ),
        .rst_n      ( rst_n     ),
        .clkDevide  ( clkDevide ),
        .clkEnable  ( clkEnable ),
        .clk        ( clkCpu    ),
        .regAddr    ( regAddr   ),
        .regData    ( regData   )
    );


    assign led[0]    = ~clkCpu;
    assign led[11:1] = ~regData[11:0];


    wire [ 31:0 ] h7segment = regData;
    wire clkHex;

    sm_clk_divider hex_clk_divider
    (
        .clkIn   ( clkIn  ),
        .rst_n   ( rst_n  ),
        .devide  ( 4'b0   ),
        .enable  ( 1'b1   ),
        .clkOut  ( clkHex )
    );

    sm_hex_display_8 sm_hex_display_8
    (
        .clock          ( clkHex    ),
        .resetn         ( rst_n     ),
        .number         ( h7segment ),
        .seven_segments ( hex[6:0]  ),
        .dot            ( hex[7]    ),
        .anodes         ( digit     )
    );

    assign buzzer = 1'b1;

endmodule
module zeowaa
(
    input         clk_50,
    input  [ 5:2] key,
    input  [ 7:0] sw,
    output [11:0] led,
    output [ 7:0] hex,
    output [ 7:0] digit,
    output        buzzer
);


    wire          clkCpu;
    wire          clkIn     =  clk_50;
    wire          rst_n     =  key[4];
    wire          clkEnable =   ~sw[  7] | ~key[5];
    wire [  3:0 ] clkDevide = { ~sw[6:5], 2'b00 };
    wire [  4:0 ] regAddr   =   ~sw[4:0];
    wire [ 31:0 ] regData;


    sm_top sm_top
    (
        .clkIn      ( clkIn     ),
        .rst_n      ( rst_n     ),
        .clkDevide  ( clkDevide ),
        .clkEnable  ( clkEnable ),
        .clk        ( clkCpu    ),
        .regAddr    ( regAddr   ),
        .regData    ( regData   )
    );


    assign led[0]    = ~clkCpu;
    assign led[11:1] = ~regData[11:0];


    wire [ 31:0 ] h7segment = regData;
    wire clkHex;

    sm_clk_divider hex_clk_divider
    (
        .clkIn   ( clkIn  ),
        .rst_n   ( rst_n  ),
        .devide  ( 4'b0   ),
        .enable  ( 1'b1   ),
        .clkOut  ( clkHex )
    );

    sm_hex_display_8 sm_hex_display_8
    (
        .clock          ( clkHex    ),
        .resetn         ( rst_n     ),
        .number         ( h7segment ),
        .seven_segments ( hex[6:0]  ),
        .dot            ( hex[7]    ),
        .anodes         ( digit     )
    );

    assign buzzer = 1'b1;

endmodule