data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:35: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117088385/rtl/e203/core,data/full_repos/permissive/117088385/e203_defines.v\n             data/full_repos/permissive/117088385/rtl/e203/core,data/full_repos/permissive/117088385/e203_defines.v.v\n             data/full_repos/permissive/117088385/rtl/e203/core,data/full_repos/permissive/117088385/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:43: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] alu_wbck_i_wdat,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:44: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  input  [`E203_RFIDX_WIDTH-1:0] alu_wbck_i_rdidx,\n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:52: Define or directive not defined: \'`E203_FLEN\'\n  input  [`E203_FLEN-1:0] longp_wbck_i_wdat,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:54: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  input  [`E203_RFIDX_WIDTH-1:0] longp_wbck_i_rdidx,\n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:60: Define or directive not defined: \'`E203_XLEN\'\n  output  [`E203_XLEN-1:0] rf_wbck_o_wdat,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:61: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  output  [`E203_RFIDX_WIDTH-1:0] rf_wbck_o_rdidx,\n           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:88: Define or directive not defined: \'`E203_FLEN\'\n  wire [`E203_FLEN-1:0] wbck_i_wdat;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:90: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  wire [`E203_RFIDX_WIDTH-1:0] wbck_i_rdidx;\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:100: Define or directive not defined: \'`E203_FLEN\'\n  assign wbck_i_wdat  = wbck_sel_alu ? {{`E203_FLEN-`E203_XLEN{1\'b0}},alu_wbck_i_wdat}  : longp_wbck_i_wdat;\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:100: Define or directive not defined: \'`E203_XLEN\'\n  assign wbck_i_wdat  = wbck_sel_alu ? {{`E203_FLEN-`E203_XLEN{1\'b0}},alu_wbck_i_wdat}  : longp_wbck_i_wdat;\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_exu_wbck.v:115: Define or directive not defined: \'`E203_XLEN\'\n  assign rf_wbck_o_wdat  = wbck_i_wdat[`E203_XLEN-1:0];\n                                       ^~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module e203_exu_wbck(



  input  alu_wbck_i_valid,
  output alu_wbck_i_ready,
  input  [`E203_XLEN-1:0] alu_wbck_i_wdat,
  input  [`E203_RFIDX_WIDTH-1:0] alu_wbck_i_rdidx,





  input  longp_wbck_i_valid,
  output longp_wbck_i_ready,
  input  [`E203_FLEN-1:0] longp_wbck_i_wdat,
  input  [5-1:0] longp_wbck_i_flags,
  input  [`E203_RFIDX_WIDTH-1:0] longp_wbck_i_rdidx,
  input  longp_wbck_i_rdfpu,



  output  rf_wbck_o_ena,
  output  [`E203_XLEN-1:0] rf_wbck_o_wdat,
  output  [`E203_RFIDX_WIDTH-1:0] rf_wbck_o_rdidx,


  
  input  clk,
  input  rst_n
  );






  wire wbck_ready4alu = (~longp_wbck_i_valid);
  wire wbck_sel_alu = alu_wbck_i_valid & wbck_ready4alu;

  wire wbck_ready4longp = 1'b1;
  wire wbck_sel_longp = longp_wbck_i_valid & wbck_ready4longp;





  wire rf_wbck_o_ready = 1'b1;

  wire wbck_i_ready;
  wire wbck_i_valid;
  wire [`E203_FLEN-1:0] wbck_i_wdat;
  wire [5-1:0] wbck_i_flags;
  wire [`E203_RFIDX_WIDTH-1:0] wbck_i_rdidx;
  wire wbck_i_rdfpu;

  assign alu_wbck_i_ready   = wbck_ready4alu   & wbck_i_ready;
  assign longp_wbck_i_ready = wbck_ready4longp & wbck_i_ready;

  assign wbck_i_valid = wbck_sel_alu ? alu_wbck_i_valid : longp_wbck_i_valid;
  `ifdef E203_FLEN_IS_32
  assign wbck_i_wdat  = wbck_sel_alu ? alu_wbck_i_wdat  : longp_wbck_i_wdat;
  `else
  assign wbck_i_wdat  = wbck_sel_alu ? {{`E203_FLEN-`E203_XLEN{1'b0}},alu_wbck_i_wdat}  : longp_wbck_i_wdat;
  `endif
  assign wbck_i_flags = wbck_sel_alu ? 5'b0  : longp_wbck_i_flags;
  assign wbck_i_rdidx = wbck_sel_alu ? alu_wbck_i_rdidx : longp_wbck_i_rdidx;
  assign wbck_i_rdfpu = wbck_sel_alu ? 1'b0 : longp_wbck_i_rdfpu;




  assign wbck_i_ready  = rf_wbck_o_ready;
  wire rf_wbck_o_valid = wbck_i_valid;

  wire wbck_o_ena   = rf_wbck_o_valid & rf_wbck_o_ready;

  assign rf_wbck_o_ena   = wbck_o_ena & (~wbck_i_rdfpu);
  assign rf_wbck_o_wdat  = wbck_i_wdat[`E203_XLEN-1:0];
  assign rf_wbck_o_rdidx = wbck_i_rdidx;


endmodule
module e203_exu_wbck(



  input  alu_wbck_i_valid,
  output alu_wbck_i_ready,
  input  [`E203_XLEN-1:0] alu_wbck_i_wdat,
  input  [`E203_RFIDX_WIDTH-1:0] alu_wbck_i_rdidx,





  input  longp_wbck_i_valid,
  output longp_wbck_i_ready,
  input  [`E203_FLEN-1:0] longp_wbck_i_wdat,
  input  [5-1:0] longp_wbck_i_flags,
  input  [`E203_RFIDX_WIDTH-1:0] longp_wbck_i_rdidx,
  input  longp_wbck_i_rdfpu,



  output  rf_wbck_o_ena,
  output  [`E203_XLEN-1:0] rf_wbck_o_wdat,
  output  [`E203_RFIDX_WIDTH-1:0] rf_wbck_o_rdidx,


  
  input  clk,
  input  rst_n
  );







  wire wbck_ready4alu = (~longp_wbck_i_valid);
  wire wbck_sel_alu = alu_wbck_i_valid & wbck_ready4alu;

  wire wbck_ready4longp = 1'b1;
  wire wbck_sel_longp = longp_wbck_i_valid & wbck_ready4longp;





  wire rf_wbck_o_ready = 1'b1;

  wire wbck_i_ready;
  wire wbck_i_valid;
  wire [`E203_FLEN-1:0] wbck_i_wdat;
  wire [5-1:0] wbck_i_flags;
  wire [`E203_RFIDX_WIDTH-1:0] wbck_i_rdidx;
  wire wbck_i_rdfpu;

  assign alu_wbck_i_ready   = wbck_ready4alu   & wbck_i_ready;
  assign longp_wbck_i_ready = wbck_ready4longp & wbck_i_ready;

  assign wbck_i_valid = wbck_sel_alu ? alu_wbck_i_valid : longp_wbck_i_valid;
  `ifdef E203_FLEN_IS_32
  assign wbck_i_wdat  = wbck_sel_alu ? alu_wbck_i_wdat  : longp_wbck_i_wdat;
  `else
  assign wbck_i_wdat  = wbck_sel_alu ? {{`E203_FLEN-`E203_XLEN{1'b0}},alu_wbck_i_wdat}  : longp_wbck_i_wdat;
  `endif
  assign wbck_i_flags = wbck_sel_alu ? 5'b0  : longp_wbck_i_flags;
  assign wbck_i_rdidx = wbck_sel_alu ? alu_wbck_i_rdidx : longp_wbck_i_rdidx;
  assign wbck_i_rdfpu = wbck_sel_alu ? 1'b0 : longp_wbck_i_rdfpu;




  assign wbck_i_ready  = rf_wbck_o_ready;
  wire rf_wbck_o_valid = wbck_i_valid;

  wire wbck_o_ena   = rf_wbck_o_valid & rf_wbck_o_ready;

  assign rf_wbck_o_ena   = wbck_o_ena & (~wbck_i_rdfpu);
  assign rf_wbck_o_wdat  = wbck_i_wdat[`E203_XLEN-1:0];
  assign rf_wbck_o_rdidx = wbck_i_rdidx;


endmodule