data/full_repos/permissive/184916587/OLD/Test_ALU.v
 line:37: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_ALU.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #0 rs1_num=32\'b00000000000010000010001010010110;rs2_num=32\'b01000001111000010111100100110110;alu_op=10\'b0000000001; \n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_ALU.v:28: Unsupported: Ignoring delay on this delayed statement.\n   #5 rs1_num=32\'b01001100000010010010000100011010;rs2_num=32\'b00000000001000010101100100110100;alu_op=10\'b0000000010; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_ALU.v:29: Unsupported: Ignoring delay on this delayed statement.\n   #5 rs1_num=32\'b10000010010010010010100010011100;rs2_num=32\'b00010001101001010000100000110010;alu_op=10\'b0000001001; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_ALU.v:30: Unsupported: Ignoring delay on this delayed statement.\n   #5 rs1_num=32\'b00100010000010001010001000010110;rs2_num=32\'b01010001011011111000100100110011;alu_op=10\'b0000001010; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_ALU.v:31: Unsupported: Ignoring delay on this delayed statement.\n   #5 rs1_num=32\'b00000100000010100010010010011000;rs2_num=32\'b00110001001000010100100100111111;alu_op=10\'b0000000001; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_ALU.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #5 rs1_num=32\'b00000000000010000010001010010110;rs2_num=32\'b01000001111000010111100100110110;alu_op=10\'b0000000011; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_ALU.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #5 rs1_num=32\'b01001100000010010010000100011010;rs2_num=32\'b00000000001000010101100100110100;alu_op=10\'b0000000101; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_ALU.v:34: Unsupported: Ignoring delay on this delayed statement.\n   #5 rs1_num=32\'b00000010010010010010100010011100;rs2_num=32\'b00010001101001010000100000110010;alu_op=10\'b0000000110; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_ALU.v:35: Unsupported: Ignoring delay on this delayed statement.\n   #5 rs1_num=32\'b00100010000010001010001000010110;rs2_num=32\'b01010001011011111000100100110011;alu_op=10\'b0000000111; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_ALU.v:36: Unsupported: Ignoring delay on this delayed statement.\n   #5 rs1_num=32\'b00000100000010100010010010011000;rs2_num=32\'b00110001001000010100100100111111;alu_op=10\'b0000001000; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_ALU.v:37: Unsupported: Ignoring delay on this delayed statement.\n   #5 $finish;\n   ^\n%Error: data/full_repos/permissive/184916587/OLD/Test_ALU.v:42: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("ALU.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/184916587/OLD/Test_ALU.v:43: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0,alu_test);\n   ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_test;
	reg[31:0] rs1_num;
	reg[31:0] rs2_num;

	reg[9:0] alu_op;

	wire[31:0] rd_num;

	ALU alu_test(
		.rs1_num(rs1_num),
		.rs2_num(rs2_num),
		.alu_op(alu_op),
		.rd_num(rd_num)
	);


	initial
		begin
			#0 rs1_num=32'b00000000000010000010001010010110;rs2_num=32'b01000001111000010111100100110110;alu_op=10'b0000000001;
			#5 rs1_num=32'b01001100000010010010000100011010;rs2_num=32'b00000000001000010101100100110100;alu_op=10'b0000000010;
			#5 rs1_num=32'b10000010010010010010100010011100;rs2_num=32'b00010001101001010000100000110010;alu_op=10'b0000001001;
			#5 rs1_num=32'b00100010000010001010001000010110;rs2_num=32'b01010001011011111000100100110011;alu_op=10'b0000001010;
			#5 rs1_num=32'b00000100000010100010010010011000;rs2_num=32'b00110001001000010100100100111111;alu_op=10'b0000000001;
			#5 rs1_num=32'b00000000000010000010001010010110;rs2_num=32'b01000001111000010111100100110110;alu_op=10'b0000000011;
			#5 rs1_num=32'b01001100000010010010000100011010;rs2_num=32'b00000000001000010101100100110100;alu_op=10'b0000000101;
			#5 rs1_num=32'b00000010010010010010100010011100;rs2_num=32'b00010001101001010000100000110010;alu_op=10'b0000000110;
			#5 rs1_num=32'b00100010000010001010001000010110;rs2_num=32'b01010001011011111000100100110011;alu_op=10'b0000000111;
			#5 rs1_num=32'b00000100000010100010010010011000;rs2_num=32'b00110001001000010100100100111111;alu_op=10'b0000001000;
			#5 $finish;
		end

	initial
		begin
			$dumpfile("ALU.vcd");
			$dumpvars(0,alu_test);
		end

endmodule
module alu_test;

	reg[31:0] rs1_num;
	reg[31:0] rs2_num;

	reg[9:0] alu_op;

	wire[31:0] rd_num;

	ALU alu_test(
		.rs1_num(rs1_num),
		.rs2_num(rs2_num),
		.alu_op(alu_op),
		.rd_num(rd_num)
	);


	initial
		begin
			#0 rs1_num=32'b00000000000010000010001010010110;rs2_num=32'b01000001111000010111100100110110;alu_op=10'b0000000001;
			#5 rs1_num=32'b01001100000010010010000100011010;rs2_num=32'b00000000001000010101100100110100;alu_op=10'b0000000010;
			#5 rs1_num=32'b10000010010010010010100010011100;rs2_num=32'b00010001101001010000100000110010;alu_op=10'b0000001001;
			#5 rs1_num=32'b00100010000010001010001000010110;rs2_num=32'b01010001011011111000100100110011;alu_op=10'b0000001010;
			#5 rs1_num=32'b00000100000010100010010010011000;rs2_num=32'b00110001001000010100100100111111;alu_op=10'b0000000001;
			#5 rs1_num=32'b00000000000010000010001010010110;rs2_num=32'b01000001111000010111100100110110;alu_op=10'b0000000011;
			#5 rs1_num=32'b01001100000010010010000100011010;rs2_num=32'b00000000001000010101100100110100;alu_op=10'b0000000101;
			#5 rs1_num=32'b00000010010010010010100010011100;rs2_num=32'b00010001101001010000100000110010;alu_op=10'b0000000110;
			#5 rs1_num=32'b00100010000010001010001000010110;rs2_num=32'b01010001011011111000100100110011;alu_op=10'b0000000111;
			#5 rs1_num=32'b00000100000010100010010010011000;rs2_num=32'b00110001001000010100100100111111;alu_op=10'b0000001000;
			#5 $finish;
		end

	initial
		begin
			$dumpfile("ALU.vcd");
			$dumpvars(0,alu_test);
		end

endmodule