data/full_repos/permissive/135822174/api/static/F721000/109_1/1/moore_machine.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/135822174/api/static/F721000/109_1/1/moore_machine.v:41: Cell has missing pin: \'div_clk\'\nclk_div myclk (clk,reset,div_clk);\n        ^~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/135822174/api/static/F721000/109_1/1/moore_machine.v:41: Signal definition not found, creating implicitly: \'div_clk\'\nclk_div myclk (clk,reset,div_clk);\n                         ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/135822174/api/static/F721000/109_1/1/moore_machine.v:41: Input port connection \'counter\' expects 32 bits on the pin connection, but pin connection\'s VARREF \'div_clk\' generates 1 bits.\n                                                                                                  : ... In instance moore_machine\nclk_div myclk (clk,reset,div_clk);\n                         ^~~~~~~\n%Error: Exiting due to 3 warning(s)\n'
module clk_div (clk,rst,counter,div_clk);
input clk,rst;
input [31:0]counter;
output div_clk;
reg div_clk;
reg [31:0]count;
always @ (posedge clk)
begin 
	if (!rst)
	begin 
	count <= 32'd0;
	div_clk <=1'b0;
	end
	else
	begin 
	if (count == `TimeExpire)
	begin 
	count<=32'd0;
	div_clk <=~div_clk;
	end
	else
	begin 
	count <= count + 32'd1;
end
end
end
endmodule
module clk_div (clk,rst,counter,div_clk);

input clk,rst;
input [31:0]counter;
output div_clk;
reg div_clk;
reg [31:0]count;
always @ (posedge clk)
begin 
	if (!rst)
	begin 
	count <= 32'd0;
	div_clk <=1'b0;
	end
	else
	begin 
	if (count == `TimeExpire)
	begin 
	count<=32'd0;
	div_clk <=~div_clk;
	end
	else
	begin 
	count <= count + 32'd1;
end
end
end
endmodule