data/full_repos/permissive/125592111/verilog/ID_EX_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/125592111/verilog/ID_EX_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n always #(tck/2) clk <= ~clk;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX_tb.v:35: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("id_ex_ah.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(-1, dut);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX_tb.v:37: Unsupported or unknown PLI call: $monitor\n  $monitor("%b", RegWrite_out, MemtoReg_out, Branch_out, MemRead_out, MemWrite_out, Jump_out,   RegDst_out, ALUSrc_out, ALUOp_out, jump_addr_out, PC_plus4_out, reg_read_data_1_out,  reg_read_data_2_out, immi_sign_extended_out, IF_ID_RegisterRs_out, IF_ID_RegisterRt_out, IF_ID_RegisterRd_out);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX_tb.v:76: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n   Branch_in <= $random(seed);\n                ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/125592111/verilog/ID_EX_tb.v:76: ../V3Ast.cpp:358: Null item passed to setOp1p\n   Branch_in <= $random(seed);\n             ^~\n                        ... See the manual and https://verilator.org for more assistance.\n'
module ID_EX_tb();

	parameter tck = 10;

	reg ID_Hazard_lwstall, ID_Hazard_Branch;
	reg Branch_in, MemRead_in, MemWrite_in, Jump_in;
	reg RegWrite_in;
	reg ALUSrc_in;
	reg [1:0] ALUOp_in, RegDst_in, MemtoReg_in;
	reg [31:0] jump_addr_in, PC_plus4_in;
	reg [31:0] reg_read_data_1_in, reg_read_data_2_in, immi_sign_extended_in;
	reg [4:0] IF_ID_RegisterRs_in, IF_ID_RegisterRt_in, IF_ID_RegisterRd_in;
	reg [5:0] IF_ID_funct_in;
	reg clk, rst; 
	
	wire RegWrite_out, MemtoReg_out;
	wire Branch_out, MemRead_out, MemWrite_out, Jump_out;
	wire RegDst_out, ALUSrc_out;
	wire [1:0] ALUOp_out;
	wire [31:0] jump_addr_out, PC_plus4_out;
	wire [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out;
	wire [4:0] IF_ID_RegisterRs_out, IF_ID_RegisterRt_out, IF_ID_RegisterRd_out;
	wire [5:0] IF_ID_funct_out;
	
	integer seed = 1;
	integer num_iter = 0 ;
	always #(tck/2) clk <= ~clk;
	
	ID_EX dut (
		ID_Hazard_lwstall, ID_Hazard_Branch, Branch_in, MemRead_in, MemWrite_in, Jump_in, 		RegWrite_in, MemtoReg_in, RegDst_in, ALUSrc_in, ALUOp_in, jump_addr_in, PC_plus4_in, 		reg_read_data_1_in, reg_read_data_2_in, immi_sign_extended_in, IF_ID_RegisterRs_in, IF_ID_RegisterRt_in, IF_ID_RegisterRd_in, IF_ID_funct_in, clk, rst, RegWrite_out, MemtoReg_out, Branch_out, MemRead_out, MemWrite_out, Jump_out, RegDst_out, ALUSrc_out, ALUOp_out, 		jump_addr_out, PC_plus4_out, reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out, 	IF_ID_RegisterRs_out, IF_ID_RegisterRt_out, IF_ID_RegisterRd_out, IF_ID_funct_out);
	
	initial begin
		$dumpfile("id_ex_ah.vcd");
		$dumpvars(-1, dut);
		$monitor("%b", RegWrite_out, MemtoReg_out, Branch_out, MemRead_out, MemWrite_out, Jump_out, 		RegDst_out, ALUSrc_out, ALUOp_out, jump_addr_out, PC_plus4_out, reg_read_data_1_out,  reg_read_data_2_out, immi_sign_extended_out, IF_ID_RegisterRs_out, IF_ID_RegisterRt_out, IF_ID_RegisterRd_out);
	end
	
	
	initial begin
		ID_Hazard_lwstall = 0;
		ID_Hazard_Branch = 	0;
		Branch_in = 		0;
		MemRead_in = 		0;
		MemWrite_in = 		0;
		Jump_in = 			0;
		RegWrite_in = 		0;
		MemtoReg_in = 		0;
		RegDst_in = 		0;
		ALUSrc_in = 		0;
		ALUOp_in = 			0;
		jump_addr_in = 		0;
		PC_plus4_in = 		0;
		reg_read_data_1_in = 0;
		reg_read_data_2_in = 0;
		immi_sign_extended_in = 0;
		IF_ID_RegisterRs_in = 0;
		IF_ID_RegisterRt_in = 0;
		IF_ID_RegisterRd_in = 0;
		IF_ID_funct_in = 0;
		clk = 0;
		rst = 0;
		
		
		
	end
	
	
	always @(posedge clk) begin
		if (rst) 
			rst = 0;
		else


			Branch_in <= $random(seed);
			MemRead_in <= $random(seed);
			MemWrite_in <= $random(seed);
			Jump_in <= $random(seed);
			RegWrite_in <= $random(seed);
			MemtoReg_in <= $random(seed);
			RegDst_in <= $random(seed);
			ALUSrc_in <= $random(seed);
			ALUOp_in <= $random(seed);
			jump_addr_in <= $random(seed);
			PC_plus4_in <= $random(seed);
			reg_read_data_1_in <= $random(seed);
			reg_read_data_2_in <= $random(seed);
			immi_sign_extended_in <= $random(seed);
			IF_ID_RegisterRs_in <= $random(seed);
			IF_ID_RegisterRt_in <= $random(seed);
			IF_ID_RegisterRd_in <= $random(seed);
			IF_ID_funct_in <= $random(seed);
			num_iter = num_iter +1 ;


		
			if (num_iter == 5) ID_Hazard_lwstall <= 1'b1;
			if (num_iter == 6) ID_Hazard_lwstall <= 1'b0;
			if (num_iter == 10) ID_Hazard_Branch <= 1'b1;
			if (num_iter == 11) ID_Hazard_Branch <= 1'b0; 

			if (num_iter > 2000)
				$finish;
	end

endmodule
module ID_EX_tb();


	parameter tck = 10;

	reg ID_Hazard_lwstall, ID_Hazard_Branch;
	reg Branch_in, MemRead_in, MemWrite_in, Jump_in;
	reg RegWrite_in;
	reg ALUSrc_in;
	reg [1:0] ALUOp_in, RegDst_in, MemtoReg_in;
	reg [31:0] jump_addr_in, PC_plus4_in;
	reg [31:0] reg_read_data_1_in, reg_read_data_2_in, immi_sign_extended_in;
	reg [4:0] IF_ID_RegisterRs_in, IF_ID_RegisterRt_in, IF_ID_RegisterRd_in;
	reg [5:0] IF_ID_funct_in;
	reg clk, rst; 
	
	wire RegWrite_out, MemtoReg_out;
	wire Branch_out, MemRead_out, MemWrite_out, Jump_out;
	wire RegDst_out, ALUSrc_out;
	wire [1:0] ALUOp_out;
	wire [31:0] jump_addr_out, PC_plus4_out;
	wire [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out;
	wire [4:0] IF_ID_RegisterRs_out, IF_ID_RegisterRt_out, IF_ID_RegisterRd_out;
	wire [5:0] IF_ID_funct_out;
	
	integer seed = 1;
	integer num_iter = 0 ;
	always #(tck/2) clk <= ~clk;
	
	ID_EX dut (
		ID_Hazard_lwstall, ID_Hazard_Branch, Branch_in, MemRead_in, MemWrite_in, Jump_in, 		RegWrite_in, MemtoReg_in, RegDst_in, ALUSrc_in, ALUOp_in, jump_addr_in, PC_plus4_in, 		reg_read_data_1_in, reg_read_data_2_in, immi_sign_extended_in, IF_ID_RegisterRs_in, IF_ID_RegisterRt_in, IF_ID_RegisterRd_in, IF_ID_funct_in, clk, rst, RegWrite_out, MemtoReg_out, Branch_out, MemRead_out, MemWrite_out, Jump_out, RegDst_out, ALUSrc_out, ALUOp_out, 		jump_addr_out, PC_plus4_out, reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out, 	IF_ID_RegisterRs_out, IF_ID_RegisterRt_out, IF_ID_RegisterRd_out, IF_ID_funct_out);
	
	initial begin
		$dumpfile("id_ex_ah.vcd");
		$dumpvars(-1, dut);
		$monitor("%b", RegWrite_out, MemtoReg_out, Branch_out, MemRead_out, MemWrite_out, Jump_out, 		RegDst_out, ALUSrc_out, ALUOp_out, jump_addr_out, PC_plus4_out, reg_read_data_1_out,  reg_read_data_2_out, immi_sign_extended_out, IF_ID_RegisterRs_out, IF_ID_RegisterRt_out, IF_ID_RegisterRd_out);
	end
	
	
	initial begin
		ID_Hazard_lwstall = 0;
		ID_Hazard_Branch = 	0;
		Branch_in = 		0;
		MemRead_in = 		0;
		MemWrite_in = 		0;
		Jump_in = 			0;
		RegWrite_in = 		0;
		MemtoReg_in = 		0;
		RegDst_in = 		0;
		ALUSrc_in = 		0;
		ALUOp_in = 			0;
		jump_addr_in = 		0;
		PC_plus4_in = 		0;
		reg_read_data_1_in = 0;
		reg_read_data_2_in = 0;
		immi_sign_extended_in = 0;
		IF_ID_RegisterRs_in = 0;
		IF_ID_RegisterRt_in = 0;
		IF_ID_RegisterRd_in = 0;
		IF_ID_funct_in = 0;
		clk = 0;
		rst = 0;
		
		
		
	end
	
	
	always @(posedge clk) begin
		if (rst) 
			rst = 0;
		else


			Branch_in <= $random(seed);
			MemRead_in <= $random(seed);
			MemWrite_in <= $random(seed);
			Jump_in <= $random(seed);
			RegWrite_in <= $random(seed);
			MemtoReg_in <= $random(seed);
			RegDst_in <= $random(seed);
			ALUSrc_in <= $random(seed);
			ALUOp_in <= $random(seed);
			jump_addr_in <= $random(seed);
			PC_plus4_in <= $random(seed);
			reg_read_data_1_in <= $random(seed);
			reg_read_data_2_in <= $random(seed);
			immi_sign_extended_in <= $random(seed);
			IF_ID_RegisterRs_in <= $random(seed);
			IF_ID_RegisterRt_in <= $random(seed);
			IF_ID_RegisterRd_in <= $random(seed);
			IF_ID_funct_in <= $random(seed);
			num_iter = num_iter +1 ;


		
			if (num_iter == 5) ID_Hazard_lwstall <= 1'b1;
			if (num_iter == 6) ID_Hazard_lwstall <= 1'b0;
			if (num_iter == 10) ID_Hazard_Branch <= 1'b1;
			if (num_iter == 11) ID_Hazard_Branch <= 1'b0; 

			if (num_iter > 2000)
				$finish;
	end

endmodule