data/full_repos/permissive/108561032/control.v
data/verilator_xmls/a5d2738b-868a-46b2-a43c-555adc061f75.xml
module control(instru,clk,Control,FFetch,FDecode,FExecute,FMemory);

input [5:0]instru;
input clk;
input FFetch;
input FDecode;
input FExecute;
input FMemory;











output reg [9:0] Control;

reg [9:0] aux;
wire [3:0] auxControl;








always @ (*)
begin 
    case(instru)
        6'b000_000: aux=10'b0100_100_010;
        6'b100_011: aux=10'b00_1111_0000;
        6'b101_011: aux=10'b0x1x001000;
        6'b000_100: aux=10'b0x0x000101;
        6'b111_111: aux=10'b00_1010_0000;
        6'b111_110: aux=10'b00_0000_0101;
        default:  aux=10'b00_1010_0000;        
    endcase

end

assign auxControl = {FFetch,FDecode,FExecute,FMemory};

always @(*)
begin
 if(auxControl == 4'b1111)
    Control = aux;
 else
    Control = aux;
    
end













endmodule
module control(instru,clk,Control,FFetch,FDecode,FExecute,FMemory);


input [5:0]instru;
input clk;
input FFetch;
input FDecode;
input FExecute;
input FMemory;











output reg [9:0] Control;

reg [9:0] aux;
wire [3:0] auxControl;








always @ (*)
begin 
    case(instru)
        6'b000_000: aux=10'b0100_100_010;
        6'b100_011: aux=10'b00_1111_0000;
        6'b101_011: aux=10'b0x1x001000;
        6'b000_100: aux=10'b0x0x000101;
        6'b111_111: aux=10'b00_1010_0000;
        6'b111_110: aux=10'b00_0000_0101;
        default:  aux=10'b00_1010_0000;        
    endcase

end

assign auxControl = {FFetch,FDecode,FExecute,FMemory};

always @(*)
begin
 if(auxControl == 4'b1111)
    Control = aux;
 else
    Control = aux;
    
end













endmodule