data/full_repos/permissive/201488448/2_circuits/1_combinational/05_gate.v
 line:10: before: "e"
data/verilator_xmls/175acea3-88a0-4f53-9170-d599024799e9.xml
module top_module (
    input in1,
    input in2,
    input in3,
    output out);

    assign	out = ~(in1^in2)^in3;
    
endmodule
module top_module (
    input in1,
    input in2,
    input in3,
    output out);


    assign	out = ~(in1^in2)^in3;
    
endmodule