data/full_repos/permissive/143278/ivltests/pr1740476b.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1740476b.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #1 ;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1740476b.v:19: Operator NEQCASE expects 32 bits on the LHS, but LHS\'s ARRAYSEL generates 4 bits.\n                                                                          : ... In instance main\n  if (dst[idx] !== idx) begin\n               ^~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire [3:0] src [15:0];
   wire [3:0] dst [15:0];

   genvar i;
   for (i = 0 ; i < 16; i = i+1) begin:bb
      buffer u (.out(dst[i]), .in(src[i]));
   end

   for (i = 0 ;  i < 16 ;  i = i+1) begin:drv
      assign src[i] = i;
   end

   integer   idx;
   initial begin
      #1 ;
      for (idx = 0 ;  idx < 16 ;  idx = idx+1) begin
	 if (dst[idx] !== idx) begin
	    $display("FAILED -- src[%0d]==%b, dst[%0d]==%b",
		     idx, src[idx], idx, dst[idx]);
	    $finish;
	 end
      end
      $display("PASSED");
   end

endmodule
module main;


   wire [3:0] src [15:0];
   wire [3:0] dst [15:0];

   genvar i;
   for (i = 0 ; i < 16; i = i+1) begin:bb
      buffer u (.out(dst[i]), .in(src[i]));
   end

   for (i = 0 ;  i < 16 ;  i = i+1) begin:drv
      assign src[i] = i;
   end

   integer   idx;
   initial begin
      #1 ;
      for (idx = 0 ;  idx < 16 ;  idx = idx+1) begin
	 if (dst[idx] !== idx) begin
	    $display("FAILED -- src[%0d]==%b, dst[%0d]==%b",
		     idx, src[idx], idx, dst[idx]);
	    $finish;
	 end
      end
      $display("PASSED");
   end

endmodule