data/full_repos/permissive/185386477/verilog/ww.v
None: at end of input
1: b'%Warning-PINMISSING: data/full_repos/permissive/185386477/verilog/ww.v:638: Cell has missing pin: \'zero_to_right\'\n ww_br_slice br_15(.clk(clk), .brn(br[15]),\n             ^~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/185386477/verilog/ww.v:638: Cell has missing pin: \'one_to_right\'\n ww_br_slice br_15(.clk(clk), .brn(br[15]),\n             ^~~~~\n%Warning-MULTITOP: data/full_repos/permissive/185386477/verilog/ww.v:22: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                       : ... Top module \'edgedet\'\nmodule edgedet(clk, reset, in, p);\n       ^~~~~~~\n                                                                       : ... Top module \'ww\'\nmodule ww(\n       ^~\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:66: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ff0 = \'o3740;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:67: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ff1 = \'o3741;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:68: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ff2 = \'o3742;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:69: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ff3 = \'o3743;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:70: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ff4 = \'o3744;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:71: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts0 = \'o3745;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:72: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts1 = \'o3746;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:73: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts2 = \'o3747;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:74: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts3 = \'o3750;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:75: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts4 = \'o3751;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:76: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts5 = \'o3752;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:77: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts6 = \'o3753;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:78: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts7 = \'o3754;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:79: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts8 = \'o3755;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:80: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts9 = \'o3756;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:81: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts10 = \'o3757;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:82: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts11 = \'o3760;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:83: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts12 = \'o3761;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:84: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts13 = \'o3762;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:85: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts14 = \'o3763;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:86: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts15 = \'o3764;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:87: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts16 = \'o3765;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:88: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts17 = \'o3766;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:89: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts18 = \'o3767;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:90: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts19 = \'o3770;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:91: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts20 = \'o3771;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:92: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts21 = \'o3772;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:93: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts22 = \'o3773;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:94: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts23 = \'o3774;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:95: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts24 = \'o3775;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:96: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts25 = \'o3776;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:97: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts26 = \'o3777;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:939: Little bit endian vector: MSB < LSB of bit range: 0:15\n input wire [0:15] sw_input,\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:944: Little bit endian vector: MSB < LSB of bit range: 0:15\n input wire [0:15] in,\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:945: Little bit endian vector: MSB < LSB of bit range: 0:15\n output wire [0:15] out\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:947: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] storage_ff;  \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:32: Little bit endian vector: MSB < LSB of bit range: 5:15\n reg [5:15] sw_pc = \'o3740;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:33: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ff_0 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:34: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ff_1 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:35: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ff_2 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:36: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ff_3 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:37: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ff_4 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:38: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_0 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:39: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_1 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:40: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_2 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:41: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_3 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:42: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_4 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:43: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_5 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:44: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_6 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:45: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_7 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:46: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_8 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:47: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_9 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:48: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_10 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:49: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_11 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:50: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_12 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:51: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_13 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:52: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_14 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:53: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_15 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:54: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_16 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:55: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_17 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:56: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_18 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:57: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_19 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:58: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_20 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:59: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_21 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:60: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_22 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:61: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_23 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:62: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_24 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:63: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_25 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:64: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_26 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:101: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] bus =\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:132: Little bit endian vector: MSB < LSB of bit range: 5:15\n reg [5:15] pc = 0;  \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:159: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] pr;   \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:169: Little bit endian vector: MSB < LSB of bit range: 0:4\n reg [0:4] cs;   \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:365: Little bit endian vector: MSB < LSB of bit range: 5:15\n reg [5:15] ss;   \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:464: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff = out_ff0 | out_ff1 | out_ff2 | out_ff3 | out_ff4;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:375: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ts =\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:668: Little bit endian vector: MSB < LSB of bit range: 11:15\n reg [11:15] sc;   \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:472: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] ar;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:494: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] ac;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:102: Operator AND expects 16 bits on the LHS, but LHS\'s REPLICATE generates 11 bits.\n                                                                     : ... In instance ww\n  {11{pc_to_bus}}&pc |\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:102: Operator AND expects 16 bits on the RHS, but RHS\'s VARREF \'pc\' generates 11 bits.\n                                                                     : ... In instance ww\n  {11{pc_to_bus}}&pc |\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:105: Operator AND expects 16 bits on the RHS, but RHS\'s VARREF \'ss\' generates 11 bits.\n                                                                     : ... In instance ww\n  {16{ss_to_bus}}&ss |\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:107: Operator AND expects 16 bits on the RHS, but RHS\'s VARREF \'sc\' generates 5 bits.\n                                                                     : ... In instance ww\n  {16{sc_to_bus}}&sc |\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:110: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] check_bus =\n      ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:111: Operator AND expects 16 bits on the LHS, but LHS\'s REPLICATE generates 11 bits.\n                                                                     : ... In instance ww\n  {11{pc_to_check}}&pc |\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:111: Operator AND expects 16 bits on the RHS, but RHS\'s VARREF \'pc\' generates 11 bits.\n                                                                     : ... In instance ww\n  {11{pc_to_check}}&pc |\n                   ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:141: Little bit endian vector: MSB < LSB of bit range: 0:1\n reg [0:1] pc_end_carry_dly = 0;  \n     ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:154: Operator OR expects 16 bits on the LHS, but LHS\'s VARREF \'pc\' generates 11 bits.\n                                                                     : ... In instance ww\n  if(pc_from_bus | pc_read_in_ff) pc <= pc | bus;  \n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:154: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s OR generates 16 bits.\n                                                                     : ... In instance ww\n  if(pc_from_bus | pc_read_in_ff) pc <= pc | bus;  \n                                     ^~\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:264: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg [0:2] pulse_cnt = 0;  \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:268: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg [0:2] delay_counter = 0;  \n     ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:371: Operator OR expects 16 bits on the LHS, but LHS\'s VARREF \'ss\' generates 11 bits.\n                                                                     : ... In instance ww\n  if(ss_from_bus) ss <= ss | bus;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:371: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s OR generates 16 bits.\n                                                                     : ... In instance ww\n  if(ss_from_bus) ss <= ss | bus;\n                     ^~\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:458: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] in_to_ff = {{5{storage_from_bus&~cs_td}}, {11{storage_from_bus}}}&bus;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:459: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff0;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:460: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff1;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:461: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff2;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:462: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff3;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:463: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff4;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:473: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] ar_neg = ~ar;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:480: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] ar_to_ac = {16{add_ar_to_ac}}&ar | {16{sub_ar_to_ac}}&~ar;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:495: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] ac_neg = ~ac;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:496: Little bit endian vector: MSB < LSB of bit range: 1:15\n wire [1:15] cry;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:503: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] ac_to_br16 = {16{ac_to_br}}&ac;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:506: Little bit endian vector: MSB < LSB of bit range: 1:15\n wire [1:15] carry_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:508: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] carry_to_left;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:509: Little bit endian vector: MSB < LSB of bit range: 1:15\n wire [1:15] zero_to_left;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:510: Little bit endian vector: MSB < LSB of bit range: 1:15\n wire [1:15] one_to_left;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:513: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] shift_left_n = {16{div_shift_left_pulse}} | {14{shift_left_pulse}};\n      ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:513: Operator OR expects 16 bits on the RHS, but RHS\'s REPLICATE generates 14 bits.\n                                                                     : ... In instance ww\n wire [0:15] shift_left_n = {16{div_shift_left_pulse}} | {14{shift_left_pulse}};\n                                                       ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:600: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] br_zero_to_left;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:601: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] br_one_to_left;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:592: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] br;   \n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:598: Little bit endian vector: MSB < LSB of bit range: 0:14\n wire [0:14] br_zero_to_right;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:599: Little bit endian vector: MSB < LSB of bit range: 0:14\n wire [0:14] br_one_to_right;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:678: Operator OR expects 16 bits on the LHS, but LHS\'s VARREF \'sc\' generates 5 bits.\n                                                                     : ... In instance ww\n  if(sc_from_bus) sc <= sc | bus;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:678: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s OR generates 16 bits.\n                                                                     : ... In instance ww\n  if(sc_from_bus) sc <= sc | bus;\n                     ^~\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:743: Little bit endian vector: MSB < LSB of bit range: 0:1\n reg [0:1] end_around_carry_dly = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:774: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] cr = 0;  \n     ^\n%Error: Exiting due to 122 warning(s)\n'
module ww_ac0(input wire clk,
	output wire acn,

	input wire from_ar,
	input wire clear,
	input wire complement,
	input wire shift_left,
	input wire shift_carry,

	input wire zero_from_right,
	input wire one_from_right,
	output reg zero_to_left,
	output reg one_to_left,

	input wire zero_from_left,
	input wire one_from_left,

	input wire carry_in,
	output wire carry_out,

	input wire carry_from_right,
	output wire carry_to_left
);
	reg ff01;
	wire carry_digit = from_ar & ff01;

	reg comp_dly;

	wire carry = carry_from_right | carry_in;
	assign carry_to_left = carry & ff01;

	assign carry_out = carry | carry_digit;

	initial zero_to_left = 0;
	initial one_to_left = 0;

	always @(posedge clk) begin
		comp_dly <= from_ar | carry;
		zero_to_left <= shift_left & ~ff01;
		one_to_left <= shift_left & ff01;

		if(clear) ff01 <= 0;
		if(complement | comp_dly) ff01 <= ~ff01;
		if(zero_from_right | zero_from_left) ff01 <= 0;
		if(one_from_right | one_from_left) ff01 <= 1;
	end

	assign acn = ff01;
endmodule
module ww_ac0(input wire clk,
	output wire acn,

	input wire from_ar,
	input wire clear,
	input wire complement,
	input wire shift_left,
	input wire shift_carry,

	input wire zero_from_right,
	input wire one_from_right,
	output reg zero_to_left,
	output reg one_to_left,

	input wire zero_from_left,
	input wire one_from_left,

	input wire carry_in,
	output wire carry_out,

	input wire carry_from_right,
	output wire carry_to_left
);

	reg ff01;
	wire carry_digit = from_ar & ff01;

	reg comp_dly;

	wire carry = carry_from_right | carry_in;
	assign carry_to_left = carry & ff01;

	assign carry_out = carry | carry_digit;

	initial zero_to_left = 0;
	initial one_to_left = 0;

	always @(posedge clk) begin
		comp_dly <= from_ar | carry;
		zero_to_left <= shift_left & ~ff01;
		one_to_left <= shift_left & ff01;

		if(clear) ff01 <= 0;
		if(complement | comp_dly) ff01 <= ~ff01;
		if(zero_from_right | zero_from_left) ff01 <= 0;
		if(one_from_right | one_from_left) ff01 <= 1;
	end

	assign acn = ff01;
endmodule