data/full_repos/permissive/143278/vhdl_tests/readout.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/readout.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module b(q);
   output q;

   assign q = 1;

endmodule
module b(q);

   output q;

   assign q = 1;

endmodule