data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/actel_ujtag/rtl/verilog/actel_ujtag.v
1: b"%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/actel_ujtag/rtl/verilog/actel_ujtag.v:108: Cannot find file containing module: 'UJTAG'\nUJTAG ujtag_inst (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/actel_ujtag/rtl/verilog,data/full_repos/permissive/17099167/UJTAG\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/actel_ujtag/rtl/verilog,data/full_repos/permissive/17099167/UJTAG.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/actel_ujtag/rtl/verilog,data/full_repos/permissive/17099167/UJTAG.sv\n             UJTAG\n             UJTAG.v\n             UJTAG.sv\n             obj_dir/UJTAG\n             obj_dir/UJTAG.v\n             obj_dir/UJTAG.sv\n%Error: Exiting due to 1 error(s)\n"
module actel_ujtag (




	tck_pad_i,
	tms_pad_i,
	tdi_pad_i,
	tdo_pad_o,
	trstb_pad_i,


	tck_o,
	debug_tdo_i,
	tdi_o,
	test_logic_reset_o,
	run_test_idle_o,
	shift_dr_o,
	capture_dr_o,
	pause_dr_o,
	update_dr_o,
	debug_select_o
);


input debug_tdo_i;
output tck_o;
output tdi_o;
output test_logic_reset_o;
output run_test_idle_o;
output shift_dr_o;
output capture_dr_o;
output pause_dr_o;
output update_dr_o;
output debug_select_o;
input tck_pad_i;
input tms_pad_i;
input tdi_pad_i;
output tdo_pad_o;
input trstb_pad_i;

wire debug_tdo_i;
wire tck_o;
wire tdi_o;
wire test_logic_reset_o;
wire run_test_idle_o;
wire shift_dr_o;
wire pause_dr_o;
wire update_dr_o;
wire debug_select_o;

wire [7:0] inst_reg;

wire tck_pad_i;
wire tms_pad_i;
wire tdi_pad_i;
wire tdo_pad_o;
wire trstb_pad_i;

UJTAG ujtag_inst (
.URSTB(test_logic_reset_o),
.UTDO(debug_tdo_i),
.UDRCK(tck_o),
.UDRCAP(capture_dr_o),
.UDRSH(shift_dr_o),
.UDRUPD(update_dr_o),
.UTDI(tdi_o),
.UIREG0(inst_reg[0]),
.UIREG1(inst_reg[1]),
.UIREG2(inst_reg[2]),
.UIREG3(inst_reg[3]),
.UIREG4(inst_reg[4]),
.UIREG5(inst_reg[5]),
.UIREG6(inst_reg[6]),
.UIREG7(inst_reg[7]),
.TCK(tck_pad_i),
.TDO(tdo_pad_o),
.TDI(tdi_pad_i),
.TMS(tms_pad_i),
.TRSTB(trstb_pad_i)
);


assign debug_select_o = (inst_reg == `UJTAG_DEBUG_IR) ? 1'b1 : 1'b0;

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;

endmodule
module actel_ujtag (




	tck_pad_i,
	tms_pad_i,
	tdi_pad_i,
	tdo_pad_o,
	trstb_pad_i,


	tck_o,
	debug_tdo_i,
	tdi_o,
	test_logic_reset_o,
	run_test_idle_o,
	shift_dr_o,
	capture_dr_o,
	pause_dr_o,
	update_dr_o,
	debug_select_o
);



input debug_tdo_i;
output tck_o;
output tdi_o;
output test_logic_reset_o;
output run_test_idle_o;
output shift_dr_o;
output capture_dr_o;
output pause_dr_o;
output update_dr_o;
output debug_select_o;
input tck_pad_i;
input tms_pad_i;
input tdi_pad_i;
output tdo_pad_o;
input trstb_pad_i;

wire debug_tdo_i;
wire tck_o;
wire tdi_o;
wire test_logic_reset_o;
wire run_test_idle_o;
wire shift_dr_o;
wire pause_dr_o;
wire update_dr_o;
wire debug_select_o;

wire [7:0] inst_reg;

wire tck_pad_i;
wire tms_pad_i;
wire tdi_pad_i;
wire tdo_pad_o;
wire trstb_pad_i;

UJTAG ujtag_inst (
.URSTB(test_logic_reset_o),
.UTDO(debug_tdo_i),
.UDRCK(tck_o),
.UDRCAP(capture_dr_o),
.UDRSH(shift_dr_o),
.UDRUPD(update_dr_o),
.UTDI(tdi_o),
.UIREG0(inst_reg[0]),
.UIREG1(inst_reg[1]),
.UIREG2(inst_reg[2]),
.UIREG3(inst_reg[3]),
.UIREG4(inst_reg[4]),
.UIREG5(inst_reg[5]),
.UIREG6(inst_reg[6]),
.UIREG7(inst_reg[7]),
.TCK(tck_pad_i),
.TDO(tdo_pad_o),
.TDI(tdi_pad_i),
.TMS(tms_pad_i),
.TRSTB(trstb_pad_i)
);


assign debug_select_o = (inst_reg == `UJTAG_DEBUG_IR) ? 1'b1 : 1'b0;

assign pause_dr_o = 1'b0;
assign run_test_idle_o = 1'b0;

endmodule