data/full_repos/permissive/157049472/Verilog Source Files/TopModule.v
1: b'%Error: Cannot find file containing module: Source\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Source\n             data/full_repos/permissive/157049472/Verilog/Source.v\n             data/full_repos/permissive/157049472/Verilog/Source.sv\n             Source\n             Source.v\n             Source.sv\n             obj_dir/Source\n             obj_dir/Source.v\n             obj_dir/Source.sv\n%Error: Cannot find file containing module: Files,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Files/TopModule.v\n%Error: Exiting due to 4 error(s)\n'
module TopModule( input wire clk, input wire rst,output wire instruction_bit,output 	wire alu_result_bit,
						output wire jump_offset_bit, output wire pc_bit );

	wire [31:0] pc;
	wire [31:0] instruction;
	wire [31:0] alu_result;
	wire[25:0] jump_offset;
	assign instruction_bit = instruction[0];
	assign pc_bit = pc[0];
	assign jump_offset_bit = jump_offset[0];
	assign alu_result_bit = alu_result[0];
	wire [5:0] opcode;
	wire [4:0] reg_addr_1, reg_addr_2, shift_amount;
	wire [10:0] opcode_ext;
	wire [20:0] immediate_const;
	wire [25:0] offset;
	InstructionDecoder ID(.instruction(instruction),.opcode(opcode), .reg_addr_1(reg_addr_1),.reg_addr_2(reg_addr_2),.shift_amount(shift_amount),
									.opcode_ext(opcode_ext),.immediate_const(immediate_const),.offset(offset));
	wire [3:0] alu_control;
	wire Branch, regWrite, MemWrite,MemRead,ALU_src,const_src,reg_data,reg_to_pc,regWrite_select;
	wire zero_flag, carry_flag, sign_flag, overflow_flag;
	InstructionFetch IF(.pc(pc),.instruction(instruction),.clk(clk),.rst(rst));
	ControlUnit CU (.opcode(opcode),.opcode_ext(opcode_ext),.clk(clk),.rst(rst),.alu_control(alu_control),
					 .Branch(Branch),.regWrite(regWrite),.MemRead(MemRead),.MemWrite(MemWrite),.ALU_src(ALU_src),.regWrite_select(regWrite_select),
					 .const_src(const_src),.reg_data(reg_data),.reg_to_pc(reg_to_pc));

	
	DataPath DP (.clk(clk),.rst(rst),.regWriteEnable(regWrite),.regAddr_1(reg_addr_1),.regAddr_2(reg_addr_2),.shift_amount(shift_amount), 
					 .npc(pc),.reg_to_pc(reg_to_pc), .regWrite_select(regWrite_select),
					 .MemRead(MemRead),.MemWrite(MemWrite),.alu_control(alu_control),.ALU_src(ALU_src),.const_src(const_src),.reg_data(reg_data),
					 .immediate_const(immediate_const),.alu_result(alu_result),.zero_flag(zero_flag),.carry_flag(carry_flag),
					 .sign_flag(sign_flag),.overflow_flag(overflow_flag)); 


	
	wire branch_success;
	PC_next PCN(.clk(clk),.rst(rst),.offset(jump_offset),.branch(branch_success),.pc(pc));
	
	BranchL BL(.clk(clk),.rst(rst),.opcode(opcode),.offset_in(offset),.rs_value(alu_result),.zflag_ff(zero_flag),
				  .cflag_ff(carry_flag),.oflag_ff(overflow_flag),.sflag_ff(sign_flag),.branch(branch_success),.offset_out(jump_offset));

	
endmodule
module TopModule( input wire clk, input wire rst,output wire instruction_bit,output 	wire alu_result_bit,
						output wire jump_offset_bit, output wire pc_bit );


	wire [31:0] pc;
	wire [31:0] instruction;
	wire [31:0] alu_result;
	wire[25:0] jump_offset;
	assign instruction_bit = instruction[0];
	assign pc_bit = pc[0];
	assign jump_offset_bit = jump_offset[0];
	assign alu_result_bit = alu_result[0];
	wire [5:0] opcode;
	wire [4:0] reg_addr_1, reg_addr_2, shift_amount;
	wire [10:0] opcode_ext;
	wire [20:0] immediate_const;
	wire [25:0] offset;
	InstructionDecoder ID(.instruction(instruction),.opcode(opcode), .reg_addr_1(reg_addr_1),.reg_addr_2(reg_addr_2),.shift_amount(shift_amount),
									.opcode_ext(opcode_ext),.immediate_const(immediate_const),.offset(offset));
	wire [3:0] alu_control;
	wire Branch, regWrite, MemWrite,MemRead,ALU_src,const_src,reg_data,reg_to_pc,regWrite_select;
	wire zero_flag, carry_flag, sign_flag, overflow_flag;
	InstructionFetch IF(.pc(pc),.instruction(instruction),.clk(clk),.rst(rst));
	ControlUnit CU (.opcode(opcode),.opcode_ext(opcode_ext),.clk(clk),.rst(rst),.alu_control(alu_control),
					 .Branch(Branch),.regWrite(regWrite),.MemRead(MemRead),.MemWrite(MemWrite),.ALU_src(ALU_src),.regWrite_select(regWrite_select),
					 .const_src(const_src),.reg_data(reg_data),.reg_to_pc(reg_to_pc));

	
	DataPath DP (.clk(clk),.rst(rst),.regWriteEnable(regWrite),.regAddr_1(reg_addr_1),.regAddr_2(reg_addr_2),.shift_amount(shift_amount), 
					 .npc(pc),.reg_to_pc(reg_to_pc), .regWrite_select(regWrite_select),
					 .MemRead(MemRead),.MemWrite(MemWrite),.alu_control(alu_control),.ALU_src(ALU_src),.const_src(const_src),.reg_data(reg_data),
					 .immediate_const(immediate_const),.alu_result(alu_result),.zero_flag(zero_flag),.carry_flag(carry_flag),
					 .sign_flag(sign_flag),.overflow_flag(overflow_flag)); 


	
	wire branch_success;
	PC_next PCN(.clk(clk),.rst(rst),.offset(jump_offset),.branch(branch_success),.pc(pc));
	
	BranchL BL(.clk(clk),.rst(rst),.opcode(opcode),.offset_in(offset),.rs_value(alu_result),.zflag_ff(zero_flag),
				  .cflag_ff(carry_flag),.oflag_ff(overflow_flag),.sflag_ff(sign_flag),.branch(branch_success),.offset_out(jump_offset));

	
endmodule