data/full_repos/permissive/129155059/04-struct_register/tester.v
 line:65: before: "("
1: b'%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:1: Cannot find include file: definitions.v\n`include "definitions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/04-struct_register,data/full_repos/permissive/129155059/definitions.v\n             data/full_repos/permissive/129155059/04-struct_register,data/full_repos/permissive/129155059/definitions.v.v\n             data/full_repos/permissive/129155059/04-struct_register,data/full_repos/permissive/129155059/definitions.v.sv\n             definitions.v\n             definitions.v.v\n             definitions.v.sv\n             obj_dir/definitions.v\n             obj_dir/definitions.v.v\n             obj_dir/definitions.v.sv\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:17: Define or directive not defined: \'`Ndir\'\n   reg  [`Ndir:0]           dir;\n         ^~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:17: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   reg  [`Ndir:0]           dir;\n              ^\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:30: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("registros.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:31: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1, tester);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:32: Unsupported or unknown PLI call: $monitor\n      $monitor("At time %t, Qcond = %h (%0d), S_OUTcond = %h (%0d), Qstruct = %h (%0d), S_OUTstruct = %h (%0d)",\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/04-struct_register/tester.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1 LE = 0;  \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/04-struct_register/tester.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:46: Define or directive not defined: \'`NumPwrCntr\'\n      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin\n                                      ^\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:46: syntax error, unexpected \')\', expecting \';\'\n      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin\n                                                     ^\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:61: Define or directive not defined: \'`LOAD\'\n      MODO = `LOAD;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:68: Define or directive not defined: \'`PUSH\'\n      MODO = `PUSH;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:73: Define or directive not defined: \'`PUSH\'\n      MODO = `PUSH;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:77: Define or directive not defined: \'`LOAD\'\n      MODO = `LOAD;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:81: Define or directive not defined: \'`CYCLE\'\n      MODO = `CYCLE;\n             ^~~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:85: Define or directive not defined: \'`LOAD\'\n      MODO = `LOAD;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:89: Define or directive not defined: \'`CYCLE\'\n      MODO = `CYCLE;\n             ^~~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:94: Define or directive not defined: \'`NumPwrCntr\'\n      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/tester.v:94: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin\n                                      ^\n%Error: Cannot continue\n'
module tester(  input      [3:0]  Qcond,
                input      [3:0]  Qstruct,
                input             S_OUTcond,
                input             S_OUTstruct,
                input             S_OUTnstruct,
                output reg [1:0]  MODO,
                output reg        DIR,
                output reg [3:0]  D,
                output reg        S_IN,
                output reg        ENB,
                output reg        CLK
                );

   reg  [31:0]              Contador;
   reg  [`Ndir:0]           dir;
   reg                      LE;
   wire [31:0]              dato;


   memTrans        m1(dir,
                      LE,
                      dato
                      );

   assign dato = (~LE)? Contador : 32'bz;

   initial begin
      $dumpfile("registros.vcd");
      $dumpvars(1, tester);
      $monitor("At time %t, Qcond = %h (%0d), S_OUTcond = %h (%0d), Qstruct = %h (%0d), S_OUTstruct = %h (%0d)",
               $time, Qcond, Qcond, S_OUTcond, S_OUTcond, Qstruct, Qstruct, S_OUTstruct, S_OUTstruct);
   end

   initial begin
      #1 LE = 0;
      CLK = 1'b0;
      ENB = 1'b0;
      D = 4'b0000;
      DIR = 1'b0;
      MODO = 2'b00;
      S_IN = 1'b0;
      #1
      Contador = 0;
      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin

        #1 Contador = 0;

      end

      repeat(2) #30 CLK = ~CLK;
      ENB = 1'b1;
      forever #30 CLK = ~CLK;
    end

    initial begin

      @(posedge ENB);
      D = 4'b1101;
      MODO = `LOAD;
      S_IN = 1'b0;
      DIR = 0;
      repeat(6) @(posedge CLK);

      S_IN = 1'b0;
      DIR = 0;
      MODO = `PUSH;
      repeat(6) @(posedge CLK);

      S_IN = 1'b1;
      DIR = 1;
      MODO = `PUSH;
      repeat(6) @(posedge CLK);

      D = 4'b1010;
      MODO = `LOAD;
      repeat(6) @(posedge CLK);

      DIR = 0;
      MODO = `CYCLE;
      repeat(6) @(posedge CLK);

      D = 4'b0110;
      MODO = `LOAD;
      repeat(6) @(posedge CLK);

      DIR = 1;
      MODO = `CYCLE;
      repeat(6) @(posedge CLK);


      #10 LE = 1;
      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin
        #1 Contador = dato;
        $display(,,"PwrCntr[%d]: %d", dir, Contador);
      end
      #1 $finish;
   end

endmodule
module tester(  input      [3:0]  Qcond,
                input      [3:0]  Qstruct,
                input             S_OUTcond,
                input             S_OUTstruct,
                input             S_OUTnstruct,
                output reg [1:0]  MODO,
                output reg        DIR,
                output reg [3:0]  D,
                output reg        S_IN,
                output reg        ENB,
                output reg        CLK
                );


   reg  [31:0]              Contador;
   reg  [`Ndir:0]           dir;
   reg                      LE;
   wire [31:0]              dato;


   memTrans        m1(dir,
                      LE,
                      dato
                      );

   assign dato = (~LE)? Contador : 32'bz;

   initial begin
      $dumpfile("registros.vcd");
      $dumpvars(1, tester);
      $monitor("At time %t, Qcond = %h (%0d), S_OUTcond = %h (%0d), Qstruct = %h (%0d), S_OUTstruct = %h (%0d)",
               $time, Qcond, Qcond, S_OUTcond, S_OUTcond, Qstruct, Qstruct, S_OUTstruct, S_OUTstruct);
   end

   initial begin
      #1 LE = 0;
      CLK = 1'b0;
      ENB = 1'b0;
      D = 4'b0000;
      DIR = 1'b0;
      MODO = 2'b00;
      S_IN = 1'b0;
      #1
      Contador = 0;
      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin

        #1 Contador = 0;

      end

      repeat(2) #30 CLK = ~CLK;
      ENB = 1'b1;
      forever #30 CLK = ~CLK;
    end

    initial begin

      @(posedge ENB);
      D = 4'b1101;
      MODO = `LOAD;
      S_IN = 1'b0;
      DIR = 0;
      repeat(6) @(posedge CLK);

      S_IN = 1'b0;
      DIR = 0;
      MODO = `PUSH;
      repeat(6) @(posedge CLK);

      S_IN = 1'b1;
      DIR = 1;
      MODO = `PUSH;
      repeat(6) @(posedge CLK);

      D = 4'b1010;
      MODO = `LOAD;
      repeat(6) @(posedge CLK);

      DIR = 0;
      MODO = `CYCLE;
      repeat(6) @(posedge CLK);

      D = 4'b0110;
      MODO = `LOAD;
      repeat(6) @(posedge CLK);

      DIR = 1;
      MODO = `CYCLE;
      repeat(6) @(posedge CLK);


      #10 LE = 1;
      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin
        #1 Contador = dato;
        $display(,,"PwrCntr[%d]: %d", dir, Contador);
      end
      #1 $finish;
   end

endmodule