data/full_repos/permissive/211235278/01. Single-cycle CPU/cpu.v
1: b'%Error: Cannot find file containing module: Single-cycle\n        ... Looked in:\n             data/full_repos/permissive/211235278/01./Single-cycle\n             data/full_repos/permissive/211235278/01./Single-cycle.v\n             data/full_repos/permissive/211235278/01./Single-cycle.sv\n             Single-cycle\n             Single-cycle.v\n             Single-cycle.sv\n             obj_dir/Single-cycle\n             obj_dir/Single-cycle.v\n             obj_dir/Single-cycle.sv\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/211235278\n%Error: Cannot find file containing module: data/full_repos/permissive/211235278/01.\n%Error: Cannot find file containing module: CPU/cpu.v\n%Error: Exiting due to 4 error(s)\n'
module cpu (
    output reg readM,
    output reg [`WORD_SIZE-1:0] address,
    inout [`WORD_SIZE-1:0] data,
    input inputReady,
    input reset_n,
    input clk,


    output reg [`WORD_SIZE-1:0] num_inst,
    output [`WORD_SIZE-1:0] output_port
);


    reg reading_instruction;
    reg [`WORD_SIZE-1:0] PC, nextPC;
    reg [`WORD_SIZE-1:0] instruction, dataReg;
    

    wire RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, OpenPort;
    wire [3:0] ALUOp;
    

    wire [`WORD_SIZE-1:0] ReadData1, ReadData2;
    

    wire bcond;
    wire [`WORD_SIZE-1:0] ALUResult;
    

    Control control(.opcode(instruction[15:12]),
                    .func(instruction[5:0]),
                    .RegDst(RegDst),
                    .Jump(Jump),
                    .Branch(Branch),
                    .MemRead(MemRead),
                    .MemtoReg(MemtoReg),
                    .ALUOp(ALUOp),
                    .MemWrite(MemWrite),
                    .ALUSrc(ALUSrc),
                    .RegWrite(RegWrite),
                    .OpenPort(OpenPort));
                    
    RF rf(.write(RegWrite),
          .clk(clk),
          .reset_n(reset_n),
          .addr1(instruction[11:10]),
          .addr2(instruction[9:8]),
          .addr3(RegDst ? instruction[7:6] : instruction[9:8]),
          .data1(ReadData1),
          .data2(ReadData2),
          .data3(MemtoReg ? dataReg : ALUResult));
          
    ALU alu(.A(ReadData1),
            .B(ALUSrc ? {{8{instruction[7]}}, instruction[7:0]} : ReadData2),
            .OP(ALUOp),
            .C(ALUResult),
            .bcond(bcond));
    
    always @(*) begin
        if (Jump) nextPC = {PC[15:12], instruction[11:0]};
        else if (Branch & bcond) nextPC = PC + {{8{instruction[7]}}, instruction[7:0]};
        else nextPC = PC + 1;
    end
    

    assign output_port = OpenPort ? ReadData1 : `WORD_SIZE'bz;
  
    always @(posedge clk, negedge reset_n) begin
        if (!reset_n) begin
            PC <= 0;
            nextPC <= 0;
            num_inst <= 1;
        end else begin
            PC <= nextPC;
            num_inst <= num_inst + 1;
        end
    end
    

    always @(PC) begin
        address = PC;
        readM = 1;
        reading_instruction = 1;
    end
    

    always @(posedge inputReady) begin
        if (reading_instruction) begin
            instruction <= data;
            readM <= 0;
            reading_instruction <= 0;
        end else begin
            dataReg <= data;
            readM <= 0;
        end
    end

endmodule
module cpu (
    output reg readM,
    output reg [`WORD_SIZE-1:0] address,
    inout [`WORD_SIZE-1:0] data,
    input inputReady,
    input reset_n,
    input clk,


    output reg [`WORD_SIZE-1:0] num_inst,
    output [`WORD_SIZE-1:0] output_port
);



    reg reading_instruction;
    reg [`WORD_SIZE-1:0] PC, nextPC;
    reg [`WORD_SIZE-1:0] instruction, dataReg;
    

    wire RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, OpenPort;
    wire [3:0] ALUOp;
    

    wire [`WORD_SIZE-1:0] ReadData1, ReadData2;
    

    wire bcond;
    wire [`WORD_SIZE-1:0] ALUResult;
    

    Control control(.opcode(instruction[15:12]),
                    .func(instruction[5:0]),
                    .RegDst(RegDst),
                    .Jump(Jump),
                    .Branch(Branch),
                    .MemRead(MemRead),
                    .MemtoReg(MemtoReg),
                    .ALUOp(ALUOp),
                    .MemWrite(MemWrite),
                    .ALUSrc(ALUSrc),
                    .RegWrite(RegWrite),
                    .OpenPort(OpenPort));
                    
    RF rf(.write(RegWrite),
          .clk(clk),
          .reset_n(reset_n),
          .addr1(instruction[11:10]),
          .addr2(instruction[9:8]),
          .addr3(RegDst ? instruction[7:6] : instruction[9:8]),
          .data1(ReadData1),
          .data2(ReadData2),
          .data3(MemtoReg ? dataReg : ALUResult));
          
    ALU alu(.A(ReadData1),
            .B(ALUSrc ? {{8{instruction[7]}}, instruction[7:0]} : ReadData2),
            .OP(ALUOp),
            .C(ALUResult),
            .bcond(bcond));
    
    always @(*) begin
        if (Jump) nextPC = {PC[15:12], instruction[11:0]};
        else if (Branch & bcond) nextPC = PC + {{8{instruction[7]}}, instruction[7:0]};
        else nextPC = PC + 1;
    end
    

    assign output_port = OpenPort ? ReadData1 : `WORD_SIZE'bz;
  
    always @(posedge clk, negedge reset_n) begin
        if (!reset_n) begin
            PC <= 0;
            nextPC <= 0;
            num_inst <= 1;
        end else begin
            PC <= nextPC;
            num_inst <= num_inst + 1;
        end
    end
    

    always @(PC) begin
        address = PC;
        readM = 1;
        reading_instruction = 1;
    end
    

    always @(posedge inputReady) begin
        if (reading_instruction) begin
            instruction <= data;
            readM <= 0;
            reading_instruction <= 0;
        end else begin
            dataReg <= data;
            readM <= 0;
        end
    end

endmodule