data/full_repos/permissive/104053853/digitron.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/104053853/digitron.v:22: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'frequency_divider\'\nmodule frequency_divider (input clock,\n       ^~~~~~~~~~~~~~~~~\n                                                                     : ... Top module \'hello_printer\'\nmodule hello_printer (input switch,\n       ^~~~~~~~~~~~~\n                                                                     : ... Top module \'fin_printer\'\nmodule fin_printer (input switch,\n       ^~~~~~~~~~~\n                                                                     : ... Top module \'digit_printer\'\nmodule digit_printer (input switch,\n       ^~~~~~~~~~~~~\n                                                                     : ... Top module \'bi_printer\'\nmodule bi_printer (input [7:0] seq1,\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module fin_printer (input switch,
                   input clock,
                   output reg [7:0] seq,
                   output reg [7:0] an);
parameter character_f = 8'b01110001,
         character_i = 8'b11011111,
         character_n = 8'b11010101;
parameter A5 = 8'b11011111,
         A6 = 8'b10111111,
         A7 = 8'b01111111;

reg [2:0] count;

initial
begin
 count = 0;
end

always @ (posedge clock)
begin
if (switch)
 begin
   case (count)
   0: begin seq <= character_f; an <= A5; end
   1: begin seq <= character_i; an <= A6; end
   2: begin seq <= character_n; an <= A7; end
   default: begin seq <= character_f; an <= A5; end
   endcase
   if (count == 3) count <= 0; else count <= count + 1;
 end
 else
 begin
   seq <= 8'b11111111;
   an <= 8'b11111111;
 end
end
endmodule
module fin_printer (input switch,
                   input clock,
                   output reg [7:0] seq,
                   output reg [7:0] an);

parameter character_f = 8'b01110001,
         character_i = 8'b11011111,
         character_n = 8'b11010101;
parameter A5 = 8'b11011111,
         A6 = 8'b10111111,
         A7 = 8'b01111111;

reg [2:0] count;

initial
begin
 count = 0;
end

always @ (posedge clock)
begin
if (switch)
 begin
   case (count)
   0: begin seq <= character_f; an <= A5; end
   1: begin seq <= character_i; an <= A6; end
   2: begin seq <= character_n; an <= A7; end
   default: begin seq <= character_f; an <= A5; end
   endcase
   if (count == 3) count <= 0; else count <= count + 1;
 end
 else
 begin
   seq <= 8'b11111111;
   an <= 8'b11111111;
 end
end
endmodule