data/full_repos/permissive/123043192/FPGA/ArduCamModule/ArduCamModule.srcs/sources_1/new/sccb.v
data/verilator_xmls/c912e6bb-5b2a-4d65-beb6-ec228469a1e0.xml
module sccb #(parameter CLK = 24000000) (
    input wire clk,
    input wire [15:0] addr_data,
    input wire sda_in,
    output reg [7:0] reg_loc,
    output reg scl,
    output reg sda_out);
    
    localparam CAMERA_ID_W = 8'h84;
    localparam IDLE = 0;
    localparam START_TX = 1;
    localparam START_DATA_TX = 2;
	localparam LOAD_FIRST_BIT = 3;
    localparam LOAD_DATA = 4;
    localparam SEND_BIT = 5;
	localparam END_BIT = 6;
    localparam STOP_DATA_TX = 7;
    localparam STOP_TX = 8;
    localparam WAIT = 9;

    reg [3:0] state = IDLE;
    reg [3:0] state_return = IDLE;
    reg [1:0] phase = 0;
    reg [3:0] i = 8;
    reg [7:0] reg_loc_val = 0;
    reg ready = 1;
    reg [5:0] wait_time = 0;
    reg [7:0] tx_data = 0;
    reg [7:0] addr = 0;
    reg [7:0] data = 0;

    initial begin
        scl = 1;
        sda_out = 1;
		reg_loc = reg_loc_val;
    end

    always@(posedge clk) begin
        case(state)
            IDLE: begin
                reg_loc = reg_loc_val;
                if(ready && reg_loc < 73) begin
                    state = START_TX;
                    reg_loc_val = reg_loc_val + 1;

                    ready = 0;
                end
            end

            START_TX: begin
                sda_out = 0;
                wait_time = 22;
                state = WAIT;
                state_return = START_DATA_TX;

             end

            START_DATA_TX: begin
				addr = addr_data[15:8];
                data = addr_data[7:0];
                scl = 0;
                wait_time = 10;
                state = WAIT;
                state_return = LOAD_DATA;

            end
				
			LOAD_FIRST_BIT: begin
				 sda_out = CAMERA_ID_W[i-1];
				 i = i - 1;
				 wait_time = 28;
				 state = WAIT;
				 state_return = SEND_BIT;
			end

            LOAD_DATA: begin
			    case(phase)
                    0: begin
                        tx_data = CAMERA_ID_W;
                    end
                    
                    1: begin
                        tx_data = addr;
                    end

                    2: begin
                        tx_data = data;
                    end
                endcase
                if(i > 0) begin
                    sda_out = tx_data[i-1];
                    i = i - 1;
                end
                else begin
                    sda_out = 0;
                    phase = phase + 1;
						  i = 8;
                end
                wait_time = 29;
                state = WAIT;
                state_return = SEND_BIT;
                
            end
    
            SEND_BIT: begin
				scl = 1;
			    wait_time = 22;
                state = WAIT;
                state_return = END_BIT;
            end

            END_BIT: begin
                scl = 0;
                wait_time = 9;
                state = WAIT;
                if(phase < 3) begin
                    state_return = LOAD_DATA;
                end
                else begin
                    state_return = STOP_DATA_TX;
						  phase = 0;
                end
            end

            STOP_DATA_TX: begin
                scl = 1;
                wait_time = 22;
                state = WAIT;
                state_return = 8;
            end

            STOP_TX: begin
                sda_out = 1;
                wait_time = 38;
                state = WAIT;
                state_return = IDLE;
                ready = 1;
            end

            WAIT: begin
                if(wait_time == 0) begin
                    state = state_return;
                end
                else begin
                    wait_time = wait_time - 1;
                end
            end
        endcase
    end

endmodule
module sccb #(parameter CLK = 24000000) (
    input wire clk,
    input wire [15:0] addr_data,
    input wire sda_in,
    output reg [7:0] reg_loc,
    output reg scl,
    output reg sda_out);

    
    localparam CAMERA_ID_W = 8'h84;
    localparam IDLE = 0;
    localparam START_TX = 1;
    localparam START_DATA_TX = 2;
	localparam LOAD_FIRST_BIT = 3;
    localparam LOAD_DATA = 4;
    localparam SEND_BIT = 5;
	localparam END_BIT = 6;
    localparam STOP_DATA_TX = 7;
    localparam STOP_TX = 8;
    localparam WAIT = 9;

    reg [3:0] state = IDLE;
    reg [3:0] state_return = IDLE;
    reg [1:0] phase = 0;
    reg [3:0] i = 8;
    reg [7:0] reg_loc_val = 0;
    reg ready = 1;
    reg [5:0] wait_time = 0;
    reg [7:0] tx_data = 0;
    reg [7:0] addr = 0;
    reg [7:0] data = 0;

    initial begin
        scl = 1;
        sda_out = 1;
		reg_loc = reg_loc_val;
    end

    always@(posedge clk) begin
        case(state)
            IDLE: begin
                reg_loc = reg_loc_val;
                if(ready && reg_loc < 73) begin
                    state = START_TX;
                    reg_loc_val = reg_loc_val + 1;

                    ready = 0;
                end
            end

            START_TX: begin
                sda_out = 0;
                wait_time = 22;
                state = WAIT;
                state_return = START_DATA_TX;

             end

            START_DATA_TX: begin
				addr = addr_data[15:8];
                data = addr_data[7:0];
                scl = 0;
                wait_time = 10;
                state = WAIT;
                state_return = LOAD_DATA;

            end
				
			LOAD_FIRST_BIT: begin
				 sda_out = CAMERA_ID_W[i-1];
				 i = i - 1;
				 wait_time = 28;
				 state = WAIT;
				 state_return = SEND_BIT;
			end

            LOAD_DATA: begin
			    case(phase)
                    0: begin
                        tx_data = CAMERA_ID_W;
                    end
                    
                    1: begin
                        tx_data = addr;
                    end

                    2: begin
                        tx_data = data;
                    end
                endcase
                if(i > 0) begin
                    sda_out = tx_data[i-1];
                    i = i - 1;
                end
                else begin
                    sda_out = 0;
                    phase = phase + 1;
						  i = 8;
                end
                wait_time = 29;
                state = WAIT;
                state_return = SEND_BIT;
                
            end
    
            SEND_BIT: begin
				scl = 1;
			    wait_time = 22;
                state = WAIT;
                state_return = END_BIT;
            end

            END_BIT: begin
                scl = 0;
                wait_time = 9;
                state = WAIT;
                if(phase < 3) begin
                    state_return = LOAD_DATA;
                end
                else begin
                    state_return = STOP_DATA_TX;
						  phase = 0;
                end
            end

            STOP_DATA_TX: begin
                scl = 1;
                wait_time = 22;
                state = WAIT;
                state_return = 8;
            end

            STOP_TX: begin
                sda_out = 1;
                wait_time = 38;
                state = WAIT;
                state_return = IDLE;
                ready = 1;
            end

            WAIT: begin
                if(wait_time == 0) begin
                    state = state_return;
                end
                else begin
                    wait_time = wait_time - 1;
                end
            end
        endcase
    end

endmodule