data/full_repos/permissive/20951436/Code/fpga code/advanced code/Advanced code.v
1: b'%Error: Cannot find file containing module: code/advanced\n        ... Looked in:\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.v\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.sv\n             code/advanced\n             code/advanced.v\n             code/advanced.sv\n             obj_dir/code/advanced\n             obj_dir/code/advanced.v\n             obj_dir/code/advanced.sv\n%Error: Cannot find file containing module: code,data/full_repos/permissive/20951436\n%Error: Cannot find file containing module: data/full_repos/permissive/20951436/Code/fpga\n%Error: Cannot find file containing module: code/Advanced\n%Error: Cannot find file containing module: code.v\n%Error: Exiting due to 5 error(s)\n'
module fourmot_testing (input clk, input en, input [2:0] des_rot0, des_rot1, des_rot2, des_rot3, input [3:0] dir, input [3:0] pulses, input PWM, output [3:0] sig_to_mot, dirp, dirn, output [8:0] count_pulse, output reg [1:0] pulse_state, input pulse_change, output reg [3:0] en_controller, output reg state);


	initial pulse_state<=0;
	wire [8:0] pulse01, pulse23, count_pulse_NE, count_pulse_NW, count_pulse_SE, count_pulse_SW;

	assign count_pulse = (pulse_state[1] ? pulse23 : pulse01);
	assign pulse01 = (pulse_state[0] ? count_pulse_NW : count_pulse_NE);
	assign pulse23 = (pulse_state[0] ? count_pulse_SW : count_pulse_SE);
	always @(posedge pulse_change) pulse_state<=pulse_state+1;


initial en_controller<=0;
	reg [3:0] en_timer; initial en_timer<=0;
	wire clk_calc, clk_PWM; assign clk_calc = clk; assign clk_PWM = clk;
	wire [4:0] speed0, speed1, speed2, speed3; wire [3:0] comp_cont;

	wire [31:0] des_rot0_inp, des_rot1_inp, des_rot2_inp, des_rot3_inp;
	assign des_rot0_inp = {24'h0,des_rot0,3'h0};
	assign des_rot1_inp = {24'h0,des_rot1,3'h0};
	assign des_rot2_inp = {24'h0,des_rot2,3'h0};
	assign des_rot3_inp = {24'h0,des_rot3,3'h0};

	controller mot_control_mod_NE(clk_calc, en_controller[0], des_rot0_inp, dir[0], pulses[0], speed0, comp_cont[0], count_pulse_NE);
	controller mot_control_mod_NW(clk_calc, en_controller[1], des_rot1_inp, dir[1], pulses[1], speed1, comp_cont[1], count_pulse_NW);
	controller mot_control_mod_SE(clk_calc, en_controller[2], des_rot2_inp, dir[2], pulses[2], speed2, comp_cont[2], count_pulse_SE);
	controller mot_control_mod_SW(clk_calc, en_controller[3], des_rot3_inp, dir[3], pulses[3], speed3, comp_cont[3], count_pulse_SW);


	PWM_timer mot_timer_mod_NE(clk_PWM, speed0, (en_timer[0] & PWM), sig_to_mot[0], dirp[0], dirn[0]);
	PWM_timer mot_timer_mod_NW(clk_PWM, speed1, (en_timer[1] & PWM), sig_to_mot[1], dirp[1], dirn[1]);
	PWM_timer mot_timer_mod_SE(clk_PWM, speed2, (en_timer[2] & PWM), sig_to_mot[2], dirp[2], dirn[2]);
	PWM_timer mot_timer_mod_SW(clk_PWM, speed3, (en_timer[3] & PWM), sig_to_mot[3], dirp[3], dirn[3]);


	initial state<=0;
	wire [3:0] len_diff = dir;
	reg state_en; initial state_en<=0;
	reg en_hist; initial en_hist<=0;
	always @(negedge clk) begin
		en_hist<=en;
		case (state)
			0: begin
				en_controller<=4'h0; en_timer<=4'h0;
				if (en && ~en_hist) begin
					state<=1;
				end
			end
			1: begin
				en_controller<=4'hF; en_timer<=4'hF;
				if (&comp_cont | ~en) state<=0;
			end
		endcase
	end
	
endmodule
module fourmot_testing (input clk, input en, input [2:0] des_rot0, des_rot1, des_rot2, des_rot3, input [3:0] dir, input [3:0] pulses, input PWM, output [3:0] sig_to_mot, dirp, dirn, output [8:0] count_pulse, output reg [1:0] pulse_state, input pulse_change, output reg [3:0] en_controller, output reg state);



	initial pulse_state<=0;
	wire [8:0] pulse01, pulse23, count_pulse_NE, count_pulse_NW, count_pulse_SE, count_pulse_SW;

	assign count_pulse = (pulse_state[1] ? pulse23 : pulse01);
	assign pulse01 = (pulse_state[0] ? count_pulse_NW : count_pulse_NE);
	assign pulse23 = (pulse_state[0] ? count_pulse_SW : count_pulse_SE);
	always @(posedge pulse_change) pulse_state<=pulse_state+1;


initial en_controller<=0;
	reg [3:0] en_timer; initial en_timer<=0;
	wire clk_calc, clk_PWM; assign clk_calc = clk; assign clk_PWM = clk;
	wire [4:0] speed0, speed1, speed2, speed3; wire [3:0] comp_cont;

	wire [31:0] des_rot0_inp, des_rot1_inp, des_rot2_inp, des_rot3_inp;
	assign des_rot0_inp = {24'h0,des_rot0,3'h0};
	assign des_rot1_inp = {24'h0,des_rot1,3'h0};
	assign des_rot2_inp = {24'h0,des_rot2,3'h0};
	assign des_rot3_inp = {24'h0,des_rot3,3'h0};

	controller mot_control_mod_NE(clk_calc, en_controller[0], des_rot0_inp, dir[0], pulses[0], speed0, comp_cont[0], count_pulse_NE);
	controller mot_control_mod_NW(clk_calc, en_controller[1], des_rot1_inp, dir[1], pulses[1], speed1, comp_cont[1], count_pulse_NW);
	controller mot_control_mod_SE(clk_calc, en_controller[2], des_rot2_inp, dir[2], pulses[2], speed2, comp_cont[2], count_pulse_SE);
	controller mot_control_mod_SW(clk_calc, en_controller[3], des_rot3_inp, dir[3], pulses[3], speed3, comp_cont[3], count_pulse_SW);


	PWM_timer mot_timer_mod_NE(clk_PWM, speed0, (en_timer[0] & PWM), sig_to_mot[0], dirp[0], dirn[0]);
	PWM_timer mot_timer_mod_NW(clk_PWM, speed1, (en_timer[1] & PWM), sig_to_mot[1], dirp[1], dirn[1]);
	PWM_timer mot_timer_mod_SE(clk_PWM, speed2, (en_timer[2] & PWM), sig_to_mot[2], dirp[2], dirn[2]);
	PWM_timer mot_timer_mod_SW(clk_PWM, speed3, (en_timer[3] & PWM), sig_to_mot[3], dirp[3], dirn[3]);


	initial state<=0;
	wire [3:0] len_diff = dir;
	reg state_en; initial state_en<=0;
	reg en_hist; initial en_hist<=0;
	always @(negedge clk) begin
		en_hist<=en;
		case (state)
			0: begin
				en_controller<=4'h0; en_timer<=4'h0;
				if (en && ~en_hist) begin
					state<=1;
				end
			end
			1: begin
				en_controller<=4'hF; en_timer<=4'hF;
				if (&comp_cont | ~en) state<=0;
			end
		endcase
	end
	
endmodule