data/full_repos/permissive/117026779/sim/Test_AmbientLightSensor.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_AmbientLightSensor.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_AmbientLightSensor.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_AmbientLightSensor.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_AmbientLightSensor.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_AmbientLightSensor.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_AmbientLightSensor.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_AmbientLightSensor.v:112: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_AmbientLightSensor.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: data/full_repos/permissive/117026779/sim/Test_AmbientLightSensor.v:39: Cannot find file containing module: \'AmbientLightSensor\'\nAmbientLightSensor U0(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/AmbientLightSensor\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/AmbientLightSensor.v\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/AmbientLightSensor.sv\n             AmbientLightSensor\n             AmbientLightSensor.v\n             AmbientLightSensor.sv\n             obj_dir/AmbientLightSensor\n             obj_dir/AmbientLightSensor.v\n             obj_dir/AmbientLightSensor.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_AmbientLightSensor;

parameter FULL_CYCLE = 32'd16_000;

reg success_flag;

reg clk, rst;
wire [31:0] data;

reg  oe;
reg  trigger;
reg  sdata;
wire cs;
wire sclk;
wire done;

AmbientLightSensor U0(
    .clk(clk),
    .rst(rst),
    .oe(oe),
    .trigger(trigger),
    .sdata(sdata),
    .sclk(sclk),
    .cs(cs),
    .done(done),
    .data(data)
);

integer i;

task RESET;
begin
	success_flag = 1;
    rst = 0;
    oe  = 0;
    clk = 0;
    #5
    rst = 1;
    #5
    rst = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask













initial begin
    #10
    #10
	RESET;
	trigger = 1;
	sdata 	= 1;
    CLOCK(FULL_CYCLE/2);
	trigger = 0;
    CLOCK(FULL_CYCLE/2);
    oe = 1;
    CLOCK(FULL_CYCLE);


	if (success_flag == 0) begin
		$display("*FAILED* TEST!");
	end
	else begin
		$display("**PASSED** TEST!");
	end

    #10 $stop;
    #5 $finish;
end

endmodule
module Test_AmbientLightSensor;


parameter FULL_CYCLE = 32'd16_000;

reg success_flag;

reg clk, rst;
wire [31:0] data;

reg  oe;
reg  trigger;
reg  sdata;
wire cs;
wire sclk;
wire done;

AmbientLightSensor U0(
    .clk(clk),
    .rst(rst),
    .oe(oe),
    .trigger(trigger),
    .sdata(sdata),
    .sclk(sclk),
    .cs(cs),
    .done(done),
    .data(data)
);

integer i;

task RESET;
begin
	success_flag = 1;
    rst = 0;
    oe  = 0;
    clk = 0;
    #5
    rst = 1;
    #5
    rst = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask













initial begin
    #10
    #10
	RESET;
	trigger = 1;
	sdata 	= 1;
    CLOCK(FULL_CYCLE/2);
	trigger = 0;
    CLOCK(FULL_CYCLE/2);
    oe = 1;
    CLOCK(FULL_CYCLE);


	if (success_flag == 0) begin
		$display("*FAILED* TEST!");
	end
	else begin
		$display("**PASSED** TEST!");
	end

    #10 $stop;
    #5 $finish;
end

endmodule