data/full_repos/permissive/210844779/lab8/8.2/tb.v
 line:3: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab8/8.2/tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n#5 clk=~clk;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab8/8.2/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/210844779/lab8/8.2/tb.v:5: Cannot find file containing module: \'dff\'\ndff u0(q,d,clk,rst,set);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab8/8.2,data/full_repos/permissive/210844779/dff\n             data/full_repos/permissive/210844779/lab8/8.2,data/full_repos/permissive/210844779/dff.v\n             data/full_repos/permissive/210844779/lab8/8.2,data/full_repos/permissive/210844779/dff.sv\n             dff\n             dff.v\n             dff.sv\n             obj_dir/dff\n             obj_dir/dff.v\n             obj_dir/dff.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.2/tb.v:12: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  d=$random;\n   ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.2/tb.v:13: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  rst=$random;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.2/tb.v:14: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  set=$random;\n     ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
wire q;
reg d,clk=0,rst,set;

dff u0(q,d,clk,rst,set);

always
#5 clk=~clk;

always
begin
  d=$random;
  rst=$random;
  set=$random;
  #10;
end

endmodule
module tb();

wire q;
reg d,clk=0,rst,set;

dff u0(q,d,clk,rst,set);

always
#5 clk=~clk;

always
begin
  d=$random;
  rst=$random;
  set=$random;
  #10;
end

endmodule