data/full_repos/permissive/205673649/MIPS/Source/alu.v
 line:47 column:9: Illegal character "'"
1: b'%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/alu.v:62: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                         : ... In instance alu\n   4\'b 1100: o_result = signed_datoA < signed_datoB;  \n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module alu
#(
    parameter LEN=32,
    parameter NB_ALU_CONTROL=4
)
(
    input [LEN-1:0] i_datoA,
    input [LEN-1:0] i_datoB,
    input [NB_ALU_CONTROL-1:0] i_opcode,
    output reg [LEN-1:0] o_result,
    output reg o_zero_flag
);

reg signed [LEN-1:0] signed_datoA;
reg signed [LEN-1:0] signed_datoB;

always @(*) begin
    signed_datoA = i_datoA;
    signed_datoB = i_datoB;
end

always @(*)
	begin
		o_zero_flag = 0;

		case (i_opcode)
		    4'b 0000: o_result = i_datoB << i_datoA;
		    4'b 0001: o_result = i_datoB >> i_datoA;
		    4'b 0010: o_result = i_datoB >>> i_datoA;
		    4'b 0011: o_result = i_datoB << 16;
		    4'b 0100: o_result = signed_datoA + signed_datoB;
		    4'b 0110: o_result = i_datoA + i_datoB;
			4'b 0111: 
			begin
			     o_result = i_datoA - i_datoB;
			     o_zero_flag = (i_datoA==i_datoB) ? 1'b1 : 1'b0;
            end
			4'b 1000: o_result = i_datoA & i_datoB;
			4'b 1001: o_result = i_datoA | i_datoB;
			4'b 1010: o_result = i_datoA ^ i_datoB;
			4'b 1011: o_result = ~(i_datoA | i_datoB);
			4'b 1100: o_result = signed_datoA < signed_datoB;
			default: o_result = 0;
		endcase	
	end

    
endmodule
module alu
#(
    parameter LEN=32,
    parameter NB_ALU_CONTROL=4
)
(
    input [LEN-1:0] i_datoA,
    input [LEN-1:0] i_datoB,
    input [NB_ALU_CONTROL-1:0] i_opcode,
    output reg [LEN-1:0] o_result,
    output reg o_zero_flag
);


reg signed [LEN-1:0] signed_datoA;
reg signed [LEN-1:0] signed_datoB;

always @(*) begin
    signed_datoA = i_datoA;
    signed_datoB = i_datoB;
end

always @(*)
	begin
		o_zero_flag = 0;

		case (i_opcode)
		    4'b 0000: o_result = i_datoB << i_datoA;
		    4'b 0001: o_result = i_datoB >> i_datoA;
		    4'b 0010: o_result = i_datoB >>> i_datoA;
		    4'b 0011: o_result = i_datoB << 16;
		    4'b 0100: o_result = signed_datoA + signed_datoB;
		    4'b 0110: o_result = i_datoA + i_datoB;
			4'b 0111: 
			begin
			     o_result = i_datoA - i_datoB;
			     o_zero_flag = (i_datoA==i_datoB) ? 1'b1 : 1'b0;
            end
			4'b 1000: o_result = i_datoA & i_datoB;
			4'b 1001: o_result = i_datoA | i_datoB;
			4'b 1010: o_result = i_datoA ^ i_datoB;
			4'b 1011: o_result = ~(i_datoA | i_datoB);
			4'b 1100: o_result = signed_datoA < signed_datoB;
			default: o_result = 0;
		endcase	
	end

    
endmodule