data/full_repos/permissive/219917900/rx_rtl_files/rx_majority.v
1: b"%Error: data/full_repos/permissive/219917900/rx_rtl_files/rx_majority.v:45: Cannot find file containing module: 'one2one'\none2one #(.whereisid(id_location)) one2one_inst(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219917900/rx_rtl_files,data/full_repos/permissive/219917900/one2one\n             data/full_repos/permissive/219917900/rx_rtl_files,data/full_repos/permissive/219917900/one2one.v\n             data/full_repos/permissive/219917900/rx_rtl_files,data/full_repos/permissive/219917900/one2one.sv\n             one2one\n             one2one.v\n             one2one.sv\n             obj_dir/one2one\n             obj_dir/one2one.v\n             obj_dir/one2one.sv\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/rx_majority.v:57: Cannot find file containing module: 'three2one'\nthree2one #(.whereisid(id_location)) three2one_inst(\n^~~~~~~~~\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/rx_majority.v:71: Cannot find file containing module: 'five2one'\nfive2one #(.whereisid(id_location)) five2one_inst(\n^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module rx_majority (

  input wire clk125MHz,
  input wire reset,



  input wire [7:0] rx_data,
  input wire rx_enable,


  output wire loss_detected,
  input wire [7:0] redundancy,
 output wire en_out,
 output wire [7:0] data_out
  );



reg [7:0] rx_data_ff1, rx_data_ff2;
reg rx_enable_ff1, rx_enable_ff2;
always @(posedge clk125MHz) begin
    rx_data_ff1 <= rx_data;
    rx_data_ff2 <= rx_data_ff1;
    
    rx_enable_ff1 <= rx_enable;
    rx_enable_ff2 <= rx_enable_ff1;
end

wire [7:0] rx_data_al = rx_data_ff2;
wire rx_enable_al = rx_enable_ff2;








parameter id_location = 6'h0;


wire [7:0] data_out_1;
wire en_out_1,loss_detected_1;
one2one #(.whereisid(id_location)) one2one_inst(
    .clk(clk125MHz),
    .clk125MHz(clk125MHz),
    .rst(reset),
    .rx_en_w(rx_enable_al),
    .rxdata_w(rx_data_al),
    .data_out(data_out_1),
    .en_out(en_out_1)
);

wire [7:0] data_out_3;
wire en_out_3,loss_detected_3;
three2one #(.whereisid(id_location)) three2one_inst(
	.clk(clk125MHz),
	.rst(reset),
	.rx_en_w(rx_enable_al),
	.rxdata_w(rx_data_al),

	.data_out(data_out_3),
	.en_out(en_out_3),
	.lost(loss_detected_3)
);


wire [7:0] data_out_5;
wire en_out_5,loss_detected_5;
five2one #(.whereisid(id_location)) five2one_inst(
	.clk(clk125MHz),
	.rst(reset),
	.rx_en_w(rx_enable_al),
	.rxdata_w(rx_data_al),
	.data_out(data_out_5),
	.en_out(en_out_5),
	.lost(loss_detected_5)
);



wire [7:0] data_out_c = redundancy==1?data_out_1: redundancy==3? data_out_3: redundancy==5? data_out_5:0;
wire en_out_c = redundancy==1? en_out_1: redundancy==3? en_out_3: redundancy==5? en_out_5:0;
wire loss_detected_c = redundancy==1? loss_detected_1: redundancy==3? loss_detected_3: redundancy==5? loss_detected_5:0;

reg [7:0] data_out_ff;
reg en_out_ff,loss_detected_ff;

always @(posedge clk125MHz) begin
    data_out_ff <= data_out_c;
    en_out_ff <= en_out_c;
    loss_detected_ff <= loss_detected_c;
end

assign data_out = data_out_ff;
assign en_out = en_out_ff;
assign loss_detected = loss_detected_ff;

endmodule
module rx_majority (

  input wire clk125MHz,
  input wire reset,



  input wire [7:0] rx_data,
  input wire rx_enable,


  output wire loss_detected,
  input wire [7:0] redundancy,
 output wire en_out,
 output wire [7:0] data_out
  );




reg [7:0] rx_data_ff1, rx_data_ff2;
reg rx_enable_ff1, rx_enable_ff2;
always @(posedge clk125MHz) begin
    rx_data_ff1 <= rx_data;
    rx_data_ff2 <= rx_data_ff1;
    
    rx_enable_ff1 <= rx_enable;
    rx_enable_ff2 <= rx_enable_ff1;
end

wire [7:0] rx_data_al = rx_data_ff2;
wire rx_enable_al = rx_enable_ff2;








parameter id_location = 6'h0;


wire [7:0] data_out_1;
wire en_out_1,loss_detected_1;
one2one #(.whereisid(id_location)) one2one_inst(
    .clk(clk125MHz),
    .clk125MHz(clk125MHz),
    .rst(reset),
    .rx_en_w(rx_enable_al),
    .rxdata_w(rx_data_al),
    .data_out(data_out_1),
    .en_out(en_out_1)
);

wire [7:0] data_out_3;
wire en_out_3,loss_detected_3;
three2one #(.whereisid(id_location)) three2one_inst(
	.clk(clk125MHz),
	.rst(reset),
	.rx_en_w(rx_enable_al),
	.rxdata_w(rx_data_al),

	.data_out(data_out_3),
	.en_out(en_out_3),
	.lost(loss_detected_3)
);


wire [7:0] data_out_5;
wire en_out_5,loss_detected_5;
five2one #(.whereisid(id_location)) five2one_inst(
	.clk(clk125MHz),
	.rst(reset),
	.rx_en_w(rx_enable_al),
	.rxdata_w(rx_data_al),
	.data_out(data_out_5),
	.en_out(en_out_5),
	.lost(loss_detected_5)
);



wire [7:0] data_out_c = redundancy==1?data_out_1: redundancy==3? data_out_3: redundancy==5? data_out_5:0;
wire en_out_c = redundancy==1? en_out_1: redundancy==3? en_out_3: redundancy==5? en_out_5:0;
wire loss_detected_c = redundancy==1? loss_detected_1: redundancy==3? loss_detected_3: redundancy==5? loss_detected_5:0;

reg [7:0] data_out_ff;
reg en_out_ff,loss_detected_ff;

always @(posedge clk125MHz) begin
    data_out_ff <= data_out_c;
    en_out_ff <= en_out_c;
    loss_detected_ff <= loss_detected_c;
end

assign data_out = data_out_ff;
assign en_out = en_out_ff;
assign loss_detected = loss_detected_ff;

endmodule