data/full_repos/permissive/162696624/Traffic Light.v
 line:32: before: "["
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/162696624/Traffic\n        ... Looked in:\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.sv\n             data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624/Traffic.sv\n             obj_dir/data/full_repos/permissive/162696624/Traffic\n             obj_dir/data/full_repos/permissive/162696624/Traffic.v\n             obj_dir/data/full_repos/permissive/162696624/Traffic.sv\n%Error: Cannot find file containing module: Light.v\n%Error: Exiting due to 2 error(s)\n'
module test_select;
  reg EN,L0,L1,L2,L3,CLK,RST;
  wire [3:0]D0;
  wire [3:0]D1;
  number_set ns(D1,D0,EN,L0,L1,L2,L3,CLK,RST);

initial 
begin
  RST=0;
  CLK=0;
  #10
  RST=1;
  repeat(200)
  #5 CLK=~CLK;
end

initial 
begin
  EN=0;
  L0=1; L1=0; L2=0; L3=0;
  #10 EN=1;
  #500 L0=0; L2=1;
end
endmodule
module test_select;

  reg EN,L0,L1,L2,L3,CLK,RST;
  wire [3:0]D0;
  wire [3:0]D1;
  number_set ns(D1,D0,EN,L0,L1,L2,L3,CLK,RST);

initial 
begin
  RST=0;
  CLK=0;
  #10
  RST=1;
  repeat(200)
  #5 CLK=~CLK;
end

initial 
begin
  EN=0;
  L0=1; L1=0; L2=0; L3=0;
  #10 EN=1;
  #500 L0=0; L2=1;
end
endmodule