data/full_repos/permissive/205673649/BIP/Simulacion/tb_control.v
 line:58: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_control.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #0\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_control.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #2  rst = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_control.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #1000 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_control.v:61: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_control.v:64: Cannot find file containing module: \'control\'\n    control\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/BIP/Simulacion,data/full_repos/permissive/205673649/control\n             data/full_repos/permissive/205673649/BIP/Simulacion,data/full_repos/permissive/205673649/control.v\n             data/full_repos/permissive/205673649/BIP/Simulacion,data/full_repos/permissive/205673649/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_control.v:84: Cannot find file containing module: \'program_memory\'\n    program_memory\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_control.v:98: Cannot find file containing module: \'count_clock\'\ncount_clock\n^~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_control();

localparam OPCODE = 5;
localparam ADDR =11;
localparam OPERANDO =11;
localparam DECODER_SEL_A =2;
localparam RAM_WIDTH =16;
localparam RAM_DEPTH_PM = 2048;
localparam RAM_PERFORMANCE = "LOW_LATENCY";
localparam INIT_FILE_PM = "/home/andres/Facultad/Arquitectura_de_Computadoras/Andres/Arqui/BIP/Source/program_memory.txt";

reg clk;
reg rst;
wire [OPCODE-1:0] opcode_pm;
wire [ADDR-1:0] addr_pm;
wire [DECODER_SEL_A-1:0] selA;
wire selB;
wire wrAcc;
wire [OPCODE-1:0] op;
wire wrRam;
wire rdRam;
wire [RAM_WIDTH-1:0] instruction_pm;
wire [ADDR-1:0] counter;

assign opcode_pm = instruction_pm [RAM_WIDTH -1 -: OPCODE];


initial begin
  #0
  rst = 1'b0;
  clk = 1'b0;
   
  #2  rst = 1'b1;
  
  
  #1000 $finish;
end

always #1 clk = ~clk;


    control
#(
    .NB_OPCODE(OPCODE),
    .NB_ADDR(ADDR),
    .NB_DECODER_SEL_A(DECODER_SEL_A)
)
    u_control
(
    .i_clk(clk),
    .i_rst(rst),
    .i_opcode(opcode_pm),  
    .o_addr(addr_pm),     
    .o_selA(selA),
    .o_selB(selB),
    .o_wrAcc(wrAcc),
    .o_op(op),
    .o_wrRam(wrRam),
    .o_rdRam(rdRam)
);

    program_memory
#(
    .RAM_WIDTH(RAM_WIDTH),
    .RAM_DEPTH(RAM_DEPTH_PM),
    .RAM_PERFORMANCE(RAM_PERFORMANCE),
    .INIT_FILE(INIT_FILE_PM)
)
    u_program_memory
(
    .i_clk(clk),
    .i_addr(addr_pm),
    .o_data(instruction_pm)
);

count_clock
#(
    .NB_OPCODE(OPCODE),
    .NB_ADDR(OPERANDO)
)
    u_counter
(
    .i_clk(clk),
    .i_rst(rst),
    .i_opcode(opcode_pm),
    .o_counter(counter)
);

endmodule
module tb_control();


localparam OPCODE = 5;
localparam ADDR =11;
localparam OPERANDO =11;
localparam DECODER_SEL_A =2;
localparam RAM_WIDTH =16;
localparam RAM_DEPTH_PM = 2048;
localparam RAM_PERFORMANCE = "LOW_LATENCY";
localparam INIT_FILE_PM = "/home/andres/Facultad/Arquitectura_de_Computadoras/Andres/Arqui/BIP/Source/program_memory.txt";

reg clk;
reg rst;
wire [OPCODE-1:0] opcode_pm;
wire [ADDR-1:0] addr_pm;
wire [DECODER_SEL_A-1:0] selA;
wire selB;
wire wrAcc;
wire [OPCODE-1:0] op;
wire wrRam;
wire rdRam;
wire [RAM_WIDTH-1:0] instruction_pm;
wire [ADDR-1:0] counter;

assign opcode_pm = instruction_pm [RAM_WIDTH -1 -: OPCODE];


initial begin
  #0
  rst = 1'b0;
  clk = 1'b0;
   
  #2  rst = 1'b1;
  
  
  #1000 $finish;
end

always #1 clk = ~clk;


    control
#(
    .NB_OPCODE(OPCODE),
    .NB_ADDR(ADDR),
    .NB_DECODER_SEL_A(DECODER_SEL_A)
)
    u_control
(
    .i_clk(clk),
    .i_rst(rst),
    .i_opcode(opcode_pm),  
    .o_addr(addr_pm),     
    .o_selA(selA),
    .o_selB(selB),
    .o_wrAcc(wrAcc),
    .o_op(op),
    .o_wrRam(wrRam),
    .o_rdRam(rdRam)
);

    program_memory
#(
    .RAM_WIDTH(RAM_WIDTH),
    .RAM_DEPTH(RAM_DEPTH_PM),
    .RAM_PERFORMANCE(RAM_PERFORMANCE),
    .INIT_FILE(INIT_FILE_PM)
)
    u_program_memory
(
    .i_clk(clk),
    .i_addr(addr_pm),
    .o_data(instruction_pm)
);

count_clock
#(
    .NB_OPCODE(OPCODE),
    .NB_ADDR(OPERANDO)
)
    u_counter
(
    .i_clk(clk),
    .i_rst(rst),
    .i_opcode(opcode_pm),
    .o_counter(counter)
);

endmodule