data/full_repos/permissive/136510272/projects/05_nes/Altera_UP_PS2_Data_In.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/Altera_UP_PS2_Data_In.v:124: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                                : ... In instance Altera_UP_PS2_Data_In\n   if ((data_count == 3\'h7) && (ps2_clk_posedge == 1\'b1))\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/Altera_UP_PS2_Data_In.v:164: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                : ... In instance Altera_UP_PS2_Data_In\n  data_count <= 3\'h0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/Altera_UP_PS2_Data_In.v:170: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                : ... In instance Altera_UP_PS2_Data_In\n  data_count <= 3\'h0;\n             ^~\n%Error: Exiting due to 3 warning(s)\n'
module Altera_UP_PS2_Data_In (

	clk,
	reset,

	wait_for_incoming_data,
	start_receiving_data,

	ps2_clk_posedge,
	ps2_clk_negedge,
	ps2_data,




	received_data,
	received_data_en
);







input				clk;
input				reset;

input				wait_for_incoming_data;
input				start_receiving_data;

input				ps2_clk_posedge;
input				ps2_clk_negedge;
input			 	ps2_data;




output reg	[7:0]	received_data;

output reg		 	received_data_en;



localparam	PS2_STATE_0_IDLE			= 3'h0,
			PS2_STATE_1_WAIT_FOR_DATA	= 3'h1,
			PS2_STATE_2_DATA_IN			= 3'h2,
			PS2_STATE_3_PARITY_IN		= 3'h3,
			PS2_STATE_4_STOP_IN			= 3'h4;



reg			[3:0]	data_count;
reg			[7:0]	data_shift_reg;


reg			[2:0]	ns_ps2_receiver;
reg			[2:0]	s_ps2_receiver;



always @(posedge clk)
begin
	if (reset == 1'b1)
		s_ps2_receiver <= PS2_STATE_0_IDLE;
	else
		s_ps2_receiver <= ns_ps2_receiver;
end

always @(*)
begin


	ns_ps2_receiver = PS2_STATE_0_IDLE;

    case (s_ps2_receiver)
    
	PS2_STATE_0_IDLE:
    
		begin
			if ((wait_for_incoming_data == 1'b1) && (received_data_en == 1'b0))
				ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
                
			else if ((start_receiving_data == 1'b1) && (received_data_en == 1'b0))
				ns_ps2_receiver = PS2_STATE_2_DATA_IN;
                
			else
				ns_ps2_receiver = PS2_STATE_0_IDLE;
		end
        
	PS2_STATE_1_WAIT_FOR_DATA:
    
		begin
			if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
				ns_ps2_receiver = PS2_STATE_2_DATA_IN;
			else if (wait_for_incoming_data == 1'b0)
				ns_ps2_receiver = PS2_STATE_0_IDLE;
			else
				ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
		end
        
	PS2_STATE_2_DATA_IN:
    
		begin
			if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
				ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
			else
				ns_ps2_receiver = PS2_STATE_2_DATA_IN;
		end
        
	PS2_STATE_3_PARITY_IN:
    
		begin
			if (ps2_clk_posedge == 1'b1)
				ns_ps2_receiver = PS2_STATE_4_STOP_IN;
			else
				ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
		end
        
	PS2_STATE_4_STOP_IN:
    
		begin
			if (ps2_clk_posedge == 1'b1)
				ns_ps2_receiver = PS2_STATE_0_IDLE;
			else
				ns_ps2_receiver = PS2_STATE_4_STOP_IN;
		end
        
	default:
    
		begin
			ns_ps2_receiver = PS2_STATE_0_IDLE;
		end
	endcase
end



always @(posedge clk)
begin

	if (reset == 1'b1) 
		data_count	<= 3'h0;
        
	else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) && (ps2_clk_posedge == 1'b1))
		data_count	<= data_count + 3'h1;
        
	else if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
		data_count	<= 3'h0;
end

always @(posedge clk)
begin
	if (reset == 1'b1)
		data_shift_reg <= 8'h00;
        
	else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) && (ps2_clk_posedge == 1'b1))
		data_shift_reg	<= {ps2_data, data_shift_reg[7:1]};
end

always @(posedge clk)
begin
	if (reset == 1'b1) begin
        received_data <= 8'h00;        
    end
        
	else if (s_ps2_receiver == PS2_STATE_4_STOP_IN) begin      
		received_data  <= keyb_xt[7:0];          
    end

end

always @(posedge clk)
begin
	if (reset == 1'b1) begin    
		received_data_en <= 1'b0;        
    end
	else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) && (ps2_clk_posedge == 1'b1)) begin       
        received_data_en <= 1'b1;
    end
	else begin
		received_data_en <= 1'b0;
    end
end



reg [7:0] keyb_xt;

always @* begin

    case (data_shift_reg)
    
8'h1C: keyb_xt = 8'h1E;
8'h32: keyb_xt = 8'h30;
8'h21: keyb_xt = 8'h2E;
8'h23: keyb_xt = 8'h20;
8'h24: keyb_xt = 8'h12;
8'h2B: keyb_xt = 8'h21;
8'h34: keyb_xt = 8'h22;
8'h33: keyb_xt = 8'h23;
8'h43: keyb_xt = 8'h17;
8'h3B: keyb_xt = 8'h24;
8'h42: keyb_xt = 8'h25;
8'h4B: keyb_xt = 8'h26;
8'h3A: keyb_xt = 8'h32;
8'h31: keyb_xt = 8'h31;
8'h44: keyb_xt = 8'h18;
8'h4D: keyb_xt = 8'h19;
8'h15: keyb_xt = 8'h10;
8'h2D: keyb_xt = 8'h13;
8'h1B: keyb_xt = 8'h1F;
8'h2C: keyb_xt = 8'h14;
8'h3C: keyb_xt = 8'h16;
8'h2A: keyb_xt = 8'h2F;
8'h1D: keyb_xt = 8'h11;
8'h22: keyb_xt = 8'h2D;
8'h35: keyb_xt = 8'h15;
8'h1A: keyb_xt = 8'h2C;
8'h45: keyb_xt = 8'h0B;
8'h16: keyb_xt = 8'h02;
8'h1E: keyb_xt = 8'h03;
8'h26: keyb_xt = 8'h04;
8'h25: keyb_xt = 8'h05;
8'h2E: keyb_xt = 8'h06;
8'h36: keyb_xt = 8'h07;
8'h3D: keyb_xt = 8'h08;
8'h3E: keyb_xt = 8'h09;
8'h46: keyb_xt = 8'h0A;        
8'h0E: keyb_xt = 8'h29;
8'h4E: keyb_xt = 8'h0C;
8'h55: keyb_xt = 8'h0D;
8'h5D: keyb_xt = 8'h2B;
8'h54: keyb_xt = 8'h1A;
8'h5B: keyb_xt = 8'h1B;
8'h4C: keyb_xt = 8'h27;
8'h52: keyb_xt = 8'h28;
8'h41: keyb_xt = 8'h33;
8'h49: keyb_xt = 8'h34;
8'h4A: keyb_xt = 8'h35;
8'h66: keyb_xt = 8'h0E;
8'h29: keyb_xt = 8'h39;
8'h0D: keyb_xt = 8'h0F;
        

8'h58: keyb_xt = 8'h3A;
8'h12: keyb_xt = 8'h2A;
8'h14: keyb_xt = 8'h1D;
8'h11: keyb_xt = 8'h38;
8'h1F: keyb_xt = 8'h5B;
8'h59: keyb_xt = 8'h36;
8'h27: keyb_xt = 8'h5C;
8'h2F: keyb_xt = 8'h5D;
8'h5A: keyb_xt = 8'h1C;
        

8'h76: keyb_xt = 8'h01;        
8'h05: keyb_xt = 8'h3B;
8'h06: keyb_xt = 8'h3C;
8'h04: keyb_xt = 8'h3D;
8'h0C: keyb_xt = 8'h3E;
8'h03: keyb_xt = 8'h3F;
8'h0B: keyb_xt = 8'h40;
8'h83: keyb_xt = 8'h41;
8'h0A: keyb_xt = 8'h42;
8'h01: keyb_xt = 8'h43;
8'h09: keyb_xt = 8'h44;
8'h78: keyb_xt = 8'h57;
8'h07: keyb_xt = 8'h58;
8'h7E: keyb_xt = 8'h46;
        

8'h77: keyb_xt = 8'h45;
8'h7C: keyb_xt = 8'h37;
8'h7B: keyb_xt = 8'h4A;
8'h79: keyb_xt = 8'h4E;
8'h71: keyb_xt = 8'h53;                
8'h70: keyb_xt = 8'h52;
8'h69: keyb_xt = 8'h4F;
8'h72: keyb_xt = 8'h50;
8'h7A: keyb_xt = 8'h51;
8'h6B: keyb_xt = 8'h4B;
8'h73: keyb_xt = 8'h4C;
8'h74: keyb_xt = 8'h4D;
8'h6C: keyb_xt = 8'h47;
8'h75: keyb_xt = 8'h48;
8'h7D: keyb_xt = 8'h49;
        

        default: keyb_xt = data_shift_reg;
        
    endcase
end
 



endmodule
module Altera_UP_PS2_Data_In (

	clk,
	reset,

	wait_for_incoming_data,
	start_receiving_data,

	ps2_clk_posedge,
	ps2_clk_negedge,
	ps2_data,




	received_data,
	received_data_en
);








input				clk;
input				reset;

input				wait_for_incoming_data;
input				start_receiving_data;

input				ps2_clk_posedge;
input				ps2_clk_negedge;
input			 	ps2_data;




output reg	[7:0]	received_data;

output reg		 	received_data_en;



localparam	PS2_STATE_0_IDLE			= 3'h0,
			PS2_STATE_1_WAIT_FOR_DATA	= 3'h1,
			PS2_STATE_2_DATA_IN			= 3'h2,
			PS2_STATE_3_PARITY_IN		= 3'h3,
			PS2_STATE_4_STOP_IN			= 3'h4;



reg			[3:0]	data_count;
reg			[7:0]	data_shift_reg;


reg			[2:0]	ns_ps2_receiver;
reg			[2:0]	s_ps2_receiver;



always @(posedge clk)
begin
	if (reset == 1'b1)
		s_ps2_receiver <= PS2_STATE_0_IDLE;
	else
		s_ps2_receiver <= ns_ps2_receiver;
end

always @(*)
begin


	ns_ps2_receiver = PS2_STATE_0_IDLE;

    case (s_ps2_receiver)
    
	PS2_STATE_0_IDLE:
    
		begin
			if ((wait_for_incoming_data == 1'b1) && (received_data_en == 1'b0))
				ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
                
			else if ((start_receiving_data == 1'b1) && (received_data_en == 1'b0))
				ns_ps2_receiver = PS2_STATE_2_DATA_IN;
                
			else
				ns_ps2_receiver = PS2_STATE_0_IDLE;
		end
        
	PS2_STATE_1_WAIT_FOR_DATA:
    
		begin
			if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
				ns_ps2_receiver = PS2_STATE_2_DATA_IN;
			else if (wait_for_incoming_data == 1'b0)
				ns_ps2_receiver = PS2_STATE_0_IDLE;
			else
				ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
		end
        
	PS2_STATE_2_DATA_IN:
    
		begin
			if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
				ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
			else
				ns_ps2_receiver = PS2_STATE_2_DATA_IN;
		end
        
	PS2_STATE_3_PARITY_IN:
    
		begin
			if (ps2_clk_posedge == 1'b1)
				ns_ps2_receiver = PS2_STATE_4_STOP_IN;
			else
				ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
		end
        
	PS2_STATE_4_STOP_IN:
    
		begin
			if (ps2_clk_posedge == 1'b1)
				ns_ps2_receiver = PS2_STATE_0_IDLE;
			else
				ns_ps2_receiver = PS2_STATE_4_STOP_IN;
		end
        
	default:
    
		begin
			ns_ps2_receiver = PS2_STATE_0_IDLE;
		end
	endcase
end



always @(posedge clk)
begin

	if (reset == 1'b1) 
		data_count	<= 3'h0;
        
	else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) && (ps2_clk_posedge == 1'b1))
		data_count	<= data_count + 3'h1;
        
	else if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
		data_count	<= 3'h0;
end

always @(posedge clk)
begin
	if (reset == 1'b1)
		data_shift_reg <= 8'h00;
        
	else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) && (ps2_clk_posedge == 1'b1))
		data_shift_reg	<= {ps2_data, data_shift_reg[7:1]};
end

always @(posedge clk)
begin
	if (reset == 1'b1) begin
        received_data <= 8'h00;        
    end
        
	else if (s_ps2_receiver == PS2_STATE_4_STOP_IN) begin      
		received_data  <= keyb_xt[7:0];          
    end

end

always @(posedge clk)
begin
	if (reset == 1'b1) begin    
		received_data_en <= 1'b0;        
    end
	else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) && (ps2_clk_posedge == 1'b1)) begin       
        received_data_en <= 1'b1;
    end
	else begin
		received_data_en <= 1'b0;
    end
end



reg [7:0] keyb_xt;

always @* begin

    case (data_shift_reg)
    
8'h1C: keyb_xt = 8'h1E;
8'h32: keyb_xt = 8'h30;
8'h21: keyb_xt = 8'h2E;
8'h23: keyb_xt = 8'h20;
8'h24: keyb_xt = 8'h12;
8'h2B: keyb_xt = 8'h21;
8'h34: keyb_xt = 8'h22;
8'h33: keyb_xt = 8'h23;
8'h43: keyb_xt = 8'h17;
8'h3B: keyb_xt = 8'h24;
8'h42: keyb_xt = 8'h25;
8'h4B: keyb_xt = 8'h26;
8'h3A: keyb_xt = 8'h32;
8'h31: keyb_xt = 8'h31;
8'h44: keyb_xt = 8'h18;
8'h4D: keyb_xt = 8'h19;
8'h15: keyb_xt = 8'h10;
8'h2D: keyb_xt = 8'h13;
8'h1B: keyb_xt = 8'h1F;
8'h2C: keyb_xt = 8'h14;
8'h3C: keyb_xt = 8'h16;
8'h2A: keyb_xt = 8'h2F;
8'h1D: keyb_xt = 8'h11;
8'h22: keyb_xt = 8'h2D;
8'h35: keyb_xt = 8'h15;
8'h1A: keyb_xt = 8'h2C;
8'h45: keyb_xt = 8'h0B;
8'h16: keyb_xt = 8'h02;
8'h1E: keyb_xt = 8'h03;
8'h26: keyb_xt = 8'h04;
8'h25: keyb_xt = 8'h05;
8'h2E: keyb_xt = 8'h06;
8'h36: keyb_xt = 8'h07;
8'h3D: keyb_xt = 8'h08;
8'h3E: keyb_xt = 8'h09;
8'h46: keyb_xt = 8'h0A;        
8'h0E: keyb_xt = 8'h29;
8'h4E: keyb_xt = 8'h0C;
8'h55: keyb_xt = 8'h0D;
8'h5D: keyb_xt = 8'h2B;
8'h54: keyb_xt = 8'h1A;
8'h5B: keyb_xt = 8'h1B;
8'h4C: keyb_xt = 8'h27;
8'h52: keyb_xt = 8'h28;
8'h41: keyb_xt = 8'h33;
8'h49: keyb_xt = 8'h34;
8'h4A: keyb_xt = 8'h35;
8'h66: keyb_xt = 8'h0E;
8'h29: keyb_xt = 8'h39;
8'h0D: keyb_xt = 8'h0F;
        

8'h58: keyb_xt = 8'h3A;
8'h12: keyb_xt = 8'h2A;
8'h14: keyb_xt = 8'h1D;
8'h11: keyb_xt = 8'h38;
8'h1F: keyb_xt = 8'h5B;
8'h59: keyb_xt = 8'h36;
8'h27: keyb_xt = 8'h5C;
8'h2F: keyb_xt = 8'h5D;
8'h5A: keyb_xt = 8'h1C;
        

8'h76: keyb_xt = 8'h01;        
8'h05: keyb_xt = 8'h3B;
8'h06: keyb_xt = 8'h3C;
8'h04: keyb_xt = 8'h3D;
8'h0C: keyb_xt = 8'h3E;
8'h03: keyb_xt = 8'h3F;
8'h0B: keyb_xt = 8'h40;
8'h83: keyb_xt = 8'h41;
8'h0A: keyb_xt = 8'h42;
8'h01: keyb_xt = 8'h43;
8'h09: keyb_xt = 8'h44;
8'h78: keyb_xt = 8'h57;
8'h07: keyb_xt = 8'h58;
8'h7E: keyb_xt = 8'h46;
        

8'h77: keyb_xt = 8'h45;
8'h7C: keyb_xt = 8'h37;
8'h7B: keyb_xt = 8'h4A;
8'h79: keyb_xt = 8'h4E;
8'h71: keyb_xt = 8'h53;                
8'h70: keyb_xt = 8'h52;
8'h69: keyb_xt = 8'h4F;
8'h72: keyb_xt = 8'h50;
8'h7A: keyb_xt = 8'h51;
8'h6B: keyb_xt = 8'h4B;
8'h73: keyb_xt = 8'h4C;
8'h74: keyb_xt = 8'h4D;
8'h6C: keyb_xt = 8'h47;
8'h75: keyb_xt = 8'h48;
8'h7D: keyb_xt = 8'h49;
        

        default: keyb_xt = data_shift_reg;
        
    endcase
end
 



endmodule