data/full_repos/permissive/193439230/sbox.v
data/verilator_xmls/9e770880-de7d-4db0-ab4b-be45e1c0d585.xml
module SM4(b, Sb);
    input[7:0] b;
    output[7:0] Sb;
    wire[7:0] g;
    wire[9:0] m;
    wire[3:0] p,
        l;
    wire[17:0] e;
    Input M1(b, g, m);
    Top M2(g, m, p);
    Middle M3(p, l);
    Bottom M4(g, m, l, e);
    Output M5(e, Sb);
endmodule
module SM4(b, Sb);

    input[7:0] b;
    output[7:0] Sb;
    wire[7:0] g;
    wire[9:0] m;
    wire[3:0] p,
        l;
    wire[17:0] e;
    Input M1(b, g, m);
    Top M2(g, m, p);
    Middle M3(p, l);
    Bottom M4(g, m, l, e);
    Output M5(e, Sb);
endmodule