data/full_repos/permissive/114553631/test/test_reg_file.v
 line:125: before: "$"
1: b'%Error: data/full_repos/permissive/114553631/test/test_reg_file.v:6: Cannot find include file: ../src/reg_file.v\n`include "../src/reg_file.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/reg_file.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/reg_file.v.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/reg_file.v.sv\n             ../src/reg_file.v\n             ../src/reg_file.v.v\n             ../src/reg_file.v.sv\n             obj_dir/../src/reg_file.v\n             obj_dir/../src/reg_file.v.v\n             obj_dir/../src/reg_file.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:23: Unsupported: Ignoring delay on this delayed statement.\n    initial #stop_time $finish;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:56: Unsupported: Ignoring delay on this delayed statement.\n            #5 clk=~clk;      \n            ^\n%Error: data/full_repos/permissive/114553631/test/test_reg_file.v:60: Unsupported or unknown PLI call: $monitor\n        $monitor("time = ", $time, " srcA=%d srcB=%d valA=%d valB=%d", d_srcA, d_srcB, d_rvalA, d_rvalB);\n        ^~~~~~~~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n'
module test_reg_file;
    wire [31:0] d_rvalA;
    wire [31:0] d_rvalB;
    reg clk = 0;
    reg [4:0] d_srcA;
    reg [4:0] d_srcB;
    reg [4:0] W_dstM;
    reg [4:0] W_dstE;
    reg [31:0] W_valM;
    reg [31:0] W_valE;

    parameter stop_time = 50;

    reg_file REG_FILE(d_rvalA, d_rvalB, clk, d_srcA, d_srcB, W_dstM, W_dstE, W_valM, W_valE);

    initial #stop_time $finish;

    initial begin
        clk = 0;
        d_srcA = 0;
        d_srcB = 0;
        #5;
        W_dstE = 1;
        W_dstM = 2;
        W_valE = 1;
        W_valM = 2;
        #5;
        d_srcA = 1;
        d_srcB = 2;
        #5;
        W_dstE = 1;
        W_dstM = 2;
        W_valE = 3;
        W_valM = 4;
        #5;
        d_srcA = 0;
        d_srcB = 0;
        #5;
        W_dstE = 0;
        W_valE = 5;
        #5;
        d_srcA = 2;
        d_srcB = 1;
        #5;
    end

    initial begin
        repeat(10)
            #5 clk=~clk;      
    end

    initial begin
        $monitor("time = ", $time, " srcA=%d srcB=%d valA=%d valB=%d", d_srcA, d_srcB, d_rvalA, d_rvalB);
    end
endmodule
module test_reg_file;

    wire [31:0] d_rvalA;
    wire [31:0] d_rvalB;
    reg clk = 0;
    reg [4:0] d_srcA;
    reg [4:0] d_srcB;
    reg [4:0] W_dstM;
    reg [4:0] W_dstE;
    reg [31:0] W_valM;
    reg [31:0] W_valE;

    parameter stop_time = 50;

    reg_file REG_FILE(d_rvalA, d_rvalB, clk, d_srcA, d_srcB, W_dstM, W_dstE, W_valM, W_valE);

    initial #stop_time $finish;

    initial begin
        clk = 0;
        d_srcA = 0;
        d_srcB = 0;
        #5;
        W_dstE = 1;
        W_dstM = 2;
        W_valE = 1;
        W_valM = 2;
        #5;
        d_srcA = 1;
        d_srcB = 2;
        #5;
        W_dstE = 1;
        W_dstM = 2;
        W_valE = 3;
        W_valM = 4;
        #5;
        d_srcA = 0;
        d_srcB = 0;
        #5;
        W_dstE = 0;
        W_valE = 5;
        #5;
        d_srcA = 2;
        d_srcB = 1;
        #5;
    end

    initial begin
        repeat(10)
            #5 clk=~clk;      
    end

    initial begin
        $monitor("time = ", $time, " srcA=%d srcB=%d valA=%d valB=%d", d_srcA, d_srcB, d_rvalA, d_rvalB);
    end
endmodule