data/full_repos/permissive/162646941/src/ander_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/162646941/src/ander_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/162646941/src/ander_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Error: data/full_repos/permissive/162646941/src/ander_tb.v:6: Cannot find file containing module: \'ander\'\n  ander uut (.a(a),.b(b),.result(result));\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/162646941/src,data/full_repos/permissive/162646941/ander\n             data/full_repos/permissive/162646941/src,data/full_repos/permissive/162646941/ander.v\n             data/full_repos/permissive/162646941/src,data/full_repos/permissive/162646941/ander.sv\n             ander\n             ander.v\n             ander.sv\n             obj_dir/ander\n             obj_dir/ander.v\n             obj_dir/ander.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ander_tb;
  reg a, b;
  wire result;
  ander uut (.a(a),.b(b),.result(result));
  initial begin
    a=0;	b=0;
    #200;
    a=0;	b=1;
    #200;
    a=1;	b=1;
  end
endmodule
module ander_tb;

  reg a, b;
  wire result;
  ander uut (.a(a),.b(b),.result(result));
  initial begin
    a=0;	b=0;
    #200;
    a=0;	b=1;
    #200;
    a=1;	b=1;
  end
endmodule