data/full_repos/permissive/10379745/hard/io_space.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/10379745/hard/io_space.sv:11: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                          : ... Top module \'io_space\'\nmodule io_space #( parameter RAM_DEPTH = 14 )\n       ^~~~~~~~\n                                                                          : ... Top module \'if_io\'\n                 if_io.io               IO );  \n                 ^~~~~\n%Error: data/full_repos/permissive/10379745/hard/io_space.sv:11: Unsupported: Interfaced port on top level module\n                 if_io.io               IO );  \n                                        ^~\n%Error: data/full_repos/permissive/10379745/hard/io_space.sv:11: Cannot find file containing interface: \'if_io\'\n                 if_io.io               IO );  \n                 ^~~~~\n%Error: Internal Error: data/full_repos/permissive/10379745/hard/io_space.sv:11: ../V3LinkDot.cpp:2055: Unlinked interface\n                 if_io.io               IO );  \n                 ^~~~~\n'
module io_space #( parameter RAM_DEPTH = 14 )
               ( input                  CLK,
                 input                  RESET,
                 input                  DBE,
                 input                  IO_REQ,
                 input                  IO_WE,
                 input                  IO_RE,
                 input  [RAM_DEPTH-1:0] IO_ADDR,
                 input           [31:0] IO_WD,
                 output          [31:0] IO_RD,
                 if_io.io               IO );

logic [RAM_DEPTH-1:0] addr_q;
logic          [31:0] wd_q;
logic ioreq_q, dbe_q, iowe_q, iore_q, req_valid;
logic leds_select;

ffd #(4)         ctrl_fd(CLK, RESET, 1'b1, {IO_REQ, DBE, IO_WE, IO_RE}, {ioreq_q, dbe_q, iowe_q, iore_q});
ffd #(RAM_DEPTH) addr_fd(CLK, RESET, 1'b1, IO_ADDR, addr_q);
ffd #(32)        data_fd(CLK, RESET, 1'b1, IO_WD,     wd_q);

assign req_valid = ioreq_q & ~dbe_q;
assign leds_select   = (addr_q[7:4] == 4'd0);

assign IO.LEDS_WE = leds_select & iowe_q & req_valid;
assign IO.LEDS_WD = wd_q;
assign IO.LEDS_A  = addr_q[3:0];

mux8  #(32) read_mux( addr_q[6:4],
                     IO.LEDS_RD,
                     32'd0,
                     32'd0,
                     32'd0,
                     32'd0,
                     32'd0,
                     32'd0,
                     32'd0,
                     IO_RD );

    
endmodule
module io_space #( parameter RAM_DEPTH = 14 )
               ( input                  CLK,
                 input                  RESET,
                 input                  DBE,
                 input                  IO_REQ,
                 input                  IO_WE,
                 input                  IO_RE,
                 input  [RAM_DEPTH-1:0] IO_ADDR,
                 input           [31:0] IO_WD,
                 output          [31:0] IO_RD,
                 if_io.io               IO );


logic [RAM_DEPTH-1:0] addr_q;
logic          [31:0] wd_q;
logic ioreq_q, dbe_q, iowe_q, iore_q, req_valid;
logic leds_select;

ffd #(4)         ctrl_fd(CLK, RESET, 1'b1, {IO_REQ, DBE, IO_WE, IO_RE}, {ioreq_q, dbe_q, iowe_q, iore_q});
ffd #(RAM_DEPTH) addr_fd(CLK, RESET, 1'b1, IO_ADDR, addr_q);
ffd #(32)        data_fd(CLK, RESET, 1'b1, IO_WD,     wd_q);

assign req_valid = ioreq_q & ~dbe_q;
assign leds_select   = (addr_q[7:4] == 4'd0);

assign IO.LEDS_WE = leds_select & iowe_q & req_valid;
assign IO.LEDS_WD = wd_q;
assign IO.LEDS_A  = addr_q[3:0];

mux8  #(32) read_mux( addr_q[6:4],
                     IO.LEDS_RD,
                     32'd0,
                     32'd0,
                     32'd0,
                     32'd0,
                     32'd0,
                     32'd0,
                     32'd0,
                     IO_RD );

    
endmodule