data/full_repos/permissive/190680822/testBench/cordic_tb.v
 line:72: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #2 clk = !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #800                                           \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #800\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #800\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #800\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #800\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/cordic_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n   #500\n   ^\n%Error: data/full_repos/permissive/190680822/testBench/cordic_tb.v:81: Unsupported or unknown PLI call: $monitor\n  $monitor($time, , COSout, , SINout, , angle);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/190680822/testBench/cordic_tb.v:81: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  $monitor($time, , COSout, , SINout, , angle);\n                  ^\n%Error: Exiting due to 2 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CORDIC_TESTBENCH;

  localparam width = 32;


  reg [width-1:0] Xin, Yin;
  reg [31:0] angle;
  reg clk;

  reg reset;

  wire [width-1:0] COSout, SINout;
  wire done;

  localparam An = 1073741824/0.82338012906;


  
  initial begin
      Xin = An;
      Yin = 0;
  

      clk = 'b0;
      forever
      begin
        #2 clk = !clk;
      end
  end
    
  initial begin


    angle = 'b00110101010101010101010101010101;
    reset = 1'b1;
    #2 reset = 1'b0;


    #800                                           
    angle = 'b00100000000000000000000000000000;
    reset = 1'b1;
    #2 reset = 1'b0;


    #800
    angle = 'b00101010101010101010101010101010;
    reset = 1'b1;
    #2 reset = 1'b0;


    #800
    angle = 'b01000000000000000000000000000000;
    reset = 1'b1;
    #2 reset = 1'b0;


    #800
    angle = 'b00110101010101010101010101010101;
    reset = 1'b1;
    #2 reset = 1'b0;    
    

    #800
    angle = 'b00000000000000000000000000000000;
    reset = 1'b1;
    #2 reset = 1'b0;

   #500
   $write("Simulation has finished");


  end

  CORDIC TEST_RUN(clk, COSout, SINout, Xin, Yin, angle,reset, done);


  initial
  $monitor($time, , COSout, , SINout, , angle);

endmodule
module CORDIC_TESTBENCH;


  localparam width = 32;


  reg [width-1:0] Xin, Yin;
  reg [31:0] angle;
  reg clk;

  reg reset;

  wire [width-1:0] COSout, SINout;
  wire done;

  localparam An = 1073741824/0.82338012906;


  
  initial begin
      Xin = An;
      Yin = 0;
  

      clk = 'b0;
      forever
      begin
        #2 clk = !clk;
      end
  end
    
  initial begin


    angle = 'b00110101010101010101010101010101;
    reset = 1'b1;
    #2 reset = 1'b0;


    #800                                           
    angle = 'b00100000000000000000000000000000;
    reset = 1'b1;
    #2 reset = 1'b0;


    #800
    angle = 'b00101010101010101010101010101010;
    reset = 1'b1;
    #2 reset = 1'b0;


    #800
    angle = 'b01000000000000000000000000000000;
    reset = 1'b1;
    #2 reset = 1'b0;


    #800
    angle = 'b00110101010101010101010101010101;
    reset = 1'b1;
    #2 reset = 1'b0;    
    

    #800
    angle = 'b00000000000000000000000000000000;
    reset = 1'b1;
    #2 reset = 1'b0;

   #500
   $write("Simulation has finished");


  end

  CORDIC TEST_RUN(clk, COSout, SINout, Xin, Yin, angle,reset, done);


  initial
  $monitor($time, , COSout, , SINout, , angle);

endmodule