data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v
 line:51: before: "("
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:3: Cannot find include file: tester.v\n`include "tester.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/s2p,data/full_repos/permissive/129155059/tester.v\n             data/full_repos/permissive/129155059/proyecto-01/s2p,data/full_repos/permissive/129155059/tester.v.v\n             data/full_repos/permissive/129155059/proyecto-01/s2p,data/full_repos/permissive/129155059/tester.v.sv\n             tester.v\n             tester.v.v\n             tester.v.sv\n             obj_dir/tester.v\n             obj_dir/tester.v.v\n             obj_dir/tester.v.sv\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:4: Cannot find include file: ffd_s2p_cond.v\n`include "ffd_s2p_cond.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:5: Cannot find include file: freq_div_cond.v\n`include "freq_div_cond.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:6: Cannot find include file: s2p_reg_cond.v\n`include "s2p_reg_cond.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:7: Cannot find include file: ffd_s2p_synth.v\n`include "ffd_s2p_synth.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:8: Cannot find include file: freq_div_synth.v\n`include "freq_div_synth.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:9: Cannot find include file: s2p_reg_synth.v\n`include "s2p_reg_synth.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:10: Cannot find include file: ffd_s2p_synth_delay.v\n`include "ffd_s2p_synth_delay.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:11: Cannot find include file: freq_div_synth_delay.v\n`include "freq_div_synth_delay.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:12: Cannot find include file: s2p_reg_synth_delay.v\n`include "s2p_reg_synth_delay.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:13: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/testbench.v:14: Cannot find include file: cmos_cells_delay.v\n`include "cmos_cells_delay.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module testbench;

  wire [2:0]  CLK_div_tb;
  wire [7:0]  Q0_cond_tb, Q1_cond_tb, Q2_cond_tb, Q3_cond_tb;
  wire [7:0]  P0_cond_tb, P1_cond_tb, P2_cond_tb, P3_cond_tb;
  wire        ENB_tb, reset_tb, CLK_tb;
  wire [3:0]  S_IN_tb;
  wire [1:0]  MODO_tb;
  wire        DIR_tb;


  wire [7:0]  Q0_synth_tb, Q1_synth_tb, Q2_synth_tb, Q3_synth_tb;
  wire [3:0]  data_out_synth_tb;
  wire [7:0]  P0_synth_tb, P1_synth_tb, P2_synth_tb, P3_synth_tb;

  wire [7:0]  Q0_synth_delay_tb, Q1_synth_delay_tb, Q2_synth_delay_tb, Q3_synth_delay_tb;
  wire [3:0]  data_out_synth_delay_tb;
  wire [7:0]  P0_synth_delay_tb, P1_synth_delay_tb, P2_synth_delay_tb, P3_synth_delay_tb;

  tester_s2p  letest_s2p( .CLK_div  (CLK_div_tb),
                          .Q0_cond  (Q0_cond_tb),
                          .Q1_cond  (Q1_cond_tb),
                          .Q2_cond  (Q2_cond_tb),
                          .Q3_cond  (Q3_cond_tb),
                          .Q0_synth  (Q0_synth_tb),
                          .Q1_synth  (Q1_synth_tb),
                          .Q2_synth  (Q2_synth_tb),
                          .Q3_synth  (Q3_synth_tb),
                          .Q0_synth_delay  (Q0_synth_delay_tb),
                          .Q1_synth_delay  (Q1_synth_delay_tb),
                          .Q2_synth_delay  (Q2_synth_delay_tb),
                          .Q3_synth_delay  (Q3_synth_delay_tb),
                          .P0_cond  (P0_cond_tb),
                          .P1_cond  (P1_cond_tb),
                          .P2_cond  (P2_cond_tb),
                          .P3_cond  (P3_cond_tb),
                          .P0_synth  (P0_synth_tb),
                          .P1_synth  (P1_synth_tb),
                          .P2_synth  (P2_synth_tb),
                          .P3_synth  (P3_synth_tb),
                          .P0_synth_delay  (P0_synth_delay_tb),
                          .P1_synth_delay  (P1_synth_delay_tb),
                          .P2_synth_delay  (P2_synth_delay_tb),
                          .P3_synth_delay  (P3_synth_delay_tb),
                          .CLK      (CLK_tb),
                          .ENB      (ENB_tb),
                          .reset    (reset_tb),
                          .S_IN     (S_IN_tb),
                          .MODO     (MODO_tb),
                          .DIR      (DIR_tb)
                          );



  s2p_reg_cond #(8) reg_lane3(  .CLK    (CLK_tb),

                            .ENB    (ENB_tb),
                            .S_IN   (S_IN_tb[3]),
                            .Q      (P3_cond_tb),
                            .MODO   (MODO_tb),
                            .DIR    (DIR_tb)
                            );

  s2p_reg_cond #(8) reg_lane2(  .CLK    (CLK_tb),

                            .ENB    (ENB_tb),
                            .S_IN   (S_IN_tb[2]),
                            .Q      (P2_cond_tb),
                            .MODO   (MODO_tb),
                            .DIR    (DIR_tb)
                            );

  s2p_reg_cond #(8) reg_lane1(  .CLK    (CLK_tb),

                            .ENB    (ENB_tb),
                            .S_IN   (S_IN_tb[1]),
                            .Q      (P1_cond_tb),
                            .MODO   (MODO_tb),
                            .DIR    (DIR_tb)
                            );

  s2p_reg_cond #(8) reg_lane0(  .CLK    (CLK_tb),

                            .ENB    (ENB_tb),
                            .S_IN   (S_IN_tb[0]),
                            .Q      (P0_cond_tb),
                            .MODO   (MODO_tb),
                            .DIR    (DIR_tb)
                            );

  ffd_s2p_cond ffd_lane3[7:0]( .CLK (CLK_div_tb[2]),
                               .D   (P3_cond_tb),
                               .ENB (ENB_tb),
                               .Q   (Q3_cond_tb)
                               );

  ffd_s2p_cond ffd_lane2[7:0]( .CLK (CLK_div_tb[2]),
                               .D   (P2_cond_tb),
                               .ENB (ENB_tb),
                               .Q   (Q2_cond_tb)
                               );

  ffd_s2p_cond ffd_lane1[7:0]( .CLK (CLK_div_tb[2]),
                               .D   (P1_cond_tb),
                               .ENB (ENB_tb),
                               .Q   (Q1_cond_tb)
                               );

  ffd_s2p_cond ffd_lane0[7:0]( .CLK (CLK_div_tb[2]),
                               .D   (P0_cond_tb),
                               .ENB (ENB_tb),
                               .Q   (Q0_cond_tb)
                               );



  s2p_reg_synth #(8) reg_lane3_synth( .CLK    (CLK_tb),

                                  .ENB    (ENB_tb),
                                  .S_IN   (S_IN_tb[3]),
                                  .Q      (P3_synth_tb),
                                  .MODO   (MODO_tb),
                                  .DIR    (DIR_tb)
                                  );

  s2p_reg_synth #(8) reg_lane2_synth( .CLK    (CLK_tb),

                                  .ENB    (ENB_tb),
                                  .S_IN   (S_IN_tb[2]),
                                  .Q      (P2_synth_tb),
                                  .MODO   (MODO_tb),
                                  .DIR    (DIR_tb)
                                  );

  s2p_reg_synth #(8) reg_lane1_synth( .CLK    (CLK_tb),

                                  .ENB    (ENB_tb),
                                  .S_IN   (S_IN_tb[1]),
                                  .Q      (P1_synth_tb),
                                  .MODO   (MODO_tb),
                                  .DIR    (DIR_tb)
                                  );

  s2p_reg_synth #(8) reg_lane0_synth( .CLK    (CLK_tb),

                                  .ENB    (ENB_tb),
                                  .S_IN   (S_IN_tb[0]),
                                  .Q      (P0_synth_tb),
                                  .MODO   (MODO_tb),
                                  .DIR    (DIR_tb)
                            );

  ffd_s2p_synth ffd_lane3_synth[7:0]( .CLK (CLK_div_tb[2]),
                                      .D   (P3_synth_tb),
                                      .ENB (ENB_tb),
                                      .Q   (Q3_synth_tb)
                                      );

  ffd_s2p_synth ffd_lane2_synth[7:0]( .CLK (CLK_div_tb[2]),
                                      .D   (P2_synth_tb),
                                      .ENB (ENB_tb),
                                      .Q   (Q2_synth_tb)
                                      );

  ffd_s2p_synth ffd_lane1_synth[7:0]( .CLK (CLK_div_tb[2]),
                                      .D   (P1_synth_tb),
                                      .ENB (ENB_tb),
                                      .Q   (Q1_synth_tb)
                                      );

  ffd_s2p_synth ffd_lane0_synth[7:0]( .CLK (CLK_div_tb[2]),
                                      .D   (P0_synth_tb),
                                      .ENB (ENB_tb),
                                      .Q   (Q0_synth_tb)
                                      );


  s2p_reg_synth_delay #(8) reg_lane3_synth_delay( .CLK    (CLK_tb),

                                              .ENB    (ENB_tb),
                                              .S_IN   (S_IN_tb[3]),
                                              .Q      (P3_synth_delay_tb),
                                              .MODO   (MODO_tb),
                                              .DIR    (DIR_tb)
                                              );

  s2p_reg_synth_delay #(8) reg_lane2_synth_delay( .CLK    (CLK_tb),

                                              .ENB    (ENB_tb),
                                              .S_IN   (S_IN_tb[2]),
                                              .Q      (P2_synth_delay_tb),
                                              .MODO   (MODO_tb),
                                              .DIR    (DIR_tb)
                                              );

  s2p_reg_synth_delay #(8) reg_lane1_synth_delay( .CLK    (CLK_tb),

                                              .ENB    (ENB_tb),
                                              .S_IN   (S_IN_tb[1]),
                                              .Q      (P1_synth_delay_tb),
                                              .MODO   (MODO_tb),
                                              .DIR    (DIR_tb)
                                              );

  s2p_reg_synth_delay #(8) reg_lane0_synth_delay( .CLK    (CLK_tb),

                                              .ENB    (ENB_tb),
                                              .S_IN   (S_IN_tb[0]),
                                              .Q      (P0_synth_delay_tb),
                                              .MODO   (MODO_tb),
                                              .DIR    (DIR_tb)
                                              );

  ffd_s2p_synth_delay ffd_lane3_synth_delay[7:0]( .CLK (CLK_div_tb[2]),
                                                  .D   (P3_synth_delay_tb),
                                                  .ENB (ENB_tb),
                                                  .Q   (Q3_synth_delay_tb)
                                                  );

  ffd_s2p_synth_delay ffd_lane2_synth_delay[7:0]( .CLK (CLK_div_tb[2]),
                                                  .D   (P2_synth_delay_tb),
                                                  .ENB (ENB_tb),
                                                  .Q   (Q2_synth_delay_tb)
                                                  );

  ffd_s2p_synth_delay ffd_lane1_synth_delay[7:0]( .CLK (CLK_div_tb[2]),
                                                  .D   (P1_synth_delay_tb),
                                                  .ENB (ENB_tb),
                                                  .Q   (Q1_synth_delay_tb)
                                                  );

  ffd_s2p_synth_delay ffd_lane0_synth_delay[7:0]( .CLK (CLK_div_tb[2]),
                                                  .D   (P0_synth_delay_tb),
                                                  .ENB (ENB_tb),
                                                  .Q   (Q0_synth_delay_tb)
                                                  );



  freq_div_cond divisor(.CLK  (CLK_tb),
                        .reset(reset_tb),
                        .CLK_2(CLK_div_tb[0]),
                        .CLK_4(CLK_div_tb[1]),
                        .CLK_8(CLK_div_tb[2])
                        );

endmodule
module testbench;


  wire [2:0]  CLK_div_tb;
  wire [7:0]  Q0_cond_tb, Q1_cond_tb, Q2_cond_tb, Q3_cond_tb;
  wire [7:0]  P0_cond_tb, P1_cond_tb, P2_cond_tb, P3_cond_tb;
  wire        ENB_tb, reset_tb, CLK_tb;
  wire [3:0]  S_IN_tb;
  wire [1:0]  MODO_tb;
  wire        DIR_tb;


  wire [7:0]  Q0_synth_tb, Q1_synth_tb, Q2_synth_tb, Q3_synth_tb;
  wire [3:0]  data_out_synth_tb;
  wire [7:0]  P0_synth_tb, P1_synth_tb, P2_synth_tb, P3_synth_tb;

  wire [7:0]  Q0_synth_delay_tb, Q1_synth_delay_tb, Q2_synth_delay_tb, Q3_synth_delay_tb;
  wire [3:0]  data_out_synth_delay_tb;
  wire [7:0]  P0_synth_delay_tb, P1_synth_delay_tb, P2_synth_delay_tb, P3_synth_delay_tb;

  tester_s2p  letest_s2p( .CLK_div  (CLK_div_tb),
                          .Q0_cond  (Q0_cond_tb),
                          .Q1_cond  (Q1_cond_tb),
                          .Q2_cond  (Q2_cond_tb),
                          .Q3_cond  (Q3_cond_tb),
                          .Q0_synth  (Q0_synth_tb),
                          .Q1_synth  (Q1_synth_tb),
                          .Q2_synth  (Q2_synth_tb),
                          .Q3_synth  (Q3_synth_tb),
                          .Q0_synth_delay  (Q0_synth_delay_tb),
                          .Q1_synth_delay  (Q1_synth_delay_tb),
                          .Q2_synth_delay  (Q2_synth_delay_tb),
                          .Q3_synth_delay  (Q3_synth_delay_tb),
                          .P0_cond  (P0_cond_tb),
                          .P1_cond  (P1_cond_tb),
                          .P2_cond  (P2_cond_tb),
                          .P3_cond  (P3_cond_tb),
                          .P0_synth  (P0_synth_tb),
                          .P1_synth  (P1_synth_tb),
                          .P2_synth  (P2_synth_tb),
                          .P3_synth  (P3_synth_tb),
                          .P0_synth_delay  (P0_synth_delay_tb),
                          .P1_synth_delay  (P1_synth_delay_tb),
                          .P2_synth_delay  (P2_synth_delay_tb),
                          .P3_synth_delay  (P3_synth_delay_tb),
                          .CLK      (CLK_tb),
                          .ENB      (ENB_tb),
                          .reset    (reset_tb),
                          .S_IN     (S_IN_tb),
                          .MODO     (MODO_tb),
                          .DIR      (DIR_tb)
                          );



  s2p_reg_cond #(8) reg_lane3(  .CLK    (CLK_tb),

                            .ENB    (ENB_tb),
                            .S_IN   (S_IN_tb[3]),
                            .Q      (P3_cond_tb),
                            .MODO   (MODO_tb),
                            .DIR    (DIR_tb)
                            );

  s2p_reg_cond #(8) reg_lane2(  .CLK    (CLK_tb),

                            .ENB    (ENB_tb),
                            .S_IN   (S_IN_tb[2]),
                            .Q      (P2_cond_tb),
                            .MODO   (MODO_tb),
                            .DIR    (DIR_tb)
                            );

  s2p_reg_cond #(8) reg_lane1(  .CLK    (CLK_tb),

                            .ENB    (ENB_tb),
                            .S_IN   (S_IN_tb[1]),
                            .Q      (P1_cond_tb),
                            .MODO   (MODO_tb),
                            .DIR    (DIR_tb)
                            );

  s2p_reg_cond #(8) reg_lane0(  .CLK    (CLK_tb),

                            .ENB    (ENB_tb),
                            .S_IN   (S_IN_tb[0]),
                            .Q      (P0_cond_tb),
                            .MODO   (MODO_tb),
                            .DIR    (DIR_tb)
                            );

  ffd_s2p_cond ffd_lane3[7:0]( .CLK (CLK_div_tb[2]),
                               .D   (P3_cond_tb),
                               .ENB (ENB_tb),
                               .Q   (Q3_cond_tb)
                               );

  ffd_s2p_cond ffd_lane2[7:0]( .CLK (CLK_div_tb[2]),
                               .D   (P2_cond_tb),
                               .ENB (ENB_tb),
                               .Q   (Q2_cond_tb)
                               );

  ffd_s2p_cond ffd_lane1[7:0]( .CLK (CLK_div_tb[2]),
                               .D   (P1_cond_tb),
                               .ENB (ENB_tb),
                               .Q   (Q1_cond_tb)
                               );

  ffd_s2p_cond ffd_lane0[7:0]( .CLK (CLK_div_tb[2]),
                               .D   (P0_cond_tb),
                               .ENB (ENB_tb),
                               .Q   (Q0_cond_tb)
                               );



  s2p_reg_synth #(8) reg_lane3_synth( .CLK    (CLK_tb),

                                  .ENB    (ENB_tb),
                                  .S_IN   (S_IN_tb[3]),
                                  .Q      (P3_synth_tb),
                                  .MODO   (MODO_tb),
                                  .DIR    (DIR_tb)
                                  );

  s2p_reg_synth #(8) reg_lane2_synth( .CLK    (CLK_tb),

                                  .ENB    (ENB_tb),
                                  .S_IN   (S_IN_tb[2]),
                                  .Q      (P2_synth_tb),
                                  .MODO   (MODO_tb),
                                  .DIR    (DIR_tb)
                                  );

  s2p_reg_synth #(8) reg_lane1_synth( .CLK    (CLK_tb),

                                  .ENB    (ENB_tb),
                                  .S_IN   (S_IN_tb[1]),
                                  .Q      (P1_synth_tb),
                                  .MODO   (MODO_tb),
                                  .DIR    (DIR_tb)
                                  );

  s2p_reg_synth #(8) reg_lane0_synth( .CLK    (CLK_tb),

                                  .ENB    (ENB_tb),
                                  .S_IN   (S_IN_tb[0]),
                                  .Q      (P0_synth_tb),
                                  .MODO   (MODO_tb),
                                  .DIR    (DIR_tb)
                            );

  ffd_s2p_synth ffd_lane3_synth[7:0]( .CLK (CLK_div_tb[2]),
                                      .D   (P3_synth_tb),
                                      .ENB (ENB_tb),
                                      .Q   (Q3_synth_tb)
                                      );

  ffd_s2p_synth ffd_lane2_synth[7:0]( .CLK (CLK_div_tb[2]),
                                      .D   (P2_synth_tb),
                                      .ENB (ENB_tb),
                                      .Q   (Q2_synth_tb)
                                      );

  ffd_s2p_synth ffd_lane1_synth[7:0]( .CLK (CLK_div_tb[2]),
                                      .D   (P1_synth_tb),
                                      .ENB (ENB_tb),
                                      .Q   (Q1_synth_tb)
                                      );

  ffd_s2p_synth ffd_lane0_synth[7:0]( .CLK (CLK_div_tb[2]),
                                      .D   (P0_synth_tb),
                                      .ENB (ENB_tb),
                                      .Q   (Q0_synth_tb)
                                      );


  s2p_reg_synth_delay #(8) reg_lane3_synth_delay( .CLK    (CLK_tb),

                                              .ENB    (ENB_tb),
                                              .S_IN   (S_IN_tb[3]),
                                              .Q      (P3_synth_delay_tb),
                                              .MODO   (MODO_tb),
                                              .DIR    (DIR_tb)
                                              );

  s2p_reg_synth_delay #(8) reg_lane2_synth_delay( .CLK    (CLK_tb),

                                              .ENB    (ENB_tb),
                                              .S_IN   (S_IN_tb[2]),
                                              .Q      (P2_synth_delay_tb),
                                              .MODO   (MODO_tb),
                                              .DIR    (DIR_tb)
                                              );

  s2p_reg_synth_delay #(8) reg_lane1_synth_delay( .CLK    (CLK_tb),

                                              .ENB    (ENB_tb),
                                              .S_IN   (S_IN_tb[1]),
                                              .Q      (P1_synth_delay_tb),
                                              .MODO   (MODO_tb),
                                              .DIR    (DIR_tb)
                                              );

  s2p_reg_synth_delay #(8) reg_lane0_synth_delay( .CLK    (CLK_tb),

                                              .ENB    (ENB_tb),
                                              .S_IN   (S_IN_tb[0]),
                                              .Q      (P0_synth_delay_tb),
                                              .MODO   (MODO_tb),
                                              .DIR    (DIR_tb)
                                              );

  ffd_s2p_synth_delay ffd_lane3_synth_delay[7:0]( .CLK (CLK_div_tb[2]),
                                                  .D   (P3_synth_delay_tb),
                                                  .ENB (ENB_tb),
                                                  .Q   (Q3_synth_delay_tb)
                                                  );

  ffd_s2p_synth_delay ffd_lane2_synth_delay[7:0]( .CLK (CLK_div_tb[2]),
                                                  .D   (P2_synth_delay_tb),
                                                  .ENB (ENB_tb),
                                                  .Q   (Q2_synth_delay_tb)
                                                  );

  ffd_s2p_synth_delay ffd_lane1_synth_delay[7:0]( .CLK (CLK_div_tb[2]),
                                                  .D   (P1_synth_delay_tb),
                                                  .ENB (ENB_tb),
                                                  .Q   (Q1_synth_delay_tb)
                                                  );

  ffd_s2p_synth_delay ffd_lane0_synth_delay[7:0]( .CLK (CLK_div_tb[2]),
                                                  .D   (P0_synth_delay_tb),
                                                  .ENB (ENB_tb),
                                                  .Q   (Q0_synth_delay_tb)
                                                  );



  freq_div_cond divisor(.CLK  (CLK_tb),
                        .reset(reset_tb),
                        .CLK_2(CLK_div_tb[0]),
                        .CLK_4(CLK_div_tb[1]),
                        .CLK_8(CLK_div_tb[2])
                        );

endmodule