data/full_repos/permissive/109209652/verilog/modelsim/testbench.v
 line:209: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:42: Cannot find file containing module: \'cam_sim\'\n cam_sim #(0,row_sz,col_sz) my_cam0(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109209652/verilog/modelsim,data/full_repos/permissive/109209652/cam_sim\n             data/full_repos/permissive/109209652/verilog/modelsim,data/full_repos/permissive/109209652/cam_sim.v\n             data/full_repos/permissive/109209652/verilog/modelsim,data/full_repos/permissive/109209652/cam_sim.sv\n             cam_sim\n             cam_sim.v\n             cam_sim.sv\n             obj_dir/cam_sim\n             obj_dir/cam_sim.v\n             obj_dir/cam_sim.sv\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:58: Cannot find file containing module: \'cam_sim\'\n cam_sim #(1,row_sz,col_sz) my_cam1(\n ^~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:103: Cannot find file containing module: \'sp_census\'\n sp_census #(row_sz,col_sz) my_census0(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:121: Cannot find file containing module: \'sp_census\'\n sp_census #(row_sz,col_sz) my_census1(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:140: Cannot find file containing module: \'census_window\'\n census_window #(3,row_sz,col_sz) my_wdw0(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:160: Cannot find file containing module: \'census_window\'\n census_window #(3,row_sz,col_sz) my_wdw1(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:180: Cannot find file containing module: \'correlate\'\n correlate #(row_sz, col_sz) my_corr(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/modelsim/testbench.v:197: Cannot find file containing module: \'vga_buf_sim\'\n vga_buf_sim my_vga(\n ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
	reg		clk;
	reg		reset;





	reg go;


	initial begin
		clk = 1'b0;
		go = 1'b1;
		

		reset = 1'b0;
		#10
		reset = 1'b1;
		#30
		reset = 1'b0;
	end


	always begin
		#10
		clk = !clk;
	end

	localparam row_sz = 450;
	localparam col_sz = 375;


	wire			pclk0;
	wire	[7:0]	cam0_val;
	wire	[9:0]	cam0_x;
	wire	[9:0]	cam0_y;
	wire			is_cam0_val;

	cam_sim #(0,row_sz,col_sz) my_cam0(
		.clk(clk),
		.reset(reset),
		.pclk(pclk0),
		.value(cam0_val),
		.x(cam0_x),
		.y(cam0_y),
		.is_val(is_cam0_val)
	);

	wire			pclk1;
	wire	[7:0]	cam1_val;
	wire	[9:0]	cam1_x;
	wire	[9:0]	cam1_y;
	wire			is_cam1_val;

	cam_sim #(1,row_sz,col_sz) my_cam1(
		.clk(clk),
		.reset(reset),
		.pclk(pclk1),
		.value(cam1_val),
		.x(cam1_x),
		.y(cam1_y),
		.is_val(is_cam1_val)
	);





	wire	[7:0]	cen0_val;
	wire	[9:0]	cen0_x;
	wire	[9:0]	cen0_y;
	wire			is_cen0_val;

	sp_census #(row_sz,col_sz) my_census0(
		.clk(pclk0),
		.reset(reset),
		.in_val(cam0_val),
		.in_x(cam0_x),
		.in_y(cam0_y),
		.is_in_val(is_cam0_val),
		.out_val(cen0_val),
		.out_x(cen0_x),
		.out_y(cen0_y),
		.is_out_val(is_cen0_val)
	);

	wire	[7:0]	cen1_val;
	wire	[9:0]	cen1_x;
	wire	[9:0]	cen1_y;
	wire			is_cen1_val;

	sp_census #(row_sz,col_sz) my_census1(
		.clk(pclk1),
		.reset(reset),
		.in_val(cam1_val),
		.in_x(cam1_x),
		.in_y(cam1_y),
		.is_in_val(is_cam1_val),
		.out_val(cen1_val),
		.out_x(cen1_x),
		.out_y(cen1_y),
		.is_out_val(is_cen1_val)
	);


	wire	[71:0]	wdw0_val;
	wire	[9:0]	wdw0_x;
	wire	[9:0]	wdw0_y;
	wire			is_wdw0_val;

	census_window #(3,row_sz,col_sz) my_wdw0(
		.clk(pclk0),
		.reset(reset),

		.in_val(cen0_val),
		.in_x(cen0_x),
		.in_y(cen0_y),
		.is_in_val(is_cen0_val),

		.out_val(wdw0_val),
		.out_x(wdw0_x),
		.out_y(wdw0_y),
		.is_out_val(is_wdw0_val)
	);

	wire	[71:0]	wdw1_val;
	wire	[9:0]	wdw1_x;
	wire	[9:0]	wdw1_y;
	wire			is_wdw1_val;

	census_window #(3,row_sz,col_sz) my_wdw1(
		.clk(pclk1),
		.reset(reset),

		.in_val(cen1_val),
		.in_x(cen1_x),
		.in_y(cen1_y),
		.is_in_val(is_cen1_val),

		.out_val(wdw1_val),
		.out_x(wdw1_x),
		.out_y(wdw1_y),
		.is_out_val(is_wdw1_val)
	);


	wire	[9:0]	out_x;
	wire	[9:0]	out_y;
	wire	[5:0]	disp_out_val;
	wire			is_disp_out_val;
	correlate #(row_sz, col_sz) my_corr(
		.clk(clk),
		.reset(reset),

		.left_bitvec(wdw0_val),
		.right_bitvec(wdw1_val),
		.bitvec_val(is_wdw0_val & is_wdw1_val),

		.input_x(wdw0_x),
		.input_y(wdw0_y),

		.out_x(out_x),
		.out_y(out_y),
		.disparity_val(is_disp_out_val),
		.disparity(disp_out_val)
	);

	vga_buf_sim my_vga(
		.pclk(pclk0),
		.reset(reset),
		.value({disp_out_val, 2'b00}),
		.x(out_x),
		.y(out_y),
		.is_val(is_disp_out_val)
	);


	initial begin
		#100
		$display("Yoooooooooo");
	end
endmodule
module testbench();

	reg		clk;
	reg		reset;





	reg go;


	initial begin
		clk = 1'b0;
		go = 1'b1;
		

		reset = 1'b0;
		#10
		reset = 1'b1;
		#30
		reset = 1'b0;
	end


	always begin
		#10
		clk = !clk;
	end

	localparam row_sz = 450;
	localparam col_sz = 375;


	wire			pclk0;
	wire	[7:0]	cam0_val;
	wire	[9:0]	cam0_x;
	wire	[9:0]	cam0_y;
	wire			is_cam0_val;

	cam_sim #(0,row_sz,col_sz) my_cam0(
		.clk(clk),
		.reset(reset),
		.pclk(pclk0),
		.value(cam0_val),
		.x(cam0_x),
		.y(cam0_y),
		.is_val(is_cam0_val)
	);

	wire			pclk1;
	wire	[7:0]	cam1_val;
	wire	[9:0]	cam1_x;
	wire	[9:0]	cam1_y;
	wire			is_cam1_val;

	cam_sim #(1,row_sz,col_sz) my_cam1(
		.clk(clk),
		.reset(reset),
		.pclk(pclk1),
		.value(cam1_val),
		.x(cam1_x),
		.y(cam1_y),
		.is_val(is_cam1_val)
	);





	wire	[7:0]	cen0_val;
	wire	[9:0]	cen0_x;
	wire	[9:0]	cen0_y;
	wire			is_cen0_val;

	sp_census #(row_sz,col_sz) my_census0(
		.clk(pclk0),
		.reset(reset),
		.in_val(cam0_val),
		.in_x(cam0_x),
		.in_y(cam0_y),
		.is_in_val(is_cam0_val),
		.out_val(cen0_val),
		.out_x(cen0_x),
		.out_y(cen0_y),
		.is_out_val(is_cen0_val)
	);

	wire	[7:0]	cen1_val;
	wire	[9:0]	cen1_x;
	wire	[9:0]	cen1_y;
	wire			is_cen1_val;

	sp_census #(row_sz,col_sz) my_census1(
		.clk(pclk1),
		.reset(reset),
		.in_val(cam1_val),
		.in_x(cam1_x),
		.in_y(cam1_y),
		.is_in_val(is_cam1_val),
		.out_val(cen1_val),
		.out_x(cen1_x),
		.out_y(cen1_y),
		.is_out_val(is_cen1_val)
	);


	wire	[71:0]	wdw0_val;
	wire	[9:0]	wdw0_x;
	wire	[9:0]	wdw0_y;
	wire			is_wdw0_val;

	census_window #(3,row_sz,col_sz) my_wdw0(
		.clk(pclk0),
		.reset(reset),

		.in_val(cen0_val),
		.in_x(cen0_x),
		.in_y(cen0_y),
		.is_in_val(is_cen0_val),

		.out_val(wdw0_val),
		.out_x(wdw0_x),
		.out_y(wdw0_y),
		.is_out_val(is_wdw0_val)
	);

	wire	[71:0]	wdw1_val;
	wire	[9:0]	wdw1_x;
	wire	[9:0]	wdw1_y;
	wire			is_wdw1_val;

	census_window #(3,row_sz,col_sz) my_wdw1(
		.clk(pclk1),
		.reset(reset),

		.in_val(cen1_val),
		.in_x(cen1_x),
		.in_y(cen1_y),
		.is_in_val(is_cen1_val),

		.out_val(wdw1_val),
		.out_x(wdw1_x),
		.out_y(wdw1_y),
		.is_out_val(is_wdw1_val)
	);


	wire	[9:0]	out_x;
	wire	[9:0]	out_y;
	wire	[5:0]	disp_out_val;
	wire			is_disp_out_val;
	correlate #(row_sz, col_sz) my_corr(
		.clk(clk),
		.reset(reset),

		.left_bitvec(wdw0_val),
		.right_bitvec(wdw1_val),
		.bitvec_val(is_wdw0_val & is_wdw1_val),

		.input_x(wdw0_x),
		.input_y(wdw0_y),

		.out_x(out_x),
		.out_y(out_y),
		.disparity_val(is_disp_out_val),
		.disparity(disp_out_val)
	);

	vga_buf_sim my_vga(
		.pclk(pclk0),
		.reset(reset),
		.value({disp_out_val, 2'b00}),
		.x(out_x),
		.y(out_y),
		.is_val(is_disp_out_val)
	);


	initial begin
		#100
		$display("Yoooooooooo");
	end
endmodule