data/full_repos/permissive/133245813/axi_shift_register/shift_register_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/133245813/axi_shift_register/shift_register_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #(T/2);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133245813/axi_shift_register/shift_register_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #(T/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/133245813/axi_shift_register/shift_register_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #(T*5);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/133245813/axi_shift_register/shift_register_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #(T*5);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/133245813/axi_shift_register/shift_register_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #T;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/133245813/axi_shift_register/shift_register_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #(T*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/133245813/axi_shift_register/shift_register_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #T;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/133245813/axi_shift_register/shift_register_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #(T*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/133245813/axi_shift_register/shift_register_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #(T*2);\n        ^\n%Error: data/full_repos/permissive/133245813/axi_shift_register/shift_register_tb.v:16: Cannot find file containing module: \'shift_register\'\n    shift_register dut\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133245813/axi_shift_register,data/full_repos/permissive/133245813/shift_register\n             data/full_repos/permissive/133245813/axi_shift_register,data/full_repos/permissive/133245813/shift_register.v\n             data/full_repos/permissive/133245813/axi_shift_register,data/full_repos/permissive/133245813/shift_register.sv\n             shift_register\n             shift_register.v\n             shift_register.sv\n             obj_dir/shift_register\n             obj_dir/shift_register.v\n             obj_dir/shift_register.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module shift_register_tb();
    localparam T = 10;
    
    reg clk;
    reg rst_n;
    reg dir;
    reg din;
    reg en;
    wire [3:0] q;
    
    shift_register dut
    (
        .clk(clk),
        .rst_n(rst_n),
        .dir(dir),
        .din(din),
        .en(en),
        .q(q)
    );

    always
    begin
        clk = 0;
        #(T/2);
        clk = 1;
        #(T/2);
    end
    
    initial
    begin
        dir = 0;
        din = 0;
        en = 0;
        

        rst_n = 0;
        #(T*5);
        rst_n = 1;
        #(T*5);
        

        dir = 0;
        en = 1;
        din = 1;
        #T;
        din = 0;
        #(T*2);
        din = 1;
        #T;
        en = 0;
        

        dir = 1;
        en = 1;
        din = 0;
        #(T*2);
        din = 1;
        #(T*2);
        en = 0;
    end

endmodule
module shift_register_tb();

    localparam T = 10;
    
    reg clk;
    reg rst_n;
    reg dir;
    reg din;
    reg en;
    wire [3:0] q;
    
    shift_register dut
    (
        .clk(clk),
        .rst_n(rst_n),
        .dir(dir),
        .din(din),
        .en(en),
        .q(q)
    );

    always
    begin
        clk = 0;
        #(T/2);
        clk = 1;
        #(T/2);
    end
    
    initial
    begin
        dir = 0;
        din = 0;
        en = 0;
        

        rst_n = 0;
        #(T*5);
        rst_n = 1;
        #(T*5);
        

        dir = 0;
        en = 1;
        din = 1;
        #T;
        din = 0;
        #(T*2);
        din = 1;
        #T;
        en = 0;
        

        dir = 1;
        en = 1;
        din = 0;
        #(T*2);
        din = 1;
        #(T*2);
        en = 0;
    end

endmodule