data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v
 line:77: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk = ~clk; \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n  initial $dumpfile("chdr_16sc_to_12sc_tb.vcd");\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n  initial $dumpvars(0,chdr_16sc_to_12sc_tb);\n          ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #50 reset = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #50000; \n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:63: syntax error, unexpected \'@\'\n       @(posedge clk) ;\n       ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:68: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:70: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:72: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:74: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:81: syntax error, unexpected \'@\'\n           @(posedge clk);\n           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:83: syntax error, unexpected \'@\'\n             @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:88: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:96: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:98: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:100: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:102: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:109: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:111: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:115: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:118: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:131: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:137: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/chdr_16sc_to_12sc_tb.v:151: syntax error, unexpected \'@\'\n      @(negedge reset);\n      ^\n%Error: Exiting due to 21 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module chdr_16sc_to_12sc_tb();
   
  reg clk = 0;
  reg reset = 1;

  always #10 clk = ~clk; 

  initial $dumpfile("chdr_16sc_to_12sc_tb.vcd");
  initial $dumpvars(0,chdr_16sc_to_12sc_tb);
   

  initial
    begin
      #50 reset = 0;
      #50000; 
      $finish;
    end


  reg [63:0] i_tdata;
  reg        i_tlast = 0;
  reg        i_tvalid = 0;
  wire       i_tready ;
  reg [7:0]  set_addr;
  reg [31:0] set_data;
  reg 	      set_stb;
   

  wire [63:0] o_tdata;
  wire        o_tlast;
   
  wire	       o_tvalid;
  reg 	       o_tready;

  chdr_16sc_to_12sc #(.BASE(89))dut
    (.clk(clk), .reset(reset),
     .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
     .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
     .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
   


  reg [63:0]  data[0:7];
  initial $readmemh("from16_to_x.hex", data);


  task test_packets;
     input [15:0] len;
     input [31:0] sid;
     reg [1:0]    index;
      
     begin
       index <= 0;

       @(posedge clk) ;

       i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, len + 16'd16,sid};
       i_tvalid <= 1;
       i_tlast <= 0;
       @(posedge clk);
       while (i_tready != 1)
         @(posedge clk);
       i_tdata <= {64'b0};
       @(posedge clk);
       while (i_tready != 1)
         @(posedge clk);
	 

       repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
         begin
           i_tdata <= {data[index]}; 
           index <= index+1;
           @(posedge clk);
           while (i_tready != 1)
             @(posedge clk);
      end
      i_tlast <= 1'b1;
      i_tdata <= {data[index]}; 

      @(posedge clk);
	 

      index <= 0;

      i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, len + 16'd16,sid};
      i_tvalid <= 1;
      i_tlast <= 0;
      @(posedge clk);
      while (i_tready != 1)
        @(posedge clk);
      i_tdata <= {64'b0};
      @(posedge clk);
      while (i_tready != 1)
        @(posedge clk);


      repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
      begin
        i_tdata <= {data[index]}; 
        index <= index+1;
        @(posedge clk);
          while (i_tready != 1)
        @(posedge clk);
      end
      i_tlast <= 1'b1;
      i_tdata <= {data[index]};
      @(posedge clk);

      while (i_tready != 1)
        @(posedge clk);
	 
      i_tvalid <= 0;
      i_tlast <= 0;
    end
  endtask


  task test_destination;
    input enable;
    input [15:0] dest_home;

    begin
      @(posedge clk);

      set_data <= {enable,dest_home};
      set_addr <= 89;
      set_stb <= 1;
         
      @(posedge clk);
      set_stb <= 0;
    end
  endtask



  initial
    begin
      i_tvalid <= 0;
      o_tready <= 1;

      i_tdata <= 0;
	
      @(negedge reset);
      @(posedge clk);
      @(posedge clk);


      test_destination(1,16'hFEED);


      test_destination(1,16'h1111);
      test_packets(4, 32'hDEAD_BEEF);


      test_destination(1,16'h2222);
      test_packets(8, 32'hDEAD_BEEF);


      test_destination(1,16'h3333);
      test_packets(12, 32'hDEAD_BEEF);


      test_destination(1,16'h4444);
      test_packets(16, 32'hDEAD_BEEF);


      test_destination(1,16'h5555);
      test_packets(20, 32'hDEAD_BEEF);


      test_destination(1,16'h6666);
      test_packets(24, 32'hDEAD_BEEF);


      test_destination(1,16'h7777);
      test_packets(28, 32'hDEAD_BEEF);


      test_destination(1,16'h8888);
      test_packets(32, 32'hDEAD_BEEF);

    end

endmodule
module chdr_16sc_to_12sc_tb();

   
  reg clk = 0;
  reg reset = 1;

  always #10 clk = ~clk; 

  initial $dumpfile("chdr_16sc_to_12sc_tb.vcd");
  initial $dumpvars(0,chdr_16sc_to_12sc_tb);
   

  initial
    begin
      #50 reset = 0;
      #50000; 
      $finish;
    end


  reg [63:0] i_tdata;
  reg        i_tlast = 0;
  reg        i_tvalid = 0;
  wire       i_tready ;
  reg [7:0]  set_addr;
  reg [31:0] set_data;
  reg 	      set_stb;
   

  wire [63:0] o_tdata;
  wire        o_tlast;
   
  wire	       o_tvalid;
  reg 	       o_tready;

  chdr_16sc_to_12sc #(.BASE(89))dut
    (.clk(clk), .reset(reset),
     .set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
     .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
     .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
   


  reg [63:0]  data[0:7];
  initial $readmemh("from16_to_x.hex", data);


  task test_packets;
     input [15:0] len;
     input [31:0] sid;
     reg [1:0]    index;
      
     begin
       index <= 0;

       @(posedge clk) ;

       i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, len + 16'd16,sid};
       i_tvalid <= 1;
       i_tlast <= 0;
       @(posedge clk);
       while (i_tready != 1)
         @(posedge clk);
       i_tdata <= {64'b0};
       @(posedge clk);
       while (i_tready != 1)
         @(posedge clk);
	 

       repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
         begin
           i_tdata <= {data[index]}; 
           index <= index+1;
           @(posedge clk);
           while (i_tready != 1)
             @(posedge clk);
      end
      i_tlast <= 1'b1;
      i_tdata <= {data[index]}; 

      @(posedge clk);
	 

      index <= 0;

      i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, len + 16'd16,sid};
      i_tvalid <= 1;
      i_tlast <= 0;
      @(posedge clk);
      while (i_tready != 1)
        @(posedge clk);
      i_tdata <= {64'b0};
      @(posedge clk);
      while (i_tready != 1)
        @(posedge clk);


      repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
      begin
        i_tdata <= {data[index]}; 
        index <= index+1;
        @(posedge clk);
          while (i_tready != 1)
        @(posedge clk);
      end
      i_tlast <= 1'b1;
      i_tdata <= {data[index]};
      @(posedge clk);

      while (i_tready != 1)
        @(posedge clk);
	 
      i_tvalid <= 0;
      i_tlast <= 0;
    end
  endtask


  task test_destination;
    input enable;
    input [15:0] dest_home;

    begin
      @(posedge clk);

      set_data <= {enable,dest_home};
      set_addr <= 89;
      set_stb <= 1;
         
      @(posedge clk);
      set_stb <= 0;
    end
  endtask



  initial
    begin
      i_tvalid <= 0;
      o_tready <= 1;

      i_tdata <= 0;
	
      @(negedge reset);
      @(posedge clk);
      @(posedge clk);


      test_destination(1,16'hFEED);


      test_destination(1,16'h1111);
      test_packets(4, 32'hDEAD_BEEF);


      test_destination(1,16'h2222);
      test_packets(8, 32'hDEAD_BEEF);


      test_destination(1,16'h3333);
      test_packets(12, 32'hDEAD_BEEF);


      test_destination(1,16'h4444);
      test_packets(16, 32'hDEAD_BEEF);


      test_destination(1,16'h5555);
      test_packets(20, 32'hDEAD_BEEF);


      test_destination(1,16'h6666);
      test_packets(24, 32'hDEAD_BEEF);


      test_destination(1,16'h7777);
      test_packets(28, 32'hDEAD_BEEF);


      test_destination(1,16'h8888);
      test_packets(32, 32'hDEAD_BEEF);

    end

endmodule