data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v
 line:144: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:138: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:140: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:152: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:164: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:163: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:168: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:169: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:31: Cannot find file containing module: \'MIPS\'\nMIPS mips(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/sim/lab_simulations,data/full_repos/permissive/117026779/MIPS\n             data/full_repos/permissive/117026779/sim/lab_simulations,data/full_repos/permissive/117026779/MIPS.v\n             data/full_repos/permissive/117026779/sim/lab_simulations,data/full_repos/permissive/117026779/MIPS.sv\n             MIPS\n             MIPS.v\n             MIPS.sv\n             obj_dir/MIPS\n             obj_dir/MIPS.v\n             obj_dir/MIPS.sv\n%Error: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:46: Cannot find file containing module: \'OR\'\nOR #(.WIDTH(2))\n^~\n%Error: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:54: Cannot find file containing module: \'ROM\'\nROM #(\n^~~\n%Error: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:64: Cannot find file containing module: \'RAM_B\'\nRAM_B #(\n^~~~~\n%Error: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:78: Cannot find file containing module: \'RAM_B\'\nRAM_B #(\n^~~~~\n%Error: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:92: Cannot find file containing module: \'RAM_B\'\n RAM_B #(\n ^~~~~\n%Error: data/full_repos/permissive/117026779/sim/lab_simulations/TestMIPS.v:106: Cannot find file containing module: \'RAM_B\'\nRAM_B #(\n^~~~~\n%Error: Exiting due to 7 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestMIPS;

reg clk;
reg rst;

wire [31:0] AddressBus, DataBus, ProgramCounter, Instruction, ALUResult;
wire BusCycle, MemRead;
wire [3:0] MemWrite;

MIPS mips(
    .clk(!clk),
    .rst(rst),
    .BusCycle(BusCycle),
    .MemWrite(MemWrite),
    .MemRead(MemRead),
    .AddressBus(AddressBus),
    .DataBus(DataBus),
    .ProgramCounter(ProgramCounter),
    .ALUResult(ALUResult),
    .Instruction(Instruction)
);

wire ram_cs;

OR #(.WIDTH(2))
ram_cs_or
(
    .in({ |MemWrite, MemRead }),
	.out(ram_cs)
);


ROM #(
    .LENGTH(32'h1000),
    .WIDTH(32),
    .FILE_NAME("CPU_TEST.mem")
) rom (
	.a({2'b00, ProgramCounter[31:2]}),
	.out(Instruction)
);


RAM_B #(
    .LENGTH(32'd255),
    .COLUMN(3),
    .USE_FILE(1),
    .FILE_NAME("ram.mem")
) ramb_3 (
    .clk(clk),
    .we(MemWrite[3]),
    .cs(ram_cs),
    .oe(MemRead),
    .address(AddressBus[13:2]),
    .data(DataBus[31:24])
);

RAM_B #(
    .LENGTH(32'd255),
    .COLUMN(2),
    .USE_FILE(1),
    .FILE_NAME("ram.mem")
) ramb_2 (
    .clk(clk),
    .we(MemWrite[2]),
    .cs(ram_cs),
    .oe(MemRead),
    .address(AddressBus[13:2]),
    .data(DataBus[23:16])
);

 RAM_B #(
    .LENGTH(32'd255),
    .COLUMN(1),
    .USE_FILE(1),
    .FILE_NAME("ram.mem")
) ramb_1 (
    .clk(clk),
    .we(MemWrite[1]),
    .cs(ram_cs),
    .oe(MemRead),
    .address(AddressBus[13:2]),
    .data(DataBus[15:8])
);

RAM_B #(
    .LENGTH(32'd255),
    .COLUMN(0),
    .USE_FILE(1),
    .FILE_NAME("ram.mem")
) ramb_0 (
    .clk(clk),
    .we(MemWrite[0]),
    .cs(ram_cs),
    .oe(MemRead),
    .address(AddressBus[13:2]),
    .data(DataBus[7:0])
);















task RESET;
begin
    rst = 0;
    clk = 0;
    #5
    rst = 1;
    #5
    rst = 0;
    clk = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask

parameter FULL_CYCLE = 32'd60;

initial begin
    #10
    #10
	RESET;
	CLOCK(FULL_CYCLE);

    #10 $stop;
    #5 $finish;
end

endmodule
module TestMIPS;


reg clk;
reg rst;

wire [31:0] AddressBus, DataBus, ProgramCounter, Instruction, ALUResult;
wire BusCycle, MemRead;
wire [3:0] MemWrite;

MIPS mips(
    .clk(!clk),
    .rst(rst),
    .BusCycle(BusCycle),
    .MemWrite(MemWrite),
    .MemRead(MemRead),
    .AddressBus(AddressBus),
    .DataBus(DataBus),
    .ProgramCounter(ProgramCounter),
    .ALUResult(ALUResult),
    .Instruction(Instruction)
);

wire ram_cs;

OR #(.WIDTH(2))
ram_cs_or
(
    .in({ |MemWrite, MemRead }),
	.out(ram_cs)
);


ROM #(
    .LENGTH(32'h1000),
    .WIDTH(32),
    .FILE_NAME("CPU_TEST.mem")
) rom (
	.a({2'b00, ProgramCounter[31:2]}),
	.out(Instruction)
);


RAM_B #(
    .LENGTH(32'd255),
    .COLUMN(3),
    .USE_FILE(1),
    .FILE_NAME("ram.mem")
) ramb_3 (
    .clk(clk),
    .we(MemWrite[3]),
    .cs(ram_cs),
    .oe(MemRead),
    .address(AddressBus[13:2]),
    .data(DataBus[31:24])
);

RAM_B #(
    .LENGTH(32'd255),
    .COLUMN(2),
    .USE_FILE(1),
    .FILE_NAME("ram.mem")
) ramb_2 (
    .clk(clk),
    .we(MemWrite[2]),
    .cs(ram_cs),
    .oe(MemRead),
    .address(AddressBus[13:2]),
    .data(DataBus[23:16])
);

 RAM_B #(
    .LENGTH(32'd255),
    .COLUMN(1),
    .USE_FILE(1),
    .FILE_NAME("ram.mem")
) ramb_1 (
    .clk(clk),
    .we(MemWrite[1]),
    .cs(ram_cs),
    .oe(MemRead),
    .address(AddressBus[13:2]),
    .data(DataBus[15:8])
);

RAM_B #(
    .LENGTH(32'd255),
    .COLUMN(0),
    .USE_FILE(1),
    .FILE_NAME("ram.mem")
) ramb_0 (
    .clk(clk),
    .we(MemWrite[0]),
    .cs(ram_cs),
    .oe(MemRead),
    .address(AddressBus[13:2]),
    .data(DataBus[7:0])
);















task RESET;
begin
    rst = 0;
    clk = 0;
    #5
    rst = 1;
    #5
    rst = 0;
    clk = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask

parameter FULL_CYCLE = 32'd60;

initial begin
    #10
    #10
	RESET;
	CLOCK(FULL_CYCLE);

    #10 $stop;
    #5 $finish;
end

endmodule