data/full_repos/permissive/119715647/sim/Timer/TimerTop_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/TimerTop_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/TimerTop_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/TimerTop_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/TimerTop_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #40;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/TimerTop_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #40;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/TimerTop_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #40;\n    ^\n%Error: data/full_repos/permissive/119715647/sim/Timer/TimerTop_tb.v:8: Cannot find file containing module: \'TimerTop\'\n  TimerTop DUT_1s_tb(clk, rst, rLED, gLED);\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119715647/sim/Timer,data/full_repos/permissive/119715647/TimerTop\n             data/full_repos/permissive/119715647/sim/Timer,data/full_repos/permissive/119715647/TimerTop.v\n             data/full_repos/permissive/119715647/sim/Timer,data/full_repos/permissive/119715647/TimerTop.sv\n             TimerTop\n             TimerTop.v\n             TimerTop.sv\n             obj_dir/TimerTop\n             obj_dir/TimerTop.v\n             obj_dir/TimerTop.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TimerTop_tb();
  reg clk, rst;

  wire gLED, rLED;

  TimerTop DUT_1s_tb(clk, rst, rLED, gLED);

  always begin
    clk = 1;
    #10;
    clk = 0;
    #10;
  end

  initial begin
    #5;
    #40;
    rst = 0;
    #40;
    rst = 1;
    #40;
  end
endmodule
module TimerTop_tb();

  reg clk, rst;

  wire gLED, rLED;

  TimerTop DUT_1s_tb(clk, rst, rLED, gLED);

  always begin
    clk = 1;
    #10;
    clk = 0;
    #10;
  end

  initial begin
    #5;
    #40;
    rst = 0;
    #40;
    rst = 1;
    #40;
  end
endmodule