data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter.v
data/verilator_xmls/b75a9b8a-66a8-4964-a2fd-c1d4607e79b5.xml
module spio_rr_arbiter#(
                         parameter PKT_BITS = 72
                       )
                       ( input wire CLK_IN
                       , input wire RESET_IN

                       , input  wire [PKT_BITS-1:0] DATA0_IN
                       , input  wire                VLD0_IN
                       , output wire                RDY0_OUT
                       , input  wire [PKT_BITS-1:0] DATA1_IN
                       , input  wire                VLD1_IN
                       , output wire                RDY1_OUT

                       , output reg  [PKT_BITS-1:0] DATA_OUT
                       , output reg                 VLD_OUT
                       , input  wire                RDY_IN
                       );















































localparam RUN    = 1'b0;
localparam PARKED = 1'b1;

reg inputstate0_i;
reg inputstate1_i;


localparam P0 = 1'b0;
localparam P1 = 1'b1;

reg rrstate_i;


reg [PKT_BITS-1:0] parkreg0_i;
reg [PKT_BITS-1:0] parkreg1_i;



wire cansend_i = !VLD_OUT || RDY_IN;



wire transfer_i = VLD_OUT && RDY_IN;



wire vld0_i = (inputstate0_i == PARKED) ? 1'b1 : VLD0_IN;
wire vld1_i = (inputstate1_i == PARKED) ? 1'b1 : VLD1_IN;



wire [PKT_BITS-1:0] data0_i = (inputstate0_i == PARKED) ? parkreg0_i : DATA0_IN;
wire [PKT_BITS-1:0] data1_i = (inputstate1_i == PARKED) ? parkreg1_i : DATA1_IN;





wire selected0_i = rrstate_i == P0 || !vld1_i;
wire selected1_i = rrstate_i == P1 || !vld0_i;



wire wait0_i = !cansend_i || !selected0_i;
wire wait1_i = !cansend_i || !selected1_i;


wire park0_i = VLD0_IN && RDY0_OUT && wait0_i;
wire park1_i = VLD1_IN && RDY1_OUT && wait1_i;


wire go0_i = !wait0_i;
wire go1_i = !wait1_i;










assign RDY0_OUT = inputstate0_i == RUN;
assign RDY1_OUT = inputstate1_i == RUN;






always @ (posedge CLK_IN)
	if (park0_i)
		parkreg0_i <= DATA0_IN;

always @ (posedge CLK_IN)
	if (park1_i)
		parkreg1_i <= DATA1_IN;








always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			DATA_OUT <= {PKT_BITS{1'bX}};
			VLD_OUT  <= 1'b0;
		end
	else
		if (cansend_i)
			begin
				if (selected0_i && vld0_i && (RDY0_OUT || inputstate0_i == PARKED))
					begin
						DATA_OUT <= data0_i;
						VLD_OUT  <= vld0_i;
					end
				else if (selected1_i && vld1_i && (RDY1_OUT || inputstate1_i == PARKED))
					begin
						DATA_OUT <= data1_i;
						VLD_OUT  <= vld1_i;
					end
				else
					begin
						DATA_OUT <= {PKT_BITS{1'bX}};
						VLD_OUT  <= 1'b0;
					end
			end

















always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		inputstate0_i <= RUN;
	else
		case (inputstate0_i)
			RUN:    if (park0_i)  inputstate0_i <= PARKED;
			PARKED: if (go0_i)    inputstate0_i <= RUN;
		endcase

always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		inputstate1_i <= RUN;
	else
		case (inputstate1_i)
			RUN:    if (park1_i)  inputstate1_i <= PARKED;
			PARKED: if (go1_i)    inputstate1_i <= RUN;
		endcase



















always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		rrstate_i <= P0;
	else
		if (transfer_i)
			case (rrstate_i)
				P0: rrstate_i <= P1;
				P1: rrstate_i <= P0;
			endcase



endmodule
module spio_rr_arbiter#(
                         parameter PKT_BITS = 72
                       )
                       ( input wire CLK_IN
                       , input wire RESET_IN

                       , input  wire [PKT_BITS-1:0] DATA0_IN
                       , input  wire                VLD0_IN
                       , output wire                RDY0_OUT
                       , input  wire [PKT_BITS-1:0] DATA1_IN
                       , input  wire                VLD1_IN
                       , output wire                RDY1_OUT

                       , output reg  [PKT_BITS-1:0] DATA_OUT
                       , output reg                 VLD_OUT
                       , input  wire                RDY_IN
                       );
















































localparam RUN    = 1'b0;
localparam PARKED = 1'b1;

reg inputstate0_i;
reg inputstate1_i;


localparam P0 = 1'b0;
localparam P1 = 1'b1;

reg rrstate_i;


reg [PKT_BITS-1:0] parkreg0_i;
reg [PKT_BITS-1:0] parkreg1_i;



wire cansend_i = !VLD_OUT || RDY_IN;



wire transfer_i = VLD_OUT && RDY_IN;



wire vld0_i = (inputstate0_i == PARKED) ? 1'b1 : VLD0_IN;
wire vld1_i = (inputstate1_i == PARKED) ? 1'b1 : VLD1_IN;



wire [PKT_BITS-1:0] data0_i = (inputstate0_i == PARKED) ? parkreg0_i : DATA0_IN;
wire [PKT_BITS-1:0] data1_i = (inputstate1_i == PARKED) ? parkreg1_i : DATA1_IN;





wire selected0_i = rrstate_i == P0 || !vld1_i;
wire selected1_i = rrstate_i == P1 || !vld0_i;



wire wait0_i = !cansend_i || !selected0_i;
wire wait1_i = !cansend_i || !selected1_i;


wire park0_i = VLD0_IN && RDY0_OUT && wait0_i;
wire park1_i = VLD1_IN && RDY1_OUT && wait1_i;


wire go0_i = !wait0_i;
wire go1_i = !wait1_i;










assign RDY0_OUT = inputstate0_i == RUN;
assign RDY1_OUT = inputstate1_i == RUN;






always @ (posedge CLK_IN)
	if (park0_i)
		parkreg0_i <= DATA0_IN;

always @ (posedge CLK_IN)
	if (park1_i)
		parkreg1_i <= DATA1_IN;








always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			DATA_OUT <= {PKT_BITS{1'bX}};
			VLD_OUT  <= 1'b0;
		end
	else
		if (cansend_i)
			begin
				if (selected0_i && vld0_i && (RDY0_OUT || inputstate0_i == PARKED))
					begin
						DATA_OUT <= data0_i;
						VLD_OUT  <= vld0_i;
					end
				else if (selected1_i && vld1_i && (RDY1_OUT || inputstate1_i == PARKED))
					begin
						DATA_OUT <= data1_i;
						VLD_OUT  <= vld1_i;
					end
				else
					begin
						DATA_OUT <= {PKT_BITS{1'bX}};
						VLD_OUT  <= 1'b0;
					end
			end

















always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		inputstate0_i <= RUN;
	else
		case (inputstate0_i)
			RUN:    if (park0_i)  inputstate0_i <= PARKED;
			PARKED: if (go0_i)    inputstate0_i <= RUN;
		endcase

always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		inputstate1_i <= RUN;
	else
		case (inputstate1_i)
			RUN:    if (park1_i)  inputstate1_i <= PARKED;
			PARKED: if (go1_i)    inputstate1_i <= RUN;
		endcase



















always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		rrstate_i <= P0;
	else
		if (transfer_i)
			case (rrstate_i)
				P0: rrstate_i <= P1;
				P1: rrstate_i <= P0;
			endcase



endmodule