data/full_repos/permissive/127311496/src/platform/SWORD4/Seg7Device.v
1: b"%Error: data/full_repos/permissive/127311496/src/platform/SWORD4/Seg7Device.v:22: Cannot find file containing module: 'ShiftReg'\n ShiftReg #(.WIDTH(64), .ONTIME(12'hC00)) U2(.clk(clkIO), .pdata(dispData), .sout(sout));\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/platform/SWORD4,data/full_repos/permissive/127311496/ShiftReg\n             data/full_repos/permissive/127311496/src/platform/SWORD4,data/full_repos/permissive/127311496/ShiftReg.v\n             data/full_repos/permissive/127311496/src/platform/SWORD4,data/full_repos/permissive/127311496/ShiftReg.sv\n             ShiftReg\n             ShiftReg.v\n             ShiftReg.sv\n             obj_dir/ShiftReg\n             obj_dir/ShiftReg.v\n             obj_dir/ShiftReg.sv\n%Error: Exiting due to 1 error(s)\n"
module Seg7Device(
	input clkIO, input [1:0] clkScan, input clkBlink,
	input [31:0] data, input [7:0] point, input [7:0] LES,
	output [2:0] sout, output reg [7:0] segment, output [1:0] anode
);
	wire [63:0] dispData;
	wire [31:0] dispPattern;
	
	Seg7Decode U0(.hex(data), .point(point),
		.LE(LES & {8{clkBlink}}), .pattern(dispData));
	Seg7Remap U1(.I(data), .O(dispPattern));

	ShiftReg #(.WIDTH(64), .ONTIME(12'hC00)) U2(.clk(clkIO), .pdata(dispData), .sout(sout));

	always @*
		case(clkScan)




		2'b00: segment <= ~dispPattern[ 7: 0];
		2'b01: segment <= ~dispPattern[15: 8];
		2'b10: segment <= ~dispPattern[23:16];
		2'b11: segment <= ~dispPattern[31:24];
		endcase
	assign anode = clkScan;
	
endmodule
module Seg7Device(
	input clkIO, input [1:0] clkScan, input clkBlink,
	input [31:0] data, input [7:0] point, input [7:0] LES,
	output [2:0] sout, output reg [7:0] segment, output [1:0] anode
);

	wire [63:0] dispData;
	wire [31:0] dispPattern;
	
	Seg7Decode U0(.hex(data), .point(point),
		.LE(LES & {8{clkBlink}}), .pattern(dispData));
	Seg7Remap U1(.I(data), .O(dispPattern));

	ShiftReg #(.WIDTH(64), .ONTIME(12'hC00)) U2(.clk(clkIO), .pdata(dispData), .sout(sout));

	always @*
		case(clkScan)




		2'b00: segment <= ~dispPattern[ 7: 0];
		2'b01: segment <= ~dispPattern[15: 8];
		2'b10: segment <= ~dispPattern[23:16];
		2'b11: segment <= ~dispPattern[31:24];
		endcase
	assign anode = clkScan;
	
endmodule