data/full_repos/permissive/205673649/MIPS/Source/top_mips.v
1: b'%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/top_mips.v:121: Operator ASSIGNW expects 96 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 65 bits.\n                                                                               : ... In instance top_mips\nassign o_if_id = {\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/top_mips.v:128: Operator ASSIGNW expects 160 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 204 bits.\n                                                                               : ... In instance top_mips\nassign o_id_ex = { \n               ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/top_mips.v:147: Operator ASSIGNW expects 128 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 112 bits.\n                                                                               : ... In instance top_mips\nassign o_ex_mem = {\n                ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/top_mips.v:157: Operator ASSIGNW expects 96 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 72 bits.\n                                                                               : ... In instance top_mips\nassign o_mem_wb = {\n                ^\n%Error: data/full_repos/permissive/205673649/MIPS/Source/top_mips.v:167: Cannot find file containing module: \'tl_instruction_fetch\'\ntl_instruction_fetch\n^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/MIPS/Source,data/full_repos/permissive/205673649/tl_instruction_fetch\n             data/full_repos/permissive/205673649/MIPS/Source,data/full_repos/permissive/205673649/tl_instruction_fetch.v\n             data/full_repos/permissive/205673649/MIPS/Source,data/full_repos/permissive/205673649/tl_instruction_fetch.sv\n             tl_instruction_fetch\n             tl_instruction_fetch.v\n             tl_instruction_fetch.sv\n             obj_dir/tl_instruction_fetch\n             obj_dir/tl_instruction_fetch.v\n             obj_dir/tl_instruction_fetch.sv\n%Error: data/full_repos/permissive/205673649/MIPS/Source/top_mips.v:191: Cannot find file containing module: \'tl_instruction_decode\'\ntl_instruction_decode\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/MIPS/Source/top_mips.v:231: Cannot find file containing module: \'tl_execute\'\ntl_execute\n^~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/MIPS/Source/top_mips.v:270: Cannot find file containing module: \'tl_memory\'\ntl_memory\n^~~~~~~~~\n%Error: data/full_repos/permissive/205673649/MIPS/Source/top_mips.v:296: Cannot find file containing module: \'tl_write_back\'\ntl_write_back\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/MIPS/Source/top_mips.v:314: Cannot find file containing module: \'unidad_cortocircuito\'\nunidad_cortocircuito\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 4 warning(s)\n'
module top_mips
#(
    parameter LEN = 32,
    parameter NB_IF_ID = 96,
    parameter NB_ID_EX = 160,
    parameter NB_EX_MEM = 128,
    parameter NB_MEM_WB = 96,
    parameter CANT_REG = 16,
    parameter CANT_MEM = 8  
)
(
    input i_clk,
    input i_rst,
    input [LEN-1:0] dir_mem_instr,
    input wea_mem_instr,
    input [LEN-1:0] addr_mem_inst,
    output [NB_IF_ID-1:0] o_if_id,
    output [NB_ID_EX-1:0] o_id_ex,
    output [NB_EX_MEM-1:0] o_ex_mem,
    output [NB_MEM_WB-1:0] o_mem_wb
);



localparam CANTIDAD_REGISTROS = `CANTIDAD_REGISTROS;
localparam NB_ADDRESS_REGISTROS = `NB_ADDRESS_REGISTROS;
localparam NB_SIGN_EXTEND = `NB_SIGN_EXTEND;
localparam NB_INSTRUCCION = `NB_INSTRUCCION;
localparam NB_ALU_CONTROL = `NB_ALU_CONTROL;
localparam NB_ALU_OP = `NB_ALU_OP;
localparam INIT_FILE_IM = `INIT_FILE_IM;

localparam NB_CTRL_WB = `NB_CTRL_WB; 
localparam NB_CTRL_MEM = `NB_CTRL_MEM; 
localparam NB_CTRL_EX = `NB_CTRL_EX; 


wire [LEN-1:0] branch_dir;
wire PCSrc;
wire [LEN-1:0] instruccion;
wire [LEN-1:0] out_adder_if_id;
wire [LEN-1:0] contador_programa;
wire flag_halt;


wire [LEN-1:0] write_data_banco_reg;
wire [LEN-1:0] out_adder_id_ex;
wire [NB_ADDRESS_REGISTROS-1:0] rs;
wire [NB_ADDRESS_REGISTROS-1:0] rd;
wire [NB_ADDRESS_REGISTROS-1:0] rt;
wire [NB_ADDRESS_REGISTROS-1:0] shamt;
wire [LEN-1:0] dato1;
wire [LEN-1:0] dato2_if_ex;
wire [LEN-1:0] sign_extend;
wire [NB_CTRL_WB-1:0] ctrl_wb_id_ex;
wire [NB_CTRL_MEM-1:0] ctrl_mem_id_ex;
wire [NB_CTRL_EX-1:0] ctrl_ex_id_ex;
wire flag_stall;
wire [LEN-1:0] dir_jump;
wire flag_jump;


wire [LEN-1:0] dato2_ex_mem;
wire [LEN-1:0] result_alu_ex_mem;
wire alu_zero;
wire [NB_CTRL_WB-1:0] ctrl_wb_ex_mem;
wire [NB_CTRL_MEM-1:0] ctrl_mem_ex_mem;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_ex_mem;


wire [LEN-1:0] result_alu_mem_wb;
wire [LEN-1:0] read_data_memory;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_mem_wb;
wire [NB_CTRL_WB-1:0] ctrl_wb_mem_wb;


wire regwrite_wb_id;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_wb_id;


wire [1:0] ctrl_muxA_corto;
wire [1:0] ctrl_muxB_corto;



assign o_if_id = {
                  contador_programa,
                  instruccion,

                  flag_halt
                  }; 

assign o_id_ex = { 

                   ctrl_wb_id_ex,
                   ctrl_mem_id_ex,
                   ctrl_ex_id_ex,

                   shamt,
                   rs,
                   rt,
                   rd,
                   out_adder_id_ex,
                   dir_jump,
                   sign_extend,
                   dato1,
                   dato2_if_ex,
                   flag_stall,
                   flag_jump
                  };   
                   
assign o_ex_mem = {

                   ctrl_wb_ex_mem,
                   ctrl_mem_ex_mem,
                   write_reg_ex_mem,
                   branch_dir,
                   result_alu_ex_mem,
                   dato2_ex_mem
                   };

assign o_mem_wb = {

                   PCSrc,
                   ctrl_wb_mem_wb,
                   write_reg_mem_wb,
                   result_alu_mem_wb,
                   read_data_memory
                   };


tl_instruction_fetch
#(
    .LEN(LEN),
    .INIT_FILE_IM(INIT_FILE_IM)
)
    u_tl_instruction_fetch
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_branch_dir(branch_dir),
    .i_PCSrc(PCSrc),
    .i_flag_stall(flag_stall),
    .i_flag_jump(flag_jump),
    .i_dir_jump(dir_jump),
    .i_dir_mem_instr(dir_mem_instr),
    .i_wea_mem_instr(wea_mem_instr),
    .i_addr_mem_inst(addr_mem_inst),
    .o_instruccion(instruccion),
    .o_adder(out_adder_if_id),
    .o_contador_programa(contador_programa),
    .o_flag_halt(flag_halt)
);


tl_instruction_decode
#(
    .LEN(LEN),
    .CANTIDAD_REGISTROS(CANTIDAD_REGISTROS),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_SIGN_EXTEND(NB_SIGN_EXTEND),
    .NB_INSTRUCCION(NB_INSTRUCCION),    
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_CTRL_EX(NB_CTRL_EX),
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_ALU_OP(NB_ALU_OP)
)
    u_tl_instruction_decode
(
    .i_clk(i_clk),          
    .i_rst(i_rst),
    .i_instruccion(instruccion),
    .i_write_data(write_data_banco_reg),
    .i_write_reg(write_reg_wb_id),
    .i_adder_pc(out_adder_if_id),
    .i_RegWrite(regwrite_wb_id),
    .i_flush(PCSrc), 
    .o_adder_pc(out_adder_id_ex), 
    .o_rs(rs),
    .o_rd(rd),
    .o_rt(rt),    
    .o_shamt(shamt),   
    .o_dato1(dato1),
    .o_dato2(dato2_if_ex),
    .o_sign_extend(sign_extend),
    .o_ctrl_wb(ctrl_wb_id_ex),
    .o_ctrl_mem(ctrl_mem_id_ex),
    .o_ctrl_ex(ctrl_ex_id_ex),
    .o_flag_stall(flag_stall),
    .o_dir_jump(dir_jump),
    .o_flag_jump(flag_jump)
);


tl_execute
#(
    .LEN(LEN),
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_CTRL_EX(NB_CTRL_EX)
    
)
    u_tl_execute
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_adder_id(out_adder_id_ex),
    .i_dato1(dato1),
    .i_dato2(dato2_if_ex),
    .i_sign_extend(sign_extend),
    .i_ctrl_wb(ctrl_wb_id_ex),
    .i_ctrl_mem(ctrl_mem_id_ex),
    .i_ctrl_ex(ctrl_ex_id_ex),
    .i_rd(rd),
    .i_rt(rt),
    .i_shamt(shamt),
    .i_ctrl_muxA_corto(ctrl_muxA_corto),
    .i_ctrl_muxB_corto(ctrl_muxB_corto),
    .i_rd_mem_corto(result_alu_ex_mem),
    .i_rd_wb_corto(write_data_banco_reg),
    .i_flush(PCSrc),
    .o_alu_zero(alu_zero),
    .o_write_reg(write_reg_ex_mem),
    .o_ctrl_wb(ctrl_wb_ex_mem),
    .o_ctrl_mem(ctrl_mem_ex_mem),
    .o_pc_branch(branch_dir),
    .o_alu_result(result_alu_ex_mem),
    .o_dato2(dato2_ex_mem)
);


tl_memory
#(
    .LEN(LEN),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)

)
    u_tl_memory
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_address(result_alu_ex_mem),
    .i_write_data(dato2_ex_mem),
    .i_ctrl_wb(ctrl_wb_ex_mem),
    .i_ctrl_mem(ctrl_mem_ex_mem),
    .i_alu_zero(alu_zero),
    .i_write_reg(write_reg_ex_mem),
    .o_address(result_alu_mem_wb),  
    .o_read_data(read_data_memory),
    .o_write_reg(write_reg_mem_wb),
    .o_ctrl_wb(ctrl_wb_mem_wb),
    .o_PCSrc(PCSrc)
);


tl_write_back
#(
    .LEN(LEN),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)
  
)
    u_tl_write_back
(
    .i_read_data(read_data_memory),
    .i_result_alu(result_alu_mem_wb),
    .i_ctrl_wb(ctrl_wb_mem_wb),
    .i_write_reg(write_reg_mem_wb),
    .o_write_data(write_data_banco_reg),
    .o_write_reg(write_reg_wb_id),
    .o_RegWrite(regwrite_wb_id)
);

unidad_cortocircuito
#(
    .LEN(LEN),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)
)
u_unidad_corto
(
   .i_rs_id_ex(rs),
   .i_rt_id_ex(rt),
   .i_write_reg_ex_mem(write_reg_ex_mem),
   .i_write_reg_mem_wb(write_reg_wb_id), 
   .i_reg_write_ex_mem(ctrl_wb_ex_mem[1]),
   .i_reg_write_mem_wb(regwrite_wb_id),
   .o_muxA_alu(ctrl_muxA_corto),
   .o_muxB_alu(ctrl_muxB_corto)
);
endmodule
module top_mips
#(
    parameter LEN = 32,
    parameter NB_IF_ID = 96,
    parameter NB_ID_EX = 160,
    parameter NB_EX_MEM = 128,
    parameter NB_MEM_WB = 96,
    parameter CANT_REG = 16,
    parameter CANT_MEM = 8  
)
(
    input i_clk,
    input i_rst,
    input [LEN-1:0] dir_mem_instr,
    input wea_mem_instr,
    input [LEN-1:0] addr_mem_inst,
    output [NB_IF_ID-1:0] o_if_id,
    output [NB_ID_EX-1:0] o_id_ex,
    output [NB_EX_MEM-1:0] o_ex_mem,
    output [NB_MEM_WB-1:0] o_mem_wb
);




localparam CANTIDAD_REGISTROS = `CANTIDAD_REGISTROS;
localparam NB_ADDRESS_REGISTROS = `NB_ADDRESS_REGISTROS;
localparam NB_SIGN_EXTEND = `NB_SIGN_EXTEND;
localparam NB_INSTRUCCION = `NB_INSTRUCCION;
localparam NB_ALU_CONTROL = `NB_ALU_CONTROL;
localparam NB_ALU_OP = `NB_ALU_OP;
localparam INIT_FILE_IM = `INIT_FILE_IM;

localparam NB_CTRL_WB = `NB_CTRL_WB; 
localparam NB_CTRL_MEM = `NB_CTRL_MEM; 
localparam NB_CTRL_EX = `NB_CTRL_EX; 


wire [LEN-1:0] branch_dir;
wire PCSrc;
wire [LEN-1:0] instruccion;
wire [LEN-1:0] out_adder_if_id;
wire [LEN-1:0] contador_programa;
wire flag_halt;


wire [LEN-1:0] write_data_banco_reg;
wire [LEN-1:0] out_adder_id_ex;
wire [NB_ADDRESS_REGISTROS-1:0] rs;
wire [NB_ADDRESS_REGISTROS-1:0] rd;
wire [NB_ADDRESS_REGISTROS-1:0] rt;
wire [NB_ADDRESS_REGISTROS-1:0] shamt;
wire [LEN-1:0] dato1;
wire [LEN-1:0] dato2_if_ex;
wire [LEN-1:0] sign_extend;
wire [NB_CTRL_WB-1:0] ctrl_wb_id_ex;
wire [NB_CTRL_MEM-1:0] ctrl_mem_id_ex;
wire [NB_CTRL_EX-1:0] ctrl_ex_id_ex;
wire flag_stall;
wire [LEN-1:0] dir_jump;
wire flag_jump;


wire [LEN-1:0] dato2_ex_mem;
wire [LEN-1:0] result_alu_ex_mem;
wire alu_zero;
wire [NB_CTRL_WB-1:0] ctrl_wb_ex_mem;
wire [NB_CTRL_MEM-1:0] ctrl_mem_ex_mem;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_ex_mem;


wire [LEN-1:0] result_alu_mem_wb;
wire [LEN-1:0] read_data_memory;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_mem_wb;
wire [NB_CTRL_WB-1:0] ctrl_wb_mem_wb;


wire regwrite_wb_id;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_wb_id;


wire [1:0] ctrl_muxA_corto;
wire [1:0] ctrl_muxB_corto;



assign o_if_id = {
                  contador_programa,
                  instruccion,

                  flag_halt
                  }; 

assign o_id_ex = { 

                   ctrl_wb_id_ex,
                   ctrl_mem_id_ex,
                   ctrl_ex_id_ex,

                   shamt,
                   rs,
                   rt,
                   rd,
                   out_adder_id_ex,
                   dir_jump,
                   sign_extend,
                   dato1,
                   dato2_if_ex,
                   flag_stall,
                   flag_jump
                  };   
                   
assign o_ex_mem = {

                   ctrl_wb_ex_mem,
                   ctrl_mem_ex_mem,
                   write_reg_ex_mem,
                   branch_dir,
                   result_alu_ex_mem,
                   dato2_ex_mem
                   };

assign o_mem_wb = {

                   PCSrc,
                   ctrl_wb_mem_wb,
                   write_reg_mem_wb,
                   result_alu_mem_wb,
                   read_data_memory
                   };


tl_instruction_fetch
#(
    .LEN(LEN),
    .INIT_FILE_IM(INIT_FILE_IM)
)
    u_tl_instruction_fetch
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_branch_dir(branch_dir),
    .i_PCSrc(PCSrc),
    .i_flag_stall(flag_stall),
    .i_flag_jump(flag_jump),
    .i_dir_jump(dir_jump),
    .i_dir_mem_instr(dir_mem_instr),
    .i_wea_mem_instr(wea_mem_instr),
    .i_addr_mem_inst(addr_mem_inst),
    .o_instruccion(instruccion),
    .o_adder(out_adder_if_id),
    .o_contador_programa(contador_programa),
    .o_flag_halt(flag_halt)
);


tl_instruction_decode
#(
    .LEN(LEN),
    .CANTIDAD_REGISTROS(CANTIDAD_REGISTROS),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_SIGN_EXTEND(NB_SIGN_EXTEND),
    .NB_INSTRUCCION(NB_INSTRUCCION),    
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_CTRL_EX(NB_CTRL_EX),
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_ALU_OP(NB_ALU_OP)
)
    u_tl_instruction_decode
(
    .i_clk(i_clk),          
    .i_rst(i_rst),
    .i_instruccion(instruccion),
    .i_write_data(write_data_banco_reg),
    .i_write_reg(write_reg_wb_id),
    .i_adder_pc(out_adder_if_id),
    .i_RegWrite(regwrite_wb_id),
    .i_flush(PCSrc), 
    .o_adder_pc(out_adder_id_ex), 
    .o_rs(rs),
    .o_rd(rd),
    .o_rt(rt),    
    .o_shamt(shamt),   
    .o_dato1(dato1),
    .o_dato2(dato2_if_ex),
    .o_sign_extend(sign_extend),
    .o_ctrl_wb(ctrl_wb_id_ex),
    .o_ctrl_mem(ctrl_mem_id_ex),
    .o_ctrl_ex(ctrl_ex_id_ex),
    .o_flag_stall(flag_stall),
    .o_dir_jump(dir_jump),
    .o_flag_jump(flag_jump)
);


tl_execute
#(
    .LEN(LEN),
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_CTRL_EX(NB_CTRL_EX)
    
)
    u_tl_execute
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_adder_id(out_adder_id_ex),
    .i_dato1(dato1),
    .i_dato2(dato2_if_ex),
    .i_sign_extend(sign_extend),
    .i_ctrl_wb(ctrl_wb_id_ex),
    .i_ctrl_mem(ctrl_mem_id_ex),
    .i_ctrl_ex(ctrl_ex_id_ex),
    .i_rd(rd),
    .i_rt(rt),
    .i_shamt(shamt),
    .i_ctrl_muxA_corto(ctrl_muxA_corto),
    .i_ctrl_muxB_corto(ctrl_muxB_corto),
    .i_rd_mem_corto(result_alu_ex_mem),
    .i_rd_wb_corto(write_data_banco_reg),
    .i_flush(PCSrc),
    .o_alu_zero(alu_zero),
    .o_write_reg(write_reg_ex_mem),
    .o_ctrl_wb(ctrl_wb_ex_mem),
    .o_ctrl_mem(ctrl_mem_ex_mem),
    .o_pc_branch(branch_dir),
    .o_alu_result(result_alu_ex_mem),
    .o_dato2(dato2_ex_mem)
);


tl_memory
#(
    .LEN(LEN),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)

)
    u_tl_memory
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_address(result_alu_ex_mem),
    .i_write_data(dato2_ex_mem),
    .i_ctrl_wb(ctrl_wb_ex_mem),
    .i_ctrl_mem(ctrl_mem_ex_mem),
    .i_alu_zero(alu_zero),
    .i_write_reg(write_reg_ex_mem),
    .o_address(result_alu_mem_wb),  
    .o_read_data(read_data_memory),
    .o_write_reg(write_reg_mem_wb),
    .o_ctrl_wb(ctrl_wb_mem_wb),
    .o_PCSrc(PCSrc)
);


tl_write_back
#(
    .LEN(LEN),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)
  
)
    u_tl_write_back
(
    .i_read_data(read_data_memory),
    .i_result_alu(result_alu_mem_wb),
    .i_ctrl_wb(ctrl_wb_mem_wb),
    .i_write_reg(write_reg_mem_wb),
    .o_write_data(write_data_banco_reg),
    .o_write_reg(write_reg_wb_id),
    .o_RegWrite(regwrite_wb_id)
);

unidad_cortocircuito
#(
    .LEN(LEN),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)
)
u_unidad_corto
(
   .i_rs_id_ex(rs),
   .i_rt_id_ex(rt),
   .i_write_reg_ex_mem(write_reg_ex_mem),
   .i_write_reg_mem_wb(write_reg_wb_id), 
   .i_reg_write_ex_mem(ctrl_wb_ex_mem[1]),
   .i_reg_write_mem_wb(regwrite_wb_id),
   .o_muxA_alu(ctrl_muxA_corto),
   .o_muxB_alu(ctrl_muxB_corto)
);
endmodule