data/full_repos/permissive/167856740/ram/ram_wishbone.v
data/verilator_xmls/cd5ae3af-dbee-4819-8f22-4824c2bf724b.xml
module ram_wishbone #(parameter SIZE=256) (
	input wire CLK_I,
	input wire RST_I,
	input wire STB_I,
	input wire WE_I,
	input wire [31:0] ADR_I,
	input wire [31:0] DAT_I,
	output wire [31:0] DAT_O
	);
	

    reg [7:0] memory [0:SIZE-1];
    integer i;

    initial begin

        $display("Initialising the data memory with zeros");
        for (i=0; i<SIZE; i=i+1) begin
            memory[i]= 8'h00;
        end
    end

	always @ (posedge CLK_I) begin
	    if(RST_I == 1'b1) begin
	        for (i=0; i<SIZE; i=i+1) begin
                memory[i]<= 8'h00;
            end
	    end
        else if(STB_I == 1'b1) begin
            if (WE_I == 1'b1) begin
                {memory[ADR_I+3],memory[ADR_I+2],memory[ADR_I+1],memory[ADR_I]} <= DAT_I;
                $display("The value %h was stored in memory", DAT_I);
            end
        end
    end  
    

    assign DAT_O = {memory[ADR_I+3],memory[ADR_I+2],memory[ADR_I+1],memory[ADR_I]};
    
endmodule
module ram_wishbone #(parameter SIZE=256) (
	input wire CLK_I,
	input wire RST_I,
	input wire STB_I,
	input wire WE_I,
	input wire [31:0] ADR_I,
	input wire [31:0] DAT_I,
	output wire [31:0] DAT_O
	);

	

    reg [7:0] memory [0:SIZE-1];
    integer i;

    initial begin

        $display("Initialising the data memory with zeros");
        for (i=0; i<SIZE; i=i+1) begin
            memory[i]= 8'h00;
        end
    end

	always @ (posedge CLK_I) begin
	    if(RST_I == 1'b1) begin
	        for (i=0; i<SIZE; i=i+1) begin
                memory[i]<= 8'h00;
            end
	    end
        else if(STB_I == 1'b1) begin
            if (WE_I == 1'b1) begin
                {memory[ADR_I+3],memory[ADR_I+2],memory[ADR_I+1],memory[ADR_I]} <= DAT_I;
                $display("The value %h was stored in memory", DAT_I);
            end
        end
    end  
    

    assign DAT_O = {memory[ADR_I+3],memory[ADR_I+2],memory[ADR_I+1],memory[ADR_I]};
    
endmodule