data/full_repos/permissive/217697217/problems/05_hex_counter/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/217697217/problems/05_hex_counter/testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/217697217/problems/05_hex_counter/testbench.v:20: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/217697217/problems/05_hex_counter/testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #100000 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
reg clk = 1'b0;

always begin
    #1 clk = ~clk;
end
top top(clk, DS_EN1, DS_EN2, DS_EN3, DS_EN4, DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G);

initial begin
    $dumpvars;
    #100000 $finish;
end

endmodule
module testbench();

reg clk = 1'b0;

always begin
    #1 clk = ~clk;
end
top top(clk, DS_EN1, DS_EN2, DS_EN3, DS_EN4, DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G);

initial begin
    $dumpvars;
    #100000 $finish;
end

endmodule