data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Division/flot_Divide_pipe.v
1: b'%Error: Cannot find file containing module: Project/SourceCode/Division,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Division,data/full_repos/permissive/119107706\n             Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Division/flot_Divide_pipe.v\n%Error: Exiting due to 3 error(s)\n'
module flot_Divide_pipe_Ito_unfold
			#(parameter 		  
			
			
									  WIDTH = 64,
									  WIDTH_exp = 11,
									  WIDTH_mat = 52,
									  LUT_addWidth = 6,
									  LUT_bits = 28
			
			


									  )

			( input 				  CLK,
									  nRST,
			  input [WIDTH-1:0] OP1,
			  input [WIDTH-1:0] OP2,
			  input 				  CE,								
			  input 				  exce_in,
			  output reg	 	  exce_out,
			  output reg [WIDTH-1:0] result
			 ); 
			 
wire exce_out_rec, exce_out_mul;
wire [WIDTH-1:0] result_rec, result_mul;
wire [WIDTH-1:0] OP1_delay;
reg nRST_delay;



	flot_Rec_pipe_Ito_unfold
	  #(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
		)
	Fang_flo_Rec_Ito_unfold
		(
		.CLK(CLK), 
		.nRST(nRST), 
		.OP(OP2), 
		.CE(CE),
		.exce_in(exce_in),
		.result(result_rec),
		.exce_out(exce_out_rec)
		);




	flot_mul_pipe 
	#(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat)
		)
	Fang_floMul_PIP (
		.CLK(CLK), 
		.nRST(nRST_delay), 
		.OP1(OP1_delay), 
		.OP2(result_rec), 
		.exce_in(exce_out_rec), 
		.exce_out(exce_out_mul),
		.result(result_mul)
	);

	localparam PIP = 9;
	reg [WIDTH-1:0] buffer_OP1 [1: PIP];
	integer i;
	
	always @(posedge CLK) begin
		if (!nRST) begin
			for (i=1; i<=PIP; i=i+1)
				buffer_OP1[i] <= 0;
		end else begin
			buffer_OP1[1] <= OP1;
			for (i=2; i<=PIP; i=i+1)
				buffer_OP1[i] <= buffer_OP1[i-1];
		end
	end

	assign OP1_delay = buffer_OP1[PIP];



always @(posedge CLK) begin
	if(!nRST) begin
		result <= result_mul;
		exce_out <= 0;
		nRST_delay <= 0;
	end
	else begin
		result <= result_mul;
		exce_out <= exce_out_mul;
		nRST_delay <= 1;
	end
end


endmodule
module flot_Divide_pipe_Ito_unfold
			#(parameter 		  
			
			
									  WIDTH = 64,
									  WIDTH_exp = 11,
									  WIDTH_mat = 52,
									  LUT_addWidth = 6,
									  LUT_bits = 28
			
			


									  )

			( input 				  CLK,
									  nRST,
			  input [WIDTH-1:0] OP1,
			  input [WIDTH-1:0] OP2,
			  input 				  CE,								
			  input 				  exce_in,
			  output reg	 	  exce_out,
			  output reg [WIDTH-1:0] result
			 );
 
			 
wire exce_out_rec, exce_out_mul;
wire [WIDTH-1:0] result_rec, result_mul;
wire [WIDTH-1:0] OP1_delay;
reg nRST_delay;



	flot_Rec_pipe_Ito_unfold
	  #(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
		)
	Fang_flo_Rec_Ito_unfold
		(
		.CLK(CLK), 
		.nRST(nRST), 
		.OP(OP2), 
		.CE(CE),
		.exce_in(exce_in),
		.result(result_rec),
		.exce_out(exce_out_rec)
		);




	flot_mul_pipe 
	#(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat)
		)
	Fang_floMul_PIP (
		.CLK(CLK), 
		.nRST(nRST_delay), 
		.OP1(OP1_delay), 
		.OP2(result_rec), 
		.exce_in(exce_out_rec), 
		.exce_out(exce_out_mul),
		.result(result_mul)
	);

	localparam PIP = 9;
	reg [WIDTH-1:0] buffer_OP1 [1: PIP];
	integer i;
	
	always @(posedge CLK) begin
		if (!nRST) begin
			for (i=1; i<=PIP; i=i+1)
				buffer_OP1[i] <= 0;
		end else begin
			buffer_OP1[1] <= OP1;
			for (i=2; i<=PIP; i=i+1)
				buffer_OP1[i] <= buffer_OP1[i-1];
		end
	end

	assign OP1_delay = buffer_OP1[PIP];



always @(posedge CLK) begin
	if(!nRST) begin
		result <= result_mul;
		exce_out <= 0;
		nRST_delay <= 0;
	end
	else begin
		result <= result_mul;
		exce_out <= exce_out_mul;
		nRST_delay <= 1;
	end
end


endmodule