data/full_repos/permissive/162672365/Mux.v
data/verilator_xmls/e3c1508f-1b12-4134-a21a-afcd103f3c3b.xml
module mux3to1(out, select, in1, in2, in3);
	input in1, in2, in3;
	input [1:0] select;
	output out;
	wire w;
	
	mux2to1 m1(w, select[0], in1, in2);
	mux2to1 m2(out, select[1], w, in3);
	
endmodule
module mux3to1(out, select, in1, in2, in3);

	input in1, in2, in3;
	input [1:0] select;
	output out;
	wire w;
	
	mux2to1 m1(w, select[0], in1, in2);
	mux2to1 m2(out, select[1], w, in3);
	
endmodule