data/full_repos/permissive/208556773/src/sim/pwm_pll.v
data/verilator_xmls/300a5a67-c80b-4197-b722-0c97bb46df98.xml
module pwm_pll(
	input  wire clock_in,
	output wire clock_out,
	output wire locked
	);

  assign clock_out = clock_in;

endmodule
module pwm_pll(
	input  wire clock_in,
	output wire clock_out,
	output wire locked
	);


  assign clock_out = clock_in;

endmodule