data/full_repos/permissive/158077025/adder.v
data/verilator_xmls/cfd20284-718e-43e8-8df0-e25038c04494.xml
module adder(
	clk,
	layer_reset,
	stage_finish,
	adder_en,
	addend,
	sum
	);

parameter AUGEND_BIT_WIDTH = 22+2;
parameter INI_AUGEND       = 24'h000000; 
parameter ADDEND_BIT_WIDTH = 16+4;

input                             clk;
input                             layer_reset;
input                             stage_finish;
input                             adder_en;
input      [ADDEND_BIT_WIDTH-1:0] addend;
output reg [AUGEND_BIT_WIDTH-1:0] sum;

always @(posedge clk or posedge layer_reset) begin
	if (layer_reset) begin
		sum <= INI_AUGEND;
	end
	else if (stage_finish) begin
		sum <= {{4{addend[ADDEND_BIT_WIDTH-1]}}, addend};
	end
	else if (adder_en) begin
		sum <= sum + {{4{addend[ADDEND_BIT_WIDTH-1]}}, addend};
	end









end

endmodule
module adder(
	clk,
	layer_reset,
	stage_finish,
	adder_en,
	addend,
	sum
	);


parameter AUGEND_BIT_WIDTH = 22+2;
parameter INI_AUGEND       = 24'h000000; 
parameter ADDEND_BIT_WIDTH = 16+4;

input                             clk;
input                             layer_reset;
input                             stage_finish;
input                             adder_en;
input      [ADDEND_BIT_WIDTH-1:0] addend;
output reg [AUGEND_BIT_WIDTH-1:0] sum;

always @(posedge clk or posedge layer_reset) begin
	if (layer_reset) begin
		sum <= INI_AUGEND;
	end
	else if (stage_finish) begin
		sum <= {{4{addend[ADDEND_BIT_WIDTH-1]}}, addend};
	end
	else if (adder_en) begin
		sum <= sum + {{4{addend[ADDEND_BIT_WIDTH-1]}}, addend};
	end









end

endmodule