data/full_repos/permissive/139225418/rtl/axis_s.v
1: b'%Warning-WIDTH: data/full_repos/permissive/139225418/rtl/axis_s.v:44: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance axis_s\n  data <= 1\'b0;\n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module axis_s (
			  input areset_n, aclk, 
			  output reg [31:0] data, 
			  input ready,
			  
			  output reg tready, 
              input  tvalid,
			  input tlast, 
			  input [31:0] tdata,
			 
			  output reg finish
			);


wire handshake;	
assign handshake = tvalid & tready;
			

always @ (posedge aclk)
	if ( ~areset_n)
		tready <= 1'b0;
	else
		if (ready && ~tready)
			tready <= 1'b1;
		else
			if (handshake)
				tready <= 1'b0;
			else
				if ( tready && ~ready && ~tvalid )
					tready <= 1'b1;
				else
					tready <= tready;


always @ (posedge aclk)
	if ( ~areset_n)
		data <= 1'b0;
	else if (handshake)
			data <= tdata;
		else
			data <= data;
			
			
always @ (posedge aclk)
	if ( ~areset_n)
		finish <= 0;
	else if (handshake)
			finish <= 1'b1;
		else
			if (finish == 1 && ready )
				finish <= 0;
			else
				finish <= finish;		

endmodule
module axis_s (
			  input areset_n, aclk, 
			  output reg [31:0] data, 
			  input ready,
			  
			  output reg tready, 
              input  tvalid,
			  input tlast, 
			  input [31:0] tdata,
			 
			  output reg finish
			);



wire handshake;	
assign handshake = tvalid & tready;
			

always @ (posedge aclk)
	if ( ~areset_n)
		tready <= 1'b0;
	else
		if (ready && ~tready)
			tready <= 1'b1;
		else
			if (handshake)
				tready <= 1'b0;
			else
				if ( tready && ~ready && ~tvalid )
					tready <= 1'b1;
				else
					tready <= tready;


always @ (posedge aclk)
	if ( ~areset_n)
		data <= 1'b0;
	else if (handshake)
			data <= tdata;
		else
			data <= data;
			
			
always @ (posedge aclk)
	if ( ~areset_n)
		finish <= 0;
	else if (handshake)
			finish <= 1'b1;
		else
			if (finish == 1 && ready )
				finish <= 0;
			else
				finish <= finish;		

endmodule