data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v
1: b'%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:7: Cannot find include file: TLBDefines.vh\n`include "TLBDefines.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/v/CPU,data/full_repos/permissive/127311496/TLBDefines.vh\n             data/full_repos/permissive/127311496/src/v/CPU,data/full_repos/permissive/127311496/TLBDefines.vh.v\n             data/full_repos/permissive/127311496/src/v/CPU,data/full_repos/permissive/127311496/TLBDefines.vh.sv\n             TLBDefines.vh\n             TLBDefines.vh.v\n             TLBDefines.vh.sv\n             obj_dir/TLBDefines.vh\n             obj_dir/TLBDefines.vh.v\n             obj_dir/TLBDefines.vh.sv\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:22: Define or directive not defined: \'`PageMask\'\n wire [16:0] evenOddBitMask = {headerData[`PageMask], 1\'b1} & {1\'b1, ~headerData[`PageMask]};\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [16:0] evenOddBitMask = {headerData[`PageMask], 1\'b1} & {1\'b1, ~headerData[`PageMask]};\n                                                   ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:22: Define or directive not defined: \'`PageMask\'\n wire [16:0] evenOddBitMask = {headerData[`PageMask], 1\'b1} & {1\'b1, ~headerData[`PageMask]};\n                                                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:25: Define or directive not defined: \'`G\'\n wire ASIDMatch = (headerData[`G] | (headerData[`ASID] == ASID));\n                              ^~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire ASIDMatch = (headerData[`G] | (headerData[`ASID] == ASID));\n                                ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:25: Define or directive not defined: \'`ASID\'\n wire ASIDMatch = (headerData[`G] | (headerData[`ASID] == ASID));\n                                                ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:26: Define or directive not defined: \'`VPN2\'\n assign matchI = (((headerData[`VPN2] ^ vAddrI[31:13]) & {3\'b111, ~headerData[`PageMask]}) == 19\'h0) & ASIDMatch;\n                               ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:26: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign matchI = (((headerData[`VPN2] ^ vAddrI[31:13]) & {3\'b111, ~headerData[`PageMask]}) == 19\'h0) & ASIDMatch;\n                                    ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:26: Define or directive not defined: \'`PageMask\'\n assign matchI = (((headerData[`VPN2] ^ vAddrI[31:13]) & {3\'b111, ~headerData[`PageMask]}) == 19\'h0) & ASIDMatch;\n                                                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:27: Define or directive not defined: \'`VPN2\'\n assign matchD = (((headerData[`VPN2] ^ vAddrD[31:13]) & {3\'b111, ~headerData[`PageMask]}) == 19\'h0) & ASIDMatch;\n                               ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign matchD = (((headerData[`VPN2] ^ vAddrD[31:13]) & {3\'b111, ~headerData[`PageMask]}) == 19\'h0) & ASIDMatch;\n                                    ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:27: Define or directive not defined: \'`PageMask\'\n assign matchD = (((headerData[`VPN2] ^ vAddrD[31:13]) & {3\'b111, ~headerData[`PageMask]}) == 19\'h0) & ASIDMatch;\n                                                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:28: Define or directive not defined: \'`VPN2\'\n assign probeMatch = (((headerData[`VPN2] ^ VPN2) & {3\'b111, ~headerData[`PageMask]}) == 19\'h0) & ASIDMatch;\n                                   ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign probeMatch = (((headerData[`VPN2] ^ VPN2) & {3\'b111, ~headerData[`PageMask]}) == 19\'h0) & ASIDMatch;\n                                        ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLBHeader.v:28: Define or directive not defined: \'`PageMask\'\n assign probeMatch = (((headerData[`VPN2] ^ VPN2) & {3\'b111, ~headerData[`PageMask]}) == 19\'h0) & ASIDMatch;\n                                                                         ^~~~~~~~~\n%Error: Exiting due to 16 error(s)\n'
module TLBHeader(input clk, input we,
	input [31:0] vAddrI, output matchI, output oddI,
	input [31:0] vAddrD, output matchD, output oddD,
	input [7:0] ASID, input [18:0] VPN2, output probeMatch,
	
	input G, input [15:0] pageMask
);
	reg [44:0] headerData = 0;
	
	always @ (posedge clk)
	if(we)
		headerData <= {pageMask, VPN2, G, ASID};
	
	wire [16:0] evenOddBitMask = {headerData[`PageMask], 1'b1} & {1'b1, ~headerData[`PageMask]};
	assign oddI = |(vAddrI[28:12] & evenOddBitMask) & matchI;
	assign oddD = |(vAddrD[28:12] & evenOddBitMask) & matchD;
	wire ASIDMatch = (headerData[`G] | (headerData[`ASID] == ASID));
	assign matchI = (((headerData[`VPN2] ^ vAddrI[31:13]) & {3'b111, ~headerData[`PageMask]}) == 19'h0) & ASIDMatch;
	assign matchD = (((headerData[`VPN2] ^ vAddrD[31:13]) & {3'b111, ~headerData[`PageMask]}) == 19'h0) & ASIDMatch;
	assign probeMatch = (((headerData[`VPN2] ^ VPN2) & {3'b111, ~headerData[`PageMask]}) == 19'h0) & ASIDMatch;

endmodule
module TLBHeader(input clk, input we,
	input [31:0] vAddrI, output matchI, output oddI,
	input [31:0] vAddrD, output matchD, output oddD,
	input [7:0] ASID, input [18:0] VPN2, output probeMatch,
	
	input G, input [15:0] pageMask
);

	reg [44:0] headerData = 0;
	
	always @ (posedge clk)
	if(we)
		headerData <= {pageMask, VPN2, G, ASID};
	
	wire [16:0] evenOddBitMask = {headerData[`PageMask], 1'b1} & {1'b1, ~headerData[`PageMask]};
	assign oddI = |(vAddrI[28:12] & evenOddBitMask) & matchI;
	assign oddD = |(vAddrD[28:12] & evenOddBitMask) & matchD;
	wire ASIDMatch = (headerData[`G] | (headerData[`ASID] == ASID));
	assign matchI = (((headerData[`VPN2] ^ vAddrI[31:13]) & {3'b111, ~headerData[`PageMask]}) == 19'h0) & ASIDMatch;
	assign matchD = (((headerData[`VPN2] ^ vAddrD[31:13]) & {3'b111, ~headerData[`PageMask]}) == 19'h0) & ASIDMatch;
	assign probeMatch = (((headerData[`VPN2] ^ VPN2) & {3'b111, ~headerData[`PageMask]}) == 19'h0) & ASIDMatch;

endmodule