data/full_repos/permissive/188795755/elec_design/beta2/sim/tb_pwm.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/188795755/elec_design/beta2/sim/tb_pwm.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/188795755/elec_design/beta2/sim/tb_pwm.v:22: Unsupported: Ignoring delay on this delayed statement.\nalways  #10     sclk    =       ~sclk;\n        ^\n%Error: data/full_repos/permissive/188795755/elec_design/beta2/sim/tb_pwm.v:24: Cannot find file containing module: \'pwm\'\npwm     pwm_inst(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/188795755/elec_design/beta2/sim,data/full_repos/permissive/188795755/pwm\n             data/full_repos/permissive/188795755/elec_design/beta2/sim,data/full_repos/permissive/188795755/pwm.v\n             data/full_repos/permissive/188795755/elec_design/beta2/sim,data/full_repos/permissive/188795755/pwm.sv\n             pwm\n             pwm.v\n             pwm.sv\n             obj_dir/pwm\n             obj_dir/pwm.v\n             obj_dir/pwm.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module  tb_pwm();

reg                     sclk                    ;
reg                     s_rst_n                 ;
reg                     direct                  ;
reg                     enable                  ;

wire    [ 1:0]          MA                      ; 

initial begin
        sclk    =       1'b1;
        s_rst_n <=      1'b0;
        direct  <=      1'b1;
        enable  <=      1'b0;
        #100
        s_rst_n <=      1'b1;
        enable  <=      1'b1;
end

always  #10     sclk    =       ~sclk;

pwm     pwm_inst(
        .sclk                   (sclk                   ),
        .s_rst_n                (s_rst_n                ),
        .enable                 (enable                 ),
        .direct                 (direct                 ),
        .MA                     (MA                     )
); 

endmodule
module  tb_pwm();


reg                     sclk                    ;
reg                     s_rst_n                 ;
reg                     direct                  ;
reg                     enable                  ;

wire    [ 1:0]          MA                      ; 

initial begin
        sclk    =       1'b1;
        s_rst_n <=      1'b0;
        direct  <=      1'b1;
        enable  <=      1'b0;
        #100
        s_rst_n <=      1'b1;
        enable  <=      1'b1;
end

always  #10     sclk    =       ~sclk;

pwm     pwm_inst(
        .sclk                   (sclk                   ),
        .s_rst_n                (s_rst_n                ),
        .enable                 (enable                 ),
        .direct                 (direct                 ),
        .MA                     (MA                     )
); 

endmodule