data/full_repos/permissive/19016904/rtl/control_unit.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/19016904/rtl/control_unit.v:10: Unsupported: Ignoring delay on this delayed statement.\n        forever #1 sysclk = ~sysclk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/19016904/rtl/control_unit.v:14: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("control_unit.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/19016904/rtl/control_unit.v:15: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_unit();
    parameter ADDR_SIZE = 12;
    parameter WORD_SIZE = 16;

    reg sysclk;
    initial begin
        sysclk <= 1'b1;
        forever #1 sysclk = ~sysclk;
    end
    
    initial begin
        $dumpfile("control_unit.vcd");
        $dumpvars;
    end




    reg [WORD_SIZE-1:0] acc;
    reg [ADDR_SIZE-1:0] ip;
    reg [WORD_SIZE-1:0] ir;
    reg [ADDR_SIZE-1:0] sp;


    reg [ADDR_SIZE-1:0] mem_addr;
    reg [WORD_SIZE-1:0] mem_in;
    wire [WORD_SIZE-1:0] mem_out;
    wire [WORD_SIZE-1:0] rom_out;
    reg mem_write;

    ram ram_blk(
        .clk(sysclk),
        .addr(mem_addr),
        .data_in(mem_in),
        .write_en(mem_write),
        .data_out(mem_out),
        .rom_addr(ip),
        .rom_out(rom_out)
    );
    
    initial begin
        ir <= 16'h4000;
        ip <= 0;
        sp <= 12'd191;
        mem_addr <= 0;
        mem_in <= 0;
        mem_write <= 0;
        acc <= 0;
    end
    

    reg state = 1;
    

    wire pop_op;
    assign pop_op = (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4'h9)
                    | (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4'hb);
    
    
    always @(posedge sysclk) begin
        
        state <= ~state;
        
        if (state) begin
            case (ir[WORD_SIZE-1:WORD_SIZE-4])
                4'h0: begin
                        acc <= mem_out;
                    end
                4'h1: begin
                        mem_in <= acc;
                        mem_addr <= ir[WORD_SIZE-5:0];
                        mem_write <= 1;
                    end
                4'h2: begin
                        acc <= acc + mem_out;
                    end
                4'h3: begin
                        acc <= acc - mem_out;
                    end
                4'h4: begin
                        ip <= ir[WORD_SIZE-5:0];
                    end
                4'h5: begin
                        if (acc[WORD_SIZE-1] == 1'b0)
                            ip <= ir[WORD_SIZE-5:0];
                    end
                4'h6: begin
                        if (acc != 8'd0)
                            ip <= ir[WORD_SIZE-5:0];
                    end
                4'h7: begin
                        $finish; 
                    end
                4'h8: begin
                        mem_addr <= sp;
                        mem_in <= acc;
                        mem_write <= 1;
                        sp <= sp + 12'b1;
                    end
                4'h9: begin
                        acc <= mem_out;
                        sp <= sp - 12'b1;
                    end
                4'ha: begin
                        ip <= mem_addr ;
                        mem_addr <= sp;
                        mem_in <= ip;
                        mem_write <= 1;
                        sp <= sp + 12'b1;
                    end
                4'hb: begin
                        ip <= mem_out;
                        sp <= sp - 12'b1;
                    end
                default: $finish;
            endcase
        end
        
        else begin
            ir <= rom_out;
            ip <= ip + 1; 
            mem_write <= 0;
            

            if (pop_op)
                mem_addr <= (sp - 12'b1);
            else
                mem_addr <= rom_out[WORD_SIZE-5:0];
        end
    end
endmodule
module control_unit();

    parameter ADDR_SIZE = 12;
    parameter WORD_SIZE = 16;

    reg sysclk;
    initial begin
        sysclk <= 1'b1;
        forever #1 sysclk = ~sysclk;
    end
    
    initial begin
        $dumpfile("control_unit.vcd");
        $dumpvars;
    end




    reg [WORD_SIZE-1:0] acc;
    reg [ADDR_SIZE-1:0] ip;
    reg [WORD_SIZE-1:0] ir;
    reg [ADDR_SIZE-1:0] sp;


    reg [ADDR_SIZE-1:0] mem_addr;
    reg [WORD_SIZE-1:0] mem_in;
    wire [WORD_SIZE-1:0] mem_out;
    wire [WORD_SIZE-1:0] rom_out;
    reg mem_write;

    ram ram_blk(
        .clk(sysclk),
        .addr(mem_addr),
        .data_in(mem_in),
        .write_en(mem_write),
        .data_out(mem_out),
        .rom_addr(ip),
        .rom_out(rom_out)
    );
    
    initial begin
        ir <= 16'h4000;
        ip <= 0;
        sp <= 12'd191;
        mem_addr <= 0;
        mem_in <= 0;
        mem_write <= 0;
        acc <= 0;
    end
    

    reg state = 1;
    

    wire pop_op;
    assign pop_op = (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4'h9)
                    | (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4'hb);
    
    
    always @(posedge sysclk) begin
        
        state <= ~state;
        
        if (state) begin
            case (ir[WORD_SIZE-1:WORD_SIZE-4])
                4'h0: begin
                        acc <= mem_out;
                    end
                4'h1: begin
                        mem_in <= acc;
                        mem_addr <= ir[WORD_SIZE-5:0];
                        mem_write <= 1;
                    end
                4'h2: begin
                        acc <= acc + mem_out;
                    end
                4'h3: begin
                        acc <= acc - mem_out;
                    end
                4'h4: begin
                        ip <= ir[WORD_SIZE-5:0];
                    end
                4'h5: begin
                        if (acc[WORD_SIZE-1] == 1'b0)
                            ip <= ir[WORD_SIZE-5:0];
                    end
                4'h6: begin
                        if (acc != 8'd0)
                            ip <= ir[WORD_SIZE-5:0];
                    end
                4'h7: begin
                        $finish; 
                    end
                4'h8: begin
                        mem_addr <= sp;
                        mem_in <= acc;
                        mem_write <= 1;
                        sp <= sp + 12'b1;
                    end
                4'h9: begin
                        acc <= mem_out;
                        sp <= sp - 12'b1;
                    end
                4'ha: begin
                        ip <= mem_addr ;
                        mem_addr <= sp;
                        mem_in <= ip;
                        mem_write <= 1;
                        sp <= sp + 12'b1;
                    end
                4'hb: begin
                        ip <= mem_out;
                        sp <= sp - 12'b1;
                    end
                default: $finish;
            endcase
        end
        
        else begin
            ir <= rom_out;
            ip <= ip + 1; 
            mem_write <= 0;
            

            if (pop_op)
                mem_addr <= (sp - 12'b1);
            else
                mem_addr <= rom_out[WORD_SIZE-5:0];
        end
    end
endmodule