data/full_repos/permissive/165663914/firmware/audio_i2s.v
data/verilator_xmls/4ef2b57c-045d-44c8-b7eb-794c6c29a384.xml
module audio_I2S 
	( 
		input [31:0]data_in,
		input empty,
		input BCLK,
		input LRCLK,
		output get_data,
		output reg data_out	
	);
	
	
reg [4:0] state;
reg [4:0] data_count;
reg shift = 0;

always @ (posedge BCLK)
begin 
	if(!empty)
	begin
		case (state)

		0:	begin
				if (LRCLK) state <= 1;
			end 
			
		1:  begin 
				if (!LRCLK) begin
					shift <= 1;
					data_count <= 5'd31;
					state <= 2;
				end
			end
			
		2: begin
				if (data_count == 16) begin 
					shift <= 0;
					if(LRCLK) begin 
						data_count <= 15;
						shift <= 1;
						state <= 3;
					end 			
				end 
				else begin
					data_count <= data_count - 5'd1;
				end
			end
			
		3:	begin 
				if (data_count == 0) begin
					shift <= 0;
					state <= 0;
				end
				else data_count <= data_count - 5'd1;
			end 
			
		default: state <= 0;
		endcase
	end 
end 



reg [5:0] get_count;		
always @ (negedge BCLK)
begin 
		if (shift) data_out <= data_in[data_count];
		else data_out <= 0;
		if (!LRCLK) get_count <= 0;
		else get_count <= get_count + 6'd1;
end 
			
assign get_data = (get_count == 6'd30);
			
			
endmodule
module audio_I2S 
	( 
		input [31:0]data_in,
		input empty,
		input BCLK,
		input LRCLK,
		output get_data,
		output reg data_out	
	);

	
	
reg [4:0] state;
reg [4:0] data_count;
reg shift = 0;

always @ (posedge BCLK)
begin 
	if(!empty)
	begin
		case (state)

		0:	begin
				if (LRCLK) state <= 1;
			end 
			
		1:  begin 
				if (!LRCLK) begin
					shift <= 1;
					data_count <= 5'd31;
					state <= 2;
				end
			end
			
		2: begin
				if (data_count == 16) begin 
					shift <= 0;
					if(LRCLK) begin 
						data_count <= 15;
						shift <= 1;
						state <= 3;
					end 			
				end 
				else begin
					data_count <= data_count - 5'd1;
				end
			end
			
		3:	begin 
				if (data_count == 0) begin
					shift <= 0;
					state <= 0;
				end
				else data_count <= data_count - 5'd1;
			end 
			
		default: state <= 0;
		endcase
	end 
end 



reg [5:0] get_count;		
always @ (negedge BCLK)
begin 
		if (shift) data_out <= data_in[data_count];
		else data_out <= 0;
		if (!LRCLK) get_count <= 0;
		else get_count <= get_count + 6'd1;
end 
			
assign get_data = (get_count == 6'd30);
			
			
endmodule