data/full_repos/permissive/173670949/ws2812/tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/173670949/ws2812/tb.v:7: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk <= !clk;  \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/173670949/ws2812/tb.v:10: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/173670949/ws2812/tb.v:11: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, top);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/173670949/ws2812/tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #1_000_000;  \n        ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
    reg clk = 0;

    always #10 clk <= !clk;

    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, top);





        #1_000_000;
        $finish;
    end

    wire ws2812_dat;
    wire ws2812_done;
    wire ws2812_reset;
    Top #(.F_CLK(50_000_000)) top(clk, ws2812_dat, ws2812_done, ws2812_reset);

endmodule
module tb();

    reg clk = 0;

    always #10 clk <= !clk;

    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, top);





        #1_000_000;
        $finish;
    end

    wire ws2812_dat;
    wire ws2812_done;
    wire ws2812_reset;
    Top #(.F_CLK(50_000_000)) top(clk, ws2812_dat, ws2812_done, ws2812_reset);

endmodule