data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:107: Operator AND expects 4 bits on the LHS, but LHS\'s VARREF \'wb_cyc_i\' generates 1 bits.\n                                                                                                  : ... In instance minsoc_onchip_ram_top\nassign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; \n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:107: Operator AND expects 4 bits on the RHS, but RHS\'s VARREF \'wb_stb_i\' generates 1 bits.\n                                                                                                  : ... In instance minsoc_onchip_ram_top\nassign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; \n                        ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:193: Cannot find file containing module: \'minsoc_onchip_ram\'\n        minsoc_onchip_ram block_ram_0 ( \n        ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/minsoc_onchip_ram\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/minsoc_onchip_ram.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/minsoc_onchip_ram.sv\n             minsoc_onchip_ram\n             minsoc_onchip_ram.v\n             minsoc_onchip_ram.sv\n             obj_dir/minsoc_onchip_ram\n             obj_dir/minsoc_onchip_ram.v\n             obj_dir/minsoc_onchip_ram.sv\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:205: Cannot find file containing module: \'minsoc_onchip_ram\'\n        minsoc_onchip_ram block_ram_1 ( \n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:216: Cannot find file containing module: \'minsoc_onchip_ram\'\n        minsoc_onchip_ram block_ram_2 ( \n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:227: Cannot find file containing module: \'minsoc_onchip_ram\'\n        minsoc_onchip_ram block_ram_3 ( \n        ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module minsoc_onchip_ram_top ( 
  wb_clk_i, wb_rst_i, 
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, 
  wb_stb_i, wb_ack_o, wb_err_o 
); 
 



parameter    adr_width = 13;
localparam    aw_int = 11;
localparam    blocks = (1<<(adr_width-aw_int));




input      wb_clk_i; 
input      wb_rst_i; 
 



input  [31:0]   wb_dat_i; 
output [31:0]   wb_dat_o; 
input  [31:0]   wb_adr_i; 
input  [3:0]    wb_sel_i; 
input      wb_we_i; 
input      wb_cyc_i; 
input      wb_stb_i; 
output     wb_ack_o; 
output     wb_err_o; 
 



wire    we; 
wire [3:0]  be_i; 
wire [31:0]  wb_dat_o; 
reg    ack_we; 
reg    ack_re; 



assign wb_ack_o = ack_re | ack_we; 
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]);
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); 
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; 
 



always @ (negedge wb_clk_i or posedge wb_rst_i) 
begin 
if (wb_rst_i) 
    ack_we <= 1'b0; 
  else 
  if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) 
    ack_we <= #1 1'b1; 
  else 
    ack_we <= #1 1'b0; 
end 
 



always @ (posedge wb_clk_i or posedge wb_rst_i) 
begin 
  if (wb_rst_i) 
    ack_re <= 1'b0; 
  else 
  if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) 
    ack_re <= #1 1'b1; 
  else 
    ack_re <= #1 1'b0; 
end 


localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;

wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];

generate
genvar j, k;
	for (j=0; j<slices; j=j+1) begin : SLICES
		for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
			if (j==0) begin
				mux2 #
                (
                    .dw(32)
                ) 
                mux_int(
                    .sel( wb_adr_i[aw_int+2+j] ), 
                    .in1( int_dat_o[k*2] ),
				    .in2( int_dat_o[k*2+1] ), 
                    .out( mux_out[k] )
                );
			end
			else begin
				mux2 #
                (
                    .dw(32)
                ) 
                mux_int(
                    .sel( wb_adr_i[aw_int+2+j] ), 
				    .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), 
				    .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), 
				    .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
                );
			end
		end
	end
endgenerate


assign wb_dat_o = mux_out[mux_out_nr-1];





wire [blocks-1:0] bank;
 
generate 
genvar i;
    for (i=0; i < blocks; i=i+1) begin : MEM

        assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;


        minsoc_onchip_ram block_ram_0 ( 
            .clk(wb_clk_i), 
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]), 
            .di(wb_dat_i[7:0]), 
            .doq(int_dat_o[i][7:0]), 
            .we(we & bank[i]), 
            .oe(1'b1),
            .ce(be_i[0])
        ); 


        minsoc_onchip_ram block_ram_1 ( 
            .clk(wb_clk_i), 
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]), 
            .di(wb_dat_i[15:8]), 
            .doq(int_dat_o[i][15:8]), 
            .we(we & bank[i]), 
            .oe(1'b1),
            .ce(be_i[1])
        ); 

        minsoc_onchip_ram block_ram_2 ( 
            .clk(wb_clk_i), 
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]), 
            .di(wb_dat_i[23:16]), 
            .doq(int_dat_o[i][23:16]), 
            .we(we & bank[i]), 
            .oe(1'b1),
            .ce(be_i[2])
        ); 

        minsoc_onchip_ram block_ram_3 ( 
            .clk(wb_clk_i), 
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]), 
            .di(wb_dat_i[31:24]), 
            .doq(int_dat_o[i][31:24]), 
            .we(we & bank[i]), 
            .oe(1'b1),
            .ce(be_i[3])
        ); 

    end
endgenerate

endmodule
module minsoc_onchip_ram_top ( 
  wb_clk_i, wb_rst_i, 
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, 
  wb_stb_i, wb_ack_o, wb_err_o 
);
 
 



parameter    adr_width = 13;
localparam    aw_int = 11;
localparam    blocks = (1<<(adr_width-aw_int));




input      wb_clk_i; 
input      wb_rst_i; 
 



input  [31:0]   wb_dat_i; 
output [31:0]   wb_dat_o; 
input  [31:0]   wb_adr_i; 
input  [3:0]    wb_sel_i; 
input      wb_we_i; 
input      wb_cyc_i; 
input      wb_stb_i; 
output     wb_ack_o; 
output     wb_err_o; 
 



wire    we; 
wire [3:0]  be_i; 
wire [31:0]  wb_dat_o; 
reg    ack_we; 
reg    ack_re; 



assign wb_ack_o = ack_re | ack_we; 
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]);
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); 
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; 
 



always @ (negedge wb_clk_i or posedge wb_rst_i) 
begin 
if (wb_rst_i) 
    ack_we <= 1'b0; 
  else 
  if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) 
    ack_we <= #1 1'b1; 
  else 
    ack_we <= #1 1'b0; 
end 
 



always @ (posedge wb_clk_i or posedge wb_rst_i) 
begin 
  if (wb_rst_i) 
    ack_re <= 1'b0; 
  else 
  if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) 
    ack_re <= #1 1'b1; 
  else 
    ack_re <= #1 1'b0; 
end 


localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;

wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];

generate
genvar j, k;
	for (j=0; j<slices; j=j+1) begin : SLICES
		for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
			if (j==0) begin
				mux2 #
                (
                    .dw(32)
                ) 
                mux_int(
                    .sel( wb_adr_i[aw_int+2+j] ), 
                    .in1( int_dat_o[k*2] ),
				    .in2( int_dat_o[k*2+1] ), 
                    .out( mux_out[k] )
                );
			end
			else begin
				mux2 #
                (
                    .dw(32)
                ) 
                mux_int(
                    .sel( wb_adr_i[aw_int+2+j] ), 
				    .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), 
				    .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), 
				    .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
                );
			end
		end
	end
endgenerate


assign wb_dat_o = mux_out[mux_out_nr-1];





wire [blocks-1:0] bank;
 
generate 
genvar i;
    for (i=0; i < blocks; i=i+1) begin : MEM

        assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;


        minsoc_onchip_ram block_ram_0 ( 
            .clk(wb_clk_i), 
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]), 
            .di(wb_dat_i[7:0]), 
            .doq(int_dat_o[i][7:0]), 
            .we(we & bank[i]), 
            .oe(1'b1),
            .ce(be_i[0])
        ); 


        minsoc_onchip_ram block_ram_1 ( 
            .clk(wb_clk_i), 
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]), 
            .di(wb_dat_i[15:8]), 
            .doq(int_dat_o[i][15:8]), 
            .we(we & bank[i]), 
            .oe(1'b1),
            .ce(be_i[1])
        ); 

        minsoc_onchip_ram block_ram_2 ( 
            .clk(wb_clk_i), 
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]), 
            .di(wb_dat_i[23:16]), 
            .doq(int_dat_o[i][23:16]), 
            .we(we & bank[i]), 
            .oe(1'b1),
            .ce(be_i[2])
        ); 

        minsoc_onchip_ram block_ram_3 ( 
            .clk(wb_clk_i), 
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]), 
            .di(wb_dat_i[31:24]), 
            .doq(int_dat_o[i][31:24]), 
            .we(we & bank[i]), 
            .oe(1'b1),
            .ce(be_i[3])
        ); 

    end
endgenerate

endmodule