data/full_repos/permissive/129127690/sign_ext_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/129127690/sign_ext_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129127690/sign_ext_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129127690/sign_ext_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/129127690/sign_ext_tb.v:12: Cannot find file containing module: \'sign_ext\'\n sign_ext #(.bus_size(bus_size), .bus_size_in(bus_size_in)) uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/sign_ext\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/sign_ext.v\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/sign_ext.sv\n             sign_ext\n             sign_ext.v\n             sign_ext.sv\n             obj_dir/sign_ext\n             obj_dir/sign_ext.v\n             obj_dir/sign_ext.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sign_ext_tb #(parameter bus_size = 8, bus_size_in = 4);


	reg [bus_size_in-1:0] datoin;


	wire [bus_size-1:0] datoout;


	sign_ext #(.bus_size(bus_size), .bus_size_in(bus_size_in)) uut (
		.in(datoin), 
		.out(datoout)
	);

	initial begin

		datoin = 4'b1001;
		#10
		datoin = 4'b1101;
		#10
		datoin = 4'b0101;
		#10;
	end
      
endmodule
module sign_ext_tb #(parameter bus_size = 8, bus_size_in = 4);



	reg [bus_size_in-1:0] datoin;


	wire [bus_size-1:0] datoout;


	sign_ext #(.bus_size(bus_size), .bus_size_in(bus_size_in)) uut (
		.in(datoin), 
		.out(datoout)
	);

	initial begin

		datoin = 4'b1001;
		#10
		datoin = 4'b1101;
		#10
		datoin = 4'b0101;
		#10;
	end
      
endmodule