data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv
 line:28: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:34: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2.0);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:36: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2.0);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:67: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:72: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:75: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 0.5);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:78: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:91: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:103: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:106: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:119: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:130: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:133: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:146: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:157: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:160: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:173: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:184: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:187: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:200: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:211: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:214: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:227: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:238: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:242: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:256: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:268: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:273: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 5);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:286: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_slave.sv:40: Cannot find file containing module: \'AHB_slave\'\n AHB_slave DUT(\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/AHB_slave\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/AHB_slave.v\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/AHB_slave.sv\n             AHB_slave\n             AHB_slave.v\n             AHB_slave.sv\n             obj_dir/AHB_slave\n             obj_dir/AHB_slave.v\n             obj_dir/AHB_slave.sv\n%Error: Exiting due to 1 error(s), 28 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_AHB_slave();


	localparam CLK_PERIOD 	= 35;
	localparam CLK_DELAY 	= 30;
	localparam RESET_VALUE  = 0;


	reg tb_HRESETn,tb_HCLK,tb_HWRITE, tb_process_complete,tb_start, tb_HRESP, tb_HREADY;
	reg [31:0]tb_HADDR,tb_HWDATA,tb_RC4_key, tb_HRDATA;
	reg [1:0] tb_HSIZE;
	reg [11:0]tb_image_width, tb_image_height;
	reg [19:0] tb_image_startAddr;
	reg tb_error;



	integer tb_test_num;
	string tb_test_case;


	always
	begin
		tb_HCLK = 1'b0;
		#(CLK_PERIOD/2.0);
		tb_HCLK = 1'b1;
		#(CLK_PERIOD/2.0);
	end
	

	AHB_slave DUT(
		.clk(tb_HCLK),
		.n_rst(tb_HRESETn),
		.HADDR(tb_HADDR),
		.HSIZE(tb_HSIZE),
		.HWDATA(tb_HWDATA),
		.HWRITE(tb_HWRITE),
		.process_complete(tb_process_complete),
		.error(tb_error),
		.RC4_key(tb_RC4_key),
		.image_width(tb_image_width),
		.image_height(tb_image_height),
		.image_startAddr(tb_image_startAddr),
		.start(tb_start),
		.HRESP(tb_HRESP),
		.HREADY(tb_HREADY),
		.HRDATA(tb_HRDATA)
	);
	

	initial 
	begin
		

		tb_HRESETn	= 1'b1;
		tb_test_num = 0;
		tb_test_case = "Test bench initializaton";
		#(0.1);


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Reset everything";
		#(0.1);
		tb_HRESETn	= 1'b0;

		#(CLK_PERIOD * 0.5);


		#(CLK_PERIOD);
		if((tb_RC4_key == RESET_VALUE) && (tb_image_width == RESET_VALUE) && (tb_image_height == RESET_VALUE) && (tb_image_startAddr == RESET_VALUE))
		begin
			$info("Reset done in %s test case", tb_test_case);
		end
		else
		begin
			$error("Reset not done in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Img start addr to mm-regs";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0001;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;
		tb_error = 0;

		#(CLK_PERIOD * 1);
		

		#(CLK_PERIOD);
		if(tb_HWDATA[19:0] == tb_image_startAddr)
		begin
			$info("Correct value stored for image start address in %s test case", tb_test_case);
		end
		else
		begin
			$error("Incorrect value stored for image start address in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "RC4 key to mm-regs";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0010;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;

		#(CLK_PERIOD * 1);
		

		#(CLK_PERIOD);
		if(tb_RC4_key == '1)
		begin
			$info("Correct value stored for RC4 key in %s test case", tb_test_case);
		end
		else
		begin
			$error("Incorrect value stored for RC4 key in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Img width to mm-regs";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0100;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;

		#(CLK_PERIOD * 1);
		

		#(CLK_PERIOD);
		if(tb_image_width == '1)
		begin
			$info("Correct value stored for image width in %s test case", tb_test_case);
		end
		else
		begin
			$error("Incorrect value stored for image width in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Img height to mm-regs";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b1000;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;

		#(CLK_PERIOD * 1);
		

		#(CLK_PERIOD);
		if(tb_image_height == '1)
		begin
			$info("Correct value stored for image height in %s test case", tb_test_case);
		end
		else
		begin
			$error("Incorrect value stored for image height in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Start signal to MCU";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0001;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;

		#(CLK_PERIOD * 1);
		

		#(CLK_PERIOD);
		if(tb_start == 1)
		begin
			$info("Correct value stored for start in %s test case", tb_test_case);
		end
		else
		begin
			$error("Incorrect value stored for start in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "HRESP signal check";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;	
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0001;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;

		#(CLK_PERIOD * 1);



		#(CLK_PERIOD);
		if(tb_start == 1)
		begin
			$info("AHB slave sets HRESP to 1 correctly in %s test case", tb_test_case);
		end
		else
		begin
			$error("AHB slave not setting HRESP correctly in %s test case", tb_test_case);
		end



		tb_test_num = tb_test_num + 1;
		tb_test_case = "Process complete received from MCU";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1011;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0001;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;
		tb_error = 1;

		#(CLK_PERIOD * 1);
		
		tb_process_complete = 0;
		tb_error = 0;

		#(CLK_PERIOD * 5);
		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b1111;
		tb_HWRITE 		= 1'b0;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;
		



		#(CLK_PERIOD);
		if(tb_start == 0)
		begin
			$info("AHB slave goes back to idle state and start signal is reset correctly in %s test case", tb_test_case);
		end
		else
		begin
			$error("AHB slave not going back to idle state in %s test case", tb_test_case);
		end

	end
	
endmodule
module tb_AHB_slave();



	localparam CLK_PERIOD 	= 35;
	localparam CLK_DELAY 	= 30;
	localparam RESET_VALUE  = 0;


	reg tb_HRESETn,tb_HCLK,tb_HWRITE, tb_process_complete,tb_start, tb_HRESP, tb_HREADY;
	reg [31:0]tb_HADDR,tb_HWDATA,tb_RC4_key, tb_HRDATA;
	reg [1:0] tb_HSIZE;
	reg [11:0]tb_image_width, tb_image_height;
	reg [19:0] tb_image_startAddr;
	reg tb_error;



	integer tb_test_num;
	string tb_test_case;


	always
	begin
		tb_HCLK = 1'b0;
		#(CLK_PERIOD/2.0);
		tb_HCLK = 1'b1;
		#(CLK_PERIOD/2.0);
	end
	

	AHB_slave DUT(
		.clk(tb_HCLK),
		.n_rst(tb_HRESETn),
		.HADDR(tb_HADDR),
		.HSIZE(tb_HSIZE),
		.HWDATA(tb_HWDATA),
		.HWRITE(tb_HWRITE),
		.process_complete(tb_process_complete),
		.error(tb_error),
		.RC4_key(tb_RC4_key),
		.image_width(tb_image_width),
		.image_height(tb_image_height),
		.image_startAddr(tb_image_startAddr),
		.start(tb_start),
		.HRESP(tb_HRESP),
		.HREADY(tb_HREADY),
		.HRDATA(tb_HRDATA)
	);
	

	initial 
	begin
		

		tb_HRESETn	= 1'b1;
		tb_test_num = 0;
		tb_test_case = "Test bench initializaton";
		#(0.1);


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Reset everything";
		#(0.1);
		tb_HRESETn	= 1'b0;

		#(CLK_PERIOD * 0.5);


		#(CLK_PERIOD);
		if((tb_RC4_key == RESET_VALUE) && (tb_image_width == RESET_VALUE) && (tb_image_height == RESET_VALUE) && (tb_image_startAddr == RESET_VALUE))
		begin
			$info("Reset done in %s test case", tb_test_case);
		end
		else
		begin
			$error("Reset not done in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Img start addr to mm-regs";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0001;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;
		tb_error = 0;

		#(CLK_PERIOD * 1);
		

		#(CLK_PERIOD);
		if(tb_HWDATA[19:0] == tb_image_startAddr)
		begin
			$info("Correct value stored for image start address in %s test case", tb_test_case);
		end
		else
		begin
			$error("Incorrect value stored for image start address in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "RC4 key to mm-regs";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0010;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;

		#(CLK_PERIOD * 1);
		

		#(CLK_PERIOD);
		if(tb_RC4_key == '1)
		begin
			$info("Correct value stored for RC4 key in %s test case", tb_test_case);
		end
		else
		begin
			$error("Incorrect value stored for RC4 key in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Img width to mm-regs";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0100;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;

		#(CLK_PERIOD * 1);
		

		#(CLK_PERIOD);
		if(tb_image_width == '1)
		begin
			$info("Correct value stored for image width in %s test case", tb_test_case);
		end
		else
		begin
			$error("Incorrect value stored for image width in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Img height to mm-regs";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b1000;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;

		#(CLK_PERIOD * 1);
		

		#(CLK_PERIOD);
		if(tb_image_height == '1)
		begin
			$info("Correct value stored for image height in %s test case", tb_test_case);
		end
		else
		begin
			$error("Incorrect value stored for image height in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Start signal to MCU";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0001;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;

		#(CLK_PERIOD * 1);
		

		#(CLK_PERIOD);
		if(tb_start == 1)
		begin
			$info("Correct value stored for start in %s test case", tb_test_case);
		end
		else
		begin
			$error("Incorrect value stored for start in %s test case", tb_test_case);
		end


		tb_test_num = tb_test_num + 1;
		tb_test_case = "HRESP signal check";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;	
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0001;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;

		#(CLK_PERIOD * 1);



		#(CLK_PERIOD);
		if(tb_start == 1)
		begin
			$info("AHB slave sets HRESP to 1 correctly in %s test case", tb_test_case);
		end
		else
		begin
			$error("AHB slave not setting HRESP correctly in %s test case", tb_test_case);
		end



		tb_test_num = tb_test_num + 1;
		tb_test_case = "Process complete received from MCU";
		#(0.1);

		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1011;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b0001;
		tb_HWRITE 		= 1'b1;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;
		tb_error = 1;

		#(CLK_PERIOD * 1);
		
		tb_process_complete = 0;
		tb_error = 0;

		#(CLK_PERIOD * 5);
		tb_HRESETn		= 1'b1;
		tb_HWDATA 		= '1;
		tb_HADDR[31:28] 	= 4'b1010;
		tb_HADDR[27:4] 		= '0;
		tb_HADDR[3:0] 		= 4'b1111;
		tb_HWRITE 		= 1'b0;
		tb_HSIZE 		= 2'b10;
		tb_process_complete 	= 1'b0;
		



		#(CLK_PERIOD);
		if(tb_start == 0)
		begin
			$info("AHB slave goes back to idle state and start signal is reset correctly in %s test case", tb_test_case);
		end
		else
		begin
			$error("AHB slave not going back to idle state in %s test case", tb_test_case);
		end

	end
	
endmodule