data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v
 line:115: before: "$"
1: b'%Error: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:2: Cannot find include file: RCA_16bit.v\n`include "RCA_16bit.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/198139336/DDLab6_2019,data/full_repos/permissive/198139336/RCA_16bit.v\n             data/full_repos/permissive/198139336/DDLab6_2019,data/full_repos/permissive/198139336/RCA_16bit.v.v\n             data/full_repos/permissive/198139336/DDLab6_2019,data/full_repos/permissive/198139336/RCA_16bit.v.sv\n             RCA_16bit.v\n             RCA_16bit.v.v\n             RCA_16bit.v.sv\n             obj_dir/RCA_16bit.v\n             obj_dir/RCA_16bit.v.v\n             obj_dir/RCA_16bit.v.sv\n%Error: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:31: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("lab6_16bit.fsdb");  \n ^~~~~~~~~\n%Error: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:32: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:35: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:37: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:38: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:39: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:40: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:41: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:42: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:43: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:44: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:45: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:46: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:47: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:48: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:49: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:50: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:51: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:52: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:53: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:54: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:55: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:56: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:57: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:58: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:59: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:60: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:61: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:62: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:63: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:64: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:65: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:66: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:67: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:68: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:69: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:70: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:71: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:72: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:73: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:74: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:76: Unsupported: Ignoring delay on this delayed statement.\n #500    $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab6_2019/testbench_16bit.v:81: Unsupported: Ignoring delay on this delayed statement.\n always #10 CLK = ~CLK;\n        ^\n%Error: Exiting due to 3 error(s), 42 warning(s)\n'
module testbench;

	reg  [15:0] in_a, in_b;
	reg CLK;
	reg reset;

	reg  [15:0] correct_ans;
	wire  [15:0] s;
	reg [5:0] counter;
	reg [5:0] ct;
	reg error;
	reg cin;	
	reg [4:0]successful_count;
	wire cout;

	initial cin = 0;
	initial ct = 0;
	initial in_a = 0;
	initial in_b = 0;
	initial successful_count = 0;

	cla_16bit DDLab6(in_a, in_b, cin, s);
	

	

	initial begin

	$dumpfile("lab6_16bit.fsdb");  
	$dumpvars;
	CLK = 1'b0;
	#10 reset = 1;
	#20 reset = 0;
	
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;	
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	
	#500    $finish;
	
	end
	

	always #10 CLK = ~CLK;

	always @(posedge CLK or posedge reset)
	begin
		if(reset)
		begin
			counter <= 0;
			in_a <= {$random};
			in_b <= {$random} % 32767;
			cin <= {$random} % 2;
			correct_ans <= 0;
			error <= 0;
			ct <= ct + 1'b1;
		end
		else
		begin
			correct_ans <= in_a + in_b +cin ;
			counter <= counter + 1;
			if(counter == 4)

				if(s == correct_ans)
				begin
					successful_count = successful_count+1;
					$display ("Test %d ", ct);
					$display ("//////////////////");
					$display ("// Successful %d//",successful_count);
					$display ("//////////////////");
					$display ("%d + %d + %d= ?", in_a, in_b , cin);
					$display ("sum = %d\n", s);
					$display ();
				end
				else
begin
					$display ();
					$display ("Test %d ", ct);
					$display ("//////////");
					$display ("// Fail //");
					$display ("//////////");
					$display ("%d + %d + %d= ?", in_a, in_b , cin);
					$display ("your  s=%d", s);
					$display ("correct:");
					$display ("sum =%d", correct_ans[15:0]);
					$display ();
				end
		end


	end


endmodule
module testbench;


	reg  [15:0] in_a, in_b;
	reg CLK;
	reg reset;

	reg  [15:0] correct_ans;
	wire  [15:0] s;
	reg [5:0] counter;
	reg [5:0] ct;
	reg error;
	reg cin;	
	reg [4:0]successful_count;
	wire cout;

	initial cin = 0;
	initial ct = 0;
	initial in_a = 0;
	initial in_b = 0;
	initial successful_count = 0;

	cla_16bit DDLab6(in_a, in_b, cin, s);
	

	

	initial begin

	$dumpfile("lab6_16bit.fsdb");  
	$dumpvars;
	CLK = 1'b0;
	#10 reset = 1;
	#20 reset = 0;
	
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;	
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	#500 reset = 1;
	#20 reset = 0;
	
	#500    $finish;
	
	end
	

	always #10 CLK = ~CLK;

	always @(posedge CLK or posedge reset)
	begin
		if(reset)
		begin
			counter <= 0;
			in_a <= {$random};
			in_b <= {$random} % 32767;
			cin <= {$random} % 2;
			correct_ans <= 0;
			error <= 0;
			ct <= ct + 1'b1;
		end
		else
		begin
			correct_ans <= in_a + in_b +cin ;
			counter <= counter + 1;
			if(counter == 4)

				if(s == correct_ans)
				begin
					successful_count = successful_count+1;
					$display ("Test %d ", ct);
					$display ("//////////////////");
					$display ("// Successful %d//",successful_count);
					$display ("//////////////////");
					$display ("%d + %d + %d= ?", in_a, in_b , cin);
					$display ("sum = %d\n", s);
					$display ();
				end
				else
begin
					$display ();
					$display ("Test %d ", ct);
					$display ("//////////");
					$display ("// Fail //");
					$display ("//////////");
					$display ("%d + %d + %d= ?", in_a, in_b , cin);
					$display ("your  s=%d", s);
					$display ("correct:");
					$display ("sum =%d", correct_ans[15:0]);
					$display ();
				end
		end


	end


endmodule