data/full_repos/permissive/181665138/verilog/capitolo_iii/D_Latch_Reg.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/181665138/verilog/capitolo_iii/D_Latch_Reg.v:23: syntax error, unexpected ==, expecting \')\' or \',\' or or\n    always @(reset_ == 0) #1 D_LATCH <= 0;\n                    ^~\n%Warning-STMTDLY: data/full_repos/permissive/181665138/verilog/capitolo_iii/D_Latch_Reg.v:25: Unsupported: Ignoring delay on this delayed statement.\n    always @(c or d) if (reset_ == 1) #2 D_LATCH <= (c == 1) ? d:D_LATCH;\n                                      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module D_Latch_Reg(d, c, q, reset_);
    input reset_;
    input d;
    input c;
    output q;

    reg D_LATCH;

    assign q = D_LATCH;

    always @(reset_ == 0) #1 D_LATCH <= 0;

    always @(c or d) if (reset_ == 1) #2 D_LATCH <= (c == 1) ? d:D_LATCH;
endmodule
module D_Latch_Reg(d, c, q, reset_);

    input reset_;
    input d;
    input c;
    output q;

    reg D_LATCH;

    assign q = D_LATCH;

    always @(reset_ == 0) #1 D_LATCH <= 0;

    always @(c or d) if (reset_ == 1) #2 D_LATCH <= (c == 1) ? d:D_LATCH;
endmodule