data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator/testbench.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator/testbench.sv:22: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator/testbench.sv:22: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator/testbench.sv:12: Cannot find file containing module: \'PPgen_wordslice\'\n PPgen_wordslice dut(Double,Negate,Single,Y,Sign3,Sign2,Sign1,Sign0,PP0,PP1,PP2,PP3);\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator,data/full_repos/permissive/13847835/PPgen_wordslice\n             data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator,data/full_repos/permissive/13847835/PPgen_wordslice.v\n             data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator,data/full_repos/permissive/13847835/PPgen_wordslice.sv\n             PPgen_wordslice\n             PPgen_wordslice.v\n             PPgen_wordslice.sv\n             obj_dir/PPgen_wordslice\n             obj_dir/PPgen_wordslice.v\n             obj_dir/PPgen_wordslice.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
	logic clk;
	logic [3:0] Double, Negate, Single;
	logic [7:0] Y;
	logic Sign3, Sign2, Sign1, Sign0;
	logic [8:0] PP0, PP1, PP2, PP3;
    logic [19:0] vectors[1048576:0], currentvec;
    logic [20:0] vectornum, errors;
	integer out;
    

	PPgen_wordslice dut(Double,Negate,Single,Y,Sign3,Sign2,Sign1,Sign0,PP0,PP1,PP2,PP3);
    

	initial begin
		$readmemb("input.txt", vectors);
		out = $fopen("output.txt","w");
		vectornum = 0; errors = 0;
	end

    always begin
       clk = 1; #10; clk = 0; #10;
    end
      

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
	   Double = currentvec[19:16];
	   Negate = currentvec[15:12];
	   Single = currentvec[11:8];
	   Y = currentvec[7:0];
       if (vectornum === 1048576) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
                  $fclose(out);
         $stop;
       end
    end
    

    always @(negedge clk) begin
       $fwrite(out, "%b%b%b%b%b%b%b%b%b\n", 
      currentvec,
		Sign3,PP3,
		Sign2,PP2,
		Sign1,PP1,
		Sign0,PP0);
       vectornum = vectornum + 1;
    end
endmodule
module testbench();

	logic clk;
	logic [3:0] Double, Negate, Single;
	logic [7:0] Y;
	logic Sign3, Sign2, Sign1, Sign0;
	logic [8:0] PP0, PP1, PP2, PP3;
    logic [19:0] vectors[1048576:0], currentvec;
    logic [20:0] vectornum, errors;
	integer out;
    

	PPgen_wordslice dut(Double,Negate,Single,Y,Sign3,Sign2,Sign1,Sign0,PP0,PP1,PP2,PP3);
    

	initial begin
		$readmemb("input.txt", vectors);
		out = $fopen("output.txt","w");
		vectornum = 0; errors = 0;
	end

    always begin
       clk = 1; #10; clk = 0; #10;
    end
      

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
	   Double = currentvec[19:16];
	   Negate = currentvec[15:12];
	   Single = currentvec[11:8];
	   Y = currentvec[7:0];
       if (vectornum === 1048576) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
                  $fclose(out);
         $stop;
       end
    end
    

    always @(negedge clk) begin
       $fwrite(out, "%b%b%b%b%b%b%b%b%b\n", 
      currentvec,
		Sign3,PP3,
		Sign2,PP2,
		Sign1,PP1,
		Sign0,PP0);
       vectornum = vectornum + 1;
    end
endmodule