data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/SyncFIFOLevel.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/SyncFIFOLevel.v:401: Unsupported: Ignoring delay on this delayed statement.\n        #0\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/SyncFIFOLevel.v:155: Cannot find file containing module: \'SyncHandshake\'\n   SyncHandshake #(.delayreturn(1))\n   ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl,data/full_repos/permissive/135350124/SyncHandshake\n             data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl,data/full_repos/permissive/135350124/SyncHandshake.v\n             data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl,data/full_repos/permissive/135350124/SyncHandshake.sv\n             SyncHandshake\n             SyncHandshake.v\n             SyncHandshake.sv\n             obj_dir/SyncHandshake\n             obj_dir/SyncHandshake.v\n             obj_dir/SyncHandshake.sv\n%Error: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/SyncFIFOLevel.v:163: Cannot find file containing module: \'SyncHandshake\'\n   SyncHandshake #(.delayreturn(1))\n   ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/SyncFIFOLevel.v:358: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                                   : ... In instance SyncFIFOLevel\n             fifoMem[i] = {((dataWidth + 1)/2){2\'b10}} ;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/SyncFIFOLevel.v:360: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                                   : ... In instance SyncFIFOLevel\n        dDoutReg = {((dataWidth + 1)/2){2\'b10}} ;\n                 ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function [indxWidth:0] grayToBinary ;
      input [indxWidth:0] grayin;
      begin: grayToBinary_block
         reg  [indxWidth:0] binary ;
         integer i ;
         for ( i = 0 ; i <= indxWidth ; i = i+1 )
           begin
              binary[i] = ^( grayin >> i ) ;
           end
         grayToBinary = binary ;
      end
   endfunction
function [indxWidth:0] grayToBinary ;

      input [indxWidth:0] grayin;
      begin: grayToBinary_block
         reg  [indxWidth:0] binary ;
         integer i ;
         for ( i = 0 ; i <= indxWidth ; i = i+1 )
           begin
              binary[i] = ^( grayin >> i ) ;
           end
         grayToBinary = binary ;
      end
   endfunction