data/full_repos/permissive/211316121/lab6_2/sources_1/new/digitalClock.v
1: b'%Warning-WIDTH: data/full_repos/permissive/211316121/lab6_2/sources_1/new/digitalClock.v:109: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hf\' generates 8 bits.\n                                                                                            : ... In instance digitalClock.seg\n        an = 8\'b1111;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/211316121/lab6_2/sources_1/new/digitalClock.v:110: Bit extraction of var[7:0] requires 3 bit index, not 2 bits.\n                                                                                            : ... In instance digitalClock.seg\n        an[clkcount] = aen[clkcount];\n                          ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2/sources_1/new/digitalClock.v:30: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                 : ... In instance digitalClock\n    wire [3:0] H1_load={\'b0,SW[13:11]};\n                        ^~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2/sources_1/new/digitalClock.v:30: Unsized numbers/parameters not allowed in replications.\n                                                                                                 : ... In instance digitalClock\n    wire [3:0] H1_load={\'b0,SW[13:11]};\n                           ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2/sources_1/new/digitalClock.v:32: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                 : ... In instance digitalClock\n    wire [3:0] M1_load={\'b0,SW[6:4]};\n                        ^~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2/sources_1/new/digitalClock.v:32: Unsized numbers/parameters not allowed in replications.\n                                                                                                 : ... In instance digitalClock\n    wire [3:0] M1_load={\'b0,SW[6:4]};\n                           ^\n%Error: Exiting due to 6 warning(s)\n'
module digitalClock(
    input CLK100MHZ,
    input [15:0] SW,
    output CA,
    output CB,
    output CC,
    output CD,
    output CE,
    output CF,
    output CG,
    output [3:0] AN,
    output DP
    );
    assign DP=1;
    
    wire [6:0] SEG;
    assign SEG = { CG, CF, CE, CD, CC, CB, CA };
    
    wire [1:0] CP_seg;
    clkdiv div(CLK100MHZ,CP_seg[0],CP_seg[1]);
    
    wire CP_clock;
    oneMinute min(CLK100MHZ,CP_clock);
    
    wire CR=SW[15];
    wire LD=SW[14];
    
    wire [3:0] H1_load={'b0,SW[13:11]};
    wire [3:0] H2_load=SW[10:7];
    wire [3:0] M1_load={'b0,SW[6:4]};
    wire [3:0] M2_load=SW[3:0];
    
    wire [3:0] H1_display;
    wire [3:0] H2_display;
    wire [3:0] M1_display;
    wire [3:0] M2_display;
    wire [15:0] display={H1_display,H2_display,M1_display,M2_display};
    
    wire Full_H1=H1_display[1]&H2_display[1]&H2_display[0]&Full_M1;
    wire Full_H2=(H2_display[3]&H2_display[0]&Full_M1)|Full_H1;
    wire Full_M1=M1_display[2]&M1_display[0]&M2_display[3]&M2_display[0];
    wire Full_M2=M2_display[3]&M2_display[0];
    
    _74LS163 H1(CP_clock,~(CR|Full_H1),~LD,Full_H2,1,H1_load,H1_display);
    _74LS163 H2(CP_clock,~(CR|Full_H2),~LD,Full_M1,1,H2_load,H2_display);
    _74LS163 M1(CP_clock,~(CR|Full_M1),~LD,Full_M2,1,M1_load,M1_display);
    _74LS163 M2(CP_clock,~(CR|Full_M2),~LD,1,1,M2_load,M2_display);
    
    BCD_7Seg seg(display,CP_seg,SEG,AN);
    
endmodule
module digitalClock(
    input CLK100MHZ,
    input [15:0] SW,
    output CA,
    output CB,
    output CC,
    output CD,
    output CE,
    output CF,
    output CG,
    output [3:0] AN,
    output DP
    );

    assign DP=1;
    
    wire [6:0] SEG;
    assign SEG = { CG, CF, CE, CD, CC, CB, CA };
    
    wire [1:0] CP_seg;
    clkdiv div(CLK100MHZ,CP_seg[0],CP_seg[1]);
    
    wire CP_clock;
    oneMinute min(CLK100MHZ,CP_clock);
    
    wire CR=SW[15];
    wire LD=SW[14];
    
    wire [3:0] H1_load={'b0,SW[13:11]};
    wire [3:0] H2_load=SW[10:7];
    wire [3:0] M1_load={'b0,SW[6:4]};
    wire [3:0] M2_load=SW[3:0];
    
    wire [3:0] H1_display;
    wire [3:0] H2_display;
    wire [3:0] M1_display;
    wire [3:0] M2_display;
    wire [15:0] display={H1_display,H2_display,M1_display,M2_display};
    
    wire Full_H1=H1_display[1]&H2_display[1]&H2_display[0]&Full_M1;
    wire Full_H2=(H2_display[3]&H2_display[0]&Full_M1)|Full_H1;
    wire Full_M1=M1_display[2]&M1_display[0]&M2_display[3]&M2_display[0];
    wire Full_M2=M2_display[3]&M2_display[0];
    
    _74LS163 H1(CP_clock,~(CR|Full_H1),~LD,Full_H2,1,H1_load,H1_display);
    _74LS163 H2(CP_clock,~(CR|Full_H2),~LD,Full_M1,1,H2_load,H2_display);
    _74LS163 M1(CP_clock,~(CR|Full_M1),~LD,Full_M2,1,M1_load,M1_display);
    _74LS163 M2(CP_clock,~(CR|Full_M2),~LD,1,1,M2_load,M2_display);
    
    BCD_7Seg seg(display,CP_seg,SEG,AN);
    
endmodule