data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v
 line:43: before: "tton_right_button_conditioner_in"
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:43: Cannot find include file: tartcfg.v\n`include "tartcfg.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:51: Define or directive not defined: \'`ACCUM_BITS\'\n  #( parameter ACCUM = `ACCUM_BITS,\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:51: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  #( parameter ACCUM = `ACCUM_BITS,\n                                  ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:53: syntax error, unexpected parameter, expecting IDENTIFIER\n     parameter MRATE = 12,        \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:54: syntax error, unexpected parameter, expecting IDENTIFIER\n     parameter MBITS = 4,\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:55: syntax error, unexpected parameter, expecting IDENTIFIER\n     parameter MSIZE = (2<<MBITS)-1,\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:56: syntax error, unexpected parameter, expecting IDENTIFIER\n     parameter DELAY = 3)\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:56: syntax error, unexpected \')\', expecting \';\'\n     parameter DELAY = 3)\n                        ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:73: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input              enable,   \n    ^~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:95: syntax error, unexpected always\n   always @(posedge clk_x)\n   ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:146: syntax error, unexpected assign\n   assign ack_o = bus_state[0];\n   ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/ones_count.v:182: syntax error, unexpected always\n   always @(posedge clk_x) begin\n   ^~~~~~\n%Error: Exiting due to 12 error(s)\n'
module ones_count
  #( parameter ACCUM = `ACCUM_BITS,
     parameter MSB   = ACCUM-1,
     parameter MRATE = 12,
     parameter MBITS = 4,
     parameter MSIZE = (2<<MBITS)-1,
     parameter DELAY = 3)
   (
    input              clk_x,
    input              rst,


    input              clk_i,
    input              cyc_i,
    input              stb_i,
    input              we_i,
    input              bst_i,
    output             ack_o,
    input [4:0]        adr_i,
    input [MSB:0]      dat_i,
    output reg [MSB:0] dat_o,


    input              enable,
    input              switch,
    input [23:0]       antenna
    );






   reg [MSB:0]         counts0[0:MSIZE];
   reg [MSB:0]         counts1[0:MSIZE];

   reg [MSB:0]         dcnt0, dcnt1, qcnt0, qcnt1;
   reg                 bank = 0, swap = 0, clear = 0;
   reg [3:0]           x_rd_adr = 0;
   reg [4:0]           x_wt_adr = 0, x_wr_adr = 0;
   wire                wrap_x_rd_adr = x_rd_adr == 11;
   wire [4:0]          next_x_rd_adr = wrap_x_rd_adr ? 0 : x_rd_adr + 1 ;



   always @(posedge clk_x)
     if (rst) begin
        x_rd_adr <= #DELAY 0;
        x_wt_adr <= #DELAY 0;
        x_wr_adr <= #DELAY 0;
     end
     else begin
        x_rd_adr <= #DELAY enable ? next_x_rd_adr : x_rd_adr;
        x_wt_adr <= #DELAY active ? {bank, x_rd_adr} : x_wt_adr;
        x_wr_adr <= #DELAY valid  ? x_wt_adr : x_wr_adr;
     end


   always @(posedge clk_x)
     if (rst) begin : RAM_RESET_LOGIC
        swap  <= #DELAY 0;
        bank  <= #DELAY 0;
        clear <= #DELAY 1;
     end
     else if (wrap_x_rd_adr && (switch || swap)) begin
        swap  <= #DELAY 0;
        bank  <= #DELAY ~bank;
        clear <= #DELAY 1;
     end
     else if (switch && !swap) begin
        swap  <= #DELAY 1;
     end
     else if (enable && wrap_x_rd_adr && clear) begin
        clear <= #DELAY 0;
     end


   always @(posedge clk_x) begin : RAM_READ_WRITE
     if (!rst && enable) begin
        dcnt0 <= #DELAY clear ? 0 : counts0[{bank, x_rd_adr}] ;
        dcnt1 <= #DELAY clear ? 0 : counts1[{bank, x_rd_adr}] ;
     end
     if (!rst && valid) begin
        counts0[x_wr_adr] <= #DELAY qcnt0;
        counts1[x_wr_adr] <= #DELAY qcnt1;
     end
   end





   wire [4:0] adr_w = {bank_n, adr_i[3:0]};
   reg [1:0]  bus_state = `BUS_IDLE;
   reg        bank_n = 1;

   assign ack_o = bus_state[0];

   always @(posedge clk_i)
     if (rst)
       bus_state <= #DELAY `BUS_IDLE;
     else
       case (bus_state)
         `BUS_IDLE:
           bus_state <= #DELAY cyc_i && stb_i ? `BUS_READ : bus_state ;

         `BUS_READ:
           bus_state <= #DELAY bst_i ? bus_state : `BUS_WAIT ;

         `BUS_WAIT:
           bus_state <= #DELAY cyc_i ? (stb_i ? `BUS_READ : bus_state) : `BUS_IDLE ;
       endcase


   always @(posedge clk_i)
     if (rst) bank_n <= #DELAY 1;
     else     bank_n <= #DELAY ~bank;
   

   always @(posedge clk_i)
     if (cyc_i && stb_i)
       dat_o <= #DELAY adr_i[4] ? counts1[adr_w] : counts0[adr_w];





   wire [11:0] ax0 = antenna[11: 0];
   wire [11:0] ax1 = antenna[23:12];
   reg         active = 0, valid = 0, a0, a1;


   always @(posedge clk_x) begin
      a0  <= #DELAY ax0[x_rd_adr];
      a1  <= #DELAY ax1[x_rd_adr];
   end

   always @(posedge clk_x)
     if (rst || !enable) active <= #DELAY 0;
     else if (enable)    active <= #DELAY 1;
     else                active <= #DELAY active;


   always @(posedge clk_x) begin
      qcnt0 <= #DELAY dcnt0 + a0;
      qcnt1 <= #DELAY dcnt1 + a1;
      valid <= #DELAY rst ? 0 : active;
   end


endmodule
module ones_count
  #( parameter ACCUM = `ACCUM_BITS,
     parameter MSB   = ACCUM-1,
     parameter MRATE = 12,
     parameter MBITS = 4,
     parameter MSIZE = (2<<MBITS)-1,
     parameter DELAY = 3)
   (
    input              clk_x,
    input              rst,


    input              clk_i,
    input              cyc_i,
    input              stb_i,
    input              we_i,
    input              bst_i,
    output             ack_o,
    input [4:0]        adr_i,
    input [MSB:0]      dat_i,
    output reg [MSB:0] dat_o,


    input              enable,
    input              switch,
    input [23:0]       antenna
    );







   reg [MSB:0]         counts0[0:MSIZE];
   reg [MSB:0]         counts1[0:MSIZE];

   reg [MSB:0]         dcnt0, dcnt1, qcnt0, qcnt1;
   reg                 bank = 0, swap = 0, clear = 0;
   reg [3:0]           x_rd_adr = 0;
   reg [4:0]           x_wt_adr = 0, x_wr_adr = 0;
   wire                wrap_x_rd_adr = x_rd_adr == 11;
   wire [4:0]          next_x_rd_adr = wrap_x_rd_adr ? 0 : x_rd_adr + 1 ;



   always @(posedge clk_x)
     if (rst) begin
        x_rd_adr <= #DELAY 0;
        x_wt_adr <= #DELAY 0;
        x_wr_adr <= #DELAY 0;
     end
     else begin
        x_rd_adr <= #DELAY enable ? next_x_rd_adr : x_rd_adr;
        x_wt_adr <= #DELAY active ? {bank, x_rd_adr} : x_wt_adr;
        x_wr_adr <= #DELAY valid  ? x_wt_adr : x_wr_adr;
     end


   always @(posedge clk_x)
     if (rst) begin : RAM_RESET_LOGIC
        swap  <= #DELAY 0;
        bank  <= #DELAY 0;
        clear <= #DELAY 1;
     end
     else if (wrap_x_rd_adr && (switch || swap)) begin
        swap  <= #DELAY 0;
        bank  <= #DELAY ~bank;
        clear <= #DELAY 1;
     end
     else if (switch && !swap) begin
        swap  <= #DELAY 1;
     end
     else if (enable && wrap_x_rd_adr && clear) begin
        clear <= #DELAY 0;
     end


   always @(posedge clk_x) begin : RAM_READ_WRITE
     if (!rst && enable) begin
        dcnt0 <= #DELAY clear ? 0 : counts0[{bank, x_rd_adr}] ;
        dcnt1 <= #DELAY clear ? 0 : counts1[{bank, x_rd_adr}] ;
     end
     if (!rst && valid) begin
        counts0[x_wr_adr] <= #DELAY qcnt0;
        counts1[x_wr_adr] <= #DELAY qcnt1;
     end
   end





   wire [4:0] adr_w = {bank_n, adr_i[3:0]};
   reg [1:0]  bus_state = `BUS_IDLE;
   reg        bank_n = 1;

   assign ack_o = bus_state[0];

   always @(posedge clk_i)
     if (rst)
       bus_state <= #DELAY `BUS_IDLE;
     else
       case (bus_state)
         `BUS_IDLE:
           bus_state <= #DELAY cyc_i && stb_i ? `BUS_READ : bus_state ;

         `BUS_READ:
           bus_state <= #DELAY bst_i ? bus_state : `BUS_WAIT ;

         `BUS_WAIT:
           bus_state <= #DELAY cyc_i ? (stb_i ? `BUS_READ : bus_state) : `BUS_IDLE ;
       endcase


   always @(posedge clk_i)
     if (rst) bank_n <= #DELAY 1;
     else     bank_n <= #DELAY ~bank;
   

   always @(posedge clk_i)
     if (cyc_i && stb_i)
       dat_o <= #DELAY adr_i[4] ? counts1[adr_w] : counts0[adr_w];





   wire [11:0] ax0 = antenna[11: 0];
   wire [11:0] ax1 = antenna[23:12];
   reg         active = 0, valid = 0, a0, a1;


   always @(posedge clk_x) begin
      a0  <= #DELAY ax0[x_rd_adr];
      a1  <= #DELAY ax1[x_rd_adr];
   end

   always @(posedge clk_x)
     if (rst || !enable) active <= #DELAY 0;
     else if (enable)    active <= #DELAY 1;
     else                active <= #DELAY active;


   always @(posedge clk_x) begin
      qcnt0 <= #DELAY dcnt0 + a0;
      qcnt1 <= #DELAY dcnt1 + a1;
      valid <= #DELAY rst ? 0 : active;
   end


endmodule