data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv
 line:22: before: "REM_END"
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:57: Cannot find include file: axi4s.vh\n `include "axi4s.vh" \n          ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv,data/full_repos/permissive/214858095/axi4s.vh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv,data/full_repos/permissive/214858095/axi4s.vh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv,data/full_repos/permissive/214858095/axi4s.vh.sv\n             axi4s.vh\n             axi4s.vh.v\n             axi4s.vh.sv\n             obj_dir/axi4s.vh\n             obj_dir/axi4s.vh.v\n             obj_dir/axi4s.vh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:24: Unsupported: virtual or generic interfaces\n  interface   i,   \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:25: Unsupported: virtual or generic interfaces\n  interface   o    \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:71: Define or directive not defined: \'`AXI4S_ASSIGN\'\n    `AXI4S_ASSIGN(s0,i)\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:71: syntax error, unexpected \',\'\n    `AXI4S_ASSIGN(s0,i)\n                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:93: syntax error, unexpected else\n    end else begin\n        ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:105: syntax error, unexpected <=, expecting IDENTIFIER\n        s1.tdata <= s0.tdata;\n                 ^~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:106: syntax error, unexpected <=, expecting IDENTIFIER\n        s1.tuser <= s0.tuser;\n                 ^~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:107: syntax error, unexpected <=, expecting IDENTIFIER\n        s1.tlast <= s0.tlast;\n                 ^~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:108: syntax error, unexpected <=, expecting IDENTIFIER\n        s1.tvalid <= 1;  \n                  ^~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:114: syntax error, unexpected <=, expecting IDENTIFIER\n        s1.tuser <= \'X;\n                 ^~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:115: syntax error, unexpected <=, expecting IDENTIFIER\n        s1.tlast <= 1\'bX;\n                 ^~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:116: syntax error, unexpected <=, expecting IDENTIFIER\n        s1.tvalid <= 0;  \n                  ^~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:330: Define or directive not defined: \'`AXI4S_ASSIGN\'\n    `AXI4S_ASSIGN(o,s2)\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_start.sv:330: syntax error, unexpected \',\'\n    `AXI4S_ASSIGN(o,s2)\n                   ^\n%Error: Cannot continue\n'
module axi4s_remove_bytes_start #(
  REM_END=3
)(
  interface   i,
  interface   o
);



  localparam UWIDTH = $clog2(i.BYTES_PER_WORD)+1;
  localparam ERROR = UWIDTH-1;


  localparam BYTES_REMOVED = REM_END+1;


  localparam END_BYTE   = REM_END  % i.BYTES_PER_WORD;
  localparam END_WORD   = REM_END  / i.BYTES_PER_WORD;










  localparam BYTE_SHIFT = BYTES_REMOVED % i.BYTES_PER_WORD;
  localparam BYTE_CARRY = i.BYTES_PER_WORD - BYTE_SHIFT;

  initial begin
    assert(END_BYTE != i.BYTES_PER_WORD-1 ) else
      $fatal(1,"Required to be not EXACT");
  end

 `include "axi4s.vh"

  AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
    .TKEEP(0),.MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
    s0(i.clk,i.rst);
  AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
    .TKEEP(0),.MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
    s1(i.clk,i.rst);
  AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
    .TKEEP(0),.MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
    s2(i.clk,i.rst);


  always_comb begin
    `AXI4S_ASSIGN(s0,i)
  end




  typedef enum {ST_REMOVING, ST_POST_REMOVE} remove_state_t;
  remove_state_t remove_state      = ST_REMOVING;
  remove_state_t next_remove_state = ST_REMOVING;


  logic s0_wr,s1_rd;
  always_comb s0_wr = s0.tvalid && s0.tready;
  always_comb s1_rd = s1.tvalid && s1.tready;

  always_ff @(posedge s1.clk) begin
    if (s1.rst) begin

      s1.tdata <= 0;
      s1.tuser <= 0;
      s1.tlast <= 0;
      s1.tvalid <= 0;
    end else begin


      if (s0_wr) begin





        assert (!s1.tvalid || s1_rd) else
              $fatal(1,"Overflow write");

        s1.tdata <= s0.tdata;
        s1.tuser <= s0.tuser;
        s1.tlast <= s0.tlast;
        s1.tvalid <= 1;



      end else if (s1_rd) begin
        s1.tdata <= 'X;
        s1.tuser <= 'X;
        s1.tlast <= 1'bX;
        s1.tvalid <= 0;
      end

    end
  end



  always_comb s0.tready = !s1.tvalid || s1_rd;

  /
  function automatic logic [s0.DATA_WIDTH-1-BYTE_SHIFT*8:0] bs_part([s0.DATA_WIDTH-1:0] data);
    begin
      return data[s0.DATA_WIDTH-1:BYTE_SHIFT*8];
    end
  endfunction
















  logic [s0.DATA_WIDTH-1:0] shift_data;
  always_comb shift_data = {s0.tdata,bs_part(s1.tdata)};






  function automatic [UWIDTH-1:0] uwrite(error=0,[UWIDTH-2:0] bytes=0);
    begin
      return {error,bytes};
    end
  endfunction




  function automatic get_error([UWIDTH-1:0] tuser);
    begin
      return tuser[ERROR];
    end
  endfunction




  function automatic [UWIDTH-1:0] get_bytes([UWIDTH-1:0] tuser);
    logic [UWIDTH-1:0] bytes;
    begin
      if (tuser[UWIDTH-2:0] == 0) bytes = s0.BYTES_PER_WORD;
      else                        bytes = tuser[UWIDTH-2:0];
      return bytes;
    end
  endfunction

  logic [UWIDTH-1:0] s0_byte_count, s1_byte_count;
  always_comb s0_byte_count = get_bytes(s0.tuser);
  always_comb s1_byte_count = get_bytes(s1.tuser);

  logic s1_error_bit, s1_error_bit_old;
  logic s0_error_bit, s0_error_bit_old;

  always_ff @(posedge s0.clk) begin
    if (s0.rst) begin
      s0_error_bit_old <= 0;
      s1_error_bit_old <= 0;
    end else begin

      if (s1.tlast && s1.tvalid && s1.tready) begin
        s1_error_bit_old <= 0;

      end else if (s1.tvalid && s1.tready) begin
        s1_error_bit_old <= s1_error_bit;
      end

      if (s0.tlast && s0.tvalid && s0.tready) begin
        s0_error_bit_old <= 0;

      end else if (s1.tvalid && s1.tready) begin
        s0_error_bit_old <= s0_error_bit;
      end

    end
  end

  assign s1_error_bit = get_error(s1.tuser) && s1.tvalid || s1_error_bit_old;
  assign s0_error_bit = get_error(s0.tuser) && s0.tvalid || s0_error_bit_old;

  logic s1_reached_end;
  always_comb s1_reached_end = s1.reached_packet_byte(REM_END);


  always_comb begin : remove_next_state

    next_remove_state = remove_state;

    s2.tdata = shift_data;
    s2.tuser = s1.tuser;
    s2.tlast = s1.tlast;
    s2.tvalid = s1.tvalid;
    s1.tready = s2.tready;
    case (remove_state)




      ST_REMOVING: begin

        s2.tuser  = 0;
        s2.tlast  = 0;
        s2.tvalid = 0;
        s1.tready = 1;


        if (s1.tvalid && s1_reached_end) begin



          if (s1.tlast && s1_byte_count <= BYTE_SHIFT) begin
            s2.tlast  = 1;
            s2.tvalid = 0;
            s1.tready = 1;

          end else if (s0.tlast && s0_byte_count <= BYTE_SHIFT) begin
            s2.tlast  = 1;
            s2.tuser = uwrite(s1_error_bit || s0_error_bit,s0_byte_count + BYTE_CARRY);
            s2.tvalid = s0.tvalid && s1.tvalid;
            s2.tlast = 1;
            s1.tready = s2.tready && s0.tvalid;

          end else if (s1.tlast) begin
            s2.tlast  = 1;
            s2.tuser = uwrite(s1_error_bit,s1_byte_count - BYTE_SHIFT);
            s2.tvalid = s1.tvalid;
            s1.tready = s2.tready;

          end else begin
            s2.tuser  = uwrite(s1_error_bit || s0_error_bit,s0.BYTES_PER_WORD);
            s2.tvalid = s0.tvalid && s1.tvalid;
            s2.tlast = 0;
            s1.tready = s2.tready && s0.tvalid;
            if (s2.tready && s0.tvalid && s1.tvalid) begin
            next_remove_state = ST_POST_REMOVE;
            end
          end
        end

      end




      ST_POST_REMOVE: begin


        s2.tuser  = uwrite(s1_error_bit || s0_error_bit,s0.BYTES_PER_WORD);
        s2.tvalid = s0.tvalid && s1.tvalid;
        s2.tlast = 0;
        s1.tready = s2.tready && s0.tvalid;







        if (s0.tlast && s0_byte_count <= BYTE_SHIFT) begin
          s2.tuser = uwrite(s1_error_bit || s0_error_bit,s0_byte_count + BYTE_CARRY);
          s2.tvalid = s0.tvalid && s1.tvalid;
          s2.tlast = 1;
          if (s2.tready && s0.tvalid && s1.tvalid) begin
            next_remove_state = ST_REMOVING;
          end

        end else if (s1.tlast) begin
          s2.tuser = uwrite(s1_error_bit,s1_byte_count - BYTE_SHIFT);
          s2.tvalid = s1.tvalid;
          s2.tlast = 1;
          if (s2.tready && s1.tvalid) begin
            next_remove_state = ST_REMOVING;
          end

        end
      end


      default: begin
        next_remove_state = ST_REMOVING;
      end
    endcase
  end

  always_ff @(posedge s1.clk) begin
    if (s1.rst) begin
      remove_state <= ST_REMOVING;
    end else begin
      remove_state <= next_remove_state;
    end
  end


  always_comb begin
    `AXI4S_ASSIGN(o,s2)
  end

endmodule
module axi4s_remove_bytes_start #(
  REM_END=3
)(
  interface   i,
  interface   o
);




  localparam UWIDTH = $clog2(i.BYTES_PER_WORD)+1;
  localparam ERROR = UWIDTH-1;


  localparam BYTES_REMOVED = REM_END+1;


  localparam END_BYTE   = REM_END  % i.BYTES_PER_WORD;
  localparam END_WORD   = REM_END  / i.BYTES_PER_WORD;










  localparam BYTE_SHIFT = BYTES_REMOVED % i.BYTES_PER_WORD;
  localparam BYTE_CARRY = i.BYTES_PER_WORD - BYTE_SHIFT;

  initial begin
    assert(END_BYTE != i.BYTES_PER_WORD-1 ) else
      $fatal(1,"Required to be not EXACT");
  end

 `include "axi4s.vh"

  AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
    .TKEEP(0),.MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
    s0(i.clk,i.rst);
  AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
    .TKEEP(0),.MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
    s1(i.clk,i.rst);
  AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
    .TKEEP(0),.MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
    s2(i.clk,i.rst);


  always_comb begin
    `AXI4S_ASSIGN(s0,i)
  end




  typedef enum {ST_REMOVING, ST_POST_REMOVE} remove_state_t;
  remove_state_t remove_state      = ST_REMOVING;
  remove_state_t next_remove_state = ST_REMOVING;


  logic s0_wr,s1_rd;
  always_comb s0_wr = s0.tvalid && s0.tready;
  always_comb s1_rd = s1.tvalid && s1.tready;

  always_ff @(posedge s1.clk) begin
    if (s1.rst) begin

      s1.tdata <= 0;
      s1.tuser <= 0;
      s1.tlast <= 0;
      s1.tvalid <= 0;
    end else begin


      if (s0_wr) begin





        assert (!s1.tvalid || s1_rd) else
              $fatal(1,"Overflow write");

        s1.tdata <= s0.tdata;
        s1.tuser <= s0.tuser;
        s1.tlast <= s0.tlast;
        s1.tvalid <= 1;



      end else if (s1_rd) begin
        s1.tdata <= 'X;
        s1.tuser <= 'X;
        s1.tlast <= 1'bX;
        s1.tvalid <= 0;
      end

    end
  end



  always_comb s0.tready = !s1.tvalid || s1_rd;

  /
  function automatic logic [s0.DATA_WIDTH-1-BYTE_SHIFT*8:0] bs_part([s0.DATA_WIDTH-1:0] data);
    begin
      return data[s0.DATA_WIDTH-1:BYTE_SHIFT*8];
    end
  endfunction
















  logic [s0.DATA_WIDTH-1:0] shift_data;
  always_comb shift_data = {s0.tdata,bs_part(s1.tdata)};






  function automatic [UWIDTH-1:0] uwrite(error=0,[UWIDTH-2:0] bytes=0);
    begin
      return {error,bytes};
    end
  endfunction




  function automatic get_error([UWIDTH-1:0] tuser);
    begin
      return tuser[ERROR];
    end
  endfunction




  function automatic [UWIDTH-1:0] get_bytes([UWIDTH-1:0] tuser);
    logic [UWIDTH-1:0] bytes;
    begin
      if (tuser[UWIDTH-2:0] == 0) bytes = s0.BYTES_PER_WORD;
      else                        bytes = tuser[UWIDTH-2:0];
      return bytes;
    end
  endfunction

  logic [UWIDTH-1:0] s0_byte_count, s1_byte_count;
  always_comb s0_byte_count = get_bytes(s0.tuser);
  always_comb s1_byte_count = get_bytes(s1.tuser);

  logic s1_error_bit, s1_error_bit_old;
  logic s0_error_bit, s0_error_bit_old;

  always_ff @(posedge s0.clk) begin
    if (s0.rst) begin
      s0_error_bit_old <= 0;
      s1_error_bit_old <= 0;
    end else begin

      if (s1.tlast && s1.tvalid && s1.tready) begin
        s1_error_bit_old <= 0;

      end else if (s1.tvalid && s1.tready) begin
        s1_error_bit_old <= s1_error_bit;
      end

      if (s0.tlast && s0.tvalid && s0.tready) begin
        s0_error_bit_old <= 0;

      end else if (s1.tvalid && s1.tready) begin
        s0_error_bit_old <= s0_error_bit;
      end

    end
  end

  assign s1_error_bit = get_error(s1.tuser) && s1.tvalid || s1_error_bit_old;
  assign s0_error_bit = get_error(s0.tuser) && s0.tvalid || s0_error_bit_old;

  logic s1_reached_end;
  always_comb s1_reached_end = s1.reached_packet_byte(REM_END);


  always_comb begin : remove_next_state

    next_remove_state = remove_state;

    s2.tdata = shift_data;
    s2.tuser = s1.tuser;
    s2.tlast = s1.tlast;
    s2.tvalid = s1.tvalid;
    s1.tready = s2.tready;
    case (remove_state)




      ST_REMOVING: begin

        s2.tuser  = 0;
        s2.tlast  = 0;
        s2.tvalid = 0;
        s1.tready = 1;


        if (s1.tvalid && s1_reached_end) begin



          if (s1.tlast && s1_byte_count <= BYTE_SHIFT) begin
            s2.tlast  = 1;
            s2.tvalid = 0;
            s1.tready = 1;

          end else if (s0.tlast && s0_byte_count <= BYTE_SHIFT) begin
            s2.tlast  = 1;
            s2.tuser = uwrite(s1_error_bit || s0_error_bit,s0_byte_count + BYTE_CARRY);
            s2.tvalid = s0.tvalid && s1.tvalid;
            s2.tlast = 1;
            s1.tready = s2.tready && s0.tvalid;

          end else if (s1.tlast) begin
            s2.tlast  = 1;
            s2.tuser = uwrite(s1_error_bit,s1_byte_count - BYTE_SHIFT);
            s2.tvalid = s1.tvalid;
            s1.tready = s2.tready;

          end else begin
            s2.tuser  = uwrite(s1_error_bit || s0_error_bit,s0.BYTES_PER_WORD);
            s2.tvalid = s0.tvalid && s1.tvalid;
            s2.tlast = 0;
            s1.tready = s2.tready && s0.tvalid;
            if (s2.tready && s0.tvalid && s1.tvalid) begin
            next_remove_state = ST_POST_REMOVE;
            end
          end
        end

      end




      ST_POST_REMOVE: begin


        s2.tuser  = uwrite(s1_error_bit || s0_error_bit,s0.BYTES_PER_WORD);
        s2.tvalid = s0.tvalid && s1.tvalid;
        s2.tlast = 0;
        s1.tready = s2.tready && s0.tvalid;







        if (s0.tlast && s0_byte_count <= BYTE_SHIFT) begin
          s2.tuser = uwrite(s1_error_bit || s0_error_bit,s0_byte_count + BYTE_CARRY);
          s2.tvalid = s0.tvalid && s1.tvalid;
          s2.tlast = 1;
          if (s2.tready && s0.tvalid && s1.tvalid) begin
            next_remove_state = ST_REMOVING;
          end

        end else if (s1.tlast) begin
          s2.tuser = uwrite(s1_error_bit,s1_byte_count - BYTE_SHIFT);
          s2.tvalid = s1.tvalid;
          s2.tlast = 1;
          if (s2.tready && s1.tvalid) begin
            next_remove_state = ST_REMOVING;
          end

        end
      end


      default: begin
        next_remove_state = ST_REMOVING;
      end
    endcase
  end

  always_ff @(posedge s1.clk) begin
    if (s1.rst) begin
      remove_state <= ST_REMOVING;
    end else begin
      remove_state <= next_remove_state;
    end
  end


  always_comb begin
    `AXI4S_ASSIGN(o,s2)
  end

endmodule