data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_serializer_eof2.sv
data/verilator_xmls/b617310f-3e7e-47d3-a863-6e523c95bf45.xml
module stream_serializer_eof2 #(
  parameter DataBits = 8,
  parameter Ratio = 2)
(
  input                      clk,
  input                      rst,

  input                      in_valid,
  output                     in_ready,
  input [Ratio*DataBits-1:0] in_data,
  input [Ratio-1:0]          in_eof,

  output                     out_valid,
  input                      out_ready,
  output [DataBits-1:0]      out_data,
  output                     out_eof
);

  logic [Ratio-1:0]              count;
  logic [(Ratio-1)*DataBits-1:0] data_r;
  logic [Ratio-2:0]              eof_r;

  always_ff @(posedge clk) begin


    if (out_valid & out_ready) begin
      count <= (count[Ratio-1] | out_eof) ? 1 : count << 1;
    end


    if (out_ready) begin
      if (count[0] & in_valid) begin

        data_r <= in_data[Ratio*DataBits-1:DataBits];
        eof_r  <= in_eof[Ratio-1:1];
      end else begin

        data_r <= data_r >> DataBits;
        eof_r  <= eof_r  >> 1;
      end
    end

    if (rst) begin
      count <= 1;
    end
  end

  assign in_ready  = count[0] ? out_ready : 1'b0;
  assign out_valid = count[0] ? in_valid  : 1'b1;
  assign out_data  = count[0] ? in_data[DataBits-1:0] : data_r[DataBits-1:0];
  assign out_eof   = count[0] ? in_eof[0] : eof_r[0];

endmodule
module stream_serializer_eof2 #(
  parameter DataBits = 8,
  parameter Ratio = 2)
(
  input                      clk,
  input                      rst,

  input                      in_valid,
  output                     in_ready,
  input [Ratio*DataBits-1:0] in_data,
  input [Ratio-1:0]          in_eof,

  output                     out_valid,
  input                      out_ready,
  output [DataBits-1:0]      out_data,
  output                     out_eof
);


  logic [Ratio-1:0]              count;
  logic [(Ratio-1)*DataBits-1:0] data_r;
  logic [Ratio-2:0]              eof_r;

  always_ff @(posedge clk) begin


    if (out_valid & out_ready) begin
      count <= (count[Ratio-1] | out_eof) ? 1 : count << 1;
    end


    if (out_ready) begin
      if (count[0] & in_valid) begin

        data_r <= in_data[Ratio*DataBits-1:DataBits];
        eof_r  <= in_eof[Ratio-1:1];
      end else begin

        data_r <= data_r >> DataBits;
        eof_r  <= eof_r  >> 1;
      end
    end

    if (rst) begin
      count <= 1;
    end
  end

  assign in_ready  = count[0] ? out_ready : 1'b0;
  assign out_valid = count[0] ? in_valid  : 1'b1;
  assign out_data  = count[0] ? in_data[DataBits-1:0] : data_r[DataBits-1:0];
  assign out_eof   = count[0] ? in_eof[0] : eof_r[0];

endmodule