data/full_repos/permissive/117026779/src/VGA.v
1: b"%Error: data/full_repos/permissive/117026779/src/VGA.v:93: syntax error, unexpected '(', expecting IDENTIFIER\n    .clk(clk),\n    ^\n%Error: Exiting due to 1 error(s)\n"
module VGA_Terminal(

    input wire clk,
    input wire rst,

    output wire hsync,

    output wire vsync,

    output wire [`RGB_RESOLUTION-1:0] r,
    output wire [`RGB_RESOLUTION-1:0] g,
    output wire [`RGB_RESOLUTION-1:0] b,
    input wire [`VALUE_BIT_WIDTH-1:0] value0,
    input wire [`VALUE_BIT_WIDTH-1:0] value1,
    input wire [`VALUE_BIT_WIDTH-1:0] value2,
    input wire [`VALUE_BIT_WIDTH-1:0] value3,
    input wire [`VALUE_BIT_WIDTH-1:0] value4,
    input wire [`VALUE_BIT_WIDTH-1:0] value5,
    input wire [`VALUE_BIT_WIDTH-1:0] value6,
    input wire [`VALUE_BIT_WIDTH-1:0] value7,
    input wire [`VALUE_BIT_WIDTH-1:0] value8,
    input wire [`VALUE_BIT_WIDTH-1:0] value9,
    input wire [`VALUE_BIT_WIDTH-1:0] value10,
    input wire [`VALUE_BIT_WIDTH-1:0] value11,
    input wire [`VALUE_BIT_WIDTH-1:0] value12,
    input wire [`VALUE_BIT_WIDTH-1:0] value13,
    input wire [`VALUE_BIT_WIDTH-1:0] value14,
    input wire [`VALUE_BIT_WIDTH-1:0] value15,
    input wire [`VALUE_BIT_WIDTH-1:0] value16,
    input wire [`VALUE_BIT_WIDTH-1:0] value17,
    input wire [`VALUE_BIT_WIDTH-1:0] value18,
    input wire [`VALUE_BIT_WIDTH-1:0] value19,


    input wire [`VGA_RAM_ADDRESS_WIDTH-1:0] address,

    input wire [`ASCII_WIDTH-1:0] data,

    input wire cs,

    output wire busy,
    input wire [2:0] text,
    input wire [2:0] background
);









wire [(`TOTAL_SEGMENTS*`VALUE_BIT_WIDTH)-1:0] values = {
    value0,  value1,  value2,  value3,
    value4,  value5,  value6,  value7,
    value8,  value9,  value10, value11,
    value12, value13, value14, value15,
    value16, value17, value18, value19
};


wire pclk;

wire [`VGA_RAM_ADDRESS_WIDTH-1:0] external_address;

wire enable_rgb;

wire [`VGA_RAM_ADDRESS_WIDTH-1:0] xyaddress;

wire [`PIXEL_WIDTH-1:0] pixels;


wire [31:0] hcount;

wire [31:0] vcount;

wire hblank;

wire vblank;



wire [`VGA_RAM_ADDRESS_WIDTH-1:0] video_ctrl_address;


wire [`VGA_RAM_ADDRESS_WIDTH-1:0] buffer_ctrl_address;


wire [`VGA_RAM_ADDRESS_WIDTH-1:0] video_address;


wire [`VGA_RAM_ADDRESS_WIDTH-1:0] buffer_address;

wire [`ASCII_WIDTH-1:0] video_data;

wire [`ASCII_WIDTH-1:0] buffer_data;


wire xy_count_select;


wire buffer_databus_enable;

wire buffer_ctrl_cs;

wire video_wr;
wire video_cs;
wire video_oe;

wire buffer_wr;
wire buffer_cs;
wire buffer_oe;



assign busy = buffer_ctrl_cs;

assign enable_rgb = !(hblank | vblank);

assign external_address = address+(`TERMINAL_COLUMNS*`HARDWARE_CONTROLLED_ROWS);



PixelClock pixel_clock_generator(
    .clk100Mhz(clk),
    .rst(rst),
    .pclk(pclk)
);

VGA vga_controller(
    .pclk(pclk),
    .rst(rst),
    .hsync(hsync),
    .vsync(vsync),
    .hcount(hcount),
    .vcount(vcount),
    .hblank(hblank),
    .vblank(vblank)
);

VGA_Terminal_Control_Unit cu(
    .pclk(clk),
    .rst(rst),
    .vblank(vblank),
    .hblank(hblank),
    .values(values),
    .video_address(video_ctrl_address),
    .buffer_address(buffer_ctrl_address),
    .external_address(external_address),
    .video_data(video_data),
    .buffer_data(buffer_data),
    .xy_count_select(xy_count_select),
    .buffer_databus_enable(buffer_databus_enable),
    .video_wr(video_wr),
    .video_cs(video_cs),
    .video_oe(video_oe),
    .buffer_wr(buffer_wr),
    .buffer_cs(buffer_ctrl_cs),
    .buffer_oe(buffer_oe)
);

ConvertXYToAddress linearize(
    .hcount(hcount),
    .vcount(vcount),
    .address(xyaddress)
);

MUX #(
    .WIDTH(`VGA_RAM_ADDRESS_WIDTH),
    .INPUTS(2)
) ram_address_mux (
    .select(xy_count_select),
    .in({xyaddress, video_ctrl_address}),
    .out(video_address)
);

RAM #(
    .LENGTH(`TERMINAL_CHARACTER_COUNT),
    .USE_FILE(0),
    .WIDTH(`ASCII_WIDTH),
    .MINIMUM_SECTIONAL_WIDTH(`ASCII_WIDTH),
    .FILE_NAME("")
) video_ram (
    .clk(clk),
    .we(video_wr),
    .cs(video_cs),
    .oe(video_oe),
    .address(video_address),
    .data(video_data)
);

MUX #(
    .WIDTH(`VGA_RAM_ADDRESS_WIDTH),
    .INPUTS(2)
) buffer_address_mux (
    .select(buffer_ctrl_cs),
    .in({buffer_ctrl_address, external_address }),
    .out(buffer_address)
);

MUX #(
    .WIDTH(1),
    .INPUTS(2)
) buffer_cs_mux (
    .select(buffer_ctrl_cs),
    .in({buffer_ctrl_cs, cs}),
    .out(buffer_cs)
);

TRIBUFFER#(.WIDTH(`ASCII_WIDTH)) tristate_switch_data_bus (
    .oe(!buffer_ctrl_cs),
    .in(data),
    .out(buffer_data)
);

RAM #(
    .LENGTH(`TERMINAL_CHARACTER_COUNT),
    .USE_FILE(0),
    .WIDTH(`ASCII_WIDTH),
    .MINIMUM_SECTIONAL_WIDTH(`ASCII_WIDTH),
    .FILE_NAME("")
) buffer_ram(
    .clk(clk),
    .we(buffer_wr),
    .cs(buffer_cs),
    .oe(buffer_oe),
    .address(buffer_address),
    .data(buffer_data)
);

FontROM rom(
    .ascii(video_data),
    .column(vcount[3:0]),
    .pixels(pixels)
);

PixelRender pixel_renderer(
    .enable(enable_rgb),
    .hcount(hcount),
    .pixels(pixels),
    .r(r),
    .g(g),
    .b(b),
    .text(text),
    .background(background)
);



endmodule
module VGA_Terminal(

    input wire clk,
    input wire rst,

    output wire hsync,

    output wire vsync,

    output wire [`RGB_RESOLUTION-1:0] r,
    output wire [`RGB_RESOLUTION-1:0] g,
    output wire [`RGB_RESOLUTION-1:0] b,
    input wire [`VALUE_BIT_WIDTH-1:0] value0,
    input wire [`VALUE_BIT_WIDTH-1:0] value1,
    input wire [`VALUE_BIT_WIDTH-1:0] value2,
    input wire [`VALUE_BIT_WIDTH-1:0] value3,
    input wire [`VALUE_BIT_WIDTH-1:0] value4,
    input wire [`VALUE_BIT_WIDTH-1:0] value5,
    input wire [`VALUE_BIT_WIDTH-1:0] value6,
    input wire [`VALUE_BIT_WIDTH-1:0] value7,
    input wire [`VALUE_BIT_WIDTH-1:0] value8,
    input wire [`VALUE_BIT_WIDTH-1:0] value9,
    input wire [`VALUE_BIT_WIDTH-1:0] value10,
    input wire [`VALUE_BIT_WIDTH-1:0] value11,
    input wire [`VALUE_BIT_WIDTH-1:0] value12,
    input wire [`VALUE_BIT_WIDTH-1:0] value13,
    input wire [`VALUE_BIT_WIDTH-1:0] value14,
    input wire [`VALUE_BIT_WIDTH-1:0] value15,
    input wire [`VALUE_BIT_WIDTH-1:0] value16,
    input wire [`VALUE_BIT_WIDTH-1:0] value17,
    input wire [`VALUE_BIT_WIDTH-1:0] value18,
    input wire [`VALUE_BIT_WIDTH-1:0] value19,


    input wire [`VGA_RAM_ADDRESS_WIDTH-1:0] address,

    input wire [`ASCII_WIDTH-1:0] data,

    input wire cs,

    output wire busy,
    input wire [2:0] text,
    input wire [2:0] background
);










wire [(`TOTAL_SEGMENTS*`VALUE_BIT_WIDTH)-1:0] values = {
    value0,  value1,  value2,  value3,
    value4,  value5,  value6,  value7,
    value8,  value9,  value10, value11,
    value12, value13, value14, value15,
    value16, value17, value18, value19
};


wire pclk;

wire [`VGA_RAM_ADDRESS_WIDTH-1:0] external_address;

wire enable_rgb;

wire [`VGA_RAM_ADDRESS_WIDTH-1:0] xyaddress;

wire [`PIXEL_WIDTH-1:0] pixels;


wire [31:0] hcount;

wire [31:0] vcount;

wire hblank;

wire vblank;



wire [`VGA_RAM_ADDRESS_WIDTH-1:0] video_ctrl_address;


wire [`VGA_RAM_ADDRESS_WIDTH-1:0] buffer_ctrl_address;


wire [`VGA_RAM_ADDRESS_WIDTH-1:0] video_address;


wire [`VGA_RAM_ADDRESS_WIDTH-1:0] buffer_address;

wire [`ASCII_WIDTH-1:0] video_data;

wire [`ASCII_WIDTH-1:0] buffer_data;


wire xy_count_select;


wire buffer_databus_enable;

wire buffer_ctrl_cs;

wire video_wr;
wire video_cs;
wire video_oe;

wire buffer_wr;
wire buffer_cs;
wire buffer_oe;



assign busy = buffer_ctrl_cs;

assign enable_rgb = !(hblank | vblank);

assign external_address = address+(`TERMINAL_COLUMNS*`HARDWARE_CONTROLLED_ROWS);



PixelClock pixel_clock_generator(
    .clk100Mhz(clk),
    .rst(rst),
    .pclk(pclk)
);

VGA vga_controller(
    .pclk(pclk),
    .rst(rst),
    .hsync(hsync),
    .vsync(vsync),
    .hcount(hcount),
    .vcount(vcount),
    .hblank(hblank),
    .vblank(vblank)
);

VGA_Terminal_Control_Unit cu(
    .pclk(clk),
    .rst(rst),
    .vblank(vblank),
    .hblank(hblank),
    .values(values),
    .video_address(video_ctrl_address),
    .buffer_address(buffer_ctrl_address),
    .external_address(external_address),
    .video_data(video_data),
    .buffer_data(buffer_data),
    .xy_count_select(xy_count_select),
    .buffer_databus_enable(buffer_databus_enable),
    .video_wr(video_wr),
    .video_cs(video_cs),
    .video_oe(video_oe),
    .buffer_wr(buffer_wr),
    .buffer_cs(buffer_ctrl_cs),
    .buffer_oe(buffer_oe)
);

ConvertXYToAddress linearize(
    .hcount(hcount),
    .vcount(vcount),
    .address(xyaddress)
);

MUX #(
    .WIDTH(`VGA_RAM_ADDRESS_WIDTH),
    .INPUTS(2)
) ram_address_mux (
    .select(xy_count_select),
    .in({xyaddress, video_ctrl_address}),
    .out(video_address)
);

RAM #(
    .LENGTH(`TERMINAL_CHARACTER_COUNT),
    .USE_FILE(0),
    .WIDTH(`ASCII_WIDTH),
    .MINIMUM_SECTIONAL_WIDTH(`ASCII_WIDTH),
    .FILE_NAME("")
) video_ram (
    .clk(clk),
    .we(video_wr),
    .cs(video_cs),
    .oe(video_oe),
    .address(video_address),
    .data(video_data)
);

MUX #(
    .WIDTH(`VGA_RAM_ADDRESS_WIDTH),
    .INPUTS(2)
) buffer_address_mux (
    .select(buffer_ctrl_cs),
    .in({buffer_ctrl_address, external_address }),
    .out(buffer_address)
);

MUX #(
    .WIDTH(1),
    .INPUTS(2)
) buffer_cs_mux (
    .select(buffer_ctrl_cs),
    .in({buffer_ctrl_cs, cs}),
    .out(buffer_cs)
);

TRIBUFFER#(.WIDTH(`ASCII_WIDTH)) tristate_switch_data_bus (
    .oe(!buffer_ctrl_cs),
    .in(data),
    .out(buffer_data)
);

RAM #(
    .LENGTH(`TERMINAL_CHARACTER_COUNT),
    .USE_FILE(0),
    .WIDTH(`ASCII_WIDTH),
    .MINIMUM_SECTIONAL_WIDTH(`ASCII_WIDTH),
    .FILE_NAME("")
) buffer_ram(
    .clk(clk),
    .we(buffer_wr),
    .cs(buffer_cs),
    .oe(buffer_oe),
    .address(buffer_address),
    .data(buffer_data)
);

FontROM rom(
    .ascii(video_data),
    .column(vcount[3:0]),
    .pixels(pixels)
);

PixelRender pixel_renderer(
    .enable(enable_rgb),
    .hcount(hcount),
    .pixels(pixels),
    .r(r),
    .g(g),
    .b(b),
    .text(text),
    .background(background)
);



endmodule