data/full_repos/permissive/204486675/components/spi/spi_tb.v
 line:91: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/204486675/components/spi/spi_tb.v:58: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile(`VCD_OUTPUT".vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/204486675/components/spi/spi_tb.v:58: Define or directive not defined: \'`VCD_OUTPUT\'\n  $dumpfile(`VCD_OUTPUT".vcd");\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/components/spi/spi_tb.v:59: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, spi_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #1 rst <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #1 rst <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #1 data_i <= 8\'b01011010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #1  go <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #9 miso <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10 cpol <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1  go <= 1\'b1;      \n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #1  go <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #9 miso <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #10 cpol <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #1  go <= 1\'b1;      \n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #1  go <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n #9  miso <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10  cpol <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #1  go <= 1\'b1;      \n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n #1  go <= 1\'b0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n #9 miso <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/spi/spi_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n   #(DURATION) $display("End of simulation");\n   ^\n%Error: Exiting due to 3 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spi_tb();


reg clk = 1;
always #0.5 clk = ~clk;

reg rst;
reg go;
wire state;
reg cpol;
reg cpha;
reg cspol;
reg autocs;
reg [7:0] data_i;
wire [7:0] data_o;
wire mosi;
reg miso;
wire sclk;
wire cs;

parameter DURATION = 100;

spimaster UUT (
	.rst(rst),
	.clkin(clk),
	.go(go),
	.state(state),
	.cpol(cpol),
	.cpha(cpha),
	.cspol(cspol),
	.autocs(autocs),
	.data_i(data_i),
	.data_o(data_o),
	.miso(miso),
	.mosi(mosi),
	.sclk(sclk),
	.cs(cs)
);

initial begin

  $dumpfile(`DUMPSTR(`VCD_OUTPUT));
  $dumpvars(0, spi_tb);

	#1	rst <= 1;
		go <= 0;
		cpol <= 1;
		cpha <= 0;
		cspol <= 1;
		miso <= 0;
		autocs <= 1;
	#1	rst <= 0;
	#1	data_i <= 8'b01011010;
		go <= 1'b1;
	#1  go <= 1'b0;
	#9	miso <= 1;
	#10	cpol <= 0;
	#1  go <= 1'b1;
		cpol <= 0;
	#1 	go <= 1'b0;
	#9	miso <= 0;
	#10 cpol <= 1;
		cpha <= 1;
	#1  go <= 1'b1;
		cpol <= 1;
		cpha <= 1;
	#1  go <= 1'b0;
	#9  miso <= 1;
	#10 	cpol <= 0;
	#1  go <= 1'b1;
		cpol <= 0;
	#1  go <= 1'b0; 
	#9 miso <= 0;

   #(DURATION) $display("End of simulation");
  $finish;
end

endmodule
module spi_tb();



reg clk = 1;
always #0.5 clk = ~clk;

reg rst;
reg go;
wire state;
reg cpol;
reg cpha;
reg cspol;
reg autocs;
reg [7:0] data_i;
wire [7:0] data_o;
wire mosi;
reg miso;
wire sclk;
wire cs;

parameter DURATION = 100;

spimaster UUT (
	.rst(rst),
	.clkin(clk),
	.go(go),
	.state(state),
	.cpol(cpol),
	.cpha(cpha),
	.cspol(cspol),
	.autocs(autocs),
	.data_i(data_i),
	.data_o(data_o),
	.miso(miso),
	.mosi(mosi),
	.sclk(sclk),
	.cs(cs)
);

initial begin

  $dumpfile(`DUMPSTR(`VCD_OUTPUT));
  $dumpvars(0, spi_tb);

	#1	rst <= 1;
		go <= 0;
		cpol <= 1;
		cpha <= 0;
		cspol <= 1;
		miso <= 0;
		autocs <= 1;
	#1	rst <= 0;
	#1	data_i <= 8'b01011010;
		go <= 1'b1;
	#1  go <= 1'b0;
	#9	miso <= 1;
	#10	cpol <= 0;
	#1  go <= 1'b1;
		cpol <= 0;
	#1 	go <= 1'b0;
	#9	miso <= 0;
	#10 cpol <= 1;
		cpha <= 1;
	#1  go <= 1'b1;
		cpol <= 1;
		cpha <= 1;
	#1  go <= 1'b0;
	#9  miso <= 1;
	#10 	cpol <= 0;
	#1  go <= 1'b1;
		cpol <= 0;
	#1  go <= 1'b0; 
	#9 miso <= 0;

   #(DURATION) $display("End of simulation");
  $finish;
end

endmodule