data/full_repos/permissive/120749710/seg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/120749710/seg.v:69: Operator EQ expects 32 or 23 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 16 bits.\n                                                             : ... In instance seg\n  else if (cnt == mili-1)\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/120749710/seg.v:67: Operator EQ expects 32 or 23 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 16 bits.\n                                                             : ... In instance seg\n  else if(cnt == mili)\n              ^~\n%Error: Exiting due to 2 warning(s)\n'
module seg(
	input clk, 
	input rst_n, 
	input [31:0] q_a,
	output reg [2:0] sel,
	output wire [6:0] segment
	);
	localparam mili = 50_000_00 / 1000;
	reg [15:0] cnt;
	reg en;
	reg [3:0] tmp;
	initial sel = 3'b000;
	encode encode1(tmp,segment);
	always@(posedge clk or negedge rst_n)
	begin
		if (~rst_n)
			cnt <= 16'h0000;
		else if(cnt == mili)
		cnt = 16'h0000;
		else if (cnt == mili-1)
		begin
			if (sel != 3'b111)
				sel <= sel + 1;
			else
				sel <= 3'b000;
			cnt <= cnt+1;
		end
		else
			cnt <= cnt+1;
	end
	always@(*)
	begin
		case (sel)
			3'b000: tmp = q_a[3:0];
			3'b001: tmp = q_a[7:4];
			3'b010: tmp = q_a[11:8];
			3'b011: tmp = q_a[15:12];
			3'b100: tmp = q_a[19:16];
			3'b101: tmp = q_a[23:20];
			3'b110: tmp = q_a[27:24];
			3'b111: tmp = q_a[31:28];
		endcase
	end
	endmodule
module seg(
	input clk, 
	input rst_n, 
	input [31:0] q_a,
	output reg [2:0] sel,
	output wire [6:0] segment
	);

	localparam mili = 50_000_00 / 1000;
	reg [15:0] cnt;
	reg en;
	reg [3:0] tmp;
	initial sel = 3'b000;
	encode encode1(tmp,segment);
	always@(posedge clk or negedge rst_n)
	begin
		if (~rst_n)
			cnt <= 16'h0000;
		else if(cnt == mili)
		cnt = 16'h0000;
		else if (cnt == mili-1)
		begin
			if (sel != 3'b111)
				sel <= sel + 1;
			else
				sel <= 3'b000;
			cnt <= cnt+1;
		end
		else
			cnt <= cnt+1;
	end
	always@(*)
	begin
		case (sel)
			3'b000: tmp = q_a[3:0];
			3'b001: tmp = q_a[7:4];
			3'b010: tmp = q_a[11:8];
			3'b011: tmp = q_a[15:12];
			3'b100: tmp = q_a[19:16];
			3'b101: tmp = q_a[23:20];
			3'b110: tmp = q_a[27:24];
			3'b111: tmp = q_a[31:28];
		endcase
	end
	endmodule