data/full_repos/permissive/210918583/boards/tf530r2/tf530r2_ram_top.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/210918583/boards/tf530r2/tf530r2_ram_top.v:119: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'tf530r2_ram_top\'\nmodule tf530r2_ram_top(\n       ^~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'intreqr\'\nmodule intreqr(\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/210918583/boards/tf530r2/tf530r2_ram_top.v:112: Signal definition not found, creating implicitly: \'IDEWAIT_INT\'\n                                                                                            : ... Suggested alternative: \'IDEWAIT\'\nassign IDEWAIT = IDEWAIT_INT ? 1\'b1 : 1\'b0;\n                 ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/210918583/boards/tf530r2/tf530r2_ram_top.v:113: Signal definition not found, creating implicitly: \'INT2_INT\'\nassign INT2 = INT2_INT ? 1\'bz : 1\'b0;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/210918583/boards/tf530r2/tf530r2_ram_top.v:72: Cannot find file containing module: \'ram_top\'\n ram_top RAMTOP (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210918583/boards/tf530r2,data/full_repos/permissive/210918583/ram_top\n             data/full_repos/permissive/210918583/boards/tf530r2,data/full_repos/permissive/210918583/ram_top.v\n             data/full_repos/permissive/210918583/boards/tf530r2,data/full_repos/permissive/210918583/ram_top.sv\n             ram_top\n             ram_top.v\n             ram_top.sv\n             obj_dir/ram_top\n             obj_dir/ram_top.v\n             obj_dir/ram_top.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module tf530r2_ram_top(

        input   CLKCPU,
        input	RESET,

        input	[23:0] A,
        inout	[7:0] D,
        input   [1:0] SIZ,
        
        input   IDEINT,
        output  IDEWAIT,
        output  INT2,
        
        input   AS20,
        input   RW20,
        input   DS20,
        

        input   CBREQ,
        output  CBACK,
        output  CIIN,
        output 	STERM,	


        output  INTCYCLE,
                

        output [3:0] RAMCS,
        output RAMOE,


        output          SPI_CLK,
        output [1:0]    SPI_CS,
        input	        SPI_MISO,
        output          SPI_MOSI

       );

wire [15:0] DATA_BUS;

assign D[7:0] = {DATA_BUS[15:8]};

wire [23:0] ADDRESS_MAP;

assign ADDRESS_MAP[6:0] = A[6:0];
assign ADDRESS_MAP[23:15] = {A[23:15]};
assign ADDRESS_MAP[13:12] = {A[13:12]};


	ram_top RAMTOP (

		.CLKCPU ( CLKCPU    ), 
		.RESET  ( RESET     ), 
		
        .AS20   ( AS20      ), 
		.RW20   ( RW20      ), 
		.DS20   ( DS20      ),
        
        .A      ( ADDRESS_MAP ), 
		.D      ( DATA_BUS  ), 
		.SIZ    ( SIZ       ),


		.IDEINT ( IDEINT    ), 
		.IDEWAIT( IDEWAIT_INT   ), 
		.INT2   ( INT2_INT      ), 
		 
		.CBREQ  ( 1'b1      ), 

		.CIIN   ( CIIN      ), 
		.STERM  ( STERM     ), 

		.INTCYCLE(INTCYCLE), 

		.DTACK  ( 1'b1      ),

		.RAMCS  ( RAMCS     ), 
		.RAMOE  ( RAMOE     ), 
		



		.SPI_CLK( SPI_CLK   ), 
		.SPI_CS ( SPI_CS    ), 

		.SPI_MISO(SPI_MISO), 
		.SPI_MOSI(SPI_MOSI)
	);

assign IDEWAIT = IDEWAIT_INT ? 1'b1 : 1'b0;
assign INT2 = INT2_INT ? 1'bz : 1'b0;
assign CBACK = 1'b1;

endmodule
module tf530r2_ram_top(

        input   CLKCPU,
        input	RESET,

        input	[23:0] A,
        inout	[7:0] D,
        input   [1:0] SIZ,
        
        input   IDEINT,
        output  IDEWAIT,
        output  INT2,
        
        input   AS20,
        input   RW20,
        input   DS20,
        

        input   CBREQ,
        output  CBACK,
        output  CIIN,
        output 	STERM,	


        output  INTCYCLE,
                

        output [3:0] RAMCS,
        output RAMOE,


        output          SPI_CLK,
        output [1:0]    SPI_CS,
        input	        SPI_MISO,
        output          SPI_MOSI

       );


wire [15:0] DATA_BUS;

assign D[7:0] = {DATA_BUS[15:8]};

wire [23:0] ADDRESS_MAP;

assign ADDRESS_MAP[6:0] = A[6:0];
assign ADDRESS_MAP[23:15] = {A[23:15]};
assign ADDRESS_MAP[13:12] = {A[13:12]};


	ram_top RAMTOP (

		.CLKCPU ( CLKCPU    ), 
		.RESET  ( RESET     ), 
		
        .AS20   ( AS20      ), 
		.RW20   ( RW20      ), 
		.DS20   ( DS20      ),
        
        .A      ( ADDRESS_MAP ), 
		.D      ( DATA_BUS  ), 
		.SIZ    ( SIZ       ),


		.IDEINT ( IDEINT    ), 
		.IDEWAIT( IDEWAIT_INT   ), 
		.INT2   ( INT2_INT      ), 
		 
		.CBREQ  ( 1'b1      ), 

		.CIIN   ( CIIN      ), 
		.STERM  ( STERM     ), 

		.INTCYCLE(INTCYCLE), 

		.DTACK  ( 1'b1      ),

		.RAMCS  ( RAMCS     ), 
		.RAMOE  ( RAMOE     ), 
		



		.SPI_CLK( SPI_CLK   ), 
		.SPI_CS ( SPI_CS    ), 

		.SPI_MISO(SPI_MISO), 
		.SPI_MOSI(SPI_MOSI)
	);

assign IDEWAIT = IDEWAIT_INT ? 1'b1 : 1'b0;
assign INT2 = INT2_INT ? 1'bz : 1'b0;
assign CBACK = 1'b1;

endmodule