data/full_repos/permissive/205673649/MIPS/Simulacion/tb_top_mips.v
 line:168: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_top_mips.v:168: Unsupported: Ignoring delay on this delayed statement.\n    #150 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_top_mips.v:171: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 i_clk2=~i_clk2;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_top_mips.v:235: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                      : ... In instance tb_top_mips\n        cuentita <= 2\'b0;\n                 ^~\n%Error: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_top_mips.v:271: Cannot find file containing module: \'tl_instruction_fetch\'\ntl_instruction_fetch\n^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_instruction_fetch\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_instruction_fetch.v\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_instruction_fetch.sv\n             tl_instruction_fetch\n             tl_instruction_fetch.v\n             tl_instruction_fetch.sv\n             obj_dir/tl_instruction_fetch\n             obj_dir/tl_instruction_fetch.v\n             obj_dir/tl_instruction_fetch.sv\n%Error: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_top_mips.v:295: Cannot find file containing module: \'tl_instruction_decode\'\ntl_instruction_decode\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_top_mips.v:335: Cannot find file containing module: \'tl_execute\'\ntl_execute\n^~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_top_mips.v:374: Cannot find file containing module: \'tl_memory\'\ntl_memory\n^~~~~~~~~\n%Error: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_top_mips.v:400: Cannot find file containing module: \'tl_write_back\'\ntl_write_back\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_top_mips.v:418: Cannot find file containing module: \'unidad_cortocircuito\'\nunidad_cortocircuito\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top_mips();
`define LEN 32
`define CANTIDAD_REGISTROS 32
`define NB_ADDRESS_REGISTROS $clog2(CANTIDAD_REGISTROS)
`define NB_SIGN_EXTEND  16
`define NB_INSTRUCCION  6
`define NB_ALU_CONTROL  4       
`define NB_ALU_OP  2
`define INIT_FILE_IM ""
            if(error2!=1) 
                $stop;
            else
                enable_mode<=cable_enable_mode;
        end
    end
end

always @(negedge i_clk2)
begin
    if(!i_rst)
    begin
        cant_clock <= 32'b0;
        cuentita <= 2'b0;
        flag <= 1'b0;
    end
    else
    begin
        if(enable_mode==1'b1)
        begin
            if(flag_halt && flag!=1'b1)
            begin
                cuentita<= cuentita + 1'b1;
            end
            else
                cuentita <= cuentita;
            
            if(cuentita >= 3'b100)
            begin
                cant_clock<= cant_clock;
                flag <= 1'b1;
            end
            else
            begin
                cant_clock<= cant_clock + 1'b1;
                flag <= flag;
            end
        end
        else
        begin
            cuentita <= cuentita;
            cant_clock <= cant_clock;
            flag <= flag;
        end
    end
end



tl_instruction_fetch
#(
    .LEN(LEN),
    .INIT_FILE_IM(INIT_FILE_IM)
)
    u_tl_instruction_fetch
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_branch_dir(branch_dir),
    .i_PCSrc(PCSrc),
    .i_flag_stall(flag_stall),
    .i_flag_jump(flag_jump),
    .i_dir_jump(dir_jump),
    .i_dir_mem_instr(dir_mem_instr),
    .i_wea_mem_instr(wea_mem_instr),
    .i_addr_mem_inst(cont),
    .o_instruccion(instruccion),
    .o_adder(out_adder_if_id),
    .o_contador_programa(contador_programa),
    .o_flag_halt(flag_halt)
);


tl_instruction_decode
#(
    .LEN(LEN),
    .CANTIDAD_REGISTROS(CANTIDAD_REGISTROS),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_SIGN_EXTEND(NB_SIGN_EXTEND),
    .NB_INSTRUCCION(NB_INSTRUCCION),    
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_CTRL_EX(NB_CTRL_EX),
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_ALU_OP(NB_ALU_OP)
)
    u_tl_instruction_decode
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_instruccion(instruccion),
    .i_write_data(write_data_banco_reg),
    .i_write_reg(write_reg_wb_id),
    .i_adder_pc(out_adder_if_id),
    .i_RegWrite(regwrite_wb_id),
    .i_flush(PCSrc), 
    .o_adder_pc(out_adder_id_ex), 
    .o_rs(rs),
    .o_rd(rd),
    .o_rt(rt),    
    .o_shamt(shamt),   
    .o_dato1(dato1),
    .o_dato2(dato2_if_ex),
    .o_sign_extend(sign_extend),
    .o_ctrl_wb(ctrl_wb_id_ex),
    .o_ctrl_mem(ctrl_mem_id_ex),
    .o_ctrl_ex(ctrl_ex_id_ex),
    .o_flag_stall(flag_stall),
    .o_dir_jump(dir_jump),
    .o_flag_jump(flag_jump)
);


tl_execute
#(
    .LEN(LEN),
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_CTRL_EX(NB_CTRL_EX)
    
)
    u_tl_execute
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_adder_id(out_adder_id_ex),
    .i_dato1(dato1),
    .i_dato2(dato2_if_ex),
    .i_sign_extend(sign_extend),
    .i_ctrl_wb(ctrl_wb_id_ex),
    .i_ctrl_mem(ctrl_mem_id_ex),
    .i_ctrl_ex(ctrl_ex_id_ex),
    .i_rd(rd),
    .i_rt(rt),
    .i_shamt(shamt),
    .i_ctrl_muxA_corto(ctrl_muxA_corto),
    .i_ctrl_muxB_corto(ctrl_muxB_corto),
    .i_rd_mem_corto(result_alu_ex_mem),
    .i_rd_wb_corto(write_data_banco_reg),
    .i_flush(PCSrc),
    .o_alu_zero(alu_zero),
    .o_write_reg(write_reg_ex_mem),
    .o_ctrl_wb(ctrl_wb_ex_mem),
    .o_ctrl_mem(ctrl_mem_ex_mem),
    .o_pc_branch(branch_dir),
    .o_alu_result(result_alu_ex_mem),
    .o_dato2(dato2_ex_mem)
);


tl_memory
#(
    .LEN(LEN),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)

)
    u_tl_memory
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_address(result_alu_ex_mem),
    .i_write_data(dato2_ex_mem),
    .i_ctrl_wb(ctrl_wb_ex_mem),
    .i_ctrl_mem(ctrl_mem_ex_mem),
    .i_alu_zero(alu_zero),
    .i_write_reg(write_reg_ex_mem),
    .o_address(result_alu_mem_wb),  
    .o_read_data(read_data_memory),
    .o_write_reg(write_reg_mem_wb),
    .o_ctrl_wb(ctrl_wb_mem_wb),
    .o_PCSrc(PCSrc)
);


tl_write_back
#(
    .LEN(LEN),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)
  
)
    u_tl_write_back
(
    .i_read_data(read_data_memory),
    .i_result_alu(result_alu_mem_wb),
    .i_ctrl_wb(ctrl_wb_mem_wb),
    .i_write_reg(write_reg_mem_wb),
    .o_write_data(write_data_banco_reg),
    .o_write_reg(write_reg_wb_id),
    .o_RegWrite(regwrite_wb_id)
);

unidad_cortocircuito
#(
    .LEN(LEN),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)
)
u_unidad_corto
(
   .i_rs_id_ex(rs),
   .i_rt_id_ex(rt),
   .i_write_reg_ex_mem(write_reg_ex_mem),
   .i_write_reg_mem_wb(write_reg_wb_id), 
   .i_reg_write_ex_mem(ctrl_wb_ex_mem[1]),
   .i_reg_write_mem_wb(regwrite_wb_id),
   .o_muxA_alu(ctrl_muxA_corto),
   .o_muxB_alu(ctrl_muxB_corto)
);


assign o_if_id = {
                  contador_programa,
                  instruccion,

                  flag_halt};

assign o_id_ex = { 

                   ctrl_wb_id_ex,
                   ctrl_mem_id_ex,
                   ctrl_ex_id_ex,

                   shamt,
                   rs,
                   rt,
                   rd,
                   out_adder_id_ex,
                   dir_jump,
                   sign_extend,
                   dato1,
                   dato2_if_ex,
                   flag_stall,
                   flag_jump
                  };   
                   
assign o_ex_mem = {

                   ctrl_wb_ex_mem,
                   ctrl_mem_ex_mem,
                   write_reg_ex_mem,
                   branch_dir,
                   result_alu_ex_mem,
                   dato2_ex_mem
                   };

assign o_mem_wb = {

                   PCSrc,
                   ctrl_wb_mem_wb,
                   write_reg_mem_wb,
                   result_alu_mem_wb,
                   read_data_memory
                   };


endmodule
module tb_top_mips();

`define LEN 32
`define CANTIDAD_REGISTROS 32
`define NB_ADDRESS_REGISTROS $clog2(CANTIDAD_REGISTROS)
`define NB_SIGN_EXTEND  16
`define NB_INSTRUCCION  6
`define NB_ALU_CONTROL  4       
`define NB_ALU_OP  2
`define INIT_FILE_IM ""
            if(error2!=1) 
                $stop;
            else
                enable_mode<=cable_enable_mode;
        end
    end
end

always @(negedge i_clk2)
begin
    if(!i_rst)
    begin
        cant_clock <= 32'b0;
        cuentita <= 2'b0;
        flag <= 1'b0;
    end
    else
    begin
        if(enable_mode==1'b1)
        begin
            if(flag_halt && flag!=1'b1)
            begin
                cuentita<= cuentita + 1'b1;
            end
            else
                cuentita <= cuentita;
            
            if(cuentita >= 3'b100)
            begin
                cant_clock<= cant_clock;
                flag <= 1'b1;
            end
            else
            begin
                cant_clock<= cant_clock + 1'b1;
                flag <= flag;
            end
        end
        else
        begin
            cuentita <= cuentita;
            cant_clock <= cant_clock;
            flag <= flag;
        end
    end
end



tl_instruction_fetch
#(
    .LEN(LEN),
    .INIT_FILE_IM(INIT_FILE_IM)
)
    u_tl_instruction_fetch
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_branch_dir(branch_dir),
    .i_PCSrc(PCSrc),
    .i_flag_stall(flag_stall),
    .i_flag_jump(flag_jump),
    .i_dir_jump(dir_jump),
    .i_dir_mem_instr(dir_mem_instr),
    .i_wea_mem_instr(wea_mem_instr),
    .i_addr_mem_inst(cont),
    .o_instruccion(instruccion),
    .o_adder(out_adder_if_id),
    .o_contador_programa(contador_programa),
    .o_flag_halt(flag_halt)
);


tl_instruction_decode
#(
    .LEN(LEN),
    .CANTIDAD_REGISTROS(CANTIDAD_REGISTROS),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_SIGN_EXTEND(NB_SIGN_EXTEND),
    .NB_INSTRUCCION(NB_INSTRUCCION),    
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_CTRL_EX(NB_CTRL_EX),
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_ALU_OP(NB_ALU_OP)
)
    u_tl_instruction_decode
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_instruccion(instruccion),
    .i_write_data(write_data_banco_reg),
    .i_write_reg(write_reg_wb_id),
    .i_adder_pc(out_adder_if_id),
    .i_RegWrite(regwrite_wb_id),
    .i_flush(PCSrc), 
    .o_adder_pc(out_adder_id_ex), 
    .o_rs(rs),
    .o_rd(rd),
    .o_rt(rt),    
    .o_shamt(shamt),   
    .o_dato1(dato1),
    .o_dato2(dato2_if_ex),
    .o_sign_extend(sign_extend),
    .o_ctrl_wb(ctrl_wb_id_ex),
    .o_ctrl_mem(ctrl_mem_id_ex),
    .o_ctrl_ex(ctrl_ex_id_ex),
    .o_flag_stall(flag_stall),
    .o_dir_jump(dir_jump),
    .o_flag_jump(flag_jump)
);


tl_execute
#(
    .LEN(LEN),
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_CTRL_EX(NB_CTRL_EX)
    
)
    u_tl_execute
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_adder_id(out_adder_id_ex),
    .i_dato1(dato1),
    .i_dato2(dato2_if_ex),
    .i_sign_extend(sign_extend),
    .i_ctrl_wb(ctrl_wb_id_ex),
    .i_ctrl_mem(ctrl_mem_id_ex),
    .i_ctrl_ex(ctrl_ex_id_ex),
    .i_rd(rd),
    .i_rt(rt),
    .i_shamt(shamt),
    .i_ctrl_muxA_corto(ctrl_muxA_corto),
    .i_ctrl_muxB_corto(ctrl_muxB_corto),
    .i_rd_mem_corto(result_alu_ex_mem),
    .i_rd_wb_corto(write_data_banco_reg),
    .i_flush(PCSrc),
    .o_alu_zero(alu_zero),
    .o_write_reg(write_reg_ex_mem),
    .o_ctrl_wb(ctrl_wb_ex_mem),
    .o_ctrl_mem(ctrl_mem_ex_mem),
    .o_pc_branch(branch_dir),
    .o_alu_result(result_alu_ex_mem),
    .o_dato2(dato2_ex_mem)
);


tl_memory
#(
    .LEN(LEN),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)

)
    u_tl_memory
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_address(result_alu_ex_mem),
    .i_write_data(dato2_ex_mem),
    .i_ctrl_wb(ctrl_wb_ex_mem),
    .i_ctrl_mem(ctrl_mem_ex_mem),
    .i_alu_zero(alu_zero),
    .i_write_reg(write_reg_ex_mem),
    .o_address(result_alu_mem_wb),  
    .o_read_data(read_data_memory),
    .o_write_reg(write_reg_mem_wb),
    .o_ctrl_wb(ctrl_wb_mem_wb),
    .o_PCSrc(PCSrc)
);


tl_write_back
#(
    .LEN(LEN),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)
  
)
    u_tl_write_back
(
    .i_read_data(read_data_memory),
    .i_result_alu(result_alu_mem_wb),
    .i_ctrl_wb(ctrl_wb_mem_wb),
    .i_write_reg(write_reg_mem_wb),
    .o_write_data(write_data_banco_reg),
    .o_write_reg(write_reg_wb_id),
    .o_RegWrite(regwrite_wb_id)
);

unidad_cortocircuito
#(
    .LEN(LEN),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)
)
u_unidad_corto
(
   .i_rs_id_ex(rs),
   .i_rt_id_ex(rt),
   .i_write_reg_ex_mem(write_reg_ex_mem),
   .i_write_reg_mem_wb(write_reg_wb_id), 
   .i_reg_write_ex_mem(ctrl_wb_ex_mem[1]),
   .i_reg_write_mem_wb(regwrite_wb_id),
   .o_muxA_alu(ctrl_muxA_corto),
   .o_muxB_alu(ctrl_muxB_corto)
);


assign o_if_id = {
                  contador_programa,
                  instruccion,

                  flag_halt};

assign o_id_ex = { 

                   ctrl_wb_id_ex,
                   ctrl_mem_id_ex,
                   ctrl_ex_id_ex,

                   shamt,
                   rs,
                   rt,
                   rd,
                   out_adder_id_ex,
                   dir_jump,
                   sign_extend,
                   dato1,
                   dato2_if_ex,
                   flag_stall,
                   flag_jump
                  };   
                   
assign o_ex_mem = {

                   ctrl_wb_ex_mem,
                   ctrl_mem_ex_mem,
                   write_reg_ex_mem,
                   branch_dir,
                   result_alu_ex_mem,
                   dato2_ex_mem
                   };

assign o_mem_wb = {

                   PCSrc,
                   ctrl_wb_mem_wb,
                   write_reg_mem_wb,
                   result_alu_mem_wb,
                   read_data_memory
                   };


endmodule