data/full_repos/permissive/165110048/assets/VGAdemo/Top.v
1: b'%Error: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:51: Cannot find file containing module: \'AntiJitter\'\n AntiJitter #(4) a0[15:0](.clk(clkdiv[15]), .I(SW), .O(SW_OK));\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165110048/assets/VGAdemo,data/full_repos/permissive/165110048/AntiJitter\n             data/full_repos/permissive/165110048/assets/VGAdemo,data/full_repos/permissive/165110048/AntiJitter.v\n             data/full_repos/permissive/165110048/assets/VGAdemo,data/full_repos/permissive/165110048/AntiJitter.sv\n             AntiJitter\n             AntiJitter.v\n             AntiJitter.sv\n             obj_dir/AntiJitter\n             obj_dir/AntiJitter.v\n             obj_dir/AntiJitter.sv\n%Error: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:55: Cannot find file containing module: \'Keypad\'\n Keypad k0 (.clk(clkdiv[15]), .keyX(BTN_Y), .keyY(BTN_X), .keyCode(keyCode), .ready(keyReady));\n ^~~~~~\n%Error: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:59: Cannot find file containing module: \'Seg7Device\'\n   Seg7Device segDevice(.clkIO(clkdiv[3]), .clkScan(clkdiv[15:14]), .clkBlink(clkdiv[25]),\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:76: Cannot find file containing module: \'vgac\'\n vgac v0 (\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:103: Operator SUB expects 20 bits on the LHS, but LHS\'s VARREF \'x\' generates 10 bits.\n                                                                             : ... In instance Top\n assign x_sqr = (x - col_addr) * (x - col_addr);\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:103: Operator SUB expects 20 bits on the RHS, but RHS\'s VARREF \'col_addr\' generates 10 bits.\n                                                                             : ... In instance Top\n assign x_sqr = (x - col_addr) * (x - col_addr);\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:103: Operator SUB expects 20 bits on the LHS, but LHS\'s VARREF \'x\' generates 10 bits.\n                                                                             : ... In instance Top\n assign x_sqr = (x - col_addr) * (x - col_addr);\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:103: Operator SUB expects 20 bits on the RHS, but RHS\'s VARREF \'col_addr\' generates 10 bits.\n                                                                             : ... In instance Top\n assign x_sqr = (x - col_addr) * (x - col_addr);\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:104: Operator SUB expects 20 bits on the LHS, but LHS\'s VARREF \'y\' generates 9 bits.\n                                                                             : ... In instance Top\n assign y_sqr = (y - row_addr) * (y - row_addr);\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:104: Operator SUB expects 20 bits on the RHS, but RHS\'s VARREF \'row_addr\' generates 9 bits.\n                                                                             : ... In instance Top\n assign y_sqr = (y - row_addr) * (y - row_addr);\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:104: Operator SUB expects 20 bits on the LHS, but LHS\'s VARREF \'y\' generates 9 bits.\n                                                                             : ... In instance Top\n assign y_sqr = (y - row_addr) * (y - row_addr);\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:104: Operator SUB expects 20 bits on the RHS, but RHS\'s VARREF \'row_addr\' generates 9 bits.\n                                                                             : ... In instance Top\n assign y_sqr = (y - row_addr) * (y - row_addr);\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:110: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 34 bits.\n                                                                             : ... In instance Top\n assign segTestData = {7\'b0,x,8\'b0,y};\n                    ^\n%Error: data/full_repos/permissive/165110048/assets/VGAdemo/Top.v:113: Cannot find file containing module: \'ShiftReg\'\n ShiftReg #(.WIDTH(16)) ledDevice (.clk(clkdiv[3]), .pdata(~ledData), .sout({LED_CLK,LED_DO,LED_PEN,LED_CLR}));\n ^~~~~~~~\n%Error: Exiting due to 5 error(s), 9 warning(s)\n'
module Top(
	input clk,
	input rstn,
	input [15:0]SW,
	output hs,
	output vs,
	output [3:0] r,
	output [3:0] g,
	output [3:0] b,
	output SEGLED_CLK,
	output SEGLED_CLR,
	output SEGLED_DO,
	output SEGLED_PEN,
   output LED_CLK,
	output LED_CLR,
	output LED_DO,
	output LED_PEN,
	inout [4:0]BTN_X,
	inout [3:0]BTN_Y,
	output buzzer
    );
	
	reg [31:0]clkdiv;
	always@(posedge clk) begin
		clkdiv <= clkdiv + 1'b1;
	end
	assign buzzer = 1'b1;
	wire [15:0] SW_OK;
	AntiJitter #(4) a0[15:0](.clk(clkdiv[15]), .I(SW), .O(SW_OK));
	
	wire [4:0] keyCode;
	wire keyReady;
	Keypad k0 (.clk(clkdiv[15]), .keyX(BTN_Y), .keyY(BTN_X), .keyCode(keyCode), .ready(keyReady));
	
	wire [31:0] segTestData;
	wire [3:0]sout;
   Seg7Device segDevice(.clkIO(clkdiv[3]), .clkScan(clkdiv[15:14]), .clkBlink(clkdiv[25]),
		.data(segTestData), .point(8'h0), .LES(8'h0),
		.sout(sout));
	assign SEGLED_CLK = sout[3];
	assign SEGLED_DO = sout[2];
	assign SEGLED_PEN = sout[1];
	assign SEGLED_CLR = sout[0];
 	
	
	reg [9:0] x;
	reg [8:0] y;
	
 	reg [11:0] vga_data;
 	wire [9:0] col_addr;
 	wire [8:0] row_addr;
	wire [19:0] x_sqr, y_sqr, r_sqr;
	
	vgac v0 (
		.vga_clk(clkdiv[1]), .clrn(SW_OK[0]), .d_in(vga_data), .row_addr(row_addr), .col_addr(col_addr), .hs(hs), .vs(vs)
	);
	reg wasReady;
	reg [9:0] radius = 10'd15;
	assign {r,g,b} = {12'h0};
	always @(posedge clk) begin
		if (!rstn) begin
			x <= 10'd320;
			y <= 9'd240;
			radius <= 10'd15;
		end else begin
			wasReady <= keyReady;
			if (!wasReady&&keyReady) begin
				case (keyCode)
					5'h10: radius <= radius - 10'd5;
					5'h12: radius <= radius + 10'd5;
					5'hc: x <= x - 10'd20;
					5'he: x <= x + 10'd20;
					5'h9: y <= y - 9'd20;
					5'h11: y <= y + 9'd20;
					default: ;
				endcase
			end
		end
	end
	
	assign x_sqr = (x - col_addr) * (x - col_addr);
	assign y_sqr = (y - row_addr) * (y - row_addr);
	assign r_sqr = radius * radius;
	
	always@(*)
	vga_data = 12'hfff;
	
	assign segTestData = {7'b0,x,8'b0,y};
	wire [15:0] ledData;
	assign ledData = SW_OK;
	ShiftReg #(.WIDTH(16)) ledDevice (.clk(clkdiv[3]), .pdata(~ledData), .sout({LED_CLK,LED_DO,LED_PEN,LED_CLR}));
endmodule
module Top(
	input clk,
	input rstn,
	input [15:0]SW,
	output hs,
	output vs,
	output [3:0] r,
	output [3:0] g,
	output [3:0] b,
	output SEGLED_CLK,
	output SEGLED_CLR,
	output SEGLED_DO,
	output SEGLED_PEN,
   output LED_CLK,
	output LED_CLR,
	output LED_DO,
	output LED_PEN,
	inout [4:0]BTN_X,
	inout [3:0]BTN_Y,
	output buzzer
    );

	
	reg [31:0]clkdiv;
	always@(posedge clk) begin
		clkdiv <= clkdiv + 1'b1;
	end
	assign buzzer = 1'b1;
	wire [15:0] SW_OK;
	AntiJitter #(4) a0[15:0](.clk(clkdiv[15]), .I(SW), .O(SW_OK));
	
	wire [4:0] keyCode;
	wire keyReady;
	Keypad k0 (.clk(clkdiv[15]), .keyX(BTN_Y), .keyY(BTN_X), .keyCode(keyCode), .ready(keyReady));
	
	wire [31:0] segTestData;
	wire [3:0]sout;
   Seg7Device segDevice(.clkIO(clkdiv[3]), .clkScan(clkdiv[15:14]), .clkBlink(clkdiv[25]),
		.data(segTestData), .point(8'h0), .LES(8'h0),
		.sout(sout));
	assign SEGLED_CLK = sout[3];
	assign SEGLED_DO = sout[2];
	assign SEGLED_PEN = sout[1];
	assign SEGLED_CLR = sout[0];
 	
	
	reg [9:0] x;
	reg [8:0] y;
	
 	reg [11:0] vga_data;
 	wire [9:0] col_addr;
 	wire [8:0] row_addr;
	wire [19:0] x_sqr, y_sqr, r_sqr;
	
	vgac v0 (
		.vga_clk(clkdiv[1]), .clrn(SW_OK[0]), .d_in(vga_data), .row_addr(row_addr), .col_addr(col_addr), .hs(hs), .vs(vs)
	);
	reg wasReady;
	reg [9:0] radius = 10'd15;
	assign {r,g,b} = {12'h0};
	always @(posedge clk) begin
		if (!rstn) begin
			x <= 10'd320;
			y <= 9'd240;
			radius <= 10'd15;
		end else begin
			wasReady <= keyReady;
			if (!wasReady&&keyReady) begin
				case (keyCode)
					5'h10: radius <= radius - 10'd5;
					5'h12: radius <= radius + 10'd5;
					5'hc: x <= x - 10'd20;
					5'he: x <= x + 10'd20;
					5'h9: y <= y - 9'd20;
					5'h11: y <= y + 9'd20;
					default: ;
				endcase
			end
		end
	end
	
	assign x_sqr = (x - col_addr) * (x - col_addr);
	assign y_sqr = (y - row_addr) * (y - row_addr);
	assign r_sqr = radius * radius;
	
	always@(*)
	vga_data = 12'hfff;
	
	assign segTestData = {7'b0,x,8'b0,y};
	wire [15:0] ledData;
	assign ledData = SW_OK;
	ShiftReg #(.WIDTH(16)) ledDevice (.clk(clkdiv[3]), .pdata(~ledData), .sout({LED_CLK,LED_DO,LED_PEN,LED_CLR}));
endmodule