data/full_repos/permissive/206842334/testbenches/sig_altmult_accum_tb.v
 line:24: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/sig_altmult_accum_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/sig_altmult_accum_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD/2) clock = ~clock;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/sig_altmult_accum_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD/2) clock = ~clock; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/sig_altmult_accum_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1 rst_n<=1\'bx;clk<=1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/sig_altmult_accum_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD*3) rst_n<=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/sig_altmult_accum_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD*3) rst_n<=0; clk<=0; clock <= 0; dataa <= 0; datab <= 0;\n    ^\n%Error: data/full_repos/permissive/206842334/testbenches/sig_altmult_accum_tb.v:31: Cannot find file containing module: \'sig_altmult_accum\'\nsig_altmult_accum mac(dataa, datab, clk, rst_n, clken, sload, adder_out);\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/sig_altmult_accum\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/sig_altmult_accum.v\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/sig_altmult_accum.sv\n             sig_altmult_accum\n             sig_altmult_accum.v\n             sig_altmult_accum.sv\n             obj_dir/sig_altmult_accum\n             obj_dir/sig_altmult_accum.v\n             obj_dir/sig_altmult_accum.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sig_altmult_accum_tb;

reg clk;
reg rst_n;

reg [7:0] dataa, datab;
reg clken, clock, sload;

localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;

wire signed [16:0] adder_out;
task run_clock;
    begin
        #(CLK_PERIOD/2) clock = ~clock;
        #(CLK_PERIOD/2) clock = ~clock; 
    end
endtask

initial begin
    #1 rst_n<=1'bx;clk<=1'bx;
    #(CLK_PERIOD*3) rst_n<=1;
    #(CLK_PERIOD*3) rst_n<=0; clk<=0; clock <= 0; dataa <= 0; datab <= 0;
    run_clock; clken <= 1; sload <= 0;
    run_clock; dataa <= 255; datab <= 128;
    run_clock; dataa <= 55;  datab <= 127;
    run_clock; dataa <= 135; datab <= 128;
    run_clock;
end

sig_altmult_accum mac(dataa, datab, clk, rst_n, clken, sload, adder_out);

endmodule
module sig_altmult_accum_tb;


reg clk;
reg rst_n;

reg [7:0] dataa, datab;
reg clken, clock, sload;

localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;

wire signed [16:0] adder_out;
task run_clock;
    begin
        #(CLK_PERIOD/2) clock = ~clock;
        #(CLK_PERIOD/2) clock = ~clock; 
    end
endtask

initial begin
    #1 rst_n<=1'bx;clk<=1'bx;
    #(CLK_PERIOD*3) rst_n<=1;
    #(CLK_PERIOD*3) rst_n<=0; clk<=0; clock <= 0; dataa <= 0; datab <= 0;
    run_clock; clken <= 1; sload <= 0;
    run_clock; dataa <= 255; datab <= 128;
    run_clock; dataa <= 55;  datab <= 127;
    run_clock; dataa <= 135; datab <= 128;
    run_clock;
end

sig_altmult_accum mac(dataa, datab, clk, rst_n, clken, sload, adder_out);

endmodule