data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup/uart_fifo.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup/uart_fifo.v:80: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup,data/full_repos/permissive/17099167/timescale.v\n             data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup,data/full_repos/permissive/17099167/timescale.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup,data/full_repos/permissive/17099167/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup/uart_fifo.v:81: Cannot find include file: uart_defines.v\n`include "uart_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup/uart_fifo.v:99: Define or directive not defined: \'`UART_FIFO_WIDTH\'\nparameter fifo_width = `UART_FIFO_WIDTH;\n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup/uart_fifo.v:99: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter fifo_width = `UART_FIFO_WIDTH;\n                                       ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup/uart_fifo.v:100: Define or directive not defined: \'`UART_FIFO_DEPTH\'\nparameter fifo_depth = `UART_FIFO_DEPTH;\n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup/uart_fifo.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter fifo_depth = `UART_FIFO_DEPTH;\n                                       ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup/uart_fifo.v:101: Define or directive not defined: \'`UART_FIFO_POINTER_W\'\nparameter fifo_pointer_w = `UART_FIFO_POINTER_W;\n                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup/uart_fifo.v:101: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter fifo_pointer_w = `UART_FIFO_POINTER_W;\n                                               ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup/uart_fifo.v:102: Define or directive not defined: \'`UART_FIFO_COUNTER_W\'\nparameter fifo_counter_w = `UART_FIFO_COUNTER_W;\n                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/rtl/verilog-backup/uart_fifo.v:102: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter fifo_counter_w = `UART_FIFO_COUNTER_W;\n                                               ^\n%Error: Exiting due to 10 error(s)\n'
module uart_fifo (clk, 
	wb_rst_i, data_in, data_out,

	push,
	pop,

	underrun,
	overrun,
	count,
	error_bit,
	fifo_reset,
	reset_status
	);



parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;

input				clk;
input				wb_rst_i;
input				push;
input				pop;
input	[fifo_width-1:0]	data_in;
input				fifo_reset;
input       reset_status;

output	[fifo_width-1:0]	data_out;
output				overrun;
output				underrun;
output	[fifo_counter_w-1:0]	count;
output				error_bit;

wire	[fifo_width-1:0]	data_out;


reg	[fifo_width-1:0]	fifo[fifo_depth-1:0];


reg	[fifo_pointer_w-1:0]	top;
reg	[fifo_pointer_w-1:0]	bottom;

reg	[fifo_counter_w-1:0]	count;
reg				overrun;
reg				underrun;





reg				push_delay; 
reg				pop_delay;

wire				push_rise = push_delay & push;
wire				pop_rise  = pop_delay  & pop;

wire [fifo_pointer_w-1:0] top_plus_1 = top + 1;

always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		push_delay <= #1 1'b0;
	else
		push_delay <= #1 ~push;
end

always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		pop_delay <= #1 1'b0;
	else
		pop_delay <= #1 ~pop;
end


always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
	begin
		top		<= #1 0;

		bottom		<= #1 1'b0;
		underrun	<= #1 1'b0;
		overrun		<= #1 1'b0;
		count		<= #1 0;
		fifo[0]		<= #1 0;
		fifo[1]		<= #1 0;
		fifo[2]		<= #1 0;
		fifo[3]		<= #1 0;
		fifo[4]		<= #1 0;
		fifo[5]		<= #1 0;
		fifo[6]		<= #1 0;
		fifo[7]		<= #1 0;
		fifo[8]		<= #1 0;
		fifo[9]		<= #1 0;
		fifo[10]	<= #1 0;
		fifo[11]	<= #1 0;
		fifo[12]	<= #1 0;
		fifo[13]	<= #1 0;
		fifo[14]	<= #1 0;
		fifo[15]	<= #1 0;
	end
	else
	if (fifo_reset) begin
		top		<= #1 0;

		bottom		<= #1 1'b0;
		underrun	<= #1 1'b0;
		overrun		<= #1 1'b0;
		count		<= #1 0;
	end
  else
  if(reset_status)
    begin
  		underrun	<= #1 1'b0;
  		overrun		<= #1 1'b0;
    end
	else
	begin
		case ({push_rise, pop_rise})
		2'b00 : begin
				underrun <= #1 1'b0;

	 	        end
		2'b10 : if (count==fifo_depth)
			begin
				overrun   <= #1 1'b1;
				underrun  <= #1 1'b0;
			end
			else
			begin
				top       <= #1 top_plus_1;

				fifo[top] <= #1 data_in;

				overrun   <= #1 0;
				count     <= #1 count + 1;
			end
		2'b01 : if (~|count)
			begin

				overrun  <= #1 1'b0;
			end
			else
			begin
				bottom   <= #1 bottom + 1;

				overrun  <= #1 1'b0;
				count	 <= #1 count - 1;
			end
		2'b11 : begin
				bottom   <= #1 bottom + 1;
				top       <= #1 top_plus_1;

				fifo[top] <= #1 data_in;
				underrun <= #1 1'b0;

		        end
		endcase
	end

end


assign data_out = fifo[bottom];




wire	[fifo_width-1:0]	word0 = fifo[0];
wire	[fifo_width-1:0]	word1 = fifo[1];
wire	[fifo_width-1:0]	word2 = fifo[2];
wire	[fifo_width-1:0]	word3 = fifo[3];
wire	[fifo_width-1:0]	word4 = fifo[4];
wire	[fifo_width-1:0]	word5 = fifo[5];
wire	[fifo_width-1:0]	word6 = fifo[6];
wire	[fifo_width-1:0]	word7 = fifo[7];

wire	[fifo_width-1:0]	word8 = fifo[8];
wire	[fifo_width-1:0]	word9 = fifo[9];
wire	[fifo_width-1:0]	word10 = fifo[10];
wire	[fifo_width-1:0]	word11 = fifo[11];
wire	[fifo_width-1:0]	word12 = fifo[12];
wire	[fifo_width-1:0]	word13 = fifo[13];
wire	[fifo_width-1:0]	word14 = fifo[14];
wire	[fifo_width-1:0]	word15 = fifo[15];


assign	error_bit = |(word0[1:0]  | word1[1:0]  | word2[1:0]  | word3[1:0]  |
            		      word4[1:0]  | word5[1:0]  | word6[1:0]  | word7[1:0]  |
            		      word8[1:0]  | word9[1:0]  | word10[1:0] | word11[1:0] |
            		      word12[1:0] | word13[1:0] | word14[1:0] | word15[1:0] );

endmodule
module uart_fifo (clk, 
	wb_rst_i, data_in, data_out,

	push,
	pop,

	underrun,
	overrun,
	count,
	error_bit,
	fifo_reset,
	reset_status
	);




parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;

input				clk;
input				wb_rst_i;
input				push;
input				pop;
input	[fifo_width-1:0]	data_in;
input				fifo_reset;
input       reset_status;

output	[fifo_width-1:0]	data_out;
output				overrun;
output				underrun;
output	[fifo_counter_w-1:0]	count;
output				error_bit;

wire	[fifo_width-1:0]	data_out;


reg	[fifo_width-1:0]	fifo[fifo_depth-1:0];


reg	[fifo_pointer_w-1:0]	top;
reg	[fifo_pointer_w-1:0]	bottom;

reg	[fifo_counter_w-1:0]	count;
reg				overrun;
reg				underrun;





reg				push_delay; 
reg				pop_delay;

wire				push_rise = push_delay & push;
wire				pop_rise  = pop_delay  & pop;

wire [fifo_pointer_w-1:0] top_plus_1 = top + 1;

always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		push_delay <= #1 1'b0;
	else
		push_delay <= #1 ~push;
end

always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		pop_delay <= #1 1'b0;
	else
		pop_delay <= #1 ~pop;
end


always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
	begin
		top		<= #1 0;

		bottom		<= #1 1'b0;
		underrun	<= #1 1'b0;
		overrun		<= #1 1'b0;
		count		<= #1 0;
		fifo[0]		<= #1 0;
		fifo[1]		<= #1 0;
		fifo[2]		<= #1 0;
		fifo[3]		<= #1 0;
		fifo[4]		<= #1 0;
		fifo[5]		<= #1 0;
		fifo[6]		<= #1 0;
		fifo[7]		<= #1 0;
		fifo[8]		<= #1 0;
		fifo[9]		<= #1 0;
		fifo[10]	<= #1 0;
		fifo[11]	<= #1 0;
		fifo[12]	<= #1 0;
		fifo[13]	<= #1 0;
		fifo[14]	<= #1 0;
		fifo[15]	<= #1 0;
	end
	else
	if (fifo_reset) begin
		top		<= #1 0;

		bottom		<= #1 1'b0;
		underrun	<= #1 1'b0;
		overrun		<= #1 1'b0;
		count		<= #1 0;
	end
  else
  if(reset_status)
    begin
  		underrun	<= #1 1'b0;
  		overrun		<= #1 1'b0;
    end
	else
	begin
		case ({push_rise, pop_rise})
		2'b00 : begin
				underrun <= #1 1'b0;

	 	        end
		2'b10 : if (count==fifo_depth)
			begin
				overrun   <= #1 1'b1;
				underrun  <= #1 1'b0;
			end
			else
			begin
				top       <= #1 top_plus_1;

				fifo[top] <= #1 data_in;

				overrun   <= #1 0;
				count     <= #1 count + 1;
			end
		2'b01 : if (~|count)
			begin

				overrun  <= #1 1'b0;
			end
			else
			begin
				bottom   <= #1 bottom + 1;

				overrun  <= #1 1'b0;
				count	 <= #1 count - 1;
			end
		2'b11 : begin
				bottom   <= #1 bottom + 1;
				top       <= #1 top_plus_1;

				fifo[top] <= #1 data_in;
				underrun <= #1 1'b0;

		        end
		endcase
	end

end


assign data_out = fifo[bottom];




wire	[fifo_width-1:0]	word0 = fifo[0];
wire	[fifo_width-1:0]	word1 = fifo[1];
wire	[fifo_width-1:0]	word2 = fifo[2];
wire	[fifo_width-1:0]	word3 = fifo[3];
wire	[fifo_width-1:0]	word4 = fifo[4];
wire	[fifo_width-1:0]	word5 = fifo[5];
wire	[fifo_width-1:0]	word6 = fifo[6];
wire	[fifo_width-1:0]	word7 = fifo[7];

wire	[fifo_width-1:0]	word8 = fifo[8];
wire	[fifo_width-1:0]	word9 = fifo[9];
wire	[fifo_width-1:0]	word10 = fifo[10];
wire	[fifo_width-1:0]	word11 = fifo[11];
wire	[fifo_width-1:0]	word12 = fifo[12];
wire	[fifo_width-1:0]	word13 = fifo[13];
wire	[fifo_width-1:0]	word14 = fifo[14];
wire	[fifo_width-1:0]	word15 = fifo[15];


assign	error_bit = |(word0[1:0]  | word1[1:0]  | word2[1:0]  | word3[1:0]  |
            		      word4[1:0]  | word5[1:0]  | word6[1:0]  | word7[1:0]  |
            		      word8[1:0]  | word9[1:0]  | word10[1:0] | word11[1:0] |
            		      word12[1:0] | word13[1:0] | word14[1:0] | word15[1:0] );

endmodule