data/full_repos/permissive/123612637/cpc_ram_expansion1mb/src/asic_lock.v
data/verilator_xmls/dc3b689c-fb45-46ad-86e2-2d4b34e17e43.xml
module asic_lock(
                 input       clk,
                 input       reset_b,
                 input       ioreq_b,
                 input       wr_b,
                 input [7:0] data,
                 input       io_cs,
                 output      enf
                 );


  reg                        enf_d, enf_q ;
  reg [`PRBS_SZ-1:0]         prbs_d, prbs_q ;
  reg [1:0]                  fsm_q, fsm_d;

`ifdef REDUCED_COMPARE
  wire                       not_match  = !(data[7:4] == prbs_q);
`else
  wire                       not_match  = !(data == prbs_q);
`endif

  assign enf = enf_q;

  always @ ( * ) begin
    fsm_d = fsm_q;
    case (fsm_q)
      `INIT: fsm_d = (data != 8'h00) ? `NEXT: `INIT;
      `NEXT: fsm_d = (data == 8'h00) ? `RUN : `INIT;
      `RUN : fsm_d = (!not_match) ? `RUN : (data!=8'h00)? `NEXT : `INIT;
      default: fsm_d = `INIT;
    endcase
  end


  always @ (* ) begin
    if ( prbs_q == `UNLOCKBYTE)
      enf_d = 1'b1;
    else if ( prbs_q == `LOCKBYTE)
      enf_d = 1'b0;
    else
      enf_d = enf_q;
  end

`ifdef REDUCED_COMPARE
  always @ ( * ) begin
    prbs_d[3] <= not_match | (prbs_q[3] ^ prbs_q[0] );
    prbs_d[2] <= not_match |  prbs_q[3];
    prbs_d[1] <= not_match |  prbs_q[2];
    prbs_d[0] <= not_match |  prbs_q[1];
  end
`else
  always @ ( * ) begin
    prbs_d[7] <= not_match | (prbs_q[7] ^ prbs_q[4] );
    prbs_d[6] <= not_match |  prbs_q[7];
    prbs_d[5] <= not_match |  prbs_q[6];
    prbs_d[4] <= not_match |  prbs_q[5];
    prbs_d[3] <= not_match | (prbs_q[1] ^ prbs_q[0] );
    prbs_d[2] <= not_match |  prbs_q[3];
    prbs_d[1] <= not_match |  prbs_q[2];
    prbs_d[0] <= not_match |  prbs_q[1];
  end
`endif

  always @ ( posedge clk or negedge reset_b) begin
    if (!reset_b ) begin
      enf_q  <= 1'b0;
      prbs_q <= {`PRBS_SZ{1'b1}};
      fsm_q <= `INIT;
    end
    else if ( !ioreq_b & !wr_b & io_cs & (fsm_q==`RUN)) begin
      prbs_q <= prbs_d;
      enf_q <= enf_d;
      fsm_q <= fsm_d;
    end
  end

endmodule
module asic_lock(
                 input       clk,
                 input       reset_b,
                 input       ioreq_b,
                 input       wr_b,
                 input [7:0] data,
                 input       io_cs,
                 output      enf
                 );



  reg                        enf_d, enf_q ;
  reg [`PRBS_SZ-1:0]         prbs_d, prbs_q ;
  reg [1:0]                  fsm_q, fsm_d;

`ifdef REDUCED_COMPARE
  wire                       not_match  = !(data[7:4] == prbs_q);
`else
  wire                       not_match  = !(data == prbs_q);
`endif

  assign enf = enf_q;

  always @ ( * ) begin
    fsm_d = fsm_q;
    case (fsm_q)
      `INIT: fsm_d = (data != 8'h00) ? `NEXT: `INIT;
      `NEXT: fsm_d = (data == 8'h00) ? `RUN : `INIT;
      `RUN : fsm_d = (!not_match) ? `RUN : (data!=8'h00)? `NEXT : `INIT;
      default: fsm_d = `INIT;
    endcase
  end


  always @ (* ) begin
    if ( prbs_q == `UNLOCKBYTE)
      enf_d = 1'b1;
    else if ( prbs_q == `LOCKBYTE)
      enf_d = 1'b0;
    else
      enf_d = enf_q;
  end

`ifdef REDUCED_COMPARE
  always @ ( * ) begin
    prbs_d[3] <= not_match | (prbs_q[3] ^ prbs_q[0] );
    prbs_d[2] <= not_match |  prbs_q[3];
    prbs_d[1] <= not_match |  prbs_q[2];
    prbs_d[0] <= not_match |  prbs_q[1];
  end
`else
  always @ ( * ) begin
    prbs_d[7] <= not_match | (prbs_q[7] ^ prbs_q[4] );
    prbs_d[6] <= not_match |  prbs_q[7];
    prbs_d[5] <= not_match |  prbs_q[6];
    prbs_d[4] <= not_match |  prbs_q[5];
    prbs_d[3] <= not_match | (prbs_q[1] ^ prbs_q[0] );
    prbs_d[2] <= not_match |  prbs_q[3];
    prbs_d[1] <= not_match |  prbs_q[2];
    prbs_d[0] <= not_match |  prbs_q[1];
  end
`endif

  always @ ( posedge clk or negedge reset_b) begin
    if (!reset_b ) begin
      enf_q  <= 1'b0;
      prbs_q <= {`PRBS_SZ{1'b1}};
      fsm_q <= `INIT;
    end
    else if ( !ioreq_b & !wr_b & io_cs & (fsm_q==`RUN)) begin
      prbs_q <= prbs_d;
      enf_q <= enf_d;
      fsm_q <= fsm_d;
    end
  end

endmodule