data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/fetch.v
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data/verilator_xmls/55ad606b-715a-48c6-bb0c-c712fc4e639b.xml
module fetch(
    input             clk,
    input             resetn,
    input             IF_valid,
    input             next_fetch,
    input      [31:0] inst,
    input      [32:0] jbr_bus,
    output     [31:0] inst_addr,
    output reg        IF_over,
    output     [63:0] IF_ID_bus,
    

    input      [32:0] exc_bus,
        

    output     [31:0] IF_pc,
    output     [31:0] IF_inst
);


    wire [31:0] next_pc;
    wire [31:0] seq_pc;
    reg  [31:0] pc;
    

    wire        jbr_taken;
    wire [31:0] jbr_target;
    assign {jbr_taken, jbr_target} = jbr_bus;
    

    wire        exc_valid;
    wire [31:0] exc_pc;
    assign {exc_valid,exc_pc} = exc_bus;
    

    assign seq_pc[31:2]    = pc[31:2] + 1'b1;
    assign seq_pc[1:0]     = pc[1:0];



    assign next_pc = exc_valid ? exc_pc : 
                     jbr_taken ? jbr_target : seq_pc;
    always @(posedge clk)
    begin
        if (!resetn)
        begin
            pc <= `STARTADDR;
        end
        else if (next_fetch)
        begin
            pc <= next_pc;
        end
    end



    assign inst_addr = pc;









    always @(posedge clk)
    begin
        if (!resetn || next_fetch)
        begin
            IF_over <= 1'b0;
        end
        else
        begin
            IF_over <= IF_valid;
        end
    end





    assign IF_ID_bus = {pc, inst};



    assign IF_pc   = pc;
    assign IF_inst = inst;

endmodule
module fetch(
    input             clk,
    input             resetn,
    input             IF_valid,
    input             next_fetch,
    input      [31:0] inst,
    input      [32:0] jbr_bus,
    output     [31:0] inst_addr,
    output reg        IF_over,
    output     [63:0] IF_ID_bus,
    

    input      [32:0] exc_bus,
        

    output     [31:0] IF_pc,
    output     [31:0] IF_inst
);



    wire [31:0] next_pc;
    wire [31:0] seq_pc;
    reg  [31:0] pc;
    

    wire        jbr_taken;
    wire [31:0] jbr_target;
    assign {jbr_taken, jbr_target} = jbr_bus;
    

    wire        exc_valid;
    wire [31:0] exc_pc;
    assign {exc_valid,exc_pc} = exc_bus;
    

    assign seq_pc[31:2]    = pc[31:2] + 1'b1;
    assign seq_pc[1:0]     = pc[1:0];



    assign next_pc = exc_valid ? exc_pc : 
                     jbr_taken ? jbr_target : seq_pc;
    always @(posedge clk)
    begin
        if (!resetn)
        begin
            pc <= `STARTADDR;
        end
        else if (next_fetch)
        begin
            pc <= next_pc;
        end
    end



    assign inst_addr = pc;









    always @(posedge clk)
    begin
        if (!resetn || next_fetch)
        begin
            IF_over <= 1'b0;
        end
        else
        begin
            IF_over <= IF_valid;
        end
    end





    assign IF_ID_bus = {pc, inst};



    assign IF_pc   = pc;
    assign IF_inst = inst;

endmodule