data/full_repos/permissive/108195533/tb.v
 line:9: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/108195533/tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = !clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108195533/tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n # 10 rst =1\'b0;\n ^\n%Error: data/full_repos/permissive/108195533/tb.v:13: Can\'t find definition of \'stall\' in dotted variable: \'uut.stall\'\n   if(uut.stall)\n          ^~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
reg clk, rst;
integer clkNum=0, stallNum=0;
mips_top uut(clk, rst);

initial begin
	clk=1'b0;
	repeat(2000) begin 
		#5 clk = !clk;
		if(clk) begin
			clkNum=clkNum+1;
			if(uut.stall)
				stallNum = stallNum+1;
		end
	end
end

initial begin
	rst=1'b1;
	# 10 rst =1'b0;
end

endmodule
module tb;

reg clk, rst;
integer clkNum=0, stallNum=0;
mips_top uut(clk, rst);

initial begin
	clk=1'b0;
	repeat(2000) begin 
		#5 clk = !clk;
		if(clk) begin
			clkNum=clkNum+1;
			if(uut.stall)
				stallNum = stallNum+1;
		end
	end
end

initial begin
	rst=1'b1;
	# 10 rst =1'b0;
end

endmodule