data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v
data/verilator_xmls/3e95e8e8-9572-4698-b2b8-13e48d3dc5da.xml
module rst_on_lut(a, b, q, out, clk, rst);

input wire rst;
input wire clk;
input wire a;
input wire b;
output reg q;
output wire out;

always @(posedge rst or posedge clk) begin
  if (rst) begin
    q <= 0;
  end else begin
    q <= a;
  end
end

assign out = b & ~rst;

endmodule
module rst_on_lut(a, b, q, out, clk, rst);


input wire rst;
input wire clk;
input wire a;
input wire b;
output reg q;
output wire out;

always @(posedge rst or posedge clk) begin
  if (rst) begin
    q <= 0;
  end else begin
    q <= a;
  end
end

assign out = b & ~rst;

endmodule