data/full_repos/permissive/118800618/Multi_CPU.v
1: b"%Error: data/full_repos/permissive/118800618/Multi_CPU.v:43: Cannot find file containing module: 'M_datapath'\n M_datapath   U11(.clk(clk),\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/118800618,data/full_repos/permissive/118800618/M_datapath\n             data/full_repos/permissive/118800618,data/full_repos/permissive/118800618/M_datapath.v\n             data/full_repos/permissive/118800618,data/full_repos/permissive/118800618/M_datapath.sv\n             M_datapath\n             M_datapath.v\n             M_datapath.sv\n             obj_dir/M_datapath\n             obj_dir/M_datapath.v\n             obj_dir/M_datapath.sv\n%Error: data/full_repos/permissive/118800618/Multi_CPU.v:66: Cannot find file containing module: 'ctrl'\n ctrl     U12(.clk(clk),\n ^~~~\n%Error: data/full_repos/permissive/118800618/Multi_CPU.v:89: Cannot find file containing module: 'INV'\n INV   myINV(.I(MemRead),\n ^~~\n%Error: data/full_repos/permissive/118800618/Multi_CPU.v:92: Cannot find file containing module: 'AND2'\n AND2   myAND(.I0(MemRead_INV),\n ^~~~\n%Error: Exiting due to 4 error(s)\n"
module Multi_CPU(	 input clk,
						 input reset,
						 input MIO_ready,
						output [31:0]PC_out,
						output [31:0]inst_out,
						output mem_w,
						output [31:0]Addr_out,
						output [31:0]Data_out,
						 input [31:0]Data_in,
						output CPU_MIO,
						 input INT,
						output [4:0]state
					  );
					  
	wire MemRead, MemWrite, MemRead_INV;
	wire zero, overflow;
	wire IorD, IRWrite, RegWrite, ALUSrcA, PCWrite, PCWriteCond;
	wire [1:0]RegDst;
	wire [1:0]MemtoReg;
	wire [1:0]ALUSrcB;
	wire [1:0]PCSource;
	wire [2:0]ALU_operation;
	M_datapath	  U11(.clk(clk),
							.reset(reset),
							.MIO_ready(MIO_ready),
							.IorD(IorD),
							.IRWrite(IRWrite),
							.RegDst(RegDst[1:0]),
							.RegWrite(RegWrite),
							.MemtoReg(MemtoReg[1:0]),
							.ALUSrcA(ALUSrcA),
							.ALUSrcB(ALUSrcB[1:0]),
							.PCSource(PCSource[1:0]),
							.PCWrite(PCWrite),
							.PCWriteCond(PCWriteCond),	
							.Branch(Branch),
							.ALU_operation(ALU_operation[2:0]),
							.PC_Current(PC_out[31:0]),
							.data2CPU(Data_in[31:0]),
							.Inst(inst_out[31:0]),
							.data_out(Data_out[31:0]),
							.M_addr(Addr_out[31:0]),
							.zero(zero),
							.overflow(overflow)
							);
	ctrl			  U12(.clk(clk),
							.reset(reset),
							.Inst_in(inst_out[31:0]),
							.zero(zero),
							.overflow(overflow),
							.MIO_ready(MIO_ready),
							.MemRead(MemRead),
							.MemWrite(MemWrite),
							.ALU_operation(ALU_operation[2:0]),
							.state_out(state[4:0]),
							.CPU_MIO(CPU_MIO),
							.IorD(IorD),
							.IRWrite(IRWrite),
							.RegDst(RegDst[1:0]),
							.RegWrite(RegWrite),
							.MemtoReg(MemtoReg[1:0]),
							.ALUSrcA(ALUSrcA),
							.ALUSrcB(ALUSrcB[1:0]),
							.PCSource(PCSource[1:0]),
							.PCWrite(PCWrite),
							.PCWriteCond(PCWriteCond),
							.Branch(Branch)
							);
	INV			myINV(.I(MemRead),
							.O(MemRead_INV)
							);
	AND2			myAND(.I0(MemRead_INV),
							.I1(MemWrite),
							.O(mem_w)
							);

endmodule
module Multi_CPU(	 input clk,
						 input reset,
						 input MIO_ready,
						output [31:0]PC_out,
						output [31:0]inst_out,
						output mem_w,
						output [31:0]Addr_out,
						output [31:0]Data_out,
						 input [31:0]Data_in,
						output CPU_MIO,
						 input INT,
						output [4:0]state
					  );

					  
	wire MemRead, MemWrite, MemRead_INV;
	wire zero, overflow;
	wire IorD, IRWrite, RegWrite, ALUSrcA, PCWrite, PCWriteCond;
	wire [1:0]RegDst;
	wire [1:0]MemtoReg;
	wire [1:0]ALUSrcB;
	wire [1:0]PCSource;
	wire [2:0]ALU_operation;
	M_datapath	  U11(.clk(clk),
							.reset(reset),
							.MIO_ready(MIO_ready),
							.IorD(IorD),
							.IRWrite(IRWrite),
							.RegDst(RegDst[1:0]),
							.RegWrite(RegWrite),
							.MemtoReg(MemtoReg[1:0]),
							.ALUSrcA(ALUSrcA),
							.ALUSrcB(ALUSrcB[1:0]),
							.PCSource(PCSource[1:0]),
							.PCWrite(PCWrite),
							.PCWriteCond(PCWriteCond),	
							.Branch(Branch),
							.ALU_operation(ALU_operation[2:0]),
							.PC_Current(PC_out[31:0]),
							.data2CPU(Data_in[31:0]),
							.Inst(inst_out[31:0]),
							.data_out(Data_out[31:0]),
							.M_addr(Addr_out[31:0]),
							.zero(zero),
							.overflow(overflow)
							);
	ctrl			  U12(.clk(clk),
							.reset(reset),
							.Inst_in(inst_out[31:0]),
							.zero(zero),
							.overflow(overflow),
							.MIO_ready(MIO_ready),
							.MemRead(MemRead),
							.MemWrite(MemWrite),
							.ALU_operation(ALU_operation[2:0]),
							.state_out(state[4:0]),
							.CPU_MIO(CPU_MIO),
							.IorD(IorD),
							.IRWrite(IRWrite),
							.RegDst(RegDst[1:0]),
							.RegWrite(RegWrite),
							.MemtoReg(MemtoReg[1:0]),
							.ALUSrcA(ALUSrcA),
							.ALUSrcB(ALUSrcB[1:0]),
							.PCSource(PCSource[1:0]),
							.PCWrite(PCWrite),
							.PCWriteCond(PCWriteCond),
							.Branch(Branch)
							);
	INV			myINV(.I(MemRead),
							.O(MemRead_INV)
							);
	AND2			myAND(.I0(MemRead_INV),
							.I1(MemWrite),
							.O(mem_w)
							);

endmodule