data/full_repos/permissive/143278/ivltests/clkgen_logic.v
 line:9: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/clkgen_logic.v:12: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/clkgen_logic.v:20: Unsupported: fork statements\n  fork\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/clkgen_logic.v:27: Unsupported: Ignoring delay on this delayed statement.\n   forever #10 clk = ~clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/clkgen_logic.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clkgen(output logic clk = 0);

initial begin
   #100;
   disable checking;
   disable gen;
   $display ("PASSED");
   $finish;
end

initial begin
  fork
    gen;
    checking;
  join
end

task gen;
   forever #10 clk = ~clk;
endtask

task checking;
   forever begin
      #1;
      if (clk === 1'bx ) begin
         $display ("FAILED!");
	     $finish;
      end
   end
endtask

endmodule
module clkgen(output logic clk = 0);


initial begin
   #100;
   disable checking;
   disable gen;
   $display ("PASSED");
   $finish;
end

initial begin
  fork
    gen;
    checking;
  join
end

task gen;
   forever #10 clk = ~clk;
endtask

task checking;
   forever begin
      #1;
      if (clk === 1'bx ) begin
         $display ("FAILED!");
	     $finish;
      end
   end
endtask

endmodule