data/full_repos/permissive/205931224/source/src/ALU.v
 line:126: before: "signed"
1: b'%Error: data/full_repos/permissive/205931224/source/src/ALU.v:24: Cannot find include file: macros.v\n`include "macros.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205931224/source/src,data/full_repos/permissive/205931224/macros.v\n             data/full_repos/permissive/205931224/source/src,data/full_repos/permissive/205931224/macros.v.v\n             data/full_repos/permissive/205931224/source/src,data/full_repos/permissive/205931224/macros.v.sv\n             macros.v\n             macros.v.v\n             macros.v.sv\n             obj_dir/macros.v\n             obj_dir/macros.v.v\n             obj_dir/macros.v.sv\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:43: Define or directive not defined: \'`ALU_ADD\'\n assign dsp_sel = (cmd == `ALU_ADD) ? 1\'b1 : 1\'b0;\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:43: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign dsp_sel = (cmd == `ALU_ADD) ? 1\'b1 : 1\'b0;\n                                  ^\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:63: Define or directive not defined: \'`ALU_AND\'\n   `ALU_AND:  OUT = opa & opb;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:63: syntax error, unexpected \':\', expecting endcase\n   `ALU_AND:  OUT = opa & opb;\n           ^\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:64: Define or directive not defined: \'`ALU_OR\'\n   `ALU_OR:   OUT = opa | opb;\n   ^~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:65: Define or directive not defined: \'`ALU_ADD\'\n            `ALU_ADD:   OUT = dsp_out;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:66: Define or directive not defined: \'`ALU_SUB\'\n            `ALU_SUB:   OUT = dsp_out;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:67: Define or directive not defined: \'`ALU_SLT\'\n   `ALU_SLT:  OUT = (opa < opb) ? 32\'d1 : 32\'d0;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:68: Define or directive not defined: \'`ALU_NOR\'\n   `ALU_NOR:  OUT = ~(opa | opb);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:69: Define or directive not defined: \'`ALU_XOR\'\n   `ALU_XOR:  OUT = opa ^ opb;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:70: Define or directive not defined: \'`ALU_LU\'\n   `ALU_LU: OUT = {opb[15:0], 16\'h0};\n   ^~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:71: Define or directive not defined: \'`ALU_SLLV\'\n   `ALU_SLLV: OUT = opa << shift;\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/ALU.v:72: Define or directive not defined: \'`ALU_SRLV\'\n   `ALU_SRLV: OUT = opa >> shift;\n   ^~~~~~~~~\n%Error: Cannot continue\n'
function signed [31:0] OUT;
		input signed [31:0] opa;
		input signed [31:0] opb;
		input signed [31:0] dsp_out;
		input [5:0]			   shift;
		input [3:0]	 		   cmd;
		begin
			case( cmd )
			`ALU_AND: 	OUT = opa & opb;
			`ALU_OR:  	OUT = opa | opb;
            `ALU_ADD:   OUT = dsp_out;
            `ALU_SUB:   OUT = dsp_out;
			`ALU_SLT: 	OUT = (opa < opb) ? 32'd1 : 32'd0;
			`ALU_NOR: 	OUT = ~(opa | opb);
			`ALU_XOR: 	OUT = opa ^ opb;
			`ALU_LU:	OUT = {opb[15:0], 16'h0};
			`ALU_SLLV:	OUT = opa << shift;
			`ALU_SRLV:	OUT = opa >> shift;
			default: OUT = 32'hxxxxxxxx;
			endcase
		end
	endfunction
function signed [31:0] OUT;

		input signed [31:0] opa;
		input signed [31:0] opb;
		input signed [31:0] dsp_out;
		input [5:0]			   shift;
		input [3:0]	 		   cmd;
		begin
			case( cmd )
			`ALU_AND: 	OUT = opa & opb;
			`ALU_OR:  	OUT = opa | opb;
            `ALU_ADD:   OUT = dsp_out;
            `ALU_SUB:   OUT = dsp_out;
			`ALU_SLT: 	OUT = (opa < opb) ? 32'd1 : 32'd0;
			`ALU_NOR: 	OUT = ~(opa | opb);
			`ALU_XOR: 	OUT = opa ^ opb;
			`ALU_LU:	OUT = {opb[15:0], 16'h0};
			`ALU_SLLV:	OUT = opa << shift;
			`ALU_SRLV:	OUT = opa >> shift;
			default: OUT = 32'hxxxxxxxx;
			endcase
		end
	endfunction