data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl/hex_driver.v
1: b"%Error: data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl/hex_driver.v:46: Cannot find file containing module: 'clock_divider'\n    clock_divider #(100000) cd1(.clk_in(CLK_50MHZ), .clk_out(sc_circuit_clk));\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl,data/full_repos/permissive/168456532/clock_divider\n             data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl,data/full_repos/permissive/168456532/clock_divider.v\n             data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl,data/full_repos/permissive/168456532/clock_divider.sv\n             clock_divider\n             clock_divider.v\n             clock_divider.sv\n             obj_dir/clock_divider\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.sv\n%Error: data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl/hex_driver.v:48: Cannot find file containing module: 'scan_control'\n    scan_control sc_circuit(.seg(seg), .an(an), .tho_seg(tho_seg), .hun_seg(hun_seg), .ten_seg(ten_seg), .lsb_seg(lsb_seg), .clk(sc_circuit_clk));\n    ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module BCDToLED(output [6:0] seg, input [3:0] x);
    wire ten = (x == 4'b1010);
    wire eleven = (x == 4'b1011);
    wire twelve = (x == 4'b1100);
    wire thirteen = (x == 4'b1101);
    wire fourteen = (x == 4'b1110);
    wire fifteen = (x == 4'b1111);
    wire two_digit = ten | eleven | twelve | thirteen | fourteen | fifteen;

    assign seg[0] = (~two_digit & ((~x[3] & ~x[2] & ~x[1] & x[0]) | (x[2] & ~x[1] & ~x[0]))) | (eleven | thirteen);
    assign seg[1] = (~two_digit & ((x[2] & ~x[1] & x[0]) | (x[2] & x[1] & ~x[0]))) | (eleven | twelve | fourteen | fifteen);
    assign seg[2] = (~two_digit & ((~x[2] & x[1] & ~x[0]))) | (twelve | fourteen | fifteen);
    assign seg[3] = (~two_digit & ((~x[3] & ~x[2] & ~x[1] & x[0]) | (x[2] & ~x[1] & ~x[0]) | (x[2] & x[1] & x[0]))) | (ten | fifteen);
    assign seg[4] = (~two_digit & ((x[0]) | (x[2] & ~x[1])));
    assign seg[5] = (~two_digit & ((~x[3] & ~x[2] & x[0]) | (~x[3] & ~x[2] & x[1]) | (x[1] & x[0]))) | (thirteen);
    assign seg[6] = (~two_digit & ((~x[3] & ~x[2] & ~x[1]) | (x[2] & x[1] & x[0]))) | (twelve);
endmodule
module BCDToLED(output [6:0] seg, input [3:0] x);

    wire ten = (x == 4'b1010);
    wire eleven = (x == 4'b1011);
    wire twelve = (x == 4'b1100);
    wire thirteen = (x == 4'b1101);
    wire fourteen = (x == 4'b1110);
    wire fifteen = (x == 4'b1111);
    wire two_digit = ten | eleven | twelve | thirteen | fourteen | fifteen;

    assign seg[0] = (~two_digit & ((~x[3] & ~x[2] & ~x[1] & x[0]) | (x[2] & ~x[1] & ~x[0]))) | (eleven | thirteen);
    assign seg[1] = (~two_digit & ((x[2] & ~x[1] & x[0]) | (x[2] & x[1] & ~x[0]))) | (eleven | twelve | fourteen | fifteen);
    assign seg[2] = (~two_digit & ((~x[2] & x[1] & ~x[0]))) | (twelve | fourteen | fifteen);
    assign seg[3] = (~two_digit & ((~x[3] & ~x[2] & ~x[1] & x[0]) | (x[2] & ~x[1] & ~x[0]) | (x[2] & x[1] & x[0]))) | (ten | fifteen);
    assign seg[4] = (~two_digit & ((x[0]) | (x[2] & ~x[1])));
    assign seg[5] = (~two_digit & ((~x[3] & ~x[2] & x[0]) | (~x[3] & ~x[2] & x[1]) | (x[1] & x[0]))) | (thirteen);
    assign seg[6] = (~two_digit & ((~x[3] & ~x[2] & ~x[1]) | (x[2] & x[1] & x[0]))) | (twelve);
endmodule