data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v
1: b'%Error: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:46: Cannot find file containing module: \'PC_adder\'\n    PC_adder pcadd(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new,data/full_repos/permissive/191638444/PC_adder\n             data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new,data/full_repos/permissive/191638444/PC_adder.v\n             data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new,data/full_repos/permissive/191638444/PC_adder.sv\n             PC_adder\n             PC_adder.v\n             PC_adder.sv\n             obj_dir/PC_adder\n             obj_dir/PC_adder.v\n             obj_dir/PC_adder.sv\n%Error: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:51: Cannot find file containing module: \'instruction_module\'\n    instruction_module instmd(\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:95: Cannot find file containing module: \'control_unit\'\n    control_unit cunit(\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:105: Cannot find file containing module: \'mux2x1\'\n    mux2x1 mux(\n    ^~~~~~\n%Error: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:111: Cannot find file containing module: \'register_file\'\n    register_file reg_file(\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:121: Cannot find file containing module: \'signext_16_32\'\n    signext_16_32 signext(\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:167: Cannot find file containing module: \'emux2x1\'\n    emux2x1 emux(\n    ^~~~~~~\n%Error: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:174: Cannot find file containing module: \'ALU\'\n    ALU alu(\n    ^~~\n%Error: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:212: Cannot find file containing module: \'data_mem\'\n    data_mem dataMem(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:242: Cannot find file containing module: \'wmux2x1\'\n    wmux2x1 wmux(\n    ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:270: Unsized constant being X/Z extended to 109 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                 : ... In instance CPU\n                    ID_EXE <= \'dX;\n                              ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/CPU.v:278: Unsized constant being X/Z extended to 72 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                 : ... In instance CPU\n                    EXE_MEM <= \'dX;\n                               ^~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n'
module CPU(clk, reset, LEDcheck);

    input clk;
    input reset;
    output reg LEDcheck;
     
    reg [31:0] PC;
    reg [31:0] IF_ID;
    reg [108:0] ID_EXE;
    reg [71:0] EXE_MEM;
    reg [70:0] MEM_WB;
    reg [4:0] wMUXoutOutput;
    reg [31:0] w_MUX_32_out_Output;
    

    wire [31:0] PC_wire;
    wire [31:0] IF_ID_wire;
    reg [108:0] ID_EXE_reg;
    reg [71:0] EXE_MEM_reg;
    reg [70:0] MEM_WB_reg;
    

    
    PC_adder pcadd(
        .inputPC(PC),
        .outputPC(PC_wire)
    );
        
    instruction_module instmd(
        .PC(PC),
        .data_out(IF_ID_wire)
    );
    

    

    reg [5:0] op,func;
    reg [4:0] rd, rs, rt, shamt;
    reg [15:0] imm ;
    

    

    wire [31:0] immext;

    wire [31:0] qa, qb;

    wire [0:0] wreg, m2reg, wmem, aluimm, regrt;
    wire [3:0] aluc;

    wire [4:0] MUXout;
    

    reg wwreg;
    reg [4:0] wMUXout;
    wire [31:0] w_MUX_32_out;
    

    reg [4:0] mMUXout;

    reg [4:0] eMUXout;
    
    always @(IF_ID)
    begin
        op <= IF_ID [31:26];
        rs <= IF_ID [25:21];
        rt <= IF_ID [20:16];
        rd <= IF_ID [15:11];
        func <= IF_ID [5:0];
        imm <= IF_ID [15:0];
    end
    
    control_unit cunit(
        .op(op),
        .func(func), 
        .m2reg(m2reg), 
        .aluimm(aluimm),
        .regrt(regrt),
        .wreg(wreg),
        .wmem(wmem),
        .aluc(aluc)
    );
    mux2x1 mux(
        .Input0(rd),
        .Input1(rt),
        .selector(regrt),
        .D(MUXout)
    );
    register_file reg_file(
        .clk(clk),
        .Read1(rs), 
        .Read2(rt), 
        .Data1(qa), 
        .Data2(qb),
        .writeEnabled(wwreg),
        .writeData(w_MUX_32_out),
        .writeAddress(wMUXout)
    );
    signext_16_32 signext(
        .I(imm),
        .O(immext)
    );
    always @(wreg, m2reg, wmem, aluc, aluimm, MUXout, qa, qb, immext)
    begin
        ID_EXE_reg [108] <= wreg;
        ID_EXE_reg [107] <= m2reg;
        ID_EXE_reg [106] <= wmem;
        ID_EXE_reg [105:102] <= aluc;
        ID_EXE_reg [101] <= aluimm;
        ID_EXE_reg [100: 96] <= MUXout;
        ID_EXE_reg [95:64] <= qa;
        ID_EXE_reg [63:32] <= qb;
        ID_EXE_reg [31:0] <= immext;

    end
    

    


    reg [31:0] eimmext;

    reg [31:0] eqa, eqb;

    reg [0:0] ewreg, em2reg, ewmem, ealuimm;
    reg [3:0] ealuc;
    

    wire [31:0] MUX_32_out;
    wire [31:0] ALU_Out;
    
    always @(ID_EXE)
    begin
        ewreg <= ID_EXE [108];
        em2reg <= ID_EXE [107] ;
        ewmem <= ID_EXE [106];
        ealuc <= ID_EXE [105:102];
        ealuimm <= ID_EXE [101];
        eMUXout <= ID_EXE [100: 96] ;
        eqa <= ID_EXE [95:64];
        eqb <= ID_EXE [63:32];
        eimmext <= ID_EXE [31:0];
    end
    
    emux2x1 emux(
        .Input0(eqb),
        .Input1(eimmext),
        .selector(ealuimm),
        .D(MUX_32_out)
    );
    
    ALU alu(
        .A(eqa),
        .B(MUX_32_out), 
        .aluc(ealuc),
        .ALUOut(ALU_Out)
    );
    
    always @(ewreg, em2reg, ewmem, eMUXout, ALU_Out, eqb)
    begin
        EXE_MEM_reg [71] <= ewreg;
        EXE_MEM_reg [70] <= em2reg;
        EXE_MEM_reg [69] <= ewmem;
        EXE_MEM_reg [68:64] <= eMUXout;
        EXE_MEM_reg [63:32] <= ALU_Out;
        EXE_MEM_reg [31:0] <= eqb;
    end

    


    reg [31:0] mqb;

    reg mwreg, mm2reg, mwmem;

    reg [31:0] mALUout;

    wire [31:0] mDataOut;
    
    always @(EXE_MEM)
    begin
        mwreg <= EXE_MEM[71];
        mm2reg <= EXE_MEM[70];
        mwmem <= EXE_MEM[69] ;
        mMUXout <= EXE_MEM[68:64];
        mALUout <= EXE_MEM[63:32];
        mqb <= EXE_MEM[31:0];
    end
    
    data_mem dataMem(
        .address(mALUout),
        .dataIn(mqb),
        .writeEnabled(mwmem),
        .dataOut(mDataOut)
    );
    
    always @(mwreg, mm2reg, mMUXout, mALUout, mqb, mDataOut)
    begin
        MEM_WB_reg [70] <= mwreg;
        MEM_WB_reg [69] <= mm2reg;
        MEM_WB_reg [68:64] <= mMUXout;
        MEM_WB_reg [63:32] <= mALUout;
        MEM_WB_reg [31:0] <= mDataOut;
    end
    

    reg wm2reg;
    reg [31:0] wALUout;
    reg [31:0] wDataOut;
    
    always @(MEM_WB)
    begin
        wwreg <= MEM_WB [70];
        wm2reg <= MEM_WB [69];
        wMUXout <= MEM_WB [68:64];
        wALUout <= MEM_WB [63:32];
        wDataOut <= MEM_WB [31:0];
    end
    
    wmux2x1 wmux(
        .Input0(wALUout),
        .Input1(wDataOut),
        .selector(wm2reg),
        .D(w_MUX_32_out)
    );
    
    reg [31:0] count;
    
    initial
    begin
        count <= 'd100;
    end
    
    always @(posedge clk)
    begin
        if (reset == 'd1)
        begin
            if (count > 'h90)
            begin
                LEDcheck <= 'b1;
            end

            count <= count+'h4;        
            if (eMUXout == rs || eMUXout == rt || mMUXout == rs || mMUXout == rt)
            begin
                if (eMUXout == rs || eMUXout == rt)
                begin
                    ID_EXE <= 'dX;
                    EXE_MEM <= EXE_MEM_reg;
                    MEM_WB <= MEM_WB_reg;
                    wMUXoutOutput <= wMUXout;
                    w_MUX_32_out_Output <= w_MUX_32_out;
                end
                if (mMUXout == rs || mMUXout == rt)
                begin
                    EXE_MEM <= 'dX;
                    MEM_WB <= MEM_WB_reg;
                    wMUXoutOutput <= wMUXout;
                    w_MUX_32_out_Output <= w_MUX_32_out;
                end
            end
            else
            begin
                PC <= PC_wire;
                IF_ID <= IF_ID_wire;
                ID_EXE <= ID_EXE_reg;
                EXE_MEM <= EXE_MEM_reg;
                MEM_WB <= MEM_WB_reg;
                wMUXoutOutput <= wMUXout;
                w_MUX_32_out_Output <= w_MUX_32_out;
            end
                
        end 
        else
        begin
            PC <= 32'd100;
            LEDcheck <= 'b0;
        end
    end
    
endmodule
module CPU(clk, reset, LEDcheck);


    input clk;
    input reset;
    output reg LEDcheck;
     
    reg [31:0] PC;
    reg [31:0] IF_ID;
    reg [108:0] ID_EXE;
    reg [71:0] EXE_MEM;
    reg [70:0] MEM_WB;
    reg [4:0] wMUXoutOutput;
    reg [31:0] w_MUX_32_out_Output;
    

    wire [31:0] PC_wire;
    wire [31:0] IF_ID_wire;
    reg [108:0] ID_EXE_reg;
    reg [71:0] EXE_MEM_reg;
    reg [70:0] MEM_WB_reg;
    

    
    PC_adder pcadd(
        .inputPC(PC),
        .outputPC(PC_wire)
    );
        
    instruction_module instmd(
        .PC(PC),
        .data_out(IF_ID_wire)
    );
    

    

    reg [5:0] op,func;
    reg [4:0] rd, rs, rt, shamt;
    reg [15:0] imm ;
    

    

    wire [31:0] immext;

    wire [31:0] qa, qb;

    wire [0:0] wreg, m2reg, wmem, aluimm, regrt;
    wire [3:0] aluc;

    wire [4:0] MUXout;
    

    reg wwreg;
    reg [4:0] wMUXout;
    wire [31:0] w_MUX_32_out;
    

    reg [4:0] mMUXout;

    reg [4:0] eMUXout;
    
    always @(IF_ID)
    begin
        op <= IF_ID [31:26];
        rs <= IF_ID [25:21];
        rt <= IF_ID [20:16];
        rd <= IF_ID [15:11];
        func <= IF_ID [5:0];
        imm <= IF_ID [15:0];
    end
    
    control_unit cunit(
        .op(op),
        .func(func), 
        .m2reg(m2reg), 
        .aluimm(aluimm),
        .regrt(regrt),
        .wreg(wreg),
        .wmem(wmem),
        .aluc(aluc)
    );
    mux2x1 mux(
        .Input0(rd),
        .Input1(rt),
        .selector(regrt),
        .D(MUXout)
    );
    register_file reg_file(
        .clk(clk),
        .Read1(rs), 
        .Read2(rt), 
        .Data1(qa), 
        .Data2(qb),
        .writeEnabled(wwreg),
        .writeData(w_MUX_32_out),
        .writeAddress(wMUXout)
    );
    signext_16_32 signext(
        .I(imm),
        .O(immext)
    );
    always @(wreg, m2reg, wmem, aluc, aluimm, MUXout, qa, qb, immext)
    begin
        ID_EXE_reg [108] <= wreg;
        ID_EXE_reg [107] <= m2reg;
        ID_EXE_reg [106] <= wmem;
        ID_EXE_reg [105:102] <= aluc;
        ID_EXE_reg [101] <= aluimm;
        ID_EXE_reg [100: 96] <= MUXout;
        ID_EXE_reg [95:64] <= qa;
        ID_EXE_reg [63:32] <= qb;
        ID_EXE_reg [31:0] <= immext;

    end
    

    


    reg [31:0] eimmext;

    reg [31:0] eqa, eqb;

    reg [0:0] ewreg, em2reg, ewmem, ealuimm;
    reg [3:0] ealuc;
    

    wire [31:0] MUX_32_out;
    wire [31:0] ALU_Out;
    
    always @(ID_EXE)
    begin
        ewreg <= ID_EXE [108];
        em2reg <= ID_EXE [107] ;
        ewmem <= ID_EXE [106];
        ealuc <= ID_EXE [105:102];
        ealuimm <= ID_EXE [101];
        eMUXout <= ID_EXE [100: 96] ;
        eqa <= ID_EXE [95:64];
        eqb <= ID_EXE [63:32];
        eimmext <= ID_EXE [31:0];
    end
    
    emux2x1 emux(
        .Input0(eqb),
        .Input1(eimmext),
        .selector(ealuimm),
        .D(MUX_32_out)
    );
    
    ALU alu(
        .A(eqa),
        .B(MUX_32_out), 
        .aluc(ealuc),
        .ALUOut(ALU_Out)
    );
    
    always @(ewreg, em2reg, ewmem, eMUXout, ALU_Out, eqb)
    begin
        EXE_MEM_reg [71] <= ewreg;
        EXE_MEM_reg [70] <= em2reg;
        EXE_MEM_reg [69] <= ewmem;
        EXE_MEM_reg [68:64] <= eMUXout;
        EXE_MEM_reg [63:32] <= ALU_Out;
        EXE_MEM_reg [31:0] <= eqb;
    end

    


    reg [31:0] mqb;

    reg mwreg, mm2reg, mwmem;

    reg [31:0] mALUout;

    wire [31:0] mDataOut;
    
    always @(EXE_MEM)
    begin
        mwreg <= EXE_MEM[71];
        mm2reg <= EXE_MEM[70];
        mwmem <= EXE_MEM[69] ;
        mMUXout <= EXE_MEM[68:64];
        mALUout <= EXE_MEM[63:32];
        mqb <= EXE_MEM[31:0];
    end
    
    data_mem dataMem(
        .address(mALUout),
        .dataIn(mqb),
        .writeEnabled(mwmem),
        .dataOut(mDataOut)
    );
    
    always @(mwreg, mm2reg, mMUXout, mALUout, mqb, mDataOut)
    begin
        MEM_WB_reg [70] <= mwreg;
        MEM_WB_reg [69] <= mm2reg;
        MEM_WB_reg [68:64] <= mMUXout;
        MEM_WB_reg [63:32] <= mALUout;
        MEM_WB_reg [31:0] <= mDataOut;
    end
    

    reg wm2reg;
    reg [31:0] wALUout;
    reg [31:0] wDataOut;
    
    always @(MEM_WB)
    begin
        wwreg <= MEM_WB [70];
        wm2reg <= MEM_WB [69];
        wMUXout <= MEM_WB [68:64];
        wALUout <= MEM_WB [63:32];
        wDataOut <= MEM_WB [31:0];
    end
    
    wmux2x1 wmux(
        .Input0(wALUout),
        .Input1(wDataOut),
        .selector(wm2reg),
        .D(w_MUX_32_out)
    );
    
    reg [31:0] count;
    
    initial
    begin
        count <= 'd100;
    end
    
    always @(posedge clk)
    begin
        if (reset == 'd1)
        begin
            if (count > 'h90)
            begin
                LEDcheck <= 'b1;
            end

            count <= count+'h4;        
            if (eMUXout == rs || eMUXout == rt || mMUXout == rs || mMUXout == rt)
            begin
                if (eMUXout == rs || eMUXout == rt)
                begin
                    ID_EXE <= 'dX;
                    EXE_MEM <= EXE_MEM_reg;
                    MEM_WB <= MEM_WB_reg;
                    wMUXoutOutput <= wMUXout;
                    w_MUX_32_out_Output <= w_MUX_32_out;
                end
                if (mMUXout == rs || mMUXout == rt)
                begin
                    EXE_MEM <= 'dX;
                    MEM_WB <= MEM_WB_reg;
                    wMUXoutOutput <= wMUXout;
                    w_MUX_32_out_Output <= w_MUX_32_out;
                end
            end
            else
            begin
                PC <= PC_wire;
                IF_ID <= IF_ID_wire;
                ID_EXE <= ID_EXE_reg;
                EXE_MEM <= EXE_MEM_reg;
                MEM_WB <= MEM_WB_reg;
                wMUXoutOutput <= wMUXout;
                w_MUX_32_out_Output <= w_MUX_32_out;
            end
                
        end 
        else
        begin
            PC <= 32'd100;
            LEDcheck <= 'b0;
        end
    end
    
endmodule