data/full_repos/permissive/169496369/MIPS_CP1_01_TB.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/169496369/MIPS_CP1_01_TB.sv:31: Unsupported: Ignoring delay on this delayed statement.\n        #30 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169496369/MIPS_CP1_01_TB.sv:37: Unsupported: Ignoring delay on this delayed statement.\n        #35 rst = 0;\n        ^\n%Error: data/full_repos/permissive/169496369/MIPS_CP1_01_TB.sv:28: Cannot find file containing module: \'MIPS_CP1_01\'\n    MIPS_CP1_01 mips1(clk, rst, y);\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169496369,data/full_repos/permissive/169496369/MIPS_CP1_01\n             data/full_repos/permissive/169496369,data/full_repos/permissive/169496369/MIPS_CP1_01.v\n             data/full_repos/permissive/169496369,data/full_repos/permissive/169496369/MIPS_CP1_01.sv\n             MIPS_CP1_01\n             MIPS_CP1_01.v\n             MIPS_CP1_01.sv\n             obj_dir/MIPS_CP1_01\n             obj_dir/MIPS_CP1_01.v\n             obj_dir/MIPS_CP1_01.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MIPS_CP1_01_TB();

    logic   clk, rst;
    logic y;
    
    MIPS_CP1_01 mips1(clk, rst, y);
        
    always
        #30 clk = ~clk;
        
    initial
    begin
        clk = 0;
        rst = 1;
        #35 rst = 0;
    end
    
endmodule
module MIPS_CP1_01_TB();


    logic   clk, rst;
    logic y;
    
    MIPS_CP1_01 mips1(clk, rst, y);
        
    always
        #30 clk = ~clk;
        
    initial
    begin
        clk = 0;
        rst = 1;
        #35 rst = 0;
    end
    
endmodule