data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:1: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory,data/full_repos/permissive/131921633/Mips/Type/Word.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory,data/full_repos/permissive/131921633/Mips/Type/Word.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory,data/full_repos/permissive/131921633/Mips/Type/Word.v.sv\n             Mips/Type/Word.v\n             Mips/Type/Word.v.v\n             Mips/Type/Word.v.sv\n             obj_dir/Mips/Type/Word.v\n             obj_dir/Mips/Type/Word.v.v\n             obj_dir/Mips/Type/Word.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:3: Cannot find include file: Mips/Control/Signal/Memory/Signal/ByteExtend.v\n`include "Mips/Control/Signal/Memory/Signal/ByteExtend.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:4: Cannot find include file: Mips/Control/Signal/Memory/Signal/ByteEnable.v\n`include "Mips/Control/Signal/Memory/Signal/ByteEnable.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:7: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_T\'\n ( `Mips_Control_Signal_Memory_Signal_ByteEnable_T(input) control\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:7: syntax error, unexpected \'(\', expecting \'[\'\n ( `Mips_Control_Signal_Memory_Signal_ByteEnable_T(input) control\n                                                   ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:8: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T(input) in\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:9: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T(output) out\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:13: syntax error, unexpected always\nalways @(*)\n^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:15: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteExtend_Unsigned\'\n  `Mips_Control_Signal_Memory_Signal_ByteExtend_Unsigned : ext = 1\'b0;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:16: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteExtend_Signed\'\n  `Mips_Control_Signal_Memory_Signal_ByteExtend_Signed   : ext = 1\'b1;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:21: syntax error, unexpected always\nalways @(*)\n^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:23: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_Word\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_Word : msb = in[31];\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:24: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_Half\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_Half : msb = in[15];\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:25: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_Byte\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_Byte : msb = in[7];\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:26: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_None\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_None : msb = 1\'b0;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:30: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (reg) out$;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:33: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_Word\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_Word : out$ = in;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:34: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_Half\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_Half : out$ = {{16{ext & msb}}, in[15:0]};\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:35: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_Byte\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_Byte : out$ = {{24{ext & msb}}, in[7:0]};\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/outMask.v:36: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_None\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_None : out$ = 32\'b0;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 20 error(s)\n'
module Mips_Datapath_Memory_outMask
	( `Mips_Control_Signal_Memory_Signal_ByteEnable_T(input) control
	, `Mips_Type_Word_T(input) in
	, `Mips_Type_Word_T(output) out
	);

reg ext;
always @(*)
	case(control)
		`Mips_Control_Signal_Memory_Signal_ByteExtend_Unsigned : ext = 1'b0;
		`Mips_Control_Signal_Memory_Signal_ByteExtend_Signed   : ext = 1'b1;
		default                                                : ext = 1'b1;
	endcase

reg msb;
always @(*)
	case(control)
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Word : msb = in[31];
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Half : msb = in[15];
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Byte : msb = in[7];
		`Mips_Control_Signal_Memory_Signal_ByteEnable_None : msb = 1'b0;
		default                                            : msb = 1'b0;
	endcase

`Mips_Type_Word_T (reg) out$;
always @(*)
	case(control)
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Word : out$ = in;
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Half : out$ = {{16{ext & msb}}, in[15:0]};
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Byte : out$ = {{24{ext & msb}}, in[7:0]};
		`Mips_Control_Signal_Memory_Signal_ByteEnable_None : out$ = 32'b0;
		default                                            : out$ = 32'b0;
	endcase
assign out = out$;

endmodule
module Mips_Datapath_Memory_outMask
	( `Mips_Control_Signal_Memory_Signal_ByteEnable_T(input) control
	, `Mips_Type_Word_T(input) in
	, `Mips_Type_Word_T(output) out
	);


reg ext;
always @(*)
	case(control)
		`Mips_Control_Signal_Memory_Signal_ByteExtend_Unsigned : ext = 1'b0;
		`Mips_Control_Signal_Memory_Signal_ByteExtend_Signed   : ext = 1'b1;
		default                                                : ext = 1'b1;
	endcase

reg msb;
always @(*)
	case(control)
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Word : msb = in[31];
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Half : msb = in[15];
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Byte : msb = in[7];
		`Mips_Control_Signal_Memory_Signal_ByteEnable_None : msb = 1'b0;
		default                                            : msb = 1'b0;
	endcase

`Mips_Type_Word_T (reg) out$;
always @(*)
	case(control)
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Word : out$ = in;
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Half : out$ = {{16{ext & msb}}, in[15:0]};
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Byte : out$ = {{24{ext & msb}}, in[7:0]};
		`Mips_Control_Signal_Memory_Signal_ByteEnable_None : out$ = 32'b0;
		default                                            : out$ = 32'b0;
	endcase
assign out = out$;

endmodule