data/full_repos/permissive/141582589/src/common_rtl/video/vin_pro.v
'utf-8' codec can't decode byte 0xbf in position 6: invalid start byte
1: b"%Error: data/full_repos/permissive/141582589/src/common_rtl/video/vin_pro.v:111: Cannot find file containing module: 'lite_fifo'\nlite_fifo#\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/lite_fifo\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/lite_fifo.v\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/lite_fifo.sv\n             lite_fifo\n             lite_fifo.v\n             lite_fifo.sv\n             obj_dir/lite_fifo\n             obj_dir/lite_fifo.v\n             obj_dir/lite_fifo.sv\n%Error: data/full_repos/permissive/141582589/src/common_rtl/video/vin_pro.v:136: Cannot find file containing module: 'vin_frame_buffer_ctrl'\nvin_frame_buffer_ctrl \n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module vin_pro
#(
	parameter MEM_DATA_BITS = 32,
	parameter INTERLACE = 1
)
(
	input rst_n,
	input pixel_clk,
	input vs,
	input f,
	input pixel_de,
	input[15:0] pixel_yc,
	input[11:0] clipper_top,
	input[11:0] clipper_left,
	input[11:0] clipper_width,
	input[11:0] clipper_height,
	input mem_clk,
	output  wr_burst_req,
	output[9:0] wr_burst_len,

	output[26:0] wr_burst_addr,
	input wr_burst_data_req,
	output[MEM_DATA_BITS - 1:0] wr_burst_data,
	input burst_finish,
	input[11:0] s_width,
	input[11:0] s_height,
	output[11:0] wr_max_line,
	input[1:0] base_addr,
	(* keep = "true" *)output[1:0] frame_addr
);
reg frame_flag = 1'b0;
reg vs_d0 = 1'b0;
reg vs_d1 = 1'b0;
reg vs_vclk_d0 = 1'b0;
reg vs_vclk_d1 = 1'b0;
wire[15:0] vfb_vin_data;
reg vfb_vin_de = 1'b0;
reg[11:0] vin_x_cnt = 12'd0;
reg[11:0] vin_y_cnt = 12'd0;
wire vfb_fifo_afull;
wire clipper_wr_en;

always@(posedge pixel_clk)
begin
	vs_d0 <= vs;
	vs_d1 <= vs_d0;
	frame_flag <= vs_d0 && ~vs_d1;
end

always@(posedge pixel_clk)
begin
	vs_vclk_d0 <= vs;
	vs_vclk_d1 <= vs_vclk_d0;
end

always@(posedge pixel_clk)
begin
	if(vs_vclk_d0 && ~vs_vclk_d1)
		vin_x_cnt <= 12'd1;
	else if(pixel_de)
		if(vin_x_cnt == s_width)
			vin_x_cnt <= 12'd1;
		else
			vin_x_cnt <= vin_x_cnt + 12'd1;
	else
		vin_x_cnt <= vin_x_cnt;		
end

always@(posedge pixel_clk)
begin
	if(vs_vclk_d0 && ~vs_vclk_d1)
		vin_y_cnt <= 12'd1;
	else if(pixel_de)
		if(vin_x_cnt == s_width)
			if(vin_y_cnt == s_height)
				vin_y_cnt <= 12'd1;
			else
				vin_y_cnt <= vin_y_cnt + 12'd1;
		else
			vin_y_cnt <= vin_y_cnt;	
	else
		vin_y_cnt <= vin_y_cnt;		
end

assign clipper_wr_en = (vin_x_cnt > clipper_left) && (vin_x_cnt <= clipper_left + clipper_width) && 
						(vin_y_cnt > clipper_top) && (vin_y_cnt <= clipper_top + clipper_height);
localparam buffer_f_depth_bits = 9;
reg[15:0] buffer_f_data;
wire buffer_f_rdclk;
wire buffer_f_rdreq;
wire buffer_f_wrclk;
reg buffer_f_wrreq;
wire[15:0] buffer_f_q;
wire buffer_f_rdempty;
wire[buffer_f_depth_bits - 1 : 0] buffer_f_rdusedw;
wire buffer_f_wrfull;
wire[buffer_f_depth_bits - 1 : 0] buffer_f_wrusedw;
assign buffer_f_rdreq = ~buffer_f_rdempty & ~vfb_fifo_afull;
assign buffer_f_rdclk = pixel_clk;
assign buffer_f_wrclk = pixel_clk;

always@(posedge buffer_f_wrclk)
begin
	buffer_f_wrreq <= pixel_de && clipper_wr_en;
	buffer_f_data <= pixel_yc;
end

lite_fifo#
(
	.COMMON_CLOCK(1),
	.ADDR_WIDTH(9),
	.DATA_WIDTH(16)
) buffer_f(
	.aclr(frame_flag),
	.data(buffer_f_data),
	.rdclk(buffer_f_rdclk),
	.rdreq(buffer_f_rdreq),
	.wrclk(buffer_f_wrclk),
	.wrreq(buffer_f_wrreq),
	.q(buffer_f_q),
	.rdempty(buffer_f_rdempty),
	.rdusedw(buffer_f_rdusedw),
	.wrfull(buffer_f_wrfull),
	.wrusedw(buffer_f_wrusedw));

always@(posedge buffer_f_rdclk)
begin
	vfb_vin_de <= buffer_f_rdreq;
end	

assign vfb_vin_data = buffer_f_q;

vin_frame_buffer_ctrl 
#
(
	.MEM_DATA_BITS(MEM_DATA_BITS),
	.INTERLACE(INTERLACE)
)
vin_frame_buffer_ctrl_m0(
	.rst_n(rst_n),
	.vin_clk(buffer_f_rdclk),
	.vin_vs(vs),
	.vin_f(f),
	.vin_de(vfb_vin_de),
	.vin_data(vfb_vin_data),
	.vin_width(clipper_width),
	.vin_height(clipper_height),
	.fifo_afull(vfb_fifo_afull),
	.mem_clk(mem_clk),
	.wr_burst_req(wr_burst_req),
	.wr_burst_len(wr_burst_len),
	.wr_burst_addr(wr_burst_addr),
	.wr_burst_data_req(wr_burst_data_req),
	.wr_burst_data(wr_burst_data),
	.burst_finish(burst_finish),
	.wr_max_line(wr_max_line),
	.base_addr(base_addr),
	.frame_addr(frame_addr)
);

endmodule
module vin_pro
#(
	parameter MEM_DATA_BITS = 32,
	parameter INTERLACE = 1
)
(
	input rst_n,
	input pixel_clk,
	input vs,
	input f,
	input pixel_de,
	input[15:0] pixel_yc,
	input[11:0] clipper_top,
	input[11:0] clipper_left,
	input[11:0] clipper_width,
	input[11:0] clipper_height,
	input mem_clk,
	output  wr_burst_req,
	output[9:0] wr_burst_len,

	output[26:0] wr_burst_addr,
	input wr_burst_data_req,
	output[MEM_DATA_BITS - 1:0] wr_burst_data,
	input burst_finish,
	input[11:0] s_width,
	input[11:0] s_height,
	output[11:0] wr_max_line,
	input[1:0] base_addr,
	(* keep = "true" *)output[1:0] frame_addr
);

reg frame_flag = 1'b0;
reg vs_d0 = 1'b0;
reg vs_d1 = 1'b0;
reg vs_vclk_d0 = 1'b0;
reg vs_vclk_d1 = 1'b0;
wire[15:0] vfb_vin_data;
reg vfb_vin_de = 1'b0;
reg[11:0] vin_x_cnt = 12'd0;
reg[11:0] vin_y_cnt = 12'd0;
wire vfb_fifo_afull;
wire clipper_wr_en;

always@(posedge pixel_clk)
begin
	vs_d0 <= vs;
	vs_d1 <= vs_d0;
	frame_flag <= vs_d0 && ~vs_d1;
end

always@(posedge pixel_clk)
begin
	vs_vclk_d0 <= vs;
	vs_vclk_d1 <= vs_vclk_d0;
end

always@(posedge pixel_clk)
begin
	if(vs_vclk_d0 && ~vs_vclk_d1)
		vin_x_cnt <= 12'd1;
	else if(pixel_de)
		if(vin_x_cnt == s_width)
			vin_x_cnt <= 12'd1;
		else
			vin_x_cnt <= vin_x_cnt + 12'd1;
	else
		vin_x_cnt <= vin_x_cnt;		
end

always@(posedge pixel_clk)
begin
	if(vs_vclk_d0 && ~vs_vclk_d1)
		vin_y_cnt <= 12'd1;
	else if(pixel_de)
		if(vin_x_cnt == s_width)
			if(vin_y_cnt == s_height)
				vin_y_cnt <= 12'd1;
			else
				vin_y_cnt <= vin_y_cnt + 12'd1;
		else
			vin_y_cnt <= vin_y_cnt;	
	else
		vin_y_cnt <= vin_y_cnt;		
end

assign clipper_wr_en = (vin_x_cnt > clipper_left) && (vin_x_cnt <= clipper_left + clipper_width) && 
						(vin_y_cnt > clipper_top) && (vin_y_cnt <= clipper_top + clipper_height);
localparam buffer_f_depth_bits = 9;
reg[15:0] buffer_f_data;
wire buffer_f_rdclk;
wire buffer_f_rdreq;
wire buffer_f_wrclk;
reg buffer_f_wrreq;
wire[15:0] buffer_f_q;
wire buffer_f_rdempty;
wire[buffer_f_depth_bits - 1 : 0] buffer_f_rdusedw;
wire buffer_f_wrfull;
wire[buffer_f_depth_bits - 1 : 0] buffer_f_wrusedw;
assign buffer_f_rdreq = ~buffer_f_rdempty & ~vfb_fifo_afull;
assign buffer_f_rdclk = pixel_clk;
assign buffer_f_wrclk = pixel_clk;

always@(posedge buffer_f_wrclk)
begin
	buffer_f_wrreq <= pixel_de && clipper_wr_en;
	buffer_f_data <= pixel_yc;
end

lite_fifo#
(
	.COMMON_CLOCK(1),
	.ADDR_WIDTH(9),
	.DATA_WIDTH(16)
) buffer_f(
	.aclr(frame_flag),
	.data(buffer_f_data),
	.rdclk(buffer_f_rdclk),
	.rdreq(buffer_f_rdreq),
	.wrclk(buffer_f_wrclk),
	.wrreq(buffer_f_wrreq),
	.q(buffer_f_q),
	.rdempty(buffer_f_rdempty),
	.rdusedw(buffer_f_rdusedw),
	.wrfull(buffer_f_wrfull),
	.wrusedw(buffer_f_wrusedw));

always@(posedge buffer_f_rdclk)
begin
	vfb_vin_de <= buffer_f_rdreq;
end	

assign vfb_vin_data = buffer_f_q;

vin_frame_buffer_ctrl 
#
(
	.MEM_DATA_BITS(MEM_DATA_BITS),
	.INTERLACE(INTERLACE)
)
vin_frame_buffer_ctrl_m0(
	.rst_n(rst_n),
	.vin_clk(buffer_f_rdclk),
	.vin_vs(vs),
	.vin_f(f),
	.vin_de(vfb_vin_de),
	.vin_data(vfb_vin_data),
	.vin_width(clipper_width),
	.vin_height(clipper_height),
	.fifo_afull(vfb_fifo_afull),
	.mem_clk(mem_clk),
	.wr_burst_req(wr_burst_req),
	.wr_burst_len(wr_burst_len),
	.wr_burst_addr(wr_burst_addr),
	.wr_burst_data_req(wr_burst_data_req),
	.wr_burst_data(wr_burst_data),
	.burst_finish(burst_finish),
	.wr_max_line(wr_max_line),
	.base_addr(base_addr),
	.frame_addr(frame_addr)
);

endmodule