data/full_repos/permissive/152986713/ice40/sprite_scanline_renderer.v
 line:273 column:19: Illegal character "'"
1: b'%Error: data/full_repos/permissive/152986713/ice40/sprite_scanline_renderer.v:2: Cannot find include file: hvsync_generator.v\n`include "hvsync_generator.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v.v\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v.sv\n             hvsync_generator.v\n             hvsync_generator.v.v\n             hvsync_generator.v.sv\n             obj_dir/hvsync_generator.v\n             obj_dir/hvsync_generator.v.v\n             obj_dir/hvsync_generator.v.sv\n%Error: data/full_repos/permissive/152986713/ice40/sprite_scanline_renderer.v:3: Cannot find include file: ram.v\n`include "ram.v" \n         ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module sprite_scanline_renderer(clk, reset, hpos, vpos, rgb,
                               ram_addr, ram_data, ram_busy,
                               rom_addr, rom_data);

  parameter NB = 5;
  parameter MB = 3;
  
  localparam N = 1<<NB;
  localparam M = 1<<MB;
  
  input clk, reset;
  input [8:0] hpos;
  input [8:0] vpos;
  output [3:0] rgb;

  output [NB:0] ram_addr;
  input [15:0] ram_data;
  output ram_busy;
  
  output [15:0] rom_addr;
  input [15:0] rom_data;
  

  reg [7:0] sprite_xpos[0:N-1];
  reg [7:0] sprite_ypos[0:N-1];
  reg [7:0] sprite_attr[0:N-1];


  reg [7:0] line_xpos[0:M-1];
  reg [7:0] line_yofs[0:M-1];
  reg [7:0] line_attr[0:M-1];
  reg line_active[0:M-1];
  

  reg [NB-1:0] i;
  reg [MB-1:0] j;
  reg [MB-1:0] k;
  reg [7:0] z;
  reg [8:0] write_ofs;
  reg [15:0] out_bitmap;
  reg [7:0] out_attr;
  reg romload;


  wire [NB-1:0] load_index = hpos[NB:1];


  reg [3:0] scanline[0:511];  
  

  wire [8:0] read_bufidx = {vpos[0], hpos[7:0]};


  always @(posedge clk) begin
    
    ram_busy <= 0;

    if (reset || vpos[8]) begin



      if (vpos == 260 && hpos < N*2+8) begin
        ram_busy <= 1;
        case (hpos[0])
          0: begin
            ram_addr <= {load_index, 1'b0};

            sprite_xpos[load_index] <= ram_data[7:0];
            sprite_ypos[load_index] <= ram_data[15:8];
          end
          1: begin
            ram_addr <= {load_index, 1'b1};

            sprite_attr[load_index] <= ram_data[7:0];
          end
        endcase
      end
    end else if (hpos < N*2) begin

      k <= 0;
      romload <= 0;

      case (hpos[0])

        0: z <= 8'(vpos - sprite_ypos[i]);
        1: begin

          if (z < 16) begin
            line_xpos[j] <= sprite_xpos[i];
            line_yofs[j] <= z;
            line_attr[j] <= sprite_attr[i];
            line_active[j] <= 1;
            j <= j + 1;
          end
          i <= i + 1;
        end
      endcase
    end else if (hpos < N*2+M*18) begin

      j <= 0;

      if (out_bitmap == 0) begin
        case (romload)
          0: begin

            rom_addr <= {4'b0, line_attr[k][7:4], line_yofs[k]};
          end
          1: begin

            write_ofs <= {~vpos[0], line_xpos[k]};

            out_bitmap <= line_active[k] ? rom_data : 0;

            out_attr <= line_attr[k];

            line_active[k] <= 0;

            k <= k + 1;
          end
        endcase
        romload <= !romload;
      end else begin

        if (out_bitmap[0])
          scanline[write_ofs] <= out_attr[3:0];

        out_bitmap <= out_bitmap >> 1;

        write_ofs <= write_ofs + 1;
      end
    end else begin

      i <= 0;
    end
    

    rgb <= scanline[read_bufidx];
    scanline[read_bufidx] <= 0;
  end
  
endmodule
module sprite_scanline_renderer(clk, reset, hpos, vpos, rgb,
                               ram_addr, ram_data, ram_busy,
                               rom_addr, rom_data);


  parameter NB = 5;
  parameter MB = 3;
  
  localparam N = 1<<NB;
  localparam M = 1<<MB;
  
  input clk, reset;
  input [8:0] hpos;
  input [8:0] vpos;
  output [3:0] rgb;

  output [NB:0] ram_addr;
  input [15:0] ram_data;
  output ram_busy;
  
  output [15:0] rom_addr;
  input [15:0] rom_data;
  

  reg [7:0] sprite_xpos[0:N-1];
  reg [7:0] sprite_ypos[0:N-1];
  reg [7:0] sprite_attr[0:N-1];


  reg [7:0] line_xpos[0:M-1];
  reg [7:0] line_yofs[0:M-1];
  reg [7:0] line_attr[0:M-1];
  reg line_active[0:M-1];
  

  reg [NB-1:0] i;
  reg [MB-1:0] j;
  reg [MB-1:0] k;
  reg [7:0] z;
  reg [8:0] write_ofs;
  reg [15:0] out_bitmap;
  reg [7:0] out_attr;
  reg romload;


  wire [NB-1:0] load_index = hpos[NB:1];


  reg [3:0] scanline[0:511];  
  

  wire [8:0] read_bufidx = {vpos[0], hpos[7:0]};


  always @(posedge clk) begin
    
    ram_busy <= 0;

    if (reset || vpos[8]) begin



      if (vpos == 260 && hpos < N*2+8) begin
        ram_busy <= 1;
        case (hpos[0])
          0: begin
            ram_addr <= {load_index, 1'b0};

            sprite_xpos[load_index] <= ram_data[7:0];
            sprite_ypos[load_index] <= ram_data[15:8];
          end
          1: begin
            ram_addr <= {load_index, 1'b1};

            sprite_attr[load_index] <= ram_data[7:0];
          end
        endcase
      end
    end else if (hpos < N*2) begin

      k <= 0;
      romload <= 0;

      case (hpos[0])

        0: z <= 8'(vpos - sprite_ypos[i]);
        1: begin

          if (z < 16) begin
            line_xpos[j] <= sprite_xpos[i];
            line_yofs[j] <= z;
            line_attr[j] <= sprite_attr[i];
            line_active[j] <= 1;
            j <= j + 1;
          end
          i <= i + 1;
        end
      endcase
    end else if (hpos < N*2+M*18) begin

      j <= 0;

      if (out_bitmap == 0) begin
        case (romload)
          0: begin

            rom_addr <= {4'b0, line_attr[k][7:4], line_yofs[k]};
          end
          1: begin

            write_ofs <= {~vpos[0], line_xpos[k]};

            out_bitmap <= line_active[k] ? rom_data : 0;

            out_attr <= line_attr[k];

            line_active[k] <= 0;

            k <= k + 1;
          end
        endcase
        romload <= !romload;
      end else begin

        if (out_bitmap[0])
          scanline[write_ofs] <= out_attr[3:0];

        out_bitmap <= out_bitmap >> 1;

        write_ofs <= write_ofs + 1;
      end
    end else begin

      i <= 0;
    end
    

    rgb <= scanline[read_bufidx];
    scanline[read_bufidx] <= 0;
  end
  
endmodule