data/full_repos/permissive/179980995/FPU/before roll.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/179980995/FPU/before\n        ... Looked in:\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/data/full_repos/permissive/179980995/FPU/before\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/data/full_repos/permissive/179980995/FPU/before.v\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/data/full_repos/permissive/179980995/FPU/before.sv\n             data/full_repos/permissive/179980995/FPU/before\n             data/full_repos/permissive/179980995/FPU/before.v\n             data/full_repos/permissive/179980995/FPU/before.sv\n             obj_dir/data/full_repos/permissive/179980995/FPU/before\n             obj_dir/data/full_repos/permissive/179980995/FPU/before.v\n             obj_dir/data/full_repos/permissive/179980995/FPU/before.sv\n%Error: Cannot find file containing module: roll.v\n%Error: Exiting due to 2 error(s)\n'
module reciprocal (in, out);
	input [31:0] in;

	output [31:0] out;

	wire [31:0] D;
	wire [31:0] N0;
	wire [31:0] N1;
	wire [31:0] N2;

	assign out[31] = in[31];
	assign out[22:0] = N2[22:0];
	assign out[30:23] = (D==9'b100000000)? 9'h102 - in[30:23] : 9'h101 - in[30:23];

	assign D = {1'b0, 8'h80, in[22:0]};

	wire [31:0] C1;
	assign C1 = 32'h4034B4B5;
	wire [31:0] C2;
	assign C2 = 32'h3FF0F0F1;
	wire [31:0] C3;
	assign C3 = 32'h40000000;



	wire [31:0] S0_2D_out;
	wire [31:0] S1_DN0_out;
	wire [31:0] S1_2min_DN0_out;
	wire [31:0] S2_DN1_out;
	wire [31:0] S2_2minDN1_out;

	wire [31:0] S0_N0_in;

	assign S0_N0_in = {~S0_2D_out[31], S0_2D_out[30:0]};


	multiplier S0_2D
	(
		.a(C2),
		.b(D),
		.out(S0_2D_out)
	);

	adder S0_N0
	(
		.a(C1),
		.b(S0_N0_in),
		.out(N0)
	);


	multiplier S1_DN0
	(
		.a(D),
		.b(N0),
		.out(S1_DN0_out)
	);

	adder S1_2minDN0
	(
		.a(C3),
		.b({~S1_DN0_out[31], S1_DN0_out[30:0]}),
		.out(S1_2min_DN0_out)
	);

	multiplier S1_N1
	(
		.a(N0),
		.b(S1_2min_DN0_out),
		.out(N1)
	);


	multiplier S2_DN1
	(
		.a(D),
		.b(N1),
		.out(S2_DN1_out)
	);

	adder S2_2minDN1
	(
		.a(C3),
		.b({~S2_DN1_out[31], S2_DN1_out[30:0]}),
		.out(S2_2minDN1_out)
	);

	multiplier S2_N2
	(
		.a(N1),
		.b(S2_2minDN1_out),
		.out(N2)
	);

endmodule
module reciprocal (in, out);

	input [31:0] in;

	output [31:0] out;

	wire [31:0] D;
	wire [31:0] N0;
	wire [31:0] N1;
	wire [31:0] N2;

	assign out[31] = in[31];
	assign out[22:0] = N2[22:0];
	assign out[30:23] = (D==9'b100000000)? 9'h102 - in[30:23] : 9'h101 - in[30:23];

	assign D = {1'b0, 8'h80, in[22:0]};

	wire [31:0] C1;
	assign C1 = 32'h4034B4B5;
	wire [31:0] C2;
	assign C2 = 32'h3FF0F0F1;
	wire [31:0] C3;
	assign C3 = 32'h40000000;



	wire [31:0] S0_2D_out;
	wire [31:0] S1_DN0_out;
	wire [31:0] S1_2min_DN0_out;
	wire [31:0] S2_DN1_out;
	wire [31:0] S2_2minDN1_out;

	wire [31:0] S0_N0_in;

	assign S0_N0_in = {~S0_2D_out[31], S0_2D_out[30:0]};


	multiplier S0_2D
	(
		.a(C2),
		.b(D),
		.out(S0_2D_out)
	);

	adder S0_N0
	(
		.a(C1),
		.b(S0_N0_in),
		.out(N0)
	);


	multiplier S1_DN0
	(
		.a(D),
		.b(N0),
		.out(S1_DN0_out)
	);

	adder S1_2minDN0
	(
		.a(C3),
		.b({~S1_DN0_out[31], S1_DN0_out[30:0]}),
		.out(S1_2min_DN0_out)
	);

	multiplier S1_N1
	(
		.a(N0),
		.b(S1_2min_DN0_out),
		.out(N1)
	);


	multiplier S2_DN1
	(
		.a(D),
		.b(N1),
		.out(S2_DN1_out)
	);

	adder S2_2minDN1
	(
		.a(C3),
		.b({~S2_DN1_out[31], S2_DN1_out[30:0]}),
		.out(S2_2minDN1_out)
	);

	multiplier S2_N2
	(
		.a(N1),
		.b(S2_2minDN1_out),
		.out(N2)
	);

endmodule