data/full_repos/permissive/108382235/SingleCycle.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/SingleCycle.v:290: Multiple top level modules\n                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                         : ... Top module \'SingleCycle\'\nmodule SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);\n       ^~~~~~~~~~~\n                                                                         : ... Top module \'And_1bit\'\nmodule And_1bit(Q, I1, I2);\n       ^~~~~~~~\n                                                                         : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n       ^~~~~~~~~~~~\n                                                                         : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n       ^~~~~~~~~~\n                                                                         : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n       ^~~~~~~~~~\n                                                                         : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:429: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                      : ... In instance SingleCycle.M_DataMemory\n  if (MemRead) ReadData=Dmemory[Address[31:2]];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:436: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                      : ... In instance SingleCycle.M_DataMemory\n  else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/SingleCycle.v:413: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                      : ... In instance SingleCycle.M_InstructionMemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n                                                                        ^\n%Error: Exiting due to 4 warning(s)\n'
module SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);
	input SwitchClk_10, reset;

	output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;

	output [31:0] PCOut;
	
	reg [31:0] PCOut=0; 
	wire [31:0] PCIn, Instruction, ReadData1, ReadData2, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, WriteData_RegFile, Immediate_Sign_32, Immediate_Zero_32, Immediate_32;
	wire [31:0] ALUInput2, ALUResult, ReadData, PCAddFour, BranchOffset, BranchAddress, PCNoJump, ShowNum;
	wire RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi, Zero, BranchMuxSignal;
	wire [1:0] ALUOp;
	wire [4:0] WriteRegister;
	wire [3:0] ALUControlSignal;
	wire [27:0] JumpImmediate;
	
	always @(posedge SwitchClk_10, posedge reset) begin
		if (reset==1) PCOut=0;
		else PCOut=PCIn;
	end
	InstructionMemory M_InstructionMemory(Instruction, PCOut);
	Control M_Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, Instruction[31:26]);
	Mux_5bit_2to1 M_Mux_WriteReg(WriteRegister, Instruction[20:16], Instruction[15:11], RegDst);
	RegisterFile M_RegisterFile(ReadData1,ReadData2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Instruction[25:21], Instruction[20:16],WriteRegister,WriteData_RegFile,RegWrite,SwitchClk_10, reset);
	SignExtend M_SignExtend(Immediate_Sign_32, Instruction[15:0]);
	ZeroExtend M_ZeroExtend(Immediate_Zero_32, Instruction[15:0]);
	Mux_32bit_2to1 M_Mux_Immediate(Immediate_32, Immediate_Sign_32, Immediate_Zero_32, Andi);
	Alucontrol M_Alucontrol(ALUControlSignal,ALUOp,Instruction[5:0]);
	Mux_32bit_2to1 M_Mux_ALUSrc(ALUInput2, Immediate_32, ReadData2, ALUSrc);
	ALU M_ALU(ALUResult,Zero,ALUControlSignal,ReadData1,ALUInput2);
	DataMemory M_DataMemory(ReadData, ALUResult, ReadData2, MemWrite, MemRead, SwitchClk_10, reset);
	Mux_32bit_2to1 M_Mux_MemtoReg(WriteData_RegFile, ALUResult, ReadData, MemtoReg);
	AddFour M_AddFour(PCAddFour, PCOut);
	ShiftLeftTwo_26to28 M_Shifter_Jump(JumpImmediate, Instruction[25:0]);
	ShiftLeftTwo_32to32 M_Shifter_Branch(BranchOffset, Immediate_32);
	Adder_32bit M_AdderBranch(BranchAddress, PCAddFour, BranchOffset);
	BrenchDetection M_BranchDetection(BranchMuxSignal, Branch, BranchN, Zero);
	Mux_32bit_2to1 M_Mux_Branch(PCNoJump, PCAddFour, BranchAddress, BranchMuxSignal);
	Mux_32bit_2to1 M_Mux_Jump(PCIn, PCNoJump, {PCAddFour[31:28],JumpImmediate}, Jump);

	
endmodule
module SingleCycle(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,PCOut, SwitchClk_10, reset);

	input SwitchClk_10, reset;

	output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;

	output [31:0] PCOut;
	
	reg [31:0] PCOut=0; 
	wire [31:0] PCIn, Instruction, ReadData1, ReadData2, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, WriteData_RegFile, Immediate_Sign_32, Immediate_Zero_32, Immediate_32;
	wire [31:0] ALUInput2, ALUResult, ReadData, PCAddFour, BranchOffset, BranchAddress, PCNoJump, ShowNum;
	wire RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Andi, Zero, BranchMuxSignal;
	wire [1:0] ALUOp;
	wire [4:0] WriteRegister;
	wire [3:0] ALUControlSignal;
	wire [27:0] JumpImmediate;
	
	always @(posedge SwitchClk_10, posedge reset) begin
		if (reset==1) PCOut=0;
		else PCOut=PCIn;
	end
	InstructionMemory M_InstructionMemory(Instruction, PCOut);
	Control M_Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, Instruction[31:26]);
	Mux_5bit_2to1 M_Mux_WriteReg(WriteRegister, Instruction[20:16], Instruction[15:11], RegDst);
	RegisterFile M_RegisterFile(ReadData1,ReadData2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Instruction[25:21], Instruction[20:16],WriteRegister,WriteData_RegFile,RegWrite,SwitchClk_10, reset);
	SignExtend M_SignExtend(Immediate_Sign_32, Instruction[15:0]);
	ZeroExtend M_ZeroExtend(Immediate_Zero_32, Instruction[15:0]);
	Mux_32bit_2to1 M_Mux_Immediate(Immediate_32, Immediate_Sign_32, Immediate_Zero_32, Andi);
	Alucontrol M_Alucontrol(ALUControlSignal,ALUOp,Instruction[5:0]);
	Mux_32bit_2to1 M_Mux_ALUSrc(ALUInput2, Immediate_32, ReadData2, ALUSrc);
	ALU M_ALU(ALUResult,Zero,ALUControlSignal,ReadData1,ALUInput2);
	DataMemory M_DataMemory(ReadData, ALUResult, ReadData2, MemWrite, MemRead, SwitchClk_10, reset);
	Mux_32bit_2to1 M_Mux_MemtoReg(WriteData_RegFile, ALUResult, ReadData, MemtoReg);
	AddFour M_AddFour(PCAddFour, PCOut);
	ShiftLeftTwo_26to28 M_Shifter_Jump(JumpImmediate, Instruction[25:0]);
	ShiftLeftTwo_32to32 M_Shifter_Branch(BranchOffset, Immediate_32);
	Adder_32bit M_AdderBranch(BranchAddress, PCAddFour, BranchOffset);
	BrenchDetection M_BranchDetection(BranchMuxSignal, Branch, BranchN, Zero);
	Mux_32bit_2to1 M_Mux_Branch(PCNoJump, PCAddFour, BranchAddress, BranchMuxSignal);
	Mux_32bit_2to1 M_Mux_Jump(PCIn, PCNoJump, {PCAddFour[31:28],JumpImmediate}, Jump);

	
endmodule