data/full_repos/permissive/118895561/Project 1/m_w.v
1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561.sv\n             1,data/full_repos/permissive/118895561\n             1,data/full_repos/permissive/118895561.v\n             1,data/full_repos/permissive/118895561.sv\n             obj_dir/1,data/full_repos/permissive/118895561\n             obj_dir/1,data/full_repos/permissive/118895561.v\n             obj_dir/1,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 1/m_w.v\n%Error: Exiting due to 3 error(s)\n'
module m_w(
	input  clk,
	input  reset,
	input  [31:0] Real_MEM_OUT_M,
	output [31:0] MEM_OUT_W,
	input  [31:0] ALU_OUT_M,
	output [31:0] ALU_OUT_W,
	input  [31:0] PCadd4M,
	output [31:0] PCadd4W,
	input  [31:0] PC_M,
	output [31:0] PC_W,
	input  [1:0] RES_M,
	output [1:0] RES_W,
	input  [4:0] WRITE_ADDR_M,
	output [4:0] WRITE_ADDR_W,
	input  [1:0] MEM_TO_REG_M, 
	input  REG_WRITE_ENABLED_M,
	output [1:0] MEM_TO_REG_W, 
	output REG_WRITE_ENABLED_W
    );
regfile #(2)  R_MW_7 (.clk(clk), .reset(reset), .Data_In(RES_M), .Data_Out(RES_W));
regfile #(5)  R_MW_1 (.clk(clk), .reset(reset), .Data_In(WRITE_ADDR_M), .Data_Out(WRITE_ADDR_W));
regfile #(32) R_MW_2 (.clk(clk), .reset(reset), .Data_In(Real_MEM_OUT_M), .Data_Out(MEM_OUT_W));
regfile #(32) R_MW_3 (.clk(clk), .reset(reset), .Data_In(ALU_OUT_M), .Data_Out(ALU_OUT_W));
regfile #(32) R_MW_4 (.clk(clk), .reset(reset), .Data_In(PCadd4M), .Data_Out(PCadd4W));
regfile #(3)  R_MW_5 (.clk(clk), .reset(reset), .Data_In({MEM_TO_REG_M, REG_WRITE_ENABLED_M}), .Data_Out({MEM_TO_REG_W, REG_WRITE_ENABLED_W}));
regfile #(32) R_MW_6 (.clk(clk), .reset(reset), .Data_In(PC_M), .Data_Out(PC_W));

endmodule
module m_w(
	input  clk,
	input  reset,
	input  [31:0] Real_MEM_OUT_M,
	output [31:0] MEM_OUT_W,
	input  [31:0] ALU_OUT_M,
	output [31:0] ALU_OUT_W,
	input  [31:0] PCadd4M,
	output [31:0] PCadd4W,
	input  [31:0] PC_M,
	output [31:0] PC_W,
	input  [1:0] RES_M,
	output [1:0] RES_W,
	input  [4:0] WRITE_ADDR_M,
	output [4:0] WRITE_ADDR_W,
	input  [1:0] MEM_TO_REG_M, 
	input  REG_WRITE_ENABLED_M,
	output [1:0] MEM_TO_REG_W, 
	output REG_WRITE_ENABLED_W
    );

regfile #(2)  R_MW_7 (.clk(clk), .reset(reset), .Data_In(RES_M), .Data_Out(RES_W));
regfile #(5)  R_MW_1 (.clk(clk), .reset(reset), .Data_In(WRITE_ADDR_M), .Data_Out(WRITE_ADDR_W));
regfile #(32) R_MW_2 (.clk(clk), .reset(reset), .Data_In(Real_MEM_OUT_M), .Data_Out(MEM_OUT_W));
regfile #(32) R_MW_3 (.clk(clk), .reset(reset), .Data_In(ALU_OUT_M), .Data_Out(ALU_OUT_W));
regfile #(32) R_MW_4 (.clk(clk), .reset(reset), .Data_In(PCadd4M), .Data_Out(PCadd4W));
regfile #(3)  R_MW_5 (.clk(clk), .reset(reset), .Data_In({MEM_TO_REG_M, REG_WRITE_ENABLED_M}), .Data_Out({MEM_TO_REG_W, REG_WRITE_ENABLED_W}));
regfile #(32) R_MW_6 (.clk(clk), .reset(reset), .Data_In(PC_M), .Data_Out(PC_W));

endmodule