data/full_repos/permissive/20726090/hw/vlog/lib/xs6_addsub_n.v
 line:2: before: "/"
1: b"%Error: data/full_repos/permissive/20726090/hw/vlog/lib/xs6_addsub_n.v:66: Cannot find file containing module: 'DSP48A1'\nDSP48A1  #(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20726090/hw/vlog/lib,data/full_repos/permissive/20726090/DSP48A1\n             data/full_repos/permissive/20726090/hw/vlog/lib,data/full_repos/permissive/20726090/DSP48A1.v\n             data/full_repos/permissive/20726090/hw/vlog/lib,data/full_repos/permissive/20726090/DSP48A1.sv\n             DSP48A1\n             DSP48A1.v\n             DSP48A1.sv\n             obj_dir/DSP48A1\n             obj_dir/DSP48A1.v\n             obj_dir/DSP48A1.sv\n%Error: Exiting due to 1 error(s)\n"
module xs6_addsub_n #(
parameter WIDTH=32
)(
input [WIDTH-1:0]   i_a,
input [WIDTH-1:0]   i_b,
input               i_cin,
input               i_sub,

output [WIDTH-1:0]  o_sum,
output              o_co
);


wire [7:0]  opmode;
wire [47:0] in_a, in_b;
wire [47:0] out;

assign opmode = {i_sub, 1'd0, i_cin, 1'd0, 2'd3, 2'd3 };
assign in_a   = {{48-WIDTH{1'd0}}, i_a};
assign in_b   = {{48-WIDTH{1'd0}}, i_b};
assign o_sum  = out[WIDTH-1:0];
assign o_co   = out[WIDTH];


DSP48A1  #(

    .A1REG          ( 0         ),
    .B0REG          ( 0         ),
    .B1REG          ( 0         ),
    .CARRYINREG     ( 0         ),
    .CARRYOUTREG    ( 0         ),
    .CREG           ( 0         ),
    .DREG           ( 0         ),
    .MREG           ( 0         ),
    .OPMODEREG      ( 0         ),
    .PREG           ( 0         ),
    .CARRYINSEL     ("OPMODE5"  ),
    .RSTTYPE        ( "SYNC"    )
)

u_dsp48 (

    .BCOUT         (                        ),
    .CARRYOUT      (                        ),
    .CARRYOUTF     (                        ), 
    .M             (                        ),
    .P             ( out                    ),
    .PCOUT         (                        ),
                                           

    .CLK           ( 1'd0                   ),
                                           
    .A             (         in_b[35:18]    ),
    .B             (         in_b[17:00]    ),
    .C             (         in_a           ),
    .D             ( {6'd0,  in_b[47:36]}   ),

    .CARRYIN       ( 1'd0                   ),
    .OPMODE        ( opmode                 ),
    .PCIN          ( 48'd0                  ),


    .CEA           ( 1'd1                   ),
    .CEB           ( 1'd1                   ),
    .CEC           ( 1'd1                   ),
    .CED           ( 1'd1                   ),
    .CEM           ( 1'd1                   ),
    .CEP           ( 1'd1                   ),
    .CECARRYIN     ( 1'd1                   ),
    .CEOPMODE      ( 1'd1                   ),
    

    .RSTA          ( 1'd0                   ),
    .RSTB          ( 1'd0                   ),
    .RSTC          ( 1'd0                   ),
    .RSTCARRYIN    ( 1'd0                   ),
    .RSTD          ( 1'd0                   ),
    .RSTM          ( 1'd0                   ),
    .RSTOPMODE     ( 1'd0                   ),
    .RSTP          ( 1'd0                   )
    );
    
    
endmodule
module xs6_addsub_n #(
parameter WIDTH=32
)(
input [WIDTH-1:0]   i_a,
input [WIDTH-1:0]   i_b,
input               i_cin,
input               i_sub,

output [WIDTH-1:0]  o_sum,
output              o_co
);



wire [7:0]  opmode;
wire [47:0] in_a, in_b;
wire [47:0] out;

assign opmode = {i_sub, 1'd0, i_cin, 1'd0, 2'd3, 2'd3 };
assign in_a   = {{48-WIDTH{1'd0}}, i_a};
assign in_b   = {{48-WIDTH{1'd0}}, i_b};
assign o_sum  = out[WIDTH-1:0];
assign o_co   = out[WIDTH];


DSP48A1  #(

    .A1REG          ( 0         ),
    .B0REG          ( 0         ),
    .B1REG          ( 0         ),
    .CARRYINREG     ( 0         ),
    .CARRYOUTREG    ( 0         ),
    .CREG           ( 0         ),
    .DREG           ( 0         ),
    .MREG           ( 0         ),
    .OPMODEREG      ( 0         ),
    .PREG           ( 0         ),
    .CARRYINSEL     ("OPMODE5"  ),
    .RSTTYPE        ( "SYNC"    )
)

u_dsp48 (

    .BCOUT         (                        ),
    .CARRYOUT      (                        ),
    .CARRYOUTF     (                        ), 
    .M             (                        ),
    .P             ( out                    ),
    .PCOUT         (                        ),
                                           

    .CLK           ( 1'd0                   ),
                                           
    .A             (         in_b[35:18]    ),
    .B             (         in_b[17:00]    ),
    .C             (         in_a           ),
    .D             ( {6'd0,  in_b[47:36]}   ),

    .CARRYIN       ( 1'd0                   ),
    .OPMODE        ( opmode                 ),
    .PCIN          ( 48'd0                  ),


    .CEA           ( 1'd1                   ),
    .CEB           ( 1'd1                   ),
    .CEC           ( 1'd1                   ),
    .CED           ( 1'd1                   ),
    .CEM           ( 1'd1                   ),
    .CEP           ( 1'd1                   ),
    .CECARRYIN     ( 1'd1                   ),
    .CEOPMODE      ( 1'd1                   ),
    

    .RSTA          ( 1'd0                   ),
    .RSTB          ( 1'd0                   ),
    .RSTC          ( 1'd0                   ),
    .RSTCARRYIN    ( 1'd0                   ),
    .RSTD          ( 1'd0                   ),
    .RSTM          ( 1'd0                   ),
    .RSTOPMODE     ( 1'd0                   ),
    .RSTP          ( 1'd0                   )
    );
    
    
endmodule