data/full_repos/permissive/105729015/Next_prime_finder.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Cell has missing pin: \'rem0\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4)));  \n             ^~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Cell has missing pin: \'rem0\'\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n             ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Cell has missing pin: \'rem0\'\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n             ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Cell has missing pin: \'rem0\'\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n             ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Cell has missing pin: \'rem0\'\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n             ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Cell has missing pin: \'rem0\'\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n             ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Cell has missing pin: \'rem0\'\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n             ^~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Cell has missing pin: \'rem0\'\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1));  \n             ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Signal definition not found, creating implicitly: \'c\'\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4)));  \n                                                                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:459: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test1(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d2), .done(remainder_done[1]), .rem0(rem0[1]));\n                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:460: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h4\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test2(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d4), .done(remainder_done[2]), .rem0(rem0[2]));\n                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:461: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h6\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test3(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d6), .done(remainder_done[3]), .rem0(rem0[3]));\n                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:462: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h8\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test4(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d8), .done(remainder_done[4]), .rem0(rem0[4]));\n                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:463: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'ha\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test5(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d10), .done(remainder_done[5]), .rem0(rem0[5]));\n                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:464: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'hc\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test6(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d12), .done(remainder_done[6]), .rem0(rem0[6]));\n                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:465: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'he\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test7(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d14), .done(remainder_done[7]), .rem0(rem0[7]));\n                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:466: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test8(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d16), .done(remainder_done[8]), .rem0(rem0[8]));\n                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:467: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h12\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test9(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d18), .done(remainder_done[9]), .rem0(rem0[9]));\n                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:468: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test10(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d20), .done(remainder_done[10]), .rem0(rem0[10]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:469: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h16\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test11(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d22), .done(remainder_done[11]), .rem0(rem0[11]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:470: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h18\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test12(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d24), .done(remainder_done[12]), .rem0(rem0[12]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:471: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1a\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test13(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d26), .done(remainder_done[13]), .rem0(rem0[13]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:472: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1c\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test14(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d28), .done(remainder_done[14]), .rem0(rem0[14]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:473: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h1e\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test15(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d30), .done(remainder_done[15]), .rem0(rem0[15]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:474: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test16(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d32), .done(remainder_done[16]), .rem0(rem0[16]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:475: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h22\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test17(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d34), .done(remainder_done[17]), .rem0(rem0[17]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:476: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h24\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test18(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d36), .done(remainder_done[18]), .rem0(rem0[18]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h26\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test19(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d38), .done(remainder_done[19]), .rem0(rem0[19]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:478: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test20(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d40), .done(remainder_done[20]), .rem0(rem0[20]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:479: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2a\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test21(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d42), .done(remainder_done[21]), .rem0(rem0[21]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:480: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2c\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test22(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d44), .done(remainder_done[22]), .rem0(rem0[22]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:481: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'6\'h2e\' generates 6 bits.\n                                                                            : ... In instance lab7.prime7\n remainder_test test23(.clk(clk), .rst((rst | clear)), .numerator(dividend), .denominator(count[31:0] + 6\'d46), .done(remainder_done[23]), .rem0(rem0[23]));\n                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:507: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n                                                                            : ... In instance lab7.prime7\n    state_c = INITIAL;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:513: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n                                                                            : ... In instance lab7.prime7\n     state_c = PROCESS;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:516: Operator EQ expects 33 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                            : ... In instance lab7.prime7\n     if (count_c[0] == 33\'b0) begin\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:533: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n                                                                            : ... In instance lab7.prime7\n     state_c = INITIAL;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:540: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n                                                                            : ... In instance lab7.prime7\n     state_c = INITIAL;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:550: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n                                                                            : ... In instance lab7.prime7\n      state_c = INITIAL;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:556: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROCESS\' generates 2 bits.\n                                                                            : ... In instance lab7.prime7\n     state_c = PROCESS;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:560: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n                                                                            : ... In instance lab7.prime7\n      state_c = INITIAL;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'INITIAL\' generates 2 bits.\n                                                                            : ... In instance lab7.prime7\n  case (state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROCESS\' generates 2 bits.\n                                                                            : ... In instance lab7.prime7\n  case (state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:504: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'DONE\' generates 2 bits.\n                                                                            : ... In instance lab7.prime7\n  case (state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:573: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INITIAL\' generates 2 bits.\n                                                                            : ... In instance lab7.prime7\n   state_c = INITIAL;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 32 bits.\n                                                                           : ... In instance lab7\nwire dividend = count;\n              ^\n%Error: data/full_repos/permissive/105729015/Next_prime_finder.v:73: Cannot find file containing module: \'pll\'\npll pll_inst (\n^~~\n        ... Looked in:\n             data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll\n             data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.v\n             data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:96: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n                                                                           : ... In instance lab7\nprime_tester prime0(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[0]), .is_prime(is_prime[0]), .count(c), .start_val(32\'d2), .end_val((count >> 4)));  \n                                                                                                                        ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:97: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n                                                                           : ... In instance lab7\nprime_tester prime1(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[1]), .is_prime(is_prime[1]), .count(c), .start_val((count >> 4)), .end_val((count >> 4) * 2\'d2));\n                                                                                                                        ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:98: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n                                                                           : ... In instance lab7\nprime_tester prime2(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[2]), .is_prime(is_prime[2]), .count(c), .start_val((count >> 4) * 2\'d2), .end_val((count >> 4) * 2\'d3));\n                                                                                                                        ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:99: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n                                                                           : ... In instance lab7\nprime_tester prime3(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[3]), .is_prime(is_prime[3]), .count(c), .start_val((count >> 4) * 2\'d3), .end_val((count >> 4) * 3\'d4));\n                                                                                                                        ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:100: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n                                                                            : ... In instance lab7\nprime_tester prime4(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[4]), .is_prime(is_prime[4]), .count(c), .start_val((count >> 4) * 3\'d4), .end_val((count >> 4) * 3\'d5));\n                                                                                                                        ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:101: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n                                                                            : ... In instance lab7\nprime_tester prime5(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[5]), .is_prime(is_prime[5]), .count(c), .start_val((count >> 4) * 3\'d5), .end_val((count >> 4) * 3\'d6));\n                                                                                                                        ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:102: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n                                                                            : ... In instance lab7\nprime_tester prime6(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[6]), .is_prime(is_prime[6]), .count(c), .start_val((count >> 4) * 3\'d6), .end_val((count >> 4) * 3\'d7));\n                                                                                                                        ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Next_prime_finder.v:103: Output port connection \'count\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'c\' generates 1 bits.\n                                                                            : ... In instance lab7\nprime_tester prime7(.clk(clk), .rst(rst), .dividend(count), .start(startTest), .done(done[7]), .is_prime(is_prime[7]), .count(c), .start_val((count >> 4) * 3\'d7), .end_val((count >> 1) + 1\'b1));  \n                                                                                                                        ^~~~~\n%Error: Exiting due to 1 error(s), 53 warning(s)\n'
module output_ram(clk, write_data, write_enable, write_addr, read_addr, read_data);
	input [7:0] write_data;
	input write_enable, clk;
	input [1:0] write_addr;
	input [1:0] read_addr;
	output [7:0] read_data;
	
	reg [7:0] Mem [0:3];


	always @(posedge clk) begin
		if (write_enable == 1'b1) begin
			Mem[write_addr] <= #1 write_data;
		end
	end
	
	assign read_data = Mem[read_addr];
	
endmodule
module output_ram(clk, write_data, write_enable, write_addr, read_addr, read_data);

	input [7:0] write_data;
	input write_enable, clk;
	input [1:0] write_addr;
	input [1:0] read_addr;
	output [7:0] read_data;
	
	reg [7:0] Mem [0:3];


	always @(posedge clk) begin
		if (write_enable == 1'b1) begin
			Mem[write_addr] <= #1 write_data;
		end
	end
	
	assign read_data = Mem[read_addr];
	
endmodule