data/full_repos/permissive/156966470/ver/clkdiv/test.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/156966470/ver/clkdiv/test.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #50 rst_n = 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/156966470/ver/clkdiv/test.v:18: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test.lxt");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/156966470/ver/clkdiv/test.v:19: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/156966470/ver/clkdiv/test.v:20: Unsupported or unknown PLI call: $dumpon\n    $dumpon;\n    ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/156966470/ver/clkdiv/test.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #(10*15*4*16) $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156966470/ver/clkdiv/test.v:28: Unsupported: Ignoring delay on this delayed statement.\n    forever #(10*15*4) period = period+4\'h1;\n            ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

reg clk, cen=1'b1, rst_n;

initial begin
    clk = 0;
    forever clk = #5 ~clk;
end

initial begin
    rst_n = 1'b0;
    #50 rst_n = 1'b1;
end

initial begin
    $dumpfile("test.lxt");
    $dumpvars;
    $dumpon;
    #(10*15*4*16) $finish;
end

reg [3:0] period;

initial begin
    period = 4'h0;
    forever #(10*15*4) period = period+4'h1;
end




wire cen_div;

jt49_div #(.width(4) ) uut (   
    .clk    ( clk       ),
    .cen    ( cen       ),
    .rst_n  ( rst_n     ),
    .period ( period    ),
    .cen_div( cen_div   )
);

endmodule
module test;


reg clk, cen=1'b1, rst_n;

initial begin
    clk = 0;
    forever clk = #5 ~clk;
end

initial begin
    rst_n = 1'b0;
    #50 rst_n = 1'b1;
end

initial begin
    $dumpfile("test.lxt");
    $dumpvars;
    $dumpon;
    #(10*15*4*16) $finish;
end

reg [3:0] period;

initial begin
    period = 4'h0;
    forever #(10*15*4) period = period+4'h1;
end




wire cen_div;

jt49_div #(.width(4) ) uut (   
    .clk    ( clk       ),
    .cen    ( cen       ),
    .rst_n  ( rst_n     ),
    .period ( period    ),
    .cen_div( cen_div   )
);

endmodule