data/full_repos/permissive/193790231/lab06/lab06part08.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193790231/lab06/lab06part08.v:58: Unsupported: Ignoring delay on this delayed statement.\n        reset = 1\'b0; #100; reset = 1\'b1;\n                      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab06/lab06part08.v:63: Unsupported: Ignoring delay on this delayed statement.\n        forever #25 clk = ~clk;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab06/lab06part08.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #150;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab06/lab06part08.v:79: Unsupported: Ignoring delay on this delayed statement.\n                        #50;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab06/lab06part08.v:84: Unsupported: Ignoring delay on this delayed statement.\n                        #50;\n                        ^\n%Error: data/full_repos/permissive/193790231/lab06/lab06part08.v:33: Cannot find file containing module: \'registerNx\'\n            registerNx #(8) savein(.Q(inData[i]), .D(SW[7:0]), .regCLK(clkEn[i]), .regRESN(KEY[2]));\n            ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193790231/lab06,data/full_repos/permissive/193790231/registerNx\n             data/full_repos/permissive/193790231/lab06,data/full_repos/permissive/193790231/registerNx.v\n             data/full_repos/permissive/193790231/lab06,data/full_repos/permissive/193790231/registerNx.sv\n             registerNx\n             registerNx.v\n             registerNx.sv\n             obj_dir/registerNx\n             obj_dir/registerNx.v\n             obj_dir/registerNx.sv\n%Error: data/full_repos/permissive/193790231/lab06/lab06part08.v:37: Cannot find file containing module: \'syncMulAdd2\'\n    syncMulAdd2 #(4) muladdA(.resultS(resultOp), .numA(inData[0][7:4]), .numB(inData[0][3:0]),\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193790231/lab06/lab06part08.v:43: Cannot find file containing module: \'mux2x1\'\n    mux2x1 #(16) dispSelect(.M(dispData), .X({inData[0], inData[1]}), .Y({6\'d0, resultOp}), .Sel(SW[9]));\n    ^~~~~~\n%Error: data/full_repos/permissive/193790231/lab06/lab06part08.v:44: Cannot find file containing module: \'hexDisplay4digit\'\n    hexDisplay4digit disply(HEX3, HEX2, HEX1, HEX0, dispData);\n    ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab06/lab06part08.v:77: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance tbtestl6p8\n                        dataA = i;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab06/lab06part08.v:78: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                           : ... In instance tbtestl6p8\n                        dataB = j;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab06/lab06part08.v:81: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'k\' generates 32 bits.\n                                                                           : ... In instance tbtestl6p8\n                        dataA = k;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab06/lab06part08.v:82: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'l\' generates 32 bits.\n                                                                           : ... In instance tbtestl6p8\n                        dataB = l;\n                              ^\n%Error: Exiting due to 4 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lab06part08(
    output [6:0]HEX3, HEX2, HEX1, HEX0,
    output [8:0]resultOp,
    input  [9:0]SW,
    input  [3:2]KEY
);

    wire[1:0]clkEn;
    assign clkEn[0] = ((~KEY[3])& ~SW[8]);
    assign clkEn[1] = ((~KEY[3])&  SW[8]);



    genvar i;
    wire [7:0]inData[1:0];
    generate
        for(i=0; i<2; i=i+1) begin: m
            registerNx #(8) savein(.Q(inData[i]), .D(SW[7:0]), .regCLK(clkEn[i]), .regRESN(KEY[2]));
        end 
    endgenerate

    syncMulAdd2 #(4) muladdA(.resultS(resultOp), .numA(inData[0][7:4]), .numB(inData[0][3:0]),
        .numC(inData[1][7:4]), .numD(inData[1][3:0]), .clkP(~KEY[3] & SW[9]), .resN(KEY[2]));


    wire [15:0]dispData;

    mux2x1 #(16) dispSelect(.M(dispData), .X({inData[0], inData[1]}), .Y({6'd0, resultOp}), .Sel(SW[9]));
    hexDisplay4digit disply(HEX3, HEX2, HEX1, HEX0, dispData);

endmodule
module lab06part08(
    output [6:0]HEX3, HEX2, HEX1, HEX0,
    output [8:0]resultOp,
    input  [9:0]SW,
    input  [3:2]KEY
);


    wire[1:0]clkEn;
    assign clkEn[0] = ((~KEY[3])& ~SW[8]);
    assign clkEn[1] = ((~KEY[3])&  SW[8]);



    genvar i;
    wire [7:0]inData[1:0];
    generate
        for(i=0; i<2; i=i+1) begin: m
            registerNx #(8) savein(.Q(inData[i]), .D(SW[7:0]), .regCLK(clkEn[i]), .regRESN(KEY[2]));
        end 
    endgenerate

    syncMulAdd2 #(4) muladdA(.resultS(resultOp), .numA(inData[0][7:4]), .numB(inData[0][3:0]),
        .numC(inData[1][7:4]), .numD(inData[1][3:0]), .clkP(~KEY[3] & SW[9]), .resN(KEY[2]));


    wire [15:0]dispData;

    mux2x1 #(16) dispSelect(.M(dispData), .X({inData[0], inData[1]}), .Y({6'd0, resultOp}), .Sel(SW[9]));
    hexDisplay4digit disply(HEX3, HEX2, HEX1, HEX0, dispData);

endmodule