data/full_repos/permissive/140927679/Quartus/USB Amplifier/USB/USB_Stream.v
1: b'%Error: Cannot find file containing module: Amplifier/USB,data/full_repos/permissive/140927679\n        ... Looked in:\n             data/full_repos/permissive/140927679/Quartus/USB/Amplifier/USB,data/full_repos/permissive/140927679\n             data/full_repos/permissive/140927679/Quartus/USB/Amplifier/USB,data/full_repos/permissive/140927679.v\n             data/full_repos/permissive/140927679/Quartus/USB/Amplifier/USB,data/full_repos/permissive/140927679.sv\n             Amplifier/USB,data/full_repos/permissive/140927679\n             Amplifier/USB,data/full_repos/permissive/140927679.v\n             Amplifier/USB,data/full_repos/permissive/140927679.sv\n             obj_dir/Amplifier/USB,data/full_repos/permissive/140927679\n             obj_dir/Amplifier/USB,data/full_repos/permissive/140927679.v\n             obj_dir/Amplifier/USB,data/full_repos/permissive/140927679.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/140927679/Quartus/USB\n%Error: Cannot find file containing module: Amplifier/USB/USB_Stream.v\n%Error: Exiting due to 3 error(s)\n'
module USB_Stream(
 input  Clk,
 input  Reset,

 output Stall,

 input            OUT_EoP,
 output           OUT_WaitRequest,
 input      [ 7:0]OUT_Data,
 input            OUT_Valid,
 output           OUT_Isochronous,

 input            Audio_Clk,
 output reg [15:0]Audio[1:0]
);


assign OUT_WaitRequest = 1'b0;
assign OUT_Isochronous = 1'b1;
assign OUT_Stall       = 1'b0;

            
reg [9:0]FIFO_WriteAddress;
wire     FIFO_Write = OUT_Valid & ~OUT_EoP;

reg  [ 7:0]FIFO_ReadAddress;
wire [31:0]FIFO_Out;

USB_FIFO FIFO(
 .clock    (Clk),

 .wraddress(FIFO_WriteAddress),
 .wren     (FIFO_Write),
 .data     (OUT_Data),

 .rdaddress(FIFO_ReadAddress),
 .q        (FIFO_Out)
);

always @(posedge Clk) begin
      if(tReset    ) FIFO_WriteAddress <= 0;
 else if(FIFO_Write) FIFO_WriteAddress <= FIFO_WriteAddress + 1'b1;


 else if(OUT_Valid & OUT_EoP) FIFO_WriteAddress[1:0] <= 0;
end


reg [1:0]Clk_48k;
reg      FIFO_Ready;
reg [7:0]FIFO_Length;


reg tReset;
always @(posedge Clk) begin 
 tReset  <= Reset;
 Clk_48k <= {Clk_48k[0], Audio_Clk};


 FIFO_Length <= FIFO_WriteAddress[9:2] - FIFO_ReadAddress;


 if(tReset) begin
  FIFO_Ready       <= 0;
  FIFO_ReadAddress <= 0;

  {Audio[1], Audio[0]} <= 0;

   
 end else begin
  if(FIFO_Ready) begin
   if(FIFO_Length == 8'h20) FIFO_Ready <= 1'b0;
  end else begin
   if(FIFO_Length == 8'h80) FIFO_Ready <= 1'b1;
  end


  if(FIFO_Ready) begin
   if(Clk_48k == 2'b10) begin
    {Audio[1], Audio[0]} <= FIFO_Out;
    FIFO_ReadAddress     <= FIFO_ReadAddress + 1'b1;
   end
  end else begin
   {Audio[1], Audio[0]} <= 0;
  end
 end
end


endmodule
module USB_Stream(
 input  Clk,
 input  Reset,

 output Stall,

 input            OUT_EoP,
 output           OUT_WaitRequest,
 input      [ 7:0]OUT_Data,
 input            OUT_Valid,
 output           OUT_Isochronous,

 input            Audio_Clk,
 output reg [15:0]Audio[1:0]
);



assign OUT_WaitRequest = 1'b0;
assign OUT_Isochronous = 1'b1;
assign OUT_Stall       = 1'b0;

            
reg [9:0]FIFO_WriteAddress;
wire     FIFO_Write = OUT_Valid & ~OUT_EoP;

reg  [ 7:0]FIFO_ReadAddress;
wire [31:0]FIFO_Out;

USB_FIFO FIFO(
 .clock    (Clk),

 .wraddress(FIFO_WriteAddress),
 .wren     (FIFO_Write),
 .data     (OUT_Data),

 .rdaddress(FIFO_ReadAddress),
 .q        (FIFO_Out)
);

always @(posedge Clk) begin
      if(tReset    ) FIFO_WriteAddress <= 0;
 else if(FIFO_Write) FIFO_WriteAddress <= FIFO_WriteAddress + 1'b1;


 else if(OUT_Valid & OUT_EoP) FIFO_WriteAddress[1:0] <= 0;
end


reg [1:0]Clk_48k;
reg      FIFO_Ready;
reg [7:0]FIFO_Length;


reg tReset;
always @(posedge Clk) begin 
 tReset  <= Reset;
 Clk_48k <= {Clk_48k[0], Audio_Clk};


 FIFO_Length <= FIFO_WriteAddress[9:2] - FIFO_ReadAddress;


 if(tReset) begin
  FIFO_Ready       <= 0;
  FIFO_ReadAddress <= 0;

  {Audio[1], Audio[0]} <= 0;

   
 end else begin
  if(FIFO_Ready) begin
   if(FIFO_Length == 8'h20) FIFO_Ready <= 1'b0;
  end else begin
   if(FIFO_Length == 8'h80) FIFO_Ready <= 1'b1;
  end


  if(FIFO_Ready) begin
   if(Clk_48k == 2'b10) begin
    {Audio[1], Audio[0]} <= FIFO_Out;
    FIFO_ReadAddress     <= FIFO_ReadAddress + 1'b1;
   end
  end else begin
   {Audio[1], Audio[0]} <= 0;
  end
 end
end


endmodule