data/full_repos/permissive/117026779/src/ExtToIntSync.v
data/verilator_xmls/12caf889-1637-467a-aa93-d7393fc014e8.xml
module ExtToIntSync(
	input wire clk,
	input wire rst,
	input wire ext_signal,
	output reg int_signal
);

always @(posedge clk or posedge rst) begin
	if (rst) begin
		int_signal = 0;
	end
	else begin
		int_signal = ext_signal;
	end
end

endmodule
module ExtToIntSync(
	input wire clk,
	input wire rst,
	input wire ext_signal,
	output reg int_signal
);


always @(posedge clk or posedge rst) begin
	if (rst) begin
		int_signal = 0;
	end
	else begin
		int_signal = ext_signal;
	end
end

endmodule