data/full_repos/permissive/187712539/modules/dataMemory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/187712539/modules/dataMemory.v:19: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 9 bits.\n                                                                            : ... In instance dataMemory\n DataMemory[Address+1] = WriteData[23:15];\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/187712539/modules/dataMemory.v:20: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 9 bits.\n                                                                            : ... In instance dataMemory\n DataMemory[Address+2] = WriteData[15:7];\n                       ^\n%Error: Exiting due to 2 warning(s)\n'
module dataMemory(Address, WriteData, MemWrite, MemRead, ReadData);
input [31:0] Address, WriteData;
input MemWrite, MemRead;
output reg [31:0] ReadData;

reg [7:0] DataMemory [0:255];

integer i;

initial
begin
	for(i=0; i<256; i=i+1)
		DataMemory[i]=0;
end

always @(posedge MemWrite)
begin
	DataMemory[Address]   = WriteData[31:24];
	DataMemory[Address+1] = WriteData[23:15];
	DataMemory[Address+2] = WriteData[15:7];
	DataMemory[Address+3] = WriteData[7:0];
end

always @(posedge MemRead)
begin
	ReadData = {DataMemory[Address],DataMemory[Address+1],DataMemory[Address+2],DataMemory[Address+3]};
end

endmodule
module dataMemory(Address, WriteData, MemWrite, MemRead, ReadData);

input [31:0] Address, WriteData;
input MemWrite, MemRead;
output reg [31:0] ReadData;

reg [7:0] DataMemory [0:255];

integer i;

initial
begin
	for(i=0; i<256; i=i+1)
		DataMemory[i]=0;
end

always @(posedge MemWrite)
begin
	DataMemory[Address]   = WriteData[31:24];
	DataMemory[Address+1] = WriteData[23:15];
	DataMemory[Address+2] = WriteData[15:7];
	DataMemory[Address+3] = WriteData[7:0];
end

always @(posedge MemRead)
begin
	ReadData = {DataMemory[Address],DataMemory[Address+1],DataMemory[Address+2],DataMemory[Address+3]};
end

endmodule