data/full_repos/permissive/159312910/thales-risc-v-vivado/git/src/hdl/clk_control.v
1: b"%Error: data/full_repos/permissive/159312910/thales-risc-v-vivado/git/src/hdl/clk_control.v:16: Cannot find file containing module: 'BUFGCE'\n  BUFGCE #(\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159312910/thales-risc-v-vivado/git/src/hdl,data/full_repos/permissive/159312910/BUFGCE\n             data/full_repos/permissive/159312910/thales-risc-v-vivado/git/src/hdl,data/full_repos/permissive/159312910/BUFGCE.v\n             data/full_repos/permissive/159312910/thales-risc-v-vivado/git/src/hdl,data/full_repos/permissive/159312910/BUFGCE.sv\n             BUFGCE\n             BUFGCE.v\n             BUFGCE.sv\n             obj_dir/BUFGCE\n             obj_dir/BUFGCE.v\n             obj_dir/BUFGCE.sv\n%Error: Exiting due to 1 error(s)\n"
module clk_control
  (clk_in,
   clk_out,
   enable);

  input clk_in;
  output clk_out;
  input enable;

  wire clk_in;
  wire clk_out;
  wire enable;

  BUFGCE #(
    .CE_TYPE("SYNC"),
    .IS_CE_INVERTED(1'b0),
    .IS_I_INVERTED(1'b0)
  )
  BUFGCE_inst (
    .O(clk_out),
    .CE(enable),
    .I(clk_in)
  );

endmodule
module clk_control
  (clk_in,
   clk_out,
   enable);


  input clk_in;
  output clk_out;
  input enable;

  wire clk_in;
  wire clk_out;
  wire enable;

  BUFGCE #(
    .CE_TYPE("SYNC"),
    .IS_CE_INVERTED(1'b0),
    .IS_I_INVERTED(1'b0)
  )
  BUFGCE_inst (
    .O(clk_out),
    .CE(enable),
    .I(clk_in)
  );

endmodule