data/full_repos/permissive/101171422/de2-115/vgadla/reset_delay.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/d8f2453e-f200-4a6c-a23d-724c1105e6b5.xml
module reset_delay
(
	input wire clk,
	output reg rst
);
	reg [19:0] cnt;
	
	always @ (posedge clk) begin
		if (cnt != 'hffff) begin
			cnt <= cnt + 1;
			rst <= 0;
		end
		else
			rst <= 1;
	end
endmodule
module reset_delay
(
	input wire clk,
	output reg rst
);

	reg [19:0] cnt;
	
	always @ (posedge clk) begin
		if (cnt != 'hffff) begin
			cnt <= cnt + 1;
			rst <= 0;
		end
		else
			rst <= 1;
	end
endmodule