data/full_repos/permissive/118800618/MUX4T1_5.v
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data/verilator_xmls/ed99142d-fa4b-4797-8430-8b28c2997426.xml
module   MUX4T1_5(input [1:0]s,
						input [4:0]I0,
						input [4:0]I1,
						input [4:0]I2,
						input [4:0]I3,						
						output reg[4:0]o
						 );

		always@*
			case(s)
				2'b00: o<=I0;
				2'b01: o<=I1;
				2'b10: o<=I2;
				2'b11: o<=I3;
			endcase
			
endmodule
module   MUX4T1_5(input [1:0]s,
						input [4:0]I0,
						input [4:0]I1,
						input [4:0]I2,
						input [4:0]I3,						
						output reg[4:0]o
						 );


		always@*
			case(s)
				2'b00: o<=I0;
				2'b01: o<=I1;
				2'b10: o<=I2;
				2'b11: o<=I3;
			endcase
			
endmodule