data/full_repos/permissive/115035459/verilog/src/mza-test045.nop.althea.revA.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/1e49b80d-7b0c-4abc-8dc7-f1a23b0e7dd6.xml
module myalthea (
	input clock50_p, clock50_n,
	input lemo,
	input a_p, a_n,
	input b_p, b_n,
	input c_p, c_n,
	input d_p, d_n,
	input e_p, e_n,
	input f_p, f_n,
	input g_p, g_n,
	input h_p, h_n,
	input j_p, j_n,
	input k_p, k_n,
	input l_p, l_n,
	input m_p, m_n,
	input led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
);
	top althea ();
endmodule
module myalthea (
	input clock50_p, clock50_n,
	input lemo,
	input a_p, a_n,
	input b_p, b_n,
	input c_p, c_n,
	input d_p, d_n,
	input e_p, e_n,
	input f_p, f_n,
	input g_p, g_n,
	input h_p, h_n,
	input j_p, j_n,
	input k_p, k_n,
	input l_p, l_n,
	input m_p, m_n,
	input led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
);

	top althea ();
endmodule