data/full_repos/permissive/206842334/testbenches/main_tb.v
 line:32: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/main_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD/2) clk=~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/main_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    always #(period2/2) sclk=~sclk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/main_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD/2) clock = ~clock;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/main_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD/2) clock = ~clock; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/main_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #(period2/2) clock = ~clock;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/main_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #(period2/2) clock = ~clock; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/main_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk <= 0; clock <= 0; reset <= 0; sclk <= 0; nss <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/main_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #50 mosi = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/main_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #50 nss = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/main_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #50 mosi = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/main_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #50 nss = 1;\n  ^\n%Warning-LITENDIAN: data/full_repos/permissive/206842334/testbenches/main_tb.v:84: Little bit endian vector: MSB < LSB of bit range: 0:6\n wire [0:6] hex0, hex4, hex5, hex6, hex7;\n      ^\n%Error: data/full_repos/permissive/206842334/testbenches/main_tb.v:88: Cannot find file containing module: \'archlearn\'\n    archlearn main(clk, mosi, miso, nss, sclk, reset, hex0, hex4, hex5, hex6, hex7, ledr, ledg, convout);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/archlearn\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/archlearn.v\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/archlearn.sv\n             archlearn\n             archlearn.v\n             archlearn.sv\n             obj_dir/archlearn\n             obj_dir/archlearn.v\n             obj_dir/archlearn.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_tb;

    reg clk, reset, clock, sclk, mosi, nss;
    wire miso;

    localparam CLK_PERIOD = 20;
    localparam period2 = 100;
    always #(CLK_PERIOD/2) clk=~clk;
    always #(period2/2) sclk=~sclk;

    task run_clock;
    begin
        #(CLK_PERIOD/2) clock = ~clock;
        #(CLK_PERIOD/2) clock = ~clock; 
    end
    endtask
	 
	task run_clock2;
    begin
        #(period2/2) clock = ~clock;
        #(period2/2) clock = ~clock; 
    end
    endtask
	
    initial begin
		#1 clk <= 0; clock <= 0; reset <= 0; sclk <= 0; nss <= 1;
		run_clock2;
		reset <= 1;
		run_clock2;
		run_clock2;
		reset <= 0;
		run_clock2;
		run_clock2;
		nss = 0;
		#50 mosi = 0;
		run_clock2;
		mosi = 0;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 0;
		run_clock2;
		mosi = 0;
		run_clock2;
		mosi = 0;
		run_clock2;
		mosi = 0;
		#50 nss = 1;
		run_clock2;
		
		nss = 0;
		#50 mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		#50 nss = 1;
    end

	wire convout;
	always @(posedge clk ) begin
		if(convout == 1'b1) begin
			$stop;
		end
	end

	wire [0:6] hex0, hex4, hex5, hex6, hex7;
	wire [17:0] ledr;
	wire [6:0] ledg;

    archlearn main(clk, mosi, miso, nss, sclk, reset, hex0, hex4, hex5, hex6, hex7, ledr, ledg, convout);
    

endmodule
module main_tb;


    reg clk, reset, clock, sclk, mosi, nss;
    wire miso;

    localparam CLK_PERIOD = 20;
    localparam period2 = 100;
    always #(CLK_PERIOD/2) clk=~clk;
    always #(period2/2) sclk=~sclk;

    task run_clock;
    begin
        #(CLK_PERIOD/2) clock = ~clock;
        #(CLK_PERIOD/2) clock = ~clock; 
    end
    endtask
	 
	task run_clock2;
    begin
        #(period2/2) clock = ~clock;
        #(period2/2) clock = ~clock; 
    end
    endtask
	
    initial begin
		#1 clk <= 0; clock <= 0; reset <= 0; sclk <= 0; nss <= 1;
		run_clock2;
		reset <= 1;
		run_clock2;
		run_clock2;
		reset <= 0;
		run_clock2;
		run_clock2;
		nss = 0;
		#50 mosi = 0;
		run_clock2;
		mosi = 0;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 0;
		run_clock2;
		mosi = 0;
		run_clock2;
		mosi = 0;
		run_clock2;
		mosi = 0;
		#50 nss = 1;
		run_clock2;
		
		nss = 0;
		#50 mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		run_clock2;
		mosi = 1;
		#50 nss = 1;
    end

	wire convout;
	always @(posedge clk ) begin
		if(convout == 1'b1) begin
			$stop;
		end
	end

	wire [0:6] hex0, hex4, hex5, hex6, hex7;
	wire [17:0] ledr;
	wire [6:0] ledg;

    archlearn main(clk, mosi, miso, nss, sclk, reset, hex0, hex4, hex5, hex6, hex7, ledr, ledg, convout);
    

endmodule