data/full_repos/permissive/173670949/dds-synth/ram.v
data/verilator_xmls/c59af939-4634-422d-99ba-cc4ef5a3feb9.xml
module ram #(
    parameter ADDR_WIDTH = 9,
    parameter DATA_WIDTH = 8
) (
    input                       clk,
    input      [ADDR_WIDTH-1:0] wr_addr,
    input      [DATA_WIDTH-1:0] din,
    input                       wr_en,
    input      [ADDR_WIDTH-1:0] rd_addr,
    output reg [DATA_WIDTH-1:0] dout
);



    reg [DATA_WIDTH-1:0] bram_memory[(1<<ADDR_WIDTH)-1:0];

    always @(posedge clk) begin
        if (wr_en)
            bram_memory[wr_addr] <= din;
        dout <= bram_memory[rd_addr];
    end

endmodule
module ram #(
    parameter ADDR_WIDTH = 9,
    parameter DATA_WIDTH = 8
) (
    input                       clk,
    input      [ADDR_WIDTH-1:0] wr_addr,
    input      [DATA_WIDTH-1:0] din,
    input                       wr_en,
    input      [ADDR_WIDTH-1:0] rd_addr,
    output reg [DATA_WIDTH-1:0] dout
);




    reg [DATA_WIDTH-1:0] bram_memory[(1<<ADDR_WIDTH)-1:0];

    always @(posedge clk) begin
        if (wr_en)
            bram_memory[wr_addr] <= din;
        dout <= bram_memory[rd_addr];
    end

endmodule