data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:69: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:69: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:181: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_1, net_2, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:182: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:183: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(gnd, y, net_2);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:184: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_2, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:185: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_2, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:186: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, vdd, net_2);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:198: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_3, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:199: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_4, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:200: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_3, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:201: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(net_4, y, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:202: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(gnd, bb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:203: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, ab, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:204: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, net_7, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:205: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_7, vdd, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:206: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, net_8, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:207: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_8, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:208: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(bb, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:209: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(ab, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:236: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:237: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:238: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_1, coutb, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:239: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(gnd, net_11, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:240: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, coutb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:241: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, net_23, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:242: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_23, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:243: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_7(gnd, net_23, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:244: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_8(net_23, sb, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:245: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_9(gnd, net_33, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:246: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_10(net_33, net_32, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:247: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_11(net_32, sb, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:248: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_12(gnd, cout, coutb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:249: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_13(gnd, s, sb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:250: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(sb, net_92, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:251: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(net_92, net_90, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:252: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_90, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:253: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(sb, net_94, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:254: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(net_94, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:255: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_6(net_94, vdd, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:256: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_7(net_94, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:257: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_8(cout, vdd, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:258: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_9(net_95, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:259: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_10(coutb, net_95, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:260: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_11(net_111, vdd, a);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:261: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_12(net_111, vdd, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:262: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_13(coutb, net_111, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.sv:263: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_14(s, vdd, sb);\n          ^~~~~~~\n%Error: Exiting due to 46 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbenchCPA();
  
  logic a0;
  logic a1;
  logic a10;
  logic a11;
  logic a12;
  logic a2;
  logic a3;
  logic a4;
  logic a5;
  logic a6;
  logic a7;
  logic a8;
  logic a9;
  logic b0;
  logic b1;
  logic b10;
  logic b11;
  logic b12;
  logic b2;
  logic b3;
  logic b4;
  logic b5;
  logic b6;
  logic b7;
  logic b8;
  logic b9;
  logic cout;
  logic overflow;
  logic s0;
  logic s1;
  logic s10;
  logic s11;
  logic s12;
  logic s2;
  logic s3;
  logic s4;
  logic s5;
  logic s6;
  logic s7;
  logic s8;
  logic s9;
  
    logic clk;
    logic [9:0] vectors[1023:0], currentvec;
    logic [25:0] vectorsOUT[1023:0], currentvecOUT;
    logic [11:0] vectornum, errors;

    
     

    CPA dut(a0, a1, a10, a11, a12, a2, a3, a4, a5, a6, a7, a8, a9, b0, b1, b10, 
      b11, b12, b2, b3, b4, b5, b6, b7, b8, b9, cout, overflow, s0, s1, s10, 
      s11, s12, s2, s3, s4, s5, s6, s7, s8, s9);
    
    

    initial begin
       $readmemb("lakis.txt", vectors);
       $readmemb("CPAcheckOUT.txt", vectorsOUT);

       vectornum = 0; errors = 0;
    end

    always begin
       clk = 1; #10; clk = 0; #10;
    end
      

    always @(posedge clk) begin
       
       currentvec = vectors[vectornum];
       currentvecOUT = vectorsOUT[vectornum];
       $display("%h%h%h%h%h%h%h%h%h%h", 
       currentvec[9], 
       currentvec[8] ,
       currentvec[7] ,
       currentvec[6] ,
       currentvec[5] ,
       currentvec[4] ,
       currentvec[3] ,
       currentvec[2] ,
       currentvec[1] ,
       currentvec[0] );
       
       $display("%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h",
       currentvecOUT[14] ,
       currentvecOUT[13], 
       currentvecOUT[12] ,
       currentvecOUT[11] ,
       currentvecOUT[10] ,
       currentvecOUT[9], 
       currentvecOUT[8] ,
       currentvecOUT[7] ,
       currentvecOUT[6] ,
       currentvecOUT[5], 
       currentvecOUT[4] ,
       currentvecOUT[3] ,
       currentvecOUT[2] ,
       currentvecOUT[1], 
       currentvecOUT[0] );
       
       
       
       a0 = currentvec[9];
       a1 = 0;
       a10 = currentvec[8];
       a11 = 1;
       a12 = currentvec[7];
       a2 = currentvec[6];
       a3 = 1;
       a4 = 1;
       a5 = 0;
       a6 = 1;
       a7 = currentvec[5];
       a8 = 1;
       a9 = 1;
       b0 = currentvec[4];
       b1 = currentvec[3];
       b10 = 1;
       b11 = 1;
       b12 = 1;
       b2 = currentvec[1];
       b3 = 0;
       b4 = currentvec[0];
       b5 = 0;
       b6 = 0;
       b7 = 0;
       b8 = currentvec[2];
       b9 = 1;
       
       
       if (vectornum === 1023) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);

         $stop;
       end
    end
    

    always @(negedge clk) begin
        if ( (cout !== currentvecOUT[14]) ||
        (overflow !== currentvecOUT[13]) || 
        (s0 !== currentvecOUT[12]) ||
        (s1 !== currentvecOUT[11]) || 
        (s10 !== currentvecOUT[10]) ||
        (s11 !== currentvecOUT[9]) || 
        (s12 !== currentvecOUT[8]) ||
        (s2 !== currentvecOUT[7]) || 
        (s3 !== currentvecOUT[6]) ||
        (s4 !== currentvecOUT[5]) || 
        (s5 !== currentvecOUT[4]) ||
        (s6 !== currentvecOUT[3]) || 
        (s7 !== currentvecOUT[2]) ||
        (s8 !== currentvecOUT[1]) || 
        (s9 !== currentvecOUT[0])         
        ) begin
          $display("Error: line %d", vectornum );
          errors = errors + 1;
       end
    
       vectornum = vectornum + 1;
    end
endmodule
module testbenchCPA();

  
  logic a0;
  logic a1;
  logic a10;
  logic a11;
  logic a12;
  logic a2;
  logic a3;
  logic a4;
  logic a5;
  logic a6;
  logic a7;
  logic a8;
  logic a9;
  logic b0;
  logic b1;
  logic b10;
  logic b11;
  logic b12;
  logic b2;
  logic b3;
  logic b4;
  logic b5;
  logic b6;
  logic b7;
  logic b8;
  logic b9;
  logic cout;
  logic overflow;
  logic s0;
  logic s1;
  logic s10;
  logic s11;
  logic s12;
  logic s2;
  logic s3;
  logic s4;
  logic s5;
  logic s6;
  logic s7;
  logic s8;
  logic s9;
  
    logic clk;
    logic [9:0] vectors[1023:0], currentvec;
    logic [25:0] vectorsOUT[1023:0], currentvecOUT;
    logic [11:0] vectornum, errors;

    
     

    CPA dut(a0, a1, a10, a11, a12, a2, a3, a4, a5, a6, a7, a8, a9, b0, b1, b10, 
      b11, b12, b2, b3, b4, b5, b6, b7, b8, b9, cout, overflow, s0, s1, s10, 
      s11, s12, s2, s3, s4, s5, s6, s7, s8, s9);
    
    

    initial begin
       $readmemb("lakis.txt", vectors);
       $readmemb("CPAcheckOUT.txt", vectorsOUT);

       vectornum = 0; errors = 0;
    end

    always begin
       clk = 1; #10; clk = 0; #10;
    end
      

    always @(posedge clk) begin
       
       currentvec = vectors[vectornum];
       currentvecOUT = vectorsOUT[vectornum];
       $display("%h%h%h%h%h%h%h%h%h%h", 
       currentvec[9], 
       currentvec[8] ,
       currentvec[7] ,
       currentvec[6] ,
       currentvec[5] ,
       currentvec[4] ,
       currentvec[3] ,
       currentvec[2] ,
       currentvec[1] ,
       currentvec[0] );
       
       $display("%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h",
       currentvecOUT[14] ,
       currentvecOUT[13], 
       currentvecOUT[12] ,
       currentvecOUT[11] ,
       currentvecOUT[10] ,
       currentvecOUT[9], 
       currentvecOUT[8] ,
       currentvecOUT[7] ,
       currentvecOUT[6] ,
       currentvecOUT[5], 
       currentvecOUT[4] ,
       currentvecOUT[3] ,
       currentvecOUT[2] ,
       currentvecOUT[1], 
       currentvecOUT[0] );
       
       
       
       a0 = currentvec[9];
       a1 = 0;
       a10 = currentvec[8];
       a11 = 1;
       a12 = currentvec[7];
       a2 = currentvec[6];
       a3 = 1;
       a4 = 1;
       a5 = 0;
       a6 = 1;
       a7 = currentvec[5];
       a8 = 1;
       a9 = 1;
       b0 = currentvec[4];
       b1 = currentvec[3];
       b10 = 1;
       b11 = 1;
       b12 = 1;
       b2 = currentvec[1];
       b3 = 0;
       b4 = currentvec[0];
       b5 = 0;
       b6 = 0;
       b7 = 0;
       b8 = currentvec[2];
       b9 = 1;
       
       
       if (vectornum === 1023) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);

         $stop;
       end
    end
    

    always @(negedge clk) begin
        if ( (cout !== currentvecOUT[14]) ||
        (overflow !== currentvecOUT[13]) || 
        (s0 !== currentvecOUT[12]) ||
        (s1 !== currentvecOUT[11]) || 
        (s10 !== currentvecOUT[10]) ||
        (s11 !== currentvecOUT[9]) || 
        (s12 !== currentvecOUT[8]) ||
        (s2 !== currentvecOUT[7]) || 
        (s3 !== currentvecOUT[6]) ||
        (s4 !== currentvecOUT[5]) || 
        (s5 !== currentvecOUT[4]) ||
        (s6 !== currentvecOUT[3]) || 
        (s7 !== currentvecOUT[2]) ||
        (s8 !== currentvecOUT[1]) || 
        (s9 !== currentvecOUT[0])         
        ) begin
          $display("Error: line %d", vectornum );
          errors = errors + 1;
       end
    
       vectornum = vectornum + 1;
    end
endmodule