data/full_repos/permissive/100796583/cpu/MBScore_IR.v
1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n             MBScore_const.v\n             MBScore_const.v.v\n             MBScore_const.v.sv\n             obj_dir/MBScore_const.v\n             obj_dir/MBScore_const.v.v\n             obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:12: Define or directive not defined: \'`ADDR_WIDTH\'\n input  [`ADDR_WIDTH-1:0] next_addr,int_addr,init_addr,\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:13: Define or directive not defined: \'`DATA_WIDTH\'\n input    [`DATA_WIDTH-1:0] inst_in,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:14: Define or directive not defined: \'`DATA_WIDTH\'\n output   [`DATA_WIDTH-1:0] inst_out,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:15: Define or directive not defined: \'`DATA_WIDTH\'\n output   [`DATA_WIDTH-1:0] pc_out\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:18: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0]   pc = 32\'d0;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:19: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0]           inst;\n      ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module MBScore_IR(
	input							clk,
	input 							rst_n,
	input							IR_ack,
	input 							next,
	input							JAL_or_J,
	input							BEQ_or_BNE,
	input							JR,
	input							hlt,
	input							jump,int_jump,
	input		[`ADDR_WIDTH-1:0]	next_addr,int_addr,init_addr,
	input  		[`DATA_WIDTH-1:0]	inst_in,
	output  	[`DATA_WIDTH-1:0]	inst_out,
	output 		[`DATA_WIDTH-1:0]	pc_out
);

	reg [`DATA_WIDTH-1:0]			pc = 32'd0;
	reg [`DATA_WIDTH-1:0]           inst;

	assign pc_out = pc;
	assign inst_out = inst;


	always @(negedge clk)
	if(IR_ack)
	inst = inst_in;

	always @(negedge clk or negedge rst_n)
	if(next || int_jump)
	begin
		if(hlt == 1'b1)
		pc = pc;
		else
		if(JAL_or_J)
		pc = (inst[25:0] << 2);
		else
		if(BEQ_or_BNE && jump)
		pc = pc + 4 + ($signed(inst[15:0]) << 2);
		else
		if(JR)
		pc = next_addr;
		else
		if(int_jump)
		pc = int_addr;
		else
		pc = pc + 4;
	end
	else
	if(!rst_n)
		pc = init_addr;

endmodule
module MBScore_IR(
	input							clk,
	input 							rst_n,
	input							IR_ack,
	input 							next,
	input							JAL_or_J,
	input							BEQ_or_BNE,
	input							JR,
	input							hlt,
	input							jump,int_jump,
	input		[`ADDR_WIDTH-1:0]	next_addr,int_addr,init_addr,
	input  		[`DATA_WIDTH-1:0]	inst_in,
	output  	[`DATA_WIDTH-1:0]	inst_out,
	output 		[`DATA_WIDTH-1:0]	pc_out
);


	reg [`DATA_WIDTH-1:0]			pc = 32'd0;
	reg [`DATA_WIDTH-1:0]           inst;

	assign pc_out = pc;
	assign inst_out = inst;


	always @(negedge clk)
	if(IR_ack)
	inst = inst_in;

	always @(negedge clk or negedge rst_n)
	if(next || int_jump)
	begin
		if(hlt == 1'b1)
		pc = pc;
		else
		if(JAL_or_J)
		pc = (inst[25:0] << 2);
		else
		if(BEQ_or_BNE && jump)
		pc = pc + 4 + ($signed(inst[15:0]) << 2);
		else
		if(JR)
		pc = next_addr;
		else
		if(int_jump)
		pc = int_addr;
		else
		pc = pc + 4;
	end
	else
	if(!rst_n)
		pc = init_addr;

endmodule