data/full_repos/permissive/216210370/soc/wdt.v
None: at end of input
1: b'%Error: data/full_repos/permissive/216210370/soc/wdt.v:45: Cannot find include file: wdt_params.v\n   `include     "wdt_params.v" \n                ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/wdt_params.v\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/wdt_params.v.v\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/wdt_params.v.sv\n             wdt_params.v\n             wdt_params.v.v\n             wdt_params.v.sv\n             obj_dir/wdt_params.v\n             obj_dir/wdt_params.v.v\n             obj_dir/wdt_params.v.sv\n%Error: data/full_repos/permissive/216210370/soc/wdt.v:118: Cannot find include file: wdt_params.v\n    `include     "wdt_params.v" \n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/wdt.v:167: Cannot find include file: wdt_params.v\n   `include     "wdt_params.v" \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/wdt.v:244: Cannot find include file: wdt_params.v\n    `include        "wdt_params.v" \n                    ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module wdt_biu #
(
    parameter      WDT_ADDR_LHS = 5'd10
)
(
    input  wire                            pclk        ,
    input  wire                            presetn     ,
    input  wire                            psel        ,
    input  wire         [WDT_ADDR_LHS:0]   paddr       ,
    input  wire                            pwrite      ,
    input  wire                            penable     ,
    input  wire                   [31:0]   pwdata      ,
    output reg                    [31:0]   prdata      ,
    input  wire                   [31:0]   iprdata     ,
    output wire   			               wr_en       ,
    output wire   			               rd_en       ,
    output wire        [WDT_ADDR_LHS-2:0]  reg_addr    ,
    output wire                   [31:0]   ipwdata      
 );
assign  wr_en = psel &  penable &  pwrite;
assign  rd_en = psel & !penable & !pwrite;
assign reg_addr = paddr[WDT_ADDR_LHS:2];
assign  ipwdata = pwdata;
always @(posedge pclk or negedge presetn)
begin
   if(presetn == 1'b0)
       prdata <= 32'b0;
   else if(rd_en == 1'b1)	    
 	  prdata <= iprdata;
   else ;
end
endmodule
module wdt_biu #
(
    parameter      WDT_ADDR_LHS = 5'd10
)
(
    input  wire                            pclk        ,
    input  wire                            presetn     ,
    input  wire                            psel        ,
    input  wire         [WDT_ADDR_LHS:0]   paddr       ,
    input  wire                            pwrite      ,
    input  wire                            penable     ,
    input  wire                   [31:0]   pwdata      ,
    output reg                    [31:0]   prdata      ,
    input  wire                   [31:0]   iprdata     ,
    output wire   			               wr_en       ,
    output wire   			               rd_en       ,
    output wire        [WDT_ADDR_LHS-2:0]  reg_addr    ,
    output wire                   [31:0]   ipwdata      
 );

assign  wr_en = psel &  penable &  pwrite;
assign  rd_en = psel & !penable & !pwrite;
assign reg_addr = paddr[WDT_ADDR_LHS:2];
assign  ipwdata = pwdata;
always @(posedge pclk or negedge presetn)
begin
   if(presetn == 1'b0)
       prdata <= 32'b0;
   else if(rd_en == 1'b1)	    
 	  prdata <= iprdata;
   else ;
end
endmodule