data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:29: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clock_i <= ~clock_i;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1 reset_i = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #1 reset_i = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:39: syntax error, unexpected \'@\'\n  @ (negedge busy_o);  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #1 clock_divider_i = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #1 send_byte(8\'h55);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #2\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #3 if (serial_o)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #1 write_i = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (serial_o != data[0])\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (serial_o != data[1])\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (serial_o != data[2])\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (serial_o != data[3])\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (serial_o != data[4])\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (serial_o != data[5])\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (serial_o != data[6])\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (serial_o != data[7])\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (!serial_o)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (!serial_o)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_tx/uart_tx_stop_bit_test.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (busy_o)\n    ^\n%Error: Exiting due to 1 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UartTxStopBitTest ();

reg reset_i = 1'b0;
reg clock_i = 1'b0;
reg write_i = 1'b0;
reg two_stop_bits_i = 1'b1;
reg parity_bit_i = 1'b0;
reg parity_even_i = 1'b0;
reg [15:0] clock_divider_i = 0;
reg [7:0] data_i = 8'h00;
wire serial_o;
wire busy_o;

UartTx uart_tx (
  .reset_i(reset_i),
  .clock_i(clock_i),
  .write_i(write_i),
  .two_stop_bits_i(two_stop_bits_i),
  .parity_bit_i(parity_bit_i),
  .parity_even_i(parity_even_i),
  .clock_divider_i(clock_divider_i),
  .data_i(data_i),
  .serial_o(serial_o),
  .busy_o(busy_o)
);

always #1 clock_i <= ~clock_i;

always @ (posedge serial_o, negedge serial_o) begin
  if (!busy_o)
    $display("FAILED - busy_o should be high when serial_o transitions");
end

initial begin
  #1 reset_i = 1'b1;
  #1 reset_i = 1'b0;
  @ (negedge busy_o);

  #1 clock_divider_i = 1;

  #1 send_byte(8'h55);
end

task send_byte;
  input [7:0] data;

  begin
    #2
    data_i = data;
    write_i = 1'b1;

    #3 if (serial_o)
      $display("FAILED - start bit incorrect");

    #1 write_i = 1'b0;

    #1 if (serial_o != data[0])
      $display("FAILED - data bit 0 incorrect");

    #2 if (serial_o != data[1])
      $display("FAILED - data bit 1 incorrect");

    #2 if (serial_o != data[2])
      $display("FAILED - data bit 2 incorrect");

    #2 if (serial_o != data[3])
      $display("FAILED - data bit 3 incorrect");

    #2 if (serial_o != data[4])
      $display("FAILED - data bit 4 incorrect");

    #2 if (serial_o != data[5])
      $display("FAILED - data bit 5 incorrect");

    #2 if (serial_o != data[6])
      $display("FAILED - data bit 6 incorrect");

    #2 if (serial_o != data[7])
      $display("FAILED - data bit 7 incorrect");

    #2 if (!serial_o)
      $display("FAILED - stop bit 1 incorrect");

    #2 if (!serial_o)
      $display("FAILED - stop bit 2 incorrect");

    #2 if (busy_o)
      $display("FAILED - busy_o should be low after sending first packet");
  end
endtask

endmodule
module UartTxStopBitTest ();


reg reset_i = 1'b0;
reg clock_i = 1'b0;
reg write_i = 1'b0;
reg two_stop_bits_i = 1'b1;
reg parity_bit_i = 1'b0;
reg parity_even_i = 1'b0;
reg [15:0] clock_divider_i = 0;
reg [7:0] data_i = 8'h00;
wire serial_o;
wire busy_o;

UartTx uart_tx (
  .reset_i(reset_i),
  .clock_i(clock_i),
  .write_i(write_i),
  .two_stop_bits_i(two_stop_bits_i),
  .parity_bit_i(parity_bit_i),
  .parity_even_i(parity_even_i),
  .clock_divider_i(clock_divider_i),
  .data_i(data_i),
  .serial_o(serial_o),
  .busy_o(busy_o)
);

always #1 clock_i <= ~clock_i;

always @ (posedge serial_o, negedge serial_o) begin
  if (!busy_o)
    $display("FAILED - busy_o should be high when serial_o transitions");
end

initial begin
  #1 reset_i = 1'b1;
  #1 reset_i = 1'b0;
  @ (negedge busy_o);

  #1 clock_divider_i = 1;

  #1 send_byte(8'h55);
end

task send_byte;
  input [7:0] data;

  begin
    #2
    data_i = data;
    write_i = 1'b1;

    #3 if (serial_o)
      $display("FAILED - start bit incorrect");

    #1 write_i = 1'b0;

    #1 if (serial_o != data[0])
      $display("FAILED - data bit 0 incorrect");

    #2 if (serial_o != data[1])
      $display("FAILED - data bit 1 incorrect");

    #2 if (serial_o != data[2])
      $display("FAILED - data bit 2 incorrect");

    #2 if (serial_o != data[3])
      $display("FAILED - data bit 3 incorrect");

    #2 if (serial_o != data[4])
      $display("FAILED - data bit 4 incorrect");

    #2 if (serial_o != data[5])
      $display("FAILED - data bit 5 incorrect");

    #2 if (serial_o != data[6])
      $display("FAILED - data bit 6 incorrect");

    #2 if (serial_o != data[7])
      $display("FAILED - data bit 7 incorrect");

    #2 if (!serial_o)
      $display("FAILED - stop bit 1 incorrect");

    #2 if (!serial_o)
      $display("FAILED - stop bit 2 incorrect");

    #2 if (busy_o)
      $display("FAILED - busy_o should be low after sending first packet");
  end
endtask

endmodule