data/full_repos/permissive/153690221/Source/cacheTestBench.v
 line:115: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/153690221/Source/cacheTestBench.v:111: Unsupported: Ignoring delay on this delayed statement.\n        forever #1 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/153690221/Source/cacheTestBench.v:115: syntax error, unexpected \'@\'\n      repeat (40) @(posedge clk);\n                  ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cacheTestBench;
    reg clk,rst,write, writeI;

    reg [59:0] address;
    reg [2:0] command;
    reg [13:0] setRead, setReadI;

    wire [61:0] L2message, L2messageI;
    wire [45:0] way1D, way2D, way3D, way4D, way5D, way6D, way7D, way8D;
    wire [44:0] way1I, way2I, way3I, way4I;
    wire processingD, processingI, processing;
    wire [63:0] missesD, hitsD, totalD, writesD, readsD, missesI, hitsI, totalI, writesI, readsI;
    reg [63:0] misses, hits, total, reads, writes;
    integer mode;
    reg [63:0] counter;

    parameter

          READ = 3'd0,
          WRITE = 3'd1,
          INVALIDATE = 3'd2,
          CLEAR = 3'd3,
          L2DATAREQUEST = 3'd4,
          

          RETURNDATA = 2'd0,
          LWWRITE = 2'd1,
          L2READ = 2'd2,
          L2READFOWN = 2'd3,
          

          INVALID = 2'd0,
          MODIFIED = 2'd1,
          SHARED = 2'd2,
          EXCLUSIVE = 2'd3;

    datacacheL1 L1D(
        .clk(clk),
        .rst(rst),
        .write(write),
        .address(address),
        .command(command),
        .setRead(setRead),
        .L2message(L2message),
        .processing(processingD),
        .way1(way1D),
        .way2(way2D), 
        .way3(way3D), 
        .way4(way4D), 
        .way5(way5D), 
        .way6(way6D), 
        .way7(way7D), 
        .way8(way8D),
        .reads(readsD),
        .writes(writesD),
        .hits(hitsD),
        .misses(missesD),
        .total(totalD)
    );
    
    instructioncacheL1 L1I(
        .clk(clk),
        .rst(rst),
        .write(writeI),
        .address(address),
        .command(command),
        .setRead(setReadI),
        .L2message(L2messageI),
        .processing(processingI),
        .way1(way1I),
        .way2(way2I), 
        .way3(way3I), 
        .way4(way4I),
        .reads(readsI),
        .writes(writesI),
        .hits(hitsI),
        .misses(missesI),
        .total(totalI)
    );

    assign processing = processingD | processingI;

    initial begin
    $value$plusargs ("MODE=%d", mode);
    if(mode == 0) begin

    end
    else begin

    end
    end
	
    integer endTime;
    initial
    begin
        counter = 0;
        command = READ;
        setRead = 14'h1960;
        setReadI = 14'h1960;
        address = 60'h3865837;
        rst = 0;
        clk = 0;
        write = 1;
        writeI = 0;
        forever #1 clk = ~clk;
    end

    initial begin
      repeat (40) @(posedge clk);
      $stop;
    end
    
    always@(posedge clk) begin
        misses <= missesI + missesD;
        hits <= hitsI + hitsD;
        total <= totalI + totalD;
        reads <= readsI + readsD;
        writes <= writesI + writesD;

        counter <= counter + 1;
        if(processing && writeI) writeI <= 0;
        if(processing && write) write <= 0;

        if(counter < 20) begin
          if(!processing && !write) write <= 1;
        end
        else begin
          if(!processing && !writeI) writeI <= 1;
        end
    end
endmodule
module cacheTestBench;

    reg clk,rst,write, writeI;

    reg [59:0] address;
    reg [2:0] command;
    reg [13:0] setRead, setReadI;

    wire [61:0] L2message, L2messageI;
    wire [45:0] way1D, way2D, way3D, way4D, way5D, way6D, way7D, way8D;
    wire [44:0] way1I, way2I, way3I, way4I;
    wire processingD, processingI, processing;
    wire [63:0] missesD, hitsD, totalD, writesD, readsD, missesI, hitsI, totalI, writesI, readsI;
    reg [63:0] misses, hits, total, reads, writes;
    integer mode;
    reg [63:0] counter;

    parameter

          READ = 3'd0,
          WRITE = 3'd1,
          INVALIDATE = 3'd2,
          CLEAR = 3'd3,
          L2DATAREQUEST = 3'd4,
          

          RETURNDATA = 2'd0,
          LWWRITE = 2'd1,
          L2READ = 2'd2,
          L2READFOWN = 2'd3,
          

          INVALID = 2'd0,
          MODIFIED = 2'd1,
          SHARED = 2'd2,
          EXCLUSIVE = 2'd3;

    datacacheL1 L1D(
        .clk(clk),
        .rst(rst),
        .write(write),
        .address(address),
        .command(command),
        .setRead(setRead),
        .L2message(L2message),
        .processing(processingD),
        .way1(way1D),
        .way2(way2D), 
        .way3(way3D), 
        .way4(way4D), 
        .way5(way5D), 
        .way6(way6D), 
        .way7(way7D), 
        .way8(way8D),
        .reads(readsD),
        .writes(writesD),
        .hits(hitsD),
        .misses(missesD),
        .total(totalD)
    );
    
    instructioncacheL1 L1I(
        .clk(clk),
        .rst(rst),
        .write(writeI),
        .address(address),
        .command(command),
        .setRead(setReadI),
        .L2message(L2messageI),
        .processing(processingI),
        .way1(way1I),
        .way2(way2I), 
        .way3(way3I), 
        .way4(way4I),
        .reads(readsI),
        .writes(writesI),
        .hits(hitsI),
        .misses(missesI),
        .total(totalI)
    );

    assign processing = processingD | processingI;

    initial begin
    $value$plusargs ("MODE=%d", mode);
    if(mode == 0) begin

    end
    else begin

    end
    end
	
    integer endTime;
    initial
    begin
        counter = 0;
        command = READ;
        setRead = 14'h1960;
        setReadI = 14'h1960;
        address = 60'h3865837;
        rst = 0;
        clk = 0;
        write = 1;
        writeI = 0;
        forever #1 clk = ~clk;
    end

    initial begin
      repeat (40) @(posedge clk);
      $stop;
    end
    
    always@(posedge clk) begin
        misses <= missesI + missesD;
        hits <= hitsI + hitsD;
        total <= totalI + totalD;
        reads <= readsI + readsD;
        writes <= writesI + writesD;

        counter <= counter + 1;
        if(processing && writeI) writeI <= 0;
        if(processing && write) write <= 0;

        if(counter < 20) begin
          if(!processing && !write) write <= 1;
        end
        else begin
          if(!processing && !writeI) writeI <= 1;
        end
    end
endmodule