data/full_repos/permissive/214620165/rtl/core/riscv_irq_sync.sv
 line:114 column:23: Illegal character "'"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/214620165/rtl/core/riscv_irq_sync.sv:62: Signal definition not found, creating implicitly: \'irq_debug\'\n                                                                                     : ... Suggested alternative: \'irq_debug_i\'\n .q    (irq_debug)\n        ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module riscv_irq_sync(

	input  logic 							clk,
	input  logic 							rst_n,
	input  logic 							irq_gpio_i,
	input  logic                            irq_timer_i,
	input  logic                            irq_debug_i,
	output logic                            irq_debug_sync_o,
	input 	logic							debug_mode_i,
	
	output logic    	                    irq_o         ,
  	output logic  [ 4:0]                    irq_id_o      ,
  	input  logic                            irq_ack_i     ,
  	input  logic  [ 4:0]                    irq_id_i      ,
  	output logic                            irq_sec_o     ,
	output logic							irq_timer_sync_o,
	output logic							irq_gpio_sync_o  
);

logic 		irq_timer;
logic 		irq_gpio;
logic [4:0] irq_id;
logic       irq_happen;
logic		debug_mode_i_r;

sync_pose timer_sync (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_timer_i),
	.q    (irq_timer)
	);

sync_pose gpio_sync (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_gpio_i),
	.q    (irq_gpio)
	);

sync_pose debug_sync (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_debug_i),
	.q    (irq_debug)
	);	
	
sync     debug_sync_level (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_debug_i),
	.q    (irq_debug_sync_o)
	);

sync     gpio_sync_level (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_gpio_i),
	.q    (irq_gpio_sync_o)
	);
	
	sync     timer_sync_level (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_timer_i),
	.q    (irq_timer_sync_o)
	);















always_comb begin  
 	irq_happen = irq_timer | irq_gpio | irq_debug;
	case(1)
		irq_timer:  irq_id = 5'd7; 
		irq_gpio :  irq_id = 5'd11;

		irq_debug:	irq_id = 5'd12;
		default:   irq_id = 5'd7;
	endcase

end

always_ff @(posedge clk or negedge rst_n) begin 
		if(~rst_n) begin
			debug_mode_i_r <= '0;
			
		end else begin
			debug_mode_i_r <= debug_mode_i;
		end
	end
	
	logic debug_mode_i_nege;
	assign debug_mode_i_nege = ~debug_mode_i & debug_mode_i_r;

logic [4:0] irq_id_t;
assign irq_id_o =debug_mode_i_nege ? irq_id : irq_id_t;
always_ff @(posedge clk or negedge rst_n) begin 
	if(~rst_n) begin
		irq_id_t<= '0;
		irq_o   <= '0;
	end else begin
		irq_o   <= irq_happen;
		if(irq_happen | debug_mode_i_nege)
		 	irq_id_t<= irq_id;
	end
end

assign irq_sec_o = 1'b1;


endmodule
module riscv_irq_sync(

	input  logic 							clk,
	input  logic 							rst_n,
	input  logic 							irq_gpio_i,
	input  logic                            irq_timer_i,
	input  logic                            irq_debug_i,
	output logic                            irq_debug_sync_o,
	input 	logic							debug_mode_i,
	
	output logic    	                    irq_o         ,
  	output logic  [ 4:0]                    irq_id_o      ,
  	input  logic                            irq_ack_i     ,
  	input  logic  [ 4:0]                    irq_id_i      ,
  	output logic                            irq_sec_o     ,
	output logic							irq_timer_sync_o,
	output logic							irq_gpio_sync_o  
);


logic 		irq_timer;
logic 		irq_gpio;
logic [4:0] irq_id;
logic       irq_happen;
logic		debug_mode_i_r;

sync_pose timer_sync (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_timer_i),
	.q    (irq_timer)
	);

sync_pose gpio_sync (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_gpio_i),
	.q    (irq_gpio)
	);

sync_pose debug_sync (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_debug_i),
	.q    (irq_debug)
	);	
	
sync     debug_sync_level (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_debug_i),
	.q    (irq_debug_sync_o)
	);

sync     gpio_sync_level (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_gpio_i),
	.q    (irq_gpio_sync_o)
	);
	
	sync     timer_sync_level (
	.clk  (clk),
	.rst_n(rst_n),
	.d    (irq_timer_i),
	.q    (irq_timer_sync_o)
	);















always_comb begin  
 	irq_happen = irq_timer | irq_gpio | irq_debug;
	case(1)
		irq_timer:  irq_id = 5'd7; 
		irq_gpio :  irq_id = 5'd11;

		irq_debug:	irq_id = 5'd12;
		default:   irq_id = 5'd7;
	endcase

end

always_ff @(posedge clk or negedge rst_n) begin 
		if(~rst_n) begin
			debug_mode_i_r <= '0;
			
		end else begin
			debug_mode_i_r <= debug_mode_i;
		end
	end
	
	logic debug_mode_i_nege;
	assign debug_mode_i_nege = ~debug_mode_i & debug_mode_i_r;

logic [4:0] irq_id_t;
assign irq_id_o =debug_mode_i_nege ? irq_id : irq_id_t;
always_ff @(posedge clk or negedge rst_n) begin 
	if(~rst_n) begin
		irq_id_t<= '0;
		irq_o   <= '0;
	end else begin
		irq_o   <= irq_happen;
		if(irq_happen | debug_mode_i_nege)
		 	irq_id_t<= irq_id;
	end
end

assign irq_sec_o = 1'b1;


endmodule