data/full_repos/permissive/218779832/junk/pipeControl_main.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/218779832/junk/pipeControl_main.v:52: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'CCG1\'\nmodule CCG1\n       ^~~~\n                                                                                  : ... Top module \'CCG2\'\nmodule CCG2(\n       ^~~~\n                                                                                  : ... Top module \'CCG3\'\nmodule CCG3(\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/218779832/junk/pipeControl_main.v:134: Signal definition not found, creating implicitly: \'S82\'\nassign {S11, S10, S20, S30, S40, S50, S82, S81, S80} = muxBits;\n                                      ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/218779832/junk/pipeControl_main.v:134: Signal definition not found, creating implicitly: \'S81\'\n                                                                                   : ... Suggested alternative: \'S11\'\nassign {S11, S10, S20, S30, S40, S50, S82, S81, S80} = muxBits;\n                                           ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/218779832/junk/pipeControl_main.v:134: Signal definition not found, creating implicitly: \'S80\'\n                                                                                   : ... Suggested alternative: \'S10\'\nassign {S11, S10, S20, S30, S40, S50, S82, S81, S80} = muxBits;\n                                                ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/218779832/junk/pipeControl_main.v:92: Signal definition not found, creating implicitly: \'flagcheck\'\n                                                                                  : ... Suggested alternative: \'flagCheck\'\nassign flagcheck = FL_reg;\n       ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/218779832/junk/pipeControl_main.v:41: Signal definition not found, creating implicitly: \'flagCheck\'\n                                                                                  : ... Suggested alternative: \'flagCheck_1\'\nassign flagCheck = FL_reg;\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:134: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'muxBits\' generates 10 bits.\n                                                                                : ... In instance CCG3\nassign {S11, S10, S20, S30, S40, S50, S82, S81, S80} = muxBits;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:139: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n    muxBits = 9\'b000000000;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:148: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:153: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:159: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:164: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h80\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b01_0000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:169: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h180\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b11_0000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:174: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hc0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b01_1000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:179: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1c0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b11_1000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:184: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h140\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b10_1000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:190: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h80\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b01_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:194: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b00_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:200: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:205: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h5\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_101;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:210: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h3\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_011;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:215: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h6\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_110;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:222: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h21\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0100_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:230: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h180\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b11_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:233: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b00_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:241: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hc0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b01_1000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:244: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b00_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:252: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1c0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b11_1000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:255: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b00_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:262: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h21\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0100_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:268: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h140\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b10_1000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:271: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b00_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:277: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h21\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0100_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:282: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h2\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_010;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:287: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:292: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h8\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0001_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:297: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h48\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_1001_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:302: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:308: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h4\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_100;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:313: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h44\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_1000_100;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:318: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:323: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:328: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:333: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:338: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:343: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:348: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:353: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:358: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:363: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:368: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:373: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:378: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:383: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Error: Exiting due to 54 warning(s)\n'
module CCG3(
    input clk,
    input   [7:0]   opcode,
    input       flagCheck,
    input  [2:0]     write_address,
    input  [7:0]     NPC_in,
    input  [7:0]     OR2,
    output RD,  WR,
    output L_PC,
    output S_AL,
    output S11, S10,
    output S20,
    output S60,
    output S30, S40,
    output S50,

    output [1:0] rw,
    output [2:0] mux_sel,
    output clr , we
);


reg [10:0] controlBits;
reg [9:0] muxBits;




assign {RD, WR, clr , we , mux_sel , rw , L_PC,S_AL} = controlBits;
assign {S11, S10, S20, S30, S40, S50, S82, S81, S80} = muxBits;

initial begin
    controlBits = 11'b00000000000;

    muxBits = 9'b000000000;
end

always @ (posedge clk)
begin
    casex (opcode)
    8'b0000_0_000 : begin

        controlBits <= 11'b00_00000_00_0_0;
        muxBits <= 9'b00_0000_000;
    end
    8'b0000_0_001 : begin

        controlBits <= 11'b00_10000_00_0_0;
        muxBits <= 9'b00_0000_001;
    end
    8'b0000_0_010 : begin


        controlBits <= 11'b00_00000_00_0_1;
        muxBits <= 9'b00_0000_000;
    end
    8'b0000_0_011 : begin

        controlBits <= 11'b00_00000_00_1_0;
        muxBits <= 9'b01_0000_000;
    end
    8'b0000_0_100 : begin

        controlBits <= 11'b00_00000_00_1_0;
        muxBits <= 9'b11_0000_000;
    end
    8'b0000_0_101 : begin

        controlBits <= 11'b01_00000_01_1_0;
        muxBits <= 9'b01_1000_000;
    end
    8'b0000_0_110 : begin

        controlBits <= 11'b01_00000_01_1_0;
        muxBits <= 9'b11_1000_000;
    end
    8'b0000_0_111 : begin

        controlBits <= 11'b10_00000_10_1_0;
        muxBits <= 9'b10_1000_000;
    end
    8'b0000_1_xxx : begin
        if (flagCheck) begin

            controlBits <= 11'b00_00000_00_1_0; 
            muxBits <= 9'b01_0000_000;
        end else begin

            controlBits <= 11'b00_00000_00_0_0;
            muxBits <= 9'b00_0000_000;
        end
    end
    8'b0001_0_000 : begin

        controlBits <= 11'b00_00000_11_0_0;
        muxBits <= 9'b00_0000_000;
    end
    8'b0001_0_xxx : begin

        controlBits <= 11'b00_01000_00_0_0;
        muxBits <= 9'b00_0000_101;
    end
    8'b0001_1_000 : begin

        controlBits <= 11'b00_01100_00_0_0;
        muxBits <= 9'b00_0000_011;
    end
    8'b0001_1_xxx : begin

        controlBits <= 11'b00_01101_00_0_0;
        muxBits <= 9'b00_0000_110;
    end


    8'b0010_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0100_001;
    end


    8'b0010_1_xxx : begin
        if (flagCheck) begin

            controlBits <= 11'b00_00000_00_1_0;
            muxBits <= 9'b11_0000_000;
        end else begin
            controlBits <= 11'b00_00000_00_0_0;
            muxBits <= 9'b00_0000_000;
        end
    end

    8'b0011_0_xxx : begin
        if (flagCheck) begin

            controlBits <= 11'b01_00000_01_1_0;
            muxBits <= 9'b01_1000_000;
        end else begin
            controlBits <= 11'b00_00000_00_0_0;
            muxBits <= 9'b00_0000_000;
        end
    end

    8'b0011_1_xxx : begin
        if (flagCheck) begin

            controlBits <= 11'b01_00000_01_1_0;
            muxBits <= 9'b11_1000_000;
        end else begin
            controlBits <= 11'b00_00000_00_0_0;
            muxBits <= 9'b00_0000_000;
        end
    end

    8'b0100_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0100_001;
    end
    8'b0100_1_xxx : begin
        if (flagCheck) begin

            controlBits <= 11'b10_00000_10_1_0;
            muxBits <= 9'b10_1000_000;
        end else begin
            controlBits <= 11'b00_00000_00_0_0;
            muxBits <= 9'b00_0000_000;
        end
    end
    8'b0101_0_xxx : begin

        controlBits <= 11'b00_0111_00_0_1;
        muxBits <= 9'b00_0100_001;
    end
    8'b0101_1_xxx : begin

        controlBits <= 11'b00_01010_00_0_0;
        muxBits <= 9'b00_0000_010;
    end
    8'b0110_0_000 : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b0110_0_xxx : begin

        controlBits <= 11'b01_00000_00_0_0;
        muxBits <= 9'b00_0001_000;
    end
    8'b0110_1_xxx : begin

        controlBits <= 11'b01_00000_01_0_0;
        muxBits <= 9'b00_1001_000;
    end
    8'b0111_0_000 : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b0111_0_xxx : begin


        controlBits <= 11'b10_01110_00_0_0;
        muxBits <= 9'b00_0000_100;
    end
    8'b0111_1_xxx : begin

        controlBits <= 11'b10_01110_10_0_0;
        muxBits <= 9'b00_1000_100;
    end
    8'b1000_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b1000_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0110_000;
    end
    8'b1001_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b1001_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0110_000;
    end
    8'b1010_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b1010_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0110_000;
    end
    8'b1011_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b1011_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0110_000;
    end
    8'b1100_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b1100_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 9'b00_0110_000;
    end
    8'b1101_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 9'b00_0000_001;
    end
    8'b1101_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;  
        muxBits <= 9'b00_0110_000;
    end
    8'b1110_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 9'b00_0000_001;
    end
    8'b1110_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;  
        muxBits <= 9'b00_0110_000;
    end


    endcase
end

endmodule
module CCG3(
    input clk,
    input   [7:0]   opcode,
    input       flagCheck,
    input  [2:0]     write_address,
    input  [7:0]     NPC_in,
    input  [7:0]     OR2,
    output RD,  WR,
    output L_PC,
    output S_AL,
    output S11, S10,
    output S20,
    output S60,
    output S30, S40,
    output S50,

    output [1:0] rw,
    output [2:0] mux_sel,
    output clr , we
);



reg [10:0] controlBits;
reg [9:0] muxBits;




assign {RD, WR, clr , we , mux_sel , rw , L_PC,S_AL} = controlBits;
assign {S11, S10, S20, S30, S40, S50, S82, S81, S80} = muxBits;

initial begin
    controlBits = 11'b00000000000;

    muxBits = 9'b000000000;
end

always @ (posedge clk)
begin
    casex (opcode)
    8'b0000_0_000 : begin

        controlBits <= 11'b00_00000_00_0_0;
        muxBits <= 9'b00_0000_000;
    end
    8'b0000_0_001 : begin

        controlBits <= 11'b00_10000_00_0_0;
        muxBits <= 9'b00_0000_001;
    end
    8'b0000_0_010 : begin


        controlBits <= 11'b00_00000_00_0_1;
        muxBits <= 9'b00_0000_000;
    end
    8'b0000_0_011 : begin

        controlBits <= 11'b00_00000_00_1_0;
        muxBits <= 9'b01_0000_000;
    end
    8'b0000_0_100 : begin

        controlBits <= 11'b00_00000_00_1_0;
        muxBits <= 9'b11_0000_000;
    end
    8'b0000_0_101 : begin

        controlBits <= 11'b01_00000_01_1_0;
        muxBits <= 9'b01_1000_000;
    end
    8'b0000_0_110 : begin

        controlBits <= 11'b01_00000_01_1_0;
        muxBits <= 9'b11_1000_000;
    end
    8'b0000_0_111 : begin

        controlBits <= 11'b10_00000_10_1_0;
        muxBits <= 9'b10_1000_000;
    end
    8'b0000_1_xxx : begin
        if (flagCheck) begin

            controlBits <= 11'b00_00000_00_1_0; 
            muxBits <= 9'b01_0000_000;
        end else begin

            controlBits <= 11'b00_00000_00_0_0;
            muxBits <= 9'b00_0000_000;
        end
    end
    8'b0001_0_000 : begin

        controlBits <= 11'b00_00000_11_0_0;
        muxBits <= 9'b00_0000_000;
    end
    8'b0001_0_xxx : begin

        controlBits <= 11'b00_01000_00_0_0;
        muxBits <= 9'b00_0000_101;
    end
    8'b0001_1_000 : begin

        controlBits <= 11'b00_01100_00_0_0;
        muxBits <= 9'b00_0000_011;
    end
    8'b0001_1_xxx : begin

        controlBits <= 11'b00_01101_00_0_0;
        muxBits <= 9'b00_0000_110;
    end


    8'b0010_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0100_001;
    end


    8'b0010_1_xxx : begin
        if (flagCheck) begin

            controlBits <= 11'b00_00000_00_1_0;
            muxBits <= 9'b11_0000_000;
        end else begin
            controlBits <= 11'b00_00000_00_0_0;
            muxBits <= 9'b00_0000_000;
        end
    end

    8'b0011_0_xxx : begin
        if (flagCheck) begin

            controlBits <= 11'b01_00000_01_1_0;
            muxBits <= 9'b01_1000_000;
        end else begin
            controlBits <= 11'b00_00000_00_0_0;
            muxBits <= 9'b00_0000_000;
        end
    end

    8'b0011_1_xxx : begin
        if (flagCheck) begin

            controlBits <= 11'b01_00000_01_1_0;
            muxBits <= 9'b11_1000_000;
        end else begin
            controlBits <= 11'b00_00000_00_0_0;
            muxBits <= 9'b00_0000_000;
        end
    end

    8'b0100_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0100_001;
    end
    8'b0100_1_xxx : begin
        if (flagCheck) begin

            controlBits <= 11'b10_00000_10_1_0;
            muxBits <= 9'b10_1000_000;
        end else begin
            controlBits <= 11'b00_00000_00_0_0;
            muxBits <= 9'b00_0000_000;
        end
    end
    8'b0101_0_xxx : begin

        controlBits <= 11'b00_0111_00_0_1;
        muxBits <= 9'b00_0100_001;
    end
    8'b0101_1_xxx : begin

        controlBits <= 11'b00_01010_00_0_0;
        muxBits <= 9'b00_0000_010;
    end
    8'b0110_0_000 : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b0110_0_xxx : begin

        controlBits <= 11'b01_00000_00_0_0;
        muxBits <= 9'b00_0001_000;
    end
    8'b0110_1_xxx : begin

        controlBits <= 11'b01_00000_01_0_0;
        muxBits <= 9'b00_1001_000;
    end
    8'b0111_0_000 : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b0111_0_xxx : begin


        controlBits <= 11'b10_01110_00_0_0;
        muxBits <= 9'b00_0000_100;
    end
    8'b0111_1_xxx : begin

        controlBits <= 11'b10_01110_10_0_0;
        muxBits <= 9'b00_1000_100;
    end
    8'b1000_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b1000_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0110_000;
    end
    8'b1001_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b1001_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0110_000;
    end
    8'b1010_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b1010_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0110_000;
    end
    8'b1011_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b1011_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0110_000;
    end
    8'b1100_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 9'b00_0000_001;
    end
    8'b1100_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 9'b00_0110_000;
    end
    8'b1101_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 9'b00_0000_001;
    end
    8'b1101_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;  
        muxBits <= 9'b00_0110_000;
    end
    8'b1110_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 9'b00_0000_001;
    end
    8'b1110_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;  
        muxBits <= 9'b00_0110_000;
    end


    endcase
end

endmodule