data/full_repos/permissive/205055389/test/verga/module1.v
 line:15: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/module1.v:6: Unsupported: Ignoring delay on this delayed statement.\n #20 ck = ~ck;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/module1.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #500 $finish;\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
   reg ck;

   always
     begin
	#20 ck = ~ck;
      end


   always @(ck) $display("ck=%b",ck);

   initial
	begin
	   ck = 1'b0;
	   #500 $finish;
	end

   foo f1;

endmodule
module top;

   reg ck;

   always
     begin
	#20 ck = ~ck;
      end


   always @(ck) $display("ck=%b",ck);

   initial
	begin
	   ck = 1'b0;
	   #500 $finish;
	end

   foo f1;

endmodule