data/full_repos/permissive/21716763/uncle_gates/tb_signal_gen.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_signal_gen.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD/2) \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_signal_gen.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD/2);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_signal_gen.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_signal_gen.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_signal_gen.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/21716763/uncle_gates/tb_signal_gen.v:67: Unsupported or unknown PLI call: $monitor\n  $monitor(" %0d %b", $time, gnt);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/21716763/uncle_gates/tb_signal_gen.v:69: Unsupported: wait statements\n  wait(gnt)\n  ^~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_signal_gen;

	parameter INPUT_PORTS = 3;
	

	reg clk;
	reg rst;
	reg req;


	wire [INPUT_PORTS-1:0] stm_value;
	wire gnt;


	signal_gen 
	#(.INPUT_PORTS(INPUT_PORTS))
	uut (
		.clk(clk), 
		.rst(rst), 
		.req(req), 
		.stm_value(stm_value), 
		.gnt(gnt)
	);
	
   parameter PERIOD = 10;

   always begin
      clk = 1'b0;
      #(PERIOD/2) 
		clk = 1'b1;
      #(PERIOD/2);
   end 

	initial begin

		rst = 1;
		req = 0;


		#100;
      
		rst = 0;
		req = 0;		

		#100;
		req = 1;
		$display($time, " << Starting the Simulation >>");
		
		#100;
		req = 0;	
		
		$monitor(" %0d %b", $time, gnt);
		
		wait(gnt)
		begin		
			$display($time, " << Finishing the Simulation >>");
			$stop;
		end
	end
      
endmodule
module tb_signal_gen;


	parameter INPUT_PORTS = 3;
	

	reg clk;
	reg rst;
	reg req;


	wire [INPUT_PORTS-1:0] stm_value;
	wire gnt;


	signal_gen 
	#(.INPUT_PORTS(INPUT_PORTS))
	uut (
		.clk(clk), 
		.rst(rst), 
		.req(req), 
		.stm_value(stm_value), 
		.gnt(gnt)
	);
	
   parameter PERIOD = 10;

   always begin
      clk = 1'b0;
      #(PERIOD/2) 
		clk = 1'b1;
      #(PERIOD/2);
   end 

	initial begin

		rst = 1;
		req = 0;


		#100;
      
		rst = 0;
		req = 0;		

		#100;
		req = 1;
		$display($time, " << Starting the Simulation >>");
		
		#100;
		req = 0;	
		
		$monitor(" %0d %b", $time, gnt);
		
		wait(gnt)
		begin		
			$display($time, " << Finishing the Simulation >>");
			$stop;
		end
	end
      
endmodule