data/full_repos/permissive/138443719/05-outputs/src/main.v
1: b'%Error: data/full_repos/permissive/138443719/05-outputs/src/main.v:11: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile(dumpfile_path);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/138443719/05-outputs/src/main.v:12: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,hello_world);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/138443719/05-outputs/src/main.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/138443719/05-outputs/src/main.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #8;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/138443719/05-outputs/src/main.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hello_world;




  reg dummy;
  reg[8*64:0] dumpfile_path = "output.vcd";

  initial begin
    dummy = $value$plusargs("VCD_PATH=%s", dumpfile_path);
    $dumpfile(dumpfile_path);
    $dumpvars(0,hello_world);
  end


  reg signal;

  initial begin

    signal = 0;
    #5;
    signal = 1;
    #8;
    signal = 0;
    #2;
    $finish;

  end

endmodule
module hello_world;





  reg dummy;
  reg[8*64:0] dumpfile_path = "output.vcd";

  initial begin
    dummy = $value$plusargs("VCD_PATH=%s", dumpfile_path);
    $dumpfile(dumpfile_path);
    $dumpvars(0,hello_world);
  end


  reg signal;

  initial begin

    signal = 0;
    #5;
    signal = 1;
    #8;
    signal = 0;
    #2;
    $finish;

  end

endmodule