data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new/screen.v
data/verilator_xmls/e79dff18-57e2-4bea-966d-df78bbfaf133.xml
module screen(clk,num,rst,led);

input clk;
input [3:0] num;
input rst;
output reg [6:0] led;
always @(posedge clk or posedge rst)
begin
    if(rst)
        led<=7'b1111110;
    else
    begin
        case(num)
            4'b0000:
                led <= 7'b1111110;
            4'b0001:
                led <= 7'b0110000;
            4'b0010:
                led <= 7'b1101101;
            4'b0011:
                led <= 7'b1111001;
            4'b0100:
                led <= 7'b0110011;
            4'b0101:
                led <= 7'b1011011;
            4'b0110:
                led <= 7'b1011111;
            4'b0111:
                led <= 7'b1110000;
            4'b1000:
                led <= 7'b1111111;
            4'b1001:
                led <= 7'b1111011;
            default:
                led <= 7'b1111110;
        endcase
    end
end
endmodule
module screen(clk,num,rst,led);


input clk;
input [3:0] num;
input rst;
output reg [6:0] led;
always @(posedge clk or posedge rst)
begin
    if(rst)
        led<=7'b1111110;
    else
    begin
        case(num)
            4'b0000:
                led <= 7'b1111110;
            4'b0001:
                led <= 7'b0110000;
            4'b0010:
                led <= 7'b1101101;
            4'b0011:
                led <= 7'b1111001;
            4'b0100:
                led <= 7'b0110011;
            4'b0101:
                led <= 7'b1011011;
            4'b0110:
                led <= 7'b1011111;
            4'b0111:
                led <= 7'b1110000;
            4'b1000:
                led <= 7'b1111111;
            4'b1001:
                led <= 7'b1111011;
            default:
                led <= 7'b1111110;
        endcase
    end
end
endmodule