data/full_repos/permissive/20430511/hardware/FPGA/wishbone/example/wb_sram_dual_port.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/7e90dd27-100e-4bb3-9105-7f3113d84665.xml
module wb_sram_dual_port
  #(parameter SBITS = 10,
    parameter SIZE  = 1 << SBITS,
    parameter ASB   = SBITS-1,
    parameter BSB   = SBITS+1,
    parameter DELAY = 3)
   (
    input             rst_i,


    input             a_clk_i,
    input             a_cyc_i,
    input             a_stb_i,
    input             a_we_i,
    input             a_bst_i,
    output reg        a_ack_o = 0,
    output reg        a_wat_o = 0,
    input [ASB:0]     a_adr_i,
    input [31:0]      a_dat_i,
    output reg [31:0] a_dat_o,


    input             b_clk_i,
    input             b_cyc_i,
    input             b_stb_i,
    input             b_we_i,
    input             b_bst_i,
    output reg        b_ack_o = 0,
    output reg        b_wat_o = 0,
    input [BSB:0]     b_adr_i,
    input [7:0]       b_dat_i,
    output reg [7:0]  b_dat_o
    );





   reg [7:0]           sram0 [0:SIZE-1];
   reg [7:0]           sram1 [0:SIZE-1];
   reg [7:0]           sram2 [0:SIZE-1];
   reg [7:0]           sram3 [0:SIZE-1];

   integer             i;
   initial begin : SRAM_INIT
      for (i = 0; i < SIZE; i = i+1) begin
        sram0[i] <= 0;
        sram1[i] <= 0;
        sram2[i] <= 0;
        sram3[i] <= 0;
      end
   end





`ifdef __WB_SRAM_CLASSIC
   wire a_ack_cls = a_cyc_i && a_stb_i && !a_ack_o;
   wire a_wat_cls = a_cyc_i && a_stb_i && a_bst_i && !a_ack_o;
`else
   reg  a_bst_dly = 0;
   wire a_wat_bst = 1'b0;
   wire a_ack_bst = a_cyc_i && a_stb_i && (!a_ack_o || a_bst_dly);

   always @(posedge a_cyc_i)
     a_bst_dly <= #DELAY a_bst_i;
`endif

   always @(posedge a_clk_i)
     if (rst_i) {a_wat_o, a_ack_o} <= #DELAY 2'b0;
`ifdef __WB_SRAM_CLASSIC
     else       {a_wat_o, a_ack_o} <= #DELAY {a_wat_cls, a_ack_cls};
`else
     else       {a_wat_o, a_ack_o} <= #DELAY {a_wat_bst, a_ack_bst};
`endif


   always @(posedge a_clk_i)
     if (!rst_i && a_cyc_i && a_stb_i) begin
        a_dat_o <= #DELAY {sram3[a_adr_i], sram2[a_adr_i], sram1[a_adr_i], sram0[a_adr_i]};
        if (a_we_i)
          {sram3[a_adr_i], sram2[a_adr_i], sram1[a_adr_i], sram0[a_adr_i]} <= #DELAY a_dat_i;
     end





   wire [ASB:0] b_adr = b_adr_i[BSB:2];

`ifdef __WB_SRAM_CLASSIC
   wire b_ack_cls = b_cyc_i && b_stb_i && !b_ack_o;
   wire b_wat_cls = b_cyc_i && b_stb_i && b_bst_i && !b_ack_o;
`else
   wire b_wat_bst = 1'b0;
   wire b_ack_bst = b_cyc_i && b_stb_i && (b_bst_i || !b_ack_o);
`endif

   always @(posedge b_clk_i)
     if (rst_i) {b_wat_o, b_ack_o} <= #DELAY 2'b0;
`ifdef __WB_SRAM_CLASSIC
     else       {b_wat_o, b_ack_o} <= #DELAY {b_wat_cls, b_ack_cls};
`else
     else       {b_wat_o, b_ack_o} <= #DELAY {b_wat_bst, b_ack_bst};
`endif



   reg [1:0]    m_reg = 0;
   reg [31:0]   d_reg;

   always @*
     case (m_reg)
       0: b_dat_o <= d_reg[ 7: 0];
       1: b_dat_o <= d_reg[15: 8];
       2: b_dat_o <= d_reg[23:16];
       3: b_dat_o <= d_reg[31:24];
     endcase

   always @(posedge b_clk_i)
     if (b_cyc_i && b_stb_i) begin
        m_reg <= #DELAY b_adr_i[1:0];
        d_reg <= #DELAY {sram3[b_adr], sram2[b_adr], sram1[b_adr], sram0[b_adr]};
        if (b_we_i)
          case (b_adr_i[1:0])
            0: sram0[b_adr] <= #DELAY b_dat_i;
            1: sram1[b_adr] <= #DELAY b_dat_i;
            2: sram2[b_adr] <= #DELAY b_dat_i;
            3: sram3[b_adr] <= #DELAY b_dat_i;
          endcase
     end




endmodule
module wb_sram_dual_port
  #(parameter SBITS = 10,
    parameter SIZE  = 1 << SBITS,
    parameter ASB   = SBITS-1,
    parameter BSB   = SBITS+1,
    parameter DELAY = 3)
   (
    input             rst_i,


    input             a_clk_i,
    input             a_cyc_i,
    input             a_stb_i,
    input             a_we_i,
    input             a_bst_i,
    output reg        a_ack_o = 0,
    output reg        a_wat_o = 0,
    input [ASB:0]     a_adr_i,
    input [31:0]      a_dat_i,
    output reg [31:0] a_dat_o,


    input             b_clk_i,
    input             b_cyc_i,
    input             b_stb_i,
    input             b_we_i,
    input             b_bst_i,
    output reg        b_ack_o = 0,
    output reg        b_wat_o = 0,
    input [BSB:0]     b_adr_i,
    input [7:0]       b_dat_i,
    output reg [7:0]  b_dat_o
    );






   reg [7:0]           sram0 [0:SIZE-1];
   reg [7:0]           sram1 [0:SIZE-1];
   reg [7:0]           sram2 [0:SIZE-1];
   reg [7:0]           sram3 [0:SIZE-1];

   integer             i;
   initial begin : SRAM_INIT
      for (i = 0; i < SIZE; i = i+1) begin
        sram0[i] <= 0;
        sram1[i] <= 0;
        sram2[i] <= 0;
        sram3[i] <= 0;
      end
   end





`ifdef __WB_SRAM_CLASSIC
   wire a_ack_cls = a_cyc_i && a_stb_i && !a_ack_o;
   wire a_wat_cls = a_cyc_i && a_stb_i && a_bst_i && !a_ack_o;
`else
   reg  a_bst_dly = 0;
   wire a_wat_bst = 1'b0;
   wire a_ack_bst = a_cyc_i && a_stb_i && (!a_ack_o || a_bst_dly);

   always @(posedge a_cyc_i)
     a_bst_dly <= #DELAY a_bst_i;
`endif

   always @(posedge a_clk_i)
     if (rst_i) {a_wat_o, a_ack_o} <= #DELAY 2'b0;
`ifdef __WB_SRAM_CLASSIC
     else       {a_wat_o, a_ack_o} <= #DELAY {a_wat_cls, a_ack_cls};
`else
     else       {a_wat_o, a_ack_o} <= #DELAY {a_wat_bst, a_ack_bst};
`endif


   always @(posedge a_clk_i)
     if (!rst_i && a_cyc_i && a_stb_i) begin
        a_dat_o <= #DELAY {sram3[a_adr_i], sram2[a_adr_i], sram1[a_adr_i], sram0[a_adr_i]};
        if (a_we_i)
          {sram3[a_adr_i], sram2[a_adr_i], sram1[a_adr_i], sram0[a_adr_i]} <= #DELAY a_dat_i;
     end





   wire [ASB:0] b_adr = b_adr_i[BSB:2];

`ifdef __WB_SRAM_CLASSIC
   wire b_ack_cls = b_cyc_i && b_stb_i && !b_ack_o;
   wire b_wat_cls = b_cyc_i && b_stb_i && b_bst_i && !b_ack_o;
`else
   wire b_wat_bst = 1'b0;
   wire b_ack_bst = b_cyc_i && b_stb_i && (b_bst_i || !b_ack_o);
`endif

   always @(posedge b_clk_i)
     if (rst_i) {b_wat_o, b_ack_o} <= #DELAY 2'b0;
`ifdef __WB_SRAM_CLASSIC
     else       {b_wat_o, b_ack_o} <= #DELAY {b_wat_cls, b_ack_cls};
`else
     else       {b_wat_o, b_ack_o} <= #DELAY {b_wat_bst, b_ack_bst};
`endif



   reg [1:0]    m_reg = 0;
   reg [31:0]   d_reg;

   always @*
     case (m_reg)
       0: b_dat_o <= d_reg[ 7: 0];
       1: b_dat_o <= d_reg[15: 8];
       2: b_dat_o <= d_reg[23:16];
       3: b_dat_o <= d_reg[31:24];
     endcase

   always @(posedge b_clk_i)
     if (b_cyc_i && b_stb_i) begin
        m_reg <= #DELAY b_adr_i[1:0];
        d_reg <= #DELAY {sram3[b_adr], sram2[b_adr], sram1[b_adr], sram0[b_adr]};
        if (b_we_i)
          case (b_adr_i[1:0])
            0: sram0[b_adr] <= #DELAY b_dat_i;
            1: sram1[b_adr] <= #DELAY b_dat_i;
            2: sram2[b_adr] <= #DELAY b_dat_i;
            3: sram3[b_adr] <= #DELAY b_dat_i;
          endcase
     end




endmodule