data/full_repos/permissive/210737016/wam_dis.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/210737016/wam_dis.v:41: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'wam_led\'\nmodule wam_led (             \n       ^~~~~~~\n                                                                    : ... Top module \'wam_lst\'\nmodule wam_lst (             \n       ^~~~~~~\n                                                                    : ... Top module \'wam_dis\'\nmodule wam_dis(              \n       ^~~~~~~\n%Error: data/full_repos/permissive/210737016/wam_dis.v:54: Cannot find file containing module: \'wam_tch\'\n    wam_tch tchc( .clk_19(clk_19), .btn(cout0), .tch(cout0s));\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_tch\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_tch.v\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_tch.sv\n             wam_tch\n             wam_tch.v\n             wam_tch.sv\n             obj_dir/wam_tch\n             obj_dir/wam_tch.v\n             obj_dir/wam_tch.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module wam_lst (
    input wire clk_19,
    input wire [7:0] tap,
    input wire lft,
    input wire rgt,
    input wire cout0,
    output reg lstn
    );

    reg  [3:0] cnt;
    wire trg;
    wire cout0s;

    wam_tch tchc( .clk_19(clk_19), .btn(cout0), .tch(cout0s));
    assign trg = tap[0] | tap[1] | tap[2] | tap[3] | tap[4] | tap[5] | tap[6] | tap[7] | lft | rgt | cout0s;

    always @ (posedge clk_19) begin
        if (cnt > 0) begin
            if (cnt > 4'b0100) begin
                cnt <= 4'b0000;
                lstn <= 0;
            end
            else begin
                cnt <= cnt + 1;
            end
        end
        else begin
            if (trg) begin
                cnt <= 4'b0001;
                lstn <= 1;
            end
        end
    end
endmodule
module wam_lst (
    input wire clk_19,
    input wire [7:0] tap,
    input wire lft,
    input wire rgt,
    input wire cout0,
    output reg lstn
    );


    reg  [3:0] cnt;
    wire trg;
    wire cout0s;

    wam_tch tchc( .clk_19(clk_19), .btn(cout0), .tch(cout0s));
    assign trg = tap[0] | tap[1] | tap[2] | tap[3] | tap[4] | tap[5] | tap[6] | tap[7] | lft | rgt | cout0s;

    always @ (posedge clk_19) begin
        if (cnt > 0) begin
            if (cnt > 4'b0100) begin
                cnt <= 4'b0000;
                lstn <= 0;
            end
            else begin
                cnt <= cnt + 1;
            end
        end
        else begin
            if (trg) begin
                cnt <= 4'b0001;
                lstn <= 1;
            end
        end
    end
endmodule