data/full_repos/permissive/131712122/bench/verilog/sync_check.v
 line:78: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:214: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:114: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'thsync\' generates 8 bits.\n                                                                                   : ... In instance sync_check\nassign hhtime_exp = (thsync +1) * clk_time;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:115: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'thlen\' generates 16 bits.\n                                                                                   : ... In instance sync_check\nassign htime_exp  = (thlen +1) * clk_time;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:116: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tvsync\' generates 8 bits.\n                                                                                   : ... In instance sync_check\nassign vhtime_exp = (htime_exp * (tvsync +1));\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:117: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tvlen\' generates 16 bits.\n                                                                                   : ... In instance sync_check\nassign vtime_exp  = htime_exp * (tvlen +1);\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:134: Operator NEQ expects 64 bits on the RHS, but RHS\'s VARREF \'htime_exp\' generates 32 bits.\n                                                                                   : ... In instance sync_check\n  if(hvalid & (htime != htime_exp))\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:145: Operator NEQ expects 64 bits on the RHS, but RHS\'s VARREF \'hhtime_exp\' generates 32 bits.\n                                                                                   : ... In instance sync_check\n  if(hvalid & (hhtime != hhtime_exp))\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:160: Operator NEQ expects 64 bits on the RHS, but RHS\'s VARREF \'vtime_exp\' generates 32 bits.\n                                                                                   : ... In instance sync_check\n  if(vvalid & (vtime != vtime_exp))\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:171: Operator NEQ expects 64 bits on the RHS, but RHS\'s VARREF \'vhtime_exp\' generates 32 bits.\n                                                                                   : ... In instance sync_check\n  if(vvalid & (vhtime != vhtime_exp))\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:183: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'tvsync\' generates 8 bits.\n                                                                                   : ... In instance sync_check\nassign bv_start = tvsync   + tvgdel + 1;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:183: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'tvgdel\' generates 8 bits.\n                                                                                   : ... In instance sync_check\nassign bv_start = tvsync   + tvgdel + 1;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:184: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'tvgate\' generates 16 bits.\n                                                                                   : ... In instance sync_check\nassign bv_end   = bv_start + tvgate + 2;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:186: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'thsync\' generates 8 bits.\n                                                                                   : ... In instance sync_check\nassign bh_start = thsync   + thgdel + 1;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:186: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'thgdel\' generates 8 bits.\n                                                                                   : ... In instance sync_check\nassign bh_start = thsync   + thgdel + 1;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/131712122/bench/verilog/sync_check.v:187: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'thgate\' generates 16 bits.\n                                                                                   : ... In instance sync_check\nassign bh_end   = bh_start + thgate + 2;\n                           ^\n%Error: Exiting due to 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sync_check(	pclk, rst, enable, hsync, vsync, csync, blanc,
			hpol, vpol, cpol, bpol,
			thsync, thgdel, thgate, thlen,
			tvsync, tvgdel, tvgate, tvlen);

input		pclk, rst, enable, hsync, vsync, csync, blanc;
input		hpol, vpol, cpol, bpol;
input	[7:0]	thsync, thgdel;
input	[15:0]	thgate, thlen;
input	[7:0]	tvsync, tvgdel;
input	[15:0]	tvgate, tvlen;


time		last_htime;
reg		hvalid;
time		htime;
time		hhtime;

time		last_vtime;
reg		vvalid;
time		vtime;
time		vhtime;

wire	[31:0]	htime_exp;
wire	[31:0]	hhtime_exp;
wire	[31:0]	vtime_exp;
wire	[31:0]	vhtime_exp;

wire		hcheck;
wire		vcheck;

wire	[31:0]	bh_start;
wire	[31:0]	bh_end;
wire	[31:0]	bv_start;
wire	[31:0]	bv_end;

integer		bdel1;
reg		bval1;
reg		bval;
integer		bdel2;
wire		bcheck;




parameter clk_time = 40;

assign hcheck = enable;
assign vcheck = enable;
assign hhtime_exp = (thsync +1) * clk_time;
assign htime_exp  = (thlen +1) * clk_time;
assign vhtime_exp = (htime_exp * (tvsync +1));
assign vtime_exp  = htime_exp * (tvlen +1);

always @(posedge pclk)
	if(!rst | !enable)
	   begin
		hvalid = 0;
		vvalid = 0;
	   end


always @(hsync)
   if(hcheck)
      begin
	if(hsync == ~hpol)
	   begin
		htime = $time - last_htime;

		if(hvalid & (htime != htime_exp))
			$display("HSYNC length ERROR: Expected: %0d Got: %0d (%0t)",
				htime_exp, htime, $time);
		last_htime = $time;
		hvalid = 1;
	   end

	if(hsync == hpol)
	   begin
		hhtime = $time - last_htime;

		if(hvalid & (hhtime != hhtime_exp))
			$display("HSYNC Pulse ERROR: Expected: %0d Got: %0d (%0t)",
				hhtime_exp, hhtime, $time);
	   end
      end



always @(vsync)
   if(vcheck)
      begin
	if(vsync == ~vpol)
	   begin
		vtime = $time - last_vtime;

		if(vvalid & (vtime != vtime_exp))
			$display("VSYNC length ERROR: Expected: %0d Got: %0d (%0t)",
				vtime_exp, vtime, $time);
		last_vtime = $time;
		vvalid = 1;
	   end

	if(vsync == vpol)
	   begin
		vhtime = $time - last_vtime;

		if(vvalid & (vhtime != vhtime_exp))
			$display("VSYNC Pulse ERROR: Expected: %0d Got: %0d (%0t)",
				vhtime_exp, vhtime, $time);
	   end
      end







assign bv_start = tvsync   + tvgdel + 1;
assign bv_end   = bv_start + tvgate + 2;

assign bh_start = thsync   + thgdel + 1;
assign bh_end   = bh_start + thgate + 2;

assign bcheck = enable;

always @(vsync)
	if(vsync == ~vpol)
		bdel1 = 0;

always @(hsync)
	if(hsync == ~hpol)
		bdel1 = bdel1 + 1;

always @(bdel1)
	bval1 = (bdel1 > bv_start) & (bdel1 < bv_end);

always @(hsync)
	if(hsync == ~hpol)
		bdel2 = 0;

always @(posedge pclk)
	bdel2 = bdel2 + 1;

initial bval = 1;
always @(bdel2)
	bval = #1 !(bval1 & (bdel2 > bh_start) & (bdel2 < bh_end));

always @(bval or blanc)
	#1
	if(enable)
	if(( (blanc ^ bpol) != bval) & bcheck)
		$display("BLANK ERROR: Expected: %0d Got: %0d (%0t)",
			bval, (blanc ^ bpol), $time);


always @(csync or vsync or hsync)
	if(enable)
	if( (csync ^ cpol) != ( (vsync ^ vpol) | (hsync ^ hpol) ) )
		$display("CSYNC ERROR: Expected: %0d Got: %0d (%0t)",
		( (vsync ^ vpol) | (hsync ^ hpol) ), (csync ^ cpol), $time);
endmodule
module sync_check(	pclk, rst, enable, hsync, vsync, csync, blanc,
			hpol, vpol, cpol, bpol,
			thsync, thgdel, thgate, thlen,
			tvsync, tvgdel, tvgate, tvlen);


input		pclk, rst, enable, hsync, vsync, csync, blanc;
input		hpol, vpol, cpol, bpol;
input	[7:0]	thsync, thgdel;
input	[15:0]	thgate, thlen;
input	[7:0]	tvsync, tvgdel;
input	[15:0]	tvgate, tvlen;


time		last_htime;
reg		hvalid;
time		htime;
time		hhtime;

time		last_vtime;
reg		vvalid;
time		vtime;
time		vhtime;

wire	[31:0]	htime_exp;
wire	[31:0]	hhtime_exp;
wire	[31:0]	vtime_exp;
wire	[31:0]	vhtime_exp;

wire		hcheck;
wire		vcheck;

wire	[31:0]	bh_start;
wire	[31:0]	bh_end;
wire	[31:0]	bv_start;
wire	[31:0]	bv_end;

integer		bdel1;
reg		bval1;
reg		bval;
integer		bdel2;
wire		bcheck;




parameter clk_time = 40;

assign hcheck = enable;
assign vcheck = enable;
assign hhtime_exp = (thsync +1) * clk_time;
assign htime_exp  = (thlen +1) * clk_time;
assign vhtime_exp = (htime_exp * (tvsync +1));
assign vtime_exp  = htime_exp * (tvlen +1);

always @(posedge pclk)
	if(!rst | !enable)
	   begin
		hvalid = 0;
		vvalid = 0;
	   end


always @(hsync)
   if(hcheck)
      begin
	if(hsync == ~hpol)
	   begin
		htime = $time - last_htime;

		if(hvalid & (htime != htime_exp))
			$display("HSYNC length ERROR: Expected: %0d Got: %0d (%0t)",
				htime_exp, htime, $time);
		last_htime = $time;
		hvalid = 1;
	   end

	if(hsync == hpol)
	   begin
		hhtime = $time - last_htime;

		if(hvalid & (hhtime != hhtime_exp))
			$display("HSYNC Pulse ERROR: Expected: %0d Got: %0d (%0t)",
				hhtime_exp, hhtime, $time);
	   end
      end



always @(vsync)
   if(vcheck)
      begin
	if(vsync == ~vpol)
	   begin
		vtime = $time - last_vtime;

		if(vvalid & (vtime != vtime_exp))
			$display("VSYNC length ERROR: Expected: %0d Got: %0d (%0t)",
				vtime_exp, vtime, $time);
		last_vtime = $time;
		vvalid = 1;
	   end

	if(vsync == vpol)
	   begin
		vhtime = $time - last_vtime;

		if(vvalid & (vhtime != vhtime_exp))
			$display("VSYNC Pulse ERROR: Expected: %0d Got: %0d (%0t)",
				vhtime_exp, vhtime, $time);
	   end
      end







assign bv_start = tvsync   + tvgdel + 1;
assign bv_end   = bv_start + tvgate + 2;

assign bh_start = thsync   + thgdel + 1;
assign bh_end   = bh_start + thgate + 2;

assign bcheck = enable;

always @(vsync)
	if(vsync == ~vpol)
		bdel1 = 0;

always @(hsync)
	if(hsync == ~hpol)
		bdel1 = bdel1 + 1;

always @(bdel1)
	bval1 = (bdel1 > bv_start) & (bdel1 < bv_end);

always @(hsync)
	if(hsync == ~hpol)
		bdel2 = 0;

always @(posedge pclk)
	bdel2 = bdel2 + 1;

initial bval = 1;
always @(bdel2)
	bval = #1 !(bval1 & (bdel2 > bh_start) & (bdel2 < bh_end));

always @(bval or blanc)
	#1
	if(enable)
	if(( (blanc ^ bpol) != bval) & bcheck)
		$display("BLANK ERROR: Expected: %0d Got: %0d (%0t)",
			bval, (blanc ^ bpol), $time);


always @(csync or vsync or hsync)
	if(enable)
	if( (csync ^ cpol) != ( (vsync ^ vpol) | (hsync ^ hpol) ) )
		$display("CSYNC ERROR: Expected: %0d Got: %0d (%0t)",
		( (vsync ^ vpol) | (hsync ^ hpol) ), (csync ^ cpol), $time);
endmodule