data/full_repos/permissive/146975244/Processador.v
1: b"%Error: data/full_repos/permissive/146975244/Processador.v:15: Cannot find file containing module: 'Temp'\nTemp t1(.clk_in(clockIn),.clockO(clock));\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/146975244,data/full_repos/permissive/146975244/Temp\n             data/full_repos/permissive/146975244,data/full_repos/permissive/146975244/Temp.v\n             data/full_repos/permissive/146975244,data/full_repos/permissive/146975244/Temp.sv\n             Temp\n             Temp.v\n             Temp.sv\n             obj_dir/Temp\n             obj_dir/Temp.v\n             obj_dir/Temp.sv\n%Error: data/full_repos/permissive/146975244/Processador.v:16: Cannot find file containing module: 'Control'\nControl bc(.instruction(instruction),.opcode(opcode),  .j(j),.branch(branch), .write(write),.memWrite(memWrite), .ALUop(ALUop), .ALUsrc(ALUsrc),.Rsrc(Rsrc),.Wsrc(Wsrc), .PCsrc(PCsrc),.I(I), .O(O), .Halt(Halt), .PCSignal(PCSignal));\n^~~~~~~\n%Error: data/full_repos/permissive/146975244/Processador.v:18: Cannot find file containing module: 'Instructions'\nInstructions  bi(.PC(PC),.Inst(instruction),.clock(clock));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/146975244/Processador.v:20: Cannot find file containing module: 'Banco'\nBanco bb(.r1(instruction[25:21]),.r2(instruction[20:16]), .r3(muxR), .data(muxWrite), .clock(clock), .write(write), .rd1(rd1),.rd2(rd2));\n^~~~~\n%Error: data/full_repos/permissive/146975244/Processador.v:22: Cannot find file containing module: 'ula'\nula balu(.a(rd1),.b(muxALU),.op(ALUop),.res(resALU),.zero(zeroALU),.clock(clock));\n^~~\n%Error: data/full_repos/permissive/146975244/Processador.v:24: Cannot find file containing module: 'MUX'\nMUX mR(.A(instruction[20:16]),.B(instruction[15:11]),.C(instruction[15:11]), .Sel(Rsrc), .Out(muxR),.clock(clock));\n^~~\n%Error: data/full_repos/permissive/146975244/Processador.v:25: Cannot find file containing module: 'MUX'\nMUX mAlu(.A(rd2),.B(resExtender),.C(instruction[25:0]), .Sel(ALUsrc), .Out(muxALU), .clock(clock));\n^~~\n%Error: data/full_repos/permissive/146975244/Processador.v:27: Cannot find file containing module: 'MUX'\nMUX mWrite(.A(resALU),.B(readData),.C(DataLCD), .Sel(Wsrc), .Out(muxWrite), .clock(clock));\n^~~\n%Error: data/full_repos/permissive/146975244/Processador.v:29: Cannot find file containing module: 'RAM'\nRAM bRAM(.data(rd2),.address(resALU), .write(memWrite), .read(readData), .clock(clock));\n^~~\n%Error: data/full_repos/permissive/146975244/Processador.v:31: Cannot find file containing module: 'Extender'\nExtender bExtender(.IMM16(instruction[15:0]), .result(resExtender), .clock(clock));\n^~~~~~~~\n%Error: data/full_repos/permissive/146975244/Processador.v:33: Cannot find file containing module: 'ProgramCounter'\nProgramCounter bPC( .PCIn(PCBranch), .signal(PCSignal), .clock(clock), .PCOut(PC), .reset(reset));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/146975244/Processador.v:35: Cannot find file containing module: 'BranchControl'\nBranchControl bBC(.halt(Halt), .j(j), .OK(OK), .branch(branch), .PCIn(PC), .zero(zeroALU), .IMM16(resExtender), .IMM26(instruction[25:0]), .clock(clock), .PCOut(PCBranch));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/146975244/Processador.v:37: Cannot find file containing module: 'InOut'\nInOut bIO(.clock(clock), .I(I), .O(O), .BusIn(BusIn), .DataLCD(DataLCD), .resALU(resALU), .Hex1(Hex1), .Hex2(Hex2), .Hex3(Hex3),.Hex4(Hex4), .pc(PC) );\n^~~~~\n%Error: Exiting due to 13 error(s)\n"
module  Processador (clockIn, OK, BusIn, reset, Hex1, Hex2, Hex3, Hex4);


input clockIn, reset, OK;


wire [31:0] instruction, resExtender, rd1, rd2, resALU, readData, muxALU, muxWrite, muxR;
wire j, clock, branch, memWrite, I , O, Halt, write,zeroALU,  PCSignal, IOFlag;
wire [1:0] ALUsrc,Rsrc,Wsrc, PCsrc;
wire [5:0] ALUop, opcode;
wire [10:0] PC, PCBranch;
input [14:0] BusIn;
wire [14:0]  DataLCD;
output [6:0] Hex1, Hex2, Hex3, Hex4;
Temp t1(.clk_in(clockIn),.clockO(clock));
Control bc(.instruction(instruction),.opcode(opcode),  .j(j),.branch(branch), .write(write),.memWrite(memWrite), .ALUop(ALUop), .ALUsrc(ALUsrc),.Rsrc(Rsrc),.Wsrc(Wsrc), .PCsrc(PCsrc),.I(I), .O(O), .Halt(Halt), .PCSignal(PCSignal));

Instructions  bi(.PC(PC),.Inst(instruction),.clock(clock));

Banco bb(.r1(instruction[25:21]),.r2(instruction[20:16]), .r3(muxR), .data(muxWrite), .clock(clock), .write(write), .rd1(rd1),.rd2(rd2));

ula balu(.a(rd1),.b(muxALU),.op(ALUop),.res(resALU),.zero(zeroALU),.clock(clock));

MUX mR(.A(instruction[20:16]),.B(instruction[15:11]),.C(instruction[15:11]), .Sel(Rsrc), .Out(muxR),.clock(clock));
MUX mAlu(.A(rd2),.B(resExtender),.C(instruction[25:0]), .Sel(ALUsrc), .Out(muxALU), .clock(clock));

MUX mWrite(.A(resALU),.B(readData),.C(DataLCD), .Sel(Wsrc), .Out(muxWrite), .clock(clock));

RAM bRAM(.data(rd2),.address(resALU), .write(memWrite), .read(readData), .clock(clock));

Extender bExtender(.IMM16(instruction[15:0]), .result(resExtender), .clock(clock));

ProgramCounter bPC( .PCIn(PCBranch), .signal(PCSignal), .clock(clock), .PCOut(PC), .reset(reset));

BranchControl bBC(.halt(Halt), .j(j), .OK(OK), .branch(branch), .PCIn(PC), .zero(zeroALU), .IMM16(resExtender), .IMM26(instruction[25:0]), .clock(clock), .PCOut(PCBranch));

InOut bIO(.clock(clock), .I(I), .O(O), .BusIn(BusIn), .DataLCD(DataLCD), .resALU(resALU), .Hex1(Hex1), .Hex2(Hex2), .Hex3(Hex3),.Hex4(Hex4), .pc(PC) );














 
endmodule
module  Processador (clockIn, OK, BusIn, reset, Hex1, Hex2, Hex3, Hex4);



input clockIn, reset, OK;


wire [31:0] instruction, resExtender, rd1, rd2, resALU, readData, muxALU, muxWrite, muxR;
wire j, clock, branch, memWrite, I , O, Halt, write,zeroALU,  PCSignal, IOFlag;
wire [1:0] ALUsrc,Rsrc,Wsrc, PCsrc;
wire [5:0] ALUop, opcode;
wire [10:0] PC, PCBranch;
input [14:0] BusIn;
wire [14:0]  DataLCD;
output [6:0] Hex1, Hex2, Hex3, Hex4;
Temp t1(.clk_in(clockIn),.clockO(clock));
Control bc(.instruction(instruction),.opcode(opcode),  .j(j),.branch(branch), .write(write),.memWrite(memWrite), .ALUop(ALUop), .ALUsrc(ALUsrc),.Rsrc(Rsrc),.Wsrc(Wsrc), .PCsrc(PCsrc),.I(I), .O(O), .Halt(Halt), .PCSignal(PCSignal));

Instructions  bi(.PC(PC),.Inst(instruction),.clock(clock));

Banco bb(.r1(instruction[25:21]),.r2(instruction[20:16]), .r3(muxR), .data(muxWrite), .clock(clock), .write(write), .rd1(rd1),.rd2(rd2));

ula balu(.a(rd1),.b(muxALU),.op(ALUop),.res(resALU),.zero(zeroALU),.clock(clock));

MUX mR(.A(instruction[20:16]),.B(instruction[15:11]),.C(instruction[15:11]), .Sel(Rsrc), .Out(muxR),.clock(clock));
MUX mAlu(.A(rd2),.B(resExtender),.C(instruction[25:0]), .Sel(ALUsrc), .Out(muxALU), .clock(clock));

MUX mWrite(.A(resALU),.B(readData),.C(DataLCD), .Sel(Wsrc), .Out(muxWrite), .clock(clock));

RAM bRAM(.data(rd2),.address(resALU), .write(memWrite), .read(readData), .clock(clock));

Extender bExtender(.IMM16(instruction[15:0]), .result(resExtender), .clock(clock));

ProgramCounter bPC( .PCIn(PCBranch), .signal(PCSignal), .clock(clock), .PCOut(PC), .reset(reset));

BranchControl bBC(.halt(Halt), .j(j), .OK(OK), .branch(branch), .PCIn(PC), .zero(zeroALU), .IMM16(resExtender), .IMM26(instruction[25:0]), .clock(clock), .PCOut(PCBranch));

InOut bIO(.clock(clock), .I(I), .O(O), .BusIn(BusIn), .DataLCD(DataLCD), .resALU(resALU), .Hex1(Hex1), .Hex2(Hex2), .Hex3(Hex3),.Hex4(Hex4), .pc(PC) );














 
endmodule