data/full_repos/permissive/162533945/multdiv.v
1: b"%Error: data/full_repos/permissive/162533945/multdiv.v:256: Cannot find file containing module: 'dffe_ref'\n dffe_ref dff0(.q(q0), .d(nq0), .clk(clk), .en(1'b1), .clr(reset));\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/dffe_ref\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/dffe_ref.v\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/dffe_ref.sv\n             dffe_ref\n             dffe_ref.v\n             dffe_ref.sv\n             obj_dir/dffe_ref\n             obj_dir/dffe_ref.v\n             obj_dir/dffe_ref.sv\n%Error: data/full_repos/permissive/162533945/multdiv.v:261: Cannot find file containing module: 'dffe_ref'\n dffe_ref dff1(.q(q1), .d(nq1), .clk(nq0), .en(1'b1), .clr(reset));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:266: Cannot find file containing module: 'dffe_ref'\n dffe_ref dff2(.q(q2), .d(nq2), .clk(nq1), .en(1'b1), .clr(reset));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:271: Cannot find file containing module: 'dffe_ref'\n dffe_ref dff3(.q(q3), .d(nq3), .clk(nq2), .en(1'b1), .clr(reset));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:276: Cannot find file containing module: 'dffe_ref'\n dffe_ref dff4(.q(q4), .d(nq4), .clk(nq3), .en(1'b1), .clr(reset));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:281: Cannot find file containing module: 'dffe_ref'\n dffe_ref dff5(.q(q5), .d(nq5), .clk(nq4), .en(1'b1), .clr(reset));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:222: Cannot find file containing module: 'dffe_ref'\n dffe_ref dff0(.q(q0), .d(nq0), .clk(clk), .en(1'b1), .clr(reset));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:227: Cannot find file containing module: 'dffe_ref'\n dffe_ref dff1(.q(q1), .d(nq1), .clk(nq0), .en(1'b1), .clr(reset));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:232: Cannot find file containing module: 'dffe_ref'\n dffe_ref dff2(.q(q2), .d(nq2), .clk(nq1), .en(1'b1), .clr(reset));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:237: Cannot find file containing module: 'dffe_ref'\n dffe_ref dff3(.q(q3), .d(nq3), .clk(nq2), .en(1'b1), .clr(reset));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:242: Cannot find file containing module: 'dffe_ref'\n dffe_ref dff4(.q(q4), .d(nq4), .clk(nq3), .en(1'b1), .clr(reset));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:56: Cannot find file containing module: 'mux_2to1_1bit'\n   mux_2to1_1bit mux_bitwise(.a(a[i]), .b(b[i]), .sel(sel), .out(out[i]));\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:292: Cannot find file containing module: 'adder'\n adder negate(.x(~in), .y(32'b1), .out(out), .sub(1'b0));\n ^~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:184: Cannot find file containing module: 'reg_32'\n reg_32 divisor_readin(.in(divisor), .out(divisor_readout), .write_enable(start), .clk(clk), .reset(1'b0));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:190: Cannot find file containing module: 'reg_32'\n reg_32 quotient(.in(quotient_in), .out(quotient_out), .write_enable(1'b1), .clk(clk), .reset(1'b0));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:191: Cannot find file containing module: 'reg_32'\n reg_32 remainder(.in(remainder_in), .out(remainder_out), .write_enable(1'b1), .clk(clk), .reset(start));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:196: Cannot find file containing module: 'adder'\n adder subtractor(.x(remainder_out), .y(sub_operand2), .sub(1'b1), .out(sub_result));\n ^~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:76: Cannot find file containing module: 'reg_32'\n reg_32 multplcd_readin(.in(multplcd), .out(multplcd_readout), .write_enable(start), .clk(clk), .reset(1'b0));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:79: Cannot find file containing module: 'dffe_ref'\n dffe_ref ovf_shift_same_sign(.q(same_sign), .d((multplcd[31] & multplr[31]) | ((~multplcd[31]) & (~multplr[31]))), .clk(clk), .en(start), .clr(1'b0));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:94: Cannot find file containing module: 'dffe_ref'\n  dffe_ref zero_dff_cand(.q(isZero_multiplicand), .d(isZero_multiplicand_in), .clk(clk), .en(start), .clr(1'b0));\n  ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:95: Cannot find file containing module: 'dffe_ref'\n  dffe_ref zero_dff_lier(.q(isZero_multiplier), .d(isZero_multiplier_in), .clk(clk), .en(start), .clr(1'b0));\n  ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:101: Cannot find file containing module: 'reg_32'\n reg_32 product_1(.in(wprod_1_in_after_mux), .out(wprod_1_out), .write_enable(1'b1), .clk(clk), .reset(1'b0));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:102: Cannot find file containing module: 'reg_32'\n reg_32 product_2(.in(wprod_2_in), .out(wprod_2_out), .write_enable(1'b1), .clk(clk), .reset(start));\n ^~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:111: Cannot find file containing module: 'dffe_ref'\n dffe_ref ovf_shift_dff(.q(overflow_shift), .d(1'b1), .clk(clk), .en(overflow_shift_temp), .clr(start));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:127: Cannot find file containing module: 'adder'\n adder addsub(.x(wprod_2_out), .y(addsub_operand1), .sub(isSub), .out(addsub_result));\n ^~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:130: Cannot find file containing module: 'dffe_ref'\n dffe_ref ovf_addsub_dff(.q(overflow_addsub), .d(1'b1), .clk(clk), .en(overflow_addsub_temp), .clr(start));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:158: Cannot find file containing module: 'dffe_ref'\n dffe_ref helper_bit(.q(helper), .d(wprod_1_out[1]), .clk(clk), .en(1'b1), .clr(start));\n ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:10: Cannot find file containing module: 'dffe_ref'\n  dffe_ref isMult_dff(.q(isMult), .d(ctrl_MULT), .clk(clock), .en(ctrl_MULT | ctrl_DIV), .clr(1'b0));\n  ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:11: Cannot find file containing module: 'dffe_ref'\n  dffe_ref isDiv_dff(.q(isDiv), .d(ctrl_DIV), .clk(clock), .en(ctrl_MULT | ctrl_DIV));\n  ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:14: Cannot find file containing module: 'dffe_ref'\n  dffe_ref zero_dff(.q(isDivByZero), .d(zero), .clk(clock), .en(ctrl_DIV));\n  ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:35: Cannot find file containing module: 'dffe_ref'\n  dffe_ref div_sign_dff(.q(div_result_sign_final), .d(div_result_sign), .clk(clock), .en(ctrl_DIV));\n  ^~~~~~~~\n%Error: data/full_repos/permissive/162533945/multdiv.v:41: Cannot find file containing module: 'mux_2to1_1bit'\n  mux_2to1_1bit mux_rdy(.a(div_rdy), .b(mult_rdy), .sel(isMult), .out(data_resultRDY_intermediate));\n  ^~~~~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n"
module multiplier(multplcd, multplr, start, clk, F_READY, overflow, result);
	
	input [31:0] multplcd, multplr;
	input start, clk;
	output F_READY, overflow;
	output [31:0] result;
	
	wire [31:0] wprod_1_in_after_mux;
	wire [31:0] wprod_2_in_beforeshift;
	wire [31:0] wprod_1_in, wprod_2_in;
	wire [31:0] wprod_1_out, wprod_2_out;
	

	wire [31:0] multplcd_readout;
	reg_32 multplcd_readin(.in(multplcd), .out(multplcd_readout), .write_enable(start), .clk(clk), .reset(1'b0));
	
	wire same_sign;
	dffe_ref ovf_shift_same_sign(.q(same_sign), .d((multplcd[31] & multplr[31]) | ((~multplcd[31]) & (~multplr[31]))), .clk(clk), .en(start), .clr(1'b0));
	
	wire isZero_multiplicand, isZero_multiplier;
	wire isZero_multiplicand_in, isZero_multiplier_in;
	
	nor zero_cand(isZero_multiplicand_in, multplcd[0], multplcd[1], multplcd[2], multplcd[3], multplcd[4], multplcd[5], multplcd[6], multplcd[7], multplcd[8], multplcd[9],
	 multplcd[10], multplcd[11], multplcd[12], multplcd[13], multplcd[4], multplcd[15], multplcd[16], multplcd[17], multplcd[18], multplcd[19],
	 multplcd[20], multplcd[21], multplcd[22], multplcd[23], multplcd[24], multplcd[25], multplcd[26], multplcd[27], multplcd[28], multplcd[29],
	 multplcd[30], multplcd[31]);
	 
	 nor zero_plier(isZero_multiplier_in, multplr[0], multplr[1], multplr[2], multplr[3], multplr[4], multplr[5], multplr[6], multplr[7], multplr[8], multplr[9],
	 multplr[10], multplr[11], multplr[12], multplr[13], multplr[4], multplr[15], multplr[16], multplr[17], multplr[18], multplr[19],
	 multplr[20], multplr[21], multplr[22], multplr[23], multplr[24], multplr[25], multplr[26], multplr[27], multplr[28], multplr[29],
	 multplr[30], multplr[31]);
	 
	 dffe_ref zero_dff_cand(.q(isZero_multiplicand), .d(isZero_multiplicand_in), .clk(clk), .en(start), .clr(1'b0));
	 dffe_ref zero_dff_lier(.q(isZero_multiplier), .d(isZero_multiplier_in), .clk(clk), .en(start), .clr(1'b0));
	


	mux_2to1_32bit mux_readin(.a(wprod_1_in), .b(multplr), .sel(start), .out(wprod_1_in_after_mux));
	
	reg_32 product_1(.in(wprod_1_in_after_mux), .out(wprod_1_out), .write_enable(1'b1), .clk(clk), .reset(1'b0));
	reg_32 product_2(.in(wprod_2_in), .out(wprod_2_out), .write_enable(1'b1), .clk(clk), .reset(start));
	
	wire isShift;
	
	wire signed [31:0] wmultiplcd, wmultiplcd_shifted;
	assign wmultiplcd = multplcd_readout;
	assign wmultiplcd_shifted = multplcd_readout<<1;
	
	wire overflow_shift, overflow_shift_temp;
	dffe_ref ovf_shift_dff(.q(overflow_shift), .d(1'b1), .clk(clk), .en(overflow_shift_temp), .clr(start));
	assign overflow_shift_temp = isShift & ((wmultiplcd[31] & (~wmultiplcd_shifted[31])) | ((~wmultiplcd[31]) & wmultiplcd_shifted[31]));
	

	wire [31:0] addsub_operand1_pos;

	mux_2to1_32bit mux_shift_multiplcd(.a(wmultiplcd), .b(wmultiplcd_shifted), .sel(isShift), .out(addsub_operand1_pos));
	

	wire [31:0] addsub_operand1_neg, addsub_operand1;
	wire isSub;
	assign addsub_operand1_neg = ~addsub_operand1_pos;
	mux_2to1_32bit mux_sign(.a(addsub_operand1_pos), .b(addsub_operand1_neg), .sel(isSub), .out(addsub_operand1));
	

	wire [31:0] addsub_result;
	adder addsub(.x(wprod_2_out), .y(addsub_operand1), .sub(isSub), .out(addsub_result));
	
	wire overflow_addsub, overflow_addsub_temp;
	dffe_ref ovf_addsub_dff(.q(overflow_addsub), .d(1'b1), .clk(clk), .en(overflow_addsub_temp), .clr(start));
	

	wire isUnChange;
	mux_2to1_32bit mux_change(.a(addsub_result), .b(wprod_2_out), .sel(isUnChange), .out(wprod_2_in_beforeshift));

	assign overflow_addsub_temp = (~isUnChange) & ((isSub & (((~wprod_2_out[31]) & addsub_operand1_pos[31] & addsub_result[31]) | (wprod_2_out[31] & (~addsub_operand1_pos[31]) & (~addsub_result[31])))) |
	((~isSub) & (((~wprod_2_out[31]) & (~addsub_operand1_pos[31]) & addsub_result[31]) | (wprod_2_out[31] & addsub_operand1_pos[31] & (~addsub_result[31])))));
	
	wire isZero_result;
	 nor zero_result(isZero_result, result[0], result[1], result[2], result[3], result[4], result[5], result[6], result[7], result[8], result[9],
	 result[10], result[11], result[12], result[13], result[4], result[15], result[16], result[17], result[18], result[19],
	 result[20], result[21], result[22], result[23], result[24], result[25], result[26], result[27], result[28], result[29],
	 result[30], result[31]);
	
	assign overflow = overflow_addsub | overflow_shift | (((same_sign & result[31] & F_READY) | ((~same_sign) & (~result[31]) & F_READY)) & (~isZero_multiplicand) & (~isZero_multiplier)) | (same_sign & (multplcd_readout[31]) & isZero_result & F_READY) ;
	

	wire signed [63:0] beforeshift, aftershift;
	assign beforeshift[31:0] = wprod_1_out;
	assign beforeshift[63:32] = wprod_2_in_beforeshift;
	assign aftershift = beforeshift>>>2;
	assign wprod_1_in = aftershift[31:0];
	assign wprod_2_in = aftershift[63:32];
	

	wire bit1, bit0;
	wire helper;
	dffe_ref helper_bit(.q(helper), .d(wprod_1_out[1]), .clk(clk), .en(1'b1), .clr(start));
	assign bit1 = wprod_1_out[1];
	assign bit0 = wprod_1_out[0];
	
	assign isUnChange = ((~bit1) & (~bit0) & (~helper)) | (bit1 & bit0 & helper);
	assign isSub = (bit1) & (((~bit0) & (~helper)) | ((bit0) & (~helper)) | ((~bit0) & (helper)));
	assign isShift = ((bit1) & (~bit0) & (~helper)) | ((~bit1) & (bit0) & (helper));
	

	counter_5 counter(.reset(start), .clk(clk), .F_READY(F_READY));
	assign result = wprod_1_out;
	
endmodule
module multiplier(multplcd, multplr, start, clk, F_READY, overflow, result);

	
	input [31:0] multplcd, multplr;
	input start, clk;
	output F_READY, overflow;
	output [31:0] result;
	
	wire [31:0] wprod_1_in_after_mux;
	wire [31:0] wprod_2_in_beforeshift;
	wire [31:0] wprod_1_in, wprod_2_in;
	wire [31:0] wprod_1_out, wprod_2_out;
	

	wire [31:0] multplcd_readout;
	reg_32 multplcd_readin(.in(multplcd), .out(multplcd_readout), .write_enable(start), .clk(clk), .reset(1'b0));
	
	wire same_sign;
	dffe_ref ovf_shift_same_sign(.q(same_sign), .d((multplcd[31] & multplr[31]) | ((~multplcd[31]) & (~multplr[31]))), .clk(clk), .en(start), .clr(1'b0));
	
	wire isZero_multiplicand, isZero_multiplier;
	wire isZero_multiplicand_in, isZero_multiplier_in;
	
	nor zero_cand(isZero_multiplicand_in, multplcd[0], multplcd[1], multplcd[2], multplcd[3], multplcd[4], multplcd[5], multplcd[6], multplcd[7], multplcd[8], multplcd[9],
	 multplcd[10], multplcd[11], multplcd[12], multplcd[13], multplcd[4], multplcd[15], multplcd[16], multplcd[17], multplcd[18], multplcd[19],
	 multplcd[20], multplcd[21], multplcd[22], multplcd[23], multplcd[24], multplcd[25], multplcd[26], multplcd[27], multplcd[28], multplcd[29],
	 multplcd[30], multplcd[31]);
	 
	 nor zero_plier(isZero_multiplier_in, multplr[0], multplr[1], multplr[2], multplr[3], multplr[4], multplr[5], multplr[6], multplr[7], multplr[8], multplr[9],
	 multplr[10], multplr[11], multplr[12], multplr[13], multplr[4], multplr[15], multplr[16], multplr[17], multplr[18], multplr[19],
	 multplr[20], multplr[21], multplr[22], multplr[23], multplr[24], multplr[25], multplr[26], multplr[27], multplr[28], multplr[29],
	 multplr[30], multplr[31]);
	 
	 dffe_ref zero_dff_cand(.q(isZero_multiplicand), .d(isZero_multiplicand_in), .clk(clk), .en(start), .clr(1'b0));
	 dffe_ref zero_dff_lier(.q(isZero_multiplier), .d(isZero_multiplier_in), .clk(clk), .en(start), .clr(1'b0));
	


	mux_2to1_32bit mux_readin(.a(wprod_1_in), .b(multplr), .sel(start), .out(wprod_1_in_after_mux));
	
	reg_32 product_1(.in(wprod_1_in_after_mux), .out(wprod_1_out), .write_enable(1'b1), .clk(clk), .reset(1'b0));
	reg_32 product_2(.in(wprod_2_in), .out(wprod_2_out), .write_enable(1'b1), .clk(clk), .reset(start));
	
	wire isShift;
	
	wire signed [31:0] wmultiplcd, wmultiplcd_shifted;
	assign wmultiplcd = multplcd_readout;
	assign wmultiplcd_shifted = multplcd_readout<<1;
	
	wire overflow_shift, overflow_shift_temp;
	dffe_ref ovf_shift_dff(.q(overflow_shift), .d(1'b1), .clk(clk), .en(overflow_shift_temp), .clr(start));
	assign overflow_shift_temp = isShift & ((wmultiplcd[31] & (~wmultiplcd_shifted[31])) | ((~wmultiplcd[31]) & wmultiplcd_shifted[31]));
	

	wire [31:0] addsub_operand1_pos;

	mux_2to1_32bit mux_shift_multiplcd(.a(wmultiplcd), .b(wmultiplcd_shifted), .sel(isShift), .out(addsub_operand1_pos));
	

	wire [31:0] addsub_operand1_neg, addsub_operand1;
	wire isSub;
	assign addsub_operand1_neg = ~addsub_operand1_pos;
	mux_2to1_32bit mux_sign(.a(addsub_operand1_pos), .b(addsub_operand1_neg), .sel(isSub), .out(addsub_operand1));
	

	wire [31:0] addsub_result;
	adder addsub(.x(wprod_2_out), .y(addsub_operand1), .sub(isSub), .out(addsub_result));
	
	wire overflow_addsub, overflow_addsub_temp;
	dffe_ref ovf_addsub_dff(.q(overflow_addsub), .d(1'b1), .clk(clk), .en(overflow_addsub_temp), .clr(start));
	

	wire isUnChange;
	mux_2to1_32bit mux_change(.a(addsub_result), .b(wprod_2_out), .sel(isUnChange), .out(wprod_2_in_beforeshift));

	assign overflow_addsub_temp = (~isUnChange) & ((isSub & (((~wprod_2_out[31]) & addsub_operand1_pos[31] & addsub_result[31]) | (wprod_2_out[31] & (~addsub_operand1_pos[31]) & (~addsub_result[31])))) |
	((~isSub) & (((~wprod_2_out[31]) & (~addsub_operand1_pos[31]) & addsub_result[31]) | (wprod_2_out[31] & addsub_operand1_pos[31] & (~addsub_result[31])))));
	
	wire isZero_result;
	 nor zero_result(isZero_result, result[0], result[1], result[2], result[3], result[4], result[5], result[6], result[7], result[8], result[9],
	 result[10], result[11], result[12], result[13], result[4], result[15], result[16], result[17], result[18], result[19],
	 result[20], result[21], result[22], result[23], result[24], result[25], result[26], result[27], result[28], result[29],
	 result[30], result[31]);
	
	assign overflow = overflow_addsub | overflow_shift | (((same_sign & result[31] & F_READY) | ((~same_sign) & (~result[31]) & F_READY)) & (~isZero_multiplicand) & (~isZero_multiplier)) | (same_sign & (multplcd_readout[31]) & isZero_result & F_READY) ;
	

	wire signed [63:0] beforeshift, aftershift;
	assign beforeshift[31:0] = wprod_1_out;
	assign beforeshift[63:32] = wprod_2_in_beforeshift;
	assign aftershift = beforeshift>>>2;
	assign wprod_1_in = aftershift[31:0];
	assign wprod_2_in = aftershift[63:32];
	

	wire bit1, bit0;
	wire helper;
	dffe_ref helper_bit(.q(helper), .d(wprod_1_out[1]), .clk(clk), .en(1'b1), .clr(start));
	assign bit1 = wprod_1_out[1];
	assign bit0 = wprod_1_out[0];
	
	assign isUnChange = ((~bit1) & (~bit0) & (~helper)) | (bit1 & bit0 & helper);
	assign isSub = (bit1) & (((~bit0) & (~helper)) | ((bit0) & (~helper)) | ((~bit0) & (helper)));
	assign isShift = ((bit1) & (~bit0) & (~helper)) | ((~bit1) & (bit0) & (helper));
	

	counter_5 counter(.reset(start), .clk(clk), .F_READY(F_READY));
	assign result = wprod_1_out;
	
endmodule