data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu.v
 line:26: before: "Z"
data/verilator_xmls/a80d148a-bf37-4cc8-91e1-0c080318c354.xml
module alu(input signed [31:0] x, input signed [31:0] y, input [3:0] alu_ctrl, output reg signed [31:0] result, output reg zero);
    

    

    
    always @ (alu_ctrl or x or y)
    begin
        case(alu_ctrl)
            4'b0000: result = x & y;
            4'b0001: result = x | y;
            4'b0010: result = x + y;
            4'b0110: result = x - y;
            4'b0011: result = x * y;
            4'b1000: result = x / y;
            4'b1001: result = x ^ y;
            4'b0111: if(x<y) result=1; else result = 0;        
            default: result = 32'bx;
        endcase 
        
        if(result==32'b0) zero=1; else zero=0;   
    end
endmodule
module alu(input signed [31:0] x, input signed [31:0] y, input [3:0] alu_ctrl, output reg signed [31:0] result, output reg zero);

    

    

    
    always @ (alu_ctrl or x or y)
    begin
        case(alu_ctrl)
            4'b0000: result = x & y;
            4'b0001: result = x | y;
            4'b0010: result = x + y;
            4'b0110: result = x - y;
            4'b0011: result = x * y;
            4'b1000: result = x / y;
            4'b1001: result = x ^ y;
            4'b0111: if(x<y) result=1; else result = 0;        
            default: result = 32'bx;
        endcase 
        
        if(result==32'b0) zero=1; else zero=0;   
    end
endmodule