data/full_repos/permissive/193669196/ahb_ic/rtl/ahb_ic_wrap.v
 line:34: before: "["
1: b"%Error: data/full_repos/permissive/193669196/ahb_ic/rtl/ahb_ic_wrap.v:126: Cannot find file containing module: 'ahb_ic'\nahb_ic #(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193669196/ahb_ic/rtl,data/full_repos/permissive/193669196/ahb_ic\n             data/full_repos/permissive/193669196/ahb_ic/rtl,data/full_repos/permissive/193669196/ahb_ic.v\n             data/full_repos/permissive/193669196/ahb_ic/rtl,data/full_repos/permissive/193669196/ahb_ic.sv\n             ahb_ic\n             ahb_ic.v\n             ahb_ic.sv\n             obj_dir/ahb_ic\n             obj_dir/ahb_ic.v\n             obj_dir/ahb_ic.sv\n%Error: data/full_repos/permissive/193669196/ahb_ic/rtl/ahb_ic_wrap.v:179: Cannot find file containing module: 'transmonitor_dummy'\ntransmonitor_dummy u_transmonitor_dummy_pram_inst (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193669196/ahb_ic/rtl/ahb_ic_wrap.v:209: Cannot find file containing module: 'transmonitor'\n       transmonitor #(\n       ^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module ahb_ic_wrap #(
  parameter NUM_SLAVES     = 18,
  parameter NUM_SRAMS      = 18,
  parameter NUM_MASTERS    = 16,
  parameter NUM_CORES      = 16,
  parameter NUM_APU_POLICY = 16,
  parameter NUM_DPU_POLICY = 16,
  parameter [31:0] SLAVE_BASE_MASK [NUM_SLAVES-1 :0]   = '{32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF},
  parameter [31:0] SLAVE_BASE [NUM_SLAVES-1 :0]   = '{32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h0000_0000}
  )(  

  input  wire         hclk,

  input   wire [31:0] hmaster_m[NUM_MASTERS-1 :0],
  input   wire [ 1:0] htrans_m[NUM_MASTERS-1 :0],
  input   wire [3:0]  hprot_m[NUM_MASTERS-1 :0],
  input   wire [31:0] haddr_m[NUM_MASTERS-1 :0],
  input   wire [ 2:0] hsize_m[NUM_MASTERS-1 :0],
  input   wire [31:0] hwdata_m[NUM_MASTERS-1 :0],
  input   wire        hwrite_m[NUM_MASTERS-1 :0],
  output  reg  [31:0] hrdata_m[NUM_MASTERS-1 :0],
  output  reg         hready_m[NUM_MASTERS-1 :0],
  output  reg         hresp_m[NUM_MASTERS-1 :0],

  output  reg         hsel_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] haddr_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] hmaster_s[NUM_SLAVES-1 :0],
  output  reg  [ 2:0] hsize_s[NUM_SLAVES-1 :0],
  output  reg         hwrite_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] hwdata_s[NUM_SLAVES-1 :0],
  input   wire [31:0] hrdata_s[NUM_SLAVES-1 :0],
  input   wire        hready_s[NUM_SLAVES-1 :0],
  input   wire        hresp_s[NUM_SLAVES-1 :0],

`ifndef NOTRANSMON

  input   wire [NUM_APU_POLICY-1 :0][31:0] apumid [NUM_SRAMS :0],
  input   wire [NUM_APU_POLICY-1 :0][31:0] apuaddr[NUM_SRAMS :0],
  input   wire [NUM_APU_POLICY-1 :0][31:0] apumask[NUM_SRAMS :0],
  input   wire [NUM_APU_POLICY-1 :0][31:0] apuperm[NUM_SRAMS :0],


  input   wire [NUM_DPU_POLICY-1 :0][31:0] dpumid [NUM_SRAMS :0],
  input   wire [NUM_DPU_POLICY-1 :0][31:0] dpuaddr[NUM_SRAMS :0],
  input   wire [NUM_DPU_POLICY-1 :0][31:0] dpudata[NUM_SRAMS :0],
  input   wire [NUM_DPU_POLICY-1 :0][31:0] dpumask[NUM_SRAMS :0],
  input   wire [NUM_DPU_POLICY-1 :0][31:0] dpuamask[NUM_SRAMS :0],
`endif

  input  wire         hresetn

);

wire        hsel_s_loc[NUM_SLAVES-1 :0];
wire [31:0] hmaster_s_loc[NUM_SLAVES-1 :0];
wire [31:0] haddr_s_loc[NUM_SLAVES-1 :0];
wire [ 2:0] hsize_s_loc[NUM_SLAVES-1 :0];
wire [ 3:0] hprot_s_loc[NUM_SLAVES-1 :0];
wire        hwrite_s_loc[NUM_SLAVES-1 :0];
wire [31:0] hwdata_s_loc[NUM_SLAVES-1 :0];
wire [31:0] hrdata_s_loc[NUM_SLAVES-1 :0];
wire        hready_s_loc[NUM_SLAVES-1 :0];
wire        hresp_s_loc[NUM_SLAVES-1 :0];


ahb_ic #(
  .NUM_SLAVES  (NUM_SLAVES),
  .NUM_MASTERS (NUM_MASTERS),
  .SLAVE_BASE_MASK (SLAVE_BASE_MASK),
  .SLAVE_BASE  (SLAVE_BASE)
  ) u_ahb_ic_inst (  
      .hclk      (hclk),
      .hresetn   (hresetn),
      .hmaster_m (hmaster_m),
      .htrans_m  (htrans_m),
      .hprot_m   (hprot_m),
      .haddr_m   (haddr_m),
      .hsize_m   (hsize_m),
      .hwdata_m  (hwdata_m),
      .hwrite_m  (hwrite_m),
      .hrdata_m  (hrdata_m),
      .hready_m  (hready_m),
      .hresp_m   (hresp_m),
      .hsel_s    (hsel_s_loc),
      .haddr_s   (haddr_s_loc),
      .hsize_s   (hsize_s_loc),
      .hmaster_s (hmaster_s_loc),
      .hprot_s   (hprot_s_loc),
      .hwrite_s  (hwrite_s_loc),
      .hwdata_s  (hwdata_s_loc),
      .hrdata_s  (hrdata_s_loc),
      .hready_s  (hready_s_loc),
      .hresp_s   (hresp_s_loc)
      );



















  genvar s,m;




transmonitor_dummy u_transmonitor_dummy_pram_inst (
         .hclk          (hclk),
         .hresetn       (hresetn),
         .hmaster_m     (hmaster_s_loc[0]),
         .hsel_m        (hsel_s_loc[0]),
         .haddr_m       (haddr_s_loc[0]),
         .hsize_m       (hsize_s_loc[0]),
         .hprot_m       (hprot_s_loc[0]),
         .hwdata_m      (hwdata_s_loc[0]),
         .hwrite_m      (hwrite_s_loc[0]),
         .hrdata_m      (hrdata_s_loc[0]),
         .hready_m      (hready_s_loc[0]),
         .hresp_m       (hresp_s_loc[0]),
         .hsel_s        (hsel_s[0]),
         .hmaster_s     (hmaster_s[0]),
         .haddr_s       (haddr_s[0]),
         .hsize_s       (hsize_s[0]),
         .hwdata_s      (hwdata_s[0]),
         .hwrite_s      (hwrite_s[0]),
         .hrdata_s      (hrdata_s[0]),
         .hready_s      (hready_s[0]),
         .hresp_s       (hresp_s[0])
       );

 
  generate
    for (s=1; s<=NUM_SRAMS; s=s+1) begin
    `ifdef NOTRANSMON
       transmonitor_dummy u_transmonitor_dummy_inst
    `else
       transmonitor #(
         .NUM_APU_POLICY (NUM_APU_POLICY),
         .NUM_DPU_POLICY (NUM_DPU_POLICY)
       ) u_transmonitor_inst
    `endif
        (
         .hclk          (hclk),
         .hmaster_m     (hmaster_s_loc[s]),
         .hsel_m        (hsel_s_loc[s]),
         .haddr_m       (haddr_s_loc[s]),
         .hsize_m       (hsize_s_loc[s]),
         .hprot_m       (hprot_s_loc[s]),
         .hwdata_m      (hwdata_s_loc[s]),
         .hwrite_m      (hwrite_s_loc[s]),
         .hrdata_m      (hrdata_s_loc[s]),
         .hready_m      (hready_s_loc[s]),
         .hresp_m       (hresp_s_loc[s]),
         .hsel_s        (hsel_s[s]),
         .hmaster_s     (hmaster_s[s]),
         .haddr_s       (haddr_s[s]),
         .hsize_s       (hsize_s[s]),
         .hwdata_s      (hwdata_s[s]),
         .hwrite_s      (hwrite_s[s]),
         .hrdata_s      (hrdata_s[s]),
         .hready_s      (hready_s[s]),
         .hresp_s       (hresp_s[s]),
    `ifndef NOTRANSMON
         .apumid        (apumid[s-1]),
         .apuaddr       (apuaddr[s-1]),
         .apumask       (apumask[s-1]),
         .apuperm       (apuperm[s-1]),
         .dpumid        (dpumid[s-1]),
         .dpuaddr       (dpuaddr[s-1]),
         .dpudata       (dpudata[s-1]),
         .dpumask       (dpumask[s-1]),
         .dpuamask      (dpuamask[s-1]),
    `endif
         .hresetn       (hresetn)
       );

    end
  endgenerate
 
  generate
    for (s=(NUM_SRAMS+1); s<NUM_SLAVES; s=s+1) begin
    `ifdef NOTRANSMON
       transmonitor_dummy u_transmonitor_dummy_periph_inst
    `else
       transmonitor #(
         .NUM_APU_POLICY (NUM_APU_POLICY),
         .NUM_DPU_POLICY (NUM_DPU_POLICY)
       ) u_transmonitor_peiph_inst
    `endif
        (
         .hclk          (hclk),
         .hmaster_m     (hmaster_s_loc[s]),
         .hsel_m        (hsel_s_loc[s]),
         .haddr_m       (haddr_s_loc[s]),
         .hsize_m       (hsize_s_loc[s]),
         .hprot_m       (hprot_s_loc[s]),
         .hwdata_m      (hwdata_s_loc[s]),
         .hwrite_m      (hwrite_s_loc[s]),
         .hrdata_m      (hrdata_s_loc[s]),
         .hready_m      (hready_s_loc[s]),
         .hresp_m       (hresp_s_loc[s]),
         .hsel_s        (hsel_s[s]),
         .hmaster_s     (hmaster_s[s]),
         .haddr_s       (haddr_s[s]),
         .hsize_s       (hsize_s[s]),
         .hwdata_s      (hwdata_s[s]),
         .hwrite_s      (hwrite_s[s]),
         .hrdata_s      (hrdata_s[s]),
         .hready_s      (hready_s[s]),
         .hresp_s       (hresp_s[s]),
    `ifndef NOTRANSMON
         .apumid        (apumid[s-1]),
         .apuaddr       (apuaddr[s-1]),
         .apumask       (apumask[s-1]),
         .apuperm       (apuperm[s-1]),
         .dpumid        (dpumid[s-1]),
         .dpuaddr       (dpuaddr[s-1]),
         .dpudata       (dpudata[s-1]),
         .dpumask       (dpumask[s-1]),
         .dpuamask      (dpuamask[s-1]),
    `endif
         .hresetn       (hresetn)
       );
    end
  endgenerate



endmodule
module ahb_ic_wrap #(
  parameter NUM_SLAVES     = 18,
  parameter NUM_SRAMS      = 18,
  parameter NUM_MASTERS    = 16,
  parameter NUM_CORES      = 16,
  parameter NUM_APU_POLICY = 16,
  parameter NUM_DPU_POLICY = 16,
  parameter [31:0] SLAVE_BASE_MASK [NUM_SLAVES-1 :0]   = '{32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF,
                                                           32'h0000_FFFF},
  parameter [31:0] SLAVE_BASE [NUM_SLAVES-1 :0]   = '{32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h4000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h2000_0000,
                                                      32'h0000_0000}
  )(  

  input  wire         hclk,

  input   wire [31:0] hmaster_m[NUM_MASTERS-1 :0],
  input   wire [ 1:0] htrans_m[NUM_MASTERS-1 :0],
  input   wire [3:0]  hprot_m[NUM_MASTERS-1 :0],
  input   wire [31:0] haddr_m[NUM_MASTERS-1 :0],
  input   wire [ 2:0] hsize_m[NUM_MASTERS-1 :0],
  input   wire [31:0] hwdata_m[NUM_MASTERS-1 :0],
  input   wire        hwrite_m[NUM_MASTERS-1 :0],
  output  reg  [31:0] hrdata_m[NUM_MASTERS-1 :0],
  output  reg         hready_m[NUM_MASTERS-1 :0],
  output  reg         hresp_m[NUM_MASTERS-1 :0],

  output  reg         hsel_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] haddr_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] hmaster_s[NUM_SLAVES-1 :0],
  output  reg  [ 2:0] hsize_s[NUM_SLAVES-1 :0],
  output  reg         hwrite_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] hwdata_s[NUM_SLAVES-1 :0],
  input   wire [31:0] hrdata_s[NUM_SLAVES-1 :0],
  input   wire        hready_s[NUM_SLAVES-1 :0],
  input   wire        hresp_s[NUM_SLAVES-1 :0],

`ifndef NOTRANSMON

  input   wire [NUM_APU_POLICY-1 :0][31:0] apumid [NUM_SRAMS :0],
  input   wire [NUM_APU_POLICY-1 :0][31:0] apuaddr[NUM_SRAMS :0],
  input   wire [NUM_APU_POLICY-1 :0][31:0] apumask[NUM_SRAMS :0],
  input   wire [NUM_APU_POLICY-1 :0][31:0] apuperm[NUM_SRAMS :0],


  input   wire [NUM_DPU_POLICY-1 :0][31:0] dpumid [NUM_SRAMS :0],
  input   wire [NUM_DPU_POLICY-1 :0][31:0] dpuaddr[NUM_SRAMS :0],
  input   wire [NUM_DPU_POLICY-1 :0][31:0] dpudata[NUM_SRAMS :0],
  input   wire [NUM_DPU_POLICY-1 :0][31:0] dpumask[NUM_SRAMS :0],
  input   wire [NUM_DPU_POLICY-1 :0][31:0] dpuamask[NUM_SRAMS :0],
`endif

  input  wire         hresetn

);


wire        hsel_s_loc[NUM_SLAVES-1 :0];
wire [31:0] hmaster_s_loc[NUM_SLAVES-1 :0];
wire [31:0] haddr_s_loc[NUM_SLAVES-1 :0];
wire [ 2:0] hsize_s_loc[NUM_SLAVES-1 :0];
wire [ 3:0] hprot_s_loc[NUM_SLAVES-1 :0];
wire        hwrite_s_loc[NUM_SLAVES-1 :0];
wire [31:0] hwdata_s_loc[NUM_SLAVES-1 :0];
wire [31:0] hrdata_s_loc[NUM_SLAVES-1 :0];
wire        hready_s_loc[NUM_SLAVES-1 :0];
wire        hresp_s_loc[NUM_SLAVES-1 :0];


ahb_ic #(
  .NUM_SLAVES  (NUM_SLAVES),
  .NUM_MASTERS (NUM_MASTERS),
  .SLAVE_BASE_MASK (SLAVE_BASE_MASK),
  .SLAVE_BASE  (SLAVE_BASE)
  ) u_ahb_ic_inst (  
      .hclk      (hclk),
      .hresetn   (hresetn),
      .hmaster_m (hmaster_m),
      .htrans_m  (htrans_m),
      .hprot_m   (hprot_m),
      .haddr_m   (haddr_m),
      .hsize_m   (hsize_m),
      .hwdata_m  (hwdata_m),
      .hwrite_m  (hwrite_m),
      .hrdata_m  (hrdata_m),
      .hready_m  (hready_m),
      .hresp_m   (hresp_m),
      .hsel_s    (hsel_s_loc),
      .haddr_s   (haddr_s_loc),
      .hsize_s   (hsize_s_loc),
      .hmaster_s (hmaster_s_loc),
      .hprot_s   (hprot_s_loc),
      .hwrite_s  (hwrite_s_loc),
      .hwdata_s  (hwdata_s_loc),
      .hrdata_s  (hrdata_s_loc),
      .hready_s  (hready_s_loc),
      .hresp_s   (hresp_s_loc)
      );



















  genvar s,m;




transmonitor_dummy u_transmonitor_dummy_pram_inst (
         .hclk          (hclk),
         .hresetn       (hresetn),
         .hmaster_m     (hmaster_s_loc[0]),
         .hsel_m        (hsel_s_loc[0]),
         .haddr_m       (haddr_s_loc[0]),
         .hsize_m       (hsize_s_loc[0]),
         .hprot_m       (hprot_s_loc[0]),
         .hwdata_m      (hwdata_s_loc[0]),
         .hwrite_m      (hwrite_s_loc[0]),
         .hrdata_m      (hrdata_s_loc[0]),
         .hready_m      (hready_s_loc[0]),
         .hresp_m       (hresp_s_loc[0]),
         .hsel_s        (hsel_s[0]),
         .hmaster_s     (hmaster_s[0]),
         .haddr_s       (haddr_s[0]),
         .hsize_s       (hsize_s[0]),
         .hwdata_s      (hwdata_s[0]),
         .hwrite_s      (hwrite_s[0]),
         .hrdata_s      (hrdata_s[0]),
         .hready_s      (hready_s[0]),
         .hresp_s       (hresp_s[0])
       );

 
  generate
    for (s=1; s<=NUM_SRAMS; s=s+1) begin
    `ifdef NOTRANSMON
       transmonitor_dummy u_transmonitor_dummy_inst
    `else
       transmonitor #(
         .NUM_APU_POLICY (NUM_APU_POLICY),
         .NUM_DPU_POLICY (NUM_DPU_POLICY)
       ) u_transmonitor_inst
    `endif
        (
         .hclk          (hclk),
         .hmaster_m     (hmaster_s_loc[s]),
         .hsel_m        (hsel_s_loc[s]),
         .haddr_m       (haddr_s_loc[s]),
         .hsize_m       (hsize_s_loc[s]),
         .hprot_m       (hprot_s_loc[s]),
         .hwdata_m      (hwdata_s_loc[s]),
         .hwrite_m      (hwrite_s_loc[s]),
         .hrdata_m      (hrdata_s_loc[s]),
         .hready_m      (hready_s_loc[s]),
         .hresp_m       (hresp_s_loc[s]),
         .hsel_s        (hsel_s[s]),
         .hmaster_s     (hmaster_s[s]),
         .haddr_s       (haddr_s[s]),
         .hsize_s       (hsize_s[s]),
         .hwdata_s      (hwdata_s[s]),
         .hwrite_s      (hwrite_s[s]),
         .hrdata_s      (hrdata_s[s]),
         .hready_s      (hready_s[s]),
         .hresp_s       (hresp_s[s]),
    `ifndef NOTRANSMON
         .apumid        (apumid[s-1]),
         .apuaddr       (apuaddr[s-1]),
         .apumask       (apumask[s-1]),
         .apuperm       (apuperm[s-1]),
         .dpumid        (dpumid[s-1]),
         .dpuaddr       (dpuaddr[s-1]),
         .dpudata       (dpudata[s-1]),
         .dpumask       (dpumask[s-1]),
         .dpuamask      (dpuamask[s-1]),
    `endif
         .hresetn       (hresetn)
       );

    end
  endgenerate
 
  generate
    for (s=(NUM_SRAMS+1); s<NUM_SLAVES; s=s+1) begin
    `ifdef NOTRANSMON
       transmonitor_dummy u_transmonitor_dummy_periph_inst
    `else
       transmonitor #(
         .NUM_APU_POLICY (NUM_APU_POLICY),
         .NUM_DPU_POLICY (NUM_DPU_POLICY)
       ) u_transmonitor_peiph_inst
    `endif
        (
         .hclk          (hclk),
         .hmaster_m     (hmaster_s_loc[s]),
         .hsel_m        (hsel_s_loc[s]),
         .haddr_m       (haddr_s_loc[s]),
         .hsize_m       (hsize_s_loc[s]),
         .hprot_m       (hprot_s_loc[s]),
         .hwdata_m      (hwdata_s_loc[s]),
         .hwrite_m      (hwrite_s_loc[s]),
         .hrdata_m      (hrdata_s_loc[s]),
         .hready_m      (hready_s_loc[s]),
         .hresp_m       (hresp_s_loc[s]),
         .hsel_s        (hsel_s[s]),
         .hmaster_s     (hmaster_s[s]),
         .haddr_s       (haddr_s[s]),
         .hsize_s       (hsize_s[s]),
         .hwdata_s      (hwdata_s[s]),
         .hwrite_s      (hwrite_s[s]),
         .hrdata_s      (hrdata_s[s]),
         .hready_s      (hready_s[s]),
         .hresp_s       (hresp_s[s]),
    `ifndef NOTRANSMON
         .apumid        (apumid[s-1]),
         .apuaddr       (apuaddr[s-1]),
         .apumask       (apumask[s-1]),
         .apuperm       (apuperm[s-1]),
         .dpumid        (dpumid[s-1]),
         .dpuaddr       (dpuaddr[s-1]),
         .dpudata       (dpudata[s-1]),
         .dpumask       (dpumask[s-1]),
         .dpuamask      (dpuamask[s-1]),
    `endif
         .hresetn       (hresetn)
       );
    end
  endgenerate



endmodule