data/full_repos/permissive/205769493/src/tera.v
 line:72: before: "begin"
1: b'%Error: data/full_repos/permissive/205769493/src/tera.v:64: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("dumpfile.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/205769493/src/tera.v:65: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars (0, m_tera);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205769493/src/tera.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #2 r_reset = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205769493/src/tera.v:72: Unsupported: Ignoring delay on this delayed statement.\n always #1 begin\n        ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module m_tera;


	reg r_clock = 1'b0;
	reg r_reset = 1'b1;

	wire w_clock, w_reset;

	assign w_clock = r_clock;
	assign w_reset = r_reset;




	reg r_pc_demux_channel = 1'b0;
	
	wire [7:0] w_bus_instr_mem_addr, w_bus_alu_out;
	wire w_jump_flag;

	m_program_counter pc (w_bus_instr_mem_addr, w_bus_alu_out, w_jump_flag, w_clock, w_reset);




	wire [7:0] w_bus_instr_mem_word, w_bus_data_mem_word, w_bus_data_mem_addr, w_bus_high_register_value, w_bus_low_register_value;
	wire w_data_mem_write_enable;

	m_instruction_memory instr_mem (w_bus_instr_mem_word, w_bus_instr_mem_addr);
	m_data_memory data_mem (w_bus_data_mem_word, w_bus_high_register_value, w_data_mem_write_enable, w_reset, w_clock);




	wire [7:0] w_bus_write_back_value;
	wire [3:0] w_bus_write_back_reg;
	wire w_write_back_flag;

	m_register_file regfile (w_bus_high_register_value, w_bus_low_register_value, w_bus_instr_mem_word, w_bus_write_back_value, w_bus_write_back_reg, w_write_back_flag, w_clock, w_reset);




	wire w_store_word_flag, w_store_pc_flag, w_load_word_flag, w_cf;
	
	m_instruction_logic_unit ilu (w_jump_flag, w_data_mem_write_enable, w_store_word_flag, w_store_pc_flag, w_load_word_flag, w_write_back_flag, w_bus_write_back_reg, w_bus_instr_mem_word, w_cf, w_clock);




	m_arithmetic_logic_unit alu (w_bus_alu_out, w_cf, w_bus_instr_mem_word, w_bus_high_register_value, w_bus_low_register_value, w_clock);




	wire [7:0] w_bus_demux_inter0, w_bus_mux_inter;

	m_1to2_8bit_demux store_demux (w_bus_demux_inter0, w_bus_data_mem_word, w_bus_alu_out, w_store_word_flag);
	m_2to1_8bit_mux load_mux (w_bus_mux_inter, w_bus_demux_inter0, w_bus_data_mem_word, w_load_word_flag);
	m_2to1_8bit_mux_with_add1 pc_mux (w_bus_write_back_value, w_bus_mux_inter, w_bus_instr_mem_addr, w_store_pc_flag);



	initial begin
		$dumpfile ("dumpfile.vcd");
		$dumpvars (0, m_tera);

		$display ("\nStarting program (Program Counter = 0).\n");
		#2 r_reset = 1'b0;
	end


	always #1 begin
		r_clock = ~w_clock;
	
		if (w_bus_instr_mem_addr == 8'b11111111) begin
			$display ("\nReached EOF (Program Counter = 255). Closing program.\n");
			$finish;
		end
	end
endmodule
module m_tera;



	reg r_clock = 1'b0;
	reg r_reset = 1'b1;

	wire w_clock, w_reset;

	assign w_clock = r_clock;
	assign w_reset = r_reset;




	reg r_pc_demux_channel = 1'b0;
	
	wire [7:0] w_bus_instr_mem_addr, w_bus_alu_out;
	wire w_jump_flag;

	m_program_counter pc (w_bus_instr_mem_addr, w_bus_alu_out, w_jump_flag, w_clock, w_reset);




	wire [7:0] w_bus_instr_mem_word, w_bus_data_mem_word, w_bus_data_mem_addr, w_bus_high_register_value, w_bus_low_register_value;
	wire w_data_mem_write_enable;

	m_instruction_memory instr_mem (w_bus_instr_mem_word, w_bus_instr_mem_addr);
	m_data_memory data_mem (w_bus_data_mem_word, w_bus_high_register_value, w_data_mem_write_enable, w_reset, w_clock);




	wire [7:0] w_bus_write_back_value;
	wire [3:0] w_bus_write_back_reg;
	wire w_write_back_flag;

	m_register_file regfile (w_bus_high_register_value, w_bus_low_register_value, w_bus_instr_mem_word, w_bus_write_back_value, w_bus_write_back_reg, w_write_back_flag, w_clock, w_reset);




	wire w_store_word_flag, w_store_pc_flag, w_load_word_flag, w_cf;
	
	m_instruction_logic_unit ilu (w_jump_flag, w_data_mem_write_enable, w_store_word_flag, w_store_pc_flag, w_load_word_flag, w_write_back_flag, w_bus_write_back_reg, w_bus_instr_mem_word, w_cf, w_clock);




	m_arithmetic_logic_unit alu (w_bus_alu_out, w_cf, w_bus_instr_mem_word, w_bus_high_register_value, w_bus_low_register_value, w_clock);




	wire [7:0] w_bus_demux_inter0, w_bus_mux_inter;

	m_1to2_8bit_demux store_demux (w_bus_demux_inter0, w_bus_data_mem_word, w_bus_alu_out, w_store_word_flag);
	m_2to1_8bit_mux load_mux (w_bus_mux_inter, w_bus_demux_inter0, w_bus_data_mem_word, w_load_word_flag);
	m_2to1_8bit_mux_with_add1 pc_mux (w_bus_write_back_value, w_bus_mux_inter, w_bus_instr_mem_addr, w_store_pc_flag);



	initial begin
		$dumpfile ("dumpfile.vcd");
		$dumpvars (0, m_tera);

		$display ("\nStarting program (Program Counter = 0).\n");
		#2 r_reset = 1'b0;
	end


	always #1 begin
		r_clock = ~w_clock;
	
		if (w_bus_instr_mem_addr == 8'b11111111) begin
			$display ("\nReached EOF (Program Counter = 255). Closing program.\n");
			$finish;
		end
	end
endmodule