data/full_repos/permissive/157979234/Semester III/Digital Design and Computer Organization/Session 06/pc.v
1: b'%Error: Cannot find file containing module: III/Digital\n        ... Looked in:\n             data/full_repos/permissive/157979234/Semester/III/Digital\n             data/full_repos/permissive/157979234/Semester/III/Digital.v\n             data/full_repos/permissive/157979234/Semester/III/Digital.sv\n             III/Digital\n             III/Digital.v\n             III/Digital.sv\n             obj_dir/III/Digital\n             obj_dir/III/Digital.v\n             obj_dir/III/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Organization/Session\n%Error: Cannot find file containing module: 06,data/full_repos/permissive/157979234\n%Error: Cannot find file containing module: data/full_repos/permissive/157979234/Semester\n%Error: Cannot find file containing module: 06/pc.v\n%Error: Exiting due to 8 error(s)\n'
module pc (input wire clk, reset, inc, add, sub, input wire [15:0] offset, output wire [15:0] pc);

wire [15:0] temp_o;
wire [15:0] o_addsub;
wire [15:0]	o_reg;
wire load;

or3 my_or(add,sub,inc,load);
or2 a0(offset[0],inc,temp_o[0]);
custom_and a1(offset[1],inc,temp_o[1]);
custom_and a2(offset[2],inc,temp_o[2]);
custom_and a3(offset[3],inc,temp_o[3]);
custom_and a4(offset[4],inc,temp_o[4]);
custom_and a5(offset[5],inc,temp_o[5]);
custom_and a6(offset[6],inc,temp_o[6]);
custom_and a7(offset[7],inc,temp_o[7]);
custom_and a8(offset[8],inc,temp_o[8]);
custom_and a9(offset[9],inc,temp_o[9]);
custom_and a10(offset[10],inc,temp_o[10]);
custom_and a11(offset[11],inc,temp_o[11]);
custom_and a12(offset[12],inc,temp_o[12]);
custom_and a13(offset[13],inc,temp_o[13]);
custom_and a14(offset[14],inc,temp_o[14]);
custom_and a15(offset[15],inc,temp_o[15]);
adder_16 my_adder(sub,o_reg,temp_o,o_addsub);
reg_unit my_reg(o_addsub,load,reset,clk,o_reg);

assign pc=o_reg;

endmodule
module pc (input wire clk, reset, inc, add, sub, input wire [15:0] offset, output wire [15:0] pc);


wire [15:0] temp_o;
wire [15:0] o_addsub;
wire [15:0]	o_reg;
wire load;

or3 my_or(add,sub,inc,load);
or2 a0(offset[0],inc,temp_o[0]);
custom_and a1(offset[1],inc,temp_o[1]);
custom_and a2(offset[2],inc,temp_o[2]);
custom_and a3(offset[3],inc,temp_o[3]);
custom_and a4(offset[4],inc,temp_o[4]);
custom_and a5(offset[5],inc,temp_o[5]);
custom_and a6(offset[6],inc,temp_o[6]);
custom_and a7(offset[7],inc,temp_o[7]);
custom_and a8(offset[8],inc,temp_o[8]);
custom_and a9(offset[9],inc,temp_o[9]);
custom_and a10(offset[10],inc,temp_o[10]);
custom_and a11(offset[11],inc,temp_o[11]);
custom_and a12(offset[12],inc,temp_o[12]);
custom_and a13(offset[13],inc,temp_o[13]);
custom_and a14(offset[14],inc,temp_o[14]);
custom_and a15(offset[15],inc,temp_o[15]);
adder_16 my_adder(sub,o_reg,temp_o,o_addsub);
reg_unit my_reg(o_addsub,load,reset,clk,o_reg);

assign pc=o_reg;

endmodule