data/full_repos/permissive/146246005/Register- D Flip-Flop- SR Latch/register.v
1: b'%Error: Cannot find file containing module: D\n        ... Looked in:\n             data/full_repos/permissive/146246005/Register-/D\n             data/full_repos/permissive/146246005/Register-/D.v\n             data/full_repos/permissive/146246005/Register-/D.sv\n             D\n             D.v\n             D.sv\n             obj_dir/D\n             obj_dir/D.v\n             obj_dir/D.sv\n%Error: Cannot find file containing module: Flip-Flop-\n%Error: Cannot find file containing module: SR\n%Error: Cannot find file containing module: Latch,data/full_repos/permissive/146246005\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/Register-\n%Error: Cannot find file containing module: Latch/register.v\n%Error: Exiting due to 6 error(s)\n'
module register(R, CLK, DATA, ENA, RST); 
	output [7:0] R; 
	input  [7:0] DATA; 
	input  CLK, ENA, RST; 

	wire [7:0] MO;
	wire [7:0] RN;

    MUX mux0(MO[0],R[0],DATA[0],ENA);
    dff dff0(R[0],RN[0],CLK,MO[0],RST);

    MUX mux1(MO[1],R[1],DATA[1],ENA);
    dff dff1(R[1],RN[1],CLK,MO[1],RST);

    MUX mux2(MO[2],R[2],DATA[2],ENA);
    dff dff2(R[2],RN[2],CLK,MO[2],RST);

    MUX mux3(MO[3],R[3],DATA[3],ENA);
    dff dff3(R[3],RN[3],CLK,MO[3],RST);

    MUX mux4(MO[4],R[4],DATA[4],ENA);
    dff dff4(R[4],RN[4],CLK,MO[4],RST);

    MUX mux5(MO[5],R[5],DATA[5],ENA);
    dff dff5(R[5],RN[5],CLK,MO[5],RST);

    MUX mux6(MO[6],R[6],DATA[6],ENA);
    dff dff6(R[6],RN[6],CLK,MO[6],RST);

    MUX mux7(MO[7],R[7],DATA[7],ENA);
    dff dff7(R[7],RN[7],CLK,MO[7],RST);
endmodule
module register(R, CLK, DATA, ENA, RST);
 
	output [7:0] R; 
	input  [7:0] DATA; 
	input  CLK, ENA, RST; 

	wire [7:0] MO;
	wire [7:0] RN;

    MUX mux0(MO[0],R[0],DATA[0],ENA);
    dff dff0(R[0],RN[0],CLK,MO[0],RST);

    MUX mux1(MO[1],R[1],DATA[1],ENA);
    dff dff1(R[1],RN[1],CLK,MO[1],RST);

    MUX mux2(MO[2],R[2],DATA[2],ENA);
    dff dff2(R[2],RN[2],CLK,MO[2],RST);

    MUX mux3(MO[3],R[3],DATA[3],ENA);
    dff dff3(R[3],RN[3],CLK,MO[3],RST);

    MUX mux4(MO[4],R[4],DATA[4],ENA);
    dff dff4(R[4],RN[4],CLK,MO[4],RST);

    MUX mux5(MO[5],R[5],DATA[5],ENA);
    dff dff5(R[5],RN[5],CLK,MO[5],RST);

    MUX mux6(MO[6],R[6],DATA[6],ENA);
    dff dff6(R[6],RN[6],CLK,MO[6],RST);

    MUX mux7(MO[7],R[7],DATA[7],ENA);
    dff dff7(R[7],RN[7],CLK,MO[7],RST);
endmodule