data/full_repos/permissive/154352170/NPC.v
data/verilator_xmls/3e53b517-b38d-4c94-80b2-9b7981487ae0.xml
module NPC(
    input Branch,
    input Zero,
	 input Bgezalr,
    input [1:0] Jump,
	 input [31:0] RD1,
	 input [31:0] RD2,
	 input [31:0] EXT_Out,
	 input [31:0] PC_Out, 
	 input [31:0] PC_D,
	 output [31:0] PC_Next
    );
	 
	 reg [31:0] PC;
	 assign PC_Next = PC;
	 
	 always @ (*) begin
	    
		 if (!Branch)
		    PC <= PC_Out + 4;
		 
       else if (Branch & Zero & (Jump == 2'b00))
			 PC <= PC_D + 4 + EXT_Out;
			 
		 else if(Branch & (Jump == 2'b01))
		    PC <= {PC_D[31:28], EXT_Out[27:0]};
		 
		 else if(Branch & (Jump == 2'b10))
		    PC <= RD1;
			 
		 else if(Branch & (Jump == 2'b11) & Bgezalr)
		    PC <= RD2;
		 
		 else
		    PC <= PC_Out + 4;

    end
	 
endmodule
module NPC(
    input Branch,
    input Zero,
	 input Bgezalr,
    input [1:0] Jump,
	 input [31:0] RD1,
	 input [31:0] RD2,
	 input [31:0] EXT_Out,
	 input [31:0] PC_Out, 
	 input [31:0] PC_D,
	 output [31:0] PC_Next
    );

	 
	 reg [31:0] PC;
	 assign PC_Next = PC;
	 
	 always @ (*) begin
	    
		 if (!Branch)
		    PC <= PC_Out + 4;
		 
       else if (Branch & Zero & (Jump == 2'b00))
			 PC <= PC_D + 4 + EXT_Out;
			 
		 else if(Branch & (Jump == 2'b01))
		    PC <= {PC_D[31:28], EXT_Out[27:0]};
		 
		 else if(Branch & (Jump == 2'b10))
		    PC <= RD1;
			 
		 else if(Branch & (Jump == 2'b11) & Bgezalr)
		    PC <= RD2;
		 
		 else
		    PC <= PC_Out + 4;

    end
	 
endmodule