data/full_repos/permissive/21716763/uncle_gates/tb_uncle_gates.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_uncle_gates.v:234: Unsupported: Ignoring delay on this delayed statement.\n  #(PERIOD/2) clk = 1\'b1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_uncle_gates.v:235: Unsupported: Ignoring delay on this delayed statement.\n  #(PERIOD/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_uncle_gates.v:244: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_uncle_gates.v:249: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21716763/uncle_gates/tb_uncle_gates.v:253: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/21716763/uncle_gates/tb_uncle_gates.v:258: Unsupported: wait statements\n  wait(gnt)\n  ^~~~\n%Error: data/full_repos/permissive/21716763/uncle_gates/tb_uncle_gates.v:290: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n   f = $fopen("output.txt");\n       ^~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_uncle_gates;
	
	parameter PERIOD = 10;

	parameter INPUT_PORTS = 3;
	parameter RESET_PORT = 1;
	parameter RESET_SENS = 0;



	wire y_ref;
	wire y;
	

	reg clk;
	wire [INPUT_PORTS-1:0] stm_value;
	wire rsb;
	wire gnt;

	reg rst;
	reg req;
	
	reg signal_en;
	integer line_num;
	integer error_cnt;
	

	integer f;










	th33r_ref ref_gate (
		.y(y_ref), 
		.a(stm_value[0]), 
		.b(stm_value[1]), 
		.c(stm_value[2]),
		.rsb(rsb)
	);


	th33r test_gate (
		.y(y), 
		.a(stm_value[0]), 
		.b(stm_value[1]), 
		.c(stm_value[2]),
		.rsb(rsb)
	);




	stimulus_gen 
	#(.INPUT_PORTS(INPUT_PORTS),
	.RESET_PORT(RESET_PORT),
	.RESET_SENS(RESET_SENS)
	)
	stimulus_gen (
		.clk(clk), 
		.rst(rst), 
		.req(req), 
		.stm_value(stm_value), 
		.rsb(rsb),
		.gnt(gnt)
	);
	

	always begin
		clk = 1'b0;
		#(PERIOD/2) clk = 1'b1;
		#(PERIOD/2);
	end  

	initial begin

		rst = 1;
		req = 0;


		#100;
      
		rst = 0;
		req = 0;		

		#100;
		req = 1;
		$display("<< Starting the Simulation >>");
		
		#100;
		req = 0;	
		


		wait(gnt)
		begin		
			$display("<< Finishing the Simulation >>");
			if(error_cnt == 0) begin
				$display("TEST RESULT = PASS");
			end
			else begin
				$display("TEST RESULT = FAIL and ERROR COUNT = %d", error_cnt);
			end
			$stop;
		end
	end
	

	always@(posedge clk)
	begin
		if(rst) begin
			signal_en <= 1'b0;
		end
		else begin
			if(req) begin
				signal_en <= 1'b1;
			end
			else if(gnt) begin
				signal_en <= 1'b0;
			end
		end
	end
	
	always@(posedge clk)
	begin
		if(rst) begin
			f = $fopen("output.txt");
			line_num = 0;
			error_cnt = 0;
		end
		else begin
			if(signal_en) begin

				$fdisplay(f, "Line No = %d, RSB = %b, STM_VALUE = 0b%b, Y_REF = %b, Y = %b, Error Count = %d"
				, line_num, rsb, stm_value, y_ref, y, error_cnt); 
				
				line_num <= line_num + 1;
				

				if(y_ref != y) begin
					error_cnt <= error_cnt + 1;
				end
			end
		end
	end
	
endmodule
module tb_uncle_gates;

	
	parameter PERIOD = 10;

	parameter INPUT_PORTS = 3;
	parameter RESET_PORT = 1;
	parameter RESET_SENS = 0;



	wire y_ref;
	wire y;
	

	reg clk;
	wire [INPUT_PORTS-1:0] stm_value;
	wire rsb;
	wire gnt;

	reg rst;
	reg req;
	
	reg signal_en;
	integer line_num;
	integer error_cnt;
	

	integer f;










	th33r_ref ref_gate (
		.y(y_ref), 
		.a(stm_value[0]), 
		.b(stm_value[1]), 
		.c(stm_value[2]),
		.rsb(rsb)
	);


	th33r test_gate (
		.y(y), 
		.a(stm_value[0]), 
		.b(stm_value[1]), 
		.c(stm_value[2]),
		.rsb(rsb)
	);




	stimulus_gen 
	#(.INPUT_PORTS(INPUT_PORTS),
	.RESET_PORT(RESET_PORT),
	.RESET_SENS(RESET_SENS)
	)
	stimulus_gen (
		.clk(clk), 
		.rst(rst), 
		.req(req), 
		.stm_value(stm_value), 
		.rsb(rsb),
		.gnt(gnt)
	);
	

	always begin
		clk = 1'b0;
		#(PERIOD/2) clk = 1'b1;
		#(PERIOD/2);
	end  

	initial begin

		rst = 1;
		req = 0;


		#100;
      
		rst = 0;
		req = 0;		

		#100;
		req = 1;
		$display("<< Starting the Simulation >>");
		
		#100;
		req = 0;	
		


		wait(gnt)
		begin		
			$display("<< Finishing the Simulation >>");
			if(error_cnt == 0) begin
				$display("TEST RESULT = PASS");
			end
			else begin
				$display("TEST RESULT = FAIL and ERROR COUNT = %d", error_cnt);
			end
			$stop;
		end
	end
	

	always@(posedge clk)
	begin
		if(rst) begin
			signal_en <= 1'b0;
		end
		else begin
			if(req) begin
				signal_en <= 1'b1;
			end
			else if(gnt) begin
				signal_en <= 1'b0;
			end
		end
	end
	
	always@(posedge clk)
	begin
		if(rst) begin
			f = $fopen("output.txt");
			line_num = 0;
			error_cnt = 0;
		end
		else begin
			if(signal_en) begin

				$fdisplay(f, "Line No = %d, RSB = %b, STM_VALUE = 0b%b, Y_REF = %b, Y = %b, Error Count = %d"
				, line_num, rsb, stm_value, y_ref, y, error_cnt); 
				
				line_num <= line_num + 1;
				

				if(y_ref != y) begin
					error_cnt <= error_cnt + 1;
				end
			end
		end
	end
	
endmodule