data/full_repos/permissive/10379745/hard/regfile.sv
 line:65: before: "get_rname"
1: b'%Error: data/full_repos/permissive/10379745/hard/regfile.sv:47: Cannot find file containing module: \'ffds\'\nffds  #(5)  aq1_reg(CLK, RD_ADDR_1, a1q        );\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds\n             data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds.v\n             data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds.sv\n             ffds\n             ffds.v\n             ffds.sv\n             obj_dir/ffds\n             obj_dir/ffds.v\n             obj_dir/ffds.sv\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:48: Cannot find file containing module: \'ffds\'\nffds  #(5)  aq2_reg(CLK, RD_ADDR_2, a2q        );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:49: Cannot find file containing module: \'ffds\'\nffds  #(1)  bp1_reg(CLK, bp_1_mem, bp_1_mem_q  );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:50: Cannot find file containing module: \'ffds\'\nffds  #(1)  bp2_reg(CLK, bp_2_mem, bp_2_mem_q  );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:51: Cannot find file containing module: \'ffds\'\nffds  #(1)  zr1_reg(CLK, zero_1,   zero_1q     );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:52: Cannot find file containing module: \'ffds\'\nffds  #(1)  zr2_reg(CLK, zero_2,   zero_2q     );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:53: Cannot find file containing module: \'ffds\'\nffds #(32)  bp_save(CLK, W_DATA,   bypass_save );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:55: Cannot find file containing module: \'mux2\'\nmux2 bp_mem_mux_1(bp_1_mem_q, rd1_mem, bypass_save, rd1_bp_mem);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:56: Cannot find file containing module: \'mux2\'\nmux2 bp_mem_mux_2(bp_2_mem_q, rd2_mem, bypass_save, rd2_bp_mem);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:58: Cannot find file containing module: \'mux2\'\nmux2 bp_cpu_mux_1(bp_1_cpu, rd1_bp_mem, W_DATA, rd1_bp_cpu);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:59: Cannot find file containing module: \'mux2\'\nmux2 bp_cpu_mux_2(bp_2_cpu, rd2_bp_mem, W_DATA, rd2_bp_cpu);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:61: Cannot find file containing module: \'mux2\'\nmux2   zero_mux_1(zero_1q, rd1_bp_cpu, 32\'d0, R_DATA_1);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:62: Cannot find file containing module: \'mux2\'\nmux2   zero_mux_2(zero_2q, rd2_bp_cpu, 32\'d0, R_DATA_2);\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/10379745/hard/regfile.sv:106: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'WR_ADDR_3\' generates 5 bits.\n                                                                       : ... In instance regfile\n  if(WE && WR_ADDR_3)\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 13 error(s), 1 warning(s)\n'
module rf_memory( input           CLK,
                  input    [4:0]  A1R, 
                  input    [4:0]  A2R, 
                  input    [4:0]  A3W,
                  input   [31:0]  WD,
                  input           WE,
                  output  [31:0]  RD1,
                  output  [31:0]  RD2 );

logic [31:0] rf[31:0];
logic [31:0] reg_rd1, reg_rd2;

always_ff@(posedge CLK)
  begin
  reg_rd1 <= rf[A1R];
  reg_rd2 <= rf[A2R];
  if(WE) rf[A3W] <= WD;
  end

assign RD1 = reg_rd1;
assign RD2 = reg_rd2;

endmodule
module rf_memory( input           CLK,
                  input    [4:0]  A1R, 
                  input    [4:0]  A2R, 
                  input    [4:0]  A3W,
                  input   [31:0]  WD,
                  input           WE,
                  output  [31:0]  RD1,
                  output  [31:0]  RD2 );


logic [31:0] rf[31:0];
logic [31:0] reg_rd1, reg_rd2;

always_ff@(posedge CLK)
  begin
  reg_rd1 <= rf[A1R];
  reg_rd2 <= rf[A2R];
  if(WE) rf[A3W] <= WD;
  end

assign RD1 = reg_rd1;
assign RD2 = reg_rd2;

endmodule