data/full_repos/permissive/117026779/src/VGA.v
1: b"%Error: data/full_repos/permissive/117026779/src/VGA.v:93: syntax error, unexpected '(', expecting IDENTIFIER\n    .clk(clk),\n    ^\n%Error: Exiting due to 1 error(s)\n"
module DEMO_DEBUG_VALUE_GENERATOR(
    input wire clk,
    input wire rst,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_0,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_1,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_2,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_3,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_4,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_5,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_6,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_7,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_8,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_9
);






reg [31:0] counter0 = 0;
reg [31:0] counter1 = 0;












always @(posedge clk or posedge rst) begin
    if (rst) begin

        counter0 = 0;
        counter1 = 0;
        debug_value_0 = 0;
        debug_value_1 = 0;
        debug_value_2 = 0;
        debug_value_3 = 0;
        debug_value_4 = 0;
        debug_value_5 = 0;
        debug_value_6 = 0;
        debug_value_7 = 0;
        debug_value_8 = 0;
        debug_value_9 = 0;
    end
    else begin
        counter0 = counter0 + 1;
        counter1 = counter1 + 1;
        if(counter0 == 32'd10_000_000)
        begin
            debug_value_0 = debug_value_0 - 1;
            debug_value_1 = debug_value_1 - 5;
            debug_value_2 = debug_value_2 - 10;
            debug_value_3 = debug_value_3 - 2;
            debug_value_4 = debug_value_4 - 13;
            debug_value_5 = debug_value_5 - 7;
            debug_value_6 = debug_value_6 - 3;
            counter0 = 0;
        end
        if(counter1 == 32'd50_000_000)
        begin
            debug_value_7 = debug_value_7 + 1;
            debug_value_8 = debug_value_8 + 5;
            debug_value_9 = debug_value_9 + 10;
            counter1 = 0;
        end
    end
end

endmodule
module DEMO_DEBUG_VALUE_GENERATOR(
    input wire clk,
    input wire rst,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_0,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_1,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_2,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_3,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_4,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_5,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_6,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_7,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_8,
    output reg [`VALUE_BIT_WIDTH-1:0] debug_value_9
);







reg [31:0] counter0 = 0;
reg [31:0] counter1 = 0;












always @(posedge clk or posedge rst) begin
    if (rst) begin

        counter0 = 0;
        counter1 = 0;
        debug_value_0 = 0;
        debug_value_1 = 0;
        debug_value_2 = 0;
        debug_value_3 = 0;
        debug_value_4 = 0;
        debug_value_5 = 0;
        debug_value_6 = 0;
        debug_value_7 = 0;
        debug_value_8 = 0;
        debug_value_9 = 0;
    end
    else begin
        counter0 = counter0 + 1;
        counter1 = counter1 + 1;
        if(counter0 == 32'd10_000_000)
        begin
            debug_value_0 = debug_value_0 - 1;
            debug_value_1 = debug_value_1 - 5;
            debug_value_2 = debug_value_2 - 10;
            debug_value_3 = debug_value_3 - 2;
            debug_value_4 = debug_value_4 - 13;
            debug_value_5 = debug_value_5 - 7;
            debug_value_6 = debug_value_6 - 3;
            counter0 = 0;
        end
        if(counter1 == 32'd50_000_000)
        begin
            debug_value_7 = debug_value_7 + 1;
            debug_value_8 = debug_value_8 + 5;
            debug_value_9 = debug_value_9 + 10;
            counter1 = 0;
        end
    end
end

endmodule