data/full_repos/permissive/110151336/lab_09/src/common/simulation/testbench.v
 line:58: before: "("
1: b'%Error: data/full_repos/permissive/110151336/lab_09/src/common/simulation/testbench.v:58: syntax error, unexpected \'@\'\n        repeat (4)  @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/110151336/lab_09/src/common/simulation/testbench.v:64: syntax error, unexpected \'@\'\n        repeat (Cycles)  @(posedge clk);\n                         ^\n%Error: data/full_repos/permissive/110151336/lab_09/src/common/simulation/testbench.v:71: Unsupported or unknown PLI call: $monitor\n        $monitor("value=%h", value);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/common/simulation/testbench.v:74: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module testbench;


    parameter Tt     = 20;
    parameter Cycles = 4000;


    reg         clk;
    reg         rst_n;


    wire        cs;
    wire        sck;
    wire        sdo;


    wire  [7:0] value;


    pmod_als als
    (
        .clk    ( clk   ),
        .rst_n  ( rst_n ),
        .cs     ( cs    ),
        .sck    ( sck   ),
        .sdo    ( sdo   ),
        .value  ( value )
    );



    pmod_als_stub stub
    (
        .cs     ( cs    ),
        .sck    ( sck   ),
        .sdo    ( sdo   )
    );


    initial begin
        clk = 0;
        forever clk = #(Tt/2) ~clk;
    end


    initial begin
        rst_n   = 0;
        repeat (4)  @(posedge clk);
        rst_n   = 1;
    end


    initial begin
        repeat (Cycles)  @(posedge clk);
        $display ("Timeout");
        $stop;
    end


    initial 
        $monitor("value=%h", value);

    initial 
        $dumpvars;

endmodule
module testbench;



    parameter Tt     = 20;
    parameter Cycles = 4000;


    reg         clk;
    reg         rst_n;


    wire        cs;
    wire        sck;
    wire        sdo;


    wire  [7:0] value;


    pmod_als als
    (
        .clk    ( clk   ),
        .rst_n  ( rst_n ),
        .cs     ( cs    ),
        .sck    ( sck   ),
        .sdo    ( sdo   ),
        .value  ( value )
    );



    pmod_als_stub stub
    (
        .cs     ( cs    ),
        .sck    ( sck   ),
        .sdo    ( sdo   )
    );


    initial begin
        clk = 0;
        forever clk = #(Tt/2) ~clk;
    end


    initial begin
        rst_n   = 0;
        repeat (4)  @(posedge clk);
        rst_n   = 1;
    end


    initial begin
        repeat (Cycles)  @(posedge clk);
        $display ("Timeout");
        $stop;
    end


    initial 
        $monitor("value=%h", value);

    initial 
        $dumpvars;

endmodule