data/full_repos/permissive/109846502/write_cycle.v
data/verilator_xmls/9af39029-6677-495c-b8cc-9eebda829d0e.xml
module write_cycle(
		input rst, clk,
		input wr_enable, reg_sel,
		output reg e_out, wr_finish,
		output rs_out, rw_out
    );

reg [1:0] st, nst;
localparam
idle = 2'd0,
init = 2'd1,
eout = 2'd2,
endwr = 2'd3;

always @(posedge clk, posedge rst)
begin
	if(rst)
		st <= idle;
	else
		st <= nst;
end

always @*
	case(st)
		idle: if(wr_enable) nst = init; else nst = idle;
		init: nst =eout;
		eout: nst = endwr;
		endwr: nst = idle;
endcase

always @*
begin
wr_finish = 1'b0;
	case(st)
		idle: begin e_out = 1'b0; end
		init: begin e_out = 1'b1; end
		eout: begin e_out = 1'b1; end
		endwr: begin
			e_out = 1'b0;
			wr_finish = 1'b1;
		end
endcase
end

assign rw_out = 1'b0;
assign rs_out = reg_sel;

endmodule
module write_cycle(
		input rst, clk,
		input wr_enable, reg_sel,
		output reg e_out, wr_finish,
		output rs_out, rw_out
    );


reg [1:0] st, nst;
localparam
idle = 2'd0,
init = 2'd1,
eout = 2'd2,
endwr = 2'd3;

always @(posedge clk, posedge rst)
begin
	if(rst)
		st <= idle;
	else
		st <= nst;
end

always @*
	case(st)
		idle: if(wr_enable) nst = init; else nst = idle;
		init: nst =eout;
		eout: nst = endwr;
		endwr: nst = idle;
endcase

always @*
begin
wr_finish = 1'b0;
	case(st)
		idle: begin e_out = 1'b0; end
		init: begin e_out = 1'b1; end
		eout: begin e_out = 1'b1; end
		endwr: begin
			e_out = 1'b0;
			wr_finish = 1'b1;
		end
endcase
end

assign rw_out = 1'b0;
assign rs_out = reg_sel;

endmodule