data/full_repos/permissive/141753280/Vivado/RTL/segment_controller.v
data/verilator_xmls/f8ec3fda-56d2-4701-b9b0-e4fa7b83db78.xml
module segment_controller(
    clock,
    reset,
    displayed_number,
    en_seg_n,
    LED_out
);




input               clock;
input               reset;
input       [15:0]  displayed_number;
output reg  [ 3:0]  en_seg_n;
output reg  [ 6:0]  LED_out;

reg         [ 3:0]  led_disp;
reg         [19:0]  count;
reg         [ 1:0]  seg_sel;







always @(posedge clock or posedge reset) begin
    if(reset) begin
        count   <= 'b0;
        seg_sel <= 2'b00;
    end else begin
        if (count == 250000) begin
            seg_sel <=  seg_sel + 1;
            count   <= 1;
        end else begin
            seg_sel <= seg_sel;
            count   <= count + 1;
        end
    end
end


always @(*) begin
    case(seg_sel)
    2'b00: begin
            en_seg_n <= 4'b0111;
            led_disp <= displayed_number[15:12];
    end
    2'b01: begin
            en_seg_n <= 4'b1011;
            led_disp <= displayed_number[11:8];
    end
    2'b10: begin
            en_seg_n <= 4'b1101;
            led_disp <= displayed_number[7:4];
    end
    2'b11: begin
            en_seg_n <= 4'b1110;
            led_disp <= displayed_number[3:0];
    end
    endcase
end


always @(*) begin
    case(led_disp)
        4'b0000: LED_out <= 7'b1000000;
        4'b0001: LED_out <= 7'b1111001;
        4'b0010: LED_out <= 7'b0100100;
        4'b0011: LED_out <= 7'b0110000;
        4'b0100: LED_out <= 7'b0011001;
        4'b0101: LED_out <= 7'b0010010;
        4'b0110: LED_out <= 7'b0000010;
        4'b0111: LED_out <= 7'b1111000;
        4'b1000: LED_out <= 7'b0000000;
        4'b1001: LED_out <= 7'b0010000;
        4'b1010: LED_out <= 7'b0001000;
        4'b1011: LED_out <= 7'b0000011;
        4'b1100: LED_out <= 7'b1000110;
        4'b1101: LED_out <= 7'b0100001;
        4'b1110: LED_out <= 7'b0000110;
        4'b1111: LED_out <= 7'b0001110;
        default: LED_out <= 7'b1000000;
    endcase
end

endmodule
module segment_controller(
    clock,
    reset,
    displayed_number,
    en_seg_n,
    LED_out
);





input               clock;
input               reset;
input       [15:0]  displayed_number;
output reg  [ 3:0]  en_seg_n;
output reg  [ 6:0]  LED_out;

reg         [ 3:0]  led_disp;
reg         [19:0]  count;
reg         [ 1:0]  seg_sel;







always @(posedge clock or posedge reset) begin
    if(reset) begin
        count   <= 'b0;
        seg_sel <= 2'b00;
    end else begin
        if (count == 250000) begin
            seg_sel <=  seg_sel + 1;
            count   <= 1;
        end else begin
            seg_sel <= seg_sel;
            count   <= count + 1;
        end
    end
end


always @(*) begin
    case(seg_sel)
    2'b00: begin
            en_seg_n <= 4'b0111;
            led_disp <= displayed_number[15:12];
    end
    2'b01: begin
            en_seg_n <= 4'b1011;
            led_disp <= displayed_number[11:8];
    end
    2'b10: begin
            en_seg_n <= 4'b1101;
            led_disp <= displayed_number[7:4];
    end
    2'b11: begin
            en_seg_n <= 4'b1110;
            led_disp <= displayed_number[3:0];
    end
    endcase
end


always @(*) begin
    case(led_disp)
        4'b0000: LED_out <= 7'b1000000;
        4'b0001: LED_out <= 7'b1111001;
        4'b0010: LED_out <= 7'b0100100;
        4'b0011: LED_out <= 7'b0110000;
        4'b0100: LED_out <= 7'b0011001;
        4'b0101: LED_out <= 7'b0010010;
        4'b0110: LED_out <= 7'b0000010;
        4'b0111: LED_out <= 7'b1111000;
        4'b1000: LED_out <= 7'b0000000;
        4'b1001: LED_out <= 7'b0010000;
        4'b1010: LED_out <= 7'b0001000;
        4'b1011: LED_out <= 7'b0000011;
        4'b1100: LED_out <= 7'b1000110;
        4'b1101: LED_out <= 7'b0100001;
        4'b1110: LED_out <= 7'b0000110;
        4'b1111: LED_out <= 7'b0001110;
        default: LED_out <= 7'b1000000;
    endcase
end

endmodule