data/full_repos/permissive/143278/contrib/gencrc.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/93056249-7b34-49df-9cdc-e66c61ff4549.xml
module test_gencrc;


reg [7:0]	test_packet[0:54];



parameter	CRC32_POLY = 32'h04C11DB7;
reg [ 7:0]	crc32_packet[0:255];
integer		crc32_length;
reg [31:0]	crc32_result;



parameter	CRC16_POLY = 16'h1020;
reg [ 7:0]	crc16_packet[0:255];
integer		crc16_length;
reg [15:0]	crc16_result;

`define TEST_GENCRC
`ifdef TEST_GENCRC


initial begin
   main_test;
   $finish;
end
`endif












task initialize_test_packet;
   begin
      test_packet[00] = 8'hC2;
      test_packet[01] = 8'h00;
      test_packet[02] = 8'h00;
      test_packet[03] = 8'h30;
      test_packet[04] = 8'hF2;
      test_packet[05] = 8'hCF;
      test_packet[06] = 8'h01;
      test_packet[07] = 8'hE0;
      test_packet[08] = 8'h2F;
      test_packet[09] = 8'h00;
      test_packet[10] = 8'h00;
      test_packet[11] = 8'h01;
      test_packet[12] = 8'h00;
      test_packet[13] = 8'h80;
      test_packet[14] = 8'h42;
      test_packet[15] = 8'h42;
      test_packet[16] = 8'h20;
      test_packet[17] = 8'h9E;
      test_packet[18] = 8'h00;
      test_packet[19] = 8'h1E;
      test_packet[20] = 8'h00;
      test_packet[21] = 8'h00;
      test_packet[22] = 8'h03;
      test_packet[23] = 8'h01;
      test_packet[24] = 8'h03;
      test_packet[25] = 8'h00;
      test_packet[26] = 8'h01;
      test_packet[27] = 8'h01;
      test_packet[28] = 8'h02;
      test_packet[29] = 8'h00;
      test_packet[30] = 8'h00;
      test_packet[31] = 8'h18;
      test_packet[32] = 8'hAA;
      test_packet[33] = 8'h58;
      test_packet[34] = 8'h00;
      test_packet[35] = 8'h18;
      test_packet[36] = 8'hA8;
      test_packet[37] = 8'hA0;
      test_packet[38] = 8'h02;
      test_packet[39] = 8'h03;
      test_packet[40] = 8'h03;
      test_packet[41] = 8'h08;
      test_packet[42] = 8'hFF;
      test_packet[43] = 8'hFC;
      test_packet[44] = 8'h40;
      test_packet[45] = 8'h00;
      test_packet[46] = 8'h00;
      test_packet[47] = 8'h01;
      test_packet[48] = 8'hC0;
      test_packet[49] = 8'h14;
      test_packet[50] = 8'hDD;
      test_packet[51] = 8'hBF;
      test_packet[52] = 8'hC1;
      test_packet[53] = 8'h2E;
   end
endtask











task main_test;
   integer	i, j;
   integer	num_errors;
   reg [15:0]	crc16_expected;
   reg [31:0]	crc32_expected;
   begin

   num_errors = 0;



   initialize_test_packet;





   for (i=0; i<4; i=i+1) begin
      crc16_packet[i] = test_packet[i];
   end
   crc16_expected = {test_packet[4], test_packet[5]};
   crc16_length = 4;
   gencrc16;
   if (crc16_result !== crc16_expected)
   begin
      num_errors = num_errors + 1;
      $display ("FAILED - Actual crc16_result = %h, Expected = %h",
      crc16_result, crc16_expected);
   end



   j = 0;
   for (i=6; i<50; i=i+1) begin
      crc32_packet[j] = test_packet[i];
      j = j + 1;
   end
   crc32_expected = {test_packet[50], test_packet[51], test_packet[52], test_packet[53]};
   crc32_length = 44;
   gencrc32;
   if (crc32_result !== crc32_expected)
     begin
       $display ("FAILED - Actual crc32_result = %h, Expected = %h",
       crc32_result, crc32_expected);
       num_errors = num_errors + 1;
     end

   if(num_errors == 0)
    $display("PASSED");
end

endtask























task gencrc16;
   integer	byte, bit;
   reg		msb;
   reg [7:0]	current_byte;
   reg [15:0]	temp;
   begin
      crc16_result = 16'hffff;
      for (byte = 0; byte < crc16_length; byte = byte + 1) begin
         current_byte = crc16_packet[byte];
         for (bit = 0; bit < 8; bit = bit + 1) begin
            msb = crc16_result[15];
            crc16_result = crc16_result << 1;
            if (msb != current_byte[bit]) begin
               crc16_result = crc16_result ^ CRC16_POLY;
               crc16_result[0] = 1;
            end
         end
      end




      for (bit = 0; bit < 16; bit = bit + 1)
         temp[15-bit] = crc16_result[bit];


      crc16_result = ~{temp[7:0], temp[15:8]};
   end
endtask















task gencrc32;
   integer	byte, bit;
   reg		msb;
   reg [7:0]	current_byte;
   reg [31:0]	temp;
   begin
      crc32_result = 32'hffffffff;
      for (byte = 0; byte < crc32_length; byte = byte + 1) begin
         current_byte = crc32_packet[byte];
         for (bit = 0; bit < 8; bit = bit + 1) begin
            msb = crc32_result[31];
            crc32_result = crc32_result << 1;
            if (msb != current_byte[bit]) begin
               crc32_result = crc32_result ^ CRC32_POLY;
               crc32_result[0] = 1;
            end
         end
      end




      for (bit = 0; bit < 32; bit = bit + 1)
         temp[31-bit] = crc32_result[bit];


      crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
   end
endtask

endmodule
module test_gencrc;



reg [7:0]	test_packet[0:54];



parameter	CRC32_POLY = 32'h04C11DB7;
reg [ 7:0]	crc32_packet[0:255];
integer		crc32_length;
reg [31:0]	crc32_result;



parameter	CRC16_POLY = 16'h1020;
reg [ 7:0]	crc16_packet[0:255];
integer		crc16_length;
reg [15:0]	crc16_result;

`define TEST_GENCRC
`ifdef TEST_GENCRC


initial begin
   main_test;
   $finish;
end
`endif












task initialize_test_packet;
   begin
      test_packet[00] = 8'hC2;
      test_packet[01] = 8'h00;
      test_packet[02] = 8'h00;
      test_packet[03] = 8'h30;
      test_packet[04] = 8'hF2;
      test_packet[05] = 8'hCF;
      test_packet[06] = 8'h01;
      test_packet[07] = 8'hE0;
      test_packet[08] = 8'h2F;
      test_packet[09] = 8'h00;
      test_packet[10] = 8'h00;
      test_packet[11] = 8'h01;
      test_packet[12] = 8'h00;
      test_packet[13] = 8'h80;
      test_packet[14] = 8'h42;
      test_packet[15] = 8'h42;
      test_packet[16] = 8'h20;
      test_packet[17] = 8'h9E;
      test_packet[18] = 8'h00;
      test_packet[19] = 8'h1E;
      test_packet[20] = 8'h00;
      test_packet[21] = 8'h00;
      test_packet[22] = 8'h03;
      test_packet[23] = 8'h01;
      test_packet[24] = 8'h03;
      test_packet[25] = 8'h00;
      test_packet[26] = 8'h01;
      test_packet[27] = 8'h01;
      test_packet[28] = 8'h02;
      test_packet[29] = 8'h00;
      test_packet[30] = 8'h00;
      test_packet[31] = 8'h18;
      test_packet[32] = 8'hAA;
      test_packet[33] = 8'h58;
      test_packet[34] = 8'h00;
      test_packet[35] = 8'h18;
      test_packet[36] = 8'hA8;
      test_packet[37] = 8'hA0;
      test_packet[38] = 8'h02;
      test_packet[39] = 8'h03;
      test_packet[40] = 8'h03;
      test_packet[41] = 8'h08;
      test_packet[42] = 8'hFF;
      test_packet[43] = 8'hFC;
      test_packet[44] = 8'h40;
      test_packet[45] = 8'h00;
      test_packet[46] = 8'h00;
      test_packet[47] = 8'h01;
      test_packet[48] = 8'hC0;
      test_packet[49] = 8'h14;
      test_packet[50] = 8'hDD;
      test_packet[51] = 8'hBF;
      test_packet[52] = 8'hC1;
      test_packet[53] = 8'h2E;
   end
endtask











task main_test;
   integer	i, j;
   integer	num_errors;
   reg [15:0]	crc16_expected;
   reg [31:0]	crc32_expected;
   begin

   num_errors = 0;



   initialize_test_packet;





   for (i=0; i<4; i=i+1) begin
      crc16_packet[i] = test_packet[i];
   end
   crc16_expected = {test_packet[4], test_packet[5]};
   crc16_length = 4;
   gencrc16;
   if (crc16_result !== crc16_expected)
   begin
      num_errors = num_errors + 1;
      $display ("FAILED - Actual crc16_result = %h, Expected = %h",
      crc16_result, crc16_expected);
   end



   j = 0;
   for (i=6; i<50; i=i+1) begin
      crc32_packet[j] = test_packet[i];
      j = j + 1;
   end
   crc32_expected = {test_packet[50], test_packet[51], test_packet[52], test_packet[53]};
   crc32_length = 44;
   gencrc32;
   if (crc32_result !== crc32_expected)
     begin
       $display ("FAILED - Actual crc32_result = %h, Expected = %h",
       crc32_result, crc32_expected);
       num_errors = num_errors + 1;
     end

   if(num_errors == 0)
    $display("PASSED");
end

endtask























task gencrc16;
   integer	byte, bit;
   reg		msb;
   reg [7:0]	current_byte;
   reg [15:0]	temp;
   begin
      crc16_result = 16'hffff;
      for (byte = 0; byte < crc16_length; byte = byte + 1) begin
         current_byte = crc16_packet[byte];
         for (bit = 0; bit < 8; bit = bit + 1) begin
            msb = crc16_result[15];
            crc16_result = crc16_result << 1;
            if (msb != current_byte[bit]) begin
               crc16_result = crc16_result ^ CRC16_POLY;
               crc16_result[0] = 1;
            end
         end
      end




      for (bit = 0; bit < 16; bit = bit + 1)
         temp[15-bit] = crc16_result[bit];


      crc16_result = ~{temp[7:0], temp[15:8]};
   end
endtask















task gencrc32;
   integer	byte, bit;
   reg		msb;
   reg [7:0]	current_byte;
   reg [31:0]	temp;
   begin
      crc32_result = 32'hffffffff;
      for (byte = 0; byte < crc32_length; byte = byte + 1) begin
         current_byte = crc32_packet[byte];
         for (bit = 0; bit < 8; bit = bit + 1) begin
            msb = crc32_result[31];
            crc32_result = crc32_result << 1;
            if (msb != current_byte[bit]) begin
               crc32_result = crc32_result ^ CRC32_POLY;
               crc32_result[0] = 1;
            end
         end
      end




      for (bit = 0; bit < 32; bit = bit + 1)
         temp[31-bit] = crc32_result[bit];


      crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
   end
endtask

endmodule