data/full_repos/permissive/175132042/rtl/picorv32/scripts/quartus/tabtest.v
1: b"%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/quartus/tabtest.v:75: Cannot find file containing module: 'picorv32_axi'\n picorv32_axi #(\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/rtl/picorv32/scripts/quartus,data/full_repos/permissive/175132042/picorv32_axi\n             data/full_repos/permissive/175132042/rtl/picorv32/scripts/quartus,data/full_repos/permissive/175132042/picorv32_axi.v\n             data/full_repos/permissive/175132042/rtl/picorv32/scripts/quartus,data/full_repos/permissive/175132042/picorv32_axi.sv\n             picorv32_axi\n             picorv32_axi.v\n             picorv32_axi.sv\n             obj_dir/picorv32_axi\n             obj_dir/picorv32_axi.v\n             obj_dir/picorv32_axi.sv\n%Error: Exiting due to 1 error(s)\n"
module delay4 #(
	parameter WIDTH = 1
) (
	input clk,
	input [WIDTH-1:0] in,
	output reg [WIDTH-1:0] out
);
	reg [WIDTH-1:0] q1, q2, q3;
	always @(posedge clk) begin
		q1 <= in;
		q2 <= q1;
		q3 <= q2;
		out <= q3;
	end
endmodule
module delay4 #(
	parameter WIDTH = 1
) (
	input clk,
	input [WIDTH-1:0] in,
	output reg [WIDTH-1:0] out
);

	reg [WIDTH-1:0] q1, q2, q3;
	always @(posedge clk) begin
		q1 <= in;
		q2 <= q1;
		q3 <= q2;
		out <= q3;
	end
endmodule