data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/io_top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/io_top.v:22: Cannot find include file: common.h\n`include "common.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.v\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.sv\n             common.h\n             common.h.v\n             common.h.sv\n             obj_dir/common.h\n             obj_dir/common.h.v\n             obj_dir/common.h.sv\n%Error: Exiting due to 1 error(s)\n'
module io_top
(

    clk,

    rst_sys,
    en_init_sys,

    rst,
    rst_n,
    en_init
);









input wire clk;

input wire rst_sys;
input wire en_init_sys;



output wire rst;
output wire rst_n;
output reg en_init;


















assign rst = rst_sys;
assign rst_n = !rst_sys;


always@(posedge clk)
begin
    en_init <= en_init_sys;
end



endmodule
module io_top
(

    clk,

    rst_sys,
    en_init_sys,

    rst,
    rst_n,
    en_init
);










input wire clk;

input wire rst_sys;
input wire en_init_sys;



output wire rst;
output wire rst_n;
output reg en_init;


















assign rst = rst_sys;
assign rst_n = !rst_sys;


always@(posedge clk)
begin
    en_init <= en_init_sys;
end



endmodule