data/full_repos/permissive/110151336/lab_05/src/08_half_adder/common/half_adder.v
data/verilator_xmls/3e584ecd-be95-4fbe-b520-5ee6a915e932.xml
module half_adder
(
    input  wire x, y, 
    output wire z,
    output wire carry_out
);
	assign {carry_out, z} = x + y;
endmodule
module half_adder
(
    input  wire x, y, 
    output wire z,
    output wire carry_out
);

	assign {carry_out, z} = x + y;
endmodule