data/full_repos/permissive/172912857/project_alu_basys3/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #2 tb_clk = ~tb_clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:23: Unsupported or unknown PLI call: $monitor\n$monitor(tb_x, tb_y, tb_opcode, tb_clk);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Error: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:67: Unsupported or unknown PLI call: $monitor\n  $monitor(tb_number, tb_thousands, tb_hundreds, tb_tens, tb_ones);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:69: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:71: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bcd_tb;
reg  [12:0] tb_number;
   wire [3:0] tb_thousands;
   wire [3:0] tb_hundreds;
   wire [3:0] tb_tens;
   wire [3:0] tb_ones;

bcd my_bcd(
        .number(tb_number), 
        .thousands(tb_thousands), 
        .hundreds(tb_hundreds), 
        .tens(tb_tens), 
        .ones(tb_ones)
        );
        
        
initial
begin
  $monitor(tb_number, tb_thousands, tb_hundreds, tb_tens, tb_ones);

#5
tb_number = 13'b1111111111111;
#5
tb_number = 13'b1010101010101;
        
end
endmodule
module bcd_tb;

reg  [12:0] tb_number;
   wire [3:0] tb_thousands;
   wire [3:0] tb_hundreds;
   wire [3:0] tb_tens;
   wire [3:0] tb_ones;

bcd my_bcd(
        .number(tb_number), 
        .thousands(tb_thousands), 
        .hundreds(tb_hundreds), 
        .tens(tb_tens), 
        .ones(tb_ones)
        );
        
        
initial
begin
  $monitor(tb_number, tb_thousands, tb_hundreds, tb_tens, tb_ones);

#5
tb_number = 13'b1111111111111;
#5
tb_number = 13'b1010101010101;
        
end
endmodule