data/full_repos/permissive/161275071/sdram.sv
Syntax Error
1: b'%Warning-WIDTH: data/full_repos/permissive/161275071/sdram.sv:214: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'refresh_count\' generates 14 bits.\n                                                                 : ... In instance sdram\n   if (!refresh_count) begin\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161275071/sdram.sv:267: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'new_wtbt\' generates 2 bits.\n                                                                 : ... In instance sdram\n   SDRAM_DQML  <= save_we & (new_wtbt ? ~new_wtbt[0] : ~save_addr[0]);\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/161275071/sdram.sv:268: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'new_wtbt\' generates 2 bits.\n                                                                 : ... In instance sdram\n   SDRAM_DQMH  <= save_we & (new_wtbt ? ~new_wtbt[1] :  save_addr[0]);\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/161275071/sdram.sv:285: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'new_wtbt\' generates 2 bits.\n                                                                 : ... In instance sdram\n   SDRAM_DQ    <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]};\n                           ^\n%Error: Exiting due to 4 warning(s)\n'
module sdram
(
   input             init,
   input             clk,


   inout  reg [15:0] SDRAM_DQ,
   output reg [12:0] SDRAM_A,
   output reg        SDRAM_DQML,
   output reg        SDRAM_DQMH,
   output reg  [1:0] SDRAM_BA,
   output            SDRAM_nCS,
   output            SDRAM_nWE,
   output            SDRAM_nRAS,
   output            SDRAM_nCAS,
   output            SDRAM_CKE,

   input       [1:0] wtbt,



   input      [24:0] addr,
   output reg [63:0] dout,
   input      [15:0] din,
   input             we,
   input             rd,
	input					rd_type,


	output reg			ready
);


assign SDRAM_nCS  = command[3];
assign SDRAM_nRAS = command[2];
assign SDRAM_nCAS = command[1];
assign SDRAM_nWE  = command[0];
assign SDRAM_CKE  = cke;






localparam BURST_LENGTH        = 3'b010;
localparam ACCESS_TYPE         = 1'b0;
localparam CAS_LATENCY         = 3'd3;
localparam OP_MODE             = 2'b00;
localparam NO_WRITE_BURST      = 1'b1;
localparam MODE                = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};

localparam sdram_startup_cycles= 14'd12100;
localparam cycles_per_refresh  = 14'd780;
localparam startup_refresh_max = 14'b11111111111111;


localparam CMD_INHIBIT         = 4'b1111;
localparam CMD_NOP             = 4'b0111;
localparam CMD_ACTIVE          = 4'b0011;
localparam CMD_READ            = 4'b0101;
localparam CMD_WRITE           = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE       = 4'b0010;
localparam CMD_AUTO_REFRESH    = 4'b0001;
localparam CMD_LOAD_MODE       = 4'b0000;

reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles;
reg  [3:0] command = CMD_INHIBIT;
reg        cke     = 0;
reg [24:0] save_addr;



typedef enum
{
	STATE_STARTUP,
	STATE_OPEN_1, STATE_OPEN_2,
	STATE_WRITE,
	STATE_READ,
	STATE_IDLE,	  STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3,
	STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7,
	STATE_IDLE_8
} state_t;

always @(posedge clk) begin
	reg old_we, old_rd;
	reg [CAS_LATENCY+3:0] data_ready_delay;

	reg [15:0] new_data;
	reg  [1:0] new_wtbt;
	reg        new_we;
	reg        new_rd;
	reg		  new_rd_type;
	reg        save_we = 1;

	state_t state = STATE_STARTUP;

	command <= CMD_NOP;
	refresh_count <= refresh_count+1'b1;

	data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY+3:1]};

	case (data_ready_delay)

		7'b0001000: begin


			

			if (~new_rd_type) ready <= 1;
			dout[63:48] <= SDRAM_DQ;
		end
		7'b0000100: begin
			dout[47:32] <= SDRAM_DQ;
		end
		7'b0000010: begin
			dout[31:16] <= SDRAM_DQ;
		end
		7'b0000001: begin
			if (new_rd_type)
			begin

				dout[15:0] <= SDRAM_DQ;
				ready <= 1;
			end
		end
		default:;
	endcase

	case (state)
		STATE_STARTUP: begin


















			cke        <= 1;
			SDRAM_DQ   <= 16'bZZZZZZZZZZZZZZZZ;
			SDRAM_DQML <= 1;
			SDRAM_DQMH <= 1;
			SDRAM_A    <= 0;
			SDRAM_BA   <= 0;


			if(refresh_count == startup_refresh_max-31) begin

				command     <= CMD_PRECHARGE;
				SDRAM_A[10] <= 1;
				SDRAM_BA    <= 2'b00;
			end else if (refresh_count == startup_refresh_max-23) begin

				command     <= CMD_AUTO_REFRESH;
			end else if (refresh_count == startup_refresh_max-15) 
				command     <= CMD_AUTO_REFRESH;
			else if (refresh_count == startup_refresh_max-7) begin

				command     <= CMD_LOAD_MODE;
				SDRAM_A     <= MODE;
			end






			if (!refresh_count) begin
				state   <= STATE_IDLE;


				ready <= 1;
				refresh_count <= 0;
			end
		end

		STATE_IDLE_8: state <= STATE_IDLE_7;
		STATE_IDLE_7: state <= STATE_IDLE_6;
		STATE_IDLE_6: state <= STATE_IDLE_5;
		STATE_IDLE_5: state <= STATE_IDLE_4;
		STATE_IDLE_4: state <= STATE_IDLE_3;
		STATE_IDLE_3: state <= STATE_IDLE_2;
		STATE_IDLE_2: state <= STATE_IDLE_1;
		STATE_IDLE_1: begin
			SDRAM_DQ   <= 16'bZZZZZZZZZZZZZZZZ;
			state      <= STATE_IDLE;

			if (refresh_count > cycles_per_refresh) begin




				state    <= STATE_IDLE_8;
				command  <= CMD_AUTO_REFRESH;
				refresh_count <= refresh_count - cycles_per_refresh + 1'd1;
			end
		end

		STATE_IDLE: begin
			if (refresh_count > (cycles_per_refresh << 1)) begin

				state <= STATE_IDLE_1;
			end else if (new_rd | new_we) begin

				new_we   <= 0;
				new_rd   <= 0;
				save_addr<= addr;
				save_we  <= new_we;
				state    <= STATE_OPEN_1;
				command  <= CMD_ACTIVE;
				SDRAM_A  <= addr[22:10];
				SDRAM_BA <= addr[24:23];
			end
		end


		STATE_OPEN_1: state <= STATE_OPEN_2;
		STATE_OPEN_2: begin
			SDRAM_A     <= {4'b0010, save_addr[9:1]};

			SDRAM_DQML  <= save_we & (new_wtbt ? ~new_wtbt[0] : ~save_addr[0]);
			SDRAM_DQMH  <= save_we & (new_wtbt ? ~new_wtbt[1] :  save_addr[0]);
			state       <= save_we ? STATE_WRITE : STATE_READ;
		end

		STATE_READ: begin

			state       <= new_rd_type ? STATE_IDLE_7 : STATE_IDLE_4;
			command     <= CMD_READ;
			SDRAM_DQ    <= 16'bZZZZZZZZZZZZZZZZ;


			data_ready_delay[CAS_LATENCY+3] <= 1;
		end

		STATE_WRITE: begin
			state       <= STATE_IDLE_5;
			command     <= CMD_WRITE;
			SDRAM_DQ    <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]};

			ready <= 1;
		end
	endcase

	if (init) begin
		state <= STATE_STARTUP;
		refresh_count <= startup_refresh_max - sdram_startup_cycles;
	end

	old_we <= we;
	if (we & ~old_we) begin


		{ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt};
	end

	old_rd <= rd;
	if (rd & ~old_rd) begin


		if (ready & ~save_we & (save_addr[24:1] == addr[24:1]))
			save_addr <= addr;
		else
			{ready, new_rd, new_rd_type} <= {1'b0, 1'b1, rd_type};

	end
end

endmodule
module sdram
(
   input             init,
   input             clk,


   inout  reg [15:0] SDRAM_DQ,
   output reg [12:0] SDRAM_A,
   output reg        SDRAM_DQML,
   output reg        SDRAM_DQMH,
   output reg  [1:0] SDRAM_BA,
   output            SDRAM_nCS,
   output            SDRAM_nWE,
   output            SDRAM_nRAS,
   output            SDRAM_nCAS,
   output            SDRAM_CKE,

   input       [1:0] wtbt,



   input      [24:0] addr,
   output reg [63:0] dout,
   input      [15:0] din,
   input             we,
   input             rd,
	input					rd_type,


	output reg			ready
);



assign SDRAM_nCS  = command[3];
assign SDRAM_nRAS = command[2];
assign SDRAM_nCAS = command[1];
assign SDRAM_nWE  = command[0];
assign SDRAM_CKE  = cke;






localparam BURST_LENGTH        = 3'b010;
localparam ACCESS_TYPE         = 1'b0;
localparam CAS_LATENCY         = 3'd3;
localparam OP_MODE             = 2'b00;
localparam NO_WRITE_BURST      = 1'b1;
localparam MODE                = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};

localparam sdram_startup_cycles= 14'd12100;
localparam cycles_per_refresh  = 14'd780;
localparam startup_refresh_max = 14'b11111111111111;


localparam CMD_INHIBIT         = 4'b1111;
localparam CMD_NOP             = 4'b0111;
localparam CMD_ACTIVE          = 4'b0011;
localparam CMD_READ            = 4'b0101;
localparam CMD_WRITE           = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE       = 4'b0010;
localparam CMD_AUTO_REFRESH    = 4'b0001;
localparam CMD_LOAD_MODE       = 4'b0000;

reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles;
reg  [3:0] command = CMD_INHIBIT;
reg        cke     = 0;
reg [24:0] save_addr;



typedef enum
{
	STATE_STARTUP,
	STATE_OPEN_1, STATE_OPEN_2,
	STATE_WRITE,
	STATE_READ,
	STATE_IDLE,	  STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3,
	STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7,
	STATE_IDLE_8
} state_t;

always @(posedge clk) begin
	reg old_we, old_rd;
	reg [CAS_LATENCY+3:0] data_ready_delay;

	reg [15:0] new_data;
	reg  [1:0] new_wtbt;
	reg        new_we;
	reg        new_rd;
	reg		  new_rd_type;
	reg        save_we = 1;

	state_t state = STATE_STARTUP;

	command <= CMD_NOP;
	refresh_count <= refresh_count+1'b1;

	data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY+3:1]};

	case (data_ready_delay)

		7'b0001000: begin


			

			if (~new_rd_type) ready <= 1;
			dout[63:48] <= SDRAM_DQ;
		end
		7'b0000100: begin
			dout[47:32] <= SDRAM_DQ;
		end
		7'b0000010: begin
			dout[31:16] <= SDRAM_DQ;
		end
		7'b0000001: begin
			if (new_rd_type)
			begin

				dout[15:0] <= SDRAM_DQ;
				ready <= 1;
			end
		end
		default:;
	endcase

	case (state)
		STATE_STARTUP: begin


















			cke        <= 1;
			SDRAM_DQ   <= 16'bZZZZZZZZZZZZZZZZ;
			SDRAM_DQML <= 1;
			SDRAM_DQMH <= 1;
			SDRAM_A    <= 0;
			SDRAM_BA   <= 0;


			if(refresh_count == startup_refresh_max-31) begin

				command     <= CMD_PRECHARGE;
				SDRAM_A[10] <= 1;
				SDRAM_BA    <= 2'b00;
			end else if (refresh_count == startup_refresh_max-23) begin

				command     <= CMD_AUTO_REFRESH;
			end else if (refresh_count == startup_refresh_max-15) 
				command     <= CMD_AUTO_REFRESH;
			else if (refresh_count == startup_refresh_max-7) begin

				command     <= CMD_LOAD_MODE;
				SDRAM_A     <= MODE;
			end






			if (!refresh_count) begin
				state   <= STATE_IDLE;


				ready <= 1;
				refresh_count <= 0;
			end
		end

		STATE_IDLE_8: state <= STATE_IDLE_7;
		STATE_IDLE_7: state <= STATE_IDLE_6;
		STATE_IDLE_6: state <= STATE_IDLE_5;
		STATE_IDLE_5: state <= STATE_IDLE_4;
		STATE_IDLE_4: state <= STATE_IDLE_3;
		STATE_IDLE_3: state <= STATE_IDLE_2;
		STATE_IDLE_2: state <= STATE_IDLE_1;
		STATE_IDLE_1: begin
			SDRAM_DQ   <= 16'bZZZZZZZZZZZZZZZZ;
			state      <= STATE_IDLE;

			if (refresh_count > cycles_per_refresh) begin




				state    <= STATE_IDLE_8;
				command  <= CMD_AUTO_REFRESH;
				refresh_count <= refresh_count - cycles_per_refresh + 1'd1;
			end
		end

		STATE_IDLE: begin
			if (refresh_count > (cycles_per_refresh << 1)) begin

				state <= STATE_IDLE_1;
			end else if (new_rd | new_we) begin

				new_we   <= 0;
				new_rd   <= 0;
				save_addr<= addr;
				save_we  <= new_we;
				state    <= STATE_OPEN_1;
				command  <= CMD_ACTIVE;
				SDRAM_A  <= addr[22:10];
				SDRAM_BA <= addr[24:23];
			end
		end


		STATE_OPEN_1: state <= STATE_OPEN_2;
		STATE_OPEN_2: begin
			SDRAM_A     <= {4'b0010, save_addr[9:1]};

			SDRAM_DQML  <= save_we & (new_wtbt ? ~new_wtbt[0] : ~save_addr[0]);
			SDRAM_DQMH  <= save_we & (new_wtbt ? ~new_wtbt[1] :  save_addr[0]);
			state       <= save_we ? STATE_WRITE : STATE_READ;
		end

		STATE_READ: begin

			state       <= new_rd_type ? STATE_IDLE_7 : STATE_IDLE_4;
			command     <= CMD_READ;
			SDRAM_DQ    <= 16'bZZZZZZZZZZZZZZZZ;


			data_ready_delay[CAS_LATENCY+3] <= 1;
		end

		STATE_WRITE: begin
			state       <= STATE_IDLE_5;
			command     <= CMD_WRITE;
			SDRAM_DQ    <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]};

			ready <= 1;
		end
	endcase

	if (init) begin
		state <= STATE_STARTUP;
		refresh_count <= startup_refresh_max - sdram_startup_cycles;
	end

	old_we <= we;
	if (we & ~old_we) begin


		{ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt};
	end

	old_rd <= rd;
	if (rd & ~old_rd) begin


		if (ready & ~save_we & (save_addr[24:1] == addr[24:1]))
			save_addr <= addr;
		else
			{ready, new_rd, new_rd_type} <= {1'b0, 1'b1, rd_type};

	end
end

endmodule