data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/nBit_mLength_shiftRegister.sv
 line:32: before: "DATA_WIDTH"
1: b"%Error: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/nBit_mLength_shiftRegister.sv:71: Cannot find file containing module: 'shiftReg'\n      shiftReg # ( DATA_WIDTH, MAX_FANOUT ) PIPELINE_REG (\n      ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/shiftReg\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/shiftReg.v\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/shiftReg.sv\n             shiftReg\n             shiftReg.v\n             shiftReg.sv\n             obj_dir/shiftReg\n             obj_dir/shiftReg.v\n             obj_dir/shiftReg.sv\n%Error: Exiting due to 1 error(s)\n"
module nBit_mLength_shiftRegister #(
  DATA_WIDTH = 16,
  DELAY_LENGTH = 1,
  MAX_FANOUT = 256
) (
  clk,
  rst,
  ena,
  data_in,
  data_out
);


  input   wire                        clk;
  input   wire                        rst;
  input   wire                        ena;
  input   wire    [DATA_WIDTH-1:0]    data_in;

  output  wire    [DATA_WIDTH-1:0]    data_out;



  wire [DATA_WIDTH-1:0] shift_mem [0:DELAY_LENGTH+1];



  generate
    if(DELAY_LENGTH <= 0) begin
      assign data_out = data_in;
    end else begin
      assign data_out     = shift_mem[DELAY_LENGTH];
      assign shift_mem[0] = data_in;
    end
  endgenerate



  genvar i;
  generate
    for (i=0; i<DELAY_LENGTH; i=i+1) begin
      shiftReg # ( DATA_WIDTH, MAX_FANOUT ) PIPELINE_REG (
        .clk        (clk),
        .rst        (rst),
        .ena        (ena),
        .in_data    (shift_mem[i]),
        .out_data   (shift_mem[i+1])
      );
    end
  endgenerate


endmodule
module nBit_mLength_shiftRegister #(
  DATA_WIDTH = 16,
  DELAY_LENGTH = 1,
  MAX_FANOUT = 256
) (
  clk,
  rst,
  ena,
  data_in,
  data_out
);



  input   wire                        clk;
  input   wire                        rst;
  input   wire                        ena;
  input   wire    [DATA_WIDTH-1:0]    data_in;

  output  wire    [DATA_WIDTH-1:0]    data_out;



  wire [DATA_WIDTH-1:0] shift_mem [0:DELAY_LENGTH+1];



  generate
    if(DELAY_LENGTH <= 0) begin
      assign data_out = data_in;
    end else begin
      assign data_out     = shift_mem[DELAY_LENGTH];
      assign shift_mem[0] = data_in;
    end
  endgenerate



  genvar i;
  generate
    for (i=0; i<DELAY_LENGTH; i=i+1) begin
      shiftReg # ( DATA_WIDTH, MAX_FANOUT ) PIPELINE_REG (
        .clk        (clk),
        .rst        (rst),
        .ena        (ena),
        .in_data    (shift_mem[i]),
        .out_data   (shift_mem[i+1])
      );
    end
  endgenerate


endmodule