data/full_repos/permissive/157005262/verilog/uart_hello.v
None: at end of input
1: b'%Error: data/full_repos/permissive/157005262/verilog/uart_hello.v:1: Cannot find include file: fpga-tools/components/uart.v\n`include "fpga-tools/components/uart.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v.sv\n             fpga-tools/components/uart.v\n             fpga-tools/components/uart.v.v\n             fpga-tools/components/uart.v.sv\n             obj_dir/fpga-tools/components/uart.v\n             obj_dir/fpga-tools/components/uart.v.v\n             obj_dir/fpga-tools/components/uart.v.sv\n%Error: Exiting due to 1 error(s)\n'
module top(input wire  CLK,
           input wire  RS232_Rx_TTL,
           output wire RS232_Tx_TTL,
           output wire LED4);

  parameter baud_rate = 9600;

  wire       reset = 0;
  wire        transmit;
  wire [7:0]  tx_byte;
  wire       received;
  wire [7:0] rx_byte;
  wire       is_receiving;
  wire       is_transmitting;
  wire       recv_error;

  uart #(.baud_rate(9600), .sys_clk_freq(12000000))
  uart0(.clk(CLK),
        .rst(reset),
        .rx(RS232_Tx_TTL),
        .tx(RS232_Tx_TTL),
        .transmit(transmit),
        .tx_byte(tx_byte),
        .received(received),
        .rx_byte(rx_byte),
        .is_receiving(is_receiving),
        .is_transmitting(is_transmitting),
        .recv_error(recv_error)
        );

  uart_node un(.clk(CLK),
               .is_receiving(is_receiving),
               .is_transmitting(is_transmitting),
               .transmit(transmit),
               .tx_byte(tx_byte),
               .received(received),
               .rx_byte(rx_byte));

  assign LED4 = (is_transmitting);
endmodule
module top(input wire  CLK,
           input wire  RS232_Rx_TTL,
           output wire RS232_Tx_TTL,
           output wire LED4);


  parameter baud_rate = 9600;

  wire       reset = 0;
  wire        transmit;
  wire [7:0]  tx_byte;
  wire       received;
  wire [7:0] rx_byte;
  wire       is_receiving;
  wire       is_transmitting;
  wire       recv_error;

  uart #(.baud_rate(9600), .sys_clk_freq(12000000))
  uart0(.clk(CLK),
        .rst(reset),
        .rx(RS232_Tx_TTL),
        .tx(RS232_Tx_TTL),
        .transmit(transmit),
        .tx_byte(tx_byte),
        .received(received),
        .rx_byte(rx_byte),
        .is_receiving(is_receiving),
        .is_transmitting(is_transmitting),
        .recv_error(recv_error)
        );

  uart_node un(.clk(CLK),
               .is_receiving(is_receiving),
               .is_transmitting(is_transmitting),
               .transmit(transmit),
               .tx_byte(tx_byte),
               .received(received),
               .rx_byte(rx_byte));

  assign LED4 = (is_transmitting);
endmodule