data/full_repos/permissive/159555381/dfff.v
 line:38: before: ","
1: b'%Error: data/full_repos/permissive/159555381/dfff.v:27: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dff.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/159555381/dfff.v:28: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, wb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159555381/dfff.v:36: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/159555381/dfff.v:38: Unsupported or unknown PLI call: $monitor\n  $monitor($time,,,"clk: %d, d : %d, q: %d res = %d\\n", clk, d, q, res);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/159555381/dfff.v:38: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  $monitor($time,,,"clk: %d, d : %d, q: %d res = %d\\n", clk, d, q, res);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/dfff.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #02 d = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/dfff.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #02 res = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/dfff.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #02 d = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/dfff.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #04 $finish;\n  ^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module wb ;
	reg clk, d, res, pr;
	wire q;
	DFF df(q, res, pr, d, clk);
	initial begin
		$dumpfile("dff.vcd");
		$dumpvars(0, wb);
		clk = 0'b0;
		pr = 1'b0;
		res = 1'b1;
		d = 1'b0;
		
		
	end
	always #1 clk = ~clk;
	initial begin
		$monitor($time,,,"clk: %d, d : %d, q: %d res = %d\n", clk, d, q, res);
		#02 d = 1'b1;
		#02 res = 1'b0;
		#02 d = 1'b1;
		#04 $finish;
	end
endmodule
module wb ;

	reg clk, d, res, pr;
	wire q;
	DFF df(q, res, pr, d, clk);
	initial begin
		$dumpfile("dff.vcd");
		$dumpvars(0, wb);
		clk = 0'b0;
		pr = 1'b0;
		res = 1'b1;
		d = 1'b0;
		
		
	end
	always #1 clk = ~clk;
	initial begin
		$monitor($time,,,"clk: %d, d : %d, q: %d res = %d\n", clk, d, q, res);
		#02 d = 1'b1;
		#02 res = 1'b0;
		#02 d = 1'b1;
		#04 $finish;
	end
endmodule