data/full_repos/permissive/124803629/src/Pipeline_CPU/UART.v
1: b'%Warning-WIDTH: data/full_repos/permissive/124803629/src/Pipeline_CPU/UART.v:55: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                               : ... In instance UART.UART_Receiver_1\n      rx_data[cnt_catch]<=uart_rx;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module UART_Sender(tx_data, tx_en, sysclk, tx_status, uart_tx, reset);

input [7:0] tx_data;
input tx_en, sysclk, reset;
output reg tx_status, uart_tx;

reg [3:0] cnt;
reg [9:0] tmp_data;
reg [12:0] brcnt;

always @(posedge sysclk or negedge reset)
begin
	if (~reset) begin
		tx_status <= 1'b1;
		uart_tx <= 1'b1;
		cnt <= 4'd0;
		end
	else begin
		if(tx_status) begin
			uart_tx <= 1'b1;
			cnt <= 4'd0;
			brcnt <= 13'd5208;
			if(tx_en) begin
				tmp_data[0] <= 1'b0;
				tmp_data[8:1] <= tx_data;
				tmp_data[9] <= 1'b1;
				tx_status <= 1'b0;
				end
			end
		else begin
			if(brcnt == 13'd5208) begin
				brcnt <= 13'd0;
				if (cnt==4'd10) begin
					cnt <= 4'd0;
					tx_status <= 1'b1;
					end
				else
					uart_tx <= tmp_data[cnt];
					cnt <= cnt + 1;
			end
			else
				brcnt <= brcnt + 12'd1;
		end
	end
end

endmodule
module UART_Sender(tx_data, tx_en, sysclk, tx_status, uart_tx, reset);


input [7:0] tx_data;
input tx_en, sysclk, reset;
output reg tx_status, uart_tx;

reg [3:0] cnt;
reg [9:0] tmp_data;
reg [12:0] brcnt;

always @(posedge sysclk or negedge reset)
begin
	if (~reset) begin
		tx_status <= 1'b1;
		uart_tx <= 1'b1;
		cnt <= 4'd0;
		end
	else begin
		if(tx_status) begin
			uart_tx <= 1'b1;
			cnt <= 4'd0;
			brcnt <= 13'd5208;
			if(tx_en) begin
				tmp_data[0] <= 1'b0;
				tmp_data[8:1] <= tx_data;
				tmp_data[9] <= 1'b1;
				tx_status <= 1'b0;
				end
			end
		else begin
			if(brcnt == 13'd5208) begin
				brcnt <= 13'd0;
				if (cnt==4'd10) begin
					cnt <= 4'd0;
					tx_status <= 1'b1;
					end
				else
					uart_tx <= tmp_data[cnt];
					cnt <= cnt + 1;
			end
			else
				brcnt <= brcnt + 12'd1;
		end
	end
end

endmodule