data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v
 line:29: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:16: Unsupported: Ignoring delay on this delayed statement.\n#00 clk <= 1\'b0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:17: Unsupported: Ignoring delay on this delayed statement.\nforever #50 clk <= ~ clk ;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:22: Unsupported: Ignoring delay on this delayed statement.\n#00 rwb <= 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:23: Unsupported: Ignoring delay on this delayed statement.\nforever #100 rwb <= ~ rwb ;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:31: Unsupported: Ignoring delay on this delayed statement.\n     #200 adrb = adrb + 8\'d1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:32: Unsupported: Ignoring delay on this delayed statement.\n     #200 adrb = adrb + 8\'d1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:33: Unsupported: Ignoring delay on this delayed statement.\n     #200 adrb = adrb + 8\'d1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:34: Unsupported: Ignoring delay on this delayed statement.\n     #200 adrb = adrb + 8\'d1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:35: Unsupported: Ignoring delay on this delayed statement.\n     #200 adrb = adrb + 8\'d1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:36: Unsupported: Ignoring delay on this delayed statement.\n     #200 adrb = adrb + 8\'d1;\n     ^\n%Error: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:42: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("ram_64B.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:43: Unsupported or unknown PLI call: $dumpvars\n$dumpvars;\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab5_RAM_Memory/ram_64B.v:46: Unsupported: Ignoring delay on this delayed statement.\ninitial #12800 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_ram_64B();

reg clk,rwb;
reg [5:0]adrb;
wire [7:0]dout;
wire [7:0]din;
reg [7:0] memory[0:63];

ram_64B uut (dout,din,clk,rwb,adrb);
two_comp utt (din,dout);

initial
begin
#00 clk <= 1'b0;
forever #50 clk <= ~ clk ;
end

initial
begin
#00 rwb <= 1'b1;
forever #100 rwb <= ~ rwb ;
end

initial
begin 
  adrb = 0;
  repeat( 64 ) 
  begin 
     #200 adrb = adrb + 8'd1;
     #200 adrb = adrb + 8'd1;
     #200 adrb = adrb + 8'd1;
     #200 adrb = adrb + 8'd1;
     #200 adrb = adrb + 8'd1;
     #200 adrb = adrb + 8'd1;
  end 
end 

initial
begin
$dumpfile("ram_64B.vcd");
$dumpvars;
end

initial #12800 $finish;

endmodule
module tb_ram_64B();


reg clk,rwb;
reg [5:0]adrb;
wire [7:0]dout;
wire [7:0]din;
reg [7:0] memory[0:63];

ram_64B uut (dout,din,clk,rwb,adrb);
two_comp utt (din,dout);

initial
begin
#00 clk <= 1'b0;
forever #50 clk <= ~ clk ;
end

initial
begin
#00 rwb <= 1'b1;
forever #100 rwb <= ~ rwb ;
end

initial
begin 
  adrb = 0;
  repeat( 64 ) 
  begin 
     #200 adrb = adrb + 8'd1;
     #200 adrb = adrb + 8'd1;
     #200 adrb = adrb + 8'd1;
     #200 adrb = adrb + 8'd1;
     #200 adrb = adrb + 8'd1;
     #200 adrb = adrb + 8'd1;
  end 
end 

initial
begin
$dumpfile("ram_64B.vcd");
$dumpvars;
end

initial #12800 $finish;

endmodule