data/full_repos/permissive/214620165/rtl/core/riscv_pre_decoder.sv
data/verilator_xmls/dbc1bcef-ac00-43d4-9784-1aa97e8b1f1f.xml
module riscv_pre_decoder
(
  input  logic [31:0] instr_i,
  output logic [31:0] instr_o
);


 assign     instr_o = instr_i;


endmodule
module riscv_pre_decoder
(
  input  logic [31:0] instr_i,
  output logic [31:0] instr_o
);



 assign     instr_o = instr_i;


endmodule