data/full_repos/permissive/143278/ivltests/ca_force.v
 line:29: before: "ca"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ca_force.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ca_force.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/ca_force.v:29: Unsupported: Verilog 1995 force\n    force ca = 1\'b0;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ca_force.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ca_force.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/ca_force.v:43: Unsupported: Verilog 1995 force\n    force ca = 1\'b1;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ca_force.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass;
  reg in;
  wire ca;

  assign ca = in;

  initial begin
    pass = 1'b1;
    if (ca !== 1'bx || in !== 1'bx) begin
      $display("Failed T0 check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    in = 1'b0;
    #1;
    if (ca !== 1'b0 || in !== 1'b0) begin
      $display("Failed 0 check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    in = 1'b1;
    #1;
    if (ca !== 1'b1 || in !== 1'b1) begin
      $display("Failed 1 check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    force ca = 1'b0;
    #1;
    if (ca !== 1'b0 || in !== 1'b1) begin
      $display("Failed force 0 check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    in = 1'bx;
    #1;
    if (ca !== 1'b0 || in !== 1'bx) begin
      $display("Failed change a check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    force ca = 1'b1;
    #1;
    if (ca !== 1'b1 || in !== 1'bx) begin
      $display("Failed force 1 check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  reg in;
  wire ca;

  assign ca = in;

  initial begin
    pass = 1'b1;
    if (ca !== 1'bx || in !== 1'bx) begin
      $display("Failed T0 check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    in = 1'b0;
    #1;
    if (ca !== 1'b0 || in !== 1'b0) begin
      $display("Failed 0 check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    in = 1'b1;
    #1;
    if (ca !== 1'b1 || in !== 1'b1) begin
      $display("Failed 1 check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    force ca = 1'b0;
    #1;
    if (ca !== 1'b0 || in !== 1'b1) begin
      $display("Failed force 0 check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    in = 1'bx;
    #1;
    if (ca !== 1'b0 || in !== 1'bx) begin
      $display("Failed change a check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    force ca = 1'b1;
    #1;
    if (ca !== 1'b1 || in !== 1'bx) begin
      $display("Failed force 1 check, in %b, ca %b", in, ca);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule