data/full_repos/permissive/189158787/div/posit_div.v
Syntax Error
1: b'%Warning-MULTITOP: data/full_repos/permissive/189158787/div/posit_div.v:205: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'posit_div\'\nmodule posit_div(in1, in2, start, out, inf, zero, done);\n       ^~~~~~~~~\n                                                                           : ... Top module \'add_1\'\nmodule add_1 (a,mant_ovf,c);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:327: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 or 5 bits.\n                                                                        : ... In instance posit_div.uut_de1.xinst_k.l1\n    else if (N & (N-1))\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:327: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 bits.\n                                                                        : ... In instance posit_div.uut_de1.xinst_k.l1.genblk2.genblk2.h\n    else if (N & (N-1))\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:192: Operator SUB expects 9 bits on the RHS, but RHS\'s VARREF \'bin\' generates 1 bits.\n                                                                        : ... In instance posit_div.uut_div_e\nassign c = a - b - bin;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:60: Operator NEGATE expects 6 bits on the LHS, but LHS\'s VARREF \'regime1\' generates 4 bits.\n                                                                       : ... In instance posit_div\nwire [Bs+1:0] r1 = rc1 ? {2\'b0,regime1} : -regime1;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:61: Operator NEGATE expects 6 bits on the LHS, but LHS\'s VARREF \'regime2\' generates 4 bits.\n                                                                       : ... In instance posit_div\nwire [Bs+1:0] r2 = rc2 ? {2\'b0,regime2} : -regime2;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:117: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                        : ... In instance posit_div\nDSR_right_N_S #(.N(3*N+3), .S(Bs+1)) dsr2 (.a({tmp_o,{N{1\'b0}}}), .b(r_o[Bs] ? {Bs{1\'b1}} : r_o), .c(tmp1_o));\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:210: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'mant_ovf\' generates 1 bits.\n                                                                        : ... In instance add_1\nassign c = a + mant_ovf;\n             ^\n%Error: Exiting due to 8 warning(s)\n'
module add_1 (a,mant_ovf,c);
parameter N=10;
input [N:0] a;
input mant_ovf;
output [N:0] c;
assign c = a + mant_ovf;
endmodule
module add_1 (a,mant_ovf,c);

parameter N=10;
input [N:0] a;
input mant_ovf;
output [N:0] c;
assign c = a + mant_ovf;
endmodule