data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/MUX4.v
data/verilator_xmls/a49145be-ea92-4575-b8af-481c9ac28af0.xml
module MUX4 #(parameter WIDTH=8)
    (
    input [WIDTH-1:0] in0,
    input [WIDTH-1:0] in1,
    input [WIDTH-1:0] in2,
    input [WIDTH-1:0] in3,
    input [1:0] s,
    output reg [WIDTH-1:0] out
    );
    
    always@(*)
    begin
        case(s)
        2'b00:out<=in0;
        2'b01:out<=in1;
        2'b10:out<=in2;
        2'b11:out<=in3;
        endcase
    end
    
endmodule
module MUX4 #(parameter WIDTH=8)
    (
    input [WIDTH-1:0] in0,
    input [WIDTH-1:0] in1,
    input [WIDTH-1:0] in2,
    input [WIDTH-1:0] in3,
    input [1:0] s,
    output reg [WIDTH-1:0] out
    );

    
    always@(*)
    begin
        case(s)
        2'b00:out<=in0;
        2'b01:out<=in1;
        2'b10:out<=in2;
        2'b11:out<=in3;
        endcase
    end
    
endmodule