data/full_repos/permissive/147790758/sum.v
 line:9: before: "("
data/verilator_xmls/d78049fd-75d9-443d-b37a-7d40985c6d22.xml
module full_adder

	(input a,
	input b,
	input c_in,
	output c_out,
	output sum);
	
	wire s0,s1,s2;
	
xor (s0,a,b);
and (s1,c_in,s0);
and (s2,a,b);
xor (sum,s0,c_in);
xor (c_out,s1,s2);

endmodule
module full_adder

	(input a,
	input b,
	input c_in,
	output c_out,
	output sum);

	
	wire s0,s1,s2;
	
xor (s0,a,b);
and (s1,c_in,s0);
and (s2,a,b);
xor (sum,s0,c_in);
xor (c_out,s1,s2);

endmodule