data/full_repos/permissive/173670949/ws2812/bitcontroller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/173670949/ws2812/bitcontroller.v:75: Bit extraction of var[23:0] requires 5 bit index, not 8 bits.\n                                                                              : ... In instance BitController\n                    if (Indata[Bit_Counter])\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-UNSIGNED: data/full_repos/permissive/173670949/ws2812/bitcontroller.v:76: Comparison is constant due to unsigned arithmetic\n                                                                                 : ... In instance BitController\n                        Ws2812Out <= (Clk_Counter < T1H) ? 1 : 0;\n                                                  ^\n%Warning-UNSIGNED: data/full_repos/permissive/173670949/ws2812/bitcontroller.v:78: Comparison is constant due to unsigned arithmetic\n                                                                                 : ... In instance BitController\n                        Ws2812Out <= (Clk_Counter < T0H) ? 1 : 0;\n                                                  ^\n%Warning-CMPCONST: data/full_repos/permissive/173670949/ws2812/bitcontroller.v:80: Comparison is constant due to limited range\n                                                                                 : ... In instance BitController\n                    if (Clk_Counter > (T1H + T1L)) begin\n                                    ^\n%Error: Exiting due to 4 warning(s)\n'
module BitController (
    input                 Clk,
    input  [BITWIDTH-1:0] Indata,
    input                 Reset,
    output                WS2812OUT,
    output                DONE
);

    parameter F_CLK = 12_000_000;
    parameter BITWIDTH = 24;


    parameter T0H    = 350 * F_CLK / 10**9;
    parameter T0L    = 800 * F_CLK / 10**9;
    parameter T1H    = 700 * F_CLK / 10**9;
    parameter T1L    = 600 * F_CLK / 10**9;
    parameter TRESET =  60 * F_CLK / 10**6;

    parameter STATE_IDLE  = 2'b00;
    parameter STATE_DATA  = 2'b01;
    parameter STATE_LATCH = 2'b10;
    parameter STATE_DONE  = 2'b11;

    initial begin
        $display("F_CLK %d", F_CLK);
        $display("T0H   %d", T0H);
        $display("T0L   %d", T0L);
        $display("T1H   %d", T1H);
        $display("T1L   %d", T1L);
    end

    reg [ 1:0] State       = STATE_DATA;
    reg        Done        = 1;
    reg        Ws2812Out   = 0;
    reg [31:0] Clk_Counter = 0;
    reg [ 7:0] Bit_Counter = 0;

    assign DONE      = Done;
    assign WS2812OUT = Ws2812Out;

    always @(posedge Clk) begin
        if (Reset) begin
            Ws2812Out   <= 0;
            Clk_Counter <= 0;
            Bit_Counter <= 0;
            Done        <= 0;
            State       <= STATE_DATA;
        end else begin
            case (State)
                STATE_IDLE: begin
                    Ws2812Out   <= 0;
                    Clk_Counter <= 0;
                    Done  <= 0;
                end

                STATE_DATA: begin
                    Clk_Counter <= Clk_Counter + 1;

                    if (Indata[Bit_Counter])
                        Ws2812Out <= (Clk_Counter < T1H) ? 1 : 0;
                    else
                        Ws2812Out <= (Clk_Counter < T0H) ? 1 : 0;

                    if (Clk_Counter > (T1H + T1L)) begin
                        Clk_Counter <= 0;
                        Bit_Counter <= Bit_Counter + 1;
                    end else if (Bit_Counter >= BITWIDTH) begin
                        State       <= STATE_LATCH;
                        Ws2812Out   <= 0;
                        Bit_Counter <= 0;
                    end
                end

                STATE_LATCH: begin
                    Ws2812Out <= 0;
                    Clk_Counter <= Clk_Counter + 1;
                    if (Clk_Counter > TRESET) begin
                        Clk_Counter <= 0;
                        State <= STATE_DONE;
                    end
                end

                STATE_DONE: begin
                    State <= STATE_IDLE;
                    Done  <= 1;
                    Clk_Counter <= 0;
                    Bit_Counter <= 0;
                end
                default: begin
                    State <= STATE_IDLE;
                    Done  <= 1;
                    Clk_Counter <= 0;
                    Bit_Counter <= 0;
                end
            endcase
        end
    end
endmodule
module BitController (
    input                 Clk,
    input  [BITWIDTH-1:0] Indata,
    input                 Reset,
    output                WS2812OUT,
    output                DONE
);


    parameter F_CLK = 12_000_000;
    parameter BITWIDTH = 24;


    parameter T0H    = 350 * F_CLK / 10**9;
    parameter T0L    = 800 * F_CLK / 10**9;
    parameter T1H    = 700 * F_CLK / 10**9;
    parameter T1L    = 600 * F_CLK / 10**9;
    parameter TRESET =  60 * F_CLK / 10**6;

    parameter STATE_IDLE  = 2'b00;
    parameter STATE_DATA  = 2'b01;
    parameter STATE_LATCH = 2'b10;
    parameter STATE_DONE  = 2'b11;

    initial begin
        $display("F_CLK %d", F_CLK);
        $display("T0H   %d", T0H);
        $display("T0L   %d", T0L);
        $display("T1H   %d", T1H);
        $display("T1L   %d", T1L);
    end

    reg [ 1:0] State       = STATE_DATA;
    reg        Done        = 1;
    reg        Ws2812Out   = 0;
    reg [31:0] Clk_Counter = 0;
    reg [ 7:0] Bit_Counter = 0;

    assign DONE      = Done;
    assign WS2812OUT = Ws2812Out;

    always @(posedge Clk) begin
        if (Reset) begin
            Ws2812Out   <= 0;
            Clk_Counter <= 0;
            Bit_Counter <= 0;
            Done        <= 0;
            State       <= STATE_DATA;
        end else begin
            case (State)
                STATE_IDLE: begin
                    Ws2812Out   <= 0;
                    Clk_Counter <= 0;
                    Done  <= 0;
                end

                STATE_DATA: begin
                    Clk_Counter <= Clk_Counter + 1;

                    if (Indata[Bit_Counter])
                        Ws2812Out <= (Clk_Counter < T1H) ? 1 : 0;
                    else
                        Ws2812Out <= (Clk_Counter < T0H) ? 1 : 0;

                    if (Clk_Counter > (T1H + T1L)) begin
                        Clk_Counter <= 0;
                        Bit_Counter <= Bit_Counter + 1;
                    end else if (Bit_Counter >= BITWIDTH) begin
                        State       <= STATE_LATCH;
                        Ws2812Out   <= 0;
                        Bit_Counter <= 0;
                    end
                end

                STATE_LATCH: begin
                    Ws2812Out <= 0;
                    Clk_Counter <= Clk_Counter + 1;
                    if (Clk_Counter > TRESET) begin
                        Clk_Counter <= 0;
                        State <= STATE_DONE;
                    end
                end

                STATE_DONE: begin
                    State <= STATE_IDLE;
                    Done  <= 1;
                    Clk_Counter <= 0;
                    Bit_Counter <= 0;
                end
                default: begin
                    State <= STATE_IDLE;
                    Done  <= 1;
                    Clk_Counter <= 0;
                    Bit_Counter <= 0;
                end
            endcase
        end
    end
endmodule