data/full_repos/permissive/202237519/verilog/ripple_carry_adder/half_adder.v
data/verilator_xmls/62a408fa-8700-4644-af4f-9f9ad7580105.xml
module half_adder(out0,out1,in0,in1);

input in1, in0;
output out1, out0;

xor xor0(out0,in1,in0);
and and0(out1,in1,in0);

endmodule
module half_adder(out0,out1,in0,in1);


input in1, in0;
output out1, out0;

xor xor0(out0,in1,in0);
and and0(out1,in1,in0);

endmodule