data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
1: b'%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v:83: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v:85: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v:100: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\nparameter dw = `OR1200_OPERAND_WIDTH;\n               ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter dw = `OR1200_OPERAND_WIDTH;\n                                    ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v:101: Define or directive not defined: \'`OR1200_ICINDX\'\nparameter aw = `OR1200_ICINDX;\n               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v:101: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter aw = `OR1200_ICINDX;\n                             ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v:153: syntax error, unexpected \'.\'\n .clk(clk),\n ^\n%Error: Exiting due to 7 error(s)\n'
module or1200_ic_ram(

	clk, rst, 

`ifdef OR1200_BIST

	mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif


	addr, en, we, datain, dataout
);

parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;




input 				clk;
input				rst;
input	[aw-1:0]		addr;
input				en;
input	[3:0]			we;
input	[dw-1:0]		datain;
output	[dw-1:0]		dataout;

`ifdef OR1200_BIST



input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif

`ifdef OR1200_NO_IC




assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif

`else




`ifdef OR1200_IC_1W_512B
or1200_spram_128x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
`endif
`ifdef OR1200_BIST

	.mbist_si_i(mbist_si_i),
	.mbist_so_o(mbist_so_o),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.clk(clk),
	.rst(rst),
	.ce(en),
	.we(we[0]),
	.oe(1'b1),
	.addr(addr),
	.di(datain),
	.doq(dataout)
);

`endif

endmodule
module or1200_ic_ram(

	clk, rst, 

`ifdef OR1200_BIST

	mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif


	addr, en, we, datain, dataout
);


parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;




input 				clk;
input				rst;
input	[aw-1:0]		addr;
input				en;
input	[3:0]			we;
input	[dw-1:0]		datain;
output	[dw-1:0]		dataout;

`ifdef OR1200_BIST



input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif

`ifdef OR1200_NO_IC




assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif

`else




`ifdef OR1200_IC_1W_512B
or1200_spram_128x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
`endif
`ifdef OR1200_BIST

	.mbist_si_i(mbist_si_i),
	.mbist_so_o(mbist_so_o),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.clk(clk),
	.rst(rst),
	.ce(en),
	.we(we[0]),
	.oe(1'b1),
	.addr(addr),
	.di(datain),
	.doq(dataout)
);

`endif

endmodule