data/full_repos/permissive/189158922/verilog_src/b64_b32.v
 line:93: before: "*"
1: b'%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/b64_b32.v:327: Operator NEQ expects 2 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance top.fifo64\n  assign \\$4  = level != (* src = "nmigen/lib/fifo.py:145" *) 1\'h0;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/b64_b32.v:112: Operator NEQ expects 3 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance top.fifo32\n  assign \\$4  = level != (* src = "nmigen/lib/fifo.py:145" *) 1\'h0;\n                      ^~\n%Error: Exiting due to 2 warning(s)\n'
module top(data_in, i_busy, rst, clk, valid_out, o_busy, data_out, valid_in);
  wire \$10 ;
  wire \$12 ;
  wire \$14 ;
  wire \$16 ;
  wire \$18 ;
  wire \$2 ;
  wire \$20 ;
  wire \$22 ;
  wire \$24 ;
  wire \$26 ;
  wire \$28 ;
  wire \$30 ;
  wire \$32 ;
  wire \$4 ;
  wire \$6 ;
  wire \$8 ;
  (* src = "b64_b32.py:105" *)
  reg [31:0] \$next\buff ;
  (* src = "b64_b32.py:38" *)
  reg [31:0] \$next\data_out ;
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [31:0] \$next\fifo32_din ;
  (* src = "nmigen/lib/fifo.py:71" *)
  reg \$next\fifo32_re ;
  (* src = "nmigen/lib/fifo.py:139" *)
  reg \$next\fifo32_replace ;
  (* src = "nmigen/lib/fifo.py:67" *)
  reg \$next\fifo32_we ;
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [63:0] \$next\fifo64_din ;
  (* src = "nmigen/lib/fifo.py:71" *)
  reg \$next\fifo64_re ;
  (* src = "nmigen/lib/fifo.py:139" *)
  reg \$next\fifo64_replace ;
  (* src = "nmigen/lib/fifo.py:67" *)
  reg \$next\fifo64_we ;
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] \$next\fsm_state ;
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg \$next\fsm_state$1 ;
  (* src = "b64_b32.py:44" *)
  reg \$next\o_busy ;
  (* src = "b64_b32.py:68" *)
  reg [63:0] \$next\reg ;
  (* src = "b64_b32.py:42" *)
  reg \$next\valid_out ;
  (* init = 32'd0 *)
  (* src = "b64_b32.py:105" *)
  reg [31:0] buff = 32'd0;
  (* src = "nmigen/hdl/mem.py:160" *)
  input clk;
  (* src = "b64_b32.py:35" *)
  input [63:0] data_in;
  (* src = "b64_b32.py:38" *)
  output [31:0] data_out;
  (* init = 32'd0 *)
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [31:0] fifo32_din = 32'd0;
  (* src = "nmigen/lib/fifo.py:69" *)
  wire [31:0] fifo32_dout;
  (* src = "nmigen/lib/fifo.py:71" *)
  wire fifo32_re;
  (* src = "nmigen/lib/fifo.py:70" *)
  wire fifo32_readable;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:139" *)
  reg fifo32_replace = 1'h0;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:67" *)
  reg fifo32_we = 1'h0;
  (* src = "nmigen/lib/fifo.py:66" *)
  wire fifo32_writable;
  (* init = 64'h0000000000000000 *)
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [63:0] fifo64_din = 64'h0000000000000000;
  (* src = "nmigen/lib/fifo.py:69" *)
  wire [63:0] fifo64_dout;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:71" *)
  reg fifo64_re = 1'h0;
  (* src = "nmigen/lib/fifo.py:70" *)
  wire fifo64_readable;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:139" *)
  reg fifo64_replace = 1'h0;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:67" *)
  reg fifo64_we = 1'h0;
  (* src = "nmigen/lib/fifo.py:66" *)
  wire fifo64_writable;
  (* init = 2'h0 *)
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] fsm_state = 2'h0;
  (* init = 1'h0 *)
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg \fsm_state$1  = 1'h0;
  (* src = "b64_b32.py:45" *)
  input i_busy;
  (* init = 1'h0 *)
  (* src = "b64_b32.py:44" *)
  output o_busy;
  reg o_busy = 1'h0;
  (* init = 64'h0000000000000000 *)
  (* src = "b64_b32.py:68" *)
  reg [63:0] \reg  = 64'h0000000000000000;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "b64_b32.py:41" *)
  input valid_in;
  (* src = "b64_b32.py:42" *)
  output valid_out;
  assign \$10  = fifo64_readable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$12  = \$8  & (* src = "b64_b32.py:111" *) \$10 ;
  assign \$14  = fifo32_writable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$16  = fifo64_readable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$18  = \$14  & (* src = "b64_b32.py:111" *) \$16 ;
  assign \$20  = fifo32_writable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$22  = fifo64_readable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$24  = \$20  & (* src = "b64_b32.py:111" *) \$22 ;
  assign \$26  = fifo32_writable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$28  = fifo64_readable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$2  = fifo32_writable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$30  = \$26  & (* src = "b64_b32.py:111" *) \$28 ;
  assign \$32  = i_busy == (* src = "b64_b32.py:131" *) 1'h0;
  assign \$4  = fifo64_readable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$6  = \$2  & (* src = "b64_b32.py:111" *) \$4 ;
  assign \$8  = fifo32_writable == (* src = "b64_b32.py:111" *) 1'h1;
  always @(posedge clk)
      \fsm_state$1  <= \$next\fsm_state$1 ;
  always @(posedge clk)
      fifo64_we <= \$next\fifo64_we ;
  always @(posedge clk)
      fifo64_replace <= \$next\fifo64_replace ;
  always @(posedge clk)
      fifo32_replace <= \$next\fifo32_replace ;
  always @(posedge clk)
      fifo64_re <= \$next\fifo64_re ;
  always @(posedge clk)
      fifo32_we <= \$next\fifo32_we ;
  always @(posedge clk)
      buff <= \$next\buff ;
  always @(posedge clk)
      fifo32_din <= \$next\fifo32_din ;
  always @(posedge clk)
      \reg  <= \$next\reg ;
  always @(posedge clk)
      fifo64_din <= \$next\fifo64_din ;
  always @(posedge clk)
      fsm_state <= \$next\fsm_state ;
  always @(posedge clk)
      o_busy <= \$next\o_busy ;
  fifo32 fifo32 (
    .clk(clk),
    .din(fifo32_din),
    .dout(fifo32_dout),
    .re(fifo32_re),
    .readable(fifo32_readable),
    .replace(fifo32_replace),
    .rst(rst),
    .we(fifo32_we),
    .writable(fifo32_writable)
  );
  fifo64 fifo64 (
    .clk(clk),
    .din(fifo64_din),
    .dout(fifo64_dout),
    .re(fifo64_re),
    .readable(fifo64_readable),
    .replace(fifo64_replace),
    .rst(rst),
    .we(fifo64_we),
    .writable(fifo64_writable)
  );
  always @* begin
    \$next\fifo32_replace  = fifo32_replace;
    \$next\fifo32_replace  = 1'h0;
    casez (rst)
      1'h1:
          \$next\fifo32_replace  = 1'h0;
    endcase
  end
  always @* begin
    \$next\fifo64_replace  = fifo64_replace;
    \$next\fifo64_replace  = 1'h0;
    casez (rst)
      1'h1:
          \$next\fifo64_replace  = 1'h0;
    endcase
  end
  always @* begin
    \$next\fifo64_re  = fifo64_re;
    casez (\fsm_state$1 )
      1'h0:
          casez ({ fifo32_writable, \$24  })
            2'bz1:
                \$next\fifo64_re  = 1'h1;
          endcase
      1'h1:
          \$next\fifo64_re  = 1'h0;
    endcase
    casez (rst)
      1'h1:
          \$next\fifo64_re  = 1'h0;
    endcase
  end
  always @* begin
    \$next\fsm_state$1  = \fsm_state$1 ;
    casez (\fsm_state$1 )
      1'h0:
          casez ({ fifo32_writable, \$30  })
            2'bz1:
                \$next\fsm_state$1  = 1'h1;
          endcase
      1'h1:
          casez (fifo32_writable)
            1'h1:
                \$next\fsm_state$1  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fsm_state$1  = 1'h0;
    endcase
  end
  always @* begin
    \$next\valid_out  = 1'h0;
    \$next\valid_out  = fifo32_readable;
  end
  always @* begin
    \$next\data_out  = 32'd0;
    \$next\data_out  = fifo32_dout;
  end
  always @* begin
    \$next\fifo32_re  = 1'h0;
    \$next\fifo32_re  = \$32 ;
  end
  always @* begin
    \$next\fifo64_we  = fifo64_we;
    casez (fsm_state)
      2'h0:
          \$next\fifo64_we  = 1'h0;
      2'h1:
          casez (valid_in)
            1'h1:
                casez (fifo64_writable)
                  1'h1:
                      \$next\fifo64_we  = 1'h1;
                endcase
          endcase
      2'h2:
          casez (fifo64_writable)
            1'h1:
                \$next\fifo64_we  = 1'h1;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fifo64_we  = 1'h0;
    endcase
  end
  always @* begin
    \$next\o_busy  = o_busy;
    casez (fsm_state)
      2'h0:
          \$next\o_busy  = 1'h0;
      2'h1:
          casez (valid_in)
            1'h1:
                casez (fifo64_writable)
                  1'h1:
                      \$next\o_busy  = 1'h1;
                  1'hz:
                      \$next\o_busy  = 1'h1;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\o_busy  = 1'h0;
    endcase
  end
  always @* begin
    \$next\fsm_state  = fsm_state;
    casez (fsm_state)
      2'h0:
          \$next\fsm_state  = 2'h1;
      2'h1:
          casez (valid_in)
            1'h1:
                casez (fifo64_writable)
                  1'h1:
                      \$next\fsm_state  = 2'h0;
                  1'hz:
                      \$next\fsm_state  = 2'h2;
                endcase
          endcase
      2'h2:
          casez (fifo64_writable)
            1'h1:
                \$next\fsm_state  = 2'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fsm_state  = 2'h0;
    endcase
  end
  always @* begin
    \$next\fifo64_din  = fifo64_din;
    casez (fsm_state)
      2'h1:
          casez (valid_in)
            1'h1:
                casez (fifo64_writable)
                  1'h1:
                      \$next\fifo64_din  = data_in;
                endcase
          endcase
      2'h2:
          casez (fifo64_writable)
            1'h1:
                \$next\fifo64_din  = \reg ;
          endcase
    endcase
  end
  always @* begin
    \$next\reg  = \reg ;
    casez (fsm_state)
      2'h1:
          casez (valid_in)
            1'h1:
                casez (fifo64_writable)
                  1'h1:
;
                  1'hz:
                      \$next\reg  = data_in;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\reg  = 64'h0000000000000000;
    endcase
  end
  always @* begin
    \$next\fifo32_din  = fifo32_din;
    casez (\fsm_state$1 )
      1'h0:
          casez ({ fifo32_writable, \$6  })
            2'bz1:
                \$next\fifo32_din  = fifo64_dout[63:32];
          endcase
      1'h1:
          casez (fifo32_writable)
            1'h1:
                \$next\fifo32_din  = buff;
          endcase
    endcase
  end
  always @* begin
    \$next\buff  = buff;
    casez (\fsm_state$1 )
      1'h0:
          casez ({ fifo32_writable, \$12  })
            2'bz1:
                \$next\buff  = fifo64_dout[31:0];
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\buff  = 32'd0;
    endcase
  end
  always @* begin
    \$next\fifo32_we  = fifo32_we;
    casez (\fsm_state$1 )
      1'h0:
          casez ({ fifo32_writable, \$18  })
            2'bz1:
                \$next\fifo32_we  = 1'h1;
            2'b1z:
                \$next\fifo32_we  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fifo32_we  = 1'h0;
    endcase
  end
  assign fifo32_re = \$next\fifo32_re ;
  assign data_out = \$next\data_out ;
  assign valid_out = \$next\valid_out ;
endmodule
module top(data_in, i_busy, rst, clk, valid_out, o_busy, data_out, valid_in);

  wire \$10 ;
  wire \$12 ;
  wire \$14 ;
  wire \$16 ;
  wire \$18 ;
  wire \$2 ;
  wire \$20 ;
  wire \$22 ;
  wire \$24 ;
  wire \$26 ;
  wire \$28 ;
  wire \$30 ;
  wire \$32 ;
  wire \$4 ;
  wire \$6 ;
  wire \$8 ;
  (* src = "b64_b32.py:105" *)
  reg [31:0] \$next\buff ;
  (* src = "b64_b32.py:38" *)
  reg [31:0] \$next\data_out ;
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [31:0] \$next\fifo32_din ;
  (* src = "nmigen/lib/fifo.py:71" *)
  reg \$next\fifo32_re ;
  (* src = "nmigen/lib/fifo.py:139" *)
  reg \$next\fifo32_replace ;
  (* src = "nmigen/lib/fifo.py:67" *)
  reg \$next\fifo32_we ;
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [63:0] \$next\fifo64_din ;
  (* src = "nmigen/lib/fifo.py:71" *)
  reg \$next\fifo64_re ;
  (* src = "nmigen/lib/fifo.py:139" *)
  reg \$next\fifo64_replace ;
  (* src = "nmigen/lib/fifo.py:67" *)
  reg \$next\fifo64_we ;
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] \$next\fsm_state ;
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg \$next\fsm_state$1 ;
  (* src = "b64_b32.py:44" *)
  reg \$next\o_busy ;
  (* src = "b64_b32.py:68" *)
  reg [63:0] \$next\reg ;
  (* src = "b64_b32.py:42" *)
  reg \$next\valid_out ;
  (* init = 32'd0 *)
  (* src = "b64_b32.py:105" *)
  reg [31:0] buff = 32'd0;
  (* src = "nmigen/hdl/mem.py:160" *)
  input clk;
  (* src = "b64_b32.py:35" *)
  input [63:0] data_in;
  (* src = "b64_b32.py:38" *)
  output [31:0] data_out;
  (* init = 32'd0 *)
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [31:0] fifo32_din = 32'd0;
  (* src = "nmigen/lib/fifo.py:69" *)
  wire [31:0] fifo32_dout;
  (* src = "nmigen/lib/fifo.py:71" *)
  wire fifo32_re;
  (* src = "nmigen/lib/fifo.py:70" *)
  wire fifo32_readable;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:139" *)
  reg fifo32_replace = 1'h0;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:67" *)
  reg fifo32_we = 1'h0;
  (* src = "nmigen/lib/fifo.py:66" *)
  wire fifo32_writable;
  (* init = 64'h0000000000000000 *)
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [63:0] fifo64_din = 64'h0000000000000000;
  (* src = "nmigen/lib/fifo.py:69" *)
  wire [63:0] fifo64_dout;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:71" *)
  reg fifo64_re = 1'h0;
  (* src = "nmigen/lib/fifo.py:70" *)
  wire fifo64_readable;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:139" *)
  reg fifo64_replace = 1'h0;
  (* init = 1'h0 *)
  (* src = "nmigen/lib/fifo.py:67" *)
  reg fifo64_we = 1'h0;
  (* src = "nmigen/lib/fifo.py:66" *)
  wire fifo64_writable;
  (* init = 2'h0 *)
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg [1:0] fsm_state = 2'h0;
  (* init = 1'h0 *)
  (* src = "nmigen/hdl/dsl.py:244" *)
  reg \fsm_state$1  = 1'h0;
  (* src = "b64_b32.py:45" *)
  input i_busy;
  (* init = 1'h0 *)
  (* src = "b64_b32.py:44" *)
  output o_busy;
  reg o_busy = 1'h0;
  (* init = 64'h0000000000000000 *)
  (* src = "b64_b32.py:68" *)
  reg [63:0] \reg  = 64'h0000000000000000;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "b64_b32.py:41" *)
  input valid_in;
  (* src = "b64_b32.py:42" *)
  output valid_out;
  assign \$10  = fifo64_readable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$12  = \$8  & (* src = "b64_b32.py:111" *) \$10 ;
  assign \$14  = fifo32_writable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$16  = fifo64_readable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$18  = \$14  & (* src = "b64_b32.py:111" *) \$16 ;
  assign \$20  = fifo32_writable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$22  = fifo64_readable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$24  = \$20  & (* src = "b64_b32.py:111" *) \$22 ;
  assign \$26  = fifo32_writable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$28  = fifo64_readable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$2  = fifo32_writable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$30  = \$26  & (* src = "b64_b32.py:111" *) \$28 ;
  assign \$32  = i_busy == (* src = "b64_b32.py:131" *) 1'h0;
  assign \$4  = fifo64_readable == (* src = "b64_b32.py:111" *) 1'h1;
  assign \$6  = \$2  & (* src = "b64_b32.py:111" *) \$4 ;
  assign \$8  = fifo32_writable == (* src = "b64_b32.py:111" *) 1'h1;
  always @(posedge clk)
      \fsm_state$1  <= \$next\fsm_state$1 ;
  always @(posedge clk)
      fifo64_we <= \$next\fifo64_we ;
  always @(posedge clk)
      fifo64_replace <= \$next\fifo64_replace ;
  always @(posedge clk)
      fifo32_replace <= \$next\fifo32_replace ;
  always @(posedge clk)
      fifo64_re <= \$next\fifo64_re ;
  always @(posedge clk)
      fifo32_we <= \$next\fifo32_we ;
  always @(posedge clk)
      buff <= \$next\buff ;
  always @(posedge clk)
      fifo32_din <= \$next\fifo32_din ;
  always @(posedge clk)
      \reg  <= \$next\reg ;
  always @(posedge clk)
      fifo64_din <= \$next\fifo64_din ;
  always @(posedge clk)
      fsm_state <= \$next\fsm_state ;
  always @(posedge clk)
      o_busy <= \$next\o_busy ;
  fifo32 fifo32 (
    .clk(clk),
    .din(fifo32_din),
    .dout(fifo32_dout),
    .re(fifo32_re),
    .readable(fifo32_readable),
    .replace(fifo32_replace),
    .rst(rst),
    .we(fifo32_we),
    .writable(fifo32_writable)
  );
  fifo64 fifo64 (
    .clk(clk),
    .din(fifo64_din),
    .dout(fifo64_dout),
    .re(fifo64_re),
    .readable(fifo64_readable),
    .replace(fifo64_replace),
    .rst(rst),
    .we(fifo64_we),
    .writable(fifo64_writable)
  );
  always @* begin
    \$next\fifo32_replace  = fifo32_replace;
    \$next\fifo32_replace  = 1'h0;
    casez (rst)
      1'h1:
          \$next\fifo32_replace  = 1'h0;
    endcase
  end
  always @* begin
    \$next\fifo64_replace  = fifo64_replace;
    \$next\fifo64_replace  = 1'h0;
    casez (rst)
      1'h1:
          \$next\fifo64_replace  = 1'h0;
    endcase
  end
  always @* begin
    \$next\fifo64_re  = fifo64_re;
    casez (\fsm_state$1 )
      1'h0:
          casez ({ fifo32_writable, \$24  })
            2'bz1:
                \$next\fifo64_re  = 1'h1;
          endcase
      1'h1:
          \$next\fifo64_re  = 1'h0;
    endcase
    casez (rst)
      1'h1:
          \$next\fifo64_re  = 1'h0;
    endcase
  end
  always @* begin
    \$next\fsm_state$1  = \fsm_state$1 ;
    casez (\fsm_state$1 )
      1'h0:
          casez ({ fifo32_writable, \$30  })
            2'bz1:
                \$next\fsm_state$1  = 1'h1;
          endcase
      1'h1:
          casez (fifo32_writable)
            1'h1:
                \$next\fsm_state$1  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fsm_state$1  = 1'h0;
    endcase
  end
  always @* begin
    \$next\valid_out  = 1'h0;
    \$next\valid_out  = fifo32_readable;
  end
  always @* begin
    \$next\data_out  = 32'd0;
    \$next\data_out  = fifo32_dout;
  end
  always @* begin
    \$next\fifo32_re  = 1'h0;
    \$next\fifo32_re  = \$32 ;
  end
  always @* begin
    \$next\fifo64_we  = fifo64_we;
    casez (fsm_state)
      2'h0:
          \$next\fifo64_we  = 1'h0;
      2'h1:
          casez (valid_in)
            1'h1:
                casez (fifo64_writable)
                  1'h1:
                      \$next\fifo64_we  = 1'h1;
                endcase
          endcase
      2'h2:
          casez (fifo64_writable)
            1'h1:
                \$next\fifo64_we  = 1'h1;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fifo64_we  = 1'h0;
    endcase
  end
  always @* begin
    \$next\o_busy  = o_busy;
    casez (fsm_state)
      2'h0:
          \$next\o_busy  = 1'h0;
      2'h1:
          casez (valid_in)
            1'h1:
                casez (fifo64_writable)
                  1'h1:
                      \$next\o_busy  = 1'h1;
                  1'hz:
                      \$next\o_busy  = 1'h1;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\o_busy  = 1'h0;
    endcase
  end
  always @* begin
    \$next\fsm_state  = fsm_state;
    casez (fsm_state)
      2'h0:
          \$next\fsm_state  = 2'h1;
      2'h1:
          casez (valid_in)
            1'h1:
                casez (fifo64_writable)
                  1'h1:
                      \$next\fsm_state  = 2'h0;
                  1'hz:
                      \$next\fsm_state  = 2'h2;
                endcase
          endcase
      2'h2:
          casez (fifo64_writable)
            1'h1:
                \$next\fsm_state  = 2'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fsm_state  = 2'h0;
    endcase
  end
  always @* begin
    \$next\fifo64_din  = fifo64_din;
    casez (fsm_state)
      2'h1:
          casez (valid_in)
            1'h1:
                casez (fifo64_writable)
                  1'h1:
                      \$next\fifo64_din  = data_in;
                endcase
          endcase
      2'h2:
          casez (fifo64_writable)
            1'h1:
                \$next\fifo64_din  = \reg ;
          endcase
    endcase
  end
  always @* begin
    \$next\reg  = \reg ;
    casez (fsm_state)
      2'h1:
          casez (valid_in)
            1'h1:
                casez (fifo64_writable)
                  1'h1:
;
                  1'hz:
                      \$next\reg  = data_in;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\reg  = 64'h0000000000000000;
    endcase
  end
  always @* begin
    \$next\fifo32_din  = fifo32_din;
    casez (\fsm_state$1 )
      1'h0:
          casez ({ fifo32_writable, \$6  })
            2'bz1:
                \$next\fifo32_din  = fifo64_dout[63:32];
          endcase
      1'h1:
          casez (fifo32_writable)
            1'h1:
                \$next\fifo32_din  = buff;
          endcase
    endcase
  end
  always @* begin
    \$next\buff  = buff;
    casez (\fsm_state$1 )
      1'h0:
          casez ({ fifo32_writable, \$12  })
            2'bz1:
                \$next\buff  = fifo64_dout[31:0];
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\buff  = 32'd0;
    endcase
  end
  always @* begin
    \$next\fifo32_we  = fifo32_we;
    casez (\fsm_state$1 )
      1'h0:
          casez ({ fifo32_writable, \$18  })
            2'bz1:
                \$next\fifo32_we  = 1'h1;
            2'b1z:
                \$next\fifo32_we  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\fifo32_we  = 1'h0;
    endcase
  end
  assign fifo32_re = \$next\fifo32_re ;
  assign data_out = \$next\data_out ;
  assign valid_out = \$next\valid_out ;
endmodule