data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_par2ser.v
 line:14: before: "CDS_LIBNAME"
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_par2ser.v:21: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_par2ser.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #CLK_PERIOD\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_par2ser.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD*2)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_par2ser.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD*10)\n    ^\n%Error: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_par2ser.v:12: Cannot find file containing module: \'par2ser\'\npar2ser utt(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches,data/full_repos/permissive/212763527/par2ser\n             data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches,data/full_repos/permissive/212763527/par2ser.v\n             data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches,data/full_repos/permissive/212763527/par2ser.sv\n             par2ser\n             par2ser.v\n             par2ser.sv\n             obj_dir/par2ser\n             obj_dir/par2ser.v\n             obj_dir/par2ser.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_par2ser;
reg clk;
reg rst;
reg read;
reg [7:0] din;

wire dout;

 
par2ser utt(
    din,
    read,
    rst,
    clk,
    dout
);

localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;

initial begin
    clk = 1'b0;
    rst = 1'b1;
    read = 1'b1;
    din = 8'b1101_1010;
end

initial begin
    #CLK_PERIOD
    rst = 1'b0;
    #(CLK_PERIOD*2)
    read = 1'b0;
    #(CLK_PERIOD*10)
    $finish;
end

endmodule
module tb_par2ser;

reg clk;
reg rst;
reg read;
reg [7:0] din;

wire dout;

 
par2ser utt(
    din,
    read,
    rst,
    clk,
    dout
);

localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;

initial begin
    clk = 1'b0;
    rst = 1'b1;
    read = 1'b1;
    din = 8'b1101_1010;
end

initial begin
    #CLK_PERIOD
    rst = 1'b0;
    #(CLK_PERIOD*2)
    read = 1'b0;
    #(CLK_PERIOD*10)
    $finish;
end

endmodule