data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/ram.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/ram.v:56: Assigning to input/const variable: 'r1_data'\n assign r1_data = mem[addr1_reg];\n        ^~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/ram.v:57: Assigning to input/const variable: 'r2_data'\n assign r2_data = mem[addr2_reg];\n        ^~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module ram(
	input clk,
	input we,
	input [31:0] r1_addr,
	input [31:0] r1_data,
	input [31:0] r2_addr,
	input [31:0] r2_data,
	input [31:0] w_addr,
	input [31:0] w_data
);
	reg [13:0] addr1_reg;
	reg [13:0] addr2_reg;
	reg [31:0] mem [0:(`MEM_SIZE-1)];

	wire [13:0] Wr1_index, Wr2_index, Ww_index;
	assign Wr1_index = r1_addr[15:2];
	assign Wr2_index = r2_addr[15:2];
	assign Ww_index = w_addr[15:2];


	integer i;
	initial begin
		for(i = 0; i < `MEM_SIZE; i=i+1) mem[i] = 0;
		$readmemb("../../../../init.ram", mem);
	end

	always @(posedge clk) begin
		if(we) mem[Ww_index] <= w_data;
		addr1_reg <= Wr1_index;
		addr2_reg <= Wr2_index;
	end

	assign r1_data = mem[addr1_reg];
	assign r2_data = mem[addr2_reg];
endmodule
module ram(
	input clk,
	input we,
	input [31:0] r1_addr,
	input [31:0] r1_data,
	input [31:0] r2_addr,
	input [31:0] r2_data,
	input [31:0] w_addr,
	input [31:0] w_data
);

	reg [13:0] addr1_reg;
	reg [13:0] addr2_reg;
	reg [31:0] mem [0:(`MEM_SIZE-1)];

	wire [13:0] Wr1_index, Wr2_index, Ww_index;
	assign Wr1_index = r1_addr[15:2];
	assign Wr2_index = r2_addr[15:2];
	assign Ww_index = w_addr[15:2];


	integer i;
	initial begin
		for(i = 0; i < `MEM_SIZE; i=i+1) mem[i] = 0;
		$readmemb("../../../../init.ram", mem);
	end

	always @(posedge clk) begin
		if(we) mem[Ww_index] <= w_data;
		addr1_reg <= Wr1_index;
		addr2_reg <= Wr2_index;
	end

	assign r1_data = mem[addr1_reg];
	assign r2_data = mem[addr2_reg];
endmodule