data/full_repos/permissive/162672365/DataForwardingUnit.v
 line:6: before: "("
1: b"%Error: data/full_repos/permissive/162672365/DataForwardingUnit.v:6: syntax error, unexpected '@', expecting TYPE-IDENTIFIER\n always (@ negedge clk) begin\n         ^\n%Error: Cannot continue\n"
module DataForwardingUnit(forwardA, forwardB, Rs2, Rt2, destreg3, destreg4, RegWrite3, RegWrite4, clk);
	input RegWrite3, RegWrite4, clk;
	input [4:0] Rs2, Rt2, destreg3, destreg4;
	output [1:0] forwardA, forwardB;
	
	always (@ negedge clk) begin
		if(RegWrite3 & (destreg3 != 0) & (destreg3 = Rs2))
			forwardA <= 2'b10;
		else if(RegWrite4 & (destreg4 != 0) & (destreg3 != Rs2) & (destreg4 = Rs2))
			forwardA <= 2'b01;
		else
			forwardA <= 2'b00;
	end
	
	always (@ negedge clk) begin
		if(RegWrite3 & (destreg3 != 0) & (destreg3 = Rt2))
			forwardB <= 2'b10;
		else if(RegWrite4 & (destreg4 != 0) & (destreg3 != Rt2) & (destreg4 = Rt2))
			forwardB <= 2'b01;
		else
			forwardB <= 2'b00;
	end
	
endmodule
module DataForwardingUnit(forwardA, forwardB, Rs2, Rt2, destreg3, destreg4, RegWrite3, RegWrite4, clk);

	input RegWrite3, RegWrite4, clk;
	input [4:0] Rs2, Rt2, destreg3, destreg4;
	output [1:0] forwardA, forwardB;
	
	always (@ negedge clk) begin
		if(RegWrite3 & (destreg3 != 0) & (destreg3 = Rs2))
			forwardA <= 2'b10;
		else if(RegWrite4 & (destreg4 != 0) & (destreg3 != Rs2) & (destreg4 = Rs2))
			forwardA <= 2'b01;
		else
			forwardA <= 2'b00;
	end
	
	always (@ negedge clk) begin
		if(RegWrite3 & (destreg3 != 0) & (destreg3 = Rt2))
			forwardB <= 2'b10;
		else if(RegWrite4 & (destreg4 != 0) & (destreg3 != Rt2) & (destreg4 = Rt2))
			forwardB <= 2'b01;
		else
			forwardB <= 2'b00;
	end
	
endmodule