data/full_repos/permissive/158922207/Verilog Design/modules/SSD.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/SSD.v\n%Error: Exiting due to 3 error(s)\n'
module SSD(
    input [3:0] bit_input,
    output reg [6:0] ssd
    );
      
    always @(*)
    begin
        case(bit_input)
        4'b0000: ssd = 7'b0000001;
        4'b0001: ssd = 7'b1001111;
        4'b0010: ssd = 7'b0010010;
        4'b0011: ssd = 7'b0000110;
        4'b0100: ssd = 7'b1001100;
        4'b0101: ssd = 7'b0100100;
        4'b0110: ssd = 7'b0100000;
        4'b0111: ssd = 7'b0001111;
        4'b1000: ssd = 7'b0000000;
        4'b1001: ssd = 7'b0000100;
        4'b1010: ssd = 7'b0001000;
        4'b1011: ssd = 7'b1100000;
        4'b1100: ssd = 7'b0110001;
        4'b1101: ssd = 7'b1000010;
        4'b1110: ssd = 7'b0110000;
        4'b1111: ssd = 7'b0111000;
        default: ssd = 7'b0000001;
        endcase
    end
 endmodule
module SSD(
    input [3:0] bit_input,
    output reg [6:0] ssd
    );

      
    always @(*)
    begin
        case(bit_input)
        4'b0000: ssd = 7'b0000001;
        4'b0001: ssd = 7'b1001111;
        4'b0010: ssd = 7'b0010010;
        4'b0011: ssd = 7'b0000110;
        4'b0100: ssd = 7'b1001100;
        4'b0101: ssd = 7'b0100100;
        4'b0110: ssd = 7'b0100000;
        4'b0111: ssd = 7'b0001111;
        4'b1000: ssd = 7'b0000000;
        4'b1001: ssd = 7'b0000100;
        4'b1010: ssd = 7'b0001000;
        4'b1011: ssd = 7'b1100000;
        4'b1100: ssd = 7'b0110001;
        4'b1101: ssd = 7'b1000010;
        4'b1110: ssd = 7'b0110000;
        4'b1111: ssd = 7'b0111000;
        default: ssd = 7'b0000001;
        endcase
    end
 endmodule