data/full_repos/permissive/104305228/code/mem.v
1: b'%Error: data/full_repos/permissive/104305228/code/mem.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/mem.v:25: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:25: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (rst == `RstEnable) begin\n                       ^\n%Error: data/full_repos/permissive/104305228/code/mem.v:26: Define or directive not defined: \'`ReadDisable\'\n   mem_re <= `ReadDisable;\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:28: Define or directive not defined: \'`WriteDisable\'\n   mem_we <= `WriteDisable;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:28: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   mem_we <= `WriteDisable;\n                          ^\n%Error: data/full_repos/permissive/104305228/code/mem.v:32: Define or directive not defined: \'`WriteDisable\'\n   we_o <= `WriteDisable;\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   we_o <= `WriteDisable;\n                        ^\n%Error: data/full_repos/permissive/104305228/code/mem.v:36: syntax error, unexpected else\n  else begin\n  ^~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:37: Define or directive not defined: \'`ReadDisable\'\n   mem_re <= `ReadDisable;\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:39: Define or directive not defined: \'`WriteDisable\'\n   mem_we <= `WriteDisable;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:47: Define or directive not defined: \'`op_lb\'\n    `op_lb : begin\n    ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:47: syntax error, unexpected \':\', expecting endcase\n    `op_lb : begin\n           ^\n%Error: data/full_repos/permissive/104305228/code/mem.v:48: Define or directive not defined: \'`ReadEnable\'\n     mem_re <= `ReadEnable;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:50: Define or directive not defined: \'`WriteDisable\'\n     mem_we <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:53: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {{24{mem_i[31]}}, mem_i[31:24]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:56: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {{24{mem_i[23]}}, mem_i[23:16]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:59: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {{24{mem_i[15]}}, mem_i[15:8]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:62: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {{24{mem_i[7]}}, mem_i[7:0]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:65: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= 32\'b0;\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:68: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:69: Define or directive not defined: \'`op_lbu\'\n    `op_lbu : begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:70: Define or directive not defined: \'`ReadEnable\'\n     mem_re <= `ReadEnable;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:72: Define or directive not defined: \'`WriteDisable\'\n     mem_we <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:75: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {24\'b0, mem_i[31:24]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:78: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {24\'b0, mem_i[23:16]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:81: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {24\'b0, mem_i[15:8]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:84: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {24\'b0, mem_i[7:0]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:87: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= 32\'b0;\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:90: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:91: Define or directive not defined: \'`op_lh\'\n    `op_lh : begin\n    ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:92: Define or directive not defined: \'`ReadEnable\'\n     mem_re <= `ReadEnable;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:94: Define or directive not defined: \'`WriteDisable\'\n     mem_we <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:97: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {{16{mem_i[31]}}, mem_i[31:16]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:100: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {{16{mem_i[15]}}, mem_i[15:0]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:103: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= 32\'b0;\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:106: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:107: Define or directive not defined: \'`op_lhu\'\n    `op_lhu : begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:108: Define or directive not defined: \'`ReadEnable\'\n     mem_re <= `ReadEnable;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:110: Define or directive not defined: \'`WriteDisable\'\n     mem_we <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:113: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {16\'b0, mem_i[31:16]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:116: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= {16\'b0, mem_i[15:0]};\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:119: syntax error, unexpected <=, expecting IDENTIFIER\n       write_instr_o <= 32\'b0;\n                     ^~\n%Error: data/full_repos/permissive/104305228/code/mem.v:122: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:123: Define or directive not defined: \'`op_lw\'\n    `op_lw : begin\n    ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:124: Define or directive not defined: \'`ReadEnable\'\n     mem_re <= `ReadEnable;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:126: Define or directive not defined: \'`WriteDisable\'\n     mem_we <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:129: Define or directive not defined: \'`op_lwr\'\n    `op_lwr : begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:131: Define or directive not defined: \'`op_lwl\'\n    `op_lwl : begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/mem.v:133: Define or directive not defined: \'`op_sb\'\n    `op_sb : begin\n    ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mem(
	input rst,
	input [31:0] instr,
	input [7:0] op,
	input [31:0] reg1,
	input [31:0] reg2,
	input [31:0] mem_i,
	input we_i,
	input [4:0] write_addr_i,
	input [31:0] write_instr_i,

	output reg mem_re,
	output reg[31:0] mem_read_addr,
	output reg mem_we,
	output reg[31:0] mem_write_addr,
	output reg[3:0] mem_write,
	output reg[31:0] mem_write_instr,
	output reg we_o,
	output reg[4:0] write_addr_o,
	output reg[31:0] write_instr_o
);
	wire [31:0] addr = reg1 + {{16{instr[15]}}, instr[15:0]};
	always @ (*) begin
		if (rst == `RstEnable) begin
			mem_re <= `ReadDisable;
			mem_read_addr <= 5'b0;
			mem_we <= `WriteDisable;
			mem_write_addr <= 5'b0;
			mem_write <= 4'b0;
			mem_write_instr <= 32'b0;
			we_o <= `WriteDisable;
			write_addr_o <= 5'b0;
			write_instr_o <= 32'b0;
		end
		else begin
			mem_re <= `ReadDisable;
			mem_read_addr <= 5'b0;
			mem_we <= `WriteDisable;
			mem_write_addr <= 5'b0;
			mem_write <= 4'b0;
			mem_write_instr <= 32'b0;
			we_o <= we_i;
			write_addr_o <= write_addr_i;
			write_instr_o <= write_instr_i;
			case (op)
				`op_lb : begin
					mem_re <= `ReadEnable;
					mem_read_addr <= addr;
					mem_we <= `WriteDisable;
					case (addr[1:0])
						2'b00 : begin
							write_instr_o <= {{24{mem_i[31]}}, mem_i[31:24]};
						end
						2'b01 : begin
							write_instr_o <= {{24{mem_i[23]}}, mem_i[23:16]};
						end
						2'b10 : begin
							write_instr_o <= {{24{mem_i[15]}}, mem_i[15:8]};
						end
						2'b11 : begin
							write_instr_o <= {{24{mem_i[7]}}, mem_i[7:0]};
						end
						default : begin
							write_instr_o <= 32'b0;
						end
					endcase
				end
				`op_lbu : begin
					mem_re <= `ReadEnable;
					mem_read_addr <= addr;
					mem_we <= `WriteDisable;
					case (addr[1:0])
						2'b00 : begin
							write_instr_o <= {24'b0, mem_i[31:24]};
						end
						2'b01 : begin
							write_instr_o <= {24'b0, mem_i[23:16]};
						end
						2'b10 : begin
							write_instr_o <= {24'b0, mem_i[15:8]};
						end
						2'b11 : begin
							write_instr_o <= {24'b0, mem_i[7:0]};
						end
						default : begin
							write_instr_o <= 32'b0;
						end
					endcase
				end
				`op_lh : begin
					mem_re <= `ReadEnable;
					mem_read_addr <= addr;
					mem_we <= `WriteDisable;
					case (addr[1:0])
						2'b00 : begin
							write_instr_o <= {{16{mem_i[31]}}, mem_i[31:16]};
						end
						2'b10 : begin
							write_instr_o <= {{16{mem_i[15]}}, mem_i[15:0]};
						end
						default : begin
							write_instr_o <= 32'b0;
						end
					endcase
				end
				`op_lhu : begin
					mem_re <= `ReadEnable;
					mem_read_addr <= addr;
					mem_we <= `WriteDisable;
					case (addr[1:0])
						2'b00 : begin
							write_instr_o <= {16'b0, mem_i[31:16]};
						end
						2'b10 : begin
							write_instr_o <= {16'b0, mem_i[15:0]};
						end
						default : begin
							write_instr_o <= 32'b0;
						end
					endcase
				end
				`op_lw : begin
					mem_re <= `ReadEnable;
					mem_read_addr <= addr;
					mem_we <= `WriteDisable;
					write_instr_o <= mem_i;
				end
				`op_lwr : begin
				end
				`op_lwl : begin
				end
				`op_sb : begin
					mem_re <= `ReadDisable;
					mem_write_addr <= addr;
					mem_we <= `WriteEnable;
					mem_write_instr <= {4{reg2[7:0]}};
					case (addr[1:0])
						2'b00 : begin
							mem_write <= 4'b1000;
						end
						2'b01 : begin
							mem_write <= 4'b0100;
						end
						2'b10 : begin
							mem_write <= 4'b0010;
						end
						2'b11 : begin
							mem_write <= 4'b0001;
						end
						default : begin
							mem_write <= 4'b0000;
						end
					endcase
				end
				`op_sh : begin
				end
				`op_sw : begin
					mem_re <= `ReadDisable;
					mem_write_addr <= addr;
					mem_we <= `WriteEnable;
					mem_write_instr <= reg2;
					mem_write <= 4'b1111;
				end
				`op_swl : begin
				end
				`op_swr : begin
				end
			endcase
		end
	end
endmodule
module mem(
	input rst,
	input [31:0] instr,
	input [7:0] op,
	input [31:0] reg1,
	input [31:0] reg2,
	input [31:0] mem_i,
	input we_i,
	input [4:0] write_addr_i,
	input [31:0] write_instr_i,

	output reg mem_re,
	output reg[31:0] mem_read_addr,
	output reg mem_we,
	output reg[31:0] mem_write_addr,
	output reg[3:0] mem_write,
	output reg[31:0] mem_write_instr,
	output reg we_o,
	output reg[4:0] write_addr_o,
	output reg[31:0] write_instr_o
);

	wire [31:0] addr = reg1 + {{16{instr[15]}}, instr[15:0]};
	always @ (*) begin
		if (rst == `RstEnable) begin
			mem_re <= `ReadDisable;
			mem_read_addr <= 5'b0;
			mem_we <= `WriteDisable;
			mem_write_addr <= 5'b0;
			mem_write <= 4'b0;
			mem_write_instr <= 32'b0;
			we_o <= `WriteDisable;
			write_addr_o <= 5'b0;
			write_instr_o <= 32'b0;
		end
		else begin
			mem_re <= `ReadDisable;
			mem_read_addr <= 5'b0;
			mem_we <= `WriteDisable;
			mem_write_addr <= 5'b0;
			mem_write <= 4'b0;
			mem_write_instr <= 32'b0;
			we_o <= we_i;
			write_addr_o <= write_addr_i;
			write_instr_o <= write_instr_i;
			case (op)
				`op_lb : begin
					mem_re <= `ReadEnable;
					mem_read_addr <= addr;
					mem_we <= `WriteDisable;
					case (addr[1:0])
						2'b00 : begin
							write_instr_o <= {{24{mem_i[31]}}, mem_i[31:24]};
						end
						2'b01 : begin
							write_instr_o <= {{24{mem_i[23]}}, mem_i[23:16]};
						end
						2'b10 : begin
							write_instr_o <= {{24{mem_i[15]}}, mem_i[15:8]};
						end
						2'b11 : begin
							write_instr_o <= {{24{mem_i[7]}}, mem_i[7:0]};
						end
						default : begin
							write_instr_o <= 32'b0;
						end
					endcase
				end
				`op_lbu : begin
					mem_re <= `ReadEnable;
					mem_read_addr <= addr;
					mem_we <= `WriteDisable;
					case (addr[1:0])
						2'b00 : begin
							write_instr_o <= {24'b0, mem_i[31:24]};
						end
						2'b01 : begin
							write_instr_o <= {24'b0, mem_i[23:16]};
						end
						2'b10 : begin
							write_instr_o <= {24'b0, mem_i[15:8]};
						end
						2'b11 : begin
							write_instr_o <= {24'b0, mem_i[7:0]};
						end
						default : begin
							write_instr_o <= 32'b0;
						end
					endcase
				end
				`op_lh : begin
					mem_re <= `ReadEnable;
					mem_read_addr <= addr;
					mem_we <= `WriteDisable;
					case (addr[1:0])
						2'b00 : begin
							write_instr_o <= {{16{mem_i[31]}}, mem_i[31:16]};
						end
						2'b10 : begin
							write_instr_o <= {{16{mem_i[15]}}, mem_i[15:0]};
						end
						default : begin
							write_instr_o <= 32'b0;
						end
					endcase
				end
				`op_lhu : begin
					mem_re <= `ReadEnable;
					mem_read_addr <= addr;
					mem_we <= `WriteDisable;
					case (addr[1:0])
						2'b00 : begin
							write_instr_o <= {16'b0, mem_i[31:16]};
						end
						2'b10 : begin
							write_instr_o <= {16'b0, mem_i[15:0]};
						end
						default : begin
							write_instr_o <= 32'b0;
						end
					endcase
				end
				`op_lw : begin
					mem_re <= `ReadEnable;
					mem_read_addr <= addr;
					mem_we <= `WriteDisable;
					write_instr_o <= mem_i;
				end
				`op_lwr : begin
				end
				`op_lwl : begin
				end
				`op_sb : begin
					mem_re <= `ReadDisable;
					mem_write_addr <= addr;
					mem_we <= `WriteEnable;
					mem_write_instr <= {4{reg2[7:0]}};
					case (addr[1:0])
						2'b00 : begin
							mem_write <= 4'b1000;
						end
						2'b01 : begin
							mem_write <= 4'b0100;
						end
						2'b10 : begin
							mem_write <= 4'b0010;
						end
						2'b11 : begin
							mem_write <= 4'b0001;
						end
						default : begin
							mem_write <= 4'b0000;
						end
					endcase
				end
				`op_sh : begin
				end
				`op_sw : begin
					mem_re <= `ReadDisable;
					mem_write_addr <= addr;
					mem_we <= `WriteEnable;
					mem_write_instr <= reg2;
					mem_write <= 4'b1111;
				end
				`op_swl : begin
				end
				`op_swr : begin
				end
			endcase
		end
	end
endmodule