data/full_repos/permissive/214823094/lab_5/project_1_1/clkdiv.v
data/verilator_xmls/2ce59fbe-7d31-43c4-a3c8-34bfa4506179.xml
module clkdiv(
    input mclk,



    output clk1_4hz
    );
    reg [27:0]q;
    always@(posedge mclk)




         q<=q+1;



    assign clk1_4hz=q[24];         
endmodule
module clkdiv(
    input mclk,



    output clk1_4hz
    );

    reg [27:0]q;
    always@(posedge mclk)




         q<=q+1;



    assign clk1_4hz=q[24];         
endmodule