data/full_repos/permissive/135820056/sys/video_freak.sv
 line:47: before: "reg"
1: b'%Error: data/full_repos/permissive/135820056/sys/video_freak.sv:165: Cannot find file containing module: \'sys_udiv\'\nsys_udiv #(24,12) div(CLK_VIDEO,div_start,div_run, div_num,div_den,div_res);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135820056/sys,data/full_repos/permissive/135820056/sys_udiv\n             data/full_repos/permissive/135820056/sys,data/full_repos/permissive/135820056/sys_udiv.v\n             data/full_repos/permissive/135820056/sys,data/full_repos/permissive/135820056/sys_udiv.sv\n             sys_udiv\n             sys_udiv.v\n             sys_udiv.sv\n             obj_dir/sys_udiv\n             obj_dir/sys_udiv.v\n             obj_dir/sys_udiv.sv\n%Error: data/full_repos/permissive/135820056/sys/video_freak.sv:171: Cannot find file containing module: \'sys_umul\'\nsys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);\n^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:185: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'arx_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n  arxf <= arx_i;\n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:186: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'ary_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n  aryf <= ary_i;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:192: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'HDMI_HEIGHT\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     div_num   <= HDMI_HEIGHT;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:200: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'arx_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     arxf      <= arx_i;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:201: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'ary_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     aryf      <= ary_i;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:197: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n   1: if(!div_res[11:0]) begin\n         ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:212: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'ary_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     if(!ary_i) begin\n        ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:237: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     mul_arg2  <= div_res[11:0] ? div_res[11:0] : 12\'d1;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:241: Operator LTE expects 24 bits on the RHS, but RHS\'s VARREF \'HDMI_WIDTH\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n   7: if(mul_res <= HDMI_WIDTH) begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:246: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'HDMI_WIDTH\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     div_num   <= HDMI_WIDTH;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:253: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     mul_arg2  <= div_res[11:0] ? div_res[11:0] : 12\'d1;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:184: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'SCALE\' generates 3 bits.\n                                                                           : ... In instance video_freak.scale\n if (!SCALE || (!ary_i && arx_i)) begin\n     ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:184: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'ary_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n if (!SCALE || (!ary_i && arx_i)) begin\n                ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:184: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'arx_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n if (!SCALE || (!ary_i && arx_i)) begin\n                       ^~\n%Error: data/full_repos/permissive/135820056/sys/video_freak.sv:39: Cannot find file containing module: \'sys_umul\'\nsys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);\n^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:68: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'vcpt\' generates 12 bits.\n                                                                          : ... In instance video_freak\n   if(!vcpt) hsize <= hcpt;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:76: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'vcrop\' generates 12 bits.\n                                                                          : ... In instance video_freak\n vsize <= vcrop ? vcrop : vtot;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:84: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'vcalc\' generates 2 bits.\n                                                                          : ... In instance video_freak\n else if (vcalc) begin\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:80: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'vcrop\' generates 12 bits.\n                                                                          : ... In instance video_freak\n if(!vcrop || !ary || !arx) begin\n    ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:80: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'ary\' generates 12 bits.\n                                                                          : ... In instance video_freak\n if(!vcrop || !ary || !arx) begin\n              ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:80: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'arx\' generates 12 bits.\n                                                                          : ... In instance video_freak\n if(!vcrop || !ary || !arx) begin\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:117: Operator COND expects 12 bits on the Conditional False, but Conditional False\'s SEL generates 11 bits.\n                                                                           : ... In instance video_freak\n voff <= vadj[11] ? 12\'d0 : ((vadj[11:1] + vcrop) > vtot) ? vtot-vcrop : vadj[11:1];\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:118: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'vcrop\' generates 12 bits.\n                                                                           : ... In instance video_freak\n ovde <= ((vcpt >= voff) && (vcpt < (vcrop + voff))) || !vcrop;\n                                                        ^\n%Error: Exiting due to 3 error(s), 22 warning(s)\n'
module video_scale_int
(
	input             CLK_VIDEO,

	input      [11:0] HDMI_WIDTH,
	input      [11:0] HDMI_HEIGHT,

	input       [2:0] SCALE,

	input      [11:0] hsize,
	input      [11:0] vsize,

	input      [11:0] arx_i,
	input      [11:0] ary_i,

	output reg [12:0] arx_o,
	output reg [12:0] ary_o
);

reg         div_start;
wire        div_run;
reg  [23:0] div_num;
reg  [11:0] div_den;
wire [23:0] div_res;
sys_udiv #(24,12) div(CLK_VIDEO,div_start,div_run, div_num,div_den,div_res);

reg         mul_start;
wire        mul_run;
reg  [11:0] mul_arg1, mul_arg2;
wire [23:0] mul_res;
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);

wire [11:0] wideres = mul_res[11:0] + hsize;

always @(posedge CLK_VIDEO) begin
	reg [11:0] oheight,wres;
	reg [12:0] arxf,aryf;
	reg  [3:0] cnt;
	reg        narrow;

	div_start <= 0;
	mul_start <= 0;

	if (!SCALE || (!ary_i && arx_i)) begin
		arxf <= arx_i;
		aryf <= ary_i;
	end
	else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin
		cnt <= cnt + 1'd1;
		case(cnt)
			0: begin
					div_num   <= HDMI_HEIGHT;
					div_den   <= vsize;
					div_start <= 1;
				end

			1: if(!div_res[11:0]) begin


					arxf      <= arx_i;
					aryf      <= ary_i;
					cnt       <= 0;
				end
				else begin
					mul_arg1  <= vsize;
					mul_arg2  <= div_res[11:0];
					mul_start <= 1;
				end

			2: begin
					oheight   <= mul_res[11:0];
					if(!ary_i) begin
						cnt    <= 8;
					end
				end
				
			3: begin
					mul_arg1  <= mul_res[11:0];
					mul_arg2  <= arx_i;
					mul_start <= 1;
				end

			4: begin
					div_num   <= mul_res;
					div_den   <= ary_i;
					div_start <= 1;
				end

			5: begin
					div_num   <= div_res;
					div_den   <= hsize;
					div_start <= 1;
				end

			6: begin
					mul_arg1  <= hsize;
					mul_arg2  <= div_res[11:0] ? div_res[11:0] : 12'd1;
					mul_start <= 1;
				end

			7: if(mul_res <= HDMI_WIDTH) begin
					cnt       <= 10;
				end

			8:	begin
					div_num   <= HDMI_WIDTH;
					div_den   <= hsize;
					div_start <= 1;
				end

			9: begin
					mul_arg1  <= hsize;
					mul_arg2  <= div_res[11:0] ? div_res[11:0] : 12'd1;
					mul_start <= 1;
				end

			10: begin
					narrow    <= ((div_num[11:0] - mul_res[11:0]) <= (wideres - div_num[11:0])) || (wideres > HDMI_WIDTH);
					wres      <= wideres;
				end

			11: begin
					case(SCALE)
							2: arxf <= {1'b1, mul_res[11:0]};
							3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres};
							4: arxf <= {1'b1,              narrow ? mul_res[11:0] : wres};
					default: arxf <= {1'b1, div_num[11:0]};
					endcase
					aryf <= {1'b1, oheight};
				end
		endcase
	end

	arx_o <= arxf;
	ary_o <= aryf;
end

endmodule
module video_scale_int
(
	input             CLK_VIDEO,

	input      [11:0] HDMI_WIDTH,
	input      [11:0] HDMI_HEIGHT,

	input       [2:0] SCALE,

	input      [11:0] hsize,
	input      [11:0] vsize,

	input      [11:0] arx_i,
	input      [11:0] ary_i,

	output reg [12:0] arx_o,
	output reg [12:0] ary_o
);


reg         div_start;
wire        div_run;
reg  [23:0] div_num;
reg  [11:0] div_den;
wire [23:0] div_res;
sys_udiv #(24,12) div(CLK_VIDEO,div_start,div_run, div_num,div_den,div_res);

reg         mul_start;
wire        mul_run;
reg  [11:0] mul_arg1, mul_arg2;
wire [23:0] mul_res;
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);

wire [11:0] wideres = mul_res[11:0] + hsize;

always @(posedge CLK_VIDEO) begin
	reg [11:0] oheight,wres;
	reg [12:0] arxf,aryf;
	reg  [3:0] cnt;
	reg        narrow;

	div_start <= 0;
	mul_start <= 0;

	if (!SCALE || (!ary_i && arx_i)) begin
		arxf <= arx_i;
		aryf <= ary_i;
	end
	else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin
		cnt <= cnt + 1'd1;
		case(cnt)
			0: begin
					div_num   <= HDMI_HEIGHT;
					div_den   <= vsize;
					div_start <= 1;
				end

			1: if(!div_res[11:0]) begin


					arxf      <= arx_i;
					aryf      <= ary_i;
					cnt       <= 0;
				end
				else begin
					mul_arg1  <= vsize;
					mul_arg2  <= div_res[11:0];
					mul_start <= 1;
				end

			2: begin
					oheight   <= mul_res[11:0];
					if(!ary_i) begin
						cnt    <= 8;
					end
				end
				
			3: begin
					mul_arg1  <= mul_res[11:0];
					mul_arg2  <= arx_i;
					mul_start <= 1;
				end

			4: begin
					div_num   <= mul_res;
					div_den   <= ary_i;
					div_start <= 1;
				end

			5: begin
					div_num   <= div_res;
					div_den   <= hsize;
					div_start <= 1;
				end

			6: begin
					mul_arg1  <= hsize;
					mul_arg2  <= div_res[11:0] ? div_res[11:0] : 12'd1;
					mul_start <= 1;
				end

			7: if(mul_res <= HDMI_WIDTH) begin
					cnt       <= 10;
				end

			8:	begin
					div_num   <= HDMI_WIDTH;
					div_den   <= hsize;
					div_start <= 1;
				end

			9: begin
					mul_arg1  <= hsize;
					mul_arg2  <= div_res[11:0] ? div_res[11:0] : 12'd1;
					mul_start <= 1;
				end

			10: begin
					narrow    <= ((div_num[11:0] - mul_res[11:0]) <= (wideres - div_num[11:0])) || (wideres > HDMI_WIDTH);
					wres      <= wideres;
				end

			11: begin
					case(SCALE)
							2: arxf <= {1'b1, mul_res[11:0]};
							3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres};
							4: arxf <= {1'b1,              narrow ? mul_res[11:0] : wres};
					default: arxf <= {1'b1, div_num[11:0]};
					endcase
					aryf <= {1'b1, oheight};
				end
		endcase
	end

	arx_o <= arxf;
	ary_o <= aryf;
end

endmodule