data/full_repos/permissive/144785545/FourbitCPU_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/144785545/FourbitCPU_TEST.v:14: Unsupported: Ignoring delay on this delayed statement.\n CLK = ~CLK; #STEP;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/144785545/FourbitCPU_TEST.v:26: Unsupported: Ignoring delay on this delayed statement.\n #STEP order=8\'b10110001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/144785545/FourbitCPU_TEST.v:27: Unsupported: Ignoring delay on this delayed statement.\n #STEP order=8\'b10110001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/144785545/FourbitCPU_TEST.v:28: Unsupported: Ignoring delay on this delayed statement.\n #STEP order=8\'b10110001;\n ^\n%Error: data/full_repos/permissive/144785545/FourbitCPU_TEST.v:19: Cannot find file containing module: \'FourBitCPU\'\nFourBitCPU cpu(.CLK(CLK), .RST(RST), .order(order), .OUT(OUT), .CNT(CNT));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/144785545,data/full_repos/permissive/144785545/FourBitCPU\n             data/full_repos/permissive/144785545,data/full_repos/permissive/144785545/FourBitCPU.v\n             data/full_repos/permissive/144785545,data/full_repos/permissive/144785545/FourBitCPU.sv\n             FourBitCPU\n             FourBitCPU.v\n             FourBitCPU.sv\n             obj_dir/FourBitCPU\n             obj_dir/FourBitCPU.v\n             obj_dir/FourBitCPU.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FourbitCPU_TEST(
			input  [3:0]  INV,
			output [3:0] OUTV
);

reg CLK, RST;
reg [7:0] order;
wire [3:0] OUT;
wire [3:0] CNT;

parameter STEP=100;

always begin
	CLK = ~CLK; #STEP;
end



FourBitCPU cpu(.CLK(CLK), .RST(RST), .order(order), .OUT(OUT), .CNT(CNT));



initial begin
	RST = 0; CLK=0; 
	
	#STEP order=8'b10110001;
	#STEP order=8'b10110001;
	#STEP order=8'b10110001;
end


endmodule
module FourbitCPU_TEST(
			input  [3:0]  INV,
			output [3:0] OUTV
);


reg CLK, RST;
reg [7:0] order;
wire [3:0] OUT;
wire [3:0] CNT;

parameter STEP=100;

always begin
	CLK = ~CLK; #STEP;
end



FourBitCPU cpu(.CLK(CLK), .RST(RST), .order(order), .OUT(OUT), .CNT(CNT));



initial begin
	RST = 0; CLK=0; 
	
	#STEP order=8'b10110001;
	#STEP order=8'b10110001;
	#STEP order=8'b10110001;
end


endmodule