data/full_repos/permissive/143278/ivltests/pr2922063.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2922063.v:11: Operator ADD expects 32 bits on the LHS, but LHS\'s CONST \'7\'sha\' generates 7 bits.\n                                                                         : ... In instance top\n    val = 7\'sd10 + (val >>> 1);\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2922063.v:20: Operator ADD expects 32 bits on the LHS, but LHS\'s SIGNED generates 7 bits.\n                                                                         : ... In instance top\n    val = $signed(7\'d10) + (val >>> 1);\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2922063.v:37: Operator ADD expects 32 bits on the LHS, but LHS\'s CONST \'7\'ha\' generates 7 bits.\n                                                                         : ... In instance top\n    val = 7\'d10 + $signed(val >>> 1);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2922063.v:45: Operator ADD expects 32 bits on the LHS, but LHS\'s CONST \'7\'ha\' generates 7 bits.\n                                                                         : ... In instance top\n    val = 7\'d10 + $unsigned(val >>> 1);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2922063.v:53: Operator ADD expects 32 bits on the LHS, but LHS\'s CONST \'7\'ha\' generates 7 bits.\n                                                                         : ... In instance top\n    val = 7\'d10 + {val >>> 1};\n                ^\n%Error: Exiting due to 5 warning(s)\n'
module top;
  reg pass;
  integer val;

  initial begin
    pass = 1'b1;



    val = -1;
    val = 7'sd10 + (val >>> 1);
    if (val !== 9) begin
      $display("Failed ARS in signed context, got %d", val);
      pass = 1'b0;
    end



    val = -1;
    val = $signed(7'd10) + (val >>> 1);
    if (val !== 9) begin
      $display("Failed ARS in cast signed context, got %d", val);
      pass = 1'b0;
    end











    val = -1;
    val = 7'd10 + $signed(val >>> 1);
    if (val !== 9) begin
      $display("Failed ARS in $signed context, got %d", val);
      pass = 1'b0;
    end


    val = -1;
    val = 7'd10 + $unsigned(val >>> 1);
    if (val !== 9) begin
      $display("Failed ARS in $unsigned context, got %d", val);
      pass = 1'b0;
    end


    val = -1;
    val = 7'd10 + {val >>> 1};
    if (val !== 9) begin
      $display("Failed ARS in a concatenation context, got %d", val);
      pass = 1'b0;
    end
    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  integer val;

  initial begin
    pass = 1'b1;



    val = -1;
    val = 7'sd10 + (val >>> 1);
    if (val !== 9) begin
      $display("Failed ARS in signed context, got %d", val);
      pass = 1'b0;
    end



    val = -1;
    val = $signed(7'd10) + (val >>> 1);
    if (val !== 9) begin
      $display("Failed ARS in cast signed context, got %d", val);
      pass = 1'b0;
    end











    val = -1;
    val = 7'd10 + $signed(val >>> 1);
    if (val !== 9) begin
      $display("Failed ARS in $signed context, got %d", val);
      pass = 1'b0;
    end


    val = -1;
    val = 7'd10 + $unsigned(val >>> 1);
    if (val !== 9) begin
      $display("Failed ARS in $unsigned context, got %d", val);
      pass = 1'b0;
    end


    val = -1;
    val = 7'd10 + {val >>> 1};
    if (val !== 9) begin
      $display("Failed ARS in a concatenation context, got %d", val);
      pass = 1'b0;
    end
    if (pass) $display("PASSED");
  end
endmodule