data/full_repos/permissive/185628295/hdl/rescale_tb.v
 line:169: before: ";"
1: b'%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:18: Cannot find include file: rescale.v\n`include "rescale.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/rescale.v\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/rescale.v.v\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/rescale.v.sv\n             rescale.v\n             rescale.v.v\n             rescale.v.sv\n             obj_dir/rescale.v\n             obj_dir/rescale.v.v\n             obj_dir/rescale.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/185628295/hdl/rescale_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:31: Unsupported: event data types\n    event end_trigger;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/185628295/hdl/rescale_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    initial #1 display_header();\n            ^\n%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:150: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:163: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:180: syntax error, unexpected \'@\'\n        repeat(6) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:186: syntax error, unexpected \'@\'\n        repeat(2) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:188: syntax error, unexpected \'@\'\n        @(negedge clk)\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:215: syntax error, unexpected \'@\'\n        repeat(4) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:222: syntax error, unexpected \'@\'\n        repeat(2) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:224: syntax error, unexpected \'@\'\n        @(negedge clk)\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:248: syntax error, unexpected \'@\'\n        repeat(10) @(negedge clk);\n                   ^\n%Error: data/full_repos/permissive/185628295/hdl/rescale_tb.v:254: syntax error, unexpected ->\n        -> end_trigger;\n        ^~\n%Error: Exiting due to 12 error(s), 2 warning(s)\n'
module rescale_tb;




    reg clk;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam NUM_WIDTH    = 33;
    localparam NUM_POINT    = 16;

    localparam IMG_WIDTH    = 16;
    localparam IMG_POINT    = 8;



    function real num_f2r;
        input signed [NUM_WIDTH-1:0] value;

        begin
            num_f2r = value / ((1<<NUM_POINT) * 1.0);
        end
    endfunction


    function signed [NUM_WIDTH-1:0] num_r2f;
        input real value;

        begin
            num_r2f = value * (1<<NUM_POINT);
        end
    endfunction


    function real img_f2r;
        input signed [IMG_WIDTH-1:0] value;

        begin
            img_f2r = value / ((1<<IMG_POINT) * 1.0);
        end
    endfunction


    function signed [IMG_WIDTH-1:0] img_r2f;
        input real value;

        begin
            img_r2f = value * (1<<IMG_POINT);
        end
    endfunction


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'rescale' num width: %d, img width: %d",
            NUM_WIDTH, IMG_WIDTH);
    end
`endif




    reg  [7:0]              shift = 8;
    reg  [7:0]              head = 23;

    reg  [NUM_WIDTH-1:0]    up_data;
    wire [IMG_WIDTH-1:0]    dn_data;




    rescale #(
        .NUM_WIDTH  (NUM_WIDTH),
        .IMG_WIDTH  (IMG_WIDTH))
    uut (
        .clk        (clk),

        .shift      (shift),
        .head       (head),

        .up_data    (up_data),
        .dn_data    (dn_data)
    );




    task display_signals;
        $display(
            "%d",
            $time,

            "\t%b\t%f",
            up_data,
            num_f2r(up_data),

            "\t%b\t%f",
            dn_data,
            img_f2r(dn_data),
        );

    endtask

    task display_header;
        $display(
            "\t\ttime",

            "\t\t\tu_d as binary",
            "\t\tu_d",

            "\t\td_d as binary",
            "\t\td_d",
        );
    endtask






    initial begin

        clk = 0;

        up_data = 'b0;


        repeat(6) @(posedge clk);

`ifdef TB_VERBOSE
    $display("test less than");
`endif

        repeat(2) @(negedge clk);
        up_data <= 33'b1_1000_0000_0000_0000_0000_0000_0000_0000;
        @(negedge clk)

        up_data <= 33'b1_1111_1111_1111_1111_1111_1111_1111_1111;
        @(negedge clk)

        up_data <= num_r2f( -127.99999 );
        @(negedge clk)

        up_data <= num_r2f( -128.0 );
        @(negedge clk)

        up_data <= num_r2f( -128.00001 );
        @(negedge clk)

        up_data <= num_r2f( -256.0 );
        @(negedge clk)

        up_data <= num_r2f( -2328.00001 );
        @(negedge clk)

        up_data <= num_r2f( -43.0 );
        @(negedge clk)

        up_data <= num_r2f( 13.0 );
        @(negedge clk)

        up_data <= 'b0;
        repeat(4) @(negedge clk);


`ifdef TB_VERBOSE
    $display("test greater than");
`endif

        repeat(2) @(negedge clk);
        up_data <= 32'b0000_0000_0111_1111_1111_1111_0000_0000;
        @(negedge clk)

        up_data <= 32'b0000_0000_0111_1111_1111_1111_0000_0001;
        @(negedge clk)

        up_data <= num_r2f( 128.0 );
        @(negedge clk)

        up_data <= num_r2f( 128.00001 );
        @(negedge clk)

        up_data <= num_r2f( 118.0 );
        @(negedge clk)

        up_data <= num_r2f( 28.00001 );
        @(negedge clk)

        up_data <= num_r2f( 247.0 );
        @(negedge clk)

        up_data <= num_r2f( 1024.00001 );
        @(negedge clk)

        up_data <= 'b0;
        repeat(10) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule
module rescale_tb;





    reg clk;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam NUM_WIDTH    = 33;
    localparam NUM_POINT    = 16;

    localparam IMG_WIDTH    = 16;
    localparam IMG_POINT    = 8;



    function real num_f2r;
        input signed [NUM_WIDTH-1:0] value;

        begin
            num_f2r = value / ((1<<NUM_POINT) * 1.0);
        end
    endfunction


    function signed [NUM_WIDTH-1:0] num_r2f;
        input real value;

        begin
            num_r2f = value * (1<<NUM_POINT);
        end
    endfunction


    function real img_f2r;
        input signed [IMG_WIDTH-1:0] value;

        begin
            img_f2r = value / ((1<<IMG_POINT) * 1.0);
        end
    endfunction


    function signed [IMG_WIDTH-1:0] img_r2f;
        input real value;

        begin
            img_r2f = value * (1<<IMG_POINT);
        end
    endfunction


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'rescale' num width: %d, img width: %d",
            NUM_WIDTH, IMG_WIDTH);
    end
`endif




    reg  [7:0]              shift = 8;
    reg  [7:0]              head = 23;

    reg  [NUM_WIDTH-1:0]    up_data;
    wire [IMG_WIDTH-1:0]    dn_data;




    rescale #(
        .NUM_WIDTH  (NUM_WIDTH),
        .IMG_WIDTH  (IMG_WIDTH))
    uut (
        .clk        (clk),

        .shift      (shift),
        .head       (head),

        .up_data    (up_data),
        .dn_data    (dn_data)
    );




    task display_signals;
        $display(
            "%d",
            $time,

            "\t%b\t%f",
            up_data,
            num_f2r(up_data),

            "\t%b\t%f",
            dn_data,
            img_f2r(dn_data),
        );

    endtask

    task display_header;
        $display(
            "\t\ttime",

            "\t\t\tu_d as binary",
            "\t\tu_d",

            "\t\td_d as binary",
            "\t\td_d",
        );
    endtask






    initial begin

        clk = 0;

        up_data = 'b0;


        repeat(6) @(posedge clk);

`ifdef TB_VERBOSE
    $display("test less than");
`endif

        repeat(2) @(negedge clk);
        up_data <= 33'b1_1000_0000_0000_0000_0000_0000_0000_0000;
        @(negedge clk)

        up_data <= 33'b1_1111_1111_1111_1111_1111_1111_1111_1111;
        @(negedge clk)

        up_data <= num_r2f( -127.99999 );
        @(negedge clk)

        up_data <= num_r2f( -128.0 );
        @(negedge clk)

        up_data <= num_r2f( -128.00001 );
        @(negedge clk)

        up_data <= num_r2f( -256.0 );
        @(negedge clk)

        up_data <= num_r2f( -2328.00001 );
        @(negedge clk)

        up_data <= num_r2f( -43.0 );
        @(negedge clk)

        up_data <= num_r2f( 13.0 );
        @(negedge clk)

        up_data <= 'b0;
        repeat(4) @(negedge clk);


`ifdef TB_VERBOSE
    $display("test greater than");
`endif

        repeat(2) @(negedge clk);
        up_data <= 32'b0000_0000_0111_1111_1111_1111_0000_0000;
        @(negedge clk)

        up_data <= 32'b0000_0000_0111_1111_1111_1111_0000_0001;
        @(negedge clk)

        up_data <= num_r2f( 128.0 );
        @(negedge clk)

        up_data <= num_r2f( 128.00001 );
        @(negedge clk)

        up_data <= num_r2f( 118.0 );
        @(negedge clk)

        up_data <= num_r2f( 28.00001 );
        @(negedge clk)

        up_data <= num_r2f( 247.0 );
        @(negedge clk)

        up_data <= num_r2f( 1024.00001 );
        @(negedge clk)

        up_data <= 'b0;
        repeat(10) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule