data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v:1: Cannot find include file: p2s_cond.v\n`include "p2s_cond.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01,data/full_repos/permissive/129155059/p2s_cond.v\n             data/full_repos/permissive/129155059/proyecto-01,data/full_repos/permissive/129155059/p2s_cond.v.v\n             data/full_repos/permissive/129155059/proyecto-01,data/full_repos/permissive/129155059/p2s_cond.v.sv\n             p2s_cond.v\n             p2s_cond.v.v\n             p2s_cond.v.sv\n             obj_dir/p2s_cond.v\n             obj_dir/p2s_cond.v.v\n             obj_dir/p2s_cond.v.sv\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v:2: Cannot find include file: s2p_cond.v\n`include "s2p_cond.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v:3: Cannot find include file: mux_ctr_cond.v\n`include "mux_ctr_cond.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v:22: Define or directive not defined: \'`PUSH\'\n  wire [1:0]  MODO_RX = `PUSH;\n                        ^~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v:22: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  wire [1:0]  MODO_RX = `PUSH;\n                             ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v:23: Define or directive not defined: \'`RIGHT\'\n  wire        DIR_RX = `RIGHT;\n                       ^~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v:23: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  wire        DIR_RX = `RIGHT;\n                             ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v:29: Define or directive not defined: \'`PUSH\'\n  assign MODO_RX = `PUSH;\n                   ^~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v:29: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign MODO_RX = `PUSH;\n                        ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v:30: Define or directive not defined: \'`LEFT\'\n  assign DIR_RX = `LEFT;\n                  ^~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p_cond.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign DIR_RX = `LEFT;\n                       ^\n%Error: Exiting due to 11 error(s)\n'
module p2s_s2p_cond(  input         IN_CLK_2MHz,
                      input         IN_CLK_250KHz,
                      input   [7:0] IN_LANE3,
                      input   [7:0] IN_LANE2,
                      input   [7:0] IN_LANE1,
                      input   [7:0] IN_LANE0,
                      input         IN_ENB_TX,
                      input         IN_RESET_TX,
                      input         IN_VALID_TX,
                      input         IN_ENB_RX,
                      input         IN_RESET_RX,
                      output  [7:0] OUT_LANE3,
                      output  [7:0] OUT_LANE2,
                      output  [7:0] OUT_LANE1,
                      output  [7:0] OUT_LANE0
  );

  wire [1:0]  MODO_RX = `PUSH;
  wire        DIR_RX = `RIGHT;
  wire [3:0]  LANE;
  wire [1:0]  CLK_RX = {IN_CLK_250KHz, IN_CLK_2MHz};

  wire [2:0]  CTR_TX;

  assign MODO_RX = `PUSH;
  assign DIR_RX = `LEFT;

  mux_ctr_cond  ctr_tx_cond(  .valid_count  (IN_VALID_TX),
                              .CLK          (IN_CLK_2MHz),
                              .reset        (IN_RESET_TX),
                              .CTR          (CTR_TX)
                              );

  p2s_cond    low_tx_cond ( .IN_CLK_p2s   (IN_CLK_2MHz),
                            .IN_LANE3_p2s (IN_LANE3),
                            .IN_LANE2_p2s (IN_LANE2),
                            .IN_LANE1_p2s (IN_LANE1),
                            .IN_LANE0_p2s (IN_LANE0),
                            .IN_CTR_p2s   (CTR_TX),
                            .IN_ENB_p2s   (IN_ENB_TX),

                            .IN_VALID_BS  (IN_VALID_TX),
                            .OUT_LANE_p2s (LANE)
                            );

  s2p_cond    low_rx_cond ( .IN_CLK_s2p   (CLK_RX),
                            .IN_LANE_s2p  (LANE),
                            .IN_MODO_s2p  (MODO_RX),
                            .IN_DIR_s2p   (DIR_RX),
                            .IN_ENB_s2p   (IN_ENB_RX),
                            .IN_RESET_s2p (IN_RESET_RX),
                            .OUT_LANE3_s2p(OUT_LANE3),
                            .OUT_LANE2_s2p(OUT_LANE2),
                            .OUT_LANE1_s2p(OUT_LANE1),
                            .OUT_LANE0_s2p(OUT_LANE0)
                            );

endmodule
module p2s_s2p_cond(  input         IN_CLK_2MHz,
                      input         IN_CLK_250KHz,
                      input   [7:0] IN_LANE3,
                      input   [7:0] IN_LANE2,
                      input   [7:0] IN_LANE1,
                      input   [7:0] IN_LANE0,
                      input         IN_ENB_TX,
                      input         IN_RESET_TX,
                      input         IN_VALID_TX,
                      input         IN_ENB_RX,
                      input         IN_RESET_RX,
                      output  [7:0] OUT_LANE3,
                      output  [7:0] OUT_LANE2,
                      output  [7:0] OUT_LANE1,
                      output  [7:0] OUT_LANE0
  );


  wire [1:0]  MODO_RX = `PUSH;
  wire        DIR_RX = `RIGHT;
  wire [3:0]  LANE;
  wire [1:0]  CLK_RX = {IN_CLK_250KHz, IN_CLK_2MHz};

  wire [2:0]  CTR_TX;

  assign MODO_RX = `PUSH;
  assign DIR_RX = `LEFT;

  mux_ctr_cond  ctr_tx_cond(  .valid_count  (IN_VALID_TX),
                              .CLK          (IN_CLK_2MHz),
                              .reset        (IN_RESET_TX),
                              .CTR          (CTR_TX)
                              );

  p2s_cond    low_tx_cond ( .IN_CLK_p2s   (IN_CLK_2MHz),
                            .IN_LANE3_p2s (IN_LANE3),
                            .IN_LANE2_p2s (IN_LANE2),
                            .IN_LANE1_p2s (IN_LANE1),
                            .IN_LANE0_p2s (IN_LANE0),
                            .IN_CTR_p2s   (CTR_TX),
                            .IN_ENB_p2s   (IN_ENB_TX),

                            .IN_VALID_BS  (IN_VALID_TX),
                            .OUT_LANE_p2s (LANE)
                            );

  s2p_cond    low_rx_cond ( .IN_CLK_s2p   (CLK_RX),
                            .IN_LANE_s2p  (LANE),
                            .IN_MODO_s2p  (MODO_RX),
                            .IN_DIR_s2p   (DIR_RX),
                            .IN_ENB_s2p   (IN_ENB_RX),
                            .IN_RESET_s2p (IN_RESET_RX),
                            .OUT_LANE3_s2p(OUT_LANE3),
                            .OUT_LANE2_s2p(OUT_LANE2),
                            .OUT_LANE1_s2p(OUT_LANE1),
                            .OUT_LANE0_s2p(OUT_LANE0)
                            );

endmodule