data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Arithmetic_Circuits/m2014_q4j.v
data/verilator_xmls/3edffbf7-217f-49cf-8e47-cac0914e841e.xml
module FullAdder(
    input a, b, cin,
    output sum, cout
);
    assign {cout, sum} = a + b + cin;
endmodule
module FullAdder(
    input a, b, cin,
    output sum, cout
);

    assign {cout, sum} = a + b + cin;
endmodule