data/full_repos/permissive/106408053/verilog/trigger_adv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n              ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trigterm_range_bit (dataIn, clock, wrenb, din, dout, cin, cout);
input dataIn;
input clock, wrenb, din, cin;
output dout, cout;
SRLC16E ram0 (
  .A0(dataIn), .A1(1'b0), .A2(1'b0), .A3(1'b0), 
  .CLK(clock), .CE(wrenb), .D(din), .Q15(dout), .Q(hit));

MUXCY MUXCY_inst (.S(hit), .DI(dataIn), .CI(cin), .O(cout));
endmodule
module trigterm_range_bit (dataIn, clock, wrenb, din, dout, cin, cout);

input dataIn;
input clock, wrenb, din, cin;
output dout, cout;
SRLC16E ram0 (
  .A0(dataIn), .A1(1'b0), .A2(1'b0), .A3(1'b0), 
  .CLK(clock), .CE(wrenb), .D(din), .Q15(dout), .Q(hit));

MUXCY MUXCY_inst (.S(hit), .DI(dataIn), .CI(cin), .O(cout));
endmodule