data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Basics/Basics/andgate.v
data/verilator_xmls/93d15055-a689-49b8-b92d-b6d038a0534d.xml
module top_module( 
    input a, 
    input b, 
    output out );
    assign out = a&b;
endmodule
module top_module( 
    input a, 
    input b, 
    output out );

    assign out = a&b;
endmodule