data/full_repos/permissive/18921956/HardwareLab/Lab1/Lab1.v
data/verilator_xmls/5e815563-a6f6-4e54-90e4-99b50e71f5b1.xml
module Lab1(p, q, c_in, sum, c_out);
output sum, c_out;
input p, q, c_in;
wire t1, t2, t3;

xor(t1, p, q);
xor(sum, t1, c_in);

and(t2, p, q);
and(t3, c_in, t1);
or(c_out, t2, t3);

endmodule
module Lab1(p, q, c_in, sum, c_out);

output sum, c_out;
input p, q, c_in;
wire t1, t2, t3;

xor(t1, p, q);
xor(sum, t1, c_in);

and(t2, p, q);
and(t3, c_in, t1);
or(c_out, t2, t3);

endmodule