data/full_repos/permissive/119758565/RAM512.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/119758565/RAM512.v:22: Little bit endian vector: MSB < LSB of bit range: 0:15\n    input [0:15] data,\n          ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/119758565/RAM512.v:24: Little bit endian vector: MSB < LSB of bit range: 0:8\n    input [0:8] address,\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/119758565/RAM512.v:26: Little bit endian vector: MSB < LSB of bit range: 0:15\n    output [0:15] out\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/119758565/RAM512.v:29: Little bit endian vector: MSB < LSB of bit range: 0:15\n    reg [0:15] Data [0:511];\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/119758565/RAM512.v:30: Little bit endian vector: MSB < LSB of bit range: 0:15\n    reg [0:15] Out;\n        ^\n%Error: Exiting due to 5 warning(s)\n'
module RAM512(
    input [0:15] data,
    input load,
    input [0:8] address,
    input clk,
    output [0:15] out
    );
	 
    reg [0:15] Data [0:511];
    reg [0:15] Out;

    always @(posedge clk)
     begin
      if (load)
        begin
          Data[address] <= data;
        end
          Out <= Data[address];
     end

    assign out = Out;
endmodule
module RAM512(
    input [0:15] data,
    input load,
    input [0:8] address,
    input clk,
    output [0:15] out
    );

	 
    reg [0:15] Data [0:511];
    reg [0:15] Out;

    always @(posedge clk)
     begin
      if (load)
        begin
          Data[address] <= data;
        end
          Out <= Data[address];
     end

    assign out = Out;
endmodule