data/full_repos/permissive/138473269/rtl/mano_cp.v
1: b'%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:5: Cannot find include file: rtl/basic_params.v\n`include "rtl/basic_params.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v.v\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v.sv\n             rtl/basic_params.v\n             rtl/basic_params.v.v\n             rtl/basic_params.v.sv\n             obj_dir/rtl/basic_params.v\n             obj_dir/rtl/basic_params.v.v\n             obj_dir/rtl/basic_params.v.sv\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:45: Define or directive not defined: \'`buswidth\'\n output  [`buswidth-1:0] cs_bus_sel;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:46: Define or directive not defined: \'`funcwidth\'\n output  [`funcwidth-1:0] cs_alu_func;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:51: Define or directive not defined: \'`datawidth\'\n input [`datawidth-1:0] IR;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:52: Define or directive not defined: \'`datawidth\'\n input [`datawidth-1:0] AC;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:53: Define or directive not defined: \'`datawidth\'\n input [`datawidth-1:0] DR;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:61: Define or directive not defined: \'`buswidth\'\n reg [`buswidth-1:0] cs_bus_sel;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:62: Define or directive not defined: \'`funcwidth\'\n reg [`funcwidth-1:0] cs_alu_func;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:72: Define or directive not defined: \'`seqwidth\'\n wire [`seqwidth-1:0] T;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:139: Define or directive not defined: \'`T0\'\n    `T0:   \n    ^~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:139: syntax error, unexpected \':\', expecting endcase\n    `T0:   \n       ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:146: Define or directive not defined: \'`BUS_PC\'\n       cs_bus_sel=`BUS_PC;\n                  ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:146: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       cs_bus_sel=`BUS_PC;\n                         ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:151: Define or directive not defined: \'`BUS_PC\'\n       cs_bus_sel = `BUS_PC; \n                    ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:151: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       cs_bus_sel = `BUS_PC; \n                           ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:155: syntax error, unexpected else\n     else\n     ^~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:158: Define or directive not defined: \'`T1\'\n    `T1:   \n    ^~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:162: Define or directive not defined: \'`BUS_TR\'\n      cs_bus_sel = `BUS_TR;\n                   ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:170: Define or directive not defined: \'`BUS_MEM\'\n     cs_bus_sel = `BUS_MEM;\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:174: Define or directive not defined: \'`T2\'\n    `T2:   \n    ^~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:186: Define or directive not defined: \'`BUS_IR\'\n      cs_bus_sel = `BUS_IR; cs_i_ld = 1; cs_ar_ld = 1;\n                   ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:189: Define or directive not defined: \'`T3\'\n    `T3:\n    ^~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:201: Define or directive not defined: \'`BUS_MEM\'\n       cs_bus_sel = `BUS_MEM;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:211: Define or directive not defined: \'`CMA_FUNC\'\n        12\'b001000000000 : begin cs_alu_func = `CMA_FUNC; cs_ac_ld = 1;  seq_clr_t = 1; end    \n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:212: Define or directive not defined: \'`CME_FUNC\'\n        12\'b000100000000 : begin cs_alu_func = `CME_FUNC; cs_e_ld = 1;  seq_clr_t = 1; end    \n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:213: Define or directive not defined: \'`CIR_FUNC\'\n        12\'b000010000000 : begin cs_alu_func = `CIR_FUNC;  seq_clr_t = 1; end    \n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:214: Define or directive not defined: \'`CIL_FUNC\'\n        12\'b000001000000 : begin cs_alu_func = `CIL_FUNC;  seq_clr_t = 1; end    \n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:227: Define or directive not defined: \'`BUS_INP\'\n        12\'b000000000001 : begin cs_ac_ld = 1; cs_bus_sel = `BUS_INP; cs_fgi_clr = 1; seq_clr_t = 1; end    \n                                                            ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:228: Define or directive not defined: \'`BUS_AC\'\n        12\'b000000000010 : begin cs_outr_ld = 1; cs_bus_sel = `BUS_AC; cs_fgo_clr = 1; seq_clr_t = 1; end    \n                                                              ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:238: Define or directive not defined: \'`T4\'\n    `T4:\n    ^~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:239: Define or directive not defined: \'`BUS_MEM\'\n     if      (D0 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end   \n                                                         ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:240: Define or directive not defined: \'`BUS_MEM\'\n     else if (D1 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end   \n                                                         ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:241: Define or directive not defined: \'`BUS_MEM\'\n     else if (D2 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end   \n                                                         ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:242: Define or directive not defined: \'`BUS_AC\'\n     else if (D3 == 1) begin  cs_mem_wr = 1; cs_bus_sel = `BUS_AC; seq_clr_t = 1; end   \n                                                          ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:243: Define or directive not defined: \'`BUS_AR\'\n     else if (D4 == 1) begin  cs_pc_ld = 1; cs_bus_sel = `BUS_AR; seq_clr_t = 1; end   \n                                                         ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:244: Define or directive not defined: \'`BUS_PC\'\n     else if (D5 == 1) begin  cs_mem_wr = 1; cs_bus_sel = `BUS_PC; cs_ar_inc = 1; end   \n                                                          ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:245: Define or directive not defined: \'`BUS_MEM\'\n     else if (D6 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end   \n                                                         ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:246: Define or directive not defined: \'`T5\'\n    `T5:\n    ^~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:247: Define or directive not defined: \'`AND_FUNC\'\n     if      (D0 == 1) begin  cs_ac_ld = 1; cs_alu_func = `AND_FUNC; seq_clr_t = 1; end   \n                                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:248: Define or directive not defined: \'`ADD_FUNC\'\n     else if (D1 == 1) begin  cs_ac_ld = 1; cs_alu_func = `ADD_FUNC; seq_clr_t = 1; end   \n                                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:249: Define or directive not defined: \'`PASSDR_FUNC\'\n     else if (D2 == 1) begin  cs_ac_ld = 1; cs_alu_func = `PASSDR_FUNC; seq_clr_t = 1; end   \n                                                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:252: Define or directive not defined: \'`BUS_AR\'\n     else if (D5 == 1) begin  cs_pc_ld = 1; cs_bus_sel = `BUS_AR; seq_clr_t = 1; end   \n                                                         ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:254: Define or directive not defined: \'`T6\'\n    `T6:   \n    ^~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:257: Define or directive not defined: \'`BUS_DR\'\n     cs_bus_sel = `BUS_DR;\n                  ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:260: syntax error, unexpected \'=\', expecting IDENTIFIER\n      cs_pc_inc = 1;\n                ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:262: syntax error, unexpected \'=\', expecting IDENTIFIER\n     seq_clr_t = 1;\n               ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cp.v:264: Define or directive not defined: \'`T7\'\n    `T7:\n    ^~~\n%Error: Cannot continue\n'
module ctrlpath (	mrst, mclk, 

					cs_ar_clr, cs_ir_clr, cs_pc_clr, cs_dr_clr, cs_ac_clr, cs_tr_clr, cs_inpr_clr, cs_outr_clr,
					cs_ar_inc, cs_ir_inc, cs_pc_inc, cs_dr_inc, cs_ac_inc, cs_tr_inc, cs_inpr_inc, cs_outr_inc,
					cs_ar_ld, cs_ir_ld,   cs_pc_ld,  cs_dr_ld,  cs_ac_ld,  cs_tr_ld,  cs_inpr_ld,  cs_outr_ld,

					cs_s_ld, cs_s_clr, cs_e_ld, cs_e_clr, cs_i_ld, cs_i_clr, 
					cs_fgi_ld, cs_fgi_clr, cs_fgo_ld, cs_fgo_clr, cs_r_ld, cs_r_clr, cs_ien_ld, cs_ien_clr,

					cs_mem_rd, cs_mem_wr,

					cs_bus_sel, 

					cs_alu_func, cs_alub_sel,

					s_in, ien_in, fgi_in, fgo_in, r_in,

					cache_hit,

					IR, 
					AC,
					DR,
					E,
					I,
					FGI,
					FGO,
					S,
					R,
					IEN,
					b_signal
					);
	input mclk, mrst;
	output cs_ar_clr, cs_ir_clr, cs_pc_clr, cs_dr_clr, cs_ac_clr, cs_tr_clr, cs_inpr_clr, cs_outr_clr;
	output cs_ar_inc, cs_ir_inc, cs_pc_inc, cs_dr_inc, cs_ac_inc, cs_tr_inc, cs_inpr_inc, cs_outr_inc;
	output cs_ar_ld,  cs_ir_ld,  cs_pc_ld,  cs_dr_ld,  cs_ac_ld,  cs_tr_ld,  cs_inpr_ld,  cs_outr_ld;
	output cs_s_ld, cs_s_clr, cs_e_ld,   cs_e_clr,   cs_i_ld,   cs_i_clr;
	output cs_fgi_ld, cs_fgi_clr, cs_fgo_ld, cs_fgo_clr, cs_r_ld, cs_r_clr, cs_ien_ld, cs_ien_clr;
	output cs_mem_rd, cs_mem_wr;
	output 	[`buswidth-1:0] cs_bus_sel;
	output 	[`funcwidth-1:0] cs_alu_func;
	output cs_alub_sel;
	output s_in, ien_in, fgi_in, fgo_in, r_in;
	reg    s_in, ien_in, fgi_in, fgo_in, r_in;
	input cache_hit;
	input [`datawidth-1:0] IR;
	input [`datawidth-1:0] AC;
	input [`datawidth-1:0] DR;
	input  E;
	input  I;
	input  FGI;
	input  FGO;
	input  S;
	input  R;
	input  IEN;
	reg [`buswidth-1:0] cs_bus_sel;
	reg [`funcwidth-1:0] cs_alu_func;
	reg cs_ar_clr, cs_ir_clr, cs_pc_clr, cs_dr_clr, cs_ac_clr, cs_tr_clr, cs_inpr_clr, cs_outr_clr;
	reg cs_ar_inc, cs_ir_inc, cs_pc_inc, cs_dr_inc, cs_ac_inc, cs_tr_inc, cs_inpr_inc, cs_outr_inc;
	reg cs_ar_ld,  cs_ir_ld,  cs_pc_ld,  cs_dr_ld,  cs_ac_ld,  cs_tr_ld,  cs_inpr_ld,  cs_outr_ld;
	reg cs_e_ld,   cs_e_clr,   cs_i_ld,   cs_i_clr,  cs_fgi_ld, cs_fgi_clr,cs_fgo_ld, cs_fgo_clr,cs_s_ld, cs_s_clr, cs_r_ld, cs_r_clr, cs_ien_ld, cs_ien_clr;
	reg cs_mem_rd, cs_mem_wr;
	reg cs_alub_sel;

	wire seq_clr;
	reg  seq_clr_t;
	wire [`seqwidth-1:0] T;
	wire [11:0] op;
	
	wire D0, D1, D2, D3, D4, D5, D6, D7;
	reg VDD = 1'b1;


	input b_signal;
	
	initial s_in = 1'b1;
	
	cntr   SEQ  (.rst(seq_clr), .en(VDD), .clk(mclk), .t(T));
	dcd3x8 DCD  (.a(IR[14:12]), .D0(D0),    .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7));

	
	assign seq_clr = seq_clr_t | mrst;
	assign op = IR[11:0];

	always @(T, D0, D1, D2, D3, D4, D5, D6, D7, op, E, I, AC, DR, FGI, FGO, cache_hit)
	begin
		
			cs_ar_clr = 0;
			cs_ir_clr = 0;
			cs_pc_clr = 0;
			cs_dr_clr = 0;
			cs_ac_clr = 0;
			cs_tr_clr = 0;
			cs_inpr_clr = 0;
			cs_outr_clr = 0;
			cs_ar_inc = 0;
			cs_ir_inc = 0;
			cs_pc_inc = 0;
			cs_dr_inc = 0;
			cs_ac_inc = 0;
			cs_tr_inc = 0;
			cs_inpr_inc = 0;
			cs_outr_inc = 0;
			cs_ar_ld = 0;
			cs_pc_ld = 0;
			cs_dr_ld = 0;
			cs_ac_ld = 0;
			cs_tr_ld = 0;
			cs_tr_ld = 0;
			cs_tr_clr = 0;
			cs_inpr_ld = 0;
			cs_outr_ld = 0;
			cs_i_ld = 0;
			cs_i_clr = 0;
			cs_fgi_ld = 0;
			cs_fgi_clr = 0;
			cs_fgo_ld = 0;
			cs_fgo_clr = 0;
			cs_s_ld = 0;
			cs_s_clr = 0;
			cs_mem_wr = 0;
			cs_bus_sel = 3'b000;
			cs_alu_func = 3'b000;
			cs_alub_sel = 0;
			seq_clr_t = 0;
			r_in = 0;
			cs_r_ld = 0;
			cs_r_clr = 0;
			if (cache_hit == 1) begin
			VDD = 1'b1;
			cs_mem_rd = 0;
			cs_ir_ld = 0;
			case (T)
				`T0:
				begin 
					if (s_in == 1)
					begin
						if(R==1)
						begin
							cs_ar_clr=1;
							cs_bus_sel=`BUS_PC;
							cs_tr_ld=1;
						end
						else
						begin 
							cs_bus_sel = `BUS_PC; 
							cs_ar_ld = 1;
						end
					end
					else
						seq_clr_t = 1;
				end
				`T1:
				begin
					if (R==1)
					begin
						cs_bus_sel = `BUS_TR;
						cs_mem_wr = 1;
						cs_pc_clr = 1;
					end
					else
					begin
					cs_mem_rd = 1;
					cs_ir_ld = 1;
					cs_bus_sel = `BUS_MEM;
					cs_pc_inc = 1;
					end
				end
				`T2:
				begin
					if (R==1)
					begin
						cs_pc_inc=1;
						ien_in=0;
						r_in=0;
						seq_clr_t=1;
					end
					else
					begin
						if (b_signal == 0) cs_ir_ld = 1;
						cs_bus_sel = `BUS_IR; cs_i_ld = 1; cs_ar_ld = 1;
					end
				end
				`T3:
				begin
					if(IEN==1)
					begin
					  if(FGI==1 | FGO==1) cs_r_ld=1;
					end
					if (D7 == 0)
					begin
						if (I == 1 )
						begin
							cs_ar_ld = 1;
							cs_mem_rd = 1;
							cs_bus_sel = `BUS_MEM;
						end
					end
					else
					begin
						if (I == 0 )
						begin
							case (op)
								12'b100000000000 : begin cs_ac_clr = 1;  seq_clr_t = 1; end
								12'b010000000000 : begin cs_e_clr = 1;  seq_clr_t = 1; end
								12'b001000000000 : begin cs_alu_func = `CMA_FUNC; cs_ac_ld = 1;  seq_clr_t = 1; end
								12'b000100000000 : begin cs_alu_func = `CME_FUNC; cs_e_ld = 1;  seq_clr_t = 1; end
								12'b000010000000 : begin cs_alu_func = `CIR_FUNC;  seq_clr_t = 1; end
								12'b000001000000 : begin cs_alu_func = `CIL_FUNC;  seq_clr_t = 1; end
								12'b000000100000 : begin cs_ac_inc = 1;  seq_clr_t = 1; end
								12'b000000010000 : begin if(AC[15] == 0) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000001000 : begin if(AC[15] == 1) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000000100 : begin if(AC == 0) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000000010 : begin if(E == 0) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000000001 : begin s_in = 1'b0; cs_s_ld=1; seq_clr_t = 1; end
								default  		 : begin  end
							endcase
						end
						else
						begin
							case (op)
								12'b000000000001 : begin cs_ac_ld = 1; cs_bus_sel = `BUS_INP; cs_fgi_clr = 1; seq_clr_t = 1; end
								12'b000000000010 : begin cs_outr_ld = 1; cs_bus_sel = `BUS_AC; cs_fgo_clr = 1; seq_clr_t = 1; end
								12'b000000000100 : begin if (FGI == 1) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000001000 : begin if (FGO == 1) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000010000 : begin ien_in = 1'b1; cs_ien_ld = 1; seq_clr_t = 1; end
								12'b000000100000 : begin cs_ien_clr = 1; seq_clr_t = 1; end
								default  		 : begin  end
							endcase                
						end
					end
				end
				`T4:
					if      (D0 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end
					else if (D1 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end
					else if (D2 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end
					else if (D3 == 1) begin  cs_mem_wr = 1; cs_bus_sel = `BUS_AC; seq_clr_t = 1; end
					else if (D4 == 1) begin  cs_pc_ld = 1; cs_bus_sel = `BUS_AR; seq_clr_t = 1; end
					else if (D5 == 1) begin  cs_mem_wr = 1; cs_bus_sel = `BUS_PC; cs_ar_inc = 1; end
					else if (D6 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end
				`T5:
					if      (D0 == 1) begin  cs_ac_ld = 1; cs_alu_func = `AND_FUNC; seq_clr_t = 1; end
					else if (D1 == 1) begin  cs_ac_ld = 1; cs_alu_func = `ADD_FUNC; seq_clr_t = 1; end
					else if (D2 == 1) begin  cs_ac_ld = 1; cs_alu_func = `PASSDR_FUNC; seq_clr_t = 1; end
					else if (D3 == 1) begin  end
					else if (D4 == 1) begin  end
					else if (D5 == 1) begin  cs_pc_ld = 1; cs_bus_sel = `BUS_AR; seq_clr_t = 1; end
					else if (D6 == 1) begin  cs_dr_inc = 1; end
				`T6:
				begin
					cs_mem_wr = 1;
					cs_bus_sel = `BUS_DR;
					if (DR == 0)
					begin
						cs_pc_inc = 1;
					end
					seq_clr_t = 1;
				end
				`T7:
				begin
					seq_clr_t = 1;
				end
				default:
				cs_ir_ld = 1;
			endcase
		end
		else 
		begin
			VDD = 1'b0;

		end
	end
endmodule
module ctrlpath (	mrst, mclk, 

					cs_ar_clr, cs_ir_clr, cs_pc_clr, cs_dr_clr, cs_ac_clr, cs_tr_clr, cs_inpr_clr, cs_outr_clr,
					cs_ar_inc, cs_ir_inc, cs_pc_inc, cs_dr_inc, cs_ac_inc, cs_tr_inc, cs_inpr_inc, cs_outr_inc,
					cs_ar_ld, cs_ir_ld,   cs_pc_ld,  cs_dr_ld,  cs_ac_ld,  cs_tr_ld,  cs_inpr_ld,  cs_outr_ld,

					cs_s_ld, cs_s_clr, cs_e_ld, cs_e_clr, cs_i_ld, cs_i_clr, 
					cs_fgi_ld, cs_fgi_clr, cs_fgo_ld, cs_fgo_clr, cs_r_ld, cs_r_clr, cs_ien_ld, cs_ien_clr,

					cs_mem_rd, cs_mem_wr,

					cs_bus_sel, 

					cs_alu_func, cs_alub_sel,

					s_in, ien_in, fgi_in, fgo_in, r_in,

					cache_hit,

					IR, 
					AC,
					DR,
					E,
					I,
					FGI,
					FGO,
					S,
					R,
					IEN,
					b_signal
					);

	input mclk, mrst;
	output cs_ar_clr, cs_ir_clr, cs_pc_clr, cs_dr_clr, cs_ac_clr, cs_tr_clr, cs_inpr_clr, cs_outr_clr;
	output cs_ar_inc, cs_ir_inc, cs_pc_inc, cs_dr_inc, cs_ac_inc, cs_tr_inc, cs_inpr_inc, cs_outr_inc;
	output cs_ar_ld,  cs_ir_ld,  cs_pc_ld,  cs_dr_ld,  cs_ac_ld,  cs_tr_ld,  cs_inpr_ld,  cs_outr_ld;
	output cs_s_ld, cs_s_clr, cs_e_ld,   cs_e_clr,   cs_i_ld,   cs_i_clr;
	output cs_fgi_ld, cs_fgi_clr, cs_fgo_ld, cs_fgo_clr, cs_r_ld, cs_r_clr, cs_ien_ld, cs_ien_clr;
	output cs_mem_rd, cs_mem_wr;
	output 	[`buswidth-1:0] cs_bus_sel;
	output 	[`funcwidth-1:0] cs_alu_func;
	output cs_alub_sel;
	output s_in, ien_in, fgi_in, fgo_in, r_in;
	reg    s_in, ien_in, fgi_in, fgo_in, r_in;
	input cache_hit;
	input [`datawidth-1:0] IR;
	input [`datawidth-1:0] AC;
	input [`datawidth-1:0] DR;
	input  E;
	input  I;
	input  FGI;
	input  FGO;
	input  S;
	input  R;
	input  IEN;
	reg [`buswidth-1:0] cs_bus_sel;
	reg [`funcwidth-1:0] cs_alu_func;
	reg cs_ar_clr, cs_ir_clr, cs_pc_clr, cs_dr_clr, cs_ac_clr, cs_tr_clr, cs_inpr_clr, cs_outr_clr;
	reg cs_ar_inc, cs_ir_inc, cs_pc_inc, cs_dr_inc, cs_ac_inc, cs_tr_inc, cs_inpr_inc, cs_outr_inc;
	reg cs_ar_ld,  cs_ir_ld,  cs_pc_ld,  cs_dr_ld,  cs_ac_ld,  cs_tr_ld,  cs_inpr_ld,  cs_outr_ld;
	reg cs_e_ld,   cs_e_clr,   cs_i_ld,   cs_i_clr,  cs_fgi_ld, cs_fgi_clr,cs_fgo_ld, cs_fgo_clr,cs_s_ld, cs_s_clr, cs_r_ld, cs_r_clr, cs_ien_ld, cs_ien_clr;
	reg cs_mem_rd, cs_mem_wr;
	reg cs_alub_sel;

	wire seq_clr;
	reg  seq_clr_t;
	wire [`seqwidth-1:0] T;
	wire [11:0] op;
	
	wire D0, D1, D2, D3, D4, D5, D6, D7;
	reg VDD = 1'b1;


	input b_signal;
	
	initial s_in = 1'b1;
	
	cntr   SEQ  (.rst(seq_clr), .en(VDD), .clk(mclk), .t(T));
	dcd3x8 DCD  (.a(IR[14:12]), .D0(D0),    .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7));

	
	assign seq_clr = seq_clr_t | mrst;
	assign op = IR[11:0];

	always @(T, D0, D1, D2, D3, D4, D5, D6, D7, op, E, I, AC, DR, FGI, FGO, cache_hit)
	begin
		
			cs_ar_clr = 0;
			cs_ir_clr = 0;
			cs_pc_clr = 0;
			cs_dr_clr = 0;
			cs_ac_clr = 0;
			cs_tr_clr = 0;
			cs_inpr_clr = 0;
			cs_outr_clr = 0;
			cs_ar_inc = 0;
			cs_ir_inc = 0;
			cs_pc_inc = 0;
			cs_dr_inc = 0;
			cs_ac_inc = 0;
			cs_tr_inc = 0;
			cs_inpr_inc = 0;
			cs_outr_inc = 0;
			cs_ar_ld = 0;
			cs_pc_ld = 0;
			cs_dr_ld = 0;
			cs_ac_ld = 0;
			cs_tr_ld = 0;
			cs_tr_ld = 0;
			cs_tr_clr = 0;
			cs_inpr_ld = 0;
			cs_outr_ld = 0;
			cs_i_ld = 0;
			cs_i_clr = 0;
			cs_fgi_ld = 0;
			cs_fgi_clr = 0;
			cs_fgo_ld = 0;
			cs_fgo_clr = 0;
			cs_s_ld = 0;
			cs_s_clr = 0;
			cs_mem_wr = 0;
			cs_bus_sel = 3'b000;
			cs_alu_func = 3'b000;
			cs_alub_sel = 0;
			seq_clr_t = 0;
			r_in = 0;
			cs_r_ld = 0;
			cs_r_clr = 0;
			if (cache_hit == 1) begin
			VDD = 1'b1;
			cs_mem_rd = 0;
			cs_ir_ld = 0;
			case (T)
				`T0:
				begin 
					if (s_in == 1)
					begin
						if(R==1)
						begin
							cs_ar_clr=1;
							cs_bus_sel=`BUS_PC;
							cs_tr_ld=1;
						end
						else
						begin 
							cs_bus_sel = `BUS_PC; 
							cs_ar_ld = 1;
						end
					end
					else
						seq_clr_t = 1;
				end
				`T1:
				begin
					if (R==1)
					begin
						cs_bus_sel = `BUS_TR;
						cs_mem_wr = 1;
						cs_pc_clr = 1;
					end
					else
					begin
					cs_mem_rd = 1;
					cs_ir_ld = 1;
					cs_bus_sel = `BUS_MEM;
					cs_pc_inc = 1;
					end
				end
				`T2:
				begin
					if (R==1)
					begin
						cs_pc_inc=1;
						ien_in=0;
						r_in=0;
						seq_clr_t=1;
					end
					else
					begin
						if (b_signal == 0) cs_ir_ld = 1;
						cs_bus_sel = `BUS_IR; cs_i_ld = 1; cs_ar_ld = 1;
					end
				end
				`T3:
				begin
					if(IEN==1)
					begin
					  if(FGI==1 | FGO==1) cs_r_ld=1;
					end
					if (D7 == 0)
					begin
						if (I == 1 )
						begin
							cs_ar_ld = 1;
							cs_mem_rd = 1;
							cs_bus_sel = `BUS_MEM;
						end
					end
					else
					begin
						if (I == 0 )
						begin
							case (op)
								12'b100000000000 : begin cs_ac_clr = 1;  seq_clr_t = 1; end
								12'b010000000000 : begin cs_e_clr = 1;  seq_clr_t = 1; end
								12'b001000000000 : begin cs_alu_func = `CMA_FUNC; cs_ac_ld = 1;  seq_clr_t = 1; end
								12'b000100000000 : begin cs_alu_func = `CME_FUNC; cs_e_ld = 1;  seq_clr_t = 1; end
								12'b000010000000 : begin cs_alu_func = `CIR_FUNC;  seq_clr_t = 1; end
								12'b000001000000 : begin cs_alu_func = `CIL_FUNC;  seq_clr_t = 1; end
								12'b000000100000 : begin cs_ac_inc = 1;  seq_clr_t = 1; end
								12'b000000010000 : begin if(AC[15] == 0) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000001000 : begin if(AC[15] == 1) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000000100 : begin if(AC == 0) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000000010 : begin if(E == 0) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000000001 : begin s_in = 1'b0; cs_s_ld=1; seq_clr_t = 1; end
								default  		 : begin  end
							endcase
						end
						else
						begin
							case (op)
								12'b000000000001 : begin cs_ac_ld = 1; cs_bus_sel = `BUS_INP; cs_fgi_clr = 1; seq_clr_t = 1; end
								12'b000000000010 : begin cs_outr_ld = 1; cs_bus_sel = `BUS_AC; cs_fgo_clr = 1; seq_clr_t = 1; end
								12'b000000000100 : begin if (FGI == 1) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000001000 : begin if (FGO == 1) begin cs_pc_inc = 1; end seq_clr_t = 1; end
								12'b000000010000 : begin ien_in = 1'b1; cs_ien_ld = 1; seq_clr_t = 1; end
								12'b000000100000 : begin cs_ien_clr = 1; seq_clr_t = 1; end
								default  		 : begin  end
							endcase                
						end
					end
				end
				`T4:
					if      (D0 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end
					else if (D1 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end
					else if (D2 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end
					else if (D3 == 1) begin  cs_mem_wr = 1; cs_bus_sel = `BUS_AC; seq_clr_t = 1; end
					else if (D4 == 1) begin  cs_pc_ld = 1; cs_bus_sel = `BUS_AR; seq_clr_t = 1; end
					else if (D5 == 1) begin  cs_mem_wr = 1; cs_bus_sel = `BUS_PC; cs_ar_inc = 1; end
					else if (D6 == 1) begin  cs_dr_ld = 1; cs_bus_sel = `BUS_MEM; end
				`T5:
					if      (D0 == 1) begin  cs_ac_ld = 1; cs_alu_func = `AND_FUNC; seq_clr_t = 1; end
					else if (D1 == 1) begin  cs_ac_ld = 1; cs_alu_func = `ADD_FUNC; seq_clr_t = 1; end
					else if (D2 == 1) begin  cs_ac_ld = 1; cs_alu_func = `PASSDR_FUNC; seq_clr_t = 1; end
					else if (D3 == 1) begin  end
					else if (D4 == 1) begin  end
					else if (D5 == 1) begin  cs_pc_ld = 1; cs_bus_sel = `BUS_AR; seq_clr_t = 1; end
					else if (D6 == 1) begin  cs_dr_inc = 1; end
				`T6:
				begin
					cs_mem_wr = 1;
					cs_bus_sel = `BUS_DR;
					if (DR == 0)
					begin
						cs_pc_inc = 1;
					end
					seq_clr_t = 1;
				end
				`T7:
				begin
					seq_clr_t = 1;
				end
				default:
				cs_ir_ld = 1;
			endcase
		end
		else 
		begin
			VDD = 1'b0;

		end
	end
endmodule