data/full_repos/permissive/128426084/src/sources_1/new/draw_background.v
1: b'%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_background.v:22: Cannot find include file: verilog_macro_bus.vh\n`include "verilog_macro_bus.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.v\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.sv\n             verilog_macro_bus.vh\n             verilog_macro_bus.vh.v\n             verilog_macro_bus.vh.sv\n             obj_dir/verilog_macro_bus.vh\n             obj_dir/verilog_macro_bus.vh.v\n             obj_dir/verilog_macro_bus.vh.sv\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_background.v:25: Define or directive not defined: \'`VGA_BUS_SIZE\'\n    input wire [`VGA_BUS_SIZE-1:0] vga_in,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_background.v:27: Define or directive not defined: \'`VGA_BUS_SIZE\'\n    output wire [`VGA_BUS_SIZE-1:0] vga_out,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_background.v:32: Define or directive not defined: \'`VGA_SPLIT_INPUT\'\n    `VGA_SPLIT_INPUT(vga_in)\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_background.v:32: syntax error, unexpected \'(\'\n    `VGA_SPLIT_INPUT(vga_in)\n                     ^~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_background.v:33: Define or directive not defined: \'`VGA_OUT_WIRE\'\n    `VGA_OUT_WIRE\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_background.v:34: Define or directive not defined: \'`VGA_MERGE_AT_OUTPUT\'\n    `VGA_MERGE_AT_OUTPUT(vga_out)\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module draw_background(
    input wire [`VGA_BUS_SIZE-1:0] vga_in,
    input [3:0] rgb,
    output wire [`VGA_BUS_SIZE-1:0] vga_out,
    output wire [18:0] address
    );
  

    `VGA_SPLIT_INPUT(vga_in)
    `VGA_OUT_WIRE
    `VGA_MERGE_AT_OUTPUT(vga_out)
  

  

      assign hsync_out = hsync_in;
      assign vsync_out = vsync_in;
      assign hblnk_out = hblnk_in;
      assign vblnk_out = vblnk_in;
      assign hcount_out = hcount_in;
      assign vcount_out = vcount_in;
      
      assign rgb_out = ((hblnk_in == 0)&&(vblnk_in == 0))? ((rgb_in == 12'hfff)?12'hfff:({rgb,rgb,rgb})) :  0;

assign address = hcount_in[10:1] + vcount_in[10:1]*400;
endmodule
module draw_background(
    input wire [`VGA_BUS_SIZE-1:0] vga_in,
    input [3:0] rgb,
    output wire [`VGA_BUS_SIZE-1:0] vga_out,
    output wire [18:0] address
    );

  

    `VGA_SPLIT_INPUT(vga_in)
    `VGA_OUT_WIRE
    `VGA_MERGE_AT_OUTPUT(vga_out)
  

  

      assign hsync_out = hsync_in;
      assign vsync_out = vsync_in;
      assign hblnk_out = hblnk_in;
      assign vblnk_out = vblnk_in;
      assign hcount_out = hcount_in;
      assign vcount_out = vcount_in;
      
      assign rgb_out = ((hblnk_in == 0)&&(vblnk_in == 0))? ((rgb_in == 12'hfff)?12'hfff:({rgb,rgb,rgb})) :  0;

assign address = hcount_in[10:1] + vcount_in[10:1]*400;
endmodule