data/full_repos/permissive/106408053/verilog/trigger_adv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n              ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram_dword (clock, addr, wrenb, wrdata, rddata);
input clock;
input [3:0] addr;
input wrenb;
input [31:0] wrdata;
output [31:0] rddata;
ram_byte byte0 (clock, addr, wrenb, wrdata[7:0], rddata[7:0]);
ram_byte byte1 (clock, addr, wrenb, wrdata[15:8], rddata[15:8]);
ram_byte byte2 (clock, addr, wrenb, wrdata[23:16], rddata[23:16]);
ram_byte byte3 (clock, addr, wrenb, wrdata[31:24], rddata[31:24]);
endmodule
module ram_dword (clock, addr, wrenb, wrdata, rddata);

input clock;
input [3:0] addr;
input wrenb;
input [31:0] wrdata;
output [31:0] rddata;
ram_byte byte0 (clock, addr, wrenb, wrdata[7:0], rddata[7:0]);
ram_byte byte1 (clock, addr, wrenb, wrdata[15:8], rddata[15:8]);
ram_byte byte2 (clock, addr, wrenb, wrdata[23:16], rddata[23:16]);
ram_byte byte3 (clock, addr, wrenb, wrdata[31:24], rddata[31:24]);
endmodule