data/full_repos/permissive/165846232/components/Ram/Ram.v
data/verilator_xmls/18565363-1184-4e7b-8a75-fe281867c690.xml
module RAM #(
    parameter DATA_WIDTH = 8,
    parameter ADDR_WIDTH = 8
) (
    input wire Clk,
    input wire [ADDR_WIDTH-1:0] Addr,
    input wire Write,
    input wire [DATA_WIDTH-1:0] Input,
    output reg [DATA_WIDTH-1:0] Output
);

    reg [DATA_WIDTH-1:0] Memory [0:(1<<ADDR_WIDTH)-1]; 
    
    always @(posedge Clk)
    begin
        if(Write)
            begin
                Memory[Addr] <= Input;
            end
        else
            begin
                Output <= Memory[Addr];
            end     
    end
endmodule
module RAM #(
    parameter DATA_WIDTH = 8,
    parameter ADDR_WIDTH = 8
) (
    input wire Clk,
    input wire [ADDR_WIDTH-1:0] Addr,
    input wire Write,
    input wire [DATA_WIDTH-1:0] Input,
    output reg [DATA_WIDTH-1:0] Output
);


    reg [DATA_WIDTH-1:0] Memory [0:(1<<ADDR_WIDTH)-1]; 
    
    always @(posedge Clk)
    begin
        if(Write)
            begin
                Memory[Addr] <= Input;
            end
        else
            begin
                Output <= Memory[Addr];
            end     
    end
endmodule