data/full_repos/permissive/196070799/src/Randomizer.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/7ddc76cb-b68d-4ff2-95fa-f70446f45723.xml
module Randomizer
(
  IN_CLOCK,
  IN_RESET_N,
  IN_START,
  OUT_RESULT
);

input                           IN_CLOCK                                                                            ;
input                           IN_RESET_N                                                                          ;
input                           IN_START                                                                            ;
output          [3:0]           OUT_RESULT                                                                          ;


reg             [17:0]          counter_r                                                                           ;
reg             [17:0]          seed_r                                                                              ;
reg             [17:0]          current_r                                                                           ;


always @ (posedge IN_CLOCK) begin
  if (!IN_RESET_N) begin
    counter_r                                       <= 18'b100110101011010111                                       ;
    seed_r                                          <= 18'b000000000000000000                                       ;
    current_r                                       <= 18'b000000000000000000                                       ;
  end
  else begin
    if (IN_START == 1'b1) begin
      counter_r                                     <= {counter_r[15:0], counter_r[17:16] ^ counter_r[10:9]}        ;
      seed_r                                        <= counter_r                                                    ;
      current_r                                     <= seed_r                                                       ;
    end
    else begin
      counter_r                                     <= {counter_r[15:0], counter_r[17:16] ^ counter_r[10:9]}        ;
      seed_r                                        <= counter_r                                                    ;
      current_r                                     <= {current_r[15:0], current_r[17:16] ^ current_r[10:9]}        ;
    end
  end
end

assign OUT_RESULT                                   = 4'b1 << current_r[1:0]                                        ;

endmodule
module Randomizer
(
  IN_CLOCK,
  IN_RESET_N,
  IN_START,
  OUT_RESULT
);


input                           IN_CLOCK                                                                            ;
input                           IN_RESET_N                                                                          ;
input                           IN_START                                                                            ;
output          [3:0]           OUT_RESULT                                                                          ;


reg             [17:0]          counter_r                                                                           ;
reg             [17:0]          seed_r                                                                              ;
reg             [17:0]          current_r                                                                           ;


always @ (posedge IN_CLOCK) begin
  if (!IN_RESET_N) begin
    counter_r                                       <= 18'b100110101011010111                                       ;
    seed_r                                          <= 18'b000000000000000000                                       ;
    current_r                                       <= 18'b000000000000000000                                       ;
  end
  else begin
    if (IN_START == 1'b1) begin
      counter_r                                     <= {counter_r[15:0], counter_r[17:16] ^ counter_r[10:9]}        ;
      seed_r                                        <= counter_r                                                    ;
      current_r                                     <= seed_r                                                       ;
    end
    else begin
      counter_r                                     <= {counter_r[15:0], counter_r[17:16] ^ counter_r[10:9]}        ;
      seed_r                                        <= counter_r                                                    ;
      current_r                                     <= {current_r[15:0], current_r[17:16] ^ current_r[10:9]}        ;
    end
  end
end

assign OUT_RESULT                                   = 4'b1 << current_r[1:0]                                        ;

endmodule