data/full_repos/permissive/212763527/school_project/16_Mealy/sources/mealy.v
data/verilator_xmls/39e249f2-2e0a-4a01-9302-dfc86d8a4434.xml
module mealy(input clk,
             input rst,
             input X,
             output reg Y);

parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b11, S3 = 2'b10;

reg [1:0] curr_state = S0;

always @(posedge clk) begin
    Y <= 1'b0;
    if (rst)
        curr_state <= S0;
    else
        case (curr_state)
            S0: if (X==0)
                    curr_state <= S0;
                else
                    curr_state <= S1; 
            S1: if (X==0)
                    curr_state <= S2;
                else
                    curr_state <= S1;
            S2: if (X==0)
                    curr_state <= S0;
                else
                    curr_state <= S3;
            S3: if (X==0)
                    curr_state <= S2;
                else begin
                    curr_state <= S1;
                    Y <= 1'b1;
                end
            default: curr_state <= S0;
        endcase
end
    
endmodule
module mealy(input clk,
             input rst,
             input X,
             output reg Y);


parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b11, S3 = 2'b10;

reg [1:0] curr_state = S0;

always @(posedge clk) begin
    Y <= 1'b0;
    if (rst)
        curr_state <= S0;
    else
        case (curr_state)
            S0: if (X==0)
                    curr_state <= S0;
                else
                    curr_state <= S1; 
            S1: if (X==0)
                    curr_state <= S2;
                else
                    curr_state <= S1;
            S2: if (X==0)
                    curr_state <= S0;
                else
                    curr_state <= S3;
            S3: if (X==0)
                    curr_state <= S2;
                else begin
                    curr_state <= S1;
                    Y <= 1'b1;
                end
            default: curr_state <= S0;
        endcase
end
    
endmodule