data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v
None: at end of input
1: b'%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:20: Cannot find include file: RV2T_common.vh\n`include "RV2T_common.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source,data/full_repos/permissive/158824477/RV2T_common.vh\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source,data/full_repos/permissive/158824477/RV2T_common.vh.v\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source,data/full_repos/permissive/158824477/RV2T_common.vh.sv\n             RV2T_common.vh\n             RV2T_common.vh.v\n             RV2T_common.vh.sv\n             obj_dir/RV2T_common.vh\n             obj_dir/RV2T_common.vh.v\n             obj_dir/RV2T_common.vh.sv\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:42: Define or directive not defined: \'`MEM_ADDR_BITS\'\n        input   wire  [`MEM_ADDR_BITS - 1 : 0]                  ocd_rw_addr,\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:43: Define or directive not defined: \'`XLEN\'\n        input   wire  [`XLEN - 1 : 0]                           ocd_write_word,\n                       ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:46: Define or directive not defined: \'`XLEN\'\n        output  wire  [`XLEN - 1 : 0]                           ocd_mem_word_out,        \n                       ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:48: Define or directive not defined: \'`REG_ADDR_BITS\'\n        input   wire  [`REG_ADDR_BITS - 1 : 0]                  ocd_reg_read_addr,\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:50: Define or directive not defined: \'`REG_ADDR_BITS\'\n        input   wire  [`REG_ADDR_BITS - 1 : 0]                  ocd_reg_write_addr,\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:51: Define or directive not defined: \'`XLEN\'\n        input   wire  [`XLEN - 1 : 0]                           ocd_reg_write_data,\n                       ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:62: Define or directive not defined: \'`PC_BITWIDTH\'\n        input   wire  [`PC_BITWIDTH - 1 : 0]                    start_address,\n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:66: Define or directive not defined: \'`XLEN\'\n        output  wire  [`XLEN - 1 : 0]                           peek_pc,\n                       ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:67: Define or directive not defined: \'`XLEN\'\n        output  wire  [`XLEN - 1 : 0]                           peek_ir,\n                       ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:69: Define or directive not defined: \'`XLEN_BYTES\'\n        output  wire  [`XLEN_BYTES - 1 : 0]                     peek_mem_write_en,\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:70: Define or directive not defined: \'`XLEN\'\n        output  wire  [`XLEN - 1 : 0]                           peek_mem_write_data,\n                       ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:71: Define or directive not defined: \'`MEM_ADDR_BITS\'\n        output  wire [`MEM_ADDR_BITS - 1 : 0]                   peek_mem_addr\n                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:80: Define or directive not defined: \'`MEM_ADDR_BITS\'\n        wire [`MEM_ADDR_BITS - 1 : 0]                           mem_addr;\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:81: Define or directive not defined: \'`MEM_ADDR_BITS\'\n        reg  [`MEM_ADDR_BITS - 1 : 0]                           mem_addr_d1;\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:83: Define or directive not defined: \'`XLEN_BYTES\'\n        wire [`XLEN_BYTES - 1 : 0]                              mem_write_en;\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:84: Define or directive not defined: \'`XLEN\'\n        wire [`XLEN - 1 : 0]                                    mem_write_data;\n              ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:85: Define or directive not defined: \'`XLEN\'\n        wire [`XLEN - 1 : 0]                                    mem_read_data;\n              ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:136: Define or directive not defined: \'`MEM_ADDR_BITS\'\n            single_port_ram #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_high_i (\n                                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:143: Define or directive not defined: \'`MEM_ADDR_BITS\'\n            single_port_ram #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_low_i (\n                                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:185: Define or directive not defined: \'`UART_STABLE_COUNT\'\n        UART_TX #(.STABLE_TIME(`UART_STABLE_COUNT), .BAUD_PERIOD_BITS(`UART_TX_BAUD_PERIOD_BITS)) UART_TX_i (\n                               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:185: Define or directive not defined: \'`UART_TX_BAUD_PERIOD_BITS\'\n        UART_TX #(.STABLE_TIME(`UART_STABLE_COUNT), .BAUD_PERIOD_BITS(`UART_TX_BAUD_PERIOD_BITS)) UART_TX_i (\n                                                                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/source/PulseRain_RV2T_MCU.v:191: Define or directive not defined: \'`UART_TX_BAUD_PERIOD\'\n            .baud_rate_period_m1 (`UART_TX_BAUD_PERIOD - 1),\n                                  ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 23 error(s)\n'
module PulseRain_RV2T_MCU (




        input   wire                                            clk,                          
        input   wire                                            reset_n,                      
        input   wire                                            sync_reset,

    





        input   wire                                            ocd_read_enable,
        input   wire                                            ocd_write_enable,
        
        input   wire  [`MEM_ADDR_BITS - 1 : 0]                  ocd_rw_addr,
        input   wire  [`XLEN - 1 : 0]                           ocd_write_word,
        
        output  wire                                            ocd_mem_enable_out,
        output  wire  [`XLEN - 1 : 0]                           ocd_mem_word_out,        
        
        input   wire  [`REG_ADDR_BITS - 1 : 0]                  ocd_reg_read_addr,
        input   wire                                            ocd_reg_we,
        input   wire  [`REG_ADDR_BITS - 1 : 0]                  ocd_reg_write_addr,
        input   wire  [`XLEN - 1 : 0]                           ocd_reg_write_data,




        output  wire                                            TXD,
        



        input   wire                                            start,
        input   wire  [`PC_BITWIDTH - 1 : 0]                    start_address,
        
        output  wire                                            processor_paused,

        output  wire  [`XLEN - 1 : 0]                           peek_pc,
        output  wire  [`XLEN - 1 : 0]                           peek_ir,
        
        output  wire  [`XLEN_BYTES - 1 : 0]                     peek_mem_write_en,
        output  wire  [`XLEN - 1 : 0]                           peek_mem_write_data,
        output  wire [`MEM_ADDR_BITS - 1 : 0]                   peek_mem_addr
        
);
     
    



 
        wire [`MEM_ADDR_BITS - 1 : 0]                           mem_addr;
        reg  [`MEM_ADDR_BITS - 1 : 0]                           mem_addr_d1;
        
        wire [`XLEN_BYTES - 1 : 0]                              mem_write_en;
        wire [`XLEN - 1 : 0]                                    mem_write_data;
        wire [`XLEN - 1 : 0]                                    mem_read_data;
            
        wire [15 : 0]                                           dout_high;
        wire [15 : 0]                                           dout_low;
        
        wire                                                    start_TX;
        wire [7 : 0]                                            tx_data;
        wire                                                    tx_active;
        



         
         PulseRain_RV2T_core PulseRain_RV2T_core_i (
                .clk        (clk),
                .reset_n    (reset_n),
                .sync_reset (sync_reset),
                
                .ocd_read_enable  (ocd_read_enable),
                .ocd_write_enable (ocd_write_enable),
                
                .ocd_rw_addr (ocd_rw_addr),
                .ocd_write_word (ocd_write_word),
                
                .ocd_mem_enable_out (ocd_mem_enable_out),
                .ocd_mem_word_out (ocd_mem_word_out),        
                
                .ocd_reg_read_addr (ocd_reg_read_addr),
                .ocd_reg_we (ocd_reg_we),
                .ocd_reg_write_addr (ocd_reg_write_addr),
                .ocd_reg_write_data (ocd_reg_write_data),

                .start_TX  (start_TX),
                .tx_data   (tx_data),
                .tx_active (tx_active),

                .start (start),
                .start_address (start_address),
                
                .peek_pc (peek_pc),
                .peek_ir (peek_ir),
                
                .mem_addr (mem_addr),
                .mem_write_en (mem_write_en),
                .mem_write_data (mem_write_data),
                .mem_read_data (mem_read_data),
                .processor_paused (processor_paused));




            single_port_ram #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_high_i (
                .addr (mem_addr),
                .din (mem_write_data [31 : 16]),
                .write_en (mem_write_en[3 : 2]),
                .clk (clk),
                .dout (dout_high));
              
            single_port_ram #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_low_i (
                .addr (mem_addr),
                .din (mem_write_data [15 : 0]),
                .write_en (mem_write_en[1 : 0]),
                .clk (clk),
                .dout (dout_low));
      

      

            
           assign mem_read_data = {dout_high, dout_low};
        
            always @(posedge clk, negedge reset_n) begin 
                if (!reset_n) begin
                    mem_addr_d1 <= 0;
                end else begin
                    mem_addr_d1 <= mem_addr;
                end
            end
            



        

        
        UART_TX #(.STABLE_TIME(`UART_STABLE_COUNT), .BAUD_PERIOD_BITS(`UART_TX_BAUD_PERIOD_BITS)) UART_TX_i (
            .clk (clk),
            .reset_n (reset_n),
            .sync_reset (sync_reset),
            
            .start_TX (start_TX),
            .baud_rate_period_m1 (`UART_TX_BAUD_PERIOD - 1),

            .SBUF_in (tx_data),
            .tx_active (tx_active),
            .TXD (TXD));
        
        
        assign  peek_mem_write_en   = mem_write_en;
        assign  peek_mem_write_data = mem_write_data;
        assign  peek_mem_addr       = mem_addr;    
            
endmodule
module PulseRain_RV2T_MCU (




        input   wire                                            clk,                          
        input   wire                                            reset_n,                      
        input   wire                                            sync_reset,

    





        input   wire                                            ocd_read_enable,
        input   wire                                            ocd_write_enable,
        
        input   wire  [`MEM_ADDR_BITS - 1 : 0]                  ocd_rw_addr,
        input   wire  [`XLEN - 1 : 0]                           ocd_write_word,
        
        output  wire                                            ocd_mem_enable_out,
        output  wire  [`XLEN - 1 : 0]                           ocd_mem_word_out,        
        
        input   wire  [`REG_ADDR_BITS - 1 : 0]                  ocd_reg_read_addr,
        input   wire                                            ocd_reg_we,
        input   wire  [`REG_ADDR_BITS - 1 : 0]                  ocd_reg_write_addr,
        input   wire  [`XLEN - 1 : 0]                           ocd_reg_write_data,




        output  wire                                            TXD,
        



        input   wire                                            start,
        input   wire  [`PC_BITWIDTH - 1 : 0]                    start_address,
        
        output  wire                                            processor_paused,

        output  wire  [`XLEN - 1 : 0]                           peek_pc,
        output  wire  [`XLEN - 1 : 0]                           peek_ir,
        
        output  wire  [`XLEN_BYTES - 1 : 0]                     peek_mem_write_en,
        output  wire  [`XLEN - 1 : 0]                           peek_mem_write_data,
        output  wire [`MEM_ADDR_BITS - 1 : 0]                   peek_mem_addr
        
);

     
    



 
        wire [`MEM_ADDR_BITS - 1 : 0]                           mem_addr;
        reg  [`MEM_ADDR_BITS - 1 : 0]                           mem_addr_d1;
        
        wire [`XLEN_BYTES - 1 : 0]                              mem_write_en;
        wire [`XLEN - 1 : 0]                                    mem_write_data;
        wire [`XLEN - 1 : 0]                                    mem_read_data;
            
        wire [15 : 0]                                           dout_high;
        wire [15 : 0]                                           dout_low;
        
        wire                                                    start_TX;
        wire [7 : 0]                                            tx_data;
        wire                                                    tx_active;
        



         
         PulseRain_RV2T_core PulseRain_RV2T_core_i (
                .clk        (clk),
                .reset_n    (reset_n),
                .sync_reset (sync_reset),
                
                .ocd_read_enable  (ocd_read_enable),
                .ocd_write_enable (ocd_write_enable),
                
                .ocd_rw_addr (ocd_rw_addr),
                .ocd_write_word (ocd_write_word),
                
                .ocd_mem_enable_out (ocd_mem_enable_out),
                .ocd_mem_word_out (ocd_mem_word_out),        
                
                .ocd_reg_read_addr (ocd_reg_read_addr),
                .ocd_reg_we (ocd_reg_we),
                .ocd_reg_write_addr (ocd_reg_write_addr),
                .ocd_reg_write_data (ocd_reg_write_data),

                .start_TX  (start_TX),
                .tx_data   (tx_data),
                .tx_active (tx_active),

                .start (start),
                .start_address (start_address),
                
                .peek_pc (peek_pc),
                .peek_ir (peek_ir),
                
                .mem_addr (mem_addr),
                .mem_write_en (mem_write_en),
                .mem_write_data (mem_write_data),
                .mem_read_data (mem_read_data),
                .processor_paused (processor_paused));




            single_port_ram #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_high_i (
                .addr (mem_addr),
                .din (mem_write_data [31 : 16]),
                .write_en (mem_write_en[3 : 2]),
                .clk (clk),
                .dout (dout_high));
              
            single_port_ram #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_low_i (
                .addr (mem_addr),
                .din (mem_write_data [15 : 0]),
                .write_en (mem_write_en[1 : 0]),
                .clk (clk),
                .dout (dout_low));
      

      

            
           assign mem_read_data = {dout_high, dout_low};
        
            always @(posedge clk, negedge reset_n) begin 
                if (!reset_n) begin
                    mem_addr_d1 <= 0;
                end else begin
                    mem_addr_d1 <= mem_addr;
                end
            end
            



        

        
        UART_TX #(.STABLE_TIME(`UART_STABLE_COUNT), .BAUD_PERIOD_BITS(`UART_TX_BAUD_PERIOD_BITS)) UART_TX_i (
            .clk (clk),
            .reset_n (reset_n),
            .sync_reset (sync_reset),
            
            .start_TX (start_TX),
            .baud_rate_period_m1 (`UART_TX_BAUD_PERIOD - 1),

            .SBUF_in (tx_data),
            .tx_active (tx_active),
            .TXD (TXD));
        
        
        assign  peek_mem_write_en   = mem_write_en;
        assign  peek_mem_write_data = mem_write_data;
        assign  peek_mem_addr       = mem_addr;    
            
endmodule