data/full_repos/permissive/143278/ivltests/sdw_release.v
 line:41: before: "working"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdw_release.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #5 ;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/sdw_release.v:41: Unsupported: Verilog 1995 force\n    force working = 0;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdw_release.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/sdw_release.v:47: Unsupported: Verilog 1995 release\n    release working;  \n    ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdw_release.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #2 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdw_release.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ();

reg working;
reg timer;

initial
  working = 1;

initial
  begin
    #5 ;
    force working = 0;
  end

initial
  begin
    #10;
    release working;
    #2 ;
    working = 1;
  end

initial
  begin
    #20;
    if(!working)
        $display("FAILED\n");
    else
        $display("PASSED\n");
  end

endmodule
module main ();


reg working;
reg timer;

initial
  working = 1;

initial
  begin
    #5 ;
    force working = 0;
  end

initial
  begin
    #10;
    release working;
    #2 ;
    working = 1;
  end

initial
  begin
    #20;
    if(!working)
        $display("FAILED\n");
    else
        $display("PASSED\n");
  end

endmodule