data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v
None: at end of input
1: b'%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:9: Cannot find include file: riscv_defs.v\n`include "riscv_defs.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v.v\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v.sv\n             riscv_defs.v\n             riscv_defs.v.v\n             riscv_defs.v.sv\n             obj_dir/riscv_defs.v\n             obj_dir/riscv_defs.v.v\n             obj_dir/riscv_defs.v.sv\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:15: Define or directive not defined: \'`RV_XLEN\'\n        parameter C_WORD_RESET_VECTOR = { `RV_XLEN-2 {1\'b0} }\n                                          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:25: Define or directive not defined: \'`RV_XLEN\'\n        output wire    [`RV_XLEN-1:0] ireqaddr_o,  \n                        ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:29: Define or directive not defined: \'`RV_XLEN\'\n        input  wire    [`RV_XLEN-1:0] irspdata_i,\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:34: Define or directive not defined: \'`RV_SOFID_RANGE\'\n        output wire [`RV_SOFID_RANGE] ids_sofid_o,     \n                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        output wire [`RV_SOFID_RANGE] ids_sofid_o,     \n                                    ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:36: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output wire                   ids_ferr_o,      \n        ^~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:37: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output wire    [`RV_XLEN-1:0] ids_pc_o,        \n        ^~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:37: Define or directive not defined: \'`RV_XLEN\'\n        output wire    [`RV_XLEN-1:0] ids_pc_o,        \n                        ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:39: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input  wire                   exs_pc_wr_i,\n        ^~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:40: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input  wire    [`RV_XLEN-1:0] exs_pc_din_i,\n        ^~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:40: Define or directive not defined: \'`RV_XLEN\'\n        input  wire    [`RV_XLEN-1:0] exs_pc_din_i,\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:42: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input  wire             [1:0] exs_hpl_i\n        ^~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:43: syntax error, unexpected \')\', expecting \',\' or \';\'\n    );\n    ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:56: Define or directive not defined: \'`RV_XLEN\'\n    reg      [`RV_XLEN-1:0] pc_q;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:57: Define or directive not defined: \'`RV_XLEN\'\n    reg      [`RV_XLEN-1:0] request_addr_q;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:61: Define or directive not defined: \'`RV_SOFID_RANGE\'\n    reg   [`RV_SOFID_RANGE] sofid_q;\n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:61: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg   [`RV_SOFID_RANGE] sofid_q;\n                          ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:63: Define or directive not defined: \'`RV_SOFID_SZ\'\n    parameter C_SOFID_SZ     = `RV_SOFID_SZ;\n                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    parameter C_SOFID_SZ     = `RV_SOFID_SZ;\n                                           ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:64: Define or directive not defined: \'`RV_XLEN\'\n    parameter C_FIFO_WIDTH   = C_SOFID_SZ + 1 + `RV_XLEN + `RV_XLEN;\n                                                ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:64: Define or directive not defined: \'`RV_XLEN\'\n    parameter C_FIFO_WIDTH   = C_SOFID_SZ + 1 + `RV_XLEN + `RV_XLEN;\n                                                           ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    parameter C_FIFO_WIDTH   = C_SOFID_SZ + 1 + `RV_XLEN + `RV_XLEN;\n                                                                   ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:66: Define or directive not defined: \'`RV_XLEN\'\n    parameter C_SOFID_LSB    = 1 + 2 * `RV_XLEN;\n                                       ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    parameter C_SOFID_LSB    = 1 + 2 * `RV_XLEN;\n                                               ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:67: Define or directive not defined: \'`RV_XLEN\'\n    parameter C_FERR_LSB     =     2 * `RV_XLEN;\n                                       ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:67: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    parameter C_FERR_LSB     =     2 * `RV_XLEN;\n                                               ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:68: Define or directive not defined: \'`RV_XLEN\'\n    parameter C_FIFO_PC_LSB  =         `RV_XLEN;\n                                       ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:68: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    parameter C_FIFO_PC_LSB  =         `RV_XLEN;\n                                               ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:74: Define or directive not defined: \'`RV_XLEN\'\n    wire     [`RV_XLEN-1:0] fifo_dout_data;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:81: syntax error, unexpected assign\n    assign ireqhpl_o   = exs_hpl_i;\n    ^~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:83: Define or directive not defined: \'`RV_XLEN\'\n    assign ireqaddr_o  = { pc_q[`RV_XLEN-1:`RV_XLEN_X-3], { `RV_XLEN_X-3 {1\'b0} } };\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:83: Define or directive not defined: \'`RV_XLEN_X\'\n    assign ireqaddr_o  = { pc_q[`RV_XLEN-1:`RV_XLEN_X-3], { `RV_XLEN_X-3 {1\'b0} } };\n                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:83: Define or directive not defined: \'`RV_XLEN_X\'\n    assign ireqaddr_o  = { pc_q[`RV_XLEN-1:`RV_XLEN_X-3], { `RV_XLEN_X-3 {1\'b0} } };\n                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:96: Define or directive not defined: \'`RV_SYNC_LOGIC_CLOCK_RESET\'\n    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin\n             ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:112: Define or directive not defined: \'`RV_SYNC_LOGIC_CLOCK_RESET\'\n    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin\n             ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:140: Define or directive not defined: \'`RV_SYNC_LOGIC_CLOCK_RESET\'\n    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin\n             ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:147: Define or directive not defined: \'`RV_XLEN\'\n                pc_q <= pc_q + { { `RV_XLEN-(`RV_XLEN_X-2) {1\'b0} }, 1\'b1, { `RV_XLEN_X-3 {1\'b0} } };\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:147: Define or directive not defined: \'`RV_XLEN_X\'\n                pc_q <= pc_q + { { `RV_XLEN-(`RV_XLEN_X-2) {1\'b0} }, 1\'b1, { `RV_XLEN_X-3 {1\'b0} } };\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:147: Define or directive not defined: \'`RV_XLEN_X\'\n                pc_q <= pc_q + { { `RV_XLEN-(`RV_XLEN_X-2) {1\'b0} }, 1\'b1, { `RV_XLEN_X-3 {1\'b0} } };\n                                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:151: Define or directive not defined: \'`RV_SYNC_LOGIC_CLOCK\'\n    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin\n             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:161: Define or directive not defined: \'`RV_SYNC_LOGIC_CLOCK_RESET\'\n    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin\n             ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:177: Define or directive not defined: \'`RV_SYNC_LOGIC_CLOCK_RESET\'\n    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin\n             ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:179: Define or directive not defined: \'`RV_SOFID_RUN\'\n            sofid_q <= `RV_SOFID_RUN;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:182: Define or directive not defined: \'`RV_SOFID_JUMP\'\n                sofid_q <= `RV_SOFID_JUMP;\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:184: Define or directive not defined: \'`RV_SOFID_RUN\'\n                sofid_q <= `RV_SOFID_RUN;\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:195: Define or directive not defined: \'`RV_XLEN\'\n    assign fifo_din[ C_FIFO_PC_LSB +: `RV_XLEN]   = request_addr_q;\n                                      ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:196: Define or directive not defined: \'`RV_XLEN\'\n    assign fifo_din[C_FIFO_INS_LSB +: `RV_XLEN]   = irspdata_i;\n                                      ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:200: Define or directive not defined: \'`RV_XLEN\'\n    assign ids_pc_o       = fifo_dout[ C_FIFO_PC_LSB +: `RV_XLEN];\n                                                        ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_pfu.v:201: Define or directive not defined: \'`RV_XLEN\'\n    assign fifo_dout_data = fifo_dout[C_FIFO_INS_LSB +: `RV_XLEN];\n                                                        ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module merlin_pfu
    #(
        parameter C_FIFO_PASSTHROUGH  = 0,
        parameter C_FIFO_DEPTH_X      = 2,
        parameter C_WORD_RESET_VECTOR = { `RV_XLEN-2 {1'b0} }
    )
    (

        input  wire                   clk_i,
        input  wire                   reset_i,

        input  wire                   ireqready_i,
        output wire                   ireqvalid_o,
        output wire             [1:0] ireqhpl_o,
        output wire    [`RV_XLEN-1:0] ireqaddr_o,
        output wire                   irspready_o,
        input  wire                   irspvalid_i,
        input  wire                   irsprerr_i,
        input  wire    [`RV_XLEN-1:0] irspdata_i,

        output wire                   ids_dav_o,
        input  wire                   ids_ack_i,
        input  wire             [1:0] ids_ack_size_i,
        output wire [`RV_SOFID_RANGE] ids_sofid_o,
        output wire            [31:0] ids_ins_o,
        output wire                   ids_ferr_o,
        output wire    [`RV_XLEN-1:0] ids_pc_o,

        input  wire                   exs_pc_wr_i,
        input  wire    [`RV_XLEN-1:0] exs_pc_din_i,

        input  wire             [1:0] exs_hpl_i
    );





    reg                     ibus_debt;
    wire                    request;
    wire                    response;

    reg  [C_FIFO_DEPTH_X:0] fifo_level_q;
    reg                     fifo_accepting;

    reg      [`RV_XLEN-1:0] pc_q;
    reg      [`RV_XLEN-1:0] request_addr_q;

    reg                     vectoring_q;

    reg   [`RV_SOFID_RANGE] sofid_q;

    parameter C_SOFID_SZ     = `RV_SOFID_SZ;
    parameter C_FIFO_WIDTH   = C_SOFID_SZ + 1 + `RV_XLEN + `RV_XLEN;

    parameter C_SOFID_LSB    = 1 + 2 * `RV_XLEN;
    parameter C_FERR_LSB     =     2 * `RV_XLEN;
    parameter C_FIFO_PC_LSB  =         `RV_XLEN;
    parameter C_FIFO_INS_LSB =                0;

    wire                    fifo_empty;
    wire [C_FIFO_WIDTH-1:0] fifo_din;
    wire [C_FIFO_WIDTH-1:0] fifo_dout;
    wire     [`RV_XLEN-1:0] fifo_dout_data;






    assign ireqhpl_o   = exs_hpl_i;
    assign ireqvalid_o = fifo_accepting & ~exs_pc_wr_i & (~ibus_debt | response);
    assign ireqaddr_o  = { pc_q[`RV_XLEN-1:`RV_XLEN_X-3], { `RV_XLEN_X-3 {1'b0} } };
    assign irspready_o = 1'b1;

    assign ids_dav_o = ~fifo_empty;
    assign ids_ins_o =  fifo_dout_data[31:0];





    assign request  = ireqvalid_o & ireqready_i;
    assign response = irspvalid_i & irspready_o;

    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            ibus_debt <= 1'b0;
        end else begin
            if (request & ~response) begin
                ibus_debt <= 1'b1;
            end else if (~request & response) begin
                ibus_debt <= 1'b0;
            end
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            fifo_level_q <= { 1'b1, { C_FIFO_DEPTH_X {1'b0} } };
        end else begin
/
            if (request & ~ids_ack_i) begin
                fifo_level_q <= fifo_level_q - { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
            end else if (~request & ids_ack_i) begin
                fifo_level_q <= fifo_level_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
            end
        end
    end
    always @ (*) begin
        if (|fifo_level_q) begin
            fifo_accepting = 1'b1;
        end else begin
            fifo_accepting = 1'b0;
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            pc_q <= { C_WORD_RESET_VECTOR, 2'b0 };
        end else begin
            if (exs_pc_wr_i) begin
                pc_q <= exs_pc_din_i;
            end else if (request) begin
                pc_q <= pc_q + { { `RV_XLEN-(`RV_XLEN_X-2) {1'b0} }, 1'b1, { `RV_XLEN_X-3 {1'b0} } };
            end
        end
    end
    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
        if (request) begin
            request_addr_q <= pc_q;
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            vectoring_q <= 1'b0;
        end else begin
            if (exs_pc_wr_i) begin
                vectoring_q <= 1'b1;
            end else if (request) begin
                vectoring_q <= 1'b0;
            end
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            sofid_q <= `RV_SOFID_RUN;
        end else begin
            if (vectoring_q & request) begin
                sofid_q <= `RV_SOFID_JUMP;
            end else if (response) begin
                sofid_q <= `RV_SOFID_RUN;
            end
        end
    end





    assign fifo_din[   C_SOFID_LSB +: C_SOFID_SZ] = sofid_q;
    assign fifo_din[    C_FERR_LSB +: 1]          = irsprerr_i;
    assign fifo_din[ C_FIFO_PC_LSB +: `RV_XLEN]   = request_addr_q;
    assign fifo_din[C_FIFO_INS_LSB +: `RV_XLEN]   = irspdata_i;

    assign ids_sofid_o    = fifo_dout[   C_SOFID_LSB +: C_SOFID_SZ];
    assign ids_ferr_o     = fifo_dout[    C_FERR_LSB +: 1];
    assign ids_pc_o       = fifo_dout[ C_FIFO_PC_LSB +: `RV_XLEN];
    assign fifo_dout_data = fifo_dout[C_FIFO_INS_LSB +: `RV_XLEN];

    merlin_fifo
        #(
            .C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
            .C_FIFO_WIDTH       (C_FIFO_WIDTH),
            .C_FIFO_DEPTH_X     (C_FIFO_DEPTH_X)
        ) i_merlin_fifo (

            .clk_i          (clk_i),
            .reset_i        (reset_i),

            .flush_i        (exs_pc_wr_i | vectoring_q),
            .empty_o        (fifo_empty),
            .full_o         (),

            .wr_i           (response),
            .din_i          (fifo_din),

            .rd_i           (ids_ack_i),
            .dout_o         (fifo_dout)
        );
endmodule
module merlin_pfu
    #(
        parameter C_FIFO_PASSTHROUGH  = 0,
        parameter C_FIFO_DEPTH_X      = 2,
        parameter C_WORD_RESET_VECTOR = { `RV_XLEN-2 {1'b0} }
    )
    (

        input  wire                   clk_i,
        input  wire                   reset_i,

        input  wire                   ireqready_i,
        output wire                   ireqvalid_o,
        output wire             [1:0] ireqhpl_o,
        output wire    [`RV_XLEN-1:0] ireqaddr_o,
        output wire                   irspready_o,
        input  wire                   irspvalid_i,
        input  wire                   irsprerr_i,
        input  wire    [`RV_XLEN-1:0] irspdata_i,

        output wire                   ids_dav_o,
        input  wire                   ids_ack_i,
        input  wire             [1:0] ids_ack_size_i,
        output wire [`RV_SOFID_RANGE] ids_sofid_o,
        output wire            [31:0] ids_ins_o,
        output wire                   ids_ferr_o,
        output wire    [`RV_XLEN-1:0] ids_pc_o,

        input  wire                   exs_pc_wr_i,
        input  wire    [`RV_XLEN-1:0] exs_pc_din_i,

        input  wire             [1:0] exs_hpl_i
    );






    reg                     ibus_debt;
    wire                    request;
    wire                    response;

    reg  [C_FIFO_DEPTH_X:0] fifo_level_q;
    reg                     fifo_accepting;

    reg      [`RV_XLEN-1:0] pc_q;
    reg      [`RV_XLEN-1:0] request_addr_q;

    reg                     vectoring_q;

    reg   [`RV_SOFID_RANGE] sofid_q;

    parameter C_SOFID_SZ     = `RV_SOFID_SZ;
    parameter C_FIFO_WIDTH   = C_SOFID_SZ + 1 + `RV_XLEN + `RV_XLEN;

    parameter C_SOFID_LSB    = 1 + 2 * `RV_XLEN;
    parameter C_FERR_LSB     =     2 * `RV_XLEN;
    parameter C_FIFO_PC_LSB  =         `RV_XLEN;
    parameter C_FIFO_INS_LSB =                0;

    wire                    fifo_empty;
    wire [C_FIFO_WIDTH-1:0] fifo_din;
    wire [C_FIFO_WIDTH-1:0] fifo_dout;
    wire     [`RV_XLEN-1:0] fifo_dout_data;






    assign ireqhpl_o   = exs_hpl_i;
    assign ireqvalid_o = fifo_accepting & ~exs_pc_wr_i & (~ibus_debt | response);
    assign ireqaddr_o  = { pc_q[`RV_XLEN-1:`RV_XLEN_X-3], { `RV_XLEN_X-3 {1'b0} } };
    assign irspready_o = 1'b1;

    assign ids_dav_o = ~fifo_empty;
    assign ids_ins_o =  fifo_dout_data[31:0];





    assign request  = ireqvalid_o & ireqready_i;
    assign response = irspvalid_i & irspready_o;

    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            ibus_debt <= 1'b0;
        end else begin
            if (request & ~response) begin
                ibus_debt <= 1'b1;
            end else if (~request & response) begin
                ibus_debt <= 1'b0;
            end
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            fifo_level_q <= { 1'b1, { C_FIFO_DEPTH_X {1'b0} } };
        end else begin
/
            if (request & ~ids_ack_i) begin
                fifo_level_q <= fifo_level_q - { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
            end else if (~request & ids_ack_i) begin
                fifo_level_q <= fifo_level_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
            end
        end
    end
    always @ (*) begin
        if (|fifo_level_q) begin
            fifo_accepting = 1'b1;
        end else begin
            fifo_accepting = 1'b0;
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            pc_q <= { C_WORD_RESET_VECTOR, 2'b0 };
        end else begin
            if (exs_pc_wr_i) begin
                pc_q <= exs_pc_din_i;
            end else if (request) begin
                pc_q <= pc_q + { { `RV_XLEN-(`RV_XLEN_X-2) {1'b0} }, 1'b1, { `RV_XLEN_X-3 {1'b0} } };
            end
        end
    end
    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
        if (request) begin
            request_addr_q <= pc_q;
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            vectoring_q <= 1'b0;
        end else begin
            if (exs_pc_wr_i) begin
                vectoring_q <= 1'b1;
            end else if (request) begin
                vectoring_q <= 1'b0;
            end
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            sofid_q <= `RV_SOFID_RUN;
        end else begin
            if (vectoring_q & request) begin
                sofid_q <= `RV_SOFID_JUMP;
            end else if (response) begin
                sofid_q <= `RV_SOFID_RUN;
            end
        end
    end





    assign fifo_din[   C_SOFID_LSB +: C_SOFID_SZ] = sofid_q;
    assign fifo_din[    C_FERR_LSB +: 1]          = irsprerr_i;
    assign fifo_din[ C_FIFO_PC_LSB +: `RV_XLEN]   = request_addr_q;
    assign fifo_din[C_FIFO_INS_LSB +: `RV_XLEN]   = irspdata_i;

    assign ids_sofid_o    = fifo_dout[   C_SOFID_LSB +: C_SOFID_SZ];
    assign ids_ferr_o     = fifo_dout[    C_FERR_LSB +: 1];
    assign ids_pc_o       = fifo_dout[ C_FIFO_PC_LSB +: `RV_XLEN];
    assign fifo_dout_data = fifo_dout[C_FIFO_INS_LSB +: `RV_XLEN];

    merlin_fifo
        #(
            .C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
            .C_FIFO_WIDTH       (C_FIFO_WIDTH),
            .C_FIFO_DEPTH_X     (C_FIFO_DEPTH_X)
        ) i_merlin_fifo (

            .clk_i          (clk_i),
            .reset_i        (reset_i),

            .flush_i        (exs_pc_wr_i | vectoring_q),
            .empty_o        (fifo_empty),
            .full_o         (),

            .wr_i           (response),
            .din_i          (fifo_din),

            .rd_i           (ids_ack_i),
            .dout_o         (fifo_dout)
        );
endmodule