data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v
None: at end of input
1: b'%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:2: Cannot find include file: modulos/enabler.v\n  `include "modulos/enabler.v" \n           ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/enabler.v\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/enabler.v.v\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/enabler.v.sv\n             modulos/enabler.v\n             modulos/enabler.v.v\n             modulos/enabler.v.sv\n             obj_dir/modulos/enabler.v\n             obj_dir/modulos/enabler.v.v\n             obj_dir/modulos/enabler.v.sv\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:5: Cannot find include file: ../tarea3/modulos/nandGate.v\n  `include "../tarea3/modulos/nandGate.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:8: Cannot find include file: ../tarea3/modulos/notGate.v\n  `include "../tarea3/modulos/notGate.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:28: Unsupported: Ignoring delay on this delayed statement.\n  always #30  clk = !clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:34: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:37: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:40: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:42: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:45: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:47: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:50: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:57: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./tests/testEnabler.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:58: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars();\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:63: Unsupported or unknown PLI call: $monitor\n    $monitor             ("%t| %b    | %b     | %b ",\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #450\n  ^\n%Error: Exiting due to 6 error(s), 9 warning(s)\n'
module testenabler();
   reg clk;
   reg enb;
   wire out;

  enabler tester(
    .clk(clk),
    .enb(enb),
    .eclk(out)
  );

  parameter retardos = 30;
  always #30  clk = !clk;

 initial begin

  	clk = 0;
	enb = 1;
	#retardos

	enb = 0;
	#retardos
	enb = 1;

	#retardos
	enb = 0;
	#retardos

	enb = 0;
	#retardos
	enb = 0;
	#retardos

	enb = 1;
	#retardos
	enb = 1;

end

  initial
    begin
    $dumpfile("./tests/testEnabler.vcd");
    $dumpvars();
    $display("------------------------------------");
    $display("--  Test para modulo Enabler      --");
    $display("------------------------------------");
    $display ("\t     tiempo | clk | enb | out ");
    $monitor             ("%t| %b    | %b     | %b ",
                          $time, clk, enb,  out);
  #450
    $display("------------------------------------");
    $display("####### FIN TEST DE: ENABLER  ######");
    $display("------------------------------------");

    $finish;
  end
endmodule
module testenabler();

   reg clk;
   reg enb;
   wire out;

  enabler tester(
    .clk(clk),
    .enb(enb),
    .eclk(out)
  );

  parameter retardos = 30;
  always #30  clk = !clk;

 initial begin

  	clk = 0;
	enb = 1;
	#retardos

	enb = 0;
	#retardos
	enb = 1;

	#retardos
	enb = 0;
	#retardos

	enb = 0;
	#retardos
	enb = 0;
	#retardos

	enb = 1;
	#retardos
	enb = 1;

end

  initial
    begin
    $dumpfile("./tests/testEnabler.vcd");
    $dumpvars();
    $display("------------------------------------");
    $display("--  Test para modulo Enabler      --");
    $display("------------------------------------");
    $display ("\t     tiempo | clk | enb | out ");
    $monitor             ("%t| %b    | %b     | %b ",
                          $time, clk, enb,  out);
  #450
    $display("------------------------------------");
    $display("####### FIN TEST DE: ENABLER  ######");
    $display("------------------------------------");

    $finish;
  end
endmodule