data/full_repos/permissive/190426879/pipelined_cpu/source/fiftyM2one.v
data/verilator_xmls/1f328326-cc66-4415-bcce-a3b6886c5a42.xml
module fiftyM2one(CLOCK_50, clk);
	input CLOCK_50;
	output reg clk;
	reg [31:0] counter;
	
	initial
	begin
		counter <= 0;
		clk <= 1;
	end
	
	always @ (posedge CLOCK_50)
	begin
		if(counter == 50000000)
		begin
			counter <= 0;
			clk <= ~clk;
		end
		counter <= counter + 1;
	end
endmodule
module fiftyM2one(CLOCK_50, clk);

	input CLOCK_50;
	output reg clk;
	reg [31:0] counter;
	
	initial
	begin
		counter <= 0;
		clk <= 1;
	end
	
	always @ (posedge CLOCK_50)
	begin
		if(counter == 50000000)
		begin
			counter <= 0;
			clk <= ~clk;
		end
		counter <= counter + 1;
	end
endmodule