data/full_repos/permissive/116266634/mux5bit_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/116266634/mux5bit_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\nselect = 1\'b0; #50;\n               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/116266634/mux5bit_testbench.v:24: Unsupported or unknown PLI call: $monitor\n$monitor("  n1 = %5b--in2 = %5b\\nout = %5b--select = %1b", in1, in2, out, select);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux5bit_testbench();

reg[4:0] in1;
reg[4:0] in2;
reg select;
wire [4:0] out;


mux_for_destination_register test(out, select, in1, in2);


initial begin
in1 = 32'b01010; 
in2 = 32'b11111;
select = 1'b0; #50;

in1 = 32'b01010; 
in2 = 32'b11111;
select = 1'b1;

end

initial begin
$monitor("İn1 = %5b--in2 = %5b\nout = %5b--select = %1b", in1, in2, out, select);
end


endmodule
module mux5bit_testbench();


reg[4:0] in1;
reg[4:0] in2;
reg select;
wire [4:0] out;


mux_for_destination_register test(out, select, in1, in2);


initial begin
in1 = 32'b01010; 
in2 = 32'b11111;
select = 1'b0; #50;

in1 = 32'b01010; 
in2 = 32'b11111;
select = 1'b1;

end

initial begin
$monitor("İn1 = %5b--in2 = %5b\nout = %5b--select = %1b", in1, in2, out, select);
end


endmodule