data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl/fifo.v
1: b"%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl/fifo.v:28: Cannot find file containing module: 'sync_dual_port_ram'\n  sync_dual_port_ram #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) ram\n  ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl,data/full_repos/permissive/137416811/sync_dual_port_ram\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl,data/full_repos/permissive/137416811/sync_dual_port_ram.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl,data/full_repos/permissive/137416811/sync_dual_port_ram.sv\n             sync_dual_port_ram\n             sync_dual_port_ram.v\n             sync_dual_port_ram.sv\n             obj_dir/sync_dual_port_ram\n             obj_dir/sync_dual_port_ram.v\n             obj_dir/sync_dual_port_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module fifo
  #( parameter ADDRESS_WIDTH = 4,
                 DATA_WIDTH    =  4
   )
   

  (
    input wire clk, reset,
    input wire read, write,
    input wire [DATA_WIDTH-1:0] write_data,
    output wire empty, full,
    output wire [DATA_WIDTH-1:0] read_data
  );
  

  reg [ADDRESS_WIDTH-1:0] write_address_reg, write_address_next, write_address_after;
  reg [ADDRESS_WIDTH-1:0] read_address_reg, read_address_next, read_address_after;
  reg full_reg, empty_reg, full_next, empty_next;
  wire write_en;
  

  assign write_en = write & ~full_reg;
  

  sync_dual_port_ram #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) ram
                       (.clk(clk), .write_en(write_en), .write_address(write_address_reg),
      .read_address(read_address_reg), .write_data_in(write_data),
      .write_data_out(), .read_data_out(read_data));
  

  always @(posedge clk, posedge reset)
    if (reset)
        begin
                    write_address_reg <= 0;
                    read_address_reg  <= 0;
                    full_reg          <= 1'b0;
                    empty_reg         <= 1'b1;
        end
    else
        begin
                    write_address_reg <= write_address_next;
                    read_address_reg  <= read_address_next;
                    full_reg          <= full_next;
                    empty_reg         <= empty_next;
        end
      

  always @*
    begin
    write_address_after = write_address_reg + 1;
    read_address_after  = read_address_reg + 1;
    end
    

  always @*
    begin

    write_address_next = write_address_reg;
    read_address_next  = read_address_reg;
    full_next          = full_reg;
    empty_next         = empty_reg;
    

    if(read && ~empty_reg && ~write)
      begin
      read_address_next = read_address_after;
      full_next = 1'b0;
      
      if (read_address_after == write_address_reg)
        empty_next = 1'b1;
      end
    

    else if(write && ~full_reg && ~read)
      begin
      write_address_next = write_address_after;
      empty_next = 1'b0;
      
      if (write_address_after == read_address_reg)
        full_next = 1'b1;
                        end
    

                else if(write && read)
      begin
      write_address_next = write_address_after;
      read_address_next  = read_address_after;
                        end
    end 
  

   assign full  = full_reg;
   assign empty = empty_reg;
endmodule
module fifo
  #( parameter ADDRESS_WIDTH = 4,
                 DATA_WIDTH    =  4
   )
   

  (
    input wire clk, reset,
    input wire read, write,
    input wire [DATA_WIDTH-1:0] write_data,
    output wire empty, full,
    output wire [DATA_WIDTH-1:0] read_data
  );

  

  reg [ADDRESS_WIDTH-1:0] write_address_reg, write_address_next, write_address_after;
  reg [ADDRESS_WIDTH-1:0] read_address_reg, read_address_next, read_address_after;
  reg full_reg, empty_reg, full_next, empty_next;
  wire write_en;
  

  assign write_en = write & ~full_reg;
  

  sync_dual_port_ram #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) ram
                       (.clk(clk), .write_en(write_en), .write_address(write_address_reg),
      .read_address(read_address_reg), .write_data_in(write_data),
      .write_data_out(), .read_data_out(read_data));
  

  always @(posedge clk, posedge reset)
    if (reset)
        begin
                    write_address_reg <= 0;
                    read_address_reg  <= 0;
                    full_reg          <= 1'b0;
                    empty_reg         <= 1'b1;
        end
    else
        begin
                    write_address_reg <= write_address_next;
                    read_address_reg  <= read_address_next;
                    full_reg          <= full_next;
                    empty_reg         <= empty_next;
        end
      

  always @*
    begin
    write_address_after = write_address_reg + 1;
    read_address_after  = read_address_reg + 1;
    end
    

  always @*
    begin

    write_address_next = write_address_reg;
    read_address_next  = read_address_reg;
    full_next          = full_reg;
    empty_next         = empty_reg;
    

    if(read && ~empty_reg && ~write)
      begin
      read_address_next = read_address_after;
      full_next = 1'b0;
      
      if (read_address_after == write_address_reg)
        empty_next = 1'b1;
      end
    

    else if(write && ~full_reg && ~read)
      begin
      write_address_next = write_address_after;
      empty_next = 1'b0;
      
      if (write_address_after == read_address_reg)
        full_next = 1'b1;
                        end
    

                else if(write && read)
      begin
      write_address_next = write_address_after;
      read_address_next  = read_address_after;
                        end
    end 
  

   assign full  = full_reg;
   assign empty = empty_reg;
endmodule