data/full_repos/permissive/204486675/hdl/ram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/204486675/hdl/ram.v:27: Operator EQ expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'in_pos\' generates 8 bits.\n                                                                 : ... In instance ram\nwire [ABITS-1:0] next_in_pos = (in_pos == DEPTH-1) ? 0 : in_pos + 1;\n                                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/204486675/hdl/ram.v:28: Operator EQ expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'next_in_pos\' generates 8 bits.\n                                                                 : ... In instance ram\nwire [ABITS-1:0] next_next_in_pos = (next_in_pos == DEPTH-1) ? 0 : next_in_pos + 1;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/204486675/hdl/ram.v:30: Operator EQ expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'out_pos\' generates 8 bits.\n                                                                 : ... In instance ram\nwire [ABITS-1:0] next_out_pos = (out_pos == DEPTH-1) ? 0 : out_pos + 1;\n                                         ^~\n%Error: Exiting due to 3 warning(s)\n'
module ram (
  din,
  write_en,
  waddr,
  wclk,
  raddr,
  rclk,
  dout
  );

parameter DEPTH = 256;
parameter WIDTH = 16;
localparam integer ABITS = $clog2(DEPTH);
input [ABITS-1:0] waddr, raddr;
input [WIDTH-1:0] din;
input write_en, wclk, rclk;
output reg [WIDTH-1:0] dout;
reg [WIDTH-1:0] mem [DEPTH-1:0];

reg [ABITS-1:0] in_pos = 0;
reg [ABITS-1:0] out_pos = 0;

reg [WIDTH-1:0] memory [0:DEPTH-1];

wire [ABITS-1:0] next_in_pos = (in_pos == DEPTH-1) ? 0 : in_pos + 1;
wire [ABITS-1:0] next_next_in_pos = (next_in_pos == DEPTH-1) ? 0 : next_in_pos + 1;

wire [ABITS-1:0] next_out_pos = (out_pos == DEPTH-1) ? 0 : out_pos + 1;
reg [WIDTH-1:0] out_data_d = 0;


always @(posedge wclk)
  begin
  if (write_en)
    mem[waddr] <= din;
  end

always @(posedge rclk)
  begin
    dout <= mem[raddr];
  end

endmodule
module ram (
  din,
  write_en,
  waddr,
  wclk,
  raddr,
  rclk,
  dout
  );


parameter DEPTH = 256;
parameter WIDTH = 16;
localparam integer ABITS = $clog2(DEPTH);
input [ABITS-1:0] waddr, raddr;
input [WIDTH-1:0] din;
input write_en, wclk, rclk;
output reg [WIDTH-1:0] dout;
reg [WIDTH-1:0] mem [DEPTH-1:0];

reg [ABITS-1:0] in_pos = 0;
reg [ABITS-1:0] out_pos = 0;

reg [WIDTH-1:0] memory [0:DEPTH-1];

wire [ABITS-1:0] next_in_pos = (in_pos == DEPTH-1) ? 0 : in_pos + 1;
wire [ABITS-1:0] next_next_in_pos = (next_in_pos == DEPTH-1) ? 0 : next_in_pos + 1;

wire [ABITS-1:0] next_out_pos = (out_pos == DEPTH-1) ? 0 : out_pos + 1;
reg [WIDTH-1:0] out_data_d = 0;


always @(posedge wclk)
  begin
  if (write_en)
    mem[waddr] <= din;
  end

always @(posedge rclk)
  begin
    dout <= mem[raddr];
  end

endmodule