data/full_repos/permissive/214620165/rtl/general/sirv_gnrl_dffs.v
'utf-8' codec can't decode byte 0xd0 in position 295: invalid continuation byte
1: b'%Error: data/full_repos/permissive/214620165/rtl/general/sirv_gnrl_dffs.v:48: Cannot find include file: ../../rtl/e203_defines.v\n`include "../../rtl/e203_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214620165/rtl/general,data/full_repos/permissive/214620165/../../rtl/e203_defines.v\n             data/full_repos/permissive/214620165/rtl/general,data/full_repos/permissive/214620165/../../rtl/e203_defines.v.v\n             data/full_repos/permissive/214620165/rtl/general,data/full_repos/permissive/214620165/../../rtl/e203_defines.v.sv\n             ../../rtl/e203_defines.v\n             ../../rtl/e203_defines.v.v\n             ../../rtl/e203_defines.v.sv\n             obj_dir/../../rtl/e203_defines.v\n             obj_dir/../../rtl/e203_defines.v.v\n             obj_dir/../../rtl/e203_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module sirv_gnrl_dffl # (
  parameter DW = 32
) (

  input               lden, 
  input      [DW-1:0] dnxt,
  output     [DW-1:0] qout,

  input               clk 
);

reg [DW-1:0] qout_r;

always @(posedge clk)
begin : DFFL_PROC
  if (lden == 1'b1)
    qout_r <= #1 dnxt;
end

assign qout = qout_r;

`ifndef FPGA_SOURCE
`ifndef DISABLE_SV_ASSERTION

sirv_gnrl_xchecker # (
  .DW(1)
) sirv_gnrl_xchecker(
  .i_dat(lden),
  .clk  (clk)
);

`endif
`endif
    

endmodule
module sirv_gnrl_dffl # (
  parameter DW = 32
) (

  input               lden, 
  input      [DW-1:0] dnxt,
  output     [DW-1:0] qout,

  input               clk 
);


reg [DW-1:0] qout_r;

always @(posedge clk)
begin : DFFL_PROC
  if (lden == 1'b1)
    qout_r <= #1 dnxt;
end

assign qout = qout_r;

`ifndef FPGA_SOURCE
`ifndef DISABLE_SV_ASSERTION

sirv_gnrl_xchecker # (
  .DW(1)
) sirv_gnrl_xchecker(
  .i_dat(lden),
  .clk  (clk)
);

`endif
`endif
    

endmodule