data/full_repos/permissive/166558975/rtl/NextZ80/NextZ80CPU.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/166558975/rtl/NextZ80/NextZ80CPU.v:119: Cannot find file containing module: \'Z80Reg\'\n Z80Reg CPU_REGS (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166558975/rtl/NextZ80,data/full_repos/permissive/166558975/Z80Reg\n             data/full_repos/permissive/166558975/rtl/NextZ80,data/full_repos/permissive/166558975/Z80Reg.v\n             data/full_repos/permissive/166558975/rtl/NextZ80,data/full_repos/permissive/166558975/Z80Reg.sv\n             Z80Reg\n             Z80Reg.v\n             Z80Reg.sv\n             obj_dir/Z80Reg\n             obj_dir/Z80Reg.v\n             obj_dir/Z80Reg.sv\n%Error: data/full_repos/permissive/166558975/rtl/NextZ80/NextZ80CPU.v:145: Cannot find file containing module: \'ALU8\'\n ALU8 CPU_ALU8 (\n ^~~~\n%Error: data/full_repos/permissive/166558975/rtl/NextZ80/NextZ80CPU.v:157: Cannot find file containing module: \'ALU16\'\n ALU16 CPU_ALU16 (\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/166558975/rtl/NextZ80/NextZ80CPU.v:1205: Operator EQ expects 4 bits on the LHS, but LHS\'s REPLICATE generates 2 bits.\n                                                                                  : ... In instance NextZ80\n    if({FETCH[5], FETCH[2]} == 4\'b10)\n                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module NextZ80
(
		input wire[7:0] DI,
		output wire[7:0] DO,
		output wire[15:0] ADDR,
		output reg WR,
		output reg MREQ,
		output reg IORQ,
		output reg HALT,
		output reg M1,
		input wire CLK,
		input wire RESET,
		input wire INT,
		input wire NMI,
		input	wire WAIT
);


	reg	[9:0] CPUStatus = 0;
	wire	[7:0] ALU8FLAGS;
	wire	[7:0]	FLAGS;
	wire 	[7:0] ALU80;
	wire 	[7:0] ALU81;
	wire 	[15:0]ALU160;
	wire 	[7:0] ALU161;
	wire	[15:0]ALU8OUT;

	reg 	[9:0]	FETCH = 0;
	reg 	[2:0]	STAGE = 0;
	wire	[5:0]	opd;
	wire	[2:0] op16;
	wire	op0mem = FETCH[2:0] == 6;
	wire	op1mem = FETCH[5:3] == 6;
	reg	[1:0]fetch98;


	reg	[1:0]DO_SEL;
	reg	ALU160_SEL;
	reg	DINW_SEL;
	reg 	[5:0]WE;
	reg 	[4:0] ALU8OP;
	reg 	[2:0] ALU16OP;
	reg 	next_stage;
	reg 	[3:0]REG_WSEL;
	reg 	[3:0]REG_RSEL;
	reg	[11:0]status;

	wire	[7:0]FlagMux = {FLAGS[7], !FLAGS[7], FLAGS[2], !FLAGS[2], FLAGS[0], !FLAGS[0], FLAGS[6], !FLAGS[6]};
	reg	tzf;
	reg 	FNMI = 0, SNMI = 0;
	reg 	SRESET = 0;
	reg	SINT = 0;
	wire	[2:0]intop = FETCH[1] ? 4 : (FETCH[0] ? 5 : 6);
	reg 	xmask;

	Z80Reg CPU_REGS (
		 .rstatus(CPUStatus[7:0]), 
		 .M1(M1), 
		 .WE(WE), 
		 .CLK(CLK), 
		 .ALU8OUT(ALU8OUT), 
		 .DI(DI), 
		 .DO(DO), 
		 .ADDR(ADDR), 									
		 .CONST(FETCH[7] ? {2'b00, FETCH[5:3], 3'b000} : 8'h66),
		 .ALU80(ALU80), 
		 .ALU81(ALU81), 
		 .ALU160(ALU160), 
		 .ALU161(ALU161), 
		 .ALU8FLAGS(ALU8FLAGS), 
		 .FLAGS(FLAGS),
		 .DO_SEL(DO_SEL), 
		 .ALU160_sel(ALU160_SEL), 
		 .REG_WSEL(REG_WSEL), 
		 .REG_RSEL(REG_RSEL), 
		 .DINW_SEL(DINW_SEL),
		 .XMASK(xmask),
		 .ALU16OP(ALU16OP),
		 .WAIT(WAIT)
		 );

	ALU8 CPU_ALU8 (
		 .D0(ALU80), 
		 .D1(ALU81), 
		 .FIN(FLAGS), 
		 .FOUT(ALU8FLAGS), 
		 .ALU8DOUT(ALU8OUT), 
		 .OP(ALU8OP),
		 .EXOP(FETCH[8:3]),
		 .LDIFLAGS(REG_WSEL[2]),
		 .DSTHI(!REG_WSEL[0])
		 );

	ALU16 CPU_ALU16 (
		 .D0(ALU160), 
		 .D1(ALU161), 
		 .DOUT(ADDR), 
		 .OP(ALU16OP)
		 );

	always @(posedge CLK)
		if(!WAIT) begin
			SRESET <= RESET;
			SNMI <= NMI;
			SINT <= INT;
			if(!SNMI) FNMI <= 0; 
			if(SRESET) FETCH <= 10'b1110000000;
			else 
				if(FETCH[9:6] == 4'b1110) {FETCH[9:7]} <= 3'b000;
				else begin 
					if(M1 || (fetch98 == 2'b10))
						case({MREQ, CPUStatus[9:8]})
							3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: FETCH <= {fetch98, DI};
							3'b010: FETCH <= {fetch98, 8'hff};
							3'b011: ;
						endcase
					if(~|{next_stage, fetch98[1:0], status[4]})
						if(SNMI & !FNMI) begin
							{FETCH[9:6], FETCH[1:0]} <= {4'b1101, HALT, M1};
							FNMI <= 1;
						end else if(SINT & CPUStatus[6] & !status[11]) {FETCH[9:6], FETCH[1:0]} <= {4'b1100, HALT, M1};
				end
			if(next_stage) STAGE <= STAGE + 3'b001;
			else STAGE <= 0;
			if(status[4]) CPUStatus[5:4] <= status[5:4];
			else if(~|{next_stage, fetch98[1]} | fetch98[0]) CPUStatus[4] <= 1'b0;
			CPUStatus[3:0] <= CPUStatus[3:0] ^ status[3:0];
			if(status[11]) CPUStatus[7:6] <= status[7:6];
			if(status[10]) CPUStatus[9:8] <= status[9:8];
			tzf <= ALU8FLAGS[6];
		end

	assign opd[0] = FETCH[0] ^ &FETCH[2:1];
	assign opd[2:1] = FETCH[2:1];
	assign opd[3] = FETCH[3] ^ &FETCH[5:4];
	assign opd[5:4] = FETCH[5:4];
	assign op16[2:0] = &FETCH[5:4] ? 3'b101 : {1'b0, FETCH[5:4]};

	always @* begin
		DO_SEL	= 2'bxx;
		ALU160_SEL = 1'bx;
		DINW_SEL = 1'bx;
		WE 		= 6'bxxxxxx;
		ALU8OP	= 5'bxxxxx;
		ALU16OP	= 3'b000;
		next_stage = 0;
		REG_WSEL	= 4'bxxxx;
		REG_RSEL	= 4'bx0xx;
		M1 		= 1;
		MREQ		= 1;
		WR			= 0;

		HALT = 0;
		IORQ = 0;
		status	= 12'b00xxxxx00000;
		fetch98 = 2'b00;
		
		case({FETCH[7:6], op1mem, op0mem})
			4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b1000, 4'b1100: xmask = 1;
			default: xmask = 0;
		endcase
		
		case(FETCH[9:6])	

			4'b0000:
				case(FETCH[3:0])

					4'b0000, 4'b1000:	
						case(FETCH[5:4])
							2'b00: begin
								DO_SEL	= 2'bxx;			
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[0] = FETCH[3];
							end
							2'b01:				
								if(!STAGE[0]) begin
									ALU160_SEL = 1;
									WE 		= 6'b010100;
									if(!FETCH[3]) begin
										ALU8OP	= 5'b01010;
										REG_WSEL	= 4'b0000;
									end
									next_stage = 1;
									M1 		= 0;
								end else if(FETCH[3]) begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
									ALU16OP	= 3;
								end else begin
									ALU160_SEL = 1;
									DINW_SEL = 0;
									WE 		= 6'b010x10;
									ALU8OP	= 5'b01010;
									ALU16OP	= tzf ? 3'd0 : 3'd3;
									REG_WSEL	= 4'b0000;
								end
							2'b10, 2'b11:
								case({STAGE[0], FlagMux[{1'b0, FETCH[4:3]}]})
									2'b00, 2'b11: begin
										ALU160_SEL = 1;
										WE 		= 6'b010x00;
										ALU16OP	= STAGE[0] ? 3'd3 : 3'd1;
									end 
									2'b01: begin
										ALU160_SEL = 1;
										WE 		= 6'b010100;
										next_stage = 1; 
										M1 		= 0;
									end
								endcase
						endcase

					4'b0001:
						case({STAGE[1:0], op16[2]})
							3'b00_0, 3'b00_1, 3'b01_0, 3'b01_1: begin
								ALU160_SEL = 1;
								DINW_SEL = 1;
								WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
								next_stage = 1;
								REG_WSEL	= {op16, 1'bx}; 
								M1 		= 0;
							end
							3'b10_0, 3'b11_1: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
							3'b10_1: begin
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= 4;
								next_stage = 1;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								MREQ		= 0;
							end
						endcase


					4'b0010,	4'b1010:
						case(STAGE[2:0])
							3'b000:
								if(FETCH[5] == 0) begin
									if(FETCH[3]) DINW_SEL = 1;
									else DO_SEL	= 2'b00;
									ALU160_SEL = 0;
									WE 		= {4'b000x, FETCH[3], 1'bx};
									next_stage = 1;
									REG_WSEL	= FETCH[3] ? 4'b011x : 4'b0110;
									REG_RSEL	= {op16, 1'bx};
									M1 		= 0;
									WR = !FETCH[3];
								end else begin
									ALU160_SEL = 1;
									DINW_SEL = 1;
									WE 		= 6'b010xx1;
									next_stage = 1;
									REG_WSEL	= 4'b111x;
									M1 		= 0;
								end
							3'b001:
								if(FETCH[5] == 0) begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end else begin
									ALU160_SEL = 1;
									DINW_SEL = 1;
									WE 		= 6'b010x10;
									next_stage = 1;
									REG_WSEL	= 4'b111x;
									M1 		= 0;
								end
							3'b010: begin					
								ALU160_SEL = 1'b0;
								REG_RSEL	= 4'b111x;
								M1 		= 0;
								WR			= !FETCH[3];
								next_stage = 1;
								if(FETCH[3]) begin
									DINW_SEL = 1;
									WE 		= {4'b000x, FETCH[4] ? 1'b1 : 1'bx, FETCH[4] ? 1'bx : 1'b1};
									REG_WSEL = FETCH[4] ? 4'b011x : 4'b010x;
								end else begin
									DO_SEL	= 2'b00;
									WE 		= 6'b000x00;
									REG_WSEL = FETCH[4] ? 4'b0110 : 4'b0101;
								end
							end
							3'b011:
								if(FETCH[4]) begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end else begin					
									REG_RSEL	= 4'b111x;
									M1 		= 0;
									WR			= !FETCH[3];
									ALU160_SEL = 1'b0;
									ALU16OP	= 1;
									next_stage = 1;
									if(FETCH[3]) begin
										DINW_SEL = 1;
										WE 		= 6'b000x10;
										REG_WSEL = 4'b010x;
									end else begin
										DO_SEL	= 2'b00;
										WE 		= 6'b000x00;
										REG_WSEL = 4'b0100;
									end
								end
							3'b100: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
						endcase

					4'b0011, 4'b1011:
						if(!STAGE[0])
							if(op16[2]) begin
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= {FETCH[3], 1'b0, FETCH[3]};
								next_stage = 1;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								MREQ		= 0;
							end else begin
								ALU160_SEL = 1;
								DINW_SEL = 0;
								WE 		= 6'b010x11;
								ALU8OP	= {4'b0111, FETCH[3]};
								REG_WSEL	= {op16, 1'b0};
								REG_RSEL	= {op16, 1'b1};
							end
						else 	begin
							ALU160_SEL = 1;
							WE 		= 6'b010x00;
						end

					4'b0100, 4'b0101, 4'b1100, 4'b1101: 
						if(!op1mem) begin
							DINW_SEL = 0;
							ALU160_SEL = 1;
							WE 		= opd[3] ? 6'b110x01 : 6'b110x10;
							ALU8OP	= {3'b010, FETCH[0], 1'b0};
							REG_WSEL	= {1'b0, opd[5:3]};
						end else case({STAGE[1:0], CPUStatus[4]})
							3'b00_0, 3'b01_1: begin
								ALU160_SEL = 0;
								DINW_SEL = 1;
								WE 		= 6'b000001;
								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
								next_stage = 1;
								REG_WSEL	= 4'b011x;
								REG_RSEL	= 4'b010x;
								M1 		= 0;
							end
							3'b00_1:	begin
								ALU160_SEL = 1;
								WE 		= 6'b010100;
								next_stage = 1;
								M1 		= 0;
							end 
							3'b01_0, 3'b10_1: begin
								DO_SEL	= 2'b11;
								ALU160_SEL = 0;
								WE 		= 6'b100x0x;
								ALU8OP	= {3'b010, FETCH[0], 1'b0};
								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
								next_stage = 1;
								REG_WSEL	= 4'b0111;
								REG_RSEL	= 4'b010x;
								M1 		= 0;
								WR			= 1;
							end
							3'b10_0, 3'b11_1: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
						endcase

					4'b0110, 4'b1110: 				
						case({STAGE[1:0], CPUStatus[4], op1mem})
							4'b00_0_0, 4'b00_0_1, 4'b00_1_0, 4'b01_1_1: begin
								ALU160_SEL = 1;
								DINW_SEL = 1;
								WE 		= opd[3] ? 6'b010001 : 6'b010010;
								next_stage = 1;
								REG_WSEL	= {1'b0, opd[5:4], 1'bx};
								M1 		= 0;
							end
							4'b01_0_0, 4'b01_1_0, 4'b10_0_1, 4'b11_1_1: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
							4'b01_0_1, 4'b10_1_1: begin
								DO_SEL	= 2'b00;
								ALU160_SEL = 0;
								WE 		= 6'b000x0x;
								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
								next_stage = 1;
								REG_WSEL	= 4'b0111;
								REG_RSEL	= 4'b010x;
								M1 		= 0;
								WR			= 1;
							end
							4'b00_1_1: begin
								ALU160_SEL = 1;
								WE 		= 6'b010100;
								next_stage = 1;
								M1 		= 0;
							end
						endcase

					4'b0111, 4'b1111: 				
						case(FETCH[5:3])
							3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101: begin
								ALU160_SEL = 1;
								DINW_SEL = 0;
								WE 		= 6'b110x1x;
								ALU8OP	= FETCH[5] ? {2'b01, !FETCH[3], 2'b01} : {3'b110, FETCH[4:3]};
								REG_WSEL	= 4'b0110;
							end
							3'b110, 3'b111:	begin
								ALU160_SEL = 1;
								DINW_SEL = 0;
								WE 		= 6'b110x0x;
								ALU8OP	= {4'b1010, !FETCH[3]};
							end
						endcase

					4'b1001: 
						if(!STAGE[0]) begin
							DINW_SEL = 0;
							WE 		= 6'b100x01;
							ALU8OP	= 5'b10000;
							next_stage = 1;
							REG_WSEL	= 4'b0101;
							REG_RSEL	= {op16, 1'b1};
							M1 		= 0;
							MREQ		= 0;
						end else begin
							ALU160_SEL = 1;
							DINW_SEL = 0;
							WE 		= 6'b110x10;
							ALU8OP	= 5'b10001;
							REG_WSEL	= 4'b0100;
							REG_RSEL	= {op16, 1'b0};
						end
				endcase


			4'b0001:	
				case({STAGE[1:0], CPUStatus[4], op1mem, op0mem})
					5'b00_0_00, 5'b00_1_00,
					5'b01_0_01,
					5'b10_1_01:
					begin	
						ALU160_SEL = 1;
						DINW_SEL	  = 0;
						WE = opd[3] ? 6'b010x01 : 6'b010x10;
						ALU8OP = 29;
						REG_WSEL = {1'b0, opd[5:4], 1'bx};
						REG_RSEL = {1'b0, opd[2:0]};
					end
					5'b00_0_01,
					5'b01_1_01:
					begin	
						ALU160_SEL = 0;
						DINW_SEL = 1;
						WE 		= 6'b000x01;
						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
						next_stage = 1;
						REG_WSEL	= 4'b011x;
						REG_RSEL = 4'b010x;
						M1 = 0;
					end
					5'b00_1_01,
					5'b00_1_10:
					begin
						ALU160_SEL = 1;
						WE 		= 6'b010100;
						next_stage = 1;
						M1 		= 0;
					end
					5'b00_0_10,
					5'b01_1_10:
					begin	
						DO_SEL	= 0;
						ALU160_SEL = 0;
						WE 		= 6'b000x00;
						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
						next_stage = 1;
						REG_WSEL	= {1'b0, opd[2:0]};
						REG_RSEL	= 4'b010x;
						M1 		= 0;
						WR			= 1;			
					end
					5'b01_0_10,
					5'b10_1_10:
					begin	
						ALU160_SEL = 1;
						WE 		= 6'b010x00;
					end
					5'b00_0_11, 5'b00_1_11: begin
						WE 		= 6'b000x00;
						M1 		= 0;
						MREQ		= 0;
						HALT 		= 1;
					end
				endcase

			4'b0010:	
				case({STAGE[1:0], CPUStatus[4], op0mem})
					4'b00_0_0, 4'b00_1_0,
					4'b01_0_1,
					4'b10_1_1:
					begin
						ALU160_SEL = 1;
						DINW_SEL = 0;
						WE 		= {4'b110x, ~&FETCH[5:3], 1'bx};
						ALU8OP	= {2'b00, FETCH[5:3]};
						REG_WSEL	= 4'b0110;
						REG_RSEL	= {1'b0, opd[2:0]};
					end
					4'b00_0_1,
					4'b01_1_1:
					begin
						ALU160_SEL = 0;
						DINW_SEL = 1;
						WE 		= 6'b000x01;
						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
						next_stage = 1;
						REG_WSEL	= 4'b011x;
						REG_RSEL	= 4'b010x;
						M1 		= 0;
					end
					4'b00_1_1:
					begin
						ALU160_SEL = 1;
						WE 		= 6'b010100;
						next_stage = 1;
						M1 		= 0;
					end
				endcase

			4'b0011:
				case(FETCH[3:0])

					4'b0000, 4'b1000:
						case(STAGE[1:0])
							2'b00, 2'b01:
								if(FlagMux[FETCH[5:3]]) begin
									ALU160_SEL = 0;
									DINW_SEL = 1;
									WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
									next_stage = 1;
									REG_WSEL	= 4'b111x;
									REG_RSEL	= 4'b101x;
									M1 		= 0;
								end else begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							2'b10: begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b111x;
							end
						endcase

					4'b0001:
						case(STAGE[1:0])
							2'b00, 2'b01: begin
								if(op16[2]) begin
									WE 		= STAGE[0] ? 6'b101x1x : 6'b001xx1;
									REG_WSEL	= {3'b011, STAGE[0] ? 1'b1 : 1'bx};
									if(STAGE[0]) ALU8OP	= 30;
								end else begin
									WE 		= STAGE[0] ? 6'b001x10 : 6'b001xx1;
									REG_WSEL	= {1'b0, FETCH[5:4], 1'bx};
								end
								ALU160_SEL = 0;
								DINW_SEL = 1;
								next_stage = 1;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
							end
							2'b10: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
						endcase

					4'b0010, 4'b1010:
						case(STAGE[1:0])
							2'b00, 2'b01:	begin
								if(FlagMux[FETCH[5:3]]) begin
									ALU160_SEL = 1;
									DINW_SEL = 1;
									WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
									next_stage = 1;
									REG_WSEL	= 4'b111x;
									M1 		= 0;
								end else begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
									ALU16OP	= 2;
								end
							end
							2'b10: begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b111x;
							end
						endcase

					4'b0011:
						case(FETCH[5:4])
							2'b00:
								case(STAGE[1:0])
									2'b00, 2'b01:	begin
										ALU160_SEL = 1;
										DINW_SEL = 1;
										WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
										next_stage = 1;
										REG_WSEL	= 4'b111x;
										M1 		= 0;
									end
									2'b10: begin
										ALU160_SEL = 0;
										WE 		= 6'b010x00;
										REG_RSEL	= 4'b111x;
									end
								endcase
							2'b01:
								case(STAGE[1:0])
									2'b00: begin
										ALU160_SEL = 1;
										DINW_SEL = 1;
										WE 		= 6'b010x01;
										next_stage = 1;
										REG_WSEL	= 4'b011x;
										M1 		= 0;
									end
									2'b01: begin
										DO_SEL	= 2'b00;
										ALU160_SEL = 0;
										WE 		= 6'b000x00;
										next_stage = 1;
										REG_WSEL	= 4'b0110;
										REG_RSEL	= 4'b011x;
										M1 		= 0;
										MREQ		= 0;
										WR 		= 1;
										IORQ		= 1;
									end
									2'b10: begin
										ALU160_SEL = 1;
										WE 		= 6'b010x00;
									end
								endcase
							2'b10:
								case(STAGE[2:0])
									3'b000, 3'b001:	begin
										ALU160_SEL = 0;
										DINW_SEL = 1;
										WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
										next_stage = 1;
										REG_WSEL	= 4'b111x;
										REG_RSEL	= 4'b101x;
										M1 		= 0;
									end
									3'b010, 3'b011: begin
										DO_SEL	= 2'b00;
										ALU160_SEL = 0;
										WE 		= 6'b001x00;
										ALU16OP	= 5;
										next_stage = 1;
										REG_WSEL	= {3'b010, STAGE[0]};
										REG_RSEL	= 4'b101x;
										M1 		= 0;
										WR			= 1;
									end
									3'b100, 3'b101: begin
										ALU160_SEL = 1;
										DINW_SEL = 0;
										WE 		= {1'b0, STAGE[0], 2'b0x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
										ALU8OP	= 29;
										next_stage = !STAGE[0];
										REG_WSEL	= 4'b010x;
										REG_RSEL	= {3'b111, !STAGE[0]};
										M1 		= STAGE[0];
										MREQ		= STAGE[0];
									end
								endcase
							2'b11:	begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[11] = 1'b1;
								status[7:6] = 2'b00;
							end
						endcase

					4'b0100, 4'b1100:	
						case(STAGE[2:0])
							3'b000, 3'b001:
								if(FlagMux[FETCH[5:3]]) begin
									ALU160_SEL = 1;
									DINW_SEL = 1;
									WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
									next_stage = 1;
									REG_WSEL	= 4'b111x;
									M1 		= 0;
								end else begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
									ALU16OP	= 2;
								end
							3'b010, 3'b011: begin
								DO_SEL	= {1'b0, STAGE[0]};
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= 5;
								next_stage = 1;
								REG_WSEL	= 4'b1xxx;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								WR			= 1;
							end
							3'b100:	begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b111x;
							end
						endcase

					4'b0101: 
						case(STAGE[1:0])
							2'b00, 2'b01: begin
								DO_SEL	= {STAGE[0] & op16[2], 1'b0};
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= 5;
								next_stage = 1;
								REG_WSEL	= {1'b0, FETCH[5:4], STAGE[0]};
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								WR			= 1;
							end
							2'b10: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
						endcase

					4'b0110, 4'b1110:
						if(!STAGE[0]) begin
							ALU160_SEL = 1;
							DINW_SEL = 1;
							WE 		= 6'b010x01;
							next_stage = 1;
							REG_WSEL	= 4'b011x;
							M1 		= 0;
						end else begin
							DINW_SEL = 0;
							ALU160_SEL = 1;
							WE 		= {4'b110x, ~&FETCH[5:3], 1'bx};
							ALU8OP	= {2'b00, FETCH[5:3]};
							REG_WSEL	= 4'b0110;
							REG_RSEL	= 4'b0111;
						end

					4'b0111, 4'b1111:
						case(STAGE[1:0])
							2'b00, 2'b01: begin
								DO_SEL	= {1'b0, STAGE[0]};
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= 5;
								next_stage = 1;
								REG_WSEL	= 4'b1xxx;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								WR			= 1;
							end
							2'b10:	begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b110x;
							end
						endcase

					4'b1001:	
						case(FETCH[5:4])	
							2'b00:
								case(STAGE[1:0])
									2'b00, 2'b01:	begin
										ALU160_SEL = 0;
										DINW_SEL = 1;
										WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
										next_stage = 1;
										REG_WSEL	= 4'b111x;
										REG_RSEL	= 4'b101x;
										M1 		= 0;
									end		
									2'b10: begin
										ALU160_SEL = 0;
										WE 		= 6'b010x00;
										REG_RSEL	= 4'b111x;
									end
								endcase
							2'b01: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[1] = 1;			
							end
							2'b10:	begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b010x;
							end
							2'b11: begin
								if(!STAGE[0]) begin
									ALU160_SEL = 0;
									WE 		= 6'b001x00;
									ALU16OP	= 4;
									next_stage = 1;
									REG_RSEL	= 4'b010x;
									M1 		= 0;
									MREQ		= 0;
								end else begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							end
						endcase

					4'b1011:
						case(FETCH[5:4])
							2'b00:
								case({STAGE[0], CPUStatus[4]})
									2'b00, 2'b11: begin
										ALU160_SEL = 1;
										WE 		= 6'b010000;
										fetch98 = 2'b10;		
										M1 = !CPUStatus[4];
									end
									2'b01: begin
										ALU160_SEL = 1;
										WE 		= 6'b010100;
										next_stage = 1;
										M1 		= 0;
									end
								endcase
							2'b01:
								case(STAGE[1:0])
									2'b00: begin
										ALU160_SEL = 1;
										DINW_SEL = 1;
										WE 		= 6'b010x01;
										next_stage = 1;
										REG_WSEL	= 4'b011x;
										M1 		= 0;
									end
									2'b01: begin
										ALU160_SEL = 0;
										DINW_SEL = 1;
										WE 		= 6'b000x1x;
										next_stage = 1;
										REG_WSEL	= 4'b011x;
										REG_RSEL	= 4'b011x;
										M1 		= 0;
										MREQ		= 0;
										IORQ		= 1;
									end
									2'b10: begin
										ALU160_SEL = 1;
										WE 		= 6'b010x00;
									end
								endcase
							2'b10: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								if(CPUStatus[1]) status[3] = 1;	
								else status[2] = 1;
							end
							2'b11: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[11] = 1'b1;
								status[7:6] = 2'b11;
							end
						endcase

					4'b1101:	
						case(FETCH[5:4])
							2'b00:
								case(STAGE[2:0])
									3'b000, 3'b001: begin
										ALU160_SEL = 1;
										DINW_SEL = 1;
										WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
										next_stage = 1;
										REG_WSEL	= 4'b111x;
										M1 		= 0;
									end
									3'b010, 3'b011: begin
										DO_SEL	= {1'b0, STAGE[0]};
										ALU160_SEL = 0;
										WE 		= 6'b001x00;
										ALU16OP	= 5;
										next_stage = 1;
										REG_WSEL	= 4'b1xxx;
										REG_RSEL	= 4'b101x;
										M1 		= 0;
										WR			= 1;
									end
									3'b100:	begin
										ALU160_SEL = 0;
										WE 		= 6'b010x00;
										REG_RSEL	= 4'b111x;
									end
								endcase
							2'b01: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[5:4] = 2'b01;
							end
							2'b10: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								fetch98 = 2'b01;		
							end
							2'b11:	begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[5:4]	= 2'b11;	
							end
						endcase
				endcase


			4'b0100, 4'b0111: begin
				ALU160_SEL = 1;
				WE 		= 6'b010x00;
			end
			4'b0101:
				case(FETCH[2:0])

					3'b000:
						if(!STAGE[0]) begin
							ALU160_SEL = 0;
							DINW_SEL = 1;
							WE 		= {4'b000x, !opd[3], opd[3]} ;
							next_stage = 1;
							REG_WSEL	= {1'b0, opd[5:4], 1'bx};
							REG_RSEL	= 4'b000x;
							M1 		= 0;
							MREQ		= 0;
							IORQ 		= 1;
						end else begin
							ALU160_SEL = 1;
							WE 		= 6'b110x00;
							ALU8OP	= 29;
							REG_RSEL	= {1'b0, opd[5:3]};
						end

					3'b001:
						if(!STAGE[0]) begin
							DO_SEL	= 2'b00;
							ALU160_SEL = 0;
							WE 		= 6'b000x00;
							next_stage = 1;
							REG_WSEL	= &opd[5:3] ? 4'b110x : {1'b0, opd[5:3]};
							REG_RSEL	= 4'b000x;
							M1 		= 0;
							MREQ		= 0;
							WR			= 1;
							IORQ 		= 1;
						end else begin
							ALU160_SEL = 1;
							WE 		= 6'b010x00;
						end

					3'b010:
						if(!STAGE[0]) begin
							DINW_SEL = 0;
							WE 		= 6'b100x01;
							ALU8OP	= {3'b000, !FETCH[3], 1'b1};
							next_stage = 1;
							REG_WSEL	= 4'b0101;
							REG_RSEL	= {op16, 1'b1};
							M1 		= 0;
							MREQ		= 0;
						end else begin
							ALU160_SEL = 1;
							DINW_SEL = 0;
							WE 		= 6'b110x10;
							ALU8OP	= {3'b000, !FETCH[3], 1'b1};
							REG_WSEL	= 4'b0100;
							REG_RSEL	= {op16, 1'b0};
						end

					3'b011:
						case(STAGE[2:1])
							2'b00:	begin
								ALU160_SEL = 1;
								DINW_SEL = 1;
								WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
								next_stage = 1;
								REG_WSEL	= 4'b111x;
								M1 		= 0;
							end
							2'b01: begin
								ALU160_SEL = 0;
								next_stage = 1;
								ALU16OP	= {2'b00, STAGE[0]};				
								REG_RSEL	= 4'b111x;
								REG_WSEL	= {op16, !STAGE[0]};
								M1 		= 0;
								if(FETCH[3]) begin
									DINW_SEL = 1;
									WE 		= {4'b000x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
								end else begin
									DO_SEL	= op16[2] ? {1'b1, !STAGE[0]} : 2'b00;
									WE 		= 6'b000x00;
									WR			= 1;
								end
							end
							2'b10:
								if(FETCH[3] & op16[2] & !STAGE[0]) begin
									ALU160_SEL = 0;
									WE 		= 6'b001x00;
									ALU16OP	= 4;
									next_stage = 1;
									REG_RSEL	= 4'b101x;
									M1 		= 0;
									MREQ		= 0;
								end else begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							endcase

					3'b100: begin
						ALU160_SEL = 1;
						DINW_SEL = 0;
						WE 		= 6'b110x10;
						ALU8OP	= 5'b11111;
						REG_WSEL	= 4'b011x;
						REG_RSEL	= 4'b0110;
					end

					3'b101:
						case(STAGE[1:0])
							2'b00, 2'b01:	begin
								ALU160_SEL = 0;
								DINW_SEL = 1;
								WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
								next_stage = 1;
								REG_WSEL	= 4'b111x;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
							end		
							2'b10: begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b111x;
								status[11] = 1'b1;
								status[7:6] = {CPUStatus[7], CPUStatus[7]};
							end
						endcase

					3'b110: begin
						ALU160_SEL = 1;
						WE 		= 6'b010x00;
						status[10:8] = {1'b1, FETCH[4:3]};
					end

					3'b111:
						case(FETCH[5:4])
							2'b00: begin
								ALU160_SEL = 1;
								DINW_SEL = 1'b0;
								WE 		= {4'b010x, !FETCH[3], FETCH[3]};
								ALU8OP	= 29;
								REG_WSEL	= 4'b1001;
								REG_RSEL	= 4'b0110;
							end
							2'b01: begin
								ALU160_SEL = 1;
								DINW_SEL = 1'b0;
								WE 		= 6'b110x1x;
								ALU8OP	= 29;
								REG_WSEL	= 4'b011x;
								REG_RSEL	= {3'b100, FETCH[3]};
							end
							2'b10:
								case(STAGE[1:0])
									2'b00:begin
										ALU160_SEL = 0;
										DINW_SEL = 1;
										WE 		= 6'b000x01;
										next_stage = 1;
										REG_WSEL	= 4'b011x;
										REG_RSEL	= 4'b010x;
										M1 		= 0;
									end
									2'b01: begin
										DINW_SEL = 0;
										WE 		= 6'b100x11;
										ALU8OP	= FETCH[3] ? 5'b01100 : 5'b01011;
										next_stage = 1;
										REG_WSEL	= 4'b0110;
										REG_RSEL	= 4'b0111;
										M1 		= 0;
										MREQ		= 0;
									end
									2'b10: begin
										DO_SEL	= 2'b00;
										ALU160_SEL = 0;
										WE 		= 6'b000x0x;
										next_stage = 1;
										REG_WSEL	= 4'b0111;
										REG_RSEL	= 4'b010x;
										M1 		= 0;
										WR			= 1;
									end
									2'b11: begin
										ALU160_SEL = 1;
										WE 		= 6'b010x00;
									end
								endcase
							2'b11: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
						endcase
				endcase

			4'b0110:
				if({FETCH[5], FETCH[2]} == 4'b10)
					case(FETCH[1:0])
						2'b00:
							case(STAGE[1:0])
								2'b00:	begin
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b100111;
									ALU8OP	= {4'b0111, FETCH[3]};
									next_stage = 1;
									REG_WSEL	= 4'b0100;
									REG_RSEL	= 4'b0101;
									M1 		= 0;
								end
								2'b01:	begin
									DINW_SEL = 0;
									WE 		= 6'b100011;
									ALU8OP	= 5'b01111;
									next_stage = 1;
									REG_WSEL	= 4'b0000;
									REG_RSEL	= 4'b0001;
									M1 		= 0;
									MREQ		= 0;
								end
								2'b10:	begin
									DO_SEL	= 2'b01;
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b000x11;
									ALU8OP	= {4'b0111, FETCH[3]};
									next_stage = FETCH[4] ? !FLAGS[2] : 1'b1;
									REG_WSEL	= 4'b0010;
									REG_RSEL	= 4'b0011;
									M1 		= 0;
									WR			= 1;
								end
								2'b11: begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							endcase
						2'b01:
							case(STAGE[1:0])
								2'b00: begin
									ALU160_SEL = 0;
									DINW_SEL = 1;
									WE 		= 6'b000x01;
									next_stage = 1;
									REG_WSEL	= 4'b011x;
									REG_RSEL	= 4'b010x;
									M1 		= 0;
								end
								2'b01: begin
									WE 		= 6'b100x0x;
									ALU8OP	= 7;
									next_stage = 1;
									REG_WSEL	= 4'b0110;
									REG_RSEL	= 4'b0111;
									M1 		= 0;
									MREQ		= 0;
								end
								2'b10: begin
									DINW_SEL = 0;
									WE 		= 6'b100x11;
									ALU8OP	= 5'b01111;
									next_stage = 1;
									REG_WSEL	= 4'b0000;
									REG_RSEL	= 4'b0001;
									M1 		= 0;
									MREQ		= 0;
								end
								2'b11: begin
									ALU160_SEL = 1;
									DINW_SEL = 0;
									M1 		= FETCH[4] ? (!FLAGS[2] || FLAGS[6]) : 1'b1;
									WE 		= {1'b0, M1, 4'b0x11};
									ALU8OP	= {4'b0111, FETCH[3]};
									REG_WSEL	= 4'b0100;
									REG_RSEL	= 4'b0101;
									MREQ		= M1;
								end
							endcase
						2'b10:
							case(STAGE[1:0])
								2'b00: 	begin
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b100110;
									ALU8OP	= 10;
									next_stage = 1;
									REG_WSEL	= 4'b0000;
									REG_RSEL	= 4'b000x;
									M1 		= 0;
									MREQ		= 0;
									IORQ		= 1;
								end
								2'b01:	begin
									DO_SEL	= 2'b01;
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b000x11;
									ALU8OP	= {4'b0111, FETCH[3]};
									next_stage = FETCH[4] ? FLAGS[6] : 1'b1;
									REG_WSEL	= 4'b0100;
									REG_RSEL	= 4'b0101;
									M1 		= 0;
									WR			= 1;
								end
								2'b10:	begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							endcase
						2'b11:
							case(STAGE[1:0])
								2'b00:	begin
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b000111;
									ALU8OP	= {4'b0111, FETCH[3]};
									next_stage = 1;
									REG_WSEL	= 4'b0100;
									REG_RSEL	= 4'b0101;
									M1 		= 0;
								end
								2'b01: 	begin
									DO_SEL	= 2'b01;
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b100x10;
									ALU8OP	= 10;
									next_stage = FETCH[4] ? (ALU80 == 8'b00000001) : 1'b1;
									REG_WSEL	= 4'b0000;
									REG_RSEL	= 4'b000x;
									M1 		= 0;
									MREQ		= 0;
									IORQ		= 1;
									WR			= 1;
								end
								2'b10:	begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							endcase
					endcase
				else begin
					ALU160_SEL = 1;
					WE 		= 6'b010x00;
				end

			4'b1000, 4'b1001, 4'b1010, 4'b1011:
				case({STAGE[1:0], CPUStatus[4], op0mem})				
					4'b00_0_0: begin
						DINW_SEL = 0;
						ALU160_SEL = 1;
						WE 		= {!FETCH[7], 3'b10x, FETCH[7:6] == 2'b01 ? 2'b00 : {!opd[0], opd[0]}};
						ALU8OP	= 28;
						REG_WSEL	= {1'b0, opd[2:0]};
					end
					4'b00_0_1, 4'b00_1_0, 4'b00_1_1: begin
						ALU160_SEL = 0;
						DINW_SEL = 1;
						WE 		= opd[0] ? 6'b000001 : 6'b000010;
						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
						next_stage = 1;
						REG_WSEL = FETCH[7:6] == 2'b01 ? 4'b111x : {1'b0, opd[2:0]};
						REG_RSEL	= 4'b010x;
						M1 		= 0;
					end
					4'b01_0_1, 4'b01_1_0, 4'b01_1_1:
						case(FETCH[7:6])
							2'b00, 2'b10, 2'b11: begin
								DINW_SEL = 0;
								DO_SEL	= 2'b11;
								ALU160_SEL = 0;
								WE 		= {!FETCH[7], 3'b00x, !opd[0], opd[0]};
								ALU8OP	= 28;
								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
								next_stage = 1;
								REG_WSEL	= {1'b0, opd[2:0]};
								REG_RSEL	= 4'b010x;
								M1 		= 0;
								WR			= 1;
							end
							2'b01: begin
								ALU160_SEL = 1;
								WE 		= 6'b110xxx;
								ALU8OP	= 28;
								REG_WSEL	= {3'b111, opd[0]};
							end 
						endcase
					4'b10_0_1, 4'b10_1_0, 4'b10_1_1: begin
						ALU160_SEL = 1;
						WE 		= 6'b010x00;
					end
				endcase

			4'b1110: begin
					ALU160_SEL = 0;
					DINW_SEL = 0;
					WE 		= 6'bx1xx11;
					ALU8OP	= 29;
					ALU16OP	= 4;
					REG_WSEL	= 4'b1001;
					REG_RSEL	= 4'b110x;
					M1 		= 0;
					MREQ		= 0;
					status[11:6] = 6'b110000;
				end 
			4'b1101:
				case(STAGE[1:0])
					2'b00: begin		
						ALU160_SEL = 1;
						WE 		= 6'b010x00;
						ALU16OP	= intop;
						next_stage = 1;
						M1 		= 0;
						MREQ		= 0;
					end
					2'b01, 2'b10: begin
						DO_SEL	= {1'b0, !STAGE[0]};
						ALU160_SEL = 0;
						WE 		= 6'b001x00;
						ALU16OP	= 5;
						next_stage = 1;
						REG_WSEL	= 4'b1xxx;
						REG_RSEL	= 4'b101x;
						M1 		= 0;
						WR			= 1;
						status[11]	= 1'b1;
						status[7:6] = {CPUStatus[7], 1'b0};
					end
					2'b11: begin
						ALU160_SEL = 0;
						WE 		= 6'b010x00;
						REG_RSEL	= 4'b110x;
					end
				endcase
			4'b1100:
				case(CPUStatus[9:8])
					2'b00, 2'b01, 2'b10: begin
						ALU160_SEL = 1;
						WE 		= 6'b010x00;
						ALU16OP	= intop;
						MREQ		= 0;
						IORQ		= 1;
						status[11]	= 1'b1;
						status[7:6] = 2'b0;
					end
					2'b11:
						case(STAGE[2:0])
							3'b000: begin
								ALU160_SEL = 1;
								DINW_SEL = 1;
								WE 		= 6'b010x01;
								ALU16OP	= intop;
								next_stage = 1;
								REG_WSEL	= 4'b1000;
								MREQ		= 0;
								IORQ		= 1;
								status[11]	= 1'b1;
								status[7:6] = 2'b0;
							end
							3'b001, 3'b010: begin
								DO_SEL	= {1'b0, !STAGE[0]};
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= 5;
								next_stage = 1;
								REG_WSEL	= 4'b1xxx;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								WR			= 1;
							end
							3'b011, 3'b100:	begin
								ALU160_SEL = 0;
								DINW_SEL = 1;
								WE 		= {4'b0x0x, STAGE[0] ? 1'bx : 1'b1, STAGE[0]};
								ALU16OP	= {2'b00, !STAGE[0]};
								next_stage = 1;
								REG_WSEL	= 4'b111x;
								REG_RSEL	= 4'b1000;
								M1 		= 0;
							end
							3'b101: begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b111x;
							end
						endcase
				endcase
		endcase	
	end

endmodule
module NextZ80
(
		input wire[7:0] DI,
		output wire[7:0] DO,
		output wire[15:0] ADDR,
		output reg WR,
		output reg MREQ,
		output reg IORQ,
		output reg HALT,
		output reg M1,
		input wire CLK,
		input wire RESET,
		input wire INT,
		input wire NMI,
		input	wire WAIT
);



	reg	[9:0] CPUStatus = 0;
	wire	[7:0] ALU8FLAGS;
	wire	[7:0]	FLAGS;
	wire 	[7:0] ALU80;
	wire 	[7:0] ALU81;
	wire 	[15:0]ALU160;
	wire 	[7:0] ALU161;
	wire	[15:0]ALU8OUT;

	reg 	[9:0]	FETCH = 0;
	reg 	[2:0]	STAGE = 0;
	wire	[5:0]	opd;
	wire	[2:0] op16;
	wire	op0mem = FETCH[2:0] == 6;
	wire	op1mem = FETCH[5:3] == 6;
	reg	[1:0]fetch98;


	reg	[1:0]DO_SEL;
	reg	ALU160_SEL;
	reg	DINW_SEL;
	reg 	[5:0]WE;
	reg 	[4:0] ALU8OP;
	reg 	[2:0] ALU16OP;
	reg 	next_stage;
	reg 	[3:0]REG_WSEL;
	reg 	[3:0]REG_RSEL;
	reg	[11:0]status;

	wire	[7:0]FlagMux = {FLAGS[7], !FLAGS[7], FLAGS[2], !FLAGS[2], FLAGS[0], !FLAGS[0], FLAGS[6], !FLAGS[6]};
	reg	tzf;
	reg 	FNMI = 0, SNMI = 0;
	reg 	SRESET = 0;
	reg	SINT = 0;
	wire	[2:0]intop = FETCH[1] ? 4 : (FETCH[0] ? 5 : 6);
	reg 	xmask;

	Z80Reg CPU_REGS (
		 .rstatus(CPUStatus[7:0]), 
		 .M1(M1), 
		 .WE(WE), 
		 .CLK(CLK), 
		 .ALU8OUT(ALU8OUT), 
		 .DI(DI), 
		 .DO(DO), 
		 .ADDR(ADDR), 									
		 .CONST(FETCH[7] ? {2'b00, FETCH[5:3], 3'b000} : 8'h66),
		 .ALU80(ALU80), 
		 .ALU81(ALU81), 
		 .ALU160(ALU160), 
		 .ALU161(ALU161), 
		 .ALU8FLAGS(ALU8FLAGS), 
		 .FLAGS(FLAGS),
		 .DO_SEL(DO_SEL), 
		 .ALU160_sel(ALU160_SEL), 
		 .REG_WSEL(REG_WSEL), 
		 .REG_RSEL(REG_RSEL), 
		 .DINW_SEL(DINW_SEL),
		 .XMASK(xmask),
		 .ALU16OP(ALU16OP),
		 .WAIT(WAIT)
		 );

	ALU8 CPU_ALU8 (
		 .D0(ALU80), 
		 .D1(ALU81), 
		 .FIN(FLAGS), 
		 .FOUT(ALU8FLAGS), 
		 .ALU8DOUT(ALU8OUT), 
		 .OP(ALU8OP),
		 .EXOP(FETCH[8:3]),
		 .LDIFLAGS(REG_WSEL[2]),
		 .DSTHI(!REG_WSEL[0])
		 );

	ALU16 CPU_ALU16 (
		 .D0(ALU160), 
		 .D1(ALU161), 
		 .DOUT(ADDR), 
		 .OP(ALU16OP)
		 );

	always @(posedge CLK)
		if(!WAIT) begin
			SRESET <= RESET;
			SNMI <= NMI;
			SINT <= INT;
			if(!SNMI) FNMI <= 0; 
			if(SRESET) FETCH <= 10'b1110000000;
			else 
				if(FETCH[9:6] == 4'b1110) {FETCH[9:7]} <= 3'b000;
				else begin 
					if(M1 || (fetch98 == 2'b10))
						case({MREQ, CPUStatus[9:8]})
							3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: FETCH <= {fetch98, DI};
							3'b010: FETCH <= {fetch98, 8'hff};
							3'b011: ;
						endcase
					if(~|{next_stage, fetch98[1:0], status[4]})
						if(SNMI & !FNMI) begin
							{FETCH[9:6], FETCH[1:0]} <= {4'b1101, HALT, M1};
							FNMI <= 1;
						end else if(SINT & CPUStatus[6] & !status[11]) {FETCH[9:6], FETCH[1:0]} <= {4'b1100, HALT, M1};
				end
			if(next_stage) STAGE <= STAGE + 3'b001;
			else STAGE <= 0;
			if(status[4]) CPUStatus[5:4] <= status[5:4];
			else if(~|{next_stage, fetch98[1]} | fetch98[0]) CPUStatus[4] <= 1'b0;
			CPUStatus[3:0] <= CPUStatus[3:0] ^ status[3:0];
			if(status[11]) CPUStatus[7:6] <= status[7:6];
			if(status[10]) CPUStatus[9:8] <= status[9:8];
			tzf <= ALU8FLAGS[6];
		end

	assign opd[0] = FETCH[0] ^ &FETCH[2:1];
	assign opd[2:1] = FETCH[2:1];
	assign opd[3] = FETCH[3] ^ &FETCH[5:4];
	assign opd[5:4] = FETCH[5:4];
	assign op16[2:0] = &FETCH[5:4] ? 3'b101 : {1'b0, FETCH[5:4]};

	always @* begin
		DO_SEL	= 2'bxx;
		ALU160_SEL = 1'bx;
		DINW_SEL = 1'bx;
		WE 		= 6'bxxxxxx;
		ALU8OP	= 5'bxxxxx;
		ALU16OP	= 3'b000;
		next_stage = 0;
		REG_WSEL	= 4'bxxxx;
		REG_RSEL	= 4'bx0xx;
		M1 		= 1;
		MREQ		= 1;
		WR			= 0;

		HALT = 0;
		IORQ = 0;
		status	= 12'b00xxxxx00000;
		fetch98 = 2'b00;
		
		case({FETCH[7:6], op1mem, op0mem})
			4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b1000, 4'b1100: xmask = 1;
			default: xmask = 0;
		endcase
		
		case(FETCH[9:6])	

			4'b0000:
				case(FETCH[3:0])

					4'b0000, 4'b1000:	
						case(FETCH[5:4])
							2'b00: begin
								DO_SEL	= 2'bxx;			
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[0] = FETCH[3];
							end
							2'b01:				
								if(!STAGE[0]) begin
									ALU160_SEL = 1;
									WE 		= 6'b010100;
									if(!FETCH[3]) begin
										ALU8OP	= 5'b01010;
										REG_WSEL	= 4'b0000;
									end
									next_stage = 1;
									M1 		= 0;
								end else if(FETCH[3]) begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
									ALU16OP	= 3;
								end else begin
									ALU160_SEL = 1;
									DINW_SEL = 0;
									WE 		= 6'b010x10;
									ALU8OP	= 5'b01010;
									ALU16OP	= tzf ? 3'd0 : 3'd3;
									REG_WSEL	= 4'b0000;
								end
							2'b10, 2'b11:
								case({STAGE[0], FlagMux[{1'b0, FETCH[4:3]}]})
									2'b00, 2'b11: begin
										ALU160_SEL = 1;
										WE 		= 6'b010x00;
										ALU16OP	= STAGE[0] ? 3'd3 : 3'd1;
									end 
									2'b01: begin
										ALU160_SEL = 1;
										WE 		= 6'b010100;
										next_stage = 1; 
										M1 		= 0;
									end
								endcase
						endcase

					4'b0001:
						case({STAGE[1:0], op16[2]})
							3'b00_0, 3'b00_1, 3'b01_0, 3'b01_1: begin
								ALU160_SEL = 1;
								DINW_SEL = 1;
								WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
								next_stage = 1;
								REG_WSEL	= {op16, 1'bx}; 
								M1 		= 0;
							end
							3'b10_0, 3'b11_1: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
							3'b10_1: begin
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= 4;
								next_stage = 1;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								MREQ		= 0;
							end
						endcase


					4'b0010,	4'b1010:
						case(STAGE[2:0])
							3'b000:
								if(FETCH[5] == 0) begin
									if(FETCH[3]) DINW_SEL = 1;
									else DO_SEL	= 2'b00;
									ALU160_SEL = 0;
									WE 		= {4'b000x, FETCH[3], 1'bx};
									next_stage = 1;
									REG_WSEL	= FETCH[3] ? 4'b011x : 4'b0110;
									REG_RSEL	= {op16, 1'bx};
									M1 		= 0;
									WR = !FETCH[3];
								end else begin
									ALU160_SEL = 1;
									DINW_SEL = 1;
									WE 		= 6'b010xx1;
									next_stage = 1;
									REG_WSEL	= 4'b111x;
									M1 		= 0;
								end
							3'b001:
								if(FETCH[5] == 0) begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end else begin
									ALU160_SEL = 1;
									DINW_SEL = 1;
									WE 		= 6'b010x10;
									next_stage = 1;
									REG_WSEL	= 4'b111x;
									M1 		= 0;
								end
							3'b010: begin					
								ALU160_SEL = 1'b0;
								REG_RSEL	= 4'b111x;
								M1 		= 0;
								WR			= !FETCH[3];
								next_stage = 1;
								if(FETCH[3]) begin
									DINW_SEL = 1;
									WE 		= {4'b000x, FETCH[4] ? 1'b1 : 1'bx, FETCH[4] ? 1'bx : 1'b1};
									REG_WSEL = FETCH[4] ? 4'b011x : 4'b010x;
								end else begin
									DO_SEL	= 2'b00;
									WE 		= 6'b000x00;
									REG_WSEL = FETCH[4] ? 4'b0110 : 4'b0101;
								end
							end
							3'b011:
								if(FETCH[4]) begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end else begin					
									REG_RSEL	= 4'b111x;
									M1 		= 0;
									WR			= !FETCH[3];
									ALU160_SEL = 1'b0;
									ALU16OP	= 1;
									next_stage = 1;
									if(FETCH[3]) begin
										DINW_SEL = 1;
										WE 		= 6'b000x10;
										REG_WSEL = 4'b010x;
									end else begin
										DO_SEL	= 2'b00;
										WE 		= 6'b000x00;
										REG_WSEL = 4'b0100;
									end
								end
							3'b100: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
						endcase

					4'b0011, 4'b1011:
						if(!STAGE[0])
							if(op16[2]) begin
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= {FETCH[3], 1'b0, FETCH[3]};
								next_stage = 1;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								MREQ		= 0;
							end else begin
								ALU160_SEL = 1;
								DINW_SEL = 0;
								WE 		= 6'b010x11;
								ALU8OP	= {4'b0111, FETCH[3]};
								REG_WSEL	= {op16, 1'b0};
								REG_RSEL	= {op16, 1'b1};
							end
						else 	begin
							ALU160_SEL = 1;
							WE 		= 6'b010x00;
						end

					4'b0100, 4'b0101, 4'b1100, 4'b1101: 
						if(!op1mem) begin
							DINW_SEL = 0;
							ALU160_SEL = 1;
							WE 		= opd[3] ? 6'b110x01 : 6'b110x10;
							ALU8OP	= {3'b010, FETCH[0], 1'b0};
							REG_WSEL	= {1'b0, opd[5:3]};
						end else case({STAGE[1:0], CPUStatus[4]})
							3'b00_0, 3'b01_1: begin
								ALU160_SEL = 0;
								DINW_SEL = 1;
								WE 		= 6'b000001;
								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
								next_stage = 1;
								REG_WSEL	= 4'b011x;
								REG_RSEL	= 4'b010x;
								M1 		= 0;
							end
							3'b00_1:	begin
								ALU160_SEL = 1;
								WE 		= 6'b010100;
								next_stage = 1;
								M1 		= 0;
							end 
							3'b01_0, 3'b10_1: begin
								DO_SEL	= 2'b11;
								ALU160_SEL = 0;
								WE 		= 6'b100x0x;
								ALU8OP	= {3'b010, FETCH[0], 1'b0};
								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
								next_stage = 1;
								REG_WSEL	= 4'b0111;
								REG_RSEL	= 4'b010x;
								M1 		= 0;
								WR			= 1;
							end
							3'b10_0, 3'b11_1: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
						endcase

					4'b0110, 4'b1110: 				
						case({STAGE[1:0], CPUStatus[4], op1mem})
							4'b00_0_0, 4'b00_0_1, 4'b00_1_0, 4'b01_1_1: begin
								ALU160_SEL = 1;
								DINW_SEL = 1;
								WE 		= opd[3] ? 6'b010001 : 6'b010010;
								next_stage = 1;
								REG_WSEL	= {1'b0, opd[5:4], 1'bx};
								M1 		= 0;
							end
							4'b01_0_0, 4'b01_1_0, 4'b10_0_1, 4'b11_1_1: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
							4'b01_0_1, 4'b10_1_1: begin
								DO_SEL	= 2'b00;
								ALU160_SEL = 0;
								WE 		= 6'b000x0x;
								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
								next_stage = 1;
								REG_WSEL	= 4'b0111;
								REG_RSEL	= 4'b010x;
								M1 		= 0;
								WR			= 1;
							end
							4'b00_1_1: begin
								ALU160_SEL = 1;
								WE 		= 6'b010100;
								next_stage = 1;
								M1 		= 0;
							end
						endcase

					4'b0111, 4'b1111: 				
						case(FETCH[5:3])
							3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101: begin
								ALU160_SEL = 1;
								DINW_SEL = 0;
								WE 		= 6'b110x1x;
								ALU8OP	= FETCH[5] ? {2'b01, !FETCH[3], 2'b01} : {3'b110, FETCH[4:3]};
								REG_WSEL	= 4'b0110;
							end
							3'b110, 3'b111:	begin
								ALU160_SEL = 1;
								DINW_SEL = 0;
								WE 		= 6'b110x0x;
								ALU8OP	= {4'b1010, !FETCH[3]};
							end
						endcase

					4'b1001: 
						if(!STAGE[0]) begin
							DINW_SEL = 0;
							WE 		= 6'b100x01;
							ALU8OP	= 5'b10000;
							next_stage = 1;
							REG_WSEL	= 4'b0101;
							REG_RSEL	= {op16, 1'b1};
							M1 		= 0;
							MREQ		= 0;
						end else begin
							ALU160_SEL = 1;
							DINW_SEL = 0;
							WE 		= 6'b110x10;
							ALU8OP	= 5'b10001;
							REG_WSEL	= 4'b0100;
							REG_RSEL	= {op16, 1'b0};
						end
				endcase


			4'b0001:	
				case({STAGE[1:0], CPUStatus[4], op1mem, op0mem})
					5'b00_0_00, 5'b00_1_00,
					5'b01_0_01,
					5'b10_1_01:
					begin	
						ALU160_SEL = 1;
						DINW_SEL	  = 0;
						WE = opd[3] ? 6'b010x01 : 6'b010x10;
						ALU8OP = 29;
						REG_WSEL = {1'b0, opd[5:4], 1'bx};
						REG_RSEL = {1'b0, opd[2:0]};
					end
					5'b00_0_01,
					5'b01_1_01:
					begin	
						ALU160_SEL = 0;
						DINW_SEL = 1;
						WE 		= 6'b000x01;
						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
						next_stage = 1;
						REG_WSEL	= 4'b011x;
						REG_RSEL = 4'b010x;
						M1 = 0;
					end
					5'b00_1_01,
					5'b00_1_10:
					begin
						ALU160_SEL = 1;
						WE 		= 6'b010100;
						next_stage = 1;
						M1 		= 0;
					end
					5'b00_0_10,
					5'b01_1_10:
					begin	
						DO_SEL	= 0;
						ALU160_SEL = 0;
						WE 		= 6'b000x00;
						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
						next_stage = 1;
						REG_WSEL	= {1'b0, opd[2:0]};
						REG_RSEL	= 4'b010x;
						M1 		= 0;
						WR			= 1;			
					end
					5'b01_0_10,
					5'b10_1_10:
					begin	
						ALU160_SEL = 1;
						WE 		= 6'b010x00;
					end
					5'b00_0_11, 5'b00_1_11: begin
						WE 		= 6'b000x00;
						M1 		= 0;
						MREQ		= 0;
						HALT 		= 1;
					end
				endcase

			4'b0010:	
				case({STAGE[1:0], CPUStatus[4], op0mem})
					4'b00_0_0, 4'b00_1_0,
					4'b01_0_1,
					4'b10_1_1:
					begin
						ALU160_SEL = 1;
						DINW_SEL = 0;
						WE 		= {4'b110x, ~&FETCH[5:3], 1'bx};
						ALU8OP	= {2'b00, FETCH[5:3]};
						REG_WSEL	= 4'b0110;
						REG_RSEL	= {1'b0, opd[2:0]};
					end
					4'b00_0_1,
					4'b01_1_1:
					begin
						ALU160_SEL = 0;
						DINW_SEL = 1;
						WE 		= 6'b000x01;
						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
						next_stage = 1;
						REG_WSEL	= 4'b011x;
						REG_RSEL	= 4'b010x;
						M1 		= 0;
					end
					4'b00_1_1:
					begin
						ALU160_SEL = 1;
						WE 		= 6'b010100;
						next_stage = 1;
						M1 		= 0;
					end
				endcase

			4'b0011:
				case(FETCH[3:0])

					4'b0000, 4'b1000:
						case(STAGE[1:0])
							2'b00, 2'b01:
								if(FlagMux[FETCH[5:3]]) begin
									ALU160_SEL = 0;
									DINW_SEL = 1;
									WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
									next_stage = 1;
									REG_WSEL	= 4'b111x;
									REG_RSEL	= 4'b101x;
									M1 		= 0;
								end else begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							2'b10: begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b111x;
							end
						endcase

					4'b0001:
						case(STAGE[1:0])
							2'b00, 2'b01: begin
								if(op16[2]) begin
									WE 		= STAGE[0] ? 6'b101x1x : 6'b001xx1;
									REG_WSEL	= {3'b011, STAGE[0] ? 1'b1 : 1'bx};
									if(STAGE[0]) ALU8OP	= 30;
								end else begin
									WE 		= STAGE[0] ? 6'b001x10 : 6'b001xx1;
									REG_WSEL	= {1'b0, FETCH[5:4], 1'bx};
								end
								ALU160_SEL = 0;
								DINW_SEL = 1;
								next_stage = 1;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
							end
							2'b10: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
						endcase

					4'b0010, 4'b1010:
						case(STAGE[1:0])
							2'b00, 2'b01:	begin
								if(FlagMux[FETCH[5:3]]) begin
									ALU160_SEL = 1;
									DINW_SEL = 1;
									WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
									next_stage = 1;
									REG_WSEL	= 4'b111x;
									M1 		= 0;
								end else begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
									ALU16OP	= 2;
								end
							end
							2'b10: begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b111x;
							end
						endcase

					4'b0011:
						case(FETCH[5:4])
							2'b00:
								case(STAGE[1:0])
									2'b00, 2'b01:	begin
										ALU160_SEL = 1;
										DINW_SEL = 1;
										WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
										next_stage = 1;
										REG_WSEL	= 4'b111x;
										M1 		= 0;
									end
									2'b10: begin
										ALU160_SEL = 0;
										WE 		= 6'b010x00;
										REG_RSEL	= 4'b111x;
									end
								endcase
							2'b01:
								case(STAGE[1:0])
									2'b00: begin
										ALU160_SEL = 1;
										DINW_SEL = 1;
										WE 		= 6'b010x01;
										next_stage = 1;
										REG_WSEL	= 4'b011x;
										M1 		= 0;
									end
									2'b01: begin
										DO_SEL	= 2'b00;
										ALU160_SEL = 0;
										WE 		= 6'b000x00;
										next_stage = 1;
										REG_WSEL	= 4'b0110;
										REG_RSEL	= 4'b011x;
										M1 		= 0;
										MREQ		= 0;
										WR 		= 1;
										IORQ		= 1;
									end
									2'b10: begin
										ALU160_SEL = 1;
										WE 		= 6'b010x00;
									end
								endcase
							2'b10:
								case(STAGE[2:0])
									3'b000, 3'b001:	begin
										ALU160_SEL = 0;
										DINW_SEL = 1;
										WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
										next_stage = 1;
										REG_WSEL	= 4'b111x;
										REG_RSEL	= 4'b101x;
										M1 		= 0;
									end
									3'b010, 3'b011: begin
										DO_SEL	= 2'b00;
										ALU160_SEL = 0;
										WE 		= 6'b001x00;
										ALU16OP	= 5;
										next_stage = 1;
										REG_WSEL	= {3'b010, STAGE[0]};
										REG_RSEL	= 4'b101x;
										M1 		= 0;
										WR			= 1;
									end
									3'b100, 3'b101: begin
										ALU160_SEL = 1;
										DINW_SEL = 0;
										WE 		= {1'b0, STAGE[0], 2'b0x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
										ALU8OP	= 29;
										next_stage = !STAGE[0];
										REG_WSEL	= 4'b010x;
										REG_RSEL	= {3'b111, !STAGE[0]};
										M1 		= STAGE[0];
										MREQ		= STAGE[0];
									end
								endcase
							2'b11:	begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[11] = 1'b1;
								status[7:6] = 2'b00;
							end
						endcase

					4'b0100, 4'b1100:	
						case(STAGE[2:0])
							3'b000, 3'b001:
								if(FlagMux[FETCH[5:3]]) begin
									ALU160_SEL = 1;
									DINW_SEL = 1;
									WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
									next_stage = 1;
									REG_WSEL	= 4'b111x;
									M1 		= 0;
								end else begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
									ALU16OP	= 2;
								end
							3'b010, 3'b011: begin
								DO_SEL	= {1'b0, STAGE[0]};
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= 5;
								next_stage = 1;
								REG_WSEL	= 4'b1xxx;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								WR			= 1;
							end
							3'b100:	begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b111x;
							end
						endcase

					4'b0101: 
						case(STAGE[1:0])
							2'b00, 2'b01: begin
								DO_SEL	= {STAGE[0] & op16[2], 1'b0};
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= 5;
								next_stage = 1;
								REG_WSEL	= {1'b0, FETCH[5:4], STAGE[0]};
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								WR			= 1;
							end
							2'b10: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
						endcase

					4'b0110, 4'b1110:
						if(!STAGE[0]) begin
							ALU160_SEL = 1;
							DINW_SEL = 1;
							WE 		= 6'b010x01;
							next_stage = 1;
							REG_WSEL	= 4'b011x;
							M1 		= 0;
						end else begin
							DINW_SEL = 0;
							ALU160_SEL = 1;
							WE 		= {4'b110x, ~&FETCH[5:3], 1'bx};
							ALU8OP	= {2'b00, FETCH[5:3]};
							REG_WSEL	= 4'b0110;
							REG_RSEL	= 4'b0111;
						end

					4'b0111, 4'b1111:
						case(STAGE[1:0])
							2'b00, 2'b01: begin
								DO_SEL	= {1'b0, STAGE[0]};
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= 5;
								next_stage = 1;
								REG_WSEL	= 4'b1xxx;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								WR			= 1;
							end
							2'b10:	begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b110x;
							end
						endcase

					4'b1001:	
						case(FETCH[5:4])	
							2'b00:
								case(STAGE[1:0])
									2'b00, 2'b01:	begin
										ALU160_SEL = 0;
										DINW_SEL = 1;
										WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
										next_stage = 1;
										REG_WSEL	= 4'b111x;
										REG_RSEL	= 4'b101x;
										M1 		= 0;
									end		
									2'b10: begin
										ALU160_SEL = 0;
										WE 		= 6'b010x00;
										REG_RSEL	= 4'b111x;
									end
								endcase
							2'b01: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[1] = 1;			
							end
							2'b10:	begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b010x;
							end
							2'b11: begin
								if(!STAGE[0]) begin
									ALU160_SEL = 0;
									WE 		= 6'b001x00;
									ALU16OP	= 4;
									next_stage = 1;
									REG_RSEL	= 4'b010x;
									M1 		= 0;
									MREQ		= 0;
								end else begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							end
						endcase

					4'b1011:
						case(FETCH[5:4])
							2'b00:
								case({STAGE[0], CPUStatus[4]})
									2'b00, 2'b11: begin
										ALU160_SEL = 1;
										WE 		= 6'b010000;
										fetch98 = 2'b10;		
										M1 = !CPUStatus[4];
									end
									2'b01: begin
										ALU160_SEL = 1;
										WE 		= 6'b010100;
										next_stage = 1;
										M1 		= 0;
									end
								endcase
							2'b01:
								case(STAGE[1:0])
									2'b00: begin
										ALU160_SEL = 1;
										DINW_SEL = 1;
										WE 		= 6'b010x01;
										next_stage = 1;
										REG_WSEL	= 4'b011x;
										M1 		= 0;
									end
									2'b01: begin
										ALU160_SEL = 0;
										DINW_SEL = 1;
										WE 		= 6'b000x1x;
										next_stage = 1;
										REG_WSEL	= 4'b011x;
										REG_RSEL	= 4'b011x;
										M1 		= 0;
										MREQ		= 0;
										IORQ		= 1;
									end
									2'b10: begin
										ALU160_SEL = 1;
										WE 		= 6'b010x00;
									end
								endcase
							2'b10: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								if(CPUStatus[1]) status[3] = 1;	
								else status[2] = 1;
							end
							2'b11: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[11] = 1'b1;
								status[7:6] = 2'b11;
							end
						endcase

					4'b1101:	
						case(FETCH[5:4])
							2'b00:
								case(STAGE[2:0])
									3'b000, 3'b001: begin
										ALU160_SEL = 1;
										DINW_SEL = 1;
										WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
										next_stage = 1;
										REG_WSEL	= 4'b111x;
										M1 		= 0;
									end
									3'b010, 3'b011: begin
										DO_SEL	= {1'b0, STAGE[0]};
										ALU160_SEL = 0;
										WE 		= 6'b001x00;
										ALU16OP	= 5;
										next_stage = 1;
										REG_WSEL	= 4'b1xxx;
										REG_RSEL	= 4'b101x;
										M1 		= 0;
										WR			= 1;
									end
									3'b100:	begin
										ALU160_SEL = 0;
										WE 		= 6'b010x00;
										REG_RSEL	= 4'b111x;
									end
								endcase
							2'b01: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[5:4] = 2'b01;
							end
							2'b10: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								fetch98 = 2'b01;		
							end
							2'b11:	begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
								status[5:4]	= 2'b11;	
							end
						endcase
				endcase


			4'b0100, 4'b0111: begin
				ALU160_SEL = 1;
				WE 		= 6'b010x00;
			end
			4'b0101:
				case(FETCH[2:0])

					3'b000:
						if(!STAGE[0]) begin
							ALU160_SEL = 0;
							DINW_SEL = 1;
							WE 		= {4'b000x, !opd[3], opd[3]} ;
							next_stage = 1;
							REG_WSEL	= {1'b0, opd[5:4], 1'bx};
							REG_RSEL	= 4'b000x;
							M1 		= 0;
							MREQ		= 0;
							IORQ 		= 1;
						end else begin
							ALU160_SEL = 1;
							WE 		= 6'b110x00;
							ALU8OP	= 29;
							REG_RSEL	= {1'b0, opd[5:3]};
						end

					3'b001:
						if(!STAGE[0]) begin
							DO_SEL	= 2'b00;
							ALU160_SEL = 0;
							WE 		= 6'b000x00;
							next_stage = 1;
							REG_WSEL	= &opd[5:3] ? 4'b110x : {1'b0, opd[5:3]};
							REG_RSEL	= 4'b000x;
							M1 		= 0;
							MREQ		= 0;
							WR			= 1;
							IORQ 		= 1;
						end else begin
							ALU160_SEL = 1;
							WE 		= 6'b010x00;
						end

					3'b010:
						if(!STAGE[0]) begin
							DINW_SEL = 0;
							WE 		= 6'b100x01;
							ALU8OP	= {3'b000, !FETCH[3], 1'b1};
							next_stage = 1;
							REG_WSEL	= 4'b0101;
							REG_RSEL	= {op16, 1'b1};
							M1 		= 0;
							MREQ		= 0;
						end else begin
							ALU160_SEL = 1;
							DINW_SEL = 0;
							WE 		= 6'b110x10;
							ALU8OP	= {3'b000, !FETCH[3], 1'b1};
							REG_WSEL	= 4'b0100;
							REG_RSEL	= {op16, 1'b0};
						end

					3'b011:
						case(STAGE[2:1])
							2'b00:	begin
								ALU160_SEL = 1;
								DINW_SEL = 1;
								WE 		= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
								next_stage = 1;
								REG_WSEL	= 4'b111x;
								M1 		= 0;
							end
							2'b01: begin
								ALU160_SEL = 0;
								next_stage = 1;
								ALU16OP	= {2'b00, STAGE[0]};				
								REG_RSEL	= 4'b111x;
								REG_WSEL	= {op16, !STAGE[0]};
								M1 		= 0;
								if(FETCH[3]) begin
									DINW_SEL = 1;
									WE 		= {4'b000x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
								end else begin
									DO_SEL	= op16[2] ? {1'b1, !STAGE[0]} : 2'b00;
									WE 		= 6'b000x00;
									WR			= 1;
								end
							end
							2'b10:
								if(FETCH[3] & op16[2] & !STAGE[0]) begin
									ALU160_SEL = 0;
									WE 		= 6'b001x00;
									ALU16OP	= 4;
									next_stage = 1;
									REG_RSEL	= 4'b101x;
									M1 		= 0;
									MREQ		= 0;
								end else begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							endcase

					3'b100: begin
						ALU160_SEL = 1;
						DINW_SEL = 0;
						WE 		= 6'b110x10;
						ALU8OP	= 5'b11111;
						REG_WSEL	= 4'b011x;
						REG_RSEL	= 4'b0110;
					end

					3'b101:
						case(STAGE[1:0])
							2'b00, 2'b01:	begin
								ALU160_SEL = 0;
								DINW_SEL = 1;
								WE 		= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};
								next_stage = 1;
								REG_WSEL	= 4'b111x;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
							end		
							2'b10: begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b111x;
								status[11] = 1'b1;
								status[7:6] = {CPUStatus[7], CPUStatus[7]};
							end
						endcase

					3'b110: begin
						ALU160_SEL = 1;
						WE 		= 6'b010x00;
						status[10:8] = {1'b1, FETCH[4:3]};
					end

					3'b111:
						case(FETCH[5:4])
							2'b00: begin
								ALU160_SEL = 1;
								DINW_SEL = 1'b0;
								WE 		= {4'b010x, !FETCH[3], FETCH[3]};
								ALU8OP	= 29;
								REG_WSEL	= 4'b1001;
								REG_RSEL	= 4'b0110;
							end
							2'b01: begin
								ALU160_SEL = 1;
								DINW_SEL = 1'b0;
								WE 		= 6'b110x1x;
								ALU8OP	= 29;
								REG_WSEL	= 4'b011x;
								REG_RSEL	= {3'b100, FETCH[3]};
							end
							2'b10:
								case(STAGE[1:0])
									2'b00:begin
										ALU160_SEL = 0;
										DINW_SEL = 1;
										WE 		= 6'b000x01;
										next_stage = 1;
										REG_WSEL	= 4'b011x;
										REG_RSEL	= 4'b010x;
										M1 		= 0;
									end
									2'b01: begin
										DINW_SEL = 0;
										WE 		= 6'b100x11;
										ALU8OP	= FETCH[3] ? 5'b01100 : 5'b01011;
										next_stage = 1;
										REG_WSEL	= 4'b0110;
										REG_RSEL	= 4'b0111;
										M1 		= 0;
										MREQ		= 0;
									end
									2'b10: begin
										DO_SEL	= 2'b00;
										ALU160_SEL = 0;
										WE 		= 6'b000x0x;
										next_stage = 1;
										REG_WSEL	= 4'b0111;
										REG_RSEL	= 4'b010x;
										M1 		= 0;
										WR			= 1;
									end
									2'b11: begin
										ALU160_SEL = 1;
										WE 		= 6'b010x00;
									end
								endcase
							2'b11: begin
								ALU160_SEL = 1;
								WE 		= 6'b010x00;
							end
						endcase
				endcase

			4'b0110:
				if({FETCH[5], FETCH[2]} == 4'b10)
					case(FETCH[1:0])
						2'b00:
							case(STAGE[1:0])
								2'b00:	begin
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b100111;
									ALU8OP	= {4'b0111, FETCH[3]};
									next_stage = 1;
									REG_WSEL	= 4'b0100;
									REG_RSEL	= 4'b0101;
									M1 		= 0;
								end
								2'b01:	begin
									DINW_SEL = 0;
									WE 		= 6'b100011;
									ALU8OP	= 5'b01111;
									next_stage = 1;
									REG_WSEL	= 4'b0000;
									REG_RSEL	= 4'b0001;
									M1 		= 0;
									MREQ		= 0;
								end
								2'b10:	begin
									DO_SEL	= 2'b01;
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b000x11;
									ALU8OP	= {4'b0111, FETCH[3]};
									next_stage = FETCH[4] ? !FLAGS[2] : 1'b1;
									REG_WSEL	= 4'b0010;
									REG_RSEL	= 4'b0011;
									M1 		= 0;
									WR			= 1;
								end
								2'b11: begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							endcase
						2'b01:
							case(STAGE[1:0])
								2'b00: begin
									ALU160_SEL = 0;
									DINW_SEL = 1;
									WE 		= 6'b000x01;
									next_stage = 1;
									REG_WSEL	= 4'b011x;
									REG_RSEL	= 4'b010x;
									M1 		= 0;
								end
								2'b01: begin
									WE 		= 6'b100x0x;
									ALU8OP	= 7;
									next_stage = 1;
									REG_WSEL	= 4'b0110;
									REG_RSEL	= 4'b0111;
									M1 		= 0;
									MREQ		= 0;
								end
								2'b10: begin
									DINW_SEL = 0;
									WE 		= 6'b100x11;
									ALU8OP	= 5'b01111;
									next_stage = 1;
									REG_WSEL	= 4'b0000;
									REG_RSEL	= 4'b0001;
									M1 		= 0;
									MREQ		= 0;
								end
								2'b11: begin
									ALU160_SEL = 1;
									DINW_SEL = 0;
									M1 		= FETCH[4] ? (!FLAGS[2] || FLAGS[6]) : 1'b1;
									WE 		= {1'b0, M1, 4'b0x11};
									ALU8OP	= {4'b0111, FETCH[3]};
									REG_WSEL	= 4'b0100;
									REG_RSEL	= 4'b0101;
									MREQ		= M1;
								end
							endcase
						2'b10:
							case(STAGE[1:0])
								2'b00: 	begin
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b100110;
									ALU8OP	= 10;
									next_stage = 1;
									REG_WSEL	= 4'b0000;
									REG_RSEL	= 4'b000x;
									M1 		= 0;
									MREQ		= 0;
									IORQ		= 1;
								end
								2'b01:	begin
									DO_SEL	= 2'b01;
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b000x11;
									ALU8OP	= {4'b0111, FETCH[3]};
									next_stage = FETCH[4] ? FLAGS[6] : 1'b1;
									REG_WSEL	= 4'b0100;
									REG_RSEL	= 4'b0101;
									M1 		= 0;
									WR			= 1;
								end
								2'b10:	begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							endcase
						2'b11:
							case(STAGE[1:0])
								2'b00:	begin
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b000111;
									ALU8OP	= {4'b0111, FETCH[3]};
									next_stage = 1;
									REG_WSEL	= 4'b0100;
									REG_RSEL	= 4'b0101;
									M1 		= 0;
								end
								2'b01: 	begin
									DO_SEL	= 2'b01;
									ALU160_SEL = 0;
									DINW_SEL = 0;
									WE 		= 6'b100x10;
									ALU8OP	= 10;
									next_stage = FETCH[4] ? (ALU80 == 8'b00000001) : 1'b1;
									REG_WSEL	= 4'b0000;
									REG_RSEL	= 4'b000x;
									M1 		= 0;
									MREQ		= 0;
									IORQ		= 1;
									WR			= 1;
								end
								2'b10:	begin
									ALU160_SEL = 1;
									WE 		= 6'b010x00;
								end
							endcase
					endcase
				else begin
					ALU160_SEL = 1;
					WE 		= 6'b010x00;
				end

			4'b1000, 4'b1001, 4'b1010, 4'b1011:
				case({STAGE[1:0], CPUStatus[4], op0mem})				
					4'b00_0_0: begin
						DINW_SEL = 0;
						ALU160_SEL = 1;
						WE 		= {!FETCH[7], 3'b10x, FETCH[7:6] == 2'b01 ? 2'b00 : {!opd[0], opd[0]}};
						ALU8OP	= 28;
						REG_WSEL	= {1'b0, opd[2:0]};
					end
					4'b00_0_1, 4'b00_1_0, 4'b00_1_1: begin
						ALU160_SEL = 0;
						DINW_SEL = 1;
						WE 		= opd[0] ? 6'b000001 : 6'b000010;
						ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
						next_stage = 1;
						REG_WSEL = FETCH[7:6] == 2'b01 ? 4'b111x : {1'b0, opd[2:0]};
						REG_RSEL	= 4'b010x;
						M1 		= 0;
					end
					4'b01_0_1, 4'b01_1_0, 4'b01_1_1:
						case(FETCH[7:6])
							2'b00, 2'b10, 2'b11: begin
								DINW_SEL = 0;
								DO_SEL	= 2'b11;
								ALU160_SEL = 0;
								WE 		= {!FETCH[7], 3'b00x, !opd[0], opd[0]};
								ALU8OP	= 28;
								ALU16OP	= CPUStatus[4] ? 3'd3 : 3'd0;
								next_stage = 1;
								REG_WSEL	= {1'b0, opd[2:0]};
								REG_RSEL	= 4'b010x;
								M1 		= 0;
								WR			= 1;
							end
							2'b01: begin
								ALU160_SEL = 1;
								WE 		= 6'b110xxx;
								ALU8OP	= 28;
								REG_WSEL	= {3'b111, opd[0]};
							end 
						endcase
					4'b10_0_1, 4'b10_1_0, 4'b10_1_1: begin
						ALU160_SEL = 1;
						WE 		= 6'b010x00;
					end
				endcase

			4'b1110: begin
					ALU160_SEL = 0;
					DINW_SEL = 0;
					WE 		= 6'bx1xx11;
					ALU8OP	= 29;
					ALU16OP	= 4;
					REG_WSEL	= 4'b1001;
					REG_RSEL	= 4'b110x;
					M1 		= 0;
					MREQ		= 0;
					status[11:6] = 6'b110000;
				end 
			4'b1101:
				case(STAGE[1:0])
					2'b00: begin		
						ALU160_SEL = 1;
						WE 		= 6'b010x00;
						ALU16OP	= intop;
						next_stage = 1;
						M1 		= 0;
						MREQ		= 0;
					end
					2'b01, 2'b10: begin
						DO_SEL	= {1'b0, !STAGE[0]};
						ALU160_SEL = 0;
						WE 		= 6'b001x00;
						ALU16OP	= 5;
						next_stage = 1;
						REG_WSEL	= 4'b1xxx;
						REG_RSEL	= 4'b101x;
						M1 		= 0;
						WR			= 1;
						status[11]	= 1'b1;
						status[7:6] = {CPUStatus[7], 1'b0};
					end
					2'b11: begin
						ALU160_SEL = 0;
						WE 		= 6'b010x00;
						REG_RSEL	= 4'b110x;
					end
				endcase
			4'b1100:
				case(CPUStatus[9:8])
					2'b00, 2'b01, 2'b10: begin
						ALU160_SEL = 1;
						WE 		= 6'b010x00;
						ALU16OP	= intop;
						MREQ		= 0;
						IORQ		= 1;
						status[11]	= 1'b1;
						status[7:6] = 2'b0;
					end
					2'b11:
						case(STAGE[2:0])
							3'b000: begin
								ALU160_SEL = 1;
								DINW_SEL = 1;
								WE 		= 6'b010x01;
								ALU16OP	= intop;
								next_stage = 1;
								REG_WSEL	= 4'b1000;
								MREQ		= 0;
								IORQ		= 1;
								status[11]	= 1'b1;
								status[7:6] = 2'b0;
							end
							3'b001, 3'b010: begin
								DO_SEL	= {1'b0, !STAGE[0]};
								ALU160_SEL = 0;
								WE 		= 6'b001x00;
								ALU16OP	= 5;
								next_stage = 1;
								REG_WSEL	= 4'b1xxx;
								REG_RSEL	= 4'b101x;
								M1 		= 0;
								WR			= 1;
							end
							3'b011, 3'b100:	begin
								ALU160_SEL = 0;
								DINW_SEL = 1;
								WE 		= {4'b0x0x, STAGE[0] ? 1'bx : 1'b1, STAGE[0]};
								ALU16OP	= {2'b00, !STAGE[0]};
								next_stage = 1;
								REG_WSEL	= 4'b111x;
								REG_RSEL	= 4'b1000;
								M1 		= 0;
							end
							3'b101: begin
								ALU160_SEL = 0;
								WE 		= 6'b010x00;
								REG_RSEL	= 4'b111x;
							end
						endcase
				endcase
		endcase	
	end

endmodule