data/full_repos/permissive/169615268/behav_srams.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/169615268/behav_srams.v:60: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                        : ... Top module \'mem_ext\'\nmodule mem_ext(\n       ^~~~~~~\n                                                                        : ... Top module \'mem_0_ext\'\nmodule mem_0_ext(\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/169615268/behav_srams.v:86: Cannot find file containing module: \'simpleuart\'\n simpleuart uart (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169615268,data/full_repos/permissive/169615268/simpleuart\n             data/full_repos/permissive/169615268,data/full_repos/permissive/169615268/simpleuart.v\n             data/full_repos/permissive/169615268,data/full_repos/permissive/169615268/simpleuart.sv\n             simpleuart\n             simpleuart.v\n             simpleuart.sv\n             obj_dir/simpleuart\n             obj_dir/simpleuart.v\n             obj_dir/simpleuart.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module mem_ext(
	input         W0_clk,
	input  [24:0] W0_addr,
	input         W0_en,
	input  [63:0] W0_data,
	input  [ 7:0] W0_mask,
	input         R0_clk,
	input  [24:0] R0_addr,
	input         R0_en,
	output [63:0] R0_data
);
	reg [24:0] reg_R0_addr;

	reg [63:0] ram [127:0];

	initial $readmemh("firmware.hex", ram);

	always @(posedge R0_clk)
		if (R0_en) begin
			reg_R0_addr <= R0_addr;
			`ifndef SYNTHESIS
			$display("## mem_rd: a=%h; d=%h",
				R0_addr[6:0], ram[R0_addr[6:0]]);
			`endif
		end
	always @(posedge W0_clk)
		if (W0_en) begin
			if (W0_mask[0])
				ram[W0_addr[6:0]][ 7: 0] <= W0_data[ 7: 0];
			if (W0_mask[1])
				ram[W0_addr[6:0]][15: 8] <= W0_data[15: 8];
			if (W0_mask[2])
				ram[W0_addr[6:0]][23:16] <= W0_data[23:16];
			if (W0_mask[3])
				ram[W0_addr[6:0]][31:24] <= W0_data[31:24];
			if (W0_mask[4])
				ram[W0_addr[6:0]][39:32] <= W0_data[39:32];
			if (W0_mask[5])
				ram[W0_addr[6:0]][47:40] <= W0_data[47:40];
			if (W0_mask[6])
				ram[W0_addr[6:0]][55:48] <= W0_data[55:48];
			if (W0_mask[7])
				ram[W0_addr[6:0]][63:56] <= W0_data[63:56];
			`ifndef SYNTHESIS
			$display("## mem_wr: a=%h d=%h [%b]",
				W0_addr[6:0], W0_data, W0_mask);
			`endif
		end
	assign R0_data = ram[reg_R0_addr[6:0]];
endmodule
module mem_ext(
	input         W0_clk,
	input  [24:0] W0_addr,
	input         W0_en,
	input  [63:0] W0_data,
	input  [ 7:0] W0_mask,
	input         R0_clk,
	input  [24:0] R0_addr,
	input         R0_en,
	output [63:0] R0_data
);

	reg [24:0] reg_R0_addr;

	reg [63:0] ram [127:0];

	initial $readmemh("firmware.hex", ram);

	always @(posedge R0_clk)
		if (R0_en) begin
			reg_R0_addr <= R0_addr;
			`ifndef SYNTHESIS
			$display("## mem_rd: a=%h; d=%h",
				R0_addr[6:0], ram[R0_addr[6:0]]);
			`endif
		end
	always @(posedge W0_clk)
		if (W0_en) begin
			if (W0_mask[0])
				ram[W0_addr[6:0]][ 7: 0] <= W0_data[ 7: 0];
			if (W0_mask[1])
				ram[W0_addr[6:0]][15: 8] <= W0_data[15: 8];
			if (W0_mask[2])
				ram[W0_addr[6:0]][23:16] <= W0_data[23:16];
			if (W0_mask[3])
				ram[W0_addr[6:0]][31:24] <= W0_data[31:24];
			if (W0_mask[4])
				ram[W0_addr[6:0]][39:32] <= W0_data[39:32];
			if (W0_mask[5])
				ram[W0_addr[6:0]][47:40] <= W0_data[47:40];
			if (W0_mask[6])
				ram[W0_addr[6:0]][55:48] <= W0_data[55:48];
			if (W0_mask[7])
				ram[W0_addr[6:0]][63:56] <= W0_data[63:56];
			`ifndef SYNTHESIS
			$display("## mem_wr: a=%h d=%h [%b]",
				W0_addr[6:0], W0_data, W0_mask);
			`endif
		end
	assign R0_data = ram[reg_R0_addr[6:0]];
endmodule