data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/registerSetup_19.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/registerSetup_19.v:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                         : ... In instance registerSetup_19\n  reg [31:0] M_regs_d, M_regs_q = 1\'h0;\n                                  ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/registerSetup_19.v:32: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                         : ... In instance registerSetup_19\n      M_regs_q <= 1\'h0;\n               ^~\n%Error: Exiting due to 2 warning(s)\n'
module registerSetup_19 (
    input clk,
    input en,
    input rst,
    input [31:0] data,
    output reg [31:0] out
  );
  
  
  
  reg [31:0] M_regs_d, M_regs_q = 1'h0;
  
  always @* begin
    M_regs_d = M_regs_q;
    
    if (en == 1'h1) begin
      M_regs_d = data;
    end else begin
      M_regs_d = M_regs_q;
    end
    out = M_regs_q;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_regs_q <= 1'h0;
    end else begin
      M_regs_q <= M_regs_d;
    end
  end
  
endmodule
module registerSetup_19 (
    input clk,
    input en,
    input rst,
    input [31:0] data,
    output reg [31:0] out
  );

  
  
  
  reg [31:0] M_regs_d, M_regs_q = 1'h0;
  
  always @* begin
    M_regs_d = M_regs_q;
    
    if (en == 1'h1) begin
      M_regs_d = data;
    end else begin
      M_regs_d = M_regs_q;
    end
    out = M_regs_q;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_regs_q <= 1'h0;
    end else begin
      M_regs_q <= M_regs_d;
    end
  end
  
endmodule