data/full_repos/permissive/143278/fpga_tests/ornor7.v
data/verilator_xmls/45803c40-9fd8-4894-968b-dbb27c870088.xml
module ornor7(output wire O_OR, output wire O_NOR,
	      input wire I0, I1, I2, I3, I4, I5, I6);

   assign O_OR  =  | {I0, I1, I2, I3, I4, I5, I6};
   assign O_NOR = ~| {I0, I1, I2, I3, I4, I5, I6};

endmodule
module ornor7(output wire O_OR, output wire O_NOR,
	      input wire I0, I1, I2, I3, I4, I5, I6);


   assign O_OR  =  | {I0, I1, I2, I3, I4, I5, I6};
   assign O_NOR = ~| {I0, I1, I2, I3, I4, I5, I6};

endmodule