data/full_repos/permissive/124180522/src/md.v
1: b"%Error: data/full_repos/permissive/124180522/src/md.v:32: Cannot find file containing module: 'div'\ndiv dd(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/124180522/src,data/full_repos/permissive/124180522/div\n             data/full_repos/permissive/124180522/src,data/full_repos/permissive/124180522/div.v\n             data/full_repos/permissive/124180522/src,data/full_repos/permissive/124180522/div.sv\n             div\n             div.v\n             div.sv\n             obj_dir/div\n             obj_dir/div.v\n             obj_dir/div.sv\n%Error: data/full_repos/permissive/124180522/src/md.v:44: Cannot find file containing module: 'mult_gen_0'\nmult_gen_0 mm(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/124180522/src/md.v:51: Cannot find file containing module: 'mult_gen_1'\nmult_gen_1 mm1(\n^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module md(
	input         clk,
	input         resetn,
	input  [ 3:0] md_op,
    input  [31:0] src1,
	input  [31:0] src2,
	output [63:0] result,
	output        en
);

wire        vd, vd1;
wire [63:0] dresult,  mresult;
wire [63:0] umresult;
reg  [ 3:0] lastmd_op;
wire        complete;
wire        div;

assign vd = md_op[0];
assign vd1 = md_op[1];
assign en = lastmd_op[2] | lastmd_op[3] | complete;

assign result = ({64{complete}} & dresult) |
				({64{lastmd_op[2]}} & mresult) |
				({64{lastmd_op[3]}} & umresult);
assign div = vd | vd1;

always @(posedge clk)
begin
	lastmd_op <= md_op;
end 

div dd(
	.div_clk  (clk),
	.resetn   (resetn),
	.div      (div),
	.div_signed (vd),
	.x        (src1),
	.y        (src2),
	.s        (dresult[31:0]),
	.r        (dresult[63:32]),
	.complete (complete)
);

mult_gen_0 mm(
	.CLK(clk),
	.A(src1),
	.B(src2),
	.P(mresult)
);

mult_gen_1 mm1(
	.CLK(clk),
	.A(src1),
	.B(src2),
	.P(umresult)
);
endmodule
module md(
	input         clk,
	input         resetn,
	input  [ 3:0] md_op,
    input  [31:0] src1,
	input  [31:0] src2,
	output [63:0] result,
	output        en
);


wire        vd, vd1;
wire [63:0] dresult,  mresult;
wire [63:0] umresult;
reg  [ 3:0] lastmd_op;
wire        complete;
wire        div;

assign vd = md_op[0];
assign vd1 = md_op[1];
assign en = lastmd_op[2] | lastmd_op[3] | complete;

assign result = ({64{complete}} & dresult) |
				({64{lastmd_op[2]}} & mresult) |
				({64{lastmd_op[3]}} & umresult);
assign div = vd | vd1;

always @(posedge clk)
begin
	lastmd_op <= md_op;
end 

div dd(
	.div_clk  (clk),
	.resetn   (resetn),
	.div      (div),
	.div_signed (vd),
	.x        (src1),
	.y        (src2),
	.s        (dresult[31:0]),
	.r        (dresult[63:32]),
	.complete (complete)
);

mult_gen_0 mm(
	.CLK(clk),
	.A(src1),
	.B(src2),
	.P(mresult)
);

mult_gen_1 mm1(
	.CLK(clk),
	.A(src1),
	.B(src2),
	.P(umresult)
);
endmodule