data/full_repos/permissive/138254793/test_eachModule.v
 line:58: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:38: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:39: Unsupported: Ignoring delay on this delayed statement.\n #1 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:40: Unsupported: Ignoring delay on this delayed statement.\n #1 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:41: Unsupported: Ignoring delay on this delayed statement.\n  forever #1 clk = ~clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:58: Unsupported: Ignoring delay on this delayed statement.\n #21 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:62: Unsupported: Ignoring delay on this delayed statement.\n #2  pkt_in = meta[1];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:63: Unsupported: Ignoring delay on this delayed statement.\n #2  pkt_in = meta[2];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:64: Unsupported: Ignoring delay on this delayed statement.\n #2  pkt_in = meta[3];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:65: Unsupported: Ignoring delay on this delayed statement.\n #2  pkt_in = meta[4];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:66: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in_valid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:67: Unsupported: Ignoring delay on this delayed statement.\n #60 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:71: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in = meta[1];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:72: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in = meta[2];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:73: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in = meta[3];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:74: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in = meta[5];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:75: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in = meta[4];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_eachModule.v:76: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in_valid = 1\'b0;\n ^\n%Error: data/full_repos/permissive/138254793/test_eachModule.v:24: Cannot find file containing module: \'parser\'\nparser parser(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138254793,data/full_repos/permissive/138254793/parser\n             data/full_repos/permissive/138254793,data/full_repos/permissive/138254793/parser.v\n             data/full_repos/permissive/138254793,data/full_repos/permissive/138254793/parser.sv\n             parser\n             parser.v\n             parser.sv\n             obj_dir/parser\n             obj_dir/parser.v\n             obj_dir/parser.sv\n%Warning-WIDTH: data/full_repos/permissive/138254793/test_eachModule.v:57: Operator ASSIGN expects 134 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance test_module\n pkt_in = 1\'b0;\n        ^\n%Error: Exiting due to 1 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_module(
);

parameter 		w_connTb = 68,
			d_connTb = 9,
			words_connTb = 512,
			w_hashTb = 17,
			d_hashTb = 9,
			words_hashTb = 512,
			w_flowKTb = 121,
			d_flowKTb = 9,
			words_flowKTb = 512;


reg 		clk;
reg 		reset;
reg		pkt_in_valid;
reg	[133:0]	pkt_in;
wire		pkt_out_valid;
wire	[133:0]	pkt_out;
wire		ready;

parser parser(
.clk(clk),
.reset(reset),
.metadata_in_valid(pkt_in_valid),
.metadata_in(pkt_in),
.metadata_out_valid(pkt_out_valid),
.metadata_out(pkt_out),
.ready_in(1'b1),
.ready_out(ready)
);


initial begin
	clk = 0;
	#5 reset = 1;
	#1 reset = 0;
	#1 reset = 1;
 	forever #1 clk = ~clk;
end

reg	[133:0]	meta[7:0];

initial begin
	meta[0] = {2'b01,4'd0,128'b0};

	meta[1] = {2'b01,4'd0,48'h000011112222,48'h333344445555,16'h0800,16'h4500};
	meta[2] = {2'b11,4'b0,56'b0,8'h6,16'b0,32'h00001111,16'h2222};
	meta[3] = {2'b11,4'b0,16'h3333,16'h0001,16'h0002,72'b0,8'h11};
	meta[4] = {2'b10,4'b0,128'd1};
	meta[5] = {2'b11,4'b0,128'd2};
	

    	pkt_in_valid = 1'b0;
	pkt_in = 1'b0;
	#21 begin
		pkt_in_valid = 1'b1;
		pkt_in = meta[0];
	end
	#2 	pkt_in = meta[1];
	#2 	pkt_in = meta[2];
	#2 	pkt_in = meta[3];
	#2 	pkt_in = meta[4];
	#2	pkt_in_valid = 1'b0;
	#60 begin
		pkt_in_valid = 1'b1;
		pkt_in = meta[0];
	end
	#2 pkt_in = meta[1];
	#2 pkt_in = meta[2];
	#2 pkt_in = meta[3];
	#2 pkt_in = meta[5];
	#2 pkt_in = meta[4];
	#2 pkt_in_valid = 1'b0;

end

	



endmodule
module test_module(
);


parameter 		w_connTb = 68,
			d_connTb = 9,
			words_connTb = 512,
			w_hashTb = 17,
			d_hashTb = 9,
			words_hashTb = 512,
			w_flowKTb = 121,
			d_flowKTb = 9,
			words_flowKTb = 512;


reg 		clk;
reg 		reset;
reg		pkt_in_valid;
reg	[133:0]	pkt_in;
wire		pkt_out_valid;
wire	[133:0]	pkt_out;
wire		ready;

parser parser(
.clk(clk),
.reset(reset),
.metadata_in_valid(pkt_in_valid),
.metadata_in(pkt_in),
.metadata_out_valid(pkt_out_valid),
.metadata_out(pkt_out),
.ready_in(1'b1),
.ready_out(ready)
);


initial begin
	clk = 0;
	#5 reset = 1;
	#1 reset = 0;
	#1 reset = 1;
 	forever #1 clk = ~clk;
end

reg	[133:0]	meta[7:0];

initial begin
	meta[0] = {2'b01,4'd0,128'b0};

	meta[1] = {2'b01,4'd0,48'h000011112222,48'h333344445555,16'h0800,16'h4500};
	meta[2] = {2'b11,4'b0,56'b0,8'h6,16'b0,32'h00001111,16'h2222};
	meta[3] = {2'b11,4'b0,16'h3333,16'h0001,16'h0002,72'b0,8'h11};
	meta[4] = {2'b10,4'b0,128'd1};
	meta[5] = {2'b11,4'b0,128'd2};
	

    	pkt_in_valid = 1'b0;
	pkt_in = 1'b0;
	#21 begin
		pkt_in_valid = 1'b1;
		pkt_in = meta[0];
	end
	#2 	pkt_in = meta[1];
	#2 	pkt_in = meta[2];
	#2 	pkt_in = meta[3];
	#2 	pkt_in = meta[4];
	#2	pkt_in_valid = 1'b0;
	#60 begin
		pkt_in_valid = 1'b1;
		pkt_in = meta[0];
	end
	#2 pkt_in = meta[1];
	#2 pkt_in = meta[2];
	#2 pkt_in = meta[3];
	#2 pkt_in = meta[5];
	#2 pkt_in = meta[4];
	#2 pkt_in_valid = 1'b0;

end

	



endmodule