data/full_repos/permissive/167856740/cpu/tb/registers_tb.v
 line:43: before: "integer"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n            #10 regwen = 0; rs1 = i; rs2 = i; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n            #10 $display("Register1 = %h, Data1= %h, Register2 = %h, Data2= %h", rs1, destination_1, rs2, destination_2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n           #10 regwen = 1; rd = i; source = i;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n           #10 regwen = 0;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n           #10 $display("Register = %h, Data = %h", rd, source);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #10 regwen = 0; rs1 = i; rs2 = i; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #10 $display("Register1 = %h, Data1= %h, Register2 = %h, Data2= %h", rs1, destination_1, rs2, destination_2);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #10 $display("\\nCheck that we can\'t write to x0");\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10 regwen = 1; rd = 4\'b0000; source = 32\'h99999999;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #10 $display("Register = %h, Data = %h", rd, source);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #10 regwen = 0; rd = 4\'b0000; source = 32\'h00000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #10 $display("Register = %h, Data = %h", rd, source);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:17: Cannot find file containing module: \'registers\'\n registers register(\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/registers\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/registers.v\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/registers.sv\n             registers\n             registers.v\n             registers.sv\n             obj_dir/registers\n             obj_dir/registers.v\n             obj_dir/registers.sv\n%Warning-WIDTH: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:44: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                             : ... In instance registers_tb\n            #10 regwen = 0; rs1 = i; rs2 = i; \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:44: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                             : ... In instance registers_tb\n            #10 regwen = 0; rs1 = i; rs2 = i; \n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:51: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                             : ... In instance registers_tb\n           #10 regwen = 1; rd = i; source = i;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:59: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                             : ... In instance registers_tb\n    #10 regwen = 0; rs1 = i; rs2 = i; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/167856740/cpu/tb/registers_tb.v:59: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                             : ... In instance registers_tb\n    #10 regwen = 0; rs1 = i; rs2 = i; \n                                 ^\n%Error: Exiting due to 1 error(s), 21 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module registers_tb;
	

	reg clk;
	reg reset;
	reg regwen;
	reg [3:0] rs1;
	reg [3:0] rs2;
	reg [3:0] rd;
	reg [31:0] source;
	wire [31:0] destination_1;
	wire [31:0] destination_2;


	registers register(
		.I_clk(clk),
		.I_rst(reset),
		.I_regwen(regwen),
		.I_rs1(rs1),
		.I_rs2(rs2),
		.I_rd(rd),
		.I_data(source),
		.O_data1(destination_1),
		.O_data2(destination_2)
	);


	always begin
		#5 clk = ~clk;
	end

	initial begin

		clk = 0; reset = 0; regwen = 0; rs1 = 0; rs2 = 0; rd = 0; source = 0;
        

        #10 reset = 1;
        #10 reset = 0;
        
        $display("Check that registers were cleared");
        for (integer i = 0; i < 16; i=i+1) begin
            #10 regwen = 0; rs1 = i; rs2 = i; 
            #10 $display("Register1 = %h, Data1= %h, Register2 = %h, Data2= %h", rs1, destination_1, rs2, destination_2);
        end


		$display("\nWrite values to registers");
		for (integer i = 1; i < 16; i=i+1) begin
           #10 regwen = 1; rd = i; source = i;
           #10 regwen = 0;
           #10 $display("Register = %h, Data = %h", rd, source);
        end


		$display("\nCheck values from registers");
		for (integer i = 0; i < 16; i=i+1) begin
		  #10 regwen = 0; rs1 = i; rs2 = i; 
		  #10 $display("Register1 = %h, Data1= %h, Register2 = %h, Data2= %h", rs1, destination_1, rs2, destination_2);
	    end


		#10 $display("\nCheck that we can't write to x0");
		#10 regwen = 1; rd = 4'b0000; source = 32'h99999999;
		#10 $display("Register = %h, Data = %h", rd, source);
		#10 regwen = 0; rd = 4'b0000; source = 32'h00000000;
		#10 $display("Register = %h, Data = %h", rd, source);


		#10 $finish;
	end
	
endmodule
module registers_tb;

	

	reg clk;
	reg reset;
	reg regwen;
	reg [3:0] rs1;
	reg [3:0] rs2;
	reg [3:0] rd;
	reg [31:0] source;
	wire [31:0] destination_1;
	wire [31:0] destination_2;


	registers register(
		.I_clk(clk),
		.I_rst(reset),
		.I_regwen(regwen),
		.I_rs1(rs1),
		.I_rs2(rs2),
		.I_rd(rd),
		.I_data(source),
		.O_data1(destination_1),
		.O_data2(destination_2)
	);


	always begin
		#5 clk = ~clk;
	end

	initial begin

		clk = 0; reset = 0; regwen = 0; rs1 = 0; rs2 = 0; rd = 0; source = 0;
        

        #10 reset = 1;
        #10 reset = 0;
        
        $display("Check that registers were cleared");
        for (integer i = 0; i < 16; i=i+1) begin
            #10 regwen = 0; rs1 = i; rs2 = i; 
            #10 $display("Register1 = %h, Data1= %h, Register2 = %h, Data2= %h", rs1, destination_1, rs2, destination_2);
        end


		$display("\nWrite values to registers");
		for (integer i = 1; i < 16; i=i+1) begin
           #10 regwen = 1; rd = i; source = i;
           #10 regwen = 0;
           #10 $display("Register = %h, Data = %h", rd, source);
        end


		$display("\nCheck values from registers");
		for (integer i = 0; i < 16; i=i+1) begin
		  #10 regwen = 0; rs1 = i; rs2 = i; 
		  #10 $display("Register1 = %h, Data1= %h, Register2 = %h, Data2= %h", rs1, destination_1, rs2, destination_2);
	    end


		#10 $display("\nCheck that we can't write to x0");
		#10 regwen = 1; rd = 4'b0000; source = 32'h99999999;
		#10 $display("Register = %h, Data = %h", rd, source);
		#10 regwen = 0; rd = 4'b0000; source = 32'h00000000;
		#10 $display("Register = %h, Data = %h", rd, source);


		#10 $finish;
	end
	
endmodule