data/full_repos/permissive/173099254/lab7/cod.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173099254/lab7/cod.v:35: Unsupported: Ignoring delay on this delayed statement.\nalways #5 CLK=~CLK;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab7/cod.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = i;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab7/cod.v:52: Unsupported: Ignoring delay on this delayed statement.\n   #20 A = i;\n   ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab7/cod.v:45: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                  : ... In instance ram_test\n  #20 A = i;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab7/cod.v:46: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                  : ... In instance ram_test\n  data_write = i;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab7/cod.v:52: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                  : ... In instance ram_test\n   #20 A = i;\n         ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram(A, CLK, OE, WE, DOUT);
input [3:0]A;
input CLK, OE, WE;
inout [3:0]DOUT;

reg[3:0] memorie[15:0];
reg[3:0] data_Read;

assign DOUT = data_Read;

always@(posedge CLK) begin
  if(OE == 0)
    data_Read=4'bz;
  else
  begin
    if(WE == 0)
      data_Read=memorie[A];
    else
      begin
       data_Read=4'bz;
       memorie[A]=DOUT;
      end
  end
end
endmodule
module ram(A, CLK, OE, WE, DOUT);

input [3:0]A;
input CLK, OE, WE;
inout [3:0]DOUT;

reg[3:0] memorie[15:0];
reg[3:0] data_Read;

assign DOUT = data_Read;

always@(posedge CLK) begin
  if(OE == 0)
    data_Read=4'bz;
  else
  begin
    if(WE == 0)
      data_Read=memorie[A];
    else
      begin
       data_Read=4'bz;
       memorie[A]=DOUT;
      end
  end
end
endmodule