data/full_repos/permissive/150329835/src/Arithmetic.v
1: b"%Error: data/full_repos/permissive/150329835/src/Arithmetic.v:16: Cannot find file containing module: 'MULTIPLEXER'\n MULTIPLEXER M3(OP,W[39:30],W[29:20],W[19:10],W[9:0],F);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150329835/src,data/full_repos/permissive/150329835/MULTIPLEXER\n             data/full_repos/permissive/150329835/src,data/full_repos/permissive/150329835/MULTIPLEXER.v\n             data/full_repos/permissive/150329835/src,data/full_repos/permissive/150329835/MULTIPLEXER.sv\n             MULTIPLEXER\n             MULTIPLEXER.v\n             MULTIPLEXER.sv\n             obj_dir/MULTIPLEXER\n             obj_dir/MULTIPLEXER.v\n             obj_dir/MULTIPLEXER.sv\n%Error: Exiting due to 1 error(s)\n"
module SUB(X,Y,difference);
	parameter n = 4;
	input [n-1:0] X,Y;
	wire [9:0] DP;
	wire [9:0] DN;
	wire [9:0] DN2;
	reg [n-1:0] temp;
	output reg [9:0] difference;
	wire [n:0] B;
	integer k;
	
	genvar i;
	assign B[0] = 0;
	
	generate
		for (i = 0; i < n; i = i+1)
		begin:subtractbit
			full_subtract stage(X[i],Y[i],B[i],DP[i],B[i+1]);
		end
	endgenerate
	
	always @*
	begin	
		for (k=0; k<n; k=k+1)
		begin
			temp[k] = ~DP[k];
		end
	end
	
	ADD A2(temp[n-1:0], 4'b0001, DN[9:0]);
	
	assign DN2[8:0] = DN[8:0];
	assign DN2[9] = 1;
	
	assign DP[8:n]= 5'b00000;
	assign DP[9]=0;
	
	always @*
		case(B[n])
			1'b0: difference = DP;
			1'b1: difference = DN2;
		endcase
endmodule
module SUB(X,Y,difference);

	parameter n = 4;
	input [n-1:0] X,Y;
	wire [9:0] DP;
	wire [9:0] DN;
	wire [9:0] DN2;
	reg [n-1:0] temp;
	output reg [9:0] difference;
	wire [n:0] B;
	integer k;
	
	genvar i;
	assign B[0] = 0;
	
	generate
		for (i = 0; i < n; i = i+1)
		begin:subtractbit
			full_subtract stage(X[i],Y[i],B[i],DP[i],B[i+1]);
		end
	endgenerate
	
	always @*
	begin	
		for (k=0; k<n; k=k+1)
		begin
			temp[k] = ~DP[k];
		end
	end
	
	ADD A2(temp[n-1:0], 4'b0001, DN[9:0]);
	
	assign DN2[8:0] = DN[8:0];
	assign DN2[9] = 1;
	
	assign DP[8:n]= 5'b00000;
	assign DP[9]=0;
	
	always @*
		case(B[n])
			1'b0: difference = DP;
			1'b1: difference = DN2;
		endcase
endmodule