data/full_repos/permissive/205055389/test/verga/multedge.v
 line:28: before: "Dsetup"
1: b'%Error: data/full_repos/permissive/205055389/test/verga/multedge.v:10: Unsupported or unknown PLI call: $monitor\n $monitor("%2d: Q=%h  D=%h  EN=%h  CLR=%h",$time,Q,D,EN,CLR);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/multedge.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/multedge.v:17: Unsupported: Ignoring delay on this delayed statement.\n #1 CK = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/multedge.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 CK = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/multedge.v:21: Unsupported: Ignoring delay on this delayed statement.\n #1 CK = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/multedge.v:22: Unsupported: Ignoring delay on this delayed statement.\n #2 CK = 1\'b0;\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module _GGREG8 #(Dsetup=1, Dhold=1, Dck_q=1) (Q, D, EN, CLR, CK);
input CK,EN,CLR;
input [7:0] D;
output [7:0] Q;
reg [7:0] Qreg;

  assign #Dck_q Q = Qreg;

  always @(posedge CK or negedge CLR)
    if (!CLR)
      Qreg = 0;
    else if (CK && ~EN)
      Qreg = D;

endmodule
module _GGREG8 #(Dsetup=1, Dhold=1, Dck_q=1) (Q, D, EN, CLR, CK);

input CK,EN,CLR;
input [7:0] D;
output [7:0] Q;
reg [7:0] Qreg;

  assign #Dck_q Q = Qreg;

  always @(posedge CK or negedge CLR)
    if (!CLR)
      Qreg = 0;
    else if (CK && ~EN)
      Qreg = D;

endmodule