data/full_repos/permissive/108500919/unidad_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #75;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/unidad_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/108500919/unidad_tb.v:35: Cannot find file containing module: \'unidad\'\n unidad uut(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/unidad\n             data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/unidad.v\n             data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/unidad.sv\n             unidad\n             unidad.v\n             unidad.sv\n             obj_dir/unidad\n             obj_dir/unidad.v\n             obj_dir/unidad.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module unidad_tb();
   
    reg [15:0] a1,a2,a3,a4;
    wire [15:0] y1,y2,y3,y4;
    reg reset;
    reg clk;

	parameter x1 = 16'h0004;
    parameter x2 = 16'h0003;
    parameter x3 = 16'h0002;
    parameter x4 = 16'h0001;

	unidad uut(
		.x1(x1),
		.x2(x2),
		.x3(x3),
		.x4(x4),		
		.a1(a1),
		.a2(a2),
		.a3(a3),
		.a4(a4),
		.reset(reset),
		.clk(clk),		
		.y1(y1),
		.y2(y2),
		.y3(y3),
		.y4(y4)
		
		);

	always begin
		clk = 1'b1;
		#50;
		clk = 1'b0;
		#50;
		end

initial begin
	
	reset = 1'b1;
	#75;
	reset = 1'b0;
	#25;
	a1 = 16'h0001;
	a2 = 16'h0008;
	a3 = 16'h000a;
	a4 = 16'h000f;
	#100;
	a1 = 16'h0002;
	a2 = 16'h0005;
	a3 = 16'h0009;
	a4 = 16'h000e;
	#100;
	a1 = 16'h0003;
	a2 = 16'h0006;
	a3 = 16'h000c;
	a4 = 16'h000d;
	#100;

	a1 = 16'h0004;
	a2 = 16'h0007;
	a3 = 16'h000b;
	a4 = 16'h0010;
	#100;
	end

endmodule
module unidad_tb();

   
    reg [15:0] a1,a2,a3,a4;
    wire [15:0] y1,y2,y3,y4;
    reg reset;
    reg clk;

	parameter x1 = 16'h0004;
    parameter x2 = 16'h0003;
    parameter x3 = 16'h0002;
    parameter x4 = 16'h0001;

	unidad uut(
		.x1(x1),
		.x2(x2),
		.x3(x3),
		.x4(x4),		
		.a1(a1),
		.a2(a2),
		.a3(a3),
		.a4(a4),
		.reset(reset),
		.clk(clk),		
		.y1(y1),
		.y2(y2),
		.y3(y3),
		.y4(y4)
		
		);

	always begin
		clk = 1'b1;
		#50;
		clk = 1'b0;
		#50;
		end

initial begin
	
	reset = 1'b1;
	#75;
	reset = 1'b0;
	#25;
	a1 = 16'h0001;
	a2 = 16'h0008;
	a3 = 16'h000a;
	a4 = 16'h000f;
	#100;
	a1 = 16'h0002;
	a2 = 16'h0005;
	a3 = 16'h0009;
	a4 = 16'h000e;
	#100;
	a1 = 16'h0003;
	a2 = 16'h0006;
	a3 = 16'h000c;
	a4 = 16'h000d;
	#100;

	a1 = 16'h0004;
	a2 = 16'h0007;
	a3 = 16'h000b;
	a4 = 16'h0010;
	#100;
	end

endmodule