data/full_repos/permissive/136510272/projects/04_charvideo_32x24/vga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/04_charvideo_32x24/vga.v:43: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance vga\nreg [9:0] x = 1\'b0;          \n              ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/04_charvideo_32x24/vga.v:44: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance vga\nreg [9:0] y = 1\'b0;\n              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/04_charvideo_32x24/vga.v:56: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 9 bits.\n                                                                                         : ... In instance vga\nwire [7:0] X = x[9:1] - 24;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/04_charvideo_32x24/vga.v:57: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 9 bits.\n                                                                                         : ... In instance vga\nwire [7:0] Y = y[9:1] - 24;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/04_charvideo_32x24/vga.v:95: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance vga\n    x <= x == (horiz_whole - 1) ? 1\'b0 : (x + 1\'b1);\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/04_charvideo_32x24/vga.v:101: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                          : ... In instance vga\n        y <= y == (vert_whole - 1) ? 1\'b0 : (y + 1\'b1);\n                                   ^\n%Error: Exiting due to 6 warning(s)\n'
module vga(


    input   wire        clk,


    output  reg  [4:0]  red,
    output  reg  [5:0]  green,
    output  reg  [4:0]  blue,
    output  wire        hs,
    output  wire        vs,


    output  reg  [ 9:0] video_addr,
    input   wire [ 7:0] video_data,
    output  reg  [10:0] char_addr,
    input   wire [ 7:0] char_data
    
);




parameter horiz_visible = 640;
parameter horiz_back    = 48;
parameter horiz_sync    = 96;
parameter horiz_front   = 16;
parameter horiz_whole   = 800;



parameter vert_visible = 480;
parameter vert_back    = 33;
parameter vert_sync    = 2;
parameter vert_front   = 10;
parameter vert_whole   = 525;


assign hs = x >= (horiz_visible + horiz_front) && x < (horiz_visible + horiz_front + horiz_sync);
assign vs = y >= (vert_visible  + vert_front)  && y < (vert_visible  + vert_front  + vert_sync);


reg [9:0] x = 1'b0;
reg [9:0] y = 1'b0;
reg [1:0] clock_divider;


always @(posedge clk) clock_divider <= clock_divider + 1'b1;


reg [7:0] current_char;
reg [7:0] current_attr;
reg [7:0] current_char_temp;


wire [7:0] X = x[9:1] - 24;
wire [7:0] Y = y[9:1] - 24;


wire current_bit = current_char[ 7 ^ X[2:0] ];



wire [3:0] cur_color = (current_bit ? current_attr[3:0] : current_attr[7:4]);


wire [15:0] color = 

    cur_color == 4'd0 ?  { 5'h03, 6'h03, 5'h03 } :
    cur_color == 4'd1 ?  { 5'h00, 6'h00, 5'h0F } :
    cur_color == 4'd2 ?  { 5'h00, 6'h1F, 5'h00 } :
    cur_color == 4'd3 ?  { 5'h00, 6'h1F, 5'h0F } :
    cur_color == 4'd4 ?  { 5'h0F, 6'h00, 5'h00 } :
    cur_color == 4'd5 ?  { 5'h0F, 6'h00, 5'h0F } :
    cur_color == 4'd6 ?  { 5'h0F, 6'h1F, 5'h00 } :
    cur_color == 4'd7 ?  { 5'h0F, 6'h1F, 5'h0F } :
    cur_color == 4'd8 ?  { 5'h07, 6'h0F, 5'h07 } :
    cur_color == 4'd9 ?  { 5'h00, 6'h00, 5'h1F } :
    cur_color == 4'd10 ? { 5'h00, 6'h3F, 5'h00 } :
    cur_color == 4'd11 ? { 5'h00, 6'h3F, 5'h1F } :
    cur_color == 4'd12 ? { 5'h1F, 6'h00, 5'h00 } :
    cur_color == 4'd13 ? { 5'h1F, 6'h00, 5'h1F } :
    cur_color == 4'd14 ? { 5'h1F, 6'h3F, 5'h00 } :
                         { 5'h1F, 6'h3F, 5'h1F };






always @(posedge clock_divider[1]) begin



    x <= x == (horiz_whole - 1) ? 1'b0 : (x + 1'b1);
    

    if (x == (horiz_whole - 1)) begin
    

        y <= y == (vert_whole - 1) ? 1'b0 : (y + 1'b1);

    end
    


    
    case (x[3:0])


        4'b0000: video_addr <= { Y[7:3], X[7:3] };
        

        4'b0001: char_addr <= {video_data, Y[2:0]};
        

        4'b0010: current_char_temp <= char_data;
        



        4'b0011: video_addr <= { 2'b11, Y[7:4], X[7:4] };


        4'b1111: begin

            current_char <= current_char_temp;            
            current_attr <= video_data;

        end

    endcase
    

    if (x < horiz_visible && y < vert_visible) begin
    
        if (x >= 64 && x < (64 + 512) && y >= 48 && y < (48 + 384)) begin
        



            {red, green, blue} <= color;
        

        end else begin

            {red, green, blue} <= {5'h03, 6'h03, 5'h03}; 
        
        end
    


    end else {red, green, blue} <= 16'h0000;
    
end

endmodule
module vga(


    input   wire        clk,


    output  reg  [4:0]  red,
    output  reg  [5:0]  green,
    output  reg  [4:0]  blue,
    output  wire        hs,
    output  wire        vs,


    output  reg  [ 9:0] video_addr,
    input   wire [ 7:0] video_data,
    output  reg  [10:0] char_addr,
    input   wire [ 7:0] char_data
    
);





parameter horiz_visible = 640;
parameter horiz_back    = 48;
parameter horiz_sync    = 96;
parameter horiz_front   = 16;
parameter horiz_whole   = 800;



parameter vert_visible = 480;
parameter vert_back    = 33;
parameter vert_sync    = 2;
parameter vert_front   = 10;
parameter vert_whole   = 525;


assign hs = x >= (horiz_visible + horiz_front) && x < (horiz_visible + horiz_front + horiz_sync);
assign vs = y >= (vert_visible  + vert_front)  && y < (vert_visible  + vert_front  + vert_sync);


reg [9:0] x = 1'b0;
reg [9:0] y = 1'b0;
reg [1:0] clock_divider;


always @(posedge clk) clock_divider <= clock_divider + 1'b1;


reg [7:0] current_char;
reg [7:0] current_attr;
reg [7:0] current_char_temp;


wire [7:0] X = x[9:1] - 24;
wire [7:0] Y = y[9:1] - 24;


wire current_bit = current_char[ 7 ^ X[2:0] ];



wire [3:0] cur_color = (current_bit ? current_attr[3:0] : current_attr[7:4]);


wire [15:0] color = 

    cur_color == 4'd0 ?  { 5'h03, 6'h03, 5'h03 } :
    cur_color == 4'd1 ?  { 5'h00, 6'h00, 5'h0F } :
    cur_color == 4'd2 ?  { 5'h00, 6'h1F, 5'h00 } :
    cur_color == 4'd3 ?  { 5'h00, 6'h1F, 5'h0F } :
    cur_color == 4'd4 ?  { 5'h0F, 6'h00, 5'h00 } :
    cur_color == 4'd5 ?  { 5'h0F, 6'h00, 5'h0F } :
    cur_color == 4'd6 ?  { 5'h0F, 6'h1F, 5'h00 } :
    cur_color == 4'd7 ?  { 5'h0F, 6'h1F, 5'h0F } :
    cur_color == 4'd8 ?  { 5'h07, 6'h0F, 5'h07 } :
    cur_color == 4'd9 ?  { 5'h00, 6'h00, 5'h1F } :
    cur_color == 4'd10 ? { 5'h00, 6'h3F, 5'h00 } :
    cur_color == 4'd11 ? { 5'h00, 6'h3F, 5'h1F } :
    cur_color == 4'd12 ? { 5'h1F, 6'h00, 5'h00 } :
    cur_color == 4'd13 ? { 5'h1F, 6'h00, 5'h1F } :
    cur_color == 4'd14 ? { 5'h1F, 6'h3F, 5'h00 } :
                         { 5'h1F, 6'h3F, 5'h1F };






always @(posedge clock_divider[1]) begin



    x <= x == (horiz_whole - 1) ? 1'b0 : (x + 1'b1);
    

    if (x == (horiz_whole - 1)) begin
    

        y <= y == (vert_whole - 1) ? 1'b0 : (y + 1'b1);

    end
    


    
    case (x[3:0])


        4'b0000: video_addr <= { Y[7:3], X[7:3] };
        

        4'b0001: char_addr <= {video_data, Y[2:0]};
        

        4'b0010: current_char_temp <= char_data;
        



        4'b0011: video_addr <= { 2'b11, Y[7:4], X[7:4] };


        4'b1111: begin

            current_char <= current_char_temp;            
            current_attr <= video_data;

        end

    endcase
    

    if (x < horiz_visible && y < vert_visible) begin
    
        if (x >= 64 && x < (64 + 512) && y >= 48 && y < (48 + 384)) begin
        



            {red, green, blue} <= color;
        

        end else begin

            {red, green, blue} <= {5'h03, 6'h03, 5'h03}; 
        
        end
    


    end else {red, green, blue} <= 16'h0000;
    
end

endmodule