data/full_repos/permissive/159479522/led_shine.v
'utf-8' codec can't decode byte 0xd7 in position 700: invalid continuation byte
1: b'%Warning-WIDTH: data/full_repos/permissive/159479522/led_shine.v:43: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 6 bits.\n                                                                   : ... In instance led_shine\n  num[3]=time_now%10;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159479522/led_shine.v:44: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 6 bits.\n                                                                   : ... In instance led_shine\n  num[4]=time_now/10;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/159479522/led_shine.v:46: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 6 bits.\n                                                                   : ... In instance led_shine\n  num[6]=time_all%10;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/159479522/led_shine.v:47: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 6 bits.\n                                                                   : ... In instance led_shine\n  num[7]=time_all/10;\n        ^\n%Error: data/full_repos/permissive/159479522/led_shine.v:49: Cannot find file containing module: \'bin27seg\'\n    bin27seg  L1(num[0],yimahou[0]);\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/bin27seg\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/bin27seg.v\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/bin27seg.sv\n             bin27seg\n             bin27seg.v\n             bin27seg.sv\n             obj_dir/bin27seg\n             obj_dir/bin27seg.v\n             obj_dir/bin27seg.sv\n%Error: data/full_repos/permissive/159479522/led_shine.v:50: Cannot find file containing module: \'bin27seg\'\n    bin27seg  L2(num[1],yimahou[1]);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/159479522/led_shine.v:51: Cannot find file containing module: \'bin27seg\'\n    bin27seg  L3(num[2],yimahou[2]);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/159479522/led_shine.v:52: Cannot find file containing module: \'bin27seg\'\n    bin27seg  L4(num[3],yimahou[3]);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/159479522/led_shine.v:53: Cannot find file containing module: \'bin27seg\'\n    bin27seg  L5(num[4],yimahou[4]);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/159479522/led_shine.v:54: Cannot find file containing module: \'bin27seg\'\n    bin27seg  L6(num[5],yimahou[5]);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/159479522/led_shine.v:55: Cannot find file containing module: \'bin27seg\'\n    bin27seg  L7(num[6],yimahou[6]);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/159479522/led_shine.v:56: Cannot find file containing module: \'bin27seg\'\n    bin27seg  L8(num[7],yimahou[7]);\n    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/159479522/led_shine.v:58: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 4 bits.\n                                                                   : ... In instance led_shine\n    which<=(which+1)%8;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/159479522/led_shine.v:116: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 6 bits.\n                                                                    : ... In instance led_shine\n      num[3]=time_now%10;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/159479522/led_shine.v:117: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 6 bits.\n                                                                    : ... In instance led_shine\n      num[4]=time_now/10;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/159479522/led_shine.v:119: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 6 bits.\n                                                                    : ... In instance led_shine\n      num[6]=time_all%10;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/159479522/led_shine.v:120: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 6 bits.\n                                                                    : ... In instance led_shine\n      num[7]=time_all/10;\n            ^\n%Error: Exiting due to 8 error(s), 9 warning(s)\n'
module led_shine(clk,clk_KHZ,reset,if_finish,counter_power,water_level,time_now,power_off,time_all,state,count);
 input wire clk;
 input  wire clk_KHZ;
 input wire  power_off,if_finish,reset;
 input wire [3:0]counter_power;
 input  wire [3:0]water_level; 
 input  wire [5:0]time_now,time_all;
 output reg [7:0] state;
 output reg [7:0] count;

   reg [2:0] which;   
   reg [3:0] num[7:0];  
   wire  [7:0] yimahou[7:0];

  initial begin
  which=0;
  state<=8'b11111111;
  count<=8'b00000000;
  num[0]=water_level%10;
  num[1]=water_level/10;
  num[2]=10;
  num[3]=time_now%10;
  num[4]=time_now/10;
  num[5]=10;
  num[6]=time_all%10;
  num[7]=time_all/10;
  end
    bin27seg  L1(num[0],yimahou[0]);
    bin27seg  L2(num[1],yimahou[1]);
    bin27seg  L3(num[2],yimahou[2]);
    bin27seg  L4(num[3],yimahou[3]);
    bin27seg  L5(num[4],yimahou[4]);
    bin27seg  L6(num[5],yimahou[5]);
    bin27seg  L7(num[6],yimahou[6]);
    bin27seg  L8(num[7],yimahou[7]);
  always @(posedge clk_KHZ)
    which<=(which+1)%8;
   
   always @(posedge clk_KHZ)
    begin
    if(power_off==1||reset==0)
      state<=8'b11111111;
      else begin
       case(which)
              3'b000: begin
              state =8'b11111110;
              count =yimahou[0];
               end
              3'b001: begin
              state =8'b11111101;
              count=yimahou[1];
              end
              3'b010: begin
              state =8'b11111011;
              count=yimahou[2];
              end
              3'b011:begin
               state =8'b11110111;
               count=yimahou[3];
               end
              3'b100: begin
              state =8'b11101111;
              count=yimahou[4];
              end
              3'b101:begin
               state =8'b11011111;
               count=yimahou[5];
               end
              3'b110: begin
              state =8'b10111111;
              count=yimahou[6];
              end
              3'b111:begin
              state =8'b01111111;
              count=yimahou[7];
              end
            endcase
          end
          end 
  always@(posedge clk_KHZ)   begin
  if(if_finish==1)begin
    num[0]=10;
      num[1]=10;
      num[2]=10;
      num[3]=10;
      num[4]=10;
      num[5]=10;
      num[6]=counter_power;
      num[7]=counter_power/10;
      end
      else begin
      num[0]=water_level%10;
      num[1]=water_level/10;
      num[2]=10;
      num[3]=time_now%10;
      num[4]=time_now/10;
      num[5]=10;
      num[6]=time_all%10;
      num[7]=time_all/10;
    end
      end
endmodule
module led_shine(clk,clk_KHZ,reset,if_finish,counter_power,water_level,time_now,power_off,time_all,state,count);

 input wire clk;
 input  wire clk_KHZ;
 input wire  power_off,if_finish,reset;
 input wire [3:0]counter_power;
 input  wire [3:0]water_level; 
 input  wire [5:0]time_now,time_all;
 output reg [7:0] state;
 output reg [7:0] count;

   reg [2:0] which;   
   reg [3:0] num[7:0];  
   wire  [7:0] yimahou[7:0];

  initial begin
  which=0;
  state<=8'b11111111;
  count<=8'b00000000;
  num[0]=water_level%10;
  num[1]=water_level/10;
  num[2]=10;
  num[3]=time_now%10;
  num[4]=time_now/10;
  num[5]=10;
  num[6]=time_all%10;
  num[7]=time_all/10;
  end
    bin27seg  L1(num[0],yimahou[0]);
    bin27seg  L2(num[1],yimahou[1]);
    bin27seg  L3(num[2],yimahou[2]);
    bin27seg  L4(num[3],yimahou[3]);
    bin27seg  L5(num[4],yimahou[4]);
    bin27seg  L6(num[5],yimahou[5]);
    bin27seg  L7(num[6],yimahou[6]);
    bin27seg  L8(num[7],yimahou[7]);
  always @(posedge clk_KHZ)
    which<=(which+1)%8;
   
   always @(posedge clk_KHZ)
    begin
    if(power_off==1||reset==0)
      state<=8'b11111111;
      else begin
       case(which)
              3'b000: begin
              state =8'b11111110;
              count =yimahou[0];
               end
              3'b001: begin
              state =8'b11111101;
              count=yimahou[1];
              end
              3'b010: begin
              state =8'b11111011;
              count=yimahou[2];
              end
              3'b011:begin
               state =8'b11110111;
               count=yimahou[3];
               end
              3'b100: begin
              state =8'b11101111;
              count=yimahou[4];
              end
              3'b101:begin
               state =8'b11011111;
               count=yimahou[5];
               end
              3'b110: begin
              state =8'b10111111;
              count=yimahou[6];
              end
              3'b111:begin
              state =8'b01111111;
              count=yimahou[7];
              end
            endcase
          end
          end 
  always@(posedge clk_KHZ)   begin
  if(if_finish==1)begin
    num[0]=10;
      num[1]=10;
      num[2]=10;
      num[3]=10;
      num[4]=10;
      num[5]=10;
      num[6]=counter_power;
      num[7]=counter_power/10;
      end
      else begin
      num[0]=water_level%10;
      num[1]=water_level/10;
      num[2]=10;
      num[3]=time_now%10;
      num[4]=time_now/10;
      num[5]=10;
      num[6]=time_all%10;
      num[7]=time_all/10;
    end
      end
endmodule