data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit.v
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data/verilator_xmls/ad4fab92-a57c-4e71-9602-c1ffe0c6842d.xml
module RAM_8bit(out, clock, address, in, chip_select, write_enable);


	parameter ADDR_WIDTH = 8;
	parameter RAM_DEPTH = 1 << ADDR_WIDTH;
	input clock, chip_select, write_enable;
	input [ADDR_WIDTH-1:0] address;
	input [7:0] in;
	output [7:0] out;
	

	reg [7:0] mem_out;

	reg [7:0] mem [0:RAM_DEPTH-1];
	


	assign out = chip_select ? mem_out : 8'b0;
	

	always @(posedge clock) begin
		mem_out = mem[address];
	end
	

	always @(posedge clock) begin
		if(chip_select && write_enable)
			mem[address] = in;
	end
endmodule
module RAM_8bit(out, clock, address, in, chip_select, write_enable);



	parameter ADDR_WIDTH = 8;
	parameter RAM_DEPTH = 1 << ADDR_WIDTH;
	input clock, chip_select, write_enable;
	input [ADDR_WIDTH-1:0] address;
	input [7:0] in;
	output [7:0] out;
	

	reg [7:0] mem_out;

	reg [7:0] mem [0:RAM_DEPTH-1];
	


	assign out = chip_select ? mem_out : 8'b0;
	

	always @(posedge clock) begin
		mem_out = mem[address];
	end
	

	always @(posedge clock) begin
		if(chip_select && write_enable)
			mem[address] = in;
	end
endmodule