data/full_repos/permissive/111258339/test/Datapath/RF_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk<=~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:35: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                             : ... In instance RF_tb\n    RFWr = 4\'b0;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:36: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                             : ... In instance RF_tb\n    WA1 = 4\'b0;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:37: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                             : ... In instance RF_tb\n    RA1 = 4\'b0;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:38: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                             : ... In instance RF_tb\n    RA2 = 4\'b0;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:40: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                             : ... In instance RF_tb\n    RD1_output = 4\'b0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:41: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                             : ... In instance RF_tb\n    RD2_output = 4\'b0;\n               ^\n%Error: data/full_repos/permissive/111258339/test/Datapath/RF_tb.v:49: Cannot find file containing module: \'RF\'\n  RF RF0(\n  ^~\n        ... Looked in:\n             data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/RF\n             data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/RF.v\n             data/full_repos/permissive/111258339/test/Datapath,data/full_repos/permissive/111258339/RF.sv\n             RF\n             RF.v\n             RF.sv\n             obj_dir/RF\n             obj_dir/RF.v\n             obj_dir/RF.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RF_tb();
  `timescale  1ns/1ps
  
  reg clk;
  reg RFWr;

    reg [4:0]WA1;

    reg [4:0]RA1;
    reg [4:0]RA2;

    reg [31:0]WD;

    wire [31:0]RD1;
    wire [31:0]RD2;
    reg [31:0]RD1_tmp;
    reg [31:0]RD2_tmp;

    reg [31:0]RD1_output;
    reg [31:0]RD2_output;
  
  integer fd, line_count;
  
  initial
  begin
    clk = 1;
    line_count = 0;
    
    RFWr = 4'b0;
    WA1 = 4'b0;
    RA1 = 4'b0;
    RA2 = 4'b0;
    WD = 32'b0;
    RD1_output = 4'b0;
    RD2_output = 4'b0;
    
    fd=$fopen("test/data/Datapath/rf_td.txt","r");
  end
  
  always
    #1 clk<=~clk;
  
  RF RF0(
    .clk(clk),
    .RFWr(RFWr),
    .WA1(WA1),
    .RA1(RA1),
    .RA2(RA2),
    .WD(WD),
    .RD1(RD1),
    .RD2(RD2)
  );
  
  always@(posedge clk)
  
  begin
    line_count <= line_count + 1;
    
    RD1_tmp = RD1[31:0];
    RD2_tmp = RD2[31:0];
    if (RD1_output != RD1_tmp)
      begin
        $display("testcase failed! RD1: %x, RD1_output: %x", RD1_tmp, RD1_output);
        $stop;
      end
    if (RD2_output != RD2_tmp)
      begin
        $display("testcase failed! RD2: %x, RD2_output: %x", RD2_tmp, RD2_output);
        $stop;
      end
    
    $fscanf(fd, "0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t", RA1, RA2, RFWr, WA1, WD, RD1_output, RD2_output);
    $display(
      "testcase: 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t Getdata: 0x%x\t0x%x",
      RA1, RA2, RFWr, WA1, WD, RD1_output, RD2_output, RD1_tmp, RD2_tmp
    );
    
    if ($feof(fd))
    begin
      $fclose(fd);
      $display("pass!");
      $stop;
    end
  end
  
endmodule
module RF_tb();

  `timescale  1ns/1ps
  
  reg clk;
  reg RFWr;

    reg [4:0]WA1;

    reg [4:0]RA1;
    reg [4:0]RA2;

    reg [31:0]WD;

    wire [31:0]RD1;
    wire [31:0]RD2;
    reg [31:0]RD1_tmp;
    reg [31:0]RD2_tmp;

    reg [31:0]RD1_output;
    reg [31:0]RD2_output;
  
  integer fd, line_count;
  
  initial
  begin
    clk = 1;
    line_count = 0;
    
    RFWr = 4'b0;
    WA1 = 4'b0;
    RA1 = 4'b0;
    RA2 = 4'b0;
    WD = 32'b0;
    RD1_output = 4'b0;
    RD2_output = 4'b0;
    
    fd=$fopen("test/data/Datapath/rf_td.txt","r");
  end
  
  always
    #1 clk<=~clk;
  
  RF RF0(
    .clk(clk),
    .RFWr(RFWr),
    .WA1(WA1),
    .RA1(RA1),
    .RA2(RA2),
    .WD(WD),
    .RD1(RD1),
    .RD2(RD2)
  );
  
  always@(posedge clk)
  
  begin
    line_count <= line_count + 1;
    
    RD1_tmp = RD1[31:0];
    RD2_tmp = RD2[31:0];
    if (RD1_output != RD1_tmp)
      begin
        $display("testcase failed! RD1: %x, RD1_output: %x", RD1_tmp, RD1_output);
        $stop;
      end
    if (RD2_output != RD2_tmp)
      begin
        $display("testcase failed! RD2: %x, RD2_output: %x", RD2_tmp, RD2_output);
        $stop;
      end
    
    $fscanf(fd, "0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t", RA1, RA2, RFWr, WA1, WD, RD1_output, RD2_output);
    $display(
      "testcase: 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t Getdata: 0x%x\t0x%x",
      RA1, RA2, RFWr, WA1, WD, RD1_output, RD2_output, RD1_tmp, RD2_tmp
    );
    
    if ($feof(fd))
    begin
      $fclose(fd);
      $display("pass!");
      $stop;
    end
  end
  
endmodule