data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/synthesis/de10_lite/de10_lite.v
1: b"%Error: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/synthesis/de10_lite/de10_lite.v:13: Cannot find file containing module: 'dff_async_rst_n_param'\n    dff_async_rst_n_param \n    ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/synthesis/de10_lite,data/full_repos/permissive/110151336/dff_async_rst_n_param\n             data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/synthesis/de10_lite,data/full_repos/permissive/110151336/dff_async_rst_n_param.v\n             data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/synthesis/de10_lite,data/full_repos/permissive/110151336/dff_async_rst_n_param.sv\n             dff_async_rst_n_param\n             dff_async_rst_n_param.v\n             dff_async_rst_n_param.sv\n             obj_dir/dff_async_rst_n_param\n             obj_dir/dff_async_rst_n_param.v\n             obj_dir/dff_async_rst_n_param.sv\n%Error: Exiting due to 1 error(s)\n"
module de10_lite
(
    input         ADC_CLK_10,
    input         MAX10_CLK1_50,
    input         MAX10_CLK2_50,

    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LEDR
);
    assign LEDR[0] = 1'b0;

    dff_async_rst_n_param 
    #(
        .WIDTH ( 8     ), 
        .RESET ( 8'hf0 )
    ) 
    dff_async_rst_n_param
    (
        .clk   ( ~KEY  [0]   ),
        .rst_n (  SW   [0]   ),
        .d     (  SW   [9:1] ),
        .q     (  LEDR [9:1] )
    );

endmodule
module de10_lite
(
    input         ADC_CLK_10,
    input         MAX10_CLK1_50,
    input         MAX10_CLK2_50,

    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LEDR
);

    assign LEDR[0] = 1'b0;

    dff_async_rst_n_param 
    #(
        .WIDTH ( 8     ), 
        .RESET ( 8'hf0 )
    ) 
    dff_async_rst_n_param
    (
        .clk   ( ~KEY  [0]   ),
        .rst_n (  SW   [0]   ),
        .d     (  SW   [9:1] ),
        .q     (  LEDR [9:1] )
    );

endmodule