data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v
 line:98: before: ","
1: b'%Error: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:2: Cannot find include file: mux81a.v\n`include "mux81a.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab7/res,data/full_repos/permissive/20270692/mux81a.v\n             data/full_repos/permissive/20270692/labs/lab7/res,data/full_repos/permissive/20270692/mux81a.v.v\n             data/full_repos/permissive/20270692/labs/lab7/res,data/full_repos/permissive/20270692/mux81a.v.sv\n             mux81a.v\n             mux81a.v.v\n             mux81a.v.sv\n             obj_dir/mux81a.v\n             obj_dir/mux81a.v.v\n             obj_dir/mux81a.v.sv\n%Error: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:30: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n      fp=$fopen("./chap4p32a_tb.out");\n         ^~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:31: Unsupported or unknown PLI call: $fmonitor\n      $fmonitor(fp,"time=%0d",$time,,"I=%b S=%b Y=%b",I,S,Y);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:31: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      $fmonitor(fp,"time=%0d",$time,,"I=%b S=%b Y=%b",I,S,Y);\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #2000\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab7/res/chap4p32a_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n  initial #4000 $finish;\n          ^\n%Error: Exiting due to 4 error(s), 17 warning(s)\n'
module chap4p32a_tb (S);

  output [0:3] S;
  reg [0:3] S;



  wire [0:7] I;
  wire Y;

  integer fp;


  assign I[0]=~S[3];
  assign I[1]=~S[3];
  assign I[2]=S[3];
  assign I[3]=S[3];
  assign I[4]=1'b0;
  assign I[5]=S[3];
  assign I[6]=1'b0;
  assign I[7]=~S[3];

  mux81a I1 (I,S[0:2],Y);

  initial
    begin
      fp=$fopen("./chap4p32a_tb.out");
      $fmonitor(fp,"time=%0d",$time,,"I=%b S=%b Y=%b",I,S,Y);
      #2000
      $fclose(fp);
      $finish;
    end

  initial
    begin
      S=4'b0000;
      #100
      S=4'b0001;
      #100
      S=4'b0010;
      #100
      S=4'b0011;
      #100
      S=4'b0100;
      #100
      S=4'b0101;
      #100
      S=4'b0110;
      #100
      S=4'b0111;
      #100
      S=4'b1000;
      #100
      S=4'b1001;
      #100
      S=4'b1010;
      #100
      S=4'b1011;
      #100
      S=4'b1100;
      #100
      S=4'b1101;
      #100
      S=4'b1110;
      #100
      S=4'b1111;
    end

  initial #4000 $finish;

endmodule
module chap4p32a_tb (S);


  output [0:3] S;
  reg [0:3] S;



  wire [0:7] I;
  wire Y;

  integer fp;


  assign I[0]=~S[3];
  assign I[1]=~S[3];
  assign I[2]=S[3];
  assign I[3]=S[3];
  assign I[4]=1'b0;
  assign I[5]=S[3];
  assign I[6]=1'b0;
  assign I[7]=~S[3];

  mux81a I1 (I,S[0:2],Y);

  initial
    begin
      fp=$fopen("./chap4p32a_tb.out");
      $fmonitor(fp,"time=%0d",$time,,"I=%b S=%b Y=%b",I,S,Y);
      #2000
      $fclose(fp);
      $finish;
    end

  initial
    begin
      S=4'b0000;
      #100
      S=4'b0001;
      #100
      S=4'b0010;
      #100
      S=4'b0011;
      #100
      S=4'b0100;
      #100
      S=4'b0101;
      #100
      S=4'b0110;
      #100
      S=4'b0111;
      #100
      S=4'b1000;
      #100
      S=4'b1001;
      #100
      S=4'b1010;
      #100
      S=4'b1011;
      #100
      S=4'b1100;
      #100
      S=4'b1101;
      #100
      S=4'b1110;
      #100
      S=4'b1111;
    end

  initial #4000 $finish;

endmodule