data/full_repos/permissive/162338081/DebounceFlipFlop_D.v
data/verilator_xmls/7cb65250-00a1-46c3-a862-00ddf2de10b7.xml
module DebounceFlipFlop_D(CLK, D, Q);
    input CLK;
    input D;
    output reg Q;
    always @ (posedge CLK) begin
        Q <= D;
    end
endmodule
module DebounceFlipFlop_D(CLK, D, Q);

    input CLK;
    input D;
    output reg Q;
    always @ (posedge CLK) begin
        Q <= D;
    end
endmodule