data/full_repos/permissive/143278/ivltests/pr1570451.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1570451.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #1 bus = 2\'b00;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1570451.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #11 if (skewed_bus !== 2\'b00) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1570451.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #4 if (skewed_bus !== 2\'b00) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1570451.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #2 if (skewed_bus !== 2\'b01) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1570451.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #5 if (skewed_bus !== 2\'b11) begin\n      ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

  reg [1:0] bus;
  reg [1:0] skewed_bus;

  integer delay0;  initial delay0 = 5;
  integer delay1;  initial delay1 = 10;



  always @( bus[0] )
    begin
      skewed_bus[0] <= #delay0 bus[0];
    end

   always @( bus[1] )
    begin
      skewed_bus[1] <= #delay1 bus[1];
    end

   initial begin
      #1 bus = 2'b00;
      #11 if (skewed_bus !== 2'b00) begin
	 $display("FAILED -- setup failed.");
	 $finish;
      end

      bus = 2'b11;

      #4 if (skewed_bus !== 2'b00) begin
	 $display("FAILED -- changed far too soon");
	 $finish;
      end

      #2 if (skewed_bus !== 2'b01) begin
	 $display("FAILED -- partial change not right.");
	 $finish;
      end

      #5 if (skewed_bus !== 2'b11) begin
	 $display("FAILED -- final change not right");
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module test;


  reg [1:0] bus;
  reg [1:0] skewed_bus;

  integer delay0;  initial delay0 = 5;
  integer delay1;  initial delay1 = 10;



  always @( bus[0] )
    begin
      skewed_bus[0] <= #delay0 bus[0];
    end

   always @( bus[1] )
    begin
      skewed_bus[1] <= #delay1 bus[1];
    end

   initial begin
      #1 bus = 2'b00;
      #11 if (skewed_bus !== 2'b00) begin
	 $display("FAILED -- setup failed.");
	 $finish;
      end

      bus = 2'b11;

      #4 if (skewed_bus !== 2'b00) begin
	 $display("FAILED -- changed far too soon");
	 $finish;
      end

      #2 if (skewed_bus !== 2'b01) begin
	 $display("FAILED -- partial change not right.");
	 $finish;
      end

      #5 if (skewed_bus !== 2'b11) begin
	 $display("FAILED -- final change not right");
	 $finish;
      end

      $display("PASSED");
   end
endmodule