data/full_repos/permissive/212020337/d_ff.v
data/verilator_xmls/008165ab-aebf-493c-b6a6-879d4f80e6f6.xml
module d_ff(
    output reg Q,
    input      D,
    input      clk
    );
    
    always @(posedge clk)
    begin
        Q <= D;
    end    

endmodule
module d_ff(
    output reg Q,
    input      D,
    input      clk
    );

    
    always @(posedge clk)
    begin
        Q <= D;
    end    

endmodule