data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v
 line:83: before: "("
1: b'%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:12: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("wf_five2one.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:14: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, tb_five2one);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:17: Unsupported or unknown PLI call: $monitor\n      $monitor(rxdata,": %h %h %h %b", rxdata,out1,out2,rx_en);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:49: Unsupported: Ignoring delay on this delayed statement.\n #cycle;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #cycle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:59: Unsupported: Ignoring delay on this delayed statement.\n #cycle;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:65: Unsupported: Ignoring delay on this delayed statement.\n #3 clk = !clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:66: Unsupported: Ignoring delay on this delayed statement.\n #5 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:71: Unsupported: Ignoring delay on this delayed statement.\n#cycle;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:73: Unsupported: Ignoring delay on this delayed statement.\n#cycle;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:75: Unsupported: Ignoring delay on this delayed statement.\n#cycle;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:78: Unsupported: Ignoring delay on this delayed statement.\n#(cycle*20);\n^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #(cycle*20);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:87: Unsupported: Ignoring delay on this delayed statement.\n #(cycle*30);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #(cycle*20);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:96: Unsupported: Ignoring delay on this delayed statement.\n #(cycle*30);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #(cycle*20);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:105: Unsupported: Ignoring delay on this delayed statement.\n #(cycle*30);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #(cycle*20);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_five2one.v:113: Unsupported: Ignoring delay on this delayed statement.\n #(cycle*30);\n ^\n%Error: Exiting due to 3 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_five2one;

reg clk,rst,rx_en;
reg [7:0] rxdata;
wire [7:0] out1,out2;


initial
  begin

      $dumpfile("wf_five2one.vcd");

      $dumpvars(0, tb_five2one);


      $monitor(rxdata,": %h %h %h %b", rxdata,out1,out2,rx_en);
	end


wire lost,en_out;
wire [7:0] data_out;
wire [3:0] rx_id;
wire [3:0] rx_id_inter;
wire [2:0] comp3bit;
reg [3:0] switches = 4'b1;
reg clk125MHz;

parameter whereis_id = 0;
five2one #(.whereisid(whereis_id)) uut (
	.clk(clk),
	.rst(rst),
	.rx_en_w(rx_en),
	.rxdata_w(rxdata),
	.en_out(en_out),

	.data_out(data_out),
	.lost(lost)
);

integer i,j,k;
parameter cycle = 16;
parameter packetsize = 35;

task onepacket;
	input [7:0] id;
	input [31:0] seed;
begin
	#cycle;
	rx_en = 1;
	for (i=0; i < packetsize; i=i+1) begin
		if (i == whereis_id)
			rxdata = id;

		 else	rxdata = ((seed+3) * packetsize *33)%255;
		#cycle;
	end
	rx_en = 0;
	#cycle;

end
endtask

always begin
	#3 clk = !clk;
	#5 ;
end

initial begin
clk=0;rx_en=0;rxdata=0;rst=0;
#cycle;
rst = 1;
#cycle;
rst = 0;
#cycle;


#(cycle*20);

for (k=1; k<=8; k=k+1) begin
	for (j=1; j<=5; j=j+1) begin
		if (j+1 != k && j+2 != k) 
			onepacket(j,k);
		#(cycle*20);
	end

	#(cycle*30);
end

for (k=1; k<=8; k=k+1) begin
	for (j=1; j<=5; j=j+1) begin
		if (j != k && j+2 != k) 
			onepacket(j,k);
		#(cycle*20);
	end
	#(cycle*30);
end

for (k=1; k<=8; k=k+1) begin
	for (j=1; j<=5; j=j+1) begin
		if (j != k && j+3 != k) 
			onepacket(j,k);
		#(cycle*20);
	end
	#(cycle*30);
end
for (k=1; k<=8; k=k+1) begin
	for (j=1; j<=5; j=j+1) begin
		if (j != k && j+3 != k && j+1 != k) 
			onepacket(j,k);
		#(cycle*20);
	end
	#(cycle*30);
end

$finish;
end
endmodule
module tb_five2one;


reg clk,rst,rx_en;
reg [7:0] rxdata;
wire [7:0] out1,out2;


initial
  begin

      $dumpfile("wf_five2one.vcd");

      $dumpvars(0, tb_five2one);


      $monitor(rxdata,": %h %h %h %b", rxdata,out1,out2,rx_en);
	end


wire lost,en_out;
wire [7:0] data_out;
wire [3:0] rx_id;
wire [3:0] rx_id_inter;
wire [2:0] comp3bit;
reg [3:0] switches = 4'b1;
reg clk125MHz;

parameter whereis_id = 0;
five2one #(.whereisid(whereis_id)) uut (
	.clk(clk),
	.rst(rst),
	.rx_en_w(rx_en),
	.rxdata_w(rxdata),
	.en_out(en_out),

	.data_out(data_out),
	.lost(lost)
);

integer i,j,k;
parameter cycle = 16;
parameter packetsize = 35;

task onepacket;
	input [7:0] id;
	input [31:0] seed;
begin
	#cycle;
	rx_en = 1;
	for (i=0; i < packetsize; i=i+1) begin
		if (i == whereis_id)
			rxdata = id;

		 else	rxdata = ((seed+3) * packetsize *33)%255;
		#cycle;
	end
	rx_en = 0;
	#cycle;

end
endtask

always begin
	#3 clk = !clk;
	#5 ;
end

initial begin
clk=0;rx_en=0;rxdata=0;rst=0;
#cycle;
rst = 1;
#cycle;
rst = 0;
#cycle;


#(cycle*20);

for (k=1; k<=8; k=k+1) begin
	for (j=1; j<=5; j=j+1) begin
		if (j+1 != k && j+2 != k) 
			onepacket(j,k);
		#(cycle*20);
	end

	#(cycle*30);
end

for (k=1; k<=8; k=k+1) begin
	for (j=1; j<=5; j=j+1) begin
		if (j != k && j+2 != k) 
			onepacket(j,k);
		#(cycle*20);
	end
	#(cycle*30);
end

for (k=1; k<=8; k=k+1) begin
	for (j=1; j<=5; j=j+1) begin
		if (j != k && j+3 != k) 
			onepacket(j,k);
		#(cycle*20);
	end
	#(cycle*30);
end
for (k=1; k<=8; k=k+1) begin
	for (j=1; j<=5; j=j+1) begin
		if (j != k && j+3 != k && j+1 != k) 
			onepacket(j,k);
		#(cycle*20);
	end
	#(cycle*30);
end

$finish;
end
endmodule