data/full_repos/permissive/117851934/ddr_layout_V5/patern.v
data/verilator_xmls/7b9a51f9-9a0b-49a8-9c86-5a7a887be1d8.xml
module data_generator( in_clk, out_data,data_clk);  
   input in_clk;
   output [27:0]out_data;
   output data_clk;
	
 assign out_data= 28'b1; 
 assign data_clk=in_clk;
 
 endmodule
module data_generator( in_clk, out_data,data_clk);
  
   input in_clk;
   output [27:0]out_data;
   output data_clk;
	
 assign out_data= 28'b1; 
 assign data_clk=in_clk;
 
 endmodule