data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/eight_bit_uc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/eight_bit_uc.v:39: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                                                                                   : ... In instance eight_bit_uc\nassign rtcc = 7\'h0;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/eight_bit_uc.v:41: Cannot find file containing module: \'ins_decode\'\nins_decode decode (.clk2(clk2), .resetn(resetn), .aluz(aluz), .inst(inst), .f_we(f_we), .w_we(w_we),\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr,data/full_repos/permissive/158500878/ins_decode\n             data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr,data/full_repos/permissive/158500878/ins_decode.v\n             data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr,data/full_repos/permissive/158500878/ins_decode.sv\n             ins_decode\n             ins_decode.v\n             ins_decode.sv\n             obj_dir/ins_decode\n             obj_dir/ins_decode.v\n             obj_dir/ins_decode.sv\n%Error: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/eight_bit_uc.v:48: Cannot find file containing module: \'prgm_cntr\'\nprgm_cntr prgmcntr ( .clk4(clk4), .resetn(resetn), .inst(inst), .k(k), .fin(aluout), .pc(pc) );\n^~~~~~~~~\n%Error: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/eight_bit_uc.v:52: Cannot find file containing module: \'reg_file\'\nreg_file regs (.clk(clk1), .f_we(f_we), .fsel(fsel), .fin(aluout), .regfile_out(regfile_out));\n^~~~~~~~\n%Error: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/eight_bit_uc.v:57: Cannot find file containing module: \'data_mux\'\ndata_mux  dmux  ( .clk2(clk2), .resetn(resetn), .fsr(fsr), .rtcc(rtcc), .pc(pc[7:0]), .status(status), .porta(porta),\n^~~~~~~~\n%Error: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/eight_bit_uc.v:65: Cannot find file containing module: \'alu\'\nalu uc_alu ( .clk3(clk3), .resetn(resetn), .status0(status[0]), .aluop(aluop), .alua(alua), .alub(alub), \n^~~\n%Error: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/eight_bit_uc.v:70: Cannot find file containing module: \'ins_rom\'\nins_rom rom (.addr(pc), .Data(romdata));\n^~~~~~~\n%Error: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/eight_bit_uc.v:74: Cannot find file containing module: \'spcl_regs\'\nspcl_regs special_regs ( .clk1(clk1), .clk4(clk4), .resetn(resetn), .aluz(aluz), .alu_cout(alu_cout), .skip(skip),\n^~~~~~~~~\n%Error: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/eight_bit_uc.v:83: Cannot find file containing module: \'io\'\nio io_buff ( .porta(porta), .portb(portb), .portc(portc),\n^~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module eight_bit_uc ( clock, resetn, porta, portb, portc );

input clock, resetn;

inout [7:0] porta, portb, portc;

wire resetn, aluz;
wire [11:0] inst;
wire f_we, w_we, status_z_we, status_c_we, tris_we, skip;
wire [7:0] k;
wire [4:0] fsel;
wire [8:0] longk;
wire [3:0] aluop;
wire [1:0] alua_sel, alub_sel;
wire bdpol;
wire [2:0] b_mux;
wire  [7:0] fin;
wire [10:0] pc;
wire [7:0] regfile_out;
wire [7:0] fsr, rtcc;
wire [7:0] status, porta, portb, portc, w;
wire [7:0] alua, alub;
wire alu_cout;
wire [7:0] aluout;
wire [11:0] romdata;				
wire [7:0] port_int_a;
wire [7:0] port_int_b;
wire [7:0] port_int_c;
wire [7:0] trisa;
wire [7:0] trisb;
wire [7:0] trisc;

wire clk1, clk2, clk3, clk4;

assign clk1 = clock;
assign clk2 = clock;
assign clk3 = clock;
assign clk4 = clock;
assign rtcc = 7'h0;

ins_decode decode (.clk2(clk2), .resetn(resetn), .aluz(aluz), .inst(inst), .f_we(f_we), .w_we(w_we),
                    .status_z_we(status_z_we), .status_c_we(status_c_we), .tris_we(tris_we),
					.skip(skip), .k(k), .fsel(fsel), .longk(longk), .aluop(aluop), 
					.alua_sel(alua_sel), .alub_sel(alub_sel), .bdpol(bdpol), .b_mux(b_mux) );



prgm_cntr prgmcntr ( .clk4(clk4), .resetn(resetn), .inst(inst), .k(k), .fin(aluout), .pc(pc) );



reg_file regs (.clk(clk1), .f_we(f_we), .fsel(fsel), .fin(aluout), .regfile_out(regfile_out));




data_mux  dmux  ( .clk2(clk2), .resetn(resetn), .fsr(fsr), .rtcc(rtcc), .pc(pc[7:0]), .status(status), .porta(porta),
                  .portb(portb), .portc(portc), .regfile_out(regfile_out), .w(w),
 				  .k(k), .fsel(fsel), .aluout(aluout), .alua_sel(alua_sel), .alub_sel(alub_sel),
				  .b_mux(b_mux), .bdpol(bdpol), .alua(alua), .alub(alub), .fin(fin) );




alu uc_alu ( .clk3(clk3), .resetn(resetn), .status0(status[0]), .aluop(aluop), .alua(alua), .alub(alub), 
             .alu_cout(alu_cout), .aluz(aluz), .aluout(aluout));



ins_rom rom (.addr(pc), .Data(romdata));



spcl_regs special_regs ( .clk1(clk1), .clk4(clk4), .resetn(resetn), .aluz(aluz), .alu_cout(alu_cout), .skip(skip),
                         .w_we(w_we), .status_c_we(status_c_we), .status_z_we(status_z_we),
						 .tris_we(tris_we), .f_we(f_we), .aluout(aluout), .romdata(romdata),
						 .fsel(fsel), .fin(aluout), .port_int_a(port_int_a), .port_int_b(port_int_b), 
						 .port_int_c(port_int_c), .trisa(trisa), .trisb(trisb), .trisc(trisc),
						 .status(status), .w(w), .fsr(fsr), .inst(inst) );



io io_buff ( .porta(porta), .portb(portb), .portc(portc),
             .port_int_a(port_int_a), .port_int_b(port_int_b), .port_int_c(port_int_c), 
		     .trisa(trisa), .trisb(trisb), .trisc(trisc) );

endmodule
module eight_bit_uc ( clock, resetn, porta, portb, portc );


input clock, resetn;

inout [7:0] porta, portb, portc;

wire resetn, aluz;
wire [11:0] inst;
wire f_we, w_we, status_z_we, status_c_we, tris_we, skip;
wire [7:0] k;
wire [4:0] fsel;
wire [8:0] longk;
wire [3:0] aluop;
wire [1:0] alua_sel, alub_sel;
wire bdpol;
wire [2:0] b_mux;
wire  [7:0] fin;
wire [10:0] pc;
wire [7:0] regfile_out;
wire [7:0] fsr, rtcc;
wire [7:0] status, porta, portb, portc, w;
wire [7:0] alua, alub;
wire alu_cout;
wire [7:0] aluout;
wire [11:0] romdata;				
wire [7:0] port_int_a;
wire [7:0] port_int_b;
wire [7:0] port_int_c;
wire [7:0] trisa;
wire [7:0] trisb;
wire [7:0] trisc;

wire clk1, clk2, clk3, clk4;

assign clk1 = clock;
assign clk2 = clock;
assign clk3 = clock;
assign clk4 = clock;
assign rtcc = 7'h0;

ins_decode decode (.clk2(clk2), .resetn(resetn), .aluz(aluz), .inst(inst), .f_we(f_we), .w_we(w_we),
                    .status_z_we(status_z_we), .status_c_we(status_c_we), .tris_we(tris_we),
					.skip(skip), .k(k), .fsel(fsel), .longk(longk), .aluop(aluop), 
					.alua_sel(alua_sel), .alub_sel(alub_sel), .bdpol(bdpol), .b_mux(b_mux) );



prgm_cntr prgmcntr ( .clk4(clk4), .resetn(resetn), .inst(inst), .k(k), .fin(aluout), .pc(pc) );



reg_file regs (.clk(clk1), .f_we(f_we), .fsel(fsel), .fin(aluout), .regfile_out(regfile_out));




data_mux  dmux  ( .clk2(clk2), .resetn(resetn), .fsr(fsr), .rtcc(rtcc), .pc(pc[7:0]), .status(status), .porta(porta),
                  .portb(portb), .portc(portc), .regfile_out(regfile_out), .w(w),
 				  .k(k), .fsel(fsel), .aluout(aluout), .alua_sel(alua_sel), .alub_sel(alub_sel),
				  .b_mux(b_mux), .bdpol(bdpol), .alua(alua), .alub(alub), .fin(fin) );




alu uc_alu ( .clk3(clk3), .resetn(resetn), .status0(status[0]), .aluop(aluop), .alua(alua), .alub(alub), 
             .alu_cout(alu_cout), .aluz(aluz), .aluout(aluout));



ins_rom rom (.addr(pc), .Data(romdata));



spcl_regs special_regs ( .clk1(clk1), .clk4(clk4), .resetn(resetn), .aluz(aluz), .alu_cout(alu_cout), .skip(skip),
                         .w_we(w_we), .status_c_we(status_c_we), .status_z_we(status_z_we),
						 .tris_we(tris_we), .f_we(f_we), .aluout(aluout), .romdata(romdata),
						 .fsel(fsel), .fin(aluout), .port_int_a(port_int_a), .port_int_b(port_int_b), 
						 .port_int_c(port_int_c), .trisa(trisa), .trisb(trisb), .trisc(trisc),
						 .status(status), .w(w), .fsr(fsr), .inst(inst) );



io io_buff ( .porta(porta), .portb(portb), .portc(portc),
             .port_int_a(port_int_a), .port_int_b(port_int_b), .port_int_c(port_int_c), 
		     .trisa(trisa), .trisb(trisb), .trisc(trisc) );

endmodule