data/full_repos/permissive/153877566/test_bench_crc.v
 line:53: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/153877566/test_bench_crc.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/153877566/test_bench_crc.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #20000 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/153877566/test_bench_crc.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #200 clk=~clk;\n  ^\n%Error: data/full_repos/permissive/153877566/test_bench_crc.v:35: Cannot find file containing module: \'crc_192bits\'\n crc_192bits uut (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/153877566,data/full_repos/permissive/153877566/crc_192bits\n             data/full_repos/permissive/153877566,data/full_repos/permissive/153877566/crc_192bits.v\n             data/full_repos/permissive/153877566,data/full_repos/permissive/153877566/crc_192bits.sv\n             crc_192bits\n             crc_192bits.v\n             crc_192bits.sv\n             obj_dir/crc_192bits\n             obj_dir/crc_192bits.v\n             obj_dir/crc_192bits.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module text_crc192;


	reg [175:0] data_in;
	reg clk;


	wire [191:0]data_out;


	crc_192bits uut (
		.data_in(data_in), 
		.clk(clk), 
		.data_out(data_out)
	);

	initial begin

		data_in = 176'hABCDEF0123456789FEDCBA9876543210ABCDEF123456;
		clk = 0;


		#100;
        


	end
       initial
		#20000 $finish;
		always
		#200 clk=~clk;
endmodule
module text_crc192;



	reg [175:0] data_in;
	reg clk;


	wire [191:0]data_out;


	crc_192bits uut (
		.data_in(data_in), 
		.clk(clk), 
		.data_out(data_out)
	);

	initial begin

		data_in = 176'hABCDEF0123456789FEDCBA9876543210ABCDEF123456;
		clk = 0;


		#100;
        


	end
       initial
		#20000 $finish;
		always
		#200 clk=~clk;
endmodule