data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v
 line:193: before: "wire"
1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:124: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:152: Unsupported: Ignoring delay on this delayed statement.\n    #40;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:155: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:172: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:175: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:189: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n       ^\n%Error: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:31: Cannot find file containing module: \'MAC_top_level\'\nMAC_top_level MAC_top_level_0(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_top_level\n             data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_top_level.v\n             data/full_repos/permissive/106583614/Final_project_mac,data/full_repos/permissive/106583614/MAC_top_level.sv\n             MAC_top_level\n             MAC_top_level.v\n             MAC_top_level.sv\n             obj_dir/MAC_top_level\n             obj_dir/MAC_top_level.v\n             obj_dir/MAC_top_level.sv\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:51: Operator ADD expects 25 bits on the RHS, but RHS\'s VARREF \'num_b\' generates 8 bits.\n                                                                                           : ... In instance tb_Control_unit\n  check_tri <= (((num_a*num_x) + num_b)*num_x) + num_c;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:51: Operator ADD expects 25 bits on the RHS, but RHS\'s VARREF \'num_c\' generates 8 bits.\n                                                                                           : ... In instance tb_Control_unit\n  check_tri <= (((num_a*num_x) + num_b)*num_x) + num_c;\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:97: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_Control_unit\n  num_a_test[2] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:98: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_Control_unit\n  num_x_test[2] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:99: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                           : ... In instance tb_Control_unit\n  num_b_test[2] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:100: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb_Control_unit\n  num_c_test[2] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:102: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb_Control_unit\n  num_a_test[3] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:103: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb_Control_unit\n  num_x_test[3] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:105: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb_Control_unit\n  num_a_test[4] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:106: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb_Control_unit\n  num_x_test[4] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:108: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb_Control_unit\n  num_a_test[5] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:109: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb_Control_unit\n  num_x_test[5] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:111: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb_Control_unit\n  num_a_test[6] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:112: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb_Control_unit\n  num_x_test[6] <= $random;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:137: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n                                                                                            : ... In instance tb_Control_unit\n    num_a_in = num_a_test[tri_test_inputs];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:138: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n                                                                                            : ... In instance tb_Control_unit\n    num_a = num_a_test[tri_test_inputs];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:140: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n                                                                                            : ... In instance tb_Control_unit\n    num_x_in = num_x_test[tri_test_inputs]; \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:141: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n                                                                                            : ... In instance tb_Control_unit\n    num_x = num_x_test[tri_test_inputs];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:160: Operator LT expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'tri_test_inputs\' generates 2 bits.\n                                                                                            : ... In instance tb_Control_unit\n   for (tri_test_inputs = 0; tri_test_inputs < 4; tri_test_inputs = tri_test_inputs + 1\'b1 ) begin\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:165: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n                                                                                            : ... In instance tb_Control_unit\n    num_a_in = num_a_test[tri_test_inputs];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:166: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n                                                                                            : ... In instance tb_Control_unit\n    num_a = num_a_test[tri_test_inputs];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:168: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n                                                                                            : ... In instance tb_Control_unit\n    num_x_in = num_x_test[tri_test_inputs];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_mac/tb_Control_unit.v:169: Bit extraction of array[6:0] requires 3 bit index, not 2 bits.\n                                                                                            : ... In instance tb_Control_unit\n    num_x = num_x_test[tri_test_inputs];\n                      ^\n%Error: Exiting due to 1 error(s), 31 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_Control_unit;
reg clk;
reg reset;

reg signed [7:0] num_a_in, num_b_in, num_c_in, num_x_in;
reg signed [7:0] num_a, num_x, num_b, num_c;
reg valid_input, last_input;

wire valid_output;

wire signed [24:0] final_output;

reg mode;
reg signed [24:0] check_tri, check_sump;
reg signed [24:0] y_reg;

reg signed [7:0] num_a_test [6:0];
reg signed [7:0] num_x_test [6:0];
reg signed [7:0] num_b_test [2:0];
reg signed [7:0] num_c_test [2:0];

reg [1:0] tri_test_inputs;

reg test_mode;

parameter TEST_TRI = 1'b0;
parameter TEST_SUMP = 1'b1;

MAC_top_level MAC_top_level_0(
	.clk(clk) ,
	.reset(reset) ,
	.valid_input(valid_input) ,
	.valid_output(valid_output) ,
	.last_input(last_input) ,
	.num_a(num_a_in) ,
	.num_b(num_b_in) ,
	.num_c(num_c_in) ,
	.num_x(num_x_in) ,
	.final_output(final_output) ,
	.mode(mode)
);

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		check_tri <= 'b0;
	end else begin


		check_tri <= (((num_a*num_x) + num_b)*num_x) + num_c;
	end
end

always @(posedge clk or posedge reset) begin
	if ((check_tri == final_output) && (mode)) begin
		$display ("Success\n");
		$display("\tin_1 (a),\tin_2 (x),\tin_add (b),\tin_add (c),\tmac_output, \tideal_out");
		$display("\t%d,\t%d,\t%d,\t%d,\t%d,\t%d", num_a_in, num_x_in, num_b_in, num_c_in, final_output, check_tri);
	end
end


always @(posedge clk or posedge reset) begin
	if (reset) begin
		check_sump <= 'b0;
		y_reg <= 'b0;
	end else begin
		#10;
		check_sump <= (num_a*num_x) + y_reg;
		y_reg <= check_sump;
		#10;
	end
end


always @(posedge clk or posedge reset) begin
	if ((check_sump == final_output) && (!mode)) begin
		$display ("Success\n");
		$display("\tin_1 (a),\tin_2 (x),\ty (y),\tmac_output, \tideal_out");
		$display("\t%d,\t%d,\t%d,\t%d", num_a_in, num_x_in,final_output, check_sump);
	end
end

always @(posedge clk or posedge reset) begin
	if (reset) begin
		num_a_test[0] <= -8'd5;
		num_x_test[0] <= -8'd3;
		num_b_test[0] <= -8'd2;
		num_c_test[0] <= -8'd1;

		num_a_test[1] <= 'd127;
		num_x_test[1] <= -'d127;
		num_b_test[1] <= 'd1;
		num_c_test[1] <= 'd50;

		num_a_test[2] <= $random;
		num_x_test[2] <= $random;
		num_b_test[2] <= $random;
		num_c_test[2] <= $random;

		num_a_test[3] <= $random;
		num_x_test[3] <= $random;

		num_a_test[4] <= $random;
		num_x_test[4] <= $random;

		num_a_test[5] <= $random;
		num_x_test[5] <= $random;

		num_a_test[6] <= $random;
		num_x_test[6] <= $random;
		
	end
end

initial begin
	clk = 1;
	reset = 1;				
	valid_input = 1'b0;
	last_input = 1'b0;

	test_mode = TEST_SUMP;
	#10;
	reset = 0;

	case (test_mode)
		TEST_TRI:
		begin
			for (tri_test_inputs = 0; tri_test_inputs < 3; tri_test_inputs = tri_test_inputs + 1'b1) begin



				mode = 'd1;
				valid_input = 1'b1;

				num_a_in = num_a_test[tri_test_inputs];
				num_a = num_a_test[tri_test_inputs];

				num_x_in = num_x_test[tri_test_inputs]; 
				num_x = num_x_test[tri_test_inputs];

				num_b_in = num_b_test[tri_test_inputs];
				num_b = num_b_test[tri_test_inputs]; 

				num_c = num_c_test[tri_test_inputs]; 

				num_c_in = num_c_test[tri_test_inputs];
				last_input = 1'b1;


				#40;
				last_input = 1'b0;
				valid_input = 1'b0;
				#20;
			end
		end 
		TEST_SUMP:
		begin
			for (tri_test_inputs = 0; tri_test_inputs < 4; tri_test_inputs = tri_test_inputs + 1'b1 ) begin
				mode = 1'b0;
				
				valid_input = 1'b1;

				num_a_in = num_a_test[tri_test_inputs];
				num_a = num_a_test[tri_test_inputs];

				num_x_in = num_x_test[tri_test_inputs];
				num_x = num_x_test[tri_test_inputs];

				last_input = 1'b1;
				#20;
				valid_input = 1'b0;
				last_input = 1'b0;
				#10;
			end
		end
		default: 
		begin
		
		end
	endcase


	$finish;
end

localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;

endmodule
module tb_Control_unit;

reg clk;
reg reset;

reg signed [7:0] num_a_in, num_b_in, num_c_in, num_x_in;
reg signed [7:0] num_a, num_x, num_b, num_c;
reg valid_input, last_input;

wire valid_output;

wire signed [24:0] final_output;

reg mode;
reg signed [24:0] check_tri, check_sump;
reg signed [24:0] y_reg;

reg signed [7:0] num_a_test [6:0];
reg signed [7:0] num_x_test [6:0];
reg signed [7:0] num_b_test [2:0];
reg signed [7:0] num_c_test [2:0];

reg [1:0] tri_test_inputs;

reg test_mode;

parameter TEST_TRI = 1'b0;
parameter TEST_SUMP = 1'b1;

MAC_top_level MAC_top_level_0(
	.clk(clk) ,
	.reset(reset) ,
	.valid_input(valid_input) ,
	.valid_output(valid_output) ,
	.last_input(last_input) ,
	.num_a(num_a_in) ,
	.num_b(num_b_in) ,
	.num_c(num_c_in) ,
	.num_x(num_x_in) ,
	.final_output(final_output) ,
	.mode(mode)
);

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		check_tri <= 'b0;
	end else begin


		check_tri <= (((num_a*num_x) + num_b)*num_x) + num_c;
	end
end

always @(posedge clk or posedge reset) begin
	if ((check_tri == final_output) && (mode)) begin
		$display ("Success\n");
		$display("\tin_1 (a),\tin_2 (x),\tin_add (b),\tin_add (c),\tmac_output, \tideal_out");
		$display("\t%d,\t%d,\t%d,\t%d,\t%d,\t%d", num_a_in, num_x_in, num_b_in, num_c_in, final_output, check_tri);
	end
end


always @(posedge clk or posedge reset) begin
	if (reset) begin
		check_sump <= 'b0;
		y_reg <= 'b0;
	end else begin
		#10;
		check_sump <= (num_a*num_x) + y_reg;
		y_reg <= check_sump;
		#10;
	end
end


always @(posedge clk or posedge reset) begin
	if ((check_sump == final_output) && (!mode)) begin
		$display ("Success\n");
		$display("\tin_1 (a),\tin_2 (x),\ty (y),\tmac_output, \tideal_out");
		$display("\t%d,\t%d,\t%d,\t%d", num_a_in, num_x_in,final_output, check_sump);
	end
end

always @(posedge clk or posedge reset) begin
	if (reset) begin
		num_a_test[0] <= -8'd5;
		num_x_test[0] <= -8'd3;
		num_b_test[0] <= -8'd2;
		num_c_test[0] <= -8'd1;

		num_a_test[1] <= 'd127;
		num_x_test[1] <= -'d127;
		num_b_test[1] <= 'd1;
		num_c_test[1] <= 'd50;

		num_a_test[2] <= $random;
		num_x_test[2] <= $random;
		num_b_test[2] <= $random;
		num_c_test[2] <= $random;

		num_a_test[3] <= $random;
		num_x_test[3] <= $random;

		num_a_test[4] <= $random;
		num_x_test[4] <= $random;

		num_a_test[5] <= $random;
		num_x_test[5] <= $random;

		num_a_test[6] <= $random;
		num_x_test[6] <= $random;
		
	end
end

initial begin
	clk = 1;
	reset = 1;				
	valid_input = 1'b0;
	last_input = 1'b0;

	test_mode = TEST_SUMP;
	#10;
	reset = 0;

	case (test_mode)
		TEST_TRI:
		begin
			for (tri_test_inputs = 0; tri_test_inputs < 3; tri_test_inputs = tri_test_inputs + 1'b1) begin



				mode = 'd1;
				valid_input = 1'b1;

				num_a_in = num_a_test[tri_test_inputs];
				num_a = num_a_test[tri_test_inputs];

				num_x_in = num_x_test[tri_test_inputs]; 
				num_x = num_x_test[tri_test_inputs];

				num_b_in = num_b_test[tri_test_inputs];
				num_b = num_b_test[tri_test_inputs]; 

				num_c = num_c_test[tri_test_inputs]; 

				num_c_in = num_c_test[tri_test_inputs];
				last_input = 1'b1;


				#40;
				last_input = 1'b0;
				valid_input = 1'b0;
				#20;
			end
		end 
		TEST_SUMP:
		begin
			for (tri_test_inputs = 0; tri_test_inputs < 4; tri_test_inputs = tri_test_inputs + 1'b1 ) begin
				mode = 1'b0;
				
				valid_input = 1'b1;

				num_a_in = num_a_test[tri_test_inputs];
				num_a = num_a_test[tri_test_inputs];

				num_x_in = num_x_test[tri_test_inputs];
				num_x = num_x_test[tri_test_inputs];

				last_input = 1'b1;
				#20;
				valid_input = 1'b0;
				last_input = 1'b0;
				#10;
			end
		end
		default: 
		begin
		
		end
	endcase


	$finish;
end

localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;

endmodule