data/full_repos/permissive/196257568/neural_net_verilog/sigmoid.v
 line:33: before: "/"
1: b"%Error: data/full_repos/permissive/196257568/neural_net_verilog/sigmoid.v:9: Cannot find file containing module: 'mult'\n mult m1 (x, $signed(32'b00000000_0000_0100_0000_0000_0000_0000), w1);    \n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/196257568/neural_net_verilog,data/full_repos/permissive/196257568/mult\n             data/full_repos/permissive/196257568/neural_net_verilog,data/full_repos/permissive/196257568/mult.v\n             data/full_repos/permissive/196257568/neural_net_verilog,data/full_repos/permissive/196257568/mult.sv\n             mult\n             mult.v\n             mult.sv\n             obj_dir/mult\n             obj_dir/mult.v\n             obj_dir/mult.sv\n%Error: data/full_repos/permissive/196257568/neural_net_verilog/sigmoid.v:10: Cannot find file containing module: 'mult'\n mult m2 (x, $signed(32'b00000000_0100_0000_0000_0000_0000_0000), w2);    \n ^~~~\n%Error: Exiting due to 2 error(s)\n"
module sigmoid(x, y);



	input  signed [31:0] x;
	output reg signed [31:0] y;
	
	wire signed [31:0] w1, w2;
	mult m1 (x, $signed(32'b00000000_0000_0100_0000_0000_0000_0000), w1);
	mult m2 (x, $signed(32'b00000000_0100_0000_0000_0000_0000_0000), w2);

	
	always @*
	begin
		if (x < $signed(32'b11111000_0000_0000_0000_0000_0000_0000))
			y <= $signed(32'b0);
			
		else if (x < $signed(32'b11111110_0110_0110_0110_0110_0110_0111))
			y <= $signed(32'b00000000_0010_0000_0000_0000_0000_0000) + w1;
		
		else if (x < $signed(32'b00000001_1001_1001_1001_1001_1001_1001))
			y <= $signed(32'b00000000_1000_0000_0000_0000_0000_0000) + w2;
		
		else if (x < $signed(32'b00001000_0000_0000_0000_0000_0000_0000))
			y <= $signed(32'b00000000_1110_0000_0000_0000_0000_0000) + w1;
		
		else
			y <= $signed(32'b00000001_0000_0000_0000_0000_0000_0000);
	end

endmodule
module sigmoid(x, y);




	input  signed [31:0] x;
	output reg signed [31:0] y;
	
	wire signed [31:0] w1, w2;
	mult m1 (x, $signed(32'b00000000_0000_0100_0000_0000_0000_0000), w1);
	mult m2 (x, $signed(32'b00000000_0100_0000_0000_0000_0000_0000), w2);

	
	always @*
	begin
		if (x < $signed(32'b11111000_0000_0000_0000_0000_0000_0000))
			y <= $signed(32'b0);
			
		else if (x < $signed(32'b11111110_0110_0110_0110_0110_0110_0111))
			y <= $signed(32'b00000000_0010_0000_0000_0000_0000_0000) + w1;
		
		else if (x < $signed(32'b00000001_1001_1001_1001_1001_1001_1001))
			y <= $signed(32'b00000000_1000_0000_0000_0000_0000_0000) + w2;
		
		else if (x < $signed(32'b00001000_0000_0000_0000_0000_0000_0000))
			y <= $signed(32'b00000000_1110_0000_0000_0000_0000_0000) + w1;
		
		else
			y <= $signed(32'b00000001_0000_0000_0000_0000_0000_0000);
	end

endmodule