data/full_repos/permissive/11584509/experimental/CM1/uart_tx.v
1: b"%Error: data/full_repos/permissive/11584509/experimental/CM1/uart_tx.v:42: Cannot find file containing module: 'uart_baudgenerator'\n uart_baudgenerator #(\n ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/uart_baudgenerator\n             data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/uart_baudgenerator.v\n             data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/uart_baudgenerator.sv\n             uart_baudgenerator\n             uart_baudgenerator.v\n             uart_baudgenerator.sv\n             obj_dir/uart_baudgenerator\n             obj_dir/uart_baudgenerator.v\n             obj_dir/uart_baudgenerator.sv\n%Error: Exiting due to 1 error(s)\n"
module uart_tx(
		clk,
		tx,
		tx_byte,
		start,
		busy
	);



	parameter CLOCK = 25000000;
	parameter BAUD = 9600;



	input clk;
	wire baudtick;
	output reg tx;
	input [7:0] tx_byte;
	input start;
	output busy;
	


	reg [3:0] state = 0;
	reg [7:0] byte_buf;
	reg muxflag;
	wire ready;
		


	


	uart_baudgenerator #(
		.CLOCK(CLOCK),
		.BAUD(BAUD),
		.ROUNDBITS(5)
	) BAUDGEN (
		.clk(clk),
		.baudtick(baudtick)
	);



	assign ready = (state==0);
	assign busy = ~ready;
	


	

	always @(posedge clk)
		if(ready & start)
			byte_buf <= tx_byte;
	

	always @(posedge clk)
		case(state)
			4'b0000: if(start) state <= 4'b0001;
			4'b0001: if(baudtick) state <= 4'b0100;
			4'b0100: if(baudtick) state <= 4'b1000;
			4'b1000: if(baudtick) state <= 4'b1001;
			4'b1001: if(baudtick) state <= 4'b1010;
			4'b1010: if(baudtick) state <= 4'b1011;
			4'b1011: if(baudtick) state <= 4'b1100;
			4'b1100: if(baudtick) state <= 4'b1101;
			4'b1101: if(baudtick) state <= 4'b1110;
			4'b1110: if(baudtick) state <= 4'b1111;
			4'b1111: if(baudtick) state <= 4'b0010;
			4'b0010: if(baudtick) state <= 4'b0011;
			4'b0011: if(baudtick) state <= 4'b0000;
			default: if(baudtick) state <= 4'b0000;		
		endcase


	always @(*)
		case(state[2:0])
			3'd0: muxflag <= byte_buf[0];
			3'd1: muxflag <= byte_buf[1];
			3'd2: muxflag <= byte_buf[2];
			3'd3: muxflag <= byte_buf[3];
			3'd4: muxflag <= byte_buf[4];
			3'd5: muxflag <= byte_buf[5];
			3'd6: muxflag <= byte_buf[6];
			3'd7: muxflag <= byte_buf[7];
		endcase


	always @(posedge clk)
		tx <= (state<4) | (state[3] & muxflag);

endmodule
module uart_tx(
		clk,
		tx,
		tx_byte,
		start,
		busy
	);




	parameter CLOCK = 25000000;
	parameter BAUD = 9600;



	input clk;
	wire baudtick;
	output reg tx;
	input [7:0] tx_byte;
	input start;
	output busy;
	


	reg [3:0] state = 0;
	reg [7:0] byte_buf;
	reg muxflag;
	wire ready;
		


	


	uart_baudgenerator #(
		.CLOCK(CLOCK),
		.BAUD(BAUD),
		.ROUNDBITS(5)
	) BAUDGEN (
		.clk(clk),
		.baudtick(baudtick)
	);



	assign ready = (state==0);
	assign busy = ~ready;
	


	

	always @(posedge clk)
		if(ready & start)
			byte_buf <= tx_byte;
	

	always @(posedge clk)
		case(state)
			4'b0000: if(start) state <= 4'b0001;
			4'b0001: if(baudtick) state <= 4'b0100;
			4'b0100: if(baudtick) state <= 4'b1000;
			4'b1000: if(baudtick) state <= 4'b1001;
			4'b1001: if(baudtick) state <= 4'b1010;
			4'b1010: if(baudtick) state <= 4'b1011;
			4'b1011: if(baudtick) state <= 4'b1100;
			4'b1100: if(baudtick) state <= 4'b1101;
			4'b1101: if(baudtick) state <= 4'b1110;
			4'b1110: if(baudtick) state <= 4'b1111;
			4'b1111: if(baudtick) state <= 4'b0010;
			4'b0010: if(baudtick) state <= 4'b0011;
			4'b0011: if(baudtick) state <= 4'b0000;
			default: if(baudtick) state <= 4'b0000;		
		endcase


	always @(*)
		case(state[2:0])
			3'd0: muxflag <= byte_buf[0];
			3'd1: muxflag <= byte_buf[1];
			3'd2: muxflag <= byte_buf[2];
			3'd3: muxflag <= byte_buf[3];
			3'd4: muxflag <= byte_buf[4];
			3'd5: muxflag <= byte_buf[5];
			3'd6: muxflag <= byte_buf[6];
			3'd7: muxflag <= byte_buf[7];
		endcase


	always @(posedge clk)
		tx <= (state<4) | (state[3] & muxflag);

endmodule