data/full_repos/permissive/131921633/tv/Data/Memory/bam.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.v:1: Cannot find include file: Altera/Mf.v\n`include "Altera/Mf.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Data/Memory,data/full_repos/permissive/131921633/Altera/Mf.v\n             data/full_repos/permissive/131921633/tv/Data/Memory,data/full_repos/permissive/131921633/Altera/Mf.v.v\n             data/full_repos/permissive/131921633/tv/Data/Memory,data/full_repos/permissive/131921633/Altera/Mf.v.sv\n             Altera/Mf.v\n             Altera/Mf.v.v\n             Altera/Mf.v.sv\n             obj_dir/Altera/Mf.v\n             obj_dir/Altera/Mf.v.v\n             obj_dir/Altera/Mf.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.v:2: Cannot find include file: Util/Math.v\n`include "Util/Math.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.v:3: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.v:19: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T(input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.v:19: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Control_Control_T(input) ctrl\n                           ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.v:27: Define or directive not defined: \'`Util_Math_log2_expr\'\n`Util_Math_log2_expr\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.v:54: syntax error, unexpected assign\nassign {addr_a, offset} = addr;\n^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.v:57: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways @(posedge `Data_Control_Control_Clock(ctrl)) offset$ = offset;\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.v:69: Define or directive not defined: \'`Data_Control_Control_Clock\'\n ( .clock0         (`Data_Control_Control_Clock(ctrl))\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module Data_Memory_bam #
	( parameter DATA_W = 32
	, parameter BYTE_W = 8
	, parameter BYTE_L = (DATA_W - 1) / BYTE_W + 1
	, parameter OFFSET_W = Util_Math_log2(BYTE_L)
	, parameter ADDR_WORD_L = 64
	, parameter ADDR_WORD_W = Util_Math_log2(ADDR_WORD_L)
	, parameter ADDR_BYTE_L = ADDR_WORD_L * BYTE_L
	, parameter ADDR_BYTE_W = Util_Math_log2(ADDR_BYTE_L)
	)
	( `Data_Control_Control_T(input) ctrl
	, input  [ADDR_BYTE_W-1:0] addr
	, input  [DATA_W-1:0] data
	, input  [BYTE_L-1:0] bytes
	, output [DATA_W-1:0] out
	, input wren
	);

`Util_Math_log2_expr

wire [ADDR_WORD_W-1:0] addr_a;
wire [ADDR_WORD_W-1:0] addr_b;
wire [OFFSET_W-1:0] offset;
reg [OFFSET_W-1:0] offset$;
wire [DATA_W-1:0] data_a;
wire [DATA_W-1:0] data_b;
wire [DATA_W-1:0] out_a;
wire [DATA_W-1:0] out_b;
wire [2*DATA_W-1:0] data_bytes [BYTE_L-1:0];
wire [2*DATA_W-1:0] out_bytes [BYTE_L-1:0];
wire [BYTE_L-1:0] byteen_a;
wire [BYTE_L-1:0] byteen_b;

`ifndef ALTERA_RESERVED_QIS

`endif





`ifndef ALTERA_RESERVED_QIS

`endif

assign {addr_a, offset} = addr;
assign addr_b = addr_a + ADDR_WORD_W'(1);
assign {byteen_b, byteen_a} = {BYTE_L'(0), bytes} << offset;
always @(posedge `Data_Control_Control_Clock(ctrl)) offset$ = offset;

genvar i;
generate for(i = 0; i < BYTE_L; i = i + 1) begin : gv
	assign data_bytes[i] = {DATA_W'(0), data} << (BYTE_W * i);
	assign out_bytes[i] = ({out_b, out_a} >> (BYTE_W * i));
end endgenerate

assign out = out_bytes[offset$][DATA_W-1:0];
assign {data_b, data_a} = data_bytes[offset];

altsyncram altsyncram_component
	( .clock0         (`Data_Control_Control_Clock(ctrl))
	, .address_a      (addr_a)
	, .address_b      (addr_b)
	, .byteena_a      (byteen_a)
	, .byteena_b      (byteen_b)
	, .data_a         (data_a)
	, .data_b         (data_b)
	, .wren_a         (wren)
	, .wren_b         (wren)
	, .q_a            (out_a)
	, .q_b            (out_b)
	, .aclr0          (1'b0)
	, .aclr1          (1'b0)
	, .addressstall_a (1'b0)
	, .addressstall_b (1'b0)
	, .clock1         (1'b1)
	, .clocken0       (1'b1)
	, .clocken1       (1'b1)
	, .clocken2       (1'b1)
	, .clocken3       (1'b1)
	, .eccstatus      ()
	, .rden_a         (1'b1)
	, .rden_b         (1'b1)
	);
defparam
	altsyncram_component.address_reg_b                      = "CLOCK0",
	altsyncram_component.byteena_reg_b                      = "CLOCK0",
	altsyncram_component.byte_size                          = BYTE_W,
	altsyncram_component.clock_enable_input_a               = "BYPASS",
	altsyncram_component.clock_enable_input_b               = "BYPASS",
	altsyncram_component.clock_enable_output_a              = "BYPASS",
	altsyncram_component.clock_enable_output_b              = "BYPASS",
	altsyncram_component.indata_reg_b                       = "CLOCK0",
	altsyncram_component.intended_device_family             = "MAX 10",
	altsyncram_component.lpm_type                           = "altsyncram",
	altsyncram_component.numwords_a                         = ADDR_WORD_L,
	altsyncram_component.numwords_b                         = ADDR_WORD_L,
	altsyncram_component.operation_mode                     = "BIDIR_DUAL_PORT",
	altsyncram_component.outdata_aclr_a                     = "NONE",
	altsyncram_component.outdata_aclr_b                     = "NONE",
	altsyncram_component.outdata_reg_a                      = "UNREGISTERED",
	altsyncram_component.outdata_reg_b                      = "UNREGISTERED",
	altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
	altsyncram_component.read_during_write_mode_port_a      = "NEW_DATA_WITH_NBE_READ",
	altsyncram_component.read_during_write_mode_port_b      = "NEW_DATA_WITH_NBE_READ",
	altsyncram_component.widthad_a                          = ADDR_WORD_W,
	altsyncram_component.widthad_b                          = ADDR_WORD_W,
	altsyncram_component.width_a                            = DATA_W,
	altsyncram_component.width_b                            = DATA_W,
	altsyncram_component.width_byteena_a                    = BYTE_L,
	altsyncram_component.width_byteena_b                    = BYTE_L,
	altsyncram_component.power_up_uninitialized             = "FALSE",
	altsyncram_component.wrcontrol_wraddress_reg_b          = "CLOCK0";

endmodule
module Data_Memory_bam #
	( parameter DATA_W = 32
	, parameter BYTE_W = 8
	, parameter BYTE_L = (DATA_W - 1) / BYTE_W + 1
	, parameter OFFSET_W = Util_Math_log2(BYTE_L)
	, parameter ADDR_WORD_L = 64
	, parameter ADDR_WORD_W = Util_Math_log2(ADDR_WORD_L)
	, parameter ADDR_BYTE_L = ADDR_WORD_L * BYTE_L
	, parameter ADDR_BYTE_W = Util_Math_log2(ADDR_BYTE_L)
	)
	( `Data_Control_Control_T(input) ctrl
	, input  [ADDR_BYTE_W-1:0] addr
	, input  [DATA_W-1:0] data
	, input  [BYTE_L-1:0] bytes
	, output [DATA_W-1:0] out
	, input wren
	);


`Util_Math_log2_expr

wire [ADDR_WORD_W-1:0] addr_a;
wire [ADDR_WORD_W-1:0] addr_b;
wire [OFFSET_W-1:0] offset;
reg [OFFSET_W-1:0] offset$;
wire [DATA_W-1:0] data_a;
wire [DATA_W-1:0] data_b;
wire [DATA_W-1:0] out_a;
wire [DATA_W-1:0] out_b;
wire [2*DATA_W-1:0] data_bytes [BYTE_L-1:0];
wire [2*DATA_W-1:0] out_bytes [BYTE_L-1:0];
wire [BYTE_L-1:0] byteen_a;
wire [BYTE_L-1:0] byteen_b;

`ifndef ALTERA_RESERVED_QIS

`endif





`ifndef ALTERA_RESERVED_QIS

`endif

assign {addr_a, offset} = addr;
assign addr_b = addr_a + ADDR_WORD_W'(1);
assign {byteen_b, byteen_a} = {BYTE_L'(0), bytes} << offset;
always @(posedge `Data_Control_Control_Clock(ctrl)) offset$ = offset;

genvar i;
generate for(i = 0; i < BYTE_L; i = i + 1) begin : gv
	assign data_bytes[i] = {DATA_W'(0), data} << (BYTE_W * i);
	assign out_bytes[i] = ({out_b, out_a} >> (BYTE_W * i));
end endgenerate

assign out = out_bytes[offset$][DATA_W-1:0];
assign {data_b, data_a} = data_bytes[offset];

altsyncram altsyncram_component
	( .clock0         (`Data_Control_Control_Clock(ctrl))
	, .address_a      (addr_a)
	, .address_b      (addr_b)
	, .byteena_a      (byteen_a)
	, .byteena_b      (byteen_b)
	, .data_a         (data_a)
	, .data_b         (data_b)
	, .wren_a         (wren)
	, .wren_b         (wren)
	, .q_a            (out_a)
	, .q_b            (out_b)
	, .aclr0          (1'b0)
	, .aclr1          (1'b0)
	, .addressstall_a (1'b0)
	, .addressstall_b (1'b0)
	, .clock1         (1'b1)
	, .clocken0       (1'b1)
	, .clocken1       (1'b1)
	, .clocken2       (1'b1)
	, .clocken3       (1'b1)
	, .eccstatus      ()
	, .rden_a         (1'b1)
	, .rden_b         (1'b1)
	);
defparam
	altsyncram_component.address_reg_b                      = "CLOCK0",
	altsyncram_component.byteena_reg_b                      = "CLOCK0",
	altsyncram_component.byte_size                          = BYTE_W,
	altsyncram_component.clock_enable_input_a               = "BYPASS",
	altsyncram_component.clock_enable_input_b               = "BYPASS",
	altsyncram_component.clock_enable_output_a              = "BYPASS",
	altsyncram_component.clock_enable_output_b              = "BYPASS",
	altsyncram_component.indata_reg_b                       = "CLOCK0",
	altsyncram_component.intended_device_family             = "MAX 10",
	altsyncram_component.lpm_type                           = "altsyncram",
	altsyncram_component.numwords_a                         = ADDR_WORD_L,
	altsyncram_component.numwords_b                         = ADDR_WORD_L,
	altsyncram_component.operation_mode                     = "BIDIR_DUAL_PORT",
	altsyncram_component.outdata_aclr_a                     = "NONE",
	altsyncram_component.outdata_aclr_b                     = "NONE",
	altsyncram_component.outdata_reg_a                      = "UNREGISTERED",
	altsyncram_component.outdata_reg_b                      = "UNREGISTERED",
	altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
	altsyncram_component.read_during_write_mode_port_a      = "NEW_DATA_WITH_NBE_READ",
	altsyncram_component.read_during_write_mode_port_b      = "NEW_DATA_WITH_NBE_READ",
	altsyncram_component.widthad_a                          = ADDR_WORD_W,
	altsyncram_component.widthad_b                          = ADDR_WORD_W,
	altsyncram_component.width_a                            = DATA_W,
	altsyncram_component.width_b                            = DATA_W,
	altsyncram_component.width_byteena_a                    = BYTE_L,
	altsyncram_component.width_byteena_b                    = BYTE_L,
	altsyncram_component.power_up_uninitialized             = "FALSE",
	altsyncram_component.wrcontrol_wraddress_reg_b          = "CLOCK0";

endmodule