data/full_repos/permissive/143278/ivltests/ptest008.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ptest008.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ptest008.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/ptest008.v:24: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                                        : ... In instance main\n  assign b = !a;\n             ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
  reg [3:0] a;
  wire b;

  assign b = !a;

  initial begin
    a = 4'd1;
    #1;
    if (b!==0) begin
      $display("FAILED");
      $finish;
    end
    a = 4'd0;
    #1;
    if (b!==1) begin
      $display("FAILED");
      $finish;
    end
    $display("PASSED");
  end
endmodule
module main;

  reg [3:0] a;
  wire b;

  assign b = !a;

  initial begin
    a = 4'd1;
    #1;
    if (b!==0) begin
      $display("FAILED");
      $finish;
    end
    a = 4'd0;
    #1;
    if (b!==1) begin
      $display("FAILED");
      $finish;
    end
    $display("PASSED");
  end
endmodule