data/full_repos/permissive/149079484/RISC-V_Cache-lab/RISCV_CLKRST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/149079484/RISC-V_Cache-lab/RISCV_CLKRST.v:13: Unsupported: Ignoring delay on this delayed statement.\n      #5 clock_q <= 1\'b1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/149079484/RISC-V_Cache-lab/RISCV_CLKRST.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #101 reset_n_q <= 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/149079484/RISC-V_Cache-lab/RISCV_CLKRST.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #5 clock_q <= ~clock_q;\n      ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RISCV_CLKRST (
  output wire CLK,
  output wire RSTn
 );

  reg clock_q = 1'b0;
  reg reset_n_q = 1'b0;

  initial
    begin
      #5 clock_q <= 1'b1;
      #101 reset_n_q <= 1'b1;
    end

  always @(clock_q)
      #5 clock_q <= ~clock_q;

  assign CLK = clock_q;
  assign RSTn = reset_n_q;

endmodule
module RISCV_CLKRST (
  output wire CLK,
  output wire RSTn
 );


  reg clock_q = 1'b0;
  reg reset_n_q = 1'b0;

  initial
    begin
      #5 clock_q <= 1'b1;
      #101 reset_n_q <= 1'b1;
    end

  always @(clock_q)
      #5 clock_q <= ~clock_q;

  assign CLK = clock_q;
  assign RSTn = reset_n_q;

endmodule