data/full_repos/permissive/135820056/rtl/jt12/mixer/jt12_fm_uprate.v
 line:95: before: "/"
1: b"%Error: data/full_repos/permissive/135820056/rtl/jt12/mixer/jt12_fm_uprate.v:52: Cannot find file containing module: 'jt12_interpol'\njt12_interpol #(.calcw(17),.inw(16),.rate(4),.m(1),.n(1)) \n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135820056/rtl/jt12/mixer,data/full_repos/permissive/135820056/jt12_interpol\n             data/full_repos/permissive/135820056/rtl/jt12/mixer,data/full_repos/permissive/135820056/jt12_interpol.v\n             data/full_repos/permissive/135820056/rtl/jt12/mixer,data/full_repos/permissive/135820056/jt12_interpol.sv\n             jt12_interpol\n             jt12_interpol.v\n             jt12_interpol.sv\n             obj_dir/jt12_interpol\n             obj_dir/jt12_interpol.v\n             obj_dir/jt12_interpol.sv\n%Error: data/full_repos/permissive/135820056/rtl/jt12/mixer/jt12_fm_uprate.v:63: Cannot find file containing module: 'jt12_interpol'\njt12_interpol #(.calcw(19),.inw(16),.rate(4),.m(1),.n(3)) \n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135820056/rtl/jt12/mixer/jt12_fm_uprate.v:74: Cannot find file containing module: 'jt12_interpol'\njt12_interpol #(.calcw(21),.inw(16),.rate(7),.m(2),.n(2)) \n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135820056/rtl/jt12/mixer/jt12_fm_uprate.v:85: Cannot find file containing module: 'jt12_interpol'\njt12_interpol #(.calcw(21),.inw(16),.rate(9),.m(2),.n(2)) \n^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module jt12_fm_uprate(
    input               rst,
    input               clk,
    input signed [15:0] fm_snd,
    input signed [11:0] psg_snd,
    input fm_en,
    input cen_1008,
    input cen_252,
    input cen_63,
    input cen_9,
    output signed [15:0] snd
);

wire signed [15:0] fm2,fm3,fm4;

reg [15:0] mixed;
always @(posedge clk)
    mixed <= (fm_en?fm_snd:16'd0) + {{1{psg_snd[11]}},psg_snd,3'b0};


jt12_interpol #(.calcw(17),.inw(16),.rate(4),.m(1),.n(1)) 
u_fm2(
    .clk    ( clk      ),
    .rst    ( rst      ),
    .cen_in ( cen_1008 ),
    .cen_out( cen_252  ),
    .snd_in ( mixed    ),
    .snd_out( fm2      )
);


jt12_interpol #(.calcw(19),.inw(16),.rate(4),.m(1),.n(3)) 
u_fm3(
    .clk    ( clk      ),
    .rst    ( rst      ),    
    .cen_in ( cen_252  ),
    .cen_out( cen_63   ),
    .snd_in ( fm2      ),
    .snd_out( fm3      )
);


jt12_interpol #(.calcw(21),.inw(16),.rate(7),.m(2),.n(2)) 
u_fm4(
    .clk    ( clk      ),
    .rst    ( rst      ),        
    .cen_in ( cen_63   ),
    .cen_out( cen_9    ),
    .snd_in ( fm3      ),
    .snd_out( fm4      )
);


jt12_interpol #(.calcw(21),.inw(16),.rate(9),.m(2),.n(2)) 
u_fm5(
    .clk    ( clk      ),
    .rst    ( rst      ),        
    .cen_in ( cen_9    ),
    .cen_out( 1'b1     ),
    .snd_in ( fm4      ),
    .snd_out( snd      )
);

endmodule
module jt12_fm_uprate(
    input               rst,
    input               clk,
    input signed [15:0] fm_snd,
    input signed [11:0] psg_snd,
    input fm_en,
    input cen_1008,
    input cen_252,
    input cen_63,
    input cen_9,
    output signed [15:0] snd
);


wire signed [15:0] fm2,fm3,fm4;

reg [15:0] mixed;
always @(posedge clk)
    mixed <= (fm_en?fm_snd:16'd0) + {{1{psg_snd[11]}},psg_snd,3'b0};


jt12_interpol #(.calcw(17),.inw(16),.rate(4),.m(1),.n(1)) 
u_fm2(
    .clk    ( clk      ),
    .rst    ( rst      ),
    .cen_in ( cen_1008 ),
    .cen_out( cen_252  ),
    .snd_in ( mixed    ),
    .snd_out( fm2      )
);


jt12_interpol #(.calcw(19),.inw(16),.rate(4),.m(1),.n(3)) 
u_fm3(
    .clk    ( clk      ),
    .rst    ( rst      ),    
    .cen_in ( cen_252  ),
    .cen_out( cen_63   ),
    .snd_in ( fm2      ),
    .snd_out( fm3      )
);


jt12_interpol #(.calcw(21),.inw(16),.rate(7),.m(2),.n(2)) 
u_fm4(
    .clk    ( clk      ),
    .rst    ( rst      ),        
    .cen_in ( cen_63   ),
    .cen_out( cen_9    ),
    .snd_in ( fm3      ),
    .snd_out( fm4      )
);


jt12_interpol #(.calcw(21),.inw(16),.rate(9),.m(2),.n(2)) 
u_fm5(
    .clk    ( clk      ),
    .rst    ( rst      ),        
    .cen_in ( cen_9    ),
    .cen_out( 1'b1     ),
    .snd_in ( fm4      ),
    .snd_out( snd      )
);

endmodule