data/full_repos/permissive/115351337/uart/transmitter_tb.v
 line:52: before: "$"
1: b'%Error: data/full_repos/permissive/115351337/uart/transmitter_tb.v:41: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("transmitter_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/115351337/uart/transmitter_tb.v:42: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,transmitter_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #20 start = 1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #12480 data = 8\'b01010101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #1248 start = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #20 start = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #12480 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/transmitter_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #6 clk = ~clk;\n        ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module transmitter_tb;
    reg clk;
    reg [7:0] data;
    wire in_progress;
    reg start;
    wire tx;

    uart_tx transmitter(clk, data, start, in_progress, tx);

    initial begin
        $dumpfile("transmitter_tb.vcd");
        $dumpvars(0,transmitter_tb);

        clk = 1'b0;
        data = 8'b01010101;
        start = 1'b1;
        #20 start = 1'b0;

        #12480 data = 8'b01010101;
        #1248 start = 1'b1;
        #20 start = 1'b0;
        #12480 $finish;
    end

    always begin
        #6 clk = ~clk;
    end
endmodule
module transmitter_tb;

    reg clk;
    reg [7:0] data;
    wire in_progress;
    reg start;
    wire tx;

    uart_tx transmitter(clk, data, start, in_progress, tx);

    initial begin
        $dumpfile("transmitter_tb.vcd");
        $dumpvars(0,transmitter_tb);

        clk = 1'b0;
        data = 8'b01010101;
        start = 1'b1;
        #20 start = 1'b0;

        #12480 data = 8'b01010101;
        #1248 start = 1'b1;
        #20 start = 1'b0;
        #12480 $finish;
    end

    always begin
        #6 clk = ~clk;
    end
endmodule