data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v
1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:21: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:43: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:66: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:77: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:88: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:99: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:114: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:136: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MULTITOP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:122: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                       : ... Top module \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                                                                                       : ... Top module \'MUXDFF\'\nmodule MUXDFF (\n       ^~~~~~\n%Error: Exiting due to 9 warning(s)\n'
module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    always @(posedge clk) begin
        if (load) begin
            q <= data;
        end
        else begin
            case (amount)
             2'b00: q <= {q[62:0], q[0]};
             2'b01: q <= {q[55:0], {8{q[0]}}};
             2'b10: q <= {q[63], q[63:1]};
             2'b11: q <= {{8{q[63]}}, q[63:8]};
            endcase
        end
    end
endmodule
module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q);
 
    always @(posedge clk) begin
        if (load) begin
            q <= data;
        end
        else begin
            case (amount)
             2'b00: q <= {q[62:0], q[0]};
             2'b01: q <= {q[55:0], {8{q[0]}}};
             2'b10: q <= {q[63], q[63:1]};
             2'b11: q <= {{8{q[63]}}, q[63:8]};
            endcase
        end
    end
endmodule