data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/dualportram.v
data/verilator_xmls/22acf5bf-8a88-4496-9a5d-9f88e385bab1.xml
module dpram(clka,clkb, wea, addra, addrb, dina,douta,doutb);
 parameter DWIDTH=8,AWIDTH=20,WORDS=1048576;

 input clka,clkb,wea;
 input [AWIDTH-1:0] addra,addrb;
 input [DWIDTH-1:0] dina;
 output reg [DWIDTH-1:0] douta,doutb;

 reg [DWIDTH-1:0] mem [WORDS-1:0];

 always @(posedge clka)
   begin
     if(wea) mem[addra] <= dina;
     douta <= mem[addra];
  end

 always @(posedge clkb)
   begin
     doutb <= mem[addrb];
  end


integer i;
integer j;
integer k;
integer adr;
initial begin

		for (i=0; i < 480; i=i+1) begin
		   for (j=0; j < 640; j=j+1)	begin
			for (k=0; k < 3; k=k+1) begin
			adr = (j + (i*640))*3 +k;
			
			if ((i-240) * (i-240) +(j-320) * (j-320) <= 3000)
			 begin
                       if (k == 0)
                        mem[adr] = 8'hff;
                       else
                        mem[adr] = 0;
            end
			else if  ((i-340) * (i-340) +(j-520) * (j-520) <= 1600) begin
			if (k == 0) mem[adr] = 8'h00;
			else mem[adr] = 8'hff;
			end else
			 if (j < 320) begin
			     if (k==1)
			     mem[adr] = 8'hff;
			     else
			     mem[adr] = 0;
			 end
			 else begin
			     if (k==2)
			     mem[adr] = 8'hff;
			     else
			     mem[adr] = 0;
			end
                        
			end
		end
	end
 end

endmodule
module dpram(clka,clkb, wea, addra, addrb, dina,douta,doutb);

 parameter DWIDTH=8,AWIDTH=20,WORDS=1048576;

 input clka,clkb,wea;
 input [AWIDTH-1:0] addra,addrb;
 input [DWIDTH-1:0] dina;
 output reg [DWIDTH-1:0] douta,doutb;

 reg [DWIDTH-1:0] mem [WORDS-1:0];

 always @(posedge clka)
   begin
     if(wea) mem[addra] <= dina;
     douta <= mem[addra];
  end

 always @(posedge clkb)
   begin
     doutb <= mem[addrb];
  end


integer i;
integer j;
integer k;
integer adr;
initial begin

		for (i=0; i < 480; i=i+1) begin
		   for (j=0; j < 640; j=j+1)	begin
			for (k=0; k < 3; k=k+1) begin
			adr = (j + (i*640))*3 +k;
			
			if ((i-240) * (i-240) +(j-320) * (j-320) <= 3000)
			 begin
                       if (k == 0)
                        mem[adr] = 8'hff;
                       else
                        mem[adr] = 0;
            end
			else if  ((i-340) * (i-340) +(j-520) * (j-520) <= 1600) begin
			if (k == 0) mem[adr] = 8'h00;
			else mem[adr] = 8'hff;
			end else
			 if (j < 320) begin
			     if (k==1)
			     mem[adr] = 8'hff;
			     else
			     mem[adr] = 0;
			 end
			 else begin
			     if (k==2)
			     mem[adr] = 8'hff;
			     else
			     mem[adr] = 0;
			end
                        
			end
		end
	end
 end

endmodule