data/full_repos/permissive/179451217/debounce.v
 line:53: before: "case"
data/verilator_xmls/8bfb1d06-e8b3-4027-83d8-9f50b4f97803.xml
module debounce #(
    parameter Bits = 4,
    parameter StableTime = 0,
    parameter StableState = "BOTH"
)(
    input wire clk,
    input wire reset,

    input wire in,
    output reg out
);

wire stable_bit;
reg [Bits-1:0] state, state_D;
reg out_D;

always @(posedge clk) begin
    if(reset) begin
        state <= 0;
        out <= 0;
    end else begin
        state <= state_D;
        out <= out_D;
    end
end

generate

case(StableState)
"LOW": assign stable_bit = 1'b0;
"HIGH": assign stable_bit = 1'b1;
default: assign stable_bit = out;
endcase

if(StableTime == 0) begin

wire [Bits:0] state_in = {state, in};
always @* begin

    state_D = state_in[Bits-1:0];

    if(state_in == ~{Bits+1{stable_bit}})
        out_D = ~stable_bit;
    else
        out_D = stable_bit;
end

end else begin


always @* begin
    out_D = out;
    state_D = state;

    if(state > 0) state_D = state-1;
    
    if(in == stable_bit) begin

        state_D = StableTime - 1;
        out_D = stable_bit;
    end else if(state == 0) begin

        out_D = ~stable_bit;
    end
end

end
endgenerate

endmodule
module debounce #(
    parameter Bits = 4,
    parameter StableTime = 0,
    parameter StableState = "BOTH"
)(
    input wire clk,
    input wire reset,

    input wire in,
    output reg out
);


wire stable_bit;
reg [Bits-1:0] state, state_D;
reg out_D;

always @(posedge clk) begin
    if(reset) begin
        state <= 0;
        out <= 0;
    end else begin
        state <= state_D;
        out <= out_D;
    end
end

generate

case(StableState)
"LOW": assign stable_bit = 1'b0;
"HIGH": assign stable_bit = 1'b1;
default: assign stable_bit = out;
endcase

if(StableTime == 0) begin

wire [Bits:0] state_in = {state, in};
always @* begin

    state_D = state_in[Bits-1:0];

    if(state_in == ~{Bits+1{stable_bit}})
        out_D = ~stable_bit;
    else
        out_D = stable_bit;
end

end else begin


always @* begin
    out_D = out;
    state_D = state;

    if(state > 0) state_D = state-1;
    
    if(in == stable_bit) begin

        state_D = StableTime - 1;
        out_D = stable_bit;
    end else if(state == 0) begin

        out_D = ~stable_bit;
    end
end

end
endgenerate

endmodule