data/full_repos/permissive/161568282/UM/UM_v1/bv_and_2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161568282/UM/UM_v1/bv_and_2.v:30: Operator ASSIGNDLY expects 65 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                           : ... In instance bv_and_2\n          bv_out <= {rule_num{1\'b0}};\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161568282/UM/UM_v1/bv_and_2.v:37: Operator ASSIGNDLY expects 65 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 92 bits.\n                                                                           : ... In instance bv_and_2\n                bv_out <= {28\'b0,bv_1 & bv_2};\n                       ^~\n%Error: Exiting due to 2 warning(s)\n'
module bv_and_2(
clk,
reset,

bv_in_valid,
bv_1,
bv_2,
bv_out_valid,
bv_out

);

parameter rule_num = 64;

input clk;
input reset;
input bv_in_valid;
input [rule_num-1:0]  bv_1;
input [rule_num-1:0]  bv_2;
output  reg         bv_out_valid;
output  reg [rule_num:0]  bv_out;

always @(posedge clk or negedge reset)
begin
    if(!reset)
      begin
          bv_out <= {rule_num{1'b0}};
          bv_out_valid <= 1'b0;
      end
    else
      begin
          if(bv_in_valid == 1'b1)
            begin
                bv_out <= {28'b0,bv_1 & bv_2};

                bv_out_valid <= 1'b1;
            end
          else  bv_out_valid <= 1'b0;
      end
end













endmodule
module bv_and_2(
clk,
reset,

bv_in_valid,
bv_1,
bv_2,
bv_out_valid,
bv_out

);


parameter rule_num = 64;

input clk;
input reset;
input bv_in_valid;
input [rule_num-1:0]  bv_1;
input [rule_num-1:0]  bv_2;
output  reg         bv_out_valid;
output  reg [rule_num:0]  bv_out;

always @(posedge clk or negedge reset)
begin
    if(!reset)
      begin
          bv_out <= {rule_num{1'b0}};
          bv_out_valid <= 1'b0;
      end
    else
      begin
          if(bv_in_valid == 1'b1)
            begin
                bv_out <= {28'b0,bv_1 & bv_2};

                bv_out_valid <= 1'b1;
            end
          else  bv_out_valid <= 1'b0;
      end
end













endmodule