data/full_repos/permissive/201488448/2_circuits/2_sequential/fsm/16_ps2parserdata.v
1: b'%Warning-WIDTH: data/full_repos/permissive/201488448/2_circuits/2_sequential/fsm/16_ps2parserdata.v:38: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                                      : ... In instance top_module\n            data <= 32\'d0;\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/201488448/2_circuits/2_sequential/fsm/16_ps2parserdata.v:46: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data\' generates 24 bits.\n                                                                                                      : ... In instance top_module\n    assign out_bytes = (done)?data:32\'d0;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/201488448/2_circuits/2_sequential/fsm/16_ps2parserdata.v:46: Operator ASSIGNW expects 24 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                      : ... In instance top_module\n    assign out_bytes = (done)?data:32\'d0;\n                     ^\n%Error: Exiting due to 3 warning(s)\n'
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output [23:0] out_bytes,
    output done);

    reg	[23:0]	data;

    parameter b1 = 2'd0, b2 = 2'd1, b3 = 2'd2, dn = 2'd3;
    reg	[1:0]	state, next_state;

    always@(*) begin
        case({state, in[3]})
            {b1, 1'b0}:	next_state = b1;
            {b1, 1'b1}:	next_state = b2;
            {b2, 1'b0}:	next_state = b3;
            {b2, 1'b1}:	next_state = b3;
            {b3, 1'b0}:	next_state = dn;
            {b3, 1'b1}:	next_state = dn;
            {dn, 1'b0}:	next_state = b1;
            {dn, 1'b1}:	next_state = b2;
        endcase
    end

    always@(posedge clk) begin
        if(reset)
            state <= b1;
        else
            state <= next_state;
    end

    assign	done = (state == dn);
    

    always@(posedge clk) begin
        if(reset)
            data <= 32'd0;
        else begin
            data[23:16] <= data[15:8];
            data[15:8] <= data[7:0];
            data[7:0] <= in;
        end
    end
    
    assign out_bytes = (done)?data:32'd0;
    
endmodule
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output [23:0] out_bytes,
    output done);


    reg	[23:0]	data;

    parameter b1 = 2'd0, b2 = 2'd1, b3 = 2'd2, dn = 2'd3;
    reg	[1:0]	state, next_state;

    always@(*) begin
        case({state, in[3]})
            {b1, 1'b0}:	next_state = b1;
            {b1, 1'b1}:	next_state = b2;
            {b2, 1'b0}:	next_state = b3;
            {b2, 1'b1}:	next_state = b3;
            {b3, 1'b0}:	next_state = dn;
            {b3, 1'b1}:	next_state = dn;
            {dn, 1'b0}:	next_state = b1;
            {dn, 1'b1}:	next_state = b2;
        endcase
    end

    always@(posedge clk) begin
        if(reset)
            state <= b1;
        else
            state <= next_state;
    end

    assign	done = (state == dn);
    

    always@(posedge clk) begin
        if(reset)
            data <= 32'd0;
        else begin
            data[23:16] <= data[15:8];
            data[15:8] <= data[7:0];
            data[7:0] <= in;
        end
    end
    
    assign out_bytes = (done)?data:32'd0;
    
endmodule