data/full_repos/permissive/164251444/analog/cdk_oa/MND3X1/netlist/pre_netlist/verilog.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/164251444/analog/cdk_oa/MND3X1/netlist/pre_netlist/verilog.v:19: Cannot find file containing module: 'pfet_b'\npfet_b  P6 ( .b(VNW), .s(VDD), .g(CK), .d(net04));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164251444/analog/cdk_oa/MND3X1/netlist/pre_netlist,data/full_repos/permissive/164251444/pfet_b\n             data/full_repos/permissive/164251444/analog/cdk_oa/MND3X1/netlist/pre_netlist,data/full_repos/permissive/164251444/pfet_b.v\n             data/full_repos/permissive/164251444/analog/cdk_oa/MND3X1/netlist/pre_netlist,data/full_repos/permissive/164251444/pfet_b.sv\n             pfet_b\n             pfet_b.v\n             pfet_b.sv\n             obj_dir/pfet_b\n             obj_dir/pfet_b.v\n             obj_dir/pfet_b.sv\n%Error: data/full_repos/permissive/164251444/analog/cdk_oa/MND3X1/netlist/pre_netlist/verilog.v:20: Cannot find file containing module: 'pfet_b'\npfet_b  P0 ( .b(VNW), .s(VDD), .g(B), .d(A));\n^~~~~~\n%Error: data/full_repos/permissive/164251444/analog/cdk_oa/MND3X1/netlist/pre_netlist/verilog.v:21: Cannot find file containing module: 'pfet_b'\npfet_b  P2 ( .b(VNW), .s(VDD), .g(CK), .d(A));\n^~~~~~\n%Error: data/full_repos/permissive/164251444/analog/cdk_oa/MND3X1/netlist/pre_netlist/verilog.v:22: Cannot find file containing module: 'nfet_b'\nnfet_b  N3 ( .b(VPW), .s(net04), .g(B), .d(A));\n^~~~~~\n%Error: data/full_repos/permissive/164251444/analog/cdk_oa/MND3X1/netlist/pre_netlist/verilog.v:23: Cannot find file containing module: 'nfet_b'\nnfet_b  N1 ( .b(VPW), .s(net17), .g(VIP), .d(net04));\n^~~~~~\n%Error: data/full_repos/permissive/164251444/analog/cdk_oa/MND3X1/netlist/pre_netlist/verilog.v:24: Cannot find file containing module: 'nfet_b'\nnfet_b  N0 ( .b(VPW), .s(VSS), .g(CK), .d(net17));\n^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module MND3X1 ( A, B, VDD, VNW, VPW, VSS, CK, VIP );

inout  A, B, VDD, VNW, VPW, VSS;

input  CK, VIP;


specify 
    specparam CDS_LIBNAME  = "rail12lp";
    specparam CDS_CELLNAME = "MND3X1";
    specparam CDS_VIEWNAME = "schematic";
endspecify

pfet_b  P6 ( .b(VNW), .s(VDD), .g(CK), .d(net04));
pfet_b  P0 ( .b(VNW), .s(VDD), .g(B), .d(A));
pfet_b  P2 ( .b(VNW), .s(VDD), .g(CK), .d(A));
nfet_b  N3 ( .b(VPW), .s(net04), .g(B), .d(A));
nfet_b  N1 ( .b(VPW), .s(net17), .g(VIP), .d(net04));
nfet_b  N0 ( .b(VPW), .s(VSS), .g(CK), .d(net17));

endmodule
module MND3X1 ( A, B, VDD, VNW, VPW, VSS, CK, VIP );


inout  A, B, VDD, VNW, VPW, VSS;

input  CK, VIP;


specify 
    specparam CDS_LIBNAME  = "rail12lp";
    specparam CDS_CELLNAME = "MND3X1";
    specparam CDS_VIEWNAME = "schematic";
endspecify

pfet_b  P6 ( .b(VNW), .s(VDD), .g(CK), .d(net04));
pfet_b  P0 ( .b(VNW), .s(VDD), .g(B), .d(A));
pfet_b  P2 ( .b(VNW), .s(VDD), .g(CK), .d(A));
nfet_b  N3 ( .b(VPW), .s(net04), .g(B), .d(A));
nfet_b  N1 ( .b(VPW), .s(net17), .g(VIP), .d(net04));
nfet_b  N0 ( .b(VPW), .s(VSS), .g(CK), .d(net17));

endmodule