data/full_repos/permissive/119758565/ALU.v
1: b"%Error: data/full_repos/permissive/119758565/ALU.v:32: syntax error, unexpected '(', expecting IDENTIFIER\n  And16(x, ~{16{control[5]}}, Xz);\n        ^\n%Error: data/full_repos/permissive/119758565/ALU.v:38: syntax error, unexpected '(', expecting IDENTIFIER\n  Not16(Xz, Xneg);\n        ^~\n%Error: data/full_repos/permissive/119758565/ALU.v:44: syntax error, unexpected '(', expecting IDENTIFIER\n  Mux16(Xz, Xneg, control[4], Xout);\n        ^~\n%Error: data/full_repos/permissive/119758565/ALU.v:49: syntax error, unexpected '(', expecting IDENTIFIER\n  Add16(Xout, Yout, XplusY);\n        ^~~~\n%Error: data/full_repos/permissive/119758565/ALU.v:53: syntax error, unexpected '(', expecting IDENTIFIER\n  And16(Xout, Yout, XandY);\n        ^~~~\n%Error: data/full_repos/permissive/119758565/ALU.v:57: syntax error, unexpected '(', expecting IDENTIFIER\n  Mux16(XandY, XplusY, control[1], almostOut);\n        ^~~~~\n%Error: data/full_repos/permissive/119758565/ALU.v:61: syntax error, unexpected '(', expecting IDENTIFIER\n  Not16(almostOut, negOut);  \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/119758565/ALU.v:66: syntax error, unexpected '(', expecting IDENTIFIER\n  Or16Way(out, notzr);\n          ^~~\n%Error: Exiting due to 8 error(s)\n"
module ALU(
    input [15:0] x,
    input [15:0] y,
    input [5:0] control,
    output [15:0] out,  
    output zr,
    output ng
    );
	 
	 wire [15:0] Xz;
	 wire [15:0] Yz;
	 And16(x, ~{16{control[5]}}, Xz);
	 And16(y, ~{16{control[3]}}, Yz);
	 
	 wire [0:15] Xneg;
	 wire [0:15] Yneg;
	 
	 Not16(Xz, Xneg);
	 Not16(Yz, Yneg);
	 
	 wire [15:0] Xout;
	 wire [15:0] Yout;
	 
	 Mux16(Xz, Xneg, control[4], Xout);
	 Mux16(Yz, Yneg, control[2], Yout);
	 
	 wire [15:0] XplusY;
	 
	 Add16(Xout, Yout, XplusY);
	 
	 wire [15:0] XandY;
	 
	 And16(Xout, Yout, XandY);
	 
	 wire [15:0] almostOut;
	 
	 Mux16(XandY, XplusY, control[1], almostOut);
	 
	 wire [15:0] negOut;
	 
	 Not16(almostOut, negOut);	 
	 
	 Mux16(almostOut, negOut, control[0], out);
	 
	 assign ng = out[15];
	 Or16Way(out, notzr);
	 notGate(notzr, zr);
	 

endmodule
module ALU(
    input [15:0] x,
    input [15:0] y,
    input [5:0] control,
    output [15:0] out,  
    output zr,
    output ng
    );

	 
	 wire [15:0] Xz;
	 wire [15:0] Yz;
	 And16(x, ~{16{control[5]}}, Xz);
	 And16(y, ~{16{control[3]}}, Yz);
	 
	 wire [0:15] Xneg;
	 wire [0:15] Yneg;
	 
	 Not16(Xz, Xneg);
	 Not16(Yz, Yneg);
	 
	 wire [15:0] Xout;
	 wire [15:0] Yout;
	 
	 Mux16(Xz, Xneg, control[4], Xout);
	 Mux16(Yz, Yneg, control[2], Yout);
	 
	 wire [15:0] XplusY;
	 
	 Add16(Xout, Yout, XplusY);
	 
	 wire [15:0] XandY;
	 
	 And16(Xout, Yout, XandY);
	 
	 wire [15:0] almostOut;
	 
	 Mux16(XandY, XplusY, control[1], almostOut);
	 
	 wire [15:0] negOut;
	 
	 Not16(almostOut, negOut);	 
	 
	 Mux16(almostOut, negOut, control[0], out);
	 
	 assign ng = out[15];
	 Or16Way(out, notzr);
	 notGate(notzr, zr);
	 

endmodule