data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/axi_packer.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/axi_packer.v:38: Operator GT expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 2 bits.\n                                                                                                                             : ... In instance axi_packer\n        if (cnt > M-1) begin\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/axi_packer.v:60: Cannot find file containing module: \'axi_fifo_flop\'\n  axi_fifo_flop #(.WIDTH(WIDTH_OUT+1)) axi_fifo_flop_pack (\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/axi_fifo_flop\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/axi_fifo_flop.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/axi_fifo_flop.sv\n             axi_fifo_flop\n             axi_fifo_flop.v\n             axi_fifo_flop.sv\n             obj_dir/axi_fifo_flop\n             obj_dir/axi_fifo_flop.v\n             obj_dir/axi_fifo_flop.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module axi_packer #(
  parameter WIDTH_IN          = 8,
  parameter WIDTH_OUT         = 32,
  parameter REVERSE           = 0)
(
  input clk, input reset, input clear,
  input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
  output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
);

  localparam M = WIDTH_OUT/WIDTH_IN;

  reg packed_tlast, packed_tvalid;
  reg [WIDTH_OUT-1:0] packed_tdata;
  reg [$clog2(M)-1:0] cnt;
  reg i_tlast_hold;
  integer i;
  always @(posedge clk) begin
    if (reset | clear) begin
      i_tlast_hold      <= 1'b0;
      cnt               <= 'd0;
      packed_tdata      <= 'd0;
      packed_tvalid     <= 1'b0;
      packed_tlast      <= 1'b0;
    end else begin
      packed_tvalid     <= 1'b0;
      packed_tlast      <= 1'b0;
      if (i_tvalid & i_tready) begin
        if (i_tlast) begin
          i_tlast_hold  <= 1'b1;
        end
        if (cnt > M-1) begin
          cnt           <= 'd0;
          packed_tlast  <= i_tlast_hold;
          packed_tvalid <= 1'b1;
        end else begin
          cnt           <= cnt + 1;
        end
        if (REVERSE) begin
          packed_tdata[WIDTH_OUT-1:WIDTH_OUT-WIDTH_IN] <= i_tdata;
          for (i = 0; i < M-1; i = i + 1) begin
            packed_tdata[WIDTH_OUT-(i+1)*WIDTH_IN-1 -: WIDTH_IN] <= packed_tdata[WIDTH_OUT-i*WIDTH_IN-1 -: WIDTH_IN];
          end
        end else begin
          packed_tdata[WIDTH_IN-1:0] <= i_tdata;
          for (i = 0; i < M-1; i = i + 1) begin
            packed_tdata[(i+2)*WIDTH_IN-1 -: WIDTH_IN] <= packed_tdata[(i+1)*WIDTH_IN-1 -: WIDTH_IN];
          end
        end
      end
    end
  end

  axi_fifo_flop #(.WIDTH(WIDTH_OUT+1)) axi_fifo_flop_pack (
    .clk(clk), .reset(reset), .clear(clear),
    .i_tdata({packed_tlast,packed_tdata}), .i_tvalid(packed_tvalid), .i_tready(i_tready),
    .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
    .space(), .occupied());

endmodule
module axi_packer #(
  parameter WIDTH_IN          = 8,
  parameter WIDTH_OUT         = 32,
  parameter REVERSE           = 0)
(
  input clk, input reset, input clear,
  input [WIDTH_IN-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
  output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
);


  localparam M = WIDTH_OUT/WIDTH_IN;

  reg packed_tlast, packed_tvalid;
  reg [WIDTH_OUT-1:0] packed_tdata;
  reg [$clog2(M)-1:0] cnt;
  reg i_tlast_hold;
  integer i;
  always @(posedge clk) begin
    if (reset | clear) begin
      i_tlast_hold      <= 1'b0;
      cnt               <= 'd0;
      packed_tdata      <= 'd0;
      packed_tvalid     <= 1'b0;
      packed_tlast      <= 1'b0;
    end else begin
      packed_tvalid     <= 1'b0;
      packed_tlast      <= 1'b0;
      if (i_tvalid & i_tready) begin
        if (i_tlast) begin
          i_tlast_hold  <= 1'b1;
        end
        if (cnt > M-1) begin
          cnt           <= 'd0;
          packed_tlast  <= i_tlast_hold;
          packed_tvalid <= 1'b1;
        end else begin
          cnt           <= cnt + 1;
        end
        if (REVERSE) begin
          packed_tdata[WIDTH_OUT-1:WIDTH_OUT-WIDTH_IN] <= i_tdata;
          for (i = 0; i < M-1; i = i + 1) begin
            packed_tdata[WIDTH_OUT-(i+1)*WIDTH_IN-1 -: WIDTH_IN] <= packed_tdata[WIDTH_OUT-i*WIDTH_IN-1 -: WIDTH_IN];
          end
        end else begin
          packed_tdata[WIDTH_IN-1:0] <= i_tdata;
          for (i = 0; i < M-1; i = i + 1) begin
            packed_tdata[(i+2)*WIDTH_IN-1 -: WIDTH_IN] <= packed_tdata[(i+1)*WIDTH_IN-1 -: WIDTH_IN];
          end
        end
      end
    end
  end

  axi_fifo_flop #(.WIDTH(WIDTH_OUT+1)) axi_fifo_flop_pack (
    .clk(clk), .reset(reset), .clear(clear),
    .i_tdata({packed_tlast,packed_tdata}), .i_tvalid(packed_tvalid), .i_tready(i_tready),
    .o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
    .space(), .occupied());

endmodule