data/full_repos/permissive/159902111/PCPU_INT/SYNinterrupt.v
data/verilator_xmls/ffaaeb6b-5e97-42fb-9e01-8e59a1b2c235.xml
module SYNinterrupt(
  input clk,
  input rst,
  input INT,
  output SYN_INT);
  
  reg SYNINT;
  always@(posedge clk or posedge rst or posedge INT)
  begin
    if (rst)
      SYNINT <= 1'b0;
    else
      begin
        if (INT) SYNINT <= 1'b1;
        else SYNINT <= INT;
      end
  end
  assign SYN_INT = SYNINT;
endmodule
module SYNinterrupt(
  input clk,
  input rst,
  input INT,
  output SYN_INT);

  
  reg SYNINT;
  always@(posedge clk or posedge rst or posedge INT)
  begin
    if (rst)
      SYNINT <= 1'b0;
    else
      begin
        if (INT) SYNINT <= 1'b1;
        else SYNINT <= INT;
      end
  end
  assign SYN_INT = SYNINT;
endmodule