data/full_repos/permissive/186443491/datapath.v
1: b'%Warning-WIDTH: data/full_repos/permissive/186443491/datapath.v:42: Operator ADD expects 8 bits on the RHS, but RHS\'s REPLICATE generates 4 bits.\n                                                                  : ... In instance dataPath\n wire [7:0] mem_address = ({cout[7:4], 4\'d0} + {cout[3:0]}+1\'b1);\n                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/186443491/datapath.v:45: Cannot find file containing module: \'gold\'\n gold g0(\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/186443491,data/full_repos/permissive/186443491/gold\n             data/full_repos/permissive/186443491,data/full_repos/permissive/186443491/gold.v\n             data/full_repos/permissive/186443491,data/full_repos/permissive/186443491/gold.sv\n             gold\n             gold.v\n             gold.sv\n             obj_dir/gold\n             obj_dir/gold.v\n             obj_dir/gold.sv\n%Warning-WIDTH: data/full_repos/permissive/186443491/datapath.v:66: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'position_in\' generates 9 bits.\n                                                                  : ... In instance dataPath\n   y[7:0] <= position_in;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/186443491/datapath.v:77: Operator ADD expects 9 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                  : ... In instance dataPath\n    if(!draw_black) X_out <= x + cout[3:0];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/186443491/datapath.v:78: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                  : ... In instance dataPath\n    else X_out <= black_cout[7:0];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/186443491/datapath.v:87: Operator ADD expects 9 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                  : ... In instance dataPath\n    if(!draw_black) Y_out <= y + cout[7:4];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/186443491/datapath.v:88: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 7 bits.\n                                                                  : ... In instance dataPath\n    else Y_out <= black_cout[14:8];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/186443491/datapath.v:109: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                   : ... In instance dataPath\n  if(resetn == 0) black_cout <= 15\'b0;\n                             ^~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
module dataPath(
		clk, 

		resetn, 
		
		position_in, 
		
		load_color, 
		resetn_c, 
		enable_c, 
		load_x,
		load_y,
		enable_x_adder, 
		enable_y_adder,
		draw_black,
		
		X_out, 
		Y_out, 
		Color_out,
		cout,
		black_cout
		);
	input clk;
	input resetn;
	
	input [8:0]position_in;
	
	input load_color, resetn_c, enable_c, load_x, load_y, enable_x_adder, enable_y_adder, draw_black;
	
	output reg [8:0]X_out;
	output reg [8:0]Y_out;
	output reg [23:0]Color_out;
	output reg [8:0]cout;
	output reg [15:0]black_cout;
	
	reg [8:0]x;
	reg [8:0]y;
	
	wire [23:0]colour;
	
	
	wire [7:0] mem_address = ({cout[7:4], 4'd0} + {cout[3:0]}+1'b1);
	
	
	gold g0(
	.address(mem_address),
	.clock(clk),
	.q(colour));
	
	

	always@(posedge clk)begin
		if(resetn == 0) x <= 9'b0;
		else
			if(load_x) begin
			x[8:0] <= position_in;
			end
	end
	

	always@(posedge clk)begin
		if(resetn == 0) y <= 9'b0;
		else
			if(load_y) begin
			y[8] =1'b0;
			y[7:0] <= position_in;
			
			end
	end
	


	always@(posedge clk)begin
		if(resetn == 0) X_out <= 9'b0;
		else
			if(enable_x_adder) begin
				if(!draw_black) X_out <= x + cout[3:0];
				else X_out <= black_cout[7:0];
				end
	end
	

	always@(posedge clk)begin
		if(resetn == 0) Y_out <= 9'b0;
		else
			if(enable_y_adder)begin
				if(!draw_black) Y_out <= y + cout[7:4];
				else Y_out <= black_cout[14:8];
				end
	end
	

	always@(posedge clk)begin
		if(resetn == 0 | draw_black) Color_out <= 24'b0;
		else
		  Color_out <= colour;
	end
	

	always@(posedge clk)begin
		if((resetn == 0) | (resetn_c == 0)) cout <= 9'b0;
		else
			if(enable_c)
			cout <= cout + 1'b1;
	end
	

	always@(posedge clk)begin
		if(resetn == 0) black_cout <= 15'b0;
		else
			if(draw_black)
			black_cout <= black_cout + 1'b1;
	end
	
endmodule
module dataPath(
		clk, 

		resetn, 
		
		position_in, 
		
		load_color, 
		resetn_c, 
		enable_c, 
		load_x,
		load_y,
		enable_x_adder, 
		enable_y_adder,
		draw_black,
		
		X_out, 
		Y_out, 
		Color_out,
		cout,
		black_cout
		);

	input clk;
	input resetn;
	
	input [8:0]position_in;
	
	input load_color, resetn_c, enable_c, load_x, load_y, enable_x_adder, enable_y_adder, draw_black;
	
	output reg [8:0]X_out;
	output reg [8:0]Y_out;
	output reg [23:0]Color_out;
	output reg [8:0]cout;
	output reg [15:0]black_cout;
	
	reg [8:0]x;
	reg [8:0]y;
	
	wire [23:0]colour;
	
	
	wire [7:0] mem_address = ({cout[7:4], 4'd0} + {cout[3:0]}+1'b1);
	
	
	gold g0(
	.address(mem_address),
	.clock(clk),
	.q(colour));
	
	

	always@(posedge clk)begin
		if(resetn == 0) x <= 9'b0;
		else
			if(load_x) begin
			x[8:0] <= position_in;
			end
	end
	

	always@(posedge clk)begin
		if(resetn == 0) y <= 9'b0;
		else
			if(load_y) begin
			y[8] =1'b0;
			y[7:0] <= position_in;
			
			end
	end
	


	always@(posedge clk)begin
		if(resetn == 0) X_out <= 9'b0;
		else
			if(enable_x_adder) begin
				if(!draw_black) X_out <= x + cout[3:0];
				else X_out <= black_cout[7:0];
				end
	end
	

	always@(posedge clk)begin
		if(resetn == 0) Y_out <= 9'b0;
		else
			if(enable_y_adder)begin
				if(!draw_black) Y_out <= y + cout[7:4];
				else Y_out <= black_cout[14:8];
				end
	end
	

	always@(posedge clk)begin
		if(resetn == 0 | draw_black) Color_out <= 24'b0;
		else
		  Color_out <= colour;
	end
	

	always@(posedge clk)begin
		if((resetn == 0) | (resetn_c == 0)) cout <= 9'b0;
		else
			if(enable_c)
			cout <= cout + 1'b1;
	end
	

	always@(posedge clk)begin
		if(resetn == 0) black_cout <= 15'b0;
		else
			if(draw_black)
			black_cout <= black_cout + 1'b1;
	end
	
endmodule