data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v
 line:35: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:7: Unsupported: Ignoring delay on this delayed statement.\n always #1 CLOCK50 <= ~CLOCK50;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:37: Unsupported: Ignoring delay on this delayed statement.\n #20 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10\'H000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 top_inst.uart_wr_inst.uart_rtl_inst.data_recv = dat;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:40: Unsupported: Ignoring delay on this delayed statement.\n #2 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10\'H000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:41: Unsupported: Ignoring delay on this delayed statement.\n #2 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10\'H000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #0   CLOCK50 = 0; KEY = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #20   KEY = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #2000  $stop; \n  ^\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:37: Can\'t find definition of \'uart_wr_inst\' in dotted scope/variable: \'top_inst.uart_wr_inst\'\n #20 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10\'H000;\n              ^~~~~~~~~~~~\n        ... Known scopes under \'top_inst\': <no cells found>\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:37: Can\'t find definition of \'uart_rtl_inst\' in dotted scope/variable: \'top_inst.uart_rtl_inst\'\n #20 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10\'H000;\n                           ^~~~~~~~~~~~~\n        ... Known scopes under \'top_inst\': <no cells found>\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:38: Can\'t find definition of \'uart_wr_inst\' in dotted scope/variable: \'top_inst.uart_wr_inst\'\n #2 top_inst.uart_wr_inst.uart_rtl_inst.data_recv = dat;\n             ^~~~~~~~~~~~\n        ... Known scopes under \'top_inst\': <no cells found>\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:38: Can\'t find definition of \'uart_rtl_inst\' in dotted scope/variable: \'top_inst.uart_rtl_inst\'\n #2 top_inst.uart_wr_inst.uart_rtl_inst.data_recv = dat;\n                          ^~~~~~~~~~~~~\n        ... Known scopes under \'top_inst\': <no cells found>\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:39: Can\'t find definition of \'uart_wr_inst\' in dotted scope/variable: \'top_inst.uart_wr_inst\'\n  top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10\'H3E0;\n           ^~~~~~~~~~~~\n        ... Known scopes under \'top_inst\': <no cells found>\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:39: Can\'t find definition of \'uart_rtl_inst\' in dotted scope/variable: \'top_inst.uart_rtl_inst\'\n  top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10\'H3E0;\n                        ^~~~~~~~~~~~~\n        ... Known scopes under \'top_inst\': <no cells found>\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:40: Can\'t find definition of \'uart_wr_inst\' in dotted scope/variable: \'top_inst.uart_wr_inst\'\n #2 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10\'H000;\n             ^~~~~~~~~~~~\n        ... Known scopes under \'top_inst\': <no cells found>\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:40: Can\'t find definition of \'uart_rtl_inst\' in dotted scope/variable: \'top_inst.uart_rtl_inst\'\n #2 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10\'H000;\n                          ^~~~~~~~~~~~~\n        ... Known scopes under \'top_inst\': <no cells found>\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:41: Can\'t find definition of \'uart_wr_inst\' in dotted scope/variable: \'top_inst.uart_wr_inst\'\n #2 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10\'H000;\n             ^~~~~~~~~~~~\n        ... Known scopes under \'top_inst\': <no cells found>\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/tb_cmd_parser.v:41: Can\'t find definition of \'uart_rtl_inst\' in dotted scope/variable: \'top_inst.uart_rtl_inst\'\n #2 top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10\'H000;\n                          ^~~~~~~~~~~~~\n        ... Known scopes under \'top_inst\': <no cells found>\n%Error: Exiting due to 10 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_cmd_parser;
	
	reg			CLOCK50;
	reg	[3:0]	KEY;
	
	always #1	CLOCK50 <= ~CLOCK50;


	wire	[19:0]		SRAM_ADDR;
	wire	[15:0]		SRAM_DQ;
	wire				SRAM_LB_N,SRAM_UB_N;
	wire				SRAM_WE_N,SRAM_OE_N;
	wire				SRAM_CE_N;

	top					top_inst(
							.CLOCK_50(CLOCK50),
							.KEY(KEY),

							.SRAM_ADDR(SRAM_ADDR),
							.SRAM_DQ(SRAM_DQ),
							.SRAM_LB_N(SRAM_LB_N),.SRAM_UB_N(SRAM_UB_N),
							.SRAM_WE_N(SRAM_WE_N),.SRAM_OE_N(SRAM_OE_N),
							.SRAM_CE_N(SRAM_CE_N)
						);

	sram_sim			sram_sim_inst(
							.SRAM_ADDR(SRAM_ADDR),
							.SRAM_DQ(SRAM_DQ),
							.SRAM_LB_N(SRAM_LB_N),.SRAM_UB_N(SRAM_UB_N),
							.SRAM_WE_N(SRAM_WE_N),.SRAM_OE_N(SRAM_OE_N),
							.SRAM_CE_N(SRAM_CE_N)
						);
						
task uart_rx_byte(input [7:0] dat);
begin
	#20	top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H000;
	#2	top_inst.uart_wr_inst.uart_rtl_inst.data_recv = dat;
		top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H3E0;
	#2	top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H000;
	#2	top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H000;
end
endtask

	
	initial
	begin
	
		#0			CLOCK50 = 0; KEY = 0;
		#20			KEY = 1;
					uart_rx_byte(8'H6D); 
					uart_rx_byte(8'H73); 
					uart_rx_byte(8'H64); 
					uart_rx_byte(8'H64); 
					uart_rx_byte(8'H72); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H01); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H10); 
					uart_rx_byte(8'H00); 

		#2000		$stop; 
	end
	
endmodule
module tb_cmd_parser;

	
	reg			CLOCK50;
	reg	[3:0]	KEY;
	
	always #1	CLOCK50 <= ~CLOCK50;


	wire	[19:0]		SRAM_ADDR;
	wire	[15:0]		SRAM_DQ;
	wire				SRAM_LB_N,SRAM_UB_N;
	wire				SRAM_WE_N,SRAM_OE_N;
	wire				SRAM_CE_N;

	top					top_inst(
							.CLOCK_50(CLOCK50),
							.KEY(KEY),

							.SRAM_ADDR(SRAM_ADDR),
							.SRAM_DQ(SRAM_DQ),
							.SRAM_LB_N(SRAM_LB_N),.SRAM_UB_N(SRAM_UB_N),
							.SRAM_WE_N(SRAM_WE_N),.SRAM_OE_N(SRAM_OE_N),
							.SRAM_CE_N(SRAM_CE_N)
						);

	sram_sim			sram_sim_inst(
							.SRAM_ADDR(SRAM_ADDR),
							.SRAM_DQ(SRAM_DQ),
							.SRAM_LB_N(SRAM_LB_N),.SRAM_UB_N(SRAM_UB_N),
							.SRAM_WE_N(SRAM_WE_N),.SRAM_OE_N(SRAM_OE_N),
							.SRAM_CE_N(SRAM_CE_N)
						);
						
task uart_rx_byte(input [7:0] dat);
begin
	#20	top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H000;
	#2	top_inst.uart_wr_inst.uart_rtl_inst.data_recv = dat;
		top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H3E0;
	#2	top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H000;
	#2	top_inst.uart_wr_inst.uart_rtl_inst.ready_x = 10'H000;
end
endtask

	
	initial
	begin
	
		#0			CLOCK50 = 0; KEY = 0;
		#20			KEY = 1;
					uart_rx_byte(8'H6D); 
					uart_rx_byte(8'H73); 
					uart_rx_byte(8'H64); 
					uart_rx_byte(8'H64); 
					uart_rx_byte(8'H72); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H01); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H00); 
					uart_rx_byte(8'H10); 
					uart_rx_byte(8'H00); 

		#2000		$stop; 
	end
	
endmodule