data/full_repos/permissive/170693225/ad.v
 line:12: before: "&&"
1: b"%Error: data/full_repos/permissive/170693225/ad.v:14: syntax error, unexpected IDENTIFIER, expecting ';'\n ad1_finish = 1b'0;\n               ^\n%Error: data/full_repos/permissive/170693225/ad.v:27: syntax error, unexpected IDENTIFIER, expecting ';'\n ad1_finish = 1b'1; \n               ^\n%Error: Exiting due to 2 error(s)\n"
module ad(
          input ad_clk,
			 input [11:0] ad1_in,

			 
			 output reg [11:0] ad_ch1,

			 
			 output ad1_finish
    );
	 
always @(posedge ad_clk && ad1_flag)
begin
	ad1_finish = 1b'0;
   ad_ch1[11] <= ad1_in[0];  
   ad_ch1[10] <= ad1_in[1];  
   ad_ch1[9] <= ad1_in[2];  
   ad_ch1[8] <= ad1_in[3];  
   ad_ch1[7] <= ad1_in[4];  
   ad_ch1[6] <= ad1_in[5];  
   ad_ch1[5] <= ad1_in[6];  
   ad_ch1[4] <= ad1_in[7];  
   ad_ch1[3] <= ad1_in[8];  
   ad_ch1[2] <= ad1_in[9]; 
   ad_ch1[1] <= ad1_in[10];  
   ad_ch1[0] <= ad1_in[11];  
	ad1_finish = 1b'1; 
end



endmodule
module ad(
          input ad_clk,
			 input [11:0] ad1_in,

			 
			 output reg [11:0] ad_ch1,

			 
			 output ad1_finish
    );

	 
always @(posedge ad_clk && ad1_flag)
begin
	ad1_finish = 1b'0;
   ad_ch1[11] <= ad1_in[0];  
   ad_ch1[10] <= ad1_in[1];  
   ad_ch1[9] <= ad1_in[2];  
   ad_ch1[8] <= ad1_in[3];  
   ad_ch1[7] <= ad1_in[4];  
   ad_ch1[6] <= ad1_in[5];  
   ad_ch1[5] <= ad1_in[6];  
   ad_ch1[4] <= ad1_in[7];  
   ad_ch1[3] <= ad1_in[8];  
   ad_ch1[2] <= ad1_in[9]; 
   ad_ch1[1] <= ad1_in[10];  
   ad_ch1[0] <= ad1_in[11];  
	ad1_finish = 1b'1; 
end



endmodule