data/full_repos/permissive/143597583/rtl/verilog/support/sprom.v
1: b"%Error: data/full_repos/permissive/143597583/rtl/verilog/support/sprom.v:21: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule sprom(clk, rst, ce, oe, addr, do);\n                                     ^~\n%Error: data/full_repos/permissive/143597583/rtl/verilog/support/sprom.v:37: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n output reg [dw-1:0] do;    \n                     ^~\n%Error: data/full_repos/permissive/143597583/rtl/verilog/support/sprom.v:52: syntax error, unexpected '='\n   do = mem[ra];\n      ^\n%Error: Cannot continue\n"
module sprom(clk, rst, ce, oe, addr, do);



	parameter aw = 10;
	parameter dw = 32;
	parameter MEM_INIT_FILE = "";




	input           clk;
	input           rst;
	input           ce;
	input           oe;
	input  [aw-1:0] addr;
	output reg [dw-1:0] do;





	reg [dw-1:0] mem [(1<<aw) -1:0];
	reg [aw-1:0] ra;
	reg oe_r;

	always @(posedge clk)
		oe_r <= oe;

	always @*
		if (oe_r)
			do = mem[ra];


	always @(posedge clk)
	  if (ce)
	    ra <= addr;

	initial begin
		if (MEM_INIT_FILE != "") begin
			$readmemh(MEM_INIT_FILE, mem);
		end
	end

endmodule
module sprom(clk, rst, ce, oe, addr, do);




	parameter aw = 10;
	parameter dw = 32;
	parameter MEM_INIT_FILE = "";




	input           clk;
	input           rst;
	input           ce;
	input           oe;
	input  [aw-1:0] addr;
	output reg [dw-1:0] do;





	reg [dw-1:0] mem [(1<<aw) -1:0];
	reg [aw-1:0] ra;
	reg oe_r;

	always @(posedge clk)
		oe_r <= oe;

	always @*
		if (oe_r)
			do = mem[ra];


	always @(posedge clk)
	  if (ce)
	    ra <= addr;

	initial begin
		if (MEM_INIT_FILE != "") begin
			$readmemh(MEM_INIT_FILE, mem);
		end
	end

endmodule