data/full_repos/permissive/140357212/Tomasulo/multi_divi.v
data/verilator_xmls/a23c4163-2e46-431d-beab-4d455ef12d1b.xml
module FU_mul_div(clk,RUN,RegX,RegY,OpCode,Result,Done,InputX_MulDiv,InputLabel_MulDiv,AddressX,Label);
	input [8:0]RegX,RegY;
	input [2:0]OpCode;
	input clk,RUN;
	output reg Done;
	input [2:0]InputX_MulDiv,InputLabel_MulDiv;
	output [2:0]AddressX,Label;
	output reg [8:0]Result;
	wire [4:0]countDiv;
	wire [4:0]countMul;
	

	assign AddressX = InputX_MulDiv;
	assign Label = InputLabel_MulDiv;
	always@(clk,RegX,RegY,OpCode,RUN) begin
		Done = 0;
		if(countMul == 3 && OpCode == 3'b010) begin
			Result = RegX * RegY;
			Done = 1;
		end
		else if(countDiv == 4 && OpCode == 3'b011) begin
			Result = RegX / RegY;
			Done = 1;
		end

	end
	
	CountMul cm(clk,RUN,Done,countMul);
	CountDiv cd(clk,RUN,Done,countDiv);
endmodule
module FU_mul_div(clk,RUN,RegX,RegY,OpCode,Result,Done,InputX_MulDiv,InputLabel_MulDiv,AddressX,Label);

	input [8:0]RegX,RegY;
	input [2:0]OpCode;
	input clk,RUN;
	output reg Done;
	input [2:0]InputX_MulDiv,InputLabel_MulDiv;
	output [2:0]AddressX,Label;
	output reg [8:0]Result;
	wire [4:0]countDiv;
	wire [4:0]countMul;
	

	assign AddressX = InputX_MulDiv;
	assign Label = InputLabel_MulDiv;
	always@(clk,RegX,RegY,OpCode,RUN) begin
		Done = 0;
		if(countMul == 3 && OpCode == 3'b010) begin
			Result = RegX * RegY;
			Done = 1;
		end
		else if(countDiv == 4 && OpCode == 3'b011) begin
			Result = RegX / RegY;
			Done = 1;
		end

	end
	
	CountMul cm(clk,RUN,Done,countMul);
	CountDiv cd(clk,RUN,Done,countDiv);
endmodule