data/full_repos/permissive/135077285/shiftLeft.v
data/verilator_xmls/2a921a2e-39dd-42d4-9169-c8518ac1d855.xml
module shiftLeft (shift_input, shift_output);

	input [31:0] shift_input;
	output wire [31:0] shift_output;


	reg [31:0] aux;

	always @(*) begin
		aux = shift_input << 2;
	end

	assign shift_output = aux;

endmodule
module shiftLeft (shift_input, shift_output);


	input [31:0] shift_input;
	output wire [31:0] shift_output;


	reg [31:0] aux;

	always @(*) begin
		aux = shift_input << 2;
	end

	assign shift_output = aux;

endmodule