data/full_repos/permissive/125927162/LFSR/LFSR.v
data/verilator_xmls/c413eb70-3494-49aa-b9c9-667b35f92dd4.xml
module LFSR (
	input clk, 
	input rst, 
	output q);

	
   reg [15:0] sr;
   
   always @ (posedge clk) begin
      if (rst)
	 sr <= 1;
      else begin
	 sr[0] <= sr[15] ^ sr[13] ^ sr[12] ^ sr[10];
	 sr[15:1] <= sr[14:0];
      end
   end
   
   assign q = sr[15];
  
endmodule
module LFSR (
	input clk, 
	input rst, 
	output q);


	
   reg [15:0] sr;
   
   always @ (posedge clk) begin
      if (rst)
	 sr <= 1;
      else begin
	 sr[0] <= sr[15] ^ sr[13] ^ sr[12] ^ sr[10];
	 sr[15:1] <= sr[14:0];
      end
   end
   
   assign q = sr[15];
  
endmodule