data/full_repos/permissive/131921633/tv/Mips/mips_single.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:1: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips,data/full_repos/permissive/131921633/Data/Control/Control.v\n             data/full_repos/permissive/131921633/tv/Mips,data/full_repos/permissive/131921633/Data/Control/Control.v.v\n             data/full_repos/permissive/131921633/tv/Mips,data/full_repos/permissive/131921633/Data/Control/Control.v.sv\n             Data/Control/Control.v\n             Data/Control/Control.v.v\n             Data/Control/Control.v.sv\n             obj_dir/Data/Control/Control.v\n             obj_dir/Data/Control/Control.v.v\n             obj_dir/Data/Control/Control.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:3: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:4: Cannot find include file: Mips/Type/AluStatus.v\n`include "Mips/Type/AluStatus.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:5: Cannot find include file: Util/Math.v\n`include "Util/Math.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:7: Cannot find include file: Mips/Datapath/Alu/datapath.v\n`include "Mips/Datapath/Alu/datapath.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:8: Cannot find include file: Mips/Datapath/Pc/datapath.v\n`include "Mips/Datapath/Pc/datapath.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:9: Cannot find include file: Mips/Datapath/Memory/datapath.v\n`include "Mips/Datapath/Memory/datapath.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:10: Cannot find include file: Mips/Datapath/Register/datapath.v\n`include "Mips/Datapath/Register/datapath.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:12: Cannot find include file: Mips/Control/Control.v\n`include "Mips/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:13: Cannot find include file: Mips/Control/generate.v\n`include "Mips/Control/generate.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:20: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T(input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:20: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Control_Control_T(input) ctrl\n                           ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:21: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T(output)      pcAddr\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:24: Define or directive not defined: \'`Util_Math_log2_expr\'\n`Util_Math_log2_expr\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:26: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) instruction ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:28: Define or directive not defined: \'`Mips_Control_Control_T\'\n`Mips_Control_Control_T (wire) control ;\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:30: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) memOut ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:32: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) regPort1 ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:33: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) regPort2 ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:36: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T      (wire) aluResult ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:36: syntax error, unexpected \'(\'\n`Mips_Type_Word_T      (wire) aluResult ;\n                        ^~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:37: Define or directive not defined: \'`Mips_Type_AluStatus_T\'\n`Mips_Type_AluStatus_T (wire) aluStatus ;  \n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:39: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pcNext ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips_single.v:45: Define or directive not defined: \'`Mips_Type_Word_W\'\n , .DATA_W  (`Mips_Type_Word_W)\n             ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 24 error(s)\n'
module Mips_mips_single #
	( parameter FILE = "asm/old/test0.mif"
	, parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	)
	( `Data_Control_Control_T(input) ctrl
	, `Mips_Type_Word_T(output)      pcAddr
	);

`Util_Math_log2_expr

`Mips_Type_Word_T (wire) instruction ;

`Mips_Control_Control_T (wire) control ;

`Mips_Type_Word_T (wire) memOut ;

`Mips_Type_Word_T (wire) regPort1 ;
`Mips_Type_Word_T (wire) regPort2 ;
wire regPortEq ;

`Mips_Type_Word_T      (wire) aluResult ;
`Mips_Type_AluStatus_T (wire) aluStatus ;

`Mips_Type_Word_T (wire) pcNext ;

Mips_Datapath_Pc_datapath #
	( .FILE    (FILE)
	, .ADDR_L  (ADDR_L)
	, .ADDR_W  (ADDR_W)
	, .DATA_W  (`Mips_Type_Word_W)
	) PC
	( .ctrl (ctrl)
	, .control     (control)
	, .instruction (instruction)
	, .regPort1    (regPort1)
	, .regPortEq   (regPortEq)
	, .addrNext    (pcNext)
	, .addrCurr    (pcAddr)
	);

Mips_Control_generate CTRL
	( .instruction (instruction)
	, .control (control)
	);

Mips_Datapath_Register_datapath REG
	( .ctrl (ctrl)
	, .writeControl     (control)
	, .readInstruction  (instruction)
	, .writeInstruction (instruction)
	, .pcAddr           (pcAddr)
	, .memOut           (memOut)
	, .aluResult        (aluResult)
	, .port1            (regPort1)
	, .port2            (regPort2)
	, .portEq           (regPortEq)
	);

Mips_Datapath_Alu_datapath ALU
	( .ctrl (ctrl)
	, .instruction (instruction)
	, .regPort1    (regPort1)
	, .regPort2    (regPort2)
	, .control     (control)
	, .result      (aluResult)
	, .status      (aluStatus)
	);

Mips_Datapath_Memory_datapath #
	( .ADDR_L      (128)
	, .INVERT_CTRL (1)
	) RAM
	( .ctrl (ctrl)
	, .aluResult (aluResult)
	, .regPort2  (regPort2)
	, .control   (control)
	, .out       (memOut)
	);

endmodule
module Mips_mips_single #
	( parameter FILE = "asm/old/test0.mif"
	, parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	)
	( `Data_Control_Control_T(input) ctrl
	, `Mips_Type_Word_T(output)      pcAddr
	);


`Util_Math_log2_expr

`Mips_Type_Word_T (wire) instruction ;

`Mips_Control_Control_T (wire) control ;

`Mips_Type_Word_T (wire) memOut ;

`Mips_Type_Word_T (wire) regPort1 ;
`Mips_Type_Word_T (wire) regPort2 ;
wire regPortEq ;

`Mips_Type_Word_T      (wire) aluResult ;
`Mips_Type_AluStatus_T (wire) aluStatus ;

`Mips_Type_Word_T (wire) pcNext ;

Mips_Datapath_Pc_datapath #
	( .FILE    (FILE)
	, .ADDR_L  (ADDR_L)
	, .ADDR_W  (ADDR_W)
	, .DATA_W  (`Mips_Type_Word_W)
	) PC
	( .ctrl (ctrl)
	, .control     (control)
	, .instruction (instruction)
	, .regPort1    (regPort1)
	, .regPortEq   (regPortEq)
	, .addrNext    (pcNext)
	, .addrCurr    (pcAddr)
	);

Mips_Control_generate CTRL
	( .instruction (instruction)
	, .control (control)
	);

Mips_Datapath_Register_datapath REG
	( .ctrl (ctrl)
	, .writeControl     (control)
	, .readInstruction  (instruction)
	, .writeInstruction (instruction)
	, .pcAddr           (pcAddr)
	, .memOut           (memOut)
	, .aluResult        (aluResult)
	, .port1            (regPort1)
	, .port2            (regPort2)
	, .portEq           (regPortEq)
	);

Mips_Datapath_Alu_datapath ALU
	( .ctrl (ctrl)
	, .instruction (instruction)
	, .regPort1    (regPort1)
	, .regPort2    (regPort2)
	, .control     (control)
	, .result      (aluResult)
	, .status      (aluStatus)
	);

Mips_Datapath_Memory_datapath #
	( .ADDR_L      (128)
	, .INVERT_CTRL (1)
	) RAM
	( .ctrl (ctrl)
	, .aluResult (aluResult)
	, .regPort2  (regPort2)
	, .control   (control)
	, .out       (memOut)
	);

endmodule