data/full_repos/permissive/201488448/1_verilog/40_adder100.v
data/verilator_xmls/115abbde-6d6a-4941-a67f-9d86dc3a9547.xml
module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );

    add1 a0(a[0], b[0], cin, sum[0], cout[0]);
    
    genvar i;
    generate
        for(i=1;i<100;i=i+1) begin: test
            add1 ai(
                .a(a[i]),
                .b(b[i]),
                .cin(cout[i-1]),
                .sum(sum[i]),
                .cout(cout[i])
            ); 
        end
    endgenerate
    
endmodule
module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );


    add1 a0(a[0], b[0], cin, sum[0], cout[0]);
    
    genvar i;
    generate
        for(i=1;i<100;i=i+1) begin: test
            add1 ai(
                .a(a[i]),
                .b(b[i]),
                .cin(cout[i-1]),
                .sum(sum[i]),
                .cout(cout[i])
            ); 
        end
    endgenerate
    
endmodule