data/full_repos/permissive/159001439/src/divider.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:108: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'dividend_i\' generates 16 bits.\n                                                                      : ... In instance divider\n      grand_dividend <= dividend_i << R_PP;\n                                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:112: Operator SHIFTL expects 24 bits on the LHS, but LHS\'s VARREF \'divisor_i\' generates 8 bits.\n                                                                      : ... In instance divider\n      grand_divisor  <= divisor_i << (N_PP+R_PP-S_PP-1);\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:127: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'subtract_node\' generates 25 bits.\n                                                                      : ... In instance divider\n      if (~subtract_node[M_PP+N_PP+R_PP-1]) grand_dividend <= subtract_node;\n                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:143: Operator SUB expects 25 bits on the LHS, but LHS\'s REPLICATE generates 18 bits.\n                                                                      : ... In instance divider\nassign subtract_node = {1\'b0,grand_dividend} - {1\'b0,grand_divisor};\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:148: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s COND generates 17 bits.\n                                                                      : ... In instance divider\nassign quotient_o = (HOLD_OUTPUT == 0)?(quotient>>R_PP):(quotient_reg>>R_PP);\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/divider.v:149: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 17 bits.\n                                                                      : ... In instance divider\nassign remainder_o = (HOLD_OUTPUT == 0)?quotient:quotient_reg;\n                   ^\n%Error: Exiting due to 6 warning(s)\n'
module divider(
	rst_i,
	clk_i,
	valid_i,
	ready_o,
	dividend_i,
	divisor_i,
	quotient_o,
	remainder_o,
	valid_o
);

parameter DIVIDEND_BITS = 16;
parameter DIVISOR_BITS = 8;
parameter REMAINDER_BITS = 0;
parameter LEADING_ZERO_BITS = 0;
parameter HOLD_OUTPUT = 0;


function integer clogb2 (input integer size);
begin
	size = size - 1;
	for (clogb2=1; size>1; clogb2=clogb2+1)
		size = size >> 1;
end
endfunction


localparam M_PP = DIVIDEND_BITS;
localparam N_PP = DIVISOR_BITS;
localparam R_PP = REMAINDER_BITS>0 ? REMAINDER_BITS : 1;
localparam S_PP = LEADING_ZERO_BITS;

localparam COUNT_WIDTH_PP = clogb2(N_PP+R_PP-S_PP); 

input  clk_i;  
input  rst_i;
input  valid_i;
input  [M_PP-1:0] dividend_i;
input  [N_PP-1:0] divisor_i;
output [M_PP-1:0] quotient_o;
output [R_PP-1:0] remainder_o;
output ready_o;
output valid_o;

reg  ready_o;
reg  valid_o;


reg  [M_PP+R_PP-1:0] grand_dividend;
reg  [M_PP+N_PP+R_PP-2:0] grand_divisor;
reg  [M_PP+R_PP-S_PP-1:0] quotient;
reg  [M_PP+R_PP-1:0] quotient_reg;
reg  [COUNT_WIDTH_PP-1:0] divide_count;

wire [M_PP+N_PP+R_PP-1:0] subtract_node;
wire [M_PP+R_PP-1:0]      quotient_node;
wire [M_PP+N_PP+R_PP-2:0]  divisor_node;





always @(posedge clk_i)
begin
  if (rst_i)
  begin
    grand_dividend <= 0;
    grand_divisor <= 0;
    divide_count <= 0;
    quotient <= 0;
    ready_o <= 1;
	valid_o <= 0;
  end
  else if(ready_o && valid_i) begin
	  ready_o <= 0;
      quotient <= 0;
      divide_count <= 0;

      grand_dividend <= dividend_i << R_PP;



      grand_divisor  <= divisor_i << (N_PP+R_PP-S_PP-1);
	  valid_o <= 1'b0;
  end
  else if (!ready_o)
  begin
    if (divide_count == N_PP+R_PP-S_PP-1)
    begin
      quotient <= quotient_node;
      quotient_reg <= quotient_node;
      ready_o <= 1;
	  valid_o <= 1;
    end
    else
    begin

      if (~subtract_node[M_PP+N_PP+R_PP-1]) grand_dividend <= subtract_node;


      quotient <= quotient_node;

      grand_divisor <= divisor_node;

      divide_count <= divide_count + 1;
    end
  end
  else
  begin
	  valid_o <= 1'b0;
  end
end

assign subtract_node = {1'b0,grand_dividend} - {1'b0,grand_divisor};
assign quotient_node = 
  {quotient[M_PP+R_PP-S_PP-2:0],~subtract_node[M_PP+N_PP+R_PP-1]};
assign divisor_node  = {1'b0,grand_divisor[M_PP+N_PP+R_PP-2:1]};

assign quotient_o = (HOLD_OUTPUT == 0)?(quotient>>R_PP):(quotient_reg>>R_PP);
assign remainder_o = (HOLD_OUTPUT == 0)?quotient:quotient_reg;



endmodule
module divider(
	rst_i,
	clk_i,
	valid_i,
	ready_o,
	dividend_i,
	divisor_i,
	quotient_o,
	remainder_o,
	valid_o
);


parameter DIVIDEND_BITS = 16;
parameter DIVISOR_BITS = 8;
parameter REMAINDER_BITS = 0;
parameter LEADING_ZERO_BITS = 0;
parameter HOLD_OUTPUT = 0;


function integer clogb2 (input integer size);
begin
	size = size - 1;
	for (clogb2=1; size>1; clogb2=clogb2+1)
		size = size >> 1;
end
endfunction


localparam M_PP = DIVIDEND_BITS;
localparam N_PP = DIVISOR_BITS;
localparam R_PP = REMAINDER_BITS>0 ? REMAINDER_BITS : 1;
localparam S_PP = LEADING_ZERO_BITS;

localparam COUNT_WIDTH_PP = clogb2(N_PP+R_PP-S_PP); 

input  clk_i;  
input  rst_i;
input  valid_i;
input  [M_PP-1:0] dividend_i;
input  [N_PP-1:0] divisor_i;
output [M_PP-1:0] quotient_o;
output [R_PP-1:0] remainder_o;
output ready_o;
output valid_o;

reg  ready_o;
reg  valid_o;


reg  [M_PP+R_PP-1:0] grand_dividend;
reg  [M_PP+N_PP+R_PP-2:0] grand_divisor;
reg  [M_PP+R_PP-S_PP-1:0] quotient;
reg  [M_PP+R_PP-1:0] quotient_reg;
reg  [COUNT_WIDTH_PP-1:0] divide_count;

wire [M_PP+N_PP+R_PP-1:0] subtract_node;
wire [M_PP+R_PP-1:0]      quotient_node;
wire [M_PP+N_PP+R_PP-2:0]  divisor_node;





always @(posedge clk_i)
begin
  if (rst_i)
  begin
    grand_dividend <= 0;
    grand_divisor <= 0;
    divide_count <= 0;
    quotient <= 0;
    ready_o <= 1;
	valid_o <= 0;
  end
  else if(ready_o && valid_i) begin
	  ready_o <= 0;
      quotient <= 0;
      divide_count <= 0;

      grand_dividend <= dividend_i << R_PP;



      grand_divisor  <= divisor_i << (N_PP+R_PP-S_PP-1);
	  valid_o <= 1'b0;
  end
  else if (!ready_o)
  begin
    if (divide_count == N_PP+R_PP-S_PP-1)
    begin
      quotient <= quotient_node;
      quotient_reg <= quotient_node;
      ready_o <= 1;
	  valid_o <= 1;
    end
    else
    begin

      if (~subtract_node[M_PP+N_PP+R_PP-1]) grand_dividend <= subtract_node;


      quotient <= quotient_node;

      grand_divisor <= divisor_node;

      divide_count <= divide_count + 1;
    end
  end
  else
  begin
	  valid_o <= 1'b0;
  end
end

assign subtract_node = {1'b0,grand_dividend} - {1'b0,grand_divisor};
assign quotient_node = 
  {quotient[M_PP+R_PP-S_PP-2:0],~subtract_node[M_PP+N_PP+R_PP-1]};
assign divisor_node  = {1'b0,grand_divisor[M_PP+N_PP+R_PP-2:1]};

assign quotient_o = (HOLD_OUTPUT == 0)?(quotient>>R_PP):(quotient_reg>>R_PP);
assign remainder_o = (HOLD_OUTPUT == 0)?quotient:quotient_reg;



endmodule