data/full_repos/permissive/179884651/examples/WF_audio_demo.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:55: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:57: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:63: Signal definition not found, creating implicitly: \'ten_ms\'\n                                                                                   : ... Suggested alternative: \'ten_us\'\n           .timer_pulse(ten_ms));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:69: Signal definition not found, creating implicitly: \'quarter_second\'\n           .timer_pulse(quarter_second));\n                        ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:78: Signal definition not found, creating implicitly: \'switch_pushed\'\n      .switch_pushed(switch_pushed),     \n                     ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:108: Signal definition not found, creating implicitly: \'sclk_fall\'\n  assign sclk_fall = sclk_d && ~SCK;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:48: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.v\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:214: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h1 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:216: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h3 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:219: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h6 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:220: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h7 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:222: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h9 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:223: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'ha : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:224: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'hb : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:244: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                 : ... In instance fpga_top\n    assign sinlut = sine[phase_acc[15:8]];\n                  ^\n%Error: Exiting due to 1 error(s), 14 warning(s)\n'
module fpga_top (
    output reg  MCLK,
    output reg  LRCK,
    output reg  SCK,
    output wire SDATA,

    input  wire WF_CPU1,
    input  wire WF_BUTTON
);



   reg [31:0] shift_data;
   reg        sclk_d;
   reg [15:0] phase_acc;

   wire mclk_pulse;
   wire lrck_pulse;
   wire sclk_pulse;


   reg [5:0] cnt1;
   reg [5:0] note;
   reg [3:0] melody;
   reg [15:0] tone;




    wire clk_en;
    assign clk_en = 1'b1;





  SB_HFOSC OSC_i (
        .CLKHFEN(clk_en),
        .CLKHFPU(clk_en),
        .CLKHF(clk));


     WF_timer #(.COUNT(479), .EVERY_CLK(1'b1)) ten_usec(
           .clk(clk),
           .enable(1'b1),
           .timer_pulse(ten_us));


     WF_timer #(.COUNT(999)) ten_msec(
           .clk(clk),
           .enable(ten_us),
           .timer_pulse(ten_ms));


     WF_timer #(.COUNT(24)) quarter_sec(
           .clk(clk),
           .enable(ten_ms),
           .timer_pulse(quarter_second));



    WF_switch_debounce switch_debounce_inst (
      .clk(clk),
      .sample_en(ten_ms),
      .switch_in(WF_BUTTON),
      .switch_out(),
      .switch_pushed(switch_pushed),
      .switch_released()
     );





WF_i2s_pulses WF_i2s_pulses_inst(
              .clk(clk),
              .mclk_pulse(mclk_pulse),
              .lrck_pulse(lrck_pulse),
              .sclk_pulse(sclk_pulse));



  always @(posedge clk)
    begin
      sclk_d <= SCK && ~lrck_pulse;

      if (mclk_pulse)
        MCLK <= ~MCLK;

      if (lrck_pulse)
        LRCK <= ~LRCK;

      if (sclk_pulse)
        SCK <= ~SCK;
      end

  assign sclk_fall = sclk_d && ~SCK;







reg     [7:0] sine [0:255];
initial $readmemh("/sine.hex", sine);





































  always @(*)
      case (note[3:0])
          4'h0 : tone = 16'd356;
          4'h1 : tone = 16'd378;
          4'h2 : tone = 16'd401;
          4'h3 : tone = 16'd424;
          4'h4 : tone = 16'd450;
          4'h5 : tone = 16'd476;
          4'h6 : tone = 16'd505;
          4'h7 : tone = 16'd534;
          4'h8 : tone = 16'd566;
          4'h9 : tone = 16'd599;
          4'ha : tone = 16'd635;
          4'hb : tone = 16'd674;
          4'hc : tone = 16'd000;
      endcase

      parameter C  = 6'h0;
      parameter Df = 6'h1;
      parameter Cs = 6'h1;
      parameter D  = 6'h2;
      parameter Ef = 6'h3;
      parameter Ds = 6'h3;
      parameter E  = 6'h4;
      parameter F  = 6'h5;
      parameter Fs = 6'h6;
      parameter Gf = 6'h6;
      parameter G  = 6'h7;
      parameter Af = 6'h8;
      parameter Gs = 6'h8;
      parameter A  = 6'h9;
      parameter Bf = 6'ha;
      parameter As = 6'ha;
      parameter B  = 6'hb;
      parameter none = 4'hc;
      parameter OL = 6'b11_0000;
      parameter OH = 6'b10_0000;

  always @(*)
      case (melody[3:0])
      `ifdef CETK
	      4'h0 : note = G;
	      4'h1 : note = A;
	      4'h2 : note = F;
	      4'h3 : note = F+OL;
	      4'h4 : note = C;
	      4'h5 : note = none;
	      4'h6 : note = none;
	      4'h7 : note = none;
	      4'h8 : note = Bf;
	      4'h9 : note = C;
	      4'ha : note = Af;
	      4'hb : note = Af+OL;
	      4'hc : note = Ef;
	      4'hd : note = none;
	      4'he : note = none;
	      4'hf : note = none;
      `else
	      4'h0 : note = G+OL;
	      4'h1 : note = none;
	      4'h2 : note = G+OL;
	      4'h3 : note = none;
	      4'h4 : note = G+OL;
	      4'h5 : note = C;
	      4'h6 : note = none;
	      4'h7 : note = none;
	      4'h8 : note = G;
	      4'h9 : note = none;
	      4'ha : note = none;
	      4'hb : note = none;
	      4'hc : note = F;
	      4'hd : note = E;
	      4'he : note = D;
	      4'hf : note = C+OH;
      `endif
      endcase




   always @ (posedge clk)                                                       
       if ((quarter_second && WF_CPU1) || switch_pushed)
           melody <= melody + 1;





    wire   [6:0] sinlut;
    assign sinlut = sine[phase_acc[15:8]];

  always @(posedge clk)
    if (lrck_pulse && LRCK)
      begin

        phase_acc <= phase_acc + (note[5] ? (note[4] ? {1'b0,tone[15:1]} :{tone[14:0],1'b0})  : tone);  






        shift_data <= {16'h0,sinlut[6],
                             sinlut[6] ? 1'b1:1'b0,
                             sinlut[6] ? 1'b1:1'b0,
                             sinlut[6] ? 1'b1:1'b0,
                             sinlut[6] ? 1'b1:1'b0,
                             sinlut[5:0],5'b0};   
      end
    else if (sclk_fall)
      shift_data <= {shift_data[30:0],1'b0};

  assign SDATA = shift_data[31];

endmodule
module fpga_top (
    output reg  MCLK,
    output reg  LRCK,
    output reg  SCK,
    output wire SDATA,

    input  wire WF_CPU1,
    input  wire WF_BUTTON
);




   reg [31:0] shift_data;
   reg        sclk_d;
   reg [15:0] phase_acc;

   wire mclk_pulse;
   wire lrck_pulse;
   wire sclk_pulse;


   reg [5:0] cnt1;
   reg [5:0] note;
   reg [3:0] melody;
   reg [15:0] tone;




    wire clk_en;
    assign clk_en = 1'b1;





  SB_HFOSC OSC_i (
        .CLKHFEN(clk_en),
        .CLKHFPU(clk_en),
        .CLKHF(clk));


     WF_timer #(.COUNT(479), .EVERY_CLK(1'b1)) ten_usec(
           .clk(clk),
           .enable(1'b1),
           .timer_pulse(ten_us));


     WF_timer #(.COUNT(999)) ten_msec(
           .clk(clk),
           .enable(ten_us),
           .timer_pulse(ten_ms));


     WF_timer #(.COUNT(24)) quarter_sec(
           .clk(clk),
           .enable(ten_ms),
           .timer_pulse(quarter_second));



    WF_switch_debounce switch_debounce_inst (
      .clk(clk),
      .sample_en(ten_ms),
      .switch_in(WF_BUTTON),
      .switch_out(),
      .switch_pushed(switch_pushed),
      .switch_released()
     );





WF_i2s_pulses WF_i2s_pulses_inst(
              .clk(clk),
              .mclk_pulse(mclk_pulse),
              .lrck_pulse(lrck_pulse),
              .sclk_pulse(sclk_pulse));



  always @(posedge clk)
    begin
      sclk_d <= SCK && ~lrck_pulse;

      if (mclk_pulse)
        MCLK <= ~MCLK;

      if (lrck_pulse)
        LRCK <= ~LRCK;

      if (sclk_pulse)
        SCK <= ~SCK;
      end

  assign sclk_fall = sclk_d && ~SCK;







reg     [7:0] sine [0:255];
initial $readmemh("/sine.hex", sine);





































  always @(*)
      case (note[3:0])
          4'h0 : tone = 16'd356;
          4'h1 : tone = 16'd378;
          4'h2 : tone = 16'd401;
          4'h3 : tone = 16'd424;
          4'h4 : tone = 16'd450;
          4'h5 : tone = 16'd476;
          4'h6 : tone = 16'd505;
          4'h7 : tone = 16'd534;
          4'h8 : tone = 16'd566;
          4'h9 : tone = 16'd599;
          4'ha : tone = 16'd635;
          4'hb : tone = 16'd674;
          4'hc : tone = 16'd000;
      endcase

      parameter C  = 6'h0;
      parameter Df = 6'h1;
      parameter Cs = 6'h1;
      parameter D  = 6'h2;
      parameter Ef = 6'h3;
      parameter Ds = 6'h3;
      parameter E  = 6'h4;
      parameter F  = 6'h5;
      parameter Fs = 6'h6;
      parameter Gf = 6'h6;
      parameter G  = 6'h7;
      parameter Af = 6'h8;
      parameter Gs = 6'h8;
      parameter A  = 6'h9;
      parameter Bf = 6'ha;
      parameter As = 6'ha;
      parameter B  = 6'hb;
      parameter none = 4'hc;
      parameter OL = 6'b11_0000;
      parameter OH = 6'b10_0000;

  always @(*)
      case (melody[3:0])
      `ifdef CETK
	      4'h0 : note = G;
	      4'h1 : note = A;
	      4'h2 : note = F;
	      4'h3 : note = F+OL;
	      4'h4 : note = C;
	      4'h5 : note = none;
	      4'h6 : note = none;
	      4'h7 : note = none;
	      4'h8 : note = Bf;
	      4'h9 : note = C;
	      4'ha : note = Af;
	      4'hb : note = Af+OL;
	      4'hc : note = Ef;
	      4'hd : note = none;
	      4'he : note = none;
	      4'hf : note = none;
      `else
	      4'h0 : note = G+OL;
	      4'h1 : note = none;
	      4'h2 : note = G+OL;
	      4'h3 : note = none;
	      4'h4 : note = G+OL;
	      4'h5 : note = C;
	      4'h6 : note = none;
	      4'h7 : note = none;
	      4'h8 : note = G;
	      4'h9 : note = none;
	      4'ha : note = none;
	      4'hb : note = none;
	      4'hc : note = F;
	      4'hd : note = E;
	      4'he : note = D;
	      4'hf : note = C+OH;
      `endif
      endcase




   always @ (posedge clk)                                                       
       if ((quarter_second && WF_CPU1) || switch_pushed)
           melody <= melody + 1;





    wire   [6:0] sinlut;
    assign sinlut = sine[phase_acc[15:8]];

  always @(posedge clk)
    if (lrck_pulse && LRCK)
      begin

        phase_acc <= phase_acc + (note[5] ? (note[4] ? {1'b0,tone[15:1]} :{tone[14:0],1'b0})  : tone);  






        shift_data <= {16'h0,sinlut[6],
                             sinlut[6] ? 1'b1:1'b0,
                             sinlut[6] ? 1'b1:1'b0,
                             sinlut[6] ? 1'b1:1'b0,
                             sinlut[6] ? 1'b1:1'b0,
                             sinlut[5:0],5'b0};   
      end
    else if (sclk_fall)
      shift_data <= {shift_data[30:0],1'b0};

  assign SDATA = shift_data[31];

endmodule