data/full_repos/permissive/206437232/TP2-UART-2019/Verilog/interface_circuit.v
 line:57 column:23: Illegal character "'"
1: b'%Warning-WIDTH: data/full_repos/permissive/206437232/TP2-UART-2019/Verilog/interface_circuit.v:59: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'i_rx_data_in\' generates 8 bits.\n                                                                                                 : ... In instance interface_circuit\n                    2\'b 10: o_operation  = i_rx_data_in;\n                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module interface_circuit
#(
	parameter  DBIT  = 8,
	           NB_OP = 6
	            
) 
(
	input                     i_clk,
 	input                     i_reset,
 	input                     i_rx_done_tick,
 	input      [DBIT-1:0]     i_rx_data_in,
 	input      [DBIT-1:0]     i_alu_data_in,

	output reg [DBIT-1 : 0]   o_data_a,
	output reg [DBIT-1 : 0]   o_data_b,
	output reg [NB_OP-1 : 0]  o_operation,
 	output reg                o_tx_start,
 	output     [DBIT-1:0]     o_data_out 
);
	reg [1 : 0] counter_in = 2'b00;
	
	assign o_data_out = i_alu_data_in;
	
	always @(posedge i_clk) 
	begin
        if (!i_reset)  begin 
            o_data_a      <= 0;
            o_data_b      <= 0;
            o_operation   <= 0;
            counter_in    <= 0;
            o_tx_start    <= 1'b0;
        end else begin
            if (i_rx_done_tick) begin
                case (counter_in)
                    2'b 00: o_data_a     = i_rx_data_in;
                    2'b 01: o_data_b     = i_rx_data_in;
                    2'b 10: o_operation  = i_rx_data_in;
                endcase		
                counter_in = counter_in + 1'b1;		
            end
            if (counter_in == 2'b11) begin
                counter_in = 0;	
                o_tx_start   = 1'b1;
            end else begin
                o_tx_start = 1'b0;
            end
        end
	end
endmodule
module interface_circuit
#(
	parameter  DBIT  = 8,
	           NB_OP = 6
	            
) 
(
	input                     i_clk,
 	input                     i_reset,
 	input                     i_rx_done_tick,
 	input      [DBIT-1:0]     i_rx_data_in,
 	input      [DBIT-1:0]     i_alu_data_in,

	output reg [DBIT-1 : 0]   o_data_a,
	output reg [DBIT-1 : 0]   o_data_b,
	output reg [NB_OP-1 : 0]  o_operation,
 	output reg                o_tx_start,
 	output     [DBIT-1:0]     o_data_out 
);

	reg [1 : 0] counter_in = 2'b00;
	
	assign o_data_out = i_alu_data_in;
	
	always @(posedge i_clk) 
	begin
        if (!i_reset)  begin 
            o_data_a      <= 0;
            o_data_b      <= 0;
            o_operation   <= 0;
            counter_in    <= 0;
            o_tx_start    <= 1'b0;
        end else begin
            if (i_rx_done_tick) begin
                case (counter_in)
                    2'b 00: o_data_a     = i_rx_data_in;
                    2'b 01: o_data_b     = i_rx_data_in;
                    2'b 10: o_operation  = i_rx_data_in;
                endcase		
                counter_in = counter_in + 1'b1;		
            end
            if (counter_in == 2'b11) begin
                counter_in = 0;	
                o_tx_start   = 1'b1;
            end else begin
                o_tx_start = 1'b0;
            end
        end
	end
endmodule