data/full_repos/permissive/21051978/processor/alutb_andy.v
None: at end of input
1: b'%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:25: Cannot find include file: alu.v\n`include "alu.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/alu.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/alu.v.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/alu.v.sv\n             alu.v\n             alu.v.v\n             alu.v.sv\n             obj_dir/alu.v\n             obj_dir/alu.v.v\n             obj_dir/alu.v.sv\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:26: Cannot find include file: control.h\n`include "control.h" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:131: Define or directive not defined: \'`aa\'\n  c_ppp=`aa;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:131: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`aa;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:132: Define or directive not defined: \'`w8\'\n  c_ww=`w8;  \n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:132: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;  \n          ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:133: Define or directive not defined: \'`aluwprm\'\n  a_op=`aluwprm;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:133: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwprm;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/alutb_andy.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:140: Define or directive not defined: \'`aa\'\n  c_ppp=`aa;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:140: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`aa;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:141: Define or directive not defined: \'`w8\'\n  c_ww=`w8;  \n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:141: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;  \n          ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:142: Define or directive not defined: \'`aluwprm\'\n  a_op=`aluwprm;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:142: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwprm;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/alutb_andy.v:143: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:150: Define or directive not defined: \'`uu\'\n  c_ppp=`uu;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:150: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`uu;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:151: Define or directive not defined: \'`w8\'\n  c_ww=`w8;  \n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:151: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;  \n          ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:152: Define or directive not defined: \'`aluwprm\'\n  a_op=`aluwprm;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:152: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwprm;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/alutb_andy.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:159: Define or directive not defined: \'`dd\'\n  c_ppp=`dd;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:159: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`dd;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:160: Define or directive not defined: \'`w8\'\n  c_ww=`w8;  \n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:160: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;  \n          ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:161: Define or directive not defined: \'`aluwprm\'\n  a_op=`aluwprm;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:161: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwprm;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/alutb_andy.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:168: Define or directive not defined: \'`ee\'\n                                                                      : ... Suggested alternative: \'`else\'\n  c_ppp=`ee;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:168: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`ee;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:169: Define or directive not defined: \'`w8\'\n  c_ww=`w8;  \n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:169: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;  \n          ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:170: Define or directive not defined: \'`aluwprm\'\n  a_op=`aluwprm;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:170: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwprm;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/alutb_andy.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:177: Define or directive not defined: \'`oo\'\n  c_ppp=`oo;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:177: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`oo;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:178: Define or directive not defined: \'`w8\'\n  c_ww=`w8;  \n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:178: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;  \n          ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:179: Define or directive not defined: \'`aluwprm\'\n  a_op=`aluwprm;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:179: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwprm;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/alutb_andy.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:186: Define or directive not defined: \'`mm\'\n  c_ppp=`mm;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:186: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`mm;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:187: Define or directive not defined: \'`w8\'\n  c_ww=`w8;  \n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:187: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;  \n          ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:188: Define or directive not defined: \'`aluwprm\'\n  a_op=`aluwprm;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:188: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwprm;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/alutb_andy.v:189: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:195: Define or directive not defined: \'`ll\'\n  c_ppp=`ll;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:195: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`ll;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:196: Define or directive not defined: \'`w8\'\n  c_ww=`w8;  \n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:196: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;  \n          ^\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:197: Define or directive not defined: \'`aluwprm\'\n  a_op=`aluwprm;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/alutb_andy.v:197: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwprm;\n               ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module tb_alu();


	


	wire [0:127] res;
	
	
	
	
	
	
	

	


	reg [0:127] r_A;

	reg [0:127] r_B;

	reg [0:2] c_ppp;

	reg [0:1] c_ww;

	reg [0:4] a_op;

	reg [0:127] e_r;
	
	
	
	

	


	
	

	
	

	

	alu alu1 (



		r_A,r_B,c_ppp,c_ww,a_op,res);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");	




		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h000102030405060708090a0b0c0d0e0f;
		e_r=128'h0123456789abcdef0123456789abcdef;
		c_ppp=`aa;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h23456789abcdef0123456789abcdef01;
		c_ppp=`aa;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;



		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h23456789abcdef010000000000000000;
		c_ppp=`uu;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h000000000000000023456789abcdef01;
		c_ppp=`dd;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h23006700ab00ef0023006700ab00ef00;
		c_ppp=`ee;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h0045008900cd00010045008900cd0001;
		c_ppp=`oo;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h23000000000000000000000000000000;
		c_ppp=`mm;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h00000000000000000000000000000001;
		c_ppp=`ll;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;



		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_alu();



	


	wire [0:127] res;
	
	
	
	
	
	
	

	


	reg [0:127] r_A;

	reg [0:127] r_B;

	reg [0:2] c_ppp;

	reg [0:1] c_ww;

	reg [0:4] a_op;

	reg [0:127] e_r;
	
	
	
	

	


	
	

	
	

	

	alu alu1 (



		r_A,r_B,c_ppp,c_ww,a_op,res);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");	




		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h000102030405060708090a0b0c0d0e0f;
		e_r=128'h0123456789abcdef0123456789abcdef;
		c_ppp=`aa;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h23456789abcdef0123456789abcdef01;
		c_ppp=`aa;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;



		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h23456789abcdef010000000000000000;
		c_ppp=`uu;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h000000000000000023456789abcdef01;
		c_ppp=`dd;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h23006700ab00ef0023006700ab00ef00;
		c_ppp=`ee;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h0045008900cd00010045008900cd0001;
		c_ppp=`oo;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h23000000000000000000000000000000;
		c_ppp=`mm;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;


		r_A=128'h0123456789abcdef0123456789abcdef;
		r_B=128'h0102030405060708090a0b0c0d0e0f00;
		e_r=128'h00000000000000000000000000000001;
		c_ppp=`ll;
		c_ww=`w8;
		a_op=`aluwprm;
		#10;



		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule