data/full_repos/permissive/132220215/half_subtractor.v
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data/verilator_xmls/6460f3ca-9613-4b88-975a-5d8c7808317c.xml
module half_subtract(
	input A,
	input B,
	output D,
	output Bo);

 xor(D,A,B);
 wire w;
 not(w,A);
 and(Bo,w,B);
endmodule
module half_subtract(
	input A,
	input B,
	output D,
	output Bo);


 xor(D,A,B);
 wire w;
 not(w,A);
 and(Bo,w,B);
endmodule