data/full_repos/permissive/174642777/Experiments/Lab X2/Lab 04 DEC_7seg/DEC_7seg.v
1: b'%Error: Cannot find file containing module: X2/Lab\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X2/Lab\n             data/full_repos/permissive/174642777/Experiments/Lab/X2/Lab.v\n             data/full_repos/permissive/174642777/Experiments/Lab/X2/Lab.sv\n             X2/Lab\n             X2/Lab.v\n             X2/Lab.sv\n             obj_dir/X2/Lab\n             obj_dir/X2/Lab.v\n             obj_dir/X2/Lab.sv\n%Error: Cannot find file containing module: 04\n%Error: Cannot find file containing module: DEC_7seg,data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: DEC_7seg/DEC_7seg.v\n%Error: Exiting due to 5 error(s)\n'
module DEC_7seg(
	input wire[3:0] X,
	output wire a,b,c,d,e,f,g,
	output wire act, neg
);
	
	assign a = X==1
				| X==4
				| X==11
				| X==13;
	
	assign b = X==5
				| X==6
				| X==11
				| X==12
				| X==14
				| X==15;
	
	assign c = X==2
				| X==12
				| X==14
				| X==15;
	
	assign d = X==1
				| X==4
				| X==7
				| X==10
				| X==15;
	
	assign e = X==1
				| X==3
				| X==4
				| X==5
				| X==7
				| X==9;
	
	assign f = X==1
				| X==2
				| X==3
				| X==7
				| X==13;
	
	assign g = X==0
				| X==1
				| X==7
				| X==12;
	
	assign act = 1;
	assign neg = 0;

endmodule
module DEC_7seg(
	input wire[3:0] X,
	output wire a,b,c,d,e,f,g,
	output wire act, neg
);

	
	assign a = X==1
				| X==4
				| X==11
				| X==13;
	
	assign b = X==5
				| X==6
				| X==11
				| X==12
				| X==14
				| X==15;
	
	assign c = X==2
				| X==12
				| X==14
				| X==15;
	
	assign d = X==1
				| X==4
				| X==7
				| X==10
				| X==15;
	
	assign e = X==1
				| X==3
				| X==4
				| X==5
				| X==7
				| X==9;
	
	assign f = X==1
				| X==2
				| X==3
				| X==7
				| X==13;
	
	assign g = X==0
				| X==1
				| X==7
				| X==12;
	
	assign act = 1;
	assign neg = 0;

endmodule