data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/bitwise_xor_testbench.v
 line:35: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/bitwise_xor_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/bitwise_xor_testbench.v:28: Cannot find file containing module: \'bitwise_xor\'\nbitwise_xor x(out,i0,i1);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new,data/full_repos/permissive/169574047/bitwise_xor\n             data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new,data/full_repos/permissive/169574047/bitwise_xor.v\n             data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new,data/full_repos/permissive/169574047/bitwise_xor.sv\n             bitwise_xor\n             bitwise_xor.v\n             bitwise_xor.sv\n             obj_dir/bitwise_xor\n             obj_dir/bitwise_xor.v\n             obj_dir/bitwise_xor.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bitwise_xor_testbench;

wire [31:0] out;
reg [31:0] i0,i1;

bitwise_xor x(out,i0,i1);

initial
begin
    i0 = 32'b1111_1110_1100_1000_0001_0011_0111_1111;
    i1 = 32'b0101_0101_0101_0101_0101_0101_0101_0101;

    #5 $finish;
end


endmodule
module bitwise_xor_testbench;


wire [31:0] out;
reg [31:0] i0,i1;

bitwise_xor x(out,i0,i1);

initial
begin
    i0 = 32'b1111_1110_1100_1000_0001_0011_0111_1111;
    i1 = 32'b0101_0101_0101_0101_0101_0101_0101_0101;

    #5 $finish;
end


endmodule