data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim/lfsr_tb.v
1: b"%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim/lfsr_tb.v:30: Cannot find file containing module: 'clock_gen'\n  clock_gen clkgen(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim,data/full_repos/permissive/181738725/clock_gen\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim,data/full_repos/permissive/181738725/clock_gen.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim,data/full_repos/permissive/181738725/clock_gen.sv\n             clock_gen\n             clock_gen.v\n             clock_gen.sv\n             obj_dir/clock_gen\n             obj_dir/clock_gen.v\n             obj_dir/clock_gen.sv\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim/lfsr_tb.v:40: Cannot find file containing module: 'lfsr_source'\n  lfsr_source #(\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/sim/lfsr_tb.v:91: Cannot find file containing module: 'lfsr_sink'\n  lfsr_sink #(\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module lfsr_tb;

  localparam DataBits = 32;




  wire clk, rst;
  clock_gen clkgen(
    .clk (clk),
    .rst (rst));




  wire                din_valid, din_ready, din_eof;
  wire [DataBits-1:0] din_data;

  lfsr_source #(
    .DataBits  (DataBits),
    .GoDefault (1),
    .MaxLength (64))
  lfsr_src (

    .cfg_clk     (clk),
    .cfg_rst     (rst),
    .cfg_paddr   (5'b0),
    .cfg_pwrite  (1'b0),
    .cfg_pwdata  (32'b0),
    .cfg_psel    (1'b0),
    .cfg_penable (1'b0),
    .cfg_pready  ( ),
    .cfg_prdata  ( ),
    .cfg_pslverr ( ),

    .dout_clk  (clk),
    .dout_rst  (rst),
    .dout_ready(din_ready),
    .dout_valid(din_valid),
    .dout_data (din_data),
    .dout_eof  (din_eof));


  reg [15:0] count;
  always @(posedge clk) begin
    if (rst) begin
      count <= 0;
    end else begin
      count <= count + 1;
    end
  end

  reg [DataBits-1:0] din_err;
  always @(*) begin
    din_err             = din_data;

    din_err[0]          = !din_data[0];
    din_err[1]          = !din_data[1];
    din_err[5]          = !din_data[5];
    din_err[DataBits-1] = !din_data[DataBits-1];
    din_err[DataBits-4] = !din_data[DataBits-4];
    din_err[DataBits-5] = !din_data[DataBits-5];
  end

  wire [DataBits-1:0] din_data_i =  (count[2:0] == 7) ? din_err : din_data;




  lfsr_sink #(
    .DataBits (DataBits))
  lfsr_snk (

    .cfg_clk     (clk),
    .cfg_rst     (rst),
    .cfg_paddr   (5'b0),
    .cfg_pwrite  (1'b0),
    .cfg_pwdata  (32'b0),
    .cfg_psel    (1'b0),
    .cfg_penable (1'b0),
    .cfg_pready  ( ),
    .cfg_prdata  ( ),
    .cfg_pslverr ( ),

    .din_clk  (clk),
    .din_rst  (rst),
    .din_ready(din_ready),
    .din_valid(din_valid),
    .din_data (din_data_i),
    .din_eof  (din_eof));


endmodule
module lfsr_tb;


  localparam DataBits = 32;




  wire clk, rst;
  clock_gen clkgen(
    .clk (clk),
    .rst (rst));




  wire                din_valid, din_ready, din_eof;
  wire [DataBits-1:0] din_data;

  lfsr_source #(
    .DataBits  (DataBits),
    .GoDefault (1),
    .MaxLength (64))
  lfsr_src (

    .cfg_clk     (clk),
    .cfg_rst     (rst),
    .cfg_paddr   (5'b0),
    .cfg_pwrite  (1'b0),
    .cfg_pwdata  (32'b0),
    .cfg_psel    (1'b0),
    .cfg_penable (1'b0),
    .cfg_pready  ( ),
    .cfg_prdata  ( ),
    .cfg_pslverr ( ),

    .dout_clk  (clk),
    .dout_rst  (rst),
    .dout_ready(din_ready),
    .dout_valid(din_valid),
    .dout_data (din_data),
    .dout_eof  (din_eof));


  reg [15:0] count;
  always @(posedge clk) begin
    if (rst) begin
      count <= 0;
    end else begin
      count <= count + 1;
    end
  end

  reg [DataBits-1:0] din_err;
  always @(*) begin
    din_err             = din_data;

    din_err[0]          = !din_data[0];
    din_err[1]          = !din_data[1];
    din_err[5]          = !din_data[5];
    din_err[DataBits-1] = !din_data[DataBits-1];
    din_err[DataBits-4] = !din_data[DataBits-4];
    din_err[DataBits-5] = !din_data[DataBits-5];
  end

  wire [DataBits-1:0] din_data_i =  (count[2:0] == 7) ? din_err : din_data;




  lfsr_sink #(
    .DataBits (DataBits))
  lfsr_snk (

    .cfg_clk     (clk),
    .cfg_rst     (rst),
    .cfg_paddr   (5'b0),
    .cfg_pwrite  (1'b0),
    .cfg_pwdata  (32'b0),
    .cfg_psel    (1'b0),
    .cfg_penable (1'b0),
    .cfg_pready  ( ),
    .cfg_prdata  ( ),
    .cfg_pslverr ( ),

    .din_clk  (clk),
    .din_rst  (rst),
    .din_ready(din_ready),
    .din_valid(din_valid),
    .din_data (din_data_i),
    .din_eof  (din_eof));


endmodule