data/full_repos/permissive/143278/ivltests/br991a.v
1: b'%Error: data/full_repos/permissive/143278/ivltests/br991a.v:12: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br991a.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br991a.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br991a.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br991a.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br991a.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br991a.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module test();

reg	  clk;
reg [1:0] state;

always begin
  case (state)
    0       : state = 1;
    1       : state = 2;
    default :;
  endcase
  @(posedge clk);
end

reg failed = 0;

initial begin
  clk = 0;
  state = 0;
  #1 clk = 1;
  #1 clk = 0;
  if (state !== 1) failed = 1;
  #1 clk = 1;
  #1 clk = 0;
  if (state !== 2) failed = 1;
  #1 clk = 1;
  #1 clk = 0;
  if (state !== 2) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module test();


reg	  clk;
reg [1:0] state;

always begin
  case (state)
    0       : state = 1;
    1       : state = 2;
    default :;
  endcase
  @(posedge clk);
end

reg failed = 0;

initial begin
  clk = 0;
  state = 0;
  #1 clk = 1;
  #1 clk = 0;
  if (state !== 1) failed = 1;
  #1 clk = 1;
  #1 clk = 0;
  if (state !== 2) failed = 1;
  #1 clk = 1;
  #1 clk = 0;
  if (state !== 2) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule