data/full_repos/permissive/140157152/hdl/sampler.v
1: b"%Error: data/full_repos/permissive/140157152/hdl/sampler.v:62: Cannot find file containing module: 'sample_fifo'\nsample_fifo negedge_fifo (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/140157152/hdl,data/full_repos/permissive/140157152/sample_fifo\n             data/full_repos/permissive/140157152/hdl,data/full_repos/permissive/140157152/sample_fifo.v\n             data/full_repos/permissive/140157152/hdl,data/full_repos/permissive/140157152/sample_fifo.sv\n             sample_fifo\n             sample_fifo.v\n             sample_fifo.sv\n             obj_dir/sample_fifo\n             obj_dir/sample_fifo.v\n             obj_dir/sample_fifo.sv\n%Error: data/full_repos/permissive/140157152/hdl/sampler.v:73: Cannot find file containing module: 'sample_fifo'\nsample_fifo posedge_fifo (\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module sampler (
	input system_clock,
	input [31:0] channel,
	output [31:0] out,
	input negedge_read_enable,
	input posedge_read_enable,
	output posedge_empty,
	output posedge_full,
	output negedge_empty,
	output negedge_full,
	input clear,
	input s4_mask,
	input s5_mask,
	input cctl_mask);


wire fi2 = channel[1];







wire write_clock = ~fi2;

wire [31:0] posedge_fifo_q;
wire [31:0] negedge_fifo_q;
reg select = 1'b0;
reg [31:0] channel_latch;
wire s4_n_latch = channel_latch[2];
wire s5_n_latch = channel_latch[3];
wire cctl_n_latch = channel_latch[4];
wire write_enable = ~((s4_n_latch|s4_mask) & (s5_n_latch|s5_mask) & (cctl_n_latch|cctl_mask));

assign out = select ? negedge_fifo_q : posedge_fifo_q;

always @(posedge fi2) begin
	channel_latch <= channel;
end

always @(posedge system_clock) begin
	if (posedge_read_enable | negedge_read_enable)
		select <= negedge_read_enable;
end

sample_fifo negedge_fifo (
	.aclr(clear),
	.data(channel),
	.rdclk(system_clock),
	.rdreq(negedge_read_enable),
	.wrclk(write_clock),
	.wrreq(write_enable),
	.q(negedge_fifo_q),
	.rdempty(negedge_empty),
	.rdfull(negedge_full));

sample_fifo posedge_fifo (
	.aclr(clear),
	.data(channel_latch),
	.rdclk(system_clock),
	.rdreq(posedge_read_enable),
	.wrclk(write_clock),
	.wrreq(write_enable),
	.q(posedge_fifo_q),
	.rdempty(posedge_empty),
	.rdfull(posedge_full));

endmodule
module sampler (
	input system_clock,
	input [31:0] channel,
	output [31:0] out,
	input negedge_read_enable,
	input posedge_read_enable,
	output posedge_empty,
	output posedge_full,
	output negedge_empty,
	output negedge_full,
	input clear,
	input s4_mask,
	input s5_mask,
	input cctl_mask);



wire fi2 = channel[1];







wire write_clock = ~fi2;

wire [31:0] posedge_fifo_q;
wire [31:0] negedge_fifo_q;
reg select = 1'b0;
reg [31:0] channel_latch;
wire s4_n_latch = channel_latch[2];
wire s5_n_latch = channel_latch[3];
wire cctl_n_latch = channel_latch[4];
wire write_enable = ~((s4_n_latch|s4_mask) & (s5_n_latch|s5_mask) & (cctl_n_latch|cctl_mask));

assign out = select ? negedge_fifo_q : posedge_fifo_q;

always @(posedge fi2) begin
	channel_latch <= channel;
end

always @(posedge system_clock) begin
	if (posedge_read_enable | negedge_read_enable)
		select <= negedge_read_enable;
end

sample_fifo negedge_fifo (
	.aclr(clear),
	.data(channel),
	.rdclk(system_clock),
	.rdreq(negedge_read_enable),
	.wrclk(write_clock),
	.wrreq(write_enable),
	.q(negedge_fifo_q),
	.rdempty(negedge_empty),
	.rdfull(negedge_full));

sample_fifo posedge_fifo (
	.aclr(clear),
	.data(channel_latch),
	.rdclk(system_clock),
	.rdreq(posedge_read_enable),
	.wrclk(write_clock),
	.wrreq(write_enable),
	.q(posedge_fifo_q),
	.rdempty(posedge_empty),
	.rdfull(posedge_full));

endmodule