data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor_ds.v
1: b'%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor_ds.v:15: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_0, net_1, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor_ds.v:16: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_0, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor_ds.v:17: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, Y, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor_ds.v:18: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(net_11, Y, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor_ds.v:19: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_11, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor_ds.v:20: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_1, vdd, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor_ds.v:21: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_1, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor_ds.v:22: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(Y, vdd, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor_ds.v:23: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_28, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor_ds.v:24: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(Y, net_28, A);\n          ^~~~~~\n%Error: Exiting due to 10 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module xnor_ds(A, B, Y);
  input A;
  input B;
  output Y;

  supply1 vdd;
  supply0 gnd;
  wire net_0, net_1, net_11, net_28;

  tranif1 nmos_0(net_0, net_1, A);
  tranif1 nmos_1(gnd, net_0, B);
  tranif1 nmos_4(net_11, Y, A);
  tranif1 nmos_5(net_11, Y, B);
  tranif1 nmos_6(gnd, net_11, net_1);
  tranif0 pmos_0(net_1, vdd, A);
  tranif0 pmos_1(net_1, vdd, B);
  tranif0 pmos_2(Y, vdd, net_1);
  tranif0 pmos_3(net_28, vdd, B);
  tranif0 pmos_4(Y, net_28, A);
endmodule
module xnor_ds(A, B, Y);

  input A;
  input B;
  output Y;

  supply1 vdd;
  supply0 gnd;
  wire net_0, net_1, net_11, net_28;

  tranif1 nmos_0(net_0, net_1, A);
  tranif1 nmos_1(gnd, net_0, B);
  tranif1 nmos_4(net_11, Y, A);
  tranif1 nmos_5(net_11, Y, B);
  tranif1 nmos_6(gnd, net_11, net_1);
  tranif0 pmos_0(net_1, vdd, A);
  tranif0 pmos_1(net_1, vdd, B);
  tranif0 pmos_2(Y, vdd, net_1);
  tranif0 pmos_3(net_28, vdd, B);
  tranif0 pmos_4(Y, net_28, A);
endmodule