data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/TestBenches/mix_columns_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/TestBenches/mix_columns_tb.v:89: syntax error, unexpected \'@\'\n  repeat(500) @ (posedge clock50MHz);  \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/TestBenches/mix_columns_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #(HALF_CLOCK_PERIOD);\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module mix_columns_tb;

reg  [127:0] inputValue;
reg startTransition;
reg clock50MHz;
wire [127:0] outputValue;

mix_columns #(

	.ENCRYPT		(1)	
	) dut(
	.inputData			(inputValue),
	.startTransition	(startTransition),
	.outputData 		(outputValue)
);		

localparam NUM_CYCLES = 20000;
localparam CLOCK_FREQ = 50000000;

real HALF_CLOCK_PERIOD = (1000000000.0 / $itor(CLOCK_FREQ)) / 2.0;

integer half_cycle = 0;	


initial begin
	inputValue = 128'h2b30c0a0cbab929f20c793eba2af2f63;
	startTransition = 0;
	clock50MHz = 0;
end

initial begin
  repeat(500) @ (posedge clock50MHz);  
  startTransition = 1;
end


always begin
	#(HALF_CLOCK_PERIOD);
	clock50MHz = ~clock50MHz;
	half_cycle = half_cycle + 1;
	
	if (half_cycle == (2 * NUM_CYCLES)) begin		
		$stop;
	end
end
endmodule
module mix_columns_tb;


reg  [127:0] inputValue;
reg startTransition;
reg clock50MHz;
wire [127:0] outputValue;

mix_columns #(

	.ENCRYPT		(1)	
	) dut(
	.inputData			(inputValue),
	.startTransition	(startTransition),
	.outputData 		(outputValue)
);		

localparam NUM_CYCLES = 20000;
localparam CLOCK_FREQ = 50000000;

real HALF_CLOCK_PERIOD = (1000000000.0 / $itor(CLOCK_FREQ)) / 2.0;

integer half_cycle = 0;	


initial begin
	inputValue = 128'h2b30c0a0cbab929f20c793eba2af2f63;
	startTransition = 0;
	clock50MHz = 0;
end

initial begin
  repeat(500) @ (posedge clock50MHz);  
  startTransition = 1;
end


always begin
	#(HALF_CLOCK_PERIOD);
	clock50MHz = ~clock50MHz;
	half_cycle = half_cycle + 1;
	
	if (half_cycle == (2 * NUM_CYCLES)) begin		
		$stop;
	end
end
endmodule