data/full_repos/permissive/203650831/hd44780_bytesender.v
None: at end of input
1: b'%Error: data/full_repos/permissive/203650831/hd44780_bytesender.v:17: Cannot find include file: ./hd44780_build_config.inc\n`include "./hd44780_build_config.inc" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203650831,data/full_repos/permissive/203650831/./hd44780_build_config.inc\n             data/full_repos/permissive/203650831,data/full_repos/permissive/203650831/./hd44780_build_config.inc.v\n             data/full_repos/permissive/203650831,data/full_repos/permissive/203650831/./hd44780_build_config.inc.sv\n             ./hd44780_build_config.inc\n             ./hd44780_build_config.inc.v\n             ./hd44780_build_config.inc.sv\n             obj_dir/./hd44780_build_config.inc\n             obj_dir/./hd44780_build_config.inc.v\n             obj_dir/./hd44780_build_config.inc.sv\n%Error: Exiting due to 1 error(s)\n'
module hd44780_bytesender(
    input wire RST_I,
    input wire CLK_I,
    input wire STB_I,
    input wire i_rs,
    input wire[7:0] i_lcd_data,
    output wire busy,
    output wire o_rs,
    output wire [3:0] o_lcd_data,
    output wire o_e
);




    reg ns_ststrobe = 0;
    wire ns_busy;
    reg [3:0] ns_nybbin = 4'b0000;
	reg byts_rs_reg = 0;

    hd44780_nybble_sender nybsen(
        .RST_I(RST_I),
        .CLK_I(CLK_I),
        .STB_I(ns_ststrobe),
		.i_rs(byts_rs_reg),
        .i_nybble(ns_nybbin),
        .o_busy(ns_busy),
        .o_lcd_data(o_lcd_data),
        .o_rs(o_rs),
        .o_e(o_e)
    );

















    reg [2:0] byts_state = 0;
    reg byts_busy_reg = 0;
    reg [7:0] i_lcd_data_shadow = 0;


    localparam st_c_idle = 3'b000;
    localparam st_c_waitstb = 3'b001;
    localparam st_c_nyb1 = 3'b010;
    localparam st_c_stb1 = 3'b011;
    localparam st_c_dstb1 = 3'b100;
    localparam st_c_nyb2 = 3'b101;
    localparam st_c_stb2 = 3'b110;
    localparam st_c_dstb2 = 3'b111;

    always @(posedge CLK_I) begin
        if(RST_I) begin

            ns_ststrobe <= 0;
            ns_nybbin <= 0;
            byts_state <= 0;
            byts_busy_reg <= 0;
			byts_rs_reg <= 0;
		end else if (STB_I & ~busy)	begin

            byts_busy_reg <= 1;
			byts_rs_reg <= i_rs;
            byts_state <= st_c_waitstb;
        end else begin





            case(byts_state)
                st_c_idle: begin
                    byts_busy_reg <= 0;
                end

                st_c_waitstb: begin

                    if(~STB_I) begin
                        i_lcd_data_shadow <= i_lcd_data;
                        byts_state <= st_c_nyb1;
                    end
                end


                st_c_nyb1: begin


                    ns_nybbin <= {i_lcd_data_shadow[7],i_lcd_data_shadow[6],i_lcd_data_shadow[5],i_lcd_data_shadow[4]};
                    byts_state <= st_c_stb1;
                end

                st_c_stb1: begin

                    ns_ststrobe <= 1;
                    byts_state <= st_c_dstb1;
                end

                st_c_dstb1: begin

                    ns_ststrobe <= 0;
                    byts_state <= st_c_nyb2;
                end

                st_c_nyb2: begin

                    if(~ns_busy) begin
                        byts_state <= st_c_stb2;


                        ns_nybbin <= {i_lcd_data_shadow[3],i_lcd_data_shadow[2],i_lcd_data_shadow[1],i_lcd_data_shadow[0]};
                    end
                end

                st_c_stb2: begin

                    ns_ststrobe <= 1;
                    byts_state <= st_c_dstb2;
                end

                st_c_dstb2: begin

                    ns_ststrobe <= 0;
                    byts_state <= st_c_idle;
                end
				
				default: begin
                    byts_state <= st_c_idle;
				end
            endcase
        end
    end

	assign busy = byts_busy_reg | ns_busy;

endmodule
module hd44780_bytesender(
    input wire RST_I,
    input wire CLK_I,
    input wire STB_I,
    input wire i_rs,
    input wire[7:0] i_lcd_data,
    output wire busy,
    output wire o_rs,
    output wire [3:0] o_lcd_data,
    output wire o_e
);





    reg ns_ststrobe = 0;
    wire ns_busy;
    reg [3:0] ns_nybbin = 4'b0000;
	reg byts_rs_reg = 0;

    hd44780_nybble_sender nybsen(
        .RST_I(RST_I),
        .CLK_I(CLK_I),
        .STB_I(ns_ststrobe),
		.i_rs(byts_rs_reg),
        .i_nybble(ns_nybbin),
        .o_busy(ns_busy),
        .o_lcd_data(o_lcd_data),
        .o_rs(o_rs),
        .o_e(o_e)
    );

















    reg [2:0] byts_state = 0;
    reg byts_busy_reg = 0;
    reg [7:0] i_lcd_data_shadow = 0;


    localparam st_c_idle = 3'b000;
    localparam st_c_waitstb = 3'b001;
    localparam st_c_nyb1 = 3'b010;
    localparam st_c_stb1 = 3'b011;
    localparam st_c_dstb1 = 3'b100;
    localparam st_c_nyb2 = 3'b101;
    localparam st_c_stb2 = 3'b110;
    localparam st_c_dstb2 = 3'b111;

    always @(posedge CLK_I) begin
        if(RST_I) begin

            ns_ststrobe <= 0;
            ns_nybbin <= 0;
            byts_state <= 0;
            byts_busy_reg <= 0;
			byts_rs_reg <= 0;
		end else if (STB_I & ~busy)	begin

            byts_busy_reg <= 1;
			byts_rs_reg <= i_rs;
            byts_state <= st_c_waitstb;
        end else begin





            case(byts_state)
                st_c_idle: begin
                    byts_busy_reg <= 0;
                end

                st_c_waitstb: begin

                    if(~STB_I) begin
                        i_lcd_data_shadow <= i_lcd_data;
                        byts_state <= st_c_nyb1;
                    end
                end


                st_c_nyb1: begin


                    ns_nybbin <= {i_lcd_data_shadow[7],i_lcd_data_shadow[6],i_lcd_data_shadow[5],i_lcd_data_shadow[4]};
                    byts_state <= st_c_stb1;
                end

                st_c_stb1: begin

                    ns_ststrobe <= 1;
                    byts_state <= st_c_dstb1;
                end

                st_c_dstb1: begin

                    ns_ststrobe <= 0;
                    byts_state <= st_c_nyb2;
                end

                st_c_nyb2: begin

                    if(~ns_busy) begin
                        byts_state <= st_c_stb2;


                        ns_nybbin <= {i_lcd_data_shadow[3],i_lcd_data_shadow[2],i_lcd_data_shadow[1],i_lcd_data_shadow[0]};
                    end
                end

                st_c_stb2: begin

                    ns_ststrobe <= 1;
                    byts_state <= st_c_dstb2;
                end

                st_c_dstb2: begin

                    ns_ststrobe <= 0;
                    byts_state <= st_c_idle;
                end
				
				default: begin
                    byts_state <= st_c_idle;
				end
            endcase
        end
    end

	assign busy = byts_busy_reg | ns_busy;

endmodule