data/full_repos/permissive/136510272/projects/x8086/marsohod2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/x8086/marsohod2.v:61: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                  : ... In instance marsohod2\nreg  [1:0] d25 = 1\'b0;\n                 ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/136510272/projects/x8086/marsohod2.v:68: Cannot find file containing module: \'mem_ram16k\'\nmem_ram16k RAM16K(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/projects/x8086,data/full_repos/permissive/136510272/mem_ram16k\n             data/full_repos/permissive/136510272/projects/x8086,data/full_repos/permissive/136510272/mem_ram16k.v\n             data/full_repos/permissive/136510272/projects/x8086,data/full_repos/permissive/136510272/mem_ram16k.sv\n             mem_ram16k\n             mem_ram16k.v\n             mem_ram16k.sv\n             obj_dir/mem_ram16k\n             obj_dir/mem_ram16k.v\n             obj_dir/mem_ram16k.sv\n%Error: data/full_repos/permissive/136510272/projects/x8086/marsohod2.v:83: Cannot find file containing module: \'cpu\'\ncpu CPU(\n^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module marsohod2(




    input   wire        clk,


    output  reg  [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);


assign sdram_addr = o_addr[11:0];

reg  [1:0] d25 = 1'b0;
always @(negedge clk) d25 <= d25 + 1'b1;

wire [19:0] o_addr;
wire [7:0]  o_data;
wire [7:0]  i_data;

mem_ram16k RAM16K(

    .clock   (clk),    


    .addr_wr (o_addr[13:0]),
    .data_wr (o_data),
    .wren    (o_write),
    .qw      (i_data)

);




cpu CPU(

    d25[1],
    1'b0,
    o_addr,
    i_data,
    o_data,
    o_write

);

endmodule
module marsohod2(




    input   wire        clk,


    output  reg  [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);



assign sdram_addr = o_addr[11:0];

reg  [1:0] d25 = 1'b0;
always @(negedge clk) d25 <= d25 + 1'b1;

wire [19:0] o_addr;
wire [7:0]  o_data;
wire [7:0]  i_data;

mem_ram16k RAM16K(

    .clock   (clk),    


    .addr_wr (o_addr[13:0]),
    .data_wr (o_data),
    .wren    (o_write),
    .qw      (i_data)

);




cpu CPU(

    d25[1],
    1'b0,
    o_addr,
    i_data,
    o_data,
    o_write

);

endmodule