data/full_repos/permissive/156539908/first-demo/first-demo.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/156539908/first-demo/first-demo.v:189: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'top\'\nmodule top (\n       ^~~\n                                                                                   : ... Top module \'button_debouncer\'\nmodule button_debouncer (\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156539908/first-demo/first-demo.v:279: Cannot find file containing module: \'SB_IO\'\n    SB_IO #(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/156539908/first-demo,data/full_repos/permissive/156539908/SB_IO\n             data/full_repos/permissive/156539908/first-demo,data/full_repos/permissive/156539908/SB_IO.v\n             data/full_repos/permissive/156539908/first-demo,data/full_repos/permissive/156539908/SB_IO.sv\n             SB_IO\n             SB_IO.v\n             SB_IO.sv\n             obj_dir/SB_IO\n             obj_dir/SB_IO.v\n             obj_dir/SB_IO.sv\n%Error: data/full_repos/permissive/156539908/first-demo/first-demo.v:267: Cannot find file containing module: \'SB_GB\'\n    SB_GB rst_gb (\n    ^~~~~\n%Error: data/full_repos/permissive/156539908/first-demo/first-demo.v:234: Cannot find file containing module: \'SB_PLL40_PAD\'\n    SB_PLL40_PAD #(\n    ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:66: Operator ASSIGNW expects 21 bits on the Assign RHS, but Assign RHS\'s VARREF \'frame_counter\' generates 20 bits.\n                                                                               : ... In instance top\n    assign {frame, subframe} = frame_counter;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:88: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 6 bits.\n                                                                               : ... In instance top\n    assign xx = x + frame[5:0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:89: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'y0\' generates 6 bits.\n                                                                               : ... In instance top\n    assign yy0 = y0 + frame[5:2];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:89: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                               : ... In instance top\n    assign yy0 = y0 + frame[5:2];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:90: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'y1\' generates 6 bits.\n                                                                               : ... In instance top\n    assign yy1 = y1 + frame[5:2];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:90: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                               : ... In instance top\n    assign yy1 = y1 + frame[5:2];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:91: Operator XOR expects 8 bits on the LHS, but LHS\'s VARREF \'x\' generates 7 bits.\n                                                                               : ... In instance top\n    assign xort = x ^ frame[9:2];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:91: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s XOR generates 8 bits.\n                                                                               : ... In instance top\n    assign xort = x ^ frame[9:2];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:99: Operator ASSIGNW expects 24 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                               : ... In instance top\n    assign rgb0 = {red0 > cmp, grn0 > cmp, blu0 > cmp};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:100: Operator ASSIGNW expects 24 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                                : ... In instance top\n    assign rgb1 = {red1 > cmp, grn1 > cmp, blu1 > cmp};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:161: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'rgb0\' generates 24 bits.\n                                                                                : ... In instance top\n                        led_rgb0  <= rgb0;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:162: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'rgb1\' generates 24 bits.\n                                                                                : ... In instance top\n                        led_rgb1  <= rgb1;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/156539908/first-demo/first-demo.v:209: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'counter\' generates 13 bits.\n                                                                                : ... In instance button_debouncer\n        if (counter) begin\n        ^~\n%Error: Exiting due to 3 error(s), 14 warning(s)\n'
module pll_30mhz (
        input clk_pin,
        input reset_pin,
        output locked,
        output clk30);

    SB_PLL40_PAD #(
        .FEEDBACK_PATH("SIMPLE"),
        .DIVR(4'b0000),
        .DIVF(7'b1001111),
        .DIVQ(3'b101),
        .FILTER_RANGE(3'b001)
    ) the_pll (
        .PACKAGEPIN(clk_pin),
        .PLLOUTCORE(clk30),
        .LOCK(locked),
        .RESETB(reset_pin),
        .BYPASS(1'b0)
    );

endmodule
module pll_30mhz (
        input clk_pin,
        input reset_pin,
        output locked,
        output clk30);


    SB_PLL40_PAD #(
        .FEEDBACK_PATH("SIMPLE"),
        .DIVR(4'b0000),
        .DIVF(7'b1001111),
        .DIVQ(3'b101),
        .FILTER_RANGE(3'b001)
    ) the_pll (
        .PACKAGEPIN(clk_pin),
        .PLLOUTCORE(clk30),
        .LOCK(locked),
        .RESETB(reset_pin),
        .BYPASS(1'b0)
    );

endmodule