data/full_repos/permissive/208113388/afu/lpc/lpc_errary.v
 line:9: before: "*"
data/verilator_xmls/cf857d5e-29cd-4436-8284-72e1506206f4.xml
module lpc_errary (
    input          clock
  , input          reset


  , input   [15:0] ery_loadsrc
  , input  [127:0] ery_src15
  , input  [127:0] ery_src14         




  , input  [127:0] ery_src09         
  , input  [127:0] ery_src08         
  , input  [127:0] ery_src07         
  , input  [127:0] ery_src06         
  , input  [127:0] ery_src05         
  , input  [127:0] ery_src04         
  , input  [127:0] ery_src03         
  , input  [127:0] ery_src02         
  , input  [127:0] ery_src01         
  , input  [127:0] ery_src00        


  , output [127:0] ery_data_out
  , output         ery_data_valid
  , input          ery_data_done


  , output         ery_simultaneous_load
  , output         ery_overflow
  , output         ery_trigger_intrp
) ;




reg  [127:0] captured_src15;
reg  [127:0] captured_src14;




reg  [127:0] captured_src09;
reg  [127:0] captured_src08;
reg  [127:0] captured_src07;
reg  [127:0] captured_src06;
reg  [127:0] captured_src05;
reg  [127:0] captured_src04;
reg  [127:0] captured_src03;
reg  [127:0] captured_src02;
reg  [127:0] captured_src01;
reg  [127:0] captured_src00;
reg   [15:0] captured_loadsrc;

always @(posedge(clock))
  begin
    captured_src15 <= (ery_loadsrc[15] == 1'b1) ? ery_src15 : captured_src15;
    captured_src14 <= (ery_loadsrc[14] == 1'b1) ? ery_src14 : captured_src14;




    captured_src09 <= (ery_loadsrc[09] == 1'b1) ? ery_src09 : captured_src09;
    captured_src08 <= (ery_loadsrc[08] == 1'b1) ? ery_src08 : captured_src08;
    captured_src07 <= (ery_loadsrc[07] == 1'b1) ? ery_src07 : captured_src07;
    captured_src06 <= (ery_loadsrc[06] == 1'b1) ? ery_src06 : captured_src06;
    captured_src05 <= (ery_loadsrc[05] == 1'b1) ? ery_src05 : captured_src05;
    captured_src04 <= (ery_loadsrc[04] == 1'b1) ? ery_src04 : captured_src04;
    captured_src03 <= (ery_loadsrc[03] == 1'b1) ? ery_src03 : captured_src03;
    captured_src02 <= (ery_loadsrc[02] == 1'b1) ? ery_src02 : captured_src02;
    captured_src01 <= (ery_loadsrc[01] == 1'b1) ? ery_src01 : captured_src01;
    captured_src00 <= (ery_loadsrc[00] == 1'b1) ? ery_src00 : captured_src00;
    captured_loadsrc <= ery_loadsrc;
  end


wire [127:0] selected_src;
assign selected_src = ( {128{captured_loadsrc[15]}} & captured_src15 ) |
                      ( {128{captured_loadsrc[14]}} & captured_src14 ) |




                      ( {128{captured_loadsrc[09]}} & captured_src09 ) |
                      ( {128{captured_loadsrc[08]}} & captured_src08 ) |
                      ( {128{captured_loadsrc[07]}} & captured_src07 ) |
                      ( {128{captured_loadsrc[06]}} & captured_src06 ) |
                      ( {128{captured_loadsrc[05]}} & captured_src05 ) |
                      ( {128{captured_loadsrc[04]}} & captured_src04 ) |
                      ( {128{captured_loadsrc[03]}} & captured_src03 ) |
                      ( {128{captured_loadsrc[02]}} & captured_src02 ) |
                      ( {128{captured_loadsrc[01]}} & captured_src01 ) |
                      ( {128{captured_loadsrc[00]}} & captured_src00 ) ;
wire combined_loadsrc;
assign combined_loadsrc = (| captured_loadsrc);


wire [3:0] loadsrc_1count;
assign loadsrc_1count = {3'b0,captured_loadsrc[15]} + {3'b0,captured_loadsrc[14]} + {3'b0,captured_loadsrc[13]} + {3'b0,captured_loadsrc[12]} + 
                        {3'b0,captured_loadsrc[11]} + {3'b0,captured_loadsrc[10]} + {3'b0,captured_loadsrc[09]} + {3'b0,captured_loadsrc[08]} +
                        {3'b0,captured_loadsrc[07]} + {3'b0,captured_loadsrc[06]} + {3'b0,captured_loadsrc[05]} + {3'b0,captured_loadsrc[04]} +
                        {3'b0,captured_loadsrc[03]} + {3'b0,captured_loadsrc[02]} + {3'b0,captured_loadsrc[01]} + {3'b0,captured_loadsrc[00]} ;
assign ery_simultaneous_load = (loadsrc_1count > 4'b0001) ? 1'b1 : 1'b0;





reg [127:0] errary [7:0];
reg   [2:0] wrptr;
reg   [2:0] rdptr;
reg   [7:0] errary_val;

always @(posedge(clock))
  begin
    if (reset == 1'b1) 
      wrptr <= 3'b000;
    else if (combined_loadsrc == 1'b1 && wrptr != 3'b111)   
      wrptr <= wrptr + 3'b001;
    else if (combined_loadsrc == 1'b1 && wrptr == 3'b111)   
      wrptr <= 3'b000;
    else
      wrptr <= wrptr;
  end









always @(posedge(clock))
  begin
    if (reset == 1'b1)
      rdptr <= 3'b000;

    else if (ery_data_done == 1'b1 && rdptr != 3'b111)
      rdptr <= rdptr + 3'b001;

    else if (ery_data_done == 1'b1 && rdptr == 3'b111)
      rdptr <= 3'b000;
    else
      rdptr <= rdptr;
  end


always @(posedge(clock))
  begin 
    if (reset == 1'b1)
      errary_val <= 8'h0;
    else if (combined_loadsrc == 1'b1 && ery_data_done == 1'b0) 
      errary_val <= errary_val | (8'h01 << wrptr);
    else if (combined_loadsrc == 1'b0 && ery_data_done == 1'b1)
      errary_val <= errary_val & ~(8'h01 << rdptr);
    else if (combined_loadsrc == 1'b1 && ery_data_done == 1'b1)
      errary_val <= (errary_val | (8'h01 << wrptr)) & ~(8'h01 << rdptr);
    else
      errary_val <= errary_val;
  end



always @(posedge(clock))
  errary[wrptr] <= (combined_loadsrc == 1'b1) ? selected_src : errary[wrptr];


assign ery_data_valid =  errary_val[rdptr];
assign ery_data_out   = (errary_val[rdptr] == 1'b1) ? errary[rdptr] : 128'b0;


assign ery_overflow   = (combined_loadsrc == 1'b1 && errary_val == 8'hFF) ? 1'b1 : 1'b0;


assign ery_trigger_intrp = combined_loadsrc;


endmodule
module lpc_errary (
    input          clock
  , input          reset


  , input   [15:0] ery_loadsrc
  , input  [127:0] ery_src15
  , input  [127:0] ery_src14         




  , input  [127:0] ery_src09         
  , input  [127:0] ery_src08         
  , input  [127:0] ery_src07         
  , input  [127:0] ery_src06         
  , input  [127:0] ery_src05         
  , input  [127:0] ery_src04         
  , input  [127:0] ery_src03         
  , input  [127:0] ery_src02         
  , input  [127:0] ery_src01         
  , input  [127:0] ery_src00        


  , output [127:0] ery_data_out
  , output         ery_data_valid
  , input          ery_data_done


  , output         ery_simultaneous_load
  , output         ery_overflow
  , output         ery_trigger_intrp
) ;





reg  [127:0] captured_src15;
reg  [127:0] captured_src14;




reg  [127:0] captured_src09;
reg  [127:0] captured_src08;
reg  [127:0] captured_src07;
reg  [127:0] captured_src06;
reg  [127:0] captured_src05;
reg  [127:0] captured_src04;
reg  [127:0] captured_src03;
reg  [127:0] captured_src02;
reg  [127:0] captured_src01;
reg  [127:0] captured_src00;
reg   [15:0] captured_loadsrc;

always @(posedge(clock))
  begin
    captured_src15 <= (ery_loadsrc[15] == 1'b1) ? ery_src15 : captured_src15;
    captured_src14 <= (ery_loadsrc[14] == 1'b1) ? ery_src14 : captured_src14;




    captured_src09 <= (ery_loadsrc[09] == 1'b1) ? ery_src09 : captured_src09;
    captured_src08 <= (ery_loadsrc[08] == 1'b1) ? ery_src08 : captured_src08;
    captured_src07 <= (ery_loadsrc[07] == 1'b1) ? ery_src07 : captured_src07;
    captured_src06 <= (ery_loadsrc[06] == 1'b1) ? ery_src06 : captured_src06;
    captured_src05 <= (ery_loadsrc[05] == 1'b1) ? ery_src05 : captured_src05;
    captured_src04 <= (ery_loadsrc[04] == 1'b1) ? ery_src04 : captured_src04;
    captured_src03 <= (ery_loadsrc[03] == 1'b1) ? ery_src03 : captured_src03;
    captured_src02 <= (ery_loadsrc[02] == 1'b1) ? ery_src02 : captured_src02;
    captured_src01 <= (ery_loadsrc[01] == 1'b1) ? ery_src01 : captured_src01;
    captured_src00 <= (ery_loadsrc[00] == 1'b1) ? ery_src00 : captured_src00;
    captured_loadsrc <= ery_loadsrc;
  end


wire [127:0] selected_src;
assign selected_src = ( {128{captured_loadsrc[15]}} & captured_src15 ) |
                      ( {128{captured_loadsrc[14]}} & captured_src14 ) |




                      ( {128{captured_loadsrc[09]}} & captured_src09 ) |
                      ( {128{captured_loadsrc[08]}} & captured_src08 ) |
                      ( {128{captured_loadsrc[07]}} & captured_src07 ) |
                      ( {128{captured_loadsrc[06]}} & captured_src06 ) |
                      ( {128{captured_loadsrc[05]}} & captured_src05 ) |
                      ( {128{captured_loadsrc[04]}} & captured_src04 ) |
                      ( {128{captured_loadsrc[03]}} & captured_src03 ) |
                      ( {128{captured_loadsrc[02]}} & captured_src02 ) |
                      ( {128{captured_loadsrc[01]}} & captured_src01 ) |
                      ( {128{captured_loadsrc[00]}} & captured_src00 ) ;
wire combined_loadsrc;
assign combined_loadsrc = (| captured_loadsrc);


wire [3:0] loadsrc_1count;
assign loadsrc_1count = {3'b0,captured_loadsrc[15]} + {3'b0,captured_loadsrc[14]} + {3'b0,captured_loadsrc[13]} + {3'b0,captured_loadsrc[12]} + 
                        {3'b0,captured_loadsrc[11]} + {3'b0,captured_loadsrc[10]} + {3'b0,captured_loadsrc[09]} + {3'b0,captured_loadsrc[08]} +
                        {3'b0,captured_loadsrc[07]} + {3'b0,captured_loadsrc[06]} + {3'b0,captured_loadsrc[05]} + {3'b0,captured_loadsrc[04]} +
                        {3'b0,captured_loadsrc[03]} + {3'b0,captured_loadsrc[02]} + {3'b0,captured_loadsrc[01]} + {3'b0,captured_loadsrc[00]} ;
assign ery_simultaneous_load = (loadsrc_1count > 4'b0001) ? 1'b1 : 1'b0;





reg [127:0] errary [7:0];
reg   [2:0] wrptr;
reg   [2:0] rdptr;
reg   [7:0] errary_val;

always @(posedge(clock))
  begin
    if (reset == 1'b1) 
      wrptr <= 3'b000;
    else if (combined_loadsrc == 1'b1 && wrptr != 3'b111)   
      wrptr <= wrptr + 3'b001;
    else if (combined_loadsrc == 1'b1 && wrptr == 3'b111)   
      wrptr <= 3'b000;
    else
      wrptr <= wrptr;
  end









always @(posedge(clock))
  begin
    if (reset == 1'b1)
      rdptr <= 3'b000;

    else if (ery_data_done == 1'b1 && rdptr != 3'b111)
      rdptr <= rdptr + 3'b001;

    else if (ery_data_done == 1'b1 && rdptr == 3'b111)
      rdptr <= 3'b000;
    else
      rdptr <= rdptr;
  end


always @(posedge(clock))
  begin 
    if (reset == 1'b1)
      errary_val <= 8'h0;
    else if (combined_loadsrc == 1'b1 && ery_data_done == 1'b0) 
      errary_val <= errary_val | (8'h01 << wrptr);
    else if (combined_loadsrc == 1'b0 && ery_data_done == 1'b1)
      errary_val <= errary_val & ~(8'h01 << rdptr);
    else if (combined_loadsrc == 1'b1 && ery_data_done == 1'b1)
      errary_val <= (errary_val | (8'h01 << wrptr)) & ~(8'h01 << rdptr);
    else
      errary_val <= errary_val;
  end



always @(posedge(clock))
  errary[wrptr] <= (combined_loadsrc == 1'b1) ? selected_src : errary[wrptr];


assign ery_data_valid =  errary_val[rdptr];
assign ery_data_out   = (errary_val[rdptr] == 1'b1) ? errary[rdptr] : 128'b0;


assign ery_overflow   = (combined_loadsrc == 1'b1 && errary_val == 8'hFF) ? 1'b1 : 1'b0;


assign ery_trigger_intrp = combined_loadsrc;


endmodule