data/full_repos/permissive/181665138/verilog/capitolo_v/Riconoscitore_di_Sequenza_Mealy.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Riconoscitore_di_Sequenza_Mealy.v:18: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(reset_ == 0) #1 STAR <= S0;\n                    ^~\n%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Riconoscitore_di_Sequenza_Mealy.v:21: syntax error, unexpected casex\n        casex(STAR)\n        ^~~~~\n%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Riconoscitore_di_Sequenza_Mealy.v:23: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n            S1: STAR <= (x1_x0 == 'B01)?S2:(x1_x0 == 'B11)?S1:S0;\n                ^~~~\n%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Riconoscitore_di_Sequenza_Mealy.v:24: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n            S2: STAR <= (x1_x0 == 'B10)?S1:S0;\n                ^~~~\n%Error: Cannot continue\n"
module Riconoscitore_di_Sequenza_Mealy();
    input       clock, reset_;
    input [1:0] x1_x0;
    output      z;

    reg [1:0]   STAR;
    parameter S0 = 'B00, S1 = 'B01, S2 = 'B10;

    assign z = ((STAR==S2) & (x1_x0 == 'B10))?1:0;

    always @(reset_ == 0) #1 STAR <= S0;

    always @(posedge clock) if (reset_ == 1) 33
        casex(STAR)
            S0: STAR <= (x1_x0 == 'B11)?S1:S0;
            S1: STAR <= (x1_x0 == 'B01)?S2:(x1_x0 == 'B11)?S1:S0;
            S2: STAR <= (x1_x0 == 'B10)?S1:S0;
        endcase

endmodule
module Riconoscitore_di_Sequenza_Mealy();

    input       clock, reset_;
    input [1:0] x1_x0;
    output      z;

    reg [1:0]   STAR;
    parameter S0 = 'B00, S1 = 'B01, S2 = 'B10;

    assign z = ((STAR==S2) & (x1_x0 == 'B10))?1:0;

    always @(reset_ == 0) #1 STAR <= S0;

    always @(posedge clock) if (reset_ == 1) 33
        casex(STAR)
            S0: STAR <= (x1_x0 == 'B11)?S1:S0;
            S1: STAR <= (x1_x0 == 'B01)?S2:(x1_x0 == 'B11)?S1:S0;
            S2: STAR <= (x1_x0 == 'B10)?S1:S0;
        endcase

endmodule