data/full_repos/permissive/13953309/NW_vc_free_pool.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/13953309/NW_vc_free_pool.v:35: syntax error, unexpected IDENTIFIER, expecting ';'\n   input flit_t flit;\n                ^~~~\n%Error: data/full_repos/permissive/13953309/NW_vc_free_pool.v:37: syntax error, unexpected IDENTIFIER, expecting ';'\n   output vc_t oh_free_vc;\n               ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module NW_vc_free_pool (flit, valid,

			oh_free_vc, no_free_vc,
			vc_consumed,

			vc_alloc_status,
			vc_allocated,
			vc_empty,
			clk, rst_n);

   parameter num_vcs_global = 4;
   parameter num_vcs_local  = 4;
   
   parameter fifo_free_pool = 0;


   parameter only_allocate_vc_when_empty = 0;
   

   input flit_t flit;
   input valid;
   output vc_t oh_free_vc;
   output no_free_vc;
   input  vc_consumed;
   input [num_vcs_global-1:0] vc_allocated;
   output [num_vcs_global-1:0] vc_alloc_status;
   input [num_vcs_global-1:0]  vc_empty;
   input  clk, rst_n;

   logic [num_vcs_global-1:0] vc_alloc_status_reg;
   vc_t fifo_out;
   fifov_flags_t fifo_flags;
   logic push;

   integer i;
   
   generate




      if (fifo_free_pool) begin
	 



	 NW_fifo_v #(.init_fifo_contents(1),

		     .size(num_vcs_local+1),
		     .input_reg(0), 
		     .output_reg(num_vcs_local>2))

	   free_vc_fifo (.push(push),
			 .pop(vc_consumed), 
			 .data_in(flit.control.vc_id), 
			 .data_out(fifo_out),
			 .flags(fifo_flags),
			 .clk, .rst_n);
	    
	 if (num_vcs_local>2) begin
	    assign oh_free_vc = fifo_out;
	 end else begin
	    assign oh_free_vc = fifo_out & {(num_vcs_local){!fifo_flags.empty}};
	 end
	 
	 assign push = valid && flit.control.tail;
	 
	 assign no_free_vc = fifo_flags.fast_empty;
	 
	 always@(posedge clk) begin


	    

	    if (push && fifo_flags.full && !vc_consumed) begin
	       $display ("%d: %m: Error free VC fifo full, push and !pop ....", $time);
	       $display ("flit.vc_id  = %b", flit.control.vc_id);
	       $display ("flit.tail   = %b", flit.control.tail);
	       $display ("vc_consumed = %b", vc_consumed);
	       $finish;
	    end

	 end
      end else begin




	 always@(posedge clk) begin
	    if (!rst_n) begin
	       for (i=0; i<num_vcs_global; i++) begin:forvcs2
		  vc_alloc_status_reg[i] <= (i<num_vcs_local);
	       end
	    end else begin
	       for (i=0; i<num_vcs_global; i++) begin:forvcs



		  if (vc_allocated[i]) vc_alloc_status_reg[i]<=1'b0;
	       end
	       if (valid && flit.control.tail) begin





		  assert (!vc_alloc_status_reg[oh2bin(flit.control.vc_id)]);
		  
		  vc_alloc_status_reg[oh2bin(flit.control.vc_id)]<=1'b1;
	       end
	    end
	 end

	 if (only_allocate_vc_when_empty) begin
	    assign vc_alloc_status = vc_alloc_status_reg & vc_empty;
	 end else begin
	    assign vc_alloc_status = vc_alloc_status_reg;
	 end
      end
   endgenerate
   
endmodule
module NW_vc_free_pool (flit, valid,

			oh_free_vc, no_free_vc,
			vc_consumed,

			vc_alloc_status,
			vc_allocated,
			vc_empty,
			clk, rst_n);


   parameter num_vcs_global = 4;
   parameter num_vcs_local  = 4;
   
   parameter fifo_free_pool = 0;


   parameter only_allocate_vc_when_empty = 0;
   

   input flit_t flit;
   input valid;
   output vc_t oh_free_vc;
   output no_free_vc;
   input  vc_consumed;
   input [num_vcs_global-1:0] vc_allocated;
   output [num_vcs_global-1:0] vc_alloc_status;
   input [num_vcs_global-1:0]  vc_empty;
   input  clk, rst_n;

   logic [num_vcs_global-1:0] vc_alloc_status_reg;
   vc_t fifo_out;
   fifov_flags_t fifo_flags;
   logic push;

   integer i;
   
   generate




      if (fifo_free_pool) begin
	 



	 NW_fifo_v #(.init_fifo_contents(1),

		     .size(num_vcs_local+1),
		     .input_reg(0), 
		     .output_reg(num_vcs_local>2))

	   free_vc_fifo (.push(push),
			 .pop(vc_consumed), 
			 .data_in(flit.control.vc_id), 
			 .data_out(fifo_out),
			 .flags(fifo_flags),
			 .clk, .rst_n);
	    
	 if (num_vcs_local>2) begin
	    assign oh_free_vc = fifo_out;
	 end else begin
	    assign oh_free_vc = fifo_out & {(num_vcs_local){!fifo_flags.empty}};
	 end
	 
	 assign push = valid && flit.control.tail;
	 
	 assign no_free_vc = fifo_flags.fast_empty;
	 
	 always@(posedge clk) begin


	    

	    if (push && fifo_flags.full && !vc_consumed) begin
	       $display ("%d: %m: Error free VC fifo full, push and !pop ....", $time);
	       $display ("flit.vc_id  = %b", flit.control.vc_id);
	       $display ("flit.tail   = %b", flit.control.tail);
	       $display ("vc_consumed = %b", vc_consumed);
	       $finish;
	    end

	 end
      end else begin




	 always@(posedge clk) begin
	    if (!rst_n) begin
	       for (i=0; i<num_vcs_global; i++) begin:forvcs2
		  vc_alloc_status_reg[i] <= (i<num_vcs_local);
	       end
	    end else begin
	       for (i=0; i<num_vcs_global; i++) begin:forvcs



		  if (vc_allocated[i]) vc_alloc_status_reg[i]<=1'b0;
	       end
	       if (valid && flit.control.tail) begin





		  assert (!vc_alloc_status_reg[oh2bin(flit.control.vc_id)]);
		  
		  vc_alloc_status_reg[oh2bin(flit.control.vc_id)]<=1'b1;
	       end
	    end
	 end

	 if (only_allocate_vc_when_empty) begin
	    assign vc_alloc_status = vc_alloc_status_reg & vc_empty;
	 end else begin
	    assign vc_alloc_status = vc_alloc_status_reg;
	 end
      end
   endgenerate
   
endmodule