data/full_repos/permissive/181665138/verilog/capitolo_ii/Multiplexer_4_to_1.v
data/verilator_xmls/94194177-0517-4e89-9cb6-9c851e2f1bd9.xml
module Multiplexer_4_to_1(x3, x2, x1, x0, b1, b0, z);
    input x3, x2, x1, x0, b1, b0;
    output z;

    assign z = ({b1, b0}=='B11)?x3:
               ({b1, b0}=='B10)?x2:
               ({b1, b0}=='B01)?x1:
x0;
endmodule
module Multiplexer_4_to_1(x3, x2, x1, x0, b1, b0, z);

    input x3, x2, x1, x0, b1, b0;
    output z;

    assign z = ({b1, b0}=='B11)?x3:
               ({b1, b0}=='B10)?x2:
               ({b1, b0}=='B01)?x1:
x0;
endmodule