data/full_repos/permissive/184916587/Regfile.v
1: b"%Error: data/full_repos/permissive/184916587/Regfile.v:18: Duplicate declaration of signal: 'data_1'\n                                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg[31:0] data_1,data_2;\n           ^~~~~~\n        data/full_repos/permissive/184916587/Regfile.v:13: ... Location of original declaration\n output[31:0] data_1,  \n              ^~~~~~\n%Error: data/full_repos/permissive/184916587/Regfile.v:18: Duplicate declaration of signal: 'data_2'\n reg[31:0] data_1,data_2;\n                  ^~~~~~\n        data/full_repos/permissive/184916587/Regfile.v:14: ... Location of original declaration\n output[31:0] data_2\n              ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Regfile(
	input _Reset,
	input State,
	input[4:0] address_1,
	input[4:0] address_2,
	input[31:0] data_w,
	output[31:0] data_1,
	output[31:0] data_2
);

	reg[31:0] register[31:0];
	reg[31:0] data_1,data_2;










	initial
		begin
			register[0]=0;
		end


	initial
		begin
			register[1]=32'b00000000001000001110010010110011;
			register[2]=32'b00000000000100010000000110110011;
			register[7]=32'b00000000001010111101101010111111;
			register[12]=32'b00000000000000000111111010101011;
		end


	always @(*)
	begin
		if(State===1)
			data_1=register[address_1];
			data_2=register[address_2];
	end

	always @(*)
	begin

		if(State===0&&address_1!=0)
			register[address_1]=data_w;
	end
endmodule
module Regfile(
	input _Reset,
	input State,
	input[4:0] address_1,
	input[4:0] address_2,
	input[31:0] data_w,
	output[31:0] data_1,
	output[31:0] data_2
);


	reg[31:0] register[31:0];
	reg[31:0] data_1,data_2;










	initial
		begin
			register[0]=0;
		end


	initial
		begin
			register[1]=32'b00000000001000001110010010110011;
			register[2]=32'b00000000000100010000000110110011;
			register[7]=32'b00000000001010111101101010111111;
			register[12]=32'b00000000000000000111111010101011;
		end


	always @(*)
	begin
		if(State===1)
			data_1=register[address_1];
			data_2=register[address_2];
	end

	always @(*)
	begin

		if(State===0&&address_1!=0)
			register[address_1]=data_w;
	end
endmodule