data/full_repos/permissive/129155059/proyecto-01/includes/s2p_reg_cond.v
None: at end of input
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/includes/s2p_reg_cond.v:1: Cannot find include file: definitions.v\n`include "definitions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/includes,data/full_repos/permissive/129155059/definitions.v\n             data/full_repos/permissive/129155059/proyecto-01/includes,data/full_repos/permissive/129155059/definitions.v.v\n             data/full_repos/permissive/129155059/proyecto-01/includes,data/full_repos/permissive/129155059/definitions.v.sv\n             definitions.v\n             definitions.v.v\n             definitions.v.sv\n             obj_dir/definitions.v\n             obj_dir/definitions.v.v\n             obj_dir/definitions.v.sv\n%Error: data/full_repos/permissive/129155059/proyecto-01/includes/s2p_reg_cond.v:16: Define or directive not defined: \'`PUSH\'\n      `PUSH:\n      ^~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/includes/s2p_reg_cond.v:16: syntax error, unexpected \':\', expecting endcase\n      `PUSH:\n           ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/includes/s2p_reg_cond.v:21: syntax error, unexpected else\n        end else begin\n            ^~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/includes/s2p_reg_cond.v:25: syntax error, unexpected end\n      end\n      ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/includes/s2p_reg_cond.v:27: Define or directive not defined: \'`CYCLE\'\n      `CYCLE:\n      ^~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/includes/s2p_reg_cond.v:38: Define or directive not defined: \'`LOAD\'\n      `LOAD:\n      ^~~~~\n%Error: Cannot continue\n'
module s2p_reg_cond ( input   wire  [7:0] D,
                      input   wire  [1:0] MODO,
                      input   wire        CLK, ENB, DIR, S_IN,
                      output  reg   [7:0] Q,
                      output  reg         S_OUT
);

always @ (posedge CLK) begin
  if (~ENB) begin
    Q <= Q;
  end else begin

    case (MODO)
      `PUSH:
      begin
        if (DIR == 0) begin
          S_OUT <= Q[7];
          Q <= {Q[6 : 0], S_IN};
        end else begin
          S_OUT <= Q[0];
          Q <= {S_IN, Q[7 : 1]};
        end
      end

      `CYCLE:
      begin
        if (DIR == 0) begin
            Q[7 : 0] <= {Q[6 : 0], Q[7]};
            S_OUT <= 0;
        end else begin
            Q[7 : 0] <= {Q[0], Q[7 : 1]};
            S_OUT <= 0;
        end
      end

      `LOAD:
      begin
        Q[7 : 0] <= D[7 : 0];
        S_OUT <= 0;
      end

      default:
      begin
        Q[7 : 0] <= D[7 : 0];
        S_OUT <= 0;
      end

    endcase

  end


end

endmodule
module s2p_reg_cond ( input   wire  [7:0] D,
                      input   wire  [1:0] MODO,
                      input   wire        CLK, ENB, DIR, S_IN,
                      output  reg   [7:0] Q,
                      output  reg         S_OUT
);


always @ (posedge CLK) begin
  if (~ENB) begin
    Q <= Q;
  end else begin

    case (MODO)
      `PUSH:
      begin
        if (DIR == 0) begin
          S_OUT <= Q[7];
          Q <= {Q[6 : 0], S_IN};
        end else begin
          S_OUT <= Q[0];
          Q <= {S_IN, Q[7 : 1]};
        end
      end

      `CYCLE:
      begin
        if (DIR == 0) begin
            Q[7 : 0] <= {Q[6 : 0], Q[7]};
            S_OUT <= 0;
        end else begin
            Q[7 : 0] <= {Q[0], Q[7 : 1]};
            S_OUT <= 0;
        end
      end

      `LOAD:
      begin
        Q[7 : 0] <= D[7 : 0];
        S_OUT <= 0;
      end

      default:
      begin
        Q[7 : 0] <= D[7 : 0];
        S_OUT <= 0;
      end

    endcase

  end


end

endmodule