data/full_repos/permissive/203526788/iVerilog/SimpleTemplate/tb.v
1: b'%Error: data/full_repos/permissive/203526788/iVerilog/SimpleTemplate/tb.v:22: Cannot find include file: dff.v\n`include "dff.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203526788/iVerilog/SimpleTemplate,data/full_repos/permissive/203526788/dff.v\n             data/full_repos/permissive/203526788/iVerilog/SimpleTemplate,data/full_repos/permissive/203526788/dff.v.v\n             data/full_repos/permissive/203526788/iVerilog/SimpleTemplate,data/full_repos/permissive/203526788/dff.v.sv\n             dff.v\n             dff.v.v\n             dff.v.sv\n             obj_dir/dff.v\n             obj_dir/dff.v.v\n             obj_dir/dff.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/203526788/iVerilog/SimpleTemplate/tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk= ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/203526788/iVerilog/SimpleTemplate/tb.v:36: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/203526788/iVerilog/SimpleTemplate/tb.v:37: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/203526788/iVerilog/SimpleTemplate/tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203526788/iVerilog/SimpleTemplate/tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203526788/iVerilog/SimpleTemplate/tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203526788/iVerilog/SimpleTemplate/tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #5 $finish;\n        ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module tb;
            
    reg in; 
    reg clk;
    wire out;


    always #1 clk= ~clk;


    initial 
    begin
        $dumpfile("tb.vcd");
        $dumpvars(0, tb);

        clk = 0;
        in=0;
        #5
        in=1;
        #5
        in=0;
        #5
        in=1;
        
        #5 $finish;
    end

    
    dff inst (.clk(clk), .d(in) , .q(out));

endmodule
module tb;

            
    reg in; 
    reg clk;
    wire out;


    always #1 clk= ~clk;


    initial 
    begin
        $dumpfile("tb.vcd");
        $dumpvars(0, tb);

        clk = 0;
        in=0;
        #5
        in=1;
        #5
        in=0;
        #5
        in=1;
        
        #5 $finish;
    end

    
    dff inst (.clk(clk), .d(in) , .q(out));

endmodule