data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v:33: Unsupported: Ignoring delay on this delayed statement.\n#3;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v:40: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v:42: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v:10: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                     : ... In instance Sim_digitalClock\nwire [3:0] H1_load={\'b0,SW[13:11]};\n                    ^~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v:10: Unsized numbers/parameters not allowed in replications.\n                                                                                                     : ... In instance Sim_digitalClock\nwire [3:0] H1_load={\'b0,SW[13:11]};\n                       ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v:12: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                     : ... In instance Sim_digitalClock\nwire [3:0] M1_load={\'b0,SW[6:4]};\n                    ^~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v:12: Unsized numbers/parameters not allowed in replications.\n                                                                                                     : ... In instance Sim_digitalClock\nwire [3:0] M1_load={\'b0,SW[6:4]};\n                       ^\n%Error: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v:25: Cannot find file containing module: \'_74LS163\'\n_74LS163 H1(CP_clock,~(CR|Full_H1),~LD,Full_H2,1,H1_load,H1_display);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab6_2/sources_1/new,data/full_repos/permissive/211316121/_74LS163\n             data/full_repos/permissive/211316121/lab6_2/sources_1/new,data/full_repos/permissive/211316121/_74LS163.v\n             data/full_repos/permissive/211316121/lab6_2/sources_1/new,data/full_repos/permissive/211316121/_74LS163.sv\n             _74LS163\n             _74LS163.v\n             _74LS163.sv\n             obj_dir/_74LS163\n             obj_dir/_74LS163.v\n             obj_dir/_74LS163.sv\n%Error: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v:26: Cannot find file containing module: \'_74LS163\'\n_74LS163 H2(CP_clock,~(CR|Full_H2),~LD,Full_M1,1,H2_load,H2_display);\n^~~~~~~~\n%Error: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v:27: Cannot find file containing module: \'_74LS163\'\n_74LS163 M1(CP_clock,~(CR|Full_M1),~LD,Full_M2,1,M1_load,M1_display);\n^~~~~~~~\n%Error: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Sim_digitalClock.v:28: Cannot find file containing module: \'_74LS163\'\n_74LS163 M2(CP_clock,~(CR|Full_M2),~LD,1,1,M2_load,M2_display);\n^~~~~~~~\n%Error: Exiting due to 4 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Sim_digitalClock();
reg [15:0] SW;
reg CP_clock;

wire CR=SW[15];
wire LD=SW[14];

wire [3:0] H1_load={'b0,SW[13:11]};
wire [3:0] H2_load=SW[10:7];
wire [3:0] M1_load={'b0,SW[6:4]};
wire [3:0] M2_load=SW[3:0];

wire [3:0] H1_display;
wire [3:0] H2_display;
wire [3:0] M1_display;
wire [3:0] M2_display;

wire Full_H1=H1_display[1]&H2_display[1]&H2_display[0]&Full_M1;
wire Full_H2=(H2_display[3]&H2_display[0]&Full_M1)|Full_H1;
wire Full_M1=M1_display[2]&M1_display[0]&M2_display[3]&M2_display[0];
wire Full_M2=M2_display[3]&M2_display[0];

_74LS163 H1(CP_clock,~(CR|Full_H1),~LD,Full_H2,1,H1_load,H1_display);
_74LS163 H2(CP_clock,~(CR|Full_H2),~LD,Full_M1,1,H2_load,H2_display);
_74LS163 M1(CP_clock,~(CR|Full_M1),~LD,Full_M2,1,M1_load,M1_display);
_74LS163 M2(CP_clock,~(CR|Full_M2),~LD,1,1,M2_load,M2_display);

initial
begin
SW='b0100000111010011;
#3;
SW='b0000000111010011;
end

always
begin
CP_clock=0;
#1;
CP_clock=1;
#1;
end

endmodule
module Sim_digitalClock();

reg [15:0] SW;
reg CP_clock;

wire CR=SW[15];
wire LD=SW[14];

wire [3:0] H1_load={'b0,SW[13:11]};
wire [3:0] H2_load=SW[10:7];
wire [3:0] M1_load={'b0,SW[6:4]};
wire [3:0] M2_load=SW[3:0];

wire [3:0] H1_display;
wire [3:0] H2_display;
wire [3:0] M1_display;
wire [3:0] M2_display;

wire Full_H1=H1_display[1]&H2_display[1]&H2_display[0]&Full_M1;
wire Full_H2=(H2_display[3]&H2_display[0]&Full_M1)|Full_H1;
wire Full_M1=M1_display[2]&M1_display[0]&M2_display[3]&M2_display[0];
wire Full_M2=M2_display[3]&M2_display[0];

_74LS163 H1(CP_clock,~(CR|Full_H1),~LD,Full_H2,1,H1_load,H1_display);
_74LS163 H2(CP_clock,~(CR|Full_H2),~LD,Full_M1,1,H2_load,H2_display);
_74LS163 M1(CP_clock,~(CR|Full_M1),~LD,Full_M2,1,M1_load,M1_display);
_74LS163 M2(CP_clock,~(CR|Full_M2),~LD,1,1,M2_load,M2_display);

initial
begin
SW='b0100000111010011;
#3;
SW='b0000000111010011;
end

always
begin
CP_clock=0;
#1;
CP_clock=1;
#1;
end

endmodule