data/full_repos/permissive/188492004/AMS_KGD/Turbo_XAUI/netlist/mvl.v
1: b"%Error: data/full_repos/permissive/188492004/AMS_KGD/Turbo_XAUI/netlist/mvl.v:26: Cannot find file containing module: 'counter'\ncounter counter1 (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188492004/AMS_KGD/Turbo_XAUI/netlist,data/full_repos/permissive/188492004/counter\n             data/full_repos/permissive/188492004/AMS_KGD/Turbo_XAUI/netlist,data/full_repos/permissive/188492004/counter.v\n             data/full_repos/permissive/188492004/AMS_KGD/Turbo_XAUI/netlist,data/full_repos/permissive/188492004/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: data/full_repos/permissive/188492004/AMS_KGD/Turbo_XAUI/netlist/mvl.v:32: Cannot find file containing module: 'counter'\ncounter counter2 (\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mvl(
	input wire early,
	input wire late, 
	input wire clk, 
	input wire rst,
	output wire clk_cont,
	output reg [1:0] ea,
	output reg [1:0] la);

reg [2:0] s;
wire c_rst;
wire [1:0] counter_ea, counter_la;

always @ (posedge clk or posedge rst) begin
	if (rst) begin
		s <= 3'b000;
	end
	else begin
		s <= s + 3'b001;
	end
end

assign clk_cont=s[2];
assign c_rst= rst || ((s==3'b101)? 1'b1:1'b0);

counter counter1 (
	.in(early),
	.clk(clk),
	.rst(c_rst),
	.out(counter_ea));

counter counter2 (
	.in(late),
	.clk(clk),
	.rst(c_rst),
	.out(counter_la));
	
always @(posedge clk_cont or posedge rst) begin
	if (rst) begin
		ea <= 2'b00;
		la <= 2'b00;
	end else begin
		ea <= counter_ea;
		la <= counter_la;
	end
end

endmodule
module mvl(
	input wire early,
	input wire late, 
	input wire clk, 
	input wire rst,
	output wire clk_cont,
	output reg [1:0] ea,
	output reg [1:0] la);


reg [2:0] s;
wire c_rst;
wire [1:0] counter_ea, counter_la;

always @ (posedge clk or posedge rst) begin
	if (rst) begin
		s <= 3'b000;
	end
	else begin
		s <= s + 3'b001;
	end
end

assign clk_cont=s[2];
assign c_rst= rst || ((s==3'b101)? 1'b1:1'b0);

counter counter1 (
	.in(early),
	.clk(clk),
	.rst(c_rst),
	.out(counter_ea));

counter counter2 (
	.in(late),
	.clk(clk),
	.rst(c_rst),
	.out(counter_la));
	
always @(posedge clk_cont or posedge rst) begin
	if (rst) begin
		ea <= 2'b00;
		la <= 2'b00;
	end else begin
		ea <= counter_ea;
		la <= counter_la;
	end
end

endmodule