data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:28: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=0;y=0;z=1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:29: Unsupported: Ignoring delay on this delayed statement.\n            #50 enable=1;x=0;y=1;z=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:30: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=0;y=1;z=1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:31: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=1;y=0;z=0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:32: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=1;y=0;z=1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:33: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=1;y=1;z=0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:34: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=1;y=1;z=1;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:5: Little bit endian vector: MSB < LSB of bit range: 0:7\n    output [0:7] D;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:22: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0:7] D;\n         ^\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_decoder_3_to_8();
    wire [0:7] D;
    reg x,y,z,enable;
    decoder_3_to_8 G(D,x,y,z,enable);
    initial
	begin
	    enable=1;x=0;y=0;z=0;
	    #50 enable=1;x=0;y=0;z=1;
       	    #50 enable=1;x=0;y=1;z=0;
	    #50 enable=1;x=0;y=1;z=1;
	    #50 enable=1;x=1;y=0;z=0;
	    #50 enable=1;x=1;y=0;z=1;
	    #50 enable=1;x=1;y=1;z=0;
	    #50 enable=1;x=1;y=1;z=1;
	end
endmodule
module test_decoder_3_to_8();

    wire [0:7] D;
    reg x,y,z,enable;
    decoder_3_to_8 G(D,x,y,z,enable);
    initial
	begin
	    enable=1;x=0;y=0;z=0;
	    #50 enable=1;x=0;y=0;z=1;
       	    #50 enable=1;x=0;y=1;z=0;
	    #50 enable=1;x=0;y=1;z=1;
	    #50 enable=1;x=1;y=0;z=0;
	    #50 enable=1;x=1;y=0;z=1;
	    #50 enable=1;x=1;y=1;z=0;
	    #50 enable=1;x=1;y=1;z=1;
	end
endmodule