data/full_repos/permissive/159830616/YJ431_PL.srcs/sources_1/new/flexbus.v
'utf-8' codec can't decode byte 0xb5 in position 476: invalid start byte
data/verilator_xmls/e524e3d0-a6be-42ff-8273-27272586f30e.xml
module ip_flexbus(
    input FB_CLK,
    input RST_n,
    input FB_OE,
    input FB_RW,
    input FB_CS,
    input FB_ALE,




    inout [31:0] FB_AD,
    
    output [31:0] ip_ADDR,
    inout [31:0] ip_DATA,

    output ip_Read,
    output ip_Write
    );
    
reg ip_Read_reg = 1'b0;
reg ip_Write_reg = 1'b0;
reg [31:0] ip_ADDR_reg = 32'b0;
reg [31:0] FB_AD_reg = 32'b0;
reg [31:0] ip_DATA_reg = 32'b0;


        


assign ip_ADDR[31:0] = ip_ADDR_reg[31:0];    


assign FB_AD[31:0] = ( FB_RW == 1'b1 && FB_ALE == 1'b0 ) ?  FB_AD_reg[31:0] : 32'bz ;
assign ip_DATA[31:0] = ( FB_RW == 1'b1 && FB_ALE == 1'b0 ) ? 32'bz  : ip_DATA_reg[31:0];
   
   
assign ip_Read = ip_Read_reg;
assign ip_Write = ip_Write_reg;


always@( negedge FB_CLK or negedge RST_n )
    if ( !RST_n )
    { ip_Read_reg,ip_Write_reg} <= { 1'b0,1'b0 };
    
    else 
    
        begin
        if ( FB_RW == 1'b0 )
            { ip_Read_reg,ip_Write_reg } <= { 1'b0,1'b1 };
        else
            { ip_Read_reg,ip_Write_reg } <= { 1'b1,1'b0 };
       
        if ( FB_ALE == 1'b1 )
        begin 
             ip_ADDR_reg[31:0] <= FB_AD[31:0];
        end
    
        else if ( FB_CS == 1'b0 )
        begin
            if( FB_RW == 1'b1  )
            begin
                FB_AD_reg[31:0] <= ip_DATA [31:0];
            end
            else if ( FB_RW == 1'b0 )
            begin
                ip_DATA_reg[31:0] <= FB_AD[31:0];
            end
        end
    end
    
    
    
    
endmodule
module ip_flexbus(
    input FB_CLK,
    input RST_n,
    input FB_OE,
    input FB_RW,
    input FB_CS,
    input FB_ALE,




    inout [31:0] FB_AD,
    
    output [31:0] ip_ADDR,
    inout [31:0] ip_DATA,

    output ip_Read,
    output ip_Write
    );

    
reg ip_Read_reg = 1'b0;
reg ip_Write_reg = 1'b0;
reg [31:0] ip_ADDR_reg = 32'b0;
reg [31:0] FB_AD_reg = 32'b0;
reg [31:0] ip_DATA_reg = 32'b0;


        


assign ip_ADDR[31:0] = ip_ADDR_reg[31:0];    


assign FB_AD[31:0] = ( FB_RW == 1'b1 && FB_ALE == 1'b0 ) ?  FB_AD_reg[31:0] : 32'bz ;
assign ip_DATA[31:0] = ( FB_RW == 1'b1 && FB_ALE == 1'b0 ) ? 32'bz  : ip_DATA_reg[31:0];
   
   
assign ip_Read = ip_Read_reg;
assign ip_Write = ip_Write_reg;


always@( negedge FB_CLK or negedge RST_n )
    if ( !RST_n )
    { ip_Read_reg,ip_Write_reg} <= { 1'b0,1'b0 };
    
    else 
    
        begin
        if ( FB_RW == 1'b0 )
            { ip_Read_reg,ip_Write_reg } <= { 1'b0,1'b1 };
        else
            { ip_Read_reg,ip_Write_reg } <= { 1'b1,1'b0 };
       
        if ( FB_ALE == 1'b1 )
        begin 
             ip_ADDR_reg[31:0] <= FB_AD[31:0];
        end
    
        else if ( FB_CS == 1'b0 )
        begin
            if( FB_RW == 1'b1  )
            begin
                FB_AD_reg[31:0] <= ip_DATA [31:0];
            end
            else if ( FB_RW == 1'b0 )
            begin
                ip_DATA_reg[31:0] <= FB_AD[31:0];
            end
        end
    end
    
    
    
    
endmodule