data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl/bin2ascii.v
 line:25: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl/bin2ascii.v:32: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                        : ... In instance bin2ascii\n            O[8*i+7:8*i] = 8\'d48 + I[4*i+3:4*i];\n                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl/bin2ascii.v:34: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                        : ... In instance bin2ascii\n            O[8*i+7:8*i] = 8\'d55 + I[4*i+3:4*i];\n                                 ^\n%Warning-UNSIGNED: data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl/bin2ascii.v:31: Comparison is constant due to unsigned arithmetic\n                                                                                                           : ... In instance bin2ascii\n        if (I[4*i+3:4*i] >= 4\'h0 && I[4*i+3:4*i] <= 4\'h9)\n                         ^~\n%Error: Exiting due to 3 warning(s)\n'
module bin2ascii(
    input [NBYTES*8-1:0] I,
    output reg [NBYTES*16-1:0] O=0
    );
    parameter NBYTES=2;
    genvar i;
    generate for (i=0; i<NBYTES*2; i=i+1)
        always@(I)
        if (I[4*i+3:4*i] >= 4'h0 && I[4*i+3:4*i] <= 4'h9)
            O[8*i+7:8*i] = 8'd48 + I[4*i+3:4*i];
        else
            O[8*i+7:8*i] = 8'd55 + I[4*i+3:4*i];
    endgenerate
endmodule
module bin2ascii(
    input [NBYTES*8-1:0] I,
    output reg [NBYTES*16-1:0] O=0
    );

    parameter NBYTES=2;
    genvar i;
    generate for (i=0; i<NBYTES*2; i=i+1)
        always@(I)
        if (I[4*i+3:4*i] >= 4'h0 && I[4*i+3:4*i] <= 4'h9)
            O[8*i+7:8*i] = 8'd48 + I[4*i+3:4*i];
        else
            O[8*i+7:8*i] = 8'd55 + I[4*i+3:4*i];
    endgenerate
endmodule