data/full_repos/permissive/159902111/Single Cycle Processor/MIPS.v
1: b'%Error: Cannot find file containing module: Cycle\n        ... Looked in:\n             data/full_repos/permissive/159902111/Single/Cycle\n             data/full_repos/permissive/159902111/Single/Cycle.v\n             data/full_repos/permissive/159902111/Single/Cycle.sv\n             Cycle\n             Cycle.v\n             Cycle.sv\n             obj_dir/Cycle\n             obj_dir/Cycle.v\n             obj_dir/Cycle.sv\n%Error: Cannot find file containing module: Processor,data/full_repos/permissive/159902111\n%Error: Cannot find file containing module: data/full_repos/permissive/159902111/Single\n%Error: Cannot find file containing module: Processor/MIPS.v\n%Error: Exiting due to 4 error(s)\n'
module MIPS(
  input         clk,
  input         rst_n,
  output [31:0] PC_Addr,
  output [31:0] Instr,
  output [63:0] ALU_result,
  output [31:0] wa_i
  );
  wire [1:0] RegDst;
  wire       ALUSrc;
  wire [1:0] MemtoReg;
  wire       RegWrite;
  wire       MemRead;
  wire       MemWrite;
  wire       Branch;
  wire [1:0] ALUOp;
  wire       Jump;
  wire [1:0] EXTOp;
  wire       zero;
  wire [4:0] ALUOP;
  wire [31:0] new_PC, RFdata, rd1, rd2, Imm32, alu2, DMdata, Branch_Add, mux3_out, final_PC;
  PC my_PC(final_PC, clk, rst_n, PC_Addr);
  Add_PC my_Add_PC(PC_Addr, new_PC);
  IM my_IM(PC_Addr, Instr);
  Ctrl my_Ctrl({Instr[31:26]}, RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUOp, Jump, EXTOp);
  MUX #(2) my_MUX2_1({27'b0,Instr[15:11]}, {27'b0,Instr[20:16]}, 32'd31, 32'b0, RegDst, wa_i);
  RF my_RF(clk, rst_n, RegWrite, {wa_i[4:0]}, {Instr[25:21]}, {Instr[20:16]}, RFdata, rd1, rd2);
  EXT my_EXT({Instr[15:0]}, EXTOp, Imm32);
  MUX #(1) my_MUX1_1(rd2, Imm32, 32'b0, 32'b0, ALUSrc, alu2);
  ALU_ctrl my_ALU_ctrl({Instr[3:0]}, ALUOp, ALUOP);
  ALU my_ALU(ALUOP, rd1, alu2, ALU_result, zero);
  DM my_DM(clk, rst_n, {ALU_result[31:0]}, rd2, MemWrite, MemRead, DMdata);
  MUX #(2) my_MUX2_2({ALU_result[31:0]}, DMdata, {new_PC[31:28],Instr[25:0],2'b0}, 32'b0, MemtoReg, RFdata);
  Add_Branch my_Add_Branch(new_PC, {Imm32[29:0],2'b0}, Branch_Add);
  and my_and(PCSrc, Branch, zero);
  MUX #(1) my_MUX1_2(new_PC, Branch_Add, 32'b0, 32'b0, PCSrc, mux3_out);
  MUX #(1) my_MUX1_3(mux3_out, {new_PC[31:28],Instr[25:0],2'b0}, 32'b0, 32'b0, Jump, final_PC);
endmodule
module MIPS(
  input         clk,
  input         rst_n,
  output [31:0] PC_Addr,
  output [31:0] Instr,
  output [63:0] ALU_result,
  output [31:0] wa_i
  );

  wire [1:0] RegDst;
  wire       ALUSrc;
  wire [1:0] MemtoReg;
  wire       RegWrite;
  wire       MemRead;
  wire       MemWrite;
  wire       Branch;
  wire [1:0] ALUOp;
  wire       Jump;
  wire [1:0] EXTOp;
  wire       zero;
  wire [4:0] ALUOP;
  wire [31:0] new_PC, RFdata, rd1, rd2, Imm32, alu2, DMdata, Branch_Add, mux3_out, final_PC;
  PC my_PC(final_PC, clk, rst_n, PC_Addr);
  Add_PC my_Add_PC(PC_Addr, new_PC);
  IM my_IM(PC_Addr, Instr);
  Ctrl my_Ctrl({Instr[31:26]}, RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUOp, Jump, EXTOp);
  MUX #(2) my_MUX2_1({27'b0,Instr[15:11]}, {27'b0,Instr[20:16]}, 32'd31, 32'b0, RegDst, wa_i);
  RF my_RF(clk, rst_n, RegWrite, {wa_i[4:0]}, {Instr[25:21]}, {Instr[20:16]}, RFdata, rd1, rd2);
  EXT my_EXT({Instr[15:0]}, EXTOp, Imm32);
  MUX #(1) my_MUX1_1(rd2, Imm32, 32'b0, 32'b0, ALUSrc, alu2);
  ALU_ctrl my_ALU_ctrl({Instr[3:0]}, ALUOp, ALUOP);
  ALU my_ALU(ALUOP, rd1, alu2, ALU_result, zero);
  DM my_DM(clk, rst_n, {ALU_result[31:0]}, rd2, MemWrite, MemRead, DMdata);
  MUX #(2) my_MUX2_2({ALU_result[31:0]}, DMdata, {new_PC[31:28],Instr[25:0],2'b0}, 32'b0, MemtoReg, RFdata);
  Add_Branch my_Add_Branch(new_PC, {Imm32[29:0],2'b0}, Branch_Add);
  and my_and(PCSrc, Branch, zero);
  MUX #(1) my_MUX1_2(new_PC, Branch_Add, 32'b0, 32'b0, PCSrc, mux3_out);
  MUX #(1) my_MUX1_3(mux3_out, {new_PC[31:28],Instr[25:0],2'b0}, 32'b0, 32'b0, Jump, final_PC);
endmodule