data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v
data/verilator_xmls/b9c5cccd-63c5-42fe-b772-fe7e2935c84a.xml
module mac_2(a, b, c, out);
parameter DATA_WIDTH = 2;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule
module mac_2(a, b, c, out);

parameter DATA_WIDTH = 2;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule