data/full_repos/permissive/179980995/Lab1/FA_4b_Testbench.v
 line:31: before: "for"
1: b'%Warning-STMTDLY: data/full_repos/permissive/179980995/Lab1/FA_4b_Testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/179980995/Lab1/FA_4b_Testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/179980995/Lab1/FA_4b_Testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Error: data/full_repos/permissive/179980995/Lab1/FA_4b_Testbench.v:13: Cannot find file containing module: \'full_adder_4b\'\nfull_adder_4b UUT(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179980995/Lab1,data/full_repos/permissive/179980995/full_adder_4b\n             data/full_repos/permissive/179980995/Lab1,data/full_repos/permissive/179980995/full_adder_4b.v\n             data/full_repos/permissive/179980995/Lab1,data/full_repos/permissive/179980995/full_adder_4b.sv\n             full_adder_4b\n             full_adder_4b.v\n             full_adder_4b.sv\n             obj_dir/full_adder_4b\n             obj_dir/full_adder_4b.v\n             obj_dir/full_adder_4b.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FA_4b_Testbench();


reg [3:0] a;
reg [3:0] b;
reg cin;


wire [3:0] sum;
wire cout;


full_adder_4b UUT(
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);

initial begin

a = 4'b0;
b = 4'b0;
cin = 1'b0;


#10


for(cin = 0; cin<1; cin = cin + 1) begin
for(b = 0; b < 15; b = b + 1) begin
for(a = 0; a < 15; a = a + 1) begin
#10;
end
end
end


#10;
end
endmodule
module FA_4b_Testbench();



reg [3:0] a;
reg [3:0] b;
reg cin;


wire [3:0] sum;
wire cout;


full_adder_4b UUT(
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);

initial begin

a = 4'b0;
b = 4'b0;
cin = 1'b0;


#10


for(cin = 0; cin<1; cin = cin + 1) begin
for(b = 0; b < 15; b = b + 1) begin
for(a = 0; a < 15; a = a + 1) begin
#10;
end
end
end


#10;
end
endmodule