data/full_repos/permissive/199399537/uart_tx.v
'utf-8' codec can't decode byte 0xd6 in position 173: invalid continuation byte
data/verilator_xmls/58591fbd-e275-484e-8036-808033532b8c.xml
module uart_tx(
				clk,
				rst_n,
				tx_data,
				tx_start,
				clk_bps,
				rs232_tx,
				bps_start,
				fifo232_rdreq
			);

input clk;
input rst_n;
input[7:0] tx_data;
input tx_start;
input clk_bps;

output rs232_tx;
output bps_start;
output fifo232_rdreq;


reg tx_en;
reg[3:0] num;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
			begin
				tx_en <= 1'b0;
			end
			
	else if(num==4'd11) 
			tx_en <= 1'b0;
			
	else if(tx_start) 
			tx_en <= 1'b1;

assign bps_start = tx_en;


reg tx_enr1,tx_enr2;
always @(posedge clk or negedge rst_n)
	if(!rst_n) 
		begin
			tx_enr1 <= 1'b1;
			tx_enr2 <= 1'b1;
		end
	else begin
			tx_enr1 <= tx_en;
			tx_enr2 <= tx_enr1;
		end

assign fifo232_rdreq = tx_enr1 & ~tx_enr2;


reg rs232_tx_r;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		begin
			num <= 4'b0;
			rs232_tx_r <= 1'b1;
		end
		
	else if(tx_en) 
		begin
			if(clk_bps)	
				begin
					num <= num+1'b1;
					case (num)
						4'd0: rs232_tx_r <= 1'b0;
						4'd1: rs232_tx_r <= tx_data[0];
						4'd2: rs232_tx_r <= tx_data[1];
						4'd3: rs232_tx_r <= tx_data[2];
						4'd4: rs232_tx_r <= tx_data[3];
						4'd5: rs232_tx_r <= tx_data[4];
						4'd6: rs232_tx_r <= tx_data[5];
						4'd7: rs232_tx_r <= tx_data[6];
						4'd8: rs232_tx_r <= tx_data[7];
						4'd9: rs232_tx_r <= 1'b1;
					 	default: rs232_tx_r <= 1'b1;
						endcase
				end
				
			else if(num==4'd11) num <= 4'd0;
			
		end

assign rs232_tx = rs232_tx_r;



endmodule
module uart_tx(
				clk,
				rst_n,
				tx_data,
				tx_start,
				clk_bps,
				rs232_tx,
				bps_start,
				fifo232_rdreq
			);


input clk;
input rst_n;
input[7:0] tx_data;
input tx_start;
input clk_bps;

output rs232_tx;
output bps_start;
output fifo232_rdreq;


reg tx_en;
reg[3:0] num;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
			begin
				tx_en <= 1'b0;
			end
			
	else if(num==4'd11) 
			tx_en <= 1'b0;
			
	else if(tx_start) 
			tx_en <= 1'b1;

assign bps_start = tx_en;


reg tx_enr1,tx_enr2;
always @(posedge clk or negedge rst_n)
	if(!rst_n) 
		begin
			tx_enr1 <= 1'b1;
			tx_enr2 <= 1'b1;
		end
	else begin
			tx_enr1 <= tx_en;
			tx_enr2 <= tx_enr1;
		end

assign fifo232_rdreq = tx_enr1 & ~tx_enr2;


reg rs232_tx_r;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		begin
			num <= 4'b0;
			rs232_tx_r <= 1'b1;
		end
		
	else if(tx_en) 
		begin
			if(clk_bps)	
				begin
					num <= num+1'b1;
					case (num)
						4'd0: rs232_tx_r <= 1'b0;
						4'd1: rs232_tx_r <= tx_data[0];
						4'd2: rs232_tx_r <= tx_data[1];
						4'd3: rs232_tx_r <= tx_data[2];
						4'd4: rs232_tx_r <= tx_data[3];
						4'd5: rs232_tx_r <= tx_data[4];
						4'd6: rs232_tx_r <= tx_data[5];
						4'd7: rs232_tx_r <= tx_data[6];
						4'd8: rs232_tx_r <= tx_data[7];
						4'd9: rs232_tx_r <= 1'b1;
					 	default: rs232_tx_r <= 1'b1;
						endcase
				end
				
			else if(num==4'd11) num <= 4'd0;
			
		end

assign rs232_tx = rs232_tx_r;



endmodule