data/full_repos/permissive/19572582/Lab2/lab2_part3.v
data/verilator_xmls/46b57a22-2ae7-4750-8e3e-8928bb477cab.xml
module fulladder (a, b, ci, s, co);
  input a, b, ci;
  output co, s;

  wire d;

  assign d = a ^ b;
  assign s = d ^ ci;
  assign co = (b & ~d) | (d & ci);
endmodule
module fulladder (a, b, ci, s, co);

  input a, b, ci;
  output co, s;

  wire d;

  assign d = a ^ b;
  assign s = d ^ ci;
  assign co = (b & ~d) | (d & ci);
endmodule