data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v
 line:272: before: "function"
1: b'%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:49: Cannot find include file: trellis.vh\n`include "trellis.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh.v\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh.sv\n             trellis.vh\n             trellis.vh.v\n             trellis.vh.sv\n             obj_dir/trellis.vh\n             obj_dir/trellis.vh.v\n             obj_dir/trellis.vh.sv\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:50: Cannot find include file: ultrascale.vh\n`include "ultrascale.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:66: Define or directive not defined: \'`SIG_CPLID_W\'\n     input [`SIG_CPLID_W-1:0]                CONFIG_COMPLETER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:74: Define or directive not defined: \'`SIG_RQ_TUSER_W\'\n     output [`SIG_RQ_TUSER_W-1:0]            S_AXIS_RQ_TUSER,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:86: Define or directive not defined: \'`SIG_FBE_W\'\n     input [`SIG_FBE_W-1:0]                  TXR_META_FDWBE, \n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:87: Define or directive not defined: \'`SIG_LBE_W\'\n     input [`SIG_LBE_W-1:0]                  TXR_META_LDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:88: Define or directive not defined: \'`SIG_ADDR_W\'\n     input [`SIG_ADDR_W-1:0]                 TXR_META_ADDR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:89: Define or directive not defined: \'`SIG_LEN_W\'\n     input [`SIG_LEN_W-1:0]                  TXR_META_LENGTH,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:90: Define or directive not defined: \'`SIG_TAG_W\'\n     input [`SIG_TAG_W-1:0]                  TXR_META_TAG,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:91: Define or directive not defined: \'`SIG_TC_W\'\n     input [`SIG_TC_W-1:0]                   TXR_META_TC,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:92: Define or directive not defined: \'`SIG_ATTR_W\'\n     input [`SIG_ATTR_W-1:0]                 TXR_META_ATTR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:93: Define or directive not defined: \'`SIG_TYPE_W\'\n     input [`SIG_TYPE_W-1:0]                 TXR_META_TYPE,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:100: Define or directive not defined: \'`UPKT_TXR_MAXHDR_W\'\n    localparam C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W;\n                                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W;\n                                                   ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:116: Define or directive not defined: \'`SIG_NONPAY_W\'\n    wire [`SIG_NONPAY_W-1:0]                 wTxHdrNonpayLen;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:117: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n    wire [`SIG_PACKETLEN_W-1:0]              wTxHdrPacketLen;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:118: Define or directive not defined: \'`SIG_LEN_W\'\n    wire [`SIG_LEN_W-1:0]                    wTxHdrPayloadLen; \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:177: Define or directive not defined: \'`SIG_LEN_W\'\n         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:178: Define or directive not defined: \'`SIG_NONPAY_W\'\n         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:179: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:188: Define or directive not defined: \'`SIG_CPLID_W\'\n         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),\n                                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:190: Define or directive not defined: \'`SIG_FBE_W\'\n         .TXR_META_FDWBE                (TXR_META_FDWBE[`SIG_FBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:191: Define or directive not defined: \'`SIG_LBE_W\'\n         .TXR_META_LDWBE                (TXR_META_LDWBE[`SIG_LBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:192: Define or directive not defined: \'`SIG_ADDR_W\'\n         .TXR_META_ADDR                 (TXR_META_ADDR[`SIG_ADDR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:193: Define or directive not defined: \'`SIG_LEN_W\'\n         .TXR_META_LENGTH               (TXR_META_LENGTH[`SIG_LEN_W-1:0]),\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:194: Define or directive not defined: \'`SIG_TAG_W\'\n         .TXR_META_TAG                  (TXR_META_TAG[`SIG_TAG_W-1:0]),\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:195: Define or directive not defined: \'`SIG_TC_W\'\n         .TXR_META_TC                   (TXR_META_TC[`SIG_TC_W-1:0]),\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:196: Define or directive not defined: \'`SIG_ATTR_W\'\n         .TXR_META_ATTR                 (TXR_META_ATTR[`SIG_ATTR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:197: Define or directive not defined: \'`SIG_TYPE_W\'\n         .TXR_META_TYPE                 (TXR_META_TYPE[`SIG_TYPE_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:225: Define or directive not defined: \'`SIG_LEN_W\'\n         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:226: Define or directive not defined: \'`SIG_NONPAY_W\'\n         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:227: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:264: Define or directive not defined: \'`SIG_RQ_TUSER_W\'\n         .S_AXIS_RQ_TUSER               (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:278: Define or directive not defined: \'`UPKT_TXR_MAXHDR_W\'\n      parameter C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W,\n                                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:278: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      parameter C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W,\n                                                    ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:280: syntax error, unexpected parameter, expecting IDENTIFIER\n      parameter C_MAX_PACKET_DWORDS = 10\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:281: syntax error, unexpected \')\', expecting \';\'\n      )\n      ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:290: Define or directive not defined: \'`SIG_CPLID_W\'\n     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:294: Define or directive not defined: \'`SIG_FBE_W\'\n     input [`SIG_FBE_W-1:0]        TXR_META_FDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:295: Define or directive not defined: \'`SIG_LBE_W\'\n     input [`SIG_LBE_W-1:0]        TXR_META_LDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:296: Define or directive not defined: \'`SIG_ADDR_W\'\n     input [`SIG_ADDR_W-1:0]       TXR_META_ADDR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:297: Define or directive not defined: \'`SIG_LEN_W\'\n     input [`SIG_LEN_W-1:0]        TXR_META_LENGTH,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:298: Define or directive not defined: \'`SIG_TAG_W\'\n     input [`SIG_TAG_W-1:0]        TXR_META_TAG,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:299: Define or directive not defined: \'`SIG_TC_W\'\n     input [`SIG_TC_W-1:0]         TXR_META_TC,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:300: Define or directive not defined: \'`SIG_ATTR_W\'\n     input [`SIG_ATTR_W-1:0]       TXR_META_ATTR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:301: Define or directive not defined: \'`SIG_TYPE_W\'\n     input [`SIG_TYPE_W-1:0]       TXR_META_TYPE,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:308: Define or directive not defined: \'`SIG_LEN_W\'\n     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:309: Define or directive not defined: \'`SIG_NONPAY_W\'\n     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:310: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n     output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:316: Define or directive not defined: \'`UPKT_TXR_MAXHDR_W\'\n    wire [`UPKT_TXR_MAXHDR_W-1:0]  wHdr;\n          ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module txr_translation_layer
    #(parameter C_PCI_DATA_WIDTH = 10'd128,
      parameter C_PIPELINE_INPUT = 1,
      parameter C_RST_COUNT = 1)
    (
     input                                   CLK,


     input                                   RST_BUS,
     input                                   RST_LOGIC,
     output                                  RST_OUT,
     output                                  DONE_RST,


     output                                  TXR_PKT_READY,
     input [C_PCI_DATA_WIDTH-1:0]            TXR_PKT,
     input                                   TXR_PKT_VALID,
     input                                   TXR_PKT_START_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_PKT_START_OFFSET,
     input                                   TXR_PKT_END_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_PKT_END_OFFSET,


     input                                   S_AXIS_RQ_TREADY,
     output                                  S_AXIS_RQ_TVALID,
     output                                  S_AXIS_RQ_TLAST,
     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_RQ_TDATA,
     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_RQ_TKEEP,
     output [`SIG_RQ_TUSER_W-1:0]            S_AXIS_RQ_TUSER);

    localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
    localparam C_OUTPUT_STAGES = 1;
    
    wire                                     wTxrPktReady;
    wire [C_PCI_DATA_WIDTH-1:0]              wTxrPkt;
    wire                                     wTxrPktValid;
    wire                                     wTxrPktStartFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktStartOffset;
    wire                                     wTxrPktEndFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktEndOffset;

    wire                                     wSAxisRqTReady;
    wire                                     wSAxisRqTValid;
    wire                                     wSAxisRqTLast;
    wire [C_PCI_DATA_WIDTH-1:0]              wSAxisRqTData;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wSAxisRqTKeep;
    wire [`SIG_RQ_TUSER_W-1:0]               wSAxisRqTUser;

    wire                                     _wSAxisRqTReady;
    wire                                     _wSAxisRqTValid;
    wire                                     _wSAxisRqTLast;
    wire [C_PCI_DATA_WIDTH-1:0]              _wSAxisRqTData;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         _wSAxisRqTKeep;

    wire                                     wRst;
    wire                                     wRstWaiting;


    assign wTxrPktReady = _wSAxisRqTReady;
    assign _wSAxisRqTValid = wTxrPktValid;
    assign _wSAxisRqTLast = wTxrPktEndFlag;
    assign _wSAxisRqTData = wTxrPkt;


    assign wSAxisRqTUser[3:0] = wTxrPkt[(`UPKT_TXR_FBE_I % C_PCI_DATA_WIDTH) +: `UPKT_TXR_FBE_W];
    assign wSAxisRqTUser[7:4] = wTxrPkt[(`UPKT_TXR_LBE_I % C_PCI_DATA_WIDTH) +: `UPKT_TXR_LBE_W];
    assign wSAxisRqTUser[`SIG_RQ_TUSER_W-1:8] = 0;
    assign RST_OUT = wRst;

    reset_controller
        #(

          .C_RST_COUNT                  (C_RST_COUNT))
    rc
        (
         .RST_OUT                       (wRst),
         .WAITING_RESET                 (wRstWaiting),

         .RST_IN                        (RST_BUS),
         .SIGNAL_RST                    (RST_LOGIC),
         .WAIT_RST                      (S_AXIS_RQ_TVALID),
         .NEXT_CYC_RST                  (S_AXIS_RQ_TREADY & S_AXIS_RQ_TLAST),


         .DONE_RST                      (DONE_RST),

         .CLK                           (CLK));

    
    pipeline
        #(
          .C_DEPTH                      (C_INPUT_STAGES),
          .C_WIDTH                      (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
          .C_USE_MEMORY                 (0)
)
    input_inst
        (

         .WR_DATA_READY                 (TXR_PKT_READY),
         .RD_DATA                       ({wTxrPkt,wTxrPktStartFlag,wTxrPktStartOffset,wTxrPktEndFlag,wTxrPktEndOffset}),
         .RD_DATA_VALID                 (wTxrPktValid),

         .WR_DATA                       ({TXR_PKT,TXR_PKT_START_FLAG,TXR_PKT_START_OFFSET,
                                           TXR_PKT_END_FLAG,TXR_PKT_END_OFFSET}),
         .WR_DATA_VALID                 (TXR_PKT_VALID),
         .RD_DATA_READY                 (wTxrPktReady),
         .RST_IN                        (wRst),


         .CLK                           (CLK));


    offset_to_mask
        #(

          .C_MASK_SWAP                  (0),
          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
)
    otom_inst
        (

         .MASK                          (_wSAxisRqTKeep),

         .OFFSET_ENABLE                 (wTxrPktEndFlag),
         .OFFSET                        (wTxrPktEndOffset)
);
    

    pipeline
        #(

          .C_DEPTH                      (64/C_PCI_DATA_WIDTH),
          .C_WIDTH                      (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
          .C_USE_MEMORY                 (0)
)
    fbe_hack_inst
        (

         .WR_DATA_READY                 (_wSAxisRqTReady),
         .RD_DATA                       ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep}),
         .RD_DATA_VALID                 (wSAxisRqTValid),

         .WR_DATA                       ({_wSAxisRqTData,_wSAxisRqTLast,_wSAxisRqTKeep}),
         .WR_DATA_VALID                 (_wSAxisRqTValid),
         .RD_DATA_READY                 (wSAxisRqTReady),
         .RST_IN                        (wRst),


         .CLK                           (CLK));

    pipeline
        #(

          .C_DEPTH                      (C_OUTPUT_STAGES),
          .C_WIDTH                      (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32) + `SIG_RQ_TUSER_W),
          .C_USE_MEMORY                 (0)
)
    output_inst
        (

         .WR_DATA_READY                 (wSAxisRqTReady),
         .RD_DATA                       ({S_AXIS_RQ_TDATA,S_AXIS_RQ_TLAST,S_AXIS_RQ_TKEEP,S_AXIS_RQ_TUSER}),
         .RD_DATA_VALID                 (S_AXIS_RQ_TVALID),

         .WR_DATA                       ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep,wSAxisRqTUser}),
         .WR_DATA_VALID                 (wSAxisRqTValid & ~wRstWaiting),
         .RD_DATA_READY                 (S_AXIS_RQ_TREADY),
         .RST_IN                        (wRst),


         .CLK                           (CLK));

endmodule
module txr_translation_layer
    #(parameter C_PCI_DATA_WIDTH = 10'd128,
      parameter C_PIPELINE_INPUT = 1,
      parameter C_RST_COUNT = 1)
    (
     input                                   CLK,


     input                                   RST_BUS,
     input                                   RST_LOGIC,
     output                                  RST_OUT,
     output                                  DONE_RST,


     output                                  TXR_PKT_READY,
     input [C_PCI_DATA_WIDTH-1:0]            TXR_PKT,
     input                                   TXR_PKT_VALID,
     input                                   TXR_PKT_START_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_PKT_START_OFFSET,
     input                                   TXR_PKT_END_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_PKT_END_OFFSET,


     input                                   S_AXIS_RQ_TREADY,
     output                                  S_AXIS_RQ_TVALID,
     output                                  S_AXIS_RQ_TLAST,
     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_RQ_TDATA,
     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_RQ_TKEEP,
     output [`SIG_RQ_TUSER_W-1:0]            S_AXIS_RQ_TUSER);


    localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
    localparam C_OUTPUT_STAGES = 1;
    
    wire                                     wTxrPktReady;
    wire [C_PCI_DATA_WIDTH-1:0]              wTxrPkt;
    wire                                     wTxrPktValid;
    wire                                     wTxrPktStartFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktStartOffset;
    wire                                     wTxrPktEndFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktEndOffset;

    wire                                     wSAxisRqTReady;
    wire                                     wSAxisRqTValid;
    wire                                     wSAxisRqTLast;
    wire [C_PCI_DATA_WIDTH-1:0]              wSAxisRqTData;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wSAxisRqTKeep;
    wire [`SIG_RQ_TUSER_W-1:0]               wSAxisRqTUser;

    wire                                     _wSAxisRqTReady;
    wire                                     _wSAxisRqTValid;
    wire                                     _wSAxisRqTLast;
    wire [C_PCI_DATA_WIDTH-1:0]              _wSAxisRqTData;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         _wSAxisRqTKeep;

    wire                                     wRst;
    wire                                     wRstWaiting;


    assign wTxrPktReady = _wSAxisRqTReady;
    assign _wSAxisRqTValid = wTxrPktValid;
    assign _wSAxisRqTLast = wTxrPktEndFlag;
    assign _wSAxisRqTData = wTxrPkt;


    assign wSAxisRqTUser[3:0] = wTxrPkt[(`UPKT_TXR_FBE_I % C_PCI_DATA_WIDTH) +: `UPKT_TXR_FBE_W];
    assign wSAxisRqTUser[7:4] = wTxrPkt[(`UPKT_TXR_LBE_I % C_PCI_DATA_WIDTH) +: `UPKT_TXR_LBE_W];
    assign wSAxisRqTUser[`SIG_RQ_TUSER_W-1:8] = 0;
    assign RST_OUT = wRst;

    reset_controller
        #(

          .C_RST_COUNT                  (C_RST_COUNT))
    rc
        (
         .RST_OUT                       (wRst),
         .WAITING_RESET                 (wRstWaiting),

         .RST_IN                        (RST_BUS),
         .SIGNAL_RST                    (RST_LOGIC),
         .WAIT_RST                      (S_AXIS_RQ_TVALID),
         .NEXT_CYC_RST                  (S_AXIS_RQ_TREADY & S_AXIS_RQ_TLAST),


         .DONE_RST                      (DONE_RST),

         .CLK                           (CLK));

    
    pipeline
        #(
          .C_DEPTH                      (C_INPUT_STAGES),
          .C_WIDTH                      (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
          .C_USE_MEMORY                 (0)
)
    input_inst
        (

         .WR_DATA_READY                 (TXR_PKT_READY),
         .RD_DATA                       ({wTxrPkt,wTxrPktStartFlag,wTxrPktStartOffset,wTxrPktEndFlag,wTxrPktEndOffset}),
         .RD_DATA_VALID                 (wTxrPktValid),

         .WR_DATA                       ({TXR_PKT,TXR_PKT_START_FLAG,TXR_PKT_START_OFFSET,
                                           TXR_PKT_END_FLAG,TXR_PKT_END_OFFSET}),
         .WR_DATA_VALID                 (TXR_PKT_VALID),
         .RD_DATA_READY                 (wTxrPktReady),
         .RST_IN                        (wRst),


         .CLK                           (CLK));


    offset_to_mask
        #(

          .C_MASK_SWAP                  (0),
          .C_MASK_WIDTH                 (C_PCI_DATA_WIDTH/32)
)
    otom_inst
        (

         .MASK                          (_wSAxisRqTKeep),

         .OFFSET_ENABLE                 (wTxrPktEndFlag),
         .OFFSET                        (wTxrPktEndOffset)
);
    

    pipeline
        #(

          .C_DEPTH                      (64/C_PCI_DATA_WIDTH),
          .C_WIDTH                      (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
          .C_USE_MEMORY                 (0)
)
    fbe_hack_inst
        (

         .WR_DATA_READY                 (_wSAxisRqTReady),
         .RD_DATA                       ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep}),
         .RD_DATA_VALID                 (wSAxisRqTValid),

         .WR_DATA                       ({_wSAxisRqTData,_wSAxisRqTLast,_wSAxisRqTKeep}),
         .WR_DATA_VALID                 (_wSAxisRqTValid),
         .RD_DATA_READY                 (wSAxisRqTReady),
         .RST_IN                        (wRst),


         .CLK                           (CLK));

    pipeline
        #(

          .C_DEPTH                      (C_OUTPUT_STAGES),
          .C_WIDTH                      (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32) + `SIG_RQ_TUSER_W),
          .C_USE_MEMORY                 (0)
)
    output_inst
        (

         .WR_DATA_READY                 (wSAxisRqTReady),
         .RD_DATA                       ({S_AXIS_RQ_TDATA,S_AXIS_RQ_TLAST,S_AXIS_RQ_TKEEP,S_AXIS_RQ_TUSER}),
         .RD_DATA_VALID                 (S_AXIS_RQ_TVALID),

         .WR_DATA                       ({wSAxisRqTData,wSAxisRqTLast,wSAxisRqTKeep,wSAxisRqTUser}),
         .WR_DATA_VALID                 (wSAxisRqTValid & ~wRstWaiting),
         .RD_DATA_READY                 (S_AXIS_RQ_TREADY),
         .RST_IN                        (wRst),


         .CLK                           (CLK));

endmodule