data/full_repos/permissive/157922101/src/rtl/hmac.v
1: b"%Error: data/full_repos/permissive/157922101/src/rtl/hmac.v:226: Can't find definition of variable: 'ADDR_KEY7'\n                                                               : ... Suggested alternative: 'ADDR_KEY0'\n              if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))\n                                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/157922101/src/rtl/hmac.v:235: Can't find definition of variable: 'ADDR_TAG3'\n                                                               : ... Suggested alternative: 'ADDR_TAG0'\n              if ((address >= ADDR_TAG0) && (address <= ADDR_TAG3))\n                                                        ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module hmac(

            input wire           clk,
            input wire           reset_n,


            input wire           cs,
            input wire           we,


            input wire  [7 : 0]  address,
            input wire  [31 : 0] write_data,
            output wire [31 : 0] read_data
           );




  localparam ADDR_NAME0       = 8'h00;
  localparam ADDR_NAME1       = 8'h01;
  localparam ADDR_VERSION     = 8'h02;

  localparam ADDR_CTRL        = 8'h08;
  localparam CTRL_INIT_BIT    = 0;
  localparam CTRL_NEXT_BIT    = 1;
  localparam CTRL_FINAL_BIT   = 2;

  localparam ADDR_STATUS      = 8'h09;
  localparam STATUS_READY_BIT = 0;

  localparam ADDR_FINAL_LEN   = 8'h0a;

  localparam ADDR_BLOCK0      = 8'h10;
  localparam ADDR_BLOCK15     = 8'h1f;

  localparam ADDR_KEY0        = 8'h20;
  localparam ADDR_KEY15       = 8'h2f;

  localparam ADDR_TAG0        = 8'h40;
  localparam ADDR_TAG7        = 8'h47;

  localparam CORE_NAME0       = 32'h73686132;
  localparam CORE_NAME1       = 32'h2d323536;
  localparam CORE_VERSION     = 32'h312e3830;





  reg init_reg;
  reg init_new;

  reg next_reg;
  reg next_new;

  reg finalize_reg;
  reg finalize_new;

  reg [5 : 0] final_len_reg;
  reg         final_len_we;

  reg [31 : 0] key_reg [0 : 15];
  reg          key_we;

  reg [31 : 0] block_reg [0 : 15];
  reg          block_we;





  wire [255 : 0] core_key;
  wire [511 : 0] core_block;
  wire           core_ready;
  wire [127 : 0] core_tag;

  reg [31 : 0]   tmp_read_data;





  assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
                       block_reg[04], block_reg[05], block_reg[06], block_reg[07],
                       block_reg[08], block_reg[09], block_reg[10], block_reg[11],
                       block_reg[12], block_reg[13], block_reg[14], block_reg[15]};

  assign core_key = {key_reg[00], key_reg[01], key_reg[02], key_reg[03],
                     key_reg[04], key_reg[05], key_reg[06], key_reg[07]};

  assign read_data = tmp_read_data;





  hmac_core core(
                 .clk(clk),
                 .reset_n(reset_n),

                 .init(init_reg),
                 .next(next_reg),
                 .finalize(finalize_reg),
                 .final_len(final_len_reg),

                 .key(core_key),

                 .block(core_block),

                 .ready(core_ready),
                 .tag(core_tag)
                );









  always @ (posedge clk or negedge reset_n)
    begin : reg_update
      integer i;

      if (!reset_n)
        begin
          for (i = 0 ; i < 16 ; i = i + 1)
            block_reg[i] <= 32'h0;

          for (i = 0 ; i < 8 ; i = i + 1)
            key_reg[i] <= 32'h0;

          init_reg      <= 1'h0;
          next_reg      <= 1'h0;
          finalize_reg  <= 1'h0;
          final_len_reg <= 6'h0;
        end
      else
        begin
          init_reg     <= init_new;
          next_reg     <= next_new;
          finalize_reg <= finalize_new;

          if (final_len_we)
            final_len_reg <= write_data[5 : 0];

          if (key_we)
            key_reg[address[3 : 0]] <= write_data;

          if (block_we)
            block_reg[address[3 : 0]] <= write_data;
        end
    end








  always @*
    begin : api_logic
      init_new      = 0;
      next_new      = 0;
      finalize_new  = 0;
      final_len_we  = 0;
      key_we        = 0;
      block_we      = 0;
      tmp_read_data = 32'h0;

      if (cs)
        begin
          if (we)
            begin
              if (address == ADDR_CTRL)
                begin
                  init_new     = write_data[CTRL_INIT_BIT];
                  next_new     = write_data[CTRL_NEXT_BIT];
                  finalize_new = write_data[CTRL_FINAL_BIT];
                end

              if (address == ADDR_FINAL_LEN)
                final_len_we = 1;

              if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
                block_we = 1;

              if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
                block_we = 1;
            end

          else
            begin
              if ((address >= ADDR_TAG0) && (address <= ADDR_TAG3))
                tmp_read_data = core_tag[(3 - (address - ADDR_TAG0)) * 32 +: 32];

              case (address)

                ADDR_NAME0:
                  tmp_read_data = CORE_NAME0;

                ADDR_NAME1:
                  tmp_read_data = CORE_NAME1;

                ADDR_VERSION:
                  tmp_read_data = CORE_VERSION;

                ADDR_STATUS:
                  tmp_read_data = {31'h0, core_ready};

                default:
                  begin
                  end
              endcase
            end
        end
    end
endmodule
module hmac(

            input wire           clk,
            input wire           reset_n,


            input wire           cs,
            input wire           we,


            input wire  [7 : 0]  address,
            input wire  [31 : 0] write_data,
            output wire [31 : 0] read_data
           );





  localparam ADDR_NAME0       = 8'h00;
  localparam ADDR_NAME1       = 8'h01;
  localparam ADDR_VERSION     = 8'h02;

  localparam ADDR_CTRL        = 8'h08;
  localparam CTRL_INIT_BIT    = 0;
  localparam CTRL_NEXT_BIT    = 1;
  localparam CTRL_FINAL_BIT   = 2;

  localparam ADDR_STATUS      = 8'h09;
  localparam STATUS_READY_BIT = 0;

  localparam ADDR_FINAL_LEN   = 8'h0a;

  localparam ADDR_BLOCK0      = 8'h10;
  localparam ADDR_BLOCK15     = 8'h1f;

  localparam ADDR_KEY0        = 8'h20;
  localparam ADDR_KEY15       = 8'h2f;

  localparam ADDR_TAG0        = 8'h40;
  localparam ADDR_TAG7        = 8'h47;

  localparam CORE_NAME0       = 32'h73686132;
  localparam CORE_NAME1       = 32'h2d323536;
  localparam CORE_VERSION     = 32'h312e3830;





  reg init_reg;
  reg init_new;

  reg next_reg;
  reg next_new;

  reg finalize_reg;
  reg finalize_new;

  reg [5 : 0] final_len_reg;
  reg         final_len_we;

  reg [31 : 0] key_reg [0 : 15];
  reg          key_we;

  reg [31 : 0] block_reg [0 : 15];
  reg          block_we;





  wire [255 : 0] core_key;
  wire [511 : 0] core_block;
  wire           core_ready;
  wire [127 : 0] core_tag;

  reg [31 : 0]   tmp_read_data;





  assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
                       block_reg[04], block_reg[05], block_reg[06], block_reg[07],
                       block_reg[08], block_reg[09], block_reg[10], block_reg[11],
                       block_reg[12], block_reg[13], block_reg[14], block_reg[15]};

  assign core_key = {key_reg[00], key_reg[01], key_reg[02], key_reg[03],
                     key_reg[04], key_reg[05], key_reg[06], key_reg[07]};

  assign read_data = tmp_read_data;





  hmac_core core(
                 .clk(clk),
                 .reset_n(reset_n),

                 .init(init_reg),
                 .next(next_reg),
                 .finalize(finalize_reg),
                 .final_len(final_len_reg),

                 .key(core_key),

                 .block(core_block),

                 .ready(core_ready),
                 .tag(core_tag)
                );









  always @ (posedge clk or negedge reset_n)
    begin : reg_update
      integer i;

      if (!reset_n)
        begin
          for (i = 0 ; i < 16 ; i = i + 1)
            block_reg[i] <= 32'h0;

          for (i = 0 ; i < 8 ; i = i + 1)
            key_reg[i] <= 32'h0;

          init_reg      <= 1'h0;
          next_reg      <= 1'h0;
          finalize_reg  <= 1'h0;
          final_len_reg <= 6'h0;
        end
      else
        begin
          init_reg     <= init_new;
          next_reg     <= next_new;
          finalize_reg <= finalize_new;

          if (final_len_we)
            final_len_reg <= write_data[5 : 0];

          if (key_we)
            key_reg[address[3 : 0]] <= write_data;

          if (block_we)
            block_reg[address[3 : 0]] <= write_data;
        end
    end








  always @*
    begin : api_logic
      init_new      = 0;
      next_new      = 0;
      finalize_new  = 0;
      final_len_we  = 0;
      key_we        = 0;
      block_we      = 0;
      tmp_read_data = 32'h0;

      if (cs)
        begin
          if (we)
            begin
              if (address == ADDR_CTRL)
                begin
                  init_new     = write_data[CTRL_INIT_BIT];
                  next_new     = write_data[CTRL_NEXT_BIT];
                  finalize_new = write_data[CTRL_FINAL_BIT];
                end

              if (address == ADDR_FINAL_LEN)
                final_len_we = 1;

              if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
                block_we = 1;

              if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
                block_we = 1;
            end

          else
            begin
              if ((address >= ADDR_TAG0) && (address <= ADDR_TAG3))
                tmp_read_data = core_tag[(3 - (address - ADDR_TAG0)) * 32 +: 32];

              case (address)

                ADDR_NAME0:
                  tmp_read_data = CORE_NAME0;

                ADDR_NAME1:
                  tmp_read_data = CORE_NAME1;

                ADDR_VERSION:
                  tmp_read_data = CORE_VERSION;

                ADDR_STATUS:
                  tmp_read_data = {31'h0, core_ready};

                default:
                  begin
                  end
              endcase
            end
        end
    end
endmodule