data/full_repos/permissive/165983004/updated_part2.v
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1: b'%Warning-IMPLICIT: data/full_repos/permissive/165983004/updated_part2.v:84: Signal definition not found, creating implicitly: \'left\'\n assign left = KEY[3];\n        ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/165983004/updated_part2.v:85: Signal definition not found, creating implicitly: \'right\'\n assign right = KEY[2];\n        ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:660: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'counterx\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n    x <= x_in + dx + counterx;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:697: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'counterx_n1\' generates 2 bits.\n                                                                        : ... In instance updated_part2.d1\n    x <= 8\'b10011001 + counterx_n1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:698: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'countery_n1\' generates 3 bits.\n                                                                        : ... In instance updated_part2.d1\n    y <= 7\'b0010111 + countery_n1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:734: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'counterx_n2\' generates 2 bits.\n                                                                        : ... In instance updated_part2.d1\n    x <= 8\'b10011001 + counterx_n2;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:735: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'countery_n2\' generates 3 bits.\n                                                                        : ... In instance updated_part2.d1\n    y <= 7\'b0101010 + countery_n2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:772: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'counterx_n3\' generates 2 bits.\n                                                                        : ... In instance updated_part2.d1\n    x <= 8\'b10011001 + counterx_n3;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:773: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'countery_n3\' generates 3 bits.\n                                                                        : ... In instance updated_part2.d1\n    y <= 7\'b0111101 + countery_n3;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:801: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'wheaty\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n    y <= wheaty;\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:811: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      counterx <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:812: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance updated_part2.d1\n      countery <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:828: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      counterx <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:829: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance updated_part2.d1\n      countery <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:839: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      counterx <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:840: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance updated_part2.d1\n      countery <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:850: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      counterx <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:851: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance updated_part2.d1\n      countery <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:861: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      counterx <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:862: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance updated_part2.d1\n      countery <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:874: Operator ADD expects 8 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n       data_result[7:0] <= data_result[7:0] + 4\'b0001;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:939: Operator GT expects 7 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n       if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:939: Operator LT expects 7 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n       if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:939: Operator GT expects 8 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n                                                                        : ... In instance updated_part2.d1\n       if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:939: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h78\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n       if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:953: Operator GT expects 7 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n      if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:953: Operator LT expects 7 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n      if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:953: Operator GT expects 8 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n                                                                        : ... In instance updated_part2.d1\n      if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:953: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h78\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:1014: Operator GT expects 8 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n                                                                         : ... In instance updated_part2.d1\n      if(SW[9] && y < 7\'b1101101 &&  y > 7\'b1000011 && x > 6\'b101000 && x < 8\'b01011111 && has_refined_wheat == 1)\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:1038: Operator GT expects 8 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n                                                                         : ... In instance updated_part2.d1\n      if(SW[9] && y < 7\'b1101101 &&  y > 7\'b1000011 && x > 6\'b101000 && x < 8\'b01011111)\n                                                         ^\n%Error: data/full_repos/permissive/165983004/updated_part2.v:54: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165983004,data/full_repos/permissive/165983004/vga_adapter\n             data/full_repos/permissive/165983004,data/full_repos/permissive/165983004/vga_adapter.v\n             data/full_repos/permissive/165983004,data/full_repos/permissive/165983004/vga_adapter.sv\n             vga_adapter\n             vga_adapter.v\n             vga_adapter.sv\n             obj_dir/vga_adapter\n             obj_dir/vga_adapter.v\n             obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 31 warning(s)\n'
module updated_part2
	(
		CLOCK_50,

        KEY,
        SW,
		  LEDR,
		  LEDG,

		VGA_CLK,
		VGA_HS,
		VGA_VS,
		VGA_BLANK_N,
		VGA_SYNC_N,
		VGA_R,
		VGA_G,
		VGA_B,
		HEX0, 
		HEX1
	);

	input			CLOCK_50;
	input   [17:0]   SW;
	input   [3:0]   KEY;
	output [17:0] LEDR;
	output [7:0] LEDG;


	output			VGA_CLK;
	output			VGA_HS;
	output			VGA_VS;
	output			VGA_BLANK_N;
	output			VGA_SYNC_N;
	output	[9:0]	VGA_R;
	output	[9:0]	VGA_G;
	output	[9:0]	VGA_B;
	
	
	output [6:0] HEX0, HEX1;

	wire resetn;
	assign resetn = KEY[0];
	

	wire [2:0] colour;
	wire [7:0] x;
	wire [6:0] y;
	wire writeEn;




	vga_adapter VGA(
			.resetn(resetn),
			.clock(CLOCK_50),
			.colour(colour),
			.x(x),
			.y(y),
			.plot(1'b1),

			.VGA_R(VGA_R),
			.VGA_G(VGA_G),
			.VGA_B(VGA_B),
			.VGA_HS(VGA_HS),
			.VGA_VS(VGA_VS),
			.VGA_BLANK(VGA_BLANK_N),
			.VGA_SYNC(VGA_SYNC_N),
			.VGA_CLK(VGA_CLK));
		defparam VGA.RESOLUTION = "160x120";
		defparam VGA.MONOCHROME = "FALSE";
		defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
		defparam VGA.BACKGROUND_IMAGE = "hopefully_this_works.mif";
			


	wire [6:0] datain;
	wire load_x, load_y, load_r, load_c, ld_alu_out;
	wire go, loadEn;
	
	wire [7:0]x_in = 8'b00110010;
	wire [6:0]y_in = 7'b0110010;
	
	assign left = KEY[3];
	assign right = KEY[2];
	
	
	datapath d1(SW, KEY, LEDR, LEDG, CLOCK_50, resetn, x_in, y_in, x, y, colour, data_result);

	
	wire [7:0] data_result;

	hex_decoder H0(
        .hex_digit(data_result[3:0]), 
        .segments(HEX0)
        );
        
    hex_decoder H1(
        .hex_digit(data_result[7:4]), 
        .segments(HEX1)
        );

    
endmodule
module updated_part2
	(
		CLOCK_50,

        KEY,
        SW,
		  LEDR,
		  LEDG,

		VGA_CLK,
		VGA_HS,
		VGA_VS,
		VGA_BLANK_N,
		VGA_SYNC_N,
		VGA_R,
		VGA_G,
		VGA_B,
		HEX0, 
		HEX1
	);


	input			CLOCK_50;
	input   [17:0]   SW;
	input   [3:0]   KEY;
	output [17:0] LEDR;
	output [7:0] LEDG;


	output			VGA_CLK;
	output			VGA_HS;
	output			VGA_VS;
	output			VGA_BLANK_N;
	output			VGA_SYNC_N;
	output	[9:0]	VGA_R;
	output	[9:0]	VGA_G;
	output	[9:0]	VGA_B;
	
	
	output [6:0] HEX0, HEX1;

	wire resetn;
	assign resetn = KEY[0];
	

	wire [2:0] colour;
	wire [7:0] x;
	wire [6:0] y;
	wire writeEn;




	vga_adapter VGA(
			.resetn(resetn),
			.clock(CLOCK_50),
			.colour(colour),
			.x(x),
			.y(y),
			.plot(1'b1),

			.VGA_R(VGA_R),
			.VGA_G(VGA_G),
			.VGA_B(VGA_B),
			.VGA_HS(VGA_HS),
			.VGA_VS(VGA_VS),
			.VGA_BLANK(VGA_BLANK_N),
			.VGA_SYNC(VGA_SYNC_N),
			.VGA_CLK(VGA_CLK));
		defparam VGA.RESOLUTION = "160x120";
		defparam VGA.MONOCHROME = "FALSE";
		defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
		defparam VGA.BACKGROUND_IMAGE = "hopefully_this_works.mif";
			


	wire [6:0] datain;
	wire load_x, load_y, load_r, load_c, ld_alu_out;
	wire go, loadEn;
	
	wire [7:0]x_in = 8'b00110010;
	wire [6:0]y_in = 7'b0110010;
	
	assign left = KEY[3];
	assign right = KEY[2];
	
	
	datapath d1(SW, KEY, LEDR, LEDG, CLOCK_50, resetn, x_in, y_in, x, y, colour, data_result);

	
	wire [7:0] data_result;

	hex_decoder H0(
        .hex_digit(data_result[3:0]), 
        .segments(HEX0)
        );
        
    hex_decoder H1(
        .hex_digit(data_result[7:4]), 
        .segments(HEX1)
        );

    
endmodule