data/full_repos/permissive/166008742/src/tb_led_driver.v
 line:97: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_led_driver.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PER/2);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/166008742/src/tb_led_driver.v:97: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_led_driver.v:99: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk)\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_led_driver.v:106: syntax error, unexpected \'@\'\n            while (~ctrl_update_done) @(posedge clk);\n                                      ^\n%Error: data/full_repos/permissive/166008742/src/tb_led_driver.v:110: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_led_driver.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_led_driver ();
    parameter ADDR_WIDTH = 16;
    parameter DATA_WIDTH = 32;
    parameter CLK_PER = 10;

    reg reset;
    reg clk;



    wire [ADDR_WIDTH-1:0] wbm_address;
    wire [DATA_WIDTH-1:0] wbm_writedata;
    wire wbm_strobe;
    wire wbm_cycle;
    wire wbm_write;


    wire wbm_ack;
    wire [DATA_WIDTH-1:0] wbm_readdata;

    reg  ctrl_update;
    reg  [DATA_WIDTH-1:0] ctrl_buf_id;
    wire ctrl_update_done;

    wire led_data_out;

    mem #(ADDR_WIDTH, DATA_WIDTH) wb_mem(
        .reset(reset),
        .clk(clk),


        .wbm_address(wbm_address),
        .wbm_writedata(wbm_writedata),
        .wbm_readdata(wbm_readdata),
        .wbm_strobe(wbm_strobe),
        .wbm_cycle(wbm_cycle),
        .wbm_write(wbm_write),
        .wbm_ack(wbm_ack)
    );


    led_driver #(ADDR_WIDTH, DATA_WIDTH, CLK_PER) dut
    (
        .reset(reset),
        .clk(clk),


        .wbm_address(wbm_address),
        .wbm_writedata(wbm_writedata),
        .wbm_readdata(wbm_readdata),
        .wbm_strobe(wbm_strobe),
        .wbm_cycle(wbm_cycle),
        .wbm_write(wbm_write),
        .wbm_ack(wbm_ack),


        .ctrl_update(ctrl_update),
        .ctrl_buf_id(ctrl_buf_id),
        .ctrl_update_done(ctrl_update_done),

        .led_data_out(led_data_out)
    );




    always begin
        #(CLK_PER/2);
        clk <= ~clk;
    end

    initial begin
        clk <= 0;
        reset <= 1;

        ctrl_update <= 0;
        ctrl_buf_id <= 0;
        

        repeat (100) @(posedge clk);
        reset <= 0;
        repeat (100) @(posedge clk)

        ctrl_buf_id <= 0;

        repeat(3) begin
            ctrl_update <= 1;
            
            while (~ctrl_update_done) @(posedge clk);

            ctrl_buf_id <= ctrl_buf_id + 1;
            ctrl_update <= 0;
            @(posedge clk);
        end

        #100;
    end

endmodule
module tb_led_driver ();

    parameter ADDR_WIDTH = 16;
    parameter DATA_WIDTH = 32;
    parameter CLK_PER = 10;

    reg reset;
    reg clk;



    wire [ADDR_WIDTH-1:0] wbm_address;
    wire [DATA_WIDTH-1:0] wbm_writedata;
    wire wbm_strobe;
    wire wbm_cycle;
    wire wbm_write;


    wire wbm_ack;
    wire [DATA_WIDTH-1:0] wbm_readdata;

    reg  ctrl_update;
    reg  [DATA_WIDTH-1:0] ctrl_buf_id;
    wire ctrl_update_done;

    wire led_data_out;

    mem #(ADDR_WIDTH, DATA_WIDTH) wb_mem(
        .reset(reset),
        .clk(clk),


        .wbm_address(wbm_address),
        .wbm_writedata(wbm_writedata),
        .wbm_readdata(wbm_readdata),
        .wbm_strobe(wbm_strobe),
        .wbm_cycle(wbm_cycle),
        .wbm_write(wbm_write),
        .wbm_ack(wbm_ack)
    );


    led_driver #(ADDR_WIDTH, DATA_WIDTH, CLK_PER) dut
    (
        .reset(reset),
        .clk(clk),


        .wbm_address(wbm_address),
        .wbm_writedata(wbm_writedata),
        .wbm_readdata(wbm_readdata),
        .wbm_strobe(wbm_strobe),
        .wbm_cycle(wbm_cycle),
        .wbm_write(wbm_write),
        .wbm_ack(wbm_ack),


        .ctrl_update(ctrl_update),
        .ctrl_buf_id(ctrl_buf_id),
        .ctrl_update_done(ctrl_update_done),

        .led_data_out(led_data_out)
    );




    always begin
        #(CLK_PER/2);
        clk <= ~clk;
    end

    initial begin
        clk <= 0;
        reset <= 1;

        ctrl_update <= 0;
        ctrl_buf_id <= 0;
        

        repeat (100) @(posedge clk);
        reset <= 0;
        repeat (100) @(posedge clk)

        ctrl_buf_id <= 0;

        repeat(3) begin
            ctrl_update <= 1;
            
            while (~ctrl_update_done) @(posedge clk);

            ctrl_buf_id <= ctrl_buf_id + 1;
            ctrl_update <= 0;
            @(posedge clk);
        end

        #100;
    end

endmodule