data/full_repos/permissive/183345139/hba_quad/quadrature.v
data/verilator_xmls/b1087a44-49f7-4626-b0cc-0284615929ef.xml
module quadrature
(
    input wire clk,
    input wire reset,


    input wire quad_enc_a,
    input wire quad_enc_b,


    output reg enc_out,
    output reg enc_dir

);




reg [1:0] sample;
reg [1:0] sample_reg;




localparam FWD      = 0;
localparam EA       = 0;
localparam EB       = 1;


always @ (posedge clk)
begin
    if (reset) begin
        sample <= 0;
        sample_reg <= 0;
    end else begin
        sample_reg <= sample;
        sample[EA] <= quad_enc_a;
        sample[EB] <= quad_enc_b;
    end
end








always @ (posedge clk)
begin
    if (reset) begin
        enc_dir <= FWD;
        enc_out <= 0;
    end else begin

        enc_out <= ^sample;



        if (sample != sample_reg) begin
            case (sample)
                0 : begin
                    enc_dir <= sample_reg[EA];
                end
                1 : begin
                    enc_dir <= sample_reg[EA];
                end
                2 : begin
                    enc_dir <= ~sample_reg[EA];
                end
                3 : begin
                    enc_dir <= ~sample_reg[EA];
                end
            endcase
        end
    end
end

endmodule
module quadrature
(
    input wire clk,
    input wire reset,


    input wire quad_enc_a,
    input wire quad_enc_b,


    output reg enc_out,
    output reg enc_dir

);





reg [1:0] sample;
reg [1:0] sample_reg;




localparam FWD      = 0;
localparam EA       = 0;
localparam EB       = 1;


always @ (posedge clk)
begin
    if (reset) begin
        sample <= 0;
        sample_reg <= 0;
    end else begin
        sample_reg <= sample;
        sample[EA] <= quad_enc_a;
        sample[EB] <= quad_enc_b;
    end
end








always @ (posedge clk)
begin
    if (reset) begin
        enc_dir <= FWD;
        enc_out <= 0;
    end else begin

        enc_out <= ^sample;



        if (sample != sample_reg) begin
            case (sample)
                0 : begin
                    enc_dir <= sample_reg[EA];
                end
                1 : begin
                    enc_dir <= sample_reg[EA];
                end
                2 : begin
                    enc_dir <= ~sample_reg[EA];
                end
                3 : begin
                    enc_dir <= ~sample_reg[EA];
                end
            endcase
        end
    end
end

endmodule