data/full_repos/permissive/136056083/src/InstructionCache.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136056083/src/InstructionCache.v:22: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 29 bits.\n                                                                              : ... In instance InstructionCache\n wire [3:0] setID = blockAddress % 16;  \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136056083/src/InstructionCache.v:23: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 29 bits.\n                                                                              : ... In instance InstructionCache\n    assign setID = blockAddress % 16;\n                 ^\n%Error: Exiting due to 2 warning(s)\n'
module InstructionCache(PC, instruction, clock);

input clock;
input [31:0] PC;



`ifdef DEBUG
  input [31:0] instruction;
`else
  output reg[31:0] instruction;
`endif
   
	reg [28:0]setAddress[0:15];
   	reg [31:0]setData[0:15]; 
	reg [6:0]i;
    wire [28:0]blockAddress = PC[31:3];

	wire [3:0] setID = blockAddress % 16;
    assign setID = blockAddress % 16;

	always @(posedge clock) begin : search

        if(blockAddress == setAddress[setID]) begin

            instruction = setData[setID];
            disable search;
        end

        else begin
                setAddress[setID] = blockAddress;


                setData[setID] = 32'hDEAD_BEEF;
                instruction = 32'hDEAD_BEEF;           
        end
       

    end

	initial begin




























        setAddress[0] = 29'h00000020; setData[0] = 32'b11111000010000000000001010000001;

        setAddress[1] = 29'h00000021; setData[1] = 32'b10001011000000010000000000100010;

        setAddress[2] = 29'h00000022; setData[2] = 32'b11010001000000000000001100110011;

        setAddress[3] = 29'h00000023; setData[3] = 32'b10110100000000000000000011100011;

        setAddress[4] = 29'h00000024; setData[4] = 32'b10010001000000000010001010010100;

        setAddress[5] = 29'h00000025; setData[5] = 32'b11111000000111110100001010000001;

        setAddress[6] = 29'h00000026; setData[6] = 32'b00010111111111111111111111111010;

        




        
	end

endmodule
module InstructionCache(PC, instruction, clock);


input clock;
input [31:0] PC;



`ifdef DEBUG
  input [31:0] instruction;
`else
  output reg[31:0] instruction;
`endif
   
	reg [28:0]setAddress[0:15];
   	reg [31:0]setData[0:15]; 
	reg [6:0]i;
    wire [28:0]blockAddress = PC[31:3];

	wire [3:0] setID = blockAddress % 16;
    assign setID = blockAddress % 16;

	always @(posedge clock) begin : search

        if(blockAddress == setAddress[setID]) begin

            instruction = setData[setID];
            disable search;
        end

        else begin
                setAddress[setID] = blockAddress;


                setData[setID] = 32'hDEAD_BEEF;
                instruction = 32'hDEAD_BEEF;           
        end
       

    end

	initial begin




























        setAddress[0] = 29'h00000020; setData[0] = 32'b11111000010000000000001010000001;

        setAddress[1] = 29'h00000021; setData[1] = 32'b10001011000000010000000000100010;

        setAddress[2] = 29'h00000022; setData[2] = 32'b11010001000000000000001100110011;

        setAddress[3] = 29'h00000023; setData[3] = 32'b10110100000000000000000011100011;

        setAddress[4] = 29'h00000024; setData[4] = 32'b10010001000000000010001010010100;

        setAddress[5] = 29'h00000025; setData[5] = 32'b11111000000111110100001010000001;

        setAddress[6] = 29'h00000026; setData[6] = 32'b00010111111111111111111111111010;

        




        
	end

endmodule