data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0401/lab0401.srcs/sim_1/new/registers_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0401/lab0401.srcs/sim_1/new/registers_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD/2) Clk = 1\'b1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0401/lab0401.srcs/sim_1/new/registers_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD/2);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0401/lab0401.srcs/sim_1/new/registers_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #285;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0401/lab0401.srcs/sim_1/new/registers_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0401/lab0401.srcs/sim_1/new/registers_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0401/lab0401.srcs/sim_1/new/registers_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0401/lab0401.srcs/sim_1/new/registers_tb.v:36: Cannot find file containing module: \'registers\'\n    registers u0(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0401/lab0401.srcs/sim_1/new,data/full_repos/permissive/194376374/registers\n             data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0401/lab0401.srcs/sim_1/new,data/full_repos/permissive/194376374/registers.v\n             data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0401/lab0401.srcs/sim_1/new,data/full_repos/permissive/194376374/registers.sv\n             registers\n             registers.v\n             registers.sv\n             obj_dir/registers\n             obj_dir/registers.v\n             obj_dir/registers.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module registers_tb(
    );
    
    reg [25:21] readReg1;
    reg [20:16] readReg2;
    reg [4:0] writeReg;
    reg [31:0] writeData;
    reg regWrite;
    reg Clk;
    
    wire [31:0] readData1;
    wire [31:0] readData2;   
    
    registers u0(
        .readReg1(readReg1),
        .readReg2(readReg2),
        .writeReg(writeReg),
        .writeData(writeData),
        .regWrite(regWrite),
        .Clk(Clk),
        
        .readData1(readData1),
        .readData2(readData2)
    );
 
    parameter PERIOD = 200;
    
   always begin
      Clk = 1'b0;
      #(PERIOD/2) Clk = 1'b1;
      #(PERIOD/2);
   end
 
    
    initial begin

        regWrite=0;
        readReg1=0;
        readReg2=0;
        writeData=0;
        writeReg=0;

    

        #285;
        regWrite=1'b1;
        writeReg=5'b10101;
        writeData=32'b11111111111111110000000000000000;


        #200;
        writeReg=5'b01010;
        writeData=32'b00000000000000001111111111111111;
                

        #200;
        regWrite=1'b0;
        writeReg=5'b00000;
        writeData=32'b00000000000000000000000000000000;
        

        #50;
        readReg1=5'b10101;
        readReg2=5'b01010;
        
                
    end
endmodule
module registers_tb(
    );

    
    reg [25:21] readReg1;
    reg [20:16] readReg2;
    reg [4:0] writeReg;
    reg [31:0] writeData;
    reg regWrite;
    reg Clk;
    
    wire [31:0] readData1;
    wire [31:0] readData2;   
    
    registers u0(
        .readReg1(readReg1),
        .readReg2(readReg2),
        .writeReg(writeReg),
        .writeData(writeData),
        .regWrite(regWrite),
        .Clk(Clk),
        
        .readData1(readData1),
        .readData2(readData2)
    );
 
    parameter PERIOD = 200;
    
   always begin
      Clk = 1'b0;
      #(PERIOD/2) Clk = 1'b1;
      #(PERIOD/2);
   end
 
    
    initial begin

        regWrite=0;
        readReg1=0;
        readReg2=0;
        writeData=0;
        writeReg=0;

    

        #285;
        regWrite=1'b1;
        writeReg=5'b10101;
        writeData=32'b11111111111111110000000000000000;


        #200;
        writeReg=5'b01010;
        writeData=32'b00000000000000001111111111111111;
                

        #200;
        regWrite=1'b0;
        writeReg=5'b00000;
        writeData=32'b00000000000000000000000000000000;
        

        #50;
        readReg1=5'b10101;
        readReg2=5'b01010;
        
                
    end
endmodule