data/full_repos/permissive/170402453/RISC/SHIFTER16_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/SHIFTER16_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/SHIFTER16_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/SHIFTER16_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/SHIFTER16_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/SHIFTER16_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n%Error: data/full_repos/permissive/170402453/RISC/SHIFTER16_tb.v:37: Cannot find file containing module: \'SHIFTER16\'\n SHIFTER16 uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/SHIFTER16\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/SHIFTER16.v\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/SHIFTER16.sv\n             SHIFTER16\n             SHIFTER16.v\n             SHIFTER16.sv\n             obj_dir/SHIFTER16\n             obj_dir/SHIFTER16.v\n             obj_dir/SHIFTER16.sv\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/SHIFTER16_tb.v:58: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance SHIFTER16_tb\n   B = i;\n     ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SHIFTER16_tb;


	reg [1:0] Select;
	reg [15:0] B;
	reg InL;
	reg InR;


	wire [15:0] HOut;
	integer i;

	SHIFTER16 uut (
		.Select(Select), 
		.B(B), 
		.InL(InL), 
		.InR(InR), 
		.HOut(HOut)
	);

	initial begin

		Select = 0;
		B = 0;
		InL = 0;
		InR = 0;


		#100;
        

	   for(i=0;i<65535;i=i+1) begin
			Select = 0;
			B = i;
			#5;
			Select = 1;
			#5;
			Select = 2;
			#5;
			Select = 3;
			#5;
		end
	end
      
endmodule
module SHIFTER16_tb;



	reg [1:0] Select;
	reg [15:0] B;
	reg InL;
	reg InR;


	wire [15:0] HOut;
	integer i;

	SHIFTER16 uut (
		.Select(Select), 
		.B(B), 
		.InL(InL), 
		.InR(InR), 
		.HOut(HOut)
	);

	initial begin

		Select = 0;
		B = 0;
		InL = 0;
		InR = 0;


		#100;
        

	   for(i=0;i<65535;i=i+1) begin
			Select = 0;
			B = i;
			#5;
			Select = 1;
			#5;
			Select = 2;
			#5;
			Select = 3;
			#5;
		end
	end
      
endmodule