data/full_repos/permissive/136510272/projects/sdramvga/sdramvga640.v
 line:358: before: ")"
1: b"%Error: data/full_repos/permissive/136510272/projects/sdramvga/sdramvga640.v:69: Too many digits for 10 bit number: 10'b010000000000\ninitial addrc = 10'b010000000000;  \n                ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module sdramvga640(


    input   wire        clock,


    output  wire        clksdram,
    output  wire [11:0] addr,
    output  reg  [1:0]  bank,
    inout   wire [15:0] dq,
    output  wire        ldqm,
    output  wire        udqm,
    output  wire        ras,
    output  wire        cas,
    output  wire        we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire [21:0] address,
    input   wire [15:0] i_data,
    output  wire [15:0] o_data,
    input   wire        rdwr,
    input   wire        clk,
    output  reg         lock

);

assign dq = we ? 16'bZ : i_data;
assign clksdram = clock;

localparam debug_init_nl = 1'b0;
localparam debug_init_sd = 1'b1;


localparam iwaitc = 1250;


localparam cmd_loadmode     = 3'b000;
localparam cmd_refresh      = 3'b001;
localparam cmd_precharge    = 3'b010;
localparam cmd_activate     = 3'b011;
localparam cmd_write        = 3'b100;
localparam cmd_read         = 3'b101;
localparam cmd_burst_term   = 3'b110;
localparam cmd_nop          = 3'b111;


`define SDRAM_WAIT      3'b000
`define SDRAM_READ3     3'b001
`define SDRAM_READ3A    3'b010
`define SDRAM_WRITE     3'b011
`define SDRAM_READ      3'b100


initial initlock = debug_init_sd;
initial lock = 1'b1;
initial addrc = 10'b010000000000;
initial cmdinit = cmd_nop;
initial cmd = cmd_nop;



assign ras  = initlock ? cmdinit[2] : cmd[2];
assign cas  = initlock ? cmdinit[1] : cmd[1];
assign  we  = initlock ? cmdinit[0] : cmd[0];
assign addr = initlock ? addrc : addrw;

reg        initlock;
reg [10:0] init = 1'b1;

reg [2:0]  cmd;
reg [11:0] addrw;

reg [2:0]  cmdinit;
reg [11:0] addrc;



reg [2:0] div;
always @(posedge clock) div <= div + 1'b1;


always @(posedge div[2]) begin

    if (initlock) begin

if (init == iwaitc + 1)  begin cmdinit <= cmd_precharge; end
else if (init == iwaitc + 4)  begin cmdinit <= cmd_refresh; end
else if (init == iwaitc + 18) begin cmdinit <= cmd_loadmode; addrc[9:0] <= 10'b0000100111; end
else if (init == iwaitc + 21) begin initlock <= 1'b0; end
else begin cmdinit <= cmd_nop; end

        init <= init + 1'b1;

    end

end


reg [7:0] bank_cnt;


reg [2:0] bank_num;


reg [9:0]  aw;
reg [15:0] dw;
reg        cb;
reg        wb;


wire [18:0] caddr = vaddr[18:0] + {bank_num[2:0],7'b0000000};



assign hdqm = 1'b0;
assign ldqm = 1'b0;
        


reg [3:0] state = `SDRAM_WAIT;
reg       nl    = debug_init_nl;
wire      x_accept = (x < 798);


always @(posedge clock) begin

    nl <= y[0];

    if (initlock == 1'b0) begin
    

        if (nl ^ y[0]) begin 
        
            state    <= `SDRAM_READ3;             
            cb       <= y[0];
            aw       <= -1;
            bank_cnt <= 1'b0;
            bank_num <= 1'b0;
            lock     <= 1'b1;
            
        end

        else case (state)
        

            `SDRAM_WAIT: begin


                 
                lock <= (x_accept & clk) | (!x_accept);
            



                
                if (clk && x_accept) state <= rdwr ? `SDRAM_WRITE : `SDRAM_READ;
                

                bank_cnt    <= 1'b0;    
                cmd         <= cmd_nop;

            end
            

            `SDRAM_READ3: begin

                bank        <= 2'b00;
                addrw       <= {1'b0, caddr[18:8]};
                cmd         <= cmd_activate;
                bank_cnt    <= 1'b0;            
                state       <= `SDRAM_READ3A;

            end
            

            `SDRAM_READ3A: begin
            

                if (bank_cnt < 3) begin
                
                    cmd   <= cmd_nop;
                
                end
            

                if (bank_cnt == 3) begin
                
                    addrw <= {4'b0000, caddr[7:0]};
                    cmd   <= cmd_read;
                
                end
                

                else if (bank_cnt == 4 || bank_cnt == 5) begin
                    
                    addrw[7:0] <= addrw[7:0] + 1'b1; 
                    
                end
                

                else if (bank_cnt > 5 && bank_cnt < 6 + 128) begin
                
                    dw <= dq;
                    wb <= 1'b1;
                    aw <= aw + 1'b1;

                    addrw[7:0] <= addrw[7:0] + 1'b1;
                
                end
                

                else if (bank_cnt == 6 + 128) begin 
                
                    cmd       <= cmd_precharge;
                    addrw[10] <= 1'b1;
                    wb        <= 1'b0;
                
                end
                

                else if (bank_cnt == 7 + 128) begin
                
                    cmd         <= cmd_nop;
                    state       <= bank_num == 3'd4 ? `SDRAM_WAIT : `SDRAM_READ3;
                    bank_num    <= bank_num + 1'b1;

                end
                

                bank_cnt <= bank_cnt + 1'b1;
            
            end            
        

            `SDRAM_WRITE: begin
            
                case (bank_cnt)
                

                    3'h0: begin
                    
                        bank  <= address[21:20];
                        addrw <= {address[19:8]};
                        cmd   <= cmd_activate;

                    end
                    

                    3'h3: begin
                    
                        addrw <= {4'b0100, address[7:0]};
                        cmd   <= cmd_write;

                    end
                    

                    3'h5: begin cmd <= cmd_precharge;  end
                    

                    3'h6: begin cmd <= cmd_nop; state <= `SDRAM_WAIT; end
                    
                
                endcase
                
                bank_cnt <= bank_cnt + 1'b1;
            
            end
            

            `SDRAM_READ: begin
            
            end
            
        endcase

    end

end






reg     [10:0]  x = 1'b0;
reg     [9:0]   y = 1'b0;


reg     [18:0]  vaddr = 1'b0;


reg     [10:0]  ar;
reg     [15:0]  dr;

assign  vga_red   = display ? dr[15:11] : 1'b0;
assign  vga_green = display ? dr[10:5] : 1'b0;
assign  vga_blue  = display ? dr[4:0] : 1'b0;

assign  vga_hs  = x > 10'd688 && x <= 10'd784; 
assign  vga_vs  = y > 10'd513 && y <= 10'd515; 
wire    display = x < 10'd640 && y < 10'd480;

wire    xend = x == 11'd800;
wire    yend = y == 10'd525;


always @(posedge div[1]) begin    


    x <= xend ?         1'b0 : x + 1'b1;
    y <= xend ? (yend ? 1'b0 : y + 1'b1) : y;
    
    ar <= {y[0] ^ 1'b1, x[9:0]};
    

    if (xend) vaddr <= y * 640;

end





vidbuf VIDBUF(

    .clock   (clksdram),
    .addr_rd (ar),
    .q       (dr),
    .addr_wr ({cb, aw}),
    .data_wr (dw),
    .wren    (wb),

);

endmodule
module sdramvga640(


    input   wire        clock,


    output  wire        clksdram,
    output  wire [11:0] addr,
    output  reg  [1:0]  bank,
    inout   wire [15:0] dq,
    output  wire        ldqm,
    output  wire        udqm,
    output  wire        ras,
    output  wire        cas,
    output  wire        we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire [21:0] address,
    input   wire [15:0] i_data,
    output  wire [15:0] o_data,
    input   wire        rdwr,
    input   wire        clk,
    output  reg         lock

);


assign dq = we ? 16'bZ : i_data;
assign clksdram = clock;

localparam debug_init_nl = 1'b0;
localparam debug_init_sd = 1'b1;


localparam iwaitc = 1250;


localparam cmd_loadmode     = 3'b000;
localparam cmd_refresh      = 3'b001;
localparam cmd_precharge    = 3'b010;
localparam cmd_activate     = 3'b011;
localparam cmd_write        = 3'b100;
localparam cmd_read         = 3'b101;
localparam cmd_burst_term   = 3'b110;
localparam cmd_nop          = 3'b111;


`define SDRAM_WAIT      3'b000
`define SDRAM_READ3     3'b001
`define SDRAM_READ3A    3'b010
`define SDRAM_WRITE     3'b011
`define SDRAM_READ      3'b100


initial initlock = debug_init_sd;
initial lock = 1'b1;
initial addrc = 10'b010000000000;
initial cmdinit = cmd_nop;
initial cmd = cmd_nop;



assign ras  = initlock ? cmdinit[2] : cmd[2];
assign cas  = initlock ? cmdinit[1] : cmd[1];
assign  we  = initlock ? cmdinit[0] : cmd[0];
assign addr = initlock ? addrc : addrw;

reg        initlock;
reg [10:0] init = 1'b1;

reg [2:0]  cmd;
reg [11:0] addrw;

reg [2:0]  cmdinit;
reg [11:0] addrc;



reg [2:0] div;
always @(posedge clock) div <= div + 1'b1;


always @(posedge div[2]) begin

    if (initlock) begin

if (init == iwaitc + 1)  begin cmdinit <= cmd_precharge; end
else if (init == iwaitc + 4)  begin cmdinit <= cmd_refresh; end
else if (init == iwaitc + 18) begin cmdinit <= cmd_loadmode; addrc[9:0] <= 10'b0000100111; end
else if (init == iwaitc + 21) begin initlock <= 1'b0; end
else begin cmdinit <= cmd_nop; end

        init <= init + 1'b1;

    end

end


reg [7:0] bank_cnt;


reg [2:0] bank_num;


reg [9:0]  aw;
reg [15:0] dw;
reg        cb;
reg        wb;


wire [18:0] caddr = vaddr[18:0] + {bank_num[2:0],7'b0000000};



assign hdqm = 1'b0;
assign ldqm = 1'b0;
        


reg [3:0] state = `SDRAM_WAIT;
reg       nl    = debug_init_nl;
wire      x_accept = (x < 798);


always @(posedge clock) begin

    nl <= y[0];

    if (initlock == 1'b0) begin
    

        if (nl ^ y[0]) begin 
        
            state    <= `SDRAM_READ3;             
            cb       <= y[0];
            aw       <= -1;
            bank_cnt <= 1'b0;
            bank_num <= 1'b0;
            lock     <= 1'b1;
            
        end

        else case (state)
        

            `SDRAM_WAIT: begin


                 
                lock <= (x_accept & clk) | (!x_accept);
            



                
                if (clk && x_accept) state <= rdwr ? `SDRAM_WRITE : `SDRAM_READ;
                

                bank_cnt    <= 1'b0;    
                cmd         <= cmd_nop;

            end
            

            `SDRAM_READ3: begin

                bank        <= 2'b00;
                addrw       <= {1'b0, caddr[18:8]};
                cmd         <= cmd_activate;
                bank_cnt    <= 1'b0;            
                state       <= `SDRAM_READ3A;

            end
            

            `SDRAM_READ3A: begin
            

                if (bank_cnt < 3) begin
                
                    cmd   <= cmd_nop;
                
                end
            

                if (bank_cnt == 3) begin
                
                    addrw <= {4'b0000, caddr[7:0]};
                    cmd   <= cmd_read;
                
                end
                

                else if (bank_cnt == 4 || bank_cnt == 5) begin
                    
                    addrw[7:0] <= addrw[7:0] + 1'b1; 
                    
                end
                

                else if (bank_cnt > 5 && bank_cnt < 6 + 128) begin
                
                    dw <= dq;
                    wb <= 1'b1;
                    aw <= aw + 1'b1;

                    addrw[7:0] <= addrw[7:0] + 1'b1;
                
                end
                

                else if (bank_cnt == 6 + 128) begin 
                
                    cmd       <= cmd_precharge;
                    addrw[10] <= 1'b1;
                    wb        <= 1'b0;
                
                end
                

                else if (bank_cnt == 7 + 128) begin
                
                    cmd         <= cmd_nop;
                    state       <= bank_num == 3'd4 ? `SDRAM_WAIT : `SDRAM_READ3;
                    bank_num    <= bank_num + 1'b1;

                end
                

                bank_cnt <= bank_cnt + 1'b1;
            
            end            
        

            `SDRAM_WRITE: begin
            
                case (bank_cnt)
                

                    3'h0: begin
                    
                        bank  <= address[21:20];
                        addrw <= {address[19:8]};
                        cmd   <= cmd_activate;

                    end
                    

                    3'h3: begin
                    
                        addrw <= {4'b0100, address[7:0]};
                        cmd   <= cmd_write;

                    end
                    

                    3'h5: begin cmd <= cmd_precharge;  end
                    

                    3'h6: begin cmd <= cmd_nop; state <= `SDRAM_WAIT; end
                    
                
                endcase
                
                bank_cnt <= bank_cnt + 1'b1;
            
            end
            

            `SDRAM_READ: begin
            
            end
            
        endcase

    end

end






reg     [10:0]  x = 1'b0;
reg     [9:0]   y = 1'b0;


reg     [18:0]  vaddr = 1'b0;


reg     [10:0]  ar;
reg     [15:0]  dr;

assign  vga_red   = display ? dr[15:11] : 1'b0;
assign  vga_green = display ? dr[10:5] : 1'b0;
assign  vga_blue  = display ? dr[4:0] : 1'b0;

assign  vga_hs  = x > 10'd688 && x <= 10'd784; 
assign  vga_vs  = y > 10'd513 && y <= 10'd515; 
wire    display = x < 10'd640 && y < 10'd480;

wire    xend = x == 11'd800;
wire    yend = y == 10'd525;


always @(posedge div[1]) begin    


    x <= xend ?         1'b0 : x + 1'b1;
    y <= xend ? (yend ? 1'b0 : y + 1'b1) : y;
    
    ar <= {y[0] ^ 1'b1, x[9:0]};
    

    if (xend) vaddr <= y * 640;

end





vidbuf VIDBUF(

    .clock   (clksdram),
    .addr_rd (ar),
    .q       (dr),
    .addr_wr ({cb, aw}),
    .data_wr (dw),
    .wren    (wb),

);

endmodule