data/full_repos/permissive/100331186/tarea3/modulos/ffD.v
 line:70: before: ":"
1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:70: Unsupported: Ignoring delay on this delayed statement.\n      if (d) # (tplhclkmin:tplhclktyp:tplhclkmax) q <= d;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:71: Unsupported: Ignoring delay on this delayed statement.\n      else # (tphlclkmin:tphlclktyp:tphlclkmax) q <= d;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:77: Unsupported: Ignoring delay on this delayed statement.\n      #(tplhmin:tplhtyp:tplhmax) q <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:79: Unsupported: Ignoring delay on this delayed statement.\n      #(tphlmin:tphltyp:tphlmax) q <= 0;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:39: Duplicate declaration of signal: \'d\'\n                                                                    : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire d;\n       ^\n        data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:32: ... Location of original declaration\n  input d,\n        ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:40: Duplicate declaration of signal: \'clk\'\n  wire clk;\n       ^~~\n        data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:33: ... Location of original declaration\n  input clk,\n        ^~~\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:43: Duplicate declaration of signal: \'q\'\n  reg q;\n      ^\n        data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:36: ... Location of original declaration\n  output q,\n         ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:44: Duplicate declaration of signal: \'notq\'\n  reg notq;\n      ^~~~\n        data/full_repos/permissive/100331186/tarea3/modulos/ffD.v:37: ... Location of original declaration\n  output notq\n         ^~~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ffD(
  input d,
  input clk,
  input notpreset,
  input notclear,
  output q,
  output notq
);
  wire d;
  wire clk;
  wire preset;
  wire clear;
  reg q;
  reg notq;


  parameter tplhmin = 1.5;
  parameter tplhtyp = 5.8;
  parameter tplhmax = 9.3;
  parameter tphlmin = 1.5;
  parameter tphltyp = 6.5;
  parameter tphlmax = 11.4;


  parameter tplhclkmin = 1.5;
  parameter tplhclktyp = 7.7;
  parameter tplhclkmax = 10.5;
  parameter tphlclkmin = 1.5;
  parameter tphlclktyp = 7.3;
  parameter tphlclkmax = 9.7;

  parameter Vcc = 3.3;
  parameter Cl = 0.05;

  integer c;
  initial c = 0;

  always @ (posedge clk) begin
    if (notpreset & notclear) begin
      if (d) # (tplhclkmin:tplhclktyp:tplhclkmax) q <= d;
      else # (tphlclkmin:tphlclktyp:tphlclkmax) q <= d;
    end
  end

  always @ (*) begin
    if (~notpreset & notclear) begin
      #(tplhmin:tplhtyp:tplhmax) q <= 1;
    end else if (notpreset & ~notclear) begin
      #(tphlmin:tphltyp:tphlmax) q <= 0;
    end
  end

  always @ (q) begin
    notq <= ~q;
    c = c+1;
    $display("    Potencia disipada por el Flip Flop: %f", c * Cl * Vcc);
  end

endmodule
module ffD(
  input d,
  input clk,
  input notpreset,
  input notclear,
  output q,
  output notq
);

  wire d;
  wire clk;
  wire preset;
  wire clear;
  reg q;
  reg notq;


  parameter tplhmin = 1.5;
  parameter tplhtyp = 5.8;
  parameter tplhmax = 9.3;
  parameter tphlmin = 1.5;
  parameter tphltyp = 6.5;
  parameter tphlmax = 11.4;


  parameter tplhclkmin = 1.5;
  parameter tplhclktyp = 7.7;
  parameter tplhclkmax = 10.5;
  parameter tphlclkmin = 1.5;
  parameter tphlclktyp = 7.3;
  parameter tphlclkmax = 9.7;

  parameter Vcc = 3.3;
  parameter Cl = 0.05;

  integer c;
  initial c = 0;

  always @ (posedge clk) begin
    if (notpreset & notclear) begin
      if (d) # (tplhclkmin:tplhclktyp:tplhclkmax) q <= d;
      else # (tphlclkmin:tphlclktyp:tphlclkmax) q <= d;
    end
  end

  always @ (*) begin
    if (~notpreset & notclear) begin
      #(tplhmin:tplhtyp:tplhmax) q <= 1;
    end else if (notpreset & ~notclear) begin
      #(tphlmin:tphltyp:tphlmax) q <= 0;
    end
  end

  always @ (q) begin
    notq <= ~q;
    c = c+1;
    $display("    Potencia disipada por el Flip Flop: %f", c * Cl * Vcc);
  end

endmodule