data/full_repos/permissive/167489907/Memory/ROM/rom_case_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/ROM/rom_case_testbench.v:7: Unsupported: Ignoring delay on this delayed statement.\nalways #10 address = address + 1\'b1;  \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/ROM/rom_case_testbench.v:11: Unsupported: Ignoring delay on this delayed statement.\n #2560;  \n ^\n%Error: data/full_repos/permissive/167489907/Memory/ROM/rom_case_testbench.v:5: Cannot find file containing module: \'rom_case\'\nrom_case dut(.out(out), .address(address));  \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167489907/Memory/ROM,data/full_repos/permissive/167489907/rom_case\n             data/full_repos/permissive/167489907/Memory/ROM,data/full_repos/permissive/167489907/rom_case.v\n             data/full_repos/permissive/167489907/Memory/ROM,data/full_repos/permissive/167489907/rom_case.sv\n             rom_case\n             rom_case.v\n             rom_case.sv\n             obj_dir/rom_case\n             obj_dir/rom_case.v\n             obj_dir/rom_case.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rom_case_testbench;
reg [7:0] address;
wire [15:0] out;

rom_case dut(.out(out), .address(address));

always #10 address = address + 1'b1;

initial begin
	address = 8'b0;
	#2560;
	$stop;
end
endmodule
module rom_case_testbench;

reg [7:0] address;
wire [15:0] out;

rom_case dut(.out(out), .address(address));

always #10 address = address + 1'b1;

initial begin
	address = 8'b0;
	#2560;
	$stop;
end
endmodule