data/full_repos/permissive/162535776/src/skeleton.v
 line:101: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/162535776/src/skeleton.v:124: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                       : ... In instance skeleton\n reg [8:0] ADDR_WB_SD, ADDR_WB1, ADDR_WB2 = 8\'b0;\n                                            ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/162535776/src/skeleton.v:159: Cannot find file containing module: \'pll\'\n pll my_pll(CLOCK_50, CLOCK_10);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/162535776/src,data/full_repos/permissive/162535776/pll\n             data/full_repos/permissive/162535776/src,data/full_repos/permissive/162535776/pll.v\n             data/full_repos/permissive/162535776/src,data/full_repos/permissive/162535776/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/162535776/src/skeleton.v:164: Cannot find file containing module: \'Reset_Delay\'\n Reset_Delay   r0 (.iCLK(CLOCK_50),.oRESET(DLY_RST) );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/162535776/src/skeleton.v:165: Cannot find file containing module: \'VGA_Audio_PLL\'\n VGA_Audio_PLL   p1 (.areset(~DLY_RST),.inclk0(CLOCK_50),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(VGA_CLK) );\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162535776/src/skeleton.v:166: Cannot find file containing module: \'vga_controller\'\n vga_controller vga_ins(.iRST_n(DLY_RST),\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162535776/src/skeleton.v:178: Cannot find file containing module: \'DE2_Audio_Example\'\n DE2_Audio_Example my_audio(CLOCK_50, CLOCK_27, AUD_ADCDAT, AUD_BCLK, AUD_ADCLRCK, AUD_DACLRCK, I2C_SDAT, AUD_XCK, AUD_DACDAT, I2C_SCLK, \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162535776/src/skeleton.v:186: Cannot find file containing module: \'sd_controller\'\n sd_controller my_sd_controller(cs,  \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162535776/src/skeleton.v:226: Cannot find file containing module: \'write_buffer\'\n write_buffer my_write_buffer1(ADDR_WB_after1, CLOCK_50, note_data, buffer_select1, wb_out1);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162535776/src/skeleton.v:227: Cannot find file containing module: \'write_buffer\'\n write_buffer my_write_buffer2(ADDR_WB_after2, CLOCK_50, note_data, buffer_select2, wb_out2);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162535776/src/skeleton.v:548: Cannot find file containing module: \'read_buffer\'\n read_buffer my_read_buffer (ADDR_RB_SD, CLOCK_50, sd_note_data, mode_read, RB_write_enable, buffer_data); \n ^~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 1 warning(s)\n'
module skeleton(resetn, 
	VGA_CLK,
	VGA_HS,
	VGA_VS,
	VGA_BLANK,
	VGA_SYNC,
	VGA_R,
	VGA_G,
	VGA_B,
	CLOCK_50,
	CLOCK_27,

	AUD_ADCDAT,


	AUD_BCLK,
	AUD_ADCLRCK,
	AUD_DACLRCK,

	I2C_SDAT,


	AUD_XCK,
	AUD_DACDAT,

	I2C_SCLK,
	 c, csharp, d, dsharp, e, f, fsharp, g, gsharp, a, asharp, b, oct_up, oct_down,

	 cs, mosi, miso, sclk, sd_dat_1, sd_dat_2,

	 mode_write_enter, mode_write_exit, mode_read, mode_playalong, init_mode_read,

	 reset, status,
	 recv_data, CLOCK_IO, wr, rd, mode_write, csharp_in, wb_drain_complete1, wb_drain_complete2);  													
		

	output			VGA_CLK;
	output			VGA_HS;
	output			VGA_VS;
	output			VGA_BLANK;
	output			VGA_SYNC;
	output	[7:0]	VGA_R;
	output	[7:0]	VGA_G;
	output	[7:0]	VGA_B;
	input 			c, csharp, d, dsharp, e, f, fsharp, g, gsharp, a, asharp, b;
	input				CLOCK_50;
	input 			resetn;
		

	output reg mode_write = 1'b0;
	input mode_write_enter, mode_write_exit, mode_playalong, mode_read, init_mode_read;
	
	always @(posedge CLOCK_IO) begin
		if (~mode_write_enter) begin
			mode_write <= 1'b1;
		end
		else if (~mode_write_exit) begin
			mode_write <= 1'b0;
		end
	end
	

	input				CLOCK_27;
	input				AUD_ADCDAT;
	input 			oct_up, oct_down;

	inout				AUD_BCLK;
	inout				AUD_ADCLRCK;
	inout				AUD_DACLRCK;

	inout				I2C_SDAT;
	output			AUD_XCK;
	output			AUD_DACDAT;

	output			I2C_SCLK;
	

	input miso;
	output cs, mosi, sclk;
	output sd_dat_1, sd_dat_2;
	assign sd_dat_1 = 1'b1;
	assign sd_dat_2 = 1'b1;
	

	output [4:0] status;

	

	output reg rd = 1'b0;
	output reg wr = 1'b0;
	
	input reset;
	wire ready;
	
	wire [7:0] dout;
	wire byte_available, ready_for_next_byte;
	
	reg [7:0] din = 8'b0;
	
	reg [31:0] wr_address, rd_address = 32'b0;
	wire [31:0] address = (wr) ? wr_address : rd_address;
	

	reg [7:0] note_data = 8'b0;
	reg [3:0] note_next = 4'b1;
	
	reg c_read, csharp_read, d_read, dsharp_read, e_read, f_read, fsharp_read, g_read, gsharp_read, a_read, asharp_read, b_read = 1'b0;
	wire c_in = (mode_read) ? c_read : ~c;
	output wire csharp_in = (mode_read) ? csharp_read : ~csharp;
	wire d_in = (mode_read) ? d_read : ~d;
   wire dsharp_in = (mode_read) ? dsharp_read : ~dsharp;
   wire e_in = (mode_read) ? e_read : ~e;
   wire f_in = (mode_read) ? f_read : ~f;
	wire fsharp_in = (mode_read) ? fsharp_read : ~fsharp;
	wire g_in = (mode_read) ? g_read : ~g;
	wire gsharp_in = (mode_read) ? gsharp_read : ~gsharp;
	wire a_in = (mode_read) ? a_read : ~a;
	wire asharp_in = (mode_read) ? asharp_read : ~asharp;
   wire b_in = (mode_read) ? b_read : ~b;	
	

	wire [7:0] wb_out, wb_out1, wb_out2;
	reg [8:0] ADDR_WB_SD, ADDR_WB1, ADDR_WB2 = 8'b0;
	
	reg buffer_select1, buffer_select2 = 1'b0;
	reg wb_ready1, wb_ready2 = 1'b0;
	output reg wb_drain_complete1, wb_drain_complete2 = 1'b0;
	reg [7:0] sd_note_data = 8'b0;
	reg RB_write_enable = 1'b0;
	reg RB_read_enable = 1'b1;
	wire [7:0] buffer_data;
	reg [15:0] ADDR_RB_SD_read = 16'b0; 
	reg [15:0] ADDR_RB_SD_write = 16'b0; 
	wire [15:0] ADDR_RB_SD;
	

	integer count = 0;
	integer count_read = 0;
	wire CLOCK_10;
   output reg CLOCK_IO = 1'b0;
	reg CLOCK_READ = 1'b0;
	
	always @(posedge CLOCK_50) begin
		count_read = count_read + 1;
		if (count_read >= 8000000) begin
			count_read = 0;
			CLOCK_READ = ~CLOCK_READ;
		end
	end
	
	always @(posedge CLOCK_50) begin
		count = count + 1;
		if (count >= 2000000) begin
			count = 0;
			CLOCK_IO = ~CLOCK_IO;
		end
	end
	pll my_pll(CLOCK_50, CLOCK_10);
	

	wire note_pa_out;
	
	Reset_Delay			r0	(.iCLK(CLOCK_50),.oRESET(DLY_RST)	);
	VGA_Audio_PLL 		p1	(.areset(~DLY_RST),.inclk0(CLOCK_50),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(VGA_CLK)	);
	vga_controller vga_ins(.iRST_n(DLY_RST),
								 .iVGA_CLK(VGA_CLK),
								 .oBLANK_n(VGA_BLANK),
								 .oHS(VGA_HS),
								 .oVS(VGA_VS),
								 .b_data(VGA_B),
								 .g_data(VGA_G),
								 .r_data(VGA_R),
								 .c(c_in), .csharp(csharp_in), .d(d_in), .dsharp(dsharp_in), .e(e_in), .f(f_in), .fsharp(fsharp_in), .g(g_in), .gsharp(gsharp_in), .a(a_in), .asharp(asharp_in), .b(b_in),
								 .note_next_in(note_next), .isPlayAlong(mode_playalong), .note_pa_out(note_pa_out)); 
	

	DE2_Audio_Example my_audio(CLOCK_50, CLOCK_27, AUD_ADCDAT, AUD_BCLK, AUD_ADCLRCK, AUD_DACLRCK, I2C_SDAT, AUD_XCK, AUD_DACDAT, I2C_SCLK, 
		c_in, csharp_in, d_in, dsharp_in, e_in, f_in, fsharp_in, g_in, gsharp_in, a_in, asharp_in, b_in, oct_up, oct_down);
		

	wire [7:0] recv_data_dummy;
	output [7:0] recv_data;
	assign recv_data = buffer_data;
	
	sd_controller my_sd_controller(cs,
	mosi,
	miso,
   sclk,


	rd, dout, 
   byte_available,
	wr, din,
   ready_for_next_byte,

   reset,
   ready,
   address,

   CLOCK_10,
   status,
	recv_data_dummy
	);
	
	always @(posedge CLOCK_50) begin
		if (~c) note_data <= 8'd1;
		else if (~csharp) note_data <= 8'd2;
		else if (~d) note_data <= 8'd3;
		else if (~dsharp) note_data <= 8'd4;
		else if (~e) note_data <= 8'd5;
		else if (~f) note_data <= 8'd6;
		else if (~fsharp) note_data <= 8'd7;
		else if (~g) note_data <= 8'd8;
		else if (~gsharp) note_data <= 8'd9;
		else if (~a) note_data <= 8'd10;
		else if (~asharp) note_data <= 8'd11;
		else if (~b) note_data <= 8'd12;
		else note_data <= 8'd0;
	end
	

	wire [8:0] ADDR_WB_after1 = (wb_ready1) ? ADDR_WB_SD : ADDR_WB1;
	wire [8:0] ADDR_WB_after2 = (wb_ready2) ? ADDR_WB_SD : ADDR_WB2;
	
	write_buffer my_write_buffer1(ADDR_WB_after1, CLOCK_50, note_data, buffer_select1, wb_out1);
	write_buffer my_write_buffer2(ADDR_WB_after2, CLOCK_50, note_data, buffer_select2, wb_out2);

	always @(posedge CLOCK_IO) begin
		if (ADDR_WB1 > 510) ADDR_WB1 <= 0;
		else if (buffer_select1) ADDR_WB1 <= ADDR_WB1 + 1;
		if (ADDR_WB2 > 510) ADDR_WB2 <= 0;
		else if (buffer_select2) ADDR_WB2 <= ADDR_WB2 + 1;
	end

	always @(posedge CLOCK_10, negedge resetn) begin
		if (!resetn) begin
			wr <= 1'b0;
			wb_drain_complete1 <= 1'b0;
			wb_drain_complete2 <= 1'b0;
			ADDR_WB_SD <= 9'b0;
			wr_address <= 32'b0;
		end
		else if (wb_ready1) begin
			wr <= 1'b1;
			wb_drain_complete1 <= 1'b0;
			wb_drain_complete2 <= 1'b0;
			
			if (ready_for_next_byte) begin
				ADDR_WB_SD <= ADDR_WB_SD + 1;
				din <= wb_out1;
			end
			
			if (ADDR_WB_SD > 510) begin
				ADDR_WB_SD <= 9'b0;
				wb_drain_complete1 <= 1'b1;
				wr <= 1'b0;
				wr_address <= wr_address + 512;
			end
		
		end
		else if (wb_ready2) begin
			wr <= 1'b1;
			wb_drain_complete1 <= 1'b0;
			wb_drain_complete2 <= 1'b0;
			
			if (ready_for_next_byte) begin
				ADDR_WB_SD <= ADDR_WB_SD + 1;
				din <= wb_out2;
			end
			
			if (ADDR_WB_SD > 510) begin
				ADDR_WB_SD <= 9'b0;
				wb_drain_complete2 <= 1'b1;
				wr <= 1'b0;
				wr_address <= wr_address + 512;
			end
		
		end
	end

	always @(posedge CLOCK_50) begin
		if (!resetn) begin
			wb_ready1 <= 1'b0;
			wb_ready2 <= 1'b0;
			buffer_select1 <= 1'b0;
			buffer_select2 <= 1'b0;
		end
		if (wb_drain_complete1) wb_ready1 <= 1'b0;
		if (wb_drain_complete2) wb_ready2 <= 1'b0;
		if (mode_write && !buffer_select1 && !buffer_select2) begin
			buffer_select1 <= 1'b1;
			buffer_select2 <= 1'b0;
		end
		else if (mode_write && buffer_select1 && (ADDR_WB1 > 510)) begin
			buffer_select1 <= 1'b0;
			buffer_select2 <= 1'b1;
			wb_ready1 <= 1'b1;
			wb_ready2 <= 1'b0;
		end
		else if (mode_write && buffer_select2 && (ADDR_WB2 > 510)) begin
			buffer_select1 <= 1'b1;
			buffer_select2 <= 1'b0;
			wb_ready1 <= 1'b0;
			wb_ready2 <= 1'b1;
		end
		else if (!mode_write && buffer_select1 && !buffer_select2) begin
			buffer_select1 <= 1'b0;
			buffer_select2 <= 1'b0;
			wb_ready1 <= 1'b1;
			wb_ready2 <= 1'b0;
		end
		else if (!mode_write && !buffer_select1 && buffer_select2) begin
			buffer_select1 <= 1'b0;
			buffer_select2 <= 1'b0;
			wb_ready1 <= 1'b0;
			wb_ready2 <= 1'b1;
		end
		
	end
	

	always @(posedge CLOCK_50) begin
		rd <= init_mode_read; 
		RB_read_enable <= mode_read;
	end
	
	assign ADDR_RB_SD = (mode_read) ? ADDR_RB_SD_read : ADDR_RB_SD_write; 
	

	always @(posedge CLOCK_50) begin
		if (buffer_data == 1) begin
			c_read <= 1'b1;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 2) begin
			csharp_read <= 1'b1;
			c_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 3) begin
			d_read <= 1'b1;
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 4) begin
			dsharp_read <= 1'b1;
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 5) begin
			e_read <= 1'b1;
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 6) begin 
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b1;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 7) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b1;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 8) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b1;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 9) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b1;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 10) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b1;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 11) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b1;
			b_read <= 1'b0;
		end
		else if (buffer_data == 12) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b1;
		end
		else begin 
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
	end
	

	always @(posedge CLOCK_READ) begin
		if (mode_read) begin
			ADDR_RB_SD_read <= ADDR_RB_SD_read + 1; 
		end
		else begin 
			ADDR_RB_SD_read <= 16'd0;
		end
	end


	
	always @(posedge CLOCK_10) begin
		if (init_mode_read) begin
			if (byte_available) begin
				RB_write_enable <= 1'b1;
				sd_note_data <= dout;
				if (ADDR_RB_SD_write < 4096) ADDR_RB_SD_write <= ADDR_RB_SD_write + 1;
				if (ADDR_RB_SD_write % 512 > 510) begin

				end
			end
			
		end
		else begin
			ADDR_RB_SD_write <= 16'd0; 
			rd_address <= 32'd0;
			RB_write_enable <= 1'b0;
		end
	end
	
	read_buffer my_read_buffer (ADDR_RB_SD, CLOCK_50, sd_note_data, mode_read, RB_write_enable, buffer_data); 
	

		
	always @(posedge CLOCK_50) 
	begin
		if (note_pa_out) begin
			if (note_next == 1) note_next <= 3;
			else if (note_next == 3) note_next <= 5;
			else if (note_next == 5) note_next <= 6;
			else if (note_next == 6) note_next <= 8;
			else if (note_next == 8) note_next <= 10;
			else if (note_next == 10) note_next <= 12;
			else note_next <= 1;
		end
	end
	
endmodule
module skeleton(resetn, 
	VGA_CLK,
	VGA_HS,
	VGA_VS,
	VGA_BLANK,
	VGA_SYNC,
	VGA_R,
	VGA_G,
	VGA_B,
	CLOCK_50,
	CLOCK_27,

	AUD_ADCDAT,


	AUD_BCLK,
	AUD_ADCLRCK,
	AUD_DACLRCK,

	I2C_SDAT,


	AUD_XCK,
	AUD_DACDAT,

	I2C_SCLK,
	 c, csharp, d, dsharp, e, f, fsharp, g, gsharp, a, asharp, b, oct_up, oct_down,

	 cs, mosi, miso, sclk, sd_dat_1, sd_dat_2,

	 mode_write_enter, mode_write_exit, mode_read, mode_playalong, init_mode_read,

	 reset, status,
	 recv_data, CLOCK_IO, wr, rd, mode_write, csharp_in, wb_drain_complete1, wb_drain_complete2);
  													
		

	output			VGA_CLK;
	output			VGA_HS;
	output			VGA_VS;
	output			VGA_BLANK;
	output			VGA_SYNC;
	output	[7:0]	VGA_R;
	output	[7:0]	VGA_G;
	output	[7:0]	VGA_B;
	input 			c, csharp, d, dsharp, e, f, fsharp, g, gsharp, a, asharp, b;
	input				CLOCK_50;
	input 			resetn;
		

	output reg mode_write = 1'b0;
	input mode_write_enter, mode_write_exit, mode_playalong, mode_read, init_mode_read;
	
	always @(posedge CLOCK_IO) begin
		if (~mode_write_enter) begin
			mode_write <= 1'b1;
		end
		else if (~mode_write_exit) begin
			mode_write <= 1'b0;
		end
	end
	

	input				CLOCK_27;
	input				AUD_ADCDAT;
	input 			oct_up, oct_down;

	inout				AUD_BCLK;
	inout				AUD_ADCLRCK;
	inout				AUD_DACLRCK;

	inout				I2C_SDAT;
	output			AUD_XCK;
	output			AUD_DACDAT;

	output			I2C_SCLK;
	

	input miso;
	output cs, mosi, sclk;
	output sd_dat_1, sd_dat_2;
	assign sd_dat_1 = 1'b1;
	assign sd_dat_2 = 1'b1;
	

	output [4:0] status;

	

	output reg rd = 1'b0;
	output reg wr = 1'b0;
	
	input reset;
	wire ready;
	
	wire [7:0] dout;
	wire byte_available, ready_for_next_byte;
	
	reg [7:0] din = 8'b0;
	
	reg [31:0] wr_address, rd_address = 32'b0;
	wire [31:0] address = (wr) ? wr_address : rd_address;
	

	reg [7:0] note_data = 8'b0;
	reg [3:0] note_next = 4'b1;
	
	reg c_read, csharp_read, d_read, dsharp_read, e_read, f_read, fsharp_read, g_read, gsharp_read, a_read, asharp_read, b_read = 1'b0;
	wire c_in = (mode_read) ? c_read : ~c;
	output wire csharp_in = (mode_read) ? csharp_read : ~csharp;
	wire d_in = (mode_read) ? d_read : ~d;
   wire dsharp_in = (mode_read) ? dsharp_read : ~dsharp;
   wire e_in = (mode_read) ? e_read : ~e;
   wire f_in = (mode_read) ? f_read : ~f;
	wire fsharp_in = (mode_read) ? fsharp_read : ~fsharp;
	wire g_in = (mode_read) ? g_read : ~g;
	wire gsharp_in = (mode_read) ? gsharp_read : ~gsharp;
	wire a_in = (mode_read) ? a_read : ~a;
	wire asharp_in = (mode_read) ? asharp_read : ~asharp;
   wire b_in = (mode_read) ? b_read : ~b;	
	

	wire [7:0] wb_out, wb_out1, wb_out2;
	reg [8:0] ADDR_WB_SD, ADDR_WB1, ADDR_WB2 = 8'b0;
	
	reg buffer_select1, buffer_select2 = 1'b0;
	reg wb_ready1, wb_ready2 = 1'b0;
	output reg wb_drain_complete1, wb_drain_complete2 = 1'b0;
	reg [7:0] sd_note_data = 8'b0;
	reg RB_write_enable = 1'b0;
	reg RB_read_enable = 1'b1;
	wire [7:0] buffer_data;
	reg [15:0] ADDR_RB_SD_read = 16'b0; 
	reg [15:0] ADDR_RB_SD_write = 16'b0; 
	wire [15:0] ADDR_RB_SD;
	

	integer count = 0;
	integer count_read = 0;
	wire CLOCK_10;
   output reg CLOCK_IO = 1'b0;
	reg CLOCK_READ = 1'b0;
	
	always @(posedge CLOCK_50) begin
		count_read = count_read + 1;
		if (count_read >= 8000000) begin
			count_read = 0;
			CLOCK_READ = ~CLOCK_READ;
		end
	end
	
	always @(posedge CLOCK_50) begin
		count = count + 1;
		if (count >= 2000000) begin
			count = 0;
			CLOCK_IO = ~CLOCK_IO;
		end
	end
	pll my_pll(CLOCK_50, CLOCK_10);
	

	wire note_pa_out;
	
	Reset_Delay			r0	(.iCLK(CLOCK_50),.oRESET(DLY_RST)	);
	VGA_Audio_PLL 		p1	(.areset(~DLY_RST),.inclk0(CLOCK_50),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(VGA_CLK)	);
	vga_controller vga_ins(.iRST_n(DLY_RST),
								 .iVGA_CLK(VGA_CLK),
								 .oBLANK_n(VGA_BLANK),
								 .oHS(VGA_HS),
								 .oVS(VGA_VS),
								 .b_data(VGA_B),
								 .g_data(VGA_G),
								 .r_data(VGA_R),
								 .c(c_in), .csharp(csharp_in), .d(d_in), .dsharp(dsharp_in), .e(e_in), .f(f_in), .fsharp(fsharp_in), .g(g_in), .gsharp(gsharp_in), .a(a_in), .asharp(asharp_in), .b(b_in),
								 .note_next_in(note_next), .isPlayAlong(mode_playalong), .note_pa_out(note_pa_out)); 
	

	DE2_Audio_Example my_audio(CLOCK_50, CLOCK_27, AUD_ADCDAT, AUD_BCLK, AUD_ADCLRCK, AUD_DACLRCK, I2C_SDAT, AUD_XCK, AUD_DACDAT, I2C_SCLK, 
		c_in, csharp_in, d_in, dsharp_in, e_in, f_in, fsharp_in, g_in, gsharp_in, a_in, asharp_in, b_in, oct_up, oct_down);
		

	wire [7:0] recv_data_dummy;
	output [7:0] recv_data;
	assign recv_data = buffer_data;
	
	sd_controller my_sd_controller(cs,
	mosi,
	miso,
   sclk,


	rd, dout, 
   byte_available,
	wr, din,
   ready_for_next_byte,

   reset,
   ready,
   address,

   CLOCK_10,
   status,
	recv_data_dummy
	);
	
	always @(posedge CLOCK_50) begin
		if (~c) note_data <= 8'd1;
		else if (~csharp) note_data <= 8'd2;
		else if (~d) note_data <= 8'd3;
		else if (~dsharp) note_data <= 8'd4;
		else if (~e) note_data <= 8'd5;
		else if (~f) note_data <= 8'd6;
		else if (~fsharp) note_data <= 8'd7;
		else if (~g) note_data <= 8'd8;
		else if (~gsharp) note_data <= 8'd9;
		else if (~a) note_data <= 8'd10;
		else if (~asharp) note_data <= 8'd11;
		else if (~b) note_data <= 8'd12;
		else note_data <= 8'd0;
	end
	

	wire [8:0] ADDR_WB_after1 = (wb_ready1) ? ADDR_WB_SD : ADDR_WB1;
	wire [8:0] ADDR_WB_after2 = (wb_ready2) ? ADDR_WB_SD : ADDR_WB2;
	
	write_buffer my_write_buffer1(ADDR_WB_after1, CLOCK_50, note_data, buffer_select1, wb_out1);
	write_buffer my_write_buffer2(ADDR_WB_after2, CLOCK_50, note_data, buffer_select2, wb_out2);

	always @(posedge CLOCK_IO) begin
		if (ADDR_WB1 > 510) ADDR_WB1 <= 0;
		else if (buffer_select1) ADDR_WB1 <= ADDR_WB1 + 1;
		if (ADDR_WB2 > 510) ADDR_WB2 <= 0;
		else if (buffer_select2) ADDR_WB2 <= ADDR_WB2 + 1;
	end

	always @(posedge CLOCK_10, negedge resetn) begin
		if (!resetn) begin
			wr <= 1'b0;
			wb_drain_complete1 <= 1'b0;
			wb_drain_complete2 <= 1'b0;
			ADDR_WB_SD <= 9'b0;
			wr_address <= 32'b0;
		end
		else if (wb_ready1) begin
			wr <= 1'b1;
			wb_drain_complete1 <= 1'b0;
			wb_drain_complete2 <= 1'b0;
			
			if (ready_for_next_byte) begin
				ADDR_WB_SD <= ADDR_WB_SD + 1;
				din <= wb_out1;
			end
			
			if (ADDR_WB_SD > 510) begin
				ADDR_WB_SD <= 9'b0;
				wb_drain_complete1 <= 1'b1;
				wr <= 1'b0;
				wr_address <= wr_address + 512;
			end
		
		end
		else if (wb_ready2) begin
			wr <= 1'b1;
			wb_drain_complete1 <= 1'b0;
			wb_drain_complete2 <= 1'b0;
			
			if (ready_for_next_byte) begin
				ADDR_WB_SD <= ADDR_WB_SD + 1;
				din <= wb_out2;
			end
			
			if (ADDR_WB_SD > 510) begin
				ADDR_WB_SD <= 9'b0;
				wb_drain_complete2 <= 1'b1;
				wr <= 1'b0;
				wr_address <= wr_address + 512;
			end
		
		end
	end

	always @(posedge CLOCK_50) begin
		if (!resetn) begin
			wb_ready1 <= 1'b0;
			wb_ready2 <= 1'b0;
			buffer_select1 <= 1'b0;
			buffer_select2 <= 1'b0;
		end
		if (wb_drain_complete1) wb_ready1 <= 1'b0;
		if (wb_drain_complete2) wb_ready2 <= 1'b0;
		if (mode_write && !buffer_select1 && !buffer_select2) begin
			buffer_select1 <= 1'b1;
			buffer_select2 <= 1'b0;
		end
		else if (mode_write && buffer_select1 && (ADDR_WB1 > 510)) begin
			buffer_select1 <= 1'b0;
			buffer_select2 <= 1'b1;
			wb_ready1 <= 1'b1;
			wb_ready2 <= 1'b0;
		end
		else if (mode_write && buffer_select2 && (ADDR_WB2 > 510)) begin
			buffer_select1 <= 1'b1;
			buffer_select2 <= 1'b0;
			wb_ready1 <= 1'b0;
			wb_ready2 <= 1'b1;
		end
		else if (!mode_write && buffer_select1 && !buffer_select2) begin
			buffer_select1 <= 1'b0;
			buffer_select2 <= 1'b0;
			wb_ready1 <= 1'b1;
			wb_ready2 <= 1'b0;
		end
		else if (!mode_write && !buffer_select1 && buffer_select2) begin
			buffer_select1 <= 1'b0;
			buffer_select2 <= 1'b0;
			wb_ready1 <= 1'b0;
			wb_ready2 <= 1'b1;
		end
		
	end
	

	always @(posedge CLOCK_50) begin
		rd <= init_mode_read; 
		RB_read_enable <= mode_read;
	end
	
	assign ADDR_RB_SD = (mode_read) ? ADDR_RB_SD_read : ADDR_RB_SD_write; 
	

	always @(posedge CLOCK_50) begin
		if (buffer_data == 1) begin
			c_read <= 1'b1;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 2) begin
			csharp_read <= 1'b1;
			c_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 3) begin
			d_read <= 1'b1;
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 4) begin
			dsharp_read <= 1'b1;
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 5) begin
			e_read <= 1'b1;
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 6) begin 
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b1;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 7) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b1;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 8) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b1;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 9) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b1;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 10) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b1;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
		else if (buffer_data == 11) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b1;
			b_read <= 1'b0;
		end
		else if (buffer_data == 12) begin
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b1;
		end
		else begin 
			c_read <= 1'b0;
			csharp_read <= 1'b0;
			d_read <= 1'b0;
			dsharp_read <= 1'b0;
			e_read <= 1'b0;
			f_read <= 1'b0;
			fsharp_read <= 1'b0;
			g_read <= 1'b0;
			gsharp_read <= 1'b0;
			a_read <= 1'b0;
			asharp_read <= 1'b0;
			b_read <= 1'b0;
		end
	end
	

	always @(posedge CLOCK_READ) begin
		if (mode_read) begin
			ADDR_RB_SD_read <= ADDR_RB_SD_read + 1; 
		end
		else begin 
			ADDR_RB_SD_read <= 16'd0;
		end
	end


	
	always @(posedge CLOCK_10) begin
		if (init_mode_read) begin
			if (byte_available) begin
				RB_write_enable <= 1'b1;
				sd_note_data <= dout;
				if (ADDR_RB_SD_write < 4096) ADDR_RB_SD_write <= ADDR_RB_SD_write + 1;
				if (ADDR_RB_SD_write % 512 > 510) begin

				end
			end
			
		end
		else begin
			ADDR_RB_SD_write <= 16'd0; 
			rd_address <= 32'd0;
			RB_write_enable <= 1'b0;
		end
	end
	
	read_buffer my_read_buffer (ADDR_RB_SD, CLOCK_50, sd_note_data, mode_read, RB_write_enable, buffer_data); 
	

		
	always @(posedge CLOCK_50) 
	begin
		if (note_pa_out) begin
			if (note_next == 1) note_next <= 3;
			else if (note_next == 3) note_next <= 5;
			else if (note_next == 5) note_next <= 6;
			else if (note_next == 6) note_next <= 8;
			else if (note_next == 8) note_next <= 10;
			else if (note_next == 10) note_next <= 12;
			else note_next <= 1;
		end
	end
	
endmodule