data/full_repos/permissive/143278/ivltests/modparam.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:138: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:141: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:158: Unsupported: Ignoring delay on this delayed statement.\nalways #(5) clk = ~clk;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:134: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'b0_00;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:137: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'h1;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:140: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h2\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'h2;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:143: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'h3;\n        ^\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

parameter WIDTH=8;
reg			clk;
reg			we;
reg    [1:0]		addr;
reg   [WIDTH-1:0]		din;
reg			error;
wire  [WIDTH-1:0]		dout;

memory mem (clk, we, addr, din,  dout);

initial
  begin



    clk = 0;
    error =0;
    #3;
    we = 1;
    addr = 0;
    din = 32'b0_00;
    #10;
    addr = 1;
    din = 32'h1;
    #10;
    addr = 2;
    din = 32'h2;
    #10;
    addr = 3;
    din = 32'h3;
    #10;
    we = 0;
    addr = 0;
    #1;
    if(dout[7:0] !== 8'h00)
      begin
         $display("FAILED - Ram[0] not 0, is %h",dout[7:0]);
         error = 1;
      end
    if(error == 0)
      $display("PASSED");
    $finish ;
  end

always #(5) clk = ~clk;
endmodule
module top;


parameter WIDTH=8;
reg			clk;
reg			we;
reg    [1:0]		addr;
reg   [WIDTH-1:0]		din;
reg			error;
wire  [WIDTH-1:0]		dout;

memory mem (clk, we, addr, din,  dout);

initial
  begin



    clk = 0;
    error =0;
    #3;
    we = 1;
    addr = 0;
    din = 32'b0_00;
    #10;
    addr = 1;
    din = 32'h1;
    #10;
    addr = 2;
    din = 32'h2;
    #10;
    addr = 3;
    din = 32'h3;
    #10;
    we = 0;
    addr = 0;
    #1;
    if(dout[7:0] !== 8'h00)
      begin
         $display("FAILED - Ram[0] not 0, is %h",dout[7:0]);
         error = 1;
      end
    if(error == 0)
      $display("PASSED");
    $finish ;
  end

always #(5) clk = ~clk;
endmodule