data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:2: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:4: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:30: Define or directive not defined: \'`REG_IDX_W\'\n  wire [`REG_IDX_W - 1:0] wb_dest_reg;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:31: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] wb_dest_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:33: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] fe_pc;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:34: Define or directive not defined: \'`INSTR_W\'\n  reg [`INSTR_W - 1:0] fe_instr;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:36: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 1:0] id_pc;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:37: Define or directive not defined: \'`INSTR_W\'\n  wire [`INSTR_W - 1:0] id_instr;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:38: Define or directive not defined: \'`ALU_OP_W\'\n  wire [`ALU_OP_W - 1:0] id_alu_op;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:39: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] id_alu_data_a;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:40: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] id_alu_data_b;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:41: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] id_imm;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:42: Define or directive not defined: \'`MEM_OP_W\'\n  wire [`MEM_OP_W - 1:0] id_mem_op;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:43: Define or directive not defined: \'`DEST_SRC_W\'\n  wire [`DEST_SRC_W - 1:0] id_dest_src;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:44: Define or directive not defined: \'`REG_IDX_W\'\n  wire [`REG_IDX_W - 1:0] id_dest_reg;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:73: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 1:0] ex_pc;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:74: Define or directive not defined: \'`INSTR_W\'\n  wire [`INSTR_W - 1:0] ex_instr;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:75: Define or directive not defined: \'`DEST_SRC_W\'\n  wire [`DEST_SRC_W - 1:0] ex_dest_src;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:76: Define or directive not defined: \'`REG_IDX_W\'\n  wire [`REG_IDX_W - 1:0] ex_dest_reg;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:77: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] ex_alu_eval;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:78: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 1:0] ex_mem_req_addr;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:79: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] ex_mem_req_wr_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:81: Define or directive not defined: \'`MEM_COUNT_W\'\n  wire [`MEM_COUNT_W - 1:0] ex_mem_req_count;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:113: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] m1_mem_read;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:114: Define or directive not defined: \'`MEM_CODE_W\'\n  wire [`MEM_CODE_W - 1:0]  m1_res_code;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:128: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 1:0] me_pc;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:129: Define or directive not defined: \'`INSTR_W\'\n  wire [`INSTR_W - 1:0] me_instr;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:130: Define or directive not defined: \'`DEST_SRC_W\'\n  wire [`DEST_SRC_W - 1:0] me_dest_src;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:131: Define or directive not defined: \'`REG_IDX_W\'\n  wire [`REG_IDX_W - 1:0] me_dest_reg;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:132: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] me_dest_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:156: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 1:0] wb_pc;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:157: Define or directive not defined: \'`INSTR_W\'\n  wire [`INSTR_W - 1:0] wb_instr;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:180: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_pipeline_id_ex.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:181: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:196: Unsupported: Ignoring delay on this delayed statement.\n    #(RESET_DURATION * CLK_PERIOD);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:205: Define or directive not defined: \'`FUNCT3_ADD\'\n    fe_instr = {12\'hfff, 5\'b00000, `FUNCT3_ADD, 5\'b00001, `OPCODE_ITYPE};\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:205: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    fe_instr = {12\'hfff, 5\'b00000, `FUNCT3_ADD, 5\'b00001, `OPCODE_ITYPE};\n                                              ^\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:205: Define or directive not defined: \'`OPCODE_ITYPE\'\n    fe_instr = {12\'hfff, 5\'b00000, `FUNCT3_ADD, 5\'b00001, `OPCODE_ITYPE};\n                                                          ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:207: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD);\n    ^\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:210: Define or directive not defined: \'`FUNCT3_ADD\'\n    fe_instr = {12\'h000, 5\'b00000, `FUNCT3_ADD, 5\'b00000, `OPCODE_ITYPE};\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:210: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    fe_instr = {12\'h000, 5\'b00000, `FUNCT3_ADD, 5\'b00000, `OPCODE_ITYPE};\n                                              ^\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:210: Define or directive not defined: \'`OPCODE_ITYPE\'\n    fe_instr = {12\'h000, 5\'b00000, `FUNCT3_ADD, 5\'b00000, `OPCODE_ITYPE};\n                                                          ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:212: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD);\n    ^\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:214: Define or directive not defined: \'`FUNCT3_ADD\'\n    fe_instr = {12\'h002, 5\'b00001, `FUNCT3_ADD, 5\'b00010, `OPCODE_ITYPE};\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:214: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    fe_instr = {12\'h002, 5\'b00001, `FUNCT3_ADD, 5\'b00010, `OPCODE_ITYPE};\n                                              ^\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:214: Define or directive not defined: \'`OPCODE_ITYPE\'\n    fe_instr = {12\'h002, 5\'b00001, `FUNCT3_ADD, 5\'b00010, `OPCODE_ITYPE};\n                                                          ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:216: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD * 5);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline_id_ex.v:222: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD / 2);\n    ^\n%Error: Exiting due to 45 error(s), 5 warning(s)\n'
module tb_pipeline_id_ex;

  localparam CLK_PERIOD = 2;
  localparam RESET_DURATION = 4;

  reg clk;
  reg rf_aresetn;
  
  reg fe_clr;
  reg fe_stall;

  reg id_clr;
  reg id_stall;
  
  reg ex_clr;
  reg ex_stall;

  reg me_clr;
  reg me_stall;

  reg wb_clr;
  reg wb_stall;

  wire wb_dest_en;
  wire [`REG_IDX_W - 1:0] wb_dest_reg;
  wire [`WORD_W - 1:0] wb_dest_data;

  reg [`ADDR_W - 1:0] fe_pc;
  reg [`INSTR_W - 1:0] fe_instr;

  wire [`ADDR_W - 1:0] id_pc;
  wire [`INSTR_W - 1:0] id_instr;
  wire [`ALU_OP_W - 1:0] id_alu_op;
  wire [`WORD_W - 1:0] id_alu_data_a;
  wire [`WORD_W - 1:0] id_alu_data_b;
  wire [`WORD_W - 1:0] id_imm;
  wire [`MEM_OP_W - 1:0] id_mem_op;
  wire [`DEST_SRC_W - 1:0] id_dest_src;
  wire [`REG_IDX_W - 1:0] id_dest_reg;
  id p1(
    .clk(clk),
    .clr(id_clr),
    .stall(id_stall),
    .rf_reset(rf_aresetn),

    .i_pc(fe_pc),
    .i_instr(fe_instr),

    .i_wb_dest_en(wb_dest_en),
    .i_wb_dest_reg(wb_dest_reg),
    .i_wb_dest_data(wb_dest_data),

    .o_pc(id_pc),
    .o_instr(id_instr),

    .o_alu_op(id_alu_op),
    
    .o_alu_data_a(id_alu_data_a),
    .o_alu_data_b(id_alu_data_b),
    .o_imm(id_imm),

    .o_mem_op(id_mem_op),

    .o_dest_src(id_dest_src),
    .o_dest_reg(id_dest_reg)
  );

  wire [`ADDR_W - 1:0] ex_pc;
  wire [`INSTR_W - 1:0] ex_instr;
  wire [`DEST_SRC_W - 1:0] ex_dest_src;
  wire [`REG_IDX_W - 1:0] ex_dest_reg;
  wire [`WORD_W - 1:0] ex_alu_eval;
  wire [`ADDR_W - 1:0] ex_mem_req_addr;
  wire [`WORD_W - 1:0] ex_mem_req_wr_data;
  wire ex_mem_req_wr_en;
  wire [`MEM_COUNT_W - 1:0] ex_mem_req_count;
  ex p2(
    .clk(clk),
    .clr(ex_clr),
    .stall(ex_stall),

    .i_pc(id_pc),
    .i_instr(id_instr),

    .i_alu_op(id_alu_op),

    .i_alu_data_a(id_alu_data_a),
    .i_alu_data_b(id_alu_data_b),
    .i_imm(id_imm),

    .i_dest_src(id_dest_src),
    .i_dest_reg(id_dest_reg),

    .o_pc(ex_pc),
    .o_instr(ex_instr),

    .o_dest_src(ex_dest_src),
    .o_dest_reg(ex_dest_reg),

    .o_alu_eval(ex_alu_eval),

    .o_mem_req_addr(ex_mem_req_addr),
    .o_mem_req_wr_data(ex_mem_req_wr_data),
    .o_mem_req_wr_en(ex_mem_req_wr_en),
    .o_mem_req_count(ex_mem_req_count)
  );
  
  wire [`WORD_W - 1:0] m1_mem_read;
  wire [`MEM_CODE_W - 1:0]  m1_res_code;
  memory_interface m1(
    .clk(clk),
    .aresetn(rf_aresetn),

    .i_req_addr(ex_mem_req_addr),
    .i_req_wr_data(ex_mem_req_wr_data),
    .i_req_wr_en(ex_mem_req_wr_en),
    .i_req_count(ex_mem_req_count),

    .o_res_rd_data(m1_mem_read),
    .o_res_code(m1_res_code)
  );

  wire [`ADDR_W - 1:0] me_pc;
  wire [`INSTR_W - 1:0] me_instr;
  wire [`DEST_SRC_W - 1:0] me_dest_src;
  wire [`REG_IDX_W - 1:0] me_dest_reg;
  wire [`WORD_W - 1:0] me_dest_data;
  me p3(
    .clk(clk),
    .clr(me_clr),
    .stall(me_stall),

    .i_pc(ex_pc),
    .i_instr(ex_instr),
    
    .i_dest_src(ex_dest_src),
    .i_dest_reg(ex_dest_reg),

    .i_alu_eval(ex_alu_eval),
    .i_mem_read(m1_mem_read),

    .o_pc(me_pc),
    .o_instr(me_instr),

    .o_dest_src(me_dest_src),
    .o_dest_reg(me_dest_reg),

    .o_dest_data(me_dest_data)
  );

  wire [`ADDR_W - 1:0] wb_pc;
  wire [`INSTR_W - 1:0] wb_instr;
  wb p4(
    .clk(clk),
    .clr(wb_clr),

    .i_pc(me_pc),
    .i_instr(me_instr),

    .i_dest_src(me_dest_src),
    .i_dest_reg(me_dest_reg),

    .i_dest_data(me_dest_data),

    .o_pc(wb_pc),
    .o_instr(wb_instr),

    .o_dest_en(wb_dest_en),
    .o_dest_reg(wb_dest_reg),
    .o_dest_data(wb_dest_data)
  );

  initial begin

    $dumpfile("tb_pipeline_id_ex.vcd");
    $dumpvars;
    
    clk = 0;
    rf_aresetn = 0;
    fe_clr = 1;
    fe_stall = 0;
    id_clr = 1;
    id_stall = 0;
    ex_clr = 1;
    ex_stall = 0;
    me_clr = 1;
    me_stall = 0;
    wb_clr = 1;
    wb_stall = 0;

    #(RESET_DURATION * CLK_PERIOD);

    rf_aresetn = 1;
    fe_clr = 0;
    id_clr = 0;
    ex_clr = 0;
    me_clr = 0;
    wb_clr = 0;

    fe_instr = {12'hfff, 5'b00000, `FUNCT3_ADD, 5'b00001, `OPCODE_ITYPE};
    
    #(CLK_PERIOD);


    fe_instr = {12'h000, 5'b00000, `FUNCT3_ADD, 5'b00000, `OPCODE_ITYPE};

    #(CLK_PERIOD);

    fe_instr = {12'h002, 5'b00001, `FUNCT3_ADD, 5'b00010, `OPCODE_ITYPE};

    #(CLK_PERIOD * 5);

    $finish;
  end

  always begin
    #(CLK_PERIOD / 2);
    clk = ~clk;
  end

endmodule
module tb_pipeline_id_ex;


  localparam CLK_PERIOD = 2;
  localparam RESET_DURATION = 4;

  reg clk;
  reg rf_aresetn;
  
  reg fe_clr;
  reg fe_stall;

  reg id_clr;
  reg id_stall;
  
  reg ex_clr;
  reg ex_stall;

  reg me_clr;
  reg me_stall;

  reg wb_clr;
  reg wb_stall;

  wire wb_dest_en;
  wire [`REG_IDX_W - 1:0] wb_dest_reg;
  wire [`WORD_W - 1:0] wb_dest_data;

  reg [`ADDR_W - 1:0] fe_pc;
  reg [`INSTR_W - 1:0] fe_instr;

  wire [`ADDR_W - 1:0] id_pc;
  wire [`INSTR_W - 1:0] id_instr;
  wire [`ALU_OP_W - 1:0] id_alu_op;
  wire [`WORD_W - 1:0] id_alu_data_a;
  wire [`WORD_W - 1:0] id_alu_data_b;
  wire [`WORD_W - 1:0] id_imm;
  wire [`MEM_OP_W - 1:0] id_mem_op;
  wire [`DEST_SRC_W - 1:0] id_dest_src;
  wire [`REG_IDX_W - 1:0] id_dest_reg;
  id p1(
    .clk(clk),
    .clr(id_clr),
    .stall(id_stall),
    .rf_reset(rf_aresetn),

    .i_pc(fe_pc),
    .i_instr(fe_instr),

    .i_wb_dest_en(wb_dest_en),
    .i_wb_dest_reg(wb_dest_reg),
    .i_wb_dest_data(wb_dest_data),

    .o_pc(id_pc),
    .o_instr(id_instr),

    .o_alu_op(id_alu_op),
    
    .o_alu_data_a(id_alu_data_a),
    .o_alu_data_b(id_alu_data_b),
    .o_imm(id_imm),

    .o_mem_op(id_mem_op),

    .o_dest_src(id_dest_src),
    .o_dest_reg(id_dest_reg)
  );

  wire [`ADDR_W - 1:0] ex_pc;
  wire [`INSTR_W - 1:0] ex_instr;
  wire [`DEST_SRC_W - 1:0] ex_dest_src;
  wire [`REG_IDX_W - 1:0] ex_dest_reg;
  wire [`WORD_W - 1:0] ex_alu_eval;
  wire [`ADDR_W - 1:0] ex_mem_req_addr;
  wire [`WORD_W - 1:0] ex_mem_req_wr_data;
  wire ex_mem_req_wr_en;
  wire [`MEM_COUNT_W - 1:0] ex_mem_req_count;
  ex p2(
    .clk(clk),
    .clr(ex_clr),
    .stall(ex_stall),

    .i_pc(id_pc),
    .i_instr(id_instr),

    .i_alu_op(id_alu_op),

    .i_alu_data_a(id_alu_data_a),
    .i_alu_data_b(id_alu_data_b),
    .i_imm(id_imm),

    .i_dest_src(id_dest_src),
    .i_dest_reg(id_dest_reg),

    .o_pc(ex_pc),
    .o_instr(ex_instr),

    .o_dest_src(ex_dest_src),
    .o_dest_reg(ex_dest_reg),

    .o_alu_eval(ex_alu_eval),

    .o_mem_req_addr(ex_mem_req_addr),
    .o_mem_req_wr_data(ex_mem_req_wr_data),
    .o_mem_req_wr_en(ex_mem_req_wr_en),
    .o_mem_req_count(ex_mem_req_count)
  );
  
  wire [`WORD_W - 1:0] m1_mem_read;
  wire [`MEM_CODE_W - 1:0]  m1_res_code;
  memory_interface m1(
    .clk(clk),
    .aresetn(rf_aresetn),

    .i_req_addr(ex_mem_req_addr),
    .i_req_wr_data(ex_mem_req_wr_data),
    .i_req_wr_en(ex_mem_req_wr_en),
    .i_req_count(ex_mem_req_count),

    .o_res_rd_data(m1_mem_read),
    .o_res_code(m1_res_code)
  );

  wire [`ADDR_W - 1:0] me_pc;
  wire [`INSTR_W - 1:0] me_instr;
  wire [`DEST_SRC_W - 1:0] me_dest_src;
  wire [`REG_IDX_W - 1:0] me_dest_reg;
  wire [`WORD_W - 1:0] me_dest_data;
  me p3(
    .clk(clk),
    .clr(me_clr),
    .stall(me_stall),

    .i_pc(ex_pc),
    .i_instr(ex_instr),
    
    .i_dest_src(ex_dest_src),
    .i_dest_reg(ex_dest_reg),

    .i_alu_eval(ex_alu_eval),
    .i_mem_read(m1_mem_read),

    .o_pc(me_pc),
    .o_instr(me_instr),

    .o_dest_src(me_dest_src),
    .o_dest_reg(me_dest_reg),

    .o_dest_data(me_dest_data)
  );

  wire [`ADDR_W - 1:0] wb_pc;
  wire [`INSTR_W - 1:0] wb_instr;
  wb p4(
    .clk(clk),
    .clr(wb_clr),

    .i_pc(me_pc),
    .i_instr(me_instr),

    .i_dest_src(me_dest_src),
    .i_dest_reg(me_dest_reg),

    .i_dest_data(me_dest_data),

    .o_pc(wb_pc),
    .o_instr(wb_instr),

    .o_dest_en(wb_dest_en),
    .o_dest_reg(wb_dest_reg),
    .o_dest_data(wb_dest_data)
  );

  initial begin

    $dumpfile("tb_pipeline_id_ex.vcd");
    $dumpvars;
    
    clk = 0;
    rf_aresetn = 0;
    fe_clr = 1;
    fe_stall = 0;
    id_clr = 1;
    id_stall = 0;
    ex_clr = 1;
    ex_stall = 0;
    me_clr = 1;
    me_stall = 0;
    wb_clr = 1;
    wb_stall = 0;

    #(RESET_DURATION * CLK_PERIOD);

    rf_aresetn = 1;
    fe_clr = 0;
    id_clr = 0;
    ex_clr = 0;
    me_clr = 0;
    wb_clr = 0;

    fe_instr = {12'hfff, 5'b00000, `FUNCT3_ADD, 5'b00001, `OPCODE_ITYPE};
    
    #(CLK_PERIOD);


    fe_instr = {12'h000, 5'b00000, `FUNCT3_ADD, 5'b00000, `OPCODE_ITYPE};

    #(CLK_PERIOD);

    fe_instr = {12'h002, 5'b00001, `FUNCT3_ADD, 5'b00010, `OPCODE_ITYPE};

    #(CLK_PERIOD * 5);

    $finish;
  end

  always begin
    #(CLK_PERIOD / 2);
    clk = ~clk;
  end

endmodule