data/full_repos/permissive/18921956/DigitalDesign/Final/ProgramCounter.v
data/verilator_xmls/2a2395f5-3ccd-4128-8b56-0158d865a77c.xml
module ProgramCounter (
    output reg          [31:0] PC_o,
    input               PC_cen,
    input               PC_wen,
    input               [31:0] PC_write,
    input               clk,
    input               reset_n
);

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            PC_o <= 32'b0;
        end else begin
            if (PC_cen) begin
                PC_o <= PC_o + 32'b1;
            end else if (PC_wen) begin
                PC_o <= PC_write;
            end else begin
                PC_o <= PC_o;
            end
        end
    end
    
endmodule
module ProgramCounter (
    output reg          [31:0] PC_o,
    input               PC_cen,
    input               PC_wen,
    input               [31:0] PC_write,
    input               clk,
    input               reset_n
);


    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            PC_o <= 32'b0;
        end else begin
            if (PC_cen) begin
                PC_o <= PC_o + 32'b1;
            end else if (PC_wen) begin
                PC_o <= PC_write;
            end else begin
                PC_o <= PC_o;
            end
        end
    end
    
endmodule