data/full_repos/permissive/170365068/Single verilog file/mipsFull.v
1: b'%Error: Cannot find file containing module: verilog\n        ... Looked in:\n             data/full_repos/permissive/170365068/Single/verilog\n             data/full_repos/permissive/170365068/Single/verilog.v\n             data/full_repos/permissive/170365068/Single/verilog.sv\n             verilog\n             verilog.v\n             verilog.sv\n             obj_dir/verilog\n             obj_dir/verilog.v\n             obj_dir/verilog.sv\n%Error: Cannot find file containing module: file,data/full_repos/permissive/170365068\n%Error: Cannot find file containing module: data/full_repos/permissive/170365068/Single\n%Error: Cannot find file containing module: file/mipsFull.v\n%Error: Exiting due to 4 error(s)\n'
module ALU(A,B,ALUCon,Zero,ALUResult);
	
	input [31:0] A,B;
	input [3:0] ALUCon;
	
	output reg [31:0] ALUResult;
	output reg Zero;
	
	always@(*)
	begin
		case(ALUCon)
			4'b0010: ALUResult=A+B;
			4'b0110: ALUResult=A-B;
			4'b0000: ALUResult=A & B;
			4'b0001: ALUResult=A | B;
			4'b0111: ALUResult=(A<B);
			4'b0011: ALUResult=~(A | B);
			default: ALUResult=A+B;
		endcase 
		Zero =(ALUResult==0);	
	end
endmodule
module ALU(A,B,ALUCon,Zero,ALUResult);

	
	input [31:0] A,B;
	input [3:0] ALUCon;
	
	output reg [31:0] ALUResult;
	output reg Zero;
	
	always@(*)
	begin
		case(ALUCon)
			4'b0010: ALUResult=A+B;
			4'b0110: ALUResult=A-B;
			4'b0000: ALUResult=A & B;
			4'b0001: ALUResult=A | B;
			4'b0111: ALUResult=(A<B);
			4'b0011: ALUResult=~(A | B);
			default: ALUResult=A+B;
		endcase 
		Zero =(ALUResult==0);	
	end
endmodule