data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/pc.v
1: b'%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/pc.v:2: Cannot find include file: definitions.vh\n`include "definitions.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh.v\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh.sv\n             definitions.vh\n             definitions.vh.v\n             definitions.vh.sv\n             obj_dir/definitions.vh\n             obj_dir/definitions.vh.v\n             obj_dir/definitions.vh.sv\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/pc.v:23: Define or directive not defined: \'`INIT_32\'\n        pc <= `INIT_32;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/pc.v:23: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        pc <= `INIT_32;\n                      ^\n%Error: Exiting due to 3 error(s)\n'
module pc(
           input  wire       clk,
           input  wire       rst,
           input  wire[31:0] npc,

           input  wire[3:0]  stall_C,

           output reg[31:0]  pc
       );

always @ (posedge clk or posedge rst) begin
    if (rst) begin
        pc <= `INIT_32;
    end
    else if(stall_C[0] == 0) begin
        pc <= npc;
    end
    else begin

    end
end
endmodule
module pc(
           input  wire       clk,
           input  wire       rst,
           input  wire[31:0] npc,

           input  wire[3:0]  stall_C,

           output reg[31:0]  pc
       );


always @ (posedge clk or posedge rst) begin
    if (rst) begin
        pc <= `INIT_32;
    end
    else if(stall_C[0] == 0) begin
        pc <= npc;
    end
    else begin

    end
end
endmodule