data/full_repos/permissive/127311496/src/platform/N4DDR/DDR2_wsWrapper.v
1: b"%Error: data/full_repos/permissive/127311496/src/platform/N4DDR/DDR2_wsWrapper.v:49: Cannot find file containing module: 'ClockGen_DDR'\n ClockGen_DDR clockGen(.clk_in1(clkIn), .sysClk(sysClk), .refClk(refClk));\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/platform/N4DDR,data/full_repos/permissive/127311496/ClockGen_DDR\n             data/full_repos/permissive/127311496/src/platform/N4DDR,data/full_repos/permissive/127311496/ClockGen_DDR.v\n             data/full_repos/permissive/127311496/src/platform/N4DDR,data/full_repos/permissive/127311496/ClockGen_DDR.sv\n             ClockGen_DDR\n             ClockGen_DDR.v\n             ClockGen_DDR.sv\n             obj_dir/ClockGen_DDR\n             obj_dir/ClockGen_DDR.v\n             obj_dir/ClockGen_DDR.sv\n%Error: data/full_repos/permissive/127311496/src/platform/N4DDR/DDR2_wsWrapper.v:161: Cannot find file containing module: 'DDR'\n DDR ddr_inst(\n ^~~\n%Error: Exiting due to 2 error(s)\n"
module DDR2_wsWrapper(
	input clkIn, input rst, output clkOut,

	input [31:0] ws_addr, input [511:0] ws_din,
	input [63:0] ws_dm, input ws_cyc, input ws_stb, input ws_we,
	output reg ws_ack, output [511:0] ws_dout,
	

	output [2:0] dbg_state,
	

	output [12:0] ddr2_addr,
	output [2:0] ddr2_ba,
	output ddr2_cas_n,
	output [0:0] ddr2_ck_n,
	output [0:0] ddr2_ck_p,
	output [0:0] ddr2_cke,
	output ddr2_ras_n,

	output ddr2_we_n,
	inout [15:0] ddr2_dq,
	inout [1:0] ddr2_dqs_n,
	inout [1:0] ddr2_dqs_p,
	output ddr2_cs_n,
	output [1:0] ddr2_dm,
	output [0:0] ddr2_odt
);
	wire sysClk, refClk;
	ClockGen_DDR clockGen(.clk_in1(clkIn), .sysClk(sysClk), .refClk(refClk));
	
	localparam MEM_READ = 3'b001;
	localparam MEM_WRITE = 3'b000;
	
	reg [20:0] addr_reg;
	reg [1:0] addrLow = 2'b00;
	reg [511:0] rdData;
	reg [511:0] wrData;
	reg [63:0] wrDm;
	
	localparam STATE_READY = 3'b000;
	localparam STATE_READ = 3'b001;
	localparam STATE_READ_WAIT = 3'b010;
	localparam STATE_WRITE_DATA = 3'b011;
	localparam STATE_WRITE_CMD = 3'b100;
	localparam STATE_WS_END = 3'b111;
	reg [2:0] state = STATE_READY;
	
	wire [26:0] app_addr;
	wire [2:0] app_cmd;
	wire app_en;
	wire app_rdy;
	
	reg [127:0] app_wdf_data;
	reg [15:0] app_wdf_mask;
	wire app_wdf_end;
	wire app_wdf_wren;
	wire app_wdf_rdy;
	
	wire [127:0] app_rd_data;
	wire app_rd_data_valid;
	
	always @ (posedge clkOut)
	case(state)
	STATE_READY: begin
		addrLow <= 2'b00;
		if(ws_cyc & ws_stb)
		begin
			addr_reg <= ws_addr[26:6];
			if(ws_we)
			begin
				state <= STATE_WRITE_DATA;
				wrData <= ws_din;
				wrDm <= ws_dm;
				ws_ack <= 1'b1;
			end
			else
				state <= STATE_READ;
		end
	end
	STATE_WRITE_DATA: begin
		ws_ack <= 1'b0;
		if(app_wdf_rdy)
		begin
			addrLow <= addrLow + 1'b1;
			if(addrLow == 2'b11)
				state <= STATE_WRITE_CMD;
		end
	end
	STATE_WRITE_CMD: begin
		if(app_rdy)
		begin
			addrLow <= addrLow + 1'b1;
			if(addrLow == 2'b11)
				state <= STATE_READY;
		end
	end
	STATE_READ: begin
		if(app_rdy)
		begin
			addrLow <= addrLow + 1'b1;
			if(addrLow == 2'b11)
				state <= STATE_READ_WAIT;
		end
	end
	STATE_READ_WAIT: begin
		if(app_rd_data_valid)
		begin
			addrLow <= addrLow + 1'b1;
			rdData <= {app_rd_data, rdData[511:128]};
			if(addrLow == 2'b11)
			begin
				state <= STATE_WS_END;
				ws_ack <= 1'b1;
			end
		end
	end
	STATE_WS_END: begin
		ws_ack <= 1'b0;
		state <= STATE_READY;
	end
	default: state <= STATE_READY;
	endcase
	
	assign app_en = (state == STATE_WRITE_CMD) | (state == STATE_READ);
	assign app_wdf_wren = (state == STATE_WRITE_DATA);
	assign app_wdf_end = app_wdf_wren;
	assign app_cmd = (state == STATE_WRITE_CMD)? MEM_WRITE: MEM_READ;

	assign app_addr = {1'b0, addr_reg, addrLow, 3'h0};
	
	assign ws_dout = rdData;
	
	always @*
	case(addrLow)
	2'b00: begin app_wdf_data <= wrData[127:  0]; app_wdf_mask <= wrDm[15: 0]; end
	2'b01: begin app_wdf_data <= wrData[255:128]; app_wdf_mask <= wrDm[31:16]; end
	2'b10: begin app_wdf_data <= wrData[383:256]; app_wdf_mask <= wrDm[47:32]; end
	2'b11: begin app_wdf_data <= wrData[511:384]; app_wdf_mask <= wrDm[63:48]; end
	endcase
	
	DDR ddr_inst(
		.ddr2_addr(ddr2_addr),
		.ddr2_ba(ddr2_ba),
		.ddr2_cas_n(ddr2_cas_n),
		.ddr2_ck_n(ddr2_ck_n),
		.ddr2_ck_p(ddr2_ck_p),
		.ddr2_cke(ddr2_cke),
		.ddr2_ras_n(ddr2_ras_n),

		.ddr2_we_n(ddr2_we_n),
		.ddr2_dq(ddr2_dq),
		.ddr2_dqs_n(ddr2_dqs_n),
		.ddr2_dqs_p(ddr2_dqs_p),
		.ddr2_cs_n(ddr2_cs_n),
		.ddr2_dm(ddr2_dm),
		.ddr2_odt(ddr2_odt),
		.init_calib_complete(init_calib_comp),

		.app_addr(app_addr),
		.app_cmd(app_cmd),
		.app_en(app_en),
		.app_rdy(app_rdy),

		.app_wdf_data(app_wdf_data),
		.app_wdf_end(app_wdf_end),
		.app_wdf_wren(app_wdf_wren),
	    .app_wdf_mask(~app_wdf_mask),
		.app_wdf_rdy(app_wdf_rdy),

		.app_rd_data(app_rd_data),
		.app_rd_data_end(),
		.app_rd_data_valid(app_rd_data_valid),

		.app_sr_req(1'b0),
		.app_ref_req(1'b0),
		.app_zq_req(1'b0),
		.app_sr_active(),
		.app_ref_ack(),
		.app_zq_ack(),

		.sys_clk_i(sysClk),
		.clk_ref_i(refClk),
		.ui_clk(clkOut),
		.sys_rst(0),
		.ui_clk_sync_rst()
	);
	
	assign dbg_state = state;
	





	
endmodule
module DDR2_wsWrapper(
	input clkIn, input rst, output clkOut,

	input [31:0] ws_addr, input [511:0] ws_din,
	input [63:0] ws_dm, input ws_cyc, input ws_stb, input ws_we,
	output reg ws_ack, output [511:0] ws_dout,
	

	output [2:0] dbg_state,
	

	output [12:0] ddr2_addr,
	output [2:0] ddr2_ba,
	output ddr2_cas_n,
	output [0:0] ddr2_ck_n,
	output [0:0] ddr2_ck_p,
	output [0:0] ddr2_cke,
	output ddr2_ras_n,

	output ddr2_we_n,
	inout [15:0] ddr2_dq,
	inout [1:0] ddr2_dqs_n,
	inout [1:0] ddr2_dqs_p,
	output ddr2_cs_n,
	output [1:0] ddr2_dm,
	output [0:0] ddr2_odt
);

	wire sysClk, refClk;
	ClockGen_DDR clockGen(.clk_in1(clkIn), .sysClk(sysClk), .refClk(refClk));
	
	localparam MEM_READ = 3'b001;
	localparam MEM_WRITE = 3'b000;
	
	reg [20:0] addr_reg;
	reg [1:0] addrLow = 2'b00;
	reg [511:0] rdData;
	reg [511:0] wrData;
	reg [63:0] wrDm;
	
	localparam STATE_READY = 3'b000;
	localparam STATE_READ = 3'b001;
	localparam STATE_READ_WAIT = 3'b010;
	localparam STATE_WRITE_DATA = 3'b011;
	localparam STATE_WRITE_CMD = 3'b100;
	localparam STATE_WS_END = 3'b111;
	reg [2:0] state = STATE_READY;
	
	wire [26:0] app_addr;
	wire [2:0] app_cmd;
	wire app_en;
	wire app_rdy;
	
	reg [127:0] app_wdf_data;
	reg [15:0] app_wdf_mask;
	wire app_wdf_end;
	wire app_wdf_wren;
	wire app_wdf_rdy;
	
	wire [127:0] app_rd_data;
	wire app_rd_data_valid;
	
	always @ (posedge clkOut)
	case(state)
	STATE_READY: begin
		addrLow <= 2'b00;
		if(ws_cyc & ws_stb)
		begin
			addr_reg <= ws_addr[26:6];
			if(ws_we)
			begin
				state <= STATE_WRITE_DATA;
				wrData <= ws_din;
				wrDm <= ws_dm;
				ws_ack <= 1'b1;
			end
			else
				state <= STATE_READ;
		end
	end
	STATE_WRITE_DATA: begin
		ws_ack <= 1'b0;
		if(app_wdf_rdy)
		begin
			addrLow <= addrLow + 1'b1;
			if(addrLow == 2'b11)
				state <= STATE_WRITE_CMD;
		end
	end
	STATE_WRITE_CMD: begin
		if(app_rdy)
		begin
			addrLow <= addrLow + 1'b1;
			if(addrLow == 2'b11)
				state <= STATE_READY;
		end
	end
	STATE_READ: begin
		if(app_rdy)
		begin
			addrLow <= addrLow + 1'b1;
			if(addrLow == 2'b11)
				state <= STATE_READ_WAIT;
		end
	end
	STATE_READ_WAIT: begin
		if(app_rd_data_valid)
		begin
			addrLow <= addrLow + 1'b1;
			rdData <= {app_rd_data, rdData[511:128]};
			if(addrLow == 2'b11)
			begin
				state <= STATE_WS_END;
				ws_ack <= 1'b1;
			end
		end
	end
	STATE_WS_END: begin
		ws_ack <= 1'b0;
		state <= STATE_READY;
	end
	default: state <= STATE_READY;
	endcase
	
	assign app_en = (state == STATE_WRITE_CMD) | (state == STATE_READ);
	assign app_wdf_wren = (state == STATE_WRITE_DATA);
	assign app_wdf_end = app_wdf_wren;
	assign app_cmd = (state == STATE_WRITE_CMD)? MEM_WRITE: MEM_READ;

	assign app_addr = {1'b0, addr_reg, addrLow, 3'h0};
	
	assign ws_dout = rdData;
	
	always @*
	case(addrLow)
	2'b00: begin app_wdf_data <= wrData[127:  0]; app_wdf_mask <= wrDm[15: 0]; end
	2'b01: begin app_wdf_data <= wrData[255:128]; app_wdf_mask <= wrDm[31:16]; end
	2'b10: begin app_wdf_data <= wrData[383:256]; app_wdf_mask <= wrDm[47:32]; end
	2'b11: begin app_wdf_data <= wrData[511:384]; app_wdf_mask <= wrDm[63:48]; end
	endcase
	
	DDR ddr_inst(
		.ddr2_addr(ddr2_addr),
		.ddr2_ba(ddr2_ba),
		.ddr2_cas_n(ddr2_cas_n),
		.ddr2_ck_n(ddr2_ck_n),
		.ddr2_ck_p(ddr2_ck_p),
		.ddr2_cke(ddr2_cke),
		.ddr2_ras_n(ddr2_ras_n),

		.ddr2_we_n(ddr2_we_n),
		.ddr2_dq(ddr2_dq),
		.ddr2_dqs_n(ddr2_dqs_n),
		.ddr2_dqs_p(ddr2_dqs_p),
		.ddr2_cs_n(ddr2_cs_n),
		.ddr2_dm(ddr2_dm),
		.ddr2_odt(ddr2_odt),
		.init_calib_complete(init_calib_comp),

		.app_addr(app_addr),
		.app_cmd(app_cmd),
		.app_en(app_en),
		.app_rdy(app_rdy),

		.app_wdf_data(app_wdf_data),
		.app_wdf_end(app_wdf_end),
		.app_wdf_wren(app_wdf_wren),
	    .app_wdf_mask(~app_wdf_mask),
		.app_wdf_rdy(app_wdf_rdy),

		.app_rd_data(app_rd_data),
		.app_rd_data_end(),
		.app_rd_data_valid(app_rd_data_valid),

		.app_sr_req(1'b0),
		.app_ref_req(1'b0),
		.app_zq_req(1'b0),
		.app_sr_active(),
		.app_ref_ack(),
		.app_zq_ack(),

		.sys_clk_i(sysClk),
		.clk_ref_i(refClk),
		.ui_clk(clkOut),
		.sys_rst(0),
		.ui_clk_sync_rst()
	);
	
	assign dbg_state = state;
	





	
endmodule