data/full_repos/permissive/194450802/hex.v
data/verilator_xmls/70187c4e-908f-4446-940a-a63068e28a4a.xml
module hex(c, hex);
    input [3:0] c;
    output [6:0] hex;

    assign hex[0] = ~c[3] & ~c[2] & ~c[1] & c[0] | ~c[3] & c[2] & ~c[1] & ~c[0] | c[3] & (c[2] ^ c[1]) & c[0];
    assign hex[1] = c[3] & c[1] & c[0]           | c[2] & c[1] & ~c[0]          | c[3] & c[2] & ~c[0]           | ~c[3] & c[2] & ~c[1] & c[0];
    assign hex[2] = c[3] & c[2] & c[1]           | c[3] & c[2] & ~c[0]          | ~c[3] & ~c[2] & c[1] & ~c[0];
    assign hex[3] = c[2] & c[1] & c[0]           | ~c[3] & c[2] & ~c[1] & ~c[0] | ~c[3] & ~c[2] & ~c[1] & c[0]  | c[3] & ~c[2] & c[1] & ~c[0];
    assign hex[4] = ~c[3] & c[0]                 | ~c[3] & c[2] & ~c[1]         | ~c[2] & ~c[1] & c[0];
    assign hex[5] = ~c[3] & ~c[2] & c[0]         | ~c[3] & ~c[2] & c[1]         | ~c[3] & c[1] & c[0]           | c[3] & c[2] & ~c[1] & c[0];
    assign hex[6] = ~c[3] & ~c[2] & ~c[1]        | ~c[3] & c[2] & c[1] & c[0]   | c[3] & c[2] & ~c[1] & ~c[0];
endmodule
module hex(c, hex);

    input [3:0] c;
    output [6:0] hex;

    assign hex[0] = ~c[3] & ~c[2] & ~c[1] & c[0] | ~c[3] & c[2] & ~c[1] & ~c[0] | c[3] & (c[2] ^ c[1]) & c[0];
    assign hex[1] = c[3] & c[1] & c[0]           | c[2] & c[1] & ~c[0]          | c[3] & c[2] & ~c[0]           | ~c[3] & c[2] & ~c[1] & c[0];
    assign hex[2] = c[3] & c[2] & c[1]           | c[3] & c[2] & ~c[0]          | ~c[3] & ~c[2] & c[1] & ~c[0];
    assign hex[3] = c[2] & c[1] & c[0]           | ~c[3] & c[2] & ~c[1] & ~c[0] | ~c[3] & ~c[2] & ~c[1] & c[0]  | c[3] & ~c[2] & c[1] & ~c[0];
    assign hex[4] = ~c[3] & c[0]                 | ~c[3] & c[2] & ~c[1]         | ~c[2] & ~c[1] & c[0];
    assign hex[5] = ~c[3] & ~c[2] & c[0]         | ~c[3] & ~c[2] & c[1]         | ~c[3] & c[1] & c[0]           | c[3] & c[2] & ~c[1] & c[0];
    assign hex[6] = ~c[3] & ~c[2] & ~c[1]        | ~c[3] & c[2] & c[1] & c[0]   | c[3] & c[2] & ~c[1] & ~c[0];
endmodule