data/full_repos/permissive/120749710/seg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/120749710/seg.v:69: Operator EQ expects 32 or 23 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 16 bits.\n                                                             : ... In instance seg\n  else if (cnt == mili-1)\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/120749710/seg.v:67: Operator EQ expects 32 or 23 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 16 bits.\n                                                             : ... In instance seg\n  else if(cnt == mili)\n              ^~\n%Error: Exiting due to 2 warning(s)\n'
module encode(
	input wire [3:0] tmp,
	output reg [6:0] segment
);
always@(*)
begin
	case (tmp)
		0:  segment = 7'b100_0000;
		1:  segment = 7'b111_1001;
		2:  segment = 7'b010_0100;
		3:  segment = 7'b011_0000;
		4:  segment = 7'b001_1001;
		5:  segment = 7'b001_0010;
		6:  segment = 7'b000_0010;
		7:  segment = 7'b111_1000;
		8:  segment = 7'b000_0000;
		9:  segment = 7'b001_0000; 
		10:  segment = 7'b000_1000;
		11:  segment = 7'b000_0011;
		12:  segment = 7'b100_0110;
		13:  segment = 7'b010_0001;
		14:  segment = 7'b000_0110;
		15:  segment = 7'b000_1110;
		default:  segment = 7'b000_0000;
	endcase
end
endmodule
module encode(
	input wire [3:0] tmp,
	output reg [6:0] segment
);

always@(*)
begin
	case (tmp)
		0:  segment = 7'b100_0000;
		1:  segment = 7'b111_1001;
		2:  segment = 7'b010_0100;
		3:  segment = 7'b011_0000;
		4:  segment = 7'b001_1001;
		5:  segment = 7'b001_0010;
		6:  segment = 7'b000_0010;
		7:  segment = 7'b111_1000;
		8:  segment = 7'b000_0000;
		9:  segment = 7'b001_0000; 
		10:  segment = 7'b000_1000;
		11:  segment = 7'b000_0011;
		12:  segment = 7'b100_0110;
		13:  segment = 7'b010_0001;
		14:  segment = 7'b000_0110;
		15:  segment = 7'b000_1110;
		default:  segment = 7'b000_0000;
	endcase
end
endmodule