data/full_repos/permissive/15946916/Lab6/lab6_2_test.v
 line:36: before: "$"
1: b'%Error: data/full_repos/permissive/15946916/Lab6/lab6_2_test.v:2: Cannot find include file: lab6_2.v\n`include "lab6_2.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/15946916/Lab6,data/full_repos/permissive/15946916/lab6_2.v\n             data/full_repos/permissive/15946916/Lab6,data/full_repos/permissive/15946916/lab6_2.v.v\n             data/full_repos/permissive/15946916/Lab6,data/full_repos/permissive/15946916/lab6_2.v.sv\n             lab6_2.v\n             lab6_2.v.v\n             lab6_2.v.sv\n             obj_dir/lab6_2.v\n             obj_dir/lab6_2.v.v\n             obj_dir/lab6_2.v.sv\n%Error: data/full_repos/permissive/15946916/Lab6/lab6_2_test.v:14: Unsupported or unknown PLI call: $monitor\n        $monitor ($time,"\\ta=%b\\tb=%b\\tsum=%b\\tcarry=%b",a,b, sum, carry);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_2_test.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_2_test.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_2_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_2_test.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module half_adder_test();

	reg    a, b;
    wire   sum;
	wire   carry;

    half_adder test(sum,carry,a,b);

    initial begin
        $monitor ($time,"\ta=%b\tb=%b\tsum=%b\tcarry=%b",a,b, sum, carry);
        a = 0; b = 0;
        #1 
        a = 0; b = 1;
        #1
        a = 1; b = 0;
        #1
        a = 1; b = 1;
        #1 
        $finish;
    end
endmodule
module half_adder_test();


	reg    a, b;
    wire   sum;
	wire   carry;

    half_adder test(sum,carry,a,b);

    initial begin
        $monitor ($time,"\ta=%b\tb=%b\tsum=%b\tcarry=%b",a,b, sum, carry);
        a = 0; b = 0;
        #1 
        a = 0; b = 1;
        #1
        a = 1; b = 0;
        #1
        a = 1; b = 1;
        #1 
        $finish;
    end
endmodule