data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v
 line:1: before: "function"
1: b'%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:4: syntax error, unexpected ::, expecting \'(\' or \';\'\nfunction void UNI_cell::post_randomize();\n                      ^~\n                                                                   : ... Perhaps \'UNI_cell\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:13: Unsupported: virtual classes\nvirtual class BaseTr;\n^~~~~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:13: Unsupported: classes\nvirtual class BaseTr;\n        ^~~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:14: Unsupported: new constructor\n  function new();\n           ^~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:15: syntax error, unexpected ++, expecting \';\'\n    id = count++;\n              ^~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:18: Unsupported: pure virtual class method\n  pure virtual function bit compare(input BaseTr to);\n  ^~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:19: Unsupported: pure virtual class method\n  pure virtual function BaseTr copy(input BaseTr to=null);\n  ^~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:20: Unsupported: pure virtual class method\n  pure virtual function void display(input string prefix="");\n  ^~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:26: syntax error, unexpected "\'", expecting TYPE-IDENTIFIER\ninteger threes[4] = \' { 3, 6, 9, 12 };\n                    ^\n%Error: Exiting due to 9 error(s)\n'
module m1(
    idx, base, fd, sd
);

input   [6:0]   idx;
output  [26:0]  base;
output  [17:0]  fd;
output  [10:0]  sd;


reg [26:0]  base;
reg [17:0]  fd;
reg [10:0]  sd;

always @(idx)
  case (idx)
    7'h00   : begin  base = 27'h3fffffe; fd = 18'h3fff7; sd = 11'h7e8;  end
    7'h01   : begin  base = 27'h3f01fbf; fd = 18'h3f027; sd = 11'h7ba;  end
    7'h02   : begin  base = 27'h3e07e06; fd = 18'h3e0b4; sd = 11'h78d;  end
    7'h7b   : begin  base = 27'h01465fe; fd = 18'h10a4c; sd = 11'h10e;  end
    7'h7c   : begin  base = 27'h0104104; fd = 18'h10830; sd = 11'h10a;  end
    7'h7d   : begin  base = 27'h00c246d; fd = 18'h1061b; sd = 11'h108;  end
    7'h7e   : begin  base = 27'h0081020; fd = 18'h1040b; sd = 11'h104;  end
    7'h7f   : begin  base = 27'h0040404; fd = 18'h10202; sd = 11'h101;  end
  endcase

endmodule
module m1(
    idx, base, fd, sd
);


input   [6:0]   idx;
output  [26:0]  base;
output  [17:0]  fd;
output  [10:0]  sd;


reg [26:0]  base;
reg [17:0]  fd;
reg [10:0]  sd;

always @(idx)
  case (idx)
    7'h00   : begin  base = 27'h3fffffe; fd = 18'h3fff7; sd = 11'h7e8;  end
    7'h01   : begin  base = 27'h3f01fbf; fd = 18'h3f027; sd = 11'h7ba;  end
    7'h02   : begin  base = 27'h3e07e06; fd = 18'h3e0b4; sd = 11'h78d;  end
    7'h7b   : begin  base = 27'h01465fe; fd = 18'h10a4c; sd = 11'h10e;  end
    7'h7c   : begin  base = 27'h0104104; fd = 18'h10830; sd = 11'h10a;  end
    7'h7d   : begin  base = 27'h00c246d; fd = 18'h1061b; sd = 11'h108;  end
    7'h7e   : begin  base = 27'h0081020; fd = 18'h1040b; sd = 11'h104;  end
    7'h7f   : begin  base = 27'h0040404; fd = 18'h10202; sd = 11'h101;  end
  endcase

endmodule