data/full_repos/permissive/19572582/Lab3/lab3_part4.v
data/verilator_xmls/f14d0b31-9c3f-4766-8601-f5340d00a4bb.xml
module lab3_part4 (D, Clk, Qa, Qb, Qc);

	input D, Clk;
	output Qa, Qb, Qc;
		
	wire D, Clk;

	Dflop D0 (D, Clk, Qa);
	PED P0 (D, Clk, Qb);
	NED N0 (D, Clk, Qc);
	
	
	
endmodule
module lab3_part4 (D, Clk, Qa, Qb, Qc);


	input D, Clk;
	output Qa, Qb, Qc;
		
	wire D, Clk;

	Dflop D0 (D, Clk, Qa);
	PED P0 (D, Clk, Qb);
	NED N0 (D, Clk, Qc);
	
	
	
endmodule