data/full_repos/permissive/202675791/hdl/mixed/blink/clkgen.v
1: b"%Error: data/full_repos/permissive/202675791/hdl/mixed/blink/clkgen.v:8: Cannot find file containing module: 'SB_GB'\n  SB_GB clk_gb (\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/202675791/hdl/mixed/blink,data/full_repos/permissive/202675791/SB_GB\n             data/full_repos/permissive/202675791/hdl/mixed/blink,data/full_repos/permissive/202675791/SB_GB.v\n             data/full_repos/permissive/202675791/hdl/mixed/blink,data/full_repos/permissive/202675791/SB_GB.sv\n             SB_GB\n             SB_GB.v\n             SB_GB.sv\n             obj_dir/SB_GB\n             obj_dir/SB_GB.v\n             obj_dir/SB_GB.sv\n%Error: Exiting due to 1 error(s)\n"
module clkgen (
  input  wire       clk,
  output wire [2:0] cnt
);


  wire clko;
  SB_GB clk_gb (
      .USER_SIGNAL_TO_GLOBAL_BUFFER(clk),
      .GLOBAL_BUFFER_OUTPUT(clko)
  );



  reg [28:0] counter = 0;
  always @(posedge clko) begin
      counter <= counter + 1;
  end
  assign cnt = counter[25:23];

endmodule
module clkgen (
  input  wire       clk,
  output wire [2:0] cnt
);



  wire clko;
  SB_GB clk_gb (
      .USER_SIGNAL_TO_GLOBAL_BUFFER(clk),
      .GLOBAL_BUFFER_OUTPUT(clko)
  );



  reg [28:0] counter = 0;
  always @(posedge clko) begin
      counter <= counter + 1;
  end
  assign cnt = counter[25:23];

endmodule