data/full_repos/permissive/174642777/Experiments/Lab X7/2. SMD (ver2)/SMD.v
1: b'%Error: Cannot find file containing module: X7/2.\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X7/2.\n             data/full_repos/permissive/174642777/Experiments/Lab/X7/2..v\n             data/full_repos/permissive/174642777/Experiments/Lab/X7/2..sv\n             X7/2.\n             X7/2..v\n             X7/2..sv\n             obj_dir/X7/2.\n             obj_dir/X7/2..v\n             obj_dir/X7/2..sv\n%Error: Cannot find file containing module: SMD\n%Error: Cannot find file containing module: (ver2),data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: (ver2)/SMD.v\n%Error: Exiting due to 5 error(s)\n'
module SMD(
  input wire CLK,
  input wire nickel, dime, quarter,
  output reg[2:0] state,
  output reg[3:0] ret
);

  reg[2:0] hold;
  
  

  initial begin
    state <= 0;
    ret   <= 0;
    hold  <= 0;
  end
  
  

  always@(posedge CLK) begin

    if(hold == 3'b000) begin
      if(nickel)  hold = 3'b001;
      if(dime)    hold = 3'b010;
      if(quarter) hold = 3'b100;
    end

    else if(!nickel&!dime&!quarter) begin

      if(hold[0]) begin
        if(state[2]) begin
          state <= 3'b000;
          ret <= 4'b1000;
        end
        else begin
          state <= state + 3'b001;
          ret <= 4'b0000;
        end
      end
      

      if(hold[1]) begin
        if(!state[2]) begin
          if(state[1]&state[0]) begin
            state <= 3'b000;
            ret <= 4'b1000;
          end
          else begin
            state <= state + 3'b010;
            ret <= 4'b0000;
          end
        end
        else begin
          state <= 3'b000;
          ret <= 4'b1100;
        end
      end
      

      if(hold[2]) begin
        case(state)
          3'b000:  ret <= 4'b1000;
          3'b001:  ret <= 4'b1100;
          3'b010:  ret <= 4'b1010;
          3'b011:  ret <= 4'b1110;
          default: ret <= 4'b1001;
        endcase
        state <= 3'b000;
      end
      

      hold = 0;
    end
  end

endmodule
module SMD(
  input wire CLK,
  input wire nickel, dime, quarter,
  output reg[2:0] state,
  output reg[3:0] ret
);


  reg[2:0] hold;
  
  

  initial begin
    state <= 0;
    ret   <= 0;
    hold  <= 0;
  end
  
  

  always@(posedge CLK) begin

    if(hold == 3'b000) begin
      if(nickel)  hold = 3'b001;
      if(dime)    hold = 3'b010;
      if(quarter) hold = 3'b100;
    end

    else if(!nickel&!dime&!quarter) begin

      if(hold[0]) begin
        if(state[2]) begin
          state <= 3'b000;
          ret <= 4'b1000;
        end
        else begin
          state <= state + 3'b001;
          ret <= 4'b0000;
        end
      end
      

      if(hold[1]) begin
        if(!state[2]) begin
          if(state[1]&state[0]) begin
            state <= 3'b000;
            ret <= 4'b1000;
          end
          else begin
            state <= state + 3'b010;
            ret <= 4'b0000;
          end
        end
        else begin
          state <= 3'b000;
          ret <= 4'b1100;
        end
      end
      

      if(hold[2]) begin
        case(state)
          3'b000:  ret <= 4'b1000;
          3'b001:  ret <= 4'b1100;
          3'b010:  ret <= 4'b1010;
          3'b011:  ret <= 4'b1110;
          default: ret <= 4'b1001;
        endcase
        state <= 3'b000;
      end
      

      hold = 0;
    end
  end

endmodule