data/full_repos/permissive/143278/ivltests/pr1704013.v
data/verilator_xmls/a0251657-2f89-4ca6-861a-ae27d24da7d2.xml
module top;
  reg clk = 0;
  reg [1:0] in = 2'b00;
  wire [1:0] out;

  test t1 (clk, out, in);
endmodule
module top;

  reg clk = 0;
  reg [1:0] in = 2'b00;
  wire [1:0] out;

  test t1 (clk, out, in);
endmodule