data/full_repos/permissive/117026779/src/MIPS.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/117026779/src/MIPS.v:898: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'MIPS\'\nmodule MIPS(\n       ^~~~\n                                                                      : ... Top module \'MULT\'\nmodule MULT #(parameter WIDTH = 32)(\n       ^~~~\n                                                                      : ... Top module \'DIV\'\nmodule DIV #(parameter WIDTH = 32)(\n       ^~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:754: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n                                                                   : ... In instance MIPS.regfile\nassign read_data_1 = (read_address_1 != 0) ? register_file[read_address_1] : 0;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:755: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n                                                                   : ... In instance MIPS.regfile\nassign read_data_2 = (read_address_2 != 0) ? register_file[read_address_2] : 0;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:774: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n                                                                   : ... In instance MIPS.regfile\n        register_file[write_address] <= write_data;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegWriteDst <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegInSelect <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            PCSrc       <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            MemWrite    <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            ALUOp       <= 1\'bx;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegWriteDst <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegInSelect <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            PCSrc       <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            MemWrite    <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            ALUOp       <= 1\'bx;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegWriteDst <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegInSelect <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            PCSrc       <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            MemWrite    <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            ALUOp       <= 1\'bx;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:194: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'write_address\' generates 5 bits.\n                                                                   : ... In instance MIPS\nassign RegWriteAddress              = write_address;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:241: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                   : ... In instance MIPS\nwire [32-1:0] DataBusByte = DataBusByteShifted & 8\'hFF;\n                                               ^\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:266: Cannot find file containing module: \'REGISTER\'\nREGISTER #(.WIDTH(32)) pc_register (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/REGISTER\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/REGISTER.v\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/REGISTER.sv\n             REGISTER\n             REGISTER.v\n             REGISTER.sv\n             obj_dir/REGISTER\n             obj_dir/REGISTER.v\n             obj_dir/REGISTER.sv\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:280: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:325: Input port connection \'a\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'branch_pc_offset\' generates 32 bits.\n                                                                   : ... In instance MIPS\n .a(branch_pc_offset),\n  ^\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:335: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:344: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:366: Cannot find file containing module: \'OR\'\nOR #(.WIDTH(4)\n^~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:372: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:385: Cannot find file containing module: \'TRIBUFFER\'\nTRIBUFFER #(.WIDTH(32)\n^~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:403: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: Exiting due to 8 error(s), 22 warning(s)\n'
module VALUE_EXTEND #(
    parameter INPUT_WIDTH = 16,
    parameter OUTPUT_WIDTH = 32
)
(
    input  wire                     sign_extend,
	input  wire [INPUT_WIDTH-1:0]   a,
	output wire [OUTPUT_WIDTH-1:0]  y
);

wire [OUTPUT_WIDTH-1:0] sign_extended_value = { { (OUTPUT_WIDTH-INPUT_WIDTH){ a[INPUT_WIDTH-1] } }, a };
wire [OUTPUT_WIDTH-1:0] zero_extended_value = { { (OUTPUT_WIDTH-INPUT_WIDTH){ 1'b0 } }, a };

assign y = (sign_extend) ? sign_extended_value : zero_extended_value;

endmodule
module VALUE_EXTEND #(
    parameter INPUT_WIDTH = 16,
    parameter OUTPUT_WIDTH = 32
)
(
    input  wire                     sign_extend,
	input  wire [INPUT_WIDTH-1:0]   a,
	output wire [OUTPUT_WIDTH-1:0]  y
);


wire [OUTPUT_WIDTH-1:0] sign_extended_value = { { (OUTPUT_WIDTH-INPUT_WIDTH){ a[INPUT_WIDTH-1] } }, a };
wire [OUTPUT_WIDTH-1:0] zero_extended_value = { { (OUTPUT_WIDTH-INPUT_WIDTH){ 1'b0 } }, a };

assign y = (sign_extend) ? sign_extended_value : zero_extended_value;

endmodule