data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM_tb.v
 line:79: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #30 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #1 CLK = ~CLK;\n        ^\n%Error: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM_tb.v:31: Cannot find file containing module: \'Instruction_Memory\'\n    Instruction_Memory mem1(\n    ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208519918/Single-Cycle-Processor,data/full_repos/permissive/208519918/Instruction_Memory\n             data/full_repos/permissive/208519918/Single-Cycle-Processor,data/full_repos/permissive/208519918/Instruction_Memory.v\n             data/full_repos/permissive/208519918/Single-Cycle-Processor,data/full_repos/permissive/208519918/Instruction_Memory.sv\n             Instruction_Memory\n             Instruction_Memory.v\n             Instruction_Memory.sv\n             obj_dir/Instruction_Memory\n             obj_dir/Instruction_Memory.v\n             obj_dir/Instruction_Memory.sv\n%Error: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM_tb.v:37: Cannot find file containing module: \'Registers\'\n    Registers mem2(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM_tb.v:48: Cannot find file containing module: \'Data_Memory\'\n    Data_Memory mem3(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM_tb.v:57: Cannot find file containing module: \'SS_ARM\'\n    SS_ARM core(\n    ^~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SS_ARM_tb;

    reg CLK;


    wire [63:0] PC_instruction;
    wire [31:0] Out_instruction;


    wire [4:0] Read_register_1;
    wire [4:0] Read_register_2;
    wire [4:0] Write_register;
    wire [63:0] Write_data;
    wire [63:0] Data_out_1;
    wire [63:0] Data_out_2;


    wire [63:0] memory_data;
    wire [63:0] ALU_result;


    wire Reg2Loc_control;
    wire RegWrite_control;
    wire MemRead_control;
    wire MemWrite_control;
    wire Branch_control;


    Instruction_Memory mem1(
        PC_instruction,
        Out_instruction
    );


    Registers mem2(
        Read_register_1,
        Read_register_2,
        Write_register,
        Write_data,
        RegWrite_control,
        Data_out_1,
        Data_out_2
    );


    Data_Memory mem3(
        ALU_result,
        Data_out_2,
        MemRead_control,
        MemWrite_control,
        memory_data
    );


    SS_ARM core(
        .CLK(CLK),
        .instruction_word(Out_instruction),
        .PC(PC_instruction),
        .Reg2Loc_control(Reg2Loc_control),
        .RegWrite_control(RegWrite_control),
        .MemRead_control(MemRead_control),
        .MemWrite_control(MemWrite_control),
        .Branch_control(Branch_control),
        .Read_register_1(Read_register_1),
        .Read_register_2(Read_register_2),
        .Write_register(Write_register),
        .register_data_1(Data_out_1),
        .register_data_2(Data_out_2),
        .ALU_result(ALU_result),
        .memory_data(memory_data),
        .Write_register_data(Write_data)
    );


    initial begin
        CLK = 1'b0;
        #30 $finish;
    end


    always begin
        #1 CLK = ~CLK;
    end
endmodule
module SS_ARM_tb;


    reg CLK;


    wire [63:0] PC_instruction;
    wire [31:0] Out_instruction;


    wire [4:0] Read_register_1;
    wire [4:0] Read_register_2;
    wire [4:0] Write_register;
    wire [63:0] Write_data;
    wire [63:0] Data_out_1;
    wire [63:0] Data_out_2;


    wire [63:0] memory_data;
    wire [63:0] ALU_result;


    wire Reg2Loc_control;
    wire RegWrite_control;
    wire MemRead_control;
    wire MemWrite_control;
    wire Branch_control;


    Instruction_Memory mem1(
        PC_instruction,
        Out_instruction
    );


    Registers mem2(
        Read_register_1,
        Read_register_2,
        Write_register,
        Write_data,
        RegWrite_control,
        Data_out_1,
        Data_out_2
    );


    Data_Memory mem3(
        ALU_result,
        Data_out_2,
        MemRead_control,
        MemWrite_control,
        memory_data
    );


    SS_ARM core(
        .CLK(CLK),
        .instruction_word(Out_instruction),
        .PC(PC_instruction),
        .Reg2Loc_control(Reg2Loc_control),
        .RegWrite_control(RegWrite_control),
        .MemRead_control(MemRead_control),
        .MemWrite_control(MemWrite_control),
        .Branch_control(Branch_control),
        .Read_register_1(Read_register_1),
        .Read_register_2(Read_register_2),
        .Write_register(Write_register),
        .register_data_1(Data_out_1),
        .register_data_2(Data_out_2),
        .ALU_result(ALU_result),
        .memory_data(memory_data),
        .Write_register_data(Write_data)
    );


    initial begin
        CLK = 1'b0;
        #30 $finish;
    end


    always begin
        #1 CLK = ~CLK;
    end
endmodule