data/full_repos/permissive/211866113/Register.v
data/verilator_xmls/f7d812cb-e5da-4922-8582-a6fd9d527597.xml
module D_FlipFlop(input D,
		  input      clk,
		  input      async_reset,
		  output reg Q
		  );

    always @(posedge clk or posedge async_reset)
      begin
	  if(async_reset==1'b1)
	    Q <= 1'b0;
	  else
	    Q <= D;
      end
endmodule
module D_FlipFlop(input D,
		  input      clk,
		  input      async_reset,
		  output reg Q
		  );


    always @(posedge clk or posedge async_reset)
      begin
	  if(async_reset==1'b1)
	    Q <= 1'b0;
	  else
	    Q <= D;
      end
endmodule