data/full_repos/permissive/210844779/lab8/8.1/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab8/8.1/tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210844779/lab8/8.1/tb.v:6: Cannot find file containing module: \'mux_8x1\'\nmux_8x1 u0mux_8x1(y,i0,i1,i2,i3,i4,i5,i6,i7,sel2,sel1,sel0);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab8/8.1,data/full_repos/permissive/210844779/mux_8x1\n             data/full_repos/permissive/210844779/lab8/8.1,data/full_repos/permissive/210844779/mux_8x1.v\n             data/full_repos/permissive/210844779/lab8/8.1,data/full_repos/permissive/210844779/mux_8x1.sv\n             mux_8x1\n             mux_8x1.v\n             mux_8x1.sv\n             obj_dir/mux_8x1\n             obj_dir/mux_8x1.v\n             obj_dir/mux_8x1.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.1/tb.v:10: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  i0=$random;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.1/tb.v:11: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  i1=$random;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.1/tb.v:12: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  i2=$random;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.1/tb.v:13: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  i3=$random;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.1/tb.v:14: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  i4=$random;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.1/tb.v:15: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  i5=$random;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.1/tb.v:16: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  i6=$random;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.1/tb.v:17: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  i7=$random;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.1/tb.v:18: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  sel2=$random;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.1/tb.v:19: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  sel1=$random;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab8/8.1/tb.v:20: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  sel0=$random;\n      ^\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  wire y;
reg i0,i1,i2,i3,i4,i5,i6,i7;
reg sel2,sel1,sel0;

mux_8x1 u0mux_8x1(y,i0,i1,i2,i3,i4,i5,i6,i7,sel2,sel1,sel0);

always
begin
  i0=$random;
  i1=$random;
  i2=$random;
  i3=$random;
  i4=$random;
  i5=$random;
  i6=$random;
  i7=$random;
  sel2=$random;
  sel1=$random;
  sel0=$random;
  #10;
end

endmodule
module tb();

  wire y;
reg i0,i1,i2,i3,i4,i5,i6,i7;
reg sel2,sel1,sel0;

mux_8x1 u0mux_8x1(y,i0,i1,i2,i3,i4,i5,i6,i7,sel2,sel1,sel0);

always
begin
  i0=$random;
  i1=$random;
  i2=$random;
  i3=$random;
  i4=$random;
  i5=$random;
  i6=$random;
  i7=$random;
  sel2=$random;
  sel1=$random;
  sel0=$random;
  #10;
end

endmodule