data/full_repos/permissive/143278/ivltests/pr2913438a.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2913438a.v:24: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                          : ... In instance bug\n      Expect = (i%2)*2 + (j%2);\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2913438a.v:25: Operator FUNCREF \'Copy\' expects 2 bits on the Function Argument, but Function Argument\'s ADD generates 32 bits.\n                                                                          : ... In instance bug\n      Actual = Copy((i%2)*2 + (j%2));\n               ^~~~\n%Error: Exiting due to 2 warning(s)\n'
module bug;

function [1:0] Copy;

input [1:0] Value;

begin
  Copy = Value;
end

endfunction

integer   i;
integer   j;

reg [1:0] Expect;
reg [1:0] Actual;
reg       Failed;

initial begin
  Failed = 0;
  for (i = 0; i < 4; i = i + 1) begin
    for (j = 0; j < 4; j = j + 1) begin
      Expect = (i%2)*2 + (j%2);
      Actual = Copy((i%2)*2 + (j%2));
      if (Actual !== Expect) begin
        $display("Failed: %0d,%0d expected %0d, got %0d", i, j, Expect, Actual);
        Failed = 1;
      end
    end
  end
  if (!Failed) $display("PASSED");
end

endmodule
module bug;


function [1:0] Copy;

input [1:0] Value;

begin
  Copy = Value;
end

endfunction

integer   i;
integer   j;

reg [1:0] Expect;
reg [1:0] Actual;
reg       Failed;

initial begin
  Failed = 0;
  for (i = 0; i < 4; i = i + 1) begin
    for (j = 0; j < 4; j = j + 1) begin
      Expect = (i%2)*2 + (j%2);
      Actual = Copy((i%2)*2 + (j%2));
      if (Actual !== Expect) begin
        $display("Failed: %0d,%0d expected %0d, got %0d", i, j, Expect, Actual);
        Failed = 1;
      end
    end
  end
  if (!Failed) $display("PASSED");
end

endmodule