data/full_repos/permissive/107499099/mips_de2-115/MIPS/pc.v
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data/verilator_xmls/1ba59cc4-a3cd-4156-b12a-8388ae61090d.xml
module pc (clock, reset, pc_next, pc);

  input       clock, reset;
  input  [31:0]    pc_next;
  output [31:0]         pc;

  reg    [31:0]     pc_reg;





  always @(posedge clock or negedge reset) begin
    if (reset == 1'b0) begin
	pc_reg <= 32'h00400000;
    end else begin
	pc_reg <= pc_next;
    end
  end

  assign pc = pc_reg;   
endmodule
module pc (clock, reset, pc_next, pc);


  input       clock, reset;
  input  [31:0]    pc_next;
  output [31:0]         pc;

  reg    [31:0]     pc_reg;





  always @(posedge clock or negedge reset) begin
    if (reset == 1'b0) begin
	pc_reg <= 32'h00400000;
    end else begin
	pc_reg <= pc_next;
    end
  end

  assign pc = pc_reg;   
endmodule