data/full_repos/permissive/146246005/AASD and Counter/counter.sv
1: b'%Error: Cannot find file containing module: and\n        ... Looked in:\n             data/full_repos/permissive/146246005/AASD/and\n             data/full_repos/permissive/146246005/AASD/and.v\n             data/full_repos/permissive/146246005/AASD/and.sv\n             and\n             and.v\n             and.sv\n             obj_dir/and\n             obj_dir/and.v\n             obj_dir/and.sv\n%Error: Cannot find file containing module: Counter,data/full_repos/permissive/146246005\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/AASD\n%Error: Cannot find file containing module: Counter/counter.sv\n%Error: Exiting due to 4 error(s)\n'
module counter(Count, Clock, Reset, Enable, Load, Data); 
	output reg [5:0] Count; 
	input  [5:0] Data; 
	input  Clock, Enable, Reset, Load; 
	
	always @(posedge Clock or negedge Reset)
		if(!Reset)
			Count <= 6'b000000;
		else if(Enable)
			begin
				if(Load)
					Count <= Data;
				else
					Count <= Count+ 1;
	end

endmodule
module counter(Count, Clock, Reset, Enable, Load, Data);
 
	output reg [5:0] Count; 
	input  [5:0] Data; 
	input  Clock, Enable, Reset, Load; 
	
	always @(posedge Clock or negedge Reset)
		if(!Reset)
			Count <= 6'b000000;
		else if(Enable)
			begin
				if(Load)
					Count <= Data;
				else
					Count <= Count+ 1;
	end

endmodule