data/full_repos/permissive/157101210/mux.v
data/verilator_xmls/948f68ae-6f21-4463-85c7-7842c2dec56f.xml
module mux
#(
	parameter data_width = 32
)
(
output[data_width-1:0]  out,
input         sel,
input[data_width-1:0]   input0, input1
);

  wire[data_width-1:0] mux[1:0];
  assign mux[0]  = input0;
  assign mux[1]  = input1;
  assign out = mux[sel];
endmodule
module mux
#(
	parameter data_width = 32
)
(
output[data_width-1:0]  out,
input         sel,
input[data_width-1:0]   input0, input1
);


  wire[data_width-1:0] mux[1:0];
  assign mux[0]  = input0;
  assign mux[1]  = input1;
  assign out = mux[sel];
endmodule