data/full_repos/permissive/175261487/src/ps2_rx.v
data/verilator_xmls/a6e2f0d0-2a0c-499f-901b-e13b20915c4d.xml
module ps2_rx(
	input clk,
	input rst,
	input ps2_clk_in,
	input ps2_dat_in,
	input ps2_clk_ena,
	input ps2_dat_sync,
	output reg [7:0] rx_code,
	output reg rx_done,
	output reg rx_frmerr,
	output reg rx_parerr
);

	localparam ST_WAIT = 4'h0;
	localparam ST_DAT0 = 4'hA;
	localparam ST_STOP = 4'h1;	
	reg [3:0] rx_state;
	reg [8:0] rx_sreg;
	always @(posedge clk)
		if(rst)
		begin
			rx_state <= ST_WAIT;
			rx_done <= 1'b0;
			rx_frmerr <= 1'b0;
			rx_parerr <= 1'b0;
		end
		else
		begin
			if(ps2_clk_ena)
			begin

				if(|rx_state)
					rx_state <= rx_state - 4'h1;
				else if(ps2_dat_sync == 1'b0)
					rx_state <= ST_DAT0;
				

				if(|rx_state)
					rx_sreg <= {ps2_dat_sync,rx_sreg[8:1]};
				

				if(rx_state == ST_STOP)
				begin
					rx_done <= 1'b1;
					if(ps2_dat_sync == 1'b0)
						rx_frmerr <= 1'b1;
					if(^rx_sreg == 1'b0)
						rx_parerr <= 1'b1;
					rx_code <= rx_sreg[7:0];
				end
			end
			else
				rx_done <= 1'b0;
		end
endmodule
module ps2_rx(
	input clk,
	input rst,
	input ps2_clk_in,
	input ps2_dat_in,
	input ps2_clk_ena,
	input ps2_dat_sync,
	output reg [7:0] rx_code,
	output reg rx_done,
	output reg rx_frmerr,
	output reg rx_parerr
);


	localparam ST_WAIT = 4'h0;
	localparam ST_DAT0 = 4'hA;
	localparam ST_STOP = 4'h1;	
	reg [3:0] rx_state;
	reg [8:0] rx_sreg;
	always @(posedge clk)
		if(rst)
		begin
			rx_state <= ST_WAIT;
			rx_done <= 1'b0;
			rx_frmerr <= 1'b0;
			rx_parerr <= 1'b0;
		end
		else
		begin
			if(ps2_clk_ena)
			begin

				if(|rx_state)
					rx_state <= rx_state - 4'h1;
				else if(ps2_dat_sync == 1'b0)
					rx_state <= ST_DAT0;
				

				if(|rx_state)
					rx_sreg <= {ps2_dat_sync,rx_sreg[8:1]};
				

				if(rx_state == ST_STOP)
				begin
					rx_done <= 1'b1;
					if(ps2_dat_sync == 1'b0)
						rx_frmerr <= 1'b1;
					if(^rx_sreg == 1'b0)
						rx_parerr <= 1'b1;
					rx_code <= rx_sreg[7:0];
				end
			end
			else
				rx_done <= 1'b0;
		end
endmodule