data/full_repos/permissive/111901713/rtl/sbox.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/111901713/rtl/sbox.v:25: Little bit endian vector: MSB < LSB of bit range: 0:7\n wire[0:7] s, x;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module xS (clk, in, out);
    input clk;
    input [7:0] in;
    output [7:0] out;
    
    wire [7:0] out_2;
	
	S S_(
		.clk(clk),
		.in(in),
		.out(out_2)
	);
	
	wire dummy;
	
	assign {dummy, out} = out_2[7]? {out_2, 1'b0}^9'h11b : {out_2, 1'b0};
	
	
endmodule
module xS (clk, in, out);

    input clk;
    input [7:0] in;
    output [7:0] out;
    
    wire [7:0] out_2;
	
	S S_(
		.clk(clk),
		.in(in),
		.out(out_2)
	);
	
	wire dummy;
	
	assign {dummy, out} = out_2[7]? {out_2, 1'b0}^9'h11b : {out_2, 1'b0};
	
	
endmodule