data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/data_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/data_fifo.v:51: Bit extraction of array[256:0] requires 9 bit index, not 8 bits.\n                                                                                                                                                                   : ... In instance data_fifo\n      queue[wr_ptr] <= din;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/data_fifo.v:57: Bit extraction of array[256:0] requires 9 bit index, not 8 bits.\n                                                                                                                                                                   : ... In instance data_fifo\n       queue[rd_ptr];\n            ^\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/data_fifo.v:88: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'depth\' generates 8 bits.\n                                                                                                                                                                   : ... In instance data_fifo\nassign data_count = depth;\n                  ^\n%Error: Exiting due to 3 warning(s)\n'
module data_fifo
    #(parameter WIDTH = 72,
      parameter FIFO_DEPTH = 256,
      parameter PROG_FULL_THRESHOLD = 8
      )
    (

     input [WIDTH-1:0] din,
     input          wr_en,

     input          rd_en,

     output reg [WIDTH-1:0]  dout,
     output         full,
     output         nearly_full,
     output         prog_full,
     output         empty,
     output [5:0]      data_count,

     input          reset,
     input          clk
     );




reg [WIDTH-1:0] queue [256 : 0];
reg [7 : 0] rd_ptr;
reg [7 : 0] wr_ptr;
reg [7 : 0] depth;


always @(posedge clk)
begin
   if (wr_en)
      queue[wr_ptr] <= din;
   if (rd_en)
      dout <=

	      #1

	      queue[rd_ptr];
end

always @(posedge clk)
begin
   if (reset) begin
      rd_ptr <= 'h0;
      wr_ptr <= 'h0;
      depth  <= 'h0;
   end
   else begin
      if (wr_en) wr_ptr <= wr_ptr + 'h1;
      if (rd_en) rd_ptr <= rd_ptr + 'h1;
      if (wr_en & ~rd_en) depth <=

				   #1

				   depth + 'h1;
      else if (~wr_en & rd_en) depth <=

				   #1

				   depth - 'h1;
   end
end


assign full = depth == 255;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= 7;
assign empty = depth == 'h0;
assign data_count = depth;


always @(posedge clk)
begin
   if (wr_en && depth == 255 && !rd_en)
      $display($time, " ERROR: Attempt to write to full FIFO: %m");
   if (rd_en && depth == 'h0)
      $display($time, " ERROR: Attempt to read an empty FIFO: %m");
end


endmodule
module data_fifo
    #(parameter WIDTH = 72,
      parameter FIFO_DEPTH = 256,
      parameter PROG_FULL_THRESHOLD = 8
      )
    (

     input [WIDTH-1:0] din,
     input          wr_en,

     input          rd_en,

     output reg [WIDTH-1:0]  dout,
     output         full,
     output         nearly_full,
     output         prog_full,
     output         empty,
     output [5:0]      data_count,

     input          reset,
     input          clk
     );





reg [WIDTH-1:0] queue [256 : 0];
reg [7 : 0] rd_ptr;
reg [7 : 0] wr_ptr;
reg [7 : 0] depth;


always @(posedge clk)
begin
   if (wr_en)
      queue[wr_ptr] <= din;
   if (rd_en)
      dout <=

	      #1

	      queue[rd_ptr];
end

always @(posedge clk)
begin
   if (reset) begin
      rd_ptr <= 'h0;
      wr_ptr <= 'h0;
      depth  <= 'h0;
   end
   else begin
      if (wr_en) wr_ptr <= wr_ptr + 'h1;
      if (rd_en) rd_ptr <= rd_ptr + 'h1;
      if (wr_en & ~rd_en) depth <=

				   #1

				   depth + 'h1;
      else if (~wr_en & rd_en) depth <=

				   #1

				   depth - 'h1;
   end
end


assign full = depth == 255;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= 7;
assign empty = depth == 'h0;
assign data_count = depth;


always @(posedge clk)
begin
   if (wr_en && depth == 255 && !rd_en)
      $display($time, " ERROR: Attempt to write to full FIFO: %m");
   if (rd_en && depth == 'h0)
      $display($time, " ERROR: Attempt to read an empty FIFO: %m");
end


endmodule