data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv
 line:20: before: "$"
1: b'%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_sim.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_sim);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:19: Unsupported: Ignoring delay on this delayed statement.\n    #1000000\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:24: Unsupported: Ignoring delay on this delayed statement.\n    initial #(RATE*10) reset <= 1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:27: Unsupported: Ignoring delay on this delayed statement.\n    always  #(RATE/2.0) clk  = ~clk;\n            ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:41: Unsupported: Verilog 1995 force\n        force i_sim_main.i_top.i_design_1.reset = reset;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:42: Unsupported: Verilog 1995 force\n        force i_sim_main.i_top.i_design_1.clk   = clk;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:72: Unsupported: Verilog 1995 force\n        force i_sim_main.i_top.i_design_1.wb_adr_i = wb_adr_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:73: Unsupported: Verilog 1995 force\n        force i_sim_main.i_top.i_design_1.wb_dat_i = wb_dat_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:74: Unsupported: Verilog 1995 force\n        force i_sim_main.i_top.i_design_1.wb_we_i  = wb_we_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:75: Unsupported: Verilog 1995 force\n        force i_sim_main.i_top.i_design_1.wb_sel_i = wb_sel_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:76: Unsupported: Verilog 1995 force\n        force i_sim_main.i_top.i_design_1.wb_stb_i = wb_stb_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:96: syntax error, unexpected \'@\'\n       @(negedge wb_clk_i);\n       ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:102: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:104: syntax error, unexpected \'@\'\n                @(negedge wb_clk_i);\n                ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:118: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:124: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:126: syntax error, unexpected \'@\'\n                @(negedge wb_clk_i);\n                ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:312: syntax error, unexpected \'@\'\n    @(negedge wb_rst_i);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:313: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:314: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- timer start --- ", ++test_num);\n                                              ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:318: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:320: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- initialize --- ", ++test_num);\n                                             ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:333: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:334: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- wup_tsk --- ", ++test_num);\n                                          ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:339: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:358: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:359: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- sus_tsk --- ", ++test_num);\n                                          ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:377: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:378: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- busy test --- ", ++test_num);\n                                            ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:384: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:385: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- dly_tsk1 --- ", ++test_num);\n                                           ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:394: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:399: Unsupported: Ignoring delay on this delayed statement.\n    #300;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:403: Unsupported: Ignoring delay on this delayed statement.\n    #300;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:409: Unsupported: Ignoring delay on this delayed statement.\n    #500;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:410: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- dly_tsk2 --- ", ++test_num);\n                                           ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:429: Unsupported: Ignoring delay on this delayed statement.\n    #300;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:432: Unsupported: Ignoring delay on this delayed statement.\n    #300;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:443: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:444: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- wai_flg --- ", ++test_num);\n                                          ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:454: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:459: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:464: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:468: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:475: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- wai_sem --- ", ++test_num);\n                                          ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:474: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:482: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:487: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:491: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:493: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:497: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:503: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- wai_sem2 --- ", ++test_num);\n                                           ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:502: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:532: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- wai_sem3 --- ", ++test_num);\n                                           ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:531: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:550: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- pol_sem --- ", ++test_num);\n                                          ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:549: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:558: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:559: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- ext flg --- ", ++test_num);\n                                          ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:568: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:576: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:577: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- MAX_ID --- ", ++test_num);\n                                         ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:603: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:604: syntax error, unexpected ++, expecting TYPE-IDENTIFIER\n        $display("[%d] --- twai_sem --- ", ++test_num);\n                                           ^~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:624: Unsupported: Ignoring delay on this delayed statement.\n    #300\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:645: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim.sv:649: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: Exiting due to 31 error(s), 37 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function [WB_ADR_WIDTH-1:0] make_addr(bit [OPCODE_WIDTH-1:0] opcode, int id);
    begin
        make_addr = '0;
        make_addr[DECODE_OPCODE_POS +: OPCODE_WIDTH] = OPCODE_WIDTH'(opcode);
        make_addr[DECODE_ID_POS     +: ID_WIDTH]     = ID_WIDTH'(id);
    end
    endfunction
function [WB_ADR_WIDTH-1:0] make_addr(bit [OPCODE_WIDTH-1:0] opcode, int id);

    begin
        make_addr = '0;
        make_addr[DECODE_OPCODE_POS +: OPCODE_WIDTH] = OPCODE_WIDTH'(opcode);
        make_addr[DECODE_ID_POS     +: ID_WIDTH]     = ID_WIDTH'(id);
    end
    endfunction