data/full_repos/permissive/205769493/src/pc.v
1: b"%Error: data/full_repos/permissive/205769493/src/pc.v:27: Cannot find file containing module: 'm_8bit_plus1_adder'\n m_8bit_plus1_adder add_pc (w_bus_pc_plus1, w_bus_addr_pc_out);\n ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205769493/src,data/full_repos/permissive/205769493/m_8bit_plus1_adder\n             data/full_repos/permissive/205769493/src,data/full_repos/permissive/205769493/m_8bit_plus1_adder.v\n             data/full_repos/permissive/205769493/src,data/full_repos/permissive/205769493/m_8bit_plus1_adder.sv\n             m_8bit_plus1_adder\n             m_8bit_plus1_adder.v\n             m_8bit_plus1_adder.sv\n             obj_dir/m_8bit_plus1_adder\n             obj_dir/m_8bit_plus1_adder.v\n             obj_dir/m_8bit_plus1_adder.sv\n%Error: data/full_repos/permissive/205769493/src/pc.v:28: Cannot find file containing module: 'm_2to1_8bit_mux'\n m_2to1_8bit_mux pc_mux (w_bus_mux_out, w_bus_pc_plus1, w_bus_jump_addr, w_channel);\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module m_pc_reg (r_bus_addr_out, w_bus_addr_in, w_clock, w_reset);
	input [7:0] w_bus_addr_in;
	input w_clock, w_reset;

	output reg [7:0] r_bus_addr_out;

	always @ (posedge w_clock)
		if (w_reset) r_bus_addr_out <= 8'b0;
		else r_bus_addr_out <= w_bus_addr_in;
endmodule
module m_pc_reg (r_bus_addr_out, w_bus_addr_in, w_clock, w_reset);

	input [7:0] w_bus_addr_in;
	input w_clock, w_reset;

	output reg [7:0] r_bus_addr_out;

	always @ (posedge w_clock)
		if (w_reset) r_bus_addr_out <= 8'b0;
		else r_bus_addr_out <= w_bus_addr_in;
endmodule