data/full_repos/permissive/167856740/cpu/tb/add_tb.v
 line:28: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/add_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/add_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #10 source_2 = 32\'h00000001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/add_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/add_tb.v:13: Cannot find file containing module: \'add\'\n    add add(.I_data1(source_1), .I_data2(source_2), .O_data(destination));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/add\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/add.v\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/add.sv\n             add\n             add.v\n             add.sv\n             obj_dir/add\n             obj_dir/add.v\n             obj_dir/add.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module add_tb;
	

	reg clk;
    reg [31:0] source_1;
    reg [31:0] source_2;
    wire [31:0] destination;


    add add(.I_data1(source_1), .I_data2(source_2), .O_data(destination));
    

	always begin
		#5 clk = ~clk;
	end

	initial begin

        clk = 1; source_1 = 32'h00000001; source_2 = 32'h00000000;
        

		#10 source_2 = 32'h00000001;
		

		#10 $finish;
	end
	
endmodule
module add_tb;

	

	reg clk;
    reg [31:0] source_1;
    reg [31:0] source_2;
    wire [31:0] destination;


    add add(.I_data1(source_1), .I_data2(source_2), .O_data(destination));
    

	always begin
		#5 clk = ~clk;
	end

	initial begin

        clk = 1; source_1 = 32'h00000001; source_2 = 32'h00000000;
        

		#10 source_2 = 32'h00000001;
		

		#10 $finish;
	end
	
endmodule