data/full_repos/permissive/174369527/FF/ff_tb.v
 line:7: before: "="
1: b'%Error: data/full_repos/permissive/174369527/FF/ff_tb.v:1: Cannot find include file: ff-rtl.v\n`include "ff-rtl.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174369527/FF,data/full_repos/permissive/174369527/ff-rtl.v\n             data/full_repos/permissive/174369527/FF,data/full_repos/permissive/174369527/ff-rtl.v.v\n             data/full_repos/permissive/174369527/FF,data/full_repos/permissive/174369527/ff-rtl.v.sv\n             ff-rtl.v\n             ff-rtl.v.v\n             ff-rtl.v.sv\n             obj_dir/ff-rtl.v\n             obj_dir/ff-rtl.v.v\n             obj_dir/ff-rtl.v.sv\n%Error: data/full_repos/permissive/174369527/FF/ff_tb.v:21: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("mydump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/174369527/FF/ff_tb.v:22: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, uut);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174369527/FF/ff_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174369527/FF/ff_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/FF/ff_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/FF/ff_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/FF/ff_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/FF/ff_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/FF/ff_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/FF/ff_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/FF/ff_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: Exiting due to 3 error(s), 9 warning(s)\n'
module alu_tb;

	reg r_clk = 1'b0;

	reg d = 1'b0;
	wire q;

	ff uut (
		.d(d),
		.q(q),
		.clk(r_clk)
		);
	
	initial begin
	$dumpfile("mydump.vcd");
	$dumpvars(0, uut);
	$display("Start simulation");
	r_clk = 1'b0;
	d = 1'b0;
	#3;
	d = 1'b1;
	#3;
	r_clk = 1'b1;
	#3;
	r_clk = 1'b0;
	#3;
	d = 1'b0;
	#3;
	r_clk = 1'b1;
	#3;
	r_clk = 1'b0;
	#3;
	r_clk = 1'b1;
	#3;
	r_clk = 1'b0;
	#3;
	$display("Finished");
	$finish;
	end

endmodule
module alu_tb;


	reg r_clk = 1'b0;

	reg d = 1'b0;
	wire q;

	ff uut (
		.d(d),
		.q(q),
		.clk(r_clk)
		);
	
	initial begin
	$dumpfile("mydump.vcd");
	$dumpvars(0, uut);
	$display("Start simulation");
	r_clk = 1'b0;
	d = 1'b0;
	#3;
	d = 1'b1;
	#3;
	r_clk = 1'b1;
	#3;
	r_clk = 1'b0;
	#3;
	d = 1'b0;
	#3;
	r_clk = 1'b1;
	#3;
	r_clk = 1'b0;
	#3;
	r_clk = 1'b1;
	#3;
	r_clk = 1'b0;
	#3;
	$display("Finished");
	$finish;
	end

endmodule