data/full_repos/permissive/117436613/testbench/alu_test.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/117436613/testbench/alu_test.sv:1: Cannot find include file: mmix_defs.sv\n`include "mmix_defs.sv" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117436613/testbench,data/full_repos/permissive/117436613/mmix_defs.sv\n             data/full_repos/permissive/117436613/testbench,data/full_repos/permissive/117436613/mmix_defs.sv.v\n             data/full_repos/permissive/117436613/testbench,data/full_repos/permissive/117436613/mmix_defs.sv.sv\n             mmix_defs.sv\n             mmix_defs.sv.v\n             mmix_defs.sv.sv\n             obj_dir/mmix_defs.sv\n             obj_dir/mmix_defs.sv.v\n             obj_dir/mmix_defs.sv.sv\n%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/alu_test.sv:40: Unsupported: Ignoring delay on this delayed statement.\n always #20\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/alu_test.sv:48: Unsupported: Ignoring delay on this delayed statement.\n  #80 reset_n <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/alu_test.sv:49: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/alu_test.sv:51: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/alu_test.sv:57: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/alu_test.sv:62: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/117436613/testbench/alu_test.sv:66: syntax error, unexpected \'@\'\n  repeat(2) @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/117436613/testbench/alu_test.sv:71: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/117436613/testbench/alu_test.sv:74: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/117436613/testbench/alu_test.sv:77: syntax error, unexpected \'@\'\n  repeat(2) @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/117436613/testbench/alu_test.sv:82: syntax error, unexpected \'@\'\n  repeat(2) @(posedge clk);\n            ^\n%Error: Exiting due to 9 error(s), 3 warning(s)\n'
module alu_test(
	);

	logic			clk = 0;
	logic		reset_n;
	logic		enable;
	
	control			data;
	
	logic[63:0]		y, z;
	logic				y_valid, z_valid;
	
	logic			regwe;
	logic[7:0]		regwa;
	logic[63:0]	regwd;

	logic			cf;
	logic			done;
	
	al_unit dut(
	   .clk,
		.reset_n,
		.enable,
		
		.data,
		
		.y, .z,
		.y_valid, .z_valid,
		
		.regwe,
		.regwa,
		.regwd,

		.cf,
		.done
		);
		
	always #20
		clk <= ~clk;
	
	initial begin
		reset_n <= 0;
		enable <= 0;
		y_valid <= 0;
		z_valid <= 0;
		#80 reset_n <= 1;
		#40;

		@(posedge clk);
		enable <= 1;
		data.i <= orn;
		y <= 'b0011;
		z <= 'b0101;
		y_valid <= 1;
		@(posedge clk);
		z_valid <= 1;
		enable <= 1;
		
		while (done == 0)
			@(posedge clk);
		
		enable <= 0;
		
		repeat(2) @(posedge clk);
		
		enable <= 1;
		data.i <= xor_;

		  @(posedge clk);
		data.i <= and_;

		  @(posedge clk);
		 enable <= 0;

  repeat(2) @(posedge clk);
  		 
		 data.i <= unsav;
		 enable <= 1;
		 
  repeat(2) @(posedge clk);
  		 
		 enable <= 0;
		 

	end
	
endmodule
module alu_test(
	);


	logic			clk = 0;
	logic		reset_n;
	logic		enable;
	
	control			data;
	
	logic[63:0]		y, z;
	logic				y_valid, z_valid;
	
	logic			regwe;
	logic[7:0]		regwa;
	logic[63:0]	regwd;

	logic			cf;
	logic			done;
	
	al_unit dut(
	   .clk,
		.reset_n,
		.enable,
		
		.data,
		
		.y, .z,
		.y_valid, .z_valid,
		
		.regwe,
		.regwa,
		.regwd,

		.cf,
		.done
		);
		
	always #20
		clk <= ~clk;
	
	initial begin
		reset_n <= 0;
		enable <= 0;
		y_valid <= 0;
		z_valid <= 0;
		#80 reset_n <= 1;
		#40;

		@(posedge clk);
		enable <= 1;
		data.i <= orn;
		y <= 'b0011;
		z <= 'b0101;
		y_valid <= 1;
		@(posedge clk);
		z_valid <= 1;
		enable <= 1;
		
		while (done == 0)
			@(posedge clk);
		
		enable <= 0;
		
		repeat(2) @(posedge clk);
		
		enable <= 1;
		data.i <= xor_;

		  @(posedge clk);
		data.i <= and_;

		  @(posedge clk);
		 enable <= 0;

  repeat(2) @(posedge clk);
  		 
		 data.i <= unsav;
		 enable <= 1;
		 
  repeat(2) @(posedge clk);
  		 
		 enable <= 0;
		 

	end
	
endmodule