data/full_repos/permissive/175808891/verilog/rv32cpu.v
1: b"%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:234: syntax error, unexpected type\n    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));\n                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:285: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\nmodule shifter(input[31:0] a, input [4:0] shamt, input[1:0] type,  output [31:0] r);\n                                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:288: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:343: syntax error, unexpected ',', expecting IDENTIFIER or do or final\n input   wire            int,\n                            ^\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:345: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input   wire            nmi\n ^~~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:369: syntax error, unexpected always\nalways @(posedge clk or posedge rst)\n^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module CPU (
	input   wire          clk, 
	input   wire          rst, 
	output  wire	[31:0] 	mAddr, 
	output  wire	[31:0] 	mDo, 
	input   wire	[31:0] 	mDi, 
	output  wire    [1:0]   mSize,
	output  wire		    mWr,
	output  wire	[4:0] 	rfRS1, 
	output  wire	[4:0] 	rfRS2, 
	output  wire	[4:0] 	rfRD, 
	input   wire	[31:0] 	rfD1, 
	input   wire	[31:0] 	rfD2,
	output  wire	[31:0]	rfWD,
	output  wire			rfWr,
	input   wire            int,
	output  wire    [2:0]   int_num,
	input   wire            nmi
);


reg	[31:0]	IR;				
reg	[31:0]	I, R1, R2, iPC, ftPC;
reg	[31:0] 	MD, R, RA;
reg 		cycle;


wire [31:0] w_PC, w_ftPC, w_iPC, w_Imm, w_TA;
wire 		c_PC_load;


wire [31:0]	w_ALU_A, w_ALU_B, w_ALU_R, w_MEM_Do, w_RA;
wire 		w_ALU_cf, w_ALU_zf, w_ALU_sf, w_ALU_vf;
wire [3:0]	c_ALU_fn;
wire 		c_ALU_A_sel, c_ALU_B_sel, c_Mem_Do_sel, c_RA_sel, c_TA_sel, c_ALU_A_fwd, c_ALU_B_fwd;
wire [1:0]	c_PC_sel;


wire [31:0]	w_WB_mux;
wire [1:0] c_WB_sel;

always @(posedge clk or posedge rst)
	if(rst)
		cycle <= 0;
	else 
		cycle <= ~ cycle;



PCUnit pcu (
	.clk(clk),
	.rst(rst),
	.TA(w_TA),
	.Imm(w_Imm),
	.PC(w_PC),
	.ftPC(w_ftPC),
	.iPC(w_iPC),
	.load(c_PC_load),
	.sel(c_PC_sel)			
);

IMMGen igen(
    .IR(IR),
    .Imm(w_Imm)
);

DEC dec (
	.IR(IR),
    .PC_load(c_PC_load),
	.PC_sel(c_PC_sel),
	.ALU_fn(),
	.ALU_A_sel(), 
	.ALU_B_sel(), 
	.Mem_Do_sel(), 
	.RA_sel(), 
	.TA_sel(), 
	.ALU_A_fwd(), 
	.ALU_B_fwd(),
	.WB_sel()
);

always @(posedge clk or posedge rst)
	if(rst) IR <= 0;
	else if(cycle == 1'b0) IR <= mDi;

always @(posedge clk or posedge rst)
	if(rst) R1 <= 0;
	else if(cycle == 1'b1) R1 <= rfD1;

always @(posedge clk or posedge rst)
	if(rst) R2 <= 0;
	else if(cycle == 1'b1) R2 <= rfD1;

always @(posedge clk or posedge rst)
	if(rst) I <= 0;
	else if(cycle) I <= w_Imm;

always @(posedge clk or posedge rst)
	if(rst) iPC <= 0;
	else if(cycle) iPC <= w_iPC;

always @(posedge clk or posedge rst)
	if(rst) ftPC <= 0;
	else if(cycle) ftPC <= w_ftPC;
	

ALU alu(
	.a(w_ALU_A), 
	.b(w_ALU_B),
	.shamt(),
	.r(w_ALU_R),
	.cf(w_ALU_cf), .zf(w_ALU_zf), .vf(w_ALU_vf), .sf(w_ALU_sf),
	.alufn(c_ALU_fn)
);

assign w_ALU_A	=	(c_ALU_A_fwd) ? w_WB_mux : R1;
assign w_ALU_B	=	(c_ALU_B_fwd) ? w_WB_mux : (c_ALU_B_sel) ? R2 : I;

always @(posedge clk or posedge rst)
	if(rst) R <= 0;
	else if(cycle) R <= w_ALU_R;

always @(posedge clk or posedge rst)
	if(rst) RA <= 0;
	else if(cycle) RA <= w_RA;

always @(posedge clk or posedge rst)
	if(rst) MD <= 0;
	else if(cycle) MD <= mDi;


assign	w_WB_mux =	(c_WB_sel[0]) ? R : 
					(c_WB_sel[1]) ? MD : RA;


endmodule
module CPU (
	input   wire          clk, 
	input   wire          rst, 
	output  wire	[31:0] 	mAddr, 
	output  wire	[31:0] 	mDo, 
	input   wire	[31:0] 	mDi, 
	output  wire    [1:0]   mSize,
	output  wire		    mWr,
	output  wire	[4:0] 	rfRS1, 
	output  wire	[4:0] 	rfRS2, 
	output  wire	[4:0] 	rfRD, 
	input   wire	[31:0] 	rfD1, 
	input   wire	[31:0] 	rfD2,
	output  wire	[31:0]	rfWD,
	output  wire			rfWr,
	input   wire            int,
	output  wire    [2:0]   int_num,
	input   wire            nmi
);



reg	[31:0]	IR;				
reg	[31:0]	I, R1, R2, iPC, ftPC;
reg	[31:0] 	MD, R, RA;
reg 		cycle;


wire [31:0] w_PC, w_ftPC, w_iPC, w_Imm, w_TA;
wire 		c_PC_load;


wire [31:0]	w_ALU_A, w_ALU_B, w_ALU_R, w_MEM_Do, w_RA;
wire 		w_ALU_cf, w_ALU_zf, w_ALU_sf, w_ALU_vf;
wire [3:0]	c_ALU_fn;
wire 		c_ALU_A_sel, c_ALU_B_sel, c_Mem_Do_sel, c_RA_sel, c_TA_sel, c_ALU_A_fwd, c_ALU_B_fwd;
wire [1:0]	c_PC_sel;


wire [31:0]	w_WB_mux;
wire [1:0] c_WB_sel;

always @(posedge clk or posedge rst)
	if(rst)
		cycle <= 0;
	else 
		cycle <= ~ cycle;



PCUnit pcu (
	.clk(clk),
	.rst(rst),
	.TA(w_TA),
	.Imm(w_Imm),
	.PC(w_PC),
	.ftPC(w_ftPC),
	.iPC(w_iPC),
	.load(c_PC_load),
	.sel(c_PC_sel)			
);

IMMGen igen(
    .IR(IR),
    .Imm(w_Imm)
);

DEC dec (
	.IR(IR),
    .PC_load(c_PC_load),
	.PC_sel(c_PC_sel),
	.ALU_fn(),
	.ALU_A_sel(), 
	.ALU_B_sel(), 
	.Mem_Do_sel(), 
	.RA_sel(), 
	.TA_sel(), 
	.ALU_A_fwd(), 
	.ALU_B_fwd(),
	.WB_sel()
);

always @(posedge clk or posedge rst)
	if(rst) IR <= 0;
	else if(cycle == 1'b0) IR <= mDi;

always @(posedge clk or posedge rst)
	if(rst) R1 <= 0;
	else if(cycle == 1'b1) R1 <= rfD1;

always @(posedge clk or posedge rst)
	if(rst) R2 <= 0;
	else if(cycle == 1'b1) R2 <= rfD1;

always @(posedge clk or posedge rst)
	if(rst) I <= 0;
	else if(cycle) I <= w_Imm;

always @(posedge clk or posedge rst)
	if(rst) iPC <= 0;
	else if(cycle) iPC <= w_iPC;

always @(posedge clk or posedge rst)
	if(rst) ftPC <= 0;
	else if(cycle) ftPC <= w_ftPC;
	

ALU alu(
	.a(w_ALU_A), 
	.b(w_ALU_B),
	.shamt(),
	.r(w_ALU_R),
	.cf(w_ALU_cf), .zf(w_ALU_zf), .vf(w_ALU_vf), .sf(w_ALU_sf),
	.alufn(c_ALU_fn)
);

assign w_ALU_A	=	(c_ALU_A_fwd) ? w_WB_mux : R1;
assign w_ALU_B	=	(c_ALU_B_fwd) ? w_WB_mux : (c_ALU_B_sel) ? R2 : I;

always @(posedge clk or posedge rst)
	if(rst) R <= 0;
	else if(cycle) R <= w_ALU_R;

always @(posedge clk or posedge rst)
	if(rst) RA <= 0;
	else if(cycle) RA <= w_RA;

always @(posedge clk or posedge rst)
	if(rst) MD <= 0;
	else if(cycle) MD <= mDi;


assign	w_WB_mux =	(c_WB_sel[0]) ? R : 
					(c_WB_sel[1]) ? MD : RA;


endmodule