data/full_repos/permissive/184916587/OLD/Decoder.v
 line:167: before: "module"
1: b'%Error: Unsupported: module decls within module decls\n%Error: data/full_repos/permissive/184916587/OLD/Decoder.v:178: syntax error, unexpected $end\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module typecode_decoder(

	input[31:0] instr,
	output[6:0] type_code,
	output[9:0] alu_op,
	output[4:0] rs1,
	output[4:0] rs2,
	output[4:0] rd,

	output[9:0] R_alu_op_out,
	output[4:0] R_rs1_out,
	output[4:0] R_rs2_out,
	output[4:0] R_rd_out
);

	assign type_code=instr[6:0];

	R_type_decode R_type_dec(
		.instr(instr),
		.alu_op(R_alu_op_out),
		.rs1(R_rs1_out),
		.rs2(R_rs2_out),
		.rd(R_rd_out)
	);

	reg[9:0] alu_op_temp;
	reg[4:0] rs1_temp;
	reg[4:0] rs2_temp;
	reg[4:0] rd_temp;


	always @(*)
	begin
		if(type_code===7'b0110011)
			alu_op_temp=R_alu_op_out;
			rs1_temp=R_rs1_out;
			rs2_temp=R_rs2_out;
			rd_temp=R_rd_out;
	end

	assign alu_op=alu_op_temp;
	assign rs1=rs1_temp;
	assign rs2=rs2_temp;
	assign rd=rd_temp;

endmodule
module typecode_decoder(

	input[31:0] instr,
	output[6:0] type_code,
	output[9:0] alu_op,
	output[4:0] rs1,
	output[4:0] rs2,
	output[4:0] rd,

	output[9:0] R_alu_op_out,
	output[4:0] R_rs1_out,
	output[4:0] R_rs2_out,
	output[4:0] R_rd_out
);


	assign type_code=instr[6:0];

	R_type_decode R_type_dec(
		.instr(instr),
		.alu_op(R_alu_op_out),
		.rs1(R_rs1_out),
		.rs2(R_rs2_out),
		.rd(R_rd_out)
	);

	reg[9:0] alu_op_temp;
	reg[4:0] rs1_temp;
	reg[4:0] rs2_temp;
	reg[4:0] rd_temp;


	always @(*)
	begin
		if(type_code===7'b0110011)
			alu_op_temp=R_alu_op_out;
			rs1_temp=R_rs1_out;
			rs2_temp=R_rs2_out;
			rd_temp=R_rd_out;
	end

	assign alu_op=alu_op_temp;
	assign rs1=rs1_temp;
	assign rs2=rs2_temp;
	assign rd=rd_temp;

endmodule