data/full_repos/permissive/175393019/rtl/xseven_seg_display.v
 line:8: before: "="
data/verilator_xmls/cd53bf9e-d740-4f24-9eec-435ae766228d.xml
module xseven_seg_display(
    input clk,
    input reset,
    output reg [3:0] Anode_Activate= 4'b0,
    output reg [6:0] LED_out=7'h0,
	 input btn,
	 input dp,
     input display_sel,
	 input [31:0] displayed_number

	 );
	 
	 reg [15:0] displayed_number1 = 16'h0;
	 reg [22:0] cnt = 0;

    reg [3:0] LED_BCD = 4'h0 ;
    reg [19:0] refresh_counter= 20'h0;

    wire [1:0] LED_activating_counter; 



				 


    always @(posedge clk)
    begin 
	 
	 if (display_sel==1'b1) begin
						if 	(btn==1)
							displayed_number1= displayed_number[31:16];
							else
							displayed_number1= displayed_number[15:0];
					end
	 
	 
	 
	 
	 
	 
	 
	 
	 
			if (refresh_counter==20'hFFFFF) begin
					refresh_counter <= 0;
				end
        else
            refresh_counter <= refresh_counter + 1;
    end 

    always @(posedge clk)
    begin
        case(refresh_counter[19:18])
        2'b00: begin
            Anode_Activate = 4'b0111; 


            LED_BCD <=displayed_number1[15:12];

              end
        2'b01: begin
            Anode_Activate = 4'b1011; 


            LED_BCD<=   displayed_number1[11:8];

              end
        2'b10: begin
            Anode_Activate = 4'b1101; 


            LED_BCD<=   displayed_number1[7:4];

                end
        2'b11: begin
            Anode_Activate = 4'b1110; 


            LED_BCD <=displayed_number1[3:0];

               end
        default: begin
            Anode_Activate = 4'b0111; 


            LED_BCD <=displayed_number1[15:12];

              end
        endcase
    end

    always @(posedge clk)
    begin
        case(LED_BCD)
        4'b0000: LED_out = 7'b1000000;
        4'b0001: LED_out = 7'b1111001;
        4'b0010: LED_out = 7'b0100100;
        4'b0011: LED_out = 7'b0110000;
        4'b0100: LED_out = 7'b0011001;
        4'b0101: LED_out = 7'b0010010;
        4'b0110: LED_out = 7'b0000010;
        4'b0111: LED_out = 7'b1111000;
        4'b1000: LED_out = 7'b0000000;
        4'b1001: LED_out = 7'b0010000;
        4'b1010: LED_out = 7'b0001000;
        4'b1011: LED_out = 7'b0000011;
        4'b1100: LED_out = 7'b1000110;
        4'b1101: LED_out = 7'b0100001;
        4'b1110: LED_out = 7'b0000110;
        4'b1111: LED_out = 7'b0001110;
        default: LED_out = 7'b1000000;
        endcase
    end
	 
endmodule
module xseven_seg_display(
    input clk,
    input reset,
    output reg [3:0] Anode_Activate= 4'b0,
    output reg [6:0] LED_out=7'h0,
	 input btn,
	 input dp,
     input display_sel,
	 input [31:0] displayed_number

	 );

	 
	 reg [15:0] displayed_number1 = 16'h0;
	 reg [22:0] cnt = 0;

    reg [3:0] LED_BCD = 4'h0 ;
    reg [19:0] refresh_counter= 20'h0;

    wire [1:0] LED_activating_counter; 



				 


    always @(posedge clk)
    begin 
	 
	 if (display_sel==1'b1) begin
						if 	(btn==1)
							displayed_number1= displayed_number[31:16];
							else
							displayed_number1= displayed_number[15:0];
					end
	 
	 
	 
	 
	 
	 
	 
	 
	 
			if (refresh_counter==20'hFFFFF) begin
					refresh_counter <= 0;
				end
        else
            refresh_counter <= refresh_counter + 1;
    end 

    always @(posedge clk)
    begin
        case(refresh_counter[19:18])
        2'b00: begin
            Anode_Activate = 4'b0111; 


            LED_BCD <=displayed_number1[15:12];

              end
        2'b01: begin
            Anode_Activate = 4'b1011; 


            LED_BCD<=   displayed_number1[11:8];

              end
        2'b10: begin
            Anode_Activate = 4'b1101; 


            LED_BCD<=   displayed_number1[7:4];

                end
        2'b11: begin
            Anode_Activate = 4'b1110; 


            LED_BCD <=displayed_number1[3:0];

               end
        default: begin
            Anode_Activate = 4'b0111; 


            LED_BCD <=displayed_number1[15:12];

              end
        endcase
    end

    always @(posedge clk)
    begin
        case(LED_BCD)
        4'b0000: LED_out = 7'b1000000;
        4'b0001: LED_out = 7'b1111001;
        4'b0010: LED_out = 7'b0100100;
        4'b0011: LED_out = 7'b0110000;
        4'b0100: LED_out = 7'b0011001;
        4'b0101: LED_out = 7'b0010010;
        4'b0110: LED_out = 7'b0000010;
        4'b0111: LED_out = 7'b1111000;
        4'b1000: LED_out = 7'b0000000;
        4'b1001: LED_out = 7'b0010000;
        4'b1010: LED_out = 7'b0001000;
        4'b1011: LED_out = 7'b0000011;
        4'b1100: LED_out = 7'b1000110;
        4'b1101: LED_out = 7'b0100001;
        4'b1110: LED_out = 7'b0000110;
        4'b1111: LED_out = 7'b0001110;
        default: LED_out = 7'b1000000;
        endcase
    end
	 
endmodule