data/full_repos/permissive/175808891/verilog/approx_mul.v
 line:13: before: "signed"
1: b'%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/approx_mul.v:19: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'y\' generates 32 bits.\n                                                                            : ... In instance mult_bth_app_signed\n        \'b001: pp_generator = y;\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/approx_mul.v:20: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'y\' generates 32 bits.\n                                                                            : ... In instance mult_bth_app_signed\n        \'b010: pp_generator = y;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/approx_mul.v:23: Operator NEGATE expects 64 bits on the LHS, but LHS\'s VARREF \'y\' generates 32 bits.\n                                                                            : ... In instance mult_bth_app_signed\n        \'b101: pp_generator = -y;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/approx_mul.v:24: Operator NEGATE expects 64 bits on the LHS, but LHS\'s VARREF \'y\' generates 32 bits.\n                                                                            : ... In instance mult_bth_app_signed\n        \'b110: pp_generator = -y;\n                              ^\n%Error: Exiting due to 4 warning(s)\n'
function signed [wl*2-1:0] pp_generator;
    input [2:0] part_x;
    input signed [wl-1:0] y;  
    begin
      case( part_x )
        'b000: pp_generator = 0;
        'b001: pp_generator = y;
        'b010: pp_generator = y;
        'b011: pp_generator = 2*y;
        'b100: pp_generator = -(2*y);
        'b101: pp_generator = -y;
        'b110: pp_generator = -y;
        'b111: pp_generator = 0;
      endcase
    end
  endfunction
function signed [wl*2-1:0] pp_generator;

    input [2:0] part_x;
    input signed [wl-1:0] y;  
    begin
      case( part_x )
        'b000: pp_generator = 0;
        'b001: pp_generator = y;
        'b010: pp_generator = y;
        'b011: pp_generator = 2*y;
        'b100: pp_generator = -(2*y);
        'b101: pp_generator = -y;
        'b110: pp_generator = -y;
        'b111: pp_generator = 0;
      endcase
    end
  endfunction