data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv
 line:29: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:35: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2.0);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:37: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2.0);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:86: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:134: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:136: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:140: Unsupported: Ignoring delay on this delayed statement.\n  #(CHECK_DELAY);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:145: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:147: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:154: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:156: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:158: Unsupported: Ignoring delay on this delayed statement.\n  #(CHECK_DELAY);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:163: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:172: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:174: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:177: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:179: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:182: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:184: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:187: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:189: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:191: Unsupported: Ignoring delay on this delayed statement.\n  #(CHECK_DELAY);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:196: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:206: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:209: Unsupported: Ignoring delay on this delayed statement.\n  #(CHECK_DELAY);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_helper.sv:214: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: Exiting due to 19 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_AHB_helper ();



	localparam	CLK_PERIOD  = 35;
	localparam	CHECK_DELAY = 30;

	reg tb_clk;


	
	reg tb_RC4_start,tb_ED_start;
	reg [31:0] tb_RC4_wdata,tb_rdata,tb_ED_wdata,tb_RC4_data, tb_SI_rdata, tb_wdata;
	reg [19:0] tb_RC4_pixNum,tb_ED_wpixNum,tb_SI_rpixNum, tb_pixNum;
	reg [1:0] tb_RC4_mode,tb_ED_mode, tb_size, tb_mode, tb_SI_mode;
	reg tb_data_feedback,tb_RC4_dfb, tb_ED_dfb, tb_SI_dfb, tb_startAddr_sel;

	integer tb_test_num;
	string tb_test;


	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2.0);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2.0);
	end


	AHB_helper DUT
	(
		.RC4_start(tb_RC4_start),
		.ED_start(tb_ED_start),
		.RC4_wdata(tb_RC4_wdata),
		.RC4_pixNum(tb_RC4_pixNum),
		.RC4_mode(tb_RC4_mode),
		.ED_wdata(tb_ED_wdata),
		.ED_wpixNum(tb_ED_wpixNum),
		.ED_mode(tb_ED_mode),
		.SI_rpixNum(tb_SI_rpixNum),
		.rdata(tb_rdata),
		.data_feedback(tb_data_feedback),
		.SI_mode(tb_SI_mode),
		.RC4_rdata(tb_RC4_data),
		.RC4_dfb(tb_RC4_dfb),
		.ED_dfb(tb_ED_dfb),
		.SI_rdata(tb_SI_rdata),
		.SI_dfb(tb_SI_dfb),
		.startAddr_sel(tb_startAddr_sel),
		.wdata(tb_wdata),
		.size(tb_size),
		.mode(tb_mode),
		.pixNum(tb_pixNum)
	);


	initial
	begin

		tb_RC4_start 		= 1'b0;
		tb_ED_start 		= 1'b0;
		tb_RC4_wdata 		= '0;
		tb_RC4_pixNum 		= '0;
		tb_RC4_mode 		= '0;
		tb_ED_wdata 		= '0;
		tb_ED_wpixNum 		='0;
		tb_ED_mode 		= '0;
		tb_SI_mode 		= '0;
		tb_SI_rpixNum 		= '0;
		tb_rdata 		= '0; 
		tb_data_feedback 	= 1'b0;


		tb_test_num 	= 0;
		@(posedge tb_clk);
		@(posedge tb_clk);
		




		tb_test_num 	= 3;
		tb_ED_start 	= 1'b1;
		@(posedge tb_clk);
		tb_ED_mode 	= 2'b01;
		@(posedge tb_clk);
		tb_SI_mode = 2'b01;
		tb_SI_rpixNum = 1;
       		
		#(CHECK_DELAY);
		if((tb_pixNum == tb_SI_rpixNum) && (tb_mode == tb_SI_mode) && (tb_size == 2'b10) && (tb_startAddr_sel == 1'b0))
			$info("Test case: Passed");
		else
			$error("Test case: FAILED");
		@(posedge tb_clk);
		tb_SI_mode = 2'b00;
		@(posedge tb_clk);



		tb_test_num 	= 4;
		tb_rdata 	= 1;
		tb_data_feedback = 1'b1;
		@(posedge tb_clk);
		tb_data_feedback = 1'b0;
		@(posedge tb_clk);
       		
		#(CHECK_DELAY);
		if((tb_ED_dfb == tb_data_feedback) && (tb_SI_rdata == tb_rdata))
			$info("PASSED: Successful read successfully told to EdgeDetection");
		else
			$error("FAILED: Insuccessful read successfully told to EdgeDetection");
		@(posedge tb_clk);
		@(posedge tb_clk);



		tb_test_num 	= 5;
		tb_test = "Buffer Fill";
		tb_SI_mode = 2'b01;
		tb_SI_rpixNum 	= 480 + 1;
		@(posedge tb_clk);
		tb_SI_mode = 2'b00;
		@(posedge tb_clk);
		tb_rdata	= 255;
		tb_data_feedback = 1'b1;
		@(posedge tb_clk);
		tb_data_feedback = 1'b0;
		@(posedge tb_clk);
		tb_SI_mode = 2'b01;
		tb_SI_rpixNum 	= (2*480) + 1;
		@(posedge tb_clk);
		tb_SI_mode = 2'b00;
		@(posedge tb_clk);
		tb_rdata	= 512;
		tb_data_feedback = 1'b1;
		@(posedge tb_clk);
		tb_data_feedback = 1'b0;
		@(posedge tb_clk);

		#(CHECK_DELAY);
		if((tb_ED_dfb == tb_data_feedback) && (tb_SI_rdata == tb_rdata))
			$info("PASSED: Successful read successfully told to EdgeDetection");
		else
			$error("FAILED: Insuccessful read successfully told to EdgeDetection");
		@(posedge tb_clk);
		@(posedge tb_clk);




		tb_test_num 	= 6;
		tb_test = "Insuccessful Read";
		tb_rdata[1:0] = 2'b00;
		tb_data_feedback = 1'b0;
		@(posedge tb_clk);
		@(posedge tb_clk);
       		
		#(CHECK_DELAY);
		if((tb_ED_dfb == tb_data_feedback) && (tb_SI_rdata == tb_rdata))
			$info("PASSED: Insuccessful read successfully told to EdgeDetection");
		else
			$error("FAILED: Insuccessful read insuccessfully told to EdgeDetection");
		@(posedge tb_clk);
		@(posedge tb_clk);


	end
endmodule
module tb_AHB_helper ();




	localparam	CLK_PERIOD  = 35;
	localparam	CHECK_DELAY = 30;

	reg tb_clk;


	
	reg tb_RC4_start,tb_ED_start;
	reg [31:0] tb_RC4_wdata,tb_rdata,tb_ED_wdata,tb_RC4_data, tb_SI_rdata, tb_wdata;
	reg [19:0] tb_RC4_pixNum,tb_ED_wpixNum,tb_SI_rpixNum, tb_pixNum;
	reg [1:0] tb_RC4_mode,tb_ED_mode, tb_size, tb_mode, tb_SI_mode;
	reg tb_data_feedback,tb_RC4_dfb, tb_ED_dfb, tb_SI_dfb, tb_startAddr_sel;

	integer tb_test_num;
	string tb_test;


	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2.0);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2.0);
	end


	AHB_helper DUT
	(
		.RC4_start(tb_RC4_start),
		.ED_start(tb_ED_start),
		.RC4_wdata(tb_RC4_wdata),
		.RC4_pixNum(tb_RC4_pixNum),
		.RC4_mode(tb_RC4_mode),
		.ED_wdata(tb_ED_wdata),
		.ED_wpixNum(tb_ED_wpixNum),
		.ED_mode(tb_ED_mode),
		.SI_rpixNum(tb_SI_rpixNum),
		.rdata(tb_rdata),
		.data_feedback(tb_data_feedback),
		.SI_mode(tb_SI_mode),
		.RC4_rdata(tb_RC4_data),
		.RC4_dfb(tb_RC4_dfb),
		.ED_dfb(tb_ED_dfb),
		.SI_rdata(tb_SI_rdata),
		.SI_dfb(tb_SI_dfb),
		.startAddr_sel(tb_startAddr_sel),
		.wdata(tb_wdata),
		.size(tb_size),
		.mode(tb_mode),
		.pixNum(tb_pixNum)
	);


	initial
	begin

		tb_RC4_start 		= 1'b0;
		tb_ED_start 		= 1'b0;
		tb_RC4_wdata 		= '0;
		tb_RC4_pixNum 		= '0;
		tb_RC4_mode 		= '0;
		tb_ED_wdata 		= '0;
		tb_ED_wpixNum 		='0;
		tb_ED_mode 		= '0;
		tb_SI_mode 		= '0;
		tb_SI_rpixNum 		= '0;
		tb_rdata 		= '0; 
		tb_data_feedback 	= 1'b0;


		tb_test_num 	= 0;
		@(posedge tb_clk);
		@(posedge tb_clk);
		




		tb_test_num 	= 3;
		tb_ED_start 	= 1'b1;
		@(posedge tb_clk);
		tb_ED_mode 	= 2'b01;
		@(posedge tb_clk);
		tb_SI_mode = 2'b01;
		tb_SI_rpixNum = 1;
       		
		#(CHECK_DELAY);
		if((tb_pixNum == tb_SI_rpixNum) && (tb_mode == tb_SI_mode) && (tb_size == 2'b10) && (tb_startAddr_sel == 1'b0))
			$info("Test case: Passed");
		else
			$error("Test case: FAILED");
		@(posedge tb_clk);
		tb_SI_mode = 2'b00;
		@(posedge tb_clk);



		tb_test_num 	= 4;
		tb_rdata 	= 1;
		tb_data_feedback = 1'b1;
		@(posedge tb_clk);
		tb_data_feedback = 1'b0;
		@(posedge tb_clk);
       		
		#(CHECK_DELAY);
		if((tb_ED_dfb == tb_data_feedback) && (tb_SI_rdata == tb_rdata))
			$info("PASSED: Successful read successfully told to EdgeDetection");
		else
			$error("FAILED: Insuccessful read successfully told to EdgeDetection");
		@(posedge tb_clk);
		@(posedge tb_clk);



		tb_test_num 	= 5;
		tb_test = "Buffer Fill";
		tb_SI_mode = 2'b01;
		tb_SI_rpixNum 	= 480 + 1;
		@(posedge tb_clk);
		tb_SI_mode = 2'b00;
		@(posedge tb_clk);
		tb_rdata	= 255;
		tb_data_feedback = 1'b1;
		@(posedge tb_clk);
		tb_data_feedback = 1'b0;
		@(posedge tb_clk);
		tb_SI_mode = 2'b01;
		tb_SI_rpixNum 	= (2*480) + 1;
		@(posedge tb_clk);
		tb_SI_mode = 2'b00;
		@(posedge tb_clk);
		tb_rdata	= 512;
		tb_data_feedback = 1'b1;
		@(posedge tb_clk);
		tb_data_feedback = 1'b0;
		@(posedge tb_clk);

		#(CHECK_DELAY);
		if((tb_ED_dfb == tb_data_feedback) && (tb_SI_rdata == tb_rdata))
			$info("PASSED: Successful read successfully told to EdgeDetection");
		else
			$error("FAILED: Insuccessful read successfully told to EdgeDetection");
		@(posedge tb_clk);
		@(posedge tb_clk);




		tb_test_num 	= 6;
		tb_test = "Insuccessful Read";
		tb_rdata[1:0] = 2'b00;
		tb_data_feedback = 1'b0;
		@(posedge tb_clk);
		@(posedge tb_clk);
       		
		#(CHECK_DELAY);
		if((tb_ED_dfb == tb_data_feedback) && (tb_SI_rdata == tb_rdata))
			$info("PASSED: Insuccessful read successfully told to EdgeDetection");
		else
			$error("FAILED: Insuccessful read insuccessfully told to EdgeDetection");
		@(posedge tb_clk);
		@(posedge tb_clk);


	end
endmodule