data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_deserializer_eof2.sv
 line:66 column:26: Illegal character "'"
1: b'%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_deserializer_eof2.sv:62: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'count\' generates 1 bits.\n                                                                                                                : ... In instance stream_deserializer_eof2\n  wire last = (count == Ratio - 1) | in_eof;\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module stream_deserializer_eof2 #(
  parameter DataBits = 8,
  parameter Ratio    = 2)
(
  input                             clk,
  input                             rst,

  input                             in_valid,
  output                            in_ready,
  input [DataBits-1:0]              in_data,
  input                             in_eof,

  output logic                      out_valid,
  input                             out_ready,
  output logic [Ratio*DataBits-1:0] out_data,
  output logic [Ratio-1:0]          out_eof
);

  logic [$clog2(Ratio)-1:0] count;

  wire last = (count == Ratio - 1) | in_eof;

  always_ff @(posedge clk) begin
    if (in_valid & in_ready) begin
      count <= (last) ? '0 : count + 1;
      out_data[count*DataBits +: DataBits] <= in_data;
      out_eof[count]  <= in_eof;
    end

    if (last & in_valid)
      out_valid <= '1;
    else if (out_ready)
      out_valid <= '0;

    if (rst)
      count <= '0;
  end

  assign in_ready = ~out_valid | out_ready;

endmodule
module stream_deserializer_eof2 #(
  parameter DataBits = 8,
  parameter Ratio    = 2)
(
  input                             clk,
  input                             rst,

  input                             in_valid,
  output                            in_ready,
  input [DataBits-1:0]              in_data,
  input                             in_eof,

  output logic                      out_valid,
  input                             out_ready,
  output logic [Ratio*DataBits-1:0] out_data,
  output logic [Ratio-1:0]          out_eof
);


  logic [$clog2(Ratio)-1:0] count;

  wire last = (count == Ratio - 1) | in_eof;

  always_ff @(posedge clk) begin
    if (in_valid & in_ready) begin
      count <= (last) ? '0 : count + 1;
      out_data[count*DataBits +: DataBits] <= in_data;
      out_eof[count]  <= in_eof;
    end

    if (last & in_valid)
      out_valid <= '1;
    else if (out_ready)
      out_valid <= '0;

    if (rst)
      count <= '0;
  end

  assign in_ready = ~out_valid | out_ready;

endmodule