data/full_repos/permissive/143597583/rtl/verilog/testbench.v
 line:90: before: "$"
1: b'%Error: data/full_repos/permissive/143597583/rtl/verilog/testbench.v:83: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143597583/rtl/verilog/testbench.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143597583/rtl/verilog/testbench.v:90: Unsupported: Ignoring delay on this delayed statement.\n  # 80000 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;

	reg clk, rst;

	wire x_ready;
	wire y_valid;

	cmplx_conv # (
	  .aw(6),
	  .ntaps(60),
	  .coeffs("coeffs.dat"))
	dut (
	  .clk(clk),
	  .rst(rst),
	  .x_a_i(x),
	  .x_b_i(x),
	  .x_valid_i(1'b1),
	  .x_ready_o(x_ready),
	  .y_a_o(y),
	  .y_b_o(),
	  .y_valid_o(y_valid),
	  .y_ready_i(1'b1)
	);

	reg [15:0] idx;
	wire [15:0] x;
	wire [15:0] y;



	assign x = (idx[2:0] == 0) ? xx[idx[15:3]] : 0;

	reg [15:0] xx[0:15];


	always @(posedge clk) begin
		if (rst) begin
			idx <= 0;
		end
		else if (x_ready) begin
			idx <= idx + 1;
		end
	end

	initial begin
		xx[0] = 1;
		xx[1] = 1;
		xx[2] = 1;
		xx[3] = 1;
		xx[4] = -1;
		xx[5] = -1;
		xx[6] = -1;
		xx[7] = 1;
		xx[8] = 1;
		xx[9] = -1;
		xx[10] = 1;
		xx[11] = 1;
		xx[12] = -1;
		xx[13] = 1;
		xx[14] = -1;
		xx[15] = 1;

		$dumpvars;
		clk = 0;
		rst = 1;

		#5
		rst = 0;

		# 80000 $finish;
	end

	always clk = #1 ~clk;

	always @(posedge clk) begin
		if (y_valid) begin
			$display("y: %h", y);
		end
	end


endmodule
module tb;


	reg clk, rst;

	wire x_ready;
	wire y_valid;

	cmplx_conv # (
	  .aw(6),
	  .ntaps(60),
	  .coeffs("coeffs.dat"))
	dut (
	  .clk(clk),
	  .rst(rst),
	  .x_a_i(x),
	  .x_b_i(x),
	  .x_valid_i(1'b1),
	  .x_ready_o(x_ready),
	  .y_a_o(y),
	  .y_b_o(),
	  .y_valid_o(y_valid),
	  .y_ready_i(1'b1)
	);

	reg [15:0] idx;
	wire [15:0] x;
	wire [15:0] y;



	assign x = (idx[2:0] == 0) ? xx[idx[15:3]] : 0;

	reg [15:0] xx[0:15];


	always @(posedge clk) begin
		if (rst) begin
			idx <= 0;
		end
		else if (x_ready) begin
			idx <= idx + 1;
		end
	end

	initial begin
		xx[0] = 1;
		xx[1] = 1;
		xx[2] = 1;
		xx[3] = 1;
		xx[4] = -1;
		xx[5] = -1;
		xx[6] = -1;
		xx[7] = 1;
		xx[8] = 1;
		xx[9] = -1;
		xx[10] = 1;
		xx[11] = 1;
		xx[12] = -1;
		xx[13] = 1;
		xx[14] = -1;
		xx[15] = 1;

		$dumpvars;
		clk = 0;
		rst = 1;

		#5
		rst = 0;

		# 80000 $finish;
	end

	always clk = #1 ~clk;

	always @(posedge clk) begin
		if (y_valid) begin
			$display("y: %h", y);
		end
	end


endmodule