data/full_repos/permissive/211891954/Finite States Machine/Maquina de Mealy/Exemplo 1/mealy.v
 line:12: before: "rst"
1: b'%Error: Cannot find file containing module: States\n        ... Looked in:\n             data/full_repos/permissive/211891954/Finite/States\n             data/full_repos/permissive/211891954/Finite/States.v\n             data/full_repos/permissive/211891954/Finite/States.sv\n             States\n             States.v\n             States.sv\n             obj_dir/States\n             obj_dir/States.v\n             obj_dir/States.sv\n%Error: Cannot find file containing module: Machine/Maquina\n%Error: Cannot find file containing module: de\n%Error: Cannot find file containing module: Mealy/Exemplo\n%Error: Cannot find file containing module: 1,data/full_repos/permissive/211891954\n%Error: Cannot find file containing module: data/full_repos/permissive/211891954/Finite\n%Error: Cannot find file containing module: 1/mealy.v\n%Error: Exiting due to 7 error(s)\n'
module odd(clk,rst,in,out);
    input wire clk,rst,in;
    output reg out; 
    reg count = 0;     
    parameter Q0 = 2'b00,
              Q1 = 2'b01,
              Q2 = 2'b10;

    reg[1:0] states;
    reg[1:0] next_state;

    always@(posedge clk or rst or in)begin
        if(rst)begin
            states = Q0;
        end
        else begin
            case(states)
                Q0:begin
                    if(in == 1'b1 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q1;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b1 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q1;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b0 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q0;
                    end

                    else if(in == 1'b0 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q0;
                    end
                end

                Q1:begin
                    if(in == 1'b1 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q2;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b1 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q2;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b0 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q1;
                    end

                    else if(in == 1'b0 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q1;
                    end
                end

                Q2:begin
                    if(in == 1'b1 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q0;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b1 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q0;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b0 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q2;
                    end

                    else if(in == 1'b1 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q2;
                    end
                end
            endcase
        end
    end
endmodule
module odd(clk,rst,in,out);

    input wire clk,rst,in;
    output reg out; 
    reg count = 0;     
    parameter Q0 = 2'b00,
              Q1 = 2'b01,
              Q2 = 2'b10;

    reg[1:0] states;
    reg[1:0] next_state;

    always@(posedge clk or rst or in)begin
        if(rst)begin
            states = Q0;
        end
        else begin
            case(states)
                Q0:begin
                    if(in == 1'b1 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q1;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b1 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q1;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b0 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q0;
                    end

                    else if(in == 1'b0 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q0;
                    end
                end

                Q1:begin
                    if(in == 1'b1 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q2;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b1 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q2;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b0 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q1;
                    end

                    else if(in == 1'b0 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q1;
                    end
                end

                Q2:begin
                    if(in == 1'b1 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q0;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b1 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q0;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b0 && count %3 == 0)begin
                        out = 1'b1;
                        next_state = Q2;
                    end

                    else if(in == 1'b1 && count %3 != 0)begin
                        out = 1'b0;
                        next_state = Q2;
                    end
                end
            endcase
        end
    end
endmodule