data/full_repos/permissive/143278/ivltests/timescale1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/timescale1.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #0 out = 0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/timescale1.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #1 out = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/timescale1.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #0 out = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/timescale1.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #1 out = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/timescale1.v:59: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/timescale1.v:70: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/timescale1.v:81: Unsupported: Ignoring delay on this delayed statement.\n      #80\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/timescale1.v:92: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire slow, fast;

   slow m1 (slow);
   fast m2 (fast);

   initial begin
      #5
	if (slow !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end

        if (fast !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end

      #10
	if (slow !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end

        if (fast !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

      #80
	if (slow !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end

        if (fast !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

      #10
	if (slow !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

        if (fast !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

      $display("PASSED");

   end
endmodule
module main;


   wire slow, fast;

   slow m1 (slow);
   fast m2 (fast);

   initial begin
      #5
	if (slow !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end

        if (fast !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end

      #10
	if (slow !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end

        if (fast !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

      #80
	if (slow !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end

        if (fast !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

      #10
	if (slow !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

        if (fast !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

      $display("PASSED");

   end
endmodule