data/full_repos/permissive/174242803/alu_regf/src/osu05_stdcells.v
 line:13: before: "tpllh$B$Y"
1: b"%Error: data/full_repos/permissive/174242803/alu_regf/src/osu05_stdcells.v:241: syntax error, unexpected '(', expecting IDENTIFIER\n   udp_dff (DS0000, D, I0_CLOCK, 1'B0, 1'B0, NOTIFIER);\n            ^~~~~~\n%Error: data/full_repos/permissive/174242803/alu_regf/src/osu05_stdcells.v:279: syntax error, unexpected '(', expecting IDENTIFIER\n   udp_dff (DS0000, D, CLK, 1'B0, 1'B0, NOTIFIER);\n            ^~~~~~\n%Error: data/full_repos/permissive/174242803/alu_regf/src/osu05_stdcells.v:321: syntax error, unexpected '(', expecting IDENTIFIER\n   udp_dff (P0003, D_, CLK, I0_SET, I0_CLEAR, NOTIFIER);\n            ^~~~~\n%Error: data/full_repos/permissive/174242803/alu_regf/src/osu05_stdcells.v:552: syntax error, unexpected '(', expecting IDENTIFIER\n   udp_tlat (DS0000, D, CLK, 1'B0, 1'B0, NOTIFIER);\n             ^~~~~~\n%Error: data/full_repos/permissive/174242803/alu_regf/src/osu05_stdcells.v:591: syntax error, unexpected '(', expecting IDENTIFIER\n   udp_mux2 (I0_out, B, A, S);\n             ^~~~~~\n%Error: Exiting due to 5 error(s)\n"
module DFFNEGX1 (CLK, D, Q);
input  CLK ;
input  D ;
output Q ;
reg NOTIFIER ;

   not (I0_CLOCK, CLK);
   udp_dff (DS0000, D, I0_CLOCK, 1'B0, 1'B0, NOTIFIER);
   not (P0002, DS0000);
   buf (Q, DS0000);

   specify

     specparam
       tphlh$CLK$Q = 0.27:0.27:0.27,
       tphhl$CLK$Q = 0.24:0.24:0.24,
       tminpwh$CLK = 0.077:0.18:0.27,
       tminpwl$CLK = 0.14:0.2:0.27,
       tsetup_negedge$D$CLK = 0.38:0.38:0.38,
       thold_negedge$D$CLK = -0.094:-0.094:-0.094,
       tsetup_posedge$D$CLK = 0.28:0.28:0.28,
       thold_posedge$D$CLK = -0.094:-0.094:-0.094;


     (CLK *> Q) = (tphlh$CLK$Q, tphhl$CLK$Q);
     $setup(negedge D, negedge CLK, tsetup_negedge$D$CLK, NOTIFIER);
     $hold (negedge D, negedge CLK, thold_negedge$D$CLK,  NOTIFIER);
     $setup(posedge D, negedge CLK, tsetup_posedge$D$CLK, NOTIFIER);
     $hold (posedge D, negedge CLK, thold_posedge$D$CLK,  NOTIFIER);
     $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER);
     $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER);

   endspecify

endmodule
module DFFNEGX1 (CLK, D, Q);

input  CLK ;
input  D ;
output Q ;
reg NOTIFIER ;

   not (I0_CLOCK, CLK);
   udp_dff (DS0000, D, I0_CLOCK, 1'B0, 1'B0, NOTIFIER);
   not (P0002, DS0000);
   buf (Q, DS0000);

   specify

     specparam
       tphlh$CLK$Q = 0.27:0.27:0.27,
       tphhl$CLK$Q = 0.24:0.24:0.24,
       tminpwh$CLK = 0.077:0.18:0.27,
       tminpwl$CLK = 0.14:0.2:0.27,
       tsetup_negedge$D$CLK = 0.38:0.38:0.38,
       thold_negedge$D$CLK = -0.094:-0.094:-0.094,
       tsetup_posedge$D$CLK = 0.28:0.28:0.28,
       thold_posedge$D$CLK = -0.094:-0.094:-0.094;


     (CLK *> Q) = (tphlh$CLK$Q, tphhl$CLK$Q);
     $setup(negedge D, negedge CLK, tsetup_negedge$D$CLK, NOTIFIER);
     $hold (negedge D, negedge CLK, thold_negedge$D$CLK,  NOTIFIER);
     $setup(posedge D, negedge CLK, tsetup_posedge$D$CLK, NOTIFIER);
     $hold (posedge D, negedge CLK, thold_posedge$D$CLK,  NOTIFIER);
     $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER);
     $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER);

   endspecify

endmodule