data/full_repos/permissive/167161024/ad9958_config_register.v
1: b'%Error: data/full_repos/permissive/167161024/ad9958_config_register.v:9: Cannot find include file: ad9958_vars.vh\n`include "ad9958_vars.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167161024,data/full_repos/permissive/167161024/ad9958_vars.vh\n             data/full_repos/permissive/167161024,data/full_repos/permissive/167161024/ad9958_vars.vh.v\n             data/full_repos/permissive/167161024,data/full_repos/permissive/167161024/ad9958_vars.vh.sv\n             ad9958_vars.vh\n             ad9958_vars.vh.v\n             ad9958_vars.vh.sv\n             obj_dir/ad9958_vars.vh\n             obj_dir/ad9958_vars.vh.v\n             obj_dir/ad9958_vars.vh.sv\n%Error: data/full_repos/permissive/167161024/ad9958_config_register.v:20: Define or directive not defined: \'`DAC_FSCALE_HALF\'\n   dac_fscale_ch0 = `DAC_FSCALE_HALF;\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_config_register.v:20: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   dac_fscale_ch0 = `DAC_FSCALE_HALF;\n                                    ^\n%Error: data/full_repos/permissive/167161024/ad9958_config_register.v:21: Define or directive not defined: \'`DAC_FSCALE_HALF\'\n   dac_fscale_ch1 = `DAC_FSCALE_HALF;\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_config_register.v:21: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   dac_fscale_ch1 = `DAC_FSCALE_HALF;\n                                    ^\n%Error: Exiting due to 5 error(s)\n'
module ad9958_config_register(
							  output reg 	   vco_gain,
							  output reg [4:0] clock_multiplier,
							  output reg [1:0] dac_fscale_ch0,
							  output reg [1:0] dac_fscale_ch1
);
   initial begin
	  vco_gain = 1'b1;
	  clock_multiplier = 5'd10;
	  dac_fscale_ch0 = `DAC_FSCALE_HALF;
	  dac_fscale_ch1 = `DAC_FSCALE_HALF;
   end
   
endmodule
module ad9958_config_register(
							  output reg 	   vco_gain,
							  output reg [4:0] clock_multiplier,
							  output reg [1:0] dac_fscale_ch0,
							  output reg [1:0] dac_fscale_ch1
);

   initial begin
	  vco_gain = 1'b1;
	  clock_multiplier = 5'd10;
	  dac_fscale_ch0 = `DAC_FSCALE_HALF;
	  dac_fscale_ch1 = `DAC_FSCALE_HALF;
   end
   
endmodule