data/full_repos/permissive/168753118/rtl/modules/GPR.v
1: b"%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:119: Cannot find file containing module: 'DECODE_F'\nDECODE_F x_decoder(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/168753118/rtl/modules,data/full_repos/permissive/168753118/DECODE_F\n             data/full_repos/permissive/168753118/rtl/modules,data/full_repos/permissive/168753118/DECODE_F.v\n             data/full_repos/permissive/168753118/rtl/modules,data/full_repos/permissive/168753118/DECODE_F.sv\n             DECODE_F\n             DECODE_F.v\n             DECODE_F.sv\n             obj_dir/DECODE_F\n             obj_dir/DECODE_F.v\n             obj_dir/DECODE_F.sv\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:160: Cannot find file containing module: 'REG_NEG'\nREG_NEG x00 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:169: Cannot find file containing module: 'REG_NEG'\nREG_NEG x01 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:178: Cannot find file containing module: 'REG_NEG'\nREG_NEG x02 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:187: Cannot find file containing module: 'REG_NEG'\nREG_NEG x03 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:196: Cannot find file containing module: 'REG_NEG'\nREG_NEG x04 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:205: Cannot find file containing module: 'REG_NEG'\nREG_NEG x05 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:214: Cannot find file containing module: 'REG_NEG'\nREG_NEG x06 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:223: Cannot find file containing module: 'REG_NEG'\nREG_NEG x08 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:232: Cannot find file containing module: 'REG_NEG'\nREG_NEG x09 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:241: Cannot find file containing module: 'REG_NEG'\nREG_NEG x10 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:250: Cannot find file containing module: 'REG_NEG'\nREG_NEG x11 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:259: Cannot find file containing module: 'REG_NEG'\nREG_NEG x12 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:268: Cannot find file containing module: 'REG_NEG'\nREG_NEG x13 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:277: Cannot find file containing module: 'REG_NEG'\nREG_NEG x14 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:286: Cannot find file containing module: 'REG_NEG'\nREG_NEG x15 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:295: Cannot find file containing module: 'REG_NEG'\nREG_NEG x16 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:304: Cannot find file containing module: 'REG_NEG'\nREG_NEG x17 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:313: Cannot find file containing module: 'REG_NEG'\nREG_NEG x18 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:322: Cannot find file containing module: 'REG_NEG'\nREG_NEG x19 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:331: Cannot find file containing module: 'REG_NEG'\nREG_NEG x20 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:340: Cannot find file containing module: 'REG_NEG'\nREG_NEG x21 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:349: Cannot find file containing module: 'REG_NEG'\nREG_NEG x22 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:358: Cannot find file containing module: 'REG_NEG'\nREG_NEG x23 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:367: Cannot find file containing module: 'REG_NEG'\nREG_NEG x24 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:376: Cannot find file containing module: 'REG_NEG'\nREG_NEG x25 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:385: Cannot find file containing module: 'REG_NEG'\nREG_NEG x26 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:394: Cannot find file containing module: 'REG_NEG'\nREG_NEG x27 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:403: Cannot find file containing module: 'REG_NEG'\nREG_NEG x28 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:412: Cannot find file containing module: 'REG_NEG'\nREG_NEG x29 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:421: Cannot find file containing module: 'REG_NEG'\nREG_NEG x30 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:430: Cannot find file containing module: 'REG_NEG'\nREG_NEG x31 (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:439: Cannot find file containing module: 'MUX_F'\nMUX_F rs1_output_mux (\n^~~~~\n%Error: data/full_repos/permissive/168753118/rtl/modules/GPR.v:483: Cannot find file containing module: 'MUX_F'\nMUX_F rs2_output_mux (\n^~~~~\n%Error: Exiting due to 34 error(s)\n"
module GPR (


    input clock_in,
    input reset_in,

    input write_enable_in,
    input [4:0] rs1_addr_in,
    input [4:0] rs2_addr_in,
    input [4:0] rd_addr_in,


    output [31:0] rs1_data_out,
    output [31:0] rs2_data_out,


    input [31:0] rd_data_in

    );





wire int_reg_x00_set_wire;
wire int_reg_x01_set_wire;
wire int_reg_x02_set_wire;
wire int_reg_x03_set_wire;
wire int_reg_x04_set_wire;
wire int_reg_x05_set_wire;
wire int_reg_x06_set_wire;
wire int_reg_x07_set_wire;
wire int_reg_x08_set_wire;
wire int_reg_x09_set_wire;
wire int_reg_x10_set_wire;
wire int_reg_x11_set_wire;
wire int_reg_x12_set_wire;
wire int_reg_x13_set_wire;
wire int_reg_x14_set_wire;
wire int_reg_x15_set_wire;
wire int_reg_x16_set_wire;
wire int_reg_x17_set_wire;
wire int_reg_x18_set_wire;
wire int_reg_x19_set_wire;
wire int_reg_x20_set_wire;
wire int_reg_x21_set_wire;
wire int_reg_x22_set_wire;
wire int_reg_x23_set_wire;
wire int_reg_x24_set_wire;
wire int_reg_x25_set_wire;
wire int_reg_x26_set_wire;
wire int_reg_x27_set_wire;
wire int_reg_x28_set_wire;
wire int_reg_x29_set_wire;
wire int_reg_x30_set_wire;
wire int_reg_x31_set_wire;


wire [31:0] int_reg_x00_data_wire;
wire [31:0] int_reg_x01_data_wire;
wire [31:0] int_reg_x02_data_wire;
wire [31:0] int_reg_x03_data_wire;
wire [31:0] int_reg_x04_data_wire;
wire [31:0] int_reg_x05_data_wire;
wire [31:0] int_reg_x06_data_wire;
wire [31:0] int_reg_x07_data_wire;
wire [31:0] int_reg_x08_data_wire;
wire [31:0] int_reg_x09_data_wire;
wire [31:0] int_reg_x10_data_wire;
wire [31:0] int_reg_x11_data_wire;
wire [31:0] int_reg_x12_data_wire;
wire [31:0] int_reg_x13_data_wire;
wire [31:0] int_reg_x14_data_wire;
wire [31:0] int_reg_x15_data_wire;
wire [31:0] int_reg_x16_data_wire;
wire [31:0] int_reg_x17_data_wire;
wire [31:0] int_reg_x18_data_wire;
wire [31:0] int_reg_x19_data_wire;
wire [31:0] int_reg_x20_data_wire;
wire [31:0] int_reg_x21_data_wire;
wire [31:0] int_reg_x22_data_wire;
wire [31:0] int_reg_x23_data_wire;
wire [31:0] int_reg_x24_data_wire;
wire [31:0] int_reg_x25_data_wire;
wire [31:0] int_reg_x26_data_wire;
wire [31:0] int_reg_x27_data_wire;
wire [31:0] int_reg_x28_data_wire;
wire [31:0] int_reg_x29_data_wire;
wire [31:0] int_reg_x30_data_wire;
wire [31:0] int_reg_x31_data_wire;


wire [31:0] rs1_data_wire;
wire [31:0] rs2_data_wire;







DECODE_F x_decoder(

  .sel_addr_in(rd_addr_in),


  .sel_x00_out(int_reg_x00_set_wire),
  .sel_x01_out(int_reg_x01_set_wire),
  .sel_x02_out(int_reg_x02_set_wire),
  .sel_x03_out(int_reg_x03_set_wire),
  .sel_x04_out(int_reg_x04_set_wire),
  .sel_x05_out(int_reg_x05_set_wire),
  .sel_x06_out(int_reg_x06_set_wire),
  .sel_x07_out(int_reg_x07_set_wire),
  .sel_x08_out(int_reg_x08_set_wire),
  .sel_x09_out(int_reg_x09_set_wire),
  .sel_x10_out(int_reg_x10_set_wire),
  .sel_x11_out(int_reg_x11_set_wire),
  .sel_x12_out(int_reg_x12_set_wire),
  .sel_x13_out(int_reg_x13_set_wire),
  .sel_x14_out(int_reg_x14_set_wire),
  .sel_x15_out(int_reg_x15_set_wire),
  .sel_x16_out(int_reg_x16_set_wire),
  .sel_x17_out(int_reg_x17_set_wire),
  .sel_x18_out(int_reg_x18_set_wire),
  .sel_x19_out(int_reg_x19_set_wire),
  .sel_x20_out(int_reg_x20_set_wire),
  .sel_x21_out(int_reg_x21_set_wire),
  .sel_x22_out(int_reg_x22_set_wire),
  .sel_x23_out(int_reg_x23_set_wire),
  .sel_x24_out(int_reg_x24_set_wire),
  .sel_x25_out(int_reg_x25_set_wire),
  .sel_x26_out(int_reg_x26_set_wire),
  .sel_x27_out(int_reg_x27_set_wire),
  .sel_x28_out(int_reg_x28_set_wire),
  .sel_x29_out(int_reg_x29_set_wire),
  .sel_x30_out(int_reg_x30_set_wire),
  .sel_x31_out(int_reg_x31_set_wire)
);



REG_NEG x00 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x00_set_wire&write_enable_in),
  .data_in(32'h00000000),
  .data_out(int_reg_x00_data_wire)
);


REG_NEG x01 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x01_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x01_data_wire)
);


REG_NEG x02 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x02_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x02_data_wire)
);


REG_NEG x03 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x03_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x03_data_wire)
);


REG_NEG x04 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x04_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x04_data_wire)
);


REG_NEG x05 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x05_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x05_data_wire)
);


REG_NEG x06 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x06_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x06_data_wire)
);


REG_NEG x08 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x08_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x08_data_wire)
);


REG_NEG x09 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x09_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x09_data_wire)
);


REG_NEG x10 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x10_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x10_data_wire)
);


REG_NEG x11 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x11_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x11_data_wire)
);


REG_NEG x12 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x12_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x12_data_wire)
);


REG_NEG x13 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x13_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x13_data_wire)
);


REG_NEG x14 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x14_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x14_data_wire)
);


REG_NEG x15 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x15_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x15_data_wire)
);


REG_NEG x16 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x16_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x16_data_wire)
);


REG_NEG x17 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x17_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x17_data_wire)
);


REG_NEG x18 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x18_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x18_data_wire)
);


REG_NEG x19 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x19_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x19_data_wire)
);


REG_NEG x20 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x20_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x20_data_wire)
);


REG_NEG x21 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x21_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x21_data_wire)
);


REG_NEG x22 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x22_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x22_data_wire)
);


REG_NEG x23 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x23_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x23_data_wire)
);


REG_NEG x24 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x24_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x24_data_wire)
);


REG_NEG x25 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x25_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x25_data_wire)
);


REG_NEG x26 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x26_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x26_data_wire)
);


REG_NEG x27 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x27_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x27_data_wire)
);


REG_NEG x28 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x28_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x28_data_wire)
);


REG_NEG x29 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x29_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x29_data_wire)
);


REG_NEG x30 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x30_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x30_data_wire)
);


REG_NEG x31 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x31_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x31_data_wire)
);


MUX_F rs1_output_mux (

  .mux_sel_in(rs1_addr_in),


  .x00_data_in(int_reg_x00_data_wire),
  .x01_data_in(int_reg_x01_data_wire),
  .x02_data_in(int_reg_x02_data_wire),
  .x03_data_in(int_reg_x03_data_wire),
  .x04_data_in(int_reg_x04_data_wire),
  .x05_data_in(int_reg_x05_data_wire),
  .x06_data_in(int_reg_x06_data_wire),
  .x07_data_in(int_reg_x07_data_wire),
  .x08_data_in(int_reg_x08_data_wire),
  .x09_data_in(int_reg_x09_data_wire),
  .x10_data_in(int_reg_x10_data_wire),
  .x11_data_in(int_reg_x11_data_wire),
  .x12_data_in(int_reg_x12_data_wire),
  .x13_data_in(int_reg_x13_data_wire),
  .x14_data_in(int_reg_x14_data_wire),
  .x15_data_in(int_reg_x15_data_wire),
  .x16_data_in(int_reg_x16_data_wire),
  .x17_data_in(int_reg_x17_data_wire),
  .x18_data_in(int_reg_x18_data_wire),
  .x19_data_in(int_reg_x19_data_wire),
  .x20_data_in(int_reg_x20_data_wire),
  .x21_data_in(int_reg_x21_data_wire),
  .x22_data_in(int_reg_x22_data_wire),
  .x23_data_in(int_reg_x23_data_wire),
  .x24_data_in(int_reg_x24_data_wire),
  .x25_data_in(int_reg_x25_data_wire),
  .x26_data_in(int_reg_x26_data_wire),
  .x27_data_in(int_reg_x27_data_wire),
  .x28_data_in(int_reg_x28_data_wire),
  .x29_data_in(int_reg_x29_data_wire),
  .x30_data_in(int_reg_x30_data_wire),
  .x31_data_in(int_reg_x31_data_wire),


  .x_data_out(rs1_data_wire)
);



MUX_F rs2_output_mux (

  .mux_sel_in(rs2_addr_in),


  .x00_data_in(int_reg_x00_data_wire),
  .x01_data_in(int_reg_x01_data_wire),
  .x02_data_in(int_reg_x02_data_wire),
  .x03_data_in(int_reg_x03_data_wire),
  .x04_data_in(int_reg_x04_data_wire),
  .x05_data_in(int_reg_x05_data_wire),
  .x06_data_in(int_reg_x06_data_wire),
  .x07_data_in(int_reg_x07_data_wire),
  .x08_data_in(int_reg_x08_data_wire),
  .x09_data_in(int_reg_x09_data_wire),
  .x10_data_in(int_reg_x10_data_wire),
  .x11_data_in(int_reg_x11_data_wire),
  .x12_data_in(int_reg_x12_data_wire),
  .x13_data_in(int_reg_x13_data_wire),
  .x14_data_in(int_reg_x14_data_wire),
  .x15_data_in(int_reg_x15_data_wire),
  .x16_data_in(int_reg_x16_data_wire),
  .x17_data_in(int_reg_x17_data_wire),
  .x18_data_in(int_reg_x18_data_wire),
  .x19_data_in(int_reg_x19_data_wire),
  .x20_data_in(int_reg_x20_data_wire),
  .x21_data_in(int_reg_x21_data_wire),
  .x22_data_in(int_reg_x22_data_wire),
  .x23_data_in(int_reg_x23_data_wire),
  .x24_data_in(int_reg_x24_data_wire),
  .x25_data_in(int_reg_x25_data_wire),
  .x26_data_in(int_reg_x26_data_wire),
  .x27_data_in(int_reg_x27_data_wire),
  .x28_data_in(int_reg_x28_data_wire),
  .x29_data_in(int_reg_x29_data_wire),
  .x30_data_in(int_reg_x30_data_wire),
  .x31_data_in(int_reg_x31_data_wire),


  .x_data_out(rs2_data_wire)
);


assign rs1_data_out = rs1_data_wire;
assign rs2_data_out = rs2_data_wire;

endmodule
module GPR (


    input clock_in,
    input reset_in,

    input write_enable_in,
    input [4:0] rs1_addr_in,
    input [4:0] rs2_addr_in,
    input [4:0] rd_addr_in,


    output [31:0] rs1_data_out,
    output [31:0] rs2_data_out,


    input [31:0] rd_data_in

    );






wire int_reg_x00_set_wire;
wire int_reg_x01_set_wire;
wire int_reg_x02_set_wire;
wire int_reg_x03_set_wire;
wire int_reg_x04_set_wire;
wire int_reg_x05_set_wire;
wire int_reg_x06_set_wire;
wire int_reg_x07_set_wire;
wire int_reg_x08_set_wire;
wire int_reg_x09_set_wire;
wire int_reg_x10_set_wire;
wire int_reg_x11_set_wire;
wire int_reg_x12_set_wire;
wire int_reg_x13_set_wire;
wire int_reg_x14_set_wire;
wire int_reg_x15_set_wire;
wire int_reg_x16_set_wire;
wire int_reg_x17_set_wire;
wire int_reg_x18_set_wire;
wire int_reg_x19_set_wire;
wire int_reg_x20_set_wire;
wire int_reg_x21_set_wire;
wire int_reg_x22_set_wire;
wire int_reg_x23_set_wire;
wire int_reg_x24_set_wire;
wire int_reg_x25_set_wire;
wire int_reg_x26_set_wire;
wire int_reg_x27_set_wire;
wire int_reg_x28_set_wire;
wire int_reg_x29_set_wire;
wire int_reg_x30_set_wire;
wire int_reg_x31_set_wire;


wire [31:0] int_reg_x00_data_wire;
wire [31:0] int_reg_x01_data_wire;
wire [31:0] int_reg_x02_data_wire;
wire [31:0] int_reg_x03_data_wire;
wire [31:0] int_reg_x04_data_wire;
wire [31:0] int_reg_x05_data_wire;
wire [31:0] int_reg_x06_data_wire;
wire [31:0] int_reg_x07_data_wire;
wire [31:0] int_reg_x08_data_wire;
wire [31:0] int_reg_x09_data_wire;
wire [31:0] int_reg_x10_data_wire;
wire [31:0] int_reg_x11_data_wire;
wire [31:0] int_reg_x12_data_wire;
wire [31:0] int_reg_x13_data_wire;
wire [31:0] int_reg_x14_data_wire;
wire [31:0] int_reg_x15_data_wire;
wire [31:0] int_reg_x16_data_wire;
wire [31:0] int_reg_x17_data_wire;
wire [31:0] int_reg_x18_data_wire;
wire [31:0] int_reg_x19_data_wire;
wire [31:0] int_reg_x20_data_wire;
wire [31:0] int_reg_x21_data_wire;
wire [31:0] int_reg_x22_data_wire;
wire [31:0] int_reg_x23_data_wire;
wire [31:0] int_reg_x24_data_wire;
wire [31:0] int_reg_x25_data_wire;
wire [31:0] int_reg_x26_data_wire;
wire [31:0] int_reg_x27_data_wire;
wire [31:0] int_reg_x28_data_wire;
wire [31:0] int_reg_x29_data_wire;
wire [31:0] int_reg_x30_data_wire;
wire [31:0] int_reg_x31_data_wire;


wire [31:0] rs1_data_wire;
wire [31:0] rs2_data_wire;







DECODE_F x_decoder(

  .sel_addr_in(rd_addr_in),


  .sel_x00_out(int_reg_x00_set_wire),
  .sel_x01_out(int_reg_x01_set_wire),
  .sel_x02_out(int_reg_x02_set_wire),
  .sel_x03_out(int_reg_x03_set_wire),
  .sel_x04_out(int_reg_x04_set_wire),
  .sel_x05_out(int_reg_x05_set_wire),
  .sel_x06_out(int_reg_x06_set_wire),
  .sel_x07_out(int_reg_x07_set_wire),
  .sel_x08_out(int_reg_x08_set_wire),
  .sel_x09_out(int_reg_x09_set_wire),
  .sel_x10_out(int_reg_x10_set_wire),
  .sel_x11_out(int_reg_x11_set_wire),
  .sel_x12_out(int_reg_x12_set_wire),
  .sel_x13_out(int_reg_x13_set_wire),
  .sel_x14_out(int_reg_x14_set_wire),
  .sel_x15_out(int_reg_x15_set_wire),
  .sel_x16_out(int_reg_x16_set_wire),
  .sel_x17_out(int_reg_x17_set_wire),
  .sel_x18_out(int_reg_x18_set_wire),
  .sel_x19_out(int_reg_x19_set_wire),
  .sel_x20_out(int_reg_x20_set_wire),
  .sel_x21_out(int_reg_x21_set_wire),
  .sel_x22_out(int_reg_x22_set_wire),
  .sel_x23_out(int_reg_x23_set_wire),
  .sel_x24_out(int_reg_x24_set_wire),
  .sel_x25_out(int_reg_x25_set_wire),
  .sel_x26_out(int_reg_x26_set_wire),
  .sel_x27_out(int_reg_x27_set_wire),
  .sel_x28_out(int_reg_x28_set_wire),
  .sel_x29_out(int_reg_x29_set_wire),
  .sel_x30_out(int_reg_x30_set_wire),
  .sel_x31_out(int_reg_x31_set_wire)
);



REG_NEG x00 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x00_set_wire&write_enable_in),
  .data_in(32'h00000000),
  .data_out(int_reg_x00_data_wire)
);


REG_NEG x01 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x01_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x01_data_wire)
);


REG_NEG x02 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x02_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x02_data_wire)
);


REG_NEG x03 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x03_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x03_data_wire)
);


REG_NEG x04 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x04_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x04_data_wire)
);


REG_NEG x05 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x05_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x05_data_wire)
);


REG_NEG x06 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x06_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x06_data_wire)
);


REG_NEG x08 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x08_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x08_data_wire)
);


REG_NEG x09 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x09_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x09_data_wire)
);


REG_NEG x10 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x10_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x10_data_wire)
);


REG_NEG x11 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x11_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x11_data_wire)
);


REG_NEG x12 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x12_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x12_data_wire)
);


REG_NEG x13 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x13_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x13_data_wire)
);


REG_NEG x14 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x14_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x14_data_wire)
);


REG_NEG x15 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x15_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x15_data_wire)
);


REG_NEG x16 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x16_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x16_data_wire)
);


REG_NEG x17 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x17_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x17_data_wire)
);


REG_NEG x18 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x18_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x18_data_wire)
);


REG_NEG x19 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x19_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x19_data_wire)
);


REG_NEG x20 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x20_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x20_data_wire)
);


REG_NEG x21 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x21_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x21_data_wire)
);


REG_NEG x22 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x22_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x22_data_wire)
);


REG_NEG x23 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x23_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x23_data_wire)
);


REG_NEG x24 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x24_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x24_data_wire)
);


REG_NEG x25 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x25_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x25_data_wire)
);


REG_NEG x26 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x26_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x26_data_wire)
);


REG_NEG x27 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x27_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x27_data_wire)
);


REG_NEG x28 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x28_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x28_data_wire)
);


REG_NEG x29 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x29_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x29_data_wire)
);


REG_NEG x30 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x30_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x30_data_wire)
);


REG_NEG x31 (
  .clock_in(clock_in),
  .reset_in(reset_in),
  .set_in(int_reg_x31_set_wire&write_enable_in),
  .data_in(rd_data_in),
  .data_out(int_reg_x31_data_wire)
);


MUX_F rs1_output_mux (

  .mux_sel_in(rs1_addr_in),


  .x00_data_in(int_reg_x00_data_wire),
  .x01_data_in(int_reg_x01_data_wire),
  .x02_data_in(int_reg_x02_data_wire),
  .x03_data_in(int_reg_x03_data_wire),
  .x04_data_in(int_reg_x04_data_wire),
  .x05_data_in(int_reg_x05_data_wire),
  .x06_data_in(int_reg_x06_data_wire),
  .x07_data_in(int_reg_x07_data_wire),
  .x08_data_in(int_reg_x08_data_wire),
  .x09_data_in(int_reg_x09_data_wire),
  .x10_data_in(int_reg_x10_data_wire),
  .x11_data_in(int_reg_x11_data_wire),
  .x12_data_in(int_reg_x12_data_wire),
  .x13_data_in(int_reg_x13_data_wire),
  .x14_data_in(int_reg_x14_data_wire),
  .x15_data_in(int_reg_x15_data_wire),
  .x16_data_in(int_reg_x16_data_wire),
  .x17_data_in(int_reg_x17_data_wire),
  .x18_data_in(int_reg_x18_data_wire),
  .x19_data_in(int_reg_x19_data_wire),
  .x20_data_in(int_reg_x20_data_wire),
  .x21_data_in(int_reg_x21_data_wire),
  .x22_data_in(int_reg_x22_data_wire),
  .x23_data_in(int_reg_x23_data_wire),
  .x24_data_in(int_reg_x24_data_wire),
  .x25_data_in(int_reg_x25_data_wire),
  .x26_data_in(int_reg_x26_data_wire),
  .x27_data_in(int_reg_x27_data_wire),
  .x28_data_in(int_reg_x28_data_wire),
  .x29_data_in(int_reg_x29_data_wire),
  .x30_data_in(int_reg_x30_data_wire),
  .x31_data_in(int_reg_x31_data_wire),


  .x_data_out(rs1_data_wire)
);



MUX_F rs2_output_mux (

  .mux_sel_in(rs2_addr_in),


  .x00_data_in(int_reg_x00_data_wire),
  .x01_data_in(int_reg_x01_data_wire),
  .x02_data_in(int_reg_x02_data_wire),
  .x03_data_in(int_reg_x03_data_wire),
  .x04_data_in(int_reg_x04_data_wire),
  .x05_data_in(int_reg_x05_data_wire),
  .x06_data_in(int_reg_x06_data_wire),
  .x07_data_in(int_reg_x07_data_wire),
  .x08_data_in(int_reg_x08_data_wire),
  .x09_data_in(int_reg_x09_data_wire),
  .x10_data_in(int_reg_x10_data_wire),
  .x11_data_in(int_reg_x11_data_wire),
  .x12_data_in(int_reg_x12_data_wire),
  .x13_data_in(int_reg_x13_data_wire),
  .x14_data_in(int_reg_x14_data_wire),
  .x15_data_in(int_reg_x15_data_wire),
  .x16_data_in(int_reg_x16_data_wire),
  .x17_data_in(int_reg_x17_data_wire),
  .x18_data_in(int_reg_x18_data_wire),
  .x19_data_in(int_reg_x19_data_wire),
  .x20_data_in(int_reg_x20_data_wire),
  .x21_data_in(int_reg_x21_data_wire),
  .x22_data_in(int_reg_x22_data_wire),
  .x23_data_in(int_reg_x23_data_wire),
  .x24_data_in(int_reg_x24_data_wire),
  .x25_data_in(int_reg_x25_data_wire),
  .x26_data_in(int_reg_x26_data_wire),
  .x27_data_in(int_reg_x27_data_wire),
  .x28_data_in(int_reg_x28_data_wire),
  .x29_data_in(int_reg_x29_data_wire),
  .x30_data_in(int_reg_x30_data_wire),
  .x31_data_in(int_reg_x31_data_wire),


  .x_data_out(rs2_data_wire)
);


assign rs1_data_out = rs1_data_wire;
assign rs2_data_out = rs2_data_wire;

endmodule