data/full_repos/permissive/115837888/source-7400/74154-tb.v
 line:5: before: "tbassert"
1: b'%Error: data/full_repos/permissive/115837888/source-7400/74154-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74154-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74154-tb.v:6: Define or directive not defined: \'`TBASSERT_2_METHOD\'\n`TBASSERT_2_METHOD(tbassert2)\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74154-tb.v:33: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("74154-tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74154-tb.v:34: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74154-tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 5 error(s), 30 warning(s)\n'
module test;

`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)

localparam WIDTH_OUT = 16;
localparam WIDTH_IN = $clog2(WIDTH_OUT);



reg Enable1_bar;
reg Enable2_bar;
reg [WIDTH_IN-1:0] A;


wire [WIDTH_OUT-1:0] Y;


ttl_74154 #(.WIDTH_OUT(WIDTH_OUT), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .Enable1_bar(Enable1_bar),
  .Enable2_bar(Enable2_bar),
  .A(A),
  .Y(Y)
);

initial
begin
  reg [WIDTH_OUT-1:0] Y_expected;
  integer i;

  $dumpfile("74154-tb.vcd");
  $dumpvars;


  Enable1_bar = 1'b0;
  Enable2_bar = 1'b0;
  A = 4'b0000;
#6
  tbassert(Y == 16'b1111111111111110, "Test 1");
#0

  Enable2_bar = 1'b1;
#6
  tbassert(Y == 16'b1111111111111111, "Test 2");
#0

  Enable1_bar = 1'b1;
#6
  tbassert(Y == 16'b1111111111111111, "Test 3");
#0

  Enable2_bar = 1'b0;
#6
  tbassert(Y == 16'b1111111111111111, "Test 4");
#0

  A = 4'b0001;
#6
  tbassert(Y == 16'b1111111111111111, "Test 5");
#0

  Enable1_bar = 1'b0;
#10
  tbassert(Y == 16'b1111111111111101, "Test 6");
#0

  Enable1_bar = 1'b1;
  Enable2_bar = 1'b1;
  A = 4'b0011;
#10
  tbassert(Y == 16'b1111111111111111, "Test 7");
#0
  Enable1_bar = 1'b0;
  Enable2_bar = 1'b0;
#10
  tbassert(Y == 16'b1111111111110111, "Test 7");
#0

  A = 4'b1111;
#10
  tbassert(Y == 16'b0111111111111111, "Test 8");
#0



  for (i = 14; i >= 0; i--)
  begin
    A = i;

    case (i)
      14:
      begin
        Y_expected = 16'b1011111111111111;
      end
      13:
      begin
        Y_expected = 16'b1101111111111111;
      end
      12:
      begin
        Y_expected = 16'b1110111111111111;
      end
      11:
      begin
        Y_expected = 16'b1111011111111111;
      end
      10:
      begin
        Y_expected = 16'b1111101111111111;
      end
      9:
      begin
        Y_expected = 16'b1111110111111111;
      end
      8:
      begin
        Y_expected = 16'b1111111011111111;
      end
      7:
      begin
        Y_expected = 16'b1111111101111111;
      end
      6:
      begin
        Y_expected = 16'b1111111110111111;
      end
      5:
      begin
        Y_expected = 16'b1111111111011111;
      end
      4:
      begin
        Y_expected = 16'b1111111111101111;
      end
      3:
      begin
        Y_expected = 16'b1111111111110111;
      end
      2:
      begin
        Y_expected = 16'b1111111111111011;
      end
      1:
      begin
        Y_expected = 16'b1111111111111101;
      end
      0:
      begin
        Y_expected = 16'b1111111111111110;
      end
    endcase
#10
    tbassert2(Y == Y_expected, "Test", (15 - i), "9");

  end


#0


  Enable1_bar = 1'b1;
  Enable2_bar = 1'b1;
#6
  tbassert(Y == 16'b1111111111111111, "Test 10");
#0
  A = 4'b0101;
#6
  tbassert(Y == 16'b1111111111111111, "Test 10");
#0

  A = 4'b1010;
#6
  tbassert(Y == 16'b1111111111111111, "Test 11");
#0

  Enable1_bar = 1'b0;
  Enable2_bar = 1'b0;
  A = 4'b0101;
#6
  tbassert(Y == 16'b1111111111011111, "Test 12");
#0

  A = 4'b1010;
#6
  tbassert(Y == 16'b1111101111111111, "Test 13");
#10
  $finish;
end

endmodule
module test;


`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)

localparam WIDTH_OUT = 16;
localparam WIDTH_IN = $clog2(WIDTH_OUT);



reg Enable1_bar;
reg Enable2_bar;
reg [WIDTH_IN-1:0] A;


wire [WIDTH_OUT-1:0] Y;


ttl_74154 #(.WIDTH_OUT(WIDTH_OUT), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .Enable1_bar(Enable1_bar),
  .Enable2_bar(Enable2_bar),
  .A(A),
  .Y(Y)
);

initial
begin
  reg [WIDTH_OUT-1:0] Y_expected;
  integer i;

  $dumpfile("74154-tb.vcd");
  $dumpvars;


  Enable1_bar = 1'b0;
  Enable2_bar = 1'b0;
  A = 4'b0000;
#6
  tbassert(Y == 16'b1111111111111110, "Test 1");
#0

  Enable2_bar = 1'b1;
#6
  tbassert(Y == 16'b1111111111111111, "Test 2");
#0

  Enable1_bar = 1'b1;
#6
  tbassert(Y == 16'b1111111111111111, "Test 3");
#0

  Enable2_bar = 1'b0;
#6
  tbassert(Y == 16'b1111111111111111, "Test 4");
#0

  A = 4'b0001;
#6
  tbassert(Y == 16'b1111111111111111, "Test 5");
#0

  Enable1_bar = 1'b0;
#10
  tbassert(Y == 16'b1111111111111101, "Test 6");
#0

  Enable1_bar = 1'b1;
  Enable2_bar = 1'b1;
  A = 4'b0011;
#10
  tbassert(Y == 16'b1111111111111111, "Test 7");
#0
  Enable1_bar = 1'b0;
  Enable2_bar = 1'b0;
#10
  tbassert(Y == 16'b1111111111110111, "Test 7");
#0

  A = 4'b1111;
#10
  tbassert(Y == 16'b0111111111111111, "Test 8");
#0



  for (i = 14; i >= 0; i--)
  begin
    A = i;

    case (i)
      14:
      begin
        Y_expected = 16'b1011111111111111;
      end
      13:
      begin
        Y_expected = 16'b1101111111111111;
      end
      12:
      begin
        Y_expected = 16'b1110111111111111;
      end
      11:
      begin
        Y_expected = 16'b1111011111111111;
      end
      10:
      begin
        Y_expected = 16'b1111101111111111;
      end
      9:
      begin
        Y_expected = 16'b1111110111111111;
      end
      8:
      begin
        Y_expected = 16'b1111111011111111;
      end
      7:
      begin
        Y_expected = 16'b1111111101111111;
      end
      6:
      begin
        Y_expected = 16'b1111111110111111;
      end
      5:
      begin
        Y_expected = 16'b1111111111011111;
      end
      4:
      begin
        Y_expected = 16'b1111111111101111;
      end
      3:
      begin
        Y_expected = 16'b1111111111110111;
      end
      2:
      begin
        Y_expected = 16'b1111111111111011;
      end
      1:
      begin
        Y_expected = 16'b1111111111111101;
      end
      0:
      begin
        Y_expected = 16'b1111111111111110;
      end
    endcase
#10
    tbassert2(Y == Y_expected, "Test", (15 - i), "9");

  end


#0


  Enable1_bar = 1'b1;
  Enable2_bar = 1'b1;
#6
  tbassert(Y == 16'b1111111111111111, "Test 10");
#0
  A = 4'b0101;
#6
  tbassert(Y == 16'b1111111111111111, "Test 10");
#0

  A = 4'b1010;
#6
  tbassert(Y == 16'b1111111111111111, "Test 11");
#0

  Enable1_bar = 1'b0;
  Enable2_bar = 1'b0;
  A = 4'b0101;
#6
  tbassert(Y == 16'b1111111111011111, "Test 12");
#0

  A = 4'b1010;
#6
  tbassert(Y == 16'b1111101111111111, "Test 13");
#10
  $finish;
end

endmodule