data/full_repos/permissive/174783592/FloatAdd/Adder/sum5bit.v
None: at end of input
1: b'%Error: data/full_repos/permissive/174783592/FloatAdd/Adder/sum5bit.v:2: Cannot find include file: Adder/kpgGen.v\n`include "Adder/kpgGen.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174783592/FloatAdd/Adder,data/full_repos/permissive/174783592/Adder/kpgGen.v\n             data/full_repos/permissive/174783592/FloatAdd/Adder,data/full_repos/permissive/174783592/Adder/kpgGen.v.v\n             data/full_repos/permissive/174783592/FloatAdd/Adder,data/full_repos/permissive/174783592/Adder/kpgGen.v.sv\n             Adder/kpgGen.v\n             Adder/kpgGen.v.v\n             Adder/kpgGen.v.sv\n             obj_dir/Adder/kpgGen.v\n             obj_dir/Adder/kpgGen.v.v\n             obj_dir/Adder/kpgGen.v.sv\n%Error: data/full_repos/permissive/174783592/FloatAdd/Adder/sum5bit.v:4: Cannot find include file: Adder/kpgCmp.v\n`include "Adder/kpgCmp.v" \n         ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module sum5bit(a,b,kIn,  sum);
    input [4:0] a;
    input  [4:0] b;
    input  [1:0] kIn;

    wire [11:0] kpgIn;
    wire [11:0] kpgOut;
     wire [9:2] w1;
     wire [7:4] w2;
     

    output reg [5:0] sum;
 
    



	
    assign kpgIn[1:0] = kIn;
    assign kpgOut[1:0]= kIn;

    
    kpgGen g1(a[0],b[0],kpgIn[3:2]);
    kpgGen g2(a[1],b[1],kpgIn[5:4]);
    kpgGen g3(a[2],b[2],kpgIn[7:6]);
    kpgGen g4(a[3],b[3],kpgIn[9:8]);
    kpgGen g5(a[4],b[4],kpgIn[11:10]);

    kpgCmp c1(kpgIn[3:2],kpgIn[1:0],kpgOut[3:2]);
    kpgCmp c2(kpgIn[5:4],kpgIn[3:2],w1[3:2]);
    kpgCmp c3(kpgIn[7:6],kpgIn[5:4],w1[5:4]);
    kpgCmp c4(kpgIn[9:8],kpgIn[7:6],w1[7:6]);
    kpgCmp c5(kpgIn[11:10],kpgIn[9:8],w1[9:8]);
    
    

    
    kpgCmp c6(w1[3:2],kpgIn[1:0],kpgOut[5:4]);
    kpgCmp c7(w1[5:4],kpgOut[3:2],kpgOut[7:6]);
    kpgCmp c8(w1[7:6],w1[3:2],w2[5:4]);
    kpgCmp c9(w1[9:8],w1[5:4],w2[7:6]);
    
    kpgCmp c10(w2[5:4],kpgOut[1:0],kpgOut[9:8]);
    kpgCmp c11(w2[7:6],kpgOut[3:2],kpgOut[11:10]);



    







    always @( *)
    begin
	    


   

			sum[0] <=  a[0]^b[0]^(kpgOut[0]| kpgOut[1]);






   




			sum[1] <=  a[1]^b[1]^(kpgOut[3]| kpgOut[2]);




	   
   




	     
			sum[2] <=  a[2]^b[2]^(kpgOut[5]| kpgOut[4]);





	   
   




	
			
      sum[3] <=  a[3]^b[3]^(kpgOut[7]| kpgOut[6]);
      sum[4] <=  a[4]^b[4]^(kpgOut[9]| kpgOut[8]);
      sum[5] <=  (kpgOut[11]| kpgOut[10]);






    end	  
  


endmodule
module sum5bit(a,b,kIn,  sum);

    input [4:0] a;
    input  [4:0] b;
    input  [1:0] kIn;

    wire [11:0] kpgIn;
    wire [11:0] kpgOut;
     wire [9:2] w1;
     wire [7:4] w2;
     

    output reg [5:0] sum;
 
    



	
    assign kpgIn[1:0] = kIn;
    assign kpgOut[1:0]= kIn;

    
    kpgGen g1(a[0],b[0],kpgIn[3:2]);
    kpgGen g2(a[1],b[1],kpgIn[5:4]);
    kpgGen g3(a[2],b[2],kpgIn[7:6]);
    kpgGen g4(a[3],b[3],kpgIn[9:8]);
    kpgGen g5(a[4],b[4],kpgIn[11:10]);

    kpgCmp c1(kpgIn[3:2],kpgIn[1:0],kpgOut[3:2]);
    kpgCmp c2(kpgIn[5:4],kpgIn[3:2],w1[3:2]);
    kpgCmp c3(kpgIn[7:6],kpgIn[5:4],w1[5:4]);
    kpgCmp c4(kpgIn[9:8],kpgIn[7:6],w1[7:6]);
    kpgCmp c5(kpgIn[11:10],kpgIn[9:8],w1[9:8]);
    
    

    
    kpgCmp c6(w1[3:2],kpgIn[1:0],kpgOut[5:4]);
    kpgCmp c7(w1[5:4],kpgOut[3:2],kpgOut[7:6]);
    kpgCmp c8(w1[7:6],w1[3:2],w2[5:4]);
    kpgCmp c9(w1[9:8],w1[5:4],w2[7:6]);
    
    kpgCmp c10(w2[5:4],kpgOut[1:0],kpgOut[9:8]);
    kpgCmp c11(w2[7:6],kpgOut[3:2],kpgOut[11:10]);



    







    always @( *)
    begin
	    


   

			sum[0] <=  a[0]^b[0]^(kpgOut[0]| kpgOut[1]);






   




			sum[1] <=  a[1]^b[1]^(kpgOut[3]| kpgOut[2]);




	   
   




	     
			sum[2] <=  a[2]^b[2]^(kpgOut[5]| kpgOut[4]);





	   
   




	
			
      sum[3] <=  a[3]^b[3]^(kpgOut[7]| kpgOut[6]);
      sum[4] <=  a[4]^b[4]^(kpgOut[9]| kpgOut[8]);
      sum[5] <=  (kpgOut[11]| kpgOut[10]);






    end	  
  


endmodule