data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit.v
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data/verilator_xmls/ad4fab92-a57c-4e71-9602-c1ffe0c6842d.xml
module bit_barrel_shifter(out, shift_amount, in);

	input [7:0] in;
	input [2:0] shift_amount;
	output [7:0] out;
	
	wire [7:0] shift4, shift2;
	

	assign shift4 = shift_amount[2] ? {in[3:0], in[7:4]} : in;

	assign shift2 = shift_amount[1] ? {shift4[1:0], shift4[7:2]} : shift4;

	assign out = shift_amount[0] ? {shift2[0], shift2[7:1]} : shift2;
endmodule
module bit_barrel_shifter(out, shift_amount, in);


	input [7:0] in;
	input [2:0] shift_amount;
	output [7:0] out;
	
	wire [7:0] shift4, shift2;
	

	assign shift4 = shift_amount[2] ? {in[3:0], in[7:4]} : in;

	assign shift2 = shift_amount[1] ? {shift4[1:0], shift4[7:2]} : shift4;

	assign out = shift_amount[0] ? {shift2[0], shift2[7:1]} : shift2;
endmodule