data/full_repos/permissive/169496369/control_logic.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169496369/control_logic.v:210: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                        : ... In instance control_logic\n            aluop = 2\'b00;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module control_logic(opcode, instr_rem, funct, fpu_alu_out_en, regdst, jump, branch, memread, memtoreg, aluop, memwrite, alusrc, regwrite, fpu_regwrite, fpu_re_en, fpu_wr_en, fpu_op, fpu_regdst, fpu_alu_en, stop);
    input [5:0] opcode;
    input [5:0] funct;
    input [19:0] instr_rem;
    input fpu_alu_out_en;
    
    output logic regdst, memread, jump, branch, memtoreg, memwrite, alusrc, regwrite, fpu_regwrite, fpu_re_en, fpu_wr_en, fpu_op, fpu_regdst, fpu_alu_en, stop;
    output logic [2:0] aluop;
        
    always_comb
    begin
        regdst = 0;
        jump = 0;
        branch = 0;
        memread = 0;
        memtoreg = 0;
        aluop = 3'b000;
        memwrite = 0;
        alusrc = 0;
        regwrite = 0;
        stop = 0;
        fpu_regwrite = 0;
        fpu_re_en = 0;
        fpu_wr_en = 0;
        fpu_op = 0;
        fpu_regdst = 0;
        fpu_alu_en = 0;

        
        if(opcode == 6'd0)
        begin
            if(funct == 6'b100000)
            begin
                regdst = 1;




                aluop = 3'b000;


                regwrite = 1;
            end
            else if(funct == 6'b100100)
            begin
                regdst = 1;




                aluop = 3'b001;


                regwrite = 1;
            end
            else if(funct == 6'b100101)
            begin
                regdst = 1;




                aluop = 3'b010;


                regwrite = 1;
            end
            else if(funct == 6'b100010)
            begin
                regdst = 1;




                aluop = 3'b011;


                regwrite = 1;
            end
            else if({instr_rem, funct} == 26'd0)
            begin
                stop = 1;
            end
            else
            begin
                regdst = 1;




                aluop = 3'b100;


                regwrite = 1;
            end

        end
        else if(opcode == 6'b000010)
        begin
            jump = 1;
        end
        else if(opcode == 6'b000100)
        begin
            branch = 1;
            aluop = 3'b011;
            alusrc = 0;
        end
        else if(opcode == 6'b001000)
        begin
            aluop = 3'b000;
            alusrc = 1;
            regwrite = 1;
        end
        else if(opcode == 6'b100011)
        begin
            memtoreg = 1;
            aluop = 3'b000;
            alusrc = 1;
            regwrite = 1;
            memread = 1;
        end
















        else if(opcode == 6'b101011)
        begin
            memwrite = 1;
            aluop = 3'b000;
            alusrc = 1;
        end
        else if(opcode == 6'b01_0001)
        begin


            fpu_op = 0;
            fpu_regdst = 1;
            fpu_regwrite = 1;
            fpu_wr_en = 1;
            fpu_alu_en = 1;

            if(fpu_alu_out_en)
            begin
                fpu_alu_en = 0;
                stop = 0;
            end
            else
            begin

                stop = 1;
            end
        end
        else if(opcode == 6'b110001)
        begin
            memtoreg = 1;
            aluop = 3'b000;
            alusrc = 1;
            fpu_regwrite = 1;
            memread = 1;

        end
        else if(opcode == 6'b111001)
        begin
            memwrite = 1;
            aluop = 3'b000;
            alusrc = 1;
            fpu_re_en = 1;
        end
        else
        begin
            regdst = 0;
            jump = 0;
            branch = 0;
            memread = 0;
            memtoreg = 0;
            aluop = 2'b00;
            memwrite = 0;
            alusrc = 0;
            regwrite = 0;            
        end
    end
endmodule
module control_logic(opcode, instr_rem, funct, fpu_alu_out_en, regdst, jump, branch, memread, memtoreg, aluop, memwrite, alusrc, regwrite, fpu_regwrite, fpu_re_en, fpu_wr_en, fpu_op, fpu_regdst, fpu_alu_en, stop);

    input [5:0] opcode;
    input [5:0] funct;
    input [19:0] instr_rem;
    input fpu_alu_out_en;
    
    output logic regdst, memread, jump, branch, memtoreg, memwrite, alusrc, regwrite, fpu_regwrite, fpu_re_en, fpu_wr_en, fpu_op, fpu_regdst, fpu_alu_en, stop;
    output logic [2:0] aluop;
        
    always_comb
    begin
        regdst = 0;
        jump = 0;
        branch = 0;
        memread = 0;
        memtoreg = 0;
        aluop = 3'b000;
        memwrite = 0;
        alusrc = 0;
        regwrite = 0;
        stop = 0;
        fpu_regwrite = 0;
        fpu_re_en = 0;
        fpu_wr_en = 0;
        fpu_op = 0;
        fpu_regdst = 0;
        fpu_alu_en = 0;

        
        if(opcode == 6'd0)
        begin
            if(funct == 6'b100000)
            begin
                regdst = 1;




                aluop = 3'b000;


                regwrite = 1;
            end
            else if(funct == 6'b100100)
            begin
                regdst = 1;




                aluop = 3'b001;


                regwrite = 1;
            end
            else if(funct == 6'b100101)
            begin
                regdst = 1;




                aluop = 3'b010;


                regwrite = 1;
            end
            else if(funct == 6'b100010)
            begin
                regdst = 1;




                aluop = 3'b011;


                regwrite = 1;
            end
            else if({instr_rem, funct} == 26'd0)
            begin
                stop = 1;
            end
            else
            begin
                regdst = 1;




                aluop = 3'b100;


                regwrite = 1;
            end

        end
        else if(opcode == 6'b000010)
        begin
            jump = 1;
        end
        else if(opcode == 6'b000100)
        begin
            branch = 1;
            aluop = 3'b011;
            alusrc = 0;
        end
        else if(opcode == 6'b001000)
        begin
            aluop = 3'b000;
            alusrc = 1;
            regwrite = 1;
        end
        else if(opcode == 6'b100011)
        begin
            memtoreg = 1;
            aluop = 3'b000;
            alusrc = 1;
            regwrite = 1;
            memread = 1;
        end
















        else if(opcode == 6'b101011)
        begin
            memwrite = 1;
            aluop = 3'b000;
            alusrc = 1;
        end
        else if(opcode == 6'b01_0001)
        begin


            fpu_op = 0;
            fpu_regdst = 1;
            fpu_regwrite = 1;
            fpu_wr_en = 1;
            fpu_alu_en = 1;

            if(fpu_alu_out_en)
            begin
                fpu_alu_en = 0;
                stop = 0;
            end
            else
            begin

                stop = 1;
            end
        end
        else if(opcode == 6'b110001)
        begin
            memtoreg = 1;
            aluop = 3'b000;
            alusrc = 1;
            fpu_regwrite = 1;
            memread = 1;

        end
        else if(opcode == 6'b111001)
        begin
            memwrite = 1;
            aluop = 3'b000;
            alusrc = 1;
            fpu_re_en = 1;
        end
        else
        begin
            regdst = 0;
            jump = 0;
            branch = 0;
            memread = 0;
            memtoreg = 0;
            aluop = 2'b00;
            memwrite = 0;
            alusrc = 0;
            regwrite = 0;            
        end
    end
endmodule