data/full_repos/permissive/192449736/WS2812_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:20: Unsupported: Ignoring delay on this delayed statement.\n #20 reset=0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n #20 iDATA_CLOCK=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n #20 iDATA_CLOCK=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20 iDATA_CLOCK=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n #20 iDATA_CLOCK=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:35: Unsupported: Ignoring delay on this delayed statement.\n #2 dR=231;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n #4 dG=195;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n #8 LED_IDX=2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:38: Unsupported: Ignoring delay on this delayed statement.\n #7 dB=136;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n #20 iDATA_CLOCK=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:40: Unsupported: Ignoring delay on this delayed statement.\n #20 iDATA_CLOCK=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/192449736/WS2812_TB.v:45: Unsupported: Ignoring delay on this delayed statement.\n #5 iSIGNAL_CLOCK=~iSIGNAL_CLOCK;\n ^\n%Error: data/full_repos/permissive/192449736/WS2812_TB.v:48: Cannot find file containing module: \'WS2812\'\n WS2812 ledCtrl(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/192449736,data/full_repos/permissive/192449736/WS2812\n             data/full_repos/permissive/192449736,data/full_repos/permissive/192449736/WS2812.v\n             data/full_repos/permissive/192449736,data/full_repos/permissive/192449736/WS2812.sv\n             WS2812\n             WS2812.v\n             WS2812.sv\n             obj_dir/WS2812\n             obj_dir/WS2812.v\n             obj_dir/WS2812.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module WS2812_TB();
	
	
	reg 		iSIGNAL_CLOCK;
	reg 		iDATA_CLOCK;
	reg [7:0]	dR, dG, dB;
	reg [8:0] LED_IDX;
	wire oCTRL_OUT;
	reg reset;
	
	initial begin
	iSIGNAL_CLOCK=0;
	iDATA_CLOCK=0;
	reset=0;
	reset=1;
	#20 reset=0;
	
	dR=255;
	dG=170;
	dB=240;
	LED_IDX=0;
	#20 iDATA_CLOCK=1;
	#20 iDATA_CLOCK=0;
	LED_IDX=1;
	dR=15;
	dG=85;
	dB=0;
	#20 iDATA_CLOCK=1;
	#20 iDATA_CLOCK=0;
	
	#2 dR=231;
	#4 dG=195;
	#8 LED_IDX=2;
	#7 dB=136;
	#20 iDATA_CLOCK=1;
	#20 iDATA_CLOCK=0;
	end
	
	
	always begin
	#5 iSIGNAL_CLOCK=~iSIGNAL_CLOCK;
	end
	
	WS2812 ledCtrl(
	.iSIGNAL_CLOCK(iSIGNAL_CLOCK),
	.iDATA_CLOCK(iDATA_CLOCK),
	.dR(dR),
	.dG(dG),
	.dB(dB),
	.LED_IDX(LED_IDX),
	.ext_reset(reset),
	.oCTRL_OUT(oCTRL_OUT));
	
endmodule
module WS2812_TB();

	
	
	reg 		iSIGNAL_CLOCK;
	reg 		iDATA_CLOCK;
	reg [7:0]	dR, dG, dB;
	reg [8:0] LED_IDX;
	wire oCTRL_OUT;
	reg reset;
	
	initial begin
	iSIGNAL_CLOCK=0;
	iDATA_CLOCK=0;
	reset=0;
	reset=1;
	#20 reset=0;
	
	dR=255;
	dG=170;
	dB=240;
	LED_IDX=0;
	#20 iDATA_CLOCK=1;
	#20 iDATA_CLOCK=0;
	LED_IDX=1;
	dR=15;
	dG=85;
	dB=0;
	#20 iDATA_CLOCK=1;
	#20 iDATA_CLOCK=0;
	
	#2 dR=231;
	#4 dG=195;
	#8 LED_IDX=2;
	#7 dB=136;
	#20 iDATA_CLOCK=1;
	#20 iDATA_CLOCK=0;
	end
	
	
	always begin
	#5 iSIGNAL_CLOCK=~iSIGNAL_CLOCK;
	end
	
	WS2812 ledCtrl(
	.iSIGNAL_CLOCK(iSIGNAL_CLOCK),
	.iDATA_CLOCK(iDATA_CLOCK),
	.dR(dR),
	.dG(dG),
	.dB(dB),
	.LED_IDX(LED_IDX),
	.ext_reset(reset),
	.oCTRL_OUT(oCTRL_OUT));
	
endmodule