data/full_repos/permissive/143278/ivltests/select7.v
 line:48 column:2: Illegal character '\x00'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/select7.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (mem[0] !== 8\'hc5) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/select7.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (mem[1] !== 8\'h30) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/select7.v:19: Operator NEQCASE expects 5 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                       : ... In instance main\n      if (mem[0][4+:4] !== 5\'ha) begin\n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/select7.v:24: Operator NEQCASE expects 5 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                       : ... In instance main\n      if (mem[1][4+:4] !== 5\'hf) begin\n                       ^~~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [7:0] mem [0:1];

   initial begin
      mem[0] = 8'ha5;
      mem[1] = 8'hf0;

      if (mem[0] !== 8'ha5) begin
	 $display("FAILED");
	 $finish;
      end

      if (mem[1] !== 8'hf0) begin
	 $display("FAILED");
	 $finish;
      end

      if (mem[0][4+:4] !== 5'ha) begin
	 $display("FAILED");
	 $finish;
      end

      if (mem[1][4+:4] !== 5'hf) begin
	 $display("FAILED");
	 $finish;
      end

      mem[0][4 +: 4] = 4'hc;

      #1 if (mem[0] !== 8'hc5) begin
	 $display("FAILED");
	 $finish;
      end

      mem[1][4 +: 4] = 4'h3;

      #1 if (mem[1] !== 8'h30) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   reg [7:0] mem [0:1];

   initial begin
      mem[0] = 8'ha5;
      mem[1] = 8'hf0;

      if (mem[0] !== 8'ha5) begin
	 $display("FAILED");
	 $finish;
      end

      if (mem[1] !== 8'hf0) begin
	 $display("FAILED");
	 $finish;
      end

      if (mem[0][4+:4] !== 5'ha) begin
	 $display("FAILED");
	 $finish;
      end

      if (mem[1][4+:4] !== 5'hf) begin
	 $display("FAILED");
	 $finish;
      end

      mem[0][4 +: 4] = 4'hc;

      #1 if (mem[0] !== 8'hc5) begin
	 $display("FAILED");
	 $finish;
      end

      mem[1][4 +: 4] = 4'h3;

      #1 if (mem[1] !== 8'h30) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule