data/full_repos/permissive/127311496/src/platform/N4DDR/Seg7Device.v
data/verilator_xmls/43ee4b35-2e87-47cd-80e7-a31968a483a9.xml
module Seg7Device #(
	parameter DIGITS = 8,
	parameter SEG_POLARITY = 1'b0,
	parameter AN_POLARITY = 1'b0
) (
	input clk, input blink, input [DIGITS*4-1:0] data, input [DIGITS-1:0] point,
	input [DIGITS-1:0] en, output reg [7:0] segment, output reg [DIGITS-1:0] anode
);
	wire [6:0] pattern;
	
	reg [DIGITS-1:0] anode_reg = 1;
	reg [DIGITS*4-1:0] dataShift;
	reg [DIGITS-1:0] pointShift;
	
	always @ (posedge clk)
	begin
		anode_reg <= {anode_reg[DIGITS-2:0], anode_reg[DIGITS-1]};
		dataShift <= anode_reg[DIGITS-1]? data: {4'h0, dataShift[DIGITS*4-1:4]};
		pointShift <= anode_reg[DIGITS-1]? point: {1'b0, pointShift[DIGITS-1:1]};
		segment[7] <= pointShift[0] ^~ SEG_POLARITY;
		segment[6:0] <= pattern;
		anode <= (anode_reg & (en | {DIGITS{blink}})) ^~ {DIGITS{AN_POLARITY}};
	end
	
	SegmentDecoder #(.POLARITY(SEG_POLARITY)) decoder(.hex(dataShift[3:0]), .segment(pattern));
	
endmodule
module Seg7Device #(
	parameter DIGITS = 8,
	parameter SEG_POLARITY = 1'b0,
	parameter AN_POLARITY = 1'b0
) (
	input clk, input blink, input [DIGITS*4-1:0] data, input [DIGITS-1:0] point,
	input [DIGITS-1:0] en, output reg [7:0] segment, output reg [DIGITS-1:0] anode
);

	wire [6:0] pattern;
	
	reg [DIGITS-1:0] anode_reg = 1;
	reg [DIGITS*4-1:0] dataShift;
	reg [DIGITS-1:0] pointShift;
	
	always @ (posedge clk)
	begin
		anode_reg <= {anode_reg[DIGITS-2:0], anode_reg[DIGITS-1]};
		dataShift <= anode_reg[DIGITS-1]? data: {4'h0, dataShift[DIGITS*4-1:4]};
		pointShift <= anode_reg[DIGITS-1]? point: {1'b0, pointShift[DIGITS-1:1]};
		segment[7] <= pointShift[0] ^~ SEG_POLARITY;
		segment[6:0] <= pattern;
		anode <= (anode_reg & (en | {DIGITS{blink}})) ^~ {DIGITS{AN_POLARITY}};
	end
	
	SegmentDecoder #(.POLARITY(SEG_POLARITY)) decoder(.hex(dataShift[3:0]), .segment(pattern));
	
endmodule