data/full_repos/permissive/150152921/apps/sha1/step2/rtl/sha1_core.v
1: b"%Error: data/full_repos/permissive/150152921/apps/sha1/step2/rtl/sha1_core.v:140: Cannot find file containing module: 'sha1_w_mem'\n  sha1_w_mem w_mem_inst(\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150152921/apps/sha1/step2/rtl,data/full_repos/permissive/150152921/sha1_w_mem\n             data/full_repos/permissive/150152921/apps/sha1/step2/rtl,data/full_repos/permissive/150152921/sha1_w_mem.v\n             data/full_repos/permissive/150152921/apps/sha1/step2/rtl,data/full_repos/permissive/150152921/sha1_w_mem.sv\n             sha1_w_mem\n             sha1_w_mem.v\n             sha1_w_mem.sv\n             obj_dir/sha1_w_mem\n             obj_dir/sha1_w_mem.v\n             obj_dir/sha1_w_mem.sv\n%Error: data/full_repos/permissive/150152921/apps/sha1/step2/rtl/sha1_core.v:274: Cannot find file containing module: 'regchain'\n  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_a (.CLK(clk), .IN(a_reg), .OUT(a_reg_hp)); \n  ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step2/rtl/sha1_core.v:275: Cannot find file containing module: 'regchain'\n  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_b (.CLK(clk), .IN(b_reg), .OUT(b_reg_hp)); \n  ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step2/rtl/sha1_core.v:276: Cannot find file containing module: 'regchain'\n  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_c (.CLK(clk), .IN(c_reg), .OUT(c_reg_hp)); \n  ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step2/rtl/sha1_core.v:277: Cannot find file containing module: 'regchain'\n  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_d (.CLK(clk), .IN(d_reg), .OUT(d_reg_hp)); \n  ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step2/rtl/sha1_core.v:278: Cannot find file containing module: 'regchain'\n  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_e (.CLK(clk), .IN(e_reg), .OUT(e_reg_hp)); \n  ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step2/rtl/sha1_core.v:279: Cannot find file containing module: 'regchain'\n  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_w (.CLK(clk), .IN(w), .OUT(w_hp)); \n  ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/sha1/step2/rtl/sha1_core.v:280: Cannot find file containing module: 'regchain'\n  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(7)) u_regchain_round_ctr (.CLK(clk), .IN(round_ctr_reg), .OUT(round_ctr_reg_hp)); \n  ^~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module sha1_core(
                 input wire            clk,
                 input wire            reset_n,

                 input wire            init,
                 input wire            next,

                 input wire [511 : 0]  block,

                 output wire           ready,

                 output wire [159 : 0] digest,
                 output wire           digest_valid
                );





  parameter H0_0 = 32'h67452301;
  parameter H0_1 = 32'hefcdab89;
  parameter H0_2 = 32'h98badcfe;
  parameter H0_3 = 32'h10325476;
  parameter H0_4 = 32'hc3d2e1f0;

  parameter SHA1_ROUNDS = 79;

  parameter CTRL_IDLE   = 0;
  parameter CTRL_ROUNDS = 1;
  parameter CTRL_DONE   = 2;

  parameter NUM_DELAY = 5;





  reg [31 : 0] a_reg;
  reg [31 : 0] a_new;
  reg [31 : 0] b_reg;
  reg [31 : 0] b_new;
  reg [31 : 0] c_reg;
  reg [31 : 0] c_new;
  reg [31 : 0] d_reg;
  reg [31 : 0] d_new;
  reg [31 : 0] e_reg;
  reg [31 : 0] e_new;
  reg          a_e_we;

  wire [31:0] a_reg_hp;
  wire [31:0] b_reg_hp;
  wire [31:0] c_reg_hp;
  wire [31:0] d_reg_hp;
  wire [31:0] e_reg_hp;
  wire [31:0] w_hp;

  reg [31 : 0] H0_reg;
  reg [31 : 0] H0_new;
  reg [31 : 0] H1_reg;
  reg [31 : 0] H1_new;
  reg [31 : 0] H2_reg;
  reg [31 : 0] H2_new;
  reg [31 : 0] H3_reg;
  reg [31 : 0] H3_new;
  reg [31 : 0] H4_reg;
  reg [31 : 0] H4_new;
  reg          H_we;

  reg [6 : 0] round_ctr_reg;
  reg [6 : 0] round_ctr_new;
  wire [6 : 0] round_ctr_reg_hp;
  reg         round_ctr_we;
  reg         round_ctr_inc;
  reg         round_ctr_rst;

  reg digest_valid_reg;
  reg digest_valid_new;
  reg digest_valid_we;

  reg [1 : 0] sha1_ctrl_reg;
  reg [1 : 0] sha1_ctrl_new;
  reg         sha1_ctrl_we;





  reg           digest_init;
  reg           digest_update;
  reg           state_init;
  reg           state_update;
  reg           first_block;
  reg           ready_flag;
  reg           w_init;
  reg           w_next;
  wire [31 : 0] w;





  sha1_w_mem w_mem_inst(
                        .clk(clk),
                        .reset_n(reset_n),

                        .block(block),

                        .init(w_init),
                        .next(w_next),

                        .w(w)
                       );





  assign ready        = ready_flag;
  assign digest       = {H0_reg, H1_reg, H2_reg, H3_reg, H4_reg};
  assign digest_valid = digest_valid_reg;










  always@(posedge clk) begin
    if(a_e_we) begin
      a_reg <= a_new;
      b_reg <= b_new;
      c_reg <= c_new;
      d_reg <= d_new;
      e_reg <= e_new;
    end 
    if (H_we)
    begin
      H0_reg <= H0_new;
      H1_reg <= H1_new;
      H2_reg <= H2_new;
      H3_reg <= H3_new;
      H4_reg <= H4_new;
    end
  end 
  
  always @ (posedge clk)
    begin : reg_update
      if (!reset_n)
        begin










          digest_valid_reg <= 0;
          round_ctr_reg    <= 7'b0;
          sha1_ctrl_reg    <= CTRL_IDLE;
        end
      else
        begin


          if (round_ctr_we)
            round_ctr_reg <= round_ctr_new;

          if (digest_valid_we)
            digest_valid_reg <= digest_valid_new;

          if (sha1_ctrl_we)
            sha1_ctrl_reg <= sha1_ctrl_new;
        end
    end







  always @*
    begin : digest_logic
      H0_new = 32'h0;
      H1_new = 32'h0;
      H2_new = 32'h0;
      H3_new = 32'h0;
      H4_new = 32'h0;
      H_we = 0;

      if (digest_init)
        begin
          H0_new = H0_0;
          H1_new = H0_1;
          H2_new = H0_2;
          H3_new = H0_3;
          H4_new = H0_4;
          H_we = 1;
        end

      if (digest_update)
        begin
          H0_new = H0_reg + a_reg;
          H1_new = H1_reg + b_reg;
          H2_new = H2_reg + c_reg;
          H3_new = H3_reg + d_reg;
          H4_new = H4_reg + e_reg;
          H_we = 1;
        end
    end

  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_a (.CLK(clk), .IN(a_reg), .OUT(a_reg_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_b (.CLK(clk), .IN(b_reg), .OUT(b_reg_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_c (.CLK(clk), .IN(c_reg), .OUT(c_reg_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_d (.CLK(clk), .IN(d_reg), .OUT(d_reg_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_e (.CLK(clk), .IN(e_reg), .OUT(e_reg_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_w (.CLK(clk), .IN(w), .OUT(w_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(7)) u_regchain_round_ctr (.CLK(clk), .IN(round_ctr_reg), .OUT(round_ctr_reg_hp)); 







  always @*
    begin : state_logic
      reg [31 : 0] a5;
      reg [31 : 0] f;
      reg [31 : 0] k;
      reg [31 : 0] t;
      reg [31 : 0] t_tmp;

      a5     = 32'h0;
      f      = 32'h0;
      k      = 32'h0;
      t      = 32'h0;
      t_tmp  = 32'h0;
      a_new  = 32'h0;
      b_new  = 32'h0;
      c_new  = 32'h0;
      d_new  = 32'h0;
      e_new  = 32'h0;
      a_e_we = 0;

      if (state_init)
        begin
          if (first_block)
            begin
              a_new  = H0_0;
              b_new  = H0_1;
              c_new  = H0_2;
              d_new  = H0_3;
              e_new  = H0_4;
              a_e_we = 1;
            end
          else
            begin
              a_new  = H0_reg;
              b_new  = H1_reg;
              c_new  = H2_reg;
              d_new  = H3_reg;
              e_new  = H4_reg;
              a_e_we = 1;
            end
        end

      if (state_update)
        begin
          if (round_ctr_reg <= 19)
            begin
              k = 32'h5a827999;
              f =  ((b_reg_hp & c_reg_hp) ^ (~b_reg_hp & d_reg_hp));
            end
          else if ((round_ctr_reg >= 20) && (round_ctr_reg <= 39))
            begin
              k = 32'h6ed9eba1;
              f = b_reg_hp ^ c_reg_hp ^ d_reg_hp;
            end
          else if ((round_ctr_reg >= 40) && (round_ctr_reg <= 59))
            begin
              k = 32'h8f1bbcdc;
              f = ((b_reg_hp | c_reg_hp) ^ (b_reg_hp | d_reg_hp) ^ (c_reg_hp | d_reg_hp));
            end
          else if (round_ctr_reg >= 60)
            begin
              k = 32'hca62c1d6;
              f = b_reg_hp ^ c_reg_hp ^ d_reg_hp;
            end

          a5 = {a_reg_hp[26 : 0], a_reg_hp[31 : 27]};
          t_tmp = (e_reg_hp + k + f + w_hp);
          t = t_tmp + a5;

          a_new  = t;
          b_new  = a_reg_hp;
          c_new  = {b_reg_hp[1 : 0], b_reg_hp[31 : 2]};
          d_new  = c_reg_hp;
          e_new  = d_reg_hp;
          if(round_ctr_inc) 
            a_e_we = 1;
        end
    end
    

    reg [NUM_DELAY:0] stage_cnt_onehot_0q;
    reg [NUM_DELAY:0] next_stage_cnt; 
   
    always@(posedge clk) begin
      if(!reset_n) 
        stage_cnt_onehot_0q <= 'd1;
      else 
        stage_cnt_onehot_0q <= next_stage_cnt;
    end 








  always @*
    begin : round_ctr
      round_ctr_new = 0;
      round_ctr_we  = 0;

      if (round_ctr_rst)
        begin
          round_ctr_new = 0;
          round_ctr_we  = 1;
        end

      if (round_ctr_inc)
        begin

          round_ctr_new = round_ctr_reg_hp + 1'b1;
          round_ctr_we  = 1;
        end
    end






  always @*
    begin : sha1_ctrl_fsm
      digest_init      = 0;
      digest_update    = 0;
      state_init       = 0;
      state_update     = 0;
      first_block      = 0;
      ready_flag       = 0;
      w_init           = 0;
      w_next           = 0;
      round_ctr_inc    = 0;
      round_ctr_rst    = 0;
      digest_valid_new = 0;
      digest_valid_we  = 0;
      sha1_ctrl_new    = CTRL_IDLE;
      sha1_ctrl_we     = 0;
      next_stage_cnt   = 'd1; 

      case (sha1_ctrl_reg)
        CTRL_IDLE:
          begin
            ready_flag = 1;

            if (init)
              begin
                digest_init      = 1;
                w_init           = 1;
                state_init       = 1;
                first_block      = 1;
                round_ctr_rst    = 1;
                digest_valid_new = 0;
                digest_valid_we  = 1;
                sha1_ctrl_new    = CTRL_ROUNDS;
                sha1_ctrl_we     = 1;
                next_stage_cnt   = 'd1; 
              end

            if (next)
              begin
                w_init           = 1;
                state_init       = 1;
                round_ctr_rst    = 1;
                digest_valid_new = 0;
                digest_valid_we  = 1;
                sha1_ctrl_new    = CTRL_ROUNDS;
                sha1_ctrl_we     = 1;
                next_stage_cnt   = 'd1; 
              end
          end


        CTRL_ROUNDS:
          begin
            state_update  = 1;


          if(stage_cnt_onehot_0q[NUM_DELAY]) begin
            round_ctr_inc = 1;
            w_next        = 1;
            next_stage_cnt = 'd1;
          end 
          else 
            next_stage_cnt = stage_cnt_onehot_0q << 1; 

            if (round_ctr_reg == SHA1_ROUNDS)
              begin
                if(stage_cnt_onehot_0q[NUM_DELAY]) begin
                  sha1_ctrl_new = CTRL_DONE;
                  sha1_ctrl_we  = 1;
                end 
              end
          end


        CTRL_DONE:
          begin
            digest_update    = 1;
            digest_valid_new = 1;
            digest_valid_we  = 1;
            sha1_ctrl_new    = CTRL_IDLE;
            sha1_ctrl_we     = 1;
            next_stage_cnt   = 'd0; 
          end
      endcase
    end

endmodule
module sha1_core(
                 input wire            clk,
                 input wire            reset_n,

                 input wire            init,
                 input wire            next,

                 input wire [511 : 0]  block,

                 output wire           ready,

                 output wire [159 : 0] digest,
                 output wire           digest_valid
                );






  parameter H0_0 = 32'h67452301;
  parameter H0_1 = 32'hefcdab89;
  parameter H0_2 = 32'h98badcfe;
  parameter H0_3 = 32'h10325476;
  parameter H0_4 = 32'hc3d2e1f0;

  parameter SHA1_ROUNDS = 79;

  parameter CTRL_IDLE   = 0;
  parameter CTRL_ROUNDS = 1;
  parameter CTRL_DONE   = 2;

  parameter NUM_DELAY = 5;





  reg [31 : 0] a_reg;
  reg [31 : 0] a_new;
  reg [31 : 0] b_reg;
  reg [31 : 0] b_new;
  reg [31 : 0] c_reg;
  reg [31 : 0] c_new;
  reg [31 : 0] d_reg;
  reg [31 : 0] d_new;
  reg [31 : 0] e_reg;
  reg [31 : 0] e_new;
  reg          a_e_we;

  wire [31:0] a_reg_hp;
  wire [31:0] b_reg_hp;
  wire [31:0] c_reg_hp;
  wire [31:0] d_reg_hp;
  wire [31:0] e_reg_hp;
  wire [31:0] w_hp;

  reg [31 : 0] H0_reg;
  reg [31 : 0] H0_new;
  reg [31 : 0] H1_reg;
  reg [31 : 0] H1_new;
  reg [31 : 0] H2_reg;
  reg [31 : 0] H2_new;
  reg [31 : 0] H3_reg;
  reg [31 : 0] H3_new;
  reg [31 : 0] H4_reg;
  reg [31 : 0] H4_new;
  reg          H_we;

  reg [6 : 0] round_ctr_reg;
  reg [6 : 0] round_ctr_new;
  wire [6 : 0] round_ctr_reg_hp;
  reg         round_ctr_we;
  reg         round_ctr_inc;
  reg         round_ctr_rst;

  reg digest_valid_reg;
  reg digest_valid_new;
  reg digest_valid_we;

  reg [1 : 0] sha1_ctrl_reg;
  reg [1 : 0] sha1_ctrl_new;
  reg         sha1_ctrl_we;





  reg           digest_init;
  reg           digest_update;
  reg           state_init;
  reg           state_update;
  reg           first_block;
  reg           ready_flag;
  reg           w_init;
  reg           w_next;
  wire [31 : 0] w;





  sha1_w_mem w_mem_inst(
                        .clk(clk),
                        .reset_n(reset_n),

                        .block(block),

                        .init(w_init),
                        .next(w_next),

                        .w(w)
                       );





  assign ready        = ready_flag;
  assign digest       = {H0_reg, H1_reg, H2_reg, H3_reg, H4_reg};
  assign digest_valid = digest_valid_reg;










  always@(posedge clk) begin
    if(a_e_we) begin
      a_reg <= a_new;
      b_reg <= b_new;
      c_reg <= c_new;
      d_reg <= d_new;
      e_reg <= e_new;
    end 
    if (H_we)
    begin
      H0_reg <= H0_new;
      H1_reg <= H1_new;
      H2_reg <= H2_new;
      H3_reg <= H3_new;
      H4_reg <= H4_new;
    end
  end 
  
  always @ (posedge clk)
    begin : reg_update
      if (!reset_n)
        begin










          digest_valid_reg <= 0;
          round_ctr_reg    <= 7'b0;
          sha1_ctrl_reg    <= CTRL_IDLE;
        end
      else
        begin


          if (round_ctr_we)
            round_ctr_reg <= round_ctr_new;

          if (digest_valid_we)
            digest_valid_reg <= digest_valid_new;

          if (sha1_ctrl_we)
            sha1_ctrl_reg <= sha1_ctrl_new;
        end
    end







  always @*
    begin : digest_logic
      H0_new = 32'h0;
      H1_new = 32'h0;
      H2_new = 32'h0;
      H3_new = 32'h0;
      H4_new = 32'h0;
      H_we = 0;

      if (digest_init)
        begin
          H0_new = H0_0;
          H1_new = H0_1;
          H2_new = H0_2;
          H3_new = H0_3;
          H4_new = H0_4;
          H_we = 1;
        end

      if (digest_update)
        begin
          H0_new = H0_reg + a_reg;
          H1_new = H1_reg + b_reg;
          H2_new = H2_reg + c_reg;
          H3_new = H3_reg + d_reg;
          H4_new = H4_reg + e_reg;
          H_we = 1;
        end
    end

  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_a (.CLK(clk), .IN(a_reg), .OUT(a_reg_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_b (.CLK(clk), .IN(b_reg), .OUT(b_reg_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_c (.CLK(clk), .IN(c_reg), .OUT(c_reg_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_d (.CLK(clk), .IN(d_reg), .OUT(d_reg_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_e (.CLK(clk), .IN(e_reg), .OUT(e_reg_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(32)) u_regchain_w (.CLK(clk), .IN(w), .OUT(w_hp)); 
  regchain #(.NUM_STG(NUM_DELAY), .WIDTH(7)) u_regchain_round_ctr (.CLK(clk), .IN(round_ctr_reg), .OUT(round_ctr_reg_hp)); 







  always @*
    begin : state_logic
      reg [31 : 0] a5;
      reg [31 : 0] f;
      reg [31 : 0] k;
      reg [31 : 0] t;
      reg [31 : 0] t_tmp;

      a5     = 32'h0;
      f      = 32'h0;
      k      = 32'h0;
      t      = 32'h0;
      t_tmp  = 32'h0;
      a_new  = 32'h0;
      b_new  = 32'h0;
      c_new  = 32'h0;
      d_new  = 32'h0;
      e_new  = 32'h0;
      a_e_we = 0;

      if (state_init)
        begin
          if (first_block)
            begin
              a_new  = H0_0;
              b_new  = H0_1;
              c_new  = H0_2;
              d_new  = H0_3;
              e_new  = H0_4;
              a_e_we = 1;
            end
          else
            begin
              a_new  = H0_reg;
              b_new  = H1_reg;
              c_new  = H2_reg;
              d_new  = H3_reg;
              e_new  = H4_reg;
              a_e_we = 1;
            end
        end

      if (state_update)
        begin
          if (round_ctr_reg <= 19)
            begin
              k = 32'h5a827999;
              f =  ((b_reg_hp & c_reg_hp) ^ (~b_reg_hp & d_reg_hp));
            end
          else if ((round_ctr_reg >= 20) && (round_ctr_reg <= 39))
            begin
              k = 32'h6ed9eba1;
              f = b_reg_hp ^ c_reg_hp ^ d_reg_hp;
            end
          else if ((round_ctr_reg >= 40) && (round_ctr_reg <= 59))
            begin
              k = 32'h8f1bbcdc;
              f = ((b_reg_hp | c_reg_hp) ^ (b_reg_hp | d_reg_hp) ^ (c_reg_hp | d_reg_hp));
            end
          else if (round_ctr_reg >= 60)
            begin
              k = 32'hca62c1d6;
              f = b_reg_hp ^ c_reg_hp ^ d_reg_hp;
            end

          a5 = {a_reg_hp[26 : 0], a_reg_hp[31 : 27]};
          t_tmp = (e_reg_hp + k + f + w_hp);
          t = t_tmp + a5;

          a_new  = t;
          b_new  = a_reg_hp;
          c_new  = {b_reg_hp[1 : 0], b_reg_hp[31 : 2]};
          d_new  = c_reg_hp;
          e_new  = d_reg_hp;
          if(round_ctr_inc) 
            a_e_we = 1;
        end
    end
    

    reg [NUM_DELAY:0] stage_cnt_onehot_0q;
    reg [NUM_DELAY:0] next_stage_cnt; 
   
    always@(posedge clk) begin
      if(!reset_n) 
        stage_cnt_onehot_0q <= 'd1;
      else 
        stage_cnt_onehot_0q <= next_stage_cnt;
    end 








  always @*
    begin : round_ctr
      round_ctr_new = 0;
      round_ctr_we  = 0;

      if (round_ctr_rst)
        begin
          round_ctr_new = 0;
          round_ctr_we  = 1;
        end

      if (round_ctr_inc)
        begin

          round_ctr_new = round_ctr_reg_hp + 1'b1;
          round_ctr_we  = 1;
        end
    end






  always @*
    begin : sha1_ctrl_fsm
      digest_init      = 0;
      digest_update    = 0;
      state_init       = 0;
      state_update     = 0;
      first_block      = 0;
      ready_flag       = 0;
      w_init           = 0;
      w_next           = 0;
      round_ctr_inc    = 0;
      round_ctr_rst    = 0;
      digest_valid_new = 0;
      digest_valid_we  = 0;
      sha1_ctrl_new    = CTRL_IDLE;
      sha1_ctrl_we     = 0;
      next_stage_cnt   = 'd1; 

      case (sha1_ctrl_reg)
        CTRL_IDLE:
          begin
            ready_flag = 1;

            if (init)
              begin
                digest_init      = 1;
                w_init           = 1;
                state_init       = 1;
                first_block      = 1;
                round_ctr_rst    = 1;
                digest_valid_new = 0;
                digest_valid_we  = 1;
                sha1_ctrl_new    = CTRL_ROUNDS;
                sha1_ctrl_we     = 1;
                next_stage_cnt   = 'd1; 
              end

            if (next)
              begin
                w_init           = 1;
                state_init       = 1;
                round_ctr_rst    = 1;
                digest_valid_new = 0;
                digest_valid_we  = 1;
                sha1_ctrl_new    = CTRL_ROUNDS;
                sha1_ctrl_we     = 1;
                next_stage_cnt   = 'd1; 
              end
          end


        CTRL_ROUNDS:
          begin
            state_update  = 1;


          if(stage_cnt_onehot_0q[NUM_DELAY]) begin
            round_ctr_inc = 1;
            w_next        = 1;
            next_stage_cnt = 'd1;
          end 
          else 
            next_stage_cnt = stage_cnt_onehot_0q << 1; 

            if (round_ctr_reg == SHA1_ROUNDS)
              begin
                if(stage_cnt_onehot_0q[NUM_DELAY]) begin
                  sha1_ctrl_new = CTRL_DONE;
                  sha1_ctrl_we  = 1;
                end 
              end
          end


        CTRL_DONE:
          begin
            digest_update    = 1;
            digest_valid_new = 1;
            digest_valid_we  = 1;
            sha1_ctrl_new    = CTRL_IDLE;
            sha1_ctrl_we     = 1;
            next_stage_cnt   = 'd0; 
          end
      endcase
    end

endmodule