data/full_repos/permissive/121410129/7seg/7seg/AnodeSelector.v
data/verilator_xmls/1205a94e-2ea7-4373-b2c2-1efb9e3951f8.xml
module AnodeSelector (counter, an);

input wire [2:0]counter;
output reg an;

always @ (counter)
begin
	case (counter)
		3'b000:		an <= 1'b0;
		3'b001:		an <= 1'b0;
		3'b010:		an <= 1'b0;
		3'b011:		an <= 1'b0;
		default:	an <= 1'b1;
	endcase
end
endmodule
module AnodeSelector (counter, an);


input wire [2:0]counter;
output reg an;

always @ (counter)
begin
	case (counter)
		3'b000:		an <= 1'b0;
		3'b001:		an <= 1'b0;
		3'b010:		an <= 1'b0;
		3'b011:		an <= 1'b0;
		default:	an <= 1'b1;
	endcase
end
endmodule