data/full_repos/permissive/13953106/lib/LAG_simple.v
 line:14: before: "data_in"
1: b"%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:14: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     flit_t data_in;\n                    ^~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:15: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    flit_t data_out;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:30: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     chan_cntrl_t ctrl_in;\n                          ^~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:31: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    chan_cntrl_t ctrl_out;\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:49: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     flit_t data_in[nPC-1:0];\n                    ^~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:50: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     chan_cntrl_t ctrl_in;\n                          ^~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:51: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    flit_t data_out[nPC-1:0];\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:52: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    chan_cntrl_t ctrl_out;\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:57: Unsupported: Multidimensional cells/interfaces.\n   flit_t ch_reg[stages-1:0][nPC-1:0];\n                            ^\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:105: syntax error, unexpected IDENTIFIER, expecting ';'\n   input flit_t data_in [n-1:0];\n                ^~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:107: syntax error, unexpected IDENTIFIER, expecting ';'\n   output flit_t data_out;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:129: syntax error, unexpected IDENTIFIER, expecting ';'\n   input flit_t data_in [n-1:0];\n                ^~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_simple.v:132: syntax error, unexpected IDENTIFIER, expecting ';'\n   output flit_t data_out [n-1:0];\n                 ^~~~~~~~\n%Error: Exiting due to 13 error(s)\n"
module LAG_pipelined_channel (data_in, ctrl_in, data_out, ctrl_out, clk, rst_n);
    
   parameter stages = 0;
   parameter nPC = 1;

   input     flit_t data_in[nPC-1:0];
   input     chan_cntrl_t ctrl_in;
   output    flit_t data_out[nPC-1:0];
   output    chan_cntrl_t ctrl_out;
   input     clk, rst_n;

   genvar    st, pc;

   flit_t ch_reg[stages-1:0][nPC-1:0];
   chan_cntrl_t ctrl_reg[stages-1:0];
   
   generate
      if (stages==0) begin

	 assign data_out = data_in;
	 assign ctrl_out = ctrl_in;
      end else begin
	 for (st=0; st<stages; st++) begin:eachstage
	    if (st==0) begin
	       
	       for (pc = 0; pc < nPC; pc++) begin:eachPC1
            LAG_data_reg data_rg (.data_in(data_in[pc]), .data_out(ch_reg[0][pc]), .clk, .rst_n);
         end  
      

	    
      end else begin
	       for (pc = 0; pc < nPC; pc++) begin:eachPC2
	         LAG_data_reg data_rg (.data_in(ch_reg[st-1][pc]), .data_out(ch_reg[st][pc]), .clk, .rst_n);
	       end
	       

	       
      end
	 end


   assign data_out = ch_reg[stages-1];

	 assign ctrl_out = ctrl_in;
	 
      end
endgenerate   

endmodule
module LAG_pipelined_channel (data_in, ctrl_in, data_out, ctrl_out, clk, rst_n);

    
   parameter stages = 0;
   parameter nPC = 1;

   input     flit_t data_in[nPC-1:0];
   input     chan_cntrl_t ctrl_in;
   output    flit_t data_out[nPC-1:0];
   output    chan_cntrl_t ctrl_out;
   input     clk, rst_n;

   genvar    st, pc;

   flit_t ch_reg[stages-1:0][nPC-1:0];
   chan_cntrl_t ctrl_reg[stages-1:0];
   
   generate
      if (stages==0) begin

	 assign data_out = data_in;
	 assign ctrl_out = ctrl_in;
      end else begin
	 for (st=0; st<stages; st++) begin:eachstage
	    if (st==0) begin
	       
	       for (pc = 0; pc < nPC; pc++) begin:eachPC1
            LAG_data_reg data_rg (.data_in(data_in[pc]), .data_out(ch_reg[0][pc]), .clk, .rst_n);
         end  
      

	    
      end else begin
	       for (pc = 0; pc < nPC; pc++) begin:eachPC2
	         LAG_data_reg data_rg (.data_in(ch_reg[st-1][pc]), .data_out(ch_reg[st][pc]), .clk, .rst_n);
	       end
	       

	       
      end
	 end


   assign data_out = ch_reg[stages-1];

	 assign ctrl_out = ctrl_in;
	 
      end
endgenerate   

endmodule