data/full_repos/permissive/131249673/MIPS_L_PipeLine/ByPasser.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/ByPasser.v:1: Cannot find include file: ctrl_encode_def.v\n`include "ctrl_encode_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/ctrl_encode_def.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/ctrl_encode_def.v.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/ctrl_encode_def.v.sv\n             ctrl_encode_def.v\n             ctrl_encode_def.v.v\n             ctrl_encode_def.v.sv\n             obj_dir/ctrl_encode_def.v\n             obj_dir/ctrl_encode_def.v.v\n             obj_dir/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/ByPasser.v:2: Cannot find include file: instruction_def.v\n`include "instruction_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module byPasser ( WriteDst_MEM, WriteDst_WB,
	rs_EX, rt_EX,
	MEM_ctrl_RegWr, WB_ctrl_RegWr,
	byPasserSelA, byPasserSelB
	);

	input	[4:0]	WriteDst_MEM;
	input	[4:0]	WriteDst_WB;
	input	[4:0]	rs_EX;
	input	[4:0]	rt_EX;
	input			MEM_ctrl_RegWr;
	input			WB_ctrl_RegWr;
	
	output	[1:0]	byPasserSelA;
	output	[1:0]	byPasserSelB;

	reg [1:0]	byPasserSelA;
	reg	[1:0]	byPasserSelB;
  	
	always @(*) begin
	byPasserSelA = 2'b00;
	byPasserSelB = 2'b00;
	

	if (WB_ctrl_RegWr && WriteDst_WB != 0)
		begin
		if (rs_EX == WriteDst_WB)
			byPasserSelA = 2'b01;
		
		if (rt_EX == WriteDst_WB)
			byPasserSelB = 2'b01;
		end

	if (MEM_ctrl_RegWr && WriteDst_MEM != 0)
		begin
		if (rs_EX == WriteDst_MEM)
			byPasserSelA = 2'b10;

		if (rt_EX == WriteDst_MEM)
			byPasserSelB = 2'b10;
		end

	end
endmodule
module byPasser ( WriteDst_MEM, WriteDst_WB,
	rs_EX, rt_EX,
	MEM_ctrl_RegWr, WB_ctrl_RegWr,
	byPasserSelA, byPasserSelB
	);


	input	[4:0]	WriteDst_MEM;
	input	[4:0]	WriteDst_WB;
	input	[4:0]	rs_EX;
	input	[4:0]	rt_EX;
	input			MEM_ctrl_RegWr;
	input			WB_ctrl_RegWr;
	
	output	[1:0]	byPasserSelA;
	output	[1:0]	byPasserSelB;

	reg [1:0]	byPasserSelA;
	reg	[1:0]	byPasserSelB;
  	
	always @(*) begin
	byPasserSelA = 2'b00;
	byPasserSelB = 2'b00;
	

	if (WB_ctrl_RegWr && WriteDst_WB != 0)
		begin
		if (rs_EX == WriteDst_WB)
			byPasserSelA = 2'b01;
		
		if (rt_EX == WriteDst_WB)
			byPasserSelB = 2'b01;
		end

	if (MEM_ctrl_RegWr && WriteDst_MEM != 0)
		begin
		if (rs_EX == WriteDst_MEM)
			byPasserSelA = 2'b10;

		if (rt_EX == WriteDst_MEM)
			byPasserSelB = 2'b10;
		end

	end
endmodule