data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1000001;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1000010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1000011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1000100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1000101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1000110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1000111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1001000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1001001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1001010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1001011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1001100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1001101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1001110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 in=7\'b1001111;\n        ^\n%Error: data/full_repos/permissive/211316121/lab1/sim_1/new/sim_decoder416.v:26: Cannot find file containing module: \'Top_decoder416\'\n    Top_decoder416 simde416(in,out);\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab1/sim_1/new,data/full_repos/permissive/211316121/Top_decoder416\n             data/full_repos/permissive/211316121/lab1/sim_1/new,data/full_repos/permissive/211316121/Top_decoder416.v\n             data/full_repos/permissive/211316121/lab1/sim_1/new,data/full_repos/permissive/211316121/Top_decoder416.sv\n             Top_decoder416\n             Top_decoder416.v\n             Top_decoder416.sv\n             obj_dir/Top_decoder416\n             obj_dir/Top_decoder416.v\n             obj_dir/Top_decoder416.sv\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_decoder416();
    reg [6:0] in;
    wire [15:0] out;
    Top_decoder416 simde416(in,out);
    initial
        begin
            in=7'b1000000;
        #10 in=7'b1000001;
        #10 in=7'b1000010;
        #10 in=7'b1000011;
        #10 in=7'b1000100;
        #10 in=7'b1000101;
        #10 in=7'b1000110;
        #10 in=7'b1000111;
        #10 in=7'b1001000;
        #10 in=7'b1001001;
        #10 in=7'b1001010;
        #10 in=7'b1001011;
        #10 in=7'b1001100;
        #10 in=7'b1001101;
        #10 in=7'b1001110;
        #10 in=7'b1001111;
        end
endmodule
module sim_decoder416();

    reg [6:0] in;
    wire [15:0] out;
    Top_decoder416 simde416(in,out);
    initial
        begin
            in=7'b1000000;
        #10 in=7'b1000001;
        #10 in=7'b1000010;
        #10 in=7'b1000011;
        #10 in=7'b1000100;
        #10 in=7'b1000101;
        #10 in=7'b1000110;
        #10 in=7'b1000111;
        #10 in=7'b1001000;
        #10 in=7'b1001001;
        #10 in=7'b1001010;
        #10 in=7'b1001011;
        #10 in=7'b1001100;
        #10 in=7'b1001101;
        #10 in=7'b1001110;
        #10 in=7'b1001111;
        end
endmodule