data/full_repos/permissive/168395472/problems/08_cpu_v2/rom.v
data/verilator_xmls/753cc8d7-b4fd-4250-88b7-4aa6c369d292.xml
module rom #(parameter ADDR_WIDTH = 3, parameter WIDTH = 32)(
    input [ADDR_WIDTH - 1:0]addr,
    input clk,

    output reg [WIDTH - 1:0]q
);

initial begin
    q = 0;
end

reg [WIDTH - 1:0]mem[2**ADDR_WIDTH - 1:0];

initial begin
    $readmemh("samples/test_v2.txt", mem);
end

always @(posedge clk) begin
    q <= mem[addr];
end

endmodule
module rom #(parameter ADDR_WIDTH = 3, parameter WIDTH = 32)(
    input [ADDR_WIDTH - 1:0]addr,
    input clk,

    output reg [WIDTH - 1:0]q
);


initial begin
    q = 0;
end

reg [WIDTH - 1:0]mem[2**ADDR_WIDTH - 1:0];

initial begin
    $readmemh("samples/test_v2.txt", mem);
end

always @(posedge clk) begin
    q <= mem[addr];
end

endmodule