data/full_repos/permissive/150947952/doc/ref/fpga-md5-cracker/commented-verilog/LcdLineWriter.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/150947952/doc/ref/fpga-md5-cracker/commented-verilog/LcdLineWriter.v:64: Multiple top level modules\n                                                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                     : ... Top module \'LcdLineWriter\'\nmodule LcdLineWriter(\n       ^~~~~~~~~~~~~\n                                                                                                                     : ... Top module \'LcdLineWriterTester\'\nmodule LcdLineWriterTester(\n       ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/150947952/doc/ref/fpga-md5-cracker/commented-verilog/LcdLineWriter.v:43: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                                                                  : ... In instance LcdLineWriter\n       char <= charArray[state] != \'h00 ? charArray[state] : \'h20;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/150947952/doc/ref/fpga-md5-cracker/commented-verilog/LcdLineWriter.v:43: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                                                                  : ... In instance LcdLineWriter\n       char <= charArray[state] != \'h00 ? charArray[state] : \'h20;\n                                                   ^\n%Error: Exiting due to 3 warning(s)\n'
module LcdLineWriter(
	input wire clk,
	input wire ready,
	input wire [127:0] line,
	output reg [7:0] char = 0,
	output reg writeChar = 0,
	output reg home = 0
);

`define AssignChar(__ofs) assign charArray[__ofs] = line[__ofs * 8 + 7 : __ofs * 8];


wire [7:0] charArray[0:63];



`AssignChar(0)
`AssignChar(1)
`AssignChar(2)
`AssignChar(3)
`AssignChar(4)
`AssignChar(5)
`AssignChar(6)
`AssignChar(7)
`AssignChar(8)
`AssignChar(9)
`AssignChar(10)
`AssignChar(11)
`AssignChar(12)
`AssignChar(13)
`AssignChar(14)
`AssignChar(15)

reg [7:0] state = 0;

always @(posedge clk)
	if (ready)
		begin
			if (!writeChar && !home)
				begin
					if (state != 16)
						begin
							char <= charArray[state] != 'h00 ? charArray[state] : 'h20;
							writeChar <= 1;
							state <= state + 1;
						end
					else
						begin
							state <= 0;
							writeChar <= 0;
							home <= 1;
						end
				end
		end
	else
		begin
			writeChar <= 0;
			home <= 0;
		end

endmodule
module LcdLineWriter(
	input wire clk,
	input wire ready,
	input wire [127:0] line,
	output reg [7:0] char = 0,
	output reg writeChar = 0,
	output reg home = 0
);


`define AssignChar(__ofs) assign charArray[__ofs] = line[__ofs * 8 + 7 : __ofs * 8];


wire [7:0] charArray[0:63];



`AssignChar(0)
`AssignChar(1)
`AssignChar(2)
`AssignChar(3)
`AssignChar(4)
`AssignChar(5)
`AssignChar(6)
`AssignChar(7)
`AssignChar(8)
`AssignChar(9)
`AssignChar(10)
`AssignChar(11)
`AssignChar(12)
`AssignChar(13)
`AssignChar(14)
`AssignChar(15)

reg [7:0] state = 0;

always @(posedge clk)
	if (ready)
		begin
			if (!writeChar && !home)
				begin
					if (state != 16)
						begin
							char <= charArray[state] != 'h00 ? charArray[state] : 'h20;
							writeChar <= 1;
							state <= state + 1;
						end
					else
						begin
							state <= 0;
							writeChar <= 0;
							home <= 1;
						end
				end
		end
	else
		begin
			writeChar <= 0;
			home <= 0;
		end

endmodule