data/full_repos/permissive/201025648/Verilog/3.52.v
 line:7: before: ","
1: b'%Error: data/full_repos/permissive/201025648/Verilog/3.52.v:7: Unsupported or unknown PLI call: $monitor\n$monitor($time,,"set=",set);\n^~~~~~~~\n%Error: data/full_repos/permissive/201025648/Verilog/3.52.v:7: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n$monitor($time,,"set=",set);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/201025648/Verilog/3.52.v:8: Unsupported: Ignoring delay on this delayed statement.\n#p set=0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/201025648/Verilog/3.52.v:9: Unsupported: Ignoring delay on this delayed statement.\n#p set=1;\n^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
reg set;
parameter p=1.6;
initial
begin
$monitor($time,,"set=",set);
#p set=0;
#p set=1;
end 
endmodule
module test;

reg set;
parameter p=1.6;
initial
begin
$monitor($time,,"set=",set);
#p set=0;
#p set=1;
end 
endmodule