data/full_repos/permissive/210946536/src/modules/hazard_unit.v
data/verilator_xmls/d2f0b173-3589-4279-a4d7-c402f5df0647.xml
module hazard_unit
  #(
    parameter NB_REG_ADDR   = 5,
    parameter NB_OPCODE     = 6

    )
   (
    output                  o_hazard,

    input                   i_re_exec,
    input                   i_re_mem,
    input                   i_jmp_branch,
    input [NB_REG_ADDR-1:0] i_rd_exec,
    input [NB_REG_ADDR-1:0] i_rd_mem,
    input                   i_rd_exec_we,
    input                   i_rd_mem_we,
    input [NB_REG_ADDR-1:0] i_rs,
    input [NB_REG_ADDR-1:0] i_rt,
    input                   i_rinst,

    input                   i_clock,
    input                   i_reset,
    input                   i_valid
    ) ;







   wire                     instr_after_load;
   wire                     branch_after_instr;
   wire                     branch_after_load;

























   assign instr_after_load = ((i_rd_exec == i_rs) | ((i_rd_exec == i_rt))) & i_re_exec;
   assign branch_after_instr = ((i_rd_exec == i_rs) | (i_rd_exec == i_rt)) & i_jmp_branch & i_rd_exec_we;
   assign branch_after_load = ((i_rd_mem == i_rs) | (i_rd_mem == i_rt)) & (i_re_mem & i_jmp_branch) & i_rd_mem_we;

   assign o_hazard = (instr_after_load | branch_after_instr | branch_after_load);

endmodule
module hazard_unit
  #(
    parameter NB_REG_ADDR   = 5,
    parameter NB_OPCODE     = 6

    )
   (
    output                  o_hazard,

    input                   i_re_exec,
    input                   i_re_mem,
    input                   i_jmp_branch,
    input [NB_REG_ADDR-1:0] i_rd_exec,
    input [NB_REG_ADDR-1:0] i_rd_mem,
    input                   i_rd_exec_we,
    input                   i_rd_mem_we,
    input [NB_REG_ADDR-1:0] i_rs,
    input [NB_REG_ADDR-1:0] i_rt,
    input                   i_rinst,

    input                   i_clock,
    input                   i_reset,
    input                   i_valid
    ) ;








   wire                     instr_after_load;
   wire                     branch_after_instr;
   wire                     branch_after_load;

























   assign instr_after_load = ((i_rd_exec == i_rs) | ((i_rd_exec == i_rt))) & i_re_exec;
   assign branch_after_instr = ((i_rd_exec == i_rs) | (i_rd_exec == i_rt)) & i_jmp_branch & i_rd_exec_we;
   assign branch_after_load = ((i_rd_mem == i_rs) | (i_rd_mem == i_rt)) & (i_re_mem & i_jmp_branch) & i_rd_mem_we;

   assign o_hazard = (instr_after_load | branch_after_instr | branch_after_load);

endmodule