data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v
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1: b'%Warning-LITENDIAN: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:172: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire  [0:7] SPCD;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:173: Cannot find file containing module: \'SPCHIP_ROM\'\nSPCHIP_ROM spchip( ~VCLKx8, SPCA, SPCD, DLCL,DLAD,DLDT,DLEN );\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/SPCHIP_ROM\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/SPCHIP_ROM.v\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/SPCHIP_ROM.sv\n             SPCHIP_ROM\n             SPCHIP_ROM.v\n             SPCHIP_ROM.sv\n             obj_dir/SPCHIP_ROM\n             obj_dir/SPCHIP_ROM.v\n             obj_dir/SPCHIP_ROM.sv\n%Warning-WIDTH: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:191: Operator GTE expects 8 bits on the LHS, but LHS\'s VARREF \'sano\' generates 6 bits.\n                                                                               : ... In instance VIDEO.spr\n    if (sano >= 8\'h30) phase <= 0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:236: Operator ADD expects 9 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                               : ... In instance VIDEO.spr\nwire [8:0] wpx = px+xcnt[3:0];\n                   ^\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:247: Cannot find file containing module: \'SPCLUT_ROM\'\nSPCLUT_ROM spclut(VCLKx8, pix, opix, DLCL,DLAD,DLDT,DLEN );\n^~~~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:258: Cannot find file containing module: \'LineBuf\'\nLineBuf lbuf(VCLKx8,lbwe & (lbdt!=0),lbad,lbdt, VCLKx8,(radr0==radr1),radr0,ispt);\n^~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:72: Cannot find file containing module: \'VRAM2048\'\nVRAM2048 cram( CPUCL, CPUAD[10:0], CS_CRAM, CPUWR, CPUWD, OD_CRAM, VCLKx4, BGVA, BGCR ); \n^~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:73: Cannot find file containing module: \'VRAM2048\'\nVRAM2048 vram( CPUCL, CPUAD[10:0], CS_VRAM, CPUWR, CPUWD, OD_VRAM, VCLKx4, BGVA, BGVR ); \n^~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:74: Cannot find file containing module: \'VRAM4096\'\nVRAM4096 mram( CPUCL, CPUAD[11:0], CS_MRAM, CPUWR, CPUWD, OD_MRAM,~VCLKx8, SAAD, SATD );\n^~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:75: Cannot find file containing module: \'VRAM32\'\nVRAM32   zrm0( CPUCL, CPUAD[ 4:0], CS_ZRM0, CPUWR, CPUWD, OD_ZRM0, VCLKx4, ZRMA, ZRM0 ); \n^~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:76: Cannot find file containing module: \'VRAM32\'\nVRAM32   zrm1( CPUCL, CPUAD[ 4:0], CS_ZRM1, CPUWR, CPUWD, OD_ZRM1, VCLKx4, ZRMA, ZRM1 ); \n^~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:92: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire  [0:7] BGCD;\n      ^\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:93: Cannot find file containing module: \'BGCHIP_ROM\'\nBGCHIP_ROM bgchip( VCLKx2, BGCA, BGCD, DLCL,DLAD,DLDT,DLEN );\n^~~~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:97: Cannot find file containing module: \'BGCLUT_ROM\'\nBGCLUT_ROM bgclut( ~VCLK, BGCT, BGPT, DLCL,DLAD,DLDT,DLEN );\n^~~~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:117: Cannot find file containing module: \'PALET_ROM\'\nPALET_ROM  palet( VCLK, PALIN, PALET, DLCL,DLAD,DLDT,DLEN );\n^~~~~~~~~\n%Error: Exiting due to 11 error(s), 4 warning(s)\n'
module SPRRENDER
(
	input					VCLKx8,
	input					VCLK,

	input  [8:0]		SPHP,
	input	 [8:0]		SPVP,

	output [7:0]		SATA,
	input  [7:0]		SATD,
	
	output reg [3:0]	SPPT,


	input					DLCL,
	input  [17:0]  	DLAD,
	input   [7:0]		DLDT,
	input					DLEN
);

reg  [5:0]	sano;
reg  [1:0]	saof;
reg  [7:0]	sat0, sat1, sat2, sat3;

reg  [2:0]	phase;

wire [8:0]	px    = {1'b0,sat2} - {sat1[7],8'h0};
wire [7:0]	py    = (phase==1) ? SATD : sat3;
wire			fx		= sat1[4];
wire			fy		= sat1[5];
wire [8:0] 	code  = {sat1[6],sat0};
wire [3:0]	color = sat1[3:0];

wire [8:0]	ht    = {1'b0,py}-SPVP;
wire			hy    = (py!=0) & (ht[8:4]==5'b11111);

reg  [4:0]	xcnt;
wire [3:0]	lx		= xcnt[3:0]^{4{ fx}};
wire [3:0]	ly		=   ht[3:0]^{4{~fy}};

wire [15:0] SPCA	= {code,ly[3],lx[3],ly[2:0],lx[2:1]};
wire  [0:7] SPCD;
SPCHIP_ROM	spchip( ~VCLKx8, SPCA, SPCD, DLCL,DLAD,DLDT,DLEN );

wire [7:0]	pix	= {color,(lx[0] ? SPCD[4:7]:SPCD[0:3])};


`define SPRITES 8'h30

always @( posedge VCLKx8 ) begin
	if (SPHP==0) begin
		xcnt  <= 0;
		sano  <= 0;
		saof  <= 3;
		phase <= 1;
	end
	else case (phase)
		0:;

		1: begin
				if (sano >= `SPRITES) phase <= 0;
				else begin
					if (hy) begin
						sat3  <= SATD;
						saof  <= 2;
						phase <= phase+3'd1;
					end
					else sano <= sano+6'd1;
				end
			end

		2: begin
				sat2  <= SATD;
				saof  <= 1;
				phase <= phase+3'd1;
			end
		
		3: begin
				sat1  <= SATD;
				saof  <= 0;
				phase <= phase+3'd1;
			end

		4: begin
				sat0  <= SATD;
				saof  <= 3;
				sano  <= sano+6'd1;
				xcnt  <= 5'b1_0000;
				phase <= phase+3'd1;
			end

		5: begin
				xcnt  <= xcnt+5'd1;
				phase <= wre ? phase : 3'd1;
			end

		default:;
	endcase
end

assign SATA = {sano,saof};


wire			wre = xcnt[4];
wire			sid = SPVP[0];
wire [8:0]	wpx = px+xcnt[3:0];


reg  [9:0] lbad;
reg  [3:0] lbdt;
reg        lbwe;
always @(posedge VCLKx8) begin
	lbad <= {~sid,wpx};
	lbwe <= wre;
end
wire [3:0] opix;
SPCLUT_ROM spclut(VCLKx8, pix, opix, DLCL,DLAD,DLDT,DLEN );
always @(negedge VCLKx8) lbdt <= opix;


reg  [9:0] radr0=0,radr1=1;
wire [3:0] ispt;
always @(negedge VCLK) radr0 <= {sid,SPHP}; 
always @(posedge VCLK) begin
	if (radr0!=radr1) SPPT <= ispt;
	radr1 <= radr0;
end
LineBuf lbuf(VCLKx8,lbwe & (lbdt!=0),lbad,lbdt, VCLKx8,(radr0==radr1),radr0,ispt);

endmodule
module SPRRENDER
(
	input					VCLKx8,
	input					VCLK,

	input  [8:0]		SPHP,
	input	 [8:0]		SPVP,

	output [7:0]		SATA,
	input  [7:0]		SATD,
	
	output reg [3:0]	SPPT,


	input					DLCL,
	input  [17:0]  	DLAD,
	input   [7:0]		DLDT,
	input					DLEN
);


reg  [5:0]	sano;
reg  [1:0]	saof;
reg  [7:0]	sat0, sat1, sat2, sat3;

reg  [2:0]	phase;

wire [8:0]	px    = {1'b0,sat2} - {sat1[7],8'h0};
wire [7:0]	py    = (phase==1) ? SATD : sat3;
wire			fx		= sat1[4];
wire			fy		= sat1[5];
wire [8:0] 	code  = {sat1[6],sat0};
wire [3:0]	color = sat1[3:0];

wire [8:0]	ht    = {1'b0,py}-SPVP;
wire			hy    = (py!=0) & (ht[8:4]==5'b11111);

reg  [4:0]	xcnt;
wire [3:0]	lx		= xcnt[3:0]^{4{ fx}};
wire [3:0]	ly		=   ht[3:0]^{4{~fy}};

wire [15:0] SPCA	= {code,ly[3],lx[3],ly[2:0],lx[2:1]};
wire  [0:7] SPCD;
SPCHIP_ROM	spchip( ~VCLKx8, SPCA, SPCD, DLCL,DLAD,DLDT,DLEN );

wire [7:0]	pix	= {color,(lx[0] ? SPCD[4:7]:SPCD[0:3])};


`define SPRITES 8'h30

always @( posedge VCLKx8 ) begin
	if (SPHP==0) begin
		xcnt  <= 0;
		sano  <= 0;
		saof  <= 3;
		phase <= 1;
	end
	else case (phase)
		0:;

		1: begin
				if (sano >= `SPRITES) phase <= 0;
				else begin
					if (hy) begin
						sat3  <= SATD;
						saof  <= 2;
						phase <= phase+3'd1;
					end
					else sano <= sano+6'd1;
				end
			end

		2: begin
				sat2  <= SATD;
				saof  <= 1;
				phase <= phase+3'd1;
			end
		
		3: begin
				sat1  <= SATD;
				saof  <= 0;
				phase <= phase+3'd1;
			end

		4: begin
				sat0  <= SATD;
				saof  <= 3;
				sano  <= sano+6'd1;
				xcnt  <= 5'b1_0000;
				phase <= phase+3'd1;
			end

		5: begin
				xcnt  <= xcnt+5'd1;
				phase <= wre ? phase : 3'd1;
			end

		default:;
	endcase
end

assign SATA = {sano,saof};


wire			wre = xcnt[4];
wire			sid = SPVP[0];
wire [8:0]	wpx = px+xcnt[3:0];


reg  [9:0] lbad;
reg  [3:0] lbdt;
reg        lbwe;
always @(posedge VCLKx8) begin
	lbad <= {~sid,wpx};
	lbwe <= wre;
end
wire [3:0] opix;
SPCLUT_ROM spclut(VCLKx8, pix, opix, DLCL,DLAD,DLDT,DLEN );
always @(negedge VCLKx8) lbdt <= opix;


reg  [9:0] radr0=0,radr1=1;
wire [3:0] ispt;
always @(negedge VCLK) radr0 <= {sid,SPHP}; 
always @(posedge VCLK) begin
	if (radr0!=radr1) SPPT <= ispt;
	radr1 <= radr0;
end
LineBuf lbuf(VCLKx8,lbwe & (lbdt!=0),lbad,lbdt, VCLKx8,(radr0==radr1),radr0,ispt);

endmodule