data/full_repos/permissive/108382235/Pipelined.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC,  SwitchClk_10, reset);\n       ^~~~~~~~~\n                                                                       : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  if (MemRead) ReadData=Dmemory[Address[31:2]];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n                                                                    : ... In instance Pipelined\n   IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n                ^~\n%Error: Exiting due to 5 warning(s)\n'
module SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);
	input [3:0] Num_0, Num_1, Num_2, Num_3;
	input clk_500;
	output [6:0] Cathod;
	output [3:0] Anode;
	reg [6:0] Cathod;
	reg [3:0] Anode;
	reg [1:0] digit=0;
	
	always @ (posedge clk_500)
	begin
		case(digit)
			2'b00: digit<=2'b01;
			2'b01: digit<=2'b10;
			2'b10: digit<=2'b11;
			2'b11: digit<=2'b00;
		endcase
	end
	always @(digit, Num_0, Num_1, Num_2, Num_3)
	begin 
		case (digit)
			2'b00: begin 
				Anode <= 4'b1110; 

				case (Num_0)
					4'b0000: Cathod <= 7'b0000001; 
					4'b0001: Cathod <= 7'b1001111;
					4'b0010: Cathod <= 7'b0010010;
					4'b0011: Cathod <= 7'b0000110;
					4'b0100: Cathod <= 7'b1001100;
					4'b0101: Cathod <= 7'b0100100;
					4'b0110: Cathod <= 7'b0100000;
					4'b0111: Cathod <= 7'b0001111;
					4'b1000: Cathod <= 7'b0000000;
					4'b1001: Cathod <= 7'b0000100;
					4'b1010: Cathod <= 7'b0001000;
					4'b1011: Cathod <= 7'b1100000;
					4'b1100: Cathod <= 7'b0110001;
					4'b1101: Cathod <= 7'b1000010;
					4'b1110: Cathod <= 7'b0110000;
					default: Cathod <= 7'b0111000;
				endcase end
			2'b01: begin 
				Anode <= 4'b1101;

				case (Num_1)
					4'b0000: Cathod <= 7'b0000001; 
					4'b0001: Cathod <= 7'b1001111;
					4'b0010: Cathod <= 7'b0010010;
					4'b0011: Cathod <= 7'b0000110;
					4'b0100: Cathod <= 7'b1001100;
					4'b0101: Cathod <= 7'b0100100;
					4'b0110: Cathod <= 7'b0100000;
					4'b0111: Cathod <= 7'b0001111;
					4'b1000: Cathod <= 7'b0000000;
					4'b1001: Cathod <= 7'b0000100;
					4'b1010: Cathod <= 7'b0001000;
					4'b1011: Cathod <= 7'b1100000;
					4'b1100: Cathod <= 7'b0110001;
					4'b1101: Cathod <= 7'b1000010;
					4'b1110: Cathod <= 7'b0110000;
					default: Cathod <= 7'b0111000;
				endcase end
			2'b10: begin 
				Anode <= 4'b1011;

				case (Num_2)
					4'b0000: Cathod <= 7'b0000001; 
					4'b0001: Cathod <= 7'b1001111;
					4'b0010: Cathod <= 7'b0010010;
					4'b0011: Cathod <= 7'b0000110;
					4'b0100: Cathod <= 7'b1001100;
					4'b0101: Cathod <= 7'b0100100;
					4'b0110: Cathod <= 7'b0100000;
					4'b0111: Cathod <= 7'b0001111;
					4'b1000: Cathod <= 7'b0000000;
					4'b1001: Cathod <= 7'b0000100;
					4'b1010: Cathod <= 7'b0001000;
					4'b1011: Cathod <= 7'b1100000;
					4'b1100: Cathod <= 7'b0110001;
					4'b1101: Cathod <= 7'b1000010;
					4'b1110: Cathod <= 7'b0110000;
					default: Cathod <= 7'b0111000;
				endcase end
			2'b11: begin 
				Anode <= 4'b0111;

				case (Num_3)
					4'b0000: Cathod <= 7'b0000001; 
					4'b0001: Cathod <= 7'b1001111;
					4'b0010: Cathod <= 7'b0010010;
					4'b0011: Cathod <= 7'b0000110;
					4'b0100: Cathod <= 7'b1001100;
					4'b0101: Cathod <= 7'b0100100;
					4'b0110: Cathod <= 7'b0100000;
					4'b0111: Cathod <= 7'b0001111;
					4'b1000: Cathod <= 7'b0000000;
					4'b1001: Cathod <= 7'b0000100;
					4'b1010: Cathod <= 7'b0001000;
					4'b1011: Cathod <= 7'b1100000;
					4'b1100: Cathod <= 7'b0110001;
					4'b1101: Cathod <= 7'b1000010;
					4'b1110: Cathod <= 7'b0110000;
					default: Cathod <= 7'b0111000;
				endcase end
		endcase
	end
endmodule
module SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);

	input [3:0] Num_0, Num_1, Num_2, Num_3;
	input clk_500;
	output [6:0] Cathod;
	output [3:0] Anode;
	reg [6:0] Cathod;
	reg [3:0] Anode;
	reg [1:0] digit=0;
	
	always @ (posedge clk_500)
	begin
		case(digit)
			2'b00: digit<=2'b01;
			2'b01: digit<=2'b10;
			2'b10: digit<=2'b11;
			2'b11: digit<=2'b00;
		endcase
	end
	always @(digit, Num_0, Num_1, Num_2, Num_3)
	begin 
		case (digit)
			2'b00: begin 
				Anode <= 4'b1110; 

				case (Num_0)
					4'b0000: Cathod <= 7'b0000001; 
					4'b0001: Cathod <= 7'b1001111;
					4'b0010: Cathod <= 7'b0010010;
					4'b0011: Cathod <= 7'b0000110;
					4'b0100: Cathod <= 7'b1001100;
					4'b0101: Cathod <= 7'b0100100;
					4'b0110: Cathod <= 7'b0100000;
					4'b0111: Cathod <= 7'b0001111;
					4'b1000: Cathod <= 7'b0000000;
					4'b1001: Cathod <= 7'b0000100;
					4'b1010: Cathod <= 7'b0001000;
					4'b1011: Cathod <= 7'b1100000;
					4'b1100: Cathod <= 7'b0110001;
					4'b1101: Cathod <= 7'b1000010;
					4'b1110: Cathod <= 7'b0110000;
					default: Cathod <= 7'b0111000;
				endcase end
			2'b01: begin 
				Anode <= 4'b1101;

				case (Num_1)
					4'b0000: Cathod <= 7'b0000001; 
					4'b0001: Cathod <= 7'b1001111;
					4'b0010: Cathod <= 7'b0010010;
					4'b0011: Cathod <= 7'b0000110;
					4'b0100: Cathod <= 7'b1001100;
					4'b0101: Cathod <= 7'b0100100;
					4'b0110: Cathod <= 7'b0100000;
					4'b0111: Cathod <= 7'b0001111;
					4'b1000: Cathod <= 7'b0000000;
					4'b1001: Cathod <= 7'b0000100;
					4'b1010: Cathod <= 7'b0001000;
					4'b1011: Cathod <= 7'b1100000;
					4'b1100: Cathod <= 7'b0110001;
					4'b1101: Cathod <= 7'b1000010;
					4'b1110: Cathod <= 7'b0110000;
					default: Cathod <= 7'b0111000;
				endcase end
			2'b10: begin 
				Anode <= 4'b1011;

				case (Num_2)
					4'b0000: Cathod <= 7'b0000001; 
					4'b0001: Cathod <= 7'b1001111;
					4'b0010: Cathod <= 7'b0010010;
					4'b0011: Cathod <= 7'b0000110;
					4'b0100: Cathod <= 7'b1001100;
					4'b0101: Cathod <= 7'b0100100;
					4'b0110: Cathod <= 7'b0100000;
					4'b0111: Cathod <= 7'b0001111;
					4'b1000: Cathod <= 7'b0000000;
					4'b1001: Cathod <= 7'b0000100;
					4'b1010: Cathod <= 7'b0001000;
					4'b1011: Cathod <= 7'b1100000;
					4'b1100: Cathod <= 7'b0110001;
					4'b1101: Cathod <= 7'b1000010;
					4'b1110: Cathod <= 7'b0110000;
					default: Cathod <= 7'b0111000;
				endcase end
			2'b11: begin 
				Anode <= 4'b0111;

				case (Num_3)
					4'b0000: Cathod <= 7'b0000001; 
					4'b0001: Cathod <= 7'b1001111;
					4'b0010: Cathod <= 7'b0010010;
					4'b0011: Cathod <= 7'b0000110;
					4'b0100: Cathod <= 7'b1001100;
					4'b0101: Cathod <= 7'b0100100;
					4'b0110: Cathod <= 7'b0100000;
					4'b0111: Cathod <= 7'b0001111;
					4'b1000: Cathod <= 7'b0000000;
					4'b1001: Cathod <= 7'b0000100;
					4'b1010: Cathod <= 7'b0001000;
					4'b1011: Cathod <= 7'b1100000;
					4'b1100: Cathod <= 7'b0110001;
					4'b1101: Cathod <= 7'b1000010;
					4'b1110: Cathod <= 7'b0110000;
					default: Cathod <= 7'b0111000;
				endcase end
		endcase
	end
endmodule