data/full_repos/permissive/167274925/ProgramCounter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167274925/ProgramCounter_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 Clk <= ~Clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/167274925/ProgramCounter_tb.v:32: syntax error, unexpected \'@\'\n @(posedge Clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/ProgramCounter_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Error: data/full_repos/permissive/167274925/ProgramCounter_tb.v:35: syntax error, unexpected \'@\'\n @(posedge Clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/ProgramCounter_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/ProgramCounter_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #30;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/ProgramCounter_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ProgramCounter_tb(); 

	reg [31:0] Address;
	reg Reset, Clk;

	wire [31:0] PCResult;

    ProgramCounter u0(
        .Address(Address), 
        .PCResult(PCResult), 
        .Reset(Reset), 
        .Clk(Clk)
    );

	initial begin
		Clk <= 1'b0;
		forever #10 Clk <= ~Clk;
	end

	initial begin
	Reset<=1;
	Address<=32'd0;
	@(posedge Clk);
	#5;
	Reset<=0;
	@(posedge Clk);
    #5;
    Address<=32'd4;
    #30;
    Reset<=1;
    #100;
	end

endmodule
module ProgramCounter_tb();
 

	reg [31:0] Address;
	reg Reset, Clk;

	wire [31:0] PCResult;

    ProgramCounter u0(
        .Address(Address), 
        .PCResult(PCResult), 
        .Reset(Reset), 
        .Clk(Clk)
    );

	initial begin
		Clk <= 1'b0;
		forever #10 Clk <= ~Clk;
	end

	initial begin
	Reset<=1;
	Address<=32'd0;
	@(posedge Clk);
	#5;
	Reset<=0;
	@(posedge Clk);
    #5;
    Address<=32'd4;
    #30;
    Reset<=1;
    #100;
	end

endmodule