data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v
'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte
1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n             const_defination.v\n             const_defination.v.v\n             const_defination.v.sv\n             obj_dir/const_defination.v\n             obj_dir/const_defination.v.v\n             obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:25: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] valE,valA,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`digitsBus] valE,valA,\n                         ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:26: Define or directive not defined: \'`icodeBus\'\n    input wire[`icodeBus] icode,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:27: Define or directive not defined: \'`digitsBus\'\n    output reg[`digitsBus] dstM,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:29: syntax error, unexpected \')\', expecting \',\' or \';\'\n    );\n    ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:34: Define or directive not defined: \'`rmmovq\'\n            `rmmovq:\n            ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:36: Define or directive not defined: \'`mrmovq\'\n                    if({icode,4\'h0}==`mrmovq)\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:48: Define or directive not defined: \'`pushq\'\n            `pushq:\n            ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:50: Define or directive not defined: \'`mrmovq\'\n                    if({icode,4\'h0}==`mrmovq)\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:62: Define or directive not defined: \'`call\'\n   `call:\n   ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:64: Define or directive not defined: \'`mrmovq\'\n                    if({icode,4\'h0}==`mrmovq)\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:76: Define or directive not defined: \'`mrmovq\'\n            `mrmovq:\n            ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:78: Define or directive not defined: \'`mrmovq\'\n                    if({icode,4\'h0}==`mrmovq)\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:90: Define or directive not defined: \'`popq\'\n   `popq:\n   ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/memOperation.v:96: Define or directive not defined: \'`ret\'\n            `ret:\n            ^~~~\n%Error: Exiting due to 16 error(s)\n'
module memOperation(
    input wire[`digitsBus] valE,valA,
    input wire[`icodeBus] icode,
    output reg[`digitsBus] dstM,
    output reg enabler,enablew
    );
    
    always@(*)
    begin
        case({icode,4'h0})
            `rmmovq:
                begin
                    if({icode,4'h0}==`mrmovq)
                    begin
                        enablew<=0;
                        enabler<=1;
                    end
                    else
                    begin
                        enablew<=1;
                        enabler<=0;
                    end
                    dstM<=valE;
                end
            `pushq:
                begin
                    if({icode,4'h0}==`mrmovq)
                    begin
                        enablew<=0;
                        enabler<=1;
                    end
                    else
                    begin
                        enablew<=1;
                        enabler<=0;
                    end
                    dstM<=valE;
                end
			`call:
                begin
                    if({icode,4'h0}==`mrmovq)
                    begin
                        enablew<=0;
                        enabler<=1;
                    end
                    else
                    begin
                        enablew<=1;
                        enabler<=0;
                    end
                    dstM<=valE;
                end
            `mrmovq:
                begin
                    if({icode,4'h0}==`mrmovq)
                    begin
                        enablew<=0;
                        enabler<=1;
                    end
                    else
                    begin
                        enablew<=1;
                        enabler<=0;
                    end
                    dstM<=valE;
                end
			`popq:
                begin
                    dstM<=valA;
                    enablew<=0;
                    enabler<=1;
                end
            `ret:
                begin
                    dstM<=valA;
                    enablew<=0;
                    enabler<=1;
                end
			default:
            begin
                enablew<=0;
                enabler<=0;
            end
        endcase
    end
endmodule
module memOperation(
    input wire[`digitsBus] valE,valA,
    input wire[`icodeBus] icode,
    output reg[`digitsBus] dstM,
    output reg enabler,enablew
    );

    
    always@(*)
    begin
        case({icode,4'h0})
            `rmmovq:
                begin
                    if({icode,4'h0}==`mrmovq)
                    begin
                        enablew<=0;
                        enabler<=1;
                    end
                    else
                    begin
                        enablew<=1;
                        enabler<=0;
                    end
                    dstM<=valE;
                end
            `pushq:
                begin
                    if({icode,4'h0}==`mrmovq)
                    begin
                        enablew<=0;
                        enabler<=1;
                    end
                    else
                    begin
                        enablew<=1;
                        enabler<=0;
                    end
                    dstM<=valE;
                end
			`call:
                begin
                    if({icode,4'h0}==`mrmovq)
                    begin
                        enablew<=0;
                        enabler<=1;
                    end
                    else
                    begin
                        enablew<=1;
                        enabler<=0;
                    end
                    dstM<=valE;
                end
            `mrmovq:
                begin
                    if({icode,4'h0}==`mrmovq)
                    begin
                        enablew<=0;
                        enabler<=1;
                    end
                    else
                    begin
                        enablew<=1;
                        enabler<=0;
                    end
                    dstM<=valE;
                end
			`popq:
                begin
                    dstM<=valA;
                    enablew<=0;
                    enabler<=1;
                end
            `ret:
                begin
                    dstM<=valA;
                    enablew<=0;
                    enabler<=1;
                end
			default:
            begin
                enablew<=0;
                enabler<=0;
            end
        endcase
    end
endmodule