data/full_repos/permissive/126085346/src/apple_iie_pal.v
1: b"%Error: data/full_repos/permissive/126085346/src/apple_iie_pal.v:37: Cannot find file containing module: 'ClockDivideByN'\n    ClockDivideByN #(\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/126085346/src,data/full_repos/permissive/126085346/ClockDivideByN\n             data/full_repos/permissive/126085346/src,data/full_repos/permissive/126085346/ClockDivideByN.v\n             data/full_repos/permissive/126085346/src,data/full_repos/permissive/126085346/ClockDivideByN.sv\n             ClockDivideByN\n             ClockDivideByN.v\n             ClockDivideByN.sv\n             obj_dir/ClockDivideByN\n             obj_dir/ClockDivideByN.v\n             obj_dir/ClockDivideByN.sv\n%Error: Exiting due to 1 error(s)\n"
module AppleIIePAL(
    input clk_14M,

    output reg clk_7M,
    output clk_3_58M,
    output reg clk_q3,
    output clk_phi_0,


    input clk_phi_1,
    input ramen_n,
    output reg pcas_n,
    output reg pras_n,

    input vid7,
    input gr,
    input eighty_vid_n,
    input entmg,

    output h0,
    output segb,
    output ldps_n,
    output vid7m
    );

    always @(posedge clk_14M)
    clk_7M <= ~clk_7M;

    ClockDivideByN #(
        .N(14)
    ) phi_0_divider(
        .clk_in(clk_14M),
        .reset(1'b0),
        .clk_out(clk_phi_0)
    );




    reg [3:0] q3_counter;
    always @(posedge clk_14M) begin
        if (q3_counter < 4'd4) clk_q3 <= 1'b1;
        else clk_q3 <= 1'b0;

        if (q3_counter >= 4'd6) q3_counter <= 0;
        else q3_counter <= q3_counter + 1;
    end



    reg pras_counter;
    always @(posedge clk_14M) begin
        if (~pras_n && ~clk_q3) begin
            if (~pras_counter) pras_counter <= 1'b1;
            else begin
                pras_counter <= 1'b0;
                pras_n <= 1'b1;
            end
        end
        else if (pras_n) begin
            if (~pras_counter) pras_counter <= 1'b1;
            else begin
                pras_counter <= 1'b0;
                pras_n <= 1'b0;
            end
        end
    end




    reg [1:0] pcas_counter;
    always @(posedge clk_14M) begin
        if (ramen_n) pcas_n <= 1'b1;
        else begin
            if (pras_n) begin
                pcas_counter <= 2'b0;
                pcas_n <= 1'b1;
            end
            else if (pcas_n) begin
                if (pcas_counter < 2'd2) pcas_counter <= pcas_counter + 1;
                else pcas_n <= 1'b0;
            end
        end
    end
endmodule
module AppleIIePAL(
    input clk_14M,

    output reg clk_7M,
    output clk_3_58M,
    output reg clk_q3,
    output clk_phi_0,


    input clk_phi_1,
    input ramen_n,
    output reg pcas_n,
    output reg pras_n,

    input vid7,
    input gr,
    input eighty_vid_n,
    input entmg,

    output h0,
    output segb,
    output ldps_n,
    output vid7m
    );


    always @(posedge clk_14M)
    clk_7M <= ~clk_7M;

    ClockDivideByN #(
        .N(14)
    ) phi_0_divider(
        .clk_in(clk_14M),
        .reset(1'b0),
        .clk_out(clk_phi_0)
    );




    reg [3:0] q3_counter;
    always @(posedge clk_14M) begin
        if (q3_counter < 4'd4) clk_q3 <= 1'b1;
        else clk_q3 <= 1'b0;

        if (q3_counter >= 4'd6) q3_counter <= 0;
        else q3_counter <= q3_counter + 1;
    end



    reg pras_counter;
    always @(posedge clk_14M) begin
        if (~pras_n && ~clk_q3) begin
            if (~pras_counter) pras_counter <= 1'b1;
            else begin
                pras_counter <= 1'b0;
                pras_n <= 1'b1;
            end
        end
        else if (pras_n) begin
            if (~pras_counter) pras_counter <= 1'b1;
            else begin
                pras_counter <= 1'b0;
                pras_n <= 1'b0;
            end
        end
    end




    reg [1:0] pcas_counter;
    always @(posedge clk_14M) begin
        if (ramen_n) pcas_n <= 1'b1;
        else begin
            if (pras_n) begin
                pcas_counter <= 2'b0;
                pcas_n <= 1'b1;
            end
            else if (pcas_n) begin
                if (pcas_counter < 2'd2) pcas_counter <= pcas_counter + 1;
                else pcas_n <= 1'b0;
            end
        end
    end
endmodule