data/full_repos/permissive/146618947/generate_tarea7/block_tester.v
 line:26: before: "("
1: b'%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:18: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("block.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:19: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #50 reset <= \'b1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:27: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:36: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:39: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:42: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:45: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:48: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:51: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:54: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:57: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:60: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:63: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/generate_tarea7/block_tester.v:91: Unsupported: Ignoring delay on this delayed statement.\n   always #40 clk <= ~clk;\n          ^\n%Error: Exiting due to 13 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module block_tester #(
                      parameter BUS_SIZE = 32,
                      parameter WORD_SIZE = 4,
                      parameter WORD_NUM = BUS_SIZE / WORD_SIZE
                      ) (
                     output reg                  clk,
                     output reg                  reset,
                     output reg [BUS_SIZE-1 : 0] bus_in,
                     input [BUS_SIZE-1 : 0]      bus_out_cond,
                     input [BUS_SIZE-1 : 0]      bus_out_est,
                     input [WORD_NUM-1 : 0]      word_bus_cond,
                     input [WORD_NUM-1 : 0]      word_bus_est,
                     input                       error_cond,
                     input                       error_est
                         );

   initial begin
      $dumpfile("block.vcd");
      $dumpvars;

      reset <= 'b0;
      bus_in <= 'b1;

      #50 reset <= 'b1;

      repeat (31) begin
         @(posedge clk);

         bus_in <= bus_in << 1;

      end



      repeat (2) begin
         @(posedge clk);
         bus_in <= 'hFAAABBB0;

         @(posedge clk);
         bus_in <= 'hFAAABBB1;

         @(posedge clk);
         bus_in <= 'hFAAABBB2;

         @(posedge clk);
         bus_in <= 'hAAAABBB3;

         @(posedge clk);
         bus_in <= 'hFAAABBB0;

         @(posedge clk);
         bus_in <= 'hFAAABBB9;

         @(posedge clk);
         bus_in <= 'hFAAABBB2;

         @(posedge clk);
         bus_in <= 'hFAAABBB3;

         @(posedge clk);
         bus_in <= 'hFAAABBB2;

         @(posedge clk);
         bus_in <= 'hFAAABBB3;

      end

      $finish;

   end

   always @ (posedge clk) begin
      if (reset) begin
         $display("Iniciando con las verificaciones en %t", $realtime);
         if (bus_out_est !== bus_out_cond) begin
            $display("Diferencia en el bus out");
         end

         if (word_bus_est !== word_bus_cond) begin
            $display("Diferencia en el bus de word");
         end

         if (error_est !== error_cond) begin
            $display("Diferencia en el bit de error");
         end
      end
   end

   initial clk <= 0;

   always #40 clk <= ~clk;

endmodule
module block_tester #(
                      parameter BUS_SIZE = 32,
                      parameter WORD_SIZE = 4,
                      parameter WORD_NUM = BUS_SIZE / WORD_SIZE
                      ) (
                     output reg                  clk,
                     output reg                  reset,
                     output reg [BUS_SIZE-1 : 0] bus_in,
                     input [BUS_SIZE-1 : 0]      bus_out_cond,
                     input [BUS_SIZE-1 : 0]      bus_out_est,
                     input [WORD_NUM-1 : 0]      word_bus_cond,
                     input [WORD_NUM-1 : 0]      word_bus_est,
                     input                       error_cond,
                     input                       error_est
                         );


   initial begin
      $dumpfile("block.vcd");
      $dumpvars;

      reset <= 'b0;
      bus_in <= 'b1;

      #50 reset <= 'b1;

      repeat (31) begin
         @(posedge clk);

         bus_in <= bus_in << 1;

      end



      repeat (2) begin
         @(posedge clk);
         bus_in <= 'hFAAABBB0;

         @(posedge clk);
         bus_in <= 'hFAAABBB1;

         @(posedge clk);
         bus_in <= 'hFAAABBB2;

         @(posedge clk);
         bus_in <= 'hAAAABBB3;

         @(posedge clk);
         bus_in <= 'hFAAABBB0;

         @(posedge clk);
         bus_in <= 'hFAAABBB9;

         @(posedge clk);
         bus_in <= 'hFAAABBB2;

         @(posedge clk);
         bus_in <= 'hFAAABBB3;

         @(posedge clk);
         bus_in <= 'hFAAABBB2;

         @(posedge clk);
         bus_in <= 'hFAAABBB3;

      end

      $finish;

   end

   always @ (posedge clk) begin
      if (reset) begin
         $display("Iniciando con las verificaciones en %t", $realtime);
         if (bus_out_est !== bus_out_cond) begin
            $display("Diferencia en el bus out");
         end

         if (word_bus_est !== word_bus_cond) begin
            $display("Diferencia en el bus de word");
         end

         if (error_est !== error_cond) begin
            $display("Diferencia en el bit de error");
         end
      end
   end

   initial clk <= 0;

   always #40 clk <= ~clk;

endmodule