data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v
1: b'%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:3: Cannot find include file: ../../define/global_def.v\n`include "../../define/global_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v.v\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v.sv\n             ../../define/global_def.v\n             ../../define/global_def.v.v\n             ../../define/global_def.v.sv\n             obj_dir/../../define/global_def.v\n             obj_dir/../../define/global_def.v.v\n             obj_dir/../../define/global_def.v.sv\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:4: Cannot find include file: ../../define/op_def.v\n`include "../../define/op_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:5: Cannot find include file: ../../define/funct_def.v\n`include "../../define/funct_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:6: Cannot find include file: ../../define/segpos_def.v\n`include "../../define/segpos_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:15: Define or directive not defined: \'`INST_BUS\'\n    input   wire[`INST_BUS]     inst,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`INST_BUS]     inst,\n                          ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:18: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     reg_val_mux_data_1,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:19: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     reg_val_mux_data_2,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`REG_ADDR_BUS] reg_addr_1,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:23: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  wire[`REG_ADDR_BUS] reg_addr_1,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:25: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`REG_ADDR_BUS] reg_addr_2,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:25: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  wire[`REG_ADDR_BUS] reg_addr_2,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:28: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     operand_1,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:29: Define or directive not defined: \'`DATA_BUS\'\n    output  reg [`DATA_BUS]     operand_2,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`REG_ADDR_BUS] write_reg_addr\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:31: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  wire[`REG_ADDR_BUS] write_reg_addr\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:34: Define or directive not defined: \'`INST_OP_BUS\'\n    wire[`INST_OP_BUS]  inst_op     = inst[`SEG_OPCODE];\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`INST_OP_BUS]  inst_op     = inst[`SEG_OPCODE];\n                     ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:34: Define or directive not defined: \'`SEG_OPCODE\'\n    wire[`INST_OP_BUS]  inst_op     = inst[`SEG_OPCODE];\n                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:35: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] inst_rs     = inst[`SEG_RS];\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] inst_rs     = inst[`SEG_RS];\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:35: Define or directive not defined: \'`SEG_RS\'\n    wire[`REG_ADDR_BUS] inst_rs     = inst[`SEG_RS];\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:36: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] inst_rt     = inst[`SEG_RT];\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] inst_rt     = inst[`SEG_RT];\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:36: Define or directive not defined: \'`SEG_RT\'\n    wire[`REG_ADDR_BUS] inst_rt     = inst[`SEG_RT];\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:37: Define or directive not defined: \'`FUNCT_BUS\'\n    wire[`FUNCT_BUS]    inst_funct  = inst[`SEG_FUNCT];\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`FUNCT_BUS]    inst_funct  = inst[`SEG_FUNCT];\n                   ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:37: Define or directive not defined: \'`SEG_FUNCT\'\n    wire[`FUNCT_BUS]    inst_funct  = inst[`SEG_FUNCT];\n                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:38: Define or directive not defined: \'`IMM_BUS\'\n    wire[`IMM_BUS]      inst_imm    = inst[`SEG_IMM];\n         ^~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`IMM_BUS]      inst_imm    = inst[`SEG_IMM];\n                 ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:38: Define or directive not defined: \'`SEG_IMM\'\n    wire[`IMM_BUS]      inst_imm    = inst[`SEG_IMM];\n                                           ^~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:40: Define or directive not defined: \'`DATA_BUS\'\n    wire[`DATA_BUS]     zero_extended_imm       = {16\'b0, inst_imm};\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`DATA_BUS]     zero_extended_imm       = {16\'b0, inst_imm};\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:41: Define or directive not defined: \'`DATA_BUS\'\n    wire[`DATA_BUS]     zero_extended_imm_hi    = {inst_imm, 16\'b0};\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`DATA_BUS]     zero_extended_imm_hi    = {inst_imm, 16\'b0};\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:42: Define or directive not defined: \'`DATA_BUS\'\n    wire[`DATA_BUS]     sign_extended_imm       = {{16{inst_imm[15]}}, inst_imm};\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`DATA_BUS]     sign_extended_imm       = {{16{inst_imm[15]}}, inst_imm};\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:44: Define or directive not defined: \'`RST_ENABLE\'\n    assign  operand_1   = (rst == `RST_ENABLE) ? `ZERO_WORD : reg_val_mux_data_1;\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:44: Define or directive not defined: \'`ZERO_WORD\'\n    assign  operand_1   = (rst == `RST_ENABLE) ? `ZERO_WORD : reg_val_mux_data_1;\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:50: Define or directive not defined: \'`OP_ANDI\'\n            `OP_ANDI,`OP_ORI,`OP_XORI,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:50: Define or directive not defined: \'`OP_ORI\'\n            `OP_ANDI,`OP_ORI,`OP_XORI,\n                     ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:50: Define or directive not defined: \'`OP_XORI\'\n            `OP_ANDI,`OP_ORI,`OP_XORI,\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:51: Define or directive not defined: \'`OP_ADDI\'\n            `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:51: Define or directive not defined: \'`OP_ADDIU\'\n            `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:51: Define or directive not defined: \'`OP_SLTI\'\n            `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,\n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:51: Define or directive not defined: \'`OP_SLTIU\'\n            `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,\n                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:52: Define or directive not defined: \'`OP_LUI\'\n            `OP_LUI:    begin\n            ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:53: Define or directive not defined: \'`TRUE\'\n                inst_immediate  <= `TRUE;\n                                   ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:57: Define or directive not defined: \'`FALSE\'\n                inst_immediate  <= `FALSE;\n                                   ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_IMM.v:64: Define or directive not defined: \'`RST_ENABLE\'\n    assign  reg_read_en_1   = (rst == `RST_ENABLE) ? `READ_DISABLE :\n                                      ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module  ID_IMM(
    input   wire                rst,


    output  reg                 inst_immediate,


    input   wire[`INST_BUS]     inst,


    input   wire[`DATA_BUS]     reg_val_mux_data_1,
    input   wire[`DATA_BUS]     reg_val_mux_data_2,


    output  wire                reg_read_en_1,
    output  wire[`REG_ADDR_BUS] reg_addr_1,
    output  wire                reg_read_en_2,
    output  wire[`REG_ADDR_BUS] reg_addr_2,


    output  wire[`DATA_BUS]     operand_1,
    output  reg [`DATA_BUS]     operand_2,
    output  wire                write_reg_en,
    output  wire[`REG_ADDR_BUS] write_reg_addr
);

    wire[`INST_OP_BUS]  inst_op     = inst[`SEG_OPCODE];
    wire[`REG_ADDR_BUS] inst_rs     = inst[`SEG_RS];
    wire[`REG_ADDR_BUS] inst_rt     = inst[`SEG_RT];
    wire[`FUNCT_BUS]    inst_funct  = inst[`SEG_FUNCT];
    wire[`IMM_BUS]      inst_imm    = inst[`SEG_IMM];

    wire[`DATA_BUS]     zero_extended_imm       = {16'b0, inst_imm};
    wire[`DATA_BUS]     zero_extended_imm_hi    = {inst_imm, 16'b0};
    wire[`DATA_BUS]     sign_extended_imm       = {{16{inst_imm[15]}}, inst_imm};
    
    assign  operand_1   = (rst == `RST_ENABLE) ? `ZERO_WORD : reg_val_mux_data_1;


    always @ (*)    begin
        case (inst_op)

            `OP_ANDI,`OP_ORI,`OP_XORI,
            `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,
            `OP_LUI:    begin
                inst_immediate  <= `TRUE;
            end

            default:    begin
                inst_immediate  <= `FALSE;
            end
            
        endcase
    end


    assign  reg_read_en_1   = (rst == `RST_ENABLE) ? `READ_DISABLE :
                              (inst_immediate == `TRUE) ? `READ_ENABLE : `READ_DISABLE;
    assign  reg_addr_1      = (rst == `RST_ENABLE) ? `ZERO_REG_ADDR :
                              (inst_immediate == `TRUE) ? inst_rs : `ZERO_REG_ADDR;
    assign  reg_read_en_2   = `READ_DISABLE;
    assign  reg_addr_2      = `ZERO_REG_ADDR;


    always @ (*)    begin
        if (rst == `READ_ENABLE)    begin
            operand_2   <= `ZERO_WORD;
        end else    begin
            case (inst_op)
                `OP_ORI, `OP_ANDI,  `OP_XORI:   
                            operand_2   <= zero_extended_imm;
                `OP_LUI:    operand_2   <= zero_extended_imm_hi;
                `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU:   
                            operand_2   <= sign_extended_imm;
                default:    operand_2   <= `ZERO_WORD;
            endcase
        end
    end


    assign  write_reg_en    = (rst == `RST_ENABLE) ? `WRITE_DISABLE :
                              (inst_immediate == `TRUE) ? `WRITE_ENABLE : `WRITE_DISABLE;
    assign  write_reg_addr  = (rst == `RST_ENABLE) ? `ZERO_REG_ADDR :
                              (inst_immediate == `TRUE) ? inst_rt : `ZERO_REG_ADDR;

endmodule
module  ID_IMM(
    input   wire                rst,


    output  reg                 inst_immediate,


    input   wire[`INST_BUS]     inst,


    input   wire[`DATA_BUS]     reg_val_mux_data_1,
    input   wire[`DATA_BUS]     reg_val_mux_data_2,


    output  wire                reg_read_en_1,
    output  wire[`REG_ADDR_BUS] reg_addr_1,
    output  wire                reg_read_en_2,
    output  wire[`REG_ADDR_BUS] reg_addr_2,


    output  wire[`DATA_BUS]     operand_1,
    output  reg [`DATA_BUS]     operand_2,
    output  wire                write_reg_en,
    output  wire[`REG_ADDR_BUS] write_reg_addr
);


    wire[`INST_OP_BUS]  inst_op     = inst[`SEG_OPCODE];
    wire[`REG_ADDR_BUS] inst_rs     = inst[`SEG_RS];
    wire[`REG_ADDR_BUS] inst_rt     = inst[`SEG_RT];
    wire[`FUNCT_BUS]    inst_funct  = inst[`SEG_FUNCT];
    wire[`IMM_BUS]      inst_imm    = inst[`SEG_IMM];

    wire[`DATA_BUS]     zero_extended_imm       = {16'b0, inst_imm};
    wire[`DATA_BUS]     zero_extended_imm_hi    = {inst_imm, 16'b0};
    wire[`DATA_BUS]     sign_extended_imm       = {{16{inst_imm[15]}}, inst_imm};
    
    assign  operand_1   = (rst == `RST_ENABLE) ? `ZERO_WORD : reg_val_mux_data_1;


    always @ (*)    begin
        case (inst_op)

            `OP_ANDI,`OP_ORI,`OP_XORI,
            `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,
            `OP_LUI:    begin
                inst_immediate  <= `TRUE;
            end

            default:    begin
                inst_immediate  <= `FALSE;
            end
            
        endcase
    end


    assign  reg_read_en_1   = (rst == `RST_ENABLE) ? `READ_DISABLE :
                              (inst_immediate == `TRUE) ? `READ_ENABLE : `READ_DISABLE;
    assign  reg_addr_1      = (rst == `RST_ENABLE) ? `ZERO_REG_ADDR :
                              (inst_immediate == `TRUE) ? inst_rs : `ZERO_REG_ADDR;
    assign  reg_read_en_2   = `READ_DISABLE;
    assign  reg_addr_2      = `ZERO_REG_ADDR;


    always @ (*)    begin
        if (rst == `READ_ENABLE)    begin
            operand_2   <= `ZERO_WORD;
        end else    begin
            case (inst_op)
                `OP_ORI, `OP_ANDI,  `OP_XORI:   
                            operand_2   <= zero_extended_imm;
                `OP_LUI:    operand_2   <= zero_extended_imm_hi;
                `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU:   
                            operand_2   <= sign_extended_imm;
                default:    operand_2   <= `ZERO_WORD;
            endcase
        end
    end


    assign  write_reg_en    = (rst == `RST_ENABLE) ? `WRITE_DISABLE :
                              (inst_immediate == `TRUE) ? `WRITE_ENABLE : `WRITE_DISABLE;
    assign  write_reg_addr  = (rst == `RST_ENABLE) ? `ZERO_REG_ADDR :
                              (inst_immediate == `TRUE) ? inst_rt : `ZERO_REG_ADDR;

endmodule