data/full_repos/permissive/179844171/rtl/mirfak_alu.v
 line:17: before: "parameter"
1: b'%Error: data/full_repos/permissive/179844171/rtl/mirfak_alu.v:8: Cannot find include file: mirfak_defines.v\n`include "mirfak_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179844171/rtl,data/full_repos/permissive/179844171/mirfak_defines.v\n             data/full_repos/permissive/179844171/rtl,data/full_repos/permissive/179844171/mirfak_defines.v.v\n             data/full_repos/permissive/179844171/rtl,data/full_repos/permissive/179844171/mirfak_defines.v.sv\n             mirfak_defines.v\n             mirfak_defines.v.v\n             mirfak_defines.v.sv\n             obj_dir/mirfak_defines.v\n             obj_dir/mirfak_defines.v.v\n             obj_dir/mirfak_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module mirfak_alu (

                   input wire [31:0] operand_a_i,
                   input wire [31:0] operand_b_i,
                   output reg [31:0] result_o,

                   input wire        adder_op_i,
                   input wire [1:0]  logic_op_i,
                   input wire [1:0]  shift_op_i,
                   input wire        compare_op_i,
                   input wire [1:0]  alu_op_i
                   );

    reg [31:0] adder_o, logic_o, shift_o, compare_o;

    always @(*) begin

        case (adder_op_i)
            ADDER_OP_ADD: adder_o = operand_a_i + operand_b_i;
            ADDER_OP_SUB: adder_o = operand_a_i - operand_b_i;
        endcase

        case (logic_op_i)
            LOGIC_OP_AND: logic_o = operand_a_i & operand_b_i;
            LOGIC_OP_OR:  logic_o = operand_a_i | operand_b_i;
            LOGIC_OP_XOR: logic_o = operand_a_i ^ operand_b_i;
            default:      logic_o = 32'bx;
        endcase

        case (shift_op_i)
            SHIFT_OP_LL: shift_o = operand_a_i << operand_b_i[4:0];
            SHIFT_OP_LR: shift_o = operand_a_i >> operand_b_i[4:0];
            SHIFT_OP_AR: shift_o = $signed(operand_a_i) >>> operand_b_i[4:0];
            default:     shift_o = 32'bx;
        endcase

        case (compare_op_i)
            COMPARE_LT:  compare_o = {31'b0, operand_a_i < operand_b_i};
            COMPARE_LTU: compare_o = {31'b0, $signed(operand_a_i) < $signed(operand_b_i)};
        endcase
    end
    always @(*) begin

        case (alu_op_i)
            ALU_OP_ADDER:   result_o = adder_o;
            ALU_OP_LOGIC:   result_o = logic_o;
            ALU_OP_SHIFT:   result_o = shift_o;
            ALU_OP_COMPARE: result_o = compare_o;
        endcase
    end

endmodule
module mirfak_alu (

                   input wire [31:0] operand_a_i,
                   input wire [31:0] operand_b_i,
                   output reg [31:0] result_o,

                   input wire        adder_op_i,
                   input wire [1:0]  logic_op_i,
                   input wire [1:0]  shift_op_i,
                   input wire        compare_op_i,
                   input wire [1:0]  alu_op_i
                   );


    reg [31:0] adder_o, logic_o, shift_o, compare_o;

    always @(*) begin

        case (adder_op_i)
            ADDER_OP_ADD: adder_o = operand_a_i + operand_b_i;
            ADDER_OP_SUB: adder_o = operand_a_i - operand_b_i;
        endcase

        case (logic_op_i)
            LOGIC_OP_AND: logic_o = operand_a_i & operand_b_i;
            LOGIC_OP_OR:  logic_o = operand_a_i | operand_b_i;
            LOGIC_OP_XOR: logic_o = operand_a_i ^ operand_b_i;
            default:      logic_o = 32'bx;
        endcase

        case (shift_op_i)
            SHIFT_OP_LL: shift_o = operand_a_i << operand_b_i[4:0];
            SHIFT_OP_LR: shift_o = operand_a_i >> operand_b_i[4:0];
            SHIFT_OP_AR: shift_o = $signed(operand_a_i) >>> operand_b_i[4:0];
            default:     shift_o = 32'bx;
        endcase

        case (compare_op_i)
            COMPARE_LT:  compare_o = {31'b0, operand_a_i < operand_b_i};
            COMPARE_LTU: compare_o = {31'b0, $signed(operand_a_i) < $signed(operand_b_i)};
        endcase
    end
    always @(*) begin

        case (alu_op_i)
            ALU_OP_ADDER:   result_o = adder_o;
            ALU_OP_LOGIC:   result_o = logic_o;
            ALU_OP_SHIFT:   result_o = shift_o;
            ALU_OP_COMPARE: result_o = compare_o;
        endcase
    end

endmodule