data/full_repos/permissive/143278/ivltests/br955.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br955.v:92: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br955.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br955.v:89: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'lp\' generates 32 bits.\n                                                                     : ... In instance top\n      sel = lp;\n          ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  parameter sel_wid = 3;
  parameter num_inputs = 2**sel_wid;

  reg [num_inputs-1:0] in;
  reg [sel_wid-1:0] sel;
  wire out;
  integer lp;
  reg pass;

  mux_n_to_1
    #(
      .sel_w(sel_wid),
      .n_inputs(num_inputs)
     )
     dut
     (
       .inputs_i(in),
       .sel_i(sel),
       .output_o(out)
     );

  initial begin
    pass = 1'b1;

    for (lp = 0; lp < num_inputs; lp = lp + 1) begin
      sel = lp;
      in = 2**lp;
      $display("Checking input %0d;", sel);
      #1;
      if (out !== 1'b1) begin
        $display("  Failed input high (%b), got %b", in, out);
        pass = 1'b0;
      end
      in = ~in;
      #1;
      if (out !== 1'b0) begin
        $display("  Failed input low (%b), got %b", in, out);
        pass = 1'b0;
      end
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  parameter sel_wid = 3;
  parameter num_inputs = 2**sel_wid;

  reg [num_inputs-1:0] in;
  reg [sel_wid-1:0] sel;
  wire out;
  integer lp;
  reg pass;

  mux_n_to_1
    #(
      .sel_w(sel_wid),
      .n_inputs(num_inputs)
     )
     dut
     (
       .inputs_i(in),
       .sel_i(sel),
       .output_o(out)
     );

  initial begin
    pass = 1'b1;

    for (lp = 0; lp < num_inputs; lp = lp + 1) begin
      sel = lp;
      in = 2**lp;
      $display("Checking input %0d;", sel);
      #1;
      if (out !== 1'b1) begin
        $display("  Failed input high (%b), got %b", in, out);
        pass = 1'b0;
      end
      in = ~in;
      #1;
      if (out !== 1'b0) begin
        $display("  Failed input low (%b), got %b", in, out);
        pass = 1'b0;
      end
    end

    if (pass) $display("PASSED");
  end
endmodule