data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:13: Little bit endian vector: MSB < LSB of bit range: 1:2\ninput  [1:2] D;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:14: Little bit endian vector: MSB < LSB of bit range: 1:2\ninput  [1:2] Clk;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:15: Little bit endian vector: MSB < LSB of bit range: 1:2\noutput [1:2] Q;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:16: Little bit endian vector: MSB < LSB of bit range: 1:2\ninput  [1:2] SD;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:17: Little bit endian vector: MSB < LSB of bit range: 1:2\ninput  [1:2] RD;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:18: Little bit endian vector: MSB < LSB of bit range: 1:2\noutput [1:2] QN;\n       ^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:25: Cannot find file containing module: \'OUTBUF\'\n    OUTBUF \\Q_pad[1]  (.D(\\Q_1_c[1] ), .PAD(Q[1]));\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis,data/full_repos/permissive/165160692/OUTBUF\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis,data/full_repos/permissive/165160692/OUTBUF.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis,data/full_repos/permissive/165160692/OUTBUF.sv\n             OUTBUF\n             OUTBUF.v\n             OUTBUF.sv\n             obj_dir/OUTBUF\n             obj_dir/OUTBUF.v\n             obj_dir/OUTBUF.sv\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:26: Cannot find file containing module: \'INV\'\n    INV \\QN_pad_RNO[1]  (.A(\\Q_1_c[1] ), .Y(\\Q_1_c_i[1] ));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:27: Cannot find file containing module: \'OUTBUF\'\n    OUTBUF \\Q_pad[2]  (.D(\\Q_1_c[2] ), .PAD(Q[2]));\n    ^~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:28: Cannot find file containing module: \'INBUF\'\n    INBUF \\SD_pad[1]  (.PAD(SD[1]), .Y(\\SD_c[1] ));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:29: Cannot find file containing module: \'GND\'\n    GND GND_i_0 (.Y(GND_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:30: Cannot find file containing module: \'INBUF\'\n    INBUF \\D_pad[1]  (.PAD(D[1]), .Y(\\D_c[1] ));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:31: Cannot find file containing module: \'VCC\'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:32: Cannot find file containing module: \'DFN1P1C1\'\n    DFN1P1C1 \\Q_1[1]  (.D(\\D_c[1] ), .CLK(\\Clk_c[1] ), .PRE(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:34: Cannot find file containing module: \'NOR2A\'\n    NOR2A \\Q_1_RNO[2]  (.A(\\SD_c[2] ), .B(\\RD_c[2] ), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:36: Cannot find file containing module: \'INV\'\n    INV \\Q_1_RNO_0[2]  (.A(\\SD_c[2] ), .Y(\\SD_c_i[2] ));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:37: Cannot find file containing module: \'GND\'\n    GND GND_i (.Y(GND));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:38: Cannot find file containing module: \'INBUF\'\n    INBUF \\Clk_pad[2]  (.PAD(Clk[2]), .Y(\\Clk_c[2] ));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:39: Cannot find file containing module: \'INBUF\'\n    INBUF \\Clk_pad[1]  (.PAD(Clk[1]), .Y(\\Clk_c[1] ));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:40: Cannot find file containing module: \'INBUF\'\n    INBUF \\RD_pad[2]  (.PAD(RD[2]), .Y(\\RD_c[2] ));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:41: Cannot find file containing module: \'INV\'\n    INV \\Q_1_RNO_0[1]  (.A(\\SD_c[1] ), .Y(\\SD_c_i[1] ));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:42: Cannot find file containing module: \'VCC\'\n    VCC VCC_i_0 (.Y(VCC_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:43: Cannot find file containing module: \'INBUF\'\n    INBUF \\D_pad[2]  (.PAD(D[2]), .Y(\\D_c[2] ));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:44: Cannot find file containing module: \'OUTBUF\'\n    OUTBUF \\QN_pad[1]  (.D(\\Q_1_c_i[1] ), .PAD(QN[1]));\n    ^~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:45: Cannot find file containing module: \'NOR2A\'\n    NOR2A \\Q_1_RNO[1]  (.A(\\SD_c[1] ), .B(\\RD_c[1] ), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:47: Cannot find file containing module: \'INV\'\n    INV \\QN_pad_RNO[2]  (.A(\\Q_1_c[2] ), .Y(\\Q_1_c_i[2] ));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:48: Cannot find file containing module: \'OUTBUF\'\n    OUTBUF \\QN_pad[2]  (.D(\\Q_1_c_i[2] ), .PAD(QN[2]));\n    ^~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:49: Cannot find file containing module: \'INBUF\'\n    INBUF \\SD_pad[2]  (.PAD(SD[2]), .Y(\\SD_c[2] ));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:50: Cannot find file containing module: \'INBUF\'\n    INBUF \\RD_pad[1]  (.PAD(RD[1]), .Y(\\RD_c[1] ));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/synthesis/HC74.v:51: Cannot find file containing module: \'DFN1P1C1\'\n    DFN1P1C1 \\Q_1[2]  (.D(\\D_c[2] ), .CLK(\\Clk_c[2] ), .PRE(\n    ^~~~~~~~\n%Error: Exiting due to 24 error(s), 6 warning(s)\n'
module HC74(
       D,
       Clk,
       Q,
       SD,
       RD,
       QN
    );
input  [1:2] D;
input  [1:2] Clk;
output [1:2] Q;
input  [1:2] SD;
input  [1:2] RD;
output [1:2] QN;

    wire GND, VCC, \D_c[2] , \D_c[1] , \Clk_c[2] , \Clk_c[1] , 
        \Q_1_c[2] , \Q_1_c[1] , \SD_c[2] , \SD_c[1] , \RD_c[2] , 
        \RD_c[1] , \Q_1_RNO[1]_net_1 , \Q_1_RNO[2]_net_1 , \SD_c_i[1] , 
        \SD_c_i[2] , \Q_1_c_i[1] , \Q_1_c_i[2] , GND_0, VCC_0;
    
    OUTBUF \Q_pad[1]  (.D(\Q_1_c[1] ), .PAD(Q[1]));
    INV \QN_pad_RNO[1]  (.A(\Q_1_c[1] ), .Y(\Q_1_c_i[1] ));
    OUTBUF \Q_pad[2]  (.D(\Q_1_c[2] ), .PAD(Q[2]));
    INBUF \SD_pad[1]  (.PAD(SD[1]), .Y(\SD_c[1] ));
    GND GND_i_0 (.Y(GND_0));
    INBUF \D_pad[1]  (.PAD(D[1]), .Y(\D_c[1] ));
    VCC VCC_i (.Y(VCC));
    DFN1P1C1 \Q_1[1]  (.D(\D_c[1] ), .CLK(\Clk_c[1] ), .PRE(
        \SD_c_i[1] ), .CLR(\Q_1_RNO[1]_net_1 ), .Q(\Q_1_c[1] ));
    NOR2A \Q_1_RNO[2]  (.A(\SD_c[2] ), .B(\RD_c[2] ), .Y(
        \Q_1_RNO[2]_net_1 ));
    INV \Q_1_RNO_0[2]  (.A(\SD_c[2] ), .Y(\SD_c_i[2] ));
    GND GND_i (.Y(GND));
    INBUF \Clk_pad[2]  (.PAD(Clk[2]), .Y(\Clk_c[2] ));
    INBUF \Clk_pad[1]  (.PAD(Clk[1]), .Y(\Clk_c[1] ));
    INBUF \RD_pad[2]  (.PAD(RD[2]), .Y(\RD_c[2] ));
    INV \Q_1_RNO_0[1]  (.A(\SD_c[1] ), .Y(\SD_c_i[1] ));
    VCC VCC_i_0 (.Y(VCC_0));
    INBUF \D_pad[2]  (.PAD(D[2]), .Y(\D_c[2] ));
    OUTBUF \QN_pad[1]  (.D(\Q_1_c_i[1] ), .PAD(QN[1]));
    NOR2A \Q_1_RNO[1]  (.A(\SD_c[1] ), .B(\RD_c[1] ), .Y(
        \Q_1_RNO[1]_net_1 ));
    INV \QN_pad_RNO[2]  (.A(\Q_1_c[2] ), .Y(\Q_1_c_i[2] ));
    OUTBUF \QN_pad[2]  (.D(\Q_1_c_i[2] ), .PAD(QN[2]));
    INBUF \SD_pad[2]  (.PAD(SD[2]), .Y(\SD_c[2] ));
    INBUF \RD_pad[1]  (.PAD(RD[1]), .Y(\RD_c[1] ));
    DFN1P1C1 \Q_1[2]  (.D(\D_c[2] ), .CLK(\Clk_c[2] ), .PRE(
        \SD_c_i[2] ), .CLR(\Q_1_RNO[2]_net_1 ), .Q(\Q_1_c[2] ));
    
endmodule
module HC74(
       D,
       Clk,
       Q,
       SD,
       RD,
       QN
    );

input  [1:2] D;
input  [1:2] Clk;
output [1:2] Q;
input  [1:2] SD;
input  [1:2] RD;
output [1:2] QN;

    wire GND, VCC, \D_c[2] , \D_c[1] , \Clk_c[2] , \Clk_c[1] , 
        \Q_1_c[2] , \Q_1_c[1] , \SD_c[2] , \SD_c[1] , \RD_c[2] , 
        \RD_c[1] , \Q_1_RNO[1]_net_1 , \Q_1_RNO[2]_net_1 , \SD_c_i[1] , 
        \SD_c_i[2] , \Q_1_c_i[1] , \Q_1_c_i[2] , GND_0, VCC_0;
    
    OUTBUF \Q_pad[1]  (.D(\Q_1_c[1] ), .PAD(Q[1]));
    INV \QN_pad_RNO[1]  (.A(\Q_1_c[1] ), .Y(\Q_1_c_i[1] ));
    OUTBUF \Q_pad[2]  (.D(\Q_1_c[2] ), .PAD(Q[2]));
    INBUF \SD_pad[1]  (.PAD(SD[1]), .Y(\SD_c[1] ));
    GND GND_i_0 (.Y(GND_0));
    INBUF \D_pad[1]  (.PAD(D[1]), .Y(\D_c[1] ));
    VCC VCC_i (.Y(VCC));
    DFN1P1C1 \Q_1[1]  (.D(\D_c[1] ), .CLK(\Clk_c[1] ), .PRE(
        \SD_c_i[1] ), .CLR(\Q_1_RNO[1]_net_1 ), .Q(\Q_1_c[1] ));
    NOR2A \Q_1_RNO[2]  (.A(\SD_c[2] ), .B(\RD_c[2] ), .Y(
        \Q_1_RNO[2]_net_1 ));
    INV \Q_1_RNO_0[2]  (.A(\SD_c[2] ), .Y(\SD_c_i[2] ));
    GND GND_i (.Y(GND));
    INBUF \Clk_pad[2]  (.PAD(Clk[2]), .Y(\Clk_c[2] ));
    INBUF \Clk_pad[1]  (.PAD(Clk[1]), .Y(\Clk_c[1] ));
    INBUF \RD_pad[2]  (.PAD(RD[2]), .Y(\RD_c[2] ));
    INV \Q_1_RNO_0[1]  (.A(\SD_c[1] ), .Y(\SD_c_i[1] ));
    VCC VCC_i_0 (.Y(VCC_0));
    INBUF \D_pad[2]  (.PAD(D[2]), .Y(\D_c[2] ));
    OUTBUF \QN_pad[1]  (.D(\Q_1_c_i[1] ), .PAD(QN[1]));
    NOR2A \Q_1_RNO[1]  (.A(\SD_c[1] ), .B(\RD_c[1] ), .Y(
        \Q_1_RNO[1]_net_1 ));
    INV \QN_pad_RNO[2]  (.A(\Q_1_c[2] ), .Y(\Q_1_c_i[2] ));
    OUTBUF \QN_pad[2]  (.D(\Q_1_c_i[2] ), .PAD(QN[2]));
    INBUF \SD_pad[2]  (.PAD(SD[2]), .Y(\SD_c[2] ));
    INBUF \RD_pad[1]  (.PAD(RD[1]), .Y(\RD_c[1] ));
    DFN1P1C1 \Q_1[2]  (.D(\D_c[2] ), .CLK(\Clk_c[2] ), .PRE(
        \SD_c_i[2] ), .CLR(\Q_1_RNO[2]_net_1 ), .Q(\Q_1_c[2] ));
    
endmodule