data/full_repos/permissive/210844779/lab7/7.2.1/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab7/7.2.1/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210844779/lab7/7.2.1/tb.v:6: Cannot find file containing module: \'nand_3\'\n  nand_3 u0(a,b,c,y);\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab7/7.2.1,data/full_repos/permissive/210844779/nand_3\n             data/full_repos/permissive/210844779/lab7/7.2.1,data/full_repos/permissive/210844779/nand_3.v\n             data/full_repos/permissive/210844779/lab7/7.2.1,data/full_repos/permissive/210844779/nand_3.sv\n             nand_3\n             nand_3.v\n             nand_3.sv\n             obj_dir/nand_3\n             obj_dir/nand_3.v\n             obj_dir/nand_3.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab7/7.2.1/tb.v:10: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\n    a=$random;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab7/7.2.1/tb.v:11: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\n    b=$random;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab7/7.2.1/tb.v:12: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\n    c=$random;\n     ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  
  reg a,b,c;
  wire y;
  
  nand_3 u0(a,b,c,y);
  
  always
  begin
    a=$random;
    b=$random;
    c=$random;
    #10;
  end
endmodule
module tb();

  
  reg a,b,c;
  wire y;
  
  nand_3 u0(a,b,c,y);
  
  always
  begin
    a=$random;
    b=$random;
    c=$random;
    #10;
  end
endmodule