data/full_repos/permissive/120024308/src/cpu/alu.v
 line:51: before: ":"
1: b"%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:51: Define or directive not defined: '`ADDI'\n   `ADDI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:51: syntax error, unexpected ':', expecting endcase\n   `ADDI:\n        ^\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:57: Define or directive not defined: '`ADD'\n   `ADD:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:58: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:63: Define or directive not defined: '`SUBI'\n   `SUBI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:64: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:69: Define or directive not defined: '`SUB'\n   `SUB:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:70: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:75: Define or directive not defined: '`AND'\n   `AND:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:76: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:81: Define or directive not defined: '`OR'\n   `OR:\n   ^~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:82: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:87: Define or directive not defined: '`XOR'\n   `XOR:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:88: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:93: Define or directive not defined: '`NOR'\n   `NOR:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:94: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:99: Define or directive not defined: '`SLT'\n   `SLT:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:100: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:109: Define or directive not defined: '`SLTI'\n   `SLTI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:119: Define or directive not defined: '`ANDI'\n   `ANDI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:125: Define or directive not defined: '`ORI'\n   `ORI:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:131: Define or directive not defined: '`XORI'\n   `XORI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:137: Define or directive not defined: '`SLL'\n   `SLL:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:143: Define or directive not defined: '`SRL'\n   `SRL:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:149: Define or directive not defined: '`MULT'\n   `MULT:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:154: Define or directive not defined: '`MFHI'\n   `MFHI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:160: Define or directive not defined: '`MTHI'\n   `MTHI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:165: Define or directive not defined: '`MFLO'\n   `MFLO:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:171: Define or directive not defined: '`MTLO'\n   `MTLO:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:176: Define or directive not defined: '`DIV'\n   `DIV:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:183: Define or directive not defined: '`BLTZ'\n   `BLTZ:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:192: Define or directive not defined: '`BGEZ'\n   `BGEZ:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:201: Define or directive not defined: '`BLTZAL'\n   `BLTZAL:\n   ^~~~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:210: Define or directive not defined: '`BGEZAL'\n   `BGEZAL:\n   ^~~~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:219: Define or directive not defined: '`BEQ'\n   `BEQ:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:228: Define or directive not defined: '`BNE'\n   `BNE:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:237: Define or directive not defined: '`BLEZ'\n   `BLEZ:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:246: Define or directive not defined: '`BGTZ'\n   `BGTZ:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:255: Define or directive not defined: '`LED'\n   `LED:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/alu.v:259: Define or directive not defined: '`LEDI'\n   `LEDI:\n   ^~~~~\n%Error: Cannot continue\n"
module Alu # (parameter SIZE=32, parameter OP_SIZE=6, parameter INM_SIZE=16)
   (
    input wire [OP_SIZE-1:0]  operation,
    input wire [SIZE-1:0]     operand0,
    input wire [SIZE-1:0]     operand1,
    input wire [SIZE-1:0]     operand2,
    input wire [INM_SIZE-1:0] inmediate,
    output reg [SIZE-1:0]     result,
    output reg 		      write_enable,
    output reg 		      branch_taken
    );

   reg [2*SIZE-1:0] 	      mult_result;

   always @ ( * )
     begin
	result = 0;
	branch_taken = 0;
	mult_result = mult_result;
	write_enable = 0;

	case (operation)

	  `ADDI:
	    begin
	       result = operand1+inmediate;
	       write_enable = 1;
	    end

	  `ADD:
	    begin
	       result = operand1 + operand0;
	       write_enable = 1;
	    end

	  `SUBI:
	    begin
	       result = operand1-inmediate;
	       write_enable = 1;
	    end

	  `SUB:
	    begin
	       result = operand1 - operand0;
	       write_enable = 1;
	    end

	  `AND:
	    begin
	       result = operand1 & operand0;
	       write_enable = 1;
	    end

	  `OR:
	    begin
	       result = operand1 | operand0;
	       write_enable = 1;
	    end

	  `XOR:
	    begin
	       result = operand1 ^ operand0;
	       write_enable = 1;
	    end

	  `NOR:
	    begin
	       result = ~(operand1|operand0);
	       write_enable = 1;
	    end

	  `SLT:
	    begin
	       if (operand1 < operand0) begin
		  result = 1;
	       end else begin
		  result = 0;
	       end
	       write_enable = 1;
	    end

	  `SLTI:
	    begin
	       if (operand1 < inmediate) begin
		  result = 1;
	       end else begin
		  result = 0;
	       end
	       write_enable = 1;
	    end

	  `ANDI:
	    begin
	       result = operand1 & inmediate;
	       write_enable = 1;
	    end

	  `ORI:
	    begin
	       result = operand1 | inmediate;
	       write_enable = 1;
	    end

	  `XORI:
	    begin
	       result = operand1 ^ inmediate;
	       write_enable = 1;
	    end

	  `SLL:
	    begin
	       result = operand1 << inmediate[15:10];
	       write_enable = 1;
	    end

	  `SRL:
	    begin
	       result = operand1 >> inmediate[15:10];
	       write_enable = 1;
	    end

	  `MULT:
	    begin
	       mult_result = operand1*operand0;
	    end

	  `MFHI:
	    begin
	       result = mult_result[63:32];
	       write_enable = 1;
	    end

	  `MTHI:
	    begin
	       mult_result[63:32] = inmediate;
	    end

	  `MFLO:
	    begin
	       result = mult_result[31:0];
	       write_enable = 1;
	    end

	  `MTLO:
	    begin
	       mult_result[31:0] = inmediate;
	    end

	  `DIV:
	    begin

	       mult_result[63:32] = 0;
	       mult_result[31:0]  = 0;
	    end

	  `BLTZ:
	    begin
	       if (operand1 < 0)begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BGEZ:
	    begin
	       if (operand1 >= 0) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BLTZAL:
	    begin
	       if (operand1 < 0) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BGEZAL:
	    begin
	       if (operand1 >= 0) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BEQ:
	    begin
	       if (operand1 == operand2) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BNE:
	    begin
	       if (operand1 != operand2) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BLEZ:
	    begin
	       if (operand1 <= 0) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BGTZ:
	    begin
	       if (operand1 > 0) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `LED:
	    begin
	       result = operand1;	       
	    end
	  `LEDI:
	    begin
	       result = inmediate;	       
	    end	  

	  
	  default:
	    begin
	       result = 0;
	       branch_taken = 0;
	       mult_result = mult_result;
	       write_enable = 0;
	    end

	endcase
     end
endmodule
module Alu # (parameter SIZE=32, parameter OP_SIZE=6, parameter INM_SIZE=16)
   (
    input wire [OP_SIZE-1:0]  operation,
    input wire [SIZE-1:0]     operand0,
    input wire [SIZE-1:0]     operand1,
    input wire [SIZE-1:0]     operand2,
    input wire [INM_SIZE-1:0] inmediate,
    output reg [SIZE-1:0]     result,
    output reg 		      write_enable,
    output reg 		      branch_taken
    );


   reg [2*SIZE-1:0] 	      mult_result;

   always @ ( * )
     begin
	result = 0;
	branch_taken = 0;
	mult_result = mult_result;
	write_enable = 0;

	case (operation)

	  `ADDI:
	    begin
	       result = operand1+inmediate;
	       write_enable = 1;
	    end

	  `ADD:
	    begin
	       result = operand1 + operand0;
	       write_enable = 1;
	    end

	  `SUBI:
	    begin
	       result = operand1-inmediate;
	       write_enable = 1;
	    end

	  `SUB:
	    begin
	       result = operand1 - operand0;
	       write_enable = 1;
	    end

	  `AND:
	    begin
	       result = operand1 & operand0;
	       write_enable = 1;
	    end

	  `OR:
	    begin
	       result = operand1 | operand0;
	       write_enable = 1;
	    end

	  `XOR:
	    begin
	       result = operand1 ^ operand0;
	       write_enable = 1;
	    end

	  `NOR:
	    begin
	       result = ~(operand1|operand0);
	       write_enable = 1;
	    end

	  `SLT:
	    begin
	       if (operand1 < operand0) begin
		  result = 1;
	       end else begin
		  result = 0;
	       end
	       write_enable = 1;
	    end

	  `SLTI:
	    begin
	       if (operand1 < inmediate) begin
		  result = 1;
	       end else begin
		  result = 0;
	       end
	       write_enable = 1;
	    end

	  `ANDI:
	    begin
	       result = operand1 & inmediate;
	       write_enable = 1;
	    end

	  `ORI:
	    begin
	       result = operand1 | inmediate;
	       write_enable = 1;
	    end

	  `XORI:
	    begin
	       result = operand1 ^ inmediate;
	       write_enable = 1;
	    end

	  `SLL:
	    begin
	       result = operand1 << inmediate[15:10];
	       write_enable = 1;
	    end

	  `SRL:
	    begin
	       result = operand1 >> inmediate[15:10];
	       write_enable = 1;
	    end

	  `MULT:
	    begin
	       mult_result = operand1*operand0;
	    end

	  `MFHI:
	    begin
	       result = mult_result[63:32];
	       write_enable = 1;
	    end

	  `MTHI:
	    begin
	       mult_result[63:32] = inmediate;
	    end

	  `MFLO:
	    begin
	       result = mult_result[31:0];
	       write_enable = 1;
	    end

	  `MTLO:
	    begin
	       mult_result[31:0] = inmediate;
	    end

	  `DIV:
	    begin

	       mult_result[63:32] = 0;
	       mult_result[31:0]  = 0;
	    end

	  `BLTZ:
	    begin
	       if (operand1 < 0)begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BGEZ:
	    begin
	       if (operand1 >= 0) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BLTZAL:
	    begin
	       if (operand1 < 0) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BGEZAL:
	    begin
	       if (operand1 >= 0) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BEQ:
	    begin
	       if (operand1 == operand2) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BNE:
	    begin
	       if (operand1 != operand2) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BLEZ:
	    begin
	       if (operand1 <= 0) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `BGTZ:
	    begin
	       if (operand1 > 0) begin
		  branch_taken = 1;
	       end else begin
		  branch_taken = 0;
	       end
	    end

	  `LED:
	    begin
	       result = operand1;	       
	    end
	  `LEDI:
	    begin
	       result = inmediate;	       
	    end	  

	  
	  default:
	    begin
	       result = 0;
	       branch_taken = 0;
	       mult_result = mult_result;
	       write_enable = 0;
	    end

	endcase
     end
endmodule