data/full_repos/permissive/104269513/spring_fifo_v2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:447: Unsupported: Ignoring delay on this delayed statement.\n#30 rst = 0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:451: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/spring_fifo_v2.v:453: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/104269513/spring_fifo_v2.v:103: Cannot find file containing module: \'spring_fifo_mem\'\nspring_fifo_mem mem2(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem.v\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/spring_fifo_mem.sv\n             spring_fifo_mem\n             spring_fifo_mem.v\n             spring_fifo_mem.sv\n             obj_dir/spring_fifo_mem\n             obj_dir/spring_fifo_mem.v\n             obj_dir/spring_fifo_mem.sv\n%Error: data/full_repos/permissive/104269513/spring_fifo_v2.v:432: Cannot find file containing module: \'regfile\'\nregfile op_reg( \n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104269513/spring_fifo_v2.v:462: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n                                                                         : ... In instance spring_fifo_tb\nip_rd_count = 4 ;\n            ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spring_fifo_tb ();


reg clk, rst;
integer count;


reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;


reg[4:0] reg_wa;


reg rd_req,wr_req;
reg [1:0] ip_rd_count;
reg out_rdy, in_wr;
wire out_wr;
wire rd_ack, wr_ack;
wire rd_done, wr_done;
reg rd_done_next;


wire [1:0] packet_count;
wire in_rdy;
wire [7:0] first_word, last_word;



wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;


wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;

spring_fifo	UUT(
						.rd_req(rd_req),
						.wr_req(wr_req),
						.out_rdy(out_rdy), 
						.in_wr(in_wr),
						.ip_rd_count(ip_rd_count),
						.out_wr(out_wr),
						.pckt_rd_wr(),
						.rd_ack(rd_ack),
						.wr_ack(wr_ack),
						.rd_done(rd_done),
						.wr_done(wr_done),
						

						.in_rdy(in_rdy),
						.full(),
						.empty(),
						.nearly_full(),
						.nearly_empty(),
						.packet_count(packet_count),
						.first_word(first_word),
						.last_word(last_word),
						.fifo_busy(),
						


						.fifo_data_in(fifo_data_in),
						.fifo_data_out(fifo_data_out),
						.fifo_ctrl_in(fifo_ctrl_in),
						.fifo_ctrl_out(fifo_ctrl_out),
						.DEPTH(),
						.wr_state(),
						.state(),	
						

						.fifo_wa(),
						.fifo_ra(),
						.fifo_rd_en(),
						.fifo_wr_en(),
						

						.clk(clk),
						.rst(rst)
						);

assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];						
						
regfile op_reg(	
				.clk(clk),
				.rst(rst),
				.r0addr(),
				.r1addr(),
				.waddr(reg_wa),
				.wdata(fifo_data_out),
				.wena(out_wr),
				.r0data(),
				.r1data()
			   );

						
initial begin
rst = 1;
#30 rst = 0;
end

initial begin
#100
clk = 0;
forever #10 clk = ~clk;
end

initial begin


count = 0;
rd_req = 0;
wr_req = 1;
ip_rd_count = 4 ;
out_rdy = 1;
in_wr = 0;
reg_wa = 0;
reg_ra = 0;
$readmemh ("ip_reg_init_var_pckt.txt",ip_reg);
end

always @ (posedge clk)
begin




















































		if (count < 2)	wr_req <= 1;
		else if (wr_ack)	wr_req <= 0;

		if (count > 5 )
		begin
			if (in_rdy && fifo_ctrl_in != 'hab)
				begin
					in_wr <= 1;
					if (in_wr)
						reg_ra <= reg_ra + 1;
				end
			else 
				begin
					reg_ra <= reg_ra;
					in_wr <= 0;
				end
		end
		
		
		if (wr_done)	rd_req <= 1;
		if (rd_ack)		rd_req <= 0;
		
		if (count == 'h24 | count == 'h36)		rd_req <= 1;
		
		if(out_wr)
			reg_wa <= reg_wa +1;
		else 
			reg_wa <= reg_wa;
			


count <= count + 1;
end

endmodule
module spring_fifo_tb ();



reg clk, rst;
integer count;


reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;


reg[4:0] reg_wa;


reg rd_req,wr_req;
reg [1:0] ip_rd_count;
reg out_rdy, in_wr;
wire out_wr;
wire rd_ack, wr_ack;
wire rd_done, wr_done;
reg rd_done_next;


wire [1:0] packet_count;
wire in_rdy;
wire [7:0] first_word, last_word;



wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;


wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;

spring_fifo	UUT(
						.rd_req(rd_req),
						.wr_req(wr_req),
						.out_rdy(out_rdy), 
						.in_wr(in_wr),
						.ip_rd_count(ip_rd_count),
						.out_wr(out_wr),
						.pckt_rd_wr(),
						.rd_ack(rd_ack),
						.wr_ack(wr_ack),
						.rd_done(rd_done),
						.wr_done(wr_done),
						

						.in_rdy(in_rdy),
						.full(),
						.empty(),
						.nearly_full(),
						.nearly_empty(),
						.packet_count(packet_count),
						.first_word(first_word),
						.last_word(last_word),
						.fifo_busy(),
						


						.fifo_data_in(fifo_data_in),
						.fifo_data_out(fifo_data_out),
						.fifo_ctrl_in(fifo_ctrl_in),
						.fifo_ctrl_out(fifo_ctrl_out),
						.DEPTH(),
						.wr_state(),
						.state(),	
						

						.fifo_wa(),
						.fifo_ra(),
						.fifo_rd_en(),
						.fifo_wr_en(),
						

						.clk(clk),
						.rst(rst)
						);

assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];						
						
regfile op_reg(	
				.clk(clk),
				.rst(rst),
				.r0addr(),
				.r1addr(),
				.waddr(reg_wa),
				.wdata(fifo_data_out),
				.wena(out_wr),
				.r0data(),
				.r1data()
			   );

						
initial begin
rst = 1;
#30 rst = 0;
end

initial begin
#100
clk = 0;
forever #10 clk = ~clk;
end

initial begin


count = 0;
rd_req = 0;
wr_req = 1;
ip_rd_count = 4 ;
out_rdy = 1;
in_wr = 0;
reg_wa = 0;
reg_ra = 0;
$readmemh ("ip_reg_init_var_pckt.txt",ip_reg);
end

always @ (posedge clk)
begin




















































		if (count < 2)	wr_req <= 1;
		else if (wr_ack)	wr_req <= 0;

		if (count > 5 )
		begin
			if (in_rdy && fifo_ctrl_in != 'hab)
				begin
					in_wr <= 1;
					if (in_wr)
						reg_ra <= reg_ra + 1;
				end
			else 
				begin
					reg_ra <= reg_ra;
					in_wr <= 0;
				end
		end
		
		
		if (wr_done)	rd_req <= 1;
		if (rd_ack)		rd_req <= 0;
		
		if (count == 'h24 | count == 'h36)		rd_req <= 1;
		
		if(out_wr)
			reg_wa <= reg_wa +1;
		else 
			reg_wa <= reg_wa;
			


count <= count + 1;
end

endmodule