data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/top_sonic_dma_irq_generator.sv
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1: b'%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/top_sonic_dma_irq_generator.sv:24: Cannot find include file: ../sonic_dma_irq_generator.sv\n`include "../sonic_dma_irq_generator.sv" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic,data/full_repos/permissive/18477150/../sonic_dma_irq_generator.sv\n             data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic,data/full_repos/permissive/18477150/../sonic_dma_irq_generator.sv.v\n             data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic,data/full_repos/permissive/18477150/../sonic_dma_irq_generator.sv.sv\n             ../sonic_dma_irq_generator.sv\n             ../sonic_dma_irq_generator.sv.v\n             ../sonic_dma_irq_generator.sv.sv\n             obj_dir/../sonic_dma_irq_generator.sv\n             obj_dir/../sonic_dma_irq_generator.sv.v\n             obj_dir/../sonic_dma_irq_generator.sv.sv\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/top_sonic_dma_irq_generator.sv:68: Unsupported: Ignoring delay on this delayed statement.\nalways #4 clk_in <= ~clk_in;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module top;
  
timeunit 1ns; timeprecision 1ps;


logic            clk_in;
logic  [12:0]    rp;
logic  [12:0]    wp;


logic  [31:0]    data_available;
logic            irq;
logic            rstn;


sonic_dma_irq_generator _sonic_dma_irq_generator(
	.clk_in (clk_in),
	.rstn(rstn),
    .rp (rp),
    .wp (wp),
    .data_available (data_available),
    .irq (irq)
	);



test_sonic_dma_irq_generator test(
	.clk_in (clk_in),
    .data_available (data_available),
    .irq (irq),
	.rstn(rstn),
    .rp (rp),
    .wp (wp)
	);


initial begin
  clk_in <= 1'b1;
end


always #4 clk_in <= ~clk_in;


endmodule
module top;

  
timeunit 1ns; timeprecision 1ps;


logic            clk_in;
logic  [12:0]    rp;
logic  [12:0]    wp;


logic  [31:0]    data_available;
logic            irq;
logic            rstn;


sonic_dma_irq_generator _sonic_dma_irq_generator(
	.clk_in (clk_in),
	.rstn(rstn),
    .rp (rp),
    .wp (wp),
    .data_available (data_available),
    .irq (irq)
	);



test_sonic_dma_irq_generator test(
	.clk_in (clk_in),
    .data_available (data_available),
    .irq (irq),
	.rstn(rstn),
    .rp (rp),
    .wp (wp)
	);


initial begin
  clk_in <= 1'b1;
end


always #4 clk_in <= ~clk_in;


endmodule