data/full_repos/permissive/158845296/instruction_mem.v
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data/verilator_xmls/5936aa96-9665-4b2d-aae3-b4b48bba9750.xml
module instruction_mem
(
    input          clock,
    input          enable,
    input   [31:0] address,
    output [127:0] data,
    output         valid
);

    reg         seq_valid;
    reg [127:0] seq_data;
    reg         previous_enable;
    reg         should_read;
    reg   [3:0] counter;
    reg  [31:0] instruction_mem [255:0];
    wire        read_request;
    wire  [7:0] block_aligned_addr;

    initial begin
        $readmemh("C:/Users/JC/repo/pa-upc/tests/instructions.txt", instruction_mem);
        counter = 4'b0;
        should_read = 1'b1;
    end


    always @(posedge clock) begin
        previous_enable = enable;
    end


    always @(posedge clock) begin
        if (read_request)
            should_read = 1'b1;
    end


    always @(posedge clock) begin

        if (should_read) begin

            counter = counter + 1;

            if (counter == 4'd10) begin
                counter          <= 4'b0;
                should_read      <= 1'b0;
                seq_data [31: 0] <= instruction_mem[block_aligned_addr];
                seq_data [63:32] <= instruction_mem[block_aligned_addr + 1];
                seq_data [95:64] <= instruction_mem[block_aligned_addr + 2];
                seq_data[127:96] <= instruction_mem[block_aligned_addr + 3];
                seq_valid        <= 1'b1;
            end
        end else
            seq_valid = 1'b0;
    end
    

    assign read_request       = ~previous_enable & enable;
    assign block_aligned_addr = address[9:2] & 8'b11111100;


    assign valid = seq_valid;
    assign data  = seq_data;

endmodule
module instruction_mem
(
    input          clock,
    input          enable,
    input   [31:0] address,
    output [127:0] data,
    output         valid
);


    reg         seq_valid;
    reg [127:0] seq_data;
    reg         previous_enable;
    reg         should_read;
    reg   [3:0] counter;
    reg  [31:0] instruction_mem [255:0];
    wire        read_request;
    wire  [7:0] block_aligned_addr;

    initial begin
        $readmemh("C:/Users/JC/repo/pa-upc/tests/instructions.txt", instruction_mem);
        counter = 4'b0;
        should_read = 1'b1;
    end


    always @(posedge clock) begin
        previous_enable = enable;
    end


    always @(posedge clock) begin
        if (read_request)
            should_read = 1'b1;
    end


    always @(posedge clock) begin

        if (should_read) begin

            counter = counter + 1;

            if (counter == 4'd10) begin
                counter          <= 4'b0;
                should_read      <= 1'b0;
                seq_data [31: 0] <= instruction_mem[block_aligned_addr];
                seq_data [63:32] <= instruction_mem[block_aligned_addr + 1];
                seq_data [95:64] <= instruction_mem[block_aligned_addr + 2];
                seq_data[127:96] <= instruction_mem[block_aligned_addr + 3];
                seq_valid        <= 1'b1;
            end
        end else
            seq_valid = 1'b0;
    end
    

    assign read_request       = ~previous_enable & enable;
    assign block_aligned_addr = address[9:2] & 8'b11111100;


    assign valid = seq_valid;
    assign data  = seq_data;

endmodule