data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v
 line:223: before: "("
1: b'%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:60: Cannot find include file: wb_model_defines.v\n`include "wb_model_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131712122/bench/verilog,data/full_repos/permissive/131712122/wb_model_defines.v\n             data/full_repos/permissive/131712122/bench/verilog,data/full_repos/permissive/131712122/wb_model_defines.v.v\n             data/full_repos/permissive/131712122/bench/verilog,data/full_repos/permissive/131712122/wb_model_defines.v.sv\n             wb_model_defines.v\n             wb_model_defines.v.v\n             wb_model_defines.v.sv\n             obj_dir/wb_model_defines.v\n             obj_dir/wb_model_defines.v.v\n             obj_dir/wb_model_defines.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:99: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:114: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:115: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:123: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:124: syntax error, unexpected \'@\'\nwhile(~ack) @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:125: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:156: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:157: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:163: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:170: syntax error, unexpected \'@\'\nwhile(~ack) @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:171: Unsupported: Ignoring delay on this delayed statement.\n#2;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:179: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:180: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:186: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:187: syntax error, unexpected \'@\'\nwhile(~ack) @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:188: Unsupported: Ignoring delay on this delayed statement.\n#2;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:195: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:196: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:202: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:203: syntax error, unexpected \'@\'\nwhile(~ack) @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:204: Unsupported: Ignoring delay on this delayed statement.\n#2;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:211: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:212: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:218: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:219: syntax error, unexpected \'@\'\nwhile(~ack) @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:220: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:245: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:246: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:254: syntax error, unexpected \'@\'\nwhile(~ack) @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:256: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:288: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:289: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:293: syntax error, unexpected \'@\'\nrepeat(delay) @(posedge clk);\n              ^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:297: syntax error, unexpected \'@\'\nwhile(~ack) @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:299: Unsupported: Ignoring delay on this delayed statement.\n#2;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:305: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:306: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:313: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:314: syntax error, unexpected \'@\'\nwhile(~ack) @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:316: Unsupported: Ignoring delay on this delayed statement.\n#2;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:322: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:323: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:331: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:332: syntax error, unexpected \'@\'\nwhile(~ack) @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:334: Unsupported: Ignoring delay on this delayed statement.\n#2;\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:340: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:341: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:348: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Error: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:349: syntax error, unexpected \'@\'\nwhile(~ack) @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/wb_mast_model.v:351: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Error: Exiting due to 30 error(s), 22 warning(s)\n'
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);

input		clk, rst;
output	[31:0]	adr;
input	[31:0]	din;
output	[31:0]	dout;
output		cyc, stb;
output	[3:0]	sel;
output		we;
input		ack, err, rty;






reg	[31:0]	adr;
reg	[31:0]	dout;
reg		cyc, stb;
reg	[3:0]	sel;
reg		we;






initial
   begin


	adr = 32'hffff_ffff;
	dout = 32'hxxxx_xxxx;
	cyc = 0;
	stb = 0;
	sel = 4'hx;
	we = 1'hx;
	#1;
	$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end






task wb_wr1;
input	[31:0]	a;
input	[3:0]	s;
input	[31:0]	d;

begin
@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;

@(posedge clk);
while(~ack)	@(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;


end
endtask







task wb_wr4;
input	[31:0]	a;
input	[3:0]	s;
input		delay;
input	[31:0]	d1;
input	[31:0]	d2;
input	[31:0]	d3;
input	[31:0]	d4;

integer		delay;

begin

@(posedge clk);
#1;
cyc = 1;
sel = s;

repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack)	@(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;


repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack)	@(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;

repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack)	@(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;

repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack)	@(posedge clk);
#1;
stb=0;
cyc=0;

adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;

end
endtask







task wb_rd1;
input	[31:0]	a;
input	[3:0]	s;
output	[31:0]	d;

begin

@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;


while(~ack)	@(posedge clk);
d = din;
#1;
cyc=0;
stb=0;


adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;

end
endtask








task wb_rd4;
input	[31:0]	a;
input	[3:0]	s;
input		delay;
output	[31:0]	d1;
output	[31:0]	d2;
output	[31:0]	d3;
output	[31:0]	d4;

integer		delay;
begin

@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)	@(posedge clk);

adr = a;
stb = 1;
while(~ack)	@(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
we = 0;
sel = s;

adr = a+4;
stb = 1;
@(posedge clk);
while(~ack)	@(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
we = 0;
sel = s;


adr = a+8;
stb = 1;
@(posedge clk);
while(~ack)	@(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
we = 0;
sel = s;

adr = a+12;
stb = 1;
@(posedge clk);
while(~ack)	@(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
end
endtask


endmodule
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);


input		clk, rst;
output	[31:0]	adr;
input	[31:0]	din;
output	[31:0]	dout;
output		cyc, stb;
output	[3:0]	sel;
output		we;
input		ack, err, rty;






reg	[31:0]	adr;
reg	[31:0]	dout;
reg		cyc, stb;
reg	[3:0]	sel;
reg		we;






initial
   begin


	adr = 32'hffff_ffff;
	dout = 32'hxxxx_xxxx;
	cyc = 0;
	stb = 0;
	sel = 4'hx;
	we = 1'hx;
	#1;
	$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end






task wb_wr1;
input	[31:0]	a;
input	[3:0]	s;
input	[31:0]	d;

begin
@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;

@(posedge clk);
while(~ack)	@(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;


end
endtask







task wb_wr4;
input	[31:0]	a;
input	[3:0]	s;
input		delay;
input	[31:0]	d1;
input	[31:0]	d2;
input	[31:0]	d3;
input	[31:0]	d4;

integer		delay;

begin

@(posedge clk);
#1;
cyc = 1;
sel = s;

repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack)	@(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;


repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack)	@(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;

repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack)	@(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;

repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack)	@(posedge clk);
#1;
stb=0;
cyc=0;

adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;

end
endtask







task wb_rd1;
input	[31:0]	a;
input	[3:0]	s;
output	[31:0]	d;

begin

@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;


while(~ack)	@(posedge clk);
d = din;
#1;
cyc=0;
stb=0;


adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;

end
endtask








task wb_rd4;
input	[31:0]	a;
input	[3:0]	s;
input		delay;
output	[31:0]	d1;
output	[31:0]	d2;
output	[31:0]	d3;
output	[31:0]	d4;

integer		delay;
begin

@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)	@(posedge clk);

adr = a;
stb = 1;
while(~ack)	@(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
we = 0;
sel = s;

adr = a+4;
stb = 1;
@(posedge clk);
while(~ack)	@(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
we = 0;
sel = s;


adr = a+8;
stb = 1;
@(posedge clk);
while(~ack)	@(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
	@(posedge clk);
	#1;
   end
we = 0;
sel = s;

adr = a+12;
stb = 1;
@(posedge clk);
while(~ack)	@(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
end
endtask


endmodule