data/full_repos/permissive/105948944/simulations/signalSync_testBench.v
 line:25: before: "="
1: b'%Error: data/full_repos/permissive/105948944/simulations/signalSync_testBench.v:50: syntax error, unexpected \'@\'\n      begin @(negedge clk)\n            ^\n%Error: data/full_repos/permissive/105948944/simulations/signalSync_testBench.v:52: Unsupported or unknown PLI call: $dist_uniform\n        delay = $dist_uniform(2,50,150);\n                ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/signalSync_testBench.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #delay;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/signalSync_testBench.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module signalSync_testBench();
    
      reg clk, async = 0; 
      wire rise, fall;
    
          signalSync UUT(
          .clock(clk),
          .asynchronous_signal(async),
          .rising_edge(rise),
          .falling_edge(fall)
      );
    
    initial begin
    
        
     clk <= 0;
      async <= 0;
    end
    

    

       time delay = 0;      
    
    initial
    begin
      while ($time < 1000) 
      begin @(negedge clk)

        delay = $dist_uniform(2,50,150);
        #delay;
        async = ~async;
      end
    end
    
    always
    begin
        #10
        clk = ~clk;
    end
    
    endmodule
module signalSync_testBench();

    
      reg clk, async = 0; 
      wire rise, fall;
    
          signalSync UUT(
          .clock(clk),
          .asynchronous_signal(async),
          .rising_edge(rise),
          .falling_edge(fall)
      );
    
    initial begin
    
        
     clk <= 0;
      async <= 0;
    end
    

    

       time delay = 0;      
    
    initial
    begin
      while ($time < 1000) 
      begin @(negedge clk)

        delay = $dist_uniform(2,50,150);
        #delay;
        async = ~async;
      end
    end
    
    always
    begin
        #10
        clk = ~clk;
    end
    
    endmodule