data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton_tb.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("automaton_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, automaton_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("data: %b (%d)", data, count);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n            #4\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128117771/Automaton-Verilog-Nbits/automaton_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  # 1 $display("FIN de la simulacion");\n  ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module automaton_tb();

	parameter WIDTH = 80;

    reg[7:0] count = 0;


	reg clk = 0;


	wire [WIDTH-1:0] data;


	automaton #(.WIDTH(WIDTH)) myCA ( .clk(clk), .data(data) );
	defparam myCA.N=1;
	defparam myCA.RULE=126;
	defparam myCA.SEED = 2**(WIDTH/2);


	always #1 clk = ~clk;

	integer file;


	initial begin


		$dumpfile("automaton_tb.vcd");
		$dumpvars(0, automaton_tb);

		#1 $display("data: %b (%d)", data, count);

		file = $fopen("data.out", "wb");
		$fwrite(file, "%b\n", data);

        for (count=1; count<=59; count=count+1)
        begin
            #4
            $display("data: %b (%d)", data, count);
			$fwrite(file, "%b\n", data);
        end

		$fclose(file);
		# 1 $display("FIN de la simulacion");
		$finish;

	end

endmodule
module automaton_tb();


	parameter WIDTH = 80;

    reg[7:0] count = 0;


	reg clk = 0;


	wire [WIDTH-1:0] data;


	automaton #(.WIDTH(WIDTH)) myCA ( .clk(clk), .data(data) );
	defparam myCA.N=1;
	defparam myCA.RULE=126;
	defparam myCA.SEED = 2**(WIDTH/2);


	always #1 clk = ~clk;

	integer file;


	initial begin


		$dumpfile("automaton_tb.vcd");
		$dumpvars(0, automaton_tb);

		#1 $display("data: %b (%d)", data, count);

		file = $fopen("data.out", "wb");
		$fwrite(file, "%b\n", data);

        for (count=1; count<=59; count=count+1)
        begin
            #4
            $display("data: %b (%d)", data, count);
			$fwrite(file, "%b\n", data);
        end

		$fclose(file);
		# 1 $display("FIN de la simulacion");
		$finish;

	end

endmodule