data/full_repos/permissive/2047449/pram_sram_top.v
1: b"%Error: data/full_repos/permissive/2047449/pram_sram_top.v:40: Cannot find file containing module: 'dcm_clock'\ndcm_clock main_clock (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2047449,data/full_repos/permissive/2047449/dcm_clock\n             data/full_repos/permissive/2047449,data/full_repos/permissive/2047449/dcm_clock.v\n             data/full_repos/permissive/2047449,data/full_repos/permissive/2047449/dcm_clock.sv\n             dcm_clock\n             dcm_clock.v\n             dcm_clock.sv\n             obj_dir/dcm_clock\n             obj_dir/dcm_clock.v\n             obj_dir/dcm_clock.sv\n%Error: data/full_repos/permissive/2047449/pram_sram_top.v:49: Cannot find file containing module: 'pram_sram_ctrl'\npram_sram_ctrl sram_ctrl (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/2047449/pram_sram_top.v:61: Cannot find file containing module: 'pattern_rom'\npattern_rom pattern_rom (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/2047449/pram_sram_top.v:67: Cannot find file containing module: 'tristate_generic'\ntristate_generic #(.N(16))\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/2047449/pram_sram_top.v:75: Cannot find file containing module: 'clock_divider'\nclock_divider clock_divider(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/2047449/pram_sram_top.v:82: Cannot find file containing module: 'debounce_generic'\ndebounce_generic button_debouncer(\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/2047449/pram_sram_top.v:90: Cannot find file containing module: 'hex_7_segment'\nhex_7_segment data_display(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/2047449/pram_sram_top.v:98: Cannot find file containing module: 'hex_7_segment'\nhex_7_segment addr_display(\n^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module pram_sram_top(
	input wire clk,
	input wire button,
	output wire [6:0] a_to_g,
	output wire [3:0] an,
	output wire [6:0] a_to_g2,
	output wire [3:0] an2,
	output reg good,
	output reg bad,
	output wire [1:0] hi_addr,
	output wire [18:0] addr,
	inout wire [15:0] data,
	output wire ce,
	output wire be,
	output wire we,
	output wire oe
);

wire clr, en, dclk, bclk, fclk;
wire [15:0] dataio, din1;
wire [17:0] sram_addr;
wire [5:0] pattern;
wire button_d;

assign clr = button_d;
assign ce = 0;
assign be = 0;
assign oe = en;

assign data = dataio;
assign addr = {1'b0, sram_addr};
assign hi_addr = sram_addr[17:16];


dcm_clock main_clock (
	.CLKIN_IN(clk),
	.RST_IN(clr),
	.CLKFX_OUT(fclk)


);


pram_sram_ctrl sram_ctrl (
	.clk(fclk),
	.clr(clr),
	.go(bclk),
	.halt(bad),
	.we(we),
	.sram_addr(sram_addr),
	.pattern(pattern),
	.en(en)
);


pattern_rom pattern_rom (
	.clk(fclk),
	.addr(pattern),
	.data(din1)
);

tristate_generic #(.N(16))
data_tristate (
	.in(din1),
	.en(en),
	.out(dataio)
);


clock_divider clock_divider(
	.clk(fclk),
	.clr(clr),
	.clk6(bclk),
	.clk17(dclk)
);

debounce_generic button_debouncer(
	.in(button),
	.clk(dclk),
	.clr(clr),
	.out(button_d)
);


hex_7_segment data_display(
	.x(data),
	.clk(fclk),
	.clr(clr),
	.a_to_g(a_to_g),
	.an(an)
);

hex_7_segment addr_display(
	.x(addr[15:0]),
	.clk(fclk),
	.clr(clr),
	.a_to_g(a_to_g2),
	.an(an2)
);

always @*
	if (data == din1)
		begin
			bad <= 0;
			good <= 1;
		end
	else
		begin
			bad <= 1;
			good <= 0;
		end

endmodule
module pram_sram_top(
	input wire clk,
	input wire button,
	output wire [6:0] a_to_g,
	output wire [3:0] an,
	output wire [6:0] a_to_g2,
	output wire [3:0] an2,
	output reg good,
	output reg bad,
	output wire [1:0] hi_addr,
	output wire [18:0] addr,
	inout wire [15:0] data,
	output wire ce,
	output wire be,
	output wire we,
	output wire oe
);


wire clr, en, dclk, bclk, fclk;
wire [15:0] dataio, din1;
wire [17:0] sram_addr;
wire [5:0] pattern;
wire button_d;

assign clr = button_d;
assign ce = 0;
assign be = 0;
assign oe = en;

assign data = dataio;
assign addr = {1'b0, sram_addr};
assign hi_addr = sram_addr[17:16];


dcm_clock main_clock (
	.CLKIN_IN(clk),
	.RST_IN(clr),
	.CLKFX_OUT(fclk)


);


pram_sram_ctrl sram_ctrl (
	.clk(fclk),
	.clr(clr),
	.go(bclk),
	.halt(bad),
	.we(we),
	.sram_addr(sram_addr),
	.pattern(pattern),
	.en(en)
);


pattern_rom pattern_rom (
	.clk(fclk),
	.addr(pattern),
	.data(din1)
);

tristate_generic #(.N(16))
data_tristate (
	.in(din1),
	.en(en),
	.out(dataio)
);


clock_divider clock_divider(
	.clk(fclk),
	.clr(clr),
	.clk6(bclk),
	.clk17(dclk)
);

debounce_generic button_debouncer(
	.in(button),
	.clk(dclk),
	.clr(clr),
	.out(button_d)
);


hex_7_segment data_display(
	.x(data),
	.clk(fclk),
	.clr(clr),
	.a_to_g(a_to_g),
	.an(an)
);

hex_7_segment addr_display(
	.x(addr[15:0]),
	.clk(fclk),
	.clr(clr),
	.a_to_g(a_to_g2),
	.an(an2)
);

always @*
	if (data == din1)
		begin
			bad <= 0;
			good <= 1;
		end
	else
		begin
			bad <= 1;
			good <= 0;
		end

endmodule