data/full_repos/permissive/134719388/alu32/alu32.v
 line:1 column:1: Illegal character '\x00'
data/verilator_xmls/ef43e684-40cb-4cac-9756-d3627caf221a.xml
module  alu32(CLK, inp1, inp2, ALUop, out);
	input  CLK;
	input  [2:0]  ALUop;
	input  [31:0] inp1;
	input  [31:0] inp2;
	output [31:0] out;
	

	parameter COMB_STATE       = 2'b00;
	parameter MULT_CONT_STATE  = 2'b01;
	parameter MULT_SHIFT_STATE = 2'b10;
	parameter MULT_END_STATE   = 2'b11;
	

	reg [1:0]  state      = COMB_STATE;
	reg [1:0]  next_state = COMB_STATE;
	reg [63:0] seqALUResult;
	reg [31:0] ALUResult;
	integer multCounter;
	
	assign out = ALUResult;
	

	parameter ADD  = 3'b000;
	parameter SUB  = 3'b001;
	parameter MULT = 3'b010;
	parameter AND  = 3'b011;
	parameter OR   = 3'b100;
	parameter NAND = 3'b101;
	parameter NOR  = 3'b110;
	parameter XOR  = 3'b111;
	
	always @(posedge CLK) begin
	
		case(state)
			COMB_STATE: begin
				seqALUResult <= {32'h00000000,inp2};
				multCounter <= 0;
				state <= next_state;
			end	
			MULT_CONT_STATE: begin

				if (multCounter < 32) begin
					seqALUResult[63:32] <= seqALUResult[63:32] + (seqALUResult[0] ? inp1 : 0);
					multCounter <= multCounter + 1;
					state <= MULT_SHIFT_STATE;
				end

				if (multCounter == 32) begin
					state <= MULT_END_STATE;
				end
			end
			MULT_SHIFT_STATE: begin

				seqALUResult <= seqALUResult >> 1;
				state <= MULT_CONT_STATE;
			end
			MULT_END_STATE: begin
				state <= next_state;
			end
			default: begin
			
			end
		endcase
		
	end
	

	always @(*) begin
	
		case(ALUop)
			ADD: begin
				ALUResult = inp1 + inp2;
			end
			SUB: begin
				ALUResult = inp1 - inp2;
			end
			MULT: begin

				if (state == COMB_STATE) begin
					next_state = MULT_CONT_STATE;
				end

				if (state == MULT_END_STATE) begin
					ALUResult = seqALUResult[31:0];
					next_state = COMB_STATE;
				end
				
			end
			AND: begin
				ALUResult = inp1 & inp2;
			end
			OR: begin
				ALUResult = inp1 | inp2;
			end
			NAND: begin
				ALUResult = ~(inp1 & inp2);
			end
			NOR: begin
				ALUResult = ~(inp1 | inp2);
			end
			XOR: begin
				ALUResult = inp1 ^ inp2;
			end
			default: begin
			
			end
		endcase
		
	end
	
endmodule
module  alu32(CLK, inp1, inp2, ALUop, out);

	input  CLK;
	input  [2:0]  ALUop;
	input  [31:0] inp1;
	input  [31:0] inp2;
	output [31:0] out;
	

	parameter COMB_STATE       = 2'b00;
	parameter MULT_CONT_STATE  = 2'b01;
	parameter MULT_SHIFT_STATE = 2'b10;
	parameter MULT_END_STATE   = 2'b11;
	

	reg [1:0]  state      = COMB_STATE;
	reg [1:0]  next_state = COMB_STATE;
	reg [63:0] seqALUResult;
	reg [31:0] ALUResult;
	integer multCounter;
	
	assign out = ALUResult;
	

	parameter ADD  = 3'b000;
	parameter SUB  = 3'b001;
	parameter MULT = 3'b010;
	parameter AND  = 3'b011;
	parameter OR   = 3'b100;
	parameter NAND = 3'b101;
	parameter NOR  = 3'b110;
	parameter XOR  = 3'b111;
	
	always @(posedge CLK) begin
	
		case(state)
			COMB_STATE: begin
				seqALUResult <= {32'h00000000,inp2};
				multCounter <= 0;
				state <= next_state;
			end	
			MULT_CONT_STATE: begin

				if (multCounter < 32) begin
					seqALUResult[63:32] <= seqALUResult[63:32] + (seqALUResult[0] ? inp1 : 0);
					multCounter <= multCounter + 1;
					state <= MULT_SHIFT_STATE;
				end

				if (multCounter == 32) begin
					state <= MULT_END_STATE;
				end
			end
			MULT_SHIFT_STATE: begin

				seqALUResult <= seqALUResult >> 1;
				state <= MULT_CONT_STATE;
			end
			MULT_END_STATE: begin
				state <= next_state;
			end
			default: begin
			
			end
		endcase
		
	end
	

	always @(*) begin
	
		case(ALUop)
			ADD: begin
				ALUResult = inp1 + inp2;
			end
			SUB: begin
				ALUResult = inp1 - inp2;
			end
			MULT: begin

				if (state == COMB_STATE) begin
					next_state = MULT_CONT_STATE;
				end

				if (state == MULT_END_STATE) begin
					ALUResult = seqALUResult[31:0];
					next_state = COMB_STATE;
				end
				
			end
			AND: begin
				ALUResult = inp1 & inp2;
			end
			OR: begin
				ALUResult = inp1 | inp2;
			end
			NAND: begin
				ALUResult = ~(inp1 & inp2);
			end
			NOR: begin
				ALUResult = ~(inp1 | inp2);
			end
			XOR: begin
				ALUResult = inp1 ^ inp2;
			end
			default: begin
			
			end
		endcase
		
	end
	
endmodule