data/full_repos/permissive/166085290/d_mem_upduino2.v
1: b'%Error: data/full_repos/permissive/166085290/d_mem_upduino2.v:15: Cannot find include file: macros/direction.vh\n`include "macros/direction.vh" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166085290,data/full_repos/permissive/166085290/macros/direction.vh\n             data/full_repos/permissive/166085290,data/full_repos/permissive/166085290/macros/direction.vh.v\n             data/full_repos/permissive/166085290,data/full_repos/permissive/166085290/macros/direction.vh.sv\n             macros/direction.vh\n             macros/direction.vh.v\n             macros/direction.vh.sv\n             obj_dir/macros/direction.vh\n             obj_dir/macros/direction.vh.v\n             obj_dir/macros/direction.vh.sv\n%Error: data/full_repos/permissive/166085290/d_mem_upduino2.v:26: Define or directive not defined: \'`DIRECTION_WRITE\'\nassign write_en = d_req && d_dir == `DIRECTION_WRITE;\n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/166085290/d_mem_upduino2.v:26: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign write_en = d_req && d_dir == `DIRECTION_WRITE;\n                                                    ^\n%Error: Exiting due to 3 error(s)\n'
module d_mem_upduino2 #(
	parameter [7:0]d_addr_width = 8'd8,
	parameter [31:0]d_mem_length = 32'd64
)(
	input clk,

	input d_req,
	input d_dir,
	input [d_addr_width-1:0]d_addr,
	input [7:0]d_wdata,
	output d_ack,
	output [7:0]d_rdata
);

`include "macros/direction.vh"

reg [7:0]memory[0:d_mem_length-1];

integer i;

wire write_en;
wire [7:0]write_data;

reg [7:0]read_data;

assign write_en = d_req && d_dir == `DIRECTION_WRITE;
assign write_data = d_wdata;
assign d_rdata = read_data;

reg ready;

assign d_ack = d_req ? ready : 0;

always @(posedge clk) begin
	if (d_req)
		ready <= 1;
	else
		ready <= 0;
end

always @(posedge clk) begin
	if (write_en)
		memory[d_addr] <= write_data;

	read_data <= memory[d_addr];
end

endmodule
module d_mem_upduino2 #(
	parameter [7:0]d_addr_width = 8'd8,
	parameter [31:0]d_mem_length = 32'd64
)(
	input clk,

	input d_req,
	input d_dir,
	input [d_addr_width-1:0]d_addr,
	input [7:0]d_wdata,
	output d_ack,
	output [7:0]d_rdata
);


`include "macros/direction.vh"

reg [7:0]memory[0:d_mem_length-1];

integer i;

wire write_en;
wire [7:0]write_data;

reg [7:0]read_data;

assign write_en = d_req && d_dir == `DIRECTION_WRITE;
assign write_data = d_wdata;
assign d_rdata = read_data;

reg ready;

assign d_ack = d_req ? ready : 0;

always @(posedge clk) begin
	if (d_req)
		ready <= 1;
	else
		ready <= 0;
end

always @(posedge clk) begin
	if (write_en)
		memory[d_addr] <= write_data;

	read_data <= memory[d_addr];
end

endmodule