data/full_repos/permissive/143278/ivltests/dotinid.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dotinid.v:33: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module m(x);
   output x;
   reg	  \y.z ;
   assign x = \y.z ;
endmodule
module m(x);

   output x;
   reg	  \y.z ;
   assign x = \y.z ;
endmodule