data/full_repos/permissive/160437780/Source/Disp.v
data/verilator_xmls/85eaf540-7281-4a00-943b-38df7e898d86.xml
module Disp(
    input  clk,
    input [7:0] Input,
    input [3:0] ColorInput,
    output reg [3:0] Dig,
    output reg [6:0] Seg
    );
    
    reg [1:0] CaseDis = 0;
    reg [17:0] CountDown = 0;
    reg [3:0] NumOut = 0;
    reg [3:0] ColorType;
    reg [11:0] bcd = 0;
    reg [3:0] i = 0;
    reg [3:0]BCDCase = 0;
    reg [7:0] Perc = 0;
    reg [11:0] BCDOut = 0;
    
    localparam max = 'd195312;
    
    always @(posedge clk)
    begin
        ColorType = ColorInput;
        if (CountDown > max)
        begin
            CaseDis = CaseDis + 1;
            CountDown = 0;
        end
        else
        begin
            CountDown = CountDown + 1;
        end
        case (BCDCase)
        0:
        begin
            Perc <= Input;
            bcd <= 0;
            i <= 0;
            BCDCase <= 1;
        end
        1:
        begin
            bcd[0] <= Perc[7];
            BCDCase <= 2;
            i <= i + 1;
        end
        2:
        begin
            if (i == 8)
            begin
                BCDCase <= 4;
            end
            else
            begin
                if (bcd[7:4] >= 5)
                    bcd <= bcd + 48;
                if (bcd[3:0] >= 5)
                    bcd <= bcd + 3;
                BCDCase <= 3;
            end
        end
        3:
        begin
            bcd <= bcd << 1;
            Perc <= Perc << 1;
            BCDCase <= 1;
        end
        4:
        begin
            BCDOut = bcd;
            BCDCase <= 0;
        end
        endcase
    end
    
    always @(posedge clk)
    begin
        case (CaseDis)
        2'b00:
            begin
                Dig = 4'b0111;
                NumOut = 4'b1010;
            end
        2'b01:
            begin
                Dig = 4'b1011;
                NumOut = BCDOut[11:8];
            end
        2'b10:
            begin
                Dig = 4'b1101;
                NumOut = BCDOut[7:4];
            end
        2'b11:
            begin
                Dig = 4'b1110; 
                NumOut = BCDOut[3:0];
            end
        endcase
        end

    always @(*)
    begin
        case (NumOut)
        4'b0000: Seg = 7'b0000001;
        4'b0001: Seg = 7'b1001111;
        4'b0010: Seg = 7'b0010010;
        4'b0011: Seg = 7'b0000110;
        4'b0100: Seg = 7'b1001100;
        4'b0101: Seg = 7'b0100100;
        4'b0110: Seg = 7'b0100000;
        4'b0111: Seg = 7'b0001111;
        4'b1000: Seg = 7'b0000000;
        4'b1001: Seg = 7'b0000100;
        4'b1010:
        begin
            if (ColorType == 0)
            begin
                Seg = 7'b1111010;
            end
            else if (ColorType == 1)
            begin
                Seg = 7'b1100000;
            end
            else if (ColorType == 2)
            begin
                Seg = 7'b0100001;
            end
            else if (ColorType == 3)
            begin 
                Seg = 7'b1001100;
            end
            else if (ColorType == 4)
            begin
                Seg = 7'b1100011;
            end
        end
        default: Seg = 7'b0000001;
        endcase
    end
    
    
endmodule
module Disp(
    input  clk,
    input [7:0] Input,
    input [3:0] ColorInput,
    output reg [3:0] Dig,
    output reg [6:0] Seg
    );

    
    reg [1:0] CaseDis = 0;
    reg [17:0] CountDown = 0;
    reg [3:0] NumOut = 0;
    reg [3:0] ColorType;
    reg [11:0] bcd = 0;
    reg [3:0] i = 0;
    reg [3:0]BCDCase = 0;
    reg [7:0] Perc = 0;
    reg [11:0] BCDOut = 0;
    
    localparam max = 'd195312;
    
    always @(posedge clk)
    begin
        ColorType = ColorInput;
        if (CountDown > max)
        begin
            CaseDis = CaseDis + 1;
            CountDown = 0;
        end
        else
        begin
            CountDown = CountDown + 1;
        end
        case (BCDCase)
        0:
        begin
            Perc <= Input;
            bcd <= 0;
            i <= 0;
            BCDCase <= 1;
        end
        1:
        begin
            bcd[0] <= Perc[7];
            BCDCase <= 2;
            i <= i + 1;
        end
        2:
        begin
            if (i == 8)
            begin
                BCDCase <= 4;
            end
            else
            begin
                if (bcd[7:4] >= 5)
                    bcd <= bcd + 48;
                if (bcd[3:0] >= 5)
                    bcd <= bcd + 3;
                BCDCase <= 3;
            end
        end
        3:
        begin
            bcd <= bcd << 1;
            Perc <= Perc << 1;
            BCDCase <= 1;
        end
        4:
        begin
            BCDOut = bcd;
            BCDCase <= 0;
        end
        endcase
    end
    
    always @(posedge clk)
    begin
        case (CaseDis)
        2'b00:
            begin
                Dig = 4'b0111;
                NumOut = 4'b1010;
            end
        2'b01:
            begin
                Dig = 4'b1011;
                NumOut = BCDOut[11:8];
            end
        2'b10:
            begin
                Dig = 4'b1101;
                NumOut = BCDOut[7:4];
            end
        2'b11:
            begin
                Dig = 4'b1110; 
                NumOut = BCDOut[3:0];
            end
        endcase
        end

    always @(*)
    begin
        case (NumOut)
        4'b0000: Seg = 7'b0000001;
        4'b0001: Seg = 7'b1001111;
        4'b0010: Seg = 7'b0010010;
        4'b0011: Seg = 7'b0000110;
        4'b0100: Seg = 7'b1001100;
        4'b0101: Seg = 7'b0100100;
        4'b0110: Seg = 7'b0100000;
        4'b0111: Seg = 7'b0001111;
        4'b1000: Seg = 7'b0000000;
        4'b1001: Seg = 7'b0000100;
        4'b1010:
        begin
            if (ColorType == 0)
            begin
                Seg = 7'b1111010;
            end
            else if (ColorType == 1)
            begin
                Seg = 7'b1100000;
            end
            else if (ColorType == 2)
            begin
                Seg = 7'b0100001;
            end
            else if (ColorType == 3)
            begin 
                Seg = 7'b1001100;
            end
            else if (ColorType == 4)
            begin
                Seg = 7'b1100011;
            end
        end
        default: Seg = 7'b0000001;
        endcase
    end
    
    
endmodule