data/full_repos/permissive/143278/ivltests/tri2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module short(inout [7:0] p, input en);
	assign p = en ? 8'h55 : 8'hzz;
endmodule
module short(inout [7:0] p, input en);

	assign p = en ? 8'h55 : 8'hzz;
endmodule