data/full_repos/permissive/216654561/HW/Pcores/Ethernet/Ethernet_MAC_V1.00-b.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/8d1f6720-8bfa-4e67-8366-a240d6b84218.xml
module Ethernet_MAC  #(parameter data_width = 32)
(

 input [3:0] phy_rx_data,
 input phy_rx_DV,
 input phy_rx_en,
 input phy_rx_clk,
 
 output [3:0] phy_tx_data,
 output phy_tx_DV,
 output phy_tx_en,
 input phy_tx_clk,
 
 output phy_MDC,
 output phy_MDIO,
 output phy_rst,
 



 input AWvalid,
 input AWready,
 input [31:0] AWaddr,
 input  [2:0] AWprot,
 

 input Wvalid,
 input Wready,
 input [data_width-1 : 0] Wdata,
 input [data_width/8 -1 : 0] Wstrb,
 

 output Bvalid,
 output Bready,
 output [1:0] Bresp,
 

 input ARvalid,
 input ARready,
 input [31:0] ARaddr,
 input [2:0] ARprot,
 

 output Rvalid,
 output Rready,
 output [data_width-1 : 0]Rdata,
 output [1:0] Rresp,
 


  input  Aclk,
  input  Areset,
  output TVALID,
  
  inout [data_width -1 : 0]   Tdata,  
  inout [data_width/8 -1 : 0] Tstrb,
  
  inout [data_width/8 -1 : 0] Tkeep,
  inout Tlast
  
    );
    
    
    
    
    
endmodule
module Ethernet_MAC  #(parameter data_width = 32)
(

 input [3:0] phy_rx_data,
 input phy_rx_DV,
 input phy_rx_en,
 input phy_rx_clk,
 
 output [3:0] phy_tx_data,
 output phy_tx_DV,
 output phy_tx_en,
 input phy_tx_clk,
 
 output phy_MDC,
 output phy_MDIO,
 output phy_rst,
 



 input AWvalid,
 input AWready,
 input [31:0] AWaddr,
 input  [2:0] AWprot,
 

 input Wvalid,
 input Wready,
 input [data_width-1 : 0] Wdata,
 input [data_width/8 -1 : 0] Wstrb,
 

 output Bvalid,
 output Bready,
 output [1:0] Bresp,
 

 input ARvalid,
 input ARready,
 input [31:0] ARaddr,
 input [2:0] ARprot,
 

 output Rvalid,
 output Rready,
 output [data_width-1 : 0]Rdata,
 output [1:0] Rresp,
 


  input  Aclk,
  input  Areset,
  output TVALID,
  
  inout [data_width -1 : 0]   Tdata,  
  inout [data_width/8 -1 : 0] Tstrb,
  
  inout [data_width/8 -1 : 0] Tkeep,
  inout Tlast
  
    );

    
    
    
    
    
endmodule