data/full_repos/permissive/146689564/whac_a_mole_v3.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:708: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'frame\' generates 4 bits.\n                                                                         : ... In instance whac_a_mole_v3.u1\nassign en = ((q == frame) & enable) ? 1:0;  \n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:716: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'frame\' generates 4 bits.\n                                                                         : ... In instance whac_a_mole_v3.u1\n    if(q == frame)  \n         ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:440: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d0: y_posi = mole_1;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:441: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_2\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d1: y_posi = mole_2;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:442: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_3\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d2: y_posi = mole_3;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:443: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_4\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d3: y_posi = mole_4;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:444: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n    default: y_posi = mole_1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:447: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  else y_posi = mole_1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:466: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n       mole_1 <= M_Y_S;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:467: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      mole_2 <= M_Y_S;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     mole_3 <= M_Y_S;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:469: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     mole_4 <= M_Y_S;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:475: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S1\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence1 <= S1;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:476: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S2\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence2 <= S2;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:477: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S3\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence3 <= S3;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:478: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S4\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence4 <= S4;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:501: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:496: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_1 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:509: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:504: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_2 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:517: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:512: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_3 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:525: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:520: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_4 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:531: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:535: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:539: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:543: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:547: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:551: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:555: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:559: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:568: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h33\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 == 7\'d51) \n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:573: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h33\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 == 7\'d51)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:578: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h34\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 < 7\'d52)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:583: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h34\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 < 7\'d52)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:640: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[5:3];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:641: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter [2:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:653: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[3:2];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:654: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter [1:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:669: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[2:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:670: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter[7:3];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:230: Operator CASE expects 2 bits on the Case expression, but Case expression\'s VARREF \'difficulty\' generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.c0\n  case(difficulty)\n  ^~~~\n%Error: data/full_repos/permissive/146689564/whac_a_mole_v3.v:60: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter.v\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter.sv\n             vga_adapter\n             vga_adapter.v\n             vga_adapter.sv\n             obj_dir/vga_adapter\n             obj_dir/vga_adapter.v\n             obj_dir/vga_adapter.sv\n%Error: data/full_repos/permissive/146689564/whac_a_mole_v3.v:88: Cannot find file containing module: \'keyboard_press_driver\'\n keyboard_press_driver KEYBOARD(\n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:139: Input port connection \'difficulty\' expects 1 bits on the pin connection, but pin connection\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3\n   .difficulty(SW[9:8]),\n    ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 48 warning(s)\n'
module hex_decoder(hex_digit, segments);
    input [3:0] hex_digit;
    output reg [6:0] segments;
   
    always @(*)
        case (hex_digit)
            4'h0: segments = 7'b100_0000;
            4'h1: segments = 7'b111_1001;
            4'h2: segments = 7'b010_0100;
            4'h3: segments = 7'b011_0000;
            4'h4: segments = 7'b001_1001;
            4'h5: segments = 7'b001_0010;
            4'h6: segments = 7'b000_0010;
            4'h7: segments = 7'b111_1000;
            4'h8: segments = 7'b000_0000;
            4'h9: segments = 7'b001_1000;
            4'hA: segments = 7'b000_1000;
            4'hB: segments = 7'b000_0011;
            4'hC: segments = 7'b100_0110;
            4'hD: segments = 7'b010_0001;
            4'hE: segments = 7'b000_0110;
            4'hF: segments = 7'b000_1110;   
            default: segments = 7'h7f;
        endcase
endmodule
module hex_decoder(hex_digit, segments);

    input [3:0] hex_digit;
    output reg [6:0] segments;
   
    always @(*)
        case (hex_digit)
            4'h0: segments = 7'b100_0000;
            4'h1: segments = 7'b111_1001;
            4'h2: segments = 7'b010_0100;
            4'h3: segments = 7'b011_0000;
            4'h4: segments = 7'b001_1001;
            4'h5: segments = 7'b001_0010;
            4'h6: segments = 7'b000_0010;
            4'h7: segments = 7'b111_1000;
            4'h8: segments = 7'b000_0000;
            4'h9: segments = 7'b001_1000;
            4'hA: segments = 7'b000_1000;
            4'hB: segments = 7'b000_0011;
            4'hC: segments = 7'b100_0110;
            4'hD: segments = 7'b010_0001;
            4'hE: segments = 7'b000_0110;
            4'hF: segments = 7'b000_1110;   
            default: segments = 7'h7f;
        endcase
endmodule