data/full_repos/permissive/108698528/mux2x.v
data/verilator_xmls/c7ac31cc-b238-405e-b63a-404f7d5f8c54.xml
module mux2x(in_a, in_b, select, out);
	parameter WIDTH = 8;

	input [WIDTH - 1:0] in_a, in_b;
	output reg [WIDTH - 1:0] out;
	input select;

	always @* begin
		if(select == 1) out = in_b;
		else out = in_a;
	end 

endmodule
module mux2x(in_a, in_b, select, out);

	parameter WIDTH = 8;

	input [WIDTH - 1:0] in_a, in_b;
	output reg [WIDTH - 1:0] out;
	input select;

	always @* begin
		if(select == 1) out = in_b;
		else out = in_a;
	end 

endmodule