data/full_repos/permissive/139213403/FPGA/front_panel_controller.v
Syntax Error
1: b"%Error: data/full_repos/permissive/139213403/FPGA/front_panel_controller.v:191: syntax error, unexpected wire, expecting '['\n  input wire [MILLIS_W-1:0] value;\n        ^~~~\n%Error: Exiting due to 1 error(s)\n"
function [COUNTER_W-1:0] millis2clocks;
		input wire [MILLIS_W-1:0] value;
		begin 
			millis2clocks = value * 1000000 / T;
		end
	endfunction
function [COUNTER_W-1:0] millis2clocks;

		input wire [MILLIS_W-1:0] value;
		begin 
			millis2clocks = value * 1000000 / T;
		end
	endfunction