data/full_repos/permissive/166661632/p5/p5/Datapath.v
1: b'%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:2: Cannot find include file: head.v\n`include "head.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166661632/p5/p5,data/full_repos/permissive/166661632/head.v\n             data/full_repos/permissive/166661632/p5/p5,data/full_repos/permissive/166661632/head.v.v\n             data/full_repos/permissive/166661632/p5/p5,data/full_repos/permissive/166661632/head.v.sv\n             head.v\n             head.v.v\n             head.v.sv\n             obj_dir/head.v\n             obj_dir/head.v.v\n             obj_dir/head.v.sv\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:83: Define or directive not defined: \'`fd_pc8_e\'\nassign fv1d=(fv1dctrl==`fd_pc8_e)?pc8_e:\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:83: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign fv1d=(fv1dctrl==`fd_pc8_e)?pc8_e:\n                                ^\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:84: Define or directive not defined: \'`fd_oth_e\'\n    (fv1dctrl==`fd_oth_e)?oth_e:\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:85: Define or directive not defined: \'`fd_ao_m\'\n    (fv1dctrl==`fd_ao_m)?ao_m:\n               ^~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:86: Define or directive not defined: \'`fd_pc8_m\'\n    (fv1dctrl==`fd_pc8_m)?pc8_m:\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:88: Define or directive not defined: \'`fd_pc8_e\'\nassign fv2d=(fv2dctrl==`fd_pc8_e)?pc8_e:\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:88: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign fv2d=(fv2dctrl==`fd_pc8_e)?pc8_e:\n                                ^\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:89: Define or directive not defined: \'`fd_oth_e\'\n    (fv2dctrl==`fd_oth_e)?oth_e:\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:90: Define or directive not defined: \'`fd_ao_m\'\n    (fv2dctrl==`fd_ao_m)?ao_m:\n               ^~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:91: Define or directive not defined: \'`fd_pc8_m\'\n    (fv2dctrl==`fd_pc8_m)?pc8_m:\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:93: Define or directive not defined: \'`regdst_rd\'\nassign regaddr=(regdst==`regdst_rd)?rd:\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:93: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign regaddr=(regdst==`regdst_rd)?rd:\n                                  ^\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:94: Define or directive not defined: \'`regdst_rt\'\n     (regdst==`regdst_rt)?rt:\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:96: Define or directive not defined: \'`oth_ext\'\nassign other=(otherctrl==`oth_ext)?extout:32\'hffffffff;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:96: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign other=(otherctrl==`oth_ext)?extout:32\'hffffffff;\n                                 ^\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:103: Define or directive not defined: \'`falue_pc8_m\'\nassign faluae=(faluaectrl==`falue_pc8_m)?pc8_m:\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:103: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign faluae=(faluaectrl==`falue_pc8_m)?pc8_m:\n                                       ^\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:104: Define or directive not defined: \'`falue_ao_m\'\n      (faluaectrl==`falue_ao_m)?ao_m:\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:105: Define or directive not defined: \'`falue_wd_w\'\n      (faluaectrl==`falue_wd_w)?regdata:\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:108: Define or directive not defined: \'`falue_pc8_m\'\nassign falube=(falubectrl==`falue_pc8_m)?pc8_m:\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:108: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign falube=(falubectrl==`falue_pc8_m)?pc8_m:\n                                       ^\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:109: Define or directive not defined: \'`falue_ao_m\'\n      (falubectrl==`falue_ao_m)?ao_m:\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:110: Define or directive not defined: \'`falue_wd_w\'\n      (falubectrl==`falue_wd_w)?regdata:\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:112: Define or directive not defined: \'`alusrc_oth\'\nassign malub=(alusrc==`alusrc_oth)?oth_e:falube;  \n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:112: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign malub=(alusrc==`alusrc_oth)?oth_e:falube;  \n                                 ^\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:114: Define or directive not defined: \'`other\'\nassign newres_e=(res_e==`other)?`alu:res_e;\n                        ^~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:114: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign newres_e=(res_e==`other)?`alu:res_e;\n                              ^\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:114: Define or directive not defined: \'`alu\'\nassign newres_e=(res_e==`other)?`alu:res_e;\n                                ^~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:127: Define or directive not defined: \'`memtoreg_ao\'\nassign regdata=(memtoreg==`memtoreg_ao)?ao_w:\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:127: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign regdata=(memtoreg==`memtoreg_ao)?ao_w:\n                                      ^\n%Error: data/full_repos/permissive/166661632/p5/p5/Datapath.v:128: Define or directive not defined: \'`memtoreg_dr\'\n     (memtoreg==`memtoreg_dr)?dr_w:\n                ^~~~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n'
module Datapath(clk,clr,stall,abus,resbus,forwardbus,res_d,
					branch,npcop,extop,regdst,otherctrl,aluop,alusrc,memwrite,memtoreg,regwrite,isbeq,
					instr_d,instr_e,instr_m,instr_w);


output [31:0] instr_d,instr_e,instr_m,instr_w;
output [39:0] abus;
output [8:0] resbus;
input clk,clr,stall;
input [12:0] forwardbus;
input [2:0]res_d;


input branch,memwrite,regwrite,isbeq;
input [1:0] npcop,extop,regdst,otherctrl,memtoreg,alusrc;
input  [2:0] aluop;


wire [4:0] a1_d,a2_d,a1_e,a2_e,a2_m,a3_e,a3_m,a3_w;
assign abus[4:0]=a1_d;
assign abus[9:5]=a2_d;
assign abus[14:10]=a1_e;
assign abus[19:15]=a2_e;
assign abus[24:20]=a2_m;
assign abus[29:25]=a3_e;
assign abus[34:30]=a3_m;
assign abus[39:35]=a3_w;

wire[2:0] res_e,res_m,res_w;
assign resbus[2:0]=res_e;
assign resbus[5:3]=res_m;
assign resbus[8:6]=res_w;

wire [2:0] fv1dctrl,fv2dctrl,faluaectrl,falubectrl;
wire fdmmctrl;
assign fv1dctrl=forwardbus[2:0];
assign fv2dctrl=forwardbus[5:3];
assign faluaectrl=forwardbus[8:6];
assign falubectrl=forwardbus[11:9];
assign fdmmctrl=forwardbus[12];


wire [31:0] regdata,fv1d,fv2d,other,faluae,falube,malub,fdmm;
wire [4:0] regaddr;

wire [31:0] instr_i,pc8_i;
wire branchlogic,zero;

wire [31:0] pc8_d;
wire [31:0]rd1,rd2,pc4_d,extout,npcout,zero32;

wire [31:0] v1_e,v2_e,pc8_e,oth_e,ao_e;
wire [31:0]v2_m,ao_m,pc8_m,dr_m;

wire [31:0] ao_w, dr_w,pc8_w;

IFU ifu(.clk(clk),.clr(clr),.stall(stall),.branch(branchlogic),.npcout(npcout),.instr(instr_i),.pc8(pc8_i));
assign zero=zero32[0];
assign branchlogic=(branch&isbeq&zero)|(branch&~isbeq);

Dpipe dpipe(.clk(clk),.clr(clr),.en(stall),
				.instr_i(instr_i),.pc8_i(pc8_i),
				.instr_d(instr_d),.pc8_d(pc8_d));


wire [4:0] rs,rt,rd;
wire [15:0] imm;
assign rs=instr_d[25:21];
assign rt=instr_d[20:16];
assign rd=instr_d[15:11];
assign imm=instr_d[15:0];
assign a1_d=rs;
assign a2_d=rt;

assign pc4_d=pc8_d-4;
GRF grf(.clk(clk),.clr(clr),.we(regwrite),.a1(rs),.a2(rt),.a3(a3_w),.wd(regdata),.rd1(rd1),.rd2(rd2));
NPC npc(.pc4(pc4_d),.extout(extout),.instr(instr_d),.rd1(fv1d),.npcop(npcop),.npcout(npcout));
EXT ext(.imm(imm),.extop(extop),.extout(extout));
CMP cmp(.a(fv1d),.b(fv2d),.cmpout(zero32));

assign fv1d=(fv1dctrl==`fd_pc8_e)?pc8_e:
				(fv1dctrl==`fd_oth_e)?oth_e:
				(fv1dctrl==`fd_ao_m)?ao_m:
				(fv1dctrl==`fd_pc8_m)?pc8_m:
				rd1;
assign fv2d=(fv2dctrl==`fd_pc8_e)?pc8_e:
				(fv2dctrl==`fd_oth_e)?oth_e:
				(fv2dctrl==`fd_ao_m)?ao_m:
				(fv2dctrl==`fd_pc8_m)?pc8_m:
				rd2;
assign regaddr=(regdst==`regdst_rd)?rd:
					(regdst==`regdst_rt)?rt:
					5'd31;
assign other=(otherctrl==`oth_ext)?extout:32'hffffffff;

Epipe epipe (.clk(clk),.clr(clr|stall),
		 .res_d(res_d),.instr_d(instr_d),.v1_d(fv1d),.v2_d(fv2d),.a1_d(a1_d),.a2_d(a2_d),.a3_d(regaddr),.oth_d(other),.pc8_d(pc8_d),
		 .res_e(res_e),.instr_e(instr_e),.v1_e(v1_e),.v2_e(v2_e),.a1_e(a1_e),.a2_e(a2_e),.a3_e(a3_e),.oth_e(oth_e),.pc8_e(pc8_e));

ALU alu(.a(faluae),.b(malub),.aluop(aluop),.ao(ao_e));	
assign faluae=(faluaectrl==`falue_pc8_m)?pc8_m:
				  (faluaectrl==`falue_ao_m)?ao_m:
				  (faluaectrl==`falue_wd_w)?regdata:
				  v1_e;

assign falube=(falubectrl==`falue_pc8_m)?pc8_m:
				  (falubectrl==`falue_ao_m)?ao_m:
				  (falubectrl==`falue_wd_w)?regdata:
				  v2_e;		
assign malub=(alusrc==`alusrc_oth)?oth_e:falube;		
wire [2:0]newres_e;
assign newres_e=(res_e==`other)?`alu:res_e;

Mpipe mpipe(.clk(clk),.clr(clr),
				.res_e(newres_e),.instr_e(instr_e),.v2_e(falube),.a2_e(a2_e),.ao_e(ao_e),.pc8_e(pc8_e),.a3_e(a3_e),
				.res_m(res_m),.instr_m(instr_m),.v2_m(v2_m),.a2_m(a2_m),.ao_m(ao_m),.pc8_m(pc8_m),.a3_m(a3_m));

DM dm(.clk(clk),.clr(clr),.we(memwrite),.addr(ao_m),.wd(fdmm),.dr(dr_m));
assign fdmm=(fdmmctrl==1)?regdata:v2_m;

Wpipe wpipe(.clk(clk),.clr(clr),
				.res_m(res_m),.instr_m(instr_m),.ao_m(ao_m),.dr_m(dr_m),.pc8_m(pc8_m),.a3_m(a3_m),
				.res_w(res_w),.instr_w(instr_w),.ao_w(ao_w),.dr_w(dr_w),.pc8_w(pc8_w),.a3_w(a3_w));

assign regdata=(memtoreg==`memtoreg_ao)?ao_w:
					(memtoreg==`memtoreg_dr)?dr_w:
					pc8_w;
endmodule
module Datapath(clk,clr,stall,abus,resbus,forwardbus,res_d,
					branch,npcop,extop,regdst,otherctrl,aluop,alusrc,memwrite,memtoreg,regwrite,isbeq,
					instr_d,instr_e,instr_m,instr_w);



output [31:0] instr_d,instr_e,instr_m,instr_w;
output [39:0] abus;
output [8:0] resbus;
input clk,clr,stall;
input [12:0] forwardbus;
input [2:0]res_d;


input branch,memwrite,regwrite,isbeq;
input [1:0] npcop,extop,regdst,otherctrl,memtoreg,alusrc;
input  [2:0] aluop;


wire [4:0] a1_d,a2_d,a1_e,a2_e,a2_m,a3_e,a3_m,a3_w;
assign abus[4:0]=a1_d;
assign abus[9:5]=a2_d;
assign abus[14:10]=a1_e;
assign abus[19:15]=a2_e;
assign abus[24:20]=a2_m;
assign abus[29:25]=a3_e;
assign abus[34:30]=a3_m;
assign abus[39:35]=a3_w;

wire[2:0] res_e,res_m,res_w;
assign resbus[2:0]=res_e;
assign resbus[5:3]=res_m;
assign resbus[8:6]=res_w;

wire [2:0] fv1dctrl,fv2dctrl,faluaectrl,falubectrl;
wire fdmmctrl;
assign fv1dctrl=forwardbus[2:0];
assign fv2dctrl=forwardbus[5:3];
assign faluaectrl=forwardbus[8:6];
assign falubectrl=forwardbus[11:9];
assign fdmmctrl=forwardbus[12];


wire [31:0] regdata,fv1d,fv2d,other,faluae,falube,malub,fdmm;
wire [4:0] regaddr;

wire [31:0] instr_i,pc8_i;
wire branchlogic,zero;

wire [31:0] pc8_d;
wire [31:0]rd1,rd2,pc4_d,extout,npcout,zero32;

wire [31:0] v1_e,v2_e,pc8_e,oth_e,ao_e;
wire [31:0]v2_m,ao_m,pc8_m,dr_m;

wire [31:0] ao_w, dr_w,pc8_w;

IFU ifu(.clk(clk),.clr(clr),.stall(stall),.branch(branchlogic),.npcout(npcout),.instr(instr_i),.pc8(pc8_i));
assign zero=zero32[0];
assign branchlogic=(branch&isbeq&zero)|(branch&~isbeq);

Dpipe dpipe(.clk(clk),.clr(clr),.en(stall),
				.instr_i(instr_i),.pc8_i(pc8_i),
				.instr_d(instr_d),.pc8_d(pc8_d));


wire [4:0] rs,rt,rd;
wire [15:0] imm;
assign rs=instr_d[25:21];
assign rt=instr_d[20:16];
assign rd=instr_d[15:11];
assign imm=instr_d[15:0];
assign a1_d=rs;
assign a2_d=rt;

assign pc4_d=pc8_d-4;
GRF grf(.clk(clk),.clr(clr),.we(regwrite),.a1(rs),.a2(rt),.a3(a3_w),.wd(regdata),.rd1(rd1),.rd2(rd2));
NPC npc(.pc4(pc4_d),.extout(extout),.instr(instr_d),.rd1(fv1d),.npcop(npcop),.npcout(npcout));
EXT ext(.imm(imm),.extop(extop),.extout(extout));
CMP cmp(.a(fv1d),.b(fv2d),.cmpout(zero32));

assign fv1d=(fv1dctrl==`fd_pc8_e)?pc8_e:
				(fv1dctrl==`fd_oth_e)?oth_e:
				(fv1dctrl==`fd_ao_m)?ao_m:
				(fv1dctrl==`fd_pc8_m)?pc8_m:
				rd1;
assign fv2d=(fv2dctrl==`fd_pc8_e)?pc8_e:
				(fv2dctrl==`fd_oth_e)?oth_e:
				(fv2dctrl==`fd_ao_m)?ao_m:
				(fv2dctrl==`fd_pc8_m)?pc8_m:
				rd2;
assign regaddr=(regdst==`regdst_rd)?rd:
					(regdst==`regdst_rt)?rt:
					5'd31;
assign other=(otherctrl==`oth_ext)?extout:32'hffffffff;

Epipe epipe (.clk(clk),.clr(clr|stall),
		 .res_d(res_d),.instr_d(instr_d),.v1_d(fv1d),.v2_d(fv2d),.a1_d(a1_d),.a2_d(a2_d),.a3_d(regaddr),.oth_d(other),.pc8_d(pc8_d),
		 .res_e(res_e),.instr_e(instr_e),.v1_e(v1_e),.v2_e(v2_e),.a1_e(a1_e),.a2_e(a2_e),.a3_e(a3_e),.oth_e(oth_e),.pc8_e(pc8_e));

ALU alu(.a(faluae),.b(malub),.aluop(aluop),.ao(ao_e));	
assign faluae=(faluaectrl==`falue_pc8_m)?pc8_m:
				  (faluaectrl==`falue_ao_m)?ao_m:
				  (faluaectrl==`falue_wd_w)?regdata:
				  v1_e;

assign falube=(falubectrl==`falue_pc8_m)?pc8_m:
				  (falubectrl==`falue_ao_m)?ao_m:
				  (falubectrl==`falue_wd_w)?regdata:
				  v2_e;		
assign malub=(alusrc==`alusrc_oth)?oth_e:falube;		
wire [2:0]newres_e;
assign newres_e=(res_e==`other)?`alu:res_e;

Mpipe mpipe(.clk(clk),.clr(clr),
				.res_e(newres_e),.instr_e(instr_e),.v2_e(falube),.a2_e(a2_e),.ao_e(ao_e),.pc8_e(pc8_e),.a3_e(a3_e),
				.res_m(res_m),.instr_m(instr_m),.v2_m(v2_m),.a2_m(a2_m),.ao_m(ao_m),.pc8_m(pc8_m),.a3_m(a3_m));

DM dm(.clk(clk),.clr(clr),.we(memwrite),.addr(ao_m),.wd(fdmm),.dr(dr_m));
assign fdmm=(fdmmctrl==1)?regdata:v2_m;

Wpipe wpipe(.clk(clk),.clr(clr),
				.res_m(res_m),.instr_m(instr_m),.ao_m(ao_m),.dr_m(dr_m),.pc8_m(pc8_m),.a3_m(a3_m),
				.res_w(res_w),.instr_w(instr_w),.ao_w(ao_w),.dr_w(dr_w),.pc8_w(pc8_w),.a3_w(a3_w));

assign regdata=(memtoreg==`memtoreg_ao)?ao_w:
					(memtoreg==`memtoreg_dr)?dr_w:
					pc8_w;
endmodule