data/full_repos/permissive/211316121/lab5_3/74LS175.v
data/verilator_xmls/93f50b06-d055-44ed-bd4b-14b8d3f620cf.xml
module Top_74LS175(
    input [4:0] sw,
    input clkstd,
    output [7:0] led
);

wire clk;

CLKDIV top_div(clkstd,clk);

LS175 top_175(sw[3:0],clk,sw[4],led[3:0],led[7:4]);

endmodule
module Top_74LS175(
    input [4:0] sw,
    input clkstd,
    output [7:0] led
);


wire clk;

CLKDIV top_div(clkstd,clk);

LS175 top_175(sw[3:0],clk,sw[4],led[3:0],led[7:4]);

endmodule