data/full_repos/permissive/111433415/verilog/03_combinacionales/03-1_florencio/florencio.v
data/verilator_xmls/132d4b06-1559-4b27-99c9-8cde0894c082.xml
module florencio (
    output reg f,
    input wire a,
    input wire b,
    input wire c,
    input wire d
    );

    always @(a, b, c, d)
    begin
        f = 1;

        if (a && b && c && d)
            f = 0;
        if (!a && !b && !c && !d)
            f = 0;
        if (b && !c)
            f = 0;
        if (a && c)
            if (!b && !d)
                f = 0;

        if ((c || d || !a) && !b)
            f = 0;
    end
endmodule
module florencio (
    output reg f,
    input wire a,
    input wire b,
    input wire c,
    input wire d
    );


    always @(a, b, c, d)
    begin
        f = 1;

        if (a && b && c && d)
            f = 0;
        if (!a && !b && !c && !d)
            f = 0;
        if (b && !c)
            f = 0;
        if (a && c)
            if (!b && !d)
                f = 0;

        if ((c || d || !a) && !b)
            f = 0;
    end
endmodule