data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:47: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("flip-flops_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:48: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #180 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:54: Unsupported: fork statements\n    initial fork\n            ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #5    cl = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #20   cl = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #140  pr = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #160  pr = 1;\n        ^\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:62: Unsupported: fork statements\n    initial fork\n            ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #20    j = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #40    j = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #60    k = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #80    k = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #100   j = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #100   k = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #160   j = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #160   k = 0;\n        ^\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:74: Unsupported: fork statements\n    initial fork\n            ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #20    d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #40    d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #80    d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #140   d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #10 ck = ~ck;\n        ^\n%Error: Exiting due to 5 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();

    reg ck = 0;
    reg j = 0;
    reg k = 0;
    reg d = 0;
    wire s;
    wire r;
    wire t;
    reg cl = 1;
    reg pr = 1;
    wire qsr, qjk, qd, qt;


    srff uut_srff(ck, s, r, cl, pr, qsr);
    jkff uut_jkff(ck, j, k, cl, pr, qjk);
    dff uut_dff(ck, d, cl, pr, qd);
    tff uut_tff(ck, t, cl, pr, qt);


    assign s = j;
    assign r = k;
    assign t = d;


    initial begin

        $dumpfile("flip-flops_tb.vcd");
        $dumpvars(0, test);

        #180 $finish;
    end


    initial fork
        #5    cl = 0;
        #20   cl = 1;
        #140  pr = 0;
        #160  pr = 1;
    join


    initial fork
        #20    j = 1;
        #40    j = 0;
        #60    k = 1;
        #80    k = 0;
        #100   j = 1;
        #100   k = 1;
        #160   j = 0;
        #160   k = 0;
    join


    initial fork
        #20    d = 1;
        #40    d = 0;
        #80    d = 1;
        #140   d = 0;
    join



    always
        #10 ck = ~ck;

endmodule
module test ();


    reg ck = 0;
    reg j = 0;
    reg k = 0;
    reg d = 0;
    wire s;
    wire r;
    wire t;
    reg cl = 1;
    reg pr = 1;
    wire qsr, qjk, qd, qt;


    srff uut_srff(ck, s, r, cl, pr, qsr);
    jkff uut_jkff(ck, j, k, cl, pr, qjk);
    dff uut_dff(ck, d, cl, pr, qd);
    tff uut_tff(ck, t, cl, pr, qt);


    assign s = j;
    assign r = k;
    assign t = d;


    initial begin

        $dumpfile("flip-flops_tb.vcd");
        $dumpvars(0, test);

        #180 $finish;
    end


    initial fork
        #5    cl = 0;
        #20   cl = 1;
        #140  pr = 0;
        #160  pr = 1;
    join


    initial fork
        #20    j = 1;
        #40    j = 0;
        #60    k = 1;
        #80    k = 0;
        #100   j = 1;
        #100   k = 1;
        #160   j = 0;
        #160   k = 0;
    join


    initial fork
        #20    d = 1;
        #40    d = 0;
        #80    d = 1;
        #140   d = 0;
    join



    always
        #10 ck = ~ck;

endmodule