data/full_repos/permissive/216654561/bfm.v
 line:113: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/216654561/bfm.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #200 rst_n = 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/216654561/bfm.v:91: Unsupported: Ignoring delay on this delayed statement.\n  always #10 sys_clk = !sys_clk;\n         ^\n%Error: data/full_repos/permissive/216654561/bfm.v:100: syntax error, unexpected \'@\'\n    wait(rst_n == 0) @(posedge sys_clk);\n                     ^\n%Error: data/full_repos/permissive/216654561/bfm.v:100: Unsupported: wait statements\n    wait(rst_n == 0) @(posedge sys_clk);\n    ^~~~\n%Error: data/full_repos/permissive/216654561/bfm.v:101: syntax error, unexpected \'@\'\n    wait(rst_n == 1) @(posedge sys_clk);\n                     ^\n%Error: data/full_repos/permissive/216654561/bfm.v:101: Unsupported: wait statements\n    wait(rst_n == 1) @(posedge sys_clk);\n    ^~~~\n%Error: data/full_repos/permissive/216654561/bfm.v:133: Unsupported: fork statements\n       fork\n       ^~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bfm_block_tb
(
);







parameter C_NUM_REG                      = 64;
parameter C_SLV_DWIDTH                   = 64;








  reg                                       rst_n;
  reg                                       sys_clk;
  integer                                   number_of_bytes;
  integer                                   i;
  integer                                   j;
  reg        [C_SLV_DWIDTH-1 : 0]           Data;
  reg        [`ADDR_BUS_WIDTH-1 : 0]        Addr;
  reg        [`RESP_BUS_WIDTH-1 : 0]        response;




  bfm_block
    dut(.sys_reset(rst_n),.sys_clk(sys_clk));





  initial begin
         rst_n = 1'b0;
    #`RESET_PERIOD rst_n = 1'b1;
  end





  initial sys_clk = 1'b0;
  always #`CLOCK_PERIOD sys_clk = !sys_clk;





  initial
  begin

    wait(rst_n == 0) @(posedge sys_clk);
    wait(rst_n == 1) @(posedge sys_clk);
   
    $display("----------------------------------------------------");
    $display("Full Registers write");
    $display("----------------------------------------------------");
    number_of_bytes = (C_SLV_DWIDTH/8);
    for( i = 0 ; i <64; i = i+1) 
	begin
      for(j = 0 ; j < number_of_bytes ; j = j+1)
        Data[j*8 +: 8] = j+(i*number_of_bytes);
      Addr = `BASE_ADDR + `REG_OFFSET + i*number_of_bytes;
      $display("Writing to Register addr=0x%h",Addr, " data=0x%h",Data);
      AXI_WRITE(Addr,Data , response);
    end
    for( i = 0 ; i <64; i = i+1)
	begin
      for(j=0 ; j < number_of_bytes ; j = j+1)
        Data[j*8 +: 8] = j+(i*number_of_bytes);
      Addr = `BASE_ADDR + `REG_OFFSET + i*number_of_bytes;
      
    end
end





  task automatic AXI_WRITE;
     input [`ADDR_BUS_WIDTH-1 : 0] address;
     input [C_SLV_DWIDTH-1 : 0]    data;
     output[`RESP_BUS_WIDTH-1 : 0] response;
     begin
       fork
          dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.SEND_WRITE_ADDRESS(address,data);
          dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.RECEIVE_WRITE_RESPONSE(response);
       join
       CHECK_RESPONSE_OKAY(response);
     end
  endtask

  







  task automatic CHECK_RESPONSE_OKAY;
    input [`RESP_BUS_WIDTH-1:0] response;
     begin
      if (response !== `RESPONSE_OKAY)
	  begin
        $display("TESTBENCH FAILED! Response is not OKAY", response);
        $stop;
      end
    end
  endtask
 
endmodule
module bfm_block_tb
(
);








parameter C_NUM_REG                      = 64;
parameter C_SLV_DWIDTH                   = 64;








  reg                                       rst_n;
  reg                                       sys_clk;
  integer                                   number_of_bytes;
  integer                                   i;
  integer                                   j;
  reg        [C_SLV_DWIDTH-1 : 0]           Data;
  reg        [`ADDR_BUS_WIDTH-1 : 0]        Addr;
  reg        [`RESP_BUS_WIDTH-1 : 0]        response;




  bfm_block
    dut(.sys_reset(rst_n),.sys_clk(sys_clk));





  initial begin
         rst_n = 1'b0;
    #`RESET_PERIOD rst_n = 1'b1;
  end





  initial sys_clk = 1'b0;
  always #`CLOCK_PERIOD sys_clk = !sys_clk;





  initial
  begin

    wait(rst_n == 0) @(posedge sys_clk);
    wait(rst_n == 1) @(posedge sys_clk);
   
    $display("----------------------------------------------------");
    $display("Full Registers write");
    $display("----------------------------------------------------");
    number_of_bytes = (C_SLV_DWIDTH/8);
    for( i = 0 ; i <64; i = i+1) 
	begin
      for(j = 0 ; j < number_of_bytes ; j = j+1)
        Data[j*8 +: 8] = j+(i*number_of_bytes);
      Addr = `BASE_ADDR + `REG_OFFSET + i*number_of_bytes;
      $display("Writing to Register addr=0x%h",Addr, " data=0x%h",Data);
      AXI_WRITE(Addr,Data , response);
    end
    for( i = 0 ; i <64; i = i+1)
	begin
      for(j=0 ; j < number_of_bytes ; j = j+1)
        Data[j*8 +: 8] = j+(i*number_of_bytes);
      Addr = `BASE_ADDR + `REG_OFFSET + i*number_of_bytes;
      
    end
end





  task automatic AXI_WRITE;
     input [`ADDR_BUS_WIDTH-1 : 0] address;
     input [C_SLV_DWIDTH-1 : 0]    data;
     output[`RESP_BUS_WIDTH-1 : 0] response;
     begin
       fork
          dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.SEND_WRITE_ADDRESS(address,data);
          dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.RECEIVE_WRITE_RESPONSE(response);
       join
       CHECK_RESPONSE_OKAY(response);
     end
  endtask

  







  task automatic CHECK_RESPONSE_OKAY;
    input [`RESP_BUS_WIDTH-1:0] response;
     begin
      if (response !== `RESPONSE_OKAY)
	  begin
        $display("TESTBENCH FAILED! Response is not OKAY", response);
        $stop;
      end
    end
  endtask
 
endmodule