data/full_repos/permissive/135795492/project/tb1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135795492/project/tb1.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135795492/project/tb1.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135795492/project/tb1.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135795492/project/tb1.v:74: Unsupported: Ignoring delay on this delayed statement.\n   always #2 clk=~clk;\n          ^\n%Error: data/full_repos/permissive/135795492/project/tb1.v:42: Cannot find file containing module: \'top\'\n top uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/135795492/project,data/full_repos/permissive/135795492/top\n             data/full_repos/permissive/135795492/project,data/full_repos/permissive/135795492/top.v\n             data/full_repos/permissive/135795492/project,data/full_repos/permissive/135795492/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb1;


	reg clk;
	reg reset_fifo;
	reg [5:0] sw;
	reg scale_sch_we;
	reg fwd_inv_we;


	wire full;
	wire empty;
	wire [5:0] rgb;
	wire hsync;
	wire vsync;


	top uut (
		.clk(clk), 
		.reset_fifo(reset_fifo), 
		.full(full), 
		.empty(empty), 
		.sw(sw), 
		.rgb(rgb), 
		.hsync(hsync), 
		.vsync(vsync), 
		.scale_sch_we(scale_sch_we), 
		.fwd_inv_we(fwd_inv_we)
	);

	initial begin

		clk = 0;
		reset_fifo = 0;
		sw = 6'b110011;
		scale_sch_we = 0;
		fwd_inv_we = 0;
		#100;
		scale_sch_we = 1;
		fwd_inv_we = 1;
		#100;
		scale_sch_we = 0;
		fwd_inv_we = 0;

		#100;
        


	end
   always #2 clk=~clk;
endmodule
module tb1;



	reg clk;
	reg reset_fifo;
	reg [5:0] sw;
	reg scale_sch_we;
	reg fwd_inv_we;


	wire full;
	wire empty;
	wire [5:0] rgb;
	wire hsync;
	wire vsync;


	top uut (
		.clk(clk), 
		.reset_fifo(reset_fifo), 
		.full(full), 
		.empty(empty), 
		.sw(sw), 
		.rgb(rgb), 
		.hsync(hsync), 
		.vsync(vsync), 
		.scale_sch_we(scale_sch_we), 
		.fwd_inv_we(fwd_inv_we)
	);

	initial begin

		clk = 0;
		reset_fifo = 0;
		sw = 6'b110011;
		scale_sch_we = 0;
		fwd_inv_we = 0;
		#100;
		scale_sch_we = 1;
		fwd_inv_we = 1;
		#100;
		scale_sch_we = 0;
		fwd_inv_we = 0;

		#100;
        


	end
   always #2 clk=~clk;
endmodule