data/full_repos/permissive/129155059/proyecto-02/memory/memory_synth.v
 line:74: before: "*"
data/verilator_xmls/b4801f5a-9d87-4387-ab66-12d70e073d79.xml
module memory_synth(CLK, ENB, sRead, sWrite, addressRead, addressWrite, inputData, outputData);
  (* src = "memory_synth.v:16" *)
  wire [2:0] _000_;
  (* src = "memory_synth.v:16" *)
  wire [7:0] _001_;
  wire _002_;
  wire _003_;
  wire _004_;
  wire _005_;
  wire _006_;
  wire _007_;
  wire _008_;
  wire _009_;
  wire _010_;
  wire _011_;
  wire _012_;
  wire _013_;
  wire _014_;
  wire _015_;
  wire _016_;
  wire [7:0] _017_;
  wire [7:0] _018_;
  wire [7:0] _019_;
  wire [7:0] _020_;
  wire [7:0] _021_;
  wire [7:0] _022_;
  wire [7:0] _023_;
  wire [7:0] _024_;
  wire _025_;
  wire _026_;
  wire _027_;
  wire _028_;
  wire _029_;
  wire _030_;
  wire _031_;
  wire _032_;
  wire [7:0] _033_;
  wire [7:0] _034_;
  wire [7:0] _035_;
  wire [7:0] _036_;
  wire [7:0] _037_;
  wire [7:0] _038_;
  wire [7:0] _039_;
  wire [7:0] _040_;
  (* src = "memory_synth.v:3" *)
  input CLK;
  (* src = "memory_synth.v:4" *)
  input ENB;
  (* src = "memory_synth.v:8" *)
  input [2:0] addressRead;
  (* src = "memory_synth.v:9" *)
  input [2:0] addressWrite;
  (* src = "memory_synth.v:10" *)
  input [7:0] inputData;
  reg [7:0] \memoria[0] ;
  reg [7:0] \memoria[1] ;
  reg [7:0] \memoria[2] ;
  reg [7:0] \memoria[3] ;
  reg [7:0] \memoria[4] ;
  reg [7:0] \memoria[5] ;
  reg [7:0] \memoria[6] ;
  reg [7:0] \memoria[7] ;
  (* src = "memory_synth.v:11" *)
  output [7:0] outputData;
  reg [7:0] outputData;
  (* src = "memory_synth.v:5" *)
  input sRead;
  (* src = "memory_synth.v:6" *)
  input sWrite;
  assign _001_[0] = sWrite ? (* src = "memory_synth.v:20" *) inputData[0] : 1'bx;
  assign _001_[1] = sWrite ? (* src = "memory_synth.v:20" *) inputData[1] : 1'bx;
  assign _001_[2] = sWrite ? (* src = "memory_synth.v:20" *) inputData[2] : 1'bx;
  assign _001_[3] = sWrite ? (* src = "memory_synth.v:20" *) inputData[3] : 1'bx;
  assign _001_[4] = sWrite ? (* src = "memory_synth.v:20" *) inputData[4] : 1'bx;
  assign _001_[5] = sWrite ? (* src = "memory_synth.v:20" *) inputData[5] : 1'bx;
  assign _001_[6] = sWrite ? (* src = "memory_synth.v:20" *) inputData[6] : 1'bx;
  assign _001_[7] = sWrite ? (* src = "memory_synth.v:20" *) inputData[7] : 1'bx;
  assign _000_[0] = sWrite ? (* src = "memory_synth.v:20" *) addressWrite[0] : 1'bx;
  assign _000_[1] = sWrite ? (* src = "memory_synth.v:20" *) addressWrite[1] : 1'bx;
  assign _000_[2] = sWrite ? (* src = "memory_synth.v:20" *) addressWrite[2] : 1'bx;
  assign _017_[0] = sRead ? _024_[0] : outputData[0];
  assign _017_[1] = sRead ? _024_[1] : outputData[1];
  assign _017_[2] = sRead ? _024_[2] : outputData[2];
  assign _017_[3] = sRead ? _024_[3] : outputData[3];
  assign _017_[4] = sRead ? _024_[4] : outputData[4];
  assign _017_[5] = sRead ? _024_[5] : outputData[5];
  assign _017_[6] = sRead ? _024_[6] : outputData[6];
  assign _017_[7] = sRead ? _024_[7] : outputData[7];
  assign _024_[0] = addressRead[2] ? _019_[0] : _018_[0];
  assign _024_[1] = addressRead[2] ? _019_[1] : _018_[1];
  assign _024_[2] = addressRead[2] ? _019_[2] : _018_[2];
  assign _024_[3] = addressRead[2] ? _019_[3] : _018_[3];
  assign _024_[4] = addressRead[2] ? _019_[4] : _018_[4];
  assign _024_[5] = addressRead[2] ? _019_[5] : _018_[5];
  assign _024_[6] = addressRead[2] ? _019_[6] : _018_[6];
  assign _024_[7] = addressRead[2] ? _019_[7] : _018_[7];
  assign _018_[0] = addressRead[1] ? _021_[0] : _020_[0];
  assign _018_[1] = addressRead[1] ? _021_[1] : _020_[1];
  assign _018_[2] = addressRead[1] ? _021_[2] : _020_[2];
  assign _018_[3] = addressRead[1] ? _021_[3] : _020_[3];
  assign _018_[4] = addressRead[1] ? _021_[4] : _020_[4];
  assign _018_[5] = addressRead[1] ? _021_[5] : _020_[5];
  assign _018_[6] = addressRead[1] ? _021_[6] : _020_[6];
  assign _018_[7] = addressRead[1] ? _021_[7] : _020_[7];
  assign _019_[0] = addressRead[1] ? _023_[0] : _022_[0];
  assign _019_[1] = addressRead[1] ? _023_[1] : _022_[1];
  assign _019_[2] = addressRead[1] ? _023_[2] : _022_[2];
  assign _019_[3] = addressRead[1] ? _023_[3] : _022_[3];
  assign _019_[4] = addressRead[1] ? _023_[4] : _022_[4];
  assign _019_[5] = addressRead[1] ? _023_[5] : _022_[5];
  assign _019_[6] = addressRead[1] ? _023_[6] : _022_[6];
  assign _019_[7] = addressRead[1] ? _023_[7] : _022_[7];
  assign _020_[0] = addressRead[0] ? \memoria[1] [0] : \memoria[0] [0];
  assign _020_[1] = addressRead[0] ? \memoria[1] [1] : \memoria[0] [1];
  assign _020_[2] = addressRead[0] ? \memoria[1] [2] : \memoria[0] [2];
  assign _020_[3] = addressRead[0] ? \memoria[1] [3] : \memoria[0] [3];
  assign _020_[4] = addressRead[0] ? \memoria[1] [4] : \memoria[0] [4];
  assign _020_[5] = addressRead[0] ? \memoria[1] [5] : \memoria[0] [5];
  assign _020_[6] = addressRead[0] ? \memoria[1] [6] : \memoria[0] [6];
  assign _020_[7] = addressRead[0] ? \memoria[1] [7] : \memoria[0] [7];
  assign _021_[0] = addressRead[0] ? \memoria[3] [0] : \memoria[2] [0];
  assign _021_[1] = addressRead[0] ? \memoria[3] [1] : \memoria[2] [1];
  assign _021_[2] = addressRead[0] ? \memoria[3] [2] : \memoria[2] [2];
  assign _021_[3] = addressRead[0] ? \memoria[3] [3] : \memoria[2] [3];
  assign _021_[4] = addressRead[0] ? \memoria[3] [4] : \memoria[2] [4];
  assign _021_[5] = addressRead[0] ? \memoria[3] [5] : \memoria[2] [5];
  assign _021_[6] = addressRead[0] ? \memoria[3] [6] : \memoria[2] [6];
  assign _021_[7] = addressRead[0] ? \memoria[3] [7] : \memoria[2] [7];
  assign _022_[0] = addressRead[0] ? \memoria[5] [0] : \memoria[4] [0];
  assign _022_[1] = addressRead[0] ? \memoria[5] [1] : \memoria[4] [1];
  assign _022_[2] = addressRead[0] ? \memoria[5] [2] : \memoria[4] [2];
  assign _022_[3] = addressRead[0] ? \memoria[5] [3] : \memoria[4] [3];
  assign _022_[4] = addressRead[0] ? \memoria[5] [4] : \memoria[4] [4];
  assign _022_[5] = addressRead[0] ? \memoria[5] [5] : \memoria[4] [5];
  assign _022_[6] = addressRead[0] ? \memoria[5] [6] : \memoria[4] [6];
  assign _022_[7] = addressRead[0] ? \memoria[5] [7] : \memoria[4] [7];
  assign _023_[0] = addressRead[0] ? \memoria[7] [0] : \memoria[6] [0];
  assign _023_[1] = addressRead[0] ? \memoria[7] [1] : \memoria[6] [1];
  assign _023_[2] = addressRead[0] ? \memoria[7] [2] : \memoria[6] [2];
  assign _023_[3] = addressRead[0] ? \memoria[7] [3] : \memoria[6] [3];
  assign _023_[4] = addressRead[0] ? \memoria[7] [4] : \memoria[6] [4];
  assign _023_[5] = addressRead[0] ? \memoria[7] [5] : \memoria[6] [5];
  assign _023_[6] = addressRead[0] ? \memoria[7] [6] : \memoria[6] [6];
  assign _023_[7] = addressRead[0] ? \memoria[7] [7] : \memoria[6] [7];
  assign _033_[0] = _025_ ? _001_[0] : \memoria[0] [0];
  assign _033_[1] = _025_ ? _001_[1] : \memoria[0] [1];
  assign _033_[2] = _025_ ? _001_[2] : \memoria[0] [2];
  assign _033_[3] = _025_ ? _001_[3] : \memoria[0] [3];
  assign _033_[4] = _025_ ? _001_[4] : \memoria[0] [4];
  assign _033_[5] = _025_ ? _001_[5] : \memoria[0] [5];
  assign _033_[6] = _025_ ? _001_[6] : \memoria[0] [6];
  assign _033_[7] = _025_ ? _001_[7] : \memoria[0] [7];
  assign _034_[0] = _026_ ? _001_[0] : \memoria[1] [0];
  assign _034_[1] = _026_ ? _001_[1] : \memoria[1] [1];
  assign _034_[2] = _026_ ? _001_[2] : \memoria[1] [2];
  assign _034_[3] = _026_ ? _001_[3] : \memoria[1] [3];
  assign _034_[4] = _026_ ? _001_[4] : \memoria[1] [4];
  assign _034_[5] = _026_ ? _001_[5] : \memoria[1] [5];
  assign _034_[6] = _026_ ? _001_[6] : \memoria[1] [6];
  assign _034_[7] = _026_ ? _001_[7] : \memoria[1] [7];
  assign _035_[0] = _027_ ? _001_[0] : \memoria[2] [0];
  assign _035_[1] = _027_ ? _001_[1] : \memoria[2] [1];
  assign _035_[2] = _027_ ? _001_[2] : \memoria[2] [2];
  assign _035_[3] = _027_ ? _001_[3] : \memoria[2] [3];
  assign _035_[4] = _027_ ? _001_[4] : \memoria[2] [4];
  assign _035_[5] = _027_ ? _001_[5] : \memoria[2] [5];
  assign _035_[6] = _027_ ? _001_[6] : \memoria[2] [6];
  assign _035_[7] = _027_ ? _001_[7] : \memoria[2] [7];
  assign _036_[0] = _028_ ? _001_[0] : \memoria[3] [0];
  assign _036_[1] = _028_ ? _001_[1] : \memoria[3] [1];
  assign _036_[2] = _028_ ? _001_[2] : \memoria[3] [2];
  assign _036_[3] = _028_ ? _001_[3] : \memoria[3] [3];
  assign _036_[4] = _028_ ? _001_[4] : \memoria[3] [4];
  assign _036_[5] = _028_ ? _001_[5] : \memoria[3] [5];
  assign _036_[6] = _028_ ? _001_[6] : \memoria[3] [6];
  assign _036_[7] = _028_ ? _001_[7] : \memoria[3] [7];
  assign _037_[0] = _029_ ? _001_[0] : \memoria[4] [0];
  assign _037_[1] = _029_ ? _001_[1] : \memoria[4] [1];
  assign _037_[2] = _029_ ? _001_[2] : \memoria[4] [2];
  assign _037_[3] = _029_ ? _001_[3] : \memoria[4] [3];
  assign _037_[4] = _029_ ? _001_[4] : \memoria[4] [4];
  assign _037_[5] = _029_ ? _001_[5] : \memoria[4] [5];
  assign _037_[6] = _029_ ? _001_[6] : \memoria[4] [6];
  assign _037_[7] = _029_ ? _001_[7] : \memoria[4] [7];
  assign _038_[0] = _030_ ? _001_[0] : \memoria[5] [0];
  assign _038_[1] = _030_ ? _001_[1] : \memoria[5] [1];
  assign _038_[2] = _030_ ? _001_[2] : \memoria[5] [2];
  assign _038_[3] = _030_ ? _001_[3] : \memoria[5] [3];
  assign _038_[4] = _030_ ? _001_[4] : \memoria[5] [4];
  assign _038_[5] = _030_ ? _001_[5] : \memoria[5] [5];
  assign _038_[6] = _030_ ? _001_[6] : \memoria[5] [6];
  assign _038_[7] = _030_ ? _001_[7] : \memoria[5] [7];
  assign _039_[0] = _031_ ? _001_[0] : \memoria[6] [0];
  assign _039_[1] = _031_ ? _001_[1] : \memoria[6] [1];
  assign _039_[2] = _031_ ? _001_[2] : \memoria[6] [2];
  assign _039_[3] = _031_ ? _001_[3] : \memoria[6] [3];
  assign _039_[4] = _031_ ? _001_[4] : \memoria[6] [4];
  assign _039_[5] = _031_ ? _001_[5] : \memoria[6] [5];
  assign _039_[6] = _031_ ? _001_[6] : \memoria[6] [6];
  assign _039_[7] = _031_ ? _001_[7] : \memoria[6] [7];
  assign _040_[0] = _032_ ? _001_[0] : \memoria[7] [0];
  assign _040_[1] = _032_ ? _001_[1] : \memoria[7] [1];
  assign _040_[2] = _032_ ? _001_[2] : \memoria[7] [2];
  assign _040_[3] = _032_ ? _001_[3] : \memoria[7] [3];
  assign _040_[4] = _032_ ? _001_[4] : \memoria[7] [4];
  assign _040_[5] = _032_ ? _001_[5] : \memoria[7] [5];
  assign _040_[6] = _032_ ? _001_[6] : \memoria[7] [6];
  assign _040_[7] = _032_ ? _001_[7] : \memoria[7] [7];
  assign _014_ = ~_000_[0];
  assign _015_ = ~_000_[1];
  assign _016_ = ~_000_[2];
  always @(posedge CLK)
      \memoria[4] [0] <= _037_[0];
  always @(posedge CLK)
      \memoria[4] [1] <= _037_[1];
  always @(posedge CLK)
      \memoria[4] [2] <= _037_[2];
  always @(posedge CLK)
      \memoria[4] [3] <= _037_[3];
  always @(posedge CLK)
      \memoria[4] [4] <= _037_[4];
  always @(posedge CLK)
      \memoria[4] [5] <= _037_[5];
  always @(posedge CLK)
      \memoria[4] [6] <= _037_[6];
  always @(posedge CLK)
      \memoria[4] [7] <= _037_[7];
  always @(posedge CLK)
      \memoria[1] [0] <= _034_[0];
  always @(posedge CLK)
      \memoria[1] [1] <= _034_[1];
  always @(posedge CLK)
      \memoria[1] [2] <= _034_[2];
  always @(posedge CLK)
      \memoria[1] [3] <= _034_[3];
  always @(posedge CLK)
      \memoria[1] [4] <= _034_[4];
  always @(posedge CLK)
      \memoria[1] [5] <= _034_[5];
  always @(posedge CLK)
      \memoria[1] [6] <= _034_[6];
  always @(posedge CLK)
      \memoria[1] [7] <= _034_[7];
  always @(posedge CLK)
      \memoria[3] [0] <= _036_[0];
  always @(posedge CLK)
      \memoria[3] [1] <= _036_[1];
  always @(posedge CLK)
      \memoria[3] [2] <= _036_[2];
  always @(posedge CLK)
      \memoria[3] [3] <= _036_[3];
  always @(posedge CLK)
      \memoria[3] [4] <= _036_[4];
  always @(posedge CLK)
      \memoria[3] [5] <= _036_[5];
  always @(posedge CLK)
      \memoria[3] [6] <= _036_[6];
  always @(posedge CLK)
      \memoria[3] [7] <= _036_[7];
  always @(posedge CLK)
      \memoria[2] [0] <= _035_[0];
  always @(posedge CLK)
      \memoria[2] [1] <= _035_[1];
  always @(posedge CLK)
      \memoria[2] [2] <= _035_[2];
  always @(posedge CLK)
      \memoria[2] [3] <= _035_[3];
  always @(posedge CLK)
      \memoria[2] [4] <= _035_[4];
  always @(posedge CLK)
      \memoria[2] [5] <= _035_[5];
  always @(posedge CLK)
      \memoria[2] [6] <= _035_[6];
  always @(posedge CLK)
      \memoria[2] [7] <= _035_[7];
  always @(posedge CLK)
      \memoria[0] [0] <= _033_[0];
  always @(posedge CLK)
      \memoria[0] [1] <= _033_[1];
  always @(posedge CLK)
      \memoria[0] [2] <= _033_[2];
  always @(posedge CLK)
      \memoria[0] [3] <= _033_[3];
  always @(posedge CLK)
      \memoria[0] [4] <= _033_[4];
  always @(posedge CLK)
      \memoria[0] [5] <= _033_[5];
  always @(posedge CLK)
      \memoria[0] [6] <= _033_[6];
  always @(posedge CLK)
      \memoria[0] [7] <= _033_[7];
  always @(posedge CLK)
      \memoria[5] [0] <= _038_[0];
  always @(posedge CLK)
      \memoria[5] [1] <= _038_[1];
  always @(posedge CLK)
      \memoria[5] [2] <= _038_[2];
  always @(posedge CLK)
      \memoria[5] [3] <= _038_[3];
  always @(posedge CLK)
      \memoria[5] [4] <= _038_[4];
  always @(posedge CLK)
      \memoria[5] [5] <= _038_[5];
  always @(posedge CLK)
      \memoria[5] [6] <= _038_[6];
  always @(posedge CLK)
      \memoria[5] [7] <= _038_[7];
  always @(posedge CLK)
      \memoria[6] [0] <= _039_[0];
  always @(posedge CLK)
      \memoria[6] [1] <= _039_[1];
  always @(posedge CLK)
      \memoria[6] [2] <= _039_[2];
  always @(posedge CLK)
      \memoria[6] [3] <= _039_[3];
  always @(posedge CLK)
      \memoria[6] [4] <= _039_[4];
  always @(posedge CLK)
      \memoria[6] [5] <= _039_[5];
  always @(posedge CLK)
      \memoria[6] [6] <= _039_[6];
  always @(posedge CLK)
      \memoria[6] [7] <= _039_[7];
  always @(posedge CLK)
      \memoria[7] [0] <= _040_[0];
  always @(posedge CLK)
      \memoria[7] [1] <= _040_[1];
  always @(posedge CLK)
      \memoria[7] [2] <= _040_[2];
  always @(posedge CLK)
      \memoria[7] [3] <= _040_[3];
  always @(posedge CLK)
      \memoria[7] [4] <= _040_[4];
  always @(posedge CLK)
      \memoria[7] [5] <= _040_[5];
  always @(posedge CLK)
      \memoria[7] [6] <= _040_[6];
  always @(posedge CLK)
      \memoria[7] [7] <= _040_[7];
  always @(posedge CLK)
      outputData[0] <= _017_[0];
  always @(posedge CLK)
      outputData[1] <= _017_[1];
  always @(posedge CLK)
      outputData[2] <= _017_[2];
  always @(posedge CLK)
      outputData[3] <= _017_[3];
  always @(posedge CLK)
      outputData[4] <= _017_[4];
  always @(posedge CLK)
      outputData[5] <= _017_[5];
  always @(posedge CLK)
      outputData[6] <= _017_[6];
  always @(posedge CLK)
      outputData[7] <= _017_[7];
  assign _009_ = _015_ & _016_;
  assign _010_ = _014_ & _009_;
  assign _025_ = _010_ & sWrite;
  assign _011_ = _000_[0] & _009_;
  assign _026_ = _011_ & sWrite;
  assign _012_ = _000_[1] & _016_;
  assign _013_ = _014_ & _012_;
  assign _027_ = _013_ & sWrite;
  assign _002_ = _000_[0] & _012_;
  assign _028_ = _002_ & sWrite;
  assign _003_ = _015_ & _000_[2];
  assign _004_ = _014_ & _003_;
  assign _029_ = _004_ & sWrite;
  assign _005_ = _000_[0] & _003_;
  assign _030_ = _005_ & sWrite;
  assign _006_ = _000_[1] & _000_[2];
  assign _007_ = _014_ & _006_;
  assign _031_ = _007_ & sWrite;
  assign _008_ = _000_[0] & _006_;
  assign _032_ = _008_ & sWrite;
endmodule
module memory_synth(CLK, ENB, sRead, sWrite, addressRead, addressWrite, inputData, outputData);

  (* src = "memory_synth.v:16" *)
  wire [2:0] _000_;
  (* src = "memory_synth.v:16" *)
  wire [7:0] _001_;
  wire _002_;
  wire _003_;
  wire _004_;
  wire _005_;
  wire _006_;
  wire _007_;
  wire _008_;
  wire _009_;
  wire _010_;
  wire _011_;
  wire _012_;
  wire _013_;
  wire _014_;
  wire _015_;
  wire _016_;
  wire [7:0] _017_;
  wire [7:0] _018_;
  wire [7:0] _019_;
  wire [7:0] _020_;
  wire [7:0] _021_;
  wire [7:0] _022_;
  wire [7:0] _023_;
  wire [7:0] _024_;
  wire _025_;
  wire _026_;
  wire _027_;
  wire _028_;
  wire _029_;
  wire _030_;
  wire _031_;
  wire _032_;
  wire [7:0] _033_;
  wire [7:0] _034_;
  wire [7:0] _035_;
  wire [7:0] _036_;
  wire [7:0] _037_;
  wire [7:0] _038_;
  wire [7:0] _039_;
  wire [7:0] _040_;
  (* src = "memory_synth.v:3" *)
  input CLK;
  (* src = "memory_synth.v:4" *)
  input ENB;
  (* src = "memory_synth.v:8" *)
  input [2:0] addressRead;
  (* src = "memory_synth.v:9" *)
  input [2:0] addressWrite;
  (* src = "memory_synth.v:10" *)
  input [7:0] inputData;
  reg [7:0] \memoria[0] ;
  reg [7:0] \memoria[1] ;
  reg [7:0] \memoria[2] ;
  reg [7:0] \memoria[3] ;
  reg [7:0] \memoria[4] ;
  reg [7:0] \memoria[5] ;
  reg [7:0] \memoria[6] ;
  reg [7:0] \memoria[7] ;
  (* src = "memory_synth.v:11" *)
  output [7:0] outputData;
  reg [7:0] outputData;
  (* src = "memory_synth.v:5" *)
  input sRead;
  (* src = "memory_synth.v:6" *)
  input sWrite;
  assign _001_[0] = sWrite ? (* src = "memory_synth.v:20" *) inputData[0] : 1'bx;
  assign _001_[1] = sWrite ? (* src = "memory_synth.v:20" *) inputData[1] : 1'bx;
  assign _001_[2] = sWrite ? (* src = "memory_synth.v:20" *) inputData[2] : 1'bx;
  assign _001_[3] = sWrite ? (* src = "memory_synth.v:20" *) inputData[3] : 1'bx;
  assign _001_[4] = sWrite ? (* src = "memory_synth.v:20" *) inputData[4] : 1'bx;
  assign _001_[5] = sWrite ? (* src = "memory_synth.v:20" *) inputData[5] : 1'bx;
  assign _001_[6] = sWrite ? (* src = "memory_synth.v:20" *) inputData[6] : 1'bx;
  assign _001_[7] = sWrite ? (* src = "memory_synth.v:20" *) inputData[7] : 1'bx;
  assign _000_[0] = sWrite ? (* src = "memory_synth.v:20" *) addressWrite[0] : 1'bx;
  assign _000_[1] = sWrite ? (* src = "memory_synth.v:20" *) addressWrite[1] : 1'bx;
  assign _000_[2] = sWrite ? (* src = "memory_synth.v:20" *) addressWrite[2] : 1'bx;
  assign _017_[0] = sRead ? _024_[0] : outputData[0];
  assign _017_[1] = sRead ? _024_[1] : outputData[1];
  assign _017_[2] = sRead ? _024_[2] : outputData[2];
  assign _017_[3] = sRead ? _024_[3] : outputData[3];
  assign _017_[4] = sRead ? _024_[4] : outputData[4];
  assign _017_[5] = sRead ? _024_[5] : outputData[5];
  assign _017_[6] = sRead ? _024_[6] : outputData[6];
  assign _017_[7] = sRead ? _024_[7] : outputData[7];
  assign _024_[0] = addressRead[2] ? _019_[0] : _018_[0];
  assign _024_[1] = addressRead[2] ? _019_[1] : _018_[1];
  assign _024_[2] = addressRead[2] ? _019_[2] : _018_[2];
  assign _024_[3] = addressRead[2] ? _019_[3] : _018_[3];
  assign _024_[4] = addressRead[2] ? _019_[4] : _018_[4];
  assign _024_[5] = addressRead[2] ? _019_[5] : _018_[5];
  assign _024_[6] = addressRead[2] ? _019_[6] : _018_[6];
  assign _024_[7] = addressRead[2] ? _019_[7] : _018_[7];
  assign _018_[0] = addressRead[1] ? _021_[0] : _020_[0];
  assign _018_[1] = addressRead[1] ? _021_[1] : _020_[1];
  assign _018_[2] = addressRead[1] ? _021_[2] : _020_[2];
  assign _018_[3] = addressRead[1] ? _021_[3] : _020_[3];
  assign _018_[4] = addressRead[1] ? _021_[4] : _020_[4];
  assign _018_[5] = addressRead[1] ? _021_[5] : _020_[5];
  assign _018_[6] = addressRead[1] ? _021_[6] : _020_[6];
  assign _018_[7] = addressRead[1] ? _021_[7] : _020_[7];
  assign _019_[0] = addressRead[1] ? _023_[0] : _022_[0];
  assign _019_[1] = addressRead[1] ? _023_[1] : _022_[1];
  assign _019_[2] = addressRead[1] ? _023_[2] : _022_[2];
  assign _019_[3] = addressRead[1] ? _023_[3] : _022_[3];
  assign _019_[4] = addressRead[1] ? _023_[4] : _022_[4];
  assign _019_[5] = addressRead[1] ? _023_[5] : _022_[5];
  assign _019_[6] = addressRead[1] ? _023_[6] : _022_[6];
  assign _019_[7] = addressRead[1] ? _023_[7] : _022_[7];
  assign _020_[0] = addressRead[0] ? \memoria[1] [0] : \memoria[0] [0];
  assign _020_[1] = addressRead[0] ? \memoria[1] [1] : \memoria[0] [1];
  assign _020_[2] = addressRead[0] ? \memoria[1] [2] : \memoria[0] [2];
  assign _020_[3] = addressRead[0] ? \memoria[1] [3] : \memoria[0] [3];
  assign _020_[4] = addressRead[0] ? \memoria[1] [4] : \memoria[0] [4];
  assign _020_[5] = addressRead[0] ? \memoria[1] [5] : \memoria[0] [5];
  assign _020_[6] = addressRead[0] ? \memoria[1] [6] : \memoria[0] [6];
  assign _020_[7] = addressRead[0] ? \memoria[1] [7] : \memoria[0] [7];
  assign _021_[0] = addressRead[0] ? \memoria[3] [0] : \memoria[2] [0];
  assign _021_[1] = addressRead[0] ? \memoria[3] [1] : \memoria[2] [1];
  assign _021_[2] = addressRead[0] ? \memoria[3] [2] : \memoria[2] [2];
  assign _021_[3] = addressRead[0] ? \memoria[3] [3] : \memoria[2] [3];
  assign _021_[4] = addressRead[0] ? \memoria[3] [4] : \memoria[2] [4];
  assign _021_[5] = addressRead[0] ? \memoria[3] [5] : \memoria[2] [5];
  assign _021_[6] = addressRead[0] ? \memoria[3] [6] : \memoria[2] [6];
  assign _021_[7] = addressRead[0] ? \memoria[3] [7] : \memoria[2] [7];
  assign _022_[0] = addressRead[0] ? \memoria[5] [0] : \memoria[4] [0];
  assign _022_[1] = addressRead[0] ? \memoria[5] [1] : \memoria[4] [1];
  assign _022_[2] = addressRead[0] ? \memoria[5] [2] : \memoria[4] [2];
  assign _022_[3] = addressRead[0] ? \memoria[5] [3] : \memoria[4] [3];
  assign _022_[4] = addressRead[0] ? \memoria[5] [4] : \memoria[4] [4];
  assign _022_[5] = addressRead[0] ? \memoria[5] [5] : \memoria[4] [5];
  assign _022_[6] = addressRead[0] ? \memoria[5] [6] : \memoria[4] [6];
  assign _022_[7] = addressRead[0] ? \memoria[5] [7] : \memoria[4] [7];
  assign _023_[0] = addressRead[0] ? \memoria[7] [0] : \memoria[6] [0];
  assign _023_[1] = addressRead[0] ? \memoria[7] [1] : \memoria[6] [1];
  assign _023_[2] = addressRead[0] ? \memoria[7] [2] : \memoria[6] [2];
  assign _023_[3] = addressRead[0] ? \memoria[7] [3] : \memoria[6] [3];
  assign _023_[4] = addressRead[0] ? \memoria[7] [4] : \memoria[6] [4];
  assign _023_[5] = addressRead[0] ? \memoria[7] [5] : \memoria[6] [5];
  assign _023_[6] = addressRead[0] ? \memoria[7] [6] : \memoria[6] [6];
  assign _023_[7] = addressRead[0] ? \memoria[7] [7] : \memoria[6] [7];
  assign _033_[0] = _025_ ? _001_[0] : \memoria[0] [0];
  assign _033_[1] = _025_ ? _001_[1] : \memoria[0] [1];
  assign _033_[2] = _025_ ? _001_[2] : \memoria[0] [2];
  assign _033_[3] = _025_ ? _001_[3] : \memoria[0] [3];
  assign _033_[4] = _025_ ? _001_[4] : \memoria[0] [4];
  assign _033_[5] = _025_ ? _001_[5] : \memoria[0] [5];
  assign _033_[6] = _025_ ? _001_[6] : \memoria[0] [6];
  assign _033_[7] = _025_ ? _001_[7] : \memoria[0] [7];
  assign _034_[0] = _026_ ? _001_[0] : \memoria[1] [0];
  assign _034_[1] = _026_ ? _001_[1] : \memoria[1] [1];
  assign _034_[2] = _026_ ? _001_[2] : \memoria[1] [2];
  assign _034_[3] = _026_ ? _001_[3] : \memoria[1] [3];
  assign _034_[4] = _026_ ? _001_[4] : \memoria[1] [4];
  assign _034_[5] = _026_ ? _001_[5] : \memoria[1] [5];
  assign _034_[6] = _026_ ? _001_[6] : \memoria[1] [6];
  assign _034_[7] = _026_ ? _001_[7] : \memoria[1] [7];
  assign _035_[0] = _027_ ? _001_[0] : \memoria[2] [0];
  assign _035_[1] = _027_ ? _001_[1] : \memoria[2] [1];
  assign _035_[2] = _027_ ? _001_[2] : \memoria[2] [2];
  assign _035_[3] = _027_ ? _001_[3] : \memoria[2] [3];
  assign _035_[4] = _027_ ? _001_[4] : \memoria[2] [4];
  assign _035_[5] = _027_ ? _001_[5] : \memoria[2] [5];
  assign _035_[6] = _027_ ? _001_[6] : \memoria[2] [6];
  assign _035_[7] = _027_ ? _001_[7] : \memoria[2] [7];
  assign _036_[0] = _028_ ? _001_[0] : \memoria[3] [0];
  assign _036_[1] = _028_ ? _001_[1] : \memoria[3] [1];
  assign _036_[2] = _028_ ? _001_[2] : \memoria[3] [2];
  assign _036_[3] = _028_ ? _001_[3] : \memoria[3] [3];
  assign _036_[4] = _028_ ? _001_[4] : \memoria[3] [4];
  assign _036_[5] = _028_ ? _001_[5] : \memoria[3] [5];
  assign _036_[6] = _028_ ? _001_[6] : \memoria[3] [6];
  assign _036_[7] = _028_ ? _001_[7] : \memoria[3] [7];
  assign _037_[0] = _029_ ? _001_[0] : \memoria[4] [0];
  assign _037_[1] = _029_ ? _001_[1] : \memoria[4] [1];
  assign _037_[2] = _029_ ? _001_[2] : \memoria[4] [2];
  assign _037_[3] = _029_ ? _001_[3] : \memoria[4] [3];
  assign _037_[4] = _029_ ? _001_[4] : \memoria[4] [4];
  assign _037_[5] = _029_ ? _001_[5] : \memoria[4] [5];
  assign _037_[6] = _029_ ? _001_[6] : \memoria[4] [6];
  assign _037_[7] = _029_ ? _001_[7] : \memoria[4] [7];
  assign _038_[0] = _030_ ? _001_[0] : \memoria[5] [0];
  assign _038_[1] = _030_ ? _001_[1] : \memoria[5] [1];
  assign _038_[2] = _030_ ? _001_[2] : \memoria[5] [2];
  assign _038_[3] = _030_ ? _001_[3] : \memoria[5] [3];
  assign _038_[4] = _030_ ? _001_[4] : \memoria[5] [4];
  assign _038_[5] = _030_ ? _001_[5] : \memoria[5] [5];
  assign _038_[6] = _030_ ? _001_[6] : \memoria[5] [6];
  assign _038_[7] = _030_ ? _001_[7] : \memoria[5] [7];
  assign _039_[0] = _031_ ? _001_[0] : \memoria[6] [0];
  assign _039_[1] = _031_ ? _001_[1] : \memoria[6] [1];
  assign _039_[2] = _031_ ? _001_[2] : \memoria[6] [2];
  assign _039_[3] = _031_ ? _001_[3] : \memoria[6] [3];
  assign _039_[4] = _031_ ? _001_[4] : \memoria[6] [4];
  assign _039_[5] = _031_ ? _001_[5] : \memoria[6] [5];
  assign _039_[6] = _031_ ? _001_[6] : \memoria[6] [6];
  assign _039_[7] = _031_ ? _001_[7] : \memoria[6] [7];
  assign _040_[0] = _032_ ? _001_[0] : \memoria[7] [0];
  assign _040_[1] = _032_ ? _001_[1] : \memoria[7] [1];
  assign _040_[2] = _032_ ? _001_[2] : \memoria[7] [2];
  assign _040_[3] = _032_ ? _001_[3] : \memoria[7] [3];
  assign _040_[4] = _032_ ? _001_[4] : \memoria[7] [4];
  assign _040_[5] = _032_ ? _001_[5] : \memoria[7] [5];
  assign _040_[6] = _032_ ? _001_[6] : \memoria[7] [6];
  assign _040_[7] = _032_ ? _001_[7] : \memoria[7] [7];
  assign _014_ = ~_000_[0];
  assign _015_ = ~_000_[1];
  assign _016_ = ~_000_[2];
  always @(posedge CLK)
      \memoria[4] [0] <= _037_[0];
  always @(posedge CLK)
      \memoria[4] [1] <= _037_[1];
  always @(posedge CLK)
      \memoria[4] [2] <= _037_[2];
  always @(posedge CLK)
      \memoria[4] [3] <= _037_[3];
  always @(posedge CLK)
      \memoria[4] [4] <= _037_[4];
  always @(posedge CLK)
      \memoria[4] [5] <= _037_[5];
  always @(posedge CLK)
      \memoria[4] [6] <= _037_[6];
  always @(posedge CLK)
      \memoria[4] [7] <= _037_[7];
  always @(posedge CLK)
      \memoria[1] [0] <= _034_[0];
  always @(posedge CLK)
      \memoria[1] [1] <= _034_[1];
  always @(posedge CLK)
      \memoria[1] [2] <= _034_[2];
  always @(posedge CLK)
      \memoria[1] [3] <= _034_[3];
  always @(posedge CLK)
      \memoria[1] [4] <= _034_[4];
  always @(posedge CLK)
      \memoria[1] [5] <= _034_[5];
  always @(posedge CLK)
      \memoria[1] [6] <= _034_[6];
  always @(posedge CLK)
      \memoria[1] [7] <= _034_[7];
  always @(posedge CLK)
      \memoria[3] [0] <= _036_[0];
  always @(posedge CLK)
      \memoria[3] [1] <= _036_[1];
  always @(posedge CLK)
      \memoria[3] [2] <= _036_[2];
  always @(posedge CLK)
      \memoria[3] [3] <= _036_[3];
  always @(posedge CLK)
      \memoria[3] [4] <= _036_[4];
  always @(posedge CLK)
      \memoria[3] [5] <= _036_[5];
  always @(posedge CLK)
      \memoria[3] [6] <= _036_[6];
  always @(posedge CLK)
      \memoria[3] [7] <= _036_[7];
  always @(posedge CLK)
      \memoria[2] [0] <= _035_[0];
  always @(posedge CLK)
      \memoria[2] [1] <= _035_[1];
  always @(posedge CLK)
      \memoria[2] [2] <= _035_[2];
  always @(posedge CLK)
      \memoria[2] [3] <= _035_[3];
  always @(posedge CLK)
      \memoria[2] [4] <= _035_[4];
  always @(posedge CLK)
      \memoria[2] [5] <= _035_[5];
  always @(posedge CLK)
      \memoria[2] [6] <= _035_[6];
  always @(posedge CLK)
      \memoria[2] [7] <= _035_[7];
  always @(posedge CLK)
      \memoria[0] [0] <= _033_[0];
  always @(posedge CLK)
      \memoria[0] [1] <= _033_[1];
  always @(posedge CLK)
      \memoria[0] [2] <= _033_[2];
  always @(posedge CLK)
      \memoria[0] [3] <= _033_[3];
  always @(posedge CLK)
      \memoria[0] [4] <= _033_[4];
  always @(posedge CLK)
      \memoria[0] [5] <= _033_[5];
  always @(posedge CLK)
      \memoria[0] [6] <= _033_[6];
  always @(posedge CLK)
      \memoria[0] [7] <= _033_[7];
  always @(posedge CLK)
      \memoria[5] [0] <= _038_[0];
  always @(posedge CLK)
      \memoria[5] [1] <= _038_[1];
  always @(posedge CLK)
      \memoria[5] [2] <= _038_[2];
  always @(posedge CLK)
      \memoria[5] [3] <= _038_[3];
  always @(posedge CLK)
      \memoria[5] [4] <= _038_[4];
  always @(posedge CLK)
      \memoria[5] [5] <= _038_[5];
  always @(posedge CLK)
      \memoria[5] [6] <= _038_[6];
  always @(posedge CLK)
      \memoria[5] [7] <= _038_[7];
  always @(posedge CLK)
      \memoria[6] [0] <= _039_[0];
  always @(posedge CLK)
      \memoria[6] [1] <= _039_[1];
  always @(posedge CLK)
      \memoria[6] [2] <= _039_[2];
  always @(posedge CLK)
      \memoria[6] [3] <= _039_[3];
  always @(posedge CLK)
      \memoria[6] [4] <= _039_[4];
  always @(posedge CLK)
      \memoria[6] [5] <= _039_[5];
  always @(posedge CLK)
      \memoria[6] [6] <= _039_[6];
  always @(posedge CLK)
      \memoria[6] [7] <= _039_[7];
  always @(posedge CLK)
      \memoria[7] [0] <= _040_[0];
  always @(posedge CLK)
      \memoria[7] [1] <= _040_[1];
  always @(posedge CLK)
      \memoria[7] [2] <= _040_[2];
  always @(posedge CLK)
      \memoria[7] [3] <= _040_[3];
  always @(posedge CLK)
      \memoria[7] [4] <= _040_[4];
  always @(posedge CLK)
      \memoria[7] [5] <= _040_[5];
  always @(posedge CLK)
      \memoria[7] [6] <= _040_[6];
  always @(posedge CLK)
      \memoria[7] [7] <= _040_[7];
  always @(posedge CLK)
      outputData[0] <= _017_[0];
  always @(posedge CLK)
      outputData[1] <= _017_[1];
  always @(posedge CLK)
      outputData[2] <= _017_[2];
  always @(posedge CLK)
      outputData[3] <= _017_[3];
  always @(posedge CLK)
      outputData[4] <= _017_[4];
  always @(posedge CLK)
      outputData[5] <= _017_[5];
  always @(posedge CLK)
      outputData[6] <= _017_[6];
  always @(posedge CLK)
      outputData[7] <= _017_[7];
  assign _009_ = _015_ & _016_;
  assign _010_ = _014_ & _009_;
  assign _025_ = _010_ & sWrite;
  assign _011_ = _000_[0] & _009_;
  assign _026_ = _011_ & sWrite;
  assign _012_ = _000_[1] & _016_;
  assign _013_ = _014_ & _012_;
  assign _027_ = _013_ & sWrite;
  assign _002_ = _000_[0] & _012_;
  assign _028_ = _002_ & sWrite;
  assign _003_ = _015_ & _000_[2];
  assign _004_ = _014_ & _003_;
  assign _029_ = _004_ & sWrite;
  assign _005_ = _000_[0] & _003_;
  assign _030_ = _005_ & sWrite;
  assign _006_ = _000_[1] & _000_[2];
  assign _007_ = _014_ & _006_;
  assign _031_ = _007_ & sWrite;
  assign _008_ = _000_[0] & _006_;
  assign _032_ = _008_ & sWrite;
endmodule