data/full_repos/permissive/157696705/brainfuck computer/Instruction_memory.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: computer,data/full_repos/permissive/157696705\n        ... Looked in:\n             data/full_repos/permissive/157696705/brainfuck/computer,data/full_repos/permissive/157696705\n             data/full_repos/permissive/157696705/brainfuck/computer,data/full_repos/permissive/157696705.v\n             data/full_repos/permissive/157696705/brainfuck/computer,data/full_repos/permissive/157696705.sv\n             computer,data/full_repos/permissive/157696705\n             computer,data/full_repos/permissive/157696705.v\n             computer,data/full_repos/permissive/157696705.sv\n             obj_dir/computer,data/full_repos/permissive/157696705\n             obj_dir/computer,data/full_repos/permissive/157696705.v\n             obj_dir/computer,data/full_repos/permissive/157696705.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/157696705/brainfuck\n%Error: Cannot find file containing module: computer/Instruction_memory.v\n%Error: Exiting due to 3 error(s)\n'
module Instruction_memory(
    input       [3:0]   inst_in,
    input               RW,
    input       [9:0]   ADR,
    output  reg [3:0]   inst_out
);

reg [3:0]   register[1023:0];

always @(posedge RW or negedge RW)
begin
  if(RW)
  begin
    inst_out[3:0] <= register[ADR[9:0]][3:0];
  end
  else
  begin
    register[ADR[9:0]][3:0] <= inst_in[3:0];
  end
end
endmodule
module Instruction_memory(
    input       [3:0]   inst_in,
    input               RW,
    input       [9:0]   ADR,
    output  reg [3:0]   inst_out
);


reg [3:0]   register[1023:0];

always @(posedge RW or negedge RW)
begin
  if(RW)
  begin
    inst_out[3:0] <= register[ADR[9:0]][3:0];
  end
  else
  begin
    register[ADR[9:0]][3:0] <= inst_in[3:0];
  end
end
endmodule