data/full_repos/permissive/174323821/hdl/cpu/j68/j68_addsub_32.v
data/verilator_xmls/9191b72c-2800-4933-9d88-166b337767e7.xml
module j68_addsub_32
(
    input         add_sub,
    input  [31:0] dataa,
    input  [31:0] datab,
    output        cout,
    output [31:0] result
);




    wire [32:0] w_result;

    assign w_result = (add_sub) ? { 1'b0, dataa } + { 1'b0, datab }
                                : { 1'b0, dataa } - { 1'b0, datab };

    assign cout   = ~w_result[32];
    assign result = w_result[31:0];

endmodule
module j68_addsub_32
(
    input         add_sub,
    input  [31:0] dataa,
    input  [31:0] datab,
    output        cout,
    output [31:0] result
);





    wire [32:0] w_result;

    assign w_result = (add_sub) ? { 1'b0, dataa } + { 1'b0, datab }
                                : { 1'b0, dataa } - { 1'b0, datab };

    assign cout   = ~w_result[32];
    assign result = w_result[31:0];

endmodule