data/full_repos/permissive/111993107/src/hms.v
data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml
module MERGE_NODE #(parameter                           E_LOG = 2,
                    parameter                           DATW  = 64,
                    parameter                           KEYW  = 32)
                   (input  wire                         CLK,
                    input  wire                         RST,
                    input  wire                         IN_FULL,
                    input  wire [(DATW<<(E_LOG-1))-1:0] DIN_A,
                    input  wire                         DINEN_A,
                    input  wire [(DATW<<(E_LOG-1))-1:0] DIN_B,
                    input  wire                         DINEN_B,
                    output wire                         FUL_A,
                    output wire                         FUL_B,
                    output wire [(DATW<<E_LOG)-1:0]     DOT,
                    output wire                         DOTEN);

  wire [(DATW<<E_LOG)-1:0] coupler_4_A_dot, coupler_4_B_dot;
  wire                     coupler_4_A_doten, coupler_4_B_doten;

  COUPLER #(E_LOG, DATW)
  coupler_4_A(CLK, RST, FUL_A, DIN_A, DINEN_A, coupler_4_A_dot, coupler_4_A_doten);
  COUPLER #(E_LOG, DATW)
  coupler_4_B(CLK, RST, FUL_B, DIN_B, DINEN_B, coupler_4_B_dot, coupler_4_B_doten);
  
  MERGE_LOGIC #(E_LOG, DATW, KEYW)
  merge_logic(CLK, RST, IN_FULL, coupler_4_A_doten, coupler_4_A_dot, coupler_4_B_doten, coupler_4_B_dot, 
              FUL_A, FUL_B, DOT, DOTEN);

endmodule
module MERGE_NODE #(parameter                           E_LOG = 2,
                    parameter                           DATW  = 64,
                    parameter                           KEYW  = 32)
                   (input  wire                         CLK,
                    input  wire                         RST,
                    input  wire                         IN_FULL,
                    input  wire [(DATW<<(E_LOG-1))-1:0] DIN_A,
                    input  wire                         DINEN_A,
                    input  wire [(DATW<<(E_LOG-1))-1:0] DIN_B,
                    input  wire                         DINEN_B,
                    output wire                         FUL_A,
                    output wire                         FUL_B,
                    output wire [(DATW<<E_LOG)-1:0]     DOT,
                    output wire                         DOTEN);


  wire [(DATW<<E_LOG)-1:0] coupler_4_A_dot, coupler_4_B_dot;
  wire                     coupler_4_A_doten, coupler_4_B_doten;

  COUPLER #(E_LOG, DATW)
  coupler_4_A(CLK, RST, FUL_A, DIN_A, DINEN_A, coupler_4_A_dot, coupler_4_A_doten);
  COUPLER #(E_LOG, DATW)
  coupler_4_B(CLK, RST, FUL_B, DIN_B, DINEN_B, coupler_4_B_dot, coupler_4_B_doten);
  
  MERGE_LOGIC #(E_LOG, DATW, KEYW)
  merge_logic(CLK, RST, IN_FULL, coupler_4_A_doten, coupler_4_A_dot, coupler_4_B_doten, coupler_4_B_dot, 
              FUL_A, FUL_B, DOT, DOTEN);

endmodule