data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v
'utf-8' codec can't decode byte 0xbd in position 1847: invalid start byte
1: b'%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:33: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v.v\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:45: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] ex_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus] ex_wd,\n                       ^\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:47: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] ex_wdata,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:47: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ex_wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:49: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] ex_aluop,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:50: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ex_mem_addr,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:51: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ex_reg2,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:55: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire div_started_i,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:58: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`CSRWriteTypeBus] ex_csr_reg_we,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:58: Define or directive not defined: \'`CSRWriteTypeBus\'\n input wire[`CSRWriteTypeBus] ex_csr_reg_we,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:59: Define or directive not defined: \'`CSRAddrBus\'\n input wire[`CSRAddrBus] ex_csr_reg_addr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:60: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ex_csr_reg_data,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:63: Define or directive not defined: \'`PhyAddrBus\'\n input wire [`PhyAddrBus]ex_mem_phy_addr,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:65: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire ex_data_tlb_w_exception,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:69: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`ExceptionTypeBus] ex_excepttype,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:69: Define or directive not defined: \'`ExceptionTypeBus\'\n input wire[`ExceptionTypeBus] ex_excepttype,\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:71: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] ex_current_inst_address,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:71: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ex_current_inst_address,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:75: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[`RegAddrBus] mem_wd,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:75: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] mem_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:77: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] mem_wdata,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:77: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] mem_wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:79: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus] mem_aluop,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:80: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] mem_mem_addr,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:81: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] mem_reg2,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:84: Define or directive not defined: \'`CSRWriteTypeBus\'\n output reg[`CSRWriteTypeBus] mem_csr_reg_we,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:85: Define or directive not defined: \'`CSRAddrBus\'\n output reg[`CSRAddrBus] mem_csr_reg_addr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:86: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] mem_csr_reg_data,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:89: Define or directive not defined: \'`ExceptionTypeBus\'\n output reg[`ExceptionTypeBus] mem_excepttype,\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:91: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] mem_current_inst_address,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:91: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] mem_current_inst_address,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:96: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [`PhyAddrBus]mem_mem_phy_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:96: Define or directive not defined: \'`PhyAddrBus\'\n output reg [`PhyAddrBus]mem_mem_phy_addr,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:98: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg mem_data_tlb_w_exception,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:101: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[1:0] cnt_o,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:102: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg div_started_o\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:108: Define or directive not defined: \'`RstEnable\'\n  if(rst_n == `RstEnable)\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:110: Define or directive not defined: \'`NOPRegAddr\'\n   mem_wd <= `NOPRegAddr;\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:111: Define or directive not defined: \'`WriteDisable\'\n   mem_wreg <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:112: Define or directive not defined: \'`ZeroWord\'\n   mem_wdata <= `ZeroWord; \n                ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:114: Define or directive not defined: \'`EXE_NOP_OP\'\n   mem_aluop <= `EXE_NOP_OP;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:115: Define or directive not defined: \'`ZeroWord\'\n   mem_mem_addr <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:116: Define or directive not defined: \'`ZeroWord\'\n   mem_reg2 <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:118: Define or directive not defined: \'`CSRWriteDisable\'\n   mem_csr_reg_we <= `CSRWriteDisable;\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:119: Define or directive not defined: \'`NOPRegAddr\'\n   mem_csr_reg_addr <= `NOPRegAddr;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:120: Define or directive not defined: \'`ZeroWord\'\n   mem_csr_reg_data <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:122: Define or directive not defined: \'`ZeroWord\'\n   mem_excepttype <= `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:123: Define or directive not defined: \'`NotInDelaySlot\'\n   mem_is_in_delayslot <= `NotInDelaySlot;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/ex_mem.v:124: Define or directive not defined: \'`ZeroWord\'\n   mem_current_inst_address <= `ZeroWord;\n                               ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ex_mem(

	input wire clk,
	input wire rst_n,


	input wire[5:0] stall,
	input wire flush,
	

	input wire[`RegAddrBus] ex_wd,
	input wire ex_wreg,
	input wire[`RegBus] ex_wdata,

	input wire[`AluOpBus] ex_aluop,
	input wire[`RegBus] ex_mem_addr,
	input wire[`RegBus] ex_reg2,


	input wire[1:0] cnt_i,
	input wire div_started_i,


	input wire[`CSRWriteTypeBus] ex_csr_reg_we,
	input wire[`CSRAddrBus] ex_csr_reg_addr,
	input wire[`RegBus] ex_csr_reg_data,


	input wire [`PhyAddrBus]ex_mem_phy_addr,
	input wire ex_data_tlb_r_exception,
	input wire ex_data_tlb_w_exception,



	input wire[`ExceptionTypeBus] ex_excepttype,
	input wire ex_is_in_delayslot,
	input wire[`RegBus] ex_current_inst_address,
	input wire ex_not_stall,
	

	output reg[`RegAddrBus] mem_wd,
	output reg mem_wreg,
	output reg[`RegBus] mem_wdata,

	output reg[`AluOpBus] mem_aluop,
	output reg[`RegBus] mem_mem_addr,
	output reg[`RegBus] mem_reg2,


	output reg[`CSRWriteTypeBus] mem_csr_reg_we,
	output reg[`CSRAddrBus] mem_csr_reg_addr,
	output reg[`RegBus] mem_csr_reg_data,


	output reg[`ExceptionTypeBus] mem_excepttype,
	output reg mem_is_in_delayslot,
	output reg[`RegBus] mem_current_inst_address,
	output reg mem_not_stall,



	output reg [`PhyAddrBus]mem_mem_phy_addr,
	output reg mem_data_tlb_r_exception,
	output reg mem_data_tlb_w_exception,


	output reg[1:0] cnt_o,
	output reg div_started_o
);


	always @ (posedge clk or negedge rst_n) 
	begin
		if(rst_n == `RstEnable)
		begin
			mem_wd <= `NOPRegAddr;
			mem_wreg <= `WriteDisable;
			mem_wdata <= `ZeroWord;	
			
			mem_aluop <= `EXE_NOP_OP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2 <= `ZeroWord;

			mem_csr_reg_we <= `CSRWriteDisable;
			mem_csr_reg_addr <= `NOPRegAddr;
			mem_csr_reg_data <= `ZeroWord;

			mem_excepttype <= `ZeroWord;
			mem_is_in_delayslot <= `NotInDelaySlot;
			mem_current_inst_address <= `ZeroWord;
			mem_not_stall <= `False_v;

			mem_mem_phy_addr <= `ZeroWord;
			mem_data_tlb_r_exception <= `False_v;
			mem_data_tlb_w_exception <= `False_v;

			cnt_o <= 2'b00;
			div_started_o <= 1'b0;

		end 
		else if(flush == `Flush)
		begin
			mem_wd <= `NOPRegAddr;
			mem_wreg <= `WriteDisable;
			mem_wdata <= `ZeroWord;
			
			mem_aluop <= `EXE_NOP_OP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2 <= `ZeroWord;

			mem_csr_reg_we <= `CSRWriteDisable;
			mem_csr_reg_addr <= `NOPRegAddr;
			mem_csr_reg_data <= `ZeroWord;

			mem_excepttype <= `ZeroWord;
			mem_is_in_delayslot <= `NotInDelaySlot;
			mem_current_inst_address <= `ZeroWord;
			mem_not_stall <= `False_v;

			mem_mem_phy_addr <= `ZeroWord;
			mem_data_tlb_r_exception <= `False_v;
			mem_data_tlb_w_exception <= `False_v;

			cnt_o <= 2'b00;
			div_started_o <= 1'b0;
		end 
		else if(stall[3] == `Stop && stall[4] == `NoStop)
		begin
			mem_wd <= `NOPRegAddr;
			mem_wreg <= `WriteDisable;
			mem_wdata <= `ZeroWord;

			mem_aluop <= `EXE_NOP_OP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2 <= `ZeroWord;

			mem_csr_reg_we <= `CSRWriteDisable;
			mem_csr_reg_addr <= `NOPRegAddr;
			mem_csr_reg_data <= `ZeroWord;

			mem_excepttype <= `ZeroWord;
			mem_is_in_delayslot <= `NotInDelaySlot;
			mem_current_inst_address <= `ZeroWord;
			mem_not_stall <= `False_v;

			mem_mem_phy_addr <= `ZeroWord;
			mem_data_tlb_r_exception <= `False_v;
			mem_data_tlb_w_exception <= `False_v;

			cnt_o <= cnt_i;
			div_started_o <= div_started_i;
		end
		else if(stall[3] == `NoStop)
		begin
			mem_wd <= ex_wd;
			mem_wreg <= ex_wreg;
			mem_wdata <= ex_wdata;

			mem_aluop <= ex_aluop;
			mem_mem_addr <= ex_mem_addr;
			mem_reg2 <= ex_reg2;
			
			mem_csr_reg_we <= ex_csr_reg_we;
			mem_csr_reg_addr <= ex_csr_reg_addr;
			mem_csr_reg_data <= ex_csr_reg_data;

			mem_excepttype <= ex_excepttype;
			mem_is_in_delayslot <= ex_is_in_delayslot;
			mem_current_inst_address <= ex_current_inst_address;
			mem_not_stall <= ex_not_stall;

			mem_mem_phy_addr <= ex_mem_phy_addr;
			mem_data_tlb_r_exception <= ex_data_tlb_r_exception;
			mem_data_tlb_w_exception <= ex_data_tlb_w_exception;

			cnt_o <= 2'b00;
			div_started_o <= 1'b0;
		end
		else
		begin
			cnt_o <= cnt_i;
			div_started_o <= div_started_i;
		end
	end
			

endmodule
module ex_mem(

	input wire clk,
	input wire rst_n,


	input wire[5:0] stall,
	input wire flush,
	

	input wire[`RegAddrBus] ex_wd,
	input wire ex_wreg,
	input wire[`RegBus] ex_wdata,

	input wire[`AluOpBus] ex_aluop,
	input wire[`RegBus] ex_mem_addr,
	input wire[`RegBus] ex_reg2,


	input wire[1:0] cnt_i,
	input wire div_started_i,


	input wire[`CSRWriteTypeBus] ex_csr_reg_we,
	input wire[`CSRAddrBus] ex_csr_reg_addr,
	input wire[`RegBus] ex_csr_reg_data,


	input wire [`PhyAddrBus]ex_mem_phy_addr,
	input wire ex_data_tlb_r_exception,
	input wire ex_data_tlb_w_exception,



	input wire[`ExceptionTypeBus] ex_excepttype,
	input wire ex_is_in_delayslot,
	input wire[`RegBus] ex_current_inst_address,
	input wire ex_not_stall,
	

	output reg[`RegAddrBus] mem_wd,
	output reg mem_wreg,
	output reg[`RegBus] mem_wdata,

	output reg[`AluOpBus] mem_aluop,
	output reg[`RegBus] mem_mem_addr,
	output reg[`RegBus] mem_reg2,


	output reg[`CSRWriteTypeBus] mem_csr_reg_we,
	output reg[`CSRAddrBus] mem_csr_reg_addr,
	output reg[`RegBus] mem_csr_reg_data,


	output reg[`ExceptionTypeBus] mem_excepttype,
	output reg mem_is_in_delayslot,
	output reg[`RegBus] mem_current_inst_address,
	output reg mem_not_stall,



	output reg [`PhyAddrBus]mem_mem_phy_addr,
	output reg mem_data_tlb_r_exception,
	output reg mem_data_tlb_w_exception,


	output reg[1:0] cnt_o,
	output reg div_started_o
);



	always @ (posedge clk or negedge rst_n) 
	begin
		if(rst_n == `RstEnable)
		begin
			mem_wd <= `NOPRegAddr;
			mem_wreg <= `WriteDisable;
			mem_wdata <= `ZeroWord;	
			
			mem_aluop <= `EXE_NOP_OP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2 <= `ZeroWord;

			mem_csr_reg_we <= `CSRWriteDisable;
			mem_csr_reg_addr <= `NOPRegAddr;
			mem_csr_reg_data <= `ZeroWord;

			mem_excepttype <= `ZeroWord;
			mem_is_in_delayslot <= `NotInDelaySlot;
			mem_current_inst_address <= `ZeroWord;
			mem_not_stall <= `False_v;

			mem_mem_phy_addr <= `ZeroWord;
			mem_data_tlb_r_exception <= `False_v;
			mem_data_tlb_w_exception <= `False_v;

			cnt_o <= 2'b00;
			div_started_o <= 1'b0;

		end 
		else if(flush == `Flush)
		begin
			mem_wd <= `NOPRegAddr;
			mem_wreg <= `WriteDisable;
			mem_wdata <= `ZeroWord;
			
			mem_aluop <= `EXE_NOP_OP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2 <= `ZeroWord;

			mem_csr_reg_we <= `CSRWriteDisable;
			mem_csr_reg_addr <= `NOPRegAddr;
			mem_csr_reg_data <= `ZeroWord;

			mem_excepttype <= `ZeroWord;
			mem_is_in_delayslot <= `NotInDelaySlot;
			mem_current_inst_address <= `ZeroWord;
			mem_not_stall <= `False_v;

			mem_mem_phy_addr <= `ZeroWord;
			mem_data_tlb_r_exception <= `False_v;
			mem_data_tlb_w_exception <= `False_v;

			cnt_o <= 2'b00;
			div_started_o <= 1'b0;
		end 
		else if(stall[3] == `Stop && stall[4] == `NoStop)
		begin
			mem_wd <= `NOPRegAddr;
			mem_wreg <= `WriteDisable;
			mem_wdata <= `ZeroWord;

			mem_aluop <= `EXE_NOP_OP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2 <= `ZeroWord;

			mem_csr_reg_we <= `CSRWriteDisable;
			mem_csr_reg_addr <= `NOPRegAddr;
			mem_csr_reg_data <= `ZeroWord;

			mem_excepttype <= `ZeroWord;
			mem_is_in_delayslot <= `NotInDelaySlot;
			mem_current_inst_address <= `ZeroWord;
			mem_not_stall <= `False_v;

			mem_mem_phy_addr <= `ZeroWord;
			mem_data_tlb_r_exception <= `False_v;
			mem_data_tlb_w_exception <= `False_v;

			cnt_o <= cnt_i;
			div_started_o <= div_started_i;
		end
		else if(stall[3] == `NoStop)
		begin
			mem_wd <= ex_wd;
			mem_wreg <= ex_wreg;
			mem_wdata <= ex_wdata;

			mem_aluop <= ex_aluop;
			mem_mem_addr <= ex_mem_addr;
			mem_reg2 <= ex_reg2;
			
			mem_csr_reg_we <= ex_csr_reg_we;
			mem_csr_reg_addr <= ex_csr_reg_addr;
			mem_csr_reg_data <= ex_csr_reg_data;

			mem_excepttype <= ex_excepttype;
			mem_is_in_delayslot <= ex_is_in_delayslot;
			mem_current_inst_address <= ex_current_inst_address;
			mem_not_stall <= ex_not_stall;

			mem_mem_phy_addr <= ex_mem_phy_addr;
			mem_data_tlb_r_exception <= ex_data_tlb_r_exception;
			mem_data_tlb_w_exception <= ex_data_tlb_w_exception;

			cnt_o <= 2'b00;
			div_started_o <= 1'b0;
		end
		else
		begin
			cnt_o <= cnt_i;
			div_started_o <= div_started_i;
		end
	end
			

endmodule