data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:26: Multiple top level modules\n                                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                          : ... Top module \'$_DFF_N_\'\nmodule  \\$_DFF_N_   (input D, C, output Q);    FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .R(1\'b0)); endmodule\n        ^~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_P_\'\nmodule  \\$_DFF_P_   (input D, C, output Q);    FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .R(1\'b0)); endmodule\n        ^~~~~~~~~\n                                                                                                          : ... Top module \'$_DFFE_NP_\'\nmodule  \\$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1\'b0)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFFE_PP_\'\nmodule  \\$_DFFE_PP_ (input D, C, E, output Q); FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1\'b0)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_NN0_\'\nmodule  \\$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .CLR(!R)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_NP0_\'\nmodule  \\$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .CLR( R)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_PN0_\'\nmodule  \\$_DFF_PN0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .CLR(!R)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_PP0_\'\nmodule  \\$_DFF_PP0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .CLR( R)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_NN1_\'\nmodule  \\$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .PRE(!R)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_NP1_\'\nmodule  \\$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .PRE( R)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_PN1_\'\nmodule  \\$_DFF_PN1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .PRE(!R)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_PP1_\'\nmodule  \\$_DFF_PP1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .PRE( R)); endmodule\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:39: Cannot find file containing module: \'FDPE\'\nmodule  \\$_DFF_PP1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .PRE( R)); endmodule\n                                               ^~~~\n        ... Looked in:\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx,data/full_repos/permissive/200142067/FDPE\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx,data/full_repos/permissive/200142067/FDPE.v\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx,data/full_repos/permissive/200142067/FDPE.sv\n             FDPE\n             FDPE.v\n             FDPE.sv\n             obj_dir/FDPE\n             obj_dir/FDPE.v\n             obj_dir/FDPE.sv\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:38: Cannot find file containing module: \'FDPE\'\nmodule  \\$_DFF_PN1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .PRE(!R)); endmodule\n                                               ^~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:37: Cannot find file containing module: \'FDPE_1\'\nmodule  \\$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .PRE( R)); endmodule\n                                               ^~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:36: Cannot find file containing module: \'FDPE_1\'\nmodule  \\$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .PRE(!R)); endmodule\n                                               ^~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:34: Cannot find file containing module: \'FDCE\'\nmodule  \\$_DFF_PP0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .CLR( R)); endmodule\n                                               ^~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:33: Cannot find file containing module: \'FDCE\'\nmodule  \\$_DFF_PN0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .CLR(!R)); endmodule\n                                               ^~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:32: Cannot find file containing module: \'FDCE_1\'\nmodule  \\$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .CLR( R)); endmodule\n                                               ^~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:31: Cannot find file containing module: \'FDCE_1\'\nmodule  \\$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .CLR(!R)); endmodule\n                                               ^~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:29: Cannot find file containing module: \'FDRE\'\nmodule  \\$_DFFE_PP_ (input D, C, E, output Q); FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1\'b0)); endmodule\n                                               ^~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:28: Cannot find file containing module: \'FDRE_1\'\nmodule  \\$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1\'b0)); endmodule\n                                               ^~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:26: Cannot find file containing module: \'FDRE\'\nmodule  \\$_DFF_P_   (input D, C, output Q);    FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .R(1\'b0)); endmodule\n                                               ^~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/ff_map.v:25: Cannot find file containing module: \'FDRE_1\'\nmodule  \\$_DFF_N_   (input D, C, output Q);    FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1\'b1), .R(1\'b0)); endmodule\n                                               ^~~~~~\n%Error: Exiting due to 12 error(s), 1 warning(s)\n'
module  \$_DFF_PN0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
module  \$_DFF_PN0_ (input D, C, R, output Q);
 FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule