data/full_repos/permissive/147690299/lab/17_comb_hex/rtl/seven_seg_N.sv
 line:32 column:27: Illegal character "'"
1: b"%Error: data/full_repos/permissive/147690299/lab/17_comb_hex/rtl/seven_seg_N.sv:16: Cannot find file containing module: 'seven_seg_digit'\n            seven_seg_digit dd ( .dig (dig[i]), .hex (seg[i]) );\n            ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147690299/lab/17_comb_hex/rtl,data/full_repos/permissive/147690299/seven_seg_digit\n             data/full_repos/permissive/147690299/lab/17_comb_hex/rtl,data/full_repos/permissive/147690299/seven_seg_digit.v\n             data/full_repos/permissive/147690299/lab/17_comb_hex/rtl,data/full_repos/permissive/147690299/seven_seg_digit.sv\n             seven_seg_digit\n             seven_seg_digit.v\n             seven_seg_digit.sv\n             obj_dir/seven_seg_digit\n             obj_dir/seven_seg_digit.v\n             obj_dir/seven_seg_digit.sv\n%Error: Exiting due to 1 error(s)\n"
module seven_seg_N
#(
    parameter DIGITS = 6
)(
    input  [4*DIGITS-1:0]      data,
    output [  DIGITS-1:0][7:0] seg
);
    wire [DIGITS-1:0][3:0] dig = data;



    genvar i;
    generate
        for (i = 0; i < DIGITS; i=i+1 ) begin : segment
            seven_seg_digit dd ( .dig (dig[i]), .hex (seg[i]) );
        end
    endgenerate

endmodule
module seven_seg_N
#(
    parameter DIGITS = 6
)(
    input  [4*DIGITS-1:0]      data,
    output [  DIGITS-1:0][7:0] seg
);

    wire [DIGITS-1:0][3:0] dig = data;



    genvar i;
    generate
        for (i = 0; i < DIGITS; i=i+1 ) begin : segment
            seven_seg_digit dd ( .dig (dig[i]), .hex (seg[i]) );
        end
    endgenerate

endmodule