data/full_repos/permissive/20270692/labs/lab5/mult_2_2_4.v
1: b'%Error: data/full_repos/permissive/20270692/labs/lab5/mult_2_2_4.v:5: Cannot find include file: half_adder.v\n`include "half_adder.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab5,data/full_repos/permissive/20270692/half_adder.v\n             data/full_repos/permissive/20270692/labs/lab5,data/full_repos/permissive/20270692/half_adder.v.v\n             data/full_repos/permissive/20270692/labs/lab5,data/full_repos/permissive/20270692/half_adder.v.sv\n             half_adder.v\n             half_adder.v.v\n             half_adder.v.sv\n             obj_dir/half_adder.v\n             obj_dir/half_adder.v.v\n             obj_dir/half_adder.v.sv\n%Error: Exiting due to 1 error(s)\n'
module mult_2_2_4(A0, A1, B0, B1, C0, C1, C2, C3);

  input A0, A1, B0, B1;

  output C0, C1, C2, C3;
  wire C0, C1, C2, C3;

  wire W0, W1, W2, W3;

  assign C0=B0&A0;
  assign W0=A0&B1;
  assign W1=A1&B0;
  assign W3=A1&B1;

  half_adder HA0 (W0, W1, C1, W2);
  half_adder HA1 (W3, W2, C2, C3);

endmodule
module mult_2_2_4(A0, A1, B0, B1, C0, C1, C2, C3);


  input A0, A1, B0, B1;

  output C0, C1, C2, C3;
  wire C0, C1, C2, C3;

  wire W0, W1, W2, W3;

  assign C0=B0&A0;
  assign W0=A0&B1;
  assign W1=A1&B0;
  assign W3=A1&B1;

  half_adder HA0 (W0, W1, C1, W2);
  half_adder HA1 (W3, W2, C2, C3);

endmodule