data/full_repos/permissive/143278/ivltests/tern7.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tern7.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (ref !== a) begin\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tern7.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tern7.v:57: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a !== 1\'b1) begin\n      ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg b, c, d, e;
   wire a = b ? c : (d&e);

   reg [4:0] tmp;
   reg	     ref;
   initial begin

      for (tmp = 0 ;  tmp < 16 ;  tmp = tmp + 1) begin
	 b <= tmp[0];
	 c <= tmp[1];
	 d <= tmp[2];
	 e <= tmp[3];
	 ref = tmp[0] ? tmp[1] : (tmp[2]&tmp[3]);

	 #1 if (ref !== a) begin
	    $display("FAILED -- a=%b, b=%b, c=%b, d=%b, e=%b",
		     a, b, c, d, e);
	    $finish;
	 end
      end

      b <= 0;
      c <= 1;
      d <= 1;
      e <= 0;
      #1 if (a !== 1'b0) begin
	 $display("FAILED (1)");
	 $finish;
      end

      e <= 1;
      #1 if (a !== 1'b1) begin
	 $display("FAILED (2)");
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg b, c, d, e;
   wire a = b ? c : (d&e);

   reg [4:0] tmp;
   reg	     ref;
   initial begin

      for (tmp = 0 ;  tmp < 16 ;  tmp = tmp + 1) begin
	 b <= tmp[0];
	 c <= tmp[1];
	 d <= tmp[2];
	 e <= tmp[3];
	 ref = tmp[0] ? tmp[1] : (tmp[2]&tmp[3]);

	 #1 if (ref !== a) begin
	    $display("FAILED -- a=%b, b=%b, c=%b, d=%b, e=%b",
		     a, b, c, d, e);
	    $finish;
	 end
      end

      b <= 0;
      c <= 1;
      d <= 1;
      e <= 0;
      #1 if (a !== 1'b0) begin
	 $display("FAILED (1)");
	 $finish;
      end

      e <= 1;
      #1 if (a !== 1'b1) begin
	 $display("FAILED (2)");
	 $finish;
      end

      $display("PASSED");
   end

endmodule