data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/xilinx/IOBUF.v
data/verilator_xmls/2b1d8910-69e5-4a31-8533-8945f114c866.xml
module IOBUF
  #(parameter IOSTANDARD = "DEFAULT",
    parameter SLEW = "SLOW",
    parameter DRIVE = "12")
   (
    input  T,
    input  I,
    output O,
    inout  IO
    );

   assign IO = T ? 1'bz : I;
   assign O  = IO;

endmodule
module IOBUF
  #(parameter IOSTANDARD = "DEFAULT",
    parameter SLEW = "SLOW",
    parameter DRIVE = "12")
   (
    input  T,
    input  I,
    output O,
    inout  IO
    );


   assign IO = T ? 1'bz : I;
   assign O  = IO;

endmodule