data/full_repos/permissive/176154329/src/game/game_state_machine.v
data/verilator_xmls/e3bc08f0-d61a-4175-96e2-45cc035979fa.xml
module game_state_machine
	(	
		input wire clk, hard_reset,
		input wire start,
        input wire collision,
		output wire [2:0] game_state,
		output wire game_en,
		output reg game_reset
    );
	

	reg start_reg;
	wire start_posedge;
	

	always @(posedge clk, posedge hard_reset)
		if(hard_reset)
			start_reg <= 0;
		else 
			start_reg <= start;
	

	assign start_posedge = start & ~start_reg;
	

	localparam [2:0] init     = 3'b000,
			 idle     = 3'b001,
		         playing  = 3'b010,
			     gameover = 3'b100;
	
	reg [2:0] game_state_reg, game_state_next;
	reg game_en_reg, game_en_next;
	

	always @(posedge clk, posedge hard_reset)
		if(hard_reset)
			begin
			game_state_reg <= init;
			game_en_reg    <= 0;
			end
		else
			begin
			game_state_reg <= game_state_next;
			game_en_reg    <= game_en_next;
			end
	
	always @*
		begin

		game_state_next = game_state_reg;
		game_en_next    = game_en_reg;
		game_reset = 0;
		
		case(game_state_reg)
			
			init:
					game_state_next = idle;
				
			idle:
				begin
				if(start_posedge)
					begin
					game_en_next = 1;
					game_reset   = 1;
					game_state_next = playing;
					end
				end
			
			playing:
				if(collision)
				begin
						game_en_next = 0;
						game_state_next = gameover;
				end
				
			gameover:
				if(start_posedge)
				begin
					game_state_next = init;
					game_reset   = 1;
				end
			endcase
			end
	

	assign game_state = game_state_reg;
	assign game_en = game_en_reg;

endmodule
module game_state_machine
	(	
		input wire clk, hard_reset,
		input wire start,
        input wire collision,
		output wire [2:0] game_state,
		output wire game_en,
		output reg game_reset
    );

	

	reg start_reg;
	wire start_posedge;
	

	always @(posedge clk, posedge hard_reset)
		if(hard_reset)
			start_reg <= 0;
		else 
			start_reg <= start;
	

	assign start_posedge = start & ~start_reg;
	

	localparam [2:0] init     = 3'b000,
			 idle     = 3'b001,
		         playing  = 3'b010,
			     gameover = 3'b100;
	
	reg [2:0] game_state_reg, game_state_next;
	reg game_en_reg, game_en_next;
	

	always @(posedge clk, posedge hard_reset)
		if(hard_reset)
			begin
			game_state_reg <= init;
			game_en_reg    <= 0;
			end
		else
			begin
			game_state_reg <= game_state_next;
			game_en_reg    <= game_en_next;
			end
	
	always @*
		begin

		game_state_next = game_state_reg;
		game_en_next    = game_en_reg;
		game_reset = 0;
		
		case(game_state_reg)
			
			init:
					game_state_next = idle;
				
			idle:
				begin
				if(start_posedge)
					begin
					game_en_next = 1;
					game_reset   = 1;
					game_state_next = playing;
					end
				end
			
			playing:
				if(collision)
				begin
						game_en_next = 0;
						game_state_next = gameover;
				end
				
			gameover:
				if(start_posedge)
				begin
					game_state_next = init;
					game_reset   = 1;
				end
			endcase
			end
	

	assign game_state = game_state_reg;
	assign game_en = game_en_reg;

endmodule