data/full_repos/permissive/174510456/vmodel/noobs_cpu.v
 line:259: before: ""data_mem rd and wr can never be set simultaneosly""
1: b'%Error: data/full_repos/permissive/174510456/vmodel/noobs_cpu.v:259: Define or directive not defined: \'`ASSERT_NEVER\'\n    `ASSERT_NEVER("data_mem rd and wr can never be set simultaneosly", u_assert_never_1, clk, reset_, data_memory_access_error)\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/174510456/vmodel/noobs_cpu.v:259: syntax error, unexpected \'(\'\n    `ASSERT_NEVER("data_mem rd and wr can never be set simultaneosly", u_assert_never_1, clk, reset_, data_memory_access_error)\n                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module noobs_cpu (
    clk,
    reset_,
`ifdef SYNTHESIS_DEBUG
    REG0,
    REG1,
    REG2,
    REG3,
    REG_WR_DATA,
    REG_WR_SEL,
    REG_WR_EN,
`endif
    i_data,
    i_addr,

    m_wr_data,
    m_rd_data,
    m_addr,
    m_rd,
    m_wr,
    m_en
);


    input           clk;
    input           reset_;

    input [7:0]     i_data;
    output [11:0]   i_addr;

    input [7:0]     m_rd_data;
    output [7:0]    m_wr_data;
    output [11:0]   m_addr;

    output          m_rd;
    output          m_wr;
    output          m_en;
`ifdef SYNTHESIS_DEBUG
    output [7:0] REG0;
    output [7:0] REG1;
    output [7:0] REG2;
    output [7:0] REG3;
    output [7:0] REG_WR_DATA;
    output [1:0] REG_WR_SEL;
    output REG_WR_EN;

    assign REG0 = reg0;
    assign REG1 = reg1;
    assign REG2 = reg2;
    assign REG3 = reg3;
    assign REG_WR_DATA = wr_data;
    assign REG_WR_SEL = wr_sel; 
    assign REG_WR_EN = wr_en;
`endif


    wire            pc_branch;
    wire [11:0]     tgt_addr;
    wire [7:0]      inst_o;

    wire            ifetch_en;
    wire            execute_en;
    wire [3:0]      exec_ctrl;

    wire [1:0]      rd_sel_0;
    wire [1:0]      rd_sel_1;

    wire [7:0]      rd_data_0;
    wire [7:0]      rd_data_1;

    wire            rd_en_0;
    wire            rd_en_1;

    wire [1:0]      dst_reg;

    wire [1:0]      wr_sel;
    wire [7:0]      wr_data;
    wire            wr_en;

    wire [7:0]      imm_data;
    wire            imm_data_vld;
    wire [11:0]     dst_addr;

    wire [7:0]      sr;

    wire            idecode_en;

    wire [11:0]     next_addr;

    wire            latch_ret_addr;

    wire [2:0]      sp_msb_10_8;
    wire [11:0]     ret_addr;
    wire            ret_addr_en;

    wire [7:0]      reg0;
    wire [7:0]      reg1;
    wire [7:0]      reg2;
    wire [7:0]      reg3;

    wire [7:0]      cr;
    wire [7:0]      cr_update;
    wire            cr_update_en;

`ifdef SYNTHESIS
   wire [31:0] cycle_counter;
   wire print_en;
   assign cycle_counter[31:0] = 32'd0;
   assign print_en = 0;
`else
    reg [31:0]      cycle_counter;
    always @(posedge clk) begin
        if(!reset_) begin
           cycle_counter <= 32'd0; 
        end
        else begin
           cycle_counter <= cycle_counter + 1'b1;
        end
    end

    reg print_en;
    always @(posedge clk or negedge clk) begin
        if(!reset_) begin
            print_en <= 0;
        end

        if(clk == 1) print_en <= 0;
        if(clk == 0) print_en <= 1;
    end
`endif




    ifetch u_ifetch(
        .clk(clk),
        .reset_(reset_),
        .branch(pc_branch),
        .ifetch_en(ifetch_en),
        .inst_i(i_data),
        .tgt_addr(tgt_addr),
        .ret_addr(ret_addr),
        .ret_addr_en(ret_addr_en),
        .inst_o(inst_o),
        .idecode_en(idecode_en),
        .inst_addr(i_addr),
        .next_addr(next_addr)
    );



    idecode u_idecode(
        .clk(clk),
        .cycle_counter(cycle_counter),
        .print_en(print_en),
        .reset_(reset_),
        .idecode_en(idecode_en),
        .inst_i(inst_o),
        .tgt_addr(tgt_addr),
        .exec_ctrl(exec_ctrl),
        .exec_src0_reg(rd_sel_0),
        .exec_src0_reg_rd_en(rd_en_0),
        .exec_src1_reg(rd_sel_1),
        .exec_src1_reg_rd_en(rd_en_1),
        .exec_dst_reg(dst_reg),
        .exec_addr(dst_addr),
        .exec_imm_val(imm_data),
        .exec_imm_val_vld(imm_data_vld),
        .decode2ifetch_en(ifetch_en),
        .decode2exec_en(execute_en),
        .decode2exec_latch_ret_addr(latch_ret_addr),
        .sp_msb_10_8(sp_msb_10_8),
        .sr(sr),
        .cr(cr),
        .cr_update(cr_update),
        .cr_update_en(cr_update_en)

    );



    reg_file u_reg_file(
        .clk(clk),
        .reset_(reset_),
        .reg0(reg0),
        .reg1(reg1),
        .reg2(reg2),
        .reg3(reg3),
        .rd_sel_0(rd_sel_0),
        .rd_en_0(rd_en_0),
        .rd_sel_1(rd_sel_1),
        .rd_en_1(rd_en_1),
        .wr_sel(wr_sel),
        .wr_en(wr_en),
        .wr_data(wr_data),
        .rd_data_0(rd_data_0),
        .rd_data_1(rd_data_1)
    );


    execute u_execute(
        .clk(clk),
        .cycle_counter(cycle_counter),
        .print_en(print_en),
        .reset_(reset_),
        .execute_en(execute_en),
        .latch_ret_addr(latch_ret_addr),
        .reg_src0_data(rd_data_0),
        .reg_src1_data(rd_data_1),
        .imm_data(imm_data),
        .imm_data_vld(imm_data_vld),
        .dst_reg(dst_reg),
        .reg_wr_data(wr_data),
        .reg_wr_sel(wr_sel),
        .reg_wr_en(wr_en),
        .exec_ctrl(exec_ctrl),
        .dst_addr(dst_addr),
        .d_mem_addr(m_addr),
        .d_mem_data_in(m_rd_data),
        .d_mem_data_out(m_wr_data),
        .d_mem_en(m_en),
        .d_mem_rd(m_rd),
        .d_mem_wr(m_wr),
        .pc_branch(pc_branch),
        .status_reg(sr),
        .sp_msb_10_8(sp_msb_10_8),
        .ret_addr(ret_addr),
        .ret_addr_en(ret_addr_en),
        .next_addr(next_addr),
        .reg0(reg0),
        .reg1(reg1),
        .reg2(reg2),
        .reg3(reg3),
        .cr(cr),
        .cr_update(cr_update),
        .cr_update_en(cr_update_en)
    );

    wire data_memory_access_error;
    assign data_memory_access_error = m_en & m_wr & m_rd;
    `ASSERT_NEVER("data_mem rd and wr can never be set simultaneosly", u_assert_never_1, clk, reset_, data_memory_access_error)
endmodule
module noobs_cpu (
    clk,
    reset_,
`ifdef SYNTHESIS_DEBUG
    REG0,
    REG1,
    REG2,
    REG3,
    REG_WR_DATA,
    REG_WR_SEL,
    REG_WR_EN,
`endif
    i_data,
    i_addr,

    m_wr_data,
    m_rd_data,
    m_addr,
    m_rd,
    m_wr,
    m_en
);



    input           clk;
    input           reset_;

    input [7:0]     i_data;
    output [11:0]   i_addr;

    input [7:0]     m_rd_data;
    output [7:0]    m_wr_data;
    output [11:0]   m_addr;

    output          m_rd;
    output          m_wr;
    output          m_en;
`ifdef SYNTHESIS_DEBUG
    output [7:0] REG0;
    output [7:0] REG1;
    output [7:0] REG2;
    output [7:0] REG3;
    output [7:0] REG_WR_DATA;
    output [1:0] REG_WR_SEL;
    output REG_WR_EN;

    assign REG0 = reg0;
    assign REG1 = reg1;
    assign REG2 = reg2;
    assign REG3 = reg3;
    assign REG_WR_DATA = wr_data;
    assign REG_WR_SEL = wr_sel; 
    assign REG_WR_EN = wr_en;
`endif


    wire            pc_branch;
    wire [11:0]     tgt_addr;
    wire [7:0]      inst_o;

    wire            ifetch_en;
    wire            execute_en;
    wire [3:0]      exec_ctrl;

    wire [1:0]      rd_sel_0;
    wire [1:0]      rd_sel_1;

    wire [7:0]      rd_data_0;
    wire [7:0]      rd_data_1;

    wire            rd_en_0;
    wire            rd_en_1;

    wire [1:0]      dst_reg;

    wire [1:0]      wr_sel;
    wire [7:0]      wr_data;
    wire            wr_en;

    wire [7:0]      imm_data;
    wire            imm_data_vld;
    wire [11:0]     dst_addr;

    wire [7:0]      sr;

    wire            idecode_en;

    wire [11:0]     next_addr;

    wire            latch_ret_addr;

    wire [2:0]      sp_msb_10_8;
    wire [11:0]     ret_addr;
    wire            ret_addr_en;

    wire [7:0]      reg0;
    wire [7:0]      reg1;
    wire [7:0]      reg2;
    wire [7:0]      reg3;

    wire [7:0]      cr;
    wire [7:0]      cr_update;
    wire            cr_update_en;

`ifdef SYNTHESIS
   wire [31:0] cycle_counter;
   wire print_en;
   assign cycle_counter[31:0] = 32'd0;
   assign print_en = 0;
`else
    reg [31:0]      cycle_counter;
    always @(posedge clk) begin
        if(!reset_) begin
           cycle_counter <= 32'd0; 
        end
        else begin
           cycle_counter <= cycle_counter + 1'b1;
        end
    end

    reg print_en;
    always @(posedge clk or negedge clk) begin
        if(!reset_) begin
            print_en <= 0;
        end

        if(clk == 1) print_en <= 0;
        if(clk == 0) print_en <= 1;
    end
`endif




    ifetch u_ifetch(
        .clk(clk),
        .reset_(reset_),
        .branch(pc_branch),
        .ifetch_en(ifetch_en),
        .inst_i(i_data),
        .tgt_addr(tgt_addr),
        .ret_addr(ret_addr),
        .ret_addr_en(ret_addr_en),
        .inst_o(inst_o),
        .idecode_en(idecode_en),
        .inst_addr(i_addr),
        .next_addr(next_addr)
    );



    idecode u_idecode(
        .clk(clk),
        .cycle_counter(cycle_counter),
        .print_en(print_en),
        .reset_(reset_),
        .idecode_en(idecode_en),
        .inst_i(inst_o),
        .tgt_addr(tgt_addr),
        .exec_ctrl(exec_ctrl),
        .exec_src0_reg(rd_sel_0),
        .exec_src0_reg_rd_en(rd_en_0),
        .exec_src1_reg(rd_sel_1),
        .exec_src1_reg_rd_en(rd_en_1),
        .exec_dst_reg(dst_reg),
        .exec_addr(dst_addr),
        .exec_imm_val(imm_data),
        .exec_imm_val_vld(imm_data_vld),
        .decode2ifetch_en(ifetch_en),
        .decode2exec_en(execute_en),
        .decode2exec_latch_ret_addr(latch_ret_addr),
        .sp_msb_10_8(sp_msb_10_8),
        .sr(sr),
        .cr(cr),
        .cr_update(cr_update),
        .cr_update_en(cr_update_en)

    );



    reg_file u_reg_file(
        .clk(clk),
        .reset_(reset_),
        .reg0(reg0),
        .reg1(reg1),
        .reg2(reg2),
        .reg3(reg3),
        .rd_sel_0(rd_sel_0),
        .rd_en_0(rd_en_0),
        .rd_sel_1(rd_sel_1),
        .rd_en_1(rd_en_1),
        .wr_sel(wr_sel),
        .wr_en(wr_en),
        .wr_data(wr_data),
        .rd_data_0(rd_data_0),
        .rd_data_1(rd_data_1)
    );


    execute u_execute(
        .clk(clk),
        .cycle_counter(cycle_counter),
        .print_en(print_en),
        .reset_(reset_),
        .execute_en(execute_en),
        .latch_ret_addr(latch_ret_addr),
        .reg_src0_data(rd_data_0),
        .reg_src1_data(rd_data_1),
        .imm_data(imm_data),
        .imm_data_vld(imm_data_vld),
        .dst_reg(dst_reg),
        .reg_wr_data(wr_data),
        .reg_wr_sel(wr_sel),
        .reg_wr_en(wr_en),
        .exec_ctrl(exec_ctrl),
        .dst_addr(dst_addr),
        .d_mem_addr(m_addr),
        .d_mem_data_in(m_rd_data),
        .d_mem_data_out(m_wr_data),
        .d_mem_en(m_en),
        .d_mem_rd(m_rd),
        .d_mem_wr(m_wr),
        .pc_branch(pc_branch),
        .status_reg(sr),
        .sp_msb_10_8(sp_msb_10_8),
        .ret_addr(ret_addr),
        .ret_addr_en(ret_addr_en),
        .next_addr(next_addr),
        .reg0(reg0),
        .reg1(reg1),
        .reg2(reg2),
        .reg3(reg3),
        .cr(cr),
        .cr_update(cr_update),
        .cr_update_en(cr_update_en)
    );

    wire data_memory_access_error;
    assign data_memory_access_error = m_en & m_wr & m_rd;
    `ASSERT_NEVER("data_mem rd and wr can never be set simultaneosly", u_assert_never_1, clk, reset_, data_memory_access_error)
endmodule