data/full_repos/permissive/121864597/Main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/121864597/Main.v:36: Unsupported: Ignoring delay on this delayed statement.\n#45 reset = 0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121864597/Main.v:44: Unsupported: Ignoring delay on this delayed statement.\n#5 clk = !clk ;\n^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Ring_B();
reg clk;
reg reset;
wire [3:0]q;
initial
begin
reset = 1;
clk = 0;
#45 reset = 0;
end

D ini(q[3],reset,clk,q[0]);
D2 rest1(q[0],clk,q[1]);
D2 rest2(q[1],clk,q[2]);
D2 rest3(q[2],clk,q[3]);
always
#5 clk = !clk ;
endmodule
module Ring_B();

reg clk;
reg reset;
wire [3:0]q;
initial
begin
reset = 1;
clk = 0;
#45 reset = 0;
end

D ini(q[3],reset,clk,q[0]);
D2 rest1(q[0],clk,q[1]);
D2 rest2(q[1],clk,q[2]);
D2 rest3(q[2],clk,q[3]);
always
#5 clk = !clk ;
endmodule