data/full_repos/permissive/123612637/cpc_ram_expansion1mb/src/cpld_ram1m_plcc84.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/123612637/cpc_ram_expansion1mb/src/cpld_ram1m_plcc84.v:215: Signal definition not found, creating implicitly: \'shadow_mode\'\n  assign shadow_mode   = dip[0] ;\n         ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/123612637/cpc_ram_expansion1mb/src/cpld_ram1m_plcc84.v:405: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                                                     : ... In instance cpld_ram1m_plcc84\n  3\'b010: {exp_ram_r, ramcs_b_r, ramadrhi_r} = { 2\'b10, ramblock_q[5:3], adr15,adr[14]} ;\n                                             ^\n%Error: Exiting due to 2 warning(s)\n'
module cpld_ram1m_plcc84(
                         input        rfsh_b,
                         inout        adr15,
                         inout        adr15_aux,

                         input [14:0] adr,
                         input        ioreq_b,
                         input        mreq_b,
                         input        reset_b,
                         input        busreset_b,
                         input        busack_b,
                         inout        wr_b,
                         inout        rd_b,
                         input        m1_b,
                         input [7:0]  data,
                         input        clk,
                         input [3:0]  dip,
                         input        ramrd_b,
                         input        romen_b,

                         inout        ramdis,
                         inout        int_b,
                         inout        nmi_b,
                         inout        ready,
                         inout [7:0]  gpio,
                         inout        romdis,
                         inout [4:0]  ramadrhi,

                         inout [4:0]  tp,
                         output       ramcs0_b,
                         output       ramcs1_b,
                         output       busreq_b,
                         output       ramoe_b,
                         output       ramwe_b
);

  parameter   shadow_bank= 4'b0111;

  reg [6:0]        ramblock_q;
  reg [5:0]        ramadrhi_r;
  wire             cardsel_w;
  wire             adr15_mx_w;
  reg              mode3_overdrive_q;
  reg              mwr_cyc_q;
  reg              mwr_cyc_f_q;
  reg              ramcs_b_r;
  reg              adr15_q;
  reg              exp_ram_r;
`ifndef DISABLE_RESET_RESYNC
  reg              reset_b_q;
  reg              reset1_b_q;
`endif
  reg              exp_ram_q;
  reg 	           urom_disable_q;
  reg 	           lrom_disable_q;
`ifndef EXT_RAMRD
  reg              int_ramrd_b_r ;
  wire             ramrd_b_w = int_ramrd_b_r;
`else
  wire             ramrd_b_w = ramrd_b;
`endif
  wire             ram_ctrl_select_w;
  wire             rom_ctrl_select_w;
  wire             full_shadow;
  wire             overdrive_mode;
  wire             mwr_cyc_d;
  wire             adr15_overdrive_w;
  wire             ram64kb_mode;
  wire             ram1mb_mode;
  wire             reset_b_w;

`ifdef PLUS
  wire             plus_unlock_w;
  wire             rmr2_ctrl_select_w;
  reg              plus_map_enable_q;

  asic_lock al_0(
                 .clk(clk),
                 .reset_b(reset_b_w),
                 .ioreq_b(ioreq_b),
                 .wr_b(wr_b),
                 .data(data),
                 .io_cs( ({ adr15, adr[14:8]} == 8'hBC) ),
                 .enf(plus_unlock_w)
                 );
`endif




`ifdef CPC6128_ONLY
  assign overdrive_mode = 1'b0;
  assign full_shadow = 1'b0;
  assign shadow_mode = 1'b0;
`else
  `ifdef FULL_SHADOW_ONLY
  assign full_shadow   = dip[0];
  `else
  assign full_shadow   = dip[1] & dip[0];
  `endif
  assign shadow_mode   = dip[0] ;
  assign overdrive_mode= dip[0] | dip[1];
`endif

  assign ram64kb_mode  = !dip[2] & dip[3];
  assign ram1mb_mode   = dip[2] & dip[3];
  assign cardsel_w     = dip[2] | dip[3];


  assign ramadrhi =  ( !reset_b_w ) ? 5'bzzzzz : ramadrhi_r[4:0];

`ifdef PLUS
  assign ram_ctrl_select_w = (!ioreq_b & !wr_b & !adr15 & data[6] & data[7]  );
  assign rom_ctrl_select_w = (!ioreq_b & !wr_b & !adr15 & !data[6] & data[7] & !data[5] );
  assign rmr2_ctrl_select_w = (!ioreq_b & !wr_b & !adr15 & !data[6] & data[7] & data[5] & plus_unlock_w );
`else
  assign ram_ctrl_select_w = (!ioreq_b & !wr_b & !adr15 & data[6] & data[7] );
  assign rom_ctrl_select_w = (!ioreq_b & !wr_b & !adr15 & !data[6] & data[7] & !data[5]);
`endif

`ifdef DISABLE_RESET_RESYNC
  assign reset_b_w = busreset_b;
`else
  assign reset_b_w = reset1_b_q & busreset_b & reset_b_q;
`endif

`ifndef EXT_RAMRD


  always @ ( * ) begin
    int_ramrd_b_r = 1'b1 ;
    if ( rfsh_b & !mreq_b & !rd_b)
      if ( adr15_mx_w != adr[14] )
        int_ramrd_b_r = 1'b0;

      else if ( urom_disable_q & ( {adr15_q,adr[14]} == 2'b11 ))
        int_ramrd_b_r = 1'b0;
      else if ( lrom_disable_q & ( {adr15_q,adr[14]} == 2'b00 ))
        int_ramrd_b_r = 1'b0;
  end
`endif


  assign ramwe_b = ! ( !wr_b & mwr_cyc_q & mwr_cyc_f_q );
  assign ramoe_b = ramrd_b_w ;





  assign wr_b = ( overdrive_mode & exp_ram_q & (mwr_cyc_q & !mwr_cyc_f_q)) ? 1'b0 : 1'bz;
  assign rd_b = ( overdrive_mode & exp_ram_q & (mwr_cyc_q|mwr_cyc_f_q)) ? 1'b0 : 1'bz ;





  assign mwr_cyc_d = !mreq_b & rd_b & rfsh_b;
  assign adr15_overdrive_w = mode3_overdrive_q & adr[14] & !adr15_mx_w & ((shadow_mode) ? (mwr_cyc_q|mwr_cyc_d): !mreq_b) ;
  assign { adr15, adr15_aux} = (adr15_overdrive_w ) ? 2'b11 : 2'bzz;
  assign adr15_mx_w = (mreq_b) ? adr15: adr15_q;


  assign ramdis = (cardsel_w & (full_shadow | !ramcs_b_r)) ? 1'b1 : 1'bz;











`ifdef FULL_SHADOW_ONLY
  assign ramcs0_b =  !cardsel_w | !((!ramadrhi_r[5] & exp_ram_r) | (full_shadow & !exp_ram_r)) | mreq_b | !rfsh_b;
`else
  assign ramcs0_b =  !cardsel_w | !((!ramadrhi_r[5] & exp_ram_r) | (full_shadow & !exp_ram_r) | (shadow_mode & !exp_ram_r & !ramcs_b_r)) | mreq_b | !rfsh_b;
`endif

  assign ramcs1_b = (!cardsel_w) | !(ramadrhi_r[5] & exp_ram_r) | mreq_b | !rfsh_b ;

  always @ (posedge clk)
    if ( mwr_cyc_d )
      mwr_cyc_q <= 1'b1;
    else if (mreq_b)
      mwr_cyc_q <= 1'b0;

  always @ (negedge mreq_b)
    adr15_q <= adr15;

  always @ (negedge clk or negedge reset_b_w)
    if ( !reset_b_w ) begin
      mwr_cyc_f_q <= 1'b0;
    end
    else begin
      mwr_cyc_f_q <= mwr_cyc_q;
    end

  always @ (posedge clk or negedge reset_b_w)
     if ( !reset_b_w ) begin
      exp_ram_q = 1'b0;
    end
    else begin
      exp_ram_q = exp_ram_r;
    end

`ifndef DISABLE_RESET_RESYNC
   always @ (posedge clk or negedge busreset_b)
     if ( !busreset_b )
       {reset1_b_q, reset_b_q}  = 2'b00;
     else
       {reset1_b_q, reset_b_q}  = {reset_b_q, busreset_b};
`endif



  always @ (negedge clk or negedge reset_b_w)
    if (!reset_b_w) begin
      ramblock_q <= 7'b0;
      mode3_overdrive_q <= 1'b0;
    end
    else begin
       if ( ram_ctrl_select_w ) begin
         if (ram64kb_mode)

           ramblock_q <= {4'b1000, data[2:0]} ;
         else if (ram1mb_mode)


           if ( shadow_mode & {adr[8],data[5:3]}==shadow_bank )
             ramblock_q <= {adr[8],data[5:4], 1'b0, data[2:0]};
           else
             ramblock_q <= {adr[8],data[5:0]};
         else

           ramblock_q <= {1'b1,data[5:0]};
         mode3_overdrive_q <= overdrive_mode & (data[2:0] == 3'b011);
       end
    end

`ifndef EXT_RAMRD
  always @ (negedge clk or negedge reset_b_w)
    if (!reset_b_w)
      { urom_disable_q, lrom_disable_q}  <= 2'b00;
    else if ( rom_ctrl_select_w )
      { urom_disable_q, lrom_disable_q } <= data[3:2];
`endif

`ifdef PLUS
  wire plus_map_enable_d = (rmr2_ctrl_select_w) ? (data[4] & data[3]) : plus_map_enable_q;

  always @ (negedge clk ) begin
    if (!reset_b_w)
      plus_map_enable_q  <= 1'b0;
    else
      plus_map_enable_q  <= plus_map_enable_d;
  end
`endif

  always @ ( * ) begin
`ifdef PLUS

    if ( plus_map_enable_q & !adr15 & adr[14] ) begin
      {exp_ram_r, ramcs_b_r, ramadrhi_r} = { 1'b0, 1'b1, 6'bxxxxxx };
    end
    else
`endif
    if ( shadow_mode )


      case (ramblock_q[2:0])
 	3'b000: {exp_ram_r, ramcs_b_r, ramadrhi_r} = { 1'b0, !mwr_cyc_q , shadow_bank, adr15,adr[14] };
 	3'b001: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b11 ) ? {2'b10, ramblock_q[6:3],2'b11} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15,adr[14] };
 	3'b010: {exp_ram_r, ramcs_b_r, ramadrhi_r} = { 2'b10, ramblock_q[5:3], adr15,adr[14]} ;
 	3'b011: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15_mx_w,adr[14]}==2'b11 ) ? {2'b10,ramblock_q[6:3],2'b11} : ({adr15_mx_w,adr[14]}==2'b01) ? {2'b00,shadow_bank,2'b11} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15,adr[14] };
 	3'b100: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b00} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15, adr[14] };
 	3'b101: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b01} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15, adr[14] };
 	3'b110: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b10} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15, adr[14] };
 	3'b111: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b11} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15, adr[14] };
      endcase
    else

      case (ramblock_q[2:0])
 	3'b000: {exp_ram_r, ramcs_b_r, ramadrhi_r} = { 2'b01, 6'bxxxxx };
 	3'b001: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b11 ) ? {2'b10,ramblock_q[6:3],2'b11} : {2'b01, 6'bxxxxx};
 	3'b010: {exp_ram_r, ramcs_b_r, ramadrhi_r} = { 2'b10,ramblock_q[6:3],adr15,adr[14]} ;
 	3'b011: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15_mx_w,adr[14]}==2'b11 ) ? {2'b10,ramblock_q[6:3],2'b11} : {2'b01, 6'bxxxxx };
 	3'b100: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b00} : {2'b01, 6'bxxxxx };
 	3'b101: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b01} : {2'b01, 6'bxxxxx };
 	3'b110: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b10} : {2'b01, 6'bxxxxx };
 	3'b111: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b11} : {2'b01, 6'bxxxxx };
      endcase
  end

endmodule
module cpld_ram1m_plcc84(
                         input        rfsh_b,
                         inout        adr15,
                         inout        adr15_aux,

                         input [14:0] adr,
                         input        ioreq_b,
                         input        mreq_b,
                         input        reset_b,
                         input        busreset_b,
                         input        busack_b,
                         inout        wr_b,
                         inout        rd_b,
                         input        m1_b,
                         input [7:0]  data,
                         input        clk,
                         input [3:0]  dip,
                         input        ramrd_b,
                         input        romen_b,

                         inout        ramdis,
                         inout        int_b,
                         inout        nmi_b,
                         inout        ready,
                         inout [7:0]  gpio,
                         inout        romdis,
                         inout [4:0]  ramadrhi,

                         inout [4:0]  tp,
                         output       ramcs0_b,
                         output       ramcs1_b,
                         output       busreq_b,
                         output       ramoe_b,
                         output       ramwe_b
);


  parameter   shadow_bank= 4'b0111;

  reg [6:0]        ramblock_q;
  reg [5:0]        ramadrhi_r;
  wire             cardsel_w;
  wire             adr15_mx_w;
  reg              mode3_overdrive_q;
  reg              mwr_cyc_q;
  reg              mwr_cyc_f_q;
  reg              ramcs_b_r;
  reg              adr15_q;
  reg              exp_ram_r;
`ifndef DISABLE_RESET_RESYNC
  reg              reset_b_q;
  reg              reset1_b_q;
`endif
  reg              exp_ram_q;
  reg 	           urom_disable_q;
  reg 	           lrom_disable_q;
`ifndef EXT_RAMRD
  reg              int_ramrd_b_r ;
  wire             ramrd_b_w = int_ramrd_b_r;
`else
  wire             ramrd_b_w = ramrd_b;
`endif
  wire             ram_ctrl_select_w;
  wire             rom_ctrl_select_w;
  wire             full_shadow;
  wire             overdrive_mode;
  wire             mwr_cyc_d;
  wire             adr15_overdrive_w;
  wire             ram64kb_mode;
  wire             ram1mb_mode;
  wire             reset_b_w;

`ifdef PLUS
  wire             plus_unlock_w;
  wire             rmr2_ctrl_select_w;
  reg              plus_map_enable_q;

  asic_lock al_0(
                 .clk(clk),
                 .reset_b(reset_b_w),
                 .ioreq_b(ioreq_b),
                 .wr_b(wr_b),
                 .data(data),
                 .io_cs( ({ adr15, adr[14:8]} == 8'hBC) ),
                 .enf(plus_unlock_w)
                 );
`endif




`ifdef CPC6128_ONLY
  assign overdrive_mode = 1'b0;
  assign full_shadow = 1'b0;
  assign shadow_mode = 1'b0;
`else
  `ifdef FULL_SHADOW_ONLY
  assign full_shadow   = dip[0];
  `else
  assign full_shadow   = dip[1] & dip[0];
  `endif
  assign shadow_mode   = dip[0] ;
  assign overdrive_mode= dip[0] | dip[1];
`endif

  assign ram64kb_mode  = !dip[2] & dip[3];
  assign ram1mb_mode   = dip[2] & dip[3];
  assign cardsel_w     = dip[2] | dip[3];


  assign ramadrhi =  ( !reset_b_w ) ? 5'bzzzzz : ramadrhi_r[4:0];

`ifdef PLUS
  assign ram_ctrl_select_w = (!ioreq_b & !wr_b & !adr15 & data[6] & data[7]  );
  assign rom_ctrl_select_w = (!ioreq_b & !wr_b & !adr15 & !data[6] & data[7] & !data[5] );
  assign rmr2_ctrl_select_w = (!ioreq_b & !wr_b & !adr15 & !data[6] & data[7] & data[5] & plus_unlock_w );
`else
  assign ram_ctrl_select_w = (!ioreq_b & !wr_b & !adr15 & data[6] & data[7] );
  assign rom_ctrl_select_w = (!ioreq_b & !wr_b & !adr15 & !data[6] & data[7] & !data[5]);
`endif

`ifdef DISABLE_RESET_RESYNC
  assign reset_b_w = busreset_b;
`else
  assign reset_b_w = reset1_b_q & busreset_b & reset_b_q;
`endif

`ifndef EXT_RAMRD


  always @ ( * ) begin
    int_ramrd_b_r = 1'b1 ;
    if ( rfsh_b & !mreq_b & !rd_b)
      if ( adr15_mx_w != adr[14] )
        int_ramrd_b_r = 1'b0;

      else if ( urom_disable_q & ( {adr15_q,adr[14]} == 2'b11 ))
        int_ramrd_b_r = 1'b0;
      else if ( lrom_disable_q & ( {adr15_q,adr[14]} == 2'b00 ))
        int_ramrd_b_r = 1'b0;
  end
`endif


  assign ramwe_b = ! ( !wr_b & mwr_cyc_q & mwr_cyc_f_q );
  assign ramoe_b = ramrd_b_w ;





  assign wr_b = ( overdrive_mode & exp_ram_q & (mwr_cyc_q & !mwr_cyc_f_q)) ? 1'b0 : 1'bz;
  assign rd_b = ( overdrive_mode & exp_ram_q & (mwr_cyc_q|mwr_cyc_f_q)) ? 1'b0 : 1'bz ;





  assign mwr_cyc_d = !mreq_b & rd_b & rfsh_b;
  assign adr15_overdrive_w = mode3_overdrive_q & adr[14] & !adr15_mx_w & ((shadow_mode) ? (mwr_cyc_q|mwr_cyc_d): !mreq_b) ;
  assign { adr15, adr15_aux} = (adr15_overdrive_w ) ? 2'b11 : 2'bzz;
  assign adr15_mx_w = (mreq_b) ? adr15: adr15_q;


  assign ramdis = (cardsel_w & (full_shadow | !ramcs_b_r)) ? 1'b1 : 1'bz;











`ifdef FULL_SHADOW_ONLY
  assign ramcs0_b =  !cardsel_w | !((!ramadrhi_r[5] & exp_ram_r) | (full_shadow & !exp_ram_r)) | mreq_b | !rfsh_b;
`else
  assign ramcs0_b =  !cardsel_w | !((!ramadrhi_r[5] & exp_ram_r) | (full_shadow & !exp_ram_r) | (shadow_mode & !exp_ram_r & !ramcs_b_r)) | mreq_b | !rfsh_b;
`endif

  assign ramcs1_b = (!cardsel_w) | !(ramadrhi_r[5] & exp_ram_r) | mreq_b | !rfsh_b ;

  always @ (posedge clk)
    if ( mwr_cyc_d )
      mwr_cyc_q <= 1'b1;
    else if (mreq_b)
      mwr_cyc_q <= 1'b0;

  always @ (negedge mreq_b)
    adr15_q <= adr15;

  always @ (negedge clk or negedge reset_b_w)
    if ( !reset_b_w ) begin
      mwr_cyc_f_q <= 1'b0;
    end
    else begin
      mwr_cyc_f_q <= mwr_cyc_q;
    end

  always @ (posedge clk or negedge reset_b_w)
     if ( !reset_b_w ) begin
      exp_ram_q = 1'b0;
    end
    else begin
      exp_ram_q = exp_ram_r;
    end

`ifndef DISABLE_RESET_RESYNC
   always @ (posedge clk or negedge busreset_b)
     if ( !busreset_b )
       {reset1_b_q, reset_b_q}  = 2'b00;
     else
       {reset1_b_q, reset_b_q}  = {reset_b_q, busreset_b};
`endif



  always @ (negedge clk or negedge reset_b_w)
    if (!reset_b_w) begin
      ramblock_q <= 7'b0;
      mode3_overdrive_q <= 1'b0;
    end
    else begin
       if ( ram_ctrl_select_w ) begin
         if (ram64kb_mode)

           ramblock_q <= {4'b1000, data[2:0]} ;
         else if (ram1mb_mode)


           if ( shadow_mode & {adr[8],data[5:3]}==shadow_bank )
             ramblock_q <= {adr[8],data[5:4], 1'b0, data[2:0]};
           else
             ramblock_q <= {adr[8],data[5:0]};
         else

           ramblock_q <= {1'b1,data[5:0]};
         mode3_overdrive_q <= overdrive_mode & (data[2:0] == 3'b011);
       end
    end

`ifndef EXT_RAMRD
  always @ (negedge clk or negedge reset_b_w)
    if (!reset_b_w)
      { urom_disable_q, lrom_disable_q}  <= 2'b00;
    else if ( rom_ctrl_select_w )
      { urom_disable_q, lrom_disable_q } <= data[3:2];
`endif

`ifdef PLUS
  wire plus_map_enable_d = (rmr2_ctrl_select_w) ? (data[4] & data[3]) : plus_map_enable_q;

  always @ (negedge clk ) begin
    if (!reset_b_w)
      plus_map_enable_q  <= 1'b0;
    else
      plus_map_enable_q  <= plus_map_enable_d;
  end
`endif

  always @ ( * ) begin
`ifdef PLUS

    if ( plus_map_enable_q & !adr15 & adr[14] ) begin
      {exp_ram_r, ramcs_b_r, ramadrhi_r} = { 1'b0, 1'b1, 6'bxxxxxx };
    end
    else
`endif
    if ( shadow_mode )


      case (ramblock_q[2:0])
 	3'b000: {exp_ram_r, ramcs_b_r, ramadrhi_r} = { 1'b0, !mwr_cyc_q , shadow_bank, adr15,adr[14] };
 	3'b001: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b11 ) ? {2'b10, ramblock_q[6:3],2'b11} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15,adr[14] };
 	3'b010: {exp_ram_r, ramcs_b_r, ramadrhi_r} = { 2'b10, ramblock_q[5:3], adr15,adr[14]} ;
 	3'b011: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15_mx_w,adr[14]}==2'b11 ) ? {2'b10,ramblock_q[6:3],2'b11} : ({adr15_mx_w,adr[14]}==2'b01) ? {2'b00,shadow_bank,2'b11} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15,adr[14] };
 	3'b100: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b00} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15, adr[14] };
 	3'b101: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b01} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15, adr[14] };
 	3'b110: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b10} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15, adr[14] };
 	3'b111: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b11} : { 1'b0, !mwr_cyc_q , shadow_bank, adr15, adr[14] };
      endcase
    else

      case (ramblock_q[2:0])
 	3'b000: {exp_ram_r, ramcs_b_r, ramadrhi_r} = { 2'b01, 6'bxxxxx };
 	3'b001: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b11 ) ? {2'b10,ramblock_q[6:3],2'b11} : {2'b01, 6'bxxxxx};
 	3'b010: {exp_ram_r, ramcs_b_r, ramadrhi_r} = { 2'b10,ramblock_q[6:3],adr15,adr[14]} ;
 	3'b011: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15_mx_w,adr[14]}==2'b11 ) ? {2'b10,ramblock_q[6:3],2'b11} : {2'b01, 6'bxxxxx };
 	3'b100: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b00} : {2'b01, 6'bxxxxx };
 	3'b101: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b01} : {2'b01, 6'bxxxxx };
 	3'b110: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b10} : {2'b01, 6'bxxxxx };
 	3'b111: {exp_ram_r, ramcs_b_r, ramadrhi_r} = ( {adr15,adr[14]}==2'b01 ) ? {2'b10,ramblock_q[6:3],2'b11} : {2'b01, 6'bxxxxx };
      endcase
  end

endmodule