data/full_repos/permissive/185628295/hdl/multiply_add_tb.v
 line:44: before: "signed"
1: b'%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:18: Cannot find include file: multiply_add.v\n`include "multiply_add.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/multiply_add.v\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/multiply_add.v.v\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/multiply_add.v.sv\n             multiply_add.v\n             multiply_add.v.v\n             multiply_add.v.sv\n             obj_dir/multiply_add.v\n             obj_dir/multiply_add.v.v\n             obj_dir/multiply_add.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:31: Unsupported: event data types\n    event end_trigger;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    initial #1 display_header();\n            ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:123: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:139: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:163: syntax error, unexpected \'@\'\n        repeat(6) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:165: syntax error, unexpected \'@\'\n        repeat(6) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:167: syntax error, unexpected \'@\'\n        repeat(6) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:174: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:177: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:180: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:189: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:194: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:199: syntax error, unexpected \'@\'\n        repeat (10) @(negedge clk);\n                    ^\n%Error: data/full_repos/permissive/185628295/hdl/multiply_add_tb.v:206: syntax error, unexpected ->\n        -> end_trigger;\n        ^~\n%Error: Exiting due to 14 error(s), 2 warning(s)\n'
module multiply_add_tb;




    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam IMG_WIDTH    = 8;
    localparam KER_WIDTH    = 16;


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'multiply_add' up_img: %d, cfg_ker: %d, dn_acc: %d",
            IMG_WIDTH, KER_WIDTH, (IMG_WIDTH+KER_WIDTH));
    end
`endif




    reg  rst;

    reg     [KER_WIDTH-1:0]             cfg_ker;
    reg                                 cfg_val;

    reg     [IMG_WIDTH-1:0]             up_img;
    reg     [IMG_WIDTH+KER_WIDTH-1:0]   up_acc;

    wire    [IMG_WIDTH-1:0]             dn_img;
    wire    [IMG_WIDTH+KER_WIDTH-1:0]   dn_acc;




    multiply_add #(
        .IMG_WIDTH  (IMG_WIDTH),
        .KER_WIDTH  (KER_WIDTH))
    uut (
        .clk        (clk),
        .rst        (rst),

        .cfg_ker    (cfg_ker),
        .cfg_val    (cfg_val),

        .up_img        (up_img),
        .up_acc        (up_acc),

        .dn_img     (dn_img),
        .dn_acc     (dn_acc)
    );




    task display_signals;
        $display(
            "%d\t%d",
            $time, rst,

            "\t%b\t%d",
            cfg_val,
            $signed(cfg_ker),

            "\t%d\t%d",
            $signed(up_img),
            $signed(up_acc),

            "\t%d\t%d",
            $signed(dn_img),
            $signed(dn_acc),
        );
    endtask

    task display_header;
        $display(
            "\t\ttime\trst",

            "\tval",
            "\tker",

            "\tup_img",
            "\tup_acc",

            "\t\tdn_img",
            "\t\tdn_acc",

        );
    endtask





    initial begin

        rst = 0;

        cfg_ker = 'b0;
        cfg_val = 1'b0;

        up_img = 'b0;
        up_acc = 'b0;


`ifdef TB_VERBOSE
    $display("RESET");
`endif

        repeat(6) @(posedge clk);
        rst <= 1'b1;
        repeat(6) @(posedge clk);
        rst <= 1'b0;
        repeat(6) @(posedge clk);


`ifdef TB_VERBOSE
    $display("set kernel weight");
`endif

        @(negedge clk);
        cfg_ker <= 'd2;
        cfg_val <= 1'b1;
        @(negedge clk);
        cfg_ker <= 'd0;
        cfg_val <= 1'b0;
        @(negedge clk);


`ifdef TB_VERBOSE
    $display("test continuous stream");
`endif

        up_img <= 'd1;
        up_acc <= 'd1;
        @(negedge clk);
        repeat (10) begin
            up_img <= up_img + 'b1;
            up_acc <= 1'b1;

            @(negedge clk);
        end

        up_img <=  'b0;
        up_acc <=  'b0;
        repeat (10) @(negedge clk);



`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule
module multiply_add_tb;





    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam IMG_WIDTH    = 8;
    localparam KER_WIDTH    = 16;


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'multiply_add' up_img: %d, cfg_ker: %d, dn_acc: %d",
            IMG_WIDTH, KER_WIDTH, (IMG_WIDTH+KER_WIDTH));
    end
`endif




    reg  rst;

    reg     [KER_WIDTH-1:0]             cfg_ker;
    reg                                 cfg_val;

    reg     [IMG_WIDTH-1:0]             up_img;
    reg     [IMG_WIDTH+KER_WIDTH-1:0]   up_acc;

    wire    [IMG_WIDTH-1:0]             dn_img;
    wire    [IMG_WIDTH+KER_WIDTH-1:0]   dn_acc;




    multiply_add #(
        .IMG_WIDTH  (IMG_WIDTH),
        .KER_WIDTH  (KER_WIDTH))
    uut (
        .clk        (clk),
        .rst        (rst),

        .cfg_ker    (cfg_ker),
        .cfg_val    (cfg_val),

        .up_img        (up_img),
        .up_acc        (up_acc),

        .dn_img     (dn_img),
        .dn_acc     (dn_acc)
    );




    task display_signals;
        $display(
            "%d\t%d",
            $time, rst,

            "\t%b\t%d",
            cfg_val,
            $signed(cfg_ker),

            "\t%d\t%d",
            $signed(up_img),
            $signed(up_acc),

            "\t%d\t%d",
            $signed(dn_img),
            $signed(dn_acc),
        );
    endtask

    task display_header;
        $display(
            "\t\ttime\trst",

            "\tval",
            "\tker",

            "\tup_img",
            "\tup_acc",

            "\t\tdn_img",
            "\t\tdn_acc",

        );
    endtask





    initial begin

        rst = 0;

        cfg_ker = 'b0;
        cfg_val = 1'b0;

        up_img = 'b0;
        up_acc = 'b0;


`ifdef TB_VERBOSE
    $display("RESET");
`endif

        repeat(6) @(posedge clk);
        rst <= 1'b1;
        repeat(6) @(posedge clk);
        rst <= 1'b0;
        repeat(6) @(posedge clk);


`ifdef TB_VERBOSE
    $display("set kernel weight");
`endif

        @(negedge clk);
        cfg_ker <= 'd2;
        cfg_val <= 1'b1;
        @(negedge clk);
        cfg_ker <= 'd0;
        cfg_val <= 1'b0;
        @(negedge clk);


`ifdef TB_VERBOSE
    $display("test continuous stream");
`endif

        up_img <= 'd1;
        up_acc <= 'd1;
        @(negedge clk);
        repeat (10) begin
            up_img <= up_img + 'b1;
            up_acc <= 1'b1;

            @(negedge clk);
        end

        up_img <=  'b0;
        up_acc <=  'b0;
        repeat (10) @(negedge clk);



`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule