data/full_repos/permissive/207111076/sdram_ctrl/sdram_data_8b.v
 line:83: before: "requests"
data/verilator_xmls/f4b8904d-ca3e-404e-9c38-fbcb341ccfee.xml
module sdram_data_8b
(



    input             clk,




    output      [7:0] rd_data,
    
    input       [3:0] data_fetch,
    input       [7:0] wr_data_b0,
    input       [7:0] wr_data_b1,
    input       [7:0] wr_data_b2,
    input       [7:0] wr_data_b3,
    



    output reg        sdram_dq_oe,
    output reg  [7:0] sdram_dq_o,
    input       [7:0] sdram_dq_i
);

    parameter Tco_dly = 4.5;


    
    reg [7:0] r_rd_data;
    
    always@(posedge clk) begin : READ_DATA_PATH
    
        r_rd_data <= sdram_dq_i;
    end
    
    assign rd_data = r_rd_data;


    
    reg [3:0] r_data_fe_p1;
    reg [3:0] r_data_fe_p2;
    
    reg       r_data_oe_p3;
    reg       r_data_oe_p4;
    
    reg [7:0] r_wr_data_p3 [0:1];
    reg [7:0] r_wr_data_p4;
    
    always@(posedge clk) begin : WRITE_DATA_PATH
    
        r_data_fe_p1 <= data_fetch;
        r_data_fe_p2 <= r_data_fe_p1;
        
        r_data_oe_p3 <= |r_data_fe_p2;
        r_data_oe_p4 <= r_data_oe_p3;
        
        r_wr_data_p3[0] <= wr_data_b0 & {8{r_data_fe_p2[0]}}
                         | wr_data_b1 & {8{r_data_fe_p2[1]}};
        r_wr_data_p3[1] <= wr_data_b2 & {8{r_data_fe_p2[2]}}
                         | wr_data_b3 & {8{r_data_fe_p2[3]}};
        r_wr_data_p4    <= r_wr_data_p3[0]
                         | r_wr_data_p3[1];
    end
    


    always@(*) sdram_dq_o  = #Tco_dly r_wr_data_p4;
    always@(*) sdram_dq_oe = #Tco_dly r_data_oe_p4;

    

    
endmodule
module sdram_data_8b
(



    input             clk,




    output      [7:0] rd_data,
    
    input       [3:0] data_fetch,
    input       [7:0] wr_data_b0,
    input       [7:0] wr_data_b1,
    input       [7:0] wr_data_b2,
    input       [7:0] wr_data_b3,
    



    output reg        sdram_dq_oe,
    output reg  [7:0] sdram_dq_o,
    input       [7:0] sdram_dq_i
);


    parameter Tco_dly = 4.5;


    
    reg [7:0] r_rd_data;
    
    always@(posedge clk) begin : READ_DATA_PATH
    
        r_rd_data <= sdram_dq_i;
    end
    
    assign rd_data = r_rd_data;


    
    reg [3:0] r_data_fe_p1;
    reg [3:0] r_data_fe_p2;
    
    reg       r_data_oe_p3;
    reg       r_data_oe_p4;
    
    reg [7:0] r_wr_data_p3 [0:1];
    reg [7:0] r_wr_data_p4;
    
    always@(posedge clk) begin : WRITE_DATA_PATH
    
        r_data_fe_p1 <= data_fetch;
        r_data_fe_p2 <= r_data_fe_p1;
        
        r_data_oe_p3 <= |r_data_fe_p2;
        r_data_oe_p4 <= r_data_oe_p3;
        
        r_wr_data_p3[0] <= wr_data_b0 & {8{r_data_fe_p2[0]}}
                         | wr_data_b1 & {8{r_data_fe_p2[1]}};
        r_wr_data_p3[1] <= wr_data_b2 & {8{r_data_fe_p2[2]}}
                         | wr_data_b3 & {8{r_data_fe_p2[3]}};
        r_wr_data_p4    <= r_wr_data_p3[0]
                         | r_wr_data_p3[1];
    end
    


    always@(*) sdram_dq_o  = #Tco_dly r_wr_data_p4;
    always@(*) sdram_dq_oe = #Tco_dly r_data_oe_p4;

    

    
endmodule