data/full_repos/permissive/132439949/sources_1/new/A_delay.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/132439949/sources_1/new/A_delay.v:37: syntax error, unexpected '(', expecting IDENTIFIER\n    gen_delay2(clk_write, data_in, temp2);\n               ^~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module A_delay(
    input [11:0] data_in,
    input [1:0] switch,
    input clk_write,
    output reg [11:0] data_out
    );

  
    initial begin
        data_out = 12'b0;
    end
    
    wire [11:0] temp2, temp3;

    gen_delay2(clk_write, data_in, temp2);
    gen_delay3(clk_write, data_in, temp3);
       
    always @ (switch) begin
        case (switch)
            2'b00: data_out <= data_in;
            2'b01: data_out <= temp2;
            2'b10: data_out <= temp3;
            default: data_out <= data_in;

        endcase
    end
    
 

endmodule
module A_delay(
    input [11:0] data_in,
    input [1:0] switch,
    input clk_write,
    output reg [11:0] data_out
    );


  
    initial begin
        data_out = 12'b0;
    end
    
    wire [11:0] temp2, temp3;

    gen_delay2(clk_write, data_in, temp2);
    gen_delay3(clk_write, data_in, temp3);
       
    always @ (switch) begin
        case (switch)
            2'b00: data_out <= data_in;
            2'b01: data_out <= temp2;
            2'b10: data_out <= temp3;
            default: data_out <= data_in;

        endcase
    end
    
 

endmodule