data/full_repos/permissive/11455462/90522229_2 (1).v
1: b'%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_2.v:8: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_2.v:10: Unsupported: Ignoring delay on this delayed statement.\n#10 \n^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_2.v:12: Unsupported: Ignoring delay on this delayed statement.\n#10 \n^\n%Error: Cannot find file containing module: (1).v\n        ... Looked in:\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.v\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.sv\n             (1).v\n             (1).v.v\n             (1).v.sv\n             obj_dir/(1).v\n             obj_dir/(1).v.v\n             obj_dir/(1).v.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module encode_tb();
reg in,out,en;


initial begin
en = 1;
in = 1;
#10
in = 2;
#10 
in = 4;
#10 
in = 8;
end
encode24 test(out,in,en);



endmodule
module encode_tb();

reg in,out,en;


initial begin
en = 1;
in = 1;
#10
in = 2;
#10 
in = 4;
#10 
in = 8;
end
encode24 test(out,in,en);



endmodule