data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/s7_icap_wb.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/s7_icap_wb.v:142: Signal definition not found, creating implicitly: \'dat_0\'\n                                                                                                                                   : ... Suggested alternative: \'dat_i\'\n   assign dat_0 = 32\'h0;\n          ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/s7_icap_wb.v:129: Cannot find file containing module: \'ICAPE2\'\n   ICAPE2  #(\n   ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/ICAPE2\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/ICAPE2.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/ICAPE2.sv\n             ICAPE2\n             ICAPE2.v\n             ICAPE2.sv\n             obj_dir/ICAPE2\n             obj_dir/ICAPE2.v\n             obj_dir/ICAPE2.sv\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/s7_icap_wb.v:142: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                                                                : ... In instance s7_icap_wb\n   assign dat_0 = 32\'h0;\n                ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module s7_icap_wb
  (
   input clk, 
   input reset,
   input cyc_i, 
   input stb_i, 
   input we_i, 
   output ack_o,
   input [31:0] dat_i, 
   output [31:0] dat_o
   );

   reg 		 rdwrb, csib;
   

   reg [2:0]    icap_state;
   localparam ICAP_IDLE  = 0;
   localparam ICAP_WR0   = 1;
   localparam ICAP_WR1   = 2;
   localparam ICAP_RD0   = 3;
   localparam ICAP_RD1   = 4;

   localparam IDLE = 1'b1;
   localparam ACTIVE = 1'b0;
   localparam READ = 1'b1;
   localparam WRITE = 1'b0;
   

   always @(posedge clk)
     if(reset) begin
	rdwrb <= READ;
	csib <= IDLE;
       icap_state <= ICAP_IDLE;
     end
     else
       case(icap_state)




         ICAP_IDLE :
           begin
              if(stb_i & cyc_i) begin
                 if(we_i) begin

		    rdwrb <= WRITE;
		    csib <= IDLE;
		    icap_state <= ICAP_WR0;
		 end else begin

		    rdwrb <= READ;
		    csib <= IDLE;
		    icap_state <= ICAP_RD0;
		 end
	      end else begin

		 rdwrb <= READ;
		 csib <= IDLE;
		 icap_state <= ICAP_IDLE;
	      end
	   end




         ICAP_WR0 : begin
	    rdwrb <= WRITE;
	    csib <= ACTIVE;
            icap_state <= ICAP_WR1;
	 end




         ICAP_WR1 : begin
	    rdwrb <= WRITE;
	    csib <= IDLE;
            icap_state <= ICAP_IDLE;
	 end




         ICAP_RD0 : begin
            rdwrb <= READ;
	    csib <= ACTIVE;
            icap_state <= ICAP_WR1;
	 end




         ICAP_RD1 : begin
	    rdwrb <= READ;
	    csib <= IDLE;
            icap_state <= ICAP_IDLE;
	 end
        
       endcase

   assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);

 

   ICAPE2  #(
	     .DEVICE_ID(32'h03651093),
	     .ICAP_WIDTH("X32"),
	     .SIM_CFG_FILE_NAME("NONE")
	     )
     ICAPE2_inst  (
		   .O(),
		   .CLK(clk),
		   .CSIB(csib),
		   .I(dat_i[31:0]),
		   .RDWRB(rdwrb)
		   );
   
   assign dat_0 = 32'h0;
   
endmodule
module s7_icap_wb
  (
   input clk, 
   input reset,
   input cyc_i, 
   input stb_i, 
   input we_i, 
   output ack_o,
   input [31:0] dat_i, 
   output [31:0] dat_o
   );


   reg 		 rdwrb, csib;
   

   reg [2:0]    icap_state;
   localparam ICAP_IDLE  = 0;
   localparam ICAP_WR0   = 1;
   localparam ICAP_WR1   = 2;
   localparam ICAP_RD0   = 3;
   localparam ICAP_RD1   = 4;

   localparam IDLE = 1'b1;
   localparam ACTIVE = 1'b0;
   localparam READ = 1'b1;
   localparam WRITE = 1'b0;
   

   always @(posedge clk)
     if(reset) begin
	rdwrb <= READ;
	csib <= IDLE;
       icap_state <= ICAP_IDLE;
     end
     else
       case(icap_state)




         ICAP_IDLE :
           begin
              if(stb_i & cyc_i) begin
                 if(we_i) begin

		    rdwrb <= WRITE;
		    csib <= IDLE;
		    icap_state <= ICAP_WR0;
		 end else begin

		    rdwrb <= READ;
		    csib <= IDLE;
		    icap_state <= ICAP_RD0;
		 end
	      end else begin

		 rdwrb <= READ;
		 csib <= IDLE;
		 icap_state <= ICAP_IDLE;
	      end
	   end




         ICAP_WR0 : begin
	    rdwrb <= WRITE;
	    csib <= ACTIVE;
            icap_state <= ICAP_WR1;
	 end




         ICAP_WR1 : begin
	    rdwrb <= WRITE;
	    csib <= IDLE;
            icap_state <= ICAP_IDLE;
	 end




         ICAP_RD0 : begin
            rdwrb <= READ;
	    csib <= ACTIVE;
            icap_state <= ICAP_WR1;
	 end




         ICAP_RD1 : begin
	    rdwrb <= READ;
	    csib <= IDLE;
            icap_state <= ICAP_IDLE;
	 end
        
       endcase

   assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);

 

   ICAPE2  #(
	     .DEVICE_ID(32'h03651093),
	     .ICAP_WIDTH("X32"),
	     .SIM_CFG_FILE_NAME("NONE")
	     )
     ICAPE2_inst  (
		   .O(),
		   .CLK(clk),
		   .CSIB(csib),
		   .I(dat_i[31:0]),
		   .RDWRB(rdwrb)
		   );
   
   assign dat_0 = 32'h0;
   
endmodule