data/full_repos/permissive/150947952/scratch/cyclone10/ip/QUAD_ENCODER/QUAD_ENCODER.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/150947952/scratch/cyclone10/ip/QUAD_ENCODER/QUAD_ENCODER.sv:74: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n                                                                                                         : ... In instance QUAD_ENCODER\n    rRESYNC_ENCODER_A<={rRESYNC_ENCODER_A,iENCODER_A};\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/150947952/scratch/cyclone10/ip/QUAD_ENCODER/QUAD_ENCODER.sv:75: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n                                                                                                         : ... In instance QUAD_ENCODER\n    rRESYNC_ENCODER_B<={rRESYNC_ENCODER_B,iENCODER_B};\n                     ^~\n%Error: Exiting due to 2 warning(s)\n'
module QUAD_ENCODER #(
    pENCODERS=2,
    pENCODER_PRECISION=32
  )(
    input                             iCLK,
    input                             iRESET,

    input  [$clog2(pENCODERS)-1:0]	  iAVL_ADDRESS,
    input        	                    iAVL_READ,
    output reg [31:0]                 oAVL_READ_DATA,

    input [pENCODERS-1:0]             iENCODER_A,
    input [pENCODERS-1:0]             iENCODER_B
  );

  



reg [3:0][pENCODERS-1:0] rRESYNC_ENCODER_A,rRESYNC_ENCODER_B;


reg [pENCODERS-1:0][pENCODER_PRECISION-1:0] rSTEPS;













wire [pENCODERS-1:0] wENABLE =  rRESYNC_ENCODER_A[2]^rRESYNC_ENCODER_A[3]^rRESYNC_ENCODER_B[2]^rRESYNC_ENCODER_B[3];
wire [pENCODERS-1:0] wDIRECTION = rRESYNC_ENCODER_A[2]^rRESYNC_ENCODER_B[3];

integer i;

initial rSTEPS <=0;

always @(posedge iCLK)
begin
  if (iRESET) begin
    rSTEPS<=0;
    rRESYNC_ENCODER_A<=0;
    rRESYNC_ENCODER_B<=0;
  end
  else begin


    rRESYNC_ENCODER_A<={rRESYNC_ENCODER_A,iENCODER_A};
    rRESYNC_ENCODER_B<={rRESYNC_ENCODER_B,iENCODER_B};

    for (i=0;i<pENCODERS;i=i+1)
    begin

      if (wENABLE[i])

        rSTEPS[i] <= rSTEPS[i]+ ((wDIRECTION[i]) ? 1 : -1);
    end

    if (iAVL_READ)
    begin

      oAVL_READ_DATA<= rSTEPS[iAVL_ADDRESS];
    end
  end
end

endmodule
module QUAD_ENCODER #(
    pENCODERS=2,
    pENCODER_PRECISION=32
  )(
    input                             iCLK,
    input                             iRESET,

    input  [$clog2(pENCODERS)-1:0]	  iAVL_ADDRESS,
    input        	                    iAVL_READ,
    output reg [31:0]                 oAVL_READ_DATA,

    input [pENCODERS-1:0]             iENCODER_A,
    input [pENCODERS-1:0]             iENCODER_B
  );


  



reg [3:0][pENCODERS-1:0] rRESYNC_ENCODER_A,rRESYNC_ENCODER_B;


reg [pENCODERS-1:0][pENCODER_PRECISION-1:0] rSTEPS;













wire [pENCODERS-1:0] wENABLE =  rRESYNC_ENCODER_A[2]^rRESYNC_ENCODER_A[3]^rRESYNC_ENCODER_B[2]^rRESYNC_ENCODER_B[3];
wire [pENCODERS-1:0] wDIRECTION = rRESYNC_ENCODER_A[2]^rRESYNC_ENCODER_B[3];

integer i;

initial rSTEPS <=0;

always @(posedge iCLK)
begin
  if (iRESET) begin
    rSTEPS<=0;
    rRESYNC_ENCODER_A<=0;
    rRESYNC_ENCODER_B<=0;
  end
  else begin


    rRESYNC_ENCODER_A<={rRESYNC_ENCODER_A,iENCODER_A};
    rRESYNC_ENCODER_B<={rRESYNC_ENCODER_B,iENCODER_B};

    for (i=0;i<pENCODERS;i=i+1)
    begin

      if (wENABLE[i])

        rSTEPS[i] <= rSTEPS[i]+ ((wDIRECTION[i]) ? 1 : -1);
    end

    if (iAVL_READ)
    begin

      oAVL_READ_DATA<= rSTEPS[iAVL_ADDRESS];
    end
  end
end

endmodule