data/full_repos/permissive/181415525/endless_reader.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/181415525/endless_reader.v:78: Operator COND expects 33 bits on the Conditional True, but Conditional True\'s REPLICATE generates 32 bits.\n                                                                        : ... In instance endless_reader.mapper1\nassign long = (short[3] == 1\'b0) ? ({\n                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181415525/endless_reader.v:84: Operator COND expects 33 bits on the Conditional True, but Conditional True\'s CONST \'32\'h2\' generates 32 bits.\n                                                                        : ... In instance endless_reader.mapper1\n  (short ==  4\'hf) ? 32\'h00_00_00_02 : (\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181415525/endless_reader.v:85: Operator COND expects 33 bits on the Conditional True, but Conditional True\'s CONST \'32\'h1\' generates 32 bits.\n                                                                        : ... In instance endless_reader.mapper1\n    (short == 4\'he) ? 32\'h00_00_00_01 : 32\'h00_00_00_00\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/181415525/endless_reader.v:85: Operator COND expects 33 bits on the Conditional False, but Conditional False\'s CONST \'32\'h0\' generates 32 bits.\n                                                                        : ... In instance endless_reader.mapper1\n    (short == 4\'he) ? 32\'h00_00_00_01 : 32\'h00_00_00_00\n                    ^\n%Error: data/full_repos/permissive/181415525/endless_reader.v:37: Cannot find file containing module: \'fifo\'\nfifo fifo1(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/181415525,data/full_repos/permissive/181415525/fifo\n             data/full_repos/permissive/181415525,data/full_repos/permissive/181415525/fifo.v\n             data/full_repos/permissive/181415525,data/full_repos/permissive/181415525/fifo.sv\n             fifo\n             fifo.v\n             fifo.sv\n             obj_dir/fifo\n             obj_dir/fifo.v\n             obj_dir/fifo.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module endless_reader(

  input wire clk,
  input wire rst_n,

	input	wire [31:0]	image_size,
	output	wire	mem_master_control_fixed_location,
	output	wire [31:0]	mem_master_control_read_base,
	output	wire [31:0]	mem_master_control_read_length,
	output	wire	mem_master_control_go,
	input		wire mem_master_control_done,
	input		wire mem_master_control_early_done,
	output	wire	mem_master_user_read_buffer,
	input		wire [31:0] mem_master_user_buffer_output_data,
	input		wire mem_master_user_data_available,
	output reg [31:0] length_left,
	input wire chip_sel,

  input wire rdclk,
  output wire [32:0] out_pix_data,
  output wire rdempty,
  input wire rdreq
);


wire wrfull;
wire wrreq;
wire [3:0] pix_data;

assign wrreq = mem_master_user_data_available && !wrfull;

color_mapper mapper1(
  .short(pix_data),
  .long(out_pix_data)
);

fifo fifo1(

	.aclr(~rst_n),
	.data(mem_master_user_buffer_output_data),
	.wrclk(clk),
	.wrreq(wrreq),
	.wrfull(wrfull),
	
	.rdclk(rdclk),
	.rdreq(rdreq),
	.q(pix_data),
	.rdempty(rdempty),

);
assign mem_master_control_fixed_location = 0;
assign mem_master_control_read_base = chip_sel ? 32'h800_0000 : 32'h810_0000;
assign mem_master_control_read_length = image_size;
assign mem_master_control_go = mem_master_control_early_done ;
assign mem_master_user_read_buffer = wrreq ;

always @ (posedge clk or negedge rst_n) begin

  if (rst_n == 0) begin
    length_left <= 32'd0;
  end else begin
    if (mem_master_user_read_buffer) begin
      length_left <= length_left == 32'd0 ? image_size - 4 : length_left - 4; 
    end else begin
      length_left <= length_left;
    end
  end

end
endmodule
module endless_reader(

  input wire clk,
  input wire rst_n,

	input	wire [31:0]	image_size,
	output	wire	mem_master_control_fixed_location,
	output	wire [31:0]	mem_master_control_read_base,
	output	wire [31:0]	mem_master_control_read_length,
	output	wire	mem_master_control_go,
	input		wire mem_master_control_done,
	input		wire mem_master_control_early_done,
	output	wire	mem_master_user_read_buffer,
	input		wire [31:0] mem_master_user_buffer_output_data,
	input		wire mem_master_user_data_available,
	output reg [31:0] length_left,
	input wire chip_sel,

  input wire rdclk,
  output wire [32:0] out_pix_data,
  output wire rdempty,
  input wire rdreq
);



wire wrfull;
wire wrreq;
wire [3:0] pix_data;

assign wrreq = mem_master_user_data_available && !wrfull;

color_mapper mapper1(
  .short(pix_data),
  .long(out_pix_data)
);

fifo fifo1(

	.aclr(~rst_n),
	.data(mem_master_user_buffer_output_data),
	.wrclk(clk),
	.wrreq(wrreq),
	.wrfull(wrfull),
	
	.rdclk(rdclk),
	.rdreq(rdreq),
	.q(pix_data),
	.rdempty(rdempty),

);
assign mem_master_control_fixed_location = 0;
assign mem_master_control_read_base = chip_sel ? 32'h800_0000 : 32'h810_0000;
assign mem_master_control_read_length = image_size;
assign mem_master_control_go = mem_master_control_early_done ;
assign mem_master_user_read_buffer = wrreq ;

always @ (posedge clk or negedge rst_n) begin

  if (rst_n == 0) begin
    length_left <= 32'd0;
  end else begin
    if (mem_master_user_read_buffer) begin
      length_left <= length_left == 32'd0 ? image_size - 4 : length_left - 4; 
    end else begin
      length_left <= length_left;
    end
  end

end
endmodule