data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/mult/mult_2_pipelined/mult_2_pipelined.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/mult/mult_2_pipelined/mult_2_pipelined.v:20: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                                             : ... In instance mult_2_pipelined\n  out = out_reg;\n  ^~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module mult_2_pipelined(clk, a, b, out);
parameter DATA_WIDTH = 2;
input [DATA_WIDTH - 1 : 0] a, b;
input clk;
output [DATA_WIDTH - 1 : 0] out;

reg [DATA_WIDTH - 1 : 0] a_reg;
reg [DATA_WIDTH - 1 : 0] b_reg;
reg [DATA_WIDTH - 1 : 0] out_reg;

always @(posedge clk) begin
  a_reg <= a;
  b_reg <= b;
  out_reg <= a_reg * b_reg;
  out = out_reg;
end

endmodule
module mult_2_pipelined(clk, a, b, out);

parameter DATA_WIDTH = 2;
input [DATA_WIDTH - 1 : 0] a, b;
input clk;
output [DATA_WIDTH - 1 : 0] out;

reg [DATA_WIDTH - 1 : 0] a_reg;
reg [DATA_WIDTH - 1 : 0] b_reg;
reg [DATA_WIDTH - 1 : 0] out_reg;

always @(posedge clk) begin
  a_reg <= a;
  b_reg <= b;
  out_reg <= a_reg * b_reg;
  out = out_reg;
end

endmodule