data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/axi_arbiter_rd.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/axi_arbiter_rd.v:71: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/axi_arbiter_rd.v:72: Cannot find include file: axi_arbiter.vh\n`include "axi_arbiter.vh" \n         ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module axi_arbiter_rd #(
  parameter Ports           = 2,
            DataBits        = 64,
            AddrBits        = 32,
            LenBits         = 4,
            NumPendingReads = 6,
            InBuffers       = 0,
            OutBuffer       = 1)
(
  input                            clk,
  input                            rst,

  input      [Ports-1:0]           slv_arvalid,
  output     [Ports-1:0]           slv_arready,
  input      [Ports*AddrBits-1:0]  slv_araddr,
  input      [Ports*LenBits-1:0]   slv_arlen,

  output reg [Ports-1:0]           slv_rvalid,
  input      [Ports-1:0]           slv_rready,
  output reg [Ports*DataBits-1:0]  slv_rdata,
  output reg [Ports*2-1:0]         slv_rresp,
  output reg [Ports-1:0]           slv_rlast,
  output     [Ports*4-1:0]         slv_rid,

  output                           mst_arvalid,
  input                            mst_arready,
  output     [AddrBits-1:0]        mst_araddr,
  output     [LenBits-1:0]         mst_arlen,
  output     [3:0]                 mst_arid,
  output     [2:0]                 mst_arsize,
  output     [1:0]                 mst_arburst,
  output     [1:0]                 mst_arlock,

  input                            mst_rvalid,
  output reg                       mst_rready,
  input      [3:0]                 mst_rid,
  input      [DataBits-1:0]        mst_rdata,
  input      [1:0]                 mst_rresp,
  input                            mst_rlast);

`include "util.vh"
`include "axi_arbiter.vh"

  localparam BytesPerWord = DataBits / 8;




  wire [Ports-1:0]      buf_arvalid;
  reg  [Ports-1:0]      buf_arready;
	wire [AddrBits-1:0]   buf_araddr[0:Ports-1];
  wire [LenBits-1:0]    buf_arlen [0:Ports-1];

  genvar n;
  generate
    for (n=0; n < Ports; n=n+1) begin: inbufs
      if (InBuffers) begin: inbuf

        stream_buf_r #(
          .DataBits (LenBits + AddrBits))
        rd_buf(
          .clk       (clk),
          .rst       (rst),
          .in_valid  (slv_arvalid[n]),
          .in_ready  (slv_arready[n]),
          .in_data   ({slv_arlen[n*LenBits +: LenBits],
                       slv_araddr[n*AddrBits +: AddrBits]}),
          .out_valid (buf_arvalid[n]),
          .out_ready (buf_arready[n]),
          .out_data  ({buf_arlen[n],
                       buf_araddr[n]})
        );

      end else begin: no_inbuf
        assign buf_arvalid[n] = slv_arvalid[n];
        assign buf_arlen[n]   = slv_arlen[n*LenBits +: LenBits];
        assign buf_araddr[n]  = slv_araddr[n*AddrBits +: AddrBits];
        assign slv_arready[n] = buf_arready[n];
      end
    end
  endgenerate




  reg [Ports-1:0]        grant, grant_nxt, request;
  reg [clog2(Ports)-1:0] sel;

  reg                    sel_arvalid;
  wire                   sel_arready;
  reg [AddrBits-1:0]     sel_araddr;
  reg [LenBits-1:0]      sel_arlen;

  always @(*) begin

    grant_nxt         = grant;


    sel               = onehot2bin(grant, Ports);


    sel_arvalid       = buf_arvalid[sel];
    sel_araddr        = buf_araddr[sel];
    sel_arlen         = buf_arlen[sel];


    buf_arready       = 0;
    buf_arready[sel]  = sel_arready;



    if (!sel_arvalid || sel_arready) begin
      request   = buf_arvalid;
      grant_nxt = round_robin(request, grant);
    end
  end



  always @(posedge clk) begin
    if (rst) grant <= 1;
    else     grant <= grant_nxt;
  end



  wire [1:0] split_valid, split_ready;
  stream_split split(
    .in_valid(sel_arvalid),
    .in_ready(sel_arready),
    .out_valid(split_valid),
    .out_ready(split_ready)
  );




  generate
    if (OutBuffer) begin: outbuf
    stream_buf_v #(
      .DataBits (LenBits + AddrBits))
    addr_obuf(
      .clk       (clk),
      .rst       (rst),
      .in_valid  (split_valid[0]),
      .in_ready  (split_ready[0]),
      .in_data   ({sel_arlen, sel_araddr}),
      .out_valid (mst_arvalid),
      .out_ready (mst_arready),
      .out_data  ({mst_arlen, mst_araddr})
    );
    end else begin: no_outbuf
      assign mst_arvalid    = split_valid[0];
      assign mst_arlen      = sel_arlen;
      assign mst_araddr     = sel_araddr;
      assign split_ready[0] = mst_arready;
    end
  endgenerate





  wire                     fifo_valid;
  reg                      fifo_ready;
  wire [clog2(Ports)-1:0]  fifo_sel;

  stream_fifo_1clk_regs #(
    .Width    (clog2(Ports)),
    .Depth    (NumPendingReads))
  fifo(
    .rst       (rst),
    .clk       (clk),

    .din_valid (split_valid[1]),
    .din_ready (split_ready[1]),
    .din_data  (sel),

    .dout_valid(fifo_valid),
    .dout_ready(fifo_ready),
    .dout_data (fifo_sel),
    .used      ());




  always @(*) begin

    slv_rvalid           = 0;


    slv_rvalid[fifo_sel] = mst_rvalid & fifo_valid;
    fifo_ready           = slv_rready[fifo_sel] & mst_rvalid & mst_rlast;
    mst_rready           = slv_rready[fifo_sel] & fifo_valid;


    slv_rdata            = {Ports{mst_rdata}};
    slv_rresp            = {Ports{mst_rresp}};
    slv_rlast            = {Ports{mst_rlast}};
  end

  assign slv_rid     = {Ports{4'b0}};
  assign mst_arid    = 4'b0;
  assign mst_arsize  = clog2(BytesPerWord);
  assign mst_arlock  = 1'b0;
  assign mst_arburst = 2'b01;

endmodule
module axi_arbiter_rd #(
  parameter Ports           = 2,
            DataBits        = 64,
            AddrBits        = 32,
            LenBits         = 4,
            NumPendingReads = 6,
            InBuffers       = 0,
            OutBuffer       = 1)
(
  input                            clk,
  input                            rst,

  input      [Ports-1:0]           slv_arvalid,
  output     [Ports-1:0]           slv_arready,
  input      [Ports*AddrBits-1:0]  slv_araddr,
  input      [Ports*LenBits-1:0]   slv_arlen,

  output reg [Ports-1:0]           slv_rvalid,
  input      [Ports-1:0]           slv_rready,
  output reg [Ports*DataBits-1:0]  slv_rdata,
  output reg [Ports*2-1:0]         slv_rresp,
  output reg [Ports-1:0]           slv_rlast,
  output     [Ports*4-1:0]         slv_rid,

  output                           mst_arvalid,
  input                            mst_arready,
  output     [AddrBits-1:0]        mst_araddr,
  output     [LenBits-1:0]         mst_arlen,
  output     [3:0]                 mst_arid,
  output     [2:0]                 mst_arsize,
  output     [1:0]                 mst_arburst,
  output     [1:0]                 mst_arlock,

  input                            mst_rvalid,
  output reg                       mst_rready,
  input      [3:0]                 mst_rid,
  input      [DataBits-1:0]        mst_rdata,
  input      [1:0]                 mst_rresp,
  input                            mst_rlast);


`include "util.vh"
`include "axi_arbiter.vh"

  localparam BytesPerWord = DataBits / 8;




  wire [Ports-1:0]      buf_arvalid;
  reg  [Ports-1:0]      buf_arready;
	wire [AddrBits-1:0]   buf_araddr[0:Ports-1];
  wire [LenBits-1:0]    buf_arlen [0:Ports-1];

  genvar n;
  generate
    for (n=0; n < Ports; n=n+1) begin: inbufs
      if (InBuffers) begin: inbuf

        stream_buf_r #(
          .DataBits (LenBits + AddrBits))
        rd_buf(
          .clk       (clk),
          .rst       (rst),
          .in_valid  (slv_arvalid[n]),
          .in_ready  (slv_arready[n]),
          .in_data   ({slv_arlen[n*LenBits +: LenBits],
                       slv_araddr[n*AddrBits +: AddrBits]}),
          .out_valid (buf_arvalid[n]),
          .out_ready (buf_arready[n]),
          .out_data  ({buf_arlen[n],
                       buf_araddr[n]})
        );

      end else begin: no_inbuf
        assign buf_arvalid[n] = slv_arvalid[n];
        assign buf_arlen[n]   = slv_arlen[n*LenBits +: LenBits];
        assign buf_araddr[n]  = slv_araddr[n*AddrBits +: AddrBits];
        assign slv_arready[n] = buf_arready[n];
      end
    end
  endgenerate




  reg [Ports-1:0]        grant, grant_nxt, request;
  reg [clog2(Ports)-1:0] sel;

  reg                    sel_arvalid;
  wire                   sel_arready;
  reg [AddrBits-1:0]     sel_araddr;
  reg [LenBits-1:0]      sel_arlen;

  always @(*) begin

    grant_nxt         = grant;


    sel               = onehot2bin(grant, Ports);


    sel_arvalid       = buf_arvalid[sel];
    sel_araddr        = buf_araddr[sel];
    sel_arlen         = buf_arlen[sel];


    buf_arready       = 0;
    buf_arready[sel]  = sel_arready;



    if (!sel_arvalid || sel_arready) begin
      request   = buf_arvalid;
      grant_nxt = round_robin(request, grant);
    end
  end



  always @(posedge clk) begin
    if (rst) grant <= 1;
    else     grant <= grant_nxt;
  end



  wire [1:0] split_valid, split_ready;
  stream_split split(
    .in_valid(sel_arvalid),
    .in_ready(sel_arready),
    .out_valid(split_valid),
    .out_ready(split_ready)
  );




  generate
    if (OutBuffer) begin: outbuf
    stream_buf_v #(
      .DataBits (LenBits + AddrBits))
    addr_obuf(
      .clk       (clk),
      .rst       (rst),
      .in_valid  (split_valid[0]),
      .in_ready  (split_ready[0]),
      .in_data   ({sel_arlen, sel_araddr}),
      .out_valid (mst_arvalid),
      .out_ready (mst_arready),
      .out_data  ({mst_arlen, mst_araddr})
    );
    end else begin: no_outbuf
      assign mst_arvalid    = split_valid[0];
      assign mst_arlen      = sel_arlen;
      assign mst_araddr     = sel_araddr;
      assign split_ready[0] = mst_arready;
    end
  endgenerate





  wire                     fifo_valid;
  reg                      fifo_ready;
  wire [clog2(Ports)-1:0]  fifo_sel;

  stream_fifo_1clk_regs #(
    .Width    (clog2(Ports)),
    .Depth    (NumPendingReads))
  fifo(
    .rst       (rst),
    .clk       (clk),

    .din_valid (split_valid[1]),
    .din_ready (split_ready[1]),
    .din_data  (sel),

    .dout_valid(fifo_valid),
    .dout_ready(fifo_ready),
    .dout_data (fifo_sel),
    .used      ());




  always @(*) begin

    slv_rvalid           = 0;


    slv_rvalid[fifo_sel] = mst_rvalid & fifo_valid;
    fifo_ready           = slv_rready[fifo_sel] & mst_rvalid & mst_rlast;
    mst_rready           = slv_rready[fifo_sel] & fifo_valid;


    slv_rdata            = {Ports{mst_rdata}};
    slv_rresp            = {Ports{mst_rresp}};
    slv_rlast            = {Ports{mst_rlast}};
  end

  assign slv_rid     = {Ports{4'b0}};
  assign mst_arid    = 4'b0;
  assign mst_arsize  = clog2(BytesPerWord);
  assign mst_arlock  = 1'b0;
  assign mst_arburst = 2'b01;

endmodule