data/full_repos/permissive/108698528/uart_out.v
1: b'%Warning-WIDTH: data/full_repos/permissive/108698528/uart_out.v:21: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n                                                                  : ... In instance uart_out\n assign final_packet = {1\'b1, packet_l, 1\'b0};\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/108698528/uart_out.v:23: Cannot find file containing module: \'sr_latch\'\n sr_latch #(8) latch_packet(packet, packet_l, clk, latch_set, latch_reset);\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/108698528,data/full_repos/permissive/108698528/sr_latch\n             data/full_repos/permissive/108698528,data/full_repos/permissive/108698528/sr_latch.v\n             data/full_repos/permissive/108698528,data/full_repos/permissive/108698528/sr_latch.sv\n             sr_latch\n             sr_latch.v\n             sr_latch.sv\n             obj_dir/sr_latch\n             obj_dir/sr_latch.v\n             obj_dir/sr_latch.sv\n%Error: data/full_repos/permissive/108698528/uart_out.v:31: Cannot find file containing module: \'up_counter\'\n up_counter #(32, ((1<<32)-1)) baud_control(baud_ctl_en, baud_ctl_clr, cycles, clk);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/108698528/uart_out.v:32: Cannot find file containing module: \'up_counter\'\n up_counter #(4,  ((1<< 4)-1)) packet_cnt(packet_cnt_en, packet_cnt_clr, packet_pos, clk);\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module uart_out(data_in, ready, rst, tx, tx_done, clk);
	parameter BIT_SIZE = 10415;
	parameter WORDSIZE = 8;

	input ready, clk, rst;
	input [WORDSIZE - 1:0] data_in;

	output reg tx, tx_done;


	wire [7:0] packet, packet_l;
	wire [10:0] final_packet;
	
	assign packet = data_in;
	assign final_packet = {1'b1, packet_l, 1'b0};
	reg latch_set, latch_reset;
	sr_latch #(8) latch_packet(packet, packet_l, clk, latch_set, latch_reset);
	
	

	wire [31:0] cycles;
	wire [3:0]  packet_pos; 
	reg baud_ctl_en, baud_ctl_clr, packet_cnt_en, packet_cnt_clr; 
	
	up_counter #(32, ((1<<32)-1)) baud_control(baud_ctl_en, baud_ctl_clr, cycles, clk);
	up_counter #(4,  ((1<< 4)-1)) packet_cnt(packet_cnt_en, packet_cnt_clr, packet_pos, clk);


	reg [2:0] state;
	parameter init = 0, wait_for_ready = 1, translate_input = 2, push = 3,
			 clock_wait = 4, done = 5;

	initial begin 
		state = init;
	end


	reg byte_done, bit_done;
	always @* begin
		if(packet_pos >= 10) byte_done = 1;
		else byte_done = 0;

		if(cycles >= BIT_SIZE) bit_done = 1;
		else bit_done = 0;
	end


	always @(posedge clk) begin 
		if(rst) state <= init;
		else begin 
		case(state)
			init: state <= wait_for_ready;
			wait_for_ready: begin 
				if(ready) state <= translate_input;
				else state <= wait_for_ready;
			end
			translate_input: state <= clock_wait;
			push: state <= clock_wait;
			clock_wait: begin 
				if(bit_done) begin 
					if(byte_done) state <= done;
					else state <= push;
				end
				else state <= clock_wait;
			end
			done: state <= wait_for_ready;
		endcase
		end 
	end


	always @* begin 
		if(state == init) latch_reset = 1;
		else latch_reset = 0;

		if(state == translate_input) latch_set = 1;
		else latch_set = 0;

		if(state == push) packet_cnt_en = 1;
		else packet_cnt_en = 0;

		if((state == done) || (state == init)) packet_cnt_clr = 1;
		else packet_cnt_clr = 0; 

		if(state == clock_wait) baud_ctl_en = 1;
		else baud_ctl_en = 0;

		if(state == clock_wait) baud_ctl_clr = 0;
		else baud_ctl_clr = 1;

		if(state == done) tx_done = 1;
		else tx_done = 0;

		if(packet_pos >= 10) tx = 1;
		else if((state == push) || (state == clock_wait)) 
			tx = final_packet[packet_pos];
		else tx = 1;
	end

endmodule
module uart_out(data_in, ready, rst, tx, tx_done, clk);

	parameter BIT_SIZE = 10415;
	parameter WORDSIZE = 8;

	input ready, clk, rst;
	input [WORDSIZE - 1:0] data_in;

	output reg tx, tx_done;


	wire [7:0] packet, packet_l;
	wire [10:0] final_packet;
	
	assign packet = data_in;
	assign final_packet = {1'b1, packet_l, 1'b0};
	reg latch_set, latch_reset;
	sr_latch #(8) latch_packet(packet, packet_l, clk, latch_set, latch_reset);
	
	

	wire [31:0] cycles;
	wire [3:0]  packet_pos; 
	reg baud_ctl_en, baud_ctl_clr, packet_cnt_en, packet_cnt_clr; 
	
	up_counter #(32, ((1<<32)-1)) baud_control(baud_ctl_en, baud_ctl_clr, cycles, clk);
	up_counter #(4,  ((1<< 4)-1)) packet_cnt(packet_cnt_en, packet_cnt_clr, packet_pos, clk);


	reg [2:0] state;
	parameter init = 0, wait_for_ready = 1, translate_input = 2, push = 3,
			 clock_wait = 4, done = 5;

	initial begin 
		state = init;
	end


	reg byte_done, bit_done;
	always @* begin
		if(packet_pos >= 10) byte_done = 1;
		else byte_done = 0;

		if(cycles >= BIT_SIZE) bit_done = 1;
		else bit_done = 0;
	end


	always @(posedge clk) begin 
		if(rst) state <= init;
		else begin 
		case(state)
			init: state <= wait_for_ready;
			wait_for_ready: begin 
				if(ready) state <= translate_input;
				else state <= wait_for_ready;
			end
			translate_input: state <= clock_wait;
			push: state <= clock_wait;
			clock_wait: begin 
				if(bit_done) begin 
					if(byte_done) state <= done;
					else state <= push;
				end
				else state <= clock_wait;
			end
			done: state <= wait_for_ready;
		endcase
		end 
	end


	always @* begin 
		if(state == init) latch_reset = 1;
		else latch_reset = 0;

		if(state == translate_input) latch_set = 1;
		else latch_set = 0;

		if(state == push) packet_cnt_en = 1;
		else packet_cnt_en = 0;

		if((state == done) || (state == init)) packet_cnt_clr = 1;
		else packet_cnt_clr = 0; 

		if(state == clock_wait) baud_ctl_en = 1;
		else baud_ctl_en = 0;

		if(state == clock_wait) baud_ctl_clr = 0;
		else baud_ctl_clr = 1;

		if(state == done) tx_done = 1;
		else tx_done = 0;

		if(packet_pos >= 10) tx = 1;
		else if((state == push) || (state == clock_wait)) 
			tx = final_packet[packet_pos];
		else tx = 1;
	end

endmodule