data/full_repos/permissive/181665138/verilog/capitolo_iv/Rete_Sequenziale_Asincrona.v
 line:51: before: "."
1: b"%Error: data/full_repos/permissive/181665138/verilog/capitolo_iv/Rete_Sequenziale_Asincrona.v:51: syntax error, unexpected '.', expecting TYPE-IDENTIFIER\n            S0: A = ...\n                    ^\n%Error: data/full_repos/permissive/181665138/verilog/capitolo_iv/Rete_Sequenziale_Asincrona.v:60: syntax error, unexpected '.', expecting TYPE-IDENTIFIER\n            S0: Z = ...\n                    ^\n%Error: Cannot continue\n"
module Rete_Sequenziale_Asincrona(z7_z0, x7_x0);
    input [7:0] x7_x0;
    output [7:0] z7_z0;

    wire [3:0] y3_y0;
    wire [3:0] a3_a0;

    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;

    assign #1 a3_a0 = A(y3_y0, z7_z0);

    assign #2 y3_y0 = a3_a0;

    assign #1 z7_z0 = Z(y3_y0);

    function [10:0] A;
        input [7:0] x7_x0;
        input [3:0] y3_y0;
        casex(y3_y0)
            S0: A = ...
                ...
            S3: A = ...
        endcase
    endfunction

    function [3:0] Z;
        input [3:0] y3_y0;
        casex(y3_y0)
            S0: Z = ...
                ...
            S3: Z = ...
        endcase
    endfunction
endmodule
module Rete_Sequenziale_Asincrona(z7_z0, x7_x0);

    input [7:0] x7_x0;
    output [7:0] z7_z0;

    wire [3:0] y3_y0;
    wire [3:0] a3_a0;

    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;

    assign #1 a3_a0 = A(y3_y0, z7_z0);

    assign #2 y3_y0 = a3_a0;

    assign #1 z7_z0 = Z(y3_y0);

    function [10:0] A;
        input [7:0] x7_x0;
        input [3:0] y3_y0;
        casex(y3_y0)
            S0: A = ...
                ...
            S3: A = ...
        endcase
    endfunction

    function [3:0] Z;
        input [3:0] y3_y0;
        casex(y3_y0)
            S0: Z = ...
                ...
            S3: Z = ...
        endcase
    endfunction
endmodule