data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:108: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:107: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:158: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:159: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:38: Cannot find file containing module: \'Keyboard_DEMO\'\nKeyboard_DEMO demo(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/Keyboard_DEMO\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/Keyboard_DEMO.v\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/Keyboard_DEMO.sv\n             Keyboard_DEMO\n             Keyboard_DEMO.v\n             Keyboard_DEMO.sv\n             obj_dir/Keyboard_DEMO\n             obj_dir/Keyboard_DEMO.v\n             obj_dir/Keyboard_DEMO.sv\n%Warning-WIDTH: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:69: Operator LT expects 64 bits on the LHS, but LHS\'s VARREF \'k\' generates 32 bits.\n                                                                               : ... In instance Test_VGA_Keyboard\n for (k=0; k < count; k = k+1)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:110: Operator TASKREF \'CLOCK\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'LOAD_RAM\' generates 32 bits.\n                                                                                : ... In instance Test_VGA_Keyboard\n    CLOCK(LOAD_RAM);\n    ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:150: Operator TASKREF \'CLOCK\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'FULL_CYCLE\' generates 32 bits.\n                                                                                : ... In instance Test_VGA_Keyboard\n    CLOCK(FULL_CYCLE);\n    ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/sim/Test_VGA_Keyboard.v:157: Operator TASKREF \'CLOCK\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'FULL_CYCLE\' generates 32 bits.\n                                                                                : ... In instance Test_VGA_Keyboard\n    CLOCK(FULL_CYCLE);\n    ^~~~~\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_VGA_Keyboard;

reg clk, rst;
reg ps2_clk, ps2_data;
wire ready, hsync, vsync;
wire [3:0] r, g, b;
reg [63:0] counter;

Keyboard_DEMO demo(
    .clk(clk),
    .rst(rst),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .ready(ready),
    .hsync(hsync),
    .vsync(vsync),
    .r(r),
    .g(g),
    .b(b)
);

task RESET;
begin
    rst = 0;
    clk = 0;
    ps2_clk = 1;
    ps2_data = 1;
    counter = 0;
    #5
    rst = 1;
    #5
    rst = 0;
end
endtask

task CLOCK;
	input [63:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
		counter = counter + 1;
	end
end
endtask

reg [10:0] payload;

task PS2_TRANSMIT;
	input [7:0] send;
	integer k;
begin
    
    payload = {1'b1, ~^send, send[7], send[6], send[5], send[4], send[3], send[2], send[1], send[0], 1'b0};
    $display("payload = 0b%b",payload);
	for (k=0; k < 11; k = k + 1)
	begin
        ps2_data = payload[k];
        ps2_clk = 1;
        $display("payload = 0b%b :: send = 0b%b :: ps2_data = 0b%b :: k = %d", payload, send, ps2_data, k);
        CLOCK(1);
        ps2_clk = 0;
        CLOCK(1);
	end
    ps2_clk = 1;
    CLOCK(1);
end
endtask

parameter LOAD_RAM = 32'd2400;
parameter FULL_CYCLE = 32'd1_555_738;

initial begin
    #10
    #10
	RESET;
    CLOCK(LOAD_RAM);

    CLOCK(5);
    PS2_TRANSMIT(`A_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`A_SCAN_CODE);
    CLOCK(10);

    PS2_TRANSMIT(`SHIFT_CODE_LEFT);
    CLOCK(10);

    PS2_TRANSMIT(`A_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`A_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`SHIFT_CODE_LEFT);
    CLOCK(10);

    PS2_TRANSMIT(`B_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`B_SCAN_CODE);
    CLOCK(10);

    PS2_TRANSMIT(8'h21);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(8'h21);
    CLOCK(10);

    PS2_TRANSMIT(8'h66);
    CLOCK(10);
    CLOCK(FULL_CYCLE);
    PS2_TRANSMIT(8'h21);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(8'h21);
    CLOCK(10);
    CLOCK(FULL_CYCLE);
    #10 $stop;
    #5 $finish;
end

endmodule
module Test_VGA_Keyboard;


reg clk, rst;
reg ps2_clk, ps2_data;
wire ready, hsync, vsync;
wire [3:0] r, g, b;
reg [63:0] counter;

Keyboard_DEMO demo(
    .clk(clk),
    .rst(rst),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .ready(ready),
    .hsync(hsync),
    .vsync(vsync),
    .r(r),
    .g(g),
    .b(b)
);

task RESET;
begin
    rst = 0;
    clk = 0;
    ps2_clk = 1;
    ps2_data = 1;
    counter = 0;
    #5
    rst = 1;
    #5
    rst = 0;
end
endtask

task CLOCK;
	input [63:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
		counter = counter + 1;
	end
end
endtask

reg [10:0] payload;

task PS2_TRANSMIT;
	input [7:0] send;
	integer k;
begin
    
    payload = {1'b1, ~^send, send[7], send[6], send[5], send[4], send[3], send[2], send[1], send[0], 1'b0};
    $display("payload = 0b%b",payload);
	for (k=0; k < 11; k = k + 1)
	begin
        ps2_data = payload[k];
        ps2_clk = 1;
        $display("payload = 0b%b :: send = 0b%b :: ps2_data = 0b%b :: k = %d", payload, send, ps2_data, k);
        CLOCK(1);
        ps2_clk = 0;
        CLOCK(1);
	end
    ps2_clk = 1;
    CLOCK(1);
end
endtask

parameter LOAD_RAM = 32'd2400;
parameter FULL_CYCLE = 32'd1_555_738;

initial begin
    #10
    #10
	RESET;
    CLOCK(LOAD_RAM);

    CLOCK(5);
    PS2_TRANSMIT(`A_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`A_SCAN_CODE);
    CLOCK(10);

    PS2_TRANSMIT(`SHIFT_CODE_LEFT);
    CLOCK(10);

    PS2_TRANSMIT(`A_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`A_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`SHIFT_CODE_LEFT);
    CLOCK(10);

    PS2_TRANSMIT(`B_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`B_SCAN_CODE);
    CLOCK(10);

    PS2_TRANSMIT(8'h21);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(8'h21);
    CLOCK(10);

    PS2_TRANSMIT(8'h66);
    CLOCK(10);
    CLOCK(FULL_CYCLE);
    PS2_TRANSMIT(8'h21);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(8'h21);
    CLOCK(10);
    CLOCK(FULL_CYCLE);
    #10 $stop;
    #5 $finish;
end

endmodule