data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v
None: at end of input
1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n             const_defination.v\n             const_defination.v.v\n             const_defination.v.sv\n             obj_dir/const_defination.v\n             obj_dir/const_defination.v.v\n             obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:26: Define or directive not defined: \'`icodeBus\'\n    input wire[`icodeBus] icode,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:26: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`icodeBus] icode,\n                        ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:27: Define or directive not defined: \'`ifunBus\'\n    input wire[`ifunBus] ifun,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:28: Define or directive not defined: \'`icodeBus\'\n    input wire[`icodeBus] reg1_read_src,reg2_read_src,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:29: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] valC,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:30: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] valP,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire bubble,stall,   \n ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[`icodeBus] D_icode,\n    ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:35: Define or directive not defined: \'`icodeBus\'\n    output reg[`icodeBus] D_icode,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:36: Define or directive not defined: \'`ifunBus\'\n    output reg[`ifunBus] D_ifun,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:37: Define or directive not defined: \'`regBus\'\n    output reg[`regBus] D_reg1_read_src,D_reg2_read_src,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:38: Define or directive not defined: \'`digitsBus\'\n    output reg[`digitsBus] D_valC,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:39: Define or directive not defined: \'`digitsBus\'\n    output reg[`digitsBus]  D_valP,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:41: syntax error, unexpected \')\', expecting \',\' or \';\'\n    );\n    ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:46: Define or directive not defined: \'`stop\'\n        else if(stat==`stop||stat==`inst_invalid||bubble==1)\n                      ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:46: Define or directive not defined: \'`inst_invalid\'\n        else if(stat==`stop||stat==`inst_invalid||bubble==1)\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:48: Define or directive not defined: \'`Nop\'\n            D_icode<=`Nop;\n                     ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:50: Define or directive not defined: \'`readZero\'\n            D_valP<=`readZero;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:51: Define or directive not defined: \'`NONE\'\n            D_reg1_read_src<=`NONE;\n                             ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decodeReg.v:52: Define or directive not defined: \'`NONE\'\n            D_reg2_read_src<=`NONE;\n                             ^~~~~\n%Error: Exiting due to 21 error(s)\n'
module decodeReg(
	input clk,
    input wire[`icodeBus] icode,
    input wire[`ifunBus] ifun,
    input wire[`icodeBus] reg1_read_src,reg2_read_src,
    input wire[`digitsBus] valC,
    input wire[`digitsBus] valP,
    input wire[2:0] stat,
	input wire bubble,stall,
    

    output reg[`icodeBus] D_icode,
    output reg[`ifunBus] D_ifun,
    output reg[`regBus] D_reg1_read_src,D_reg2_read_src,
    output reg[`digitsBus] D_valC,
    output reg[`digitsBus]  D_valP,
    output reg[2:0] D_stat
    );
    always@(posedge clk)
    begin
		if(stall==1)
		begin end
        else if(stat==`stop||stat==`inst_invalid||bubble==1)
        begin
            D_icode<=`Nop;
            D_ifun<=0;
            D_valP<=`readZero;
            D_reg1_read_src<=`NONE;
            D_reg2_read_src<=`NONE;
            D_valP<=0;
            D_valC<=0;
            D_stat<=stat;
        end
        else 
        begin
            D_icode<=icode;
            D_ifun<=ifun;
            D_valP<=valP;
            D_reg1_read_src<=reg1_read_src;
            D_reg2_read_src<=reg2_read_src;
            D_valP<=valP;
            D_valC<=valC;
            D_stat<=stat;
        end
    end
endmodule
module decodeReg(
	input clk,
    input wire[`icodeBus] icode,
    input wire[`ifunBus] ifun,
    input wire[`icodeBus] reg1_read_src,reg2_read_src,
    input wire[`digitsBus] valC,
    input wire[`digitsBus] valP,
    input wire[2:0] stat,
	input wire bubble,stall,
    

    output reg[`icodeBus] D_icode,
    output reg[`ifunBus] D_ifun,
    output reg[`regBus] D_reg1_read_src,D_reg2_read_src,
    output reg[`digitsBus] D_valC,
    output reg[`digitsBus]  D_valP,
    output reg[2:0] D_stat
    );

    always@(posedge clk)
    begin
		if(stall==1)
		begin end
        else if(stat==`stop||stat==`inst_invalid||bubble==1)
        begin
            D_icode<=`Nop;
            D_ifun<=0;
            D_valP<=`readZero;
            D_reg1_read_src<=`NONE;
            D_reg2_read_src<=`NONE;
            D_valP<=0;
            D_valC<=0;
            D_stat<=stat;
        end
        else 
        begin
            D_icode<=icode;
            D_ifun<=ifun;
            D_valP<=valP;
            D_reg1_read_src<=reg1_read_src;
            D_reg2_read_src<=reg2_read_src;
            D_valP<=valP;
            D_valC<=valC;
            D_stat<=stat;
        end
    end
endmodule