data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate.v
None: at end of input
1: b"%Error: data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate.v:12: Duplicate declaration of signal: 'xy_2'\n                                                                                                  : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg xy_2;\n    ^~~~\n        data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate.v:6: ... Location of original declaration\n    output xy_2,      \n           ^~~~\n%Error: data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate.v:13: Duplicate declaration of signal: 'xy_3'\nreg xy_3;\n    ^~~~\n        data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate.v:7: ... Location of original declaration\n    output xy_3,      \n           ^~~~\n%Error: Exiting due to 2 error(s)\n"
module and_gate(
    input  x,
    input  y,
    output xy_1,
    output xy_2,
    output xy_3,
    output xy_4
);


reg xy_2;
reg xy_3;


assign xy_1 = x & y;


always @ ( * ) begin
    xy_2 <= x & y;
end



always @ ( * ) begin
    xy_3 = x & y;
end


and(xy_4, x, y);

endmodule
module and_gate(
    input  x,
    input  y,
    output xy_1,
    output xy_2,
    output xy_3,
    output xy_4
);



reg xy_2;
reg xy_3;


assign xy_1 = x & y;


always @ ( * ) begin
    xy_2 <= x & y;
end



always @ ( * ) begin
    xy_3 = x & y;
end


and(xy_4, x, y);

endmodule