data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:18: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr,data/full_repos/permissive/214858095/test_exec.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr,data/full_repos/permissive/214858095/test_exec.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr,data/full_repos/permissive/214858095/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:20: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgTestExec::*;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:72: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);\n                                               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:75: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t  chdr_word_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:76: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::item_t       item_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:77: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::item_queue_t item_queue_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:79: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrPacket #(CHDR_W) ChdrPacket_t;\n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:165: Unsupported: classes\n  class Rand #(WIDTH = 32);\n  ^~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:166: Unsupported: \'static\' class item\n    static function logic [WIDTH-1:0] rand_logic();\n    ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:170: Unsupported or unknown PLI call: $urandom\n        result = {result, $urandom()};\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:196: syntax error, unexpected IDENTIFIER, expecting \'(\' or \';\'\n  function automatic ChdrPacket_t gen_rand_chdr_pkt(\n                                  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:200: syntax error, unexpected \'=\', expecting \',\' or \';\'\n    ChdrPacket_t     packet = new();\n                            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:208: syntax error, unexpected \'=\', expecting IDENTIFIER\n    header = Rand#($bits(header))::rand_logic();\n           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:210: syntax error, unexpected \'=\', expecting IDENTIFIER\n    header.pkt_type = ($urandom() & 1) ? CHDR_DATA_NO_TS : CHDR_DATA_WITH_TS;\n                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:210: Unsupported or unknown PLI call: $urandom\n    header.pkt_type = ($urandom() & 1) ? CHDR_DATA_NO_TS : CHDR_DATA_WITH_TS;\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:214: Unsupported or unknown PLI call: $urandom_range\n    repeat ($urandom_range(0, max_mdata));\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:215: syntax error, unexpected \'(\', expecting IDENTIFIER\n      mdata.push_back(Rand#(CHDR_W)::rand_logic());\n                      ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:217: Unsupported or unknown PLI call: $urandom_range\n    num_samps = $urandom_range(1, max_samps);\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:222: syntax error, unexpected \'(\', expecting IDENTIFIER\n      data.push_back(Rand#(CHDR_W)::rand_logic());\n                     ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:225: syntax error, unexpected \'(\', expecting IDENTIFIER\n    packet.write_raw(header, data, mdata, timestamp, num_samps * (ITEM_W/8));\n                     ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:232: syntax error, unexpected \'=\', expecting \',\' or \';\'\n    mailbox #(ChdrPacket_t) packets = new();\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:235: syntax error, unexpected int, expecting IDENTIFIER or genvar\n    for (int packet_count = 0; packet_count < num_packets; packet_count++) begin\n         ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:239: syntax error, unexpected \'(\', expecting IDENTIFIER\n      packets.put(packet);\n                  ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:240: syntax error, unexpected \'(\', expecting IDENTIFIER\n      blk_ctrl.put_chdr(port, packet);\n                        ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:251: syntax error, unexpected \'(\', expecting IDENTIFIER\n      packets.get(sent_packet);\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:273: syntax error, unexpected \'=\', expecting IDENTIFIER\n      expected_header.length = recv_packet.header.length;\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:274: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(expected_header == recv_packet.header,\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:279: Define or directive not defined: \'`ASSERT_ERROR\'\n        `ASSERT_ERROR(sent_packet.timestamp == recv_packet.timestamp,\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:279: syntax error, unexpected \'(\'\n        `ASSERT_ERROR(sent_packet.timestamp == recv_packet.timestamp,\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:284: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(sent_packet.metadata.size() == recv_packet.metadata.size(),\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:287: Define or directive not defined: \'`ASSERT_ERROR\'\n        `ASSERT_ERROR(sent_packet.metadata[i] == recv_packet.metadata[i],\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:292: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:302: syntax error, unexpected \'=\', expecting IDENTIFIER\n        if (error < 0) error = -error;\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:303: Define or directive not defined: \'`ASSERT_ERROR\'\n        `ASSERT_ERROR(\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:322: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_tb($sformatf("rfnoc_block_logpwr_tb (CHDR_W = %0d)", CHDR_W));\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:327: syntax error, unexpected \'(\', expecting IDENTIFIER\n    rfnoc_chdr_clk_gen.start();\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:328: syntax error, unexpected \'(\', expecting IDENTIFIER\n    rfnoc_ctrl_clk_gen.start();\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:329: syntax error, unexpected \'(\', expecting IDENTIFIER\n    ce_clk_gen.start();\n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:332: syntax error, unexpected \'(\', expecting IDENTIFIER\n    blk_ctrl.run();\n                 ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:338: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Flush block then reset it", 10us);\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:339: syntax error, unexpected \'(\', expecting IDENTIFIER\n    blk_ctrl.flush_and_reset();\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:340: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:346: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Verify Block Info", 2us);\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:347: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:348: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:349: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:350: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:351: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:361: syntax error, unexpected \'(\', expecting IDENTIFIER\n      test.start_test($sformatf("Test random packets (port %0d)", port), 1ms);\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_logpwr/rfnoc_block_logpwr_tb.sv:363: syntax error, unexpected \'(\', expecting IDENTIFIER\n      test.end_test();\n                    ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
function automatic ChdrPacket_t gen_rand_chdr_pkt(
    int max_samps = SPP,
    int max_mdata = 31
  );
    ChdrPacket_t     packet = new();
    chdr_header_t    header;
    chdr_word_t      data[$];
    chdr_word_t      mdata[$];
    chdr_timestamp_t timestamp;
    int              num_samps;


    header = Rand#($bits(header))::rand_logic();

    header.pkt_type = ($urandom() & 1) ? CHDR_DATA_NO_TS : CHDR_DATA_WITH_TS;

    timestamp = Rand#(64)::rand_logic();

    repeat ($urandom_range(0, max_mdata));
      mdata.push_back(Rand#(CHDR_W)::rand_logic());

    num_samps = $urandom_range(1, max_samps);
    repeat (num_samps * ITEM_W / CHDR_W)
      data.push_back(Rand#(CHDR_W)::rand_logic());

    if (num_samps * ITEM_W % CHDR_W != 0)
      data.push_back(Rand#(CHDR_W)::rand_logic());


    packet.write_raw(header, data, mdata, timestamp, num_samps * (ITEM_W/8));

    return packet;
  endfunction
function automatic ChdrPacket_t gen_rand_chdr_pkt(
    int max_samps = SPP,
    int max_mdata = 31
  );

    ChdrPacket_t     packet = new();
    chdr_header_t    header;
    chdr_word_t      data[$];
    chdr_word_t      mdata[$];
    chdr_timestamp_t timestamp;
    int              num_samps;


    header = Rand#($bits(header))::rand_logic();

    header.pkt_type = ($urandom() & 1) ? CHDR_DATA_NO_TS : CHDR_DATA_WITH_TS;

    timestamp = Rand#(64)::rand_logic();

    repeat ($urandom_range(0, max_mdata));
      mdata.push_back(Rand#(CHDR_W)::rand_logic());

    num_samps = $urandom_range(1, max_samps);
    repeat (num_samps * ITEM_W / CHDR_W)
      data.push_back(Rand#(CHDR_W)::rand_logic());

    if (num_samps * ITEM_W % CHDR_W != 0)
      data.push_back(Rand#(CHDR_W)::rand_logic());


    packet.write_raw(header, data, mdata, timestamp, num_samps * (ITEM_W/8));

    return packet;
  endfunction