data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/cells_sim.v
 line:48: before: "="
1: b'%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/cells_sim.v:492: Cannot find include file: qlal4s3b_sim.v\n`include "qlal4s3b_sim.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220229160/ql-qlf-plugin/pp3,data/full_repos/permissive/220229160/qlal4s3b_sim.v\n             data/full_repos/permissive/220229160/ql-qlf-plugin/pp3,data/full_repos/permissive/220229160/qlal4s3b_sim.v.v\n             data/full_repos/permissive/220229160/ql-qlf-plugin/pp3,data/full_repos/permissive/220229160/qlal4s3b_sim.v.sv\n             qlal4s3b_sim.v\n             qlal4s3b_sim.v.v\n             qlal4s3b_sim.v.sv\n             obj_dir/qlal4s3b_sim.v\n             obj_dir/qlal4s3b_sim.v.v\n             obj_dir/qlal4s3b_sim.v.sv\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/cells_sim.v:494: Cannot find include file: qlal3_sim.v\n`include "qlal3_sim.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/cells_sim.v:496: Cannot find include file: brams_sim.v\n`include "brams_sim.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/cells_sim.v:498: Cannot find include file: mult_sim.v\n`include "mult_sim.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module dffepc (
    output reg Q,
    input D,
    (* clkbuf_sink *)
    input CLK,
    input EN,
    (* clkbuf_sink *)
    input CLR,
    (* clkbuf_sink *)
    input PRE
);
  parameter [0:0] INIT = 1'b0;

  specify
    if (EN) (posedge CLK => (Q : D)) = 1701;
    if (CLR) (CLR => Q) = 967;
    if (PRE) (PRE => Q) = 1252;
    $setup(D, posedge CLK, 216);
    $setup(EN, posedge CLK, 590);
  endspecify

  initial Q = INIT;
  always @(posedge CLK or posedge CLR or posedge PRE)
    if (CLR) Q <= 1'b0;
    else if (PRE) Q <= 1'b1;
    else if (EN) Q <= D;
endmodule
module dffepc (
    output reg Q,
    input D,
    (* clkbuf_sink *)
    input CLK,
    input EN,
    (* clkbuf_sink *)
    input CLR,
    (* clkbuf_sink *)
    input PRE
);

  parameter [0:0] INIT = 1'b0;

  specify
    if (EN) (posedge CLK => (Q : D)) = 1701;
    if (CLR) (CLR => Q) = 967;
    if (PRE) (PRE => Q) = 1252;
    $setup(D, posedge CLK, 216);
    $setup(EN, posedge CLK, 590);
  endspecify

  initial Q = INIT;
  always @(posedge CLK or posedge CLR or posedge PRE)
    if (CLR) Q <= 1'b0;
    else if (PRE) Q <= 1'b1;
    else if (EN) Q <= D;
endmodule