data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v
1: b"%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:95: Cannot find file containing module: 'AO1C'\n    AO1C AO1C_3 (.A(DataOut_2_0[3]), .B(DataOut_2[3]), .C(NOR2A_0_Y), \n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis,data/full_repos/permissive/165160692/AO1C\n             data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis,data/full_repos/permissive/165160692/AO1C.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis,data/full_repos/permissive/165160692/AO1C.sv\n             AO1C\n             AO1C.v\n             AO1C.sv\n             obj_dir/AO1C\n             obj_dir/AO1C.v\n             obj_dir/AO1C.sv\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:97: Cannot find file containing module: 'AO1C'\n    AO1C AO1C_2 (.A(DataOut_2[3]), .B(DataOut_2_0[3]), .C(AO1C_3_Y), \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:99: Cannot find file containing module: 'AO1C'\n    AO1C AO1C_5 (.A(DataOut_2_0[5]), .B(DataOut_2[5]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:101: Cannot find file containing module: 'NOR3A'\n    NOR3A NOR3A_0 (.A(OR2A_3_Y), .B(AO1C_5_Y), .C(DataOut_2[4]), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:103: Cannot find file containing module: 'GND'\n    GND GND_i_0 (.Y(GND_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:104: Cannot find file containing module: 'AO1D'\n    AO1D AO1D_0 (.A(AO1C_1_Y), .B(AO1C_4_Y), .C(AO1C_2_Y), .Y(AO1D_0_Y)\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:106: Cannot find file containing module: 'AND2A'\n    AND2A AND_SIGN (.A(DataOut_2[7]), .B(DataOut_2_0[7]), .Y(U2));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:107: Cannot find file containing module: 'AO1C'\n    AO1C AO1C_0 (.A(DataA_c[0]), .B(DataB_c[0]), .C(OR2A_1_Y), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:109: Cannot find file containing module: 'AND3'\n    AND3 AND3_0 (.A(XNOR2_1_Y), .B(XNOR2_0_Y), .C(XNOR2_2_Y), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:111: Cannot find file containing module: 'VCC'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:112: Cannot find file containing module: 'AO1C'\n    AO1C AO1C_4 (.A(DataOut_2_0[2]), .B(DataOut_2[2]), .C(OR2A_0_Y), \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:114: Cannot find file containing module: 'OR2A'\n    OR2A OR2A_0 (.A(DataOut_2[1]), .B(DataOut_2_0[1]), .Y(OR2A_0_Y));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:115: Cannot find file containing module: 'NAND3A'\n    NAND3A NAND3A_1 (.A(DataOut_2[5]), .B(DataOut_2_0[5]), .C(OR2A_3_Y)\n    ^~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:117: Cannot find file containing module: 'OR2A'\n    OR2A OR2A_3 (.A(DataOut_2[6]), .B(DataOut_2_0[6]), .Y(OR2A_3_Y));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:118: Cannot find file containing module: 'NOR2A'\n    NOR2A NOR2A_0 (.A(DataOut_2_0[2]), .B(DataOut_2[2]), .Y(NOR2A_0_Y));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:119: Cannot find file containing module: 'GND'\n    GND GND_i (.Y(GND));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:120: Cannot find file containing module: 'AO1C'\n    AO1C AO1C_1 (.A(DataOut_2_0[3]), .B(DataOut_2[3]), .C(AO1C_0_Y), \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:122: Cannot find file containing module: 'XNOR2'\n    XNOR2 XNOR2_0 (.A(DataOut_2_0[5]), .B(DataOut_2[5]), .Y(XNOR2_0_Y));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:123: Cannot find file containing module: 'XNOR2'\n    XNOR2 XNOR2_2 (.A(DataOut_2_0[6]), .B(DataOut_2[6]), .Y(XNOR2_2_Y));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:124: Cannot find file containing module: 'OR2A'\n    OR2A OR2A_2 (.A(DataOut_2_0[6]), .B(DataOut_2[6]), .Y(OR2A_2_Y));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:125: Cannot find file containing module: 'NAND3A'\n    NAND3A NAND3A_0 (.A(NOR3A_0_Y), .B(OR2A_2_Y), .C(NAND3A_1_Y), .Y(\n    ^~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:127: Cannot find file containing module: 'AO1'\n    AO1 AND_AO21 (.A(le_OUT), .B(U1), .C(U2), .Y(AGEB_c));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:128: Cannot find file containing module: 'VCC'\n    VCC VCC_i_0 (.Y(VCC_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:129: Cannot find file containing module: 'OR2A'\n    OR2A OR2A_1 (.A(DataOut_2_0[1]), .B(DataOut_2[1]), .Y(OR2A_1_Y));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:130: Cannot find file containing module: 'XNOR2'\n    XNOR2 XNOR2_1 (.A(DataOut_2_0[4]), .B(DataOut_2[4]), .Y(XNOR2_1_Y));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:131: Cannot find file containing module: 'OR2A'\n    OR2A OR_SIGN (.A(DataOut_2[7]), .B(DataOut_2_0[7]), .Y(U1));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:132: Cannot find file containing module: 'AOI1'\n    AOI1 AOI1_le_OUT (.A(AND3_0_Y), .B(AO1D_0_Y), .C(NAND3A_0_Y), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:50: Cannot find file containing module: 'AX1C'\n    AX1C \\DataOut_2[1]  (.A(DataB_c[0]), .B(DataB_c[7]), .C(DataB_c[1])\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:52: Cannot find file containing module: 'AX1C'\n    AX1C \\DataOut_2[3]  (.A(CO2), .B(DataB_c[7]), .C(DataB_c[3]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:54: Cannot find file containing module: 'OR2'\n    OR2 DataOut_1_1_ANC2 (.A(DataB_c[2]), .B(CO1), .Y(CO2));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:55: Cannot find file containing module: 'VCC'\n    VCC VCC_i_0 (.Y(VCC_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:56: Cannot find file containing module: 'VCC'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:57: Cannot find file containing module: 'OR2'\n    OR2 DataOut_1_1_ANC5 (.A(DataB_c[5]), .B(CO4), .Y(CO5));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:58: Cannot find file containing module: 'OR2'\n    OR2 DataOut_1_1_ANC4 (.A(DataB_c[4]), .B(CO3), .Y(CO4));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:59: Cannot find file containing module: 'OR2'\n    OR2 DataOut_1_1_ANC3 (.A(DataB_c[3]), .B(CO2), .Y(CO3));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:60: Cannot find file containing module: 'AX1C'\n    AX1C \\DataOut_2[2]  (.A(CO1), .B(DataB_c[7]), .C(DataB_c[2]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:62: Cannot find file containing module: 'GND'\n    GND GND_i_0 (.Y(GND_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:63: Cannot find file containing module: 'GND'\n    GND GND_i (.Y(GND));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:64: Cannot find file containing module: 'OA1'\n    OA1 \\DataOut_2[7]  (.A(CO5), .B(DataB_c[6]), .C(DataB_c[7]), .Y(\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:66: Cannot find file containing module: 'OR2'\n    OR2 DataOut_1_1_ANC1 (.A(DataB_c[1]), .B(DataB_c[0]), .Y(CO1));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:67: Cannot find file containing module: 'AX1C'\n    AX1C \\DataOut_2[6]  (.A(CO5), .B(DataB_c[7]), .C(DataB_c[6]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:69: Cannot find file containing module: 'AX1C'\n    AX1C \\DataOut_2[5]  (.A(CO4), .B(DataB_c[7]), .C(DataB_c[5]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:71: Cannot find file containing module: 'AX1C'\n    AX1C \\DataOut_2[4]  (.A(CO3), .B(DataB_c[7]), .C(DataB_c[4]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:14: Cannot find file containing module: 'AX1C'\n    AX1C \\DataOut_2[1]  (.A(DataA_c[0]), .B(DataA_c[7]), .C(DataA_c[1])\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:16: Cannot find file containing module: 'AX1C'\n    AX1C \\DataOut_2[3]  (.A(CO2), .B(DataA_c[7]), .C(DataA_c[3]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:18: Cannot find file containing module: 'OR2'\n    OR2 DataOut_1_1_ANC2 (.A(DataA_c[2]), .B(CO1), .Y(CO2));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:19: Cannot find file containing module: 'VCC'\n    VCC VCC_i_0 (.Y(VCC_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:20: Cannot find file containing module: 'VCC'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:21: Cannot find file containing module: 'OR2'\n    OR2 DataOut_1_1_ANC5 (.A(DataA_c[5]), .B(CO4), .Y(CO5));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_sign_cmp/synthesis/XYF.v:22: Cannot find file containing module: 'OR2'\n    OR2 DataOut_1_1_ANC4 (.A(DataA_c[4]), .B(CO3), .Y(CO4));\n    ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module Com_2C_Com_2C_1_1(
       DataOut_2,
       DataA_c
    );
output [7:1] DataOut_2;
input  [7:0] DataA_c;

    wire CO1, CO2, CO3, CO4, CO5, GND, VCC, GND_0, VCC_0;
    
    AX1C \DataOut_2[1]  (.A(DataA_c[0]), .B(DataA_c[7]), .C(DataA_c[1])
        , .Y(DataOut_2[1]));
    AX1C \DataOut_2[3]  (.A(CO2), .B(DataA_c[7]), .C(DataA_c[3]), .Y(
        DataOut_2[3]));
    OR2 DataOut_1_1_ANC2 (.A(DataA_c[2]), .B(CO1), .Y(CO2));
    VCC VCC_i_0 (.Y(VCC_0));
    VCC VCC_i (.Y(VCC));
    OR2 DataOut_1_1_ANC5 (.A(DataA_c[5]), .B(CO4), .Y(CO5));
    OR2 DataOut_1_1_ANC4 (.A(DataA_c[4]), .B(CO3), .Y(CO4));
    OR2 DataOut_1_1_ANC3 (.A(DataA_c[3]), .B(CO2), .Y(CO3));
    AX1C \DataOut_2[2]  (.A(CO1), .B(DataA_c[7]), .C(DataA_c[2]), .Y(
        DataOut_2[2]));
    GND GND_i_0 (.Y(GND_0));
    GND GND_i (.Y(GND));
    OA1 \DataOut_2[7]  (.A(CO5), .B(DataA_c[6]), .C(DataA_c[7]), .Y(
        DataOut_2[7]));
    OR2 DataOut_1_1_ANC1 (.A(DataA_c[1]), .B(DataA_c[0]), .Y(CO1));
    AX1C \DataOut_2[6]  (.A(CO5), .B(DataA_c[7]), .C(DataA_c[6]), .Y(
        DataOut_2[6]));
    AX1C \DataOut_2[5]  (.A(CO4), .B(DataA_c[7]), .C(DataA_c[5]), .Y(
        DataOut_2[5]));
    AX1C \DataOut_2[4]  (.A(CO3), .B(DataA_c[7]), .C(DataA_c[4]), .Y(
        DataOut_2[4]));
    
endmodule
module Com_2C_Com_2C_1_1(
       DataOut_2,
       DataA_c
    );

output [7:1] DataOut_2;
input  [7:0] DataA_c;

    wire CO1, CO2, CO3, CO4, CO5, GND, VCC, GND_0, VCC_0;
    
    AX1C \DataOut_2[1]  (.A(DataA_c[0]), .B(DataA_c[7]), .C(DataA_c[1])
        , .Y(DataOut_2[1]));
    AX1C \DataOut_2[3]  (.A(CO2), .B(DataA_c[7]), .C(DataA_c[3]), .Y(
        DataOut_2[3]));
    OR2 DataOut_1_1_ANC2 (.A(DataA_c[2]), .B(CO1), .Y(CO2));
    VCC VCC_i_0 (.Y(VCC_0));
    VCC VCC_i (.Y(VCC));
    OR2 DataOut_1_1_ANC5 (.A(DataA_c[5]), .B(CO4), .Y(CO5));
    OR2 DataOut_1_1_ANC4 (.A(DataA_c[4]), .B(CO3), .Y(CO4));
    OR2 DataOut_1_1_ANC3 (.A(DataA_c[3]), .B(CO2), .Y(CO3));
    AX1C \DataOut_2[2]  (.A(CO1), .B(DataA_c[7]), .C(DataA_c[2]), .Y(
        DataOut_2[2]));
    GND GND_i_0 (.Y(GND_0));
    GND GND_i (.Y(GND));
    OA1 \DataOut_2[7]  (.A(CO5), .B(DataA_c[6]), .C(DataA_c[7]), .Y(
        DataOut_2[7]));
    OR2 DataOut_1_1_ANC1 (.A(DataA_c[1]), .B(DataA_c[0]), .Y(CO1));
    AX1C \DataOut_2[6]  (.A(CO5), .B(DataA_c[7]), .C(DataA_c[6]), .Y(
        DataOut_2[6]));
    AX1C \DataOut_2[5]  (.A(CO4), .B(DataA_c[7]), .C(DataA_c[5]), .Y(
        DataOut_2[5]));
    AX1C \DataOut_2[4]  (.A(CO3), .B(DataA_c[7]), .C(DataA_c[4]), .Y(
        DataOut_2[4]));
    
endmodule