data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules/module_cseladd.v
1: b"%Error: data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules/module_cseladd.v:8: Cannot find file containing module: 'add16'\n    add16 ins1(a[15:0], b[15:0], 0, sum1, cout);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules,data/full_repos/permissive/199632300/add16\n             data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules,data/full_repos/permissive/199632300/add16.v\n             data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules,data/full_repos/permissive/199632300/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules/module_cseladd.v:9: Cannot find file containing module: 'add16'\n    add16 ins2(a[31:16], b[31:16], 0, sum2, cout1);\n    ^~~~~\n%Error: data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules/module_cseladd.v:10: Cannot find file containing module: 'add16'\n    add16 ins3(a[31:16], b[31:16], 1, sum3, cout1);\n    ^~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire [15:0] sum1,sum2,sum3;
    wire cout,cout1;
    add16 ins1(a[15:0], b[15:0], 0, sum1, cout);
    add16 ins2(a[31:16], b[31:16], 0, sum2, cout1);
    add16 ins3(a[31:16], b[31:16], 1, sum3, cout1);
    always @(*) begin
        case (cout)
            1'b0:begin 
                sum[31:0] = {sum2[15:0],sum1[15:0]};
            end
            1'b1:begin
                sum = {sum3,sum1};
            end
        endcase
    end
endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    wire [15:0] sum1,sum2,sum3;
    wire cout,cout1;
    add16 ins1(a[15:0], b[15:0], 0, sum1, cout);
    add16 ins2(a[31:16], b[31:16], 0, sum2, cout1);
    add16 ins3(a[31:16], b[31:16], 1, sum3, cout1);
    always @(*) begin
        case (cout)
            1'b0:begin 
                sum[31:0] = {sum2[15:0],sum1[15:0]};
            end
            1'b1:begin
                sum = {sum3,sum1};
            end
        endcase
    end
endmodule