data/full_repos/permissive/135475029/lab_8/src/top.v
1: b"%Error: data/full_repos/permissive/135475029/lab_8/src/top.v:54: Cannot find file containing module: 'clockdiv'\n  clockdiv ClockDiv (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135475029/lab_8/src,data/full_repos/permissive/135475029/clockdiv\n             data/full_repos/permissive/135475029/lab_8/src,data/full_repos/permissive/135475029/clockdiv.v\n             data/full_repos/permissive/135475029/lab_8/src,data/full_repos/permissive/135475029/clockdiv.sv\n             clockdiv\n             clockdiv.v\n             clockdiv.sv\n             obj_dir/clockdiv\n             obj_dir/clockdiv.v\n             obj_dir/clockdiv.sv\n%Error: data/full_repos/permissive/135475029/lab_8/src/top.v:102: Cannot find file containing module: 'MIPS'\n  MIPS processor (\n  ^~~~\n%Error: Exiting due to 2 error(s)\n"
module top(
  input             FPGACLK,


  input      [1:0]  speed,
  input             RESET,
  output     [6:0]  LED,
  output reg [3:0]  AN
);


  wire CLK;


  wire [31:0] IOWriteData;
  wire  [3:0] IOAddr;
  wire        IOWriteEn;
  wire [31:0] IOReadData;

  reg   [27:0] DispReg;
  reg    [6:0] DispDigit;
  reg   [15:0] DispCount;





  wire  [1:0]  IOin;





  clockdiv ClockDiv (
      .clk(FPGACLK),
      .rst(RESET),
      .clk_en(CLK)
      );


  always @ (posedge CLK, posedge RESET)
    if(RESET)
      DispCount = 0;
	  else
      DispCount = DispCount + 1;




   always @ ( * )
	   begin
		   case (DispCount[15:14])
			  2'b00:   begin AN = 4'b1110; DispDigit = DispReg[6:0];  end
			  2'b01:   begin AN = 4'b1101; DispDigit = DispReg[13:7];  end
			  2'b10:   begin AN = 4'b1011; DispDigit = DispReg[20:14]; end
			  2'b11:   begin AN = 4'b0111; DispDigit = DispReg[27:21];end
			endcase
		end



   assign LED = ~DispDigit;







   assign IOReadData = (IOAddr == 4'b0100) ? { 30'b0, speed } : 32'b0;



  always @ (posedge CLK, posedge RESET)
    if(RESET)
      DispReg = 28'h0;
	 else if(IOWriteEn)
	    DispReg = IOWriteData[27:0];



  MIPS processor (
      .CLK(CLK),
      .RESET(RESET),
      .IOWriteData(IOWriteData),
      .IOAddr(IOAddr),
      .IOWriteEn(IOWriteEn),
      .IOReadData(IOReadData)
      );

endmodule
module top(
  input             FPGACLK,


  input      [1:0]  speed,
  input             RESET,
  output     [6:0]  LED,
  output reg [3:0]  AN
);



  wire CLK;


  wire [31:0] IOWriteData;
  wire  [3:0] IOAddr;
  wire        IOWriteEn;
  wire [31:0] IOReadData;

  reg   [27:0] DispReg;
  reg    [6:0] DispDigit;
  reg   [15:0] DispCount;





  wire  [1:0]  IOin;





  clockdiv ClockDiv (
      .clk(FPGACLK),
      .rst(RESET),
      .clk_en(CLK)
      );


  always @ (posedge CLK, posedge RESET)
    if(RESET)
      DispCount = 0;
	  else
      DispCount = DispCount + 1;




   always @ ( * )
	   begin
		   case (DispCount[15:14])
			  2'b00:   begin AN = 4'b1110; DispDigit = DispReg[6:0];  end
			  2'b01:   begin AN = 4'b1101; DispDigit = DispReg[13:7];  end
			  2'b10:   begin AN = 4'b1011; DispDigit = DispReg[20:14]; end
			  2'b11:   begin AN = 4'b0111; DispDigit = DispReg[27:21];end
			endcase
		end



   assign LED = ~DispDigit;







   assign IOReadData = (IOAddr == 4'b0100) ? { 30'b0, speed } : 32'b0;



  always @ (posedge CLK, posedge RESET)
    if(RESET)
      DispReg = 28'h0;
	 else if(IOWriteEn)
	    DispReg = IOWriteData[27:0];



  MIPS processor (
      .CLK(CLK),
      .RESET(RESET),
      .IOWriteData(IOWriteData),
      .IOAddr(IOAddr),
      .IOWriteEn(IOWriteEn),
      .IOReadData(IOReadData)
      );

endmodule