data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:53: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile(  "hrmcpu_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:54: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, hrmcpu_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #0 i_rst = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_in_data = 8\'h23;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_in_data = 8\'h00;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_in_data = 8\'h15;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #6\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_in_data = 8\'h00;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_in_data = 8\'h11;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #6\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_in_data = 8\'h00;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_in_data = 8\'h22;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_in_data = 8\'h00;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_out_rd = 1\'b 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_out_rd = 1\'b 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_out_rd = 1\'b 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_out_rd = 1\'b 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_out_rd = 1\'b 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_out_rd = 1\'b 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_out_rd = 1\'b 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #2 cpu_out_rd = 1\'b 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/hrmcpu_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #1000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 26 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hrmcpu_tb;


    reg        cpu_debug = 0;
    reg        cpu_nxtInstr = 0;
    reg  [7:0] cpu_in_data = 0;
    reg        cpu_in_wr = 0;
    reg        cpu_out_rd = 0;

    wire       cpu_in_full;
    wire       cpu_out_empty;
    wire [7:0] cpu_out_data;

    reg        clk     = 0;
    reg        i_rst   = 0;


    hrmcpu CPU (

        .cpu_debug(cpu_debug),
        .cpu_nxtInstr(cpu_nxtInstr),
        .cpu_in_data(cpu_in_data),
        .cpu_in_wr(cpu_in_wr),
        .cpu_out_rd(cpu_out_rd),

        .cpu_in_full(cpu_in_full),
        .cpu_out_empty(cpu_out_empty),
        .cpu_out_data(cpu_out_data),

        .clk(clk),
        .i_rst(i_rst)
    );
    defparam CPU.PROGRAM = `PROGRAM;
    defparam CPU.ROMFILE = `ROMFILE;


    always #1 clk = ~clk;


    initial begin

        $dumpfile(  "hrmcpu_tb.vcd");
        $dumpvars(0, hrmcpu_tb);

        #0 i_rst = 1;

        #2 i_rst = 0;


        #2 cpu_in_data = 8'h23;
           cpu_in_wr   = 1'b 1;
        #2 cpu_in_data = 8'h00;
           cpu_in_wr   = 1'b 0;


        #6


        #2 cpu_in_data = 8'h15;
           cpu_in_wr   = 1'b 1;
        #2 cpu_in_data = 8'h00;
           cpu_in_wr   = 1'b 0;


        #6


        #2 cpu_in_data = 8'h11;
           cpu_in_wr   = 1'b 1;
        #2 cpu_in_data = 8'h00;
           cpu_in_wr   = 1'b 0;


        #2 cpu_in_data = 8'h22;
           cpu_in_wr   = 1'b 1;
        #2 cpu_in_data = 8'h00;
           cpu_in_wr   = 1'b 0;


        #100


        #2 cpu_out_rd = 1'b 1;
           $display("%t OUTBOX= %h", $time, cpu_out_data);
        #2 cpu_out_rd = 1'b 0;


        #100
        

        #2 cpu_out_rd = 1'b 1;
           $display("%t OUTBOX= %h", $time, cpu_out_data);
        #2 cpu_out_rd = 1'b 0;


        #2
        

        #2 cpu_out_rd = 1'b 1;
           $display("%t OUTBOX= %h", $time, cpu_out_data);
        #2 cpu_out_rd = 1'b 0;


        #2
        

        #2 cpu_out_rd = 1'b 1;
           $display("%t OUTBOX= %h", $time, cpu_out_data);
        #2 cpu_out_rd = 1'b 0;

        #1000 $finish;
    end

endmodule
module hrmcpu_tb;



    reg        cpu_debug = 0;
    reg        cpu_nxtInstr = 0;
    reg  [7:0] cpu_in_data = 0;
    reg        cpu_in_wr = 0;
    reg        cpu_out_rd = 0;

    wire       cpu_in_full;
    wire       cpu_out_empty;
    wire [7:0] cpu_out_data;

    reg        clk     = 0;
    reg        i_rst   = 0;


    hrmcpu CPU (

        .cpu_debug(cpu_debug),
        .cpu_nxtInstr(cpu_nxtInstr),
        .cpu_in_data(cpu_in_data),
        .cpu_in_wr(cpu_in_wr),
        .cpu_out_rd(cpu_out_rd),

        .cpu_in_full(cpu_in_full),
        .cpu_out_empty(cpu_out_empty),
        .cpu_out_data(cpu_out_data),

        .clk(clk),
        .i_rst(i_rst)
    );
    defparam CPU.PROGRAM = `PROGRAM;
    defparam CPU.ROMFILE = `ROMFILE;


    always #1 clk = ~clk;


    initial begin

        $dumpfile(  "hrmcpu_tb.vcd");
        $dumpvars(0, hrmcpu_tb);

        #0 i_rst = 1;

        #2 i_rst = 0;


        #2 cpu_in_data = 8'h23;
           cpu_in_wr   = 1'b 1;
        #2 cpu_in_data = 8'h00;
           cpu_in_wr   = 1'b 0;


        #6


        #2 cpu_in_data = 8'h15;
           cpu_in_wr   = 1'b 1;
        #2 cpu_in_data = 8'h00;
           cpu_in_wr   = 1'b 0;


        #6


        #2 cpu_in_data = 8'h11;
           cpu_in_wr   = 1'b 1;
        #2 cpu_in_data = 8'h00;
           cpu_in_wr   = 1'b 0;


        #2 cpu_in_data = 8'h22;
           cpu_in_wr   = 1'b 1;
        #2 cpu_in_data = 8'h00;
           cpu_in_wr   = 1'b 0;


        #100


        #2 cpu_out_rd = 1'b 1;
           $display("%t OUTBOX= %h", $time, cpu_out_data);
        #2 cpu_out_rd = 1'b 0;


        #100
        

        #2 cpu_out_rd = 1'b 1;
           $display("%t OUTBOX= %h", $time, cpu_out_data);
        #2 cpu_out_rd = 1'b 0;


        #2
        

        #2 cpu_out_rd = 1'b 1;
           $display("%t OUTBOX= %h", $time, cpu_out_data);
        #2 cpu_out_rd = 1'b 0;


        #2
        

        #2 cpu_out_rd = 1'b 1;
           $display("%t OUTBOX= %h", $time, cpu_out_data);
        #2 cpu_out_rd = 1'b 0;

        #1000 $finish;
    end

endmodule