data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:28: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=0;y=0;z=1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:29: Unsupported: Ignoring delay on this delayed statement.\n            #50 enable=1;x=0;y=1;z=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:30: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=0;y=1;z=1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:31: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=1;y=0;z=0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:32: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=1;y=0;z=1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:33: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=1;y=1;z=0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:34: Unsupported: Ignoring delay on this delayed statement.\n     #50 enable=1;x=1;y=1;z=1;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:5: Little bit endian vector: MSB < LSB of bit range: 0:7\n    output [0:7] D;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/3_to_8_decoder/3_to_8_decoder.v:22: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0:7] D;\n         ^\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decoder_3_to_8(D,x,y,z,enable);
    output [0:7] D;
    input x,y,z,enable;
    wire not_x,not_y,not_z;
    not G1(not_x,x);
    not G2(not_y,y);
    not G3(not_z,z);
    and G4(D[0],not_x,not_y,not_z,enable);
    and G5(D[1],not_x,not_y,z,enable);
    and	G6(D[2],not_x,y,not_z,enable);
    and	G7(D[3],not_x,y,z,enable);
    and	G8(D[4],x,not_y,not_z,enable);
    and	G9(D[5],x,not_y,z,enable);
    and	G10(D[6],x,y,not_z,enable);
    and	G11(D[7],x,y,z,enable);
endmodule
module decoder_3_to_8(D,x,y,z,enable);

    output [0:7] D;
    input x,y,z,enable;
    wire not_x,not_y,not_z;
    not G1(not_x,x);
    not G2(not_y,y);
    not G3(not_z,z);
    and G4(D[0],not_x,not_y,not_z,enable);
    and G5(D[1],not_x,not_y,z,enable);
    and	G6(D[2],not_x,y,not_z,enable);
    and	G7(D[3],not_x,y,z,enable);
    and	G8(D[4],x,not_y,not_z,enable);
    and	G9(D[5],x,not_y,z,enable);
    and	G10(D[6],x,y,not_z,enable);
    and	G11(D[7],x,y,z,enable);
endmodule