data/full_repos/permissive/157135695/lab4iramHRM.v
data/verilator_xmls/82ad65cd-27c1-41e8-9693-917a3d3f2f09.xml
module lab4iramHRM(CLK, RESET, ADDR, Q);
  input         CLK;
  input         RESET;
  input  [7:0]  ADDR;
  output [15:0] Q;

  reg    [15:0] mem[0:127];

  wire   [6:0]  saddr;
  integer       i;

  assign saddr = ADDR[7:1];
  assign Q = mem[saddr];

  always @(posedge CLK) begin
    if(RESET) begin
      mem[0]  <= 16'b1111000000000001;
      mem[1]  <= 16'b1111010010010001;
      mem[2]  <= 16'b1111111111111001;
      mem[3]  <= 16'b1111110110110001;
      mem[4]  <= 16'b0101000101111111;
      mem[5]  <= 16'b1111101000101011;
      mem[6]  <= 16'b0010000011111011;
      mem[7]  <= 16'b0110011011000001;
      mem[8]  <= 16'b0010000100111011;
      mem[9]  <= 16'b0110100100000001;
      mem[10]  <= 16'b1111100011011000;
      mem[11]  <= 16'b0110011011000001;
      mem[12]  <= 16'b1111011100011101;
      mem[13]  <= 16'b1111010011010000;
      mem[14]  <= 16'b1111100000011000;
      mem[15]  <= 16'b0101111111111111;
      mem[16]  <= 16'b1001000111111000;
      mem[17]  <= 16'b0101110110111111;
      mem[18]  <= 16'b1001000110110110;
      mem[19]  <= 16'b0101101101111111;
      mem[20]  <= 16'b1001000101110011;
      mem[21]  <= 16'b0101010100100010;
      mem[22]  <= 16'b1011100000000001;
      mem[23]  <= 16'b0101000010011101;
      mem[24]  <= 16'b1111010000010100;
      mem[25]  <= 16'b0010010011000000;
      mem[26]  <= 16'b0100000011111110;
      mem[27]  <= 16'b0010010011000001;
      mem[28]  <= 16'b0100000011111111;

    
      for(i = 29; i < 128; i = i + 1) begin
        mem[i] <= 16'b0000000000000000;
      end
    end
  end

endmodule
module lab4iramHRM(CLK, RESET, ADDR, Q);

  input         CLK;
  input         RESET;
  input  [7:0]  ADDR;
  output [15:0] Q;

  reg    [15:0] mem[0:127];

  wire   [6:0]  saddr;
  integer       i;

  assign saddr = ADDR[7:1];
  assign Q = mem[saddr];

  always @(posedge CLK) begin
    if(RESET) begin
      mem[0]  <= 16'b1111000000000001;
      mem[1]  <= 16'b1111010010010001;
      mem[2]  <= 16'b1111111111111001;
      mem[3]  <= 16'b1111110110110001;
      mem[4]  <= 16'b0101000101111111;
      mem[5]  <= 16'b1111101000101011;
      mem[6]  <= 16'b0010000011111011;
      mem[7]  <= 16'b0110011011000001;
      mem[8]  <= 16'b0010000100111011;
      mem[9]  <= 16'b0110100100000001;
      mem[10]  <= 16'b1111100011011000;
      mem[11]  <= 16'b0110011011000001;
      mem[12]  <= 16'b1111011100011101;
      mem[13]  <= 16'b1111010011010000;
      mem[14]  <= 16'b1111100000011000;
      mem[15]  <= 16'b0101111111111111;
      mem[16]  <= 16'b1001000111111000;
      mem[17]  <= 16'b0101110110111111;
      mem[18]  <= 16'b1001000110110110;
      mem[19]  <= 16'b0101101101111111;
      mem[20]  <= 16'b1001000101110011;
      mem[21]  <= 16'b0101010100100010;
      mem[22]  <= 16'b1011100000000001;
      mem[23]  <= 16'b0101000010011101;
      mem[24]  <= 16'b1111010000010100;
      mem[25]  <= 16'b0010010011000000;
      mem[26]  <= 16'b0100000011111110;
      mem[27]  <= 16'b0010010011000001;
      mem[28]  <= 16'b0100000011111111;

    
      for(i = 29; i < 128; i = i + 1) begin
        mem[i] <= 16'b0000000000000000;
      end
    end
  end

endmodule