data/full_repos/permissive/191241380/zxdos/relojes.v
 line:66 column:2: Illegal character '`'
1: b"%Error: data/full_repos/permissive/191241380/zxdos/relojes.v:13: Cannot find file containing module: 'IBUFG'\n  IBUFG clkin1_buf\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/191241380/zxdos,data/full_repos/permissive/191241380/IBUFG\n             data/full_repos/permissive/191241380/zxdos,data/full_repos/permissive/191241380/IBUFG.v\n             data/full_repos/permissive/191241380/zxdos,data/full_repos/permissive/191241380/IBUFG.sv\n             IBUFG\n             IBUFG.v\n             IBUFG.sv\n             obj_dir/IBUFG\n             obj_dir/IBUFG.v\n             obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/191241380/zxdos/relojes.v:26: Cannot find file containing module: 'PLL_BASE'\n  PLL_BASE\n  ^~~~~~~~\n%Error: data/full_repos/permissive/191241380/zxdos/relojes.v:56: Cannot find file containing module: 'BUFG'\n  BUFG clkf_buf\n  ^~~~\n%Error: data/full_repos/permissive/191241380/zxdos/relojes.v:60: Cannot find file containing module: 'BUFG'\n  BUFG clkout1_buf\n  ^~~~\n%Error: Exiting due to 4 error(s)\n"
module genreloj
 (
  input wire        CLK_IN1,

  output wire       CLK_OUT1
 );



  IBUFG clkin1_buf
   (.O (clkin1),
    .I (CLK_IN1));






  wire        clkfbout;
  wire        clkfbout_buf;
  wire        clkout0;

  PLL_BASE
  #(.BANDWIDTH              ("OPTIMIZED"),
    .CLK_FEEDBACK           ("CLKFBOUT"),
    .COMPENSATION           ("SYSTEM_SYNCHRONOUS"),
    .DIVCLK_DIVIDE          (1),
    .CLKFBOUT_MULT          (8),
    .CLKFBOUT_PHASE         (0.000),
    .CLKOUT0_DIVIDE         (16),
    .CLKOUT0_PHASE          (0.000),
    .CLKOUT0_DUTY_CYCLE     (0.500),
    .CLKIN_PERIOD           (20.000),
    .REF_JITTER             (0.010))
  pll_base_inst

   (.CLKFBOUT              (clkfbout),
    .CLKOUT0               (clkout0),
    .CLKOUT1               (),
    .CLKOUT2               (),
    .CLKOUT3               (),
    .CLKOUT4               (),
    .CLKOUT5               (),
    .LOCKED                (),
    .RST                   (1'b0),

    .CLKFBIN               (clkfbout_buf),
    .CLKIN                 (clkin1));




  BUFG clkf_buf
   (.O (clkfbout_buf),
    .I (clkfbout));

  BUFG clkout1_buf
   (.O   (CLK_OUT1),
    .I   (clkout0));

endmodule
module genreloj
 (
  input wire        CLK_IN1,

  output wire       CLK_OUT1
 );




  IBUFG clkin1_buf
   (.O (clkin1),
    .I (CLK_IN1));






  wire        clkfbout;
  wire        clkfbout_buf;
  wire        clkout0;

  PLL_BASE
  #(.BANDWIDTH              ("OPTIMIZED"),
    .CLK_FEEDBACK           ("CLKFBOUT"),
    .COMPENSATION           ("SYSTEM_SYNCHRONOUS"),
    .DIVCLK_DIVIDE          (1),
    .CLKFBOUT_MULT          (8),
    .CLKFBOUT_PHASE         (0.000),
    .CLKOUT0_DIVIDE         (16),
    .CLKOUT0_PHASE          (0.000),
    .CLKOUT0_DUTY_CYCLE     (0.500),
    .CLKIN_PERIOD           (20.000),
    .REF_JITTER             (0.010))
  pll_base_inst

   (.CLKFBOUT              (clkfbout),
    .CLKOUT0               (clkout0),
    .CLKOUT1               (),
    .CLKOUT2               (),
    .CLKOUT3               (),
    .CLKOUT4               (),
    .CLKOUT5               (),
    .LOCKED                (),
    .RST                   (1'b0),

    .CLKFBIN               (clkfbout_buf),
    .CLKIN                 (clkin1));




  BUFG clkf_buf
   (.O (clkfbout_buf),
    .I (clkfbout));

  BUFG clkout1_buf
   (.O   (CLK_OUT1),
    .I   (clkout0));

endmodule