data/full_repos/permissive/136371172/conv.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:60: Operator ADD expects 32 or 12 bits on the LHS, but LHS\'s VARREF \'r_00\' generates 8 bits.\n                                                              : ... In instance conv\n assign ver = ((r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ) > 0)? (r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22) : -(r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ); \n                                                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:60: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_02\' generates 8 bits.\n                                                              : ... In instance conv\n assign ver = ((r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ) > 0)? (r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22) : -(r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ); \n                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:60: Operator SUB expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_20\' generates 8 bits.\n                                                              : ... In instance conv\n assign ver = ((r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ) > 0)? (r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22) : -(r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:60: Operator SUB expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_22\' generates 8 bits.\n                                                              : ... In instance conv\n assign ver = ((r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ) > 0)? (r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22) : -(r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ); \n                                                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:60: Operator ADD expects 32 or 12 bits on the LHS, but LHS\'s VARREF \'r_00\' generates 8 bits.\n                                                              : ... In instance conv\n assign ver = ((r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ) > 0)? (r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22) : -(r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ); \n                                                                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:60: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_02\' generates 8 bits.\n                                                              : ... In instance conv\n assign ver = ((r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ) > 0)? (r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22) : -(r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ); \n                                                                                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:60: Operator SUB expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_20\' generates 8 bits.\n                                                              : ... In instance conv\n assign ver = ((r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ) > 0)? (r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22) : -(r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ); \n                                                                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:60: Operator SUB expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_22\' generates 8 bits.\n                                                              : ... In instance conv\n assign ver = ((r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ) > 0)? (r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22) : -(r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ); \n                                                                                                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:61: Operator SUB expects 32 or 12 bits on the LHS, but LHS\'s VARREF \'r_00\' generates 8 bits.\n                                                              : ... In instance conv\n assign hor = ((r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 ) > 0)? (r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22) : -(r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 );\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:61: Operator SUB expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_02\' generates 8 bits.\n                                                              : ... In instance conv\n assign hor = ((r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 ) > 0)? (r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22) : -(r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 );\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:61: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_20\' generates 8 bits.\n                                                              : ... In instance conv\n assign hor = ((r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 ) > 0)? (r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22) : -(r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 );\n                                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:61: Operator SUB expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_22\' generates 8 bits.\n                                                              : ... In instance conv\n assign hor = ((r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 ) > 0)? (r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22) : -(r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 );\n                                                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:61: Operator SUB expects 32 or 12 bits on the LHS, but LHS\'s VARREF \'r_00\' generates 8 bits.\n                                                              : ... In instance conv\n assign hor = ((r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 ) > 0)? (r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22) : -(r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 );\n                                                                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:61: Operator SUB expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_02\' generates 8 bits.\n                                                              : ... In instance conv\n assign hor = ((r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 ) > 0)? (r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22) : -(r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 );\n                                                                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:61: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_20\' generates 8 bits.\n                                                              : ... In instance conv\n assign hor = ((r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 ) > 0)? (r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22) : -(r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 );\n                                                                                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:61: Operator SUB expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'r_22\' generates 8 bits.\n                                                              : ... In instance conv\n assign hor = ((r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 ) > 0)? (r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22) : -(r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 );\n                                                                                                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:62: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s CONST \'8\'hff\' generates 8 bits.\n                                                              : ... In instance conv\n assign tresh=(ver+hor < 70)?8\'b11111111:0;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:63: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                              : ... In instance conv\n assign filter1 = ((r_00 * kernel_00) + (r_01 * kernel_01) + (r_02 * kernel_02) + \n                ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:69: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                              : ... In instance conv\n assign filter2 = ((r_00 * kernel2_00) + (r_01 * kernel2_01) + (r_02 * kernel2_02) + \n                ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:73: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                              : ... In instance conv\n assign filter3 = ((r_00 * kernel3_00) + (r_01 * kernel3_01) + (r_02 * kernel3_02) +\n                ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:80: Operator COND expects 12 bits on the Conditional True, but Conditional True\'s VARREF \'filter1\' generates 8 bits.\n                                                              : ... In instance conv\n assign pixel_out = (select[0])?filter1:(select[1])?tresh:(select[2])?filter3:r_11;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:80: Operator COND expects 12 bits on the Conditional True, but Conditional True\'s VARREF \'filter3\' generates 8 bits.\n                                                              : ... In instance conv\n assign pixel_out = (select[0])?filter1:(select[1])?tresh:(select[2])?filter3:r_11;\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:80: Operator COND expects 12 bits on the Conditional False, but Conditional False\'s VARREF \'r_11\' generates 8 bits.\n                                                              : ... In instance conv\n assign pixel_out = (select[0])?filter1:(select[1])?tresh:(select[2])?filter3:r_11;\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/136371172/conv.v:80: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 12 bits.\n                                                              : ... In instance conv\n assign pixel_out = (select[0])?filter1:(select[1])?tresh:(select[2])?filter3:r_11;\n                  ^\n%Error: Exiting due to 24 warning(s)\n'
module conv(
	input [2:0]select,
	input [7:0] pixel_in,
	input clk,
	input LOCKED,
	output [7:0] pixel_out,
	output valid
    );
	 
	 
	


	reg signed [7:0] r_00 = 0;reg signed [7:0] r_01 = 0;reg signed [7:0] r_02 = 0;
	reg signed [7:0] r_10 = 0;reg signed [7:0] r_11 = 0;reg signed [7:0] r_12 = 0;
	reg signed [7:0] r_20 = 0;reg signed [7:0] r_21 = 0;reg signed [7:0] r_22 = 0;
	
	
	integer kernel_00 = 0; integer kernel_01 = -1; integer kernel_02 = 0;
	integer kernel_10 = -1; integer kernel_11 = 5; integer kernel_12 = -1;
	integer kernel_20 = 0; integer kernel_21 = -1; integer kernel_22 = 0;
	
	integer kernel2_00 = 1; integer kernel2_01 = 0; integer kernel2_02 = -1;
	integer kernel2_10 = 2; integer kernel2_11 = 0; integer kernel2_12 = -2;
	integer kernel2_20 = 1; integer kernel2_21 = 0; integer kernel2_22 = -1;

	integer kernel3_00 = 1; integer kernel3_01 = 2; integer kernel3_02 = 1;
	integer kernel3_10 = 2; integer kernel3_11 = 4; integer kernel3_12 = 2;
	integer kernel3_20 = 1; integer kernel3_21 = 2; integer kernel3_22 = 1;
	
	

	wire [11:0] ver,hor;
	wire [11:0] tresh;
	reg [1:0] n = 0;
	wire [7:0] filter1, filter2, filter3;



	assign ver = ((r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ) > 0)? (r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22) : -(r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ); 
	assign hor = ((r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 ) > 0)? (r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22) : -(r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 );
	assign tresh=(ver+hor < 70)?8'b11111111:0;
	assign filter1 = ((r_00 * kernel_00) + (r_01 * kernel_01) + (r_02 * kernel_02) + 
							(r_10 * kernel_10) + (r_11 * kernel_11) + (r_12 * kernel_12) + 
							(r_20 * kernel_20) + (r_21 * kernel_21) + (r_22 * kernel_22));

							
							
	assign filter2 = ((r_00 * kernel2_00) + (r_01 * kernel2_01) + (r_02 * kernel2_02) + 
							(r_10 * kernel2_10) + (r_11 * kernel2_11) + (r_12 * kernel2_12) + 
							(r_20 * kernel2_20) + (r_21 * kernel2_21) + (r_22 * kernel2_22));
							
	assign filter3 = ((r_00 * kernel3_00) + (r_01 * kernel3_01) + (r_02 * kernel3_02) +
							(r_10 * kernel3_10) + (r_11 * kernel3_11) + (r_12 * kernel3_12) + 
							(r_20 * kernel3_20) + (r_21 * kernel3_21) + (r_22 * kernel3_22));
							



	assign pixel_out = (select[0])?filter1:(select[1])?tresh:(select[2])?filter3:r_11;






	always @(posedge clk)
	begin
	if(LOCKED)
	begin
		if(n == 0)
			r_02 <= pixel_in;
		else if(n == 1)
			r_12 <= pixel_in;
		else if(n == 2)
		begin
			r_22 <= pixel_in;
			r_00 <= r_01;
			r_10 <= r_11;
			r_20 <= r_21;
			r_01 <= r_02;
			r_11 <= r_12;
			r_21 <= r_22;
		end
		n <= n + 1;	
				
		if(n >= 2)
			n <= 0;  
	end
	end	

			
			
			
	assign valid  = (n==2)?1:0;




		


endmodule
module conv(
	input [2:0]select,
	input [7:0] pixel_in,
	input clk,
	input LOCKED,
	output [7:0] pixel_out,
	output valid
    );

	 
	 
	


	reg signed [7:0] r_00 = 0;reg signed [7:0] r_01 = 0;reg signed [7:0] r_02 = 0;
	reg signed [7:0] r_10 = 0;reg signed [7:0] r_11 = 0;reg signed [7:0] r_12 = 0;
	reg signed [7:0] r_20 = 0;reg signed [7:0] r_21 = 0;reg signed [7:0] r_22 = 0;
	
	
	integer kernel_00 = 0; integer kernel_01 = -1; integer kernel_02 = 0;
	integer kernel_10 = -1; integer kernel_11 = 5; integer kernel_12 = -1;
	integer kernel_20 = 0; integer kernel_21 = -1; integer kernel_22 = 0;
	
	integer kernel2_00 = 1; integer kernel2_01 = 0; integer kernel2_02 = -1;
	integer kernel2_10 = 2; integer kernel2_11 = 0; integer kernel2_12 = -2;
	integer kernel2_20 = 1; integer kernel2_21 = 0; integer kernel2_22 = -1;

	integer kernel3_00 = 1; integer kernel3_01 = 2; integer kernel3_02 = 1;
	integer kernel3_10 = 2; integer kernel3_11 = 4; integer kernel3_12 = 2;
	integer kernel3_20 = 1; integer kernel3_21 = 2; integer kernel3_22 = 1;
	
	

	wire [11:0] ver,hor;
	wire [11:0] tresh;
	reg [1:0] n = 0;
	wire [7:0] filter1, filter2, filter3;



	assign ver = ((r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ) > 0)? (r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22) : -(r_00 + r_01 * 2 + r_02 - r_20 - r_21 * 2 - r_22 ); 
	assign hor = ((r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 ) > 0)? (r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22) : -(r_00 - r_02 + r_10 * 2 - r_12 * 2 + r_20 - r_22 );
	assign tresh=(ver+hor < 70)?8'b11111111:0;
	assign filter1 = ((r_00 * kernel_00) + (r_01 * kernel_01) + (r_02 * kernel_02) + 
							(r_10 * kernel_10) + (r_11 * kernel_11) + (r_12 * kernel_12) + 
							(r_20 * kernel_20) + (r_21 * kernel_21) + (r_22 * kernel_22));

							
							
	assign filter2 = ((r_00 * kernel2_00) + (r_01 * kernel2_01) + (r_02 * kernel2_02) + 
							(r_10 * kernel2_10) + (r_11 * kernel2_11) + (r_12 * kernel2_12) + 
							(r_20 * kernel2_20) + (r_21 * kernel2_21) + (r_22 * kernel2_22));
							
	assign filter3 = ((r_00 * kernel3_00) + (r_01 * kernel3_01) + (r_02 * kernel3_02) +
							(r_10 * kernel3_10) + (r_11 * kernel3_11) + (r_12 * kernel3_12) + 
							(r_20 * kernel3_20) + (r_21 * kernel3_21) + (r_22 * kernel3_22));
							



	assign pixel_out = (select[0])?filter1:(select[1])?tresh:(select[2])?filter3:r_11;






	always @(posedge clk)
	begin
	if(LOCKED)
	begin
		if(n == 0)
			r_02 <= pixel_in;
		else if(n == 1)
			r_12 <= pixel_in;
		else if(n == 2)
		begin
			r_22 <= pixel_in;
			r_00 <= r_01;
			r_10 <= r_11;
			r_20 <= r_21;
			r_01 <= r_02;
			r_11 <= r_12;
			r_21 <= r_22;
		end
		n <= n + 1;	
				
		if(n >= 2)
			n <= 0;  
	end
	end	

			
			
			
	assign valid  = (n==2)?1:0;




		


endmodule