data/full_repos/permissive/134757352/mojo-io-shield/src/hex/ring_counter.v
data/verilator_xmls/2d4bf666-d875-432f-a2b1-a20aecb7cdb8.xml
module ring_counter #(
    parameter LEN = 4,
    parameter DIV = 16
  )(
    input clk,
    input rst,
    output [LEN-1:0] out
  );

  reg [LEN-1:0] ring_d, ring_q;
  reg [DIV-1:0] count_d, count_q;
  wire shift = &count_q;
  assign out = ring_q;

  initial begin
    ring_q = {1'b1, {LEN-1{1'b0}}};
    count_q = {DIV{1'b0}};
  end


  always @(*) begin
    count_d = count_q + 1'b1;
    ring_d = {ring_q[0], ring_q[LEN-1:1]};
  end


  always @(posedge clk) begin
    if (rst) begin
      count_q <= {DIV{1'b0}};
    end else begin
      count_q <= count_d;
    end
  end


  always @(posedge clk) begin
    if (rst) begin
      ring_q <= {1'b1, {LEN-1{1'b0}}};
    end else if (shift) begin
      ring_q <= ring_d;
    end
  end

endmodule
module ring_counter #(
    parameter LEN = 4,
    parameter DIV = 16
  )(
    input clk,
    input rst,
    output [LEN-1:0] out
  );


  reg [LEN-1:0] ring_d, ring_q;
  reg [DIV-1:0] count_d, count_q;
  wire shift = &count_q;
  assign out = ring_q;

  initial begin
    ring_q = {1'b1, {LEN-1{1'b0}}};
    count_q = {DIV{1'b0}};
  end


  always @(*) begin
    count_d = count_q + 1'b1;
    ring_d = {ring_q[0], ring_q[LEN-1:1]};
  end


  always @(posedge clk) begin
    if (rst) begin
      count_q <= {DIV{1'b0}};
    end else begin
      count_q <= count_d;
    end
  end


  always @(posedge clk) begin
    if (rst) begin
      ring_q <= {1'b1, {LEN-1{1'b0}}};
    end else if (shift) begin
      ring_q <= ring_d;
    end
  end

endmodule