data/full_repos/permissive/154350027/rtl/tcpip/ip_pack.v
1: b'%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/ip_pack.v:123: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'ip_head_cnt\' generates 5 bits.\n                                                                            : ... In instance ip_pack\n      ip_wram_addr <= ip_head_cnt + 10\'d22;\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/ip_pack.v:125: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'ip_chksum_cnt\' generates 1 bits.\n                                                                            : ... In instance ip_pack\n      ip_wram_addr <= ip_chksum_cnt + 10\'d32;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/ip_pack.v:201: Operator ADD expects 32 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                            : ... In instance ip_pack\n sum_ext <= checksum + {ip_wram_dat_dly,ip_wram_dat};\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/ip_pack.v:206: Operator ADD expects 32 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                            : ... In instance ip_pack\n  assign checksum = sum_ext[31:16] + sum_ext[15:0];\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/ip_pack.v:206: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                            : ... In instance ip_pack\n  assign checksum = sum_ext[31:16] + sum_ext[15:0];\n                                   ^\n%Error: Exiting due to 5 warning(s)\n'
module ip_pack
  (

   input wire 	     clk,
   input wire 	     rst_n,


   input wire [7:0]  prot_type,
   input wire [31:0] src_ip_addr,
   input wire [31:0] des_ip_addr,


   input wire 	     mac_head_end,
   output reg 	     ip_head_end,


   output reg 	     ip_wram_clk_en,
   output reg [9:0]  ip_wram_addr,
   output reg [7:0]  ip_wram_dat
   
   );

  parameter IDLE   = 3'd0;
  parameter HEAD   = 3'd1;
  parameter WAIT   = 3'd2;
  parameter CHKSUM = 3'd3;
  parameter DONE   = 3'd4;

  reg [2:0] 	     ip_cs;
  reg [2:0] 	     ip_ns;

  reg [4:0] 	     ip_head_cnt;
  reg [15:0] 	     id_cnt;

  reg 		     ip_chksum_cnt;
  wire [31:0] 	     checksum;
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_cs <= IDLE;
    else
      ip_cs <= ip_ns;

  always@(*)
    case(ip_cs)
      IDLE:
	if(mac_head_end)ip_ns = HEAD;
	else ip_ns = IDLE;
      HEAD:
	if(ip_head_cnt == 5'd19)ip_ns = WAIT;
	else ip_ns = HEAD;
      WAIT:
	ip_ns = CHKSUM;
      CHKSUM:
	if(ip_chksum_cnt == 1'b1)ip_ns = DONE;
	else ip_ns = CHKSUM;
      DONE:
	ip_ns = IDLE;
      default:
	ip_ns = IDLE;
    endcase
     

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_head_cnt <= 5'd0;
    else if(ip_cs == HEAD)
      ip_head_cnt <= ip_head_cnt + 1'b1;
    else
      ip_head_cnt <= 5'd0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_chksum_cnt <= 1'b0;
    else if(ip_cs == CHKSUM)
      ip_chksum_cnt <= ip_chksum_cnt + 1'b1;
    else
      ip_chksum_cnt <= 1'b0;
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_wram_clk_en <= 1'b0;
    else if(ip_cs == HEAD || ip_cs == CHKSUM)
      ip_wram_clk_en <= 1'b1;
    else
      ip_wram_clk_en <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_wram_addr <= 10'd0;
    else if(ip_cs == HEAD)
      ip_wram_addr <= ip_head_cnt + 10'd22;
    else if(ip_cs == CHKSUM)
      ip_wram_addr <= ip_chksum_cnt + 10'd32;
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_wram_dat <= 8'h00;
    else if(ip_cs == HEAD)
      begin
	case(ip_head_cnt)
	  5'd0: ip_wram_dat <= 8'h45;
	  5'd1: ip_wram_dat <= 8'h00;
	  5'd2: ip_wram_dat <= 8'h03;
	  5'd3: ip_wram_dat <= 8'hdd;
	  5'd4: ip_wram_dat <= id_cnt[15:8];
	  5'd5: ip_wram_dat <= id_cnt[7:0];
	  5'd6: ip_wram_dat <= 8'h00;
	  5'd7: ip_wram_dat <= 8'h00;
	  5'd8: ip_wram_dat <= 8'h40;
	  5'd9: ip_wram_dat <= prot_type;
	  5'd10: ip_wram_dat <= 8'h00;
	  5'd11: ip_wram_dat <= 8'h00;
	  5'd12: ip_wram_dat <= src_ip_addr[31:24];
	  5'd13: ip_wram_dat <= src_ip_addr[23:16];
	  5'd14: ip_wram_dat <= src_ip_addr[15:8];
	  5'd15: ip_wram_dat <= src_ip_addr[7:0];
	  5'd16: ip_wram_dat <= des_ip_addr[31:24];
	  5'd17: ip_wram_dat <= des_ip_addr[23:16];
	  5'd18: ip_wram_dat <= des_ip_addr[15:8];
	  5'd19: ip_wram_dat <= des_ip_addr[7:0];
	endcase
      end
    else if(ip_cs == CHKSUM)
      begin
	if(ip_chksum_cnt == 1'b0)ip_wram_dat <= ~checksum[15:8];
	else ip_wram_dat <= ~checksum[7:0];
      end


  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_head_end <= 1'b0;
    else if(ip_cs == CHKSUM && ip_chksum_cnt == 1'b1)
      ip_head_end <= 1'b1;
    else
      ip_head_end <= 1'b0;


  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      id_cnt <= 16'd0;
    else if(ip_cs == DONE)
      id_cnt <= id_cnt + 1'b1;


  reg [7:0]ip_wram_dat_dly;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_wram_dat_dly <= 8'h00;
    else
      ip_wram_dat_dly <= ip_wram_dat;

  reg 	   st_head_dly;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      st_head_dly <= 1'b0;
    else if(ip_cs == HEAD)
      st_head_dly <= 1'b1;
    else
      st_head_dly <= 1'b0;
  
  reg [31:0] sum_ext;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      sum_ext <= 32'b0;
    else if(st_head_dly && 
	    !ip_head_cnt[0] && ip_head_cnt != 5'd0)
      begin
	sum_ext <= checksum + {ip_wram_dat_dly,ip_wram_dat};
      end
    else if(ip_cs == DONE)
      sum_ext <= 32'b0;
  
  assign checksum = sum_ext[31:16] + sum_ext[15:0];

  
endmodule
module ip_pack
  (

   input wire 	     clk,
   input wire 	     rst_n,


   input wire [7:0]  prot_type,
   input wire [31:0] src_ip_addr,
   input wire [31:0] des_ip_addr,


   input wire 	     mac_head_end,
   output reg 	     ip_head_end,


   output reg 	     ip_wram_clk_en,
   output reg [9:0]  ip_wram_addr,
   output reg [7:0]  ip_wram_dat
   
   );


  parameter IDLE   = 3'd0;
  parameter HEAD   = 3'd1;
  parameter WAIT   = 3'd2;
  parameter CHKSUM = 3'd3;
  parameter DONE   = 3'd4;

  reg [2:0] 	     ip_cs;
  reg [2:0] 	     ip_ns;

  reg [4:0] 	     ip_head_cnt;
  reg [15:0] 	     id_cnt;

  reg 		     ip_chksum_cnt;
  wire [31:0] 	     checksum;
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_cs <= IDLE;
    else
      ip_cs <= ip_ns;

  always@(*)
    case(ip_cs)
      IDLE:
	if(mac_head_end)ip_ns = HEAD;
	else ip_ns = IDLE;
      HEAD:
	if(ip_head_cnt == 5'd19)ip_ns = WAIT;
	else ip_ns = HEAD;
      WAIT:
	ip_ns = CHKSUM;
      CHKSUM:
	if(ip_chksum_cnt == 1'b1)ip_ns = DONE;
	else ip_ns = CHKSUM;
      DONE:
	ip_ns = IDLE;
      default:
	ip_ns = IDLE;
    endcase
     

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_head_cnt <= 5'd0;
    else if(ip_cs == HEAD)
      ip_head_cnt <= ip_head_cnt + 1'b1;
    else
      ip_head_cnt <= 5'd0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_chksum_cnt <= 1'b0;
    else if(ip_cs == CHKSUM)
      ip_chksum_cnt <= ip_chksum_cnt + 1'b1;
    else
      ip_chksum_cnt <= 1'b0;
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_wram_clk_en <= 1'b0;
    else if(ip_cs == HEAD || ip_cs == CHKSUM)
      ip_wram_clk_en <= 1'b1;
    else
      ip_wram_clk_en <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_wram_addr <= 10'd0;
    else if(ip_cs == HEAD)
      ip_wram_addr <= ip_head_cnt + 10'd22;
    else if(ip_cs == CHKSUM)
      ip_wram_addr <= ip_chksum_cnt + 10'd32;
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_wram_dat <= 8'h00;
    else if(ip_cs == HEAD)
      begin
	case(ip_head_cnt)
	  5'd0: ip_wram_dat <= 8'h45;
	  5'd1: ip_wram_dat <= 8'h00;
	  5'd2: ip_wram_dat <= 8'h03;
	  5'd3: ip_wram_dat <= 8'hdd;
	  5'd4: ip_wram_dat <= id_cnt[15:8];
	  5'd5: ip_wram_dat <= id_cnt[7:0];
	  5'd6: ip_wram_dat <= 8'h00;
	  5'd7: ip_wram_dat <= 8'h00;
	  5'd8: ip_wram_dat <= 8'h40;
	  5'd9: ip_wram_dat <= prot_type;
	  5'd10: ip_wram_dat <= 8'h00;
	  5'd11: ip_wram_dat <= 8'h00;
	  5'd12: ip_wram_dat <= src_ip_addr[31:24];
	  5'd13: ip_wram_dat <= src_ip_addr[23:16];
	  5'd14: ip_wram_dat <= src_ip_addr[15:8];
	  5'd15: ip_wram_dat <= src_ip_addr[7:0];
	  5'd16: ip_wram_dat <= des_ip_addr[31:24];
	  5'd17: ip_wram_dat <= des_ip_addr[23:16];
	  5'd18: ip_wram_dat <= des_ip_addr[15:8];
	  5'd19: ip_wram_dat <= des_ip_addr[7:0];
	endcase
      end
    else if(ip_cs == CHKSUM)
      begin
	if(ip_chksum_cnt == 1'b0)ip_wram_dat <= ~checksum[15:8];
	else ip_wram_dat <= ~checksum[7:0];
      end


  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_head_end <= 1'b0;
    else if(ip_cs == CHKSUM && ip_chksum_cnt == 1'b1)
      ip_head_end <= 1'b1;
    else
      ip_head_end <= 1'b0;


  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      id_cnt <= 16'd0;
    else if(ip_cs == DONE)
      id_cnt <= id_cnt + 1'b1;


  reg [7:0]ip_wram_dat_dly;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      ip_wram_dat_dly <= 8'h00;
    else
      ip_wram_dat_dly <= ip_wram_dat;

  reg 	   st_head_dly;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      st_head_dly <= 1'b0;
    else if(ip_cs == HEAD)
      st_head_dly <= 1'b1;
    else
      st_head_dly <= 1'b0;
  
  reg [31:0] sum_ext;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      sum_ext <= 32'b0;
    else if(st_head_dly && 
	    !ip_head_cnt[0] && ip_head_cnt != 5'd0)
      begin
	sum_ext <= checksum + {ip_wram_dat_dly,ip_wram_dat};
      end
    else if(ip_cs == DONE)
      sum_ext <= 32'b0;
  
  assign checksum = sum_ext[31:16] + sum_ext[15:0];

  
endmodule