data/full_repos/permissive/19572582/Lab3/lab3_part5.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:118: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output reg [0:6] SSD;\n             ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:67: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:92: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H0 (SW[3:0], HEX0);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:93: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H1 (SW[7:4], HEX1);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:94: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H2 (SW[11:8], HEX2);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:95: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H3 (SW[15:12], HEX3);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:96: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H4 (R[3:0], HEX4);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:97: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H5 (R[7:4], HEX5);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:98: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H6 (R[11:8], HEX6);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:99: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H7 (R[15:12], HEX7);\n               ^\n%Error: Exiting due to 10 warning(s)\n'
module D_ff_with_sync_clr (Clk, D, Q, Clr);
  input Clk, D, Clr;
  output reg Q;
  always @ ( posedge Clk or posedge Clr)
	 if (Clr)
	 begin
		Q <= 1'b0;
	 end else
	 begin
		Q <= D;
	 end
endmodule
module D_ff_with_sync_clr (Clk, D, Q, Clr);

  input Clk, D, Clr;
  output reg Q;
  always @ ( posedge Clk or posedge Clr)
	 if (Clr)
	 begin
		Q <= 1'b0;
	 end else
	 begin
		Q <= D;
	 end
endmodule