data/full_repos/permissive/174783592/WallacePL/Adder/sum16bitTB.sv
 line:42: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Adder/sum16bitTB.sv:42: Unsupported: Ignoring delay on this delayed statement.\n  #15 $finish; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Adder/sum16bitTB.sv:46: Unsupported: Ignoring delay on this delayed statement.\n    always #5 a <= a+1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Adder/sum16bitTB.sv:47: Unsupported: Ignoring delay on this delayed statement.\n    always #5 b<= b+1;\n           ^\n%Error: data/full_repos/permissive/174783592/WallacePL/Adder/sum16bitTB.sv:49: Unsupported or unknown PLI call: $monitor\n  $monitor ($time,"clk = %b, a=%b   b=%b \\nsum=%b \\n",clk,a,b,sum); \n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Adder/sum16bitTB.sv:52: Unsupported: Ignoring delay on this delayed statement.\n #20 $display ("kpgIn[%d]=%b",i,s1.wl4[i]);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sum16bitTB();
	reg [15:0] a;
	reg    [15:0] b;
	reg [1:0] kIn;

       	integer i;
	wire [16:0] sum ;

	
	sum16bit s1(a,b,kIn,  sum);
	initial
	begin
		a <= {4{4'b1001}};
		b <= {4{4'b1111}};
		kIn <= 2'b00;

		#15 $finish;	
	end


    always #5 a <= a+1;
    always #5 b<= b+1;
	initial begin
		$monitor ($time,"clk = %b, a=%b   b=%b \nsum=%b \n",clk,a,b,sum);
	for(i=0;i<16;i=i+1) 
		begin
	#20	$display ("kpgIn[%d]=%b",i,s1.wl4[i]);

		end
	end	

endmodule
module sum16bitTB();

	reg [15:0] a;
	reg    [15:0] b;
	reg [1:0] kIn;

       	integer i;
	wire [16:0] sum ;

	
	sum16bit s1(a,b,kIn,  sum);
	initial
	begin
		a <= {4{4'b1001}};
		b <= {4{4'b1111}};
		kIn <= 2'b00;

		#15 $finish;	
	end


    always #5 a <= a+1;
    always #5 b<= b+1;
	initial begin
		$monitor ($time,"clk = %b, a=%b   b=%b \nsum=%b \n",clk,a,b,sum);
	for(i=0;i<16;i=i+1) 
		begin
	#20	$display ("kpgIn[%d]=%b",i,s1.wl4[i]);

		end
	end	

endmodule