data/full_repos/permissive/158096953/alu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/158096953/alu_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clk <= ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158096953/alu_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/158096953/alu_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/158096953/alu_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n # 40\n ^\n%Warning-STMTDLY: data/full_repos/permissive/158096953/alu_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n # 40\n ^\n%Warning-STMTDLY: data/full_repos/permissive/158096953/alu_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n # 40\n ^\n%Warning-STMTDLY: data/full_repos/permissive/158096953/alu_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n # 40\n ^\n%Warning-STMTDLY: data/full_repos/permissive/158096953/alu_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n # 40\n ^\n%Error: data/full_repos/permissive/158096953/alu_tb.v:21: Cannot find file containing module: \'instr_excute\'\ninstr_excute alu(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158096953,data/full_repos/permissive/158096953/instr_excute\n             data/full_repos/permissive/158096953,data/full_repos/permissive/158096953/instr_excute.v\n             data/full_repos/permissive/158096953,data/full_repos/permissive/158096953/instr_excute.sv\n             instr_excute\n             instr_excute.v\n             instr_excute.sv\n             obj_dir/instr_excute\n             obj_dir/instr_excute.v\n             obj_dir/instr_excute.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb();

reg clk;
reg reset;
reg fsm_ie_en;
reg [4:0] of_ie_operation;
reg [7:0] of_ie_operand_des;
reg [7:0] of_ie_operand_sou;
reg [7:0] of_ie_operand_des_high;
reg [7:0] of_ie_operand_sou_high;
reg [7:0] of_ie_flag_reg;
wire [7:0] ie_os_result;
wire [7:0] ie_os_result_high;
wire [7:0] ie_os_flag_reg;
wire [7:0] ie_fsm_flag_reg;



instr_excute alu(
	clk,
	reset,
	fsm_ie_en,	
	of_ie_operand_des,
	of_ie_operand_des_high,
	of_ie_operand_sou,
	of_ie_operand_sou_high,
	of_ie_flag_reg,
	of_ie_operation,
	ie_os_result,
	ie_os_result_high,
	ie_os_flag_reg,
	ie_fsm_flag_reg
);

initial begin
	clk <= 1'b0;
	forever #20 clk <= ~clk;
end
initial begin
	fsm_ie_en = 1;
	reset = 1;
	#10 reset = 0;
	#10 reset = 1;
end

initial begin
	of_ie_operation = 5'd1;
	of_ie_operand_des = 8'd125;
	of_ie_operand_sou = 8'd100;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'h00;	
	# 40
	of_ie_operation = 5'd2;
	of_ie_operand_des = 8'd127;
	of_ie_operand_sou = 8'd126;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'hff;
	# 40
	of_ie_operation = 5'd3;
	of_ie_operand_des = 8'd125;
	of_ie_operand_sou = 8'd124;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'h00;	
	# 40
	of_ie_operation = 5'd4;
	of_ie_operand_des = 8'd124;
	of_ie_operand_sou = 8'd124;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'hff;	
	# 40
	of_ie_operation = 5'd3;
	of_ie_operand_des = 8'd0;
	of_ie_operand_sou = 8'h80;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'h00;	
	# 40
	of_ie_operation = 5'd3;
	of_ie_operand_des = 8'd0;
	of_ie_operand_sou = 8'h00;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'h00;		
end


endmodule
module alu_tb();


reg clk;
reg reset;
reg fsm_ie_en;
reg [4:0] of_ie_operation;
reg [7:0] of_ie_operand_des;
reg [7:0] of_ie_operand_sou;
reg [7:0] of_ie_operand_des_high;
reg [7:0] of_ie_operand_sou_high;
reg [7:0] of_ie_flag_reg;
wire [7:0] ie_os_result;
wire [7:0] ie_os_result_high;
wire [7:0] ie_os_flag_reg;
wire [7:0] ie_fsm_flag_reg;



instr_excute alu(
	clk,
	reset,
	fsm_ie_en,	
	of_ie_operand_des,
	of_ie_operand_des_high,
	of_ie_operand_sou,
	of_ie_operand_sou_high,
	of_ie_flag_reg,
	of_ie_operation,
	ie_os_result,
	ie_os_result_high,
	ie_os_flag_reg,
	ie_fsm_flag_reg
);

initial begin
	clk <= 1'b0;
	forever #20 clk <= ~clk;
end
initial begin
	fsm_ie_en = 1;
	reset = 1;
	#10 reset = 0;
	#10 reset = 1;
end

initial begin
	of_ie_operation = 5'd1;
	of_ie_operand_des = 8'd125;
	of_ie_operand_sou = 8'd100;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'h00;	
	# 40
	of_ie_operation = 5'd2;
	of_ie_operand_des = 8'd127;
	of_ie_operand_sou = 8'd126;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'hff;
	# 40
	of_ie_operation = 5'd3;
	of_ie_operand_des = 8'd125;
	of_ie_operand_sou = 8'd124;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'h00;	
	# 40
	of_ie_operation = 5'd4;
	of_ie_operand_des = 8'd124;
	of_ie_operand_sou = 8'd124;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'hff;	
	# 40
	of_ie_operation = 5'd3;
	of_ie_operand_des = 8'd0;
	of_ie_operand_sou = 8'h80;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'h00;	
	# 40
	of_ie_operation = 5'd3;
	of_ie_operand_des = 8'd0;
	of_ie_operand_sou = 8'h00;
	of_ie_operand_des_high = 8'd0;
	of_ie_operand_sou_high = 8'd0;
	of_ie_flag_reg = 8'h00;		
end


endmodule