data/full_repos/permissive/182885969/test/dm_tb.v
1: b'%Error: data/full_repos/permissive/182885969/test/dm_tb.v:8: Cannot find include file: dm.v\n`include "dm.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/182885969/test,data/full_repos/permissive/182885969/dm.v\n             data/full_repos/permissive/182885969/test,data/full_repos/permissive/182885969/dm.v.v\n             data/full_repos/permissive/182885969/test,data/full_repos/permissive/182885969/dm.v.sv\n             dm.v\n             dm.v.v\n             dm.v.sv\n             obj_dir/dm.v\n             obj_dir/dm.v.v\n             obj_dir/dm.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/182885969/test/dm_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/182885969/test/dm_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dm_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/182885969/test/dm_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, dm_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/182885969/test/dm_tb.v:32: Unsupported or unknown PLI call: $monitor\n  $monitor("%x,    %x,  %x,  %x, %x", addr, rd, wr, rdata, wdata);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/182885969/test/dm_tb.v:39: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/182885969/test/dm_tb.v:46: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/182885969/test/dm_tb.v:53: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/182885969/test/dm_tb.v:59: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/182885969/test/dm_tb.v:65: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 9 error(s), 1 warning(s)\n'
module dm_tb;

	reg clk;

	reg [6:0]	addr;
	reg			rd, wr;
	reg [31:0]	wdata;
	wire [31:0]	rdata;

	dm dm1(.clk(clk), .addr(addr), .rd(rd), .wr(wr),
				.rdata(rdata), .wdata(wdata));

	always begin
		clk <= ~clk;
		#5;
	end

	initial begin
		$dumpfile("dm_tb.vcd");
		$dumpvars(0, dm_tb);

		$display("addr,  rd, wr, rdata,    wdata");
		$monitor("%x,    %x,  %x,  %x, %x", addr, rd, wr, rdata, wdata);

		clk <= 1'b0;
		rd <= 1'b0;
		wr <= 1'b0;
		addr <= 7'd0;

		@(posedge clk);

		wdata <= 32'hABCDEF01;
		addr <= 7'd0;
		rd <= 1'b0;
		wr <= 1'b1;

		@(posedge clk);

		wdata <= 32'hFFFFAAAA;
		addr <= 7'd1;
		rd <= 1'b0;
		wr <= 1'b1;

		@(posedge clk);

		rd <= 1'b1;
		wr <= 1'b0;
		addr <= 7'd0;

		@(posedge clk);

		rd <= 1'b1;
		wr <= 1'b0;
		addr <= 7'd1;

		@(posedge clk);

		rd <= 1'b1;
		wr <= 1'b1;
		wdata <= 32'hFEFEFEFE;
		addr <= 7'd0;

		$finish;
	end

endmodule
module dm_tb;


	reg clk;

	reg [6:0]	addr;
	reg			rd, wr;
	reg [31:0]	wdata;
	wire [31:0]	rdata;

	dm dm1(.clk(clk), .addr(addr), .rd(rd), .wr(wr),
				.rdata(rdata), .wdata(wdata));

	always begin
		clk <= ~clk;
		#5;
	end

	initial begin
		$dumpfile("dm_tb.vcd");
		$dumpvars(0, dm_tb);

		$display("addr,  rd, wr, rdata,    wdata");
		$monitor("%x,    %x,  %x,  %x, %x", addr, rd, wr, rdata, wdata);

		clk <= 1'b0;
		rd <= 1'b0;
		wr <= 1'b0;
		addr <= 7'd0;

		@(posedge clk);

		wdata <= 32'hABCDEF01;
		addr <= 7'd0;
		rd <= 1'b0;
		wr <= 1'b1;

		@(posedge clk);

		wdata <= 32'hFFFFAAAA;
		addr <= 7'd1;
		rd <= 1'b0;
		wr <= 1'b1;

		@(posedge clk);

		rd <= 1'b1;
		wr <= 1'b0;
		addr <= 7'd0;

		@(posedge clk);

		rd <= 1'b1;
		wr <= 1'b0;
		addr <= 7'd1;

		@(posedge clk);

		rd <= 1'b1;
		wr <= 1'b1;
		wdata <= 32'hFEFEFEFE;
		addr <= 7'd0;

		$finish;
	end

endmodule