data/full_repos/permissive/178304323/vga.v
 line:9: before: ")"
1: b'%Error: data/full_repos/permissive/178304323/vga.v:9: syntax error, unexpected \')\', expecting \'[\'\n);\n^\n%Error: data/full_repos/permissive/178304323/vga.v:16: syntax error, unexpected IDENTIFIER\nSB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/178304323/vga.v:37: Too many digits for 32 bit number: \'h000000000000000000000000000000000f00011000010001200000000000000000000000000\nreg [300:0] storage = \'h000000000000000000000000000000000f00011000010001200000000000000000000000000;  \n                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/178304323/vga.v:44: syntax error, unexpected always\nalways @(posedge Vsync) begin\n^~~~~~\n%Error: data/full_repos/permissive/178304323/vga.v:50: syntax error, unexpected always\nalways @(posedge clk) begin\n^~~~~~\n%Error: data/full_repos/permissive/178304323/vga.v:121: syntax error, unexpected always\nalways @(negedge clock_div[4]) begin  \n^~~~~~\n%Error: Exiting due to 6 error(s)\n'
module vga(
    input wire pclk,
    output wire r,
    output wire g,
    output wire b,
    output wire Hsync,
    output wire Vsync,
    output wire D1,
);

wire clk; 




SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
    .PLLOUT_SELECT("GENCLK"),
    .DIVR(4'b001),
    .DIVF(7'b1000010),
    .DIVQ(3'b100),
    .FILTER_RANGE(3'b01),
) uut (
.REFERENCECLK(pclk),
.PLLOUTCORE(clk),
.LOCK(D5),
.RESETB(1'b1),
.BYPASS(1'b0)
);


reg [9:0] Hcounter;
reg [9:0] Vcounter;
reg [9:0] Hpixels;
reg [9:0] Vpixels;


reg [300:0] storage = 'h000000000000000000000000000000000f00011000010001200000000000000000000000000;
reg [22:0] storage_new;
reg [10:0] clock_div;
reg [40:0] human_clock;
reg [20:0] frame_counter = 0;


always @(posedge Vsync) begin
    frame_counter <= frame_counter + 1;
end

integer i;

always @(posedge clk) begin
    human_clock <= human_clock + 1;



    if (Hcounter < 799) begin
        Hcounter <= Hcounter + 1;
    end
    else begin
        Hcounter <= 0;
        clock_div <= 0;
        if (Vcounter < 520) begin
            Vcounter <= Vcounter + 1;
        end
        else begin
            Vcounter <= 0;
        end
    end


    if (Vcounter >= 30 & Vcounter < 511 & Hcounter >= 144 & Hcounter < 784) begin
        clock_div <= clock_div + 1;
    end

    



    if (frame_counter % 16 == 0) begin
        if (Vcounter == 0) begin
            if (Hcounter < 600) begin
                if (Hcounter % 2) begin

                    storage[0] <= storage[299];
                    for (i = 1; i < 300; i = i + 1) begin
                        storage[i] <= storage[i - 1];
                    end


                    storage_new[0] <= storage[299];
                    for (i = 1; i < 22; i = i + 1) begin
                        storage_new[i] <= storage_new[i-1];
                    end
                end
                if (!(Hcounter % 2)) begin

                    if (frame_counter > 320) begin
                       storage[0] <= ((storage_new[1] + storage_new[19]
                       + storage_new[20] + storage_new[21] + storage[279]
                       + storage[280] + storage[281] + storage[299])
                       | storage[0]) == 3;
                    end
                end
            end
        end
    end
end



assign Vsync = (Vcounter < 2) ? 0 : 1;
assign Hsync = (Hcounter < 96) ? 0 : 1;

assign D1 = human_clock[24];




assign r = ((Vcounter == 31 & Hcounter == 144) | (Vcounter == 510 & Hcounter == 783)) ? 1 : 0;

reg [8:0] counter; 
always @(negedge clock_div[4]) begin
    if (Hcounter > 780) begin
        counter <= ((Vcounter - 30) / 32) * 20;
    end
    else begin
        counter <= counter + 1;
    end
end

assign g = (Vcounter >= 31 & Vcounter < 511 & Hcounter >= 144 & Hcounter < 784 & (storage[counter]))? 1 : 0;


endmodule
module vga(
    input wire pclk,
    output wire r,
    output wire g,
    output wire b,
    output wire Hsync,
    output wire Vsync,
    output wire D1,
);


wire clk; 




SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
    .PLLOUT_SELECT("GENCLK"),
    .DIVR(4'b001),
    .DIVF(7'b1000010),
    .DIVQ(3'b100),
    .FILTER_RANGE(3'b01),
) uut (
.REFERENCECLK(pclk),
.PLLOUTCORE(clk),
.LOCK(D5),
.RESETB(1'b1),
.BYPASS(1'b0)
);


reg [9:0] Hcounter;
reg [9:0] Vcounter;
reg [9:0] Hpixels;
reg [9:0] Vpixels;


reg [300:0] storage = 'h000000000000000000000000000000000f00011000010001200000000000000000000000000;
reg [22:0] storage_new;
reg [10:0] clock_div;
reg [40:0] human_clock;
reg [20:0] frame_counter = 0;


always @(posedge Vsync) begin
    frame_counter <= frame_counter + 1;
end

integer i;

always @(posedge clk) begin
    human_clock <= human_clock + 1;



    if (Hcounter < 799) begin
        Hcounter <= Hcounter + 1;
    end
    else begin
        Hcounter <= 0;
        clock_div <= 0;
        if (Vcounter < 520) begin
            Vcounter <= Vcounter + 1;
        end
        else begin
            Vcounter <= 0;
        end
    end


    if (Vcounter >= 30 & Vcounter < 511 & Hcounter >= 144 & Hcounter < 784) begin
        clock_div <= clock_div + 1;
    end

    



    if (frame_counter % 16 == 0) begin
        if (Vcounter == 0) begin
            if (Hcounter < 600) begin
                if (Hcounter % 2) begin

                    storage[0] <= storage[299];
                    for (i = 1; i < 300; i = i + 1) begin
                        storage[i] <= storage[i - 1];
                    end


                    storage_new[0] <= storage[299];
                    for (i = 1; i < 22; i = i + 1) begin
                        storage_new[i] <= storage_new[i-1];
                    end
                end
                if (!(Hcounter % 2)) begin

                    if (frame_counter > 320) begin
                       storage[0] <= ((storage_new[1] + storage_new[19]
                       + storage_new[20] + storage_new[21] + storage[279]
                       + storage[280] + storage[281] + storage[299])
                       | storage[0]) == 3;
                    end
                end
            end
        end
    end
end



assign Vsync = (Vcounter < 2) ? 0 : 1;
assign Hsync = (Hcounter < 96) ? 0 : 1;

assign D1 = human_clock[24];




assign r = ((Vcounter == 31 & Hcounter == 144) | (Vcounter == 510 & Hcounter == 783)) ? 1 : 0;

reg [8:0] counter; 
always @(negedge clock_div[4]) begin
    if (Hcounter > 780) begin
        counter <= ((Vcounter - 30) / 32) * 20;
    end
    else begin
        counter <= counter + 1;
    end
end

assign g = (Vcounter >= 31 & Vcounter < 511 & Hcounter >= 144 & Hcounter < 784 & (storage[counter]))? 1 : 0;


endmodule