data/full_repos/permissive/143278/vpi/celldefine.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vpi/celldefine.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #1 in = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/vpi/celldefine.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1 in = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/vpi/celldefine.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1 in = 1\'b0;\n    ^\n%Error: data/full_repos/permissive/143278/vpi/celldefine.v:30: Unsupported or unknown PLI call: $is_cell\n    $is_cell(dut);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/vpi/celldefine.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (pass) $display("Verilog checking was OK.");\n    ^\n%Error: data/full_repos/permissive/143278/vpi/celldefine.v:31: Unsupported or unknown PLI call: $is_cell\n    $is_cell(dutb);\n    ^~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lower_no_cell(output out, input in);
  buf(out, in);
endmodule
module lower_no_cell(output out, input in);

  buf(out, in);
endmodule