data/full_repos/permissive/200478172/source/MUXBC.v
data/verilator_xmls/246c11c0-41f8-43d5-bd75-45d0251392de.xml
module MUXBC(
    input [31:0]a,
    input [31:0]b,
    input [31:0]c,
    input [31:0]d,
    input [1:0]ctr,
    
    output [31:0] z
    );
    reg [31:0] temp;
        always@(*)begin
            case(ctr)
                2'b00:temp<=a;
                2'b01:temp<=b;
                2'b10:temp<=c;
                2'b11:temp<=d;
            endcase
        end
        assign z=temp;
endmodule
module MUXBC(
    input [31:0]a,
    input [31:0]b,
    input [31:0]c,
    input [31:0]d,
    input [1:0]ctr,
    
    output [31:0] z
    );

    reg [31:0] temp;
        always@(*)begin
            case(ctr)
                2'b00:temp<=a;
                2'b01:temp<=b;
                2'b10:temp<=c;
                2'b11:temp<=d;
            endcase
        end
        assign z=temp;
endmodule