data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog/okWireOut.v
1: b'%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog/okWireOut.v:20: Cannot find include file: parameters.v\n`include "parameters.v"  \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/parameters.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/parameters.v.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog/okWireOut.v:21: Cannot find include file: mappings.v\n`include "mappings.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module okWireOut(
	input  wire [112:0] okHE,
	output wire [64:0]  okEH,
	input  wire [7:0]   ep_addr,
	input  wire [31:0]  ep_datain
	);

`include "parameters.v" 
`include "mappings.v"

reg  [31:0] wirehold;

assign okEH[okEH_DATAH:okEH_DATAL] = (ti_addr == ep_addr) ? (wirehold) : (0);
assign okEH[okEH_READY]            = 0;
assign okEH[okEH_REGREADDATAH:okEH_REGREADDATAL] = 32'b0;

always @(posedge ti_clk) begin
	if (ti_reset == 1)
		wirehold <= 0;
	else if (ti_wireupdate == 1)
		wirehold <= ep_datain;
end

endmodule
module okWireOut(
	input  wire [112:0] okHE,
	output wire [64:0]  okEH,
	input  wire [7:0]   ep_addr,
	input  wire [31:0]  ep_datain
	);


`include "parameters.v" 
`include "mappings.v"

reg  [31:0] wirehold;

assign okEH[okEH_DATAH:okEH_DATAL] = (ti_addr == ep_addr) ? (wirehold) : (0);
assign okEH[okEH_READY]            = 0;
assign okEH[okEH_REGREADDATAH:okEH_REGREADDATAL] = 32'b0;

always @(posedge ti_clk) begin
	if (ti_reset == 1)
		wirehold <= 0;
	else if (ti_wireupdate == 1)
		wirehold <= ep_datain;
end

endmodule