data/full_repos/permissive/198643510/prewish_blinky.v
data/verilator_xmls/09eb1e1b-0a5d-4d05-b19b-c08520c869dc.xml
module prewish_blinky (
    input CLK_I,
    input RST_I,
    input STB_I,
    input[7:0] DAT_I,
    output o_alive,
    output o_led
);
    reg[7:0] mask = 0;


    parameter SYSCLK_DIV_BITS = 22;
    reg [SYSCLK_DIV_BITS-1:0] ckdiv = 0;
    reg ledreg = 0;

    always @(posedge CLK_I) begin
        if(RST_I == 1) begin
            ckdiv <= 0;
            mask <= 0;
            ledreg <= 0;
        end else begin
            if(STB_I == 1) begin
                ckdiv <= 0;
                ledreg <= 0;
                mask <= DAT_I;
            end else begin
                ckdiv <= ckdiv + 1;


                if(ckdiv == 1) begin
                    mask <= mask <<< 1;
                    mask[0] <= mask[7];
                    ledreg <= mask[7];
                end
            end
        end
    end


    assign o_led = ledreg;


    assign o_alive = ckdiv[SYSCLK_DIV_BITS-1];

endmodule
module prewish_blinky (
    input CLK_I,
    input RST_I,
    input STB_I,
    input[7:0] DAT_I,
    output o_alive,
    output o_led
);

    reg[7:0] mask = 0;


    parameter SYSCLK_DIV_BITS = 22;
    reg [SYSCLK_DIV_BITS-1:0] ckdiv = 0;
    reg ledreg = 0;

    always @(posedge CLK_I) begin
        if(RST_I == 1) begin
            ckdiv <= 0;
            mask <= 0;
            ledreg <= 0;
        end else begin
            if(STB_I == 1) begin
                ckdiv <= 0;
                ledreg <= 0;
                mask <= DAT_I;
            end else begin
                ckdiv <= ckdiv + 1;


                if(ckdiv == 1) begin
                    mask <= mask <<< 1;
                    mask[0] <= mask[7];
                    ledreg <= mask[7];
                end
            end
        end
    end


    assign o_led = ledreg;


    assign o_alive = ckdiv[SYSCLK_DIV_BITS-1];

endmodule