data/full_repos/permissive/167274925/Mux32Bit2To1.v
data/verilator_xmls/a6bc9ae7-422c-4788-890a-9291e2f77816.xml
module Mux32Bit2To1(out, inA, inB, sel);

    output reg [31:0] out;
   
    input [31:0] inA;
    input [31:0] inB;
    input sel;
 
   always@(inA,inB,sel)begin 
      case(sel)
      1'b0:out<=inA;
      1'b1:out<=inB;
      endcase 
   end 
endmodule
module Mux32Bit2To1(out, inA, inB, sel);


    output reg [31:0] out;
   
    input [31:0] inA;
    input [31:0] inB;
    input sel;
 
   always@(inA,inB,sel)begin 
      case(sel)
      1'b0:out<=inA;
      1'b1:out<=inB;
      endcase 
   end 
endmodule