data/full_repos/permissive/184431263/AOI/AOI42.v
data/verilator_xmls/94c3f4d1-a058-4552-8864-17af1a0e1c46.xml
module AOI42(Y, A0, A1, A2, A3, B0, B1, B2, B3, VDD, VSS );
  input A0, A1, A2, A3, B0, B1, B2, B3;
  output Y;
  inout VDD, VSS;

  assign Y=~((A0 && A1 && A2 && A3) || (B0 && B1 && B2 && B3));
endmodule
module AOI42(Y, A0, A1, A2, A3, B0, B1, B2, B3, VDD, VSS );

  input A0, A1, A2, A3, B0, B1, B2, B3;
  output Y;
  inout VDD, VSS;

  assign Y=~((A0 && A1 && A2 && A3) || (B0 && B1 && B2 && B3));
endmodule