data/full_repos/permissive/212763527/school_project/3_mux4_1/sources/basic_gates.v
 line:29: before: "TabNine"
1: b"%Error: data/full_repos/permissive/212763527/school_project/3_mux4_1/sources/basic_gates.v:29: syntax error, unexpected IDENTIFIER\nTabNine::config\n^~~~~~~\n%Error: data/full_repos/permissive/212763527/school_project/3_mux4_1/sources/basic_gates.v:29: Unsupported: Verilog 2001-config reserved word not implemented: 'config'\nTabNine::config\n         ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module gate_and #(parameter WIDTH = 32)
                 (input[WIDTH-1:0] a,
                  input[WIDTH-1:0] b,
                  output[WIDTH-1:0] c);
    assign c = a & b;
    
endmodule
module gate_and #(parameter WIDTH = 32)
                 (input[WIDTH-1:0] a,
                  input[WIDTH-1:0] b,
                  output[WIDTH-1:0] c);

    assign c = a & b;
    
endmodule