data/full_repos/permissive/208113388/afu/afp/mcp3_ram128x036q.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/f027d768-9c9d-4617-ba1b-007239059754.xml
module mcp3_ram128x036q (


    input              clk


  , input              wren
  , input        [6:0] wrad
  , input       [35:0] data


  , input              rden
  , input        [6:0] rdad
  , output reg  [35:0] q

  );

 (* ram_style = "block" *)

  reg    [35:0] ram [0:127];
  reg    [35:0] q_int;

  always @(posedge clk)
    begin
      if ( wren == 1'b1 )
        ram [wrad] <= data[35:0];
    
      if ( rden == 1'b1)
        begin
          if (( rdad[6:0] != wrad[6:0] ) || ( wren == 1'b0 ))
             q_int[35:0] <= ram[rdad];
          else
             q_int[35:0] <= 36'bx; 
        end
      else
        q_int[35:0] <= 36'b0;


     q[35:0] <= q_int[35:0];

   end

endmodule
module mcp3_ram128x036q (


    input              clk


  , input              wren
  , input        [6:0] wrad
  , input       [35:0] data


  , input              rden
  , input        [6:0] rdad
  , output reg  [35:0] q

  );


 (* ram_style = "block" *)

  reg    [35:0] ram [0:127];
  reg    [35:0] q_int;

  always @(posedge clk)
    begin
      if ( wren == 1'b1 )
        ram [wrad] <= data[35:0];
    
      if ( rden == 1'b1)
        begin
          if (( rdad[6:0] != wrad[6:0] ) || ( wren == 1'b0 ))
             q_int[35:0] <= ram[rdad];
          else
             q_int[35:0] <= 36'bx; 
        end
      else
        q_int[35:0] <= 36'b0;


     q[35:0] <= q_int[35:0];

   end

endmodule