data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v
None: at end of input
1: b'%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:1: Cannot find include file: cypress.v\n`include "cypress.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg,data/full_repos/permissive/193054270/cypress.v\n             data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg,data/full_repos/permissive/193054270/cypress.v.v\n             data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg,data/full_repos/permissive/193054270/cypress.v.sv\n             cypress.v\n             cypress.v.v\n             cypress.v.sv\n             obj_dir/cypress.v\n             obj_dir/cypress.v.v\n             obj_dir/cypress.v.sv\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:51: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:51: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                   ^\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:51: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:51: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:52: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:52: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:52: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:53: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:53: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:53: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:54: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:55: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:55: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:55: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:56: Define or directive not defined: \'`CS_SHFT_OP___SL\'\n    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:56: Define or directive not defined: \'`CS_A0_SRC__ALU\'\n    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:56: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:57: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:57: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:57: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:58: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:59: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:59: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:59: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:60: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:60: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:60: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:61: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:61: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:61: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:62: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:63: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:63: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:63: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:64: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:64: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:64: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:65: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:65: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:65: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:66: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:67: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:67: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:67: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:68: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:68: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:68: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:69: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg/shift_reg.cydsn/shift_reg/shift_reg.v:69: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module shift_reg (
	output  isr,
	input   clock
);

localparam REG_IDLE  = 3'd0;
localparam REG_SHIFT = 3'd1;

reg f0_load_flag;
reg si_value;
reg[4:0] bit_count;
reg[2:0] reg_state;

reg[3:0] step;
reg[4:0] step_count;

always @(posedge clock)
begin
case(reg_state)
    REG_IDLE:
    begin
        f0_load_flag = 1'b0;
        
        step_count = step_count + 1'b1;
        if(step_count == step)
        begin
            si_value = 1'b1;
            step_count = 1'b0;
            step = step + 1'b1;
        end
        else
        begin
            si_value = 1'b0;
        end
        
        reg_state = REG_SHIFT;
    end
    REG_SHIFT:
    begin
        bit_count = bit_count + 5'd1;
        f0_load_flag = (bit_count == 5'd0);
        reg_state = REG_IDLE;
    end
endcase
end

cy_psoc3_dp32 #(
.cy_dpconfig_a({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_ROUTE,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_b({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO__EDGE,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_c({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A0_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO__EDGE,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_d({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A0_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO__EDGE,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}))dp(
.clk(clock),
.cs_addr(reg_state),
.route_si(si_value),
.route_ci(1'b0),
.f0_load(f0_load_flag),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.f0_bus_stat(isr),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);

endmodule
module shift_reg (
	output  isr,
	input   clock
);


localparam REG_IDLE  = 3'd0;
localparam REG_SHIFT = 3'd1;

reg f0_load_flag;
reg si_value;
reg[4:0] bit_count;
reg[2:0] reg_state;

reg[3:0] step;
reg[4:0] step_count;

always @(posedge clock)
begin
case(reg_state)
    REG_IDLE:
    begin
        f0_load_flag = 1'b0;
        
        step_count = step_count + 1'b1;
        if(step_count == step)
        begin
            si_value = 1'b1;
            step_count = 1'b0;
            step = step + 1'b1;
        end
        else
        begin
            si_value = 1'b0;
        end
        
        reg_state = REG_SHIFT;
    end
    REG_SHIFT:
    begin
        bit_count = bit_count + 5'd1;
        f0_load_flag = (bit_count == 5'd0);
        reg_state = REG_IDLE;
    end
endcase
end

cy_psoc3_dp32 #(
.cy_dpconfig_a({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_ROUTE,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_b({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO__EDGE,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_c({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A0_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO__EDGE,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_d({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A0_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO__EDGE,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}))dp(
.clk(clock),
.cs_addr(reg_state),
.route_si(si_value),
.route_ci(1'b0),
.f0_load(f0_load_flag),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.f0_bus_stat(isr),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);

endmodule