data/full_repos/permissive/104305228/code/id_ex.v
1: b'%Error: data/full_repos/permissive/104305228/code/id_ex.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:25: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:25: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n  if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin\n                        ^~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:25: Define or directive not defined: \'`StallEnable\'\n  if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin\n                                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:25: Define or directive not defined: \'`StallDisable\'\n  if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin\n                                                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:27: Define or directive not defined: \'`op_null\'\n   ex_op <= `op_null;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_op <= `op_null;\n                    ^\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:28: Define or directive not defined: \'`type_null\'\n   ex_type <= `type_null;\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:28: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_type <= `type_null;\n                        ^\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:31: Define or directive not defined: \'`WriteDisable\'\n   ex_we <= `WriteDisable;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:31: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_we <= `WriteDisable;\n                         ^\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:35: syntax error, unexpected else\n  else if (stall[2] == `StallDisable) begin\n  ^~~~\n%Error: data/full_repos/permissive/104305228/code/id_ex.v:35: Define or directive not defined: \'`StallDisable\'\n  else if (stall[2] == `StallDisable) begin\n                       ^~~~~~~~~~~~~\n%Error: Cannot continue\n'
module id_ex(
	input clk,
	input rst,
	input [5:0] stall,
	input [31:0] id_instr,
	input [7:0] id_op,
	input [2:0] id_type,
	input [31:0] id_reg1,
	input [31:0] id_reg2,
	input id_we,
	input [4:0] id_write_addr,
	input [31:0] id_write_instr,

	output reg[31:0] ex_instr,
	output reg[7:0] ex_op,
	output reg[2:0] ex_type,
	output reg[31:0] ex_reg1,
	output reg[31:0] ex_reg2,
	output reg ex_we,
	output reg[4:0] ex_write_addr,
	output reg[31:0] ex_write_instr
);
	always @ (posedge clk) begin
		if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin
			ex_instr <= 32'b0;
			ex_op <= `op_null;
			ex_type <= `type_null;
			ex_reg1 <= 32'b0;
			ex_reg2 <= 32'b0;
			ex_we <= `WriteDisable;
			ex_write_addr <= 32'b0;
			ex_write_instr <= 32'b0;
		end
		else if (stall[2] == `StallDisable) begin
			ex_instr <= id_instr;
			ex_op <= id_op;
			ex_type <= id_type;
			ex_reg1 <= id_reg1;
			ex_reg2 <= id_reg2;
			ex_we <= id_we;
			ex_write_addr <= id_write_addr;
			ex_write_instr <= id_write_instr;
		end
	end
endmodule
module id_ex(
	input clk,
	input rst,
	input [5:0] stall,
	input [31:0] id_instr,
	input [7:0] id_op,
	input [2:0] id_type,
	input [31:0] id_reg1,
	input [31:0] id_reg2,
	input id_we,
	input [4:0] id_write_addr,
	input [31:0] id_write_instr,

	output reg[31:0] ex_instr,
	output reg[7:0] ex_op,
	output reg[2:0] ex_type,
	output reg[31:0] ex_reg1,
	output reg[31:0] ex_reg2,
	output reg ex_we,
	output reg[4:0] ex_write_addr,
	output reg[31:0] ex_write_instr
);

	always @ (posedge clk) begin
		if (rst == `RstEnable || (stall[2] == `StallEnable && stall[3] == `StallDisable)) begin
			ex_instr <= 32'b0;
			ex_op <= `op_null;
			ex_type <= `type_null;
			ex_reg1 <= 32'b0;
			ex_reg2 <= 32'b0;
			ex_we <= `WriteDisable;
			ex_write_addr <= 32'b0;
			ex_write_instr <= 32'b0;
		end
		else if (stall[2] == `StallDisable) begin
			ex_instr <= id_instr;
			ex_op <= id_op;
			ex_type <= id_type;
			ex_reg1 <= id_reg1;
			ex_reg2 <= id_reg2;
			ex_we <= id_we;
			ex_write_addr <= id_write_addr;
			ex_write_instr <= id_write_instr;
		end
	end
endmodule