data/full_repos/permissive/157101210/alu.v
data/verilator_xmls/37bfacbe-b9ac-4c25-bf23-ddd091e41228.xml
module ALUBitSlice(
	input a,
	input b,
	input[5:0] opcode,
	input[5:0] funct,
	input carryIn,
	output res,
	output carryOut,
	output reg isSubtract
);
wire addRes;
wire finalAdd;
wire xorRes;
wire finalXor;
wire finalA;
reg isA;
reg isAdd;
reg isXor;

	AdderAndSubtractor adder (
        .res (addRes),
        .carryout (carryOut),
        .a (a),
        .b (b),
        .isSubtract (isSubtract),
        .carryin (carryIn)
    );

    xor xorRes(xorRes, a, b);


	always @(opcode or funct) begin
		case (opcode)
			`LW_OP:   begin isA=0; isAdd=1; isXor=0; isSubtract=0; end
			`SW_OP:   begin isA=0; isAdd=1; isXor=0; isSubtract=0; end
			`J_OP:    begin isA=1; isAdd=0; isXor=0; isSubtract=0; end
			`JAL_OP:  begin isA=1; isAdd=0; isXor=0; isSubtract=0; end
			`BEQ_OP:  begin isA=0; isAdd=1; isXor=0; isSubtract=1; end
			`BNE_OP:  begin isA=0; isAdd=1; isXor=0; isSubtract=1; end
			`XORI_OP: begin isA=0; isAdd=0; isXor=1; isSubtract=0; end
			`ADDI_OP: begin isA=0; isAdd=1; isXor=0; isSubtract=0; end

			`RTYPE_OP: begin
				case (funct)
					`JR_FUNCT:  begin isA=1; isAdd=0; isXor=0; isSubtract=0; end
					`ADD_FUNCT: begin isA=0; isAdd=1; isXor=0; isSubtract=0; end
					`SUB_FUNCT: begin isA=0; isAdd=1; isXor=0; isSubtract=1; end
					`SLT_FUNCT: begin isA=0; isAdd=1; isXor=0; isSubtract=1; end
					default: $display("Error in ALUBitSlice: Invalid funct");
				endcase
			end
			default: $display("Error in ALU: Invalid opcode. OPCODE: %b", opcode);
		endcase
	end

	and andAdd(finalAdd, addRes, isAdd);
	and andXor(finalXor, xorRes, isXor);
	and andA(finalA, a, isA);

	or orRes(res, finalAdd, finalXor, finalA);

endmodule
module ALUBitSlice(
	input a,
	input b,
	input[5:0] opcode,
	input[5:0] funct,
	input carryIn,
	output res,
	output carryOut,
	output reg isSubtract
);

wire addRes;
wire finalAdd;
wire xorRes;
wire finalXor;
wire finalA;
reg isA;
reg isAdd;
reg isXor;

	AdderAndSubtractor adder (
        .res (addRes),
        .carryout (carryOut),
        .a (a),
        .b (b),
        .isSubtract (isSubtract),
        .carryin (carryIn)
    );

    xor xorRes(xorRes, a, b);


	always @(opcode or funct) begin
		case (opcode)
			`LW_OP:   begin isA=0; isAdd=1; isXor=0; isSubtract=0; end
			`SW_OP:   begin isA=0; isAdd=1; isXor=0; isSubtract=0; end
			`J_OP:    begin isA=1; isAdd=0; isXor=0; isSubtract=0; end
			`JAL_OP:  begin isA=1; isAdd=0; isXor=0; isSubtract=0; end
			`BEQ_OP:  begin isA=0; isAdd=1; isXor=0; isSubtract=1; end
			`BNE_OP:  begin isA=0; isAdd=1; isXor=0; isSubtract=1; end
			`XORI_OP: begin isA=0; isAdd=0; isXor=1; isSubtract=0; end
			`ADDI_OP: begin isA=0; isAdd=1; isXor=0; isSubtract=0; end

			`RTYPE_OP: begin
				case (funct)
					`JR_FUNCT:  begin isA=1; isAdd=0; isXor=0; isSubtract=0; end
					`ADD_FUNCT: begin isA=0; isAdd=1; isXor=0; isSubtract=0; end
					`SUB_FUNCT: begin isA=0; isAdd=1; isXor=0; isSubtract=1; end
					`SLT_FUNCT: begin isA=0; isAdd=1; isXor=0; isSubtract=1; end
					default: $display("Error in ALUBitSlice: Invalid funct");
				endcase
			end
			default: $display("Error in ALU: Invalid opcode. OPCODE: %b", opcode);
		endcase
	end

	and andAdd(finalAdd, addRes, isAdd);
	and andXor(finalXor, xorRes, isXor);
	and andA(finalA, a, isA);

	or orRes(res, finalAdd, finalXor, finalA);

endmodule