data/full_repos/permissive/208741034/cymometer/rtl/clk.v
1: b'%Warning-WIDTH: data/full_repos/permissive/208741034/cymometer/rtl/clk.v:20: Operator DIV expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'DIV_N\' generates 7 bits.\n                                                                           : ... In instance clk\n        if(cnt == DIV_N/2 - 1\'b1) begin\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module clk #(parameter DIV_N = 7'd100)
(
  input sys_clk,
  input rst_n,
  
  output reg clk_out

);

reg [9 : 0]cnt;



always @(posedge sys_clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
        cnt     <= 0;
        clk_out <= 0;
    end
    else begin
        if(cnt == DIV_N/2 - 1'b1) begin
            cnt     <= 10'd0;
            clk_out <= ~clk_out;
        end
        else
            cnt <= cnt + 1'b1;
    end
end


endmodule
module clk #(parameter DIV_N = 7'd100)
(
  input sys_clk,
  input rst_n,
  
  output reg clk_out

);


reg [9 : 0]cnt;



always @(posedge sys_clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
        cnt     <= 0;
        clk_out <= 0;
    end
    else begin
        if(cnt == DIV_N/2 - 1'b1) begin
            cnt     <= 10'd0;
            clk_out <= ~clk_out;
        end
        else
            cnt <= cnt + 1'b1;
    end
end


endmodule