data/full_repos/permissive/13136965/mux5bit.v
1: b"%Error: data/full_repos/permissive/13136965/mux5bit.v:2: Duplicate declaration of signal: 'y'\n                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg [4:0] y;\n          ^\n        data/full_repos/permissive/13136965/mux5bit.v:1: ... Location of original declaration\nmodule mux5bit (input [4:0] a,input [4:0] b,output [4:0] y,input sel); \n                                                         ^\n%Error: Exiting due to 1 error(s)\n"
module mux5bit (input [4:0] a,input [4:0] b,output [4:0] y,input sel); 
reg [4:0] y;

always @(b or a or sel)
begin
	case ( sel )
		0 : y = a;
		1 : y = b;
	endcase
end 
endmodule
module mux5bit (input [4:0] a,input [4:0] b,output [4:0] y,input sel);
 
reg [4:0] y;

always @(b or a or sel)
begin
	case ( sel )
		0 : y = a;
		1 : y = b;
	endcase
end 
endmodule