data/full_repos/permissive/109936328/tb/tb_id.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/tb/tb_id.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:2: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:4: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:16: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] i_pc = 0;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:17: Define or directive not defined: \'`INSTR_W\'\n  reg [`INSTR_W - 1:0] i_instr = 0;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:19: Define or directive not defined: \'`REG_IDX_W\'\n  reg [`REG_IDX_W - 1:0] ex_dest_reg = 0;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:20: Define or directive not defined: \'`DEST_SRC_W\'\n  reg [`DEST_SRC_W - 1:0] ex_dest_src = `DEST_SRC_NONE;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:20: Define or directive not defined: \'`DEST_SRC_NONE\'\n  reg [`DEST_SRC_W - 1:0] ex_dest_src = `DEST_SRC_NONE;\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:20: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  reg [`DEST_SRC_W - 1:0] ex_dest_src = `DEST_SRC_NONE;\n                                                      ^\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:21: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] ex_alu_eval = 0;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:23: Define or directive not defined: \'`REG_IDX_W\'\n  reg [`REG_IDX_W - 1:0] me_dest_reg;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:24: Define or directive not defined: \'`DEST_SRC_W\'\n  reg [`DEST_SRC_W - 1:0] me_dest_src = `DEST_SRC_NONE;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:24: Define or directive not defined: \'`DEST_SRC_NONE\'\n  reg [`DEST_SRC_W - 1:0] me_dest_src = `DEST_SRC_NONE;\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  reg [`DEST_SRC_W - 1:0] me_dest_src = `DEST_SRC_NONE;\n                                                      ^\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:25: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] me_dest_data;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:28: Define or directive not defined: \'`REG_IDX_W\'\n  reg [`REG_IDX_W - 1:0] wb_dest_reg;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:29: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] wb_dest_data;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:31: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 1:0] o_pc;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:32: Define or directive not defined: \'`INSTR_W\'\n  wire [`INSTR_W - 1:0] o_instr;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:34: Define or directive not defined: \'`ALU_OP_W\'\n  wire [`ALU_OP_W - 1:0] alu_op;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:36: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] alu_data_a;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:37: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] alu_data_b;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:38: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] imm;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:40: Define or directive not defined: \'`MEM_OP_W\'\n  wire [`MEM_OP_W - 1:0] mem_op;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:42: Define or directive not defined: \'`DEST_SRC_W\'\n  wire [`DEST_SRC_W - 1:0] dest_src;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:43: Define or directive not defined: \'`REG_IDX_W\'\n  wire [`REG_IDX_W - 1:0] dest_reg;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:49: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_id.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_id.v:50: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_id.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #(RESET_DURATION * CLK_PERIOD);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_id.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #(5 * CLK_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_id.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD / 2);\n    ^\n%Error: Exiting due to 29 error(s), 3 warning(s)\n'
module tb_id;

  localparam CLK_PERIOD = 2;
  localparam RESET_DURATION = 5;

  reg clk = 0;
  reg clr = 0;
  reg stall = 0;
  reg rf_aresetn = 0;

  reg [`ADDR_W - 1:0] i_pc = 0;
  reg [`INSTR_W - 1:0] i_instr = 0;

  reg [`REG_IDX_W - 1:0] ex_dest_reg = 0;
  reg [`DEST_SRC_W - 1:0] ex_dest_src = `DEST_SRC_NONE;
  reg [`WORD_W - 1:0] ex_alu_eval = 0;

  reg [`REG_IDX_W - 1:0] me_dest_reg;
  reg [`DEST_SRC_W - 1:0] me_dest_src = `DEST_SRC_NONE;
  reg [`WORD_W - 1:0] me_dest_data;

  reg wb_dest_en = 0;
  reg [`REG_IDX_W - 1:0] wb_dest_reg;
  reg [`WORD_W - 1:0] wb_dest_data;

  wire [`ADDR_W - 1:0] o_pc;
  wire [`INSTR_W - 1:0] o_instr;

  wire [`ALU_OP_W - 1:0] alu_op;

  wire [`WORD_W - 1:0] alu_data_a;
  wire [`WORD_W - 1:0] alu_data_b;
  wire [`WORD_W - 1:0] imm;

  wire [`MEM_OP_W - 1:0] mem_op;

  wire [`DEST_SRC_W - 1:0] dest_src;
  wire [`REG_IDX_W - 1:0] dest_reg;

  wire mem_hazard;

  initial begin

    $dumpfile("tb_id.vcd");
    $dumpvars;
    
    clk = 0;
    clr = 1;
    stall = 0;
    rf_aresetn = 0;

    i_pc = 0;
    i_instr = 0;
    
    wb_dest_en = 0;
    wb_dest_reg = 0;
    wb_dest_data = 0;

    #(RESET_DURATION * CLK_PERIOD);

    clr = 0;
    rf_aresetn = 1;

    i_instr = {12'hfff, 5'b00000, 3'b000, 5'b00001, 7'b0010011};

    #(5 * CLK_PERIOD);

    $display("%0x", i_instr);
    $display("%0x", alu_op);
    $display("%0d", $signed(imm));
    $display("%0d", $signed(dut.s_reg_data_a));
    $display("%0d", $signed(alu_data_b));

    $finish;
  end

  always begin
    #(CLK_PERIOD / 2);
    clk = ~clk;
  end

  id dut(
    .clk(clk),
    .clr(clr),
    .stall(stall),
    .rf_reset(rf_aresetn),

    .i_pc(i_pc),
    .i_instr(i_instr),

    .i_ex_dest_reg(ex_dest_reg),
    .i_ex_dest_src(ex_dest_src),
    .i_ex_alu_eval(ex_alu_eval),

    .i_me_dest_reg(me_dest_reg),
    .i_me_dest_src(me_dest_src),
    .i_me_dest_data(me_dest_data),

    .i_wb_dest_en(wb_dest_en),
    .i_wb_dest_reg(wb_dest_reg),
    .i_wb_dest_data(wb_dest_data),

    .o_pc(o_pc),
    .o_instr(o_instr),

    .o_alu_op(alu_op),
    
    .o_alu_data_a(alu_data_a),
    .o_alu_data_b(alu_data_b),
    .o_imm(imm),

    .o_mem_op(mem_op),

    .o_dest_src(dest_src),
    .o_dest_reg(dest_reg),

    .o_mem_hazard(mem_hazard)
  );

endmodule
module tb_id;


  localparam CLK_PERIOD = 2;
  localparam RESET_DURATION = 5;

  reg clk = 0;
  reg clr = 0;
  reg stall = 0;
  reg rf_aresetn = 0;

  reg [`ADDR_W - 1:0] i_pc = 0;
  reg [`INSTR_W - 1:0] i_instr = 0;

  reg [`REG_IDX_W - 1:0] ex_dest_reg = 0;
  reg [`DEST_SRC_W - 1:0] ex_dest_src = `DEST_SRC_NONE;
  reg [`WORD_W - 1:0] ex_alu_eval = 0;

  reg [`REG_IDX_W - 1:0] me_dest_reg;
  reg [`DEST_SRC_W - 1:0] me_dest_src = `DEST_SRC_NONE;
  reg [`WORD_W - 1:0] me_dest_data;

  reg wb_dest_en = 0;
  reg [`REG_IDX_W - 1:0] wb_dest_reg;
  reg [`WORD_W - 1:0] wb_dest_data;

  wire [`ADDR_W - 1:0] o_pc;
  wire [`INSTR_W - 1:0] o_instr;

  wire [`ALU_OP_W - 1:0] alu_op;

  wire [`WORD_W - 1:0] alu_data_a;
  wire [`WORD_W - 1:0] alu_data_b;
  wire [`WORD_W - 1:0] imm;

  wire [`MEM_OP_W - 1:0] mem_op;

  wire [`DEST_SRC_W - 1:0] dest_src;
  wire [`REG_IDX_W - 1:0] dest_reg;

  wire mem_hazard;

  initial begin

    $dumpfile("tb_id.vcd");
    $dumpvars;
    
    clk = 0;
    clr = 1;
    stall = 0;
    rf_aresetn = 0;

    i_pc = 0;
    i_instr = 0;
    
    wb_dest_en = 0;
    wb_dest_reg = 0;
    wb_dest_data = 0;

    #(RESET_DURATION * CLK_PERIOD);

    clr = 0;
    rf_aresetn = 1;

    i_instr = {12'hfff, 5'b00000, 3'b000, 5'b00001, 7'b0010011};

    #(5 * CLK_PERIOD);

    $display("%0x", i_instr);
    $display("%0x", alu_op);
    $display("%0d", $signed(imm));
    $display("%0d", $signed(dut.s_reg_data_a));
    $display("%0d", $signed(alu_data_b));

    $finish;
  end

  always begin
    #(CLK_PERIOD / 2);
    clk = ~clk;
  end

  id dut(
    .clk(clk),
    .clr(clr),
    .stall(stall),
    .rf_reset(rf_aresetn),

    .i_pc(i_pc),
    .i_instr(i_instr),

    .i_ex_dest_reg(ex_dest_reg),
    .i_ex_dest_src(ex_dest_src),
    .i_ex_alu_eval(ex_alu_eval),

    .i_me_dest_reg(me_dest_reg),
    .i_me_dest_src(me_dest_src),
    .i_me_dest_data(me_dest_data),

    .i_wb_dest_en(wb_dest_en),
    .i_wb_dest_reg(wb_dest_reg),
    .i_wb_dest_data(wb_dest_data),

    .o_pc(o_pc),
    .o_instr(o_instr),

    .o_alu_op(alu_op),
    
    .o_alu_data_a(alu_data_a),
    .o_alu_data_b(alu_data_b),
    .o_imm(imm),

    .o_mem_op(mem_op),

    .o_dest_src(dest_src),
    .o_dest_reg(dest_reg),

    .o_mem_hazard(mem_hazard)
  );

endmodule