data/full_repos/permissive/140357212/Tomasulo/tomasulo.v
1: b'%Error: data/full_repos/permissive/140357212/Tomasulo/tomasulo.v:12: Cannot find file containing module: \'controle\'\n controle c1(KEY[0],inst,Regs[0],Regs[1],Regs[2],Regs[3],label_add,Tempo,Add_full,Mult_full);\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/140357212/Tomasulo,data/full_repos/permissive/140357212/controle\n             data/full_repos/permissive/140357212/Tomasulo,data/full_repos/permissive/140357212/controle.v\n             data/full_repos/permissive/140357212/Tomasulo,data/full_repos/permissive/140357212/controle.sv\n             controle\n             controle.v\n             controle.sv\n             obj_dir/controle\n             obj_dir/controle.v\n             obj_dir/controle.sv\n%Error: data/full_repos/permissive/140357212/Tomasulo/tomasulo.v:13: Cannot find file containing module: \'sete_seg\'\n sete_seg add(add_full,HEX5);\n ^~~~~~~~\n%Error: data/full_repos/permissive/140357212/Tomasulo/tomasulo.v:14: Cannot find file containing module: \'sete_seg\'\n sete_seg mult(Mult_full,HEX4);\n ^~~~~~~~\n%Error: data/full_repos/permissive/140357212/Tomasulo/tomasulo.v:15: Cannot find file containing module: \'sete_seg\'\n sete_seg reg0(Regs[0],HEX0);\n ^~~~~~~~\n%Error: data/full_repos/permissive/140357212/Tomasulo/tomasulo.v:16: Cannot find file containing module: \'sete_seg\'\n sete_seg reg1(Regs[1],HEX1);\n ^~~~~~~~\n%Error: data/full_repos/permissive/140357212/Tomasulo/tomasulo.v:17: Cannot find file containing module: \'sete_seg\'\n sete_seg reg2(Regs[2],HEX2);\n ^~~~~~~~\n%Error: data/full_repos/permissive/140357212/Tomasulo/tomasulo.v:18: Cannot find file containing module: \'sete_seg\'\n sete_seg reg3(Regs[3],HEX3);\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/140357212/Tomasulo/tomasulo.v:21: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                           : ... In instance tomasulo\n assign LEDG = Tempo[7:0];\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 7 error(s), 1 warning(s)\n'
module tomasulo(KEY,LEDR,LEDG,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7);
	input [0:0]KEY;
	output [17:0]LEDR;
	output [8:0]LEDG;
	output [6:0]HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
	wire [8:0]Regs[3:0];
	wire [2:0]label_add;
	wire [2:0]label_mult;
	wire [2:0] Add_full;
	wire [20:0] Tempo;
	wire [8:0] inst;
	controle c1(KEY[0],inst,Regs[0],Regs[1],Regs[2],Regs[3],label_add,Tempo,Add_full,Mult_full);
	sete_seg add(add_full,HEX5);
	sete_seg	mult(Mult_full,HEX4);
	sete_seg reg0(Regs[0],HEX0);
	sete_seg reg1(Regs[1],HEX1);
	sete_seg reg2(Regs[2],HEX2);
	sete_seg reg3(Regs[3],HEX3);

	assign LEDR[8:0] = inst;
	assign LEDG = Tempo[7:0];
endmodule
module tomasulo(KEY,LEDR,LEDG,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7);

	input [0:0]KEY;
	output [17:0]LEDR;
	output [8:0]LEDG;
	output [6:0]HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
	wire [8:0]Regs[3:0];
	wire [2:0]label_add;
	wire [2:0]label_mult;
	wire [2:0] Add_full;
	wire [20:0] Tempo;
	wire [8:0] inst;
	controle c1(KEY[0],inst,Regs[0],Regs[1],Regs[2],Regs[3],label_add,Tempo,Add_full,Mult_full);
	sete_seg add(add_full,HEX5);
	sete_seg	mult(Mult_full,HEX4);
	sete_seg reg0(Regs[0],HEX0);
	sete_seg reg1(Regs[1],HEX1);
	sete_seg reg2(Regs[2],HEX2);
	sete_seg reg3(Regs[3],HEX3);

	assign LEDR[8:0] = inst;
	assign LEDG = Tempo[7:0];
endmodule