data/full_repos/permissive/206842334/testbenches/ram_ren_tb.v
 line:21: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/ram_ren_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #10 enclk = ~enclk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/ram_ren_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #10 enclk = ~enclk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/ram_ren_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/206842334/testbenches/ram_ren_tb.v:45: Cannot find file containing module: \'ram\'\n    ram ram1(clk, address, datain, wen, ren, q);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/ram\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/ram.v\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/ram.sv\n             ram\n             ram.v\n             ram.sv\n             obj_dir/ram\n             obj_dir/ram.v\n             obj_dir/ram.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram_ren_tb;

    reg clk, enclk, wen, ren;
    reg [15:0] address;
    reg [7:0] datain;
    wire [7:0] q;

    task run_clock;
    begin
        #10 enclk = ~enclk;
        #10 enclk = ~enclk;
    end
    endtask

    always begin
        #10 clk = ~clk;
    end

    initial begin
        clk = 0; wen = 0; ren = 0; address = 0; enclk = 0;
        run_clock;
        address = 0; datain = 2; wen = 1;
        run_clock;
        wen = 0;
        run_clock;
        address = 1;
        datain  = 255;
        wen     = 1;
        run_clock;
        wen     = 0;
        run_clock; 
        address = 1;
        ren     = 1;
        run_clock;
        ren     = 0;
        run_clock;
        address = 0;
        ren = 1;
        run_clock;
        ren = 0;
    end



    ram ram1(clk, address, datain, wen, ren, q);

endmodule
module ram_ren_tb;


    reg clk, enclk, wen, ren;
    reg [15:0] address;
    reg [7:0] datain;
    wire [7:0] q;

    task run_clock;
    begin
        #10 enclk = ~enclk;
        #10 enclk = ~enclk;
    end
    endtask

    always begin
        #10 clk = ~clk;
    end

    initial begin
        clk = 0; wen = 0; ren = 0; address = 0; enclk = 0;
        run_clock;
        address = 0; datain = 2; wen = 1;
        run_clock;
        wen = 0;
        run_clock;
        address = 1;
        datain  = 255;
        wen     = 1;
        run_clock;
        wen     = 0;
        run_clock; 
        address = 1;
        ren     = 1;
        run_clock;
        ren     = 0;
        run_clock;
        address = 0;
        ren = 1;
        run_clock;
        ren = 0;
    end



    ram ram1(clk, address, datain, wen, ren, q);

endmodule