data/full_repos/permissive/171075078/src/sdram_master_bfm.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/171075078/src/sdram_master_bfm.sv:4: Cannot find include file: sdram_macros.svh\n`include "sdram_macros.svh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171075078/src,data/full_repos/permissive/171075078/sdram_macros.svh\n             data/full_repos/permissive/171075078/src,data/full_repos/permissive/171075078/sdram_macros.svh.v\n             data/full_repos/permissive/171075078/src,data/full_repos/permissive/171075078/sdram_macros.svh.sv\n             sdram_macros.svh\n             sdram_macros.svh.v\n             sdram_macros.svh.sv\n             obj_dir/sdram_macros.svh\n             obj_dir/sdram_macros.svh.v\n             obj_dir/sdram_macros.svh.sv\n%Error: data/full_repos/permissive/171075078/src/sdram_master_bfm.sv:206: Cannot find include file: sdram_master_bfm_api.svh\n`include "sdram_master_bfm_api.svh"  \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171075078/src/sdram_master_bfm.sv:17: Define or directive not defined: \'`SDRAM_INITIATOR_PORT\'\n `SDRAM_INITIATOR_PORT(, ADDR_WIDTH, DATA_WIDTH, BANKSEL_WIDTH)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171075078/src/sdram_master_bfm.sv:17: syntax error, unexpected \'(\', expecting \'[\'\n `SDRAM_INITIATOR_PORT(, ADDR_WIDTH, DATA_WIDTH, BANKSEL_WIDTH)\n                       ^\n%Error: Exiting due to 4 error(s)\n'
module sdram_master_bfm #(
		parameter int ADDR_WIDTH=11,
		parameter int DATA_WIDTH=16,
		parameter int BANKSEL_WIDTH=2) (
	input clock,
	input reset,
	`SDRAM_INITIATOR_PORT(, ADDR_WIDTH, DATA_WIDTH, BANKSEL_WIDTH)
		);

	sdram_master_bfm_core u_core(
		.clock(clock),
		.reset(reset)
		);
	
	assign addr = u_core.addr;
	assign bs = u_core.bs;
	assign u_core.dq_i = dq;
	assign dq = (we_n == 0)?u_core.dq_o:{DATA_WIDTH{1'bz}};
	assign cs_n = u_core.cs_n;
	assign ras_n = u_core.ras_n;
	assign cas_n = u_core.cas_n;
	assign we_n = u_core.we_n;
	assign dqm = u_core.dqm;
	assign cke = u_core.cke;
	
endmodule
module sdram_master_bfm #(
		parameter int ADDR_WIDTH=11,
		parameter int DATA_WIDTH=16,
		parameter int BANKSEL_WIDTH=2) (
	input clock,
	input reset,
	`SDRAM_INITIATOR_PORT(, ADDR_WIDTH, DATA_WIDTH, BANKSEL_WIDTH)
		);


	sdram_master_bfm_core u_core(
		.clock(clock),
		.reset(reset)
		);
	
	assign addr = u_core.addr;
	assign bs = u_core.bs;
	assign u_core.dq_i = dq;
	assign dq = (we_n == 0)?u_core.dq_o:{DATA_WIDTH{1'bz}};
	assign cs_n = u_core.cs_n;
	assign ras_n = u_core.ras_n;
	assign cas_n = u_core.cas_n;
	assign we_n = u_core.we_n;
	assign dqm = u_core.dqm;
	assign cke = u_core.cke;
	
endmodule