data/full_repos/permissive/113002755/verilog/oneshot.v
data/verilator_xmls/de1b30dd-e00f-4a06-9299-38cf5726124e.xml
module oneshot (
	iTrig,
	iClk,
	oPulse
);


input iTrig;
input iClk;


output oPulse;


reg oPulse;
reg qState;


always@(posedge iTrig or posedge oPulse)
begin
	if(oPulse)
		qState <= 0;
	else
		qState <= 1;
end

always@(posedge iClk)
begin
	oPulse <= qState;
end


endmodule
module oneshot (
	iTrig,
	iClk,
	oPulse
);



input iTrig;
input iClk;


output oPulse;


reg oPulse;
reg qState;


always@(posedge iTrig or posedge oPulse)
begin
	if(oPulse)
		qState <= 0;
	else
		qState <= 1;
end

always@(posedge iClk)
begin
	oPulse <= qState;
end


endmodule