data/full_repos/permissive/210844779/lab2/2.8.1/dlatch.v
data/verilator_xmls/a2c115b0-0ab3-4830-8ebc-c1aeafa0f482.xml
module dlatch(d,En,rst,q);
  input d,En,rst;
  output reg q;
  
  
  always @(En,rst,d)
  begin
  

  if (rst)
    q=0;
  else if (En)
     q=d;
	 
end

endmodule
module dlatch(d,En,rst,q);

  input d,En,rst;
  output reg q;
  
  
  always @(En,rst,d)
  begin
  

  if (rst)
    q=0;
  else if (En)
     q=d;
	 
end

endmodule