data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v
1: b'%Error: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:11: Unsupported or unknown PLI call: $dumpvars\n    initial $dumpvars;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:18: Unsupported or unknown PLI call: $monitor\n        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 0; d = 4\'h0; rst_n = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 1; d = 4\'h1; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 0; d = 4\'h2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 1; d = 4\'h3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 0; d = 4\'h4; rst_n = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 1; d = 4\'h5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 0; d = 4\'h6;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n        # 20;   clk = 1; d = 4\'h7; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 1; d = 4\'h8; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 0; d = 4\'h9;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 0; d = 4\'ha; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 1; d = 4\'hb; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 1; d = 4\'hc; rst_n = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 0; d = 4\'hd;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 0; d = 4\'he;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 1; d = 4\'hf;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n        # 10;   clk = 1; d = 4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_02/src/08_dff_parameterized/simulation/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n        # 20;\n        ^\n%Error: Exiting due to 2 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

    reg  clk, rst_n;
    reg  [3:0] d;
    wire [3:0] q;

    dff_async_rst_n_param #(.WIDTH(4), .RESET(4'ha)) dff_async_rst_n_param (clk, rst_n, d, q);
    
    initial $dumpvars;

    initial
    begin
        rst_n = 1;
        clk   = 1;
        
        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);

        # 20;   clk = 0; d = 4'h0; rst_n = 0;
        # 20;   clk = 1; d = 4'h1; 
        # 20;   clk = 0; d = 4'h2;
        # 20;   clk = 1; d = 4'h3;
        # 20;   clk = 0; d = 4'h4; rst_n = 1;
        # 20;   clk = 1; d = 4'h5;
        # 20;   clk = 0; d = 4'h6;
        # 20;   clk = 1; d = 4'h7; 
        # 10;   clk = 1; d = 4'h8; 
        # 10;   clk = 0; d = 4'h9;
        # 10;   clk = 0; d = 4'ha; 
        # 10;   clk = 1; d = 4'hb; 
        # 10;   clk = 1; d = 4'hc; rst_n = 0;
        # 10;   clk = 0; d = 4'hd;
        # 10;   clk = 0; d = 4'he;
        # 10;   clk = 1; d = 4'hf;
        # 10;   clk = 1; d = 4'h0;
        # 20;

        $finish;
    end

endmodule
module testbench;


    reg  clk, rst_n;
    reg  [3:0] d;
    wire [3:0] q;

    dff_async_rst_n_param #(.WIDTH(4), .RESET(4'ha)) dff_async_rst_n_param (clk, rst_n, d, q);
    
    initial $dumpvars;

    initial
    begin
        rst_n = 1;
        clk   = 1;
        
        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);

        # 20;   clk = 0; d = 4'h0; rst_n = 0;
        # 20;   clk = 1; d = 4'h1; 
        # 20;   clk = 0; d = 4'h2;
        # 20;   clk = 1; d = 4'h3;
        # 20;   clk = 0; d = 4'h4; rst_n = 1;
        # 20;   clk = 1; d = 4'h5;
        # 20;   clk = 0; d = 4'h6;
        # 20;   clk = 1; d = 4'h7; 
        # 10;   clk = 1; d = 4'h8; 
        # 10;   clk = 0; d = 4'h9;
        # 10;   clk = 0; d = 4'ha; 
        # 10;   clk = 1; d = 4'hb; 
        # 10;   clk = 1; d = 4'hc; rst_n = 0;
        # 10;   clk = 0; d = 4'hd;
        # 10;   clk = 0; d = 4'he;
        # 10;   clk = 1; d = 4'hf;
        # 10;   clk = 1; d = 4'h0;
        # 20;

        $finish;
    end

endmodule