data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v
 line:13: before: "localparam"
1: b'%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v:108: Operator ADD expects 18 bits on the RHS, but RHS\'s ARRAYSEL generates 16 bits.\n                                                                                                    : ... In instance Convolutor\n            parcial0 = parcial0 + array_prod[ptr0];\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v:115: Operator ADD expects 18 bits on the RHS, but RHS\'s ARRAYSEL generates 16 bits.\n                                                                                                    : ... In instance Convolutor\n            parcial1 = parcial1 + array_prod[4+ptr1]; \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v:119: Operator ADD expects 20 bits on the LHS, but LHS\'s VARREF \'parcial0\' generates 18 bits.\n                                                                                                    : ... In instance Convolutor\n    assign  resultado = parcial0 + parcial1 + array_prod[8];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v:119: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'parcial1\' generates 18 bits.\n                                                                                                    : ... In instance Convolutor\n    assign  resultado = parcial0 + parcial1 + array_prod[8];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v:119: Operator ADD expects 20 bits on the RHS, but RHS\'s ARRAYSEL generates 16 bits.\n                                                                                                    : ... In instance Convolutor\n    assign  resultado = parcial0 + parcial1 + array_prod[8];\n                                            ^\n%Error: Exiting due to 5 warning(s)\n'
module Convolutor #(
    parameter BIT_LEN       = `BIT_LEN,
    parameter CONV_LEN      = `CONV_LEN,
    parameter CONV_LPOS     = `CONV_LPOS,
    parameter M_LEN         = `M_LEN,
    localparam BIT_ARRAY    = BIT_LEN*M_LEN
    )(
    output [CONV_LPOS-1:0]  o_data,
    input [BIT_LEN-1:0]     i_dato0,
    input [BIT_LEN-1:0]     i_dato1,
    input [BIT_LEN-1:0]     i_dato2,
    input i_selecK_I,
    input i_reset,
    input i_valid,
    input i_CLK
    
    );


    reg signed [BIT_ARRAY-1:0]  kernel [0:M_LEN-1];    

    reg signed [BIT_ARRAY-1:0]  imagen [0:M_LEN-1];

    reg signed [CONV_LPOS-1:0]  conv_reg;

    
    reg signed [CONV_LEN-3:0]   parcial0,parcial1;

    wire signed [CONV_LEN-1:0]   resultado;
    
    reg signed [(2*BIT_LEN)-1:0] array_prod [0:(M_LEN*M_LEN)-1];

    integer ptr0 , ptr1, i;
    integer shift;


    assign {o_data[CONV_LPOS-1],o_data[CONV_LPOS-2:0]}= {~conv_reg[CONV_LPOS-1], conv_reg[CONV_LPOS-2:0]};
    always @( posedge i_CLK) begin
        if(i_reset) begin

            for(shift=0; shift < M_LEN; shift = shift +1) begin
                imagen[shift]<={BIT_ARRAY{1'b0}};
                kernel[shift]<={BIT_ARRAY{1'b0}};
            end 

            conv_reg<={CONV_LPOS{1'b0}};
        end
        else if(i_valid)begin
            case (i_selecK_I)
                1'b1: begin

                    for( shift = 0; shift < M_LEN-1; shift = shift +1)
                        imagen[shift]<=imagen[shift+1];
                    
                    imagen[M_LEN-1]<={i_dato2,i_dato1,i_dato0};

                    conv_reg<= resultado[CONV_LEN-2:CONV_LEN-CONV_LPOS-1];
                end
                1'b0: begin

                    for( shift = 0; shift < M_LEN-1; shift = shift +1)
                        kernel[shift]<=kernel[shift+1];

                    kernel[M_LEN-1]<={i_dato2,i_dato1,i_dato0};

                    conv_reg<=conv_reg;
                end
            endcase
        end
        else begin 

            for (shift =0 ; shift<M_LEN;shift=shift+1) begin: elseequ
                imagen[shift]<=imagen[shift];
                kernel[shift]<=kernel[shift];
            end

            conv_reg<=conv_reg;
        end
    end



    always@(posedge i_CLK)
        for(i = 0 ; i < (M_LEN*M_LEN) ; i=i+1) begin
            array_prod[i] =
                $signed(kernel[i/3][((i%3)+1)*BIT_LEN-1 -: BIT_LEN])*
                $signed(imagen[i/3][((i%3)+1)*BIT_LEN-1 -: BIT_LEN]);
        end
    
    always @(*) begin
        parcial0=0;
        for(ptr0 = 0 ; ptr0 < 4; ptr0 = ptr0 +1)begin
            parcial0 = parcial0 + array_prod[ptr0];
        end
    end

    always @(*) begin
        parcial1=0;
        for(ptr1 = 0 ; ptr1 < 4; ptr1 = ptr1 +1)begin
            parcial1 = parcial1 + array_prod[4+ptr1]; 
        end
    end

    assign  resultado = parcial0 + parcial1 + array_prod[8];
   
endmodule
module Convolutor #(
    parameter BIT_LEN       = `BIT_LEN,
    parameter CONV_LEN      = `CONV_LEN,
    parameter CONV_LPOS     = `CONV_LPOS,
    parameter M_LEN         = `M_LEN,
    localparam BIT_ARRAY    = BIT_LEN*M_LEN
    )(
    output [CONV_LPOS-1:0]  o_data,
    input [BIT_LEN-1:0]     i_dato0,
    input [BIT_LEN-1:0]     i_dato1,
    input [BIT_LEN-1:0]     i_dato2,
    input i_selecK_I,
    input i_reset,
    input i_valid,
    input i_CLK
    
    );



    reg signed [BIT_ARRAY-1:0]  kernel [0:M_LEN-1];    

    reg signed [BIT_ARRAY-1:0]  imagen [0:M_LEN-1];

    reg signed [CONV_LPOS-1:0]  conv_reg;

    
    reg signed [CONV_LEN-3:0]   parcial0,parcial1;

    wire signed [CONV_LEN-1:0]   resultado;
    
    reg signed [(2*BIT_LEN)-1:0] array_prod [0:(M_LEN*M_LEN)-1];

    integer ptr0 , ptr1, i;
    integer shift;


    assign {o_data[CONV_LPOS-1],o_data[CONV_LPOS-2:0]}= {~conv_reg[CONV_LPOS-1], conv_reg[CONV_LPOS-2:0]};
    always @( posedge i_CLK) begin
        if(i_reset) begin

            for(shift=0; shift < M_LEN; shift = shift +1) begin
                imagen[shift]<={BIT_ARRAY{1'b0}};
                kernel[shift]<={BIT_ARRAY{1'b0}};
            end 

            conv_reg<={CONV_LPOS{1'b0}};
        end
        else if(i_valid)begin
            case (i_selecK_I)
                1'b1: begin

                    for( shift = 0; shift < M_LEN-1; shift = shift +1)
                        imagen[shift]<=imagen[shift+1];
                    
                    imagen[M_LEN-1]<={i_dato2,i_dato1,i_dato0};

                    conv_reg<= resultado[CONV_LEN-2:CONV_LEN-CONV_LPOS-1];
                end
                1'b0: begin

                    for( shift = 0; shift < M_LEN-1; shift = shift +1)
                        kernel[shift]<=kernel[shift+1];

                    kernel[M_LEN-1]<={i_dato2,i_dato1,i_dato0};

                    conv_reg<=conv_reg;
                end
            endcase
        end
        else begin 

            for (shift =0 ; shift<M_LEN;shift=shift+1) begin: elseequ
                imagen[shift]<=imagen[shift];
                kernel[shift]<=kernel[shift];
            end

            conv_reg<=conv_reg;
        end
    end



    always@(posedge i_CLK)
        for(i = 0 ; i < (M_LEN*M_LEN) ; i=i+1) begin
            array_prod[i] =
                $signed(kernel[i/3][((i%3)+1)*BIT_LEN-1 -: BIT_LEN])*
                $signed(imagen[i/3][((i%3)+1)*BIT_LEN-1 -: BIT_LEN]);
        end
    
    always @(*) begin
        parcial0=0;
        for(ptr0 = 0 ; ptr0 < 4; ptr0 = ptr0 +1)begin
            parcial0 = parcial0 + array_prod[ptr0];
        end
    end

    always @(*) begin
        parcial1=0;
        for(ptr1 = 0 ; ptr1 < 4; ptr1 = ptr1 +1)begin
            parcial1 = parcial1 + array_prod[4+ptr1]; 
        end
    end

    assign  resultado = parcial0 + parcial1 + array_prod[8];
   
endmodule