data/full_repos/permissive/129527056/cores/tora/hdl/jttora_sound.v
1: b"%Error: data/full_repos/permissive/129527056/cores/tora/hdl/jttora_sound.v:70: Cannot find file containing module: 'jtframe_sync'\njtframe_sync #(.W(4)) syncer(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129527056/cores/tora/hdl,data/full_repos/permissive/129527056/jtframe_sync\n             data/full_repos/permissive/129527056/cores/tora/hdl,data/full_repos/permissive/129527056/jtframe_sync.v\n             data/full_repos/permissive/129527056/cores/tora/hdl,data/full_repos/permissive/129527056/jtframe_sync.sv\n             jtframe_sync\n             jtframe_sync.v\n             jtframe_sync.sv\n             obj_dir/jtframe_sync\n             obj_dir/jtframe_sync.v\n             obj_dir/jtframe_sync.sv\n%Error: data/full_repos/permissive/129527056/cores/tora/hdl/jttora_sound.v:76: Cannot find file containing module: 'jtgng_sound'\njtgng_sound #(.LAYOUT(3),.PSG_ATT(2)) u_fmcpu (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/tora/hdl/jttora_sound.v:118: Cannot find file containing module: 'jttora_adpcm'\njttora_adpcm u_adpcmcpu(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/tora/hdl/jttora_sound.v:136: Cannot find file containing module: 'jtframe_mixer'\njtframe_mixer #(.W0(16),.W1(12)) u_mixer(\n^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module jttora_sound(
    input           rst,
    input           clk,
    input           cen3,
    input           cenfm,
    input           cenp384,
    input           jap,

    input   [7:0]   snd_latch,

    input   [7:0]   snd_din,
    output  [7:0]   snd_dout,
    output          snd_mcu_wr,

    input           enable_psg,
    input           enable_fm,
    input   [ 1:0]  psg_level,

    output  [14:0]  rom_addr,
    output          rom_cs,
    input   [ 7:0]  rom_data,
    input           rom_ok,

    output  [15:0]  rom2_addr,
    output          rom2_cs,
    input   [ 7:0]  rom2_data,
    input           rom2_ok,


    output signed [15:0] ym_snd,
    output               sample,
    output  reg          peak,
    output        [ 7:0] debug_view
);

wire signed [15:0] fm_snd;
wire signed [11:0] adpcm_snd, prepcm_snd;
wire        [ 7:0] snd2_latch;
wire               fm_peak, mix_peak;



assign snd_mcu_wr = 1'b0;
assign snd_dout   = 8'd0;
assign adpcm_snd  = jap ? prepcm_snd : 12'd0;

always @(posedge clk) peak <= mix_peak | fm_peak;

wire [1:0] level;
wire       psgen_s, fmen_s;

jtframe_sync #(.W(4)) syncer(
    .clk_out( clk       ),
    .raw    ( { enable_psg, enable_fm, psg_level } ),
    .sync   ( { psgen_s, fmen_s, level }           )
);

jtgng_sound #(.LAYOUT(3),.PSG_ATT(2)) u_fmcpu (
    .rst        (  rst          ),
    .clk        (  clk          ),
    .cen3       (  cenfm        ),
    .cen1p5     (  cenfm        ),
    .sres_b     (  1'b1         ),
`ifndef F1DREAM
    .snd_latch  (  snd_latch    ),
`else
    .snd_latch  (  snd_din      ),
`endif
    .snd2_latch (  snd2_latch   ),
    .snd_int    (  1'b1         ),
    .enable_psg (  psgen_s      ),
    .enable_fm  (  fmen_s       ),
    .psg_level  (  level        ),
    .rom_addr   (  rom_addr     ),
    .rom_cs     (  rom_cs       ),
    .rom_data   (  rom_data     ),
    .rom_ok     (  rom_ok       ),
    .ym_snd     (  fm_snd       ),
    .sample     (  sample       ),
    .peak       (  fm_peak      ),
    .debug_view ( debug_view    )
);

`ifndef F1DREAM
reg [7:0] pcm_gain;

always @(posedge clk) begin
    if( !psgen_s )
        pcm_gain <= 8'h0;
    else begin
        case( level )
            2'd0: pcm_gain <= 8'h04;
            2'd1: pcm_gain <= 8'h08;
            2'd2: pcm_gain <= 8'h10;
            2'd3: pcm_gain <= 8'h20;
        endcase
    end
end

jttora_adpcm u_adpcmcpu(
    .rst        ( rst           ),
    .clk        ( clk           ),
    .cen3       ( cen3          ),
    .cenp384    ( cenp384       ),

    .snd2_latch ( snd2_latch    ),

    .rom2_addr  ( rom2_addr     ),
    .rom2_cs    ( rom2_cs       ),
    .rom2_data  ( rom2_data     ),
    .rom2_ok    ( rom2_ok       ),

    .snd        ( prepcm_snd    )
);

wire [7:0] fm_gain = jap ? 8'h08 : 8'h10;

jtframe_mixer #(.W0(16),.W1(12)) u_mixer(
    .rst    ( rst       ),
    .clk    ( clk       ),
    .cen    ( cenfm     ),

    .ch0    ( fm_snd    ),
    .ch1    ( adpcm_snd ),
    .ch2    ( 16'd0     ),
    .ch3    ( 16'd0     ),



    .gain0  ( 8'h10     ),
    .gain1  ( pcm_gain  ),
    .gain2  ( 8'h00     ),
    .gain3  ( 8'h00     ),
    .mixed  ( ym_snd    ),
    .peak   ( mix_peak  )
);
`else

assign ym_snd   = fm_snd;
assign mix_peak = 0;
`endif

endmodule
module jttora_sound(
    input           rst,
    input           clk,
    input           cen3,
    input           cenfm,
    input           cenp384,
    input           jap,

    input   [7:0]   snd_latch,

    input   [7:0]   snd_din,
    output  [7:0]   snd_dout,
    output          snd_mcu_wr,

    input           enable_psg,
    input           enable_fm,
    input   [ 1:0]  psg_level,

    output  [14:0]  rom_addr,
    output          rom_cs,
    input   [ 7:0]  rom_data,
    input           rom_ok,

    output  [15:0]  rom2_addr,
    output          rom2_cs,
    input   [ 7:0]  rom2_data,
    input           rom2_ok,


    output signed [15:0] ym_snd,
    output               sample,
    output  reg          peak,
    output        [ 7:0] debug_view
);


wire signed [15:0] fm_snd;
wire signed [11:0] adpcm_snd, prepcm_snd;
wire        [ 7:0] snd2_latch;
wire               fm_peak, mix_peak;



assign snd_mcu_wr = 1'b0;
assign snd_dout   = 8'd0;
assign adpcm_snd  = jap ? prepcm_snd : 12'd0;

always @(posedge clk) peak <= mix_peak | fm_peak;

wire [1:0] level;
wire       psgen_s, fmen_s;

jtframe_sync #(.W(4)) syncer(
    .clk_out( clk       ),
    .raw    ( { enable_psg, enable_fm, psg_level } ),
    .sync   ( { psgen_s, fmen_s, level }           )
);

jtgng_sound #(.LAYOUT(3),.PSG_ATT(2)) u_fmcpu (
    .rst        (  rst          ),
    .clk        (  clk          ),
    .cen3       (  cenfm        ),
    .cen1p5     (  cenfm        ),
    .sres_b     (  1'b1         ),
`ifndef F1DREAM
    .snd_latch  (  snd_latch    ),
`else
    .snd_latch  (  snd_din      ),
`endif
    .snd2_latch (  snd2_latch   ),
    .snd_int    (  1'b1         ),
    .enable_psg (  psgen_s      ),
    .enable_fm  (  fmen_s       ),
    .psg_level  (  level        ),
    .rom_addr   (  rom_addr     ),
    .rom_cs     (  rom_cs       ),
    .rom_data   (  rom_data     ),
    .rom_ok     (  rom_ok       ),
    .ym_snd     (  fm_snd       ),
    .sample     (  sample       ),
    .peak       (  fm_peak      ),
    .debug_view ( debug_view    )
);

`ifndef F1DREAM
reg [7:0] pcm_gain;

always @(posedge clk) begin
    if( !psgen_s )
        pcm_gain <= 8'h0;
    else begin
        case( level )
            2'd0: pcm_gain <= 8'h04;
            2'd1: pcm_gain <= 8'h08;
            2'd2: pcm_gain <= 8'h10;
            2'd3: pcm_gain <= 8'h20;
        endcase
    end
end

jttora_adpcm u_adpcmcpu(
    .rst        ( rst           ),
    .clk        ( clk           ),
    .cen3       ( cen3          ),
    .cenp384    ( cenp384       ),

    .snd2_latch ( snd2_latch    ),

    .rom2_addr  ( rom2_addr     ),
    .rom2_cs    ( rom2_cs       ),
    .rom2_data  ( rom2_data     ),
    .rom2_ok    ( rom2_ok       ),

    .snd        ( prepcm_snd    )
);

wire [7:0] fm_gain = jap ? 8'h08 : 8'h10;

jtframe_mixer #(.W0(16),.W1(12)) u_mixer(
    .rst    ( rst       ),
    .clk    ( clk       ),
    .cen    ( cenfm     ),

    .ch0    ( fm_snd    ),
    .ch1    ( adpcm_snd ),
    .ch2    ( 16'd0     ),
    .ch3    ( 16'd0     ),



    .gain0  ( 8'h10     ),
    .gain1  ( pcm_gain  ),
    .gain2  ( 8'h00     ),
    .gain3  ( 8'h00     ),
    .mixed  ( ym_snd    ),
    .peak   ( mix_peak  )
);
`else

assign ym_snd   = fm_snd;
assign mix_peak = 0;
`endif

endmodule