data/full_repos/permissive/128276399/ultra_sonic.v
None: at end of input
data/verilator_xmls/0547efd5-5d9c-4258-aa73-1cb89d5e6eff.xml
module ultra_sonic(clk,echo,trig,led);


input clk;
input echo;


output reg trig;
output reg led;


reg [31:0] dist_counter;
reg [31:0] counter;

always@(posedge clk)
    begin
        if(counter==0)
        trig<=1;
    
        if(counter==1000)
        begin
            trig<=0;
        end
            
        if(counter<32'd10000000)
        begin
            if(echo==1)
            begin
                dist_counter<=dist_counter+1;  
            end
            counter<=counter+1;
        end
        else
        begin
            counter<=0;
            dist_counter<=0;
        end
        if(echo==0)
        begin
            if(dist_counter>58800 && dist_counter<117600)
                led<=1;
            else
                led<=0;
        end 
    end
endmodule
module ultra_sonic(clk,echo,trig,led);



input clk;
input echo;


output reg trig;
output reg led;


reg [31:0] dist_counter;
reg [31:0] counter;

always@(posedge clk)
    begin
        if(counter==0)
        trig<=1;
    
        if(counter==1000)
        begin
            trig<=0;
        end
            
        if(counter<32'd10000000)
        begin
            if(echo==1)
            begin
                dist_counter<=dist_counter+1;  
            end
            counter<=counter+1;
        end
        else
        begin
            counter<=0;
            dist_counter<=0;
        end
        if(echo==0)
        begin
            if(dist_counter>58800 && dist_counter<117600)
                led<=1;
            else
                led<=0;
        end 
    end
endmodule