data/full_repos/permissive/21051978/processor/andy/alutb_slli.v
1: b'%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:25: Cannot find include file: alu.v\n`include "alu.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor/andy,data/full_repos/permissive/21051978/alu.v\n             data/full_repos/permissive/21051978/processor/andy,data/full_repos/permissive/21051978/alu.v.v\n             data/full_repos/permissive/21051978/processor/andy,data/full_repos/permissive/21051978/alu.v.sv\n             alu.v\n             alu.v.v\n             alu.v.sv\n             obj_dir/alu.v\n             obj_dir/alu.v.v\n             obj_dir/alu.v.sv\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:26: Cannot find include file: control.h\n`include "control.h" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:133: Define or directive not defined: \'`aa\'\n  c_ppp=`aa;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:133: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`aa;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:134: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:134: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:135: Define or directive not defined: \'`aluwslli\'\n  a_op=`aluwslli;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:135: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwslli;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:142: Define or directive not defined: \'`aa\'\n  c_ppp=`aa;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:142: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`aa;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:143: Define or directive not defined: \'`w8\'\n  c_ww=`w8;  \n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:143: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;  \n          ^\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:144: Define or directive not defined: \'`aluwslli\'\n  a_op=`aluwslli;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:144: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwslli;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:151: Define or directive not defined: \'`aa\'\n  c_ppp=`aa;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:151: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`aa;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:152: Define or directive not defined: \'`w16\'\n  c_ww=`w16;  \n       ^~~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:152: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w16;  \n           ^\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:153: Define or directive not defined: \'`aluwslli\'\n  a_op=`aluwslli;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:153: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwslli;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:160: Define or directive not defined: \'`aa\'\n  c_ppp=`aa;\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:160: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ppp=`aa;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:161: Define or directive not defined: \'`w32\'\n  c_ww=`w32;  \n       ^~~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:161: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w32;  \n           ^\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:162: Define or directive not defined: \'`aluwslli\'\n  a_op=`aluwslli;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:162: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwslli;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:163: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/andy/alutb_slli.v:822: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Error: Exiting due to 26 error(s), 5 warning(s)\n'
module tb_alu();


	


	wire [0:127] res;
	
	
	
	
	
	
	

	


	reg [0:127] r_A;

	reg [0:127] r_B;

	reg [0:2] c_ppp;

	reg [0:1] c_ww;

	reg [0:4] a_op;

	reg [0:127] e_r;
	
	
	
	

	


	
	

	
	

	

	alu alu1 (



		r_A,r_B,c_ppp,c_ww,a_op,res);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");	





		r_A=128'h11111111111111111111111111111111;
		r_B=128'h00000000000000000000000000000000;
		e_r=128'h11111111111111111111111111111111;
		c_ppp=`aa;
		c_ww=`w8;
		a_op=`aluwslli;
		#10;


		r_A=128'h0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f;
		r_B=128'h08000000000000000000000000000000;
		e_r=128'h1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e;
		c_ppp=`aa;
		c_ww=`w8;
		a_op=`aluwslli;
		#10;


		r_A=128'h0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f;
		r_B=128'h08000000000000000000000000000000;
		e_r=128'h1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e;
		c_ppp=`aa;
		c_ww=`w16;
		a_op=`aluwslli;
		#10;


		r_A=128'h000f000f000f000f000f000f000f000f;
		r_B=128'h08000000000000000000000000000000;
		e_r=128'h001e001e001e001e001e001e001e001e;
		c_ppp=`aa;
		c_ww=`w32;
		a_op=`aluwslli;
		#10;






		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_alu();



	


	wire [0:127] res;
	
	
	
	
	
	
	

	


	reg [0:127] r_A;

	reg [0:127] r_B;

	reg [0:2] c_ppp;

	reg [0:1] c_ww;

	reg [0:4] a_op;

	reg [0:127] e_r;
	
	
	
	

	


	
	

	
	

	

	alu alu1 (



		r_A,r_B,c_ppp,c_ww,a_op,res);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");	





		r_A=128'h11111111111111111111111111111111;
		r_B=128'h00000000000000000000000000000000;
		e_r=128'h11111111111111111111111111111111;
		c_ppp=`aa;
		c_ww=`w8;
		a_op=`aluwslli;
		#10;


		r_A=128'h0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f;
		r_B=128'h08000000000000000000000000000000;
		e_r=128'h1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e;
		c_ppp=`aa;
		c_ww=`w8;
		a_op=`aluwslli;
		#10;


		r_A=128'h0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f;
		r_B=128'h08000000000000000000000000000000;
		e_r=128'h1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e;
		c_ppp=`aa;
		c_ww=`w16;
		a_op=`aluwslli;
		#10;


		r_A=128'h000f000f000f000f000f000f000f000f;
		r_B=128'h08000000000000000000000000000000;
		e_r=128'h001e001e001e001e001e001e001e001e;
		c_ppp=`aa;
		c_ww=`w32;
		a_op=`aluwslli;
		#10;






		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule