data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/coherence_controller.sv
 line:53: before: "integer"
data/verilator_xmls/7f3f9778-e7b9-4076-a2be-466868a28754.xml
function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
endfunction
function integer log2;

      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
endfunction