data/full_repos/permissive/188434311/verilog/fifo/async_fifo/async_fifo_full.v
 line:2: before: "function"
1: b"%Error: data/full_repos/permissive/188434311/verilog/fifo/async_fifo/async_fifo_full.v:3: syntax error, unexpected wire, expecting '['\n    input wire  [ 3 : 0 ]  wr_ptr_bin,\n          ^~~~\n%Error: data/full_repos/permissive/188434311/verilog/fifo/async_fifo/async_fifo_full.v:4: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire  [ 3 : 0 ]  rd_ptr_bin\n    ^~~~~\n%Error: data/full_repos/permissive/188434311/verilog/fifo/async_fifo/async_fifo_full.v:5: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: Exiting due to 3 error(s)\n"
function aysnc_fifo_full(
    input wire  [ 3 : 0 ]  wr_ptr_bin,
    input wire  [ 3 : 0 ]  rd_ptr_bin
);



endfunction
function aysnc_fifo_full(
    input wire  [ 3 : 0 ]  wr_ptr_bin,
    input wire  [ 3 : 0 ]  rd_ptr_bin
);




endfunction