data/full_repos/permissive/123796236/reg_file.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123796236/reg_file.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100 clk <= ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123796236/reg_file.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #300 regWriteCtrl = 1;\n  ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testregfile();

wire [31:0] readData1, readData2;
reg [4:0] readRegister1, readRegister2, writeRegister;
reg [31:0] writeData;
reg clk, regWriteCtrl;

reg_file rf(readData1, readData2, readRegister1, readRegister2, writeRegister, writeData, 
regWriteCtrl, clk);
initial begin
	clk = 0;
	regWriteCtrl = 0;
	readRegister1 = 0;
	readRegister2 = 1;
	writeRegister = 5;
	writeData = 32'hffffffff;
	end

always
	begin
	#100 clk <= ~clk;
	end

always
	begin
		#300 regWriteCtrl = 1;
		readRegister1 = 5;
	end
endmodule
module testregfile();


wire [31:0] readData1, readData2;
reg [4:0] readRegister1, readRegister2, writeRegister;
reg [31:0] writeData;
reg clk, regWriteCtrl;

reg_file rf(readData1, readData2, readRegister1, readRegister2, writeRegister, writeData, 
regWriteCtrl, clk);
initial begin
	clk = 0;
	regWriteCtrl = 0;
	readRegister1 = 0;
	readRegister2 = 1;
	writeRegister = 5;
	writeData = 32'hffffffff;
	end

always
	begin
	#100 clk <= ~clk;
	end

always
	begin
		#300 regWriteCtrl = 1;
		readRegister1 = 5;
	end
endmodule