data/full_repos/permissive/125592111/verilog/branch_jump_calc.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/125592111/verilog/branch_jump_calc.v:25: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'branch_calculator\'\nmodule branch_calculator(In1_extended_imm, In2_pc_plus_4, BTA);\n       ^~~~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'jump_calculator\'\nmodule jump_calculator(In1_instruction, In2_pc_plus_4, Jump_Address);\n       ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/125592111/verilog/branch_jump_calc.v:34: Operator SHIFTL expects 28 bits on the LHS, but LHS\'s SEL generates 26 bits.\n                                                                                  : ... In instance jump_calculator\n  temp <= In1_instruction[25:0] << 2;\n                                ^~\n%Error: Exiting due to 2 warning(s)\n'
module jump_calculator(In1_instruction, In2_pc_plus_4, Jump_Address);

	input [31:0] In1_instruction;
	input [31:0] In2_pc_plus_4;
	
	output reg [31:0] Jump_Address;
	reg [27:0] temp;
	
	always @(In1_instruction) begin
		temp <= In1_instruction[25:0] << 2;
		Jump_Address <= {In2_pc_plus_4[31:28],temp};
	end
endmodule
module jump_calculator(In1_instruction, In2_pc_plus_4, Jump_Address);


	input [31:0] In1_instruction;
	input [31:0] In2_pc_plus_4;
	
	output reg [31:0] Jump_Address;
	reg [27:0] temp;
	
	always @(In1_instruction) begin
		temp <= In1_instruction[25:0] << 2;
		Jump_Address <= {In2_pc_plus_4[31:28],temp};
	end
endmodule