data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ice40/arith_map.v
 line:58 column:17: Illegal character "'"
1: b"%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ice40/arith_map.v:38: Can't resolve module reference: '$pos'\n \\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n                                                                    ^~~~~~\n%Error: Exiting due to 1 error(s)\n"
module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 1;
	parameter B_WIDTH = 1;
	parameter Y_WIDTH = 1;

	input [A_WIDTH-1:0] A;
	input [B_WIDTH-1:0] B;
	output [Y_WIDTH-1:0] X, Y;

	input CI, BI;
	output [Y_WIDTH-1:0] CO;

	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;

	wire [Y_WIDTH-1:0] A_buf, B_buf;
	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));

	wire [Y_WIDTH-1:0] AA = A_buf;
	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
	wire [Y_WIDTH-1:0] C = {CO, CI};

	genvar i;
	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
		SB_CARRY carry (
			.I0(AA[i]),
			.I1(BB[i]),
			.CI(C[i]),
			.CO(CO[i])
		);
		SB_LUT4 #(




			.LUT_INIT(16'b 0110_1001_1001_0110)
		) adder (
			.I0(1'b0),
			.I1(AA[i]),
			.I2(BB[i]),
			.I3(C[i]),
			.O(Y[i])
		);
	end endgenerate

	assign X = AA ^ BB;
endmodule
module _80_ice40_alu (A, B, CI, BI, X, Y, CO);

	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 1;
	parameter B_WIDTH = 1;
	parameter Y_WIDTH = 1;

	input [A_WIDTH-1:0] A;
	input [B_WIDTH-1:0] B;
	output [Y_WIDTH-1:0] X, Y;

	input CI, BI;
	output [Y_WIDTH-1:0] CO;

	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;

	wire [Y_WIDTH-1:0] A_buf, B_buf;
	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));

	wire [Y_WIDTH-1:0] AA = A_buf;
	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
	wire [Y_WIDTH-1:0] C = {CO, CI};

	genvar i;
	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
		SB_CARRY carry (
			.I0(AA[i]),
			.I1(BB[i]),
			.CI(C[i]),
			.CO(CO[i])
		);
		SB_LUT4 #(




			.LUT_INIT(16'b 0110_1001_1001_0110)
		) adder (
			.I0(1'b0),
			.I1(AA[i]),
			.I2(BB[i]),
			.I3(C[i]),
			.O(Y[i])
		);
	end endgenerate

	assign X = AA ^ BB;
endmodule