data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v
1: b'%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:9: Cannot find include file: verilog_macro_bus.vh\n`include "verilog_macro_bus.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.v\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.sv\n             verilog_macro_bus.vh\n             verilog_macro_bus.vh.v\n             verilog_macro_bus.vh.sv\n             obj_dir/verilog_macro_bus.vh\n             obj_dir/verilog_macro_bus.vh.v\n             obj_dir/verilog_macro_bus.vh.sv\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:15: Define or directive not defined: \'`VGA_BUS_SIZE\'\n  output wire [`VGA_BUS_SIZE-1:0] vga_out,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:20: Define or directive not defined: \'`VGA_OUT_REG\'\n    `VGA_OUT_REG\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:21: Define or directive not defined: \'`VGA_MERGE_AT_OUTPUT\'\n    `VGA_MERGE_AT_OUTPUT(vga_out)\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:21: syntax error, unexpected \'(\'\n    `VGA_MERGE_AT_OUTPUT(vga_out)\n                         ^~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:44: syntax error, unexpected <=, expecting IDENTIFIER\n                  if(vcount_out == 627) vcount_out <= 0;\n                                                   ^~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:45: syntax error, unexpected <=, expecting IDENTIFIER\n                  else vcount_out <= vcount_out + 1;\n                                  ^~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:47: syntax error, unexpected \'=\', expecting IDENTIFIER\n                  if(vcount_out > 599) vblnk_out = 1\'b1;\n                                                 ^\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:48: syntax error, unexpected <=, expecting IDENTIFIER\n                  else vblnk_out <= 1\'b0;\n                                 ^~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:50: syntax error, unexpected <=, expecting IDENTIFIER\n                  if((vcount_out >= 600) & (vcount_out <= 603)) vsync_out <= 1\'b1;\n                                                                          ^~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:51: syntax error, unexpected <=, expecting IDENTIFIER\n                  else vsync_out <= 1\'b0;\n                                 ^~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:56: syntax error, unexpected <=, expecting IDENTIFIER\n                if (hcount_out >= 800) hblnk_out <= 1\'b1;\n                                                 ^~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:57: syntax error, unexpected <=, expecting IDENTIFIER\n                else hblnk_out <= 1\'b0; \n                               ^~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:59: syntax error, unexpected <=, expecting IDENTIFIER\n                if( (hcount_out >= 840) & ( hcount_out <= 968)) hsync_out <= 1\'b1;\n                                                                          ^~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/vga_timing.v:60: syntax error, unexpected <=, expecting IDENTIFIER\n                else hsync_out <= 1\'b0;\n                               ^~\n%Error: Cannot continue\n'
module vga_timing (
  output wire [`VGA_BUS_SIZE-1:0] vga_out,
  input wire pclk,
  input wire rst
  );
  
    `VGA_OUT_REG
    `VGA_MERGE_AT_OUTPUT(vga_out)
 
 


  
  always @(posedge pclk) 

  if(!rst)
    begin
      hblnk_out <= 0;
      hcount_out <= 0;  
      vcount_out <= 0;
      vblnk_out <= 0;
      vsync_out <= 0;
      hsync_out <= 0;
    end
    else
        if (hcount_out == 1055)
            begin
                  hblnk_out <= 0;
                  hcount_out <= 0;
                
                  if(vcount_out == 627) vcount_out <= 0;
                  else vcount_out <= vcount_out + 1;
                  
                  if(vcount_out > 599) vblnk_out = 1'b1;
                  else vblnk_out <= 1'b0;
                 
                  if((vcount_out >= 600) & (vcount_out <= 603)) vsync_out <= 1'b1;
                  else vsync_out <= 1'b0;
            end
         else
            begin
                hcount_out <= hcount_out + 1;
                if (hcount_out >= 800) hblnk_out <= 1'b1;
                else hblnk_out <= 1'b0; 
                
                if( (hcount_out >= 840) & ( hcount_out <= 968)) hsync_out <= 1'b1;
                else hsync_out <= 1'b0;
            end 
        
        
        





endmodule
module vga_timing (
  output wire [`VGA_BUS_SIZE-1:0] vga_out,
  input wire pclk,
  input wire rst
  );

  
    `VGA_OUT_REG
    `VGA_MERGE_AT_OUTPUT(vga_out)
 
 


  
  always @(posedge pclk) 

  if(!rst)
    begin
      hblnk_out <= 0;
      hcount_out <= 0;  
      vcount_out <= 0;
      vblnk_out <= 0;
      vsync_out <= 0;
      hsync_out <= 0;
    end
    else
        if (hcount_out == 1055)
            begin
                  hblnk_out <= 0;
                  hcount_out <= 0;
                
                  if(vcount_out == 627) vcount_out <= 0;
                  else vcount_out <= vcount_out + 1;
                  
                  if(vcount_out > 599) vblnk_out = 1'b1;
                  else vblnk_out <= 1'b0;
                 
                  if((vcount_out >= 600) & (vcount_out <= 603)) vsync_out <= 1'b1;
                  else vsync_out <= 1'b0;
            end
         else
            begin
                hcount_out <= hcount_out + 1;
                if (hcount_out >= 800) hblnk_out <= 1'b1;
                else hblnk_out <= 1'b0; 
                
                if( (hcount_out >= 840) & ( hcount_out <= 968)) hsync_out <= 1'b1;
                else hsync_out <= 1'b0;
            end 
        
        
        





endmodule