data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb/apufClassic_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb/apufClassic_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb/apufClassic_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb/apufClassic_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n always #100 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb/apufClassic_tb.v:38: Cannot find file containing module: \'apufClassic\'\n apufClassic uut (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb,data/full_repos/permissive/128781882/apufClassic\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb,data/full_repos/permissive/128781882/apufClassic.v\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb,data/full_repos/permissive/128781882/apufClassic.sv\n             apufClassic\n             apufClassic.v\n             apufClassic.sv\n             obj_dir/apufClassic\n             obj_dir/apufClassic.v\n             obj_dir/apufClassic.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module apufClassic_tb;


	reg clk;
	reg tigSignal;
	reg vcc;
	reg [63:0] c;


	wire respReady;
	wire respBit;
	wire pathT, pathB,tigReg;


	apufClassic uut (
		.clk(clk), 
		.tigSignal(tigSignal), 
		.vcc(vcc), 
		.c(c), 
		.respReady(respReady), 
		.respBit(respBit),
		.pathT(pathT),
		.pathB(pathB),
		.tigReg(tigReg)
	);

	initial begin

		clk = 0;
		tigSignal = 0;
		vcc = 0;
		c = 0;

		#100;
		vcc = 1;
		
		#100;
		tigSignal = 0;
		
		
	end
	
	always #100 clk = ~clk;
      
endmodule
module apufClassic_tb;



	reg clk;
	reg tigSignal;
	reg vcc;
	reg [63:0] c;


	wire respReady;
	wire respBit;
	wire pathT, pathB,tigReg;


	apufClassic uut (
		.clk(clk), 
		.tigSignal(tigSignal), 
		.vcc(vcc), 
		.c(c), 
		.respReady(respReady), 
		.respBit(respBit),
		.pathT(pathT),
		.pathB(pathB),
		.tigReg(tigReg)
	);

	initial begin

		clk = 0;
		tigSignal = 0;
		vcc = 0;
		c = 0;

		#100;
		vcc = 1;
		
		#100;
		tigSignal = 0;
		
		
	end
	
	always #100 clk = ~clk;
      
endmodule