data/full_repos/permissive/169266176/ram.v
data/verilator_xmls/842324de-9989-4cae-a784-92b9cf34e25b.xml
module ram(
    input wire [7:0] address,
	 input wire ras,
	 input wire cas,
    input wire [7:0] data_in,
    output wire [7:0] data_out,
    input wire rw
    );

reg [7:0] memory[65535:0];
reg [7:0] q;
reg [15:0] ramaddress;
integer i;

always @(negedge ras)
		ramaddress[7:0]=address;

always @(negedge cas)
		begin
		ramaddress[15:8]=address;
		if (rw==0)
			memory[ramaddress]=data_in;
		else 
			q=memory[ramaddress];
		end
		
assign data_out=(!cas && rw)?q:8'hff;

initial begin
	for (i=0;i<=65535;i=i+2)
		begin
		memory[i]=8'h00;
		memory[i+1]=8'hff;
		end
	end	
endmodule
module ram(
    input wire [7:0] address,
	 input wire ras,
	 input wire cas,
    input wire [7:0] data_in,
    output wire [7:0] data_out,
    input wire rw
    );


reg [7:0] memory[65535:0];
reg [7:0] q;
reg [15:0] ramaddress;
integer i;

always @(negedge ras)
		ramaddress[7:0]=address;

always @(negedge cas)
		begin
		ramaddress[15:8]=address;
		if (rw==0)
			memory[ramaddress]=data_in;
		else 
			q=memory[ramaddress];
		end
		
assign data_out=(!cas && rw)?q:8'hff;

initial begin
	for (i=0;i<=65535;i=i+2)
		begin
		memory[i]=8'h00;
		memory[i+1]=8'hff;
		end
	end	
endmodule