data/full_repos/permissive/209997170/Sound/sound_ref/source/pwm_tb.v
1: b'%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/sound_ref/source/pwm_tb.v:18: Operator ASSIGN expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance pwm\n        ctr_d = 1\'b0;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/sound_ref/source/pwm_tb.v:33: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance pwm\n        ctr_q <= 1\'b0;\n              ^~\n%Error: Exiting due to 2 warning(s)\n'
module pwm #(parameter MAX_WAVE = 24) (
  input clk,
  input rst,
  input [MAX_WAVE-1:0] period,
  input [MAX_WAVE-1:0] compare,
  output pwm
  );

reg pwm_d, pwm_q;
reg [MAX_WAVE-1:0] ctr_d, ctr_q;

assign pwm = pwm_q;

always@(ctr_q) begin

    if (ctr_q > period) begin
        ctr_d = 1'b0;
    end else begin
        ctr_d = ctr_q + 1'b1;
    end


    if (compare > ctr_d) begin
        pwm_d = 1'b0;
    end else begin
        pwm_d = 1'b1;
    end
end

always@(posedge clk) begin
    if (rst) begin
        ctr_q <= 1'b0;
		  pwm_q <= 1'b0;
    end else begin
        ctr_q <= ctr_d;
		  pwm_q <= pwm_d;
    end
end

endmodule
module pwm #(parameter MAX_WAVE = 24) (
  input clk,
  input rst,
  input [MAX_WAVE-1:0] period,
  input [MAX_WAVE-1:0] compare,
  output pwm
  );


reg pwm_d, pwm_q;
reg [MAX_WAVE-1:0] ctr_d, ctr_q;

assign pwm = pwm_q;

always@(ctr_q) begin

    if (ctr_q > period) begin
        ctr_d = 1'b0;
    end else begin
        ctr_d = ctr_q + 1'b1;
    end


    if (compare > ctr_d) begin
        pwm_d = 1'b0;
    end else begin
        pwm_d = 1'b1;
    end
end

always@(posedge clk) begin
    if (rst) begin
        ctr_q <= 1'b0;
		  pwm_q <= 1'b0;
    end else begin
        ctr_q <= ctr_d;
		  pwm_q <= pwm_d;
    end
end

endmodule