data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v
 line:84: before: "#"
1: b'%Error: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:55: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dut.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:56: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #101 Rst = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:84: syntax error, unexpected \'@\'\n    @(posedge Clk) #1 Ld = 1; M = 4\'b0110; R = 4\'b0101;\n    ^\n%Error: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:85: syntax error, unexpected \'@\'\n    @(posedge Clk) #1 Ld = 0; M=0; R=0;\n    ^\n%Error: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:86: syntax error, unexpected \'@\'\n    @(posedge Valid);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/104443190/Booth_Multiplier/tb_Booth_Multiplier.v:96: Unsupported: Ignoring delay on this delayed statement.\nalways #5 Clk = ~Clk;\n       ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_Booth_Multiplier;

parameter N = 2;



reg     Rst;
reg     Clk;

reg     Ld;
reg     [(2**N - 1):0] M;
reg     [(2**N - 1):0] R;

wire    Valid;
wire    [(2**(N+1) - 1):0] P;



reg     [2**(N+1):0] i;



                    Booth_Multiplier #(
                        .pN(N)
                    )chen_dut(
                      .Rst_n(~Rst),
                      .Clk(Clk),
                      .En(Ld),
                      .M(M),
                      .Q(R),
                      .Valid(Valid),
                      .Product(P)

                    );

`ifdef tb_iverilog

initial
begin
    $dumpfile("dut.vcd");
    $dumpvars;
end

`endif

initial begin

    Rst = 1;
    Clk = 1;
    Ld  = 0;
    M   = 0;
    R   = 0;

    i   = 0;


    #101 Rst = 0;



    @(posedge Clk) #1 Ld = 1; M = 4'b0110; R = 4'b0101;
    @(posedge Clk) #1 Ld = 0; M=0; R=0;
    @(posedge Valid);

    @(posedge Clk);
    @(posedge Clk);

    $finish;
end



always #5 Clk = ~Clk;



endmodule
module tb_Booth_Multiplier;


parameter N = 2;



reg     Rst;
reg     Clk;

reg     Ld;
reg     [(2**N - 1):0] M;
reg     [(2**N - 1):0] R;

wire    Valid;
wire    [(2**(N+1) - 1):0] P;



reg     [2**(N+1):0] i;



                    Booth_Multiplier #(
                        .pN(N)
                    )chen_dut(
                      .Rst_n(~Rst),
                      .Clk(Clk),
                      .En(Ld),
                      .M(M),
                      .Q(R),
                      .Valid(Valid),
                      .Product(P)

                    );

`ifdef tb_iverilog

initial
begin
    $dumpfile("dut.vcd");
    $dumpvars;
end

`endif

initial begin

    Rst = 1;
    Clk = 1;
    Ld  = 0;
    M   = 0;
    R   = 0;

    i   = 0;


    #101 Rst = 0;



    @(posedge Clk) #1 Ld = 1; M = 4'b0110; R = 4'b0101;
    @(posedge Clk) #1 Ld = 0; M=0; R=0;
    @(posedge Valid);

    @(posedge Clk);
    @(posedge Clk);

    $finish;
end



always #5 Clk = ~Clk;



endmodule