data/full_repos/permissive/123043192/FPGA/USB/Loopback-FPGA/USB_Loopback.srcs/sources_1/new/UsbController.v
data/verilator_xmls/65c97bd5-9cc0-4327-940a-7f34ca3f3f79.xml
module UsbController(


    inout [7:0] USBInterfaceData,
    input RXF,
    input TXE,
    output reg RD,
    output reg WR,
    

    input clock
    );
    
    reg [7:0]counter;
    reg [7:0]waitForTime;
    
    reg [3:0]state;
    reg [3:0]nextState;
    parameter IDLE = 0, READING_START = 1, READING_WAIT_T3 = 2, READING_DATA = 3, READING_WAIT_T1 = 4, READING_WAIT_T2 = 5, READING_WAIT_T6 = 6,
    WRITE_START = 7;
    
    reg USBRXFlag;
    reg USBTXFlag;
    
    initial begin
        USBTXFlag <= 1;
        USBRXFlag <= 0;
        counter <= 0;
        waitForTime <= 0;
        RD <= 1;
        WR <= 0;
    end
        
    always @(posedge clock)begin
        state <= nextState;
    end
    


    always @(negedge RXF) begin
         USBRXFlag <= 1;
    end
    


    always @(posedge TXE) begin
        USBTXFlag = 0;
    end
    
    
    always @(posedge clock) begin

        if(state == IDLE)
        begin

            if(USBRXFlag)
            begin
                nextState = READING_START;
            end
            


            if(!USBTXFlag)
            begin
                nextState = WRITE_START;
            end
        end
    end
    
    always @(posedge clock) begin
        case(state)



            
            READING_START:
            begin

                counter = 0;
                
                USBRXFlag = 0;

                waitForTime = 5;
                nextState = READING_WAIT_T3;
            end
            
            READING_WAIT_T3:
            begin
                if(counter < waitForTime)
                    counter <= counter + 1;
                else begin
                    counter <= 0;
                    waitForTime <= 0;
                    nextState = READING_DATA;
                    end
            end
            
            READING_DATA:
            begin

                
                waitForTime <= 5;
                counter <= 0;
                
                nextState = READING_WAIT_T1;
            end
            
            READING_WAIT_T1:
            begin
                if (counter < waitForTime)
                    counter <= counter + 1;
                else begin
                    counter <= 0;
                    waitForTime <= 5;
                    nextState = READING_WAIT_T2;
                end
            end
            
            READING_WAIT_T2:
            begin
                if (counter < waitForTime)
                    counter <= counter + 1;
                else begin
                    counter <= 0;
                    waitForTime <= 8;
                    nextState = READING_WAIT_T6;
                end
            end
            
            READING_WAIT_T6:
            begin
                if (counter < waitForTime)
                    counter <= counter + 1;
                else begin
                    counter <= 0;
                    waitForTime <= 0;
                    nextState = IDLE;
                end
            end



            



            WRITE_START:
            begin
            
            end       
            



            
        endcase
    end
    
    
endmodule
module UsbController(


    inout [7:0] USBInterfaceData,
    input RXF,
    input TXE,
    output reg RD,
    output reg WR,
    

    input clock
    );

    
    reg [7:0]counter;
    reg [7:0]waitForTime;
    
    reg [3:0]state;
    reg [3:0]nextState;
    parameter IDLE = 0, READING_START = 1, READING_WAIT_T3 = 2, READING_DATA = 3, READING_WAIT_T1 = 4, READING_WAIT_T2 = 5, READING_WAIT_T6 = 6,
    WRITE_START = 7;
    
    reg USBRXFlag;
    reg USBTXFlag;
    
    initial begin
        USBTXFlag <= 1;
        USBRXFlag <= 0;
        counter <= 0;
        waitForTime <= 0;
        RD <= 1;
        WR <= 0;
    end
        
    always @(posedge clock)begin
        state <= nextState;
    end
    


    always @(negedge RXF) begin
         USBRXFlag <= 1;
    end
    


    always @(posedge TXE) begin
        USBTXFlag = 0;
    end
    
    
    always @(posedge clock) begin

        if(state == IDLE)
        begin

            if(USBRXFlag)
            begin
                nextState = READING_START;
            end
            


            if(!USBTXFlag)
            begin
                nextState = WRITE_START;
            end
        end
    end
    
    always @(posedge clock) begin
        case(state)



            
            READING_START:
            begin

                counter = 0;
                
                USBRXFlag = 0;

                waitForTime = 5;
                nextState = READING_WAIT_T3;
            end
            
            READING_WAIT_T3:
            begin
                if(counter < waitForTime)
                    counter <= counter + 1;
                else begin
                    counter <= 0;
                    waitForTime <= 0;
                    nextState = READING_DATA;
                    end
            end
            
            READING_DATA:
            begin

                
                waitForTime <= 5;
                counter <= 0;
                
                nextState = READING_WAIT_T1;
            end
            
            READING_WAIT_T1:
            begin
                if (counter < waitForTime)
                    counter <= counter + 1;
                else begin
                    counter <= 0;
                    waitForTime <= 5;
                    nextState = READING_WAIT_T2;
                end
            end
            
            READING_WAIT_T2:
            begin
                if (counter < waitForTime)
                    counter <= counter + 1;
                else begin
                    counter <= 0;
                    waitForTime <= 8;
                    nextState = READING_WAIT_T6;
                end
            end
            
            READING_WAIT_T6:
            begin
                if (counter < waitForTime)
                    counter <= counter + 1;
                else begin
                    counter <= 0;
                    waitForTime <= 0;
                    nextState = IDLE;
                end
            end



            



            WRITE_START:
            begin
            
            end       
            



            
        endcase
    end
    
    
endmodule