data/full_repos/permissive/156129873/verilog/MMU.v
1: b'%Error: data/full_repos/permissive/156129873/verilog/MMU.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:56: Define or directive not defined: \'`MEM_WRITE_OP\'\nassign ramData = (memOp_i == `MEM_WRITE_OP) ? mem_ramData_i : `HighZ;\n                             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:56: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign ramData = (memOp_i == `MEM_WRITE_OP) ? mem_ramData_i : `HighZ;\n                                          ^\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:56: Define or directive not defined: \'`HighZ\'\nassign ramData = (memOp_i == `MEM_WRITE_OP) ? mem_ramData_i : `HighZ;\n                                                              ^~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:62: Define or directive not defined: \'`Disable\'\n vga_e_o = `Disable;\n           ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n vga_e_o = `Disable;\n                   ^\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:64: Define or directive not defined: \'`ZERO\'\n vga_data_o = `ZERO;\n              ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n vga_data_o = `ZERO;\n                   ^\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:65: Define or directive not defined: \'`COM_READ\'\n serial_status_o = `COM_READ;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n serial_status_o = `COM_READ;\n                            ^\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:68: Define or directive not defined: \'`ZERO\'\n mem_data_o = `ZERO;\n              ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:68: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n mem_data_o = `ZERO;\n                   ^\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:69: Define or directive not defined: \'`ZERO\'\n comData_o = `ZERO;\n             ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:69: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n comData_o = `ZERO;\n                  ^\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:73: Define or directive not defined: \'`Enable\'\n if(pc_pause_i == `Enable) begin\n                  ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:73: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(pc_pause_i == `Enable) begin\n                         ^\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:80: Define or directive not defined: \'`MEM_READ_OP\'\n      `MEM_READ_OP: begin   \n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:81: Define or directive not defined: \'`COM_DATA_REG\'\n          if(mem_ramAddr_i == `COM_DATA_REG) begin\n                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:82: Define or directive not defined: \'`COM_READ\'\n           serial_status_o = `COM_READ;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:85: Define or directive not defined: \'`COM_SITU_REG\'\n          end else if (mem_ramAddr_i == `COM_SITU_REG) begin\n                                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:87: Define or directive not defined: \'`KEYB_DATA_REG\'\n          end else if(mem_ramAddr_i == `KEYB_DATA_REG) begin\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:90: Define or directive not defined: \'`KEYB_SITU_REG\'\n          end else if (mem_ramAddr_i == `KEYB_SITU_REG) begin\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:101: Define or directive not defined: \'`MEM_WRITE_OP\'\n      `MEM_WRITE_OP: begin    \n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:102: Define or directive not defined: \'`COM_DATA_REG\'\n         if(mem_ramAddr_i == `COM_DATA_REG) begin\n                             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:103: Define or directive not defined: \'`COM_WRITE\'\n           serial_status_o = `COM_WRITE;\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:105: Define or directive not defined: \'`VGA_SEC_MIN\'\n    end else if(mem_ramAddr_i >= `VGA_SEC_MIN && mem_ramAddr_i <= `VGA_SEC_MAX) begin\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:105: Define or directive not defined: \'`VGA_SEC_MAX\'\n    end else if(mem_ramAddr_i >= `VGA_SEC_MIN && mem_ramAddr_i <= `VGA_SEC_MAX) begin\n                                                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:106: Define or directive not defined: \'`Enable\'\n           vga_e_o = `Enable;\n                     ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:109: Define or directive not defined: \'`ROM_SEC_MIN\'\n          end else if(mem_ramAddr_i >= `ROM_SEC_MIN && mem_ramAddr_i <= `RAM_SEC_MAX) begin\n                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:109: Define or directive not defined: \'`RAM_SEC_MAX\'\n          end else if(mem_ramAddr_i >= `ROM_SEC_MIN && mem_ramAddr_i <= `RAM_SEC_MAX) begin\n                                                                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:117: Define or directive not defined: \'`ROM_SEC_MIN\'\n          if(pc_i >= `ROM_SEC_MIN && pc_i <= `ROM_SEC_MAX) begin\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:117: Define or directive not defined: \'`ROM_SEC_MAX\'\n          if(pc_i >= `ROM_SEC_MIN && pc_i <= `ROM_SEC_MAX) begin\n                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:120: Define or directive not defined: \'`RAM_SEC_MIN\'\n       end else if(pc_i >= `RAM_SEC_MIN && pc_i <= `RAM_SEC_MAX) begin\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/MMU.v:120: Define or directive not defined: \'`RAM_SEC_MAX\'\n       end else if(pc_i >= `RAM_SEC_MIN && pc_i <= `RAM_SEC_MAX) begin\n                                                   ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module MMU (


    input wire[1:0] memOp_i,
    input wire[15:0] mem_ramData_i,
    input wire[15:0] mem_ramAddr_i,


    input wire[15:0] pc_i,


    input wire[15:0] rom_ins_i,


    input wire[7:0] comData_i,
    input wire writeable, readable,


	input wire keybStatus_i,
	input wire[6:0] keybKey_i,
	 

	input wire pc_pause_i,


    output reg[15:0] ins_o,


    output reg[15:0] mem_data_o,


    inout wire[15:0] ramData,
    output reg[17:0] ramAddr,
    output reg ramOE,
    output reg ramWE,
    output reg ramEN,


    output reg[15:0] pc_o,


	 output reg serial_status_o,
	 output reg serial_enable_o,
    output reg serial_fetch_o,
    output reg[7:0] comData_o,


    output reg vga_e_o,
    output reg[8:0] vga_addr_o,
    output reg[15:0] vga_data_o
);


assign ramData = (memOp_i == `MEM_WRITE_OP) ? mem_ramData_i : `HighZ;


always @(*) begin
	pc_o = 16'b0;

	vga_e_o = `Disable;
	vga_addr_o = 9'b0;
	vga_data_o = `ZERO;
	serial_status_o = `COM_READ;
	serial_enable_o = 1'b1;
	serial_fetch_o = 1'b0;
	mem_data_o = `ZERO;
	comData_o = `ZERO;
	ramEN = 1;
	ramOE = 1;
	ramWE = 1;
	if(pc_pause_i == `Enable) begin
		ins_o = ins_o;
	end else begin
		ins_o = 16'b0000100000000000;
	end
	
    case (memOp_i)
      `MEM_READ_OP: begin
          if(mem_ramAddr_i == `COM_DATA_REG) begin
          	serial_status_o = `COM_READ;
            serial_fetch_o = 1'b1;
          	mem_data_o = {8'b0, comData_i};
          end else if (mem_ramAddr_i == `COM_SITU_REG) begin
            mem_data_o = {14'b0, readable, writeable};
          end else if(mem_ramAddr_i == `KEYB_DATA_REG) begin

			 mem_data_o = {8'b0, keybKey_i};
          end else if (mem_ramAddr_i == `KEYB_SITU_REG) begin
		  	 mem_data_o = {15'b0, keybStatus_i};
		  end
      	  else begin
          	ramEN = 0;
          	ramOE = 0;
          	ramWE = 1;
          	ramAddr = {2'b00, mem_ramAddr_i};
          	mem_data_o = ramData;
          end
      end
      `MEM_WRITE_OP: begin
      	  if(mem_ramAddr_i == `COM_DATA_REG) begin
          	serial_status_o = `COM_WRITE;
          	comData_o = mem_ramData_i[7:0];
		  end else if(mem_ramAddr_i >= `VGA_SEC_MIN && mem_ramAddr_i <= `VGA_SEC_MAX) begin
          	vga_e_o = `Enable;
          	vga_data_o = mem_ramData_i;
          	vga_addr_o = mem_ramAddr_i[8:0];
          end else if(mem_ramAddr_i >= `ROM_SEC_MIN && mem_ramAddr_i <= `RAM_SEC_MAX) begin
      	  	ramAddr = {2'b00, mem_ramAddr_i};
          	ramEN = 0;
          	ramOE = 1;
          	ramWE = 0;
          end
      end
      default: begin
          if(pc_i >= `ROM_SEC_MIN && pc_i <= `ROM_SEC_MAX) begin
				pc_o = pc_i;
				ins_o = rom_ins_i;
    	  end else if(pc_i >= `RAM_SEC_MIN && pc_i <= `RAM_SEC_MAX) begin
				ramEN = 0;
          		ramOE = 0;
          		ramWE = 1;
				ramAddr = {2'b00, pc_i};
				ins_o = ramData;
    	  end
	  end
    endcase
end

endmodule
module MMU (


    input wire[1:0] memOp_i,
    input wire[15:0] mem_ramData_i,
    input wire[15:0] mem_ramAddr_i,


    input wire[15:0] pc_i,


    input wire[15:0] rom_ins_i,


    input wire[7:0] comData_i,
    input wire writeable, readable,


	input wire keybStatus_i,
	input wire[6:0] keybKey_i,
	 

	input wire pc_pause_i,


    output reg[15:0] ins_o,


    output reg[15:0] mem_data_o,


    inout wire[15:0] ramData,
    output reg[17:0] ramAddr,
    output reg ramOE,
    output reg ramWE,
    output reg ramEN,


    output reg[15:0] pc_o,


	 output reg serial_status_o,
	 output reg serial_enable_o,
    output reg serial_fetch_o,
    output reg[7:0] comData_o,


    output reg vga_e_o,
    output reg[8:0] vga_addr_o,
    output reg[15:0] vga_data_o
);



assign ramData = (memOp_i == `MEM_WRITE_OP) ? mem_ramData_i : `HighZ;


always @(*) begin
	pc_o = 16'b0;

	vga_e_o = `Disable;
	vga_addr_o = 9'b0;
	vga_data_o = `ZERO;
	serial_status_o = `COM_READ;
	serial_enable_o = 1'b1;
	serial_fetch_o = 1'b0;
	mem_data_o = `ZERO;
	comData_o = `ZERO;
	ramEN = 1;
	ramOE = 1;
	ramWE = 1;
	if(pc_pause_i == `Enable) begin
		ins_o = ins_o;
	end else begin
		ins_o = 16'b0000100000000000;
	end
	
    case (memOp_i)
      `MEM_READ_OP: begin
          if(mem_ramAddr_i == `COM_DATA_REG) begin
          	serial_status_o = `COM_READ;
            serial_fetch_o = 1'b1;
          	mem_data_o = {8'b0, comData_i};
          end else if (mem_ramAddr_i == `COM_SITU_REG) begin
            mem_data_o = {14'b0, readable, writeable};
          end else if(mem_ramAddr_i == `KEYB_DATA_REG) begin

			 mem_data_o = {8'b0, keybKey_i};
          end else if (mem_ramAddr_i == `KEYB_SITU_REG) begin
		  	 mem_data_o = {15'b0, keybStatus_i};
		  end
      	  else begin
          	ramEN = 0;
          	ramOE = 0;
          	ramWE = 1;
          	ramAddr = {2'b00, mem_ramAddr_i};
          	mem_data_o = ramData;
          end
      end
      `MEM_WRITE_OP: begin
      	  if(mem_ramAddr_i == `COM_DATA_REG) begin
          	serial_status_o = `COM_WRITE;
          	comData_o = mem_ramData_i[7:0];
		  end else if(mem_ramAddr_i >= `VGA_SEC_MIN && mem_ramAddr_i <= `VGA_SEC_MAX) begin
          	vga_e_o = `Enable;
          	vga_data_o = mem_ramData_i;
          	vga_addr_o = mem_ramAddr_i[8:0];
          end else if(mem_ramAddr_i >= `ROM_SEC_MIN && mem_ramAddr_i <= `RAM_SEC_MAX) begin
      	  	ramAddr = {2'b00, mem_ramAddr_i};
          	ramEN = 0;
          	ramOE = 1;
          	ramWE = 0;
          end
      end
      default: begin
          if(pc_i >= `ROM_SEC_MIN && pc_i <= `ROM_SEC_MAX) begin
				pc_o = pc_i;
				ins_o = rom_ins_i;
    	  end else if(pc_i >= `RAM_SEC_MIN && pc_i <= `RAM_SEC_MAX) begin
				ramEN = 0;
          		ramOE = 0;
          		ramWE = 1;
				ramAddr = {2'b00, pc_i};
				ins_o = ramData;
    	  end
	  end
    endcase
end

endmodule