data/full_repos/permissive/206261917/src/clkgate.v
None: at end of input
data/verilator_xmls/5de9c96c-ac4d-459b-905d-c9557e2147b1.xml
module clkgate (
  input   clk_in,
  input   clock_en,
  output  clk_out
);

reg en;

always@(*)
  if (!clk_in)
    en = clock_en ;

assign clk_out = en & clk_in;

endmodule
module clkgate (
  input   clk_in,
  input   clock_en,
  output  clk_out
);


reg en;

always@(*)
  if (!clk_in)
    en = clock_en ;

assign clk_out = en & clk_in;

endmodule