data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v
 line:51: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:38: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD/2) \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:51: Unsupported: Ignoring delay on this delayed statement.\n        repeat (9) #CLK_PERIOD\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #CLK_PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*9);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:70: Unsupported: Ignoring delay on this delayed statement.\n        repeat (3) #CLK_PERIOD\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:75: Unsupported: Ignoring delay on this delayed statement.\n        repeat (6) #CLK_PERIOD\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*4);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:89: Unsupported: Ignoring delay on this delayed statement.\n        repeat (9) #CLK_PERIOD\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #CLK_PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*4);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*2);\n        ^\n%Error: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_FIFO.v:25: Cannot find file containing module: \'FIFO\'\n    FIFO #(8, 8) utt(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/14_memory/testbenches,data/full_repos/permissive/212763527/FIFO\n             data/full_repos/permissive/212763527/school_project/14_memory/testbenches,data/full_repos/permissive/212763527/FIFO.v\n             data/full_repos/permissive/212763527/school_project/14_memory/testbenches,data/full_repos/permissive/212763527/FIFO.sv\n             FIFO\n             FIFO.v\n             FIFO.sv\n             obj_dir/FIFO\n             obj_dir/FIFO.v\n             obj_dir/FIFO.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_FIFO;

    reg clk;



    reg [7:0] data_in;
    reg wr_en;
    reg rd_en;
    reg rst;


    wire [7:0] data_out;
    wire empty;
    wire full;



    initial begin
        clk = 0;
    end
    
    FIFO #(8, 8) utt(
        data_in,
        wr_en,
        rd_en,
        clk,
        rst,
        data_out,
        empty,
        full

    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin

        rst = 1'b1;
        #(CLK_PERIOD*2);


        rst = 1'b0;
        wr_en = 1'b1;
        data_in = 8'h0_1;

        repeat (9) #CLK_PERIOD
            data_in = data_in + 1;

        #CLK_PERIOD;

        wr_en = 1'b0;
        rd_en = 1'b1;

        #(CLK_PERIOD*9);


        rst = 1'b1;
        #(CLK_PERIOD*2);
        rst = 1'b0;
        
        wr_en = 1'b1;
        rd_en = 1'b0;

        data_in = 8'h0_1;
        repeat (3) #CLK_PERIOD
            data_in = data_in + 1;
        
        rd_en = 1'b1;

        repeat (6) #CLK_PERIOD
            data_in = data_in + 1;
        
        wr_en = 1'b0;

        #(CLK_PERIOD*4);



        rst = 1'b0;
        wr_en = 1'b1;
        rd_en = 1'b0;
        data_in = 8'h0_1;

        repeat (9) #CLK_PERIOD
            data_in = data_in + 1;

        #CLK_PERIOD;

        wr_en = 1'b0;
        rd_en = 1'b1;

        #(CLK_PERIOD*4);

        rst = 1'b1;
        #(CLK_PERIOD*2);

        rst = 1'b0;
        #(CLK_PERIOD*2);


        $finish;
    end

endmodule
module tb_FIFO;


    reg clk;



    reg [7:0] data_in;
    reg wr_en;
    reg rd_en;
    reg rst;


    wire [7:0] data_out;
    wire empty;
    wire full;



    initial begin
        clk = 0;
    end
    
    FIFO #(8, 8) utt(
        data_in,
        wr_en,
        rd_en,
        clk,
        rst,
        data_out,
        empty,
        full

    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin

        rst = 1'b1;
        #(CLK_PERIOD*2);


        rst = 1'b0;
        wr_en = 1'b1;
        data_in = 8'h0_1;

        repeat (9) #CLK_PERIOD
            data_in = data_in + 1;

        #CLK_PERIOD;

        wr_en = 1'b0;
        rd_en = 1'b1;

        #(CLK_PERIOD*9);


        rst = 1'b1;
        #(CLK_PERIOD*2);
        rst = 1'b0;
        
        wr_en = 1'b1;
        rd_en = 1'b0;

        data_in = 8'h0_1;
        repeat (3) #CLK_PERIOD
            data_in = data_in + 1;
        
        rd_en = 1'b1;

        repeat (6) #CLK_PERIOD
            data_in = data_in + 1;
        
        wr_en = 1'b0;

        #(CLK_PERIOD*4);



        rst = 1'b0;
        wr_en = 1'b1;
        rd_en = 1'b0;
        data_in = 8'h0_1;

        repeat (9) #CLK_PERIOD
            data_in = data_in + 1;

        #CLK_PERIOD;

        wr_en = 1'b0;
        rd_en = 1'b1;

        #(CLK_PERIOD*4);

        rst = 1'b1;
        #(CLK_PERIOD*2);

        rst = 1'b0;
        #(CLK_PERIOD*2);


        $finish;
    end

endmodule