data/full_repos/permissive/210844779/lab3/3.3/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab3/3.3/tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab3/3.3/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab3/3.3/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab3/3.3/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab3/3.3/tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab3/3.3/tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab3/3.3/tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #60\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab3/3.3/tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #60;\n  ^\n%Error: data/full_repos/permissive/210844779/lab3/3.3/tb.v:7: Cannot find file containing module: \'uni_shift\'\n  uni_shift u0(d,clk,load,shift_en,sel,q);\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab3/3.3,data/full_repos/permissive/210844779/uni_shift\n             data/full_repos/permissive/210844779/lab3/3.3,data/full_repos/permissive/210844779/uni_shift.v\n             data/full_repos/permissive/210844779/lab3/3.3,data/full_repos/permissive/210844779/uni_shift.sv\n             uni_shift\n             uni_shift.v\n             uni_shift.sv\n             obj_dir/uni_shift\n             obj_dir/uni_shift.v\n             obj_dir/uni_shift.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab3/3.3/tb.v:27: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                     : ... In instance tb\n  shift_en=2\'b01;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab3/3.3/tb.v:32: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                     : ... In instance tb\n  load=2\'b10;\n      ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  reg [15:0]d;
  reg [1:0]sel;
  reg clk,load,shift_en;
  wire [15:0]q;
  
  uni_shift u0(d,clk,load,shift_en,sel,q);
  
  always
  begin
    clk=1'b0;
    #5
    clk=1'b1;
    #5;
  end
  
  always
  begin
    
  load=1'b1;
  shift_en=1'b0;
  sel=2'b00;
  d=16'b1010011011100101;
  #20
  
  load=1'b0;
  shift_en=2'b01;
  sel=2'b00;
  d=16'b1010011011100101;
  #50
  
  load=2'b10;
  shift_en=1'b1;
  sel=2'b01;
  d=16'b1010011011100101;
  #50
  
  load=1'b1;
  shift_en=1'b0;
  sel=2'b00;
  d=16'b1110011010110110;
  #20
  
  load=1'b0;
  shift_en=1'b1;
  sel=2'b10;
  d=16'b1010011011100100;
  #60
  
  load=1'b0;
  shift_en=1'b1;
  sel=2'b11;
  d=16'b1010011011100100;
  #60;
  
end

endmodule
module tb();

  reg [15:0]d;
  reg [1:0]sel;
  reg clk,load,shift_en;
  wire [15:0]q;
  
  uni_shift u0(d,clk,load,shift_en,sel,q);
  
  always
  begin
    clk=1'b0;
    #5
    clk=1'b1;
    #5;
  end
  
  always
  begin
    
  load=1'b1;
  shift_en=1'b0;
  sel=2'b00;
  d=16'b1010011011100101;
  #20
  
  load=1'b0;
  shift_en=2'b01;
  sel=2'b00;
  d=16'b1010011011100101;
  #50
  
  load=2'b10;
  shift_en=1'b1;
  sel=2'b01;
  d=16'b1010011011100101;
  #50
  
  load=1'b1;
  shift_en=1'b0;
  sel=2'b00;
  d=16'b1110011010110110;
  #20
  
  load=1'b0;
  shift_en=1'b1;
  sel=2'b10;
  d=16'b1010011011100100;
  #60
  
  load=1'b0;
  shift_en=1'b1;
  sel=2'b11;
  d=16'b1010011011100100;
  #60;
  
end

endmodule