data/full_repos/permissive/143278/ivltests/nb_ec_pv.v
 line:15: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:10: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:11: Unsupported: Ignoring delay on this delayed statement.\n  always #20 in = in + 4\'h1;\n         ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:15: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n    result[3:0] <= repeat(count) @(posedge clk) in;\n                   ^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:16: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 0 || result !== 8\'bx) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:18: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:21: syntax error, unexpected \'@\'\n    @(result);\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:22: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 50 || result !== 8\'hx0) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:24: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #15;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:30: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n    result[7:4] <= repeat(count) @(posedge clk) in;\n                   ^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:32: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 65 || result !== 8\'h30) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:34: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:40: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n    result[8:5] <= repeat(count) @(posedge clk) in;\n                   ^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:42: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 85 || result !== 8\'h90) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:44: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:49: syntax error, unexpected \'@\', expecting TYPE-IDENTIFIER\n    result[7:4] <= @(posedge clk) 4\'h0;\n                   ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:50: syntax error, unexpected \'@\', expecting TYPE-IDENTIFIER\n    result[7:4] <= @(posedge clk) in;  \n                   ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:52: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 110 || result !== 8\'h50) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:54: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:59: syntax error, unexpected \'@\', expecting TYPE-IDENTIFIER\n    result[3:0] <= @(posedge clk) 4\'h1;\n                   ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:60: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n    result[7:4] <= repeat(icount) @(posedge clk) 4\'h2;\n                   ^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:61: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n    result[1:-2] <= repeat(3) @(posedge clk) 4\'h3;\n                    ^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:63: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 130 || result !== 8\'h51) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:65: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:68: syntax error, unexpected \'@\'\n    @(result);\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:69: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 150 || result !== 8\'h21) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:71: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:74: syntax error, unexpected \'@\'\n    @(result);\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:75: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 170 || result !== 8\'h20) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_pv.v:77: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: Exiting due to 27 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass = 1'b1;

  integer count;
  reg [2:0] icount;
  reg clk = 0;
  reg [3:0] in = 4'h0;
  reg [7:0] result;

  always #10 clk = ~clk;
  always #20 in = in + 4'h1;

  initial begin
    count = 3;
    result[3:0] <= repeat(count) @(posedge clk) in;
    if ($simtime != 0 || result !== 8'bx) begin
      $display("Failed repeat(3) blocked at %0t, expected 8'hxx, got %h",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 50 || result !== 8'hx0) begin
      $display("Failed repeat(3) at %0t, expected 8'hx0, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    #15;
    count = 0;
    result[7:4] <= repeat(count) @(posedge clk) in;
    @(result);
    if ($simtime != 65 || result !== 8'h30) begin
      $display("Failed repeat(0) at %0t, expected 8'h30, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    #20;
    count = -1;
    result[8:5] <= repeat(count) @(posedge clk) in;
    @(result);
    if ($simtime != 85 || result !== 8'h90) begin
      $display("Failed repeat(-1) at %0t, expected 8'h80, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    #20;
    result[7:4] <= @(posedge clk) 4'h0;
    result[7:4] <= @(posedge clk) in;
    @(result);
    if ($simtime != 110 || result !== 8'h50) begin
      $display("Failed @ at %0t, expected 8'h50, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    icount = 3'd2;
    result[3:0] <= @(posedge clk) 4'h1;
    result[7:4] <= repeat(icount) @(posedge clk) 4'h2;
    result[1:-2] <= repeat(3) @(posedge clk) 4'h3;
    @(result);
    if ($simtime != 130 || result !== 8'h51) begin
      $display("Failed first @ at %0t, expected 8'h51, got %h",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 150 || result !== 8'h21) begin
      $display("Failed second @ at %0t, expected 8'h21, got %h",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 170 || result !== 8'h20) begin
      $display("Failed third @ at %0t, expected 8'h20, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
    $finish;
  end
endmodule
module top;

  reg pass = 1'b1;

  integer count;
  reg [2:0] icount;
  reg clk = 0;
  reg [3:0] in = 4'h0;
  reg [7:0] result;

  always #10 clk = ~clk;
  always #20 in = in + 4'h1;

  initial begin
    count = 3;
    result[3:0] <= repeat(count) @(posedge clk) in;
    if ($simtime != 0 || result !== 8'bx) begin
      $display("Failed repeat(3) blocked at %0t, expected 8'hxx, got %h",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 50 || result !== 8'hx0) begin
      $display("Failed repeat(3) at %0t, expected 8'hx0, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    #15;
    count = 0;
    result[7:4] <= repeat(count) @(posedge clk) in;
    @(result);
    if ($simtime != 65 || result !== 8'h30) begin
      $display("Failed repeat(0) at %0t, expected 8'h30, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    #20;
    count = -1;
    result[8:5] <= repeat(count) @(posedge clk) in;
    @(result);
    if ($simtime != 85 || result !== 8'h90) begin
      $display("Failed repeat(-1) at %0t, expected 8'h80, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    #20;
    result[7:4] <= @(posedge clk) 4'h0;
    result[7:4] <= @(posedge clk) in;
    @(result);
    if ($simtime != 110 || result !== 8'h50) begin
      $display("Failed @ at %0t, expected 8'h50, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    icount = 3'd2;
    result[3:0] <= @(posedge clk) 4'h1;
    result[7:4] <= repeat(icount) @(posedge clk) 4'h2;
    result[1:-2] <= repeat(3) @(posedge clk) 4'h3;
    @(result);
    if ($simtime != 130 || result !== 8'h51) begin
      $display("Failed first @ at %0t, expected 8'h51, got %h",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 150 || result !== 8'h21) begin
      $display("Failed second @ at %0t, expected 8'h21, got %h",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 170 || result !== 8'h20) begin
      $display("Failed third @ at %0t, expected 8'h20, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
    $finish;
  end
endmodule