data/full_repos/permissive/159596577/src/shifter.v
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data/verilator_xmls/75601a05-aa94-4b82-9e25-2dd017ea53b1.xml
module shifter(
    d,
    sa,
    right,
    arith,
    sh
);
    input [31:0]d;
    input [4:0]sa;
    input right,arith;
    output [31:0]sh;
    reg [31:0] sh;
    always @(*) begin
        if(!right)begin
            sh = d << sa;
        end else if (!arith) begin
            sh = d >> sa;
        end else begin
            sh = $signed(d)>>>sa;
        end
    end
endmodule
module shifter(
    d,
    sa,
    right,
    arith,
    sh
);

    input [31:0]d;
    input [4:0]sa;
    input right,arith;
    output [31:0]sh;
    reg [31:0] sh;
    always @(*) begin
        if(!right)begin
            sh = d << sa;
        end else if (!arith) begin
            sh = d >> sa;
        end else begin
            sh = $signed(d)>>>sa;
        end
    end
endmodule