data/full_repos/permissive/159166357/tests/counter.v
1: b"%Error: data/full_repos/permissive/159166357/tests/counter.v:23: Can't find definition of variable: 'mtime'\n                                                               : ... Suggested alternative: 'mtimel'\n        mtime <= mtime + 32'b1;\n                 ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module counter_top
  (
      input wire clk,
      input wire resetb,
      output reg led
  );
  (*keep*)
  reg we;
  (*keep*)
  wire cmp;
  (*keep*)
  wire [31:0] mtimel, mtimeh;
  (*keep*)
  wire [63:0] mtimecmp;
  counter C0(.clk(clk),.resetb(resetb),
      .wenl(we),.wenh(1'b0),.sel(1'b1),.din(32'h1000),.cmp(cmp),
      .mtimel(mtimel),.mtimeh(mtimeh),.mtimecmp(mtimecmp)
  );

  reg cmp_written;
  always @ (posedge clk) begin
      if (!resetb) begin
          led <= 1'b0;
          cmp_written <= 1'b0;
          we <= 1'b0;
      end
      else if (clk) begin
          cmp_written <= 1'b1;
          we <= !cmp_written;
          led <= cmp ? ~led : led;
      end
  end
  endmodule
module counter_top
  (
      input wire clk,
      input wire resetb,
      output reg led
  );

  (*keep*)
  reg we;
  (*keep*)
  wire cmp;
  (*keep*)
  wire [31:0] mtimel, mtimeh;
  (*keep*)
  wire [63:0] mtimecmp;
  counter C0(.clk(clk),.resetb(resetb),
      .wenl(we),.wenh(1'b0),.sel(1'b1),.din(32'h1000),.cmp(cmp),
      .mtimel(mtimel),.mtimeh(mtimeh),.mtimecmp(mtimecmp)
  );

  reg cmp_written;
  always @ (posedge clk) begin
      if (!resetb) begin
          led <= 1'b0;
          cmp_written <= 1'b0;
          we <= 1'b0;
      end
      else if (clk) begin
          cmp_written <= 1'b1;
          we <= !cmp_written;
          led <= cmp ? ~led : led;
      end
  end
  endmodule