data/full_repos/permissive/201488448/2_circuits/2_sequential/fsm/07_fsm3.v
data/verilator_xmls/9c3e981e-8567-42eb-b705-6f2d24084457.xml
module top_module(
    input clk,
    input in,
    input areset,
    output out);

    parameter A=2'd0, B=2'd1, C=2'd2, D=2'd3;
    reg [1:0]	state, next_state;

    always@(*) begin
        case({state, in})
            {A, 1'b0}:	next_state = A;
            {A, 1'b1}:	next_state = B;
            {B, 1'b0}:	next_state = C;
            {B, 1'b1}:	next_state = B;
            {C, 1'b0}:	next_state = A;
            {C, 1'b1}:	next_state = D;
            {D, 1'b0}:	next_state = C;
            {D, 1'b1}:	next_state = B;
        endcase
    end

    always@(posedge clk, posedge areset) begin
        if(areset)
            state <= A;
        else
            state <= next_state;
    end

    assign out = (state == D);
endmodule
module top_module(
    input clk,
    input in,
    input areset,
    output out);


    parameter A=2'd0, B=2'd1, C=2'd2, D=2'd3;
    reg [1:0]	state, next_state;

    always@(*) begin
        case({state, in})
            {A, 1'b0}:	next_state = A;
            {A, 1'b1}:	next_state = B;
            {B, 1'b0}:	next_state = C;
            {B, 1'b1}:	next_state = B;
            {C, 1'b0}:	next_state = A;
            {C, 1'b1}:	next_state = D;
            {D, 1'b0}:	next_state = C;
            {D, 1'b1}:	next_state = B;
        endcase
    end

    always@(posedge clk, posedge areset) begin
        if(areset)
            state <= A;
        else
            state <= next_state;
    end

    assign out = (state == D);
endmodule