data/full_repos/permissive/116563702/fsm/counter/mod3counter.v
 line:14: before: "reset"
data/verilator_xmls/57091ecf-cb0c-4099-8cf9-6aa8bc74a82f.xml
module mod3counter( input clk,
		    input  reset,
		    output y);

   reg [1:0] 		   state, nextstate;

   parameter S0 = 2'b00;
   parameter S1 = 2'b01;
   parameter S2 = 2'b01;
   

   always @(posedge clk, reset)
     begin
	if (reset)
	  state <= 2'b00;
	else
	  state <= nextstate;
     end


   always @(*)
     begin
	case (state)
	  S0 : nextstate = S1;
	  S1 : nextstate = S2;
	  S2 : nextstate = S0;
	  default : nextstate = S0;
	endcase
     end

   assign y = (state == S0);
   
endmodule
module mod3counter( input clk,
		    input  reset,
		    output y);


   reg [1:0] 		   state, nextstate;

   parameter S0 = 2'b00;
   parameter S1 = 2'b01;
   parameter S2 = 2'b01;
   

   always @(posedge clk, reset)
     begin
	if (reset)
	  state <= 2'b00;
	else
	  state <= nextstate;
     end


   always @(*)
     begin
	case (state)
	  S0 : nextstate = S1;
	  S1 : nextstate = S2;
	  S2 : nextstate = S0;
	  default : nextstate = S0;
	endcase
     end

   assign y = (state == S0);
   
endmodule