data/full_repos/permissive/211878730/atlys/practice/mux.v
data/verilator_xmls/c50fd3bb-0cd0-4128-a825-bc6059b093d0.xml
module mux(
	input  wire [2:0] d0,
	input  wire [2:0] d1,
	input  wire sel,
	output reg [2:0] y
    );

	always @(*) begin

		if (sel) begin
			y = d0;
		end else begin
			y = d1;
		end
	end
endmodule
module mux(
	input  wire [2:0] d0,
	input  wire [2:0] d1,
	input  wire sel,
	output reg [2:0] y
    );


	always @(*) begin

		if (sel) begin
			y = d0;
		end else begin
			y = d1;
		end
	end
endmodule