data/full_repos/permissive/192241640/uart_transmitter.v
1: b"%Error: data/full_repos/permissive/192241640/uart_transmitter.v:23: syntax error, unexpected break, expecting '['\n input break,    \n       ^~~~~\n%Error: data/full_repos/permissive/192241640/uart_transmitter.v:30: syntax error, unexpected assign\n assign empty = (counter == 8'd0);\n ^~~~~~\n%Error: data/full_repos/permissive/192241640/uart_transmitter.v:40: syntax error, unexpected always\n always @(posedge txclk) begin\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module uart_tx (

	input txclk,
	input reset,

	input we,
	input [8:0] din,
	input parity,

	input break,
	output sout,
	output empty
);


	reg [7:0] counter = 8'd0;
	assign empty = (counter == 8'd0);
	always @(posedge txclk) begin
		if (reset) counter <= 8'd0;
		else if (we) counter <= parity ? 8'hAF : 8'h9F;
		else if (!empty) counter <= counter - 1'd1;
	end


	reg [9:0] sout_buf = 10'h3ff;
	wire sout_shift = (counter[3:0] == 4'd0);
	always @(posedge txclk) begin
		if (reset) sout_buf <= 10'h3ff;
		else if (we) sout_buf <= parity ? {din, 1'b0} : {1'b1, din[7:0], 1'b0};
		else if (sout_shift) sout_buf <= {1'b1, sout_buf[9:1]};
	end
	assign sout = break ? 1'b0 : sout_buf[0];

endmodule
module uart_tx (

	input txclk,
	input reset,

	input we,
	input [8:0] din,
	input parity,

	input break,
	output sout,
	output empty
);



	reg [7:0] counter = 8'd0;
	assign empty = (counter == 8'd0);
	always @(posedge txclk) begin
		if (reset) counter <= 8'd0;
		else if (we) counter <= parity ? 8'hAF : 8'h9F;
		else if (!empty) counter <= counter - 1'd1;
	end


	reg [9:0] sout_buf = 10'h3ff;
	wire sout_shift = (counter[3:0] == 4'd0);
	always @(posedge txclk) begin
		if (reset) sout_buf <= 10'h3ff;
		else if (we) sout_buf <= parity ? {din, 1'b0} : {1'b1, din[7:0], 1'b0};
		else if (sout_shift) sout_buf <= {1'b1, sout_buf[9:1]};
	end
	assign sout = break ? 1'b0 : sout_buf[0];

endmodule