data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v
 line:64: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #0\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #2  rst = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10 rx_alu_done=1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #2   rx_alu_done=1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #2  done_tx = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #2  done_tx = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10 rx_alu_done=1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #2   rx_alu_done=1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #200 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:67: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:54: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                      : ... In instance tb_intTx_alu\n  #10 rx_alu_done=1\'b1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:55: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance tb_intTx_alu\n  #2   rx_alu_done=1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:61: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                      : ... In instance tb_intTx_alu\n  #10 rx_alu_done=1\'b1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:62: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance tb_intTx_alu\n  #2   rx_alu_done=1\'b0;\n                  ^\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:69: Cannot find file containing module: \'interfaz_tx\'\n    interfaz_tx  \n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/interfaz_tx\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/interfaz_tx.v\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/interfaz_tx.sv\n             interfaz_tx\n             interfaz_tx.v\n             interfaz_tx.sv\n             obj_dir/interfaz_tx\n             obj_dir/interfaz_tx.v\n             obj_dir/interfaz_tx.sv\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_intTx_alu.v:82: Cannot find file containing module: \'ALU\'\n      ALU\n      ^~~\n%Error: Exiting due to 2 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_intTx_alu();


localparam  NB_DBIT_01    =  8;
localparam NB_OPER_01 = 6;

reg  clk;
reg  rst;
reg done_tx;


wire  signed       [NB_DBIT_01-1:0]        o_data;
wire tx_start;
wire tx_done_alu;

reg  signed       [NB_DBIT_01-1:0]        o_data_bus_a;
reg  signed       [NB_DBIT_01-1:0]        o_data_bus_b;
reg  [NB_OPER_01-1:0]    o_data_operador;
reg [NB_DBIT_01-1:0]  rx_alu_done;

wire [NB_DBIT_01-1:0] alu_resultado;
initial begin
  #0
  rst = 1'b0;
  clk = 1'b0;
  done_tx = 1'b0;
  o_data_bus_a= 8'b00000100;
  o_data_bus_b= 8'b00000010;
  o_data_operador= 6'b100000;
  
  #2  rst = 1'b1;
  #10 rx_alu_done=1'b1;
  #2   rx_alu_done=1'b0;
  #2  done_tx = 1'b1;
  #2  done_tx = 1'b0;
  o_data_bus_a= 8'b00000110;
  o_data_bus_b= 8'b00000011;
  o_data_operador= 6'b100010;
  #10 rx_alu_done=1'b1;
  #2   rx_alu_done=1'b0;

  #200 $finish;
end

always #1 clk = ~clk;

    interfaz_tx  
    #(.NB_DATA           (NB_DBIT_01))
    u_interfaz_01
    (
      .i_clk (clk),
      .i_rst (rst),
      .i_resultado (alu_resultado),
      .i_done_alu (tx_done_alu),
      .i_done_tx(done_tx),
      .o_data (o_data),
      .o_int_tx (tx_start)
    );
    
      ALU
      #(.NB_DATA           (NB_DBIT_01), .NB_OPERADOR(NB_OPER_01))
      u_alu1
      (
       .i_dato_a(o_data_bus_a),
       .i_dato_b(o_data_bus_b),
       .i_operador(o_data_operador),
       .i_alu_valid(rx_alu_done),
       .o_done_alu_tx(tx_done_alu),
       .o_resultado(alu_resultado)  
      );

endmodule
module tb_intTx_alu();



localparam  NB_DBIT_01    =  8;
localparam NB_OPER_01 = 6;

reg  clk;
reg  rst;
reg done_tx;


wire  signed       [NB_DBIT_01-1:0]        o_data;
wire tx_start;
wire tx_done_alu;

reg  signed       [NB_DBIT_01-1:0]        o_data_bus_a;
reg  signed       [NB_DBIT_01-1:0]        o_data_bus_b;
reg  [NB_OPER_01-1:0]    o_data_operador;
reg [NB_DBIT_01-1:0]  rx_alu_done;

wire [NB_DBIT_01-1:0] alu_resultado;
initial begin
  #0
  rst = 1'b0;
  clk = 1'b0;
  done_tx = 1'b0;
  o_data_bus_a= 8'b00000100;
  o_data_bus_b= 8'b00000010;
  o_data_operador= 6'b100000;
  
  #2  rst = 1'b1;
  #10 rx_alu_done=1'b1;
  #2   rx_alu_done=1'b0;
  #2  done_tx = 1'b1;
  #2  done_tx = 1'b0;
  o_data_bus_a= 8'b00000110;
  o_data_bus_b= 8'b00000011;
  o_data_operador= 6'b100010;
  #10 rx_alu_done=1'b1;
  #2   rx_alu_done=1'b0;

  #200 $finish;
end

always #1 clk = ~clk;

    interfaz_tx  
    #(.NB_DATA           (NB_DBIT_01))
    u_interfaz_01
    (
      .i_clk (clk),
      .i_rst (rst),
      .i_resultado (alu_resultado),
      .i_done_alu (tx_done_alu),
      .i_done_tx(done_tx),
      .o_data (o_data),
      .o_int_tx (tx_start)
    );
    
      ALU
      #(.NB_DATA           (NB_DBIT_01), .NB_OPERADOR(NB_OPER_01))
      u_alu1
      (
       .i_dato_a(o_data_bus_a),
       .i_dato_b(o_data_bus_b),
       .i_operador(o_data_operador),
       .i_alu_valid(rx_alu_done),
       .o_done_alu_tx(tx_done_alu),
       .o_resultado(alu_resultado)  
      );

endmodule