data/full_repos/permissive/218126213/spi_ip_core.v
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1: b'%Error: data/full_repos/permissive/218126213/spi_ip_core.v:1: Cannot find include file: global_memory_parameters.v\n`include "global_memory_parameters.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/218126213,data/full_repos/permissive/218126213/global_memory_parameters.v\n             data/full_repos/permissive/218126213,data/full_repos/permissive/218126213/global_memory_parameters.v.v\n             data/full_repos/permissive/218126213,data/full_repos/permissive/218126213/global_memory_parameters.v.sv\n             global_memory_parameters.v\n             global_memory_parameters.v.v\n             global_memory_parameters.v.sv\n             obj_dir/global_memory_parameters.v\n             obj_dir/global_memory_parameters.v.v\n             obj_dir/global_memory_parameters.v.sv\n%Error: data/full_repos/permissive/218126213/spi_ip_core.v:117: Define or directive not defined: \'`t_clqv\'\n  MISO<=#`t_clqv 1\'bZ;\n         ^~~~~~~\n%Error: data/full_repos/permissive/218126213/spi_ip_core.v:121: Define or directive not defined: \'`t_clqv\'\n  MISO<= #`t_clqv miso_buff;\n          ^~~~~~~\n%Error: data/full_repos/permissive/218126213/spi_ip_core.v:121: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  MISO<= #`t_clqv miso_buff;\n                           ^\n%Error: Exiting due to 4 error(s)\n'
module spi_ip_core(
	input clk,

	input MOSI,
	input SPI_SCK,
	input SPI_RESET,
	input SPI_S,
	output reg MISO,

	output reg [7:0] D,
	output reg RESET,
	output reg S,
	output reg DATA_DONE,
	input [7:0] Q
);

reg sck_val=1'b0;
reg [2:0] cnt_bit=3'b000;
reg [7:0] data_to_read=8'h00;
reg [7:0] data_to_send=8'h00;
reg [2:0] s_reg=3'b000;
reg s_flag=1'b0;
reg rst_flag=1'b0;
reg miso_buff=1'b0;


always @ (posedge clk)
begin
	if(rst_flag)
	begin
		sck_val<=0;
	end
	else
	begin
		sck_val<=SPI_SCK;
	end
end
	
wire sck_pos=(SPI_SCK && !sck_val);
wire sck_neg=(!SPI_SCK && sck_val);


always @ (posedge clk)
	begin
	if(rst_flag)
	begin
		s_flag<=1'b0;
	end
	else
	begin
		s_flag<=SPI_S;
	end
	S<=SPI_S;
end

wire s_rise=(SPI_S && !s_flag);
wire s_neg=(!SPI_S && s_flag);


always @ (SPI_RESET)
begin
	if(SPI_RESET)
	begin
		rst_flag<=1'b0;
	end
	else
	begin
		rst_flag<=1'b1;
	end
	RESET<=SPI_RESET;
end


always @ (posedge clk)
begin	
	if(sck_neg && !s_flag)
	begin
		cnt_bit<=cnt_bit+1;
		data_to_read[7-cnt_bit]<=MOSI;
	end
	else if(cnt_bit==3'b111 && !s_flag)
	begin
		DATA_DONE<=1'b1;
	end
	else if (DATA_DONE)
	begin
		data_to_read[7-cnt_bit]<=MOSI;
		D<=data_to_read;
		data_to_read<=8'h00;
		DATA_DONE<=1'b0;
		data_to_send<=Q;
	end
	else if(s_flag)
	begin
		cnt_bit<=0;
	end
	else
	begin
		DATA_DONE<=1'b0;
	end
end

always @ (posedge clk)
begin
	if(!s_flag && !rst_flag && sck_pos)
	begin
		miso_buff<=data_to_send[7-cnt_bit];
	end
end

always @ (miso_buff)
begin
	if(rst_flag)
	begin
		MISO<=#`t_clqv 1'bZ;
	end
	else
	begin
		MISO<= #`t_clqv miso_buff;
	end
end

endmodule
module spi_ip_core(
	input clk,

	input MOSI,
	input SPI_SCK,
	input SPI_RESET,
	input SPI_S,
	output reg MISO,

	output reg [7:0] D,
	output reg RESET,
	output reg S,
	output reg DATA_DONE,
	input [7:0] Q
);


reg sck_val=1'b0;
reg [2:0] cnt_bit=3'b000;
reg [7:0] data_to_read=8'h00;
reg [7:0] data_to_send=8'h00;
reg [2:0] s_reg=3'b000;
reg s_flag=1'b0;
reg rst_flag=1'b0;
reg miso_buff=1'b0;


always @ (posedge clk)
begin
	if(rst_flag)
	begin
		sck_val<=0;
	end
	else
	begin
		sck_val<=SPI_SCK;
	end
end
	
wire sck_pos=(SPI_SCK && !sck_val);
wire sck_neg=(!SPI_SCK && sck_val);


always @ (posedge clk)
	begin
	if(rst_flag)
	begin
		s_flag<=1'b0;
	end
	else
	begin
		s_flag<=SPI_S;
	end
	S<=SPI_S;
end

wire s_rise=(SPI_S && !s_flag);
wire s_neg=(!SPI_S && s_flag);


always @ (SPI_RESET)
begin
	if(SPI_RESET)
	begin
		rst_flag<=1'b0;
	end
	else
	begin
		rst_flag<=1'b1;
	end
	RESET<=SPI_RESET;
end


always @ (posedge clk)
begin	
	if(sck_neg && !s_flag)
	begin
		cnt_bit<=cnt_bit+1;
		data_to_read[7-cnt_bit]<=MOSI;
	end
	else if(cnt_bit==3'b111 && !s_flag)
	begin
		DATA_DONE<=1'b1;
	end
	else if (DATA_DONE)
	begin
		data_to_read[7-cnt_bit]<=MOSI;
		D<=data_to_read;
		data_to_read<=8'h00;
		DATA_DONE<=1'b0;
		data_to_send<=Q;
	end
	else if(s_flag)
	begin
		cnt_bit<=0;
	end
	else
	begin
		DATA_DONE<=1'b0;
	end
end

always @ (posedge clk)
begin
	if(!s_flag && !rst_flag && sck_pos)
	begin
		miso_buff<=data_to_send[7-cnt_bit];
	end
end

always @ (miso_buff)
begin
	if(rst_flag)
	begin
		MISO<=#`t_clqv 1'bZ;
	end
	else
	begin
		MISO<= #`t_clqv miso_buff;
	end
end

endmodule