data/full_repos/permissive/129527056/modules/jtgng_tile3.v
data/verilator_xmls/167a1674-8e4e-440f-a50f-b08c7c90d2ec.xml
module jtgng_tile3 #( parameter
    DATAREAD = 1,
    ROM_AW   = 15,
    PALW     = 4,

    IDMSB1   = 7,
    IDMSB0   = 6,
    VFLIP    = 5,
    HFLIP    = 4
) (
    input                   clk,
    input                   pxl_cen,
    input       [8:0]       HS,
    input       [8:0]       VS,
    input       [7:0]       attr,
    input       [7:0]       id,
    input                   flip,

    output reg [ROM_AW-1:0] scr_addr,
    input            [23:0] rom_data,
    input                   rom_ok,
    output reg [PALW-1:0]   scr_pal,
    output reg     [ 2:0]   scr_col
);

reg scr_hflip;
reg [7:0] addr_lsb;

reg [PALW:0] scr_attr0, scr_attr1;


always @(posedge clk) if(pxl_cen) begin
    if( HS[2:0]==DATAREAD ) begin

        scr_attr1 <= scr_attr0;
        scr_attr0 <= { attr[HFLIP], attr[PALW-1:0] };
        scr_addr  <= {   attr[IDMSB1:IDMSB0], id,
                        HS[3]^attr[HFLIP],
                        {4{attr[VFLIP]}}^VS[3:0]};
    end
end


reg [7:0] x,y,z;
reg [PALW-1:0] scr_attr2;

reg [23:0] good_data;
always @(posedge clk) begin
    if( HS[2:0] > (DATAREAD+3'd1) && rom_ok )
        good_data <= rom_data;
end

always @(posedge clk) if(pxl_cen) begin



    if( HS[2:0]==(DATAREAD+3'd1) ) begin
            { z,y,x } <= good_data;
            scr_hflip <= scr_attr1[PALW] ^ flip;
            scr_attr2 <= scr_attr1[PALW-1:0];
        end
    else
        begin
            if( scr_hflip ) begin
                x <= {1'b0, x[7:1]};
                y <= {1'b0, y[7:1]};
                z <= {1'b0, z[7:1]};
            end
            else  begin
                x <= {x[6:0], 1'b0};
                y <= {y[6:0], 1'b0};
                z <= {z[6:0], 1'b0};
            end
        end
    scr_col <= scr_hflip ? { x[0], y[0], z[0] } : { x[7], y[7], z[7] };
    scr_pal <= scr_attr2[PALW-1:0];
end

endmodule
module jtgng_tile3 #( parameter
    DATAREAD = 1,
    ROM_AW   = 15,
    PALW     = 4,

    IDMSB1   = 7,
    IDMSB0   = 6,
    VFLIP    = 5,
    HFLIP    = 4
) (
    input                   clk,
    input                   pxl_cen,
    input       [8:0]       HS,
    input       [8:0]       VS,
    input       [7:0]       attr,
    input       [7:0]       id,
    input                   flip,

    output reg [ROM_AW-1:0] scr_addr,
    input            [23:0] rom_data,
    input                   rom_ok,
    output reg [PALW-1:0]   scr_pal,
    output reg     [ 2:0]   scr_col
);


reg scr_hflip;
reg [7:0] addr_lsb;

reg [PALW:0] scr_attr0, scr_attr1;


always @(posedge clk) if(pxl_cen) begin
    if( HS[2:0]==DATAREAD ) begin

        scr_attr1 <= scr_attr0;
        scr_attr0 <= { attr[HFLIP], attr[PALW-1:0] };
        scr_addr  <= {   attr[IDMSB1:IDMSB0], id,
                        HS[3]^attr[HFLIP],
                        {4{attr[VFLIP]}}^VS[3:0]};
    end
end


reg [7:0] x,y,z;
reg [PALW-1:0] scr_attr2;

reg [23:0] good_data;
always @(posedge clk) begin
    if( HS[2:0] > (DATAREAD+3'd1) && rom_ok )
        good_data <= rom_data;
end

always @(posedge clk) if(pxl_cen) begin



    if( HS[2:0]==(DATAREAD+3'd1) ) begin
            { z,y,x } <= good_data;
            scr_hflip <= scr_attr1[PALW] ^ flip;
            scr_attr2 <= scr_attr1[PALW-1:0];
        end
    else
        begin
            if( scr_hflip ) begin
                x <= {1'b0, x[7:1]};
                y <= {1'b0, y[7:1]};
                z <= {1'b0, z[7:1]};
            end
            else  begin
                x <= {x[6:0], 1'b0};
                y <= {y[6:0], 1'b0};
                z <= {z[6:0], 1'b0};
            end
        end
    scr_col <= scr_hflip ? { x[0], y[0], z[0] } : { x[7], y[7], z[7] };
    scr_pal <= scr_attr2[PALW-1:0];
end

endmodule