data/full_repos/permissive/2084115/rtl/bus/jelly_axi4s_video_width_converter.v
1: b"%Error: data/full_repos/permissive/2084115/rtl/bus/jelly_axi4s_video_width_converter.v:45: Cannot find file containing module: 'jelly_data_width_converter'\n    jelly_data_width_converter\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/bus,data/full_repos/permissive/2084115/jelly_data_width_converter\n             data/full_repos/permissive/2084115/rtl/bus,data/full_repos/permissive/2084115/jelly_data_width_converter.v\n             data/full_repos/permissive/2084115/rtl/bus,data/full_repos/permissive/2084115/jelly_data_width_converter.sv\n             jelly_data_width_converter\n             jelly_data_width_converter.v\n             jelly_data_width_converter.sv\n             obj_dir/jelly_data_width_converter\n             obj_dir/jelly_data_width_converter.v\n             obj_dir/jelly_data_width_converter.sv\n%Error: Exiting due to 1 error(s)\n"
module jelly_axi4s_video_width_converter
        #(
            parameter   UNIT_WIDTH    = 8,
            parameter   S_TDATA_SIZE  = 0,
            parameter   M_TDATA_SIZE  = 0,
                                                
            parameter   S_TDATA_WIDTH = (UNIT_WIDTH << S_TDATA_SIZE),
            parameter   M_TDATA_WIDTH = (UNIT_WIDTH << M_TDATA_SIZE)
        )
        (
            input   wire                        aresetn,
            input   wire                        aclk,
            input   wire                        aclken,
            
            input   wire                        endian,
            
            input   wire    [0:0]               s_axi4s_tuser,
            input   wire                        s_axi4s_tlast,
            input   wire    [S_TDATA_WIDTH-1:0] s_axi4s_tdata,
            input   wire                        s_axi4s_tvalid,
            output  wire                        s_axi4s_tready,
            
            output  wire    [0:0]               m_axi4s_tuser,
            output  wire                        m_axi4s_tlast,
            output  wire    [M_TDATA_WIDTH-1:0] m_axi4s_tdata,
            output  wire                        m_axi4s_tvalid,
            input   wire                        m_axi4s_tready
        );
    
    
    jelly_data_width_converter
            #(
                .UNIT_WIDTH     (UNIT_WIDTH),
                .S_DATA_SIZE    (S_TDATA_SIZE),
                .M_DATA_SIZE    (M_TDATA_SIZE),
                .INIT_DATA      ({M_TDATA_WIDTH{1'bx}})
            )
        i_data_width_converter_tdata
            (
                .reset          (~aresetn),
                .clk            (aclk),
                .cke            (aclken),
                
                .endian         (endian),
                
                .s_data         (s_axi4s_tdata),
                .s_first        (s_axi4s_tuser),
                .s_last         (s_axi4s_tlast),
                .s_valid        (s_axi4s_tvalid),
                .s_ready        (s_axi4s_tready),
                
                .m_data         (m_axi4s_tdata),
                .m_first        (m_axi4s_tuser),
                .m_last         (m_axi4s_tlast),
                .m_valid        (m_axi4s_tvalid),
                .m_ready        (m_axi4s_tready)
            );
    
    
endmodule
module jelly_axi4s_video_width_converter
        #(
            parameter   UNIT_WIDTH    = 8,
            parameter   S_TDATA_SIZE  = 0,
            parameter   M_TDATA_SIZE  = 0,
                                                
            parameter   S_TDATA_WIDTH = (UNIT_WIDTH << S_TDATA_SIZE),
            parameter   M_TDATA_WIDTH = (UNIT_WIDTH << M_TDATA_SIZE)
        )
        (
            input   wire                        aresetn,
            input   wire                        aclk,
            input   wire                        aclken,
            
            input   wire                        endian,
            
            input   wire    [0:0]               s_axi4s_tuser,
            input   wire                        s_axi4s_tlast,
            input   wire    [S_TDATA_WIDTH-1:0] s_axi4s_tdata,
            input   wire                        s_axi4s_tvalid,
            output  wire                        s_axi4s_tready,
            
            output  wire    [0:0]               m_axi4s_tuser,
            output  wire                        m_axi4s_tlast,
            output  wire    [M_TDATA_WIDTH-1:0] m_axi4s_tdata,
            output  wire                        m_axi4s_tvalid,
            input   wire                        m_axi4s_tready
        );

    
    
    jelly_data_width_converter
            #(
                .UNIT_WIDTH     (UNIT_WIDTH),
                .S_DATA_SIZE    (S_TDATA_SIZE),
                .M_DATA_SIZE    (M_TDATA_SIZE),
                .INIT_DATA      ({M_TDATA_WIDTH{1'bx}})
            )
        i_data_width_converter_tdata
            (
                .reset          (~aresetn),
                .clk            (aclk),
                .cke            (aclken),
                
                .endian         (endian),
                
                .s_data         (s_axi4s_tdata),
                .s_first        (s_axi4s_tuser),
                .s_last         (s_axi4s_tlast),
                .s_valid        (s_axi4s_tvalid),
                .s_ready        (s_axi4s_tready),
                
                .m_data         (m_axi4s_tdata),
                .m_first        (m_axi4s_tuser),
                .m_last         (m_axi4s_tlast),
                .m_valid        (m_axi4s_tvalid),
                .m_ready        (m_axi4s_tready)
            );
    
    
endmodule