data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/d_ff2.v
data/verilator_xmls/7a9f7306-73ac-4c5e-8357-2ced47cfcaaa.xml
module d_ff2 (q,clk,reset,out);

input [20:0]q;
input clk;
input reset;
output reg [20:0]out;

always@ (posedge clk)
begin
    if(~reset)
    begin
        out <= 21'b0;
    end
    else 
    begin
        out <= q;
    end

end

endmodule
module d_ff2 (q,clk,reset,out);


input [20:0]q;
input clk;
input reset;
output reg [20:0]out;

always@ (posedge clk)
begin
    if(~reset)
    begin
        out <= 21'b0;
    end
    else 
    begin
        out <= q;
    end

end

endmodule