data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:619: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:623: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:628: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  {temp[0], temp[31:1]} = out_left & key_left;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:596: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:600: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:604: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  {temp[0], temp[31:1]} = in_left & key_left;\n                                ^\n%Error: Exiting due to 14 warning(s)\n'
module Camellia_key_scheduler( EncDec, RSTn, EN, CLK, kl, ka, state, round, kl_in, ka_in );
  input          CLK, RSTn, EN;
  input [3:0] 	 state;
  input [4:0] 	 round;
  input [127:0]  kl_in;
  input [127:0]  ka_in;
  input 	 EncDec;
  
  output [127:0] kl, ka;


  parameter ST_IDLE                = 4'h0;
  parameter ST_IDLE_READY          = 4'h1;


  parameter ST_KEY_GET             = 4'h3;
  parameter ST_KEY_F_FUNC          = 4'h4;
  parameter ST_KEY_XOR             = 4'h5;


  parameter ST_RANDOMIZE_GET         = 4'h7;
  parameter ST_RANDOMIZE_INITIAL_XOR = 4'h8;
  parameter ST_RANDOMIZE_FINAL_XOR   = 4'h9;
  parameter ST_RANDOMIZE_F_FUNC      = 4'ha;
  parameter ST_RANDOMIZE_FL_1        = 4'hb;
  parameter ST_RANDOMIZE_FL_2        = 4'hc;

  parameter Enc = 1'b0;
  parameter Dec = 1'b1;

  reg [127:0] 	 kl, ka;
  reg 		 EncDec_reg;

  wire [127:0] 	 kl_rotate_left_15,  ka_rotate_left_15;
  wire [127:0] 	 kl_rotate_left_17,  ka_rotate_left_17;
  wire [127:0] 	 kl_rotate_right_15, ka_rotate_right_15;
  wire [127:0] 	 kl_rotate_right_17, ka_rotate_right_17;

  assign 	 kl_rotate_left_15 = {kl[112:0], kl[127:113]};
  assign 	 ka_rotate_left_15 = {ka[112:0], ka[127:113]};
  assign 	 kl_rotate_left_17 = {kl[110:0], kl[127:111]};
  assign 	 ka_rotate_left_17 = {ka[110:0], ka[127:111]};

  assign 	 kl_rotate_right_15 = {kl[14:0], kl[127:15]};
  assign 	 ka_rotate_right_15 = {ka[14:0], ka[127:15]};
  assign 	 kl_rotate_right_17 = {kl[16:0], kl[127:17]};
  assign 	 ka_rotate_right_17 = {ka[16:0], ka[127:17]};
  
  always @(posedge CLK) begin
    if (RSTn == 1'b0) begin
      kl <= 128'h00000000000000000000000000000000;
      ka <= 128'h00000000000000000000000000000000;
    end
    else if(EN == 1)
      case(state)
	ST_KEY_GET:    kl <= kl_in;
	ST_KEY_F_FUNC: if(round == 5'd04) ka <= ka_in;

	ST_RANDOMIZE_GET: begin
	  EncDec_reg <= EncDec;
	  if(EncDec == Dec) begin

	    kl <= kl_rotate_right_17;
	    ka <= ka_rotate_right_17;
	  end
	end

	ST_RANDOMIZE_FL_1: begin
	  kl <= (EncDec_reg == Enc) ? kl_rotate_left_15 : kl_rotate_right_17;
	  ka <= (EncDec_reg == Enc) ? ka_rotate_left_15 : ka_rotate_right_17;
	end

	ST_RANDOMIZE_FL_2: begin
	  kl <= (EncDec_reg == Enc) ? kl_rotate_left_17 : kl_rotate_right_15;
	  ka <= (EncDec_reg == Enc) ? ka_rotate_left_17 : ka_rotate_right_15;
	end
	
	ST_RANDOMIZE_F_FUNC:
	  case(round)
	    5'd02, 5'd06 :   begin
	      kl <= (EncDec_reg == Enc) ? kl_rotate_left_15 : kl_rotate_right_17;
	      ka <= (EncDec_reg == Enc) ? ka_rotate_left_15 : ka_rotate_right_17;
	    end
	    
	    5'd09 : begin
	      kl <= (EncDec_reg == Enc) ? kl_rotate_left_15 : kl_rotate_right_15;
	      ka <= (EncDec_reg == Enc) ? ka_rotate_left_15 : ka_rotate_right_15;
	    end		 
	    
	    5'd12, 5'd16: begin
	      kl <= (EncDec_reg == Enc) ? kl_rotate_left_17 : kl_rotate_right_15;
	      ka <= (EncDec_reg == Enc) ? ka_rotate_left_17 : ka_rotate_right_15;
	    end
	  endcase



	ST_RANDOMIZE_FINAL_XOR: begin
	  if(EncDec_reg == Enc) begin
	    kl <= kl_rotate_left_17;
	    ka <= ka_rotate_left_17;
	  end
	end	
      endcase

  end
endmodule
module Camellia_key_scheduler( EncDec, RSTn, EN, CLK, kl, ka, state, round, kl_in, ka_in );

  input          CLK, RSTn, EN;
  input [3:0] 	 state;
  input [4:0] 	 round;
  input [127:0]  kl_in;
  input [127:0]  ka_in;
  input 	 EncDec;
  
  output [127:0] kl, ka;


  parameter ST_IDLE                = 4'h0;
  parameter ST_IDLE_READY          = 4'h1;


  parameter ST_KEY_GET             = 4'h3;
  parameter ST_KEY_F_FUNC          = 4'h4;
  parameter ST_KEY_XOR             = 4'h5;


  parameter ST_RANDOMIZE_GET         = 4'h7;
  parameter ST_RANDOMIZE_INITIAL_XOR = 4'h8;
  parameter ST_RANDOMIZE_FINAL_XOR   = 4'h9;
  parameter ST_RANDOMIZE_F_FUNC      = 4'ha;
  parameter ST_RANDOMIZE_FL_1        = 4'hb;
  parameter ST_RANDOMIZE_FL_2        = 4'hc;

  parameter Enc = 1'b0;
  parameter Dec = 1'b1;

  reg [127:0] 	 kl, ka;
  reg 		 EncDec_reg;

  wire [127:0] 	 kl_rotate_left_15,  ka_rotate_left_15;
  wire [127:0] 	 kl_rotate_left_17,  ka_rotate_left_17;
  wire [127:0] 	 kl_rotate_right_15, ka_rotate_right_15;
  wire [127:0] 	 kl_rotate_right_17, ka_rotate_right_17;

  assign 	 kl_rotate_left_15 = {kl[112:0], kl[127:113]};
  assign 	 ka_rotate_left_15 = {ka[112:0], ka[127:113]};
  assign 	 kl_rotate_left_17 = {kl[110:0], kl[127:111]};
  assign 	 ka_rotate_left_17 = {ka[110:0], ka[127:111]};

  assign 	 kl_rotate_right_15 = {kl[14:0], kl[127:15]};
  assign 	 ka_rotate_right_15 = {ka[14:0], ka[127:15]};
  assign 	 kl_rotate_right_17 = {kl[16:0], kl[127:17]};
  assign 	 ka_rotate_right_17 = {ka[16:0], ka[127:17]};
  
  always @(posedge CLK) begin
    if (RSTn == 1'b0) begin
      kl <= 128'h00000000000000000000000000000000;
      ka <= 128'h00000000000000000000000000000000;
    end
    else if(EN == 1)
      case(state)
	ST_KEY_GET:    kl <= kl_in;
	ST_KEY_F_FUNC: if(round == 5'd04) ka <= ka_in;

	ST_RANDOMIZE_GET: begin
	  EncDec_reg <= EncDec;
	  if(EncDec == Dec) begin

	    kl <= kl_rotate_right_17;
	    ka <= ka_rotate_right_17;
	  end
	end

	ST_RANDOMIZE_FL_1: begin
	  kl <= (EncDec_reg == Enc) ? kl_rotate_left_15 : kl_rotate_right_17;
	  ka <= (EncDec_reg == Enc) ? ka_rotate_left_15 : ka_rotate_right_17;
	end

	ST_RANDOMIZE_FL_2: begin
	  kl <= (EncDec_reg == Enc) ? kl_rotate_left_17 : kl_rotate_right_15;
	  ka <= (EncDec_reg == Enc) ? ka_rotate_left_17 : ka_rotate_right_15;
	end
	
	ST_RANDOMIZE_F_FUNC:
	  case(round)
	    5'd02, 5'd06 :   begin
	      kl <= (EncDec_reg == Enc) ? kl_rotate_left_15 : kl_rotate_right_17;
	      ka <= (EncDec_reg == Enc) ? ka_rotate_left_15 : ka_rotate_right_17;
	    end
	    
	    5'd09 : begin
	      kl <= (EncDec_reg == Enc) ? kl_rotate_left_15 : kl_rotate_right_15;
	      ka <= (EncDec_reg == Enc) ? ka_rotate_left_15 : ka_rotate_right_15;
	    end		 
	    
	    5'd12, 5'd16: begin
	      kl <= (EncDec_reg == Enc) ? kl_rotate_left_17 : kl_rotate_right_15;
	      ka <= (EncDec_reg == Enc) ? ka_rotate_left_17 : ka_rotate_right_15;
	    end
	  endcase



	ST_RANDOMIZE_FINAL_XOR: begin
	  if(EncDec_reg == Enc) begin
	    kl <= kl_rotate_left_17;
	    ka <= ka_rotate_left_17;
	  end
	end	
      endcase

  end
endmodule