data/full_repos/permissive/110151336/lab_02/src/05_dff_with_sync_rst_n/dff_sync_rst_n.v
data/verilator_xmls/ce3c23f9-109a-47cc-8487-6b7a546b8f08.xml
module dff_sync_rst_n
(
    input       clk,
    input       rst_n,
    input       d,
    output  reg q
);

    always @ (posedge clk)
        if (!rst_n)
            q <= 0;
        else
            q <= d;
 
endmodule
module dff_sync_rst_n
(
    input       clk,
    input       rst_n,
    input       d,
    output  reg q
);


    always @ (posedge clk)
        if (!rst_n)
            q <= 0;
        else
            q <= d;
 
endmodule