data/full_repos/permissive/135852214/Verilog/bustap.v
1: b'%Warning-WIDTH: data/full_repos/permissive/135852214/Verilog/bustap.v:9: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 38 bits.\n                                                                       : ... In instance bustap\n data_out <= {rw,addr,data_out};\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module bustap(
    input rw, 
    input [11:0] addr,
    input [11:0] data,
    output reg [24:0] data_out 
    );

always @*
	data_out <= {rw,addr,data_out};

endmodule
module bustap(
    input rw, 
    input [11:0] addr,
    input [11:0] data,
    output reg [24:0] data_out 
    );


always @*
	data_out <= {rw,addr,data_out};

endmodule