data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v
1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:5: Define or directive not defined: \'`ICODE_BUS\'\n    input wire [`ICODE_BUS] M_icode_i,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:5: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`ICODE_BUS] M_icode_i,\n                          ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:6: Define or directive not defined: \'`ICODE_BUS\'\n    input wire [`ICODE_BUS] W_icode_i,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:7: Define or directive not defined: \'`ADDR_BUS\'\n    input wire [`ADDR_BUS] M_valA_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:8: Define or directive not defined: \'`ADDR_BUS\'\n    input wire [`ADDR_BUS] W_valM_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:9: Define or directive not defined: \'`ADDR_BUS\'\n    input wire [`ADDR_BUS] F_predPC_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:11: Define or directive not defined: \'`ADDR_BUS\'\n    output reg [`ADDR_BUS] f_pc_o\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:16: Define or directive not defined: \'`JXX\'\n            if(M_icode_i == `JXX && !M_Cnd_i)\n                            ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/select_pc.v:20: Define or directive not defined: \'`RET\'\n            else if(W_icode_i == `RET)\n                                 ^~~~\n%Error: Exiting due to 10 error(s)\n'
module select_pc(
    input wire M_Cnd_i,
    input wire [`ICODE_BUS] M_icode_i,
    input wire [`ICODE_BUS] W_icode_i,
    input wire [`ADDR_BUS] M_valA_i,
    input wire [`ADDR_BUS] W_valM_i,
    input wire [`ADDR_BUS] F_predPC_i,
    
    output reg [`ADDR_BUS] f_pc_o
    );
    
    always @(*)
        begin
            if(M_icode_i == `JXX && !M_Cnd_i)
            begin
                f_pc_o = M_valA_i;
            end
            else if(W_icode_i == `RET)
            begin
                f_pc_o = W_valM_i;
            end
            else
            begin
                f_pc_o = F_predPC_i;
            end
        end
endmodule
module select_pc(
    input wire M_Cnd_i,
    input wire [`ICODE_BUS] M_icode_i,
    input wire [`ICODE_BUS] W_icode_i,
    input wire [`ADDR_BUS] M_valA_i,
    input wire [`ADDR_BUS] W_valM_i,
    input wire [`ADDR_BUS] F_predPC_i,
    
    output reg [`ADDR_BUS] f_pc_o
    );

    
    always @(*)
        begin
            if(M_icode_i == `JXX && !M_Cnd_i)
            begin
                f_pc_o = M_valA_i;
            end
            else if(W_icode_i == `RET)
            begin
                f_pc_o = W_valM_i;
            end
            else
            begin
                f_pc_o = F_predPC_i;
            end
        end
endmodule