data/full_repos/permissive/18469949/LC3_ALU.v
data/verilator_xmls/c07dae51-3683-447b-94b7-3665752a615e.xml
module LC3_ALU(
		input				[15:0]	NUMA,
		input				[15:0]	NUMB,
		input				[1:0]	ALUK,
		output	reg	[15:0]	ALUout
    );
		always@(NUMA or NUMB or ALUK) begin
			case (ALUK)
				2'b00:	ALUout<=NUMA+NUMB;
				2'b01:	ALUout<=NUMA&NUMB;
				2'b10:	ALUout<=~NUMA;
				2'b11:	ALUout<=NUMA;
			endcase
		end
			


endmodule
module LC3_ALU(
		input				[15:0]	NUMA,
		input				[15:0]	NUMB,
		input				[1:0]	ALUK,
		output	reg	[15:0]	ALUout
    );

		always@(NUMA or NUMB or ALUK) begin
			case (ALUK)
				2'b00:	ALUout<=NUMA+NUMB;
				2'b01:	ALUout<=NUMA&NUMB;
				2'b10:	ALUout<=~NUMA;
				2'b11:	ALUout<=NUMA;
			endcase
		end
			


endmodule