data/full_repos/permissive/204636037/project_led_exp.srcs/sources_1/new/led_first.v
data/verilator_xmls/f50f9826-8ed2-4345-8311-78de5676477e.xml
module led_first(
           input        clock,
           output [7:0] led
       );
parameter CNT_1S = 27'd99_999_999;

reg [7:0] led_tmp;

assign led = led_tmp;


reg [26:0] cnt;
wire cnt_eq_1s = cnt == CNT_1S;

always @(posedge clock) begin
    if(cnt_eq_1s) begin
        cnt <= 27'd0;
    end
    else begin
        cnt <= cnt+1'b1;
    end
end

always @(posedge clock) begin
    if(cnt_eq_1s) begin
        led_tmp <= {led_tmp[6:0],led_tmp[7]};
    end
end


endmodule
module led_first(
           input        clock,
           output [7:0] led
       );

parameter CNT_1S = 27'd99_999_999;

reg [7:0] led_tmp;

assign led = led_tmp;


reg [26:0] cnt;
wire cnt_eq_1s = cnt == CNT_1S;

always @(posedge clock) begin
    if(cnt_eq_1s) begin
        cnt <= 27'd0;
    end
    else begin
        cnt <= cnt+1'b1;
    end
end

always @(posedge clock) begin
    if(cnt_eq_1s) begin
        led_tmp <= {led_tmp[6:0],led_tmp[7]};
    end
end


endmodule