data/full_repos/permissive/209644662/hardware/unused/sb/rtl/test_mux.svp
 line:4: before: "parameter"
1: b"%Error: data/full_repos/permissive/209644662/hardware/unused/sb/rtl/test_mux.svp:3: Define or directive not defined: '`mname'\nmodule `mname`  #(\n       ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/sb/rtl/test_mux.svp:3: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule `mname`  #(\n             ^\n%Error: data/full_repos/permissive/209644662/hardware/unused/sb/rtl/test_mux.svp:5: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter NumInp    = 4\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/sb/rtl/test_mux.svp:6: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/209644662/hardware/unused/sb/rtl/test_mux.svp:20: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/209644662/hardware/unused/sb/rtl/test_mux.svp:25: syntax error, unexpected always_comb\n  always_comb begin\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/sb/rtl/test_mux.svp:37: syntax error, unexpected always_ff\n  always_ff @(posedge clk or negedge rst_n) begin\n  ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module `mname`  #(
  parameter DataWidth = 16,
  parameter NumInp    = 4
) (

  input                        clk,
  input                        rst_n,


  input  [DataWidth-1:0]       data_in [NumInp-1:0],
  input  [$clog2(NumInp)-1:0]    sel,


  input                        reg_en,


  output logic [DataWidth-1:0] res
);

  logic [DataWidth-1:0] res_w;
  integer j;

  always_comb begin
    res_w = 'hX;

    for(j=0;j<NumInp; j=j+1) begin
      if(sel == j)
        res_w = data_in[j];
    end
  end


  logic [DataWidth-1:0] res_reg;

  always_ff @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
      res_reg <= 16'h0;
    end else if(reg_en) begin
      res_reg <= res_w;
    end
  end

  assign res = reg_en ? res_reg : res_w;

    assign res = res_w;


endmodule
module `mname`  #(
  parameter DataWidth = 16,
  parameter NumInp    = 4
) (

  input                        clk,
  input                        rst_n,


  input  [DataWidth-1:0]       data_in [NumInp-1:0],
  input  [$clog2(NumInp)-1:0]    sel,


  input                        reg_en,


  output logic [DataWidth-1:0] res
);


  logic [DataWidth-1:0] res_w;
  integer j;

  always_comb begin
    res_w = 'hX;

    for(j=0;j<NumInp; j=j+1) begin
      if(sel == j)
        res_w = data_in[j];
    end
  end


  logic [DataWidth-1:0] res_reg;

  always_ff @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
      res_reg <= 16'h0;
    end else if(reg_en) begin
      res_reg <= res_w;
    end
  end

  assign res = reg_en ? res_reg : res_w;

    assign res = res_w;


endmodule