data/full_repos/permissive/147790758/tb1_sum.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_sum.v:10: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_sum.v:12: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_sum.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_sum.v:16: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_sum.v:18: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_sum.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/147790758/tb1_sum.v:6: Cannot find file containing module: \'sum\'\nsum #(.WIDTH(4)) DUT (.data_a(term1), .data_b(term2));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/sum\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/sum.v\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/sum.sv\n             sum\n             sum.v\n             sum.sv\n             obj_dir/sum\n             obj_dir/sum.v\n             obj_dir/sum.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb1_sum ();
	reg [3:0]term1;
	reg [3:0]term2;
sum #(.WIDTH(4)) DUT (.data_a(term1), .data_b(term2));

initial begin
	term1 = 4'd15; term2 = 4'd15;
	#10;
	term1 = 4'd0; term2 = 4'd0;
	#10;
	term1 = 4'd6; term2 = 4'd5;
	#10;
	term1 = 4'd8; term2 = 4'd4;
	#10;
	term1 = 4'd15; term2 = 4'd1;
	#10;
	term1 = 4'd15; term2 = 4'd0;
	#10;
end 
endmodule
module tb1_sum ();

	reg [3:0]term1;
	reg [3:0]term2;
sum #(.WIDTH(4)) DUT (.data_a(term1), .data_b(term2));

initial begin
	term1 = 4'd15; term2 = 4'd15;
	#10;
	term1 = 4'd0; term2 = 4'd0;
	#10;
	term1 = 4'd6; term2 = 4'd5;
	#10;
	term1 = 4'd8; term2 = 4'd4;
	#10;
	term1 = 4'd15; term2 = 4'd1;
	#10;
	term1 = 4'd15; term2 = 4'd0;
	#10;
end 
endmodule