data/full_repos/permissive/167274925/DataMemory_tb.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-STMTDLY: data/full_repos/permissive/167274925/DataMemory_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 Clk <= ~Clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167274925/DataMemory_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Error: data/full_repos/permissive/167274925/DataMemory_tb.v:38: syntax error, unexpected \'@\'\n @(posedge Clk);\n ^\n%Error: data/full_repos/permissive/167274925/DataMemory_tb.v:42: syntax error, unexpected \'@\'\n  @(posedge Clk);\n  ^\n%Error: data/full_repos/permissive/167274925/DataMemory_tb.v:45: syntax error, unexpected \'@\'\n  @(posedge Clk);\n  ^\n%Error: data/full_repos/permissive/167274925/DataMemory_tb.v:48: syntax error, unexpected \'@\'\n     @(posedge Clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/DataMemory_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DataMemory_tb(); 

    reg     [31:0]  Address;
    reg     [31:0]  WriteData;
    reg             Clk;
    reg             MemWrite;
    reg             MemRead;

    wire [31:0] ReadData;

    DataMemory u0(
        .Address(Address), 
        .WriteData(WriteData), 
        .Clk(Clk), 
        .MemWrite(MemWrite), 
        .MemRead(MemRead), 
        .ReadData(ReadData)
    ); 

	initial begin
		Clk <= 1'b0;
		forever #10 Clk <= ~Clk;
	end

	initial begin
	MemWrite<=0;
	MemRead<=1;
	#5;
	@(posedge Clk);
	 MemWrite<=1;
	 Address<=32'd0;
	 WriteData<=32'd1;
	 @(posedge Clk);
      Address<=32'd4;
	  WriteData<=32'd7;
	 @(posedge Clk);
      Address<=32'd8;
     WriteData<=32'd20;
     @(posedge Clk);
     Address<=32'd12;
     WriteData<=32'd25;
      #100;
	end

endmodule
module DataMemory_tb();
 

    reg     [31:0]  Address;
    reg     [31:0]  WriteData;
    reg             Clk;
    reg             MemWrite;
    reg             MemRead;

    wire [31:0] ReadData;

    DataMemory u0(
        .Address(Address), 
        .WriteData(WriteData), 
        .Clk(Clk), 
        .MemWrite(MemWrite), 
        .MemRead(MemRead), 
        .ReadData(ReadData)
    ); 

	initial begin
		Clk <= 1'b0;
		forever #10 Clk <= ~Clk;
	end

	initial begin
	MemWrite<=0;
	MemRead<=1;
	#5;
	@(posedge Clk);
	 MemWrite<=1;
	 Address<=32'd0;
	 WriteData<=32'd1;
	 @(posedge Clk);
      Address<=32'd4;
	  WriteData<=32'd7;
	 @(posedge Clk);
      Address<=32'd8;
     WriteData<=32'd20;
     @(posedge Clk);
     Address<=32'd12;
     WriteData<=32'd25;
      #100;
	end

endmodule