data/full_repos/permissive/125520060/problem-1002-gate2/top.v
data/verilator_xmls/abdca8c8-4d2c-4c4b-a55d-4523df495ff5.xml
module gate2(
    a
   ,b
   ,z
);

input           a, b;
output  [5:0]   z;

assign  z[5] =   a & b ;
assign  z[4] = ~(a & b);
assign  z[3] =   a | b ;
assign  z[2] = ~(a | b);
assign  z[1] =   a ^ b ;
assign  z[0] = ~(a ^ b);

endmodule
module gate2(
    a
   ,b
   ,z
);


input           a, b;
output  [5:0]   z;

assign  z[5] =   a & b ;
assign  z[4] = ~(a & b);
assign  z[3] =   a | b ;
assign  z[2] = ~(a | b);
assign  z[1] =   a ^ b ;
assign  z[0] = ~(a ^ b);

endmodule