data/full_repos/permissive/121592400/tb_learnCosts.v
 line:434: before: "#"
1: b'%Error: data/full_repos/permissive/121592400/tb_learnCosts.v:7: Cannot find include file: learnCosts.v\n`include "learnCosts.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/121592400,data/full_repos/permissive/121592400/learnCosts.v\n             data/full_repos/permissive/121592400,data/full_repos/permissive/121592400/learnCosts.v.v\n             data/full_repos/permissive/121592400,data/full_repos/permissive/121592400/learnCosts.v.sv\n             learnCosts.v\n             learnCosts.v.v\n             learnCosts.v.sv\n             obj_dir/learnCosts.v\n             obj_dir/learnCosts.v.v\n             obj_dir/learnCosts.v.sv\n%Error: data/full_repos/permissive/121592400/tb_learnCosts.v:8: Cannot find include file: memory.v\n`include "memory.v" \n         ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_learnCosts.v:43: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clock = ~clock;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_learnCosts.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #5 nrst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_learnCosts.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #10 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_learnCosts.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_learnCosts.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_learnCosts.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_learnCosts.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #450\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_learnCosts.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_learnCosts.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: data/full_repos/permissive/121592400/tb_learnCosts.v:67: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_learnCosts.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/121592400/tb_learnCosts.v:68: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_learnCosts);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_learnCosts.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #1200\n        ^\n%Error: Exiting due to 4 error(s), 10 warning(s)\n'
module tb_learnCosts();
	reg clock, nrst, en;


	wire wr_en;
	wire [`WORD_WIDTH-1:0] mem_data_in, mem_data_out;
    wire [10:0] address;
	mem mem1(clock, address, wr_en, mem_data_in, mem_data_out);


	reg [`WORD_WIDTH-1:0] fsourceID, fbatteryStat, fValue, fclusterID, initial_epsilon;
	wire reinit, done;
	learnCosts lc1(clock, nrst, en, fsourceID, fbatteryStat, fValue, fclusterID, initial_epsilon, address, wr_en, mem_data_out, mem_data_in, done);

    initial begin




        fsourceID = 31;
        fbatteryStat = 5;
        fValue = 10;
        fclusterID = 11;
        initial_epsilon = 1;
    end


    initial begin
        clock = 0;
        forever #10 clock = ~clock;
    end


    initial begin
        en = 0;
        nrst = 1;
        #5 nrst = 0;
        #10 
        nrst = 1;
        #50
        en = 1;
        #20
        en = 0;
        #50
        #450
        #50
        en = 1;
        #20
        en = 0;
        
    end

    initial begin
        $dumpfile("tb_learnCosts.vcd");
        $dumpvars(0, tb_learnCosts);
        #1200
        $finish; 
    end
endmodule
module tb_learnCosts();

	reg clock, nrst, en;


	wire wr_en;
	wire [`WORD_WIDTH-1:0] mem_data_in, mem_data_out;
    wire [10:0] address;
	mem mem1(clock, address, wr_en, mem_data_in, mem_data_out);


	reg [`WORD_WIDTH-1:0] fsourceID, fbatteryStat, fValue, fclusterID, initial_epsilon;
	wire reinit, done;
	learnCosts lc1(clock, nrst, en, fsourceID, fbatteryStat, fValue, fclusterID, initial_epsilon, address, wr_en, mem_data_out, mem_data_in, done);

    initial begin




        fsourceID = 31;
        fbatteryStat = 5;
        fValue = 10;
        fclusterID = 11;
        initial_epsilon = 1;
    end


    initial begin
        clock = 0;
        forever #10 clock = ~clock;
    end


    initial begin
        en = 0;
        nrst = 1;
        #5 nrst = 0;
        #10 
        nrst = 1;
        #50
        en = 1;
        #20
        en = 0;
        #50
        #450
        #50
        en = 1;
        #20
        en = 0;
        
    end

    initial begin
        $dumpfile("tb_learnCosts.vcd");
        $dumpvars(0, tb_learnCosts);
        #1200
        $finish; 
    end
endmodule