data/full_repos/permissive/2084115/projects/kv260_sample/rtl/kv260_sample.sv
 line:22 column:35: Illegal character "'"
1: b"%Error: data/full_repos/permissive/2084115/projects/kv260_sample/rtl/kv260_sample.sv:16: Cannot find file containing module: 'design_1'\n    design_1\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/projects/kv260_sample/rtl,data/full_repos/permissive/2084115/design_1\n             data/full_repos/permissive/2084115/projects/kv260_sample/rtl,data/full_repos/permissive/2084115/design_1.v\n             data/full_repos/permissive/2084115/projects/kv260_sample/rtl,data/full_repos/permissive/2084115/design_1.sv\n             design_1\n             design_1.v\n             design_1.sv\n             obj_dir/design_1\n             obj_dir/design_1.v\n             obj_dir/design_1.sv\n%Error: Exiting due to 1 error(s)\n"
module kv260_sample
            (
                output  wire    [7:0]   pmod
            );
    

    wire            clk;

    design_1
        i_design_1
            (
                .pl_clk     (clk)
            );
    
    logic   [27:0]     counter = '0;
    always_ff @(posedge clk) begin
        counter <= counter + 1'b1;
    end

    assign pmod[3:0] = counter[11:8];
    assign pmod[7:4] = counter[27:24];
    
endmodule
module kv260_sample
            (
                output  wire    [7:0]   pmod
            );

    

    wire            clk;

    design_1
        i_design_1
            (
                .pl_clk     (clk)
            );
    
    logic   [27:0]     counter = '0;
    always_ff @(posedge clk) begin
        counter <= counter + 1'b1;
    end

    assign pmod[3:0] = counter[11:8];
    assign pmod[7:4] = counter[27:24];
    
endmodule