data/full_repos/permissive/174783592/IFU/IFU.sv
1: b'%Error: data/full_repos/permissive/174783592/IFU/IFU.sv:3: Cannot find include file: sum16bit.sv\n`include "sum16bit.sv" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174783592/IFU,data/full_repos/permissive/174783592/sum16bit.sv\n             data/full_repos/permissive/174783592/IFU,data/full_repos/permissive/174783592/sum16bit.sv.v\n             data/full_repos/permissive/174783592/IFU,data/full_repos/permissive/174783592/sum16bit.sv.sv\n             sum16bit.sv\n             sum16bit.sv.v\n             sum16bit.sv.sv\n             obj_dir/sum16bit.sv\n             obj_dir/sum16bit.sv.v\n             obj_dir/sum16bit.sv.sv\n%Error: Exiting due to 1 error(s)\n'
module IFU(reset,clk,en,isr);
	
	input
	      reset,
	      clk,
	      en;
      	output reg [15:0]isr;

	 reg [15:0] pc;
	 reg [15:0]temp1;
	 reg [15:0] temp2;
	wire [16:0] pcwire;

	wire [15:0] imem [0:1023];


	sum16bit inc(pc,16'b1,2'b0,pcwire);

	always @(clk)
	begin

		if (reset)
		begin
			pc <= {4{4'b0000}};
			

		end


			if (en && ~reset)
			begin

			


			isr <= imem[pc[9:0]];


			pc <=pcwire;

		end
	end	

endmodule
module IFU(reset,clk,en,isr);

	
	input
	      reset,
	      clk,
	      en;
      	output reg [15:0]isr;

	 reg [15:0] pc;
	 reg [15:0]temp1;
	 reg [15:0] temp2;
	wire [16:0] pcwire;

	wire [15:0] imem [0:1023];


	sum16bit inc(pc,16'b1,2'b0,pcwire);

	always @(clk)
	begin

		if (reset)
		begin
			pc <= {4{4'b0000}};
			

		end


			if (en && ~reset)
			begin

			


			isr <= imem[pc[9:0]];


			pc <=pcwire;

		end
	end	

endmodule