data/full_repos/permissive/115035459/verilog/src/lib/edge_to_pulse.v
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data/verilator_xmls/08ee9971-e836-4154-82ab-5759bfc204c9.xml
module edge_to_pulse #(
	parameter polarity = 1
) (
	input clock,
	input i,
	output reg o = 0
);

	reg state = 0;
	always @(posedge clock) begin
		o <= ~polarity;
		if (i==polarity) begin
			if (state!=polarity) begin
				o <= polarity;
				state <= polarity;
			end
		end else begin
			state <= ~polarity;
		end
	end
endmodule
module edge_to_pulse #(
	parameter polarity = 1
) (
	input clock,
	input i,
	output reg o = 0
);


	reg state = 0;
	always @(posedge clock) begin
		o <= ~polarity;
		if (i==polarity) begin
			if (state!=polarity) begin
				o <= polarity;
				state <= polarity;
			end
		end else begin
			state <= ~polarity;
		end
	end
endmodule