data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/rfnoc/moving_sum/moving_sum_tb.v
 line:26: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/rfnoc/moving_sum/moving_sum_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n     #100 clk = ~clk;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/rfnoc/moving_sum/moving_sum_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 reset = 0;\n           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/rfnoc/moving_sum/moving_sum_tb.v:23: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("moving_sum_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/rfnoc/moving_sum/moving_sum_tb.v:24: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,moving_sum_tb);\n           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/rfnoc/moving_sum/moving_sum_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000000 $finish;\n           ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module moving_sum_tb();
   

   
   localparam STR_SINK_FIFOSIZE = 9;
      
   reg clk, reset;
   always
     #100 clk = ~clk;

   initial clk = 0;
   initial reset = 1;
   initial #1000 reset = 0;
   
   initial $dumpfile("moving_sum_tb.vcd");
   initial $dumpvars(0,moving_sum_tb);

   initial #1000000 $finish;

   wire [15:0] i_tdata;
   wire [25:0] o_tdata;
   wire        i_tvalid, i_tready, o_tvalid, o_tready;
   
   moving_sum #(.MAX_LEN_LOG2(10), .WIDTH(16)) moving_sum
     (.clk(clk), .reset(reset), .clear(0),
      .len(20),
      .i_tdata(i_tdata), .i_tlast(), .i_tvalid(i_tvalid), .i_tready(i_tready),
      .o_tdata(o_tdata), .o_tlast(), .o_tvalid(o_tvalid), .o_tready(o_tready));

   assign i_tdata = 1;
   assign i_tvalid = 1;
   assign o_tready = 1;
   
      
endmodule
module moving_sum_tb();

   

   
   localparam STR_SINK_FIFOSIZE = 9;
      
   reg clk, reset;
   always
     #100 clk = ~clk;

   initial clk = 0;
   initial reset = 1;
   initial #1000 reset = 0;
   
   initial $dumpfile("moving_sum_tb.vcd");
   initial $dumpvars(0,moving_sum_tb);

   initial #1000000 $finish;

   wire [15:0] i_tdata;
   wire [25:0] o_tdata;
   wire        i_tvalid, i_tready, o_tvalid, o_tready;
   
   moving_sum #(.MAX_LEN_LOG2(10), .WIDTH(16)) moving_sum
     (.clk(clk), .reset(reset), .clear(0),
      .len(20),
      .i_tdata(i_tdata), .i_tlast(), .i_tvalid(i_tvalid), .i_tready(i_tready),
      .o_tdata(o_tdata), .o_tlast(), .o_tvalid(o_tvalid), .o_tready(o_tready));

   assign i_tdata = 1;
   assign i_tvalid = 1;
   assign o_tready = 1;
   
      
endmodule