data/full_repos/permissive/136510272/projects/01_tiny_videoadapter/vga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/01_tiny_videoadapter/vga.v:36: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance vga\nreg [9:0] x = 1\'b0;  \n              ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/01_tiny_videoadapter/vga.v:37: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance vga\nreg [9:0] y = 1\'b0;\n              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/01_tiny_videoadapter/vga.v:51: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance vga\n    x <= x == (horiz_whole - 1) ? 1\'b0 : (x + 1\'b1);\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/01_tiny_videoadapter/vga.v:57: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance vga\n        y <= y == (vert_whole - 1) ? 1\'b0 : (y + 1\'b1);\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/01_tiny_videoadapter/vga.v:73: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance vga\n        red   <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/01_tiny_videoadapter/vga.v:74: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance vga\n        green <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/01_tiny_videoadapter/vga.v:75: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance vga\n        blue  <= 1\'b0;\n              ^~\n%Error: Exiting due to 7 warning(s)\n'
module vga(


    input   wire        clk,


    output  reg  [4:0]  red,
    output  reg  [5:0]  green,
    output  reg  [4:0]  blue,
    output  wire        hs,
    output  wire        vs

);



parameter horiz_visible = 640;
parameter horiz_back    = 48;
parameter horiz_sync    = 96;
parameter horiz_front   = 16;
parameter horiz_whole   = 800;



parameter vert_visible = 480;
parameter vert_back    = 33;
parameter vert_sync    = 2;
parameter vert_front   = 10;
parameter vert_whole   = 525;


assign hs = x >= (horiz_visible + horiz_front) && x < (horiz_visible + horiz_front + horiz_sync);
assign vs = y >= (vert_visible  + vert_front)  && y < (vert_visible  + vert_front  + vert_sync);


reg [9:0] x = 1'b0;
reg [9:0] y = 1'b0;


reg [1:0] clock_divider;


always @(posedge clk) clock_divider <= clock_divider + 1'b1;



always @(posedge clock_divider[1]) begin



    x <= x == (horiz_whole - 1) ? 1'b0 : (x + 1'b1);
    

    if (x == (horiz_whole - 1)) begin
    

        y <= y == (vert_whole - 1) ? 1'b0 : (y + 1'b1);

    end
    

    if (x < horiz_visible && y < vert_visible) begin
    

        red   <= x[4:0] ^ y[4:0];
        green <= x[5:0] ^ y[5:0];
        blue  <= x[4:0] ^ y[4:0];
    


    end else begin
    
        red   <= 1'b0;
        green <= 1'b0;
        blue  <= 1'b0;
    
    end

end

endmodule
module vga(


    input   wire        clk,


    output  reg  [4:0]  red,
    output  reg  [5:0]  green,
    output  reg  [4:0]  blue,
    output  wire        hs,
    output  wire        vs

);




parameter horiz_visible = 640;
parameter horiz_back    = 48;
parameter horiz_sync    = 96;
parameter horiz_front   = 16;
parameter horiz_whole   = 800;



parameter vert_visible = 480;
parameter vert_back    = 33;
parameter vert_sync    = 2;
parameter vert_front   = 10;
parameter vert_whole   = 525;


assign hs = x >= (horiz_visible + horiz_front) && x < (horiz_visible + horiz_front + horiz_sync);
assign vs = y >= (vert_visible  + vert_front)  && y < (vert_visible  + vert_front  + vert_sync);


reg [9:0] x = 1'b0;
reg [9:0] y = 1'b0;


reg [1:0] clock_divider;


always @(posedge clk) clock_divider <= clock_divider + 1'b1;



always @(posedge clock_divider[1]) begin



    x <= x == (horiz_whole - 1) ? 1'b0 : (x + 1'b1);
    

    if (x == (horiz_whole - 1)) begin
    

        y <= y == (vert_whole - 1) ? 1'b0 : (y + 1'b1);

    end
    

    if (x < horiz_visible && y < vert_visible) begin
    

        red   <= x[4:0] ^ y[4:0];
        green <= x[5:0] ^ y[5:0];
        blue  <= x[4:0] ^ y[4:0];
    


    end else begin
    
        red   <= 1'b0;
        green <= 1'b0;
        blue  <= 1'b0;
    
    end

end

endmodule