data/full_repos/permissive/118895561/Project 1/grf.v
1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561.sv\n             1,data/full_repos/permissive/118895561\n             1,data/full_repos/permissive/118895561.v\n             1,data/full_repos/permissive/118895561.sv\n             obj_dir/1,data/full_repos/permissive/118895561\n             obj_dir/1,data/full_repos/permissive/118895561.v\n             obj_dir/1,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 1/grf.v\n%Error: Exiting due to 3 error(s)\n'
module grf(PC, Read_1, Read_2, Write_Dst, Read_Data_1, Read_Data_2, WriteData, WriteEnabled, clk, rst);
	 input  [31:0] PC;
	 input  [4:0]  Read_1;
    input  [4:0]  Read_2;
    input  [4:0]  Write_Dst;
    output [31:0] Read_Data_1;  
    output [31:0] Read_Data_2;
	 input  [31:0] WriteData;
	 input  WriteEnabled;             
	 input  clk;
    input  rst;
	
	reg [31:0] GPR[31:0];
	
	assign Read_Data_1 = (WriteEnabled & Read_1 == Write_Dst & Write_Dst != 0) ? WriteData	 :
																										  GPR[Read_1];
	assign Read_Data_2 = (WriteEnabled & Read_2 == Write_Dst & Write_Dst != 0) ? WriteData	 :
																										  GPR[Read_2];

	integer i;
	
	initial begin 
		for(i = 0 ; i < 32 ; i = i + 1)
			GPR[i] = 0;
	end
	
	always @(posedge clk) begin
			if(rst == 1) begin
				for(i = 0; i <32; i = i + 1) begin
					case(i)
						28 		:	GPR[i] <= 32'h0000_1800;
						29 		:	GPR[i] <= 32'h0000_2ffc;
						default  :	GPR[i] <= 32'b0;
					endcase
				 end
				end
			else if(WriteEnabled) begin
            $display("%d@%h: $%d <= %h", $time, PC, Write_Dst, WriteData);
				if(Write_Dst != 0)
					GPR[Write_Dst] <= WriteData;
			end



	end

endmodule
module grf(PC, Read_1, Read_2, Write_Dst, Read_Data_1, Read_Data_2, WriteData, WriteEnabled, clk, rst);

	 input  [31:0] PC;
	 input  [4:0]  Read_1;
    input  [4:0]  Read_2;
    input  [4:0]  Write_Dst;
    output [31:0] Read_Data_1;  
    output [31:0] Read_Data_2;
	 input  [31:0] WriteData;
	 input  WriteEnabled;             
	 input  clk;
    input  rst;
	
	reg [31:0] GPR[31:0];
	
	assign Read_Data_1 = (WriteEnabled & Read_1 == Write_Dst & Write_Dst != 0) ? WriteData	 :
																										  GPR[Read_1];
	assign Read_Data_2 = (WriteEnabled & Read_2 == Write_Dst & Write_Dst != 0) ? WriteData	 :
																										  GPR[Read_2];

	integer i;
	
	initial begin 
		for(i = 0 ; i < 32 ; i = i + 1)
			GPR[i] = 0;
	end
	
	always @(posedge clk) begin
			if(rst == 1) begin
				for(i = 0; i <32; i = i + 1) begin
					case(i)
						28 		:	GPR[i] <= 32'h0000_1800;
						29 		:	GPR[i] <= 32'h0000_2ffc;
						default  :	GPR[i] <= 32'b0;
					endcase
				 end
				end
			else if(WriteEnabled) begin
            $display("%d@%h: $%d <= %h", $time, PC, Write_Dst, WriteData);
				if(Write_Dst != 0)
					GPR[Write_Dst] <= WriteData;
			end



	end

endmodule