data/full_repos/permissive/139767240/IntelReferenceDesign/single_port_ram.v
data/verilator_xmls/d9dd94e6-59c6-4a30-9010-f47d0b5c0a5f.xml
module single_port_ram
(
	input [7:0] data,
	input [5:0] addr,
	input we, clk,
	output [7:0] q
);


	reg [7:0] ram[63:0];
	

	reg [5:0] addr_reg;
	
	always @ (posedge clk)
	begin

		if (we)
			ram[addr] <= data;
		
		addr_reg <= addr;
		
	end
		



	assign q = ram[addr_reg];
	
endmodule
module single_port_ram
(
	input [7:0] data,
	input [5:0] addr,
	input we, clk,
	output [7:0] q
);



	reg [7:0] ram[63:0];
	

	reg [5:0] addr_reg;
	
	always @ (posedge clk)
	begin

		if (we)
			ram[addr] <= data;
		
		addr_reg <= addr;
		
	end
		



	assign q = ram[addr_reg];
	
endmodule