data/full_repos/permissive/20688874/coding_theory/decodertb.v
 line:41: before: "function"
1: b'%Error: data/full_repos/permissive/20688874/coding_theory/decodertb.v:23: Cannot find include file: decoder.v\n`include "decoder.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/coding_theory,data/full_repos/permissive/20688874/decoder.v\n             data/full_repos/permissive/20688874/coding_theory,data/full_repos/permissive/20688874/decoder.v.v\n             data/full_repos/permissive/20688874/coding_theory,data/full_repos/permissive/20688874/decoder.v.sv\n             decoder.v\n             decoder.v.v\n             decoder.v.sv\n             obj_dir/decoder.v\n             obj_dir/decoder.v.v\n             obj_dir/decoder.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/decodertb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/decodertb.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/decodertb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/decodertb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/decodertb.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module tb_decoder();

	

	wire [10:0] qout;
	

	reg [14:0] cin;
	
	
	

	ham_15_11_decoder dec (


		cin,qout);
	

	

	initial
	begin

		$display(" << Starting the simulation >>");
		cin = 15'b110101100000011;
		$display(cin[1]," << b1 b2 >>",cin[2]);
		$display(cin[3]," << b1 b2 >>",cin[4]);
		

		#1;
		cin = 15'b111000111000011;
		
		
		#1;
		cin = 15'b110011101010011;
		
				
		#1;
		cin = 15'b111101110010011;
		
		#1;
		cin = 15'b111110000100011;
		
				
		#20;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_decoder();


	

	wire [10:0] qout;
	

	reg [14:0] cin;
	
	
	

	ham_15_11_decoder dec (


		cin,qout);
	

	

	initial
	begin

		$display(" << Starting the simulation >>");
		cin = 15'b110101100000011;
		$display(cin[1]," << b1 b2 >>",cin[2]);
		$display(cin[3]," << b1 b2 >>",cin[4]);
		

		#1;
		cin = 15'b111000111000011;
		
		
		#1;
		cin = 15'b110011101010011;
		
				
		#1;
		cin = 15'b111101110010011;
		
		#1;
		cin = 15'b111110000100011;
		
				
		#20;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule