data/full_repos/permissive/210250459/src/reg.v
 line:21: before: "addr0"
data/verilator_xmls/d655216c-7aa0-43d8-bea1-57433b29dfcd.xml
module Register(out0, out1, wrt_sig, addr0, addr1, addr_wrt, in, clk);

output [31:0] out0, out1;
input wrt_sig, clk;
input [4:0] addr0, addr1, addr_wrt;
input [31:0] in;

reg [31:0] regfile[31:0];

initial
begin
    regfile[0] = 0;
end

assign out0 = regfile[addr0];
assign out1 = regfile[addr1];

always @(posedge clk, addr0) begin
    if (wrt_sig && addr_wrt > 0) regfile[addr_wrt] = in;
    $display($time, " [2 Register] wrt_sig = %d addr_wrt = %d in = %d", wrt_sig, addr_wrt, regfile[addr_wrt]);
    $display($time, " [2 Register] addr0 = %d out0 = %d", addr0, out0);
end

endmodule
module Register(out0, out1, wrt_sig, addr0, addr1, addr_wrt, in, clk);


output [31:0] out0, out1;
input wrt_sig, clk;
input [4:0] addr0, addr1, addr_wrt;
input [31:0] in;

reg [31:0] regfile[31:0];

initial
begin
    regfile[0] = 0;
end

assign out0 = regfile[addr0];
assign out1 = regfile[addr1];

always @(posedge clk, addr0) begin
    if (wrt_sig && addr_wrt > 0) regfile[addr_wrt] = in;
    $display($time, " [2 Register] wrt_sig = %d addr_wrt = %d in = %d", wrt_sig, addr_wrt, regfile[addr_wrt]);
    $display($time, " [2 Register] addr0 = %d out0 = %d", addr0, out0);
end

endmodule