data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/SW_IP_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/SW_IP_test.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #(10) reset =1\'b1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/SW_IP_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #(10) reset =1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/SW_IP_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk=~clk;\n  ^\n%Error: data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/SW_IP_test.v:64: Cannot find file containing module: \'SW_IP\'\n SW_IP #(DATA_WIDTH, 4\'b0101, 1, FREQ) SW0101 (.dataInE(dataInE),.dataInW(dataInW),.dataInS(dataInS),.dataInN(dataInN),\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim,data/full_repos/permissive/163602545/SW_IP\n             data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim,data/full_repos/permissive/163602545/SW_IP.v\n             data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim,data/full_repos/permissive/163602545/SW_IP.sv\n             SW_IP\n             SW_IP.v\n             SW_IP.sv\n             obj_dir/SW_IP\n             obj_dir/SW_IP.v\n             obj_dir/SW_IP.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SW_IP_test
   #(  parameter DATA_WIDTH = 37,
       parameter FREQ = 4 
   

    )
();

reg clk;
reg reset;

initial 
begin 
  $display("Start simulation at %t",$time); 
  clk=0;
  reset=0;
  #(10) reset =1'b1;
  #(10) reset =1'b0;
end
always
begin
  #1 clk=~clk;
end


wire [DATA_WIDTH-1 : 0] dataInE, dataInW, dataInS, dataInN;
wire [DATA_WIDTH-1 : 0] dataOutE, dataOutW, dataOutS, dataOutN;
wire  Inr_N, Inr_E, Inr_S, Inr_W;
wire  Inw_N, Inw_E, Inw_S, Inw_W;
wire  Outr_N, Outr_E, Outr_S, Outr_W;
wire  Outw_N, Outw_E, Outw_S, Outw_W;

assign Inr_N=1'b0;
assign Inr_E=1'b0;
assign Inr_W=1'b0;
assign Inr_S=1'b0;
assign Inw_N=1'b0;
assign Inw_E=1'b0;
assign Inw_W=1'b0;
assign Inw_S=1'b0;
assign Outr_N=1'b0;
assign Outr_E=1'b0;
assign Outr_W=1'b0;
assign Outr_S=1'b0;
assign Outw_N=1'b0;
assign Outw_E=1'b0;
assign Outw_W=1'b0;
assign Outw_S=1'b0;

SW_IP #(DATA_WIDTH, 4'b0101, 1, FREQ) SW0101 (.dataInE(dataInE),.dataInW(dataInW),.dataInS(dataInS),.dataInN(dataInN),
                                     .dataOutE(dataOutE),.dataOutW(dataOutW),.dataOutS(dataOutS),.dataOutN(dataOutN),
                                     .Inr_N(Inr_N),.Inr_E(Inr_E),.Inr_S(Inr_S),.Inr_W(Inr_W),
                                     .Inw_N(Inw_N),.Inw_E(Inw_E),.Inw_S(Inw_S),.Inw_W(Inw_W),
                                     .Outr_N(Outr_N),.Outr_E(Outr_E),.Outr_S(Outr_S),.Outr_W(Outr_W),
                                     .Outw_N(Outw_N),.Outw_E(Outw_E),.Outw_S(Outw_S),.Outw_W(Outw_W),
                                     .clk(clk),.reset(reset));                     













                                                                                                      

endmodule
module SW_IP_test
   #(  parameter DATA_WIDTH = 37,
       parameter FREQ = 4 
   

    )
();


reg clk;
reg reset;

initial 
begin 
  $display("Start simulation at %t",$time); 
  clk=0;
  reset=0;
  #(10) reset =1'b1;
  #(10) reset =1'b0;
end
always
begin
  #1 clk=~clk;
end


wire [DATA_WIDTH-1 : 0] dataInE, dataInW, dataInS, dataInN;
wire [DATA_WIDTH-1 : 0] dataOutE, dataOutW, dataOutS, dataOutN;
wire  Inr_N, Inr_E, Inr_S, Inr_W;
wire  Inw_N, Inw_E, Inw_S, Inw_W;
wire  Outr_N, Outr_E, Outr_S, Outr_W;
wire  Outw_N, Outw_E, Outw_S, Outw_W;

assign Inr_N=1'b0;
assign Inr_E=1'b0;
assign Inr_W=1'b0;
assign Inr_S=1'b0;
assign Inw_N=1'b0;
assign Inw_E=1'b0;
assign Inw_W=1'b0;
assign Inw_S=1'b0;
assign Outr_N=1'b0;
assign Outr_E=1'b0;
assign Outr_W=1'b0;
assign Outr_S=1'b0;
assign Outw_N=1'b0;
assign Outw_E=1'b0;
assign Outw_W=1'b0;
assign Outw_S=1'b0;

SW_IP #(DATA_WIDTH, 4'b0101, 1, FREQ) SW0101 (.dataInE(dataInE),.dataInW(dataInW),.dataInS(dataInS),.dataInN(dataInN),
                                     .dataOutE(dataOutE),.dataOutW(dataOutW),.dataOutS(dataOutS),.dataOutN(dataOutN),
                                     .Inr_N(Inr_N),.Inr_E(Inr_E),.Inr_S(Inr_S),.Inr_W(Inr_W),
                                     .Inw_N(Inw_N),.Inw_E(Inw_E),.Inw_S(Inw_S),.Inw_W(Inw_W),
                                     .Outr_N(Outr_N),.Outr_E(Outr_E),.Outr_S(Outr_S),.Outr_W(Outr_W),
                                     .Outw_N(Outw_N),.Outw_E(Outw_E),.Outw_S(Outw_S),.Outw_W(Outw_W),
                                     .clk(clk),.reset(reset));                     













                                                                                                      

endmodule