data/full_repos/permissive/143278/ivltests/genvar_scopes.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/genvar_scopes.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module genvar_scopes();





genvar  i;
genvar  j;

reg  [1:0] a[1:0];
wire [1:0] b[1:0];
wire [1:0] c[1:0];
wire [1:0] d[1:0];

for (i = 0; i < 2; i = i + 1) begin
  for (j = 0; j < 2; j = j + 1) begin
    assign b[i][j] = a[i][j];
  end
end

for (i = 0; i < 2; i = i + 1) begin
  genvar j;
  for (j = 0; j < 2; j = j + 1) begin
    assign c[i][j] = a[i][j];
  end
end

for (j = 0; j < 2; j = j + 1) begin
  genvar k;
  for (k = 0; k < 2; k = k + 1) begin
    assign d[j][k] = a[j][k];
  end
end

initial begin
  a[0] = 2'b01;
  a[1] = 2'b10;
  #1;
  $display("%b %b", b[0], b[1]);
  $display("%b %b", c[0], c[1]);
  $display("%b %b", d[0], d[1]);
  if ((b[0] === 2'b01) && (b[1] === 2'b10)
   && (c[0] === 2'b01) && (c[1] === 2'b10)
   && (d[0] === 2'b01) && (d[1] === 2'b10))
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module genvar_scopes();






genvar  i;
genvar  j;

reg  [1:0] a[1:0];
wire [1:0] b[1:0];
wire [1:0] c[1:0];
wire [1:0] d[1:0];

for (i = 0; i < 2; i = i + 1) begin
  for (j = 0; j < 2; j = j + 1) begin
    assign b[i][j] = a[i][j];
  end
end

for (i = 0; i < 2; i = i + 1) begin
  genvar j;
  for (j = 0; j < 2; j = j + 1) begin
    assign c[i][j] = a[i][j];
  end
end

for (j = 0; j < 2; j = j + 1) begin
  genvar k;
  for (k = 0; k < 2; k = k + 1) begin
    assign d[j][k] = a[j][k];
  end
end

initial begin
  a[0] = 2'b01;
  a[1] = 2'b10;
  #1;
  $display("%b %b", b[0], b[1]);
  $display("%b %b", c[0], c[1]);
  $display("%b %b", d[0], d[1]);
  if ((b[0] === 2'b01) && (b[1] === 2'b10)
   && (c[0] === 2'b01) && (c[1] === 2'b10)
   && (d[0] === 2'b01) && (d[1] === 2'b10))
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule