data/full_repos/permissive/150329835/src/Arithmetic.v
1: b"%Error: data/full_repos/permissive/150329835/src/Arithmetic.v:16: Cannot find file containing module: 'MULTIPLEXER'\n MULTIPLEXER M3(OP,W[39:30],W[29:20],W[19:10],W[9:0],F);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150329835/src,data/full_repos/permissive/150329835/MULTIPLEXER\n             data/full_repos/permissive/150329835/src,data/full_repos/permissive/150329835/MULTIPLEXER.v\n             data/full_repos/permissive/150329835/src,data/full_repos/permissive/150329835/MULTIPLEXER.sv\n             MULTIPLEXER\n             MULTIPLEXER.v\n             MULTIPLEXER.sv\n             obj_dir/MULTIPLEXER\n             obj_dir/MULTIPLEXER.v\n             obj_dir/MULTIPLEXER.sv\n%Error: Exiting due to 1 error(s)\n"
module ADD(A, B, sum);
	parameter n = 4;
	input [n-1:0] A,B;
	output [9:0] sum;
	wire [n:0] C;
	
	genvar i;

	assign C[0] = 0;
	
	generate
		for (i = 0; i < n; i = i+1)
		begin:addbit
			full_add stage(A[i],B[i],C[i],sum[i],C[i+1]);
		end
	endgenerate
	
	assign sum[n] = C[n];
	assign sum[8:5] = 4'b0000;
	assign sum[9] = C[n];
endmodule
module ADD(A, B, sum);

	parameter n = 4;
	input [n-1:0] A,B;
	output [9:0] sum;
	wire [n:0] C;
	
	genvar i;

	assign C[0] = 0;
	
	generate
		for (i = 0; i < n; i = i+1)
		begin:addbit
			full_add stage(A[i],B[i],C[i],sum[i],C[i+1]);
		end
	endgenerate
	
	assign sum[n] = C[n];
	assign sum[8:5] = 4'b0000;
	assign sum[9] = C[n];
endmodule