data/full_repos/permissive/143278/ivltests/test_gxor.v
 line:7: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_gxor.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #T;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_gxor.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_gxor.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #S;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_gxor.v:14: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                         : ... In instance test.stim\n    a = $random % MAX ;\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/test_gxor.v:50: Cannot find file containing module: \'gxor_reduce\'\n  gxor_reduce  #(HW)   duv   (.a(a), .ar(y));\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/gxor_reduce\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/gxor_reduce.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/gxor_reduce.sv\n             gxor_reduce\n             gxor_reduce.v\n             gxor_reduce.sv\n             obj_dir/gxor_reduce\n             obj_dir/gxor_reduce.v\n             obj_dir/gxor_reduce.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  parameter M = 200;
  parameter T = 10;
  parameter HW = 4;
  parameter S = M*T + 40;

  wire [2*HW-1:0] a;
  wire y;

  stimulus #(HW, T, M) stim  (.a(a));
  gxor_reduce  #(HW)   duv   (.a(a), .ar(y));
  check                check (.x(a), .y(y) );

  initial begin
    #S;
    $display("PASSED");
    $finish;
  end

endmodule
module test;

  parameter M = 200;
  parameter T = 10;
  parameter HW = 4;
  parameter S = M*T + 40;

  wire [2*HW-1:0] a;
  wire y;

  stimulus #(HW, T, M) stim  (.a(a));
  gxor_reduce  #(HW)   duv   (.a(a), .ar(y));
  check                check (.x(a), .y(y) );

  initial begin
    #S;
    $display("PASSED");
    $finish;
  end

endmodule