data/full_repos/permissive/158077025/cnn_accelerator_tb.v
 line:54: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/158077025/cnn_accelerator_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158077025/cnn_accelerator_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n # 35 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/158077025/cnn_accelerator_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n # 10 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/158077025/cnn_accelerator_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n # 60 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/158077025/cnn_accelerator_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n # 4   \n ^\n%Warning-STMTDLY: data/full_repos/permissive/158077025/cnn_accelerator_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n # 40\n ^\n%Error: data/full_repos/permissive/158077025/cnn_accelerator_tb.v:28: Cannot find file containing module: \'cnn_accelerator\'\ncnn_accelerator cnn_accelerator_0(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158077025,data/full_repos/permissive/158077025/cnn_accelerator\n             data/full_repos/permissive/158077025,data/full_repos/permissive/158077025/cnn_accelerator.v\n             data/full_repos/permissive/158077025,data/full_repos/permissive/158077025/cnn_accelerator.sv\n             cnn_accelerator\n             cnn_accelerator.v\n             cnn_accelerator.sv\n             obj_dir/cnn_accelerator\n             obj_dir/cnn_accelerator.v\n             obj_dir/cnn_accelerator.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cnn_accelerator_tb();


parameter INPUT_BIT_WIDTH           = 8;
parameter QUAD_DATA_BUS_BIT_WIDTH   = 32;
parameter OUTPUT_BIT_WIDTH          = 16+6+2+2;
parameter DATA_BUS_BIT_WIDTH        = 128;
parameter INI_DATA_BUS              = 128'h0;
parameter OUPUT_DATA_BUS_BIT_WIDTH  = 512;
parameter MEM_READ                  = 1'b1;
parameter MEM_WRITE                 = 1'b0;
parameter MEM_ADDRESS_BIT_WIDTH     = 8;
parameter INI_MEM_ADDRESS           = 8'h0;
parameter MEM_ADDRESS_ZERO          = 8'h0;
parameter MEM_ADDRESS_ONE           = 8'h1;
parameter MEM_ADDRESS_OFFSET_ONE    = 8'h1;

reg                               clk;
reg                               reset;
reg                               cpu_to_cnn;
reg  [DATA_BUS_BIT_WIDTH-1:0]     data_bus_i;
wire [OUPUT_DATA_BUS_BIT_WIDTH-1:0]     data_bus_o;
wire                              mem_read_en;
wire                              mem_write_en;
wire [MEM_ADDRESS_BIT_WIDTH-1:0]  mem_address_o;
wire                              cnn_to_cpu;

cnn_accelerator cnn_accelerator_0(
	.clk(clk),
	.reset(reset),
	.cpu_to_cnn(cpu_to_cnn),
	.data_bus_i(data_bus_i),
	.data_bus_o(data_bus_o),
	.mem_read_en(mem_read_en),
	.mem_write_en(mem_write_en),
	.mem_address_o(mem_address_o),
	.cnn_to_cpu(cnn_to_cpu)
);

initial begin
	clk = 1'b0;
	forever #20 clk = ~clk;
end

initial begin
	reset = 1'b0;
	# 35 reset = 1'b1;
	# 10 reset = 1'b0;
end

initial begin
	cpu_to_cnn = 1'b0;
	# 4
	# 60 
	cpu_to_cnn = 1'b1;
	# 40
	cpu_to_cnn = 1'b0;
end


































































































































































































































































always @(posedge clk) begin
	if (mem_read_en) begin
		case(mem_address_o)












			8'h0: data_bus_i <= 128'h0000_0000_001b_0007_0201_0051_0307_0301;
			8'h1: data_bus_i <= 128'hffff_ffff_ffff_0000_1111_1111_1111_0002;
			8'h00: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff23;
			8'h01: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff84;
			8'h02: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffd9;
			8'h03: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff82;
			8'h04: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffff;
			8'h05: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffa6;
			8'h06: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff8d;
			8'h07: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffde;
			8'h08: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff00;
			8'h09: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffad;
			8'h0a: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffd1;
			8'h0b: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff96;
			8'h0c: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff91;
			8'h0d: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff76;
			8'h0e: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff3b;
			8'h0f: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffcc;

			8'h10: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffcc;
			8'h11: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h12: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h13: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h14: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffd9;
			8'h15: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h16: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h17: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h18: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h19: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h1a: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h1b: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff1a;
			8'h1c: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_fff2;
			8'h1d: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h1e: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h1f: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h20: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h21: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h22: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h23: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h24: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h25: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff0d;
			8'h26: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h27: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h28: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;

			default: data_bus_i <= 128'h1111_1111_1111_1111_1111_1111_1111_1111;
		endcase
	end
end

















































































































































reg  [OUPUT_DATA_BUS_BIT_WIDTH-1:0]     data [8:0];
always @(posedge clk) begin
	if (mem_write_en) begin
		case(mem_address_o[3:0])
			4'h0: data[0] <= data_bus_o;
			4'h1: data[1] <= data_bus_o;
			4'h2: data[2] <= data_bus_o;
			4'h3: data[3] <= data_bus_o;
			4'h4: data[4] <= data_bus_o;
			4'h5: data[5] <= data_bus_o;
			4'h6: data[6] <= data_bus_o;
			4'h7: data[7] <= data_bus_o;
			4'h8: data[8] <= data_bus_o;
		endcase
	end
end

endmodule
module cnn_accelerator_tb();



parameter INPUT_BIT_WIDTH           = 8;
parameter QUAD_DATA_BUS_BIT_WIDTH   = 32;
parameter OUTPUT_BIT_WIDTH          = 16+6+2+2;
parameter DATA_BUS_BIT_WIDTH        = 128;
parameter INI_DATA_BUS              = 128'h0;
parameter OUPUT_DATA_BUS_BIT_WIDTH  = 512;
parameter MEM_READ                  = 1'b1;
parameter MEM_WRITE                 = 1'b0;
parameter MEM_ADDRESS_BIT_WIDTH     = 8;
parameter INI_MEM_ADDRESS           = 8'h0;
parameter MEM_ADDRESS_ZERO          = 8'h0;
parameter MEM_ADDRESS_ONE           = 8'h1;
parameter MEM_ADDRESS_OFFSET_ONE    = 8'h1;

reg                               clk;
reg                               reset;
reg                               cpu_to_cnn;
reg  [DATA_BUS_BIT_WIDTH-1:0]     data_bus_i;
wire [OUPUT_DATA_BUS_BIT_WIDTH-1:0]     data_bus_o;
wire                              mem_read_en;
wire                              mem_write_en;
wire [MEM_ADDRESS_BIT_WIDTH-1:0]  mem_address_o;
wire                              cnn_to_cpu;

cnn_accelerator cnn_accelerator_0(
	.clk(clk),
	.reset(reset),
	.cpu_to_cnn(cpu_to_cnn),
	.data_bus_i(data_bus_i),
	.data_bus_o(data_bus_o),
	.mem_read_en(mem_read_en),
	.mem_write_en(mem_write_en),
	.mem_address_o(mem_address_o),
	.cnn_to_cpu(cnn_to_cpu)
);

initial begin
	clk = 1'b0;
	forever #20 clk = ~clk;
end

initial begin
	reset = 1'b0;
	# 35 reset = 1'b1;
	# 10 reset = 1'b0;
end

initial begin
	cpu_to_cnn = 1'b0;
	# 4
	# 60 
	cpu_to_cnn = 1'b1;
	# 40
	cpu_to_cnn = 1'b0;
end


































































































































































































































































always @(posedge clk) begin
	if (mem_read_en) begin
		case(mem_address_o)












			8'h0: data_bus_i <= 128'h0000_0000_001b_0007_0201_0051_0307_0301;
			8'h1: data_bus_i <= 128'hffff_ffff_ffff_0000_1111_1111_1111_0002;
			8'h00: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff23;
			8'h01: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff84;
			8'h02: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffd9;
			8'h03: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff82;
			8'h04: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffff;
			8'h05: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffa6;
			8'h06: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff8d;
			8'h07: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffde;
			8'h08: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff00;
			8'h09: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffad;
			8'h0a: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffd1;
			8'h0b: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff96;
			8'h0c: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff91;
			8'h0d: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff76;
			8'h0e: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ff3b;
			8'h0f: data_bus_i <= 128'h0000_0000_0000_0000_0000_0000_0000_ffcc;

			8'h10: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffcc;
			8'h11: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h12: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h13: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h14: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffd9;
			8'h15: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h16: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h17: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h18: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h19: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h1a: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h1b: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff1a;
			8'h1c: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_fff2;
			8'h1d: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h1e: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h1f: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h20: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h21: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h22: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h23: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h24: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
			8'h25: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff0d;
			8'h26: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h27: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;
			8'h28: data_bus_i <= 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ff00;

			default: data_bus_i <= 128'h1111_1111_1111_1111_1111_1111_1111_1111;
		endcase
	end
end

















































































































































reg  [OUPUT_DATA_BUS_BIT_WIDTH-1:0]     data [8:0];
always @(posedge clk) begin
	if (mem_write_en) begin
		case(mem_address_o[3:0])
			4'h0: data[0] <= data_bus_o;
			4'h1: data[1] <= data_bus_o;
			4'h2: data[2] <= data_bus_o;
			4'h3: data[3] <= data_bus_o;
			4'h4: data[4] <= data_bus_o;
			4'h5: data[5] <= data_bus_o;
			4'h6: data[6] <= data_bus_o;
			4'h7: data[7] <= data_bus_o;
			4'h8: data[8] <= data_bus_o;
		endcase
	end
end

endmodule