data/full_repos/permissive/136197078/hardware/ip/nt_recv_interpackettime/hdl/nt_recv_interpackettime.v
data/verilator_xmls/28084664-5732-4077-b52d-69dc730b3066.xml
module nt_recv_interpackettime (

  input wire clk156,
  input wire rstn156,
  input wire rst_sw156,


  input wire [63:0]    s_axis_tdata,
  input wire [7:0]     s_axis_tkeep,
  input wire           s_axis_tvalid,
  input wire           s_axis_tlast,
  output wire          s_axis_tready,
  input wire [24:0]    s_axis_tuser,


  output reg [63:0]    m_axis_tdata,
  output reg [7:0]     m_axis_tkeep,
  output reg           m_axis_tvalid,
  output reg           m_axis_tlast,
  input wire           m_axis_tready,
  output reg [52:0]    m_axis_tuser
);


  assign s_axis_tready = m_axis_tready;


  reg [27:0] cntr_inter_packet_cycles;


  reg [27:0] inter_packet_cycles;



  reg axis_active;

  always @(posedge clk156) begin
    if (~rstn156 | rst_sw156) begin
      m_axis_tdata <= 64'b0;
      m_axis_tkeep <= 8'b0;
      m_axis_tvalid <= 1'b0;
      m_axis_tlast <= 1'b0;
      m_axis_tuser <= 53'b0;

      cntr_inter_packet_cycles <= 28'b0;
      inter_packet_cycles <= 28'b0;
      axis_active <= 1'b0;
    end else begin
      if (m_axis_tready) begin

        m_axis_tdata <= s_axis_tdata;
        m_axis_tkeep <= s_axis_tkeep;
        m_axis_tvalid <= s_axis_tvalid;
        m_axis_tlast <= s_axis_tlast;

        if (s_axis_tvalid & ~axis_active) begin


          inter_packet_cycles <= cntr_inter_packet_cycles + 28'b1;
          cntr_inter_packet_cycles <= 28'b0;



          if (s_axis_tlast) begin
            m_axis_tuser <= {cntr_inter_packet_cycles + 28'b1, s_axis_tuser};
          end else begin
            m_axis_tuser <= 53'b0;
          end
        end else begin


          inter_packet_cycles <= inter_packet_cycles;
          cntr_inter_packet_cycles <= cntr_inter_packet_cycles + 28'b1;



          if (s_axis_tlast) begin
            m_axis_tuser <= {inter_packet_cycles, s_axis_tuser};
          end else begin
            m_axis_tuser <= 53'b0;
          end
        end


        axis_active <= s_axis_tvalid ? ~s_axis_tlast : axis_active;
      end else begin

        m_axis_tdata <= m_axis_tdata;
        m_axis_tkeep <= m_axis_tkeep;
        m_axis_tvalid <= m_axis_tvalid;
        m_axis_tlast <= m_axis_tlast;
        m_axis_tuser <= m_axis_tuser;

        inter_packet_cycles <= inter_packet_cycles;
        cntr_inter_packet_cycles <= cntr_inter_packet_cycles + 28'b1;
      end
    end
  end

endmodule
module nt_recv_interpackettime (

  input wire clk156,
  input wire rstn156,
  input wire rst_sw156,


  input wire [63:0]    s_axis_tdata,
  input wire [7:0]     s_axis_tkeep,
  input wire           s_axis_tvalid,
  input wire           s_axis_tlast,
  output wire          s_axis_tready,
  input wire [24:0]    s_axis_tuser,


  output reg [63:0]    m_axis_tdata,
  output reg [7:0]     m_axis_tkeep,
  output reg           m_axis_tvalid,
  output reg           m_axis_tlast,
  input wire           m_axis_tready,
  output reg [52:0]    m_axis_tuser
);



  assign s_axis_tready = m_axis_tready;


  reg [27:0] cntr_inter_packet_cycles;


  reg [27:0] inter_packet_cycles;



  reg axis_active;

  always @(posedge clk156) begin
    if (~rstn156 | rst_sw156) begin
      m_axis_tdata <= 64'b0;
      m_axis_tkeep <= 8'b0;
      m_axis_tvalid <= 1'b0;
      m_axis_tlast <= 1'b0;
      m_axis_tuser <= 53'b0;

      cntr_inter_packet_cycles <= 28'b0;
      inter_packet_cycles <= 28'b0;
      axis_active <= 1'b0;
    end else begin
      if (m_axis_tready) begin

        m_axis_tdata <= s_axis_tdata;
        m_axis_tkeep <= s_axis_tkeep;
        m_axis_tvalid <= s_axis_tvalid;
        m_axis_tlast <= s_axis_tlast;

        if (s_axis_tvalid & ~axis_active) begin


          inter_packet_cycles <= cntr_inter_packet_cycles + 28'b1;
          cntr_inter_packet_cycles <= 28'b0;



          if (s_axis_tlast) begin
            m_axis_tuser <= {cntr_inter_packet_cycles + 28'b1, s_axis_tuser};
          end else begin
            m_axis_tuser <= 53'b0;
          end
        end else begin


          inter_packet_cycles <= inter_packet_cycles;
          cntr_inter_packet_cycles <= cntr_inter_packet_cycles + 28'b1;



          if (s_axis_tlast) begin
            m_axis_tuser <= {inter_packet_cycles, s_axis_tuser};
          end else begin
            m_axis_tuser <= 53'b0;
          end
        end


        axis_active <= s_axis_tvalid ? ~s_axis_tlast : axis_active;
      end else begin

        m_axis_tdata <= m_axis_tdata;
        m_axis_tkeep <= m_axis_tkeep;
        m_axis_tvalid <= m_axis_tvalid;
        m_axis_tlast <= m_axis_tlast;
        m_axis_tuser <= m_axis_tuser;

        inter_packet_cycles <= inter_packet_cycles;
        cntr_inter_packet_cycles <= cntr_inter_packet_cycles + 28'b1;
      end
    end
  end

endmodule