data/full_repos/permissive/148201731/rtl/execute/branch_control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/148201731/rtl/execute/branch_control.v:54: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 27 bits.\n                                                                                    : ... In instance branch_control\n   assign pc_jump = {pc_offset_in,{2{1\'b0}}};\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/148201731/rtl/execute/branch_control.v:58: Operator COND expects 34 bits on the Conditional True, but Conditional True\'s VARREF \'reg_a_data_in\' generates 32 bits.\n                                                                                    : ... In instance branch_control\n   assign branch_val = branch_use_r_in? reg_a_data_in : pc_in + ({reg_b_data_in,{2{1\'b0}}}) + 4;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/148201731/rtl/execute/branch_control.v:58: Operator ADD expects 34 bits on the LHS, but LHS\'s VARREF \'pc_in\' generates 6 bits.\n                                                                                    : ... In instance branch_control\n   assign branch_val = branch_use_r_in? reg_a_data_in : pc_in + ({reg_b_data_in,{2{1\'b0}}}) + 4;\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/148201731/rtl/execute/branch_control.v:58: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 34 bits.\n                                                                                    : ... In instance branch_control\n   assign branch_val = branch_use_r_in? reg_a_data_in : pc_in + ({reg_b_data_in,{2{1\'b0}}}) + 4;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/148201731/rtl/execute/branch_control.v:60: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'pc_jump\' generates 6 bits.\n                                                                                    : ... In instance branch_control\n   assign jmp_val = jmp_use_r_in ? reg_a_data_in : pc_jump;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/148201731/rtl/execute/branch_control.v:62: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                    : ... In instance branch_control\n   assign pc_out = jmp_inst_in ? jmp_val : branch_val;\n                 ^\n%Error: Exiting due to 6 warning(s)\n'
module branch_control
#(
   parameter DATA_WIDTH = 32,
   parameter PC_WIDTH = 6,
   parameter PC_OFFSET_WIDTH = 25
)
(
   input jmp_inst_in,
   input jmp_use_r_in,
   input branch_use_r_in,
   input branch_inst_in,
   input branch_result_in,
   input [PC_WIDTH-1:0] pc_in,
   input [DATA_WIDTH-1:0] reg_a_data_in,
   input [DATA_WIDTH-1:0] reg_b_data_in,
   input [PC_OFFSET_WIDTH-1:0] pc_offset_in,

   output select_new_pc_out,
   output [PC_WIDTH-1:0] pc_out

);

   wire [DATA_WIDTH-1:0] jmp_val;
   wire [DATA_WIDTH-1:0] branch_val;
   wire [PC_WIDTH-1:0] pc_jump;



   assign pc_jump = {pc_offset_in,{2{1'b0}}};

   assign select_new_pc_out = jmp_inst_in | (branch_inst_in & branch_result_in);

   assign branch_val = branch_use_r_in? reg_a_data_in : pc_in + ({reg_b_data_in,{2{1'b0}}}) + 4;

   assign jmp_val = jmp_use_r_in ? reg_a_data_in : pc_jump;

   assign pc_out = jmp_inst_in ? jmp_val : branch_val;

endmodule
module branch_control
#(
   parameter DATA_WIDTH = 32,
   parameter PC_WIDTH = 6,
   parameter PC_OFFSET_WIDTH = 25
)
(
   input jmp_inst_in,
   input jmp_use_r_in,
   input branch_use_r_in,
   input branch_inst_in,
   input branch_result_in,
   input [PC_WIDTH-1:0] pc_in,
   input [DATA_WIDTH-1:0] reg_a_data_in,
   input [DATA_WIDTH-1:0] reg_b_data_in,
   input [PC_OFFSET_WIDTH-1:0] pc_offset_in,

   output select_new_pc_out,
   output [PC_WIDTH-1:0] pc_out

);


   wire [DATA_WIDTH-1:0] jmp_val;
   wire [DATA_WIDTH-1:0] branch_val;
   wire [PC_WIDTH-1:0] pc_jump;



   assign pc_jump = {pc_offset_in,{2{1'b0}}};

   assign select_new_pc_out = jmp_inst_in | (branch_inst_in & branch_result_in);

   assign branch_val = branch_use_r_in? reg_a_data_in : pc_in + ({reg_b_data_in,{2{1'b0}}}) + 4;

   assign jmp_val = jmp_use_r_in ? reg_a_data_in : pc_jump;

   assign pc_out = jmp_inst_in ? jmp_val : branch_val;

endmodule