data/full_repos/permissive/161275071/video/neo_b1.v
1: b"%Error: data/full_repos/permissive/161275071/video/neo_b1.v:89: Cannot find file containing module: 'linebuffer'\n linebuffer RAMBL(CLK, CK[0], WE[0], LD1, SS1, GAD, PCK2, SPR_PAL, PBUS[7:0], RAMBL_OUT);\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161275071/video,data/full_repos/permissive/161275071/linebuffer\n             data/full_repos/permissive/161275071/video,data/full_repos/permissive/161275071/linebuffer.v\n             data/full_repos/permissive/161275071/video,data/full_repos/permissive/161275071/linebuffer.sv\n             linebuffer\n             linebuffer.v\n             linebuffer.sv\n             obj_dir/linebuffer\n             obj_dir/linebuffer.v\n             obj_dir/linebuffer.sv\n%Error: data/full_repos/permissive/161275071/video/neo_b1.v:90: Cannot find file containing module: 'linebuffer'\n linebuffer RAMBR(CLK, CK[1], WE[1], LD1, SS1, GBD, PCK2, SPR_PAL, PBUS[15:8], RAMBR_OUT);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/161275071/video/neo_b1.v:91: Cannot find file containing module: 'linebuffer'\n linebuffer RAMTL(CLK, CK[2], WE[2], LD2, SS2, GAD, PCK2, SPR_PAL, PBUS[7:0], RAMTL_OUT);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/161275071/video/neo_b1.v:92: Cannot find file containing module: 'linebuffer'\n linebuffer RAMTR(CLK, CK[3], WE[3], LD2, SS2, GBD, PCK2, SPR_PAL, PBUS[15:8], RAMTR_OUT);\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module neo_b1(
	input CLK,
	input CLK_6MB,
	input CLK_1HB,
	
	input [23:0] PBUS,
	input [7:0] FIXD,
	input PCK1,
	input PCK2,
	input CHBL,
	input BNKB,
	input [3:0] GAD, GBD,
	input [3:0] WE,
	input [3:0] CK,
	input TMS0,
	input LD1, LD2,
	input SS1, SS2,
	input S1H1,
	
	input A23I, A22I,
	output [11:0] PA,
	
	input nLDS,
	input RW,
	input nAS,
	input [21:17] M68K_ADDR_U,
	input [12:1] M68K_ADDR_L,
	output nHALT,
	output nRESET,
	input nRST,
	
	input EN_FIX
);

	reg nCPU_ACCESS;
	
	reg [7:0] FIXD_REG;
	reg [3:0] FIX_PAL_REG;
	wire [3:0] FIX_COLOR;
	wire [3:0] SPR_COLOR;
	wire [11:0] RAMBL_OUT;
	wire [11:0] RAMBR_OUT;
	wire [11:0] RAMTL_OUT;
	wire [11:0] RAMTR_OUT;
	wire [7:0] SPR_PAL;
	wire [1:0] MUX_BA;
	wire [11:0] PA_MUX_A;
	wire [11:0] PA_MUX_B;
	wire [11:0] RAM_MUX_OUT;
	reg [11:0] PA_VIDEO;



	always @(posedge CLK_1HB)
		FIXD_REG <= FIXD;
	


	assign FIX_COLOR = S1H1 ? FIXD_REG[7:4] : FIXD_REG[3:0];



	wire FIX_OPAQUE = |{FIX_COLOR} & EN_FIX;


	always @(posedge PCK1)
		FIX_PAL_REG <= PBUS[19:16];

	assign SPR_PAL = PBUS[23:16];
	
	linebuffer RAMBL(CLK, CK[0], WE[0], LD1, SS1, GAD, PCK2, SPR_PAL, PBUS[7:0], RAMBL_OUT);
	linebuffer RAMBR(CLK, CK[1], WE[1], LD1, SS1, GBD, PCK2, SPR_PAL, PBUS[15:8], RAMBR_OUT);
	linebuffer RAMTL(CLK, CK[2], WE[2], LD2, SS2, GAD, PCK2, SPR_PAL, PBUS[7:0], RAMTL_OUT);
	linebuffer RAMTR(CLK, CK[3], WE[3], LD2, SS2, GBD, PCK2, SPR_PAL, PBUS[15:8], RAMTR_OUT);
	
	assign MUX_BA = {TMS0, S1H1};
	

	


	assign RAM_MUX_OUT = 
							(MUX_BA == 2'b00) ? RAMBR_OUT :
							(MUX_BA == 2'b01) ? RAMBL_OUT :
							(MUX_BA == 2'b10) ? RAMTR_OUT :
							RAMTL_OUT;
	





	


	always @(negedge nAS)
		nCPU_ACCESS <= A23I | ~A22I;
	


	assign PA_MUX_A = FIX_OPAQUE ? {4'b0000, FIX_PAL_REG, FIX_COLOR} : RAM_MUX_OUT;
	assign PA_MUX_B = CHBL ? 12'h000 : PA_MUX_A;


	always @(posedge CLK_6MB)
		PA_VIDEO <= PA_MUX_B;
	

	assign PA = nCPU_ACCESS ? PA_VIDEO : M68K_ADDR_L;




	
endmodule
module neo_b1(
	input CLK,
	input CLK_6MB,
	input CLK_1HB,
	
	input [23:0] PBUS,
	input [7:0] FIXD,
	input PCK1,
	input PCK2,
	input CHBL,
	input BNKB,
	input [3:0] GAD, GBD,
	input [3:0] WE,
	input [3:0] CK,
	input TMS0,
	input LD1, LD2,
	input SS1, SS2,
	input S1H1,
	
	input A23I, A22I,
	output [11:0] PA,
	
	input nLDS,
	input RW,
	input nAS,
	input [21:17] M68K_ADDR_U,
	input [12:1] M68K_ADDR_L,
	output nHALT,
	output nRESET,
	input nRST,
	
	input EN_FIX
);


	reg nCPU_ACCESS;
	
	reg [7:0] FIXD_REG;
	reg [3:0] FIX_PAL_REG;
	wire [3:0] FIX_COLOR;
	wire [3:0] SPR_COLOR;
	wire [11:0] RAMBL_OUT;
	wire [11:0] RAMBR_OUT;
	wire [11:0] RAMTL_OUT;
	wire [11:0] RAMTR_OUT;
	wire [7:0] SPR_PAL;
	wire [1:0] MUX_BA;
	wire [11:0] PA_MUX_A;
	wire [11:0] PA_MUX_B;
	wire [11:0] RAM_MUX_OUT;
	reg [11:0] PA_VIDEO;



	always @(posedge CLK_1HB)
		FIXD_REG <= FIXD;
	


	assign FIX_COLOR = S1H1 ? FIXD_REG[7:4] : FIXD_REG[3:0];



	wire FIX_OPAQUE = |{FIX_COLOR} & EN_FIX;


	always @(posedge PCK1)
		FIX_PAL_REG <= PBUS[19:16];

	assign SPR_PAL = PBUS[23:16];
	
	linebuffer RAMBL(CLK, CK[0], WE[0], LD1, SS1, GAD, PCK2, SPR_PAL, PBUS[7:0], RAMBL_OUT);
	linebuffer RAMBR(CLK, CK[1], WE[1], LD1, SS1, GBD, PCK2, SPR_PAL, PBUS[15:8], RAMBR_OUT);
	linebuffer RAMTL(CLK, CK[2], WE[2], LD2, SS2, GAD, PCK2, SPR_PAL, PBUS[7:0], RAMTL_OUT);
	linebuffer RAMTR(CLK, CK[3], WE[3], LD2, SS2, GBD, PCK2, SPR_PAL, PBUS[15:8], RAMTR_OUT);
	
	assign MUX_BA = {TMS0, S1H1};
	

	


	assign RAM_MUX_OUT = 
							(MUX_BA == 2'b00) ? RAMBR_OUT :
							(MUX_BA == 2'b01) ? RAMBL_OUT :
							(MUX_BA == 2'b10) ? RAMTR_OUT :
							RAMTL_OUT;
	





	


	always @(negedge nAS)
		nCPU_ACCESS <= A23I | ~A22I;
	


	assign PA_MUX_A = FIX_OPAQUE ? {4'b0000, FIX_PAL_REG, FIX_COLOR} : RAM_MUX_OUT;
	assign PA_MUX_B = CHBL ? 12'h000 : PA_MUX_A;


	always @(posedge CLK_6MB)
		PA_VIDEO <= PA_MUX_B;
	

	assign PA = nCPU_ACCESS ? PA_VIDEO : M68K_ADDR_L;




	
endmodule