data/full_repos/permissive/208741034/key_control_beep/rtl/key_debounce.v
 line:59: before: "/"
1: b'%Warning-WIDTH: data/full_repos/permissive/208741034/key_control_beep/rtl/key_debounce.v:45: Operator EQ expects 20 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                           : ... In instance key_debounce\n         if(key_cnt == 1\'b1)begin\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module key_debounce(
    input clk,
    input rst_n,

    input key,
    output reg key_value,
    output reg key_flag
    
);

reg key_reg;
reg [19 : 0]key_cnt;


always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
    key_reg <= 1'b1 ;
    key_cnt <= 20'd0;
	 end
    else begin
        key_reg <= key;
        if(key_reg != key)
		  
           key_cnt <= 20'd1000_000;
        else begin
            if(key_cnt > 20'd0)
            key_cnt <= key_cnt - 1'b1;
            else
            key_cnt <= 20'd0;
           
        end
    end

end


always @(posedge clk or negedge rst_n) begin
     
     if(!rst_n)begin
         key_value <= 1'b1;
         key_flag  <= 1'b0;
     end

     else begin
         if(key_cnt == 1'b1)begin
             key_flag = 1'b1;
             key_value = key;
         end
         else begin
             key_flag <= 1'b0;
             key_value <= key_value;

         end
     end
    
end


endmodule
module key_debounce(
    input clk,
    input rst_n,

    input key,
    output reg key_value,
    output reg key_flag
    
);


reg key_reg;
reg [19 : 0]key_cnt;


always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
    key_reg <= 1'b1 ;
    key_cnt <= 20'd0;
	 end
    else begin
        key_reg <= key;
        if(key_reg != key)
		  
           key_cnt <= 20'd1000_000;
        else begin
            if(key_cnt > 20'd0)
            key_cnt <= key_cnt - 1'b1;
            else
            key_cnt <= 20'd0;
           
        end
    end

end


always @(posedge clk or negedge rst_n) begin
     
     if(!rst_n)begin
         key_value <= 1'b1;
         key_flag  <= 1'b0;
     end

     else begin
         if(key_cnt == 1'b1)begin
             key_flag = 1'b1;
             key_value = key;
         end
         else begin
             key_flag <= 1'b0;
             key_value <= key_value;

         end
     end
    
end


endmodule