data/full_repos/permissive/157135695/lab4iramHalt.v
 line:17 column:22: Illegal character "'"
data/verilator_xmls/33d5f81e-3234-4208-8b38-e9057c488a71.xml
module lab4iramHalt(CLK, RESET, ADDR, Q);
  input         CLK;
  input         RESET;
  input  [7:0]  ADDR;
  output [15:0] Q;

  reg    [15:0] mem[0:127];

  wire   [6:0]  saddr;
  integer       i;

  assign saddr = ADDR[7:1];
  assign Q = mem[saddr];

  always @(posedge CLK) begin
    if(RESET) begin
      mem[0]   <= 16'b 1111010010010001;
      mem[1]   <= 16'b 1111001001001001;
      mem[2]   <= 16'b 0101010010111111;
      mem[3]   <= 16'b 0100010001000000;
      mem[4]   <= 16'b 0000000000000001;
      mem[5]   <= 16'b 1111010010010000;
      mem[6]   <= 16'b 0101010010111111;
      mem[7]   <= 16'b 0101010010111111;
      mem[8]   <= 16'b 1111010001010001;
      mem[9]   <= 16'b 0101010010000011;
      mem[10]   <= 16'b 0101001001000001;
      mem[11]  <= 16'b 0100010001000000;
      mem[12]   <= 16'b 0000000000000001;
      mem[13]  <= 16'b 0101001001000001;
      mem[14]  <= 16'b 0100010001000000;
      mem[15]  <= 16'b 0101001001000001;
      mem[16]   <= 16'b 0000000000000001;
      mem[17]  <= 16'b 0100010001000000;
      mem[18]  <= 16'b 0101001001000001;
      mem[19]  <= 16'b 0100010001000000;

      for(i = 23; i < 128; i = i + 1) begin
        mem[i] <= 16'b0000000000000000;
      end
    end
  end

endmodule
module lab4iramHalt(CLK, RESET, ADDR, Q);

  input         CLK;
  input         RESET;
  input  [7:0]  ADDR;
  output [15:0] Q;

  reg    [15:0] mem[0:127];

  wire   [6:0]  saddr;
  integer       i;

  assign saddr = ADDR[7:1];
  assign Q = mem[saddr];

  always @(posedge CLK) begin
    if(RESET) begin
      mem[0]   <= 16'b 1111010010010001;
      mem[1]   <= 16'b 1111001001001001;
      mem[2]   <= 16'b 0101010010111111;
      mem[3]   <= 16'b 0100010001000000;
      mem[4]   <= 16'b 0000000000000001;
      mem[5]   <= 16'b 1111010010010000;
      mem[6]   <= 16'b 0101010010111111;
      mem[7]   <= 16'b 0101010010111111;
      mem[8]   <= 16'b 1111010001010001;
      mem[9]   <= 16'b 0101010010000011;
      mem[10]   <= 16'b 0101001001000001;
      mem[11]  <= 16'b 0100010001000000;
      mem[12]   <= 16'b 0000000000000001;
      mem[13]  <= 16'b 0101001001000001;
      mem[14]  <= 16'b 0100010001000000;
      mem[15]  <= 16'b 0101001001000001;
      mem[16]   <= 16'b 0000000000000001;
      mem[17]  <= 16'b 0100010001000000;
      mem[18]  <= 16'b 0101001001000001;
      mem[19]  <= 16'b 0100010001000000;

      for(i = 23; i < 128; i = i + 1) begin
        mem[i] <= 16'b0000000000000000;
      end
    end
  end

endmodule