data/full_repos/permissive/163728837/src/line_writer.v
 line:486: before: "signed"
1: b'%Error: data/full_repos/permissive/163728837/src/line_writer.v:110: Cannot find file containing module: \'simple_dual_ram\'\nsimple_dual_ram #(.SIZE(16), .DEPTH((HEIGHT_MAX+1)*2)) line_ram (\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/163728837/src,data/full_repos/permissive/163728837/simple_dual_ram\n             data/full_repos/permissive/163728837/src,data/full_repos/permissive/163728837/simple_dual_ram.v\n             data/full_repos/permissive/163728837/src,data/full_repos/permissive/163728837/simple_dual_ram.sv\n             simple_dual_ram\n             simple_dual_ram.v\n             simple_dual_ram.sv\n             obj_dir/simple_dual_ram\n             obj_dir/simple_dual_ram.v\n             obj_dir/simple_dual_ram.sv\n%Error: data/full_repos/permissive/163728837/src/line_writer.v:127: Cannot find file containing module: \'simple_dual_ram\'\nsimple_dual_ram #(.SIZE(4), .DEPTH(16384)) texture_ram (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/163728837/src/line_writer.v:138: Cannot find file containing module: \'simple_dual_ram\'\nsimple_dual_ram #(.SIZE(16), .DEPTH(256)) texture_pal_ram (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/163728837/src/line_writer.v:152: Cannot find file containing module: \'floordist_rom\'\nfloordist_rom floordist_rom (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/163728837/src/line_writer.v:161: Cannot find file containing module: \'iheight_rom\'\niheight_rom iheight_rom (\n^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:184: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                          : ... In instance line_writer\n    draw_end_q = 16\'d0;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:185: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                          : ... In instance line_writer\n    draw_start_q = 16\'d0;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:201: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                          : ... In instance line_writer\n    ram_write_data = 8\'d0;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:207: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'count_q\' generates 8 bits.\n                                                                          : ... In instance line_writer\n    fd_addr = count_q;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:261: Operator SUB expects 14 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                          : ... In instance line_writer\n                tex_offset_d[21:8] = TEX_SIZE * (pixel[3:0] - 1\'b1) + (tex_x << 5);\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:261: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'tex_x\' generates 7 bits.\n                                                                          : ... In instance line_writer\n                tex_offset_d[21:8] = TEX_SIZE * (pixel[3:0] - 1\'b1) + (tex_x << 5);\n                                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:263: Operator SUB expects 32 or 8 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                          : ... In instance line_writer\n                texp_offset_d = PAL_SIZE * (pixel[3:0] - 1\'b1);\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:278: Operator SUB expects 32 bits on the LHS, but LHS\'s CONST \'16\'h100\' generates 16 bits.\n                                                                          : ... In instance line_writer\n            cfloor_x_d = trunc_fixed_mul(weight_q * floor_x_q) + trunc_fixed_mul((16\'h01_00 - weight_q) * pos_x_q);\n                                                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:278: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'weight_q\' generates 16 bits.\n                                                                          : ... In instance line_writer\n            cfloor_x_d = trunc_fixed_mul(weight_q * floor_x_q) + trunc_fixed_mul((16\'h01_00 - weight_q) * pos_x_q);\n                                                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:279: Operator SUB expects 32 bits on the LHS, but LHS\'s CONST \'16\'h100\' generates 16 bits.\n                                                                          : ... In instance line_writer\n            cfloor_y_d = trunc_fixed_mul(weight_q * floor_y_q) + trunc_fixed_mul((16\'h01_00 - weight_q) * pos_y_q);\n                                                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:279: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'weight_q\' generates 16 bits.\n                                                                          : ... In instance line_writer\n            cfloor_y_d = trunc_fixed_mul(weight_q * floor_y_q) + trunc_fixed_mul((16\'h01_00 - weight_q) * pos_y_q);\n                                                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:286: Operator SHIFTL expects 32 or 14 bits on the LHS, but LHS\'s SEL generates 5 bits.\n                                                                          : ... In instance line_writer\n                tram_raddr = CEILING_OFFSET + (cfloor_x_q[7:3] << 5) + cfloor_y_q[7:3];\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:286: Operator ADD expects 32 or 14 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                          : ... In instance line_writer\n                tram_raddr = CEILING_OFFSET + (cfloor_x_q[7:3] << 5) + cfloor_y_q[7:3];\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:290: Operator SHIFTL expects 32 or 14 bits on the LHS, but LHS\'s SEL generates 5 bits.\n                                                                          : ... In instance line_writer\n                tram_raddr = FLOOR_OFFSET + (cfloor_x_q[7:3] << 5) + cfloor_y_q[7:3];\n                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:290: Operator ADD expects 32 or 14 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                          : ... In instance line_writer\n                tram_raddr = FLOOR_OFFSET + (cfloor_x_q[7:3] << 5) + cfloor_y_q[7:3];\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:295: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'tram_read_data\' generates 4 bits.\n                                                                          : ... In instance line_writer\n            tpram_raddr = texp_offset_q + tram_read_data;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:297: Operator ADD expects 32 or 8 bits on the RHS, but RHS\'s VARREF \'tram_read_data\' generates 4 bits.\n                                                                          : ... In instance line_writer\n                tpram_raddr = CEILING_PAL + tram_read_data;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:299: Operator ADD expects 32 or 8 bits on the RHS, but RHS\'s VARREF \'tram_read_data\' generates 4 bits.\n                                                                          : ... In instance line_writer\n                tpram_raddr = FLOOR_PAL + tram_read_data;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:319: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'scale_q\' generates 16 bits.\n                                                                          : ... In instance line_writer\n                tex_offset_d = tex_offset_q + scale_q;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:364: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'spr_height_q\' generates 16 bits.\n                                                                          : ... In instance line_writer\n            spr_tex_x_d = ((spr_height_q >> 1) - (spr_screenx_q - camera_x_q)) << 16;\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:364: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'spr_screenx_q\' generates 16 bits.\n                                                                          : ... In instance line_writer\n            spr_tex_x_d = ((spr_height_q >> 1) - (spr_screenx_q - camera_x_q)) << 16;\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:364: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'camera_x_q\' generates 9 bits.\n                                                                          : ... In instance line_writer\n            spr_tex_x_d = ((spr_height_q >> 1) - (spr_screenx_q - camera_x_q)) << 16;\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:366: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'iheight\' generates 16 bits.\n                                                                          : ... In instance line_writer\n            spr_iheight_d = iheight << 8;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:373: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'spr_texid_q\' generates 8 bits.\n                                                                          : ... In instance line_writer\n            tex_offset_d[21:8] = (spr_texid_q << 10) + (spr_tex_x_d[20:16] << 5);\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:373: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s SEL generates 5 bits.\n                                                                          : ... In instance line_writer\n            tex_offset_d[21:8] = (spr_texid_q << 10) + (spr_tex_x_d[20:16] << 5);\n                                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:386: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'spr_starty_q\' generates 16 bits.\n                                                                          : ... In instance line_writer\n                count_d = spr_starty_q;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:389: Operator SUB expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'HEIGHT_MAX\' generates 8 bits.\n                                                                          : ... In instance line_writer\n                spr_endy_d = HEIGHT_MAX-1;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:388: Operator SUB expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'HEIGHT_MAX\' generates 8 bits.\n                                                                          : ... In instance line_writer\n            if (spr_endy_q > HEIGHT_MAX-1) begin\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:401: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'spr_idx_q\' generates 16 bits.\n                                                                          : ... In instance line_writer\n            tram_holdr_d = (trunc_fixed_mul32((spr_idx_q << 16) * spr_iheight_q) >> 16) + tex_offset_q[21:8];\n                                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:401: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 14 bits.\n                                                                          : ... In instance line_writer\n            tram_holdr_d = (trunc_fixed_mul32((spr_idx_q << 16) * spr_iheight_q) >> 16) + tex_offset_q[21:8];\n                                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:401: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                          : ... In instance line_writer\n            tram_holdr_d = (trunc_fixed_mul32((spr_idx_q << 16) * spr_iheight_q) >> 16) + tex_offset_q[21:8];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:413: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'tram_read_data\' generates 4 bits.\n                                                                          : ... In instance line_writer\n                tpram_raddr = texp_offset_q + tram_read_data;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/line_writer.v:425: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'count_q\' generates 8 bits.\n                                                                          : ... In instance line_writer\n            if (count_q == spr_endy_q) begin\n                        ^~\n%Error: Exiting due to 5 error(s), 33 warning(s)\n'
function signed [31:0] trunc_fixed_mul32(input signed [63:0] mulres);
  trunc_fixed_mul32 = mulres[47:16];
endfunction
function signed [31:0] trunc_fixed_mul32(input signed [63:0] mulres);

  trunc_fixed_mul32 = mulres[47:16];
endfunction