data/full_repos/permissive/169574047/fulladd4/fulladd4.srcs/sim_1/new/testbench.v
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1: b'%Error: data/full_repos/permissive/169574047/fulladd4/fulladd4.srcs/sim_1/new/testbench.v:38: Unsupported or unknown PLI call: $monitor\n    $monitor($time," A = %b, B = %b, C_IN = %b --- C_OUT = %b, SUM = %b", A, B, C_IN, C_OUT1, SUM1);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169574047/fulladd4/fulladd4.srcs/sim_1/new/testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #5 A = 4\'d3; B = 4\'d4;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/fulladd4/fulladd4.srcs/sim_1/new/testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #5 A = 4\'d2; B = 4\'d5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/fulladd4/fulladd4.srcs/sim_1/new/testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #5 A = 4\'d9; B = 4\'d9;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/fulladd4/fulladd4.srcs/sim_1/new/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #5 A = 4\'d10; B = 4\'d15;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/fulladd4/fulladd4.srcs/sim_1/new/testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #5 A = 4\'d10; B = 4\'d5; C_IN = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/fulladd4/fulladd4.srcs/sim_1/new/testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM1, SUM2, SUM3;
wire C_OUT1, C_OUT2, C_OUT3;


fulladd4 FA1_4_1(SUM1, C_OUT1, A, B, C_IN);
logic1_fulladd4 FA1_4_2(SUM2, C_OUT2, A, B, C_IN);
logic2_fulladd4 FA1_4_3(SUM3, C_OUT3, A, B, C_IN);


initial
begin
    $monitor($time," A = %b, B = %b, C_IN = %b --- C_OUT = %b, SUM = %b", A, B, C_IN, C_OUT1, SUM1);
end


initial
begin
    A = 4'd0; B = 4'd0; C_IN = 1'b0;
    #5 A = 4'd3; B = 4'd4;
    #5 A = 4'd2; B = 4'd5;
    #5 A = 4'd9; B = 4'd9;
    #5 A = 4'd10; B = 4'd15;
    #5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
    #5 $finish;
end

endmodule
module testbench;


reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM1, SUM2, SUM3;
wire C_OUT1, C_OUT2, C_OUT3;


fulladd4 FA1_4_1(SUM1, C_OUT1, A, B, C_IN);
logic1_fulladd4 FA1_4_2(SUM2, C_OUT2, A, B, C_IN);
logic2_fulladd4 FA1_4_3(SUM3, C_OUT3, A, B, C_IN);


initial
begin
    $monitor($time," A = %b, B = %b, C_IN = %b --- C_OUT = %b, SUM = %b", A, B, C_IN, C_OUT1, SUM1);
end


initial
begin
    A = 4'd0; B = 4'd0; C_IN = 1'b0;
    #5 A = 4'd3; B = 4'd4;
    #5 A = 4'd2; B = 4'd5;
    #5 A = 4'd9; B = 4'd9;
    #5 A = 4'd10; B = 4'd15;
    #5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
    #5 $finish;
end

endmodule