data/full_repos/permissive/136610640/soc_system/submodules/alt_vipitc130_common_trigger_sync.v
1: b"%Error: data/full_repos/permissive/136610640/soc_system/submodules/alt_vipitc130_common_trigger_sync.v:32: Cannot find file containing module: 'alt_vipitc130_common_sync'\n        alt_vipitc130_common_sync #(CLOCKS_ARE_SAME) toggle_sync(\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136610640/soc_system/submodules,data/full_repos/permissive/136610640/alt_vipitc130_common_sync\n             data/full_repos/permissive/136610640/soc_system/submodules,data/full_repos/permissive/136610640/alt_vipitc130_common_sync.v\n             data/full_repos/permissive/136610640/soc_system/submodules,data/full_repos/permissive/136610640/alt_vipitc130_common_sync.sv\n             alt_vipitc130_common_sync\n             alt_vipitc130_common_sync.v\n             alt_vipitc130_common_sync.sv\n             obj_dir/alt_vipitc130_common_sync\n             obj_dir/alt_vipitc130_common_sync.v\n             obj_dir/alt_vipitc130_common_sync.sv\n%Error: Exiting due to 1 error(s)\n"
module alt_vipitc130_common_trigger_sync(
    input wire input_rst,
    input wire input_clock,
    input wire rst,
    input wire sync_clock,
    
    input wire trigger_in,
    input wire ack_in,
    output wire trigger_out);

parameter CLOCKS_ARE_SAME = 0;

generate
    if(CLOCKS_ARE_SAME) 
        assign trigger_out = trigger_in;
    else begin
        reg trigger_in_reg;
        reg toggle;
        reg toggle_synched_reg;
        wire toggle_synched;
        
        always @ (posedge input_rst or posedge input_clock) begin
            if(input_rst) begin
                trigger_in_reg <= 1'b0;
                toggle <= 1'b0;
            end else begin
                trigger_in_reg <= trigger_in;
                toggle <= toggle ^ (trigger_in & (~trigger_in_reg | ack_in));
            end
        end
        
        alt_vipitc130_common_sync #(CLOCKS_ARE_SAME) toggle_sync(
            .rst(rst),
            .sync_clock(sync_clock),
            .data_in(toggle),
            .data_out(toggle_synched));
            
        always @ (posedge rst or posedge sync_clock) begin
            if(rst) begin
                toggle_synched_reg <= 1'b0;
            end else begin
                toggle_synched_reg <= toggle_synched;
            end
        end
        
        assign trigger_out = toggle_synched ^ toggle_synched_reg;
    end
endgenerate

endmodule
module alt_vipitc130_common_trigger_sync(
    input wire input_rst,
    input wire input_clock,
    input wire rst,
    input wire sync_clock,
    
    input wire trigger_in,
    input wire ack_in,
    output wire trigger_out);


parameter CLOCKS_ARE_SAME = 0;

generate
    if(CLOCKS_ARE_SAME) 
        assign trigger_out = trigger_in;
    else begin
        reg trigger_in_reg;
        reg toggle;
        reg toggle_synched_reg;
        wire toggle_synched;
        
        always @ (posedge input_rst or posedge input_clock) begin
            if(input_rst) begin
                trigger_in_reg <= 1'b0;
                toggle <= 1'b0;
            end else begin
                trigger_in_reg <= trigger_in;
                toggle <= toggle ^ (trigger_in & (~trigger_in_reg | ack_in));
            end
        end
        
        alt_vipitc130_common_sync #(CLOCKS_ARE_SAME) toggle_sync(
            .rst(rst),
            .sync_clock(sync_clock),
            .data_in(toggle),
            .data_out(toggle_synched));
            
        always @ (posedge rst or posedge sync_clock) begin
            if(rst) begin
                toggle_synched_reg <= 1'b0;
            end else begin
                toggle_synched_reg <= toggle_synched;
            end
        end
        
        assign trigger_out = toggle_synched ^ toggle_synched_reg;
    end
endgenerate

endmodule