data/full_repos/permissive/165983004/updated_part2.v
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1: b'%Warning-IMPLICIT: data/full_repos/permissive/165983004/updated_part2.v:84: Signal definition not found, creating implicitly: \'left\'\n assign left = KEY[3];\n        ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/165983004/updated_part2.v:85: Signal definition not found, creating implicitly: \'right\'\n assign right = KEY[2];\n        ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:660: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'counterx\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n    x <= x_in + dx + counterx;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:697: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'counterx_n1\' generates 2 bits.\n                                                                        : ... In instance updated_part2.d1\n    x <= 8\'b10011001 + counterx_n1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:698: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'countery_n1\' generates 3 bits.\n                                                                        : ... In instance updated_part2.d1\n    y <= 7\'b0010111 + countery_n1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:734: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'counterx_n2\' generates 2 bits.\n                                                                        : ... In instance updated_part2.d1\n    x <= 8\'b10011001 + counterx_n2;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:735: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'countery_n2\' generates 3 bits.\n                                                                        : ... In instance updated_part2.d1\n    y <= 7\'b0101010 + countery_n2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:772: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'counterx_n3\' generates 2 bits.\n                                                                        : ... In instance updated_part2.d1\n    x <= 8\'b10011001 + counterx_n3;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:773: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'countery_n3\' generates 3 bits.\n                                                                        : ... In instance updated_part2.d1\n    y <= 7\'b0111101 + countery_n3;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:801: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'wheaty\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n    y <= wheaty;\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:811: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      counterx <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:812: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance updated_part2.d1\n      countery <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:828: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      counterx <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:829: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance updated_part2.d1\n      countery <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:839: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      counterx <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:840: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance updated_part2.d1\n      countery <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:850: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      counterx <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:851: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance updated_part2.d1\n      countery <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:861: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      counterx <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:862: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance updated_part2.d1\n      countery <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:874: Operator ADD expects 8 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n       data_result[7:0] <= data_result[7:0] + 4\'b0001;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:939: Operator GT expects 7 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n       if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:939: Operator LT expects 7 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n       if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:939: Operator GT expects 8 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n                                                                        : ... In instance updated_part2.d1\n       if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:939: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h78\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n       if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:953: Operator GT expects 7 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n      if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:953: Operator LT expects 7 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance updated_part2.d1\n      if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:953: Operator GT expects 8 bits on the RHS, but RHS\'s CONST \'6\'h14\' generates 6 bits.\n                                                                        : ... In instance updated_part2.d1\n      if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:953: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h78\' generates 7 bits.\n                                                                        : ... In instance updated_part2.d1\n      if(SW[9] && y > 4\'b1010 && y < 4\'b1111 && x > 6\'b10100 && x < 7\'b1111000)\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:1014: Operator GT expects 8 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n                                                                         : ... In instance updated_part2.d1\n      if(SW[9] && y < 7\'b1101101 &&  y > 7\'b1000011 && x > 6\'b101000 && x < 8\'b01011111 && has_refined_wheat == 1)\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/165983004/updated_part2.v:1038: Operator GT expects 8 bits on the RHS, but RHS\'s CONST \'6\'h28\' generates 6 bits.\n                                                                         : ... In instance updated_part2.d1\n      if(SW[9] && y < 7\'b1101101 &&  y > 7\'b1000011 && x > 6\'b101000 && x < 8\'b01011111)\n                                                         ^\n%Error: data/full_repos/permissive/165983004/updated_part2.v:54: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165983004,data/full_repos/permissive/165983004/vga_adapter\n             data/full_repos/permissive/165983004,data/full_repos/permissive/165983004/vga_adapter.v\n             data/full_repos/permissive/165983004,data/full_repos/permissive/165983004/vga_adapter.sv\n             vga_adapter\n             vga_adapter.v\n             vga_adapter.sv\n             obj_dir/vga_adapter\n             obj_dir/vga_adapter.v\n             obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 31 warning(s)\n'
module hex_decoder(hex_digit, segments);
    input [3:0] hex_digit;
    output reg [6:0] segments;
   
    always @(*)
        case (hex_digit)
            4'h0: segments = 7'b100_0000;
            4'h1: segments = 7'b111_1001;
            4'h2: segments = 7'b010_0100;
            4'h3: segments = 7'b011_0000;
            4'h4: segments = 7'b001_1001;
            4'h5: segments = 7'b001_0010;
            4'h6: segments = 7'b000_0010;
            4'h7: segments = 7'b111_1000;
            4'h8: segments = 7'b000_0000;
            4'h9: segments = 7'b001_1000;
            4'hA: segments = 7'b000_1000;
            4'hB: segments = 7'b000_0011;
            4'hC: segments = 7'b100_0110;
            4'hD: segments = 7'b010_0001;
            4'hE: segments = 7'b000_0110;
            4'hF: segments = 7'b000_1110;   
            default: segments = 7'h7f;
        endcase
endmodule
module hex_decoder(hex_digit, segments);

    input [3:0] hex_digit;
    output reg [6:0] segments;
   
    always @(*)
        case (hex_digit)
            4'h0: segments = 7'b100_0000;
            4'h1: segments = 7'b111_1001;
            4'h2: segments = 7'b010_0100;
            4'h3: segments = 7'b011_0000;
            4'h4: segments = 7'b001_1001;
            4'h5: segments = 7'b001_0010;
            4'h6: segments = 7'b000_0010;
            4'h7: segments = 7'b111_1000;
            4'h8: segments = 7'b000_0000;
            4'h9: segments = 7'b001_1000;
            4'hA: segments = 7'b000_1000;
            4'hB: segments = 7'b000_0011;
            4'hC: segments = 7'b100_0110;
            4'hD: segments = 7'b010_0001;
            4'hE: segments = 7'b000_0110;
            4'hF: segments = 7'b000_1110;   
            default: segments = 7'h7f;
        endcase
endmodule