data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/wb.v
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data/verilator_xmls/383a2f80-bb5b-4814-9d91-2ace71c00079.xml
module wb(
    input          WB_valid,
    input  [117:0] MEM_WB_bus_r,
    output         rf_wen,
    output [  4:0] rf_wdest,
    output [ 31:0] rf_wdata,
    output         WB_over,


     input             clk,
    input             resetn,
     output [ 32:0] exc_bus,
     output [  4:0] WB_wdest,
     output         cancel,

 

     output [ 31:0] WB_pc,
     output [ 31:0] HI_data,
     output [ 31:0] LO_data
);


    wire [31:0] mem_result;

    wire [31:0] lo_result;
    wire        hi_write;
    wire        lo_write;
    

    wire wen;
    wire [4:0] wdest;
    

    wire mfhi;
    wire mflo;
    wire mtc0;
    wire mfc0;
    wire [7 :0] cp0r_addr;
    wire       syscall;
    wire       eret;
    

    wire [31:0] pc;    
    assign {wen,
            wdest,
            mem_result,
            lo_result,
            hi_write,
            lo_write,
            mfhi,
            mflo,
            mtc0,
            mfc0,
            cp0r_addr,
            syscall,
            eret,
            pc} = MEM_WB_bus_r;





    reg [31:0] hi;
    reg [31:0] lo;
    

    always @(posedge clk)
    begin
        if (hi_write)
        begin
            hi <= mem_result;
        end
    end

    always @(posedge clk)
    begin
        if (lo_write)
        begin
            lo <= lo_result;
        end
    end







   wire [31:0] cp0r_status;
   wire [31:0] cp0r_cause;
   wire [31:0] cp0r_epc;
   

   wire status_wen;

   wire epc_wen;
   assign status_wen = mtc0 & (cp0r_addr=={5'd12,3'd0});
   assign epc_wen    = mtc0 & (cp0r_addr=={5'd14,3'd0});
   

   wire [31:0] cp0r_rdata;
   assign cp0r_rdata = (cp0r_addr=={5'd12,3'd0}) ? cp0r_status :
                       (cp0r_addr=={5'd13,3'd0}) ? cp0r_cause  :
                       (cp0r_addr=={5'd14,3'd0}) ? cp0r_epc : 32'd0;
   



   reg status_exl_r;
   assign cp0r_status = {30'd0,status_exl_r,1'b0};
   always @(posedge clk)
   begin
       if (!resetn || eret)
       begin
           status_exl_r <= 1'b0;
       end
       else if (syscall)
       begin
           status_exl_r <= 1'b1;
       end
       else if (status_wen)
       begin
           status_exl_r <= mem_result[1];
       end
   end
   



   reg [4:0] cause_exc_code_r;
   assign cp0r_cause = {25'd0,cause_exc_code_r,2'd0};
   always @(posedge clk)
   begin
       if (syscall)
       begin
           cause_exc_code_r <= 5'd8;
       end
   end
   



   reg [31:0] epc_r;
   assign cp0r_epc = epc_r;
   always @(posedge clk)
   begin
       if (syscall)
       begin
           epc_r <= pc;
       end
       else if (epc_wen)
       begin
           epc_r <= mem_result;
       end
   end
   

   assign cancel = (syscall | eret) & WB_over;





    assign WB_over = WB_valid;



    assign rf_wen   = wen & WB_over;
    assign rf_wdest = wdest;
    assign rf_wdata = mfhi ? hi :
                      mflo ? lo :
                      mfc0 ? cp0r_rdata : mem_result;



    wire        exc_valid;
    wire [31:0] exc_pc;
    assign exc_valid = (syscall | eret) & WB_valid;



    assign exc_pc = syscall ? `EXC_ENTER_ADDR : cp0r_epc;
    
    assign exc_bus = {exc_valid,exc_pc};




    assign WB_wdest = rf_wdest & {5{WB_valid}};



    assign WB_pc = pc;
    assign HI_data = hi;
    assign LO_data = lo;

endmodule
module wb(
    input          WB_valid,
    input  [117:0] MEM_WB_bus_r,
    output         rf_wen,
    output [  4:0] rf_wdest,
    output [ 31:0] rf_wdata,
    output         WB_over,


     input             clk,
    input             resetn,
     output [ 32:0] exc_bus,
     output [  4:0] WB_wdest,
     output         cancel,

 

     output [ 31:0] WB_pc,
     output [ 31:0] HI_data,
     output [ 31:0] LO_data
);



    wire [31:0] mem_result;

    wire [31:0] lo_result;
    wire        hi_write;
    wire        lo_write;
    

    wire wen;
    wire [4:0] wdest;
    

    wire mfhi;
    wire mflo;
    wire mtc0;
    wire mfc0;
    wire [7 :0] cp0r_addr;
    wire       syscall;
    wire       eret;
    

    wire [31:0] pc;    
    assign {wen,
            wdest,
            mem_result,
            lo_result,
            hi_write,
            lo_write,
            mfhi,
            mflo,
            mtc0,
            mfc0,
            cp0r_addr,
            syscall,
            eret,
            pc} = MEM_WB_bus_r;





    reg [31:0] hi;
    reg [31:0] lo;
    

    always @(posedge clk)
    begin
        if (hi_write)
        begin
            hi <= mem_result;
        end
    end

    always @(posedge clk)
    begin
        if (lo_write)
        begin
            lo <= lo_result;
        end
    end







   wire [31:0] cp0r_status;
   wire [31:0] cp0r_cause;
   wire [31:0] cp0r_epc;
   

   wire status_wen;

   wire epc_wen;
   assign status_wen = mtc0 & (cp0r_addr=={5'd12,3'd0});
   assign epc_wen    = mtc0 & (cp0r_addr=={5'd14,3'd0});
   

   wire [31:0] cp0r_rdata;
   assign cp0r_rdata = (cp0r_addr=={5'd12,3'd0}) ? cp0r_status :
                       (cp0r_addr=={5'd13,3'd0}) ? cp0r_cause  :
                       (cp0r_addr=={5'd14,3'd0}) ? cp0r_epc : 32'd0;
   



   reg status_exl_r;
   assign cp0r_status = {30'd0,status_exl_r,1'b0};
   always @(posedge clk)
   begin
       if (!resetn || eret)
       begin
           status_exl_r <= 1'b0;
       end
       else if (syscall)
       begin
           status_exl_r <= 1'b1;
       end
       else if (status_wen)
       begin
           status_exl_r <= mem_result[1];
       end
   end
   



   reg [4:0] cause_exc_code_r;
   assign cp0r_cause = {25'd0,cause_exc_code_r,2'd0};
   always @(posedge clk)
   begin
       if (syscall)
       begin
           cause_exc_code_r <= 5'd8;
       end
   end
   



   reg [31:0] epc_r;
   assign cp0r_epc = epc_r;
   always @(posedge clk)
   begin
       if (syscall)
       begin
           epc_r <= pc;
       end
       else if (epc_wen)
       begin
           epc_r <= mem_result;
       end
   end
   

   assign cancel = (syscall | eret) & WB_over;





    assign WB_over = WB_valid;



    assign rf_wen   = wen & WB_over;
    assign rf_wdest = wdest;
    assign rf_wdata = mfhi ? hi :
                      mflo ? lo :
                      mfc0 ? cp0r_rdata : mem_result;



    wire        exc_valid;
    wire [31:0] exc_pc;
    assign exc_valid = (syscall | eret) & WB_valid;



    assign exc_pc = syscall ? `EXC_ENTER_ADDR : cp0r_epc;
    
    assign exc_bus = {exc_valid,exc_pc};




    assign WB_wdest = rf_wdest & {5{WB_valid}};



    assign WB_pc = pc;
    assign HI_data = hi;
    assign LO_data = lo;

endmodule