data/full_repos/permissive/200314387/verilog/74163/test.v
 line:229: before: ">"
1: b'%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:3: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/74163,data/full_repos/permissive/200314387/../lib/assertion.v\n             data/full_repos/permissive/200314387/verilog/74163,data/full_repos/permissive/200314387/../lib/assertion.v.v\n             data/full_repos/permissive/200314387/verilog/74163,data/full_repos/permissive/200314387/../lib/assertion.v.sv\n             ../lib/assertion.v\n             ../lib/assertion.v.v\n             ../lib/assertion.v.sv\n             obj_dir/../lib/assertion.v\n             obj_dir/../lib/assertion.v.v\n             obj_dir/../lib/assertion.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:4: Cannot find include file: hct74163.v\n`include "hct74163.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:49: Unsupported or unknown PLI call: $timeformat\n  $timeformat(-9, 0, " ns", 10);\n  ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:61: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'bxxxx);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:61: syntax error, unexpected \',\'\n  `Equals(Q, 4\'bxxxx);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #300 \n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:66: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b0000);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:66: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b0000);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #300 \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:84: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b0001);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:84: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b0001);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #300\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #300\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:99: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1011);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:99: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b1011);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:113: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1011);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:113: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b1011);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:127: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1011);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:127: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b1011);\n           ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:136: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1011);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:136: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b1011);  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:141: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1011);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:141: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b1011);  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:140: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:146: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b0000);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:146: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b0000);  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:157: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b0000);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:157: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b0000);  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:163: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b0000);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:163: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b0000);  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:168: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b0000);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:168: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b0000);  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:173: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1110);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:173: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b1110);  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:179: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1110);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:179: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b1110);  \n           ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:180: Define or directive not defined: \'`Equals\'\n  `Equals(TC, 1\'b0);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:180: syntax error, unexpected \',\'\n  `Equals(TC, 1\'b0);  \n            ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:186: Define or directive not defined: \'`Equals\'\n  `Equals(TC, 1\'b0);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:186: syntax error, unexpected \',\'\n  `Equals(TC, 1\'b0);  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:187: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1110);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:187: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b1110);  \n           ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:191: Define or directive not defined: \'`Equals\'\n  `Equals(TC, 1\'b0);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:191: syntax error, unexpected \',\'\n  `Equals(TC, 1\'b0);  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:190: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:192: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1110);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:192: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b1110);  \n           ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:196: Define or directive not defined: \'`Equals\'\n  `Equals(TC, 1\'b1);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:196: syntax error, unexpected \',\'\n  `Equals(TC, 1\'b1);  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:195: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:197: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1111);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:197: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b1111);  \n           ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:201: Define or directive not defined: \'`Equals\'\n  `Equals(TC, 1\'b0);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:201: syntax error, unexpected \',\'\n  `Equals(TC, 1\'b0);  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74163/test.v:200: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:202: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1111);  \n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:202: syntax error, unexpected \',\'\n  `Equals(Q, 4\'b1111);  \n           ^\n%Error: data/full_repos/permissive/200314387/verilog/74163/test.v:203: Define or directive not defined: \'`Equals\'\n  `Equals(Q, 4\'b1111);  \n  ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module counter_74163_tb();
logic CP;
logic _MR;
logic CEP;
logic CET;
logic _PE;
logic [3:0] D;
logic [3:0] Q;

wire TC;

always @(*)  begin
    $display(" %t TEST : CP=%1b _MR=%1b CEP=%1b CET=%1b _PE=%1b D=%4b Q=%4b ", $time, CP, _MR, CEP, CET, _PE, D, Q);
end


hct74163 DUT
(
  .CP(CP),
  ._MR(_MR),
  .CEP(CEP),
  .CET(CET),
  ._PE(_PE),
  .D(D),

  .Q(Q),
  .TC(TC)
);

`define CLOCK_PULSE  \
  #300 \
  CP= 1'b0; \
  #300 \
  CP= 1'b1; \
  #300 \
  CP= 1'b0; \
  #300

initial begin


  $timeformat(-9, 0, " ns", 10);
  $display("[%t]: initial state", $time);

  CP = 1'b0;
  CEP = 1'b0;
  CET = 1'b0;
  _PE = 1'b1;
  D = 4'b1111;


  _MR = 1'b0;
  #100;
  `Equals(Q, 4'bxxxx);


  $display("[%t]: clock pulse", $time);
  `CLOCK_PULSE
  `Equals(Q, 4'b0000);


  _MR = 1'b1;
  #100;


  $display("[%t]: Load 1 as initial value", $time);
  D = 4'b0001;
  #10
  _PE = 1'b0;

  `CLOCK_PULSE 

  #100
  _PE = 1'b1;
  #100;

  `Equals(Q, 4'b0001);
  
  
  $display("[%t]: Regular count test", $time);
  CEP = 1'b1;
  CET = 1'b1;
  $display("COUNT %4b", Q);
  for (int i = 0; i < 10; i++)
  begin
    #300
    CP= 1'b1;
    #300
    CP= 1'b0;
  end

  `Equals(Q, 4'b1011);


  $display("[%t]", $time, " both CEP and CET have to be High to count");
  CEP = 1'b0;
  CET = 1'b1;
  #50;


  CP= 1'b1;
  #300
  CP= 1'b0;
  #300
  $display("NO COUNT %4b", Q);
  `Equals(Q, 4'b1011);


  $display("[%t]", $time, " both CEP and CET have to be High to count");
  CEP = 1'b1;
  CET = 1'b0;
  #50;


  CP= 1'b1;
  #300
  CP= 1'b0;
  #300
  $display("NO COUNT %4b", Q);
  `Equals(Q, 4'b1011);



  $display("[%t]", $time, " _MR test = _MR low");
  CEP = 1'b1;
  CET = 1'b1; 
  _MR= 1'b0;
  #300
  `Equals(Q, 4'b1011);
  
  $display("[%t]", $time, " _MR test = _MR low and CP low");
  CP= 1'b0;
  #300
  `Equals(Q, 4'b1011);
  
  $display("[%t]", $time, " _MR test = _MR low and CP high");
  CP= 1'b1;
  #300
  `Equals(Q, 4'b0000);
  



  $display("[%t]", $time, " _PE test = _MR hi and CP high");
  CP= 1'b1;
  CEP = 1'b1;
  CET = 1'b1; 
  _MR= 1'b1;
  #300
  `Equals(Q, 4'b0000);

  $display("[%t]", $time, " _PE test = _PE low but no load yet as no +ve CP");
  D=4'b1110;
  _PE=1'b0;
  #300
  `Equals(Q, 4'b0000);
  
  $display("[%t]", $time, " _PE test = _PE low but no load yet as no +ve CP");
  CP= 1'b0;
  #300
  `Equals(Q, 4'b0000);
  
  $display("[%t]", $time, " _PE test = _PE low expect load as +ve CP");
  CP= 1'b1;
  #300
  `Equals(Q, 4'b1110);
  



  $display("[%t]", $time, " overflow test");
  `Equals(Q, 4'b1110);
  `Equals(TC, 1'b0);
  CEP = 1'b1;
  CET = 1'b1; 
  _MR= 1'b1;
  _PE= 1'b1;
  #300
  `Equals(TC, 1'b0);
  `Equals(Q, 4'b1110);
  
  CP= 1'b0;
  #300
  `Equals(TC, 1'b0);
  `Equals(Q, 4'b1110);
  
  CP= 1'b1;
  #300
  `Equals(TC, 1'b1);
  `Equals(Q, 4'b1111);
  
  CET=1'b0;
  #300
  `Equals(TC, 1'b0);
  `Equals(Q, 4'b1111);
  `Equals(Q, 4'b1111);
  
end

endmodule
module counter_74163_tb();

logic CP;
logic _MR;
logic CEP;
logic CET;
logic _PE;
logic [3:0] D;
logic [3:0] Q;

wire TC;

always @(*)  begin
    $display(" %t TEST : CP=%1b _MR=%1b CEP=%1b CET=%1b _PE=%1b D=%4b Q=%4b ", $time, CP, _MR, CEP, CET, _PE, D, Q);
end


hct74163 DUT
(
  .CP(CP),
  ._MR(_MR),
  .CEP(CEP),
  .CET(CET),
  ._PE(_PE),
  .D(D),

  .Q(Q),
  .TC(TC)
);

`define CLOCK_PULSE  \
  #300 \
  CP= 1'b0; \
  #300 \
  CP= 1'b1; \
  #300 \
  CP= 1'b0; \
  #300

initial begin


  $timeformat(-9, 0, " ns", 10);
  $display("[%t]: initial state", $time);

  CP = 1'b0;
  CEP = 1'b0;
  CET = 1'b0;
  _PE = 1'b1;
  D = 4'b1111;


  _MR = 1'b0;
  #100;
  `Equals(Q, 4'bxxxx);


  $display("[%t]: clock pulse", $time);
  `CLOCK_PULSE
  `Equals(Q, 4'b0000);


  _MR = 1'b1;
  #100;


  $display("[%t]: Load 1 as initial value", $time);
  D = 4'b0001;
  #10
  _PE = 1'b0;

  `CLOCK_PULSE 

  #100
  _PE = 1'b1;
  #100;

  `Equals(Q, 4'b0001);
  
  
  $display("[%t]: Regular count test", $time);
  CEP = 1'b1;
  CET = 1'b1;
  $display("COUNT %4b", Q);
  for (int i = 0; i < 10; i++)
  begin
    #300
    CP= 1'b1;
    #300
    CP= 1'b0;
  end

  `Equals(Q, 4'b1011);


  $display("[%t]", $time, " both CEP and CET have to be High to count");
  CEP = 1'b0;
  CET = 1'b1;
  #50;


  CP= 1'b1;
  #300
  CP= 1'b0;
  #300
  $display("NO COUNT %4b", Q);
  `Equals(Q, 4'b1011);


  $display("[%t]", $time, " both CEP and CET have to be High to count");
  CEP = 1'b1;
  CET = 1'b0;
  #50;


  CP= 1'b1;
  #300
  CP= 1'b0;
  #300
  $display("NO COUNT %4b", Q);
  `Equals(Q, 4'b1011);



  $display("[%t]", $time, " _MR test = _MR low");
  CEP = 1'b1;
  CET = 1'b1; 
  _MR= 1'b0;
  #300
  `Equals(Q, 4'b1011);
  
  $display("[%t]", $time, " _MR test = _MR low and CP low");
  CP= 1'b0;
  #300
  `Equals(Q, 4'b1011);
  
  $display("[%t]", $time, " _MR test = _MR low and CP high");
  CP= 1'b1;
  #300
  `Equals(Q, 4'b0000);
  



  $display("[%t]", $time, " _PE test = _MR hi and CP high");
  CP= 1'b1;
  CEP = 1'b1;
  CET = 1'b1; 
  _MR= 1'b1;
  #300
  `Equals(Q, 4'b0000);

  $display("[%t]", $time, " _PE test = _PE low but no load yet as no +ve CP");
  D=4'b1110;
  _PE=1'b0;
  #300
  `Equals(Q, 4'b0000);
  
  $display("[%t]", $time, " _PE test = _PE low but no load yet as no +ve CP");
  CP= 1'b0;
  #300
  `Equals(Q, 4'b0000);
  
  $display("[%t]", $time, " _PE test = _PE low expect load as +ve CP");
  CP= 1'b1;
  #300
  `Equals(Q, 4'b1110);
  



  $display("[%t]", $time, " overflow test");
  `Equals(Q, 4'b1110);
  `Equals(TC, 1'b0);
  CEP = 1'b1;
  CET = 1'b1; 
  _MR= 1'b1;
  _PE= 1'b1;
  #300
  `Equals(TC, 1'b0);
  `Equals(Q, 4'b1110);
  
  CP= 1'b0;
  #300
  `Equals(TC, 1'b0);
  `Equals(Q, 4'b1110);
  
  CP= 1'b1;
  #300
  `Equals(TC, 1'b1);
  `Equals(Q, 4'b1111);
  
  CET=1'b0;
  #300
  `Equals(TC, 1'b0);
  `Equals(Q, 4'b1111);
  `Equals(Q, 4'b1111);
  
end

endmodule