data/full_repos/permissive/143278/ivltests/tern5.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern5.v:10: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s CONST \'2\'h0\' generates 2 bits.\n                                                                     : ... In instance main\n      foo = 2\'b00 ? 9\'b000111xxx : 9\'b01x01x01x;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern5.v:13: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s CONST \'2\'h1\' generates 2 bits.\n                                                                     : ... In instance main\n      foo = 2\'b01 ? 9\'b000111xxx : 9\'b01x01x01x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern5.v:16: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s CONST \'2\'bx\' generates 2 bits.\n                                                                     : ... In instance main\n      foo = 2\'b0x ? 9\'b000111xxx : 9\'b01x01x01x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern5.v:19: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s CONST \'2\'h3\' generates 2 bits.\n                                                                     : ... In instance main\n      foo = 2\'b11 ? 9\'b000111xxx : 9\'b01x01x01x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern5.v:22: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s CONST \'2\'b1x\' generates 2 bits.\n                                                                     : ... In instance main\n      foo = 2\'b1x ? 9\'b000111xxx : 9\'b01x01x01x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern5.v:26: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'bar\' generates 2 bits.\n                                                                     : ... In instance main\n      foo = bar? 9\'b000111xxx : 9\'b01x01x01x;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern5.v:30: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'bar\' generates 2 bits.\n                                                                     : ... In instance main\n      foo = bar? 9\'b000111xxx : 9\'b01x01x01x;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern5.v:34: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'bar\' generates 2 bits.\n                                                                     : ... In instance main\n      foo = bar? 9\'b000111xxx : 9\'b01x01x01x;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern5.v:38: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'bar\' generates 2 bits.\n                                                                     : ... In instance main\n      foo = bar? 9\'b000111xxx : 9\'b01x01x01x;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern5.v:42: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'bar\' generates 2 bits.\n                                                                     : ... In instance main\n      foo = bar? 9\'b000111xxx : 9\'b01x01x01x;\n               ^\n%Error: Exiting due to 10 warning(s)\n'
module main();

   reg [8:0] foo;

   reg [1:0] bar;
   initial begin
      foo = 2'b00 ? 9'b000111xxx : 9'b01x01x01x;
      $display("00: foo = %b", foo);

      foo = 2'b01 ? 9'b000111xxx : 9'b01x01x01x;
      $display("01: foo = %b", foo);

      foo = 2'b0x ? 9'b000111xxx : 9'b01x01x01x;
      $display("0x: foo = %b", foo);

      foo = 2'b11 ? 9'b000111xxx : 9'b01x01x01x;
      $display("11: foo = %b", foo);

      foo = 2'b1x ? 9'b000111xxx : 9'b01x01x01x;
      $display("1x: foo = %b", foo);

      bar = 2'b00;
      foo = bar? 9'b000111xxx : 9'b01x01x01x;
      $display("%b: foo = %b", bar, foo);

      bar = 2'b01;
      foo = bar? 9'b000111xxx : 9'b01x01x01x;
      $display("%b: foo = %b", bar, foo);

      bar = 2'b0x;
      foo = bar? 9'b000111xxx : 9'b01x01x01x;
      $display("%b: foo = %b", bar, foo);

      bar = 2'b11;
      foo = bar? 9'b000111xxx : 9'b01x01x01x;
      $display("%b: foo = %b", bar, foo);

      bar = 2'b1x;
      foo = bar? 9'b000111xxx : 9'b01x01x01x;
      $display("%b: foo = %b", bar, foo);

   end

endmodule
module main();


   reg [8:0] foo;

   reg [1:0] bar;
   initial begin
      foo = 2'b00 ? 9'b000111xxx : 9'b01x01x01x;
      $display("00: foo = %b", foo);

      foo = 2'b01 ? 9'b000111xxx : 9'b01x01x01x;
      $display("01: foo = %b", foo);

      foo = 2'b0x ? 9'b000111xxx : 9'b01x01x01x;
      $display("0x: foo = %b", foo);

      foo = 2'b11 ? 9'b000111xxx : 9'b01x01x01x;
      $display("11: foo = %b", foo);

      foo = 2'b1x ? 9'b000111xxx : 9'b01x01x01x;
      $display("1x: foo = %b", foo);

      bar = 2'b00;
      foo = bar? 9'b000111xxx : 9'b01x01x01x;
      $display("%b: foo = %b", bar, foo);

      bar = 2'b01;
      foo = bar? 9'b000111xxx : 9'b01x01x01x;
      $display("%b: foo = %b", bar, foo);

      bar = 2'b0x;
      foo = bar? 9'b000111xxx : 9'b01x01x01x;
      $display("%b: foo = %b", bar, foo);

      bar = 2'b11;
      foo = bar? 9'b000111xxx : 9'b01x01x01x;
      $display("%b: foo = %b", bar, foo);

      bar = 2'b1x;
      foo = bar? 9'b000111xxx : 9'b01x01x01x;
      $display("%b: foo = %b", bar, foo);

   end

endmodule