data/full_repos/permissive/124803629/src/Pipeline_CPU/DataMem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/124803629/src/Pipeline_CPU/DataMem.v:13: Bit extraction of array[255:0] requires 8 bit index, not 30 bits.\n                                                                                  : ... In instance DataMem\nassign rdata = (rd && (addr[31:2] < RAM_SIZE)) ? RAMDATA[addr[31:2]] : 32\'b0;\n                                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/124803629/src/Pipeline_CPU/DataMem.v:17: Bit extraction of array[255:0] requires 8 bit index, not 30 bits.\n                                                                                  : ... In instance DataMem\n  RAMDATA[addr[31:2]] <= wdata;\n         ^\n%Error: Exiting due to 2 warning(s)\n'
module DataMem (reset,clk,rd,wr,addr,wdata,rdata);
input reset,clk;
input rd,wr;
input [31:0] addr;
input [31:0] wdata;
output [31:0] rdata;

parameter RAM_SIZE = 256;
reg [31:0] RAMDATA [RAM_SIZE-1:0];

assign rdata = (rd && (addr[31:2] < RAM_SIZE)) ? RAMDATA[addr[31:2]] : 32'b0;

always@(posedge clk) begin
	if(wr && (addr[31:2] < RAM_SIZE))
		RAMDATA[addr[31:2]] <= wdata;
end

endmodule
module DataMem (reset,clk,rd,wr,addr,wdata,rdata);

input reset,clk;
input rd,wr;
input [31:0] addr;
input [31:0] wdata;
output [31:0] rdata;

parameter RAM_SIZE = 256;
reg [31:0] RAMDATA [RAM_SIZE-1:0];

assign rdata = (rd && (addr[31:2] < RAM_SIZE)) ? RAMDATA[addr[31:2]] : 32'b0;

always@(posedge clk) begin
	if(wr && (addr[31:2] < RAM_SIZE))
		RAMDATA[addr[31:2]] <= wdata;
end

endmodule