data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:358: Cannot find file containing module: 'NOR3A'\n    NOR3A \\SM_8S_1_i_0_a3[3]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .C(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A.sv\n             NOR3A\n             NOR3A.v\n             NOR3A.sv\n             obj_dir/NOR3A\n             obj_dir/NOR3A.v\n             obj_dir/NOR3A.sv\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:360: Cannot find file containing module: 'NOR2A'\n    NOR2A \\SM_8S_1_i_0_1[3]  (.A(SM_8S_1_i_0_a3_0_0), .B(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:362: Cannot find file containing module: 'NOR2B'\n    NOR2B \\SM_8S_1_i_0_o2[1]  (.A(Disp_dat[3]), .B(Disp_dat[1]), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:364: Cannot find file containing module: 'NOR3B'\n    NOR3B \\SM_8S_1_i_i_a2[6]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:366: Cannot find file containing module: 'AX1C'\n    AX1C \\SM_8S_1_i_i_x2[6]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:368: Cannot find file containing module: 'GND'\n    GND GND_i_0 (.Y(GND_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:369: Cannot find file containing module: 'NOR2'\n    NOR2 \\SM_8S_1_0_0_o2[5]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:371: Cannot find file containing module: 'OR2B'\n    OR2B \\SM_8S_1_i_0_a3_0[1]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:373: Cannot find file containing module: 'AO1C'\n    AO1C \\SM_8S_1_0_0[5]  (.A(N_17), .B(Disp_dat[0]), .C(N_15_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:375: Cannot find file containing module: 'VCC'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:376: Cannot find file containing module: 'OR3C'\n    OR3C \\SM_8S_1_0_i_a3_0[2]  (.A(Disp_dat[3]), .B(Disp_dat[0]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:378: Cannot find file containing module: 'AO1A'\n    AO1A \\SM_8S_1_i_i_a3[6]  (.A(Disp_dat[0]), .B(Disp_dat[2]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:380: Cannot find file containing module: 'AOI1B'\n    AOI1B \\SM_8S_1_i_i_a3_0[4]  (.A(Disp_dat[2]), .B(Disp_dat[1]), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:382: Cannot find file containing module: 'GND'\n    GND GND_i (.Y(GND));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:383: Cannot find file containing module: 'XOR2'\n    XOR2 \\SM_8S_1_i_0_x2[0]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:385: Cannot find file containing module: 'OA1B'\n    OA1B \\SM_8S_1_i_0[1]  (.A(N_19), .B(\\SM_8S_1_i_0_a3_0[1]_net_1 ), \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:387: Cannot find file containing module: 'VCC'\n    VCC VCC_i_0 (.Y(VCC_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:388: Cannot find file containing module: 'OR2B'\n    OR2B \\SM_8S_1_i_i_1[6]  (.A(N_70), .B(N_15_i), .Y(Seg_c[6]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:389: Cannot find file containing module: 'OR2A'\n    OR2A \\SM_8S_1_i_0_a3_0[0]  (.A(N_19), .B(N_14_i_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:683: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_3[2]  (.A(Q_NS_e2_0_a2_1_0), .B(N_30), .Y(N_40));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:684: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_2[2]  (.A(Q_NS[2]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:686: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[1]  (.A(N_34), .B(Q_NS_e1_0_0), .C(N_39_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:688: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_0[4]  (.A(Q_NS[4]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:690: Cannot find file containing module: 'OR2B'\n    OR2B Q_NS_e1_0_a2_4 (.A(N_30), .B(one_seond_clk_0_Cout), .Y(N_62));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:691: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_1[7]  (.A(Q_NS[7]), .B(Q_NSlde_i_o2tt_m1_0_a2), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:693: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[7]  (.A(N_56), .B(N_58), .C(N_57), .Y(Q_NS_e7));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:694: Cannot find file containing module: 'OR3'\n    OR3 \\Q_NS_RNO_2[3]  (.A(N_19), .B(Q_NS[3]), .C(N_62), .Y(N_44));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:695: Cannot find file containing module: 'OA1'\n    OA1 \\Q_NS_RNO_2[6]  (.A(N_22), .B(Q_NS[5]), .C(Q_NS[6]), .Y(\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:697: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_0[3]  (.A(Q_NS_e3_0_a2_0), .B(N_30), .Y(N_43));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:698: Cannot find file containing module: 'NOR2B'\n    NOR2B \\Q_NS_RNO_3[3]  (.A(Q_NS[3]), .B(N_19), .Y(Q_NS_e3_0_a2_0));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:699: Cannot find file containing module: 'VCC'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:700: Cannot find file containing module: 'NOR2B'\n    NOR2B \\Q_NS_RNO_3[5]  (.A(Q_NS[5]), .B(N_22), .Y(Q_NS_e5_0_a2_0_0));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:701: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNO_0[7]  (.A(N_30), .B(Q_NS[7]), .C(N_26), .Y(N_56));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:702: Cannot find file containing module: 'NOR3'\n    NOR3 \\Q_NS_RNISBRL[6]  (.A(N_22), .B(Q_NS[5]), .C(Q_NS[6]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:704: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[0]  (.D(Q_NS_e0), .CLK(Clk_c), .Q(Q_NS[0]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:705: Cannot find file containing module: 'AO1C'\n    AO1C \\Q_NS_RNO[2]  (.A(N_19), .B(N_24), .C(Q_NS_e2_0_2), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:707: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNIF75S[7]  (.A(one_seond_clk_0_Cout), .B(N_26), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:709: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNO_1[2]  (.A(Green2_c), .B(N_16), .C(N_30), .Y(N_41));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:710: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[7]  (.D(Q_NS_e7), .CLK(Clk_c), .Q(Q_NS[7]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:711: Cannot find file containing module: 'NOR2A'\n    NOR2A Q_NS_e2_0_a2_4_1 (.A(current_state[0]), .B(Red1_c), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:713: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[5]  (.D(Q_NS_e5), .CLK(Clk_c), .Q(Q_NS[5]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:714: Cannot find file containing module: 'NOR3C'\n    NOR3C \\Q_NS_RNO_0[2]  (.A(N_41), .B(Q_NS_e2_0_0), .C(N_39_i), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:716: Cannot find file containing module: 'NOR2'\n    NOR2 un1_Reset_1_i_i_a2 (.A(Ld_i), .B(Reset_c), .Y(N_30));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:717: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[3]  (.A(N_43), .B(N_45), .C(N_44), .Y(Q_NS_e3));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:718: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_0[6]  (.A(Q_NS[6]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:720: Cannot find file containing module: 'OR3A'\n    OR3A \\Q_NS_RNO_2[7]  (.A(N_26), .B(N_62), .C(Q_NS[7]), .Y(N_57));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:721: Cannot find file containing module: 'OA1'\n    OA1 \\Q_NS_RNO_4[2]  (.A(Q_NS[0]), .B(Q_NS[1]), .C(Q_NS[2]), .Y(\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:723: Cannot find file containing module: 'OR3A'\n    OR3A \\Q_NS_RNO_1[5]  (.A(N_24), .B(N_22), .C(Q_NS[5]), .Y(N_51));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:724: Cannot find file containing module: 'AO1C'\n    AO1C \\Q_NS_RNO[6]  (.A(N_62), .B(N_26), .C(Q_NS_e6_0_0), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:726: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_1[6]  (.A(Q_NS_e6_0_a2_0), .B(N_30), .Y(N_54));\n    ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module timer_NS(
       current_state,
       Q_NS_0,
       Clk_c,
       Red1_c,
       Yellow1_c,
       Q_NSlde_i_o2tt_m1_0_a2,
       N_60_0,
       Ld_i,
       Reset_c,
       timer_NS_0_Done_NS,
       one_seond_clk_0_Cout,
       N_16
    );
input  [0:0] current_state;
output [7:0] Q_NS_0;
input  Clk_c;
input  Red1_c;
input  Yellow1_c;
output Q_NSlde_i_o2tt_m1_0_a2;
input  N_60_0;
input  Ld_i;
input  Reset_c;
output timer_NS_0_Done_NS;
input  one_seond_clk_0_Cout;
output N_16;

    wire Q_NS_e2_0_2, Q_NS_e2_0_0, N_40, N_404, Q_NS_e2_0_a2_2_0, N_42, 
        Done_NS_0_a2_m3_e_5, Done_NS_0_a2_m3_e_2, Done_NS_0_a2_m3_e_1, 
        Done_NS_0_a2_m3_e_3, N_18, N_60, Q_NS_e2_0_a2_4_1_net_1, 
        Q_NS_e1, N_35, Q_NS_e1_0_0, N_34, Q_NS_e2, N_19, N_24, Q_NS_e7, 
        N_81, Q_NS_e7_0_0, Q_NS_e6, N_54, N_55, Q_NS_e5, Q_NS_e5_0_0, 
        N_51, Q_NS_e4, Q_NS_e4_0_0, N_46, Q_NS_e0, N_62, Q_NS_e0_0_0, 
        Q_NS_e3, N_43, Q_NS_e3_0_0, N_44, N_23, N_26, N_22, N_52, N_47, 
        N_36, Q_NS_e7_0_a2_0, N_58, Q_NS_e0_0_a2_0_0_net_1, N_45, N_33, 
        Q_NS_e6_0_a2_0, Q_NS_e3_0_a2_0, Q_NS_e4_0_a2_0_0, 
        Q_NS_e5_0_a2_0_0, Q_NS_e2_0_a2_1_0, Q_NS_e1_0_a2_1_0, GND, VCC, 
        GND_0, VCC_0;
    
    OA1C \Q_NS_RNO_3[2]  (.A(N_60), .B(Ld_i), .C(Reset_c), .Y(N_404));
    OR3B \Q_NS_RNO_2[2]  (.A(Ld_i), .B(Q_NS_e2_0_a2_1_0), .C(Reset_c), 
        .Y(N_40));
    OR3C \Q_NS_RNO[1]  (.A(N_35), .B(Q_NS_e1_0_0), .C(N_34), .Y(
        Q_NS_e1));
    OR3A \Q_NS_RNIEA9C[6]  (.A(N_22), .B(Q_NS_0[5]), .C(Q_NS_0[6]), .Y(
        N_26));
    AOI1B \Q_NS_RNO_0[4]  (.A(Q_NS_0[4]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .C(N_47), .Y(Q_NS_e4_0_0));
    OR3B Q_NS_e1_0_a2_4 (.A(Ld_i), .B(N_16), .C(Reset_c), .Y(N_62));
    OR2 \Q_NS_RNIQJHH2[6]  (.A(N_62), .B(N_26), .Y(N_81));
    NOR3A Q_NS_e1_0_o2 (.A(N_60_0), .B(Reset_c), .C(N_60), .Y(N_23));
    NOR3B \Q_NS_RNO_1[7]  (.A(Ld_i), .B(Q_NS_0[7]), .C(Reset_c), .Y(
        Q_NS_e7_0_a2_0));
    OAI1 \Q_NS_RNO[7]  (.A(N_81), .B(Q_NS_0[7]), .C(Q_NS_e7_0_0), .Y(
        Q_NS_e7));
    NOR2B \Q_NS_RNO_6[2]  (.A(Q_NS_0[2]), .B(N_18), .Y(
        Q_NS_e2_0_a2_1_0));
    OR3 \Q_NS_RNO_2[3]  (.A(N_19), .B(Q_NS_0[3]), .C(N_62), .Y(N_44));
    OA1A \Q_NS_RNO_2[6]  (.A(N_22), .B(Q_NS_0[5]), .C(Q_NS_0[6]), .Y(
        Q_NS_e6_0_a2_0));
    OR3B \Q_NS_RNO_0[3]  (.A(Ld_i), .B(Q_NS_e3_0_a2_0), .C(Reset_c), 
        .Y(N_43));
    NOR2B \Q_NS_RNO_3[3]  (.A(Q_NS_0[3]), .B(N_19), .Y(Q_NS_e3_0_a2_0));
    VCC VCC_i (.Y(VCC));
    NOR2A \Q_NS_RNO_3[5]  (.A(Q_NS_0[5]), .B(N_22), .Y(
        Q_NS_e5_0_a2_0_0));
    NOR2 \Q_NS_RNI5GG3[4]  (.A(Q_NS_0[3]), .B(Q_NS_0[4]), .Y(
        Done_NS_0_a2_m3_e_2));
    AOI1B \Q_NS_RNO_0[7]  (.A(Q_NS_e7_0_a2_0), .B(N_26), .C(N_58), .Y(
        Q_NS_e7_0_0));
    OA1 \Q_NS_RNO_0[0]  (.A(Ld_i), .B(Q_NS_e0_0_a2_0_0_net_1), .C(N_33)
        , .Y(Q_NS_e0_0_0));
    NOR3C \Q_NS_RNI0NND[2]  (.A(Done_NS_0_a2_m3_e_2), .B(
        Done_NS_0_a2_m3_e_1), .C(Done_NS_0_a2_m3_e_3), .Y(
        Done_NS_0_a2_m3_e_5));
    DFN1 \Q_NS[0]  (.D(Q_NS_e0), .CLK(Clk_c), .Q(Q_NS_0[0]));
    AO1C \Q_NS_RNO[2]  (.A(N_19), .B(N_24), .C(Q_NS_e2_0_2), .Y(
        Q_NS_e2));
    AOI1B \Q_NS_RNO_1[2]  (.A(Q_NS_e2_0_a2_2_0), .B(N_16), .C(N_42), 
        .Y(Q_NS_e2_0_0));
    OR2 \Q_NS_RNI0Q75[2]  (.A(Q_NS_0[2]), .B(N_18), .Y(N_19));
    NOR2 \Q_NS_RNI7OG3[2]  (.A(Q_NS_0[7]), .B(Q_NS_0[2]), .Y(
        Done_NS_0_a2_m3_e_1));
    NOR3 \Q_NS_RNI5AO8[4]  (.A(N_19), .B(Q_NS_0[3]), .C(Q_NS_0[4]), .Y(
        N_22));
    DFN1 \Q_NS[7]  (.D(Q_NS_e7), .CLK(Clk_c), .Q(Q_NS_0[7]));
    OR2B Q_NS_e2_0_a2_4_1 (.A(Red1_c), .B(current_state[0]), .Y(
        Q_NS_e2_0_a2_4_1_net_1));
    DFN1 \Q_NS[5]  (.D(Q_NS_e5), .CLK(Clk_c), .Q(Q_NS_0[5]));
    NOR3C \Q_NS_RNO_0[2]  (.A(Q_NS_e2_0_0), .B(N_40), .C(N_404), .Y(
        Q_NS_e2_0_2));
    OR3C \Q_NS_RNO[3]  (.A(N_43), .B(Q_NS_e3_0_0), .C(N_44), .Y(
        Q_NS_e3));
    OR3B \Q_NS_RNO_0[6]  (.A(Ld_i), .B(Q_NS_e6_0_a2_0), .C(Reset_c), 
        .Y(N_54));
    OR2B \Q_NS_RNO_2[7]  (.A(Q_NS_0[7]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .Y(N_58));
    OA1C \Q_NS_RNO_4[2]  (.A(Ld_i), .B(Reset_c), .C(Yellow1_c), .Y(
        Q_NS_e2_0_a2_2_0));
    OR3B \Q_NS_RNO_1[5]  (.A(N_22), .B(N_24), .C(Q_NS_0[5]), .Y(N_51));
    OR3C \Q_NS_RNO[6]  (.A(N_54), .B(N_55), .C(N_81), .Y(Q_NS_e6));
    OR2B \Q_NS_RNO_1[6]  (.A(Q_NS_0[6]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .Y(N_55));
    DFN1 \Q_NS[6]  (.D(Q_NS_e6), .CLK(Clk_c), .Q(Q_NS_0[6]));
    DFN1 \Q_NS[3]  (.D(Q_NS_e3), .CLK(Clk_c), .Q(Q_NS_0[3]));
    DFN1 \Q_NS[2]  (.D(Q_NS_e2), .CLK(Clk_c), .Q(Q_NS_0[2]));
    GND GND_i (.Y(GND));
    NOR2B \Q_NS_RNO_3[1]  (.A(Q_NS_0[0]), .B(Q_NS_0[1]), .Y(
        Q_NS_e1_0_a2_1_0));
    OR2A Q_NS_e2_0_o2 (.A(Ld_i), .B(one_seond_clk_0_Cout), .Y(N_16));
    OR2B \Q_NS_RNO_1[4]  (.A(N_24), .B(N_22), .Y(N_46));
    OA1 \Q_NS_RNO_3[4]  (.A(N_19), .B(Q_NS_0[3]), .C(Q_NS_0[4]), .Y(
        Q_NS_e4_0_a2_0_0));
    OR3B \Q_NS_RNO_2[5]  (.A(Ld_i), .B(Q_NS_e5_0_a2_0_0), .C(Reset_c), 
        .Y(N_52));
    NOR2 Q_NSlde_i_o2tt_m1_0_a2_inst_1 (.A(one_seond_clk_0_Cout), .B(
        Reset_c), .Y(Q_NSlde_i_o2tt_m1_0_a2));
    AOI1B \Q_NS_RNO_0[5]  (.A(Q_NS_0[5]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .C(N_52), .Y(Q_NS_e5_0_0));
    OR3B \Q_NS_RNO_2[4]  (.A(Ld_i), .B(Q_NS_e4_0_a2_0_0), .C(Reset_c), 
        .Y(N_47));
    NOR3A \Q_NS_RNIKEM6[6]  (.A(one_seond_clk_0_Cout), .B(Q_NS_0[6]), 
        .C(Q_NS_0[5]), .Y(Done_NS_0_a2_m3_e_3));
    NOR2A Q_NS_e2_0_a2_4 (.A(N_16), .B(Q_NS_e2_0_a2_4_1_net_1), .Y(
        N_60));
    OR3C \Q_NS_RNO[4]  (.A(N_35), .B(Q_NS_e4_0_0), .C(N_46), .Y(
        Q_NS_e4));
    DFN1 \Q_NS[1]  (.D(Q_NS_e1), .CLK(Clk_c), .Q(Q_NS_0[1]));
    OR2B \Q_NS_RNO_4[3]  (.A(Q_NS_0[3]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .Y(N_45));
    OR2B \Q_NS_RNO_1[0]  (.A(Q_NS_0[0]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .Y(N_33));
    OA1 \Q_NS_RNO_1[3]  (.A(Ld_i), .B(Q_NS_e0_0_a2_0_0_net_1), .C(N_45)
        , .Y(Q_NS_e3_0_0));
    OR3C \Q_NS_RNO[5]  (.A(N_35), .B(Q_NS_e5_0_0), .C(N_51), .Y(
        Q_NS_e5));
    OR3B \Q_NS_RNO_2[1]  (.A(Ld_i), .B(Q_NS_e1_0_a2_1_0), .C(Reset_c), 
        .Y(N_36));
    OR2A \Q_NS_RNO_1[1]  (.A(N_24), .B(N_18), .Y(N_34));
    DFN1 \Q_NS[4]  (.D(Q_NS_e4), .CLK(Clk_c), .Q(Q_NS_0[4]));
    OR2 \Q_NS_RNIVNF3[0]  (.A(Q_NS_0[1]), .B(Q_NS_0[0]), .Y(N_18));
    OR2A Q_NS_e1_0_o2_0 (.A(N_62), .B(Reset_c), .Y(N_24));
    OR2B \Q_NS_RNO_5[2]  (.A(Q_NS_0[2]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .Y(N_42));
    OAI1 \Q_NS_RNO[0]  (.A(N_62), .B(Q_NS_0[0]), .C(Q_NS_e0_0_0), .Y(
        Q_NS_e0));
    OR2A \Q_NS_RNIVE7H[0]  (.A(Done_NS_0_a2_m3_e_5), .B(N_18), .Y(
        timer_NS_0_Done_NS));
    OR2A Q_NS_e0_0_a2_0_0 (.A(Yellow1_c), .B(Reset_c), .Y(
        Q_NS_e0_0_a2_0_0_net_1));
    AOI1B \Q_NS_RNO_0[1]  (.A(Q_NS_0[1]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .C(N_36), .Y(Q_NS_e1_0_0));
    VCC VCC_i_0 (.Y(VCC_0));
    AO1A Q_NS_e1_0_a2_0 (.A(Reset_c), .B(Ld_i), .C(N_23), .Y(N_35));
    GND GND_i_0 (.Y(GND_0));
    
endmodule
module timer_NS(
       current_state,
       Q_NS_0,
       Clk_c,
       Red1_c,
       Yellow1_c,
       Q_NSlde_i_o2tt_m1_0_a2,
       N_60_0,
       Ld_i,
       Reset_c,
       timer_NS_0_Done_NS,
       one_seond_clk_0_Cout,
       N_16
    );

input  [0:0] current_state;
output [7:0] Q_NS_0;
input  Clk_c;
input  Red1_c;
input  Yellow1_c;
output Q_NSlde_i_o2tt_m1_0_a2;
input  N_60_0;
input  Ld_i;
input  Reset_c;
output timer_NS_0_Done_NS;
input  one_seond_clk_0_Cout;
output N_16;

    wire Q_NS_e2_0_2, Q_NS_e2_0_0, N_40, N_404, Q_NS_e2_0_a2_2_0, N_42, 
        Done_NS_0_a2_m3_e_5, Done_NS_0_a2_m3_e_2, Done_NS_0_a2_m3_e_1, 
        Done_NS_0_a2_m3_e_3, N_18, N_60, Q_NS_e2_0_a2_4_1_net_1, 
        Q_NS_e1, N_35, Q_NS_e1_0_0, N_34, Q_NS_e2, N_19, N_24, Q_NS_e7, 
        N_81, Q_NS_e7_0_0, Q_NS_e6, N_54, N_55, Q_NS_e5, Q_NS_e5_0_0, 
        N_51, Q_NS_e4, Q_NS_e4_0_0, N_46, Q_NS_e0, N_62, Q_NS_e0_0_0, 
        Q_NS_e3, N_43, Q_NS_e3_0_0, N_44, N_23, N_26, N_22, N_52, N_47, 
        N_36, Q_NS_e7_0_a2_0, N_58, Q_NS_e0_0_a2_0_0_net_1, N_45, N_33, 
        Q_NS_e6_0_a2_0, Q_NS_e3_0_a2_0, Q_NS_e4_0_a2_0_0, 
        Q_NS_e5_0_a2_0_0, Q_NS_e2_0_a2_1_0, Q_NS_e1_0_a2_1_0, GND, VCC, 
        GND_0, VCC_0;
    
    OA1C \Q_NS_RNO_3[2]  (.A(N_60), .B(Ld_i), .C(Reset_c), .Y(N_404));
    OR3B \Q_NS_RNO_2[2]  (.A(Ld_i), .B(Q_NS_e2_0_a2_1_0), .C(Reset_c), 
        .Y(N_40));
    OR3C \Q_NS_RNO[1]  (.A(N_35), .B(Q_NS_e1_0_0), .C(N_34), .Y(
        Q_NS_e1));
    OR3A \Q_NS_RNIEA9C[6]  (.A(N_22), .B(Q_NS_0[5]), .C(Q_NS_0[6]), .Y(
        N_26));
    AOI1B \Q_NS_RNO_0[4]  (.A(Q_NS_0[4]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .C(N_47), .Y(Q_NS_e4_0_0));
    OR3B Q_NS_e1_0_a2_4 (.A(Ld_i), .B(N_16), .C(Reset_c), .Y(N_62));
    OR2 \Q_NS_RNIQJHH2[6]  (.A(N_62), .B(N_26), .Y(N_81));
    NOR3A Q_NS_e1_0_o2 (.A(N_60_0), .B(Reset_c), .C(N_60), .Y(N_23));
    NOR3B \Q_NS_RNO_1[7]  (.A(Ld_i), .B(Q_NS_0[7]), .C(Reset_c), .Y(
        Q_NS_e7_0_a2_0));
    OAI1 \Q_NS_RNO[7]  (.A(N_81), .B(Q_NS_0[7]), .C(Q_NS_e7_0_0), .Y(
        Q_NS_e7));
    NOR2B \Q_NS_RNO_6[2]  (.A(Q_NS_0[2]), .B(N_18), .Y(
        Q_NS_e2_0_a2_1_0));
    OR3 \Q_NS_RNO_2[3]  (.A(N_19), .B(Q_NS_0[3]), .C(N_62), .Y(N_44));
    OA1A \Q_NS_RNO_2[6]  (.A(N_22), .B(Q_NS_0[5]), .C(Q_NS_0[6]), .Y(
        Q_NS_e6_0_a2_0));
    OR3B \Q_NS_RNO_0[3]  (.A(Ld_i), .B(Q_NS_e3_0_a2_0), .C(Reset_c), 
        .Y(N_43));
    NOR2B \Q_NS_RNO_3[3]  (.A(Q_NS_0[3]), .B(N_19), .Y(Q_NS_e3_0_a2_0));
    VCC VCC_i (.Y(VCC));
    NOR2A \Q_NS_RNO_3[5]  (.A(Q_NS_0[5]), .B(N_22), .Y(
        Q_NS_e5_0_a2_0_0));
    NOR2 \Q_NS_RNI5GG3[4]  (.A(Q_NS_0[3]), .B(Q_NS_0[4]), .Y(
        Done_NS_0_a2_m3_e_2));
    AOI1B \Q_NS_RNO_0[7]  (.A(Q_NS_e7_0_a2_0), .B(N_26), .C(N_58), .Y(
        Q_NS_e7_0_0));
    OA1 \Q_NS_RNO_0[0]  (.A(Ld_i), .B(Q_NS_e0_0_a2_0_0_net_1), .C(N_33)
        , .Y(Q_NS_e0_0_0));
    NOR3C \Q_NS_RNI0NND[2]  (.A(Done_NS_0_a2_m3_e_2), .B(
        Done_NS_0_a2_m3_e_1), .C(Done_NS_0_a2_m3_e_3), .Y(
        Done_NS_0_a2_m3_e_5));
    DFN1 \Q_NS[0]  (.D(Q_NS_e0), .CLK(Clk_c), .Q(Q_NS_0[0]));
    AO1C \Q_NS_RNO[2]  (.A(N_19), .B(N_24), .C(Q_NS_e2_0_2), .Y(
        Q_NS_e2));
    AOI1B \Q_NS_RNO_1[2]  (.A(Q_NS_e2_0_a2_2_0), .B(N_16), .C(N_42), 
        .Y(Q_NS_e2_0_0));
    OR2 \Q_NS_RNI0Q75[2]  (.A(Q_NS_0[2]), .B(N_18), .Y(N_19));
    NOR2 \Q_NS_RNI7OG3[2]  (.A(Q_NS_0[7]), .B(Q_NS_0[2]), .Y(
        Done_NS_0_a2_m3_e_1));
    NOR3 \Q_NS_RNI5AO8[4]  (.A(N_19), .B(Q_NS_0[3]), .C(Q_NS_0[4]), .Y(
        N_22));
    DFN1 \Q_NS[7]  (.D(Q_NS_e7), .CLK(Clk_c), .Q(Q_NS_0[7]));
    OR2B Q_NS_e2_0_a2_4_1 (.A(Red1_c), .B(current_state[0]), .Y(
        Q_NS_e2_0_a2_4_1_net_1));
    DFN1 \Q_NS[5]  (.D(Q_NS_e5), .CLK(Clk_c), .Q(Q_NS_0[5]));
    NOR3C \Q_NS_RNO_0[2]  (.A(Q_NS_e2_0_0), .B(N_40), .C(N_404), .Y(
        Q_NS_e2_0_2));
    OR3C \Q_NS_RNO[3]  (.A(N_43), .B(Q_NS_e3_0_0), .C(N_44), .Y(
        Q_NS_e3));
    OR3B \Q_NS_RNO_0[6]  (.A(Ld_i), .B(Q_NS_e6_0_a2_0), .C(Reset_c), 
        .Y(N_54));
    OR2B \Q_NS_RNO_2[7]  (.A(Q_NS_0[7]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .Y(N_58));
    OA1C \Q_NS_RNO_4[2]  (.A(Ld_i), .B(Reset_c), .C(Yellow1_c), .Y(
        Q_NS_e2_0_a2_2_0));
    OR3B \Q_NS_RNO_1[5]  (.A(N_22), .B(N_24), .C(Q_NS_0[5]), .Y(N_51));
    OR3C \Q_NS_RNO[6]  (.A(N_54), .B(N_55), .C(N_81), .Y(Q_NS_e6));
    OR2B \Q_NS_RNO_1[6]  (.A(Q_NS_0[6]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .Y(N_55));
    DFN1 \Q_NS[6]  (.D(Q_NS_e6), .CLK(Clk_c), .Q(Q_NS_0[6]));
    DFN1 \Q_NS[3]  (.D(Q_NS_e3), .CLK(Clk_c), .Q(Q_NS_0[3]));
    DFN1 \Q_NS[2]  (.D(Q_NS_e2), .CLK(Clk_c), .Q(Q_NS_0[2]));
    GND GND_i (.Y(GND));
    NOR2B \Q_NS_RNO_3[1]  (.A(Q_NS_0[0]), .B(Q_NS_0[1]), .Y(
        Q_NS_e1_0_a2_1_0));
    OR2A Q_NS_e2_0_o2 (.A(Ld_i), .B(one_seond_clk_0_Cout), .Y(N_16));
    OR2B \Q_NS_RNO_1[4]  (.A(N_24), .B(N_22), .Y(N_46));
    OA1 \Q_NS_RNO_3[4]  (.A(N_19), .B(Q_NS_0[3]), .C(Q_NS_0[4]), .Y(
        Q_NS_e4_0_a2_0_0));
    OR3B \Q_NS_RNO_2[5]  (.A(Ld_i), .B(Q_NS_e5_0_a2_0_0), .C(Reset_c), 
        .Y(N_52));
    NOR2 Q_NSlde_i_o2tt_m1_0_a2_inst_1 (.A(one_seond_clk_0_Cout), .B(
        Reset_c), .Y(Q_NSlde_i_o2tt_m1_0_a2));
    AOI1B \Q_NS_RNO_0[5]  (.A(Q_NS_0[5]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .C(N_52), .Y(Q_NS_e5_0_0));
    OR3B \Q_NS_RNO_2[4]  (.A(Ld_i), .B(Q_NS_e4_0_a2_0_0), .C(Reset_c), 
        .Y(N_47));
    NOR3A \Q_NS_RNIKEM6[6]  (.A(one_seond_clk_0_Cout), .B(Q_NS_0[6]), 
        .C(Q_NS_0[5]), .Y(Done_NS_0_a2_m3_e_3));
    NOR2A Q_NS_e2_0_a2_4 (.A(N_16), .B(Q_NS_e2_0_a2_4_1_net_1), .Y(
        N_60));
    OR3C \Q_NS_RNO[4]  (.A(N_35), .B(Q_NS_e4_0_0), .C(N_46), .Y(
        Q_NS_e4));
    DFN1 \Q_NS[1]  (.D(Q_NS_e1), .CLK(Clk_c), .Q(Q_NS_0[1]));
    OR2B \Q_NS_RNO_4[3]  (.A(Q_NS_0[3]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .Y(N_45));
    OR2B \Q_NS_RNO_1[0]  (.A(Q_NS_0[0]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .Y(N_33));
    OA1 \Q_NS_RNO_1[3]  (.A(Ld_i), .B(Q_NS_e0_0_a2_0_0_net_1), .C(N_45)
        , .Y(Q_NS_e3_0_0));
    OR3C \Q_NS_RNO[5]  (.A(N_35), .B(Q_NS_e5_0_0), .C(N_51), .Y(
        Q_NS_e5));
    OR3B \Q_NS_RNO_2[1]  (.A(Ld_i), .B(Q_NS_e1_0_a2_1_0), .C(Reset_c), 
        .Y(N_36));
    OR2A \Q_NS_RNO_1[1]  (.A(N_24), .B(N_18), .Y(N_34));
    DFN1 \Q_NS[4]  (.D(Q_NS_e4), .CLK(Clk_c), .Q(Q_NS_0[4]));
    OR2 \Q_NS_RNIVNF3[0]  (.A(Q_NS_0[1]), .B(Q_NS_0[0]), .Y(N_18));
    OR2A Q_NS_e1_0_o2_0 (.A(N_62), .B(Reset_c), .Y(N_24));
    OR2B \Q_NS_RNO_5[2]  (.A(Q_NS_0[2]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .Y(N_42));
    OAI1 \Q_NS_RNO[0]  (.A(N_62), .B(Q_NS_0[0]), .C(Q_NS_e0_0_0), .Y(
        Q_NS_e0));
    OR2A \Q_NS_RNIVE7H[0]  (.A(Done_NS_0_a2_m3_e_5), .B(N_18), .Y(
        timer_NS_0_Done_NS));
    OR2A Q_NS_e0_0_a2_0_0 (.A(Yellow1_c), .B(Reset_c), .Y(
        Q_NS_e0_0_a2_0_0_net_1));
    AOI1B \Q_NS_RNO_0[1]  (.A(Q_NS_0[1]), .B(Q_NSlde_i_o2tt_m1_0_a2), 
        .C(N_36), .Y(Q_NS_e1_0_0));
    VCC VCC_i_0 (.Y(VCC_0));
    AO1A Q_NS_e1_0_a2_0 (.A(Reset_c), .B(Ld_i), .C(N_23), .Y(N_35));
    GND GND_i_0 (.Y(GND_0));
    
endmodule