data/full_repos/permissive/112823543/Avalon_LedPanel/LedMemory_Avalon.v
1: b"%Error: data/full_repos/permissive/112823543/Avalon_LedPanel/LedMemory_Avalon.v:116: Cannot find file containing module: 'LedPanel'\n  LedPanel #(\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/112823543/Avalon_LedPanel,data/full_repos/permissive/112823543/LedPanel\n             data/full_repos/permissive/112823543/Avalon_LedPanel,data/full_repos/permissive/112823543/LedPanel.v\n             data/full_repos/permissive/112823543/Avalon_LedPanel,data/full_repos/permissive/112823543/LedPanel.sv\n             LedPanel\n             LedPanel.v\n             LedPanel.sv\n             obj_dir/LedPanel\n             obj_dir/LedPanel.v\n             obj_dir/LedPanel.sv\n%Error: Exiting due to 1 error(s)\n"
module LedPanel_Avalon (

	input 	wire				clock200,
	input		wire				reset,


	input		wire				s0_address,
	input		wire				s0_write,
	input		wire	[31:0]	s0_writedata,
	input		wire				s0_read,
	output	reg	[31:0]	s0_readdata,
	
	output	wire				irq,
	


	input		wire 	[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES:0]	s1_address,
	input		wire				s1_write,
	input		wire	[31:0]	s1_writedata,

	

	output	wire	[1:0]		led_red,
	output	wire	[1:0]		led_green,
	output	wire	[1:0]		led_blue,
	output	wire	[3:0]		led_addr,
	output	wire 				led_clock,
	output	wire				led_blank,
	output	wire				led_latch,


	input 	wire				debug_clock
);


	parameter	DISPLAY_ROWS_LINES = 4;
	parameter	DISPLAY_COLS_LINES = 6;
	parameter	COLOR_BITS			 = 8;

	







	reg							backbuffer;
	reg							flip_backbuffer;
	wire							v_sync;
	wire	[7:0]					reg_stat = {flip_backbuffer, 5'b00000, backbuffer, v_sync};
	

	reg	[7:0]					reg_irq;
	wire	irq_ena		= reg_irq[7];
	wire	irq_latch	= reg_irq[0];


	reg	[1:0]					v_sync_edge_detect;
	reg 							req_backbuffer_flip;
	
	assign irq = irq_ena && irq_latch;
	


	always @(posedge clock200)
		begin
			if (reset) begin
				backbuffer <= 1'b0;
				flip_backbuffer <= 1'b0;
				reg_irq  <= 8'h00;
				v_sync_edge_detect <= 2'b00;
			end else begin

				v_sync_edge_detect <= {v_sync_edge_detect[0], v_sync};

				if (s0_address) begin
					if (s0_read) begin
						s0_readdata <= {24'b0, reg_irq};
					end else if (s0_write) begin
						reg_irq[7] 	 <= s0_writedata[7];
						reg_irq[0] <= 1'b0;
					end
				end else begin

					if (s0_read) begin
						s0_readdata <= {24'b0, reg_stat};
					end else if (s0_write) begin
						flip_backbuffer <= s0_writedata[7];
					end
				end

				if (v_sync_edge_detect == 2'b01) begin
					reg_irq[0] <= 1'b1;
				end

				if (req_backbuffer_flip) begin
					backbuffer <= ~backbuffer;
					flip_backbuffer <= 0;
				end
			end
		end
	

		always @(posedge debug_clock)
			begin
				if (reset) begin
					req_backbuffer_flip <= 1'b0;
				end else begin
					if ((v_sync_edge_detect == 2'b01) && (flip_backbuffer) ) begin
							req_backbuffer_flip <= 1'b1;
					end else req_backbuffer_flip <= 1'b0;
				end
			end
	
		LedPanel #(
			.COLOR_BITS(COLOR_BITS),
			.DISPLAY_ROWS_LINES(DISPLAY_ROWS_LINES),
			.DISPLAY_COLS_LINES(DISPLAY_COLS_LINES)
		)		panel(
		.CLK(debug_clock),
		.RST(reset),
	
		.RED(led_red),
		.GREEN(led_green),
		.BLUE(led_blue),
		.ADDR(led_addr),
		.CLK_LED(led_clock),
		.BLANK(led_blank),
		.LATCH(led_latch),
		
		.memAddrIn(s1_address),
		.memDataIn(s1_writedata[23:0]),
		.memWrite(s1_write),
		.v_sync(v_sync),
		.backbuffer(backbuffer)
	);



endmodule
module LedPanel_Avalon (

	input 	wire				clock200,
	input		wire				reset,


	input		wire				s0_address,
	input		wire				s0_write,
	input		wire	[31:0]	s0_writedata,
	input		wire				s0_read,
	output	reg	[31:0]	s0_readdata,
	
	output	wire				irq,
	


	input		wire 	[DISPLAY_ROWS_LINES+DISPLAY_COLS_LINES:0]	s1_address,
	input		wire				s1_write,
	input		wire	[31:0]	s1_writedata,

	

	output	wire	[1:0]		led_red,
	output	wire	[1:0]		led_green,
	output	wire	[1:0]		led_blue,
	output	wire	[3:0]		led_addr,
	output	wire 				led_clock,
	output	wire				led_blank,
	output	wire				led_latch,


	input 	wire				debug_clock
);



	parameter	DISPLAY_ROWS_LINES = 4;
	parameter	DISPLAY_COLS_LINES = 6;
	parameter	COLOR_BITS			 = 8;

	







	reg							backbuffer;
	reg							flip_backbuffer;
	wire							v_sync;
	wire	[7:0]					reg_stat = {flip_backbuffer, 5'b00000, backbuffer, v_sync};
	

	reg	[7:0]					reg_irq;
	wire	irq_ena		= reg_irq[7];
	wire	irq_latch	= reg_irq[0];


	reg	[1:0]					v_sync_edge_detect;
	reg 							req_backbuffer_flip;
	
	assign irq = irq_ena && irq_latch;
	


	always @(posedge clock200)
		begin
			if (reset) begin
				backbuffer <= 1'b0;
				flip_backbuffer <= 1'b0;
				reg_irq  <= 8'h00;
				v_sync_edge_detect <= 2'b00;
			end else begin

				v_sync_edge_detect <= {v_sync_edge_detect[0], v_sync};

				if (s0_address) begin
					if (s0_read) begin
						s0_readdata <= {24'b0, reg_irq};
					end else if (s0_write) begin
						reg_irq[7] 	 <= s0_writedata[7];
						reg_irq[0] <= 1'b0;
					end
				end else begin

					if (s0_read) begin
						s0_readdata <= {24'b0, reg_stat};
					end else if (s0_write) begin
						flip_backbuffer <= s0_writedata[7];
					end
				end

				if (v_sync_edge_detect == 2'b01) begin
					reg_irq[0] <= 1'b1;
				end

				if (req_backbuffer_flip) begin
					backbuffer <= ~backbuffer;
					flip_backbuffer <= 0;
				end
			end
		end
	

		always @(posedge debug_clock)
			begin
				if (reset) begin
					req_backbuffer_flip <= 1'b0;
				end else begin
					if ((v_sync_edge_detect == 2'b01) && (flip_backbuffer) ) begin
							req_backbuffer_flip <= 1'b1;
					end else req_backbuffer_flip <= 1'b0;
				end
			end
	
		LedPanel #(
			.COLOR_BITS(COLOR_BITS),
			.DISPLAY_ROWS_LINES(DISPLAY_ROWS_LINES),
			.DISPLAY_COLS_LINES(DISPLAY_COLS_LINES)
		)		panel(
		.CLK(debug_clock),
		.RST(reset),
	
		.RED(led_red),
		.GREEN(led_green),
		.BLUE(led_blue),
		.ADDR(led_addr),
		.CLK_LED(led_clock),
		.BLANK(led_blank),
		.LATCH(led_latch),
		
		.memAddrIn(s1_address),
		.memDataIn(s1_writedata[23:0]),
		.memWrite(s1_write),
		.v_sync(v_sync),
		.backbuffer(backbuffer)
	);



endmodule