data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/extend.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/extend.v:2: Cannot find include file: definitions.vh\n`include "definitions.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh.v\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh.sv\n             definitions.vh\n             definitions.vh.v\n             definitions.vh.sv\n             obj_dir/definitions.vh\n             obj_dir/definitions.vh.v\n             obj_dir/definitions.vh.sv\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/extend.v:13: Define or directive not defined: \'`EXT_OP_LENGTH\'\n           input  wire[`EXT_OP_LENGTH  - 1:0] cu_ext_op,\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/extend.v:19: Define or directive not defined: \'`EXT_OP_SFT16\'\n       (cu_ext_op == `EXT_OP_SFT16) ? {imm16, 16\'b0} :             \n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/extend.v:19: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n       (cu_ext_op == `EXT_OP_SFT16) ? {imm16, 16\'b0} :             \n                                  ^\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/extend.v:20: Define or directive not defined: \'`EXT_OP_SIGNED\'\n       (cu_ext_op == `EXT_OP_SIGNED) ? {{16{imm16[15]}}, imm16} :  \n                     ^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module extend(
           input  wire[15:0]                  imm16,
           input  wire[`EXT_OP_LENGTH  - 1:0] cu_ext_op,

           output wire[31:0]                  extended_imm
       );

assign extended_imm =
       (cu_ext_op == `EXT_OP_SFT16) ? {imm16, 16'b0} :
       (cu_ext_op == `EXT_OP_SIGNED) ? {{16{imm16[15]}}, imm16} :
       {16'b0, imm16};
endmodule
module extend(
           input  wire[15:0]                  imm16,
           input  wire[`EXT_OP_LENGTH  - 1:0] cu_ext_op,

           output wire[31:0]                  extended_imm
       );


assign extended_imm =
       (cu_ext_op == `EXT_OP_SFT16) ? {imm16, 16'b0} :
       (cu_ext_op == `EXT_OP_SIGNED) ? {{16{imm16[15]}}, imm16} :
       {16'b0, imm16};
endmodule