data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Led.v
 line:55: before: "/"
1: b'%Warning-MULTITOP: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Led.v:40: Multiple top level modules\n                                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                        : ... Top module \'Led\'\nmodule Led(\n       ^~~\n                                                                                                        : ... Top module \'RGB\'\nmodule RGB (\n       ^~~\n%Error: Exiting due to 1 warning(s)\n'
module RGB (
    input [3:0] stat,
    input clk,
    output [5:0] led 
);
    reg [5:0] led_ = 6'b000000;
    always @(posedge clk) begin
        case (stat)
            4'h0: led_ = 6'b000001;
            4'h1: led_ = 6'b001010;
            4'h2: led_ = 6'b010010;
            default: led_ = 6'b111111;
        endcase
    end
    assign led = led_;
endmodule
module RGB (
    input [3:0] stat,
    input clk,
    output [5:0] led 
);

    reg [5:0] led_ = 6'b000000;
    always @(posedge clk) begin
        case (stat)
            4'h0: led_ = 6'b000001;
            4'h1: led_ = 6'b001010;
            4'h2: led_ = 6'b010010;
            default: led_ = 6'b111111;
        endcase
    end
    assign led = led_;
endmodule