data/full_repos/permissive/111258339/src/Datapath/EXT.v
1: b'%Error: data/full_repos/permissive/111258339/src/Datapath/EXT.v:1: Cannot find include file: src/Define/ctrl_encode_def.v\n`include "src/Define/ctrl_encode_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111258339/src/Datapath,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v\n             data/full_repos/permissive/111258339/src/Datapath,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.v\n             data/full_repos/permissive/111258339/src/Datapath,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.sv\n             src/Define/ctrl_encode_def.v\n             src/Define/ctrl_encode_def.v.v\n             src/Define/ctrl_encode_def.v.sv\n             obj_dir/src/Define/ctrl_encode_def.v\n             obj_dir/src/Define/ctrl_encode_def.v.v\n             obj_dir/src/Define/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/111258339/src/Datapath/EXT.v:14: Define or directive not defined: \'`EXTOP_ZERO\'\n            `EXTOP_ZERO: Immediate32 <= {{16\'b0}, Immediate16[15:0]};\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Datapath/EXT.v:14: syntax error, unexpected \':\', expecting endcase\n            `EXTOP_ZERO: Immediate32 <= {{16\'b0}, Immediate16[15:0]};\n                       ^\n%Error: data/full_repos/permissive/111258339/src/Datapath/EXT.v:15: Define or directive not defined: \'`EXTOP_SIGNED\'\n            `EXTOP_SIGNED: Immediate32 <= {{16{Immediate16[15]}}, Immediate16[15:0]};\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Datapath/EXT.v:16: Define or directive not defined: \'`EXTOP_INST\'\n            `EXTOP_INST: Immediate32 <= 32\'b0;\n            ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module EXT(
    input wire[15:0] Immediate16,
    input wire[1:0] EXTOp,
    output reg[31:0] Immediate32
);

    initial begin
        Immediate32 = 32'b00;
    end

    always @(Immediate16) begin
        case(EXTOp)
            `EXTOP_ZERO: Immediate32 <= {{16'b0}, Immediate16[15:0]};
            `EXTOP_SIGNED: Immediate32 <= {{16{Immediate16[15]}}, Immediate16[15:0]};
            `EXTOP_INST: Immediate32 <= 32'b0;
            default: Immediate32 <= {{16'b0}, Immediate16[15:0]};
        endcase
        $display("EXT in: %x, out: %x", Immediate16, Immediate32);
    end
endmodule
module EXT(
    input wire[15:0] Immediate16,
    input wire[1:0] EXTOp,
    output reg[31:0] Immediate32
);


    initial begin
        Immediate32 = 32'b00;
    end

    always @(Immediate16) begin
        case(EXTOp)
            `EXTOP_ZERO: Immediate32 <= {{16'b0}, Immediate16[15:0]};
            `EXTOP_SIGNED: Immediate32 <= {{16{Immediate16[15]}}, Immediate16[15:0]};
            `EXTOP_INST: Immediate32 <= 32'b0;
            default: Immediate32 <= {{16'b0}, Immediate16[15:0]};
        endcase
        $display("EXT in: %x, out: %x", Immediate16, Immediate32);
    end
endmodule