data/full_repos/permissive/123690745/ExcCarrierD.v
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data/verilator_xmls/b4f9018d-1358-435f-9605-934842458227.xml
module ExcCarrierD(
    input InterruptRequest,
	 input clk,
	 input reset,
	 input FlushE,
	 input Nullify,
    input ErrorRlD,
	 input MulFlushE,
    output reg ErrorRlE = 0,
    input [31:0] PCD,
    output reg [31:0] PCE = 0
    );
	 always @(posedge clk) begin
		if ((!FlushE &&(Nullify || InterruptRequest)) || reset) begin
			ErrorRlE <= 0;
			PCE <= 0;
		end
		else if (FlushE) begin
			ErrorRlE <= 0;
			PCE <= PCD;
		end
		else begin
			ErrorRlE <= ErrorRlD;
			PCE <= PCD;
		end 
 	end
endmodule
module ExcCarrierD(
    input InterruptRequest,
	 input clk,
	 input reset,
	 input FlushE,
	 input Nullify,
    input ErrorRlD,
	 input MulFlushE,
    output reg ErrorRlE = 0,
    input [31:0] PCD,
    output reg [31:0] PCE = 0
    );

	 always @(posedge clk) begin
		if ((!FlushE &&(Nullify || InterruptRequest)) || reset) begin
			ErrorRlE <= 0;
			PCE <= 0;
		end
		else if (FlushE) begin
			ErrorRlE <= 0;
			PCE <= PCD;
		end
		else begin
			ErrorRlE <= ErrorRlD;
			PCE <= PCD;
		end 
 	end
endmodule