data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:56: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:56: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:211: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:212: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:213: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_1, coutb, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:214: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(gnd, net_11, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:215: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, coutb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:216: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, net_23, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:217: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_23, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:218: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_7(gnd, net_23, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:219: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_8(net_23, sb, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:220: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_9(gnd, net_33, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:221: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_10(net_33, net_32, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:222: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_11(net_32, sb, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:223: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_12(gnd, cout, coutb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:224: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_13(gnd, s, sb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:225: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(sb, net_92, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:226: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(net_92, net_90, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:227: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_90, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:228: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(sb, net_94, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:229: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(net_94, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:230: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_6(net_94, vdd, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:231: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_7(net_94, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:232: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_8(cout, vdd, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:233: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_9(net_95, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:234: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_10(coutb, net_95, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:235: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_11(net_111, vdd, a);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:236: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_12(net_111, vdd, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:237: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_13(coutb, net_111, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:238: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_14(s, vdd, sb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:247: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, y, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:248: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:260: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_5, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:261: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_5, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:262: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:263: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:275: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_0, net_1, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:276: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_0, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:277: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, Y, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:278: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(net_11, Y, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:279: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_11, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:280: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_1, vdd, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:281: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_1, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:282: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(Y, vdd, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:283: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_28, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.sv:284: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(Y, net_28, A);\n          ^~~~~~\n%Error: Exiting due to 44 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module muddlib07__xnor_ds(A, B, Y);
  input A;
  input B;
  output Y;

  supply1 vdd;
  supply0 gnd;
  wire net_0, net_1, net_11, net_28;

  tranif1 nmos_0(net_0, net_1, A);
  tranif1 nmos_1(gnd, net_0, B);
  tranif1 nmos_4(net_11, Y, A);
  tranif1 nmos_5(net_11, Y, B);
  tranif1 nmos_6(gnd, net_11, net_1);
  tranif0 pmos_0(net_1, vdd, A);
  tranif0 pmos_1(net_1, vdd, B);
  tranif0 pmos_2(Y, vdd, net_1);
  tranif0 pmos_3(net_28, vdd, B);
  tranif0 pmos_4(Y, net_28, A);
endmodule
module muddlib07__xnor_ds(A, B, Y);

  input A;
  input B;
  output Y;

  supply1 vdd;
  supply0 gnd;
  wire net_0, net_1, net_11, net_28;

  tranif1 nmos_0(net_0, net_1, A);
  tranif1 nmos_1(gnd, net_0, B);
  tranif1 nmos_4(net_11, Y, A);
  tranif1 nmos_5(net_11, Y, B);
  tranif1 nmos_6(gnd, net_11, net_1);
  tranif0 pmos_0(net_1, vdd, A);
  tranif0 pmos_1(net_1, vdd, B);
  tranif0 pmos_2(Y, vdd, net_1);
  tranif0 pmos_3(net_28, vdd, B);
  tranif0 pmos_4(Y, net_28, A);
endmodule