data/full_repos/permissive/185824253/rtl/myCPU/mux_4.v
data/verilator_xmls/8cdd1b11-d5d6-4048-9fd5-1eba82bb2eff.xml
module mux_4 (data_0, data_1, data_2, data_3, condition, data_out);
	parameter WIDTH = 32;

	input  [WIDTH-1:0] data_0;
	input  [WIDTH-1:0] data_1;
	input  [WIDTH-1:0] data_2;
	input  [WIDTH-1:0] data_3;
	input  [1:0] condition;
	output [WIDTH-1:0] data_out;

	assign data_out = ({WIDTH{condition==2'd0}} & data_0)
					| ({WIDTH{condition==2'd1}} & data_1)
					| ({WIDTH{condition==2'd2}} & data_2)
					| ({WIDTH{condition==2'd3}} & data_3);
endmodule
module mux_4 (data_0, data_1, data_2, data_3, condition, data_out);

	parameter WIDTH = 32;

	input  [WIDTH-1:0] data_0;
	input  [WIDTH-1:0] data_1;
	input  [WIDTH-1:0] data_2;
	input  [WIDTH-1:0] data_3;
	input  [1:0] condition;
	output [WIDTH-1:0] data_out;

	assign data_out = ({WIDTH{condition==2'd0}} & data_0)
					| ({WIDTH{condition==2'd1}} & data_1)
					| ({WIDTH{condition==2'd2}} & data_2)
					| ({WIDTH{condition==2'd3}} & data_3);
endmodule