data/full_repos/permissive/143278/ivltests/pr2790236.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2790236.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  wire out1, out2;

  test dut(out1, out2);

  initial begin
    #1;
    if (out1 !== 1'b0 || out2 !== 1'b1) begin
      $display("Failed: expected 0:1, got %b:%b", out1, out2);
    end else $display("PASSED");
  end
endmodule
module top;

  wire out1, out2;

  test dut(out1, out2);

  initial begin
    #1;
    if (out1 !== 1'b0 || out2 !== 1'b1) begin
      $display("Failed: expected 0:1, got %b:%b", out1, out2);
    end else $display("PASSED");
  end
endmodule