data/full_repos/permissive/189013641/src/clkdiv.v
None: at end of input
data/verilator_xmls/f5a4ab15-8370-4719-a3d2-1122f8ee7d88.xml
module clkdiv(rst,clk, clkout); 
input rst;
input clk;
output clkout;
reg clkout; 
reg [7:0] cnt; 

always @(posedge clk)
begin 

if(rst) begin
cnt<=0;
clkout<=0;
end
else if(cnt==8'd12) 
begin clkout <= 1'b1; 
cnt<=cnt+8'd1; 
end 
else if(cnt==8'd26) 
begin 
clkout<=1'b0; 
cnt<=8'd0; 
end 
else 
begin 
cnt<=cnt+8'd1; 
end 
end 
endmodule
module clkdiv(rst,clk, clkout);
 
input rst;
input clk;
output clkout;
reg clkout; 
reg [7:0] cnt; 

always @(posedge clk)
begin 

if(rst) begin
cnt<=0;
clkout<=0;
end
else if(cnt==8'd12) 
begin clkout <= 1'b1; 
cnt<=cnt+8'd1; 
end 
else if(cnt==8'd26) 
begin 
clkout<=1'b0; 
cnt<=8'd0; 
end 
else 
begin 
cnt<=cnt+8'd1; 
end 
end 
endmodule