data/full_repos/permissive/143278/ivltests/ptest007.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ptest007.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ptest007.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ptest007.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/ptest007.v:24: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                                        : ... In instance main\n  assign c = a && b;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/ptest007.v:24: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n                                                                        : ... In instance main\n  assign c = a && b;\n               ^~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
  reg [3:0] a,b;
  wire c;

  assign c = a && b;

  initial begin
    a = 4'd3;
    b = 4'd6;
    #1;
    if (c!==1) begin
      $display("FAILED");
      $finish;
    end
    a = 4'd0;
    #1;
    if (c!==0) begin
      $display("FAILED");
      $finish;
    end
    b = 4'd0;
    #1;
    if (c!==0) begin
      $display("FAILED");
      $finish;
    end
    $display("PASSED");
  end
endmodule
module main;

  reg [3:0] a,b;
  wire c;

  assign c = a && b;

  initial begin
    a = 4'd3;
    b = 4'd6;
    #1;
    if (c!==1) begin
      $display("FAILED");
      $finish;
    end
    a = 4'd0;
    #1;
    if (c!==0) begin
      $display("FAILED");
      $finish;
    end
    b = 4'd0;
    #1;
    if (c!==0) begin
      $display("FAILED");
      $finish;
    end
    $display("PASSED");
  end
endmodule