data/full_repos/permissive/210844779/lab2/2.8.1/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.1/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.1/tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.1/tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.1/tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.1/tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.1/tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.1/tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.1/tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.1/tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Error: data/full_repos/permissive/210844779/lab2/2.8.1/tb.v:5: Cannot find file containing module: \'dlatch\'\ndlatch u0(.d(d),.En(En),.rst(rst),.q(q));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab2/2.8.1,data/full_repos/permissive/210844779/dlatch\n             data/full_repos/permissive/210844779/lab2/2.8.1,data/full_repos/permissive/210844779/dlatch.v\n             data/full_repos/permissive/210844779/lab2/2.8.1,data/full_repos/permissive/210844779/dlatch.sv\n             dlatch\n             dlatch.v\n             dlatch.sv\n             obj_dir/dlatch\n             obj_dir/dlatch.v\n             obj_dir/dlatch.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  reg d,En,rst;
  wire q;
  
dlatch u0(.d(d),.En(En),.rst(rst),.q(q));
  
always
begin

d= 1'b1;
En= 1'b0;
rst= 1'b1;
#10

d= 1'b1;
En= 1'b1;
rst= 1'b1;
#10

d= 1'b1;
En= 1'b1;
rst= 1'b0;
#10

d= 1'b1;
En= 1'b0;
rst= 1'b1;
#10

d= 1'b1;
En= 1'b1;
rst= 1'b1;
#10

d= 1'b1;
En= 1'b1;
rst= 1'b0;
#10

d= 1'b0;
En= 1'b1;
rst= 1'b0;
#10

d= 1'b0;
En= 1'b1;
rst= 1'b1;
#10

d= 1'b1;
En= 1'b1;
rst= 1'b0;
#10;
end

endmodule
module tb();

  reg d,En,rst;
  wire q;
  
dlatch u0(.d(d),.En(En),.rst(rst),.q(q));
  
always
begin

d= 1'b1;
En= 1'b0;
rst= 1'b1;
#10

d= 1'b1;
En= 1'b1;
rst= 1'b1;
#10

d= 1'b1;
En= 1'b1;
rst= 1'b0;
#10

d= 1'b1;
En= 1'b0;
rst= 1'b1;
#10

d= 1'b1;
En= 1'b1;
rst= 1'b1;
#10

d= 1'b1;
En= 1'b1;
rst= 1'b0;
#10

d= 1'b0;
En= 1'b1;
rst= 1'b0;
#10

d= 1'b0;
En= 1'b1;
rst= 1'b1;
#10

d= 1'b1;
En= 1'b1;
rst= 1'b0;
#10;
end

endmodule