data/full_repos/permissive/19384863/sixbitpow_tb.v
1: b'%Error: data/full_repos/permissive/19384863/sixbitpow_tb.v:2: Cannot find include file: sixbitpow.v\n`include "sixbitpow.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19384863,data/full_repos/permissive/19384863/sixbitpow.v\n             data/full_repos/permissive/19384863,data/full_repos/permissive/19384863/sixbitpow.v.v\n             data/full_repos/permissive/19384863,data/full_repos/permissive/19384863/sixbitpow.v.sv\n             sixbitpow.v\n             sixbitpow.v.v\n             sixbitpow.v.sv\n             obj_dir/sixbitpow.v\n             obj_dir/sixbitpow.v.v\n             obj_dir/sixbitpow.v.sv\n%Error: data/full_repos/permissive/19384863/sixbitpow_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("sixbitpow_wave.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/19384863/sixbitpow_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, testbench);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19384863/sixbitpow_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n                #250;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module testbench;
    reg[5:0] ain;
    reg[5:0] bin;
    wire[5:0] pow;
    wire overflow;

    integer i, j;

    sixbitpow pow1 (ain, bin, pow, overflow);

    initial begin

        $dumpfile("sixbitpow_wave.vcd");
        $dumpvars(0, testbench);
    
        for(i = 0; i < 64; i = i + 1)
        begin
            ain = i;
            for(j = 0; j < 64; j = j + 1)
            begin
                bin = j;
                #250;
            end
        end
    end
endmodule
module testbench;

    reg[5:0] ain;
    reg[5:0] bin;
    wire[5:0] pow;
    wire overflow;

    integer i, j;

    sixbitpow pow1 (ain, bin, pow, overflow);

    initial begin

        $dumpfile("sixbitpow_wave.vcd");
        $dumpvars(0, testbench);
    
        for(i = 0; i < 64; i = i + 1)
        begin
            ain = i;
            for(j = 0; j < 64; j = j + 1)
            begin
                bin = j;
                #250;
            end
        end
    end
endmodule