data/full_repos/permissive/18477150/lib/sonic/xcvr_xg/sonic_v1_15/synthesis/submodules/sonic_v1_15_pcs_eth_10g_mac_tx_st_pause_ctrl_error_adapter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/18477150/lib/sonic/xcvr_xg/sonic_v1_15/synthesis/submodules/sonic_v1_15_pcs_eth_10g_mac_tx_st_pause_ctrl_error_adapter.v:51: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'in_error\' generates 1 bits.\n                                                                                                                                                                      : ... In instance sonic_v1_15_pcs_eth_10g_mac_tx_st_pause_ctrl_error_adapter\n      out_error = in_error;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sonic_v1_15_pcs_eth_10g_mac_tx_st_pause_ctrl_error_adapter (
    

      input              clk,

      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [63: 0] in_data,
      input      [ 0: 0] in_error,
      input              in_startofpacket,
      input              in_endofpacket,
      input      [ 2: 0] in_empty,

      input              out_ready,
      output reg         out_valid,
      output reg [63: 0] out_data,
      output reg [ 1: 0] out_error,
      output reg         out_startofpacket,
      output reg         out_endofpacket,
      output reg [ 2: 0] out_empty
);






   always @* begin
      in_ready = out_ready;
      out_valid = in_valid;
      out_data = in_data;
      out_startofpacket = in_startofpacket;
      out_endofpacket = in_endofpacket;
      out_empty = in_empty;

   end




   always @* begin
      out_error = 0;
      
      out_error = in_error;
   end
endmodule
module sonic_v1_15_pcs_eth_10g_mac_tx_st_pause_ctrl_error_adapter (
    

      input              clk,

      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [63: 0] in_data,
      input      [ 0: 0] in_error,
      input              in_startofpacket,
      input              in_endofpacket,
      input      [ 2: 0] in_empty,

      input              out_ready,
      output reg         out_valid,
      output reg [63: 0] out_data,
      output reg [ 1: 0] out_error,
      output reg         out_startofpacket,
      output reg         out_endofpacket,
      output reg [ 2: 0] out_empty
);







   always @* begin
      in_ready = out_ready;
      out_valid = in_valid;
      out_data = in_data;
      out_startofpacket = in_startofpacket;
      out_endofpacket = in_endofpacket;
      out_empty = in_empty;

   end




   always @* begin
      out_error = 0;
      
      out_error = in_error;
   end
endmodule