data/full_repos/permissive/121041165/vm1801mini/mini.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/121041165/vm1801mini/mini.v:205: Signal definition not found, creating implicitly: \'wb_we\'\n                                                                             : ... Suggested alternative: \'wb_sel\'\nassign wb_ack_mem = wb_cyc & wb_stb & (ack[1] | wb_we);\n                                                ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/121041165/vm1801mini/mini.v:263: Signal definition not found, creating implicitly: \'dclo\'\nassign dclo = dclo_out;\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/121041165/vm1801mini/mini.v:264: Signal definition not found, creating implicitly: \'aclo\'\n                                                                             : ... Suggested alternative: \'dclo\'\nassign aclo = aclo_out; \n       ^~~~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:47: Cannot find file containing module: \'SYNC\'\nSYNC gen(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/121041165/vm1801mini,data/full_repos/permissive/121041165/SYNC\n             data/full_repos/permissive/121041165/vm1801mini,data/full_repos/permissive/121041165/SYNC.v\n             data/full_repos/permissive/121041165/vm1801mini,data/full_repos/permissive/121041165/SYNC.sv\n             SYNC\n             SYNC.v\n             SYNC.sv\n             obj_dir/SYNC\n             obj_dir/SYNC.v\n             obj_dir/SYNC.sv\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:62: Cannot find file containing module: \'vm1_wb\'\nvm1_wb cpu(\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/121041165/vm1801mini/mini.v:104: Operator EQ expects 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                          : ... In instance mini\nwire A_FFCx = wb_adr[15:4] == (16\'o177700 >> 4);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/121041165/vm1801mini/mini.v:105: Operator EQ expects 16 bits on the LHS, but LHS\'s SEL generates 13 bits.\n                                                                          : ... In instance mini\nwire A_FF7x = wb_adr[15:3] == (16\'o177560 >> 3);\n                           ^~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:182: Cannot find file containing module: \'serial_tx\'\nserial_tx TX(.reset(!RST[1]), .clk(mclkp), .sbyte(wb_out[7:0]), .send(mx_stb[2] & wb_we), .tx(uart_tx), .busy(TX_busy));\n^~~~~~~~~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:186: Cannot find file containing module: \'serial_rx\'\nserial_rx RX(.reset(!RST[1]), .clk(mclkp), .rx(uart_rx), .rxread(wb_ack_FF7x), .rxbyte(RX_data), .ready(RX_ready));\n^~~~~~~~~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:218: Cannot find file containing module: \'video\'\nvideo vga(\n^~~~~\n%Warning-WIDTH: data/full_repos/permissive/121041165/vm1801mini/mini.v:227: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s REPLICATE generates 7 bits.\n                                                                          : ... In instance mini\nwire [7:0]WRV = {6\'d0, (mx_stb[3] & wb_we)} << wb_adr[13:11];\n                                            ^~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:228: Cannot find file containing module: \'VIDEORAM\'\nVIDEORAM VRAM0( \n^~~~~~~~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:232: Cannot find file containing module: \'VIDEORAM\'\nVIDEORAM VRAM1( \n^~~~~~~~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:236: Cannot find file containing module: \'VIDEORAM\'\nVIDEORAM VRAM2( \n^~~~~~~~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:240: Cannot find file containing module: \'VIDEORAM\'\nVIDEORAM VRAM3( \n^~~~~~~~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:244: Cannot find file containing module: \'VIDEORAM\'\nVIDEORAM VRAM4( \n^~~~~~~~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:248: Cannot find file containing module: \'VIDEORAM\'\nVIDEORAM VRAM5( \n^~~~~~~~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:252: Cannot find file containing module: \'VIDEORAM\'\nVIDEORAM VRAM6( \n^~~~~~~~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:256: Cannot find file containing module: \'VIDEORAM\'\nVIDEORAM VRAM7( \n^~~~~~~~\n%Error: data/full_repos/permissive/121041165/vm1801mini/mini.v:261: Cannot find file containing module: \'RAM\'\nRAM RAMALL(.di(wb_out),.addr(wb_adr),.Q(ram_data),.we(mx_stb[1] & wb_we),.sel(wb_sel),.clk(mclkp));\n^~~\n%Error: Exiting due to 14 error(s), 6 warning(s)\n'
module  mini(
  input clk,
  input reset,
  input uart_rx,
  output uart_tx, 

  output [4:0]Ro, 
  output [4:0]Bo,
  output [5:0]Go,
  output HS, VS

);
localparam DCLO_COUNTER_WIDTH = 4;
localparam ACLO_COUNTER_WIDTH = 3;

reg [DCLO_COUNTER_WIDTH-1:0] dclo_cnt;
reg [ACLO_COUNTER_WIDTH-1:0] aclo_cnt;

reg aclo_out, dclo_out;


wire vclk, mclkp, mclkn;
SYNC gen(
   .clk75(vclk),
	.clk50p(mclkp),
	.clk50n(mclkn),
	.CLK(clk)
);

wire [15:0]	mx_dat[3:0];
wire [15:0]	wb_adr;
wire [15:0] wb_out;
wire [15:0] wb_mux;
wire [1:0]  wb_sel;
wire [3:1]	vm_irq = 3'b000;
wire wb_cyc, wb_stb, wb_acki, wb_ack_cpu, wb_ack_mem, wb_ack_FF7x;

vm1_wb cpu(
 .vm_clk_p(mclkp),
 .vm_clk_n(mclkn),
 .vm_clk_slow(1'b0),
 .vm_clk_ena(1'b1),
 .vm_clk_tve(1'b1),
 .vm_clk_sp(1'b0),
 
 .vm_pa(2'b00),
 .vm_init_in(1'b0),
 .vm_dclo(dclo),
 .vm_aclo(aclo),
 
 .wbm_adr_o(wb_adr),
 .wbm_dat_o(wb_out),
 .wbm_dat_i(wb_mux),
 .wbm_cyc_o(wb_cyc),
 .wbm_we_o(wb_we),
 .wbm_sel_o(wb_sel),
 .wbm_stb_o(wb_stb),
 .wbm_ack_i(wb_ack_mem|wb_ack_cpu),
 
 .vm_irq(vm_irq),
 .vm_virq(1'b1),
 
 
 .wbs_adr_i(wb_adr[3:0]),
 .wbs_dat_i(wb_out),
 .wbs_cyc_i(wb_cyc),
 .wbs_we_i(wb_we),
 .wbs_stb_i(mx_stb[0]),
 .wbs_ack_o(wb_ack_cpu),
 .wbs_dat_o(mx_dat[0]),
 	
 .wbm_gnt_i(1'b1),

 .vm_reg14(16'o000000),
 .vm_reg16(16'o000000)
);


wire [3:0]	mx_stb;
wire A_FFCx = wb_adr[15:4] == (16'o177700 >> 4);
wire A_FF7x = wb_adr[15:3] == (16'o177560 >> 3);


wire A_VP = (wb_adr[15:11] == 5'b10_111) | ((wb_adr[15:14] == 2'b11) & !(&wb_adr[15:11]));
 
assign mx_stb[0]	= wb_stb & wb_cyc & A_FFCx;
assign mx_stb[2]	= wb_stb & wb_cyc & A_FF7x;

assign mx_stb[1]	= wb_stb & wb_cyc & (!(A_FFCx | A_FF7x | A_VP));
assign mx_stb[3]	= wb_stb & wb_cyc & A_VP;






wire TX_busy;
serial_tx TX(.reset(!RST[1]), .clk(mclkp), .sbyte(wb_out[7:0]), .send(mx_stb[2] & wb_we), .tx(uart_tx), .busy(TX_busy));

wire RX_ready;
wire [7:0]RX_data;
serial_rx RX(.reset(!RST[1]), .clk(mclkp), .rx(uart_rx), .rxread(wb_ack_FF7x), .rxbyte(RX_data), .ready(RX_ready));

wire [15:0]BUSV[7:0];
wire [15:0]vram_data = 
(wb_adr[15:11] == 24)? BUSV[0]   :
(wb_adr[15:11] == 25)? BUSV[1]   :
(wb_adr[15:11] == 26)? BUSV[2]   :
(wb_adr[15:11] == 27)? BUSV[3]   :
(wb_adr[15:11] == 28)? BUSV[4]   :
(wb_adr[15:11] == 29)? BUSV[5]   :
(wb_adr[15:11] == 30)? BUSV[6]   : BUSV[7];

wire [15:0]ram_data;

assign wb_mux		= (mx_stb[0] ? mx_dat[0] : 16'd0)
						| (mx_stb[1] ? ram_data  : 16'd0)
						| (mx_stb[3] ? vram_data  : 16'd0)
						| (mx_stb[2] ? {TX_busy, RX_ready, 6'd0, RX_data}  : 16'd0);

assign wb_ack_mem = wb_cyc & wb_stb & (ack[1] | wb_we);
assign wb_ack_FF7x = wb_cyc & wb_stb & ack[1] & A_FF7x;
reg [1:0]ack;
always@(posedge mclkp) 
begin
	ack[0] <= wb_cyc & wb_stb;
	ack[1] <= wb_cyc & ack[0];
end


wire [13:0] VADDR;
wire [7:0]  vdata[7:0];
wire [7:0]  video_data = vdata[VADDR[13:11]];
video vga(
        .RGB({Ro, Go, Bo}),
        .HSync(HS),
        .VSync(VS),
        .PIXADDR(VADDR),
        .PIXDATA(video_data),
        .PixClock(vclk)
);

wire [7:0]WRV = {6'd0, (mx_stb[3] & wb_we)} << wb_adr[13:11];
VIDEORAM VRAM0( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[0]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[7]), .q_b(BUSV[7])
);
VIDEORAM VRAM1( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[1]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[0]), .q_b(BUSV[0])
);
VIDEORAM VRAM2( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[2]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[1]), .q_b(BUSV[1])
);
VIDEORAM VRAM3( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[3]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[2]), .q_b(BUSV[2])
);
VIDEORAM VRAM4( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[4]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[3]), .q_b(BUSV[3])
);
VIDEORAM VRAM5( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[5]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[4]), .q_b(BUSV[4])
);
VIDEORAM VRAM6( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[6]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[5]), .q_b(BUSV[5])
);
VIDEORAM VRAM7( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[7]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[6]), .q_b(BUSV[6])
);

RAM RAMALL(.di(wb_out),.addr(wb_adr),.Q(ram_data),.we(mx_stb[1] & wb_we),.sel(wb_sel),.clk(mclkp));

assign dclo = dclo_out;
assign aclo = aclo_out; 
reg [1:0]RST;
always@(posedge mclkp)
begin



	RST[0] <= !reset;
	RST[1] <= RST[0];
	
	if (RST[1]) begin
		dclo_cnt  	<= 0;
		aclo_cnt  	<= 0;
		aclo_out		<= 1'b1;
		dclo_out		<= 1'b1;
	end
	else	begin



		if (dclo_cnt != `DE0_DCLO_WIDTH_CLK)
			dclo_cnt <= dclo_cnt + 1'b1;
		else
			dclo_out <= 1'b0;
			



		if (~dclo_out)
			if (aclo_cnt != `DE0_ACLO_DELAY_CLK)
				aclo_cnt <= aclo_cnt + 1'b1;
			else
				aclo_out <= 1'b0;
	end
end

endmodule
module  mini(
  input clk,
  input reset,
  input uart_rx,
  output uart_tx, 

  output [4:0]Ro, 
  output [4:0]Bo,
  output [5:0]Go,
  output HS, VS

);

localparam DCLO_COUNTER_WIDTH = 4;
localparam ACLO_COUNTER_WIDTH = 3;

reg [DCLO_COUNTER_WIDTH-1:0] dclo_cnt;
reg [ACLO_COUNTER_WIDTH-1:0] aclo_cnt;

reg aclo_out, dclo_out;


wire vclk, mclkp, mclkn;
SYNC gen(
   .clk75(vclk),
	.clk50p(mclkp),
	.clk50n(mclkn),
	.CLK(clk)
);

wire [15:0]	mx_dat[3:0];
wire [15:0]	wb_adr;
wire [15:0] wb_out;
wire [15:0] wb_mux;
wire [1:0]  wb_sel;
wire [3:1]	vm_irq = 3'b000;
wire wb_cyc, wb_stb, wb_acki, wb_ack_cpu, wb_ack_mem, wb_ack_FF7x;

vm1_wb cpu(
 .vm_clk_p(mclkp),
 .vm_clk_n(mclkn),
 .vm_clk_slow(1'b0),
 .vm_clk_ena(1'b1),
 .vm_clk_tve(1'b1),
 .vm_clk_sp(1'b0),
 
 .vm_pa(2'b00),
 .vm_init_in(1'b0),
 .vm_dclo(dclo),
 .vm_aclo(aclo),
 
 .wbm_adr_o(wb_adr),
 .wbm_dat_o(wb_out),
 .wbm_dat_i(wb_mux),
 .wbm_cyc_o(wb_cyc),
 .wbm_we_o(wb_we),
 .wbm_sel_o(wb_sel),
 .wbm_stb_o(wb_stb),
 .wbm_ack_i(wb_ack_mem|wb_ack_cpu),
 
 .vm_irq(vm_irq),
 .vm_virq(1'b1),
 
 
 .wbs_adr_i(wb_adr[3:0]),
 .wbs_dat_i(wb_out),
 .wbs_cyc_i(wb_cyc),
 .wbs_we_i(wb_we),
 .wbs_stb_i(mx_stb[0]),
 .wbs_ack_o(wb_ack_cpu),
 .wbs_dat_o(mx_dat[0]),
 	
 .wbm_gnt_i(1'b1),

 .vm_reg14(16'o000000),
 .vm_reg16(16'o000000)
);


wire [3:0]	mx_stb;
wire A_FFCx = wb_adr[15:4] == (16'o177700 >> 4);
wire A_FF7x = wb_adr[15:3] == (16'o177560 >> 3);


wire A_VP = (wb_adr[15:11] == 5'b10_111) | ((wb_adr[15:14] == 2'b11) & !(&wb_adr[15:11]));
 
assign mx_stb[0]	= wb_stb & wb_cyc & A_FFCx;
assign mx_stb[2]	= wb_stb & wb_cyc & A_FF7x;

assign mx_stb[1]	= wb_stb & wb_cyc & (!(A_FFCx | A_FF7x | A_VP));
assign mx_stb[3]	= wb_stb & wb_cyc & A_VP;






wire TX_busy;
serial_tx TX(.reset(!RST[1]), .clk(mclkp), .sbyte(wb_out[7:0]), .send(mx_stb[2] & wb_we), .tx(uart_tx), .busy(TX_busy));

wire RX_ready;
wire [7:0]RX_data;
serial_rx RX(.reset(!RST[1]), .clk(mclkp), .rx(uart_rx), .rxread(wb_ack_FF7x), .rxbyte(RX_data), .ready(RX_ready));

wire [15:0]BUSV[7:0];
wire [15:0]vram_data = 
(wb_adr[15:11] == 24)? BUSV[0]   :
(wb_adr[15:11] == 25)? BUSV[1]   :
(wb_adr[15:11] == 26)? BUSV[2]   :
(wb_adr[15:11] == 27)? BUSV[3]   :
(wb_adr[15:11] == 28)? BUSV[4]   :
(wb_adr[15:11] == 29)? BUSV[5]   :
(wb_adr[15:11] == 30)? BUSV[6]   : BUSV[7];

wire [15:0]ram_data;

assign wb_mux		= (mx_stb[0] ? mx_dat[0] : 16'd0)
						| (mx_stb[1] ? ram_data  : 16'd0)
						| (mx_stb[3] ? vram_data  : 16'd0)
						| (mx_stb[2] ? {TX_busy, RX_ready, 6'd0, RX_data}  : 16'd0);

assign wb_ack_mem = wb_cyc & wb_stb & (ack[1] | wb_we);
assign wb_ack_FF7x = wb_cyc & wb_stb & ack[1] & A_FF7x;
reg [1:0]ack;
always@(posedge mclkp) 
begin
	ack[0] <= wb_cyc & wb_stb;
	ack[1] <= wb_cyc & ack[0];
end


wire [13:0] VADDR;
wire [7:0]  vdata[7:0];
wire [7:0]  video_data = vdata[VADDR[13:11]];
video vga(
        .RGB({Ro, Go, Bo}),
        .HSync(HS),
        .VSync(VS),
        .PIXADDR(VADDR),
        .PIXDATA(video_data),
        .PixClock(vclk)
);

wire [7:0]WRV = {6'd0, (mx_stb[3] & wb_we)} << wb_adr[13:11];
VIDEORAM VRAM0( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[0]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[7]), .q_b(BUSV[7])
);
VIDEORAM VRAM1( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[1]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[0]), .q_b(BUSV[0])
);
VIDEORAM VRAM2( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[2]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[1]), .q_b(BUSV[1])
);
VIDEORAM VRAM3( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[3]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[2]), .q_b(BUSV[2])
);
VIDEORAM VRAM4( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[4]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[3]), .q_b(BUSV[3])
);
VIDEORAM VRAM5( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[5]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[4]), .q_b(BUSV[4])
);
VIDEORAM VRAM6( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[6]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[5]), .q_b(BUSV[5])
);
VIDEORAM VRAM7( 
 .clka(vclk), .data_a(8'd0), .addr_a(VADDR[10:0]), .we_a(1'b0), .q_a(vdata[7]),
 .clkb(mclkp), .data_b(wb_out), .addr_b(wb_adr[10:1]), .sel(wb_sel), .we_b(WRV[6]), .q_b(BUSV[6])
);

RAM RAMALL(.di(wb_out),.addr(wb_adr),.Q(ram_data),.we(mx_stb[1] & wb_we),.sel(wb_sel),.clk(mclkp));

assign dclo = dclo_out;
assign aclo = aclo_out; 
reg [1:0]RST;
always@(posedge mclkp)
begin



	RST[0] <= !reset;
	RST[1] <= RST[0];
	
	if (RST[1]) begin
		dclo_cnt  	<= 0;
		aclo_cnt  	<= 0;
		aclo_out		<= 1'b1;
		dclo_out		<= 1'b1;
	end
	else	begin



		if (dclo_cnt != `DE0_DCLO_WIDTH_CLK)
			dclo_cnt <= dclo_cnt + 1'b1;
		else
			dclo_out <= 1'b0;
			



		if (~dclo_out)
			if (aclo_cnt != `DE0_ACLO_DELAY_CLK)
				aclo_cnt <= aclo_cnt + 1'b1;
			else
				aclo_out <= 1'b0;
	end
end

endmodule