data/full_repos/permissive/216210370/soc/rtc.v
1: b"%Error: data/full_repos/permissive/216210370/soc/rtc.v:892: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.v\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:510: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:469: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:409: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:197: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module rtc_cdr_sync(
  aou_pdu_cnt,
  cnt_sync,
  pclk,
  presetn,
  test_mode
);
input   [31:0]  aou_pdu_cnt; 
input           pclk;       
input           presetn;    
input           test_mode;  
output  [31:0]  cnt_sync;   
reg             cnt_reg1;   
reg             cnt_reg2;   
reg             cnt_reg3;   
reg     [31:0]  cnt_sync;   
wire    [31:0]  aou_pdu_cnt; 
wire            cnt_ed;     
wire            pclk;       
wire            pclk_sync;  
wire            presetn;    
wire            test_mode;  
 always @(posedge pclk or negedge presetn)
 begin
   if(~presetn)
     begin
       cnt_reg1 <= 1'b0;
       cnt_reg2 <= 1'b0;
       cnt_reg3 <= 1'b0;
     end
   else
     begin
       cnt_reg1 <= aou_pdu_cnt[0];
       cnt_reg2 <= cnt_reg1;
       cnt_reg3 <= cnt_reg2;
     end
 end
assign cnt_ed = cnt_reg2 ^ cnt_reg3;
gated_clk_cell  gatecell (
  .clk_in               (pclk                ),
  .clk_out              (pclk_sync           ),
  .external_en          (cnt_ed              ),
  .global_en            (1'b0                ),
  .local_en             (1'b0                ),
  .module_en            (1'b0                ),
  .pad_yy_gate_clk_en_b (1'b0                ),
  .pad_yy_test_mode     (test_mode           )
);
 always @(posedge pclk_sync or negedge presetn)
 begin
   if(~presetn)
     begin
       cnt_sync[31:0] <= 32'b0;
     end
   else 
     begin
       cnt_sync[31:0] <= aou_pdu_cnt[31:0];
     end
 end
endmodule
module rtc_cdr_sync(
  aou_pdu_cnt,
  cnt_sync,
  pclk,
  presetn,
  test_mode
);

input   [31:0]  aou_pdu_cnt; 
input           pclk;       
input           presetn;    
input           test_mode;  
output  [31:0]  cnt_sync;   
reg             cnt_reg1;   
reg             cnt_reg2;   
reg             cnt_reg3;   
reg     [31:0]  cnt_sync;   
wire    [31:0]  aou_pdu_cnt; 
wire            cnt_ed;     
wire            pclk;       
wire            pclk_sync;  
wire            presetn;    
wire            test_mode;  
 always @(posedge pclk or negedge presetn)
 begin
   if(~presetn)
     begin
       cnt_reg1 <= 1'b0;
       cnt_reg2 <= 1'b0;
       cnt_reg3 <= 1'b0;
     end
   else
     begin
       cnt_reg1 <= aou_pdu_cnt[0];
       cnt_reg2 <= cnt_reg1;
       cnt_reg3 <= cnt_reg2;
     end
 end
assign cnt_ed = cnt_reg2 ^ cnt_reg3;
gated_clk_cell  gatecell (
  .clk_in               (pclk                ),
  .clk_out              (pclk_sync           ),
  .external_en          (cnt_ed              ),
  .global_en            (1'b0                ),
  .local_en             (1'b0                ),
  .module_en            (1'b0                ),
  .pad_yy_gate_clk_en_b (1'b0                ),
  .pad_yy_test_mode     (test_mode           )
);
 always @(posedge pclk_sync or negedge presetn)
 begin
   if(~presetn)
     begin
       cnt_sync[31:0] <= 32'b0;
     end
   else 
     begin
       cnt_sync[31:0] <= aou_pdu_cnt[31:0];
     end
 end
endmodule