data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:579: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter                    FIFO_WIDTH = 64)   \n       ^~~~~~~~~~~~~~\n                                                                                         : ... Top module \'_MULTI_CHANNEL_FIFO\'\nmodule _MULTI_CHANNEL_FIFO #(parameter                    C_LOG      = 2,   \n       ^~~~~~~~~~~~~~~~~~~\n                                                                                         : ... Top module \'vMERGE_SORTER_TREE\'\nmodule vMERGE_SORTER_TREE #(parameter                       W_LOG     = 2,\n       ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113471686/virtualtree/src/virtualtree.v:248: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n                                                                                      : ... In instance vMERGE_SORTER_TREE.sorter_stage_tree.stage[1].body.sorter_stage_body.ram_layer\n  wire [W_LOG-2:0]          enq_idx  = (ENQ_IDX >> 1);\n                                     ^\n%Error: Exiting due to 2 warning(s)\n'
module TREE_FILLER #(parameter                       W_LOG     = 2,
                     parameter                       P_LOG     = 3,
                     parameter                       Q_SIZE    = 2,
                     parameter                       DATW      = 64)
                    (input  wire                     CLK,
                     input  wire                     RST,
                     input  wire [W_LOG-1:0]         I_REQUEST,
                     input  wire                     I_REQUEST_VALID,
                     input  wire [(DATW<<P_LOG)-1:0] DIN,
                     input  wire                     DINEN,
                     input  wire [W_LOG-1:0]         DIN_IDX,
                     output wire                     QUEUE_FULL,
                     output wire [DATW-1:0]          DOT,
                     output wire                     DOTEN,
                     output wire [W_LOG-1:0]         DOT_IDX,
                     output wire [(1<<W_LOG)-1:0]    emp);
  
  localparam NUM_RECORD = (1<<P_LOG);

  wire                  queue_enq;
  wire                  queue_deq;
  wire [W_LOG-1:0]      queue_din;
  wire [W_LOG-1:0]      queue_dot;
  wire                  queue_emp;
  wire                  queue_ful; 
  wire [Q_SIZE:0]       queue_cnt;

  reg  [W_LOG-1:0]      queue_dot_buf;

  wire                  bram_we;
  wire [W_LOG-1:0]      bram_raddr;
  wire [W_LOG-1:0]      bram_waddr;
  wire [DATW-1:0]       bram_din [NUM_RECORD-1:0];
  wire [DATW-1:0]       bram_dot [NUM_RECORD-1:0];

  reg  [P_LOG-1:0]      head_list [(1<<W_LOG)-1:0];
  wire [(1<<W_LOG)-1:0] emp_list;
  
  reg                   data_ready;

  assign queue_enq  = I_REQUEST_VALID;
  assign queue_deq  = ~|{queue_emp, emp_list[queue_dot]};
  assign queue_din  = I_REQUEST;

  assign bram_we    = DINEN;
  assign bram_raddr = queue_dot;
  assign bram_waddr = DIN_IDX;
  
  DFIFO #(Q_SIZE, W_LOG)
  request_queue(CLK, RST, queue_enq, queue_deq, queue_din, 
                queue_dot, queue_emp, queue_ful, queue_cnt);
  
  genvar i;
  generate
    for (i=0; i<NUM_RECORD; i=i+1) begin: entries
      assign bram_din[i] = DIN[DATW*(i+1)-1:DATW*i];
      BRAM #(W_LOG, DATW)
      bram(CLK, bram_we, bram_raddr, bram_waddr, bram_din[i], bram_dot[i]);
    end
    for (i=0; i<(1<<W_LOG); i=i+1) begin: logical_fifo
      reg [P_LOG:0] head;
      always @(posedge CLK) begin
        if (RST) begin
          head <= NUM_RECORD;
        end else begin
          case ({&{bram_we,(bram_waddr == i)}, &{queue_deq,(bram_raddr == i)}})
            2'b01: head <= head + 1;
            2'b10: head <= 0;
          endcase
        end
      end
      always @(posedge CLK) begin
        head_list[i] <= head[P_LOG-1:0];
      end
      assign emp_list[i] = head[P_LOG];
    end
  endgenerate
  
  always @(posedge CLK) queue_dot_buf <= queue_dot;
  always @(posedge CLK) data_ready    <= (RST) ? 0 : queue_deq;
    

  assign QUEUE_FULL = queue_ful;
  assign DOT        = bram_dot[head_list[queue_dot_buf]];
  assign DOTEN      = data_ready;
  assign DOT_IDX    = queue_dot_buf;
  assign emp        = emp_list;
  
endmodule
module TREE_FILLER #(parameter                       W_LOG     = 2,
                     parameter                       P_LOG     = 3,
                     parameter                       Q_SIZE    = 2,
                     parameter                       DATW      = 64)
                    (input  wire                     CLK,
                     input  wire                     RST,
                     input  wire [W_LOG-1:0]         I_REQUEST,
                     input  wire                     I_REQUEST_VALID,
                     input  wire [(DATW<<P_LOG)-1:0] DIN,
                     input  wire                     DINEN,
                     input  wire [W_LOG-1:0]         DIN_IDX,
                     output wire                     QUEUE_FULL,
                     output wire [DATW-1:0]          DOT,
                     output wire                     DOTEN,
                     output wire [W_LOG-1:0]         DOT_IDX,
                     output wire [(1<<W_LOG)-1:0]    emp);

  
  localparam NUM_RECORD = (1<<P_LOG);

  wire                  queue_enq;
  wire                  queue_deq;
  wire [W_LOG-1:0]      queue_din;
  wire [W_LOG-1:0]      queue_dot;
  wire                  queue_emp;
  wire                  queue_ful; 
  wire [Q_SIZE:0]       queue_cnt;

  reg  [W_LOG-1:0]      queue_dot_buf;

  wire                  bram_we;
  wire [W_LOG-1:0]      bram_raddr;
  wire [W_LOG-1:0]      bram_waddr;
  wire [DATW-1:0]       bram_din [NUM_RECORD-1:0];
  wire [DATW-1:0]       bram_dot [NUM_RECORD-1:0];

  reg  [P_LOG-1:0]      head_list [(1<<W_LOG)-1:0];
  wire [(1<<W_LOG)-1:0] emp_list;
  
  reg                   data_ready;

  assign queue_enq  = I_REQUEST_VALID;
  assign queue_deq  = ~|{queue_emp, emp_list[queue_dot]};
  assign queue_din  = I_REQUEST;

  assign bram_we    = DINEN;
  assign bram_raddr = queue_dot;
  assign bram_waddr = DIN_IDX;
  
  DFIFO #(Q_SIZE, W_LOG)
  request_queue(CLK, RST, queue_enq, queue_deq, queue_din, 
                queue_dot, queue_emp, queue_ful, queue_cnt);
  
  genvar i;
  generate
    for (i=0; i<NUM_RECORD; i=i+1) begin: entries
      assign bram_din[i] = DIN[DATW*(i+1)-1:DATW*i];
      BRAM #(W_LOG, DATW)
      bram(CLK, bram_we, bram_raddr, bram_waddr, bram_din[i], bram_dot[i]);
    end
    for (i=0; i<(1<<W_LOG); i=i+1) begin: logical_fifo
      reg [P_LOG:0] head;
      always @(posedge CLK) begin
        if (RST) begin
          head <= NUM_RECORD;
        end else begin
          case ({&{bram_we,(bram_waddr == i)}, &{queue_deq,(bram_raddr == i)}})
            2'b01: head <= head + 1;
            2'b10: head <= 0;
          endcase
        end
      end
      always @(posedge CLK) begin
        head_list[i] <= head[P_LOG-1:0];
      end
      assign emp_list[i] = head[P_LOG];
    end
  endgenerate
  
  always @(posedge CLK) queue_dot_buf <= queue_dot;
  always @(posedge CLK) data_ready    <= (RST) ? 0 : queue_deq;
    

  assign QUEUE_FULL = queue_ful;
  assign DOT        = bram_dot[head_list[queue_dot_buf]];
  assign DOTEN      = data_ready;
  assign DOT_IDX    = queue_dot_buf;
  assign emp        = emp_list;
  
endmodule