data/full_repos/permissive/109846502/clockDivider.v
Syntax Error
1: b'%Warning-IMPLICIT: data/full_repos/permissive/109846502/clockDivider.v:32: Signal definition not found, creating implicitly: \'comp\'\nassign comp = (cnt == (div - 1));\n       ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module clockDivider
	#(parameter div = 25000000)
	(
		input clk,
		input rst,
		output reg slow_clk
    );

localparam nbits = clog2b(div);
reg [nbits-1:0] cnt;

assign comp = (cnt == (div - 1));

always @(posedge clk, posedge rst) begin
	if(rst)
		cnt <= {nbits{1'b0}};
	else if(comp)
		cnt <= {nbits{1'b0}};
	else
		cnt <= cnt + 1;
end

always @(posedge clk, posedge rst) begin
	if(rst) slow_clk <= 1'b0;
	else if(comp)
		slow_clk <= 1'b1;
	else 
		slow_clk <= 1'b0;
end

function integer clog2b;
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
	val = val >> 1;
end
endfunction


endmodule
module clockDivider
	#(parameter div = 25000000)
	(
		input clk,
		input rst,
		output reg slow_clk
    );


localparam nbits = clog2b(div);
reg [nbits-1:0] cnt;

assign comp = (cnt == (div - 1));

always @(posedge clk, posedge rst) begin
	if(rst)
		cnt <= {nbits{1'b0}};
	else if(comp)
		cnt <= {nbits{1'b0}};
	else
		cnt <= cnt + 1;
end

always @(posedge clk, posedge rst) begin
	if(rst) slow_clk <= 1'b0;
	else if(comp)
		slow_clk <= 1'b1;
	else 
		slow_clk <= 1'b0;
end

function integer clog2b;
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
	val = val >> 1;
end
endfunction


endmodule