data/full_repos/permissive/143278/ivltests/pr338.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr338.v:24: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                     : ... In instance Bug\n     x = \'h4000 + \'hzz;  \n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Bug;
   reg [7:0] x;
   initial begin
     x = 'h4000 + 'hzz;
   end
endmodule
module Bug;

   reg [7:0] x;
   initial begin
     x = 'h4000 + 'hzz;
   end
endmodule