data/full_repos/permissive/202915498/src/prime_time/sample_lib1.v
 line:152: before: "ifier"
data/verilator_xmls/95a9672a-65bd-4f1a-b0a7-7eb9f7518bf8.xml
module dffrx1 ( CK, RB, D, Q );
   output Q;
   input  CK, D, RB;

   wire      dly_Q;
   reg       notifier;

   udp_dff dff(dly_Q, D, CK, RB, 1'b1, notifier);
   buf uq(Q, dly_Q);

   specify
      if (CK) ( RB => Q ) = ( 0.0, 0.0 );
      if (RB) ( CK => Q ) = ( 0.1, 0.1 );
      $width     (negedge RB, 0.0, 0, notifier);
      $width     (negedge CK &&& RB==1'b1, 0.0, 0, notifier);
      $width     (posedge CK &&& RB==1'b1, 0.0, 0, notifier);
      $setuphold (posedge CK &&& RB==1'b1, posedge D, 0.0, 0.0, notifier);
      $setuphold (posedge CK &&& RB==1'b1, negedge D, 0.0, 0.0, notifier);
      $recrem    (posedge RB, posedge CK &&& D==1'b1, 0.0, 0.0, notifier);
   endspecify
endmodule
module dffrx1 ( CK, RB, D, Q );

   output Q;
   input  CK, D, RB;

   wire      dly_Q;
   reg       notifier;

   udp_dff dff(dly_Q, D, CK, RB, 1'b1, notifier);
   buf uq(Q, dly_Q);

   specify
      if (CK) ( RB => Q ) = ( 0.0, 0.0 );
      if (RB) ( CK => Q ) = ( 0.1, 0.1 );
      $width     (negedge RB, 0.0, 0, notifier);
      $width     (negedge CK &&& RB==1'b1, 0.0, 0, notifier);
      $width     (posedge CK &&& RB==1'b1, 0.0, 0, notifier);
      $setuphold (posedge CK &&& RB==1'b1, posedge D, 0.0, 0.0, notifier);
      $setuphold (posedge CK &&& RB==1'b1, negedge D, 0.0, 0.0, notifier);
      $recrem    (posedge RB, posedge CK &&& D==1'b1, 0.0, 0.0, notifier);
   endspecify
endmodule