data/full_repos/permissive/154448000/src/controller.v
Syntax Error
1: b'%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:67: Operator VAR \'waiting_for_go\' expects 3 bits on the Initial value, but Initial value\'s CONST \'4\'h0\' generates 4 bits.\n                                                                        : ... In instance controller\n    waiting_for_go     = 4\'b000,\n    ^~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:68: Operator VAR \'reading_in\' expects 3 bits on the Initial value, but Initial value\'s CONST \'4\'h1\' generates 4 bits.\n                                                                        : ... In instance controller\n    reading_in         = 4\'b001,\n    ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:69: Operator VAR \'initalize_w_stage\' expects 3 bits on the Initial value, but Initial value\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance controller\n    initalize_w_stage  = 4\'b010,\n    ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:70: Operator VAR \'compute_hash\' expects 3 bits on the Initial value, but Initial value\'s CONST \'4\'h4\' generates 4 bits.\n                                                                        : ... In instance controller\n    compute_hash       = 4\'b100,\n    ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:71: Operator VAR \'wait_for_hash_done\' expects 3 bits on the Initial value, but Initial value\'s CONST \'4\'h5\' generates 4 bits.\n                                                                        : ... In instance controller\n    wait_for_hash_done = 4\'b101,\n    ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:72: Operator VAR \'sending_data_dom\' expects 3 bits on the Initial value, but Initial value\'s CONST \'4\'h6\' generates 4 bits.\n                                                                        : ... In instance controller\n    sending_data_dom   = 4\'b110,\n    ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:73: Operator VAR \'done_hashing\' expects 3 bits on the Initial value, but Initial value\'s CONST \'4\'h7\' generates 4 bits.\n                                                                        : ... In instance controller\n    done_hashing       = 4\'b111;\n    ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:79: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'waiting_for_go\' generates 3 bits.\n                                                                        : ... In instance controller\n        if (reset) current_state <= waiting_for_go;\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:98: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reading_in\' generates 3 bits.\n                                                                        : ... In instance controller\n                next_state = reading_in; \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:100: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'waiting_for_go\' generates 3 bits.\n                                                                         : ... In instance controller\n            else next_state = waiting_for_go;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:107: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'initalize_w_stage\' generates 3 bits.\n                                                                         : ... In instance controller\n                next_state = initalize_w_stage; \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:109: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reading_in\' generates 3 bits.\n                                                                         : ... In instance controller\n            next_state=reading_in;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:115: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'compute_hash\' generates 3 bits.\n                                                                         : ... In instance controller\n            next_state=compute_hash;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:122: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'sending_data_dom\' generates 3 bits.\n                                                                         : ... In instance controller\n                next_state=sending_data_dom;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:124: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'compute_hash\' generates 3 bits.\n                                                                         : ... In instance controller\n                next_state=compute_hash;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:131: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'done_hashing\' generates 3 bits.\n                                                                         : ... In instance controller\n                next_state=done_hashing;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:133: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'sending_data_dom\' generates 3 bits.\n                                                                         : ... In instance controller\n                next_state=sending_data_dom;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:139: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'waiting_for_go\' generates 3 bits.\n                                                                         : ... In instance controller\n            next_state=waiting_for_go;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:142: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'waiting_for_go\' generates 3 bits.\n                                                                         : ... In instance controller\n        default: next_state=waiting_for_go;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:91: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'waiting_for_go\' generates 3 bits.\n                                                                        : ... In instance controller\n        case (current_state)  \n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:91: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'reading_in\' generates 3 bits.\n                                                                        : ... In instance controller\n        case (current_state)  \n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:91: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'initalize_w_stage\' generates 3 bits.\n                                                                        : ... In instance controller\n        case (current_state)  \n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:91: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'compute_hash\' generates 3 bits.\n                                                                        : ... In instance controller\n        case (current_state)  \n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:91: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'sending_data_dom\' generates 3 bits.\n                                                                        : ... In instance controller\n        case (current_state)  \n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:91: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'done_hashing\' generates 3 bits.\n                                                                        : ... In instance controller\n        case (current_state)  \n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:150: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'xxx__dut__msg_length\' generates 7 bits.\n                                                                         : ... In instance controller\n        in_msg_length      <= xxx__dut__msg_length;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:158: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'counter\' generates 7 bits.\n                                                                         : ... In instance controller\n        dut__kmem__address <= counter;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:159: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'counter\' generates 7 bits.\n                                                                         : ... In instance controller\n        dut__msg__address  <= counter;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:160: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'counter\' generates 7 bits.\n                                                                         : ... In instance controller\n        dut__hmem__address <= counter;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:164: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'in_msg_length\' generates 6 bits.\n                                                                         : ... In instance controller\n    assign address_range= in_msg_length-1;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:181: Operator GT expects 64 bits on the LHS, but LHS\'s VARREF \'counter\' generates 7 bits.\n                                                                         : ... In instance controller\n        else if(counter > address_range) msg_read_done=1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/154448000/src/controller.v:218: Operator GT expects 7 bits on the RHS, but RHS\'s VARREF \'h_mem_range\' generates 3 bits.\n                                                                         : ... In instance controller\n        else if(counter > h_mem_range) h_read_done=1;\n                        ^\n%Error: Exiting due to 32 warning(s)\n'
module controller #(parameter OUTPUT_LENGTH       = 8,
                    parameter NUMBER_OF_Hs        = 8 ,
                    parameter NUMBER_OF_Ks        = 64,
                    parameter MAX_MESSAGE_LENGTH  = 55)
            (
            input  wire                                     xxx__dut__go         ,  
            input  wire  [ $clog2(MAX_MESSAGE_LENGTH):0]    xxx__dut__msg_length ,
            output reg                                     dut__xxx__finish     ,

            output reg  [ $clog2(MAX_MESSAGE_LENGTH)-1:0]   dut__msg__address    ,
            output reg                                      dut__msg__enable     ,
            output reg                                      dut__msg__write      ,
            output reg                                      trigger_msg_2        ,

            output  reg                                     initialize_w         , 
            output  reg                                     trigger_w            ,
            output reg  [ $clog2(NUMBER_OF_Ks)-1:0]         dut__kmem__address   ,
            output reg                                      dut__kmem__enable    ,
            output reg                                      dut__kmem__write     ,  
            output reg                                      trigger_dom_send     ,          

            output reg  [ $clog2(NUMBER_OF_Hs)-1:0]         dut__hmem__address   ,
            output reg                                      dut__hmem__enable    ,
            output reg                                      dut__hmem__write     ,
            output reg                                      trigger_h_2          ,

            input reg                                       completed_send       ,

            input  wire                                     hash_complete        ,
            input  wire                                     clk                  ,
            input  wire                                     reset  
            );




    reg [$clog2(MAX_MESSAGE_LENGTH)-1:0] in_msg_length;
    reg en, in_go, en_finish, send_dom_data;
    reg [6:0] counter;  

    reg msg_read_done, msg__mem__enable, msg__mem__write, trigger_msg_1; 
    wire [63:0] address_range;

    reg h_read_done, h__mem__enable, h__mem__write, trigger_h_1; 
    wire [2:0] h_mem_range;

    reg k__mem__enable, k__mem__write; 
    reg done_calc;
    wire [6:0] number_of_calc;

    reg done_write;

    parameter [2:0]
    waiting_for_go     = 4'b000,
    reading_in         = 4'b001,
    initalize_w_stage  = 4'b010,
    compute_hash       = 4'b100,
    wait_for_hash_done = 4'b101,
    sending_data_dom   = 4'b110,
    done_hashing       = 4'b111;

    reg [3:0]current_state, next_state;


    always@(posedge clk)
        if (reset) current_state <= waiting_for_go;
        else current_state <= next_state;
    

    always@(*)
    begin 
        en = 0; 
        en_finish = 0;
        trigger_w = 0; 
        initialize_w  = 0; 
        send_dom_data = 0;
        trigger_dom_send = 0;
        case (current_state)

        waiting_for_go:
        begin

            if (in_go) 
            begin 
                next_state = reading_in; 
            end
            else next_state = waiting_for_go;
        end

        reading_in: 
        begin
            en = 1;
            if(msg_read_done && h_read_done)  
                next_state = initalize_w_stage; 
            else 
            next_state=reading_in;
        end
        
        initalize_w_stage: 
        begin
            initialize_w = 1;
            next_state=compute_hash;
        end

        compute_hash: 
        begin
            trigger_w= 1;
            if(done_calc)
                next_state=sending_data_dom;
            else
                next_state=compute_hash;
        end

        sending_data_dom: 
        begin
            send_dom_data = 1;
            if(~completed_send)
                next_state=done_hashing;
            else
                next_state=sending_data_dom;
        end

        done_hashing: 
        begin
            en_finish = 1;
            next_state=waiting_for_go;
        end

        default: next_state=waiting_for_go;
        endcase
    end
 

    always@(posedge clk)
    begin
        in_go              <= xxx__dut__go;
        in_msg_length      <= xxx__dut__msg_length;
        dut__msg__enable   <= msg__mem__enable;
        dut__msg__write    <= msg__mem__write;
        dut__hmem__enable  <= h__mem__enable;
        dut__hmem__write   <= h__mem__write;
        dut__kmem__enable  <= k__mem__enable;
        dut__kmem__write   <= k__mem__write;
        dut__xxx__finish   <= en_finish;
        dut__kmem__address <= counter;
        dut__msg__address  <= counter;
        dut__hmem__address <= counter;
    end

    
    assign address_range= in_msg_length-1;
    assign h_mem_range= 3'd7;
    assign number_of_calc=7'd63;

    always @(posedge clk) 
        if(~en && ~trigger_w && ~send_dom_data)
            counter = 0;
        else 
            counter= counter+1;
        
    



    always @(posedge clk) 
    begin
        if (~en) msg_read_done = 0;
        else if(counter > address_range) msg_read_done=1;
    end

    
    always@(posedge clk)
        if (reset) 
        begin
            msg__mem__enable = 0;
            msg__mem__write  = 1;
        end
        else 
        begin
            if (~msg_read_done && en) 
            begin
                msg__mem__enable  = 1;
                msg__mem__write   = 0;
            end
            else 
            begin
                msg__mem__enable  = 0;
                msg__mem__write   = 1;
            end
        end


    always@(posedge clk)
    begin
      trigger_msg_1 <= msg__mem__enable; 
      trigger_msg_2 <= trigger_msg_1; 
    end




    always @(posedge clk) 
    begin
        if (~en) h_read_done = 0;
        else if(counter > h_mem_range) h_read_done=1;
    end

    always@(posedge clk)
    if (reset) 
    begin
        h__mem__enable = 0;
        h__mem__write  = 1;
    end
    else 
    begin
        if (~h_read_done && en) 
        begin
            h__mem__enable  = 1;
            h__mem__write   = 0;
        end
        else 
        begin
            h__mem__enable  = 0;
            h__mem__write   = 1;
        end
    end

    always@(posedge clk)
    begin
      trigger_h_1 <= h__mem__enable; 
      trigger_h_2 <= trigger_h_1; 
    end




    always @(posedge clk) 
    begin
        if (~trigger_w) done_calc = 0;
        else if(counter > number_of_calc) done_calc=1;
    end

    always@(posedge clk)
    if (reset) 
    begin
        k__mem__enable = 0;
        k__mem__write  = 1;
    end
    else 
    begin
        if (trigger_w) 
        begin
            k__mem__enable  = 1;
            k__mem__write   = 0;
        end
        else 
        begin
            k__mem__enable  = 0;
            k__mem__write   = 1;
        end
    end

    always@(send_dom_data)
    begin
      trigger_dom_send <= send_dom_data; 
    end

endmodule
module controller #(parameter OUTPUT_LENGTH       = 8,
                    parameter NUMBER_OF_Hs        = 8 ,
                    parameter NUMBER_OF_Ks        = 64,
                    parameter MAX_MESSAGE_LENGTH  = 55)
            (
            input  wire                                     xxx__dut__go         ,  
            input  wire  [ $clog2(MAX_MESSAGE_LENGTH):0]    xxx__dut__msg_length ,
            output reg                                     dut__xxx__finish     ,

            output reg  [ $clog2(MAX_MESSAGE_LENGTH)-1:0]   dut__msg__address    ,
            output reg                                      dut__msg__enable     ,
            output reg                                      dut__msg__write      ,
            output reg                                      trigger_msg_2        ,

            output  reg                                     initialize_w         , 
            output  reg                                     trigger_w            ,
            output reg  [ $clog2(NUMBER_OF_Ks)-1:0]         dut__kmem__address   ,
            output reg                                      dut__kmem__enable    ,
            output reg                                      dut__kmem__write     ,  
            output reg                                      trigger_dom_send     ,          

            output reg  [ $clog2(NUMBER_OF_Hs)-1:0]         dut__hmem__address   ,
            output reg                                      dut__hmem__enable    ,
            output reg                                      dut__hmem__write     ,
            output reg                                      trigger_h_2          ,

            input reg                                       completed_send       ,

            input  wire                                     hash_complete        ,
            input  wire                                     clk                  ,
            input  wire                                     reset  
            );





    reg [$clog2(MAX_MESSAGE_LENGTH)-1:0] in_msg_length;
    reg en, in_go, en_finish, send_dom_data;
    reg [6:0] counter;  

    reg msg_read_done, msg__mem__enable, msg__mem__write, trigger_msg_1; 
    wire [63:0] address_range;

    reg h_read_done, h__mem__enable, h__mem__write, trigger_h_1; 
    wire [2:0] h_mem_range;

    reg k__mem__enable, k__mem__write; 
    reg done_calc;
    wire [6:0] number_of_calc;

    reg done_write;

    parameter [2:0]
    waiting_for_go     = 4'b000,
    reading_in         = 4'b001,
    initalize_w_stage  = 4'b010,
    compute_hash       = 4'b100,
    wait_for_hash_done = 4'b101,
    sending_data_dom   = 4'b110,
    done_hashing       = 4'b111;

    reg [3:0]current_state, next_state;


    always@(posedge clk)
        if (reset) current_state <= waiting_for_go;
        else current_state <= next_state;
    

    always@(*)
    begin 
        en = 0; 
        en_finish = 0;
        trigger_w = 0; 
        initialize_w  = 0; 
        send_dom_data = 0;
        trigger_dom_send = 0;
        case (current_state)

        waiting_for_go:
        begin

            if (in_go) 
            begin 
                next_state = reading_in; 
            end
            else next_state = waiting_for_go;
        end

        reading_in: 
        begin
            en = 1;
            if(msg_read_done && h_read_done)  
                next_state = initalize_w_stage; 
            else 
            next_state=reading_in;
        end
        
        initalize_w_stage: 
        begin
            initialize_w = 1;
            next_state=compute_hash;
        end

        compute_hash: 
        begin
            trigger_w= 1;
            if(done_calc)
                next_state=sending_data_dom;
            else
                next_state=compute_hash;
        end

        sending_data_dom: 
        begin
            send_dom_data = 1;
            if(~completed_send)
                next_state=done_hashing;
            else
                next_state=sending_data_dom;
        end

        done_hashing: 
        begin
            en_finish = 1;
            next_state=waiting_for_go;
        end

        default: next_state=waiting_for_go;
        endcase
    end
 

    always@(posedge clk)
    begin
        in_go              <= xxx__dut__go;
        in_msg_length      <= xxx__dut__msg_length;
        dut__msg__enable   <= msg__mem__enable;
        dut__msg__write    <= msg__mem__write;
        dut__hmem__enable  <= h__mem__enable;
        dut__hmem__write   <= h__mem__write;
        dut__kmem__enable  <= k__mem__enable;
        dut__kmem__write   <= k__mem__write;
        dut__xxx__finish   <= en_finish;
        dut__kmem__address <= counter;
        dut__msg__address  <= counter;
        dut__hmem__address <= counter;
    end

    
    assign address_range= in_msg_length-1;
    assign h_mem_range= 3'd7;
    assign number_of_calc=7'd63;

    always @(posedge clk) 
        if(~en && ~trigger_w && ~send_dom_data)
            counter = 0;
        else 
            counter= counter+1;
        
    



    always @(posedge clk) 
    begin
        if (~en) msg_read_done = 0;
        else if(counter > address_range) msg_read_done=1;
    end

    
    always@(posedge clk)
        if (reset) 
        begin
            msg__mem__enable = 0;
            msg__mem__write  = 1;
        end
        else 
        begin
            if (~msg_read_done && en) 
            begin
                msg__mem__enable  = 1;
                msg__mem__write   = 0;
            end
            else 
            begin
                msg__mem__enable  = 0;
                msg__mem__write   = 1;
            end
        end


    always@(posedge clk)
    begin
      trigger_msg_1 <= msg__mem__enable; 
      trigger_msg_2 <= trigger_msg_1; 
    end




    always @(posedge clk) 
    begin
        if (~en) h_read_done = 0;
        else if(counter > h_mem_range) h_read_done=1;
    end

    always@(posedge clk)
    if (reset) 
    begin
        h__mem__enable = 0;
        h__mem__write  = 1;
    end
    else 
    begin
        if (~h_read_done && en) 
        begin
            h__mem__enable  = 1;
            h__mem__write   = 0;
        end
        else 
        begin
            h__mem__enable  = 0;
            h__mem__write   = 1;
        end
    end

    always@(posedge clk)
    begin
      trigger_h_1 <= h__mem__enable; 
      trigger_h_2 <= trigger_h_1; 
    end




    always @(posedge clk) 
    begin
        if (~trigger_w) done_calc = 0;
        else if(counter > number_of_calc) done_calc=1;
    end

    always@(posedge clk)
    if (reset) 
    begin
        k__mem__enable = 0;
        k__mem__write  = 1;
    end
    else 
    begin
        if (trigger_w) 
        begin
            k__mem__enable  = 1;
            k__mem__write   = 0;
        end
        else 
        begin
            k__mem__enable  = 0;
            k__mem__write   = 1;
        end
    end

    always@(send_dom_data)
    begin
      trigger_dom_send <= send_dom_data; 
    end

endmodule