data/full_repos/permissive/158845296/data_mem.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/a87a014d-6586-4fa7-9e3c-a1ac2c514862.xml
module data_mem
(
    input          clock,
    input          read,
    input          write,
    input   [31:0] write_address,
    input   [31:0] read_address,
    input  [127:0] write_data,
    output [127:0] read_data,
    output         write_done,
    output         read_valid
);

    reg         seq_write_done;
    reg         seq_read_valid;
    reg [127:0] seq_data;
    reg         previous_write;
    reg         should_write;
    reg         previous_read;
    reg         should_read;
    reg   [3:0] read_counter;
    reg   [3:0] write_counter;
    reg  [31:0] data_mem [255:0];
    wire        write_request;
    wire        read_request;
    wire  [7:0] block_aligned_write;
    wire  [7:0] block_aligned_read;


    integer i;
    initial begin
        read_counter  = 4'b0;
        write_counter = 4'b0;
        should_read   = 1'b0;
        should_write  = 1'b0;
        for (i = 0; i < 256; i = i + 1)
            data_mem[i] = 32'b0;
    end


    always @(posedge clock) begin
        previous_write = write;
        previous_read = read;
    end


    always @(posedge clock) begin
        if (read_request)
            should_read = 1'b1;
        if (write_request)
            should_write = 1'b1;
    end


    always @(posedge clock) begin

        if (should_read) begin

            read_counter = read_counter + 1;

            if (read_counter == 4'd10) begin
                read_counter     <= 4'b0;
                should_read      <= 1'b0;
                seq_data [31: 0] <= data_mem[block_aligned_read];
                seq_data [63:32] <= data_mem[block_aligned_read + 1];
                seq_data [95:64] <= data_mem[block_aligned_read + 2];
                seq_data[127:96] <= data_mem[block_aligned_read + 3];
                seq_read_valid   <= 1'b1;
            end
        end else
            seq_read_valid = 1'b0;
    end


    always @(posedge clock) begin

        if (should_write) begin

            write_counter = write_counter + 1;

            if (write_counter == 4'd10) begin
                write_counter                     <= 4'b0;
                should_write                      <= 1'b0;
                data_mem[block_aligned_write]     <= write_data [31: 0];
                data_mem[block_aligned_write + 1] <= write_data [63:32];
                data_mem[block_aligned_write + 2] <= write_data [95:64];
                data_mem[block_aligned_write + 3] <= write_data[127:96];
                seq_write_done                    <= 1'b1;
            end
        end else
            seq_write_done = 1'b0;
    end


    assign read_request        = (~previous_read & read) || (previous_read === 1'bx & read);
    assign write_request       = ~previous_write & write;
    assign block_aligned_read  = read_address[9:2] & 8'b11111100;
    assign block_aligned_write = write_address[9:2] & 8'b11111100;


    assign read_valid = seq_read_valid;
    assign read_data  = seq_data;
    assign write_done = seq_write_done;

endmodule
module data_mem
(
    input          clock,
    input          read,
    input          write,
    input   [31:0] write_address,
    input   [31:0] read_address,
    input  [127:0] write_data,
    output [127:0] read_data,
    output         write_done,
    output         read_valid
);


    reg         seq_write_done;
    reg         seq_read_valid;
    reg [127:0] seq_data;
    reg         previous_write;
    reg         should_write;
    reg         previous_read;
    reg         should_read;
    reg   [3:0] read_counter;
    reg   [3:0] write_counter;
    reg  [31:0] data_mem [255:0];
    wire        write_request;
    wire        read_request;
    wire  [7:0] block_aligned_write;
    wire  [7:0] block_aligned_read;


    integer i;
    initial begin
        read_counter  = 4'b0;
        write_counter = 4'b0;
        should_read   = 1'b0;
        should_write  = 1'b0;
        for (i = 0; i < 256; i = i + 1)
            data_mem[i] = 32'b0;
    end


    always @(posedge clock) begin
        previous_write = write;
        previous_read = read;
    end


    always @(posedge clock) begin
        if (read_request)
            should_read = 1'b1;
        if (write_request)
            should_write = 1'b1;
    end


    always @(posedge clock) begin

        if (should_read) begin

            read_counter = read_counter + 1;

            if (read_counter == 4'd10) begin
                read_counter     <= 4'b0;
                should_read      <= 1'b0;
                seq_data [31: 0] <= data_mem[block_aligned_read];
                seq_data [63:32] <= data_mem[block_aligned_read + 1];
                seq_data [95:64] <= data_mem[block_aligned_read + 2];
                seq_data[127:96] <= data_mem[block_aligned_read + 3];
                seq_read_valid   <= 1'b1;
            end
        end else
            seq_read_valid = 1'b0;
    end


    always @(posedge clock) begin

        if (should_write) begin

            write_counter = write_counter + 1;

            if (write_counter == 4'd10) begin
                write_counter                     <= 4'b0;
                should_write                      <= 1'b0;
                data_mem[block_aligned_write]     <= write_data [31: 0];
                data_mem[block_aligned_write + 1] <= write_data [63:32];
                data_mem[block_aligned_write + 2] <= write_data [95:64];
                data_mem[block_aligned_write + 3] <= write_data[127:96];
                seq_write_done                    <= 1'b1;
            end
        end else
            seq_write_done = 1'b0;
    end


    assign read_request        = (~previous_read & read) || (previous_read === 1'bx & read);
    assign write_request       = ~previous_write & write;
    assign block_aligned_read  = read_address[9:2] & 8'b11111100;
    assign block_aligned_write = write_address[9:2] & 8'b11111100;


    assign read_valid = seq_read_valid;
    assign read_data  = seq_data;
    assign write_done = seq_write_done;

endmodule