data/full_repos/permissive/114664169/instructionparser.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/114664169/instructionparser.v:67: Signal definition not found, creating implicitly: \'w_running\'\nassign w_running = r_run && !i_stop && !r_stop;\n       ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module instructionparser (
	input sys_clock,
	
	output [23:0] o_output_bus,
	

	output [9:0] o_ram_address,
	input [31:0] i_ram_data,
	

	input [15:0] i_spc_data,
		

	input [23:0] i_idle_state,
	input [31:0] i_shots,
	

	input i_trigger,
	input i_stop,
	output o_finished
);


reg r_run;
reg r_stop;

assign w_running = r_run && !i_stop && !r_stop;
assign o_finished = !w_running;


reg [23:0] r_output;
assign o_output_bus = r_output;


reg [9:0] r_address;
assign o_ram_address = r_address;



reg [29:0] r_wait_counter;
reg [31:0] r_shot_counter;

initial begin
	r_run <= 0;
	r_stop <= 0;
	r_trigger <= 0;
	r_address <= 1;
	r_wait_counter <= 0;
	r_shot_counter <= 0;
	r_output <= i_idle_state;
end


reg r_trigger;

always @ (negedge sys_clock or posedge i_trigger) begin
	if (i_trigger == 1) begin
		r_trigger <= 1;
	end else begin
		r_trigger <= 0;
	end
end


always @ (negedge sys_clock) begin



	if (w_running == 0) begin
		r_output <= i_idle_state;
		

		r_wait_counter <= 0;
		r_shot_counter <= 0;
		r_address <= 1;
		r_stop <= 0;
		

		r_run <= r_trigger;
	end
	


	if (r_wait_counter > 0) begin
		r_wait_counter <= r_wait_counter - 1;
	end
	
	

	
	if (r_wait_counter == 0 && w_running == 1) begin
	
		casez (i_ram_data[31:29])
		
		3'b00?:
		begin
			r_wait_counter <= i_ram_data[29:0];
			r_address <= r_address + 1;
		end
		
		3'b10?:
		begin
			r_output <= i_ram_data[23:0];
			r_address <= r_address + 1;
		end
		
		3'b010:
		begin
		
			if (i_spc_data >= i_ram_data[25:10]) begin
				r_address <= i_ram_data[9:0];
			end else begin
				r_address <= r_address + 1;
			end
			
	   end 
		
		3'b011:
		begin
			r_address <= i_ram_data[9:0];
		end
		
		default:
		begin
			r_address <= 1;
			if (r_shot_counter < i_shots) begin
				r_shot_counter <= r_shot_counter + 1;
			end else begin
				r_stop <= 1;
			end
		end
		
		endcase
	
	end

end

endmodule
module instructionparser (
	input sys_clock,
	
	output [23:0] o_output_bus,
	

	output [9:0] o_ram_address,
	input [31:0] i_ram_data,
	

	input [15:0] i_spc_data,
		

	input [23:0] i_idle_state,
	input [31:0] i_shots,
	

	input i_trigger,
	input i_stop,
	output o_finished
);



reg r_run;
reg r_stop;

assign w_running = r_run && !i_stop && !r_stop;
assign o_finished = !w_running;


reg [23:0] r_output;
assign o_output_bus = r_output;


reg [9:0] r_address;
assign o_ram_address = r_address;



reg [29:0] r_wait_counter;
reg [31:0] r_shot_counter;

initial begin
	r_run <= 0;
	r_stop <= 0;
	r_trigger <= 0;
	r_address <= 1;
	r_wait_counter <= 0;
	r_shot_counter <= 0;
	r_output <= i_idle_state;
end


reg r_trigger;

always @ (negedge sys_clock or posedge i_trigger) begin
	if (i_trigger == 1) begin
		r_trigger <= 1;
	end else begin
		r_trigger <= 0;
	end
end


always @ (negedge sys_clock) begin



	if (w_running == 0) begin
		r_output <= i_idle_state;
		

		r_wait_counter <= 0;
		r_shot_counter <= 0;
		r_address <= 1;
		r_stop <= 0;
		

		r_run <= r_trigger;
	end
	


	if (r_wait_counter > 0) begin
		r_wait_counter <= r_wait_counter - 1;
	end
	
	

	
	if (r_wait_counter == 0 && w_running == 1) begin
	
		casez (i_ram_data[31:29])
		
		3'b00?:
		begin
			r_wait_counter <= i_ram_data[29:0];
			r_address <= r_address + 1;
		end
		
		3'b10?:
		begin
			r_output <= i_ram_data[23:0];
			r_address <= r_address + 1;
		end
		
		3'b010:
		begin
		
			if (i_spc_data >= i_ram_data[25:10]) begin
				r_address <= i_ram_data[9:0];
			end else begin
				r_address <= r_address + 1;
			end
			
	   end 
		
		3'b011:
		begin
			r_address <= i_ram_data[9:0];
		end
		
		default:
		begin
			r_address <= 1;
			if (r_shot_counter < i_shots) begin
				r_shot_counter <= r_shot_counter + 1;
			end else begin
				r_stop <= 1;
			end
		end
		
		endcase
	
	end

end

endmodule