data/full_repos/permissive/206670486/Modulos/Clock.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:4: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:5: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:6: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:7: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:8: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206670486/Modulos/Clock.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLOCK = 0;\n  ^\n%Error: Exiting due to 60 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Clock(CLOCK);
    output reg CLOCK;
initial begin
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;

end


endmodule
module Clock(CLOCK);

    output reg CLOCK;
initial begin
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;
  #1	CLOCK = 1;
  #1	CLOCK = 0;

end


endmodule