data/full_repos/permissive/143278/ivltests/patch1268.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/patch1268.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #4;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/patch1268.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

reg [19:0] a[15:0];

reg [3:0] idx[3:1];

initial begin
  idx[1] = 2;
  idx[2] = 3;
  idx[3] = 4;
  a[idx[1]][idx[2]*4 +: 4] <= #(idx[3]) 4'ha;
  #4;
  $display("%h", a[2]);
  if (a[2] !== 20'hxxxxx) begin
    $display("FAILED");
    $finish;
  end
  #1;
  $display("%h", a[2]);
  if (a[2] !== 20'hxaxxx) begin
    $display("FAILED");
    $finish;
  end
  $display("PASSED");
end

endmodule
module test();


reg [19:0] a[15:0];

reg [3:0] idx[3:1];

initial begin
  idx[1] = 2;
  idx[2] = 3;
  idx[3] = 4;
  a[idx[1]][idx[2]*4 +: 4] <= #(idx[3]) 4'ha;
  #4;
  $display("%h", a[2]);
  if (a[2] !== 20'hxxxxx) begin
    $display("FAILED");
    $finish;
  end
  #1;
  $display("%h", a[2]);
  if (a[2] !== 20'hxaxxx) begin
    $display("FAILED");
    $finish;
  end
  $display("PASSED");
end

endmodule