data/full_repos/permissive/159823067/omercevik_hw3_32bitMipsRType_verilog_files/mips_registers.v
data/verilator_xmls/094451be-9e69-425e-a640-f19d35db34db.xml
module mips_registers
( read_data_1, read_data_2, write_data, read_reg_1, read_reg_2, write_reg, signal_reg_write, clk );

	output [31:0] read_data_1, read_data_2;
	input [31:0] write_data;
	input [4:0] read_reg_1, read_reg_2, write_reg;
	input signal_reg_write, clk;
	
	reg [31:0] registers [31:0];
	
	assign read_data_1 = registers[read_reg_1];
	assign read_data_2 = registers[read_reg_2];
	
	always @(posedge clk)
	begin
		if( signal_reg_write == 1'b1 )
		begin
			if( write_reg == 5'd0 )
			begin
				registers[write_reg] <= 32'd0;
			end
			else
			begin
				registers[write_reg] <= write_data;
			end
		end
	end
	
endmodule
module mips_registers
( read_data_1, read_data_2, write_data, read_reg_1, read_reg_2, write_reg, signal_reg_write, clk );


	output [31:0] read_data_1, read_data_2;
	input [31:0] write_data;
	input [4:0] read_reg_1, read_reg_2, write_reg;
	input signal_reg_write, clk;
	
	reg [31:0] registers [31:0];
	
	assign read_data_1 = registers[read_reg_1];
	assign read_data_2 = registers[read_reg_2];
	
	always @(posedge clk)
	begin
		if( signal_reg_write == 1'b1 )
		begin
			if( write_reg == 5'd0 )
			begin
				registers[write_reg] <= 32'd0;
			end
			else
			begin
				registers[write_reg] <= write_data;
			end
		end
	end
	
endmodule