data/full_repos/permissive/131069375/uv-risc/verilog/uvrisc.v
1: b"%Error: data/full_repos/permissive/131069375/uv-risc/verilog/uvrisc.v:27: Can't find definition of variable: 'pc_we'\n   assign halt = (pc_we) ? alu_out == pc : 0;\n                  ^~~~~\n%Error: data/full_repos/permissive/131069375/uv-risc/verilog/uvrisc.v:27: Can't find definition of variable: 'alu_out'\n   assign halt = (pc_we) ? alu_out == pc : 0;\n                           ^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module uvrisc
(
 input 	       clk, reset,
 input [15:0]  instr,
 input [15:0]  mem_out,
 output        mem_we,
 output [15:0] pc,
 output [15:0] mem_in, mem_addr,
 output halt
 );




   





   assign halt = (pc_we) ? alu_out == pc : 0;
   
endmodule
module uvrisc
(
 input 	       clk, reset,
 input [15:0]  instr,
 input [15:0]  mem_out,
 output        mem_we,
 output [15:0] pc,
 output [15:0] mem_in, mem_addr,
 output halt
 );





   





   assign halt = (pc_we) ? alu_out == pc : 0;
   
endmodule