data/full_repos/permissive/117439233/hdl/tb/armv6_TB.v
 line:24: before: "$"
1: b'%Error: data/full_repos/permissive/117439233/hdl/tb/armv6_TB.v:18: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("armv6.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/117439233/hdl/tb/armv6_TB.v:19: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,armv6_TB);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117439233/hdl/tb/armv6_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #50 RST = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117439233/hdl/tb/armv6_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #50 RST = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/117439233/hdl/tb/armv6_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #3000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module armv6_TB;
	reg CLK;
	reg RST;

	initial begin
        $dumpfile("armv6.vcd");
        $dumpvars(0,armv6_TB);
        CLK = 0;
        RST = 0;
        #50 RST = 1;
        #50 RST = 0;
        #3000 $finish;
    end

	always CLK = #50 ~CLK;

	armv6 DUT(
		.CLK(CLK),
		.RST(RST)
		);
endmodule
module armv6_TB;

	reg CLK;
	reg RST;

	initial begin
        $dumpfile("armv6.vcd");
        $dumpvars(0,armv6_TB);
        CLK = 0;
        RST = 0;
        #50 RST = 1;
        #50 RST = 0;
        #3000 $finish;
    end

	always CLK = #50 ~CLK;

	armv6 DUT(
		.CLK(CLK),
		.RST(RST)
		);
endmodule