data/full_repos/permissive/143278/ivltests/vcd1.v
 line:31: before: "1"
1: b'%Error: data/full_repos/permissive/143278/ivltests/vcd1.v:49: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("work/test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/vcd1.v:50: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,main.myckt);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vcd1.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vcd1.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vcd1.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vcd1.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #5 ;\n    ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

wire xout;
reg i1,i2;

xorckt myckt (.out(xout),.in0(i1),.in1(i2));

initial
  begin
    $dumpfile("work/test.vcd");
    $dumpvars(0,main.myckt);
    i1 = 1'b0;
    i2 = 1'b0;
    #5;
    $display("%b xor %b = %b",i1,i2,xout);
    i1 = 1'b1;
    i2 = 1'b0;
    #5;
    $display("%b xor %b = %b",i1,i2,xout);
    i1 = 1'b1;
    i2 = 1'b1;
    #5;
    $display("%b xor %b = %b",i1,i2,xout);
    i1 = 1'b0;
    i2 = 1'b1;
    #5 ;
    $display("%b xor %b = %b",i1,i2,xout);
  end

endmodule
module main;


wire xout;
reg i1,i2;

xorckt myckt (.out(xout),.in0(i1),.in1(i2));

initial
  begin
    $dumpfile("work/test.vcd");
    $dumpvars(0,main.myckt);
    i1 = 1'b0;
    i2 = 1'b0;
    #5;
    $display("%b xor %b = %b",i1,i2,xout);
    i1 = 1'b1;
    i2 = 1'b0;
    #5;
    $display("%b xor %b = %b",i1,i2,xout);
    i1 = 1'b1;
    i2 = 1'b1;
    #5;
    $display("%b xor %b = %b",i1,i2,xout);
    i1 = 1'b0;
    i2 = 1'b1;
    #5 ;
    $display("%b xor %b = %b",i1,i2,xout);
  end

endmodule