data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:34: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                      : ... In instance map_38\n    map_out = 1\'h0;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:35: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                      : ... In instance map_38\n    player_position_out = 1\'h0;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:36: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                      : ... In instance map_38\n    win_position_out = 1\'h0;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:37: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                      : ... In instance map_38\n    map_index = 1\'h0;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:42: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h64\' generates 7 bits.\n                                                                                                                                      : ... In instance map_38\n        player_position_out[8+7-:8] = 7\'h64;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:44: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                                                      : ... In instance map_38\n        map_index = 1\'h1;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:52: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h6d\' generates 7 bits.\n                                                                                                                                      : ... In instance map_38\n        win_position_out = 7\'h6d;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:63: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                                                                                      : ... In instance map_38\n        player_position_out[8+7-:8] = 7\'h61;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:64: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h7e\' generates 7 bits.\n                                                                                                                                      : ... In instance map_38\n        win_position_out = 7\'h7e;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:77: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                                                                      : ... In instance map_38\n        map_index = 3\'h4;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:87: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h71\' generates 7 bits.\n                                                                                                                                      : ... In instance map_38\n        player_position_out[8+7-:8] = 7\'h71;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:88: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h7d\' generates 7 bits.\n                                                                                                                                      : ... In instance map_38\n        win_position_out = 7\'h7d;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:89: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                                                                      : ... In instance map_38\n        map_index = 3\'h5;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:99: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                      : ... In instance map_38\n        player_position_out[8+7-:8] = 1\'h0;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:100: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                       : ... In instance map_38\n        win_position_out = 1\'h0;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:101: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                                                                       : ... In instance map_38\n        map_index = 3\'h6;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:107: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                       : ... In instance map_38\n        player_position_out = 1\'h0;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/map_38.v:114: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                       : ... In instance map_38\n      M_map_fsm_q <= 1\'h0;\n                  ^~\n%Error: Exiting due to 18 warning(s)\n'
module map_38 (
    input clk,
    input rst,
    input button_stage_left,
    input button_stage_right,
    input win_bool_in,
    input loss_bool_in,
    output reg [255:0] map_out,
    output reg [15:0] player_position_out,
    output reg [7:0] win_position_out,
    output reg [1:0] map_index
  );
  
  
  
  localparam MAP1_map_fsm = 3'd0;
  localparam MAP2_map_fsm = 3'd1;
  localparam MAP3_map_fsm = 3'd2;
  localparam MAP4_map_fsm = 3'd3;
  localparam MAP5_map_fsm = 3'd4;
  localparam MAPWIN_map_fsm = 3'd5;
  
  reg [2:0] M_map_fsm_d, M_map_fsm_q = MAP1_map_fsm;
  
  always @* begin
    M_map_fsm_d = M_map_fsm_q;
    
    map_out = 1'h0;
    player_position_out = 1'h0;
    win_position_out = 1'h0;
    map_index = 1'h0;
    
    case (M_map_fsm_q)
      MAP1_map_fsm: begin
        map_out = 256'h000000000000000000001c001f801ff00ff800f8007000000000000000000000;
        player_position_out[8+7-:8] = 7'h64;
        win_position_out = 8'h9a;
        map_index = 1'h1;
        if (win_bool_in || button_stage_right) begin
          M_map_fsm_d = MAP2_map_fsm;
        end
      end
      MAP2_map_fsm: begin
        map_out = 256'h0000000000000000000003cef3cef3cef3cefffef3c000000000000000000000;
        player_position_out[8+7-:8] = 8'h91;
        win_position_out = 7'h6d;
        map_index = 2'h2;
        if (win_bool_in || button_stage_right) begin
          M_map_fsm_d = MAP3_map_fsm;
        end
        if (button_stage_left) begin
          M_map_fsm_d = MAP1_map_fsm;
        end
      end
      MAP3_map_fsm: begin
        map_out = 256'h00000000000007f004f004fc7c0f0e0f0e07026003e003e001c0000000000000;
        player_position_out[8+7-:8] = 7'h61;
        win_position_out = 7'h7e;
        map_index = 2'h3;
        if (win_bool_in || button_stage_right) begin
          M_map_fsm_d = MAP4_map_fsm;
        end
        if (button_stage_left) begin
          M_map_fsm_d = MAP2_map_fsm;
        end
      end
      MAP4_map_fsm: begin
        map_out = 256'h0000000000000000000003f8f398ff9ef01ef01e000e00000000000000000000;
        player_position_out[8+7-:8] = 8'h81;
        win_position_out = 8'h8d;
        map_index = 3'h4;
        if (win_bool_in || button_stage_right) begin
          M_map_fsm_d = MAP5_map_fsm;
        end
        if (button_stage_left) begin
          M_map_fsm_d = MAP3_map_fsm;
        end
      end
      MAP5_map_fsm: begin
        map_out = 256'h000000000000000000f000f0e09eff8ee1cee1ce71003f000000000000000000;
        player_position_out[8+7-:8] = 7'h71;
        win_position_out = 7'h7d;
        map_index = 3'h5;
        if (win_bool_in || button_stage_right) begin
          M_map_fsm_d = MAPWIN_map_fsm;
        end
        if (button_stage_left) begin
          M_map_fsm_d = MAP4_map_fsm;
        end
      end
      MAPWIN_map_fsm: begin
        map_out = 256'h0000000000000000000045d2449a449a4496549629d200000000000000000000;
        player_position_out[8+7-:8] = 1'h0;
        win_position_out = 1'h0;
        map_index = 3'h6;
        if (button_stage_left) begin
          M_map_fsm_d = MAP5_map_fsm;
        end
      end
      default: begin
        player_position_out = 1'h0;
      end
    endcase
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_map_fsm_q <= 1'h0;
    end else begin
      M_map_fsm_q <= M_map_fsm_d;
    end
  end
  
endmodule
module map_38 (
    input clk,
    input rst,
    input button_stage_left,
    input button_stage_right,
    input win_bool_in,
    input loss_bool_in,
    output reg [255:0] map_out,
    output reg [15:0] player_position_out,
    output reg [7:0] win_position_out,
    output reg [1:0] map_index
  );

  
  
  
  localparam MAP1_map_fsm = 3'd0;
  localparam MAP2_map_fsm = 3'd1;
  localparam MAP3_map_fsm = 3'd2;
  localparam MAP4_map_fsm = 3'd3;
  localparam MAP5_map_fsm = 3'd4;
  localparam MAPWIN_map_fsm = 3'd5;
  
  reg [2:0] M_map_fsm_d, M_map_fsm_q = MAP1_map_fsm;
  
  always @* begin
    M_map_fsm_d = M_map_fsm_q;
    
    map_out = 1'h0;
    player_position_out = 1'h0;
    win_position_out = 1'h0;
    map_index = 1'h0;
    
    case (M_map_fsm_q)
      MAP1_map_fsm: begin
        map_out = 256'h000000000000000000001c001f801ff00ff800f8007000000000000000000000;
        player_position_out[8+7-:8] = 7'h64;
        win_position_out = 8'h9a;
        map_index = 1'h1;
        if (win_bool_in || button_stage_right) begin
          M_map_fsm_d = MAP2_map_fsm;
        end
      end
      MAP2_map_fsm: begin
        map_out = 256'h0000000000000000000003cef3cef3cef3cefffef3c000000000000000000000;
        player_position_out[8+7-:8] = 8'h91;
        win_position_out = 7'h6d;
        map_index = 2'h2;
        if (win_bool_in || button_stage_right) begin
          M_map_fsm_d = MAP3_map_fsm;
        end
        if (button_stage_left) begin
          M_map_fsm_d = MAP1_map_fsm;
        end
      end
      MAP3_map_fsm: begin
        map_out = 256'h00000000000007f004f004fc7c0f0e0f0e07026003e003e001c0000000000000;
        player_position_out[8+7-:8] = 7'h61;
        win_position_out = 7'h7e;
        map_index = 2'h3;
        if (win_bool_in || button_stage_right) begin
          M_map_fsm_d = MAP4_map_fsm;
        end
        if (button_stage_left) begin
          M_map_fsm_d = MAP2_map_fsm;
        end
      end
      MAP4_map_fsm: begin
        map_out = 256'h0000000000000000000003f8f398ff9ef01ef01e000e00000000000000000000;
        player_position_out[8+7-:8] = 8'h81;
        win_position_out = 8'h8d;
        map_index = 3'h4;
        if (win_bool_in || button_stage_right) begin
          M_map_fsm_d = MAP5_map_fsm;
        end
        if (button_stage_left) begin
          M_map_fsm_d = MAP3_map_fsm;
        end
      end
      MAP5_map_fsm: begin
        map_out = 256'h000000000000000000f000f0e09eff8ee1cee1ce71003f000000000000000000;
        player_position_out[8+7-:8] = 7'h71;
        win_position_out = 7'h7d;
        map_index = 3'h5;
        if (win_bool_in || button_stage_right) begin
          M_map_fsm_d = MAPWIN_map_fsm;
        end
        if (button_stage_left) begin
          M_map_fsm_d = MAP4_map_fsm;
        end
      end
      MAPWIN_map_fsm: begin
        map_out = 256'h0000000000000000000045d2449a449a4496549629d200000000000000000000;
        player_position_out[8+7-:8] = 1'h0;
        win_position_out = 1'h0;
        map_index = 3'h6;
        if (button_stage_left) begin
          M_map_fsm_d = MAP5_map_fsm;
        end
      end
      default: begin
        player_position_out = 1'h0;
      end
    endcase
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_map_fsm_q <= 1'h0;
    end else begin
      M_map_fsm_q <= M_map_fsm_d;
    end
  end
  
endmodule