data/full_repos/permissive/147790758/tb2f_b2bd.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2f_b2bd.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147790758/tb2f_b2bd.v:13: Cannot find file containing module: \'b2bd\'\nb2bd DUT (.sw(datain), .led(dataout));\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b2bd\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b2bd.v\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b2bd.sv\n             b2bd\n             b2bd.v\n             b2bd.sv\n             obj_dir/b2bd\n             obj_dir/b2bd.v\n             obj_dir/b2bd.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb2f_b2bd();
	
	reg [3:0]datain;
	reg [7:0]expected;
	wire [7:0]dataout;
	reg [3:0]tetrad;
	integer i;
	reg [3:0] input_mem [0:5];
	reg [7:0] expected_mem [0:5];
	
b2bd DUT (.sw(datain), .led(dataout));
	
initial begin: read_dataFile
	$display("**UNIT TEST STARTED**");
	$readmemb("input_b2bd.dat", input_mem);
	$readmemb("exp_b2bd.dat", expected_mem);
end 

initial begin: test_work
	for (i=0; i<=5; i=i+1) begin
		datain = input_mem[i];
		#10;
		$display("Now testing with inputs: %b, Expected result: %b Actual result: %b", datain, expected_mem[i], dataout);
		if (dataout != expected_mem[i]) begin
			$display("ERROR: Expected %b, but got %b. Inputs were: %b", expected_mem[i], dataout, datain);
			$display("**ERROR: UNIT DOES NOT WORK PROPERLY**");
			$stop;
		end 
	end
	$display("**ALL TESTS PASSED**");
	$stop;
end

endmodule
module tb2f_b2bd();

	
	reg [3:0]datain;
	reg [7:0]expected;
	wire [7:0]dataout;
	reg [3:0]tetrad;
	integer i;
	reg [3:0] input_mem [0:5];
	reg [7:0] expected_mem [0:5];
	
b2bd DUT (.sw(datain), .led(dataout));
	
initial begin: read_dataFile
	$display("**UNIT TEST STARTED**");
	$readmemb("input_b2bd.dat", input_mem);
	$readmemb("exp_b2bd.dat", expected_mem);
end 

initial begin: test_work
	for (i=0; i<=5; i=i+1) begin
		datain = input_mem[i];
		#10;
		$display("Now testing with inputs: %b, Expected result: %b Actual result: %b", datain, expected_mem[i], dataout);
		if (dataout != expected_mem[i]) begin
			$display("ERROR: Expected %b, but got %b. Inputs were: %b", expected_mem[i], dataout, datain);
			$display("**ERROR: UNIT DOES NOT WORK PROPERLY**");
			$stop;
		end 
	end
	$display("**ALL TESTS PASSED**");
	$stop;
end

endmodule