data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv
 line:18: before: "CHDR_W"
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:23: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream,data/full_repos/permissive/214858095/test_exec.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream,data/full_repos/permissive/214858095/test_exec.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream,data/full_repos/permissive/214858095/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:25: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgTestExec::*;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:80: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);\n                                               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:83: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:84: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::item_t      item_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:100: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrPacket #(CHDR_W) ChdrPacket_t;\n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:183: Unsupported: Static in this context\n    static int count;\n    ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:196: Unsupported: Static in this context\n    static int count;\n    ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:214: Unsupported: classes\n  class Rand #(WIDTH = 32);\n  ^~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:215: Unsupported: \'static\' class item\n    static function logic [WIDTH-1:0] rand_logic();\n    ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:219: Unsupported or unknown PLI call: $urandom\n        result = {result, $urandom()};\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:227: syntax error, unexpected IDENTIFIER, expecting \'(\' or \';\'\n  function automatic ChdrPacket_t gen_rand_chdr_pkt(int num_samps);\n                                  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:228: syntax error, unexpected \'=\', expecting \',\' or \';\'\n    ChdrPacket_t  packet = new();\n                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:237: syntax error, unexpected \'=\', expecting IDENTIFIER\n    header = Rand#($bits(header))::rand_logic();\n           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:238: syntax error, unexpected \'=\', expecting IDENTIFIER\n    header.pkt_type  = CHDR_DATA_NO_TS;\n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:239: syntax error, unexpected \'=\', expecting IDENTIFIER\n    header.num_mdata = 0;\n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:240: syntax error, unexpected \'=\', expecting IDENTIFIER\n    header.length    = CHDR_W/8 + num_samps*ITEM_W/8;   \n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:247: syntax error, unexpected \'(\', expecting IDENTIFIER\n      data.push_back(Rand#(CHDR_W)::rand_logic());\n                     ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:250: syntax error, unexpected \'(\', expecting IDENTIFIER\n    packet.write_raw(header, data);\n                     ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:278: syntax error, unexpected \'=\', expecting \',\' or \';\'\n    mailbox #(ChdrPacket_t) packets = new();\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:281: syntax error, unexpected \'(\', expecting IDENTIFIER\n    blk_ctrl.set_master_stall_prob(port,    stall_prob_m);\n                                   ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:282: syntax error, unexpected int, expecting IDENTIFIER or genvar\n    for (int branch=0; branch < NUM_BRANCHES; branch++)\n         ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:297: Unsupported or unknown PLI call: $urandom_range\n          packet = gen_rand_chdr_pkt($urandom_range(max_samps));\n                                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:298: syntax error, unexpected \'(\', expecting IDENTIFIER\n          packets.put(packet);\n                      ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:299: syntax error, unexpected \'(\', expecting IDENTIFIER\n          master_bfm.put_chdr(packet);\n                              ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:323: Define or directive not defined: \'`ASSERT_ERROR\'\n            `ASSERT_ERROR(packet.equal(expected), error_msg);\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:343: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_tb(tb_name);\n                  ^~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:348: syntax error, unexpected \'(\', expecting IDENTIFIER\n    rfnoc_chdr_clk_gen.start();\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:349: syntax error, unexpected \'(\', expecting IDENTIFIER\n    rfnoc_ctrl_clk_gen.start();\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:352: syntax error, unexpected \'(\', expecting IDENTIFIER\n    blk_ctrl.run();\n                 ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:358: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Flush block then reset it", 10us);\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:359: syntax error, unexpected \'(\', expecting IDENTIFIER\n    blk_ctrl.flush_and_reset();\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:360: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:366: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Verify Block Info", 2us);\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:367: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:368: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:369: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:370: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:371: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:377: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Test short packets", 1ms);\n                    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:379: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:381: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Test long packets", 1ms);\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:383: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:385: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Test short packets, fast source, slow sink", 1ms);\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:387: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:389: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Test long packets, fast source, slow sink", 1ms);\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:391: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:394: syntax error, unexpected \'(\', expecting IDENTIFIER\n      test.start_test("Test another port", 1ms);\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:398: syntax error, unexpected \'(\', expecting IDENTIFIER\n      test.end_test();\n                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_split_stream/rfnoc_block_split_stream_tb.sv:401: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Check input stall", 1us);\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module rfnoc_block_split_stream_tb #(
  parameter int CHDR_W       = 64,
  parameter int NUM_PORTS    = 1,
  parameter int NUM_BRANCHES = 2
);

  `include "test_exec.svh"

  import PkgTestExec::*;
  import PkgChdrUtils::*;
  import PkgRfnocBlockCtrlBfm::*;
  import PkgRfnocItemUtils::*;






  localparam [ 9:0] THIS_PORTID     = 10'h123;
  localparam [31:0] NOC_ID          = 32'h57570000;
  localparam int    ITEM_W          = 32;
  localparam int    NUM_PORTS_I     = NUM_PORTS;
  localparam int    NUM_PORTS_O     = NUM_PORTS*NUM_BRANCHES;
  localparam int    MTU             = $clog2(512);
  localparam int    SPP             = 128;
  localparam int    PKT_SIZE_BYTES  = SPP * (ITEM_W/8);
  localparam int    STALL_PROB      = 25;
  localparam real   CHDR_CLK_PER    = 5.0;
  localparam real   CTRL_CLK_PER    = 25.0;






  bit rfnoc_chdr_clk;
  bit rfnoc_ctrl_clk;




  sim_clock_gen #(.PERIOD(CHDR_CLK_PER), .AUTOSTART(0))
    rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
  sim_clock_gen #(.PERIOD(CTRL_CLK_PER), .AUTOSTART(0))
    rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());







  RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_ctrl_clk);


  AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, 1'b0);
  AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, 1'b0);


  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS_I] (rfnoc_chdr_clk, 1'b0);
  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS_O] (rfnoc_chdr_clk, 1'b0);


  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);


  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_t      item_t;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_bfm_input_connections
    initial begin
      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
    end
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_bfm_output_connections
    initial begin
      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
    end
  end

  typedef ChdrPacket #(CHDR_W) ChdrPacket_t;







  logic [CHDR_W*NUM_PORTS_I-1:0] s_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tready;


  logic [CHDR_W*NUM_PORTS_O-1:0] m_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tready;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_dut_input_connections

    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_dut_output_connections

    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
  end

  rfnoc_block_split_stream #(
    .THIS_PORTID         (THIS_PORTID),
    .CHDR_W              (CHDR_W),
    .MTU                 (MTU),
    .NUM_PORTS           (NUM_PORTS),
    .NUM_BRANCHES        (NUM_BRANCHES)
  ) dut (
    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
    .rfnoc_core_config   (backend.cfg),
    .rfnoc_core_status   (backend.sts),
    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
    .s_rfnoc_ctrl_tdata  (m_ctrl.tdata),
    .s_rfnoc_ctrl_tlast  (m_ctrl.tlast),
    .s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
    .s_rfnoc_ctrl_tready (m_ctrl.tready),
    .m_rfnoc_ctrl_tdata  (s_ctrl.tdata),
    .m_rfnoc_ctrl_tlast  (s_ctrl.tlast),
    .m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
    .m_rfnoc_ctrl_tready (s_ctrl.tready)
  );











  const int STALL_THRESH = 50;



  int input_stall_count = 0;
  int split_stall_count = 0;


  always @(posedge rfnoc_chdr_clk) begin : check_input_stall
    static int count;
    if (s_rfnoc_chdr_tvalid[0] === 1'b1 && s_rfnoc_chdr_tready[0] === 1'b0) begin
      count++;
      if (count == STALL_THRESH) begin
        input_stall_count++;
      end
    end else begin
      count=0;      
    end
  end


  always @(posedge rfnoc_chdr_clk) begin : check_splitter_stall
    static int count;
    if (dut.gen_splitters[0].in_tvalid === 1'b1 && dut.gen_splitters[0].in_tready === 1'b0) begin
      count++;
      if (count == STALL_THRESH) begin
        split_stall_count++;
      end
    end else begin
      count=0;      
    end
  end








  class Rand #(WIDTH = 32);
    static function logic [WIDTH-1:0] rand_logic();
      logic [WIDTH-1:0] result;
      int num_rand32 = (WIDTH + 31) / 32;
      for (int i = 0; i < num_rand32; i++) begin
        result = {result, $urandom()};
      end
      return result;
    endfunction : rand_logic
  endclass : Rand



  function automatic ChdrPacket_t gen_rand_chdr_pkt(int num_samps);
    ChdrPacket_t  packet = new();
    chdr_header_t header;
    chdr_word_t   data[$];




    

    header = Rand#($bits(header))::rand_logic();
    header.pkt_type  = CHDR_DATA_NO_TS;
    header.num_mdata = 0;
    header.length    = CHDR_W/8 + num_samps*ITEM_W/8;


    repeat (num_samps * ITEM_W / CHDR_W) 
      data.push_back(Rand#(CHDR_W)::rand_logic());

    if (num_samps * ITEM_W % CHDR_W != 0)
      data.push_back(Rand#(CHDR_W)::rand_logic());


    packet.write_raw(header, data);

    return packet;
  endfunction : gen_rand_chdr_pkt












  task automatic test_rand(
    int port          = 0,
    int num_packets   = 100,
    int max_samps     = SPP,
    int stall_prob_m  = STALL_PROB,
    int stall_prob_s  = STALL_PROB
  );

    ChdrIfaceBfm #(CHDR_W, ITEM_W) master_bfm;
    ChdrIfaceBfm #(CHDR_W, ITEM_W) slave_bfm[NUM_BRANCHES];


    mailbox #(ChdrPacket_t) packets = new();


    blk_ctrl.set_master_stall_prob(port,    stall_prob_m);
    for (int branch=0; branch < NUM_BRANCHES; branch++)
      blk_ctrl.set_slave_stall_prob(NUM_PORTS*branch + port, stall_prob_s);


    master_bfm = blk_ctrl.get_master_data_bfm(port);
    foreach (slave_bfm[branch])
      slave_bfm[branch] = blk_ctrl.get_slave_data_bfm(NUM_PORTS*branch + port);

    fork



      begin : master
        ChdrPacket_t packet;
        repeat (num_packets) begin
          packet = gen_rand_chdr_pkt($urandom_range(max_samps));
          packets.put(packet);
          master_bfm.put_chdr(packet);
        end        
      end




      begin : slaves
        ChdrPacket_t expected, packet;

        repeat (num_packets) begin

          packets.get(expected);



          foreach (slave_bfm[branch]) begin
            string error_msg;
            $sformat(
              error_msg, 
              "Received packet on branch %d of port %d did not match input packet",
              branch, port
            );
            slave_bfm[branch].get_chdr(packet);
            `ASSERT_ERROR(packet.equal(expected), error_msg);
          end
        end
      end
    join
  endtask : test_rand






  initial begin : tb_main
    string tb_name;


    tb_name = $sformatf(
      "rfnoc_block_split_stream_tb\nCHDR_W = %0D, NUM_PORTS = %0D, NUM_BRANCHES = %0D",
      CHDR_W, NUM_PORTS, NUM_BRANCHES
    );
    test.start_tb(tb_name);




    rfnoc_chdr_clk_gen.start();
    rfnoc_ctrl_clk_gen.start();


    blk_ctrl.run();





    test.start_test("Flush block then reset it", 10us);
    blk_ctrl.flush_and_reset();
    test.end_test();





    test.start_test("Verify Block Info", 2us);
    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");
    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
    test.end_test();





    test.start_test("Test short packets", 1ms);
    test_rand(0, 1000, 4*CHDR_W/ITEM_W);
    test.end_test();

    test.start_test("Test long packets", 1ms);
    test_rand(0, 100, SPP);
    test.end_test();

    test.start_test("Test short packets, fast source, slow sink", 1ms);
    test_rand(0, 1000, 4*CHDR_W/ITEM_W, 10, 90);
    test.end_test();

    test.start_test("Test long packets, fast source, slow sink", 1ms);
    test_rand(0, 200, SPP, 10, 90);
    test.end_test();

    if (NUM_PORTS > 1) begin
      test.start_test("Test another port", 1ms);


      test_rand(NUM_PORTS-1, 100, 4*CHDR_W/ITEM_W);
      test.end_test();
    end

    test.start_test("Check input stall", 1us);


    `ASSERT_ERROR(input_stall_count > 20, "Input never filled during tests");
    `ASSERT_ERROR(split_stall_count > 20, "Splitter never filled during tests");
    test.end_test();







    test.end_tb(0);


    rfnoc_chdr_clk_gen.kill();
    rfnoc_ctrl_clk_gen.kill();

  end : tb_main

endmodule
module rfnoc_block_split_stream_tb #(
  parameter int CHDR_W       = 64,
  parameter int NUM_PORTS    = 1,
  parameter int NUM_BRANCHES = 2
);


  `include "test_exec.svh"

  import PkgTestExec::*;
  import PkgChdrUtils::*;
  import PkgRfnocBlockCtrlBfm::*;
  import PkgRfnocItemUtils::*;






  localparam [ 9:0] THIS_PORTID     = 10'h123;
  localparam [31:0] NOC_ID          = 32'h57570000;
  localparam int    ITEM_W          = 32;
  localparam int    NUM_PORTS_I     = NUM_PORTS;
  localparam int    NUM_PORTS_O     = NUM_PORTS*NUM_BRANCHES;
  localparam int    MTU             = $clog2(512);
  localparam int    SPP             = 128;
  localparam int    PKT_SIZE_BYTES  = SPP * (ITEM_W/8);
  localparam int    STALL_PROB      = 25;
  localparam real   CHDR_CLK_PER    = 5.0;
  localparam real   CTRL_CLK_PER    = 25.0;






  bit rfnoc_chdr_clk;
  bit rfnoc_ctrl_clk;




  sim_clock_gen #(.PERIOD(CHDR_CLK_PER), .AUTOSTART(0))
    rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
  sim_clock_gen #(.PERIOD(CTRL_CLK_PER), .AUTOSTART(0))
    rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());







  RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_ctrl_clk);


  AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, 1'b0);
  AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, 1'b0);


  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS_I] (rfnoc_chdr_clk, 1'b0);
  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS_O] (rfnoc_chdr_clk, 1'b0);


  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);


  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_t      item_t;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_bfm_input_connections
    initial begin
      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
    end
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_bfm_output_connections
    initial begin
      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
    end
  end

  typedef ChdrPacket #(CHDR_W) ChdrPacket_t;







  logic [CHDR_W*NUM_PORTS_I-1:0] s_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tready;


  logic [CHDR_W*NUM_PORTS_O-1:0] m_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tready;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_dut_input_connections

    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_dut_output_connections

    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
  end

  rfnoc_block_split_stream #(
    .THIS_PORTID         (THIS_PORTID),
    .CHDR_W              (CHDR_W),
    .MTU                 (MTU),
    .NUM_PORTS           (NUM_PORTS),
    .NUM_BRANCHES        (NUM_BRANCHES)
  ) dut (
    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
    .rfnoc_core_config   (backend.cfg),
    .rfnoc_core_status   (backend.sts),
    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
    .s_rfnoc_ctrl_tdata  (m_ctrl.tdata),
    .s_rfnoc_ctrl_tlast  (m_ctrl.tlast),
    .s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
    .s_rfnoc_ctrl_tready (m_ctrl.tready),
    .m_rfnoc_ctrl_tdata  (s_ctrl.tdata),
    .m_rfnoc_ctrl_tlast  (s_ctrl.tlast),
    .m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
    .m_rfnoc_ctrl_tready (s_ctrl.tready)
  );











  const int STALL_THRESH = 50;



  int input_stall_count = 0;
  int split_stall_count = 0;


  always @(posedge rfnoc_chdr_clk) begin : check_input_stall
    static int count;
    if (s_rfnoc_chdr_tvalid[0] === 1'b1 && s_rfnoc_chdr_tready[0] === 1'b0) begin
      count++;
      if (count == STALL_THRESH) begin
        input_stall_count++;
      end
    end else begin
      count=0;      
    end
  end


  always @(posedge rfnoc_chdr_clk) begin : check_splitter_stall
    static int count;
    if (dut.gen_splitters[0].in_tvalid === 1'b1 && dut.gen_splitters[0].in_tready === 1'b0) begin
      count++;
      if (count == STALL_THRESH) begin
        split_stall_count++;
      end
    end else begin
      count=0;      
    end
  end








  class Rand #(WIDTH = 32);
    static function logic [WIDTH-1:0] rand_logic();
      logic [WIDTH-1:0] result;
      int num_rand32 = (WIDTH + 31) / 32;
      for (int i = 0; i < num_rand32; i++) begin
        result = {result, $urandom()};
      end
      return result;
    endfunction : rand_logic
  endclass : Rand



  function automatic ChdrPacket_t gen_rand_chdr_pkt(int num_samps);
    ChdrPacket_t  packet = new();
    chdr_header_t header;
    chdr_word_t   data[$];




    

    header = Rand#($bits(header))::rand_logic();
    header.pkt_type  = CHDR_DATA_NO_TS;
    header.num_mdata = 0;
    header.length    = CHDR_W/8 + num_samps*ITEM_W/8;


    repeat (num_samps * ITEM_W / CHDR_W) 
      data.push_back(Rand#(CHDR_W)::rand_logic());

    if (num_samps * ITEM_W % CHDR_W != 0)
      data.push_back(Rand#(CHDR_W)::rand_logic());


    packet.write_raw(header, data);

    return packet;
  endfunction : gen_rand_chdr_pkt












  task automatic test_rand(
    int port          = 0,
    int num_packets   = 100,
    int max_samps     = SPP,
    int stall_prob_m  = STALL_PROB,
    int stall_prob_s  = STALL_PROB
  );

    ChdrIfaceBfm #(CHDR_W, ITEM_W) master_bfm;
    ChdrIfaceBfm #(CHDR_W, ITEM_W) slave_bfm[NUM_BRANCHES];


    mailbox #(ChdrPacket_t) packets = new();


    blk_ctrl.set_master_stall_prob(port,    stall_prob_m);
    for (int branch=0; branch < NUM_BRANCHES; branch++)
      blk_ctrl.set_slave_stall_prob(NUM_PORTS*branch + port, stall_prob_s);


    master_bfm = blk_ctrl.get_master_data_bfm(port);
    foreach (slave_bfm[branch])
      slave_bfm[branch] = blk_ctrl.get_slave_data_bfm(NUM_PORTS*branch + port);

    fork



      begin : master
        ChdrPacket_t packet;
        repeat (num_packets) begin
          packet = gen_rand_chdr_pkt($urandom_range(max_samps));
          packets.put(packet);
          master_bfm.put_chdr(packet);
        end        
      end




      begin : slaves
        ChdrPacket_t expected, packet;

        repeat (num_packets) begin

          packets.get(expected);



          foreach (slave_bfm[branch]) begin
            string error_msg;
            $sformat(
              error_msg, 
              "Received packet on branch %d of port %d did not match input packet",
              branch, port
            );
            slave_bfm[branch].get_chdr(packet);
            `ASSERT_ERROR(packet.equal(expected), error_msg);
          end
        end
      end
    join
  endtask : test_rand






  initial begin : tb_main
    string tb_name;


    tb_name = $sformatf(
      "rfnoc_block_split_stream_tb\nCHDR_W = %0D, NUM_PORTS = %0D, NUM_BRANCHES = %0D",
      CHDR_W, NUM_PORTS, NUM_BRANCHES
    );
    test.start_tb(tb_name);




    rfnoc_chdr_clk_gen.start();
    rfnoc_ctrl_clk_gen.start();


    blk_ctrl.run();





    test.start_test("Flush block then reset it", 10us);
    blk_ctrl.flush_and_reset();
    test.end_test();





    test.start_test("Verify Block Info", 2us);
    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");
    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
    test.end_test();





    test.start_test("Test short packets", 1ms);
    test_rand(0, 1000, 4*CHDR_W/ITEM_W);
    test.end_test();

    test.start_test("Test long packets", 1ms);
    test_rand(0, 100, SPP);
    test.end_test();

    test.start_test("Test short packets, fast source, slow sink", 1ms);
    test_rand(0, 1000, 4*CHDR_W/ITEM_W, 10, 90);
    test.end_test();

    test.start_test("Test long packets, fast source, slow sink", 1ms);
    test_rand(0, 200, SPP, 10, 90);
    test.end_test();

    if (NUM_PORTS > 1) begin
      test.start_test("Test another port", 1ms);


      test_rand(NUM_PORTS-1, 100, 4*CHDR_W/ITEM_W);
      test.end_test();
    end

    test.start_test("Check input stall", 1us);


    `ASSERT_ERROR(input_stall_count > 20, "Input never filled during tests");
    `ASSERT_ERROR(split_stall_count > 20, "Splitter never filled during tests");
    test.end_test();







    test.end_tb(0);


    rfnoc_chdr_clk_gen.kill();
    rfnoc_ctrl_clk_gen.kill();

  end : tb_main

endmodule