data/full_repos/permissive/178052224/Tarea3y4/modules/flip-flop.v
 line:41: before: "+"
data/verilator_xmls/9b9433b2-6661-4016-a564-4f86a88841ec.xml
module ff_d_nand(
    output reg Q,
    input D, CLK, CLR_BAR   
);


    parameter Vcc = 5;
    parameter t_hmin = 0.5;
    parameter t_hmax = 0.7;

    parameter C_L = 0.05 ;


    integer counter;
    initial counter = 0;



    always@(posedge CLK) begin
        if (CLR_BAR != 0)
            Q <= D;
        else
            Q <= 0;
    end    

    always@(Q) begin
        counter += 1;
        $display("Potencia disipada en el Flip Flop: %f", counter * C_L * Vcc * Vcc );
    end
endmodule
module ff_d_nand(
    output reg Q,
    input D, CLK, CLR_BAR   
);



    parameter Vcc = 5;
    parameter t_hmin = 0.5;
    parameter t_hmax = 0.7;

    parameter C_L = 0.05 ;


    integer counter;
    initial counter = 0;



    always@(posedge CLK) begin
        if (CLR_BAR != 0)
            Q <= D;
        else
            Q <= 0;
    end    

    always@(Q) begin
        counter += 1;
        $display("Potencia disipada en el Flip Flop: %f", counter * C_L * Vcc * Vcc );
    end
endmodule