data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Demux_tb.v
1: b'%Error: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Demux_tb.v:1: Cannot find include file: Demux.v\n`include "Demux.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/Demux.v\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/Demux.v.v\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/Demux.v.sv\n             Demux.v\n             Demux.v.v\n             Demux.v.sv\n             obj_dir/Demux.v\n             obj_dir/Demux.v.v\n             obj_dir/Demux.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Demux_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("Demux_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Demux_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,Demux_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Demux_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module Demux_tb;

reg In;
wire [3:0] Out;
reg [1:0] Sel;
integer i;

DeMux demux0 (In,Out,Sel);

initial begin
    $dumpfile("Demux_tb.vcd");
    $dumpvars(0,Demux_tb);
    for(i = 0; i < 4; i = i+1) 
    begin
        Out <= 4'b1111;
        In <= 1'b1;
        Sel <= i;
        #500;
    end
    $finish;
end



endmodule
module Demux_tb;


reg In;
wire [3:0] Out;
reg [1:0] Sel;
integer i;

DeMux demux0 (In,Out,Sel);

initial begin
    $dumpfile("Demux_tb.vcd");
    $dumpvars(0,Demux_tb);
    for(i = 0; i < 4; i = i+1) 
    begin
        Out <= 4'b1111;
        In <= 1'b1;
        Sel <= i;
        #500;
    end
    $finish;
end



endmodule