data/full_repos/permissive/211316121/lab5_3_nexys4/74LS173.v
1: b'%Warning-WIDTH: data/full_repos/permissive/211316121/lab5_3_nexys4/74LS173.v:35: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n                                                                               : ... In instance Top_74LS173.top_173\n        Q<=\'bzzzz;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module CLKDIV(
    input clkstd,
    output clk
);
reg [26:0] q;

always@(posedge clkstd)
    q<=q+1;

assign clk=q[26];

endmodule
module CLKDIV(
    input clkstd,
    output clk
);

reg [26:0] q;

always@(posedge clkstd)
    q<=q+1;

assign clk=q[26];

endmodule