data/full_repos/permissive/150482260/d_flipflop.v
 line:42: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/150482260/d_flipflop.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10 clear = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150482260/d_flipflop.v:33: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clock = ~clock;\n                ^\n%Error: data/full_repos/permissive/150482260/d_flipflop.v:37: Unsupported or unknown PLI call: $monitor\n        $monitor("%d clock=%b d=%b -> q=%b", $time, clock, d, q);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150482260/d_flipflop.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10 d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/d_flipflop.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10 d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/d_flipflop.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10 d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/d_flipflop.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module d_flipflop (
    input clock,
    input clear,
    input d,
    output reg q
);

    always @(negedge clock, posedge clear)
        if (clear)
            q = 0;
        else
            q = d;
endmodule
module d_flipflop (
    input clock,
    input clear,
    input d,
    output reg q
);


    always @(negedge clock, posedge clear)
        if (clear)
            q = 0;
        else
            q = d;
endmodule