data/full_repos/permissive/165514176/Matrix_scalar.v
data/verilator_xmls/e09f32c7-f5f9-4ecd-a6d5-2b7eca79f191.xml
module Matrix_scalar(A,B,clk,Res);
	parameter widthbig = 127; 
	parameter width = 31;


    input signed [127:0] A;
    input signed[127:0] B;
    output signed [127:0] Res;

    reg signed [127:0] Res;
    reg signed [31:0] A1 [0:1][0:1];
    reg signed [31:0] B1 [0:1][0:1];
    reg signed [31:0] Res1 [0:1][0:1];  
	 reg signed [31:0]temp1= 32'd25;
	 reg signed [31:0]temp2 = 32'd5;
	 	 reg signed go = 1'b1;
    integer i,j,k;

    input clk;

    always@ (A or B)
    begin

        {A1[0][0],A1[0][1],A1[1][0],A1[1][1]} = A;
        {B1[0][0],B1[0][1],B1[1][0],B1[1][1]} = B;
        i = 0;
        j = 0;
        k = 0;
        {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]} = 128'd0;

        for(i=0;i < 2;i=i+1)
            for(j=0;j < 2;j=j+1)
                for(k=0;k < 2;k=k+1)
                    Res1[i][j] = Res1[i][j] + (A1[i][k] * B1[k][j]);

        Res = {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]};     
    end 

endmodule
module Matrix_scalar(A,B,clk,Res);

	parameter widthbig = 127; 
	parameter width = 31;


    input signed [127:0] A;
    input signed[127:0] B;
    output signed [127:0] Res;

    reg signed [127:0] Res;
    reg signed [31:0] A1 [0:1][0:1];
    reg signed [31:0] B1 [0:1][0:1];
    reg signed [31:0] Res1 [0:1][0:1];  
	 reg signed [31:0]temp1= 32'd25;
	 reg signed [31:0]temp2 = 32'd5;
	 	 reg signed go = 1'b1;
    integer i,j,k;

    input clk;

    always@ (A or B)
    begin

        {A1[0][0],A1[0][1],A1[1][0],A1[1][1]} = A;
        {B1[0][0],B1[0][1],B1[1][0],B1[1][1]} = B;
        i = 0;
        j = 0;
        k = 0;
        {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]} = 128'd0;

        for(i=0;i < 2;i=i+1)
            for(j=0;j < 2;j=j+1)
                for(k=0;k < 2;k=k+1)
                    Res1[i][j] = Res1[i][j] + (A1[i][k] * B1[k][j]);

        Res = {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]};     
    end 

endmodule