data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/PC_adder.v
data/verilator_xmls/ae19b47e-0486-4002-ba6c-d39e7cf022c4.xml
module PC_adder(inputPC, outputPC);
    
    input [31:0] inputPC;
    output reg [31:0] outputPC;
    
    parameter [31:0] INCREMENT_AMOUNT = 32'd4;
    
    initial
    begin
        outputPC <= 'd100;
    end
         
    always @ (inputPC) 
    begin
        outputPC <= inputPC + INCREMENT_AMOUNT;    
    end
    
endmodule
module PC_adder(inputPC, outputPC);

    
    input [31:0] inputPC;
    output reg [31:0] outputPC;
    
    parameter [31:0] INCREMENT_AMOUNT = 32'd4;
    
    initial
    begin
        outputPC <= 'd100;
    end
         
    always @ (inputPC) 
    begin
        outputPC <= inputPC + INCREMENT_AMOUNT;    
    end
    
endmodule