data/full_repos/permissive/109400221/hdl/nand/ErrLoc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/109400221/hdl/nand/ErrLoc.v:72: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                         : ... In instance ErrLoc\n  din <= 8\'h00;\n      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ErrLoc(
      clk,
      Res,
      F_ecc_data ,
      WrECC,
      error_bv,
      ECC_status
);
  input    clk;
  input    Res;
  input  [6:0]  F_ecc_data ;
  input    WrECC ;
  input    error_bv;

  output reg ECC_status;

wire check1,check2,check3;
reg [6:0] din;

always@(posedge clk)
 if (Res)
  din <= 8'h00;
 else if (WrECC)
  din <= F_ecc_data;

assign check1=din[6]^din[4]^din[2]^din[0];
assign check2=din[5]^din[4]^din[1]^din[0];
assign check3=din[3]^din[2]^din[1]^din[0];

always@(posedge clk)
 if (Res)
  ECC_status <= 1'h0;
 else
  ECC_status <= (check1 | check2 | check3 | error_bv);


endmodule
module ErrLoc(
      clk,
      Res,
      F_ecc_data ,
      WrECC,
      error_bv,
      ECC_status
);

  input    clk;
  input    Res;
  input  [6:0]  F_ecc_data ;
  input    WrECC ;
  input    error_bv;

  output reg ECC_status;

wire check1,check2,check3;
reg [6:0] din;

always@(posedge clk)
 if (Res)
  din <= 8'h00;
 else if (WrECC)
  din <= F_ecc_data;

assign check1=din[6]^din[4]^din[2]^din[0];
assign check2=din[5]^din[4]^din[1]^din[0];
assign check3=din[3]^din[2]^din[1]^din[0];

always@(posedge clk)
 if (Res)
  ECC_status <= 1'h0;
 else
  ECC_status <= (check1 | check2 | check3 | error_bv);


endmodule