data/full_repos/permissive/216615048/src/mux.v
data/verilator_xmls/ec74f0c8-2d4b-4040-9920-9def3b53bb09.xml
module mux(input a, input b, input sel, output c);
    assign c = sel ? b : a;
endmodule
module mux(input a, input b, input sel, output c);

    assign c = sel ? b : a;
endmodule