data/full_repos/permissive/158922207/Verilog Design/modules/mux3_1.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/mux3_1.v\n%Error: Exiting due to 3 error(s)\n'
module Mux3_1(sel,A,B,C,F);
parameter N = 32;
input [1:0] sel;
input [N-1:0] C, A, B;
output [N-1:0] F;
reg [N-1:0] F;
always @(A,B,C,sel) begin
case (sel)
   2'b00: F<=A;
   2'b01: F<=B;
   2'b10: F<=C;
   default: F<=0;
endcase
end
endmodule
module Mux3_1(sel,A,B,C,F);

parameter N = 32;
input [1:0] sel;
input [N-1:0] C, A, B;
output [N-1:0] F;
reg [N-1:0] F;
always @(A,B,C,sel) begin
case (sel)
   2'b00: F<=A;
   2'b01: F<=B;
   2'b10: F<=C;
   default: F<=0;
endcase
end
endmodule