data/full_repos/permissive/175808891/verilog/prv32.v
 line:209: before: "("
1: b"%Error: data/full_repos/permissive/175808891/verilog/prv32.v:280: syntax error, unexpected type\n    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));\n                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:310: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    output reg [31:0] do\n                      ^~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:315: syntax error, unexpected '='\n        3'b100  : do = {24'b0,di[7:0]};\n                     ^\n%Error: Cannot continue\n"
module prv32_memData(
    input wire [2:0] func3,
    input wire [31:0] di,
    output reg [31:0] do
);

    always @ * begin
        case (func3)
        3'b100  : do = {24'b0,di[7:0]};
        3'b000  : do = { {24{di[7]}}, di[7:0] };
        3'b101  : do = {16'b0,di[15:0]};
        3'b001  : do = { {16{di[15]} },di[15:0]};
        default : do = di;
        endcase
    end

endmodule
module prv32_memData(
    input wire [2:0] func3,
    input wire [31:0] di,
    output reg [31:0] do
);


    always @ * begin
        case (func3)
        3'b100  : do = {24'b0,di[7:0]};
        3'b000  : do = { {24{di[7]}}, di[7:0] };
        3'b101  : do = {16'b0,di[15:0]};
        3'b001  : do = { {16{di[15]} },di[15:0]};
        default : do = di;
        endcase
    end

endmodule