data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v
None: at end of input
1: b'%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:12: Cannot find include file: nettype.h\n`include "nettype.h" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169597129/io/uart/rtl,data/full_repos/permissive/169597129/nettype.h\n             data/full_repos/permissive/169597129/io/uart/rtl,data/full_repos/permissive/169597129/nettype.h.v\n             data/full_repos/permissive/169597129/io/uart/rtl,data/full_repos/permissive/169597129/nettype.h.sv\n             nettype.h\n             nettype.h.v\n             nettype.h.sv\n             obj_dir/nettype.h\n             obj_dir/nettype.h.v\n             obj_dir/nettype.h.sv\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:13: Cannot find include file: stddef.h\n`include "stddef.h" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:14: Cannot find include file: global_config.h\n`include "global_config.h" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:17: Cannot find include file: uart.h\n`include "uart.h" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:28: Define or directive not defined: \'`UartAddrBus\'\n input  wire [`UartAddrBus] addr,   \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input  wire [`UartAddrBus] addr,   \n                          ^\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:29: Define or directive not defined: \'`WordDataBus\'\n input  wire [`WordDataBus] wr_data,   \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:30: Define or directive not defined: \'`WordDataBus\'\n output reg [`WordDataBus] rd_data,   \n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg       irq_rx,   \n ^~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg       irq_tx,   \n ^~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:37: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input  wire       rx_busy,   \n ^~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:38: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire       rx_end,   \n ^~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:39: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire [`ByteDataBus] rx_data,   \n ^~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:39: Define or directive not defined: \'`ByteDataBus\'\n input  wire [`ByteDataBus] rx_data,   \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:42: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire       tx_end,   \n ^~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:43: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg       tx_start,  \n ^~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:44: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [`ByteDataBus] tx_data   \n ^~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:44: Define or directive not defined: \'`ByteDataBus\'\n output reg [`ByteDataBus] tx_data   \n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:49: Define or directive not defined: \'`ByteDataBus\'\n reg [`ByteDataBus]     rx_buf;   \n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`ByteDataBus]     rx_buf;   \n                  ^\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:52: Define or directive not defined: \'`RESET_EDGE\'\n always @(posedge clk or `RESET_EDGE reset) begin\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:53: Define or directive not defined: \'`RESET_ENABLE\'\n  if (reset == `RESET_ENABLE) begin\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:55: Define or directive not defined: \'`WORD_DATA_W\'\n   rd_data  <= #1 `WORD_DATA_W\'h0;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:56: Define or directive not defined: \'`DISABLE_\'\n   rdy_  <= #1 `DISABLE_;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:57: Define or directive not defined: \'`DISABLE\'\n   irq_rx  <= #1 `DISABLE;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:58: Define or directive not defined: \'`DISABLE\'\n   irq_tx  <= #1 `DISABLE;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:59: Define or directive not defined: \'`BYTE_DATA_W\'\n   rx_buf  <= #1 `BYTE_DATA_W\'h0;\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:60: Define or directive not defined: \'`DISABLE\'\n   tx_start <= #1 `DISABLE;\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:61: Define or directive not defined: \'`BYTE_DATA_W\'\n   tx_data  <= #1 `BYTE_DATA_W\'h0;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:64: Define or directive not defined: \'`ENABLE_\'\n   if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin\n               ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:64: Define or directive not defined: \'`ENABLE_\'\n   if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:65: Define or directive not defined: \'`ENABLE_\'\n    rdy_  <= #1 `ENABLE_;\n                ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:67: Define or directive not defined: \'`DISABLE_\'\n    rdy_  <= #1 `DISABLE_;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:70: Define or directive not defined: \'`ENABLE_\'\n   if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `READ)) begin\n               ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:70: Define or directive not defined: \'`ENABLE_\'\n   if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `READ)) begin\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:70: Define or directive not defined: \'`READ\'\n   if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `READ)) begin\n                                                        ^~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:72: Define or directive not defined: \'`UART_ADDR_STATUS\'\n     `UART_ADDR_STATUS  : begin  \n     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:73: Define or directive not defined: \'`WORD_DATA_W\'\n      rd_data  <= #1 {{`WORD_DATA_W-4{1\'b0}}, \n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:76: Define or directive not defined: \'`UART_ADDR_DATA\'\n     `UART_ADDR_DATA   : begin  \n     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:77: Define or directive not defined: \'`BYTE_DATA_W\'\n      rd_data  <= #1 {{`BYTE_DATA_W*2{1\'b0}}, rx_buf};\n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:81: Define or directive not defined: \'`WORD_DATA_W\'\n    rd_data  <= #1 `WORD_DATA_W\'h0;\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:85: Define or directive not defined: \'`ENABLE\'\n   if (tx_end == `ENABLE) begin\n                 ^~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:86: Define or directive not defined: \'`ENABLE\'\n    irq_tx<= #1 `ENABLE;\n                ^~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:87: Define or directive not defined: \'`ENABLE_\'\n   end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && \n                        ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:87: Define or directive not defined: \'`ENABLE_\'\n   end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && \n                                             ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:88: Define or directive not defined: \'`WRITE\'\n       (rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin\n              ^~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:88: Define or directive not defined: \'`UART_ADDR_STATUS\'\n       (rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin\n                                  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:89: Define or directive not defined: \'`UartCtrlIrqTx\'\n    irq_tx<= #1 wr_data[`UartCtrlIrqTx];\n                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:92: Define or directive not defined: \'`ENABLE\'\n   if (rx_end == `ENABLE) begin\n                 ^~~~~~~\n%Error: data/full_repos/permissive/169597129/io/uart/rtl/uart_ctrl.v:93: Define or directive not defined: \'`ENABLE\'\n    irq_rx<= #1 `ENABLE;\n                ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module uart_ctrl (

	input  wire				   clk,
	input  wire				   reset,

	input  wire				   cs_,
	input  wire				   as_,
	input  wire				   rw,
	input  wire [`UartAddrBus] addr,
	input  wire [`WordDataBus] wr_data,
	output reg	[`WordDataBus] rd_data,
	output reg				   rdy_,

	output reg				   irq_rx,
	output reg				   irq_tx,


	input  wire				   rx_busy,
	input  wire				   rx_end,
	input  wire [`ByteDataBus] rx_data,

	input  wire				   tx_busy,
	input  wire				   tx_end,
	output reg				   tx_start,
	output reg	[`ByteDataBus] tx_data
);



	reg [`ByteDataBus]		   rx_buf;


	always @(posedge clk or `RESET_EDGE reset) begin
		if (reset == `RESET_ENABLE) begin

			rd_data	 <= #1 `WORD_DATA_W'h0;
			rdy_	 <= #1 `DISABLE_;
			irq_rx	 <= #1 `DISABLE;
			irq_tx	 <= #1 `DISABLE;
			rx_buf	 <= #1 `BYTE_DATA_W'h0;
			tx_start <= #1 `DISABLE;
			tx_data	 <= #1 `BYTE_DATA_W'h0;
	   end else begin

			if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin
				rdy_	 <= #1 `ENABLE_;
			end else begin
				rdy_	 <= #1 `DISABLE_;
			end

			if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `READ)) begin
				case (addr)
					`UART_ADDR_STATUS	 : begin
						rd_data	 <= #1 {{`WORD_DATA_W-4{1'b0}}, 
										tx_busy, rx_busy, irq_tx, irq_rx};
					end
					`UART_ADDR_DATA		 : begin
						rd_data	 <= #1 {{`BYTE_DATA_W*2{1'b0}}, rx_buf};
					end
				endcase
			end else begin
				rd_data	 <= #1 `WORD_DATA_W'h0;
			end


			if (tx_end == `ENABLE) begin
				irq_tx<= #1 `ENABLE;
			end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && 
						 (rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin
				irq_tx<= #1 wr_data[`UartCtrlIrqTx];
			end

			if (rx_end == `ENABLE) begin
				irq_rx<= #1 `ENABLE;
			end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && 
						 (rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin
				irq_rx<= #1 wr_data[`UartCtrlIrqRx];
			end

			if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && 
				(rw == `WRITE) && (addr == `UART_ADDR_DATA)) begin
				tx_start <= #1 `ENABLE;
				tx_data	 <= #1 wr_data[`BYTE_MSB:`LSB];
			end else begin
				tx_start <= #1 `DISABLE;
				tx_data	 <= #1 `BYTE_DATA_W'h0;
			end

			if (rx_end == `ENABLE) begin
				rx_buf	 <= #1 rx_data;
			end
		end
	end

endmodule
module uart_ctrl (

	input  wire				   clk,
	input  wire				   reset,

	input  wire				   cs_,
	input  wire				   as_,
	input  wire				   rw,
	input  wire [`UartAddrBus] addr,
	input  wire [`WordDataBus] wr_data,
	output reg	[`WordDataBus] rd_data,
	output reg				   rdy_,

	output reg				   irq_rx,
	output reg				   irq_tx,


	input  wire				   rx_busy,
	input  wire				   rx_end,
	input  wire [`ByteDataBus] rx_data,

	input  wire				   tx_busy,
	input  wire				   tx_end,
	output reg				   tx_start,
	output reg	[`ByteDataBus] tx_data
);




	reg [`ByteDataBus]		   rx_buf;


	always @(posedge clk or `RESET_EDGE reset) begin
		if (reset == `RESET_ENABLE) begin

			rd_data	 <= #1 `WORD_DATA_W'h0;
			rdy_	 <= #1 `DISABLE_;
			irq_rx	 <= #1 `DISABLE;
			irq_tx	 <= #1 `DISABLE;
			rx_buf	 <= #1 `BYTE_DATA_W'h0;
			tx_start <= #1 `DISABLE;
			tx_data	 <= #1 `BYTE_DATA_W'h0;
	   end else begin

			if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin
				rdy_	 <= #1 `ENABLE_;
			end else begin
				rdy_	 <= #1 `DISABLE_;
			end

			if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `READ)) begin
				case (addr)
					`UART_ADDR_STATUS	 : begin
						rd_data	 <= #1 {{`WORD_DATA_W-4{1'b0}}, 
										tx_busy, rx_busy, irq_tx, irq_rx};
					end
					`UART_ADDR_DATA		 : begin
						rd_data	 <= #1 {{`BYTE_DATA_W*2{1'b0}}, rx_buf};
					end
				endcase
			end else begin
				rd_data	 <= #1 `WORD_DATA_W'h0;
			end


			if (tx_end == `ENABLE) begin
				irq_tx<= #1 `ENABLE;
			end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && 
						 (rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin
				irq_tx<= #1 wr_data[`UartCtrlIrqTx];
			end

			if (rx_end == `ENABLE) begin
				irq_rx<= #1 `ENABLE;
			end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && 
						 (rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin
				irq_rx<= #1 wr_data[`UartCtrlIrqRx];
			end

			if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && 
				(rw == `WRITE) && (addr == `UART_ADDR_DATA)) begin
				tx_start <= #1 `ENABLE;
				tx_data	 <= #1 wr_data[`BYTE_MSB:`LSB];
			end else begin
				tx_start <= #1 `DISABLE;
				tx_data	 <= #1 `BYTE_DATA_W'h0;
			end

			if (rx_end == `ENABLE) begin
				rx_buf	 <= #1 rx_data;
			end
		end
	end

endmodule