data/full_repos/permissive/152142712/v1/framegen.v
'utf-8' codec can't decode byte 0xfa in position 940: invalid start byte
1: b'%Warning-MULTITOP: data/full_repos/permissive/152142712/v1/framegen.v:80: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                        : ... Top module \'framegen\'\nmodule framegen (\n       ^~~~~~~~\n                                                                        : ... Top module \'framebuffer\'\nmodule framebuffer (\n       ^~~~~~~~~~~\n                                                                        : ... Top module \'audiogen\'\nmodule audiogen (\n       ^~~~~~~~\n%Warning-UNSIGNED: data/full_repos/permissive/152142712/v1/framegen.v:47: Comparison is constant due to unsigned arithmetic\n                                                                        : ... In instance framegen\n      if (hc >= 9\'d0 && hc < 9\'d384 && vc >= 9\'d0 && vc < 9\'d288) begin   \n             ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152142712/v1/framegen.v:47: Comparison is constant due to unsigned arithmetic\n                                                                        : ... In instance framegen\n      if (hc >= 9\'d0 && hc < 9\'d384 && vc >= 9\'d0 && vc < 9\'d288) begin   \n                                          ^~\n%Error: Exiting due to 3 warning(s)\n'
module audiogen (
  input wire clk,
  output reg audio
  );
  
  reg [11:0] cnt = 12'h000;
  initial audio = 1'b0;
  
  always @(posedge clk) begin
    if (cnt == 12'd3750) begin
      cnt <= 12'h000;
      audio <= ~audio;
    end
    else
      cnt <= cnt + 12'd1;
  end
endmodule
module audiogen (
  input wire clk,
  output reg audio
  );

  
  reg [11:0] cnt = 12'h000;
  initial audio = 1'b0;
  
  always @(posedge clk) begin
    if (cnt == 12'd3750) begin
      cnt <= 12'h000;
      audio <= ~audio;
    end
    else
      cnt <= cnt + 12'd1;
  end
endmodule