data/full_repos/permissive/143278/ivltests/idiv2.v
Syntax Error
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/idiv2.v:30: Operator DIV expects 32 bits on the RHS, but RHS\'s VARREF \'b\' generates 16 bits.\n                                                                     : ... In instance test\n  out = a-(a/b)*b;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/idiv2.v:37: Operator TASKREF \'mod\' expects 16 bits on the Function Argument, but Function Argument\'s VARREF \'nl\' generates 32 bits.\n                                                                     : ... In instance test\n      mod(c, nl, result);\n      ^~~\n%Error: Exiting due to 2 warning(s)\n'
module test;
   task mod;
      input  [31:0] a;
      input  [15:0] b;
      output [31:0] out;
      begin
	 out = a-(a/b)*b;
      end
   endtask

   reg [31:0] result,c, nl;
   initial begin
      c = 13; nl = 3;
      mod(c, nl, result);
      $display("13 %% 3 = %d", result);
      if (result !== 32'h00_00_00_01) begin
	 $display("FAILED -- result is %b", result);
	 $finish;
      end

      $display("PASSED");

  end
endmodule
module test;

   task mod;
      input  [31:0] a;
      input  [15:0] b;
      output [31:0] out;
      begin
	 out = a-(a/b)*b;
      end
   endtask

   reg [31:0] result,c, nl;
   initial begin
      c = 13; nl = 3;
      mod(c, nl, result);
      $display("13 %% 3 = %d", result);
      if (result !== 32'h00_00_00_01) begin
	 $display("FAILED -- result is %b", result);
	 $finish;
      end

      $display("PASSED");

  end
endmodule