data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:16: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg,data/full_repos/permissive/214858095/test_exec.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg,data/full_repos/permissive/214858095/test_exec.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg,data/full_repos/permissive/214858095/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:25: Cannot find include file: rfnoc_block_moving_avg_regs.vh\n  `include "rfnoc_block_moving_avg_regs.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:18: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgTestExec::*;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:80: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);\n                                               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:83: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t  chdr_word_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:84: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::item_t       item_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:85: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::item_queue_t item_queue_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:198: syntax error, unexpected IDENTIFIER, expecting \')\'\n    item_t sample = \'X\n           ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:200: syntax error, unexpected \'=\', expecting \',\' or \';\'\n    MovingAverage sum_i = new(), sum_q = new();\n                        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:201: syntax error, unexpected \'=\', expecting \',\' or \';\'\n    mailbox #(item_queue_t) packets = new();\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:209: syntax error, unexpected \'(\', expecting IDENTIFIER\n    sum_i.set_sum_length(sum_length);\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:210: syntax error, unexpected \'(\', expecting IDENTIFIER\n    sum_q.set_sum_length(sum_length);\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:211: syntax error, unexpected \'(\', expecting IDENTIFIER\n    sum_i.set_divisor(divisor);\n                      ^~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:212: syntax error, unexpected \'(\', expecting IDENTIFIER\n    sum_q.set_divisor(divisor);\n                      ^~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:215: syntax error, unexpected int, expecting IDENTIFIER or genvar\n    for (int packet_count = 0; packet_count < num_packets; packet_count++) begin\n         ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:219: syntax error, unexpected int, expecting IDENTIFIER or genvar\n      for (int sample_count = 0; sample_count < packet_len; sample_count++) begin\n           ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:223: Unsupported or unknown PLI call: $urandom\n          payload.push_back($urandom());\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:227: syntax error, unexpected \'(\', expecting IDENTIFIER\n      blk_ctrl.send_items(port, payload);\n                          ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:233: syntax error, unexpected \'(\', expecting IDENTIFIER\n      packets.get(sent);\n                  ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:236: syntax error, unexpected \'(\', expecting IDENTIFIER\n      blk_ctrl.recv_items(port, received);\n                          ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:239: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:252: syntax error, unexpected \'(\', expecting IDENTIFIER\n        sum_i.add_value(signed\'(sent_val[31:16]));\n                        ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:253: syntax error, unexpected \'(\', expecting IDENTIFIER\n        sum_q.add_value(signed\'(sent_val[15: 0]));\n                        ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:259: syntax error, unexpected $display\n          $display("Received %09d,%09d", signed\'(received_val[31:16]), signed\'(received_val[15:0]));\n          ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:261: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:277: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Test registers", 1ms);\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:282: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value === {REG_SUM_LENGTH_LEN{1\'bX}},\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:286: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value === {REG_DIVISOR_LEN{1\'bX}},\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:292: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value == 0, "REG_SUM_LENGTH didn\'t readback correctly");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:296: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value == 0, "REG_DIVISOR didn\'t readback correctly");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:301: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value == {REG_SUM_LENGTH_LEN{1\'b1}},\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:306: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value == {REG_DIVISOR_LEN{1\'b1}},\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:309: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:324: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Test random", 10ms);\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:327: syntax error, unexpected int, expecting IDENTIFIER or genvar\n    for (int iteration = 0; iteration < num_iterations; iteration++) begin\n         ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:335: syntax error, unexpected \'=\', expecting IDENTIFIER\n      sum_length  = $urandom_range(1, 2**REG_SUM_LENGTH_LEN-1);\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:335: Unsupported or unknown PLI call: $urandom_range\n      sum_length  = $urandom_range(1, 2**REG_SUM_LENGTH_LEN-1);\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:337: Unsupported or unknown PLI call: $urandom_range\n      divisor     = divisor_t\'($urandom_range(1, 20*sum_length));\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:338: Unsupported or unknown PLI call: $urandom_range\n      if ($urandom_range(0,1)) divisor = -divisor;\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:338: syntax error, unexpected \'=\', expecting IDENTIFIER\n      if ($urandom_range(0,1)) divisor = -divisor;\n                                       ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:339: Unsupported or unknown PLI call: $urandom_range\n      packet_len  = $urandom_range(1, SPP);\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:340: Unsupported or unknown PLI call: $urandom_range\n      num_packets = $urandom_range(3, 8);\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:352: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test($sformatf("Test basic, port %0d", port), 100us);\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:370: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:379: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Test max values", 1ms);\n                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:406: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:412: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test("Test back pressure", 1ms);\n                    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:413: syntax error, unexpected \'(\', expecting IDENTIFIER\n    blk_ctrl.set_slave_stall_prob(port, 90);\n                                  ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:415: syntax error, unexpected \'(\', expecting IDENTIFIER\n    blk_ctrl.set_slave_stall_prob(port, STALL_PROB);\n                                  ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg_tb.sv:416: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.end_test();\n                  ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module rfnoc_block_moving_avg_tb;

  `include "test_exec.svh"

  import PkgTestExec::*;
  import PkgChdrUtils::*;
  import PkgRfnocBlockCtrlBfm::*;
  import PkgRfnocItemUtils::*;

  import PkgMovingAverage::MovingAverage;

  `include "rfnoc_block_moving_avg_regs.vh"






  localparam [31:0] NOC_ID          = 32'hAAD20000;
  localparam [ 9:0] THIS_PORTID     = 10'h123;
  localparam int    CHDR_W          = 64;
  localparam int    MTU             = 10;
  localparam int    NUM_PORTS       = 2;
  localparam int    NUM_PORTS_I     = NUM_PORTS;
  localparam int    NUM_PORTS_O     = NUM_PORTS;
  localparam int    ITEM_W          = 32;
  localparam int    SPP             = 64;
  localparam int    PKT_SIZE_BYTES  = SPP * (ITEM_W/8);
  localparam int    STALL_PROB      = 25;
  localparam real   CHDR_CLK_PER    = 5.0;
  localparam real   CTRL_CLK_PER    = 8.0;
  localparam real   CE_CLK_PER      = 4.0;


  typedef bit signed [REG_DIVISOR_LEN-1:0] divisor_t;






  bit rfnoc_chdr_clk;
  bit rfnoc_ctrl_clk;
  bit ce_clk;

  sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
  sim_clock_gen #(CTRL_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
  sim_clock_gen #(CE_CLK_PER) ce_clk_gen (.clk(ce_clk), .rst());







  RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_ctrl_clk);


  AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, 1'b0);
  AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, 1'b0);


  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS_I] (rfnoc_chdr_clk, 1'b0);
  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS_O] (rfnoc_chdr_clk, 1'b0);


  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);


  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t  chdr_word_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_t       item_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_queue_t item_queue_t;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_bfm_input_connections
    initial begin
      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
    end
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_bfm_output_connections
    initial begin
      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
    end
  end







  logic [CHDR_W*NUM_PORTS_I-1:0] s_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tready;


  logic [CHDR_W*NUM_PORTS_O-1:0] m_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tready;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_dut_input_connections

    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_dut_output_connections

    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
  end

  rfnoc_block_moving_avg #(
    .THIS_PORTID         (THIS_PORTID),
    .CHDR_W              (CHDR_W),
    .MTU                 (MTU),
    .NUM_PORTS           (NUM_PORTS)
  ) dut (
    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
    .ce_clk              (ce_clk),
    .rfnoc_core_config   (backend.cfg),
    .rfnoc_core_status   (backend.sts),
    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
    .s_rfnoc_ctrl_tdata  (m_ctrl.tdata),
    .s_rfnoc_ctrl_tlast  (m_ctrl.tlast),
    .s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
    .s_rfnoc_ctrl_tready (m_ctrl.tready),
    .m_rfnoc_ctrl_tdata  (s_ctrl.tdata),
    .m_rfnoc_ctrl_tlast  (s_ctrl.tlast),
    .m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
    .m_rfnoc_ctrl_tready (s_ctrl.tready)
  );







  task automatic write_reg(int port, bit [19:0] addr, bit [31:0] value);
    blk_ctrl.reg_write(port * (2**MOVING_AVG_ADDR_W) + addr, value);
  endtask : write_reg


  task automatic read_reg(int port, bit [19:0] addr, output logic [31:0] value);
    blk_ctrl.reg_read(port * (2**MOVING_AVG_ADDR_W) + addr, value);
  endtask : read_reg















  task automatic test_moving_avg(
    int port,
    int sum_length,
    int divisor,
    int packet_len,
    int num_packets,
    item_t sample = 'X
  );
    MovingAverage sum_i = new(), sum_q = new();
    mailbox #(item_queue_t) packets = new();

    $display("Testing: sum_length=%04d, divisor=%08d, packet_len=%04d, num_packets=%04d",
      sum_length, divisor, packet_len, num_packets);

    write_reg(port, REG_SUM_LENGTH, sum_length);
    write_reg(port, REG_DIVISOR, divisor);

    sum_i.set_sum_length(sum_length);
    sum_q.set_sum_length(sum_length);
    sum_i.set_divisor(divisor);
    sum_q.set_divisor(divisor);


    for (int packet_count = 0; packet_count < num_packets; packet_count++) begin
      item_t payload[$];

      payload = {};
      for (int sample_count = 0; sample_count < packet_len; sample_count++) begin
        if (sample !== 'X) begin
          payload.push_back(sample);
        end else begin
          payload.push_back($urandom());
        end
      end
      packets.put(payload);
      blk_ctrl.send_items(port, payload);
    end


    for (int packet_count = 0; packet_count < num_packets; packet_count++) begin
      item_t sent[$], received[$];
      packets.get(sent);


      blk_ctrl.recv_items(port, received);


      `ASSERT_ERROR(
        sent.size() == received.size(),
        $sformatf("For packet %0d, received length was incorrect", packet_count)
      );


      foreach(received[i]) begin
        item_t expected_val, sent_val, received_val;




        sent_val = sent[i];
        sum_i.add_value(signed'(sent_val[31:16]));
        sum_q.add_value(signed'(sent_val[15: 0]));
        expected_val[31:16] = sum_i.get_average();
        expected_val[15: 0] = sum_q.get_average();

        received_val = received[i];
        if(received_val != expected_val) begin
          $display("Received %09d,%09d", signed'(received_val[31:16]), signed'(received_val[15:0]));
          $display("Expected %09d,%09d", signed'(expected_val[31:16]), signed'(expected_val[15:0]));
          `ASSERT_ERROR(
            0,
            $sformatf("Unexpected result for packet %0d, sample %0d.", packet_count, i)
          );
        end
      end
    end

  endtask : test_moving_avg




  task automatic test_registers(int port);
    logic [31:0] value;

    test.start_test("Test registers", 1ms);



    read_reg(port, REG_SUM_LENGTH, value);
    `ASSERT_ERROR(value === {REG_SUM_LENGTH_LEN{1'bX}},
      "REG_SUM_LENGTH initial value didn't match expected value");

    read_reg(port, REG_DIVISOR, value);
    `ASSERT_ERROR(value === {REG_DIVISOR_LEN{1'bX}},
      "REG_DIVISOR_LEN initial value didn't match expected value");


    write_reg(port, REG_SUM_LENGTH, 0);
    read_reg(port, REG_SUM_LENGTH, value);
    `ASSERT_ERROR(value == 0, "REG_SUM_LENGTH didn't readback correctly");

    write_reg(port, REG_DIVISOR, 0);
    read_reg(port, REG_DIVISOR, value);
    `ASSERT_ERROR(value == 0, "REG_DIVISOR didn't readback correctly");


    write_reg(port, REG_SUM_LENGTH, '1);
    read_reg(port, REG_SUM_LENGTH, value);
    `ASSERT_ERROR(value == {REG_SUM_LENGTH_LEN{1'b1}},
      "REG_SUM_LENGTH didn't readback correctly");

    write_reg(port, REG_DIVISOR, '1);
    read_reg(port, REG_DIVISOR, value);
    `ASSERT_ERROR(value == {REG_DIVISOR_LEN{1'b1}},
      "REG_DIVISOR didn't readback correctly");

    test.end_test();
  endtask : test_registers








  task automatic test_random_config(
    int port,
    int num_iterations  = 100,
    int max_packet_len  = SPP
  );
    test.start_test("Test random", 10ms);


    for (int iteration = 0; iteration < num_iterations; iteration++) begin

      int sum_length;
      int divisor;
      int packet_len;
      int num_packets;


      sum_length  = $urandom_range(1, 2**REG_SUM_LENGTH_LEN-1);

      divisor     = divisor_t'($urandom_range(1, 20*sum_length));
      if ($urandom_range(0,1)) divisor = -divisor;
      packet_len  = $urandom_range(1, SPP);
      num_packets = $urandom_range(3, 8);


      test_moving_avg(port, sum_length, divisor, packet_len, num_packets);
    end

    test.end_test();
  endtask : test_random_config



  task automatic test_basic(int port);
    test.start_test($sformatf("Test basic, port %0d", port), 100us);


    test_moving_avg(.port(port), .sum_length(1), .divisor(1),
      .packet_len(SPP), .num_packets(3));

    test_moving_avg(.port(port), .sum_length(1), .divisor(-1),
      .packet_len(SPP), .num_packets(3));

    test_moving_avg(.port(port), .sum_length(1), .divisor(2),
      .packet_len(SPP), .num_packets(3));

    test_moving_avg(.port(port), .sum_length(2), .divisor(1),
      .packet_len(SPP), .num_packets(3));

    test_moving_avg(.port(port), .sum_length(2), .divisor(2),
      .packet_len(SPP), .num_packets(3));

    test.end_test();
  endtask : test_basic




  task automatic test_max_values(int port);
    int max_length, max_divisor, min_divisor;

    test.start_test("Test max values", 1ms);

    max_length  =  2**REG_SUM_LENGTH_LEN-1;
    max_divisor =  2**(REG_DIVISOR_LEN-1)-1;
    min_divisor = -2**(REG_DIVISOR_LEN-1);





    test_moving_avg(.port(port), .sum_length(max_length), .divisor(max_length),
      .packet_len(SPP), .num_packets(3*max_length/SPP));

    test_moving_avg(.port(port), .sum_length(max_length), .divisor(max_divisor),
      .packet_len(SPP), .num_packets(3*max_length/SPP));

    test_moving_avg(.port(port), .sum_length(max_length), .divisor(min_divisor),
      .packet_len(SPP), .num_packets(3*max_length/SPP));



    test_moving_avg(.port(port), .sum_length(max_length), .divisor(max_length),
      .packet_len(SPP), .num_packets(3*max_length/SPP), .sample(32'h7FFF_7FFF));

    test_moving_avg(.port(port), .sum_length(max_length), .divisor(max_length),
      .packet_len(SPP), .num_packets(3*max_length/SPP), .sample(32'h8000_8000));

    test.end_test();
  endtask : test_max_values



  task automatic test_back_pressure(int port);
    test.start_test("Test back pressure", 1ms);
    blk_ctrl.set_slave_stall_prob(port, 90);
    test_moving_avg(port, 16, 16, SPP, 20);
    blk_ctrl.set_slave_stall_prob(port, STALL_PROB);
    test.end_test();
  endtask : test_back_pressure




  task automatic test_underflow(int port);
    test.start_test("Test underflow", 1ms);
    blk_ctrl.set_master_stall_prob(port, 90);
    test_moving_avg(port, 16, 16, SPP, 20);
    blk_ctrl.set_master_stall_prob(port, STALL_PROB);
    test.end_test();
  endtask : test_underflow






  initial begin : tb_main
    int port;


    test.start_tb("rfnoc_block_moving_avg_tb");


    blk_ctrl.run();





    test.start_test("Flush block then reset it", 10us);
    blk_ctrl.flush_and_reset();
    test.end_test();





    test.start_test("Verify Block Info", 2us);
    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");
    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
    test.end_test();






    for (port = 0; port < NUM_PORTS; port++) begin
      test_registers(port);
      test_basic(port);
    end


    port = 1;
    test_max_values(port);
    test_back_pressure(port);
    test_underflow(port);
    test_random_config(port, 100);






    test.end_tb();
  end : tb_main

endmodule
module rfnoc_block_moving_avg_tb;


  `include "test_exec.svh"

  import PkgTestExec::*;
  import PkgChdrUtils::*;
  import PkgRfnocBlockCtrlBfm::*;
  import PkgRfnocItemUtils::*;

  import PkgMovingAverage::MovingAverage;

  `include "rfnoc_block_moving_avg_regs.vh"






  localparam [31:0] NOC_ID          = 32'hAAD20000;
  localparam [ 9:0] THIS_PORTID     = 10'h123;
  localparam int    CHDR_W          = 64;
  localparam int    MTU             = 10;
  localparam int    NUM_PORTS       = 2;
  localparam int    NUM_PORTS_I     = NUM_PORTS;
  localparam int    NUM_PORTS_O     = NUM_PORTS;
  localparam int    ITEM_W          = 32;
  localparam int    SPP             = 64;
  localparam int    PKT_SIZE_BYTES  = SPP * (ITEM_W/8);
  localparam int    STALL_PROB      = 25;
  localparam real   CHDR_CLK_PER    = 5.0;
  localparam real   CTRL_CLK_PER    = 8.0;
  localparam real   CE_CLK_PER      = 4.0;


  typedef bit signed [REG_DIVISOR_LEN-1:0] divisor_t;






  bit rfnoc_chdr_clk;
  bit rfnoc_ctrl_clk;
  bit ce_clk;

  sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
  sim_clock_gen #(CTRL_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
  sim_clock_gen #(CE_CLK_PER) ce_clk_gen (.clk(ce_clk), .rst());







  RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_ctrl_clk);


  AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, 1'b0);
  AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, 1'b0);


  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS_I] (rfnoc_chdr_clk, 1'b0);
  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS_O] (rfnoc_chdr_clk, 1'b0);


  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);


  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t  chdr_word_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_t       item_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_queue_t item_queue_t;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_bfm_input_connections
    initial begin
      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
    end
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_bfm_output_connections
    initial begin
      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
    end
  end







  logic [CHDR_W*NUM_PORTS_I-1:0] s_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tready;


  logic [CHDR_W*NUM_PORTS_O-1:0] m_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tready;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_dut_input_connections

    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_dut_output_connections

    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
  end

  rfnoc_block_moving_avg #(
    .THIS_PORTID         (THIS_PORTID),
    .CHDR_W              (CHDR_W),
    .MTU                 (MTU),
    .NUM_PORTS           (NUM_PORTS)
  ) dut (
    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
    .ce_clk              (ce_clk),
    .rfnoc_core_config   (backend.cfg),
    .rfnoc_core_status   (backend.sts),
    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
    .s_rfnoc_ctrl_tdata  (m_ctrl.tdata),
    .s_rfnoc_ctrl_tlast  (m_ctrl.tlast),
    .s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
    .s_rfnoc_ctrl_tready (m_ctrl.tready),
    .m_rfnoc_ctrl_tdata  (s_ctrl.tdata),
    .m_rfnoc_ctrl_tlast  (s_ctrl.tlast),
    .m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
    .m_rfnoc_ctrl_tready (s_ctrl.tready)
  );







  task automatic write_reg(int port, bit [19:0] addr, bit [31:0] value);
    blk_ctrl.reg_write(port * (2**MOVING_AVG_ADDR_W) + addr, value);
  endtask : write_reg


  task automatic read_reg(int port, bit [19:0] addr, output logic [31:0] value);
    blk_ctrl.reg_read(port * (2**MOVING_AVG_ADDR_W) + addr, value);
  endtask : read_reg















  task automatic test_moving_avg(
    int port,
    int sum_length,
    int divisor,
    int packet_len,
    int num_packets,
    item_t sample = 'X
  );
    MovingAverage sum_i = new(), sum_q = new();
    mailbox #(item_queue_t) packets = new();

    $display("Testing: sum_length=%04d, divisor=%08d, packet_len=%04d, num_packets=%04d",
      sum_length, divisor, packet_len, num_packets);

    write_reg(port, REG_SUM_LENGTH, sum_length);
    write_reg(port, REG_DIVISOR, divisor);

    sum_i.set_sum_length(sum_length);
    sum_q.set_sum_length(sum_length);
    sum_i.set_divisor(divisor);
    sum_q.set_divisor(divisor);


    for (int packet_count = 0; packet_count < num_packets; packet_count++) begin
      item_t payload[$];

      payload = {};
      for (int sample_count = 0; sample_count < packet_len; sample_count++) begin
        if (sample !== 'X) begin
          payload.push_back(sample);
        end else begin
          payload.push_back($urandom());
        end
      end
      packets.put(payload);
      blk_ctrl.send_items(port, payload);
    end


    for (int packet_count = 0; packet_count < num_packets; packet_count++) begin
      item_t sent[$], received[$];
      packets.get(sent);


      blk_ctrl.recv_items(port, received);


      `ASSERT_ERROR(
        sent.size() == received.size(),
        $sformatf("For packet %0d, received length was incorrect", packet_count)
      );


      foreach(received[i]) begin
        item_t expected_val, sent_val, received_val;




        sent_val = sent[i];
        sum_i.add_value(signed'(sent_val[31:16]));
        sum_q.add_value(signed'(sent_val[15: 0]));
        expected_val[31:16] = sum_i.get_average();
        expected_val[15: 0] = sum_q.get_average();

        received_val = received[i];
        if(received_val != expected_val) begin
          $display("Received %09d,%09d", signed'(received_val[31:16]), signed'(received_val[15:0]));
          $display("Expected %09d,%09d", signed'(expected_val[31:16]), signed'(expected_val[15:0]));
          `ASSERT_ERROR(
            0,
            $sformatf("Unexpected result for packet %0d, sample %0d.", packet_count, i)
          );
        end
      end
    end

  endtask : test_moving_avg




  task automatic test_registers(int port);
    logic [31:0] value;

    test.start_test("Test registers", 1ms);



    read_reg(port, REG_SUM_LENGTH, value);
    `ASSERT_ERROR(value === {REG_SUM_LENGTH_LEN{1'bX}},
      "REG_SUM_LENGTH initial value didn't match expected value");

    read_reg(port, REG_DIVISOR, value);
    `ASSERT_ERROR(value === {REG_DIVISOR_LEN{1'bX}},
      "REG_DIVISOR_LEN initial value didn't match expected value");


    write_reg(port, REG_SUM_LENGTH, 0);
    read_reg(port, REG_SUM_LENGTH, value);
    `ASSERT_ERROR(value == 0, "REG_SUM_LENGTH didn't readback correctly");

    write_reg(port, REG_DIVISOR, 0);
    read_reg(port, REG_DIVISOR, value);
    `ASSERT_ERROR(value == 0, "REG_DIVISOR didn't readback correctly");


    write_reg(port, REG_SUM_LENGTH, '1);
    read_reg(port, REG_SUM_LENGTH, value);
    `ASSERT_ERROR(value == {REG_SUM_LENGTH_LEN{1'b1}},
      "REG_SUM_LENGTH didn't readback correctly");

    write_reg(port, REG_DIVISOR, '1);
    read_reg(port, REG_DIVISOR, value);
    `ASSERT_ERROR(value == {REG_DIVISOR_LEN{1'b1}},
      "REG_DIVISOR didn't readback correctly");

    test.end_test();
  endtask : test_registers








  task automatic test_random_config(
    int port,
    int num_iterations  = 100,
    int max_packet_len  = SPP
  );
    test.start_test("Test random", 10ms);


    for (int iteration = 0; iteration < num_iterations; iteration++) begin

      int sum_length;
      int divisor;
      int packet_len;
      int num_packets;


      sum_length  = $urandom_range(1, 2**REG_SUM_LENGTH_LEN-1);

      divisor     = divisor_t'($urandom_range(1, 20*sum_length));
      if ($urandom_range(0,1)) divisor = -divisor;
      packet_len  = $urandom_range(1, SPP);
      num_packets = $urandom_range(3, 8);


      test_moving_avg(port, sum_length, divisor, packet_len, num_packets);
    end

    test.end_test();
  endtask : test_random_config



  task automatic test_basic(int port);
    test.start_test($sformatf("Test basic, port %0d", port), 100us);


    test_moving_avg(.port(port), .sum_length(1), .divisor(1),
      .packet_len(SPP), .num_packets(3));

    test_moving_avg(.port(port), .sum_length(1), .divisor(-1),
      .packet_len(SPP), .num_packets(3));

    test_moving_avg(.port(port), .sum_length(1), .divisor(2),
      .packet_len(SPP), .num_packets(3));

    test_moving_avg(.port(port), .sum_length(2), .divisor(1),
      .packet_len(SPP), .num_packets(3));

    test_moving_avg(.port(port), .sum_length(2), .divisor(2),
      .packet_len(SPP), .num_packets(3));

    test.end_test();
  endtask : test_basic




  task automatic test_max_values(int port);
    int max_length, max_divisor, min_divisor;

    test.start_test("Test max values", 1ms);

    max_length  =  2**REG_SUM_LENGTH_LEN-1;
    max_divisor =  2**(REG_DIVISOR_LEN-1)-1;
    min_divisor = -2**(REG_DIVISOR_LEN-1);





    test_moving_avg(.port(port), .sum_length(max_length), .divisor(max_length),
      .packet_len(SPP), .num_packets(3*max_length/SPP));

    test_moving_avg(.port(port), .sum_length(max_length), .divisor(max_divisor),
      .packet_len(SPP), .num_packets(3*max_length/SPP));

    test_moving_avg(.port(port), .sum_length(max_length), .divisor(min_divisor),
      .packet_len(SPP), .num_packets(3*max_length/SPP));



    test_moving_avg(.port(port), .sum_length(max_length), .divisor(max_length),
      .packet_len(SPP), .num_packets(3*max_length/SPP), .sample(32'h7FFF_7FFF));

    test_moving_avg(.port(port), .sum_length(max_length), .divisor(max_length),
      .packet_len(SPP), .num_packets(3*max_length/SPP), .sample(32'h8000_8000));

    test.end_test();
  endtask : test_max_values



  task automatic test_back_pressure(int port);
    test.start_test("Test back pressure", 1ms);
    blk_ctrl.set_slave_stall_prob(port, 90);
    test_moving_avg(port, 16, 16, SPP, 20);
    blk_ctrl.set_slave_stall_prob(port, STALL_PROB);
    test.end_test();
  endtask : test_back_pressure




  task automatic test_underflow(int port);
    test.start_test("Test underflow", 1ms);
    blk_ctrl.set_master_stall_prob(port, 90);
    test_moving_avg(port, 16, 16, SPP, 20);
    blk_ctrl.set_master_stall_prob(port, STALL_PROB);
    test.end_test();
  endtask : test_underflow






  initial begin : tb_main
    int port;


    test.start_tb("rfnoc_block_moving_avg_tb");


    blk_ctrl.run();





    test.start_test("Flush block then reset it", 10us);
    blk_ctrl.flush_and_reset();
    test.end_test();





    test.start_test("Verify Block Info", 2us);
    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");
    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
    test.end_test();






    for (port = 0; port < NUM_PORTS; port++) begin
      test_registers(port);
      test_basic(port);
    end


    port = 1;
    test_max_values(port);
    test_back_pressure(port);
    test_underflow(port);
    test_random_config(port, 100);






    test.end_tb();
  end : tb_main

endmodule