data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:14: Cannot find include file: spio_hss_multiplexer_common.h\n`include "spio_hss_multiplexer_common.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h.v\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h.sv\n             spio_hss_multiplexer_common.h\n             spio_hss_multiplexer_common.h.v\n             spio_hss_multiplexer_common.h.sv\n             obj_dir/spio_hss_multiplexer_common.h\n             obj_dir/spio_hss_multiplexer_common.h.v\n             obj_dir/spio_hss_multiplexer_common.h.sv\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:26: Define or directive not defined: \'`IDLE_BITS\'\n                                        , output reg  [`IDLE_BITS - 1:0] REG_IDSI_OUT\n                                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:62: Define or directive not defined: \'`KCH_IDLE\'\n                     && aligned_rxdata_i[31:16] == `KCH_IDLE\n                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:63: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                     && aligned_rxcharisk_i == `IDLE_KBITS\n                     ^~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:63: Define or directive not defined: \'`IDLE_KBITS\'\n                     && aligned_rxcharisk_i == `IDLE_KBITS\n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:69: Define or directive not defined: \'`IDLE_BITS\'\n    REG_IDSI_OUT <= {`IDLE_BITS{1\'b1}};\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:72: Define or directive not defined: \'`IDLE_BITS\'\n      REG_IDSI_OUT <= aligned_rxdata_i[`IDLE_BITS-1:0];\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:189: Define or directive not defined: \'`KCH_CLKC\'\n                                  && aligned_rxdata_i    == {4{`KCH_CLKC}}\n                                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:189: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n                                  && aligned_rxdata_i    == {4{`KCH_CLKC}}\n                                                                        ^\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:220: Define or directive not defined: \'`KCH_COMMA\'\n                    && aligned_rxdata_i[31:24] == `KCH_COMMA\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:221: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                    && aligned_rxdata_i[23:16] == `KCH_HANDSHAKE\n                    ^~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:221: Define or directive not defined: \'`KCH_HANDSHAKE\'\n                    && aligned_rxdata_i[23:16] == `KCH_HANDSHAKE\n                                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:234: Define or directive not defined: \'`PROTOCOL_VERSION\'\n   VERSION_MISMATCH_OUT <= handshake_version_in_i != `PROTOCOL_VERSION;\n                                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:234: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   VERSION_MISMATCH_OUT <= handshake_version_in_i != `PROTOCOL_VERSION;\n                                                                      ^\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:256: Define or directive not defined: \'`PROTOCOL_VERSION\'\n                         || (is_handshake_i && (handshake_version_in_i != `PROTOCOL_VERSION))\n                                                                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_rx_control.v:256: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                         || (is_handshake_i && (handshake_version_in_i != `PROTOCOL_VERSION))\n                                                                                           ^\n%Error: Exiting due to 16 error(s)\n'
module spio_hss_multiplexer_rx_control #(

                                          parameter NUM_HANDSHAKES = 100

                                        , parameter NUM_HANDSHAKES_BITS = 7
                                        )
                                        ( input wire  CLK_IN
                                        , input wire  RESET_IN
                                        

                                        , output reg  [`IDLE_BITS - 1:0] REG_IDSI_OUT



                                        ,   output reg HANDSHAKE_COMPLETE_OUT


                                        ,   output wire HANDSHAKE_PHASE_OUT


                                        ,   output reg VERSION_MISMATCH_OUT
                                        


                                        ,   input wire [31:0] RXDATA_IN
                                        ,   input wire  [3:0] RXCHARISCOMMA_IN
                                        ,   input wire  [3:0] RXCHARISK_IN
                                        ,   input wire  [1:0] RXLOSSOFSYNC_IN
                                        


                                        ,   output reg [31:0] RXDATA_OUT
                                        ,   output reg  [3:0] RXCHARISK_OUT



                                        ,   output reg RXVLD_OUT
                                        );







wire is_idle_frame_i = is_word_aligned_i
                     && aligned_rxdata_i[31:16] == `KCH_IDLE
                     && aligned_rxcharisk_i == `IDLE_KBITS
                     ;


always @ (posedge CLK_IN or posedge RESET_IN)
  if (RESET_IN)
    REG_IDSI_OUT <= {`IDLE_BITS{1'b1}};
  else
    if (is_idle_frame_i)
      REG_IDSI_OUT <= aligned_rxdata_i[`IDLE_BITS-1:0];





wire is_byte_aligned_i = (los_state_i == 2'b00);

localparam NUM_CLKC_FOR_SYNC = 4;

reg   [1:0] los_state_i;
reg   [2:0] los_cnt_i;


always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
	  los_cnt_i = 0;
	else
	  case ({los_state_i, RXLOSSOFSYNC_IN})
	    4'b01_01: los_cnt_i = los_cnt_i + 1;
	    default:  los_cnt_i = 0;
	  endcase
  
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
	  los_state_i = 2'b10;
	else
	  casex ({los_state_i, RXLOSSOFSYNC_IN})
	    4'bxx_10,
	    4'bxx_11: los_state_i = 2'b10;

	    4'b10_01: los_state_i = 2'b01;

	    4'b01_01: if (los_cnt_i >= NUM_CLKC_FOR_SYNC)
	                los_state_i = 2'b00;
                      else
	                los_state_i = los_state_i;

	    4'bxx_00: los_state_i = 2'b00;

	    default:  los_state_i = los_state_i;
	  endcase










wire [31:0] this_rxdata_i    = RXDATA_IN;
wire  [3:0] this_rxcharisk_i = RXCHARISK_IN;
reg  [31:8] last_rxdata_i;
reg   [3:1] last_rxcharisk_i;

always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			last_rxdata_i    <= 32'b0;
			last_rxcharisk_i <=  4'b0;
		end
	else
		begin
			last_rxdata_i    <= RXDATA_IN[31:8];
			last_rxcharisk_i <= RXCHARISK_IN[3:1];
		end

wire [63:8] unaligned_rxdata_i    = {this_rxdata_i,    last_rxdata_i};
wire  [7:1] unaligned_rxcharisk_i = {this_rxcharisk_i, last_rxcharisk_i};

reg [31:0] aligned_rxdata_i;
reg  [3:0] aligned_rxcharisk_i;



reg [3:0] alignment_i;

always @ (*)
	case (alignment_i)
		4'b0001: aligned_rxdata_i = unaligned_rxdata_i[39:8];
		4'b0010: aligned_rxdata_i = unaligned_rxdata_i[47:16];
		4'b0100: aligned_rxdata_i = unaligned_rxdata_i[55:24];
		4'b1000: aligned_rxdata_i = unaligned_rxdata_i[63:32];
		default: aligned_rxdata_i = 32'bX;
	endcase

always @ (*)
	case (alignment_i)
		4'b0001: aligned_rxcharisk_i = unaligned_rxcharisk_i[4:1];
		4'b0010: aligned_rxcharisk_i = unaligned_rxcharisk_i[5:2];
		4'b0100: aligned_rxcharisk_i = unaligned_rxcharisk_i[6:3];
		4'b1000: aligned_rxcharisk_i = unaligned_rxcharisk_i[7:4];
		default: aligned_rxcharisk_i = 4'bXXXX;
	endcase



always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		alignment_i <= 4'b0000;
	else
		if (!is_byte_aligned_i)
			alignment_i <= 4'b0000;
		else if (RXCHARISCOMMA_IN != 4'b0000)
			alignment_i <= RXCHARISCOMMA_IN;

wire is_word_aligned_i = is_byte_aligned_i && alignment_i != 4'b0000;







wire is_clock_correction_sequence = is_word_aligned_i
                                  && aligned_rxdata_i    == {4{`KCH_CLKC}}
                                  && aligned_rxcharisk_i == 4'b1111
                                  ;



























wire is_handshake_i = is_word_aligned_i
                    && aligned_rxdata_i[31:24] == `KCH_COMMA
                    && aligned_rxdata_i[23:16] == `KCH_HANDSHAKE
                    && aligned_rxcharisk_i == 4'b1100
                    ;

wire       handshake_phase_in_i   = is_handshake_i ? aligned_rxdata_i[8]   : 1'bX;
wire [7:0] handshake_version_in_i = is_handshake_i ? aligned_rxdata_i[7:0] : 8'bX;


always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		VERSION_MISMATCH_OUT <= 0;
	else
		if (is_handshake_i)
			VERSION_MISMATCH_OUT <= handshake_version_in_i != `PROTOCOL_VERSION;
		else
			VERSION_MISMATCH_OUT <= 1'b0;




reg last_handshake_phase_in_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		last_handshake_phase_in_i <= 0;
	else
		if (is_handshake_i)
			last_handshake_phase_in_i <= handshake_phase_in_i;






wire restart_handshake_i = !is_word_aligned_i
                         || (is_handshake_i && (handshake_phase_in_i   <  last_handshake_phase_in_i))
                         || (is_handshake_i && (handshake_version_in_i != `PROTOCOL_VERSION))
                         ;





reg [NUM_HANDSHAKES_BITS-1:0] handshake_counter_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		handshake_counter_i <= 0;
	else
		if (is_handshake_i && !restart_handshake_i)
			begin
				if (handshake_counter_i < NUM_HANDSHAKES)
					handshake_counter_i <= handshake_counter_i + 1;
			end
		else if (!is_clock_correction_sequence)
			handshake_counter_i <= 0;



assign HANDSHAKE_PHASE_OUT = handshake_counter_i == NUM_HANDSHAKES;



always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		HANDSHAKE_COMPLETE_OUT <= 1'b0;
	else
		if (restart_handshake_i)
			HANDSHAKE_COMPLETE_OUT <= 1'b0;
		else if (HANDSHAKE_PHASE_OUT == 1'b1 && handshake_phase_in_i == 1'b1)
			HANDSHAKE_COMPLETE_OUT <= 1'b1;










always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			RXDATA_OUT    <= 32'bX;
			RXCHARISK_OUT <= 4'bX;
			RXVLD_OUT     <= 1'b0;
		end
	else
		if (is_word_aligned_i && HANDSHAKE_COMPLETE_OUT && !is_clock_correction_sequence 
                     && !is_handshake_i && !is_idle_frame_i
                   )
			begin
				RXDATA_OUT    <= aligned_rxdata_i;
				RXCHARISK_OUT <= aligned_rxcharisk_i;
				RXVLD_OUT     <= 1'b1;
			end
		else
			begin
				RXDATA_OUT    <= 32'bX;
				RXCHARISK_OUT <= 4'bX;
				RXVLD_OUT     <= 1'b0;
			end


endmodule
module spio_hss_multiplexer_rx_control #(

                                          parameter NUM_HANDSHAKES = 100

                                        , parameter NUM_HANDSHAKES_BITS = 7
                                        )
                                        ( input wire  CLK_IN
                                        , input wire  RESET_IN
                                        

                                        , output reg  [`IDLE_BITS - 1:0] REG_IDSI_OUT



                                        ,   output reg HANDSHAKE_COMPLETE_OUT


                                        ,   output wire HANDSHAKE_PHASE_OUT


                                        ,   output reg VERSION_MISMATCH_OUT
                                        


                                        ,   input wire [31:0] RXDATA_IN
                                        ,   input wire  [3:0] RXCHARISCOMMA_IN
                                        ,   input wire  [3:0] RXCHARISK_IN
                                        ,   input wire  [1:0] RXLOSSOFSYNC_IN
                                        


                                        ,   output reg [31:0] RXDATA_OUT
                                        ,   output reg  [3:0] RXCHARISK_OUT



                                        ,   output reg RXVLD_OUT
                                        );








wire is_idle_frame_i = is_word_aligned_i
                     && aligned_rxdata_i[31:16] == `KCH_IDLE
                     && aligned_rxcharisk_i == `IDLE_KBITS
                     ;


always @ (posedge CLK_IN or posedge RESET_IN)
  if (RESET_IN)
    REG_IDSI_OUT <= {`IDLE_BITS{1'b1}};
  else
    if (is_idle_frame_i)
      REG_IDSI_OUT <= aligned_rxdata_i[`IDLE_BITS-1:0];





wire is_byte_aligned_i = (los_state_i == 2'b00);

localparam NUM_CLKC_FOR_SYNC = 4;

reg   [1:0] los_state_i;
reg   [2:0] los_cnt_i;


always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
	  los_cnt_i = 0;
	else
	  case ({los_state_i, RXLOSSOFSYNC_IN})
	    4'b01_01: los_cnt_i = los_cnt_i + 1;
	    default:  los_cnt_i = 0;
	  endcase
  
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
	  los_state_i = 2'b10;
	else
	  casex ({los_state_i, RXLOSSOFSYNC_IN})
	    4'bxx_10,
	    4'bxx_11: los_state_i = 2'b10;

	    4'b10_01: los_state_i = 2'b01;

	    4'b01_01: if (los_cnt_i >= NUM_CLKC_FOR_SYNC)
	                los_state_i = 2'b00;
                      else
	                los_state_i = los_state_i;

	    4'bxx_00: los_state_i = 2'b00;

	    default:  los_state_i = los_state_i;
	  endcase










wire [31:0] this_rxdata_i    = RXDATA_IN;
wire  [3:0] this_rxcharisk_i = RXCHARISK_IN;
reg  [31:8] last_rxdata_i;
reg   [3:1] last_rxcharisk_i;

always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			last_rxdata_i    <= 32'b0;
			last_rxcharisk_i <=  4'b0;
		end
	else
		begin
			last_rxdata_i    <= RXDATA_IN[31:8];
			last_rxcharisk_i <= RXCHARISK_IN[3:1];
		end

wire [63:8] unaligned_rxdata_i    = {this_rxdata_i,    last_rxdata_i};
wire  [7:1] unaligned_rxcharisk_i = {this_rxcharisk_i, last_rxcharisk_i};

reg [31:0] aligned_rxdata_i;
reg  [3:0] aligned_rxcharisk_i;



reg [3:0] alignment_i;

always @ (*)
	case (alignment_i)
		4'b0001: aligned_rxdata_i = unaligned_rxdata_i[39:8];
		4'b0010: aligned_rxdata_i = unaligned_rxdata_i[47:16];
		4'b0100: aligned_rxdata_i = unaligned_rxdata_i[55:24];
		4'b1000: aligned_rxdata_i = unaligned_rxdata_i[63:32];
		default: aligned_rxdata_i = 32'bX;
	endcase

always @ (*)
	case (alignment_i)
		4'b0001: aligned_rxcharisk_i = unaligned_rxcharisk_i[4:1];
		4'b0010: aligned_rxcharisk_i = unaligned_rxcharisk_i[5:2];
		4'b0100: aligned_rxcharisk_i = unaligned_rxcharisk_i[6:3];
		4'b1000: aligned_rxcharisk_i = unaligned_rxcharisk_i[7:4];
		default: aligned_rxcharisk_i = 4'bXXXX;
	endcase



always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		alignment_i <= 4'b0000;
	else
		if (!is_byte_aligned_i)
			alignment_i <= 4'b0000;
		else if (RXCHARISCOMMA_IN != 4'b0000)
			alignment_i <= RXCHARISCOMMA_IN;

wire is_word_aligned_i = is_byte_aligned_i && alignment_i != 4'b0000;







wire is_clock_correction_sequence = is_word_aligned_i
                                  && aligned_rxdata_i    == {4{`KCH_CLKC}}
                                  && aligned_rxcharisk_i == 4'b1111
                                  ;



























wire is_handshake_i = is_word_aligned_i
                    && aligned_rxdata_i[31:24] == `KCH_COMMA
                    && aligned_rxdata_i[23:16] == `KCH_HANDSHAKE
                    && aligned_rxcharisk_i == 4'b1100
                    ;

wire       handshake_phase_in_i   = is_handshake_i ? aligned_rxdata_i[8]   : 1'bX;
wire [7:0] handshake_version_in_i = is_handshake_i ? aligned_rxdata_i[7:0] : 8'bX;


always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		VERSION_MISMATCH_OUT <= 0;
	else
		if (is_handshake_i)
			VERSION_MISMATCH_OUT <= handshake_version_in_i != `PROTOCOL_VERSION;
		else
			VERSION_MISMATCH_OUT <= 1'b0;




reg last_handshake_phase_in_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		last_handshake_phase_in_i <= 0;
	else
		if (is_handshake_i)
			last_handshake_phase_in_i <= handshake_phase_in_i;






wire restart_handshake_i = !is_word_aligned_i
                         || (is_handshake_i && (handshake_phase_in_i   <  last_handshake_phase_in_i))
                         || (is_handshake_i && (handshake_version_in_i != `PROTOCOL_VERSION))
                         ;





reg [NUM_HANDSHAKES_BITS-1:0] handshake_counter_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		handshake_counter_i <= 0;
	else
		if (is_handshake_i && !restart_handshake_i)
			begin
				if (handshake_counter_i < NUM_HANDSHAKES)
					handshake_counter_i <= handshake_counter_i + 1;
			end
		else if (!is_clock_correction_sequence)
			handshake_counter_i <= 0;



assign HANDSHAKE_PHASE_OUT = handshake_counter_i == NUM_HANDSHAKES;



always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		HANDSHAKE_COMPLETE_OUT <= 1'b0;
	else
		if (restart_handshake_i)
			HANDSHAKE_COMPLETE_OUT <= 1'b0;
		else if (HANDSHAKE_PHASE_OUT == 1'b1 && handshake_phase_in_i == 1'b1)
			HANDSHAKE_COMPLETE_OUT <= 1'b1;










always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			RXDATA_OUT    <= 32'bX;
			RXCHARISK_OUT <= 4'bX;
			RXVLD_OUT     <= 1'b0;
		end
	else
		if (is_word_aligned_i && HANDSHAKE_COMPLETE_OUT && !is_clock_correction_sequence 
                     && !is_handshake_i && !is_idle_frame_i
                   )
			begin
				RXDATA_OUT    <= aligned_rxdata_i;
				RXCHARISK_OUT <= aligned_rxcharisk_i;
				RXVLD_OUT     <= 1'b1;
			end
		else
			begin
				RXDATA_OUT    <= 32'bX;
				RXCHARISK_OUT <= 4'bX;
				RXVLD_OUT     <= 1'b0;
			end


endmodule