data/full_repos/permissive/143278/ivltests/pr2815398a.v
 line:10: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2815398a.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2815398a.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2815398a.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2815398a.v:29: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                          : ... In instance top\n      dummy[i] = 1\'b0;\n               ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass;
  reg [2:0] res [0:7];
  reg [2:0] in [0:7];
  reg [7:0] dummy [0:6];
  time run_time [0:7];
  time exp_time [0:7];
  integer i;

  initial begin
    pass = 1'b1;
    #1;

    for (i=0; i<8; i=i+1) begin
      in[i] = i[2:0];
    end
    #1;
    for (i=0; i<8; i=i+1) begin
      exp_time[i] = $time-1;
    end
    check;


    for (i=0; i<7; i=i+1) begin
      dummy[i] = 1'b0;
      #1;
      exp_time[i] = $time-1;
      check;
    end

    if (pass) $display("PASSED");
  end


  task check;
    integer j;
    begin
      for (j=0; j<8; j=j+1) begin
        if (res[j] !== j[2:0]) begin
          $display("FAILED: index %0d value, at %2t, expexted %b, got %b.",
                   j, $time, j[2:0], res[j]);
          pass = 1'b0;
        end
        if (run_time[j] !== exp_time[j]) begin
          $display("FAILED: index %0d time, at %2t, expexted %2t, got %2t.",
                   j, $time, exp_time[j], run_time[j]);
          pass = 1'b0;
        end
      end
    end
  endtask

  genvar m;
  generate
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
     for (m=0; m<=7; m=m+1) begin: idac_loop
`else
     for (m=0; m<=6; m=m+1) begin: idac_loop
`endif

      always @ (in[m] or dummy[m]) begin
        res[m] = in[m];
        run_time[m] = $time;
      end
    end
  endgenerate
endmodule
module top;

  reg pass;
  reg [2:0] res [0:7];
  reg [2:0] in [0:7];
  reg [7:0] dummy [0:6];
  time run_time [0:7];
  time exp_time [0:7];
  integer i;

  initial begin
    pass = 1'b1;
    #1;

    for (i=0; i<8; i=i+1) begin
      in[i] = i[2:0];
    end
    #1;
    for (i=0; i<8; i=i+1) begin
      exp_time[i] = $time-1;
    end
    check;


    for (i=0; i<7; i=i+1) begin
      dummy[i] = 1'b0;
      #1;
      exp_time[i] = $time-1;
      check;
    end

    if (pass) $display("PASSED");
  end


  task check;
    integer j;
    begin
      for (j=0; j<8; j=j+1) begin
        if (res[j] !== j[2:0]) begin
          $display("FAILED: index %0d value, at %2t, expexted %b, got %b.",
                   j, $time, j[2:0], res[j]);
          pass = 1'b0;
        end
        if (run_time[j] !== exp_time[j]) begin
          $display("FAILED: index %0d time, at %2t, expexted %2t, got %2t.",
                   j, $time, exp_time[j], run_time[j]);
          pass = 1'b0;
        end
      end
    end
  endtask

  genvar m;
  generate
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
     for (m=0; m<=7; m=m+1) begin: idac_loop
`else
     for (m=0; m<=6; m=m+1) begin: idac_loop
`endif

      always @ (in[m] or dummy[m]) begin
        res[m] = in[m];
        run_time[m] = $time;
      end
    end
  endgenerate
endmodule