data/full_repos/permissive/200314387/verilog/random/random.v
1: b'%Warning-WIDTH: data/full_repos/permissive/200314387/verilog/random/random.v:22: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance random\n        val <= #27 $random;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module random (
    input clk,
    input _OE,
    output [7:0] Q
);
    reg [7:0] val = 0;




    assign Q = _OE ? 8'bz: val;

    always @(posedge clk) begin
        val <= #27 $random;
    end

endmodule
module random (
    input clk,
    input _OE,
    output [7:0] Q
);

    reg [7:0] val = 0;




    assign Q = _OE ? 8'bz: val;

    always @(posedge clk) begin
        val <= #27 $random;
    end

endmodule