data/full_repos/permissive/122125962/hardware/SDRv2_src_sync_rst/fifo/fifo128x8.v
1: b'%Warning-WIDTH: data/full_repos/permissive/122125962/hardware/SDRv2_src_sync_rst/fifo/fifo128x8.v:20: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'tail\' generates 7 bits.\n                                                                                                    : ... In instance fifo128x8\nassign EMPTY = (half)? ((head==0)&&(tail==DEPTH-1))? 1 : (head == (tail+1))? 1 : 0 : 0;\n                                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/122125962/hardware/SDRv2_src_sync_rst/fifo/fifo128x8.v:40: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 8 bits.\n                                                                                                    : ... In instance fifo128x8\n  tail <= DEPTH - 1;\n       ^~\n%Error: Exiting due to 2 warning(s)\n'
module fifo128x8(DATA, Q, CLK, WE, RE, RESET, FULL, EMPTY);

parameter WIDTH = 8;
parameter HALF_WIDTH = (WIDTH>>1);
parameter DEPTH = 128;
parameter DEPTH_BITS = 7;

input	[WIDTH-1:0] DATA;
output	[HALF_WIDTH-1:0] Q;

input	CLK, RESET, WE, RE;
output	FULL, EMPTY;

reg		[WIDTH-1:0] mem [0:DEPTH-1];
reg		[DEPTH_BITS-1:0] head, tail; 
reg		half;

assign Q = (half)? mem[tail][WIDTH-1:HALF_WIDTH] : mem[tail][HALF_WIDTH-1:0];

assign EMPTY = (half)? ((head==0)&&(tail==DEPTH-1))? 1 : (head == (tail+1))? 1 : 0 : 0;
assign FULL = (head==tail)? 1:0;

integer k;

`define SD #1



always @ (posedge CLK)
begin
	if (~RESET)
	begin
		head <= 0;
		tail <= DEPTH - 1;
		half <= 1;
		for (k = 0; k < DEPTH; k = k + 1)
    		mem[k] <= 0;
	end
	else
	begin
		if (RE & ~EMPTY)
		begin
			half <= `SD ~half;
			if (half)
				tail <= `SD tail + 1;
		end

		if (WE & ~FULL)
		begin
			mem[head] <= `SD DATA;
			head <= `SD head + 1;
		end
	end
end


endmodule
module fifo128x8(DATA, Q, CLK, WE, RE, RESET, FULL, EMPTY);


parameter WIDTH = 8;
parameter HALF_WIDTH = (WIDTH>>1);
parameter DEPTH = 128;
parameter DEPTH_BITS = 7;

input	[WIDTH-1:0] DATA;
output	[HALF_WIDTH-1:0] Q;

input	CLK, RESET, WE, RE;
output	FULL, EMPTY;

reg		[WIDTH-1:0] mem [0:DEPTH-1];
reg		[DEPTH_BITS-1:0] head, tail; 
reg		half;

assign Q = (half)? mem[tail][WIDTH-1:HALF_WIDTH] : mem[tail][HALF_WIDTH-1:0];

assign EMPTY = (half)? ((head==0)&&(tail==DEPTH-1))? 1 : (head == (tail+1))? 1 : 0 : 0;
assign FULL = (head==tail)? 1:0;

integer k;

`define SD #1



always @ (posedge CLK)
begin
	if (~RESET)
	begin
		head <= 0;
		tail <= DEPTH - 1;
		half <= 1;
		for (k = 0; k < DEPTH; k = k + 1)
    		mem[k] <= 0;
	end
	else
	begin
		if (RE & ~EMPTY)
		begin
			half <= `SD ~half;
			if (half)
				tail <= `SD tail + 1;
		end

		if (WE & ~FULL)
		begin
			mem[head] <= `SD DATA;
			head <= `SD head + 1;
		end
	end
end


endmodule