data/full_repos/permissive/157490365/buildV1.1/stack3.v
1: b"%Error: data/full_repos/permissive/157490365/buildV1.1/stack3.v:6: Cannot find file containing module: 'mux2'\n    mux2 a0(i0[0],i1[0],op,out[0]);\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/157490365/buildV1.1,data/full_repos/permissive/157490365/mux2\n             data/full_repos/permissive/157490365/buildV1.1,data/full_repos/permissive/157490365/mux2.v\n             data/full_repos/permissive/157490365/buildV1.1,data/full_repos/permissive/157490365/mux2.sv\n             mux2\n             mux2.v\n             mux2.sv\n             obj_dir/mux2\n             obj_dir/mux2.v\n             obj_dir/mux2.sv\n%Error: data/full_repos/permissive/157490365/buildV1.1/stack3.v:7: Cannot find file containing module: 'mux2'\n    mux2 a1(i0[1],i1[1],op,out[1]);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/buildV1.1/stack3.v:8: Cannot find file containing module: 'mux2'\n    mux2 a2(i0[2],i1[2],op,out[2]);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/buildV1.1/stack3.v:2: Cannot find file containing module: 'dfrl'\n    dfrl dl[2:0](clk, reset, load, d[2:0], q[2:0]);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/buildV1.1/stack3.v:17: Cannot find file containing module: 'or2'\n    or2 o0(push, pop, push_or_pop);\n    ^~~\n%Error: data/full_repos/permissive/157490365/buildV1.1/stack3.v:19: Cannot find file containing module: 'fas3'\n    fas3 a(top, 3'b001, 1'b0, inc, carry_a);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/buildV1.1/stack3.v:20: Cannot find file containing module: 'fas3'\n    fas3 b(top, 3'b001, 1'b1, dec, carry_s);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/buildV1.1/stack3.v:36: Cannot find file containing module: 'reg_file'\n    reg_file rf(clk, reset, push, top, 3'bxxx, top, value_in, value_out, d_care);\n    ^~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module stack(input wire clk, reset, push, pop, input wire [15:0] value_in, output wire [15:0] value_out);
    wire [2:0] top, inc_temp, dec_temp, inc_dec, inc, dec;
    wire carry_a, carry_s, is7, is0;
    wire push_or_pop;
    wire [15:0] d_care;

    or2 o0(push, pop, push_or_pop);

    fas3 a(top, 3'b001, 1'b0, inc, carry_a);
    fas3 b(top, 3'b001, 1'b1, dec, carry_s);








    
    mux2_3 m23_2(pop, inc, dec, inc_dec);

    reg_3 r3(clk, reset, push_or_pop, inc_dec, top);



    reg_file rf(clk, reset, push, top, 3'bxxx, top, value_in, value_out, d_care);
endmodule
module stack(input wire clk, reset, push, pop, input wire [15:0] value_in, output wire [15:0] value_out);

    wire [2:0] top, inc_temp, dec_temp, inc_dec, inc, dec;
    wire carry_a, carry_s, is7, is0;
    wire push_or_pop;
    wire [15:0] d_care;

    or2 o0(push, pop, push_or_pop);

    fas3 a(top, 3'b001, 1'b0, inc, carry_a);
    fas3 b(top, 3'b001, 1'b1, dec, carry_s);








    
    mux2_3 m23_2(pop, inc, dec, inc_dec);

    reg_3 r3(clk, reset, push_or_pop, inc_dec, top);



    reg_file rf(clk, reset, push, top, 3'bxxx, top, value_in, value_out, d_care);
endmodule