data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v
1: b"%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:35: Cannot find file containing module: 'NODE_0'\n NODE_0 NODE_0 (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/NODE_0\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/NODE_0.v\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/NODE_0.sv\n             NODE_0\n             NODE_0.v\n             NODE_0.sv\n             obj_dir/NODE_0\n             obj_dir/NODE_0.v\n             obj_dir/NODE_0.sv\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:45: Cannot find file containing module: 'NODE_1'\n  NODE_1 NODE_1 (\n  ^~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:54: Cannot find file containing module: 'NODE_2'\n  NODE_2 NODE_2 (\n  ^~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:63: Cannot find file containing module: 'NODE_3'\n  NODE_3 NODE_3 (\n  ^~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:72: Cannot find file containing module: 'NODE_4'\n  NODE_4 NODE_4 (\n  ^~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:81: Cannot find file containing module: 'NODE_5'\n  NODE_5 NODE_5 (\n  ^~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:90: Cannot find file containing module: 'NODE_6'\n  NODE_6 NODE_6 (\n  ^~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:99: Cannot find file containing module: 'NODE_7'\n  NODE_7 NODE_7 (\n  ^~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:108: Cannot find file containing module: 'NODE_8'\n  NODE_8 NODE_8 (\n  ^~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:117: Cannot find file containing module: 'NODE_9'\n  NODE_9 NODE_9 (\n  ^~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:126: Cannot find file containing module: 'NODE_10'\n  NODE_10 NODE_10 (\n  ^~~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:135: Cannot find file containing module: 'NODE_11'\n  NODE_11 NODE_11 (\n  ^~~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:144: Cannot find file containing module: 'NODE_12'\n  NODE_12 NODE_12 (\n  ^~~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:153: Cannot find file containing module: 'NODE_13'\n  NODE_13 NODE_13 (\n  ^~~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:162: Cannot find file containing module: 'NODE_14'\n  NODE_14 NODE_14 (\n  ^~~~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/FC_LAYER.v:171: Cannot find file containing module: 'NODE_15'\n  NODE_15 NODE_15 (\n  ^~~~~~~\n%Error: Exiting due to 16 error(s)\n"
module FC_LAYER(
input [35:0] A,
input CLK,
input ENABLE,
input RST,
input [5:0] COUNT,
input [3:0] READ,
output reg DONE,
output reg signed [39:0] OUT_PORT
 );
 
 wire NODE_DONE;
 wire signed [39:0] Z0;
 wire signed [39:0] Z1;
 wire signed [39:0] Z2;
 wire signed [39:0] Z3;
 wire signed [39:0] Z4;
 wire signed [39:0] Z5;
 wire signed [39:0] Z6;
 wire signed [39:0] Z7;
 wire signed [39:0] Z8;
 wire signed [39:0] Z9;
 wire signed [39:0] Z10;
 wire signed [39:0] Z11;
 wire signed [39:0] Z12;
 wire signed [39:0] Z13;
 wire signed [39:0] Z14;
 wire signed [39:0] Z15;

always@(posedge CLK) DONE <= NODE_DONE;

 NODE_0 NODE_0 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z0),
 .DONE(NODE_DONE)
 );
 
  NODE_1 NODE_1 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z1)
 );
 
  NODE_2 NODE_2 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z2)
 );
 
  NODE_3 NODE_3 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z3)
 );
 
  NODE_4 NODE_4 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z4)
 );
 
  NODE_5 NODE_5 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z5)
 );
 
  NODE_6 NODE_6 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z6)
 );
 
  NODE_7 NODE_7 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z7)
 );
 
  NODE_8 NODE_8 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z8)
 );
 
  NODE_9 NODE_9 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z9)
 );
 
  NODE_10 NODE_10 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z10)
 );
 
  NODE_11 NODE_11 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z11)
 );
 
  NODE_12 NODE_12 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z12)
 );
 
  NODE_13 NODE_13 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z13)
 );
 
  NODE_14 NODE_14 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z14)
 );
 
  NODE_15 NODE_15 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z15)
 );
   


 reg [39:0] REGBLOCK [15:0];
always@ ( posedge CLK )
 begin
     if (NODE_DONE)
         begin
         case(READ)
             4'd0: OUT_PORT<=REGBLOCK[0];
             4'd1: OUT_PORT<=REGBLOCK[1];
             4'd2: OUT_PORT<=REGBLOCK[2];
             4'd3: OUT_PORT<=REGBLOCK[3];
             4'd4: OUT_PORT<=REGBLOCK[4];
             4'd5: OUT_PORT<=REGBLOCK[5];
             4'd6: OUT_PORT<=REGBLOCK[6];
             4'd7: OUT_PORT<=REGBLOCK[7];
             4'd8: OUT_PORT<=REGBLOCK[8];
             4'd9: OUT_PORT<=REGBLOCK[9];
             4'd10: OUT_PORT<=REGBLOCK[10];
             4'd11: OUT_PORT<=REGBLOCK[11];
             4'd12: OUT_PORT<=REGBLOCK[12];
             4'd13: OUT_PORT<=REGBLOCK[13]; 
             4'd14: OUT_PORT<=REGBLOCK[14];
             4'd15: OUT_PORT<=REGBLOCK[15];
             default: OUT_PORT<= 40'd0;     
         endcase
         end
 end
always@ ( posedge CLK )
begin
    if (NODE_DONE)
        begin
        REGBLOCK[0]<=Z0;
        REGBLOCK[1]<=Z1;
        REGBLOCK[2]<=Z2;
        REGBLOCK[3]<=Z3;
        REGBLOCK[4]<=Z4;
        REGBLOCK[5]<=Z5;
        REGBLOCK[6]<=Z6;
        REGBLOCK[7]<=Z7;
        REGBLOCK[8]<=Z8;
        REGBLOCK[9]<=Z9;
        REGBLOCK[10]<=Z10;
        REGBLOCK[11]<=Z11;
        REGBLOCK[12]<=Z12;
        REGBLOCK[13]<=Z13;  
        REGBLOCK[14]<=Z14;
        REGBLOCK[15]<=Z15;  
  end
  
end
 
endmodule
module FC_LAYER(
input [35:0] A,
input CLK,
input ENABLE,
input RST,
input [5:0] COUNT,
input [3:0] READ,
output reg DONE,
output reg signed [39:0] OUT_PORT
 );

 
 wire NODE_DONE;
 wire signed [39:0] Z0;
 wire signed [39:0] Z1;
 wire signed [39:0] Z2;
 wire signed [39:0] Z3;
 wire signed [39:0] Z4;
 wire signed [39:0] Z5;
 wire signed [39:0] Z6;
 wire signed [39:0] Z7;
 wire signed [39:0] Z8;
 wire signed [39:0] Z9;
 wire signed [39:0] Z10;
 wire signed [39:0] Z11;
 wire signed [39:0] Z12;
 wire signed [39:0] Z13;
 wire signed [39:0] Z14;
 wire signed [39:0] Z15;

always@(posedge CLK) DONE <= NODE_DONE;

 NODE_0 NODE_0 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z0),
 .DONE(NODE_DONE)
 );
 
  NODE_1 NODE_1 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z1)
 );
 
  NODE_2 NODE_2 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z2)
 );
 
  NODE_3 NODE_3 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z3)
 );
 
  NODE_4 NODE_4 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z4)
 );
 
  NODE_5 NODE_5 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z5)
 );
 
  NODE_6 NODE_6 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z6)
 );
 
  NODE_7 NODE_7 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z7)
 );
 
  NODE_8 NODE_8 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z8)
 );
 
  NODE_9 NODE_9 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z9)
 );
 
  NODE_10 NODE_10 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z10)
 );
 
  NODE_11 NODE_11 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z11)
 );
 
  NODE_12 NODE_12 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z12)
 );
 
  NODE_13 NODE_13 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z13)
 );
 
  NODE_14 NODE_14 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z14)
 );
 
  NODE_15 NODE_15 (
 .A(A),
 .step(COUNT),
 .CLK(CLK),
 .ENABLE(ENABLE),
 .RST(RST),
 .OUT(Z15)
 );
   


 reg [39:0] REGBLOCK [15:0];
always@ ( posedge CLK )
 begin
     if (NODE_DONE)
         begin
         case(READ)
             4'd0: OUT_PORT<=REGBLOCK[0];
             4'd1: OUT_PORT<=REGBLOCK[1];
             4'd2: OUT_PORT<=REGBLOCK[2];
             4'd3: OUT_PORT<=REGBLOCK[3];
             4'd4: OUT_PORT<=REGBLOCK[4];
             4'd5: OUT_PORT<=REGBLOCK[5];
             4'd6: OUT_PORT<=REGBLOCK[6];
             4'd7: OUT_PORT<=REGBLOCK[7];
             4'd8: OUT_PORT<=REGBLOCK[8];
             4'd9: OUT_PORT<=REGBLOCK[9];
             4'd10: OUT_PORT<=REGBLOCK[10];
             4'd11: OUT_PORT<=REGBLOCK[11];
             4'd12: OUT_PORT<=REGBLOCK[12];
             4'd13: OUT_PORT<=REGBLOCK[13]; 
             4'd14: OUT_PORT<=REGBLOCK[14];
             4'd15: OUT_PORT<=REGBLOCK[15];
             default: OUT_PORT<= 40'd0;     
         endcase
         end
 end
always@ ( posedge CLK )
begin
    if (NODE_DONE)
        begin
        REGBLOCK[0]<=Z0;
        REGBLOCK[1]<=Z1;
        REGBLOCK[2]<=Z2;
        REGBLOCK[3]<=Z3;
        REGBLOCK[4]<=Z4;
        REGBLOCK[5]<=Z5;
        REGBLOCK[6]<=Z6;
        REGBLOCK[7]<=Z7;
        REGBLOCK[8]<=Z8;
        REGBLOCK[9]<=Z9;
        REGBLOCK[10]<=Z10;
        REGBLOCK[11]<=Z11;
        REGBLOCK[12]<=Z12;
        REGBLOCK[13]<=Z13;  
        REGBLOCK[14]<=Z14;
        REGBLOCK[15]<=Z15;  
  end
  
end
 
endmodule