data/full_repos/permissive/135852214/Verilog/Memory.v
data/verilator_xmls/f46c3e48-7ae5-45d3-8a41-8bf778d925cb.xml
module Memory(
    input clk,
	 input reset,
    input write,
    input [7:0] address,
    input [7:0] data_in,
    output reg [7:0] data_out 
    );
	reg [7:0] r[0:255];
	always @(posedge clk, posedge reset)
	if(reset)
	begin
			r[0] <= 8'b01000000;
			r[1] <= 8'b00001010;
			r[2] <= 8'b01100000;
			r[3] <= 8'b00000101;
			r[4] <= 8'b00000000;
			r[5] <= 8'b10000000;
			r[6] <= 8'b00001000;
			r[7] <= 8'b11100000;
			r[8] <= 8'b00000000;
	end
	
	always @*
		if(~write)
			data_out <= r[address];
		else
			r[address] <= data_in;
		

endmodule
module Memory(
    input clk,
	 input reset,
    input write,
    input [7:0] address,
    input [7:0] data_in,
    output reg [7:0] data_out 
    );

	reg [7:0] r[0:255];
	always @(posedge clk, posedge reset)
	if(reset)
	begin
			r[0] <= 8'b01000000;
			r[1] <= 8'b00001010;
			r[2] <= 8'b01100000;
			r[3] <= 8'b00000101;
			r[4] <= 8'b00000000;
			r[5] <= 8'b10000000;
			r[6] <= 8'b00001000;
			r[7] <= 8'b11100000;
			r[8] <= 8'b00000000;
	end
	
	always @*
		if(~write)
			data_out <= r[address];
		else
			r[address] <= data_in;
		

endmodule