data/full_repos/permissive/219219909/Vedic_Multiplier/src/buf1.v
data/verilator_xmls/64321f5a-8262-4d81-aa4d-9ae6231f2923.xml
module buf1(
    input [23:0] a,
    input [23:0] b,
    input clk,
    output reg [23:0] a1,
    output reg [23:0] b1
    );

always @(posedge clk) begin
a1<=a;
b1<=b;
end

endmodule
module buf1(
    input [23:0] a,
    input [23:0] b,
    input clk,
    output reg [23:0] a1,
    output reg [23:0] b1
    );


always @(posedge clk) begin
a1<=a;
b1<=b;
end

endmodule