data/full_repos/permissive/175316557/sprite.v
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1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/175316557/sprite.v:203: Unsized numbers/parameters not allowed in concatenations.\n                                                                       : ... In instance sprite_draw.s_data.gsc\nassign mem_offset_x = {7-get_x,2\'b00};\n                        ^\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/175316557/sprite.v:203: Unsized numbers/parameters not allowed in replications.\n                                                                       : ... In instance sprite_draw.s_data.gsc\nassign mem_offset_x = {7-get_x,2\'b00};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/175316557/sprite.v:89: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                : ... In instance sprite_draw.s_data\nassign x_out = x_anchor + pixel_loc[2:0];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/175316557/sprite.v:90: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                : ... In instance sprite_draw.s_data\nassign y_out = y_anchor + pixel_loc[5:3];\n                        ^\n%Error: data/full_repos/permissive/175316557/sprite.v:26: Cannot find file containing module: \'vga_adapter\'\nvga_adapter VGA(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175316557,data/full_repos/permissive/175316557/vga_adapter\n             data/full_repos/permissive/175316557,data/full_repos/permissive/175316557/vga_adapter.v\n             data/full_repos/permissive/175316557,data/full_repos/permissive/175316557/vga_adapter.sv\n             vga_adapter\n             vga_adapter.v\n             vga_adapter.sv\n             obj_dir/vga_adapter\n             obj_dir/vga_adapter.v\n             obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module sprite_control(
        input clk,
        input resetn,
        input go,

        output reg plot,
        output reg ld_xys,
        output reg [5:0] pixel_loc
    );

reg [1:0] current_state, next_state;
wire finished_counting;
assign finished_counting = pixel_loc == 6'b111111;

localparam  S_LOAD        = 2'd0,
            S_LOAD_WAIT   = 2'd1,
            S_DRAW        = 2'd2;


always@(*)
begin: state_table
    case (current_state)
        S_LOAD: next_state = go ? S_LOAD_WAIT : S_LOAD;
        S_LOAD_WAIT: next_state = go ? S_LOAD_WAIT : S_DRAW;
        S_DRAW: next_state = finished_counting ? S_LOAD : S_DRAW;
        default: next_state = S_LOAD;
    endcase
end



always @(*)
begin: enable_signals

    ld_xys = 1'b0;
    plot = 1'b0;
    case (current_state)
        S_LOAD_WAIT: begin
            ld_xys  = 1'b1;
        end
        S_DRAW: begin
            plot  = 1'b1;
        end

    endcase
end

always@(posedge clk)
begin: drawing
    if(current_state == S_DRAW && ~finished_counting)
        pixel_loc <= pixel_loc + 1;
    else
        pixel_loc <= 6'b0;
end


always@(posedge clk)
begin: state_FFs
    if(!resetn)
        current_state <= S_LOAD;
    else
        current_state <= next_state;
end
endmodule
module sprite_control(
        input clk,
        input resetn,
        input go,

        output reg plot,
        output reg ld_xys,
        output reg [5:0] pixel_loc
    );


reg [1:0] current_state, next_state;
wire finished_counting;
assign finished_counting = pixel_loc == 6'b111111;

localparam  S_LOAD        = 2'd0,
            S_LOAD_WAIT   = 2'd1,
            S_DRAW        = 2'd2;


always@(*)
begin: state_table
    case (current_state)
        S_LOAD: next_state = go ? S_LOAD_WAIT : S_LOAD;
        S_LOAD_WAIT: next_state = go ? S_LOAD_WAIT : S_DRAW;
        S_DRAW: next_state = finished_counting ? S_LOAD : S_DRAW;
        default: next_state = S_LOAD;
    endcase
end



always @(*)
begin: enable_signals

    ld_xys = 1'b0;
    plot = 1'b0;
    case (current_state)
        S_LOAD_WAIT: begin
            ld_xys  = 1'b1;
        end
        S_DRAW: begin
            plot  = 1'b1;
        end

    endcase
end

always@(posedge clk)
begin: drawing
    if(current_state == S_DRAW && ~finished_counting)
        pixel_loc <= pixel_loc + 1;
    else
        pixel_loc <= 6'b0;
end


always@(posedge clk)
begin: state_FFs
    if(!resetn)
        current_state <= S_LOAD;
    else
        current_state <= next_state;
end
endmodule