data/full_repos/permissive/142505464/modules/wb_slave_adapter/rtl/verilog/wb_slave_adapter.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/a3455c20-23b6-4906-b7c5-d07565941a63.xml
module wb_slave_adapter #(
    parameter dw = 32,
    parameter aw = 32,

    parameter g_master_mode        = 0,

    parameter g_master_granularity = 0,

    parameter g_slave_mode         = 0,

    parameter g_slave_granularity  = 0
) (

    input               clk_i,
    input               rst_n_i,



    input  [aw-1:0]     sl_adr_i,
    input  [dw-1:0]     sl_dat_i,
    input  [dw/8-1:0]   sl_sel_i,
    input               sl_we_i,
    input               sl_cyc_i,
    input               sl_stb_i,
    output [dw-1:0]     sl_dat_o,
    output              sl_ack_o,
    output              sl_err_o,
    output              sl_rty_o,
    output              sl_stall_o,


    output [aw-1:0]     ma_adr_o,
    output [dw-1:0]     ma_dat_o,
    output [dw/8-1:0]   ma_sel_o,
    output              ma_we_o,
    output              ma_cyc_o,
    output              ma_stb_o,
    input [dw-1:0]      ma_dat_i,
    input               ma_ack_i,
    input               ma_err_i,
    input               ma_rty_i,
    input               ma_stall_i
);



localparam c_num_bytes2word_bits = 2;
localparam [c_num_bytes2word_bits-1:0] c_zero_bytes2word = 0;
localparam c_state_width = 1;
localparam [c_state_width-1:0]
    IDLE = 0,
    WAIT4ACK = 1;

reg [c_state_width-1:0] fsm_state = IDLE;


generate
    if (g_master_granularity == g_slave_granularity)
        assign ma_adr_o = sl_adr_i;
    else if (g_master_granularity == 0)
        assign ma_adr_o = {sl_adr_i[32-c_num_bytes2word_bits-1:0], c_zero_bytes2word};
    else
        assign ma_adr_o = {c_zero_bytes2word, sl_adr_i[32-1:c_num_bytes2word_bits]};
endgenerate


generate if (g_slave_mode != 0 && g_slave_mode != 1) begin: gen_error
    g_slave_mode_is_invalid_valid_modes_are_classic_or_pipelined invalid();
end
endgenerate


generate if (g_master_mode != 0 && g_master_mode != 1) begin: gen_error
    g_master_mode_is_invalid_valid_modes_are_classic_or_pipelined invalid();
end
endgenerate

generate if (g_slave_mode == 1 && g_master_mode == 0) begin: gen_p2c
    assign ma_stb_o = sl_stb_i;
    assign sl_stall_o = ~ma_ack_i;
end
endgenerate

generate if (g_slave_mode == 0 && g_master_mode == 1) begin: gen_c2p
    assign ma_stb_o = (fsm_state == IDLE)? sl_stb_i : 0;
    assign sl_stall_o = 0;

    always @(posedge clk_i) begin
        if (~rst_n_i)
            fsm_state <= IDLE;
        else begin
            case (fsm_state)
                IDLE: begin
                    if (sl_stb_i && sl_cyc_i && ~ma_stall_i && ~ma_ack_i)
                        fsm_state <= WAIT4ACK;
                end

                WAIT4ACK: begin
                    if ((~sl_stb_i && ~sl_cyc_i) || ma_ack_i || ma_err_i)
                        fsm_state <= IDLE;
                end
            endcase
        end
    end
end
endgenerate

generate if (g_slave_mode == g_master_mode) begin: gen_x2x
    assign ma_stb_o = sl_stb_i;
    assign sl_stall_o = ma_stall_i;
end
endgenerate

assign ma_dat_o = sl_dat_i;
assign ma_cyc_o = sl_cyc_i;
assign ma_sel_o = sl_sel_i;
assign ma_we_o  = sl_we_i;

assign sl_ack_o = ma_ack_i;
assign sl_err_o = ma_err_i;
assign sl_rty_o = ma_rty_i;
assign sl_dat_o = ma_dat_i;

endmodule
module wb_slave_adapter #(
    parameter dw = 32,
    parameter aw = 32,

    parameter g_master_mode        = 0,

    parameter g_master_granularity = 0,

    parameter g_slave_mode         = 0,

    parameter g_slave_granularity  = 0
) (

    input               clk_i,
    input               rst_n_i,



    input  [aw-1:0]     sl_adr_i,
    input  [dw-1:0]     sl_dat_i,
    input  [dw/8-1:0]   sl_sel_i,
    input               sl_we_i,
    input               sl_cyc_i,
    input               sl_stb_i,
    output [dw-1:0]     sl_dat_o,
    output              sl_ack_o,
    output              sl_err_o,
    output              sl_rty_o,
    output              sl_stall_o,


    output [aw-1:0]     ma_adr_o,
    output [dw-1:0]     ma_dat_o,
    output [dw/8-1:0]   ma_sel_o,
    output              ma_we_o,
    output              ma_cyc_o,
    output              ma_stb_o,
    input [dw-1:0]      ma_dat_i,
    input               ma_ack_i,
    input               ma_err_i,
    input               ma_rty_i,
    input               ma_stall_i
);




localparam c_num_bytes2word_bits = 2;
localparam [c_num_bytes2word_bits-1:0] c_zero_bytes2word = 0;
localparam c_state_width = 1;
localparam [c_state_width-1:0]
    IDLE = 0,
    WAIT4ACK = 1;

reg [c_state_width-1:0] fsm_state = IDLE;


generate
    if (g_master_granularity == g_slave_granularity)
        assign ma_adr_o = sl_adr_i;
    else if (g_master_granularity == 0)
        assign ma_adr_o = {sl_adr_i[32-c_num_bytes2word_bits-1:0], c_zero_bytes2word};
    else
        assign ma_adr_o = {c_zero_bytes2word, sl_adr_i[32-1:c_num_bytes2word_bits]};
endgenerate


generate if (g_slave_mode != 0 && g_slave_mode != 1) begin: gen_error
    g_slave_mode_is_invalid_valid_modes_are_classic_or_pipelined invalid();
end
endgenerate


generate if (g_master_mode != 0 && g_master_mode != 1) begin: gen_error
    g_master_mode_is_invalid_valid_modes_are_classic_or_pipelined invalid();
end
endgenerate

generate if (g_slave_mode == 1 && g_master_mode == 0) begin: gen_p2c
    assign ma_stb_o = sl_stb_i;
    assign sl_stall_o = ~ma_ack_i;
end
endgenerate

generate if (g_slave_mode == 0 && g_master_mode == 1) begin: gen_c2p
    assign ma_stb_o = (fsm_state == IDLE)? sl_stb_i : 0;
    assign sl_stall_o = 0;

    always @(posedge clk_i) begin
        if (~rst_n_i)
            fsm_state <= IDLE;
        else begin
            case (fsm_state)
                IDLE: begin
                    if (sl_stb_i && sl_cyc_i && ~ma_stall_i && ~ma_ack_i)
                        fsm_state <= WAIT4ACK;
                end

                WAIT4ACK: begin
                    if ((~sl_stb_i && ~sl_cyc_i) || ma_ack_i || ma_err_i)
                        fsm_state <= IDLE;
                end
            endcase
        end
    end
end
endgenerate

generate if (g_slave_mode == g_master_mode) begin: gen_x2x
    assign ma_stb_o = sl_stb_i;
    assign sl_stall_o = ma_stall_i;
end
endgenerate

assign ma_dat_o = sl_dat_i;
assign ma_cyc_o = sl_cyc_i;
assign ma_sel_o = sl_sel_i;
assign ma_we_o  = sl_we_i;

assign sl_ack_o = ma_ack_i;
assign sl_err_o = ma_err_i;
assign sl_rty_o = ma_rty_i;
assign sl_dat_o = ma_dat_i;

endmodule