data/full_repos/permissive/162106151/pico_axilite_qsys/pico_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/162106151/pico_axilite_qsys/pico_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/162106151/pico_axilite_qsys/pico_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n #100 rst = 1;\n ^\n%Error: data/full_repos/permissive/162106151/pico_axilite_qsys/pico_tb.v:23: Cannot find file containing module: \'pico_axilite_top\'\npico_axilite_top uo(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162106151/pico_axilite_qsys,data/full_repos/permissive/162106151/pico_axilite_top\n             data/full_repos/permissive/162106151/pico_axilite_qsys,data/full_repos/permissive/162106151/pico_axilite_top.v\n             data/full_repos/permissive/162106151/pico_axilite_qsys,data/full_repos/permissive/162106151/pico_axilite_top.sv\n             pico_axilite_top\n             pico_axilite_top.v\n             pico_axilite_top.sv\n             obj_dir/pico_axilite_top\n             obj_dir/pico_axilite_top.v\n             obj_dir/pico_axilite_top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pico_tb;


reg clk, rst;
wire rx, tx;
wire [7:0] led;
wire [8:0] seg1, seg2;

initial begin
	clk = 1;
	forever #10 clk = ~clk;
end

initial begin
	rst = 0;
	#100 rst = 1;
end

assign rx = 1;

pico_axilite_top uo(
	.clk(clk),
	.rst_n(rst),
	.rx(rx),
	.tx(tx),
	.led(led),
	.seg1(seg1),
	.seg2(seg2),
	.sw(4'b1111)
);


endmodule
module pico_tb;



reg clk, rst;
wire rx, tx;
wire [7:0] led;
wire [8:0] seg1, seg2;

initial begin
	clk = 1;
	forever #10 clk = ~clk;
end

initial begin
	rst = 0;
	#100 rst = 1;
end

assign rx = 1;

pico_axilite_top uo(
	.clk(clk),
	.rst_n(rst),
	.rx(rx),
	.tx(tx),
	.led(led),
	.seg1(seg1),
	.seg2(seg2),
	.sw(4'b1111)
);


endmodule