data/full_repos/permissive/217768747/division.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/217768747/division.v:45: Signal definition not found, creating implicitly: \'g\'\n  if(g || eq)\n     ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/division.v:45: Signal definition not found, creating implicitly: \'eq\'\n                                                                     : ... Suggested alternative: \'q\'\n  if(g || eq)\n          ^~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/division.v:51: Signal definition not found, creating implicitly: \'l\'\n  if(l)\n     ^\n%Error: data/full_repos/permissive/217768747/division.v:20: Cannot find file containing module: \'Comparator\'\nComparator comp(r,reg_b,l,g,eq);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/Comparator\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/Comparator.v\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/Comparator.sv\n             Comparator\n             Comparator.v\n             Comparator.sv\n             obj_dir/Comparator\n             obj_dir/Comparator.v\n             obj_dir/Comparator.sv\n%Error: data/full_repos/permissive/217768747/division.v:21: Cannot find file containing module: \'Sub\'\nSub subtract(r,reg_b,32\'b1,diff,borrow);\n^~~\n%Error: data/full_repos/permissive/217768747/division.v:22: Cannot find file containing module: \'Adder_32\'\nAdder_32 add(q,32\'b1,32\'b0,sum,carry);\n^~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module divison(page_rank,out_deg,clk,reset,quotient,done);
input [31:0] page_rank,out_deg;
input clk,reset;
output reg [31:0] quotient;
output reg done=0;



reg state; 
reg [31:0] q,r;
reg [31:0] reg_a, reg_b;



wire [31:0] sum,diff;
parameter s_wait=1'b0, first=1'b1;
Comparator comp(r,reg_b,l,g,eq);
Sub subtract(r,reg_b,32'b1,diff,borrow);
Adder_32 add(q,32'b1,32'b0,sum,carry);



always @(posedge clk, negedge reset)
begin
	state <= s_wait;
	if(!reset)
	begin
		quotient<=0;
		
	end
	else
	begin
		case(state)
		s_wait: begin
		reg_a <= page_rank;  
		reg_b <= out_deg;
		state<=first;
		q <= 0;
		r <= page_rank;
		end
		first: begin
		if(g || eq)
		begin
			q<=sum;
			r<=diff;
			state <= first;
		end
		if(l)
		begin	
		
			state <=s_wait;
			quotient <= q;	
			done = 1;
		end
		end
		endcase
	end
end
endmodule
module divison(page_rank,out_deg,clk,reset,quotient,done);

input [31:0] page_rank,out_deg;
input clk,reset;
output reg [31:0] quotient;
output reg done=0;



reg state; 
reg [31:0] q,r;
reg [31:0] reg_a, reg_b;



wire [31:0] sum,diff;
parameter s_wait=1'b0, first=1'b1;
Comparator comp(r,reg_b,l,g,eq);
Sub subtract(r,reg_b,32'b1,diff,borrow);
Adder_32 add(q,32'b1,32'b0,sum,carry);



always @(posedge clk, negedge reset)
begin
	state <= s_wait;
	if(!reset)
	begin
		quotient<=0;
		
	end
	else
	begin
		case(state)
		s_wait: begin
		reg_a <= page_rank;  
		reg_b <= out_deg;
		state<=first;
		q <= 0;
		r <= page_rank;
		end
		first: begin
		if(g || eq)
		begin
			q<=sum;
			r<=diff;
			state <= first;
		end
		if(l)
		begin	
		
			state <=s_wait;
			quotient <= q;	
			done = 1;
		end
		end
		endcase
	end
end
endmodule