data/full_repos/permissive/148201731/rtl/decode/instruction_decode.v
1: b"%Error: data/full_repos/permissive/148201731/rtl/decode/instruction_decode.v:123: Cannot find file containing module: 'instruction_decoder'\ninstruction_decoder\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/148201731/rtl/decode,data/full_repos/permissive/148201731/instruction_decoder\n             data/full_repos/permissive/148201731/rtl/decode,data/full_repos/permissive/148201731/instruction_decoder.v\n             data/full_repos/permissive/148201731/rtl/decode,data/full_repos/permissive/148201731/instruction_decoder.sv\n             instruction_decoder\n             instruction_decoder.v\n             instruction_decoder.sv\n             obj_dir/instruction_decoder\n             obj_dir/instruction_decoder.v\n             obj_dir/instruction_decoder.sv\n%Error: data/full_repos/permissive/148201731/rtl/decode/instruction_decode.v:162: Cannot find file containing module: 'register_bank'\nregister_bank\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/148201731/rtl/decode/instruction_decode.v:192: Cannot find file containing module: 'control'\ncontrol\n^~~~~~~\n%Error: data/full_repos/permissive/148201731/rtl/decode/instruction_decode.v:216: Cannot find file containing module: 'signal_extend'\nsignal_extend\n^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module instruction_decode
#(
   parameter PC_WIDTH = 20,
   parameter DATA_WIDTH = 32,
   parameter INSTRUCTION_WIDTH = 32,
   parameter REG_ADDR_WIDTH = 5,
   parameter OPCODE_WIDTH = 6,
   parameter FUNCTION_WIDTH = 6,
   parameter IMEDIATE_WIDTH = 16,
   parameter PC_OFFSET_WIDTH = 26
)
(
   input clk,
   input rst_n,
   input en,
   input [INSTRUCTION_WIDTH-1:0] instruction_in,

   
   input [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_in,
   input [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_in,
   input [DATA_WIDTH-1:0] reg_a_wr_data_in,
   input [DATA_WIDTH-1:0] reg_b_wr_data_in,
   input reg_a_wr_en_in,
   input reg_b_wr_en_in,





   input select_new_pc_in,

   input id_ex_mem_data_rd_en_in,
   input [REG_ADDR_WIDTH-1:0] id_ex_reg_wr_addr_in,



   output [REG_ADDR_WIDTH-1:0] reg_rd_addr1_out,
   output [REG_ADDR_WIDTH-1:0] reg_rd_addr2_out,

   output [OPCODE_WIDTH-1:0] opcode_out,
   output [FUNCTION_WIDTH-1:0] inst_function_out,
   output mem_data_rd_en_out,
   output mem_data_wr_en_out,
   output write_back_mux_sel_out,
   output [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_out,
   output [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_out,
   output reg_a_wr_en_out,
   output reg_b_wr_en_out,
   output [DATA_WIDTH-1:0] constant_out,
   output imm_inst_out,
   output [DATA_WIDTH-1:0] data_alu_a_out,
   output [DATA_WIDTH-1:0] data_alu_b_out,

   output [PC_OFFSET_WIDTH-1:0] pc_offset_out,
   output branch_inst_out,
   output branch_use_r_out,
   output jump_inst_out,
   output jump_use_r_out,

   output rd_inst_ena_out,
   output stall_out,
   output general_flush_out,
   output decode_flush_out
);











wire [REG_ADDR_WIDTH-1:0] reg_rd_addr1;
wire [REG_ADDR_WIDTH-1:0] reg_rd_addr2;
wire reg_rd_en1;
wire reg_rd_en2;


wire [IMEDIATE_WIDTH-1:0] immediate;














instruction_decoder
#(
   .INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
   .OPCODE_WIDTH(OPCODE_WIDTH),
   .FUNCTION_WIDTH(FUNCTION_WIDTH),
   .REG_ADDR_WIDTH(REG_ADDR_WIDTH),
   .IMEDIATE_WIDTH(IMEDIATE_WIDTH),
   .PC_OFFSET_WIDTH(PC_OFFSET_WIDTH)
)
instruction_decoder_u0
(
   .instruction_in(instruction_in),
   .opcode(opcode_out),
   .inst_function(inst_function_out),
   .reg_rd_addr1_out(reg_rd_addr1),
   .reg_rd_addr2_out(reg_rd_addr2),
   .reg_rd_en1_out(reg_rd_en1),
   .reg_rd_en2_out(reg_rd_en2),
   .reg_a_wr_addr_out(reg_a_wr_addr_out),
   .reg_b_wr_addr_out(reg_b_wr_addr_out),
   .reg_a_wr_en_out(reg_a_wr_en_out),
   .reg_b_wr_en_out(reg_b_wr_en_out),
   .immediate_out(immediate),
   .imm_inst_out(imm_inst_out),
   .pc_offset(pc_offset_out),
   .mem_data_wr_en_out(mem_data_wr_en_out),
   .mem_data_rd_en_out(mem_data_rd_en_out),
   .write_back_mux_sel_out(write_back_mux_sel_out),
   .branch_inst_out(branch_inst_out),
   .branch_use_r_out(branch_use_r_out),
   .jump_inst_out(jump_inst_out),
   .jump_use_r_out(jump_use_r_out)
);

assign reg_rd_addr1_out = reg_rd_addr1;
assign reg_rd_addr2_out = reg_rd_addr2;



register_bank
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDRESS_WIDTH(REG_ADDR_WIDTH)
)
register_bank_u0
(
   .clk(clk),
   .rst_n(rst_n),
   .en(en),
   .rd_reg1_addr(reg_rd_addr1),
   .rd_reg2_addr(reg_rd_addr2),



   .reg_a_wr_addr(reg_a_wr_addr_in),
   .reg_b_wr_addr(reg_b_wr_addr_in),
   .reg_a_wr_data(reg_a_wr_data_in),
   .reg_b_wr_data(reg_b_wr_data_in),
   .reg_a_wr_en(reg_a_wr_en_in),
   .reg_b_wr_en(reg_b_wr_en_in),

   .rd_reg1_data_out(data_alu_a_out),
   .rd_reg2_data_out(data_alu_b_out)
);





control
#(
   .REG_ADDR_WIDTH(REG_ADDR_WIDTH)
)
control_u0
(
   .id_ex_mem_data_rd_en(id_ex_mem_data_rd_en_in),
   .id_ex_reg_wr_addr(id_ex_reg_wr_addr_in),
   .if_id_rd_reg_a_en(reg_rd_en1),
   .if_id_rd_reg_b_en(reg_rd_en2),
   .if_id_rd_reg_a_addr(reg_rd_addr1),
   .if_id_rd_reg_b_addr(reg_rd_addr2),
   .select_new_pc(select_new_pc_in),

   .inst_rd_en(rd_inst_ena_out),
   .stall(stall_out),
   .general_flush(general_flush_out),
   .decode_flush(decode_flush_out)
);





signal_extend
#(
    .OUT_DATA_WIDTH(32),
    .IN_DATA_WIDTH(16)
)
signal_extend_u0
(
    .signal_in(immediate),
    .signal_out(constant_out)
);

































































endmodule
module instruction_decode
#(
   parameter PC_WIDTH = 20,
   parameter DATA_WIDTH = 32,
   parameter INSTRUCTION_WIDTH = 32,
   parameter REG_ADDR_WIDTH = 5,
   parameter OPCODE_WIDTH = 6,
   parameter FUNCTION_WIDTH = 6,
   parameter IMEDIATE_WIDTH = 16,
   parameter PC_OFFSET_WIDTH = 26
)
(
   input clk,
   input rst_n,
   input en,
   input [INSTRUCTION_WIDTH-1:0] instruction_in,

   
   input [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_in,
   input [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_in,
   input [DATA_WIDTH-1:0] reg_a_wr_data_in,
   input [DATA_WIDTH-1:0] reg_b_wr_data_in,
   input reg_a_wr_en_in,
   input reg_b_wr_en_in,





   input select_new_pc_in,

   input id_ex_mem_data_rd_en_in,
   input [REG_ADDR_WIDTH-1:0] id_ex_reg_wr_addr_in,



   output [REG_ADDR_WIDTH-1:0] reg_rd_addr1_out,
   output [REG_ADDR_WIDTH-1:0] reg_rd_addr2_out,

   output [OPCODE_WIDTH-1:0] opcode_out,
   output [FUNCTION_WIDTH-1:0] inst_function_out,
   output mem_data_rd_en_out,
   output mem_data_wr_en_out,
   output write_back_mux_sel_out,
   output [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_out,
   output [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_out,
   output reg_a_wr_en_out,
   output reg_b_wr_en_out,
   output [DATA_WIDTH-1:0] constant_out,
   output imm_inst_out,
   output [DATA_WIDTH-1:0] data_alu_a_out,
   output [DATA_WIDTH-1:0] data_alu_b_out,

   output [PC_OFFSET_WIDTH-1:0] pc_offset_out,
   output branch_inst_out,
   output branch_use_r_out,
   output jump_inst_out,
   output jump_use_r_out,

   output rd_inst_ena_out,
   output stall_out,
   output general_flush_out,
   output decode_flush_out
);












wire [REG_ADDR_WIDTH-1:0] reg_rd_addr1;
wire [REG_ADDR_WIDTH-1:0] reg_rd_addr2;
wire reg_rd_en1;
wire reg_rd_en2;


wire [IMEDIATE_WIDTH-1:0] immediate;














instruction_decoder
#(
   .INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
   .OPCODE_WIDTH(OPCODE_WIDTH),
   .FUNCTION_WIDTH(FUNCTION_WIDTH),
   .REG_ADDR_WIDTH(REG_ADDR_WIDTH),
   .IMEDIATE_WIDTH(IMEDIATE_WIDTH),
   .PC_OFFSET_WIDTH(PC_OFFSET_WIDTH)
)
instruction_decoder_u0
(
   .instruction_in(instruction_in),
   .opcode(opcode_out),
   .inst_function(inst_function_out),
   .reg_rd_addr1_out(reg_rd_addr1),
   .reg_rd_addr2_out(reg_rd_addr2),
   .reg_rd_en1_out(reg_rd_en1),
   .reg_rd_en2_out(reg_rd_en2),
   .reg_a_wr_addr_out(reg_a_wr_addr_out),
   .reg_b_wr_addr_out(reg_b_wr_addr_out),
   .reg_a_wr_en_out(reg_a_wr_en_out),
   .reg_b_wr_en_out(reg_b_wr_en_out),
   .immediate_out(immediate),
   .imm_inst_out(imm_inst_out),
   .pc_offset(pc_offset_out),
   .mem_data_wr_en_out(mem_data_wr_en_out),
   .mem_data_rd_en_out(mem_data_rd_en_out),
   .write_back_mux_sel_out(write_back_mux_sel_out),
   .branch_inst_out(branch_inst_out),
   .branch_use_r_out(branch_use_r_out),
   .jump_inst_out(jump_inst_out),
   .jump_use_r_out(jump_use_r_out)
);

assign reg_rd_addr1_out = reg_rd_addr1;
assign reg_rd_addr2_out = reg_rd_addr2;



register_bank
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDRESS_WIDTH(REG_ADDR_WIDTH)
)
register_bank_u0
(
   .clk(clk),
   .rst_n(rst_n),
   .en(en),
   .rd_reg1_addr(reg_rd_addr1),
   .rd_reg2_addr(reg_rd_addr2),



   .reg_a_wr_addr(reg_a_wr_addr_in),
   .reg_b_wr_addr(reg_b_wr_addr_in),
   .reg_a_wr_data(reg_a_wr_data_in),
   .reg_b_wr_data(reg_b_wr_data_in),
   .reg_a_wr_en(reg_a_wr_en_in),
   .reg_b_wr_en(reg_b_wr_en_in),

   .rd_reg1_data_out(data_alu_a_out),
   .rd_reg2_data_out(data_alu_b_out)
);





control
#(
   .REG_ADDR_WIDTH(REG_ADDR_WIDTH)
)
control_u0
(
   .id_ex_mem_data_rd_en(id_ex_mem_data_rd_en_in),
   .id_ex_reg_wr_addr(id_ex_reg_wr_addr_in),
   .if_id_rd_reg_a_en(reg_rd_en1),
   .if_id_rd_reg_b_en(reg_rd_en2),
   .if_id_rd_reg_a_addr(reg_rd_addr1),
   .if_id_rd_reg_b_addr(reg_rd_addr2),
   .select_new_pc(select_new_pc_in),

   .inst_rd_en(rd_inst_ena_out),
   .stall(stall_out),
   .general_flush(general_flush_out),
   .decode_flush(decode_flush_out)
);





signal_extend
#(
    .OUT_DATA_WIDTH(32),
    .IN_DATA_WIDTH(16)
)
signal_extend_u0
(
    .signal_in(immediate),
    .signal_out(constant_out)
);

































































endmodule