data/full_repos/permissive/160895047/Mux_2_1.v
data/verilator_xmls/f71d504a-c7ed-4d94-b705-06a0d7b75ea8.xml
module Mux_2_1(
	A, 
	B, 
	S,
	Q
);

input [31:0] A;
input [31:0] B;
input S;
output [31:0] Q;

wire [31:0] A;
wire [31:0] B;
wire S;
wire [31:0] Q;

assign Q = S ? B : A;
endmodule
module Mux_2_1(
	A, 
	B, 
	S,
	Q
);


input [31:0] A;
input [31:0] B;
input S;
output [31:0] Q;

wire [31:0] A;
wire [31:0] B;
wire S;
wire [31:0] Q;

assign Q = S ? B : A;
endmodule