data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v
 line:104: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_rst_01 = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_rst_01    = 1\'b0;         \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10   i_rst_01  = 1\'b1;       \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_rst_01    = 1\'b0;         \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #10   i_rst_01  = 1\'b1;       \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:107: Unsupported: Ignoring delay on this delayed statement.\n    always #2.5 i_clk_01 = ~i_clk_01;   \n           ^\n%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_datapath.v:110: Cannot find file containing module: \'datapath\'\n    datapath\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/datapath\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/datapath.v\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/datapath.sv\n             datapath\n             datapath.v\n             datapath.sv\n             obj_dir/datapath\n             obj_dir/datapath.v\n             obj_dir/datapath.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_datapath();
    		
    


    parameter NB_DATA_01    = 16;
    parameter NB_OPERAND_01 = 11;
    parameter NB_ADDR_01    = 11;
    parameter NB_OPCODE_01  = 5;
    
    

    reg                         i_clk_01;
    reg                         i_rst_01;
    reg [1:0]                   i_SelA_01;
    reg                         i_SelB_01;
    reg                         i_WrAcc_01;
    reg                         i_op_01;
    reg [NB_OPERAND_01-1:0]     i_operand_01;
    reg [NB_DATA_01-1:0]        i_data_memory_01;                      
    

    wire [NB_ADDR_01-1:0]       o_addr_01;
    wire [NB_DATA_01-1:0]       o_data_memory_01;
    
    
    initial    begin
    #1
    i_clk_01    = 0;
    i_SelA_01   = 2'b00;
    i_SelB_01   = 1'b0;
    i_op_01     = 1'b0;
    i_WrAcc_01  = 1'b0;
    i_operand_01        = 0;
    i_data_memory_01    = 0;
    
    i_rst_01    = 1'b0;
    
    #10 i_rst_01 = 1'b1;




    #10 i_rst_01    = 1'b0;
    #10   i_rst_01  = 1'b1;
    
    

    #100
    i_SelA_01   = 2'b01;
    i_SelB_01   = 1'b0;
    i_WrAcc_01  = 1'b1;
    i_op_01     = 1'b1;
    i_operand_01        = 1;
    i_data_memory_01    = 2;
    
    
    

    #100
    i_SelA_01   = 2'b10;
    i_SelB_01   = 1'b0;
    i_op_01     = 1'b0;
    i_WrAcc_01  = 1'b1;
    i_operand_01        = 3;
    i_data_memory_01    = 4;
    
    

    #100
    i_SelA_01   = 2'b10;
    i_SelB_01   = 1'b1;
    i_op_01     = 1'b0;
    i_WrAcc_01  = 1'b1;
    i_operand_01        = 5;
    i_data_memory_01    = 6;
    
    

    #100
    i_SelA_01   = 2'b10;
    i_SelB_01   = 1'b0;
    i_op_01     = 1'b1;
    i_WrAcc_01  = 1'b1;
    i_operand_01        = 7;
    i_data_memory_01    = 8;
    

    #100
    i_SelA_01   = 2'b00;
    i_SelB_01   = 1'b1;
    i_op_01     = 1'b1;
    i_WrAcc_01  = 1'b1;
    i_operand_01        = 9;
    i_data_memory_01    = 10;
    

    #10 i_rst_01    = 1'b0;
    #10   i_rst_01  = 1'b1;
    
    
    #10 $finish;
    end
    
    always #2.5 i_clk_01 = ~i_clk_01;
    

    datapath
    #(
    .NB_DATA    (NB_DATA_01),
    .NB_OPERAND (NB_OPERAND_01),
    .NB_ADDR    (NB_ADDR_01),
    .NB_OPCODE  (NB_OPCODE_01)
    
    )
    u_datapath_01
    (
    .i_clk          (i_clk_01),
    .i_rst          (i_rst_01),
    .i_SelA         (i_SelA_01),
    .i_SelB         (i_SelB_01),
    .i_WrAcc        (i_WrAcc_01),
    .i_op           (i_op_01),
    .i_operand      (i_operand_01),
    .i_data_memory  (i_data_memory_01),
    .o_addr         (o_addr_01),
    .o_data_memory  (o_data_memory_01)            
    );
    
endmodule
module tb_datapath();

    		
    


    parameter NB_DATA_01    = 16;
    parameter NB_OPERAND_01 = 11;
    parameter NB_ADDR_01    = 11;
    parameter NB_OPCODE_01  = 5;
    
    

    reg                         i_clk_01;
    reg                         i_rst_01;
    reg [1:0]                   i_SelA_01;
    reg                         i_SelB_01;
    reg                         i_WrAcc_01;
    reg                         i_op_01;
    reg [NB_OPERAND_01-1:0]     i_operand_01;
    reg [NB_DATA_01-1:0]        i_data_memory_01;                      
    

    wire [NB_ADDR_01-1:0]       o_addr_01;
    wire [NB_DATA_01-1:0]       o_data_memory_01;
    
    
    initial    begin
    #1
    i_clk_01    = 0;
    i_SelA_01   = 2'b00;
    i_SelB_01   = 1'b0;
    i_op_01     = 1'b0;
    i_WrAcc_01  = 1'b0;
    i_operand_01        = 0;
    i_data_memory_01    = 0;
    
    i_rst_01    = 1'b0;
    
    #10 i_rst_01 = 1'b1;




    #10 i_rst_01    = 1'b0;
    #10   i_rst_01  = 1'b1;
    
    

    #100
    i_SelA_01   = 2'b01;
    i_SelB_01   = 1'b0;
    i_WrAcc_01  = 1'b1;
    i_op_01     = 1'b1;
    i_operand_01        = 1;
    i_data_memory_01    = 2;
    
    
    

    #100
    i_SelA_01   = 2'b10;
    i_SelB_01   = 1'b0;
    i_op_01     = 1'b0;
    i_WrAcc_01  = 1'b1;
    i_operand_01        = 3;
    i_data_memory_01    = 4;
    
    

    #100
    i_SelA_01   = 2'b10;
    i_SelB_01   = 1'b1;
    i_op_01     = 1'b0;
    i_WrAcc_01  = 1'b1;
    i_operand_01        = 5;
    i_data_memory_01    = 6;
    
    

    #100
    i_SelA_01   = 2'b10;
    i_SelB_01   = 1'b0;
    i_op_01     = 1'b1;
    i_WrAcc_01  = 1'b1;
    i_operand_01        = 7;
    i_data_memory_01    = 8;
    

    #100
    i_SelA_01   = 2'b00;
    i_SelB_01   = 1'b1;
    i_op_01     = 1'b1;
    i_WrAcc_01  = 1'b1;
    i_operand_01        = 9;
    i_data_memory_01    = 10;
    

    #10 i_rst_01    = 1'b0;
    #10   i_rst_01  = 1'b1;
    
    
    #10 $finish;
    end
    
    always #2.5 i_clk_01 = ~i_clk_01;
    

    datapath
    #(
    .NB_DATA    (NB_DATA_01),
    .NB_OPERAND (NB_OPERAND_01),
    .NB_ADDR    (NB_ADDR_01),
    .NB_OPCODE  (NB_OPCODE_01)
    
    )
    u_datapath_01
    (
    .i_clk          (i_clk_01),
    .i_rst          (i_rst_01),
    .i_SelA         (i_SelA_01),
    .i_SelB         (i_SelB_01),
    .i_WrAcc        (i_WrAcc_01),
    .i_op           (i_op_01),
    .i_operand      (i_operand_01),
    .i_data_memory  (i_data_memory_01),
    .o_addr         (o_addr_01),
    .o_data_memory  (o_data_memory_01)            
    );
    
endmodule