data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v
1: b'%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:3: Cannot find include file: ../define/global_def.v\n`include "../define/global_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147520230/src/cpu/utility,data/full_repos/permissive/147520230/../define/global_def.v\n             data/full_repos/permissive/147520230/src/cpu/utility,data/full_repos/permissive/147520230/../define/global_def.v.v\n             data/full_repos/permissive/147520230/src/cpu/utility,data/full_repos/permissive/147520230/../define/global_def.v.sv\n             ../define/global_def.v\n             ../define/global_def.v.v\n             ../define/global_def.v.sv\n             obj_dir/../define/global_def.v\n             obj_dir/../define/global_def.v.v\n             obj_dir/../define/global_def.v.sv\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:14: Define or directive not defined: \'`ADDR_BUS\'\n    input   wire[`ADDR_BUS] addr,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`ADDR_BUS] addr,\n                          ^\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:15: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS] write_data,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:18: Define or directive not defined: \'`DATA_BUS\'\n    output  reg [`DATA_BUS] read_data\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:21: Define or directive not defined: \'`BYTE_BUS\'\n    reg [`BYTE_BUS] data_mem0[`DATA_MEM_BUS];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`BYTE_BUS] data_mem0[`DATA_MEM_BUS];\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:21: Define or directive not defined: \'`DATA_MEM_BUS\'\n    reg [`BYTE_BUS] data_mem0[`DATA_MEM_BUS];\n                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:22: Define or directive not defined: \'`BYTE_BUS\'\n    reg [`BYTE_BUS] data_mem1[`DATA_MEM_BUS];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`BYTE_BUS] data_mem1[`DATA_MEM_BUS];\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:22: Define or directive not defined: \'`DATA_MEM_BUS\'\n    reg [`BYTE_BUS] data_mem1[`DATA_MEM_BUS];\n                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:23: Define or directive not defined: \'`BYTE_BUS\'\n    reg [`BYTE_BUS] data_mem2[`DATA_MEM_BUS];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`BYTE_BUS] data_mem2[`DATA_MEM_BUS];\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:23: Define or directive not defined: \'`DATA_MEM_BUS\'\n    reg [`BYTE_BUS] data_mem2[`DATA_MEM_BUS];\n                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:24: Define or directive not defined: \'`BYTE_BUS\'\n    reg [`BYTE_BUS] data_mem3[`DATA_MEM_BUS];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`BYTE_BUS] data_mem3[`DATA_MEM_BUS];\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:24: Define or directive not defined: \'`DATA_MEM_BUS\'\n    reg [`BYTE_BUS] data_mem3[`DATA_MEM_BUS];\n                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:28: Define or directive not defined: \'`CHIP_DISABLE\'\n        if (ram_en == `CHIP_DISABLE)    begin\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:29: Define or directive not defined: \'`WRITE_ENABLE\'\n        end else if (write_en == `WRITE_ENABLE) begin\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:30: Define or directive not defined: \'`DATA_MEM_NUM_LOG2\'\n            if (write_sel[3])   data_mem3[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[31:24];\n                                               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:31: Define or directive not defined: \'`DATA_MEM_NUM_LOG2\'\n            if (write_sel[2])   data_mem2[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[23:16];\n                                               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:32: Define or directive not defined: \'`DATA_MEM_NUM_LOG2\'\n            if (write_sel[1])   data_mem1[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[15: 8];\n                                               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:33: Define or directive not defined: \'`DATA_MEM_NUM_LOG2\'\n            if (write_sel[0])   data_mem0[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[ 7: 0];\n                                               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:39: Define or directive not defined: \'`CHIP_DISABLE\'\n        if (ram_en == `CHIP_DISABLE)    \n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:40: Define or directive not defined: \'`ZERO_WORD\'\n            read_data   <= `ZERO_WORD;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:41: Define or directive not defined: \'`WRITE_DISABLE\'\n        else if (write_en == `WRITE_DISABLE)\n                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:42: Define or directive not defined: \'`DATA_MEM_NUM_LOG2\'\n            read_data   <= {data_mem3[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]],\n                                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:43: Define or directive not defined: \'`DATA_MEM_NUM_LOG2\'\n                            data_mem2[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]], \n                                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:44: Define or directive not defined: \'`DATA_MEM_NUM_LOG2\'\n                            data_mem1[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]],\n                                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:45: Define or directive not defined: \'`DATA_MEM_NUM_LOG2\'\n                            data_mem0[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]]};\n                                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/utility/data_ram.v:47: Define or directive not defined: \'`ZERO_WORD\'\n            read_data   <= `ZERO_WORD;\n                           ^~~~~~~~~~\n%Error: Exiting due to 31 error(s)\n'
module  data_ram(
    input   wire            clk,
    input   wire            rst,

    input   wire            ram_en,


    input   wire            write_en,
    input   wire[3:0]       write_sel,
    input   wire[`ADDR_BUS] addr,
    input   wire[`DATA_BUS] write_data,


    output  reg [`DATA_BUS] read_data
);

    reg [`BYTE_BUS] data_mem0[`DATA_MEM_BUS];
    reg [`BYTE_BUS] data_mem1[`DATA_MEM_BUS];
    reg [`BYTE_BUS] data_mem2[`DATA_MEM_BUS];
    reg [`BYTE_BUS] data_mem3[`DATA_MEM_BUS];


    always @ (posedge clk)  begin
        if (ram_en == `CHIP_DISABLE)    begin
        end else if (write_en == `WRITE_ENABLE) begin
            if (write_sel[3])   data_mem3[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[31:24];
            if (write_sel[2])   data_mem2[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[23:16];
            if (write_sel[1])   data_mem1[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[15: 8];
            if (write_sel[0])   data_mem0[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[ 7: 0];
        end
    end


    always @ (*)    begin
        if (ram_en == `CHIP_DISABLE)    
            read_data   <= `ZERO_WORD;
        else if (write_en == `WRITE_DISABLE)
            read_data   <= {data_mem3[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]],
                            data_mem2[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]], 
                            data_mem1[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]],
                            data_mem0[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]]};
        else
            read_data   <= `ZERO_WORD;
    end

endmodule
module  data_ram(
    input   wire            clk,
    input   wire            rst,

    input   wire            ram_en,


    input   wire            write_en,
    input   wire[3:0]       write_sel,
    input   wire[`ADDR_BUS] addr,
    input   wire[`DATA_BUS] write_data,


    output  reg [`DATA_BUS] read_data
);


    reg [`BYTE_BUS] data_mem0[`DATA_MEM_BUS];
    reg [`BYTE_BUS] data_mem1[`DATA_MEM_BUS];
    reg [`BYTE_BUS] data_mem2[`DATA_MEM_BUS];
    reg [`BYTE_BUS] data_mem3[`DATA_MEM_BUS];


    always @ (posedge clk)  begin
        if (ram_en == `CHIP_DISABLE)    begin
        end else if (write_en == `WRITE_ENABLE) begin
            if (write_sel[3])   data_mem3[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[31:24];
            if (write_sel[2])   data_mem2[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[23:16];
            if (write_sel[1])   data_mem1[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[15: 8];
            if (write_sel[0])   data_mem0[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]] <= write_data[ 7: 0];
        end
    end


    always @ (*)    begin
        if (ram_en == `CHIP_DISABLE)    
            read_data   <= `ZERO_WORD;
        else if (write_en == `WRITE_DISABLE)
            read_data   <= {data_mem3[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]],
                            data_mem2[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]], 
                            data_mem1[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]],
                            data_mem0[addr[`DATA_MEM_NUM_LOG2 + 1 : 2]]};
        else
            read_data   <= `ZERO_WORD;
    end

endmodule