data/full_repos/permissive/130234582/assignment_002/SRAM.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/130234582/assignment_002/SRAM.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1 mem[wr_addr] = wr_din;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SRAM
#(
  parameter WIDTH=8,
  parameter DEPTH=16,
  parameter ADDR_WIDTH=4
  )
(
  input [ADDR_WIDTH-1:0]  rd_addr,
  input                   rd_en,
  output [WIDTH-1:0]      rd_dout,
  
  input [ADDR_WIDTH-1:0]  wr_addr,
  input                   wr_en,
  input [WIDTH-1:0]       wr_din
);

reg [WIDTH-1:0] mem[DEPTH-1:0];
wire [WIDTH-1:0] rd_out;

assign rd_out = ~rd_en ? {WIDTH{1'bx}} : mem[rd_addr];
assign #1 rd_dout = rd_out;

always @(*) begin
  if(wr_en)
    #1 mem[wr_addr] = wr_din;
end

endmodule
module SRAM
#(
  parameter WIDTH=8,
  parameter DEPTH=16,
  parameter ADDR_WIDTH=4
  )
(
  input [ADDR_WIDTH-1:0]  rd_addr,
  input                   rd_en,
  output [WIDTH-1:0]      rd_dout,
  
  input [ADDR_WIDTH-1:0]  wr_addr,
  input                   wr_en,
  input [WIDTH-1:0]       wr_din
);


reg [WIDTH-1:0] mem[DEPTH-1:0];
wire [WIDTH-1:0] rd_out;

assign rd_out = ~rd_en ? {WIDTH{1'bx}} : mem[rd_addr];
assign #1 rd_dout = rd_out;

always @(*) begin
  if(wr_en)
    #1 mem[wr_addr] = wr_din;
end

endmodule