data/full_repos/permissive/181665138/verilog/capitolo_iii/Latch_SR.v
data/verilator_xmls/ce667142-42b7-46f2-95d4-69004f98c182.xml
module Latch_SR(q, qN, s, r);
    input s, r;
    output q, qN;

    assign #1 q = ~(r|qN);
    assign #1 qN = ~(s|q);
endmodule
module Latch_SR(q, qN, s, r);

    input s, r;
    output q, qN;

    assign #1 q = ~(r|qN);
    assign #1 qN = ~(s|q);
endmodule