data/full_repos/permissive/171075078/ve/sdram_master_bfm/tb/sdram_master_bfm_tb_hdl.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/171075078/ve/sdram_master_bfm/tb/sdram_master_bfm_tb_hdl.sv:4: Cannot find include file: sdram_macros.svh\n`include "sdram_macros.svh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171075078/ve/sdram_master_bfm/tb,data/full_repos/permissive/171075078/sdram_macros.svh\n             data/full_repos/permissive/171075078/ve/sdram_master_bfm/tb,data/full_repos/permissive/171075078/sdram_macros.svh.v\n             data/full_repos/permissive/171075078/ve/sdram_master_bfm/tb,data/full_repos/permissive/171075078/sdram_macros.svh.sv\n             sdram_macros.svh\n             sdram_macros.svh.v\n             sdram_macros.svh.sv\n             obj_dir/sdram_macros.svh\n             obj_dir/sdram_macros.svh.v\n             obj_dir/sdram_macros.svh.sv\n%Error: data/full_repos/permissive/171075078/ve/sdram_master_bfm/tb/sdram_master_bfm_tb_hdl.sv:32: Define or directive not defined: \'`SDRAM_WIRES\'\n `SDRAM_WIRES(bfm2dut_, 11, 16, 2);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/171075078/ve/sdram_master_bfm/tb/sdram_master_bfm_tb_hdl.sv:32: syntax error, unexpected \'(\'\n `SDRAM_WIRES(bfm2dut_, 11, 16, 2);\n              ^~~~~~~~\n%Error: data/full_repos/permissive/171075078/ve/sdram_master_bfm/tb/sdram_master_bfm_tb_hdl.sv:41: Define or directive not defined: \'`SDRAM_CONNECT\'\n   `SDRAM_CONNECT(, bfm2dut_)\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171075078/ve/sdram_master_bfm/tb/sdram_master_bfm_tb_hdl.sv:41: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   `SDRAM_CONNECT(, bfm2dut_)\n                  ^\n%Error: Exiting due to 5 error(s)\n'
module sdram_master_bfm_tb_hdl(input clock);

`ifdef HAVE_HDL_CLKGEN
	reg clk_r = 0;

	initial begin
		forever begin
			#10ns;
			clk_r <= ~clk_r;
		end
	end

	assign clock = clk_r;
`endif

	reg reset = 1;
	reg [7:0] reset_cnt = 0;

	always @(posedge clock) begin
		if (reset_cnt == 10) begin
			reset <= 0;
		end else begin
			reset_cnt <= reset_cnt + 1;
		end
	end
	
	`SDRAM_WIRES(bfm2dut_, 11, 16, 2);

	sdram_master_bfm #(
		.DATA_WIDTH     (16    ), 
		.ADDR_WIDTH     (11    ), 
		.BANKSEL_WIDTH  (2 )
		) u_bfm (
			.clock		(clock			),
			.reset		(reset			),
			`SDRAM_CONNECT(, bfm2dut_)
		);

	mt48lc16m16a2 #(
			.addr_bits(11)
		) u_dut (
		.Dq     (bfm2dut_dq    ), 
		.Addr   (bfm2dut_addr  ), 
		.Ba     (bfm2dut_bs    ), 
		.Clk    (clock         ), 
		.Cke    (bfm2dut_cke   ), 
		.Cs_n   (bfm2dut_cs_n  ), 
		.Ras_n  (bfm2dut_ras_n ), 
		.Cas_n  (bfm2dut_cas_n ), 
		.We_n   (bfm2dut_we_n  ), 
		.Dqm    (bfm2dut_dqm   ));
	
endmodule
module sdram_master_bfm_tb_hdl(input clock);


`ifdef HAVE_HDL_CLKGEN
	reg clk_r = 0;

	initial begin
		forever begin
			#10ns;
			clk_r <= ~clk_r;
		end
	end

	assign clock = clk_r;
`endif

	reg reset = 1;
	reg [7:0] reset_cnt = 0;

	always @(posedge clock) begin
		if (reset_cnt == 10) begin
			reset <= 0;
		end else begin
			reset_cnt <= reset_cnt + 1;
		end
	end
	
	`SDRAM_WIRES(bfm2dut_, 11, 16, 2);

	sdram_master_bfm #(
		.DATA_WIDTH     (16    ), 
		.ADDR_WIDTH     (11    ), 
		.BANKSEL_WIDTH  (2 )
		) u_bfm (
			.clock		(clock			),
			.reset		(reset			),
			`SDRAM_CONNECT(, bfm2dut_)
		);

	mt48lc16m16a2 #(
			.addr_bits(11)
		) u_dut (
		.Dq     (bfm2dut_dq    ), 
		.Addr   (bfm2dut_addr  ), 
		.Ba     (bfm2dut_bs    ), 
		.Clk    (clock         ), 
		.Cke    (bfm2dut_cke   ), 
		.Cs_n   (bfm2dut_cs_n  ), 
		.Ras_n  (bfm2dut_ras_n ), 
		.Cas_n  (bfm2dut_cas_n ), 
		.We_n   (bfm2dut_we_n  ), 
		.Dqm    (bfm2dut_dqm   ));
	
endmodule