data/full_repos/permissive/119913252/parity_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119913252/parity_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #5   ctr = ctr + 1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/119913252/parity_tb.v:15: Cannot find file containing module: \'parity\'\nparity instance1 (a,b,c,d,e,f,g,out_test);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119913252,data/full_repos/permissive/119913252/parity\n             data/full_repos/permissive/119913252,data/full_repos/permissive/119913252/parity.v\n             data/full_repos/permissive/119913252,data/full_repos/permissive/119913252/parity.sv\n             parity\n             parity.v\n             parity.sv\n             obj_dir/parity\n             obj_dir/parity.v\n             obj_dir/parity.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module parity_tb;
   reg  [6:0]  ctr;
   wire   a,b,c,d,e,f,g;
   wire   out_test;
   

parity instance1 (a,b,c,d,e,f,g,out_test);

initial
  begin        
     ctr = 7'b0;
  end

always
   #5   ctr = ctr + 1;
  
assign a = ctr[6];
assign b = ctr[5];
assign c = ctr[4];
assign d = ctr[3];
assign e = ctr[2];
assign f = ctr[1];
assign g = ctr[0];


endmodule
module parity_tb;

   reg  [6:0]  ctr;
   wire   a,b,c,d,e,f,g;
   wire   out_test;
   

parity instance1 (a,b,c,d,e,f,g,out_test);

initial
  begin        
     ctr = 7'b0;
  end

always
   #5   ctr = ctr + 1;
  
assign a = ctr[6];
assign b = ctr[5];
assign c = ctr[4];
assign d = ctr[3];
assign e = ctr[2];
assign f = ctr[1];
assign g = ctr[0];


endmodule