data/full_repos/permissive/123690745/TC.v
'utf-8' codec can't decode byte 0xa1 in position 702: invalid start byte
data/verilator_xmls/3f682b01-3599-40a0-8d1c-cf6cf7cbea43.xml
module TC(
    input clk,
    input reset,
    input [3:2] PrAddr,
    input WE,
    input [31:0] DataIn,
    output [31:0] DataOut,
    output InterruptRequest
    );






	
	reg [31:0] Ctrl = 0;
	reg [31:0] Preset = 0;
	reg [31:0] Count = 0;
	reg [15:0] Stage = 0;
	reg idle = 0;
	
	wire Interruptable;
	reg Interrupt = 0;
	wire [1:0] Mode;
	wire AllowCount;

	
	assign Interruptable = Ctrl[3];
	assign Mode = Ctrl[2:1];
	assign AllowCount = Ctrl[0];
	
	assign InterruptRequest = Interruptable && Count == 0;
	
	assign DataOut = (PrAddr == 0) ? Ctrl :
						  (PrAddr == 1) ? Preset :
						  (PrAddr == 2) ? Count :
						  32'hdead2333;
						  


	
	 always @(posedge clk)
		if (reset)
		begin
			Ctrl <= 0;
			Preset <= 0;
			Count <= 0;
			Stage <= 0;
		end
		else 
		begin
			if (Stage == 0) begin
				if (Preset >= 1 & Ctrl[0] ) begin
					Count <= Preset;
					Stage <= 1;
				end
			end
			if (Stage == 1) begin
				if (Ctrl[0]) begin
					if (Count >= 1) 
						Count <= Count - 1;
					else begin
						if (Ctrl[2:1] == 0) begin
							Stage <= 0;
							Ctrl[0] <= 0;
						end
						if (Ctrl[2:1] == 1) begin
							Count <= Preset;
						end						
					end
				end
			end
			if (WE == 1) begin
				if (PrAddr == 0) begin 
					Ctrl[3:0] <= DataIn[3:0];
					Count <= Preset;
					Stage <= 1;
				end
				if (PrAddr == 1) Preset <= DataIn;
				if (PrAddr == 2) Count <= DataIn;
			end
		end
endmodule
module TC(
    input clk,
    input reset,
    input [3:2] PrAddr,
    input WE,
    input [31:0] DataIn,
    output [31:0] DataOut,
    output InterruptRequest
    );







	
	reg [31:0] Ctrl = 0;
	reg [31:0] Preset = 0;
	reg [31:0] Count = 0;
	reg [15:0] Stage = 0;
	reg idle = 0;
	
	wire Interruptable;
	reg Interrupt = 0;
	wire [1:0] Mode;
	wire AllowCount;

	
	assign Interruptable = Ctrl[3];
	assign Mode = Ctrl[2:1];
	assign AllowCount = Ctrl[0];
	
	assign InterruptRequest = Interruptable && Count == 0;
	
	assign DataOut = (PrAddr == 0) ? Ctrl :
						  (PrAddr == 1) ? Preset :
						  (PrAddr == 2) ? Count :
						  32'hdead2333;
						  


	
	 always @(posedge clk)
		if (reset)
		begin
			Ctrl <= 0;
			Preset <= 0;
			Count <= 0;
			Stage <= 0;
		end
		else 
		begin
			if (Stage == 0) begin
				if (Preset >= 1 & Ctrl[0] ) begin
					Count <= Preset;
					Stage <= 1;
				end
			end
			if (Stage == 1) begin
				if (Ctrl[0]) begin
					if (Count >= 1) 
						Count <= Count - 1;
					else begin
						if (Ctrl[2:1] == 0) begin
							Stage <= 0;
							Ctrl[0] <= 0;
						end
						if (Ctrl[2:1] == 1) begin
							Count <= Preset;
						end						
					end
				end
			end
			if (WE == 1) begin
				if (PrAddr == 0) begin 
					Ctrl[3:0] <= DataIn[3:0];
					Count <= Preset;
					Stage <= 1;
				end
				if (PrAddr == 1) Preset <= DataIn;
				if (PrAddr == 2) Count <= DataIn;
			end
		end
endmodule