data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:288: Unsupported: Ignoring delay on this delayed statement.\n  #5     key[0] = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:289: Unsupported: Ignoring delay on this delayed statement.\n  #12000 key[0] = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:293: Unsupported: Ignoring delay on this delayed statement.\n  #20 clk50 = ~clk50;\n  ^\n%Error: data/full_repos/permissive/101171422/de2-115/vgadla/vgadla.v:294: Unsupported or unknown PLI call: $monitor\n  $monitor("t %d st %d we %d dq %d da %d s %d xw %d yw %d xr %x yr %x",\n  ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vgadla_test();
	reg        clk50;
	reg [3:0]  key;
	reg [17:0] sw;
	
	wire [15:0]  sram_dq;
	wire [19:0]  sram_addr;
	wire         sram_ub_n;
	wire         sram_lb_n;
	wire         sram_we_n;
	wire         sram_ce_n;
	wire         sram_oe_n;
	
	wire       vga_clk;
	wire       vga_hs;
	wire       vga_vs;
	wire       vga_blank;
	wire       vga_sync;
	wire [7:0] vga_r;
	wire [7:0] vga_g;
	wire [7:0] vga_b;
	
	wire [8:0]  ledg;
	wire [17:0] ledr;
	
	initial begin
		clk50 = 0;
		key = 'hf;
		sw = 0;

		#5     key[0] = 0;
		#12000 key[0] = 1;
	end
	
	always begin
		#20 clk50 = ~clk50;
		$monitor("t %d st %d we %d dq %d da %d s %d xw %d yw %d xr %x yr %x",
			$time, v.state, v.we, v.sram_dq, v.data, v.sum, v.xw, v.yw, v.xr, v.yr);
	end
	
	vgadla v(
		.clk50(clk50),
		.key(key),
		.sw(sw),
		.sram_dq(sram_dq),
		.sram_addr(sram_addr),
		.sram_ub_n(sram_ub_n),
		.sram_lb_n(sram_lb_n),
		.sram_we_n(sram_we_n),
		.sram_ce_n(sram_ce_n),
		.sram_oe_n(sram_oe_n),
		.vga_clk(vga_clk),
		.vga_hs(vga_hs),
		.vga_vs(vga_vs),
		.vga_blank(vga_blank),
		.vga_sync(vga_sync),
		.vga_r(vga_r),
		.vga_g(vga_g),
		.vga_b(vga_b),
		.ledg(ledg),
		.ledr(ledr)
	);
endmodule
module vgadla_test();

	reg        clk50;
	reg [3:0]  key;
	reg [17:0] sw;
	
	wire [15:0]  sram_dq;
	wire [19:0]  sram_addr;
	wire         sram_ub_n;
	wire         sram_lb_n;
	wire         sram_we_n;
	wire         sram_ce_n;
	wire         sram_oe_n;
	
	wire       vga_clk;
	wire       vga_hs;
	wire       vga_vs;
	wire       vga_blank;
	wire       vga_sync;
	wire [7:0] vga_r;
	wire [7:0] vga_g;
	wire [7:0] vga_b;
	
	wire [8:0]  ledg;
	wire [17:0] ledr;
	
	initial begin
		clk50 = 0;
		key = 'hf;
		sw = 0;

		#5     key[0] = 0;
		#12000 key[0] = 1;
	end
	
	always begin
		#20 clk50 = ~clk50;
		$monitor("t %d st %d we %d dq %d da %d s %d xw %d yw %d xr %x yr %x",
			$time, v.state, v.we, v.sram_dq, v.data, v.sum, v.xw, v.yw, v.xr, v.yr);
	end
	
	vgadla v(
		.clk50(clk50),
		.key(key),
		.sw(sw),
		.sram_dq(sram_dq),
		.sram_addr(sram_addr),
		.sram_ub_n(sram_ub_n),
		.sram_lb_n(sram_lb_n),
		.sram_we_n(sram_we_n),
		.sram_ce_n(sram_ce_n),
		.sram_oe_n(sram_oe_n),
		.vga_clk(vga_clk),
		.vga_hs(vga_hs),
		.vga_vs(vga_vs),
		.vga_blank(vga_blank),
		.vga_sync(vga_sync),
		.vga_r(vga_r),
		.vga_g(vga_g),
		.vga_b(vga_b),
		.ledg(ledg),
		.ledr(ledr)
	);
endmodule