data/full_repos/permissive/188580251/Project5/PC.v
data/verilator_xmls/75574c49-d06b-44a6-a0e8-2dcf5acb3463.xml
module PC(
    input Clock,
	 input Reset,
	 input Stop,
	 input [31:0] NextPC,
    output reg [31:0] PC
    );
	 
	initial begin
		PC = 32'h0000_3000;
	end

	always @ (posedge Clock) begin
		if(Reset == 1)
			PC = 32'h0000_3000;
		else if(Stop == 1)
			PC = PC;
		else
			PC = NextPC;
	end

endmodule
module PC(
    input Clock,
	 input Reset,
	 input Stop,
	 input [31:0] NextPC,
    output reg [31:0] PC
    );

	 
	initial begin
		PC = 32'h0000_3000;
	end

	always @ (posedge Clock) begin
		if(Reset == 1)
			PC = 32'h0000_3000;
		else if(Stop == 1)
			PC = PC;
		else
			PC = NextPC;
	end

endmodule