data/full_repos/permissive/110151336/lab_05/src/06_alu/common/alu.v
data/verilator_xmls/a111c935-462f-4c85-855f-2296c62b66ff.xml
module alu
#(
    parameter WIDTH = 4,
    parameter SHIFT = 2
)
(
    input      [WIDTH - 1:0] x, y,
    input      [SHIFT - 1:0] shamt,
    input      [ 1:0]        operation,
    output                   zero,
    output reg [WIDTH - 1:0] result
);

    always @ (*) begin
        case (operation)
            `ALU_AND : result = x & y; 
            `ALU_ADD : result = x + y;
            `ALU_SLL : result = y << shamt;
            `ALU_SLT : result = (x < y) ? 1 : 0;
        endcase
    end


    assign zero      = (result == 0);

endmodule
module alu
#(
    parameter WIDTH = 4,
    parameter SHIFT = 2
)
(
    input      [WIDTH - 1:0] x, y,
    input      [SHIFT - 1:0] shamt,
    input      [ 1:0]        operation,
    output                   zero,
    output reg [WIDTH - 1:0] result
);


    always @ (*) begin
        case (operation)
            `ALU_AND : result = x & y; 
            `ALU_ADD : result = x + y;
            `ALU_SLL : result = y << shamt;
            `ALU_SLT : result = (x < y) ? 1 : 0;
        endcase
    end


    assign zero      = (result == 0);

endmodule