data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v
 line:97: before: "("
1: b'%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:86: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, perceptron_top, uart);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\nalways #(clk_pulse_width/2) clk = !clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:94: Unsupported or unknown PLI call: $monitor\n $monitor("Time %d", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:97: syntax error, unexpected \'@\'\n repeat (5) @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:108: Unsupported: wait statements\n wait( rst_n );\n ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:109: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:118: syntax error, unexpected \'@\'\n repeat (2) @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:122: Unsupported: wait statements\n  wait (uart_new_value);  \n  ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:124: syntax error, unexpected \'@\'\n  repeat (2) @(negedge clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[0] != OP_READ_RESPONSE) begin $display(" ASSERT FAILED: %s", "Operation CODE not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[1] != 0 || packet_readings[2] != 0) begin $display(" ASSERT FAILED: %s", "Weight 1 not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[3] != 0 || packet_readings[4] != 0) begin $display(" ASSERT FAILED: %s", "Weight 2 not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[5] != 8\'h10 || packet_readings[6] != 0) begin $display(" ASSERT FAILED: %s", "Result not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                        ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:137: syntax error, unexpected \'@\'\n repeat (5000) @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:152: Unsupported: wait statements\n  wait(uart_tx_busy);\n  ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:154: Unsupported: wait statements\n  wait(!uart_tx_busy);\n  ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:159: Unsupported: wait statements\n wait (uart_new_value);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n if(uart_received_data != OP_WRITE_RESPONSE_OK) begin $display(" ASSERT FAILED: %s", "Confirmation CODE not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                       ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:164: syntax error, unexpected \'@\'\n repeat (5000) @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:172: syntax error, unexpected \'@\'\n repeat (2) @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:176: Unsupported: wait statements\n  wait (uart_new_value);  \n  ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:178: syntax error, unexpected \'@\'\n  repeat (2) @(negedge clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[0] != OP_READ_RESPONSE) begin $display(" ASSERT FAILED: %s", "Operation CODE not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[1] != packet_weights[1] || packet_readings[2] != packet_weights[2]) begin $display(" ASSERT FAILED: %s", "Weight 1 not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[3] != packet_weights[3] || packet_readings[4] != packet_weights[4]) begin $display(" ASSERT FAILED: %s", "Weight 2 not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:187: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[5] != 8\'h10 || packet_readings[6] != 0) begin $display(" ASSERT FAILED: %s", "Result not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                        ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:203: Unsupported: wait statements\n  wait(uart_tx_busy);\n  ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:205: Unsupported: wait statements\n  wait(!uart_tx_busy);\n  ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:210: Unsupported: wait statements\n wait (uart_new_value);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n if(uart_received_data != OP_WRITE_RESPONSE_OK) begin $display(" ASSERT FAILED: %s", "Confirmation CODE not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                       ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:215: syntax error, unexpected \'@\'\n repeat (5000) @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:223: syntax error, unexpected \'@\'\n repeat (2) @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:227: Unsupported: wait statements\n  wait (uart_new_value);  \n  ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:229: syntax error, unexpected \'@\'\n  repeat (2) @(negedge clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[0] != OP_READ_RESPONSE) begin $display(" ASSERT FAILED: %s", "Operation CODE not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[1] != packet_weights[1] || packet_readings[2] != packet_weights[2]) begin $display(" ASSERT FAILED: %s", "Weight 1 not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[3] != packet_weights[3] || packet_readings[4] != packet_weights[4]) begin $display(" ASSERT FAILED: %s", "Weight 2 not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_top_16b_tb.v:238: Unsupported: Ignoring delay on this delayed statement.\n if(packet_readings[5] != 0 || packet_readings[6] != 0) begin $display(" ASSERT FAILED: %s", "Result not correct"); #(1000*clk_pulse_width) $finish; end\n                                                                                                                    ^\n%Error: Exiting due to 23 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module perceptron_top_16b_tb;

localparam fp_integer_width = 4;
localparam fp_fract_width = 12;

localparam clock_frequency	= 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

localparam uart_baud_rate	= 9600;

localparam integer 
	OP_READ 				= 5,
	OP_WRITE_WEIGHTS		= 50,
	OP_WRITE_INPUTS			= 51,
 	OP_READ_RESPONSE		= 100,
 	OP_WRITE_RESPONSE_OK 	= 101,
	OP_WRITE_RESPONSE_ERR	= 102;


`define assert(cond, msg) if(cond) begin $display(" ASSERT FAILED: %s", msg); #(1000*clk_pulse_width) $finish; end

integer i;

reg clk, rst_n;


wire perceptron_rx, perceptron_tx;
wire [4:0] cont_state;


reg uart_clear;
reg uart_transmit;
reg [7:0] uart_data_to_send;
wire uart_tx_busy, uart_rx_busy, uart_error, uart_new_value;
wire [7:0] uart_received_data;

reg [7:0] packet_inputs [0:4];
reg [7:0] packet_weights [0:4];
reg [7:0] packet_readings [0:6];

perceptron_top #(
    .fp_integer_width(fp_integer_width),
    .fp_fract_width(fp_fract_width),
	.clock_frequency(clock_frequency),
	.uart_baud_rate(uart_baud_rate)
    ) perceptron_top (
    .rst_n(rst_n),
    .clk(clk),
    .cont_state(cont_state),
    .rx(perceptron_rx),
	.tx(perceptron_tx)
);

uart #(
	.clock_frequency(clock_frequency),
	.baud_rate(uart_baud_rate)
) uart (
    .rst_n(rst_n),
    .clk(clk),
    .rx(perceptron_tx),
	.tx(perceptron_rx),
    .clear(uart_clear),
	.start_transmit(uart_transmit),
    .tx_busy(uart_tx_busy),
	.rx_busy(uart_rx_busy),
    .error(uart_error),
    .new_value(uart_new_value),
	.data_to_send(uart_data_to_send),
    .recvd_data(uart_received_data)
);


initial begin
    $dumpvars(0, perceptron_top, uart);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	uart_clear = 1;

	uart_transmit = 0;
	uart_data_to_send = 0;

	wait( rst_n );
	@(negedge clk);





	uart_data_to_send = OP_READ;
	uart_transmit = 1;

	repeat (2) @(negedge clk);
	uart_transmit = 0;

	for (i = 0; i < 7 ; i = i+1) begin
		wait (uart_new_value);
		packet_readings[i] = uart_received_data;
		repeat (2) @(negedge clk);
	end
	
	$display(" - Finished reading from perceptron");


	`assert(packet_readings[0] != OP_READ_RESPONSE, "Operation CODE not correct")
	`assert(packet_readings[1] != 0 || packet_readings[2] != 0, "Weight 1 not correct")
	`assert(packet_readings[3] != 0 || packet_readings[4] != 0, "Weight 2 not correct")
	`assert(packet_readings[5] != 8'h10 || packet_readings[6] != 0, "Result not correct")
 
	$display(" - Value check OK");

	repeat (5000) @(negedge clk);





	packet_weights[0] = OP_WRITE_WEIGHTS;
	packet_weights[1] =	8'b00010101;
	packet_weights[2] =	8'b10101010;
	packet_weights[3] =	8'b11111100;
	packet_weights[4] =	8'b00110011;

	for (i = 0; i < 5 ; i = i+1) begin
		uart_data_to_send = packet_weights[i];
		uart_transmit = 1;
		wait(uart_tx_busy);
		uart_transmit = 0;
		wait(!uart_tx_busy);
	end
	$display(" - Finished writing weights to perceptron");


	wait (uart_new_value);
	`assert(uart_received_data != OP_WRITE_RESPONSE_OK, "Confirmation CODE not correct")
	
	$display(" - Confirmation received OK");

	repeat (5000) @(negedge clk);




	uart_data_to_send = OP_READ;
	uart_transmit = 1;

	repeat (2) @(negedge clk);
	uart_transmit = 0;

	for (i = 0; i < 7 ; i = i+1) begin
		wait (uart_new_value);
		packet_readings[i] = uart_received_data;
		repeat (2) @(negedge clk);
	end

	$display(" - Finished reading from perceptron");


	`assert(packet_readings[0] != OP_READ_RESPONSE, "Operation CODE not correct")
	`assert(packet_readings[1] != packet_weights[1] || packet_readings[2] != packet_weights[2], "Weight 1 not correct")
	`assert(packet_readings[3] != packet_weights[3] || packet_readings[4] != packet_weights[4], "Weight 2 not correct")
	`assert(packet_readings[5] != 8'h10 || packet_readings[6] != 0, "Result not correct")

	$display(" - Value check OK");




	packet_inputs[0] = OP_WRITE_INPUTS;
	packet_inputs[1] =	8'b11100000;
	packet_inputs[2] =	8'b00000000;
	packet_inputs[3] =	8'b00100000;
	packet_inputs[4] =	8'b00001111;

	for (i = 0; i < 5 ; i = i+1) begin
		uart_data_to_send = packet_inputs[i];
		uart_transmit = 1;
		wait(uart_tx_busy);
		uart_transmit = 0;
		wait(!uart_tx_busy);
	end
	$display(" - Finished writing inputs to perceptron");


	wait (uart_new_value);
	`assert(uart_received_data != OP_WRITE_RESPONSE_OK, "Confirmation CODE not correct")
	
	$display(" - Confirmation received OK");

	repeat (5000) @(negedge clk);




	uart_data_to_send = OP_READ;
	uart_transmit = 1;

	repeat (2) @(negedge clk);
	uart_transmit = 0;

	for (i = 0; i < 7 ; i = i+1) begin
		wait (uart_new_value);
		packet_readings[i] = uart_received_data;
		repeat (2) @(negedge clk);
	end

	$display(" - Finished reading from perceptron");


	`assert(packet_readings[0] != OP_READ_RESPONSE, "Operation CODE not correct")
	`assert(packet_readings[1] != packet_weights[1] || packet_readings[2] != packet_weights[2], "Weight 1 not correct")
	`assert(packet_readings[3] != packet_weights[3] || packet_readings[4] != packet_weights[4], "Weight 2 not correct")
	`assert(packet_readings[5] != 0 || packet_readings[6] != 0, "Result not correct")





	$display(" - Value check OK");

	$display(" - All test CORRECT");
	$finish;
end

endmodule
module perceptron_top_16b_tb;


localparam fp_integer_width = 4;
localparam fp_fract_width = 12;

localparam clock_frequency	= 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

localparam uart_baud_rate	= 9600;

localparam integer 
	OP_READ 				= 5,
	OP_WRITE_WEIGHTS		= 50,
	OP_WRITE_INPUTS			= 51,
 	OP_READ_RESPONSE		= 100,
 	OP_WRITE_RESPONSE_OK 	= 101,
	OP_WRITE_RESPONSE_ERR	= 102;


`define assert(cond, msg) if(cond) begin $display(" ASSERT FAILED: %s", msg); #(1000*clk_pulse_width) $finish; end

integer i;

reg clk, rst_n;


wire perceptron_rx, perceptron_tx;
wire [4:0] cont_state;


reg uart_clear;
reg uart_transmit;
reg [7:0] uart_data_to_send;
wire uart_tx_busy, uart_rx_busy, uart_error, uart_new_value;
wire [7:0] uart_received_data;

reg [7:0] packet_inputs [0:4];
reg [7:0] packet_weights [0:4];
reg [7:0] packet_readings [0:6];

perceptron_top #(
    .fp_integer_width(fp_integer_width),
    .fp_fract_width(fp_fract_width),
	.clock_frequency(clock_frequency),
	.uart_baud_rate(uart_baud_rate)
    ) perceptron_top (
    .rst_n(rst_n),
    .clk(clk),
    .cont_state(cont_state),
    .rx(perceptron_rx),
	.tx(perceptron_tx)
);

uart #(
	.clock_frequency(clock_frequency),
	.baud_rate(uart_baud_rate)
) uart (
    .rst_n(rst_n),
    .clk(clk),
    .rx(perceptron_tx),
	.tx(perceptron_rx),
    .clear(uart_clear),
	.start_transmit(uart_transmit),
    .tx_busy(uart_tx_busy),
	.rx_busy(uart_rx_busy),
    .error(uart_error),
    .new_value(uart_new_value),
	.data_to_send(uart_data_to_send),
    .recvd_data(uart_received_data)
);


initial begin
    $dumpvars(0, perceptron_top, uart);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	uart_clear = 1;

	uart_transmit = 0;
	uart_data_to_send = 0;

	wait( rst_n );
	@(negedge clk);





	uart_data_to_send = OP_READ;
	uart_transmit = 1;

	repeat (2) @(negedge clk);
	uart_transmit = 0;

	for (i = 0; i < 7 ; i = i+1) begin
		wait (uart_new_value);
		packet_readings[i] = uart_received_data;
		repeat (2) @(negedge clk);
	end
	
	$display(" - Finished reading from perceptron");


	`assert(packet_readings[0] != OP_READ_RESPONSE, "Operation CODE not correct")
	`assert(packet_readings[1] != 0 || packet_readings[2] != 0, "Weight 1 not correct")
	`assert(packet_readings[3] != 0 || packet_readings[4] != 0, "Weight 2 not correct")
	`assert(packet_readings[5] != 8'h10 || packet_readings[6] != 0, "Result not correct")
 
	$display(" - Value check OK");

	repeat (5000) @(negedge clk);





	packet_weights[0] = OP_WRITE_WEIGHTS;
	packet_weights[1] =	8'b00010101;
	packet_weights[2] =	8'b10101010;
	packet_weights[3] =	8'b11111100;
	packet_weights[4] =	8'b00110011;

	for (i = 0; i < 5 ; i = i+1) begin
		uart_data_to_send = packet_weights[i];
		uart_transmit = 1;
		wait(uart_tx_busy);
		uart_transmit = 0;
		wait(!uart_tx_busy);
	end
	$display(" - Finished writing weights to perceptron");


	wait (uart_new_value);
	`assert(uart_received_data != OP_WRITE_RESPONSE_OK, "Confirmation CODE not correct")
	
	$display(" - Confirmation received OK");

	repeat (5000) @(negedge clk);




	uart_data_to_send = OP_READ;
	uart_transmit = 1;

	repeat (2) @(negedge clk);
	uart_transmit = 0;

	for (i = 0; i < 7 ; i = i+1) begin
		wait (uart_new_value);
		packet_readings[i] = uart_received_data;
		repeat (2) @(negedge clk);
	end

	$display(" - Finished reading from perceptron");


	`assert(packet_readings[0] != OP_READ_RESPONSE, "Operation CODE not correct")
	`assert(packet_readings[1] != packet_weights[1] || packet_readings[2] != packet_weights[2], "Weight 1 not correct")
	`assert(packet_readings[3] != packet_weights[3] || packet_readings[4] != packet_weights[4], "Weight 2 not correct")
	`assert(packet_readings[5] != 8'h10 || packet_readings[6] != 0, "Result not correct")

	$display(" - Value check OK");




	packet_inputs[0] = OP_WRITE_INPUTS;
	packet_inputs[1] =	8'b11100000;
	packet_inputs[2] =	8'b00000000;
	packet_inputs[3] =	8'b00100000;
	packet_inputs[4] =	8'b00001111;

	for (i = 0; i < 5 ; i = i+1) begin
		uart_data_to_send = packet_inputs[i];
		uart_transmit = 1;
		wait(uart_tx_busy);
		uart_transmit = 0;
		wait(!uart_tx_busy);
	end
	$display(" - Finished writing inputs to perceptron");


	wait (uart_new_value);
	`assert(uart_received_data != OP_WRITE_RESPONSE_OK, "Confirmation CODE not correct")
	
	$display(" - Confirmation received OK");

	repeat (5000) @(negedge clk);




	uart_data_to_send = OP_READ;
	uart_transmit = 1;

	repeat (2) @(negedge clk);
	uart_transmit = 0;

	for (i = 0; i < 7 ; i = i+1) begin
		wait (uart_new_value);
		packet_readings[i] = uart_received_data;
		repeat (2) @(negedge clk);
	end

	$display(" - Finished reading from perceptron");


	`assert(packet_readings[0] != OP_READ_RESPONSE, "Operation CODE not correct")
	`assert(packet_readings[1] != packet_weights[1] || packet_readings[2] != packet_weights[2], "Weight 1 not correct")
	`assert(packet_readings[3] != packet_weights[3] || packet_readings[4] != packet_weights[4], "Weight 2 not correct")
	`assert(packet_readings[5] != 0 || packet_readings[6] != 0, "Result not correct")





	$display(" - Value check OK");

	$display(" - All test CORRECT");
	$finish;
end

endmodule