data/full_repos/permissive/19214654/rs232_top.v
 line:34: before: "else"
1: b'%Error: data/full_repos/permissive/19214654/rs232_top.v:34: syntax error, unexpected else\n      else\n      ^~~~\n%Error: data/full_repos/permissive/19214654/rs232_top.v:39: syntax error, unexpected else\n        else begin\n        ^~~~\n%Error: Cannot continue\n'
module rs232_top (
                  input  I_CLK,
                  input  I_RSTF,
                  input  I_RX,
                  output O_TX
                  );


   reg  [7:0] baud_cnt;
   reg        baud_tick;
   wire [7:0] data;
   wire       rx_done;

   uart_rx rx ( .I_CLK        (I_CLK     ), 
                .I_RSTF       (I_RSTF    ), 
                .I_RX         (I_RX      ), 
                .I_BAUD_TICK  (baud_tick ), 
                .O_DATA       (data      ), 
                .O_RX_DONE    (rx_done   ));

   uart_tx tx ( .I_CLK        (I_CLK     ), 
                .I_RSTF       (I_RSTF    ), 
                .I_TX_START   (rx_done   ), 
                .I_BAUD_TICK  (baud_tick ), 
                .I_DATA       (data      ), 
                .O_TX_DONE    (          ), 
                .O_TX         (O_TX      )) ;


   always @ (posedge I_CLK, negedge I_RSTF) begin
      if (!I_RSTF)
        baud_cnt  <= 0;
        baud_tick <= 1;
      else
        if (baud_cnt == 26) begin
           baud_cnt  <= 0;
           baud_tick <= 1;
        end
        else begin
           baud_cnt  <= baud_cnt+1 ;
           baud_tick <= 0;
        end
   end
      
endmodule
module rs232_top (
                  input  I_CLK,
                  input  I_RSTF,
                  input  I_RX,
                  output O_TX
                  );



   reg  [7:0] baud_cnt;
   reg        baud_tick;
   wire [7:0] data;
   wire       rx_done;

   uart_rx rx ( .I_CLK        (I_CLK     ), 
                .I_RSTF       (I_RSTF    ), 
                .I_RX         (I_RX      ), 
                .I_BAUD_TICK  (baud_tick ), 
                .O_DATA       (data      ), 
                .O_RX_DONE    (rx_done   ));

   uart_tx tx ( .I_CLK        (I_CLK     ), 
                .I_RSTF       (I_RSTF    ), 
                .I_TX_START   (rx_done   ), 
                .I_BAUD_TICK  (baud_tick ), 
                .I_DATA       (data      ), 
                .O_TX_DONE    (          ), 
                .O_TX         (O_TX      )) ;


   always @ (posedge I_CLK, negedge I_RSTF) begin
      if (!I_RSTF)
        baud_cnt  <= 0;
        baud_tick <= 1;
      else
        if (baud_cnt == 26) begin
           baud_cnt  <= 0;
           baud_tick <= 1;
        end
        else begin
           baud_cnt  <= baud_cnt+1 ;
           baud_tick <= 0;
        end
   end
      
endmodule