data/full_repos/permissive/191834901/VerilogHDL/mainMemory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/191834901/VerilogHDL/mainMemory.v:20: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'instMemory\'\nmodule instMemory #(parameter instructionW=32, parameter addrW=16) (\n       ^~~~~~~~~~\n                                                                                  : ... Top module \'dataMemory\'\nmodule dataMemory #(parameter dataW=32, parameter addrW=16) (\n       ^~~~~~~~~~\n                                                                                  : ... Top module \'controlPathDriver\'\nmodule controlPathDriver #(parameter controlWordWidth=16, parameter caddrW=16) (\n       ^~~~~~~~~~~~~~~~~\n                                                                                  : ... Top module \'registerFile\'\nmodule registerFile #(parameter dataWidth=32, parameter addrWidth=5) (\n       ^~~~~~~~~~~~\n                                                                                  : ... Top module \'registerNx\'\nmodule registerNx #(parameter regWidth=8)(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module instMemory #(parameter instructionW=32, parameter addrW=16) (
	output reg [(instructionW-1):0]inst,
	input [(addrW-1):0] pcVal,
	input sysCLK
);
	reg [instructionW-1:0] instructionROM[2**addrW-1:0];
	
	initial begin
		$readmemh("C:/rom_instruction_memory.txt", instructionROM);
	end

	always @ (posedge sysCLK) begin
		inst <= instructionROM[pcVal];
	end
endmodule
module instMemory #(parameter instructionW=32, parameter addrW=16) (
	output reg [(instructionW-1):0]inst,
	input [(addrW-1):0] pcVal,
	input sysCLK
);

	reg [instructionW-1:0] instructionROM[2**addrW-1:0];
	
	initial begin
		$readmemh("C:/rom_instruction_memory.txt", instructionROM);
	end

	always @ (posedge sysCLK) begin
		inst <= instructionROM[pcVal];
	end
endmodule