data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #1.5\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #18.5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #23\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #125\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #101.25\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #11.5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk_5x = ~clk_5x;\n        ^\n%Error: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:66: Cannot find file containing module: \'async_reset\'\n    async_reset async_reset_instance (\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/async_reset\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/async_reset.v\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/async_reset.sv\n             async_reset\n             async_reset.v\n             async_reset.sv\n             obj_dir/async_reset\n             obj_dir/async_reset.v\n             obj_dir/async_reset.sv\n%Error: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:72: Cannot find file containing module: \'serializer_10to1\'\n    serializer_10to1 serialize_data_1 (\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:80: Cannot find file containing module: \'serializer_10to1\'\n    serializer_10to1 serialize_data_2 (\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173150157/rtl/test/serializer_10to1_tb.v:88: Cannot find file containing module: \'serializer_10to1\'\n     serializer_10to1 serialize_data_3 (\n     ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module serializer_10to1_tb();

    reg rst;
    reg clk;
    reg clk_5x;
    reg clk_lock;

    wire rst_oserdes;
    reg [9:0] tmds_data_1;
    reg [9:0] tmds_data_2;
    reg [9:0] tmds_data_3;
    wire tmds_data_1_serial;
    wire tmds_data_2_serial;
    wire tmds_data_3_serial;

    initial begin
        $display($time, " << Starting Simulation >>");
        clk = 0;
        clk_5x = 0;
        rst = 0;
        clk_lock = 0;

        #1.5
        rst = 1;

        #18.5
        rst = 0;

        #20
        clk_lock = 1;
        tmds_data_1 = 10'b0110100110;
        tmds_data_2 = 10'b1001011001;
        tmds_data_3 = 10'b1100000010;

        #100
        tmds_data_1 = 10'b1111111111;
        tmds_data_2 = 10'b1010101010;
        tmds_data_3 = 10'b0000000000;

        #2
        clk_lock = 0;

        #23
        clk_lock = 1;

        #125
        tmds_data_1 = 10'b0110100110;
        tmds_data_2 = 10'b1001011001;
        tmds_data_3 = 10'b1100000010;

        #101.25
        rst = 1;

        #11.5
        rst = 0;
    end


    async_reset async_reset_instance (
        .i_clk(clk),
        .i_rst(rst | ~clk_lock),
        .o_rst(rst_oserdes)
    );

    serializer_10to1 serialize_data_1 (
        .i_clk(clk),
        .i_clk_hs(clk_5x),
        .i_rst_oserdes(rst_oserdes),
        .i_data(tmds_data_1),
        .o_data(tmds_data_1_serial)
    );

    serializer_10to1 serialize_data_2 (
        .i_clk(clk),
        .i_clk_hs(clk_5x),
        .i_rst_oserdes(rst_oserdes),
        .i_data(tmds_data_2),
        .o_data(tmds_data_2_serial)
    );

     serializer_10to1 serialize_data_3 (
        .i_clk(clk),
        .i_clk_hs(clk_5x),
        .i_rst_oserdes(rst_oserdes),
        .i_data(tmds_data_3),
        .o_data(tmds_data_3_serial)
    );

    always
        #5 clk = ~clk;

    always
        #1 clk_5x = ~clk_5x;

endmodule
module serializer_10to1_tb();


    reg rst;
    reg clk;
    reg clk_5x;
    reg clk_lock;

    wire rst_oserdes;
    reg [9:0] tmds_data_1;
    reg [9:0] tmds_data_2;
    reg [9:0] tmds_data_3;
    wire tmds_data_1_serial;
    wire tmds_data_2_serial;
    wire tmds_data_3_serial;

    initial begin
        $display($time, " << Starting Simulation >>");
        clk = 0;
        clk_5x = 0;
        rst = 0;
        clk_lock = 0;

        #1.5
        rst = 1;

        #18.5
        rst = 0;

        #20
        clk_lock = 1;
        tmds_data_1 = 10'b0110100110;
        tmds_data_2 = 10'b1001011001;
        tmds_data_3 = 10'b1100000010;

        #100
        tmds_data_1 = 10'b1111111111;
        tmds_data_2 = 10'b1010101010;
        tmds_data_3 = 10'b0000000000;

        #2
        clk_lock = 0;

        #23
        clk_lock = 1;

        #125
        tmds_data_1 = 10'b0110100110;
        tmds_data_2 = 10'b1001011001;
        tmds_data_3 = 10'b1100000010;

        #101.25
        rst = 1;

        #11.5
        rst = 0;
    end


    async_reset async_reset_instance (
        .i_clk(clk),
        .i_rst(rst | ~clk_lock),
        .o_rst(rst_oserdes)
    );

    serializer_10to1 serialize_data_1 (
        .i_clk(clk),
        .i_clk_hs(clk_5x),
        .i_rst_oserdes(rst_oserdes),
        .i_data(tmds_data_1),
        .o_data(tmds_data_1_serial)
    );

    serializer_10to1 serialize_data_2 (
        .i_clk(clk),
        .i_clk_hs(clk_5x),
        .i_rst_oserdes(rst_oserdes),
        .i_data(tmds_data_2),
        .o_data(tmds_data_2_serial)
    );

     serializer_10to1 serialize_data_3 (
        .i_clk(clk),
        .i_clk_hs(clk_5x),
        .i_rst_oserdes(rst_oserdes),
        .i_data(tmds_data_3),
        .o_data(tmds_data_3_serial)
    );

    always
        #5 clk = ~clk;

    always
        #1 clk_5x = ~clk_5x;

endmodule