data/full_repos/permissive/102490099/sdram_rw_de2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/102490099/sdram_rw_de2.v:204: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 32 bits.\n                                                                       : ... In instance sdram_rw\n      if( (read_cntr & 32\'h01))\n      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102490099/sdram_rw_de2.v:228: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 32 bits.\n                                                                       : ... In instance sdram_rw\n       if( read_cntr & 32\'h01)\n       ^~\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:265: Cannot find file containing module: \'SEG7_LUT\'\n  SEG7_LUT seg0 ( hex0, state[3:0]);\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102490099,data/full_repos/permissive/102490099/SEG7_LUT\n             data/full_repos/permissive/102490099,data/full_repos/permissive/102490099/SEG7_LUT.v\n             data/full_repos/permissive/102490099,data/full_repos/permissive/102490099/SEG7_LUT.sv\n             SEG7_LUT\n             SEG7_LUT.v\n             SEG7_LUT.sv\n             obj_dir/SEG7_LUT\n             obj_dir/SEG7_LUT.v\n             obj_dir/SEG7_LUT.sv\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:266: Cannot find file containing module: \'SEG7_LUT\'\n  SEG7_LUT seg1 ( hex1, time_count[3:0]);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:267: Cannot find file containing module: \'SEG7_LUT\'\n  SEG7_LUT seg2 ( hex2, time_count[7:4]);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:268: Cannot find file containing module: \'SEG7_LUT\'\n  SEG7_LUT seg3 ( hex3, time_count[11:8]);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:269: Cannot find file containing module: \'SEG7_LUT\'\n  SEG7_LUT seg4 ( hex4, time_count[15:12]);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/102490099/sdram_rw_de2.v:270: Cannot find file containing module: \'SEG7_LUT\'\n  SEG7_LUT seg5 ( hex5, time_count[19:16]);\n  ^~~~~~~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module sdram_rw
  (
   input clk_i,
   input rst_i,
   output [24:0] addr_i,
   output [31:0] dat_i,
   input [31:0] dat_o,
   output we_i,
   input ack_o,
   output stb_i,
   output cyc_i,
	input  init_done,
   output [0:0] green_led,
   output [0:0] red_led,
	output [7:0] hex0, 
	output [7:0] hex1, 
	output [7:0] hex2, 
	output [7:0] hex3, 
	output [7:0] hex4, 
	output [7:0] hex5,
	input  [9:0] switches
   );

  parameter START_WRITE_ST        = 4'b0000,
              WRITE_ST           = 4'b0001,
              WAIT_WRITE_ACK_ST  = 4'b0010,
              READ_ST            = 4'b0011,
              WAIT_READ_ACK_ST   = 4'b0100,
              WRITE_WAIT_ST      = 4'b0101,
              START_READ_ST      = 4'b0110,
              READ_WAIT_ST       = 4'b0111,
              DONE_ST            = 4'b1000,
				  DONE_WAIT_ST       = 4'b1001,
              WRITE_SECOND_BANK	= 4'b1010,
              WAIT_WRITE2_ACK_ST	= 4'b1011;
				  
  
  parameter MAX_RW = 24'd0002000;
  parameter R_TO_W_WAIT_TIME  = 24'd1;
  parameter INITIAL_MEM_VALUE =32'h00005678;
  
  reg [24:0] addr_i_r;
  reg [31:0] dat_i_r;
  reg        we_i_r;
  reg        stb_i_r;
  reg        cyc_i_r;

  reg [23:0] rw_cntr;  
  reg [23:0] cntr;
  reg [31:0] number;
  reg [31:0] mem_value;
  reg [3:0]  state;   
  reg [31:0]  read_cntr, time_count;
  reg [7:0]  bad_count;

  reg [0:0]       red_led_r;
  reg [0:0]       green_led_r;
  

  assign dat_i = dat_i_r;
  assign addr_i = addr_i_r;
  assign we_i = we_i_r;
  assign stb_i = stb_i_r;
  assign cyc_i = cyc_i_r;
  assign red_led = red_led_r;
  assign green_led = green_led_r;


  initial begin
    mem_value <= INITIAL_MEM_VALUE;
    cntr <= 24'b0;
    rw_cntr <= 24'b0;
    state <= DONE_WAIT_ST;
    we_i_r <= 1'b0;
    addr_i_r <= 25'b0;
    stb_i_r <= 1'b0;
    cyc_i_r <= 1'b0;
    red_led_r <= 1'b0;
    green_led_r <= 1'b0;
	 read_cntr <= 0;
  end
  
  
  always@ (posedge clk_i or posedge rst_i) begin
    if( rst_i && state == DONE_WAIT_ST ) begin
		state <= START_WRITE_ST;
		red_led_r <= 1'b0;
		green_led_r <= 1'b0;
		rw_cntr <= 24'b0;
		addr_i_r <= 25'd0;
		bad_count <= switches[7:0]; 
		time_count <= 0;
    end else begin
	 
      case (state) 
        START_WRITE_ST:
          begin
            state <= WRITE_ST;
          end
        
        WRITE_ST:
          begin
            stb_i_r <= 1'b1;
            cyc_i_r <= 1'b1;
            dat_i_r <= mem_value;
            we_i_r <= 1'b1;

			   addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
            state <= WAIT_WRITE_ACK_ST;
          end

        WAIT_WRITE_ACK_ST:
          if (ack_o) begin
            state <= WRITE_SECOND_BANK;
            stb_i_r <= 1'b0;
            cyc_i_r <= 1'b0;
				read_cntr <= 0;
				bad_count <= 0;
          end
			 else rw_cntr <= rw_cntr + 24'b1;
			 
			 
		  WRITE_SECOND_BANK:
          begin
            stb_i_r <= 1'b1;
            cyc_i_r <= 1'b1;
            dat_i_r <= mem_value + 1;
            we_i_r <= 1'b1;
			   addr_i_r <= { 1'b1, switches[9:8], 12'b0, switches };
            state <= WAIT_WRITE2_ACK_ST;
          end
		  
        WAIT_WRITE2_ACK_ST:
          if (ack_o) begin
            state <= READ_ST;
            stb_i_r <= 1'b0;
            cyc_i_r <= 1'b0;
				read_cntr <= 0;
				bad_count <= 0;
          end
			 else rw_cntr <= rw_cntr + 24'b1;

        READ_ST:
          begin
            stb_i_r <= 1'b1;
            cyc_i_r <= 1'b1;
            we_i_r <= 1'b0;
				addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
            state <= WAIT_READ_ACK_ST;
          end
        
        WAIT_READ_ACK_ST:
          if (ack_o) begin
            state <= READ_WAIT_ST;
            number <= dat_o;
            stb_i_r <= 1'b0;
            cyc_i_r <= 1'b0;
          end
			 else rw_cntr <= rw_cntr + 24'b1;


        READ_WAIT_ST:
          begin
				  if( (read_cntr & 32'h01))
				  begin
					  if (mem_value + 1 != number) begin
						 bad_count <= bad_count + 1;
						 red_led_r[0] <= 1'b1;
					  end 
				  end else
				  begin
					  if (mem_value != number) begin
						 bad_count <= bad_count + 1;
						 red_led_r[0] <= 1'b1;
					  end 
				  end
				  read_cntr <= read_cntr + 1;
				  if( read_cntr == 'h00ffffff)
				  begin
					  mem_value <= mem_value + 1'b1;
					  state <= DONE_ST;
					  time_count <= number;
				  end else begin

					  stb_i_r <= 1'b1;
					  cyc_i_r <= 1'b1;
					  we_i_r <= 1'b0;
					  if( read_cntr & 32'h01)
						  addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
					  else
						  addr_i_r <= { 1'b1, switches[9:8], 12'b0, switches };
					  state <= WAIT_READ_ACK_ST;
              end
          end

        DONE_ST:
          begin
            state <= DONE_WAIT_ST;
            if (!red_led_r[0])
              green_led_r[0] <= 1'b1;
 			   else
              green_led_r[0] <= 1'b0;
          end

        DONE_WAIT_ST:
          begin
			 end
			 
      endcase
    end
  end


  always@ (posedge clk_i) begin
    if (rst_i) begin
      cntr <= 24'b0;
    end else if (state == WRITE_WAIT_ST) begin
      cntr <= R_TO_W_WAIT_TIME;
    end else
      cntr <= cntr - 24'b1;
  end



  SEG7_LUT seg0 ( hex0, state[3:0]);
  SEG7_LUT seg1 ( hex1, time_count[3:0]);
  SEG7_LUT seg2 ( hex2, time_count[7:4]);
  SEG7_LUT seg3 ( hex3, time_count[11:8]);
  SEG7_LUT seg4 ( hex4, time_count[15:12]);
  SEG7_LUT seg5 ( hex5, time_count[19:16]);

  
endmodule
module sdram_rw
  (
   input clk_i,
   input rst_i,
   output [24:0] addr_i,
   output [31:0] dat_i,
   input [31:0] dat_o,
   output we_i,
   input ack_o,
   output stb_i,
   output cyc_i,
	input  init_done,
   output [0:0] green_led,
   output [0:0] red_led,
	output [7:0] hex0, 
	output [7:0] hex1, 
	output [7:0] hex2, 
	output [7:0] hex3, 
	output [7:0] hex4, 
	output [7:0] hex5,
	input  [9:0] switches
   );


  parameter START_WRITE_ST        = 4'b0000,
              WRITE_ST           = 4'b0001,
              WAIT_WRITE_ACK_ST  = 4'b0010,
              READ_ST            = 4'b0011,
              WAIT_READ_ACK_ST   = 4'b0100,
              WRITE_WAIT_ST      = 4'b0101,
              START_READ_ST      = 4'b0110,
              READ_WAIT_ST       = 4'b0111,
              DONE_ST            = 4'b1000,
				  DONE_WAIT_ST       = 4'b1001,
              WRITE_SECOND_BANK	= 4'b1010,
              WAIT_WRITE2_ACK_ST	= 4'b1011;
				  
  
  parameter MAX_RW = 24'd0002000;
  parameter R_TO_W_WAIT_TIME  = 24'd1;
  parameter INITIAL_MEM_VALUE =32'h00005678;
  
  reg [24:0] addr_i_r;
  reg [31:0] dat_i_r;
  reg        we_i_r;
  reg        stb_i_r;
  reg        cyc_i_r;

  reg [23:0] rw_cntr;  
  reg [23:0] cntr;
  reg [31:0] number;
  reg [31:0] mem_value;
  reg [3:0]  state;   
  reg [31:0]  read_cntr, time_count;
  reg [7:0]  bad_count;

  reg [0:0]       red_led_r;
  reg [0:0]       green_led_r;
  

  assign dat_i = dat_i_r;
  assign addr_i = addr_i_r;
  assign we_i = we_i_r;
  assign stb_i = stb_i_r;
  assign cyc_i = cyc_i_r;
  assign red_led = red_led_r;
  assign green_led = green_led_r;


  initial begin
    mem_value <= INITIAL_MEM_VALUE;
    cntr <= 24'b0;
    rw_cntr <= 24'b0;
    state <= DONE_WAIT_ST;
    we_i_r <= 1'b0;
    addr_i_r <= 25'b0;
    stb_i_r <= 1'b0;
    cyc_i_r <= 1'b0;
    red_led_r <= 1'b0;
    green_led_r <= 1'b0;
	 read_cntr <= 0;
  end
  
  
  always@ (posedge clk_i or posedge rst_i) begin
    if( rst_i && state == DONE_WAIT_ST ) begin
		state <= START_WRITE_ST;
		red_led_r <= 1'b0;
		green_led_r <= 1'b0;
		rw_cntr <= 24'b0;
		addr_i_r <= 25'd0;
		bad_count <= switches[7:0]; 
		time_count <= 0;
    end else begin
	 
      case (state) 
        START_WRITE_ST:
          begin
            state <= WRITE_ST;
          end
        
        WRITE_ST:
          begin
            stb_i_r <= 1'b1;
            cyc_i_r <= 1'b1;
            dat_i_r <= mem_value;
            we_i_r <= 1'b1;

			   addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
            state <= WAIT_WRITE_ACK_ST;
          end

        WAIT_WRITE_ACK_ST:
          if (ack_o) begin
            state <= WRITE_SECOND_BANK;
            stb_i_r <= 1'b0;
            cyc_i_r <= 1'b0;
				read_cntr <= 0;
				bad_count <= 0;
          end
			 else rw_cntr <= rw_cntr + 24'b1;
			 
			 
		  WRITE_SECOND_BANK:
          begin
            stb_i_r <= 1'b1;
            cyc_i_r <= 1'b1;
            dat_i_r <= mem_value + 1;
            we_i_r <= 1'b1;
			   addr_i_r <= { 1'b1, switches[9:8], 12'b0, switches };
            state <= WAIT_WRITE2_ACK_ST;
          end
		  
        WAIT_WRITE2_ACK_ST:
          if (ack_o) begin
            state <= READ_ST;
            stb_i_r <= 1'b0;
            cyc_i_r <= 1'b0;
				read_cntr <= 0;
				bad_count <= 0;
          end
			 else rw_cntr <= rw_cntr + 24'b1;

        READ_ST:
          begin
            stb_i_r <= 1'b1;
            cyc_i_r <= 1'b1;
            we_i_r <= 1'b0;
				addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
            state <= WAIT_READ_ACK_ST;
          end
        
        WAIT_READ_ACK_ST:
          if (ack_o) begin
            state <= READ_WAIT_ST;
            number <= dat_o;
            stb_i_r <= 1'b0;
            cyc_i_r <= 1'b0;
          end
			 else rw_cntr <= rw_cntr + 24'b1;


        READ_WAIT_ST:
          begin
				  if( (read_cntr & 32'h01))
				  begin
					  if (mem_value + 1 != number) begin
						 bad_count <= bad_count + 1;
						 red_led_r[0] <= 1'b1;
					  end 
				  end else
				  begin
					  if (mem_value != number) begin
						 bad_count <= bad_count + 1;
						 red_led_r[0] <= 1'b1;
					  end 
				  end
				  read_cntr <= read_cntr + 1;
				  if( read_cntr == 'h00ffffff)
				  begin
					  mem_value <= mem_value + 1'b1;
					  state <= DONE_ST;
					  time_count <= number;
				  end else begin

					  stb_i_r <= 1'b1;
					  cyc_i_r <= 1'b1;
					  we_i_r <= 1'b0;
					  if( read_cntr & 32'h01)
						  addr_i_r <= { 1'b0, switches[9:8], 12'b0, switches };
					  else
						  addr_i_r <= { 1'b1, switches[9:8], 12'b0, switches };
					  state <= WAIT_READ_ACK_ST;
              end
          end

        DONE_ST:
          begin
            state <= DONE_WAIT_ST;
            if (!red_led_r[0])
              green_led_r[0] <= 1'b1;
 			   else
              green_led_r[0] <= 1'b0;
          end

        DONE_WAIT_ST:
          begin
			 end
			 
      endcase
    end
  end


  always@ (posedge clk_i) begin
    if (rst_i) begin
      cntr <= 24'b0;
    end else if (state == WRITE_WAIT_ST) begin
      cntr <= R_TO_W_WAIT_TIME;
    end else
      cntr <= cntr - 24'b1;
  end



  SEG7_LUT seg0 ( hex0, state[3:0]);
  SEG7_LUT seg1 ( hex1, time_count[3:0]);
  SEG7_LUT seg2 ( hex2, time_count[7:4]);
  SEG7_LUT seg3 ( hex3, time_count[11:8]);
  SEG7_LUT seg4 ( hex4, time_count[15:12]);
  SEG7_LUT seg5 ( hex5, time_count[19:16]);

  
endmodule