data/full_repos/permissive/184916587/Decode_INST.v
1: b'%Warning-WIDTH: data/full_repos/permissive/184916587/Decode_INST.v:125: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                      : ... In instance Decode_INST\n         immr=inst[24:20];\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/184916587/Decode_INST.v:131: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                      : ... In instance Decode_INST\n         immr=inst[24:20];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/184916587/Decode_INST.v:137: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                      : ... In instance Decode_INST\n         immr=inst[24:20];\n             ^\n%Error: Exiting due to 3 warning(s)\n'
module Decode_INST(

		input [31:0] inst,

		output reg[9:0] alu_op,
		output reg[4:0] rs1,
		output reg[4:0] rs2,
		output reg[4:0] rd,
		output reg[31:0] address_imm,
		output reg[4:0] ls_op,
		output reg[4:0] j_op,
		output reg[4:0] b_op
	);
	

	reg[31:0] immr;

	always @* begin
		address_imm<=immr;
	end




	always @* begin
		case(inst[6:0])

			7'b0110011:begin
			rs1=inst[19:15];
			rs2=inst[24:20];
			rd=inst[11:7];
			b_op={5{1'b1}};
			ls_op={5{1'b1}};
			j_op={5{1'b1}};
			immr={32{1'b0}};
				case(inst[31:25])
					7'b0000000:begin
						case(inst[14:12])
							3'b000:begin
								alu_op=10'b0000000001;
							end
							3'b001:begin
								alu_op=10'b0000000011;
							end
							3'b010:begin
								alu_op=10'b0000000101;
							end
							3'b011:begin
								alu_op=10'b0000000110;
							end
							3'b100:begin
								alu_op=10'b0000000111;
							end
							3'b101:begin
								alu_op=10'b0000001000;
							end
							3'b110:begin
								alu_op=10'b0000001010;
							end
							3'b111:begin
								alu_op=10'b0000001011;
							end
						endcase
					end
					7'b0100000:begin
						case(inst[14:12])
							3'b000:begin
								alu_op=10'b0000000010;
							end
							3'b101:begin
								alu_op=10'b0000001001;
							end
						endcase
					end
				endcase
			end

			7'b0010011:begin
				rs1=inst[19:15];
				rs2={5{1'b0}};
				rd=inst[11:7];
				b_op={5{1'b1}};
				ls_op={5{1'b1}};
				j_op={5{1'b1}};
				case(inst[14:12])
					3'b000:begin
						alu_op=10'b1000000001;
						immr={{20{inst[31]}},inst[31:20]};
					end
					3'b010:begin
						alu_op=10'b1000000101;
						immr={{20{inst[31]}},inst[31:20]};
					end
					3'b011:begin
						alu_op=10'b1000000110;
						immr={{20{inst[31]}},inst[31:20]};
					end
					3'b100:begin
						alu_op=10'b1000000111;
						immr={{20{inst[31]}},inst[31:20]};
					end
					3'b110:begin
						alu_op=10'b1000001010;
						immr={{20{inst[31]}},inst[31:20]};
					end
					3'b111:begin
						alu_op=10'b1000001011;
						immr={{20{inst[31]}},inst[31:20]};
					end
				endcase


				case(inst[31:25])
					7'b0000000:begin
						case(inst[14:12])
							3'b001:begin
								if(inst[24]==1'b0) begin
									alu_op=10'b1000000011;
									immr=inst[24:20];
								end
							end
							3'b001:begin
								if(inst[24]==1'b0) begin
									alu_op=10'b1000001000;
									immr=inst[24:20];
								end
							end
							3'b101:begin
								if(inst[24]==1'b0) begin
									alu_op=10'b1000001001;
									immr=inst[24:20];
								end
							end
						endcase
					end
				endcase
			end


			7'b0000011:begin
				rs1=inst[19:15];
				rd=inst[11:7];
				rs2=inst[24:20];
				alu_op={10{1'b1}};
				ls_op={5{1'b1}};
				j_op={5{1'b1}};
				case(inst[14:12])
					3'b000:begin
						immr={{20{inst[31]}},inst[31:20]};
						ls_op=5'b00001;
					end
					3'b001:begin
						immr={{20{inst[31]}},inst[31:20]};
						ls_op=5'b00010;
					end
					3'b010:begin
						immr={{20{inst[31]}},inst[31:20]};
						ls_op=5'b00011;
					end
					3'b100:begin
						immr={{20{1'b0}},inst[31:20]};
						ls_op=5'b00001;
					end
					3'b101:begin
						immr={{20{1'b0}},inst[31:20]};
						ls_op=5'b00010;
					end
				endcase
			end

			7'b1100111:begin
				rs1=inst[19:15];
				rs2={5{1'b0}};
				rd=inst[11:7];
				alu_op={10{1'b1}};
				b_op={5{1'b1}};
				ls_op={5{1'b1}};

				case(inst[14:12])
					3'b000:begin
						immr={{20{inst[31]}},inst[31:20]};
						j_op=5'b00001;
					end
				endcase
			end

			7'b0001111:begin

			end

			7'b1110011:begin

			end

			7'b1101111:begin
				rs1={5{1'b0}};
				rs2={5{1'b0}};
				rd=inst[11:7];
				alu_op={10{1'b1}};
				b_op={5{1'b1}};
				ls_op={5{1'b1}};

				immr={{11{inst[31]}},inst[31],inst[19:12],inst[20],inst[30:21],1'b0};
				j_op=5'b00010;
			end

			7'b0110111:begin
				rs1={5{1'b0}};
				rs2={5{1'b0}};
				rd=inst[11:7];
				alu_op={10{1'b1}};
				j_op={5{1'b1}};
				b_op={5{1'b1}};

				immr={{12{inst[31]}},inst[31:12]};
				ls_op=5'b00100;
			end

			7'b0010111:begin
				rs1={5{1'b0}};
				rs2={5{1'b0}};
				rd=inst[11:7];
				alu_op={10{1'b1}};
				j_op={5{1'b1}};
				b_op={5{1'b1}};

				immr={{12{inst[31]}},inst[31:12]};
				ls_op=5'b00101;
			end


			7'b0100011:begin
				rs1=inst[19:15];
				rs2=inst[24:20];
				rd=inst[11:7];
				alu_op={10{1'b1}};
				j_op={5{1'b1}};
				b_op={5{1'b1}};
				case(inst[14:12])
					3'b000:begin
						immr={{20{inst[31]}},inst[31:25],inst[11:7]};
						ls_op=5'b00110;
					end
					3'b001:begin
						immr={{20{inst[31]}},inst[31:25],inst[11:7]};
						ls_op=5'b00111;
					end
					3'b010:begin
						immr={{20{inst[31]}},inst[31:25],inst[11:7]};
						ls_op=5'b01000;
					end
				endcase
			end

			7'b1100011:begin
				rs1=inst[19:15];
				rs2=inst[24:20];
				rd={5{1'b0}};
				alu_op={10{1'b1}};
				ls_op={5{1'b1}};
				j_op={5{1'b1}};
				case(inst[14:12])
					3'b000:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00001;
					end
					3'b001:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00010;
					end
					3'b100:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00011;
					end
					3'b101:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00100;
					end
					3'b110:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00101;
					end
					3'b111:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00111;
					end
				endcase
			end
		endcase
	end

endmodule
module Decode_INST(

		input [31:0] inst,

		output reg[9:0] alu_op,
		output reg[4:0] rs1,
		output reg[4:0] rs2,
		output reg[4:0] rd,
		output reg[31:0] address_imm,
		output reg[4:0] ls_op,
		output reg[4:0] j_op,
		output reg[4:0] b_op
	);

	

	reg[31:0] immr;

	always @* begin
		address_imm<=immr;
	end




	always @* begin
		case(inst[6:0])

			7'b0110011:begin
			rs1=inst[19:15];
			rs2=inst[24:20];
			rd=inst[11:7];
			b_op={5{1'b1}};
			ls_op={5{1'b1}};
			j_op={5{1'b1}};
			immr={32{1'b0}};
				case(inst[31:25])
					7'b0000000:begin
						case(inst[14:12])
							3'b000:begin
								alu_op=10'b0000000001;
							end
							3'b001:begin
								alu_op=10'b0000000011;
							end
							3'b010:begin
								alu_op=10'b0000000101;
							end
							3'b011:begin
								alu_op=10'b0000000110;
							end
							3'b100:begin
								alu_op=10'b0000000111;
							end
							3'b101:begin
								alu_op=10'b0000001000;
							end
							3'b110:begin
								alu_op=10'b0000001010;
							end
							3'b111:begin
								alu_op=10'b0000001011;
							end
						endcase
					end
					7'b0100000:begin
						case(inst[14:12])
							3'b000:begin
								alu_op=10'b0000000010;
							end
							3'b101:begin
								alu_op=10'b0000001001;
							end
						endcase
					end
				endcase
			end

			7'b0010011:begin
				rs1=inst[19:15];
				rs2={5{1'b0}};
				rd=inst[11:7];
				b_op={5{1'b1}};
				ls_op={5{1'b1}};
				j_op={5{1'b1}};
				case(inst[14:12])
					3'b000:begin
						alu_op=10'b1000000001;
						immr={{20{inst[31]}},inst[31:20]};
					end
					3'b010:begin
						alu_op=10'b1000000101;
						immr={{20{inst[31]}},inst[31:20]};
					end
					3'b011:begin
						alu_op=10'b1000000110;
						immr={{20{inst[31]}},inst[31:20]};
					end
					3'b100:begin
						alu_op=10'b1000000111;
						immr={{20{inst[31]}},inst[31:20]};
					end
					3'b110:begin
						alu_op=10'b1000001010;
						immr={{20{inst[31]}},inst[31:20]};
					end
					3'b111:begin
						alu_op=10'b1000001011;
						immr={{20{inst[31]}},inst[31:20]};
					end
				endcase


				case(inst[31:25])
					7'b0000000:begin
						case(inst[14:12])
							3'b001:begin
								if(inst[24]==1'b0) begin
									alu_op=10'b1000000011;
									immr=inst[24:20];
								end
							end
							3'b001:begin
								if(inst[24]==1'b0) begin
									alu_op=10'b1000001000;
									immr=inst[24:20];
								end
							end
							3'b101:begin
								if(inst[24]==1'b0) begin
									alu_op=10'b1000001001;
									immr=inst[24:20];
								end
							end
						endcase
					end
				endcase
			end


			7'b0000011:begin
				rs1=inst[19:15];
				rd=inst[11:7];
				rs2=inst[24:20];
				alu_op={10{1'b1}};
				ls_op={5{1'b1}};
				j_op={5{1'b1}};
				case(inst[14:12])
					3'b000:begin
						immr={{20{inst[31]}},inst[31:20]};
						ls_op=5'b00001;
					end
					3'b001:begin
						immr={{20{inst[31]}},inst[31:20]};
						ls_op=5'b00010;
					end
					3'b010:begin
						immr={{20{inst[31]}},inst[31:20]};
						ls_op=5'b00011;
					end
					3'b100:begin
						immr={{20{1'b0}},inst[31:20]};
						ls_op=5'b00001;
					end
					3'b101:begin
						immr={{20{1'b0}},inst[31:20]};
						ls_op=5'b00010;
					end
				endcase
			end

			7'b1100111:begin
				rs1=inst[19:15];
				rs2={5{1'b0}};
				rd=inst[11:7];
				alu_op={10{1'b1}};
				b_op={5{1'b1}};
				ls_op={5{1'b1}};

				case(inst[14:12])
					3'b000:begin
						immr={{20{inst[31]}},inst[31:20]};
						j_op=5'b00001;
					end
				endcase
			end

			7'b0001111:begin

			end

			7'b1110011:begin

			end

			7'b1101111:begin
				rs1={5{1'b0}};
				rs2={5{1'b0}};
				rd=inst[11:7];
				alu_op={10{1'b1}};
				b_op={5{1'b1}};
				ls_op={5{1'b1}};

				immr={{11{inst[31]}},inst[31],inst[19:12],inst[20],inst[30:21],1'b0};
				j_op=5'b00010;
			end

			7'b0110111:begin
				rs1={5{1'b0}};
				rs2={5{1'b0}};
				rd=inst[11:7];
				alu_op={10{1'b1}};
				j_op={5{1'b1}};
				b_op={5{1'b1}};

				immr={{12{inst[31]}},inst[31:12]};
				ls_op=5'b00100;
			end

			7'b0010111:begin
				rs1={5{1'b0}};
				rs2={5{1'b0}};
				rd=inst[11:7];
				alu_op={10{1'b1}};
				j_op={5{1'b1}};
				b_op={5{1'b1}};

				immr={{12{inst[31]}},inst[31:12]};
				ls_op=5'b00101;
			end


			7'b0100011:begin
				rs1=inst[19:15];
				rs2=inst[24:20];
				rd=inst[11:7];
				alu_op={10{1'b1}};
				j_op={5{1'b1}};
				b_op={5{1'b1}};
				case(inst[14:12])
					3'b000:begin
						immr={{20{inst[31]}},inst[31:25],inst[11:7]};
						ls_op=5'b00110;
					end
					3'b001:begin
						immr={{20{inst[31]}},inst[31:25],inst[11:7]};
						ls_op=5'b00111;
					end
					3'b010:begin
						immr={{20{inst[31]}},inst[31:25],inst[11:7]};
						ls_op=5'b01000;
					end
				endcase
			end

			7'b1100011:begin
				rs1=inst[19:15];
				rs2=inst[24:20];
				rd={5{1'b0}};
				alu_op={10{1'b1}};
				ls_op={5{1'b1}};
				j_op={5{1'b1}};
				case(inst[14:12])
					3'b000:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00001;
					end
					3'b001:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00010;
					end
					3'b100:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00011;
					end
					3'b101:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00100;
					end
					3'b110:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00101;
					end
					3'b111:begin
						immr={{19{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
						b_op=5'b00111;
					end
				endcase
			end
		endcase
	end

endmodule