data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/atlys/rtl/verilog/clkgen.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/atlys/rtl/verilog/clkgen.v:8: Cannot find include file: orpsoc-defines.v\n`include "orpsoc-defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/atlys/rtl/verilog,data/full_repos/permissive/19905110/orpsoc-defines.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/atlys/rtl/verilog,data/full_repos/permissive/19905110/orpsoc-defines.v.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/atlys/rtl/verilog,data/full_repos/permissive/19905110/orpsoc-defines.v.sv\n             orpsoc-defines.v\n             orpsoc-defines.v.v\n             orpsoc-defines.v.sv\n             obj_dir/orpsoc-defines.v\n             obj_dir/orpsoc-defines.v.v\n             obj_dir/orpsoc-defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module clkgen
       (

	input  sys_clk_pad_i,

	input  rst_n_pad_i,

	output async_rst_o,


	output wb_clk_o,
	output wb_rst_o,


	input  tck_pad_i,
	output dbg_tck_o,


	output dvi_clk_o,


	output ddr2_if_clk_o,
	output ddr2_if_rst_o,
	output clk100_o
);


wire	async_rst_n;

assign async_rst_n = rst_n_pad_i;


assign async_rst_o = ~async_rst_n;

assign dbg_tck_o = tck_pad_i;






wire	sync_wb_rst_n;
wire	sync_ddr2_rst_n;


wire	sync_eth_rst_n;


wire	sys_clk_pad_ibufg;

wire	dcm0_clk0_prebufg, dcm0_clk0;
wire	dcm0_clk90_prebufg, dcm0_clk90;
wire	dcm0_clkfx_prebufg, dcm0_clkfx;
wire	dcm0_clkdv_prebufg, dcm0_clkdv;
wire	dcm0_clk2x_prebufg, dcm0_clk2x;
wire	dcm0_locked;

wire	pll0_clkfb;
wire	pll0_locked;
wire	pll0_clk1_prebufg, pll0_clk1;

IBUFG sys_clk_in_ibufg (
	.I	(sys_clk_pad_i),
	.O	(sys_clk_pad_ibufg)
);



DCM_SP #(

	.CLKFX_MULTIPLY	(8),
	.CLKFX_DIVIDE	(3),


	.CLKDV_DIVIDE	(2.0)
) dcm0 (

	.CLK0		(dcm0_clk0_prebufg),
	.CLK180		(),
	.CLK270		(),
	.CLK2X180	(),
	.CLK2X		(dcm0_clk2x_prebufg),
	.CLK90		(dcm0_clk90_prebufg),
	.CLKDV		(dcm0_clkdv_prebufg),
	.CLKFX180	(dcm0_clkfx_prebufg),
	.CLKFX		(),
	.LOCKED		(dcm0_locked),

	.CLKFB		(dcm0_clk0),
	.CLKIN		(sys_clk_pad_ibufg),
	.PSEN		(1'b0),
	.RST		(async_rst_o)
);


PLL_BASE #(
	.BANDWIDTH("OPTIMIZED"),

	.CLKFBOUT_MULT(5),
	.CLKFBOUT_PHASE(0.0),
	.CLKIN_PERIOD(10),
	.CLKOUT1_DIVIDE(10),
	.CLKOUT2_DIVIDE(1),
	.CLKOUT3_DIVIDE(1),
	.CLKOUT4_DIVIDE(1),
	.CLKOUT5_DIVIDE(1),
	.CLKOUT1_DUTY_CYCLE(0.5),
	.CLKOUT2_DUTY_CYCLE(0.5),
	.CLKOUT3_DUTY_CYCLE(0.5),
	.CLKOUT4_DUTY_CYCLE(0.5),
	.CLKOUT5_DUTY_CYCLE(0.5),
	.CLKOUT1_PHASE(0.0),
	.CLKOUT2_PHASE(0.0),
	.CLKOUT3_PHASE(0.0),
	.CLKOUT4_PHASE(0.0),
	.CLKOUT5_PHASE(0.0),
	.CLK_FEEDBACK("CLKFBOUT"),
	.COMPENSATION("DCM2PLL"),
	.DIVCLK_DIVIDE(1),
	.REF_JITTER(0.1),
	.RESET_ON_LOSS_OF_LOCK("FALSE")
) pll0 (
	.CLKFBOUT	(pll0_clkfb),
	.CLKOUT1	(pll0_clk1_prebufg),
	.CLKOUT2	(),
	.CLKOUT3	(CLKOUT3),
	.CLKOUT4	(CLKOUT4),
	.CLKOUT5	(CLKOUT5),
	.LOCKED		(pll0_locked),
	.CLKFBIN	(pll0_clkfb),
	.CLKIN		(dcm0_clk90_prebufg),
	.RST		(async_rst_o)
);

BUFG dcm0_clk0_bufg
       (
	.O	(dcm0_clk0),

	.I	(dcm0_clk0_prebufg)
);

BUFG dcm0_clk2x_bufg
       (
	.O	(dcm0_clk2x),

	.I	(dcm0_clk2x_prebufg)
);

BUFG dcm0_clkfx_bufg
       (
	.O	(dcm0_clkfx),

	.I	(dcm0_clkfx_prebufg)
);



BUFG pll0_clk1_bufg
       (
	.O	(pll0_clk1),

	.I	(pll0_clk1_prebufg));

assign wb_clk_o = pll0_clk1;
assign sync_wb_rst_n = pll0_locked;
assign sync_ddr2_rst_n = dcm0_locked;

assign ddr2_if_clk_o = dcm0_clkfx;
assign clk100_o = dcm0_clk0;

assign dvi_clk_o = dcm0_clkdv_prebufg;







reg [15:0] 	   wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst_o)
	if (async_rst_o)
		wb_rst_shr <= 16'hffff;
	else
		wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_wb_rst_n)};

assign wb_rst_o = wb_rst_shr[15];

assign ddr2_if_rst_o = async_rst_o;

endmodule
module clkgen
       (

	input  sys_clk_pad_i,

	input  rst_n_pad_i,

	output async_rst_o,


	output wb_clk_o,
	output wb_rst_o,


	input  tck_pad_i,
	output dbg_tck_o,


	output dvi_clk_o,


	output ddr2_if_clk_o,
	output ddr2_if_rst_o,
	output clk100_o
);



wire	async_rst_n;

assign async_rst_n = rst_n_pad_i;


assign async_rst_o = ~async_rst_n;

assign dbg_tck_o = tck_pad_i;






wire	sync_wb_rst_n;
wire	sync_ddr2_rst_n;


wire	sync_eth_rst_n;


wire	sys_clk_pad_ibufg;

wire	dcm0_clk0_prebufg, dcm0_clk0;
wire	dcm0_clk90_prebufg, dcm0_clk90;
wire	dcm0_clkfx_prebufg, dcm0_clkfx;
wire	dcm0_clkdv_prebufg, dcm0_clkdv;
wire	dcm0_clk2x_prebufg, dcm0_clk2x;
wire	dcm0_locked;

wire	pll0_clkfb;
wire	pll0_locked;
wire	pll0_clk1_prebufg, pll0_clk1;

IBUFG sys_clk_in_ibufg (
	.I	(sys_clk_pad_i),
	.O	(sys_clk_pad_ibufg)
);



DCM_SP #(

	.CLKFX_MULTIPLY	(8),
	.CLKFX_DIVIDE	(3),


	.CLKDV_DIVIDE	(2.0)
) dcm0 (

	.CLK0		(dcm0_clk0_prebufg),
	.CLK180		(),
	.CLK270		(),
	.CLK2X180	(),
	.CLK2X		(dcm0_clk2x_prebufg),
	.CLK90		(dcm0_clk90_prebufg),
	.CLKDV		(dcm0_clkdv_prebufg),
	.CLKFX180	(dcm0_clkfx_prebufg),
	.CLKFX		(),
	.LOCKED		(dcm0_locked),

	.CLKFB		(dcm0_clk0),
	.CLKIN		(sys_clk_pad_ibufg),
	.PSEN		(1'b0),
	.RST		(async_rst_o)
);


PLL_BASE #(
	.BANDWIDTH("OPTIMIZED"),

	.CLKFBOUT_MULT(5),
	.CLKFBOUT_PHASE(0.0),
	.CLKIN_PERIOD(10),
	.CLKOUT1_DIVIDE(10),
	.CLKOUT2_DIVIDE(1),
	.CLKOUT3_DIVIDE(1),
	.CLKOUT4_DIVIDE(1),
	.CLKOUT5_DIVIDE(1),
	.CLKOUT1_DUTY_CYCLE(0.5),
	.CLKOUT2_DUTY_CYCLE(0.5),
	.CLKOUT3_DUTY_CYCLE(0.5),
	.CLKOUT4_DUTY_CYCLE(0.5),
	.CLKOUT5_DUTY_CYCLE(0.5),
	.CLKOUT1_PHASE(0.0),
	.CLKOUT2_PHASE(0.0),
	.CLKOUT3_PHASE(0.0),
	.CLKOUT4_PHASE(0.0),
	.CLKOUT5_PHASE(0.0),
	.CLK_FEEDBACK("CLKFBOUT"),
	.COMPENSATION("DCM2PLL"),
	.DIVCLK_DIVIDE(1),
	.REF_JITTER(0.1),
	.RESET_ON_LOSS_OF_LOCK("FALSE")
) pll0 (
	.CLKFBOUT	(pll0_clkfb),
	.CLKOUT1	(pll0_clk1_prebufg),
	.CLKOUT2	(),
	.CLKOUT3	(CLKOUT3),
	.CLKOUT4	(CLKOUT4),
	.CLKOUT5	(CLKOUT5),
	.LOCKED		(pll0_locked),
	.CLKFBIN	(pll0_clkfb),
	.CLKIN		(dcm0_clk90_prebufg),
	.RST		(async_rst_o)
);

BUFG dcm0_clk0_bufg
       (
	.O	(dcm0_clk0),

	.I	(dcm0_clk0_prebufg)
);

BUFG dcm0_clk2x_bufg
       (
	.O	(dcm0_clk2x),

	.I	(dcm0_clk2x_prebufg)
);

BUFG dcm0_clkfx_bufg
       (
	.O	(dcm0_clkfx),

	.I	(dcm0_clkfx_prebufg)
);



BUFG pll0_clk1_bufg
       (
	.O	(pll0_clk1),

	.I	(pll0_clk1_prebufg));

assign wb_clk_o = pll0_clk1;
assign sync_wb_rst_n = pll0_locked;
assign sync_ddr2_rst_n = dcm0_locked;

assign ddr2_if_clk_o = dcm0_clkfx;
assign clk100_o = dcm0_clk0;

assign dvi_clk_o = dcm0_clkdv_prebufg;







reg [15:0] 	   wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst_o)
	if (async_rst_o)
		wb_rst_shr <= 16'hffff;
	else
		wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_wb_rst_n)};

assign wb_rst_o = wb_rst_shr[15];

assign ddr2_if_rst_o = async_rst_o;

endmodule