data/full_repos/permissive/2084115/rtl/peripheral/jelly_ddr_sdram_oddr.v
1: b"%Error: data/full_repos/permissive/2084115/rtl/peripheral/jelly_ddr_sdram_oddr.v:32: Cannot find file containing module: 'OBUF'\n        OBUF\n        ^~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/peripheral,data/full_repos/permissive/2084115/OBUF\n             data/full_repos/permissive/2084115/rtl/peripheral,data/full_repos/permissive/2084115/OBUF.v\n             data/full_repos/permissive/2084115/rtl/peripheral,data/full_repos/permissive/2084115/OBUF.sv\n             OBUF\n             OBUF.v\n             OBUF.sv\n             obj_dir/OBUF\n             obj_dir/OBUF.v\n             obj_dir/OBUF.sv\n%Error: data/full_repos/permissive/2084115/rtl/peripheral/jelly_ddr_sdram_oddr.v:42: Cannot find file containing module: 'ODDR2'\n        ODDR2\n        ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module jelly_ddr_sdram_oddr
        #(
            parameter                       INIT   = 1'b0,
            parameter                       WIDTH  = 1
        )
        (
            input   wire                    clk,
            
            input   wire    [WIDTH-1:0]     in_even,
            input   wire    [WIDTH-1:0]     in_odd,
            output  wire    [WIDTH-1:0]     out
        );
    
    wire    [WIDTH-1:0]     ddr_q;
    
    generate
    genvar  i;
    for ( i = 0; i < WIDTH; i = i + 1 ) begin : oddr
        OBUF
                #(
                    .IOSTANDARD         ("SSTL2_I")
                )
            i_obuf
                (
                    .O                  (out[i]),
                    .I                  (ddr_q[i])
                );
        
        ODDR2
                #(
                    .DDR_ALIGNMENT      ("NONE"),
                    .INIT               (INIT),
                    .SRTYPE             ("SYNC")
                )
            i_oddr_dq
                (
                    .Q                  (ddr_q[i]),
                    .C0                 (clk),
                    .C1                 (~clk),
                    .CE                 (1'b1),
                    .D0                 (in_even[i]),
                    .D1                 (in_odd[i]),
                    .R                  (1'b0),
                    .S                  (1'b0)
                );
    end
    endgenerate
    
endmodule
module jelly_ddr_sdram_oddr
        #(
            parameter                       INIT   = 1'b0,
            parameter                       WIDTH  = 1
        )
        (
            input   wire                    clk,
            
            input   wire    [WIDTH-1:0]     in_even,
            input   wire    [WIDTH-1:0]     in_odd,
            output  wire    [WIDTH-1:0]     out
        );

    
    wire    [WIDTH-1:0]     ddr_q;
    
    generate
    genvar  i;
    for ( i = 0; i < WIDTH; i = i + 1 ) begin : oddr
        OBUF
                #(
                    .IOSTANDARD         ("SSTL2_I")
                )
            i_obuf
                (
                    .O                  (out[i]),
                    .I                  (ddr_q[i])
                );
        
        ODDR2
                #(
                    .DDR_ALIGNMENT      ("NONE"),
                    .INIT               (INIT),
                    .SRTYPE             ("SYNC")
                )
            i_oddr_dq
                (
                    .Q                  (ddr_q[i]),
                    .C0                 (clk),
                    .C1                 (~clk),
                    .CE                 (1'b1),
                    .D0                 (in_even[i]),
                    .D1                 (in_odd[i]),
                    .R                  (1'b0),
                    .S                  (1'b0)
                );
    end
    endgenerate
    
endmodule