data/full_repos/permissive/162696624/Traffic Light.v
 line:32: before: "["
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/162696624/Traffic\n        ... Looked in:\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.sv\n             data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624/Traffic.sv\n             obj_dir/data/full_repos/permissive/162696624/Traffic\n             obj_dir/data/full_repos/permissive/162696624/Traffic.v\n             obj_dir/data/full_repos/permissive/162696624/Traffic.sv\n%Error: Cannot find file containing module: Light.v\n%Error: Exiting due to 2 error(s)\n'
module traffic_light(A,B,R,AT,BT,CLK,ATH,ATL,AL,BL,finished1,finished2);
  input A,B,R,AT,BT,CLK;
  output AL,BL,finished1,finished2;
  output [3:0]ATH;
  output [3:0]ATL;
  wire [3:0]L;
  wire [3:0]ATL2;
  wire [3:0]ATH2;
  wire PO,S,e,AL1,BL1,AL2,BL2,EN;
  assign EN=~(PO|e);
  assign PO=A|B|R;
  assign S=e&~PO;
  mux4x2 mx(AL1,AL2,BL1,BL2,S,AL,BL);
  main m(A|e,B,~R,CLK,L,BL1,AL1,finished1);
  number_set n(ATL2,ATH2,EN,L[0],L[1],L[2],L[3],CLK,~R);
  blink b(finished2,AL2,BL2,e,PO,AT,BT,CLK,~R);  
  assign ATL[0]=PO|ATL2[0];
  assign ATH[0]=PO|ATH2[0];
  assign ATL[1]=PO|ATL2[1];
  assign ATH[1]=PO|ATH2[1];
  assign ATL[2]=PO|ATL2[2];
  assign ATH[2]=PO|ATH2[2];
  assign ATL[3]=PO|ATL2[3];
  assign ATH[3]=PO|ATH2[3];
endmodule
module traffic_light(A,B,R,AT,BT,CLK,ATH,ATL,AL,BL,finished1,finished2);

  input A,B,R,AT,BT,CLK;
  output AL,BL,finished1,finished2;
  output [3:0]ATH;
  output [3:0]ATL;
  wire [3:0]L;
  wire [3:0]ATL2;
  wire [3:0]ATH2;
  wire PO,S,e,AL1,BL1,AL2,BL2,EN;
  assign EN=~(PO|e);
  assign PO=A|B|R;
  assign S=e&~PO;
  mux4x2 mx(AL1,AL2,BL1,BL2,S,AL,BL);
  main m(A|e,B,~R,CLK,L,BL1,AL1,finished1);
  number_set n(ATL2,ATH2,EN,L[0],L[1],L[2],L[3],CLK,~R);
  blink b(finished2,AL2,BL2,e,PO,AT,BT,CLK,~R);  
  assign ATL[0]=PO|ATL2[0];
  assign ATH[0]=PO|ATH2[0];
  assign ATL[1]=PO|ATL2[1];
  assign ATH[1]=PO|ATH2[1];
  assign ATL[2]=PO|ATL2[2];
  assign ATH[2]=PO|ATH2[2];
  assign ATL[3]=PO|ATL2[3];
  assign ATH[3]=PO|ATH2[3];
endmodule