data/full_repos/permissive/108561032/control1.v
 line:36: before: "parameter"
data/verilator_xmls/eb05ab33-faf4-4bd6-8aea-2a9ac98c085f.xml
module control1(reset,clk,Control,RegDest,ALUOp,FuenteALU,Controls1,Saltoincond);

    input [9:0] Control;
    input  clk;
    input reset;
    output reg [9:0] Controls1;
        
    output reg RegDest;
    output reg Saltoincond;


    output reg [1:0]ALUOp;

    output reg FuenteALU;

    

                                                

always   @(posedge clk)
begin

Controls1 = Control;   
Saltoincond  = Control[9];
RegDest      = Control[8];
FuenteALU    = Control[7];






ALUOp        = Control[1:0];
    

    

end     
endmodule
module control1(reset,clk,Control,RegDest,ALUOp,FuenteALU,Controls1,Saltoincond);


    input [9:0] Control;
    input  clk;
    input reset;
    output reg [9:0] Controls1;
        
    output reg RegDest;
    output reg Saltoincond;


    output reg [1:0]ALUOp;

    output reg FuenteALU;

    

                                                

always   @(posedge clk)
begin

Controls1 = Control;   
Saltoincond  = Control[9];
RegDest      = Control[8];
FuenteALU    = Control[7];






ALUOp        = Control[1:0];
    

    

end     
endmodule