data/full_repos/permissive/143286506/CPU.v
None: at end of input
1: b'%Error: data/full_repos/permissive/143286506/CPU.v:1: Cannot find include file: execute\n`include "execute" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143286506,data/full_repos/permissive/143286506/execute\n             data/full_repos/permissive/143286506,data/full_repos/permissive/143286506/execute.v\n             data/full_repos/permissive/143286506,data/full_repos/permissive/143286506/execute.sv\n             execute\n             execute.v\n             execute.sv\n             obj_dir/execute\n             obj_dir/execute.v\n             obj_dir/execute.sv\n%Error: Exiting due to 1 error(s)\n'
module CPU(clk,rstd);
    input clk;
    input rstd;
    wire [31:0]ins;
    reg [31:0]pc;
    
    wire [31:0] imm_i;
    wire [31:0] imm_s;
    wire [12:0] imm_b;
    wire [19:0] imm_u;
    wire [19:0] imm_j;

    wire [31:0]r1;
    wire [31:0]r2;
    wire [31:0] alures;
    wire [31:0] memres;
    wire [31:0] CSRres;
    wire [31:0] lastres;
    wire [31:0] nextpc;

    wire [3:0]selectop;
    wire wren;
    wire npcren;
    wire csren;

    fetch fetch1(pc,ins);

    

    decode decode1(ins,selectop,wren,npcen,csren);

    assign imm_i = $signed(ins[31:20]);
    assign imm_s = $signed({ins[31:25], ins[11:7]});
    assign imm_b = {ins[31], ins[7], ins[30:25], ins[11:8]};
    assign imm_u = ins[31:12];
    assign imm_j = {ins[31], ins[19:12], ins[20], ins[30:21]};


    

    alu alu1(r1,r2,ins[24:20],imm_i,alures,ins[14:12],ins[30],ins[5]);
    mem_access mem_access1(clk,r1,r2,imm_i,imm_s,memres,ins[14:12],ins[5]);
    CSR CSR1(r1,ins[19:15],ins[31:20],CSRres,ins[14:12],csren);
    select select1(alures,memres,CSRres,lastres,selectop);



    npc npc1(r1,r2,imm_b,pc,nextpc,ins[14:12],npcen);
    always @(negedge rstd or posedge clk)
     begin
	if (rstd == 0) pc <= 32'h00000000;
	  else if (clk == 1) pc <= nextpc;
     end
    reg_file reg_file1(clk, rstd, lastres, ins[19:15], ins[24:20], ins[11:7], wren, r1, r2);


endmodule
module CPU(clk,rstd);

    input clk;
    input rstd;
    wire [31:0]ins;
    reg [31:0]pc;
    
    wire [31:0] imm_i;
    wire [31:0] imm_s;
    wire [12:0] imm_b;
    wire [19:0] imm_u;
    wire [19:0] imm_j;

    wire [31:0]r1;
    wire [31:0]r2;
    wire [31:0] alures;
    wire [31:0] memres;
    wire [31:0] CSRres;
    wire [31:0] lastres;
    wire [31:0] nextpc;

    wire [3:0]selectop;
    wire wren;
    wire npcren;
    wire csren;

    fetch fetch1(pc,ins);

    

    decode decode1(ins,selectop,wren,npcen,csren);

    assign imm_i = $signed(ins[31:20]);
    assign imm_s = $signed({ins[31:25], ins[11:7]});
    assign imm_b = {ins[31], ins[7], ins[30:25], ins[11:8]};
    assign imm_u = ins[31:12];
    assign imm_j = {ins[31], ins[19:12], ins[20], ins[30:21]};


    

    alu alu1(r1,r2,ins[24:20],imm_i,alures,ins[14:12],ins[30],ins[5]);
    mem_access mem_access1(clk,r1,r2,imm_i,imm_s,memres,ins[14:12],ins[5]);
    CSR CSR1(r1,ins[19:15],ins[31:20],CSRres,ins[14:12],csren);
    select select1(alures,memres,CSRres,lastres,selectop);



    npc npc1(r1,r2,imm_b,pc,nextpc,ins[14:12],npcen);
    always @(negedge rstd or posedge clk)
     begin
	if (rstd == 0) pc <= 32'h00000000;
	  else if (clk == 1) pc <= nextpc;
     end
    reg_file reg_file1(clk, rstd, lastres, ins[19:15], ins[24:20], ins[11:7], wren, r1, r2);


endmodule