data/full_repos/permissive/148200700/Quartus/designFiles/ip/KBandIPsubPro/KBandIPsubPro_KBandInput_2/KBandIPsubPro_KBandInput_2_bb.v
data/verilator_xmls/57844a2d-1ed5-46c0-899f-18e860e5add6.xml
module KBandIPsubPro_KBandInput_2 (
		input  wire         clock_clk,
		input  wire         reset_n_reset_n,
		input  wire [31:0]  csr_writedata,
		input  wire         csr_write,
		input  wire [3:0]   csr_byteenable,
		output wire [31:0]  csr_readdata,
		input  wire         csr_read,
		input  wire [2:0]   csr_address,
		input  wire         descriptor_slave_write,
		output wire         descriptor_slave_waitrequest,
		input  wire [127:0] descriptor_slave_writedata,
		input  wire [15:0]  descriptor_slave_byteenable,
		output wire         csr_irq_irq,
		output wire [31:0]  mm_read_address,
		output wire         mm_read_read,
		input  wire [7:0]   mm_read_readdata,
		input  wire         mm_read_waitrequest,
		input  wire         mm_read_readdatavalid,
		output wire [7:0]   st_source_data,
		output wire         st_source_valid,
		input  wire         st_source_ready
	);
endmodule
module KBandIPsubPro_KBandInput_2 (
		input  wire         clock_clk,
		input  wire         reset_n_reset_n,
		input  wire [31:0]  csr_writedata,
		input  wire         csr_write,
		input  wire [3:0]   csr_byteenable,
		output wire [31:0]  csr_readdata,
		input  wire         csr_read,
		input  wire [2:0]   csr_address,
		input  wire         descriptor_slave_write,
		output wire         descriptor_slave_waitrequest,
		input  wire [127:0] descriptor_slave_writedata,
		input  wire [15:0]  descriptor_slave_byteenable,
		output wire         csr_irq_irq,
		output wire [31:0]  mm_read_address,
		output wire         mm_read_read,
		input  wire [7:0]   mm_read_readdata,
		input  wire         mm_read_waitrequest,
		input  wire         mm_read_readdatavalid,
		output wire [7:0]   st_source_data,
		output wire         st_source_valid,
		input  wire         st_source_ready
	);

endmodule