data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v
 line:35: before: "#"
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:17: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("pruebaByteStripping.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:18: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #0\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:55: Unsupported: Ignoring delay on this delayed statement.\n  always #0.5 clk1Mhz <= ~clk1Mhz;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_striping/tester_byte_striping.v:58: Unsupported: Ignoring delay on this delayed statement.\n  always #2 clk250k <= ~clk250k;\n         ^\n%Error: Exiting due to 2 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester_byte_striping (
  input wire [7:0] stripedLane0,
  input wire [7:0] stripedLane1,
  input wire [7:0] stripedLane2,
  input wire [7:0] stripedLane3,
  input wire byteStripingVLD,

  output reg [7:0] byteStripingIN,
  output reg laneVLD,
  output reg clk250k,
  output reg clk1Mhz,
  output reg conteo,
  output reg reset
  );

  initial begin
    $dumpfile("pruebaByteStripping.vcd");
    $dumpvars;

    #0
    reset = 0;
    laneVLD = 1'b1;

    #1
    reset = 1;
    laneVLD = 1'b1;
    byteStripingIN = 8'b00000000;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b00001111;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b11110000;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b11111111;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b11111111;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b11110000;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b00001111;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b00000000;
    #1

    $finish;
  end

  initial clk1Mhz <=0;
  always #0.5 clk1Mhz <= ~clk1Mhz;

  initial clk250k <=0;
  always #2 clk250k <= ~clk250k;






endmodule
module tester_byte_striping (
  input wire [7:0] stripedLane0,
  input wire [7:0] stripedLane1,
  input wire [7:0] stripedLane2,
  input wire [7:0] stripedLane3,
  input wire byteStripingVLD,

  output reg [7:0] byteStripingIN,
  output reg laneVLD,
  output reg clk250k,
  output reg clk1Mhz,
  output reg conteo,
  output reg reset
  );


  initial begin
    $dumpfile("pruebaByteStripping.vcd");
    $dumpvars;

    #0
    reset = 0;
    laneVLD = 1'b1;

    #1
    reset = 1;
    laneVLD = 1'b1;
    byteStripingIN = 8'b00000000;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b00001111;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b11110000;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b11111111;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b11111111;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b11110000;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b00001111;
    #1
    laneVLD = 1'b1;
    byteStripingIN = 8'b00000000;
    #1

    $finish;
  end

  initial clk1Mhz <=0;
  always #0.5 clk1Mhz <= ~clk1Mhz;

  initial clk250k <=0;
  always #2 clk250k <= ~clk250k;






endmodule