data/full_repos/permissive/167489907/DE0 Stuff/Fib_tb.v
1: b'%Error: Cannot find file containing module: Stuff,data/full_repos/permissive/167489907\n        ... Looked in:\n             data/full_repos/permissive/167489907/DE0/Stuff,data/full_repos/permissive/167489907\n             data/full_repos/permissive/167489907/DE0/Stuff,data/full_repos/permissive/167489907.v\n             data/full_repos/permissive/167489907/DE0/Stuff,data/full_repos/permissive/167489907.sv\n             Stuff,data/full_repos/permissive/167489907\n             Stuff,data/full_repos/permissive/167489907.v\n             Stuff,data/full_repos/permissive/167489907.sv\n             obj_dir/Stuff,data/full_repos/permissive/167489907\n             obj_dir/Stuff,data/full_repos/permissive/167489907.v\n             obj_dir/Stuff,data/full_repos/permissive/167489907.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/167489907/DE0\n%Error: Cannot find file containing module: Stuff/Fib_tb.v\n%Error: Exiting due to 3 error(s)\n'
module Fib_tb;


reg clk, rst;
wire [3:0] status;
wire [2:0] constant_sel;
wire [63:0] D, reg_out, r1, r2, r3, r4, r5, r6, r7;
wire [33:0] control_word;
wire [31:0] IR_Out;
wire [1:0] EX0_sel;
wire AS, PC_Sel, K_Sel, IL, SL, C0, MW, RW;
wire [1:0] NS, DS, PS;
wire [4:0] FS, DA, SA, SB;
wire [63:0] ALU_out, K;
wire [1:0] state;
wire [31:0] PC_out;
wire [31:0] ADDR;

wire [9:0] LEDG;
wire [6:0] HEX3, HEX2, HEX1, HEX0;

Fib dut(.CLOCK_50(clk), .BUTTON(rst), .LEDG(LEDG), .HEX3(HEX3), .HEX2(HEX2), .HEX1(HEX1), .HEX0(HEX0));

assign ADDR = dut.CPU.core.ADDR;
assign reg_out = dut.register;
assign status = dut.status;
assign r1 = dut.CPU.core.r1;
assign r2 = dut.CPU.core.r2;
assign r3 = dut.CPU.core.r3;
assign r4 = dut.CPU.core.r4;
assign r5 = dut.CPU.core.r5;
assign r6 = dut.CPU.core.r6;
assign r7 = dut.CPU.core.r7;
assign D = dut.CPU.core.D;
assign ALU_out = dut.CPU.core.regfile_alu_ram.F;

assign PC_out = dut.CPU.core.PC_out;
assign K = dut.CPU.K;
assign control_word = dut.CPU.control_word;
assign state = dut.CPU.CU.state;
assign IR_Out = dut.CPU.core.IR_Out;
assign EX0_sel = dut.CPU.CU.EX0_sel;
assign AS = dut.CPU.AS;
assign PC_Sel = dut.CPU.PC_Sel;
assign K_Sel = dut.CPU.K_Sel;
assign constant_sel = dut.CPU.CU.constant_sel;
assign IL = dut.CPU.CPU.IL;
assign SL = dut.CPU.CPU.SL;
assign C0 = dut.CPU.C0;
assign MW = dut.CPU.MW;
assign RW = dut.CPU.RW;
assign NS = dut.CPU.NS;
assign DS = dut.CPU.DS;
assign PS = dut.CPU.PS;
assign FS = dut.CPU.FS;
assign DA = dut.CPU.DA;
assign SA = dut.CPU.SA;
assign SB = dut.CPU.SB;




























`timescale 1s/1s 

always begin
	#10 clk = ~clk;
end
	
initial begin
	clk <= 1'b0;
	rst <= 1'b0;
	#10;
	rst <= 1'b1;
	
	#50000;
	$stop;
end
endmodule
module Fib_tb;



reg clk, rst;
wire [3:0] status;
wire [2:0] constant_sel;
wire [63:0] D, reg_out, r1, r2, r3, r4, r5, r6, r7;
wire [33:0] control_word;
wire [31:0] IR_Out;
wire [1:0] EX0_sel;
wire AS, PC_Sel, K_Sel, IL, SL, C0, MW, RW;
wire [1:0] NS, DS, PS;
wire [4:0] FS, DA, SA, SB;
wire [63:0] ALU_out, K;
wire [1:0] state;
wire [31:0] PC_out;
wire [31:0] ADDR;

wire [9:0] LEDG;
wire [6:0] HEX3, HEX2, HEX1, HEX0;

Fib dut(.CLOCK_50(clk), .BUTTON(rst), .LEDG(LEDG), .HEX3(HEX3), .HEX2(HEX2), .HEX1(HEX1), .HEX0(HEX0));

assign ADDR = dut.CPU.core.ADDR;
assign reg_out = dut.register;
assign status = dut.status;
assign r1 = dut.CPU.core.r1;
assign r2 = dut.CPU.core.r2;
assign r3 = dut.CPU.core.r3;
assign r4 = dut.CPU.core.r4;
assign r5 = dut.CPU.core.r5;
assign r6 = dut.CPU.core.r6;
assign r7 = dut.CPU.core.r7;
assign D = dut.CPU.core.D;
assign ALU_out = dut.CPU.core.regfile_alu_ram.F;

assign PC_out = dut.CPU.core.PC_out;
assign K = dut.CPU.K;
assign control_word = dut.CPU.control_word;
assign state = dut.CPU.CU.state;
assign IR_Out = dut.CPU.core.IR_Out;
assign EX0_sel = dut.CPU.CU.EX0_sel;
assign AS = dut.CPU.AS;
assign PC_Sel = dut.CPU.PC_Sel;
assign K_Sel = dut.CPU.K_Sel;
assign constant_sel = dut.CPU.CU.constant_sel;
assign IL = dut.CPU.CPU.IL;
assign SL = dut.CPU.CPU.SL;
assign C0 = dut.CPU.C0;
assign MW = dut.CPU.MW;
assign RW = dut.CPU.RW;
assign NS = dut.CPU.NS;
assign DS = dut.CPU.DS;
assign PS = dut.CPU.PS;
assign FS = dut.CPU.FS;
assign DA = dut.CPU.DA;
assign SA = dut.CPU.SA;
assign SB = dut.CPU.SB;




























`timescale 1s/1s 

always begin
	#10 clk = ~clk;
end
	
initial begin
	clk <= 1'b0;
	rst <= 1'b0;
	#10;
	rst <= 1'b1;
	
	#50000;
	$stop;
end
endmodule