data/full_repos/permissive/136510272/projects/z80.proc/com_clock_divisor.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/z80.proc/com_clock_divisor.v:21: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance com_clock_divisor\nreg [3:0] div     = 1\'b0;\n                    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/z80.proc/com_clock_divisor.v:22: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                                             : ... In instance com_clock_divisor\nreg [1:0] delay   = 3\'h2;\n                    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/z80.proc/com_clock_divisor.v:37: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance com_clock_divisor\n        div     <= 1\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/z80.proc/com_clock_divisor.v:28: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'delay\' generates 2 bits.\n                                                                                             : ... In instance com_clock_divisor\n    if (delay) begin\n    ^~\n%Error: Exiting due to 4 warning(s)\n'
module com_clock_divisor(

    input  wire clk,
    output reg  clk_z80,
            




    input  wire [3:0] param_div
);

reg [3:0] div     = 1'b0;
reg [1:0] delay   = 3'h2;
initial   clk_z80 = 1'b0;

always @(posedge clk) begin


    if (delay) begin
    
        delay <= delay - 1;
            
    end
    

    else if (div == param_div) begin

        div     <= 1'b0;
        clk_z80 <= clk_z80 + 1'b1;

    end else begin

        div <= div + 1'b1;

    end

end

endmodule
module com_clock_divisor(

    input  wire clk,
    output reg  clk_z80,
            




    input  wire [3:0] param_div
);


reg [3:0] div     = 1'b0;
reg [1:0] delay   = 3'h2;
initial   clk_z80 = 1'b0;

always @(posedge clk) begin


    if (delay) begin
    
        delay <= delay - 1;
            
    end
    

    else if (div == param_div) begin

        div     <= 1'b0;
        clk_z80 <= clk_z80 + 1'b1;

    end else begin

        div <= div + 1'b1;

    end

end

endmodule