data/full_repos/permissive/165126488/HDMI_test.v
1: b'%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:78: Operator AND expects 4 bits on the LHS, but LHS\'s REPLICATE generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance_acc_inc = balance - ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0));\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:78: Operator NOT expects 4 bits on the LHS, but LHS\'s LOGOR generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance_acc_inc = balance - ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0));\n                                                                      ^\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:37: Cannot find file containing module: \'DCM_SP\'\nDCM_SP #(.CLKFX_MULTIPLY(10)) DCM_TMDS_inst(.CLKIN(pixclk), .CLKFX(DCM_TMDS_CLKFX), .RST(1\'b0));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165126488,data/full_repos/permissive/165126488/DCM_SP\n             data/full_repos/permissive/165126488,data/full_repos/permissive/165126488/DCM_SP.v\n             data/full_repos/permissive/165126488,data/full_repos/permissive/165126488/DCM_SP.sv\n             DCM_SP\n             DCM_SP.v\n             DCM_SP.sv\n             obj_dir/DCM_SP\n             obj_dir/DCM_SP.v\n             obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:38: Cannot find file containing module: \'BUFG\'\nBUFG BUFG_TMDSp(.I(DCM_TMDS_CLKFX), .O(clk_TMDS));\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:48: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s SEL generates 9 bits.\n                                                                   : ... In instance HDMI_test\n TMDS_shift_red   <= TMDS_shift_load ? TMDS_red   : TMDS_shift_red  [9:1];\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:49: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s SEL generates 9 bits.\n                                                                   : ... In instance HDMI_test\n TMDS_shift_green <= TMDS_shift_load ? TMDS_green : TMDS_shift_green[9:1];\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:50: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s SEL generates 9 bits.\n                                                                   : ... In instance HDMI_test\n TMDS_shift_blue  <= TMDS_shift_load ? TMDS_blue  : TMDS_shift_blue [9:1]; \n                                     ^\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:54: Cannot find file containing module: \'OBUFDS\'\nOBUFDS OBUFDS_red  (.I(TMDS_shift_red  [0]), .O(TMDSp[2]), .OB(TMDSn[2]));\n^~~~~~\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:55: Cannot find file containing module: \'OBUFDS\'\nOBUFDS OBUFDS_green(.I(TMDS_shift_green[0]), .O(TMDSp[1]), .OB(TMDSn[1]));\n^~~~~~\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:56: Cannot find file containing module: \'OBUFDS\'\nOBUFDS OBUFDS_blue (.I(TMDS_shift_blue [0]), .O(TMDSp[0]), .OB(TMDSn[0]));\n^~~~~~\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:57: Cannot find file containing module: \'OBUFDS\'\nOBUFDS OBUFDS_clock(.I(pixclk), .O(TMDSp_clock), .OB(TMDSn_clock));\n^~~~~~\n%Error: Exiting due to 6 error(s), 21 warning(s)\n'
module TMDS_encoder(
	input clk,
	input [7:0] VD,
	input [1:0] CD,
	input VDE,
	output reg [9:0] TMDS = 0
);

wire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];
wire XNOR = (Nb1s>4'd4) || (Nb1s==4'd4 && VD[0]==1'b0);
wire [8:0] q_m = {~XNOR, q_m[6:0] ^ VD[7:1] ^ {7{XNOR}}, VD[0]};

reg [3:0] balance_acc = 0;
wire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4'd4;
wire balance_sign_eq = (balance[3] == balance_acc[3]);
wire invert_q_m = (balance==0 || balance_acc==0) ? ~q_m[8] : balance_sign_eq;
wire [3:0] balance_acc_inc = balance - ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0));
wire [3:0] balance_acc_new = invert_q_m ? balance_acc-balance_acc_inc : balance_acc+balance_acc_inc;
wire [9:0] TMDS_data = {invert_q_m, q_m[8], q_m[7:0] ^ {8{invert_q_m}}};
wire [9:0] TMDS_code = CD[1] ? (CD[0] ? 10'b1010101011 : 10'b0101010100) : (CD[0] ? 10'b0010101011 : 10'b1101010100);

always @(posedge clk) TMDS <= VDE ? TMDS_data : TMDS_code;
always @(posedge clk) balance_acc <= VDE ? balance_acc_new : 4'h0;
endmodule
module TMDS_encoder(
	input clk,
	input [7:0] VD,
	input [1:0] CD,
	input VDE,
	output reg [9:0] TMDS = 0
);


wire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];
wire XNOR = (Nb1s>4'd4) || (Nb1s==4'd4 && VD[0]==1'b0);
wire [8:0] q_m = {~XNOR, q_m[6:0] ^ VD[7:1] ^ {7{XNOR}}, VD[0]};

reg [3:0] balance_acc = 0;
wire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4'd4;
wire balance_sign_eq = (balance[3] == balance_acc[3]);
wire invert_q_m = (balance==0 || balance_acc==0) ? ~q_m[8] : balance_sign_eq;
wire [3:0] balance_acc_inc = balance - ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0));
wire [3:0] balance_acc_new = invert_q_m ? balance_acc-balance_acc_inc : balance_acc+balance_acc_inc;
wire [9:0] TMDS_data = {invert_q_m, q_m[8], q_m[7:0] ^ {8{invert_q_m}}};
wire [9:0] TMDS_code = CD[1] ? (CD[0] ? 10'b1010101011 : 10'b0101010100) : (CD[0] ? 10'b0010101011 : 10'b1101010100);

always @(posedge clk) TMDS <= VDE ? TMDS_data : TMDS_code;
always @(posedge clk) balance_acc <= VDE ? balance_acc_new : 4'h0;
endmodule