data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #20 I1=$random;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #20 I2=$random;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #20 S1=0;S2=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #100 S1=1;S2=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #100 S1=1;S2=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #100 S1=0;S2=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:36: Unsupported: Ignoring delay on this delayed statement.\n #20 E1N=0;E2N=0;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:4: Little bit endian vector: MSB < LSB of bit range: 0:3\nreg[0:3]I1;reg[0:3]I2;\n   ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:4: Little bit endian vector: MSB < LSB of bit range: 0:3\nreg[0:3]I1;reg[0:3]I2;\n              ^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:8: Cannot find file containing module: \'HC153\'\nHC153 u1(I1,I2,S1,S2,E1N,E2N,Y1,Y2);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus,data/full_repos/permissive/165160692/HC153\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus,data/full_repos/permissive/165160692/HC153.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus,data/full_repos/permissive/165160692/HC153.sv\n             HC153\n             HC153.v\n             HC153.sv\n             obj_dir/HC153\n             obj_dir/HC153.v\n             obj_dir/HC153.sv\n%Warning-WIDTH: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                    : ... In instance testbench\n  #20 I1=$random;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/165160692/04.FPGA/5932_74HC153/stimulus/testbench153.v:20: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                    : ... In instance testbench\n  #20 I2=$random;\n        ^\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
reg[0:3]I1;reg[0:3]I2;
reg S1,S2,E1N,E2N;
wire Y1,Y2;

HC153 u1(I1,I2,S1,S2,E1N,E2N,Y1,Y2);
initial
begin
 I1=0;
 repeat(20)
  #20 I1=$random;
end

initial
begin
 I2=0;
 repeat(20)
  #20 I2=$random;
end

initial
 begin
  S1=0;S2=0;
  #20 S1=0;S2=1;
  #100 S1=1;S2=0;
  #100 S1=1;S2=1;
  #100 S1=0;S2=0;
  #100;
end

initial
begin
 E1N=1;E2N=1;
 #20 E1N=0;E2N=0;
end
endmodule
module testbench();

reg[0:3]I1;reg[0:3]I2;
reg S1,S2,E1N,E2N;
wire Y1,Y2;

HC153 u1(I1,I2,S1,S2,E1N,E2N,Y1,Y2);
initial
begin
 I1=0;
 repeat(20)
  #20 I1=$random;
end

initial
begin
 I2=0;
 repeat(20)
  #20 I2=$random;
end

initial
 begin
  S1=0;S2=0;
  #20 S1=0;S2=1;
  #100 S1=1;S2=0;
  #100 S1=1;S2=1;
  #100 S1=0;S2=0;
  #100;
end

initial
begin
 E1N=1;E2N=1;
 #20 E1N=0;E2N=0;
end
endmodule