data/full_repos/permissive/206169433/pipeline/sign_extension.v
1: b'%Warning-WIDTH: data/full_repos/permissive/206169433/pipeline/sign_extension.v:6: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                : ... In instance sign_extension\n         out <= 32\'b0+in[15:0]; \n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/206169433/pipeline/sign_extension.v:8: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                : ... In instance sign_extension\n       out<=32\'b11111111111111110000000000000000+in[15:0]; \n                                                ^\n%Error: Exiting due to 2 warning(s)\n'
module sign_extension(in, out);
    input [15:0] in;
    output reg [31:0] out;
      always @(in)begin
      if (in[15]==1'b0)
         out <= 32'b0+in[15:0]; 
       else
       out<=32'b11111111111111110000000000000000+in[15:0]; 
      end 

endmodule
module sign_extension(in, out);

    input [15:0] in;
    output reg [31:0] out;
      always @(in)begin
      if (in[15]==1'b0)
         out <= 32'b0+in[15:0]; 
       else
       out<=32'b11111111111111110000000000000000+in[15:0]; 
      end 

endmodule