data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v
1: b'%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:17: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.v\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.sv\n             rvm_constants.v\n             rvm_constants.v.v\n             rvm_constants.v.sv\n             obj_dir/rvm_constants.v\n             obj_dir/rvm_constants.v.v\n             obj_dir/rvm_constants.v.sv\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:31: Define or directive not defined: \'`RVM_BITWISE_NOP\'\nwire [31:0] i_lhs = lhs & {32{op != `RVM_BITWISE_NOP}};\n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:31: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nwire [31:0] i_lhs = lhs & {32{op != `RVM_BITWISE_NOP}};\n                                                    ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:32: Define or directive not defined: \'`RVM_BITWISE_NOP\'\nwire [31:0] i_rhs = rhs & {32{op != `RVM_BITWISE_NOP}};\n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:32: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nwire [31:0] i_rhs = rhs & {32{op != `RVM_BITWISE_NOP}};\n                                                    ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:34: Define or directive not defined: \'`RVM_BITWISE_NOP\'\nassign valid = op != `RVM_BITWISE_NOP;\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:34: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign valid = op != `RVM_BITWISE_NOP;\n                                     ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:38: Define or directive not defined: \'`RVM_BITWISE_OR\'\nassign result = ({32{op == `RVM_BITWISE_OR }} & (i_lhs | i_rhs)) |\n                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:38: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nassign result = ({32{op == `RVM_BITWISE_OR }} & (i_lhs | i_rhs)) |\n                                           ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:39: Define or directive not defined: \'`RVM_BITWISE_AND\'\n                ({32{op == `RVM_BITWISE_AND}} & (i_lhs & i_rhs)) |\n                           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_bitwise.v:40: Define or directive not defined: \'`RVM_BITWISE_XOR\'\n                ({32{op == `RVM_BITWISE_XOR}} & (i_lhs ^ i_rhs)) ;\n                           ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n'
module rvm_bitwise(
input  wire [31:0] lhs,
input  wire [31:0] rhs,

input  wire [2:0]  op,

output wire        valid,
output wire [31:0] result
);



wire [31:0] i_lhs = lhs & {32{op != `RVM_BITWISE_NOP}};
wire [31:0] i_rhs = rhs & {32{op != `RVM_BITWISE_NOP}};

assign valid = op != `RVM_BITWISE_NOP;



assign result = ({32{op == `RVM_BITWISE_OR }} & (i_lhs | i_rhs)) |
                ({32{op == `RVM_BITWISE_AND}} & (i_lhs & i_rhs)) |
                ({32{op == `RVM_BITWISE_XOR}} & (i_lhs ^ i_rhs)) ;

endmodule
module rvm_bitwise(
input  wire [31:0] lhs,
input  wire [31:0] rhs,

input  wire [2:0]  op,

output wire        valid,
output wire [31:0] result
);




wire [31:0] i_lhs = lhs & {32{op != `RVM_BITWISE_NOP}};
wire [31:0] i_rhs = rhs & {32{op != `RVM_BITWISE_NOP}};

assign valid = op != `RVM_BITWISE_NOP;



assign result = ({32{op == `RVM_BITWISE_OR }} & (i_lhs | i_rhs)) |
                ({32{op == `RVM_BITWISE_AND}} & (i_lhs & i_rhs)) |
                ({32{op == `RVM_BITWISE_XOR}} & (i_lhs ^ i_rhs)) ;

endmodule