data/full_repos/permissive/205673649/ALU/tb_alu.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/ALU/tb_alu.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #0\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/ALU/tb_alu.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #1000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/ALU/tb_alu.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/ALU/tb_alu.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/ALU/tb_alu.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/ALU/tb_alu.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/ALU/tb_alu.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/ALU/tb_alu.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/ALU/tb_alu.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/ALU/tb_alu.v:55: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/ALU/tb_alu.v:59: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Error: data/full_repos/permissive/205673649/ALU/tb_alu.v:65: Cannot find file containing module: \'ALU\'\n    ALU  \n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/ALU,data/full_repos/permissive/205673649/ALU\n             data/full_repos/permissive/205673649/ALU,data/full_repos/permissive/205673649/ALU.v\n             data/full_repos/permissive/205673649/ALU,data/full_repos/permissive/205673649/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testb_ALU();

localparam  NB_DATA_01    =  5;
localparam  NB_OPERADOR_01   =  6;

reg  signed       [NB_DATA_01-1:0]        i_data_bus_a;
reg  signed       [NB_DATA_01-1:0]        i_data_bus_b;
reg         [NB_OPERADOR_01-1:0]    i_data_operador;

wire        [NB_DATA_01-1:0]        o_data_resultado;


    initial begin
      #0
      i_data_bus_a  ={NB_DATA_01{1'b0}};
      i_data_bus_b  ={NB_DATA_01{1'b0}};
      i_data_operador  ={NB_OPERADOR_01{1'b0}};
      #1000
      $finish;
    end

    always begin
      #100
      i_data_bus_a = 5'b00010;
      i_data_bus_b = 5'b01010;
      i_data_operador = 6'b100000;
      #100
      i_data_bus_a = 5'b01010;
      i_data_bus_b = 5'b01010;
      i_data_operador = 6'b100000;
      #100
      i_data_bus_a = 5'b00110;
      i_data_bus_b = 5'b00111;
      i_data_operador = 6'b100010;
      #100
      i_data_bus_a = 5'b10101;
      i_data_bus_b = 5'b00111;
      i_data_operador = 6'b100100;
      #100
      i_data_bus_a = 5'b11001;
      i_data_bus_b = 5'b01011;
      i_data_operador = 6'b100101;
      #100
      i_data_bus_a = 5'b11111;
      i_data_bus_b = 5'b01101;
      i_data_operador = 6'b100110;
      #100
      i_data_bus_a = 5'b00110;
      i_data_bus_b = 5'b10001;
      i_data_operador =6'b100111;
      #100
      i_data_bus_a = 5'b10110;
      i_data_bus_b = 5'b11;
      i_data_operador =6'b000011;
      #100
      i_data_bus_a = 5'b11010;
      i_data_bus_b = 5'b11;
      i_data_operador =6'b000010;
    end

    ALU  
    #(
      .NB_DATA           (NB_DATA_01),
      .NB_OPERADOR          (NB_OPERADOR_01)
     )
    u_alu_01
    (
      .i_dato_a       (i_data_bus_a),
      .i_dato_b       (i_data_bus_b),
      .i_operador (i_data_operador),
      .o_resultado (o_data_resultado)
    );

endmodule
module testb_ALU();


localparam  NB_DATA_01    =  5;
localparam  NB_OPERADOR_01   =  6;

reg  signed       [NB_DATA_01-1:0]        i_data_bus_a;
reg  signed       [NB_DATA_01-1:0]        i_data_bus_b;
reg         [NB_OPERADOR_01-1:0]    i_data_operador;

wire        [NB_DATA_01-1:0]        o_data_resultado;


    initial begin
      #0
      i_data_bus_a  ={NB_DATA_01{1'b0}};
      i_data_bus_b  ={NB_DATA_01{1'b0}};
      i_data_operador  ={NB_OPERADOR_01{1'b0}};
      #1000
      $finish;
    end

    always begin
      #100
      i_data_bus_a = 5'b00010;
      i_data_bus_b = 5'b01010;
      i_data_operador = 6'b100000;
      #100
      i_data_bus_a = 5'b01010;
      i_data_bus_b = 5'b01010;
      i_data_operador = 6'b100000;
      #100
      i_data_bus_a = 5'b00110;
      i_data_bus_b = 5'b00111;
      i_data_operador = 6'b100010;
      #100
      i_data_bus_a = 5'b10101;
      i_data_bus_b = 5'b00111;
      i_data_operador = 6'b100100;
      #100
      i_data_bus_a = 5'b11001;
      i_data_bus_b = 5'b01011;
      i_data_operador = 6'b100101;
      #100
      i_data_bus_a = 5'b11111;
      i_data_bus_b = 5'b01101;
      i_data_operador = 6'b100110;
      #100
      i_data_bus_a = 5'b00110;
      i_data_bus_b = 5'b10001;
      i_data_operador =6'b100111;
      #100
      i_data_bus_a = 5'b10110;
      i_data_bus_b = 5'b11;
      i_data_operador =6'b000011;
      #100
      i_data_bus_a = 5'b11010;
      i_data_bus_b = 5'b11;
      i_data_operador =6'b000010;
    end

    ALU  
    #(
      .NB_DATA           (NB_DATA_01),
      .NB_OPERADOR          (NB_OPERADOR_01)
     )
    u_alu_01
    (
      .i_dato_a       (i_data_bus_a),
      .i_dato_b       (i_data_bus_b),
      .i_operador (i_data_operador),
      .o_resultado (o_data_resultado)
    );

endmodule