data/full_repos/permissive/143278/ivltests/pr685.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr685.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr685.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr685.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1 if ((value > 16) && (sat !== 5\'d16)) begin\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr685.v:10: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 16 bits.\n                                                                     : ... In instance main.dut\n      out = (in >= 16) ? 16 : in;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr685.v:35: Operator NEQCASE expects 16 bits on the RHS, but RHS\'s VARREF \'sat\' generates 5 bits.\n                                                                     : ... In instance main\n  if ((value <= 16) && (value !== sat)) begin\n                              ^~~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test (clk, in, out);
   input clk;
   input [15:0] in;
   output [4:0] out;

   reg [4:0] out;
   (* ivl_synthesis_on *)
   always @(posedge clk) begin

      out = (in >= 16) ? 16 : in;
   end

endmodule
module test (clk, in, out);

   input clk;
   input [15:0] in;
   output [4:0] out;

   reg [4:0] out;
   (* ivl_synthesis_on *)
   always @(posedge clk) begin

      out = (in >= 16) ? 16 : in;
   end

endmodule