data/full_repos/permissive/13953309/NW_pipereg.v
 line:48: before: "typedef"
1: b'%Error: data/full_repos/permissive/13953309/NW_pipereg.v:28: Cannot find include file: types.v\n`include "types.v"     \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13953309,data/full_repos/permissive/13953309/types.v\n             data/full_repos/permissive/13953309,data/full_repos/permissive/13953309/types.v.v\n             data/full_repos/permissive/13953309,data/full_repos/permissive/13953309/types.v.sv\n             types.v\n             types.v.v\n             types.v.sv\n             obj_dir/types.v\n             obj_dir/types.v.v\n             obj_dir/types.v.sv\n%Error: data/full_repos/permissive/13953309/NW_pipereg.v:30: syntax error, unexpected IDENTIFIER, expecting \'.\' or \';\'\n typedef flit_t reg_t;\n                ^~~~~\n%Error: data/full_repos/permissive/13953309/NW_pipereg.v:37: syntax error, unexpected IDENTIFIER, expecting \';\'\n   input reg_t data_in;\n               ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_pipereg.v:38: syntax error, unexpected IDENTIFIER, expecting \';\'\n   output reg_t data_out;\n                ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module NW_pipereg (push, pop, data_in, data_out, ready, valid, clk, rst_n);



   input push, pop, clk, rst_n;
   input reg_t data_in;
   output reg_t data_out;
   output valid, ready;

   logic  valid;
   reg_t r;
   
   always@(posedge clk) begin
      if (!rst_n) begin
	 valid<=1'b0;
      end else begin


	 assert (!(push & !ready)) else $fatal;

	 if (pop) begin

	 end
	 
	 if (push) begin
	    r <= data_in;
	    valid<=1'b1;


	    
	 end else begin
	    if (pop) begin
	       valid<=1'b0;
	    end
	 end
	 
      end
   end

   assign ready = !valid || pop ;

   assign data_out = r;
   
endmodule
module NW_pipereg (push, pop, data_in, data_out, ready, valid, clk, rst_n);




   input push, pop, clk, rst_n;
   input reg_t data_in;
   output reg_t data_out;
   output valid, ready;

   logic  valid;
   reg_t r;
   
   always@(posedge clk) begin
      if (!rst_n) begin
	 valid<=1'b0;
      end else begin


	 assert (!(push & !ready)) else $fatal;

	 if (pop) begin

	 end
	 
	 if (push) begin
	    r <= data_in;
	    valid<=1'b1;


	    
	 end else begin
	    if (pop) begin
	       valid<=1'b0;
	    end
	 end
	 
      end
   end

   assign ready = !valid || pop ;

   assign data_out = r;
   
endmodule