data/full_repos/permissive/123304708/src/common/be_ext.v
None: at end of input
1: b'%Error: data/full_repos/permissive/123304708/src/common/be_ext.v:1: Cannot find include file: ././define/instr_def.v\n`include "././define/instr_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123304708/src/common,data/full_repos/permissive/123304708/././define/instr_def.v\n             data/full_repos/permissive/123304708/src/common,data/full_repos/permissive/123304708/././define/instr_def.v.v\n             data/full_repos/permissive/123304708/src/common,data/full_repos/permissive/123304708/././define/instr_def.v.sv\n             ././define/instr_def.v\n             ././define/instr_def.v.v\n             ././define/instr_def.v.sv\n             obj_dir/././define/instr_def.v\n             obj_dir/././define/instr_def.v.v\n             obj_dir/././define/instr_def.v.sv\n%Error: data/full_repos/permissive/123304708/src/common/be_ext.v:12: Define or directive not defined: \'`OP_SW\'\n      `OP_SW: be = 4\'b1111;\n      ^~~~~~\n%Error: data/full_repos/permissive/123304708/src/common/be_ext.v:12: syntax error, unexpected \':\', expecting endcase\n      `OP_SW: be = 4\'b1111;\n            ^\n%Error: data/full_repos/permissive/123304708/src/common/be_ext.v:13: Define or directive not defined: \'`OP_SH\'\n      `OP_SH:\n      ^~~~~~\n%Error: data/full_repos/permissive/123304708/src/common/be_ext.v:20: Define or directive not defined: \'`OP_SB\'\n      `OP_SB:\n      ^~~~~~\n%Error: data/full_repos/permissive/123304708/src/common/be_ext.v:21: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      begin\n      ^~~~~\n%Error: Cannot continue\n'
module be_ext(
  input [1:0] control,
  input [5:0] OP,
  output reg[3:0] be
  );
   
  always@(*)
  begin
    case(OP)
      `OP_SW: be = 4'b1111;
      `OP_SH:
      begin
        if(control[1])
          be = 4'b1100;
        else
          be = 4'b0011;
      end
      `OP_SB:
      begin
        case(control)
          2'b00: be = 4'b0001;
          2'b01: be = 4'b0010;
          2'b10: be = 4'b0100;
          2'b11: be = 4'b1000;
        endcase
      end
    endcase
  end
  
endmodule
module be_ext(
  input [1:0] control,
  input [5:0] OP,
  output reg[3:0] be
  );

   
  always@(*)
  begin
    case(OP)
      `OP_SW: be = 4'b1111;
      `OP_SH:
      begin
        if(control[1])
          be = 4'b1100;
        else
          be = 4'b0011;
      end
      `OP_SB:
      begin
        case(control)
          2'b00: be = 4'b0001;
          2'b01: be = 4'b0010;
          2'b10: be = 4'b0100;
          2'b11: be = 4'b1000;
        endcase
      end
    endcase
  end
  
endmodule