data/full_repos/permissive/220281533/mips_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/220281533/mips_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #50 clock=~clock; #50 clock=~clock;\n                    ^\n%Error: data/full_repos/permissive/220281533/mips_testbench.v:26: Cannot find file containing module: \'mips_core\'\n mips_core test(clock);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220281533,data/full_repos/permissive/220281533/mips_core\n             data/full_repos/permissive/220281533,data/full_repos/permissive/220281533/mips_core.v\n             data/full_repos/permissive/220281533,data/full_repos/permissive/220281533/mips_core.sv\n             mips_core\n             mips_core.v\n             mips_core.sv\n             obj_dir/mips_core\n             obj_dir/mips_core.v\n             obj_dir/mips_core.sv\n%Error: Exiting due to 1 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_testbench ();

	reg clock;
	wire result;
	mips_core test(clock);

	initial clock = 0;

	initial begin 
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
	end


endmodule
module mips_testbench ();


	reg clock;
	wire result;
	mips_core test(clock);

	initial clock = 0;

	initial begin 
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
		#50 clock=~clock; #50 clock=~clock;
	end


endmodule