data/full_repos/permissive/181082280/lab_1/top.v
data/verilator_xmls/f40c0bba-7424-4cfd-8236-3f6279797abd.xml
module top
(
    input  io_72,
    input  io_73,
    output io_74
);
    assign io_74 = io_72 ^ io_73;

endmodule
module top
(
    input  io_72,
    input  io_73,
    output io_74
);

    assign io_74 = io_72 ^ io_73;

endmodule