data/full_repos/permissive/21203606/ex3/uart_tx.v
None: at end of input
1: b'%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:3: Cannot find include file: uart_params.v\n`include "uart_params.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21203606/ex3,data/full_repos/permissive/21203606/uart_params.v\n             data/full_repos/permissive/21203606/ex3,data/full_repos/permissive/21203606/uart_params.v.v\n             data/full_repos/permissive/21203606/ex3,data/full_repos/permissive/21203606/uart_params.v.sv\n             uart_params.v\n             uart_params.v.v\n             uart_params.v.sv\n             obj_dir/uart_params.v\n             obj_dir/uart_params.v.v\n             obj_dir/uart_params.v.sv\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:19: Define or directive not defined: \'`UART_FULL_ETU\'\n  wire etu_full = (etu_cnt == `UART_FULL_ETU);\n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:19: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  wire etu_full = (etu_cnt == `UART_FULL_ETU);\n                                            ^\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:39: Define or directive not defined: \'`UART_START\'\n      `UART_START:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:39: syntax error, unexpected \':\', expecting endcase\n      `UART_START:\n                 ^\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:48: Define or directive not defined: \'`UART_DATA\'\n          state <= `UART_DATA;\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:48: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n          state <= `UART_DATA;\n                             ^\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:53: Define or directive not defined: \'`UART_DATA\'\n      `UART_DATA:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:54: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      begin\n      ^~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:62: Define or directive not defined: \'`UART_STOP\'\n            state <= `UART_STOP;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            state <= `UART_STOP;\n                               ^\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:65: syntax error, unexpected end\n      end\n      ^~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:67: Define or directive not defined: \'`UART_STOP\'\n      `UART_STOP:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:72: Define or directive not defined: \'`UART_IDLE\'\n          state <= `UART_IDLE;\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:76: Define or directive not defined: \'`UART_IDLE\'\n      `UART_IDLE:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:80: Define or directive not defined: \'`UART_IDLE2\'\n          state <= `UART_IDLE2;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:84: Define or directive not defined: \'`UART_IDLE2\'\n      `UART_IDLE2:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx.v:88: Define or directive not defined: \'`UART_START\'\n          state <= `UART_START;\n                   ^~~~~~~~~~~\n%Error: Cannot continue\n'
module uart_tx(
  input wire clk,
  input wire rst,
  input wire en,
  input wire [7:0] data_out,
  output reg rdy,
  output reg dout);
  
  reg [7:0] data;
  reg [2:0] state;
  reg [2:0] cnt;
  reg [8:0] etu_cnt;
  
  wire etu_full = (etu_cnt == `UART_FULL_ETU);
  
  always @(posedge clk) begin
    
    etu_cnt <= (etu_cnt + 1);
    state <= state;
    cnt <= cnt;
    dout <= dout;
    data <= data;
    rdy <= rdy;
    
    if (rst) begin
      state <= 2'd0;
      cnt <= 3'd0;
      dout <= 1'd1;
      data <= 8'd0;
      rdy <= 1'd1;
    end
    
    case(state)
      `UART_START:
      begin
        rdy <= 1'd1;
        
        if (en) begin
          dout <= 1'd0;
          cnt <= 3'd0;
          etu_cnt <= 9'd0;
          data <= data_out;
          state <= `UART_DATA;
          rdy <= 1'd0;
        end
      end
      
      `UART_DATA:
      begin
        if (etu_full) begin
          etu_cnt <= 9'd0;
          dout <= data[0];
          cnt <= cnt + 1;
          data <= {1'b0, data[7:1]};

          if (cnt == 3'd7) begin
            state <= `UART_STOP;
          end
        end
      end
      
      `UART_STOP:
      begin
        if (etu_full) begin
          etu_cnt <= 9'd0;
          dout <= 1'd1;
          state <= `UART_IDLE;
        end
      end
      
      `UART_IDLE:
      begin
        if (etu_full) begin
          etu_cnt <= 9'd0;
          state <= `UART_IDLE2;
        end
      end
      
      `UART_IDLE2:
      begin
        if (etu_full) begin
          etu_cnt <= 9'd0;
          state <= `UART_START;
        end
      end
      
    endcase
  end
endmodule
module uart_tx(
  input wire clk,
  input wire rst,
  input wire en,
  input wire [7:0] data_out,
  output reg rdy,
  output reg dout);

  
  reg [7:0] data;
  reg [2:0] state;
  reg [2:0] cnt;
  reg [8:0] etu_cnt;
  
  wire etu_full = (etu_cnt == `UART_FULL_ETU);
  
  always @(posedge clk) begin
    
    etu_cnt <= (etu_cnt + 1);
    state <= state;
    cnt <= cnt;
    dout <= dout;
    data <= data;
    rdy <= rdy;
    
    if (rst) begin
      state <= 2'd0;
      cnt <= 3'd0;
      dout <= 1'd1;
      data <= 8'd0;
      rdy <= 1'd1;
    end
    
    case(state)
      `UART_START:
      begin
        rdy <= 1'd1;
        
        if (en) begin
          dout <= 1'd0;
          cnt <= 3'd0;
          etu_cnt <= 9'd0;
          data <= data_out;
          state <= `UART_DATA;
          rdy <= 1'd0;
        end
      end
      
      `UART_DATA:
      begin
        if (etu_full) begin
          etu_cnt <= 9'd0;
          dout <= data[0];
          cnt <= cnt + 1;
          data <= {1'b0, data[7:1]};

          if (cnt == 3'd7) begin
            state <= `UART_STOP;
          end
        end
      end
      
      `UART_STOP:
      begin
        if (etu_full) begin
          etu_cnt <= 9'd0;
          dout <= 1'd1;
          state <= `UART_IDLE;
        end
      end
      
      `UART_IDLE:
      begin
        if (etu_full) begin
          etu_cnt <= 9'd0;
          state <= `UART_IDLE2;
        end
      end
      
      `UART_IDLE2:
      begin
        if (etu_full) begin
          etu_cnt <= 9'd0;
          state <= `UART_START;
        end
      end
      
    endcase
  end
endmodule