data/full_repos/permissive/181738725/wavetrace/verilog/mask_compare.v
data/verilator_xmls/e344e2e4-dbd6-4b0e-9694-bd0ced3134a5.xml
module mask_compare #(
  parameter DataBits = 32,
  parameter SyncBits = 1)
(
  input                     clk,
  input                     rst,

  input                     din_valid,
  input [DataBits-1:0]      din_data,
  input [DataBits-1:0]      mask,
  input [DataBits-1:0]      value,
  input [SyncBits-1:0]      din_sync,

  output reg                dout_valid,
  output reg [DataBits-1:0] dout_data,
  output reg                result,
  output reg [SyncBits-1:0] dout_sync
);


  localparam CompSets = (DataBits + 31) / 32;

  reg                   mask_valid, comp_valid;
  reg [DataBits-1:0]    pipe_data[0:1];
  reg [SyncBits-1:0]    pipe_sync[0:1];
  reg [DataBits-1:0]    mask_result;
  reg [CompSets-1:0]    comp_result;


  wire [CompSets*32-1:0] mask_result_pad = mask_result;
  wire [CompSets*32-1:0] value_pad       = value;

  integer i;
  always @(posedge clk) begin


    mask_valid <= 0;
    comp_valid <= 0;
    dout_valid <= 0;


    if (din_valid) begin
      mask_valid   <= 1;
      pipe_data[0] <= din_data;
      pipe_sync[0] <= din_sync;
      mask_result  <= din_data & mask;
    end


    if (mask_valid) begin
      comp_valid <= 1;
      pipe_data[1] <= pipe_data[0];
      pipe_sync[1] <= pipe_sync[0];
      for (i=0; i < CompSets; i=i+1) begin
        comp_result[i] <= (mask_result_pad[32*i +: 32] == value_pad[32*i +: 32]);
      end
    end


    if (comp_valid) begin
      dout_valid <= 1;
      dout_data  <= pipe_data[1];
      dout_sync  <= pipe_sync[1];
      result     <= &comp_result;
    end

    if (rst) begin
      mask_valid <= 0;
      comp_valid <= 0;
      dout_valid <= 0;
    end
  end

endmodule
module mask_compare #(
  parameter DataBits = 32,
  parameter SyncBits = 1)
(
  input                     clk,
  input                     rst,

  input                     din_valid,
  input [DataBits-1:0]      din_data,
  input [DataBits-1:0]      mask,
  input [DataBits-1:0]      value,
  input [SyncBits-1:0]      din_sync,

  output reg                dout_valid,
  output reg [DataBits-1:0] dout_data,
  output reg                result,
  output reg [SyncBits-1:0] dout_sync
);



  localparam CompSets = (DataBits + 31) / 32;

  reg                   mask_valid, comp_valid;
  reg [DataBits-1:0]    pipe_data[0:1];
  reg [SyncBits-1:0]    pipe_sync[0:1];
  reg [DataBits-1:0]    mask_result;
  reg [CompSets-1:0]    comp_result;


  wire [CompSets*32-1:0] mask_result_pad = mask_result;
  wire [CompSets*32-1:0] value_pad       = value;

  integer i;
  always @(posedge clk) begin


    mask_valid <= 0;
    comp_valid <= 0;
    dout_valid <= 0;


    if (din_valid) begin
      mask_valid   <= 1;
      pipe_data[0] <= din_data;
      pipe_sync[0] <= din_sync;
      mask_result  <= din_data & mask;
    end


    if (mask_valid) begin
      comp_valid <= 1;
      pipe_data[1] <= pipe_data[0];
      pipe_sync[1] <= pipe_sync[0];
      for (i=0; i < CompSets; i=i+1) begin
        comp_result[i] <= (mask_result_pad[32*i +: 32] == value_pad[32*i +: 32]);
      end
    end


    if (comp_valid) begin
      dout_valid <= 1;
      dout_data  <= pipe_data[1];
      dout_sync  <= pipe_sync[1];
      result     <= &comp_result;
    end

    if (rst) begin
      mask_valid <= 0;
      comp_valid <= 0;
      dout_valid <= 0;
    end
  end

endmodule