data/full_repos/permissive/162400762/um.v
1: b"%Error: data/full_repos/permissive/162400762/um.v:76: Cannot find file containing module: 'usg_top'\nusg_top usg(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/usg_top\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/usg_top.v\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/usg_top.sv\n             usg_top\n             usg_top.v\n             usg_top.sv\n             obj_dir/usg_top\n             obj_dir/usg_top.v\n             obj_dir/usg_top.sv\n%Error: Exiting due to 1 error(s)\n"
module um #(
	parameter    PLATFORM = "Xilinx"
)(
	input clk,
	input [63:0] um_timestamp,
	input rst_n,
    

input  pktin_data_wr,
input  [133:0] pktin_data,
input  pktin_data_valid,
input  pktin_data_valid_wr,
output wire pktin_ready,
    
output wire pktout_data_wr,
output wire [133:0] pktout_data,
output wire pktout_data_valid,
output wire pktout_data_valid_wr,
input pktout_ready,


input [133:0] dma2um_data,
input dma2um_data_wr,
output wire um2dma_ready,

output wire [133:0] um2dma_data,
output wire um2dma_data_wr,
input dma2um_ready,


	output reg um2me_key_wr,
	output reg um2me_key_valid,
	output reg [511:0] um2match_key,
	input um2me_ready,


	input me2um_id_wr,
	input [15:0] match2um_id,
	output reg um2match_gme_alful,

	input ctrl_valid,  
	input ctrl2um_cs_n,
	output reg um2ctrl_ack_n,
	input ctrl_cmd,
	input [31:0] ctrl_datain,
	input [31:0] ctrl_addr,
	output wire [31:0] ctrl_dataout
);
 




always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin

		um2match_gme_alful <= 1'b0;
		um2me_key_wr <= 1'b0;
		um2me_key_valid <= 1'b0;
		um2match_key <= 512'b0;
		um2ctrl_ack_n <= 1'b1;
	end
	else begin
	end
end

usg_top usg(
.clk(clk),
.reset(rst_n),
.pktin_data_wr(pktin_data_wr),
.pktin_data(pktin_data),
.pktin_data_valid_wr(pktin_data_valid_wr),
.pktin_data_valid(pktin_data_valid),
.pktin_ready(pktin_ready),
.pktout_data_wr(pktout_data_wr),
.pktout_data(pktout_data),
.pktout_data_valid_wr(pktout_data_valid_wr),
.pktout_data_valid(pktout_data_valid),
.pktout_ready(pktout_ready),

.cin_data_wr(dma2um_data_wr),
.cin_data(dma2um_data),
.cin_ready(um2dma_ready),
.cout_data_wr(um2dma_data_wr),
.cout_data(um2dma_data),
.cout_ready(dma2um_ready)
);

endmodule
module um #(
	parameter    PLATFORM = "Xilinx"
)(
	input clk,
	input [63:0] um_timestamp,
	input rst_n,
    

input  pktin_data_wr,
input  [133:0] pktin_data,
input  pktin_data_valid,
input  pktin_data_valid_wr,
output wire pktin_ready,
    
output wire pktout_data_wr,
output wire [133:0] pktout_data,
output wire pktout_data_valid,
output wire pktout_data_valid_wr,
input pktout_ready,


input [133:0] dma2um_data,
input dma2um_data_wr,
output wire um2dma_ready,

output wire [133:0] um2dma_data,
output wire um2dma_data_wr,
input dma2um_ready,


	output reg um2me_key_wr,
	output reg um2me_key_valid,
	output reg [511:0] um2match_key,
	input um2me_ready,


	input me2um_id_wr,
	input [15:0] match2um_id,
	output reg um2match_gme_alful,

	input ctrl_valid,  
	input ctrl2um_cs_n,
	output reg um2ctrl_ack_n,
	input ctrl_cmd,
	input [31:0] ctrl_datain,
	input [31:0] ctrl_addr,
	output wire [31:0] ctrl_dataout
);

 




always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin

		um2match_gme_alful <= 1'b0;
		um2me_key_wr <= 1'b0;
		um2me_key_valid <= 1'b0;
		um2match_key <= 512'b0;
		um2ctrl_ack_n <= 1'b1;
	end
	else begin
	end
end

usg_top usg(
.clk(clk),
.reset(rst_n),
.pktin_data_wr(pktin_data_wr),
.pktin_data(pktin_data),
.pktin_data_valid_wr(pktin_data_valid_wr),
.pktin_data_valid(pktin_data_valid),
.pktin_ready(pktin_ready),
.pktout_data_wr(pktout_data_wr),
.pktout_data(pktout_data),
.pktout_data_valid_wr(pktout_data_valid_wr),
.pktout_data_valid(pktout_data_valid),
.pktout_ready(pktout_ready),

.cin_data_wr(dma2um_data_wr),
.cin_data(dma2um_data),
.cin_ready(um2dma_ready),
.cout_data_wr(um2dma_data_wr),
.cout_data(um2dma_data),
.cout_ready(dma2um_ready)
);

endmodule