data/full_repos/permissive/182885969/dm.v
data/verilator_xmls/8a9a1cd5-80f4-4661-abd4-c7f1df2fa7fb.xml
module dm(
		input wire			clk,
		input wire	[6:0]	addr,
		input wire			rd, wr,
		input wire 	[31:0]	wdata,
		output wire	[31:0]	rdata);

	parameter NMEM = 20;

	parameter RM_DATA = "dm_data.txt";

	reg [31:0] mem [0:127];

        initial begin
		$readmemh(RM_DATA, mem, 0, NMEM-1);
	end

	always @(posedge clk) begin
		if (wr) begin
			mem[addr] <= wdata;
		end
	end

	assign rdata = wr ? wdata : mem[addr][31:0];


endmodule
module dm(
		input wire			clk,
		input wire	[6:0]	addr,
		input wire			rd, wr,
		input wire 	[31:0]	wdata,
		output wire	[31:0]	rdata);


	parameter NMEM = 20;

	parameter RM_DATA = "dm_data.txt";

	reg [31:0] mem [0:127];

        initial begin
		$readmemh(RM_DATA, mem, 0, NMEM-1);
	end

	always @(posedge clk) begin
		if (wr) begin
			mem[addr] <= wdata;
		end
	end

	assign rdata = wr ? wdata : mem[addr][31:0];


endmodule