data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32.v
data/verilator_xmls/eb2b7558-1943-41fc-ade2-078d6385f732.xml
module fifo32 (
		read_clock_i,
		write_clock_i,
		reset_i,
		read_i,
		write_i,
		data_i,
		data_o,
		almost_full_o,
		almost_empty_o,
		not_empty_o
	);
	

	parameter	FIFO_WIDTH	= 16;
	parameter	FIFO_MSB	= FIFO_WIDTH - 1;
	
	input	read_clock_i;
	input	write_clock_i;
	input	reset_i;
	input	read_i;
	input	write_i;
	input	[FIFO_MSB:0]	data_i;
	output	[FIFO_MSB:0]	data_o;
	output	almost_full_o;
	output	almost_empty_o;
	output	not_empty_o;
	
	

	reg		[4:0]	f_start		= 5'h0;
	reg		[4:0]	f_end		= 5'h0;
	
	

	assign	almost_full_o	= (f_start - 1) == f_end;
	assign	almost_empty_o	= (f_start + 1) == f_end;
	assign	not_empty_o		= f_start != f_end;
	
	

	always @(posedge read_clock_i)
	begin
		if (reset_i)
			f_start	<= 5'b0;
		else
		begin
			if (read_i)
				f_start	<= f_start + 1;
			else
				f_start	<= f_start;
		end
	end
	
	

	always @(posedge write_clock_i)
	begin
		if (reset_i)
			f_end	<= 5'b0;
		else
		begin
			if (write_i)
				f_end	<= f_end + 1;
			else
				f_end	<= f_end;
		end
	end
	
	

	reg    [FIFO_MSB:0]  mem[0:31];
	
	always @ (posedge write_clock_i)
	begin
		if (write_i)
		begin     
			mem[f_end]  <= data_i;  
		end
	end
	
	assign data_o = mem[f_start];
	
	
endmodule
module fifo32 (
		read_clock_i,
		write_clock_i,
		reset_i,
		read_i,
		write_i,
		data_i,
		data_o,
		almost_full_o,
		almost_empty_o,
		not_empty_o
	);

	

	parameter	FIFO_WIDTH	= 16;
	parameter	FIFO_MSB	= FIFO_WIDTH - 1;
	
	input	read_clock_i;
	input	write_clock_i;
	input	reset_i;
	input	read_i;
	input	write_i;
	input	[FIFO_MSB:0]	data_i;
	output	[FIFO_MSB:0]	data_o;
	output	almost_full_o;
	output	almost_empty_o;
	output	not_empty_o;
	
	

	reg		[4:0]	f_start		= 5'h0;
	reg		[4:0]	f_end		= 5'h0;
	
	

	assign	almost_full_o	= (f_start - 1) == f_end;
	assign	almost_empty_o	= (f_start + 1) == f_end;
	assign	not_empty_o		= f_start != f_end;
	
	

	always @(posedge read_clock_i)
	begin
		if (reset_i)
			f_start	<= 5'b0;
		else
		begin
			if (read_i)
				f_start	<= f_start + 1;
			else
				f_start	<= f_start;
		end
	end
	
	

	always @(posedge write_clock_i)
	begin
		if (reset_i)
			f_end	<= 5'b0;
		else
		begin
			if (write_i)
				f_end	<= f_end + 1;
			else
				f_end	<= f_end;
		end
	end
	
	

	reg    [FIFO_MSB:0]  mem[0:31];
	
	always @ (posedge write_clock_i)
	begin
		if (write_i)
		begin     
			mem[f_end]  <= data_i;  
		end
	end
	
	assign data_o = mem[f_start];
	
	
endmodule