data/full_repos/permissive/100975158/MIPS32_Full/Processor/Instruction_Fetch_Decode_Pipeline.v
data/verilator_xmls/b88874b2-98d9-425a-b474-15245d215f9a.xml
module Instruction_Fetch_Decode_Pipeline (
    input           clock,
    input           reset,
    input           if_flush,
    input           if_stall,
    input           id_stall,
    input           if_bra_delay,
    input [31:0]    if_instruction,
    input [31:0]    if_pc_add_4,
    input [31:0]    if_pc_usable,


    output reg [31:0]   id_instruction,
    output reg [31:0]   id_pc_add_4,
    output reg [31:0]   id_pc
);

    always @ (posedge clock) begin

        id_instruction <= (reset) ? 32'b0 : ( (id_stall) ? id_instruction : ( (if_stall | if_flush | if_bra_delay) ? 32'b0 : if_instruction ) );

        id_pc_add_4    <= (reset) ? 32'b0 : ( (id_stall) ? id_pc_add_4 : if_pc_add_4);


        id_pc          <= (reset) ? 32'b0 : ( (id_stall | if_bra_delay) ? id_pc : if_pc_usable);
    end

endmodule
module Instruction_Fetch_Decode_Pipeline (
    input           clock,
    input           reset,
    input           if_flush,
    input           if_stall,
    input           id_stall,
    input           if_bra_delay,
    input [31:0]    if_instruction,
    input [31:0]    if_pc_add_4,
    input [31:0]    if_pc_usable,


    output reg [31:0]   id_instruction,
    output reg [31:0]   id_pc_add_4,
    output reg [31:0]   id_pc
);


    always @ (posedge clock) begin

        id_instruction <= (reset) ? 32'b0 : ( (id_stall) ? id_instruction : ( (if_stall | if_flush | if_bra_delay) ? 32'b0 : if_instruction ) );

        id_pc_add_4    <= (reset) ? 32'b0 : ( (id_stall) ? id_pc_add_4 : if_pc_add_4);


        id_pc          <= (reset) ? 32'b0 : ( (id_stall | if_bra_delay) ? id_pc : if_pc_usable);
    end

endmodule