data/full_repos/permissive/161033574/spi.v
1: b"%Error: data/full_repos/permissive/161033574/spi.v:13: Duplicate declaration of signal: 'rxbuf'\n                                                     : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n   reg [7:0]                  rxbuf;\n                              ^~~~~\n        data/full_repos/permissive/161033574/spi.v:7: ... Location of original declaration\n                 output [7:0] rxbuf,\n                              ^~~~~\n%Error: data/full_repos/permissive/161033574/spi.v:14: Duplicate declaration of signal: 'dr'\n   reg                        dr;\n                              ^~\n        data/full_repos/permissive/161033574/spi.v:10: ... Location of original declaration\n                 output       dr\n                              ^~\n%Error: data/full_repos/permissive/161033574/spi.v:15: Duplicate declaration of signal: 'miso'\n   reg                        miso;\n                              ^~~~\n        data/full_repos/permissive/161033574/spi.v:6: ... Location of original declaration\n                 output       miso,\n                              ^~~~\n%Error: Exiting due to 3 error(s)\n"
module spi_slave(
                 input        rst_n,
                 input        cs_n,
                 input        sclk,
                 input        mosi,
                 output       miso,
                 output [7:0] rxbuf,
                 input        txset,
                 input [7:0]  tx,
                 output       dr
                 );

   reg [7:0]                  rxbuf;
   reg                        dr;
   reg                        miso;

   reg [7:0]                  txbuf;
   reg [2:0]                  count;

   wire                       rst = rst_n && (!cs_n);

   always @ (posedge sclk, negedge rst)
     begin
        if (!rst)
          begin
             count <= 0;
             dr <= 0;
             rxbuf <= 0;
            end
        else
          begin
             count <= count + 1;
             dr <= count == 3'd7;
             rxbuf <= {rxbuf[6:0], mosi};
          end

     end

   always @ (negedge txset)
     begin
        txbuf <= tx;
     end
endmodule
module spi_slave(
                 input        rst_n,
                 input        cs_n,
                 input        sclk,
                 input        mosi,
                 output       miso,
                 output [7:0] rxbuf,
                 input        txset,
                 input [7:0]  tx,
                 output       dr
                 );


   reg [7:0]                  rxbuf;
   reg                        dr;
   reg                        miso;

   reg [7:0]                  txbuf;
   reg [2:0]                  count;

   wire                       rst = rst_n && (!cs_n);

   always @ (posedge sclk, negedge rst)
     begin
        if (!rst)
          begin
             count <= 0;
             dr <= 0;
             rxbuf <= 0;
            end
        else
          begin
             count <= count + 1;
             dr <= count == 3'd7;
             rxbuf <= {rxbuf[6:0], mosi};
          end

     end

   always @ (negedge txset)
     begin
        txbuf <= tx;
     end
endmodule