data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/gowin/cells_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/gowin/cells_map.v:2: Multiple top level modules\n                                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                           : ... Top module \'$_DFF_N_\'\nmodule  \\$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule\n        ^~~~~~~~~\n                                                                                                           : ... Top module \'$_DFF_P_\'\nmodule  \\$_DFF_P_ #(parameter INIT = 1\'b0) (input D, C, output Q); DFF  #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule\n        ^~~~~~~~~\n                                                                                                           : ... Top module \'$__DFFS_PN0_\'\nmodule  \\$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                           : ... Top module \'$__DFFS_PP0_\'\nmodule  \\$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                           : ... Top module \'$__DFFS_PP1_\'\nmodule  \\$__DFFS_PP1_ (input D, C, R, output Q); DFFR  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                           : ... Top module \'$lut\'\nmodule \\$lut (A, Y);\n       ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/gowin/cells_map.v:12: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input [WIDTH-1:0] A;\n        ^\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/gowin/cells_map.v:6: Cannot find file containing module: \'DFFR\'\nmodule  \\$__DFFS_PP1_ (input D, C, R, output Q); DFFR  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule\n                                                 ^~~~\n        ... Looked in:\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/gowin,data/full_repos/permissive/200142067/DFFR\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/gowin,data/full_repos/permissive/200142067/DFFR.v\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/gowin,data/full_repos/permissive/200142067/DFFR.sv\n             DFFR\n             DFFR.v\n             DFFR.sv\n             obj_dir/DFFR\n             obj_dir/DFFR.v\n             obj_dir/DFFR.sv\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/gowin/cells_map.v:5: Cannot find file containing module: \'DFFR\'\nmodule  \\$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule\n                                                 ^~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/gowin/cells_map.v:4: Cannot find file containing module: \'DFFR\'\nmodule  \\$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule\n                                                 ^~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/gowin/cells_map.v:2: Cannot find file containing module: \'DFF\'\nmodule  \\$_DFF_P_ #(parameter INIT = 1\'b0) (input D, C, output Q); DFF  #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule\n                                                                   ^~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/gowin/cells_map.v:1: Cannot find file containing module: \'DFFN\'\nmodule  \\$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule\n                                          ^~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module  \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
module  \$_DFF_N_ (input D, C, output Q);
 DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule