data/full_repos/permissive/168228981/klok.v
data/verilator_xmls/325621f6-724e-446b-8138-43b1cbdfca3c.xml
module klok(reset, clock,klok);
output klok;
input reset;
input clock;
reg [30:0] counter;
reg klok;
always @(posedge clock)
if (reset) begin
counter = 0;
klok = 0;
end else begin
if (counter == 24999999) begin
klok = !klok; 
counter = 0;
end else
counter = counter + 1;
end
endmodule
module klok(reset, clock,klok);

output klok;
input reset;
input clock;
reg [30:0] counter;
reg klok;
always @(posedge clock)
if (reset) begin
counter = 0;
klok = 0;
end else begin
if (counter == 24999999) begin
klok = !klok; 
counter = 0;
end else
counter = counter + 1;
end
endmodule