data/full_repos/permissive/185398148/1.logarithm/tb_logarithm.sv
 line:10 column:10: Illegal character "'"
1: b'%Warning-STMTDLY: data/full_repos/permissive/185398148/1.logarithm/tb_logarithm.sv:11: Unsupported: Ignoring delay on this delayed statement.\n  forever #(0.5) clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/185398148/1.logarithm/tb_logarithm.sv:19: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/185398148/1.logarithm/tb_logarithm.sv:21: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/185398148/1.logarithm/tb_logarithm.sv:23: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/185398148/1.logarithm/tb_logarithm.sv:25: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/185398148/1.logarithm/tb_logarithm.sv:27: Unsupported: Ignoring delay on this delayed statement.\n  #500\n  ^\n%Error: data/full_repos/permissive/185398148/1.logarithm/tb_logarithm.sv:60: syntax error, unexpected \'@\'\n  repeat(1200)@(posedge clk);\n              ^\n%Error: data/full_repos/permissive/185398148/1.logarithm/tb_logarithm.sv:66: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("logarithm.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/185398148/1.logarithm/tb_logarithm.sv:67: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, tb_logarithm);\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_logarithm ();

	logic clk;


	initial begin
		clk = '0;
		forever #(0.5) clk = ~clk;
	end


	initial begin
		x = 9'b110110001;
		start = 1'd1;
		reset = 1'd0;
		#100
		reset = 1'd1;
		#100
		start = 1'd0;
		#100
		start = 1'd1;
		#100
		start = 1'd0;
		#500
		start = 1'd1;
	end



	parameter n = 8;
	parameter m = 16;
	parameter k = 5;
	parameter p = 16;

	logic       reset;
	logic       start;
	logic [0:n] x;
	logic [1:p] y;
	logic       done;

	logarithm #(
			.n(n),
			.m(m),
			.k(k),
			.p(p)
		) inst_logarithm (
			.clk   (clk),
			.reset (reset),
			.start (start),
			.x     (x),
			.y     (y),
			.done  (done)
		);

	initial begin

		repeat(1200)@(posedge clk);
		$finish;
	end


	initial begin
		$dumpfile("logarithm.vcd");
		$dumpvars(0, tb_logarithm);
	end

endmodule
module tb_logarithm ();


	logic clk;


	initial begin
		clk = '0;
		forever #(0.5) clk = ~clk;
	end


	initial begin
		x = 9'b110110001;
		start = 1'd1;
		reset = 1'd0;
		#100
		reset = 1'd1;
		#100
		start = 1'd0;
		#100
		start = 1'd1;
		#100
		start = 1'd0;
		#500
		start = 1'd1;
	end



	parameter n = 8;
	parameter m = 16;
	parameter k = 5;
	parameter p = 16;

	logic       reset;
	logic       start;
	logic [0:n] x;
	logic [1:p] y;
	logic       done;

	logarithm #(
			.n(n),
			.m(m),
			.k(k),
			.p(p)
		) inst_logarithm (
			.clk   (clk),
			.reset (reset),
			.start (start),
			.x     (x),
			.y     (y),
			.done  (done)
		);

	initial begin

		repeat(1200)@(posedge clk);
		$finish;
	end


	initial begin
		$dumpfile("logarithm.vcd");
		$dumpvars(0, tb_logarithm);
	end

endmodule