data/full_repos/permissive/159902111/MCPU_experiment/A.v
data/verilator_xmls/39e1dedb-7219-4e31-a5be-360eea08c085.xml
module A(
  input clk,
  input rst_n,
  input [31:0] Rdata1_i,
  
  output [31:0] data1_o
  );
  reg [31:0] A;
  always@(posedge clk or posedge rst_n)
  begin
    if (rst_n)
      A <= 32'h0;
    else
      A <= Rdata1_i;
  end
  assign data1_o = A;
endmodule
module A(
  input clk,
  input rst_n,
  input [31:0] Rdata1_i,
  
  output [31:0] data1_o
  );

  reg [31:0] A;
  always@(posedge clk or posedge rst_n)
  begin
    if (rst_n)
      A <= 32'h0;
    else
      A <= Rdata1_i;
  end
  assign data1_o = A;
endmodule