data/full_repos/permissive/156417892/hdl/Execute/AdderBranch/AdderBranch.v
data/verilator_xmls/bf388b27-44a2-4346-8352-5f4e115c2a80.xml
module AdderBranch(clk,
                    pc,
                   imm32,
                   pcAddResult);
   input clk;
   input [31:0] pc, imm32;
   output reg [31:0] pcAddResult;
   
   always @(posedge clk) begin
      pcAddResult = pc + imm32;
   end
   
endmodule
module AdderBranch(clk,
                    pc,
                   imm32,
                   pcAddResult);

   input clk;
   input [31:0] pc, imm32;
   output reg [31:0] pcAddResult;
   
   always @(posedge clk) begin
      pcAddResult = pc + imm32;
   end
   
endmodule