data/full_repos/permissive/218779832/test/dpregtb.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/218779832/test/dpregtb.v:24: Unsupported: Ignoring delay on this delayed statement.\n# 5\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/218779832/test/dpregtb.v:26: Unsupported: Ignoring delay on this delayed statement.\n# 5\n^\n%Error: data/full_repos/permissive/218779832/test/dpregtb.v:31: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("dpregtb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/218779832/test/dpregtb.v:32: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(1,dpregtb);\n^~~~~~~~~\n%Error: data/full_repos/permissive/218779832/test/dpregtb.v:33: Unsupported or unknown PLI call: $monitor\n$monitor("data ->%d,read_addr-> %d,write_addr-> %d,we-> %d,q -> %d" ,data,read_addr,write_addr,we,q);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/218779832/test/dpregtb.v:35: Unsupported: Ignoring delay on this delayed statement.\n#period\n^\n%Warning-STMTDLY: data/full_repos/permissive/218779832/test/dpregtb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#period\n^\n%Warning-STMTDLY: data/full_repos/permissive/218779832/test/dpregtb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#period\n^\n%Warning-STMTDLY: data/full_repos/permissive/218779832/test/dpregtb.v:48: Unsupported: Ignoring delay on this delayed statement.\n#period\n^\n%Warning-STMTDLY: data/full_repos/permissive/218779832/test/dpregtb.v:53: Unsupported: Ignoring delay on this delayed statement.\n#period\n^\n%Warning-STMTDLY: data/full_repos/permissive/218779832/test/dpregtb.v:56: Unsupported: Ignoring delay on this delayed statement.\n#period\n^\n%Warning-STMTDLY: data/full_repos/permissive/218779832/test/dpregtb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#period\n^\n%Error: Exiting due to 3 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dpregtb ;
  reg      [7:0] data;
  reg      [2:0] read_addr;
  reg     [2:0] write_addr;
  reg           we;
  reg clk;
  wire reg [7:0] q;

  dpreg dp1
  (
   .data (data),
   .read_addr (read_addr),
   .write_addr (write_addr),
   .we (we),
   .clk (clk),
   .q  (q)
  );

localparam period = 10;

always begin 
# 5
clk = 1'b1;
# 5
clk = 1'b0;
end

initial begin
$dumpfile("dpregtb.vcd");
$dumpvars(1,dpregtb);
$monitor("data ->%d,read_addr-> %d,write_addr-> %d,we-> %d,q -> %d" ,data,read_addr,write_addr,we,q);

#period
data <= 8'haa;
we <= 1'b1;
write_addr <= 3'b001;

#period
read_addr <= 3'b001;

#period
data <= 8'hfe;
we <= 1'b1;
write_addr <= 3'b011;

#period
data <= 8'h0f;
we <= 1'b1;
write_addr <= 3'b101;

#period
read_addr <= 3'b001;

#period
data <= 8'h0e;
we <= 1'b1;
write_addr <= 3'b011;
read_addr <= 3'b011;

#period
data <= 8'h03;
we <= 1'b1;
write_addr <= 3'b101;
read_addr <=  3'b101;

end
endmodule
module dpregtb ;

  reg      [7:0] data;
  reg      [2:0] read_addr;
  reg     [2:0] write_addr;
  reg           we;
  reg clk;
  wire reg [7:0] q;

  dpreg dp1
  (
   .data (data),
   .read_addr (read_addr),
   .write_addr (write_addr),
   .we (we),
   .clk (clk),
   .q  (q)
  );

localparam period = 10;

always begin 
# 5
clk = 1'b1;
# 5
clk = 1'b0;
end

initial begin
$dumpfile("dpregtb.vcd");
$dumpvars(1,dpregtb);
$monitor("data ->%d,read_addr-> %d,write_addr-> %d,we-> %d,q -> %d" ,data,read_addr,write_addr,we,q);

#period
data <= 8'haa;
we <= 1'b1;
write_addr <= 3'b001;

#period
read_addr <= 3'b001;

#period
data <= 8'hfe;
we <= 1'b1;
write_addr <= 3'b011;

#period
data <= 8'h0f;
we <= 1'b1;
write_addr <= 3'b101;

#period
read_addr <= 3'b001;

#period
data <= 8'h0e;
we <= 1'b1;
write_addr <= 3'b011;
read_addr <= 3'b011;

#period
data <= 8'h03;
we <= 1'b1;
write_addr <= 3'b101;
read_addr <=  3'b101;

end
endmodule