data/full_repos/permissive/172912857/project_bin_bcd_7dig/bin_bcd_7dig.v
 line:194: before: "("
data/verilator_xmls/b300b048-3dde-488a-a93e-90374b50244d.xml
module top(

    input [12:0] number,
    input reset,
    input clk,
    output [3:0] anode,
    output [6:0] seg
    );
    
wire [3:0] A, B, C, D;

bcd bcd(
        .number(number),
        .thousands(D), 
        .hundreds(C), 
        .tens(B), 
        .ones(A)
        );


bcdto7segmentclocked bcdto7segmentclocked(
    .A(A), 
    .B(B), 
    .C(C), 
    .D(D),
    .reset(reset),
    .clk(clk),
    .anode(anode),
    .seg(seg) 
    );
    
    
endmodule
module top(

    input [12:0] number,
    input reset,
    input clk,
    output [3:0] anode,
    output [6:0] seg
    );

    
wire [3:0] A, B, C, D;

bcd bcd(
        .number(number),
        .thousands(D), 
        .hundreds(C), 
        .tens(B), 
        .ones(A)
        );


bcdto7segmentclocked bcdto7segmentclocked(
    .A(A), 
    .B(B), 
    .C(C), 
    .D(D),
    .reset(reset),
    .clk(clk),
    .anode(anode),
    .seg(seg) 
    );
    
    
endmodule