data/full_repos/permissive/162533945/alu.v
1: b"%Error: data/full_repos/permissive/162533945/alu.v:24: Cannot find file containing module: 'adder'\n adder adder0(.x(data_operandA), .y(data_operandB), .sub(ctrl_ALUopcode[0]), .out(out0));\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/adder\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/adder.v\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/adder.sv\n             adder\n             adder.v\n             adder.sv\n             obj_dir/adder\n             obj_dir/adder.v\n             obj_dir/adder.sv\n%Error: data/full_repos/permissive/162533945/alu.v:34: Cannot find file containing module: 'adder'\n adder suber1(.x(data_operandA), .y(nB), .sub(ctrl_ALUopcode[0]), .out(out1));\n ^~~~~\n%Error: data/full_repos/permissive/162533945/alu.v:53: Cannot find file containing module: 'mux_2to1_1bit'\n mux_2to1_1bit mux_carry(ov_add, ov_sub, ctrl_ALUopcode[0], overflow);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162533945/alu.v:69: Cannot find file containing module: 'sll'\n sll sll4(.in(data_operandA), .amt(ctrl_shiftamt), .out(out4));\n ^~~\n%Error: data/full_repos/permissive/162533945/alu.v:71: Cannot find file containing module: 'sra'\n sra sra5(.in(data_operandA), .amt(ctrl_shiftamt), .out(out5));\n ^~~\n%Error: Exiting due to 5 error(s)\n"
module mux_8to1_1bit(i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2, out);
	
	input i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2;
	output out;
	

	
	wire ns0, ns1, ns2;
	not not0(ns0, s0);
	not not1(ns1, s1);
	not not2(ns2, s2);
	
	wire t0, t1, t2, t3, t4, t5, t6, t7;
	and and0(t0, i0, ns0, ns1, ns2);
	and and1(t1, i1, s0, ns1, ns2);
	and and2(t2, i2, ns0, s1, ns2);
	and and3(t3, i3, s0, s1, ns2);
	and and4(t4, i4, ns0, ns1, s2);
	and and5(t5, i5, s0, ns1, s2);
	and and6(t6, i6, ns0, s1, s2);
	and and7(t7, i7, s0, s1, s2);
	
	or or0(out, t0, t1, t2, t3, t4, t5, t6, t7);
	
endmodule
module mux_8to1_1bit(i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2, out);

	
	input i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2;
	output out;
	

	
	wire ns0, ns1, ns2;
	not not0(ns0, s0);
	not not1(ns1, s1);
	not not2(ns2, s2);
	
	wire t0, t1, t2, t3, t4, t5, t6, t7;
	and and0(t0, i0, ns0, ns1, ns2);
	and and1(t1, i1, s0, ns1, ns2);
	and and2(t2, i2, ns0, s1, ns2);
	and and3(t3, i3, s0, s1, ns2);
	and and4(t4, i4, ns0, ns1, s2);
	and and5(t5, i5, s0, ns1, s2);
	and and6(t6, i6, ns0, s1, s2);
	and and7(t7, i7, s0, s1, s2);
	
	or or0(out, t0, t1, t2, t3, t4, t5, t6, t7);
	
endmodule