data/full_repos/permissive/165663914/firmware/Hermes_Lite_SDK.v
1: b"%Error: data/full_repos/permissive/165663914/firmware/Hermes_Lite_SDK.v:87: Cannot find file containing module: 'PLL_IF'\nPLL_IF PLL_IF_inst(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165663914/firmware,data/full_repos/permissive/165663914/PLL_IF\n             data/full_repos/permissive/165663914/firmware,data/full_repos/permissive/165663914/PLL_IF.v\n             data/full_repos/permissive/165663914/firmware,data/full_repos/permissive/165663914/PLL_IF.sv\n             PLL_IF\n             PLL_IF.v\n             PLL_IF.sv\n             obj_dir/PLL_IF\n             obj_dir/PLL_IF.v\n             obj_dir/PLL_IF.sv\n%Error: data/full_repos/permissive/165663914/firmware/Hermes_Lite_SDK.v:93: Cannot find file containing module: 'PLL_AUDIO'\nPLL_AUDIO PLL_AUDIO_inst(\n^~~~~~~~~\n%Error: data/full_repos/permissive/165663914/firmware/Hermes_Lite_SDK.v:110: Cannot find file containing module: 'RMII2MII_rev2'\nRMII2MII_rev2 RMII2MII_inst(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/165663914/firmware/Hermes_Lite_SDK.v:134: Cannot find file containing module: 'hermes_lite_core'\nhermes_lite_core #(\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module Hermes_Lite(

    input [1:0] dipsw,
    input ptt_i,
    output exp_ptt_n,
    input [13:0] ADC_in,
    output [13:0] DAC_out,
    input ADC_ready,
    input ADC_OVR,
    input ADC_DRY,
    output DAC_CLK,
    output preamp,
    output audio_l,
    output audio_r,
    output [6:0] userout,
    output [3:0] LEDS,


    output AC_BCLK,
    output AC_DALRC,
    output AC_ADCLRC,
    output AC_MCLK,
    inout AC_IIC_DAT,
    output AC_IIC_SCK,
    output AC_DACDAT,
    input  AC_ADCDAT,


    output [1:0] rmii_tx,
    output rmii_tx_en,
    input [1:0] rmii_rx,
    input rmii_osc,
    input rmii_crs_dv,
    inout PHY_MDIO,
    output PHY_MDC
);




parameter MAC = {8'h00,8'h1c,8'hc0,8'ha2,8'h22,8'h5d};
parameter IP = {8'd0,8'd0,8'd0,8'd0};



parameter CLK_FREQ = 96000000;


parameter NR = 1;

wire IF_locked;
wire AC_locked;

wire pll_96000;
wire pll_48;
wire pll_12288;
wire pll_3072;
wire pll_800;

assign DAC_CLK = pll_96000;
assign AC_DALRC = pll_48;
assign AC_ADCLRC = pll_48;
assign AC_BCLK = pll_3072;
assign AC_MCLK = pll_12288;

PLL_IF PLL_IF_inst(
    .inclk0(ADC_ready),
    .c0(pll_96000), 
    .c1(pll_48),
    .locked(IF_locked));

PLL_AUDIO PLL_AUDIO_inst(
    .inclk0(pll_96000),
    .c0(pll_12288),
    .c1(pll_3072), 
    .c2(pll_800),
    .locked(AC_locked));



wire [3:0] PHY_TX;
wire PHY_TX_EN;
reg PHY_TX_CLOCK;
wire [3:0] PHY_RX;
wire RX_DV;
reg PHY_RX_CLOCK;
wire PHY_RESET_N;

RMII2MII_rev2 RMII2MII_inst(
    .clk(rmii_osc),
    .resetn(1'b1),
    .phy_RXD(rmii_rx),
    .phy_CRS(rmii_crs_dv),
    .mac_RXD(PHY_RX),
    .mac_RX_CLK(PHY_RX_CLOCK),
    .mac_RX_DV(RX_DV),
    .mac_TXD(PHY_TX),
    .mac_TX_EN(PHY_TX_EN),
    .phy_TXD(rmii_tx),
    .phy_TX_EN(rmii_tx_en),
    .mac_TX_CLK(PHY_TX_CLOCK),
    .mac_MDC_in(),
    .phy_MDC_out(),
    .mac_MDO_oen(),
    .mac_MDO_in(),
    .phy_MDIO(),
    .mac_MDI_out(),
    .phy_resetn()
);



hermes_lite_core #(
    .MAC(MAC),
    .IP(IP),
    .CLK_FREQ(CLK_FREQ),
    .NR(NR)) 

    hermes_lite_core_inst(

        .ADC_CLK(pll_96000),

        .IF_locked(1'b1),
        .IF_CLRCLK(pll_48),
        .leds(LEDS),
        .preamp (preamp),
        .audio_l (audio_l),
        .audio_r (audio_r),
        .exp_ptt_n(exp_ptt_n),
        .pll_3072(pll_3072),
        .pll_12288(pll_12288),
        .pll_800(pll_800),
        .userout(userout),
        .dipsw({dipsw[1],dipsw}),


        .ptt_i(ptt_i),


        .DAC_out(DAC_out),
        .ADC_in(ADC_in),
        .ADC_ready(ADC_ready),
        .ADC_ovr(ADC_OVR),
   
        .AC_IIC_DAT(AC_IIC_DAT),
        .AC_IIC_SCK(AC_IIC_SCK),
        .AC_ADCDAT(AC_ADCDAT),
        .AC_DACDAT(AC_DACDAT),



        .PHY_TX(PHY_TX),
        .PHY_TX_EN(PHY_TX_EN),        
        .PHY_TX_CLOCK(PHY_TX_CLOCK),
        .PHY_RX(PHY_RX),     
        .RX_DV(RX_DV),
        .PHY_RX_CLOCK(PHY_RX_CLOCK),         
        .PHY_RESET_N(PHY_RESET_N),
        .PHY_MDIO(PHY_MDIO),             
        .PHY_MDC(PHY_MDC)
);             

endmodule
module Hermes_Lite(

    input [1:0] dipsw,
    input ptt_i,
    output exp_ptt_n,
    input [13:0] ADC_in,
    output [13:0] DAC_out,
    input ADC_ready,
    input ADC_OVR,
    input ADC_DRY,
    output DAC_CLK,
    output preamp,
    output audio_l,
    output audio_r,
    output [6:0] userout,
    output [3:0] LEDS,


    output AC_BCLK,
    output AC_DALRC,
    output AC_ADCLRC,
    output AC_MCLK,
    inout AC_IIC_DAT,
    output AC_IIC_SCK,
    output AC_DACDAT,
    input  AC_ADCDAT,


    output [1:0] rmii_tx,
    output rmii_tx_en,
    input [1:0] rmii_rx,
    input rmii_osc,
    input rmii_crs_dv,
    inout PHY_MDIO,
    output PHY_MDC
);





parameter MAC = {8'h00,8'h1c,8'hc0,8'ha2,8'h22,8'h5d};
parameter IP = {8'd0,8'd0,8'd0,8'd0};



parameter CLK_FREQ = 96000000;


parameter NR = 1;

wire IF_locked;
wire AC_locked;

wire pll_96000;
wire pll_48;
wire pll_12288;
wire pll_3072;
wire pll_800;

assign DAC_CLK = pll_96000;
assign AC_DALRC = pll_48;
assign AC_ADCLRC = pll_48;
assign AC_BCLK = pll_3072;
assign AC_MCLK = pll_12288;

PLL_IF PLL_IF_inst(
    .inclk0(ADC_ready),
    .c0(pll_96000), 
    .c1(pll_48),
    .locked(IF_locked));

PLL_AUDIO PLL_AUDIO_inst(
    .inclk0(pll_96000),
    .c0(pll_12288),
    .c1(pll_3072), 
    .c2(pll_800),
    .locked(AC_locked));



wire [3:0] PHY_TX;
wire PHY_TX_EN;
reg PHY_TX_CLOCK;
wire [3:0] PHY_RX;
wire RX_DV;
reg PHY_RX_CLOCK;
wire PHY_RESET_N;

RMII2MII_rev2 RMII2MII_inst(
    .clk(rmii_osc),
    .resetn(1'b1),
    .phy_RXD(rmii_rx),
    .phy_CRS(rmii_crs_dv),
    .mac_RXD(PHY_RX),
    .mac_RX_CLK(PHY_RX_CLOCK),
    .mac_RX_DV(RX_DV),
    .mac_TXD(PHY_TX),
    .mac_TX_EN(PHY_TX_EN),
    .phy_TXD(rmii_tx),
    .phy_TX_EN(rmii_tx_en),
    .mac_TX_CLK(PHY_TX_CLOCK),
    .mac_MDC_in(),
    .phy_MDC_out(),
    .mac_MDO_oen(),
    .mac_MDO_in(),
    .phy_MDIO(),
    .mac_MDI_out(),
    .phy_resetn()
);



hermes_lite_core #(
    .MAC(MAC),
    .IP(IP),
    .CLK_FREQ(CLK_FREQ),
    .NR(NR)) 

    hermes_lite_core_inst(

        .ADC_CLK(pll_96000),

        .IF_locked(1'b1),
        .IF_CLRCLK(pll_48),
        .leds(LEDS),
        .preamp (preamp),
        .audio_l (audio_l),
        .audio_r (audio_r),
        .exp_ptt_n(exp_ptt_n),
        .pll_3072(pll_3072),
        .pll_12288(pll_12288),
        .pll_800(pll_800),
        .userout(userout),
        .dipsw({dipsw[1],dipsw}),


        .ptt_i(ptt_i),


        .DAC_out(DAC_out),
        .ADC_in(ADC_in),
        .ADC_ready(ADC_ready),
        .ADC_ovr(ADC_OVR),
   
        .AC_IIC_DAT(AC_IIC_DAT),
        .AC_IIC_SCK(AC_IIC_SCK),
        .AC_ADCDAT(AC_ADCDAT),
        .AC_DACDAT(AC_DACDAT),



        .PHY_TX(PHY_TX),
        .PHY_TX_EN(PHY_TX_EN),        
        .PHY_TX_CLOCK(PHY_TX_CLOCK),
        .PHY_RX(PHY_RX),     
        .RX_DV(RX_DV),
        .PHY_RX_CLOCK(PHY_RX_CLOCK),         
        .PHY_RESET_N(PHY_RESET_N),
        .PHY_MDIO(PHY_MDIO),             
        .PHY_MDC(PHY_MDC)
);             

endmodule