data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg3.v
 line:37: before: ";"
1: b'%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg3.v:25: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                              : ... In instance muxer_reg3\n      out      <=  3\'b0; \n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg3.v:36: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                              : ... In instance muxer_reg3\n         default :  out  <= 3\'b0 ; \n                         ^~\n%Error: Exiting due to 2 warning(s)\n'
module muxer_reg3 #(
   parameter     RES = 14 
)
(

   input                 clk,rst,
   input      [  3-1: 0] sel,
   input      [RES-1: 0] in0,
   input      [RES-1: 0] in1,
   input      [RES-1: 0] in2,
   input      [RES-1: 0] in3,
   input      [RES-1: 0] in4,
   input      [RES-1: 0] in5,
   input      [RES-1: 0] in6,
   input      [RES-1: 0] in7,


   output reg [RES-1: 0] out
);



always @(posedge clk)
   if (rst)
      out      <=  3'b0; 
   else
      case (sel)
         3'd00   :  out  <= in0  ;
         3'd01   :  out  <= in1  ;
         3'd02   :  out  <= in2  ;
         3'd03   :  out  <= in3  ;
         3'd04   :  out  <= in4  ;
         3'd05   :  out  <= in5  ;
         3'd06   :  out  <= in6  ;
         3'd07   :  out  <= in7  ;
         default :  out  <= 3'b0 ; 
      endcase ;
   
 


endmodule
module muxer_reg3 #(
   parameter     RES = 14 
)
(

   input                 clk,rst,
   input      [  3-1: 0] sel,
   input      [RES-1: 0] in0,
   input      [RES-1: 0] in1,
   input      [RES-1: 0] in2,
   input      [RES-1: 0] in3,
   input      [RES-1: 0] in4,
   input      [RES-1: 0] in5,
   input      [RES-1: 0] in6,
   input      [RES-1: 0] in7,


   output reg [RES-1: 0] out
);




always @(posedge clk)
   if (rst)
      out      <=  3'b0; 
   else
      case (sel)
         3'd00   :  out  <= in0  ;
         3'd01   :  out  <= in1  ;
         3'd02   :  out  <= in2  ;
         3'd03   :  out  <= in3  ;
         3'd04   :  out  <= in4  ;
         3'd05   :  out  <= in5  ;
         3'd06   :  out  <= in6  ;
         3'd07   :  out  <= in7  ;
         default :  out  <= 3'b0 ; 
      endcase ;
   
 


endmodule