data/full_repos/permissive/129127690/sign_ext.v
data/verilator_xmls/c71da06f-e66f-48df-b083-54ae06d62c4c.xml
module sign_ext #(parameter bus_size = 32, bus_size_in = 16) (
	input [bus_size_in-1:0] in,
	output [bus_size-1:0] 	out);
		
	wire tmp = in[bus_size_in-1];
	assign out[bus_size-1:0] = {{bus_size_in{tmp}},in};

endmodule
module sign_ext #(parameter bus_size = 32, bus_size_in = 16) (
	input [bus_size_in-1:0] in,
	output [bus_size-1:0] 	out);

		
	wire tmp = in[bus_size_in-1];
	assign out[bus_size-1:0] = {{bus_size_in{tmp}},in};

endmodule