data/full_repos/permissive/127511545/src/DFlipFlop.v
data/verilator_xmls/764a6120-f296-4b12-9887-171ba4d0533b.xml
module DFlipFlop(Q, D, Reset, CLK);
	
	output Q;
	input D, Reset, CLK;
	reg Q;

	always @(posedge CLK or posedge Reset)
		if (Reset)
			Q = 0;
		else
			Q = D;

endmodule
module DFlipFlop(Q, D, Reset, CLK);

	
	output Q;
	input D, Reset, CLK;
	reg Q;

	always @(posedge CLK or posedge Reset)
		if (Reset)
			Q = 0;
		else
			Q = D;

endmodule