data/full_repos/permissive/143278/vpi/range1.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/143278/vpi/range1.v:10: Unsupported or unknown PLI call: $sn\n    initial begin clk = 1\'b1; $sn; #160 $finish(0); end\n                              ^~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/vpi/range1.v:10: Unsupported: Ignoring delay on this delayed statement.\n    initial begin clk = 1\'b1; $sn; #160 $finish(0); end\n                                   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/vpi/range1.v:11: Unsupported: Ignoring delay on this delayed statement.\n    always #50 clk = ~clk;\n           ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module xor_try;

    reg  [1:0]  inp_xor;
    reg     out_xor;
    reg     clk;

    initial begin clk = 1'b1; $sn; #160 $finish(0); end
    always #50 clk = ~clk;


    always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]);

 endmodule
module xor_try;


    reg  [1:0]  inp_xor;
    reg     out_xor;
    reg     clk;

    initial begin clk = 1'b1; $sn; #160 $finish(0); end
    always #50 clk = ~clk;


    always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]);

 endmodule