data/full_repos/permissive/115403704/src/ALU.v
1: b'%Error: data/full_repos/permissive/115403704/src/ALU.v:1: Cannot find include file: ./alu_def.v\n`include "./alu_def.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/./alu_def.v\n             data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/./alu_def.v.v\n             data/full_repos/permissive/115403704/src,data/full_repos/permissive/115403704/./alu_def.v.sv\n             ./alu_def.v\n             ./alu_def.v.v\n             ./alu_def.v.sv\n             obj_dir/./alu_def.v\n             obj_dir/./alu_def.v.v\n             obj_dir/./alu_def.v.sv\n%Error: data/full_repos/permissive/115403704/src/ALU.v:22: Define or directive not defined: \'`ALU_ADD\'\n   `ALU_ADD : C = A + B;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:22: syntax error, unexpected \':\', expecting endcase\n   `ALU_ADD : C = A + B;\n            ^\n%Error: data/full_repos/permissive/115403704/src/ALU.v:23: Define or directive not defined: \'`ALU_SUB\'\n   `ALU_SUB : C = A - B;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:24: Define or directive not defined: \'`ALU_SLT\'\n   `ALU_SLT : C = $signed(A) < $signed(B) ? 1 : 0;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:25: Define or directive not defined: \'`ALU_SLTU\'\n      `ALU_SLTU: C = A < B ? 1 : 0;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:26: Define or directive not defined: \'`ALU_XOR\'\n   `ALU_XOR : C = A ^ B;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:27: Define or directive not defined: \'`ALU_AND\'\n   `ALU_AND : C = A & B;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:28: Define or directive not defined: \'`ALU_OR\'\n   `ALU_OR  : C = A | B;\n   ^~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:29: Define or directive not defined: \'`ALU_NOR\'\n   `ALU_NOR : C = ~(A | B);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:30: Define or directive not defined: \'`ALU_LUI\'\n   `ALU_LUI : C = {B[15:0] , 16\'d0};\n   ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:31: Define or directive not defined: \'`ALU_SLL\'\n   `ALU_SLL : C = B << A[4:0];\n   ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:32: Define or directive not defined: \'`ALU_SRL\'\n   `ALU_SRL : C = B >> A[4:0];\n   ^~~~~~~~\n%Error: data/full_repos/permissive/115403704/src/ALU.v:33: Define or directive not defined: \'`ALU_SRA\'\n   `ALU_SRA : C = (B >> A[4:0]) | ({32{B[31]}}<<(6\'d32-{1\'b0,A[4:0]}));\n   ^~~~~~~~\n%Error: Cannot continue\n'
module ALU(C,Zero,A,B,ALUOp,A_First,A_Zero);
	input  [31:0] 		A;
	input  [31:0]		B;
	input  [3:0]		ALUOp;	
	output reg[31:0]	C;
	output				Zero;
	output A_First;
	output A_Zero;
	initial
	begin
		C = 0;
	end
	
    assign Zero = (C==0) ? 1 : 0;
	assign A_First = A[31];
	assign A_Zero = (A==0)? 1 : 0;
	
	always@(A or B or ALUOp)
	begin
		case (ALUOp)
			`ALU_ADD : C = A + B;
			`ALU_SUB : C = A - B;
			`ALU_SLT : C = $signed(A) < $signed(B) ? 1 : 0;
    		`ALU_SLTU: C = A < B ? 1 : 0;
			`ALU_XOR : C = A ^ B;
			`ALU_AND : C = A & B;
			`ALU_OR  : C = A | B;
			`ALU_NOR : C = ~(A | B);
			`ALU_LUI : C = {B[15:0] , 16'd0};
			`ALU_SLL : C = B << A[4:0];
			`ALU_SRL : C = B >> A[4:0];
			`ALU_SRA : C = (B >> A[4:0]) | ({32{B[31]}}<<(6'd32-{1'b0,A[4:0]}));
		endcase
	end
endmodule
module ALU(C,Zero,A,B,ALUOp,A_First,A_Zero);

	input  [31:0] 		A;
	input  [31:0]		B;
	input  [3:0]		ALUOp;	
	output reg[31:0]	C;
	output				Zero;
	output A_First;
	output A_Zero;
	initial
	begin
		C = 0;
	end
	
    assign Zero = (C==0) ? 1 : 0;
	assign A_First = A[31];
	assign A_Zero = (A==0)? 1 : 0;
	
	always@(A or B or ALUOp)
	begin
		case (ALUOp)
			`ALU_ADD : C = A + B;
			`ALU_SUB : C = A - B;
			`ALU_SLT : C = $signed(A) < $signed(B) ? 1 : 0;
    		`ALU_SLTU: C = A < B ? 1 : 0;
			`ALU_XOR : C = A ^ B;
			`ALU_AND : C = A & B;
			`ALU_OR  : C = A | B;
			`ALU_NOR : C = ~(A | B);
			`ALU_LUI : C = {B[15:0] , 16'd0};
			`ALU_SLL : C = B << A[4:0];
			`ALU_SRL : C = B >> A[4:0];
			`ALU_SRA : C = (B >> A[4:0]) | ({32{B[31]}}<<(6'd32-{1'b0,A[4:0]}));
		endcase
	end
endmodule