data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v
1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n             MBScore_const.v\n             MBScore_const.v.v\n             MBScore_const.v.sv\n             obj_dir/MBScore_const.v\n             obj_dir/MBScore_const.v.v\n             obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:5: Define or directive not defined: \'`DATA_WIDTH\'\n    inout  [`DATA_WIDTH-1:0]        data_bus,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:6: Define or directive not defined: \'`INT_SEL_WIDTH\'\n    input  [`INT_SEL_WIDTH-1:0]     int_vec,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:8: Define or directive not defined: \'`ADDR_WIDTH\'\n    input  [`ADDR_WIDTH-1:0]        init_addr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:12: Define or directive not defined: \'`ADDR_WIDTH\'\n    output [`ADDR_WIDTH-1:0]        addr_bus,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:16: Define or directive not defined: \'`SYSCODE_WIDTH\'\n    output [`SYSCODE_WIDTH-1:0]     syscall_code,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:20: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n    wire [`ALU_SEL_WIDTH-1:0]   alu_sel_a,alu_sel_b;\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:21: Define or directive not defined: \'`ALU_OP_WIDTH\'\n    wire [`ALU_OP_WIDTH-1:0]    alu_op_type;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:23: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n    wire [`REG_ADDR_WIDTH-1:0]  rs_addr,rt_addr,rd_addr;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:25: Define or directive not defined: \'`IMM_WIDTH\'\n    wire [`IMM_WIDTH-1:0]       imm;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:26: Define or directive not defined: \'`DATA_WIDTH\'\n    wire [`DATA_WIDTH-1:0]      rs_data,rt_data,alu_a,alu_b,alu_out;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:27: Define or directive not defined: \'`ADDR_WIDTH\'\n    wire [`ADDR_WIDTH-1:0]      inst_mem_addr,data_mem_addr,int_addr;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:28: Define or directive not defined: \'`DATA_WIDTH\'\n    wire [`DATA_WIDTH-1:0]      inst;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:32: Define or directive not defined: \'`DATA_WIDTH\'\n    wire [`DATA_WIDTH-1:0]      rf_data_in;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:40: Define or directive not defined: \'`DATA_WIDTH\'\n    wire [`DATA_WIDTH-1:0]      spr_temp;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:45: Define or directive not defined: \'`DATA_WIDTH\'\n    wire [`DATA_WIDTH-1:0]      data_from_bus;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:46: Define or directive not defined: \'`ADDR_WIDTH\'\n    wire [`ADDR_WIDTH-1:0]      inst_addr,data_addr;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:47: Define or directive not defined: \'`OPCODE_LW\'\n    assign data_addr    = (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_SW) ? rs_data + $signed(inst[15:0]) : rs_data;\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:47: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n    assign data_addr    = (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_SW) ? rs_data + $signed(inst[15:0]) : rs_data;\n                                                     ^~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:47: Define or directive not defined: \'`OPCODE_SW\'\n    assign data_addr    = (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_SW) ? rs_data + $signed(inst[15:0]) : rs_data;\n                                                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:52: Define or directive not defined: \'`OPCODE_STREX\'\n    assign lock = ((inst[31:26] == `OPCODE_STREX || inst[31:26] == `OPCODE_LDREX) && (~inst_re) )? 1\'b1 : 1\'b0;\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:52: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n    assign lock = ((inst[31:26] == `OPCODE_STREX || inst[31:26] == `OPCODE_LDREX) && (~inst_re) )? 1\'b1 : 1\'b0;\n                                                 ^~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:52: Define or directive not defined: \'`OPCODE_LDREX\'\n    assign lock = ((inst[31:26] == `OPCODE_STREX || inst[31:26] == `OPCODE_LDREX) && (~inst_re) )? 1\'b1 : 1\'b0;\n                                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:133: Define or directive not defined: \'`OPCODE_STREX\'\n        .alu_data_in( (inst[31:26] == `OPCODE_STREX ) ? {31\'b0,lock_flag} : alu_out ),\n                                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:133: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        .alu_data_in( (inst[31:26] == `OPCODE_STREX ) ? {31\'b0,lock_flag} : alu_out ),\n                                                    ^\n%Error: Exiting due to 25 error(s)\n'
module MBScore_cpu_top(
    input                           clk,rst_n,
    inout  [`DATA_WIDTH-1:0]        data_bus,
    input  [`INT_SEL_WIDTH-1:0]     int_vec,
    input                           pause,
    input  [`ADDR_WIDTH-1:0]        init_addr,
    input                           cpu_sel,
    input                           lock_flag,
    output                          lock,
    output [`ADDR_WIDTH-1:0]        addr_bus,
    output                          ram_re,ram_we,
    output                          int_able,
    output                          syscall,
    output [`SYSCODE_WIDTH-1:0]     syscall_code,
    output [2:0]                    state
);

    wire [`ALU_SEL_WIDTH-1:0]   alu_sel_a,alu_sel_b;
    wire [`ALU_OP_WIDTH-1:0]    alu_op_type;
    wire                        alu_mux_ack;
    wire [`REG_ADDR_WIDTH-1:0]  rs_addr,rt_addr,rd_addr;
    wire                        reg_we,spr_sel,next,JAL_or_J,BEQ_or_BNE,JR,hlt;
    wire [`IMM_WIDTH-1:0]       imm;
    wire [`DATA_WIDTH-1:0]      rs_data,rt_data,alu_a,alu_b,alu_out;
    wire [`ADDR_WIDTH-1:0]      inst_mem_addr,data_mem_addr,int_addr;
    wire [`DATA_WIDTH-1:0]      inst;
    wire                        IR_ack;
    wire                        pc_we;
    wire                        data_mem_we;
    wire [`DATA_WIDTH-1:0]      rf_data_in;
    wire                        mem_to_reg_we;
    wire                        LUI;
    wire                        stop;
    wire                        setINTR;
    wire                        int_jump;
    wire                        cf;
    wire                        int_en_n;
    wire [`DATA_WIDTH-1:0]      spr_temp;
    wire                        data_mem_re;
    wire                        rf_clk,bus_clk;
    wire                        inst_re;

    wire [`DATA_WIDTH-1:0]      data_from_bus;
    wire [`ADDR_WIDTH-1:0]      inst_addr,data_addr;
    assign data_addr    = (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_SW) ? rs_data + $signed(inst[15:0]) : rs_data;
    assign inst_out     = inst;
    assign int_able     = ~int_en_n;
    assign syscall_code = inst[25:6];

    assign lock = ((inst[31:26] == `OPCODE_STREX || inst[31:26] == `OPCODE_LDREX) && (~inst_re) )? 1'b1 : 1'b0;

    MBScore_bus_ctrl bus_ctrl(
        .clk(bus_clk),
        .inst_addr(inst_addr),
        .data_addr(data_addr),
        .data_sel(data_mem_re | data_mem_we),
        .inst_re(inst_re),
        .data_re(data_mem_re),
        .data_we(data_mem_we),
        .addr(addr_bus),
        .data_rd(data_from_bus),
        .data_wr(rt_data),
        .ram_re(ram_re),
        .ram_we(ram_we),
        .data(data_bus),
        .cpu_sel(cpu_sel)
    );

    MBScore_ctrl ctrl(
        .state(state),
	    .clk(clk),
	    .rst_n(rst_n),
	    .inst(inst),
	    .IR_ack(IR_ack),
	    .alu_sel_a(alu_sel_a),
	    .alu_sel_b(alu_sel_b),
	    .alu_op_type(alu_op_type),
	    .alu_mux_ack(alu_mux_ack),
	    .rs_addr(rs_addr),
	    .rd_addr(rd_addr),
	    .rt_addr(rt_addr),
	    .reg_we(reg_we),
        .spr_sel(spr_sel),
	    .imm(imm),
	    .JAL_or_J(JAL_or_J),
        .BEQ_or_BNE(BEQ_or_BNE),
        .JR(JR),
        .hlt(hlt),
        .next(next),
        .pc_we(pc_we),
        .mem_we(data_mem_we),
        .mem_re(data_mem_re),
        .inst_re(inst_re),
        .mem_to_reg_we(mem_to_reg_we),
        .LUI(LUI),
        .stop(stop),
        .pause(pause),
        .syscall(syscall),
        .rf_clk(rf_clk),
        .bus_clk(bus_clk)
    );

    MBScore_IR IR(
	    .clk(clk),
	    .rst_n(rst_n),
	    .IR_ack(IR_ack),
	    .next(next),
	    .JAL_or_J(JAL_or_J),
	    .BEQ_or_BNE(BEQ_or_BNE),
	    .JR(JR),
	    .hlt(hlt),
	    .jump(alu_out[0]),
	    .next_addr(rs_data),
        .int_addr(int_addr),
	    .inst_in(data_from_bus),
	    .inst_out(inst),
	    .pc_out(inst_addr),
        .int_jump(int_jump),
        .init_addr(init_addr)
    );

    MBScore_rf rf(
        .clk(rf_clk),
        .rst_n(rst_n),
        .rs_addr(rs_addr),
        .rd_addr(rd_addr),
        .rt_addr(rt_addr),
        .reg_we(reg_we),
        .mem_to_reg_we(mem_to_reg_we),
        .spr_sel(spr_sel),
        .alu_data_in( (inst[31:26] == `OPCODE_STREX ) ? {31'b0,lock_flag} : alu_out ),
        .mem_data_in(data_from_bus),
        .rs_out(rs_data),
        .rt_out(rt_data),
        .pc_we(pc_we),
        .pc_in(inst_addr),
        .LUI(LUI),
        .setINTR(setINTR),
        .int_en_n(int_en_n),
        .spr_out(spr_temp),
        .spr_in(spr_temp)
    );

    MBScore_alu_operator_mux alu_op_mux(
        .clk(clk),
        .alu_mux_ack(alu_mux_ack),
        .imm(imm),
        .alu_sel_a(alu_sel_a),
	    .alu_sel_b(alu_sel_b),
        .rs(rs_data),
        .rt(rt_data),
        .alu_a(alu_a),
        .alu_b(alu_b)
    );

    MBScore_alu alu(
        .clk(clk),
        .rst_n(rst_n),
        .alu_in_a(alu_a),
        .alu_in_b(alu_b),
        .alu_op_type(alu_op_type),
        .alu_out(alu_out),
        .cf(cf)
    );

    MBScore_interrupt_ctrl int_ctrl(
        .clk(clk),
        .rst_n(rst_n),
        .int_vec(int_vec),
        .int_en_n(int_en_n),  
        .stop(stop),
        .setINTR(setINTR),
        .int_addr(int_addr),
        .int_jump(int_jump)
    );

endmodule
module MBScore_cpu_top(
    input                           clk,rst_n,
    inout  [`DATA_WIDTH-1:0]        data_bus,
    input  [`INT_SEL_WIDTH-1:0]     int_vec,
    input                           pause,
    input  [`ADDR_WIDTH-1:0]        init_addr,
    input                           cpu_sel,
    input                           lock_flag,
    output                          lock,
    output [`ADDR_WIDTH-1:0]        addr_bus,
    output                          ram_re,ram_we,
    output                          int_able,
    output                          syscall,
    output [`SYSCODE_WIDTH-1:0]     syscall_code,
    output [2:0]                    state
);


    wire [`ALU_SEL_WIDTH-1:0]   alu_sel_a,alu_sel_b;
    wire [`ALU_OP_WIDTH-1:0]    alu_op_type;
    wire                        alu_mux_ack;
    wire [`REG_ADDR_WIDTH-1:0]  rs_addr,rt_addr,rd_addr;
    wire                        reg_we,spr_sel,next,JAL_or_J,BEQ_or_BNE,JR,hlt;
    wire [`IMM_WIDTH-1:0]       imm;
    wire [`DATA_WIDTH-1:0]      rs_data,rt_data,alu_a,alu_b,alu_out;
    wire [`ADDR_WIDTH-1:0]      inst_mem_addr,data_mem_addr,int_addr;
    wire [`DATA_WIDTH-1:0]      inst;
    wire                        IR_ack;
    wire                        pc_we;
    wire                        data_mem_we;
    wire [`DATA_WIDTH-1:0]      rf_data_in;
    wire                        mem_to_reg_we;
    wire                        LUI;
    wire                        stop;
    wire                        setINTR;
    wire                        int_jump;
    wire                        cf;
    wire                        int_en_n;
    wire [`DATA_WIDTH-1:0]      spr_temp;
    wire                        data_mem_re;
    wire                        rf_clk,bus_clk;
    wire                        inst_re;

    wire [`DATA_WIDTH-1:0]      data_from_bus;
    wire [`ADDR_WIDTH-1:0]      inst_addr,data_addr;
    assign data_addr    = (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_SW) ? rs_data + $signed(inst[15:0]) : rs_data;
    assign inst_out     = inst;
    assign int_able     = ~int_en_n;
    assign syscall_code = inst[25:6];

    assign lock = ((inst[31:26] == `OPCODE_STREX || inst[31:26] == `OPCODE_LDREX) && (~inst_re) )? 1'b1 : 1'b0;

    MBScore_bus_ctrl bus_ctrl(
        .clk(bus_clk),
        .inst_addr(inst_addr),
        .data_addr(data_addr),
        .data_sel(data_mem_re | data_mem_we),
        .inst_re(inst_re),
        .data_re(data_mem_re),
        .data_we(data_mem_we),
        .addr(addr_bus),
        .data_rd(data_from_bus),
        .data_wr(rt_data),
        .ram_re(ram_re),
        .ram_we(ram_we),
        .data(data_bus),
        .cpu_sel(cpu_sel)
    );

    MBScore_ctrl ctrl(
        .state(state),
	    .clk(clk),
	    .rst_n(rst_n),
	    .inst(inst),
	    .IR_ack(IR_ack),
	    .alu_sel_a(alu_sel_a),
	    .alu_sel_b(alu_sel_b),
	    .alu_op_type(alu_op_type),
	    .alu_mux_ack(alu_mux_ack),
	    .rs_addr(rs_addr),
	    .rd_addr(rd_addr),
	    .rt_addr(rt_addr),
	    .reg_we(reg_we),
        .spr_sel(spr_sel),
	    .imm(imm),
	    .JAL_or_J(JAL_or_J),
        .BEQ_or_BNE(BEQ_or_BNE),
        .JR(JR),
        .hlt(hlt),
        .next(next),
        .pc_we(pc_we),
        .mem_we(data_mem_we),
        .mem_re(data_mem_re),
        .inst_re(inst_re),
        .mem_to_reg_we(mem_to_reg_we),
        .LUI(LUI),
        .stop(stop),
        .pause(pause),
        .syscall(syscall),
        .rf_clk(rf_clk),
        .bus_clk(bus_clk)
    );

    MBScore_IR IR(
	    .clk(clk),
	    .rst_n(rst_n),
	    .IR_ack(IR_ack),
	    .next(next),
	    .JAL_or_J(JAL_or_J),
	    .BEQ_or_BNE(BEQ_or_BNE),
	    .JR(JR),
	    .hlt(hlt),
	    .jump(alu_out[0]),
	    .next_addr(rs_data),
        .int_addr(int_addr),
	    .inst_in(data_from_bus),
	    .inst_out(inst),
	    .pc_out(inst_addr),
        .int_jump(int_jump),
        .init_addr(init_addr)
    );

    MBScore_rf rf(
        .clk(rf_clk),
        .rst_n(rst_n),
        .rs_addr(rs_addr),
        .rd_addr(rd_addr),
        .rt_addr(rt_addr),
        .reg_we(reg_we),
        .mem_to_reg_we(mem_to_reg_we),
        .spr_sel(spr_sel),
        .alu_data_in( (inst[31:26] == `OPCODE_STREX ) ? {31'b0,lock_flag} : alu_out ),
        .mem_data_in(data_from_bus),
        .rs_out(rs_data),
        .rt_out(rt_data),
        .pc_we(pc_we),
        .pc_in(inst_addr),
        .LUI(LUI),
        .setINTR(setINTR),
        .int_en_n(int_en_n),
        .spr_out(spr_temp),
        .spr_in(spr_temp)
    );

    MBScore_alu_operator_mux alu_op_mux(
        .clk(clk),
        .alu_mux_ack(alu_mux_ack),
        .imm(imm),
        .alu_sel_a(alu_sel_a),
	    .alu_sel_b(alu_sel_b),
        .rs(rs_data),
        .rt(rt_data),
        .alu_a(alu_a),
        .alu_b(alu_b)
    );

    MBScore_alu alu(
        .clk(clk),
        .rst_n(rst_n),
        .alu_in_a(alu_a),
        .alu_in_b(alu_b),
        .alu_op_type(alu_op_type),
        .alu_out(alu_out),
        .cf(cf)
    );

    MBScore_interrupt_ctrl int_ctrl(
        .clk(clk),
        .rst_n(rst_n),
        .int_vec(int_vec),
        .int_en_n(int_en_n),  
        .stop(stop),
        .setINTR(setINTR),
        .int_addr(int_addr),
        .int_jump(int_jump)
    );

endmodule