data/full_repos/permissive/167962127/phase_accu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167962127/phase_accu_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/167962127/phase_accu_tb.v:9: Cannot find file containing module: \'phase_accu\'\n  phase_accu UUT(\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/phase_accu\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/phase_accu.v\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/phase_accu.sv\n             phase_accu\n             phase_accu.v\n             phase_accu.sv\n             obj_dir/phase_accu\n             obj_dir/phase_accu.v\n             obj_dir/phase_accu.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module phase_accu_tb();
 
  reg clk5 = 0;
  reg [23:0] fcw = 24'hffffff;
  wire [15:0] addr;

  phase_accu UUT(
    .i_clk5MHz(clk5),
    .i_fcw(fcw),
    .o_16bit_addr(addr)
  );

  

  always
  begin
    #100
    clk5 = !clk5;
  end

endmodule
module phase_accu_tb();

 
  reg clk5 = 0;
  reg [23:0] fcw = 24'hffffff;
  wire [15:0] addr;

  phase_accu UUT(
    .i_clk5MHz(clk5),
    .i_fcw(fcw),
    .o_16bit_addr(addr)
  );

  

  always
  begin
    #100
    clk5 = !clk5;
  end

endmodule