data/full_repos/permissive/137045072/pipeline.v
1: b'%Error: data/full_repos/permissive/137045072/pipeline.v:24: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/137045072/pipeline.v:41: Define or directive not defined: \'`PREG_BUS\'\n    input [`PREG_BUS] dec_rs_addr,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`PREG_BUS] dec_rs_addr,\n                    ^\n%Error: data/full_repos/permissive/137045072/pipeline.v:43: Define or directive not defined: \'`PREG_BUS\'\n    input [`PREG_BUS] dec_rt_addr,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:47: Define or directive not defined: \'`PREG_BUS\'\n    input [`PREG_BUS] exec_physical_write_addr,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:51: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] exec_branch_target,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:60: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output     fetch_flush,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:64: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg decode_flush,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:67: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg exec_stall,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:68: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg exec_flush,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:71: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg mem_stall,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:72: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg mem_flush,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:75: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg wb_stall,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:76: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg wb_flush,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:78: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg global_flush,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:81: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg fetch_branch,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:82: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`DATA_BUS] fetch_branch_target,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:82: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] fetch_branch_target,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:86: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] exception,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:87: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] mem_cp0_epc\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:91: Define or directive not defined: \'`DATA_BUS\'\n    reg [`DATA_BUS] fetch_addr;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:91: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`DATA_BUS] fetch_addr;\n                  ^\n%Error: data/full_repos/permissive/137045072/pipeline.v:94: syntax error, unexpected assign\n    assign fetch_flush = fetch_flush_data || fetch_flush_control;\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:103: syntax error, unexpected always\n    always @*\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:282: Define or directive not defined: \'`EXCEPT_INTERRUPT\'\n                    `EXCEPT_INTERRUPT: begin\n                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:283: Define or directive not defined: \'`EXCEPT_INTERRUPT_ADDR\'\n                        fetch_addr <= `EXCEPT_INTERRUPT_ADDR;\n                                      ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:285: Define or directive not defined: \'`EXCEPT_SYSCALL\'\n                    `EXCEPT_SYSCALL: begin\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:286: Define or directive not defined: \'`EXCEPT_SYSCALL_ADDR\'\n                        fetch_addr <= `EXCEPT_SYSCALL_ADDR;\n                                      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:288: Define or directive not defined: \'`EXCEPT_ILLEGAL\'\n                    `EXCEPT_ILLEGAL: begin\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:289: Define or directive not defined: \'`EXCEPT_ILLEGAL_ADDR\'\n                        fetch_addr <= `EXCEPT_ILLEGAL_ADDR;\n                                      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:291: Define or directive not defined: \'`EXCEPT_TRAP\'\n                    `EXCEPT_TRAP: begin\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:292: Define or directive not defined: \'`EXCEPT_TRAP_ADDR\'\n                        fetch_addr <= `EXCEPT_TRAP_ADDR;\n                                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:294: Define or directive not defined: \'`EXCEPT_OVERFLOW\'\n                    `EXCEPT_OVERFLOW: begin\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:295: Define or directive not defined: \'`EXCEPT_OVERFLOW_ADDR\'\n                        fetch_addr <= `EXCEPT_OVERFLOW_ADDR;\n                                      ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline.v:297: Define or directive not defined: \'`EXCEPT_ERET\'\n                    `EXCEPT_ERET: begin\n                    ^~~~~~~~~~~~\n%Error: Exiting due to 35 error(s)\n'
module pipeline#(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,

    input external_done,
    input done,
    
    input regfile_stall,



    input fetch_done,


    input dec_rs_enable,
    input [`PREG_BUS] dec_rs_addr,
    input dec_rt_enable,
    input [`PREG_BUS] dec_rt_addr,
    input decode_branch,


    input [`PREG_BUS] exec_physical_write_addr,
    input exec_mem_enable,
    input exec_wb_reg,
    input exec_take_branch,
    input [`DATA_BUS] exec_branch_target,


    input mem_done,

    


    output reg fetch_stall,
    output     fetch_flush,


    output reg decode_stall,
    output reg decode_flush,


    output reg exec_stall,
    output reg exec_flush,


    output reg mem_stall,
    output reg mem_flush,


    output reg wb_stall,
    output reg wb_flush,

    output reg global_flush,


    output reg fetch_branch,
    output reg [`DATA_BUS] fetch_branch_target,


    
    input [`DATA_BUS] exception,
    input [`DATA_BUS] mem_cp0_epc
    );

    reg fetch_load;
    reg [`DATA_BUS] fetch_addr;
    reg fetch_flush_data;
    reg fetch_flush_control;
    assign fetch_flush = fetch_flush_data || fetch_flush_control;

    wire executing = external_done && !done;






    always @*
    begin
        fetch_stall <= 0;
        fetch_flush_data <= 0;

        if (executing)
        begin



            if (decode_stall || !fetch_done)
                fetch_stall <= 1;

            if (exec_take_branch || !fetch_done)
                fetch_flush_data <= 1;
        end
        else
        begin
            fetch_stall <= 1;
            fetch_flush_data <= 1;
        end
    end


    always @*
    begin
        decode_stall <= 0;
        decode_flush <= 0;

        if (executing)
        begin   


            if (decode_branch && !fetch_done)
            begin
                decode_stall <= 1;
                decode_flush <= 1;
            end
            
            if (exec_take_branch)
                decode_flush <= 1;




            if (exec_wb_reg && exec_mem_enable && (
                (dec_rs_addr == exec_physical_write_addr && dec_rs_enable) ||
                (dec_rt_addr == exec_physical_write_addr && dec_rt_enable)))
            begin
                decode_stall <= 1;
                decode_flush <= 1;
            end


            if (exec_stall || regfile_stall)
                decode_stall <= 1;
        end
        else
        begin
            decode_stall <= 1;
            decode_flush <= 1;
        end
    end


    always @*
    begin
        exec_stall <= 0;
        exec_flush <= 0;

        if (executing)
        begin

            if (mem_stall)
                exec_stall <= 1;
        end
        else
        begin
            exec_stall <= 1;
            exec_flush <= 1;
        end
    end


    always @*
    begin
        mem_stall <= 0;
        mem_flush <= 0;

        if (executing)
        begin

            if (!mem_done)
            begin
                mem_stall <= 1;
                mem_flush <= 1;
            end


            if (wb_stall)
                mem_stall <= 1;
        end
        else
        begin
            mem_stall <= 1;
            mem_flush <= 1;
        end
    end


    always @*
    begin
        wb_stall <= 0;
        wb_flush <= 0;

        if (executing)
        begin

        end
        else
        begin
            wb_stall <= 1;
            wb_flush <= 1;
        end
    end





    always @*
    begin

        fetch_branch <= exec_take_branch || fetch_load;
        if (exec_take_branch)
            fetch_branch_target <= exec_branch_target;
        else
            fetch_branch_target <= fetch_addr;
    end

    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            fetch_flush_control <= 0;
        end
        else
        begin



            if (exec_take_branch && !fetch_done)
            begin
                fetch_flush_control <= 1;
            end
            else if (fetch_flush_control && fetch_done)
            begin

                fetch_flush_control <= 0;
            end
        end
    end

    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            global_flush <= 0;
            fetch_load <= 0;
            fetch_addr <= 'bx;
        end
        else
        begin
            global_flush <= 0;
            if (exception != 0)
            begin
                global_flush <= 1;
                fetch_load <= 1;
                case (exception)
                    `EXCEPT_INTERRUPT: begin
                        fetch_addr <= `EXCEPT_INTERRUPT_ADDR;
                    end
                    `EXCEPT_SYSCALL: begin
                        fetch_addr <= `EXCEPT_SYSCALL_ADDR;
                    end
                    `EXCEPT_ILLEGAL: begin
                        fetch_addr <= `EXCEPT_ILLEGAL_ADDR;
                    end
                    `EXCEPT_TRAP: begin
                        fetch_addr <= `EXCEPT_TRAP_ADDR;
                    end
                    `EXCEPT_OVERFLOW: begin
                        fetch_addr <= `EXCEPT_OVERFLOW_ADDR;
                    end
                    `EXCEPT_ERET: begin
                        fetch_addr <= mem_cp0_epc;
                    end
                    default: begin
                        fetch_addr <= 0;
                    end
                endcase
            end
            else if (fetch_stall && exec_take_branch)
            begin
                fetch_load <= 1;
                fetch_addr <= exec_branch_target;
            end
            else if (fetch_load && !fetch_stall)
            begin
                fetch_load <= 0;
                fetch_addr <= 'bx;
            end
        end
    end
endmodule
module pipeline#(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,

    input external_done,
    input done,
    
    input regfile_stall,



    input fetch_done,


    input dec_rs_enable,
    input [`PREG_BUS] dec_rs_addr,
    input dec_rt_enable,
    input [`PREG_BUS] dec_rt_addr,
    input decode_branch,


    input [`PREG_BUS] exec_physical_write_addr,
    input exec_mem_enable,
    input exec_wb_reg,
    input exec_take_branch,
    input [`DATA_BUS] exec_branch_target,


    input mem_done,

    


    output reg fetch_stall,
    output     fetch_flush,


    output reg decode_stall,
    output reg decode_flush,


    output reg exec_stall,
    output reg exec_flush,


    output reg mem_stall,
    output reg mem_flush,


    output reg wb_stall,
    output reg wb_flush,

    output reg global_flush,


    output reg fetch_branch,
    output reg [`DATA_BUS] fetch_branch_target,


    
    input [`DATA_BUS] exception,
    input [`DATA_BUS] mem_cp0_epc
    );


    reg fetch_load;
    reg [`DATA_BUS] fetch_addr;
    reg fetch_flush_data;
    reg fetch_flush_control;
    assign fetch_flush = fetch_flush_data || fetch_flush_control;

    wire executing = external_done && !done;






    always @*
    begin
        fetch_stall <= 0;
        fetch_flush_data <= 0;

        if (executing)
        begin



            if (decode_stall || !fetch_done)
                fetch_stall <= 1;

            if (exec_take_branch || !fetch_done)
                fetch_flush_data <= 1;
        end
        else
        begin
            fetch_stall <= 1;
            fetch_flush_data <= 1;
        end
    end


    always @*
    begin
        decode_stall <= 0;
        decode_flush <= 0;

        if (executing)
        begin   


            if (decode_branch && !fetch_done)
            begin
                decode_stall <= 1;
                decode_flush <= 1;
            end
            
            if (exec_take_branch)
                decode_flush <= 1;




            if (exec_wb_reg && exec_mem_enable && (
                (dec_rs_addr == exec_physical_write_addr && dec_rs_enable) ||
                (dec_rt_addr == exec_physical_write_addr && dec_rt_enable)))
            begin
                decode_stall <= 1;
                decode_flush <= 1;
            end


            if (exec_stall || regfile_stall)
                decode_stall <= 1;
        end
        else
        begin
            decode_stall <= 1;
            decode_flush <= 1;
        end
    end


    always @*
    begin
        exec_stall <= 0;
        exec_flush <= 0;

        if (executing)
        begin

            if (mem_stall)
                exec_stall <= 1;
        end
        else
        begin
            exec_stall <= 1;
            exec_flush <= 1;
        end
    end


    always @*
    begin
        mem_stall <= 0;
        mem_flush <= 0;

        if (executing)
        begin

            if (!mem_done)
            begin
                mem_stall <= 1;
                mem_flush <= 1;
            end


            if (wb_stall)
                mem_stall <= 1;
        end
        else
        begin
            mem_stall <= 1;
            mem_flush <= 1;
        end
    end


    always @*
    begin
        wb_stall <= 0;
        wb_flush <= 0;

        if (executing)
        begin

        end
        else
        begin
            wb_stall <= 1;
            wb_flush <= 1;
        end
    end





    always @*
    begin

        fetch_branch <= exec_take_branch || fetch_load;
        if (exec_take_branch)
            fetch_branch_target <= exec_branch_target;
        else
            fetch_branch_target <= fetch_addr;
    end

    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            fetch_flush_control <= 0;
        end
        else
        begin



            if (exec_take_branch && !fetch_done)
            begin
                fetch_flush_control <= 1;
            end
            else if (fetch_flush_control && fetch_done)
            begin

                fetch_flush_control <= 0;
            end
        end
    end

    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            global_flush <= 0;
            fetch_load <= 0;
            fetch_addr <= 'bx;
        end
        else
        begin
            global_flush <= 0;
            if (exception != 0)
            begin
                global_flush <= 1;
                fetch_load <= 1;
                case (exception)
                    `EXCEPT_INTERRUPT: begin
                        fetch_addr <= `EXCEPT_INTERRUPT_ADDR;
                    end
                    `EXCEPT_SYSCALL: begin
                        fetch_addr <= `EXCEPT_SYSCALL_ADDR;
                    end
                    `EXCEPT_ILLEGAL: begin
                        fetch_addr <= `EXCEPT_ILLEGAL_ADDR;
                    end
                    `EXCEPT_TRAP: begin
                        fetch_addr <= `EXCEPT_TRAP_ADDR;
                    end
                    `EXCEPT_OVERFLOW: begin
                        fetch_addr <= `EXCEPT_OVERFLOW_ADDR;
                    end
                    `EXCEPT_ERET: begin
                        fetch_addr <= mem_cp0_epc;
                    end
                    default: begin
                        fetch_addr <= 0;
                    end
                endcase
            end
            else if (fetch_stall && exec_take_branch)
            begin
                fetch_load <= 1;
                fetch_addr <= exec_branch_target;
            end
            else if (fetch_load && !fetch_stall)
            begin
                fetch_load <= 0;
                fetch_addr <= 'bx;
            end
        end
    end
endmodule