data/full_repos/permissive/129155059/counter/synth.v
 line:61: before: "*"
1: b'%Error: data/full_repos/permissive/129155059/counter/synth.v:56: Can\'t resolve module reference: \'$_DLATCH_P_\'\n  \\$_DLATCH_P_  _10_ (\n                ^~~~\n%Warning-MULTITOP: data/full_repos/permissive/129155059/counter/synth.v:56: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                          : ... Top module \'counter\'\nmodule counter(out, iclk, ireset);\n       ^~~~~~~\n                                                                          : ... Top module \'$_DLATCH_P_\'\n  \\$_DLATCH_P_  _10_ (\n                ^~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module counter(out, iclk, ireset);
  (* src = "counter.v:11" *)
  wire [7:0] _00_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _01_;
  (* src = "counter.v:6" *)
  input iclk;
  (* src = "counter.v:6" *)
  input ireset;
  (* src = "counter.v:5" *)
  output [7:0] out;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[0];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[1];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[2];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[3];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[4];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[5];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[6];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[7];
  assign out[7] = \out_reg[7] ;
  \$_DLATCH_P_  _10_ (
    .D(1'b0),
    .E(ireset),
    .Q(out[7])
  );
  assign _00_[1] = out[7] ^(* src = "<techmap.v>:263" *)  out[7];
  assign _00_[2] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[1];
  assign _00_[3] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[2];
  assign _00_[4] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[3];
  assign _00_[5] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[4];
  assign _00_[6] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[5];
  assign _00_[7] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[6];
  assign _01_[1] = out[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  out[7];
  assign _01_[3] = _01_[1] &(* src = "<techmap.v>:260|<techmap.v>:222" *)  _01_[1];
  assign _01_[5] = _01_[1] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _01_[3];
  assign _01_[2] = out[7] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _01_[1];
  assign _01_[4] = out[7] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _01_[3];
  assign _01_[6] = out[7] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _01_[5];
  assign _00_[0] = out[7] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign out[6:0] = { out[7], out[7], out[7], out[7], out[7], out[7], out[7] };
endmodule
module counter(out, iclk, ireset);

  (* src = "counter.v:11" *)
  wire [7:0] _00_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _01_;
  (* src = "counter.v:6" *)
  input iclk;
  (* src = "counter.v:6" *)
  input ireset;
  (* src = "counter.v:5" *)
  output [7:0] out;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[0];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[1];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[2];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[3];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[4];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[5];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[6];
  assign out[7] = \out_reg[7] ;
  reg \out_reg[7] ;
  (* src = "counter.v:11" *)
  always @(posedge iclk)
      \out_reg[7]  <= _00_[7];
  assign out[7] = \out_reg[7] ;
  \$_DLATCH_P_  _10_ (
    .D(1'b0),
    .E(ireset),
    .Q(out[7])
  );
  assign _00_[1] = out[7] ^(* src = "<techmap.v>:263" *)  out[7];
  assign _00_[2] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[1];
  assign _00_[3] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[2];
  assign _00_[4] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[3];
  assign _00_[5] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[4];
  assign _00_[6] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[5];
  assign _00_[7] = out[7] ^(* src = "<techmap.v>:263" *)  _01_[6];
  assign _01_[1] = out[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  out[7];
  assign _01_[3] = _01_[1] &(* src = "<techmap.v>:260|<techmap.v>:222" *)  _01_[1];
  assign _01_[5] = _01_[1] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _01_[3];
  assign _01_[2] = out[7] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _01_[1];
  assign _01_[4] = out[7] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _01_[3];
  assign _01_[6] = out[7] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _01_[5];
  assign _00_[0] = out[7] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign out[6:0] = { out[7], out[7], out[7], out[7], out[7], out[7], out[7] };
endmodule