data/full_repos/permissive/156609923/fifo/memoria.v
data/verilator_xmls/51011d5c-5c0e-4520-a41f-f9250e433570.xml
module memoria#(

		parameter BUS_SIZE = 5,
		parameter ADDR_WIDTH = 3,
		parameter MEM_LENGTH = 1 << ADDR_WIDTH
		
	) (
	input 			  clk,
	input 			  read,
	input 			  reset,
	input 			  write,
	input [BUS_SIZE-1:0] 	  data_in,
	input [ADDR_WIDTH-1:0] 	  addressR,
	input [ADDR_WIDTH-1:0] 	  addressW,
	output reg [BUS_SIZE-1:0] data_out
);


reg [BUS_SIZE-1:0] mem [MEM_LENGTH-1:0];

always @ (posedge clk) begin
	if(reset)
	    data_out <= 0;
	else begin
  		if (write)  mem[addressW] <= data_in;
  		if (read) data_out <= mem[addressR];
	end
	   
end

endmodule
module memoria#(

		parameter BUS_SIZE = 5,
		parameter ADDR_WIDTH = 3,
		parameter MEM_LENGTH = 1 << ADDR_WIDTH
		
	) (
	input 			  clk,
	input 			  read,
	input 			  reset,
	input 			  write,
	input [BUS_SIZE-1:0] 	  data_in,
	input [ADDR_WIDTH-1:0] 	  addressR,
	input [ADDR_WIDTH-1:0] 	  addressW,
	output reg [BUS_SIZE-1:0] data_out
);



reg [BUS_SIZE-1:0] mem [MEM_LENGTH-1:0];

always @ (posedge clk) begin
	if(reset)
	    data_out <= 0;
	else begin
  		if (write)  mem[addressW] <= data_in;
  		if (read) data_out <= mem[addressR];
	end
	   
end

endmodule