data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v
 line:1: before: "["
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:7: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:25: Unsupported: Ignoring delay on this delayed statement.\n       #1 A[103:8] = {$random, $random, $random};\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:32: Unsupported: Ignoring delay on this delayed statement.\n       #1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #120000;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:26: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                     : ... In instance test.stim\n          A[7:0] = $random % 256;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:28: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                     : ... In instance test.stim\n          B[7:0] = $random % 256;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:34: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                     : ... In instance test.stim\n       A[7:0] = $random % 256;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:36: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                     : ... In instance test.stim\n       B[7:0] = $random % 256;\n              ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:73: Cannot find file containing module: \'xnor104\'\n  xnor104      duv            (.a_i(a), .b_i(b), .c_o(r) );\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/xnor104\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/xnor104.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/xnor104.sv\n             xnor104\n             xnor104.v\n             xnor104.sv\n             obj_dir/xnor104\n             obj_dir/xnor104.v\n             obj_dir/xnor104.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stimulus (output reg unsigned [103:0] A, B);
  parameter S = 2000;
  int unsigned i;


  initial begin
    A = 0; B= 0;

    for (i=0; i<S; i=i+1) begin
       #1 A[103:8] = {$random, $random, $random};
          A[7:0] = $random % 256;
          B[103:8] = {$random, $random, $random};
          B[7:0] = $random % 256;
    end

    for (i=0; i<S; i=i+1) begin
       #1;
       A[103:8] = {$random, $random, $random};
       A[7:0] = $random % 256;
       B[103:8] = {$random, $random, $random};
       B[7:0] = $random % 256;
       A[103:72] = xz_inject (A[103:72]);
       A[71:40]  = xz_inject (A[71:40]);
       B[71:40]  = xz_inject (B[71:40]);
       B[39:8]   = xz_inject (B[39:8]);
    end
  end


  function [31:0] xz_inject (input unsigned [31:0] value);
      integer i, temp;
      begin
        temp = {$random};
        for (i=0; i<32; i=i+1)
          begin
             if (temp[i] == 1'b1)
               begin
                 temp = $random;
                 if (temp <= 0)
                    value[i] = 1'bx;
                 else
                    value[i] = 1'bz;
               end
          end
          xz_inject = value;
      end
  endfunction


endmodule
module stimulus (output reg unsigned [103:0] A, B);

  parameter S = 2000;
  int unsigned i;


  initial begin
    A = 0; B= 0;

    for (i=0; i<S; i=i+1) begin
       #1 A[103:8] = {$random, $random, $random};
          A[7:0] = $random % 256;
          B[103:8] = {$random, $random, $random};
          B[7:0] = $random % 256;
    end

    for (i=0; i<S; i=i+1) begin
       #1;
       A[103:8] = {$random, $random, $random};
       A[7:0] = $random % 256;
       B[103:8] = {$random, $random, $random};
       B[7:0] = $random % 256;
       A[103:72] = xz_inject (A[103:72]);
       A[71:40]  = xz_inject (A[71:40]);
       B[71:40]  = xz_inject (B[71:40]);
       B[39:8]   = xz_inject (B[39:8]);
    end
  end


  function [31:0] xz_inject (input unsigned [31:0] value);
      integer i, temp;
      begin
        temp = {$random};
        for (i=0; i<32; i=i+1)
          begin
             if (temp[i] == 1'b1)
               begin
                 temp = $random;
                 if (temp <= 0)
                    value[i] = 1'bx;
                 else
                    value[i] = 1'bz;
               end
          end
          xz_inject = value;
      end
  endfunction


endmodule