data/full_repos/permissive/173150157/rtl/test/async_reset_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/async_reset_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #3.14159\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/async_reset_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #27.1828\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/async_reset_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #40\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/async_reset_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #15\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/async_reset_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/173150157/rtl/test/async_reset_tb.v:14: Cannot find file containing module: \'async_reset\'\n    async_reset async_reset_instance (\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/async_reset\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/async_reset.v\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/async_reset.sv\n             async_reset\n             async_reset.v\n             async_reset.sv\n             obj_dir/async_reset\n             obj_dir/async_reset.v\n             obj_dir/async_reset.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module async_reset_tb();

    reg rst;
    reg clk;

    wire rst_output;
    async_reset async_reset_instance (
        .i_clk(clk),
        .i_rst(rst),
        .o_rst(rst_output)
    );

    initial begin
        $display($time, " << Starting Simulation >>");
        clk = 1;
        rst = 0;

        #3.14159
        rst = 1;

        #27.1828
        rst = 0;

        #40
        rst = 1;

        #15
        rst = 0;
    end

    always
        #5 clk = ~clk;

endmodule
module async_reset_tb();


    reg rst;
    reg clk;

    wire rst_output;
    async_reset async_reset_instance (
        .i_clk(clk),
        .i_rst(rst),
        .o_rst(rst_output)
    );

    initial begin
        $display($time, " << Starting Simulation >>");
        clk = 1;
        rst = 0;

        #3.14159
        rst = 1;

        #27.1828
        rst = 0;

        #40
        rst = 1;

        #15
        rst = 0;
    end

    always
        #5 clk = ~clk;

endmodule