data/full_repos/permissive/143278/ivltests/always3.1.3E2.v
 line:37: before: "value1"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.3E2.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #15;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/always3.1.3E2.v:37: Unsupported: Verilog 1995 force\nalways #10 force value1 = 1\'b1 & 1\'b1 ;\n           ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.3E2.v:37: Unsupported: Ignoring delay on this delayed statement.\nalways #10 force value1 = 1\'b1 & 1\'b1 ;\n       ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ;

reg [3:0] value1 ;

initial
  begin
    #15;
    if(value1 !== 4'b1)
      $display("FAILED - 3.1.3E always force reg_lvalue = boolean_expr;");
    else
      $display("PASSED");
     $finish;
  end

always #10 force value1 = 1'b1 & 1'b1 ;

endmodule
module main ;


reg [3:0] value1 ;

initial
  begin
    #15;
    if(value1 !== 4'b1)
      $display("FAILED - 3.1.3E always force reg_lvalue = boolean_expr;");
    else
      $display("PASSED");
     $finish;
  end

always #10 force value1 = 1'b1 & 1'b1 ;

endmodule