data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v:64: Cannot find include file: adbg_wb_defines.v\n`include "adbg_wb_defines.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog,data/full_repos/permissive/17099167/adbg_wb_defines.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog,data/full_repos/permissive/17099167/adbg_wb_defines.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog,data/full_repos/permissive/17099167/adbg_wb_defines.v.sv\n             adbg_wb_defines.v\n             adbg_wb_defines.v.v\n             adbg_wb_defines.v.sv\n             obj_dir/adbg_wb_defines.v\n             obj_dir/adbg_wb_defines.v.v\n             obj_dir/adbg_wb_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module adbg_wb_biu
  (

   tck_i,
   rst_i,
   data_i,
   data_o,
   addr_i,
   strobe_i,
   rd_wrn_i,
   rdy_o,
   err_o,
   word_size_i,


   wb_clk_i,
   wb_adr_o,
   wb_dat_o,
   wb_dat_i,
   wb_cyc_o,
   wb_stb_o,
   wb_sel_o,
   wb_we_o,
   wb_ack_i,
   wb_cab_o,
   wb_err_i,
   wb_cti_o,
   wb_bte_o
   );


   input tck_i;
   input rst_i;
   input [31:0] data_i;
   output [31:0] data_o;
   input [31:0]  addr_i;
   input 	 strobe_i;
   input 	 rd_wrn_i;
   output 	 rdy_o;
   output 	 err_o;
   input [2:0] 	 word_size_i;


   input 	 wb_clk_i;
   output [31:0] wb_adr_o;
   output [31:0] wb_dat_o;
   input [31:0]  wb_dat_i;
   output 	 wb_cyc_o;
   output 	 wb_stb_o;
   output [3:0]  wb_sel_o;
   output 	 wb_we_o;
   input 	 wb_ack_i;
   output 	 wb_cab_o;
   input 	 wb_err_i;
   output [2:0]  wb_cti_o;
   output [1:0]  wb_bte_o;

   wire [31:0] 	 data_o;
   reg 		 rdy_o;
   wire 	 err_o;

   wire [31:0] 	 wb_adr_o;
   reg 		 wb_cyc_o;
   reg 		 wb_stb_o;
   wire [31:0] 	 wb_dat_o;
   wire [3:0] 	 wb_sel_o;
   wire 	 wb_we_o;
   wire 	 wb_cab_o;
   wire [2:0] 	 wb_cti_o;
   wire [1:0] 	 wb_bte_o;



   reg [3:0] 	 sel_reg;
   reg [31:0] 	 addr_reg;
   reg [31:0] 	 data_in_reg;
   reg [31:0] 	 data_out_reg;
   reg 		 wr_reg;
   reg 		 str_sync;
   reg 		 rdy_sync;
   reg 		 err_reg;


   reg 		 rdy_sync_tff1;
   reg 		 rdy_sync_tff2;
   reg 		 rdy_sync_tff2q;
   reg 		 str_sync_wbff1;
   reg 		 str_sync_wbff2;
   reg 		 str_sync_wbff2q;



   reg 		 data_o_en;
   reg 		 rdy_sync_en;
   reg 		 err_en;


   reg [3:0] 	 be_dec;
   wire 	 start_toggle;
   reg [31:0] 	 swapped_data_i;
   reg [31:0] 	 swapped_data_out;







 `ifdef DBG_WB_LITTLE_ENDIAN


   always @ (word_size_i or addr_i)
     begin
	case (word_size_i)
	  3'h1:
            begin
               if(addr_i[1:0] == 2'b00) be_dec <= 4'b0001;
               else if(addr_i[1:0] == 2'b01) be_dec <= 4'b0010;
               else if(addr_i[1:0] == 2'b10) be_dec <= 4'b0100;
               else be_dec <= 4'b1000;
            end
	  3'h2:
            begin
               if(addr_i[1]) be_dec <= 4'b1100;
               else          be_dec <= 4'b0011;
            end
	  3'h4: be_dec <= 4'b1111;
	  default: be_dec <= 4'b1111;
	endcase 
     end
 `else


   always @ (word_size_i or addr_i)
     begin
	case (word_size_i)
	  3'h1:
            begin
               if(addr_i[1:0] == 2'b00) be_dec <= 4'b1000;
               else if(addr_i[1:0] == 2'b01) be_dec <= 4'b0100;
               else if(addr_i[1:0] == 2'b10) be_dec <= 4'b0010;
               else be_dec <= 4'b0001;
            end
	  3'h2:
            begin
               if(addr_i[1] == 1'b1) be_dec <= 4'b0011;
               else                  be_dec <= 4'b1100;
            end
	  3'h4: be_dec <= 4'b1111;
	  default: be_dec <= 4'b1111;
	endcase
     end
 `endif






   always @ (be_dec or data_i)
     begin
	case (be_dec)
	  4'b1111: swapped_data_i <= data_i;
	  4'b0011: swapped_data_i <= {16'h0,data_i[31:16]};
	  4'b1100: swapped_data_i <= data_i;
	  4'b0001: swapped_data_i <= {24'h0, data_i[31:24]};
	  4'b0010: swapped_data_i <= {16'h0, data_i[31:24], 8'h0};
	  4'b0100: swapped_data_i <= {8'h0, data_i[31:24], 16'h0};
	  4'b1000: swapped_data_i <= {data_i[31:24], 24'h0};
	  default: swapped_data_i <= data_i;
	endcase
     end


   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) begin
	   sel_reg <= 4'h0;
	   addr_reg <= 32'h0;
	   data_in_reg <= 32'h0;
	   wr_reg <= 1'b0;
	end
	else
	  if(strobe_i && rdy_o) begin
	     sel_reg <= be_dec;
	     addr_reg <= addr_i;
	     if(!rd_wrn_i) data_in_reg <= swapped_data_i;
	     wr_reg <= ~rd_wrn_i;
	  end 
     end



   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) str_sync <= 1'b0;
	else if(strobe_i && rdy_o) str_sync <= ~str_sync;
     end 


   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) begin
           rdy_sync_tff1 <= 1'b0;
           rdy_sync_tff2 <= 1'b0;
           rdy_sync_tff2q <= 1'b0;
           rdy_o <= 1'b1; 
	end
	else begin  
	   rdy_sync_tff1 <= rdy_sync;
	   rdy_sync_tff2 <= rdy_sync_tff1;
	   rdy_sync_tff2q <= rdy_sync_tff2;

	   if(strobe_i && rdy_o) rdy_o <= 1'b0;
	   else if(rdy_sync_tff2 != rdy_sync_tff2q) rdy_o <= 1'b1;
	end

     end 




   assign wb_dat_o = data_in_reg;
   assign wb_we_o = wr_reg;
   assign wb_adr_o = addr_reg;
   assign wb_sel_o = sel_reg;

   assign data_o = data_out_reg;
   assign err_o = err_reg;

   assign wb_cti_o = 3'h0;
   assign wb_bte_o = 2'h0;
   assign wb_cab_o = 1'b0;





    always @ (posedge wb_clk_i or posedge rst_i)
	  begin
	     if(rst_i) begin
		str_sync_wbff1 <= 1'b0;
		str_sync_wbff2 <= 1'b0;
		str_sync_wbff2q <= 1'b0;      
	     end
	     else begin
		str_sync_wbff1 <= str_sync;
		str_sync_wbff2 <= str_sync_wbff1;
		str_sync_wbff2q <= str_sync_wbff2;
	     end
	  end

   assign start_toggle = (str_sync_wbff2 != str_sync_wbff2q);


   always @ (posedge wb_clk_i or posedge rst_i)
     begin
	if(rst_i) err_reg <= 1'b0;
	else if(err_en) err_reg <= wb_err_i; 
     end




   always @ (sel_reg or wb_dat_i)
     begin
	case (sel_reg)
	  4'b1111: swapped_data_out <= wb_dat_i;
	  4'b0011: swapped_data_out <= wb_dat_i;
	  4'b1100: swapped_data_out <= {16'h0, wb_dat_i[31:16]};
	  4'b0001: swapped_data_out <= wb_dat_i;
	  4'b0010: swapped_data_out <= {24'h0, wb_dat_i[15:8]};
	  4'b0100: swapped_data_out <= {16'h0, wb_dat_i[31:16]};
	  4'b1000: swapped_data_out <= {24'h0, wb_dat_i[31:24]};
	  default: swapped_data_out <= wb_dat_i;
	endcase
     end


   always @ (posedge wb_clk_i or posedge rst_i)
     begin
	if(rst_i) data_out_reg <= 32'h0;
	else if(data_o_en) data_out_reg <= swapped_data_out;
     end


   always @ (posedge wb_clk_i or posedge rst_i)
     begin
	if(rst_i) rdy_sync <= 1'b0;
	else if(rdy_sync_en) rdy_sync <= ~rdy_sync;
     end 







   reg wb_fsm_state;
   reg next_fsm_state;

`define STATE_IDLE     1'h0
`define STATE_TRANSFER 1'h1


   always @ (posedge wb_clk_i or posedge rst_i)
     begin
	if(rst_i) wb_fsm_state <= `STATE_IDLE;
	else wb_fsm_state <= next_fsm_state; 
     end


   always @ (wb_fsm_state or start_toggle or wb_ack_i or wb_err_i)
     begin
	case (wb_fsm_state)
          `STATE_IDLE:
            begin
               if(start_toggle && !(wb_ack_i || wb_err_i)) next_fsm_state <= `STATE_TRANSFER;
               else next_fsm_state <= `STATE_IDLE;
            end
          `STATE_TRANSFER:
            begin
               if(wb_ack_i || wb_err_i) next_fsm_state <= `STATE_IDLE;
               else next_fsm_state <= `STATE_TRANSFER;
            end
	endcase
     end


   always @ (wb_fsm_state or start_toggle or wb_ack_i or wb_err_i or wr_reg)
     begin
	rdy_sync_en <= 1'b0;
	err_en <= 1'b0;
	data_o_en <= 1'b0;
	wb_cyc_o <= 1'b0;
	wb_stb_o <= 1'b0;
	
	case (wb_fsm_state)
          `STATE_IDLE:
            begin
               if(start_toggle) begin
		  wb_cyc_o <= 1'b1;
		  wb_stb_o <= 1'b1;
		  if(wb_ack_i || wb_err_i) begin
                     err_en <= 1'b1;
                     rdy_sync_en <= 1'b1;
		  end
		  
		  if (wb_ack_i && !wr_reg) begin
                     data_o_en <= 1'b1;
		  end
               end
            end

          `STATE_TRANSFER:
            begin
               wb_cyc_o <= 1'b1;
               wb_stb_o <= 1'b1;
               if(wb_ack_i) begin
                  err_en <= 1'b1;
                  data_o_en <= 1'b1;
                  rdy_sync_en <= 1'b1;
               end
               else if (wb_err_i) begin
                  err_en <= 1'b1;
                  rdy_sync_en <= 1'b1;
               end
            end
	endcase

     end

endmodule
module adbg_wb_biu
  (

   tck_i,
   rst_i,
   data_i,
   data_o,
   addr_i,
   strobe_i,
   rd_wrn_i,
   rdy_o,
   err_o,
   word_size_i,


   wb_clk_i,
   wb_adr_o,
   wb_dat_o,
   wb_dat_i,
   wb_cyc_o,
   wb_stb_o,
   wb_sel_o,
   wb_we_o,
   wb_ack_i,
   wb_cab_o,
   wb_err_i,
   wb_cti_o,
   wb_bte_o
   );



   input tck_i;
   input rst_i;
   input [31:0] data_i;
   output [31:0] data_o;
   input [31:0]  addr_i;
   input 	 strobe_i;
   input 	 rd_wrn_i;
   output 	 rdy_o;
   output 	 err_o;
   input [2:0] 	 word_size_i;


   input 	 wb_clk_i;
   output [31:0] wb_adr_o;
   output [31:0] wb_dat_o;
   input [31:0]  wb_dat_i;
   output 	 wb_cyc_o;
   output 	 wb_stb_o;
   output [3:0]  wb_sel_o;
   output 	 wb_we_o;
   input 	 wb_ack_i;
   output 	 wb_cab_o;
   input 	 wb_err_i;
   output [2:0]  wb_cti_o;
   output [1:0]  wb_bte_o;

   wire [31:0] 	 data_o;
   reg 		 rdy_o;
   wire 	 err_o;

   wire [31:0] 	 wb_adr_o;
   reg 		 wb_cyc_o;
   reg 		 wb_stb_o;
   wire [31:0] 	 wb_dat_o;
   wire [3:0] 	 wb_sel_o;
   wire 	 wb_we_o;
   wire 	 wb_cab_o;
   wire [2:0] 	 wb_cti_o;
   wire [1:0] 	 wb_bte_o;



   reg [3:0] 	 sel_reg;
   reg [31:0] 	 addr_reg;
   reg [31:0] 	 data_in_reg;
   reg [31:0] 	 data_out_reg;
   reg 		 wr_reg;
   reg 		 str_sync;
   reg 		 rdy_sync;
   reg 		 err_reg;


   reg 		 rdy_sync_tff1;
   reg 		 rdy_sync_tff2;
   reg 		 rdy_sync_tff2q;
   reg 		 str_sync_wbff1;
   reg 		 str_sync_wbff2;
   reg 		 str_sync_wbff2q;



   reg 		 data_o_en;
   reg 		 rdy_sync_en;
   reg 		 err_en;


   reg [3:0] 	 be_dec;
   wire 	 start_toggle;
   reg [31:0] 	 swapped_data_i;
   reg [31:0] 	 swapped_data_out;







 `ifdef DBG_WB_LITTLE_ENDIAN


   always @ (word_size_i or addr_i)
     begin
	case (word_size_i)
	  3'h1:
            begin
               if(addr_i[1:0] == 2'b00) be_dec <= 4'b0001;
               else if(addr_i[1:0] == 2'b01) be_dec <= 4'b0010;
               else if(addr_i[1:0] == 2'b10) be_dec <= 4'b0100;
               else be_dec <= 4'b1000;
            end
	  3'h2:
            begin
               if(addr_i[1]) be_dec <= 4'b1100;
               else          be_dec <= 4'b0011;
            end
	  3'h4: be_dec <= 4'b1111;
	  default: be_dec <= 4'b1111;
	endcase 
     end
 `else


   always @ (word_size_i or addr_i)
     begin
	case (word_size_i)
	  3'h1:
            begin
               if(addr_i[1:0] == 2'b00) be_dec <= 4'b1000;
               else if(addr_i[1:0] == 2'b01) be_dec <= 4'b0100;
               else if(addr_i[1:0] == 2'b10) be_dec <= 4'b0010;
               else be_dec <= 4'b0001;
            end
	  3'h2:
            begin
               if(addr_i[1] == 1'b1) be_dec <= 4'b0011;
               else                  be_dec <= 4'b1100;
            end
	  3'h4: be_dec <= 4'b1111;
	  default: be_dec <= 4'b1111;
	endcase
     end
 `endif






   always @ (be_dec or data_i)
     begin
	case (be_dec)
	  4'b1111: swapped_data_i <= data_i;
	  4'b0011: swapped_data_i <= {16'h0,data_i[31:16]};
	  4'b1100: swapped_data_i <= data_i;
	  4'b0001: swapped_data_i <= {24'h0, data_i[31:24]};
	  4'b0010: swapped_data_i <= {16'h0, data_i[31:24], 8'h0};
	  4'b0100: swapped_data_i <= {8'h0, data_i[31:24], 16'h0};
	  4'b1000: swapped_data_i <= {data_i[31:24], 24'h0};
	  default: swapped_data_i <= data_i;
	endcase
     end


   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) begin
	   sel_reg <= 4'h0;
	   addr_reg <= 32'h0;
	   data_in_reg <= 32'h0;
	   wr_reg <= 1'b0;
	end
	else
	  if(strobe_i && rdy_o) begin
	     sel_reg <= be_dec;
	     addr_reg <= addr_i;
	     if(!rd_wrn_i) data_in_reg <= swapped_data_i;
	     wr_reg <= ~rd_wrn_i;
	  end 
     end



   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) str_sync <= 1'b0;
	else if(strobe_i && rdy_o) str_sync <= ~str_sync;
     end 


   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) begin
           rdy_sync_tff1 <= 1'b0;
           rdy_sync_tff2 <= 1'b0;
           rdy_sync_tff2q <= 1'b0;
           rdy_o <= 1'b1; 
	end
	else begin  
	   rdy_sync_tff1 <= rdy_sync;
	   rdy_sync_tff2 <= rdy_sync_tff1;
	   rdy_sync_tff2q <= rdy_sync_tff2;

	   if(strobe_i && rdy_o) rdy_o <= 1'b0;
	   else if(rdy_sync_tff2 != rdy_sync_tff2q) rdy_o <= 1'b1;
	end

     end 




   assign wb_dat_o = data_in_reg;
   assign wb_we_o = wr_reg;
   assign wb_adr_o = addr_reg;
   assign wb_sel_o = sel_reg;

   assign data_o = data_out_reg;
   assign err_o = err_reg;

   assign wb_cti_o = 3'h0;
   assign wb_bte_o = 2'h0;
   assign wb_cab_o = 1'b0;





    always @ (posedge wb_clk_i or posedge rst_i)
	  begin
	     if(rst_i) begin
		str_sync_wbff1 <= 1'b0;
		str_sync_wbff2 <= 1'b0;
		str_sync_wbff2q <= 1'b0;      
	     end
	     else begin
		str_sync_wbff1 <= str_sync;
		str_sync_wbff2 <= str_sync_wbff1;
		str_sync_wbff2q <= str_sync_wbff2;
	     end
	  end

   assign start_toggle = (str_sync_wbff2 != str_sync_wbff2q);


   always @ (posedge wb_clk_i or posedge rst_i)
     begin
	if(rst_i) err_reg <= 1'b0;
	else if(err_en) err_reg <= wb_err_i; 
     end




   always @ (sel_reg or wb_dat_i)
     begin
	case (sel_reg)
	  4'b1111: swapped_data_out <= wb_dat_i;
	  4'b0011: swapped_data_out <= wb_dat_i;
	  4'b1100: swapped_data_out <= {16'h0, wb_dat_i[31:16]};
	  4'b0001: swapped_data_out <= wb_dat_i;
	  4'b0010: swapped_data_out <= {24'h0, wb_dat_i[15:8]};
	  4'b0100: swapped_data_out <= {16'h0, wb_dat_i[31:16]};
	  4'b1000: swapped_data_out <= {24'h0, wb_dat_i[31:24]};
	  default: swapped_data_out <= wb_dat_i;
	endcase
     end


   always @ (posedge wb_clk_i or posedge rst_i)
     begin
	if(rst_i) data_out_reg <= 32'h0;
	else if(data_o_en) data_out_reg <= swapped_data_out;
     end


   always @ (posedge wb_clk_i or posedge rst_i)
     begin
	if(rst_i) rdy_sync <= 1'b0;
	else if(rdy_sync_en) rdy_sync <= ~rdy_sync;
     end 







   reg wb_fsm_state;
   reg next_fsm_state;

`define STATE_IDLE     1'h0
`define STATE_TRANSFER 1'h1


   always @ (posedge wb_clk_i or posedge rst_i)
     begin
	if(rst_i) wb_fsm_state <= `STATE_IDLE;
	else wb_fsm_state <= next_fsm_state; 
     end


   always @ (wb_fsm_state or start_toggle or wb_ack_i or wb_err_i)
     begin
	case (wb_fsm_state)
          `STATE_IDLE:
            begin
               if(start_toggle && !(wb_ack_i || wb_err_i)) next_fsm_state <= `STATE_TRANSFER;
               else next_fsm_state <= `STATE_IDLE;
            end
          `STATE_TRANSFER:
            begin
               if(wb_ack_i || wb_err_i) next_fsm_state <= `STATE_IDLE;
               else next_fsm_state <= `STATE_TRANSFER;
            end
	endcase
     end


   always @ (wb_fsm_state or start_toggle or wb_ack_i or wb_err_i or wr_reg)
     begin
	rdy_sync_en <= 1'b0;
	err_en <= 1'b0;
	data_o_en <= 1'b0;
	wb_cyc_o <= 1'b0;
	wb_stb_o <= 1'b0;
	
	case (wb_fsm_state)
          `STATE_IDLE:
            begin
               if(start_toggle) begin
		  wb_cyc_o <= 1'b1;
		  wb_stb_o <= 1'b1;
		  if(wb_ack_i || wb_err_i) begin
                     err_en <= 1'b1;
                     rdy_sync_en <= 1'b1;
		  end
		  
		  if (wb_ack_i && !wr_reg) begin
                     data_o_en <= 1'b1;
		  end
               end
            end

          `STATE_TRANSFER:
            begin
               wb_cyc_o <= 1'b1;
               wb_stb_o <= 1'b1;
               if(wb_ack_i) begin
                  err_en <= 1'b1;
                  data_o_en <= 1'b1;
                  rdy_sync_en <= 1'b1;
               end
               else if (wb_err_i) begin
                  err_en <= 1'b1;
                  rdy_sync_en <= 1'b1;
               end
            end
	endcase

     end

endmodule