data/full_repos/permissive/14432793/OLD/I2C/test/test.v
 line:49: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #40\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #22\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #2\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/test/test.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #400\n    ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

reg clk, sda;
wire out;

test u1 (clk, sda, out);

always
  begin
    #5 clk = ~clk;
  end

initial
  begin
    clk = 0;
    sda = 1;
    #40
    sda = 0;
    #22
    sda = 1;
    #4
    sda = 0;
    #2
    sda = 1;
    #400
    
    
    $finish;
  end

endmodule
module testbench();


reg clk, sda;
wire out;

test u1 (clk, sda, out);

always
  begin
    #5 clk = ~clk;
  end

initial
  begin
    clk = 0;
    sda = 1;
    #40
    sda = 0;
    #22
    sda = 1;
    #4
    sda = 0;
    #2
    sda = 1;
    #400
    
    
    $finish;
  end

endmodule