data/full_repos/permissive/143278/ivltests/pr2991457b.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2991457b.v:14: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                          : ... In instance main\n      tmp = \'hx;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2991457b.v:15: Operator NEQCASE expects 32 bits on the LHS, but LHS\'s VARREF \'tmp\' generates 4 bits.\n                                                                          : ... In instance main\n      if (tmp !== \'hx) begin\n              ^~~\n%Error: Exiting due to 2 warning(s)\n'
module main;

   reg [3:0] tmp;

   initial begin
      tmp = 'hx;
      if (tmp !== 'hx) begin
	 $display("PASSED");
	 $finish;
      end
      $display("FAILED");
   end

endmodule
module main;


   reg [3:0] tmp;

   initial begin
      tmp = 'hx;
      if (tmp !== 'hx) begin
	 $display("PASSED");
	 $finish;
      end
      $display("FAILED");
   end

endmodule