data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source/flight_mode.v
 line:117: before: "reg"
1: b'%Error: data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source/flight_mode.v:16: Cannot find include file: common_defines.v\n`include "common_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source,data/full_repos/permissive/114714167/common_defines.v\n             data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source,data/full_repos/permissive/114714167/common_defines.v.v\n             data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source,data/full_repos/permissive/114714167/common_defines.v.sv\n             common_defines.v\n             common_defines.v.v\n             common_defines.v.sv\n             obj_dir/common_defines.v\n             obj_dir/common_defines.v.v\n             obj_dir/common_defines.v.sv\n%Error: data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source/flight_mode.v:21: Define or directive not defined: \'`REC_VAL_BIT_WIDTH\'\n input  wire [`REC_VAL_BIT_WIDTH-1:0] swa_swb_val,\n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source/flight_mode.v:27: Define or directive not defined: \'`REC_VAL_BIT_WIDTH\'\n  input reg [`REC_VAL_BIT_WIDTH-1:0]value;\n             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source/flight_mode.v:28: Define or directive not defined: \'`REC_VAL_BIT_WIDTH\'\n  input reg [`REC_VAL_BIT_WIDTH-1:0]lower_lim;\n             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source/flight_mode.v:29: Define or directive not defined: \'`REC_VAL_BIT_WIDTH\'\n  input reg [`REC_VAL_BIT_WIDTH-1:0]upper_lim;\n             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source/flight_mode.v:41: Define or directive not defined: \'`TRUE\'\n   case(`TRUE)\n        ^~~~~\n%Error: data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source/flight_mode.v:41: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   case(`TRUE)\n             ^\n%Error: data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source/flight_mode.v:43: syntax error, unexpected \':\'\n    in_range(swa_swb_val, 8\'d50,  8\'d99 ): begin switch_a <= 3\'b100; switch_b <= 2\'b10; end  \n                                         ^\n%Error: data/full_repos/permissive/114714167/Source-Code/Drone2/impl1/source/flight_mode.v:44: syntax error, unexpected \'(\', expecting IDENTIFIER\n    in_range(swa_swb_val, 8\'d100, 8\'d149): begin switch_a <= 3\'b001; switch_b <= 2\'b11; end  \n             ^~~~~~~~~~~\n%Error: Cannot continue\n'
module flight_mode (
	output reg  [2:0] switch_a,
	output reg  [1:0] switch_b,
	input  wire [`REC_VAL_BIT_WIDTH-1:0] swa_swb_val,
	input  wire resetn,
	input  wire us_clk
	);
	
	function automatic reg in_range;
		input reg [`REC_VAL_BIT_WIDTH-1:0]value;
		input reg [`REC_VAL_BIT_WIDTH-1:0]lower_lim;
		input reg [`REC_VAL_BIT_WIDTH-1:0]upper_lim;
		if ( (value >= lower_lim) && (value <= upper_lim) )
			in_range = 1'b1;
		else
			in_range = 1'b0;
	endfunction
	
	always@(posedge us_clk, negedge resetn) begin
		if(~resetn) begin
			switch_a <= 3'b000; switch_b <= 2'b00; 
		end
		else begin
			case(`TRUE)
				in_range(swa_swb_val, 8'd0,   8'd49 ): begin switch_a <= 3'b100; switch_b <= 2'b01; end
				in_range(swa_swb_val, 8'd50,  8'd99 ): begin switch_a <= 3'b100; switch_b <= 2'b10; end
				in_range(swa_swb_val, 8'd100, 8'd149): begin switch_a <= 3'b001; switch_b <= 2'b11; end
				in_range(swa_swb_val, 8'd150, 8'd199): begin switch_a <= 3'b010; switch_b <= 2'b10; end
				in_range(swa_swb_val, 8'd200, 8'd250): begin switch_a <= 3'b010; switch_b <= 2'b01; end
				default :                              begin switch_a <= 3'b000; switch_b <= 2'b00; end
			endcase
		end
	end
	
endmodule
module flight_mode (
	output reg  [2:0] switch_a,
	output reg  [1:0] switch_b,
	input  wire [`REC_VAL_BIT_WIDTH-1:0] swa_swb_val,
	input  wire resetn,
	input  wire us_clk
	);

	
	function automatic reg in_range;
		input reg [`REC_VAL_BIT_WIDTH-1:0]value;
		input reg [`REC_VAL_BIT_WIDTH-1:0]lower_lim;
		input reg [`REC_VAL_BIT_WIDTH-1:0]upper_lim;
		if ( (value >= lower_lim) && (value <= upper_lim) )
			in_range = 1'b1;
		else
			in_range = 1'b0;
	endfunction
	
	always@(posedge us_clk, negedge resetn) begin
		if(~resetn) begin
			switch_a <= 3'b000; switch_b <= 2'b00; 
		end
		else begin
			case(`TRUE)
				in_range(swa_swb_val, 8'd0,   8'd49 ): begin switch_a <= 3'b100; switch_b <= 2'b01; end
				in_range(swa_swb_val, 8'd50,  8'd99 ): begin switch_a <= 3'b100; switch_b <= 2'b10; end
				in_range(swa_swb_val, 8'd100, 8'd149): begin switch_a <= 3'b001; switch_b <= 2'b11; end
				in_range(swa_swb_val, 8'd150, 8'd199): begin switch_a <= 3'b010; switch_b <= 2'b10; end
				in_range(swa_swb_val, 8'd200, 8'd250): begin switch_a <= 3'b010; switch_b <= 2'b01; end
				default :                              begin switch_a <= 3'b000; switch_b <= 2'b00; end
			endcase
		end
	end
	
endmodule