data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v
1: b'%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:43: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                             : ... In instance salsaengine\n reg [5:0] mcount = 5\'d0;  \n                    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:110: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram1_blk (ram_addr, ram_clk, ram1_din, ram_wren, ram1_dout);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/11584509/experimental/LX150-SPLIT,data/full_repos/permissive/11584509/ram\n             data/full_repos/permissive/11584509/experimental/LX150-SPLIT,data/full_repos/permissive/11584509/ram.v\n             data/full_repos/permissive/11584509/experimental/LX150-SPLIT,data/full_repos/permissive/11584509/ram.sv\n             ram\n             ram.v\n             ram.sv\n             obj_dir/ram\n             obj_dir/ram.v\n             obj_dir/ram.sv\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:111: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram2_blk (ram_addr, ram_clk, ram2_din, ram_wren, ram2_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:112: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram3_blk (ram_addr, ram_clk, ram3_din, ram_wren, ram3_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:113: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram4_blk (ram_addr, ram_clk, ram4_din, ram_wren, ram4_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-SPLIT/salsaengine.v:119: Cannot find file containing module: \'salsa\'\n salsa salsa_blk (hash_clk, mixfeedback, X0, X1, Xmix);\n ^~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result );

	input hash_clk, reset, din, shift, start;
	output reg busy = 1'b0;
	output reg result = 1'b0;
	output dout;

	parameter XSnull = 0, XSload = 1, XSmix = 2, XSram = 4;
	reg [2:0] XCtl = XSnull;
	


	parameter R_IDLE=0, R_START=1, R_WRITE=2, R_MIX=4, R_INT=8;
	reg [3:0] mstate = R_IDLE;
	reg [10:0] cycle = 11'd0;
	reg [5:0] mcount = 5'd0;
	reg doneROM = 1'd0;
	reg mixfeedback = 1'b0;
	reg addrsourceMix = 1'b0;
	reg addrsourceSave = 1'b0;
	reg xoren = 1'b1;
	reg	 [1:0] intcycles = 2'b0;

	wire [511:0] Xmix;
	reg [511:0] X0;
	reg [511:0] X1;
	wire [511:0] X0in;
	wire [511:0] X1in;
	reg [1023:0] salsaShiftReg;
	assign dout = salsaShiftReg[1023];




	wire [1023:0] X;
	`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
	genvar i;
	generate
	for (i = 0; i < 32; i = i + 1) begin : Xrewire
		wire [31:0] tmp;
		assign tmp = salsaShiftReg[`IDX(i)];
		assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
	end
	endgenerate


	reg [9:0] writeaddr = 10'd0;
	



	
	`ifdef HALFRAM
		parameter ADDRBITS = 9;
	`else
		parameter ADDRBITS = 10;
	`endif

	wire [ADDRBITS-1:0]ram_addr;
	wire [255:0]ram1_din;
	wire [255:0]ram1_dout;
	wire [255:0]ram2_din;
	wire [255:0]ram2_dout;
	wire [255:0]ram3_din;
	wire [255:0]ram3_dout;
	wire [255:0]ram4_din;
	wire [255:0]ram4_dout;
	wire [1023:0]ramout;

	reg ram_wren = 1'b0;
	wire ram_clk;
	assign ram_clk = hash_clk;
	
	`ifdef HALFRAM


		wire [8:0] adj_addr = (Xmix[9:1] == 9'h1ff) ? 9'h1fe : Xmix[9:1];
		assign ram_addr = addrsourceMix ? (addrsourceSave ? 9'h1ff : adj_addr) : writeaddr[9:1];
	`else

		assign ram_addr = addrsourceMix ? Xmix[9:0] : writeaddr;
	`endif
	ram # (.ADDRBITS(ADDRBITS)) ram1_blk (ram_addr, ram_clk, ram1_din, ram_wren, ram1_dout);
	ram # (.ADDRBITS(ADDRBITS)) ram2_blk (ram_addr, ram_clk, ram2_din, ram_wren, ram2_dout);
	ram # (.ADDRBITS(ADDRBITS)) ram3_blk (ram_addr, ram_clk, ram3_din, ram_wren, ram3_dout);
	ram # (.ADDRBITS(ADDRBITS)) ram4_blk (ram_addr, ram_clk, ram4_din, ram_wren, ram4_dout);
	assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout };
	assign { ram4_din, ram3_din, ram2_din, ram1_din } = { X1, X0} ;


	
	salsa salsa_blk (hash_clk, mixfeedback, X0, X1, Xmix);


	wire [511:0] Zbits;
	assign Zbits = {512{xoren}};
	

	assign X0in = (XCtl==XSmix) ? X1 : (XCtl==XSram) ? (X0 & Zbits) ^ ramout[511:0] : (XCtl==XSload) ? X[511:0] : X0;
	assign X1in = (XCtl==XSmix) ? Xmix : (XCtl==XSram) ? (X1 & Zbits) ^ ramout[1023:512] : (XCtl==XSload) ? X[1023:512] : X1;
	

	
	always @ (posedge hash_clk)
	begin
		X0 <= X0in;
		X1 <= X1in;
		
		XCtl <= XSnull;
		addrsourceSave <= 0;
		ram_wren <= 0;
		xoren <= 1;
		
		if (shift)
			salsaShiftReg <= { salsaShiftReg[1022:0], din };
		
		if (reset == 1'b1)
		begin
			mstate <= R_IDLE;
			result <= 1'b0;
		end
		else
		begin
			case (mstate)
				R_IDLE: begin
					writeaddr <= 0;
					mcount <= 0;
					mixfeedback <= 1'b0;
					addrsourceMix <= 1'b0;
					if (start)
					begin
						if (~result)
							XCtl <= XSload;
						doneROM <= 1'b0;
						busy <= 1'b1;
						result <= 1'b0;
						mstate <= R_START;
					end
				end
				R_START: begin
						ram_wren <= 1'b1;
						mstate <= R_WRITE;
					end
				R_WRITE: begin
					mcount <= mcount + 6'd1;





					if (mcount==0)
					begin
						mixfeedback <= 1'b1;
						if (writeaddr==1023)
							doneROM <= 1'b1;
						writeaddr <= writeaddr + 10'd1;
					end
					if (mcount==4)
						mixfeedback <= 1'b1;
					if (mcount == 2 || mcount == 6)
						XCtl <= XSmix;							
					if (mcount == 3 || mcount == 7)
						mixfeedback <= 1'b0;
					if (mcount == 6 && doneROM)
						addrsourceMix <= 1'b1;
					if (mcount == 7)
					begin
						mcount <= 0;
						if (doneROM)
						begin
							cycle <= 0;
							mstate <= R_MIX;
							XCtl <= XSram;
							`ifdef HALFRAM

							intcycles <= { 1'b0, Xmix[0] };
							if ( Xmix[9:1] == 9'h1ff )
								intcycles <= { 1'b1, Xmix[0] };

							if ( (Xmix[9:1] == 9'h1ff) || Xmix[0])
							begin
								addrsourceSave <= 1'b1;
								ram_wren <= 1'b1;
								xoren <= 0;
							end
							`endif
						end
						else
						begin

							`ifdef HALFRAM
								if (!writeaddr[0])
									ram_wren <= 1'b1;
							`else
									ram_wren <= 1'b1;
							`endif
						end
					end
				end
				R_MIX: begin




					mcount <= mcount + 5'd1;
					if (mcount == 0)
					begin
						mixfeedback <= 1'b0;
						`ifdef HALFRAM
							if (intcycles != 0)
								mstate <= R_INT;
						`endif
					end
					if (mcount==1 || mcount==5)
						mixfeedback <= 1;
					if (mcount == 3 || mcount == 7)
						XCtl <= XSmix;
					if (mcount == 4 || mcount == 8)
						mixfeedback <= 1'b0;
					if (mcount == 7 && cycle == 1023)
							XCtl <= XSload;
					if (mcount == 8)
					begin
						mcount <= 0;
						cycle <= cycle + 11'd1;
						if (cycle == 1023)
						begin

							salsaShiftReg <= { Xmix, X1 };

							result <= 1'b1;
							busy <= 1'b0;
							mstate <= R_IDLE;
						end
						else
						begin
							XCtl <= XSram;
							`ifdef HALFRAM

							intcycles <= { 1'b0, Xmix[0] };
							if ( Xmix[9:1] == 9'h1ff )
								intcycles <= { 1'b1, Xmix[0] };

							if ( (Xmix[9:1] == 9'h1ff) || Xmix[0])
							begin
								addrsourceSave <= 1'b1;
								ram_wren <= 1'b1;
								xoren <= 0;
							end
							`endif
						end
					end
				end
				`ifdef HALFRAM
				R_INT: begin


					mcount <= mcount + 6'd1;
					if (mcount==1 || mcount==5)
						mixfeedback <= 1'b1;
					if (mcount == 3 || mcount == 7)
						XCtl <= XSmix;
					if (mcount == 4 || mcount == 8)
						mixfeedback <= 1'b0;
					if (mcount == 7)
						addrsourceSave <= 1'b1;
					if (mcount == 8)
					begin
						if (intcycles == 1)
							XCtl <= XSram;
					end
					if (mcount == 9)
					begin
						intcycles <= intcycles - 1;
						mcount <= 1;
						if (intcycles == 1)
							mstate <= R_MIX;

					end
				end
				`endif
			endcase
		end
`ifdef SIM

	if (mstate == R_MIX && mcount == 8)
		$display ("cycle %d Xmix %08x\n", cycle, Xmix[511:480]);
`endif
	end
endmodule
module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result );


	input hash_clk, reset, din, shift, start;
	output reg busy = 1'b0;
	output reg result = 1'b0;
	output dout;

	parameter XSnull = 0, XSload = 1, XSmix = 2, XSram = 4;
	reg [2:0] XCtl = XSnull;
	


	parameter R_IDLE=0, R_START=1, R_WRITE=2, R_MIX=4, R_INT=8;
	reg [3:0] mstate = R_IDLE;
	reg [10:0] cycle = 11'd0;
	reg [5:0] mcount = 5'd0;
	reg doneROM = 1'd0;
	reg mixfeedback = 1'b0;
	reg addrsourceMix = 1'b0;
	reg addrsourceSave = 1'b0;
	reg xoren = 1'b1;
	reg	 [1:0] intcycles = 2'b0;

	wire [511:0] Xmix;
	reg [511:0] X0;
	reg [511:0] X1;
	wire [511:0] X0in;
	wire [511:0] X1in;
	reg [1023:0] salsaShiftReg;
	assign dout = salsaShiftReg[1023];




	wire [1023:0] X;
	`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
	genvar i;
	generate
	for (i = 0; i < 32; i = i + 1) begin : Xrewire
		wire [31:0] tmp;
		assign tmp = salsaShiftReg[`IDX(i)];
		assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
	end
	endgenerate


	reg [9:0] writeaddr = 10'd0;
	



	
	`ifdef HALFRAM
		parameter ADDRBITS = 9;
	`else
		parameter ADDRBITS = 10;
	`endif

	wire [ADDRBITS-1:0]ram_addr;
	wire [255:0]ram1_din;
	wire [255:0]ram1_dout;
	wire [255:0]ram2_din;
	wire [255:0]ram2_dout;
	wire [255:0]ram3_din;
	wire [255:0]ram3_dout;
	wire [255:0]ram4_din;
	wire [255:0]ram4_dout;
	wire [1023:0]ramout;

	reg ram_wren = 1'b0;
	wire ram_clk;
	assign ram_clk = hash_clk;
	
	`ifdef HALFRAM


		wire [8:0] adj_addr = (Xmix[9:1] == 9'h1ff) ? 9'h1fe : Xmix[9:1];
		assign ram_addr = addrsourceMix ? (addrsourceSave ? 9'h1ff : adj_addr) : writeaddr[9:1];
	`else

		assign ram_addr = addrsourceMix ? Xmix[9:0] : writeaddr;
	`endif
	ram # (.ADDRBITS(ADDRBITS)) ram1_blk (ram_addr, ram_clk, ram1_din, ram_wren, ram1_dout);
	ram # (.ADDRBITS(ADDRBITS)) ram2_blk (ram_addr, ram_clk, ram2_din, ram_wren, ram2_dout);
	ram # (.ADDRBITS(ADDRBITS)) ram3_blk (ram_addr, ram_clk, ram3_din, ram_wren, ram3_dout);
	ram # (.ADDRBITS(ADDRBITS)) ram4_blk (ram_addr, ram_clk, ram4_din, ram_wren, ram4_dout);
	assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout };
	assign { ram4_din, ram3_din, ram2_din, ram1_din } = { X1, X0} ;


	
	salsa salsa_blk (hash_clk, mixfeedback, X0, X1, Xmix);


	wire [511:0] Zbits;
	assign Zbits = {512{xoren}};
	

	assign X0in = (XCtl==XSmix) ? X1 : (XCtl==XSram) ? (X0 & Zbits) ^ ramout[511:0] : (XCtl==XSload) ? X[511:0] : X0;
	assign X1in = (XCtl==XSmix) ? Xmix : (XCtl==XSram) ? (X1 & Zbits) ^ ramout[1023:512] : (XCtl==XSload) ? X[1023:512] : X1;
	

	
	always @ (posedge hash_clk)
	begin
		X0 <= X0in;
		X1 <= X1in;
		
		XCtl <= XSnull;
		addrsourceSave <= 0;
		ram_wren <= 0;
		xoren <= 1;
		
		if (shift)
			salsaShiftReg <= { salsaShiftReg[1022:0], din };
		
		if (reset == 1'b1)
		begin
			mstate <= R_IDLE;
			result <= 1'b0;
		end
		else
		begin
			case (mstate)
				R_IDLE: begin
					writeaddr <= 0;
					mcount <= 0;
					mixfeedback <= 1'b0;
					addrsourceMix <= 1'b0;
					if (start)
					begin
						if (~result)
							XCtl <= XSload;
						doneROM <= 1'b0;
						busy <= 1'b1;
						result <= 1'b0;
						mstate <= R_START;
					end
				end
				R_START: begin
						ram_wren <= 1'b1;
						mstate <= R_WRITE;
					end
				R_WRITE: begin
					mcount <= mcount + 6'd1;





					if (mcount==0)
					begin
						mixfeedback <= 1'b1;
						if (writeaddr==1023)
							doneROM <= 1'b1;
						writeaddr <= writeaddr + 10'd1;
					end
					if (mcount==4)
						mixfeedback <= 1'b1;
					if (mcount == 2 || mcount == 6)
						XCtl <= XSmix;							
					if (mcount == 3 || mcount == 7)
						mixfeedback <= 1'b0;
					if (mcount == 6 && doneROM)
						addrsourceMix <= 1'b1;
					if (mcount == 7)
					begin
						mcount <= 0;
						if (doneROM)
						begin
							cycle <= 0;
							mstate <= R_MIX;
							XCtl <= XSram;
							`ifdef HALFRAM

							intcycles <= { 1'b0, Xmix[0] };
							if ( Xmix[9:1] == 9'h1ff )
								intcycles <= { 1'b1, Xmix[0] };

							if ( (Xmix[9:1] == 9'h1ff) || Xmix[0])
							begin
								addrsourceSave <= 1'b1;
								ram_wren <= 1'b1;
								xoren <= 0;
							end
							`endif
						end
						else
						begin

							`ifdef HALFRAM
								if (!writeaddr[0])
									ram_wren <= 1'b1;
							`else
									ram_wren <= 1'b1;
							`endif
						end
					end
				end
				R_MIX: begin




					mcount <= mcount + 5'd1;
					if (mcount == 0)
					begin
						mixfeedback <= 1'b0;
						`ifdef HALFRAM
							if (intcycles != 0)
								mstate <= R_INT;
						`endif
					end
					if (mcount==1 || mcount==5)
						mixfeedback <= 1;
					if (mcount == 3 || mcount == 7)
						XCtl <= XSmix;
					if (mcount == 4 || mcount == 8)
						mixfeedback <= 1'b0;
					if (mcount == 7 && cycle == 1023)
							XCtl <= XSload;
					if (mcount == 8)
					begin
						mcount <= 0;
						cycle <= cycle + 11'd1;
						if (cycle == 1023)
						begin

							salsaShiftReg <= { Xmix, X1 };

							result <= 1'b1;
							busy <= 1'b0;
							mstate <= R_IDLE;
						end
						else
						begin
							XCtl <= XSram;
							`ifdef HALFRAM

							intcycles <= { 1'b0, Xmix[0] };
							if ( Xmix[9:1] == 9'h1ff )
								intcycles <= { 1'b1, Xmix[0] };

							if ( (Xmix[9:1] == 9'h1ff) || Xmix[0])
							begin
								addrsourceSave <= 1'b1;
								ram_wren <= 1'b1;
								xoren <= 0;
							end
							`endif
						end
					end
				end
				`ifdef HALFRAM
				R_INT: begin


					mcount <= mcount + 6'd1;
					if (mcount==1 || mcount==5)
						mixfeedback <= 1'b1;
					if (mcount == 3 || mcount == 7)
						XCtl <= XSmix;
					if (mcount == 4 || mcount == 8)
						mixfeedback <= 1'b0;
					if (mcount == 7)
						addrsourceSave <= 1'b1;
					if (mcount == 8)
					begin
						if (intcycles == 1)
							XCtl <= XSram;
					end
					if (mcount == 9)
					begin
						intcycles <= intcycles - 1;
						mcount <= 1;
						if (intcycles == 1)
							mstate <= R_MIX;

					end
				end
				`endif
			endcase
		end
`ifdef SIM

	if (mstate == R_MIX && mcount == 8)
		$display ("cycle %d Xmix %08x\n", cycle, Xmix[511:480]);
`endif
	end
endmodule