data/full_repos/permissive/139213403/FPGA/tick_counter.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/tick_counter.v:30: Operator COND expects 32 or 4 bits on the Conditional True, but Conditional True\'s CONST \'1\'h1\' generates 1 bits.\n                                                                           : ... In instance tick_counter\n   counter_next = counter_reg + (tick == 1\'b1 ? 1\'b1 : 0);\n                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module tick_counter
#(
	parameter N=4
)
(
	input wire clk, reset,
	input wire tick,
	output wire [N-1:0] counter,
	output wire of
);

	reg [N-1:0] counter_reg, counter_next;
	reg of_reg, of_next;
	
	always @(posedge clk, posedge reset)
		if (reset)
			begin
				counter_reg <= 0;
				of_reg <= 0;
			end
		else
			begin
				counter_reg <= counter_next;
				of_reg <= of_next;
			end
			
	always @*
		begin
			counter_next = counter_reg + (tick == 1'b1 ? 1'b1 : 0);
			of_next = of_reg;
			if (counter_next < counter_reg)
				of_next = 1;
		end
		
	assign counter = counter_reg;
	assign of = of_reg;

endmodule
module tick_counter
#(
	parameter N=4
)
(
	input wire clk, reset,
	input wire tick,
	output wire [N-1:0] counter,
	output wire of
);


	reg [N-1:0] counter_reg, counter_next;
	reg of_reg, of_next;
	
	always @(posedge clk, posedge reset)
		if (reset)
			begin
				counter_reg <= 0;
				of_reg <= 0;
			end
		else
			begin
				counter_reg <= counter_next;
				of_reg <= of_next;
			end
			
	always @*
		begin
			counter_next = counter_reg + (tick == 1'b1 ? 1'b1 : 0);
			of_next = of_reg;
			if (counter_next < counter_reg)
				of_next = 1;
		end
		
	assign counter = counter_reg;
	assign of = of_reg;

endmodule