data/full_repos/permissive/143278/ivltests/signed9.v
 line:27: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/signed9.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("bar=%h(%0d), foo=%0d, baz = %b", bar, bar, foo, baz);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed9.v:24: Operator LTS expects 32 bits on the LHS, but LHS\'s VARREF \'bar\' generates 16 bits.\n                                                                       : ... In instance assignsigned\n   assign    baz = (bar < $signed(foo));\n                        ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module assignsigned();
   parameter foo = 10;
   reg	     signed [15:0] bar = -1;
   wire      baz;
   assign    baz = (bar < $signed(foo));

   initial begin
      #1 $display("bar=%h(%0d), foo=%0d, baz = %b", bar, bar, foo, baz);
      if (baz !== 1'b1) begin
	 $display("FAILED -- Compare returns %b instead of 1.", baz);
	 $finish;
      end
      $display("PASSED");
   end

endmodule
module assignsigned();

   parameter foo = 10;
   reg	     signed [15:0] bar = -1;
   wire      baz;
   assign    baz = (bar < $signed(foo));

   initial begin
      #1 $display("bar=%h(%0d), foo=%0d, baz = %b", bar, bar, foo, baz);
      if (baz !== 1'b1) begin
	 $display("FAILED -- Compare returns %b instead of 1.", baz);
	 $finish;
      end
      $display("PASSED");
   end

endmodule