data/full_repos/permissive/200104480/Processor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:440: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'singleBit\' generates 1 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.A.ze\n assign dataOut = 32\'b0 + singleBit;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:361: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'dataIn\' generates 16 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.ZE\n assign dataOut = 32\'b0 + dataIn;\n                        ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DataMem(input CLK,
			input WE,
			input [31:0] A,
			input [31:0] WD,
			output reg [31:0] RD);

	reg [31:0] dataMemory [0:1023];
	reg [31:0] i;
	
	initial
	begin
		for (i=0; i<1024; i=i+1)
		begin
			dataMemory[i] <= 32'b0;
		end
	end
	
	always @(A)
	begin
		RD <= dataMemory[A];
	end
	
	always @(negedge CLK)
	begin
		if (WE == 1'b1)
		begin
			dataMemory[A] <= WD;
		end
	end
	

endmodule
module DataMem(input CLK,
			input WE,
			input [31:0] A,
			input [31:0] WD,
			output reg [31:0] RD);


	reg [31:0] dataMemory [0:1023];
	reg [31:0] i;
	
	initial
	begin
		for (i=0; i<1024; i=i+1)
		begin
			dataMemory[i] <= 32'b0;
		end
	end
	
	always @(A)
	begin
		RD <= dataMemory[A];
	end
	
	always @(negedge CLK)
	begin
		if (WE == 1'b1)
		begin
			dataMemory[A] <= WD;
		end
	end
	

endmodule