data/full_repos/permissive/157494568/Part3/Part3.v
1: b"%Error: data/full_repos/permissive/157494568/Part3/Part3.v:19: Cannot find file containing module: 'clock_1hz'\nclock_1hz clock(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157494568/Part3,data/full_repos/permissive/157494568/clock_1hz\n             data/full_repos/permissive/157494568/Part3,data/full_repos/permissive/157494568/clock_1hz.v\n             data/full_repos/permissive/157494568/Part3,data/full_repos/permissive/157494568/clock_1hz.sv\n             clock_1hz\n             clock_1hz.v\n             clock_1hz.sv\n             obj_dir/clock_1hz\n             obj_dir/clock_1hz.v\n             obj_dir/clock_1hz.sv\n%Error: data/full_repos/permissive/157494568/Part3/Part3.v:37: Cannot find file containing module: 'seven_segment_display'\nseven_segment_display display(\n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Part3(HEX0, CLOCK_50, KEY, count, LEDR);

input CLOCK_50;
output [6:0] HEX0;
output reg [3:0] count;
output [10:0] LEDR;
input [1:0] KEY;

wire out_1hz;
wire [6:0] display_out;


clock_1hz clock(
	.clk(CLOCK_50), 
	.out(out_1hz)
);


initial count = 4'b0;

always @ (posedge out_1hz) begin

	if (count < 9)
		count <= count + 1;
	else
		count <= 4'b0;
	
end


seven_segment_display display(
	.in(count),
	.out(display_out)
);

assign HEX0 = display_out;
assign LEDR[0] = out_1hz;

endmodule
module Part3(HEX0, CLOCK_50, KEY, count, LEDR);


input CLOCK_50;
output [6:0] HEX0;
output reg [3:0] count;
output [10:0] LEDR;
input [1:0] KEY;

wire out_1hz;
wire [6:0] display_out;


clock_1hz clock(
	.clk(CLOCK_50), 
	.out(out_1hz)
);


initial count = 4'b0;

always @ (posedge out_1hz) begin

	if (count < 9)
		count <= count + 1;
	else
		count <= 4'b0;
	
end


seven_segment_display display(
	.in(count),
	.out(display_out)
);

assign HEX0 = display_out;
assign LEDR[0] = out_1hz;

endmodule