data/full_repos/permissive/152883307/Project/Lock.v
data/verilator_xmls/df75d19f-70cf-44a6-ba30-f1fd35eb0e06.xml
module Lock(
	input			[8:0] 	Duty,
	input					 	clk,
	output reg	[8:0]  	Fix_Duty
);

always@(negedge clk)
begin
		if(Duty<200) Fix_Duty<=200;
		else Fix_Duty<=Duty;
end
endmodule
module Lock(
	input			[8:0] 	Duty,
	input					 	clk,
	output reg	[8:0]  	Fix_Duty
);


always@(negedge clk)
begin
		if(Duty<200) Fix_Duty<=200;
		else Fix_Duty<=Duty;
end
endmodule