data/full_repos/permissive/117851934/ddr_layout_V5/SPI_Out_EN.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/e966f20c-780e-4a8c-a2b3-4f61e3256068.xml
module SPI_Out_EN
(
 input wire SPI_SYNC,   
 input wire SPI_CLK,
 input wire nReset,
 input wire SPI_MOSI,
 input wire Clock_108M,
 
 output wire SPI_Out_EN,
 output wire SPI_Out_EN2
);
parameter SPI_Command_Len = 16;
parameter Output_Delay_Clock = 27;

reg [7:0]Clock_Number;
reg [9:0]Clock_Number2; 
reg Out_enable;
reg Out_enable_Delay;
reg Write_Read_Flag;


	  always@(posedge SPI_CLK or negedge SPI_SYNC or negedge nReset)
	    begin 
		  if(!nReset)
		   begin
			 Clock_Number=0;
          Out_enable=1;
			 Write_Read_Flag=1;
			end
		  else if(!SPI_SYNC)
		   begin
			 Clock_Number=0;
          Out_enable=1;
			 Write_Read_Flag=1;
			end
		  else if(SPI_CLK)
		   begin
			 if(Clock_Number==0)Write_Read_Flag=SPI_MOSI;
		    if(Write_Read_Flag==0)
            Out_enable=1;
		    else if(Write_Read_Flag==1)
		     begin
		      if(Clock_Number<SPI_Command_Len-1)
	          Out_enable=1;
            else
				 Out_enable=0;
	         Clock_Number=Clock_Number+1'h1;
		     end
			end
      end


	 always@(posedge Clock_108M or negedge nReset)
	  begin
	   if(!nReset)
		  begin
			Clock_Number2=0;
         Out_enable_Delay=1;
		  end
		else if(Out_enable)
		 begin
		  Out_enable_Delay=1;
	     Clock_Number2=0;
		 end
		else if(!Out_enable)	
		 begin
		  if(Clock_Number2<Output_Delay_Clock+1)
		   begin
			 Out_enable_Delay=1;
			 Clock_Number2=Clock_Number2+1'h1;
			end
		  else
		   Out_enable_Delay=0;	  
		 end
	  end

	assign SPI_Out_EN2=Out_enable_Delay;
   assign SPI_Out_EN=Out_enable | Out_enable_Delay;
	
endmodule
module SPI_Out_EN
(
 input wire SPI_SYNC,   
 input wire SPI_CLK,
 input wire nReset,
 input wire SPI_MOSI,
 input wire Clock_108M,
 
 output wire SPI_Out_EN,
 output wire SPI_Out_EN2
);

parameter SPI_Command_Len = 16;
parameter Output_Delay_Clock = 27;

reg [7:0]Clock_Number;
reg [9:0]Clock_Number2; 
reg Out_enable;
reg Out_enable_Delay;
reg Write_Read_Flag;


	  always@(posedge SPI_CLK or negedge SPI_SYNC or negedge nReset)
	    begin 
		  if(!nReset)
		   begin
			 Clock_Number=0;
          Out_enable=1;
			 Write_Read_Flag=1;
			end
		  else if(!SPI_SYNC)
		   begin
			 Clock_Number=0;
          Out_enable=1;
			 Write_Read_Flag=1;
			end
		  else if(SPI_CLK)
		   begin
			 if(Clock_Number==0)Write_Read_Flag=SPI_MOSI;
		    if(Write_Read_Flag==0)
            Out_enable=1;
		    else if(Write_Read_Flag==1)
		     begin
		      if(Clock_Number<SPI_Command_Len-1)
	          Out_enable=1;
            else
				 Out_enable=0;
	         Clock_Number=Clock_Number+1'h1;
		     end
			end
      end


	 always@(posedge Clock_108M or negedge nReset)
	  begin
	   if(!nReset)
		  begin
			Clock_Number2=0;
         Out_enable_Delay=1;
		  end
		else if(Out_enable)
		 begin
		  Out_enable_Delay=1;
	     Clock_Number2=0;
		 end
		else if(!Out_enable)	
		 begin
		  if(Clock_Number2<Output_Delay_Clock+1)
		   begin
			 Out_enable_Delay=1;
			 Clock_Number2=Clock_Number2+1'h1;
			end
		  else
		   Out_enable_Delay=0;	  
		 end
	  end

	assign SPI_Out_EN2=Out_enable_Delay;
   assign SPI_Out_EN=Out_enable | Out_enable_Delay;
	
endmodule