data/full_repos/permissive/132220215/ram_module.v
data/verilator_xmls/5ada97d5-5908-4ac1-ba58-88ef77bdd162.xml
module ram_3 (
	output [7:0] data_out,
	input [7:0] data_in,
	input [9:0] addr,
	input wr,
	input cs);

 parameter addr_size = 10, word_size = 8, memory_size = 1024;





 reg [word_size-1:0] mem [memory_size-1:0];

 assign data_out = mem[addr];

 always @(wr or cs)
 begin
	 if(wr)
		 mem[addr] = data_in;
 end
endmodule
module ram_3 (
	output [7:0] data_out,
	input [7:0] data_in,
	input [9:0] addr,
	input wr,
	input cs);


 parameter addr_size = 10, word_size = 8, memory_size = 1024;





 reg [word_size-1:0] mem [memory_size-1:0];

 assign data_out = mem[addr];

 always @(wr or cs)
 begin
	 if(wr)
		 mem[addr] = data_in;
 end
endmodule