data/full_repos/permissive/159902111/MCPU_experiment/B.v
data/verilator_xmls/47d9cd91-1959-4703-85ab-749fc8ec16d3.xml
module B(
  input clk,
  input rst_n,
  input [31:0] Rdata2_i,
  
  output [31:0] data2_o
  );
  reg [31:0] B;
  always@(posedge clk or posedge rst_n)
  begin
    if (rst_n)
      B <= 32'h0;
    else
      B <= Rdata2_i;
  end
  assign data2_o = B;
endmodule
module B(
  input clk,
  input rst_n,
  input [31:0] Rdata2_i,
  
  output [31:0] data2_o
  );

  reg [31:0] B;
  always@(posedge clk or posedge rst_n)
  begin
    if (rst_n)
      B <= 32'h0;
    else
      B <= Rdata2_i;
  end
  assign data2_o = B;
endmodule