data/full_repos/permissive/133571498/dance/top_tb.v
 line:19: before: ";"
1: b'%Error: data/full_repos/permissive/133571498/dance/top_tb.v:19: Unsupported: event data types\n    event terminate;\n    ^~~~~\n%Error: data/full_repos/permissive/133571498/dance/top_tb.v:20: Unsupported: event data types\n    event reset_enable, reset_done;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133571498/dance/top_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        forever #(PERIOD/2) clock = !clock;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/133571498/dance/top_tb.v:37: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("top_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/133571498/dance/top_tb.v:38: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/133571498/dance/top_tb.v:43: syntax error, unexpected \'@\'\n        @(reset_enable);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/133571498/dance/top_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #15 reset = 0;\n        ^\n%Error: data/full_repos/permissive/133571498/dance/top_tb.v:51: syntax error, unexpected \'@\'\n        @(posedge clock);\n        ^\n%Error: data/full_repos/permissive/133571498/dance/top_tb.v:54: syntax error, unexpected ->\n        -> reset_done;\n        ^~\n%Error: data/full_repos/permissive/133571498/dance/top_tb.v:59: syntax error, unexpected ->\n        -> reset_enable;\n        ^~\n%Error: data/full_repos/permissive/133571498/dance/top_tb.v:63: syntax error, unexpected \'@\'\n            @(posedge clock);\n            ^\n%Error: data/full_repos/permissive/133571498/dance/top_tb.v:70: syntax error, unexpected ->\n        -> terminate;\n        ^~\n%Error: data/full_repos/permissive/133571498/dance/top_tb.v:75: syntax error, unexpected \'@\'\n        @(terminate);\n        ^\n%Error: Exiting due to 11 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb;

    parameter PERIOD = 20;

    reg clock;
    reg reset;
    wire [4:0] led;

    top top (
        .clock (clock),
        .reset (reset),
        .led   (led)
    );

    event terminate;
    event reset_enable, reset_done;

    reg [4:0] test_data [0:8];
    integer err_cnt, i;


    initial begin
        $readmemb("prog.hex", test_data);
    end


    initial begin
        forever #(PERIOD/2) clock = !clock;
    end


    initial begin
		$dumpfile("top_tb.vcd");
		$dumpvars;
        $display("----------------------------------------");
	end

    initial begin
        @(reset_enable);
        $display("Resetting DUT");

        err_cnt = 0;
        clock   = 0;
        reset   = 1;

        #15 reset = 0;
        @(posedge clock);

        $display("Reset complete");
        -> reset_done;
    end


    initial begin
        -> reset_enable;
        @(reset_done);

        for (i = 0; i < 8; i++) begin
            @(posedge clock);
            if (led !== test_data[i]) begin
                err_cnt++;
                $display("[%dns] Expected %b, got %b", $time, test_data[i],
                         led);
            end
        end
        -> terminate;
    end


    initial begin
        @(terminate);
        $display("Simulation complete!");
        $display("%0d errors", err_cnt);
        $display("----------------------------------------");
        $finish;
    end

endmodule
module top_tb;


    parameter PERIOD = 20;

    reg clock;
    reg reset;
    wire [4:0] led;

    top top (
        .clock (clock),
        .reset (reset),
        .led   (led)
    );

    event terminate;
    event reset_enable, reset_done;

    reg [4:0] test_data [0:8];
    integer err_cnt, i;


    initial begin
        $readmemb("prog.hex", test_data);
    end


    initial begin
        forever #(PERIOD/2) clock = !clock;
    end


    initial begin
		$dumpfile("top_tb.vcd");
		$dumpvars;
        $display("----------------------------------------");
	end

    initial begin
        @(reset_enable);
        $display("Resetting DUT");

        err_cnt = 0;
        clock   = 0;
        reset   = 1;

        #15 reset = 0;
        @(posedge clock);

        $display("Reset complete");
        -> reset_done;
    end


    initial begin
        -> reset_enable;
        @(reset_done);

        for (i = 0; i < 8; i++) begin
            @(posedge clock);
            if (led !== test_data[i]) begin
                err_cnt++;
                $display("[%dns] Expected %b, got %b", $time, test_data[i],
                         led);
            end
        end
        -> terminate;
    end


    initial begin
        @(terminate);
        $display("Simulation complete!");
        $display("%0d errors", err_cnt);
        $display("----------------------------------------");
        $finish;
    end

endmodule