data/full_repos/permissive/159001439/src/bcd2bin.v
data/verilator_xmls/ea207250-e674-4df6-a543-b0686a92e297.xml
module bcd2bin #(parameter BB = 32, MB = 18) (
	input clk_i,
	input rst_i,
	input clr_i,
	input nd_i,
	input [3:0] bcd_i,
	input [MB-1:0] wgt_i,
	output [BB-1:0] q_o
);

reg [BB-1:0] acc_1;
assign q_o = acc_1;

always @(posedge clk_i, posedge rst_i)
begin
	if(rst_i)
	begin
		acc_1 <= 'b0;
	end
	else if(clr_i)
	begin
		if(nd_i)
			acc_1 <= bcd_i*wgt_i;
		else
			acc_1 <= 'b0;
	end
	else if(nd_i)
	begin

		acc_1 <= acc_1 + bcd_i*wgt_i;
	end
end

endmodule
module bcd2bin #(parameter BB = 32, MB = 18) (
	input clk_i,
	input rst_i,
	input clr_i,
	input nd_i,
	input [3:0] bcd_i,
	input [MB-1:0] wgt_i,
	output [BB-1:0] q_o
);


reg [BB-1:0] acc_1;
assign q_o = acc_1;

always @(posedge clk_i, posedge rst_i)
begin
	if(rst_i)
	begin
		acc_1 <= 'b0;
	end
	else if(clr_i)
	begin
		if(nd_i)
			acc_1 <= bcd_i*wgt_i;
		else
			acc_1 <= 'b0;
	end
	else if(nd_i)
	begin

		acc_1 <= acc_1 + bcd_i*wgt_i;
	end
end

endmodule