data/full_repos/permissive/172912857/project_alu_basys3/alu_basys3.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/172912857/project_alu_basys3/alu_basys3.v:31: Signal definition not found, creating implicitly: \'zr\'\n            .zr(zr),\n                ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/172912857/project_alu_basys3/alu_basys3.v:32: Signal definition not found, creating implicitly: \'ng\'\n            .ng(ng)\n                ^~\n%Warning-LITENDIAN: data/full_repos/permissive/172912857/project_alu_basys3/alu_basys3.v:87: Little bit endian vector: MSB < LSB of bit range: 1:6\n    input [1:6] c,\n          ^\n%Error: Exiting due to 3 warning(s)\n'
module data(
    input [15:0] data,

    input reset,
    input [2:0] load,
    output reg [15:0] x, y,
    output reg [5:0] opcode
    );
    
wire load_x, load_y, load_opcode;




       


always @(*)
if (reset)
    begin
    x = 0;
    y = 0;
    opcode = 0;
    end
else
    begin
        case (load)
        3'b001 : x = data;
        3'b010 : y = data;
        3'b100 : opcode = data[5:0];
        endcase
    end
       
endmodule
module data(
    input [15:0] data,

    input reset,
    input [2:0] load,
    output reg [15:0] x, y,
    output reg [5:0] opcode
    );

    
wire load_x, load_y, load_opcode;




       


always @(*)
if (reset)
    begin
    x = 0;
    y = 0;
    opcode = 0;
    end
else
    begin
        case (load)
        3'b001 : x = data;
        3'b010 : y = data;
        3'b100 : opcode = data[5:0];
        endcase
    end
       
endmodule