data/full_repos/permissive/102388603/rmii_send_pack.v
1: b'%Error: data/full_repos/permissive/102388603/rmii_send_pack.v:18: Cannot find file containing module: \'timer\'\ntimer #(.period(1000000)) startTimer(.clk(clk),.rst(rst),.out(start));\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/timer\n             data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/timer.v\n             data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/timer.sv\n             timer\n             timer.v\n             timer.sv\n             obj_dir/timer\n             obj_dir/timer.v\n             obj_dir/timer.sv\n%Error: data/full_repos/permissive/102388603/rmii_send_pack.v:38: Cannot find file containing module: \'rmii_tx\'\nrmii_tx rmiiTx(.clk(clk), .rst(rst), .dataIn(byteSendRmii), .start(startSendRmii), .dataLen(72),\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/102388603/rmii_send_pack.v:66: Bit extraction of array[71:0] requires 7 bit index, not 16 bits.\n                                                                        : ... In instance rmii_send_pack\n   byteSendRmii <= packUDP[countByteSend];  \n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102388603/rmii_send_pack.v:80: Bit extraction of array[71:0] requires 7 bit index, not 16 bits.\n                                                                        : ... In instance rmii_send_pack\n   byteSendRmii <= packUDP[countByteSend];  \n                          ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module rmii_send_pack
(	input clk,
	input nrst,
	output [1:0]PhyTxd,
	output reg PhyClk50Mhz,
	output PhyTxEn,
	output reg PhyRstn);
	
wire rst;
assign rst = ~nrst;

wire start;

timer #(.period(1000000)) startTimer(.clk(clk),.rst(rst),.out(start));


parameter lenPack = 72;
reg [7:0]packUDP[0:lenPack-1];
initial $readmemh("packUDP.hex",packUDP);

reg [15:0]countByteSend;

reg [7:0]byteSendRmii;
reg startSendRmii;

always @(posedge clk, posedge rst)
if(rst)
	PhyClk50Mhz <= 0;
else
	PhyClk50Mhz <= ~PhyClk50Mhz;
	
wire getByte;
wire readyRMII;
rmii_tx rmiiTx(.clk(clk), .rst(rst), .dataIn(byteSendRmii), .start(startSendRmii), .dataLen(72),
	.ready(readyRMII), .dataOut(PhyTxd), .TXEN(PhyTxEn), .getByte(getByte));

reg [1:0] state;
parameter idle 	= 2'b00;
parameter send	= 2'b01;

reg tmpGetByte;
always @(posedge clk, posedge rst)
if(rst)
begin
	countByteSend <= 0;
	byteSendRmii <= 0;
	startSendRmii <= 0;
	state <= idle;
	tmpGetByte <= 0;
	PhyRstn <= 0;
end
else
begin
	PhyRstn <= 1;
	tmpGetByte <= getByte;
	case(state)
	idle:
	begin
		if(start)
		begin
			countByteSend <= 1;
			byteSendRmii <= packUDP[countByteSend];
			startSendRmii <= 1;
			
			state <= send;
		end
	end
	
	send:
	begin

		if((getByte == 1) && (tmpGetByte == 0))
		begin
			startSendRmii <= 0;
			countByteSend <= countByteSend + 1;
			byteSendRmii <= packUDP[countByteSend];
		end
		else if(readyRMII & (countByteSend >= lenPack))
		begin
			state <= idle;
			countByteSend <= 0;
		end
	end
	endcase
end

endmodule
module rmii_send_pack
(	input clk,
	input nrst,
	output [1:0]PhyTxd,
	output reg PhyClk50Mhz,
	output PhyTxEn,
	output reg PhyRstn);

	
wire rst;
assign rst = ~nrst;

wire start;

timer #(.period(1000000)) startTimer(.clk(clk),.rst(rst),.out(start));


parameter lenPack = 72;
reg [7:0]packUDP[0:lenPack-1];
initial $readmemh("packUDP.hex",packUDP);

reg [15:0]countByteSend;

reg [7:0]byteSendRmii;
reg startSendRmii;

always @(posedge clk, posedge rst)
if(rst)
	PhyClk50Mhz <= 0;
else
	PhyClk50Mhz <= ~PhyClk50Mhz;
	
wire getByte;
wire readyRMII;
rmii_tx rmiiTx(.clk(clk), .rst(rst), .dataIn(byteSendRmii), .start(startSendRmii), .dataLen(72),
	.ready(readyRMII), .dataOut(PhyTxd), .TXEN(PhyTxEn), .getByte(getByte));

reg [1:0] state;
parameter idle 	= 2'b00;
parameter send	= 2'b01;

reg tmpGetByte;
always @(posedge clk, posedge rst)
if(rst)
begin
	countByteSend <= 0;
	byteSendRmii <= 0;
	startSendRmii <= 0;
	state <= idle;
	tmpGetByte <= 0;
	PhyRstn <= 0;
end
else
begin
	PhyRstn <= 1;
	tmpGetByte <= getByte;
	case(state)
	idle:
	begin
		if(start)
		begin
			countByteSend <= 1;
			byteSendRmii <= packUDP[countByteSend];
			startSendRmii <= 1;
			
			state <= send;
		end
	end
	
	send:
	begin

		if((getByte == 1) && (tmpGetByte == 0))
		begin
			startSendRmii <= 0;
			countByteSend <= countByteSend + 1;
			byteSendRmii <= packUDP[countByteSend];
		end
		else if(readyRMII & (countByteSend >= lenPack))
		begin
			state <= idle;
			countByteSend <= 0;
		end
	end
	endcase
end

endmodule