data/full_repos/permissive/135701568/EXE_MEM_Reg.v
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data/verilator_xmls/c5ae45fa-a8a7-4531-9d90-573c44a2c38b.xml
module EXE_MEM_Reg (clk, rst, regWr_IN, memWr_IN, memRd_IN, aluRes_IN, memWrData_IN, rd_IN,
  regWr_OUT, memWr_OUT, memRd_OUT, aluRes_OUT, memWrData_OUT, rd_OUT);

  input clk, rst, regWr_IN, memWr_IN, memRd_IN;
  input[2:0] rd_IN;
  input[7:0] aluRes_IN, memWrData_IN;
  output reg regWr_OUT, memWr_OUT, memRd_OUT;
  output reg[2:0] rd_OUT;
  output reg[7:0] aluRes_OUT, memWrData_OUT;

  always @(posedge clk, posedge rst) begin
    if (rst) begin
      {regWr_OUT, memWr_OUT, memRd_OUT, rd_OUT, aluRes_OUT, memWrData_OUT} <= 0;
    end
    else begin
      regWr_OUT <= regWr_IN; memWr_OUT <= memWr_IN; memRd_OUT <= memRd_IN;
      rd_OUT <= rd_IN; aluRes_OUT <= aluRes_IN; memWrData_OUT <= memWrData_IN;
    end
  end

endmodule
module EXE_MEM_Reg (clk, rst, regWr_IN, memWr_IN, memRd_IN, aluRes_IN, memWrData_IN, rd_IN,
  regWr_OUT, memWr_OUT, memRd_OUT, aluRes_OUT, memWrData_OUT, rd_OUT);


  input clk, rst, regWr_IN, memWr_IN, memRd_IN;
  input[2:0] rd_IN;
  input[7:0] aluRes_IN, memWrData_IN;
  output reg regWr_OUT, memWr_OUT, memRd_OUT;
  output reg[2:0] rd_OUT;
  output reg[7:0] aluRes_OUT, memWrData_OUT;

  always @(posedge clk, posedge rst) begin
    if (rst) begin
      {regWr_OUT, memWr_OUT, memRd_OUT, rd_OUT, aluRes_OUT, memWrData_OUT} <= 0;
    end
    else begin
      regWr_OUT <= regWr_IN; memWr_OUT <= memWr_IN; memRd_OUT <= memRd_IN;
      rd_OUT <= rd_IN; aluRes_OUT <= aluRes_IN; memWrData_OUT <= memWrData_IN;
    end
  end

endmodule