data/full_repos/permissive/159016511/src/rtl/common/rst_sync.v
data/verilator_xmls/d992e54e-28c8-461b-b50b-1ce4708ce782.xml
module rst_sync (
input wire clk,
input wire in_rstn,
output wire out_rstn
);

reg rstn_d1;
reg rstn_d2;

always @ (posedge clk or negedge in_rstn)
begin
	if(!in_rstn)
	begin
		rstn_d1 <= 1'b0;
		rstn_d2 <= 1'b0;
	end
	else
	begin
		rstn_d1 <= 1'b1;
		rstn_d2 <= rstn_d1;
	end
end
assign out_rstn = in_rstn && rstn_d2;


endmodule
module rst_sync (
input wire clk,
input wire in_rstn,
output wire out_rstn
);


reg rstn_d1;
reg rstn_d2;

always @ (posedge clk or negedge in_rstn)
begin
	if(!in_rstn)
	begin
		rstn_d1 <= 1'b0;
		rstn_d2 <= 1'b0;
	end
	else
	begin
		rstn_d1 <= 1'b1;
		rstn_d2 <= rstn_d1;
	end
end
assign out_rstn = in_rstn && rstn_d2;


endmodule