data/full_repos/permissive/194920488/minlib.v
 line:167: before: "for"
1: b'%Warning-MULTITOP: data/full_repos/permissive/194920488/minlib.v:37: Multiple top level modules\n                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                   : ... Top module \'priority_arb\'\nmodule priority_arb #( parameter integer N = 1 ) (\n       ^~~~~~~~~~~~\n                                                                   : ... Top module \'sequencer\'\nmodule sequencer #( parameter integer N = 0, parameter [N-1:0] sticky = 0 ) (\n       ^~~~~~~~~\n                                                                   : ... Top module \'one_hot_mux\'\nmodule one_hot_mux #( parameter integer Ninputs = 0, parameter integer Nbits = 1 ) (\n       ^~~~~~~~~~~\n                                                                   : ... Top module \'pipeline\'\nmodule pipeline #( parameter Nbits = 1, parameter Nstages = 1 ) (\n       ^~~~~~~~\n                                                                   : ... Top module \'pipeline_resetable\'\nmodule pipeline_resetable #( parameter Nbits = 1, parameter Nstages = 1 ) (\n       ^~~~~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/194920488/minlib.v:37: Little bit endian vector: MSB < LSB of bit range: -1:0\nmodule sequencer #( parameter integer N = 0, parameter [N-1:0] sticky = 0 ) (\n                                                       ^\n%Warning-LITENDIAN: data/full_repos/permissive/194920488/minlib.v:91: Little bit endian vector: MSB < LSB of bit range: -1:0\n      input [ Ninputs*Nbits -1 : 0 ] ins\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/194920488/minlib.v:92: Little bit endian vector: MSB < LSB of bit range: -1:0\n    , input [ Ninputs       -1 : 0 ] select\n            ^\n%Warning-WIDTH: data/full_repos/permissive/194920488/minlib.v:114: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n                                                                 : ... In instance one_hot_mux\n        tmp = ins >> ( Nbits * i );\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/194920488/minlib.v:38: Little bit endian vector: MSB < LSB of bit range: -1:0\n      input      [N-1:0] readyIn\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/194920488/minlib.v:39: Little bit endian vector: MSB < LSB of bit range: -1:0\n    , output reg [N-1:0] readyOut\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/194920488/minlib.v:45: Little bit endian vector: MSB < LSB of bit range: -1:0\nreg [     N-1 : 0] outs;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/194920488/minlib.v:48: Little bit endian vector: MSB < LSB of bit range: -1:0\nreg [ Nbits-1 : 0] state;       \n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/194920488/minlib.v:49: Little bit endian vector: MSB < LSB of bit range: -1:0\nreg [ Nbits-1 : 0] state1;      \n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/194920488/minlib.v:50: Little bit endian vector: MSB < LSB of bit range: -1:0\nreg [ Nbits-1 : 0] state_next;  \n    ^\n%Warning-WIDTH: data/full_repos/permissive/194920488/minlib.v:72: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                : ... In instance sequencer\n                state1 = ( i+1 < N ) ? i+1 : 0;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/194920488/minlib.v:69: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'state1\' generates 2 bits.\n                                                                : ... In instance sequencer\n        if ( !done && ( i == state1 ) ) begin\n                          ^~\n%Error: Exiting due to 13 warning(s)\n'
module register_resetable #( parameter Nbits = 1 ) (
      input  [ Nbits-1:0 ] in
    , input                enable
    , output reg [ Nbits-1:0 ] out

    , input                clk
    , input                 resetn
);

always @(posedge clk ) begin
    if (!resetn) out <= 0;
    else if ( enable ) out <= in;
end

endmodule
module register_resetable #( parameter Nbits = 1 ) (
      input  [ Nbits-1:0 ] in
    , input                enable
    , output reg [ Nbits-1:0 ] out

    , input                clk
    , input                 resetn
);


always @(posedge clk ) begin
    if (!resetn) out <= 0;
    else if ( enable ) out <= in;
end

endmodule