data/full_repos/permissive/214126507/quartus/testbench.sv
 line:51 column:14: Illegal character "'"
1: b'%Warning-STMTDLY: data/full_repos/permissive/214126507/quartus/testbench.sv:57: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/214126507/quartus/testbench.sv:60: Unsupported: Ignoring delay on this delayed statement.\n   #5 CLK1_50 = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/214126507/quartus/testbench.sv:61: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/214126507/quartus/testbench.sv:67: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/214126507/quartus/testbench.sv:71: Unsupported: Ignoring delay on this delayed statement.\n initial #2000000\n         ^\n%Error: data/full_repos/permissive/214126507/quartus/testbench.sv:26: Cannot find file containing module: \'CPU\'\n CPU DUT(\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/214126507/quartus,data/full_repos/permissive/214126507/CPU\n             data/full_repos/permissive/214126507/quartus,data/full_repos/permissive/214126507/CPU.v\n             data/full_repos/permissive/214126507/quartus,data/full_repos/permissive/214126507/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench; 
	reg SW[9:0];
	reg KEY[1:0];
	wire LEDR[9:0];
	reg CLK1_50;
	wire [3:0] VGA_R;
	wire [3:0] VGA_G;
	wire [3:0] VGA_B;
	wire VGA_HS;
	wire VGA_VS;
	wire[15:0] PC;
	wire[15:0] STATE;
	wire[15:0] OPCODE;
	wire[15:0] ROM;
	wire[15:0] SP;
	wire[15:0] ADDR;
	wire[7:0] HEX0;
	wire[7:0] HEX1;
	wire[7:0] HEX2;
	wire[7:0] HEX3;
	wire[7:0] HEX4;
	wire[7:0] HEX5;


	CPU DUT(
		.CLK1_50(CLK1_50),
		.SW(SW),
		.KEY(KEY),
		.LEDR(LEDR),
		.VGA_R(VGA_R),
		.VGA_G(VGA_G),
		.VGA_B(VGA_B),
		.VGA_HS(VGA_HS),
		.VGA_VS(VGA_VS),
		.OUT1(PC),
		.OUT2(STATE),
		.OUT3(OPCODE),
		.OUT4(ROM),
		.OUT5(SP),
		.OUT6(ADDR),
		.HEX0(HEX0),
		.HEX1(HEX1),
		.HEX2(HEX2),
		.HEX3(HEX3),
		.HEX4(HEX4),
		.HEX5(HEX5)
	);

	initial begin
		SW[9:0] = '{ 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0 };
		KEY[1:0] = '{1'b1, 1'b0};
	end

	initial begin
		CLK1_50 = 0;
		#5;
		forever begin
			CLK1_50 = 1;
			#5 CLK1_50 = 0;
			#5;
		end
	end

	initial begin
		KEY[0] = 0;
		#1000;
		KEY[0] = 1;
	end

	initial #2000000
		$stop;
endmodule
module testbench;
 
	reg SW[9:0];
	reg KEY[1:0];
	wire LEDR[9:0];
	reg CLK1_50;
	wire [3:0] VGA_R;
	wire [3:0] VGA_G;
	wire [3:0] VGA_B;
	wire VGA_HS;
	wire VGA_VS;
	wire[15:0] PC;
	wire[15:0] STATE;
	wire[15:0] OPCODE;
	wire[15:0] ROM;
	wire[15:0] SP;
	wire[15:0] ADDR;
	wire[7:0] HEX0;
	wire[7:0] HEX1;
	wire[7:0] HEX2;
	wire[7:0] HEX3;
	wire[7:0] HEX4;
	wire[7:0] HEX5;


	CPU DUT(
		.CLK1_50(CLK1_50),
		.SW(SW),
		.KEY(KEY),
		.LEDR(LEDR),
		.VGA_R(VGA_R),
		.VGA_G(VGA_G),
		.VGA_B(VGA_B),
		.VGA_HS(VGA_HS),
		.VGA_VS(VGA_VS),
		.OUT1(PC),
		.OUT2(STATE),
		.OUT3(OPCODE),
		.OUT4(ROM),
		.OUT5(SP),
		.OUT6(ADDR),
		.HEX0(HEX0),
		.HEX1(HEX1),
		.HEX2(HEX2),
		.HEX3(HEX3),
		.HEX4(HEX4),
		.HEX5(HEX5)
	);

	initial begin
		SW[9:0] = '{ 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0 };
		KEY[1:0] = '{1'b1, 1'b0};
	end

	initial begin
		CLK1_50 = 0;
		#5;
		forever begin
			CLK1_50 = 1;
			#5 CLK1_50 = 0;
			#5;
		end
	end

	initial begin
		KEY[0] = 0;
		#1000;
		KEY[0] = 1;
	end

	initial #2000000
		$stop;
endmodule