data/full_repos/permissive/205055389/vlib/tty.v
1: b'%Error: data/full_repos/permissive/205055389/vlib/tty.v:151: Unsupported or unknown PLI call: $tkg$post\n  initial $tkg$post("TTY","%m");\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:156: syntax error, unexpected \'@\'\n      @(posedge DSR);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:157: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:160: Unsupported or unknown PLI call: $tkg$send\n      $tkg$send("%m.RD",RD);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:161: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:162: syntax error, unexpected \'@\'\n      @(negedge DSR);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:163: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:168: syntax error, unexpected \'@\'\n      @ (negedge CTS);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:169: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:170: Unsupported or unknown PLI call: $tkg$recv\n      data = $tkg$recv("%m.TD");\n             ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:171: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:173: syntax error, unexpected \'@\'\n      @ (posedge CTS);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:174: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n%Error: Exiting due to 7 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
wire w4;
wire [7:0] w3;
wire [7:0] w0;
wire w1;
wire w2;
wire w5;


  TTY g0 (.TD(w0), .DSR(w1), .RTS(w2), .RD(w3), .CTS(w4), .DTR(w5));

endmodule
module main;

wire w4;
wire [7:0] w3;
wire [7:0] w0;
wire w1;
wire w2;
wire w5;


  TTY g0 (.TD(w0), .DSR(w1), .RTS(w2), .RD(w3), .CTS(w4), .DTR(w5));

endmodule