data/full_repos/permissive/115837888/source-7400/7442-tb.v
 line:5: before: "tbassert"
1: b'%Error: data/full_repos/permissive/115837888/source-7400/7442-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7442-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7442-tb.v:6: Define or directive not defined: \'`TBASSERT_2_METHOD\'\n`TBASSERT_2_METHOD(tbassert2)\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7442-tb.v:30: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("7442-tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7442-tb.v:31: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/7442-tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 5 error(s), 18 warning(s)\n'
module test;

`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)

localparam WIDTH_OUT = 10;

localparam WIDTH_IN = $clog2(WIDTH_OUT);



reg [WIDTH_IN-1:0] A;


wire [WIDTH_OUT-1:0] Y;


ttl_7442 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .A(A),
  .Y(Y)
);

initial
begin
  reg [WIDTH_OUT-1:0] Y_expected;
  integer i;

  $dumpfile("7442-tb.vcd");
  $dumpvars;


  A = 4'b0000;
#6
  tbassert(Y == 10'b1111111110, "Test 1");
#0

  A = 4'b0001;
#6
  tbassert(Y == 10'b1111111101, "Test 2");
#0

  A = 4'b1001;
#6
  tbassert(Y == 10'b0111111111, "Test 3");
#0

  A = 4'b1111;
#10
  tbassert(Y == 10'b1111111111, "Test 4");
#0

  A = 4'b1010;
#10
  tbassert(Y == 10'b1111111111, "Test 5");
#0



  for (i = 9; i >= 0; i--)
  begin
    A = i;

    case (i)
      9:
      begin
        Y_expected = 10'b0111111111;
      end
      8:
      begin
        Y_expected = 10'b1011111111;
      end
      7:
      begin
        Y_expected = 10'b1101111111;
      end
      6:
      begin
        Y_expected = 10'b1110111111;
      end
      5:
      begin
        Y_expected = 10'b1111011111;
      end
      4:
      begin
        Y_expected = 10'b1111101111;
      end
      3:
      begin
        Y_expected = 10'b1111110111;
      end
      2:
      begin
        Y_expected = 10'b1111111011;
      end
      1:
      begin
        Y_expected = 10'b1111111101;
      end
      0:
      begin
        Y_expected = 10'b1111111110;
      end
    endcase
#10
    tbassert2(Y == Y_expected, "Test", (10 - i), "6");

  end


#0


  A = 4'b1110;
#6
  tbassert(Y == 10'b1111111111, "Test 7");
#0
  A = 4'b0110;
#6
  tbassert(Y == 10'b1110111111, "Test 7");
#0

  A = 4'b1001;
#6
  tbassert(Y == 10'b0111111111, "Test 8");
#10
  $finish;
end

endmodule
module test;


`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)

localparam WIDTH_OUT = 10;

localparam WIDTH_IN = $clog2(WIDTH_OUT);



reg [WIDTH_IN-1:0] A;


wire [WIDTH_OUT-1:0] Y;


ttl_7442 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .A(A),
  .Y(Y)
);

initial
begin
  reg [WIDTH_OUT-1:0] Y_expected;
  integer i;

  $dumpfile("7442-tb.vcd");
  $dumpvars;


  A = 4'b0000;
#6
  tbassert(Y == 10'b1111111110, "Test 1");
#0

  A = 4'b0001;
#6
  tbassert(Y == 10'b1111111101, "Test 2");
#0

  A = 4'b1001;
#6
  tbassert(Y == 10'b0111111111, "Test 3");
#0

  A = 4'b1111;
#10
  tbassert(Y == 10'b1111111111, "Test 4");
#0

  A = 4'b1010;
#10
  tbassert(Y == 10'b1111111111, "Test 5");
#0



  for (i = 9; i >= 0; i--)
  begin
    A = i;

    case (i)
      9:
      begin
        Y_expected = 10'b0111111111;
      end
      8:
      begin
        Y_expected = 10'b1011111111;
      end
      7:
      begin
        Y_expected = 10'b1101111111;
      end
      6:
      begin
        Y_expected = 10'b1110111111;
      end
      5:
      begin
        Y_expected = 10'b1111011111;
      end
      4:
      begin
        Y_expected = 10'b1111101111;
      end
      3:
      begin
        Y_expected = 10'b1111110111;
      end
      2:
      begin
        Y_expected = 10'b1111111011;
      end
      1:
      begin
        Y_expected = 10'b1111111101;
      end
      0:
      begin
        Y_expected = 10'b1111111110;
      end
    endcase
#10
    tbassert2(Y == Y_expected, "Test", (10 - i), "6");

  end


#0


  A = 4'b1110;
#6
  tbassert(Y == 10'b1111111111, "Test 7");
#0
  A = 4'b0110;
#6
  tbassert(Y == 10'b1110111111, "Test 7");
#0

  A = 4'b1001;
#6
  tbassert(Y == 10'b0111111111, "Test 8");
#10
  $finish;
end

endmodule