data/full_repos/permissive/162672365/Mux.v
data/verilator_xmls/e3c1508f-1b12-4134-a21a-afcd103f3c3b.xml
module bit32_3to1mux (out, select, in1, in2, in3);
	input [31:0] in1, in2, in3;
	input [1:0] select;
	output [31:0] out;
	genvar j;
	
	generate
		for(j = 0; j <32; j = j + 1) begin: mux_loop
			mux3to1 m1(out[j], select, in1[j], in2[j], in3[j]);
		end
	endgenerate
	
endmodule
module bit32_3to1mux (out, select, in1, in2, in3);

	input [31:0] in1, in2, in3;
	input [1:0] select;
	output [31:0] out;
	genvar j;
	
	generate
		for(j = 0; j <32; j = j + 1) begin: mux_loop
			mux3to1 m1(out[j], select, in1[j], in2[j], in3[j]);
		end
	endgenerate
	
endmodule