data/full_repos/permissive/170402453/RISC_DIVIDER/MUX2.v
data/verilator_xmls/4157f9f4-ab7f-486d-8403-f14b513ef52d.xml
module MUX2(
    input select,
    input [BITS-1:0] in1,
    input [BITS-1:0] in2,
    output wire [BITS-1:0] out
    );
	 
	 parameter BITS = 32;
	 
	 assign out = (select == 0) ? in1 :
					  (select == 1) ? in2 : 32'hXXXXXXXX;
endmodule
module MUX2(
    input select,
    input [BITS-1:0] in1,
    input [BITS-1:0] in2,
    output wire [BITS-1:0] out
    );

	 
	 parameter BITS = 32;
	 
	 assign out = (select == 0) ? in1 :
					  (select == 1) ? in2 : 32'hXXXXXXXX;
endmodule