data/full_repos/permissive/150329835/src/Logic.v
data/verilator_xmls/3acdeef9-c225-4a37-87dc-bdd5b6b007ea.xml
module MY_OR(A,B,F);
	input [3:0] A,B;
	output [9:0] F;
	
	assign F[0] = A[0]|B[0];
	assign F[1] = A[1]|B[1];
	assign F[2] = A[2]|B[2];
	assign F[3] = A[3]|B[3];
	assign F[9:4] = 6'b000000;
endmodule
module MY_OR(A,B,F);

	input [3:0] A,B;
	output [9:0] F;
	
	assign F[0] = A[0]|B[0];
	assign F[1] = A[1]|B[1];
	assign F[2] = A[2]|B[2];
	assign F[3] = A[3]|B[3];
	assign F[9:4] = 6'b000000;
endmodule