data/full_repos/permissive/194847941/demo_v_5_6/11_SparkRoad/FPGA/sparkroad/src/rtl/flash/flash_write.v
data/verilator_xmls/e7eb4cb5-0193-49db-8ccb-08451c26217a.xml
module flash_write
(
    input   wire        clk,


    output  reg         fls_sck,
    output  reg         fls_ncs,
    output  reg         fls_sdo,
    input   wire        fls_sdi,


    input   wire        start,
    input   wire [23:0] addr,
    input   wire [7:0]  din,

    output  reg         busy
);

reg [9:0] cnt;
reg [6:0] cycle_cnt; 
reg [2:0] phase_cnt;
reg [39:0] tx_reg;
reg sft_wen;
reg byte_flag;

initial
begin
    cnt = 0;
    tx_reg = 40'd0;
    busy = 0;
end


always@(posedge clk)
begin
    if(busy)
        cnt <= cnt + 1;
    else
        cnt <= 0;
end


always@(posedge clk)
begin
    cycle_cnt <= cnt[9:3];
end


always@(posedge clk)
begin
    phase_cnt <= cnt[2:0];
end


always@(posedge clk)
begin
    fls_sck <= cnt[2];
end


always@(posedge clk)
begin
    if(busy)
        fls_ncs <= 0;
    else
        fls_ncs <= 1;
end


always@(posedge clk)
begin
    if(start)
        tx_reg <= {8'h02,addr,din};
    else if(sft_wen)
        tx_reg <= {tx_reg[38:0],1'b0};
end


always@(posedge clk)
begin
    sft_wen <= (phase_cnt == 6);
end


always@(posedge clk)
begin
    byte_flag <= (cycle_cnt[2:0] == 7) && (phase_cnt == 5);
end


always@(posedge clk)
begin
    fls_sdo <= tx_reg[39];
end


always@(posedge clk)
begin
    if(start)
        busy <= 1;
    else if(cycle_cnt == 40)
        busy <= 0;
end

endmodule
module flash_write
(
    input   wire        clk,


    output  reg         fls_sck,
    output  reg         fls_ncs,
    output  reg         fls_sdo,
    input   wire        fls_sdi,


    input   wire        start,
    input   wire [23:0] addr,
    input   wire [7:0]  din,

    output  reg         busy
);


reg [9:0] cnt;
reg [6:0] cycle_cnt; 
reg [2:0] phase_cnt;
reg [39:0] tx_reg;
reg sft_wen;
reg byte_flag;

initial
begin
    cnt = 0;
    tx_reg = 40'd0;
    busy = 0;
end


always@(posedge clk)
begin
    if(busy)
        cnt <= cnt + 1;
    else
        cnt <= 0;
end


always@(posedge clk)
begin
    cycle_cnt <= cnt[9:3];
end


always@(posedge clk)
begin
    phase_cnt <= cnt[2:0];
end


always@(posedge clk)
begin
    fls_sck <= cnt[2];
end


always@(posedge clk)
begin
    if(busy)
        fls_ncs <= 0;
    else
        fls_ncs <= 1;
end


always@(posedge clk)
begin
    if(start)
        tx_reg <= {8'h02,addr,din};
    else if(sft_wen)
        tx_reg <= {tx_reg[38:0],1'b0};
end


always@(posedge clk)
begin
    sft_wen <= (phase_cnt == 6);
end


always@(posedge clk)
begin
    byte_flag <= (cycle_cnt[2:0] == 7) && (phase_cnt == 5);
end


always@(posedge clk)
begin
    fls_sdo <= tx_reg[39];
end


always@(posedge clk)
begin
    if(start)
        busy <= 1;
    else if(cycle_cnt == 40)
        busy <= 0;
end

endmodule