data/full_repos/permissive/162696624/Traffic Light.v
 line:32: before: "["
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/162696624/Traffic\n        ... Looked in:\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.sv\n             data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624/Traffic.sv\n             obj_dir/data/full_repos/permissive/162696624/Traffic\n             obj_dir/data/full_repos/permissive/162696624/Traffic.v\n             obj_dir/data/full_repos/permissive/162696624/Traffic.sv\n%Error: Cannot find file containing module: Light.v\n%Error: Exiting due to 2 error(s)\n'
module main(A,B,RST,CLK,L,BL,AL,finished);
   
    
   input  A,B,RST,CLK;
   output  [3:0] L;
   output  finished,AL,BL; 

   wire load,D;
   assign load = (A | B | finished);
   
   wire [7:0] O;
   wire [7:0] P;
   wire [7:0] Q;
   
 Meally_main meally(A,B,CLK,finished,AL,BL,D,RST); 
 
 
   assign  L[0]= (AL & ~BL);
   assign  L[1]= (~AL & ~BL&D);
   assign  L[2]= (~AL &  BL);
   assign  L[3]= (~AL & ~BL&~D);
   
   counter8 light90(8'b00000000,CLK,RST,load,~(A|B) & L[0],O);
   counter8 light30(8'b00000000,CLK,RST,load,~(A|B) & L[2],P);
   counter8 light5 (8'b00000000,CLK,RST,load,~(A|B) & (L[1]|L[3]),Q);
   
   wire Oa;
   assign Oa = ~O[7]&O[6]&~O[5]&O[4]&O[3]&~O[2]&O[1]&~O[0];
   wire  Pa;
   assign Pa=~P[7]& ~P[6]& ~P[5]& P[4]& P[3]& P[2]& P[1]& ~P[0] ;
   wire Qa;
   assign Qa=~Q[7]&~Q[6]&~Q[5]&~Q[4]&~Q[3]&Q[2]&~Q[1]&Q[0];
      
  assign finished = Oa| Pa | Qa;

 endmodule
module main(A,B,RST,CLK,L,BL,AL,finished);

   
    
   input  A,B,RST,CLK;
   output  [3:0] L;
   output  finished,AL,BL; 

   wire load,D;
   assign load = (A | B | finished);
   
   wire [7:0] O;
   wire [7:0] P;
   wire [7:0] Q;
   
 Meally_main meally(A,B,CLK,finished,AL,BL,D,RST); 
 
 
   assign  L[0]= (AL & ~BL);
   assign  L[1]= (~AL & ~BL&D);
   assign  L[2]= (~AL &  BL);
   assign  L[3]= (~AL & ~BL&~D);
   
   counter8 light90(8'b00000000,CLK,RST,load,~(A|B) & L[0],O);
   counter8 light30(8'b00000000,CLK,RST,load,~(A|B) & L[2],P);
   counter8 light5 (8'b00000000,CLK,RST,load,~(A|B) & (L[1]|L[3]),Q);
   
   wire Oa;
   assign Oa = ~O[7]&O[6]&~O[5]&O[4]&O[3]&~O[2]&O[1]&~O[0];
   wire  Pa;
   assign Pa=~P[7]& ~P[6]& ~P[5]& P[4]& P[3]& P[2]& P[1]& ~P[0] ;
   wire Qa;
   assign Qa=~Q[7]&~Q[6]&~Q[5]&~Q[4]&~Q[3]&Q[2]&~Q[1]&Q[0];
      
  assign finished = Oa| Pa | Qa;

 endmodule