data/full_repos/permissive/131069375/uv-risc/verilog/writeback.v
data/verilator_xmls/18ec4aeb-1a51-48c7-97af-b92680f3a287.xml
module writeback
(
 input 	       mem_re,
 input [15:0]  alu_out, data2,
 input [15:0]  mem_out,
 output [15:0] mem_addr,
 output [15:0] mem_in,
 output [15:0] result
 );
   
endmodule
module writeback
(
 input 	       mem_re,
 input [15:0]  alu_out, data2,
 input [15:0]  mem_out,
 output [15:0] mem_addr,
 output [15:0] mem_in,
 output [15:0] result
 );

   
endmodule