data/full_repos/permissive/157587577/Basics/verilog/Counter/Counter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/157587577/Basics/verilog/Counter/Counter_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157587577/Basics/verilog/Counter/Counter_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157587577/Basics/verilog/Counter/Counter_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #50 clk <= ~clk;\n    ^\n%Error: data/full_repos/permissive/157587577/Basics/verilog/Counter/Counter_tb.v:8: Cannot find file containing module: \'Counter\'\nCounter #(.DATA_WIDTH(4), .OUTPUT_DATA_WIDTH(8)) uut (.rst(rst), .clk(clk), .data(data));\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157587577/Basics/verilog/Counter,data/full_repos/permissive/157587577/Counter\n             data/full_repos/permissive/157587577/Basics/verilog/Counter,data/full_repos/permissive/157587577/Counter.v\n             data/full_repos/permissive/157587577/Basics/verilog/Counter,data/full_repos/permissive/157587577/Counter.sv\n             Counter\n             Counter.v\n             Counter.sv\n             obj_dir/Counter\n             obj_dir/Counter.v\n             obj_dir/Counter.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Counter_tb;

reg rst;
reg clk;
wire [7:0] data;

Counter #(.DATA_WIDTH(4), .OUTPUT_DATA_WIDTH(8)) uut (.rst(rst), .clk(clk), .data(data));

initial
begin
    clk <= 0;
    rst <= 1;
    #200
    rst <= 0;
    #200
    rst <= 1;
end

always
begin
    #50 clk <= ~clk;
end

endmodule
module Counter_tb;


reg rst;
reg clk;
wire [7:0] data;

Counter #(.DATA_WIDTH(4), .OUTPUT_DATA_WIDTH(8)) uut (.rst(rst), .clk(clk), .data(data));

initial
begin
    clk <= 0;
    rst <= 1;
    #200
    rst <= 0;
    #200
    rst <= 1;
end

always
begin
    #50 clk <= ~clk;
end

endmodule