data/full_repos/permissive/19478345/scratch_pad_gold/scratch_pad_gold_tb.v
 line:41: before: "$"
1: b'%Error: data/full_repos/permissive/19478345/scratch_pad_gold/scratch_pad_gold_tb.v:2: Cannot find include file: log2.vh\n    `include "log2.vh" \n             ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19478345/scratch_pad_gold,data/full_repos/permissive/19478345/log2.vh\n             data/full_repos/permissive/19478345/scratch_pad_gold,data/full_repos/permissive/19478345/log2.vh.v\n             data/full_repos/permissive/19478345/scratch_pad_gold,data/full_repos/permissive/19478345/log2.vh.sv\n             log2.vh\n             log2.vh.v\n             log2.vh.sv\n             obj_dir/log2.vh\n             obj_dir/log2.vh.v\n             obj_dir/log2.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/19478345/scratch_pad_gold/scratch_pad_gold_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = !clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/19478345/scratch_pad_gold/scratch_pad_gold_tb.v:23: Unsupported or unknown PLI call: $monitor\n        $monitor(valid[0]);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19478345/scratch_pad_gold/scratch_pad_gold_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #101 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/scratch_pad_gold/scratch_pad_gold_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #100 wr_en[0] = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/scratch_pad_gold/scratch_pad_gold_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10 wr_en = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/scratch_pad_gold/scratch_pad_gold_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #100 rd_en[0] = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/scratch_pad_gold/scratch_pad_gold_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #10 rd_en = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/scratch_pad_gold/scratch_pad_gold_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/scratch_pad_gold/scratch_pad_gold_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    initial #10000 $finish;\n            ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module scratch_pad_gold_tb;
    `include "log2.vh"
    `define PORTS 16
    `define WIDTH 64
    `define DEPTH `PORTS*512
    `define ADDR_WIDTH log2(`DEPTH-1)
    reg rst, clk;
    reg [0:`PORTS-1] rd_en, wr_en;
    reg [`PORTS*`WIDTH-1:0] d;
    wire [`PORTS*`WIDTH-1:0] q;
    reg [`PORTS*`ADDR_WIDTH-1:0] addr;
    reg [0:`PORTS-1] stall;
    wire [0:`PORTS - 1] valid, full;
    

    scratch_pad_gold #(`PORTS, `WIDTH) dut(rst, clk, rd_en, wr_en, d, q, addr, stall, valid, full);
    
    initial begin
        clk = 0;
        forever #5 clk = !clk;
    end
    initial begin
        $monitor(valid[0]);
        rst = 1;
        rd_en = 0;
        wr_en = 0;
        d = 0;
        addr = 0;
        stall = 0;
        #101 rst = 0;
        #100 wr_en[0] = 1;
        d[`PORTS*`WIDTH-1 -: `WIDTH] = 42;
        #10 wr_en = 0;
        #100 rd_en[0] = 1;
        #10 rd_en = 0;
        #100 $finish;

    end
    initial #10000 $finish;
    integer i;
    always @(posedge clk) begin
        for(i = 0; i < 8; i = i + 1)
            if(valid[i])
                $display("read output: %d", q[`PORTS*`WIDTH-1 -: `WIDTH ]);
        for(i = 0; i < 8; i = i + 1) begin
            if(rd_en[i] || wr_en[i])
                $display("using address: %d", addr[`PORTS*`ADDR_WIDTH-1 -: `ADDR_WIDTH ]);
            if(wr_en[i])
                $display("writing: %d", d[`PORTS*`WIDTH - 1 -: `WIDTH]);
        end
    end
    always @(posedge clk) begin
    end
endmodule
module scratch_pad_gold_tb;

    `include "log2.vh"
    `define PORTS 16
    `define WIDTH 64
    `define DEPTH `PORTS*512
    `define ADDR_WIDTH log2(`DEPTH-1)
    reg rst, clk;
    reg [0:`PORTS-1] rd_en, wr_en;
    reg [`PORTS*`WIDTH-1:0] d;
    wire [`PORTS*`WIDTH-1:0] q;
    reg [`PORTS*`ADDR_WIDTH-1:0] addr;
    reg [0:`PORTS-1] stall;
    wire [0:`PORTS - 1] valid, full;
    

    scratch_pad_gold #(`PORTS, `WIDTH) dut(rst, clk, rd_en, wr_en, d, q, addr, stall, valid, full);
    
    initial begin
        clk = 0;
        forever #5 clk = !clk;
    end
    initial begin
        $monitor(valid[0]);
        rst = 1;
        rd_en = 0;
        wr_en = 0;
        d = 0;
        addr = 0;
        stall = 0;
        #101 rst = 0;
        #100 wr_en[0] = 1;
        d[`PORTS*`WIDTH-1 -: `WIDTH] = 42;
        #10 wr_en = 0;
        #100 rd_en[0] = 1;
        #10 rd_en = 0;
        #100 $finish;

    end
    initial #10000 $finish;
    integer i;
    always @(posedge clk) begin
        for(i = 0; i < 8; i = i + 1)
            if(valid[i])
                $display("read output: %d", q[`PORTS*`WIDTH-1 -: `WIDTH ]);
        for(i = 0; i < 8; i = i + 1) begin
            if(rd_en[i] || wr_en[i])
                $display("using address: %d", addr[`PORTS*`ADDR_WIDTH-1 -: `ADDR_WIDTH ]);
            if(wr_en[i])
                $display("writing: %d", d[`PORTS*`WIDTH - 1 -: `WIDTH]);
        end
    end
    always @(posedge clk) begin
    end
endmodule