data/full_repos/permissive/198223683/rtl/video/neo_cmc.v
 line:31: before: "reg"
1: b'%Warning-LITENDIAN: data/full_repos/permissive/198223683/rtl/video/neo_cmc.v:33: Little bit endian vector: MSB < LSB of bit range: 0:79\n reg [0:79] banks;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/198223683/rtl/video/neo_cmc.v:37: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                           : ... In instance neo_cmc\n if(ADDR == \'h7E2 && !PBUS[14:12]) begin\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/198223683/rtl/video/neo_cmc.v:46: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                           : ... In instance neo_cmc\n   if(ADDR[10:8] == 7 && !PBUS[14:12]) begin\n                         ^\n%Error: Exiting due to 3 warning(s)\n'
module neo_cmc
(
	input             PCK2B,
	input      [14:0] PBUS,
	input      [10:0] ADDR,
	input       [1:0] TYPE,
	output reg  [1:0] BANK
);

always @(posedge PCK2B) begin
	reg [10:0] old_addr;
	reg        skip;
	reg [0:79] banks;
	reg  [3:0] map[32];
	reg  [4:0] line;

	if(ADDR == 'h7E2 && !PBUS[14:12]) begin
		skip <= 0;
		line <= 0;
		BANK <= 1;
	end

	old_addr <= ADDR;
	if(old_addr == ADDR) begin
		if(TYPE[0]) begin
			if(ADDR[10:8] == 7 && !PBUS[14:12]) begin
				if(&map[line][3:2] && ~skip) begin
					BANK <= map[line][1:0];
					skip <= 1;
				end
				else begin
					line <= line + 1'd1;
					skip <= 0;
				end
			end


			if ({ADDR[6],ADDR[0],ADDR[10:8]} == 5) begin
				if(ADDR[7]) map[ADDR[5:1]][2:0] <= {&PBUS[11:8], ~PBUS[1:0]};
				       else map[ADDR[5:1]][3]   <= (PBUS[11:0] == 'h200);
			end
		end

		if(TYPE[1]) begin

			if(ADDR[10:8] == 5 && &PBUS[14:12]) banks[{1'b0,ADDR[7:5],3'b000}+{2'b00,ADDR[7:5],2'b00} +:12] <= ~PBUS[11:0];
			BANK <= banks[{ADDR[10:5],1'b0} +:2];
		end
	end

	if(~^TYPE) BANK <= 0;
end

endmodule
module neo_cmc
(
	input             PCK2B,
	input      [14:0] PBUS,
	input      [10:0] ADDR,
	input       [1:0] TYPE,
	output reg  [1:0] BANK
);


always @(posedge PCK2B) begin
	reg [10:0] old_addr;
	reg        skip;
	reg [0:79] banks;
	reg  [3:0] map[32];
	reg  [4:0] line;

	if(ADDR == 'h7E2 && !PBUS[14:12]) begin
		skip <= 0;
		line <= 0;
		BANK <= 1;
	end

	old_addr <= ADDR;
	if(old_addr == ADDR) begin
		if(TYPE[0]) begin
			if(ADDR[10:8] == 7 && !PBUS[14:12]) begin
				if(&map[line][3:2] && ~skip) begin
					BANK <= map[line][1:0];
					skip <= 1;
				end
				else begin
					line <= line + 1'd1;
					skip <= 0;
				end
			end


			if ({ADDR[6],ADDR[0],ADDR[10:8]} == 5) begin
				if(ADDR[7]) map[ADDR[5:1]][2:0] <= {&PBUS[11:8], ~PBUS[1:0]};
				       else map[ADDR[5:1]][3]   <= (PBUS[11:0] == 'h200);
			end
		end

		if(TYPE[1]) begin

			if(ADDR[10:8] == 5 && &PBUS[14:12]) banks[{1'b0,ADDR[7:5],3'b000}+{2'b00,ADDR[7:5],2'b00} +:12] <= ~PBUS[11:0];
			BANK <= banks[{ADDR[10:5],1'b0} +:2];
		end
	end

	if(~^TYPE) BANK <= 0;
end

endmodule