data/full_repos/permissive/152883307/Project/AD7928.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152883307/Project/AD7928.v:61: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'idx\' generates 1 bits.\n                                                                        : ... In instance AD7928\n       ad7928_reg_out[11:9] = idx;      \n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/152883307/Project/AD7928.v:67: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 15 bits.\n                                                                        : ... In instance AD7928\n       ad7928_din = (ad7928_reg_out >> rout_no) & 1;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152883307/Project/AD7928.v:78: Operator OR expects 15 bits on the RHS, but RHS\'s VARREF \'ad7928_dout\' generates 1 bits.\n                                                                        : ... In instance AD7928\n       ad7928_reg_in = ad7928_reg_in | ad7928_dout;\n                                     ^\n%Error: Exiting due to 3 warning(s)\n'
module AD7928(
	input 				Clock_in,
	input 				rstn,
	output reg 			ad7928_sclk,
	output reg 			ad7928_din,
	output reg 			ad7928_csn,
	input 				ad7928_dout, 

	output reg [11:0]	vin0,
	output reg [11:0]	vin1






	);

reg [14:0] ad7928_reg_in;
reg [14:0] ad7928_reg_out; 


reg [7:0] seq;
reg [3:0] rout_no, rin_no;
reg 		 idx;


always@(negedge Clock_in or negedge rstn) 
begin
	if (!rstn)
		begin
			vin0 = 0;
			vin1 = 0;






			idx = 0;
			seq = 0;
			ad7928_csn = 1;
			ad7928_sclk = 1;
			ad7928_din = 1;

			ad7928_reg_out = 15'b100_0001_1000_1000;
		end
	else 
		begin
				case (seq)
					0:	begin
							ad7928_csn = 0; 
							ad7928_reg_out = 15'b100_0001_1000_1000;
							ad7928_reg_out[11:9] = idx;
							rout_no = 14;
							rin_no = 0;
							seq = seq + 1;
						end
					1: begin
							ad7928_din = (ad7928_reg_out >> rout_no) & 1;
							rout_no = rout_no - 1;
							seq = seq + 1;
						end
					2: begin
							ad7928_sclk = 0;
							seq = seq + 1;
						end
					3: begin
							ad7928_sclk = 1;
							ad7928_reg_in = (ad7928_reg_in << 1);
							ad7928_reg_in = ad7928_reg_in | ad7928_dout;
							rin_no = rin_no + 1;
						if (rin_no > 14) 
                        seq = seq + 1;
						else 
								seq = 1;
						end
					4: begin
							ad7928_sclk = 0;
							seq = seq + 1;
						end
					5: begin
							ad7928_sclk = 1;
							seq = seq + 1;
                end
					6:	begin
							ad7928_csn = 1;
							seq = seq + 1;
						end
					7: begin
							case (ad7928_reg_in[14:12])
							0: begin
									vin0 = ad7928_reg_in[11:0];

								end
							1:	begin 

									vin1 = ad7928_reg_in[11:0];
								end






                     endcase
                     idx = idx + 1;
							seq = 0; 
						end
				endcase

      end
end




endmodule
module AD7928(
	input 				Clock_in,
	input 				rstn,
	output reg 			ad7928_sclk,
	output reg 			ad7928_din,
	output reg 			ad7928_csn,
	input 				ad7928_dout, 

	output reg [11:0]	vin0,
	output reg [11:0]	vin1






	);


reg [14:0] ad7928_reg_in;
reg [14:0] ad7928_reg_out; 


reg [7:0] seq;
reg [3:0] rout_no, rin_no;
reg 		 idx;


always@(negedge Clock_in or negedge rstn) 
begin
	if (!rstn)
		begin
			vin0 = 0;
			vin1 = 0;






			idx = 0;
			seq = 0;
			ad7928_csn = 1;
			ad7928_sclk = 1;
			ad7928_din = 1;

			ad7928_reg_out = 15'b100_0001_1000_1000;
		end
	else 
		begin
				case (seq)
					0:	begin
							ad7928_csn = 0; 
							ad7928_reg_out = 15'b100_0001_1000_1000;
							ad7928_reg_out[11:9] = idx;
							rout_no = 14;
							rin_no = 0;
							seq = seq + 1;
						end
					1: begin
							ad7928_din = (ad7928_reg_out >> rout_no) & 1;
							rout_no = rout_no - 1;
							seq = seq + 1;
						end
					2: begin
							ad7928_sclk = 0;
							seq = seq + 1;
						end
					3: begin
							ad7928_sclk = 1;
							ad7928_reg_in = (ad7928_reg_in << 1);
							ad7928_reg_in = ad7928_reg_in | ad7928_dout;
							rin_no = rin_no + 1;
						if (rin_no > 14) 
                        seq = seq + 1;
						else 
								seq = 1;
						end
					4: begin
							ad7928_sclk = 0;
							seq = seq + 1;
						end
					5: begin
							ad7928_sclk = 1;
							seq = seq + 1;
                end
					6:	begin
							ad7928_csn = 1;
							seq = seq + 1;
						end
					7: begin
							case (ad7928_reg_in[14:12])
							0: begin
									vin0 = ad7928_reg_in[11:0];

								end
							1:	begin 

									vin1 = ad7928_reg_in[11:0];
								end






                     endcase
                     idx = idx + 1;
							seq = 0; 
						end
				endcase

      end
end




endmodule