data/full_repos/permissive/143278/ivltests/pr1833754.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1833754.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #1 count2 = 4;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1833754.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #1 count2 = 5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1833754.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #1 count2 = 6;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1833754.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #1 count2 = 7;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1833754.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1 count = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1833754.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1 count = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1833754.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #1 count = 2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1833754.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #1 count = 3;\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1833754.v:16: Duplicate declaration of block: \'block1\'\ninitial begin:block1\n              ^~~~~~\n        data/full_repos/permissive/143278/ivltests/pr1833754.v:10: ... Location of original declaration\n    begin:block1\n          ^~~~~~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module duplicate_names();

localparam up = 1;

generate
  if (up)
    begin:block1
      wire [2:0] count1;
      count_up   counter(count1);
    end
endgenerate

initial begin:block1
  reg [2:0] count2;

  #1 count2 = 4;
  #1 count2 = 5;
  #1 count2 = 6;
  #1 count2 = 7;
end

endmodule
module duplicate_names();


localparam up = 1;

generate
  if (up)
    begin:block1
      wire [2:0] count1;
      count_up   counter(count1);
    end
endgenerate

initial begin:block1
  reg [2:0] count2;

  #1 count2 = 4;
  #1 count2 = 5;
  #1 count2 = 6;
  #1 count2 = 7;
end

endmodule