data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:44: Operator ADD expects 5 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n out =  in[0]  + in[1]  + in[2]  + in[3] + \n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:44: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n out =  in[0]  + in[1]  + in[2]  + in[3] + \n               ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:44: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n out =  in[0]  + in[1]  + in[2]  + in[3] + \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:44: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n out =  in[0]  + in[1]  + in[2]  + in[3] + \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:44: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n out =  in[0]  + in[1]  + in[2]  + in[3] + \n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:45: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[4]  + in[5]  + in[6]  + in[7] + \n          ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:45: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[4]  + in[5]  + in[6]  + in[7] + \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:45: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[4]  + in[5]  + in[6]  + in[7] + \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:45: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[4]  + in[5]  + in[6]  + in[7] + \n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:46: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[8]  + in[9]  + in[10] + in[11] + \n          ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:46: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[8]  + in[9]  + in[10] + in[11] + \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:46: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[8]  + in[9]  + in[10] + in[11] + \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:46: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[8]  + in[9]  + in[10] + in[11] + \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:47: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[12] + in[13] + in[14] + in[15] + \n          ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:47: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[12] + in[13] + in[14] + in[15] + \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:47: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[12] + in[13] + in[14] + in[15] + \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:47: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[12] + in[13] + in[14] + in[15] + \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:48: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[16] + in[17] + in[18] + in[19] + \n          ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:48: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[16] + in[17] + in[18] + in[19] + \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:48: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[16] + in[17] + in[18] + in[19] + \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:48: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[16] + in[17] + in[18] + in[19] + \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:49: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[20] + in[21] + in[22] + in[23] + \n          ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:49: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[20] + in[21] + in[22] + in[23] + \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:49: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[20] + in[21] + in[22] + in[23] + \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:49: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[20] + in[21] + in[22] + in[23] + \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:50: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[24] + in[25] + in[26] + in[27] + \n          ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:50: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[24] + in[25] + in[26] + in[27] + \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:50: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[24] + in[25] + in[26] + in[27] + \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:50: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[24] + in[25] + in[26] + in[27] + \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:51: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[28] + in[29] + in[30];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/bit_accumlator.v:51: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                        : ... In instance bit_accumlator\n   in[28] + in[29] + in[30];\n                   ^\n%Error: Exiting due to 31 warning(s)\n'
module bit_accumlator(in, out);

input	[30:0]	in;
output	[4:0]	out;
reg		[4:0]	out;

always @ *
begin
	out	= 	in[0]  + in[1]  + in[2]  + in[3] + 
			in[4]  + in[5]  + in[6]  + in[7] + 
			in[8]  + in[9]  + in[10] + in[11] + 
			in[12] + in[13] + in[14] + in[15] + 
			in[16] + in[17] + in[18] + in[19] + 
			in[20] + in[21] + in[22] + in[23] + 
			in[24] + in[25] + in[26] + in[27] + 
			in[28] + in[29] + in[30];
end

endmodule
module bit_accumlator(in, out);


input	[30:0]	in;
output	[4:0]	out;
reg		[4:0]	out;

always @ *
begin
	out	= 	in[0]  + in[1]  + in[2]  + in[3] + 
			in[4]  + in[5]  + in[6]  + in[7] + 
			in[8]  + in[9]  + in[10] + in[11] + 
			in[12] + in[13] + in[14] + in[15] + 
			in[16] + in[17] + in[18] + in[19] + 
			in[20] + in[21] + in[22] + in[23] + 
			in[24] + in[25] + in[26] + in[27] + 
			in[28] + in[29] + in[30];
end

endmodule