data/full_repos/permissive/16591284/fifo_with_bram/fifo.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:32: Unsupported: Ignoring delay on this delayed statement.\n    forever #(5) CLK = ~CLK;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Error: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:40: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile(VCD);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:41: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, fifo);\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FIFO #(parameter               WIDTH = 32,
              parameter               DEPTH = 4,
              parameter               W_CNT = 3,
              parameter               W_POS = 2)
             (input  wire             CLK, 
              input  wire             RST_X, 
              input  wire             ENQ, 
              input  wire             DEQ, 
              input  wire [WIDTH-1:0] DIN, 
              output wire [WIDTH-1:0] DOUT, 
              output wire             EMPTY, 
              output wire             FULL);
  
  reg [W_CNT-1:0] cnt;
  reg [W_POS-1:0] head;
  reg [W_POS-1:0] tail;
  reg             dout_en;
  
  wire             re = DEQ && !EMPTY;
  wire             we = ENQ && !FULL;
  wire [WIDTH-1:0] dout;
  
  FIFO_RAM #(.WIDTH(WIDTH), .DEPTH(DEPTH), .W_POS(W_POS))
  fifo_ram(CLK, we, head, tail, DIN, dout);
  
  assign DOUT  = (dout_en) ? dout : 0;
  assign EMPTY = (cnt == 0);
  assign FULL  = (cnt == DEPTH);

  always @(posedge CLK) begin
    if (!RST_X) begin
      cnt     <= 0;
      head    <= 0;
      tail    <= 0;
      dout_en <= 0;
    end else begin
      if (we) tail <= (tail == DEPTH-1) ? 0 : tail+1;
      if (re) head <= (head == DEPTH-1) ? 0 : head+1;
      if (we && re) cnt <= cnt;
      else if (we)  cnt <= cnt + 1;
      else if (re)  cnt <= cnt - 1;
      dout_en <= re;
    end
  end
endmodule
module FIFO #(parameter               WIDTH = 32,
              parameter               DEPTH = 4,
              parameter               W_CNT = 3,
              parameter               W_POS = 2)
             (input  wire             CLK, 
              input  wire             RST_X, 
              input  wire             ENQ, 
              input  wire             DEQ, 
              input  wire [WIDTH-1:0] DIN, 
              output wire [WIDTH-1:0] DOUT, 
              output wire             EMPTY, 
              output wire             FULL);

  
  reg [W_CNT-1:0] cnt;
  reg [W_POS-1:0] head;
  reg [W_POS-1:0] tail;
  reg             dout_en;
  
  wire             re = DEQ && !EMPTY;
  wire             we = ENQ && !FULL;
  wire [WIDTH-1:0] dout;
  
  FIFO_RAM #(.WIDTH(WIDTH), .DEPTH(DEPTH), .W_POS(W_POS))
  fifo_ram(CLK, we, head, tail, DIN, dout);
  
  assign DOUT  = (dout_en) ? dout : 0;
  assign EMPTY = (cnt == 0);
  assign FULL  = (cnt == DEPTH);

  always @(posedge CLK) begin
    if (!RST_X) begin
      cnt     <= 0;
      head    <= 0;
      tail    <= 0;
      dout_en <= 0;
    end else begin
      if (we) tail <= (tail == DEPTH-1) ? 0 : tail+1;
      if (re) head <= (head == DEPTH-1) ? 0 : head+1;
      if (we && re) cnt <= cnt;
      else if (we)  cnt <= cnt + 1;
      else if (re)  cnt <= cnt - 1;
      dout_en <= re;
    end
  end
endmodule