data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/regfile.v
data/verilator_xmls/34d9918d-163d-48c8-bfc4-3e50b97d930d.xml
module regfile(
    input clk,
    input we3,
    input [4:0] ra1,ra2,wa3,
    input [31:0] wd3,
    output [31:0] rd1,rd2,
    input [4:0] sw,
    output reg [31:0] t
    );
    
    reg [31:0] rf[31:0];
    
    always@(negedge clk)
    if(we3)
        rf[wa3]<=wd3;
        

    assign rd1=(ra1!=0)?rf[ra1]:0;
    assign rd2=(ra2!=0)?rf[ra2]:0;
    

    always@(*)
        t<=rf[sw];
    
endmodule
module regfile(
    input clk,
    input we3,
    input [4:0] ra1,ra2,wa3,
    input [31:0] wd3,
    output [31:0] rd1,rd2,
    input [4:0] sw,
    output reg [31:0] t
    );

    
    reg [31:0] rf[31:0];
    
    always@(negedge clk)
    if(we3)
        rf[wa3]<=wd3;
        

    assign rd1=(ra1!=0)?rf[ra1]:0;
    assign rd2=(ra2!=0)?rf[ra2]:0;
    

    always@(*)
        t<=rf[sw];
    
endmodule