data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_reg_ro.v
 line:74: before: "integer"
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_reg_ro.v:101: syntax error, unexpected '(', expecting IDENTIFIER\n    WIDTH_must_be_at_least_1();\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_reg_ro.v:106: syntax error, unexpected '(', expecting IDENTIFIER\n    ADDR_must_be_aligned_to_the_size_of_the_register();\n                                                     ^\n%Error: Exiting due to 2 error(s)\n"
module ctrlport_reg_ro #(
  parameter [   19:0] ADDR     = 0,
  parameter           WIDTH    = 32,
  parameter           COHERENT = 0
) (
  input wire ctrlport_clk,

  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  output reg         s_ctrlport_resp_ack,
  output wire [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,

  input wire [WIDTH-1:0] value_in
);





  function automatic integer max(input integer a, b);
    max = a > b ? a : b;
  endfunction








  localparam NUM_BYTES = max(4, 2**$clog2(WIDTH) / 8);


  localparam BYTE_ADDR_W = $clog2(NUM_BYTES);



  localparam WORD_ADDR_W = BYTE_ADDR_W-2;







  if (WIDTH < 1) begin
    WIDTH_must_be_at_least_1();
  end


  if (ADDR[BYTE_ADDR_W-1:0] != 0) begin
    ADDR_must_be_aligned_to_the_size_of_the_register();
  end







  reg [NUM_BYTES*8-1:0] reg_val = 0;

  always @(*) begin
    reg_val            <= 0;
    reg_val[WIDTH-1:0] <= value_in;
  end






  reg [WIDTH-1:0] cache_reg;

  assign s_ctrlport_resp_status = 0;




  if (WIDTH > 32 && COHERENT) begin : gen_coherent




    always @(posedge ctrlport_clk) begin

      if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
        s_ctrlport_resp_ack  <= 1'b1;


        if (s_ctrlport_req_addr[BYTE_ADDR_W-1 : 2] == 0) begin
          s_ctrlport_resp_data <= reg_val[31:0];
          cache_reg            <= reg_val;


        end else begin
          s_ctrlport_resp_data <= cache_reg[s_ctrlport_req_addr[2 +: WORD_ADDR_W]*32 +: 32];
        end
      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end




  end else begin : gen_no_coherent



    always @(posedge ctrlport_clk) begin

      if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
        s_ctrlport_resp_ack  <= 1'b1;
        if (WORD_ADDR_W > 0) begin

          s_ctrlport_resp_data <= reg_val[s_ctrlport_req_addr[2 +: WORD_ADDR_W]*32 +: 32];
        end else begin
          s_ctrlport_resp_data <= reg_val;
        end
      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end
   
endmodule
module ctrlport_reg_ro #(
  parameter [   19:0] ADDR     = 0,
  parameter           WIDTH    = 32,
  parameter           COHERENT = 0
) (
  input wire ctrlport_clk,

  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  output reg         s_ctrlport_resp_ack,
  output wire [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,

  input wire [WIDTH-1:0] value_in
);






  function automatic integer max(input integer a, b);
    max = a > b ? a : b;
  endfunction








  localparam NUM_BYTES = max(4, 2**$clog2(WIDTH) / 8);


  localparam BYTE_ADDR_W = $clog2(NUM_BYTES);



  localparam WORD_ADDR_W = BYTE_ADDR_W-2;







  if (WIDTH < 1) begin
    WIDTH_must_be_at_least_1();
  end


  if (ADDR[BYTE_ADDR_W-1:0] != 0) begin
    ADDR_must_be_aligned_to_the_size_of_the_register();
  end







  reg [NUM_BYTES*8-1:0] reg_val = 0;

  always @(*) begin
    reg_val            <= 0;
    reg_val[WIDTH-1:0] <= value_in;
  end






  reg [WIDTH-1:0] cache_reg;

  assign s_ctrlport_resp_status = 0;




  if (WIDTH > 32 && COHERENT) begin : gen_coherent




    always @(posedge ctrlport_clk) begin

      if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
        s_ctrlport_resp_ack  <= 1'b1;


        if (s_ctrlport_req_addr[BYTE_ADDR_W-1 : 2] == 0) begin
          s_ctrlport_resp_data <= reg_val[31:0];
          cache_reg            <= reg_val;


        end else begin
          s_ctrlport_resp_data <= cache_reg[s_ctrlport_req_addr[2 +: WORD_ADDR_W]*32 +: 32];
        end
      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end




  end else begin : gen_no_coherent



    always @(posedge ctrlport_clk) begin

      if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
        s_ctrlport_resp_ack  <= 1'b1;
        if (WORD_ADDR_W > 0) begin

          s_ctrlport_resp_data <= reg_val[s_ctrlport_req_addr[2 +: WORD_ADDR_W]*32 +: 32];
        end else begin
          s_ctrlport_resp_data <= reg_val;
        end
      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end
   
endmodule