data/full_repos/permissive/2047449/pram_sram_ctrl_a.v
 line:121: before: ";"
1: b'%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:26: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'START\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n   state <= START;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:41: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ADDROUT\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n      state <= ADDROUT;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:44: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'START\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n     state <= START;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:49: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATAOUT\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n    state <= DATAOUT;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:55: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'WRITE\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n    state <= WRITE;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:61: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TEST1\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n    state <= TEST1;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:69: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'HALT\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n     state <= HALT;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:75: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_AND_GO\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n        state <= WAIT_AND_GO;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:79: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ADDROUT\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n       state <= ADDROUT;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:87: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_AND_GO\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n     state <= WAIT_AND_GO;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:89: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'READ\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n     state <= READ;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:97: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TEST2\' generates 4 bits.\n                                                                        : ... In instance sram_ctrl_a\n      state <= TEST2;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:101: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'READ\' generates 4 bits.\n                                                                         : ... In instance sram_ctrl_a\n     state <= READ;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:110: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'START\' generates 4 bits.\n                                                                         : ... In instance sram_ctrl_a\n      state <= START;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:113: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_AND_GO\' generates 4 bits.\n                                                                         : ... In instance sram_ctrl_a\n     state <= WAIT_AND_GO;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:118: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'HALT\' generates 4 bits.\n                                                                         : ... In instance sram_ctrl_a\n    state <= HALT;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/2047449/pram_sram_ctrl_a.v:33: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 3 bits.\n                                                                        : ... In instance sram_ctrl_a\n  case(state)\n  ^~~~\n%Error: Exiting due to 17 warning(s)\n'
module sram_ctrl_a(
	input clk,
	input clr,
	input go,
	input halt,
	output reg we,
	output [17:0] sram_addr,
	output [2:0] pattern,
	output reg en
);

reg[2:0] state;
parameter START = 4'b0000, ADDROUT = 4'b0001, DATAOUT = 4'b0010,
	WRITE = 4'b0011, TEST1 = 4'b0100, WAIT_AND_GO = 4'b0101, READ = 4'b0110,
	TEST2 = 4'b0111, HALT = 4'b1000;
reg [17:0] addrv;
reg [2:0] patternv;

assign sram_addr = addrv;
assign pattern = patternv;

always @(posedge clk or posedge clr)
begin
	if (clr == 1)
		begin
			state <= START;
			addrv = 0;
			patternv = 0;
			we <= 1;
			en <= 0;
		end
	else
		case(state)
			START:
			begin
				we <= 1;
				if (go == 1)
					begin
						addrv = 0;
						en <= 1;
						state <= ADDROUT;
					end
				else
					state <= START;
			end
			
			ADDROUT:
			begin
				state <= DATAOUT;
				we <= 1;
			end
			
			DATAOUT:
			begin
				state <= WRITE;
				we <= 0;
			end
			
			WRITE:
			begin
				state <= TEST1;
				we <= 1;
			end
			
			TEST1:
			begin
				we <= 1;
				if (halt == 1)
					state <= HALT;
				else
					begin
						addrv = addrv + 1;
						if (addrv == 0)
							begin
								state <= WAIT_AND_GO;
								en <= 0;
							end
						else
							state <= ADDROUT;
					end
			end
			
			WAIT_AND_GO:
			begin
				we <= 1;
				if (go == 1)
					state <= WAIT_AND_GO;
				else
					state <= READ;
			end
			
			READ:
			begin
				we <= 1;
				if (go == 1)
					begin
						state <= TEST2;
						addrv = addrv + 1;
					end
				else
					state <= READ;
			end
			
			TEST2:
			begin
				we <= 1;
				if (addrv == 0)
					begin
						patternv = patternv + 1;
						state <= START;
					end
				else
					state <= WAIT_AND_GO;
			end
			
			HALT:
			begin
				state <= HALT;
			end
			
			default;
		endcase
end

endmodule
module sram_ctrl_a(
	input clk,
	input clr,
	input go,
	input halt,
	output reg we,
	output [17:0] sram_addr,
	output [2:0] pattern,
	output reg en
);


reg[2:0] state;
parameter START = 4'b0000, ADDROUT = 4'b0001, DATAOUT = 4'b0010,
	WRITE = 4'b0011, TEST1 = 4'b0100, WAIT_AND_GO = 4'b0101, READ = 4'b0110,
	TEST2 = 4'b0111, HALT = 4'b1000;
reg [17:0] addrv;
reg [2:0] patternv;

assign sram_addr = addrv;
assign pattern = patternv;

always @(posedge clk or posedge clr)
begin
	if (clr == 1)
		begin
			state <= START;
			addrv = 0;
			patternv = 0;
			we <= 1;
			en <= 0;
		end
	else
		case(state)
			START:
			begin
				we <= 1;
				if (go == 1)
					begin
						addrv = 0;
						en <= 1;
						state <= ADDROUT;
					end
				else
					state <= START;
			end
			
			ADDROUT:
			begin
				state <= DATAOUT;
				we <= 1;
			end
			
			DATAOUT:
			begin
				state <= WRITE;
				we <= 0;
			end
			
			WRITE:
			begin
				state <= TEST1;
				we <= 1;
			end
			
			TEST1:
			begin
				we <= 1;
				if (halt == 1)
					state <= HALT;
				else
					begin
						addrv = addrv + 1;
						if (addrv == 0)
							begin
								state <= WAIT_AND_GO;
								en <= 0;
							end
						else
							state <= ADDROUT;
					end
			end
			
			WAIT_AND_GO:
			begin
				we <= 1;
				if (go == 1)
					state <= WAIT_AND_GO;
				else
					state <= READ;
			end
			
			READ:
			begin
				we <= 1;
				if (go == 1)
					begin
						state <= TEST2;
						addrv = addrv + 1;
					end
				else
					state <= READ;
			end
			
			TEST2:
			begin
				we <= 1;
				if (addrv == 0)
					begin
						patternv = patternv + 1;
						state <= START;
					end
				else
					state <= WAIT_AND_GO;
			end
			
			HALT:
			begin
				state <= HALT;
			end
			
			default;
		endcase
end

endmodule