data/full_repos/permissive/112626266/our_top_module.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:6: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/112626266/our_top_module.v:75: Cannot find file containing module: \'PC\'\n PC pc1(clk , next_PC , PCWrite , current_PC);\n ^~\n        ... Looked in:\n             data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC\n             data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.v\n             data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.sv\n             PC\n             PC.v\n             PC.sv\n             obj_dir/PC\n             obj_dir/PC.v\n             obj_dir/PC.sv\n%Error: data/full_repos/permissive/112626266/our_top_module.v:80: Cannot find file containing module: \'Instruction_Memory\'\n Instruction_Memory imem(current_PC , Instruction, addent);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:87: Cannot find file containing module: \'IFID\'\n IFID IFID1(clk , Instruction ,IFIDWrite , PC_from_Adder , Instruction_to_ID , PC_from_Adder_to_ID);\n ^~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:121: Cannot find file containing module: \'decode\'\n decode d1(clk , WBRegRd , WBreg2 , M , EXRegRt , Write_Data , PC_from_Adder_to_ID , Instruction_to_ID ,\n ^~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:176: Cannot find file containing module: \'EXMEM\'\n EXMEM emem1(clk,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:192: Cannot find file containing module: \'Data_Memory\'\n Data_Memory dm1(.Clock(clk) , .Address(ALUreg) , .Write_Data(WriteDataOut) , .MemWrite(MemWrite) , .MemRead(MemRead) , \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:217: Cannot find file containing module: \'MEMWB\'\n MEMWB mwb(.clock(clk) , .WB(WBreg) , .Memout(Read_Data) , .ALUOut(ALUreg) , .RegRD(RegRDreg) , \n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:223: Cannot find file containing module: \'ExBrunch\'\n ExBrunch EXBranch(.clock(clk),.datatowrite(Write_Data),.MEMALUOut(ALUreg),.DEXWB(DecodeWB) ,.DEXM(DecodeM),.DEXEX(EX),\n ^~~~~~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_mod;


	wire clk;
	Clock c1(clk);


















	wire Branch_Control;
	wire Branch_Taken;
	wire PC_selector;
	and(PC_selector , Branch_Control , Branch_Taken);


	wire[31:0] PC_from_Branch;
	wire[31:0] PC_from_Adder;
	wire[31:0] next_PC;

	MUX pc_mux(PC_selector , PC_from_Branch , PC_from_Adder , next_PC);




	wire PCWrite;
	wire[31:0] current_PC;
	PC pc1(clk , next_PC , PCWrite , current_PC);


	wire[31:0] Instruction;
    wire [31:0] addent;
	Instruction_Memory imem(current_PC , Instruction, addent);

	Adder normal_pc_adder(current_PC , addent , PC_from_Adder);


	wire IFIDWrite;
	wire[31:0] Instruction_to_ID , PC_from_Adder_to_ID;
	IFID IFID1(clk , Instruction ,IFIDWrite , PC_from_Adder , Instruction_to_ID , PC_from_Adder_to_ID);















    wire [2:0] M;
	wire [4:0]EXRegRt;


	wire [4:0]WBRegRd;
	wire [31:0] Write_Data;
  
	wire [1:0]DecodeWB;
	wire [2:0]DecodeM;
	wire [3:0]EX;
	wire [4:0]IDRegRs,IDRegRt,IDRegRd;
	wire [31:0]DataA,DataB,imm_value;




	wire     [1:0]   WBreg2;

	decode d1(clk , WBRegRd , WBreg2 , M , EXRegRt , Write_Data , PC_from_Adder_to_ID , Instruction_to_ID ,
		DecodeWB , DecodeM , EX , IDRegRs , IDRegRt , IDRegRd , DataA , DataB, imm_value ,
		PC_from_Branch , Branch_Taken , Branch_Control , PCWrite , IFIDWrite);











	





    wire [1:0] WB;

 

















	wire           [4:0]   RegRD;
	wire           [31:0]  ALUOut,WriteDataIn;



	wire     [1:0]   WBreg;
	wire     [2:0]   Mreg;
	wire     [31:0]  ALUreg,WriteDataOut;
	wire     [4:0]   RegRDreg;



	EXMEM emem1(clk,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);







	wire MemWrite; assign MemWrite = Mreg[0:0];
	wire MemRead; assign MemRead = Mreg[1:1];
	

	wire[31:0] Read_Data;
	

	
	Data_Memory dm1(.Clock(clk) , .Address(ALUreg) , .Write_Data(WriteDataOut) , .MemWrite(MemWrite) , .MemRead(MemRead) , 
			.Read_Data(Read_Data));
	

	





	
	


	


	


	wire     [31:0]  Memreg2,ALUreg2;



	
	MEMWB mwb(.clock(clk) , .WB(WBreg) , .Memout(Read_Data) , .ALUOut(ALUreg) , .RegRD(RegRDreg) , 
		  .WBreg(WBreg2) , .Memreg(Memreg2) , .ALUreg(ALUreg2) , .RegRDreg(WBRegRd));
	
	


 ExBrunch EXBranch(.clock(clk),.datatowrite(Write_Data),.MEMALUOut(ALUreg),.DEXWB(DecodeWB) ,.DEXM(DecodeM),.DEXEX(EX),
.DEXRegRs(IDRegRs),.DEXRegRt(IDRegRt),.DEXRegRd(IDRegRd),.DEXDataA(DataA),.DEXDataB(DataB),
.DEXimm_value(imm_value),.EXMEMRegRd(RegRDreg),.MEMWBRegRd(WBRegRd),.EXMEM_RegWrite(WBreg),.MEMWB_RegWrite(WBreg2),
.EXMWB(WB),.EXMM(M),.EXALUOut(ALUOut),.regtopass(RegRD),.EXMWriteDataIn(WriteDataIn), .RtReg(EXRegRt));




	wire MemtoReg; assign MemtoReg = WBreg2[1];

	





	
	MUX m1(.MemtoReg(MemtoReg) , .Read_Data(Memreg2) , .ALU_Result(ALUreg2) , .Write_Data(Write_Data));
	

	
	
	


	
endmodule
module top_mod;



	wire clk;
	Clock c1(clk);


















	wire Branch_Control;
	wire Branch_Taken;
	wire PC_selector;
	and(PC_selector , Branch_Control , Branch_Taken);


	wire[31:0] PC_from_Branch;
	wire[31:0] PC_from_Adder;
	wire[31:0] next_PC;

	MUX pc_mux(PC_selector , PC_from_Branch , PC_from_Adder , next_PC);




	wire PCWrite;
	wire[31:0] current_PC;
	PC pc1(clk , next_PC , PCWrite , current_PC);


	wire[31:0] Instruction;
    wire [31:0] addent;
	Instruction_Memory imem(current_PC , Instruction, addent);

	Adder normal_pc_adder(current_PC , addent , PC_from_Adder);


	wire IFIDWrite;
	wire[31:0] Instruction_to_ID , PC_from_Adder_to_ID;
	IFID IFID1(clk , Instruction ,IFIDWrite , PC_from_Adder , Instruction_to_ID , PC_from_Adder_to_ID);















    wire [2:0] M;
	wire [4:0]EXRegRt;


	wire [4:0]WBRegRd;
	wire [31:0] Write_Data;
  
	wire [1:0]DecodeWB;
	wire [2:0]DecodeM;
	wire [3:0]EX;
	wire [4:0]IDRegRs,IDRegRt,IDRegRd;
	wire [31:0]DataA,DataB,imm_value;




	wire     [1:0]   WBreg2;

	decode d1(clk , WBRegRd , WBreg2 , M , EXRegRt , Write_Data , PC_from_Adder_to_ID , Instruction_to_ID ,
		DecodeWB , DecodeM , EX , IDRegRs , IDRegRt , IDRegRd , DataA , DataB, imm_value ,
		PC_from_Branch , Branch_Taken , Branch_Control , PCWrite , IFIDWrite);











	





    wire [1:0] WB;

 

















	wire           [4:0]   RegRD;
	wire           [31:0]  ALUOut,WriteDataIn;



	wire     [1:0]   WBreg;
	wire     [2:0]   Mreg;
	wire     [31:0]  ALUreg,WriteDataOut;
	wire     [4:0]   RegRDreg;



	EXMEM emem1(clk,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);







	wire MemWrite; assign MemWrite = Mreg[0:0];
	wire MemRead; assign MemRead = Mreg[1:1];
	

	wire[31:0] Read_Data;
	

	
	Data_Memory dm1(.Clock(clk) , .Address(ALUreg) , .Write_Data(WriteDataOut) , .MemWrite(MemWrite) , .MemRead(MemRead) , 
			.Read_Data(Read_Data));
	

	





	
	


	


	


	wire     [31:0]  Memreg2,ALUreg2;



	
	MEMWB mwb(.clock(clk) , .WB(WBreg) , .Memout(Read_Data) , .ALUOut(ALUreg) , .RegRD(RegRDreg) , 
		  .WBreg(WBreg2) , .Memreg(Memreg2) , .ALUreg(ALUreg2) , .RegRDreg(WBRegRd));
	
	


 ExBrunch EXBranch(.clock(clk),.datatowrite(Write_Data),.MEMALUOut(ALUreg),.DEXWB(DecodeWB) ,.DEXM(DecodeM),.DEXEX(EX),
.DEXRegRs(IDRegRs),.DEXRegRt(IDRegRt),.DEXRegRd(IDRegRd),.DEXDataA(DataA),.DEXDataB(DataB),
.DEXimm_value(imm_value),.EXMEMRegRd(RegRDreg),.MEMWBRegRd(WBRegRd),.EXMEM_RegWrite(WBreg),.MEMWB_RegWrite(WBreg2),
.EXMWB(WB),.EXMM(M),.EXALUOut(ALUOut),.regtopass(RegRD),.EXMWriteDataIn(WriteDataIn), .RtReg(EXRegRt));




	wire MemtoReg; assign MemtoReg = WBreg2[1];

	





	
	MUX m1(.MemtoReg(MemtoReg) , .Read_Data(Memreg2) , .ALU_Result(ALUreg2) , .Write_Data(Write_Data));
	

	
	
	


	
endmodule