data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v:49: Unsupported: Ignoring delay on this delayed statement.\n         #0 ;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v:51: Unsupported: Ignoring delay on this delayed statement.\n         # initDelay ;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v:55: Unsupported: Ignoring delay on this delayed statement.\n               # v1Width ;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v:57: Unsupported: Ignoring delay on this delayed statement.\n               # v2Width ;\n               ^\n%Warning-INFINITELOOP: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v:52: Infinite loop (condition always true)\n                                                                                                    : ... In instance ClockGen\n         forever\n         ^~~~~~~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ClockGen(CLK_OUT);

   parameter v1Width = 5;
   parameter v2Width  = 5;
   parameter initDelay = 5;
   parameter initValue = 1'b0;
   parameter otherValue = 1'b1 ;

   output    CLK_OUT ;
   reg       CLK_OUT ;





   initial
      begin : clock_loop
         #0 ;
         CLK_OUT = initValue ;
         # initDelay ;
         forever
            begin
               CLK_OUT = otherValue ;
               # v1Width ;
               CLK_OUT = initValue ;
               # v2Width ;

            end
      end


   initial
     begin : parameter_assertions
        integer ok ;
        ok = 1 ;

        if (! ( (( initValue == 1'b0 ) && ( otherValue == 1'b1 )) ||
             (( initValue == 1'b1 ) && ( otherValue == 1'b0 )) ) )
          begin
             ok = 0;
             $display ( "ERROR ClockGen.v: clock values must be complements" ) ;
          end

        if ( ( v1Width <= 0 ) || ( v2Width <= 0 ))
          begin
             ok = 0;
             $display( "ERROR ClockGen.v: duty cycle must be greater then 0") ;
          end

        if ( ok == 0 ) $finish ;

      end


endmodule
module ClockGen(CLK_OUT);


   parameter v1Width = 5;
   parameter v2Width  = 5;
   parameter initDelay = 5;
   parameter initValue = 1'b0;
   parameter otherValue = 1'b1 ;

   output    CLK_OUT ;
   reg       CLK_OUT ;





   initial
      begin : clock_loop
         #0 ;
         CLK_OUT = initValue ;
         # initDelay ;
         forever
            begin
               CLK_OUT = otherValue ;
               # v1Width ;
               CLK_OUT = initValue ;
               # v2Width ;

            end
      end


   initial
     begin : parameter_assertions
        integer ok ;
        ok = 1 ;

        if (! ( (( initValue == 1'b0 ) && ( otherValue == 1'b1 )) ||
             (( initValue == 1'b1 ) && ( otherValue == 1'b0 )) ) )
          begin
             ok = 0;
             $display ( "ERROR ClockGen.v: clock values must be complements" ) ;
          end

        if ( ( v1Width <= 0 ) || ( v2Width <= 0 ))
          begin
             ok = 0;
             $display( "ERROR ClockGen.v: duty cycle must be greater then 0") ;
          end

        if ( ok == 0 ) $finish ;

      end


endmodule