data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv
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1: b'%Warning-WIDTH: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:140: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance f2sdram_safe_terminator\n  write_burstcounter     <= waitrequest_master ? 1\'d0 : 1\'d1;\n                                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:140: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                       : ... In instance f2sdram_safe_terminator\n  write_burstcounter     <= waitrequest_master ? 1\'d0 : 1\'d1;\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:198: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance f2sdram_safe_terminator\n      write_terminate_counter <= waitrequest_master ? 1\'d0 : 1\'d1;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:198: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                       : ... In instance f2sdram_safe_terminator\n      write_terminate_counter <= waitrequest_master ? 1\'d0 : 1\'d1;\n                                                    ^\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:152: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'next_state_write\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n   next_state_write = 1\'b0;\n   ^~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:154: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'next_state_write\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n   next_state_write = 1\'b1;\n   ^~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:156: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'next_state_write\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n   next_state_write = 1\'b0;\n   ^~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:160: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'next_state_write\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n   next_state_write = 1\'b0;\n   ^~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:162: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'next_state_write\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n   next_state_write = 1\'b1;\n   ^~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:229: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'burstcount_master\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n  burstcount_master = burstcount_latch;\n  ^~~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:230: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'address_master\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n  address_master    = address_latch;\n  ^~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:231: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'read_master\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n  read_master       = read_terminating;\n  ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:232: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'write_master\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n  write_master      = write_terminating;\n  ^~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:233: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'byteenable_master\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n  byteenable_master = 0;\n  ^~~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:236: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'burstcount_master\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n  burstcount_master = burstcount_slave;\n  ^~~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:237: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'address_master\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n  address_master    = address_slave;\n  ^~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:238: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'read_master\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n  read_master       = read_slave;\n  ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:239: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'byteenable_master\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n  byteenable_master = byteenable_slave;\n  ^~~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/135820056/sys/f2sdram_safe_terminator.sv:240: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'write_master\'\n                                                                                           : ... In instance f2sdram_safe_terminator\n  write_master      = write_slave;\n  ^~~~~~~~~~~~\n%Error: Exiting due to 15 error(s), 4 warning(s)\n'
module f2sdram_safe_terminator #(
  parameter     DATA_WIDTH = 64,
  parameter     BURSTCOUNT_WIDTH = 8
) (


	input         clk,


	input         rst_req_sync,


	input                         waitrequest_master,
	output [BURSTCOUNT_WIDTH-1:0] burstcount_master,
	output    [ADDRESS_WITDH-1:0] address_master,
	input        [DATA_WIDTH-1:0] readdata_master,
	input                         readdatavalid_master,
	output                        read_master,
	output       [DATA_WIDTH-1:0] writedata_master,
	output [BYTEENABLE_WIDTH-1:0] byteenable_master,
	output                        write_master,


	output                        waitrequest_slave,
	input  [BURSTCOUNT_WIDTH-1:0] burstcount_slave,
	input     [ADDRESS_WITDH-1:0] address_slave,
	output       [DATA_WIDTH-1:0] readdata_slave,
	output                        readdatavalid_slave,
	input                         read_slave,
	input        [DATA_WIDTH-1:0] writedata_slave,
	input  [BYTEENABLE_WIDTH-1:0] byteenable_slave,
	input                         write_slave
);

localparam BYTEENABLE_WIDTH = DATA_WIDTH/8;
localparam ADDRESS_WITDH    = 32-$clog2(BYTEENABLE_WIDTH);


reg init_reset_deasserted = 1'b0;

always_ff @(posedge clk) begin
	if (!rst_req_sync) begin
		init_reset_deasserted <= 1'b1;
	end
end


reg lock_stage = 1'b0;

always_ff @(posedge clk) begin
	if (rst_req_sync) begin

		if (init_reset_deasserted) begin
			lock_stage <= 1'b1;
		end
	end
	else begin

		lock_stage <= 1'b0;
	end
end


reg  state_write = 1'b0;
wire next_state_write;

wire burst_write_start     = !state_write  && next_state_write;
wire valid_write_data      = state_write && !waitrequest_master;
wire burst_write_end       = state_write && (write_burstcounter == write_burstcount_latch - 1'd1);
wire valid_non_burst_write = !state_write && write_slave && (burstcount_slave == 1) && !waitrequest_master;

reg [BURSTCOUNT_WIDTH-1:0] write_burstcounter     = 0;
reg [BURSTCOUNT_WIDTH-1:0] write_burstcount_latch = 0;
reg [ADDRESS_WITDH-1:0]    write_address_latch    = 0;

always_ff @(posedge clk) begin
	state_write <= next_state_write;

	if (burst_write_start) begin
		write_burstcounter     <= waitrequest_master ? 1'd0 : 1'd1;
		write_burstcount_latch <= burstcount_slave;
		write_address_latch    <= address_slave;
	end
	else if (valid_write_data) begin
		write_burstcounter     <= write_burstcounter + 1'd1;
	end
end

always_comb begin
	if (!state_write) begin
		if (valid_non_burst_write)
			next_state_write = 1'b0;
		else if (write_slave)
			next_state_write = 1'b1;
		else
			next_state_write = 1'b0;
	end
	else begin
		if (burst_write_end)
			next_state_write = 1'b0;
		else
			next_state_write = 1'b1;
	end
end

reg [BURSTCOUNT_WIDTH-1:0] write_terminate_counter = 0;
reg [BURSTCOUNT_WIDTH-1:0] burstcount_latch        = 0;
reg [ADDRESS_WITDH-1:0]    address_latch           = 0;

reg terminating       = 0;
reg read_terminating  = 0;
reg write_terminating = 0;

wire on_write_transaction       =  state_write && next_state_write;
wire on_start_write_transaction = !state_write && next_state_write;

always_ff @(posedge clk) begin
	if (rst_req_sync) begin

		if (init_reset_deasserted) begin
			if (!lock_stage) begin



				burstcount_latch              <= burstcount_slave;
				address_latch                 <= address_slave;
				terminating                   <= 1;

				if (on_write_transaction) begin
					write_terminating          <= 1;
					burstcount_latch           <= write_burstcount_latch;
					address_latch              <= write_address_latch;
					write_terminate_counter    <= waitrequest_master ? write_burstcounter : write_burstcounter + 1'd1;
				end
				else if (on_start_write_transaction) begin
					if (!valid_non_burst_write) begin
						write_terminating       <= 1;
						write_terminate_counter <= waitrequest_master ? 1'd0 : 1'd1;
					end
				end
				else if (read_slave && waitrequest_master) begin

					read_terminating           <= 1;
				end
			end
			else if (!waitrequest_master) begin
				read_terminating              <= 0;
			end
		end
	end
	else begin

		if (!write_terminating) terminating <= 0;
		read_terminating  <= 0;
	end

	if (write_terminating) begin

		if (!waitrequest_master) write_terminate_counter <= write_terminate_counter + 1'd1;
		if (write_terminate_counter == burstcount_latch - 1'd1) write_terminating <= 0;
	end
end


always_comb begin
	if (terminating) begin
		burstcount_master = burstcount_latch;
		address_master    = address_latch;
		read_master       = read_terminating;
		write_master      = write_terminating;
		byteenable_master = 0;
	end
	else begin
		burstcount_master = burstcount_slave;
		address_master    = address_slave;
		read_master       = read_slave;
		byteenable_master = byteenable_slave;
		write_master      = write_slave;
	end
end


assign writedata_master    = writedata_slave;
assign readdata_slave      = readdata_master;
assign readdatavalid_slave = readdatavalid_master;
assign waitrequest_slave   = waitrequest_master;

endmodule
module f2sdram_safe_terminator #(
  parameter     DATA_WIDTH = 64,
  parameter     BURSTCOUNT_WIDTH = 8
) (


	input         clk,


	input         rst_req_sync,


	input                         waitrequest_master,
	output [BURSTCOUNT_WIDTH-1:0] burstcount_master,
	output    [ADDRESS_WITDH-1:0] address_master,
	input        [DATA_WIDTH-1:0] readdata_master,
	input                         readdatavalid_master,
	output                        read_master,
	output       [DATA_WIDTH-1:0] writedata_master,
	output [BYTEENABLE_WIDTH-1:0] byteenable_master,
	output                        write_master,


	output                        waitrequest_slave,
	input  [BURSTCOUNT_WIDTH-1:0] burstcount_slave,
	input     [ADDRESS_WITDH-1:0] address_slave,
	output       [DATA_WIDTH-1:0] readdata_slave,
	output                        readdatavalid_slave,
	input                         read_slave,
	input        [DATA_WIDTH-1:0] writedata_slave,
	input  [BYTEENABLE_WIDTH-1:0] byteenable_slave,
	input                         write_slave
);


localparam BYTEENABLE_WIDTH = DATA_WIDTH/8;
localparam ADDRESS_WITDH    = 32-$clog2(BYTEENABLE_WIDTH);


reg init_reset_deasserted = 1'b0;

always_ff @(posedge clk) begin
	if (!rst_req_sync) begin
		init_reset_deasserted <= 1'b1;
	end
end


reg lock_stage = 1'b0;

always_ff @(posedge clk) begin
	if (rst_req_sync) begin

		if (init_reset_deasserted) begin
			lock_stage <= 1'b1;
		end
	end
	else begin

		lock_stage <= 1'b0;
	end
end


reg  state_write = 1'b0;
wire next_state_write;

wire burst_write_start     = !state_write  && next_state_write;
wire valid_write_data      = state_write && !waitrequest_master;
wire burst_write_end       = state_write && (write_burstcounter == write_burstcount_latch - 1'd1);
wire valid_non_burst_write = !state_write && write_slave && (burstcount_slave == 1) && !waitrequest_master;

reg [BURSTCOUNT_WIDTH-1:0] write_burstcounter     = 0;
reg [BURSTCOUNT_WIDTH-1:0] write_burstcount_latch = 0;
reg [ADDRESS_WITDH-1:0]    write_address_latch    = 0;

always_ff @(posedge clk) begin
	state_write <= next_state_write;

	if (burst_write_start) begin
		write_burstcounter     <= waitrequest_master ? 1'd0 : 1'd1;
		write_burstcount_latch <= burstcount_slave;
		write_address_latch    <= address_slave;
	end
	else if (valid_write_data) begin
		write_burstcounter     <= write_burstcounter + 1'd1;
	end
end

always_comb begin
	if (!state_write) begin
		if (valid_non_burst_write)
			next_state_write = 1'b0;
		else if (write_slave)
			next_state_write = 1'b1;
		else
			next_state_write = 1'b0;
	end
	else begin
		if (burst_write_end)
			next_state_write = 1'b0;
		else
			next_state_write = 1'b1;
	end
end

reg [BURSTCOUNT_WIDTH-1:0] write_terminate_counter = 0;
reg [BURSTCOUNT_WIDTH-1:0] burstcount_latch        = 0;
reg [ADDRESS_WITDH-1:0]    address_latch           = 0;

reg terminating       = 0;
reg read_terminating  = 0;
reg write_terminating = 0;

wire on_write_transaction       =  state_write && next_state_write;
wire on_start_write_transaction = !state_write && next_state_write;

always_ff @(posedge clk) begin
	if (rst_req_sync) begin

		if (init_reset_deasserted) begin
			if (!lock_stage) begin



				burstcount_latch              <= burstcount_slave;
				address_latch                 <= address_slave;
				terminating                   <= 1;

				if (on_write_transaction) begin
					write_terminating          <= 1;
					burstcount_latch           <= write_burstcount_latch;
					address_latch              <= write_address_latch;
					write_terminate_counter    <= waitrequest_master ? write_burstcounter : write_burstcounter + 1'd1;
				end
				else if (on_start_write_transaction) begin
					if (!valid_non_burst_write) begin
						write_terminating       <= 1;
						write_terminate_counter <= waitrequest_master ? 1'd0 : 1'd1;
					end
				end
				else if (read_slave && waitrequest_master) begin

					read_terminating           <= 1;
				end
			end
			else if (!waitrequest_master) begin
				read_terminating              <= 0;
			end
		end
	end
	else begin

		if (!write_terminating) terminating <= 0;
		read_terminating  <= 0;
	end

	if (write_terminating) begin

		if (!waitrequest_master) write_terminate_counter <= write_terminate_counter + 1'd1;
		if (write_terminate_counter == burstcount_latch - 1'd1) write_terminating <= 0;
	end
end


always_comb begin
	if (terminating) begin
		burstcount_master = burstcount_latch;
		address_master    = address_latch;
		read_master       = read_terminating;
		write_master      = write_terminating;
		byteenable_master = 0;
	end
	else begin
		burstcount_master = burstcount_slave;
		address_master    = address_slave;
		read_master       = read_slave;
		byteenable_master = byteenable_slave;
		write_master      = write_slave;
	end
end


assign writedata_master    = writedata_slave;
assign readdata_slave      = readdata_master;
assign readdatavalid_slave = readdatavalid_master;
assign waitrequest_slave   = waitrequest_master;

endmodule