data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ClockDivider_50Mhz_to_30Hz.v
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ClockDivider_50Mhz_to_30Hz.v\n%Error: Exiting due to 4 error(s)\n'
module ClockDivider_50Mhz_to_30Hz(
    input clock,
	 input reset,
    output reg enable
    );
	reg [24:0] count;
	
	always@(posedge clock) begin
		count <= 0;
		enable <= 1;
		if(reset) begin
			enable <= 1;
			count  <= 0;
		end				  
		

		else if(count == 1666670) begin

			enable <= 1;
			count  <= 0;
		end
		else begin
			enable <= 0;
			count <= count + 1;
		end
	
	end

endmodule
module ClockDivider_50Mhz_to_30Hz(
    input clock,
	 input reset,
    output reg enable
    );

	reg [24:0] count;
	
	always@(posedge clock) begin
		count <= 0;
		enable <= 1;
		if(reset) begin
			enable <= 1;
			count  <= 0;
		end				  
		

		else if(count == 1666670) begin

			enable <= 1;
			count  <= 0;
		end
		else begin
			enable <= 0;
			count <= count + 1;
		end
	
	end

endmodule