data/full_repos/permissive/177136805/6bitgtoreq.v
1: b"%Error: data/full_repos/permissive/177136805/6bitgtoreq.v:37: Cannot find file containing module: 'Final'\nFinal gteqoreq(.c(a[7:0]),.d(b[7:0]),.eight(agteqb));    \n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/177136805,data/full_repos/permissive/177136805/Final\n             data/full_repos/permissive/177136805,data/full_repos/permissive/177136805/Final.v\n             data/full_repos/permissive/177136805,data/full_repos/permissive/177136805/Final.sv\n             Final\n             Final.v\n             Final.sv\n             obj_dir/Final\n             obj_dir/Final.v\n             obj_dir/Final.sv\n%Error: Exiting due to 1 error(s)\n"
module sixbitgtoreq
(
    input wire[5:0] x,y,
    output wire agteqb
);
reg[7:0] a,b;

always @*
begin
    if(x[5]==0)
    begin
        a[7]=0;
        a[6]=0;
        a[5:0]=x;
    end
     if(x[5]==1)
     begin
        a[7]=1;
        a[6]=1;
        a[5:0]=x;
    end
    if(y[5]==0)
    begin
        b[7]=0;
        b[6]=0;
        b[5:0]=y;
    end
    if(y[5]==1)
    begin
        b[7]=1;
        b[6]=1;
        b[5:0]=y;
    end
end
Final gteqoreq(.c(a[7:0]),.d(b[7:0]),.eight(agteqb));

endmodule
module sixbitgtoreq
(
    input wire[5:0] x,y,
    output wire agteqb
);

reg[7:0] a,b;

always @*
begin
    if(x[5]==0)
    begin
        a[7]=0;
        a[6]=0;
        a[5:0]=x;
    end
     if(x[5]==1)
     begin
        a[7]=1;
        a[6]=1;
        a[5:0]=x;
    end
    if(y[5]==0)
    begin
        b[7]=0;
        b[6]=0;
        b[5:0]=y;
    end
    if(y[5]==1)
    begin
        b[7]=1;
        b[6]=1;
        b[5:0]=y;
    end
end
Final gteqoreq(.c(a[7:0]),.d(b[7:0]),.eight(agteqb));

endmodule