data/full_repos/permissive/140493787/src/hdl/pixel_memory.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:71: Unsupported: Ignoring delay on this delayed statement.\n      forever #(CLK_PER / 2) clk <= ~clk;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:76: syntax error, unexpected \'@\'\n      wrEnable <= 1; @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:79: syntax error, unexpected \'@\'\n            writeX <= i; writeY <= j; @(posedge clk);\n                                      ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:82: syntax error, unexpected \'@\'\n      wrEnable <= 0; @ (posedge clk);\n                     ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:89: syntax error, unexpected \'@\'\n            readX <= i; readY <= j; @(posedge clk);\n                                    ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:93: syntax error, unexpected \'@\'\n      readX <= 24; readY <= 24; @(posedge clk);\n                                ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:94: syntax error, unexpected \'@\'\n      readX <= 12; readY <= 12; @(posedge clk);\n                                ^\n%Error: Exiting due to 6 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pixel_memory (
   output wire       color,
   input  wire [9:0] readX,
   input  wire [9:0] readY,
   input  wire [8:0] writeX,
   input  wire [8:0] writeY,
   input  wire       wrEnable,
   input  wire       clk,
   
   input wire reset,
   output wire reset_done
);

   parameter
   FRAME_WIDTH  = 10'd640,
   FRAME_HEIGHT = 10'd480;

   reg px_color [FRAME_WIDTH * FRAME_HEIGHT - 1 : 0];
   reg [19:0] reset_addr_counter = 0;

   wire [18:0] readAddr, writeAddr;
   assign readAddr = readY * FRAME_WIDTH + readX + 1;
   assign writeAddr = (reset_done == 1'b1) ? (writeY * FRAME_WIDTH + writeX) : (reset_addr_counter[18:0]);

   always@(posedge clk)
      if (reset)
         reset_addr_counter <= 'b0;
      else if (reset_done == 1'b0)
         reset_addr_counter <= reset_addr_counter + 1;
   assign reset_done = reset_addr_counter[19];
   
   blk_mem_gen_0 px_mem (
      .addra(writeAddr),
      .clka(clk),
      .dina(reset_done),
      .wea(~reset_done | wrEnable),
      .addrb(readAddr),
      .enb(1'b1),
      .clkb(clk),
      .doutb(color)
   );
endmodule
module pixel_memory (
   output wire       color,
   input  wire [9:0] readX,
   input  wire [9:0] readY,
   input  wire [8:0] writeX,
   input  wire [8:0] writeY,
   input  wire       wrEnable,
   input  wire       clk,
   
   input wire reset,
   output wire reset_done
);


   parameter
   FRAME_WIDTH  = 10'd640,
   FRAME_HEIGHT = 10'd480;

   reg px_color [FRAME_WIDTH * FRAME_HEIGHT - 1 : 0];
   reg [19:0] reset_addr_counter = 0;

   wire [18:0] readAddr, writeAddr;
   assign readAddr = readY * FRAME_WIDTH + readX + 1;
   assign writeAddr = (reset_done == 1'b1) ? (writeY * FRAME_WIDTH + writeX) : (reset_addr_counter[18:0]);

   always@(posedge clk)
      if (reset)
         reset_addr_counter <= 'b0;
      else if (reset_done == 1'b0)
         reset_addr_counter <= reset_addr_counter + 1;
   assign reset_done = reset_addr_counter[19];
   
   blk_mem_gen_0 px_mem (
      .addra(writeAddr),
      .clka(clk),
      .dina(reset_done),
      .wea(~reset_done | wrEnable),
      .addrb(readAddr),
      .enb(1'b1),
      .clkb(clk),
      .doutb(color)
   );
endmodule