data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v
 line:33: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #10 iclk = ~iclk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:23: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("debouncing_reset.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:24: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars();\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #100 irst_n = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #20  irst_n = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #20  irst_n = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #20  irst_n = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #20  irst_n = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #20  irst_n = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #20  irst_n = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #20  irst_n = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176979397/test_bench/debouncing_reset_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #1000 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module debouncing_reset_tb();

	reg 	iclk;
	reg 	irst_n;
	wire	orst_n;
	
	debouncing_reset i0 (
		.iclk (iclk),
		.irst_n (irst_n),
		.orst_n (orst_n)
	);
	
	initial begin
		iclk 		= 0;
		irst_n	= 1;
	end
	
	always begin
		#10	iclk = ~iclk;
	end
	
	always begin
		$dumpfile("debouncing_reset.vcd");
		$dumpvars();
		#100	irst_n	= 0;
		#20		irst_n	= 1;
		#20		irst_n	=	0;
		#20		irst_n	= 1;
		#20		irst_n	=	0;
		#20		irst_n	= 1;
		#20		irst_n	=	0;
		#20		irst_n	= 1;
		#1000	$finish;
	end
	
endmodule
module debouncing_reset_tb();


	reg 	iclk;
	reg 	irst_n;
	wire	orst_n;
	
	debouncing_reset i0 (
		.iclk (iclk),
		.irst_n (irst_n),
		.orst_n (orst_n)
	);
	
	initial begin
		iclk 		= 0;
		irst_n	= 1;
	end
	
	always begin
		#10	iclk = ~iclk;
	end
	
	always begin
		$dumpfile("debouncing_reset.vcd");
		$dumpvars();
		#100	irst_n	= 0;
		#20		irst_n	= 1;
		#20		irst_n	=	0;
		#20		irst_n	= 1;
		#20		irst_n	=	0;
		#20		irst_n	= 1;
		#20		irst_n	=	0;
		#20		irst_n	= 1;
		#1000	$finish;
	end
	
endmodule