data/full_repos/permissive/20688874/coding_theory/ee577bHw2q3.v
data/verilator_xmls/05cda1ee-fff2-488b-a019-6572ae44eed2.xml
module adder1bit(A,B,Cin,S,Cout);
	input A,B,Cin;
	output S,Cout;
	reg [1:0] SUM;
	reg S, Cout;
	
	always @(A or B or Cin)
	begin
		SUM[1:0] = A + B + Cin;
		S = SUM[0];
		Cout = SUM[1];
	end

endmodule
module adder1bit(A,B,Cin,S,Cout);

	input A,B,Cin;
	output S,Cout;
	reg [1:0] SUM;
	reg S, Cout;
	
	always @(A or B or Cin)
	begin
		SUM[1:0] = A + B + Cin;
		S = SUM[0];
		Cout = SUM[1];
	end

endmodule