data/full_repos/permissive/143278/blif/blif02b.v
 line:5: before: "~&"
data/verilator_xmls/61c0264b-3ba1-4d75-a02e-44926b450b51.xml
module test_logic(input A, B, output reg q_nand, q_nor, q_xnor, q_not);

   always @(A, B) begin
      q_nand = A ~& B;
      q_nor  = A ~| B;
      q_xnor = A ~^ B;
      q_not  = ~A;
   end

endmodule
module test_logic(input A, B, output reg q_nand, q_nor, q_xnor, q_not);


   always @(A, B) begin
      q_nand = A ~& B;
      q_nor  = A ~| B;
      q_xnor = A ~^ B;
      q_not  = ~A;
   end

endmodule