data/full_repos/permissive/125592111/verilog/MEM_WB.v
1: b"%Error: data/full_repos/permissive/125592111/verilog/MEM_WB.v:28: Duplicate declaration of signal: 'RegWrite_out'\n                                                                : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg RegWrite_out;\n     ^~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/MEM_WB.v:24: ... Location of original declaration\n output RegWrite_out, \n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/MEM_WB.v:29: Duplicate declaration of signal: 'MemtoReg_out'\n reg [1:0] MemtoReg_out, RegDst_out;\n           ^~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/MEM_WB.v:25: ... Location of original declaration\n output [1:0] MemtoReg_out, RegDst_out\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/MEM_WB.v:29: Duplicate declaration of signal: 'RegDst_out'\n reg [1:0] MemtoReg_out, RegDst_out;\n                         ^~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/MEM_WB.v:25: ... Location of original declaration\n output [1:0] MemtoReg_out, RegDst_out\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/MEM_WB.v:30: Duplicate declaration of signal: 'D_MEM_read_data_out'\n reg [31:0] D_MEM_read_data_out, D_MEM_read_addr_out, PC_plus_4_out;\n            ^~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/MEM_WB.v:22: ... Location of original declaration\n output [31:0] D_MEM_read_data_out, D_MEM_read_addr_out, PC_plus_4_out,\n               ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/MEM_WB.v:30: Duplicate declaration of signal: 'D_MEM_read_addr_out'\n reg [31:0] D_MEM_read_data_out, D_MEM_read_addr_out, PC_plus_4_out;\n                                 ^~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/MEM_WB.v:22: ... Location of original declaration\n output [31:0] D_MEM_read_data_out, D_MEM_read_addr_out, PC_plus_4_out,\n                                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/MEM_WB.v:30: Duplicate declaration of signal: 'PC_plus_4_out'\n reg [31:0] D_MEM_read_data_out, D_MEM_read_addr_out, PC_plus_4_out;\n                                                      ^~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/MEM_WB.v:22: ... Location of original declaration\n output [31:0] D_MEM_read_data_out, D_MEM_read_addr_out, PC_plus_4_out,\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/MEM_WB.v:31: Duplicate declaration of signal: 'MEM_WB_RegisterRd_out'\n reg [4:0] MEM_WB_RegisterRd_out;\n           ^~~~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/MEM_WB.v:23: ... Location of original declaration\n output [4:0] MEM_WB_RegisterRd_out,\n              ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module MEM_WB (
	input RegWrite_in, 
	input [1:0] MemtoReg_in, RegDst_in,
	input [31:0] D_MEM_read_data_in, D_MEM_read_addr_in, PC_plus_4_in,
	input [4:0] EX_MEM_RegisterRd_in,
	input clk, rst,

	output [31:0] D_MEM_read_data_out, D_MEM_read_addr_out, PC_plus_4_out,
	output [4:0] MEM_WB_RegisterRd_out,
	output RegWrite_out, 
	output [1:0] MemtoReg_out, RegDst_out
);
	
	reg RegWrite_out;
	reg [1:0] MemtoReg_out, RegDst_out;
	reg [31:0] D_MEM_read_data_out, D_MEM_read_addr_out, PC_plus_4_out;
	reg [4:0] MEM_WB_RegisterRd_out;
	
	always @(negedge clk)
	begin
		if (rst == 1'b1) begin
			RegWrite_out <= 1'b0;
			MemtoReg_out <= 2'b00;
			RegDst_out <= 2'b00;
			D_MEM_read_data_out <= 32'b0;
			D_MEM_read_addr_out <= 32'b0;
			PC_plus_4_out <= 32'b0;
			MEM_WB_RegisterRd_out <= 5'b0;
		end
		else begin
			RegWrite_out <= RegWrite_in;
			MemtoReg_out <= MemtoReg_in;
			RegDst_out <= RegDst_in;
			D_MEM_read_data_out <= D_MEM_read_data_in;
			D_MEM_read_addr_out <= D_MEM_read_addr_in;
			MEM_WB_RegisterRd_out <= EX_MEM_RegisterRd_in;
			PC_plus_4_out <= PC_plus_4_in;
		end
	end
	
endmodule
module MEM_WB (
	input RegWrite_in, 
	input [1:0] MemtoReg_in, RegDst_in,
	input [31:0] D_MEM_read_data_in, D_MEM_read_addr_in, PC_plus_4_in,
	input [4:0] EX_MEM_RegisterRd_in,
	input clk, rst,

	output [31:0] D_MEM_read_data_out, D_MEM_read_addr_out, PC_plus_4_out,
	output [4:0] MEM_WB_RegisterRd_out,
	output RegWrite_out, 
	output [1:0] MemtoReg_out, RegDst_out
);

	
	reg RegWrite_out;
	reg [1:0] MemtoReg_out, RegDst_out;
	reg [31:0] D_MEM_read_data_out, D_MEM_read_addr_out, PC_plus_4_out;
	reg [4:0] MEM_WB_RegisterRd_out;
	
	always @(negedge clk)
	begin
		if (rst == 1'b1) begin
			RegWrite_out <= 1'b0;
			MemtoReg_out <= 2'b00;
			RegDst_out <= 2'b00;
			D_MEM_read_data_out <= 32'b0;
			D_MEM_read_addr_out <= 32'b0;
			PC_plus_4_out <= 32'b0;
			MEM_WB_RegisterRd_out <= 5'b0;
		end
		else begin
			RegWrite_out <= RegWrite_in;
			MemtoReg_out <= MemtoReg_in;
			RegDst_out <= RegDst_in;
			D_MEM_read_data_out <= D_MEM_read_data_in;
			D_MEM_read_addr_out <= D_MEM_read_addr_in;
			MEM_WB_RegisterRd_out <= EX_MEM_RegisterRd_in;
			PC_plus_4_out <= PC_plus_4_in;
		end
	end
	
endmodule