data/full_repos/permissive/159276987/rtl/e203/subsys/e203_subsys_pll.v
None: at end of input
1: b'%Error: data/full_repos/permissive/159276987/rtl/e203/subsys/e203_subsys_pll.v:28: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159276987/rtl/e203/subsys,data/full_repos/permissive/159276987/e203_defines.v\n             data/full_repos/permissive/159276987/rtl/e203/subsys,data/full_repos/permissive/159276987/e203_defines.v.v\n             data/full_repos/permissive/159276987/rtl/e203/subsys,data/full_repos/permissive/159276987/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module e203_subsys_pll(
  input  pll_asleep,

  input  pllrefclk,
  output plloutclk,

  input        pll_RESET,
  input [1:0]  pll_OD,
  input [7:0]  pll_M,
  input [4:0]  pll_N 
  );

  wire pllout;
  `ifdef FPGA_SOURCE

      assign pllout = pllrefclk;
  `else
      assign pllout = pllrefclk;
  `endif

  assign plloutclk = pllout;
endmodule
module e203_subsys_pll(
  input  pll_asleep,

  input  pllrefclk,
  output plloutclk,

  input        pll_RESET,
  input [1:0]  pll_OD,
  input [7:0]  pll_M,
  input [4:0]  pll_N 
  );


  wire pllout;
  `ifdef FPGA_SOURCE

      assign pllout = pllrefclk;
  `else
      assign pllout = pllrefclk;
  `endif

  assign plloutclk = pllout;
endmodule