data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v
data/verilator_xmls/68acafc2-bc2a-438e-af55-bbcf80447269.xml
module mac_8_9(a, b, c, out);
parameter DATA_WIDTH = 18;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out[8:0] = a[8:0] * b[8:0] + c[8:0];
assign out[17:9] = a[17:9] * b[17:9] + c[17:9];

endmodule
module mac_8_9(a, b, c, out);

parameter DATA_WIDTH = 18;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out[8:0] = a[8:0] * b[8:0] + c[8:0];
assign out[17:9] = a[17:9] * b[17:9] + c[17:9];

endmodule