data/full_repos/permissive/212763527/others/sources/t.v
1: b"%Error: data/full_repos/permissive/212763527/others/sources/t.v:3: Duplicate declaration of signal: 'sel'\nreg sel = 1;\n    ^~~\n        data/full_repos/permissive/212763527/others/sources/t.v:1: ... Location of original declaration\nmodule test(input clk, output reg dout, output sel);\n                                               ^~~\n%Error: Exiting due to 1 error(s)\n"
module test(input clk, output reg dout, output sel);

reg sel = 1;

always @(*) begin
    sel <= sel;
    dout <= sel;
end
        
endmodule
module test(input clk, output reg dout, output sel);


reg sel = 1;

always @(*) begin
    sel <= sel;
    dout <= sel;
end
        
endmodule