data/full_repos/permissive/152129793/comun/modulos.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:576: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.los_interruptores\n  wire [7:0] posx = hc - XINIT;   \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:577: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.los_interruptores\n  wire [7:0] posy = vc - YINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:503: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_leds\n  wire [7:0] pos = hc - XINIT;   \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:399: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n    posicion_caracter_en_pantalla = (hc - XINIT + 1)>>4;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:403: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n  wire [7:0] posx = hc - XINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:404: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n  wire [7:0] posy = vc - YINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:436: Bit extraction of array[127:0] requires 7 bit index, not 8 bits.\n                                                                        : ... In instance display.display_digitos\n        scan_actual <= chars[charaddr];\n                            ^\n%Warning-UNSIGNED: data/full_repos/permissive/152129793/comun/modulos.v:216: Comparison is constant due to unsigned arithmetic\n                                                                           : ... In instance display.sincronismos\n    if (hcont>=0 && hcont<HACTIVE && vcont>=0 && vcont<VACTIVE)\n             ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152129793/comun/modulos.v:216: Comparison is constant due to unsigned arithmetic\n                                                                           : ... In instance display.sincronismos\n    if (hcont>=0 && hcont<HACTIVE && vcont>=0 && vcont<VACTIVE)\n                                          ^~\n%Error: Exiting due to 9 warning(s)\n'
module switches (
  input wire clk,
  input wire evento_teclado,
  input wire [7:0] scancode,
  input wire extended,
  input wire released,


  output reg [7:0] switch,


  input wire [10:0] hc,
  input wire [10:0] vc,
  output reg [5:0] r,
  output reg [5:0] g,
  output reg [5:0] b
  );
  
  parameter YINIT = 392;
  
  localparam ANCHO = 8*8 + 7*24;
  localparam XINIT = (640 - ANCHO) / 2;
  localparam XFIN  = XINIT + ANCHO - 1;
  localparam YFIN  = YINIT + 15;
  
  localparam COLOR_CONTORNO   = {6'h3F, 6'h3F, 6'h3F};
  localparam COLOR_SW_ON      = {6'h20, 6'h20, 6'h20};
  localparam COLOR_SW_OFF     = {6'h00, 6'h00, 6'h20};
  
  initial begin
    switch[0] = 1'b0;
    switch[1] = 1'b0;
    switch[2] = 1'b0;
    switch[3] = 1'b0;
    switch[4] = 1'b0;
    switch[5] = 1'b0;
    switch[6] = 1'b0;
    switch[7] = 1'b0;
  end
  
  always @(posedge clk) begin
    if (evento_teclado == 1'b1 && released == 1'b0 && extended == 1'b0) begin
      case (scancode)
        8'h05: switch[7] <= ~switch[7];
        8'h06: switch[6] <= ~switch[6];
        8'h04: switch[5] <= ~switch[5];
        8'h0C: switch[4] <= ~switch[4];
        8'h03: switch[3] <= ~switch[3];
        8'h0B: switch[2] <= ~switch[2];
        8'h83: switch[1] <= ~switch[1];
        8'h0A: switch[0] <= ~switch[0];
      endcase
    end
  end

  wire [7:0] posx = hc - XINIT;
  wire [7:0] posy = vc - YINIT;
  always @* begin
    {r,g,b} = 18'h00000;
    if (hc >= XINIT && hc <= XFIN && vc >= YINIT && vc <= YFIN) begin
      if (posx[4:3] == 2'b00) begin
        if (vc == YINIT || vc == YFIN || posx[2:0] == 3'b000 || posx[2:0] == 3'b111)
          {r,g,b} = COLOR_CONTORNO;
        else if (posy[3] == 1'b0) begin
          if (switch[~posx[7:5]] == 1'b1)
            {r,g,b} = COLOR_SW_ON;
          else
            {r,g,b} = COLOR_SW_OFF;
        end
        else begin
          if (switch[~posx[7:5]] == 1'b0)
            {r,g,b} = COLOR_SW_ON;
          else
            {r,g,b} = COLOR_SW_OFF;
        end
      end
    end
  end
  
endmodule
module switches (
  input wire clk,
  input wire evento_teclado,
  input wire [7:0] scancode,
  input wire extended,
  input wire released,


  output reg [7:0] switch,


  input wire [10:0] hc,
  input wire [10:0] vc,
  output reg [5:0] r,
  output reg [5:0] g,
  output reg [5:0] b
  );

  
  parameter YINIT = 392;
  
  localparam ANCHO = 8*8 + 7*24;
  localparam XINIT = (640 - ANCHO) / 2;
  localparam XFIN  = XINIT + ANCHO - 1;
  localparam YFIN  = YINIT + 15;
  
  localparam COLOR_CONTORNO   = {6'h3F, 6'h3F, 6'h3F};
  localparam COLOR_SW_ON      = {6'h20, 6'h20, 6'h20};
  localparam COLOR_SW_OFF     = {6'h00, 6'h00, 6'h20};
  
  initial begin
    switch[0] = 1'b0;
    switch[1] = 1'b0;
    switch[2] = 1'b0;
    switch[3] = 1'b0;
    switch[4] = 1'b0;
    switch[5] = 1'b0;
    switch[6] = 1'b0;
    switch[7] = 1'b0;
  end
  
  always @(posedge clk) begin
    if (evento_teclado == 1'b1 && released == 1'b0 && extended == 1'b0) begin
      case (scancode)
        8'h05: switch[7] <= ~switch[7];
        8'h06: switch[6] <= ~switch[6];
        8'h04: switch[5] <= ~switch[5];
        8'h0C: switch[4] <= ~switch[4];
        8'h03: switch[3] <= ~switch[3];
        8'h0B: switch[2] <= ~switch[2];
        8'h83: switch[1] <= ~switch[1];
        8'h0A: switch[0] <= ~switch[0];
      endcase
    end
  end

  wire [7:0] posx = hc - XINIT;
  wire [7:0] posy = vc - YINIT;
  always @* begin
    {r,g,b} = 18'h00000;
    if (hc >= XINIT && hc <= XFIN && vc >= YINIT && vc <= YFIN) begin
      if (posx[4:3] == 2'b00) begin
        if (vc == YINIT || vc == YFIN || posx[2:0] == 3'b000 || posx[2:0] == 3'b111)
          {r,g,b} = COLOR_CONTORNO;
        else if (posy[3] == 1'b0) begin
          if (switch[~posx[7:5]] == 1'b1)
            {r,g,b} = COLOR_SW_ON;
          else
            {r,g,b} = COLOR_SW_OFF;
        end
        else begin
          if (switch[~posx[7:5]] == 1'b0)
            {r,g,b} = COLOR_SW_ON;
          else
            {r,g,b} = COLOR_SW_OFF;
        end
      end
    end
  end
  
endmodule