data/full_repos/permissive/141038711/hdl/apb_levirq.v
data/verilator_xmls/6e80032b-295d-42e2-8bfa-c198dec6bb41.xml
module apb_levirq (

   input             reset_n,
   input             enable,


   input             pclk,            
   input      [ 2:0] paddr,
   input             pwrite,
   input             psel,
   input             penable,
   input      [31:0] pwdata,
   output reg [31:0] prdata,
   output            pready,
   output            pslverr,
   output            irq,


   input      [ 3:0] irq_request
);

reg  [3:0] irq_control;
wire [3:0] irq_pending;

wire apb_write = psel & penable & pwrite;
wire apb_read  = psel & ~pwrite;

   assign pready  = 1'b1;
   assign pslverr = 1'b0;
   
   assign irq_pending = irq_request & irq_control;
   assign irq = |irq_pending;
   
   always @(posedge pclk or negedge reset_n)
   begin
      if (!reset_n)
      begin
         irq_control <= 4'h0;
         prdata    <= 32'h0;
      end
      else if (enable)
      begin
         
         if (apb_write)
         begin
            case (paddr)
            3'h0  : irq_control <= pwdata[3:0];

           endcase
         end
         
         if (apb_read)
         begin
            case (paddr)
            3'h0 : prdata <= {28'h0,irq_control};
            3'h4 : prdata <= {24'h0,irq_pending,irq_request};
            endcase
         end
         else
            prdata <= 32'h0;
      end
   end
   
endmodule
module apb_levirq (

   input             reset_n,
   input             enable,


   input             pclk,            
   input      [ 2:0] paddr,
   input             pwrite,
   input             psel,
   input             penable,
   input      [31:0] pwdata,
   output reg [31:0] prdata,
   output            pready,
   output            pslverr,
   output            irq,


   input      [ 3:0] irq_request
);


reg  [3:0] irq_control;
wire [3:0] irq_pending;

wire apb_write = psel & penable & pwrite;
wire apb_read  = psel & ~pwrite;

   assign pready  = 1'b1;
   assign pslverr = 1'b0;
   
   assign irq_pending = irq_request & irq_control;
   assign irq = |irq_pending;
   
   always @(posedge pclk or negedge reset_n)
   begin
      if (!reset_n)
      begin
         irq_control <= 4'h0;
         prdata    <= 32'h0;
      end
      else if (enable)
      begin
         
         if (apb_write)
         begin
            case (paddr)
            3'h0  : irq_control <= pwdata[3:0];

           endcase
         end
         
         if (apb_read)
         begin
            case (paddr)
            3'h0 : prdata <= {28'h0,irq_control};
            3'h4 : prdata <= {24'h0,irq_pending,irq_request};
            endcase
         end
         else
            prdata <= 32'h0;
      end
   end
   
endmodule