data/full_repos/permissive/150482260/eightbit_alu.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/150482260/eightbit_alu.v:39: Unsupported or unknown PLI call: $monitor\n        $monitor("%d sel=%d, a=%d (%8b), b=%d (%8b) -> f=%d (%8b), ovf=%b, take_branch=%b", $time, sel, a, a, b, b, f, f, ovf, take_branch);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10 sel = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b11010100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b00101011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #10 sel = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b01010101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b11111111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #10 sel = 2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b01010101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b11111111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #10 sel = 3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b01010101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b11111111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #10 sel = 4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b01010101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b11111111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #10 sel = 5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b01010101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b11111111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #10 sel = 6;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b01010101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b11111111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #10 sel = 7;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b01010101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #10 a   = 8\'b11111111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/eightbit_alu.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 25 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module eightbit_alu_tb;
    reg signed [7:0] a, b;
    reg [2:0] sel;

    wire signed [7:0] f;
    wire ovf, take_branch;

    eightbit_alu uut(
        .a(a),
        .b(b),
        .sel(sel),
        .f(f),
        .ovf(ovf),
        .take_branch(take_branch));

    initial begin
        $monitor("%d sel=%d, a=%d (%8b), b=%d (%8b) -> f=%d (%8b), ovf=%b, take_branch=%b", $time, sel, a, a, b, b, f, f, ovf, take_branch);

        #10 sel = 0;
            a   = 8'b00000001;
            b   = 8'b00000000;
        #10 a   = 8'b11010100;
            b   = 8'b10101010;
        #10 a   = 8'b00101011;
            b   = 8'b01010101;

        #10 sel = 1;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 2;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 3;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 4;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 5;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 6;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 7;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 $finish;
    end
endmodule
module eightbit_alu_tb;

    reg signed [7:0] a, b;
    reg [2:0] sel;

    wire signed [7:0] f;
    wire ovf, take_branch;

    eightbit_alu uut(
        .a(a),
        .b(b),
        .sel(sel),
        .f(f),
        .ovf(ovf),
        .take_branch(take_branch));

    initial begin
        $monitor("%d sel=%d, a=%d (%8b), b=%d (%8b) -> f=%d (%8b), ovf=%b, take_branch=%b", $time, sel, a, a, b, b, f, f, ovf, take_branch);

        #10 sel = 0;
            a   = 8'b00000001;
            b   = 8'b00000000;
        #10 a   = 8'b11010100;
            b   = 8'b10101010;
        #10 a   = 8'b00101011;
            b   = 8'b01010101;

        #10 sel = 1;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 2;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 3;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 4;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 5;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 6;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 sel = 7;
            a   = 8'b00000000;
            b   = 8'b00000000;
        #10 a   = 8'b01010101;
            b   = 8'b10101010;
        #10 a   = 8'b11111111;
            b   = 8'b11111111;

        #10 $finish;
    end
endmodule