data/full_repos/permissive/187464337/stopwatch/testbench_1.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/187464337/stopwatch/testbench_1.v:11: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/187464337/stopwatch/testbench_1.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #200 start_pause = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/187464337/stopwatch/testbench_1.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #201 start_pause = 1;\n      ^\n%Error: data/full_repos/permissive/187464337/stopwatch/testbench_1.v:16: Unsupported or unknown PLI call: $monitor\n      $monitor($time, " Output enable = %d", enable);\n      ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
   reg clk = 0, start_pause = 1, reset = 1;
   wire enable;
   wire [3:0] min_higher, min_lower, s_higher, s_lower, ms_higher, ms_lower;
   
   stopwatch_counter sc(
      clk, min_higher, min_lower, s_higher, s_lower,
      ms_higher, ms_lower, start_pause, reset, enable
   );
   
   always #5 clk = ~clk;
   
   initial begin
      #200 start_pause = 0;
      #201 start_pause = 1;
      $monitor($time, " Output enable = %d", enable);
   end

endmodule
module tb;

   reg clk = 0, start_pause = 1, reset = 1;
   wire enable;
   wire [3:0] min_higher, min_lower, s_higher, s_lower, ms_higher, ms_lower;
   
   stopwatch_counter sc(
      clk, min_higher, min_lower, s_higher, s_lower,
      ms_higher, ms_lower, start_pause, reset, enable
   );
   
   always #5 clk = ~clk;
   
   initial begin
      #200 start_pause = 0;
      #201 start_pause = 1;
      $monitor($time, " Output enable = %d", enable);
   end

endmodule