data/full_repos/permissive/184431263/OAI/OAI22.v
data/verilator_xmls/bdbcf9eb-558b-4586-ae8f-367eaa6740fd.xml
module OAI22(Y, A0, A1, B0, B1, VDD, VSS );
  input A0, A1, B0, B1;
  output Y;
  inout VDD, VSS;

  assign Y=~((A0 || A1) && (B0 || B1));
endmodule
module OAI22(Y, A0, A1, B0, B1, VDD, VSS );

  input A0, A1, B0, B1;
  output Y;
  inout VDD, VSS;

  assign Y=~((A0 || A1) && (B0 || B1));
endmodule