data/full_repos/permissive/157424577/main.v
1: b'%Error: data/full_repos/permissive/157424577/main.v:1: Cannot find include file: cache_memory.v\n`include "cache_memory.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157424577,data/full_repos/permissive/157424577/cache_memory.v\n             data/full_repos/permissive/157424577,data/full_repos/permissive/157424577/cache_memory.v.v\n             data/full_repos/permissive/157424577,data/full_repos/permissive/157424577/cache_memory.v.sv\n             cache_memory.v\n             cache_memory.v.v\n             cache_memory.v.sv\n             obj_dir/cache_memory.v\n             obj_dir/cache_memory.v.v\n             obj_dir/cache_memory.v.sv\n%Error: data/full_repos/permissive/157424577/main.v:2: Cannot find include file: main_memory.v\n`include "main_memory.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157424577/main.v:3: Cannot find include file: cache_controller.v\n`include "cache_controller.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module main(clk,address,dataOut,hit);
    input clk;
    input [31:0] address;

    output [31:0] dataOut;
    output hit;

    wire read;
    wire [511:0] dataIn;



    main_memory u0(clk,address,dataIn);
    cache_memory u1(clk,address,read,dataIn,dataOut,hit);
    cache_controller u2(clk,hit,read);

endmodule
module main(clk,address,dataOut,hit);

    input clk;
    input [31:0] address;

    output [31:0] dataOut;
    output hit;

    wire read;
    wire [511:0] dataIn;



    main_memory u0(clk,address,dataIn);
    cache_memory u1(clk,address,read,dataIn,dataOut,hit);
    cache_controller u2(clk,hit,read);

endmodule