data/full_repos/permissive/162672365/Adder.v
data/verilator_xmls/fbe7f381-9c5d-417b-8dbc-a02327e27a4f.xml
module thirtytwoBitFullAdder(sum, carry, in1, in2, cin);
	input [31:0] in1, in2;
	input cin;
	output [31:0] sum;
	output carry;
	wire caux1, caux2, caux3;
	
	eightBitFullAdder ebfa1(sum[7:0], caux1, in1[7:0], in2[7:0], cin);
	eightBitFullAdder ebfa2(sum[15:8], caux2, in1[15:8], in2[15:8], caux1);
	eightBitFullAdder ebfa3(sum[23:16], caux3, in1[23:16], in2[23:16], caux2);
	eightBitFullAdder ebfa4(sum[31:24], carry, in1[31:24], in2[31:24], caux3);
	
endmodule
module thirtytwoBitFullAdder(sum, carry, in1, in2, cin);

	input [31:0] in1, in2;
	input cin;
	output [31:0] sum;
	output carry;
	wire caux1, caux2, caux3;
	
	eightBitFullAdder ebfa1(sum[7:0], caux1, in1[7:0], in2[7:0], cin);
	eightBitFullAdder ebfa2(sum[15:8], caux2, in1[15:8], in2[15:8], caux1);
	eightBitFullAdder ebfa3(sum[23:16], caux3, in1[23:16], in2[23:16], caux2);
	eightBitFullAdder ebfa4(sum[31:24], carry, in1[31:24], in2[31:24], caux3);
	
endmodule