data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v
 line:20: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v:421: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 4 bits.\n                                                                                                                         : ... In instance DATA_CACHE\n     DataLine[DC_TagBits+DC_LRUBits-1:DC_TagBits] = 8-1;\n                                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v:175: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'UpdateData_LRU\' generates 1 bits.\n                                                                                                                         : ... In instance DATA_CACHE\n   temp = UpdateData_LRU(DC_LRU, Index); \n        ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v:272: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'UpdateData_LRU\' generates 1 bits.\n                                                                                                                         : ... In instance DATA_CACHE\n   temp = UpdateData_LRU(DC_LRU, Index);  \n        ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v:295: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'UpdateData_LRU\' generates 1 bits.\n                                                                                                                         : ... In instance DATA_CACHE\n   temp = UpdateData_LRU(DC_LRU, Index);  \n        ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v:325: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'UpdateData_LRU\' generates 1 bits.\n                                                                                                                         : ... In instance DATA_CACHE\n   temp = UpdateData_LRU(DC_LRU, Index);  \n        ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v:339: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'w\' generates 32 bits.\n                                                                                                                         : ... In instance DATA_CACHE\n     DataLine[DC_TagBits + DC_LRUBits-1 : DC_TagBits] = w;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v:372: Operator NEQ expects 12 bits on the RHS, but RHS\'s CONST \'8\'h78\' generates 8 bits.\n                                                                                                                         : ... In instance DATA_CACHE\n     if(print == TRUE || MESI_Bits != Invalid || DC_Tag != "x")\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v:440: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h49\' generates 8 bits.\n                                                                                                                         : ... In instance DATA_CACHE\n   2\'b00: Get_MESI_ID = "I";\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v:441: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h45\' generates 8 bits.\n                                                                                                                         : ... In instance DATA_CACHE\n   2\'b01: Get_MESI_ID = "E";\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v:442: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h53\' generates 8 bits.\n                                                                                                                         : ... In instance DATA_CACHE\n   2\'b10: Get_MESI_ID = "S";\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/DataCache.v:443: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h4d\' generates 8 bits.\n                                                                                                                         : ... In instance DATA_CACHE\n   2\'b11: Get_MESI_ID = "M";\n                      ^\n%Error: Exiting due to 11 warning(s)\n'
function UpdateData_LRU;
		input [DC_LRUBits-1:0] LRU;
		input [DC_IndexBits-1:0] index;
		
		integer w;

		begin 

			for (w=0; w<`DataCacheWay; w=w+1)
			begin
				DataLine = DataCache[w][index];
				DC_LRU = DataLine[DC_TagBits+DC_LRUBits-1:DC_TagBits];

				if(DC_LRU == LRU)
				begin
					DataLine[DC_TagBits+DC_LRUBits-1:DC_TagBits] = `DataCacheWay-1;
					DataCache[w][index] = DataLine;
				end

				else if(DC_LRU > LRU)
				begin
					DataLine[DC_TagBits+DC_LRUBits-1:DC_TagBits] = DC_LRU-1;
					DataCache[w][index] = DataLine;
				end
			end
		end
	endfunction
function UpdateData_LRU;

		input [DC_LRUBits-1:0] LRU;
		input [DC_IndexBits-1:0] index;
		
		integer w;

		begin 

			for (w=0; w<`DataCacheWay; w=w+1)
			begin
				DataLine = DataCache[w][index];
				DC_LRU = DataLine[DC_TagBits+DC_LRUBits-1:DC_TagBits];

				if(DC_LRU == LRU)
				begin
					DataLine[DC_TagBits+DC_LRUBits-1:DC_TagBits] = `DataCacheWay-1;
					DataCache[w][index] = DataLine;
				end

				else if(DC_LRU > LRU)
				begin
					DataLine[DC_TagBits+DC_LRUBits-1:DC_TagBits] = DC_LRU-1;
					DataCache[w][index] = DataLine;
				end
			end
		end
	endfunction