data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v
 line:266: before: "function"
1: b'%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:43: Cannot find include file: trellis.vh\n`include "trellis.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh.v\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh.sv\n             trellis.vh\n             trellis.vh.v\n             trellis.vh.sv\n             obj_dir/trellis.vh\n             obj_dir/trellis.vh.v\n             obj_dir/trellis.vh.sv\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:57: Define or directive not defined: \'`SIG_ADDR_W\'\n     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      WR_ADDR,  \n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:57: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      WR_ADDR,  \n                                   ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:58: Define or directive not defined: \'`SIG_LEN_W\'\n     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       WR_LEN,  \n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:66: Define or directive not defined: \'`SIG_ADDR_W\'\n     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      RD_ADDR,  \n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:67: Define or directive not defined: \'`SIG_LEN_W\'\n     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       RD_LEN,  \n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:88: Define or directive not defined: \'`SIG_FBE_W\'\n     output [`SIG_FBE_W-1:0]                   TXR_META_FDWBE, \n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:89: Define or directive not defined: \'`SIG_LBE_W\'\n     output [`SIG_LBE_W-1:0]                   TXR_META_LDWBE,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:90: Define or directive not defined: \'`SIG_ADDR_W\'\n     output [`SIG_ADDR_W-1:0]                  TXR_META_ADDR,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:91: Define or directive not defined: \'`SIG_LEN_W\'\n     output [`SIG_LEN_W-1:0]                   TXR_META_LENGTH,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:92: Define or directive not defined: \'`SIG_TAG_W\'\n     output [`SIG_TAG_W-1:0]                   TXR_META_TAG,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:93: Define or directive not defined: \'`SIG_TC_W\'\n     output [`SIG_TC_W-1:0]                    TXR_META_TC,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:94: Define or directive not defined: \'`SIG_ATTR_W\'\n     output [`SIG_ATTR_W-1:0]                  TXR_META_ATTR,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:95: Define or directive not defined: \'`SIG_TYPE_W\'\n     output [`SIG_TYPE_W-1:0]                  TXR_META_TYPE,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:108: syntax error, unexpected always\n    always @(*) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:173: Define or directive not defined: \'`SIG_FBE_W\'\n                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:174: Define or directive not defined: \'`SIG_LBE_W\'\n                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:175: Define or directive not defined: \'`SIG_ADDR_W\'\n                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:176: Define or directive not defined: \'`SIG_LEN_W\'\n                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:177: Define or directive not defined: \'`SIG_TAG_W\'\n                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:178: Define or directive not defined: \'`SIG_TC_W\'\n                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:179: Define or directive not defined: \'`SIG_ATTR_W\'\n                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:180: Define or directive not defined: \'`SIG_TYPE_W\'\n                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:186: Define or directive not defined: \'`SIG_ADDR_W\'\n                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),\n                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:187: Define or directive not defined: \'`SIG_LEN_W\'\n                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),\n                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:191: Define or directive not defined: \'`SIG_ADDR_W\'\n                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),\n                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:192: Define or directive not defined: \'`SIG_LEN_W\'\n                 .RD_LEN                (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),\n                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:224: Define or directive not defined: \'`SIG_FBE_W\'\n                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:225: Define or directive not defined: \'`SIG_LBE_W\'\n                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:226: Define or directive not defined: \'`SIG_ADDR_W\'\n                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:227: Define or directive not defined: \'`SIG_LEN_W\'\n                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:228: Define or directive not defined: \'`SIG_TAG_W\'\n                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:229: Define or directive not defined: \'`SIG_TC_W\'\n                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:230: Define or directive not defined: \'`SIG_ATTR_W\'\n                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:231: Define or directive not defined: \'`SIG_TYPE_W\'\n                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:237: Define or directive not defined: \'`SIG_ADDR_W\'\n                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),\n                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:238: Define or directive not defined: \'`SIG_LEN_W\'\n                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),\n                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:242: Define or directive not defined: \'`SIG_ADDR_W\'\n                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),\n                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:243: Define or directive not defined: \'`SIG_LEN_W\'\n                 .RD_LEN                (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),\n                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:275: Define or directive not defined: \'`SIG_FBE_W\'\n                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:276: Define or directive not defined: \'`SIG_LBE_W\'\n                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:277: Define or directive not defined: \'`SIG_ADDR_W\'\n                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:278: Define or directive not defined: \'`SIG_LEN_W\'\n                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:279: Define or directive not defined: \'`SIG_TAG_W\'\n                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:280: Define or directive not defined: \'`SIG_TC_W\'\n                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:281: Define or directive not defined: \'`SIG_ATTR_W\'\n                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:282: Define or directive not defined: \'`SIG_TYPE_W\'\n                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:288: Define or directive not defined: \'`SIG_ADDR_W\'\n                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),\n                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:289: Define or directive not defined: \'`SIG_LEN_W\'\n                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),\n                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/tx_multiplexer.v:293: Define or directive not defined: \'`SIG_ADDR_W\'\n                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),\n                                                             ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module tx_multiplexer
    #(
      parameter C_PCI_DATA_WIDTH = 128,
      parameter C_NUM_CHNL = 12,
      parameter C_TAG_WIDTH = 5,
      parameter C_VENDOR = "ALTERA",
      parameter C_DEPTH_PACKETS = 10
      )
    (
     input                                     CLK,
     input                                     RST_IN,

     input [C_NUM_CHNL-1:0]                    WR_REQ,
     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      WR_ADDR,
     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       WR_LEN,
     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA,
     output [C_NUM_CHNL-1:0]                   WR_DATA_REN,
     output [C_NUM_CHNL-1:0]                   WR_ACK,
     output [C_NUM_CHNL-1:0]                   WR_SENT,
     
     input [C_NUM_CHNL-1:0]                    RD_REQ,
     input [(C_NUM_CHNL*2)-1:0]                RD_SG_CHNL,
     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      RD_ADDR,
     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       RD_LEN,
     output [C_NUM_CHNL-1:0]                   RD_ACK,

     output [5:0]                              INT_TAG,
     output                                    INT_TAG_VALID,
     input [C_TAG_WIDTH-1:0]                   EXT_TAG,
     input                                     EXT_TAG_VALID,

     output                                    TX_ENG_RD_REQ_SENT,
     input                                     RXBUF_SPACE_AVAIL,
     

     output                                    TXR_DATA_VALID,
     output [C_PCI_DATA_WIDTH-1:0]             TXR_DATA,
     output                                    TXR_DATA_START_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_START_OFFSET,
     output                                    TXR_DATA_END_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_END_OFFSET,
     input                                     TXR_DATA_READY,

     output                                    TXR_META_VALID,
     output [`SIG_FBE_W-1:0]                   TXR_META_FDWBE, 
     output [`SIG_LBE_W-1:0]                   TXR_META_LDWBE,
     output [`SIG_ADDR_W-1:0]                  TXR_META_ADDR,
     output [`SIG_LEN_W-1:0]                   TXR_META_LENGTH,
     output [`SIG_TAG_W-1:0]                   TXR_META_TAG,
     output [`SIG_TC_W-1:0]                    TXR_META_TC,
     output [`SIG_ATTR_W-1:0]                  TXR_META_ATTR,
     output [`SIG_TYPE_W-1:0]                  TXR_META_TYPE,
     output                                    TXR_META_EP,
     input                                     TXR_META_READY,
     input                                     TXR_SENT);

    wire [C_NUM_CHNL-1:0]                      wAckRdData;
    wire                                       wAckValid;
                                      
    reg [C_NUM_CHNL-1:0]                       rAckWrData;
    reg [C_NUM_CHNL-1:0]                       rAckRdData;
    reg                                        rAckWrEn,_rAckWrEn;
    reg                                        rAckRdEn;

    always @(*) begin
        _rAckWrEn = (WR_ACK != 0) | (RD_ACK != 0);
    end

    always @(posedge CLK) begin
        rAckWrData <= WR_ACK;
        rAckWrEn <= _rAckWrEn;
    end    

    always @(posedge CLK) begin
        rAckRdEn <= TXR_SENT;
        if(rAckRdEn & wAckValid) begin
            rAckRdData <= wAckRdData;
        end else begin
            rAckRdData <= 0;
        end
    end

    assign WR_SENT = rAckRdData;
    
    fifo
        #(
          .C_WIDTH                      (C_NUM_CHNL),
          .C_DEPTH                      (C_DEPTH_PACKETS*8),
          .C_DELAY                      (0)
)
    req_ack_fifo
        (
         .WR_READY                      (),
         .RD_DATA                       (wAckRdData),
         .RD_VALID                      (wAckValid),

         .WR_DATA                       (rAckWrData),
         .WR_VALID                      (rAckWrEn),
         .RD_READY                      (rAckRdEn),
         .RST                           (RST_IN),


         .CLK                           (CLK));

    generate
        if(C_PCI_DATA_WIDTH == 32) begin
            tx_multiplexer_32 
                #(

                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
                  .C_NUM_CHNL           (C_NUM_CHNL),
                  .C_TAG_WIDTH          (C_TAG_WIDTH),
                  .C_VENDOR             (C_VENDOR))
            tx_mux 
                (

                 .WR_DATA_REN           (WR_DATA_REN[C_NUM_CHNL-1:0]),
                 .WR_ACK                (WR_ACK[C_NUM_CHNL-1:0]),
                 .RD_ACK                (RD_ACK[C_NUM_CHNL-1:0]),
                 .INT_TAG               (INT_TAG[5:0]),
                 .INT_TAG_VALID         (INT_TAG_VALID),
                 .TX_ENG_RD_REQ_SENT    (TX_ENG_RD_REQ_SENT),
                 .TXR_DATA_VALID        (TXR_DATA_VALID),
                 .TXR_DATA              (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
                 .TXR_DATA_START_FLAG   (TXR_DATA_START_FLAG),
                 .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_DATA_END_FLAG     (TXR_DATA_END_FLAG),
                 .TXR_DATA_END_OFFSET   (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_META_VALID        (TXR_META_VALID),
                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),
                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),
                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
                 .TXR_META_EP           (TXR_META_EP),

                 .CLK                   (CLK),
                 .RST_IN                (RST_IN),
                 .WR_REQ                (WR_REQ[C_NUM_CHNL-1:0]),
                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .WR_DATA               (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
                 .RD_REQ                (RD_REQ[C_NUM_CHNL-1:0]),
                 .RD_SG_CHNL            (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .RD_LEN                (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .EXT_TAG               (EXT_TAG[C_TAG_WIDTH-1:0]),
                 .EXT_TAG_VALID         (EXT_TAG_VALID),
                 .RXBUF_SPACE_AVAIL     (RXBUF_SPACE_AVAIL),
                 .TXR_DATA_READY        (TXR_DATA_READY),
                 .TXR_META_READY        (TXR_META_READY));
            
        end else if(C_PCI_DATA_WIDTH == 64) begin

            tx_multiplexer_64 
                #(

                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
                  .C_NUM_CHNL           (C_NUM_CHNL),
                  .C_TAG_WIDTH          (C_TAG_WIDTH),
                  .C_VENDOR             (C_VENDOR))
            tx_mux 
                (

                 .WR_DATA_REN           (WR_DATA_REN[C_NUM_CHNL-1:0]),
                 .WR_ACK                (WR_ACK[C_NUM_CHNL-1:0]),
                 .RD_ACK                (RD_ACK[C_NUM_CHNL-1:0]),
                 .INT_TAG               (INT_TAG[5:0]),
                 .INT_TAG_VALID         (INT_TAG_VALID),
                 .TX_ENG_RD_REQ_SENT    (TX_ENG_RD_REQ_SENT),
                 .TXR_DATA_VALID        (TXR_DATA_VALID),
                 .TXR_DATA              (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
                 .TXR_DATA_START_FLAG   (TXR_DATA_START_FLAG),
                 .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_DATA_END_FLAG     (TXR_DATA_END_FLAG),
                 .TXR_DATA_END_OFFSET   (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_META_VALID        (TXR_META_VALID),
                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),
                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),
                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
                 .TXR_META_EP           (TXR_META_EP),

                 .CLK                   (CLK),
                 .RST_IN                (RST_IN),
                 .WR_REQ                (WR_REQ[C_NUM_CHNL-1:0]),
                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .WR_DATA               (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
                 .RD_REQ                (RD_REQ[C_NUM_CHNL-1:0]),
                 .RD_SG_CHNL            (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .RD_LEN                (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .EXT_TAG               (EXT_TAG[C_TAG_WIDTH-1:0]),
                 .EXT_TAG_VALID         (EXT_TAG_VALID),
                 .RXBUF_SPACE_AVAIL     (RXBUF_SPACE_AVAIL),
                 .TXR_DATA_READY        (TXR_DATA_READY),
                 .TXR_META_READY        (TXR_META_READY));

        end else if(C_PCI_DATA_WIDTH == 128) begin

            tx_multiplexer_128
                #(

                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
                  .C_NUM_CHNL           (C_NUM_CHNL),
                  .C_TAG_WIDTH          (C_TAG_WIDTH),
                  .C_VENDOR             (C_VENDOR))
            tx_mux_128_inst
                (

                 .WR_DATA_REN           (WR_DATA_REN[C_NUM_CHNL-1:0]),
                 .WR_ACK                (WR_ACK[C_NUM_CHNL-1:0]),
                 .RD_ACK                (RD_ACK[C_NUM_CHNL-1:0]),
                 .INT_TAG               (INT_TAG[5:0]),
                 .INT_TAG_VALID         (INT_TAG_VALID),
                 .TX_ENG_RD_REQ_SENT    (TX_ENG_RD_REQ_SENT),
                 .TXR_DATA_VALID        (TXR_DATA_VALID),
                 .TXR_DATA              (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
                 .TXR_DATA_START_FLAG   (TXR_DATA_START_FLAG),
                 .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_DATA_END_FLAG     (TXR_DATA_END_FLAG),
                 .TXR_DATA_END_OFFSET   (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_META_VALID        (TXR_META_VALID),
                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),
                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),
                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
                 .TXR_META_EP           (TXR_META_EP),

                 .CLK                   (CLK),
                 .RST_IN                (RST_IN),
                 .WR_REQ                (WR_REQ[C_NUM_CHNL-1:0]),
                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .WR_DATA               (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
                 .RD_REQ                (RD_REQ[C_NUM_CHNL-1:0]),
                 .RD_SG_CHNL            (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .RD_LEN                (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .EXT_TAG               (EXT_TAG[C_TAG_WIDTH-1:0]),
                 .EXT_TAG_VALID         (EXT_TAG_VALID),
                 .RXBUF_SPACE_AVAIL     (RXBUF_SPACE_AVAIL),
                 .TXR_DATA_READY        (TXR_DATA_READY),
                 .TXR_META_READY        (TXR_META_READY));

        end 
    endgenerate
endmodule
module tx_multiplexer
    #(
      parameter C_PCI_DATA_WIDTH = 128,
      parameter C_NUM_CHNL = 12,
      parameter C_TAG_WIDTH = 5,
      parameter C_VENDOR = "ALTERA",
      parameter C_DEPTH_PACKETS = 10
      )
    (
     input                                     CLK,
     input                                     RST_IN,

     input [C_NUM_CHNL-1:0]                    WR_REQ,
     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      WR_ADDR,
     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       WR_LEN,
     input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA,
     output [C_NUM_CHNL-1:0]                   WR_DATA_REN,
     output [C_NUM_CHNL-1:0]                   WR_ACK,
     output [C_NUM_CHNL-1:0]                   WR_SENT,
     
     input [C_NUM_CHNL-1:0]                    RD_REQ,
     input [(C_NUM_CHNL*2)-1:0]                RD_SG_CHNL,
     input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0]      RD_ADDR,
     input [(C_NUM_CHNL*`SIG_LEN_W)-1:0]       RD_LEN,
     output [C_NUM_CHNL-1:0]                   RD_ACK,

     output [5:0]                              INT_TAG,
     output                                    INT_TAG_VALID,
     input [C_TAG_WIDTH-1:0]                   EXT_TAG,
     input                                     EXT_TAG_VALID,

     output                                    TX_ENG_RD_REQ_SENT,
     input                                     RXBUF_SPACE_AVAIL,
     

     output                                    TXR_DATA_VALID,
     output [C_PCI_DATA_WIDTH-1:0]             TXR_DATA,
     output                                    TXR_DATA_START_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_START_OFFSET,
     output                                    TXR_DATA_END_FLAG,
     output [clog2s(C_PCI_DATA_WIDTH/32)-1:0]  TXR_DATA_END_OFFSET,
     input                                     TXR_DATA_READY,

     output                                    TXR_META_VALID,
     output [`SIG_FBE_W-1:0]                   TXR_META_FDWBE, 
     output [`SIG_LBE_W-1:0]                   TXR_META_LDWBE,
     output [`SIG_ADDR_W-1:0]                  TXR_META_ADDR,
     output [`SIG_LEN_W-1:0]                   TXR_META_LENGTH,
     output [`SIG_TAG_W-1:0]                   TXR_META_TAG,
     output [`SIG_TC_W-1:0]                    TXR_META_TC,
     output [`SIG_ATTR_W-1:0]                  TXR_META_ATTR,
     output [`SIG_TYPE_W-1:0]                  TXR_META_TYPE,
     output                                    TXR_META_EP,
     input                                     TXR_META_READY,
     input                                     TXR_SENT);


    wire [C_NUM_CHNL-1:0]                      wAckRdData;
    wire                                       wAckValid;
                                      
    reg [C_NUM_CHNL-1:0]                       rAckWrData;
    reg [C_NUM_CHNL-1:0]                       rAckRdData;
    reg                                        rAckWrEn,_rAckWrEn;
    reg                                        rAckRdEn;

    always @(*) begin
        _rAckWrEn = (WR_ACK != 0) | (RD_ACK != 0);
    end

    always @(posedge CLK) begin
        rAckWrData <= WR_ACK;
        rAckWrEn <= _rAckWrEn;
    end    

    always @(posedge CLK) begin
        rAckRdEn <= TXR_SENT;
        if(rAckRdEn & wAckValid) begin
            rAckRdData <= wAckRdData;
        end else begin
            rAckRdData <= 0;
        end
    end

    assign WR_SENT = rAckRdData;
    
    fifo
        #(
          .C_WIDTH                      (C_NUM_CHNL),
          .C_DEPTH                      (C_DEPTH_PACKETS*8),
          .C_DELAY                      (0)
)
    req_ack_fifo
        (
         .WR_READY                      (),
         .RD_DATA                       (wAckRdData),
         .RD_VALID                      (wAckValid),

         .WR_DATA                       (rAckWrData),
         .WR_VALID                      (rAckWrEn),
         .RD_READY                      (rAckRdEn),
         .RST                           (RST_IN),


         .CLK                           (CLK));

    generate
        if(C_PCI_DATA_WIDTH == 32) begin
            tx_multiplexer_32 
                #(

                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
                  .C_NUM_CHNL           (C_NUM_CHNL),
                  .C_TAG_WIDTH          (C_TAG_WIDTH),
                  .C_VENDOR             (C_VENDOR))
            tx_mux 
                (

                 .WR_DATA_REN           (WR_DATA_REN[C_NUM_CHNL-1:0]),
                 .WR_ACK                (WR_ACK[C_NUM_CHNL-1:0]),
                 .RD_ACK                (RD_ACK[C_NUM_CHNL-1:0]),
                 .INT_TAG               (INT_TAG[5:0]),
                 .INT_TAG_VALID         (INT_TAG_VALID),
                 .TX_ENG_RD_REQ_SENT    (TX_ENG_RD_REQ_SENT),
                 .TXR_DATA_VALID        (TXR_DATA_VALID),
                 .TXR_DATA              (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
                 .TXR_DATA_START_FLAG   (TXR_DATA_START_FLAG),
                 .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_DATA_END_FLAG     (TXR_DATA_END_FLAG),
                 .TXR_DATA_END_OFFSET   (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_META_VALID        (TXR_META_VALID),
                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),
                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),
                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
                 .TXR_META_EP           (TXR_META_EP),

                 .CLK                   (CLK),
                 .RST_IN                (RST_IN),
                 .WR_REQ                (WR_REQ[C_NUM_CHNL-1:0]),
                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .WR_DATA               (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
                 .RD_REQ                (RD_REQ[C_NUM_CHNL-1:0]),
                 .RD_SG_CHNL            (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .RD_LEN                (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .EXT_TAG               (EXT_TAG[C_TAG_WIDTH-1:0]),
                 .EXT_TAG_VALID         (EXT_TAG_VALID),
                 .RXBUF_SPACE_AVAIL     (RXBUF_SPACE_AVAIL),
                 .TXR_DATA_READY        (TXR_DATA_READY),
                 .TXR_META_READY        (TXR_META_READY));
            
        end else if(C_PCI_DATA_WIDTH == 64) begin

            tx_multiplexer_64 
                #(

                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
                  .C_NUM_CHNL           (C_NUM_CHNL),
                  .C_TAG_WIDTH          (C_TAG_WIDTH),
                  .C_VENDOR             (C_VENDOR))
            tx_mux 
                (

                 .WR_DATA_REN           (WR_DATA_REN[C_NUM_CHNL-1:0]),
                 .WR_ACK                (WR_ACK[C_NUM_CHNL-1:0]),
                 .RD_ACK                (RD_ACK[C_NUM_CHNL-1:0]),
                 .INT_TAG               (INT_TAG[5:0]),
                 .INT_TAG_VALID         (INT_TAG_VALID),
                 .TX_ENG_RD_REQ_SENT    (TX_ENG_RD_REQ_SENT),
                 .TXR_DATA_VALID        (TXR_DATA_VALID),
                 .TXR_DATA              (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
                 .TXR_DATA_START_FLAG   (TXR_DATA_START_FLAG),
                 .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_DATA_END_FLAG     (TXR_DATA_END_FLAG),
                 .TXR_DATA_END_OFFSET   (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_META_VALID        (TXR_META_VALID),
                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),
                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),
                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
                 .TXR_META_EP           (TXR_META_EP),

                 .CLK                   (CLK),
                 .RST_IN                (RST_IN),
                 .WR_REQ                (WR_REQ[C_NUM_CHNL-1:0]),
                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .WR_DATA               (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
                 .RD_REQ                (RD_REQ[C_NUM_CHNL-1:0]),
                 .RD_SG_CHNL            (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .RD_LEN                (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .EXT_TAG               (EXT_TAG[C_TAG_WIDTH-1:0]),
                 .EXT_TAG_VALID         (EXT_TAG_VALID),
                 .RXBUF_SPACE_AVAIL     (RXBUF_SPACE_AVAIL),
                 .TXR_DATA_READY        (TXR_DATA_READY),
                 .TXR_META_READY        (TXR_META_READY));

        end else if(C_PCI_DATA_WIDTH == 128) begin

            tx_multiplexer_128
                #(

                  .C_PCI_DATA_WIDTH     (C_PCI_DATA_WIDTH),
                  .C_NUM_CHNL           (C_NUM_CHNL),
                  .C_TAG_WIDTH          (C_TAG_WIDTH),
                  .C_VENDOR             (C_VENDOR))
            tx_mux_128_inst
                (

                 .WR_DATA_REN           (WR_DATA_REN[C_NUM_CHNL-1:0]),
                 .WR_ACK                (WR_ACK[C_NUM_CHNL-1:0]),
                 .RD_ACK                (RD_ACK[C_NUM_CHNL-1:0]),
                 .INT_TAG               (INT_TAG[5:0]),
                 .INT_TAG_VALID         (INT_TAG_VALID),
                 .TX_ENG_RD_REQ_SENT    (TX_ENG_RD_REQ_SENT),
                 .TXR_DATA_VALID        (TXR_DATA_VALID),
                 .TXR_DATA              (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
                 .TXR_DATA_START_FLAG   (TXR_DATA_START_FLAG),
                 .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_DATA_END_FLAG     (TXR_DATA_END_FLAG),
                 .TXR_DATA_END_OFFSET   (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
                 .TXR_META_VALID        (TXR_META_VALID),
                 .TXR_META_FDWBE        (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
                 .TXR_META_LDWBE        (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
                 .TXR_META_ADDR         (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
                 .TXR_META_LENGTH       (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
                 .TXR_META_TAG          (TXR_META_TAG[`SIG_TAG_W-1:0]),
                 .TXR_META_TC           (TXR_META_TC[`SIG_TC_W-1:0]),
                 .TXR_META_ATTR         (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
                 .TXR_META_TYPE         (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
                 .TXR_META_EP           (TXR_META_EP),

                 .CLK                   (CLK),
                 .RST_IN                (RST_IN),
                 .WR_REQ                (WR_REQ[C_NUM_CHNL-1:0]),
                 .WR_ADDR               (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .WR_LEN                (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .WR_DATA               (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
                 .RD_REQ                (RD_REQ[C_NUM_CHNL-1:0]),
                 .RD_SG_CHNL            (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
                 .RD_ADDR               (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
                 .RD_LEN                (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
                 .EXT_TAG               (EXT_TAG[C_TAG_WIDTH-1:0]),
                 .EXT_TAG_VALID         (EXT_TAG_VALID),
                 .RXBUF_SPACE_AVAIL     (RXBUF_SPACE_AVAIL),
                 .TXR_DATA_READY        (TXR_DATA_READY),
                 .TXR_META_READY        (TXR_META_READY));

        end 
    endgenerate
endmodule