data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_controller.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_controller.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = 32\'h08000c05;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_controller.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = 32\'h20110001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_controller.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = 32\'h20120002;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_controller.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = 32\'h20130003;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_controller.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = 32\'h08000c09;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_controller.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = 32\'h20110001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_controller.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = 32\'h20120002;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_controller.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = 32\'h20130003;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_controller.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10 instruction = 32\'h08000c0d;\n        ^\n%Error: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_controller.v:33: Cannot find file containing module: \'ControlUnit\'\n    ControlUnit contorller(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/ControlUnit\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/ControlUnit.v\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/ControlUnit.sv\n             ControlUnit\n             ControlUnit.v\n             ControlUnit.sv\n             obj_dir/ControlUnit\n             obj_dir/ControlUnit.v\n             obj_dir/ControlUnit.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_controller;
    reg [31:0] instruction;
    wire jmp, jr, signedext, beq, bne, memtoreg, memwrite, alusrcb, regwrite, jal, regdst, syscall;
    wire [3:0] AluOP;

    initial begin
        instruction = 32'h20110001;
        #10 instruction = 32'h08000c05;
        #10 instruction = 32'h20110001;
        #10 instruction = 32'h20120002;
        #10 instruction = 32'h20130003;
        #10 instruction = 32'h08000c09;
        #10 instruction = 32'h20110001;
        #10 instruction = 32'h20120002;
        #10 instruction = 32'h20130003;
        #10 instruction = 32'h08000c0d;
    end

    ControlUnit contorller(
        .opcode(instruction[31:26]), .func(instruction[5:0]),
        .JMP(jmp), .JR(jr), .SignedExt(signedext),
        .Beq(beq), .Bne(bne), .MemToReg(memtoreg), .MemWrite(memwrite),
        .AluSrcB(alusrcb), .RegWrite(regwrite), .JAL(jal),
        .RegDst(regdst), .Syscall(syscall),
        .AluOP(AluOP)
    );
endmodule
module test_controller;

    reg [31:0] instruction;
    wire jmp, jr, signedext, beq, bne, memtoreg, memwrite, alusrcb, regwrite, jal, regdst, syscall;
    wire [3:0] AluOP;

    initial begin
        instruction = 32'h20110001;
        #10 instruction = 32'h08000c05;
        #10 instruction = 32'h20110001;
        #10 instruction = 32'h20120002;
        #10 instruction = 32'h20130003;
        #10 instruction = 32'h08000c09;
        #10 instruction = 32'h20110001;
        #10 instruction = 32'h20120002;
        #10 instruction = 32'h20130003;
        #10 instruction = 32'h08000c0d;
    end

    ControlUnit contorller(
        .opcode(instruction[31:26]), .func(instruction[5:0]),
        .JMP(jmp), .JR(jr), .SignedExt(signedext),
        .Beq(beq), .Bne(bne), .MemToReg(memtoreg), .MemWrite(memwrite),
        .AluSrcB(alusrcb), .RegWrite(regwrite), .JAL(jal),
        .RegDst(regdst), .Syscall(syscall),
        .AluOP(AluOP)
    );
endmodule