data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/adder.v
data/verilator_xmls/79a0ccbd-4162-43ae-b320-71a44b7d2084.xml
module ADDF(
  input [0:0] A,
  input [0:0] B,
  input [0:0] CI,
  output [0:0] CO,
  output [0:0] SUM
);
  assign SUM = A ^ B ^ CI;
  assign CO = (A & B) | (A & CI) | (B & CI); 
endmodule
module ADDF(
  input [0:0] A,
  input [0:0] B,
  input [0:0] CI,
  output [0:0] CO,
  output [0:0] SUM
);

  assign SUM = A ^ B ^ CI;
  assign CO = (A & B) | (A & CI) | (B & CI); 
endmodule