data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/fifo_ptr.v
 line:58: before: "integer"
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/fifo_ptr.v:35: Cannot find include file: graycode.vh\n`include "graycode.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/graycode.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/graycode.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/graycode.vh.sv\n             graycode.vh\n             graycode.vh.v\n             graycode.vh.sv\n             obj_dir/graycode.vh\n             obj_dir/graycode.vh.v\n             obj_dir/graycode.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module fifo_ptr #(
  parameter AddrBits = 8)
(
  input                   clk,
  input                   rst,
  input                   inc,
  output reg [AddrBits:0] pbin,
  output     [AddrBits:0] pbin_next,
  output reg [AddrBits:0] pgray,
  output     [AddrBits:0] pgray_next);

`include "graycode.vh"

  always @(posedge clk) begin
    if (rst) pbin <= 0;
    else     pbin <= pbin_next;
  end




  always @(posedge clk or posedge rst) begin
    if (rst) pgray <= 0;
    else     pgray <= pgray_next;
  end

  assign pbin_next  = pbin + inc;
  assign pgray_next = bin2gray(pbin_next);

endmodule
module fifo_ptr #(
  parameter AddrBits = 8)
(
  input                   clk,
  input                   rst,
  input                   inc,
  output reg [AddrBits:0] pbin,
  output     [AddrBits:0] pbin_next,
  output reg [AddrBits:0] pgray,
  output     [AddrBits:0] pgray_next);


`include "graycode.vh"

  always @(posedge clk) begin
    if (rst) pbin <= 0;
    else     pbin <= pbin_next;
  end




  always @(posedge clk or posedge rst) begin
    if (rst) pgray <= 0;
    else     pgray <= pgray_next;
  end

  assign pbin_next  = pbin + inc;
  assign pgray_next = bin2gray(pbin_next);

endmodule