data/full_repos/permissive/108500919/proc_tb.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108500919/proc_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Error: data/full_repos/permissive/108500919/proc_tb.v:32: Cannot find file containing module: \'proc\'\n proc uut(\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/proc\n             data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/proc.v\n             data/full_repos/permissive/108500919,data/full_repos/permissive/108500919/proc.sv\n             proc\n             proc.v\n             proc.sv\n             obj_dir/proc\n             obj_dir/proc.v\n             obj_dir/proc.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module proc_tb( );
    reg [15:0] x;
    reg [15:0] x_init;
    reg  [15:0] a;
    reg reset;
    reg clk;
    wire [15:0] y;


	proc uut(
		.x(x),
		.x_init(x_init),
		.a(a),
		.reset(reset),
		.clk(clk),
		.y(y)
	);

	always begin
		clk =1'b1;
		#50;
		clk =1'b0;
		#50;
		end

initial begin
	reset = 1'b1;
	#50;
	reset = 1'b0;
	#50;
	a  = 16'h0003;
	x_init = 16'h0002;
	x  = 16'h0001;
	#100;

		
	#100;
end

endmodule
module proc_tb( );

    reg [15:0] x;
    reg [15:0] x_init;
    reg  [15:0] a;
    reg reset;
    reg clk;
    wire [15:0] y;


	proc uut(
		.x(x),
		.x_init(x_init),
		.a(a),
		.reset(reset),
		.clk(clk),
		.y(y)
	);

	always begin
		clk =1'b1;
		#50;
		clk =1'b0;
		#50;
		end

initial begin
	reset = 1'b1;
	#50;
	reset = 1'b0;
	#50;
	a  = 16'h0003;
	x_init = 16'h0002;
	x  = 16'h0001;
	#100;

		
	#100;
end

endmodule