data/full_repos/permissive/169738435/System/c1_regs.v
data/verilator_xmls/145a6af9-7152-4181-9230-53b6261fe023.xml
module c1_regs(
	input nICOMZONE,
	input RW,
	inout [15:8] M68K_DATA,
	inout [7:0] SDD,
	input nSDZ80R, nSDZ80W, nSDZ80CLR,
	output nSDW
);

	reg [7:0] SDD_LATCH_CMD;
	reg [7:0] SDD_LATCH_REP;
	

	assign SDD = nSDZ80R ? 8'bzzzzzzzz : SDD_LATCH_CMD;
	

	always @(posedge nSDZ80W)
	begin
		SDD_LATCH_REP <= SDD;
	end
	

	assign M68K_DATA = (RW & ~nICOMZONE) ? SDD_LATCH_REP : 8'bzzzzzzzz;
	

	assign nSDW = (RW | nICOMZONE);
	

	always @(negedge nICOMZONE or negedge nSDZ80CLR)
	begin
		if (!nSDZ80CLR)
		begin
			SDD_LATCH_CMD <= 8'b00000000;
		end
		else
		begin
			if (!RW)
				SDD_LATCH_CMD <= M68K_DATA;
		end
	end
	
endmodule
module c1_regs(
	input nICOMZONE,
	input RW,
	inout [15:8] M68K_DATA,
	inout [7:0] SDD,
	input nSDZ80R, nSDZ80W, nSDZ80CLR,
	output nSDW
);


	reg [7:0] SDD_LATCH_CMD;
	reg [7:0] SDD_LATCH_REP;
	

	assign SDD = nSDZ80R ? 8'bzzzzzzzz : SDD_LATCH_CMD;
	

	always @(posedge nSDZ80W)
	begin
		SDD_LATCH_REP <= SDD;
	end
	

	assign M68K_DATA = (RW & ~nICOMZONE) ? SDD_LATCH_REP : 8'bzzzzzzzz;
	

	assign nSDW = (RW | nICOMZONE);
	

	always @(negedge nICOMZONE or negedge nSDZ80CLR)
	begin
		if (!nSDZ80CLR)
		begin
			SDD_LATCH_CMD <= 8'b00000000;
		end
		else
		begin
			if (!RW)
				SDD_LATCH_CMD <= M68K_DATA;
		end
	end
	
endmodule