data/full_repos/permissive/186491764/control2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/186491764/control2.v:26: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                  : ... In instance control2\n assign select = {ALUOpcodeX,Opcode};\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/186491764/control2.v:28: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h4\' generates 5 bits.\n                                                                  : ... In instance control2\n casex (select)\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/186491764/control2.v:28: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h5\' generates 5 bits.\n                                                                  : ... In instance control2\n casex (select)\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/186491764/control2.v:28: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'h6\' generates 5 bits.\n                                                                  : ... In instance control2\n casex (select)\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/186491764/control2.v:28: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'b10xxx\' generates 5 bits.\n                                                                  : ... In instance control2\n casex (select)\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/186491764/control2.v:28: Operator CASE expects 6 bits on the Case Item, but Case Item\'s CONST \'5\'b1xxx\' generates 5 bits.\n                                                                  : ... In instance control2\n casex (select)\n ^~~~~\n%Error: Exiting due to 6 warning(s)\n'
module control2(ALU_rep, ALUOpcodeX, Opcode);
output reg[1:0] ALU_rep;
 input [1:0] ALUOpcodeX;
 input [2:0] Opcode;
 wire [5:0] select;
 assign select = {ALUOpcodeX,Opcode};
 always @(select)
 casex (select)
   5'b00100: ALU_rep=2'b00;
   5'b00101: ALU_rep=2'b01;
   5'b00110: ALU_rep=2'b10;
   5'b10xxx: ALU_rep=2'b00;
   5'b01xxx: ALU_rep=2'b01;
	
  default: ALU_rep=2'b00;
  endcase
  
endmodule
module control2(ALU_rep, ALUOpcodeX, Opcode);

output reg[1:0] ALU_rep;
 input [1:0] ALUOpcodeX;
 input [2:0] Opcode;
 wire [5:0] select;
 assign select = {ALUOpcodeX,Opcode};
 always @(select)
 casex (select)
   5'b00100: ALU_rep=2'b00;
   5'b00101: ALU_rep=2'b01;
   5'b00110: ALU_rep=2'b10;
   5'b10xxx: ALU_rep=2'b00;
   5'b01xxx: ALU_rep=2'b01;
	
  default: ALU_rep=2'b00;
  endcase
  
endmodule