data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v
1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                         ^~~~~~\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                               ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                      ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                 ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                            ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                       ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                                  ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                                             ^\n%Error: Exiting due to 8 warning(s)\n'
module clkdiv(
    input mclk,
    output [2:0] clk_seg
    );
    reg [27:0] q;
    always@(posedge mclk)
         q<=q+1;
    assign clk_seg[0]=q[15];
    assign clk_seg[1]=q[16];
    assign clk_seg[2]=q[17];       
endmodule
module clkdiv(
    input mclk,
    output [2:0] clk_seg
    );

    reg [27:0] q;
    always@(posedge mclk)
         q<=q+1;
    assign clk_seg[0]=q[15];
    assign clk_seg[1]=q[16];
    assign clk_seg[2]=q[17];       
endmodule