data/full_repos/permissive/107007139/Lab 2/my_2_bit_full_adder_simulation.v
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/107007139\n        ... Looked in:\n             data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139\n             data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.v\n             data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.sv\n             2,data/full_repos/permissive/107007139\n             2,data/full_repos/permissive/107007139.v\n             2,data/full_repos/permissive/107007139.sv\n             obj_dir/2,data/full_repos/permissive/107007139\n             obj_dir/2,data/full_repos/permissive/107007139.v\n             obj_dir/2,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 2/my_2_bit_full_adder_simulation.v\n%Error: Exiting due to 3 error(s)\n'
module my_2_bit_full_adder_simulation(

    );
    

    reg [1:0] A;
    reg [1:0] B;
    reg CIN;
    

    wire COUT;
    wire [1:0] S;
    

    my_2_bit_full_adder dut(A, B, CIN, S, COUT);
    
    initial begin
        A = 2'b00; B = 2'b00; CIN = 1'b0; #10;
        A = 2'b00; B = 2'b01; CIN = 1'b0; #10;
        A = 2'b01; B = 2'b01; CIN = 1'b0; #10;
        A = 2'b01; B = 2'b01; CIN = 1'b1; #10;
    end
endmodule
module my_2_bit_full_adder_simulation(

    );

    

    reg [1:0] A;
    reg [1:0] B;
    reg CIN;
    

    wire COUT;
    wire [1:0] S;
    

    my_2_bit_full_adder dut(A, B, CIN, S, COUT);
    
    initial begin
        A = 2'b00; B = 2'b00; CIN = 1'b0; #10;
        A = 2'b00; B = 2'b01; CIN = 1'b0; #10;
        A = 2'b01; B = 2'b01; CIN = 1'b0; #10;
        A = 2'b01; B = 2'b01; CIN = 1'b1; #10;
    end
endmodule