data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/Write_Master/byte_enable_generator.v
data/verilator_xmls/8eeda7c9-42e4-4030-9ffd-e44cfef86957.xml
module byte_enable_generator (
  clk,
  reset,


  write_in,
  byteenable_in,
  waitrequest_out,


  byteenable_out,
  waitrequest_in
);

  parameter BYTEENABLE_WIDTH = 4;

  input clk;
  input reset;

  input write_in;
  input [BYTEENABLE_WIDTH-1:0] byteenable_in;
  output wire waitrequest_out;

  output wire [BYTEENABLE_WIDTH-1:0] byteenable_out;
  input waitrequest_in;


generate
  if (BYTEENABLE_WIDTH == 1)
  begin
      assign byteenable_out = byteenable_in;
      assign waitrequest_out = waitrequest_in;
  end
  else if (BYTEENABLE_WIDTH == 2)
  begin
      sixteen_bit_byteenable_FSM the_sixteen_bit_byteenable_FSM (
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );  
  end
  else if (BYTEENABLE_WIDTH == 4)
  begin
      thirty_two_bit_byteenable_FSM the_thirty_two_bit_byteenable_FSM(
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );  
  end
  else if (BYTEENABLE_WIDTH == 8)
  begin
      sixty_four_bit_byteenable_FSM the_sixty_four_bit_byteenable_FSM(
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );  
  end
  else if (BYTEENABLE_WIDTH == 16)
  begin
      one_hundred_twenty_eight_bit_byteenable_FSM the_one_hundred_twenty_eight_bit_byteenable_FSM(
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );  
  end
  else if (BYTEENABLE_WIDTH == 32)
  begin
      two_hundred_fifty_six_bit_byteenable_FSM the_two_hundred_fifty_six_bit_byteenable_FSM(
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );
  end
  else if (BYTEENABLE_WIDTH == 64)
  begin
      five_hundred_twelve_bit_byteenable_FSM the_five_hundred_twelve_bit_byteenable_FSM (
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );
  end
  else if (BYTEENABLE_WIDTH == 128)
  begin
      one_thousand_twenty_four_byteenable_FSM the_one_thousand_twenty_four_byteenable_FSM (
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );
  end
endgenerate

endmodule
module byte_enable_generator (
  clk,
  reset,


  write_in,
  byteenable_in,
  waitrequest_out,


  byteenable_out,
  waitrequest_in
);


  parameter BYTEENABLE_WIDTH = 4;

  input clk;
  input reset;

  input write_in;
  input [BYTEENABLE_WIDTH-1:0] byteenable_in;
  output wire waitrequest_out;

  output wire [BYTEENABLE_WIDTH-1:0] byteenable_out;
  input waitrequest_in;


generate
  if (BYTEENABLE_WIDTH == 1)
  begin
      assign byteenable_out = byteenable_in;
      assign waitrequest_out = waitrequest_in;
  end
  else if (BYTEENABLE_WIDTH == 2)
  begin
      sixteen_bit_byteenable_FSM the_sixteen_bit_byteenable_FSM (
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );  
  end
  else if (BYTEENABLE_WIDTH == 4)
  begin
      thirty_two_bit_byteenable_FSM the_thirty_two_bit_byteenable_FSM(
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );  
  end
  else if (BYTEENABLE_WIDTH == 8)
  begin
      sixty_four_bit_byteenable_FSM the_sixty_four_bit_byteenable_FSM(
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );  
  end
  else if (BYTEENABLE_WIDTH == 16)
  begin
      one_hundred_twenty_eight_bit_byteenable_FSM the_one_hundred_twenty_eight_bit_byteenable_FSM(
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );  
  end
  else if (BYTEENABLE_WIDTH == 32)
  begin
      two_hundred_fifty_six_bit_byteenable_FSM the_two_hundred_fifty_six_bit_byteenable_FSM(
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );
  end
  else if (BYTEENABLE_WIDTH == 64)
  begin
      five_hundred_twelve_bit_byteenable_FSM the_five_hundred_twelve_bit_byteenable_FSM (
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );
  end
  else if (BYTEENABLE_WIDTH == 128)
  begin
      one_thousand_twenty_four_byteenable_FSM the_one_thousand_twenty_four_byteenable_FSM (
        .clk (clk),
        .reset (reset),
        .write_in (write_in),
        .byteenable_in (byteenable_in),
        .waitrequest_out (waitrequest_out),
        .byteenable_out (byteenable_out),
        .waitrequest_in (waitrequest_in)
      );
  end
endgenerate

endmodule