data/full_repos/permissive/203526788/GoBoard/SPI_master/Once.v
 line:10: before: ")"
1: b"%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/Once.v:22: `ifdef not terminated at EOF\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/Once.v:10: syntax error, unexpected ')', expecting '['\n  );\n  ^\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/Once.v:14: syntax error, unexpected always\n  always @(posedge iClk)\n  ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module Once 
  (
	input iClk,
	input iEnable,
  output oOnceEnable,
  );

  reg curr=0;

  always @(posedge iClk)
  begin
      curr <= iEnable;
      oOnceEnable <= iEnable & !curr;
  end

endmodule
module Once 
  (
	input iClk,
	input iEnable,
  output oOnceEnable,
  );


  reg curr=0;

  always @(posedge iClk)
  begin
      curr <= iEnable;
      oOnceEnable <= iEnable & !curr;
  end

endmodule