data/full_repos/permissive/110151336/lab_05/src/10_ripple_carry_adder/common/ripple_carry_adder.v
1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/10_ripple_carry_adder/common/ripple_carry_adder.v:22: Cannot find file containing module: 'full_adder'\n            full_adder FA\n            ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/lab_05/src/10_ripple_carry_adder/common,data/full_repos/permissive/110151336/full_adder\n             data/full_repos/permissive/110151336/lab_05/src/10_ripple_carry_adder/common,data/full_repos/permissive/110151336/full_adder.v\n             data/full_repos/permissive/110151336/lab_05/src/10_ripple_carry_adder/common,data/full_repos/permissive/110151336/full_adder.sv\n             full_adder\n             full_adder.v\n             full_adder.sv\n             obj_dir/full_adder\n             obj_dir/full_adder.v\n             obj_dir/full_adder.sv\n%Error: Exiting due to 1 error(s)\n"
module ripple_carry_adder
# (
    parameter WIDTH = 8
)
(
    input                  carry_in,
    input  [WIDTH - 1 : 0] x,
    input  [WIDTH - 1 : 0] y,
    output [WIDTH - 1 : 0] z,
    output                 carry_out
);
    wire [WIDTH : 0] carry;
    
    assign carry[0] = carry_in; 
    
    generate
    
        genvar i;
    
        for (i = 0; i <= WIDTH - 1; i = i + 1)
        begin : stage
            full_adder FA
            (
                .x		   (x    [i]    ),
                .y         (y    [i]    ),
                .z         (z    [i]    ),
                .carry_in  (carry[i]    ),
                .carry_out (carry[i + 1])
            );
        end
    endgenerate
    
    assign carry_out = carry[WIDTH];

endmodule
module ripple_carry_adder
# (
    parameter WIDTH = 8
)
(
    input                  carry_in,
    input  [WIDTH - 1 : 0] x,
    input  [WIDTH - 1 : 0] y,
    output [WIDTH - 1 : 0] z,
    output                 carry_out
);

    wire [WIDTH : 0] carry;
    
    assign carry[0] = carry_in; 
    
    generate
    
        genvar i;
    
        for (i = 0; i <= WIDTH - 1; i = i + 1)
        begin : stage
            full_adder FA
            (
                .x		   (x    [i]    ),
                .y         (y    [i]    ),
                .z         (z    [i]    ),
                .carry_in  (carry[i]    ),
                .carry_out (carry[i + 1])
            );
        end
    endgenerate
    
    assign carry_out = carry[WIDTH];

endmodule