data/full_repos/permissive/154804262/src/DataSend.v
'utf-8' codec can't decode byte 0xb7 in position 3: invalid start byte
1: b'%Warning-WIDTH: data/full_repos/permissive/154804262/src/DataSend.v:26: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                      : ... In instance DataSend\n   fsmFrame <= 1\'d0;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154804262/src/DataSend.v:28: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                      : ... In instance DataSend\n   fsmFrame <= 1\'d0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/154804262/src/DataSend.v:35: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                      : ... In instance DataSend\n   fsmFrame <= 1\'d0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/154804262/src/DataSend.v:62: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                      : ... In instance DataSend\n   case (fsmFrame)\n   ^~~~\n%Error: data/full_repos/permissive/154804262/src/DataSend.v:128: Cannot find file containing module: \'UartTx\'\n UartTx #(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154804262/src,data/full_repos/permissive/154804262/UartTx\n             data/full_repos/permissive/154804262/src,data/full_repos/permissive/154804262/UartTx.v\n             data/full_repos/permissive/154804262/src,data/full_repos/permissive/154804262/UartTx.sv\n             UartTx\n             UartTx.v\n             UartTx.sv\n             obj_dir/UartTx\n             obj_dir/UartTx.v\n             obj_dir/UartTx.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module DataSend
#(
	parameter CLKFREQ = 100_000_000,
	parameter BAUDRATE = 115200,
	parameter BYTENUM = 7
)

(
	input clk,
	input reset,
	input enable,
	input [8*BYTENUM-1:0] dataIn,
	
	output uartTx,
	output dataTxDone
);


	wire nextByteEnable;
	parameter WIDTH = 8;
	reg [WIDTH-1:0] fsmFrame;
	always @ (posedge clk or negedge reset)
	begin
		if (!reset)
			fsmFrame <= 1'd0;
		else if (fsmFrame == (BYTENUM + 2))
			fsmFrame <= 1'd0;
		else if (enable)
			begin
				if (nextByteEnable)
					fsmFrame <= fsmFrame + 1'd1;
			end
		else
			fsmFrame <= 1'd0;
	end


	reg isDone;
	always @(posedge clk or negedge reset)
	begin
		if (!reset)
			isDone <= 1'b0;
		else if (fsmFrame == (BYTENUM + 1))
			isDone <= 1'b1;
		else
			isDone <= 1'b0;
	end
	assign dataTxDone = isDone;


	reg [7:0] dataByte;
	reg txByteEnable;
	always @ (posedge clk or negedge reset)
	begin
		if (!reset)
			begin
				dataByte <= 8'bz;
				txByteEnable <= 1'b0;
			end
		else if (enable)
			case (fsmFrame)
				8'd0:
					begin
						dataByte <= 8'hFF;
						txByteEnable <= 1'b1;
					end
				8'd1:
					begin
						dataByte <= dataIn[55:48];
						txByteEnable <= 1'b1;
					end
				8'd2:
					begin
						dataByte <= dataIn[47:40];
						txByteEnable <= 1'b1;
					end
				8'd3:
					begin
						dataByte <= dataIn[39:32];
						txByteEnable <= 1'b1;
					end
				4'd4:
					begin
						dataByte <= dataIn[31:24];
						txByteEnable <= 1'b1;
					end
				8'd5:
					begin
						dataByte <= dataIn[23:16];
						txByteEnable <= 1'b1;
					end
				8'd6:
					begin
						dataByte <= dataIn[15:8];
						txByteEnable <= 1'b1;
					end
				8'd7:
					begin
						dataByte <= dataIn[7:0];
						txByteEnable <= 1'b1;
					end
				8'd8:
					begin
						dataByte <= 8'hz;
						txByteEnable <= 1'b0;
					end
				default:
					begin
						dataByte <= 8'bz;
						txByteEnable <= 1'b0;
					end
			endcase
		else
			begin
				dataByte <= 8'bz;
				txByteEnable <= 1'b0;
			end
	end
	wire [7:0] uartInByte;
	assign uartInByte = dataByte;




	wire txEnable;
	wire uartTxDone;
	UartTx #(
		.CLKFREQ(CLKFREQ),
		.BAUDRATE(BAUDRATE)
		)
		uartTxIns (
			.clk(clk),
			.reset(reset),
			.txEnable(txEnable),
			.uartInByte(uartInByte),
			.uartTxBit(uartTx),
			.uartTxDone(uartTxDone)
			);
	assign nextByteEnable = uartTxDone;
	assign txEnable = txByteEnable;



endmodule
module DataSend
#(
	parameter CLKFREQ = 100_000_000,
	parameter BAUDRATE = 115200,
	parameter BYTENUM = 7
)

(
	input clk,
	input reset,
	input enable,
	input [8*BYTENUM-1:0] dataIn,
	
	output uartTx,
	output dataTxDone
);



	wire nextByteEnable;
	parameter WIDTH = 8;
	reg [WIDTH-1:0] fsmFrame;
	always @ (posedge clk or negedge reset)
	begin
		if (!reset)
			fsmFrame <= 1'd0;
		else if (fsmFrame == (BYTENUM + 2))
			fsmFrame <= 1'd0;
		else if (enable)
			begin
				if (nextByteEnable)
					fsmFrame <= fsmFrame + 1'd1;
			end
		else
			fsmFrame <= 1'd0;
	end


	reg isDone;
	always @(posedge clk or negedge reset)
	begin
		if (!reset)
			isDone <= 1'b0;
		else if (fsmFrame == (BYTENUM + 1))
			isDone <= 1'b1;
		else
			isDone <= 1'b0;
	end
	assign dataTxDone = isDone;


	reg [7:0] dataByte;
	reg txByteEnable;
	always @ (posedge clk or negedge reset)
	begin
		if (!reset)
			begin
				dataByte <= 8'bz;
				txByteEnable <= 1'b0;
			end
		else if (enable)
			case (fsmFrame)
				8'd0:
					begin
						dataByte <= 8'hFF;
						txByteEnable <= 1'b1;
					end
				8'd1:
					begin
						dataByte <= dataIn[55:48];
						txByteEnable <= 1'b1;
					end
				8'd2:
					begin
						dataByte <= dataIn[47:40];
						txByteEnable <= 1'b1;
					end
				8'd3:
					begin
						dataByte <= dataIn[39:32];
						txByteEnable <= 1'b1;
					end
				4'd4:
					begin
						dataByte <= dataIn[31:24];
						txByteEnable <= 1'b1;
					end
				8'd5:
					begin
						dataByte <= dataIn[23:16];
						txByteEnable <= 1'b1;
					end
				8'd6:
					begin
						dataByte <= dataIn[15:8];
						txByteEnable <= 1'b1;
					end
				8'd7:
					begin
						dataByte <= dataIn[7:0];
						txByteEnable <= 1'b1;
					end
				8'd8:
					begin
						dataByte <= 8'hz;
						txByteEnable <= 1'b0;
					end
				default:
					begin
						dataByte <= 8'bz;
						txByteEnable <= 1'b0;
					end
			endcase
		else
			begin
				dataByte <= 8'bz;
				txByteEnable <= 1'b0;
			end
	end
	wire [7:0] uartInByte;
	assign uartInByte = dataByte;




	wire txEnable;
	wire uartTxDone;
	UartTx #(
		.CLKFREQ(CLKFREQ),
		.BAUDRATE(BAUDRATE)
		)
		uartTxIns (
			.clk(clk),
			.reset(reset),
			.txEnable(txEnable),
			.uartInByte(uartInByte),
			.uartTxBit(uartTx),
			.uartTxDone(uartTxDone)
			);
	assign nextByteEnable = uartTxDone;
	assign txEnable = txByteEnable;



endmodule