data/full_repos/permissive/162928820/main_con.v
1: b'%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:116: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'num0_reg\' generates 4 bits.\n                                                                   : ... In instance main_con\n frequency <= num0_reg + num1_reg*10 + num2_reg*100 + num3_reg*1000;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:148: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'yshang\' generates 32 bits.\n                                                                   : ... In instance main_con\n  temp = (addr + 1\'b1) * (yshang >> 8) + (((addr + 1\'b1) * (yshang && 8\'b11111111)) >> 8);\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:148: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                   : ... In instance main_con\n  temp = (addr + 1\'b1) * (yshang >> 8) + (((addr + 1\'b1) * (yshang && 8\'b11111111)) >> 8);\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:148: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addr\' generates 8 bits.\n                                                                   : ... In instance main_con\n  temp = (addr + 1\'b1) * (yshang >> 8) + (((addr + 1\'b1) * (yshang && 8\'b11111111)) >> 8);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:148: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'addr\' generates 8 bits.\n                                                                   : ... In instance main_con\n  temp = (addr + 1\'b1) * (yshang >> 8) + (((addr + 1\'b1) * (yshang && 8\'b11111111)) >> 8);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con.v:157: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                   : ... In instance main_con\n  yshang_temp <= 1\'b0;\n              ^~\n%Error: Exiting due to 6 warning(s)\n'
module main_con(
	input wire clk,
	input wire aaa,
	input wire bbb,
	input wire ccc,
	input wire ddd,
	input wire [7:0] x,
	output wire [2:0] contro,
	output wire [3:0] num3_disp,
	output wire [3:0] num2_disp,
	output wire [3:0] num1_disp,
	output wire [3:0] num0_disp,
	output wire memclk,
	output wire [1:0] memmode
	);

reg [1:0] place;
reg [3:0] num3_reg;
reg [3:0] num2_reg;
reg [3:0] num1_reg;
reg [3:0] num0_reg;
reg is_bling;
reg [3:0] alex;
wire [3:0] alex_wire;

reg [24:0] bbb_delay_count;
reg [24:0] ccc_delay_count;

reg [15:0] frequency;
reg [31:0] yshang_temp;
reg [7:0] addr;
reg [31:0] temp = 0;
reg memclk_reg = 1'b0;
wire [31:0] yshang;
wire [15:0] yyushu;



initial begin
	place = 'b00;
	num3_reg = 'b0000;
	num2_reg = 'b0000;
	num1_reg = 'b0000;
	num0_reg = 'b0000;
	alex = 'b0000;
	is_bling = 1;
	addr = 0;
end

always@(negedge aaa) begin
	if(is_bling) place <= place + 1;
end

always@(posedge ddd) begin
	is_bling <= ~is_bling;
end









always@(posedge clk) begin
	if(bbb) bbb_delay_count <= bbb_delay_count + 1; else bbb_delay_count <= 0;
	if(ccc) ccc_delay_count <= ccc_delay_count + 1; else ccc_delay_count <= 0;

	if(bbb & bbb_delay_count=='b1111010000100100000) alex[0] <= 1;
	if(ccc & ccc_delay_count=='b1111010000100100000) alex[2] <= 1;
	if(bbb==0) alex[0] <= 0;
	if(ccc==0) alex[2] <= 0;

	alex[1] <= alex_wire[0];
	alex[3] <= alex_wire[2];
	case({alex_wire,contro})
		'b0001100:begin num0_reg <= num0_reg==9 ? 0 : (num0_reg + 1); end
		'b0001101:begin num1_reg <= num1_reg==9 ? 0 : (num1_reg + 1); end
		'b0001110:begin num2_reg <= num2_reg==9 ? 0 : (num2_reg + 1); end
		'b0001111:begin num3_reg <= num3_reg==9 ? 0 : (num3_reg + 1); end
		'b0100100:begin num0_reg <= num0_reg==0 ? 9 : (num0_reg - 1); end
		'b0100101:begin num1_reg <= num1_reg==0 ? 9 : (num1_reg - 1); end
		'b0100110:begin num2_reg <= num2_reg==0 ? 9 : (num2_reg - 1); end
		'b0100111:begin num3_reg <= num3_reg==0 ? 9 : (num3_reg - 1); end








	default:num0_reg <= num0_reg;
	endcase
	frequency <= num0_reg + num1_reg*10 + num2_reg*100 + num3_reg*1000;














	














	if(yshang_temp < yshang) begin
		yshang_temp <= yshang_temp + 1'b1;
		temp = (addr + 1'b1) * (yshang >> 8) + (((addr + 1'b1) * (yshang && 8'b11111111)) >> 8);
		if(yshang_temp == temp) begin
			memclk_reg <= 1'b1;
			addr <= addr + 1'b1;
			end
		else
			memclk_reg <= 1'b0;
		end
	else begin
		yshang_temp <= 1'b0;
		end
end



assign alex_wire = alex;
assign contro = {is_bling,place};

assign num3_disp = num3_reg;
assign num2_disp = num2_reg;
assign num1_disp = num1_reg;
assign num0_disp = num0_reg;
assign memclk = memclk_reg;
assign memmode = x[2:1];

div_rill div(32'h02FAF080, frequency, yshang, yyushu);




endmodule
module main_con(
	input wire clk,
	input wire aaa,
	input wire bbb,
	input wire ccc,
	input wire ddd,
	input wire [7:0] x,
	output wire [2:0] contro,
	output wire [3:0] num3_disp,
	output wire [3:0] num2_disp,
	output wire [3:0] num1_disp,
	output wire [3:0] num0_disp,
	output wire memclk,
	output wire [1:0] memmode
	);


reg [1:0] place;
reg [3:0] num3_reg;
reg [3:0] num2_reg;
reg [3:0] num1_reg;
reg [3:0] num0_reg;
reg is_bling;
reg [3:0] alex;
wire [3:0] alex_wire;

reg [24:0] bbb_delay_count;
reg [24:0] ccc_delay_count;

reg [15:0] frequency;
reg [31:0] yshang_temp;
reg [7:0] addr;
reg [31:0] temp = 0;
reg memclk_reg = 1'b0;
wire [31:0] yshang;
wire [15:0] yyushu;



initial begin
	place = 'b00;
	num3_reg = 'b0000;
	num2_reg = 'b0000;
	num1_reg = 'b0000;
	num0_reg = 'b0000;
	alex = 'b0000;
	is_bling = 1;
	addr = 0;
end

always@(negedge aaa) begin
	if(is_bling) place <= place + 1;
end

always@(posedge ddd) begin
	is_bling <= ~is_bling;
end









always@(posedge clk) begin
	if(bbb) bbb_delay_count <= bbb_delay_count + 1; else bbb_delay_count <= 0;
	if(ccc) ccc_delay_count <= ccc_delay_count + 1; else ccc_delay_count <= 0;

	if(bbb & bbb_delay_count=='b1111010000100100000) alex[0] <= 1;
	if(ccc & ccc_delay_count=='b1111010000100100000) alex[2] <= 1;
	if(bbb==0) alex[0] <= 0;
	if(ccc==0) alex[2] <= 0;

	alex[1] <= alex_wire[0];
	alex[3] <= alex_wire[2];
	case({alex_wire,contro})
		'b0001100:begin num0_reg <= num0_reg==9 ? 0 : (num0_reg + 1); end
		'b0001101:begin num1_reg <= num1_reg==9 ? 0 : (num1_reg + 1); end
		'b0001110:begin num2_reg <= num2_reg==9 ? 0 : (num2_reg + 1); end
		'b0001111:begin num3_reg <= num3_reg==9 ? 0 : (num3_reg + 1); end
		'b0100100:begin num0_reg <= num0_reg==0 ? 9 : (num0_reg - 1); end
		'b0100101:begin num1_reg <= num1_reg==0 ? 9 : (num1_reg - 1); end
		'b0100110:begin num2_reg <= num2_reg==0 ? 9 : (num2_reg - 1); end
		'b0100111:begin num3_reg <= num3_reg==0 ? 9 : (num3_reg - 1); end








	default:num0_reg <= num0_reg;
	endcase
	frequency <= num0_reg + num1_reg*10 + num2_reg*100 + num3_reg*1000;














	














	if(yshang_temp < yshang) begin
		yshang_temp <= yshang_temp + 1'b1;
		temp = (addr + 1'b1) * (yshang >> 8) + (((addr + 1'b1) * (yshang && 8'b11111111)) >> 8);
		if(yshang_temp == temp) begin
			memclk_reg <= 1'b1;
			addr <= addr + 1'b1;
			end
		else
			memclk_reg <= 1'b0;
		end
	else begin
		yshang_temp <= 1'b0;
		end
end



assign alex_wire = alex;
assign contro = {is_bling,place};

assign num3_disp = num3_reg;
assign num2_disp = num2_reg;
assign num1_disp = num1_reg;
assign num0_disp = num0_reg;
assign memclk = memclk_reg;
assign memmode = x[2:1];

div_rill div(32'h02FAF080, frequency, yshang, yyushu);




endmodule