data/full_repos/permissive/133571498/adder/top_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/133571498/adder/top_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("adder.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/133571498/adder/top_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133571498/adder/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n   #5 {A, B} = i;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb #(parameter WIDTH = 4);

	reg [WIDTH-1:0] A, B;
	wire [WIDTH-1:0] Sum;

	integer i = 0;

	adder adder (.A(A), .B(B), .Sum(Sum));

	initial begin
		$dumpfile("adder.vcd");
		$dumpvars;


		{A,B} = 0;


		for (i=1; i<'hFF; i=i+1) begin
			#5 {A, B} = i;
		end

		$finish;
	end

endmodule
module top_tb #(parameter WIDTH = 4);


	reg [WIDTH-1:0] A, B;
	wire [WIDTH-1:0] Sum;

	integer i = 0;

	adder adder (.A(A), .B(B), .Sum(Sum));

	initial begin
		$dumpfile("adder.vcd");
		$dumpvars;


		{A,B} = 0;


		for (i=1; i<'hFF; i=i+1) begin
			#5 {A, B} = i;
		end

		$finish;
	end

endmodule