data/full_repos/permissive/159555381/Lab_Exam/mux1.v
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1: b'%Error: data/full_repos/permissive/159555381/Lab_Exam/mux1.v:29: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("mux.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/159555381/Lab_Exam/mux1.v:30: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, wb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mux1.v:36: Unsupported: Ignoring delay on this delayed statement.\n   #5 sel = {1\'b0, 1\'b1};\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mux1.v:37: Unsupported: Ignoring delay on this delayed statement.\n   #5 sel = {1\'b1, 1\'b0};\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mux1.v:38: Unsupported: Ignoring delay on this delayed statement.\n   #5 sel = {1\'b1, 1\'b1};\n   ^\n%Error: data/full_repos/permissive/159555381/Lab_Exam/mux1.v:42: Unsupported or unknown PLI call: $monitor\n   $monitor ($time,,, "a = %b b = %b,  c = %b,  d= %b , sel = %b, out = %b\\n", a,b, c, d, sel, out);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/159555381/Lab_Exam/mux1.v:42: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   $monitor ($time,,, "a = %b b = %b,  c = %b,  d= %b , sel = %b, out = %b\\n", a,b, c, d, sel, out);\n                   ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module wb();
	reg [1:0] sel;
	reg [7:0] a, b, c, d;
	wire [7:0] out;
	mux mu1(out, a, b, c, d, sel);
	initial
		begin
		$dumpfile("mux.vcd");
		$dumpvars(0, wb);
		{a} = {1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1};
		{b} = {1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1};
		{c} = {1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1};
		{d} = {1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1};
			sel = {1'b0, 1'b0};
			#5 sel = {1'b0, 1'b1};
			#5 sel = {1'b1, 1'b0};
			#5 sel = {1'b1, 1'b1};
	end
	initial
		begin
			$monitor ($time,,, "a = %b b = %b,  c = %b,  d= %b , sel = %b, out = %b\n", a,b, c, d, sel, out);
		end
endmodule
module wb();

	reg [1:0] sel;
	reg [7:0] a, b, c, d;
	wire [7:0] out;
	mux mu1(out, a, b, c, d, sel);
	initial
		begin
		$dumpfile("mux.vcd");
		$dumpvars(0, wb);
		{a} = {1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1};
		{b} = {1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1};
		{c} = {1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1};
		{d} = {1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1};
			sel = {1'b0, 1'b0};
			#5 sel = {1'b0, 1'b1};
			#5 sel = {1'b1, 1'b0};
			#5 sel = {1'b1, 1'b1};
	end
	initial
		begin
			$monitor ($time,,, "a = %b b = %b,  c = %b,  d= %b , sel = %b, out = %b\n", a,b, c, d, sel, out);
		end
endmodule