data/full_repos/permissive/136197078/hardware/ip/nt_gen_timestamp_insert/hdl/nt_gen_timestamp_insert.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_gen_timestamp_insert/hdl/nt_gen_timestamp_insert.v:108: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 11 bits.\n                                                                                                                          : ... In instance nt_gen_timestamp_insert\n  assign axis_word_select = pos_i >> 3;  \n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_gen_timestamp_insert/hdl/nt_gen_timestamp_insert.v:113: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n                                                                                                                          : ... In instance nt_gen_timestamp_insert\n  assign axis_word_pos = pos_i - (pos_i & 11\'h7F8);  \n                       ^\n%Error: Exiting due to 2 warning(s)\n'
module nt_gen_timestamp_insert (

  input wire clk156,
  input wire rstn156,
  input wire rst_sw156,


  input wire [63:0]    s_axis_tdata,
  input wire [7:0]     s_axis_tkeep,
  input wire           s_axis_tvalid,
  input wire           s_axis_tlast,
  output wire          s_axis_tready,


  output reg [63:0]    m_axis_tdata,
  output reg [7:0]     m_axis_tkeep,
  output reg           m_axis_tvalid,
  output reg           m_axis_tlast,
  input wire           m_axis_tready,

  input wire [1:0]     mode_i,
  input wire [10:0]    pos_i,
  input wire           width_i,
  input wire [23:0]    timestamp_i
);

  localparam [1:0] MODE_DISABLED  = 2'b00,
                   MODE_FIXED_POS = 2'b01,
                   MODE_HEADER    = 2'b10;


  assign s_axis_tready = m_axis_tready;


  reg [15:0] ethertype;



  reg [7:0] axis_word_cntr;



  wire [7:0] axis_word_select;
  assign axis_word_select = pos_i >> 3;



  wire [2:0] axis_word_pos;
  assign axis_word_pos = pos_i - (pos_i & 11'h7F8);



  reg [63:0] axis_tdata_timestamp16;
  always @(*) begin

    if (s_axis_tkeep[axis_word_pos+1]) begin
      axis_tdata_timestamp16 = s_axis_tdata;
      case (axis_word_pos)
        3'h0: axis_tdata_timestamp16[0+:16] = timestamp_i[15:0];
        3'h1: axis_tdata_timestamp16[8+:16] = timestamp_i[15:0];
        3'h2: axis_tdata_timestamp16[16+:16] = timestamp_i[15:0];
        3'h3: axis_tdata_timestamp16[24+:16] = timestamp_i[15:0];
        3'h4: axis_tdata_timestamp16[32+:16] = timestamp_i[15:0];
        3'h5: axis_tdata_timestamp16[40+:16] = timestamp_i[15:0];
        3'h6: axis_tdata_timestamp16[48+:16] = timestamp_i[15:0];
      endcase
    end else begin

      axis_tdata_timestamp16 = s_axis_tdata;
    end
  end



  reg [63:0] axis_tdata_timestamp24;
  always @(*) begin

    if (s_axis_tkeep[axis_word_pos+2]) begin
      axis_tdata_timestamp24 = s_axis_tdata;
      case (axis_word_pos)
        3'h0: axis_tdata_timestamp24[0+:24] = timestamp_i;
        3'h1: axis_tdata_timestamp24[8+:24] = timestamp_i;
        3'h2: axis_tdata_timestamp24[16+:24] = timestamp_i;
        3'h3: axis_tdata_timestamp24[24+:24] = timestamp_i;
        3'h4: axis_tdata_timestamp24[32+:24] = timestamp_i;
        3'h5: axis_tdata_timestamp24[40+:24] = timestamp_i;
      endcase
    end else begin

      axis_tdata_timestamp24 = s_axis_tdata;
    end
  end



  always @(posedge clk156) begin
    if (~rstn156 | rst_sw156) begin
      m_axis_tdata <= 64'b0;
      m_axis_tkeep <= 8'b0;
      m_axis_tvalid <= 1'b0;
      m_axis_tlast <= 1'b0;
      ethertype <= 16'b0;
      axis_word_cntr <= 8'b0;
    end else begin
      if (m_axis_tready) begin


        if (mode_i == MODE_HEADER) begin



          if (axis_word_cntr == 1) begin

            ethertype <= s_axis_tdata[47:32];

            if (s_axis_tdata[47:32] == 16'hdd86) begin


              m_axis_tdata <= {s_axis_tdata[63:60], 4'b0, s_axis_tdata[55:0]};
            end else begin
              m_axis_tdata <= s_axis_tdata;
            end
          end else if (axis_word_cntr == 2) begin

            if (ethertype == 16'hdd86) begin
              m_axis_tdata <= {s_axis_tdata[63:16], timestamp_i[15:0]};
            end else begin
              m_axis_tdata <= s_axis_tdata;
            end
          end else if (axis_word_cntr == 3) begin

            if (ethertype == 16'h0008) begin
              m_axis_tdata <= {s_axis_tdata[63:16], timestamp_i[15:0]};
            end else begin
              m_axis_tdata <= s_axis_tdata;
            end
          end else begin
            m_axis_tdata <= s_axis_tdata;
          end
        end else if (mode_i == MODE_FIXED_POS) begin


          if (axis_word_cntr == axis_word_select) begin


            if (width_i == 0) begin

              m_axis_tdata <= axis_tdata_timestamp16;
            end else begin

              m_axis_tdata <= axis_tdata_timestamp24;
            end
          end else begin
            m_axis_tdata <= s_axis_tdata;
          end
        end else begin

          m_axis_tdata <= s_axis_tdata;
        end


        m_axis_tkeep <= s_axis_tkeep;
        m_axis_tvalid <= s_axis_tvalid;
        m_axis_tlast <= s_axis_tlast;


        if (s_axis_tvalid) begin
          axis_word_cntr <= s_axis_tlast ? 8'b0 : (axis_word_cntr + 1);
        end else begin
          axis_word_cntr <= axis_word_cntr;
        end
      end else begin

        m_axis_tdata <= m_axis_tdata;
        m_axis_tkeep <= m_axis_tkeep;
        m_axis_tvalid <= m_axis_tvalid;
        m_axis_tlast <= m_axis_tlast;

        ethertype <= ethertype;
        axis_word_cntr <= axis_word_cntr;
      end
    end
  end

endmodule
module nt_gen_timestamp_insert (

  input wire clk156,
  input wire rstn156,
  input wire rst_sw156,


  input wire [63:0]    s_axis_tdata,
  input wire [7:0]     s_axis_tkeep,
  input wire           s_axis_tvalid,
  input wire           s_axis_tlast,
  output wire          s_axis_tready,


  output reg [63:0]    m_axis_tdata,
  output reg [7:0]     m_axis_tkeep,
  output reg           m_axis_tvalid,
  output reg           m_axis_tlast,
  input wire           m_axis_tready,

  input wire [1:0]     mode_i,
  input wire [10:0]    pos_i,
  input wire           width_i,
  input wire [23:0]    timestamp_i
);


  localparam [1:0] MODE_DISABLED  = 2'b00,
                   MODE_FIXED_POS = 2'b01,
                   MODE_HEADER    = 2'b10;


  assign s_axis_tready = m_axis_tready;


  reg [15:0] ethertype;



  reg [7:0] axis_word_cntr;



  wire [7:0] axis_word_select;
  assign axis_word_select = pos_i >> 3;



  wire [2:0] axis_word_pos;
  assign axis_word_pos = pos_i - (pos_i & 11'h7F8);



  reg [63:0] axis_tdata_timestamp16;
  always @(*) begin

    if (s_axis_tkeep[axis_word_pos+1]) begin
      axis_tdata_timestamp16 = s_axis_tdata;
      case (axis_word_pos)
        3'h0: axis_tdata_timestamp16[0+:16] = timestamp_i[15:0];
        3'h1: axis_tdata_timestamp16[8+:16] = timestamp_i[15:0];
        3'h2: axis_tdata_timestamp16[16+:16] = timestamp_i[15:0];
        3'h3: axis_tdata_timestamp16[24+:16] = timestamp_i[15:0];
        3'h4: axis_tdata_timestamp16[32+:16] = timestamp_i[15:0];
        3'h5: axis_tdata_timestamp16[40+:16] = timestamp_i[15:0];
        3'h6: axis_tdata_timestamp16[48+:16] = timestamp_i[15:0];
      endcase
    end else begin

      axis_tdata_timestamp16 = s_axis_tdata;
    end
  end



  reg [63:0] axis_tdata_timestamp24;
  always @(*) begin

    if (s_axis_tkeep[axis_word_pos+2]) begin
      axis_tdata_timestamp24 = s_axis_tdata;
      case (axis_word_pos)
        3'h0: axis_tdata_timestamp24[0+:24] = timestamp_i;
        3'h1: axis_tdata_timestamp24[8+:24] = timestamp_i;
        3'h2: axis_tdata_timestamp24[16+:24] = timestamp_i;
        3'h3: axis_tdata_timestamp24[24+:24] = timestamp_i;
        3'h4: axis_tdata_timestamp24[32+:24] = timestamp_i;
        3'h5: axis_tdata_timestamp24[40+:24] = timestamp_i;
      endcase
    end else begin

      axis_tdata_timestamp24 = s_axis_tdata;
    end
  end



  always @(posedge clk156) begin
    if (~rstn156 | rst_sw156) begin
      m_axis_tdata <= 64'b0;
      m_axis_tkeep <= 8'b0;
      m_axis_tvalid <= 1'b0;
      m_axis_tlast <= 1'b0;
      ethertype <= 16'b0;
      axis_word_cntr <= 8'b0;
    end else begin
      if (m_axis_tready) begin


        if (mode_i == MODE_HEADER) begin



          if (axis_word_cntr == 1) begin

            ethertype <= s_axis_tdata[47:32];

            if (s_axis_tdata[47:32] == 16'hdd86) begin


              m_axis_tdata <= {s_axis_tdata[63:60], 4'b0, s_axis_tdata[55:0]};
            end else begin
              m_axis_tdata <= s_axis_tdata;
            end
          end else if (axis_word_cntr == 2) begin

            if (ethertype == 16'hdd86) begin
              m_axis_tdata <= {s_axis_tdata[63:16], timestamp_i[15:0]};
            end else begin
              m_axis_tdata <= s_axis_tdata;
            end
          end else if (axis_word_cntr == 3) begin

            if (ethertype == 16'h0008) begin
              m_axis_tdata <= {s_axis_tdata[63:16], timestamp_i[15:0]};
            end else begin
              m_axis_tdata <= s_axis_tdata;
            end
          end else begin
            m_axis_tdata <= s_axis_tdata;
          end
        end else if (mode_i == MODE_FIXED_POS) begin


          if (axis_word_cntr == axis_word_select) begin


            if (width_i == 0) begin

              m_axis_tdata <= axis_tdata_timestamp16;
            end else begin

              m_axis_tdata <= axis_tdata_timestamp24;
            end
          end else begin
            m_axis_tdata <= s_axis_tdata;
          end
        end else begin

          m_axis_tdata <= s_axis_tdata;
        end


        m_axis_tkeep <= s_axis_tkeep;
        m_axis_tvalid <= s_axis_tvalid;
        m_axis_tlast <= s_axis_tlast;


        if (s_axis_tvalid) begin
          axis_word_cntr <= s_axis_tlast ? 8'b0 : (axis_word_cntr + 1);
        end else begin
          axis_word_cntr <= axis_word_cntr;
        end
      end else begin

        m_axis_tdata <= m_axis_tdata;
        m_axis_tkeep <= m_axis_tkeep;
        m_axis_tvalid <= m_axis_tvalid;
        m_axis_tlast <= m_axis_tlast;

        ethertype <= ethertype;
        axis_word_cntr <= axis_word_cntr;
      end
    end
  end

endmodule