data/full_repos/permissive/169522605/hw3_1/nor2.v
data/verilator_xmls/c3f39fad-4b47-4a17-bcc4-abce9f3fc14c.xml
module nor2 (in1,in2,out);
    input in1,in2;
    output out;
    assign out = ~(in1 | in2);
endmodule
module nor2 (in1,in2,out);

    input in1,in2;
    output out;
    assign out = ~(in1 | in2);
endmodule