data/full_repos/permissive/205673649/BIP/Source/tx.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/205673649/BIP/Source/tx.v:121: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'n_reg\' generates 3 bits.\n                                                                        : ... In instance tx\n                        if(n_reg==(NB_DATA-1))\n                                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205673649/BIP/Source/tx.v:135: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'s_reg\' generates 4 bits.\n                                                                        : ... In instance tx\n                    if(s_reg==(SB_TICK-1))\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/205673649/BIP/Source/tx.v:148: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'s_reg\' generates 4 bits.\n                                                                        : ... In instance tx\n   assign o_done_tx = ((s_reg==(SB_TICK-1)) && (state_reg==stop))? 1\'b0: 1\'b1;\n                             ^~\n%Error: Exiting due to 3 warning(s)\n'
module tx
  #(
    parameter NB_DATA = 8,
    parameter SB_TICK = 16
   )
   (
    input i_clk,  
    input i_rst,
    input i_tx_start,
    input i_tick,
    input [NB_DATA-1:0] i_data,
    output o_done_tx,
    output o_tx
   );
   

   localparam [2-1:0] idle= 2'b00;
   localparam [2-1:0] start= 2'b01;
   localparam [2-1:0] data=2'b10;
   localparam [2-1:0] stop=2'b11;
   

   reg [2-1:0] state_reg;
   reg [2-1:0] state_next;
   reg [4-1:0] s_reg;
   reg [4-1:0] s_next;
   reg [3-1:0] n_reg;
   reg [3-1:0] n_next;
   reg [NB_DATA-1:0] b_reg;
   reg [NB_DATA-1:0] b_next;
   reg tx_reg;
   reg tx_next;

   

   always @(posedge i_clk)
   begin
    if(!i_rst)
    begin
        state_reg <= idle;
        s_reg <= 4'b0;
        n_reg <= 3'b0;
        b_reg <= 8'b0;
        tx_reg <= 1'b1;
    end
    else
    begin
        state_reg <= state_next;
        s_reg <= s_next;
        n_reg <= n_next;
        b_reg <= b_next;
        tx_reg <= tx_next;
    end
   end
   

   always @(*)
   begin
        state_next = state_reg;
        s_next = s_reg;
        n_next = n_reg;
        b_next = b_reg;
        tx_next = tx_reg;
        
        case(state_reg)
            idle:
            begin
                tx_next = 1'b1;
                if(i_tx_start)
                begin
                    state_next = start;
                    s_next = 0;
                    b_next = i_data;
                end
            end
            start:
            begin
                tx_next = 1'b0;
                if(i_tick)
                begin
                    if(s_reg==15)
                    begin
                        state_next = data;
                        s_next = 4'b0;
                        n_next = 3'b0;    
                    end
                    else
                        s_next = s_reg + 1'b1;    
                end
            end
            data:
            begin
                tx_next = b_reg[0];
                if(i_tick)
                begin
                    if(s_reg==15)
                    begin
                        s_next = 4'b0;
                        b_next = b_reg >> 1;
                        if(n_reg==(NB_DATA-1))
                            state_next = stop;
                        else
                            n_next = n_reg + 1'b1;    
                    end
                    else
                        s_next = s_reg + 1'b1;    
                end
            end
            stop:
            begin
                tx_next = 1'b1;
                if(i_tick)
                begin
                    if(s_reg==(SB_TICK-1))
                    begin
                       state_next = idle;
                    end
                    else
                        s_next = s_reg + 1'b1;    
                end
            end
        endcase
   end
   

   assign o_tx = tx_reg;
   assign o_done_tx = ((s_reg==(SB_TICK-1)) && (state_reg==stop))? 1'b0: 1'b1;

endmodule
module tx
  #(
    parameter NB_DATA = 8,
    parameter SB_TICK = 16
   )
   (
    input i_clk,  
    input i_rst,
    input i_tx_start,
    input i_tick,
    input [NB_DATA-1:0] i_data,
    output o_done_tx,
    output o_tx
   );

   

   localparam [2-1:0] idle= 2'b00;
   localparam [2-1:0] start= 2'b01;
   localparam [2-1:0] data=2'b10;
   localparam [2-1:0] stop=2'b11;
   

   reg [2-1:0] state_reg;
   reg [2-1:0] state_next;
   reg [4-1:0] s_reg;
   reg [4-1:0] s_next;
   reg [3-1:0] n_reg;
   reg [3-1:0] n_next;
   reg [NB_DATA-1:0] b_reg;
   reg [NB_DATA-1:0] b_next;
   reg tx_reg;
   reg tx_next;

   

   always @(posedge i_clk)
   begin
    if(!i_rst)
    begin
        state_reg <= idle;
        s_reg <= 4'b0;
        n_reg <= 3'b0;
        b_reg <= 8'b0;
        tx_reg <= 1'b1;
    end
    else
    begin
        state_reg <= state_next;
        s_reg <= s_next;
        n_reg <= n_next;
        b_reg <= b_next;
        tx_reg <= tx_next;
    end
   end
   

   always @(*)
   begin
        state_next = state_reg;
        s_next = s_reg;
        n_next = n_reg;
        b_next = b_reg;
        tx_next = tx_reg;
        
        case(state_reg)
            idle:
            begin
                tx_next = 1'b1;
                if(i_tx_start)
                begin
                    state_next = start;
                    s_next = 0;
                    b_next = i_data;
                end
            end
            start:
            begin
                tx_next = 1'b0;
                if(i_tick)
                begin
                    if(s_reg==15)
                    begin
                        state_next = data;
                        s_next = 4'b0;
                        n_next = 3'b0;    
                    end
                    else
                        s_next = s_reg + 1'b1;    
                end
            end
            data:
            begin
                tx_next = b_reg[0];
                if(i_tick)
                begin
                    if(s_reg==15)
                    begin
                        s_next = 4'b0;
                        b_next = b_reg >> 1;
                        if(n_reg==(NB_DATA-1))
                            state_next = stop;
                        else
                            n_next = n_reg + 1'b1;    
                    end
                    else
                        s_next = s_reg + 1'b1;    
                end
            end
            stop:
            begin
                tx_next = 1'b1;
                if(i_tick)
                begin
                    if(s_reg==(SB_TICK-1))
                    begin
                       state_next = idle;
                    end
                    else
                        s_next = s_reg + 1'b1;    
                end
            end
        endcase
   end
   

   assign o_tx = tx_reg;
   assign o_done_tx = ((s_reg==(SB_TICK-1)) && (state_reg==stop))? 1'b0: 1'b1;

endmodule