data/full_repos/permissive/164569208/rtl/dma_if_mux_wr.v
1: b"%Error: data/full_repos/permissive/164569208/rtl/dma_if_mux_wr.v:138: Cannot find file containing module: 'dma_if_desc_mux'\ndma_if_desc_mux #(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164569208/rtl,data/full_repos/permissive/164569208/dma_if_desc_mux\n             data/full_repos/permissive/164569208/rtl,data/full_repos/permissive/164569208/dma_if_desc_mux.v\n             data/full_repos/permissive/164569208/rtl,data/full_repos/permissive/164569208/dma_if_desc_mux.sv\n             dma_if_desc_mux\n             dma_if_desc_mux.v\n             dma_if_desc_mux.sv\n             obj_dir/dma_if_desc_mux\n             obj_dir/dma_if_desc_mux.v\n             obj_dir/dma_if_desc_mux.sv\n%Error: data/full_repos/permissive/164569208/rtl/dma_if_mux_wr.v:198: Cannot find file containing module: 'dma_ram_demux_rd'\ndma_ram_demux_rd #(\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module dma_if_mux_wr #
(

    parameter PORTS = 2,

    parameter SEG_COUNT = 2,

    parameter SEG_DATA_WIDTH = 64,

    parameter SEG_ADDR_WIDTH = 8,

    parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,

    parameter S_RAM_SEL_WIDTH = 2,


    parameter M_RAM_SEL_WIDTH = S_RAM_SEL_WIDTH+$clog2(PORTS),

    parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),

    parameter DMA_ADDR_WIDTH = 64,

    parameter IMM_ENABLE = 0,

    parameter IMM_WIDTH = 32,

    parameter LEN_WIDTH = 16,

    parameter S_TAG_WIDTH = 8,


    parameter M_TAG_WIDTH = S_TAG_WIDTH+$clog2(PORTS),

    parameter ARB_TYPE_ROUND_ROBIN = 0,

    parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
    input  wire                                       clk,
    input  wire                                       rst,


    output wire [DMA_ADDR_WIDTH-1:0]                  m_axis_write_desc_dma_addr,
    output wire [M_RAM_SEL_WIDTH-1:0]                 m_axis_write_desc_ram_sel,
    output wire [RAM_ADDR_WIDTH-1:0]                  m_axis_write_desc_ram_addr,
    output wire [IMM_WIDTH-1:0]                       m_axis_write_desc_imm,
    output wire                                       m_axis_write_desc_imm_en,
    output wire [LEN_WIDTH-1:0]                       m_axis_write_desc_len,
    output wire [M_TAG_WIDTH-1:0]                     m_axis_write_desc_tag,
    output wire                                       m_axis_write_desc_valid,
    input  wire                                       m_axis_write_desc_ready,


    input  wire [M_TAG_WIDTH-1:0]                     s_axis_write_desc_status_tag,
    input  wire [3:0]                                 s_axis_write_desc_status_error,
    input  wire                                       s_axis_write_desc_status_valid,


    input  wire [PORTS*DMA_ADDR_WIDTH-1:0]            s_axis_write_desc_dma_addr,
    input  wire [PORTS*S_RAM_SEL_WIDTH-1:0]           s_axis_write_desc_ram_sel,
    input  wire [PORTS*RAM_ADDR_WIDTH-1:0]            s_axis_write_desc_ram_addr,
    input  wire [PORTS*IMM_WIDTH-1:0]                 s_axis_write_desc_imm,
    input  wire [PORTS-1:0]                           s_axis_write_desc_imm_en,
    input  wire [PORTS*LEN_WIDTH-1:0]                 s_axis_write_desc_len,
    input  wire [PORTS*S_TAG_WIDTH-1:0]               s_axis_write_desc_tag,
    input  wire [PORTS-1:0]                           s_axis_write_desc_valid,
    output wire [PORTS-1:0]                           s_axis_write_desc_ready,


    output wire [PORTS*S_TAG_WIDTH-1:0]               m_axis_write_desc_status_tag,
    output wire [PORTS*4-1:0]                         m_axis_write_desc_status_error,
    output wire [PORTS-1:0]                           m_axis_write_desc_status_valid,


    input  wire [SEG_COUNT*M_RAM_SEL_WIDTH-1:0]       if_ram_rd_cmd_sel,
    input  wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0]        if_ram_rd_cmd_addr,
    input  wire [SEG_COUNT-1:0]                       if_ram_rd_cmd_valid,
    output wire [SEG_COUNT-1:0]                       if_ram_rd_cmd_ready,
    output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0]        if_ram_rd_resp_data,
    output wire [SEG_COUNT-1:0]                       if_ram_rd_resp_valid,
    input  wire [SEG_COUNT-1:0]                       if_ram_rd_resp_ready,


    output wire [PORTS*SEG_COUNT*S_RAM_SEL_WIDTH-1:0] ram_rd_cmd_sel,
    output wire [PORTS*SEG_COUNT*SEG_ADDR_WIDTH-1:0]  ram_rd_cmd_addr,
    output wire [PORTS*SEG_COUNT-1:0]                 ram_rd_cmd_valid,
    input  wire [PORTS*SEG_COUNT-1:0]                 ram_rd_cmd_ready,
    input  wire [PORTS*SEG_COUNT*SEG_DATA_WIDTH-1:0]  ram_rd_resp_data,
    input  wire [PORTS*SEG_COUNT-1:0]                 ram_rd_resp_valid,
    output wire [PORTS*SEG_COUNT-1:0]                 ram_rd_resp_ready
);

dma_if_desc_mux #(
    .PORTS(PORTS),
    .EXTEND_RAM_SEL(1),
    .S_RAM_SEL_WIDTH(S_RAM_SEL_WIDTH),
    .M_RAM_SEL_WIDTH(M_RAM_SEL_WIDTH),
    .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
    .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
    .IMM_ENABLE(IMM_ENABLE),
    .IMM_WIDTH(IMM_WIDTH),
    .LEN_WIDTH(LEN_WIDTH),
    .S_TAG_WIDTH(S_TAG_WIDTH),
    .M_TAG_WIDTH(M_TAG_WIDTH),
    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
dma_if_desc_mux_inst (
    .clk(clk),
    .rst(rst),


    .m_axis_desc_dma_addr(m_axis_write_desc_dma_addr),
    .m_axis_desc_ram_sel(m_axis_write_desc_ram_sel),
    .m_axis_desc_ram_addr(m_axis_write_desc_ram_addr),
    .m_axis_desc_imm(m_axis_write_desc_imm),
    .m_axis_desc_imm_en(m_axis_write_desc_imm_en),
    .m_axis_desc_len(m_axis_write_desc_len),
    .m_axis_desc_tag(m_axis_write_desc_tag),
    .m_axis_desc_valid(m_axis_write_desc_valid),
    .m_axis_desc_ready(m_axis_write_desc_ready),


    .s_axis_desc_status_tag(s_axis_write_desc_status_tag),
    .s_axis_desc_status_error(s_axis_write_desc_status_error),
    .s_axis_desc_status_valid(s_axis_write_desc_status_valid),


    .s_axis_desc_dma_addr(s_axis_write_desc_dma_addr),
    .s_axis_desc_ram_sel(s_axis_write_desc_ram_sel),
    .s_axis_desc_ram_addr(s_axis_write_desc_ram_addr),
    .s_axis_desc_imm(s_axis_write_desc_imm),
    .s_axis_desc_imm_en(s_axis_write_desc_imm_en),
    .s_axis_desc_len(s_axis_write_desc_len),
    .s_axis_desc_tag(s_axis_write_desc_tag),
    .s_axis_desc_valid(s_axis_write_desc_valid),
    .s_axis_desc_ready(s_axis_write_desc_ready),


    .m_axis_desc_status_tag(m_axis_write_desc_status_tag),
    .m_axis_desc_status_error(m_axis_write_desc_status_error),
    .m_axis_desc_status_valid(m_axis_write_desc_status_valid)
);

dma_ram_demux_rd #(
    .PORTS(PORTS),
    .SEG_COUNT(SEG_COUNT),
    .SEG_DATA_WIDTH(SEG_DATA_WIDTH),
    .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
    .S_RAM_SEL_WIDTH(S_RAM_SEL_WIDTH),
    .M_RAM_SEL_WIDTH(M_RAM_SEL_WIDTH)
)
dma_ram_demux_inst (
    .clk(clk),
    .rst(rst),


    .ctrl_rd_cmd_sel(if_ram_rd_cmd_sel),
    .ctrl_rd_cmd_addr(if_ram_rd_cmd_addr),
    .ctrl_rd_cmd_valid(if_ram_rd_cmd_valid),
    .ctrl_rd_cmd_ready(if_ram_rd_cmd_ready),
    .ctrl_rd_resp_data(if_ram_rd_resp_data),
    .ctrl_rd_resp_valid(if_ram_rd_resp_valid),
    .ctrl_rd_resp_ready(if_ram_rd_resp_ready),


    .ram_rd_cmd_sel(ram_rd_cmd_sel),
    .ram_rd_cmd_addr(ram_rd_cmd_addr),
    .ram_rd_cmd_valid(ram_rd_cmd_valid),
    .ram_rd_cmd_ready(ram_rd_cmd_ready),
    .ram_rd_resp_data(ram_rd_resp_data),
    .ram_rd_resp_valid(ram_rd_resp_valid),
    .ram_rd_resp_ready(ram_rd_resp_ready)
);

endmodule
module dma_if_mux_wr #
(

    parameter PORTS = 2,

    parameter SEG_COUNT = 2,

    parameter SEG_DATA_WIDTH = 64,

    parameter SEG_ADDR_WIDTH = 8,

    parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,

    parameter S_RAM_SEL_WIDTH = 2,


    parameter M_RAM_SEL_WIDTH = S_RAM_SEL_WIDTH+$clog2(PORTS),

    parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),

    parameter DMA_ADDR_WIDTH = 64,

    parameter IMM_ENABLE = 0,

    parameter IMM_WIDTH = 32,

    parameter LEN_WIDTH = 16,

    parameter S_TAG_WIDTH = 8,


    parameter M_TAG_WIDTH = S_TAG_WIDTH+$clog2(PORTS),

    parameter ARB_TYPE_ROUND_ROBIN = 0,

    parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
    input  wire                                       clk,
    input  wire                                       rst,


    output wire [DMA_ADDR_WIDTH-1:0]                  m_axis_write_desc_dma_addr,
    output wire [M_RAM_SEL_WIDTH-1:0]                 m_axis_write_desc_ram_sel,
    output wire [RAM_ADDR_WIDTH-1:0]                  m_axis_write_desc_ram_addr,
    output wire [IMM_WIDTH-1:0]                       m_axis_write_desc_imm,
    output wire                                       m_axis_write_desc_imm_en,
    output wire [LEN_WIDTH-1:0]                       m_axis_write_desc_len,
    output wire [M_TAG_WIDTH-1:0]                     m_axis_write_desc_tag,
    output wire                                       m_axis_write_desc_valid,
    input  wire                                       m_axis_write_desc_ready,


    input  wire [M_TAG_WIDTH-1:0]                     s_axis_write_desc_status_tag,
    input  wire [3:0]                                 s_axis_write_desc_status_error,
    input  wire                                       s_axis_write_desc_status_valid,


    input  wire [PORTS*DMA_ADDR_WIDTH-1:0]            s_axis_write_desc_dma_addr,
    input  wire [PORTS*S_RAM_SEL_WIDTH-1:0]           s_axis_write_desc_ram_sel,
    input  wire [PORTS*RAM_ADDR_WIDTH-1:0]            s_axis_write_desc_ram_addr,
    input  wire [PORTS*IMM_WIDTH-1:0]                 s_axis_write_desc_imm,
    input  wire [PORTS-1:0]                           s_axis_write_desc_imm_en,
    input  wire [PORTS*LEN_WIDTH-1:0]                 s_axis_write_desc_len,
    input  wire [PORTS*S_TAG_WIDTH-1:0]               s_axis_write_desc_tag,
    input  wire [PORTS-1:0]                           s_axis_write_desc_valid,
    output wire [PORTS-1:0]                           s_axis_write_desc_ready,


    output wire [PORTS*S_TAG_WIDTH-1:0]               m_axis_write_desc_status_tag,
    output wire [PORTS*4-1:0]                         m_axis_write_desc_status_error,
    output wire [PORTS-1:0]                           m_axis_write_desc_status_valid,


    input  wire [SEG_COUNT*M_RAM_SEL_WIDTH-1:0]       if_ram_rd_cmd_sel,
    input  wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0]        if_ram_rd_cmd_addr,
    input  wire [SEG_COUNT-1:0]                       if_ram_rd_cmd_valid,
    output wire [SEG_COUNT-1:0]                       if_ram_rd_cmd_ready,
    output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0]        if_ram_rd_resp_data,
    output wire [SEG_COUNT-1:0]                       if_ram_rd_resp_valid,
    input  wire [SEG_COUNT-1:0]                       if_ram_rd_resp_ready,


    output wire [PORTS*SEG_COUNT*S_RAM_SEL_WIDTH-1:0] ram_rd_cmd_sel,
    output wire [PORTS*SEG_COUNT*SEG_ADDR_WIDTH-1:0]  ram_rd_cmd_addr,
    output wire [PORTS*SEG_COUNT-1:0]                 ram_rd_cmd_valid,
    input  wire [PORTS*SEG_COUNT-1:0]                 ram_rd_cmd_ready,
    input  wire [PORTS*SEG_COUNT*SEG_DATA_WIDTH-1:0]  ram_rd_resp_data,
    input  wire [PORTS*SEG_COUNT-1:0]                 ram_rd_resp_valid,
    output wire [PORTS*SEG_COUNT-1:0]                 ram_rd_resp_ready
);


dma_if_desc_mux #(
    .PORTS(PORTS),
    .EXTEND_RAM_SEL(1),
    .S_RAM_SEL_WIDTH(S_RAM_SEL_WIDTH),
    .M_RAM_SEL_WIDTH(M_RAM_SEL_WIDTH),
    .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
    .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
    .IMM_ENABLE(IMM_ENABLE),
    .IMM_WIDTH(IMM_WIDTH),
    .LEN_WIDTH(LEN_WIDTH),
    .S_TAG_WIDTH(S_TAG_WIDTH),
    .M_TAG_WIDTH(M_TAG_WIDTH),
    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
dma_if_desc_mux_inst (
    .clk(clk),
    .rst(rst),


    .m_axis_desc_dma_addr(m_axis_write_desc_dma_addr),
    .m_axis_desc_ram_sel(m_axis_write_desc_ram_sel),
    .m_axis_desc_ram_addr(m_axis_write_desc_ram_addr),
    .m_axis_desc_imm(m_axis_write_desc_imm),
    .m_axis_desc_imm_en(m_axis_write_desc_imm_en),
    .m_axis_desc_len(m_axis_write_desc_len),
    .m_axis_desc_tag(m_axis_write_desc_tag),
    .m_axis_desc_valid(m_axis_write_desc_valid),
    .m_axis_desc_ready(m_axis_write_desc_ready),


    .s_axis_desc_status_tag(s_axis_write_desc_status_tag),
    .s_axis_desc_status_error(s_axis_write_desc_status_error),
    .s_axis_desc_status_valid(s_axis_write_desc_status_valid),


    .s_axis_desc_dma_addr(s_axis_write_desc_dma_addr),
    .s_axis_desc_ram_sel(s_axis_write_desc_ram_sel),
    .s_axis_desc_ram_addr(s_axis_write_desc_ram_addr),
    .s_axis_desc_imm(s_axis_write_desc_imm),
    .s_axis_desc_imm_en(s_axis_write_desc_imm_en),
    .s_axis_desc_len(s_axis_write_desc_len),
    .s_axis_desc_tag(s_axis_write_desc_tag),
    .s_axis_desc_valid(s_axis_write_desc_valid),
    .s_axis_desc_ready(s_axis_write_desc_ready),


    .m_axis_desc_status_tag(m_axis_write_desc_status_tag),
    .m_axis_desc_status_error(m_axis_write_desc_status_error),
    .m_axis_desc_status_valid(m_axis_write_desc_status_valid)
);

dma_ram_demux_rd #(
    .PORTS(PORTS),
    .SEG_COUNT(SEG_COUNT),
    .SEG_DATA_WIDTH(SEG_DATA_WIDTH),
    .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
    .S_RAM_SEL_WIDTH(S_RAM_SEL_WIDTH),
    .M_RAM_SEL_WIDTH(M_RAM_SEL_WIDTH)
)
dma_ram_demux_inst (
    .clk(clk),
    .rst(rst),


    .ctrl_rd_cmd_sel(if_ram_rd_cmd_sel),
    .ctrl_rd_cmd_addr(if_ram_rd_cmd_addr),
    .ctrl_rd_cmd_valid(if_ram_rd_cmd_valid),
    .ctrl_rd_cmd_ready(if_ram_rd_cmd_ready),
    .ctrl_rd_resp_data(if_ram_rd_resp_data),
    .ctrl_rd_resp_valid(if_ram_rd_resp_valid),
    .ctrl_rd_resp_ready(if_ram_rd_resp_ready),


    .ram_rd_cmd_sel(ram_rd_cmd_sel),
    .ram_rd_cmd_addr(ram_rd_cmd_addr),
    .ram_rd_cmd_valid(ram_rd_cmd_valid),
    .ram_rd_cmd_ready(ram_rd_cmd_ready),
    .ram_rd_resp_data(ram_rd_resp_data),
    .ram_rd_resp_valid(ram_rd_resp_valid),
    .ram_rd_resp_ready(ram_rd_resp_ready)
);

endmodule