data/full_repos/permissive/146246005/RAM and ROM/RAM_TB.v
 line:44: before: "$"
1: b'%Error: Cannot find file containing module: and\n        ... Looked in:\n             data/full_repos/permissive/146246005/RAM/and\n             data/full_repos/permissive/146246005/RAM/and.v\n             data/full_repos/permissive/146246005/RAM/and.sv\n             and\n             and.v\n             and.sv\n             obj_dir/and\n             obj_dir/and.v\n             obj_dir/and.sv\n%Error: Cannot find file containing module: ROM,data/full_repos/permissive/146246005\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/RAM\n%Error: Cannot find file containing module: ROM/RAM_TB.v\n%Error: Exiting due to 4 error(s)\n'
module RAM_TB();
  reg OE, CS, WS;
  reg [4:0] ADDRbus;
  wire [7:0] DATAbus;
  reg [7:0] DATAreg;
  integer i,j,k;
  

  assign DATAbus = (!OE && !CS) ? DATAreg:8'bz; 
  
  RAM RAM1(DATAbus, ADDRbus, OE, CS, WS);

  initial begin
    $vcdpluson;


    $monitor(" ADDRbus =%d  CS =%b  OE =%b  WS =%b  DATAbus =%d  DATAreg =%d", ADDRbus, CS, OE, WS, DATAbus, DATAreg);
  end

initial begin
    $monitoroff;
    #10 CS=0; OE=0;
    $display("\n\t\t TEST WRITE");
    $monitoron;
    for(i=0;i<32;i=i+1) begin
      #10 $monitoroff; WS=0; DATAreg=i; ADDRbus=i;
      #10 $monitoron; WS=1;
    end


  #20 $display("\n\t\t INDIVIDUAL READ OF ADDR 12");
  #10 CS=0; OE=1; WS=0; ADDRbus=12;


  #10 $monitoroff;
  #10 CS=0; OE=1;
  $display("\n\t\t BLOCK READ");
   for(j=0;j<32;j=j+1) begin
     $strobe("\t\t RAM[%2d] = %d",j, RAM.memory[j]);
     #10 ADDRbus=j;
   end
  

  #10 CS=1; $monitoron;
  $display("\n\t\t HIGH IMPEDANCE TEST");
  

  $monitorb("ADDRbus =%d  CS =%b  OE =%b  WS =%b  DATAbus =%b  DATAreg =%b", ADDRbus, CS, OE, WS, DATAbus, DATAreg);
  #10 k=1; CS=0; OE=0;
  $display("\n\t\t WRITING WALKING ONES");
  for(i=0;i<8;i=i+1) begin
  #10 $monitoroff; WS=0;  ADDRbus=i; DATAreg=k;
  #10 $monitoron; WS=1; k=k*2;
    if(k==256) k=1;
    else;
  end
  
  #10 $monitoroff; OE=1; WS=0; CS=0;
  #10 $display("\n\t\t READING WALKING ONES");
  #10 $monitoron;
  for(i=0; i<8; i=i+1) #10 ADDRbus=i;

  
#100 $finish;
end
endmodule
module RAM_TB();

  reg OE, CS, WS;
  reg [4:0] ADDRbus;
  wire [7:0] DATAbus;
  reg [7:0] DATAreg;
  integer i,j,k;
  

  assign DATAbus = (!OE && !CS) ? DATAreg:8'bz; 
  
  RAM RAM1(DATAbus, ADDRbus, OE, CS, WS);

  initial begin
    $vcdpluson;


    $monitor(" ADDRbus =%d  CS =%b  OE =%b  WS =%b  DATAbus =%d  DATAreg =%d", ADDRbus, CS, OE, WS, DATAbus, DATAreg);
  end

initial begin
    $monitoroff;
    #10 CS=0; OE=0;
    $display("\n\t\t TEST WRITE");
    $monitoron;
    for(i=0;i<32;i=i+1) begin
      #10 $monitoroff; WS=0; DATAreg=i; ADDRbus=i;
      #10 $monitoron; WS=1;
    end


  #20 $display("\n\t\t INDIVIDUAL READ OF ADDR 12");
  #10 CS=0; OE=1; WS=0; ADDRbus=12;


  #10 $monitoroff;
  #10 CS=0; OE=1;
  $display("\n\t\t BLOCK READ");
   for(j=0;j<32;j=j+1) begin
     $strobe("\t\t RAM[%2d] = %d",j, RAM.memory[j]);
     #10 ADDRbus=j;
   end
  

  #10 CS=1; $monitoron;
  $display("\n\t\t HIGH IMPEDANCE TEST");
  

  $monitorb("ADDRbus =%d  CS =%b  OE =%b  WS =%b  DATAbus =%b  DATAreg =%b", ADDRbus, CS, OE, WS, DATAbus, DATAreg);
  #10 k=1; CS=0; OE=0;
  $display("\n\t\t WRITING WALKING ONES");
  for(i=0;i<8;i=i+1) begin
  #10 $monitoroff; WS=0;  ADDRbus=i; DATAreg=k;
  #10 $monitoron; WS=1; k=k*2;
    if(k==256) k=1;
    else;
  end
  
  #10 $monitoroff; OE=1; WS=0; CS=0;
  #10 $display("\n\t\t READING WALKING ONES");
  #10 $monitoron;
  for(i=0; i<8; i=i+1) #10 ADDRbus=i;

  
#100 $finish;
end
endmodule