data/full_repos/permissive/161029703/src/periph/seg_disp.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/161029703/src/periph/seg_disp.v:28: Operator ADD expects 3 bits on the RHS, but RHS\'s REDAND generates 1 bits.\n                                                                             : ... In instance seg_disp\n        scan <= scan + (&divider);\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161029703/src/periph/seg_disp.v:30: Operator NOT expects 8 bits on the LHS, but LHS\'s ARRAYSEL generates 7 bits.\n                                                                             : ... In instance seg_disp\n        seg <= ~seg_all[scan];\n               ^\n%Error: Exiting due to 2 warning(s)\n'
module seg_disp (
    input wire clk,
    input wire [31:0] din,  
    output reg [7:0] seg,
    output reg [7:0] com
);

wire[6:0] seg_all[0:7];
reg[2:0] scan;
reg[12:0] divider;

genvar k;
generate
    for(k=0;k<8;k=k+1) begin : proc_decoder
        SEG7_LUT decoder(seg_all[k], din[(k+1)*4-1:k*4]);
    end
endgenerate

always @(posedge clk) begin : proc_divider
    begin
        divider <= divider + 1'b1;
    end
end

integer i;
always @(posedge clk) begin : proc_scan
    begin
        scan <= scan + (&divider);
        com <= ~(1<<scan);
        seg <= ~seg_all[scan];





    end
end

endmodule
module seg_disp (
    input wire clk,
    input wire [31:0] din,  
    output reg [7:0] seg,
    output reg [7:0] com
);


wire[6:0] seg_all[0:7];
reg[2:0] scan;
reg[12:0] divider;

genvar k;
generate
    for(k=0;k<8;k=k+1) begin : proc_decoder
        SEG7_LUT decoder(seg_all[k], din[(k+1)*4-1:k*4]);
    end
endgenerate

always @(posedge clk) begin : proc_divider
    begin
        divider <= divider + 1'b1;
    end
end

integer i;
always @(posedge clk) begin : proc_scan
    begin
        scan <= scan + (&divider);
        com <= ~(1<<scan);
        seg <= ~seg_all[scan];





    end
end

endmodule