data/full_repos/permissive/187199324/stannel/Enable.v
1: b'%Error: data/full_repos/permissive/187199324/stannel/Enable.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:4: Define or directive not defined: \'`ADDRESS_BITS\'\nmodule Enable #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:4: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nmodule Enable #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                                   ^\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:4: Define or directive not defined: \'`DATA_BITS\'\nmodule Enable #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:4: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule Enable #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                                                                     ^\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:7: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                reset,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:8: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                 finished,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:10: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg  [addrBits-1:0] address,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:11: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                 readWriteMode,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:13: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire [dataBits-1:0] dataOut,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg  [dataBits-1:0] dataIn,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:17: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire [addrBits-1:0] channel,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [addrBits-1:0] rxPid,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                 rxCanReceive\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:42: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:67: Define or directive not defined: \'`RAM_READ\'\n    readWriteMode = `RAM_READ;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:101: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable.v:108: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: Exiting due to 18 error(s)\n'
module Enable #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    output reg                 finished,

    output reg  [addrBits-1:0] address,
    output reg                 readWriteMode,

    input  wire [dataBits-1:0] dataOut,

    output reg  [dataBits-1:0] dataIn,

    input  wire [addrBits-1:0] channel,
    input  wire [addrBits-1:0] rxPid,

    output reg                 rxCanReceive
  );


  localparam STATE_INIT            = 3'd0;
  localparam STATE_READ_TX_PROC    = 3'd1;
  localparam STATE_HANDLE_TX_PROC  = 3'd2;
  localparam STATE_WRITE_RX_PROC_0 = 3'd3;
  localparam STATE_WRITE_RX_PROC_1 = 3'd4;

  reg [2:0]          rState;
  reg [addrBits-1:0] rTx;



  reg [2:0]          wNextState;
  reg                wFinished;
  reg [addrBits-1:0] wTx;
  reg                wUpdateTx;
  reg                wRxCanReceive;


  always @(posedge clk)
  begin
    if (!reset)
      begin
        rState            <= STATE_INIT;
        finished          <= 0;
        rxCanReceive <= 0;

      end
    else
      begin
        rState            <= wNextState;
        finished          <= wFinished;
        rxCanReceive <= wRxCanReceive;

        if (wUpdateTx)
            rTx <= wTx;
      end
  end


  always @(*)
  begin
    address       = {addrBits{1'bx}};
    dataIn        = {dataBits{1'bx}};
    readWriteMode = `RAM_READ;
    wNextState    = rState;
    wFinished     = 0;
    wUpdateTx     = 0;
    wTx           = {addrBits{1'bx}};
    wRxCanReceive = rxCanReceive;
    case (rState)
      STATE_INIT:
        begin
          address   = channel;
          wNextState = STATE_READ_TX_PROC;
        end
      STATE_READ_TX_PROC:
        begin
          wUpdateTx  = 1;
          wTx        = dataOut[7:0];
          address   = channel;
          wNextState = STATE_HANDLE_TX_PROC;
        end
      STATE_HANDLE_TX_PROC:
        begin
          if (rTx == 0)
            wNextState = STATE_WRITE_RX_PROC_0;
          else
            begin
              wFinished     = 1;
              wNextState    = STATE_INIT;
              wRxCanReceive = 1;
            end
        end
      STATE_WRITE_RX_PROC_0:
        begin
          address       = channel;
          dataIn        = {8'b0, rxPid};
          readWriteMode = `RAM_WRITE;
          wNextState     = STATE_WRITE_RX_PROC_1;
        end
      STATE_WRITE_RX_PROC_1:
        begin
          address       = channel;
          dataIn        = {8'b0,rxPid};
          readWriteMode = `RAM_WRITE;
          wNextState     = STATE_INIT;
          wFinished      = 1;
        end
      default:
        begin
        end
    endcase
  end

endmodule
module Enable #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    output reg                 finished,

    output reg  [addrBits-1:0] address,
    output reg                 readWriteMode,

    input  wire [dataBits-1:0] dataOut,

    output reg  [dataBits-1:0] dataIn,

    input  wire [addrBits-1:0] channel,
    input  wire [addrBits-1:0] rxPid,

    output reg                 rxCanReceive
  );



  localparam STATE_INIT            = 3'd0;
  localparam STATE_READ_TX_PROC    = 3'd1;
  localparam STATE_HANDLE_TX_PROC  = 3'd2;
  localparam STATE_WRITE_RX_PROC_0 = 3'd3;
  localparam STATE_WRITE_RX_PROC_1 = 3'd4;

  reg [2:0]          rState;
  reg [addrBits-1:0] rTx;



  reg [2:0]          wNextState;
  reg                wFinished;
  reg [addrBits-1:0] wTx;
  reg                wUpdateTx;
  reg                wRxCanReceive;


  always @(posedge clk)
  begin
    if (!reset)
      begin
        rState            <= STATE_INIT;
        finished          <= 0;
        rxCanReceive <= 0;

      end
    else
      begin
        rState            <= wNextState;
        finished          <= wFinished;
        rxCanReceive <= wRxCanReceive;

        if (wUpdateTx)
            rTx <= wTx;
      end
  end


  always @(*)
  begin
    address       = {addrBits{1'bx}};
    dataIn        = {dataBits{1'bx}};
    readWriteMode = `RAM_READ;
    wNextState    = rState;
    wFinished     = 0;
    wUpdateTx     = 0;
    wTx           = {addrBits{1'bx}};
    wRxCanReceive = rxCanReceive;
    case (rState)
      STATE_INIT:
        begin
          address   = channel;
          wNextState = STATE_READ_TX_PROC;
        end
      STATE_READ_TX_PROC:
        begin
          wUpdateTx  = 1;
          wTx        = dataOut[7:0];
          address   = channel;
          wNextState = STATE_HANDLE_TX_PROC;
        end
      STATE_HANDLE_TX_PROC:
        begin
          if (rTx == 0)
            wNextState = STATE_WRITE_RX_PROC_0;
          else
            begin
              wFinished     = 1;
              wNextState    = STATE_INIT;
              wRxCanReceive = 1;
            end
        end
      STATE_WRITE_RX_PROC_0:
        begin
          address       = channel;
          dataIn        = {8'b0, rxPid};
          readWriteMode = `RAM_WRITE;
          wNextState     = STATE_WRITE_RX_PROC_1;
        end
      STATE_WRITE_RX_PROC_1:
        begin
          address       = channel;
          dataIn        = {8'b0,rxPid};
          readWriteMode = `RAM_WRITE;
          wNextState     = STATE_INIT;
          wFinished      = 1;
        end
      default:
        begin
        end
    endcase
  end

endmodule