data/full_repos/permissive/121803953/Lab1/lab1.v
data/verilator_xmls/012f2d9a-376f-4eca-8f5d-548a280b9e02.xml
module part2(a, b, c, d, U);
	input a, b, c, d;
	output U;
	wire [1:0] x;
	and and1(x[0], a, b);
	and and2(x[1], c, d);
	assign U = ~&x;
endmodule
module part2(a, b, c, d, U);

	input a, b, c, d;
	output U;
	wire [1:0] x;
	and and1(x[0], a, b);
	and and2(x[1], c, d);
	assign U = ~&x;
endmodule