data/full_repos/permissive/188434311/verilog/fifo/async_fifo/async_fifo_grey_code.vh
 line:9: before: "localparam"
1: b"%Error: data/full_repos/permissive/188434311/verilog/fifo/async_fifo/async_fifo_grey_code.vh:98: syntax error, unexpected ':'\n    { GREY_6 , GREY_0 } :\n                        ^\n%Error: data/full_repos/permissive/188434311/verilog/fifo/async_fifo/async_fifo_grey_code.vh:121: syntax error, unexpected ':'\n    { GREY_1  , GREY_1 } : \n                         ^\n%Error: Exiting due to 2 error(s)\n"
function grey_to_bin;
    input [ 3 : 0 ] ingrey;
    case( ingrey )
      GREY_0  :  grey_to_bin = BIN_0 ; 
      GREY_1  :  grey_to_bin = BIN_1 ; 
      GREY_2  :  grey_to_bin = BIN_2 ; 
      GREY_3  :  grey_to_bin = BIN_3 ; 
      GREY_4  :  grey_to_bin = BIN_4 ; 
      GREY_5  :  grey_to_bin = BIN_5 ; 
      GREY_6  :  grey_to_bin = BIN_6 ; 
      GREY_7  :  grey_to_bin = BIN_7 ; 
      GREY_8  :  grey_to_bin = BIN_8 ; 
      GREY_9  :  grey_to_bin = BIN_9 ; 
      GREY_10  :  grey_to_bin = BIN_10 ; 
      GREY_11  :  grey_to_bin = BIN_11 ; 
      default :  grey_to_bin = BIN_0 ;

    endcase
endfunction
function grey_to_bin;

    input [ 3 : 0 ] ingrey;
    case( ingrey )
      GREY_0  :  grey_to_bin = BIN_0 ; 
      GREY_1  :  grey_to_bin = BIN_1 ; 
      GREY_2  :  grey_to_bin = BIN_2 ; 
      GREY_3  :  grey_to_bin = BIN_3 ; 
      GREY_4  :  grey_to_bin = BIN_4 ; 
      GREY_5  :  grey_to_bin = BIN_5 ; 
      GREY_6  :  grey_to_bin = BIN_6 ; 
      GREY_7  :  grey_to_bin = BIN_7 ; 
      GREY_8  :  grey_to_bin = BIN_8 ; 
      GREY_9  :  grey_to_bin = BIN_9 ; 
      GREY_10  :  grey_to_bin = BIN_10 ; 
      GREY_11  :  grey_to_bin = BIN_11 ; 
      default :  grey_to_bin = BIN_0 ;

    endcase
endfunction