data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_always_on_edge_wrapped_tb.v
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_always_on_edge_wrapped_tb.v:3: Cannot find include file: ovl_always_on_edge_wrapped.v\n`include "ovl_always_on_edge_wrapped.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_always_on_edge_wrapped.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_always_on_edge_wrapped.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_always_on_edge_wrapped.v.sv\n             ovl_always_on_edge_wrapped.v\n             ovl_always_on_edge_wrapped.v.v\n             ovl_always_on_edge_wrapped.v.sv\n             obj_dir/ovl_always_on_edge_wrapped.v\n             obj_dir/ovl_always_on_edge_wrapped.v.v\n             obj_dir/ovl_always_on_edge_wrapped.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_always_on_edge_wrapped_tb.v:4: Cannot find include file: ovl_ported/ovl_always_on_edge.v\n`include "ovl_ported/ovl_always_on_edge.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module main();


   reg clk;
   reg rst;
   reg enable;
   reg sampling_event;
   reg test_expr;
   reg prevConfigInvalid;


   wire out;

   ovl_always_on_edge_wrapped ovl_aoew_t(.clk(clk),
                                         .rst(rst),
                                         .enable(enable),
                                         .sampling_event(sampling_event),
                                         .test_expr(test_expr),
                                         .prevConfigInvalid(prevConfigInvalid),
                                         .out(out));
   
   initial begin
      clk = 0;
      rst = 1;
      enable = 0;
      sampling_event = 0;
      test_expr = 0;
      prevConfigInvalid = 0;
   end
   
   always begin
      clk = #5 !clk;
   end
   

endmodule
module main();



   reg clk;
   reg rst;
   reg enable;
   reg sampling_event;
   reg test_expr;
   reg prevConfigInvalid;


   wire out;

   ovl_always_on_edge_wrapped ovl_aoew_t(.clk(clk),
                                         .rst(rst),
                                         .enable(enable),
                                         .sampling_event(sampling_event),
                                         .test_expr(test_expr),
                                         .prevConfigInvalid(prevConfigInvalid),
                                         .out(out));
   
   initial begin
      clk = 0;
      rst = 1;
      enable = 0;
      sampling_event = 0;
      test_expr = 0;
      prevConfigInvalid = 0;
   end
   
   always begin
      clk = #5 !clk;
   end
   

endmodule