data/full_repos/permissive/190426879/single_cpu/source/io_input_reg.v
data/verilator_xmls/1a4f3cb9-ffdf-4bac-ad0b-a1ebc0d603cc.xml
module io_input_reg(addr,io_clk,io_read_data,in_port0,in_port1);
	
	input		[31:0]	addr;
	input		[4:0]	in_port0,in_port1;
	input					io_clk;
	
	output	[31:0]	io_read_data;

	reg		[31:0]	in_reg0,in_reg1;
	
	io_input_mux		io_input_mux2x32(in_reg0,in_reg1,addr[7:2],io_read_data);
	
	always @(posedge io_clk)
		begin
			in_reg0 <= {27'b0,in_port0};
			in_reg1 <= {27'b0,in_port1};
		end

endmodule
module io_input_reg(addr,io_clk,io_read_data,in_port0,in_port1);

	
	input		[31:0]	addr;
	input		[4:0]	in_port0,in_port1;
	input					io_clk;
	
	output	[31:0]	io_read_data;

	reg		[31:0]	in_reg0,in_reg1;
	
	io_input_mux		io_input_mux2x32(in_reg0,in_reg1,addr[7:2],io_read_data);
	
	always @(posedge io_clk)
		begin
			in_reg0 <= {27'b0,in_port0};
			in_reg1 <= {27'b0,in_port1};
		end

endmodule