data/full_repos/permissive/160024456/exp/rotate_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160024456/exp/rotate_test.v:10: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = !clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160024456/exp/rotate_test.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/exp/rotate_test.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #48000010\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/exp/rotate_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #48000010\n    ^\n%Error: data/full_repos/permissive/160024456/exp/rotate_test.v:12: Cannot find file containing module: \'rotate\'\n  rotate dut (clk, LED1, LED2, LED3, LED4, LED5);\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160024456/exp,data/full_repos/permissive/160024456/rotate\n             data/full_repos/permissive/160024456/exp,data/full_repos/permissive/160024456/rotate.v\n             data/full_repos/permissive/160024456/exp,data/full_repos/permissive/160024456/rotate.sv\n             rotate\n             rotate.v\n             rotate.sv\n             obj_dir/rotate\n             obj_dir/rotate.v\n             obj_dir/rotate.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rotate_test;

  wire LED1;
  wire LED2;
  wire LED3;
  wire LED4;
  wire LED5;

  reg clk = 0;
  always #5 clk = !clk;

  rotate dut (clk, LED1, LED2, LED3, LED4, LED5);

  initial begin
    $display("start");

    #10
    if ((LED1 != 0) || (LED2 != 0) || (LED3 != 0) || (LED4 != 0) || (LED5 != 1))
      $display("failed1 led1=", LED1, ", led2=", LED2, ", led3=", LED3, ", led4=", LED4, ", led5=", LED5);

    #48000010
    if ((LED1 != 1) || (LED2 != 0) || (LED3 != 0) || (LED4 != 0) || (LED5 != 0))
      $display("failed2 led1=", LED1, ", led2=", LED2, ", led3=", LED3, ", led4=", LED4, ", led5=", LED5);

    #48000010
    if ((LED1 != 0) || (LED2 != 1) || (LED3 != 0) || (LED4 != 0) || (LED5 != 0))
      $display("failed3 led1=", LED1, ", led2=", LED2, ", led3=", LED3, ", led4=", LED4, ", led5=", LED5);

    $display("done");
    $finish;
  end

endmodule
module rotate_test;


  wire LED1;
  wire LED2;
  wire LED3;
  wire LED4;
  wire LED5;

  reg clk = 0;
  always #5 clk = !clk;

  rotate dut (clk, LED1, LED2, LED3, LED4, LED5);

  initial begin
    $display("start");

    #10
    if ((LED1 != 0) || (LED2 != 0) || (LED3 != 0) || (LED4 != 0) || (LED5 != 1))
      $display("failed1 led1=", LED1, ", led2=", LED2, ", led3=", LED3, ", led4=", LED4, ", led5=", LED5);

    #48000010
    if ((LED1 != 1) || (LED2 != 0) || (LED3 != 0) || (LED4 != 0) || (LED5 != 0))
      $display("failed2 led1=", LED1, ", led2=", LED2, ", led3=", LED3, ", led4=", LED4, ", led5=", LED5);

    #48000010
    if ((LED1 != 0) || (LED2 != 1) || (LED3 != 0) || (LED4 != 0) || (LED5 != 0))
      $display("failed3 led1=", LED1, ", led2=", LED2, ", led3=", LED3, ", led4=", LED4, ", led5=", LED5);

    $display("done");
    $finish;
  end

endmodule