data/full_repos/permissive/155064391/components/uart.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:144: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'rx_clk\' generates 18 bits.\n                                                                          : ... In instance uart\n        if(rx_clk) begin\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:148: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'tx_clk\' generates 14 bits.\n                                                                          : ... In instance uart\n        if(tx_clk) begin\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:161: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 27 bits.\n                                                                          : ... In instance uart\n                    rx_clk = one_baud_cnt / 2;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:172: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 27 bits.\n                                                                          : ... In instance uart\n                        rx_clk = (one_baud_cnt / 2) + (one_baud_cnt * 3) / 8; \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:167: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'rx_clk\' generates 18 bits.\n                                                                          : ... In instance uart\n                if (!rx_clk) begin\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:191: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 27 bits.\n                                                                          : ... In instance uart\n                    rx_clk = one_baud_cnt / 8;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:193: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'rx_sample_countdown\' generates 4 bits.\n                                                                          : ... In instance uart\n                    recv_state = rx_sample_countdown ? RX_SAMPLE_BITS : RX_READ_BITS;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:187: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'rx_clk\' generates 18 bits.\n                                                                          : ... In instance uart\n                if (!rx_clk) begin\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:207: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 27 bits.\n                                                                          : ... In instance uart\n                    rx_clk = (one_baud_cnt * 3) / 8;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:216: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 27 bits.\n                                                                          : ... In instance uart\n                        rx_clk = one_baud_cnt / 2;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:212: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'rx_bits_remaining\' generates 4 bits.\n                                                                          : ... In instance uart\n                    if(rx_bits_remaining)begin\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:198: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'rx_clk\' generates 18 bits.\n                                                                          : ... In instance uart\n                if (!rx_clk) begin\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:222: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'rx_clk\' generates 18 bits.\n                                                                          : ... In instance uart\n                if (!rx_clk) begin\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:238: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 27 bits.\n                                                                          : ... In instance uart\n                rx_clk = 8 * sys_clk_freq / (baud_rate);\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:247: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'rx_clk\' generates 18 bits.\n                                                                          : ... In instance uart\n                recv_state = rx_clk ? RX_DELAY_RESTART : RX_IDLE;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:273: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s VARREF \'one_baud_cnt\' generates 32 or 27 bits.\n                                                                          : ... In instance uart\n                    tx_clk = one_baud_cnt;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:286: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s VARREF \'one_baud_cnt\' generates 32 or 27 bits.\n                                                                          : ... In instance uart\n                        tx_clk = one_baud_cnt;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:291: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 or 27 bits.\n                                                                          : ... In instance uart\n                        tx_clk = 16 * one_baud_cnt; \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:282: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'tx_bits_remaining\' generates 4 bits.\n                                                                          : ... In instance uart\n                    if (tx_bits_remaining) begin\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:281: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'tx_clk\' generates 14 bits.\n                                                                          : ... In instance uart\n                if (!tx_clk) begin\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/155064391/components/uart.v:301: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'tx_clk\' generates 14 bits.\n                                                                          : ... In instance uart\n                tx_state = tx_clk ? TX_DELAY_RESTART : TX_RECOVER; \n                                  ^\n%Error: Exiting due to 21 warning(s)\n'
function integer log2(input integer M);
        integer i;
    begin
        log2 = 1;
        for (i = 0; 2**i <= M; i = i + 1)
            log2 = i + 1;
    end endfunction
function integer log2(input integer M);

        integer i;
    begin
        log2 = 1;
        for (i = 0; 2**i <= M; i = i + 1)
            log2 = i + 1;
    end endfunction