data/full_repos/permissive/113780415/src/top_test.v
 line:1736: before: "&&"
1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(posedge clk && enable == 1'b1)\n                                   ^~\n%Error: Cannot continue\n"
module d_ff(reg_input, reg_output, clk, reset);


    input reg_input;

    output reg reg_output;

    input clk;

    input reset;



    always @(posedge clk)

    begin

        if (reset == 1'b1)

            reg_output <= 1'b0;

        else

            if (reg_input >= reg_output)

                reg_output <= reg_input;

    end

endmodule
module d_ff(reg_input, reg_output, clk, reset);



    input reg_input;

    output reg reg_output;

    input clk;

    input reset;



    always @(posedge clk)

    begin

        if (reset == 1'b1)

            reg_output <= 1'b0;

        else

            if (reg_input >= reg_output)

                reg_output <= reg_input;

    end

endmodule