data/full_repos/permissive/170626364/hw3_2/fullAdder_tb.v
 line:10: before: "for"
1: b'%Warning-STMTDLY: data/full_repos/permissive/170626364/hw3_2/fullAdder_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/170626364/hw3_2/fullAdder_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #5 for (inputs = 0; inputs < 8; inputs = inputs + 1) begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/170626364/hw3_2/fullAdder_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    initial #60 $finish; \n            ^\n%Error: data/full_repos/permissive/170626364/hw3_2/fullAdder_tb.v:6: Cannot find file containing module: \'fullAdder_1b\'\n    fullAdder_1b iDUT(a, b, c_in, s, c_out); \n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170626364/hw3_2,data/full_repos/permissive/170626364/fullAdder_1b\n             data/full_repos/permissive/170626364/hw3_2,data/full_repos/permissive/170626364/fullAdder_1b.v\n             data/full_repos/permissive/170626364/hw3_2,data/full_repos/permissive/170626364/fullAdder_1b.sv\n             fullAdder_1b\n             fullAdder_1b.v\n             fullAdder_1b.sv\n             obj_dir/fullAdder_1b\n             obj_dir/fullAdder_1b.v\n             obj_dir/fullAdder_1b.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fullAdder_tb();
    reg[3:0] inputs; 
    wire a, b, c_in; 
    wire s, c_out;
    
    fullAdder_1b iDUT(a, b, c_in, s, c_out); 
    assign {a, b, c_in} = inputs[2:0]; 
    
    initial begin
        #5 for (inputs = 0; inputs < 8; inputs = inputs + 1) begin
            #5;
        end
    end 

    initial #60 $finish; 
endmodule
module fullAdder_tb();

    reg[3:0] inputs; 
    wire a, b, c_in; 
    wire s, c_out;
    
    fullAdder_1b iDUT(a, b, c_in, s, c_out); 
    assign {a, b, c_in} = inputs[2:0]; 
    
    initial begin
        #5 for (inputs = 0; inputs < 8; inputs = inputs + 1) begin
            #5;
        end
    end 

    initial #60 $finish; 
endmodule