data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_spi_tb.v
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_spi_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n  #(SCLK_PERIOD/2)\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_spi_tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #(SCLK_PERIOD/2)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_spi_tb.v:231: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD * 10)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_spi_tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD * 10)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_spi_tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n #(SCLK_PERIOD*10)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_spi_tb.v:268: Unsupported: Ignoring delay on this delayed statement.\n #(SCLK_PERIOD*2)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_spi_tb.v:281: Unsupported: Ignoring delay on this delayed statement.\n  forever #(CLK_PERIOD/2) clk_i = ~clk_i;\n          ^\n%Error: data/full_repos/permissive/19591557/designs/spinnaker_fpgas/spinnaker_fpgas_spi_tb.v:62: Cannot find file containing module: \'spinnaker_fpgas_spi\'\nspinnaker_fpgas_spi #( .DIR_BITS  (DIR_BITS)\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/designs/spinnaker_fpgas,data/full_repos/permissive/19591557/spinnaker_fpgas_spi\n             data/full_repos/permissive/19591557/designs/spinnaker_fpgas,data/full_repos/permissive/19591557/spinnaker_fpgas_spi.v\n             data/full_repos/permissive/19591557/designs/spinnaker_fpgas,data/full_repos/permissive/19591557/spinnaker_fpgas_spi.sv\n             spinnaker_fpgas_spi\n             spinnaker_fpgas_spi.v\n             spinnaker_fpgas_spi.sv\n             obj_dir/spinnaker_fpgas_spi\n             obj_dir/spinnaker_fpgas_spi.v\n             obj_dir/spinnaker_fpgas_spi.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spinnaker_fpgas_spi_tb;

localparam CLK_PERIOD  =  10;
localparam SCLK_PERIOD = 100;

localparam DIR_BITS  =  8;
localparam ADDR_BITS = 32;
localparam VAL_BITS  = ADDR_BITS;






reg clk_i;
reg reset_i;


reg  sclk_i;
reg  mosi_i;
wire miso_i;
reg  nss_i;


wire [ADDR_BITS-1:0] address_i;
wire                 read_i;
wire                 write_i;
wire [VAL_BITS-1:0]  write_value_i;
wire [VAL_BITS-1:0]  read_value_i;









reg [ADDR_BITS-3:0] next_address_i;


reg [ADDR_BITS-3:0] expected_address_i;


reg ignored_bit;





spinnaker_fpgas_spi #( .DIR_BITS  (DIR_BITS)
                     , .ADDR_BITS (ADDR_BITS)
                     , .VAL_BITS  (VAL_BITS)
                     )
spinnaker_fpgas_spi_i( .CLK_IN   (clk_i)
                     , .RESET_IN (reset_i)

                     , .SCLK_IN  (sclk_i)
                     , .MOSI_IN  (mosi_i)
                     , .MISO_OUT (miso_i)
                     , .NSS_IN   (nss_i)

                     , .ADDRESS_OUT     (address_i)
                     , .READ_OUT        (read_i)
                     , .WRITE_OUT       (write_i)
                     , .WRITE_VALUE_OUT (write_value_i)
                     , .READ_VALUE_IN   (read_value_i)
                     );










always @ (posedge clk_i, posedge reset_i)
	if (!reset_i && (write_i || read_i) && (nss_i))
		$display("%0d: ERROR: Peek/poke attempted while not selected!", $time);





always @ (posedge clk_i, posedge reset_i)
	if (reset_i)
		expected_address_i <= 0;
	else
		if (nss_i)
			expected_address_i <= next_address_i;
		else if ((write_i || read_i))
			begin
				if (address_i != {expected_address_i, 1'b0, expected_address_i[0]})
					$display( "%0d: ERROR: Address 0x%0X accessed, expected 0x%0X."
					        , $time
					        , address_i
					        , {expected_address_i, 1'b0, expected_address_i[0]}
					        );
				expected_address_i <= expected_address_i + 1;
			end



always @ (posedge clk_i, posedge reset_i)
	if (!reset_i && ((write_i && !address_i[0]) || (read_i && address_i[0])))
		$display( "%0d: ERROR: At address 0x%0X a %s is expected, got a %s."
		        , $time
		        , address_i
		        , address_i[0] ? "write" : "read"
		        , address_i[0] ? "read" : "write"
		        );



always @ (posedge clk_i, posedge reset_i)
	if (!reset_i && write_i && (write_value_i != ~address_i))
		$display( "%0d: ERROR: At address 0x%0X, wrote 0x%0X, expected 0x%0X."
		        , $time
		        , address_i
		        , write_value_i
		        , ~address_i
		        );




assign read_value_i = read_i ? ~address_i : {VAL_BITS{1'bX}};








task spi_bit;
	input ibit;
	output obit;
	begin

		mosi_i <= ibit;
		

		#(SCLK_PERIOD/2)
		sclk_i <= 1'b1;
		obit <= miso_i;
		

		#(SCLK_PERIOD/2)
		sclk_i <= 1'b0;
	end
endtask



task spi_addr;
	input reg [ADDR_BITS-1:0] addr;
	integer i;
	begin
		for (i = ADDR_BITS-1; i >= 0; i = i - 1)
			spi_bit(addr[i], ignored_bit);
	end
endtask



task spi_val;
	input  reg [VAL_BITS-1:0] ival;
	output reg [VAL_BITS-1:0] oval;
	integer i;
	begin
		for (i = VAL_BITS-1; i >= 0; i = i - 1)
			spi_bit(ival[i], oval[i]);
	end
endtask



task spi_command;
	reg [VAL_BITS-1:0] val;
	reg [ADDR_BITS-3:0] addr;
	begin
		addr = next_address_i;
		next_address_i = next_address_i + 1;
		
		spi_addr({addr, 1'b0, addr[0]});
		spi_val(~{addr, 1'b0, addr[0]}, val);
		

		if (~nss_i && ~addr[0] && val != ~{addr, 1'b0, addr[0]})
			$display( "%0d: ERROR: Read from 0x%0X returned 0x%0X expected 0x%0X."
			        , $time
			        , {addr, 1'b0, addr[0]}
			        , val
			        , ~{addr, 1'b0, addr[0]}
			        );
	end
endtask


initial
	begin

	nss_i  <= 1'b1;
	sclk_i <= 1'b0;
	next_address_i <= 0;
	

	reset_i <= 1'b1;
	#(CLK_PERIOD * 10)
	reset_i <= 1'b0;
	#(CLK_PERIOD * 10)
	

	spi_command();
	spi_command();
	spi_command();
	spi_command();
	

	nss_i <= 1'b0;
	spi_command();
	spi_command();
	spi_command();
	spi_command();
	


	spi_bit(1'b1, ignored_bit);
	spi_bit(1'b1, ignored_bit);
	spi_bit(1'b1, ignored_bit);
	nss_i <= 1'b1;
	#(SCLK_PERIOD*10)
	nss_i <= 1'b0;
	spi_command();
	spi_command();
	spi_command();
	spi_command();
	

	nss_i <= 1'b1;
	spi_command();
	spi_command();
	spi_command();
	spi_command();
	
	#(SCLK_PERIOD*2)
	$display("%0d: End of stimulus, stopping simulation.", $time);
	$finish();
	end






initial
	begin
		clk_i = 1'b0;
		forever #(CLK_PERIOD/2) clk_i = ~clk_i;
	end



endmodule
module spinnaker_fpgas_spi_tb;


localparam CLK_PERIOD  =  10;
localparam SCLK_PERIOD = 100;

localparam DIR_BITS  =  8;
localparam ADDR_BITS = 32;
localparam VAL_BITS  = ADDR_BITS;






reg clk_i;
reg reset_i;


reg  sclk_i;
reg  mosi_i;
wire miso_i;
reg  nss_i;


wire [ADDR_BITS-1:0] address_i;
wire                 read_i;
wire                 write_i;
wire [VAL_BITS-1:0]  write_value_i;
wire [VAL_BITS-1:0]  read_value_i;









reg [ADDR_BITS-3:0] next_address_i;


reg [ADDR_BITS-3:0] expected_address_i;


reg ignored_bit;





spinnaker_fpgas_spi #( .DIR_BITS  (DIR_BITS)
                     , .ADDR_BITS (ADDR_BITS)
                     , .VAL_BITS  (VAL_BITS)
                     )
spinnaker_fpgas_spi_i( .CLK_IN   (clk_i)
                     , .RESET_IN (reset_i)

                     , .SCLK_IN  (sclk_i)
                     , .MOSI_IN  (mosi_i)
                     , .MISO_OUT (miso_i)
                     , .NSS_IN   (nss_i)

                     , .ADDRESS_OUT     (address_i)
                     , .READ_OUT        (read_i)
                     , .WRITE_OUT       (write_i)
                     , .WRITE_VALUE_OUT (write_value_i)
                     , .READ_VALUE_IN   (read_value_i)
                     );










always @ (posedge clk_i, posedge reset_i)
	if (!reset_i && (write_i || read_i) && (nss_i))
		$display("%0d: ERROR: Peek/poke attempted while not selected!", $time);





always @ (posedge clk_i, posedge reset_i)
	if (reset_i)
		expected_address_i <= 0;
	else
		if (nss_i)
			expected_address_i <= next_address_i;
		else if ((write_i || read_i))
			begin
				if (address_i != {expected_address_i, 1'b0, expected_address_i[0]})
					$display( "%0d: ERROR: Address 0x%0X accessed, expected 0x%0X."
					        , $time
					        , address_i
					        , {expected_address_i, 1'b0, expected_address_i[0]}
					        );
				expected_address_i <= expected_address_i + 1;
			end



always @ (posedge clk_i, posedge reset_i)
	if (!reset_i && ((write_i && !address_i[0]) || (read_i && address_i[0])))
		$display( "%0d: ERROR: At address 0x%0X a %s is expected, got a %s."
		        , $time
		        , address_i
		        , address_i[0] ? "write" : "read"
		        , address_i[0] ? "read" : "write"
		        );



always @ (posedge clk_i, posedge reset_i)
	if (!reset_i && write_i && (write_value_i != ~address_i))
		$display( "%0d: ERROR: At address 0x%0X, wrote 0x%0X, expected 0x%0X."
		        , $time
		        , address_i
		        , write_value_i
		        , ~address_i
		        );




assign read_value_i = read_i ? ~address_i : {VAL_BITS{1'bX}};








task spi_bit;
	input ibit;
	output obit;
	begin

		mosi_i <= ibit;
		

		#(SCLK_PERIOD/2)
		sclk_i <= 1'b1;
		obit <= miso_i;
		

		#(SCLK_PERIOD/2)
		sclk_i <= 1'b0;
	end
endtask



task spi_addr;
	input reg [ADDR_BITS-1:0] addr;
	integer i;
	begin
		for (i = ADDR_BITS-1; i >= 0; i = i - 1)
			spi_bit(addr[i], ignored_bit);
	end
endtask



task spi_val;
	input  reg [VAL_BITS-1:0] ival;
	output reg [VAL_BITS-1:0] oval;
	integer i;
	begin
		for (i = VAL_BITS-1; i >= 0; i = i - 1)
			spi_bit(ival[i], oval[i]);
	end
endtask



task spi_command;
	reg [VAL_BITS-1:0] val;
	reg [ADDR_BITS-3:0] addr;
	begin
		addr = next_address_i;
		next_address_i = next_address_i + 1;
		
		spi_addr({addr, 1'b0, addr[0]});
		spi_val(~{addr, 1'b0, addr[0]}, val);
		

		if (~nss_i && ~addr[0] && val != ~{addr, 1'b0, addr[0]})
			$display( "%0d: ERROR: Read from 0x%0X returned 0x%0X expected 0x%0X."
			        , $time
			        , {addr, 1'b0, addr[0]}
			        , val
			        , ~{addr, 1'b0, addr[0]}
			        );
	end
endtask


initial
	begin

	nss_i  <= 1'b1;
	sclk_i <= 1'b0;
	next_address_i <= 0;
	

	reset_i <= 1'b1;
	#(CLK_PERIOD * 10)
	reset_i <= 1'b0;
	#(CLK_PERIOD * 10)
	

	spi_command();
	spi_command();
	spi_command();
	spi_command();
	

	nss_i <= 1'b0;
	spi_command();
	spi_command();
	spi_command();
	spi_command();
	


	spi_bit(1'b1, ignored_bit);
	spi_bit(1'b1, ignored_bit);
	spi_bit(1'b1, ignored_bit);
	nss_i <= 1'b1;
	#(SCLK_PERIOD*10)
	nss_i <= 1'b0;
	spi_command();
	spi_command();
	spi_command();
	spi_command();
	

	nss_i <= 1'b1;
	spi_command();
	spi_command();
	spi_command();
	spi_command();
	
	#(SCLK_PERIOD*2)
	$display("%0d: End of stimulus, stopping simulation.", $time);
	$finish();
	end






initial
	begin
		clk_i = 1'b0;
		forever #(CLK_PERIOD/2) clk_i = ~clk_i;
	end



endmodule