data/full_repos/permissive/201025648/Verilog/3.51.v
data/verilator_xmls/29fd398e-d2ee-4ebc-a986-95fe61750198.xml
module test;
reg[7:0] memory [0:7];
integer i;
initial
begin
$readmemb("init.dat",memory);
for(i=0;i<8;i=i+1)
$display("Memort[%d]=%b",i,memory[i]);
end
endmodule
module test;

reg[7:0] memory [0:7];
integer i;
initial
begin
$readmemb("init.dat",memory);
for(i=0;i<8;i=i+1)
$display("Memort[%d]=%b",i,memory[i]);
end
endmodule