data/full_repos/permissive/109594910/example-1k.v
 line:13: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/109594910/example-1k.v:33: Operator OR expects 33 bits on the LHS, but LHS\'s VARREF \'rng\' generates 32 bits.\n                                                                    : ... In instance top\n        rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});        \n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/109594910/example-1k.v:33: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s XOR generates 33 bits.\n                                                                    : ... In instance top\n        rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});        \n            ^~\n%Error: Exiting due to 2 warning(s)\n'
module top (
    input clk,
    output LED1,
    output LED2,
    output LED3,
    output LED4,
    output LED5
);

    localparam BITS = 5;
    localparam LOG2DELAY = 22;
    
    function [BITS-1:0] bin2gray(input [BITS-1:0] in);
        integer i;
        reg [BITS-1:0] temp;
        begin
            temp = in;
            for (i=0; i<BITS; i=i+1)
                bin2gray[i] = ^temp[i +: 2];
        end
    endfunction
    
    
    reg [BITS+LOG2DELAY-1:0] counter = 0;
    
    always@(posedge clk)
        counter <= counter + 1;
        
        
    reg [31:0] rng = 32'h00010000; 
    
    always@(posedge counter[LOG2DELAY-2])
        rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});        
        
    assign {LED1, LED2, LED3, LED4, LED5} = rng[11:7];
    
endmodule
module top (
    input clk,
    output LED1,
    output LED2,
    output LED3,
    output LED4,
    output LED5
);


    localparam BITS = 5;
    localparam LOG2DELAY = 22;
    
    function [BITS-1:0] bin2gray(input [BITS-1:0] in);
        integer i;
        reg [BITS-1:0] temp;
        begin
            temp = in;
            for (i=0; i<BITS; i=i+1)
                bin2gray[i] = ^temp[i +: 2];
        end
    endfunction
    
    
    reg [BITS+LOG2DELAY-1:0] counter = 0;
    
    always@(posedge clk)
        counter <= counter + 1;
        
        
    reg [31:0] rng = 32'h00010000; 
    
    always@(posedge counter[LOG2DELAY-2])
        rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});        
        
    assign {LED1, LED2, LED3, LED4, LED5} = rng[11:7];
    
endmodule