data/full_repos/permissive/198653989/JTAG2AXIL/JTAG2AXIL.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/198653989/JTAG2AXIL/JTAG2AXIL.v:477: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'read_index\' generates 1 bits.\n                                                                              : ... In instance JTAG2AXIL\n             expected_rdata <= C_M_START_DATA_VALUE + read_index;\n                                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/198653989/JTAG2AXIL/JTAG2AXIL.v:604: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'write_index\' generates 1 bits.\n                                                                              : ... In instance JTAG2AXIL\n     else if ((write_index == C_M_TRANSACTIONS_NUM) && M_AXI_AWREADY)                \n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/198653989/JTAG2AXIL/JTAG2AXIL.v:640: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'read_index\' generates 1 bits.\n                                                                              : ... In instance JTAG2AXIL\n     else if ((read_index == C_M_TRANSACTIONS_NUM) && (M_AXI_ARREADY) )              \n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/198653989/JTAG2AXIL/JTAG2AXIL.v:703: Operator ASSIGNDLY expects 65 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                              : ... In instance JTAG2AXIL\n   r_shift_regs <= {(C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH){1\'h0}};\n                ^~\n%Error: Exiting due to 4 warning(s)\n'
module JTAG2AXIL #
	(






		parameter  C_M_START_DATA_VALUE	= 32'h00000000,


		parameter  C_M_TARGET_SLAVE_BASE_ADDR	= 32'h00000000,


		parameter integer C_M_AXI_ADDR_WIDTH	= 32,


		parameter integer C_M_AXI_DATA_WIDTH	= 32,


		parameter integer C_M_TRANSACTIONS_NUM	= 1
	)
	(

		input wire CAPTURE,
		input wire DRCK   ,
		input wire RESET  ,
		input wire RUNTEST,
		input wire SEL    ,
		input wire SHIFT  ,
		input wire UPDATE ,
		input wire TCK,	
		input wire TDI,	
		input wire TMS,
		output wire TDO,	






		output reg  ERROR,

		output wire  TXN_DONE,

		input wire  M_AXI_ACLK,

		input wire  M_AXI_ARESETN,

		output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,



		output wire [2 : 0] M_AXI_AWPROT,


		output wire  M_AXI_AWVALID,


		input wire  M_AXI_AWREADY,

		output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,



		output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,

		output wire  M_AXI_WVALID,

		input wire  M_AXI_WREADY,


		input wire [1 : 0] M_AXI_BRESP,


		input wire  M_AXI_BVALID,

		output wire  M_AXI_BREADY,

		output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,



		output wire [2 : 0] M_AXI_ARPROT,


		output wire  M_AXI_ARVALID,


		input wire  M_AXI_ARREADY,

		input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,

		input wire [1 : 0] M_AXI_RRESP,

		input wire  M_AXI_RVALID,

		output wire  M_AXI_RREADY
	);
	wire INIT_AXI_TXN_W;
	wire INIT_AXI_TXN_R;



	 function integer clogb2 (input integer bit_depth);
		 begin
		 for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
			 bit_depth = bit_depth >> 1;
		 end
	 endfunction



	 localparam integer TRANS_NUM_BITS = clogb2(C_M_TRANSACTIONS_NUM-1);




	parameter [1:0] IDLE = 2'b00,


		INIT_WRITE   = 2'b01,


		INIT_READ = 2'b10,


		INIT_COMPARE = 2'b11;


	 reg [1:0] mst_exec_state;



	reg  	axi_awvalid;

	reg  	axi_wvalid;

	reg  	axi_arvalid;

	reg  	axi_rready;

	reg  	axi_bready;

	reg [C_M_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;

	reg [C_M_AXI_DATA_WIDTH-1 : 0] 	axi_wdata;

	reg [C_M_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;

	wire  	write_resp_error;

	wire  	read_resp_error;

	reg  	start_single_write;

	reg  	start_single_read;

	reg  	write_issued;

	reg  	read_issued;

	reg  	writes_done;

	reg  	reads_done;

	reg  	error_reg;

	reg [TRANS_NUM_BITS : 0] 	write_index;

	reg [TRANS_NUM_BITS : 0] 	read_index;

	reg [C_M_AXI_DATA_WIDTH-1 : 0] 	expected_rdata;

	reg  	compare_done;

	reg  	read_mismatch;

	reg  	last_write;

	reg  	last_read;
	reg  	init_txn_ff;
	reg  	init_txn_ff2;
	reg  	init_txn_ff_r;
	reg  	init_txn_ff2_r;	
	reg  	init_txn_edge;
	wire  	init_txn_pulse;
	wire	init_txn_pulse_r;




	assign M_AXI_AWADDR	= C_M_TARGET_SLAVE_BASE_ADDR + axi_awaddr;

	assign M_AXI_WDATA	= axi_wdata;
	assign M_AXI_AWPROT	= 3'b000;
	assign M_AXI_AWVALID	= axi_awvalid;

	assign M_AXI_WVALID	= axi_wvalid;

	assign M_AXI_WSTRB	= 4'b1111;

	assign M_AXI_BREADY	= axi_bready;

	assign M_AXI_ARADDR	= C_M_TARGET_SLAVE_BASE_ADDR + axi_awaddr;
	assign M_AXI_ARVALID	= axi_arvalid;
	assign M_AXI_ARPROT	= 3'b001;

	assign M_AXI_RREADY	= axi_rready;

	assign TXN_DONE	= compare_done;
	assign init_txn_pulse	= (!init_txn_ff2) && init_txn_ff;
	assign init_txn_pulse_r	= (!init_txn_ff2_r) && init_txn_ff_r;


	always @(posedge M_AXI_ACLK)										      
	  begin                                                                        

	    if (M_AXI_ARESETN == 0 )                                                   
	      begin                                                                    
	        init_txn_ff <= 1'b0;                                                   
	        init_txn_ff2 <= 1'b0;                                                   
	      end                                                                               
	    else                                                                       
	      begin  
	        init_txn_ff <= INIT_AXI_TXN_W;
	        init_txn_ff2 <= init_txn_ff;                                                                 
	      end                                                                      
	  end     
	  
	always @(posedge M_AXI_ACLK)										      
	  begin                                                                        

	    if (M_AXI_ARESETN == 0 )                                                   
	      begin                                                                    
	        init_txn_ff_r <= 1'b0;                                                   
	        init_txn_ff2_r <= 1'b0;                                                   
	      end                                                                               
	    else                                                                       
	      begin  
	        init_txn_ff_r <= INIT_AXI_TXN_R;
	        init_txn_ff2_r <= init_txn_ff_r;                                                                 
	      end                                                                      
	  end  	  


























	  always @(posedge M_AXI_ACLK)										      
	  begin                                                                        


	    if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)                                                   
	      begin                                                                    
	        axi_awvalid <= 1'b0;                                                   
	      end                                                                      

	    else                                                                       
	      begin                                                                    
	        if (start_single_write)                                                
	          begin                                                                
	            axi_awvalid <= 1'b1;                                               
	          end                                                                  

	        else if (M_AXI_AWREADY && axi_awvalid)                                 
	          begin                                                                
	            axi_awvalid <= 1'b0;                                               
	          end                                                                  
	      end                                                                      
	  end                                                                          
	                                                                               
	                                                                               




	  always @(posedge M_AXI_ACLK)                                                 
	  begin                                                                        
	    if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)                                                   
	      begin                                                                    
	        write_index <= 0;                                                      
	      end                                                                      


	    else if (start_single_write)                                               
	      begin                                                                    
	        write_index <= write_index + 1;                                        
	      end                                                                      
	  end                                                                          










	   always @(posedge M_AXI_ACLK)                                        
	   begin                                                                         
	     if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)                                                    
	       begin                                                                     
	         axi_wvalid <= 1'b0;                                                     
	       end                                                                       

	     else if (start_single_write)                                                
	       begin                                                                     
	         axi_wvalid <= 1'b1;                                                     
	       end                                                                       

	     else if (M_AXI_WREADY && axi_wvalid)                                        
	       begin                                                                     
	        axi_wvalid <= 1'b0;                                                      
	       end                                                                       
	   end                                                                           

















	  always @(posedge M_AXI_ACLK)                                    
	  begin                                                                
	    if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)                                           
	      begin                                                            
	        axi_bready <= 1'b0;                                            
	      end                                                              


	    else if (M_AXI_BVALID && ~axi_bready)                              
	      begin                                                            
	        axi_bready <= 1'b1;                                            
	      end                                                              

	    else if (axi_bready)                                               
	      begin                                                            
	        axi_bready <= 1'b0;                                            
	      end                                                              

	    else                                                               
	      axi_bready <= axi_bready;                                        
	  end                                                                  
	                                                                       

	assign write_resp_error = (axi_bready & M_AXI_BVALID & M_AXI_BRESP[1]);









	  always @(posedge M_AXI_ACLK)                                                     
	  begin                                                                            
	    if (M_AXI_ARESETN == 0 || init_txn_pulse_r == 1'b1)                                                       
	      begin                                                                        
	        read_index <= 0;                                                           
	      end                                                                          


	    else if (start_single_read)                                                    
	      begin                                                                        
	        read_index <= read_index + 1;                                              
	      end                                                                          
	  end                                                                              
	                                                                                   



	  always @(posedge M_AXI_ACLK)                                                     
	  begin                                                                            
	    if (M_AXI_ARESETN == 0 || init_txn_pulse_r == 1'b1)                                                       
	      begin                                                                        
	        axi_arvalid <= 1'b0;                                                       
	      end                                                                          

	    else if (start_single_read)                                                    
	      begin                                                                        
	        axi_arvalid <= 1'b1;                                                       
	      end                                                                          

	    else if (M_AXI_ARREADY && axi_arvalid)                                         
	      begin                                                                        
	        axi_arvalid <= 1'b0;                                                       
	      end                                                                          

	  end                                                                              












	  always @(posedge M_AXI_ACLK)                                    
	  begin                                                                 
	    if (M_AXI_ARESETN == 0 || init_txn_pulse_r == 1'b1)                                            
	      begin                                                             
	        axi_rready <= 1'b0;                                             
	      end                                                               


	    else if (M_AXI_RVALID && ~axi_rready)                               
	      begin                                                             
	        axi_rready <= 1'b1;                                             
	      end                                                               

	    else if (axi_rready)                                                
	      begin                                                             
	        axi_rready <= 1'b0;                                             
	      end                                                               

	  end                                                                   
	                                                                        

	assign read_resp_error = (axi_rready & M_AXI_RVALID & M_AXI_RRESP[1]);  





                                                               
	  always @(posedge M_AXI_ACLK)                                  
	      begin                                                     
	        if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)                                
	          begin                                                 
	            expected_rdata <= C_M_START_DATA_VALUE;             
	          end                                                   


	        else if (M_AXI_RVALID && axi_rready)                    
	          begin                                                 
	            expected_rdata <= C_M_START_DATA_VALUE + read_index;
	          end                                                   
	      end                                                       

	  always @ ( posedge M_AXI_ACLK)                                                    
	  begin                                                                             
	    if (M_AXI_ARESETN == 1'b0)                                                     
	      begin                                                                         


	        mst_exec_state  <= IDLE;                                            
	        start_single_write <= 1'b0;                                                 
	        write_issued  <= 1'b0;                                                      
	        start_single_read  <= 1'b0;                                                 
	        read_issued   <= 1'b0;                                                      
	        compare_done  <= 1'b0;                                                      
	        ERROR <= 1'b0;
	      end                                                                           
	    else                                                                            
	      begin                                                                         

	        case (mst_exec_state)                                                       
	                                                                                    
	          IDLE:                                                             


				begin
					if ( init_txn_pulse == 1'b1 )                                     
					  begin                                                                 
						mst_exec_state  <= INIT_WRITE;                                      
						ERROR <= 1'b0;
						compare_done <= 1'b0;

					  end   
					else if (init_txn_pulse_r)
						begin
						  mst_exec_state <= INIT_READ;
						end
					else                                                                    
					  begin                                                                 
						mst_exec_state  <= IDLE;  

					  end                                                                   
				
				end				
	          INIT_WRITE:                                                               




	            if (writes_done)                                                        
	              begin                                                                 
	                mst_exec_state <= IDLE;
	              end                                                                   
	            else                                                                    
	              begin                                                                 
	                mst_exec_state  <= INIT_WRITE;                                      
	                                                                                    
	                  if (~axi_awvalid && ~axi_wvalid && ~M_AXI_BVALID && ~last_write && ~start_single_write && ~write_issued)
	                    begin                                                           
	                      start_single_write <= 1'b1;                                   
	                      write_issued  <= 1'b1;                                        
	                    end                                                             
	                  else if (axi_bready)                                              
	                    begin                                                           
	                      write_issued  <= 1'b0;                                        
	                    end                                                             
	                  else                                                              
	                    begin                                                           
	                      start_single_write <= 1'b0;
	                    end                                                             
	              end                                                                   
	                                                                                    
	          INIT_READ:                                                                




	             if (reads_done)                                                        
	               begin                                                                
	                 mst_exec_state <= IDLE;                                    
	               end                                                                  
	             else                                                                   
	               begin                                                                
	                 mst_exec_state  <= INIT_READ;                                      
	                                                                                    
	                 if (~axi_arvalid && ~M_AXI_RVALID && ~last_read && ~start_single_read && ~read_issued)
	                   begin                                                            
	                     start_single_read <= 1'b1;                                     
	                     read_issued  <= 1'b1;                                          
	                   end                                                              
	                 else if (axi_rready)                                               
	                   begin                                                            
	                     read_issued  <= 1'b0;                                          
	                   end                                                              
	                 else                                                               
	                   begin                                                            
	                     start_single_read <= 1'b0;
	                   end                                                              
	               end                                                                  
	                                                                                    
	           INIT_COMPARE:                                                            
	             begin



	                 ERROR <= error_reg; 
	                 mst_exec_state <= IDLE;                                    
	                 compare_done <= 1'b1;                                              
	             end                                                                  
	           default :                                                                
	             begin                                                                  
	               mst_exec_state  <= IDLE;                                     
	             end                                                                    
	        endcase                                                                     
	    end                                                                             
	  end
	                                                                                    

	                                                                                    
	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)                                                         
	      last_write <= 1'b0;                                                           
	                                                                                    

	    else if ((write_index == C_M_TRANSACTIONS_NUM) && M_AXI_AWREADY)                
	      last_write <= 1'b1;                                                           
	    else                                                                            
	      last_write <= last_write;                                                     
	  end                                                                               
	                                                                                    

	                                                                                    



	                                                                                    
	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)                                                         
	      writes_done <= 1'b0;                                                          
	                                                                                    

	    else if (last_write && M_AXI_BVALID && axi_bready)                              
	      writes_done <= 1'b1;                                                          
	    else                                                                            
	      writes_done <= writes_done;                                                   
	  end                                                                               
	                                                                                    



	                                                                                    

	                                                                                    
	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0 || init_txn_pulse_r == 1'b1)                                                         
	      last_read <= 1'b0;                                                            
	                                                                                    

	    else if ((read_index == C_M_TRANSACTIONS_NUM) && (M_AXI_ARREADY) )              
	      last_read <= 1'b1;                                                            
	    else                                                                            
	      last_read <= last_read;                                                       
	  end                                                                               
	                                                                                    

	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0 || init_txn_pulse_r == 1'b1)                                                         
	      reads_done <= 1'b0;                                                           
	                                                                                    

	    else if (last_read && M_AXI_RVALID && axi_rready)                               
	      reads_done <= 1'b1;                                                           
	    else                                                                            
	      reads_done <= reads_done;                                                     
	    end                                                                             
	                                                                                    



	                                                                                    

	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0  || init_txn_pulse_r == 1'b1)                                                         
	    read_mismatch <= 1'b0;                                                          
	                                                                                    

	    else if ((M_AXI_RVALID && axi_rready) && (M_AXI_RDATA != expected_rdata))         
	      read_mismatch <= 1'b1;                                                        
	    else                                                                            
	      read_mismatch <= read_mismatch;                                               
	  end                                                                               
	                                                                                    

	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)                                                         
	      error_reg <= 1'b0;                                                            
	                                                                                    

	    else if (read_mismatch || write_resp_error || read_resp_error)                  
	      error_reg <= 1'b1;                                                            
	    else                                                                            
	      error_reg <= error_reg;                                                       
	  end            

	  

	(* srl_style = "register" *) reg [C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH:0] r_shift_regs;
	reg	direct_wr;
	reg [3:0] r_sh_init_axi_txn_w;
	reg [3:0] r_sh_init_axi_txn_r;
	reg [C_M_AXI_DATA_WIDTH-1:0] r_send;
	always @( posedge TCK )
		if ( !M_AXI_ARESETN )
			r_shift_regs <= {(C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH){1'h0}};
		else
			if ( SHIFT && SEL )
				r_shift_regs <= { TDI, r_shift_regs[C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH:1] };
			else if ( CAPTURE && direct_wr && SEL )
				r_shift_regs[C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH-1:C_M_AXI_ADDR_WIDTH] <= r_send;
			
	always @( posedge TCK )	
		if ( !M_AXI_ARESETN )
			begin
				direct_wr	<= 1'h0;
				axi_awaddr	<= {(C_M_AXI_ADDR_WIDTH){1'h0}};
				axi_wdata   <= {(C_M_AXI_DATA_WIDTH){1'h0}};			
			end
		else
			if ( UPDATE && SEL )
				begin
					direct_wr	<= r_shift_regs[C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH];
					axi_awaddr	<= r_shift_regs[C_M_AXI_ADDR_WIDTH-1:0];
					axi_wdata   <= r_shift_regs[C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH-1:C_M_AXI_ADDR_WIDTH];
				end
	
	always @( posedge M_AXI_ACLK )
		if ( !M_AXI_ARESETN )
			begin
				r_sh_init_axi_txn_w	<= 4'h0;
				r_sh_init_axi_txn_r <= 4'h0;
			end
		else
			begin
				r_sh_init_axi_txn_w <= {r_sh_init_axi_txn_w[2:0],UPDATE};
				r_sh_init_axi_txn_r <= {r_sh_init_axi_txn_r[2:0],UPDATE};
			end

assign INIT_AXI_TXN_W = (!direct_wr) ? (!r_sh_init_axi_txn_w[1] & r_sh_init_axi_txn_w[3]) : 1'h0;		
assign INIT_AXI_TXN_R = ( direct_wr) ? (!r_sh_init_axi_txn_r[1] & r_sh_init_axi_txn_r[3]) : 1'h0;	
assign TDO = r_shift_regs[0];	

always @( posedge M_AXI_ACLK )
	if ( !M_AXI_ARESETN )
		r_send <= {(C_M_AXI_DATA_WIDTH){1'b0}};
	else
		if ( M_AXI_RVALID && direct_wr )
			r_send <= M_AXI_RDATA;
		
		



	endmodule
module JTAG2AXIL #
	(






		parameter  C_M_START_DATA_VALUE	= 32'h00000000,


		parameter  C_M_TARGET_SLAVE_BASE_ADDR	= 32'h00000000,


		parameter integer C_M_AXI_ADDR_WIDTH	= 32,


		parameter integer C_M_AXI_DATA_WIDTH	= 32,


		parameter integer C_M_TRANSACTIONS_NUM	= 1
	)
	(

		input wire CAPTURE,
		input wire DRCK   ,
		input wire RESET  ,
		input wire RUNTEST,
		input wire SEL    ,
		input wire SHIFT  ,
		input wire UPDATE ,
		input wire TCK,	
		input wire TDI,	
		input wire TMS,
		output wire TDO,	






		output reg  ERROR,

		output wire  TXN_DONE,

		input wire  M_AXI_ACLK,

		input wire  M_AXI_ARESETN,

		output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,



		output wire [2 : 0] M_AXI_AWPROT,


		output wire  M_AXI_AWVALID,


		input wire  M_AXI_AWREADY,

		output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,



		output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,

		output wire  M_AXI_WVALID,

		input wire  M_AXI_WREADY,


		input wire [1 : 0] M_AXI_BRESP,


		input wire  M_AXI_BVALID,

		output wire  M_AXI_BREADY,

		output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,



		output wire [2 : 0] M_AXI_ARPROT,


		output wire  M_AXI_ARVALID,


		input wire  M_AXI_ARREADY,

		input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,

		input wire [1 : 0] M_AXI_RRESP,

		input wire  M_AXI_RVALID,

		output wire  M_AXI_RREADY
	);

	wire INIT_AXI_TXN_W;
	wire INIT_AXI_TXN_R;



	 function integer clogb2 (input integer bit_depth);
		 begin
		 for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
			 bit_depth = bit_depth >> 1;
		 end
	 endfunction



	 localparam integer TRANS_NUM_BITS = clogb2(C_M_TRANSACTIONS_NUM-1);




	parameter [1:0] IDLE = 2'b00,


		INIT_WRITE   = 2'b01,


		INIT_READ = 2'b10,


		INIT_COMPARE = 2'b11;


	 reg [1:0] mst_exec_state;



	reg  	axi_awvalid;

	reg  	axi_wvalid;

	reg  	axi_arvalid;

	reg  	axi_rready;

	reg  	axi_bready;

	reg [C_M_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;

	reg [C_M_AXI_DATA_WIDTH-1 : 0] 	axi_wdata;

	reg [C_M_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;

	wire  	write_resp_error;

	wire  	read_resp_error;

	reg  	start_single_write;

	reg  	start_single_read;

	reg  	write_issued;

	reg  	read_issued;

	reg  	writes_done;

	reg  	reads_done;

	reg  	error_reg;

	reg [TRANS_NUM_BITS : 0] 	write_index;

	reg [TRANS_NUM_BITS : 0] 	read_index;

	reg [C_M_AXI_DATA_WIDTH-1 : 0] 	expected_rdata;

	reg  	compare_done;

	reg  	read_mismatch;

	reg  	last_write;

	reg  	last_read;
	reg  	init_txn_ff;
	reg  	init_txn_ff2;
	reg  	init_txn_ff_r;
	reg  	init_txn_ff2_r;	
	reg  	init_txn_edge;
	wire  	init_txn_pulse;
	wire	init_txn_pulse_r;




	assign M_AXI_AWADDR	= C_M_TARGET_SLAVE_BASE_ADDR + axi_awaddr;

	assign M_AXI_WDATA	= axi_wdata;
	assign M_AXI_AWPROT	= 3'b000;
	assign M_AXI_AWVALID	= axi_awvalid;

	assign M_AXI_WVALID	= axi_wvalid;

	assign M_AXI_WSTRB	= 4'b1111;

	assign M_AXI_BREADY	= axi_bready;

	assign M_AXI_ARADDR	= C_M_TARGET_SLAVE_BASE_ADDR + axi_awaddr;
	assign M_AXI_ARVALID	= axi_arvalid;
	assign M_AXI_ARPROT	= 3'b001;

	assign M_AXI_RREADY	= axi_rready;

	assign TXN_DONE	= compare_done;
	assign init_txn_pulse	= (!init_txn_ff2) && init_txn_ff;
	assign init_txn_pulse_r	= (!init_txn_ff2_r) && init_txn_ff_r;


	always @(posedge M_AXI_ACLK)										      
	  begin                                                                        

	    if (M_AXI_ARESETN == 0 )                                                   
	      begin                                                                    
	        init_txn_ff <= 1'b0;                                                   
	        init_txn_ff2 <= 1'b0;                                                   
	      end                                                                               
	    else                                                                       
	      begin  
	        init_txn_ff <= INIT_AXI_TXN_W;
	        init_txn_ff2 <= init_txn_ff;                                                                 
	      end                                                                      
	  end     
	  
	always @(posedge M_AXI_ACLK)										      
	  begin                                                                        

	    if (M_AXI_ARESETN == 0 )                                                   
	      begin                                                                    
	        init_txn_ff_r <= 1'b0;                                                   
	        init_txn_ff2_r <= 1'b0;                                                   
	      end                                                                               
	    else                                                                       
	      begin  
	        init_txn_ff_r <= INIT_AXI_TXN_R;
	        init_txn_ff2_r <= init_txn_ff_r;                                                                 
	      end                                                                      
	  end  	  


























	  always @(posedge M_AXI_ACLK)										      
	  begin                                                                        


	    if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)                                                   
	      begin                                                                    
	        axi_awvalid <= 1'b0;                                                   
	      end                                                                      

	    else                                                                       
	      begin                                                                    
	        if (start_single_write)                                                
	          begin                                                                
	            axi_awvalid <= 1'b1;                                               
	          end                                                                  

	        else if (M_AXI_AWREADY && axi_awvalid)                                 
	          begin                                                                
	            axi_awvalid <= 1'b0;                                               
	          end                                                                  
	      end                                                                      
	  end                                                                          
	                                                                               
	                                                                               




	  always @(posedge M_AXI_ACLK)                                                 
	  begin                                                                        
	    if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)                                                   
	      begin                                                                    
	        write_index <= 0;                                                      
	      end                                                                      


	    else if (start_single_write)                                               
	      begin                                                                    
	        write_index <= write_index + 1;                                        
	      end                                                                      
	  end                                                                          










	   always @(posedge M_AXI_ACLK)                                        
	   begin                                                                         
	     if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)                                                    
	       begin                                                                     
	         axi_wvalid <= 1'b0;                                                     
	       end                                                                       

	     else if (start_single_write)                                                
	       begin                                                                     
	         axi_wvalid <= 1'b1;                                                     
	       end                                                                       

	     else if (M_AXI_WREADY && axi_wvalid)                                        
	       begin                                                                     
	        axi_wvalid <= 1'b0;                                                      
	       end                                                                       
	   end                                                                           

















	  always @(posedge M_AXI_ACLK)                                    
	  begin                                                                
	    if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)                                           
	      begin                                                            
	        axi_bready <= 1'b0;                                            
	      end                                                              


	    else if (M_AXI_BVALID && ~axi_bready)                              
	      begin                                                            
	        axi_bready <= 1'b1;                                            
	      end                                                              

	    else if (axi_bready)                                               
	      begin                                                            
	        axi_bready <= 1'b0;                                            
	      end                                                              

	    else                                                               
	      axi_bready <= axi_bready;                                        
	  end                                                                  
	                                                                       

	assign write_resp_error = (axi_bready & M_AXI_BVALID & M_AXI_BRESP[1]);









	  always @(posedge M_AXI_ACLK)                                                     
	  begin                                                                            
	    if (M_AXI_ARESETN == 0 || init_txn_pulse_r == 1'b1)                                                       
	      begin                                                                        
	        read_index <= 0;                                                           
	      end                                                                          


	    else if (start_single_read)                                                    
	      begin                                                                        
	        read_index <= read_index + 1;                                              
	      end                                                                          
	  end                                                                              
	                                                                                   



	  always @(posedge M_AXI_ACLK)                                                     
	  begin                                                                            
	    if (M_AXI_ARESETN == 0 || init_txn_pulse_r == 1'b1)                                                       
	      begin                                                                        
	        axi_arvalid <= 1'b0;                                                       
	      end                                                                          

	    else if (start_single_read)                                                    
	      begin                                                                        
	        axi_arvalid <= 1'b1;                                                       
	      end                                                                          

	    else if (M_AXI_ARREADY && axi_arvalid)                                         
	      begin                                                                        
	        axi_arvalid <= 1'b0;                                                       
	      end                                                                          

	  end                                                                              












	  always @(posedge M_AXI_ACLK)                                    
	  begin                                                                 
	    if (M_AXI_ARESETN == 0 || init_txn_pulse_r == 1'b1)                                            
	      begin                                                             
	        axi_rready <= 1'b0;                                             
	      end                                                               


	    else if (M_AXI_RVALID && ~axi_rready)                               
	      begin                                                             
	        axi_rready <= 1'b1;                                             
	      end                                                               

	    else if (axi_rready)                                                
	      begin                                                             
	        axi_rready <= 1'b0;                                             
	      end                                                               

	  end                                                                   
	                                                                        

	assign read_resp_error = (axi_rready & M_AXI_RVALID & M_AXI_RRESP[1]);  





                                                               
	  always @(posedge M_AXI_ACLK)                                  
	      begin                                                     
	        if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)                                
	          begin                                                 
	            expected_rdata <= C_M_START_DATA_VALUE;             
	          end                                                   


	        else if (M_AXI_RVALID && axi_rready)                    
	          begin                                                 
	            expected_rdata <= C_M_START_DATA_VALUE + read_index;
	          end                                                   
	      end                                                       

	  always @ ( posedge M_AXI_ACLK)                                                    
	  begin                                                                             
	    if (M_AXI_ARESETN == 1'b0)                                                     
	      begin                                                                         


	        mst_exec_state  <= IDLE;                                            
	        start_single_write <= 1'b0;                                                 
	        write_issued  <= 1'b0;                                                      
	        start_single_read  <= 1'b0;                                                 
	        read_issued   <= 1'b0;                                                      
	        compare_done  <= 1'b0;                                                      
	        ERROR <= 1'b0;
	      end                                                                           
	    else                                                                            
	      begin                                                                         

	        case (mst_exec_state)                                                       
	                                                                                    
	          IDLE:                                                             


				begin
					if ( init_txn_pulse == 1'b1 )                                     
					  begin                                                                 
						mst_exec_state  <= INIT_WRITE;                                      
						ERROR <= 1'b0;
						compare_done <= 1'b0;

					  end   
					else if (init_txn_pulse_r)
						begin
						  mst_exec_state <= INIT_READ;
						end
					else                                                                    
					  begin                                                                 
						mst_exec_state  <= IDLE;  

					  end                                                                   
				
				end				
	          INIT_WRITE:                                                               




	            if (writes_done)                                                        
	              begin                                                                 
	                mst_exec_state <= IDLE;
	              end                                                                   
	            else                                                                    
	              begin                                                                 
	                mst_exec_state  <= INIT_WRITE;                                      
	                                                                                    
	                  if (~axi_awvalid && ~axi_wvalid && ~M_AXI_BVALID && ~last_write && ~start_single_write && ~write_issued)
	                    begin                                                           
	                      start_single_write <= 1'b1;                                   
	                      write_issued  <= 1'b1;                                        
	                    end                                                             
	                  else if (axi_bready)                                              
	                    begin                                                           
	                      write_issued  <= 1'b0;                                        
	                    end                                                             
	                  else                                                              
	                    begin                                                           
	                      start_single_write <= 1'b0;
	                    end                                                             
	              end                                                                   
	                                                                                    
	          INIT_READ:                                                                




	             if (reads_done)                                                        
	               begin                                                                
	                 mst_exec_state <= IDLE;                                    
	               end                                                                  
	             else                                                                   
	               begin                                                                
	                 mst_exec_state  <= INIT_READ;                                      
	                                                                                    
	                 if (~axi_arvalid && ~M_AXI_RVALID && ~last_read && ~start_single_read && ~read_issued)
	                   begin                                                            
	                     start_single_read <= 1'b1;                                     
	                     read_issued  <= 1'b1;                                          
	                   end                                                              
	                 else if (axi_rready)                                               
	                   begin                                                            
	                     read_issued  <= 1'b0;                                          
	                   end                                                              
	                 else                                                               
	                   begin                                                            
	                     start_single_read <= 1'b0;
	                   end                                                              
	               end                                                                  
	                                                                                    
	           INIT_COMPARE:                                                            
	             begin



	                 ERROR <= error_reg; 
	                 mst_exec_state <= IDLE;                                    
	                 compare_done <= 1'b1;                                              
	             end                                                                  
	           default :                                                                
	             begin                                                                  
	               mst_exec_state  <= IDLE;                                     
	             end                                                                    
	        endcase                                                                     
	    end                                                                             
	  end
	                                                                                    

	                                                                                    
	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)                                                         
	      last_write <= 1'b0;                                                           
	                                                                                    

	    else if ((write_index == C_M_TRANSACTIONS_NUM) && M_AXI_AWREADY)                
	      last_write <= 1'b1;                                                           
	    else                                                                            
	      last_write <= last_write;                                                     
	  end                                                                               
	                                                                                    

	                                                                                    



	                                                                                    
	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)                                                         
	      writes_done <= 1'b0;                                                          
	                                                                                    

	    else if (last_write && M_AXI_BVALID && axi_bready)                              
	      writes_done <= 1'b1;                                                          
	    else                                                                            
	      writes_done <= writes_done;                                                   
	  end                                                                               
	                                                                                    



	                                                                                    

	                                                                                    
	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0 || init_txn_pulse_r == 1'b1)                                                         
	      last_read <= 1'b0;                                                            
	                                                                                    

	    else if ((read_index == C_M_TRANSACTIONS_NUM) && (M_AXI_ARREADY) )              
	      last_read <= 1'b1;                                                            
	    else                                                                            
	      last_read <= last_read;                                                       
	  end                                                                               
	                                                                                    

	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0 || init_txn_pulse_r == 1'b1)                                                         
	      reads_done <= 1'b0;                                                           
	                                                                                    

	    else if (last_read && M_AXI_RVALID && axi_rready)                               
	      reads_done <= 1'b1;                                                           
	    else                                                                            
	      reads_done <= reads_done;                                                     
	    end                                                                             
	                                                                                    



	                                                                                    

	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0  || init_txn_pulse_r == 1'b1)                                                         
	    read_mismatch <= 1'b0;                                                          
	                                                                                    

	    else if ((M_AXI_RVALID && axi_rready) && (M_AXI_RDATA != expected_rdata))         
	      read_mismatch <= 1'b1;                                                        
	    else                                                                            
	      read_mismatch <= read_mismatch;                                               
	  end                                                                               
	                                                                                    

	  always @(posedge M_AXI_ACLK)                                                      
	  begin                                                                             
	    if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)                                                         
	      error_reg <= 1'b0;                                                            
	                                                                                    

	    else if (read_mismatch || write_resp_error || read_resp_error)                  
	      error_reg <= 1'b1;                                                            
	    else                                                                            
	      error_reg <= error_reg;                                                       
	  end            

	  

	(* srl_style = "register" *) reg [C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH:0] r_shift_regs;
	reg	direct_wr;
	reg [3:0] r_sh_init_axi_txn_w;
	reg [3:0] r_sh_init_axi_txn_r;
	reg [C_M_AXI_DATA_WIDTH-1:0] r_send;
	always @( posedge TCK )
		if ( !M_AXI_ARESETN )
			r_shift_regs <= {(C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH){1'h0}};
		else
			if ( SHIFT && SEL )
				r_shift_regs <= { TDI, r_shift_regs[C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH:1] };
			else if ( CAPTURE && direct_wr && SEL )
				r_shift_regs[C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH-1:C_M_AXI_ADDR_WIDTH] <= r_send;
			
	always @( posedge TCK )	
		if ( !M_AXI_ARESETN )
			begin
				direct_wr	<= 1'h0;
				axi_awaddr	<= {(C_M_AXI_ADDR_WIDTH){1'h0}};
				axi_wdata   <= {(C_M_AXI_DATA_WIDTH){1'h0}};			
			end
		else
			if ( UPDATE && SEL )
				begin
					direct_wr	<= r_shift_regs[C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH];
					axi_awaddr	<= r_shift_regs[C_M_AXI_ADDR_WIDTH-1:0];
					axi_wdata   <= r_shift_regs[C_M_AXI_ADDR_WIDTH+C_M_AXI_DATA_WIDTH-1:C_M_AXI_ADDR_WIDTH];
				end
	
	always @( posedge M_AXI_ACLK )
		if ( !M_AXI_ARESETN )
			begin
				r_sh_init_axi_txn_w	<= 4'h0;
				r_sh_init_axi_txn_r <= 4'h0;
			end
		else
			begin
				r_sh_init_axi_txn_w <= {r_sh_init_axi_txn_w[2:0],UPDATE};
				r_sh_init_axi_txn_r <= {r_sh_init_axi_txn_r[2:0],UPDATE};
			end

assign INIT_AXI_TXN_W = (!direct_wr) ? (!r_sh_init_axi_txn_w[1] & r_sh_init_axi_txn_w[3]) : 1'h0;		
assign INIT_AXI_TXN_R = ( direct_wr) ? (!r_sh_init_axi_txn_r[1] & r_sh_init_axi_txn_r[3]) : 1'h0;	
assign TDO = r_shift_regs[0];	

always @( posedge M_AXI_ACLK )
	if ( !M_AXI_ARESETN )
		r_send <= {(C_M_AXI_DATA_WIDTH){1'b0}};
	else
		if ( M_AXI_RVALID && direct_wr )
			r_send <= M_AXI_RDATA;
		
		



	endmodule