data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/PC.v
data/verilator_xmls/b6c89a7b-17d6-424a-82d5-0f7b30b401c8.xml
module PC(
	input clk,
	input rst_n,
	
	input pcen,
	
	input [31:0] addr,
	input en,
	
	output [31:0] now_addr
);

assign now_addr=nextaddr;

reg [31:0] nowaddr;
reg [31:0] nextaddr;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		nowaddr<=32'hFFFF_FFFC;
	end
	else if(pcen)
	begin
		nowaddr<= nextaddr;
	end
	

end

always@(*)
begin
	if(en)
		nextaddr=addr;
	else
		nextaddr=nowaddr+32'h4;
end


endmodule
module PC(
	input clk,
	input rst_n,
	
	input pcen,
	
	input [31:0] addr,
	input en,
	
	output [31:0] now_addr
);


assign now_addr=nextaddr;

reg [31:0] nowaddr;
reg [31:0] nextaddr;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		nowaddr<=32'hFFFF_FFFC;
	end
	else if(pcen)
	begin
		nowaddr<= nextaddr;
	end
	

end

always@(*)
begin
	if(en)
		nextaddr=addr;
	else
		nextaddr=nowaddr+32'h4;
end


endmodule