data/full_repos/permissive/100918256/CANIPCORETEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:89: Unsupported: Ignoring delay on this delayed statement.\n always #5 sys_clk=~sys_clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:90: Unsupported: Ignoring delay on this delayed statement.\n    always #25 can_clk=~can_clk;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/100918256/CANIPCORETEST.v:34: Little bit endian vector: MSB < LSB of bit range: 0:5\n reg [0:5] bus2ip_addr;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/100918256/CANIPCORETEST.v:35: Little bit endian vector: MSB < LSB of bit range: 0:31\n reg [0:31] bus2ip_data;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/100918256/CANIPCORETEST.v:42: Little bit endian vector: MSB < LSB of bit range: 0:31\n wire [0:31] ip2bus_data;\n      ^\n%Error: data/full_repos/permissive/100918256/CANIPCORETEST.v:45: Cannot find file containing module: \'CAN_BUS_Model\'\n CAN_BUS_Model uut (\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/CAN_BUS_Model\n             data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/CAN_BUS_Model.v\n             data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/CAN_BUS_Model.sv\n             CAN_BUS_Model\n             CAN_BUS_Model.v\n             CAN_BUS_Model.sv\n             obj_dir/CAN_BUS_Model\n             obj_dir/CAN_BUS_Model.v\n             obj_dir/CAN_BUS_Model.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CANIPCORETEST;


	reg can_clk;
	reg can_phy_rx;
	reg bus2ip_reset;
	reg bus2ip_rnw;
	reg bus2ip_cs;
	reg sys_clk;
	reg [0:5] bus2ip_addr;
	reg [0:31] bus2ip_data;


	wire ip2bus_intrevent;
	wire ip2bus_error;
	wire ip2bus_ack;
	wire can_phy_tx;
	wire [0:31] ip2bus_data;


	CAN_BUS_Model uut (
		.can_phy_rx(can_phy_rx), 
		.can_clk(can_clk), 
		.bus2ip_reset(bus2ip_reset), 
		.ip2bus_intrevent(ip2bus_intrevent), 
		.bus2ip_rnw(bus2ip_rnw), 
		.bus2ip_cs(bus2ip_cs), 
		.ip2bus_error(ip2bus_error), 
		.sys_clk(sys_clk), 
		.ip2bus_ack(ip2bus_ack), 
		.can_phy_tx(can_phy_tx), 
		.ip2bus_data(ip2bus_data), 
		.bus2ip_addr(bus2ip_addr), 
		.bus2ip_data(bus2ip_data)
	);

	initial begin

		can_clk = 0;
		bus2ip_reset = 1;
		bus2ip_rnw = 1;
		bus2ip_cs = 0;
		sys_clk = 0;
		bus2ip_addr = 6'd3;
		bus2ip_data = 32'd42;
		can_phy_rx = 1;


		#100;
		bus2ip_reset = 0;
		#10;
		bus2ip_data = 32'd42;
		bus2ip_addr = 6'd3;
		#10;
        bus2ip_cs = 1;
		bus2ip_rnw = 0;
		#50
		bus2ip_cs = 0;
		bus2ip_rnw = 1;
		


	end
	
	always #5 sys_clk=~sys_clk;
    always #25 can_clk=~can_clk;
endmodule
module CANIPCORETEST;



	reg can_clk;
	reg can_phy_rx;
	reg bus2ip_reset;
	reg bus2ip_rnw;
	reg bus2ip_cs;
	reg sys_clk;
	reg [0:5] bus2ip_addr;
	reg [0:31] bus2ip_data;


	wire ip2bus_intrevent;
	wire ip2bus_error;
	wire ip2bus_ack;
	wire can_phy_tx;
	wire [0:31] ip2bus_data;


	CAN_BUS_Model uut (
		.can_phy_rx(can_phy_rx), 
		.can_clk(can_clk), 
		.bus2ip_reset(bus2ip_reset), 
		.ip2bus_intrevent(ip2bus_intrevent), 
		.bus2ip_rnw(bus2ip_rnw), 
		.bus2ip_cs(bus2ip_cs), 
		.ip2bus_error(ip2bus_error), 
		.sys_clk(sys_clk), 
		.ip2bus_ack(ip2bus_ack), 
		.can_phy_tx(can_phy_tx), 
		.ip2bus_data(ip2bus_data), 
		.bus2ip_addr(bus2ip_addr), 
		.bus2ip_data(bus2ip_data)
	);

	initial begin

		can_clk = 0;
		bus2ip_reset = 1;
		bus2ip_rnw = 1;
		bus2ip_cs = 0;
		sys_clk = 0;
		bus2ip_addr = 6'd3;
		bus2ip_data = 32'd42;
		can_phy_rx = 1;


		#100;
		bus2ip_reset = 0;
		#10;
		bus2ip_data = 32'd42;
		bus2ip_addr = 6'd3;
		#10;
        bus2ip_cs = 1;
		bus2ip_rnw = 0;
		#50
		bus2ip_cs = 0;
		bus2ip_rnw = 1;
		


	end
	
	always #5 sys_clk=~sys_clk;
    always #25 can_clk=~can_clk;
endmodule