data/full_repos/permissive/185658197/src/step-1/verilog/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/185658197/src/step-1/verilog/testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #1;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/185658197/src/step-1/verilog/testbench.v:6: Cannot find file containing module: \'Multiplier\'\n  Multiplier multiplier(\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/185658197/src/step-1/verilog,data/full_repos/permissive/185658197/Multiplier\n             data/full_repos/permissive/185658197/src/step-1/verilog,data/full_repos/permissive/185658197/Multiplier.v\n             data/full_repos/permissive/185658197/src/step-1/verilog,data/full_repos/permissive/185658197/Multiplier.sv\n             Multiplier\n             Multiplier.v\n             Multiplier.sv\n             obj_dir/Multiplier\n             obj_dir/Multiplier.v\n             obj_dir/Multiplier.sv\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-1/verilog/testbench.v:18: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                      : ... In instance Testbench\n        a = i;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-1/verilog/testbench.v:19: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                                      : ... In instance Testbench\n        b = j;   \n          ^\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-1/verilog/testbench.v:25: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'p\' generates 16 bits.\n                                                                                      : ... In instance Testbench\n        if (p != i*j) begin\n              ^~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Testbench;  
  reg [7:0] a;
  reg [7:0] b;
  wire [15:0] p;
  
  Multiplier multiplier(
    .a(a),
    .b(b), 
    .p(p)
  );
  
  integer i, j, errCount;  
  initial begin
    $display("Running unsigned multiplication test...");
    errCount = 0;
    for (i = 0; i < 256; i = i + 1) begin
      for (j = 0; j < 256; j = j + 1) begin
        a = i;
        b = j;   
        

        #1;  
        

        if (p != i*j) begin
          errCount = errCount + 1;
          $display("Error: a = %0d, b = %0d, expected = %0d, found = %0d",
            i, j, i*j, p);    
        end
      end      
    end 
  $display("The test is completed with %0d error(s).", errCount);
  $finish;
  end  
endmodule
module Testbench;
  
  reg [7:0] a;
  reg [7:0] b;
  wire [15:0] p;
  
  Multiplier multiplier(
    .a(a),
    .b(b), 
    .p(p)
  );
  
  integer i, j, errCount;  
  initial begin
    $display("Running unsigned multiplication test...");
    errCount = 0;
    for (i = 0; i < 256; i = i + 1) begin
      for (j = 0; j < 256; j = j + 1) begin
        a = i;
        b = j;   
        

        #1;  
        

        if (p != i*j) begin
          errCount = errCount + 1;
          $display("Error: a = %0d, b = %0d, expected = %0d, found = %0d",
            i, j, i*j, p);    
        end
      end      
    end 
  $display("The test is completed with %0d error(s).", errCount);
  $finish;
  end  
endmodule