data/full_repos/permissive/123627914/src/main/modules/program-counter/programCounter.v
data/verilator_xmls/ba42a5a4-7294-4184-bb93-70ede69904b4.xml
module programCounter(
WCLOCK  ,
WO      ,
IADDR   ,
OADDR
);

parameter ADDR_WIDTH = 11;


input                       WCLOCK;
input                       WO;
input   [ADDR_WIDTH-1:0]    IADDR;


output reg [ADDR_WIDTH-1:0] OADDR;




always @(negedge WCLOCK) begin
    if (WO)
        OADDR <= IADDR;
end

endmodule
module programCounter(
WCLOCK  ,
WO      ,
IADDR   ,
OADDR
);


parameter ADDR_WIDTH = 11;


input                       WCLOCK;
input                       WO;
input   [ADDR_WIDTH-1:0]    IADDR;


output reg [ADDR_WIDTH-1:0] OADDR;




always @(negedge WCLOCK) begin
    if (WO)
        OADDR <= IADDR;
end

endmodule