data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v:25: Multiple top level modules\n                                                                                                                                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                                                                                           : ... Top module \'mult_8x8\'\nmodule mult_8x8 (\n       ^~~~~~~~\n                                                                                                                                                                                                           : ... Top module \'mult_16x16\'\nmodule mult_16x16 (\n       ^~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v:26: Little bit endian vector: MSB < LSB of bit range: 0:15\n  input [0:15] A,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v:27: Little bit endian vector: MSB < LSB of bit range: 0:15\n  input [0:15] B,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v:28: Little bit endian vector: MSB < LSB of bit range: 0:31\n  output [0:31] Y\n         ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v:36: Cannot find file containing module: \'mult_16\'\n  mult_16 #() _TECHMAP_REPLACE_ (\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib,data/full_repos/permissive/137416811/mult_16\n             data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib,data/full_repos/permissive/137416811/mult_16.v\n             data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib,data/full_repos/permissive/137416811/mult_16.sv\n             mult_16\n             mult_16.v\n             mult_16.sv\n             obj_dir/mult_16\n             obj_dir/mult_16.v\n             obj_dir/mult_16.sv\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v:5: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input [0:7] A,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v:6: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input [0:7] B,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v:7: Little bit endian vector: MSB < LSB of bit range: 0:15\n  output [0:15] Y\n         ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v:15: Cannot find file containing module: \'mult_8\'\n  mult_8 #() _TECHMAP_REPLACE_ (\n  ^~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n'
module mult_8x8 (
  input [0:7] A,
  input [0:7] B,
  output [0:15] Y
);
  parameter A_SIGNED = 0;
  parameter B_SIGNED = 0;
  parameter A_WIDTH = 0;
  parameter B_WIDTH = 0;
  parameter Y_WIDTH = 0;

  mult_8 #() _TECHMAP_REPLACE_ (
    .A    (A),
    .B    (B),
    .Y    (Y) );

endmodule
module mult_8x8 (
  input [0:7] A,
  input [0:7] B,
  output [0:15] Y
);

  parameter A_SIGNED = 0;
  parameter B_SIGNED = 0;
  parameter A_WIDTH = 0;
  parameter B_WIDTH = 0;
  parameter Y_WIDTH = 0;

  mult_8 #() _TECHMAP_REPLACE_ (
    .A    (A),
    .B    (B),
    .Y    (Y) );

endmodule