data/full_repos/permissive/169522605/hw3_2/nand2.v
data/verilator_xmls/9501cb71-37b0-46df-94c9-8489e6721d31.xml
module nand2 (in1,in2,out);
    input in1,in2;
    output out;
    assign out = ~(in1 & in2);
endmodule
module nand2 (in1,in2,out);

    input in1,in2;
    output out;
    assign out = ~(in1 & in2);
endmodule