data/full_repos/permissive/128659832/verilog/ufifo_tb.v
 line:87: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:55: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile(  "ufifo_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:56: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, ufifo_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_data = i;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_wr = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_wr = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_rd = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_rd = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_data = i;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_wr = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_wr = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #2  INBOX_i_rd = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #2  INBOX_i_rd = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n                #2 ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #1000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hex_to_ascii_digit(data, sel, o_ascii_code);

    input  wire [7:0] data;
    input  wire [1:0] sel;
    output reg [7:0] o_ascii_code;


    reg [3:0] hex_digit;
    always @(*)
    case (sel)
        2'd1: hex_digit = data[7:4];
        2'd2: hex_digit = data[3:0];
        default: hex_digit = 4'h x;
    endcase

    reg [7:0] ascii_code;
    always @(*)
    case (hex_digit)
        4'h0: ascii_code = 8'h30;
        4'h1: ascii_code = 8'h31;
        4'h2: ascii_code = 8'h32;
        4'h3: ascii_code = 8'h33;
        4'h4: ascii_code = 8'h34;
        4'h5: ascii_code = 8'h35;
        4'h6: ascii_code = 8'h36;
        4'h7: ascii_code = 8'h37;
        4'h8: ascii_code = 8'h38;
        4'h9: ascii_code = 8'h39;
        4'hA: ascii_code = 8'h41;
        4'hB: ascii_code = 8'h42;
        4'hC: ascii_code = 8'h43;
        4'hD: ascii_code = 8'h44;
        4'hE: ascii_code = 8'h45;
        4'hF: ascii_code = 8'h46;
        default: ascii_code = 8'h xx;
    endcase

    always @(*)
    case (sel)
        2'd1: o_ascii_code = ascii_code;
        2'd2: o_ascii_code = ascii_code;
        default: o_ascii_code = 8'h xx;
    endcase

endmodule
module hex_to_ascii_digit(data, sel, o_ascii_code);


    input  wire [7:0] data;
    input  wire [1:0] sel;
    output reg [7:0] o_ascii_code;


    reg [3:0] hex_digit;
    always @(*)
    case (sel)
        2'd1: hex_digit = data[7:4];
        2'd2: hex_digit = data[3:0];
        default: hex_digit = 4'h x;
    endcase

    reg [7:0] ascii_code;
    always @(*)
    case (hex_digit)
        4'h0: ascii_code = 8'h30;
        4'h1: ascii_code = 8'h31;
        4'h2: ascii_code = 8'h32;
        4'h3: ascii_code = 8'h33;
        4'h4: ascii_code = 8'h34;
        4'h5: ascii_code = 8'h35;
        4'h6: ascii_code = 8'h36;
        4'h7: ascii_code = 8'h37;
        4'h8: ascii_code = 8'h38;
        4'h9: ascii_code = 8'h39;
        4'hA: ascii_code = 8'h41;
        4'hB: ascii_code = 8'h42;
        4'hC: ascii_code = 8'h43;
        4'hD: ascii_code = 8'h44;
        4'hE: ascii_code = 8'h45;
        4'hF: ascii_code = 8'h46;
        default: ascii_code = 8'h xx;
    endcase

    always @(*)
    case (sel)
        2'd1: o_ascii_code = ascii_code;
        2'd2: o_ascii_code = ascii_code;
        default: o_ascii_code = 8'h xx;
    endcase

endmodule