data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic/sum_bits.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic/sum_bits.v:24: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
function automatic [2:0] sum_bits_4(input [3:0] x);
    reg [2:0] r;
    begin
      case (x)
        4'b0000: r=0;
        4'b0001: r=1;
        4'b0010: r=1;
        4'b0011: r=2;
        4'b0100: r=1;
        4'b0101: r=2;
        4'b0110: r=2;
        4'b0111: r=3;
        4'b1000: r=1;
        4'b1001: r=2;
        4'b1010: r=2;
        4'b1011: r=3;
        4'b1100: r=2;
        4'b1101: r=3;
        4'b1110: r=3;
        4'b1111: r=4;
      endcase
      sum_bits_4 = r;
    end
  endfunction
function automatic [2:0] sum_bits_4(input [3:0] x);

    reg [2:0] r;
    begin
      case (x)
        4'b0000: r=0;
        4'b0001: r=1;
        4'b0010: r=1;
        4'b0011: r=2;
        4'b0100: r=1;
        4'b0101: r=2;
        4'b0110: r=2;
        4'b0111: r=3;
        4'b1000: r=1;
        4'b1001: r=2;
        4'b1010: r=2;
        4'b1011: r=3;
        4'b1100: r=2;
        4'b1101: r=3;
        4'b1110: r=3;
        4'b1111: r=4;
      endcase
      sum_bits_4 = r;
    end
  endfunction