data/full_repos/permissive/112823543/Avalon_LedPanel _Client_Server/LedPanelServer.v
1: b'%Error: Cannot find file containing module: _Client_Server,data/full_repos/permissive/112823543\n        ... Looked in:\n             data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543\n             data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.v\n             data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.sv\n             _Client_Server,data/full_repos/permissive/112823543\n             _Client_Server,data/full_repos/permissive/112823543.v\n             _Client_Server,data/full_repos/permissive/112823543.sv\n             obj_dir/_Client_Server,data/full_repos/permissive/112823543\n             obj_dir/_Client_Server,data/full_repos/permissive/112823543.v\n             obj_dir/_Client_Server,data/full_repos/permissive/112823543.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/112823543/Avalon_LedPanel\n%Error: Cannot find file containing module: _Client_Server/LedPanelServer.v\n%Error: Exiting due to 3 error(s)\n'
module LedPanelServer #(
        parameter COLOR_BITS = 8,
        parameter DISPLAY_ROWS_LINES = 4,
        parameter DISPLAY_COLS_LINES = 6
    ) (
        input   wire        CLK,
        input   wire        RST,
        
        output  reg  [3:0]  ADDR_MST,
        output  reg         CLK_LED_MST,
        output  reg         BLANK_MST,
        output  reg         LATCH_MST,
        
        input   wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES:0]   memAddrIn,
        input   wire [23:0] memDataIn,
        input   wire		memWrite,
        
        output  reg          v_sync,


        output  wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES-1:0]     memAddrMst,
        output  reg  [2:0]  bitplaneMst
    );
	     

    reg [1:0]           clkReg_d, clkReg_q;
    wire                CLK_50 = clkReg_q[1];
    

    reg [DISPLAY_COLS_LINES-1:0]           col;
    reg [DISPLAY_ROWS_LINES-1:0]           row;
 

    localparam          s_00      = 2'b00,
                        s_01      = 2'b01,
                        s_10      = 2'b10,
                        s_11      = 2'b11;

    localparam          s_UNBLANK = 3'b000,
                        s_WAIT    = 3'b001,
                        s_BLANK   = 3'b010,
                        s_LATCH   = 3'b011,
                        s_DELATCH = 3'b100;

    reg [2:0]           state;
    reg                 sig_shifting_ready;
    reg                 shifting_ena;
    reg [13:0]          display_counter;                        
    reg [DISPLAY_ROWS_LINES-1:0]           old_addr;

    assign              memAddrMst = {row, col};
    


	 
	 

    always @(*)   
        begin
            case (clkReg_q)
                2'b00:      clkReg_d = 2'b01;
                2'b01:      clkReg_d = 2'b10;
                2'b10:      clkReg_d = 2'b11;
                2'b11:      clkReg_d = 2'b00;
                default:    clkReg_d = 2'b00;
            endcase
        end

    always @(negedge CLK)
        begin
            clkReg_q <= clkReg_d;
        end


    always @(posedge CLK_50)
        begin
            if (RST) begin
                col = {DISPLAY_COLS_LINES{1'b0}};
                row = {DISPLAY_ROWS_LINES{1'b0}};
                CLK_LED_MST <= 0;
                bitplaneMst <= 3'b000;
                sig_shifting_ready <= 0;
                v_sync <= 0;
            end else begin
                CLK_LED_MST <= 0;
                v_sync <= 0;
                if (state == s_WAIT) begin
                    if ((shifting_ena == 1) && (sig_shifting_ready == 0) ) begin
                        if (CLK_LED_MST == 0) begin

                            col <= col + 1;
                            if (col == &1) begin
                                sig_shifting_ready <= 1;

                                bitplaneMst <= bitplaneMst + 1;
                                if (bitplaneMst == &1) begin

                                    row <= row + 1;
                                    if (row == &1) begin

                                        v_sync <= 1;
                                    end                            
                                end
                            end
                        end
                        CLK_LED_MST <= ~CLK_LED_MST;
                    end
                end else sig_shifting_ready <= 0;

            end
        end
        

    always @(posedge CLK_50)
        begin
            if (RST) begin
                BLANK_MST <= 0;
                ADDR_MST = {DISPLAY_ROWS_LINES{1'b0}};
                old_addr = 0;
            end else begin
                if (state == s_BLANK) begin 
                    BLANK_MST <= 1;
                    ADDR_MST = old_addr;
                    old_addr = row;
                end else if (state == s_UNBLANK) begin
                    BLANK_MST <= 0;
                end
            end
        end


    always @(posedge CLK_50)
        begin
            if (RST)
                LATCH_MST <= 1'b1;
            else begin
                if (state == s_LATCH)
                    LATCH_MST <= 1'b1;
                else if (state == s_DELATCH)
                    LATCH_MST <= 1'b0;
            end
        end
                
    reg sig_wait_done;
    

    always @(posedge CLK_50)
        begin
            if (RST) begin
                display_counter <= 14'd123;
                shifting_ena <= 0;
                sig_wait_done <= 0;
            end else if (state == s_WAIT) begin
                if (display_counter != 0) begin
                    display_counter <= display_counter - 14'b1;
                end else if (sig_shifting_ready) begin
                        shifting_ena <= 0;
                        sig_wait_done <= 1;
                end 
            end else if (state == s_UNBLANK) begin
                case (bitplaneMst)
                    0:  display_counter = 122 << 7;
                    1:  display_counter = 122 << 0;
                    2:  display_counter = 122 << 1;
                    3:  display_counter = 122 << 2;
                    4:  display_counter = 122 << 3;
                    5:  display_counter = 122 << 4;
                    6:  display_counter = 122 << 5;
                    7:  display_counter = 122 << 6;
                    default: display_counter = 122 << 0;
                endcase
                shifting_ena <= 1;
            end else sig_wait_done <= 0;
        end
        

    always @(posedge CLK_50)
        begin
            if (RST) begin  state = s_UNBLANK;
            end else begin
                case    (state)
                    s_UNBLANK:  state = s_WAIT;
                        
                    s_WAIT:     if (sig_wait_done == 1) state = s_BLANK;
                        
                    s_BLANK:    state = s_LATCH;
                    
                    s_LATCH:    state = s_DELATCH;
                        
                    s_DELATCH:  state = s_UNBLANK;
                endcase
            end 
        end
endmodule
module LedPanelServer #(
        parameter COLOR_BITS = 8,
        parameter DISPLAY_ROWS_LINES = 4,
        parameter DISPLAY_COLS_LINES = 6
    ) (
        input   wire        CLK,
        input   wire        RST,
        
        output  reg  [3:0]  ADDR_MST,
        output  reg         CLK_LED_MST,
        output  reg         BLANK_MST,
        output  reg         LATCH_MST,
        
        input   wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES:0]   memAddrIn,
        input   wire [23:0] memDataIn,
        input   wire		memWrite,
        
        output  reg          v_sync,


        output  wire [DISPLAY_ROWS_LINES + DISPLAY_COLS_LINES-1:0]     memAddrMst,
        output  reg  [2:0]  bitplaneMst
    );

	     

    reg [1:0]           clkReg_d, clkReg_q;
    wire                CLK_50 = clkReg_q[1];
    

    reg [DISPLAY_COLS_LINES-1:0]           col;
    reg [DISPLAY_ROWS_LINES-1:0]           row;
 

    localparam          s_00      = 2'b00,
                        s_01      = 2'b01,
                        s_10      = 2'b10,
                        s_11      = 2'b11;

    localparam          s_UNBLANK = 3'b000,
                        s_WAIT    = 3'b001,
                        s_BLANK   = 3'b010,
                        s_LATCH   = 3'b011,
                        s_DELATCH = 3'b100;

    reg [2:0]           state;
    reg                 sig_shifting_ready;
    reg                 shifting_ena;
    reg [13:0]          display_counter;                        
    reg [DISPLAY_ROWS_LINES-1:0]           old_addr;

    assign              memAddrMst = {row, col};
    


	 
	 

    always @(*)   
        begin
            case (clkReg_q)
                2'b00:      clkReg_d = 2'b01;
                2'b01:      clkReg_d = 2'b10;
                2'b10:      clkReg_d = 2'b11;
                2'b11:      clkReg_d = 2'b00;
                default:    clkReg_d = 2'b00;
            endcase
        end

    always @(negedge CLK)
        begin
            clkReg_q <= clkReg_d;
        end


    always @(posedge CLK_50)
        begin
            if (RST) begin
                col = {DISPLAY_COLS_LINES{1'b0}};
                row = {DISPLAY_ROWS_LINES{1'b0}};
                CLK_LED_MST <= 0;
                bitplaneMst <= 3'b000;
                sig_shifting_ready <= 0;
                v_sync <= 0;
            end else begin
                CLK_LED_MST <= 0;
                v_sync <= 0;
                if (state == s_WAIT) begin
                    if ((shifting_ena == 1) && (sig_shifting_ready == 0) ) begin
                        if (CLK_LED_MST == 0) begin

                            col <= col + 1;
                            if (col == &1) begin
                                sig_shifting_ready <= 1;

                                bitplaneMst <= bitplaneMst + 1;
                                if (bitplaneMst == &1) begin

                                    row <= row + 1;
                                    if (row == &1) begin

                                        v_sync <= 1;
                                    end                            
                                end
                            end
                        end
                        CLK_LED_MST <= ~CLK_LED_MST;
                    end
                end else sig_shifting_ready <= 0;

            end
        end
        

    always @(posedge CLK_50)
        begin
            if (RST) begin
                BLANK_MST <= 0;
                ADDR_MST = {DISPLAY_ROWS_LINES{1'b0}};
                old_addr = 0;
            end else begin
                if (state == s_BLANK) begin 
                    BLANK_MST <= 1;
                    ADDR_MST = old_addr;
                    old_addr = row;
                end else if (state == s_UNBLANK) begin
                    BLANK_MST <= 0;
                end
            end
        end


    always @(posedge CLK_50)
        begin
            if (RST)
                LATCH_MST <= 1'b1;
            else begin
                if (state == s_LATCH)
                    LATCH_MST <= 1'b1;
                else if (state == s_DELATCH)
                    LATCH_MST <= 1'b0;
            end
        end
                
    reg sig_wait_done;
    

    always @(posedge CLK_50)
        begin
            if (RST) begin
                display_counter <= 14'd123;
                shifting_ena <= 0;
                sig_wait_done <= 0;
            end else if (state == s_WAIT) begin
                if (display_counter != 0) begin
                    display_counter <= display_counter - 14'b1;
                end else if (sig_shifting_ready) begin
                        shifting_ena <= 0;
                        sig_wait_done <= 1;
                end 
            end else if (state == s_UNBLANK) begin
                case (bitplaneMst)
                    0:  display_counter = 122 << 7;
                    1:  display_counter = 122 << 0;
                    2:  display_counter = 122 << 1;
                    3:  display_counter = 122 << 2;
                    4:  display_counter = 122 << 3;
                    5:  display_counter = 122 << 4;
                    6:  display_counter = 122 << 5;
                    7:  display_counter = 122 << 6;
                    default: display_counter = 122 << 0;
                endcase
                shifting_ena <= 1;
            end else sig_wait_done <= 0;
        end
        

    always @(posedge CLK_50)
        begin
            if (RST) begin  state = s_UNBLANK;
            end else begin
                case    (state)
                    s_UNBLANK:  state = s_WAIT;
                        
                    s_WAIT:     if (sig_wait_done == 1) state = s_BLANK;
                        
                    s_BLANK:    state = s_LATCH;
                    
                    s_LATCH:    state = s_DELATCH;
                        
                    s_DELATCH:  state = s_UNBLANK;
                endcase
            end 
        end
endmodule