data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/multiplier.v
1: b'%Warning-WIDTH: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/multiplier.v:28: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                                    : ... In instance mul\n    assign result = C + S + cin;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mul(
    input  wire        mul_clk,
    input  wire        resetn,
    input  wire        mul_signed,
    
    input  wire [31:0] x,
    input  wire [31:0] y,    
    output wire [63:0] result
);

    wire [65  : 0] dx;
    wire [33  : 0] dy;
    wire [63  : 0] dC;
    wire [63  : 0] dS;
    wire           dCo;
    reg  [63  : 0] C;
    reg  [63  : 0] S;
    reg            cin;
    wire [1121: 0] tmp;
    wire [1121:66] sum;
    wire [1121: 0] tr;
    wire [16  : 0] c;
    wire [989 : 0] mc;
    wire [66  : 0] tc;
    wire [65  : 0] ts;

    assign result = C + S + cin;
    assign dx     = {{34{mul_signed & x[31]}}, x};
    assign dy     = {{ 2{mul_signed & y[31]}}, y};
    assign tc[0]  = c[15];
    assign dCo    = c[16];
    assign dC     = tc[63:0];
    assign dS     = ts[63:0];

    always @(posedge mul_clk) begin
        if (!resetn) begin
            C   <= 64'b0;
            S   <= 64'b0;
            cin <= 1'b0;
        end
        else begin
            C   <= dC;
            S   <= dS;
            cin <= dCo;
        end
    end

    booth_mul booth(
        .x (dx            ),
        .y ({dy[1:0],1'b0}),
        .p (tmp[65:0]     ),
        .c (c[0]          )
    );
    generate genvar i;
        for (i = 1; i < 17; i = i + 1) begin
            booth_mul booth(
                .x (dx                  ),
                .y (dy[i*2+1    : i*2-1]),
                .p (sum[66*i+65 : 66*i ]),
                .c (c[i]                )
            );
            assign tmp[66*i+65 : 66*i] = {sum[64*i+65 : 66*i], {i*2{c[i]}}};
        end
    endgenerate

    generate genvar m, n;
        for (m = 0; m < 66; m = m + 1) begin
        for (n = 0; n < 17; n = n + 1) begin
            assign tr[m*17+n] = tmp [n*66+m];
        end
        end
    endgenerate

    wallace_tree tree(
        .x  (tr[16:0]),
        .ci (c [14:0]),
        .co (mc[14:0]),
        .C  (tc[1]   ),
        .S  (ts[0]   )
    );
    generate genvar j;
        for (j = 1; j < 66; j = j + 1) begin
            wallace_tree tree(
                .x  (tr[17*j+16 : 17*j   ]),
                .ci (mc[15*j-1  : 15*j-15]),
                .co (mc[15*j+14 : 15*j   ]),
                .C  (tc[j+1]              ),
                .S  (ts[j]                )
            );
        end
    endgenerate
endmodule
module mul(
    input  wire        mul_clk,
    input  wire        resetn,
    input  wire        mul_signed,
    
    input  wire [31:0] x,
    input  wire [31:0] y,    
    output wire [63:0] result
);


    wire [65  : 0] dx;
    wire [33  : 0] dy;
    wire [63  : 0] dC;
    wire [63  : 0] dS;
    wire           dCo;
    reg  [63  : 0] C;
    reg  [63  : 0] S;
    reg            cin;
    wire [1121: 0] tmp;
    wire [1121:66] sum;
    wire [1121: 0] tr;
    wire [16  : 0] c;
    wire [989 : 0] mc;
    wire [66  : 0] tc;
    wire [65  : 0] ts;

    assign result = C + S + cin;
    assign dx     = {{34{mul_signed & x[31]}}, x};
    assign dy     = {{ 2{mul_signed & y[31]}}, y};
    assign tc[0]  = c[15];
    assign dCo    = c[16];
    assign dC     = tc[63:0];
    assign dS     = ts[63:0];

    always @(posedge mul_clk) begin
        if (!resetn) begin
            C   <= 64'b0;
            S   <= 64'b0;
            cin <= 1'b0;
        end
        else begin
            C   <= dC;
            S   <= dS;
            cin <= dCo;
        end
    end

    booth_mul booth(
        .x (dx            ),
        .y ({dy[1:0],1'b0}),
        .p (tmp[65:0]     ),
        .c (c[0]          )
    );
    generate genvar i;
        for (i = 1; i < 17; i = i + 1) begin
            booth_mul booth(
                .x (dx                  ),
                .y (dy[i*2+1    : i*2-1]),
                .p (sum[66*i+65 : 66*i ]),
                .c (c[i]                )
            );
            assign tmp[66*i+65 : 66*i] = {sum[64*i+65 : 66*i], {i*2{c[i]}}};
        end
    endgenerate

    generate genvar m, n;
        for (m = 0; m < 66; m = m + 1) begin
        for (n = 0; n < 17; n = n + 1) begin
            assign tr[m*17+n] = tmp [n*66+m];
        end
        end
    endgenerate

    wallace_tree tree(
        .x  (tr[16:0]),
        .ci (c [14:0]),
        .co (mc[14:0]),
        .C  (tc[1]   ),
        .S  (ts[0]   )
    );
    generate genvar j;
        for (j = 1; j < 66; j = j + 1) begin
            wallace_tree tree(
                .x  (tr[17*j+16 : 17*j   ]),
                .ci (mc[15*j-1  : 15*j-15]),
                .co (mc[15*j+14 : 15*j   ]),
                .C  (tc[j+1]              ),
                .S  (ts[j]                )
            );
        end
    endgenerate
endmodule