data/full_repos/permissive/194847941/demo/10_SDRAM_TEST/pll1.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/194847941/demo/10_SDRAM_TEST/pll1.v:67: In defparam, cell pll0_clk never declared\ndefparam pll0_clk.CLKC0_FPHASE   = "5";     \n                                 ^\n%Error: data/full_repos/permissive/194847941/demo/10_SDRAM_TEST/pll1.v:68: In defparam, cell pll0_clk never declared\ndefparam pll0_clk.CLKC1_FPHASE   = "0";     \n                                 ^\n%Error: data/full_repos/permissive/194847941/demo/10_SDRAM_TEST/pll1.v:69: In defparam, cell pll0_clk never declared\ndefparam pll0_clk.CLKC2_FPHASE   = "7";     \n                                 ^\n%Error: data/full_repos/permissive/194847941/demo/10_SDRAM_TEST/pll1.v:70: In defparam, cell pll0_clk never declared\ndefparam pll0_clk.CLKC3_FPHASE   = "7";     \n                                 ^\n%Error: data/full_repos/permissive/194847941/demo/10_SDRAM_TEST/pll1.v:71: In defparam, cell pll0_clk never declared\ndefparam pll0_clk.CLKC4_FPHASE   = "0";     \n                                 ^\n%Error: Exiting due to 5 error(s)\n'
module pll1 (
	inclk0,
	reset,
	c0,
	c1,
	c2,
	c3,
	c4,
	ext_lock
	);

input inclk0,reset;
output ext_lock;
output c0;
output c1;
output c2;
output c3;
output c4;


wire [4:0] clkc;
wire [2:0] dummy;

    EG_LOGIC_BUFG  pll_c0(.o(c0),.i(clkc[0]));
    EG_LOGIC_BUFG  pll_c1(.o(c1),.i(clkc[1]));
    EG_LOGIC_BUFG  pll_c2(.o(c2),.i(clkc[2]));
    EG_LOGIC_BUFG  pll_c3(.o(c3),.i(clkc[3]));
    EG_LOGIC_BUFG  pll_c4(.o(c4),.i(clkc[4]));







EG_PHY_PLL  pll_clk (.refclk(inclk0),
                     .reset(reset),
			    .stdby(1'b0),
                     .clkc(clkc),
                     .extlock(ext_lock)

				);  
defparam pll_clk.FBCLK_DIV = 45;
defparam pll_clk.CLKC0_DIV = 8;
defparam pll_clk.CLKC1_DIV = 8;
defparam pll_clk.CLKC2_DIV = 8;
defparam pll_clk.CLKC3_DIV = 8;
defparam pll_clk.CLKC4_DIV = 8;

defparam pll_clk.CLKC0_ENABLE = "ENABLE";
defparam pll_clk.CLKC1_ENABLE = "ENABLE";
defparam pll_clk.CLKC2_ENABLE = "DISABLE";
defparam pll_clk.CLKC3_ENABLE = "DISABLE";
defparam pll_clk.CLKC4_ENABLE = "DISABLE";


defparam pll_clk.CLKC0_CPHASE = 6;
defparam pll_clk.CLKC1_CPHASE = 0;
defparam pll_clk.CLKC2_CPHASE = 4;
defparam pll_clk.CLKC3_CPHASE = 2;
defparam pll_clk.CLKC4_CPHASE = 0;


defparam pll0_clk.CLKC0_FPHASE   = "5";
defparam pll0_clk.CLKC1_FPHASE   = "0";
defparam pll0_clk.CLKC2_FPHASE   = "7";
defparam pll0_clk.CLKC3_FPHASE   = "7";
defparam pll0_clk.CLKC4_FPHASE   = "0";

endmodule
module pll1 (
	inclk0,
	reset,
	c0,
	c1,
	c2,
	c3,
	c4,
	ext_lock
	);


input inclk0,reset;
output ext_lock;
output c0;
output c1;
output c2;
output c3;
output c4;


wire [4:0] clkc;
wire [2:0] dummy;

    EG_LOGIC_BUFG  pll_c0(.o(c0),.i(clkc[0]));
    EG_LOGIC_BUFG  pll_c1(.o(c1),.i(clkc[1]));
    EG_LOGIC_BUFG  pll_c2(.o(c2),.i(clkc[2]));
    EG_LOGIC_BUFG  pll_c3(.o(c3),.i(clkc[3]));
    EG_LOGIC_BUFG  pll_c4(.o(c4),.i(clkc[4]));







EG_PHY_PLL  pll_clk (.refclk(inclk0),
                     .reset(reset),
			    .stdby(1'b0),
                     .clkc(clkc),
                     .extlock(ext_lock)

				);  
defparam pll_clk.FBCLK_DIV = 45;
defparam pll_clk.CLKC0_DIV = 8;
defparam pll_clk.CLKC1_DIV = 8;
defparam pll_clk.CLKC2_DIV = 8;
defparam pll_clk.CLKC3_DIV = 8;
defparam pll_clk.CLKC4_DIV = 8;

defparam pll_clk.CLKC0_ENABLE = "ENABLE";
defparam pll_clk.CLKC1_ENABLE = "ENABLE";
defparam pll_clk.CLKC2_ENABLE = "DISABLE";
defparam pll_clk.CLKC3_ENABLE = "DISABLE";
defparam pll_clk.CLKC4_ENABLE = "DISABLE";


defparam pll_clk.CLKC0_CPHASE = 6;
defparam pll_clk.CLKC1_CPHASE = 0;
defparam pll_clk.CLKC2_CPHASE = 4;
defparam pll_clk.CLKC3_CPHASE = 2;
defparam pll_clk.CLKC4_CPHASE = 0;


defparam pll0_clk.CLKC0_FPHASE   = "5";
defparam pll0_clk.CLKC1_FPHASE   = "0";
defparam pll0_clk.CLKC2_FPHASE   = "7";
defparam pll0_clk.CLKC3_FPHASE   = "7";
defparam pll0_clk.CLKC4_FPHASE   = "0";

endmodule