data/full_repos/permissive/143278/ivltests/vhdl_notg_stdlogic.v
 line:18: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_notg_stdlogic.v:5: Unsupported: Ignoring delay on this delayed statement.\n    #0  A = 1\'bx;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_notg_stdlogic.v:7: Unsupported: Ignoring delay on this delayed statement.\n    #10 A = 1\'bz;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_notg_stdlogic.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #10 A = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_notg_stdlogic.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #10 A = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_notg_stdlogic.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_notg_stdlogic.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Warning-IMPLICIT: data/full_repos/permissive/143278/ivltests/vhdl_notg_stdlogic.v:52: Signal definition not found, creating implicitly: \'A\'\n  stimulus     stim    (A);\n                        ^\n%Warning-IMPLICIT: data/full_repos/permissive/143278/ivltests/vhdl_notg_stdlogic.v:54: Signal definition not found, creating implicitly: \'Y\'\n  scoreboard   mon     (Y, A);\n                        ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_notg_stdlogic.v:53: Cannot find file containing module: \'not_gate\'\n  not_gate     duv     (.a_i(A), .c_o(Y) );\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/not_gate\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/not_gate.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/not_gate.sv\n             not_gate\n             not_gate.v\n             not_gate.sv\n             obj_dir/not_gate\n             obj_dir/not_gate.v\n             obj_dir/not_gate.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stimulus (output reg A);

  initial begin

    #0  A = 1'bx;

    #10 A = 1'bz;

    #10 A = 1'b0;

    #10 A = 1'b1;
  end

endmodule
module stimulus (output reg A);


  initial begin

    #0  A = 1'bx;

    #10 A = 1'bz;

    #10 A = 1'b0;

    #10 A = 1'b1;
  end

endmodule