data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/Xilinx/xc_tb.v
 line:10: before: "reg"
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/Xilinx/xc_tb.v:4: Unsupported: Ignoring delay on this delayed statement.\n always #5 clock <= ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/Xilinx/xc_tb.v:9: Unsupported: Verilog 2001-config reserved word not implemented: \'config\'\n reg config\n     ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/Xilinx/xc_tb.v:10: syntax error, unexpected reg, expecting IDENTIFIER or \'=\' or do or final\n reg [2:0] command;\n ^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module xilinx_controller_tb;
	
	reg	clock	= 1;
	always	#5	clock	<= ~clock;
	reg	reset	= 0;
	
	reg	[22:0]	user_addr;
	reg	[1:0]	user_ba;
	reg	config
	reg	[2:0]	command;
	
	controller controller0 (
		.dip1               ( CKE),
		.clk                ( clock), 
		.rst0               ( reset),
		.rst180             ( reset),
		
		.address            ( user_input_address),
		.bank_address       ( user_bank_address),
		.config_register    ( user_config_register),
		.command_register   ( user_command_register),
		.burst_done         ( burst_done),
		
		.ddr_rasb_cntrl     ( ddr_rasb_cntrl),
		.ddr_casb_cntrl     ( ddr_casb_cntrl),
		.ddr_web_cntrl      ( ddr_web_cntrl),
		.ddr_ba_cntrl       ( ddr_ba_cntrl),
		.ddr_address_cntrl  ( ddr_address_cntrl),
		.ddr_cke_cntrl      ( ddr_cke_cntrl),
		.ddr_csb_cntrl      ( ddr_csb_cntrl),
		.dqs_enable         ( dqs_enable),
		.dqs_reset          ( dqs_reset),
		.write_enable       ( write_enable),
		.rst_calib          ( rst_calib),
		.rst_dqs_div_int    ( rst_dqs_div_int),
		.rst_dqs_div_int1   ( rst_dqs_div_int1),
		.cmd_ack            ( user_cmd_ack),
		.init               ( init_val),
		.ar_done            ( ar_done)
		
	);
	
endmodule
module xilinx_controller_tb;

	
	reg	clock	= 1;
	always	#5	clock	<= ~clock;
	reg	reset	= 0;
	
	reg	[22:0]	user_addr;
	reg	[1:0]	user_ba;
	reg	config
	reg	[2:0]	command;
	
	controller controller0 (
		.dip1               ( CKE),
		.clk                ( clock), 
		.rst0               ( reset),
		.rst180             ( reset),
		
		.address            ( user_input_address),
		.bank_address       ( user_bank_address),
		.config_register    ( user_config_register),
		.command_register   ( user_command_register),
		.burst_done         ( burst_done),
		
		.ddr_rasb_cntrl     ( ddr_rasb_cntrl),
		.ddr_casb_cntrl     ( ddr_casb_cntrl),
		.ddr_web_cntrl      ( ddr_web_cntrl),
		.ddr_ba_cntrl       ( ddr_ba_cntrl),
		.ddr_address_cntrl  ( ddr_address_cntrl),
		.ddr_cke_cntrl      ( ddr_cke_cntrl),
		.ddr_csb_cntrl      ( ddr_csb_cntrl),
		.dqs_enable         ( dqs_enable),
		.dqs_reset          ( dqs_reset),
		.write_enable       ( write_enable),
		.rst_calib          ( rst_calib),
		.rst_dqs_div_int    ( rst_dqs_div_int),
		.rst_dqs_div_int1   ( rst_dqs_div_int1),
		.cmd_ack            ( user_cmd_ack),
		.init               ( init_val),
		.ar_done            ( ar_done)
		
	);
	
endmodule