data/full_repos/permissive/133043770/AddOperationTest.v
1: b'%Error: data/full_repos/permissive/133043770/AddOperationTest.v:2: Cannot find include file: AddOperation.v\n`include "AddOperation.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133043770,data/full_repos/permissive/133043770/AddOperation.v\n             data/full_repos/permissive/133043770,data/full_repos/permissive/133043770/AddOperation.v.v\n             data/full_repos/permissive/133043770,data/full_repos/permissive/133043770/AddOperation.v.sv\n             AddOperation.v\n             AddOperation.v.v\n             AddOperation.v.sv\n             obj_dir/AddOperation.v\n             obj_dir/AddOperation.v.v\n             obj_dir/AddOperation.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/133043770/AddOperationTest.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133043770/AddOperationTest.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133043770/AddOperationTest.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133043770/AddOperationTest.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133043770/AddOperationTest.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module AddOperationTest;


	reg [11:0] lhs;
	reg [11:0] rhs;


	wire [11:0] result;
	wire overflow;


	AddOperation uut (
		.lhs(lhs), 
		.rhs(rhs), 
		.result(result), 
		.overflow(overflow)
	);

	initial begin

		lhs = 5;
		rhs = 5;

		#5;
		rhs = 10;
		#5;
		lhs = 10;
		#5;
		rhs = 12'hFFF;
		#5;
		lhs = 12'hFFF;
		#5;
		$finish;
	end
      
endmodule
module AddOperationTest;



	reg [11:0] lhs;
	reg [11:0] rhs;


	wire [11:0] result;
	wire overflow;


	AddOperation uut (
		.lhs(lhs), 
		.rhs(rhs), 
		.result(result), 
		.overflow(overflow)
	);

	initial begin

		lhs = 5;
		rhs = 5;

		#5;
		rhs = 10;
		#5;
		lhs = 10;
		#5;
		rhs = 12'hFFF;
		#5;
		lhs = 12'hFFF;
		#5;
		$finish;
	end
      
endmodule