data/full_repos/permissive/113780415/src/top_test.v
 line:1736: before: "&&"
1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(posedge clk && enable == 1'b1)\n                                   ^~\n%Error: Cannot continue\n"
module ratedivider(clear_b, clk, out);



    input clear_b;

    input clk;

    output out;



    reg [30:0] q;

    reg [30:0] t = 125000;

	                 

    assign out = (q == 0) ? 1 : 0;

    

 



    always @(posedge clk)

    begin

        if (clear_b == 1'b0)

            q <= t;

        else if (q == 1'b0)

            q <= t;

        else

            q <= q - 1'b1;

    end

endmodule
module ratedivider(clear_b, clk, out);




    input clear_b;

    input clk;

    output out;



    reg [30:0] q;

    reg [30:0] t = 125000;

	                 

    assign out = (q == 0) ? 1 : 0;

    

 



    always @(posedge clk)

    begin

        if (clear_b == 1'b0)

            q <= t;

        else if (q == 1'b0)

            q <= t;

        else

            q <= q - 1'b1;

    end

endmodule