data/full_repos/permissive/143278/vhdl_tests/pr2541625.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/pr2541625.v:8: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module child(in1, in2, out);
  input in1, in2;
  output out;

  assign out = in1 & in2;
endmodule
module child(in1, in2, out);

  input in1, in2;
  output out;

  assign out = in1 & in2;
endmodule