data/full_repos/permissive/141038711/tb/apb_pulse_test.v
 line:47: before: "#"
1: b'%Error: data/full_repos/permissive/141038711/tb/apb_pulse_test.v:46: syntax error, unexpected \'@\'\n      @(posedge pclk)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_pulse_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n       #(CLK_PERIOD*5) ; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/141038711/tb/apb_pulse_test.v:55: syntax error, unexpected \'@\'\n          @(posedge pclk);\n          ^\n%Error: data/full_repos/permissive/141038711/tb/apb_pulse_test.v:66: syntax error, unexpected \'@\'\n          @(posedge pclk);\n          ^\n%Error: data/full_repos/permissive/141038711/tb/apb_pulse_test.v:76: syntax error, unexpected \'@\'\n          @(posedge pclk);\n          ^\n%Error: data/full_repos/permissive/141038711/tb/apb_pulse_test.v:84: syntax error, unexpected \'@\'\n          @(posedge pclk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_pulse_test.v:97: Unsupported: Ignoring delay on this delayed statement.\n   #500 $stop;       \n   ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module apb_pulse_test;

localparam CLK_PERIOD=100;




reg          reset_n;
reg          enable;


wire         pclk;
wire [ 15:0] paddr;
wire         pwrite;
wire         psel;
wire         penable;
wire [ 31:0] pwdata;
wire [ 31:0] prdata;
wire         pready;
wire         pslverr;


wire pulse_write;
wire pulse_writebit;
wire pulse_read;


reg fail;
integer i;

   initial
   begin


      reset_n    = 1'b0;
      enable     = 1'b1;
      fail = 0;
      
      @(posedge pclk)
         #(CLK_PERIOD*5) ; 
      reset_n = 1'b1;
       #(CLK_PERIOD*5) ; 
       

       apb_bus0.write(16'h0,32'h0);

       for (i=0; i<3; i=i+1)
          @(posedge pclk);
       @(posedge pclk)
          if (pulse_write!==1'b1)
             fail = 1;
       @(posedge pclk)
          if (pulse_write!==1'b0)
             fail = 1;
              
       apb_bus0.write(16'h4,32'h1);

       for (i=0; i<3; i=i+1)
          @(posedge pclk);
       @(posedge pclk)
          if (pulse_writebit!==1'b1)
             fail = 1;
       @(posedge pclk)
          if (pulse_writebit!==1'b0)
             fail = 1;
       
       apb_bus0.write(16'h4,32'h0);
       for (i=0; i<3; i=i+1)
          @(posedge pclk);
       @(posedge pclk)
          if (pulse_writebit!==1'b0)
             fail = 1;
       
        apb_bus0.read(16'h8,32'hx);

       for (i=0; i<3; i=i+1)
          @(posedge pclk);
       @(posedge pclk)
          if (pulse_read!==1'b1)
             fail = 1;
       @(posedge pclk)
          if (pulse_read!==1'b0)
             fail = 1;
       
       if (fail==0)
          $display("apb_pulse test passed");
       else
          $display("apb_pulse test FAILED!");
		
		 #500 $stop;       
   end


apb_pulse
apb_pulse_0 (


      .reset_n  (reset_n),
      .enable   (enable),


      .pclk     (pclk),
      .paddr    (paddr[3:0]),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr),


      .pulse_write   (pulse_write   ),
      .pulse_writebit(pulse_writebit),
      .pulse_read    (pulse_read    )
   );
   
apb_bus 
#(.CLKPER(CLK_PERIOD)
 )
apb_bus0 (

      .pclk     (pclk),
      .paddr    (paddr),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr)
      ); 
   


endmodule
module apb_pulse_test;


localparam CLK_PERIOD=100;




reg          reset_n;
reg          enable;


wire         pclk;
wire [ 15:0] paddr;
wire         pwrite;
wire         psel;
wire         penable;
wire [ 31:0] pwdata;
wire [ 31:0] prdata;
wire         pready;
wire         pslverr;


wire pulse_write;
wire pulse_writebit;
wire pulse_read;


reg fail;
integer i;

   initial
   begin


      reset_n    = 1'b0;
      enable     = 1'b1;
      fail = 0;
      
      @(posedge pclk)
         #(CLK_PERIOD*5) ; 
      reset_n = 1'b1;
       #(CLK_PERIOD*5) ; 
       

       apb_bus0.write(16'h0,32'h0);

       for (i=0; i<3; i=i+1)
          @(posedge pclk);
       @(posedge pclk)
          if (pulse_write!==1'b1)
             fail = 1;
       @(posedge pclk)
          if (pulse_write!==1'b0)
             fail = 1;
              
       apb_bus0.write(16'h4,32'h1);

       for (i=0; i<3; i=i+1)
          @(posedge pclk);
       @(posedge pclk)
          if (pulse_writebit!==1'b1)
             fail = 1;
       @(posedge pclk)
          if (pulse_writebit!==1'b0)
             fail = 1;
       
       apb_bus0.write(16'h4,32'h0);
       for (i=0; i<3; i=i+1)
          @(posedge pclk);
       @(posedge pclk)
          if (pulse_writebit!==1'b0)
             fail = 1;
       
        apb_bus0.read(16'h8,32'hx);

       for (i=0; i<3; i=i+1)
          @(posedge pclk);
       @(posedge pclk)
          if (pulse_read!==1'b1)
             fail = 1;
       @(posedge pclk)
          if (pulse_read!==1'b0)
             fail = 1;
       
       if (fail==0)
          $display("apb_pulse test passed");
       else
          $display("apb_pulse test FAILED!");
		
		 #500 $stop;       
   end


apb_pulse
apb_pulse_0 (


      .reset_n  (reset_n),
      .enable   (enable),


      .pclk     (pclk),
      .paddr    (paddr[3:0]),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr),


      .pulse_write   (pulse_write   ),
      .pulse_writebit(pulse_writebit),
      .pulse_read    (pulse_read    )
   );
   
apb_bus 
#(.CLKPER(CLK_PERIOD)
 )
apb_bus0 (

      .pclk     (pclk),
      .paddr    (paddr),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr)
      ); 
   


endmodule