data/full_repos/permissive/156417892/hdl/WriteBack/WriteBack_test.v
 line:6: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/WriteBack/WriteBack_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/WriteBack/WriteBack_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n #25 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/156417892/hdl/WriteBack/WriteBack_test.v:41: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("./main_test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/156417892/hdl/WriteBack/WriteBack_test.v:42: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;


   reg clk, resetn=1;
   reg iSig_regfile_write, iSig_MemtoReg;
   reg [31:0] iread_from_ram, ialu_result;

   wire [31:0] odata2write2regfile;

   integer    i;


   WriteBack uut(
                  clk,
                  rstn,
                  iSig_regfile_write,
                  iSig_MemtoReg,
                  iread_from_ram,
                  ialu_result,
                  odata2write2regfile,
                  );

   initial begin

      resetn = 0;
      #10;


   end

   initial begin
      clk = 0;
      for (i = 0; i < 2000; i = i + 1)
	#25 clk = ~clk;
   end


   initial begin
      $dumpfile("./main_test.vcd");
      $dumpvars;
   end

endmodule
module main_test;



   reg clk, resetn=1;
   reg iSig_regfile_write, iSig_MemtoReg;
   reg [31:0] iread_from_ram, ialu_result;

   wire [31:0] odata2write2regfile;

   integer    i;


   WriteBack uut(
                  clk,
                  rstn,
                  iSig_regfile_write,
                  iSig_MemtoReg,
                  iread_from_ram,
                  ialu_result,
                  odata2write2regfile,
                  );

   initial begin

      resetn = 0;
      #10;


   end

   initial begin
      clk = 0;
      for (i = 0; i < 2000; i = i + 1)
	#25 clk = ~clk;
   end


   initial begin
      $dumpfile("./main_test.vcd");
      $dumpvars;
   end

endmodule