data/full_repos/permissive/205673649/MIPS/Source/control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:52: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                             : ... In instance control\n                o_ctrl_ex = {7\'b0010000,o_alu_control};    \n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:59: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                             : ... In instance control\n                o_ctrl_ex = {7\'b0001100,o_alu_control}; \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:68: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                             : ... In instance control\n                    o_ctrl_ex = {7\'b0000110,o_alu_control};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:70: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                             : ... In instance control\n                    o_ctrl_ex = {7\'b0000100,o_alu_control};  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:78: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                             : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:86: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                             : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:94: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                             : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:102: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:110: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:118: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:126: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:134: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:142: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:151: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};  \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:159: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};  \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:167: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};  \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:175: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};  \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:183: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};  \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:191: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000001,o_alu_control};  \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:199: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000000,o_alu_control}; \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:207: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000000,o_alu_control}; \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:215: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0100000,o_alu_control};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:223: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b1000000,o_alu_control};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/205673649/MIPS/Source/control.v:231: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                              : ... In instance control\n            o_ctrl_ex = {7\'b0000000,o_alu_control};\n                      ^\n%Error: data/full_repos/permissive/205673649/MIPS/Source/control.v:237: Cannot find file containing module: \'alu_control\'\nalu_control\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/MIPS/Source,data/full_repos/permissive/205673649/alu_control\n             data/full_repos/permissive/205673649/MIPS/Source,data/full_repos/permissive/205673649/alu_control.v\n             data/full_repos/permissive/205673649/MIPS/Source,data/full_repos/permissive/205673649/alu_control.sv\n             alu_control\n             alu_control.v\n             alu_control.sv\n             obj_dir/alu_control\n             obj_dir/alu_control.v\n             obj_dir/alu_control.sv\n%Error: Exiting due to 1 error(s), 24 warning(s)\n'
module control
#(  parameter NB_INSTRUCCION = 6,
    parameter NB_CTRL_WB = 2,
    parameter NB_CTRL_MEM = 9,
    parameter NB_CTRL_EX = 8,
    parameter NB_ALU_CONTROL = 4,
    parameter NB_ALU_OP = 2
)
(
    input [NB_INSTRUCCION-1:0] i_opcode,
    input [NB_INSTRUCCION-1:0] i_inst_funcion,
    output reg [NB_CTRL_WB-1:0] o_ctrl_wb,
    output reg [NB_CTRL_MEM-1:0] o_ctrl_mem,
    output reg [NB_CTRL_EX-1:0] o_ctrl_ex
);

reg [NB_ALU_OP-1:0] alu_op;
wire [NB_ALU_CONTROL-1:0] o_alu_control;

always @(*)
begin
    case(i_opcode)
        6'b000000:
        begin
            if(i_inst_funcion == 6'b001000)
            begin
                alu_op = 2'b10;
                o_ctrl_wb = 2'b00;
                o_ctrl_mem = 9'b000000000;
                o_ctrl_ex = {7'b0010000,o_alu_control};    
            end
            else if(i_inst_funcion == 6'b001001)
            begin
                alu_op = 2'b10;
                o_ctrl_wb = 2'b10;
                o_ctrl_mem = 9'b000000000;
                o_ctrl_ex = {7'b0001100,o_alu_control}; 
            end
            
            else
            begin
                alu_op = 2'b10;
                o_ctrl_wb = 2'b10;
                o_ctrl_mem = 9'b000000000;
                if((i_inst_funcion == 6'b000000) || (i_inst_funcion == 6'b000010) || (i_inst_funcion == 6'b000011))
                    o_ctrl_ex = {7'b0000110,o_alu_control};
                else    
                    o_ctrl_ex = {7'b0000100,o_alu_control};
            end
        end
        
        6'b100000:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000100010;
        end
        
        6'b100001:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000010010; 
        end
        
        6'b100011:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000000010;  
        end
        
        6'b100111:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000000010;  
        end
        
        6'b100100:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000101010;
        end
        
        6'b100101:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000011010; 
        end
        
        6'b101000:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b00;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b010000001;
        end
        
        6'b101001:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b00;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b001000001;
        end
        
        6'b101011:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b00;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000000001;
        end
        
        6'b001000:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b001100:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b001101:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b001110:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b001111:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b001010:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b000100:
        begin
            alu_op = 2'b01;
            o_ctrl_wb = 2'b00;
            o_ctrl_mem = 9'b000000100;  
            o_ctrl_ex = {7'b0000000,o_alu_control}; 
        end
        
        6'b000101:
        begin
            alu_op = 2'b01;
            o_ctrl_wb = 2'b00;
            o_ctrl_mem = 9'b100000100;  
            o_ctrl_ex = {7'b0000000,o_alu_control}; 
        end
        
        6'b000010:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b00;
            o_ctrl_mem = 9'b000; 
            o_ctrl_ex = {7'b0100000,o_alu_control};
        end
        
        6'b000011:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000; 
            o_ctrl_ex = {7'b1000000,o_alu_control};
        end
        
        default:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b00;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000000,o_alu_control};
        end
    endcase
end


alu_control
#(
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_ALU_OP(NB_ALU_OP),
    .NB_INSTRUCCION(NB_INSTRUCCION)
)
u_alu_control
(
    .i_inst_funcion(i_inst_funcion),
    .i_opcode(i_opcode),
    .i_alu_op(alu_op),
    .o_alu_code(o_alu_control)
);
endmodule
module control
#(  parameter NB_INSTRUCCION = 6,
    parameter NB_CTRL_WB = 2,
    parameter NB_CTRL_MEM = 9,
    parameter NB_CTRL_EX = 8,
    parameter NB_ALU_CONTROL = 4,
    parameter NB_ALU_OP = 2
)
(
    input [NB_INSTRUCCION-1:0] i_opcode,
    input [NB_INSTRUCCION-1:0] i_inst_funcion,
    output reg [NB_CTRL_WB-1:0] o_ctrl_wb,
    output reg [NB_CTRL_MEM-1:0] o_ctrl_mem,
    output reg [NB_CTRL_EX-1:0] o_ctrl_ex
);


reg [NB_ALU_OP-1:0] alu_op;
wire [NB_ALU_CONTROL-1:0] o_alu_control;

always @(*)
begin
    case(i_opcode)
        6'b000000:
        begin
            if(i_inst_funcion == 6'b001000)
            begin
                alu_op = 2'b10;
                o_ctrl_wb = 2'b00;
                o_ctrl_mem = 9'b000000000;
                o_ctrl_ex = {7'b0010000,o_alu_control};    
            end
            else if(i_inst_funcion == 6'b001001)
            begin
                alu_op = 2'b10;
                o_ctrl_wb = 2'b10;
                o_ctrl_mem = 9'b000000000;
                o_ctrl_ex = {7'b0001100,o_alu_control}; 
            end
            
            else
            begin
                alu_op = 2'b10;
                o_ctrl_wb = 2'b10;
                o_ctrl_mem = 9'b000000000;
                if((i_inst_funcion == 6'b000000) || (i_inst_funcion == 6'b000010) || (i_inst_funcion == 6'b000011))
                    o_ctrl_ex = {7'b0000110,o_alu_control};
                else    
                    o_ctrl_ex = {7'b0000100,o_alu_control};
            end
        end
        
        6'b100000:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000100010;
        end
        
        6'b100001:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000010010; 
        end
        
        6'b100011:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000000010;  
        end
        
        6'b100111:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000000010;  
        end
        
        6'b100100:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000101010;
        end
        
        6'b100101:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b11;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000011010; 
        end
        
        6'b101000:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b00;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b010000001;
        end
        
        6'b101001:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b00;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b001000001;
        end
        
        6'b101011:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b00;
            o_ctrl_ex = {7'b0000001,o_alu_control};
            o_ctrl_mem = 9'b000000001;
        end
        
        6'b001000:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b001100:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b001101:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b001110:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b001111:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b001010:
        begin
            alu_op = 2'b11;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000001,o_alu_control};  
        end
        
        6'b000100:
        begin
            alu_op = 2'b01;
            o_ctrl_wb = 2'b00;
            o_ctrl_mem = 9'b000000100;  
            o_ctrl_ex = {7'b0000000,o_alu_control}; 
        end
        
        6'b000101:
        begin
            alu_op = 2'b01;
            o_ctrl_wb = 2'b00;
            o_ctrl_mem = 9'b100000100;  
            o_ctrl_ex = {7'b0000000,o_alu_control}; 
        end
        
        6'b000010:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b00;
            o_ctrl_mem = 9'b000; 
            o_ctrl_ex = {7'b0100000,o_alu_control};
        end
        
        6'b000011:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b10;
            o_ctrl_mem = 9'b000; 
            o_ctrl_ex = {7'b1000000,o_alu_control};
        end
        
        default:
        begin
            alu_op = 2'b00;
            o_ctrl_wb = 2'b00;
            o_ctrl_mem = 9'b000000000;
            o_ctrl_ex = {7'b0000000,o_alu_control};
        end
    endcase
end


alu_control
#(
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_ALU_OP(NB_ALU_OP),
    .NB_INSTRUCCION(NB_INSTRUCCION)
)
u_alu_control
(
    .i_inst_funcion(i_inst_funcion),
    .i_opcode(i_opcode),
    .i_alu_op(alu_op),
    .o_alu_code(o_alu_control)
);
endmodule