data/full_repos/permissive/189193559/03/led_module.v
1: b"%Error: data/full_repos/permissive/189193559/03/led_module.v:22: Cannot find file containing module: 'pwm_modulator'\n    pwm_modulator mb(CLK, RST, lb_b, LEDS[0], CLK_FREQ);\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/189193559/03,data/full_repos/permissive/189193559/pwm_modulator\n             data/full_repos/permissive/189193559/03,data/full_repos/permissive/189193559/pwm_modulator.v\n             data/full_repos/permissive/189193559/03,data/full_repos/permissive/189193559/pwm_modulator.sv\n             pwm_modulator\n             pwm_modulator.v\n             pwm_modulator.sv\n             obj_dir/pwm_modulator\n             obj_dir/pwm_modulator.v\n             obj_dir/pwm_modulator.sv\n%Error: data/full_repos/permissive/189193559/03/led_module.v:23: Cannot find file containing module: 'pwm_modulator'\n    pwm_modulator mg(CLK, RST, lb_g, LEDS[1], CLK_FREQ);\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/189193559/03/led_module.v:24: Cannot find file containing module: 'pwm_modulator'\n    pwm_modulator mr(CLK, RST, lb_r, LEDS[2], CLK_FREQ);\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module led_module(CLK, RST, LEDS);
    input CLK, RST;

    output [2:0] LEDS;


    reg [31:0] cnt_clock;
    wire is_clk_max;
    

    reg [7:0] lb_r;
    reg [7:0] lb_g;
    reg [7:0] lb_b;
    

    parameter CLK_FREQ = 12000000;

    pwm_modulator mb(CLK, RST, lb_b, LEDS[0], CLK_FREQ);
    pwm_modulator mg(CLK, RST, lb_g, LEDS[1], CLK_FREQ);
    pwm_modulator mr(CLK, RST, lb_r, LEDS[2], CLK_FREQ);
    
    always @(posedge CLK) begin
        if(RST == 1) cnt_clock <= 0;
        else begin
            if(cnt_clock >= CLK_FREQ / 100 - 1) cnt_clock <= 0;
            else cnt_clock <= cnt_clock + 1;
        end
    end
    assign is_clk_max = (cnt_clock == CLK_FREQ / 100 - 1);


    always @(posedge CLK) begin
        if(RST == 1) begin
            lb_r <= 8'd0;
            lb_g <= 8'd85;
            lb_b <= 8'd171;
        end
        else begin
            if(is_clk_max) begin
                lb_r <= lb_r + 1;
                lb_g <= lb_g + 2;
                lb_b <= lb_b + 4;
            end
        end
    end
endmodule
module led_module(CLK, RST, LEDS);

    input CLK, RST;

    output [2:0] LEDS;


    reg [31:0] cnt_clock;
    wire is_clk_max;
    

    reg [7:0] lb_r;
    reg [7:0] lb_g;
    reg [7:0] lb_b;
    

    parameter CLK_FREQ = 12000000;

    pwm_modulator mb(CLK, RST, lb_b, LEDS[0], CLK_FREQ);
    pwm_modulator mg(CLK, RST, lb_g, LEDS[1], CLK_FREQ);
    pwm_modulator mr(CLK, RST, lb_r, LEDS[2], CLK_FREQ);
    
    always @(posedge CLK) begin
        if(RST == 1) cnt_clock <= 0;
        else begin
            if(cnt_clock >= CLK_FREQ / 100 - 1) cnt_clock <= 0;
            else cnt_clock <= cnt_clock + 1;
        end
    end
    assign is_clk_max = (cnt_clock == CLK_FREQ / 100 - 1);


    always @(posedge CLK) begin
        if(RST == 1) begin
            lb_r <= 8'd0;
            lb_g <= 8'd85;
            lb_b <= 8'd171;
        end
        else begin
            if(is_clk_max) begin
                lb_r <= lb_r + 1;
                lb_g <= lb_g + 2;
                lb_b <= lb_b + 4;
            end
        end
    end
endmodule