data/full_repos/permissive/156417892/hdl/InstructionDecode/SignExtend/SignExtend.v
 line:42: before: ":"
data/verilator_xmls/49c24f28-6271-467f-9ccf-4ccc7a7bbf9f.xml
module SignExtend(in,
                  out);
                  
    input [15:0] in;
    output [31:0] out;
    wire [15:0] sgn = (in[15]) ? 16'hFFFF:16'h0000;
    assign out = {sgn , in};
endmodule
module SignExtend(in,
                  out);

                  
    input [15:0] in;
    output [31:0] out;
    wire [15:0] sgn = (in[15]) ? 16'hFFFF:16'h0000;
    assign out = {sgn , in};
endmodule