data/full_repos/permissive/10379745/hw_de0/hard/mcpu.sv
 line:3: before: "IO"
1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/mcpu.sv:11: syntax error, unexpected ::, expecting IDENTIFIER\ndef::c_inst INST_INFO;  \n   ^~\n                                                                  : ... Perhaps 'def' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: Exiting due to 1 error(s)\n"
module mcpu(  input        CLK,
              input        RESET,
              if_io        IO);
              

parameter RAM_DEPTH = 13;
            
logic jtag_reset, any_reset;
assign any_reset = jtag_reset | RESET;

def::c_inst INST_INFO;
def::ctrl   CTRL_INFO;

if_hazard  if_hazard();
if_except  if_except();
if_cp0     if_cp0();
if_memory  if_memory();
if_debug   if_debug();

controller the_controller ( INST_INFO, CTRL_INFO );

hazard_unit the_hazard_unit( if_hazard );

datapath     the_datapath ( .CLK      ( CLK            ),
                                  

                            .INST_O   ( INST_INFO      ),
                            .CI       ( CTRL_INFO      ),


                            .HZRD     ( if_hazard      ),
                          

                            .CP0      ( if_cp0         ), 


                            .EXC      ( if_except      ),
                  

                            .MEM      ( if_memory      ),


                            .DEBUG    ( if_debug       ));

coprocessor0 #(RAM_DEPTH) cp0  ( .CLK      ( CLK            ),
                                 .RESET    ( any_reset      ),
                                 .CP0      ( if_cp0         ),
                                 .EXC      ( if_except      ),
                                 .IO       ( IO             ),
                                 .DEBUG    ( if_debug       ));


exceptions            excp_unit( .CLK      ( CLK            ),
                                 .RESET    ( any_reset      ),
                                 .EXC      ( if_except      ),
                                 .DEBUG    ( if_debug       ));


phy_mem #(RAM_DEPTH) phy_mem(CLK, any_reset, if_memory, IO);

jtag        jtag(CLK, RESET, jtag_reset, if_debug );

          
endmodule
module mcpu(  input        CLK,
              input        RESET,
              if_io        IO);

              

parameter RAM_DEPTH = 13;
            
logic jtag_reset, any_reset;
assign any_reset = jtag_reset | RESET;

def::c_inst INST_INFO;
def::ctrl   CTRL_INFO;

if_hazard  if_hazard();
if_except  if_except();
if_cp0     if_cp0();
if_memory  if_memory();
if_debug   if_debug();

controller the_controller ( INST_INFO, CTRL_INFO );

hazard_unit the_hazard_unit( if_hazard );

datapath     the_datapath ( .CLK      ( CLK            ),
                                  

                            .INST_O   ( INST_INFO      ),
                            .CI       ( CTRL_INFO      ),


                            .HZRD     ( if_hazard      ),
                          

                            .CP0      ( if_cp0         ), 


                            .EXC      ( if_except      ),
                  

                            .MEM      ( if_memory      ),


                            .DEBUG    ( if_debug       ));

coprocessor0 #(RAM_DEPTH) cp0  ( .CLK      ( CLK            ),
                                 .RESET    ( any_reset      ),
                                 .CP0      ( if_cp0         ),
                                 .EXC      ( if_except      ),
                                 .IO       ( IO             ),
                                 .DEBUG    ( if_debug       ));


exceptions            excp_unit( .CLK      ( CLK            ),
                                 .RESET    ( any_reset      ),
                                 .EXC      ( if_except      ),
                                 .DEBUG    ( if_debug       ));


phy_mem #(RAM_DEPTH) phy_mem(CLK, any_reset, if_memory, IO);

jtag        jtag(CLK, RESET, jtag_reset, if_debug );

          
endmodule