data/full_repos/permissive/135475029/lab_2/src/FullAdder.v
data/verilator_xmls/c8917342-4f61-4c30-9ce3-7067ff303136.xml
module FullAdder(
    input a, input b, input ci, output s, output co
    );
    
    assign s = a ^ b ^ ci;
    assign co = (a & b) | ((a ^ b) & ci);
endmodule
module FullAdder(
    input a, input b, input ci, output s, output co
    );

    
    assign s = a ^ b ^ ci;
    assign co = (a & b) | ((a ^ b) & ci);
endmodule