data/full_repos/permissive/156417892/hdl/Memory/DataCache/DataCache.v
None: at end of input
data/verilator_xmls/b14ad703-dc06-497e-b112-40e551b8be32.xml
module DataCache(clk,
                 rstn,
                 iaddr,
                 idata_write,
                 ohit,
                 omem_addr,
                 imem_in,
                 omem_write_data,
                 odata_read,
                 iSigMemRead,
                 iSigMemWrite);
   input clk, rstn;
   input [31:0] iaddr;
   input [31:0] idata_write;
   input [127:0] imem_in;
   input iSigMemRead, iSigMemWrite;
   output reg ohit;
   output reg [31:0] omem_addr;

   output reg [31:0] omem_write_data;
   output reg [31:0] odata_read;
   
   reg [154:0] content[3:0];
   reg [1:0] counter;

   integer i;

   always @(negedge rstn) begin
      omem_addr = 0;
      odata_read = 0;
      omem_write_data = 0;
      ohit = 1;
      counter = 0;
      for (i = 0; i < 4; i = i + 1) begin
         content[i] = 0;
      end
   end

   always @(posedge clk) begin
      if (iSigMemWrite) begin

        omem_write_data = idata_write;
        omem_addr = iaddr;

         if (content[iaddr[5:4]][0] == 1'b1 &&
            content[iaddr[5:4]][154:129] == iaddr[31:6]) begin
            case (iaddr[3:2])
               2'b00 : content[iaddr[5:4]][32:1]   = idata_write;
               2'b01 : content[iaddr[5:4]][64:33]  = idata_write;
               2'b10 : content[iaddr[5:4]][96:65]  = idata_write; 
               2'b11 : content[iaddr[5:4]][128:97] = idata_write;
            endcase
         end




      end

      if (iSigMemRead) begin
         if (content[iaddr[5:4]][0] == 1'b1 &&
            iaddr[31:6] == content[iaddr[5:4]][154:129]) begin
            case (iaddr[3:2])
               2'b00 : odata_read = content[iaddr[5:4]][32:1];
               2'b01 : odata_read = content[iaddr[5:4]][64:33];
               2'b10 : odata_read = content[iaddr[5:4]][96:65];
               2'b11 : odata_read = content[iaddr[5:4]][128:97];
            endcase
            ohit = 1;
         end else begin
            ohit = 0;
            if (counter == 3) begin
               content[iaddr[5:4]] = {iaddr[31:6],
                                      imem_in,
                                      1'b1};
               counter = 0;
               case (iaddr[3:2])
                  2'b00 : odata_read = imem_in[31:0];
                  2'b01 : odata_read = imem_in[63:32];
                  2'b10 : odata_read = imem_in[95:64];
                  2'b11 : odata_read = imem_in[127:96];
               endcase
               ohit = 1;
            end else begin
               counter = counter + 1;
            end
         end
      end
   end


endmodule
module DataCache(clk,
                 rstn,
                 iaddr,
                 idata_write,
                 ohit,
                 omem_addr,
                 imem_in,
                 omem_write_data,
                 odata_read,
                 iSigMemRead,
                 iSigMemWrite);

   input clk, rstn;
   input [31:0] iaddr;
   input [31:0] idata_write;
   input [127:0] imem_in;
   input iSigMemRead, iSigMemWrite;
   output reg ohit;
   output reg [31:0] omem_addr;

   output reg [31:0] omem_write_data;
   output reg [31:0] odata_read;
   
   reg [154:0] content[3:0];
   reg [1:0] counter;

   integer i;

   always @(negedge rstn) begin
      omem_addr = 0;
      odata_read = 0;
      omem_write_data = 0;
      ohit = 1;
      counter = 0;
      for (i = 0; i < 4; i = i + 1) begin
         content[i] = 0;
      end
   end

   always @(posedge clk) begin
      if (iSigMemWrite) begin

        omem_write_data = idata_write;
        omem_addr = iaddr;

         if (content[iaddr[5:4]][0] == 1'b1 &&
            content[iaddr[5:4]][154:129] == iaddr[31:6]) begin
            case (iaddr[3:2])
               2'b00 : content[iaddr[5:4]][32:1]   = idata_write;
               2'b01 : content[iaddr[5:4]][64:33]  = idata_write;
               2'b10 : content[iaddr[5:4]][96:65]  = idata_write; 
               2'b11 : content[iaddr[5:4]][128:97] = idata_write;
            endcase
         end




      end

      if (iSigMemRead) begin
         if (content[iaddr[5:4]][0] == 1'b1 &&
            iaddr[31:6] == content[iaddr[5:4]][154:129]) begin
            case (iaddr[3:2])
               2'b00 : odata_read = content[iaddr[5:4]][32:1];
               2'b01 : odata_read = content[iaddr[5:4]][64:33];
               2'b10 : odata_read = content[iaddr[5:4]][96:65];
               2'b11 : odata_read = content[iaddr[5:4]][128:97];
            endcase
            ohit = 1;
         end else begin
            ohit = 0;
            if (counter == 3) begin
               content[iaddr[5:4]] = {iaddr[31:6],
                                      imem_in,
                                      1'b1};
               counter = 0;
               case (iaddr[3:2])
                  2'b00 : odata_read = imem_in[31:0];
                  2'b01 : odata_read = imem_in[63:32];
                  2'b10 : odata_read = imem_in[95:64];
                  2'b11 : odata_read = imem_in[127:96];
               endcase
               ohit = 1;
            end else begin
               counter = counter + 1;
            end
         end
      end
   end


endmodule