data/full_repos/permissive/123304708/src/test.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/123304708/src/test.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #50; \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123304708/src/test.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/123304708/src/test.v:17: Unsupported: Ignoring delay on this delayed statement.\n    forever #50  \n            ^\n%Error: data/full_repos/permissive/123304708/src/test.v:23: Cannot find file containing module: \'mips\'\n  mips mips(clk, rst);\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/123304708/src,data/full_repos/permissive/123304708/mips\n             data/full_repos/permissive/123304708/src,data/full_repos/permissive/123304708/mips.v\n             data/full_repos/permissive/123304708/src,data/full_repos/permissive/123304708/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();
  `timescale 1ns / 1ns
  reg clk;
  reg rst;

  initial
  begin
    clk = 0;
    rst = 1;
    

    #50; 
    clk = ~clk;
    #50;
    rst = 0;
    
    forever #50  
    begin
      clk = ~clk;
    end
  end
  
  mips mips(clk, rst);
endmodule
module test();

  `timescale 1ns / 1ns
  reg clk;
  reg rst;

  initial
  begin
    clk = 0;
    rst = 1;
    

    #50; 
    clk = ~clk;
    #50;
    rst = 0;
    
    forever #50  
    begin
      clk = ~clk;
    end
  end
  
  mips mips(clk, rst);
endmodule