data/full_repos/permissive/127311496/src/v/CPU/TLB.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:16: Cannot find include file: TLBDefines.vh\n`include "TLBDefines.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/v/CPU,data/full_repos/permissive/127311496/TLBDefines.vh\n             data/full_repos/permissive/127311496/src/v/CPU,data/full_repos/permissive/127311496/TLBDefines.vh.v\n             data/full_repos/permissive/127311496/src/v/CPU,data/full_repos/permissive/127311496/TLBDefines.vh.sv\n             TLBDefines.vh\n             TLBDefines.vh.v\n             TLBDefines.vh.sv\n             obj_dir/TLBDefines.vh\n             obj_dir/TLBDefines.vh.v\n             obj_dir/TLBDefines.vh.sv\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:52: Define or directive not defined: \'`PageMask\'\n assign dataInHeader[`PageMask] = regPageMaskIn[28:13];\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInHeader[`PageMask] = regPageMaskIn[28:13];\n                              ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:53: Define or directive not defined: \'`VPN2\'\n assign dataInHeader[`VPN2] = regEntryHiIn[31:13];\n                     ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInHeader[`VPN2] = regEntryHiIn[31:13];\n                          ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:54: Define or directive not defined: \'`G\'\n assign dataInHeader[`G] = regEntryLo0In[0] & regEntryLo1In[0];\n                     ^~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:54: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInHeader[`G] = regEntryLo0In[0] & regEntryLo1In[0];\n                       ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:55: Define or directive not defined: \'`ASID\'\n assign dataInHeader[`ASID] = regEntryHiIn[7:0];\n                     ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:55: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInHeader[`ASID] = regEntryHiIn[7:0];\n                          ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:56: Define or directive not defined: \'`PFN1\'\n assign dataInEntry[`PFN1] = regEntryLo1In[29:6];\n                    ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInEntry[`PFN1] = regEntryLo1In[29:6];\n                         ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:57: Define or directive not defined: \'`C1\'\n assign dataInEntry[`C1] = regEntryLo1In[5:3];\n                    ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInEntry[`C1] = regEntryLo1In[5:3];\n                       ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:58: Define or directive not defined: \'`D1\'\n assign dataInEntry[`D1] = regEntryLo1In[2];\n                    ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:58: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInEntry[`D1] = regEntryLo1In[2];\n                       ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:59: Define or directive not defined: \'`V1\'\n assign dataInEntry[`V1] = regEntryLo1In[1];\n                    ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:59: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInEntry[`V1] = regEntryLo1In[1];\n                       ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:60: Define or directive not defined: \'`PFN0\'\n assign dataInEntry[`PFN0] = regEntryLo0In[29:6];\n                    ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:60: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInEntry[`PFN0] = regEntryLo0In[29:6];\n                         ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:61: Define or directive not defined: \'`C0\'\n assign dataInEntry[`C0] = regEntryLo0In[5:3];\n                    ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:61: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInEntry[`C0] = regEntryLo0In[5:3];\n                       ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:62: Define or directive not defined: \'`D0\'\n assign dataInEntry[`D0] = regEntryLo0In[2];\n                    ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:62: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInEntry[`D0] = regEntryLo0In[2];\n                       ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:63: Define or directive not defined: \'`V0\'\n assign dataInEntry[`V0] = regEntryLo0In[1];\n                    ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:63: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign dataInEntry[`V0] = regEntryLo0In[1];\n                       ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:65: Define or directive not defined: \'`PageMask\'\n assign regPageMaskOut = {3\'h0, dataOutHeader[`PageMask], 13\'h0};\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign regPageMaskOut = {3\'h0, dataOutHeader[`PageMask], 13\'h0};\n                                                       ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:66: Define or directive not defined: \'`VPN2\'\n assign regEntryHiOut = {dataOutHeader[`VPN2], 5\'h0, dataOutHeader[`ASID]};\n                                       ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:66: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign regEntryHiOut = {dataOutHeader[`VPN2], 5\'h0, dataOutHeader[`ASID]};\n                                            ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:66: Define or directive not defined: \'`ASID\'\n assign regEntryHiOut = {dataOutHeader[`VPN2], 5\'h0, dataOutHeader[`ASID]};\n                                                                   ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:67: Define or directive not defined: \'`PFN1\'\n assign regEntryLo1Out = {6\'h0, dataOutEntry[`PFN1], dataOutEntry[`C1], dataOutEntry[`D1], dataOutEntry[`V1], dataOutHeader[`G]};\n                                             ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:67: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign regEntryLo1Out = {6\'h0, dataOutEntry[`PFN1], dataOutEntry[`C1], dataOutEntry[`D1], dataOutEntry[`V1], dataOutHeader[`G]};\n                                                  ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:67: Define or directive not defined: \'`C1\'\n assign regEntryLo1Out = {6\'h0, dataOutEntry[`PFN1], dataOutEntry[`C1], dataOutEntry[`D1], dataOutEntry[`V1], dataOutHeader[`G]};\n                                                                  ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:67: Define or directive not defined: \'`D1\'\n assign regEntryLo1Out = {6\'h0, dataOutEntry[`PFN1], dataOutEntry[`C1], dataOutEntry[`D1], dataOutEntry[`V1], dataOutHeader[`G]};\n                                                                                     ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:67: Define or directive not defined: \'`V1\'\n assign regEntryLo1Out = {6\'h0, dataOutEntry[`PFN1], dataOutEntry[`C1], dataOutEntry[`D1], dataOutEntry[`V1], dataOutHeader[`G]};\n                                                                                                        ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:67: Define or directive not defined: \'`G\'\n assign regEntryLo1Out = {6\'h0, dataOutEntry[`PFN1], dataOutEntry[`C1], dataOutEntry[`D1], dataOutEntry[`V1], dataOutHeader[`G]};\n                                                                                                                            ^~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:68: Define or directive not defined: \'`PFN0\'\n assign regEntryLo0Out = {6\'h0, dataOutEntry[`PFN0], dataOutEntry[`C0], dataOutEntry[`D0], dataOutEntry[`V0], dataOutHeader[`G]};\n                                             ^~~~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:68: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign regEntryLo0Out = {6\'h0, dataOutEntry[`PFN0], dataOutEntry[`C0], dataOutEntry[`D0], dataOutEntry[`V0], dataOutHeader[`G]};\n                                                  ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:68: Define or directive not defined: \'`C0\'\n assign regEntryLo0Out = {6\'h0, dataOutEntry[`PFN0], dataOutEntry[`C0], dataOutEntry[`D0], dataOutEntry[`V0], dataOutHeader[`G]};\n                                                                  ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:68: Define or directive not defined: \'`D0\'\n assign regEntryLo0Out = {6\'h0, dataOutEntry[`PFN0], dataOutEntry[`C0], dataOutEntry[`D0], dataOutEntry[`V0], dataOutHeader[`G]};\n                                                                                     ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:68: Define or directive not defined: \'`V0\'\n assign regEntryLo0Out = {6\'h0, dataOutEntry[`PFN0], dataOutEntry[`C0], dataOutEntry[`D0], dataOutEntry[`V0], dataOutHeader[`G]};\n                                                                                                        ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:68: Define or directive not defined: \'`G\'\n assign regEntryLo0Out = {6\'h0, dataOutEntry[`PFN0], dataOutEntry[`C0], dataOutEntry[`D0], dataOutEntry[`V0], dataOutHeader[`G]};\n                                                                                                                            ^~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:83: Define or directive not defined: \'`C0\'\n assign cacheI = uncacheI? 3\'b010: entryDataI[`C0];\n                                              ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:83: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign cacheI = uncacheI? 3\'b010: entryDataI[`C0];\n                                                 ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:84: Define or directive not defined: \'`C0\'\n assign cacheD = uncacheD? 3\'b010: entryDataD[`C0];\n                                              ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:84: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign cacheD = uncacheD? 3\'b010: entryDataD[`C0];\n                                                 ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:85: Define or directive not defined: \'`V0\'\n assign invalidI = ~entryDataI[`V0] & ~unmapI;\n                               ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:85: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign invalidI = ~entryDataI[`V0] & ~unmapI;\n                                  ^\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:86: Define or directive not defined: \'`V0\'\n assign invalidD = ~entryDataD[`V0] & reqD_internal;\n                               ^~~\n%Error: data/full_repos/permissive/127311496/src/v/CPU/TLB.v:86: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign invalidD = ~entryDataD[`V0] & reqD_internal;\n                                  ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module TLB(input clk, input rst, input statusERL,

	input [31:0] vAddrI, output [31:0] pAddrI,
	output missI, output invalidI, output [2:0] cacheI,
	output IOAddrI,
	output [15:0] pageMaskI_out,

	input [31:0] vAddrD, input reqD, input writeD, output [31:0] pAddrD,
	output missD, output invalidD, output modifiedD, output [2:0] cacheD,
	output IOAddrD,

	output dupMatch,

	input [31:0] regEntryLo0In, output [31:0] regEntryLo0Out,
	input [31:0] regEntryLo1In, output [31:0] regEntryLo1Out,
	input [31:0] regEntryHiIn, output [31:0] regEntryHiOut,
	input [31:0] regPageMaskIn, output [31:0] regPageMaskOut,
	input [31:0] regIndexIn, output [31:0] regIndexOut,
	input [4:0] regWired, output [4:0] regRandom,
	input regWiredWrite, input [1:0] op
);

	wire [43:0] dataInHeader;
	wire [49:0] dataInEntry;
	wire [49:0] dataOutEntry;
	wire [4:0] indexInHeader;
	
	wire [31:0] matchI, matchD, probeMatch;

	wire [43:0] dataOutHeader;
	wire [5:0] entryIndexI, entryIndexD;
	wire [15:0] pageMaskI, pageMaskD;
	

	assign dataInHeader[`PageMask] = regPageMaskIn[28:13];
	assign dataInHeader[`VPN2] = regEntryHiIn[31:13];
	assign dataInHeader[`G] = regEntryLo0In[0] & regEntryLo1In[0];
	assign dataInHeader[`ASID] = regEntryHiIn[7:0];
	assign dataInEntry[`PFN1] = regEntryLo1In[29:6];
	assign dataInEntry[`C1] = regEntryLo1In[5:3];
	assign dataInEntry[`D1] = regEntryLo1In[2];
	assign dataInEntry[`V1] = regEntryLo1In[1];
	assign dataInEntry[`PFN0] = regEntryLo0In[29:6];
	assign dataInEntry[`C0] = regEntryLo0In[5:3];
	assign dataInEntry[`D0] = regEntryLo0In[2];
	assign dataInEntry[`V0] = regEntryLo0In[1];
	
	assign regPageMaskOut = {3'h0, dataOutHeader[`PageMask], 13'h0};
	assign regEntryHiOut = {dataOutHeader[`VPN2], 5'h0, dataOutHeader[`ASID]};
	assign regEntryLo1Out = {6'h0, dataOutEntry[`PFN1], dataOutEntry[`C1], dataOutEntry[`D1], dataOutEntry[`V1], dataOutHeader[`G]};
	assign regEntryLo0Out = {6'h0, dataOutEntry[`PFN0], dataOutEntry[`C0], dataOutEntry[`D0], dataOutEntry[`V0], dataOutHeader[`G]};

	assign indexInHeader = (op == 2'b11)? regRandom: regIndexIn[4:0];
	

	wire [24:0] entryDataI;
	wire [24:0] entryDataD;
	wire [31:0] pAddrI_internal, pAddrD_internal;
	wire unmapI = (vAddrI[31:30] == 2'b10) | (statusERL & vAddrI[31:29] == 3'b0);
	wire unmapD = (vAddrD[31:30] == 2'b10) | (statusERL & vAddrD[31:29] == 3'b0);
	wire reqD_internal = reqD & ~unmapD;
	wire uncacheI = (vAddrI[31:29] == 3'b101) | (vAddrI[31:29] == 3'b000 & statusERL);
	wire uncacheD = (vAddrD[31:29] == 3'b101) | (vAddrD[31:29] == 3'b000 & statusERL);
	assign missI = (~|matchI) & ~unmapI;
	assign missD = (~|matchD) & reqD_internal;
	assign cacheI = uncacheI? 3'b010: entryDataI[`C0];
	assign cacheD = uncacheD? 3'b010: entryDataD[`C0];
	assign invalidI = ~entryDataI[`V0] & ~unmapI;
	assign invalidD = ~entryDataD[`V0] & reqD_internal;
	assign modifiedD = ~entryDataD[`D0] & reqD_internal & writeD;
	assign IOAddrI = (vAddrI[31:29] == 3'b101);
	assign IOAddrD = (vAddrD[31:29] == 3'b101);
	wire [19:0] PFNI = entryDataI[`PFN0];
	wire [19:0] PFND = entryDataD[`PFN0];
	assign pAddrI_internal[31:28] = PFNI[19:16];
	assign pAddrI_internal[11:0] = vAddrI[11:0];
	assign pAddrI_internal[27:12] = (PFNI[15:0] & ~pageMaskI) | (vAddrI[27:12] & pageMaskI);
	assign pAddrD_internal[31:28] = PFND[19:16];
	assign pAddrD_internal[11:0] = vAddrD[11:0];
	assign pAddrD_internal[27:12] = (PFND[15:0] & ~pageMaskD) | (vAddrD[27:12] & pageMaskD);
	assign pAddrI = unmapI? {3'b0, vAddrI[28:0]}: pAddrI_internal;
	assign pAddrD = unmapD? {3'b0, vAddrD[28:0]}: pAddrD_internal;
	
	TLBEntry entryPool (.clk(clk), .we(op[1]),
		.indexA(entryIndexI), .entryA(entryDataI), .pageMaskA(pageMaskI),
		.indexB(entryIndexD), .entryB(entryDataD), .pageMaskB(pageMaskD),
		.indexC(regIndexIn[4:0]), .entryC(dataOutEntry), .headerC(dataOutHeader),
		.indexD(indexInHeader), .entryD(dataInEntry), .headerD(dataInHeader));
	
	wire [31:0] headerWE = op[1]? (1 << indexInHeader): 32'h0;
	wire [31:0] oddI, oddD;
	TLBHeader headers[31:0] (.clk(clk), .we(headerWE),
		.vAddrI(vAddrI), .matchI(matchI), .oddI(oddI),
		.vAddrD(vAddrD), .matchD(matchD), .oddD(oddD),
		.ASID(dataInHeader[`ASID]), .VPN2(dataInHeader[`VPN2]), .probeMatch(probeMatch),
		.G(dataInHeader[`G]), .pageMask(dataInHeader[`PageMask]));
	
	assign regIndexOut[31] = ~|probeMatch;
	assign regIndexOut[30:5] = 0;
	Encoder32 regIndexEncoder(.I(probeMatch), .O(regIndexOut[4:0]));
	Encoder32 entryIndexIEncoder(.I(matchI), .O(entryIndexI[4:0]));
	Encoder32 entryIndexDEncoder(.I(matchD), .O(entryIndexD[4:0]));
	assign entryIndexI[5] = |oddI;
	assign entryIndexD[5] = |oddD;
	
	TLBRNG randomGen(.clk(clk), .rst(regWiredWrite), .next(op == 2'b11),
		.regWired(regWired), .regRandom(regRandom));
	
	assign dupMatch = 1'b0;
	
	assign pageMaskI_out = unmapI? 16'hffff: pageMaskI;
	
endmodule
module TLB(input clk, input rst, input statusERL,

	input [31:0] vAddrI, output [31:0] pAddrI,
	output missI, output invalidI, output [2:0] cacheI,
	output IOAddrI,
	output [15:0] pageMaskI_out,

	input [31:0] vAddrD, input reqD, input writeD, output [31:0] pAddrD,
	output missD, output invalidD, output modifiedD, output [2:0] cacheD,
	output IOAddrD,

	output dupMatch,

	input [31:0] regEntryLo0In, output [31:0] regEntryLo0Out,
	input [31:0] regEntryLo1In, output [31:0] regEntryLo1Out,
	input [31:0] regEntryHiIn, output [31:0] regEntryHiOut,
	input [31:0] regPageMaskIn, output [31:0] regPageMaskOut,
	input [31:0] regIndexIn, output [31:0] regIndexOut,
	input [4:0] regWired, output [4:0] regRandom,
	input regWiredWrite, input [1:0] op
);


	wire [43:0] dataInHeader;
	wire [49:0] dataInEntry;
	wire [49:0] dataOutEntry;
	wire [4:0] indexInHeader;
	
	wire [31:0] matchI, matchD, probeMatch;

	wire [43:0] dataOutHeader;
	wire [5:0] entryIndexI, entryIndexD;
	wire [15:0] pageMaskI, pageMaskD;
	

	assign dataInHeader[`PageMask] = regPageMaskIn[28:13];
	assign dataInHeader[`VPN2] = regEntryHiIn[31:13];
	assign dataInHeader[`G] = regEntryLo0In[0] & regEntryLo1In[0];
	assign dataInHeader[`ASID] = regEntryHiIn[7:0];
	assign dataInEntry[`PFN1] = regEntryLo1In[29:6];
	assign dataInEntry[`C1] = regEntryLo1In[5:3];
	assign dataInEntry[`D1] = regEntryLo1In[2];
	assign dataInEntry[`V1] = regEntryLo1In[1];
	assign dataInEntry[`PFN0] = regEntryLo0In[29:6];
	assign dataInEntry[`C0] = regEntryLo0In[5:3];
	assign dataInEntry[`D0] = regEntryLo0In[2];
	assign dataInEntry[`V0] = regEntryLo0In[1];
	
	assign regPageMaskOut = {3'h0, dataOutHeader[`PageMask], 13'h0};
	assign regEntryHiOut = {dataOutHeader[`VPN2], 5'h0, dataOutHeader[`ASID]};
	assign regEntryLo1Out = {6'h0, dataOutEntry[`PFN1], dataOutEntry[`C1], dataOutEntry[`D1], dataOutEntry[`V1], dataOutHeader[`G]};
	assign regEntryLo0Out = {6'h0, dataOutEntry[`PFN0], dataOutEntry[`C0], dataOutEntry[`D0], dataOutEntry[`V0], dataOutHeader[`G]};

	assign indexInHeader = (op == 2'b11)? regRandom: regIndexIn[4:0];
	

	wire [24:0] entryDataI;
	wire [24:0] entryDataD;
	wire [31:0] pAddrI_internal, pAddrD_internal;
	wire unmapI = (vAddrI[31:30] == 2'b10) | (statusERL & vAddrI[31:29] == 3'b0);
	wire unmapD = (vAddrD[31:30] == 2'b10) | (statusERL & vAddrD[31:29] == 3'b0);
	wire reqD_internal = reqD & ~unmapD;
	wire uncacheI = (vAddrI[31:29] == 3'b101) | (vAddrI[31:29] == 3'b000 & statusERL);
	wire uncacheD = (vAddrD[31:29] == 3'b101) | (vAddrD[31:29] == 3'b000 & statusERL);
	assign missI = (~|matchI) & ~unmapI;
	assign missD = (~|matchD) & reqD_internal;
	assign cacheI = uncacheI? 3'b010: entryDataI[`C0];
	assign cacheD = uncacheD? 3'b010: entryDataD[`C0];
	assign invalidI = ~entryDataI[`V0] & ~unmapI;
	assign invalidD = ~entryDataD[`V0] & reqD_internal;
	assign modifiedD = ~entryDataD[`D0] & reqD_internal & writeD;
	assign IOAddrI = (vAddrI[31:29] == 3'b101);
	assign IOAddrD = (vAddrD[31:29] == 3'b101);
	wire [19:0] PFNI = entryDataI[`PFN0];
	wire [19:0] PFND = entryDataD[`PFN0];
	assign pAddrI_internal[31:28] = PFNI[19:16];
	assign pAddrI_internal[11:0] = vAddrI[11:0];
	assign pAddrI_internal[27:12] = (PFNI[15:0] & ~pageMaskI) | (vAddrI[27:12] & pageMaskI);
	assign pAddrD_internal[31:28] = PFND[19:16];
	assign pAddrD_internal[11:0] = vAddrD[11:0];
	assign pAddrD_internal[27:12] = (PFND[15:0] & ~pageMaskD) | (vAddrD[27:12] & pageMaskD);
	assign pAddrI = unmapI? {3'b0, vAddrI[28:0]}: pAddrI_internal;
	assign pAddrD = unmapD? {3'b0, vAddrD[28:0]}: pAddrD_internal;
	
	TLBEntry entryPool (.clk(clk), .we(op[1]),
		.indexA(entryIndexI), .entryA(entryDataI), .pageMaskA(pageMaskI),
		.indexB(entryIndexD), .entryB(entryDataD), .pageMaskB(pageMaskD),
		.indexC(regIndexIn[4:0]), .entryC(dataOutEntry), .headerC(dataOutHeader),
		.indexD(indexInHeader), .entryD(dataInEntry), .headerD(dataInHeader));
	
	wire [31:0] headerWE = op[1]? (1 << indexInHeader): 32'h0;
	wire [31:0] oddI, oddD;
	TLBHeader headers[31:0] (.clk(clk), .we(headerWE),
		.vAddrI(vAddrI), .matchI(matchI), .oddI(oddI),
		.vAddrD(vAddrD), .matchD(matchD), .oddD(oddD),
		.ASID(dataInHeader[`ASID]), .VPN2(dataInHeader[`VPN2]), .probeMatch(probeMatch),
		.G(dataInHeader[`G]), .pageMask(dataInHeader[`PageMask]));
	
	assign regIndexOut[31] = ~|probeMatch;
	assign regIndexOut[30:5] = 0;
	Encoder32 regIndexEncoder(.I(probeMatch), .O(regIndexOut[4:0]));
	Encoder32 entryIndexIEncoder(.I(matchI), .O(entryIndexI[4:0]));
	Encoder32 entryIndexDEncoder(.I(matchD), .O(entryIndexD[4:0]));
	assign entryIndexI[5] = |oddI;
	assign entryIndexD[5] = |oddD;
	
	TLBRNG randomGen(.clk(clk), .rst(regWiredWrite), .next(op == 2'b11),
		.regWired(regWired), .regRandom(regRandom));
	
	assign dupMatch = 1'b0;
	
	assign pageMaskI_out = unmapI? 16'hffff: pageMaskI;
	
endmodule