data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/or1200_top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/or1200_top.v:3: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes,data/full_repos/permissive/19905110/or1200_defines.v\n             data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes,data/full_repos/permissive/19905110/or1200_defines.v.v\n             data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes,data/full_repos/permissive/19905110/or1200_defines.v.sv\n             or1200_defines.v\n             or1200_defines.v.v\n             or1200_defines.v.sv\n             obj_dir/or1200_defines.v\n             obj_dir/or1200_defines.v.v\n             obj_dir/or1200_defines.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/or1200_top.v:43: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\nparameter dw = `OR1200_OPERAND_WIDTH;\n               ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/or1200_top.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter dw = `OR1200_OPERAND_WIDTH;\n                                    ^\n%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/or1200_top.v:44: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\nparameter aw = `OR1200_OPERAND_WIDTH;\n               ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/or1200_top.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter aw = `OR1200_OPERAND_WIDTH;\n                                    ^\n%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/or1200_top.v:45: Define or directive not defined: \'`OR1200_PIC_INTS\'\nparameter ppic_ints = `OR1200_PIC_INTS;\n                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/or1200_top.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter ppic_ints = `OR1200_PIC_INTS;\n                                      ^\n%Error: Exiting due to 7 error(s)\n'
module or1200_top(

	clk_i, rst_i, pic_ints_i, clmode_i,


	iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
	iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
`ifdef OR1200_WB_CAB
	iwb_cab_o,
`endif
`ifdef OR1200_WB_B3
	iwb_cti_o, iwb_bte_o,
`endif

	dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
	dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
`ifdef OR1200_WB_CAB
	dwb_cab_o,
`endif
`ifdef OR1200_WB_B3
	dwb_cti_o, dwb_bte_o,
`endif


	dbg_stall_i, dbg_ewt_i,	dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
	dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
	
`ifdef OR1200_BIST

	mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif

	pm_cpustall_i,
	pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, 
	pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o

);

parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
parameter ppic_ints = `OR1200_PIC_INTS;








input			clk_i;
input			rst_i;
input	[1:0]		clmode_i;
input	[ppic_ints-1:0]	pic_ints_i;




input			iwb_clk_i;
input			iwb_rst_i;
input			iwb_ack_i;
input			iwb_err_i;
input			iwb_rty_i;
input	[dw-1:0]	iwb_dat_i;
output			iwb_cyc_o;
output	[aw-1:0]	iwb_adr_o;
output			iwb_stb_o;
output			iwb_we_o;
output	[3:0]		iwb_sel_o;
output	[dw-1:0]	iwb_dat_o;
`ifdef OR1200_WB_CAB
output			iwb_cab_o;
`endif
`ifdef OR1200_WB_B3
output	[2:0]		iwb_cti_o;
output	[1:0]		iwb_bte_o;
`endif




input			dwb_clk_i;
input			dwb_rst_i;
input			dwb_ack_i;
input			dwb_err_i;
input			dwb_rty_i;
input	[dw-1:0]	dwb_dat_i;
output			dwb_cyc_o;
output	[aw-1:0]	dwb_adr_o;
output			dwb_stb_o;
output			dwb_we_o;
output	[3:0]		dwb_sel_o;
output	[dw-1:0]	dwb_dat_o;
`ifdef OR1200_WB_CAB
output			dwb_cab_o;
`endif
`ifdef OR1200_WB_B3
output	[2:0]		dwb_cti_o;
output	[1:0]		dwb_bte_o;
`endif




input			dbg_stall_i;
input			dbg_ewt_i;
output	[3:0]		dbg_lss_o;
output	[1:0]		dbg_is_o;
output	[10:0]		dbg_wp_o;
output			dbg_bp_o;
input			dbg_stb_i;
input			dbg_we_i;
input	[aw-1:0]	dbg_adr_i;
input	[dw-1:0]	dbg_dat_i;
output	[dw-1:0]	dbg_dat_o;
output			dbg_ack_o;

`ifdef OR1200_BIST



input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif




input			pm_cpustall_i;
output	[3:0]		pm_clksd_o;
output			pm_dc_gate_o;
output			pm_ic_gate_o;
output			pm_dmmu_gate_o;
output			pm_immu_gate_o;
output			pm_tt_gate_o;
output			pm_cpu_gate_o;
output			pm_wakeup_o;
output			pm_lvolt_o;


endmodule
module or1200_top(

	clk_i, rst_i, pic_ints_i, clmode_i,


	iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
	iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
`ifdef OR1200_WB_CAB
	iwb_cab_o,
`endif
`ifdef OR1200_WB_B3
	iwb_cti_o, iwb_bte_o,
`endif

	dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
	dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
`ifdef OR1200_WB_CAB
	dwb_cab_o,
`endif
`ifdef OR1200_WB_B3
	dwb_cti_o, dwb_bte_o,
`endif


	dbg_stall_i, dbg_ewt_i,	dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
	dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
	
`ifdef OR1200_BIST

	mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif

	pm_cpustall_i,
	pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, 
	pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o

);


parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
parameter ppic_ints = `OR1200_PIC_INTS;








input			clk_i;
input			rst_i;
input	[1:0]		clmode_i;
input	[ppic_ints-1:0]	pic_ints_i;




input			iwb_clk_i;
input			iwb_rst_i;
input			iwb_ack_i;
input			iwb_err_i;
input			iwb_rty_i;
input	[dw-1:0]	iwb_dat_i;
output			iwb_cyc_o;
output	[aw-1:0]	iwb_adr_o;
output			iwb_stb_o;
output			iwb_we_o;
output	[3:0]		iwb_sel_o;
output	[dw-1:0]	iwb_dat_o;
`ifdef OR1200_WB_CAB
output			iwb_cab_o;
`endif
`ifdef OR1200_WB_B3
output	[2:0]		iwb_cti_o;
output	[1:0]		iwb_bte_o;
`endif




input			dwb_clk_i;
input			dwb_rst_i;
input			dwb_ack_i;
input			dwb_err_i;
input			dwb_rty_i;
input	[dw-1:0]	dwb_dat_i;
output			dwb_cyc_o;
output	[aw-1:0]	dwb_adr_o;
output			dwb_stb_o;
output			dwb_we_o;
output	[3:0]		dwb_sel_o;
output	[dw-1:0]	dwb_dat_o;
`ifdef OR1200_WB_CAB
output			dwb_cab_o;
`endif
`ifdef OR1200_WB_B3
output	[2:0]		dwb_cti_o;
output	[1:0]		dwb_bte_o;
`endif




input			dbg_stall_i;
input			dbg_ewt_i;
output	[3:0]		dbg_lss_o;
output	[1:0]		dbg_is_o;
output	[10:0]		dbg_wp_o;
output			dbg_bp_o;
input			dbg_stb_i;
input			dbg_we_i;
input	[aw-1:0]	dbg_adr_i;
input	[dw-1:0]	dbg_dat_i;
output	[dw-1:0]	dbg_dat_o;
output			dbg_ack_o;

`ifdef OR1200_BIST



input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif




input			pm_cpustall_i;
output	[3:0]		pm_clksd_o;
output			pm_dc_gate_o;
output			pm_ic_gate_o;
output			pm_dmmu_gate_o;
output			pm_immu_gate_o;
output			pm_tt_gate_o;
output			pm_cpu_gate_o;
output			pm_wakeup_o;
output			pm_lvolt_o;


endmodule