data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop_TB.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #5 samplePoint_tb = ~samplePoint_tb;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #1 samplePointFD_tb = ~samplePointFD_tb;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n   #5 canRX_tb = messageTest[124];\n   ^\n%Error: data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/frameMakerTop_TB.v:11: Cannot find file containing module: \'frameMakerTop\'\n frameMakerTop dut(samplePoint_tb, samplePointFD_tb, canRX_tb, isError_tb, isStuff_tb, endOverload_tb, BS_onoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, IDE_tb, EDL_tb, BRS_tb, isRemote_tb, size_tb, frame_tb, frameReady_tb, isStart_tb);\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop,data/full_repos/permissive/107735152/frameMakerTop\n             data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop,data/full_repos/permissive/107735152/frameMakerTop.v\n             data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop,data/full_repos/permissive/107735152/frameMakerTop.sv\n             frameMakerTop\n             frameMakerTop.v\n             frameMakerTop.sv\n             obj_dir/frameMakerTop\n             obj_dir/frameMakerTop.v\n             obj_dir/frameMakerTop.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module frameMakerTop_TB();

	reg	[124:0] messageTest;
	
	reg samplePoint_tb, samplePointFD_tb, canRX_tb, isError_tb, isStuff_tb;
	wire endOverload_tb, BS_onoff_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, IDE_tb, EDL_tb, BRS_tb, isRemote_tb, frameReady_tb, isStart_tb;
	wire [1:0] CRCtype_tb;
	wire [9:0] size_tb;
	wire [150:0] frame_tb;
	
	frameMakerTop dut(samplePoint_tb, samplePointFD_tb, canRX_tb, isError_tb, isStuff_tb, endOverload_tb, BS_onoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, IDE_tb, EDL_tb, BRS_tb, isRemote_tb, size_tb, frame_tb, frameReady_tb, isStart_tb);
	




	initial
	begin
		$stop;
		canRX_tb = 1'b1;
		samplePoint_tb = 1'b1;
		samplePointFD_tb = 1'b0;
		isStuff_tb = 1'b0;
		isError_tb = 1'b0;



		


		

		messageTest = 125'b11011001001001000000110101010010101010101010111111111111101100100100110000000101010101010101111111111100000011111111111110111;
		



	end
	
	always
		begin
		#5 samplePoint_tb = ~samplePoint_tb;
		#1 samplePointFD_tb = ~samplePointFD_tb;
		end
	 
	always @(posedge samplePoint_tb)
	begin
		if(messageTest != 0)
		begin
			#5 canRX_tb = messageTest[124];
			messageTest <= messageTest << 1;

		end
		else
		begin
			$stop;
		end
	
	end
		
endmodule
module frameMakerTop_TB();


	reg	[124:0] messageTest;
	
	reg samplePoint_tb, samplePointFD_tb, canRX_tb, isError_tb, isStuff_tb;
	wire endOverload_tb, BS_onoff_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, IDE_tb, EDL_tb, BRS_tb, isRemote_tb, frameReady_tb, isStart_tb;
	wire [1:0] CRCtype_tb;
	wire [9:0] size_tb;
	wire [150:0] frame_tb;
	
	frameMakerTop dut(samplePoint_tb, samplePointFD_tb, canRX_tb, isError_tb, isStuff_tb, endOverload_tb, BS_onoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, IDE_tb, EDL_tb, BRS_tb, isRemote_tb, size_tb, frame_tb, frameReady_tb, isStart_tb);
	




	initial
	begin
		$stop;
		canRX_tb = 1'b1;
		samplePoint_tb = 1'b1;
		samplePointFD_tb = 1'b0;
		isStuff_tb = 1'b0;
		isError_tb = 1'b0;



		


		

		messageTest = 125'b11011001001001000000110101010010101010101010111111111111101100100100110000000101010101010101111111111100000011111111111110111;
		



	end
	
	always
		begin
		#5 samplePoint_tb = ~samplePoint_tb;
		#1 samplePointFD_tb = ~samplePointFD_tb;
		end
	 
	always @(posedge samplePoint_tb)
	begin
		if(messageTest != 0)
		begin
			#5 canRX_tb = messageTest[124];
			messageTest <= messageTest << 1;

		end
		else
		begin
			$stop;
		end
	
	end
		
endmodule