data/full_repos/permissive/100331186/lib/cmos_tech.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:45: Unsupported: Ignoring delay on this delayed statement.\n # (tpmin:tptyp:tpmax) Q <= D;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:56: Unsupported: Ignoring delay on this delayed statement.\n  # (tpmin:tptyp:tpmax) Q <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:58: Unsupported: Ignoring delay on this delayed statement.\n  # (tpmin:tptyp:tpmax) Q <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/lib/cmos_tech.v:60: Unsupported: Ignoring delay on this delayed statement.\n  # (tpmin:tptyp:tpmax) Q <= D;\n  ^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/lib/cmos_tech.v:11: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                          : ... Top module \'BUF\'\nmodule BUF(A, Y);\n       ^~~\n                                                                          : ... Top module \'NOT\'\nmodule NOT(A, Y);\n       ^~~\n                                                                          : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n       ^~~~\n                                                                          : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n       ^~~\n                                                                          : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n       ^~~\n                                                                          : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R);\n       ^~~~~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DFF(C, D, Q);
parameter tpmin = 1.5;
parameter tptyp = 7.7;
parameter tpmax = 10.5;

input C, D;
output reg Q;
always @(posedge C)
	# (tpmin:tptyp:tpmax) Q <= D;
endmodule
module DFF(C, D, Q);

parameter tpmin = 1.5;
parameter tptyp = 7.7;
parameter tpmax = 10.5;

input C, D;
output reg Q;
always @(posedge C)
	# (tpmin:tptyp:tpmax) Q <= D;
endmodule