data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/src/rw_trigger.v
data/verilator_xmls/0bd73e5d-73b1-43f4-9fd4-b96fecd12eef.xml
module rw_trigger
(
    input wire reset,
    input wire clk,
    input wire ior,
    input wire iow,
    output reg w,
    output reg r
);


always @(posedge clk)
begin
    if(reset)
    begin
        r <= 1'b1;
        w <= 1'b1;
    end
    else
    begin
        if (ior == 1'b0 && iow == 1'b1)
        begin
            r <= 1'b0;
            w <= 1'b1;
        end
        else if (ior == 1'b1 && iow == 1'b0)
        begin
            r <= 1'b1;
            w <= 1'b0;
        end
        else
        begin
            r <= 1'b1;
            w <= 1'b1;
        end
    end
end

endmodule
module rw_trigger
(
    input wire reset,
    input wire clk,
    input wire ior,
    input wire iow,
    output reg w,
    output reg r
);



always @(posedge clk)
begin
    if(reset)
    begin
        r <= 1'b1;
        w <= 1'b1;
    end
    else
    begin
        if (ior == 1'b0 && iow == 1'b1)
        begin
            r <= 1'b0;
            w <= 1'b1;
        end
        else if (ior == 1'b1 && iow == 1'b0)
        begin
            r <= 1'b1;
            w <= 1'b0;
        end
        else
        begin
            r <= 1'b1;
            w <= 1'b1;
        end
    end
end

endmodule