data/full_repos/permissive/206169433/pipeline/pc.v
data/verilator_xmls/85f86984-5dc6-4ce4-a392-30cfc465e4fb.xml
module pc(clk, pc_in, pc_out, stall);
    input clk, stall;
    input [31:0] pc_in;
    output [31:0] pc_out;
    reg [31:0] pc_out;
    initial begin
        pc_out <= 32'b11111111111111111111111111111100;
    end
    always @(posedge clk) begin
        if (!stall)
            pc_out <= pc_in;
    end
endmodule
module pc(clk, pc_in, pc_out, stall);

    input clk, stall;
    input [31:0] pc_in;
    output [31:0] pc_out;
    reg [31:0] pc_out;
    initial begin
        pc_out <= 32'b11111111111111111111111111111100;
    end
    always @(posedge clk) begin
        if (!stall)
            pc_out <= pc_in;
    end
endmodule