data/full_repos/permissive/104784866/SBox/Verilog/src/MDimMux.v
data/verilator_xmls/03985fbd-b68e-487c-96f5-73f274a65ed6.xml
module MDimMux#(

		parameter DIMENSION = 4,

		parameter CH_IN_WIDTH = 8,

		parameter DIMENSION_WIDTH = 2,

		parameter CH_IN_WIDTH_WIDTH = 3
	) (

		mode,
		c_clk,
		c_bus,
		c_dimension,


		ch_in,
		ch_out
	);


	parameter CONFIG_WORD_WIDTH = DIMENSION*CH_IN_WIDTH_WIDTH;


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	input [CH_IN_WIDTH-1:0] ch_in;
	output ch_out;


	reg [CONFIG_WORD_WIDTH-1:0] configReg;

	wire [CH_IN_WIDTH-1:0] muxWires;


	always @(posedge c_clk) begin
		if(mode) begin
			`CONFIGREG_MUX_VALUE = `C_BUS_MUX_VALUE;
		end
	end


	genvar i;
	generate
		for(i = 0; i < CH_IN_WIDTH; i = i+1) begin : muxWiresGen
			assign muxWires[i] = (i == ((`CONFIGREG_MUX_VALUE >> (c_dimension * CH_IN_WIDTH_WIDTH)) & CH_IN_WIDTH-1))? ch_in[i] : 1'b0;
		end
	endgenerate


	assign ch_out = (| muxWires);

endmodule
module MDimMux#(

		parameter DIMENSION = 4,

		parameter CH_IN_WIDTH = 8,

		parameter DIMENSION_WIDTH = 2,

		parameter CH_IN_WIDTH_WIDTH = 3
	) (

		mode,
		c_clk,
		c_bus,
		c_dimension,


		ch_in,
		ch_out
	);



	parameter CONFIG_WORD_WIDTH = DIMENSION*CH_IN_WIDTH_WIDTH;


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	input [CH_IN_WIDTH-1:0] ch_in;
	output ch_out;


	reg [CONFIG_WORD_WIDTH-1:0] configReg;

	wire [CH_IN_WIDTH-1:0] muxWires;


	always @(posedge c_clk) begin
		if(mode) begin
			`CONFIGREG_MUX_VALUE = `C_BUS_MUX_VALUE;
		end
	end


	genvar i;
	generate
		for(i = 0; i < CH_IN_WIDTH; i = i+1) begin : muxWiresGen
			assign muxWires[i] = (i == ((`CONFIGREG_MUX_VALUE >> (c_dimension * CH_IN_WIDTH_WIDTH)) & CH_IN_WIDTH-1))? ch_in[i] : 1'b0;
		end
	endgenerate


	assign ch_out = (| muxWires);

endmodule