data/full_repos/permissive/172054326/rtl/trng_reg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:46: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  ctl_state <= IDLE;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:50: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'RGEN\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n        IDLE : ctl_state  <= (gen)? RGEN : IDLE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:50: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n        IDLE : ctl_state  <= (gen)? RGEN : IDLE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:51: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROC\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n        RGEN : ctl_state  <= PROC;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:52: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  PROC : ctl_state  <= (trn_gen_done)? IDLE: PROC;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:52: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'PROC\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  PROC : ctl_state  <= (trn_gen_done)? IDLE: PROC;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:54: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n            ctl_state <= IDLE;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:49: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  case (ctl_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:49: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'RGEN\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  case (ctl_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:49: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROC\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  case (ctl_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:59: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n     case (ctl_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:59: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'RGEN\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n     case (ctl_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:59: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROC\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n     case (ctl_state)\n     ^~~~\n%Error: data/full_repos/permissive/172054326/rtl/trng_reg.v:87: Cannot find file containing module: \'es_trng\'\n       (* dont_touch = "true" *) es_trng trng_ins(\n                                 ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172054326/rtl,data/full_repos/permissive/172054326/es_trng\n             data/full_repos/permissive/172054326/rtl,data/full_repos/permissive/172054326/es_trng.v\n             data/full_repos/permissive/172054326/rtl,data/full_repos/permissive/172054326/es_trng.sv\n             es_trng\n             es_trng.v\n             es_trng.sv\n             obj_dir/es_trng\n             obj_dir/es_trng.v\n             obj_dir/es_trng.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n'
module trng_reg (
    clk,
    rst,
    gen,
    rdy,
    rdn );
parameter W  = 32;
parameter O  =  3;
parameter RI = 32;

localparam WI = W/RI; 
localparam b = $clog2(WI)+1;

input           clk, rst;
input           gen;		
output          rdy;
output [W-1:0]  rdn;


wire   [W-1:0] rdn;
reg    rdy;
reg    trn_gen;
reg    trn_gen_done;




localparam IDLE    = 2'b00;
localparam RGEN    = 2'b01;
localparam PROC    = 2'b10;

reg [3:0] ctl_state;
always @(posedge clk)
	if (rst) begin
		ctl_state <= IDLE;
		end
	else
		case (ctl_state)
        IDLE : ctl_state  <= (gen)? RGEN : IDLE;
        RGEN : ctl_state  <= PROC;
		PROC : ctl_state  <= (trn_gen_done)? IDLE: PROC;
        default : begin
            ctl_state <= IDLE;
        end
         endcase
         
always @(ctl_state)
     case (ctl_state)
     IDLE : begin          
         rdy        <= 1'b0;
         trn_gen    <= 1'b0;
         end
     RGEN : begin         
         rdy        <= 1'b1;
         trn_gen    <= 1'b1;
         end
     PROC: begin      
         rdy        <= 1'b0;
         trn_gen    <= 1'b1;
         end
     default : begin
         rdy        <= 1'b0;
         trn_gen    <= 1'b0;
         end
      endcase

wire [RI-1: 0]   trn_rnb; 
wire [RI-1: 0]   trn_val;
wire [RI-1: 0]   fil_val;
wire [RI-1: 0]   fil_out;

genvar i;
generate
   for (i=0; i < RI; i=i+1)
   begin: filtered_es_trng
       (* dont_touch = "true" *) es_trng trng_ins(
       .rst(rst),
       .clk(clk),
       .gen(trn_gen),
       .rnb(trn_rnb[i]),
       .val(trn_val[i]) 
       );

       parity_filter #(.ORD(O)) filt_ins (.rst(rst), .clk(clk), .trn_val(trn_val[i]), .trn_rnb(trn_rnb[i]), .val(fil_val[i]), .rnb(fil_out[i]));
   end
endgenerate

integer j;
reg [RI-1:0] trn_bit;
always @(posedge clk) begin
    if  (rst)               	trn_bit 	<= {RI{1'b0}};
    else begin
        for (j=0; j<RI; j=j+1)
            trn_bit[j]	<= (fil_val[j])?fil_out[j]:trn_bit[j];		
	end    
end

reg [RI-1:0] RI_bits_val;
wire all_val = &(RI_bits_val);
always @(posedge clk) begin
    if  (rst)          RI_bits_val	<= {RI{1'b0}};
    else if (all_val)  RI_bits_val	<= {RI{1'b0}};
    else		       RI_bits_val	<= RI_bits_val | fil_val;
end

wire new_value;
reg [W-1:0] trn_reg;

generate
      if (W==RI) begin: condgen1
          always @(posedge clk) begin
              if      (rst)       trn_reg <= {W{1'b0}};    
              else if (all_val)   trn_reg <= trn_bit;    
          end
          assign new_value = all_val;
      end else begin:condgen2
          reg [b-1:0]  RIbits_cnt;
          always @(posedge clk) begin
              if      (rst)       trn_reg <= {W{1'b0}};    
              else if (all_val)   trn_reg <= {trn_reg[W-RI-1:0], trn_bit};    
          end
          
          always @(posedge clk) begin
              if      (rst)       RIbits_cnt <= {b{1'b0}};    
              else if (all_val)   RIbits_cnt <= RIbits_cnt + 1'b1;    
          end
      
          assign new_value = all_val && (RIbits_cnt == WI-1);
      end
   endgenerate

always @(posedge clk) begin
    if  (rst)        trn_gen_done <= 1'b0;
    else if (new_value)  trn_gen_done <=1'b1;
    else                 trn_gen_done <= 1'b0;    
end

assign rdn = trn_reg;

endmodule
module trng_reg (
    clk,
    rst,
    gen,
    rdy,
    rdn );

parameter W  = 32;
parameter O  =  3;
parameter RI = 32;

localparam WI = W/RI; 
localparam b = $clog2(WI)+1;

input           clk, rst;
input           gen;		
output          rdy;
output [W-1:0]  rdn;


wire   [W-1:0] rdn;
reg    rdy;
reg    trn_gen;
reg    trn_gen_done;




localparam IDLE    = 2'b00;
localparam RGEN    = 2'b01;
localparam PROC    = 2'b10;

reg [3:0] ctl_state;
always @(posedge clk)
	if (rst) begin
		ctl_state <= IDLE;
		end
	else
		case (ctl_state)
        IDLE : ctl_state  <= (gen)? RGEN : IDLE;
        RGEN : ctl_state  <= PROC;
		PROC : ctl_state  <= (trn_gen_done)? IDLE: PROC;
        default : begin
            ctl_state <= IDLE;
        end
         endcase
         
always @(ctl_state)
     case (ctl_state)
     IDLE : begin          
         rdy        <= 1'b0;
         trn_gen    <= 1'b0;
         end
     RGEN : begin         
         rdy        <= 1'b1;
         trn_gen    <= 1'b1;
         end
     PROC: begin      
         rdy        <= 1'b0;
         trn_gen    <= 1'b1;
         end
     default : begin
         rdy        <= 1'b0;
         trn_gen    <= 1'b0;
         end
      endcase

wire [RI-1: 0]   trn_rnb; 
wire [RI-1: 0]   trn_val;
wire [RI-1: 0]   fil_val;
wire [RI-1: 0]   fil_out;

genvar i;
generate
   for (i=0; i < RI; i=i+1)
   begin: filtered_es_trng
       (* dont_touch = "true" *) es_trng trng_ins(
       .rst(rst),
       .clk(clk),
       .gen(trn_gen),
       .rnb(trn_rnb[i]),
       .val(trn_val[i]) 
       );

       parity_filter #(.ORD(O)) filt_ins (.rst(rst), .clk(clk), .trn_val(trn_val[i]), .trn_rnb(trn_rnb[i]), .val(fil_val[i]), .rnb(fil_out[i]));
   end
endgenerate

integer j;
reg [RI-1:0] trn_bit;
always @(posedge clk) begin
    if  (rst)               	trn_bit 	<= {RI{1'b0}};
    else begin
        for (j=0; j<RI; j=j+1)
            trn_bit[j]	<= (fil_val[j])?fil_out[j]:trn_bit[j];		
	end    
end

reg [RI-1:0] RI_bits_val;
wire all_val = &(RI_bits_val);
always @(posedge clk) begin
    if  (rst)          RI_bits_val	<= {RI{1'b0}};
    else if (all_val)  RI_bits_val	<= {RI{1'b0}};
    else		       RI_bits_val	<= RI_bits_val | fil_val;
end

wire new_value;
reg [W-1:0] trn_reg;

generate
      if (W==RI) begin: condgen1
          always @(posedge clk) begin
              if      (rst)       trn_reg <= {W{1'b0}};    
              else if (all_val)   trn_reg <= trn_bit;    
          end
          assign new_value = all_val;
      end else begin:condgen2
          reg [b-1:0]  RIbits_cnt;
          always @(posedge clk) begin
              if      (rst)       trn_reg <= {W{1'b0}};    
              else if (all_val)   trn_reg <= {trn_reg[W-RI-1:0], trn_bit};    
          end
          
          always @(posedge clk) begin
              if      (rst)       RIbits_cnt <= {b{1'b0}};    
              else if (all_val)   RIbits_cnt <= RIbits_cnt + 1'b1;    
          end
      
          assign new_value = all_val && (RIbits_cnt == WI-1);
      end
   endgenerate

always @(posedge clk) begin
    if  (rst)        trn_gen_done <= 1'b0;
    else if (new_value)  trn_gen_done <=1'b1;
    else                 trn_gen_done <= 1'b0;    
end

assign rdn = trn_reg;

endmodule