data/full_repos/permissive/165663914/firmware/receiver.v
 line:44: before: ";"
1: b"%Error: data/full_repos/permissive/165663914/firmware/receiver.v:44: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'CICRATE'\n                                                                   : ... In instance receiver\n  parameter CICRATE;\n            ^~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module receiver(
  input clock,
  input [5:0] rate,
  input [31:0] frequency,
  output out_strobe,
  input signed [13:0] in_data,
  output [23:0] out_data_I,
  output [23:0] out_data_Q,
  output signed [17:0] cordic_outdata_I,
  output signed [17:0] cordic_outdata_Q
  );

  parameter CICRATE;



wire signed [23:0] out_data_I2;
wire signed [23:0] out_data_Q2;
assign out_data_I = out_data_I2;
assign out_data_Q = out_data_Q2;






cordic cordic_inst(
  .clock(clock),
  .in_data(in_data),
  .frequency(frequency),
  .out_data_I(cordic_outdata_I),
  .out_data_Q(cordic_outdata_Q)
  );

  




























































cic #(.STAGES(5), .DECIMATION(50), .IN_WIDTH(18), .ACC_WIDTH(47), .OUT_WIDTH(24))
  cic_inst_I1(
    .clock(clock),
    .in_strobe(1'b1),
    .out_strobe(cic_outstrobe_1),
    .in_data(cordic_outdata_I),
    .out_data(cic_outdata_I1)
    );



cic #(.STAGES(5), .DECIMATION(50), .IN_WIDTH(18), .ACC_WIDTH(47), .OUT_WIDTH(24))
  cic_inst_Q1(
    .clock(clock),
    .in_strobe(1'b1),
    .out_strobe(),
    .in_data(cordic_outdata_Q),
    .out_data(cic_outdata_Q1)
    );


wire cic_outstrobe_1;
wire signed [23:0] cic_outdata_I1;
wire signed [23:0] cic_outdata_Q1;




memcic #(.STAGES(11), .DECIMATION(5), .ACC_WIDTH(48)) 
  memcic_inst_I(
    .clock(clock),
    .in_strobe(cic_outstrobe_1),
    .out_strobe(cic_outstrobe_2),
    .in_data(cic_outdata_I1),
    .out_data(cic_outdata_I2)
    );


memcic #(.STAGES(11), .DECIMATION(5), .ACC_WIDTH(48)) 
  memcic_inst_Q(
    .clock(clock),
    .in_strobe(cic_outstrobe_1),
    .out_strobe(),
    .in_data(cic_outdata_Q1),
    .out_data(cic_outdata_Q2)
    );


wire cic_outstrobe_2;
wire signed [23:0] cic_outdata_I2;
wire signed [23:0] cic_outdata_Q2;


firX2R2 fir3 (clock, cic_outstrobe_2, cic_outdata_I2, cic_outdata_Q2, out_strobe, out_data_I2, out_data_Q2);


endmodule
module receiver(
  input clock,
  input [5:0] rate,
  input [31:0] frequency,
  output out_strobe,
  input signed [13:0] in_data,
  output [23:0] out_data_I,
  output [23:0] out_data_Q,
  output signed [17:0] cordic_outdata_I,
  output signed [17:0] cordic_outdata_Q
  );


  parameter CICRATE;



wire signed [23:0] out_data_I2;
wire signed [23:0] out_data_Q2;
assign out_data_I = out_data_I2;
assign out_data_Q = out_data_Q2;






cordic cordic_inst(
  .clock(clock),
  .in_data(in_data),
  .frequency(frequency),
  .out_data_I(cordic_outdata_I),
  .out_data_Q(cordic_outdata_Q)
  );

  




























































cic #(.STAGES(5), .DECIMATION(50), .IN_WIDTH(18), .ACC_WIDTH(47), .OUT_WIDTH(24))
  cic_inst_I1(
    .clock(clock),
    .in_strobe(1'b1),
    .out_strobe(cic_outstrobe_1),
    .in_data(cordic_outdata_I),
    .out_data(cic_outdata_I1)
    );



cic #(.STAGES(5), .DECIMATION(50), .IN_WIDTH(18), .ACC_WIDTH(47), .OUT_WIDTH(24))
  cic_inst_Q1(
    .clock(clock),
    .in_strobe(1'b1),
    .out_strobe(),
    .in_data(cordic_outdata_Q),
    .out_data(cic_outdata_Q1)
    );


wire cic_outstrobe_1;
wire signed [23:0] cic_outdata_I1;
wire signed [23:0] cic_outdata_Q1;




memcic #(.STAGES(11), .DECIMATION(5), .ACC_WIDTH(48)) 
  memcic_inst_I(
    .clock(clock),
    .in_strobe(cic_outstrobe_1),
    .out_strobe(cic_outstrobe_2),
    .in_data(cic_outdata_I1),
    .out_data(cic_outdata_I2)
    );


memcic #(.STAGES(11), .DECIMATION(5), .ACC_WIDTH(48)) 
  memcic_inst_Q(
    .clock(clock),
    .in_strobe(cic_outstrobe_1),
    .out_strobe(),
    .in_data(cic_outdata_Q1),
    .out_data(cic_outdata_Q2)
    );


wire cic_outstrobe_2;
wire signed [23:0] cic_outdata_I2;
wire signed [23:0] cic_outdata_Q2;


firX2R2 fir3 (clock, cic_outstrobe_2, cic_outdata_I2, cic_outdata_Q2, out_strobe, out_data_I2, out_data_Q2);


endmodule