data/full_repos/permissive/143278/ivltests/vhdl_to_integer.v
 line:23: before: "unsign"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_to_integer.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_to_integer.v:33: Can\'t find definition of \'s_natural\' in dotted variable: \'dut.s_natural\'\n  if(dut.s_natural !== 204)\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_to_integer.v:39: Can\'t find definition of \'s_integer\' in dotted variable: \'dut.s_integer\'\n  if(dut.s_integer !== -52)\n         ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module to_int_test;
logic unsigned [7:0] unsign;
logic signed [7:0] sign;
to_int dut(unsign, sign);

initial begin
  unsign = 8'b11001100;
  sign = 8'b11001100;

  #1;

  if(dut.s_natural !== 204)
  begin
    $display("FAILED 1");
    $finish();
  end

  if(dut.s_integer !== -52)
  begin
    $display("FAILED 2");
    $finish();
  end

  $display("PASSED");
end
endmodule
module to_int_test;

logic unsigned [7:0] unsign;
logic signed [7:0] sign;
to_int dut(unsign, sign);

initial begin
  unsign = 8'b11001100;
  sign = 8'b11001100;

  #1;

  if(dut.s_natural !== 204)
  begin
    $display("FAILED 1");
    $finish();
  end

  if(dut.s_integer !== -52)
  begin
    $display("FAILED 2");
    $finish();
  end

  $display("PASSED");
end
endmodule