data/full_repos/permissive/154123726/3rdParty/fugue/fugue256.v
1: b'%Error: data/full_repos/permissive/154123726/3rdParty/fugue/fugue256.v:83: Cannot find file containing module: \'fugue256_tix\'\nfugue256_tix U_tix (\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154123726/3rdParty/fugue,data/full_repos/permissive/154123726/fugue256_tix\n             data/full_repos/permissive/154123726/3rdParty/fugue,data/full_repos/permissive/154123726/fugue256_tix.v\n             data/full_repos/permissive/154123726/3rdParty/fugue,data/full_repos/permissive/154123726/fugue256_tix.sv\n             fugue256_tix\n             fugue256_tix.v\n             fugue256_tix.sv\n             obj_dir/fugue256_tix\n             obj_dir/fugue256_tix.v\n             obj_dir/fugue256_tix.sv\n%Error: data/full_repos/permissive/154123726/3rdParty/fugue/fugue256.v:92: Cannot find file containing module: \'fugue256_cmix\'\nfugue256_cmix U0_cmix(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/fugue/fugue256.v:100: Cannot find file containing module: \'fugue256_smix\'\nfugue256_smix U0_smix(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/fugue/fugue256.v:113: Cannot find file containing module: \'fugue256_col_xor1516\'\nfugue256_col_xor1516 U0_colxor(\n^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/fugue/fugue256.v:153: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'Base\' generates 5 bits.\n                                                                                  : ... In instance fugue256_round\n         temp   = Base + col;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/fugue/fugue256.v:153: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'col\' generates 5 bits.\n                                                                                  : ... In instance fugue256_round\n         temp   = Base + col;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/fugue/fugue256.v:154: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                  : ... In instance fugue256_round\n         COLUMN = (temp < 30) ? temp : (temp-30); \n                ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module fugue256_round(
											hs_stat_i,
											hs_base_i,
											message_i,
											mod_sel_i,
											hs_stat_o,
											hs_base_o);
input  [959:0] hs_stat_i;
input  [  4:0] hs_base_i;
input  [ 31:0] message_i;
input  [  2:0] mod_sel_i;
output [959:0] hs_stat_o;
output [  4:0] hs_base_o;

wire   [  2:0] mod_sel_i;
wire   [959:0] hs_stat_i;
wire   [  4:0] hs_base_i;
wire   [959:0] hs_stat_o;
wire   [  4:0] hs_base_o;


parameter n =  8,
					s = 30,
					k =  2,
					r =  5,
					t = 13;

parameter UPDATEa = 0, FINAL_G2a = 1, LAST = 2, DIRECT = 3, FINAL_G1 = 4, FINAL_G2b = 5, UPDATEb = 6;					












wire [959:0] step0_stat,step1_stat,step2_stat,step3_stat;
wire [  4:0] step0_base,step1_base,step2_base,step3_base;


wire [ 31:0] step0_stat_array[0:29];
wire [ 31:0] step1_stat_array[0:29];
wire [ 31:0] step2_stat_array[0:29];
wire [ 31:0] step3_stat_array[0:29];

genvar i;
generate
	for(i=0;i<30;i=i+1) begin : gen_step
		assign step0_stat_array[i] = step0_stat[(i+1)*32-1:i*32];	
		assign step1_stat_array[i] = step1_stat[(i+1)*32-1:i*32];	
		assign step2_stat_array[i] = step2_stat[(i+1)*32-1:i*32];	
		assign step3_stat_array[i] = step3_stat[(i+1)*32-1:i*32];	
	end    
endgenerate





wire [959:0] TIX;
fugue256_tix U_tix (
								    .Base        (hs_base_i),
								    .state_d_long(hs_stat_i),
								    .sc          (message_i),

								    .TIX         (TIX)	
									 );

wire [959:0] CMIX_0;
fugue256_cmix U0_cmix(
										.Base         (step1_base),
										.state_d_long (step1_stat),

										.CMIX         (CMIX_0)
										);

wire [959:0] SMIX_0;					
fugue256_smix U0_smix(
										.Base        (step2_base),
										.state_d_long(step2_stat),

										.SMIX        (SMIX_0)
										);

wire [959:0] Col_Xor1516_0;
wire [959:0] Col_Xor1516_1;

wire sel_final_g2;
assign sel_final_g2 = (mod_sel_i == FINAL_G2a|mod_sel_i==LAST) ? 1 : 0;

fugue256_col_xor1516 U0_colxor(
														 .Base        (hs_base_i),
														 .sel         (sel_final_g2),
														 .state_d_long(hs_stat_i),

														 .Col_Xor1516 (Col_Xor1516_0)
														 );


	assign step0_stat = mod_sel_i==UPDATEa   ? TIX : 
											mod_sel_i==FINAL_G2a ? Col_Xor1516_0:   
											mod_sel_i==FINAL_G2b ? Col_Xor1516_0:   
										  mod_sel_i==LAST      ? Col_Xor1516_0: 
										  							 		   	 hs_stat_i;	 
																 
	assign step0_base = hs_base_i;
	

	assign step1_stat = step0_stat;
	assign step1_base = (mod_sel_i==UPDATEa|mod_sel_i==UPDATEb|mod_sel_i==FINAL_G1) ? ROTATE(step0_base, 3): step0_base;	
	

  assign step2_stat = (mod_sel_i==UPDATEa|mod_sel_i==UPDATEb|mod_sel_i==FINAL_G1) ? CMIX_0 : step1_stat;	
  assign step2_base = mod_sel_i==FINAL_G2a  ? ROTATE(step1_base, 15) : 
  										mod_sel_i==FINAL_G2b  ?	ROTATE(step1_base, 14) : step1_base;


  assign step3_stat = (mod_sel_i==UPDATEa|mod_sel_i==UPDATEb|mod_sel_i==FINAL_G2a|mod_sel_i==FINAL_G2b|mod_sel_i==FINAL_G1 )? SMIX_0 : step2_stat;
  assign step3_base = step2_base;
  assign hs_stat_o  = step3_stat;
  assign hs_base_o  = step3_base;



   	  function [4:0] COLUMN;
   	  		input [4:0] Base;
   	  		input [4:0] col;

   	  		integer temp;
   	  		begin
   	  			temp   = Base + col;
   	  			COLUMN = (temp < 30) ? temp : (temp-30); 
   	  		end
   	  endfunction
   	


   		function [4:0] ROTATE;
   				input [4:0] Base;
   				input [3:0] r;
   				begin
   					ROTATE = COLUMN(Base, 30-r);
   				end
   		endfunction

endmodule
module fugue256_round(
											hs_stat_i,
											hs_base_i,
											message_i,
											mod_sel_i,
											hs_stat_o,
											hs_base_o);

input  [959:0] hs_stat_i;
input  [  4:0] hs_base_i;
input  [ 31:0] message_i;
input  [  2:0] mod_sel_i;
output [959:0] hs_stat_o;
output [  4:0] hs_base_o;

wire   [  2:0] mod_sel_i;
wire   [959:0] hs_stat_i;
wire   [  4:0] hs_base_i;
wire   [959:0] hs_stat_o;
wire   [  4:0] hs_base_o;


parameter n =  8,
					s = 30,
					k =  2,
					r =  5,
					t = 13;

parameter UPDATEa = 0, FINAL_G2a = 1, LAST = 2, DIRECT = 3, FINAL_G1 = 4, FINAL_G2b = 5, UPDATEb = 6;					












wire [959:0] step0_stat,step1_stat,step2_stat,step3_stat;
wire [  4:0] step0_base,step1_base,step2_base,step3_base;


wire [ 31:0] step0_stat_array[0:29];
wire [ 31:0] step1_stat_array[0:29];
wire [ 31:0] step2_stat_array[0:29];
wire [ 31:0] step3_stat_array[0:29];

genvar i;
generate
	for(i=0;i<30;i=i+1) begin : gen_step
		assign step0_stat_array[i] = step0_stat[(i+1)*32-1:i*32];	
		assign step1_stat_array[i] = step1_stat[(i+1)*32-1:i*32];	
		assign step2_stat_array[i] = step2_stat[(i+1)*32-1:i*32];	
		assign step3_stat_array[i] = step3_stat[(i+1)*32-1:i*32];	
	end    
endgenerate





wire [959:0] TIX;
fugue256_tix U_tix (
								    .Base        (hs_base_i),
								    .state_d_long(hs_stat_i),
								    .sc          (message_i),

								    .TIX         (TIX)	
									 );

wire [959:0] CMIX_0;
fugue256_cmix U0_cmix(
										.Base         (step1_base),
										.state_d_long (step1_stat),

										.CMIX         (CMIX_0)
										);

wire [959:0] SMIX_0;					
fugue256_smix U0_smix(
										.Base        (step2_base),
										.state_d_long(step2_stat),

										.SMIX        (SMIX_0)
										);

wire [959:0] Col_Xor1516_0;
wire [959:0] Col_Xor1516_1;

wire sel_final_g2;
assign sel_final_g2 = (mod_sel_i == FINAL_G2a|mod_sel_i==LAST) ? 1 : 0;

fugue256_col_xor1516 U0_colxor(
														 .Base        (hs_base_i),
														 .sel         (sel_final_g2),
														 .state_d_long(hs_stat_i),

														 .Col_Xor1516 (Col_Xor1516_0)
														 );


	assign step0_stat = mod_sel_i==UPDATEa   ? TIX : 
											mod_sel_i==FINAL_G2a ? Col_Xor1516_0:   
											mod_sel_i==FINAL_G2b ? Col_Xor1516_0:   
										  mod_sel_i==LAST      ? Col_Xor1516_0: 
										  							 		   	 hs_stat_i;	 
																 
	assign step0_base = hs_base_i;
	

	assign step1_stat = step0_stat;
	assign step1_base = (mod_sel_i==UPDATEa|mod_sel_i==UPDATEb|mod_sel_i==FINAL_G1) ? ROTATE(step0_base, 3): step0_base;	
	

  assign step2_stat = (mod_sel_i==UPDATEa|mod_sel_i==UPDATEb|mod_sel_i==FINAL_G1) ? CMIX_0 : step1_stat;	
  assign step2_base = mod_sel_i==FINAL_G2a  ? ROTATE(step1_base, 15) : 
  										mod_sel_i==FINAL_G2b  ?	ROTATE(step1_base, 14) : step1_base;


  assign step3_stat = (mod_sel_i==UPDATEa|mod_sel_i==UPDATEb|mod_sel_i==FINAL_G2a|mod_sel_i==FINAL_G2b|mod_sel_i==FINAL_G1 )? SMIX_0 : step2_stat;
  assign step3_base = step2_base;
  assign hs_stat_o  = step3_stat;
  assign hs_base_o  = step3_base;



   	  function [4:0] COLUMN;
   	  		input [4:0] Base;
   	  		input [4:0] col;

   	  		integer temp;
   	  		begin
   	  			temp   = Base + col;
   	  			COLUMN = (temp < 30) ? temp : (temp-30); 
   	  		end
   	  endfunction
   	


   		function [4:0] ROTATE;
   				input [4:0] Base;
   				input [3:0] r;
   				begin
   					ROTATE = COLUMN(Base, 30-r);
   				end
   		endfunction

endmodule