data/full_repos/permissive/123796236/alu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123796236/alu.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alu.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alu.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alu.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alu.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testALU();

wire [31:0] alu_Result;
reg [31:0] input1, input2;
wire alu_zeroFlag;
reg [3:0] aluCtrl;

alu a(alu_Result, alu_zeroFlag, input1, input2, aluCtrl);
initial begin
	input1 = 32'd1;
	input2 = 32'd1;
	end

always
	begin
		#100
		aluCtrl = 4'b0000;
		#100
		aluCtrl = 4'b0001;
		#100
		aluCtrl = 4'b0010;
		#100
		aluCtrl = 4'b0110;
		#100
		aluCtrl = 4'b0111;

	end
endmodule
module testALU();


wire [31:0] alu_Result;
reg [31:0] input1, input2;
wire alu_zeroFlag;
reg [3:0] aluCtrl;

alu a(alu_Result, alu_zeroFlag, input1, input2, aluCtrl);
initial begin
	input1 = 32'd1;
	input2 = 32'd1;
	end

always
	begin
		#100
		aluCtrl = 4'b0000;
		#100
		aluCtrl = 4'b0001;
		#100
		aluCtrl = 4'b0010;
		#100
		aluCtrl = 4'b0110;
		#100
		aluCtrl = 4'b0111;

	end
endmodule