data/full_repos/permissive/157049472/Verilog Source Files/InstructionFetch.v
1: b'%Error: Cannot find file containing module: Source\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Source\n             data/full_repos/permissive/157049472/Verilog/Source.v\n             data/full_repos/permissive/157049472/Verilog/Source.sv\n             Source\n             Source.v\n             Source.sv\n             obj_dir/Source\n             obj_dir/Source.v\n             obj_dir/Source.sv\n%Error: Cannot find file containing module: Files,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Files/InstructionFetch.v\n%Error: Exiting due to 4 error(s)\n'
module InstructionFetch(input wire [31:0] pc,output wire [31:0] instruction,input wire clk,input wire rst);
	wire [4:0] rom_address;
	assign rom_address = pc[6:2];
	blk_mem_gen_v7_3 instruction_memory(.clka(~clk),.rsta(rst),.ena(1'b1),.wea(1'b0),.addra(rom_address),.dina(32'd0),.douta(instruction));
endmodule
module InstructionFetch(input wire [31:0] pc,output wire [31:0] instruction,input wire clk,input wire rst);

	wire [4:0] rom_address;
	assign rom_address = pc[6:2];
	blk_mem_gen_v7_3 instruction_memory(.clka(~clk),.rsta(rst),.ena(1'b1),.wea(1'b0),.addra(rom_address),.dina(32'd0),.douta(instruction));
endmodule