data/full_repos/permissive/214823094/lab_7/project_1/project_1.srcs/sources_1/new/bus.v
data/verilator_xmls/7f7dd0f0-285f-46b7-bf12-d5571dcce98b.xml
module ram2(
    input clk,
    input wen,
    input [3:0] addr,
    input [3:0] din,
    output [3:0] qout
    );
    reg[3:0]ram[0:15];
    always@(posedge clk)
      if(wen)
        ram[addr]<=din;
      assign qout=ram[addr];  
endmodule
module ram2(
    input clk,
    input wen,
    input [3:0] addr,
    input [3:0] din,
    output [3:0] qout
    );

    reg[3:0]ram[0:15];
    always@(posedge clk)
      if(wen)
        ram[addr]<=din;
      assign qout=ram[addr];  
endmodule