data/full_repos/permissive/101171422/sim/gates.v
 line:19: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #5 x = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #5 x = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #5 x = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/gates.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #5 $finish;\n  ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function f_nor
	(
		input x,
		input y
	);
		f_nor = f_not(f_or(x, y));
	endfunction
function f_nor
	(
		input x,
		input y
	);

		f_nor = f_not(f_or(x, y));
	endfunction