data/full_repos/permissive/211866113/RippleCarryAdder.v
data/verilator_xmls/1566e309-2d70-4d78-a82a-39e516bebabc.xml
module rippe_carry_adder(input [2:0] X,
			 input [2:0]  Y,
			 input Cin,
			 output [2:0] S,
			 output       Cout);

    wire 			      w0, w1;

    full_adder fa0(X[0], Y[0], Cin, S[0], w0);
    full_adder fa1(X[1], Y[1], w0, S[1], w1);
    full_adder fa2(X[2], Y[2], w1, S[2], Cout);
endmodule
module rippe_carry_adder(input [2:0] X,
			 input [2:0]  Y,
			 input Cin,
			 output [2:0] S,
			 output       Cout);


    wire 			      w0, w1;

    full_adder fa0(X[0], Y[0], Cin, S[0], w0);
    full_adder fa1(X[1], Y[1], w0, S[1], w1);
    full_adder fa2(X[2], Y[2], w1, S[2], Cout);
endmodule