data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/pc.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/0f5b3725-bd56-4815-8e33-85adfb5ffd71.xml
module pc(
    input wire          rst,
    input wire          clk,
    input wire[31:0]    npc,
    
    output reg[31:0]    pc
    );



    always @ (posedge rst or posedge clk) begin
        if (rst) begin
            pc <= 32'h00000000;
        end else begin
            pc <= npc;
        end
    end

endmodule
module pc(
    input wire          rst,
    input wire          clk,
    input wire[31:0]    npc,
    
    output reg[31:0]    pc
    );




    always @ (posedge rst or posedge clk) begin
        if (rst) begin
            pc <= 32'h00000000;
        end else begin
            pc <= npc;
        end
    end

endmodule