data/full_repos/permissive/201425860/verilator_simulators/Verilog_RTL/DMITap.v
 line:10: before: "import"
1: b'%Error: data/full_repos/permissive/201425860/verilator_simulators/Verilog_RTL/DMITap.v:6: Cannot find include file: sim_socket.vh\n`include "sim_socket.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201425860/verilator_simulators/Verilog_RTL,data/full_repos/permissive/201425860/sim_socket.vh\n             data/full_repos/permissive/201425860/verilator_simulators/Verilog_RTL,data/full_repos/permissive/201425860/sim_socket.vh.v\n             data/full_repos/permissive/201425860/verilator_simulators/Verilog_RTL,data/full_repos/permissive/201425860/sim_socket.vh.sv\n             sim_socket.vh\n             sim_socket.vh.v\n             sim_socket.vh.sv\n             obj_dir/sim_socket.vh\n             obj_dir/sim_socket.vh.v\n             obj_dir/sim_socket.vh.sv\n%Error: data/full_repos/permissive/201425860/verilator_simulators/Verilog_RTL/DMITap.v:7: Cannot find include file: sim_dmi.vh\n`include "sim_dmi.vh" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module DMITap(

  input clock,
  input reset,



  input dmi_in_dmiClock,
  input dmi_in_dmiReset,

  output        dmi_out_dmi_req_valid,
  input         dmi_out_dmi_req_ready,
  output [ 6:0] dmi_out_dmi_req_bits_addr,
  output [ 1:0] dmi_out_dmi_req_bits_op,
  output [31:0] dmi_out_dmi_req_bits_data,

  input         dmi_out_dmi_resp_valid,
  output        dmi_out_dmi_resp_ready,
  input  [ 1:0] dmi_out_dmi_resp_bits_resp,
  input  [31:0] dmi_out_dmi_resp_bits_data,

  input         dmi_in_dmi_req_valid,
  output        dmi_in_dmi_req_ready,
  input  [ 6:0] dmi_in_dmi_req_bits_addr,
  input  [ 1:0] dmi_in_dmi_req_bits_op,
  input  [31:0] dmi_in_dmi_req_bits_data,

  output        dmi_in_dmi_resp_valid,
  input         dmi_in_dmi_resp_ready,
  output [ 1:0] dmi_in_dmi_resp_bits_resp,
  output [31:0] dmi_in_dmi_resp_bits_data,

  output dmi_out_dmiClock,
  output dmi_out_dmiReset
);

   int port;
   int sock;
   int fd;
   int err;
   int delay_count;

   initial begin
      fd = -1;
      delay_count = 0;

      if ($value$plusargs("vpi_port=%d", port) == 0)
	port = `DEFAULT_DEBUG_PORT_VPI;

      $display("using debug port (vpi) :%d", port);

      sock = socket_open(port);
      if (sock < 0) begin
	 $display("ERROR: socket_open(%d) returned %d", port, sock);
	 $finish;
      end
   end


   assign dmi_out_dmiClock = clock;
   assign dmi_out_dmiReset = reset;




   assign dmi_in_dmi_req_ready  = 0;
   assign dmi_in_dmi_resp_valid = 0;
   assign dmi_in_dmi_resp_bits_resp = '0;
   assign dmi_in_dmi_resp_bits_data = '0;

   always @(posedge clock) begin
      if (reset) begin
	 dmi_out_dmi_req_valid <= 0;
	 dmi_out_dmi_req_bits_addr <= 0;
	 dmi_out_dmi_req_bits_data <= 0;
	 dmi_out_dmi_req_bits_op <= 0;
	 dmi_out_dmi_resp_ready <= 0;
      end
   end

   always @(posedge clock) begin
      if (~reset) begin
	 if (fd >= 0) begin
	    dmi_out_dmi_resp_ready <= 1;

	    if (dmi_out_dmi_resp_valid) begin
	       int data;
	       int response;
	       data = dmi_out_dmi_resp_bits_data;
	       response = {30'd0, dmi_out_dmi_resp_bits_resp};
	       err = vpidmi_response(fd, data, response);
	       if (err < 0) begin
		  $display("ERROR: vpidmi_response() returned %d", err);
		  $finish;
	       end
	    end

	    if (!dmi_out_dmi_req_valid || dmi_out_dmi_req_ready) begin
	       if (delay_count == 0) begin
		  int addr;
		  int data;
		  int op;
		  err = vpidmi_request(fd, addr, data, op);
		  if (err < 0) begin
		     $display("ERROR: vpidmi_request() returned %d", err);
		     $finish;
		  end
		  else if (err > 0) begin
		     dmi_out_dmi_req_valid <= 1;
		     dmi_out_dmi_req_bits_addr <= addr[6:0];
		     dmi_out_dmi_req_bits_data <= data;
		     dmi_out_dmi_req_bits_op <= op[1:0];
		     if (op[1:0] == 2) delay_count = `DELAY_VALUE;
		  end
		  else
		     dmi_out_dmi_req_valid <= 0;
	       end
	       else begin
		  delay_count = delay_count - 1;
		  dmi_out_dmi_req_valid <= 0;
	       end
	    end
	 end
	 else begin
	    fd = socket_accept(sock);
	 end
      end
   end

endmodule
module DMITap(

  input clock,
  input reset,



  input dmi_in_dmiClock,
  input dmi_in_dmiReset,

  output        dmi_out_dmi_req_valid,
  input         dmi_out_dmi_req_ready,
  output [ 6:0] dmi_out_dmi_req_bits_addr,
  output [ 1:0] dmi_out_dmi_req_bits_op,
  output [31:0] dmi_out_dmi_req_bits_data,

  input         dmi_out_dmi_resp_valid,
  output        dmi_out_dmi_resp_ready,
  input  [ 1:0] dmi_out_dmi_resp_bits_resp,
  input  [31:0] dmi_out_dmi_resp_bits_data,

  input         dmi_in_dmi_req_valid,
  output        dmi_in_dmi_req_ready,
  input  [ 6:0] dmi_in_dmi_req_bits_addr,
  input  [ 1:0] dmi_in_dmi_req_bits_op,
  input  [31:0] dmi_in_dmi_req_bits_data,

  output        dmi_in_dmi_resp_valid,
  input         dmi_in_dmi_resp_ready,
  output [ 1:0] dmi_in_dmi_resp_bits_resp,
  output [31:0] dmi_in_dmi_resp_bits_data,

  output dmi_out_dmiClock,
  output dmi_out_dmiReset
);


   int port;
   int sock;
   int fd;
   int err;
   int delay_count;

   initial begin
      fd = -1;
      delay_count = 0;

      if ($value$plusargs("vpi_port=%d", port) == 0)
	port = `DEFAULT_DEBUG_PORT_VPI;

      $display("using debug port (vpi) :%d", port);

      sock = socket_open(port);
      if (sock < 0) begin
	 $display("ERROR: socket_open(%d) returned %d", port, sock);
	 $finish;
      end
   end


   assign dmi_out_dmiClock = clock;
   assign dmi_out_dmiReset = reset;




   assign dmi_in_dmi_req_ready  = 0;
   assign dmi_in_dmi_resp_valid = 0;
   assign dmi_in_dmi_resp_bits_resp = '0;
   assign dmi_in_dmi_resp_bits_data = '0;

   always @(posedge clock) begin
      if (reset) begin
	 dmi_out_dmi_req_valid <= 0;
	 dmi_out_dmi_req_bits_addr <= 0;
	 dmi_out_dmi_req_bits_data <= 0;
	 dmi_out_dmi_req_bits_op <= 0;
	 dmi_out_dmi_resp_ready <= 0;
      end
   end

   always @(posedge clock) begin
      if (~reset) begin
	 if (fd >= 0) begin
	    dmi_out_dmi_resp_ready <= 1;

	    if (dmi_out_dmi_resp_valid) begin
	       int data;
	       int response;
	       data = dmi_out_dmi_resp_bits_data;
	       response = {30'd0, dmi_out_dmi_resp_bits_resp};
	       err = vpidmi_response(fd, data, response);
	       if (err < 0) begin
		  $display("ERROR: vpidmi_response() returned %d", err);
		  $finish;
	       end
	    end

	    if (!dmi_out_dmi_req_valid || dmi_out_dmi_req_ready) begin
	       if (delay_count == 0) begin
		  int addr;
		  int data;
		  int op;
		  err = vpidmi_request(fd, addr, data, op);
		  if (err < 0) begin
		     $display("ERROR: vpidmi_request() returned %d", err);
		     $finish;
		  end
		  else if (err > 0) begin
		     dmi_out_dmi_req_valid <= 1;
		     dmi_out_dmi_req_bits_addr <= addr[6:0];
		     dmi_out_dmi_req_bits_data <= data;
		     dmi_out_dmi_req_bits_op <= op[1:0];
		     if (op[1:0] == 2) delay_count = `DELAY_VALUE;
		  end
		  else
		     dmi_out_dmi_req_valid <= 0;
	       end
	       else begin
		  delay_count = delay_count - 1;
		  dmi_out_dmi_req_valid <= 0;
	       end
	    end
	 end
	 else begin
	    fd = socket_accept(sock);
	 end
      end
   end

endmodule