data/full_repos/permissive/128117771/Automaton-VGA-80bit/register.v
data/verilator_xmls/862aa393-b791-4c81-bf03-00ee54cbff18.xml
module register #( parameter W=1 ) (
    input wire clk, 
    input wire  [W-1:0] in,
    output reg  [W-1:0] out
  );

  always @( posedge clk )
    out <= in;
endmodule
module register #( parameter W=1 ) (
    input wire clk, 
    input wire  [W-1:0] in,
    output reg  [W-1:0] out
  );


  always @( posedge clk )
    out <= in;
endmodule