data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Rom.v
data/verilator_xmls/ca0e6e5c-06fe-400e-aab3-ac5ca6b5b77e.xml
module Rom #(
        parameter ADDR_WIDTH = 10,
        parameter DATA_WIDTH = 32,
        parameter ROM_SIZE = 1024
    )(
        input [ADDR_WIDTH - 1:0] addr,
        output [DATA_WIDTH - 1:0] data
    );

    reg [31:0] memory [ROM_SIZE - 1:0];

    initial begin
        $readmemh("instructions.txt", memory);
    end

    assign data = memory[addr];

endmodule
module Rom #(
        parameter ADDR_WIDTH = 10,
        parameter DATA_WIDTH = 32,
        parameter ROM_SIZE = 1024
    )(
        input [ADDR_WIDTH - 1:0] addr,
        output [DATA_WIDTH - 1:0] data
    );


    reg [31:0] memory [ROM_SIZE - 1:0];

    initial begin
        $readmemh("instructions.txt", memory);
    end

    assign data = memory[addr];

endmodule