data/full_repos/permissive/114459345/srcCache/ex.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/ex.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:9: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] pc_i,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] pc_i,\n                        ^\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:10: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] aluop_i,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:11: Define or directive not defined: \'`AluFunct3Bus\'\n input wire[`AluFunct3Bus] alufunct3_i,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:12: Define or directive not defined: \'`AluFunct7Bus\'\n input wire[`AluFunct7Bus] alufunct7_i,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:13: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg1_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg2_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] imm_i,   \n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:16: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] wd_i,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[`AluOpBus] aluop_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:20: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus] aluop_o,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:21: Define or directive not defined: \'`AluFunct3Bus\'\n output reg[`AluFunct3Bus] alufunct3_o,  \n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`MemAddrBus] maddr_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:23: Define or directive not defined: \'`MemAddrBus\'\n output reg[`MemAddrBus] maddr_o,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] wd_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:25: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_o,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:26: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wdata_o,  \n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:30: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] wd_f,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:30: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_f,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:31: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wdata_f\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:36: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] shiftbits = reg2_i[4:0];\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] shiftbits = reg2_i[4:0];\n                 ^\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:39: Define or directive not defined: \'`MemAddrBus\'\n reg[`MemAddrBus] maddr;   \n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`MemAddrBus] maddr;   \n                ^\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:40: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] logicout;   \n     ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] logicout;   \n            ^\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:44: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:45: Define or directive not defined: \'`MemDisable\'\n   me <= `MemDisable;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:46: Define or directive not defined: \'`NopMem\'\n   maddr <= `NopMem;\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:47: Define or directive not defined: \'`ZeroWord\'\n   logicout <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:50: Define or directive not defined: \'`MemDisable\'\n   me <= `MemDisable;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:51: Define or directive not defined: \'`NopMem\'\n   maddr <= `NopMem;\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:52: Define or directive not defined: \'`ZeroWord\'\n   logicout <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:55: Define or directive not defined: \'`LUI\'\n    `LUI : begin\n    ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:58: Define or directive not defined: \'`AUIPC\'\n    `AUIPC : begin\n    ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:61: Define or directive not defined: \'`JAL\'\n    `JAL : begin\n    ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:64: Define or directive not defined: \'`JALR\'\n    `JALR : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:68: Define or directive not defined: \'`LOAD\'\n    `LOAD : begin\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:69: Define or directive not defined: \'`MemEnable\'\n     me <= `MemEnable;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:89: Define or directive not defined: \'`STORE\'\n    `STORE : begin\n    ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:90: Define or directive not defined: \'`MemEnable\'\n     me <= `MemEnable;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:105: Define or directive not defined: \'`EXE_IMM\'\n    `EXE_IMM : begin\n    ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:107: Define or directive not defined: \'`ADDI\'\n      `ADDI : begin\n      ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:110: Define or directive not defined: \'`SLTI\'\n      `SLTI : begin\n      ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:112: Define or directive not defined: \'`OneWord\'\n        logicout <= `OneWord;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:115: Define or directive not defined: \'`ZeroWord\'\n        logicout <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:118: Define or directive not defined: \'`SLTIU\'\n      `SLTIU : begin\n      ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:120: Define or directive not defined: \'`OneWord\'\n        logicout <= `OneWord;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:123: Define or directive not defined: \'`ZeroWord\'\n        logicout <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ex(

	input wire rst,
	

	input wire[`InstAddrBus] pc_i,
	input wire[`AluOpBus] aluop_i,
	input wire[`AluFunct3Bus] alufunct3_i,
	input wire[`AluFunct7Bus] alufunct7_i,
	input wire[`RegBus] reg1_i,
	input wire[`RegBus] reg2_i,
	input wire[`RegBus] imm_i,
	input wire[`RegAddrBus] wd_i,
	input wire wreg_i,
	

	output reg[`AluOpBus] aluop_o,
	output reg[`AluFunct3Bus] alufunct3_o,
	output reg me_o,
	output reg[`MemAddrBus] maddr_o,
	output reg wreg_o,
	output reg[`RegAddrBus] wd_o,
	output reg[`RegBus] wdata_o,
	

	output reg wreg_f,
	output reg[`RegAddrBus] wd_f,
	output reg[`RegBus] wdata_f
	
);


	wire[`RegAddrBus] shiftbits = reg2_i[4:0];

	reg me;
	reg[`MemAddrBus] maddr;
	reg[`RegBus] logicout;
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			me <= `MemDisable;
			maddr <= `NopMem;
			logicout <= `ZeroWord;
		end
		else begin
			me <= `MemDisable;
			maddr <= `NopMem;
			logicout <= `ZeroWord;
			
			case(aluop_i)
				`LUI : begin
					logicout <= reg1_i;
				end
				`AUIPC : begin
					logicout <= reg1_i + pc_i;
				end
				`JAL : begin
					logicout <= pc_i + 4;
				end
				`JALR : begin
					logicout <= pc_i + 4;					
				end

				`LOAD : begin
					me <= `MemEnable;
					maddr <= reg1_i + imm_i;


							


						


						


						


						


				end
				`STORE : begin
					me <= `MemEnable;
					maddr <= reg1_i + imm_i;
					logicout <= reg2_i;


						


						


						


				end
				`EXE_IMM : begin
					case(alufunct3_i)
						`ADDI : begin
							logicout <= reg1_i + reg2_i;
						end
						`SLTI : begin
							if($signed(reg1_i) < $signed(reg2_i)) begin
								logicout <= `OneWord;
							end
							else begin
								logicout <= `ZeroWord;
							end
						end
						`SLTIU : begin
							if(reg1_i < reg2_i) begin
								logicout <= `OneWord;
							end
							else begin
								logicout <= `ZeroWord;
							end
						end
						`XORI : begin
							logicout <= reg1_i ^ reg2_i;
						end
						`ORI : begin
							logicout <= reg1_i | reg2_i;
						end
						`ANDI : begin
							logicout <= reg1_i & reg2_i;
						end
						`SLLI : begin
							logicout <= reg1_i << shiftbits;
						end
						`SRLI_SRAI : begin
							case(alufunct7_i)
								`SRLI : begin
									logicout <= reg1_i >> shiftbits;
								end
								`SRAI : begin
									logicout <= (reg1_i >> shiftbits) | ({32{1'b1}} << (`RegWidth - shiftbits));
								end
							endcase
						end
					endcase
				end
				`EXE : begin
					case(alufunct3_i)
						`ADD_SUB : begin
							case(alufunct7_i)
								`ADD : begin
									logicout <= $signed(reg1_i) + $signed(reg2_i);
								end
								`SUB : begin
									logicout <= $signed(reg1_i) - $signed(reg2_i);
								end
							endcase
						end
						`SLL : begin
							logicout <= reg1_i << shiftbits;
						end
						`SLT : begin
							if($signed(reg1_i) < $signed(reg2_i)) begin
								logicout <= `OneWord;
							end
							else begin
								logicout <= `ZeroWord;
							end					
						end
						`SLTU : begin
							if(reg1_i < reg2_i) begin
								logicout <= `OneWord;
							end
							else begin
								logicout <= `ZeroWord;
							end							
						end
						`XOR : begin
							logicout <= reg1_i ^ reg2_i;
						end
						`SRL_SRA : begin
							case(alufunct7_i)
								`SRL : begin
									logicout <= reg1_i >> shiftbits;
								end
								`SRA : begin
									logicout <= (reg1_i >> shiftbits) | ({32{1'b1}} << (`RegWidth - shiftbits));
								end
							endcase						
						end
						`OR : begin
							logicout <= reg1_i | reg2_i;
						end
						`AND : begin
							logicout <= reg1_i & reg2_i;
						end
					endcase
				end




						


						


						


						


						


						


						



				default: begin
					logicout <= `ZeroWord;
				end
			endcase
		end
	end
	
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			aluop_o <= `NOP;
			alufunct3_o <= `NOP_FUNCT3;
			me_o <= `MemDisable;
			maddr_o <= `NopMem;
			wreg_o <= `WriteDisable;
			wd_o <= `NopRegAddr;
			wdata_o <= `ZeroWord;		
		end
		else begin
			aluop_o <= aluop_i;
			alufunct3_o <= alufunct3_i;
			me_o <= me;
			maddr_o <= maddr;
			wreg_o <= wreg_i;
			wd_o <= wd_i;
			wdata_o <= logicout;
		end
	end
	

	always @ (*) begin 
		if(rst == `RstEnable) begin
			wreg_f <= `WriteDisable;
			wd_f <= `NopRegAddr;
			wdata_f <= `ZeroWord;
		end
		else begin
			if(aluop_i == `LOAD) begin
				wreg_f <= `WriteDisable;
			end
			else begin
				wreg_f <= wreg_o;
			end	
			wd_f <= wd_o;
			wdata_f <= wdata_o;		
		end
	end

endmodule
module ex(

	input wire rst,
	

	input wire[`InstAddrBus] pc_i,
	input wire[`AluOpBus] aluop_i,
	input wire[`AluFunct3Bus] alufunct3_i,
	input wire[`AluFunct7Bus] alufunct7_i,
	input wire[`RegBus] reg1_i,
	input wire[`RegBus] reg2_i,
	input wire[`RegBus] imm_i,
	input wire[`RegAddrBus] wd_i,
	input wire wreg_i,
	

	output reg[`AluOpBus] aluop_o,
	output reg[`AluFunct3Bus] alufunct3_o,
	output reg me_o,
	output reg[`MemAddrBus] maddr_o,
	output reg wreg_o,
	output reg[`RegAddrBus] wd_o,
	output reg[`RegBus] wdata_o,
	

	output reg wreg_f,
	output reg[`RegAddrBus] wd_f,
	output reg[`RegBus] wdata_f
	
);



	wire[`RegAddrBus] shiftbits = reg2_i[4:0];

	reg me;
	reg[`MemAddrBus] maddr;
	reg[`RegBus] logicout;
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			me <= `MemDisable;
			maddr <= `NopMem;
			logicout <= `ZeroWord;
		end
		else begin
			me <= `MemDisable;
			maddr <= `NopMem;
			logicout <= `ZeroWord;
			
			case(aluop_i)
				`LUI : begin
					logicout <= reg1_i;
				end
				`AUIPC : begin
					logicout <= reg1_i + pc_i;
				end
				`JAL : begin
					logicout <= pc_i + 4;
				end
				`JALR : begin
					logicout <= pc_i + 4;					
				end

				`LOAD : begin
					me <= `MemEnable;
					maddr <= reg1_i + imm_i;


							


						


						


						


						


				end
				`STORE : begin
					me <= `MemEnable;
					maddr <= reg1_i + imm_i;
					logicout <= reg2_i;


						


						


						


				end
				`EXE_IMM : begin
					case(alufunct3_i)
						`ADDI : begin
							logicout <= reg1_i + reg2_i;
						end
						`SLTI : begin
							if($signed(reg1_i) < $signed(reg2_i)) begin
								logicout <= `OneWord;
							end
							else begin
								logicout <= `ZeroWord;
							end
						end
						`SLTIU : begin
							if(reg1_i < reg2_i) begin
								logicout <= `OneWord;
							end
							else begin
								logicout <= `ZeroWord;
							end
						end
						`XORI : begin
							logicout <= reg1_i ^ reg2_i;
						end
						`ORI : begin
							logicout <= reg1_i | reg2_i;
						end
						`ANDI : begin
							logicout <= reg1_i & reg2_i;
						end
						`SLLI : begin
							logicout <= reg1_i << shiftbits;
						end
						`SRLI_SRAI : begin
							case(alufunct7_i)
								`SRLI : begin
									logicout <= reg1_i >> shiftbits;
								end
								`SRAI : begin
									logicout <= (reg1_i >> shiftbits) | ({32{1'b1}} << (`RegWidth - shiftbits));
								end
							endcase
						end
					endcase
				end
				`EXE : begin
					case(alufunct3_i)
						`ADD_SUB : begin
							case(alufunct7_i)
								`ADD : begin
									logicout <= $signed(reg1_i) + $signed(reg2_i);
								end
								`SUB : begin
									logicout <= $signed(reg1_i) - $signed(reg2_i);
								end
							endcase
						end
						`SLL : begin
							logicout <= reg1_i << shiftbits;
						end
						`SLT : begin
							if($signed(reg1_i) < $signed(reg2_i)) begin
								logicout <= `OneWord;
							end
							else begin
								logicout <= `ZeroWord;
							end					
						end
						`SLTU : begin
							if(reg1_i < reg2_i) begin
								logicout <= `OneWord;
							end
							else begin
								logicout <= `ZeroWord;
							end							
						end
						`XOR : begin
							logicout <= reg1_i ^ reg2_i;
						end
						`SRL_SRA : begin
							case(alufunct7_i)
								`SRL : begin
									logicout <= reg1_i >> shiftbits;
								end
								`SRA : begin
									logicout <= (reg1_i >> shiftbits) | ({32{1'b1}} << (`RegWidth - shiftbits));
								end
							endcase						
						end
						`OR : begin
							logicout <= reg1_i | reg2_i;
						end
						`AND : begin
							logicout <= reg1_i & reg2_i;
						end
					endcase
				end




						


						


						


						


						


						


						



				default: begin
					logicout <= `ZeroWord;
				end
			endcase
		end
	end
	
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			aluop_o <= `NOP;
			alufunct3_o <= `NOP_FUNCT3;
			me_o <= `MemDisable;
			maddr_o <= `NopMem;
			wreg_o <= `WriteDisable;
			wd_o <= `NopRegAddr;
			wdata_o <= `ZeroWord;		
		end
		else begin
			aluop_o <= aluop_i;
			alufunct3_o <= alufunct3_i;
			me_o <= me;
			maddr_o <= maddr;
			wreg_o <= wreg_i;
			wd_o <= wd_i;
			wdata_o <= logicout;
		end
	end
	

	always @ (*) begin 
		if(rst == `RstEnable) begin
			wreg_f <= `WriteDisable;
			wd_f <= `NopRegAddr;
			wdata_f <= `ZeroWord;
		end
		else begin
			if(aluop_i == `LOAD) begin
				wreg_f <= `WriteDisable;
			end
			else begin
				wreg_f <= wreg_o;
			end	
			wd_f <= wd_o;
			wdata_f <= wdata_o;		
		end
	end

endmodule