data/full_repos/permissive/136794488/source/pipemem.v
1: b"%Error: data/full_repos/permissive/136794488/source/pipemem.v:19: Cannot find file containing module: 'mux2x32'\n  mux2x32  mem_io_dataout_mux(mem_dataout,io_read_data,malu[7],mmo); \n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136794488/source,data/full_repos/permissive/136794488/mux2x32\n             data/full_repos/permissive/136794488/source,data/full_repos/permissive/136794488/mux2x32.v\n             data/full_repos/permissive/136794488/source,data/full_repos/permissive/136794488/mux2x32.sv\n             mux2x32\n             mux2x32.v\n             mux2x32.sv\n             obj_dir/mux2x32\n             obj_dir/mux2x32.v\n             obj_dir/mux2x32.sv\n%Error: data/full_repos/permissive/136794488/source/pipemem.v:23: Cannot find file containing module: 'lpm_ram_dq_dram'\n  lpm_ram_dq_dram  dram(malu[6:2],dmem_clk,mb,write_datamem_enable,mem_dataout );     \n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136794488/source/pipemem.v:26: Cannot find file containing module: 'io_output_reg'\n    io_output_reg io_output_regx2 (malu,mb,write_io_output_reg_enable, dmem_clk,resetn,out_port0,out_port1,out_port2); \n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136794488/source/pipemem.v:28: Cannot find file containing module: 'io_input_reg'\n    io_input_reg io_input_regx2(malu,dmem_clk,io_read_data,in_port0,in_port1); \n    ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module pipemem ( clock,mem_clk,resetn,mwmem,malu,mb,mmo,
						out_port0,out_port1,out_port2,in_port0,in_port1);
    
	 input           clock,mem_clk,resetn,mwmem;
	 input  [31:0]   malu,mb;
	 output [31:0]   mmo;    
		 
	 input  [31:0]   in_port0,in_port1;   
	 output [31:0]   out_port0,out_port1,out_port2;      
    
	 wire [31:0]     mmo;    
	 wire            dmem_clk = mem_clk & ( ~ clock) ;            
	 wire [31:0]     mem_dataout,io_read_data;   
	 
	 wire            write_enable = mwmem & ~clock;
	 wire            write_datamem_enable = write_enable & ( ~ malu[7]);
	 wire            write_io_output_reg_enable = write_enable & ( malu[7]);
	 
	 mux2x32  mem_io_dataout_mux(mem_dataout,io_read_data,malu[7],mmo); 



	 lpm_ram_dq_dram  dram(malu[6:2],dmem_clk,mb,write_datamem_enable,mem_dataout );     


    io_output_reg io_output_regx2 (malu,mb,write_io_output_reg_enable, dmem_clk,resetn,out_port0,out_port1,out_port2); 
	  
    io_input_reg io_input_regx2(malu,dmem_clk,io_read_data,in_port0,in_port1); 
	 
endmodule
module pipemem ( clock,mem_clk,resetn,mwmem,malu,mb,mmo,
						out_port0,out_port1,out_port2,in_port0,in_port1);

    
	 input           clock,mem_clk,resetn,mwmem;
	 input  [31:0]   malu,mb;
	 output [31:0]   mmo;    
		 
	 input  [31:0]   in_port0,in_port1;   
	 output [31:0]   out_port0,out_port1,out_port2;      
    
	 wire [31:0]     mmo;    
	 wire            dmem_clk = mem_clk & ( ~ clock) ;            
	 wire [31:0]     mem_dataout,io_read_data;   
	 
	 wire            write_enable = mwmem & ~clock;
	 wire            write_datamem_enable = write_enable & ( ~ malu[7]);
	 wire            write_io_output_reg_enable = write_enable & ( malu[7]);
	 
	 mux2x32  mem_io_dataout_mux(mem_dataout,io_read_data,malu[7],mmo); 



	 lpm_ram_dq_dram  dram(malu[6:2],dmem_clk,mb,write_datamem_enable,mem_dataout );     


    io_output_reg io_output_regx2 (malu,mb,write_io_output_reg_enable, dmem_clk,resetn,out_port0,out_port1,out_port2); 
	  
    io_input_reg io_input_regx2(malu,dmem_clk,io_read_data,in_port0,in_port1); 
	 
endmodule