data/full_repos/permissive/205055389/test/tkgate/clock.v
 line:20: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205055389/test/tkgate/clock.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/tkgate/clock.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/tkgate/clock.v:19: Unsupported: Ignoring delay on this delayed statement.\ninitial #0\n        ^\n%Warning-INFINITELOOP: data/full_repos/permissive/205055389/test/tkgate/clock.v:21: Infinite loop (condition always true)\n                                                                                  : ... In instance main.g0\n    forever\n    ^~~~~~~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module _GGCLOCK_P100_0_50 (Z);
output Z;
reg Z;

initial #0
  begin 
    forever
      begin
        Z = 1'b0;
        #50;
        Z = 1'b1;
        #50;
      end
   end

endmodule
module _GGCLOCK_P100_0_50 (Z);

output Z;
reg Z;

initial #0
  begin 
    forever
      begin
        Z = 1'b0;
        #50;
        Z = 1'b1;
        #50;
      end
   end

endmodule