data/full_repos/permissive/163494071/count_num/test3/test3.v
data/verilator_xmls/d3ac263f-b60b-4fe5-93a8-9c6962f4ceb3.xml
module test3(clk,rst,rst_num,seg,seg_on);
	input clk;
	input rst;
	input rst_num;
	output reg[7:0] seg;
	output reg[1:0] seg_on;
	reg[7:0] seg_num[15:0];
	reg onMSChange;
	reg[7:0] sum;
	reg[4:0] shake_cnt;
	reg[16:0] clk_count;	
	reg[16:0] cnt_num;
	reg mode;
	initial
		begin
		seg_num[0] <= 8'b11111100;
		seg_num[1] <= 8'b01100000;
		seg_num[2] <= 8'b11011010;
		seg_num[3] <= 8'b11110010;
		seg_num[4] <= 8'b01100110;
		seg_num[5] <= 8'b10110110;
		seg_num[6] <= 8'b10111110;
		seg_num[7] <= 8'b11100000;
		seg_num[8] <= 8'b11111110;
		seg_num[9] <= 8'b11110110;
		seg_num[10] <= 8'b11101110;
		seg_num[11] <= 8'b00111110;
		seg_num[12] <= 8'b10011100;
		seg_num[13] <= 8'b01111010;
		seg_num[14] <= 8'b10011110;
		seg_num[15] <= 8'b10001110;
		seg <= 8'b0;
		seg_on <= 2'b10;
		clk_count <= 0;
		onMSChange <= 0;


		shake_cnt <= 0;
		sum <= 8'd0;
		cnt_num <= 13000;
		mode <= 0;
		end
		
	always@(posedge clk)
		
			begin
			if(clk_count >= 44800)
				begin
				clk_count <= 0;
				onMSChange <= 1;
				end
			else
				begin
				clk_count <= clk_count + 1;
				onMSChange <= 0;
				end
			end

	always@(posedge onMSChange)
		begin

			if(rst_num)
				begin
				if(shake_cnt <= 10)
					begin
					shake_cnt <= shake_cnt + 1;
					end
				if(shake_cnt == 10)
					begin
					sum <= sum + 8'd1;
					end
				end
			else
				begin
				shake_cnt <= 0;
				end
		if(sum[3:0] >= 4'd10)
			begin
			sum[7:4] <= sum[7:4] + 1;
			sum[3:0] <= sum[3:0] - 10;
			end
		if(sum[7:4] == 4'd9)
			begin
			sum <= 8'd0;
			end
		if(rst)
			begin
			sum <= 8'd0;
			end
		
		

			if(seg_on == 2'b01)
				begin
				seg_on <= 2'b10;
				end
			else
				begin
				seg_on <= seg_on << 1 | 1;
				end
			
			
				if(seg_on == 2'b10)
					begin
					seg <= seg_num[sum[7:4]];
					end
				else if(seg_on == 2'b01)
					begin
					seg <= seg_num[sum[3:0]];
					end
		
		end
endmodule
module test3(clk,rst,rst_num,seg,seg_on);

	input clk;
	input rst;
	input rst_num;
	output reg[7:0] seg;
	output reg[1:0] seg_on;
	reg[7:0] seg_num[15:0];
	reg onMSChange;
	reg[7:0] sum;
	reg[4:0] shake_cnt;
	reg[16:0] clk_count;	
	reg[16:0] cnt_num;
	reg mode;
	initial
		begin
		seg_num[0] <= 8'b11111100;
		seg_num[1] <= 8'b01100000;
		seg_num[2] <= 8'b11011010;
		seg_num[3] <= 8'b11110010;
		seg_num[4] <= 8'b01100110;
		seg_num[5] <= 8'b10110110;
		seg_num[6] <= 8'b10111110;
		seg_num[7] <= 8'b11100000;
		seg_num[8] <= 8'b11111110;
		seg_num[9] <= 8'b11110110;
		seg_num[10] <= 8'b11101110;
		seg_num[11] <= 8'b00111110;
		seg_num[12] <= 8'b10011100;
		seg_num[13] <= 8'b01111010;
		seg_num[14] <= 8'b10011110;
		seg_num[15] <= 8'b10001110;
		seg <= 8'b0;
		seg_on <= 2'b10;
		clk_count <= 0;
		onMSChange <= 0;


		shake_cnt <= 0;
		sum <= 8'd0;
		cnt_num <= 13000;
		mode <= 0;
		end
		
	always@(posedge clk)
		
			begin
			if(clk_count >= 44800)
				begin
				clk_count <= 0;
				onMSChange <= 1;
				end
			else
				begin
				clk_count <= clk_count + 1;
				onMSChange <= 0;
				end
			end

	always@(posedge onMSChange)
		begin

			if(rst_num)
				begin
				if(shake_cnt <= 10)
					begin
					shake_cnt <= shake_cnt + 1;
					end
				if(shake_cnt == 10)
					begin
					sum <= sum + 8'd1;
					end
				end
			else
				begin
				shake_cnt <= 0;
				end
		if(sum[3:0] >= 4'd10)
			begin
			sum[7:4] <= sum[7:4] + 1;
			sum[3:0] <= sum[3:0] - 10;
			end
		if(sum[7:4] == 4'd9)
			begin
			sum <= 8'd0;
			end
		if(rst)
			begin
			sum <= 8'd0;
			end
		
		

			if(seg_on == 2'b01)
				begin
				seg_on <= 2'b10;
				end
			else
				begin
				seg_on <= seg_on << 1 | 1;
				end
			
			
				if(seg_on == 2'b10)
					begin
					seg <= seg_num[sum[7:4]];
					end
				else if(seg_on == 2'b01)
					begin
					seg <= seg_num[sum[3:0]];
					end
		
		end
endmodule