data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/DMemModule.v
1: b'%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/DMemModule.v:58: Cannot find file containing module: \'DMem\'\nDMem u_DMem(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/DMem\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/DMem.v\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/DMem.sv\n             DMem\n             DMem.v\n             DMem.sv\n             obj_dir/DMem\n             obj_dir/DMem.v\n             obj_dir/DMem.sv\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/DMemModule.v:181: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s UNSIGNED generates 7 bits.\n                                                                                                             : ... In instance DMemModule\nassign outdata = which==2\'h1 ? $unsigned(local_sw) : (which==2\'h2 ? douta : local_alu_ans);\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module DMemModule(
	input clk,
	input rst_n,
	
	
	input dmem_stall,
	input dmem_bubble,
	
	input [31:0] pc,
	input [31:0] ir,
	
	input [4:0] regaddr3,
	input [31:0] alu_ans,
	
	input [31:0] swdata,
	
	input [5:0] optype,

	input [6:0] sw,

	output reg [5:0] to_optype,
	output reg [4:0] to_regaddr3,
	
	output [31:0] outdata,
	
	output reg [31:0] smg,
	output reg [7:0] led
);



wire we;

wire [31:0] douta;

assign we = optype==6'h14 ? 1 : 0;

DMem u_DMem(
	clk,
	we,
	alu_ans[6:2],
	swdata,
	douta
);


reg [6:0] local_sw;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		smg<=32'h0;
		led<=8'hFD;
		local_sw<=7'h0;
	end
	else
	begin
		local_sw<=sw;
		if(we && alu_ans==32'h78 )
		begin
			smg<=swdata;
		end
		else if(we && alu_ans==32'h7C )
		begin
			led<=swdata[7:0];
		end
		else
		begin
		end
	end
end




reg [31:0] temp_aluans;
always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
		temp_aluans<=32'hCCCC_CCCC;
	else if(!dmem_stall)
		temp_aluans<=alu_ans;
	else
	begin
	end
end




reg [31:0] local_alu_ans;
reg [5:0] local_optype;
always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		local_alu_ans<=32'h0;
		local_optype<=6'h3f;
	end
	else
	begin
		local_alu_ans<=alu_ans;
		local_optype<=optype;
	end
end


reg [1:0] which;
always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
		which<=2'h0;
	else
		if(optype==6'h13 && alu_ans==32'h74)
			which<=2'h1;
		else if(optype==6'h13)
			which<=2'h2;
		else
			which<=2'h3;
end



assign outdata = which==2'h1 ? $unsigned(local_sw) : (which==2'h2 ? douta : local_alu_ans);






always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		to_optype<=6'h3F;
		to_regaddr3<=5'h0;
	end
	else if(dmem_bubble)
	begin
		to_optype<=6'h3F;
	end
	else if(!dmem_stall)
	begin
		to_optype<=optype;
		to_regaddr3<=regaddr3;
	end
	else
	begin
	end
end

endmodule
module DMemModule(
	input clk,
	input rst_n,
	
	
	input dmem_stall,
	input dmem_bubble,
	
	input [31:0] pc,
	input [31:0] ir,
	
	input [4:0] regaddr3,
	input [31:0] alu_ans,
	
	input [31:0] swdata,
	
	input [5:0] optype,

	input [6:0] sw,

	output reg [5:0] to_optype,
	output reg [4:0] to_regaddr3,
	
	output [31:0] outdata,
	
	output reg [31:0] smg,
	output reg [7:0] led
);




wire we;

wire [31:0] douta;

assign we = optype==6'h14 ? 1 : 0;

DMem u_DMem(
	clk,
	we,
	alu_ans[6:2],
	swdata,
	douta
);


reg [6:0] local_sw;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		smg<=32'h0;
		led<=8'hFD;
		local_sw<=7'h0;
	end
	else
	begin
		local_sw<=sw;
		if(we && alu_ans==32'h78 )
		begin
			smg<=swdata;
		end
		else if(we && alu_ans==32'h7C )
		begin
			led<=swdata[7:0];
		end
		else
		begin
		end
	end
end




reg [31:0] temp_aluans;
always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
		temp_aluans<=32'hCCCC_CCCC;
	else if(!dmem_stall)
		temp_aluans<=alu_ans;
	else
	begin
	end
end




reg [31:0] local_alu_ans;
reg [5:0] local_optype;
always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		local_alu_ans<=32'h0;
		local_optype<=6'h3f;
	end
	else
	begin
		local_alu_ans<=alu_ans;
		local_optype<=optype;
	end
end


reg [1:0] which;
always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
		which<=2'h0;
	else
		if(optype==6'h13 && alu_ans==32'h74)
			which<=2'h1;
		else if(optype==6'h13)
			which<=2'h2;
		else
			which<=2'h3;
end



assign outdata = which==2'h1 ? $unsigned(local_sw) : (which==2'h2 ? douta : local_alu_ans);






always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		to_optype<=6'h3F;
		to_regaddr3<=5'h0;
	end
	else if(dmem_bubble)
	begin
		to_optype<=6'h3F;
	end
	else if(!dmem_stall)
	begin
		to_optype<=optype;
		to_regaddr3<=regaddr3;
	end
	else
	begin
	end
end

endmodule