data/full_repos/permissive/212394344/MaiModule_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/212394344/MaiModule_TB.v:71: Unsupported: Ignoring delay on this delayed statement.\n #200; reset = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212394344/MaiModule_TB.v:72: Unsupported: Ignoring delay on this delayed statement.\n #500; reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/MaiModule_TB.v:76: Unsupported: Ignoring delay on this delayed statement.\n #500 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/212394344/MaiModule_TB.v:47: Cannot find file containing module: \'MainModule\'\n MainModule uut (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/MainModule\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/MainModule.v\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/MainModule.sv\n             MainModule\n             MainModule.v\n             MainModule.sv\n             obj_dir/MainModule\n             obj_dir/MainModule.v\n             obj_dir/MainModule.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MaiModule_TB;


	reg [7:0] data_in;
	reg clk;
	reg interrupt;
	reg reset;


	wire [7:0] A;
	wire [7:0] B;
	wire [7:0] Current_Address;
	wire [7:0] ans_ex;
	wire [7:0] ans_dm;
	wire [7:0] ans_wb;
	wire [1:0] mux_sel_A;
	wire [1:0] mux_sel_B;
	wire imm_sel;
	wire [23:0] ins;
	wire [7:0] data_out;


	MainModule uut (
		.A(A), 
		.B(B), 
		.Current_Address(Current_Address), 
		.ans_ex(ans_ex), 
		.ans_dm(ans_dm), 
		.ans_wb(ans_wb), 
		.mux_sel_A(mux_sel_A), 
		.mux_sel_B(mux_sel_B), 
		.imm_sel(imm_sel), 
		.ins(ins), 
		.data_out(data_out), 
		.data_in(data_in), 
		.clk(clk), 
		.interrupt(interrupt), 
		.reset(reset)
	);

	initial
	begin
	data_in = 0;
	interrupt = 0;
	clk = 0;
	reset = 1;
	#200; reset = 0;
	#500; reset = 1;
	end
	
	always
	#500 clk = ~clk;
	
endmodule
module MaiModule_TB;



	reg [7:0] data_in;
	reg clk;
	reg interrupt;
	reg reset;


	wire [7:0] A;
	wire [7:0] B;
	wire [7:0] Current_Address;
	wire [7:0] ans_ex;
	wire [7:0] ans_dm;
	wire [7:0] ans_wb;
	wire [1:0] mux_sel_A;
	wire [1:0] mux_sel_B;
	wire imm_sel;
	wire [23:0] ins;
	wire [7:0] data_out;


	MainModule uut (
		.A(A), 
		.B(B), 
		.Current_Address(Current_Address), 
		.ans_ex(ans_ex), 
		.ans_dm(ans_dm), 
		.ans_wb(ans_wb), 
		.mux_sel_A(mux_sel_A), 
		.mux_sel_B(mux_sel_B), 
		.imm_sel(imm_sel), 
		.ins(ins), 
		.data_out(data_out), 
		.data_in(data_in), 
		.clk(clk), 
		.interrupt(interrupt), 
		.reset(reset)
	);

	initial
	begin
	data_in = 0;
	interrupt = 0;
	clk = 0;
	reset = 1;
	#200; reset = 0;
	#500; reset = 1;
	end
	
	always
	#500 clk = ~clk;
	
endmodule