data/full_repos/permissive/169661644/hw3_2/fullAdder_1b.v
data/verilator_xmls/e1149fcd-e131-4f1b-b49b-3d8a0e4c16ea.xml
module fullAdder_1b(A, B, C_in, S, C_out);
    input  A, B;
	input  C_in;
    output S;
    output C_out;



endmodule
module fullAdder_1b(A, B, C_in, S, C_out);

    input  A, B;
	input  C_in;
    output S;
    output C_out;



endmodule