data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_buf_rv.sv
1: b"%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_buf_rv.sv:38: Cannot find file containing module: 'stream_buf_r'\n  stream_buf_r #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_buf_r\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_buf_r.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_buf_r.sv\n             stream_buf_r\n             stream_buf_r.v\n             stream_buf_r.sv\n             obj_dir/stream_buf_r\n             obj_dir/stream_buf_r.v\n             obj_dir/stream_buf_r.sv\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_buf_rv.sv:50: Cannot find file containing module: 'stream_buf_v'\n  stream_buf_v #(\n  ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module stream_buf_rv #(
  parameter DataBits = 8)
  ( input                 clk,
    input                 rst,

    input                 in_valid,
    output                in_ready,
    input [DataBits-1:0]  in_data,

    output                out_valid,
    input                 out_ready,
    output [DataBits-1:0] out_data
);

  wire                bufr_valid, bufr_ready;
  wire [DataBits-1:0] bufr_data;
  stream_buf_r #(
    .DataBits(DataBits))
  bufr(
    .clk      (clk),
    .rst      (rst),
    .in_valid (in_valid),
    .in_ready (in_ready),
    .in_data  (in_data),
    .out_valid(bufr_valid),
    .out_ready(bufr_ready),
    .out_data (bufr_data));

  stream_buf_v #(
    .DataBits (DataBits))
  bufv(
    .clk      (clk),
    .rst      (rst),
    .in_valid (bufr_valid),
    .in_ready (bufr_ready),
    .in_data  (bufr_data),
    .out_valid(out_valid),
    .out_ready(out_ready),
    .out_data (out_data));

endmodule
module stream_buf_rv #(
  parameter DataBits = 8)
  ( input                 clk,
    input                 rst,

    input                 in_valid,
    output                in_ready,
    input [DataBits-1:0]  in_data,

    output                out_valid,
    input                 out_ready,
    output [DataBits-1:0] out_data
);


  wire                bufr_valid, bufr_ready;
  wire [DataBits-1:0] bufr_data;
  stream_buf_r #(
    .DataBits(DataBits))
  bufr(
    .clk      (clk),
    .rst      (rst),
    .in_valid (in_valid),
    .in_ready (in_ready),
    .in_data  (in_data),
    .out_valid(bufr_valid),
    .out_ready(bufr_ready),
    .out_data (bufr_data));

  stream_buf_v #(
    .DataBits (DataBits))
  bufv(
    .clk      (clk),
    .rst      (rst),
    .in_valid (bufr_valid),
    .in_ready (bufr_ready),
    .in_data  (bufr_data),
    .out_valid(out_valid),
    .out_ready(out_ready),
    .out_data (out_data));

endmodule