data/full_repos/permissive/100331186/tarea3/modulos/mux.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:70: Unsupported: Ignoring delay on this delayed statement.\n      #(tdismin:tdismax:tdismax) y = 1\'bz;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #(tpdmin:tpdmax:tpdmax) y = aRet[s];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #(tpdmin:tpdmax:tpdmax) y = aRet[s];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #tpin aRet = a;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:39: Duplicate declaration of signal: \'s\'\n                                                                    : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire s;\n       ^\n        data/full_repos/permissive/100331186/tarea3/modulos/mux.v:34: ... Location of original declaration\n  input s,        \n        ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:40: Duplicate declaration of signal: \'a\'\n  wire [1:0] a;\n             ^\n        data/full_repos/permissive/100331186/tarea3/modulos/mux.v:35: ... Location of original declaration\n  input [1:0] a,  \n              ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:41: Duplicate declaration of signal: \'notoe\'\n  wire notoe;\n       ^~~~~\n        data/full_repos/permissive/100331186/tarea3/modulos/mux.v:36: ... Location of original declaration\n  input notoe,    \n        ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/mux.v:42: Duplicate declaration of signal: \'y\'\n  reg y;\n      ^\n        data/full_repos/permissive/100331186/tarea3/modulos/mux.v:37: ... Location of original declaration\n  output y\n         ^\n%Error: Exiting due to 4 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux(
  input s,
  input [1:0] a,
  input notoe,
  output y
);
  wire s;
  wire [1:0] a;
  wire notoe;
  reg y;

  parameter tpin = 0.25;


  parameter tpdmin = 1.8;
  parameter tpdmax = 5.3;


  parameter tenmin = 2;
  parameter tenmax = 5.3;


  parameter tdismin = 1.6;
  parameter tdismax = 5.5;

  parameter Vcc = 3.3;
  parameter Cl = 0.05;

  integer c;
  initial c = 0;


  reg [1:0] aRet;

  always @ (*) begin

    if (notoe) begin
      #(tdismin:tdismax:tdismax) y = 1'bz;

    end else begin

      if (a == 1'bz) begin
        #(tpdmin:tpdmax:tpdmax) y = aRet[s];

      end else begin
        #(tpdmin:tpdmax:tpdmax) y = aRet[s];
      end
    end
  end


  always @ (a) begin
    #tpin aRet = a;
  end


  always @ (y) begin
    c = c+1;

  end
endmodule
module mux(
  input s,
  input [1:0] a,
  input notoe,
  output y
);

  wire s;
  wire [1:0] a;
  wire notoe;
  reg y;

  parameter tpin = 0.25;


  parameter tpdmin = 1.8;
  parameter tpdmax = 5.3;


  parameter tenmin = 2;
  parameter tenmax = 5.3;


  parameter tdismin = 1.6;
  parameter tdismax = 5.5;

  parameter Vcc = 3.3;
  parameter Cl = 0.05;

  integer c;
  initial c = 0;


  reg [1:0] aRet;

  always @ (*) begin

    if (notoe) begin
      #(tdismin:tdismax:tdismax) y = 1'bz;

    end else begin

      if (a == 1'bz) begin
        #(tpdmin:tpdmax:tpdmax) y = aRet[s];

      end else begin
        #(tpdmin:tpdmax:tpdmax) y = aRet[s];
      end
    end
  end


  always @ (a) begin
    #tpin aRet = a;
  end


  always @ (y) begin
    c = c+1;

  end
endmodule