data/full_repos/permissive/193073090/ServoEdition3_tb.v
 line:51: before: "("
1: b'%Error: data/full_repos/permissive/193073090/ServoEdition3_tb.v:51: syntax error, unexpected \'@\'\n    repeat(2) @(posedge clock);                         \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/193073090/ServoEdition3_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #(HALF_CLOCK_PERIOD);           \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module ServoEdition3_tb;




localparam NUM_CYCLES = 5000000;
localparam CLOCK_FREQ = 50000000;
localparam S0_STATE   = 8'b00000000;
localparam S1_STATE   = 8'b00011111;
localparam S2_STATE   = 8'b00111111;
localparam S3_STATE   = 8'b01011111;
localparam S4_STATE   = 8'b11111111;



reg  clock;
reg  clock_enable;
reg  reset;
reg [7:0] pwm_switch;


wire pwm_output;




ServoEdition3 ServoEdition3_dut(
   .clock      ( clock      ),
   .reset    ( reset      ),
	.clock_enable (clock_enable),
   .pwm_switch    (pwm_switch),
   .pwm_output  (pwm_output)
);





initial begin
	clock_enable = 1'b1;
end

initial begin
    $display("%d ns\tSimulation Started",$time);
    reset = 1'b1;
    repeat(2) @(posedge clock);
    reset = 1'b0;
    $display("%d ns\tInitialisation Complete",$time);
end





initial begin

pwm_switch = 8'd255;


end

















initial begin
    clock = 1'b0;
end



real HALF_CLOCK_PERIOD = (1000000000.0 / $itor(CLOCK_FREQ)) / 2.0;


integer half_cycles = 0;
always begin

    #(HALF_CLOCK_PERIOD);
    clock = ~clock;
    half_cycles = half_cycles + 1;
    

    if (half_cycles == (2*NUM_CYCLES)) begin 

		half_cycles = 0;
        $stop;

    end
end

endmodule
module ServoEdition3_tb;





localparam NUM_CYCLES = 5000000;
localparam CLOCK_FREQ = 50000000;
localparam S0_STATE   = 8'b00000000;
localparam S1_STATE   = 8'b00011111;
localparam S2_STATE   = 8'b00111111;
localparam S3_STATE   = 8'b01011111;
localparam S4_STATE   = 8'b11111111;



reg  clock;
reg  clock_enable;
reg  reset;
reg [7:0] pwm_switch;


wire pwm_output;




ServoEdition3 ServoEdition3_dut(
   .clock      ( clock      ),
   .reset    ( reset      ),
	.clock_enable (clock_enable),
   .pwm_switch    (pwm_switch),
   .pwm_output  (pwm_output)
);





initial begin
	clock_enable = 1'b1;
end

initial begin
    $display("%d ns\tSimulation Started",$time);
    reset = 1'b1;
    repeat(2) @(posedge clock);
    reset = 1'b0;
    $display("%d ns\tInitialisation Complete",$time);
end





initial begin

pwm_switch = 8'd255;


end

















initial begin
    clock = 1'b0;
end



real HALF_CLOCK_PERIOD = (1000000000.0 / $itor(CLOCK_FREQ)) / 2.0;


integer half_cycles = 0;
always begin

    #(HALF_CLOCK_PERIOD);
    clock = ~clock;
    half_cycles = half_cycles + 1;
    

    if (half_cycles == (2*NUM_CYCLES)) begin 

		half_cycles = 0;
        $stop;

    end
end

endmodule