data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v
1: b'%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:91: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'add1_out\' generates 13 bits.\n                                                                                    : ... In instance adders\n                    adder19_regNext=add1_out;\n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:92: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'add2_out\' generates 13 bits.\n                                                                                    : ... In instance adders\n                    adder20_regNext=add2_out;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:93: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'add3_out\' generates 13 bits.\n                                                                                    : ... In instance adders\n                    adder21_regNext=add3_out;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:94: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'add4_out\' generates 13 bits.\n                                                                                    : ... In instance adders\n                    adder24_regNext=add4_out;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:95: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'add5_out\' generates 13 bits.\n                                                                                    : ... In instance adders\n                    adder25_regNext=add5_out;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:96: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'add6_out\' generates 13 bits.\n                                                                                    : ... In instance adders\n                    adder26_regNext=add6_out;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:98: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_0\' generates 8 bits.\n                                                                                    : ... In instance adders\n                    add1_in1=input_0;    \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:99: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_1\' generates 8 bits.\n                                                                                    : ... In instance adders\n                    add1_in2=input_1;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:100: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_2\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add2_in1=input_2;    \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:101: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_3\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add2_in2=input_3;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:102: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_4\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add3_in1=input_4;    \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:103: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_5\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add3_in2=input_5;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:104: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_6\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add4_in1=input_6;    \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:105: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_7\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add4_in2=input_7;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:106: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_8\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add5_in1=input_8;    \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:107: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_9\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add5_in2=input_9;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:108: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_10\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add6_in1=input_10;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:109: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_11\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add6_in2=input_11;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:112: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'add1_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    adder22_regNext=add1_out;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:113: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'add2_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    adder23_regNext=add2_out;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:114: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'add3_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    adder27_regNext=add3_out;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:115: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'add4_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    adder28_regNext=add4_out;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:119: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_12\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add1_in1=input_12;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:120: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_13\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add1_in2=input_13;  \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:121: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_14\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add2_in1=input_14;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:122: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_15\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add2_in2=input_15;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:123: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_16\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add3_in1=input_16;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:124: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_17\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add3_in2=input_17;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:125: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_18\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add4_in1=input_18;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:126: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_19\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add4_in2=input_19;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:127: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_20\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add5_in1=input_20;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:128: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_21\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add5_in2=input_21;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:129: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_22\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add6_in1=input_22;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:130: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_23\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add6_in2=input_23;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:133: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_24\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add1_in1=input_24;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:134: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_25\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add1_in2=input_25;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:135: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_26\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add2_in1=input_26;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:136: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_27\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add2_in2=input_27;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:137: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_28\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add3_in1=input_28;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:138: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_29\' generates 8 bits.\n                                                                                     : ... In instance adders\n                    add3_in2=input_29;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:140: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add1_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add4_in1=add1_out;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:141: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add2_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add4_in2=add2_out;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:142: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add3_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add5_in1=add3_out;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:143: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add4_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add5_in2=add4_out;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:144: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add5_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add6_in1=add5_out;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:145: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add6_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add6_in2=add6_out;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:149: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add1_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add1_in1=add1_out;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:150: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add2_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add1_in2=add2_out;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:151: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add3_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add2_in1=add3_out;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:152: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add4_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add2_in2=add4_out;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:153: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add5_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add3_in1=add5_out;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:154: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add6_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add3_in2=add6_out;                    \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:157: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder18_reg\' generates 9 bits.\n                                                                                     : ... In instance adders\n                        add4_in1=adder18_reg;   \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:158: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder19_reg\' generates 9 bits.\n                                                                                     : ... In instance adders\n                        add4_in2=adder19_reg;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:159: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder20_reg\' generates 9 bits.\n                                                                                     : ... In instance adders\n                        add5_in1=adder20_reg;   \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:160: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder21_reg\' generates 9 bits.\n                                                                                     : ... In instance adders\n                        add5_in2=adder21_reg;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:161: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder22_reg\' generates 9 bits.\n                                                                                     : ... In instance adders\n                        add6_in1=adder22_reg;   \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:162: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder15_reg\' generates 8 bits.\n                                                                                     : ... In instance adders\n                        add6_in2=adder15_reg;                    \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:166: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'add3_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    adder15_regNext=add3_out;    \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:167: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'add6_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    adder18_regNext=add6_out;    \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:170: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add1_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add1_in1=add1_out;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:171: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add2_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add1_in2=add2_out;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:172: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add4_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add2_in1=add4_out;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:173: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'add5_out\' generates 13 bits.\n                                                                                     : ... In instance adders\n                    add2_in2=add5_out;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:176: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder23_reg\' generates 10 bits.\n                                                                                     : ... In instance adders\n                        add3_in1=adder23_reg;   \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:177: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder24_reg\' generates 10 bits.\n                                                                                     : ... In instance adders\n                        add3_in2=adder24_reg;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:178: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder25_reg\' generates 10 bits.\n                                                                                     : ... In instance adders\n                        add4_in1=adder25_reg;   \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:179: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder26_reg\' generates 10 bits.\n                                                                                     : ... In instance adders\n                        add4_in2=adder26_reg;                    \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:182: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder27_reg\' generates 11 bits.\n                                                                                     : ... In instance adders\n                        add5_in1=adder27_reg;   \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/201196900/Verilog_5CycleAdder/adders.v:183: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'adder28_reg\' generates 11 bits.\n                                                                                     : ... In instance adders\n                        add5_in2=adder28_reg;      \n                                ^\n%Error: Exiting due to 70 warning(s)\n'
module FA_13Bit2Cycle(input clk, input rst, input [11:0] in1, input [11:0] in2, output reg [12:0] out);
reg [12:0] accumulator, accumulatorNext, outNext;
always @(posedge clk)begin
    accumulator <= accumulatorNext;
    out <= outNext;
end
always @(*)begin
    accumulatorNext=in1+in2;
    outNext=accumulator;    
end
endmodule
module FA_13Bit2Cycle(input clk, input rst, input [11:0] in1, input [11:0] in2, output reg [12:0] out);

reg [12:0] accumulator, accumulatorNext, outNext;
always @(posedge clk)begin
    accumulator <= accumulatorNext;
    out <= outNext;
end
always @(*)begin
    accumulatorNext=in1+in2;
    outNext=accumulator;    
end
endmodule