data/full_repos/permissive/150012894/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/150012894/ALU.v:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                             : ... In instance ALU\n 3\'b010 : out = scr1 < scr2;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/150012894/ALU.v:18: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                             : ... In instance ALU\n 3\'b011 : out = diff[0];\n              ^\n%Error: Exiting due to 2 warning(s)\n'
module ALU (
	input signed [31:0] scr1,
	input [31:0] scr2,
	input [2:0] op,
	input op_extend,
	output reg [31:0] out
);

wire [31:0] diff = scr1 - scr2;

always @(*) case(op)
	3'b000 : out = op_extend ? diff : scr1 + scr2;
	3'b001 : out = scr1 << scr2[4:0];
	3'b010 : out = scr1 < scr2;
	3'b011 : out = diff[0];
	3'b100 : out = scr1 ^ scr2;
	3'b101 : out = op_extend ? scr1 >>> scr2[4:0] :  scr1 >> scr2[4:0] ;
	3'b110 : out = scr1 | scr2;
	3'b111 : out = scr1 & scr2;

endcase


endmodule
module ALU (
	input signed [31:0] scr1,
	input [31:0] scr2,
	input [2:0] op,
	input op_extend,
	output reg [31:0] out
);


wire [31:0] diff = scr1 - scr2;

always @(*) case(op)
	3'b000 : out = op_extend ? diff : scr1 + scr2;
	3'b001 : out = scr1 << scr2[4:0];
	3'b010 : out = scr1 < scr2;
	3'b011 : out = diff[0];
	3'b100 : out = scr1 ^ scr2;
	3'b101 : out = op_extend ? scr1 >>> scr2[4:0] :  scr1 >> scr2[4:0] ;
	3'b110 : out = scr1 | scr2;
	3'b111 : out = scr1 & scr2;

endcase


endmodule