data/full_repos/permissive/156506242/src/seven_seg_display.v
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data/verilator_xmls/f59cb922-4ce4-4044-9edf-376d71cb4c2d.xml
module seven_seg_display(
    input [3:0] enable_input,
    output reg [7:0] AN
    );
    
    always@(enable_input) begin
        case(enable_input)
            4'b0001: AN = 8'b1111_1110;
            4'b0010: AN = 8'b1111_1101;
            4'b0100: AN = 8'b1111_1011;
            4'b1000: AN = 8'b1111_0111;
            default: AN = 0;
        endcase
    end
    
endmodule
module seven_seg_display(
    input [3:0] enable_input,
    output reg [7:0] AN
    );

    
    always@(enable_input) begin
        case(enable_input)
            4'b0001: AN = 8'b1111_1110;
            4'b0010: AN = 8'b1111_1101;
            4'b0100: AN = 8'b1111_1011;
            4'b1000: AN = 8'b1111_0111;
            default: AN = 0;
        endcase
    end
    
endmodule