data/full_repos/permissive/135077285/ex_mem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/135077285/ex_mem.v:64: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'aluZeroInput\' generates 1 bits.\n                                                                : ... In instance exMem\n    aluZero <= aluZeroInput;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module exMem(
  input wire clock,



  input wire [2:0] memControlInput,


  input wire [1:0] wbControlInput,


  input wire [31:0] aluResultInput,
  input wire aluZeroInput,
  input wire [31:0] pcInput,
  input wire [31:0] registerDataInput,
  input wire [4:0] writeRegisterInput,




  output reg branch,
  output reg memRead,
  output reg memWrite,


  output reg [1:0] wbControlExMem,


  output reg [31:0] aluResult,
  output reg [31:0] aluZero,
  output reg [31:0] pc,
  output reg [31:0] registerData,
  output reg [4:0] writeRegister
);

  initial begin

    branch <= 0;
    memRead <= 0;
    memWrite <= 0;


    wbControlExMem <= 0;


    aluResult <= 0;
    aluZero <= 0;
    pc <= 0;
    registerData <= 0;
    writeRegister <= 0;
  end

  always @(posedge clock) begin

    branch <= memControlInput[2];
    memRead <= memControlInput[1];
    memWrite <= memControlInput[0];


    wbControlExMem <= wbControlInput;


    aluResult <= aluResultInput;
    aluZero <= aluZeroInput;
    pc <= pcInput;
    registerData <= registerDataInput;
    writeRegister <= writeRegisterInput;
  end


endmodule
module exMem(
  input wire clock,



  input wire [2:0] memControlInput,


  input wire [1:0] wbControlInput,


  input wire [31:0] aluResultInput,
  input wire aluZeroInput,
  input wire [31:0] pcInput,
  input wire [31:0] registerDataInput,
  input wire [4:0] writeRegisterInput,




  output reg branch,
  output reg memRead,
  output reg memWrite,


  output reg [1:0] wbControlExMem,


  output reg [31:0] aluResult,
  output reg [31:0] aluZero,
  output reg [31:0] pc,
  output reg [31:0] registerData,
  output reg [4:0] writeRegister
);


  initial begin

    branch <= 0;
    memRead <= 0;
    memWrite <= 0;


    wbControlExMem <= 0;


    aluResult <= 0;
    aluZero <= 0;
    pc <= 0;
    registerData <= 0;
    writeRegister <= 0;
  end

  always @(posedge clock) begin

    branch <= memControlInput[2];
    memRead <= memControlInput[1];
    memWrite <= memControlInput[0];


    wbControlExMem <= wbControlInput;


    aluResult <= aluResultInput;
    aluZero <= aluZeroInput;
    pc <= pcInput;
    registerData <= registerDataInput;
    writeRegister <= writeRegisterInput;
  end


endmodule