data/full_repos/permissive/137595696/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/137595696/top.v:18: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                             : ... In instance top\n            counter <= 8\'b00000000;\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/137595696/top.v:24: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                             : ... In instance top\n            counter <= 8\'b00000000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/137595696/top.v:30: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                             : ... In instance top\n            counter <= 8\'b00000000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/137595696/top.v:36: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                             : ... In instance top\n            counter <= 8\'b00000000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/137595696/top.v:42: Operator ADD expects 28 bits on the RHS, but RHS\'s CONST \'8\'h1\' generates 8 bits.\n                                                             : ... In instance top\n            counter <= counter + 8\'b00000001;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137595696/top.v:48: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                             : ... In instance top\n            counter <= 8\'b0000000;\n                    ^~\n%Error: Exiting due to 6 warning(s)\n'
module top(
    input CLK100MHZ,
    output reg [3:0] led,
    input [3:0] sw,
    input [3:0] btn
    );
    
    reg [27:0] counter;
    reg [27:0] speed;
    reg on;
    
    always @ (posedge CLK100MHZ)
    begin
        if (btn[0] == 1)
        begin
            counter <= 8'b00000000;
            speed <= 100000000;
            on <= 1'b0;
        end
        else if (btn[1] == 1)
        begin
            counter <= 8'b00000000;
            speed <= 50000000;
            on <= 1'b0;
        end
        else if (btn[2] == 1)
        begin
            counter <= 8'b00000000;
            speed <= 25000000;
            on <= 1'b0;
        end
        else if (btn[3] == 1)
        begin
            counter <= 8'b00000000;
            speed <= 12500000;
            on <= 1'b0;
        end
        else begin

            counter <= counter + 8'b00000001;
        end
        

        if (counter == speed)
        begin
            counter <= 8'b0000000;
            on <= !on;
        end
    

        if (sw[0] == 0)
        begin
            led[0] <= 1'b0;
        end
        else
        begin
            led[0] <= on;
        end
        

        if (sw[1] == 0)
        begin
            led[1] <= 1'b0;
        end
        else
        begin
            led[1] <= 1'b1;
        end
        

        if (sw[2] == 0)
        begin
            led[2] <= 1'b0;
        end
        else
        begin
            led[2] <= 1'b1;
        end
        

        if (sw[3] == 0)
        begin
            led[3] <= 1'b0;
        end
        else
        begin
            led[3] <= 1'b1;
        end
    end
endmodule
module top(
    input CLK100MHZ,
    output reg [3:0] led,
    input [3:0] sw,
    input [3:0] btn
    );

    
    reg [27:0] counter;
    reg [27:0] speed;
    reg on;
    
    always @ (posedge CLK100MHZ)
    begin
        if (btn[0] == 1)
        begin
            counter <= 8'b00000000;
            speed <= 100000000;
            on <= 1'b0;
        end
        else if (btn[1] == 1)
        begin
            counter <= 8'b00000000;
            speed <= 50000000;
            on <= 1'b0;
        end
        else if (btn[2] == 1)
        begin
            counter <= 8'b00000000;
            speed <= 25000000;
            on <= 1'b0;
        end
        else if (btn[3] == 1)
        begin
            counter <= 8'b00000000;
            speed <= 12500000;
            on <= 1'b0;
        end
        else begin

            counter <= counter + 8'b00000001;
        end
        

        if (counter == speed)
        begin
            counter <= 8'b0000000;
            on <= !on;
        end
    

        if (sw[0] == 0)
        begin
            led[0] <= 1'b0;
        end
        else
        begin
            led[0] <= on;
        end
        

        if (sw[1] == 0)
        begin
            led[1] <= 1'b0;
        end
        else
        begin
            led[1] <= 1'b1;
        end
        

        if (sw[2] == 0)
        begin
            led[2] <= 1'b0;
        end
        else
        begin
            led[2] <= 1'b1;
        end
        

        if (sw[3] == 0)
        begin
            led[3] <= 1'b0;
        end
        else
        begin
            led[3] <= 1'b1;
        end
    end
endmodule