data/full_repos/permissive/114459345/srcCache/cache.v
 line:305: before: "begin"
1: b'%Error: data/full_repos/permissive/114459345/srcCache/cache.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:11: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] wvalid_bit,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`ValidBitBus] wvalid_bit,\n                        ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:12: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] waddr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:13: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] data_i,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`ValidBitBus] rvalid_bit,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:17: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] rvalid_bit,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:18: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] raddr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:19: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus] data_o,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`DataAddrBus] miss_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:23: Define or directive not defined: \'`DataAddrBus\'\n output reg[`DataAddrBus] miss_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:25: Define or directive not defined: \'`CacheBus\'\n input wire[`CacheBus] rewrite_data\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:28: Define or directive not defined: \'`PowIndexBus\'\n reg Pres[`PowIndexBus];\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:29: Define or directive not defined: \'`TagBus\'\n reg[`TagBus] Tags[`PowIndexBus];\n     ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`TagBus] Tags[`PowIndexBus];\n            ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:29: Define or directive not defined: \'`PowIndexBus\'\n reg[`TagBus] Tags[`PowIndexBus];\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:30: Define or directive not defined: \'`CacheBus\'\n reg[`CacheBus] data_cache[`PowIndexBus];\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`CacheBus] data_cache[`PowIndexBus];\n              ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:30: Define or directive not defined: \'`PowIndexBus\'\n reg[`CacheBus] data_cache[`PowIndexBus];\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:32: Define or directive not defined: \'`TagBus\'\n reg[`TagBus] rtag;\n     ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`TagBus] rtag;\n            ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:33: Define or directive not defined: \'`IndexBus\'\n reg[`IndexBus] rindex;\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:33: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`IndexBus] rindex;\n              ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:34: Define or directive not defined: \'`SelectBus\'\n reg[`SelectBus] rselect;\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`SelectBus] rselect;\n               ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:36: Define or directive not defined: \'`TagBus\'\n reg[`TagBus] wtag;\n     ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`TagBus] wtag;\n            ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:37: Define or directive not defined: \'`IndexBus\'\n reg[`IndexBus] windex;\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`IndexBus] windex;\n              ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:38: Define or directive not defined: \'`SelectBus\'\n reg[`SelectBus] wselect;\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`SelectBus] wselect;\n               ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:42: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:44: Define or directive not defined: \'`NotPresent\'\n   Pres[i] = `NotPresent;\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:57: Define or directive not defined: \'`ChipDisable\'\n  if(cache_ce == `ChipDisable) begin\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:58: Define or directive not defined: \'`ZeroWord\'\n   data_o <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:60: Define or directive not defined: \'`WriteEnable\'\n  else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:60: Define or directive not defined: \'`ReadEnable\'\n  else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:63: Define or directive not defined: \'`ReadEnable\'\n  else if(re == `ReadEnable) begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:64: Define or directive not defined: \'`NotPresent\'\n   if(Pres[rindex] == `NotPresent) begin\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:65: Define or directive not defined: \'`Miss\'\n    miss = `Miss;\n           ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:71: Define or directive not defined: \'`Byte\'\n      `Byte : begin\n      ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:79: Define or directive not defined: \'`Half\'\n      `Half : begin\n      ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:87: Define or directive not defined: \'`Word\'\n      `Word : begin\n      ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:96: Define or directive not defined: \'`Miss\'\n     miss = `Miss;\n            ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:110: Define or directive not defined: \'`Present\'\n   Pres[rindex] <= `Present;\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:122: Define or directive not defined: \'`ChipDisable\'\n  if(cache_ce == `ChipDisable) begin\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:125: Define or directive not defined: \'`WriteEnable\'\n  else if(we == `WriteEnable) begin   \n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:126: Define or directive not defined: \'`NotPresent\'\n   Pres[windex[11:2]] <= `NotPresent;   \n                         ^~~~~~~~~~~\n%Error: Exiting due to 48 error(s)\n'
module cache(

	input wire cache_ce,
	

	input wire we,
	input wire[`ValidBitBus] wvalid_bit,
	input wire[`DataAddrBus] waddr,
	input wire[`DataBus] data_i,


	input wire re,
	input wire[`ValidBitBus] rvalid_bit,
	input wire[`DataAddrBus] raddr,
	output reg[`DataBus] data_o,
	

	output reg miss,
	output reg[`DataAddrBus] miss_addr,

	input wire[`CacheBus] rewrite_data
);
	
	reg Pres[`PowIndexBus];
	reg[`TagBus] Tags[`PowIndexBus];
	reg[`CacheBus] data_cache[`PowIndexBus];
	
	reg[`TagBus] rtag;
	reg[`IndexBus] rindex;
	reg[`SelectBus] rselect;
	
	reg[`TagBus] wtag;
	reg[`IndexBus] windex;
	reg[`SelectBus] wselect;
	

	integer i;
	initial begin
		for(i = 0; i < 1024; i = i + 1) begin
			Pres[i] = `NotPresent;
		end
	end
	

	always @(*) begin
		rtag <= raddr[31:12];
		rindex <= raddr[11:2];
		rselect <= raddr[1:0];
	end
	

	always @ (*) begin
		if(cache_ce == `ChipDisable) begin
			data_o <= `ZeroWord;
		end
		else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
			data_o <= {data_i[7:0],data_i[15:8],data_i[23:16],data_i[31:24]};
		end
		else if(re == `ReadEnable) begin
			if(Pres[rindex] == `NotPresent) begin
				miss = `Miss;
				miss_addr <= raddr;		
			end
			else begin
				if(Tags[rindex] == rtag) begin
					case(rvalid_bit)
						`Byte : begin
							case(rselect)
								2'b00 : data_o <= {{24{1'b0}}, data_cache[rindex][7:0]};
								2'b01 : data_o <= {{24{1'b0}}, data_cache[rindex][15:8]};
								2'b10 : data_o <= {{24{1'b0}}, data_cache[rindex][23:16]};
								2'b11 : data_o <= {{24{1'b0}}, data_cache[rindex][31:24]};
							endcase
						end
						`Half : begin
							case(rselect)
								2'b00 : data_o <= {{16{1'b0}}, data_cache[rindex][7:0],data_cache[rindex][15:8]};

								2'b10 : data_o <= {{16{1'b0}}, data_cache[rindex][23:16],data_cache[rindex][31:24]};

							endcase
						end
						`Word : begin
							data_o <= {data_cache[rindex][7:0], data_cache[rindex][15:8], data_cache[rindex][23:16],data_cache[rindex][31:24]};
						end
						default begin
							
						end
					endcase
				end
				else begin
					miss = `Miss;
					miss_addr <= raddr;
				end
			end
		end
		else begin
		
		end
	end	
	

	always @ (*) begin
			data_cache[rindex] <= rewrite_data;
			Tags[rindex] <= rtag;
			Pres[rindex] <= `Present;
	end
	

	always @(*) begin
		wtag <= waddr[31:12];
		windex <= waddr[11:2];
		wselect <= waddr[1:0];		
	end
	

	always @ (*) begin
		if(cache_ce == `ChipDisable) begin

		end
		else if(we == `WriteEnable) begin			
			Pres[windex[11:2]] <= `NotPresent;
		end
		else begin
			
		end
	end

endmodule
module cache(

	input wire cache_ce,
	

	input wire we,
	input wire[`ValidBitBus] wvalid_bit,
	input wire[`DataAddrBus] waddr,
	input wire[`DataBus] data_i,


	input wire re,
	input wire[`ValidBitBus] rvalid_bit,
	input wire[`DataAddrBus] raddr,
	output reg[`DataBus] data_o,
	

	output reg miss,
	output reg[`DataAddrBus] miss_addr,

	input wire[`CacheBus] rewrite_data
);

	
	reg Pres[`PowIndexBus];
	reg[`TagBus] Tags[`PowIndexBus];
	reg[`CacheBus] data_cache[`PowIndexBus];
	
	reg[`TagBus] rtag;
	reg[`IndexBus] rindex;
	reg[`SelectBus] rselect;
	
	reg[`TagBus] wtag;
	reg[`IndexBus] windex;
	reg[`SelectBus] wselect;
	

	integer i;
	initial begin
		for(i = 0; i < 1024; i = i + 1) begin
			Pres[i] = `NotPresent;
		end
	end
	

	always @(*) begin
		rtag <= raddr[31:12];
		rindex <= raddr[11:2];
		rselect <= raddr[1:0];
	end
	

	always @ (*) begin
		if(cache_ce == `ChipDisable) begin
			data_o <= `ZeroWord;
		end
		else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
			data_o <= {data_i[7:0],data_i[15:8],data_i[23:16],data_i[31:24]};
		end
		else if(re == `ReadEnable) begin
			if(Pres[rindex] == `NotPresent) begin
				miss = `Miss;
				miss_addr <= raddr;		
			end
			else begin
				if(Tags[rindex] == rtag) begin
					case(rvalid_bit)
						`Byte : begin
							case(rselect)
								2'b00 : data_o <= {{24{1'b0}}, data_cache[rindex][7:0]};
								2'b01 : data_o <= {{24{1'b0}}, data_cache[rindex][15:8]};
								2'b10 : data_o <= {{24{1'b0}}, data_cache[rindex][23:16]};
								2'b11 : data_o <= {{24{1'b0}}, data_cache[rindex][31:24]};
							endcase
						end
						`Half : begin
							case(rselect)
								2'b00 : data_o <= {{16{1'b0}}, data_cache[rindex][7:0],data_cache[rindex][15:8]};

								2'b10 : data_o <= {{16{1'b0}}, data_cache[rindex][23:16],data_cache[rindex][31:24]};

							endcase
						end
						`Word : begin
							data_o <= {data_cache[rindex][7:0], data_cache[rindex][15:8], data_cache[rindex][23:16],data_cache[rindex][31:24]};
						end
						default begin
							
						end
					endcase
				end
				else begin
					miss = `Miss;
					miss_addr <= raddr;
				end
			end
		end
		else begin
		
		end
	end	
	

	always @ (*) begin
			data_cache[rindex] <= rewrite_data;
			Tags[rindex] <= rtag;
			Pres[rindex] <= `Present;
	end
	

	always @(*) begin
		wtag <= waddr[31:12];
		windex <= waddr[11:2];
		wselect <= waddr[1:0];		
	end
	

	always @ (*) begin
		if(cache_ce == `ChipDisable) begin

		end
		else if(we == `WriteEnable) begin			
			Pres[windex[11:2]] <= `NotPresent;
		end
		else begin
			
		end
	end

endmodule