data/full_repos/permissive/115035459/verilog/src/lib/reset.v
 line:43: before: "20"
1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #200; downstream_pll_locked <= 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #20; downstream_pll_locked <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #100; upstream_reset <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #200; downstream_pll_locked <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:181: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #100; downstream_pll_locked <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:184: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #200; downstream_pll_locked <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:187: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:189: Unsupported: Ignoring delay on this delayed statement.\n  #100; clock_enabled <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:190: Unsupported: Ignoring delay on this delayed statement.\n  #100; downstream_pll_locked <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:191: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:196: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:53: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                  : ... Top module \'reset3_wait4plls\'\nmodule reset3_wait4plls #(\n       ^~~~~~~~~~~~~~~~\n                                                                                  : ... Top module \'reset_promulgator\'\nmodule reset_promulgator #(\n       ^~~~~~~~~~~~~~~~~\n                                                                                  : ... Top module \'reset_tb\'\nmodule reset_tb();\n       ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n                                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n                                                                       : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n                                                                                                                               ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n                                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n                                                                       : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n                                                                                                                               ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n                                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n                                                                       : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n                                                                                                                               ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reset3_wait4plls #(
	parameter CLOCK1_BIT_PICKOFF = 20,
	parameter CLOCK2_BIT_PICKOFF = 20,
	parameter CLOCK3_BIT_PICKOFF = 20,
	parameter RESET_PIPELINE_PICKOFF = 5,
	parameter PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF = 10,
	parameter PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF = 10,
	parameter PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF = 10
) (
	input reset_input,
	input pll_locked1_input, pll_locked2_input, pll_locked3_input,
	input clock1_input, clock2_input, clock3_input,
	output reset1_output,
	output reset2_output,
	output reset3_output
);
	reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));
	reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));
	reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));
endmodule
module reset3_wait4plls #(
	parameter CLOCK1_BIT_PICKOFF = 20,
	parameter CLOCK2_BIT_PICKOFF = 20,
	parameter CLOCK3_BIT_PICKOFF = 20,
	parameter RESET_PIPELINE_PICKOFF = 5,
	parameter PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF = 10,
	parameter PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF = 10,
	parameter PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF = 10
) (
	input reset_input,
	input pll_locked1_input, pll_locked2_input, pll_locked3_input,
	input clock1_input, clock2_input, clock3_input,
	output reset1_output,
	output reset2_output,
	output reset3_output
);

	reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));
	reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));
	reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));
endmodule