data/full_repos/permissive/167856740/cpu/tb/pc_tb.v
 line:31: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0; address_in = 32\'h00000004;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/pc_tb.v:13: Cannot find file containing module: \'pc\'\n    pc pc(.I_clk(clk), .I_rst(reset), .I_address(address_in), .O_address(address_out));\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/pc\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/pc.v\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/pc.sv\n             pc\n             pc.v\n             pc.sv\n             obj_dir/pc\n             obj_dir/pc.v\n             obj_dir/pc.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pc_tb;
	

	reg clk;
	reg reset;
    reg [31:0] address_in;
    wire [31:0] address_out;


    pc pc(.I_clk(clk), .I_rst(reset), .I_address(address_in), .O_address(address_out));
    

	always begin
		#5 clk = ~clk;
	end

	initial begin

        clk = 0; reset = 0; address_in = 32'hFFFFFFFF;
        

        #10 reset = 1;
        

        #10 reset = 0; address_in = 32'h00000004;
	

		#10 $finish;
	end
	
endmodule
module pc_tb;

	

	reg clk;
	reg reset;
    reg [31:0] address_in;
    wire [31:0] address_out;


    pc pc(.I_clk(clk), .I_rst(reset), .I_address(address_in), .O_address(address_out));
    

	always begin
		#5 clk = ~clk;
	end

	initial begin

        clk = 0; reset = 0; address_in = 32'hFFFFFFFF;
        

        #10 reset = 1;
        

        #10 reset = 0; address_in = 32'h00000004;
	

		#10 $finish;
	end
	
endmodule