data/full_repos/permissive/142844950/rtl/xc_aessub/xc_aessub.v
1: b"%Error: data/full_repos/permissive/142844950/rtl/xc_aessub/xc_aessub.v:48: Cannot find file containing module: 'xc_aessub_sbox'\nxc_aessub_sbox sbox_0(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/142844950/rtl/xc_aessub,data/full_repos/permissive/142844950/xc_aessub_sbox\n             data/full_repos/permissive/142844950/rtl/xc_aessub,data/full_repos/permissive/142844950/xc_aessub_sbox.v\n             data/full_repos/permissive/142844950/rtl/xc_aessub,data/full_repos/permissive/142844950/xc_aessub_sbox.sv\n             xc_aessub_sbox\n             xc_aessub_sbox.v\n             xc_aessub_sbox.sv\n             obj_dir/xc_aessub_sbox\n             obj_dir/xc_aessub_sbox.v\n             obj_dir/xc_aessub_sbox.sv\n%Error: data/full_repos/permissive/142844950/rtl/xc_aessub/xc_aessub.v:54: Cannot find file containing module: 'xc_aessub_sbox'\nxc_aessub_sbox sbox_1(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_aessub/xc_aessub.v:60: Cannot find file containing module: 'xc_aessub_sbox'\nxc_aessub_sbox sbox_2(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_aessub/xc_aessub.v:66: Cannot find file containing module: 'xc_aessub_sbox'\nxc_aessub_sbox sbox_3(\n^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module xc_aessub(

input  wire        clock ,
input  wire        reset ,

input  wire        flush ,
input  wire [31:0] flush_data,

input  wire        valid ,
input  wire [31:0] rs1   ,
input  wire [31:0] rs2   ,
input  wire        enc   ,
input  wire        rot   ,
output wire        ready ,
output wire [31:0] result

);

parameter FAST = 1'b1;

generate if(FAST) begin





assign ready = valid;

wire [7:0] sb_in_0 = rs1[ 7: 0] & {8{valid}};
wire [7:0] sb_in_1 = rs2[15: 8] & {8{valid}};
wire [7:0] sb_in_2 = rs1[23:16] & {8{valid}};
wire [7:0] sb_in_3 = rs2[31:24] & {8{valid}};

wire [7:0] sb_out_0;
wire [7:0] sb_out_1;
wire [7:0] sb_out_2;
wire [7:0] sb_out_3;

assign result = rot ? {sb_out_2, sb_out_1, sb_out_0, sb_out_3} :
                      {sb_out_3, sb_out_2, sb_out_1, sb_out_0} ;

xc_aessub_sbox sbox_0(
.in  (sb_in_0 ),
.inv (!enc    ),
.out (sb_out_0)
);

xc_aessub_sbox sbox_1(
.in  (sb_in_1 ),
.inv (!enc    ),
.out (sb_out_1)
);

xc_aessub_sbox sbox_2(
.in  (sb_in_2 ),
.inv (!enc    ),
.out (sb_out_2)
);

xc_aessub_sbox sbox_3(
.in  (sb_in_3 ),
.inv (!enc    ),
.out (sb_out_3)
);

end else begin





reg  [1:0] fsm     ;
wire [1:0] n_fsm   = fsm + 1 ;

wire       fsm_0   = fsm == 0;
wire       fsm_1   = fsm == 1;
wire       fsm_2   = fsm == 2;
wire       fsm_3   = fsm == 3;

wire [7:0] sbox_in = 
    {8{valid && fsm_0}} & rs1[ 7: 0] |
    {8{valid && fsm_1}} & rs2[15: 8] |
    {8{valid && fsm_2}} & rs1[23:16] |
    {8{valid && fsm_3}} & rs2[31:24] ;

wire [7:0] sbox_out;

assign     ready   = fsm_3;

reg [7:0]  b_0;
reg [7:0]  b_1;
reg [7:0]  b_2;

assign     result  = rot ? {b_2, b_1, b_0, sbox_out} :
                           {sbox_out, b_2, b_1, b_0} ;

always @(posedge clock) begin
    if(reset || flush) begin
        b_0 <= flush_data[7:0];
    end else if(fsm_0 && valid) begin
        b_0 <= sbox_out;
    end
end

always @(posedge clock) begin
    if(reset) begin
        b_1 <= flush_data[15:8];
    end else if(fsm_1 && valid) begin
        b_1 <= sbox_out;
    end
end

always @(posedge clock) begin
    if(reset) begin
        b_2 <= flush_data[23:16];
    end else if(fsm_2 && valid) begin
        b_2 <= sbox_out;
    end
end

always @(posedge clock) begin
    if(reset || flush) begin
        fsm <= 0;
    end else if(valid || ready) begin
        fsm <= n_fsm;
    end
end

xc_aessub_sbox sbox_0(
.in  (sbox_in ),
.inv (!enc    ),
.out (sbox_out)
);

end endgenerate

endmodule
module xc_aessub(

input  wire        clock ,
input  wire        reset ,

input  wire        flush ,
input  wire [31:0] flush_data,

input  wire        valid ,
input  wire [31:0] rs1   ,
input  wire [31:0] rs2   ,
input  wire        enc   ,
input  wire        rot   ,
output wire        ready ,
output wire [31:0] result

);


parameter FAST = 1'b1;

generate if(FAST) begin





assign ready = valid;

wire [7:0] sb_in_0 = rs1[ 7: 0] & {8{valid}};
wire [7:0] sb_in_1 = rs2[15: 8] & {8{valid}};
wire [7:0] sb_in_2 = rs1[23:16] & {8{valid}};
wire [7:0] sb_in_3 = rs2[31:24] & {8{valid}};

wire [7:0] sb_out_0;
wire [7:0] sb_out_1;
wire [7:0] sb_out_2;
wire [7:0] sb_out_3;

assign result = rot ? {sb_out_2, sb_out_1, sb_out_0, sb_out_3} :
                      {sb_out_3, sb_out_2, sb_out_1, sb_out_0} ;

xc_aessub_sbox sbox_0(
.in  (sb_in_0 ),
.inv (!enc    ),
.out (sb_out_0)
);

xc_aessub_sbox sbox_1(
.in  (sb_in_1 ),
.inv (!enc    ),
.out (sb_out_1)
);

xc_aessub_sbox sbox_2(
.in  (sb_in_2 ),
.inv (!enc    ),
.out (sb_out_2)
);

xc_aessub_sbox sbox_3(
.in  (sb_in_3 ),
.inv (!enc    ),
.out (sb_out_3)
);

end else begin





reg  [1:0] fsm     ;
wire [1:0] n_fsm   = fsm + 1 ;

wire       fsm_0   = fsm == 0;
wire       fsm_1   = fsm == 1;
wire       fsm_2   = fsm == 2;
wire       fsm_3   = fsm == 3;

wire [7:0] sbox_in = 
    {8{valid && fsm_0}} & rs1[ 7: 0] |
    {8{valid && fsm_1}} & rs2[15: 8] |
    {8{valid && fsm_2}} & rs1[23:16] |
    {8{valid && fsm_3}} & rs2[31:24] ;

wire [7:0] sbox_out;

assign     ready   = fsm_3;

reg [7:0]  b_0;
reg [7:0]  b_1;
reg [7:0]  b_2;

assign     result  = rot ? {b_2, b_1, b_0, sbox_out} :
                           {sbox_out, b_2, b_1, b_0} ;

always @(posedge clock) begin
    if(reset || flush) begin
        b_0 <= flush_data[7:0];
    end else if(fsm_0 && valid) begin
        b_0 <= sbox_out;
    end
end

always @(posedge clock) begin
    if(reset) begin
        b_1 <= flush_data[15:8];
    end else if(fsm_1 && valid) begin
        b_1 <= sbox_out;
    end
end

always @(posedge clock) begin
    if(reset) begin
        b_2 <= flush_data[23:16];
    end else if(fsm_2 && valid) begin
        b_2 <= sbox_out;
    end
end

always @(posedge clock) begin
    if(reset || flush) begin
        fsm <= 0;
    end else if(valid || ready) begin
        fsm <= n_fsm;
    end
end

xc_aessub_sbox sbox_0(
.in  (sbox_in ),
.inv (!enc    ),
.out (sbox_out)
);

end endgenerate

endmodule