data/full_repos/permissive/166441728/RockBand.v
 line:58: before: "."
1: b'%Warning-PINMISSING: data/full_repos/permissive/166441728/RockBand.v:212: Cell has missing pin: \'pass\'\n control control0(\n         ^~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/166441728/RockBand.v:212: Cell has missing pin: \'remove\'\n control control0(\n         ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/166441728/RockBand.v:212: Cell has missing pin: \'done_remove\'\n control control0(\n         ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/166441728/RockBand.v:208: Signal definition not found, creating implicitly: \'done_score_over\'\n                                                                      : ... Suggested alternative: \'done_game_over\'\n  .done_score(done_score_over), .score_plot(score_over_plot), .final_x(x_over_score), .final_y(y_over_score), .offx(\'d167), .offy(\'d218));\n              ^~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/166441728/RockBand.v:285: Signal definition not found, creating implicitly: \'ps2_key_pressed\'\n  .ps2_key_pressed(ps2_key_pressed));\n                   ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:425: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 10 bits.\n                                                                   : ... In instance RockBand.finalscore.d_counter\n assign ones = val_counter % \'d10;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:426: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 10 bits.\n                                                                   : ... In instance RockBand.finalscore.d_counter\n assign tens = (val_counter % \'d100) / \'d10;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:427: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 10 bits.\n                                                                   : ... In instance RockBand.finalscore.d_counter\n assign hundreds = val_counter / \'d100;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:1083: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'counter_y\' generates 10 bits.\n                                                                    : ... In instance RockBand.load_background0\n assign final_y = counter_y;\n                ^\n%Error: data/full_repos/permissive/166441728/RockBand.v:1085: Cannot find file containing module: \'Background_ram\'\n Background_ram b0 (.address(memory_address), .clock(clock), .data(9\'b0), .wren(1\'b0), .q(color_play));\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166441728,data/full_repos/permissive/166441728/Background_ram\n             data/full_repos/permissive/166441728,data/full_repos/permissive/166441728/Background_ram.v\n             data/full_repos/permissive/166441728,data/full_repos/permissive/166441728/Background_ram.sv\n             Background_ram\n             Background_ram.v\n             Background_ram.sv\n             obj_dir/Background_ram\n             obj_dir/Background_ram.v\n             obj_dir/Background_ram.sv\n%Error: data/full_repos/permissive/166441728/RockBand.v:1086: Cannot find file containing module: \'gameover\'\n gameover g0 (.address(memory_address), .clock(clock), .q(color_end));\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:1033: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'counter_y\' generates 10 bits.\n                                                                    : ... In instance RockBand.load_over0\n assign final_y = counter_y;\n                ^\n%Error: data/full_repos/permissive/166441728/RockBand.v:1035: Cannot find file containing module: \'gameover\'\n gameover g0 (.address(memory_address), .clock(clock), .q(color_end));\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:947: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                   : ... In instance RockBand.note_to_ram0\n   wr <= 10\'b0;\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:912: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'memory_address\' generates 8 bits.\n                                                                   : ... In instance RockBand.load_notes0\n assign final_y = memory_address + 10\'d36;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:739: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                   : ... In instance RockBand.datapath0\n initial note_count = 3\'b0;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:775: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                   : ... In instance RockBand.datapath0\n    note_count <= 3\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:453: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'current_place\' generates 2 bits.\n                                                                   : ... In instance RockBand.finalscore\n  case (current_place)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:467: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                   : ... In instance RockBand.finalscore\n   current_seg <= 3\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:487: Bit extraction of var[6:0] requires 3 bit index, not 4 bits.\n                                                                   : ... In instance RockBand.finalscore\n     else if (seg[current_seg] == 1 || counter_x == 10\'d4)\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:506: Bit extraction of var[6:0] requires 3 bit index, not 4 bits.\n                                                                   : ... In instance RockBand.finalscore\n     else if (seg[current_seg] == 1 || counter_y == 10\'d4)\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:525: Bit extraction of var[6:0] requires 3 bit index, not 4 bits.\n                                                                   : ... In instance RockBand.finalscore\n     else if (seg[current_seg] == 1 || counter_y == 10\'d8)\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:544: Bit extraction of var[6:0] requires 3 bit index, not 4 bits.\n                                                                   : ... In instance RockBand.finalscore\n     else if (seg[current_seg] == 1 || counter_x == 10\'d4)\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:563: Bit extraction of var[6:0] requires 3 bit index, not 4 bits.\n                                                                   : ... In instance RockBand.finalscore\n     else if (seg[current_seg] == 1 || counter_y == 10\'d8)\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:582: Bit extraction of var[6:0] requires 3 bit index, not 4 bits.\n                                                                   : ... In instance RockBand.finalscore\n     else if (seg[current_seg] == 1 || counter_y == 10\'d4)\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:601: Bit extraction of var[6:0] requires 3 bit index, not 4 bits.\n                                                                   : ... In instance RockBand.finalscore\n     else if (seg[current_seg] == 1 || counter_x == 10\'d4)\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:478: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h0\' generates 3 bits.\n                                                                   : ... In instance RockBand.finalscore\n   case (current_seg)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:478: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h1\' generates 3 bits.\n                                                                   : ... In instance RockBand.finalscore\n   case (current_seg)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:478: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h2\' generates 3 bits.\n                                                                   : ... In instance RockBand.finalscore\n   case (current_seg)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:478: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h3\' generates 3 bits.\n                                                                   : ... In instance RockBand.finalscore\n   case (current_seg)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:478: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                   : ... In instance RockBand.finalscore\n   case (current_seg)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:478: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                   : ... In instance RockBand.finalscore\n   case (current_seg)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:478: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n                                                                   : ... In instance RockBand.finalscore\n   case (current_seg)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:618: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 11 bits.\n                                                                   : ... In instance RockBand.finalscore\n assign final_x = counter_x + current_place*12 + offx;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:619: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 11 bits.\n                                                                   : ... In instance RockBand.finalscore\n assign final_y = counter_y + offy;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:373: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'last_note\' generates 5 bits.\n                                                                   : ... In instance RockBand.hit_detection0\n   prev_hit <= last_note;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:371: Operator NEQ expects 10 bits on the RHS, but RHS\'s VARREF \'last_note\' generates 5 bits.\n                                                                   : ... In instance RockBand.hit_detection0\n  if (last_note != 0 && prev_hit != last_note)\n                                 ^~\n%Error: data/full_repos/permissive/166441728/RockBand.v:42: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:111: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                   : ... In instance RockBand\n   final_color <= 3\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:117: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                   : ... In instance RockBand\n   final_color <= 3\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:123: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                   : ... In instance RockBand\n   final_color <= 3\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:129: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                   : ... In instance RockBand\n   final_color <= 3\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:135: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                   : ... In instance RockBand\n   final_color <= 3\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:173: Input port connection \'user_note\' expects 5 bits on the pin connection, but pin connection\'s VARREF \'user_note\' generates 4 bits.\n                                                                   : ... In instance RockBand\n hit_detection hit_detection0(.remove(remove), .resetn(done_draw), .clock(CLOCK_50), .user_note(user_note), \n                                                                                      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:177: Output port connection \'final_x\' expects 11 bits on the pin connection, but pin connection\'s VARREF \'x_background\' generates 10 bits.\n                                                                   : ... In instance RockBand\n  .out_color(background_color), .done_erase(done_erase), .final_x(x_background), .final_y(y_background), .erase_plot(erase_plot));\n                                                          ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:177: Output port connection \'final_y\' expects 11 bits on the pin connection, but pin connection\'s VARREF \'y_background\' generates 10 bits.\n                                                                   : ... In instance RockBand\n  .out_color(background_color), .done_erase(done_erase), .final_x(x_background), .final_y(y_background), .erase_plot(erase_plot));\n                                                                                  ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:180: Output port connection \'final_x\' expects 11 bits on the pin connection, but pin connection\'s VARREF \'x_over\' generates 10 bits.\n                                                                   : ... In instance RockBand\n  .out_color(over_color), .done_erase(done_game_over), .final_x(x_over), .final_y(y_over), .erase_plot(over_plot));\n                                                        ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:180: Output port connection \'final_y\' expects 11 bits on the pin connection, but pin connection\'s VARREF \'y_over\' generates 10 bits.\n                                                                   : ... In instance RockBand\n  .out_color(over_color), .done_erase(done_game_over), .final_x(x_over), .final_y(y_over), .erase_plot(over_plot));\n                                                                          ^~~~~~~\n%Error: data/full_repos/permissive/166441728/RockBand.v:189: Cannot find file containing module: \'notes_display_test\'\n notes_display_test notes_display0(.clock(CLOCK_50), .data(data_in), .rdaddress(mem_address), .rden(rden), \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/166441728/RockBand.v:195: Cannot find file containing module: \'song1\'\n song1 song (.address(song_address), .clock(CLOCK_50), .data(4\'b0), .wren(1\'b0), .q(feed_note));\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:204: Input port connection \'correct\' expects 10 bits on the pin connection, but pin connection\'s SEL generates 3 bits.\n                                                                   : ... In instance RockBand\n load_score lhit(.correct(SW[2:0]), .display_score(display_hit), .resetn(~hit), .clock(CLOCK_50), \n                  ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/166441728/RockBand.v:210: Input port connection \'data\' expects 2 bits on the pin connection, but pin connection\'s SEL generates 3 bits.\n                                                                   : ... In instance RockBand\n difficulty difficulty0(.data(SW[2:0]), .out(speed));\n                         ^~~~\n%Error: data/full_repos/permissive/166441728/RockBand.v:268: Cannot find file containing module: \'PS2_Controller\'\n PS2_Controller PS2 (\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 46 warning(s)\n'
module control(clock, resetn, go, done_erase, done_draw, done_feed, done_hit, speed, erase, draw, feed, load, 
	pass, hit, done_new, remove, done_remove, score, done_score, over, again, gameover,
	correct, wrong, done_correct, done_wrong, done_game_over, over_score);
	
	input clock, resetn, go, done_erase, done_draw, done_feed, done_hit, done_new, remove, done_remove, done_score, again, gameover,
		done_correct, done_wrong, done_game_over;
	input [25:0] speed;
	output reg erase, draw, feed, load, pass, hit, score, correct, wrong, over, over_score;

	reg [5:0] current_state, next_state;
	
	localparam  S_BEGIN  	  		= 6'd0,
					S_ERASE       		= 6'd1,
					S_FEED_RAM 			= 6'd2,
					S_DRAW	 	 		= 6'd3,
					S_WAIT 	      	= 6'd4,
					S_NEW_NOTE 	      = 6'd5,
					S_DISP_SCORE		= 6'd6,
					S_DISP_CORRECT		= 6'd7,
					S_DISP_WRONG		= 6'd8,
					S_DISP_HIT			= 6'd9,
					S_GAME_OVER 		= 6'd10,
					S_GAME_OVER_SCORE 	= 6'd11;
	
	wire counter;
	wire [25:0] w1;
	assign counter = (w1 == 26'b0) ? 1 : 0;
	
	rate_divider r0(
				.clock(clock),
				.load(speed),
				.enable(current_state == S_WAIT),
				.count(w1)
				);
 
	always @(*)
	begin: state_table 
			case (current_state)
					S_BEGIN: next_state 		<= go ? S_ERASE : S_BEGIN;
					S_ERASE: next_state 		<= done_erase ? S_FEED_RAM : S_ERASE;
					S_FEED_RAM: next_state 	<= done_feed ? S_DRAW : S_FEED_RAM;
					S_DRAW: next_state 	<= done_draw ? S_DISP_SCORE : S_DRAW;
					S_DISP_SCORE: next_state 		<= done_score ? S_DISP_CORRECT : S_DISP_SCORE;
					S_DISP_CORRECT: next_state 		<= done_correct ? S_DISP_WRONG : S_DISP_CORRECT;
					S_DISP_WRONG: next_state 		<= done_wrong ? S_DISP_HIT : S_DISP_WRONG;
					S_DISP_HIT: next_state 		<= done_hit ? S_WAIT : S_DISP_HIT;	
					S_WAIT: next_state 		<= counter ? S_NEW_NOTE : S_WAIT;
					S_NEW_NOTE: next_state 		<= done_new ? S_ERASE : S_NEW_NOTE;
					
					S_GAME_OVER: next_state <= done_game_over ? S_GAME_OVER_SCORE : S_GAME_OVER;
					S_GAME_OVER_SCORE: next_state <= S_GAME_OVER_SCORE;
					








					default: next_state 		<= S_BEGIN;
			endcase
	end
   
	always @(*)
	begin: enable_signals
		load	<= 1'b0;
		erase	<= 1'b0;
		feed	<= 1'b0;
		draw	<= 1'b0;
		score <= 1'b0;
		correct <= 1'b0;
		wrong <= 1'b0;
		hit <= 1'b0;
		over 	<= 1'b0;
		over_score <= 1'b0;
		
		case (current_state)
			S_ERASE: 	erase <= 1'b1;
			S_NEW_NOTE: load 	<= 1'b1;
			S_FEED_RAM: feed 	<= 1'b1;
			S_DRAW: 		draw 	<= 1'b1;
			S_DISP_SCORE: score <= 1'b1;
			S_DISP_CORRECT: correct <= 1'b1;
			S_DISP_WRONG: wrong <= 1'b1;
			S_DISP_HIT: hit <= 1'b1;
			S_GAME_OVER: over <= 1'b1;
			S_GAME_OVER_SCORE: over_score <= 1'b1;
		endcase
	end
   
	always@(posedge clock)
	begin: state_FFs
		if(!resetn)
		begin
			current_state <= S_BEGIN;
		end
		else if (gameover)
			current_state <= S_GAME_OVER;
		else
		begin
			current_state <= next_state;
		end
	end
endmodule
module control(clock, resetn, go, done_erase, done_draw, done_feed, done_hit, speed, erase, draw, feed, load, 
	pass, hit, done_new, remove, done_remove, score, done_score, over, again, gameover,
	correct, wrong, done_correct, done_wrong, done_game_over, over_score);

	
	input clock, resetn, go, done_erase, done_draw, done_feed, done_hit, done_new, remove, done_remove, done_score, again, gameover,
		done_correct, done_wrong, done_game_over;
	input [25:0] speed;
	output reg erase, draw, feed, load, pass, hit, score, correct, wrong, over, over_score;

	reg [5:0] current_state, next_state;
	
	localparam  S_BEGIN  	  		= 6'd0,
					S_ERASE       		= 6'd1,
					S_FEED_RAM 			= 6'd2,
					S_DRAW	 	 		= 6'd3,
					S_WAIT 	      	= 6'd4,
					S_NEW_NOTE 	      = 6'd5,
					S_DISP_SCORE		= 6'd6,
					S_DISP_CORRECT		= 6'd7,
					S_DISP_WRONG		= 6'd8,
					S_DISP_HIT			= 6'd9,
					S_GAME_OVER 		= 6'd10,
					S_GAME_OVER_SCORE 	= 6'd11;
	
	wire counter;
	wire [25:0] w1;
	assign counter = (w1 == 26'b0) ? 1 : 0;
	
	rate_divider r0(
				.clock(clock),
				.load(speed),
				.enable(current_state == S_WAIT),
				.count(w1)
				);
 
	always @(*)
	begin: state_table 
			case (current_state)
					S_BEGIN: next_state 		<= go ? S_ERASE : S_BEGIN;
					S_ERASE: next_state 		<= done_erase ? S_FEED_RAM : S_ERASE;
					S_FEED_RAM: next_state 	<= done_feed ? S_DRAW : S_FEED_RAM;
					S_DRAW: next_state 	<= done_draw ? S_DISP_SCORE : S_DRAW;
					S_DISP_SCORE: next_state 		<= done_score ? S_DISP_CORRECT : S_DISP_SCORE;
					S_DISP_CORRECT: next_state 		<= done_correct ? S_DISP_WRONG : S_DISP_CORRECT;
					S_DISP_WRONG: next_state 		<= done_wrong ? S_DISP_HIT : S_DISP_WRONG;
					S_DISP_HIT: next_state 		<= done_hit ? S_WAIT : S_DISP_HIT;	
					S_WAIT: next_state 		<= counter ? S_NEW_NOTE : S_WAIT;
					S_NEW_NOTE: next_state 		<= done_new ? S_ERASE : S_NEW_NOTE;
					
					S_GAME_OVER: next_state <= done_game_over ? S_GAME_OVER_SCORE : S_GAME_OVER;
					S_GAME_OVER_SCORE: next_state <= S_GAME_OVER_SCORE;
					








					default: next_state 		<= S_BEGIN;
			endcase
	end
   
	always @(*)
	begin: enable_signals
		load	<= 1'b0;
		erase	<= 1'b0;
		feed	<= 1'b0;
		draw	<= 1'b0;
		score <= 1'b0;
		correct <= 1'b0;
		wrong <= 1'b0;
		hit <= 1'b0;
		over 	<= 1'b0;
		over_score <= 1'b0;
		
		case (current_state)
			S_ERASE: 	erase <= 1'b1;
			S_NEW_NOTE: load 	<= 1'b1;
			S_FEED_RAM: feed 	<= 1'b1;
			S_DRAW: 		draw 	<= 1'b1;
			S_DISP_SCORE: score <= 1'b1;
			S_DISP_CORRECT: correct <= 1'b1;
			S_DISP_WRONG: wrong <= 1'b1;
			S_DISP_HIT: hit <= 1'b1;
			S_GAME_OVER: over <= 1'b1;
			S_GAME_OVER_SCORE: over_score <= 1'b1;
		endcase
	end
   
	always@(posedge clock)
	begin: state_FFs
		if(!resetn)
		begin
			current_state <= S_BEGIN;
		end
		else if (gameover)
			current_state <= S_GAME_OVER;
		else
		begin
			current_state <= next_state;
		end
	end
endmodule