data/full_repos/permissive/202448421/rtl/av/YUV422_to_444.v
data/verilator_xmls/ab7fae3e-548b-490e-94c0-4cf5dcfd56c3.xml
module YUV422_to_444	(
							iYCbCr,

							oY,
							oCb,
							oCr,

							iX,
							iCLK,
							iRST_N	);

input	[15:0]	iYCbCr;

output	[7:0]	oY;
output	[7:0]	oCb;
output	[7:0]	oCr;

input	[9:0]	iX;
input			iCLK;
input			iRST_N;

reg		[7:0]	mY;
reg		[7:0]	mCb;
reg		[7:0]	mCr;

assign	oY	=	mY;
assign	oCb	=	mCb;
assign	oCr	=	mCr;

always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		mY	<=	0;
		mCb	<=	0;
		mCr	<=	0;
	end
	else
	begin
		if(iX[0])
		{mY,mCr}	<=	iYCbCr;
		else
		{mY,mCb}	<=	iYCbCr;
	end
end

endmodule
module YUV422_to_444	(
							iYCbCr,

							oY,
							oCb,
							oCr,

							iX,
							iCLK,
							iRST_N	);


input	[15:0]	iYCbCr;

output	[7:0]	oY;
output	[7:0]	oCb;
output	[7:0]	oCr;

input	[9:0]	iX;
input			iCLK;
input			iRST_N;

reg		[7:0]	mY;
reg		[7:0]	mCb;
reg		[7:0]	mCr;

assign	oY	=	mY;
assign	oCb	=	mCb;
assign	oCr	=	mCr;

always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		mY	<=	0;
		mCb	<=	0;
		mCr	<=	0;
	end
	else
	begin
		if(iX[0])
		{mY,mCr}	<=	iYCbCr;
		else
		{mY,mCb}	<=	iYCbCr;
	end
end

endmodule