data/full_repos/permissive/143278/ivltests/dcomp1.v
 line:9: before: ";"
1: b'%Error: data/full_repos/permissive/143278/ivltests/dcomp1.v:16: Unsupported or unknown PLI call: $monitor\n      $monitor("%b %b %t %t %t", internal_Clk, Clk, phdelay, compdelay, $time);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dcomp1.v:18: Unsupported: Ignoring delay on this delayed statement.\n       #2000;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dcomp1.v:20: Unsupported: Ignoring delay on this delayed statement.\n       #2001;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dcomp1.v:25: Unsupported: Ignoring delay on this delayed statement.\n   always #(clk_period/2) internal_Clk = ~internal_Clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dcomp1.v:31: Unsupported: Ignoring delay on this delayed statement.\n      compdelay = phdelay + phoffset;  #(compdelay);   \n                                       ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dcomp;
   time      phdelay;
   parameter clk_period = 400;
   parameter phoffset = 4;
   time      compdelay;
   reg       internal_Clk, Clk;

   initial begin
      $monitor("%b %b %t %t %t", internal_Clk, Clk, phdelay, compdelay, $time);
      phdelay = 0;
       #2000;
       phdelay = 13;
       #2001;
       $finish(0);
   end

   initial internal_Clk <= 0;
   always #(clk_period/2) internal_Clk = ~internal_Clk;

   always @(internal_Clk) begin



      compdelay = phdelay + phoffset;  #(compdelay);


      $display("got here");

      Clk <= internal_Clk;



   end

endmodule
module dcomp;

   time      phdelay;
   parameter clk_period = 400;
   parameter phoffset = 4;
   time      compdelay;
   reg       internal_Clk, Clk;

   initial begin
      $monitor("%b %b %t %t %t", internal_Clk, Clk, phdelay, compdelay, $time);
      phdelay = 0;
       #2000;
       phdelay = 13;
       #2001;
       $finish(0);
   end

   initial internal_Clk <= 0;
   always #(clk_period/2) internal_Clk = ~internal_Clk;

   always @(internal_Clk) begin



      compdelay = phdelay + phoffset;  #(compdelay);


      $display("got here");

      Clk <= internal_Clk;



   end

endmodule