data/full_repos/permissive/129155059/proyecto-01/s2p/freq_div_synth_delay.v
1: b"%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/freq_div_synth_delay.v:12: Cannot find file containing module: 'NOT_delay'\n  NOT_delay _2_ (\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/s2p,data/full_repos/permissive/129155059/NOT_delay\n             data/full_repos/permissive/129155059/proyecto-01/s2p,data/full_repos/permissive/129155059/NOT_delay.v\n             data/full_repos/permissive/129155059/proyecto-01/s2p,data/full_repos/permissive/129155059/NOT_delay.sv\n             NOT_delay\n             NOT_delay.v\n             NOT_delay.sv\n             obj_dir/NOT_delay\n             obj_dir/NOT_delay.v\n             obj_dir/NOT_delay.sv\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p/freq_div_synth_delay.v:16: Cannot find file containing module: 'NOR_delay'\n  NOR_delay _3_ (\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module freq_div_synth_delay(CLK, reset, CLK_2, CLK_4, CLK_8);
  wire _0_;
  wire _1_;
  input CLK;
  output CLK_2;
  reg CLK_2;
  output CLK_4;
  output CLK_8;
  input reset;
  NOT_delay _2_ (
    .A(reset),
    .Y(_1_)
  );
  NOR_delay _3_ (
    .A(CLK_2),
    .B(_1_),
    .Y(_0_)
  );
  always @(posedge CLK)
      CLK_2 <= #15  _0_;
  assign CLK_4 = 1'b0;
  assign CLK_8 = 1'b0;
endmodule
module freq_div_synth_delay(CLK, reset, CLK_2, CLK_4, CLK_8);

  wire _0_;
  wire _1_;
  input CLK;
  output CLK_2;
  reg CLK_2;
  output CLK_4;
  output CLK_8;
  input reset;
  NOT_delay _2_ (
    .A(reset),
    .Y(_1_)
  );
  NOR_delay _3_ (
    .A(CLK_2),
    .B(_1_),
    .Y(_0_)
  );
  always @(posedge CLK)
      CLK_2 <= #15  _0_;
  assign CLK_4 = 1'b0;
  assign CLK_8 = 1'b0;
endmodule