data/full_repos/permissive/212495825/src/gaplus_io.v
1: b'%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:356: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'INP\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h0: out <= INP;  \n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:357: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h1: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'hF;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:357: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h1: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'hF;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'he\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:359: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h3: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'h1;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:359: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'h1\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h3: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'h1;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:276: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_add\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp1\n    regs[4\'h0] <= credit_add;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:277: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_sub\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp1\n    regs[4\'h1] <= credit_sub;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:144: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_add\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp0\n    regs[4\'h2] <= credit_add;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:145: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_sub\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp0\n    regs[4\'h3] <= credit_sub;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:46: Output port connection \'rd\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'iocust_rd\' generates 4 bits.\n                                                                       : ... In instance GAPLUS_IO\nGAPLUS_IO_CUS2 iocust( reset, clk, iocust_cs, cpu_ad[3:0], iocust_rd, cpu_wd, cpu_wr,  pcm_kick, INP2 );\n                                                           ^~~~~~~~~\n%Error: Exiting due to 13 warning(s)\n'
module GAPLUS_IO
(
	input			 reset,
	input			 clk,
	input	 		 VBLK,

	input	[15:0] cpu_ad,
	input			 cpu_vma,
	input			 cpu_wr,
	input	 [7:0] cpu_wd,
	output [7:0] cpu_rd,
	output		 cpu_cs,

	input	[31:0] INP0,
	input	[31:0] INP1,
	input	 [3:0] INP2,
	
	output		 pcm_kick
);

wire io_cs = ( cpu_ad[15:8] == 8'h68 ) & cpu_vma;

wire iochp0_cs = ( cpu_ad[7:4] == 4'h0 ) & io_cs;
wire iochp1_cs = ( cpu_ad[7:4] == 4'h1 ) & io_cs;
wire iocust_cs = ( cpu_ad[7:4] == 4'h2 ) & io_cs;

wire [3:0] iochp0_rd;
wire [3:0] iochp1_rd;
wire [3:0] iocust_rd;

wire [3:0] io_rd = iochp0_cs ? iochp0_rd :
						 iochp1_cs ? iochp1_rd :
						 iocust_cs ? iocust_rd :
						 4'hF;

assign cpu_cs = io_cs;
assign cpu_rd = { 4'hF, io_rd };

GAPLUS_IO_CUS0	iochp0( reset, clk, VBLK, iochp0_cs, cpu_ad[3:0], iochp0_rd, cpu_wd[3:0], cpu_wr, INP0 );
GAPLUS_IO_CUS1	iochp1( reset, clk, VBLK, iochp1_cs, cpu_ad[3:0], iochp1_rd, cpu_wd[3:0], cpu_wr, INP1 );
GAPLUS_IO_CUS2	iocust( reset, clk, iocust_cs, cpu_ad[3:0], iocust_rd, cpu_wd, cpu_wr,  pcm_kick, INP2 );

endmodule
module GAPLUS_IO
(
	input			 reset,
	input			 clk,
	input	 		 VBLK,

	input	[15:0] cpu_ad,
	input			 cpu_vma,
	input			 cpu_wr,
	input	 [7:0] cpu_wd,
	output [7:0] cpu_rd,
	output		 cpu_cs,

	input	[31:0] INP0,
	input	[31:0] INP1,
	input	 [3:0] INP2,
	
	output		 pcm_kick
);


wire io_cs = ( cpu_ad[15:8] == 8'h68 ) & cpu_vma;

wire iochp0_cs = ( cpu_ad[7:4] == 4'h0 ) & io_cs;
wire iochp1_cs = ( cpu_ad[7:4] == 4'h1 ) & io_cs;
wire iocust_cs = ( cpu_ad[7:4] == 4'h2 ) & io_cs;

wire [3:0] iochp0_rd;
wire [3:0] iochp1_rd;
wire [3:0] iocust_rd;

wire [3:0] io_rd = iochp0_cs ? iochp0_rd :
						 iochp1_cs ? iochp1_rd :
						 iocust_cs ? iocust_rd :
						 4'hF;

assign cpu_cs = io_cs;
assign cpu_rd = { 4'hF, io_rd };

GAPLUS_IO_CUS0	iochp0( reset, clk, VBLK, iochp0_cs, cpu_ad[3:0], iochp0_rd, cpu_wd[3:0], cpu_wr, INP0 );
GAPLUS_IO_CUS1	iochp1( reset, clk, VBLK, iochp1_cs, cpu_ad[3:0], iochp1_rd, cpu_wd[3:0], cpu_wr, INP1 );
GAPLUS_IO_CUS2	iocust( reset, clk, iocust_cs, cpu_ad[3:0], iocust_rd, cpu_wd, cpu_wr,  pcm_kick, INP2 );

endmodule