data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:3: Cannot find include file: RV2T_common.vh\n`include "RV2T_common.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158824477/sim/iverilog,data/full_repos/permissive/158824477/RV2T_common.vh\n             data/full_repos/permissive/158824477/sim/iverilog,data/full_repos/permissive/158824477/RV2T_common.vh.v\n             data/full_repos/permissive/158824477/sim/iverilog,data/full_repos/permissive/158824477/RV2T_common.vh.sv\n             RV2T_common.vh\n             RV2T_common.vh.v\n             RV2T_common.vh.sv\n             obj_dir/RV2T_common.vh\n             obj_dir/RV2T_common.vh.v\n             obj_dir/RV2T_common.vh.sv\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:23: Define or directive not defined: \'`MEM_ADDR_BITS\'\n        reg  [`MEM_ADDR_BITS - 1 : 0]                  ocd_rw_addr;\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:24: Define or directive not defined: \'`XLEN\'\n        reg  [`XLEN - 1 : 0]                           ocd_write_word;\n              ^~~~~\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:27: Define or directive not defined: \'`XLEN\'\n        wire  [`XLEN - 1 : 0]                           ocd_mem_word_out;        \n               ^~~~~\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:29: Define or directive not defined: \'`REG_ADDR_BITS\'\n        reg  [`REG_ADDR_BITS - 1 : 0]                  ocd_reg_read_addr;\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:31: Define or directive not defined: \'`REG_ADDR_BITS\'\n        reg  [`REG_ADDR_BITS - 1 : 0]                  ocd_reg_write_addr;\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:32: Define or directive not defined: \'`XLEN\'\n        reg  [`XLEN - 1 : 0]                           ocd_reg_write_data;\n              ^~~~~\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:43: Define or directive not defined: \'`PC_BITWIDTH\'\n        reg  [`PC_BITWIDTH - 1 : 0]                    start_address;\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:47: Define or directive not defined: \'`XLEN\'\n        wire  [`XLEN - 1 : 0]                           peek_pc;\n               ^~~~~\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:48: Define or directive not defined: \'`XLEN\'\n        wire  [`XLEN - 1 : 0]                           peek_ir;\n               ^~~~~\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:50: Define or directive not defined: \'`XLEN_BYTES\'\n        wire  [`XLEN_BYTES - 1 : 0]                     peek_mem_write_en;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:51: Define or directive not defined: \'`XLEN\'\n        wire  [`XLEN - 1 : 0]                           peek_mem_write_data;\n               ^~~~~\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:52: Define or directive not defined: \'`MEM_ADDR_BITS\'\n        wire [`MEM_ADDR_BITS - 1 : 0]                   peek_mem_addr;\n              ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n    repeat(4) #10 clk = ~clk;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n    forever #10 clk = ~clk;  \n            ^\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:129: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, PulseRain_RV2T_MCU_i);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:196: syntax error, unexpected \'@\'\n                    @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:200: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/158824477/sim/iverilog/mcu_tb.v:213: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: Exiting due to 17 error(s), 3 warning(s)\n'
function [15:0] swap_16(input [15:0] in);
    swap_16 =  {in[7:0], in[15:8]};
endfunction
function [15:0] swap_16(input [15:0] in);

    swap_16 =  {in[7:0], in[15:8]};
endfunction