data/full_repos/permissive/136510272/projects/version.1.x8086/icarus.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/version.1.x8086/icarus.v:60: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk         = ~clk;       \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/version.1.x8086/icarus.v:61: Unsupported: Ignoring delay on this delayed statement.\nalways #2   clock_25    = ~clock_25;  \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/version.1.x8086/icarus.v:62: Unsupported: Ignoring delay on this delayed statement.\nalways #4   clock_12    = ~clock_12;  \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/version.1.x8086/icarus.v:63: Unsupported: Ignoring delay on this delayed statement.\nalways #8   clock_6     = ~clock_6;   \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/version.1.x8086/icarus.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #2000 $finish;\n  ^\n%Error: data/full_repos/permissive/136510272/projects/version.1.x8086/icarus.v:81: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("icarus_result.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.x8086/icarus.v:82: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, icarus);\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module icarus;





reg clk;
reg clock_25;
reg clock_12;
reg clock_6;


reg [3:0]   led;
reg [1:0]   keys;


reg         adc_clock_20mhz;
reg [7:0]   adc_input;


reg        sdram_clock;
reg [11:0] sdram_addr;
reg [1:0]  sdram_bank;
reg [15:0] sdram_dq;
reg        sdram_ldqm;
reg        sdram_udqm;
reg        sdram_ras;
reg        sdram_cas;
reg        sdram_we;
    

reg [4:0]  vga_red;
reg [5:0]  vga_green;
reg [4:0]  vga_blue;
reg        vga_hs;
reg        vga_vs;


reg        ftdi_rx;
reg        ftdi_tx;




reg [1:0]  usb;


reg        sound_left;
reg        sound_right;


reg [1:0]  ps2_keyb;
reg [1:0]  ps2_mouse;


always #0.5 clk         = ~clk;
always #2   clock_25    = ~clock_25;
always #4   clock_12    = ~clock_12;
always #8   clock_6     = ~clock_6;


initial begin

  clk      = 1;
  clock_25 = 0;
  clock_12 = 0;
  clock_6  = 0;
  #2000 $finish;

end 



initial
begin

    $dumpfile("icarus_result.vcd");
    $dumpvars(0, icarus);

end




reg     [15:0] i_data;
wire    [15:0] o_data;
wire    [19:0] o_addr;


processor i8086(

    clock_25,
    1'b1,
    1'b1,
    o_addr,    
    i_data,
    o_data,
    o_wr    
);




reg [7:0] memory [65535 : 0];
reg [1:0] trigger;

integer j;
initial begin

    $readmemh("icarus_memory.hex", memory);
    
end

always @(posedge clk) begin

    trigger[1:0] <= {trigger[0], o_wr};


    i_data <= {memory[ {o_addr[15:1], 1'b1} ],
               memory[ {o_addr[15:1], 1'b0} ]};


    if (trigger == 2'b01) begin
    
        memory[ {o_addr[15:1], 1'b0} ] <= o_data[7:0];
        memory[ {o_addr[15:1], 1'b1} ] <= o_data[15:8];        

    end

end

endmodule
module icarus;






reg clk;
reg clock_25;
reg clock_12;
reg clock_6;


reg [3:0]   led;
reg [1:0]   keys;


reg         adc_clock_20mhz;
reg [7:0]   adc_input;


reg        sdram_clock;
reg [11:0] sdram_addr;
reg [1:0]  sdram_bank;
reg [15:0] sdram_dq;
reg        sdram_ldqm;
reg        sdram_udqm;
reg        sdram_ras;
reg        sdram_cas;
reg        sdram_we;
    

reg [4:0]  vga_red;
reg [5:0]  vga_green;
reg [4:0]  vga_blue;
reg        vga_hs;
reg        vga_vs;


reg        ftdi_rx;
reg        ftdi_tx;




reg [1:0]  usb;


reg        sound_left;
reg        sound_right;


reg [1:0]  ps2_keyb;
reg [1:0]  ps2_mouse;


always #0.5 clk         = ~clk;
always #2   clock_25    = ~clock_25;
always #4   clock_12    = ~clock_12;
always #8   clock_6     = ~clock_6;


initial begin

  clk      = 1;
  clock_25 = 0;
  clock_12 = 0;
  clock_6  = 0;
  #2000 $finish;

end 



initial
begin

    $dumpfile("icarus_result.vcd");
    $dumpvars(0, icarus);

end




reg     [15:0] i_data;
wire    [15:0] o_data;
wire    [19:0] o_addr;


processor i8086(

    clock_25,
    1'b1,
    1'b1,
    o_addr,    
    i_data,
    o_data,
    o_wr    
);




reg [7:0] memory [65535 : 0];
reg [1:0] trigger;

integer j;
initial begin

    $readmemh("icarus_memory.hex", memory);
    
end

always @(posedge clk) begin

    trigger[1:0] <= {trigger[0], o_wr};


    i_data <= {memory[ {o_addr[15:1], 1'b1} ],
               memory[ {o_addr[15:1], 1'b0} ]};


    if (trigger == 2'b01) begin
    
        memory[ {o_addr[15:1], 1'b0} ] <= o_data[7:0];
        memory[ {o_addr[15:1], 1'b1} ] <= o_data[15:8];        

    end

end

endmodule