data/full_repos/permissive/169522605/hw3_1/mux4_1.v
data/verilator_xmls/f34ffbe3-af3c-48e3-b15b-a0b2421f1fd5.xml
module mux4_1(InA, InB, InC, InD, S, Out);
    input        InA, InB, InC, InD;
    input [1:0]  S;
    output       Out;



endmodule
module mux4_1(InA, InB, InC, InD, S, Out);

    input        InA, InB, InC, InD;
    input [1:0]  S;
    output       Out;



endmodule