data/full_repos/permissive/173003307/src/processor_wrapper.v
1: b"%Error: data/full_repos/permissive/173003307/src/processor_wrapper.v:52: Duplicate declaration of signal: 'VGA_COLOUR'\n                                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire [7:0] VGA_COLOUR;\n               ^~~~~~~~~~\n        data/full_repos/permissive/173003307/src/processor_wrapper.v:34: ... Location of original declaration\n                    output [7:0] VGA_COLOUR,\n                                 ^~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module processor_wrapper(
                    input CLK,
                    input RESET,
                    output [7:0] VGA_COLOUR,
                    output VGA_HS,
                    output VGA_VS
    );
    

    wire [7:0] BUS_DATA;
    wire [7:0] BUS_ADDR;
    wire BUS_WE;
    

    wire [7:0] ROM_DATA;
    wire [7:0] ROM_ADDRESS;
    

    wire       BUS_INTERRUPT_RAISE_A;
    wire [1:0] BUS_INTERRUPTS_ACK;
    
    wire [7:0] VGA_COLOUR;
    
    Processor Processor(

                    .CLK(CLK),
                    .RESET(RESET),

                    .BUS_DATA(BUS_DATA),
                    .BUS_ADDR(BUS_ADDR),
                    .BUS_WE(BUS_WE),

                    .ROM_ADDRESS(ROM_ADDRESS),
                    .ROM_DATA(ROM_DATA),

                    .BUS_INTERRUPTS_RAISE(BUS_INTERRUPT_RAISE_A),
                    .BUS_INTERRUPTS_ACK(BUS_INTERRUPTS_ACK)
                    );

    
    timer       timer(

                    .CLK(CLK),
                    .RESET(RESET),

                    .BUS_DATA(BUS_DATA),
                    .BUS_ADDR(BUS_ADDR),
                    .BUS_WE(BUS_WE),
                    .BUS_INTERRUPT_RAISE(BUS_INTERRUPT_RAISE_A),
                    .BUS_INTERRUPT_ACK(BUS_INTERRUPTS_ACK[0])
                     );
                     
    RAM         RAM0(

                    .CLK(CLK),

                    .BUS_DATA(BUS_DATA),
                    .BUS_ADDR(BUS_ADDR),
                    .BUS_WE(BUS_WE)
                    );
                    
    ROM         ROM0(

                    .CLK(CLK),

                    .DATA(ROM_DATA),
                    .ADDR(ROM_ADDRESS)
                    );
                    
    vga_wrapper VGA(
                    .CLK(CLK),
                    .RESET(RESET),
                    .BUS_ADDR(BUS_ADDR),
                    .BUS_DATA(BUS_DATA),
                    .VGA_COLOUR(VGA_COLOUR),
                    .VGA_HS(VGA_HS),
                    .VGA_VS(VGA_VS)
                    );


endmodule
module processor_wrapper(
                    input CLK,
                    input RESET,
                    output [7:0] VGA_COLOUR,
                    output VGA_HS,
                    output VGA_VS
    );

    

    wire [7:0] BUS_DATA;
    wire [7:0] BUS_ADDR;
    wire BUS_WE;
    

    wire [7:0] ROM_DATA;
    wire [7:0] ROM_ADDRESS;
    

    wire       BUS_INTERRUPT_RAISE_A;
    wire [1:0] BUS_INTERRUPTS_ACK;
    
    wire [7:0] VGA_COLOUR;
    
    Processor Processor(

                    .CLK(CLK),
                    .RESET(RESET),

                    .BUS_DATA(BUS_DATA),
                    .BUS_ADDR(BUS_ADDR),
                    .BUS_WE(BUS_WE),

                    .ROM_ADDRESS(ROM_ADDRESS),
                    .ROM_DATA(ROM_DATA),

                    .BUS_INTERRUPTS_RAISE(BUS_INTERRUPT_RAISE_A),
                    .BUS_INTERRUPTS_ACK(BUS_INTERRUPTS_ACK)
                    );

    
    timer       timer(

                    .CLK(CLK),
                    .RESET(RESET),

                    .BUS_DATA(BUS_DATA),
                    .BUS_ADDR(BUS_ADDR),
                    .BUS_WE(BUS_WE),
                    .BUS_INTERRUPT_RAISE(BUS_INTERRUPT_RAISE_A),
                    .BUS_INTERRUPT_ACK(BUS_INTERRUPTS_ACK[0])
                     );
                     
    RAM         RAM0(

                    .CLK(CLK),

                    .BUS_DATA(BUS_DATA),
                    .BUS_ADDR(BUS_ADDR),
                    .BUS_WE(BUS_WE)
                    );
                    
    ROM         ROM0(

                    .CLK(CLK),

                    .DATA(ROM_DATA),
                    .ADDR(ROM_ADDRESS)
                    );
                    
    vga_wrapper VGA(
                    .CLK(CLK),
                    .RESET(RESET),
                    .BUS_ADDR(BUS_ADDR),
                    .BUS_DATA(BUS_DATA),
                    .VGA_COLOUR(VGA_COLOUR),
                    .VGA_HS(VGA_HS),
                    .VGA_VS(VGA_VS)
                    );


endmodule