data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_basic.v
1: b"%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_basic.v:32: Cannot find file containing module: 'uart_baud_tick_gen'\n uart_baud_tick_gen #(\n ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart,data/full_repos/permissive/104660645/uart_baud_tick_gen\n             data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart,data/full_repos/permissive/104660645/uart_baud_tick_gen.v\n             data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart,data/full_repos/permissive/104660645/uart_baud_tick_gen.sv\n             uart_baud_tick_gen\n             uart_baud_tick_gen.v\n             uart_baud_tick_gen.sv\n             obj_dir/uart_baud_tick_gen\n             obj_dir/uart_baud_tick_gen.v\n             obj_dir/uart_baud_tick_gen.sv\n%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_basic.v:42: Cannot find file containing module: 'uart_rx'\n uart_rx uart_rx_blk (\n ^~~~~~~\n%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_basic.v:57: Cannot find file containing module: 'uart_baud_tick_gen'\n uart_baud_tick_gen #(\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_basic.v:67: Cannot find file containing module: 'uart_tx'\n uart_tx uart_tx_blk (\n ^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module uart_basic
#(
	parameter CLK_FREQUENCY = 100000000,
	parameter BAUD_RATE = 115200
)(
	input clk,
	input reset,
	input rx,
	output [7:0] rx_data,
	output reg rx_ready,
	output tx,
	input tx_start,
	input [7:0] tx_data,
	output tx_busy
);

	wire baud8_tick;
	wire baud_tick;

	reg rx_ready_sync;
	wire rx_ready_pre;

	uart_baud_tick_gen #(
		.CLK_FREQUENCY(CLK_FREQUENCY),
		.BAUD_RATE(BAUD_RATE),
		.OVERSAMPLING(8)
	) baud8_tick_blk (
		.clk(clk),
		.enable(1'b1),
		.tick(baud8_tick)
	);

	uart_rx uart_rx_blk (
		.clk(clk),
		.reset(reset),
		.baud8_tick(baud8_tick),
		.rx(rx),
		.rx_data(rx_data),
		.rx_ready(rx_ready_pre)
	);

	always @(posedge clk) begin
		rx_ready_sync <= rx_ready_pre;
		rx_ready <= ~rx_ready_sync & rx_ready_pre;
	end


	uart_baud_tick_gen #(
		.CLK_FREQUENCY(CLK_FREQUENCY),
		.BAUD_RATE(BAUD_RATE),
		.OVERSAMPLING(1)
	) baud_tick_blk (
		.clk(clk),
		.enable(tx_busy),
		.tick(baud_tick)
	);

	uart_tx uart_tx_blk (
		.clk(clk),
		.reset(reset),
		.baud_tick(baud_tick),
		.tx(tx),
		.tx_start(tx_start),
		.tx_data(tx_data),
		.tx_busy(tx_busy)
	);

endmodule
module uart_basic
#(
	parameter CLK_FREQUENCY = 100000000,
	parameter BAUD_RATE = 115200
)(
	input clk,
	input reset,
	input rx,
	output [7:0] rx_data,
	output reg rx_ready,
	output tx,
	input tx_start,
	input [7:0] tx_data,
	output tx_busy
);


	wire baud8_tick;
	wire baud_tick;

	reg rx_ready_sync;
	wire rx_ready_pre;

	uart_baud_tick_gen #(
		.CLK_FREQUENCY(CLK_FREQUENCY),
		.BAUD_RATE(BAUD_RATE),
		.OVERSAMPLING(8)
	) baud8_tick_blk (
		.clk(clk),
		.enable(1'b1),
		.tick(baud8_tick)
	);

	uart_rx uart_rx_blk (
		.clk(clk),
		.reset(reset),
		.baud8_tick(baud8_tick),
		.rx(rx),
		.rx_data(rx_data),
		.rx_ready(rx_ready_pre)
	);

	always @(posedge clk) begin
		rx_ready_sync <= rx_ready_pre;
		rx_ready <= ~rx_ready_sync & rx_ready_pre;
	end


	uart_baud_tick_gen #(
		.CLK_FREQUENCY(CLK_FREQUENCY),
		.BAUD_RATE(BAUD_RATE),
		.OVERSAMPLING(1)
	) baud_tick_blk (
		.clk(clk),
		.enable(tx_busy),
		.tick(baud_tick)
	);

	uart_tx uart_tx_blk (
		.clk(clk),
		.reset(reset),
		.baud_tick(baud_tick),
		.tx(tx),
		.tx_start(tx_start),
		.tx_data(tx_data),
		.tx_busy(tx_busy)
	);

endmodule