data/full_repos/permissive/117026779/sim/lab_simulations/TestMotherboard.v
 line:77: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMotherboard.v:97: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMotherboard.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMotherboard.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMotherboard.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMotherboard.v:124: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMotherboard.v:123: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMotherboard.v:184: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/lab_simulations/TestMotherboard.v:185: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: data/full_repos/permissive/117026779/sim/lab_simulations/TestMotherboard.v:48: Cannot find file containing module: \'Motherboard\'\nMotherboard #(.CLOCK_DIVIDER(1)) motherboard(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/sim/lab_simulations,data/full_repos/permissive/117026779/Motherboard\n             data/full_repos/permissive/117026779/sim/lab_simulations,data/full_repos/permissive/117026779/Motherboard.v\n             data/full_repos/permissive/117026779/sim/lab_simulations,data/full_repos/permissive/117026779/Motherboard.sv\n             Motherboard\n             Motherboard.v\n             Motherboard.sv\n             obj_dir/Motherboard\n             obj_dir/Motherboard.v\n             obj_dir/Motherboard.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestMotherboard;

integer clock_count;
reg clk;
reg rst;
reg ps2_clk;
reg ps2_data;

wire hsync;
wire vsync;
wire [3:0] r;
wire [3:0] g;
wire [3:0] b;

Motherboard #(.CLOCK_DIVIDER(1)) motherboard(

    .clk100Mhz(clk),
    .rst(rst),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),

    .hsync(hsync),

    .vsync(vsync),

    .r(r),
    .g(g),
    .b(b),
    .clk_select(1'b1),
    .button_clock(1'b1)
);

reg [10:0] payload;

task PS2_TRANSMIT;
	input [7:0] send;
	integer k;
begin
    
    payload = {1'b1, ~^send, send[7], send[6], send[5], send[4], send[3], send[2], send[1], send[0], 1'b0};
    $display("payload = 0b%b",payload);
	for (k=0; k < 11; k = k + 1)
	begin
        CLOCK(2);
        ps2_data = payload[k];
        ps2_clk = 1;
        $display("payload = 0b%b :: send = 0b%b :: ps2_data = 0b%b :: k = %d", payload, send, ps2_data, k);
        CLOCK(2);
        ps2_clk = 0;
        CLOCK(2);
	end
    ps2_clk = 1;
    CLOCK(2);
end
endtask

task RESET;
begin
    rst = 0;
    clock_count = 0;
    clk = 0;
    ps2_clk = 1;
    ps2_data = 1;
    #5
    rst = 1;
    #5
    rst = 0;
    clk = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		clock_count = clock_count + 1;
		#5
		clk = 0;
	end
end
endtask

parameter FULL_CYCLE = 32'd5000;

initial begin
    #10
    #10
	RESET;
	CLOCK(FULL_CYCLE);

    PS2_TRANSMIT(`A_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`A_SCAN_CODE);

    PS2_TRANSMIT(`B_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`B_SCAN_CODE);

    PS2_TRANSMIT(`C_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`C_SCAN_CODE);

    PS2_TRANSMIT(`D_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`D_SCAN_CODE);

    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);

    PS2_TRANSMIT(`E_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`E_SCAN_CODE);

    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);

    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);

    PS2_TRANSMIT(`NEWLINE_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`NEWLINE_SCAN_CODE);
    CLOCK(20);

	CLOCK(FULL_CYCLE);
    #10 $stop;
    #5 $finish;
end

endmodule
module TestMotherboard;


integer clock_count;
reg clk;
reg rst;
reg ps2_clk;
reg ps2_data;

wire hsync;
wire vsync;
wire [3:0] r;
wire [3:0] g;
wire [3:0] b;

Motherboard #(.CLOCK_DIVIDER(1)) motherboard(

    .clk100Mhz(clk),
    .rst(rst),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),

    .hsync(hsync),

    .vsync(vsync),

    .r(r),
    .g(g),
    .b(b),
    .clk_select(1'b1),
    .button_clock(1'b1)
);

reg [10:0] payload;

task PS2_TRANSMIT;
	input [7:0] send;
	integer k;
begin
    
    payload = {1'b1, ~^send, send[7], send[6], send[5], send[4], send[3], send[2], send[1], send[0], 1'b0};
    $display("payload = 0b%b",payload);
	for (k=0; k < 11; k = k + 1)
	begin
        CLOCK(2);
        ps2_data = payload[k];
        ps2_clk = 1;
        $display("payload = 0b%b :: send = 0b%b :: ps2_data = 0b%b :: k = %d", payload, send, ps2_data, k);
        CLOCK(2);
        ps2_clk = 0;
        CLOCK(2);
	end
    ps2_clk = 1;
    CLOCK(2);
end
endtask

task RESET;
begin
    rst = 0;
    clock_count = 0;
    clk = 0;
    ps2_clk = 1;
    ps2_data = 1;
    #5
    rst = 1;
    #5
    rst = 0;
    clk = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		clock_count = clock_count + 1;
		#5
		clk = 0;
	end
end
endtask

parameter FULL_CYCLE = 32'd5000;

initial begin
    #10
    #10
	RESET;
	CLOCK(FULL_CYCLE);

    PS2_TRANSMIT(`A_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`A_SCAN_CODE);

    PS2_TRANSMIT(`B_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`B_SCAN_CODE);

    PS2_TRANSMIT(`C_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`C_SCAN_CODE);

    PS2_TRANSMIT(`D_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`D_SCAN_CODE);

    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);

    PS2_TRANSMIT(`E_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`E_SCAN_CODE);

    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);

    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);

    PS2_TRANSMIT(`NEWLINE_SCAN_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`BREAK_CODE);
    CLOCK(10);
    PS2_TRANSMIT(`NEWLINE_SCAN_CODE);
    CLOCK(20);

	CLOCK(FULL_CYCLE);
    #10 $stop;
    #5 $finish;
end

endmodule