data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v
1: b'%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:43: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                               : ... In instance insert_value\n            In1 <= 1\'b0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:47: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                               : ... In instance insert_value\n            In1 <= 1\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:44: Operator EQ expects 11 bits on the RHS, but RHS\'s CONST \'10\'h13f\' generates 10 bits.\n                                                                                               : ... In instance insert_value\n        else if(counter == 10\'d319)\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:54: Operator EQ expects 11 bits on the RHS, but RHS\'s CONST \'10\'h12c\' generates 10 bits.\n                                                                                               : ... In instance insert_value\n        else if(counter == 10\'d300)\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:65: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                               : ... In instance insert_value\n            counter <= 1\'b0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:67: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                               : ... In instance insert_value\n            counter <= 1\'b0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:75: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                               : ... In instance insert_value\n            counter_1 <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:77: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                               : ... In instance insert_value\n            counter_1 <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:88: Operator EQ expects 11 bits on the RHS, but RHS\'s CONST \'10\'h276\' generates 10 bits.\n                                                                                               : ... In instance insert_value\n        else if(counter == 11\'d310 || counter == 10\'d630)\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:86: Operator EQ expects 11 bits on the RHS, but RHS\'s CONST \'10\'h96\' generates 10 bits.\n                                                                                               : ... In instance insert_value\n        else if(counter == 10\'d150 || counter == 10\'d470)\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:86: Operator EQ expects 11 bits on the RHS, but RHS\'s CONST \'10\'h1d6\' generates 10 bits.\n                                                                                               : ... In instance insert_value\n        else if(counter == 10\'d150 || counter == 10\'d470)\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:107: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance insert_value\n            In2 <= 1\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:111: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance insert_value\n            In2 <= 1\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:110: Operator EQ expects 11 bits on the RHS, but RHS\'s CONST \'10\'h27f\' generates 10 bits.\n                                                                                                : ... In instance insert_value\n        else if(counter == 11\'d319 || counter == 10\'d639)\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:108: Operator EQ expects 11 bits on the RHS, but RHS\'s CONST \'10\'h9f\' generates 10 bits.\n                                                                                                : ... In instance insert_value\n        else if(counter == 10\'d159 || counter == 10\'d479)\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/176606610/ip_repo/axi_datatran/src/insert_value.v:108: Operator EQ expects 11 bits on the RHS, but RHS\'s CONST \'10\'h1df\' generates 10 bits.\n                                                                                                : ... In instance insert_value\n        else if(counter == 10\'d159 || counter == 10\'d479)\n                                              ^~\n%Error: Exiting due to 16 warning(s)\n'
module insert_value(
        input clk,
        input rst_n,
        input signed [15:0] inpsig,
        output reg signed  [15:0] In1,
        output reg signed [15:0] In2,
        input signed [15:0] Out1,
        output reg enb_hbf1,
        output reg enb_hbf2,
        output reg enb_cic8
    );
    
    reg [10:0] counter;
    reg [4:0] counter_1;
    parameter CNT_END = 639;
    

    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            In1 <= 1'b0;
        else if(counter == 10'd319)
            In1 <= inpsig;
        else if(counter == 11'd639)
            In1 <= 1'b0;
    end
    
        always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            enb_hbf1 <= 1'b0;
        else if(counter == 10'd300)
            enb_hbf1 <= 1'b1;
        else if(counter == 11'd620)
            enb_hbf1 <= 1'b1;
        else
            enb_hbf1 <= 1'b0;
    end
    
    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            counter <= 1'b0;
        else if(counter == CNT_END)
            counter <= 1'b0;
        else
            counter <= counter + 1'b1;
    end

    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            counter_1 <= 1'b0;
        else if(counter_1 == 5'd19)
            counter_1 <= 1'b0;
        else
            counter_1 <= counter_1 + 1'b1;
    end
    
    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            enb_hbf2 <= 1'b0;
        else if(counter == 10'd150 || counter == 10'd470)
            enb_hbf2 <= 1'b1;
        else if(counter == 11'd310 || counter == 10'd630)
            enb_hbf2 <= 1'b1;
        else
            enb_hbf2 <= 1'b0;
    end
    
    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            enb_cic8 <= 1'b0;
        else if(counter_1 == 5'd5)
            enb_cic8 <= 1'b1;
        else
            enb_cic8 <= 1'b0;
    end
    
    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            In2 <= 1'b0;
        else if(counter == 10'd159 || counter == 10'd479)
            In2 <= Out1;
        else if(counter == 11'd319 || counter == 10'd639)
            In2 <= 1'b0;
    end
    
endmodule
module insert_value(
        input clk,
        input rst_n,
        input signed [15:0] inpsig,
        output reg signed  [15:0] In1,
        output reg signed [15:0] In2,
        input signed [15:0] Out1,
        output reg enb_hbf1,
        output reg enb_hbf2,
        output reg enb_cic8
    );

    
    reg [10:0] counter;
    reg [4:0] counter_1;
    parameter CNT_END = 639;
    

    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            In1 <= 1'b0;
        else if(counter == 10'd319)
            In1 <= inpsig;
        else if(counter == 11'd639)
            In1 <= 1'b0;
    end
    
        always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            enb_hbf1 <= 1'b0;
        else if(counter == 10'd300)
            enb_hbf1 <= 1'b1;
        else if(counter == 11'd620)
            enb_hbf1 <= 1'b1;
        else
            enb_hbf1 <= 1'b0;
    end
    
    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            counter <= 1'b0;
        else if(counter == CNT_END)
            counter <= 1'b0;
        else
            counter <= counter + 1'b1;
    end

    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            counter_1 <= 1'b0;
        else if(counter_1 == 5'd19)
            counter_1 <= 1'b0;
        else
            counter_1 <= counter_1 + 1'b1;
    end
    
    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            enb_hbf2 <= 1'b0;
        else if(counter == 10'd150 || counter == 10'd470)
            enb_hbf2 <= 1'b1;
        else if(counter == 11'd310 || counter == 10'd630)
            enb_hbf2 <= 1'b1;
        else
            enb_hbf2 <= 1'b0;
    end
    
    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            enb_cic8 <= 1'b0;
        else if(counter_1 == 5'd5)
            enb_cic8 <= 1'b1;
        else
            enb_cic8 <= 1'b0;
    end
    
    always@(posedge clk, negedge rst_n)
    begin
        if(!rst_n)
            In2 <= 1'b0;
        else if(counter == 10'd159 || counter == 10'd479)
            In2 <= Out1;
        else if(counter == 11'd319 || counter == 10'd639)
            In2 <= 1'b0;
    end
    
endmodule