data/full_repos/permissive/120518070/main/source/RC4.sv
None: at end of input
1: b"%Error: data/full_repos/permissive/120518070/main/source/RC4.sv:31: Cannot find file containing module: 'RC4_CORE'\n  RC4_CORE DUT_core (.clk(clk),.n_rst_i(n_rst_i),.rc4_dfb_i(rc4_dfb_i),.rc4_start_i(rc4_start_i),.rc4_rdata_i(rc4_rdata_i),.sarrGenerated_i(sarrGenerated),\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/RC4_CORE\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/RC4_CORE.v\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/RC4_CORE.sv\n             RC4_CORE\n             RC4_CORE.v\n             RC4_CORE.sv\n             obj_dir/RC4_CORE\n             obj_dir/RC4_CORE.v\n             obj_dir/RC4_CORE.sv\n%Error: data/full_repos/permissive/120518070/main/source/RC4.sv:36: Cannot find file containing module: 'RC4_gen_pseudo_rand_module'\n RC4_gen_pseudo_rand_module DUT_gpr (.clk(clk),.n_rst(n_rst_i),.genStateArr_i(genStateArr),.genVal_i(genVal),\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module RC4(
	input wire clk,
	input wire n_rst_i,
	input wire [19:0] img_width_i,
	input wire [19:0] img_hight_i,
	input wire rc4_dfb_i,
	input wire [31:0] rc4_rdata_i,
	input wire rc4_start_i,
	input wire [31:0] rc4_key,
	output reg [1:0] rc4_mode_o,	
	output reg [31:0] rc4_wdata_o,
	output reg [19:0] rc4_pix_num_o,
	output reg rc4_done_o
	);

	wire sarrGenerated;
	wire valReady;
	wire [7:0] outputToXor;
	wire genVal;
	wire genStateArr;

	 RC4_CORE DUT_core (.clk(clk),.n_rst_i(n_rst_i),.rc4_dfb_i(rc4_dfb_i),.rc4_start_i(rc4_start_i),.rc4_rdata_i(rc4_rdata_i),.sarrGenerated_i(sarrGenerated),
			.valReady_i(valReady),.outputToXor_i(outputToXor),.img_width_i(img_width_i),.img_hight_i(img_hight_i),
			.rc4_wdata_o(rc4_wdata_o),.rc4_pix_num_o(rc4_pix_num_o),.rc4_mode_o(rc4_mode_o),
			.rc4_done_o(rc4_done_o),.genVal_o(genVal),.genStateArr_o(genStateArr));

	RC4_gen_pseudo_rand_module DUT_gpr (.clk(clk),.n_rst(n_rst_i),.genStateArr_i(genStateArr),.genVal_i(genVal),
					.rc4_key_i_(rc4_key),.outputToXor_o(outputToXor),.sarrGenerated_o_(sarrGenerated),.valReady_o_(valReady));

endmodule
module RC4(
	input wire clk,
	input wire n_rst_i,
	input wire [19:0] img_width_i,
	input wire [19:0] img_hight_i,
	input wire rc4_dfb_i,
	input wire [31:0] rc4_rdata_i,
	input wire rc4_start_i,
	input wire [31:0] rc4_key,
	output reg [1:0] rc4_mode_o,	
	output reg [31:0] rc4_wdata_o,
	output reg [19:0] rc4_pix_num_o,
	output reg rc4_done_o
	);


	wire sarrGenerated;
	wire valReady;
	wire [7:0] outputToXor;
	wire genVal;
	wire genStateArr;

	 RC4_CORE DUT_core (.clk(clk),.n_rst_i(n_rst_i),.rc4_dfb_i(rc4_dfb_i),.rc4_start_i(rc4_start_i),.rc4_rdata_i(rc4_rdata_i),.sarrGenerated_i(sarrGenerated),
			.valReady_i(valReady),.outputToXor_i(outputToXor),.img_width_i(img_width_i),.img_hight_i(img_hight_i),
			.rc4_wdata_o(rc4_wdata_o),.rc4_pix_num_o(rc4_pix_num_o),.rc4_mode_o(rc4_mode_o),
			.rc4_done_o(rc4_done_o),.genVal_o(genVal),.genStateArr_o(genStateArr));

	RC4_gen_pseudo_rand_module DUT_gpr (.clk(clk),.n_rst(n_rst_i),.genStateArr_i(genStateArr),.genVal_i(genVal),
					.rc4_key_i_(rc4_key),.outputToXor_o(outputToXor),.sarrGenerated_o_(sarrGenerated),.valReady_o_(valReady));

endmodule