data/full_repos/permissive/157005262/verilog/counter.v
data/verilator_xmls/4eb96f57-7270-48f9-abe5-2ea4748bc3da.xml
module counter(input wire       clk,
               input wire       en,
               input wire       rst,
               output reg [3:0] count);

endmodule
module counter(input wire       clk,
               input wire       en,
               input wire       rst,
               output reg [3:0] count);


endmodule