data/full_repos/permissive/204608363/64_4 ag4bits data32bits fixedpt/qtable.v
1: b'%Error: Cannot find file containing module: ag4bits\n        ... Looked in:\n             data/full_repos/permissive/204608363/64_4/ag4bits\n             data/full_repos/permissive/204608363/64_4/ag4bits.v\n             data/full_repos/permissive/204608363/64_4/ag4bits.sv\n             ag4bits\n             ag4bits.v\n             ag4bits.sv\n             obj_dir/ag4bits\n             obj_dir/ag4bits.v\n             obj_dir/ag4bits.sv\n%Error: Cannot find file containing module: data32bits\n%Error: Cannot find file containing module: fixedpt,data/full_repos/permissive/204608363\n%Error: Cannot find file containing module: data/full_repos/permissive/204608363/64_4\n%Error: Cannot find file containing module: fixedpt/qtable.v\n%Error: Exiting due to 5 error(s)\n'
module qtable #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, DEPTH = 256) (
    input wire i_clk,
    input wire i_rst,
    input wire [ADDR_WIDTH-1:0] i_addr_r, 
    input wire [ADDR_WIDTH-1:0] i_addr_w, 
    input wire i_read_en,
    input wire i_write_en,
    input wire [DATA_WIDTH-1:0] i_data,
    output reg [DATA_WIDTH-1:0] o_data

    ); 
    integer i;
    reg [DATA_WIDTH-1:0] memory_array [0:DEPTH-1]; 
    

    generate

     integer ii;
     initial
        for (ii=0;ii<DEPTH;ii=ii+1) begin
            memory_array[ii] <= {DATA_WIDTH{1'b0}};
        end    
    endgenerate     
    always @ (posedge i_clk)
    begin

            if(i_write_en) begin
                memory_array[i_addr_w] <= i_data;
                $display("q written %02h in: %08b", i_data, i_addr_w);
            end
            if(i_read_en) begin
                o_data <= memory_array[i_addr_r];
                $display("q read %02h from: %08b", o_data, i_addr_r);
            end     
    end
endmodule
module qtable #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, DEPTH = 256) (
    input wire i_clk,
    input wire i_rst,
    input wire [ADDR_WIDTH-1:0] i_addr_r, 
    input wire [ADDR_WIDTH-1:0] i_addr_w, 
    input wire i_read_en,
    input wire i_write_en,
    input wire [DATA_WIDTH-1:0] i_data,
    output reg [DATA_WIDTH-1:0] o_data

    );
 
    integer i;
    reg [DATA_WIDTH-1:0] memory_array [0:DEPTH-1]; 
    

    generate

     integer ii;
     initial
        for (ii=0;ii<DEPTH;ii=ii+1) begin
            memory_array[ii] <= {DATA_WIDTH{1'b0}};
        end    
    endgenerate     
    always @ (posedge i_clk)
    begin

            if(i_write_en) begin
                memory_array[i_addr_w] <= i_data;
                $display("q written %02h in: %08b", i_data, i_addr_w);
            end
            if(i_read_en) begin
                o_data <= memory_array[i_addr_r];
                $display("q read %02h from: %08b", o_data, i_addr_r);
            end     
    end
endmodule