data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-2_flip-flops/flip-flops.v:47: Multiple top level modules\n                                                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                               : ... Top module \'srff\'\nmodule srff (\n       ^~~~\n                                                                                                               : ... Top module \'jkff\'\nmodule jkff (\n       ^~~~\n                                                                                                               : ... Top module \'dff\'\nmodule dff (\n       ^~~\n                                                                                                               : ... Top module \'tff\'\nmodule tff (\n       ^~~\n%Error: Exiting due to 1 warning(s)\n'
module jkff (
    input wire ck,
    input wire j,
    input wire k,
    input wire cl,
    input wire pr,
    output reg q
    );

    always @(posedge ck, negedge cl, negedge pr)
        if (!cl)
            q <= 1'b0;
        else if (!pr)
            q <= 1'b1;
        else
            case ({j, k})
            2'b01: q <= 1'b0;
            2'b10: q <= 1'b1;
            2'b11: q <= ~q;
            endcase
endmodule
module jkff (
    input wire ck,
    input wire j,
    input wire k,
    input wire cl,
    input wire pr,
    output reg q
    );


    always @(posedge ck, negedge cl, negedge pr)
        if (!cl)
            q <= 1'b0;
        else if (!pr)
            q <= 1'b1;
        else
            case ({j, k})
            2'b01: q <= 1'b0;
            2'b10: q <= 1'b1;
            2'b11: q <= ~q;
            endcase
endmodule