data/full_repos/permissive/109936328/pipeline/wb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/pipeline/wb.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:2: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:27: Define or directive not defined: \'`ADDR_W\'\n  input [`ADDR_W - 1:0] i_pc;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:28: Define or directive not defined: \'`INSTR_W\'\n  input [`INSTR_W - 1:0] i_instr;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:30: Define or directive not defined: \'`DEST_SRC_W\'\n  input [`DEST_SRC_W - 1:0] i_dest_src;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:31: Define or directive not defined: \'`REG_IDX_W\'\n  input [`REG_IDX_W - 1:0] i_dest_reg;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:33: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_dest_data;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:35: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] r_pc;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:36: Define or directive not defined: \'`INSTR_W\'\n  reg [`INSTR_W - 1:0] r_instr;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:38: Define or directive not defined: \'`DEST_SRC_W\'\n  reg [`DEST_SRC_W - 1:0] r_dest_src;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:39: Define or directive not defined: \'`REG_IDX_W\'\n  reg [`REG_IDX_W - 1:0] r_dest_reg;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:41: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] r_dest_data;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:43: Define or directive not defined: \'`ADDR_W\'\n  output [`ADDR_W - 1:0] o_pc;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:44: Define or directive not defined: \'`INSTR_W\'\n  output [`INSTR_W - 1:0] o_instr;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:47: Define or directive not defined: \'`REG_IDX_W\'\n  output [`REG_IDX_W - 1:0] o_dest_reg;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:48: Define or directive not defined: \'`WORD_W\'\n  output [`WORD_W - 1:0] o_dest_data;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:53: Define or directive not defined: \'`DEST_SRC_NONE\'\n  assign o_dest_en = r_dest_src != `DEST_SRC_NONE;\n                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  assign o_dest_en = r_dest_src != `DEST_SRC_NONE;\n                                                 ^\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:62: Define or directive not defined: \'`DEST_SRC_NONE\'\n      r_dest_src <= `DEST_SRC_NONE;\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/wb.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      r_dest_src <= `DEST_SRC_NONE;\n                                  ^\n%Error: Exiting due to 20 error(s)\n'
module wb(
  clk,
  clr,

  i_pc,
  i_instr,

  i_dest_src,
  i_dest_reg,

  i_dest_data,

  o_pc,
  o_instr,

  o_dest_en,
  o_dest_reg,
  o_dest_data
);

  input clk;
  input clr;

  input [`ADDR_W - 1:0] i_pc;
  input [`INSTR_W - 1:0] i_instr;

  input [`DEST_SRC_W - 1:0] i_dest_src;
  input [`REG_IDX_W - 1:0] i_dest_reg;

  input [`WORD_W - 1:0] i_dest_data;

  reg [`ADDR_W - 1:0] r_pc;
  reg [`INSTR_W - 1:0] r_instr;

  reg [`DEST_SRC_W - 1:0] r_dest_src;
  reg [`REG_IDX_W - 1:0] r_dest_reg;

  reg [`WORD_W - 1:0] r_dest_data;

  output [`ADDR_W - 1:0] o_pc;
  output [`INSTR_W - 1:0] o_instr;

  output o_dest_en;
  output [`REG_IDX_W - 1:0] o_dest_reg;
  output [`WORD_W - 1:0] o_dest_data;

  assign o_pc = r_pc;
  assign o_instr = r_instr;

  assign o_dest_en = r_dest_src != `DEST_SRC_NONE;
  assign o_dest_reg = r_dest_reg;
  assign o_dest_data = r_dest_data;

  always@(posedge clk) begin
    if(clr == 1) begin
      r_pc <= 0;
      r_instr <= 0;

      r_dest_src <= `DEST_SRC_NONE;
      r_dest_reg <= 0;

      r_dest_data <= 0;
    end else begin
      r_pc <= i_pc;
      r_instr <= i_instr;

      r_dest_src <= i_dest_src;
      r_dest_reg <= i_dest_reg;

      r_dest_data <= i_dest_data;
    end
  end

endmodule
module wb(
  clk,
  clr,

  i_pc,
  i_instr,

  i_dest_src,
  i_dest_reg,

  i_dest_data,

  o_pc,
  o_instr,

  o_dest_en,
  o_dest_reg,
  o_dest_data
);


  input clk;
  input clr;

  input [`ADDR_W - 1:0] i_pc;
  input [`INSTR_W - 1:0] i_instr;

  input [`DEST_SRC_W - 1:0] i_dest_src;
  input [`REG_IDX_W - 1:0] i_dest_reg;

  input [`WORD_W - 1:0] i_dest_data;

  reg [`ADDR_W - 1:0] r_pc;
  reg [`INSTR_W - 1:0] r_instr;

  reg [`DEST_SRC_W - 1:0] r_dest_src;
  reg [`REG_IDX_W - 1:0] r_dest_reg;

  reg [`WORD_W - 1:0] r_dest_data;

  output [`ADDR_W - 1:0] o_pc;
  output [`INSTR_W - 1:0] o_instr;

  output o_dest_en;
  output [`REG_IDX_W - 1:0] o_dest_reg;
  output [`WORD_W - 1:0] o_dest_data;

  assign o_pc = r_pc;
  assign o_instr = r_instr;

  assign o_dest_en = r_dest_src != `DEST_SRC_NONE;
  assign o_dest_reg = r_dest_reg;
  assign o_dest_data = r_dest_data;

  always@(posedge clk) begin
    if(clr == 1) begin
      r_pc <= 0;
      r_instr <= 0;

      r_dest_src <= `DEST_SRC_NONE;
      r_dest_reg <= 0;

      r_dest_data <= 0;
    end else begin
      r_pc <= i_pc;
      r_instr <= i_instr;

      r_dest_src <= i_dest_src;
      r_dest_reg <= i_dest_reg;

      r_dest_data <= i_dest_data;
    end
  end

endmodule