data/full_repos/permissive/143278/ivltests/pr1703346.v
 line:5: before: "("
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr1703346.v:5: Unsupported: Verilog 1995 strength specifiers\n   assign     (highz0, strong1) foo[0] = 2\'b01;\n               ^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1703346.v:5: Unsupported: Verilog 1995 strength specifiers\n   assign     (highz0, strong1) foo[0] = 2\'b01;\n                       ^~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1703346.v:6: Unsupported: Verilog 1995 strength specifiers\n   assign     (strong0, highz1) foo[0] = 2\'b01;\n               ^~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1703346.v:6: Unsupported: Verilog 1995 strength specifiers\n   assign     (strong0, highz1) foo[0] = 2\'b01;\n                        ^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1703346.v:8: Unsupported: Verilog 1995 strength specifiers\n   assign     (highz0, strong1) foo[1] = 2\'b10;\n               ^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1703346.v:8: Unsupported: Verilog 1995 strength specifiers\n   assign     (highz0, strong1) foo[1] = 2\'b10;\n                       ^~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1703346.v:9: Unsupported: Verilog 1995 strength specifiers\n   assign     (strong0, highz1) foo[1] = 2\'b10;\n               ^~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1703346.v:9: Unsupported: Verilog 1995 strength specifiers\n   assign     (strong0, highz1) foo[1] = 2\'b10;\n                        ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1703346.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("foo[0] = %b, foo[1] = %b", foo[0], foo[1]);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 8 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire [1:0] foo [0:1];

   assign     (highz0, strong1) foo[0] = 2'b01;
   assign     (strong0, highz1) foo[0] = 2'b01;

   assign     (highz0, strong1) foo[1] = 2'b10;
   assign     (strong0, highz1) foo[1] = 2'b10;

   initial begin
      #1 $display("foo[0] = %b, foo[1] = %b", foo[0], foo[1]);

      if (foo[0] !== 2'b01) begin
	 $display("FAILED -- foo[0] = %b", foo[0]);
	 $finish;
      end

      if (foo[1] !== 2'b10) begin
	 $display("FAILED == foo[1] = %b", foo[1]);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   wire [1:0] foo [0:1];

   assign     (highz0, strong1) foo[0] = 2'b01;
   assign     (strong0, highz1) foo[0] = 2'b01;

   assign     (highz0, strong1) foo[1] = 2'b10;
   assign     (strong0, highz1) foo[1] = 2'b10;

   initial begin
      #1 $display("foo[0] = %b, foo[1] = %b", foo[0], foo[1]);

      if (foo[0] !== 2'b01) begin
	 $display("FAILED -- foo[0] = %b", foo[0]);
	 $finish;
      end

      if (foo[1] !== 2'b10) begin
	 $display("FAILED == foo[1] = %b", foo[1]);
	 $finish;
      end

      $display("PASSED");
   end

endmodule