data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire/raw_acquire.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire/raw_acquire.v:47: Cannot find include file: tartcfg.v\n`include "tartcfg.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Error: Exiting due to 1 error(s)\n'
module raw_acquire
  #(
    parameter AXNUM = 24,
    parameter MSB   = AXNUM-1,
    parameter ABITS = 20,

    parameter ASB   = ABITS-1,


    parameter RESET = 0,


    parameter DELAY = 3)
   (
    input          clock_i,
    input          reset_i,


    input          capture_i,
    input          request_i,



    input          locked_i,
    input          strobe_i,
    input          middle_i,
    input [MSB:0]  signal_i,


    output         mcb_ce_o,
    output         mcb_wr_o,
    input          mcb_rdy_i,
    output [ASB:0] mcb_adr_o,
    output [31:0]  mcb_dat_o,


    output         oflow_o,
    output [2:0]   state_o
    );


`ifdef __USE_ACQUISITION



   wire [MSB:0]    rdata;
   wire [8:0]      raddr, waddr;







   block_buffer AQ_BB
     (
       .read_clock_i   (clock_i),
       .read_address_i (raddr),
       .read_data_o    (rdata),

       .write_clock_i  (clock_i),
       .write_enable_i (middle_i),
       .write_address_i(waddr),
       .write_data_i   (signal_i)
       );






   fifo_control
     #(.SDRAM_ADDRESS_WIDTH(ABITS+1))
   SCHEDULER0
     ( .clock_i (clock_i),
       .reset_i (reset_i),
       .enable_i(capture_i),
       .strobe_i(strobe_i),

       .bb_rd_adr_o(raddr),
       .bb_wr_adr_o(waddr),
       .bb_rd_dat_i(rdata),

       .aq_rd_req_i(request_i),

       .cmd_request(mcb_ce_o),
       .cmd_write  (mcb_wr_o),
       .cmd_waiting(mcb_rdy_i),
       .cmd_address(mcb_adr_o),
       .cmd_data_in(mcb_dat_o),

       .overflow_o (oflow_o),
       .aq_state_o (state_o)
       );


`else




   assign mcb_ce_o  = 1'b0;
   assign mcb_wr_o  = 1'b0;
   assign mcb_adr_o = {(ABITS-1){1'b0}};
   assign mcb_dat_o = {32{1'b0}};

`endif


endmodule
module raw_acquire
  #(
    parameter AXNUM = 24,
    parameter MSB   = AXNUM-1,
    parameter ABITS = 20,

    parameter ASB   = ABITS-1,


    parameter RESET = 0,


    parameter DELAY = 3)
   (
    input          clock_i,
    input          reset_i,


    input          capture_i,
    input          request_i,



    input          locked_i,
    input          strobe_i,
    input          middle_i,
    input [MSB:0]  signal_i,


    output         mcb_ce_o,
    output         mcb_wr_o,
    input          mcb_rdy_i,
    output [ASB:0] mcb_adr_o,
    output [31:0]  mcb_dat_o,


    output         oflow_o,
    output [2:0]   state_o
    );



`ifdef __USE_ACQUISITION



   wire [MSB:0]    rdata;
   wire [8:0]      raddr, waddr;







   block_buffer AQ_BB
     (
       .read_clock_i   (clock_i),
       .read_address_i (raddr),
       .read_data_o    (rdata),

       .write_clock_i  (clock_i),
       .write_enable_i (middle_i),
       .write_address_i(waddr),
       .write_data_i   (signal_i)
       );






   fifo_control
     #(.SDRAM_ADDRESS_WIDTH(ABITS+1))
   SCHEDULER0
     ( .clock_i (clock_i),
       .reset_i (reset_i),
       .enable_i(capture_i),
       .strobe_i(strobe_i),

       .bb_rd_adr_o(raddr),
       .bb_wr_adr_o(waddr),
       .bb_rd_dat_i(rdata),

       .aq_rd_req_i(request_i),

       .cmd_request(mcb_ce_o),
       .cmd_write  (mcb_wr_o),
       .cmd_waiting(mcb_rdy_i),
       .cmd_address(mcb_adr_o),
       .cmd_data_in(mcb_dat_o),

       .overflow_o (oflow_o),
       .aq_state_o (state_o)
       );


`else




   assign mcb_ce_o  = 1'b0;
   assign mcb_wr_o  = 1'b0;
   assign mcb_adr_o = {(ABITS-1){1'b0}};
   assign mcb_dat_o = {32{1'b0}};

`endif


endmodule