data/full_repos/permissive/114642806/dev/milestone2/fsm.v
1: b"%Error: data/full_repos/permissive/114642806/dev/milestone2/fsm.v:23: Cannot find file containing module: 'counter10s'\ncounter10s c10(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114642806/dev/milestone2,data/full_repos/permissive/114642806/counter10s\n             data/full_repos/permissive/114642806/dev/milestone2,data/full_repos/permissive/114642806/counter10s.v\n             data/full_repos/permissive/114642806/dev/milestone2,data/full_repos/permissive/114642806/counter10s.sv\n             counter10s\n             counter10s.v\n             counter10s.sv\n             obj_dir/counter10s\n             obj_dir/counter10s.v\n             obj_dir/counter10s.sv\n%Error: Exiting due to 1 error(s)\n"
module control(clk, go, resetn, counter10, counter5, ledIn);
input clk, go, resetn, counter10, counter5;
output reg [2:0] ledIn;

reg [2:0] current_state, next_state;

localparam  N_GREEN        = 3'd0,
            N_YELLOW       = 3'd1,
            RED_1          = 3'd2,
            E_LEFT         = 3'd3,
            E_GREEN        = 3'd4,
            E_YELLOW       = 3'd5,
            RED_2          = 3'd6,
            N_LEFT         = 3'd7;

always@(*)
begin: state_table
        case (current_state)
            N_GREEN: next_state = go ? N_YELLOW : N_GREEN;
            N_YELLOW: next_state = counter10 ? RED_1: N_YELLOW;
            RED_1: next_state = counter5 ? E_LEFT: RED_1;
            E_LEFT: next_state = counter10 ? E_GREEN: E_LEFT;
            E_GREEN: next_state = counter5 ? E_YELLOW: E_GREEN;
            E_YELLOW: next_state = counter10 ? RED_2: E_YELLOW;
            RED_2: next_state = counter5 ? N_LEFT: RED_2;
            N_LEFT: next_state = counter10 ? N_GREEN: N_LEFT;
        default:     next_state = N_GREEN;
    endcase
end

always @(*)
begin: enable_signals

    ledIn[0] = 1'b0;
    ledIn[1] = 1'b0;
    ledIn[2] = 1'b0;

    case (current_state)
        N_GREEN: begin
            ledIn[0] = 1'b0;
            ledIn[1] = 1'b0;
            ledIn[2] = 1'b0;
          end
        N_YELLOW: begin
            ledIn[0] = 1'b1;
            ledIn[1] = 1'b0;
            ledIn[2] = 1'b0;
          end
        RED_1: begin
            ledIn[0] = 1'b0;
            ledIn[1] = 1'b1;
            ledIn[2] = 1'b0;
          end
        E_LEFT: begin
            ledIn[0] = 1'b1;
            ledIn[1] = 1'b1;
            ledIn[2] = 1'b0;
          end
        E_GREEN: begin
            ledIn[0] = 1'b0;
            ledIn[1] = 1'b0;
            ledIn[2] = 1'b1;
          end
        E_YELLOW: begin
            ledIn[0] = 1'b1;
            ledIn[1] = 1'b0;
            ledIn[2] = 1'b1;
          end
        RED_2: begin
            ledIn[0] = 1'b0;
            ledIn[1] = 1'b1;
            ledIn[2] = 1'b1;
          end
        N_LEFT: begin
            ledIn[0] = 1'b1;
            ledIn[1] = 1'b1;
            ledIn[2] = 1'b1;
            end
    default: begin
            ledIn[0] = 1'b0;
            ledIn[1] = 1'b0;
            ledIn[2] = 1'b0;
            end
    endcase
end


always@(posedge clk)
begin: state_FFs
    if(!resetn)
        current_state <= N_GREEN;
    else
        current_state <= next_state;
end
endmodule
module control(clk, go, resetn, counter10, counter5, ledIn);

input clk, go, resetn, counter10, counter5;
output reg [2:0] ledIn;

reg [2:0] current_state, next_state;

localparam  N_GREEN        = 3'd0,
            N_YELLOW       = 3'd1,
            RED_1          = 3'd2,
            E_LEFT         = 3'd3,
            E_GREEN        = 3'd4,
            E_YELLOW       = 3'd5,
            RED_2          = 3'd6,
            N_LEFT         = 3'd7;

always@(*)
begin: state_table
        case (current_state)
            N_GREEN: next_state = go ? N_YELLOW : N_GREEN;
            N_YELLOW: next_state = counter10 ? RED_1: N_YELLOW;
            RED_1: next_state = counter5 ? E_LEFT: RED_1;
            E_LEFT: next_state = counter10 ? E_GREEN: E_LEFT;
            E_GREEN: next_state = counter5 ? E_YELLOW: E_GREEN;
            E_YELLOW: next_state = counter10 ? RED_2: E_YELLOW;
            RED_2: next_state = counter5 ? N_LEFT: RED_2;
            N_LEFT: next_state = counter10 ? N_GREEN: N_LEFT;
        default:     next_state = N_GREEN;
    endcase
end

always @(*)
begin: enable_signals

    ledIn[0] = 1'b0;
    ledIn[1] = 1'b0;
    ledIn[2] = 1'b0;

    case (current_state)
        N_GREEN: begin
            ledIn[0] = 1'b0;
            ledIn[1] = 1'b0;
            ledIn[2] = 1'b0;
          end
        N_YELLOW: begin
            ledIn[0] = 1'b1;
            ledIn[1] = 1'b0;
            ledIn[2] = 1'b0;
          end
        RED_1: begin
            ledIn[0] = 1'b0;
            ledIn[1] = 1'b1;
            ledIn[2] = 1'b0;
          end
        E_LEFT: begin
            ledIn[0] = 1'b1;
            ledIn[1] = 1'b1;
            ledIn[2] = 1'b0;
          end
        E_GREEN: begin
            ledIn[0] = 1'b0;
            ledIn[1] = 1'b0;
            ledIn[2] = 1'b1;
          end
        E_YELLOW: begin
            ledIn[0] = 1'b1;
            ledIn[1] = 1'b0;
            ledIn[2] = 1'b1;
          end
        RED_2: begin
            ledIn[0] = 1'b0;
            ledIn[1] = 1'b1;
            ledIn[2] = 1'b1;
          end
        N_LEFT: begin
            ledIn[0] = 1'b1;
            ledIn[1] = 1'b1;
            ledIn[2] = 1'b1;
            end
    default: begin
            ledIn[0] = 1'b0;
            ledIn[1] = 1'b0;
            ledIn[2] = 1'b0;
            end
    endcase
end


always@(posedge clk)
begin: state_FFs
    if(!resetn)
        current_state <= N_GREEN;
    else
        current_state <= next_state;
end
endmodule