data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/IR.v
 line:163: before: "("
data/verilator_xmls/5eabd752-d7be-4e1b-b899-6683d0ae468a.xml
module IR(IR_out,IR_in,load,clk,rst);

output reg	[7:0]IR_out;
input	[7:0]IR_in;
input	load,clk,rst;

always@(posedge clk)
	begin
		if(rst==1)IR_out<=8'b0;
		else if(load==1)IR_out<=IR_in;		
	end

endmodule
module IR(IR_out,IR_in,load,clk,rst);


output reg	[7:0]IR_out;
input	[7:0]IR_in;
input	load,clk,rst;

always@(posedge clk)
	begin
		if(rst==1)IR_out<=8'b0;
		else if(load==1)IR_out<=IR_in;		
	end

endmodule