data/full_repos/permissive/131921633/tv/Mips/Hazard/lwRead.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Hazard/lwRead.v:1: Cannot find include file: Mips/Type/Bool.v\n`include "Mips/Type/Bool.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Hazard,data/full_repos/permissive/131921633/Mips/Type/Bool.v\n             data/full_repos/permissive/131921633/tv/Mips/Hazard,data/full_repos/permissive/131921633/Mips/Type/Bool.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Hazard,data/full_repos/permissive/131921633/Mips/Type/Bool.v.sv\n             Mips/Type/Bool.v\n             Mips/Type/Bool.v.v\n             Mips/Type/Bool.v.sv\n             obj_dir/Mips/Type/Bool.v\n             obj_dir/Mips/Type/Bool.v.v\n             obj_dir/Mips/Type/Bool.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Hazard/lwRead.v:2: Cannot find include file: Mips/Type/RegAddr.v\n`include "Mips/Type/RegAddr.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Hazard/lwRead.v:3: Cannot find include file: Mips/Control/Signal/Register/Signal/WriteDataSource.v\n`include "Mips/Control/Signal/Register/Signal/WriteDataSource.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Hazard/lwRead.v:6: Define or directive not defined: \'`Mips_Type_Bool_T\'\n ( `Mips_Type_Bool_T (output) stallLwRead\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Hazard/lwRead.v:6: syntax error, unexpected \'(\', expecting \'[\'\n ( `Mips_Type_Bool_T (output) stallLwRead\n                      ^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Hazard/lwRead.v:7: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n , `Mips_Type_RegAddr_T (input) regRead1Addr\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Hazard/lwRead.v:8: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n , `Mips_Type_RegAddr_T (input) regRead2Addr\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Hazard/lwRead.v:9: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n , `Mips_Type_RegAddr_T (input) exWriteAddr\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Hazard/lwRead.v:10: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteDataSource_T\'\n , `Mips_Control_Signal_Register_Signal_WriteDataSource_T (input) exWriteData\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Hazard/lwRead.v:14: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteDataSource_Memory\'\n exWriteData == `Mips_Control_Signal_Register_Signal_WriteDataSource_Memory &&\n                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n'
module Mips_Hazard_lwRead
	( `Mips_Type_Bool_T (output) stallLwRead
	, `Mips_Type_RegAddr_T (input) regRead1Addr
	, `Mips_Type_RegAddr_T (input) regRead2Addr
	, `Mips_Type_RegAddr_T (input) exWriteAddr
	, `Mips_Control_Signal_Register_Signal_WriteDataSource_T (input) exWriteData
	);

assign stallLwRead =
	exWriteData == `Mips_Control_Signal_Register_Signal_WriteDataSource_Memory &&
	(|exWriteAddr) &&
	(
		exWriteAddr == regRead1Addr ||
		exWriteAddr == regRead2Addr
	);

endmodule
module Mips_Hazard_lwRead
	( `Mips_Type_Bool_T (output) stallLwRead
	, `Mips_Type_RegAddr_T (input) regRead1Addr
	, `Mips_Type_RegAddr_T (input) regRead2Addr
	, `Mips_Type_RegAddr_T (input) exWriteAddr
	, `Mips_Control_Signal_Register_Signal_WriteDataSource_T (input) exWriteData
	);


assign stallLwRead =
	exWriteData == `Mips_Control_Signal_Register_Signal_WriteDataSource_Memory &&
	(|exWriteAddr) &&
	(
		exWriteAddr == regRead1Addr ||
		exWriteAddr == regRead2Addr
	);

endmodule