data/full_repos/permissive/14593708/tests/program-counter-testbench.v
 line:28: before: "$"
1: b'%Error: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:12: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("program-counter-test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:13: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, program_counter_testbench);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:16: Unsupported or unknown PLI call: $monitor\n        $monitor("\\t%b,\\t%b,\\t\\t%x", clock, enable_overwrite, pc_value);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #0 clock = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #0 overwrite_value = \'h42;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #0 enable_overwrite = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #4 enable_overwrite = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #1 overwrite_value = \'h42424242;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #1 enable_overwrite = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #1 enable_overwrite = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #5 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/program-counter-testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clock = ~clock;\n           ^\n%Error: Exiting due to 3 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module program_counter_testbench;

    reg        clock;
    reg        enable_overwrite;
    reg[31:0]  overwrite_value;
    wire[31:0] pc_value;

    program_counter pc0(clock, enable_overwrite, overwrite_value, pc_value);

    initial
    begin
        $dumpfile("program-counter-test.vcd");
        $dumpvars(0, program_counter_testbench);

        $display("\tclock,\toverwrite\tpc value");
        $monitor("\t%b,\t%b,\t\t%x", clock, enable_overwrite, pc_value);

        #0 clock = 0;
        #0 overwrite_value = 'h42;
        #0 enable_overwrite = 1;

        #4 enable_overwrite = 0;
        #1 overwrite_value = 'h42424242;
        #1 enable_overwrite = 1;
        $display("\n\tjmp 0x42424242\n");
        #1 enable_overwrite = 0;

        #5 $finish;
    end

    always #1 clock = ~clock;

endmodule
module program_counter_testbench;


    reg        clock;
    reg        enable_overwrite;
    reg[31:0]  overwrite_value;
    wire[31:0] pc_value;

    program_counter pc0(clock, enable_overwrite, overwrite_value, pc_value);

    initial
    begin
        $dumpfile("program-counter-test.vcd");
        $dumpvars(0, program_counter_testbench);

        $display("\tclock,\toverwrite\tpc value");
        $monitor("\t%b,\t%b,\t\t%x", clock, enable_overwrite, pc_value);

        #0 clock = 0;
        #0 overwrite_value = 'h42;
        #0 enable_overwrite = 1;

        #4 enable_overwrite = 0;
        #1 overwrite_value = 'h42424242;
        #1 enable_overwrite = 1;
        $display("\n\tjmp 0x42424242\n");
        #1 enable_overwrite = 0;

        #5 $finish;
    end

    always #1 clock = ~clock;

endmodule