data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/sys_bus_model.sv
 line:29: before: "int"
1: b"%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/sys_bus_model.sv:59: syntax error, unexpected '@'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/sys_bus_model.sv:65: syntax error, unexpected '@'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/sys_bus_model.sv:69: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/sys_bus_model.sv:71: syntax error, unexpected '@'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 4 error(s)\n"
module sys_bus_model #(
  int unsigned AXI_DW = 32      ,
  int unsigned AXI_AW = 32      ,
  int unsigned AXI_SW = AXI_DW/8
)(

  input  logic              clk  ,
  input  logic              rstn ,

  output logic [AXI_AW-1:0] sys_addr ,
  output logic [AXI_DW-1:0] sys_wdata,
  output logic [AXI_SW-1:0] sys_sel  ,
  output logic              sys_wen  ,
  output logic              sys_ren  ,
  input  logic [AXI_DW-1:0] sys_rdata,
  input  logic              sys_err  ,
  input  logic              sys_ack
);

initial begin
   sys_wen <= 1'b0 ;
   sys_ren <= 1'b0 ;
end


task transaction (
  input  logic          we,
  input  logic [32-1:0] addr,
  input  logic [32-1:0] wdata,
  output logic [32-1:0] rdata
);
  @(posedge clk)
  sys_sel    <= '1;
  sys_wen    <=  we   ;
  sys_ren    <= ~we   ;
  sys_addr   <= addr  ;
  sys_wdata  <= wdata ;
  @(posedge clk);
  sys_wen    <= 1'b0  ;
  sys_ren    <= 1'b0  ;
  while (~sys_ack & ~sys_err)
    @(posedge clk);
  rdata <= sys_rdata ;
  @(posedge clk);
endtask: transaction


task write (
  input  logic [32-1:0] addr,
  input  logic [32-1:0] wdata
);
  logic [32-1:0] rdata;
  transaction (.we (1'b1), .addr (addr), .wdata (wdata), .rdata (rdata));
endtask: write


task read (
  input  logic [32-1:0] addr,
  output logic [32-1:0] rdata
);
  transaction (.we (1'b0), .addr (addr), .wdata (32'hx), .rdata (rdata));
endtask: read

endmodule
module sys_bus_model #(
  int unsigned AXI_DW = 32      ,
  int unsigned AXI_AW = 32      ,
  int unsigned AXI_SW = AXI_DW/8
)(

  input  logic              clk  ,
  input  logic              rstn ,

  output logic [AXI_AW-1:0] sys_addr ,
  output logic [AXI_DW-1:0] sys_wdata,
  output logic [AXI_SW-1:0] sys_sel  ,
  output logic              sys_wen  ,
  output logic              sys_ren  ,
  input  logic [AXI_DW-1:0] sys_rdata,
  input  logic              sys_err  ,
  input  logic              sys_ack
);


initial begin
   sys_wen <= 1'b0 ;
   sys_ren <= 1'b0 ;
end


task transaction (
  input  logic          we,
  input  logic [32-1:0] addr,
  input  logic [32-1:0] wdata,
  output logic [32-1:0] rdata
);
  @(posedge clk)
  sys_sel    <= '1;
  sys_wen    <=  we   ;
  sys_ren    <= ~we   ;
  sys_addr   <= addr  ;
  sys_wdata  <= wdata ;
  @(posedge clk);
  sys_wen    <= 1'b0  ;
  sys_ren    <= 1'b0  ;
  while (~sys_ack & ~sys_err)
    @(posedge clk);
  rdata <= sys_rdata ;
  @(posedge clk);
endtask: transaction


task write (
  input  logic [32-1:0] addr,
  input  logic [32-1:0] wdata
);
  logic [32-1:0] rdata;
  transaction (.we (1'b1), .addr (addr), .wdata (wdata), .rdata (rdata));
endtask: write


task read (
  input  logic [32-1:0] addr,
  output logic [32-1:0] rdata
);
  transaction (.we (1'b0), .addr (addr), .wdata (32'hx), .rdata (rdata));
endtask: read

endmodule