data/full_repos/permissive/181013988/src/ctrl_unit.v
data/verilator_xmls/337e02ec-e1ae-4069-90b1-799812cbaadb.xml
module ctrl_unit(
    input [31:0] instr,
    output reg reg_dst,
    output reg alu_src,
    output reg mem_to_reg,
    output reg reg_wrt,
    output reg mem_rd,
    output reg mem_wrt,
    output reg brnch,
    output reg jmp,
    output reg [2:0] alu_op
);

    wire [5:0] opcode;
    assign opcode = instr [31:26];
    reg [10:0] ctrl_sgnls[63:0];

    initial begin
        ctrl_sgnls[6'b000000] = 11'b10010000100;
        ctrl_sgnls[6'b010000] = 11'b01010000110;
        ctrl_sgnls[6'b010001] = 11'b01010001000;
        ctrl_sgnls[6'b010010] = 11'b01010001010;
        ctrl_sgnls[6'b010011] = 11'b00000010010;

        ctrl_sgnls[6'b010101] = 11'b01111000000;
        ctrl_sgnls[6'b010110] = 11'b01001000000;
        ctrl_sgnls[6'b010111] = 11'b10010000100;
        ctrl_sgnls[6'b011000] = 11'b01010001100;
        ctrl_sgnls[6'b110000] = 11'b00000011111;
    end

    always @(instr) begin
        reg_dst     = ctrl_sgnls[opcode][10];
        alu_src     = ctrl_sgnls[opcode][9];
        mem_to_reg  = ctrl_sgnls[opcode][8];
        reg_wrt     = ctrl_sgnls[opcode][7];
        mem_wrt     = ctrl_sgnls[opcode][6];
        mem_rd      = ctrl_sgnls[opcode][5];
        brnch       = ctrl_sgnls[opcode][4];
        alu_op      = ctrl_sgnls[opcode][3:1];
        jmp         = ctrl_sgnls[opcode][0];
    end

endmodule
module ctrl_unit(
    input [31:0] instr,
    output reg reg_dst,
    output reg alu_src,
    output reg mem_to_reg,
    output reg reg_wrt,
    output reg mem_rd,
    output reg mem_wrt,
    output reg brnch,
    output reg jmp,
    output reg [2:0] alu_op
);


    wire [5:0] opcode;
    assign opcode = instr [31:26];
    reg [10:0] ctrl_sgnls[63:0];

    initial begin
        ctrl_sgnls[6'b000000] = 11'b10010000100;
        ctrl_sgnls[6'b010000] = 11'b01010000110;
        ctrl_sgnls[6'b010001] = 11'b01010001000;
        ctrl_sgnls[6'b010010] = 11'b01010001010;
        ctrl_sgnls[6'b010011] = 11'b00000010010;

        ctrl_sgnls[6'b010101] = 11'b01111000000;
        ctrl_sgnls[6'b010110] = 11'b01001000000;
        ctrl_sgnls[6'b010111] = 11'b10010000100;
        ctrl_sgnls[6'b011000] = 11'b01010001100;
        ctrl_sgnls[6'b110000] = 11'b00000011111;
    end

    always @(instr) begin
        reg_dst     = ctrl_sgnls[opcode][10];
        alu_src     = ctrl_sgnls[opcode][9];
        mem_to_reg  = ctrl_sgnls[opcode][8];
        reg_wrt     = ctrl_sgnls[opcode][7];
        mem_wrt     = ctrl_sgnls[opcode][6];
        mem_rd      = ctrl_sgnls[opcode][5];
        brnch       = ctrl_sgnls[opcode][4];
        alu_op      = ctrl_sgnls[opcode][3:1];
        jmp         = ctrl_sgnls[opcode][0];
    end

endmodule