data/full_repos/permissive/124591763/ram/ram.v
data/verilator_xmls/80134039-0292-4a59-a630-8d4a54737e22.xml
module ram #(
    parameter ADDR_WIDTH = 8,
    parameter DATA_WIDTH = 8
) (
    input  wire                    clk,

    input  wire                    wr_en,
    input  wire [DATA_WIDTH - 1:0] d_in,
    input  wire [ADDR_WIDTH - 1:0] addr,

    output wire [DATA_WIDTH - 1:0] d_out
);

    reg [DATA_WIDTH - 1:0] mem [0:`RAM_DEPTH - 1];


    assign d_out = mem[addr];

    integer i;


    initial begin
        for (i = 0; i < `RAM_DEPTH; i = i + 1) begin
            mem[i] = {DATA_WIDTH{1'b0}};
        end
    end


    always @ (posedge clk) begin
        if (wr_en) mem[addr] <= d_in;
    end

endmodule
module ram #(
    parameter ADDR_WIDTH = 8,
    parameter DATA_WIDTH = 8
) (
    input  wire                    clk,

    input  wire                    wr_en,
    input  wire [DATA_WIDTH - 1:0] d_in,
    input  wire [ADDR_WIDTH - 1:0] addr,

    output wire [DATA_WIDTH - 1:0] d_out
);


    reg [DATA_WIDTH - 1:0] mem [0:`RAM_DEPTH - 1];


    assign d_out = mem[addr];

    integer i;


    initial begin
        for (i = 0; i < `RAM_DEPTH; i = i + 1) begin
            mem[i] = {DATA_WIDTH{1'b0}};
        end
    end


    always @ (posedge clk) begin
        if (wr_en) mem[addr] <= d_in;
    end

endmodule