data/full_repos/permissive/158845296/instr_mem_ctrl.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/158845296/instr_mem_ctrl.v:38: syntax error, unexpected byte\n        .byte         (2'b0),          \n         ^~~~\n%Error: Exiting due to 1 error(s)\n"
module instr_mem_ctrl
(
    input clock,
    input reset,
    input [31:0] address,
    output [31:0] data,
    output stall
);


    wire  [1:0] cache_line;
    wire  [1:0] cache_word;
    wire [25:0] cache_tag_in;


    wire         cache_hit;
    wire         cache_dirty;
    wire  [31:0] cache_data;
    wire         cache_valid;
    wire [127:0] cache_block;
    wire  [26:0] cache_tag_out;


    wire         mem_enable;
    wire [127:0] mem_data;
    wire         mem_valid;


    cache i_cache
    (
        .clock        (clock),
        .reset        (reset),
        .write_word   (1'b0),
        .write_block  (mem_valid),
        .byte_access  (1'b0),
        .index        (cache_line),
        .word         (cache_word),
        .byte         (2'b0),
        .tag_in       (cache_tag_in),
        .word_in      (31'b0),
        .block_in     (mem_data),
        .hit          (cache_hit),
        .dirty        (cache_dirty),
        .word_out     (cache_data),
        .word_valid   (cache_valid),
        .block_out    (cache_block),
        .tag_out      (cache_tag_out)
    );

    instruction_mem i_mem
    (
        .clock    (clock),
        .enable   (mem_enable),
        .address  (address),
        .data     (mem_data),
        .valid    (mem_valid)
    );


    assign cache_tag_in = address[31:6];
    assign cache_line   = address[5:4];
    assign cache_word   = address[3:2];


    assign mem_enable = ~cache_hit || ~cache_valid;


    assign data  = cache_data;
    assign stall = mem_enable;

endmodule
module instr_mem_ctrl
(
    input clock,
    input reset,
    input [31:0] address,
    output [31:0] data,
    output stall
);



    wire  [1:0] cache_line;
    wire  [1:0] cache_word;
    wire [25:0] cache_tag_in;


    wire         cache_hit;
    wire         cache_dirty;
    wire  [31:0] cache_data;
    wire         cache_valid;
    wire [127:0] cache_block;
    wire  [26:0] cache_tag_out;


    wire         mem_enable;
    wire [127:0] mem_data;
    wire         mem_valid;


    cache i_cache
    (
        .clock        (clock),
        .reset        (reset),
        .write_word   (1'b0),
        .write_block  (mem_valid),
        .byte_access  (1'b0),
        .index        (cache_line),
        .word         (cache_word),
        .byte         (2'b0),
        .tag_in       (cache_tag_in),
        .word_in      (31'b0),
        .block_in     (mem_data),
        .hit          (cache_hit),
        .dirty        (cache_dirty),
        .word_out     (cache_data),
        .word_valid   (cache_valid),
        .block_out    (cache_block),
        .tag_out      (cache_tag_out)
    );

    instruction_mem i_mem
    (
        .clock    (clock),
        .enable   (mem_enable),
        .address  (address),
        .data     (mem_data),
        .valid    (mem_valid)
    );


    assign cache_tag_in = address[31:6];
    assign cache_line   = address[5:4];
    assign cache_word   = address[3:2];


    assign mem_enable = ~cache_hit || ~cache_valid;


    assign data  = cache_data;
    assign stall = mem_enable;

endmodule