data/full_repos/permissive/211235278/04. Data Forwarding CPU/HazardDetector.v
1: b'%Error: Cannot find file containing module: Data\n        ... Looked in:\n             data/full_repos/permissive/211235278/04./Data\n             data/full_repos/permissive/211235278/04./Data.v\n             data/full_repos/permissive/211235278/04./Data.sv\n             Data\n             Data.v\n             Data.sv\n             obj_dir/Data\n             obj_dir/Data.v\n             obj_dir/Data.sv\n%Error: Cannot find file containing module: Forwarding\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/211235278\n%Error: Cannot find file containing module: data/full_repos/permissive/211235278/04.\n%Error: Cannot find file containing module: CPU/HazardDetector.v\n%Error: Exiting due to 5 error(s)\n'
module HazardDetector(
    input [15:0] inst,
    input [1:0] ID_EX_RFWriteAddress, EX_MEM_RFWriteAddress, MEM_WB_RFWriteAddress,
    input ID_EX_RegWrite, EX_MEM_RegWrite, MEM_WB_RegWrite,
    input ID_EX_IsLWD,
    output reg Stall,
    output reg [1:0] Forward_Rs, Forward_Rt
    );

    
    always @(*) begin
    

        if ((inst[15:12]==`OPCODE_R && (inst[5:0]==`FUNC_ADD || inst[5:0]==`FUNC_SUB || inst[5:0]==`FUNC_AND || inst[5:0]==`FUNC_ORR)) || inst[15:12]==`OPCODE_SWD || inst[15:12]==`OPCODE_BNE || inst[15:12]==`OPCODE_BEQ) begin 
            

            if ((ID_EX_RFWriteAddress ==inst[11:10]) && ID_EX_RegWrite) begin
                if (ID_EX_IsLWD) begin
                    Stall = 1;
                    Forward_Rs = 0;
                end else begin
                    Stall = 0;
                    Forward_Rs = 1;
                end
            end else if ((EX_MEM_RFWriteAddress==inst[11:10]) && EX_MEM_RegWrite) begin
                Stall = 0;
                Forward_Rs = 2;
            end else if ((MEM_WB_RFWriteAddress==inst[11:10]) && MEM_WB_RegWrite) begin
                Stall = 0;
                Forward_Rs = 3;
            end else begin
                Stall = 0;
                Forward_Rs = 0;
            end
            

            if ((ID_EX_RFWriteAddress ==inst[9:8]) && ID_EX_RegWrite) begin
                if (ID_EX_IsLWD) begin
                    Stall = 1;
                    Forward_Rt = 0;
                end else begin
                    Stall = 0;
                    Forward_Rt = 1;
                end
            end else if ((EX_MEM_RFWriteAddress==inst[9:8]) && EX_MEM_RegWrite) begin
                Stall = 0;
                Forward_Rt = 2;
            end else if ((MEM_WB_RFWriteAddress==inst[9:8]) && MEM_WB_RegWrite) begin
                Stall = 0;
                Forward_Rt = 3;
            end else begin
                Stall = 0;
                Forward_Rt = 0;
            end
            
        end
        

        else if ((inst[15:12]==`OPCODE_R && (inst[5:0]==`FUNC_NOT || inst[5:0]==`FUNC_TCP || inst[5:0]==`FUNC_SHL || inst[5:0]==`FUNC_SHR || inst[5:0]==`FUNC_WWD || inst[5:0]==`FUNC_JPR || inst[5:0]==`FUNC_JRL))
          || inst[15:12]==`OPCODE_ADI || inst[15:12]==`OPCODE_ORI || inst[15:12]==`OPCODE_LWD || inst[15:12]==`OPCODE_BGZ || inst[15:12]==`OPCODE_BLZ) begin
          

            if ((ID_EX_RFWriteAddress ==inst[11:10]) && ID_EX_RegWrite) begin
                if (ID_EX_IsLWD) begin
                    Stall = 1;
                    Forward_Rs = 0;
                end else begin
                    Stall = 0;
                    Forward_Rs = 1;
                end
            end else if ((EX_MEM_RFWriteAddress==inst[11:10]) && EX_MEM_RegWrite) begin
                Stall = 0;
                Forward_Rs = 2;
            end else if ((MEM_WB_RFWriteAddress==inst[11:10]) && MEM_WB_RegWrite) begin
                Stall = 0;
                Forward_Rs = 3;
            end else begin
                Stall = 0;
                Forward_Rs = 0;
            end
            
        end
        

        else begin
            Stall = 0;
            Forward_Rs = 0;
            Forward_Rt = 0;
        end
        
     end
    
endmodule
module HazardDetector(
    input [15:0] inst,
    input [1:0] ID_EX_RFWriteAddress, EX_MEM_RFWriteAddress, MEM_WB_RFWriteAddress,
    input ID_EX_RegWrite, EX_MEM_RegWrite, MEM_WB_RegWrite,
    input ID_EX_IsLWD,
    output reg Stall,
    output reg [1:0] Forward_Rs, Forward_Rt
    );


    
    always @(*) begin
    

        if ((inst[15:12]==`OPCODE_R && (inst[5:0]==`FUNC_ADD || inst[5:0]==`FUNC_SUB || inst[5:0]==`FUNC_AND || inst[5:0]==`FUNC_ORR)) || inst[15:12]==`OPCODE_SWD || inst[15:12]==`OPCODE_BNE || inst[15:12]==`OPCODE_BEQ) begin 
            

            if ((ID_EX_RFWriteAddress ==inst[11:10]) && ID_EX_RegWrite) begin
                if (ID_EX_IsLWD) begin
                    Stall = 1;
                    Forward_Rs = 0;
                end else begin
                    Stall = 0;
                    Forward_Rs = 1;
                end
            end else if ((EX_MEM_RFWriteAddress==inst[11:10]) && EX_MEM_RegWrite) begin
                Stall = 0;
                Forward_Rs = 2;
            end else if ((MEM_WB_RFWriteAddress==inst[11:10]) && MEM_WB_RegWrite) begin
                Stall = 0;
                Forward_Rs = 3;
            end else begin
                Stall = 0;
                Forward_Rs = 0;
            end
            

            if ((ID_EX_RFWriteAddress ==inst[9:8]) && ID_EX_RegWrite) begin
                if (ID_EX_IsLWD) begin
                    Stall = 1;
                    Forward_Rt = 0;
                end else begin
                    Stall = 0;
                    Forward_Rt = 1;
                end
            end else if ((EX_MEM_RFWriteAddress==inst[9:8]) && EX_MEM_RegWrite) begin
                Stall = 0;
                Forward_Rt = 2;
            end else if ((MEM_WB_RFWriteAddress==inst[9:8]) && MEM_WB_RegWrite) begin
                Stall = 0;
                Forward_Rt = 3;
            end else begin
                Stall = 0;
                Forward_Rt = 0;
            end
            
        end
        

        else if ((inst[15:12]==`OPCODE_R && (inst[5:0]==`FUNC_NOT || inst[5:0]==`FUNC_TCP || inst[5:0]==`FUNC_SHL || inst[5:0]==`FUNC_SHR || inst[5:0]==`FUNC_WWD || inst[5:0]==`FUNC_JPR || inst[5:0]==`FUNC_JRL))
          || inst[15:12]==`OPCODE_ADI || inst[15:12]==`OPCODE_ORI || inst[15:12]==`OPCODE_LWD || inst[15:12]==`OPCODE_BGZ || inst[15:12]==`OPCODE_BLZ) begin
          

            if ((ID_EX_RFWriteAddress ==inst[11:10]) && ID_EX_RegWrite) begin
                if (ID_EX_IsLWD) begin
                    Stall = 1;
                    Forward_Rs = 0;
                end else begin
                    Stall = 0;
                    Forward_Rs = 1;
                end
            end else if ((EX_MEM_RFWriteAddress==inst[11:10]) && EX_MEM_RegWrite) begin
                Stall = 0;
                Forward_Rs = 2;
            end else if ((MEM_WB_RFWriteAddress==inst[11:10]) && MEM_WB_RegWrite) begin
                Stall = 0;
                Forward_Rs = 3;
            end else begin
                Stall = 0;
                Forward_Rs = 0;
            end
            
        end
        

        else begin
            Stall = 0;
            Forward_Rs = 0;
            Forward_Rt = 0;
        end
        
     end
    
endmodule