data/full_repos/permissive/139213403/FPGA/tick_counter_testbench.v
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/tick_counter_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/tick_counter_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/tick_counter_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/tick_counter_testbench.v:37: syntax error, unexpected \'@\'\n     @(negedge clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/tick_counter_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n     #(T);\n     ^\n%Error: data/full_repos/permissive/139213403/FPGA/tick_counter_testbench.v:51: syntax error, unexpected \'@\'\n   @(negedge reset);\n   ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tick_counter_testbench;
	localparam T = 20;
	localparam N = 4;
	
	integer i;
	reg clk, reset;
	reg tick;
	wire [N-1:0] counter;
	wire of;
	
	tick_counter #(.N(N)) uut(.clk(clk), .reset(reset), .tick(tick), .counter(counter), .of(of));
	

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end


	initial
		begin
			tick = 0;
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
		
	task do_tick;
		input reg [N-1:0] count;
		begin
			$display("do_tick: %d counts", count);
			for (i = 0; i < count - 1; i = i + 1)
				begin
					@(negedge clk);
					tick = 1;
					#(T);
					tick = 0;
				end
		end
	endtask
	
	always @*
		$display("do_tick: counter: %d of: %b", counter, of);
		

	initial
		begin
			@(negedge reset);
			@(negedge clk);
			
			do_tick(1);
			do_tick(2);
			do_tick(3);
			do_tick(6);
			
			$display("force overflow");
			do_tick(15);
			
			$stop;
		end
	
endmodule
module tick_counter_testbench;

	localparam T = 20;
	localparam N = 4;
	
	integer i;
	reg clk, reset;
	reg tick;
	wire [N-1:0] counter;
	wire of;
	
	tick_counter #(.N(N)) uut(.clk(clk), .reset(reset), .tick(tick), .counter(counter), .of(of));
	

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end


	initial
		begin
			tick = 0;
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
		
	task do_tick;
		input reg [N-1:0] count;
		begin
			$display("do_tick: %d counts", count);
			for (i = 0; i < count - 1; i = i + 1)
				begin
					@(negedge clk);
					tick = 1;
					#(T);
					tick = 0;
				end
		end
	endtask
	
	always @*
		$display("do_tick: counter: %d of: %b", counter, of);
		

	initial
		begin
			@(negedge reset);
			@(negedge clk);
			
			do_tick(1);
			do_tick(2);
			do_tick(3);
			do_tick(6);
			
			$display("force overflow");
			do_tick(15);
			
			$stop;
		end
	
endmodule