data/full_repos/permissive/143278/ivltests/pr699.v
 line:17: before: "b"
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr699.v:17: Unsupported: Verilog 1995 force\n    force b = 1\'b1;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr699.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (b !== 1\'b1) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr699.v:28: Unsupported: Verilog 1995 release\n    release b;\n    ^~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug;

wire a, b, c, d;

assign c = 1'b0;
assign a = 1'b0;
assign b = 1'b0;

assign d = c ? a : b;

initial
  begin
    force b = 1'b1;
    #1 if (b !== 1'b1) begin
       $display("FAILED -- b = %b", b);
       $finish;
    end

    if (d !== 1'b1) begin
       $display("FAILED -- d = %b", d);
       $finish;
    end

    release b;
    $display("PASSED");
    $finish;
  end

endmodule
module bug;


wire a, b, c, d;

assign c = 1'b0;
assign a = 1'b0;
assign b = 1'b0;

assign d = c ? a : b;

initial
  begin
    force b = 1'b1;
    #1 if (b !== 1'b1) begin
       $display("FAILED -- b = %b", b);
       $finish;
    end

    if (d !== 1'b1) begin
       $display("FAILED -- d = %b", d);
       $finish;
    end

    release b;
    $display("PASSED");
    $finish;
  end

endmodule