data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/IDSegReg.v
'utf-8' codec can't decode bytes in position 52-53: invalid continuation byte
1: b"%Error: data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/IDSegReg.v:46: Cannot find file containing module: 'InstructionRamNoCache'\n    InstructionRamNoCache InstructionRam (\n    ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog,data/full_repos/permissive/175780824/InstructionRamNoCache\n             data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog,data/full_repos/permissive/175780824/InstructionRamNoCache.v\n             data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog,data/full_repos/permissive/175780824/InstructionRamNoCache.sv\n             InstructionRamNoCache\n             InstructionRamNoCache.v\n             InstructionRamNoCache.sv\n             obj_dir/InstructionRamNoCache\n             obj_dir/InstructionRamNoCache.v\n             obj_dir/InstructionRamNoCache.sv\n%Error: Exiting due to 1 error(s)\n"
module IDSegReg(
    input wire clk,
    input wire rst,
    input wire clear,
    input wire en,

    input wire [31:0] A,
    output wire [31:0] RD,

    input wire [31:0] PCF,
    output reg [31:0] PCD 
    );
    



    reg stall_or_clear = 1'b0;
    reg  [31:0] stall_or_clear_data = 0;
    wire [31:0] RD_raw;
    assign RD = stall_or_clear ? stall_or_clear_data : RD_raw;
    always @ (posedge clk or posedge rst) begin
        if(rst) begin
            stall_or_clear <= 1'b0;
            stall_or_clear_data <= 0;
        end else begin
            if(~en) begin
                stall_or_clear <= 1'b1;
                stall_or_clear_data <= RD;
            end else if(clear) begin
                stall_or_clear <= 1'b1;
                stall_or_clear_data <= 0;
            end else begin
                stall_or_clear <= 1'b0;
                stall_or_clear_data <= 0;
            end
        end
    end

    always@(posedge clk or posedge rst)
        if(rst)
            PCD <= 0;
        else if(en)
            PCD <= clear ? 0: PCF;
    
    InstructionRamNoCache InstructionRam (
         .clk    ( clk        ),
         .rst    ( rst        ),
         .addra  ( A          ),
         .douta  ( RD_raw     )
     );

    
endmodule
module IDSegReg(
    input wire clk,
    input wire rst,
    input wire clear,
    input wire en,

    input wire [31:0] A,
    output wire [31:0] RD,

    input wire [31:0] PCF,
    output reg [31:0] PCD 
    );

    



    reg stall_or_clear = 1'b0;
    reg  [31:0] stall_or_clear_data = 0;
    wire [31:0] RD_raw;
    assign RD = stall_or_clear ? stall_or_clear_data : RD_raw;
    always @ (posedge clk or posedge rst) begin
        if(rst) begin
            stall_or_clear <= 1'b0;
            stall_or_clear_data <= 0;
        end else begin
            if(~en) begin
                stall_or_clear <= 1'b1;
                stall_or_clear_data <= RD;
            end else if(clear) begin
                stall_or_clear <= 1'b1;
                stall_or_clear_data <= 0;
            end else begin
                stall_or_clear <= 1'b0;
                stall_or_clear_data <= 0;
            end
        end
    end

    always@(posedge clk or posedge rst)
        if(rst)
            PCD <= 0;
        else if(en)
            PCD <= clear ? 0: PCF;
    
    InstructionRamNoCache InstructionRam (
         .clk    ( clk        ),
         .rst    ( rst        ),
         .addra  ( A          ),
         .douta  ( RD_raw     )
     );

    
endmodule