data/full_repos/permissive/143278/ivltests/const3.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/const3.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #1 testr = {-5\'d1, -3\'sd1};\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [7:0] testr;
   wire [7:0] testw = {-5'd1, -3'sd1};

   initial begin
      #1 testr = {-5'd1, -3'sd1};
      if (testr !== 8'b11111_111) begin
	 $display("FAILED -- testr=%b", testr);
	 $finish;
      end

      if (testw !== 8'b11111_111) begin
	 $display("FAILED -- testw=%b", testw);
	 $finish;
      end

      $display("testr=%b", testr);
      $display("testw=%b", testw);
      $display("PASSED");
   end

endmodule
module main;


   reg [7:0] testr;
   wire [7:0] testw = {-5'd1, -3'sd1};

   initial begin
      #1 testr = {-5'd1, -3'sd1};
      if (testr !== 8'b11111_111) begin
	 $display("FAILED -- testr=%b", testr);
	 $finish;
      end

      if (testw !== 8'b11111_111) begin
	 $display("FAILED -- testw=%b", testw);
	 $finish;
      end

      $display("testr=%b", testr);
      $display("testw=%b", testw);
      $display("PASSED");
   end

endmodule