data/full_repos/permissive/137213315/backup_aes_cipher.v
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1: b'%Error: data/full_repos/permissive/137213315/backup_aes_cipher.v:4: Cannot find include file: AddRoundKey.v\n`include "AddRoundKey.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137213315,data/full_repos/permissive/137213315/AddRoundKey.v\n             data/full_repos/permissive/137213315,data/full_repos/permissive/137213315/AddRoundKey.v.v\n             data/full_repos/permissive/137213315,data/full_repos/permissive/137213315/AddRoundKey.v.sv\n             AddRoundKey.v\n             AddRoundKey.v.v\n             AddRoundKey.v.sv\n             obj_dir/AddRoundKey.v\n             obj_dir/AddRoundKey.v.v\n             obj_dir/AddRoundKey.v.sv\n%Error: data/full_repos/permissive/137213315/backup_aes_cipher.v:5: Cannot find include file: SubBytes.v\n`include "SubBytes.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137213315/backup_aes_cipher.v:6: Cannot find include file: ShiftRows.v\n`include "ShiftRows.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137213315/backup_aes_cipher.v:7: Cannot find include file: MixColumns.v\n`include "MixColumns.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137213315/backup_aes_cipher.v:8: Cannot find include file: KeyExpansion.v\n`include "KeyExpansion.v" \n         ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module aes_cipher(input clk, rstn,
                  input [127:0] plain_text, key,
                  output [127:0] cipher_text);
  wire [127:0] firstAddRoundKeyOUT;
  AddRoundKey addroundkeyStart(.in(plain_text),.key(key),.out(firstAddRoundKeyOUT));
  
  reg start;
  wire [127:0] sboxIN;
  assign sboxIN = start ? firstAddRoundKeyOUT : state;
  
  wire [127:0] sboxOUT;
  SubBytes sbox (.in(sboxIN),.out(sboxOUT));

  wire[127:0] shiftrowsOUT;
  ShiftRows shiftrows(.in(sboxOUT), .out(shiftrowsOUT));
  wire[127:0] mixcolumnsOUT;
  MixColumns mixcolumns(.in(shiftrowsOUT),.out(mixcolumnsOUT));
  wire[127:0] KeyExpansionOUT, addroundkeymiddleOUT;
  
  
  
  reg [127:0] state;
  reg [3:0] round;
  reg [127:0] roundkey;
  
  always@(posedge clk or negedge rstn) begin
    if(!rstn) begin
      round <= 0;
    end
    else begin
      if(round == 4'd11) begin
        state <= state;
      end
      else begin
      round <= round + 1;
      state <= addroundkeymiddleOUT;
      roundkey <= KeyExpansionOUT;
      end
    end
  end
  
  wire [127:0] keyexpansionIN;
  assign keyexpansionIN = start ? key : roundkey;
  
  KeyExpansion keyexpansion(.RoundKey(keyexpansionIN),.RoundNumber(round),.NextRoundKey(KeyExpansionOUT));

  AddRoundKey addroundkeyMiddle(.in(mixcolumnsOUT),.key(KeyExpansionOUT), .out(addroundkeymiddleOUT));

  always@(*) begin
    if(round == 0) begin
      start = 1'b1;
    end
    else begin
      start = 1'b0;
    end
  end
  
  wire [127:0] sboxOUT2;
  SubBytes sbox2(.in(state),.out(sboxOUT2));
  wire[127:0] shiftrowsOUT2;
  ShiftRows shiftrows2(.in(sboxOUT2),.out(shiftrowsOUT2));
  
  AddRoundKey addroundkeyfinal(.in(shiftrowsOUT2),.key(KeyExpansionOUT),.out(cipher_text));
  
  

endmodule
module aes_cipher(input clk, rstn,
                  input [127:0] plain_text, key,
                  output [127:0] cipher_text);

  wire [127:0] firstAddRoundKeyOUT;
  AddRoundKey addroundkeyStart(.in(plain_text),.key(key),.out(firstAddRoundKeyOUT));
  
  reg start;
  wire [127:0] sboxIN;
  assign sboxIN = start ? firstAddRoundKeyOUT : state;
  
  wire [127:0] sboxOUT;
  SubBytes sbox (.in(sboxIN),.out(sboxOUT));

  wire[127:0] shiftrowsOUT;
  ShiftRows shiftrows(.in(sboxOUT), .out(shiftrowsOUT));
  wire[127:0] mixcolumnsOUT;
  MixColumns mixcolumns(.in(shiftrowsOUT),.out(mixcolumnsOUT));
  wire[127:0] KeyExpansionOUT, addroundkeymiddleOUT;
  
  
  
  reg [127:0] state;
  reg [3:0] round;
  reg [127:0] roundkey;
  
  always@(posedge clk or negedge rstn) begin
    if(!rstn) begin
      round <= 0;
    end
    else begin
      if(round == 4'd11) begin
        state <= state;
      end
      else begin
      round <= round + 1;
      state <= addroundkeymiddleOUT;
      roundkey <= KeyExpansionOUT;
      end
    end
  end
  
  wire [127:0] keyexpansionIN;
  assign keyexpansionIN = start ? key : roundkey;
  
  KeyExpansion keyexpansion(.RoundKey(keyexpansionIN),.RoundNumber(round),.NextRoundKey(KeyExpansionOUT));

  AddRoundKey addroundkeyMiddle(.in(mixcolumnsOUT),.key(KeyExpansionOUT), .out(addroundkeymiddleOUT));

  always@(*) begin
    if(round == 0) begin
      start = 1'b1;
    end
    else begin
      start = 1'b0;
    end
  end
  
  wire [127:0] sboxOUT2;
  SubBytes sbox2(.in(state),.out(sboxOUT2));
  wire[127:0] shiftrowsOUT2;
  ShiftRows shiftrows2(.in(sboxOUT2),.out(shiftrowsOUT2));
  
  AddRoundKey addroundkeyfinal(.in(shiftrowsOUT2),.key(KeyExpansionOUT),.out(cipher_text));
  
  

endmodule