data/full_repos/permissive/197806087/booth-multiplier/tb.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/197806087/booth-multiplier/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n            #5; clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/197806087/booth-multiplier/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n            #5; clk = ~clk;\n            ^\n%Error: data/full_repos/permissive/197806087/booth-multiplier/tb.v:25: syntax error, unexpected \'@\'\n            @(posedge ready) begin\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/booth-multiplier/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n                #15; mul1 <= j;\n                ^\n%Error: data/full_repos/permissive/197806087/booth-multiplier/tb.v:29: syntax error, unexpected \'@\'\n                    @(posedge ready) begin\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/booth-multiplier/tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n                        #15; mul2 <= k;\n                        ^\n%Error: data/full_repos/permissive/197806087/booth-multiplier/tb.v:35: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/197806087/booth-multiplier/tb.v:38: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("data/dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/197806087/booth-multiplier/tb.v:39: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb);\n        ^~~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
    localparam OPERAND_BITS = 8;
    reg clk;
    reg signed [OPERAND_BITS - 1:0] mul1;
    reg signed [OPERAND_BITS - 1:0] mul2;
    wire signed [2 * OPERAND_BITS - 1:0] res_not;
    wire signed [2 * OPERAND_BITS - 1:0] res_true;
    wire ready;
    booth #(.OPERAND_BITS(OPERAND_BITS)) b1(.clk(clk), .mul1(mul1), .mul2(mul2), .res_out(res_not), .ready(ready), .comp(res_true));
    integer i;
    initial begin
        clk = 0;
        for(i = 0; i <= 657918; i = i+1) begin
            #5; clk = ~clk;
            #5; clk = ~clk;
        end
    end
    integer j;
    integer k;
    initial begin
        mul1 <= 1;
        mul2 <= 1;
        for(j = 0; j < (2 ** OPERAND_BITS); j = j+1) begin
            @(posedge ready) begin
                $display("mul1=%d, mul2=%d, res=%d", mul1, mul2, res_true);
                #15; mul1 <= j;
                for(k = 0; k < (2 ** OPERAND_BITS); k = k+1) begin
                    @(posedge ready) begin
                        $display("mul1=%d, mul2=%d, res=%d", mul1, mul2, res_true);
                        #15; mul2 <= k;
                    end
                end
            end
        end
    end
    initial begin
        $dumpfile("data/dumpfile.vcd");
        $dumpvars(0, tb);
    end
endmodule
module tb;

    localparam OPERAND_BITS = 8;
    reg clk;
    reg signed [OPERAND_BITS - 1:0] mul1;
    reg signed [OPERAND_BITS - 1:0] mul2;
    wire signed [2 * OPERAND_BITS - 1:0] res_not;
    wire signed [2 * OPERAND_BITS - 1:0] res_true;
    wire ready;
    booth #(.OPERAND_BITS(OPERAND_BITS)) b1(.clk(clk), .mul1(mul1), .mul2(mul2), .res_out(res_not), .ready(ready), .comp(res_true));
    integer i;
    initial begin
        clk = 0;
        for(i = 0; i <= 657918; i = i+1) begin
            #5; clk = ~clk;
            #5; clk = ~clk;
        end
    end
    integer j;
    integer k;
    initial begin
        mul1 <= 1;
        mul2 <= 1;
        for(j = 0; j < (2 ** OPERAND_BITS); j = j+1) begin
            @(posedge ready) begin
                $display("mul1=%d, mul2=%d, res=%d", mul1, mul2, res_true);
                #15; mul1 <= j;
                for(k = 0; k < (2 ** OPERAND_BITS); k = k+1) begin
                    @(posedge ready) begin
                        $display("mul1=%d, mul2=%d, res=%d", mul1, mul2, res_true);
                        #15; mul2 <= k;
                    end
                end
            end
        end
    end
    initial begin
        $dumpfile("data/dumpfile.vcd");
        $dumpvars(0, tb);
    end
endmodule