data/full_repos/permissive/190680822/testBench/fp32_tb.v
 line:96: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #2 clk = !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #80\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #80\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #80\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #80\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #80\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #80\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #80\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #80\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/190680822/testBench/fp32_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n   #500\n   ^\n%Error: data/full_repos/permissive/190680822/testBench/fp32_tb.v:101: Cannot find file containing module: \'adder\'\n  adder test_run(Xin, Yin, clk, reset, Zout, done);\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/190680822/testBench,data/full_repos/permissive/190680822/adder\n             data/full_repos/permissive/190680822/testBench,data/full_repos/permissive/190680822/adder.v\n             data/full_repos/permissive/190680822/testBench,data/full_repos/permissive/190680822/adder.sv\n             adder\n             adder.v\n             adder.sv\n             obj_dir/adder\n             obj_dir/adder.v\n             obj_dir/adder.sv\n%Error: data/full_repos/permissive/190680822/testBench/fp32_tb.v:102: Cannot find file containing module: \'multiplier\'\n  multiplier test_run2(Xin, Yin, clk, reset, Zout2, done2);\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FPU_TESTBENCH;


  reg [31:0] Xin, Yin;
  reg clk;

  reg reset;

  wire [31:0] Zout, Zout2;
  wire done, done2;
  
  initial begin
      clk = 'b0;
      forever
      begin
        #2 clk = !clk;
      end
  end
    
  initial begin









    Xin = 'b00111111010011001100110011001101;
    Yin = 'b10111111001100110011001100110011;
    reset = 1'b1;
    #2 reset = 1'b0;


    #80
    Yin = 'b00111111010011001100110011001101;
    Xin = 'b10111111001100110011001100110011;
    reset = 1'b1;
    #2 reset = 1'b0;


    #80
    Xin = 'b10111111010011001100110011001101;
    Yin = 'b00111111001100110011001100110011;
    reset = 1'b1;
    #2 reset = 1'b0;


    #80
    Yin = 'b10111111010011001100110011001101;
    Xin = 'b00111111001100110011001100110011;
    reset = 1'b1;
    #2 reset = 1'b0;    
    

    #80
    Xin = 'b00000000011111111111111111111111;
    Yin = 'b00000000000000000000000000000001;
    reset = 1'b1;
    #2 reset = 1'b0;
    

    #80
    Yin = 'b00000000111111111111111111111111;
    Xin = 'b00000000000000000000000000000001;
    reset = 1'b1;
    #2 reset = 1'b0;
    

    #80
    Xin = 'b00000000100000000000000000000000;
    Yin = 'b10000000000000000000000000000001;
    reset = 1'b1;
    #2 reset = 1'b0;
    

    #80
    Xin = 'b00000000100000000000000000000000;
    Yin = 'b10000001000000000000000000000001;
    reset = 1'b1;
    #2 reset = 1'b0;
    

    #80
    Xin = 'b01000000001000000000000000000000;
    Yin = 'b11000000001000000000000000000000;
    reset = 1'b1;
    #2 reset = 1'b0;

   #500
   $write("Simulation has finished");


  end

  adder test_run(Xin, Yin, clk, reset, Zout, done);
  multiplier test_run2(Xin, Yin, clk, reset, Zout2, done2);

endmodule
module FPU_TESTBENCH;



  reg [31:0] Xin, Yin;
  reg clk;

  reg reset;

  wire [31:0] Zout, Zout2;
  wire done, done2;
  
  initial begin
      clk = 'b0;
      forever
      begin
        #2 clk = !clk;
      end
  end
    
  initial begin









    Xin = 'b00111111010011001100110011001101;
    Yin = 'b10111111001100110011001100110011;
    reset = 1'b1;
    #2 reset = 1'b0;


    #80
    Yin = 'b00111111010011001100110011001101;
    Xin = 'b10111111001100110011001100110011;
    reset = 1'b1;
    #2 reset = 1'b0;


    #80
    Xin = 'b10111111010011001100110011001101;
    Yin = 'b00111111001100110011001100110011;
    reset = 1'b1;
    #2 reset = 1'b0;


    #80
    Yin = 'b10111111010011001100110011001101;
    Xin = 'b00111111001100110011001100110011;
    reset = 1'b1;
    #2 reset = 1'b0;    
    

    #80
    Xin = 'b00000000011111111111111111111111;
    Yin = 'b00000000000000000000000000000001;
    reset = 1'b1;
    #2 reset = 1'b0;
    

    #80
    Yin = 'b00000000111111111111111111111111;
    Xin = 'b00000000000000000000000000000001;
    reset = 1'b1;
    #2 reset = 1'b0;
    

    #80
    Xin = 'b00000000100000000000000000000000;
    Yin = 'b10000000000000000000000000000001;
    reset = 1'b1;
    #2 reset = 1'b0;
    

    #80
    Xin = 'b00000000100000000000000000000000;
    Yin = 'b10000001000000000000000000000001;
    reset = 1'b1;
    #2 reset = 1'b0;
    

    #80
    Xin = 'b01000000001000000000000000000000;
    Yin = 'b11000000001000000000000000000000;
    reset = 1'b1;
    #2 reset = 1'b0;

   #500
   $write("Simulation has finished");


  end

  adder test_run(Xin, Yin, clk, reset, Zout, done);
  multiplier test_run2(Xin, Yin, clk, reset, Zout2, done2);

endmodule