data/full_repos/permissive/154123726/3rdParty/simd/Step.v
1: b"%Error: data/full_repos/permissive/154123726/3rdParty/simd/Step.v:63: syntax error, unexpected const, expecting IDENTIFIER or do or final\n wire [1:0] const [0:2][0:3];\n                  ^\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/Step.v:74: syntax error, unexpected const, expecting TYPE-IDENTIFIER\n assign OA[127:96]=(((tmpA[127:96]<<s)|(tmpA[127:96]>>(sp)))+(tmp[const[i][3]]));\n                                                                       ^\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/Step.v:75: syntax error, unexpected const, expecting TYPE-IDENTIFIER\n assign OA[95:64]=(((tmpA[95:64]<<s)|(tmpA[95:64]>>(sp)))+(tmp[const[i][2]]));   \n                                                                    ^\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/Step.v:76: syntax error, unexpected const, expecting TYPE-IDENTIFIER\n assign OA[63:32]=(((tmpA[63:32]<<s)|(tmpA[63:32]>>(sp)))+(tmp[const[i][1]]));\n                                                                    ^\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/Step.v:77: syntax error, unexpected const, expecting TYPE-IDENTIFIER\n assign OA[31:0]=(((tmpA[31:0]<<s)|(tmpA[31:0]>>(sp)))+(tmp[const[i][0]]));\n                                                                 ^\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/Step.v:82: syntax error, unexpected const, expecting TYPE-IDENTIFIER\n assign const[0][0] = 3'd1;\n             ^\n%Error: Exiting due to 6 error(s)\n"
module Step(init,
			IA,
			IB,
			IC,
			ID,
			r,
			s,
			rp,
			sp,
			w,
			i,
			F,
			OA,
			OB,
			OC,
			OD

			);


	input init;
	input [127:0] IA;
	input [127:0] IB;
	input [127:0] IC;
	input [127:0] ID;
	input [4:0] r;
	input [4:0] s;
	input [4:0] rp;
	input [4:0] sp;	
	input [127:0] w;
	input [1:0] i;
	input F;


	output [127:0] OA;
	output [127:0] OB;
	output [127:0] OC;
	output [127:0] OD;
	

	wire [31:0] tmp[0:3];
	wire [127:0] tmpA;
	

	
	wire [1:0] const [0:2][0:3];

	assign tmpA[127:96] = (F==0)?ID[127:96]+w[127:96]+((IA[127:96]&IB[127:96])|(~IA[127:96]&IC[127:96])) : ID[127:96]+w[127:96]+((IC[127:96]&IB[127:96])|(IC[127:96]&IA[127:96])|(IA[127:96]&IB[127:96]));
	assign tmpA[95:64] = (F==0)?ID[95:64]+w[95:64]+((IA[95:64]&IB[95:64])|(~IA[95:64]&IC[95:64])) : ID[95:64]+w[95:64]+((IC[95:64]&IB[95:64])|(IC[95:64]&IA[95:64])|(IA[95:64]&IB[95:64]));
	assign tmpA[63:32] =(F==0)?ID[63:32]+w[63:32]+((IA[63:32]&IB[63:32])|(~IA[63:32]&IC[63:32])) : ID[63:32]+w[63:32]+((IC[63:32]&IB[63:32])|(IC[63:32]&IA[63:32])|(IA[63:32]&IB[63:32]));
	assign tmpA[31:0] =(F==0)?ID[31:0]+w[31:0]+((IA[31:0]&IB[31:0])|(~IA[31:0]&IC[31:0])) : ID[31:0]+w[31:0]+((IC[31:0]&IB[31:0])|(IC[31:0]&IA[31:0])|(IA[31:0]&IB[31:0]));
	assign tmp[3] = (IA[127:96]<<r)|(IA[127:96]>>(rp));
	assign tmp[2] = (IA[95:64]<<r)|(IA[95:64]>>(rp));
	assign tmp[1] = (IA[63:32]<<r)|(IA[63:32]>>(rp));
	assign tmp[0] = (IA[31:0]<<r)|(IA[31:0]>>(rp));

	assign OA[127:96]=(((tmpA[127:96]<<s)|(tmpA[127:96]>>(sp)))+(tmp[const[i][3]]));
	assign OA[95:64]=(((tmpA[95:64]<<s)|(tmpA[95:64]>>(sp)))+(tmp[const[i][2]]));			
	assign OA[63:32]=(((tmpA[63:32]<<s)|(tmpA[63:32]>>(sp)))+(tmp[const[i][1]]));
	assign OA[31:0]=(((tmpA[31:0]<<s)|(tmpA[31:0]>>(sp)))+(tmp[const[i][0]]));
	assign OD=IC;
	assign OC=IB;
	assign OB={tmp[3],tmp[2],tmp[1],tmp[0]};
	
	assign const[0][0] = 3'd1;
	assign const[0][1] = 3'd0;
	assign const[0][2] = 3'd3;
	assign const[0][3] = 3'd2;
	assign const[1][0] = 3'd2;
	assign const[1][1] = 3'd3;
	assign const[1][2] = 3'd0;
	assign const[1][3] = 3'd1;
	assign const[2][0] = 3'd3;
	assign const[2][1] = 3'd2;
	assign const[2][2] = 3'd1;
	assign const[2][3] = 3'd0;

endmodule
module Step(init,
			IA,
			IB,
			IC,
			ID,
			r,
			s,
			rp,
			sp,
			w,
			i,
			F,
			OA,
			OB,
			OC,
			OD

			);



	input init;
	input [127:0] IA;
	input [127:0] IB;
	input [127:0] IC;
	input [127:0] ID;
	input [4:0] r;
	input [4:0] s;
	input [4:0] rp;
	input [4:0] sp;	
	input [127:0] w;
	input [1:0] i;
	input F;


	output [127:0] OA;
	output [127:0] OB;
	output [127:0] OC;
	output [127:0] OD;
	

	wire [31:0] tmp[0:3];
	wire [127:0] tmpA;
	

	
	wire [1:0] const [0:2][0:3];

	assign tmpA[127:96] = (F==0)?ID[127:96]+w[127:96]+((IA[127:96]&IB[127:96])|(~IA[127:96]&IC[127:96])) : ID[127:96]+w[127:96]+((IC[127:96]&IB[127:96])|(IC[127:96]&IA[127:96])|(IA[127:96]&IB[127:96]));
	assign tmpA[95:64] = (F==0)?ID[95:64]+w[95:64]+((IA[95:64]&IB[95:64])|(~IA[95:64]&IC[95:64])) : ID[95:64]+w[95:64]+((IC[95:64]&IB[95:64])|(IC[95:64]&IA[95:64])|(IA[95:64]&IB[95:64]));
	assign tmpA[63:32] =(F==0)?ID[63:32]+w[63:32]+((IA[63:32]&IB[63:32])|(~IA[63:32]&IC[63:32])) : ID[63:32]+w[63:32]+((IC[63:32]&IB[63:32])|(IC[63:32]&IA[63:32])|(IA[63:32]&IB[63:32]));
	assign tmpA[31:0] =(F==0)?ID[31:0]+w[31:0]+((IA[31:0]&IB[31:0])|(~IA[31:0]&IC[31:0])) : ID[31:0]+w[31:0]+((IC[31:0]&IB[31:0])|(IC[31:0]&IA[31:0])|(IA[31:0]&IB[31:0]));
	assign tmp[3] = (IA[127:96]<<r)|(IA[127:96]>>(rp));
	assign tmp[2] = (IA[95:64]<<r)|(IA[95:64]>>(rp));
	assign tmp[1] = (IA[63:32]<<r)|(IA[63:32]>>(rp));
	assign tmp[0] = (IA[31:0]<<r)|(IA[31:0]>>(rp));

	assign OA[127:96]=(((tmpA[127:96]<<s)|(tmpA[127:96]>>(sp)))+(tmp[const[i][3]]));
	assign OA[95:64]=(((tmpA[95:64]<<s)|(tmpA[95:64]>>(sp)))+(tmp[const[i][2]]));			
	assign OA[63:32]=(((tmpA[63:32]<<s)|(tmpA[63:32]>>(sp)))+(tmp[const[i][1]]));
	assign OA[31:0]=(((tmpA[31:0]<<s)|(tmpA[31:0]>>(sp)))+(tmp[const[i][0]]));
	assign OD=IC;
	assign OC=IB;
	assign OB={tmp[3],tmp[2],tmp[1],tmp[0]};
	
	assign const[0][0] = 3'd1;
	assign const[0][1] = 3'd0;
	assign const[0][2] = 3'd3;
	assign const[0][3] = 3'd2;
	assign const[1][0] = 3'd2;
	assign const[1][1] = 3'd3;
	assign const[1][2] = 3'd0;
	assign const[1][3] = 3'd1;
	assign const[2][0] = 3'd3;
	assign const[2][1] = 3'd2;
	assign const[2][2] = 3'd1;
	assign const[2][3] = 3'd0;

endmodule