data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v
 line:72: before: "."
1: b'%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_top.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, tb_top);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:18: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, i_axi4s_master_model);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:19: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, i_top);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:20: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, i_top.i_image_processing);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:21: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, i_top.i_image_processing.i_img_mean_grad_to_angle);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:22: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, i_top.i_data_logger_fifo_img);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:23: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, i_top.i_data_logger_fifo_motor);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #100000000\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:30: Unsupported: Ignoring delay on this delayed statement.\n    always #(RATE125/2.0)   clk125 = ~clk125;\n           ^\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:114: Unsupported: Verilog 1995 force\n        force i_top.axi4s_csi2_tuser  = axi4s_model_tuser;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:115: Unsupported: Verilog 1995 force\n        force i_top.axi4s_csi2_tlast  = axi4s_model_tlast;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:116: Unsupported: Verilog 1995 force\n        force i_top.axi4s_csi2_tdata  = {axi4s_model_tdata, 2\'d0};\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:117: Unsupported: Verilog 1995 force\n        force i_top.axi4s_csi2_tvalid = axi4s_model_tvalid & axi4s_model_enbale;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:169: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_adr_i = wb_adr_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:170: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_dat_i = wb_dat_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:171: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_we_i  = wb_we_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:172: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_sel_i = wb_sel_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:173: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_stb_i = wb_stb_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:194: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:200: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:202: syntax error, unexpected \'@\'\n                @(negedge wb_clk_i);\n                ^\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:216: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:222: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:224: syntax error, unexpected \'@\'\n                @(negedge wb_clk_i);\n                ^\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:238: syntax error, unexpected \'@\'\n    @(negedge wb_rst_i);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:239: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:242: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:257: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:281: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:294: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/zybo_z7_imx219_stepper_motor/sim/tb_top/tb_top.v:299: Unsupported: Ignoring delay on this delayed statement.\n    #1000000;\n    ^\n%Error: Exiting due to 24 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top();
    localparam RATE125 = 1000.0/125.0;
    
    initial begin
        $dumpfile("tb_top.vcd");
        $dumpvars(1, tb_top);
        $dumpvars(1, i_axi4s_master_model);
        $dumpvars(1, i_top);
        $dumpvars(1, i_top.i_image_processing);
        $dumpvars(1, i_top.i_image_processing.i_img_mean_grad_to_angle);
        $dumpvars(1, i_top.i_data_logger_fifo_img);
        $dumpvars(1, i_top.i_data_logger_fifo_motor);
        
    #100000000
        $finish;
    end
    
    reg     clk125 = 1'b1;
    always #(RATE125/2.0)   clk125 = ~clk125;
    
    



    parameter   X_NUM = 64;
    parameter   Y_NUM = 64;
    
    
    zybo_z7_imx219_stepper_motor
        i_top
            (
                .in_clk125      (clk125),
                
                .push_sw        (0),
                .dip_sw         (0),
                .led            (),
                .pmod_a         ()
            );
    
    wire                    atan_clk         = i_top.i_image_processing.clk;
    wire                    atan_cke         = i_top.i_image_processing.cke;
    wire    signed  [46:0]  atan_s_x     = i_top.i_image_processing.i_img_mean_grad_to_angle.i_fixed_atan2_multicycle.s_x;
    wire    signed  [46:0]  atan_s_y     = i_top.i_image_processing.i_img_mean_grad_to_angle.i_fixed_atan2_multicycle.s_y;
    wire                    atan_s_valid = i_top.i_image_processing.i_img_mean_grad_to_angle.i_fixed_atan2_multicycle.s_valid;
    wire    signed  [31:0]  atan_m_angle = i_top.i_image_processing.i_img_mean_grad_to_angle.i_fixed_atan2_multicycle.m_angle;
    wire                    atan_m_valid = i_top.i_image_processing.i_img_mean_grad_to_angle.i_fixed_atan2_multicycle.m_valid;
    reg     signed  [46:0]  reg_atan_x;
    reg     signed  [46:0]  reg_atan_y;
    reg     signed  [31:0]  reg_atan_angle;
    always @(posedge atan_clk) begin
        if ( atan_cke ) begin
            if ( atan_s_valid ) begin
                reg_atan_x <= atan_s_x;
                reg_atan_y <= atan_s_y;
            end
            if ( atan_m_valid ) begin
                reg_atan_angle <= atan_m_angle;
            end
        end
    end
    
    



    
    reg             axi4s_model_enbale = 1'b0;
    
    wire            axi4s_model_aresetn = i_top.axi4s_cam_aresetn;
    wire            axi4s_model_aclk    = i_top.axi4s_cam_aclk;
    wire    [0:0]   axi4s_model_tuser;
    wire            axi4s_model_tlast;
    wire    [7:0]   axi4s_model_tdata;
    wire            axi4s_model_tvalid;
    wire            axi4s_model_tready = i_top.axi4s_csi2_tready & axi4s_model_enbale;
    
    jelly_axi4s_master_model
            #(
                .AXI4S_DATA_WIDTH   (8),
                .X_NUM              (X_NUM),
                .Y_NUM              (Y_NUM),
                .PGM_FILE           ("img_0000.pgm"),
                .SEQUENTIAL_FILE    (1),
                .DIGIT_NUM          (4),
                .DIGIT_POS          (4),
                .BUSY_RATE          (0),
                .RANDOM_SEED        (0),
                .INTERVAL           (X_NUM * 10)
            )
        i_axi4s_master_model
            (
                .aresetn            (axi4s_model_aresetn),
                .aclk               (axi4s_model_aclk),
                
                .m_axi4s_tuser      (axi4s_model_tuser),
                .m_axi4s_tlast      (axi4s_model_tlast),
                .m_axi4s_tdata      (axi4s_model_tdata),
                .m_axi4s_tvalid     (axi4s_model_tvalid),
                .m_axi4s_tready     (axi4s_model_tready)
            );
    
    initial begin
        force i_top.axi4s_csi2_tuser  = axi4s_model_tuser;
        force i_top.axi4s_csi2_tlast  = axi4s_model_tlast;
        force i_top.axi4s_csi2_tdata  = {axi4s_model_tdata, 2'd0};
        force i_top.axi4s_csi2_tvalid = axi4s_model_tvalid & axi4s_model_enbale;
    end
    
    
    

    jelly_img_record_model
            #(
                .COMPONENT_NUM  (1),
                .DATA_WIDTH     (10),
                .FILE_NAME      ("src_%04d.pgm")
            )
        i_img_record_model_src
            (
                .reset              (i_top.i_image_processing.reset),
                .clk                (i_top.i_image_processing.clk),
                .cke                (i_top.i_image_processing.cke),
                
                .param_width        (X_NUM),
                .param_height       (Y_NUM),
                
                .s_img_line_first   (i_top.i_image_processing.img_src_line_first),
                .s_img_line_last    (i_top.i_image_processing.img_src_line_last),
                .s_img_pixel_first  (i_top.i_image_processing.img_src_pixel_first),
                .s_img_pixel_last   (i_top.i_image_processing.img_src_pixel_last),
                .s_img_de           (i_top.i_image_processing.img_src_de),
                .s_img_data         (i_top.i_image_processing.img_src_data),
                .s_img_valid        (i_top.i_image_processing.img_src_valid)
            );
    
    
    
    



    
    parameter   WB_ADR_WIDTH        = 30;
    parameter   WB_DAT_WIDTH        = 32;
    parameter   WB_SEL_WIDTH        = (WB_DAT_WIDTH / 8);
    
    wire                            wb_rst_i = i_top.wb_peri_rst_i;
    wire                            wb_clk_i = i_top.wb_peri_clk_i;
    reg     [WB_ADR_WIDTH-1:0]      wb_adr_o;
    wire    [WB_DAT_WIDTH-1:0]      wb_dat_i = i_top.wb_peri_dat_o;
    reg     [WB_DAT_WIDTH-1:0]      wb_dat_o;
    reg                             wb_we_o;
    reg     [WB_SEL_WIDTH-1:0]      wb_sel_o;
    reg                             wb_stb_o = 0;
    wire                            wb_ack_i = i_top.wb_peri_ack_o;
    
    initial begin
        force i_top.wb_peri_adr_i = wb_adr_o;
        force i_top.wb_peri_dat_i = wb_dat_o;
        force i_top.wb_peri_we_i  = wb_we_o;
        force i_top.wb_peri_sel_i = wb_sel_o;
        force i_top.wb_peri_stb_i = wb_stb_o;
    end
    
    
    reg     [WB_DAT_WIDTH-1:0]      reg_wb_dat;
    reg                             reg_wb_ack;
    always @(posedge wb_clk_i) begin
        if ( ~wb_we_o & wb_stb_o & wb_ack_i ) begin
            reg_wb_dat <= wb_dat_i;
        end
        reg_wb_ack <= wb_ack_i;
    end
    
    
    task wb_write(
                input [31:0]    adr,
                input [31:0]    dat,
                input [3:0]     sel
            );
    begin
        $display("WISHBONE_WRITE(adr:%h dat:%h sel:%b)", adr, dat, sel);
        @(negedge wb_clk_i);
            wb_adr_o = (adr >> 2);
            wb_dat_o = dat;
            wb_sel_o = sel;
            wb_we_o  = 1'b1;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
    end
    endtask
    
    task wb_read(
                input [31:0]    adr
            );
    begin
        @(negedge wb_clk_i);
            wb_adr_o = (adr >> 2);
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'b1}};
            wb_we_o  = 1'b0;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
            $display("WISHBONE_READ(adr:%h dat:%h)", adr, reg_wb_dat);
    end
    endtask
    
    
    
    initial begin
    @(negedge wb_rst_i);
    #10000;
        $display("start");

    #1000;
        $display("read core ID");
        wb_read(32'h40010000);
        wb_read(32'h40011000);
        wb_read(32'h40021000);
        wb_read(32'h40030000);
        wb_read(32'h40030400);
        wb_read(32'h40030800);
        wb_read(32'h40030c00);
        wb_read(32'h40033c00);
        wb_read(32'h40041000);
        wb_read(32'h40042000);
        wb_read(32'h40070000);
        wb_read(32'h40071000);
        
    #1000;

        $display("set demosaic");
        wb_write(32'h40030040,     0, 4'b1111);
        wb_write(32'h40030010,     3, 4'b1111);


        $display("set gauss");
        wb_write(32'h40030800 + 8'h08*4, 32'h000f, 4'b1111);
        wb_write(32'h40030800 + 8'h04*4, 32'h0003, 4'b1111);
        



        
        

        $display("set format reg");
        wb_write(32'h40010040, X_NUM, 4'b1111);
        wb_write(32'h40010044, Y_NUM, 4'b1111);
        wb_write(32'h40010048,     0, 4'b1111);
        wb_write(32'h4001004c,  1024, 4'b1111);
        wb_write(32'h40010010,     1, 4'b1111);
    
    #1000;
        $display("start image input");
        axi4s_model_enbale = 1'b1;
        
        $display("start motor");
        wb_write(32'h40031000 + 4*8'h09,  10000, 4'b1111);
        wb_write(32'h40031000 + 4*8'h0a,    100, 4'b1111);
        wb_write(32'h40031000 + 4*8'h0f,    200, 4'b1111);
        wb_write(32'h40031000 + 4*8'h04, 100000, 4'b1111);
        wb_write(32'h40031000 + 4*8'h02,      1, 4'b1111);
        wb_write(32'h40031000 + 4*8'h01,      1, 4'b1111);
        
        
    #10000;
        $display("set selector");
        wb_write(32'h40043c00,     1, 4'b1111);
        
        
    #1000000;
        $display("log0 read0");
        wb_read (32'h40070000 + 4*8'h05);
        wb_read (32'h40070000 + 4*8'h07);
        wb_read (32'h40070000 + 4*8'h08);
        wb_read (32'h40070000 + 4*8'h09);
        wb_read (32'h40070000 + 4*8'h10);
        wb_write(32'h40070000 + 4*8'h04, 1, 4'b1111);
        
        $display("log0 read1");
        wb_read (32'h40070000 + 4*8'h05);
        wb_read (32'h40070000 + 4*8'h07);
        wb_read (32'h40070000 + 4*8'h08);
        wb_read (32'h40070000 + 4*8'h09);
        wb_read (32'h40070000 + 4*8'h10);
        wb_write(32'h40070000 + 4*8'h04, 1, 4'b1111);
        
        $display("log0 read2");
        wb_read (32'h40070000 + 4*8'h05);
        wb_read (32'h40070000 + 4*8'h07);
        wb_read (32'h40070000 + 4*8'h08);
        wb_read (32'h40070000 + 4*8'h09);
        wb_read (32'h40070000 + 4*8'h10);
        wb_write(32'h40070000 + 4*8'h04, 1, 4'b1111);
        
        
        $display("log1 read0");
        wb_read (32'h40071000 + 4*8'h05);
        wb_read (32'h40071000 + 4*8'h07);
        wb_read (32'h40071000 + 4*8'h08);
        wb_read (32'h40071000 + 4*8'h09);
        wb_read (32'h40071000 + 4*8'h10);
        wb_read (32'h40071000 + 4*8'h11);
        wb_read (32'h40071000 + 4*8'h12);
        wb_read (32'h40071000 + 4*8'h13);
        wb_read (32'h40071000 + 4*8'h14);
        wb_read (32'h40071000 + 4*8'h15);
        wb_read (32'h40071000 + 4*8'h16);
        wb_read (32'h40071000 + 4*8'h17);
        wb_write(32'h40071000 + 4*8'h04, 1, 4'b1111);
        
        $display("log1 read1");
        wb_read (32'h40071000 + 4*8'h05);
        wb_read (32'h40071000 + 4*8'h07);
        wb_read (32'h40071000 + 4*8'h08);
        wb_read (32'h40071000 + 4*8'h09);
        wb_read (32'h40071000 + 4*8'h10);
        wb_read (32'h40071000 + 4*8'h11);
        wb_read (32'h40071000 + 4*8'h12);
        wb_read (32'h40071000 + 4*8'h13);
        wb_read (32'h40071000 + 4*8'h14);
        wb_read (32'h40071000 + 4*8'h15);
        wb_read (32'h40071000 + 4*8'h16);
        wb_read (32'h40071000 + 4*8'h17);
        wb_write(32'h40071000 + 4*8'h04, 1, 4'b1111);
        
        $display("log0 read2");
        wb_read (32'h40071000 + 4*8'h05);
        wb_read (32'h40071000 + 4*8'h07);
        wb_read (32'h40071000 + 4*8'h08);
        wb_read (32'h40071000 + 4*8'h09);
        wb_read (32'h40071000 + 4*8'h10);
        wb_read (32'h40071000 + 4*8'h11);
        wb_read (32'h40071000 + 4*8'h12);
        wb_read (32'h40071000 + 4*8'h13);
        wb_read (32'h40071000 + 4*8'h14);
        wb_read (32'h40071000 + 4*8'h15);
        wb_read (32'h40071000 + 4*8'h16);
        wb_read (32'h40071000 + 4*8'h17);
        wb_write(32'h40071000 + 4*8'h04, 1, 4'b1111);
        

        
    end
    
    
endmodule
module tb_top();

    localparam RATE125 = 1000.0/125.0;
    
    initial begin
        $dumpfile("tb_top.vcd");
        $dumpvars(1, tb_top);
        $dumpvars(1, i_axi4s_master_model);
        $dumpvars(1, i_top);
        $dumpvars(1, i_top.i_image_processing);
        $dumpvars(1, i_top.i_image_processing.i_img_mean_grad_to_angle);
        $dumpvars(1, i_top.i_data_logger_fifo_img);
        $dumpvars(1, i_top.i_data_logger_fifo_motor);
        
    #100000000
        $finish;
    end
    
    reg     clk125 = 1'b1;
    always #(RATE125/2.0)   clk125 = ~clk125;
    
    



    parameter   X_NUM = 64;
    parameter   Y_NUM = 64;
    
    
    zybo_z7_imx219_stepper_motor
        i_top
            (
                .in_clk125      (clk125),
                
                .push_sw        (0),
                .dip_sw         (0),
                .led            (),
                .pmod_a         ()
            );
    
    wire                    atan_clk         = i_top.i_image_processing.clk;
    wire                    atan_cke         = i_top.i_image_processing.cke;
    wire    signed  [46:0]  atan_s_x     = i_top.i_image_processing.i_img_mean_grad_to_angle.i_fixed_atan2_multicycle.s_x;
    wire    signed  [46:0]  atan_s_y     = i_top.i_image_processing.i_img_mean_grad_to_angle.i_fixed_atan2_multicycle.s_y;
    wire                    atan_s_valid = i_top.i_image_processing.i_img_mean_grad_to_angle.i_fixed_atan2_multicycle.s_valid;
    wire    signed  [31:0]  atan_m_angle = i_top.i_image_processing.i_img_mean_grad_to_angle.i_fixed_atan2_multicycle.m_angle;
    wire                    atan_m_valid = i_top.i_image_processing.i_img_mean_grad_to_angle.i_fixed_atan2_multicycle.m_valid;
    reg     signed  [46:0]  reg_atan_x;
    reg     signed  [46:0]  reg_atan_y;
    reg     signed  [31:0]  reg_atan_angle;
    always @(posedge atan_clk) begin
        if ( atan_cke ) begin
            if ( atan_s_valid ) begin
                reg_atan_x <= atan_s_x;
                reg_atan_y <= atan_s_y;
            end
            if ( atan_m_valid ) begin
                reg_atan_angle <= atan_m_angle;
            end
        end
    end
    
    



    
    reg             axi4s_model_enbale = 1'b0;
    
    wire            axi4s_model_aresetn = i_top.axi4s_cam_aresetn;
    wire            axi4s_model_aclk    = i_top.axi4s_cam_aclk;
    wire    [0:0]   axi4s_model_tuser;
    wire            axi4s_model_tlast;
    wire    [7:0]   axi4s_model_tdata;
    wire            axi4s_model_tvalid;
    wire            axi4s_model_tready = i_top.axi4s_csi2_tready & axi4s_model_enbale;
    
    jelly_axi4s_master_model
            #(
                .AXI4S_DATA_WIDTH   (8),
                .X_NUM              (X_NUM),
                .Y_NUM              (Y_NUM),
                .PGM_FILE           ("img_0000.pgm"),
                .SEQUENTIAL_FILE    (1),
                .DIGIT_NUM          (4),
                .DIGIT_POS          (4),
                .BUSY_RATE          (0),
                .RANDOM_SEED        (0),
                .INTERVAL           (X_NUM * 10)
            )
        i_axi4s_master_model
            (
                .aresetn            (axi4s_model_aresetn),
                .aclk               (axi4s_model_aclk),
                
                .m_axi4s_tuser      (axi4s_model_tuser),
                .m_axi4s_tlast      (axi4s_model_tlast),
                .m_axi4s_tdata      (axi4s_model_tdata),
                .m_axi4s_tvalid     (axi4s_model_tvalid),
                .m_axi4s_tready     (axi4s_model_tready)
            );
    
    initial begin
        force i_top.axi4s_csi2_tuser  = axi4s_model_tuser;
        force i_top.axi4s_csi2_tlast  = axi4s_model_tlast;
        force i_top.axi4s_csi2_tdata  = {axi4s_model_tdata, 2'd0};
        force i_top.axi4s_csi2_tvalid = axi4s_model_tvalid & axi4s_model_enbale;
    end
    
    
    

    jelly_img_record_model
            #(
                .COMPONENT_NUM  (1),
                .DATA_WIDTH     (10),
                .FILE_NAME      ("src_%04d.pgm")
            )
        i_img_record_model_src
            (
                .reset              (i_top.i_image_processing.reset),
                .clk                (i_top.i_image_processing.clk),
                .cke                (i_top.i_image_processing.cke),
                
                .param_width        (X_NUM),
                .param_height       (Y_NUM),
                
                .s_img_line_first   (i_top.i_image_processing.img_src_line_first),
                .s_img_line_last    (i_top.i_image_processing.img_src_line_last),
                .s_img_pixel_first  (i_top.i_image_processing.img_src_pixel_first),
                .s_img_pixel_last   (i_top.i_image_processing.img_src_pixel_last),
                .s_img_de           (i_top.i_image_processing.img_src_de),
                .s_img_data         (i_top.i_image_processing.img_src_data),
                .s_img_valid        (i_top.i_image_processing.img_src_valid)
            );
    
    
    
    



    
    parameter   WB_ADR_WIDTH        = 30;
    parameter   WB_DAT_WIDTH        = 32;
    parameter   WB_SEL_WIDTH        = (WB_DAT_WIDTH / 8);
    
    wire                            wb_rst_i = i_top.wb_peri_rst_i;
    wire                            wb_clk_i = i_top.wb_peri_clk_i;
    reg     [WB_ADR_WIDTH-1:0]      wb_adr_o;
    wire    [WB_DAT_WIDTH-1:0]      wb_dat_i = i_top.wb_peri_dat_o;
    reg     [WB_DAT_WIDTH-1:0]      wb_dat_o;
    reg                             wb_we_o;
    reg     [WB_SEL_WIDTH-1:0]      wb_sel_o;
    reg                             wb_stb_o = 0;
    wire                            wb_ack_i = i_top.wb_peri_ack_o;
    
    initial begin
        force i_top.wb_peri_adr_i = wb_adr_o;
        force i_top.wb_peri_dat_i = wb_dat_o;
        force i_top.wb_peri_we_i  = wb_we_o;
        force i_top.wb_peri_sel_i = wb_sel_o;
        force i_top.wb_peri_stb_i = wb_stb_o;
    end
    
    
    reg     [WB_DAT_WIDTH-1:0]      reg_wb_dat;
    reg                             reg_wb_ack;
    always @(posedge wb_clk_i) begin
        if ( ~wb_we_o & wb_stb_o & wb_ack_i ) begin
            reg_wb_dat <= wb_dat_i;
        end
        reg_wb_ack <= wb_ack_i;
    end
    
    
    task wb_write(
                input [31:0]    adr,
                input [31:0]    dat,
                input [3:0]     sel
            );
    begin
        $display("WISHBONE_WRITE(adr:%h dat:%h sel:%b)", adr, dat, sel);
        @(negedge wb_clk_i);
            wb_adr_o = (adr >> 2);
            wb_dat_o = dat;
            wb_sel_o = sel;
            wb_we_o  = 1'b1;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
    end
    endtask
    
    task wb_read(
                input [31:0]    adr
            );
    begin
        @(negedge wb_clk_i);
            wb_adr_o = (adr >> 2);
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'b1}};
            wb_we_o  = 1'b0;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
            $display("WISHBONE_READ(adr:%h dat:%h)", adr, reg_wb_dat);
    end
    endtask
    
    
    
    initial begin
    @(negedge wb_rst_i);
    #10000;
        $display("start");

    #1000;
        $display("read core ID");
        wb_read(32'h40010000);
        wb_read(32'h40011000);
        wb_read(32'h40021000);
        wb_read(32'h40030000);
        wb_read(32'h40030400);
        wb_read(32'h40030800);
        wb_read(32'h40030c00);
        wb_read(32'h40033c00);
        wb_read(32'h40041000);
        wb_read(32'h40042000);
        wb_read(32'h40070000);
        wb_read(32'h40071000);
        
    #1000;

        $display("set demosaic");
        wb_write(32'h40030040,     0, 4'b1111);
        wb_write(32'h40030010,     3, 4'b1111);


        $display("set gauss");
        wb_write(32'h40030800 + 8'h08*4, 32'h000f, 4'b1111);
        wb_write(32'h40030800 + 8'h04*4, 32'h0003, 4'b1111);
        



        
        

        $display("set format reg");
        wb_write(32'h40010040, X_NUM, 4'b1111);
        wb_write(32'h40010044, Y_NUM, 4'b1111);
        wb_write(32'h40010048,     0, 4'b1111);
        wb_write(32'h4001004c,  1024, 4'b1111);
        wb_write(32'h40010010,     1, 4'b1111);
    
    #1000;
        $display("start image input");
        axi4s_model_enbale = 1'b1;
        
        $display("start motor");
        wb_write(32'h40031000 + 4*8'h09,  10000, 4'b1111);
        wb_write(32'h40031000 + 4*8'h0a,    100, 4'b1111);
        wb_write(32'h40031000 + 4*8'h0f,    200, 4'b1111);
        wb_write(32'h40031000 + 4*8'h04, 100000, 4'b1111);
        wb_write(32'h40031000 + 4*8'h02,      1, 4'b1111);
        wb_write(32'h40031000 + 4*8'h01,      1, 4'b1111);
        
        
    #10000;
        $display("set selector");
        wb_write(32'h40043c00,     1, 4'b1111);
        
        
    #1000000;
        $display("log0 read0");
        wb_read (32'h40070000 + 4*8'h05);
        wb_read (32'h40070000 + 4*8'h07);
        wb_read (32'h40070000 + 4*8'h08);
        wb_read (32'h40070000 + 4*8'h09);
        wb_read (32'h40070000 + 4*8'h10);
        wb_write(32'h40070000 + 4*8'h04, 1, 4'b1111);
        
        $display("log0 read1");
        wb_read (32'h40070000 + 4*8'h05);
        wb_read (32'h40070000 + 4*8'h07);
        wb_read (32'h40070000 + 4*8'h08);
        wb_read (32'h40070000 + 4*8'h09);
        wb_read (32'h40070000 + 4*8'h10);
        wb_write(32'h40070000 + 4*8'h04, 1, 4'b1111);
        
        $display("log0 read2");
        wb_read (32'h40070000 + 4*8'h05);
        wb_read (32'h40070000 + 4*8'h07);
        wb_read (32'h40070000 + 4*8'h08);
        wb_read (32'h40070000 + 4*8'h09);
        wb_read (32'h40070000 + 4*8'h10);
        wb_write(32'h40070000 + 4*8'h04, 1, 4'b1111);
        
        
        $display("log1 read0");
        wb_read (32'h40071000 + 4*8'h05);
        wb_read (32'h40071000 + 4*8'h07);
        wb_read (32'h40071000 + 4*8'h08);
        wb_read (32'h40071000 + 4*8'h09);
        wb_read (32'h40071000 + 4*8'h10);
        wb_read (32'h40071000 + 4*8'h11);
        wb_read (32'h40071000 + 4*8'h12);
        wb_read (32'h40071000 + 4*8'h13);
        wb_read (32'h40071000 + 4*8'h14);
        wb_read (32'h40071000 + 4*8'h15);
        wb_read (32'h40071000 + 4*8'h16);
        wb_read (32'h40071000 + 4*8'h17);
        wb_write(32'h40071000 + 4*8'h04, 1, 4'b1111);
        
        $display("log1 read1");
        wb_read (32'h40071000 + 4*8'h05);
        wb_read (32'h40071000 + 4*8'h07);
        wb_read (32'h40071000 + 4*8'h08);
        wb_read (32'h40071000 + 4*8'h09);
        wb_read (32'h40071000 + 4*8'h10);
        wb_read (32'h40071000 + 4*8'h11);
        wb_read (32'h40071000 + 4*8'h12);
        wb_read (32'h40071000 + 4*8'h13);
        wb_read (32'h40071000 + 4*8'h14);
        wb_read (32'h40071000 + 4*8'h15);
        wb_read (32'h40071000 + 4*8'h16);
        wb_read (32'h40071000 + 4*8'h17);
        wb_write(32'h40071000 + 4*8'h04, 1, 4'b1111);
        
        $display("log0 read2");
        wb_read (32'h40071000 + 4*8'h05);
        wb_read (32'h40071000 + 4*8'h07);
        wb_read (32'h40071000 + 4*8'h08);
        wb_read (32'h40071000 + 4*8'h09);
        wb_read (32'h40071000 + 4*8'h10);
        wb_read (32'h40071000 + 4*8'h11);
        wb_read (32'h40071000 + 4*8'h12);
        wb_read (32'h40071000 + 4*8'h13);
        wb_read (32'h40071000 + 4*8'h14);
        wb_read (32'h40071000 + 4*8'h15);
        wb_read (32'h40071000 + 4*8'h16);
        wb_read (32'h40071000 + 4*8'h17);
        wb_write(32'h40071000 + 4*8'h04, 1, 4'b1111);
        

        
    end
    
    
endmodule