data/full_repos/permissive/130234582/src/clk_gen.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/130234582/src/clk_gen.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD_PS/2) clk = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/130234582/src/clk_gen.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD_PS-PERIOD_PS/2) clk = 1;\n        ^\n%Warning-INFINITELOOP: data/full_repos/permissive/130234582/src/clk_gen.v:8: Infinite loop (condition always true)\n                                                                           : ... In instance clk_gen\n    forever begin\n    ^~~~~~~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clk_gen
#(  parameter PERIOD_PS=100 )
(   output reg clk          );

initial begin
    clk = 0;
    forever begin
        #(PERIOD_PS/2) clk = 0;
        #(PERIOD_PS-PERIOD_PS/2) clk = 1;
    end    
end

endmodule
module clk_gen
#(  parameter PERIOD_PS=100 )
(   output reg clk          );


initial begin
    clk = 0;
    forever begin
        #(PERIOD_PS/2) clk = 0;
        #(PERIOD_PS-PERIOD_PS/2) clk = 1;
    end    
end

endmodule