data/full_repos/permissive/19340845/src/SZCVRegister.v
data/verilator_xmls/cb1c1770-6996-410a-83f2-3131b249aeab.xml
module SZCVRegister(
   input [3:0] 	SZCV_in,
   input 	FLAG_write, CLOCK,
   output [3:0] SZCV_out);

   reg [3:0] 	SZCV;
   
   
   always @ (posedge CLOCK) begin
      if (FLAG_write == 1'b1)
	SZCV <= SZCV_in;
   end
   
   assign SZCV_out = SZCV;
   
endmodule
module SZCVRegister(
   input [3:0] 	SZCV_in,
   input 	FLAG_write, CLOCK,
   output [3:0] SZCV_out);


   reg [3:0] 	SZCV;
   
   
   always @ (posedge CLOCK) begin
      if (FLAG_write == 1'b1)
	SZCV <= SZCV_in;
   end
   
   assign SZCV_out = SZCV;
   
endmodule