data/full_repos/permissive/212008255/codes/decoder_8x3/decoder_83_tb.v
1: b'%Error: data/full_repos/permissive/212008255/codes/decoder_8x3/decoder_83_tb.v:37: Unsupported or unknown PLI call: $monitor\n$monitor ("%b %b  %b  %b  %b  %b  %b  %b  %b  %b  %b  %b", \n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/212008255/codes/decoder_8x3/decoder_83_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #5 s_0=~s_0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212008255/codes/decoder_8x3/decoder_83_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #10 s_1=~s_1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/212008255/codes/decoder_8x3/decoder_83_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #15 s_2=~s_2;\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decoder_83_tb;

	reg s_0;
	reg s_1;
	reg s_2;
	reg e;

	wire q_0;
	wire q_1;
	wire q_2;
	wire q_3;
	wire q_4;
	wire q_5;
	wire q_6;
	wire q_7;

	decoder_83 uut (
		.s_0(s_0), 
		.s_1(s_1), 
		.s_2(s_2), 
		.e(e), 
		.q_0(q_0), 
		.q_1(q_1), 
		.q_2(q_2), 
		.q_3(q_3), 
		.q_4(q_4), 
		.q_5(q_5), 
		.q_6(q_6), 
		.q_7(q_7)
	);

	initial begin
		
	$display ("e s_0 s_1 s_2 I0 I1 I2 I3 I4 I5 I6 I7");
$monitor ("%b %b  %b  %b  %b  %b  %b  %b  %b  %b  %b  %b", 
	    e,s_0,s_1,s_2,q_0,q_1,q_2,q_3,q_4,q_5,q_6,q_7);
		s_0 = 0;
		s_1 = 0;
		s_2 = 0;
		e = 1;
	end
	
      always begin
	#5 s_0=~s_0;
	end
	
	always begin
	#10 s_1=~s_1;
	end
	
   always begin
	#15 s_2=~s_2;
	end
endmodule
module decoder_83_tb;


	reg s_0;
	reg s_1;
	reg s_2;
	reg e;

	wire q_0;
	wire q_1;
	wire q_2;
	wire q_3;
	wire q_4;
	wire q_5;
	wire q_6;
	wire q_7;

	decoder_83 uut (
		.s_0(s_0), 
		.s_1(s_1), 
		.s_2(s_2), 
		.e(e), 
		.q_0(q_0), 
		.q_1(q_1), 
		.q_2(q_2), 
		.q_3(q_3), 
		.q_4(q_4), 
		.q_5(q_5), 
		.q_6(q_6), 
		.q_7(q_7)
	);

	initial begin
		
	$display ("e s_0 s_1 s_2 I0 I1 I2 I3 I4 I5 I6 I7");
$monitor ("%b %b  %b  %b  %b  %b  %b  %b  %b  %b  %b  %b", 
	    e,s_0,s_1,s_2,q_0,q_1,q_2,q_3,q_4,q_5,q_6,q_7);
		s_0 = 0;
		s_1 = 0;
		s_2 = 0;
		e = 1;
	end
	
      always begin
	#5 s_0=~s_0;
	end
	
	always begin
	#10 s_1=~s_1;
	end
	
   always begin
	#15 s_2=~s_2;
	end
endmodule