data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/basic_shuffler.v
1: b"%Error: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/basic_shuffler.v:29: Cannot find file containing module: 'buf88'\nbuf88 M2 (.a(b),.clk(clk),.a1(b3));\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/219219909/3-parallel_Data_Shuffler,data/full_repos/permissive/219219909/buf88\n             data/full_repos/permissive/219219909/3-parallel_Data_Shuffler,data/full_repos/permissive/219219909/buf88.v\n             data/full_repos/permissive/219219909/3-parallel_Data_Shuffler,data/full_repos/permissive/219219909/buf88.sv\n             buf88\n             buf88.v\n             buf88.sv\n             obj_dir/buf88\n             obj_dir/buf88.v\n             obj_dir/buf88.sv\n%Error: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/basic_shuffler.v:30: Cannot find file containing module: 'mux_2x1'\nmux_2x1 M3 (.data0(a),.data1(b3),.sel(sel),.data_out(a3));\n^~~~~~~\n%Error: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/basic_shuffler.v:31: Cannot find file containing module: 'buf88'\nbuf88 M4 (.a(a3),.clk(clk),.a1(a1));\n^~~~~\n%Error: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/basic_shuffler.v:32: Cannot find file containing module: 'mux_2x1'\nmux_2x1 M5 (.data0(b3),.data1(a),.sel(sel),.data_out(b4));\n^~~~~~~\n%Error: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/basic_shuffler.v:33: Cannot find file containing module: 'buf87'\nbuf87 M6 (.a(b4),.clk(clk),.a1(b1));\n^~~~~\n%Error: Exiting due to 5 error(s)\n"
module basic_shuffler(
    input [31:0] a,
    input [31:0] b,
	 input sel,clk,
    output [31:0] a1,
    output [31:0] b1
    );
wire [31:0] a2,a3,b2,b3,b4;
buf88 M2 (.a(b),.clk(clk),.a1(b3));
mux_2x1 M3 (.data0(a),.data1(b3),.sel(sel),.data_out(a3));
buf88 M4 (.a(a3),.clk(clk),.a1(a1));
mux_2x1 M5 (.data0(b3),.data1(a),.sel(sel),.data_out(b4));
buf87 M6 (.a(b4),.clk(clk),.a1(b1));
endmodule
module basic_shuffler(
    input [31:0] a,
    input [31:0] b,
	 input sel,clk,
    output [31:0] a1,
    output [31:0] b1
    );

wire [31:0] a2,a3,b2,b3,b4;
buf88 M2 (.a(b),.clk(clk),.a1(b3));
mux_2x1 M3 (.data0(a),.data1(b3),.sel(sel),.data_out(a3));
buf88 M4 (.a(a3),.clk(clk),.a1(a1));
mux_2x1 M5 (.data0(b3),.data1(a),.sel(sel),.data_out(b4));
buf87 M6 (.a(b4),.clk(clk),.a1(b1));
endmodule