data/full_repos/permissive/184332405/adder_subtractor_tb.v
 line:39: before: "$"
1: b'%Error: data/full_repos/permissive/184332405/adder_subtractor_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("adder_subtractor.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/184332405/adder_subtractor_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,Johnson);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/184332405/adder_subtractor_tb.v:15: Unsupported or unknown PLI call: $monitor\n  $monitor("%d %d  %d  | %d  %d", a, b, op, s, overflow);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #0  a = 8\'b1;  b =  8\'d1;  op = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = 8\'d1;   b =  8\'d1;  op = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = 8\'d1;   b = -8\'d1;  op = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = 8\'d1;   b = -8\'d1;  op = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = -8\'d1;  b =  8\'d1;  op = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = -8\'d1;  b =  8\'d1;  op = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = -8\'d1;  b = -8\'d1;  op = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = -8\'d1;  b = -8\'d1;  op = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #50 a =  8\'d127; b =  8\'d1;  op = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #50 a =  8\'d127; b =  8\'d1;  op = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #50 a =  8\'d127; b = -8\'d1;  op = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #50 a =  8\'d127; b = -8\'d1;  op = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = -8\'d127; b =  8\'d1;  op = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = -8\'d127; b =  8\'d1;  op = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = -8\'d127; b = -8\'d1;  op = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = -8\'d127; b = -8\'d1;  op = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #50 a = -8\'d127; b = -8\'d15; op = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/adder_subtractor_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #50 $finish;\n  ^\n%Error: Exiting due to 3 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder_subtractor_tb;
reg signed [7:0] a;
reg signed [7:0] b;
reg op;
wire signed [7:0] s;
wire overflow;

initial
	begin
		$dumpfile("adder_subtractor.vcd");
		$dumpvars(0,Johnson);
		$display("  a   b op     s overflow");
		$monitor("%d %d  %d  | %d  %d", a, b, op, s, overflow);
		

		#0  a = 8'b1; 	b =  8'd1; 	op = 1'b0;
		#50 a = 8'd1;  	b =  8'd1; 	op = 1'b1;
		#50 a = 8'd1;  	b = -8'd1; 	op = 1'b0;
		#50 a = 8'd1;  	b = -8'd1; 	op = 1'b1;
		#50 a = -8'd1; 	b =  8'd1; 	op = 1'b0;
		#50 a = -8'd1; 	b =  8'd1; 	op = 1'b1;
		#50 a = -8'd1; 	b = -8'd1; 	op = 1'b0;
		#50 a = -8'd1; 	b = -8'd1; 	op = 1'b1;
		

		#50 a =  8'd127;	b =  8'd1; 	op = 1'b0;
		#50 a =  8'd127;	b =  8'd1; 	op = 1'b1;
		#50 a =  8'd127;	b = -8'd1; 	op = 1'b0;
		#50 a =  8'd127;	b = -8'd1;  op = 1'b1;
		#50 a = -8'd127;	b =  8'd1; 	op = 1'b0;
		#50 a = -8'd127;	b =  8'd1; 	op = 1'b1;
		#50 a = -8'd127;	b = -8'd1; 	op = 1'b0;
		#50 a = -8'd127;	b = -8'd1; 	op = 1'b1;
		

		#50 a = -8'd127;	b = -8'd15; op = 1'b0;
		#50 $finish;
	end

adder_subtractor Johnson(s,overflow,a,b,op);

endmodule
module adder_subtractor_tb;

reg signed [7:0] a;
reg signed [7:0] b;
reg op;
wire signed [7:0] s;
wire overflow;

initial
	begin
		$dumpfile("adder_subtractor.vcd");
		$dumpvars(0,Johnson);
		$display("  a   b op     s overflow");
		$monitor("%d %d  %d  | %d  %d", a, b, op, s, overflow);
		

		#0  a = 8'b1; 	b =  8'd1; 	op = 1'b0;
		#50 a = 8'd1;  	b =  8'd1; 	op = 1'b1;
		#50 a = 8'd1;  	b = -8'd1; 	op = 1'b0;
		#50 a = 8'd1;  	b = -8'd1; 	op = 1'b1;
		#50 a = -8'd1; 	b =  8'd1; 	op = 1'b0;
		#50 a = -8'd1; 	b =  8'd1; 	op = 1'b1;
		#50 a = -8'd1; 	b = -8'd1; 	op = 1'b0;
		#50 a = -8'd1; 	b = -8'd1; 	op = 1'b1;
		

		#50 a =  8'd127;	b =  8'd1; 	op = 1'b0;
		#50 a =  8'd127;	b =  8'd1; 	op = 1'b1;
		#50 a =  8'd127;	b = -8'd1; 	op = 1'b0;
		#50 a =  8'd127;	b = -8'd1;  op = 1'b1;
		#50 a = -8'd127;	b =  8'd1; 	op = 1'b0;
		#50 a = -8'd127;	b =  8'd1; 	op = 1'b1;
		#50 a = -8'd127;	b = -8'd1; 	op = 1'b0;
		#50 a = -8'd127;	b = -8'd1; 	op = 1'b1;
		

		#50 a = -8'd127;	b = -8'd15; op = 1'b0;
		#50 $finish;
	end

adder_subtractor Johnson(s,overflow,a,b,op);

endmodule