data/full_repos/permissive/201488448/2_circuits/2_sequential/22_countslow.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/22_countslow.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                 : ... In instance top_module\n            q <= 4'd0;\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/22_countslow.v:11: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                  : ... In instance top_module\n            q <= q + 1'b1;\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/22_countslow.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                  : ... In instance top_module\n            q <= 4'd0;\n            ^\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);

    always@(posedge clk) begin
        if(reset)
            q <= 4'd0;
        else if(slowena && q < 9)
            q <= q + 1'b1;
        else if(slowena && q == 9)
            q <= 4'd0;
    end
    
endmodule
module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);


    always@(posedge clk) begin
        if(reset)
            q <= 4'd0;
        else if(slowena && q < 9)
            q <= q + 1'b1;
        else if(slowena && q == 9)
            q <= 4'd0;
    end
    
endmodule