data/full_repos/permissive/101428364/SC_top_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:48: Unsupported: Ignoring delay on this delayed statement.\n always #50 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #100;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:147: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:152: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:163: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:175: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:186: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:197: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:208: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:218: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:231: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/101428364/SC_top_sim.v:241: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: data/full_repos/permissive/101428364/SC_top_sim.v:247: Cannot find file containing module: \'SCPU_v1\'\n    SCPU_v1 uut2(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/101428364,data/full_repos/permissive/101428364/SCPU_v1\n             data/full_repos/permissive/101428364,data/full_repos/permissive/101428364/SCPU_v1.v\n             data/full_repos/permissive/101428364,data/full_repos/permissive/101428364/SCPU_v1.sv\n             SCPU_v1\n             SCPU_v1.v\n             SCPU_v1.sv\n             obj_dir/SCPU_v1\n             obj_dir/SCPU_v1.v\n             obj_dir/SCPU_v1.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SC_top_sim();


    reg clk;			
	reg reset;
	
	reg MIO_ready;					
	reg [31:0]inst_in;
	reg [31:0]Data_in;	
	

	wire mem_w;
	wire[31:0]PC_out;
	wire[31:0]Addr_out;
	wire[31:0]Data_out;
	
	reg[5:0] OPCODE;
	reg[4:0] RS;
	reg[4:0] RT;
	reg[4:0] RD;
	reg[4:0] SHAMT;
	reg[5:0] FUNC;

	
	
	always #50 clk = ~clk;
	
	initial begin
		reset = 1;
		clk = 1;
		inst_in = 0;
		Data_in = 0;
		inst_in = 0;
		
		#100;
		reset = 0;
				

		OPCODE = 0;
		RS = 17;
		RT = 18;
		RD = 19;
		SHAMT = 0;
		FUNC = 6'b100000;
		inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
	
		
		#100;
		

		OPCODE = 0;
		RS = 18;
		RT = 19;
		RD = 19;
		SHAMT = 0;
		FUNC = 6'b100000;
		inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
		
		
		#100;
		

		OPCODE = 0;
		RS = 18;
		RT = 19;
		RD = 19;
		SHAMT = 0;
		FUNC = 6'b100100;
		inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
		
		
		#100;
		

		OPCODE = 0;
		RS = 18;
		RT = 19;
		RD = 19;
		SHAMT = 0;
		FUNC = 6'b100010;
		inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
		
		
		#100;
		

		OPCODE = 6'b100011;
		RS = 15;
		RT = 16;

		inst_in = {OPCODE, RS, RT, 16'h0004};
		Data_in = 32'hcdcdcdcd;
		
		
		#100;
		

		OPCODE = 6'b000100;
		RS = 15;
		RT = 15;

		inst_in = {OPCODE, RS, RT, 16'hFFFC};
		Data_in = 32'hcdcdcdcd;
		
		
		#100;

		
        OPCODE = 6'b000010;
        RS = 15;
        RT = 15;

        inst_in = {OPCODE, 26'h4};
        Data_in = 32'hcdcdcdcd;
		
		
        #100;
		

        OPCODE = 6'b000000;
        RS = 15;
        FUNC = 6'b001000;
        inst_in = {OPCODE, RS, 15'b0, FUNC};
        
        #50
        OPCODE = 6'b000000;
        RS = 16;
        FUNC = 6'b001000;
        inst_in = {OPCODE, RS, 15'b0, FUNC};
        #50
		

		
        OPCODE = 6'b001000;
        RS = 14;
        RT = 14;

        inst_in = {OPCODE, RS, RT, 16'h8000};
		
		
        #100;
		

		
        OPCODE = 6'b001010;
        RS = 13;
        RT = 13;

        inst_in = {OPCODE, RS, RT, 16'hd};
		#50;
		inst_in = {OPCODE, RS, RT, 16'he};
		
        #50;
        

		
        OPCODE = 6'b001100;
        RS = 12;
        RT = 12;

        inst_in = {OPCODE, RS, RT, 16'hcdc8};
		
		
        #100;
		

		
        OPCODE = 6'b001101;
        RS = 11;
        RT = 11;

        inst_in = {OPCODE, RS, RT, 16'hcdcd};
		
		
        #100;
		

		
        OPCODE = 6'b101011;
        RS = 10;
        RT = 10;

        inst_in = {OPCODE, RS, RT, 16'h0004};
		
		
        #100;
		

		
        OPCODE = 6'b001111;
        RT = 9;

        inst_in = {OPCODE, 5'b0, RT, 16'hcdcd};
		
		
        #100;
		

		
        OPCODE = 6'b000000;
        RT = 9;
		RD = 8;
		SHAMT = 3;
		FUNC = 6'b000010;

        inst_in = {OPCODE, 5'b0, RT, RD, SHAMT, FUNC};
		
		
        #100;
		

		
        OPCODE = 6'b000011;
 

        inst_in = {OPCODE, 26'hf};
		
		
        #100;

		$finish;
	
	end
    
    SCPU_v1 uut2(
		.clk(clk),		
		.reset(reset),
						
		.inst_in(inst_in),
		.Data_in(Data_in),	
		
		.mem_w(mem_w),			
		.PC_out(PC_out),		
		.Addr_out(Addr_out),	
		.Data_out(Data_out), 
.test_reg_index(), 
		.test_reg_result()		
	);
    
    
    
    

endmodule
module SC_top_sim();



    reg clk;			
	reg reset;
	
	reg MIO_ready;					
	reg [31:0]inst_in;
	reg [31:0]Data_in;	
	

	wire mem_w;
	wire[31:0]PC_out;
	wire[31:0]Addr_out;
	wire[31:0]Data_out;
	
	reg[5:0] OPCODE;
	reg[4:0] RS;
	reg[4:0] RT;
	reg[4:0] RD;
	reg[4:0] SHAMT;
	reg[5:0] FUNC;

	
	
	always #50 clk = ~clk;
	
	initial begin
		reset = 1;
		clk = 1;
		inst_in = 0;
		Data_in = 0;
		inst_in = 0;
		
		#100;
		reset = 0;
				

		OPCODE = 0;
		RS = 17;
		RT = 18;
		RD = 19;
		SHAMT = 0;
		FUNC = 6'b100000;
		inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
	
		
		#100;
		

		OPCODE = 0;
		RS = 18;
		RT = 19;
		RD = 19;
		SHAMT = 0;
		FUNC = 6'b100000;
		inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
		
		
		#100;
		

		OPCODE = 0;
		RS = 18;
		RT = 19;
		RD = 19;
		SHAMT = 0;
		FUNC = 6'b100100;
		inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
		
		
		#100;
		

		OPCODE = 0;
		RS = 18;
		RT = 19;
		RD = 19;
		SHAMT = 0;
		FUNC = 6'b100010;
		inst_in = {OPCODE, RS, RT, RD, SHAMT, FUNC};
		
		
		#100;
		

		OPCODE = 6'b100011;
		RS = 15;
		RT = 16;

		inst_in = {OPCODE, RS, RT, 16'h0004};
		Data_in = 32'hcdcdcdcd;
		
		
		#100;
		

		OPCODE = 6'b000100;
		RS = 15;
		RT = 15;

		inst_in = {OPCODE, RS, RT, 16'hFFFC};
		Data_in = 32'hcdcdcdcd;
		
		
		#100;

		
        OPCODE = 6'b000010;
        RS = 15;
        RT = 15;

        inst_in = {OPCODE, 26'h4};
        Data_in = 32'hcdcdcdcd;
		
		
        #100;
		

        OPCODE = 6'b000000;
        RS = 15;
        FUNC = 6'b001000;
        inst_in = {OPCODE, RS, 15'b0, FUNC};
        
        #50
        OPCODE = 6'b000000;
        RS = 16;
        FUNC = 6'b001000;
        inst_in = {OPCODE, RS, 15'b0, FUNC};
        #50
		

		
        OPCODE = 6'b001000;
        RS = 14;
        RT = 14;

        inst_in = {OPCODE, RS, RT, 16'h8000};
		
		
        #100;
		

		
        OPCODE = 6'b001010;
        RS = 13;
        RT = 13;

        inst_in = {OPCODE, RS, RT, 16'hd};
		#50;
		inst_in = {OPCODE, RS, RT, 16'he};
		
        #50;
        

		
        OPCODE = 6'b001100;
        RS = 12;
        RT = 12;

        inst_in = {OPCODE, RS, RT, 16'hcdc8};
		
		
        #100;
		

		
        OPCODE = 6'b001101;
        RS = 11;
        RT = 11;

        inst_in = {OPCODE, RS, RT, 16'hcdcd};
		
		
        #100;
		

		
        OPCODE = 6'b101011;
        RS = 10;
        RT = 10;

        inst_in = {OPCODE, RS, RT, 16'h0004};
		
		
        #100;
		

		
        OPCODE = 6'b001111;
        RT = 9;

        inst_in = {OPCODE, 5'b0, RT, 16'hcdcd};
		
		
        #100;
		

		
        OPCODE = 6'b000000;
        RT = 9;
		RD = 8;
		SHAMT = 3;
		FUNC = 6'b000010;

        inst_in = {OPCODE, 5'b0, RT, RD, SHAMT, FUNC};
		
		
        #100;
		

		
        OPCODE = 6'b000011;
 

        inst_in = {OPCODE, 26'hf};
		
		
        #100;

		$finish;
	
	end
    
    SCPU_v1 uut2(
		.clk(clk),		
		.reset(reset),
						
		.inst_in(inst_in),
		.Data_in(Data_in),	
		
		.mem_w(mem_w),			
		.PC_out(PC_out),		
		.Addr_out(Addr_out),	
		.Data_out(Data_out), 
.test_reg_index(), 
		.test_reg_result()		
	);
    
    
    
    

endmodule