data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/apb_demux.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/apb_demux.v:42: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module apb_demux #(
  parameter NumPorts = 2,
  parameter AddrBits = 32)
(
  input                        clk,
  input                        rst,

  input [AddrBits-1:0]         slv_paddr,
  input                        slv_psel,
  input                        slv_penable,
  output                       slv_pready,
  output [31:0]                slv_prdata,
  output                       slv_pslverr,

  output reg [NumPorts-1:0]    mst_psel,
  output reg [NumPorts-1:0]    mst_penable,
  input      [NumPorts-1:0]    mst_pready,
  input      [NumPorts*32-1:0] mst_prdata,
  input      [NumPorts-1:0]    mst_pslverr
);
`include "util.vh"

  localparam PortBits = clog2(NumPorts);


  wire [PortBits-1:0] sel = slv_paddr[AddrBits-1 -: PortBits];


  always @(*) begin
    mst_psel          = 0;
    mst_penable       = 0;
    mst_psel[sel]     = slv_psel;
    mst_penable[sel]  = slv_penable;
  end


  assign slv_prdata  = mst_prdata[sel*32 +: 32];
  assign slv_pready  = mst_pready[sel];
  assign slv_pslverr = mst_pslverr[sel];

endmodule
module apb_demux #(
  parameter NumPorts = 2,
  parameter AddrBits = 32)
(
  input                        clk,
  input                        rst,

  input [AddrBits-1:0]         slv_paddr,
  input                        slv_psel,
  input                        slv_penable,
  output                       slv_pready,
  output [31:0]                slv_prdata,
  output                       slv_pslverr,

  output reg [NumPorts-1:0]    mst_psel,
  output reg [NumPorts-1:0]    mst_penable,
  input      [NumPorts-1:0]    mst_pready,
  input      [NumPorts*32-1:0] mst_prdata,
  input      [NumPorts-1:0]    mst_pslverr
);

`include "util.vh"

  localparam PortBits = clog2(NumPorts);


  wire [PortBits-1:0] sel = slv_paddr[AddrBits-1 -: PortBits];


  always @(*) begin
    mst_psel          = 0;
    mst_penable       = 0;
    mst_psel[sel]     = slv_psel;
    mst_penable[sel]  = slv_penable;
  end


  assign slv_prdata  = mst_prdata[sel*32 +: 32];
  assign slv_pready  = mst_pready[sel];
  assign slv_pslverr = mst_pslverr[sel];

endmodule