data/full_repos/permissive/165490876/src/synth/VeriSynth.v
1: b"%Error: data/full_repos/permissive/165490876/src/synth/VeriSynth.v:45: Duplicate declaration of signal: 'amplitudeControlWord'\n reg [7:0] amplitudeControlWord; \n           ^~~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/165490876/src/synth/VeriSynth.v:44: ... Location of original declaration\n reg [7:0] amplitudeControlWord; \n           ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module VeriSynth (
  output pin_vs_led,
  output pin_vs_dout,
  input pin_vs_ss,
  input pin_vs_mosi,
  input pin_vs_sclk,
  input pin_vs_fsk,
  input pin_vs_ask,
  input pin_vs_psk
);

	wire [7:0] controlWord;
	wire [3:0] controlAddress;
	wire clk;
	wire controlReady;
	wire [11:0] amplitude;		
	wire [4:0] phase;
    reg [1:0] waveForm;
	reg [7:0] pWidth;
	reg [15:0] frequencyControlWordA;
	reg [15:0] frequencyControlWordB;	
	reg [7:0] phaseShiftControlWordA;
	reg [7:0] phaseShiftControlWordB;	
	reg [7:0] amplitudeControlWord;	
	reg [7:0] amplitudeControlWord;	
	
	OSCH #(
	.NOM_FREQ("2.08")
	) internal_oscillator_inst (
		.STDBY(1'b0),		
		.OSC(clk)
	);
		

	PDMEncoder #(
		.DATA_BITS(12)
	) pdm_encoder (
		.clock(clk),
		.amplitude(amplitude),
		.digital_out(pin_vs_dout)
	);
	

	ControlInterface #(
	    .ADDR_BITS(4),
		.DATA_BITS(8)
	) control_interface (
		.controlWord(controlWord),
		.controlAddress(controlAddress),
		.controlReady(controlReady),
		.SCLK(pin_vs_ss),
		.MOSI(pin_vs_mosi),
		.SS(pin_vs_sclk) 
	);
	
	NCO #(
		.PA_SIZE(16), 
		.PH_SIZE(5)
	) nco (		
		.frequencyControlWord(pin_vs_fsk ? frequencyControlWordA : frequencyControlWordB),		
		.phaseShiftControlWord(pin_vs_psk ? phaseShiftControlWordA : phaseShiftControlWordB),
		.clock(clk),
		.phase(phase)
	);
	
	PAC pac (
		.phase(phase),
		.waveForm(waveForm),		
		.pWidth(pWidth),
		.amplitude(pin_vs_ask ? amplitudeControlWord[7:4] : amplitudeControlWord[3:0]),
		.out(amplitude)		
	);
	



	always @(posedge controlReady) begin
		case (controlAddress)	
			0: phaseShiftControlWordA <= controlWord;
			1: phaseShiftControlWordB <= controlWord;
			2: amplitudeControlWord <= controlWord;			
			3: pWidth <= controlWord;
			4: waveForm <= controlWord[1:0];
			5: frequencyControlWordA[15:8] <= controlWord;
			6: frequencyControlWordA[7:0] <= controlWord;
			7: frequencyControlWordB[15:8] <= controlWord;
			8: frequencyControlWordB[7:0] <= controlWord;
		endcase
	end
	


	assign pin_vs_led = controlReady;
		
endmodule
module VeriSynth (
  output pin_vs_led,
  output pin_vs_dout,
  input pin_vs_ss,
  input pin_vs_mosi,
  input pin_vs_sclk,
  input pin_vs_fsk,
  input pin_vs_ask,
  input pin_vs_psk
);


	wire [7:0] controlWord;
	wire [3:0] controlAddress;
	wire clk;
	wire controlReady;
	wire [11:0] amplitude;		
	wire [4:0] phase;
    reg [1:0] waveForm;
	reg [7:0] pWidth;
	reg [15:0] frequencyControlWordA;
	reg [15:0] frequencyControlWordB;	
	reg [7:0] phaseShiftControlWordA;
	reg [7:0] phaseShiftControlWordB;	
	reg [7:0] amplitudeControlWord;	
	reg [7:0] amplitudeControlWord;	
	
	OSCH #(
	.NOM_FREQ("2.08")
	) internal_oscillator_inst (
		.STDBY(1'b0),		
		.OSC(clk)
	);
		

	PDMEncoder #(
		.DATA_BITS(12)
	) pdm_encoder (
		.clock(clk),
		.amplitude(amplitude),
		.digital_out(pin_vs_dout)
	);
	

	ControlInterface #(
	    .ADDR_BITS(4),
		.DATA_BITS(8)
	) control_interface (
		.controlWord(controlWord),
		.controlAddress(controlAddress),
		.controlReady(controlReady),
		.SCLK(pin_vs_ss),
		.MOSI(pin_vs_mosi),
		.SS(pin_vs_sclk) 
	);
	
	NCO #(
		.PA_SIZE(16), 
		.PH_SIZE(5)
	) nco (		
		.frequencyControlWord(pin_vs_fsk ? frequencyControlWordA : frequencyControlWordB),		
		.phaseShiftControlWord(pin_vs_psk ? phaseShiftControlWordA : phaseShiftControlWordB),
		.clock(clk),
		.phase(phase)
	);
	
	PAC pac (
		.phase(phase),
		.waveForm(waveForm),		
		.pWidth(pWidth),
		.amplitude(pin_vs_ask ? amplitudeControlWord[7:4] : amplitudeControlWord[3:0]),
		.out(amplitude)		
	);
	



	always @(posedge controlReady) begin
		case (controlAddress)	
			0: phaseShiftControlWordA <= controlWord;
			1: phaseShiftControlWordB <= controlWord;
			2: amplitudeControlWord <= controlWord;			
			3: pWidth <= controlWord;
			4: waveForm <= controlWord[1:0];
			5: frequencyControlWordA[15:8] <= controlWord;
			6: frequencyControlWordA[7:0] <= controlWord;
			7: frequencyControlWordB[15:8] <= controlWord;
			8: frequencyControlWordB[7:0] <= controlWord;
		endcase
	end
	


	assign pin_vs_led = controlReady;
		
endmodule