data/full_repos/permissive/151863926/src/sensor_intf.v
1: b'%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:128: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                          : ... In instance sensor_intf\n            i_fsm_cnt <= {TIMING_PARAMS_WIDTH{1\'b0}};\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:132: Operator GT expects 24 bits on the RHS, but RHS\'s REPLICATE generates 12 bits.\n                                                                          : ... In instance sensor_intf\n            if (i_fsm_cnt > {TIMING_PARAMS_WIDTH{1\'b0}}) begin\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:138: Operator EQ expects 24 bits on the RHS, but RHS\'s REPLICATE generates 12 bits.\n                                                                          : ... In instance sensor_intf\n    wire  i_fsm_cnt_zero = (i_fsm_cnt == {TIMING_PARAMS_WIDTH{1\'b0}});\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:157: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'t_pxlrst_i\' generates 12 bits.\n                                                                          : ... In instance sensor_intf\n            i_fsm_cnt_load_value     <= t_pxlrst_i;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:183: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'t_rsthold_i\' generates 12 bits.\n                                                                          : ... In instance sensor_intf\n                i_fsm_cnt_load_value <= t_rsthold_i;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:197: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'t_intprep_i\' generates 12 bits.\n                                                                          : ... In instance sensor_intf\n                i_fsm_cnt_load_value <= t_intprep_i;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:212: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'t_intprep2_i\' generates 12 bits.\n                                                                          : ... In instance sensor_intf\n                i_fsm_cnt_load_value <= t_intprep2_i;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:240: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'t_inthold_i\' generates 12 bits.\n                                                                          : ... In instance sensor_intf\n                i_fsm_cnt_load_value <= t_inthold_i;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:254: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'t_inthold2_i\' generates 12 bits.\n                                                                          : ... In instance sensor_intf\n                i_fsm_cnt_load_value <= t_inthold2_i;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:268: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'t_rdoprep_i\' generates 12 bits.\n                                                                          : ... In instance sensor_intf\n                i_fsm_cnt_load_value <= t_rdoprep_i;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:295: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'t_rdohold_i\' generates 12 bits.\n                                                                          : ... In instance sensor_intf\n                i_fsm_cnt_load_value <= t_rdohold_i;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/sensor_intf.v:309: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'t_pxlrst_i\' generates 12 bits.\n                                                                          : ... In instance sensor_intf\n                i_fsm_cnt_load_value <= t_pxlrst_i;\n                                     ^~\n%Error: Exiting due to 12 warning(s)\n'
module sensor_intf(
    clk_i,
    rst_i,

    start_i,
    autostart_i,
    ready_o,
    
    t_pxlrst_i,
    t_rsthold_i,
    t_intprep_i,
    t_intprep2_i,
    t_inthold_i, 
    t_inthold2_i,
    t_rdoprep_i,
    t_rdohold_i,
    t_roiclk_i,
    t_int_numclocks_i,
    
    sns_reset_1_o,
    sns_hold_o,
    sns_modsel_en_o,
    
    sns_start_roi_o,
    sns_enable_roi_i,
    sns_clk_roi_o,
    sns_sel_sr_o,
    
    ppi_frame_valid_i,
    
    deb_state_o,
    deb_fsm_cnt_o,
    deb_fsm_cnt_en_o
);


localparam integer TIMING_PARAMS_WIDTH = 12;


input                                  clk_i;

input                                  rst_i;


input                                  start_i;

input                                  autostart_i;

output                                 ready_o;


input      [TIMING_PARAMS_WIDTH-1:0]   t_pxlrst_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_rsthold_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_intprep_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_intprep2_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_inthold_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_inthold2_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_rdoprep_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_rdohold_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_roiclk_i;

input      [24-1:0]                    t_int_numclocks_i;


output                                 sns_reset_1_o;
output                                 sns_hold_o;
output reg                             sns_modsel_en_o = 0;


output                                 sns_start_roi_o;
input                                  sns_enable_roi_i;
output                                 sns_clk_roi_o;
output                                 sns_sel_sr_o;

input ppi_frame_valid_i;

output [3:0] deb_state_o;
output [24-1:0] deb_fsm_cnt_o;
output deb_fsm_cnt_en_o;
    












`define STATE_RESET         4'd0
`define STATE_READY         4'd1
`define STATE_RESET_DONE    4'd2
`define STATE_INT_PREPARE   4'd3
`define STATE_INT_PREPARE2  4'd4
`define STATE_INTEGRATION   4'd5
`define STATE_INT_HOLD      4'd6
`define STATE_INT_HOLD2     4'd7
`define STATE_RDO_PREPARE   4'd8
`define STATE_READOUT       4'd9
`define STATE_RDO_HOLD      4'd10


    reg [3:0] i_state;
    assign deb_state_o = i_state;
    
    reg [24-1:0] i_fsm_cnt_load_value;
    
    reg [24-1:0] i_fsm_cnt;
    assign deb_fsm_cnt_o = i_fsm_cnt;
    reg i_fsm_cnt_en;
    assign deb_fsm_cnt_en_o = i_fsm_cnt_en;

    always @(posedge clk_i) begin
        if (rst_i)
            i_fsm_cnt <= {TIMING_PARAMS_WIDTH{1'b0}};
        else if (!i_fsm_cnt_en)
            i_fsm_cnt <= i_fsm_cnt_load_value;
        else
            if (i_fsm_cnt > {TIMING_PARAMS_WIDTH{1'b0}}) begin
                i_fsm_cnt <= i_fsm_cnt - 1'b1;
            end
    end
    

    wire  i_fsm_cnt_zero = (i_fsm_cnt == {TIMING_PARAMS_WIDTH{1'b0}});
    reg i_fsm_cnt_zero_prev = 0;
    always @(posedge clk_i)
        i_fsm_cnt_zero_prev <= i_fsm_cnt_zero;
    wire i_fsm_cnt_done = i_fsm_cnt_zero && !i_fsm_cnt_zero_prev;
    
    
    wire i_rdo_done;
    reg i_sns_reset_1, i_sns_hold;
    

    assign ready_o = (i_state == `STATE_READY);

    always @(posedge clk_i) begin

    
        if (rst_i) begin
            
            i_state                  <= `STATE_RESET;
            i_fsm_cnt_load_value     <= t_pxlrst_i;
            i_fsm_cnt_en             <= 1'b0;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b0;
            
        end else if (i_state == `STATE_RESET) begin
            
            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b0;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_READY;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b0;
            end
        
        end else if (i_state == `STATE_READY) begin
            
            i_fsm_cnt_en             <= 1'b0;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b0;

            if (start_i | autostart_i) begin
                i_state              <= `STATE_RESET_DONE;
                i_fsm_cnt_load_value <= t_rsthold_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b1;
            end

        end else if (i_state == `STATE_RESET_DONE) begin
        
            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b1;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_INT_PREPARE;
                i_fsm_cnt_load_value <= t_intprep_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b0;
                i_sns_hold           <= 1'b1;
            end


        end else if (i_state == `STATE_INT_PREPARE) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b0;
            i_sns_hold               <= 1'b1;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_INT_PREPARE2;
                i_fsm_cnt_load_value <= t_intprep2_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b0;
                i_sns_hold           <= 1'b0;
            end

        end else if (i_state == `STATE_INT_PREPARE2) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b0;
            i_sns_hold               <= 1'b0;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_INTEGRATION;
                i_fsm_cnt_load_value <= t_int_numclocks_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b0;
                i_sns_hold           <= 1'b0;
            end

        end else if (i_state == `STATE_INTEGRATION) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b0;
            i_sns_hold               <= 1'b0;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_INT_HOLD;
                i_fsm_cnt_load_value <= t_inthold_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b0;
                i_sns_hold           <= 1'b0;
            end

        end else if (i_state == `STATE_INT_HOLD) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b0;
            i_sns_hold               <= 1'b0;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_INT_HOLD2;
                i_fsm_cnt_load_value <= t_inthold2_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b0;
                i_sns_hold           <= 1'b1;
            end

        end else if (i_state == `STATE_INT_HOLD2) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b0;
            i_sns_hold               <= 1'b1;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_RDO_PREPARE;
                i_fsm_cnt_load_value <= t_rdoprep_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b1;
            end

        end else if (i_state == `STATE_RDO_PREPARE) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b1;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_READOUT;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b1;
            end

        end else if (i_state == `STATE_READOUT) begin

            i_fsm_cnt_en             <= 1'b0;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b1;

            if (i_rdo_done) begin
                i_state              <= `STATE_RDO_HOLD;
                i_fsm_cnt_load_value <= t_rdohold_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b1;
            end

        end else if (i_state == `STATE_RDO_HOLD) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b1;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_RESET;
                i_fsm_cnt_load_value <= t_pxlrst_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b0;
            end

        end
    end
    
    assign sns_reset_1_o = i_sns_reset_1;
    assign sns_hold_o    = i_sns_hold;
    


    
    always @(posedge clk_i) begin
        sns_modsel_en_o <= (i_state == `STATE_INTEGRATION);
    end
    


    reg  [TIMING_PARAMS_WIDTH-1:0] i_roi_clk_fdcntr;
    reg  i_roi_clk;
    wire i_roi_clk_t, i_roi_clk_re, i_roi_clk_fe;
    
    always @(posedge clk_i) begin
        if (rst_i || i_roi_clk_t)
            i_roi_clk_fdcntr <= t_roiclk_i-1;
        else
            i_roi_clk_fdcntr <= i_roi_clk_fdcntr - 1'b1;
        
        if (rst_i)
            i_roi_clk <= 1'b0;
        else if (i_roi_clk_t)
            i_roi_clk <= !i_roi_clk;
    end
    assign i_roi_clk_t = (i_roi_clk_fdcntr == {TIMING_PARAMS_WIDTH{1'b0}});
    assign i_roi_clk_fe = (i_roi_clk_t && i_roi_clk);
    assign i_roi_clk_re = (i_roi_clk_t && !i_roi_clk);
    
    reg  i_roi_start, i_roi_cycle;
    reg  [1:0] i_roi_enable;
    wire i_rdo_start;

    assign i_rdo_start = (i_state == `STATE_READOUT && i_roi_clk_fe && !i_roi_cycle);
    
    wire composite_frame_valid = sns_enable_roi_i | ppi_frame_valid_i;

    always @(posedge clk_i) begin

        if (i_state != `STATE_READOUT)
            i_roi_cycle <= 1'b0;
        else if (i_roi_clk_fe && !i_roi_cycle)
            i_roi_cycle <= 1'b1;
            
        if (rst_i || (i_roi_start && i_roi_clk_fe))
            i_roi_start <= 1'b0;
        else if (i_rdo_start)
            i_roi_start <= 1'b1;
        
        if (i_roi_clk_re)
            i_roi_enable[1:0] <= {i_roi_enable[0], composite_frame_valid};
    end
    
    assign i_rdo_done = ((i_state == `STATE_READOUT) && (i_roi_enable == 2'b10));
    
    assign sns_start_roi_o = i_roi_start;
    assign sns_clk_roi_o = i_roi_clk;
    assign sns_sel_sr_o = 1'b0;
    

endmodule
module sensor_intf(
    clk_i,
    rst_i,

    start_i,
    autostart_i,
    ready_o,
    
    t_pxlrst_i,
    t_rsthold_i,
    t_intprep_i,
    t_intprep2_i,
    t_inthold_i, 
    t_inthold2_i,
    t_rdoprep_i,
    t_rdohold_i,
    t_roiclk_i,
    t_int_numclocks_i,
    
    sns_reset_1_o,
    sns_hold_o,
    sns_modsel_en_o,
    
    sns_start_roi_o,
    sns_enable_roi_i,
    sns_clk_roi_o,
    sns_sel_sr_o,
    
    ppi_frame_valid_i,
    
    deb_state_o,
    deb_fsm_cnt_o,
    deb_fsm_cnt_en_o
);



localparam integer TIMING_PARAMS_WIDTH = 12;


input                                  clk_i;

input                                  rst_i;


input                                  start_i;

input                                  autostart_i;

output                                 ready_o;


input      [TIMING_PARAMS_WIDTH-1:0]   t_pxlrst_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_rsthold_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_intprep_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_intprep2_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_inthold_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_inthold2_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_rdoprep_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_rdohold_i;

input      [TIMING_PARAMS_WIDTH-1:0]   t_roiclk_i;

input      [24-1:0]                    t_int_numclocks_i;


output                                 sns_reset_1_o;
output                                 sns_hold_o;
output reg                             sns_modsel_en_o = 0;


output                                 sns_start_roi_o;
input                                  sns_enable_roi_i;
output                                 sns_clk_roi_o;
output                                 sns_sel_sr_o;

input ppi_frame_valid_i;

output [3:0] deb_state_o;
output [24-1:0] deb_fsm_cnt_o;
output deb_fsm_cnt_en_o;
    












`define STATE_RESET         4'd0
`define STATE_READY         4'd1
`define STATE_RESET_DONE    4'd2
`define STATE_INT_PREPARE   4'd3
`define STATE_INT_PREPARE2  4'd4
`define STATE_INTEGRATION   4'd5
`define STATE_INT_HOLD      4'd6
`define STATE_INT_HOLD2     4'd7
`define STATE_RDO_PREPARE   4'd8
`define STATE_READOUT       4'd9
`define STATE_RDO_HOLD      4'd10


    reg [3:0] i_state;
    assign deb_state_o = i_state;
    
    reg [24-1:0] i_fsm_cnt_load_value;
    
    reg [24-1:0] i_fsm_cnt;
    assign deb_fsm_cnt_o = i_fsm_cnt;
    reg i_fsm_cnt_en;
    assign deb_fsm_cnt_en_o = i_fsm_cnt_en;

    always @(posedge clk_i) begin
        if (rst_i)
            i_fsm_cnt <= {TIMING_PARAMS_WIDTH{1'b0}};
        else if (!i_fsm_cnt_en)
            i_fsm_cnt <= i_fsm_cnt_load_value;
        else
            if (i_fsm_cnt > {TIMING_PARAMS_WIDTH{1'b0}}) begin
                i_fsm_cnt <= i_fsm_cnt - 1'b1;
            end
    end
    

    wire  i_fsm_cnt_zero = (i_fsm_cnt == {TIMING_PARAMS_WIDTH{1'b0}});
    reg i_fsm_cnt_zero_prev = 0;
    always @(posedge clk_i)
        i_fsm_cnt_zero_prev <= i_fsm_cnt_zero;
    wire i_fsm_cnt_done = i_fsm_cnt_zero && !i_fsm_cnt_zero_prev;
    
    
    wire i_rdo_done;
    reg i_sns_reset_1, i_sns_hold;
    

    assign ready_o = (i_state == `STATE_READY);

    always @(posedge clk_i) begin

    
        if (rst_i) begin
            
            i_state                  <= `STATE_RESET;
            i_fsm_cnt_load_value     <= t_pxlrst_i;
            i_fsm_cnt_en             <= 1'b0;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b0;
            
        end else if (i_state == `STATE_RESET) begin
            
            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b0;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_READY;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b0;
            end
        
        end else if (i_state == `STATE_READY) begin
            
            i_fsm_cnt_en             <= 1'b0;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b0;

            if (start_i | autostart_i) begin
                i_state              <= `STATE_RESET_DONE;
                i_fsm_cnt_load_value <= t_rsthold_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b1;
            end

        end else if (i_state == `STATE_RESET_DONE) begin
        
            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b1;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_INT_PREPARE;
                i_fsm_cnt_load_value <= t_intprep_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b0;
                i_sns_hold           <= 1'b1;
            end


        end else if (i_state == `STATE_INT_PREPARE) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b0;
            i_sns_hold               <= 1'b1;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_INT_PREPARE2;
                i_fsm_cnt_load_value <= t_intprep2_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b0;
                i_sns_hold           <= 1'b0;
            end

        end else if (i_state == `STATE_INT_PREPARE2) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b0;
            i_sns_hold               <= 1'b0;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_INTEGRATION;
                i_fsm_cnt_load_value <= t_int_numclocks_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b0;
                i_sns_hold           <= 1'b0;
            end

        end else if (i_state == `STATE_INTEGRATION) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b0;
            i_sns_hold               <= 1'b0;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_INT_HOLD;
                i_fsm_cnt_load_value <= t_inthold_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b0;
                i_sns_hold           <= 1'b0;
            end

        end else if (i_state == `STATE_INT_HOLD) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b0;
            i_sns_hold               <= 1'b0;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_INT_HOLD2;
                i_fsm_cnt_load_value <= t_inthold2_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b0;
                i_sns_hold           <= 1'b1;
            end

        end else if (i_state == `STATE_INT_HOLD2) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b0;
            i_sns_hold               <= 1'b1;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_RDO_PREPARE;
                i_fsm_cnt_load_value <= t_rdoprep_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b1;
            end

        end else if (i_state == `STATE_RDO_PREPARE) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b1;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_READOUT;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b1;
            end

        end else if (i_state == `STATE_READOUT) begin

            i_fsm_cnt_en             <= 1'b0;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b1;

            if (i_rdo_done) begin
                i_state              <= `STATE_RDO_HOLD;
                i_fsm_cnt_load_value <= t_rdohold_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b1;
            end

        end else if (i_state == `STATE_RDO_HOLD) begin

            i_fsm_cnt_en             <= 1'b1;
            i_sns_reset_1            <= 1'b1;
            i_sns_hold               <= 1'b1;

            if (i_fsm_cnt_done) begin
                i_state              <= `STATE_RESET;
                i_fsm_cnt_load_value <= t_pxlrst_i;
                i_fsm_cnt_en         <= 1'b0;
                i_sns_reset_1        <= 1'b1;
                i_sns_hold           <= 1'b0;
            end

        end
    end
    
    assign sns_reset_1_o = i_sns_reset_1;
    assign sns_hold_o    = i_sns_hold;
    


    
    always @(posedge clk_i) begin
        sns_modsel_en_o <= (i_state == `STATE_INTEGRATION);
    end
    


    reg  [TIMING_PARAMS_WIDTH-1:0] i_roi_clk_fdcntr;
    reg  i_roi_clk;
    wire i_roi_clk_t, i_roi_clk_re, i_roi_clk_fe;
    
    always @(posedge clk_i) begin
        if (rst_i || i_roi_clk_t)
            i_roi_clk_fdcntr <= t_roiclk_i-1;
        else
            i_roi_clk_fdcntr <= i_roi_clk_fdcntr - 1'b1;
        
        if (rst_i)
            i_roi_clk <= 1'b0;
        else if (i_roi_clk_t)
            i_roi_clk <= !i_roi_clk;
    end
    assign i_roi_clk_t = (i_roi_clk_fdcntr == {TIMING_PARAMS_WIDTH{1'b0}});
    assign i_roi_clk_fe = (i_roi_clk_t && i_roi_clk);
    assign i_roi_clk_re = (i_roi_clk_t && !i_roi_clk);
    
    reg  i_roi_start, i_roi_cycle;
    reg  [1:0] i_roi_enable;
    wire i_rdo_start;

    assign i_rdo_start = (i_state == `STATE_READOUT && i_roi_clk_fe && !i_roi_cycle);
    
    wire composite_frame_valid = sns_enable_roi_i | ppi_frame_valid_i;

    always @(posedge clk_i) begin

        if (i_state != `STATE_READOUT)
            i_roi_cycle <= 1'b0;
        else if (i_roi_clk_fe && !i_roi_cycle)
            i_roi_cycle <= 1'b1;
            
        if (rst_i || (i_roi_start && i_roi_clk_fe))
            i_roi_start <= 1'b0;
        else if (i_rdo_start)
            i_roi_start <= 1'b1;
        
        if (i_roi_clk_re)
            i_roi_enable[1:0] <= {i_roi_enable[0], composite_frame_valid};
    end
    
    assign i_rdo_done = ((i_state == `STATE_READOUT) && (i_roi_enable == 2'b10));
    
    assign sns_start_roi_o = i_roi_start;
    assign sns_clk_roi_o = i_roi_clk;
    assign sns_sel_sr_o = 1'b0;
    

endmodule