data/full_repos/permissive/160895047/Sign_Extend.v
data/verilator_xmls/477b7902-2a49-41f3-a213-8e06eff3adef.xml
module Sign_Extend(
	v,
	sv
);
input [15:0] v;
output [31:0] sv;

wire [15:0] v;
wire [31:0] sv;

assign sv[31:16] = {16{v[15]}};
assign sv[15:0] = v;
endmodule
module Sign_Extend(
	v,
	sv
);

input [15:0] v;
output [31:0] sv;

wire [15:0] v;
wire [31:0] sv;

assign sv[31:16] = {16{v[15]}};
assign sv[15:0] = v;
endmodule