data/full_repos/permissive/125592111/verilog/Control.v
data/verilator_xmls/a12e0fd4-a754-4243-9b9f-c6d5a97d3d12.xml
module Control(opcode, ALUSrc, RegDst, MemWrite, MemRead, Beq, Jump, MemToReg, RegWrite, ALUOp);
	input [5:0] opcode;
	output reg ALUSrc, MemWrite, MemRead, Beq, Jump, RegWrite;
	output reg [1:0] RegDst, MemToReg;
	output reg [2:0] ALUOp;

	always @(*) begin
		case (opcode)

			6'b000000: begin
				ALUSrc <= 0;
				RegDst <= 1;
				MemWrite <= 0;
				MemRead <= 0;
				Beq <= 0;
				Jump <= 0;
				MemToReg <= 0;
				RegWrite <= 1;
				ALUOp <= 4;
			end


			6'b100011: begin
				ALUSrc <= 1;
				RegDst <= 0;
				MemWrite <= 0;
				MemRead <= 1;
				Beq <= 0;
				Jump <= 0;
				MemToReg <= 1;
				RegWrite <= 1;
				ALUOp <= 0; 
			end


			6'b101011: begin
				ALUSrc <= 1;
				MemWrite <= 1;
				MemRead <= 0;
				Beq <= 0;
				Jump <= 0;
				RegWrite <= 0;
				ALUOp <= 0;
			end


			6'b000100: begin
			    ALUSrc <= 1;
			    MemWrite <= 0;
			    MemRead <= 0;
			    Beq <= 1;
			    Jump <= 0;
			    RegWrite <= 0;
			    ALUOp <= 1; 
			end


			6'b000010: begin
				RegDst <= 0;
				MemToReg <= 0;
			    MemWrite <= 0;
			    MemRead <= 0;
			    Beq <= 0;
			    Jump <= 1;
			    RegWrite <= 0;
			end
			

			6'b00011: begin
				RegDst <= 2;
				MemToReg <= 2;
			    MemWrite <= 0;
			    MemRead <= 0;
			    Beq <= 0;
			    Jump <= 1;
			    RegWrite <= 0;
			end

			6'b01000: begin
			    ALUSrc <= 1;
			    RegDst <= 0;
			    MemWrite <= 0;
			    MemRead <= 0;
			    Beq <= 0;
			    Jump <= 0;
			    MemToReg <= 0;
			    RegWrite <= 1;
			    ALUOp <= 2;
			end
			

			6'b01001: begin
			    ALUSrc <= 1;
			    RegDst <= 0;
			    MemWrite <= 0;
			    MemRead <= 0;
			    Beq <= 0;
			    Jump <= 0;
			    MemToReg <= 0;
			    RegWrite <= 1;
			    ALUOp <= 3;
			end
			
		endcase
		
	end
endmodule
module Control(opcode, ALUSrc, RegDst, MemWrite, MemRead, Beq, Jump, MemToReg, RegWrite, ALUOp);

	input [5:0] opcode;
	output reg ALUSrc, MemWrite, MemRead, Beq, Jump, RegWrite;
	output reg [1:0] RegDst, MemToReg;
	output reg [2:0] ALUOp;

	always @(*) begin
		case (opcode)

			6'b000000: begin
				ALUSrc <= 0;
				RegDst <= 1;
				MemWrite <= 0;
				MemRead <= 0;
				Beq <= 0;
				Jump <= 0;
				MemToReg <= 0;
				RegWrite <= 1;
				ALUOp <= 4;
			end


			6'b100011: begin
				ALUSrc <= 1;
				RegDst <= 0;
				MemWrite <= 0;
				MemRead <= 1;
				Beq <= 0;
				Jump <= 0;
				MemToReg <= 1;
				RegWrite <= 1;
				ALUOp <= 0; 
			end


			6'b101011: begin
				ALUSrc <= 1;
				MemWrite <= 1;
				MemRead <= 0;
				Beq <= 0;
				Jump <= 0;
				RegWrite <= 0;
				ALUOp <= 0;
			end


			6'b000100: begin
			    ALUSrc <= 1;
			    MemWrite <= 0;
			    MemRead <= 0;
			    Beq <= 1;
			    Jump <= 0;
			    RegWrite <= 0;
			    ALUOp <= 1; 
			end


			6'b000010: begin
				RegDst <= 0;
				MemToReg <= 0;
			    MemWrite <= 0;
			    MemRead <= 0;
			    Beq <= 0;
			    Jump <= 1;
			    RegWrite <= 0;
			end
			

			6'b00011: begin
				RegDst <= 2;
				MemToReg <= 2;
			    MemWrite <= 0;
			    MemRead <= 0;
			    Beq <= 0;
			    Jump <= 1;
			    RegWrite <= 0;
			end

			6'b01000: begin
			    ALUSrc <= 1;
			    RegDst <= 0;
			    MemWrite <= 0;
			    MemRead <= 0;
			    Beq <= 0;
			    Jump <= 0;
			    MemToReg <= 0;
			    RegWrite <= 1;
			    ALUOp <= 2;
			end
			

			6'b01001: begin
			    ALUSrc <= 1;
			    RegDst <= 0;
			    MemWrite <= 0;
			    MemRead <= 0;
			    Beq <= 0;
			    Jump <= 0;
			    MemToReg <= 0;
			    RegWrite <= 1;
			    ALUOp <= 3;
			end
			
		endcase
		
	end
endmodule