data/full_repos/permissive/120845848/001-counter/tb/counter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/120845848/001-counter/tb/counter_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n always #(10/2) clk_t = ~clk_t;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120845848/001-counter/tb/counter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #(10*20);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120845848/001-counter/tb/counter_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #(10*10);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120845848/001-counter/tb/counter_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #(10*200);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120845848/001-counter/tb/counter_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #(10*50);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120845848/001-counter/tb/counter_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #(10*50);\n  ^\n%Error: data/full_repos/permissive/120845848/001-counter/tb/counter_tb.v:11: Cannot find file containing module: \'counter\'\n counter counter_t0(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120845848/001-counter/tb,data/full_repos/permissive/120845848/counter\n             data/full_repos/permissive/120845848/001-counter/tb,data/full_repos/permissive/120845848/counter.v\n             data/full_repos/permissive/120845848/001-counter/tb,data/full_repos/permissive/120845848/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb();

	reg clk_t;
	reg en_t;
	reg nclr_t;
	wire [3:0]counterv_t;
	
	counter counter_t0(
		.clk(clk_t),
		.en(en_t),
		.nclr(nclr_t),
		.countv(counterv_t)
	);

	initial clk_t = 1;
	always #(`clk_period/2) clk_t = ~clk_t;
	
	initial begin
		en_t = 0;
		nclr_t = 1;
		#(`clk_period*20);
		nclr_t = 0;
		#(`clk_period*10);
		nclr_t = 1;
		en_t = 1;
		#(`clk_period*200);
		en_t = 0;
		#(`clk_period*50);
		nclr_t = 0;
		#(`clk_period*50);
		nclr_t = 1;
		$stop;
	end

endmodule
module counter_tb();


	reg clk_t;
	reg en_t;
	reg nclr_t;
	wire [3:0]counterv_t;
	
	counter counter_t0(
		.clk(clk_t),
		.en(en_t),
		.nclr(nclr_t),
		.countv(counterv_t)
	);

	initial clk_t = 1;
	always #(`clk_period/2) clk_t = ~clk_t;
	
	initial begin
		en_t = 0;
		nclr_t = 1;
		#(`clk_period*20);
		nclr_t = 0;
		#(`clk_period*10);
		nclr_t = 1;
		en_t = 1;
		#(`clk_period*200);
		en_t = 0;
		#(`clk_period*50);
		nclr_t = 0;
		#(`clk_period*50);
		nclr_t = 1;
		$stop;
	end

endmodule