data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n     #(1.01*PERIOD) reset = 1\'b0;        \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #(2*PERIOD);                        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n            #2                              \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD-2);                    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #189 we = 1\'b1;                     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #1;                                 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n            #1                              \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n            #2;                             \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD-3);                    \n            ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:48: Cannot find file containing module: \'register_file\'\n    register_file DUT (\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/register_file\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/register_file.v\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/register_file.sv\n             register_file\n             register_file.v\n             register_file.sv\n             obj_dir/register_file\n             obj_dir/register_file.v\n             obj_dir/register_file.sv\n%Warning-WIDTH: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:91: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                  : ... In instance register_file_tb\n            add1 = i;                       \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:92: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                                  : ... In instance register_file_tb\n            add2 = i + 1;                   \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:119: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                   : ... In instance register_file_tb\n            add1 = i;                       \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:120: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                                   : ... In instance register_file_tb\n            add2 = i - 1;                   \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:121: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                   : ... In instance register_file_tb\n            din1 = i;                       \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/134057391/2018_cpu/code/testbench/register_file_tb.v:126: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'dout2\' generates 8 bits.\n                                                                                                   : ... In instance register_file_tb\n            if (dout2 == (i - 1))\n                      ^~\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_file_tb;

    parameter PERIOD = 10;
    parameter PC_WIDTH = 4;
    parameter REG_COUNT = 32;
    
    integer             i;
    reg                 ok;
    
    reg                 clk;
    reg                 reset;
    reg                 we;
    reg  [4:0]          add1,
                        add2;
    reg  [7:0]          din1;
    wire [7:0]          dout1,
                        dout2;


    register_file DUT (
        .clk(clk),
        .reset(reset),
        .we(we),
        .add1(add1),
        .add2(add2),
        .din1(din1),
        .dout1(dout1),
        .dout2(dout2)
    );


    always begin
        #(PERIOD/2) clk = ~clk;
    end


	initial begin
        clk = 1'b1;
	    reset = 1'b1;
	    #(1.01*PERIOD) reset = 1'b0;
	end


    initial begin
        ok = 1'bx;
        we = 1'b0;
        add1 = 0;
        add2 = 0;
        din1 = 0;
        $display($time, " << Starting simulation >>");
    end
    





    initial begin
        #(2*PERIOD);


        for (i = 0; i < REG_COUNT; i = i + 2) begin
            add1 = i;
            add2 = i + 1;
            
            #2
            if ((dout1 == 8'd0) && (dout2 == 8'd0))
                ok = 1'b1;
            else begin
                ok = 1'bx;
                $display($time, " *** ERROR - Non-zero value found *** - i %d dout1 %b dout2 %b ", i, dout1, dout2);
            end
            
            #(PERIOD-2);
        end
     end
     





     initial begin
        #189 we = 1'b1;
        #1;



        for (i = 1; i < REG_COUNT; i = i + 1) begin
            #1
            add1 = i;
            add2 = i - 1;
            din1 = i;
            
            #2;
            

            if (dout2 == (i - 1))
                ok = 1'b1;
            else begin
                ok = 1'bx;
                $display($time, " *** ERROR - Screwy data write *** - i %d dout2 %b ", i, dout2);
            end
            
            #(PERIOD-3);
        end

        we = 1'b0;
        
    end
    
endmodule
module register_file_tb;


    parameter PERIOD = 10;
    parameter PC_WIDTH = 4;
    parameter REG_COUNT = 32;
    
    integer             i;
    reg                 ok;
    
    reg                 clk;
    reg                 reset;
    reg                 we;
    reg  [4:0]          add1,
                        add2;
    reg  [7:0]          din1;
    wire [7:0]          dout1,
                        dout2;


    register_file DUT (
        .clk(clk),
        .reset(reset),
        .we(we),
        .add1(add1),
        .add2(add2),
        .din1(din1),
        .dout1(dout1),
        .dout2(dout2)
    );


    always begin
        #(PERIOD/2) clk = ~clk;
    end


	initial begin
        clk = 1'b1;
	    reset = 1'b1;
	    #(1.01*PERIOD) reset = 1'b0;
	end


    initial begin
        ok = 1'bx;
        we = 1'b0;
        add1 = 0;
        add2 = 0;
        din1 = 0;
        $display($time, " << Starting simulation >>");
    end
    





    initial begin
        #(2*PERIOD);


        for (i = 0; i < REG_COUNT; i = i + 2) begin
            add1 = i;
            add2 = i + 1;
            
            #2
            if ((dout1 == 8'd0) && (dout2 == 8'd0))
                ok = 1'b1;
            else begin
                ok = 1'bx;
                $display($time, " *** ERROR - Non-zero value found *** - i %d dout1 %b dout2 %b ", i, dout1, dout2);
            end
            
            #(PERIOD-2);
        end
     end
     





     initial begin
        #189 we = 1'b1;
        #1;



        for (i = 1; i < REG_COUNT; i = i + 1) begin
            #1
            add1 = i;
            add2 = i - 1;
            din1 = i;
            
            #2;
            

            if (dout2 == (i - 1))
                ok = 1'b1;
            else begin
                ok = 1'bx;
                $display($time, " *** ERROR - Screwy data write *** - i %d dout2 %b ", i, dout2);
            end
            
            #(PERIOD-3);
        end

        we = 1'b0;
        
    end
    
endmodule