data/full_repos/permissive/139476920/rtl/muxcpld.v
data/verilator_xmls/742acb0b-8f59-4035-a752-8435389f7b73.xml
module muxcpld (
	input RAM_MUX,
	input CLKCPU,
	input [19:3] A,
	output [9:2] RAM_A,
	input  JMP,
	output [2:0] IPL
);

assign RAM_A = RAM_MUX ? {A[19:12]} : {A[11:4]};

assign IPL = 3'bzzz;

endmodule
module muxcpld (
	input RAM_MUX,
	input CLKCPU,
	input [19:3] A,
	output [9:2] RAM_A,
	input  JMP,
	output [2:0] IPL
);


assign RAM_A = RAM_MUX ? {A[19:12]} : {A[11:4]};

assign IPL = 3'bzzz;

endmodule