data/full_repos/permissive/143278/ivltests/scope2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/scope2.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q !== 1\'b0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire q = 0;
   wire sig;
   test inst(sig);

   initial begin
      #1 if (q !== 1'b0) begin
	 $display("FAILED -- main.q == %b", q);
	 $finish;
      end

      if (sig !== 1'b1) begin
	 $display("FAILED -- main.test.q == %b", sig);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   wire q = 0;
   wire sig;
   test inst(sig);

   initial begin
      #1 if (q !== 1'b0) begin
	 $display("FAILED -- main.q == %b", q);
	 $finish;
      end

      if (sig !== 1'b1) begin
	 $display("FAILED -- main.test.q == %b", sig);
	 $finish;
      end

      $display("PASSED");
   end

endmodule