data/full_repos/permissive/143278/ivltests/signed6.v
 line:31: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/signed6.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #1  \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-UNSIGNED: data/full_repos/permissive/143278/ivltests/signed6.v:48: Comparison is constant due to unsigned arithmetic\n                                                                          : ... In instance main\n      if (val_w < 0) begin\n                ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg signed [7:0] val_rs = -5;
   wire [7:0] val_w = val_rs + 1;
   wire       signed [7:0] val_ws = val_rs + 1;

   initial begin
      #1
	$display("val_w=%d, val_ws=%d", val_w, val_ws);

      if (val_w !== 8'd252) begin
	 $display("FAILED -- val_w is wrong: %b", val_w);
	 $finish;
      end

      if (val_ws !== -8'sd4) begin
	 $display("FAILED == val_ws is wrong: %b", val_ws);
	 $finish;
      end

      if (val_ws > 0) begin
	 $display("FAILED -- signed test of val_ws failed");
	 $finish;
      end

      if (val_w < 0) begin
	 $display("FAILED -- signed test of val_w failed");
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;


   reg signed [7:0] val_rs = -5;
   wire [7:0] val_w = val_rs + 1;
   wire       signed [7:0] val_ws = val_rs + 1;

   initial begin
      #1
	$display("val_w=%d, val_ws=%d", val_w, val_ws);

      if (val_w !== 8'd252) begin
	 $display("FAILED -- val_w is wrong: %b", val_w);
	 $finish;
      end

      if (val_ws !== -8'sd4) begin
	 $display("FAILED == val_ws is wrong: %b", val_ws);
	 $finish;
      end

      if (val_ws > 0) begin
	 $display("FAILED -- signed test of val_ws failed");
	 $finish;
      end

      if (val_w < 0) begin
	 $display("FAILED -- signed test of val_w failed");
	 $finish;
      end

      $display("PASSED");
   end
endmodule