data/full_repos/permissive/116266634/ALU_testbench.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0001; shamt = 5\'b00000; #20;\n                                   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0010; shamt = 5\'b00000; #20;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0011; shamt = 5\'b00000; #20;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0100; shamt = 5\'b00000; #20;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0101; shamt = 5\'b00010; #20;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0110; shamt = 5\'b00011; #20;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b0111; shamt = 5\'b00011; #20;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b1000; shamt = 5\'b00011; #20;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b1001; shamt = 5\'b00011; #20;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b1010; shamt = 5\'b00011; #20;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b1001; shamt = 5\'b00011; #20;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/ALU_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\nALUOp = 4\'b1010; shamt = 5\'b00011; #20;\n                                   ^\n%Error: data/full_repos/permissive/116266634/ALU_testbench.v:56: Unsupported or unknown PLI call: $monitor\n $monitor("time = %2d\\nALUOp = %4b\\nshamt = %5b\\ndata1 =  %32b\\ndata2 =  %32b\\nresult = %32b\\nzero = %1b\\n\\n",\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_testbench();



reg [31:0] data1, data2;
reg [3:0] ALUOp;
reg [4:0] shamt;
wire [31:0] result;
wire zero;

ALU opeartionresult(data1, data2, ALUOp, shamt, result, zero);



initial begin

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0001; shamt = 5'b00000; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0010; shamt = 5'b00000; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0011; shamt = 5'b00000; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0100; shamt = 5'b00000; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0101; shamt = 5'b00010; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0110; shamt = 5'b00011; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0111; shamt = 5'b00011; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1000; shamt = 5'b00011; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1001; shamt = 5'b00011; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1010; shamt = 5'b00011; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b10000001010101010101111111001101;
ALUOp = 4'b1001; shamt = 5'b00011; #20;

data1 = 32'b00000000000000111111111111110000; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1010; shamt = 5'b00011; #20;

end

initial begin
	$monitor("time = %2d\nALUOp = %4b\nshamt = %5b\ndata1 =  %32b\ndata2 =  %32b\nresult = %32b\nzero = %1b\n\n",
				$time, ALUOp, shamt, data1, data2, result, zero);
end


endmodule
module ALU_testbench();




reg [31:0] data1, data2;
reg [3:0] ALUOp;
reg [4:0] shamt;
wire [31:0] result;
wire zero;

ALU opeartionresult(data1, data2, ALUOp, shamt, result, zero);



initial begin

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0001; shamt = 5'b00000; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0010; shamt = 5'b00000; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0011; shamt = 5'b00000; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0100; shamt = 5'b00000; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0101; shamt = 5'b00010; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0110; shamt = 5'b00011; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b0111; shamt = 5'b00011; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1000; shamt = 5'b00011; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1001; shamt = 5'b00011; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1010; shamt = 5'b00011; #20;

data1 = 32'b10000001010101010101111111001101; data2 = 32'b10000001010101010101111111001101;
ALUOp = 4'b1001; shamt = 5'b00011; #20;

data1 = 32'b00000000000000111111111111110000; data2 = 32'b00000000000000111111111111110000;
ALUOp = 4'b1010; shamt = 5'b00011; #20;

end

initial begin
	$monitor("time = %2d\nALUOp = %4b\nshamt = %5b\ndata1 =  %32b\ndata2 =  %32b\nresult = %32b\nzero = %1b\n\n",
				$time, ALUOp, shamt, data1, data2, result, zero);
end


endmodule