data/full_repos/permissive/140357212/Tomasulo/multi_divi.v
data/verilator_xmls/a23c4163-2e46-431d-beab-4d455ef12d1b.xml
module CountMul(clk,RUN,reset,q);
	input clk,reset,RUN;
	output reg [4:0]q;
	initial
		q = 0;
		
	always@(posedge clk) begin
		if(q == 4 || reset)
			q = 0;
		else if(RUN)
			q = q + 1;
	end
endmodule
module CountMul(clk,RUN,reset,q);

	input clk,reset,RUN;
	output reg [4:0]q;
	initial
		q = 0;
		
	always@(posedge clk) begin
		if(q == 4 || reset)
			q = 0;
		else if(RUN)
			q = q + 1;
	end
endmodule