data/full_repos/permissive/19572582/Lab3/lab3_part2.v
1: b"%Error: data/full_repos/permissive/19572582/Lab3/lab3_part2.v:23: syntax error, unexpected '(', expecting IDENTIFIER\nDflop(SW[1],SW[0],LEDR[0]);\n      ^~\n%Error: Exiting due to 1 error(s)\n"
module Dflop (Clk, D, Q);
  input Clk, D;
  output Q;

  wire R_g, S_g, Qa, Qb;
  


assign S_g = ((~D & ~Clk) | (~D & Clk) | (D & ~Clk));



assign R_g = ((~D & ~Clk) | (D & ~Clk) | (D & Clk));

assign Qa = (R_g & ~Qb);
assign Qb = (S_g & ~Qa);

assign Q = Qa;

endmodule
module Dflop (Clk, D, Q);

  input Clk, D;
  output Q;

  wire R_g, S_g, Qa, Qb;
  


assign S_g = ((~D & ~Clk) | (~D & Clk) | (D & ~Clk));



assign R_g = ((~D & ~Clk) | (D & ~Clk) | (D & Clk));

assign Qa = (R_g & ~Qb);
assign Qb = (S_g & ~Qa);

assign Q = Qa;

endmodule