data/full_repos/permissive/194847941/demo_v_5_6/11_SparkRoad/FPGA/sparkroad/src/rtl/flash/flash_fast_read.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/194847941/demo_v_5_6/11_SparkRoad/FPGA/sparkroad/src/rtl/flash/flash_fast_read.v:161: Operator EQ expects 29 bits on the RHS, but RHS\'s CONST \'28\'h8000028\' generates 28 bits.\n                                                                                                                               : ... In instance flash_fast_read\n    else if(cycle_cnt == 28\'h800_0028)\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module flash_fast_read
(
    input   wire        clk,


    output  reg         fls_sck,
    output  reg         fls_ncs,
    output  reg         fls_sdo,
    input   wire        fls_sdi,


    input   wire        start,
    output  reg         dout_en,
    output  reg [23:0]  addr,
    output  reg [7:0]   dout,

    output  reg         busy
);

reg [31:0] cnt;
reg [28:0] cycle_cnt; 
reg [2:0] phase_cnt;
reg [31:0] tx_reg;
reg [7:0] rx_reg;
reg sft_wen;
reg sft_ren;
reg byte_flag;

initial
begin
    cnt = 0;
    tx_reg = 0;
    rx_reg = 0;
    busy = 0;
end


always@(posedge clk)
begin
    if(busy)
        cnt <= cnt + 1;
    else
        cnt <= 0;
end


always@(posedge clk)
begin
    cycle_cnt <= cnt[31:3];
end


always@(posedge clk)
begin
    phase_cnt <= cnt[2:0];
end


always@(posedge clk)
begin
    fls_sck <= cnt[2];
end


always@(posedge clk)
begin
    if(busy)
        fls_ncs <= 0;
    else
        fls_ncs <= 1;
end


always@(posedge clk)
begin
    if(start)
        tx_reg <= {8'h0b,8'h00,8'h00,8'h00};
    else if(sft_wen)
        tx_reg <= {tx_reg[30:0],1'b0};
end


always@(posedge clk)
begin
    sft_wen <= (phase_cnt == 6);
end


always@(posedge clk)
begin
    sft_ren <= (phase_cnt == 3) && (cycle_cnt > 39);
end


always@(posedge clk)
begin
    byte_flag <= (cycle_cnt > 39) && (cycle_cnt[2:0] == 7) && (phase_cnt == 5);
end


always@(posedge clk)
begin
    fls_sdo <= tx_reg[31];
end


always@(posedge clk)
begin
    if(sft_ren)
        rx_reg <= {rx_reg[6:0],fls_sdi};
end


always@(posedge clk)
begin
    dout_en <= byte_flag;
end


always@(posedge clk)
begin
    if(byte_flag)
        dout <= rx_reg;
end
 

always@(posedge clk)
begin
    if(start)
        addr <= 24'hFF_FFFF;
    else if(byte_flag)
        addr <= addr + 1;
end


always@(posedge clk)
begin
    if(start)
        busy <= 1;
    else if(cycle_cnt == 28'h800_0028)
        busy <= 0;
end

endmodule
module flash_fast_read
(
    input   wire        clk,


    output  reg         fls_sck,
    output  reg         fls_ncs,
    output  reg         fls_sdo,
    input   wire        fls_sdi,


    input   wire        start,
    output  reg         dout_en,
    output  reg [23:0]  addr,
    output  reg [7:0]   dout,

    output  reg         busy
);


reg [31:0] cnt;
reg [28:0] cycle_cnt; 
reg [2:0] phase_cnt;
reg [31:0] tx_reg;
reg [7:0] rx_reg;
reg sft_wen;
reg sft_ren;
reg byte_flag;

initial
begin
    cnt = 0;
    tx_reg = 0;
    rx_reg = 0;
    busy = 0;
end


always@(posedge clk)
begin
    if(busy)
        cnt <= cnt + 1;
    else
        cnt <= 0;
end


always@(posedge clk)
begin
    cycle_cnt <= cnt[31:3];
end


always@(posedge clk)
begin
    phase_cnt <= cnt[2:0];
end


always@(posedge clk)
begin
    fls_sck <= cnt[2];
end


always@(posedge clk)
begin
    if(busy)
        fls_ncs <= 0;
    else
        fls_ncs <= 1;
end


always@(posedge clk)
begin
    if(start)
        tx_reg <= {8'h0b,8'h00,8'h00,8'h00};
    else if(sft_wen)
        tx_reg <= {tx_reg[30:0],1'b0};
end


always@(posedge clk)
begin
    sft_wen <= (phase_cnt == 6);
end


always@(posedge clk)
begin
    sft_ren <= (phase_cnt == 3) && (cycle_cnt > 39);
end


always@(posedge clk)
begin
    byte_flag <= (cycle_cnt > 39) && (cycle_cnt[2:0] == 7) && (phase_cnt == 5);
end


always@(posedge clk)
begin
    fls_sdo <= tx_reg[31];
end


always@(posedge clk)
begin
    if(sft_ren)
        rx_reg <= {rx_reg[6:0],fls_sdi};
end


always@(posedge clk)
begin
    dout_en <= byte_flag;
end


always@(posedge clk)
begin
    if(byte_flag)
        dout <= rx_reg;
end
 

always@(posedge clk)
begin
    if(start)
        addr <= 24'hFF_FFFF;
    else if(byte_flag)
        addr <= addr + 1;
end


always@(posedge clk)
begin
    if(start)
        busy <= 1;
    else if(cycle_cnt == 28'h800_0028)
        busy <= 0;
end

endmodule