data/full_repos/permissive/169522605/hw3_2/fullAdder_1b.v
data/verilator_xmls/5e899f00-3830-4218-ad39-6bcced138b81.xml
module fullAdder_1b(A, B, C_in, S, C_out);
    input  A, B;
    input  C_in;
    output S;
    output C_out;



endmodule
module fullAdder_1b(A, B, C_in, S, C_out);

    input  A, B;
    input  C_in;
    output S;
    output C_out;



endmodule