data/full_repos/permissive/143278/ivltests/port-test7.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test7.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #(2*1) clk <= 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test7.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #(2*1) if (q !== d) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test7.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #(1 + 1) if (q !== 8\'h00) begin\n      ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg clk, reset;
   reg [7:0] d;
   wire [7:0] q;

   ansireg U(clk, reset, d, q);

   initial begin
      clk = 0;
      reset = 0;
      d = 'hff;

      #(2*`REG_DELAY) clk <= 1;
      #(2*`REG_DELAY) if (q !== d) begin
	 $display("FAILED -- clk=%b, reset=%b, d=%b, q=%b", clk, reset, d, q);
	 $finish;
      end

      reset <= 1;
      #(1 + `REG_DELAY) if (q !== 8'h00) begin
	 $display("FAILED -- clk=%b, reset=%b, d=%b, q=%b", clk, reset, d, q);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;


   reg clk, reset;
   reg [7:0] d;
   wire [7:0] q;

   ansireg U(clk, reset, d, q);

   initial begin
      clk = 0;
      reset = 0;
      d = 'hff;

      #(2*`REG_DELAY) clk <= 1;
      #(2*`REG_DELAY) if (q !== d) begin
	 $display("FAILED -- clk=%b, reset=%b, d=%b, q=%b", clk, reset, d, q);
	 $finish;
      end

      reset <= 1;
      #(1 + `REG_DELAY) if (q !== 8'h00) begin
	 $display("FAILED -- clk=%b, reset=%b, d=%b, q=%b", clk, reset, d, q);
	 $finish;
      end

      $display("PASSED");
   end
endmodule