data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/UART_tx_control_wrapper.v
1: b"%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/UART_tx_control_wrapper.v:14: Cannot find file containing module: 'TX_control'\nTX_control \n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new,data/full_repos/permissive/104660645/TX_control\n             data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new,data/full_repos/permissive/104660645/TX_control.v\n             data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new,data/full_repos/permissive/104660645/TX_control.sv\n             TX_control\n             TX_control.v\n             TX_control.sv\n             obj_dir/TX_control\n             obj_dir/TX_control.v\n             obj_dir/TX_control.sv\n%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/UART_tx_control_wrapper.v:29: Cannot find file containing module: 'TX_sequence'\nTX_sequence TX_sequence_inst0 \n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module UART_tx_control_wrapper
#(	parameter INTER_BYTE_DELAY = 1000000,
    parameter WAIT_FOR_REGISTER_DELAY = 100
)(
	input clock,
    input reset,
    input PB,
    input [15:0] SW,
    output [7:0] tx_data,
    output tx_start,
    output [1:0] stateID
    );

TX_control 
#(  .INTER_BYTE_DELAY (INTER_BYTE_DELAY),
    .WAIT_FOR_REGISTER_DELAY (WAIT_FOR_REGISTER_DELAY)
)TX_control_inst0
(
	.clock (clock),
	.reset (reset),
	.PB (PB),
	.send16 (send16),
	.dataIn16 (SW),
	.tx_data (tx_data),
	.tx_start (tx_start),
	.busy (busy)
    );

TX_sequence TX_sequence_inst0 
(
	.clock (clock),
	.reset (reset),
	.PB (PB),
	.send16 (send16),
	.busy (busy),
	.stateID(stateID)
    );

endmodule
module UART_tx_control_wrapper
#(	parameter INTER_BYTE_DELAY = 1000000,
    parameter WAIT_FOR_REGISTER_DELAY = 100
)(
	input clock,
    input reset,
    input PB,
    input [15:0] SW,
    output [7:0] tx_data,
    output tx_start,
    output [1:0] stateID
    );


TX_control 
#(  .INTER_BYTE_DELAY (INTER_BYTE_DELAY),
    .WAIT_FOR_REGISTER_DELAY (WAIT_FOR_REGISTER_DELAY)
)TX_control_inst0
(
	.clock (clock),
	.reset (reset),
	.PB (PB),
	.send16 (send16),
	.dataIn16 (SW),
	.tx_data (tx_data),
	.tx_start (tx_start),
	.busy (busy)
    );

TX_sequence TX_sequence_inst0 
(
	.clock (clock),
	.reset (reset),
	.PB (PB),
	.send16 (send16),
	.busy (busy),
	.stateID(stateID)
    );

endmodule