data/full_repos/permissive/175132042/rtl/picorv32/scripts/quartus/system_tb.v
 line:13: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/175132042/rtl/picorv32/scripts/quartus/system_tb.v:5: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/quartus/system_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("system.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/quartus/system_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0, system_tb);\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/quartus/system_tb.v:13: syntax error, unexpected \'@\'\n  repeat (100) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/scripts/quartus/system_tb.v:32: Unsupported: $fflush of all handles does not map to C++.\n   $fflush;\n   ^~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module system_tb;
	reg clk = 1;
	always #5 clk = ~clk;

	reg resetn = 0;
	initial begin
		if ($test$plusargs("vcd")) begin
			$dumpfile("system.vcd");
			$dumpvars(0, system_tb);
		end
		repeat (100) @(posedge clk);
		resetn <= 1;
	end

	wire trap;
	wire [7:0] out_byte;
	wire out_byte_en;

	system uut (
		.clk        (clk        ),
		.resetn     (resetn     ),
		.trap       (trap       ),
		.out_byte   (out_byte   ),
		.out_byte_en(out_byte_en)
	);

	always @(posedge clk) begin
		if (resetn && out_byte_en) begin
			$write("%c", out_byte);
			$fflush;
		end
		if (resetn && trap) begin
			$finish;
		end
	end
endmodule
module system_tb;

	reg clk = 1;
	always #5 clk = ~clk;

	reg resetn = 0;
	initial begin
		if ($test$plusargs("vcd")) begin
			$dumpfile("system.vcd");
			$dumpvars(0, system_tb);
		end
		repeat (100) @(posedge clk);
		resetn <= 1;
	end

	wire trap;
	wire [7:0] out_byte;
	wire out_byte_en;

	system uut (
		.clk        (clk        ),
		.resetn     (resetn     ),
		.trap       (trap       ),
		.out_byte   (out_byte   ),
		.out_byte_en(out_byte_en)
	);

	always @(posedge clk) begin
		if (resetn && out_byte_en) begin
			$write("%c", out_byte);
			$fflush;
		end
		if (resetn && trap) begin
			$finish;
		end
	end
endmodule