data/full_repos/permissive/211316121/lab5_2/clkdiv.v
data/verilator_xmls/40a6f2f3-8807-47bc-b256-b48c06b63d31.xml
module clkdiv(
    input mclk,

    output clk20,
    output clk19

    );
    reg [27:0]q;
    always@(posedge mclk )
    begin



         q<=q+1;
    end
    assign clk20=q[20];
    assign clk19=q[19];
      
endmodule
module clkdiv(
    input mclk,

    output clk20,
    output clk19

    );

    reg [27:0]q;
    always@(posedge mclk )
    begin



         q<=q+1;
    end
    assign clk20=q[20];
    assign clk19=q[19];
      
endmodule