data/full_repos/permissive/157436936/ex1/toptb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex1/toptb.v:60: Unsupported: Ignoring delay on this delayed statement.\n always #1 sys_clk = ~sys_clk;\n        ^\n%Error: data/full_repos/permissive/157436936/ex1/toptb.v:15: Cannot find file containing module: \'Top\'\n Top uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/157436936/ex1,data/full_repos/permissive/157436936/Top\n             data/full_repos/permissive/157436936/ex1,data/full_repos/permissive/157436936/Top.v\n             data/full_repos/permissive/157436936/ex1,data/full_repos/permissive/157436936/Top.sv\n             Top\n             Top.v\n             Top.sv\n             obj_dir/Top\n             obj_dir/Top.v\n             obj_dir/Top.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Toptb;


	reg sys_clk;
	reg sys_rst;
	reg [1:0] switch;
	reg [1:0] key;


	wire [1:0] com;
	wire [7:0] seg;
	wire [3:0] led;


	Top uut (
		.sys_clk(sys_clk), 
		.sys_rst(sys_rst), 
		.switch(switch), 
		.key(key), 
		.com(com), 
		.seg(seg), 
		.led(led)
	);

	initial begin

		sys_clk = 0;
		sys_rst = 1;
		switch = 2'b00;
		key = 2'b00;


		#100;
		

		sys_rst = 0;
		#10;
		sys_rst = 1;
		#10;
		switch = 2'b00;
		key = 2'b10;
		#2000000;
		key = 2'b00;
		#2000000;
		key = 2'b10;
		#2000000;
		key = 2'b00;
		#2000000;
		switch = 2'b01;
		#10;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#2000000;
		key = 2'b01;
		#2000000;
		key = 2'b00;
	end

	always #1 sys_clk = ~sys_clk;
      
endmodule
module Toptb;



	reg sys_clk;
	reg sys_rst;
	reg [1:0] switch;
	reg [1:0] key;


	wire [1:0] com;
	wire [7:0] seg;
	wire [3:0] led;


	Top uut (
		.sys_clk(sys_clk), 
		.sys_rst(sys_rst), 
		.switch(switch), 
		.key(key), 
		.com(com), 
		.seg(seg), 
		.led(led)
	);

	initial begin

		sys_clk = 0;
		sys_rst = 1;
		switch = 2'b00;
		key = 2'b00;


		#100;
		

		sys_rst = 0;
		#10;
		sys_rst = 1;
		#10;
		switch = 2'b00;
		key = 2'b10;
		#2000000;
		key = 2'b00;
		#2000000;
		key = 2'b10;
		#2000000;
		key = 2'b00;
		#2000000;
		switch = 2'b01;
		#10;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#2000000;
		key = 2'b01;
		#2000000;
		key = 2'b00;
	end

	always #1 sys_clk = ~sys_clk;
      
endmodule