data/full_repos/permissive/169496369/pc_reg.v
data/verilator_xmls/b263d5e2-a793-4be8-9a79-f7781fd615eb.xml
module pc_reg(clk, rst, pcin, pcout);
    input clk, rst;
    input [31:0] pcin;
    output logic [31:0] pcout;
    
    always_ff@(posedge clk)
    begin
        if(rst)
            pcout <= 32'd0;
        else
            pcout <= pcin;
    end
endmodule
module pc_reg(clk, rst, pcin, pcout);

    input clk, rst;
    input [31:0] pcin;
    output logic [31:0] pcout;
    
    always_ff@(posedge clk)
    begin
        if(rst)
            pcout <= 32'd0;
        else
            pcout <= pcin;
    end
endmodule