data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v
None: at end of input
1: b'%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:20: Cannot find include file: RV2T_common.vh\n`include "RV2T_common.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source,data/full_repos/permissive/158824477/RV2T_common.vh\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source,data/full_repos/permissive/158824477/RV2T_common.vh.v\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source,data/full_repos/permissive/158824477/RV2T_common.vh.sv\n             RV2T_common.vh\n             RV2T_common.vh.v\n             RV2T_common.vh.sv\n             obj_dir/RV2T_common.vh\n             obj_dir/RV2T_common.vh.v\n             obj_dir/RV2T_common.vh.sv\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:43: Define or directive not defined: \'`XLEN\'\n        input wire [`XLEN - 1 : 0]                              csr_new_value,\n                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:44: Define or directive not defined: \'`XLEN\'\n        input wire [`XLEN - 1 : 0]                              csr_old_value,\n                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:46: Define or directive not defined: \'`CSR_BITS\'\n        input wire [`CSR_BITS - 1 : 0]                          csr_addr,\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:50: Define or directive not defined: \'`REG_ADDR_BITS\'\n        input wire [`REG_ADDR_BITS - 1 : 0]                     rd_addr_in,\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:51: Define or directive not defined: \'`XLEN\'\n        input wire [`XLEN - 1 : 0]                              rd_data_in,\n                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:56: Define or directive not defined: \'`XLEN\'\n        input wire [`XLEN - 1 : 0]                              data_to_store,\n                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:57: Define or directive not defined: \'`XLEN\'\n        input wire [`XLEN - 1 : 0]                              mem_access_addr,\n                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:66: Define or directive not defined: \'`XLEN\'\n        output wire [`XLEN - 1 : 0]                             ctl_reg_data_to_write,\n                     ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:67: Define or directive not defined: \'`REG_ADDR_BITS\'\n        output wire [`REG_ADDR_BITS - 1 : 0]                    ctl_reg_addr,\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:73: Define or directive not defined: \'`CSR_ADDR_BITS\'\n        output wire [`CSR_ADDR_BITS - 1 : 0]                    ctl_csr_write_addr,\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:74: Define or directive not defined: \'`XLEN\'\n        output wire [`XLEN - 1 : 0]                             ctl_csr_write_data,\n                     ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:80: Define or directive not defined: \'`XLEN\'\n        input  wire [`XLEN - 1 : 0]                             mem_data_in,\n                     ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:83: Define or directive not defined: \'`XLEN\'\n        input  wire [`XLEN - 1 : 0]                             mm_reg_data_in,\n                     ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:87: Define or directive not defined: \'`XLEN_BYTES\'\n        output reg [`XLEN_BYTES - 1 : 0]                        mem_we,\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:88: Define or directive not defined: \'`XLEN\'\n        output reg [`XLEN - 1 : 0]                              mem_data_to_write,\n                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:89: Define or directive not defined: \'`XLEN\'\n        output reg [`XLEN - 1 : 0]                              mem_addr_rw_out,\n                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:97: Define or directive not defined: \'`XLEN\'\n        output reg [`XLEN - 1 : 0]                              mm_reg_data_to_write,\n                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:98: Define or directive not defined: \'`MM_REG_ADDR_BITS\'\n        output reg [`MM_REG_ADDR_BITS - 1 : 0]                  mm_reg_addr_rw_out\n                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:123: Define or directive not defined: \'`XLEN\'\n        reg [`XLEN - 1 : 0]                                     mem_data_in_reg;\n             ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:124: Define or directive not defined: \'`XLEN\'\n        reg [`XLEN - 1 : 0]                                     load_masked_data;\n             ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:128: Define or directive not defined: \'`XLEN\'\n        wire [`XLEN - 1 : 0]                                    mem_data_in_mux;\n              ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:129: Define or directive not defined: \'`XLEN\'\n        reg [`XLEN - 1 : 0]                                     mem_access_addr_d1;\n             ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:183: Define or directive not defined: \'`MEM_SPACE_BIT\'\n            assign mem_re = ctl_mem_re & mem_access_addr [`MEM_SPACE_BIT];\n                                                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:183: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n            assign mem_re = ctl_mem_re & mem_access_addr [`MEM_SPACE_BIT];\n                                                                        ^\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:198: Define or directive not defined: \'`XLEN\'\n                        mem_data_in_reg = {8\'d0, mem_data_in_mux[`XLEN - 1 : 8]};\n                                                                 ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:202: Define or directive not defined: \'`XLEN\'\n                        mem_data_in_reg = {16\'d0, mem_data_in_mux[`XLEN - 1 : 16]};\n                                                                  ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:206: Define or directive not defined: \'`XLEN\'\n                        mem_data_in_reg = {24\'d0, mem_data_in_mux[`XLEN - 1 : 24]};\n                                                                  ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:278: Define or directive not defined: \'`REG_SPACE_BIT\'\n                    mm_reg_we <= ctl_mem_we & mem_access_addr [`REG_SPACE_BIT];\n                                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:278: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                    mm_reg_we <= ctl_mem_we & mem_access_addr [`REG_SPACE_BIT];\n                                                                             ^\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:279: Define or directive not defined: \'`REG_SPACE_BIT\'\n                    mm_reg_re <= ctl_mem_re & mem_access_addr [`REG_SPACE_BIT];\n                                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:279: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                    mm_reg_re <= ctl_mem_re & mem_access_addr [`REG_SPACE_BIT];\n                                                                             ^\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:282: Define or directive not defined: \'`MM_REG_ADDR_BITS\'\n                    mm_reg_addr_rw_out <= ctl_mem_we ? mem_access_addr [`MM_REG_ADDR_BITS + 1 : 2] : mem_access_addr [`MM_REG_ADDR_BITS + 1 : 2];\n                                                                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:282: Define or directive not defined: \'`MM_REG_ADDR_BITS\'\n                    mm_reg_addr_rw_out <= ctl_mem_we ? mem_access_addr [`MM_REG_ADDR_BITS + 1 : 2] : mem_access_addr [`MM_REG_ADDR_BITS + 1 : 2];\n                                                                                                                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:294: Define or directive not defined: \'`MEM_SPACE_BIT\'\n                    mem_we <= {4{ctl_mem_we & mem_access_addr [`MEM_SPACE_BIT]}} & width_mask;\n                                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_data_access.v:294: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                    mem_we <= {4{ctl_mem_we & mem_access_addr [`MEM_SPACE_BIT]}} & width_mask;\n                                                                             ^\n%Error: Exiting due to 36 error(s)\n'
module RV2T_data_access (



        input wire                                              clk,                          
        input wire                                              reset_n,                      
        input wire                                              sync_reset,




        input wire                                              data_access_enable,
   



        input wire                                              ctl_CSR,
        input wire                                              ctl_CSR_write,
        
        input wire [`XLEN - 1 : 0]                              csr_new_value,
        input wire [`XLEN - 1 : 0]                              csr_old_value,
        
        input wire [`CSR_BITS - 1 : 0]                          csr_addr,
        
        input wire                                              ctl_save_to_rd,
        
        input wire [`REG_ADDR_BITS - 1 : 0]                     rd_addr_in,
        input wire [`XLEN - 1 : 0]                              rd_data_in,
        
        input wire                                              load_active,
        input wire                                              store_active,
        input wire [2 : 0]                                      width_load_store,
        input wire [`XLEN - 1 : 0]                              data_to_store,
        input wire [`XLEN - 1 : 0]                              mem_access_addr,
        input wire                                              mem_access_unaligned,
        
        input wire                                              mul_div_done,
        



        output wire                                             ctl_reg_we,
        output wire [`XLEN - 1 : 0]                             ctl_reg_data_to_write,
        output wire [`REG_ADDR_BITS - 1 : 0]                    ctl_reg_addr,
    



        output wire                                             ctl_csr_we,
        output wire [`CSR_ADDR_BITS - 1 : 0]                    ctl_csr_write_addr,
        output wire [`XLEN - 1 : 0]                             ctl_csr_write_data,
        



        input  wire                                             mem_enable_in,
        input  wire [`XLEN - 1 : 0]                             mem_data_in,
        
        input  wire                                             mm_reg_enable_in,
        input  wire [`XLEN - 1 : 0]                             mm_reg_data_in,
        
        
        output wire                                             mem_re,
        output reg [`XLEN_BYTES - 1 : 0]                        mem_we,
        output reg [`XLEN - 1 : 0]                              mem_data_to_write,
        output reg [`XLEN - 1 : 0]                              mem_addr_rw_out,
        output reg                                              store_done,
        output wire                                             load_done,
        output wire                                             exception_alignment,
        
        output reg                                              mm_reg_re,
        output reg                                              mm_reg_we,
        
        output reg [`XLEN - 1 : 0]                              mm_reg_data_to_write,
        output reg [`MM_REG_ADDR_BITS - 1 : 0]                  mm_reg_addr_rw_out
         
);





        reg                                                     ctl_mem_we;
        reg                                                     ctl_mem_re;
        reg                                                     ctl_mem_we_d1;
        
        reg                                                     ctl_load_exception;
        reg                                                     ctl_store_exception;
        reg                                                     ctl_load_exception_d1;
        
        reg                                                     ctl_store_done;
        reg                                                     ctl_load_done;
        reg                                                     ctl_load_shift;
        reg                                                     ctl_load_mask;
        reg                                                     ctl_load_reg_write;
        
        reg [2 : 0]                                             width_reg;
        reg [3 : 0]                                             width_mask;
        
        reg [`XLEN - 1 : 0]                                     mem_data_in_reg;
        reg [`XLEN - 1 : 0]                                     load_masked_data;
        
        reg [1 : 0]                                             mem_addr_rw_out_tail_reg;
        
        wire [`XLEN - 1 : 0]                                    mem_data_in_mux;
        reg [`XLEN - 1 : 0]                                     mem_access_addr_d1;
        






            assign ctl_reg_we            = (data_access_enable & ctl_save_to_rd) | ctl_load_reg_write | mul_div_done;
            assign ctl_reg_data_to_write = ctl_CSR ? csr_old_value : (ctl_load_reg_write ? load_masked_data : rd_data_in);
            assign ctl_reg_addr          = rd_addr_in;




            assign ctl_csr_we            = data_access_enable & ctl_CSR_write;
            assign ctl_csr_write_addr    = csr_addr;
            assign ctl_csr_write_data    = csr_new_value;
        



            

            always @(*) begin
                if (width_load_store [1 : 0] == 2'b00) begin
                    width_mask = 4'b0001 << (mem_access_addr[1 : 0]);
                end else if (width_load_store [1 : 0] == 2'b01) begin
                    width_mask = 4'b0011 << (mem_access_addr[1 : 0]);
                end else begin
                    width_mask = 4'b1111;
                end
            end
             

            assign mem_re = ctl_mem_re & mem_access_addr [`MEM_SPACE_BIT];
            
            always @(*) begin
                if (ctl_mem_we_d1) begin
                    mem_addr_rw_out = mem_access_addr_d1;
                end else begin
                    mem_addr_rw_out = mem_access_addr;
                end
            end
            
            assign mem_data_in_mux = mem_enable_in ? mem_data_in : mm_reg_data_in;
            
            always @(*) begin
                case (mem_addr_rw_out_tail_reg)
                    2'b01 : begin
                        mem_data_in_reg = {8'd0, mem_data_in_mux[`XLEN - 1 : 8]};
                    end
                    
                    2'b10 : begin
                        mem_data_in_reg = {16'd0, mem_data_in_mux[`XLEN - 1 : 16]};
                    end
                    
                    2'b11 : begin
                        mem_data_in_reg = {24'd0, mem_data_in_mux[`XLEN - 1 : 24]};
                    end
                    
                    default : begin
                        mem_data_in_reg = mem_data_in_mux;
                    end
                    
                endcase
            end
            
            always @(*) begin
                case (width_reg)
                    3'b000 : begin
                        load_masked_data = {{24{mem_data_in_reg[7]}}, mem_data_in_reg[7 : 0]};
                    end
                    
                    3'b001 : begin
                        load_masked_data = {{16{mem_data_in_reg[15]}}, mem_data_in_reg[15 : 0]};
                    end
                    
                    3'b100 : begin
                        load_masked_data = {24'd0, mem_data_in_reg[7 : 0]};
                    end
                    
                    3'b101 : begin
                        load_masked_data = {16'd0, mem_data_in_reg[15 : 0]};
                    end
                    
                    default : begin
                        load_masked_data = mem_data_in_reg;
                    end
                    
                endcase
            end
            
            assign load_done = ctl_load_done;
            
            always @(posedge clk, negedge reset_n) begin
                if (!reset_n) begin

                    mem_we <= 0;
                    mm_reg_re <= 0;
                    mm_reg_we <= 0;
                    mem_data_to_write <= 0;

                    
                    width_reg  <= 0;

                    

                    
                    ctl_mem_we_d1 <= 0;
                    
                    store_done <= 0;

                    

                    
                    mm_reg_data_to_write <= 0;
                    mm_reg_addr_rw_out <= 0;
                    
                    mem_addr_rw_out_tail_reg <= 0;
                    
                    mem_access_addr_d1 <= 0;
                    
                    ctl_load_exception_d1 <= 0;
                    
                end else begin
                    
                    mem_access_addr_d1 <= mem_access_addr;
                    ctl_load_exception_d1 <= ctl_load_exception;
                    
                    mm_reg_we <= ctl_mem_we & mem_access_addr [`REG_SPACE_BIT];
                    mm_reg_re <= ctl_mem_re & mem_access_addr [`REG_SPACE_BIT];
                    
                    mm_reg_data_to_write <= data_to_store;
                    mm_reg_addr_rw_out <= ctl_mem_we ? mem_access_addr [`MM_REG_ADDR_BITS + 1 : 2] : mem_access_addr [`MM_REG_ADDR_BITS + 1 : 2];
                    

                    ctl_mem_we_d1 <= ctl_mem_we;
                    
                    store_done <= ctl_store_done;

                    
                    
                    

                
                    mem_we <= {4{ctl_mem_we & mem_access_addr [`MEM_SPACE_BIT]}} & width_mask;
                    


                case (mem_access_addr[1 : 0])
                    2'b01 : begin
                        mem_data_to_write <= {data_to_store[23 : 0], 8'd0};
                    end

                    2'b10 : begin
                        mem_data_to_write <= {data_to_store[15 : 0], 16'd0};
                    end
                    
                    2'b11 : begin
                        mem_data_to_write <= {data_to_store[7 : 0], 24'd0};
                    end
                    
                    default : begin
                        mem_data_to_write <= data_to_store;
                    end
                    
                endcase
                        


                    

                    
                    if (data_access_enable) begin
                        width_reg <= width_load_store;
                        mem_addr_rw_out_tail_reg <= mem_addr_rw_out [1 : 0];

                    end
                    

                    
                end 
            end
            




            assign exception_alignment = ctl_store_exception | ctl_load_exception_d1;
            



            localparam S_IDLE = 0, S_EXCEPTION = 1, S_LOAD = 2; 
            
            reg [2 : 0] current_state, next_state;
                    

            always @(posedge clk, negedge reset_n) begin : state_machine_reg
                if (!reset_n) begin
                    current_state <= 0;
                end else if (sync_reset) begin 
                    current_state <= 0;
                end else begin
                    current_state <= next_state;
                end
            end
                

            always @(*) begin : state_machine_comb
    
                next_state = 0;
                
                ctl_mem_we               = 0;
                ctl_mem_re               = 0;
                ctl_load_exception       = 0;
                ctl_store_exception      = 0;
                ctl_store_done           = 0;
                ctl_load_done            = 0;
                ctl_load_shift           = 0;
                ctl_load_mask            = 0;
                ctl_load_reg_write       = 0;
                
                case (1'b1)
                    
                    current_state[S_IDLE]: begin
                        if (data_access_enable) begin
                            if (store_active) begin
                                if (mem_access_unaligned) begin
                                    ctl_store_exception = 1'b1;
                                    next_state [S_EXCEPTION] = 1'b1;
                                end else begin
                                    ctl_mem_we = 1'b1;

                                    next_state [S_IDLE] = 1'b1;
                                end
                            end else if (load_active) begin
                                if (mem_access_unaligned) begin
                                    ctl_load_exception = 1'b1;
                                    next_state [S_EXCEPTION] = 1'b1;
                                end else begin
                                    ctl_mem_re = 1'b1;
                                    next_state [S_LOAD] = 1'b1;
                                end
                            end else begin
                                next_state [S_IDLE] = 1'b1;
                            end
                        end else begin
                            next_state [S_IDLE] = 1'b1;
                        end
                    end
                    
                    current_state [S_EXCEPTION] : begin
                        next_state [S_IDLE] = 1'b1;
                    end
                    
                    current_state [S_LOAD] : begin
                        if (mem_enable_in | mm_reg_enable_in) begin

                            
                            ctl_load_reg_write = 1'b1;
                            ctl_load_done = 1'b1;
                            next_state [S_IDLE] = 1'b1;
                        end else begin
                            next_state [S_LOAD] = 1'b1;
                        end
                    end
                    
                    default: begin
                        next_state[S_IDLE] = 1'b1;
                    end
                    
                endcase
                  
            end  
        
endmodule
module RV2T_data_access (



        input wire                                              clk,                          
        input wire                                              reset_n,                      
        input wire                                              sync_reset,




        input wire                                              data_access_enable,
   



        input wire                                              ctl_CSR,
        input wire                                              ctl_CSR_write,
        
        input wire [`XLEN - 1 : 0]                              csr_new_value,
        input wire [`XLEN - 1 : 0]                              csr_old_value,
        
        input wire [`CSR_BITS - 1 : 0]                          csr_addr,
        
        input wire                                              ctl_save_to_rd,
        
        input wire [`REG_ADDR_BITS - 1 : 0]                     rd_addr_in,
        input wire [`XLEN - 1 : 0]                              rd_data_in,
        
        input wire                                              load_active,
        input wire                                              store_active,
        input wire [2 : 0]                                      width_load_store,
        input wire [`XLEN - 1 : 0]                              data_to_store,
        input wire [`XLEN - 1 : 0]                              mem_access_addr,
        input wire                                              mem_access_unaligned,
        
        input wire                                              mul_div_done,
        



        output wire                                             ctl_reg_we,
        output wire [`XLEN - 1 : 0]                             ctl_reg_data_to_write,
        output wire [`REG_ADDR_BITS - 1 : 0]                    ctl_reg_addr,
    



        output wire                                             ctl_csr_we,
        output wire [`CSR_ADDR_BITS - 1 : 0]                    ctl_csr_write_addr,
        output wire [`XLEN - 1 : 0]                             ctl_csr_write_data,
        



        input  wire                                             mem_enable_in,
        input  wire [`XLEN - 1 : 0]                             mem_data_in,
        
        input  wire                                             mm_reg_enable_in,
        input  wire [`XLEN - 1 : 0]                             mm_reg_data_in,
        
        
        output wire                                             mem_re,
        output reg [`XLEN_BYTES - 1 : 0]                        mem_we,
        output reg [`XLEN - 1 : 0]                              mem_data_to_write,
        output reg [`XLEN - 1 : 0]                              mem_addr_rw_out,
        output reg                                              store_done,
        output wire                                             load_done,
        output wire                                             exception_alignment,
        
        output reg                                              mm_reg_re,
        output reg                                              mm_reg_we,
        
        output reg [`XLEN - 1 : 0]                              mm_reg_data_to_write,
        output reg [`MM_REG_ADDR_BITS - 1 : 0]                  mm_reg_addr_rw_out
         
);






        reg                                                     ctl_mem_we;
        reg                                                     ctl_mem_re;
        reg                                                     ctl_mem_we_d1;
        
        reg                                                     ctl_load_exception;
        reg                                                     ctl_store_exception;
        reg                                                     ctl_load_exception_d1;
        
        reg                                                     ctl_store_done;
        reg                                                     ctl_load_done;
        reg                                                     ctl_load_shift;
        reg                                                     ctl_load_mask;
        reg                                                     ctl_load_reg_write;
        
        reg [2 : 0]                                             width_reg;
        reg [3 : 0]                                             width_mask;
        
        reg [`XLEN - 1 : 0]                                     mem_data_in_reg;
        reg [`XLEN - 1 : 0]                                     load_masked_data;
        
        reg [1 : 0]                                             mem_addr_rw_out_tail_reg;
        
        wire [`XLEN - 1 : 0]                                    mem_data_in_mux;
        reg [`XLEN - 1 : 0]                                     mem_access_addr_d1;
        






            assign ctl_reg_we            = (data_access_enable & ctl_save_to_rd) | ctl_load_reg_write | mul_div_done;
            assign ctl_reg_data_to_write = ctl_CSR ? csr_old_value : (ctl_load_reg_write ? load_masked_data : rd_data_in);
            assign ctl_reg_addr          = rd_addr_in;




            assign ctl_csr_we            = data_access_enable & ctl_CSR_write;
            assign ctl_csr_write_addr    = csr_addr;
            assign ctl_csr_write_data    = csr_new_value;
        



            

            always @(*) begin
                if (width_load_store [1 : 0] == 2'b00) begin
                    width_mask = 4'b0001 << (mem_access_addr[1 : 0]);
                end else if (width_load_store [1 : 0] == 2'b01) begin
                    width_mask = 4'b0011 << (mem_access_addr[1 : 0]);
                end else begin
                    width_mask = 4'b1111;
                end
            end
             

            assign mem_re = ctl_mem_re & mem_access_addr [`MEM_SPACE_BIT];
            
            always @(*) begin
                if (ctl_mem_we_d1) begin
                    mem_addr_rw_out = mem_access_addr_d1;
                end else begin
                    mem_addr_rw_out = mem_access_addr;
                end
            end
            
            assign mem_data_in_mux = mem_enable_in ? mem_data_in : mm_reg_data_in;
            
            always @(*) begin
                case (mem_addr_rw_out_tail_reg)
                    2'b01 : begin
                        mem_data_in_reg = {8'd0, mem_data_in_mux[`XLEN - 1 : 8]};
                    end
                    
                    2'b10 : begin
                        mem_data_in_reg = {16'd0, mem_data_in_mux[`XLEN - 1 : 16]};
                    end
                    
                    2'b11 : begin
                        mem_data_in_reg = {24'd0, mem_data_in_mux[`XLEN - 1 : 24]};
                    end
                    
                    default : begin
                        mem_data_in_reg = mem_data_in_mux;
                    end
                    
                endcase
            end
            
            always @(*) begin
                case (width_reg)
                    3'b000 : begin
                        load_masked_data = {{24{mem_data_in_reg[7]}}, mem_data_in_reg[7 : 0]};
                    end
                    
                    3'b001 : begin
                        load_masked_data = {{16{mem_data_in_reg[15]}}, mem_data_in_reg[15 : 0]};
                    end
                    
                    3'b100 : begin
                        load_masked_data = {24'd0, mem_data_in_reg[7 : 0]};
                    end
                    
                    3'b101 : begin
                        load_masked_data = {16'd0, mem_data_in_reg[15 : 0]};
                    end
                    
                    default : begin
                        load_masked_data = mem_data_in_reg;
                    end
                    
                endcase
            end
            
            assign load_done = ctl_load_done;
            
            always @(posedge clk, negedge reset_n) begin
                if (!reset_n) begin

                    mem_we <= 0;
                    mm_reg_re <= 0;
                    mm_reg_we <= 0;
                    mem_data_to_write <= 0;

                    
                    width_reg  <= 0;

                    

                    
                    ctl_mem_we_d1 <= 0;
                    
                    store_done <= 0;

                    

                    
                    mm_reg_data_to_write <= 0;
                    mm_reg_addr_rw_out <= 0;
                    
                    mem_addr_rw_out_tail_reg <= 0;
                    
                    mem_access_addr_d1 <= 0;
                    
                    ctl_load_exception_d1 <= 0;
                    
                end else begin
                    
                    mem_access_addr_d1 <= mem_access_addr;
                    ctl_load_exception_d1 <= ctl_load_exception;
                    
                    mm_reg_we <= ctl_mem_we & mem_access_addr [`REG_SPACE_BIT];
                    mm_reg_re <= ctl_mem_re & mem_access_addr [`REG_SPACE_BIT];
                    
                    mm_reg_data_to_write <= data_to_store;
                    mm_reg_addr_rw_out <= ctl_mem_we ? mem_access_addr [`MM_REG_ADDR_BITS + 1 : 2] : mem_access_addr [`MM_REG_ADDR_BITS + 1 : 2];
                    

                    ctl_mem_we_d1 <= ctl_mem_we;
                    
                    store_done <= ctl_store_done;

                    
                    
                    

                
                    mem_we <= {4{ctl_mem_we & mem_access_addr [`MEM_SPACE_BIT]}} & width_mask;
                    


                case (mem_access_addr[1 : 0])
                    2'b01 : begin
                        mem_data_to_write <= {data_to_store[23 : 0], 8'd0};
                    end

                    2'b10 : begin
                        mem_data_to_write <= {data_to_store[15 : 0], 16'd0};
                    end
                    
                    2'b11 : begin
                        mem_data_to_write <= {data_to_store[7 : 0], 24'd0};
                    end
                    
                    default : begin
                        mem_data_to_write <= data_to_store;
                    end
                    
                endcase
                        


                    

                    
                    if (data_access_enable) begin
                        width_reg <= width_load_store;
                        mem_addr_rw_out_tail_reg <= mem_addr_rw_out [1 : 0];

                    end
                    

                    
                end 
            end
            




            assign exception_alignment = ctl_store_exception | ctl_load_exception_d1;
            



            localparam S_IDLE = 0, S_EXCEPTION = 1, S_LOAD = 2; 
            
            reg [2 : 0] current_state, next_state;
                    

            always @(posedge clk, negedge reset_n) begin : state_machine_reg
                if (!reset_n) begin
                    current_state <= 0;
                end else if (sync_reset) begin 
                    current_state <= 0;
                end else begin
                    current_state <= next_state;
                end
            end
                

            always @(*) begin : state_machine_comb
    
                next_state = 0;
                
                ctl_mem_we               = 0;
                ctl_mem_re               = 0;
                ctl_load_exception       = 0;
                ctl_store_exception      = 0;
                ctl_store_done           = 0;
                ctl_load_done            = 0;
                ctl_load_shift           = 0;
                ctl_load_mask            = 0;
                ctl_load_reg_write       = 0;
                
                case (1'b1)
                    
                    current_state[S_IDLE]: begin
                        if (data_access_enable) begin
                            if (store_active) begin
                                if (mem_access_unaligned) begin
                                    ctl_store_exception = 1'b1;
                                    next_state [S_EXCEPTION] = 1'b1;
                                end else begin
                                    ctl_mem_we = 1'b1;

                                    next_state [S_IDLE] = 1'b1;
                                end
                            end else if (load_active) begin
                                if (mem_access_unaligned) begin
                                    ctl_load_exception = 1'b1;
                                    next_state [S_EXCEPTION] = 1'b1;
                                end else begin
                                    ctl_mem_re = 1'b1;
                                    next_state [S_LOAD] = 1'b1;
                                end
                            end else begin
                                next_state [S_IDLE] = 1'b1;
                            end
                        end else begin
                            next_state [S_IDLE] = 1'b1;
                        end
                    end
                    
                    current_state [S_EXCEPTION] : begin
                        next_state [S_IDLE] = 1'b1;
                    end
                    
                    current_state [S_LOAD] : begin
                        if (mem_enable_in | mm_reg_enable_in) begin

                            
                            ctl_load_reg_write = 1'b1;
                            ctl_load_done = 1'b1;
                            next_state [S_IDLE] = 1'b1;
                        end else begin
                            next_state [S_LOAD] = 1'b1;
                        end
                    end
                    
                    default: begin
                        next_state[S_IDLE] = 1'b1;
                    end
                    
                endcase
                  
            end  
        
endmodule