data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_v2.v
data/verilator_xmls/815a2a21-3d52-41e6-a4be-650a5ce813a9.xml
module SPI_Master(
input clk,
input [31:0]ToSPI,
input enable,
input reset,
output reg MOSI,
output sClk,
output reg SPI_CS
    );

reg [1:0] NS = 0;
reg [1:0] PS = 0;
reg [31:0]sendOut = 0;
parameter idle  = 0;
parameter latchData = 1;
parameter send =  2;
reg [5:0] count = 0;




assign sClk = ~clk;


always@(posedge clk)
begin
	if(~reset)
		PS <= idle;
	else 
		PS <= NS;
end


	
	
	


always@(*)
begin
		NS <= idle;
		case(PS)

			idle			:	NS <= (enable) 			? latchData	:	idle;

			latchData	:	NS <=	send;

			send			:	NS <= (count == 31)		? idle		: 	send;
			default		:	NS <= idle;
		endcase
end	

	

always@(posedge clk)
begin
	count 	<= 0;
	sendOut 	<= 0;
	MOSI 		<=	0;
	case(PS)
	
	latchData 	: 	begin


							sendOut <= ToSPI;

							SPI_CS <= 0;
							count <= count + 1;
							MOSI <= ToSPI[31];
						end
	send			:	begin

							sendOut <= sendOut << 1;
							count <= count + 1;
							SPI_CS <= 0;

							MOSI 	<= sendOut[30];
						end

	default		:	begin



							count <= 0;
							SPI_CS <= 1;
							MOSI <= 0;

						end
	endcase 
end




endmodule
module SPI_Master(
input clk,
input [31:0]ToSPI,
input enable,
input reset,
output reg MOSI,
output sClk,
output reg SPI_CS
    );


reg [1:0] NS = 0;
reg [1:0] PS = 0;
reg [31:0]sendOut = 0;
parameter idle  = 0;
parameter latchData = 1;
parameter send =  2;
reg [5:0] count = 0;




assign sClk = ~clk;


always@(posedge clk)
begin
	if(~reset)
		PS <= idle;
	else 
		PS <= NS;
end


	
	
	


always@(*)
begin
		NS <= idle;
		case(PS)

			idle			:	NS <= (enable) 			? latchData	:	idle;

			latchData	:	NS <=	send;

			send			:	NS <= (count == 31)		? idle		: 	send;
			default		:	NS <= idle;
		endcase
end	

	

always@(posedge clk)
begin
	count 	<= 0;
	sendOut 	<= 0;
	MOSI 		<=	0;
	case(PS)
	
	latchData 	: 	begin


							sendOut <= ToSPI;

							SPI_CS <= 0;
							count <= count + 1;
							MOSI <= ToSPI[31];
						end
	send			:	begin

							sendOut <= sendOut << 1;
							count <= count + 1;
							SPI_CS <= 0;

							MOSI 	<= sendOut[30];
						end

	default		:	begin



							count <= 0;
							SPI_CS <= 1;
							MOSI <= 0;

						end
	endcase 
end




endmodule