data/full_repos/permissive/211316121/lab5_1/clk_div.v
data/verilator_xmls/9a64153b-e2e7-447f-a2bf-f1e5ab0832e5.xml
module clkdiv(
    input mclk,
    input clr,
    output clk190,
    output clk48,
    output clk1_4hz
    );
    reg [27:0]q;
    always@(posedge mclk)
    begin
        if(!clr)
          q<=0;
        else
         q<=q+1;
    end
    assign clk190=q[18];
    assign clk48=q[20];
    assign clk1_4hz=q[24];         
endmodule
module clkdiv(
    input mclk,
    input clr,
    output clk190,
    output clk48,
    output clk1_4hz
    );

    reg [27:0]q;
    always@(posedge mclk)
    begin
        if(!clr)
          q<=0;
        else
         q<=q+1;
    end
    assign clk190=q[18];
    assign clk48=q[20];
    assign clk1_4hz=q[24];         
endmodule