data/full_repos/permissive/189834092/src/pl/sample_clk_gen.v
 line:31: before: "="
data/verilator_xmls/3371c936-340a-44fd-abce-0b661dce149e.xml
module sample_clk_gen#(
        parameter integer C_M_AXIS_DATA_WIDTH = 32
    )(

        input wire                              ACLK,
        input wire                              ARESETN,

        input wire [C_M_AXIS_DATA_WIDTH-1:0]    clk_divider,               

        output reg                              sample_clk = 1'b0
    );
    
    reg [C_M_AXIS_DATA_WIDTH-1:0] counter_r = 'd0;
    
    always @(posedge ACLK) begin

        if(~ARESETN) begin
            sample_clk <= 1'b0;
        end
        else begin


            if(clk_divider > 1) begin

                if(counter_r < (clk_divider - 'd2)) begin
                    counter_r <= counter_r + 'd1;
                end

                else begin
                    counter_r <= 'd0;
                    if(sample_clk == 1'b0) begin
                        sample_clk <= 1'b1;
                    end
                    else begin
                        sample_clk <= 1'b0;
                    end
                end
            end
        end
    end
endmodule
module sample_clk_gen#(
        parameter integer C_M_AXIS_DATA_WIDTH = 32
    )(

        input wire                              ACLK,
        input wire                              ARESETN,

        input wire [C_M_AXIS_DATA_WIDTH-1:0]    clk_divider,               

        output reg                              sample_clk = 1'b0
    );

    
    reg [C_M_AXIS_DATA_WIDTH-1:0] counter_r = 'd0;
    
    always @(posedge ACLK) begin

        if(~ARESETN) begin
            sample_clk <= 1'b0;
        end
        else begin


            if(clk_divider > 1) begin

                if(counter_r < (clk_divider - 'd2)) begin
                    counter_r <= counter_r + 'd1;
                end

                else begin
                    counter_r <= 'd0;
                    if(sample_clk == 1'b0) begin
                        sample_clk <= 1'b1;
                    end
                    else begin
                        sample_clk <= 1'b0;
                    end
                end
            end
        end
    end
endmodule