data/full_repos/permissive/176449044/SPI/test_top.v
 line:45: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/176449044/SPI/test_top.v:26: Unsupported: Ignoring delay on this delayed statement.\n        forever #(10) clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/176449044/SPI/test_top.v:32: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test_top.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/176449044/SPI/test_top.v:33: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,test_top);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/176449044/SPI/test_top.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #(10);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/176449044/SPI/test_top.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #400 rd = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/176449044/SPI/test_top.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #(600) $finish;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_top ;
    reg clk;
    reg rst_n;
    reg rd;
    reg wr;
    reg si;
    reg [`SIZE - 1:0] data_in;

    wire sclk;
    wire so;
    wire cs;
    wire [`SIZE -1:0] data_out;

    reg [`SIZE-1:0] si_buf;


    initial
    begin
        clk = 0;
        forever #(`HALF_PERIOD) clk = ~clk;
    end

    initial
    begin
        $display("spi test_top start");
        $dumpfile("test_top.vcd");
        $dumpvars(0,test_top);

        data_in = 8'b0101_0011;
        si_buf = 8'b1001_1010;

        rst_n = 0;
        #(`HALF_PERIOD);
        rst_n = 1;
        wr = 1;
        rd = 1;
        #400 rd = 0;

        #(`SIM_TIME) $finish;
    end

    always @(posedge clk ) begin 
        si_buf = si_buf << 1;
        si <= si_buf[7];
    end

    spi spi_test (clk,rst_n,rd,wr,si,data_in,sclk,so,cs,data_out);

endmodule
module test_top ;

    reg clk;
    reg rst_n;
    reg rd;
    reg wr;
    reg si;
    reg [`SIZE - 1:0] data_in;

    wire sclk;
    wire so;
    wire cs;
    wire [`SIZE -1:0] data_out;

    reg [`SIZE-1:0] si_buf;


    initial
    begin
        clk = 0;
        forever #(`HALF_PERIOD) clk = ~clk;
    end

    initial
    begin
        $display("spi test_top start");
        $dumpfile("test_top.vcd");
        $dumpvars(0,test_top);

        data_in = 8'b0101_0011;
        si_buf = 8'b1001_1010;

        rst_n = 0;
        #(`HALF_PERIOD);
        rst_n = 1;
        wr = 1;
        rd = 1;
        #400 rd = 0;

        #(`SIM_TIME) $finish;
    end

    always @(posedge clk ) begin 
        si_buf = si_buf << 1;
        si <= si_buf[7];
    end

    spi spi_test (clk,rst_n,rd,wr,si,data_in,sclk,so,cs,data_out);

endmodule