data/full_repos/permissive/218463548/hardware/sim/nvme/pcie_endp_model.v
None: at end of input
1: b'%Error: data/full_repos/permissive/218463548/hardware/sim/nvme/pcie_endp_model.v:82: Cannot find include file: denaliPcieTypes.v\n`include "denaliPcieTypes.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/218463548/hardware/sim/nvme,data/full_repos/permissive/218463548/denaliPcieTypes.v\n             data/full_repos/permissive/218463548/hardware/sim/nvme,data/full_repos/permissive/218463548/denaliPcieTypes.v.v\n             data/full_repos/permissive/218463548/hardware/sim/nvme,data/full_repos/permissive/218463548/denaliPcieTypes.v.sv\n             denaliPcieTypes.v\n             denaliPcieTypes.v.v\n             denaliPcieTypes.v.sv\n             obj_dir/denaliPcieTypes.v\n             obj_dir/denaliPcieTypes.v.v\n             obj_dir/denaliPcieTypes.v.sv\n%Error: Exiting due to 1 error(s)\n'
module pcie_endp_model
  (

   output [25:0] pipe_common_commands_in_rp,
   output [83:0] pipe_rx_0_rp,
   output [83:0] pipe_rx_1_rp,
   output [83:0] pipe_rx_2_rp,
   output [83:0] pipe_rx_3_rp,
   output [83:0] pipe_rx_4_rp,
   output [83:0] pipe_rx_5_rp,
   output [83:0] pipe_rx_6_rp,
   output [83:0] pipe_rx_7_rp,
  
   input  [16:0] pipe_common_commands_out_rp,
   input  [69:0] pipe_tx_0_rp,
   input  [69:0] pipe_tx_1_rp,
   input  [69:0] pipe_tx_2_rp,
   input  [69:0] pipe_tx_3_rp,
   input  [69:0] pipe_tx_4_rp,
   input  [69:0] pipe_tx_5_rp,
   input  [69:0] pipe_tx_6_rp,
   input  [69:0] pipe_tx_7_rp,

   input         sys_rst_n,
   input         nperst
   );

   localparam zero = 256'h0;

   parameter linkWidth = 4;
   parameter maxlinkWidth = 8;


   




`include "denaliPcieTypes.v"


   wire [(32*maxlinkWidth-1):0] TxData;
   wire  [(4*maxlinkWidth-1):0] TxDataK;
   wire                         TxDetectRx;
   wire    [(maxlinkWidth-1):0] TxElecIdle;
   wire    [(maxlinkWidth-1):0] TxCompliance;
   wire    [(maxlinkWidth-1):0] RxPolarity;
   wire                         Reset_n;
   wire                  [15:0] PowerDown;
   wire                   [1:0] Rate;
   

   wire [(32*maxlinkWidth-1):0] RxData;
   wire  [(4*maxlinkWidth-1):0] RxDataK;
   wire    [(maxlinkWidth-1):0] RxValid;
   wire                         PhyStatus;
   wire    [(maxlinkWidth-1):0] RxElecIdle;
   wire  [(3*maxlinkWidth-1):0] RxStatus;
   wire    [(maxlinkWidth-1):0] TxStartBlock;
   wire    [(maxlinkWidth-1):0] RxStartBlock;
   wire    [(maxlinkWidth-1):0] TxDataValid;
   wire    [(maxlinkWidth-1):0] RxDataValid;
   wire  [(2*maxlinkWidth-1):0] TxSyncHeader;
   wire  [(2*maxlinkWidth-1):0] RxSyncHeader;
   



   wire                         PCLK;

   
   xil_sig2pipe xil_dut_pipe (
                              
     .xil_rx0_sigs(pipe_rx_0_rp),
     .xil_rx1_sigs(pipe_rx_1_rp),
     .xil_rx2_sigs(pipe_rx_2_rp),
     .xil_rx3_sigs(pipe_rx_3_rp),
     .xil_rx4_sigs(pipe_rx_4_rp),
     .xil_rx5_sigs(pipe_rx_5_rp),
     .xil_rx6_sigs(pipe_rx_6_rp),
     .xil_rx7_sigs(pipe_rx_7_rp),
     .xil_tx0_sigs(pipe_tx_0_rp),
     .xil_tx1_sigs(pipe_tx_1_rp),
     .xil_tx2_sigs(pipe_tx_2_rp),
     .xil_tx3_sigs(pipe_tx_3_rp),
     .xil_tx4_sigs(pipe_tx_4_rp),
     .xil_tx5_sigs(pipe_tx_5_rp),
     .xil_tx6_sigs(pipe_tx_6_rp),
     .xil_tx7_sigs(pipe_tx_7_rp),     
 
     .xil_common_commands(pipe_common_commands_out_rp),


     .pipe_clk(PCLK),
     .pipe_tx_rate(Rate),
     .pipe_tx_detect_rx(TxDetectRx),
     .pipe_tx_powerdown(PowerDown),

     .pipe_tx0_data(TxData[31:0]),
     .pipe_tx1_data(TxData[63:32]),
     .pipe_tx2_data(TxData[95:64]),
     .pipe_tx3_data(TxData[127:96]),
     .pipe_tx4_data(TxData[159:128]),
     .pipe_tx5_data(TxData[191:160]),
     .pipe_tx6_data(TxData[223:192]),
     .pipe_tx7_data(TxData[255:224]),
     .pipe_tx0_char_is_k(TxDataK[1:0]),
     .pipe_tx1_char_is_k(TxDataK[5:4]),
     .pipe_tx2_char_is_k(TxDataK[9:8]),
     .pipe_tx3_char_is_k(TxDataK[13:12]),
     .pipe_tx4_char_is_k(TxDataK[17:16]),
     .pipe_tx5_char_is_k(TxDataK[21:20]),
     .pipe_tx6_char_is_k(TxDataK[25:24]),
     .pipe_tx7_char_is_k(TxDataK[29:28]),
     .pipe_tx0_elec_idle(TxElecIdle[0]),
     .pipe_tx1_elec_idle(TxElecIdle[1]),
     .pipe_tx2_elec_idle(TxElecIdle[2]),
     .pipe_tx3_elec_idle(TxElecIdle[3]),
     .pipe_tx4_elec_idle(TxElecIdle[4]),
     .pipe_tx5_elec_idle(TxElecIdle[5]),
     .pipe_tx6_elec_idle(TxElecIdle[6]),
     .pipe_tx7_elec_idle(TxElecIdle[7]),
     .pipe_tx0_start_block(TxStartBlock[0]),
     .pipe_tx1_start_block(TxStartBlock[1]),
     .pipe_tx2_start_block(TxStartBlock[2]),
     .pipe_tx3_start_block(TxStartBlock[3]),
     .pipe_tx4_start_block(TxStartBlock[4]),
     .pipe_tx5_start_block(TxStartBlock[5]),
     .pipe_tx6_start_block(TxStartBlock[6]),
     .pipe_tx7_start_block(TxStartBlock[7]),
     .pipe_tx0_syncheader(TxSyncHeader[1:0]),
     .pipe_tx1_syncheader(TxSyncHeader[3:2]),
     .pipe_tx2_syncheader(TxSyncHeader[5:4]),
     .pipe_tx3_syncheader(TxSyncHeader[7:6]),
     .pipe_tx4_syncheader(TxSyncHeader[9:8]),
     .pipe_tx5_syncheader(TxSyncHeader[11:10]),
     .pipe_tx6_syncheader(TxSyncHeader[13:12]),
     .pipe_tx7_syncheader(TxSyncHeader[15:14]),
     .pipe_tx0_data_valid(TxDataValid[0]),
     .pipe_tx1_data_valid(TxDataValid[1]),
     .pipe_tx2_data_valid(TxDataValid[2]),
     .pipe_tx3_data_valid(TxDataValid[3]),
     .pipe_tx4_data_valid(TxDataValid[4]),
     .pipe_tx5_data_valid(TxDataValid[5]),
     .pipe_tx6_data_valid(TxDataValid[6]),
     .pipe_tx7_data_valid(TxDataValid[7]),

     .pipe_rx0_data(RxData[31:0]),
     .pipe_rx1_data(RxData[63:32]),
     .pipe_rx2_data(RxData[95:64]),
     .pipe_rx3_data(RxData[127:96]),
     .pipe_rx4_data(RxData[159:128]),
     .pipe_rx5_data(RxData[191:160]),
     .pipe_rx6_data(RxData[223:192]),
     .pipe_rx7_data(RxData[255:224]),
     .pipe_rx0_char_is_k(RxDataK[1:0]),
     .pipe_rx1_char_is_k(RxDataK[5:4]),
     .pipe_rx2_char_is_k(RxDataK[9:8]),
     .pipe_rx3_char_is_k(RxDataK[13:12]),
     .pipe_rx4_char_is_k(RxDataK[17:16]),
     .pipe_rx5_char_is_k(RxDataK[21:20]),
     .pipe_rx6_char_is_k(RxDataK[25:24]),
     .pipe_rx7_char_is_k(RxDataK[29:28]),
     .pipe_rx0_elec_idle(RxElecIdle[0]),
     .pipe_rx1_elec_idle(RxElecIdle[1]),
     .pipe_rx2_elec_idle(RxElecIdle[2]),
     .pipe_rx3_elec_idle(RxElecIdle[3]),
     .pipe_rx4_elec_idle(RxElecIdle[4]),
     .pipe_rx5_elec_idle(RxElecIdle[5]),
     .pipe_rx6_elec_idle(RxElecIdle[6]),
     .pipe_rx7_elec_idle(RxElecIdle[7]),
     .pipe_rx0_start_block(RxStartBlock[0]),
     .pipe_rx1_start_block(RxStartBlock[1]),
     .pipe_rx2_start_block(RxStartBlock[2]),
     .pipe_rx3_start_block(RxStartBlock[3]),
     .pipe_rx4_start_block(RxStartBlock[4]),
     .pipe_rx5_start_block(RxStartBlock[5]),
     .pipe_rx6_start_block(RxStartBlock[6]),
     .pipe_rx7_start_block(RxStartBlock[7]),
     .pipe_rx0_syncheader(RxSyncHeader[1:0]),
     .pipe_rx1_syncheader(RxSyncHeader[3:2]),
     .pipe_rx2_syncheader(RxSyncHeader[5:4]),
     .pipe_rx3_syncheader(RxSyncHeader[7:6]),
     .pipe_rx4_syncheader(RxSyncHeader[9:8]),
     .pipe_rx5_syncheader(RxSyncHeader[11:10]),
     .pipe_rx6_syncheader(RxSyncHeader[13:12]),
     .pipe_rx7_syncheader(RxSyncHeader[15:14]),
     .pipe_rx0_data_valid(RxDataValid[0]),
     .pipe_rx1_data_valid(RxDataValid[1]),
     .pipe_rx2_data_valid(RxDataValid[2]),
     .pipe_rx3_data_valid(RxDataValid[3]),
     .pipe_rx4_data_valid(RxDataValid[4]),
     .pipe_rx5_data_valid(RxDataValid[5]),
     .pipe_rx6_data_valid(RxDataValid[6]),
     .pipe_rx7_data_valid(RxDataValid[7])
);


   assign PowerDown[1:0]             = pipe_tx_0_rp[41:40];
   assign TxDetectRx                 = pipe_common_commands_out_rp[0];
   assign Rate[1:0]                  = pipe_common_commands_out_rp[2:1];
   assign Reset_n                    = ~pipe_common_commands_out_rp[8];
   assign RxPolarity[7:0]            = 8'd0;
   assign TxCompliance[7:0]          = 8'd0;
   assign TxDataK[3:2]               = 2'b00;
   assign TxDataK[7:6]               = 2'b00;
   assign TxDataK[11:10]             = 2'b00;
   assign TxDataK[15:14]             = 2'b00;
   assign pipe_common_commands_in_rp = 26'b0;



   endp_4_pipe32 #(linkWidth) endp 
     (
      .TxData (TxData[(32*linkWidth-1):0]),
      .TxDataK (TxDataK[(4*linkWidth-1):0]),
      .RxData (RxData[(32*linkWidth-1):0]),
      .RxDataK (RxDataK[(4*linkWidth-1):0]),
      .TxDetectRx (TxDetectRx),
      .TxElecIdle (TxElecIdle[(linkWidth-1):0]),
      .TxCompliance (TxCompliance[(linkWidth-1):0]),
      .RxPolarity (RxPolarity[(linkWidth-1):0]),
      .Reset_ (Reset_n),
      .PowerDown (PowerDown[1:0]),
      .RxValid (RxValid[(linkWidth-1):0]),
      .PhyStatus (PhyStatus),
      .RxElecIdle (RxElecIdle[(linkWidth-1):0]),
      .RxStatus (RxStatus[(3*linkWidth-1):0]),
      .PCLK (PCLK),
      .Rate (Rate),
      .TxStartBlock (TxStartBlock[(linkWidth-1):0]),
      .RxStartBlock (RxStartBlock[(linkWidth-1):0]),
      .TxDataValid (TxDataValid[(linkWidth-1):0]),
      .RxDataValid (RxDataValid[(linkWidth-1):0]),
      .TxSyncHeader (TxSyncHeader[(2*linkWidth-1):0]),
      .RxSyncHeader (RxSyncHeader[(2*linkWidth-1):0])
      );
   

   generate if( maxlinkWidth>linkWidth) begin :unused_lanes
      assign RxData[(32*maxlinkWidth-1):(32*linkWidth)] = zero[(32*maxlinkWidth-1):(32*linkWidth)];
      assign RxDataK[(4*maxlinkWidth-1):(4*linkWidth)] = zero[(4*maxlinkWidth-1):(4*linkWidth)];
      assign RxValid[(maxlinkWidth-1):(linkWidth)] = zero[(maxlinkWidth-1):(linkWidth)];      
      assign RxElecIdle[(maxlinkWidth-1):(linkWidth)] = zero[(maxlinkWidth-1):(linkWidth)];
      assign RxStatus[(3*maxlinkWidth-1):(3*linkWidth)] = zero[(3*maxlinkWidth-1):(3*linkWidth)];
      assign RxStartBlock[(maxlinkWidth-1):(linkWidth)] = zero[(maxlinkWidth-1):(linkWidth)];
      assign RxDataValid[(maxlinkWidth-1):(linkWidth)] = zero[(maxlinkWidth-1):(linkWidth)];
      assign RxSyncHeader[(2*maxlinkWidth-1):(2*linkWidth)] = zero[(2*maxlinkWidth-1):(2*linkWidth)];
   end
   endgenerate
   
   defparam endp.interface_soma = "./denali/endp_4_pipe32.soma";
endmodule
module pcie_endp_model
  (

   output [25:0] pipe_common_commands_in_rp,
   output [83:0] pipe_rx_0_rp,
   output [83:0] pipe_rx_1_rp,
   output [83:0] pipe_rx_2_rp,
   output [83:0] pipe_rx_3_rp,
   output [83:0] pipe_rx_4_rp,
   output [83:0] pipe_rx_5_rp,
   output [83:0] pipe_rx_6_rp,
   output [83:0] pipe_rx_7_rp,
  
   input  [16:0] pipe_common_commands_out_rp,
   input  [69:0] pipe_tx_0_rp,
   input  [69:0] pipe_tx_1_rp,
   input  [69:0] pipe_tx_2_rp,
   input  [69:0] pipe_tx_3_rp,
   input  [69:0] pipe_tx_4_rp,
   input  [69:0] pipe_tx_5_rp,
   input  [69:0] pipe_tx_6_rp,
   input  [69:0] pipe_tx_7_rp,

   input         sys_rst_n,
   input         nperst
   );


   localparam zero = 256'h0;

   parameter linkWidth = 4;
   parameter maxlinkWidth = 8;


   




`include "denaliPcieTypes.v"


   wire [(32*maxlinkWidth-1):0] TxData;
   wire  [(4*maxlinkWidth-1):0] TxDataK;
   wire                         TxDetectRx;
   wire    [(maxlinkWidth-1):0] TxElecIdle;
   wire    [(maxlinkWidth-1):0] TxCompliance;
   wire    [(maxlinkWidth-1):0] RxPolarity;
   wire                         Reset_n;
   wire                  [15:0] PowerDown;
   wire                   [1:0] Rate;
   

   wire [(32*maxlinkWidth-1):0] RxData;
   wire  [(4*maxlinkWidth-1):0] RxDataK;
   wire    [(maxlinkWidth-1):0] RxValid;
   wire                         PhyStatus;
   wire    [(maxlinkWidth-1):0] RxElecIdle;
   wire  [(3*maxlinkWidth-1):0] RxStatus;
   wire    [(maxlinkWidth-1):0] TxStartBlock;
   wire    [(maxlinkWidth-1):0] RxStartBlock;
   wire    [(maxlinkWidth-1):0] TxDataValid;
   wire    [(maxlinkWidth-1):0] RxDataValid;
   wire  [(2*maxlinkWidth-1):0] TxSyncHeader;
   wire  [(2*maxlinkWidth-1):0] RxSyncHeader;
   



   wire                         PCLK;

   
   xil_sig2pipe xil_dut_pipe (
                              
     .xil_rx0_sigs(pipe_rx_0_rp),
     .xil_rx1_sigs(pipe_rx_1_rp),
     .xil_rx2_sigs(pipe_rx_2_rp),
     .xil_rx3_sigs(pipe_rx_3_rp),
     .xil_rx4_sigs(pipe_rx_4_rp),
     .xil_rx5_sigs(pipe_rx_5_rp),
     .xil_rx6_sigs(pipe_rx_6_rp),
     .xil_rx7_sigs(pipe_rx_7_rp),
     .xil_tx0_sigs(pipe_tx_0_rp),
     .xil_tx1_sigs(pipe_tx_1_rp),
     .xil_tx2_sigs(pipe_tx_2_rp),
     .xil_tx3_sigs(pipe_tx_3_rp),
     .xil_tx4_sigs(pipe_tx_4_rp),
     .xil_tx5_sigs(pipe_tx_5_rp),
     .xil_tx6_sigs(pipe_tx_6_rp),
     .xil_tx7_sigs(pipe_tx_7_rp),     
 
     .xil_common_commands(pipe_common_commands_out_rp),


     .pipe_clk(PCLK),
     .pipe_tx_rate(Rate),
     .pipe_tx_detect_rx(TxDetectRx),
     .pipe_tx_powerdown(PowerDown),

     .pipe_tx0_data(TxData[31:0]),
     .pipe_tx1_data(TxData[63:32]),
     .pipe_tx2_data(TxData[95:64]),
     .pipe_tx3_data(TxData[127:96]),
     .pipe_tx4_data(TxData[159:128]),
     .pipe_tx5_data(TxData[191:160]),
     .pipe_tx6_data(TxData[223:192]),
     .pipe_tx7_data(TxData[255:224]),
     .pipe_tx0_char_is_k(TxDataK[1:0]),
     .pipe_tx1_char_is_k(TxDataK[5:4]),
     .pipe_tx2_char_is_k(TxDataK[9:8]),
     .pipe_tx3_char_is_k(TxDataK[13:12]),
     .pipe_tx4_char_is_k(TxDataK[17:16]),
     .pipe_tx5_char_is_k(TxDataK[21:20]),
     .pipe_tx6_char_is_k(TxDataK[25:24]),
     .pipe_tx7_char_is_k(TxDataK[29:28]),
     .pipe_tx0_elec_idle(TxElecIdle[0]),
     .pipe_tx1_elec_idle(TxElecIdle[1]),
     .pipe_tx2_elec_idle(TxElecIdle[2]),
     .pipe_tx3_elec_idle(TxElecIdle[3]),
     .pipe_tx4_elec_idle(TxElecIdle[4]),
     .pipe_tx5_elec_idle(TxElecIdle[5]),
     .pipe_tx6_elec_idle(TxElecIdle[6]),
     .pipe_tx7_elec_idle(TxElecIdle[7]),
     .pipe_tx0_start_block(TxStartBlock[0]),
     .pipe_tx1_start_block(TxStartBlock[1]),
     .pipe_tx2_start_block(TxStartBlock[2]),
     .pipe_tx3_start_block(TxStartBlock[3]),
     .pipe_tx4_start_block(TxStartBlock[4]),
     .pipe_tx5_start_block(TxStartBlock[5]),
     .pipe_tx6_start_block(TxStartBlock[6]),
     .pipe_tx7_start_block(TxStartBlock[7]),
     .pipe_tx0_syncheader(TxSyncHeader[1:0]),
     .pipe_tx1_syncheader(TxSyncHeader[3:2]),
     .pipe_tx2_syncheader(TxSyncHeader[5:4]),
     .pipe_tx3_syncheader(TxSyncHeader[7:6]),
     .pipe_tx4_syncheader(TxSyncHeader[9:8]),
     .pipe_tx5_syncheader(TxSyncHeader[11:10]),
     .pipe_tx6_syncheader(TxSyncHeader[13:12]),
     .pipe_tx7_syncheader(TxSyncHeader[15:14]),
     .pipe_tx0_data_valid(TxDataValid[0]),
     .pipe_tx1_data_valid(TxDataValid[1]),
     .pipe_tx2_data_valid(TxDataValid[2]),
     .pipe_tx3_data_valid(TxDataValid[3]),
     .pipe_tx4_data_valid(TxDataValid[4]),
     .pipe_tx5_data_valid(TxDataValid[5]),
     .pipe_tx6_data_valid(TxDataValid[6]),
     .pipe_tx7_data_valid(TxDataValid[7]),

     .pipe_rx0_data(RxData[31:0]),
     .pipe_rx1_data(RxData[63:32]),
     .pipe_rx2_data(RxData[95:64]),
     .pipe_rx3_data(RxData[127:96]),
     .pipe_rx4_data(RxData[159:128]),
     .pipe_rx5_data(RxData[191:160]),
     .pipe_rx6_data(RxData[223:192]),
     .pipe_rx7_data(RxData[255:224]),
     .pipe_rx0_char_is_k(RxDataK[1:0]),
     .pipe_rx1_char_is_k(RxDataK[5:4]),
     .pipe_rx2_char_is_k(RxDataK[9:8]),
     .pipe_rx3_char_is_k(RxDataK[13:12]),
     .pipe_rx4_char_is_k(RxDataK[17:16]),
     .pipe_rx5_char_is_k(RxDataK[21:20]),
     .pipe_rx6_char_is_k(RxDataK[25:24]),
     .pipe_rx7_char_is_k(RxDataK[29:28]),
     .pipe_rx0_elec_idle(RxElecIdle[0]),
     .pipe_rx1_elec_idle(RxElecIdle[1]),
     .pipe_rx2_elec_idle(RxElecIdle[2]),
     .pipe_rx3_elec_idle(RxElecIdle[3]),
     .pipe_rx4_elec_idle(RxElecIdle[4]),
     .pipe_rx5_elec_idle(RxElecIdle[5]),
     .pipe_rx6_elec_idle(RxElecIdle[6]),
     .pipe_rx7_elec_idle(RxElecIdle[7]),
     .pipe_rx0_start_block(RxStartBlock[0]),
     .pipe_rx1_start_block(RxStartBlock[1]),
     .pipe_rx2_start_block(RxStartBlock[2]),
     .pipe_rx3_start_block(RxStartBlock[3]),
     .pipe_rx4_start_block(RxStartBlock[4]),
     .pipe_rx5_start_block(RxStartBlock[5]),
     .pipe_rx6_start_block(RxStartBlock[6]),
     .pipe_rx7_start_block(RxStartBlock[7]),
     .pipe_rx0_syncheader(RxSyncHeader[1:0]),
     .pipe_rx1_syncheader(RxSyncHeader[3:2]),
     .pipe_rx2_syncheader(RxSyncHeader[5:4]),
     .pipe_rx3_syncheader(RxSyncHeader[7:6]),
     .pipe_rx4_syncheader(RxSyncHeader[9:8]),
     .pipe_rx5_syncheader(RxSyncHeader[11:10]),
     .pipe_rx6_syncheader(RxSyncHeader[13:12]),
     .pipe_rx7_syncheader(RxSyncHeader[15:14]),
     .pipe_rx0_data_valid(RxDataValid[0]),
     .pipe_rx1_data_valid(RxDataValid[1]),
     .pipe_rx2_data_valid(RxDataValid[2]),
     .pipe_rx3_data_valid(RxDataValid[3]),
     .pipe_rx4_data_valid(RxDataValid[4]),
     .pipe_rx5_data_valid(RxDataValid[5]),
     .pipe_rx6_data_valid(RxDataValid[6]),
     .pipe_rx7_data_valid(RxDataValid[7])
);


   assign PowerDown[1:0]             = pipe_tx_0_rp[41:40];
   assign TxDetectRx                 = pipe_common_commands_out_rp[0];
   assign Rate[1:0]                  = pipe_common_commands_out_rp[2:1];
   assign Reset_n                    = ~pipe_common_commands_out_rp[8];
   assign RxPolarity[7:0]            = 8'd0;
   assign TxCompliance[7:0]          = 8'd0;
   assign TxDataK[3:2]               = 2'b00;
   assign TxDataK[7:6]               = 2'b00;
   assign TxDataK[11:10]             = 2'b00;
   assign TxDataK[15:14]             = 2'b00;
   assign pipe_common_commands_in_rp = 26'b0;



   endp_4_pipe32 #(linkWidth) endp 
     (
      .TxData (TxData[(32*linkWidth-1):0]),
      .TxDataK (TxDataK[(4*linkWidth-1):0]),
      .RxData (RxData[(32*linkWidth-1):0]),
      .RxDataK (RxDataK[(4*linkWidth-1):0]),
      .TxDetectRx (TxDetectRx),
      .TxElecIdle (TxElecIdle[(linkWidth-1):0]),
      .TxCompliance (TxCompliance[(linkWidth-1):0]),
      .RxPolarity (RxPolarity[(linkWidth-1):0]),
      .Reset_ (Reset_n),
      .PowerDown (PowerDown[1:0]),
      .RxValid (RxValid[(linkWidth-1):0]),
      .PhyStatus (PhyStatus),
      .RxElecIdle (RxElecIdle[(linkWidth-1):0]),
      .RxStatus (RxStatus[(3*linkWidth-1):0]),
      .PCLK (PCLK),
      .Rate (Rate),
      .TxStartBlock (TxStartBlock[(linkWidth-1):0]),
      .RxStartBlock (RxStartBlock[(linkWidth-1):0]),
      .TxDataValid (TxDataValid[(linkWidth-1):0]),
      .RxDataValid (RxDataValid[(linkWidth-1):0]),
      .TxSyncHeader (TxSyncHeader[(2*linkWidth-1):0]),
      .RxSyncHeader (RxSyncHeader[(2*linkWidth-1):0])
      );
   

   generate if( maxlinkWidth>linkWidth) begin :unused_lanes
      assign RxData[(32*maxlinkWidth-1):(32*linkWidth)] = zero[(32*maxlinkWidth-1):(32*linkWidth)];
      assign RxDataK[(4*maxlinkWidth-1):(4*linkWidth)] = zero[(4*maxlinkWidth-1):(4*linkWidth)];
      assign RxValid[(maxlinkWidth-1):(linkWidth)] = zero[(maxlinkWidth-1):(linkWidth)];      
      assign RxElecIdle[(maxlinkWidth-1):(linkWidth)] = zero[(maxlinkWidth-1):(linkWidth)];
      assign RxStatus[(3*maxlinkWidth-1):(3*linkWidth)] = zero[(3*maxlinkWidth-1):(3*linkWidth)];
      assign RxStartBlock[(maxlinkWidth-1):(linkWidth)] = zero[(maxlinkWidth-1):(linkWidth)];
      assign RxDataValid[(maxlinkWidth-1):(linkWidth)] = zero[(maxlinkWidth-1):(linkWidth)];
      assign RxSyncHeader[(2*maxlinkWidth-1):(2*linkWidth)] = zero[(2*maxlinkWidth-1):(2*linkWidth)];
   end
   endgenerate
   
   defparam endp.interface_soma = "./denali/endp_4_pipe32.soma";
endmodule