data/full_repos/permissive/168395472/labs/09_vga/top.v
1: b'%Error: data/full_repos/permissive/168395472/labs/09_vga/top.v:17: Cannot find file containing module: \'pll\'\npll pll_inst(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/168395472/labs/09_vga,data/full_repos/permissive/168395472/pll\n             data/full_repos/permissive/168395472/labs/09_vga,data/full_repos/permissive/168395472/pll.v\n             data/full_repos/permissive/168395472/labs/09_vga,data/full_repos/permissive/168395472/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/168395472/labs/09_vga/top.v:28: Cannot find file containing module: \'rom\'\nrom #(13, 3, "rom.txt") vrom(vrom_addr, vga_clk, vrom_q);\n^~~\n%Error: data/full_repos/permissive/168395472/labs/09_vga/top.v:30: Cannot find file containing module: \'vga_sync\'\nvga_sync vga_sync(vga_clk, H_SYNC, V_SYNC, x, y);\n^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/168395472/labs/09_vga/top.v:35: Operator ADD expects 32 or 13 bits on the LHS, but LHS\'s SEL generates 7 bits.\n                                                                         : ... In instance top\n    vrom_addr = x_fwd[9:3] + y[9:3] * 80;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module top (
    input CLK,

    output H_SYNC, V_SYNC,
    output [4:0]V_R,
    output [5:0]V_G,
    output [4:0]V_B
);

reg [2:0]rgb;

assign V_R = {5{rgb[0]}};
assign V_G = {6{rgb[1]}};
assign V_B = {5{rgb[2]}};

wire vga_clk;
pll pll_inst(
    .inclk0(CLK),
    .c0(vga_clk)
);

wire [9:0]x;
wire [9:0]y;

reg [12:0]vrom_addr;
wire [2:0]vrom_q;

rom #(13, 3, "rom.txt") vrom(vrom_addr, vga_clk, vrom_q);

vga_sync vga_sync(vga_clk, H_SYNC, V_SYNC, x, y);

wire [9:0]x_fwd = x + 1;

always @(*) begin
    vrom_addr = x_fwd[9:3] + y[9:3] * 80;
    rgb = ((x < 640) && (y < 480)) ? vrom_q : 3'b0;
end

endmodule
module top (
    input CLK,

    output H_SYNC, V_SYNC,
    output [4:0]V_R,
    output [5:0]V_G,
    output [4:0]V_B
);


reg [2:0]rgb;

assign V_R = {5{rgb[0]}};
assign V_G = {6{rgb[1]}};
assign V_B = {5{rgb[2]}};

wire vga_clk;
pll pll_inst(
    .inclk0(CLK),
    .c0(vga_clk)
);

wire [9:0]x;
wire [9:0]y;

reg [12:0]vrom_addr;
wire [2:0]vrom_q;

rom #(13, 3, "rom.txt") vrom(vrom_addr, vga_clk, vrom_q);

vga_sync vga_sync(vga_clk, H_SYNC, V_SYNC, x, y);

wire [9:0]x_fwd = x + 1;

always @(*) begin
    vrom_addr = x_fwd[9:3] + y[9:3] * 80;
    rgb = ((x < 640) && (y < 480)) ? vrom_q : 3'b0;
end

endmodule