data/full_repos/permissive/143278/ivltests/p_monta.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/p_monta.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/p_monta.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main();

function [7:0] f;
  input [7:0] r;
  f = {
    r[0]^r[1]^r[2]^r[3]^r[7],
    r[3]^r[6]^r[7],
    r[2]^r[5]^r[6],
    r[1]^r[4]^r[5]^r[7],
    r[0]^r[3]^r[4]^r[6]^r[7],
    r[0]^r[1]^r[5]^r[6],
    r[1]^r[2]^r[3]^r[4]^r[5],
    r[0]^r[1]^r[2]^r[3]^r[4] };
endfunction

  reg [7:0] data_in;
  reg [7:0] r;
  reg start_in;

  initial begin
    data_in = 8'h23;
    r = 0;
    start_in = 0;
    #2;
    r <= #1 start_in ? 0 : f(data_in);
    #2;
    $display("%b",r);
     if (r === 8'b00101100)
       $display("PASSED");
     else
       $display("FAILED");
  end

endmodule
module main();


function [7:0] f;
  input [7:0] r;
  f = {
    r[0]^r[1]^r[2]^r[3]^r[7],
    r[3]^r[6]^r[7],
    r[2]^r[5]^r[6],
    r[1]^r[4]^r[5]^r[7],
    r[0]^r[3]^r[4]^r[6]^r[7],
    r[0]^r[1]^r[5]^r[6],
    r[1]^r[2]^r[3]^r[4]^r[5],
    r[0]^r[1]^r[2]^r[3]^r[4] };
endfunction

  reg [7:0] data_in;
  reg [7:0] r;
  reg start_in;

  initial begin
    data_in = 8'h23;
    r = 0;
    start_in = 0;
    #2;
    r <= #1 start_in ? 0 : f(data_in);
    #2;
    $display("%b",r);
     if (r === 8'b00101100)
       $display("PASSED");
     else
       $display("FAILED");
  end

endmodule