data/full_repos/permissive/18469949/tb_lc3_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/18469949/tb_lc3_top.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #4 reset=0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/18469949/tb_lc3_top.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #2 LD_char=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18469949/tb_lc3_top.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #2 LD_char=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18469949/tb_lc3_top.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk=~clk;\n  ^\n%Error: data/full_repos/permissive/18469949/tb_lc3_top.v:51: Cannot find file containing module: \'LC3_computer_top\'\nLC3_computer_top lc3(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18469949,data/full_repos/permissive/18469949/LC3_computer_top\n             data/full_repos/permissive/18469949,data/full_repos/permissive/18469949/LC3_computer_top.v\n             data/full_repos/permissive/18469949,data/full_repos/permissive/18469949/LC3_computer_top.sv\n             LC3_computer_top\n             LC3_computer_top.v\n             LC3_computer_top.sv\n             obj_dir/LC3_computer_top\n             obj_dir/LC3_computer_top.v\n             obj_dir/LC3_computer_top.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_lc3_top;


reg	clk;
reg	reset;
reg	LD_char;
reg	[7:0]	I_char;
wire	[15:0]	DDR;
wire				WR_DDR;


initial
	begin
		clk=0;
		reset=1;
		LD_char=0;
		I_char=8'h30;
	end
	
initial
	begin
		#4	reset=0;
		#2 LD_char=1;
		#2 LD_char=0;
	end

initial
	forever
		#1	clk=~clk;

LC3_computer_top	lc3(
		.clk						(clk),
		.reset					(reset),
		
		.LD_char					(LD_char),
		.I_char					(I_char),
		.DDR						(DDR),
		.WR_DDR					(WR_DDR)
    );
	 
endmodule
module tb_lc3_top;



reg	clk;
reg	reset;
reg	LD_char;
reg	[7:0]	I_char;
wire	[15:0]	DDR;
wire				WR_DDR;


initial
	begin
		clk=0;
		reset=1;
		LD_char=0;
		I_char=8'h30;
	end
	
initial
	begin
		#4	reset=0;
		#2 LD_char=1;
		#2 LD_char=0;
	end

initial
	forever
		#1	clk=~clk;

LC3_computer_top	lc3(
		.clk						(clk),
		.reset					(reset),
		
		.LD_char					(LD_char),
		.I_char					(I_char),
		.DDR						(DDR),
		.WR_DDR					(WR_DDR)
    );
	 
endmodule