data/full_repos/permissive/163494071/analog/analog.v
 line:349: before: "["
1: b'%Warning-MULTITOP: data/full_repos/permissive/163494071/analog/analog.v:322: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'analog\'\nmodule analog(clk,rst,start,change_map,direction1,direction2,direction3,direction4,time_sign,row,g_col,r_col,suc,step_cnt);\n       ^~~~~~\n                                                                           : ... Top module \'two_ten\'\nmodule two_ten(clk,num,ten,one);\n       ^~~~~~~\n                                                                           : ... Top module \'debounce\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n       ^~~~~~~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                ^~~\n        data/full_repos/permissive/163494071/analog/analog.v:355: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                       ^~~\n        data/full_repos/permissive/163494071/analog/analog.v:355: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                              ^~~\n        data/full_repos/permissive/163494071/analog/analog.v:355: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key_pulse\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                  ^~~~~~~~~\n        data/full_repos/permissive/163494071/analog/analog.v:356: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key_pulse\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                               ^~~~~~~~~\n        data/full_repos/permissive/163494071/analog/analog.v:356: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key_pulse\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                                            ^~~~~~~~~\n        data/full_repos/permissive/163494071/analog/analog.v:356: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module sw(clk,key_in,key_out);
	input key_in;
	input clk;
	output reg key_out;
	reg [19:0]tcnt1;
	
	always @(posedge clk or negedge key_in)
	begin
	if(!key_in)tcnt1<=20'd0;
	else tcnt1<=tcnt1+1;
	end
	always @(posedge clk or negedge key_in)
	begin
	if(!key_in)key_out<=0;
		else if(tcnt1==20'h1)key_out<=key_in;
	end
endmodule
module sw(clk,key_in,key_out);

	input key_in;
	input clk;
	output reg key_out;
	reg [19:0]tcnt1;
	
	always @(posedge clk or negedge key_in)
	begin
	if(!key_in)tcnt1<=20'd0;
	else tcnt1<=tcnt1+1;
	end
	always @(posedge clk or negedge key_in)
	begin
	if(!key_in)key_out<=0;
		else if(tcnt1==20'h1)key_out<=key_in;
	end
endmodule