data/full_repos/permissive/143278/ivltests/ptest011.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ptest011.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
  wire [3:0] a,b,c,d,e,f;

  ma a1(a);
  ma #(4'd9) a2(b);
  mb #(4'd12) b1(c);
  mb b2(d);
  mc #(4'd2) c1(e,f);

  initial begin
    #1;
    if (a===4'd5 && b===4'd9 && c===4'd12 && d===4'd7 && e===4'd2 && f===4'd3)
      $display("PASSED");
    else
      $display("FAILED");
  end
endmodule
module main;

  wire [3:0] a,b,c,d,e,f;

  ma a1(a);
  ma #(4'd9) a2(b);
  mb #(4'd12) b1(c);
  mb b2(d);
  mc #(4'd2) c1(e,f);

  initial begin
    #1;
    if (a===4'd5 && b===4'd9 && c===4'd12 && d===4'd7 && e===4'd2 && f===4'd3)
      $display("PASSED");
    else
      $display("FAILED");
  end
endmodule