data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_full_add.svp
 line:4: before: "parameter"
1: b"%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_full_add.svp:3: Define or directive not defined: '`mname'\nmodule `mname`  #(\n       ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_full_add.svp:3: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule `mname`  #(\n             ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_full_add.svp:5: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_full_add.svp:14: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic                  c_out\n  ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/rtl/test_full_add.svp:19: syntax error, unexpected assign\nassign {c_out_lsb, res[DataWidth/2-1:0]} = a[DataWidth/2-1:0] + b[DataWidth/2-1:0] + c_in;\n^~~~~~\n%Error: Exiting due to 5 error(s)\n"
module `mname`  #(
  parameter DataWidth = 16
) (

  input  [DataWidth-1:0]        a,
  input  [DataWidth-1:0]        b,
  input                         c_in,

  input                    dual_mode,

  output logic [DataWidth-1:0]  res,
  output logic                  c_out
);


logic c_out_lsb;
assign {c_out_lsb, res[DataWidth/2-1:0]} = a[DataWidth/2-1:0] + b[DataWidth/2-1:0] + c_in;
assign {c_out, res[DataWidth-1:DataWidth/2]} = a[DataWidth-1:DataWidth/2] + b[DataWidth-1:DataWidth/2] +
                                               (c_out_lsb );

assign {c_out, res} = a + b + c_in;


endmodule
module `mname`  #(
  parameter DataWidth = 16
) (

  input  [DataWidth-1:0]        a,
  input  [DataWidth-1:0]        b,
  input                         c_in,

  input                    dual_mode,

  output logic [DataWidth-1:0]  res,
  output logic                  c_out
);



logic c_out_lsb;
assign {c_out_lsb, res[DataWidth/2-1:0]} = a[DataWidth/2-1:0] + b[DataWidth/2-1:0] + c_in;
assign {c_out, res[DataWidth-1:DataWidth/2]} = a[DataWidth-1:DataWidth/2] + b[DataWidth-1:DataWidth/2] +
                                               (c_out_lsb );

assign {c_out, res} = a + b + c_in;


endmodule