data/full_repos/permissive/146975244/Extender.v
1: b'%Warning-WIDTH: data/full_repos/permissive/146975244/Extender.v:10: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'IMM16\' generates 16 bits.\n                                                                  : ... In instance Extender\n  result = IMM16;\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Extender (IMM16, result, clock);

input [15:0] IMM16;
input clock;


output reg [31:0] result;

always @ (*) begin
		result = IMM16;
		if(IMM16[15]==1'b1) result = {{16{IMM16[15]}}, IMM16};;
end

endmodule
module Extender (IMM16, result, clock);


input [15:0] IMM16;
input clock;


output reg [31:0] result;

always @ (*) begin
		result = IMM16;
		if(IMM16[15]==1'b1) result = {{16{IMM16[15]}}, IMM16};;
end

endmodule