data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_clock.v
 line:33: before: "FDDRRSE"
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_clock.v:57: Cannot find file containing module: 'FDDRRSE'\nFDDRRSE fddr_ck_n (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/FDDRRSE\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/FDDRRSE.v\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/FDDRRSE.sv\n             FDDRRSE\n             FDDRRSE.v\n             FDDRRSE.sv\n             obj_dir/FDDRRSE\n             obj_dir/FDDRRSE.v\n             obj_dir/FDDRRSE.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_clock.v:68: Cannot find file containing module: 'FDDRRSE'\nFDDRRSE fddr_ck (\n^~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_clock.v:79: Cannot find file containing module: 'OBUF'\nOBUF ck_obuf ( .I (ddr_ck_w), .O (ddr_ck_o));\n^~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_clock.v:80: Cannot find file containing module: 'OBUF'\nOBUF ckn_obuf ( .I (ddr_ck_nw), .O (ddr_ck_no));\n^~~~\n%Error: Exiting due to 4 error(s)\n"
module iobs_clock (
	clock_i,
	reset_ni,
	
	enable_i,
	
	ddr_cke_o,
	ddr_ck_o,
	ddr_ck_no
);

input	clock_i;
input	reset_ni;

input	enable_i;

output	ddr_cke_o;
output	ddr_ck_o;
output	ddr_ck_no;


wire	ddr_ck_w;
wire	ddr_ck_nw;


reg	ddr_cke_o	= 0;


always @(posedge clock_i)
	ddr_cke_o	<= enable_i;


FDDRRSE fddr_ck_n (
	.Q	(ddr_ck_w),
	.C0	(clock_i),
	.C1	(~clock_i),
	.CE	(1'b1),
	.D0	(0),
	.D1	(1),
	.R	(!reset_ni),
	.S	(0)
);

FDDRRSE fddr_ck (
	.Q	(ddr_ck_nw),
	.C0	(clock_i),
	.C1	(~clock_i),
	.CE	(1'b1),
	.D0	(1),
	.D1	(0),
	.R	(0),
	.S	(!reset_ni)
);

OBUF ck_obuf	( .I (ddr_ck_w), .O (ddr_ck_o));
OBUF ckn_obuf	( .I (ddr_ck_nw), .O (ddr_ck_no));


endmodule
module iobs_clock (
	clock_i,
	reset_ni,
	
	enable_i,
	
	ddr_cke_o,
	ddr_ck_o,
	ddr_ck_no
);


input	clock_i;
input	reset_ni;

input	enable_i;

output	ddr_cke_o;
output	ddr_ck_o;
output	ddr_ck_no;


wire	ddr_ck_w;
wire	ddr_ck_nw;


reg	ddr_cke_o	= 0;


always @(posedge clock_i)
	ddr_cke_o	<= enable_i;


FDDRRSE fddr_ck_n (
	.Q	(ddr_ck_w),
	.C0	(clock_i),
	.C1	(~clock_i),
	.CE	(1'b1),
	.D0	(0),
	.D1	(1),
	.R	(!reset_ni),
	.S	(0)
);

FDDRRSE fddr_ck (
	.Q	(ddr_ck_nw),
	.C0	(clock_i),
	.C1	(~clock_i),
	.CE	(1'b1),
	.D0	(1),
	.D1	(0),
	.R	(0),
	.S	(!reset_ni)
);

OBUF ck_obuf	( .I (ddr_ck_w), .O (ddr_ck_o));
OBUF ckn_obuf	( .I (ddr_ck_nw), .O (ddr_ck_no));


endmodule