data/full_repos/permissive/194847941/demo/4_Running_LED/sources/rtl/running_led.v
'utf-8' codec can't decode byte 0xc1 in position 266: invalid start byte
1: b"%Error: data/full_repos/permissive/194847941/demo/4_Running_LED/sources/rtl/running_led.v:31: Cannot find file containing module: 'rst_n'\nrst_n ux_rst_n\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/4_Running_LED/sources/rtl,data/full_repos/permissive/194847941/rst_n\n             data/full_repos/permissive/194847941/demo/4_Running_LED/sources/rtl,data/full_repos/permissive/194847941/rst_n.v\n             data/full_repos/permissive/194847941/demo/4_Running_LED/sources/rtl,data/full_repos/permissive/194847941/rst_n.sv\n             rst_n\n             rst_n.v\n             rst_n.sv\n             obj_dir/rst_n\n             obj_dir/rst_n.v\n             obj_dir/rst_n.sv\n%Error: Exiting due to 1 error(s)\n"
module running_led
( 
	input	wire 		clk_24m,
	output  reg [15:0] 	led
);

wire rst_n;

parameter CNT = 25'd12000_000;

initial
begin
	cnt_time = 0;
	flag = 0;
	led = 0;
end

rst_n ux_rst_n
(
	.clk	(clk_24m	),
	.rst_n	(rst_n		)
);

reg [24:0] cnt_time;
reg flag;


always @(posedge clk_24m)
begin 
	if(cnt_time == CNT - 1) 
		cnt_time <= 0; 
	else 
		cnt_time <= cnt_time + 1'b1; 
end

always @(posedge clk_24m)
begin
	if(!led[0])
		flag <= 0;
	else if(!led[15])
		flag <= 1;
	else
		flag <= flag;
end













always @(posedge clk_24m)
begin
	if(led == 0) 
		led <= 16'hfffe; 
	else if(cnt_time == CNT - 1)
	begin
		if(!flag)
			led <= {led[14:0],led[15]};
		else
			led <= {led[0],led[15:1]};
	end
	else
		led <= led;
end


endmodule
module running_led
( 
	input	wire 		clk_24m,
	output  reg [15:0] 	led
);


wire rst_n;

parameter CNT = 25'd12000_000;

initial
begin
	cnt_time = 0;
	flag = 0;
	led = 0;
end

rst_n ux_rst_n
(
	.clk	(clk_24m	),
	.rst_n	(rst_n		)
);

reg [24:0] cnt_time;
reg flag;


always @(posedge clk_24m)
begin 
	if(cnt_time == CNT - 1) 
		cnt_time <= 0; 
	else 
		cnt_time <= cnt_time + 1'b1; 
end

always @(posedge clk_24m)
begin
	if(!led[0])
		flag <= 0;
	else if(!led[15])
		flag <= 1;
	else
		flag <= flag;
end













always @(posedge clk_24m)
begin
	if(led == 0) 
		led <= 16'hfffe; 
	else if(cnt_time == CNT - 1)
	begin
		if(!flag)
			led <= {led[14:0],led[15]};
		else
			led <= {led[0],led[15:1]};
	end
	else
		led <= led;
end


endmodule