data/full_repos/permissive/156609923/FSM_Control/probador.v
 line:66: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/156609923/FSM_Control/probador.v:21: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk; \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/156609923/FSM_Control/probador.v:25: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("fsmControl.vcd");  \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/FSM_Control/probador.v:26: Unsupported or unknown PLI call: $dumpvars\n       $dumpvars(0,testbench);   \n       ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/FSM_Control/probador.v:37: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/156609923/FSM_Control/probador.v:40: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/156609923/FSM_Control/probador.v:44: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/156609923/FSM_Control/probador.v:48: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/FSM_Control/probador.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #4 reset_L <= 1;\n    ^\n%Error: data/full_repos/permissive/156609923/FSM_Control/probador.v:54: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/156609923/FSM_Control/probador.v:59: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/FSM_Control/probador.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #4 FIFO_empty <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/FSM_Control/probador.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #20 $finish;\n    ^\n%Error: Exiting due to 8 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador (	input [7:0] umbrales_VCFC_condu,
			input 	   active_condu,
			input 	   idle_condu,
			input 	   error_condu, 
			input [7:0] umbrales_VCFC_estru,
			input 	   active_estru,
			input 	   idle_estru,
			input 	   error_estru, 
			output reg clk,
			output reg reset_L,
			output reg init,
			output reg [7:0] umbral_VCFC,
			output reg FIFO_error,
			output reg FIFO_empty);

   


	initial clk <= 0;
	always #1 clk = ~clk;	

	initial 
	begin
		$dumpfile("fsmControl.vcd");
     		$dumpvars(0,testbench);


	   reset_L <= 0;
	   init<=0;
	   umbral_VCFC<=8'b00000000;
	   FIFO_error<=0;
	   FIFO_empty <= 0;
 


	   @(posedge clk);
	   reset_L <= 1;
	   
	   @(posedge clk);
	   init <= 1;

	   
	   @(posedge clk);
	   FIFO_error <= 1;
	   init <= 0;

	   @(posedge clk);
	   reset_L <= 0;
	   FIFO_error <= 0;

	   #4 reset_L <= 1;
	
	   @(posedge clk);
	   init <= 1;
	   umbral_VCFC<=8'b10101111;
	   FIFO_empty <= 1;

	   @(posedge clk);
	   init <= 0;

	   #4 FIFO_empty <= 0;
  
	   
	   
	   #20 $finish;
	   
	end

endmodule
module probador (	input [7:0] umbrales_VCFC_condu,
			input 	   active_condu,
			input 	   idle_condu,
			input 	   error_condu, 
			input [7:0] umbrales_VCFC_estru,
			input 	   active_estru,
			input 	   idle_estru,
			input 	   error_estru, 
			output reg clk,
			output reg reset_L,
			output reg init,
			output reg [7:0] umbral_VCFC,
			output reg FIFO_error,
			output reg FIFO_empty);


   


	initial clk <= 0;
	always #1 clk = ~clk;	

	initial 
	begin
		$dumpfile("fsmControl.vcd");
     		$dumpvars(0,testbench);


	   reset_L <= 0;
	   init<=0;
	   umbral_VCFC<=8'b00000000;
	   FIFO_error<=0;
	   FIFO_empty <= 0;
 


	   @(posedge clk);
	   reset_L <= 1;
	   
	   @(posedge clk);
	   init <= 1;

	   
	   @(posedge clk);
	   FIFO_error <= 1;
	   init <= 0;

	   @(posedge clk);
	   reset_L <= 0;
	   FIFO_error <= 0;

	   #4 reset_L <= 1;
	
	   @(posedge clk);
	   init <= 1;
	   umbral_VCFC<=8'b10101111;
	   FIFO_empty <= 1;

	   @(posedge clk);
	   init <= 0;

	   #4 FIFO_empty <= 0;
  
	   
	   
	   #20 $finish;
	   
	end

endmodule