data/full_repos/permissive/193530477/source codes/sigkeyscan.v
1: b'%Error: Cannot find file containing module: codes,data/full_repos/permissive/193530477\n        ... Looked in:\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.v\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.sv\n             codes,data/full_repos/permissive/193530477\n             codes,data/full_repos/permissive/193530477.v\n             codes,data/full_repos/permissive/193530477.sv\n             obj_dir/codes,data/full_repos/permissive/193530477\n             obj_dir/codes,data/full_repos/permissive/193530477.v\n             obj_dir/codes,data/full_repos/permissive/193530477.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/193530477/source\n%Error: Cannot find file containing module: codes/sigkeyscan.v\n%Error: Exiting due to 3 error(s)\n'
module sigkeyscan(
			input clk,
			input rst_n,
			input[3:0] key_v,
			output[3:0] keyv_value,
			output key_neg,
			output key_pos
    		);



wire key;
reg[3:0] keyr;

assign key = key_v[0] & key_v[1] & key_v[2] & key_v[3];

always @(posedge clk or negedge rst_n)
    if (!rst_n) keyr <= 4'b1111;
    else keyr <= {keyr[2:0],key};

assign key_neg = ~keyr[2] & keyr[3];
assign key_pos = keyr[2] & ~keyr[3];



reg[19:0]  cnt;	


always @ (posedge clk or negedge rst_n)
   if (!rst_n) cnt <= 20'd0;	
	else if(key_pos || key_neg) cnt <= 20'd0;
	else if(cnt < 20'd999_999) cnt <= cnt + 1'b1;
	else cnt <= 20'd0;
  
reg[3:0] key_value[1:0];


always @(posedge clk or negedge rst_n)
    if (!rst_n) begin
		key_value[0] <= 4'b1111;
		key_value[1] <= 4'b1111;
	end
	else begin 
		key_value[1] <= key_value[0];		
		if(cnt == 20'd999_999) key_value[0] <= key_v;
		else ;	
	end

assign keyv_value = key_value[1] & ~key_value[0];

  
endmodule
module sigkeyscan(
			input clk,
			input rst_n,
			input[3:0] key_v,
			output[3:0] keyv_value,
			output key_neg,
			output key_pos
    		);




wire key;
reg[3:0] keyr;

assign key = key_v[0] & key_v[1] & key_v[2] & key_v[3];

always @(posedge clk or negedge rst_n)
    if (!rst_n) keyr <= 4'b1111;
    else keyr <= {keyr[2:0],key};

assign key_neg = ~keyr[2] & keyr[3];
assign key_pos = keyr[2] & ~keyr[3];



reg[19:0]  cnt;	


always @ (posedge clk or negedge rst_n)
   if (!rst_n) cnt <= 20'd0;	
	else if(key_pos || key_neg) cnt <= 20'd0;
	else if(cnt < 20'd999_999) cnt <= cnt + 1'b1;
	else cnt <= 20'd0;
  
reg[3:0] key_value[1:0];


always @(posedge clk or negedge rst_n)
    if (!rst_n) begin
		key_value[0] <= 4'b1111;
		key_value[1] <= 4'b1111;
	end
	else begin 
		key_value[1] <= key_value[0];		
		if(cnt == 20'd999_999) key_value[0] <= key_v;
		else ;	
	end

assign keyv_value = key_value[1] & ~key_value[0];

  
endmodule