data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v
None: at end of input
1: b'%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:2: Cannot find include file: common.h\n`include "common.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src,data/full_repos/permissive/191476706/common.h\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src,data/full_repos/permissive/191476706/common.h.v\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src,data/full_repos/permissive/191476706/common.h.sv\n             common.h\n             common.h.v\n             common.h.sv\n             obj_dir/common.h\n             obj_dir/common.h.v\n             obj_dir/common.h.sv\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:23: Define or directive not defined: \'`BW_DATA_IN\'\nparameter BW_DATA_IN = `BW_DATA_IN;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:23: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DATA_IN = `BW_DATA_IN;\n                                  ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:25: Define or directive not defined: \'`BW_DIM_IN\'\nparameter BW_DIM_IN = `BW_DIM_IN;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:25: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DIM_IN = `BW_DIM_IN;\n                                ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:26: Define or directive not defined: \'`BW_DIM_EMB\'\nparameter BW_DIM_EMB = `BW_DIM_EMB;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:26: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DIM_EMB = `BW_DIM_EMB;\n                                  ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:28: Define or directive not defined: \'`BW_DIM_IN\'\nparameter DIM_IN = `BW_DIM_IN;\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:28: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter DIM_IN = `BW_DIM_IN;\n                             ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:31: Define or directive not defined: \'`BW_DATA_EMB_W\'\nparameter BW_DATA = `BW_DATA_EMB_W;\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:31: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DATA = `BW_DATA_EMB_W;\n                                  ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:32: Define or directive not defined: \'`CLOG2\'\nparameter BW_ADDR = `CLOG2(BW_DIM_IN);         \n                    ^~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:34: Define or directive not defined: \'`NUM_MEM\'\nparameter NUM_MEM = `NUM_MEM;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:34: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter NUM_MEM = `NUM_MEM;\n                            ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:36: Define or directive not defined: \'`BW_DATA_EMB_W\'\nparameter BW_DATA_EMB_W = `BW_DATA_EMB_W;\n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DATA_EMB_W = `BW_DATA_EMB_W;\n                                        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:38: Define or directive not defined: \'`BW_WORD_VEC\'\nparameter BW_WORD_VEC = `BW_WORD_VEC;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:38: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_WORD_VEC = `BW_WORD_VEC;\n                                    ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:40: Define or directive not defined: \'`NUM_ITR\'\nparameter NUM_ITR = `NUM_ITR;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/imports/xillybus-eval-virtexultrascale-1.2c_160815/verilog/src/xillydemo.v:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter NUM_ITR = `NUM_ITR;\n                            ^\n%Error: Exiting due to 20 error(s)\n'
module xillydemo
(
    clk_sys_in1_p,
    clk_sys_in1_n,
    rst_sys,
    rst_button,
    en_init_sys,
    PCIE_PERST_B_LS,
    PCIE_REFCLK_N,
    PCIE_REFCLK_P,
    PCIE_RX_N,
    PCIE_RX_P,
    GPIO_LED,
    PCIE_TX_N,
    PCIE_TX_P
);


parameter BW_DATA_IN = `BW_DATA_IN;

parameter BW_DIM_IN = `BW_DIM_IN;
parameter BW_DIM_EMB = `BW_DIM_EMB;

parameter DIM_IN = `BW_DIM_IN;
parameter DIM_EMB = 1<<BW_DIM_EMB;

parameter BW_DATA = `BW_DATA_EMB_W;
parameter BW_ADDR = `CLOG2(BW_DIM_IN);

parameter NUM_MEM = `NUM_MEM;

parameter BW_DATA_EMB_W = `BW_DATA_EMB_W;

parameter BW_WORD_VEC = `BW_WORD_VEC;

parameter NUM_ITR = `NUM_ITR;

parameter MAX_TEST_INPUT = 500000;



input wire clk_sys_in1_p;
input wire clk_sys_in1_n;
input wire rst_sys;
input wire rst_button;
input wire en_init_sys;


input wire PCIE_PERST_B_LS;
input wire PCIE_REFCLK_N;
input wire PCIE_REFCLK_P;
input wire [7:0] PCIE_RX_N;
input wire [7:0] PCIE_RX_P;
output wire [7:0] GPIO_LED;
output wire [7:0] PCIE_TX_N;
output wire [7:0] PCIE_TX_P;



wire  clk_pcie;
wire  quiesce;






wire  user_r_read_16_rden;
wire  user_r_read_16_empty;
wire [15:0] user_r_read_16_data;
wire  user_r_read_16_eof;
(* DONT_TOUCH="yes" *) wire  user_r_read_16_open;
wire user_r_read_16_val;









wire  user_w_write_16_wren;
wire  user_w_write_16_full;
wire [15:0] user_w_write_16_data;
(* DONT_TOUCH="yes" *) wire  user_w_write_16_open;








wire [16-1:0] user_w_write_16_data_fifo_in;
wire [16-1:0] user_r_read_16_data_fifo_in;
wire user_w_write_16_wren_fifo_in;
wire user_r_read_16_rden_fifo_in;
wire user_w_write_16_full_fifo_in;
wire user_r_read_16_empty_fifo_in;
wire user_r_read_16_val_fifo_in;

wire [16-1:0] user_w_write_16_data_fifo_out;
wire [16-1:0] user_r_read_16_data_fifo_out;
wire user_w_write_16_wren_fifo_out;
wire user_r_read_16_rden_fifo_out;
wire user_w_write_16_full_fifo_out;
wire user_r_read_16_empty_fifo_out;
wire user_r_read_16_val_fifo_out;









wire clk;
wire rst_n;
wire en;
wire en_init;

wire [BW_DATA_IN-1:0] data_in;

wire rb_n_debug;
wire [BW_DATA_IN-1:0] data_out;








wire done_init;
wire done_init_memn2n;
wire done_memn2n;



wire en_init_memn2n;


assign en_init_memn2n = en_init_sys;


wire rst_memn2n;






assign rst_memn2n = rst_sys || rst_button;
























(* DONT_TOUCH="yes" *)
xillybus xillybus_ins (



  


    .user_r_read_16_rden(user_r_read_16_rden),
    .user_r_read_16_empty(user_r_read_16_empty),
    .user_r_read_16_data(user_r_read_16_data),
    .user_r_read_16_eof(user_r_read_16_eof),
    .user_r_read_16_open(user_r_read_16_open),
  
  


  



  
  


    .user_w_write_16_wren(user_w_write_16_wren),
    .user_w_write_16_full(user_w_write_16_full),
    .user_w_write_16_data(user_w_write_16_data),
    .user_w_write_16_open(user_w_write_16_open),
  
  


  
  



  
  

    .PCIE_PERST_B_LS(PCIE_PERST_B_LS),
    .PCIE_REFCLK_N(PCIE_REFCLK_N),
    .PCIE_REFCLK_P(PCIE_REFCLK_P),
    .PCIE_RX_N(PCIE_RX_N),
    .PCIE_RX_P(PCIE_RX_P),
    .GPIO_LED(GPIO_LED[3:0]),
    .PCIE_TX_N(PCIE_TX_N),
    .PCIE_TX_P(PCIE_TX_P),
    .bus_clk(clk_pcie),
    .quiesce(quiesce)
);













(* DONT_TOUCH="yes" *) reg rst_fifo_in;
(* DONT_TOUCH="yes" *) reg rst_fifo_in_meta;

always@(posedge clk_pcie)
begin


    rst_fifo_in_meta <= !user_w_write_16_open;
end

always@(posedge clk_pcie)
begin
    rst_fifo_in <= rst_fifo_in_meta;
end


(* DONT_TOUCH="yes" *) reg rst_fifo_out;
(* DONT_TOUCH="yes" *) reg rst_fifo_out_meta;


always@(posedge clk)
begin
    rst_fifo_out_meta <= !user_w_write_16_open;


end

always@(posedge clk)
begin
    rst_fifo_out <= rst_fifo_out_meta;
end





assign user_w_write_16_data_fifo_in = user_w_write_16_data;
assign user_w_write_16_wren_fifo_in = user_w_write_16_wren;
assign user_w_write_16_full = user_w_write_16_full_fifo_in;


assign user_r_read_16_rden_fifo_out = user_r_read_16_rden;
assign user_r_read_16_data = user_r_read_16_data_fifo_out;
assign user_r_read_16_empty = user_r_read_16_empty_fifo_out;




fifo_host_to_fpga_16x1024
fifo_in_16
(



    .srst(rst_fifo_in),
    .wr_clk(clk_pcie),
    .rd_clk(clk),
    .din(user_w_write_16_data_fifo_in),
    .wr_en(user_w_write_16_wren_fifo_in),
    .rd_en(user_r_read_16_rden_fifo_in),
    .dout(user_r_read_16_data_fifo_in),
    .full(user_w_write_16_full_fifo_in),
    .empty(user_r_read_16_empty_fifo_in),
    .valid(user_r_read_16_val_fifo_in)
);

fifo_fpga_to_host_16x1024
fifo_out_16
(



    .srst(rst_fifo_out),
    .wr_clk(clk),
    .rd_clk(clk_pcie),
    .din(user_w_write_16_data_fifo_out),
    .wr_en(user_w_write_16_wren_fifo_out),
    .rd_en(user_r_read_16_rden_fifo_out),
    .dout(user_r_read_16_data_fifo_out),
    .full(user_w_write_16_full_fifo_out),
    .empty(user_r_read_16_empty_fifo_out),
    .valid(user_r_read_16_val_fifo_out)
);

memory_network_top
memory_network_top_module
(

    .clk(clk),

    .rst_sys(rst_memn2n),

    .en_init_sys(en_init_memn2n),


    .empty_fifo_in(user_r_read_16_empty_fifo_in),
    .valid_fifo_in(user_r_read_16_val_fifo_in),
    .valid_fifo_out(user_r_read_16_val_fifo_out),
    .dout_fifo_in(user_r_read_16_data_fifo_in),
    .done_init_memory_network(1'b1),




    .rd_en_fifo_in(user_r_read_16_rden_fifo_in),
    .wr_en_fifo_out(user_w_write_16_wren_fifo_out),
    .din_fifo_out(user_w_write_16_data_fifo_out),
    .rb_n_debug(rb_n_debug)

);







clk_wiz_0
clk_wiz_sys_clk
(

    .clk_in1_p(clk_sys_in1_p),
    .clk_in1_n(clk_sys_in1_n),

    .clk_out1(clk),

    .resetn(!(rst_sys||rst_button))

);

`ifdef DEBUG



`endif


endmodule
module xillydemo
(
    clk_sys_in1_p,
    clk_sys_in1_n,
    rst_sys,
    rst_button,
    en_init_sys,
    PCIE_PERST_B_LS,
    PCIE_REFCLK_N,
    PCIE_REFCLK_P,
    PCIE_RX_N,
    PCIE_RX_P,
    GPIO_LED,
    PCIE_TX_N,
    PCIE_TX_P
);



parameter BW_DATA_IN = `BW_DATA_IN;

parameter BW_DIM_IN = `BW_DIM_IN;
parameter BW_DIM_EMB = `BW_DIM_EMB;

parameter DIM_IN = `BW_DIM_IN;
parameter DIM_EMB = 1<<BW_DIM_EMB;

parameter BW_DATA = `BW_DATA_EMB_W;
parameter BW_ADDR = `CLOG2(BW_DIM_IN);

parameter NUM_MEM = `NUM_MEM;

parameter BW_DATA_EMB_W = `BW_DATA_EMB_W;

parameter BW_WORD_VEC = `BW_WORD_VEC;

parameter NUM_ITR = `NUM_ITR;

parameter MAX_TEST_INPUT = 500000;



input wire clk_sys_in1_p;
input wire clk_sys_in1_n;
input wire rst_sys;
input wire rst_button;
input wire en_init_sys;


input wire PCIE_PERST_B_LS;
input wire PCIE_REFCLK_N;
input wire PCIE_REFCLK_P;
input wire [7:0] PCIE_RX_N;
input wire [7:0] PCIE_RX_P;
output wire [7:0] GPIO_LED;
output wire [7:0] PCIE_TX_N;
output wire [7:0] PCIE_TX_P;



wire  clk_pcie;
wire  quiesce;






wire  user_r_read_16_rden;
wire  user_r_read_16_empty;
wire [15:0] user_r_read_16_data;
wire  user_r_read_16_eof;
(* DONT_TOUCH="yes" *) wire  user_r_read_16_open;
wire user_r_read_16_val;









wire  user_w_write_16_wren;
wire  user_w_write_16_full;
wire [15:0] user_w_write_16_data;
(* DONT_TOUCH="yes" *) wire  user_w_write_16_open;








wire [16-1:0] user_w_write_16_data_fifo_in;
wire [16-1:0] user_r_read_16_data_fifo_in;
wire user_w_write_16_wren_fifo_in;
wire user_r_read_16_rden_fifo_in;
wire user_w_write_16_full_fifo_in;
wire user_r_read_16_empty_fifo_in;
wire user_r_read_16_val_fifo_in;

wire [16-1:0] user_w_write_16_data_fifo_out;
wire [16-1:0] user_r_read_16_data_fifo_out;
wire user_w_write_16_wren_fifo_out;
wire user_r_read_16_rden_fifo_out;
wire user_w_write_16_full_fifo_out;
wire user_r_read_16_empty_fifo_out;
wire user_r_read_16_val_fifo_out;









wire clk;
wire rst_n;
wire en;
wire en_init;

wire [BW_DATA_IN-1:0] data_in;

wire rb_n_debug;
wire [BW_DATA_IN-1:0] data_out;








wire done_init;
wire done_init_memn2n;
wire done_memn2n;



wire en_init_memn2n;


assign en_init_memn2n = en_init_sys;


wire rst_memn2n;






assign rst_memn2n = rst_sys || rst_button;
























(* DONT_TOUCH="yes" *)
xillybus xillybus_ins (



  


    .user_r_read_16_rden(user_r_read_16_rden),
    .user_r_read_16_empty(user_r_read_16_empty),
    .user_r_read_16_data(user_r_read_16_data),
    .user_r_read_16_eof(user_r_read_16_eof),
    .user_r_read_16_open(user_r_read_16_open),
  
  


  



  
  


    .user_w_write_16_wren(user_w_write_16_wren),
    .user_w_write_16_full(user_w_write_16_full),
    .user_w_write_16_data(user_w_write_16_data),
    .user_w_write_16_open(user_w_write_16_open),
  
  


  
  



  
  

    .PCIE_PERST_B_LS(PCIE_PERST_B_LS),
    .PCIE_REFCLK_N(PCIE_REFCLK_N),
    .PCIE_REFCLK_P(PCIE_REFCLK_P),
    .PCIE_RX_N(PCIE_RX_N),
    .PCIE_RX_P(PCIE_RX_P),
    .GPIO_LED(GPIO_LED[3:0]),
    .PCIE_TX_N(PCIE_TX_N),
    .PCIE_TX_P(PCIE_TX_P),
    .bus_clk(clk_pcie),
    .quiesce(quiesce)
);













(* DONT_TOUCH="yes" *) reg rst_fifo_in;
(* DONT_TOUCH="yes" *) reg rst_fifo_in_meta;

always@(posedge clk_pcie)
begin


    rst_fifo_in_meta <= !user_w_write_16_open;
end

always@(posedge clk_pcie)
begin
    rst_fifo_in <= rst_fifo_in_meta;
end


(* DONT_TOUCH="yes" *) reg rst_fifo_out;
(* DONT_TOUCH="yes" *) reg rst_fifo_out_meta;


always@(posedge clk)
begin
    rst_fifo_out_meta <= !user_w_write_16_open;


end

always@(posedge clk)
begin
    rst_fifo_out <= rst_fifo_out_meta;
end





assign user_w_write_16_data_fifo_in = user_w_write_16_data;
assign user_w_write_16_wren_fifo_in = user_w_write_16_wren;
assign user_w_write_16_full = user_w_write_16_full_fifo_in;


assign user_r_read_16_rden_fifo_out = user_r_read_16_rden;
assign user_r_read_16_data = user_r_read_16_data_fifo_out;
assign user_r_read_16_empty = user_r_read_16_empty_fifo_out;




fifo_host_to_fpga_16x1024
fifo_in_16
(



    .srst(rst_fifo_in),
    .wr_clk(clk_pcie),
    .rd_clk(clk),
    .din(user_w_write_16_data_fifo_in),
    .wr_en(user_w_write_16_wren_fifo_in),
    .rd_en(user_r_read_16_rden_fifo_in),
    .dout(user_r_read_16_data_fifo_in),
    .full(user_w_write_16_full_fifo_in),
    .empty(user_r_read_16_empty_fifo_in),
    .valid(user_r_read_16_val_fifo_in)
);

fifo_fpga_to_host_16x1024
fifo_out_16
(



    .srst(rst_fifo_out),
    .wr_clk(clk),
    .rd_clk(clk_pcie),
    .din(user_w_write_16_data_fifo_out),
    .wr_en(user_w_write_16_wren_fifo_out),
    .rd_en(user_r_read_16_rden_fifo_out),
    .dout(user_r_read_16_data_fifo_out),
    .full(user_w_write_16_full_fifo_out),
    .empty(user_r_read_16_empty_fifo_out),
    .valid(user_r_read_16_val_fifo_out)
);

memory_network_top
memory_network_top_module
(

    .clk(clk),

    .rst_sys(rst_memn2n),

    .en_init_sys(en_init_memn2n),


    .empty_fifo_in(user_r_read_16_empty_fifo_in),
    .valid_fifo_in(user_r_read_16_val_fifo_in),
    .valid_fifo_out(user_r_read_16_val_fifo_out),
    .dout_fifo_in(user_r_read_16_data_fifo_in),
    .done_init_memory_network(1'b1),




    .rd_en_fifo_in(user_r_read_16_rden_fifo_in),
    .wr_en_fifo_out(user_w_write_16_wren_fifo_out),
    .din_fifo_out(user_w_write_16_data_fifo_out),
    .rb_n_debug(rb_n_debug)

);







clk_wiz_0
clk_wiz_sys_clk
(

    .clk_in1_p(clk_sys_in1_p),
    .clk_in1_n(clk_sys_in1_n),

    .clk_out1(clk),

    .resetn(!(rst_sys||rst_button))

);

`ifdef DEBUG



`endif


endmodule