data/full_repos/permissive/207111076/jt51/jt51_sh.v
data/verilator_xmls/1b1d14b9-8e89-4bbb-a965-b9a3da34cda3.xml
module jt51_sh #(parameter width=5, stages=32 )
(
	input 							clk,
	input		[width-1:0]			din,
   	output		[width-1:0]			drop
);

reg [stages-1:0] bits[width-1:0];

genvar i;
generate
	for (i=0; i < width; i=i+1) begin: bit_shifter
		always @(posedge clk)
			bits[i] <= {bits[i][stages-2:0], din[i]};
		assign drop[i] = bits[i][stages-1];
	end
endgenerate

endmodule
module jt51_sh #(parameter width=5, stages=32 )
(
	input 							clk,
	input		[width-1:0]			din,
   	output		[width-1:0]			drop
);


reg [stages-1:0] bits[width-1:0];

genvar i;
generate
	for (i=0; i < width; i=i+1) begin: bit_shifter
		always @(posedge clk)
			bits[i] <= {bits[i][stages-2:0], din[i]};
		assign drop[i] = bits[i][stages-1];
	end
endgenerate

endmodule