data/full_repos/permissive/116468596/count4.v
1: b"%Error: data/full_repos/permissive/116468596/count4.v:33: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(eightSec), .CE(enable), .D(inD0), .Q(outQ[0]));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n             FDRE\n             FDRE.v\n             FDRE.sv\n             obj_dir/FDRE\n             obj_dir/FDRE.v\n             obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/count4.v:34: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(eightSec), .CE(enable), .D(inD1), .Q(outQ[1]));\n    ^~~~\n%Error: data/full_repos/permissive/116468596/count4.v:35: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(eightSec), .CE(enable), .D(inD2), .Q(outQ[2]));\n    ^~~~\n%Error: data/full_repos/permissive/116468596/count4.v:36: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(eightSec), .CE(enable), .D(inD3), .Q(outQ[3]));\n    ^~~~\n%Error: Exiting due to 4 error(s)\n"
module count4(
input clk, enable,
    output eightSec
    );
    wire [3:0] outQ;
    wire inD0 = enable ^ outQ[0];
    wire inD1 = (enable & outQ[0]) ^ outQ[1];
    wire inD2 = (enable & outQ[0] & outQ[1]) ^ outQ[2];
    wire inD3 = (enable & outQ[0] & outQ[1] & outQ[2]) ^ outQ[3];

    FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(eightSec), .CE(enable), .D(inD0), .Q(outQ[0]));
    FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(eightSec), .CE(enable), .D(inD1), .Q(outQ[1]));
    FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(eightSec), .CE(enable), .D(inD2), .Q(outQ[2]));
    FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(eightSec), .CE(enable), .D(inD3), .Q(outQ[3]));

   
    assign eightSec = ( ~outQ[0] & ~outQ[1] & ~outQ[2] & outQ[3] );   
    
endmodule
module count4(
input clk, enable,
    output eightSec
    );

    wire [3:0] outQ;
    wire inD0 = enable ^ outQ[0];
    wire inD1 = (enable & outQ[0]) ^ outQ[1];
    wire inD2 = (enable & outQ[0] & outQ[1]) ^ outQ[2];
    wire inD3 = (enable & outQ[0] & outQ[1] & outQ[2]) ^ outQ[3];

    FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(eightSec), .CE(enable), .D(inD0), .Q(outQ[0]));
    FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(eightSec), .CE(enable), .D(inD1), .Q(outQ[1]));
    FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(eightSec), .CE(enable), .D(inD2), .Q(outQ[2]));
    FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(eightSec), .CE(enable), .D(inD3), .Q(outQ[3]));

   
    assign eightSec = ( ~outQ[0] & ~outQ[1] & ~outQ[2] & outQ[3] );   
    
endmodule