data/full_repos/permissive/168453867/rtl/LASER310_TOP.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:1194: Signal definition not found, creating implicitly: \'AUD_CTRL_CLK\'\nassign AUD_XCK = AUD_CTRL_CLK;\n                 ^~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:243: Cannot find file containing module: \'CLK10MHZ_PLL\'\nCLK10MHZ_PLL CLK10MHZ_PLL_INST(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/168453867/rtl,data/full_repos/permissive/168453867/CLK10MHZ_PLL\n             data/full_repos/permissive/168453867/rtl,data/full_repos/permissive/168453867/CLK10MHZ_PLL.v\n             data/full_repos/permissive/168453867/rtl,data/full_repos/permissive/168453867/CLK10MHZ_PLL.sv\n             CLK10MHZ_PLL\n             CLK10MHZ_PLL.v\n             CLK10MHZ_PLL.sv\n             obj_dir/CLK10MHZ_PLL\n             obj_dir/CLK10MHZ_PLL.v\n             obj_dir/CLK10MHZ_PLL.sv\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:424: Cannot find file containing module: \'RESET_DE\'\nRESET_DE RESET_DE(\n^~~~~~~~\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:454: Cannot find file containing module: \'VGA_Audio_PLL\'\nVGA_Audio_PLL  VGA_AUDIO_PLL(.inclk0(CLK27MHZ),.c0(VGA_CLK),.c1(AUD_CTRL_CLK));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:661: Cannot find file containing module: \'tv80s\'\ntv80s Z80CPU (\n^~~~~\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:757: Cannot find file containing module: \'sys_rom_altera\'\nsys_rom_altera sys_rom(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:792: Cannot find file containing module: \'ram_2k_altera\'\nram_2k_altera sys_ram_78(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:800: Cannot find file containing module: \'ram_2k_altera\'\nram_2k_altera sys_ram_80(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:844: Cannot find file containing module: \'vram_altera\'\nvram_altera vram_2k(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:863: Cannot find file containing module: \'MC6847_VGA\'\nMC6847_VGA MC6847_VGA(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:1152: Cannot find file containing module: \'ps2_keyboard\'\nps2_keyboard KEYBOARD(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:1167: Cannot find file containing module: \'AUDIO_IF\'\nAUDIO_IF AUD_IF(\n^~~~~~~~\n%Error: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:1185: Cannot find file containing module: \'I2C_AV_Config\'\nI2C_AV_Config AUD_I2C(\n^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/168453867/rtl/LASER310_TOP.v:1221: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                            : ... In instance LASER310_TOP\nassign LED = {4\'b0, CASS_IN, CASS_IN_L, CASS_IN_R, CASS_OUT, A_KEY_PRESSED, CPU_RESET};\n           ^\n%Error: Exiting due to 12 error(s), 2 warning(s)\n'
module LASER310_TOP(
	CLK50MHZ,

`ifdef CLOCK_27MHZ
	CLK27MHZ,
`endif


`ifdef VGA_RESISTOR
	VGA_RED,
	VGA_GREEN,
	VGA_BLUE,
	VGA_HS,
	VGA_VS,
`endif

`ifdef VGA_ADV7123
	VGA_DAC_RED,
	VGA_DAC_GREEN,
	VGA_DAC_BLUE,
	VGA_HS,
	VGA_VS,
	VGA_DAC_BLANK_N,
	VGA_DAC_SYNC_N,
	VGA_DAC_CLOCK,
`endif


	PS2_KBCLK,
	PS2_KBDAT,

	LED,

`ifdef AUDIO_WM8731

	AUD_ADCLRCK,
	AUD_ADCDAT,
	AUD_DACLRCK,
	AUD_DACDAT,
	AUD_BCLK,
	AUD_XCK,


	I2C_SDAT,
	I2C_SCLK,

`endif

`ifdef GPIO_PIN



`endif

	BUTTON_N
);


input				CLK50MHZ;

`ifdef CLOCK_27MHZ
input				CLK27MHZ;
`endif


`ifdef VGA_RESISTOR

`ifdef VGA_BIT12
output	wire	[3:0]	VGA_RED;
output	wire	[3:0]	VGA_GREEN;
output	wire	[3:0]	VGA_BLUE;
`endif

output	wire			VGA_HS;
output	wire			VGA_VS;
`endif


`ifdef VGA_ADV7123

`ifdef VGA_BIT30
output	wire	[9:0]	VGA_DAC_RED;
output	wire	[9:0]	VGA_DAC_GREEN;
output	wire	[9:0]	VGA_DAC_BLUE;
`endif

`ifdef VGA_BIT24
output	wire	[7:0]	VGA_DAC_RED;
output	wire	[7:0]	VGA_DAC_GREEN;
output	wire	[7:0]	VGA_DAC_BLUE;
`endif

output	reg				VGA_HS;
output	reg				VGA_VS;
output	wire			VGA_DAC_BLANK_N;
output	wire			VGA_DAC_SYNC_N;
output	wire			VGA_DAC_CLOCK;
`endif



input 			PS2_KBCLK;
input			PS2_KBDAT;


output	wire	[9:0]	LED;


`ifdef AUDIO_WM8731



inout			AUD_ADCLRCK;
input			AUD_ADCDAT;


inout			AUD_DACLRCK;
output	wire	AUD_DACDAT;

inout			AUD_BCLK;
output	wire	AUD_XCK;


inout			I2C_SDAT;
output			I2C_SCLK;

`endif


input	[1:0]		BUTTON_N;
wire	[1:0]		BUTTON;
assign	BUTTON	=	~BUTTON_N;


`ifdef GPIO_PIN





`endif




wire				CLK10MHZ;
CLK10MHZ_PLL CLK10MHZ_PLL_INST(
	CLK50MHZ,
	CLK10MHZ);


wire				BASE_CLK = CLK50MHZ;

reg		[3:0]		CLK;

reg					MEM_OP_WR;



reg					GPIO_CPU_CLK;


reg					CPU_CLK;
wire	[15:0]		CPU_A;
wire	[7:0]		CPU_DI;
wire	[7:0]		CPU_DO;

wire				CPU_RESET;
wire				CPU_HALT;
wire				CPU_WAIT;

wire				CPU_MREQ;
wire				CPU_RD;
wire				CPU_WR;
wire				CPU_IORQ;

reg					CPU_INT;
wire				CPU_NMI;
wire				CPU_M1;


wire				CPU_BUSRQ;
wire				CPU_BUSAK;

wire				CPU_RFSH;

`ifdef TV80

wire				CPU_RESET_N;
wire				CPU_HALT_N;
wire				CPU_WAIT_N;

wire				CPU_MREQ_N;
wire				CPU_RD_N;
wire				CPU_WR_N;
wire				CPU_IORQ_N;

wire				CPU_INT_N;
wire				CPU_NMI_N;
wire				CPU_M1_N;

wire				CPU_BUSRQ_N;
wire				CPU_BUSAK_N;

wire				CPU_RFSH_N;

`endif



wire	[12:0]		VRAM_ADDRESS;
wire				VRAM_WR;
wire	[7:0]		VRAM_DATA_OUT;

wire				VDG_RD;
wire	[12:0]		VDG_ADDRESS;
wire	[7:0]		VDG_DATA;


wire	[7:0]		SYS_ROM_DATA;

wire				RAM_78_WR;
wire	[7:0]		RAM_78_DATA_OUT;

wire				RAM_80_WR;
wire	[7:0]		RAM_80_DATA_OUT;


wire				RAM_16K_WR;
wire	[7:0]		RAM_16K_DATA_OUT;

wire				ADDRESS_ROM;
wire				ADDRESS_IO;
wire				ADDRESS_VRAM;

wire				ADDRESS_RAM_78;
wire				ADDRESS_RAM_80;

wire				ADDRESS_RAM_16K;




reg		[7:0]		LATCHED_IO_DATA_WR;


wire	[7:0]		VGA_OUT_RED;
wire	[7:0]		VGA_OUT_GREEN;
wire	[7:0]		VGA_OUT_BLUE;

wire				VGA_OUT_HS;
wire				VGA_OUT_VS;

wire				VGA_OUT_BLANK;

`ifdef CLOCK_50MHZ
reg					VGA_CLK;
`else

wire				VGA_CLK;
`endif


reg		[4:0]		KB_CLK;

wire	[7:0]		SCAN;
wire				PRESS;
wire				PRESS_N;
wire				EXTENDED;

reg		[63:0]		KEY;
reg		[9:0]		KEY_EX;
reg		[11:0]		KEY_Fxx;
wire	[7:0]		KEY_DATA;



wire				A_KEY_PRESSED;

reg		[7:0]		LATCHED_KEY_DATA;



wire	SPEAKER_A = LATCHED_IO_DATA_WR[0];
wire	SPEAKER_B = LATCHED_IO_DATA_WR[5];



wire	[1:0]		CASS_OUT;
wire				CASS_IN;
wire				CASS_IN_L;
wire				CASS_IN_R;




wire				SYS_RESET_N;
wire				RESET_N;
wire				RESET_AHEAD_N;

reg		[16:0]		RESET_KEY_COUNT;
wire				RESET_KEY_N;







assign	I2C_SDAT	=	1'bz;
assign	AUD_ADCLRCK	=	1'bz;
assign	AUD_DACLRCK	=	1'bz;
assign	AUD_BCLK	=	1'bz;




assign SYS_RESET_N = !BUTTON[0];

RESET_DE RESET_DE(
	.CLK(CLK50MHZ),
	.SYS_RESET_N(SYS_RESET_N && RESET_KEY_N),
	.RESET_N(RESET_N),
	.RESET_AHEAD_N(RESET_AHEAD_N)
);



assign RESET_KEY_N = RESET_KEY_COUNT[16];


`ifdef SIMULATE
initial
	begin
		VGA_CLK = 1'b0;
		CLK = 4'b0;
	end
`endif

`ifdef CLOCK_50MHZ

always @(negedge CLK50MHZ)
	VGA_CLK <= !VGA_CLK;

`endif


`ifdef CLOCK_27MHZ

VGA_Audio_PLL  VGA_AUDIO_PLL(.inclk0(CLK27MHZ),.c0(VGA_CLK),.c1(AUD_CTRL_CLK));

`endif












reg 		[17:0]	INT_CNT;

always @ (negedge CLK10MHZ)
	case(INT_CNT[17:0])
		18'd0:
		begin
			CPU_INT <= 1'b1;
			INT_CNT <= 18'd1;
		end
		18'd640:
		begin
			CPU_INT <= 1'b0;
			INT_CNT <= 18'd641;
		end
		18'd199999:
		begin
			INT_CNT <= 18'd0;
		end
		default:
		begin
			INT_CNT <= INT_CNT + 1;
		end
	endcase
















`ifdef SIMULATE
initial
	begin
		CLK = 4'b0;
	end
`endif

always @(posedge BASE_CLK or negedge RESET_N)
	if(~RESET_N)
	begin
		CPU_CLK					<=	1'b0;
		GPIO_CPU_CLK			<=	1'b0;


		MEM_OP_WR				<=	1'b0;

		LATCHED_KEY_DATA		<=	8'b0;
		LATCHED_IO_DATA_WR		<=	8'b0;

		CLK						<=	4'd0;
	end
	else
	begin
		case (CLK[3:0])
		4'd0:
			begin

				CPU_CLK				<=	1'b1;
				GPIO_CPU_CLK		<=	1'b1;

				MEM_OP_WR			<=	1'b1;

				CLK					<=	4'd1;
			end

		4'd1:
			begin

				CPU_CLK				<=	1'b0;
				MEM_OP_WR			<=	1'b0;

				LATCHED_KEY_DATA	<=	KEY_DATA;

				if({CPU_MREQ,CPU_RD,CPU_WR,ADDRESS_IO}==4'b1011)
					LATCHED_IO_DATA_WR	<=	CPU_DO;

				CLK					<=	4'd2;
			end

		4'd2:
			begin

				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	4'd3;
			end


		4'd7:
			begin
				CPU_CLK				<=	1'b0;
				GPIO_CPU_CLK		<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	4'd8;
			end


		4'd13:
			begin
				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	4'd0;
			end
		default:
			begin
				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	CLK + 1'b1;
			end
		endcase
	end





wire [7:0] InPort = 8'b0;



`ifdef NEXTZ80

assign CPU_RD = ~CPU_WR;



NextZ80 Z80CPU (
	.DI(CPU_IORQ ? (CPU_M1 ? 8'b00000000 : InPort) : CPU_DI),
	.DO(CPU_DO),
	.ADDR(CPU_A),
	.WR(CPU_WR),
	.MREQ(CPU_MREQ),
	.IORQ(CPU_IORQ),
	.HALT(CPU_HALT),
	.CLK(CPU_CLK),
	.RESET(CPU_RESET),
	.INT(CPU_INT),
	.NMI(CPU_NMI),
	.WAIT(CPU_WAIT),
	.M1(CPU_M1)
);

`endif


`ifdef TV80

assign CPU_M1 = ~CPU_M1_N;
assign CPU_MREQ = ~CPU_MREQ_N;
assign CPU_IORQ = ~CPU_IORQ_N;
assign CPU_RD = ~CPU_RD_N;
assign CPU_WR = ~CPU_WR_N;
assign CPU_RFSH = ~CPU_RFSH_N;
assign CPU_HALT= ~CPU_HALT_N;
assign CPU_BUSAK = ~CPU_BUSAK_N;

assign CPU_RESET_N = ~CPU_RESET;
assign CPU_WAIT_N = ~CPU_WAIT;
assign CPU_INT_N = ~CPU_INT;

assign CPU_NMI_N = ~CPU_NMI;
assign CPU_BUSRQ_N = ~CPU_BUSRQ;



tv80s Z80CPU (
	.m1_n(CPU_M1_N),
	.mreq_n(CPU_MREQ_N),
	.iorq_n(CPU_IORQ_N),
	.rd_n(CPU_RD_N),
	.wr_n(CPU_WR_N),
	.rfsh_n(CPU_RFSH_N),
	.halt_n(CPU_HALT_N),
	.busak_n(CPU_BUSAK_N),
	.A(CPU_A),
	.dout(CPU_DO),
	.reset_n(CPU_RESET_N),
	.clk(CPU_CLK),
	.wait_n(CPU_WAIT_N),
	.int_n(CPU_INT_N),
	.nmi_n(CPU_NMI_N),
	.busrq_n(CPU_BUSRQ_N),
	.di(CPU_IORQ_N ? CPU_DI : (CPU_M1_N ? InPort: 8'b00000000))
);

`endif

assign CPU_RESET = ~RESET_N;

assign CPU_NMI = 1'b0;


assign CPU_WAIT = 1'b0;














assign ADDRESS_ROM			=	(CPU_A[15:14] == 2'b00)?1'b1:1'b0;
assign ADDRESS_IO			=	(CPU_A[15:11] == 5'b01101)?1'b1:1'b0;
assign ADDRESS_VRAM			=	(CPU_A[15:11] == 5'b01110)?1'b1:1'b0;


assign ADDRESS_RAM_78		=	(CPU_A[15:11] == 5'b01111)?1'b1:1'b0;


assign ADDRESS_RAM_80		=	(CPU_A[15:11] == 5'b10000)?1'b1:1'b0;





assign ADDRESS_RAM_16K		=	(CPU_A[15:12] == 4'h8)?1'b1:
								(CPU_A[15:12] == 4'h9)?1'b1:
								(CPU_A[15:12] == 4'hA)?1'b1:
								(CPU_A[15:11] == 5'b01111)?1'b1:
								(CPU_A[15:11] == 5'b10110)?1'b1:
								1'b0;


assign VRAM_WR			= ({ADDRESS_VRAM,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;

assign RAM_78_WR		= ({ADDRESS_RAM_78,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
assign RAM_80_WR		= ({ADDRESS_RAM_80,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;

assign RAM_16K_WR		= ({ADDRESS_RAM_16K,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;


`ifdef	RAM_ON_FPGA

assign CPU_DI = 	ADDRESS_ROM			? SYS_ROM_DATA		:
					ADDRESS_IO			? LATCHED_KEY_DATA	:
					ADDRESS_VRAM		? VRAM_DATA_OUT		:
`ifdef BASE_RAM_2K
					ADDRESS_RAM_78		? RAM_78_DATA_OUT	:
`endif
`ifdef BASE_RAM_4K
					ADDRESS_RAM_78		? RAM_78_DATA_OUT	:
					ADDRESS_RAM_80		? RAM_80_DATA_OUT	:
`endif
`ifdef BASE_RAM_16K
					ADDRESS_RAM_16K		? RAM_16K_DATA_OUT	:
`endif
					8'hzz;

`endif


`ifdef BASE_SYS_ROM

`ifdef FPGA_ALTERA

sys_rom_altera sys_rom(
	.address(CPU_A[13:0]),
	.clock(BASE_CLK),
	.q(SYS_ROM_DATA)
);

`endif

`endif


`ifdef	RAM_ON_FPGA


`ifdef BASE_RAM_2K

`ifdef FPGA_ALTERA

ram_2k_altera sys_ram_78(
	.address(CPU_A[10:0]),
	.clock(BASE_CLK),
	.data(CPU_DO),
	.wren(CPU_MREQ & RAM_78_WR),
	.q(RAM_78_DATA_OUT)
);

`endif

`endif


`ifdef BASE_RAM_4K

`ifdef FPGA_ALTERA

ram_2k_altera sys_ram_78(
	.address(CPU_A[10:0]),
	.clock(BASE_CLK),
	.data(CPU_DO),
	.wren(CPU_MREQ & RAM_78_WR),
	.q(RAM_78_DATA_OUT)
);

ram_2k_altera sys_ram_80(
	.address(CPU_A[10:0]),
	.clock(BASE_CLK),
	.data(CPU_DO),
	.wren(CPU_MREQ & RAM_80_WR),
	.q(RAM_80_DATA_OUT)
);

`endif

`endif


`ifdef BASE_RAM_16K

`ifdef FPGA_ALTERA

ram_altera sys_ram_16k(
	.address(CPU_A[13:0]),
	.clock(BASE_CLK),
	.data(CPU_DO),
	.wren(CPU_MREQ & RAM_16K_WR),
	.q(RAM_16K_DATA_OUT)
);

`endif

`endif


`endif







`ifdef VRAM_2K

`ifdef FPGA_ALTERA

vram_altera vram_2k(
	.address_a(CPU_A[10:0]),
	.address_b(VDG_ADDRESS[10:0]),
	.clock_a(BASE_CLK),
	.clock_b(VDG_RD),
	.data_a(CPU_DO),
	.data_b(),
	.wren_a(CPU_MREQ & VRAM_WR),
	.wren_b(1'b0),
	.q_a(VRAM_DATA_OUT),
	.q_b(VDG_DATA)
);

`endif

`endif



MC6847_VGA MC6847_VGA(
	.PIX_CLK(VGA_CLK),
	.RESET_N(RESET_N),

	.RD(VDG_RD),
	.DD(VDG_DATA),
	.DA(VDG_ADDRESS),

	.AG(LATCHED_IO_DATA_WR[3]),
	.AS(1'b0),
	.EXT(1'b0),
	.INV(1'b0),
	.GM(3'b010),
	.CSS(LATCHED_IO_DATA_WR[4]),


	.VGA_OUT_HSYNC(VGA_OUT_HS),
	.VGA_OUT_VSYNC(VGA_OUT_VS),
	.VGA_OUT_RED(VGA_OUT_RED),
	.VGA_OUT_GREEN(VGA_OUT_GREEN),
	.VGA_OUT_BLUE(VGA_OUT_BLUE)
);


`ifdef VGA_RESISTOR

`ifdef VGA_BIT12
assign VGA_RED = VGA_OUT_RED[7:4];
assign VGA_GREEN = VGA_OUT_GREEN[7:4];
assign VGA_BLUE = VGA_OUT_BLUE[7:4];
`endif

assign VGA_HS = VGA_OUT_HS;
assign VGA_VS = VGA_OUT_VS;

`endif

`ifdef VGA_ADV7123

`ifdef VGA_BIT24
assign VGA_DAC_RED = VGA_OUT_RED;
assign VGA_DAC_GREEN = VGA_OUT_GREEN;
assign VGA_DAC_BLUE = VGA_OUT_BLUE;
`endif

`ifdef VGA_BIT30
assign VGA_DAC_RED = {VGA_OUT_RED,2'b0};
assign VGA_DAC_GREEN = {VGA_OUT_GREEN,2'b0};
assign VGA_DAC_BLUE = {VGA_OUT_BLUE,2'b0};
`endif

assign VGA_DAC_BLANK_N = 1'b1;
assign VGA_DAC_SYNC_N = ~(VGA_OUT_HS | VGA_OUT_VS);
assign VGA_DAC_CLOCK = VGA_CLK;

always @(posedge VGA_CLK)
	begin
		VGA_HS <= VGA_OUT_HS;
		VGA_VS <= VGA_OUT_VS;
	end

`endif







































wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);

wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45],           KEY[37]&KEY_EX[5]&KEY_EX[8], KEY[29], KEY[21],           KEY[13],                   KEY[ 5]})==8'hff;
wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44],           KEY[36]&KEY_EX[7],           KEY[28], KEY[20],           KEY[12],                   KEY[ 4]})==8'hff;
wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43],           KEY[35]&KEY_EX[6],           KEY[27], KEY[19],           KEY[11],                   KEY[ 3]})==8'hff;
wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42]&KEY_EX[3], KEY[34],                     KEY[26], KEY[18]&KEY_EX[0], KEY[10]&KEY_CTRL_ULRD_BRK, KEY[ 2]})==8'hff;
wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41],           KEY[33]&KEY_EX[4],           KEY[25], KEY[17],           KEY[ 9],                   KEY[ 1]})==8'hff;
wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40],           KEY[32],                     KEY[24], KEY[16],           KEY[ 8],                   KEY[ 0]})==8'hff;



wire KEY_DATA_BIT7 = 1'b1;

wire KEY_DATA_BIT6 = ~CASS_IN;

assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };




assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;

always @(posedge KB_CLK[3] or negedge SYS_RESET_N)
begin
	if(~SYS_RESET_N)
	begin
		KEY					<=	64'hFFFFFFFFFFFFFFFF;
		KEY_EX				<=	10'h3FF;
		KEY_Fxx				<=	12'h000;

		RESET_KEY_COUNT		<=	17'h1FFFF;
	end
	else
	begin

		if(RESET_KEY_COUNT[16]==1'b0)
			RESET_KEY_COUNT <= RESET_KEY_COUNT+1;

		case(SCAN)
		8'h07:
		begin
				KEY_Fxx[11]	<= PRESS;
				if(PRESS && (KEY[10]==PRESS_N))
				begin
					RESET_KEY_COUNT		<=	17'h0;
				end
		end
		8'h78:	KEY_Fxx[10] <= PRESS;
		8'h09:	KEY_Fxx[ 9] <= PRESS;
		8'h01:	KEY_Fxx[ 8] <= PRESS;
		8'h0A:	KEY_Fxx[ 7] <= PRESS;
		8'h83:	KEY_Fxx[ 6] <= PRESS;
		8'h0B:	KEY_Fxx[ 5] <= PRESS;
		8'h03:	KEY_Fxx[ 4] <= PRESS;
		8'h0C:	KEY_Fxx[ 3] <= PRESS;
		8'h04:	KEY_Fxx[ 2] <= PRESS;
		8'h06:	KEY_Fxx[ 1] <= PRESS;
		8'h05:	KEY_Fxx[ 0] <= PRESS;

		8'h16:	KEY[28] <= PRESS_N;
		8'h1E:	KEY[25] <= PRESS_N;
		8'h26:	KEY[27] <= PRESS_N;
		8'h25:	KEY[29] <= PRESS_N;
		8'h2E:	KEY[24] <= PRESS_N;
		8'h36:	KEY[40] <= PRESS_N;
		8'h3D:	KEY[45] <= PRESS_N;

		8'h3E:	KEY[43] <= PRESS_N;
		8'h46:	KEY[41] <= PRESS_N;
		8'h45:	KEY[44] <= PRESS_N;
		8'h4E:	KEY[42] <= PRESS_N;

		8'h66:	KEY_EX[8] <= PRESS_N;


		8'h49:	KEY[33] <= PRESS_N;
		8'h4b:	KEY[57] <= PRESS_N;
		8'h44:	KEY[49] <= PRESS_N;

		8'h5A:	KEY[50] <= PRESS_N;


		8'h52:	KEY[58] <= PRESS_N;
		8'h1D:	KEY[ 1] <= PRESS_N;
		8'h24:	KEY[ 3] <= PRESS_N;
		8'h2D:	KEY[ 5] <= PRESS_N;
		8'h2C:	KEY[ 0] <= PRESS_N;
		8'h35:	KEY[48] <= PRESS_N;
		8'h3C:	KEY[53] <= PRESS_N;
		8'h43:	KEY[51] <= PRESS_N;
		8'h1B:	KEY[ 9] <= PRESS_N;
		8'h23:	KEY[11] <= PRESS_N;
		8'h2B:	KEY[13] <= PRESS_N;
		8'h34:	KEY[ 8] <= PRESS_N;
		8'h33:	KEY[56] <= PRESS_N;
		8'h3B:	KEY[61] <= PRESS_N;
		8'h42:	KEY[59] <= PRESS_N;
		8'h22:	KEY[17] <= PRESS_N;
		8'h21:	KEY[19] <= PRESS_N;
		8'h2a:	KEY[21] <= PRESS_N;
		8'h32:	KEY[16] <= PRESS_N;
		8'h31:	KEY[32] <= PRESS_N;
		8'h3a:	KEY[37] <= PRESS_N;
		8'h41:	KEY[35] <= PRESS_N;
		8'h15:	KEY[ 4] <= PRESS_N;
		8'h1C:	KEY[12] <= PRESS_N;
		8'h1A:	KEY[20] <= PRESS_N;
		8'h29:	KEY[36] <= PRESS_N;

		8'h4C:	KEY[60] <= PRESS_N;
		8'h4D:	KEY[52] <= PRESS_N;
		8'h14:	KEY[10] <= PRESS_N;
		8'h12:	KEY[18] <= PRESS_N;
		8'h59:	KEY_EX[0] <= PRESS_N;
		8'h11:
		begin
			if(~EXTENDED)
					KEY_EX[1] <= PRESS_N;
			else
					KEY_EX[2] <= PRESS_N;
		end
		8'h76:	KEY_EX[3] <= PRESS_N;
		8'h75:	KEY_EX[4] <= PRESS_N;
		8'h6B:	KEY_EX[5] <= PRESS_N;
		8'h74:	KEY_EX[6] <= PRESS_N;
		8'h72:	KEY_EX[7] <= PRESS_N;
		endcase
	end
end


`ifdef SIMULATE
initial
	begin
		KB_CLK = 5'b0;
	end
`endif

always @ (posedge CLK50MHZ)
	KB_CLK <= KB_CLK + 1'b1;

ps2_keyboard KEYBOARD(
		.RESET_N(RESET_N),
		.CLK(KB_CLK[4]),
		.PS2_CLK(PS2_KBCLK),
		.PS2_DATA(PS2_KBDAT),
		.RX_SCAN(SCAN),
		.RX_PRESSED(PRESS),
		.RX_EXTENDED(EXTENDED)
);

assign PRESS_N = ~PRESS;


`ifdef AUDIO_WM8731

AUDIO_IF AUD_IF(

	.oAUD_BCLK(AUD_BCLK),
	.oAUD_DACLRCK(AUD_DACLRCK),
	.oAUD_DACDAT(AUD_DACDAT),
	.oAUD_ADCLRCK(AUD_ADCLRCK),
	.iAUD_ADCDAT(AUD_ADCDAT),

	.iSPK_A(SPEAKER_A),
	.iSPK_B(SPEAKER_B),
	.iCASS_OUT(CASS_OUT),
	.oCASS_IN_L(CASS_IN_L),
	.oCASS_IN_R(CASS_IN_R),

	.iCLK_18_4(AUD_CTRL_CLK),
	.iRST_N(RESET_N)
);

I2C_AV_Config AUD_I2C(

	.iCLK(CLK50MHZ),
	.iRST_N(RESET_N),

	.I2C_SCLK(I2C_SCLK),
	.I2C_SDAT(I2C_SDAT)
);

assign	AUD_XCK = AUD_CTRL_CLK;

`endif


`ifdef AUDIO_GPIO
`endif


assign	CASS_OUT		=	{LATCHED_IO_DATA_WR[2], 1'b0};

`ifdef AUDIO_WM8731
assign	CASS_IN			=	CASS_IN_L;
`endif

`ifdef AUDIO_GPIO
assign	CASS_IN			=	1'b0;
`endif


`ifdef GPIO_PIN


`endif



assign LED = {4'b0, CASS_IN, CASS_IN_L, CASS_IN_R, CASS_OUT, A_KEY_PRESSED, CPU_RESET};

endmodule
module LASER310_TOP(
	CLK50MHZ,

`ifdef CLOCK_27MHZ
	CLK27MHZ,
`endif


`ifdef VGA_RESISTOR
	VGA_RED,
	VGA_GREEN,
	VGA_BLUE,
	VGA_HS,
	VGA_VS,
`endif

`ifdef VGA_ADV7123
	VGA_DAC_RED,
	VGA_DAC_GREEN,
	VGA_DAC_BLUE,
	VGA_HS,
	VGA_VS,
	VGA_DAC_BLANK_N,
	VGA_DAC_SYNC_N,
	VGA_DAC_CLOCK,
`endif


	PS2_KBCLK,
	PS2_KBDAT,

	LED,

`ifdef AUDIO_WM8731

	AUD_ADCLRCK,
	AUD_ADCDAT,
	AUD_DACLRCK,
	AUD_DACDAT,
	AUD_BCLK,
	AUD_XCK,


	I2C_SDAT,
	I2C_SCLK,

`endif

`ifdef GPIO_PIN



`endif

	BUTTON_N
);



input				CLK50MHZ;

`ifdef CLOCK_27MHZ
input				CLK27MHZ;
`endif


`ifdef VGA_RESISTOR

`ifdef VGA_BIT12
output	wire	[3:0]	VGA_RED;
output	wire	[3:0]	VGA_GREEN;
output	wire	[3:0]	VGA_BLUE;
`endif

output	wire			VGA_HS;
output	wire			VGA_VS;
`endif


`ifdef VGA_ADV7123

`ifdef VGA_BIT30
output	wire	[9:0]	VGA_DAC_RED;
output	wire	[9:0]	VGA_DAC_GREEN;
output	wire	[9:0]	VGA_DAC_BLUE;
`endif

`ifdef VGA_BIT24
output	wire	[7:0]	VGA_DAC_RED;
output	wire	[7:0]	VGA_DAC_GREEN;
output	wire	[7:0]	VGA_DAC_BLUE;
`endif

output	reg				VGA_HS;
output	reg				VGA_VS;
output	wire			VGA_DAC_BLANK_N;
output	wire			VGA_DAC_SYNC_N;
output	wire			VGA_DAC_CLOCK;
`endif



input 			PS2_KBCLK;
input			PS2_KBDAT;


output	wire	[9:0]	LED;


`ifdef AUDIO_WM8731



inout			AUD_ADCLRCK;
input			AUD_ADCDAT;


inout			AUD_DACLRCK;
output	wire	AUD_DACDAT;

inout			AUD_BCLK;
output	wire	AUD_XCK;


inout			I2C_SDAT;
output			I2C_SCLK;

`endif


input	[1:0]		BUTTON_N;
wire	[1:0]		BUTTON;
assign	BUTTON	=	~BUTTON_N;


`ifdef GPIO_PIN





`endif




wire				CLK10MHZ;
CLK10MHZ_PLL CLK10MHZ_PLL_INST(
	CLK50MHZ,
	CLK10MHZ);


wire				BASE_CLK = CLK50MHZ;

reg		[3:0]		CLK;

reg					MEM_OP_WR;



reg					GPIO_CPU_CLK;


reg					CPU_CLK;
wire	[15:0]		CPU_A;
wire	[7:0]		CPU_DI;
wire	[7:0]		CPU_DO;

wire				CPU_RESET;
wire				CPU_HALT;
wire				CPU_WAIT;

wire				CPU_MREQ;
wire				CPU_RD;
wire				CPU_WR;
wire				CPU_IORQ;

reg					CPU_INT;
wire				CPU_NMI;
wire				CPU_M1;


wire				CPU_BUSRQ;
wire				CPU_BUSAK;

wire				CPU_RFSH;

`ifdef TV80

wire				CPU_RESET_N;
wire				CPU_HALT_N;
wire				CPU_WAIT_N;

wire				CPU_MREQ_N;
wire				CPU_RD_N;
wire				CPU_WR_N;
wire				CPU_IORQ_N;

wire				CPU_INT_N;
wire				CPU_NMI_N;
wire				CPU_M1_N;

wire				CPU_BUSRQ_N;
wire				CPU_BUSAK_N;

wire				CPU_RFSH_N;

`endif



wire	[12:0]		VRAM_ADDRESS;
wire				VRAM_WR;
wire	[7:0]		VRAM_DATA_OUT;

wire				VDG_RD;
wire	[12:0]		VDG_ADDRESS;
wire	[7:0]		VDG_DATA;


wire	[7:0]		SYS_ROM_DATA;

wire				RAM_78_WR;
wire	[7:0]		RAM_78_DATA_OUT;

wire				RAM_80_WR;
wire	[7:0]		RAM_80_DATA_OUT;


wire				RAM_16K_WR;
wire	[7:0]		RAM_16K_DATA_OUT;

wire				ADDRESS_ROM;
wire				ADDRESS_IO;
wire				ADDRESS_VRAM;

wire				ADDRESS_RAM_78;
wire				ADDRESS_RAM_80;

wire				ADDRESS_RAM_16K;




reg		[7:0]		LATCHED_IO_DATA_WR;


wire	[7:0]		VGA_OUT_RED;
wire	[7:0]		VGA_OUT_GREEN;
wire	[7:0]		VGA_OUT_BLUE;

wire				VGA_OUT_HS;
wire				VGA_OUT_VS;

wire				VGA_OUT_BLANK;

`ifdef CLOCK_50MHZ
reg					VGA_CLK;
`else

wire				VGA_CLK;
`endif


reg		[4:0]		KB_CLK;

wire	[7:0]		SCAN;
wire				PRESS;
wire				PRESS_N;
wire				EXTENDED;

reg		[63:0]		KEY;
reg		[9:0]		KEY_EX;
reg		[11:0]		KEY_Fxx;
wire	[7:0]		KEY_DATA;



wire				A_KEY_PRESSED;

reg		[7:0]		LATCHED_KEY_DATA;



wire	SPEAKER_A = LATCHED_IO_DATA_WR[0];
wire	SPEAKER_B = LATCHED_IO_DATA_WR[5];



wire	[1:0]		CASS_OUT;
wire				CASS_IN;
wire				CASS_IN_L;
wire				CASS_IN_R;




wire				SYS_RESET_N;
wire				RESET_N;
wire				RESET_AHEAD_N;

reg		[16:0]		RESET_KEY_COUNT;
wire				RESET_KEY_N;







assign	I2C_SDAT	=	1'bz;
assign	AUD_ADCLRCK	=	1'bz;
assign	AUD_DACLRCK	=	1'bz;
assign	AUD_BCLK	=	1'bz;




assign SYS_RESET_N = !BUTTON[0];

RESET_DE RESET_DE(
	.CLK(CLK50MHZ),
	.SYS_RESET_N(SYS_RESET_N && RESET_KEY_N),
	.RESET_N(RESET_N),
	.RESET_AHEAD_N(RESET_AHEAD_N)
);



assign RESET_KEY_N = RESET_KEY_COUNT[16];


`ifdef SIMULATE
initial
	begin
		VGA_CLK = 1'b0;
		CLK = 4'b0;
	end
`endif

`ifdef CLOCK_50MHZ

always @(negedge CLK50MHZ)
	VGA_CLK <= !VGA_CLK;

`endif


`ifdef CLOCK_27MHZ

VGA_Audio_PLL  VGA_AUDIO_PLL(.inclk0(CLK27MHZ),.c0(VGA_CLK),.c1(AUD_CTRL_CLK));

`endif












reg 		[17:0]	INT_CNT;

always @ (negedge CLK10MHZ)
	case(INT_CNT[17:0])
		18'd0:
		begin
			CPU_INT <= 1'b1;
			INT_CNT <= 18'd1;
		end
		18'd640:
		begin
			CPU_INT <= 1'b0;
			INT_CNT <= 18'd641;
		end
		18'd199999:
		begin
			INT_CNT <= 18'd0;
		end
		default:
		begin
			INT_CNT <= INT_CNT + 1;
		end
	endcase
















`ifdef SIMULATE
initial
	begin
		CLK = 4'b0;
	end
`endif

always @(posedge BASE_CLK or negedge RESET_N)
	if(~RESET_N)
	begin
		CPU_CLK					<=	1'b0;
		GPIO_CPU_CLK			<=	1'b0;


		MEM_OP_WR				<=	1'b0;

		LATCHED_KEY_DATA		<=	8'b0;
		LATCHED_IO_DATA_WR		<=	8'b0;

		CLK						<=	4'd0;
	end
	else
	begin
		case (CLK[3:0])
		4'd0:
			begin

				CPU_CLK				<=	1'b1;
				GPIO_CPU_CLK		<=	1'b1;

				MEM_OP_WR			<=	1'b1;

				CLK					<=	4'd1;
			end

		4'd1:
			begin

				CPU_CLK				<=	1'b0;
				MEM_OP_WR			<=	1'b0;

				LATCHED_KEY_DATA	<=	KEY_DATA;

				if({CPU_MREQ,CPU_RD,CPU_WR,ADDRESS_IO}==4'b1011)
					LATCHED_IO_DATA_WR	<=	CPU_DO;

				CLK					<=	4'd2;
			end

		4'd2:
			begin

				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	4'd3;
			end


		4'd7:
			begin
				CPU_CLK				<=	1'b0;
				GPIO_CPU_CLK		<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	4'd8;
			end


		4'd13:
			begin
				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	4'd0;
			end
		default:
			begin
				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	CLK + 1'b1;
			end
		endcase
	end





wire [7:0] InPort = 8'b0;



`ifdef NEXTZ80

assign CPU_RD = ~CPU_WR;



NextZ80 Z80CPU (
	.DI(CPU_IORQ ? (CPU_M1 ? 8'b00000000 : InPort) : CPU_DI),
	.DO(CPU_DO),
	.ADDR(CPU_A),
	.WR(CPU_WR),
	.MREQ(CPU_MREQ),
	.IORQ(CPU_IORQ),
	.HALT(CPU_HALT),
	.CLK(CPU_CLK),
	.RESET(CPU_RESET),
	.INT(CPU_INT),
	.NMI(CPU_NMI),
	.WAIT(CPU_WAIT),
	.M1(CPU_M1)
);

`endif


`ifdef TV80

assign CPU_M1 = ~CPU_M1_N;
assign CPU_MREQ = ~CPU_MREQ_N;
assign CPU_IORQ = ~CPU_IORQ_N;
assign CPU_RD = ~CPU_RD_N;
assign CPU_WR = ~CPU_WR_N;
assign CPU_RFSH = ~CPU_RFSH_N;
assign CPU_HALT= ~CPU_HALT_N;
assign CPU_BUSAK = ~CPU_BUSAK_N;

assign CPU_RESET_N = ~CPU_RESET;
assign CPU_WAIT_N = ~CPU_WAIT;
assign CPU_INT_N = ~CPU_INT;

assign CPU_NMI_N = ~CPU_NMI;
assign CPU_BUSRQ_N = ~CPU_BUSRQ;



tv80s Z80CPU (
	.m1_n(CPU_M1_N),
	.mreq_n(CPU_MREQ_N),
	.iorq_n(CPU_IORQ_N),
	.rd_n(CPU_RD_N),
	.wr_n(CPU_WR_N),
	.rfsh_n(CPU_RFSH_N),
	.halt_n(CPU_HALT_N),
	.busak_n(CPU_BUSAK_N),
	.A(CPU_A),
	.dout(CPU_DO),
	.reset_n(CPU_RESET_N),
	.clk(CPU_CLK),
	.wait_n(CPU_WAIT_N),
	.int_n(CPU_INT_N),
	.nmi_n(CPU_NMI_N),
	.busrq_n(CPU_BUSRQ_N),
	.di(CPU_IORQ_N ? CPU_DI : (CPU_M1_N ? InPort: 8'b00000000))
);

`endif

assign CPU_RESET = ~RESET_N;

assign CPU_NMI = 1'b0;


assign CPU_WAIT = 1'b0;














assign ADDRESS_ROM			=	(CPU_A[15:14] == 2'b00)?1'b1:1'b0;
assign ADDRESS_IO			=	(CPU_A[15:11] == 5'b01101)?1'b1:1'b0;
assign ADDRESS_VRAM			=	(CPU_A[15:11] == 5'b01110)?1'b1:1'b0;


assign ADDRESS_RAM_78		=	(CPU_A[15:11] == 5'b01111)?1'b1:1'b0;


assign ADDRESS_RAM_80		=	(CPU_A[15:11] == 5'b10000)?1'b1:1'b0;





assign ADDRESS_RAM_16K		=	(CPU_A[15:12] == 4'h8)?1'b1:
								(CPU_A[15:12] == 4'h9)?1'b1:
								(CPU_A[15:12] == 4'hA)?1'b1:
								(CPU_A[15:11] == 5'b01111)?1'b1:
								(CPU_A[15:11] == 5'b10110)?1'b1:
								1'b0;


assign VRAM_WR			= ({ADDRESS_VRAM,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;

assign RAM_78_WR		= ({ADDRESS_RAM_78,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;
assign RAM_80_WR		= ({ADDRESS_RAM_80,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;

assign RAM_16K_WR		= ({ADDRESS_RAM_16K,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;


`ifdef	RAM_ON_FPGA

assign CPU_DI = 	ADDRESS_ROM			? SYS_ROM_DATA		:
					ADDRESS_IO			? LATCHED_KEY_DATA	:
					ADDRESS_VRAM		? VRAM_DATA_OUT		:
`ifdef BASE_RAM_2K
					ADDRESS_RAM_78		? RAM_78_DATA_OUT	:
`endif
`ifdef BASE_RAM_4K
					ADDRESS_RAM_78		? RAM_78_DATA_OUT	:
					ADDRESS_RAM_80		? RAM_80_DATA_OUT	:
`endif
`ifdef BASE_RAM_16K
					ADDRESS_RAM_16K		? RAM_16K_DATA_OUT	:
`endif
					8'hzz;

`endif


`ifdef BASE_SYS_ROM

`ifdef FPGA_ALTERA

sys_rom_altera sys_rom(
	.address(CPU_A[13:0]),
	.clock(BASE_CLK),
	.q(SYS_ROM_DATA)
);

`endif

`endif


`ifdef	RAM_ON_FPGA


`ifdef BASE_RAM_2K

`ifdef FPGA_ALTERA

ram_2k_altera sys_ram_78(
	.address(CPU_A[10:0]),
	.clock(BASE_CLK),
	.data(CPU_DO),
	.wren(CPU_MREQ & RAM_78_WR),
	.q(RAM_78_DATA_OUT)
);

`endif

`endif


`ifdef BASE_RAM_4K

`ifdef FPGA_ALTERA

ram_2k_altera sys_ram_78(
	.address(CPU_A[10:0]),
	.clock(BASE_CLK),
	.data(CPU_DO),
	.wren(CPU_MREQ & RAM_78_WR),
	.q(RAM_78_DATA_OUT)
);

ram_2k_altera sys_ram_80(
	.address(CPU_A[10:0]),
	.clock(BASE_CLK),
	.data(CPU_DO),
	.wren(CPU_MREQ & RAM_80_WR),
	.q(RAM_80_DATA_OUT)
);

`endif

`endif


`ifdef BASE_RAM_16K

`ifdef FPGA_ALTERA

ram_altera sys_ram_16k(
	.address(CPU_A[13:0]),
	.clock(BASE_CLK),
	.data(CPU_DO),
	.wren(CPU_MREQ & RAM_16K_WR),
	.q(RAM_16K_DATA_OUT)
);

`endif

`endif


`endif







`ifdef VRAM_2K

`ifdef FPGA_ALTERA

vram_altera vram_2k(
	.address_a(CPU_A[10:0]),
	.address_b(VDG_ADDRESS[10:0]),
	.clock_a(BASE_CLK),
	.clock_b(VDG_RD),
	.data_a(CPU_DO),
	.data_b(),
	.wren_a(CPU_MREQ & VRAM_WR),
	.wren_b(1'b0),
	.q_a(VRAM_DATA_OUT),
	.q_b(VDG_DATA)
);

`endif

`endif



MC6847_VGA MC6847_VGA(
	.PIX_CLK(VGA_CLK),
	.RESET_N(RESET_N),

	.RD(VDG_RD),
	.DD(VDG_DATA),
	.DA(VDG_ADDRESS),

	.AG(LATCHED_IO_DATA_WR[3]),
	.AS(1'b0),
	.EXT(1'b0),
	.INV(1'b0),
	.GM(3'b010),
	.CSS(LATCHED_IO_DATA_WR[4]),


	.VGA_OUT_HSYNC(VGA_OUT_HS),
	.VGA_OUT_VSYNC(VGA_OUT_VS),
	.VGA_OUT_RED(VGA_OUT_RED),
	.VGA_OUT_GREEN(VGA_OUT_GREEN),
	.VGA_OUT_BLUE(VGA_OUT_BLUE)
);


`ifdef VGA_RESISTOR

`ifdef VGA_BIT12
assign VGA_RED = VGA_OUT_RED[7:4];
assign VGA_GREEN = VGA_OUT_GREEN[7:4];
assign VGA_BLUE = VGA_OUT_BLUE[7:4];
`endif

assign VGA_HS = VGA_OUT_HS;
assign VGA_VS = VGA_OUT_VS;

`endif

`ifdef VGA_ADV7123

`ifdef VGA_BIT24
assign VGA_DAC_RED = VGA_OUT_RED;
assign VGA_DAC_GREEN = VGA_OUT_GREEN;
assign VGA_DAC_BLUE = VGA_OUT_BLUE;
`endif

`ifdef VGA_BIT30
assign VGA_DAC_RED = {VGA_OUT_RED,2'b0};
assign VGA_DAC_GREEN = {VGA_OUT_GREEN,2'b0};
assign VGA_DAC_BLUE = {VGA_OUT_BLUE,2'b0};
`endif

assign VGA_DAC_BLANK_N = 1'b1;
assign VGA_DAC_SYNC_N = ~(VGA_OUT_HS | VGA_OUT_VS);
assign VGA_DAC_CLOCK = VGA_CLK;

always @(posedge VGA_CLK)
	begin
		VGA_HS <= VGA_OUT_HS;
		VGA_VS <= VGA_OUT_VS;
	end

`endif







































wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);

wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45],           KEY[37]&KEY_EX[5]&KEY_EX[8], KEY[29], KEY[21],           KEY[13],                   KEY[ 5]})==8'hff;
wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44],           KEY[36]&KEY_EX[7],           KEY[28], KEY[20],           KEY[12],                   KEY[ 4]})==8'hff;
wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43],           KEY[35]&KEY_EX[6],           KEY[27], KEY[19],           KEY[11],                   KEY[ 3]})==8'hff;
wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42]&KEY_EX[3], KEY[34],                     KEY[26], KEY[18]&KEY_EX[0], KEY[10]&KEY_CTRL_ULRD_BRK, KEY[ 2]})==8'hff;
wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41],           KEY[33]&KEY_EX[4],           KEY[25], KEY[17],           KEY[ 9],                   KEY[ 1]})==8'hff;
wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40],           KEY[32],                     KEY[24], KEY[16],           KEY[ 8],                   KEY[ 0]})==8'hff;



wire KEY_DATA_BIT7 = 1'b1;

wire KEY_DATA_BIT6 = ~CASS_IN;

assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };




assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;

always @(posedge KB_CLK[3] or negedge SYS_RESET_N)
begin
	if(~SYS_RESET_N)
	begin
		KEY					<=	64'hFFFFFFFFFFFFFFFF;
		KEY_EX				<=	10'h3FF;
		KEY_Fxx				<=	12'h000;

		RESET_KEY_COUNT		<=	17'h1FFFF;
	end
	else
	begin

		if(RESET_KEY_COUNT[16]==1'b0)
			RESET_KEY_COUNT <= RESET_KEY_COUNT+1;

		case(SCAN)
		8'h07:
		begin
				KEY_Fxx[11]	<= PRESS;
				if(PRESS && (KEY[10]==PRESS_N))
				begin
					RESET_KEY_COUNT		<=	17'h0;
				end
		end
		8'h78:	KEY_Fxx[10] <= PRESS;
		8'h09:	KEY_Fxx[ 9] <= PRESS;
		8'h01:	KEY_Fxx[ 8] <= PRESS;
		8'h0A:	KEY_Fxx[ 7] <= PRESS;
		8'h83:	KEY_Fxx[ 6] <= PRESS;
		8'h0B:	KEY_Fxx[ 5] <= PRESS;
		8'h03:	KEY_Fxx[ 4] <= PRESS;
		8'h0C:	KEY_Fxx[ 3] <= PRESS;
		8'h04:	KEY_Fxx[ 2] <= PRESS;
		8'h06:	KEY_Fxx[ 1] <= PRESS;
		8'h05:	KEY_Fxx[ 0] <= PRESS;

		8'h16:	KEY[28] <= PRESS_N;
		8'h1E:	KEY[25] <= PRESS_N;
		8'h26:	KEY[27] <= PRESS_N;
		8'h25:	KEY[29] <= PRESS_N;
		8'h2E:	KEY[24] <= PRESS_N;
		8'h36:	KEY[40] <= PRESS_N;
		8'h3D:	KEY[45] <= PRESS_N;

		8'h3E:	KEY[43] <= PRESS_N;
		8'h46:	KEY[41] <= PRESS_N;
		8'h45:	KEY[44] <= PRESS_N;
		8'h4E:	KEY[42] <= PRESS_N;

		8'h66:	KEY_EX[8] <= PRESS_N;


		8'h49:	KEY[33] <= PRESS_N;
		8'h4b:	KEY[57] <= PRESS_N;
		8'h44:	KEY[49] <= PRESS_N;

		8'h5A:	KEY[50] <= PRESS_N;


		8'h52:	KEY[58] <= PRESS_N;
		8'h1D:	KEY[ 1] <= PRESS_N;
		8'h24:	KEY[ 3] <= PRESS_N;
		8'h2D:	KEY[ 5] <= PRESS_N;
		8'h2C:	KEY[ 0] <= PRESS_N;
		8'h35:	KEY[48] <= PRESS_N;
		8'h3C:	KEY[53] <= PRESS_N;
		8'h43:	KEY[51] <= PRESS_N;
		8'h1B:	KEY[ 9] <= PRESS_N;
		8'h23:	KEY[11] <= PRESS_N;
		8'h2B:	KEY[13] <= PRESS_N;
		8'h34:	KEY[ 8] <= PRESS_N;
		8'h33:	KEY[56] <= PRESS_N;
		8'h3B:	KEY[61] <= PRESS_N;
		8'h42:	KEY[59] <= PRESS_N;
		8'h22:	KEY[17] <= PRESS_N;
		8'h21:	KEY[19] <= PRESS_N;
		8'h2a:	KEY[21] <= PRESS_N;
		8'h32:	KEY[16] <= PRESS_N;
		8'h31:	KEY[32] <= PRESS_N;
		8'h3a:	KEY[37] <= PRESS_N;
		8'h41:	KEY[35] <= PRESS_N;
		8'h15:	KEY[ 4] <= PRESS_N;
		8'h1C:	KEY[12] <= PRESS_N;
		8'h1A:	KEY[20] <= PRESS_N;
		8'h29:	KEY[36] <= PRESS_N;

		8'h4C:	KEY[60] <= PRESS_N;
		8'h4D:	KEY[52] <= PRESS_N;
		8'h14:	KEY[10] <= PRESS_N;
		8'h12:	KEY[18] <= PRESS_N;
		8'h59:	KEY_EX[0] <= PRESS_N;
		8'h11:
		begin
			if(~EXTENDED)
					KEY_EX[1] <= PRESS_N;
			else
					KEY_EX[2] <= PRESS_N;
		end
		8'h76:	KEY_EX[3] <= PRESS_N;
		8'h75:	KEY_EX[4] <= PRESS_N;
		8'h6B:	KEY_EX[5] <= PRESS_N;
		8'h74:	KEY_EX[6] <= PRESS_N;
		8'h72:	KEY_EX[7] <= PRESS_N;
		endcase
	end
end


`ifdef SIMULATE
initial
	begin
		KB_CLK = 5'b0;
	end
`endif

always @ (posedge CLK50MHZ)
	KB_CLK <= KB_CLK + 1'b1;

ps2_keyboard KEYBOARD(
		.RESET_N(RESET_N),
		.CLK(KB_CLK[4]),
		.PS2_CLK(PS2_KBCLK),
		.PS2_DATA(PS2_KBDAT),
		.RX_SCAN(SCAN),
		.RX_PRESSED(PRESS),
		.RX_EXTENDED(EXTENDED)
);

assign PRESS_N = ~PRESS;


`ifdef AUDIO_WM8731

AUDIO_IF AUD_IF(

	.oAUD_BCLK(AUD_BCLK),
	.oAUD_DACLRCK(AUD_DACLRCK),
	.oAUD_DACDAT(AUD_DACDAT),
	.oAUD_ADCLRCK(AUD_ADCLRCK),
	.iAUD_ADCDAT(AUD_ADCDAT),

	.iSPK_A(SPEAKER_A),
	.iSPK_B(SPEAKER_B),
	.iCASS_OUT(CASS_OUT),
	.oCASS_IN_L(CASS_IN_L),
	.oCASS_IN_R(CASS_IN_R),

	.iCLK_18_4(AUD_CTRL_CLK),
	.iRST_N(RESET_N)
);

I2C_AV_Config AUD_I2C(

	.iCLK(CLK50MHZ),
	.iRST_N(RESET_N),

	.I2C_SCLK(I2C_SCLK),
	.I2C_SDAT(I2C_SDAT)
);

assign	AUD_XCK = AUD_CTRL_CLK;

`endif


`ifdef AUDIO_GPIO
`endif


assign	CASS_OUT		=	{LATCHED_IO_DATA_WR[2], 1'b0};

`ifdef AUDIO_WM8731
assign	CASS_IN			=	CASS_IN_L;
`endif

`ifdef AUDIO_GPIO
assign	CASS_IN			=	1'b0;
`endif


`ifdef GPIO_PIN


`endif



assign LED = {4'b0, CASS_IN, CASS_IN_L, CASS_IN_R, CASS_OUT, A_KEY_PRESSED, CPU_RESET};

endmodule