data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu_ctrl.v
data/verilator_xmls/6d387e74-b76a-4413-a577-6a0eeb4d2160.xml
module alu_ctrl(input [5:0] instr, input [1:0] alu_op, output reg [3:0] alu_ctrl);

always@(alu_op or instr) begin
    if(alu_op==2'b00) alu_ctrl=4'b0010;
    else if(alu_op==2'b01) alu_ctrl=4'b0110;
    else if(alu_op==2'b10) begin
        case(instr)
            6'b100000: alu_ctrl=4'b0010;
            6'b100010: alu_ctrl=4'b0110;
            6'b100100: alu_ctrl=4'b0000;
            6'b100101: alu_ctrl=4'b0001;
            6'b101010: alu_ctrl=4'b0111;
            6'b100110: alu_ctrl=4'b1001;
            6'b011000: alu_ctrl=4'b0011;
            6'b011010: alu_ctrl=4'b1000;
            default: alu_ctrl=4'b0010;
        endcase
    end
end
endmodule
module alu_ctrl(input [5:0] instr, input [1:0] alu_op, output reg [3:0] alu_ctrl);


always@(alu_op or instr) begin
    if(alu_op==2'b00) alu_ctrl=4'b0010;
    else if(alu_op==2'b01) alu_ctrl=4'b0110;
    else if(alu_op==2'b10) begin
        case(instr)
            6'b100000: alu_ctrl=4'b0010;
            6'b100010: alu_ctrl=4'b0110;
            6'b100100: alu_ctrl=4'b0000;
            6'b100101: alu_ctrl=4'b0001;
            6'b101010: alu_ctrl=4'b0111;
            6'b100110: alu_ctrl=4'b1001;
            6'b011000: alu_ctrl=4'b0011;
            6'b011010: alu_ctrl=4'b1000;
            default: alu_ctrl=4'b0010;
        endcase
    end
end
endmodule