data/full_repos/permissive/174369527/mem/ram_sp_ar_sw.v
data/verilator_xmls/c789c51d-6e84-4ce6-ae3e-5488cc85abb4.xml
module ram_sp_ar_sw (
clk         ,
address     ,
data        ,
cs          ,
we          ,
oe
); 

parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;


input                                     clk          ;
input [ADDR_WIDTH-1:0] address ;
input                                     cs           ;
input                                     we          ;
input                                     oe           ; 


inout [DATA_WIDTH-1:0]  data       ;


reg [DATA_WIDTH-1:0]   data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];





assign data = (cs && oe && !we) ? data_out : 8'bz; 



always @ (posedge clk)
begin : MEM_WRITE
   if ( cs && we ) begin
       mem[address] = data;
   end
end



always @ (address or cs or we or oe)
begin : MEM_READ
    if (cs && !we && oe) begin
         data_out = mem[address];
    end
end

endmodule
module ram_sp_ar_sw (
clk         ,
address     ,
data        ,
cs          ,
we          ,
oe
);
 

parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;


input                                     clk          ;
input [ADDR_WIDTH-1:0] address ;
input                                     cs           ;
input                                     we          ;
input                                     oe           ; 


inout [DATA_WIDTH-1:0]  data       ;


reg [DATA_WIDTH-1:0]   data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];





assign data = (cs && oe && !we) ? data_out : 8'bz; 



always @ (posedge clk)
begin : MEM_WRITE
   if ( cs && we ) begin
       mem[address] = data;
   end
end



always @ (address or cs or we or oe)
begin : MEM_READ
    if (cs && !we && oe) begin
         data_out = mem[address];
    end
end

endmodule