data/full_repos/permissive/20270692/labs/lab2/sample/flip_me_tb.v
 line:37: before: "$"
1: b'%Error: data/full_repos/permissive/20270692/labs/lab2/sample/flip_me_tb.v:7: Cannot find include file: flip_me.v\n`include "flip_me.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab2/sample,data/full_repos/permissive/20270692/flip_me.v\n             data/full_repos/permissive/20270692/labs/lab2/sample,data/full_repos/permissive/20270692/flip_me.v.v\n             data/full_repos/permissive/20270692/labs/lab2/sample,data/full_repos/permissive/20270692/flip_me.v.sv\n             flip_me.v\n             flip_me.v.v\n             flip_me.v.sv\n             obj_dir/flip_me.v\n             obj_dir/flip_me.v.v\n             obj_dir/flip_me.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab2/sample/flip_me_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  initial #1000 $finish;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab2/sample/flip_me_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n      forever #5; t_clock=~t_clock;\n              ^\n%Error: data/full_repos/permissive/20270692/labs/lab2/sample/flip_me_tb.v:45: Unsupported or unknown PLI call: $monitor\n      $monitor("time=%05d", $time,, "A=%b B=%b", A, B);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab2/sample/flip_me_tb.v:45: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      $monitor("time=%05d", $time,, "A=%b B=%b", A, B);\n                                  ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module flip_me_tb (A);

  output A;
  reg A;

  wire B;

  reg t_A[10000:0];
  reg t_clock;
  reg vectornum[31:0];

  flip_me I1 (A,B);

  initial #1000 $finish;

  initial
    begin
      t_clock=0;
      forever #5; t_clock=~t_clock;
    end

  initial
    begin $readmemb("/dir", t_A);
      vectornum=0;
    end

  always @(negedge t_clock)
    begin
      A<=t_A[vectornum];
      vectornum<=vectornum+1;
    end

  initial
    begin
      $monitor("time=%05d", $time,, "A=%b B=%b", A, B);
    end

endmodule
module flip_me_tb (A);


  output A;
  reg A;

  wire B;

  reg t_A[10000:0];
  reg t_clock;
  reg vectornum[31:0];

  flip_me I1 (A,B);

  initial #1000 $finish;

  initial
    begin
      t_clock=0;
      forever #5; t_clock=~t_clock;
    end

  initial
    begin $readmemb("/dir", t_A);
      vectornum=0;
    end

  always @(negedge t_clock)
    begin
      A<=t_A[vectornum];
      vectornum<=vectornum+1;
    end

  initial
    begin
      $monitor("time=%05d", $time,, "A=%b B=%b", A, B);
    end

endmodule