data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v
1: b'%Error: data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v:42: Cannot find include file: ../../pipe/rtl/pipe_defs.v\n`include "../../pipe/rtl/pipe_defs.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/190755935/src/pipe/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v\n             data/full_repos/permissive/190755935/src/pipe/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v.v\n             data/full_repos/permissive/190755935/src/pipe/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v.sv\n             ../../pipe/rtl/pipe_defs.v\n             ../../pipe/rtl/pipe_defs.v.v\n             ../../pipe/rtl/pipe_defs.v.sv\n             obj_dir/../../pipe/rtl/pipe_defs.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.sv\n%Error: data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v:44: Define or directive not defined: \'`PS_d8s\'\nmodule pipe_fifo #( parameter PipeSpec = `PS_d8s, parameter MemoryWidth = 3 ) (\n                                         ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v:44: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nmodule pipe_fifo #( parameter PipeSpec = `PS_d8s, parameter MemoryWidth = 3 ) (\n                                                ^\n%Error: data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v:44: syntax error, unexpected \')\', expecting \';\'\nmodule pipe_fifo #( parameter PipeSpec = `PS_d8s, parameter MemoryWidth = 3 ) (\n                                                                            ^\n%Error: data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v:48: Define or directive not defined: \'`P_m\'\n        inout [`P_m(PipeSpec):0] pipe_in,\n               ^~~~\n%Error: data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v:49: Define or directive not defined: \'`P_m\'\n        inout [`P_m(PipeSpec):0] pipe_out\n               ^~~~\n%Error: data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v:52: Define or directive not defined: \'`P_Payload_m\'\n    wire [`P_Payload_m(PipeSpec):0] in_payload;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v:55: Define or directive not defined: \'`P_Payload_m\'\n    wire [`P_Payload_m(PipeSpec):0] out_payload;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v:59: syntax error, unexpected IDENTIFIER\n    p_unpack_payload #( .PipeSpec(PipeSpec) ) p_up_p( .pipe(pipe_in), .payload(in_payload) );\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v:65: Define or directive not defined: \'`P_Payload_m\'\n    reg [`P_Payload_m(PipeSpec):0] memory [0:1<<MemoryWidth];\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/pipe/rtl/pipe_fifo.v:72: syntax error, unexpected assign\n    assign in_ready = ( read_address[MemoryWidth] == write_address[MemoryWidth] ) ||\n    ^~~~~~\n%Error: Exiting due to 11 error(s)\n'
module pipe_fifo #( parameter PipeSpec = `PS_d8s, parameter MemoryWidth = 3 ) (
        input clock,
        input reset,

        inout [`P_m(PipeSpec):0] pipe_in,
        inout [`P_m(PipeSpec):0] pipe_out
    );

    wire [`P_Payload_m(PipeSpec):0] in_payload;
    wire in_valid;
    wire in_ready;
    wire [`P_Payload_m(PipeSpec):0] out_payload;
    wire out_valid;
    wire out_ready;

    p_unpack_payload #( .PipeSpec(PipeSpec) ) p_up_p( .pipe(pipe_in), .payload(in_payload) );
    p_unpack_valid_ready #( .PipeSpec(PipeSpec) ) p_up_vr( .pipe(pipe_in), .valid(in_valid), .ready(in_ready) );
    p_pack_payload   #( .PipeSpec(PipeSpec) ) p_p_p( .payload(out_payload), .pipe(pipe_out) );
    p_pack_valid_ready  #( .PipeSpec(PipeSpec) ) p_p_vr( .valid(out_valid), .ready(out_ready), .pipe(pipe_out) );


    reg [`P_Payload_m(PipeSpec):0] memory [0:1<<MemoryWidth];


    reg [MemoryWidth:0] read_address;
    reg [MemoryWidth:0] write_address;


    assign in_ready = ( read_address[MemoryWidth] == write_address[MemoryWidth] ) ||
                      ( read_address[MemoryWidth-1:0] != write_address[MemoryWidth-1:0] );


    always @(posedge clock) begin
        if ( reset ) begin
            write_address <= 0;
        end else begin
            if ( in_ready ) begin
                if ( in_valid ) begin
                    memory[ write_address[MemoryWidth-1:0] ] <= in_payload;
                    write_address <= write_address + 1;
                end
            end
        end
    end


    assign out_valid = ( read_address != write_address );


    always @(posedge clock) begin
        if ( reset ) begin
            read_address <= 0;
        end else begin
            if ( out_valid ) begin
                if ( out_ready ) begin
                    read_address <= read_address + 1;
                end
            end
        end
    end

    assign out_payload = ( out_valid ) ? memory[ read_address[MemoryWidth-1:0] ] : 0;

endmodule
module pipe_fifo #( parameter PipeSpec = `PS_d8s, parameter MemoryWidth = 3 ) (
        input clock,
        input reset,

        inout [`P_m(PipeSpec):0] pipe_in,
        inout [`P_m(PipeSpec):0] pipe_out
    );


    wire [`P_Payload_m(PipeSpec):0] in_payload;
    wire in_valid;
    wire in_ready;
    wire [`P_Payload_m(PipeSpec):0] out_payload;
    wire out_valid;
    wire out_ready;

    p_unpack_payload #( .PipeSpec(PipeSpec) ) p_up_p( .pipe(pipe_in), .payload(in_payload) );
    p_unpack_valid_ready #( .PipeSpec(PipeSpec) ) p_up_vr( .pipe(pipe_in), .valid(in_valid), .ready(in_ready) );
    p_pack_payload   #( .PipeSpec(PipeSpec) ) p_p_p( .payload(out_payload), .pipe(pipe_out) );
    p_pack_valid_ready  #( .PipeSpec(PipeSpec) ) p_p_vr( .valid(out_valid), .ready(out_ready), .pipe(pipe_out) );


    reg [`P_Payload_m(PipeSpec):0] memory [0:1<<MemoryWidth];


    reg [MemoryWidth:0] read_address;
    reg [MemoryWidth:0] write_address;


    assign in_ready = ( read_address[MemoryWidth] == write_address[MemoryWidth] ) ||
                      ( read_address[MemoryWidth-1:0] != write_address[MemoryWidth-1:0] );


    always @(posedge clock) begin
        if ( reset ) begin
            write_address <= 0;
        end else begin
            if ( in_ready ) begin
                if ( in_valid ) begin
                    memory[ write_address[MemoryWidth-1:0] ] <= in_payload;
                    write_address <= write_address + 1;
                end
            end
        end
    end


    assign out_valid = ( read_address != write_address );


    always @(posedge clock) begin
        if ( reset ) begin
            read_address <= 0;
        end else begin
            if ( out_valid ) begin
                if ( out_ready ) begin
                    read_address <= read_address + 1;
                end
            end
        end
    end

    assign out_payload = ( out_valid ) ? memory[ read_address[MemoryWidth-1:0] ] : 0;

endmodule