data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_sink.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_sink.v:67: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'cfg_paddr\' generates 5 bits.\n                                                                                                  : ... In instance frame_sink\n    addr_i = cfg_paddr >> 2;  \n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_sink.v:79: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                                  : ... In instance frame_sink\n          StatusAddr:     cfg_prdata <= {din_ready, din_valid};\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_sink.v:81: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'pos\' generates 16 bits.\n                                                                                                  : ... In instance frame_sink\n          PosCountAddr:   cfg_prdata <= pos;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_sink.v:83: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_irq\' generates 1 bits.\n                                                                                                  : ... In instance frame_sink\n          IrqAddr:        cfg_prdata <= cfg_irq;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_sink.v:107: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'din_data\' generates 8 bits.\n                                                                                                   : ... In instance frame_sink\n        checksum_r  <= checksum + din_data;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/frame_sink.v:111: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'din_data\' generates 8 bits.\n                                                                                                   : ... In instance frame_sink\n        checksum <= checksum + din_data;\n                             ^\n%Error: Exiting due to 6 warning(s)\n'
module frame_sink #(
  parameter DataBits = 8)
(
  input                 clk,
  input                 rst,

  input [4:0]           cfg_paddr,
  input                 cfg_pwrite,
  input [31:0]          cfg_pwdata,
  input                 cfg_psel,
  input                 cfg_penable,
  output                cfg_pready,
  output reg [31:0]     cfg_prdata,
  output                cfg_pslverr,
  output reg            cfg_irq,

  input                 din_valid,
  output                din_ready,
  input  [DataBits-1:0] din_data,
  input                 din_eof
);




  localparam StatusAddr     = 0,
             ChecksumAddr   = 1,
             PosCountAddr   = 2,
             FrameCountAddr = 3,
             IrqAddr        = 4;




  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;


  reg [31:0] frame_count;
  reg [31:0] checksum, checksum_r;
  reg [15:0] pos;


  always @(posedge clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;

    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        case (addr_i)
          IrqAddr:  cfg_irq <= cfg_pwdata[0];
        endcase


      end else begin
        case (addr_i)
          StatusAddr:     cfg_prdata <= {din_ready, din_valid};
          ChecksumAddr:   cfg_prdata <= checksum_r;
          PosCountAddr:   cfg_prdata <= pos;
          FrameCountAddr: cfg_prdata <= frame_count;
          IrqAddr:        cfg_prdata <= cfg_irq;
        endcase
      end
    end


    if (din_valid & din_ready & din_eof)
      cfg_irq <= 1;

    if (rst) begin
      cfg_irq <= 0;
    end

  end




  always @(posedge clk) begin

    if (din_valid && din_ready) begin
      if (din_eof) begin
        pos         <= 0;
        frame_count <= frame_count + 1;
        checksum_r  <= checksum + din_data;
        checksum    <= 0;
      end else begin
        pos      <= pos + 1;
        checksum <= checksum + din_data;
      end
    end

    if (rst) begin
      checksum    <= 0;
      pos         <= 0;
      frame_count <= 0;
    end
  end

  assign din_ready = 1;

endmodule
module frame_sink #(
  parameter DataBits = 8)
(
  input                 clk,
  input                 rst,

  input [4:0]           cfg_paddr,
  input                 cfg_pwrite,
  input [31:0]          cfg_pwdata,
  input                 cfg_psel,
  input                 cfg_penable,
  output                cfg_pready,
  output reg [31:0]     cfg_prdata,
  output                cfg_pslverr,
  output reg            cfg_irq,

  input                 din_valid,
  output                din_ready,
  input  [DataBits-1:0] din_data,
  input                 din_eof
);





  localparam StatusAddr     = 0,
             ChecksumAddr   = 1,
             PosCountAddr   = 2,
             FrameCountAddr = 3,
             IrqAddr        = 4;




  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;


  reg [31:0] frame_count;
  reg [31:0] checksum, checksum_r;
  reg [15:0] pos;


  always @(posedge clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;

    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        case (addr_i)
          IrqAddr:  cfg_irq <= cfg_pwdata[0];
        endcase


      end else begin
        case (addr_i)
          StatusAddr:     cfg_prdata <= {din_ready, din_valid};
          ChecksumAddr:   cfg_prdata <= checksum_r;
          PosCountAddr:   cfg_prdata <= pos;
          FrameCountAddr: cfg_prdata <= frame_count;
          IrqAddr:        cfg_prdata <= cfg_irq;
        endcase
      end
    end


    if (din_valid & din_ready & din_eof)
      cfg_irq <= 1;

    if (rst) begin
      cfg_irq <= 0;
    end

  end




  always @(posedge clk) begin

    if (din_valid && din_ready) begin
      if (din_eof) begin
        pos         <= 0;
        frame_count <= frame_count + 1;
        checksum_r  <= checksum + din_data;
        checksum    <= 0;
      end else begin
        pos      <= pos + 1;
        checksum <= checksum + din_data;
      end
    end

    if (rst) begin
      checksum    <= 0;
      pos         <= 0;
      frame_count <= 0;
    end
  end

  assign din_ready = 1;

endmodule