data/full_repos/permissive/169496369/mux_32.v
data/verilator_xmls/ca02ed11-8fcc-4f12-9eaf-0a2778dea22b.xml
module mux_32(a, b, s, c);
    input [31:0] a, b;
    input s;
    
    output [31:0] c;
    
    assign c = (s ? b : a);
endmodule
module mux_32(a, b, s, c);

    input [31:0] a, b;
    input s;
    
    output [31:0] c;
    
    assign c = (s ? b : a);
endmodule