data/full_repos/permissive/135622446/trig2_board_firmware/LED_4.v
Syntax Error
1: b'%Warning-WIDTH: data/full_repos/permissive/135622446/trig2_board_firmware/LED_4.v:33: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'firingticks\' generates 8 bits.\n                                                                                    : ... In instance LED_4\n   if (firingcounter >= deadticks*4 + firingticks) begin  \n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module LED_4(
	input nrst,
	input clk,
	inout reg [3:0]led,
	input [15:0] coax_in,
	output reg [15:0] coax_out,	
	input [7:0] deadticks, input [7:0] firingticks);
		

	integer state=READY;
	localparam READY=0, FIRING=1, DEAD=2;
	integer firingcounter=0;
	always@(posedge clk) begin		
	case (state)
		READY: begin
			firingcounter<=0;
			coax_out <= 0;

			if ( coax_in >0) begin
				state = FIRING;
			end
		end
		FIRING: begin
			firingcounter <= firingcounter+1;
			coax_out <= 16'hffff;
			if (firingcounter >= firingticks) begin
				state = DEAD;
			end
		end
		DEAD: begin
			firingcounter <= firingcounter+1;
			coax_out <= 0;
			if (firingcounter >= deadticks*4 + firingticks) begin
				state = READY;
			end
		end
	endcase
	end	
	

	integer counter;
	reg clk2;
	always@(posedge clk) begin
		if(!nrst) begin
			counter <= 0;
			clk2 <= 0;
		end
		else if (counter == 100000000) begin
			counter <= 0;
			clk2 = ~clk2;
		end
		else counter <= counter + 32'd1;
	end
	reg [1:0] ledi;	
	always@(posedge clk2) begin
		case (ledi)
		0:	begin led <= 4'b1110;ledi<=ledi+2'b01; end
		1:	begin led <= 4'b1101;ledi<=ledi+2'b01; end
		2:	begin led <= 4'b1011;ledi<=ledi+2'b01; end
		3:	begin led <= 4'b0111;ledi<=ledi+2'b01; end
		endcase			
	end
	
endmodule
module LED_4(
	input nrst,
	input clk,
	inout reg [3:0]led,
	input [15:0] coax_in,
	output reg [15:0] coax_out,	
	input [7:0] deadticks, input [7:0] firingticks);

		

	integer state=READY;
	localparam READY=0, FIRING=1, DEAD=2;
	integer firingcounter=0;
	always@(posedge clk) begin		
	case (state)
		READY: begin
			firingcounter<=0;
			coax_out <= 0;

			if ( coax_in >0) begin
				state = FIRING;
			end
		end
		FIRING: begin
			firingcounter <= firingcounter+1;
			coax_out <= 16'hffff;
			if (firingcounter >= firingticks) begin
				state = DEAD;
			end
		end
		DEAD: begin
			firingcounter <= firingcounter+1;
			coax_out <= 0;
			if (firingcounter >= deadticks*4 + firingticks) begin
				state = READY;
			end
		end
	endcase
	end	
	

	integer counter;
	reg clk2;
	always@(posedge clk) begin
		if(!nrst) begin
			counter <= 0;
			clk2 <= 0;
		end
		else if (counter == 100000000) begin
			counter <= 0;
			clk2 = ~clk2;
		end
		else counter <= counter + 32'd1;
	end
	reg [1:0] ledi;	
	always@(posedge clk2) begin
		case (ledi)
		0:	begin led <= 4'b1110;ledi<=ledi+2'b01; end
		1:	begin led <= 4'b1101;ledi<=ledi+2'b01; end
		2:	begin led <= 4'b1011;ledi<=ledi+2'b01; end
		3:	begin led <= 4'b0111;ledi<=ledi+2'b01; end
		endcase			
	end
	
endmodule