data/full_repos/permissive/219219909/Complex_Multiplier/buf5.v
data/verilator_xmls/fcf732c2-d059-4ff0-beac-6bda6d8a696a.xml
module buf5(
    input [31:0] C,
    output reg [31:0] C1,
    input CLK
    );

always @(posedge CLK) begin
C1<=C;
end
endmodule
module buf5(
    input [31:0] C,
    output reg [31:0] C1,
    input CLK
    );


always @(posedge CLK) begin
C1<=C;
end
endmodule