data/full_repos/permissive/104443190/chen_div.v
 line:13: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:14: Unsupported: Ignoring delay on this delayed statement.\n initial #30 rst=1;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:15: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n       ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module shift_compute#( parameter width=64 )( clk,a_i,b_i,a_o,b_o );
	input clk;
	input [width-1:0] a_i,b_i;
	output reg [width-1:0] a_o,b_o;

	wire [width-1:0] temp_a,temp_b;
	assign temp_a = {a_i[width-2:0],1'b0};
	assign temp_b = b_i;

	always@(posedge clk)
	begin
		if(temp_a[width-1:width/2] >= temp_b[width-1:width/2])  
            a_o <= temp_a - temp_b + 1'b1;  
        else  
            a_o <= temp_a;
        b_o <= temp_b;
	end

endmodule
module shift_compute#( parameter width=64 )( clk,a_i,b_i,a_o,b_o );

	input clk;
	input [width-1:0] a_i,b_i;
	output reg [width-1:0] a_o,b_o;

	wire [width-1:0] temp_a,temp_b;
	assign temp_a = {a_i[width-2:0],1'b0};
	assign temp_b = b_i;

	always@(posedge clk)
	begin
		if(temp_a[width-1:width/2] >= temp_b[width-1:width/2])  
            a_o <= temp_a - temp_b + 1'b1;  
        else  
            a_o <= temp_a;
        b_o <= temp_b;
	end

endmodule