data/full_repos/permissive/200478172/source/ControlUnit.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:100: Operator VAR \'ADDU\' expects 13 bits on the Initial value, but Initial value\'s CONST \'6\'h21\' generates 6 bits.\n                                                                             : ... In instance ControlUnit\n    parameter [12:0] ADDU = 6\'b000000_100001, \n                     ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:101: Operator VAR \'AND\' expects 13 bits on the Initial value, but Initial value\'s CONST \'6\'h24\' generates 6 bits.\n                                                                             : ... In instance ControlUnit\n                       AND = 6\'b000000_100100, \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:102: Operator VAR \'JR\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h8\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       JR = 12\'b000000_001000, \n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:103: Operator VAR \'XOR\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h26\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       XOR = 12\'b000000_100110, \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:104: Operator VAR \'NOR\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h27\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       NOR = 12\'b000000_100111, \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:105: Operator VAR \'OR\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h25\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       OR = 12\'b000000_100101, \n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:106: Operator VAR \'SLL\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h0\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       SLL = 12\'b000000_000000, \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:107: Operator VAR \'SLLV\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h4\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       SLLV = 12\'b000000_000100, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:108: Operator VAR \'SLTU\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h2b\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       SLTU = 12\'b000000_101011, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:109: Operator VAR \'SRA\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h3\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       SRA = 12\'b000000_000011, \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:110: Operator VAR \'SRL\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h2\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       SRL = 12\'b000000_000010, \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:111: Operator VAR \'SUBU\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h23\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       SUBU = 12\'b000000_100011, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:112: Operator VAR \'ADD\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h20\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       ADD = 12\'b000000_100000, \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:113: Operator VAR \'SUB\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h22\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       SUB = 12\'b000000_100010, \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:114: Operator VAR \'SLT\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h2a\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       SLT = 12\'b000000_101010, \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:115: Operator VAR \'SRLV\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h6\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       SRLV = 12\'b000000_000110, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:116: Operator VAR \'SRAV\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h7\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       SRAV = 12\'b000000_000111, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:117: Operator VAR \'CLZ\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h720\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       CLZ = 12\'b011100_100000, \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:118: Operator VAR \'DIVU\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h1b\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       DIVU = 12\'b000000_011011, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:119: Operator VAR \'ERET\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h418\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       ERET = 12\'b010000_011000, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:120: Operator VAR \'JALR\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h9\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       JALR = 12\'b000000_001001, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:121: Operator VAR \'MFC0\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h400\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       MFC0 = 12\'b010000_000000, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:122: Operator VAR \'MFHI\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h10\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       MFHI = 12\'b000000_010000, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:123: Operator VAR \'MFLO\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h12\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       MFLO = 12\'b000000_010010, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:124: Operator VAR \'MTC0\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h400\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       MTC0 = 12\'b010000_000000, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:125: Operator VAR \'MTHI\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h11\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       MTHI = 12\'b000000_010001, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:126: Operator VAR \'MTLO\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h13\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       MTLO = 12\'b000000_010011, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:128: Operator VAR \'MUL\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h702\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       MUL = 12\'b011100_000010,\n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:129: Operator VAR \'MULT\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h18\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       MULT = 12\'b000000_011000, \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:130: Operator VAR \'MULTU\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h19\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       MULTU = 12\'b000000_011001, \n                       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:131: Operator VAR \'SYSCALL\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'hc\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       SYSCALL = 12\'b000000_001100, \n                       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:132: Operator VAR \'TEQ\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h34\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       TEQ = 12\'b000000_110100, \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:133: Operator VAR \'BREAK\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'hd\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       BREAK = 12\'b000000_001101, \n                       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:134: Operator VAR \'DIV\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h1a\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                       DIV = 12\'b000000_011010; \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:171: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SYSCALL||inst_tag==BREAK||inst_tag==ERET)\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:171: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SYSCALL||inst_tag==BREAK||inst_tag==ERET)\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:171: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SYSCALL||inst_tag==BREAK||inst_tag==ERET)\n                                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:169: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MFC0||inst_tag==MFHI||inst_tag==MFLO||inst_tag==MTC0||inst_tag==MTHI||inst_tag==MTLO)\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:169: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MFC0||inst_tag==MFHI||inst_tag==MFLO||inst_tag==MTC0||inst_tag==MTHI||inst_tag==MTLO)\n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:169: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MFC0||inst_tag==MFHI||inst_tag==MFLO||inst_tag==MTC0||inst_tag==MTHI||inst_tag==MTLO)\n                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:169: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MFC0||inst_tag==MFHI||inst_tag==MFLO||inst_tag==MTC0||inst_tag==MTHI||inst_tag==MTLO)\n                                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:169: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MFC0||inst_tag==MFHI||inst_tag==MFLO||inst_tag==MTC0||inst_tag==MTHI||inst_tag==MTLO)\n                                                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:169: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MFC0||inst_tag==MFHI||inst_tag==MFLO||inst_tag==MTC0||inst_tag==MTHI||inst_tag==MTLO)\n                                                                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:167: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MUL||inst_tag==MULTU||inst_tag==DIV||inst_tag==DIVU||inst_tag==MULT)\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:167: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MUL||inst_tag==MULTU||inst_tag==DIV||inst_tag==DIVU||inst_tag==MULT)\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:167: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MUL||inst_tag==MULTU||inst_tag==DIV||inst_tag==DIVU||inst_tag==MULT)\n                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:167: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MUL||inst_tag==MULTU||inst_tag==DIV||inst_tag==DIVU||inst_tag==MULT)\n                                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:167: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MUL||inst_tag==MULTU||inst_tag==DIV||inst_tag==DIVU||inst_tag==MULT)\n                                                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:165: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==CLZ)\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:161: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag1==BEQ||inst_tag1==BNE||inst_tag1==BGEZ||inst_tag==TEQ)\n                                                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:159: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag1==J||inst_tag==JR||inst==0)\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:157: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag1==JAL||inst_tag==JALR)\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:181: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==MUL)\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:194: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==TEQ&&ALUzero==1)next_state<=SBRK;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:232: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'bzz\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n            LT_ctr<=2\'bzz;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:265: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'bzz\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n                LT_ctr<=2\'bzz;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:299: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==JALR)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:311: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==JR)C_MUXP<=2\'b10;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:323: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==JALR)C_MUXP<=2\'b10;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:397: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==CLZ)C_MUXD<=3\'b110;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:427: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n                    C_MUXH<=2\'b000;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:428: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n                    C_MUXL<=2\'b000;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:432: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n                    C_MUXH<=2\'b000;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:433: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n                    C_MUXL<=2\'b000;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:437: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n                     C_MUXH<=2\'b001;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:438: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n                     C_MUXL<=2\'b001;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:442: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n                     C_MUXH<=2\'b010;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:443: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n                     C_MUXL<=2\'b010;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:447: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n                     C_MUXH<=2\'b011;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:448: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                             : ... In instance ControlUnit\n                     C_MUXL<=2\'b011;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:445: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==DIVU)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:440: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==DIV)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:435: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MULTU)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:430: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MUL)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:425: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==MULT)begin\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:459: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==MTLO)begin\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:492: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MTC0)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:485: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MFHI)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:478: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MUL)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:471: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==MFLO)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:465: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==MTHI)begin\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:525: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==ERET)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:521: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==BREAK)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:517: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==TEQ)begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:513: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==SYSCALL)begin\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:538: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SLL||inst_tag==SRL||inst_tag==SRA)     \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:538: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SLL||inst_tag==SRL||inst_tag==SRA)     \n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:538: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SLL||inst_tag==SRL||inst_tag==SRA)     \n                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:537: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==SLLV||inst_tag==SRLV||inst_tag==SRAV)C_MUXA<=2\'b10;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:537: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==SLLV||inst_tag==SRLV||inst_tag==SRAV)C_MUXA<=2\'b10;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:537: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==SLLV||inst_tag==SRLV||inst_tag==SRAV)C_MUXA<=2\'b10;\n                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:546: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==SLL||inst_tag==SRL||inst_tag==SRA)C_MUXC<=2\'b10;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:546: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==SLL||inst_tag==SRL||inst_tag==SRA)C_MUXC<=2\'b10;\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:546: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==SLL||inst_tag==SRL||inst_tag==SRA)C_MUXC<=2\'b10;\n                                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:566: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SRA||inst_tag==SRAV)ALU_op<=4\'b1100;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:566: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SRA||inst_tag==SRAV)ALU_op<=4\'b1100;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:565: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SRL||inst_tag==SRLV)ALU_op<=4\'b1101;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:565: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SRL||inst_tag==SRLV)ALU_op<=4\'b1101;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:564: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SLL||inst_tag==SLLV)ALU_op<=4\'b1110;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:564: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SLL||inst_tag==SLLV)ALU_op<=4\'b1110;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:562: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SUBU)ALU_op<=4\'b0001;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:561: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SUB)ALU_op<=4\'b0011;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:560: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==NOR)ALU_op<=4\'b0111;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:559: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SLTU||inst_tag1==SLTIU)ALU_op<=4\'b1010;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:558: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==SLT||inst_tag1==SLTI)ALU_op<=4\'b1011;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:557: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==XOR||inst_tag1==XORI)ALU_op<=4\'b0110;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:556: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==OR||inst_tag1==ORI)ALU_op<=4\'b0101;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:555: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==AND||inst_tag1==ANDI)ALU_op<=4\'b0100;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:554: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                else if(inst_tag==ADDU||inst_tag1==ADDIU)ALU_op<=4\'b0000;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/200478172/source/ControlUnit.v:553: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'inst_tag\' generates 12 bits.\n                                                                             : ... In instance ControlUnit\n                if(inst_tag==ADD||inst_tag1==ADDI)ALU_op<=4\'b0010;\n                           ^~\n%Error: Exiting due to 110 warning(s)\n'
module ControlUnit(
    input clk,
    input reset,
    input [31:0] inst,
    input ALUzero,
    input ALUnega,
    
    output reg PC_ctr,
    output reg PC_ena,
    output reg IM_ctr,
    output reg Z_ctr,
    output reg Write_ena,
    output reg [3:0] ALU_op,
    output reg ALU_ctr,
    output reg II_ctr,
    output reg [1:0] C_MUXA,
    output reg [1:0] C_MUXB,
    output reg [1:0] C_MUXC,
    output reg [2:0] C_MUXD,
    output reg [2:0] C_MUXH,
    output reg [2:0] C_MUXL,
    output reg [1:0] C_MUXP,
    output reg [1:0] C_MUXADDR,
    output reg [1:0] DM_W,
    output reg [2:0] LT_ctr,
    output reg HI_ctr,
    output reg LO_ctr,
    output reg CLZ_ctr,
    output reg MUL_ctr,
    output reg MULTU_ctr,
    output reg DIV_ctr,
    output reg DIVU_ctr,
    output reg mfc0,
    output reg mtc0,
    output reg expection,
    output reg [3:0] cause,
    output reg eret,
    output reg finish,
    
    output reg state_out
    );
    parameter [3:0] SIF = 4'b0000,
	                  SID = 4'b0001,
                      SEXE_J = 4'b0010,
					  SEXE_ALU = 4'b0011,
					  SEXE_B = 4'b0100,
					  SEXE_B1 = 4'b0101,
					  SEXE_LS = 4'b0110,
					  SEXE_LS1 = 4'b0111,
					  SWB = 4'b1000,
					  SCLZ= 4'b1001,
				      SMD= 4'b1010,
				      SHL=4'b1011,
					  SBRK=4'b1100;
					  	  
	 parameter [5:0]ADDI = 6'b001000,
                     ADDIU = 6'b001001,
                     ANDI = 6'b001100,
                     ORI = 6'b001101,
                     SLTIU = 6'b001011,
                     LUI = 6'b001111,
                     XORI = 6'b001110,
                     SLTI = 6'b001010,
                     BEQ = 6'b000100,
                     BNE = 6'b000101,
                     J = 6'b000010,
                     JAL = 6'b000011,
                     LW = 6'b100011,
                     SW = 6'b101011,
                     LB = 6'b100000,
                     LBU = 6'b100100,
                     LHU = 6'b100101,
                     SB = 6'b101000,
                     SH = 6'b101001,
                     LH = 6'b100001,
                     BGEZ = 6'b000001;
                                     
    parameter [12:0] ADDU = 6'b000000_100001,
                       AND = 6'b000000_100100,
                       JR = 12'b000000_001000,
                       XOR = 12'b000000_100110,
                       NOR = 12'b000000_100111,
                       OR = 12'b000000_100101,
                       SLL = 12'b000000_000000,
                       SLLV = 12'b000000_000100,
                       SLTU = 12'b000000_101011,
                       SRA = 12'b000000_000011,
                       SRL = 12'b000000_000010,
                       SUBU = 12'b000000_100011,
                       ADD = 12'b000000_100000,
                       SUB = 12'b000000_100010,
                       SLT = 12'b000000_101010,
                       SRLV = 12'b000000_000110,
                       SRAV = 12'b000000_000111,
                       CLZ = 12'b011100_100000,
                       DIVU = 12'b000000_011011,
                       ERET = 12'b010000_011000,
                       JALR = 12'b000000_001001,
                       MFC0 = 12'b010000_000000,
                       MFHI = 12'b000000_010000,
                       MFLO = 12'b000000_010010,
                       MTC0 = 12'b010000_000000,
                       MTHI = 12'b000000_010001,
                       MTLO = 12'b000000_010011,

                       MUL = 12'b011100_000010,
                       MULT = 12'b000000_011000,
                       MULTU = 12'b000000_011001,
                       SYSCALL = 12'b000000_001100,
                       TEQ = 12'b000000_110100,
                       BREAK = 12'b000000_001101,
                       DIV = 12'b000000_011010;
                       
	 reg [3:0] state;
	 reg [3:0] next_state;
     reg [11:0] inst_tag;
     reg [5:0] inst_tag1;
     reg [4:0] jump_tag;
     reg [4:0] CP0_tag;
     
    always@(posedge clk or posedge reset)begin
        if(reset==1)begin
            state<=SIF;
            state_out<=1;
        end
        else 
            state<=next_state;
    end

    always@(*)begin
        case(state)
            SIF:next_state<=SID;

            SID:begin
                if(inst_tag1==JAL||inst_tag==JALR)
                    next_state<=SEXE_J;
                else if(inst_tag1==J||inst_tag==JR||inst==0)
                    next_state<=SIF;
                else if(inst_tag1==BEQ||inst_tag1==BNE||inst_tag1==BGEZ||inst_tag==TEQ)
                    next_state<=SEXE_B;
                else if(inst_tag1==LB||inst_tag1==LBU||inst_tag1==LH||inst_tag1==LHU||inst_tag1==LW||inst_tag1==SB||inst_tag1==SH||inst_tag1==SW)
                    next_state<=SEXE_LS;
                else if(inst_tag==CLZ)
                    next_state<=SCLZ;
                else if(inst_tag==MUL||inst_tag==MULTU||inst_tag==DIV||inst_tag==DIVU||inst_tag==MULT)
                    next_state<=SMD;
                else if(inst_tag==MFC0||inst_tag==MFHI||inst_tag==MFLO||inst_tag==MTC0||inst_tag==MTHI||inst_tag==MTLO)
                    next_state<=SHL;
                else if(inst_tag==SYSCALL||inst_tag==BREAK||inst_tag==ERET)
                    next_state<=SBRK;
                else next_state<=SEXE_ALU;
            end
            
            SBRK:next_state<=SIF;
            
            SHL:next_state<=SIF;
            
            SMD:begin
                if(inst_tag==MUL)
                    next_state<=SHL;
                else 
                    next_state<=SIF;
            end
            
            SEXE_J:next_state<=SIF;
            
            SEXE_B:begin
                if(inst_tag1==BEQ&&ALUzero==1)next_state<=SEXE_B1;
                else if(inst_tag1==BNE&&ALUzero==0)next_state<=SEXE_B1;
                else if(inst_tag1==BGEZ&&ALUnega==0)
                    next_state<=SEXE_B1;
                else if(inst_tag==TEQ&&ALUzero==1)next_state<=SBRK;
                else next_state<=SIF;
            end
            
            SEXE_B1:next_state<=SIF;
            
            SEXE_LS:next_state<=SEXE_LS1;
            
            SEXE_LS1:next_state<=SIF;
            
            SEXE_ALU:next_state<=SWB;
            
            SCLZ:next_state<=SWB;
            
            SWB:next_state<=SIF;
        endcase
        if(next_state==SIF)finish<=1;
        else finish<=0;
    end

    always@(*)begin
        if(reset)begin
            PC_ctr<=0;
            PC_ena<=0;
            IM_ctr<=0;
            Z_ctr<=0;
            Write_ena<=0;
            ALU_op<=4'b0000;
            ALU_ctr<=0;
            C_MUXA<=2'b00;
            C_MUXB<=2'b00;
            C_MUXC<=2'bzz;
            C_MUXD<=3'bzzz;
            C_MUXH<=3'bzzz;
            C_MUXL<=3'bzzz;
            C_MUXP<=2'b00;
            C_MUXADDR<=2'bzz;
            DM_W<=2'bzz;
            LT_ctr<=2'bzz;
            CLZ_ctr<=0;
            HI_ctr<=0;
            LO_ctr<=0;
            MUL_ctr<=0;
            MULTU_ctr<=0;
            DIV_ctr<=0;
            DIVU_ctr<=0;
            mtc0<=0;
            mfc0<=0;
            expection<=0;
            eret<=0;
            cause<=4'b0000;
            II_ctr<=0;
        end
        case(state)
            SIF:begin
                PC_ctr<=1;
                PC_ena<=0;
                IM_ctr<=1;
                Z_ctr<=1;
                Write_ena<=0;
                ALU_op<=4'b0000;
                ALU_ctr<=1;
                C_MUXA<=2'b00;
                C_MUXB<=2'b00;
                C_MUXC<=2'bzz;
                C_MUXP<=2'b00;
                C_MUXD<=3'bzzz;
                C_MUXH<=3'bzzz;
                C_MUXL<=3'bzzz;
                C_MUXADDR<=2'bzz;
                DM_W<=2'bzz;
                LT_ctr<=2'bzz;
                CLZ_ctr<=0;
                HI_ctr<=0;
                LO_ctr<=0;
                MUL_ctr<=0;
                MULTU_ctr<=0;
                DIV_ctr<=0;
                DIVU_ctr<=0;
                mtc0<=0;
                mfc0<=0;
                expection<=0;
                eret<=0;
                cause<=4'b0000;
                II_ctr<=0;
                
                inst_tag <= {inst[31:26],inst[5:0]};
                inst_tag1<=inst[31:26];
                jump_tag<=inst[20:16];
                CP0_tag<=inst[25:21];
            end

            SID:begin
                PC_ctr<=1;
                PC_ena<=1;
                              
                IM_ctr<=0;
                Z_ctr<=0;
                ALU_ctr<=0;
                if(inst_tag1==JAL)begin
                    II_ctr<=1;
                    Write_ena<=1;
                    C_MUXD<=3'b000;
                    C_MUXADDR<=2'b10;
                end
                else if(inst_tag==JALR)begin
                     Write_ena<=1;
                     C_MUXD<=3'b000;
                     if(jump_tag==5'b00000)C_MUXADDR<=2'b10;
                     else C_MUXADDR<=2'b00;
                     end
                else Write_ena<=0;
                
                if(inst_tag1==J)begin
                    C_MUXP<=2'b01;
                    II_ctr<=1;
                end
                else if(inst_tag==JR)C_MUXP<=2'b10;
                else C_MUXP<=2'b00;
            end

            SEXE_J:begin
                PC_ctr<=1;
                PC_ena<=1;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=0;
                ALU_ctr<=0;
                if(inst_tag1==JAL)C_MUXP<=2'b01;
                else if(inst_tag==JALR)C_MUXP<=2'b10;
            end

            SEXE_B:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=1;
                Write_ena<=0;
                ALU_op<=4'b0011;
                ALU_ctr<=1;
                C_MUXA<=2'b01;
                if(inst_tag1==BGEZ)C_MUXB<=2'b11;
                else C_MUXB<=2'b01;
            end

            SEXE_B1:begin
                PC_ctr<=1;
                PC_ena<=1;
                IM_ctr<=0;
                Z_ctr<=1;
                Write_ena<=0;
                ALU_op<=4'b0010;
                ALU_ctr<=1;
                C_MUXA<=2'b00;
                C_MUXB<=2'b10;
                C_MUXC<=2'b11;
                C_MUXP<=2'b00;
            end

            SEXE_LS:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=1;
                Write_ena<=0;
                ALU_op<=4'b0010;
                ALU_ctr<=1;
                C_MUXA<=2'b01;
                C_MUXB<=2'b10;
                C_MUXC<=2'b00;
            end

            SEXE_LS1:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=0;
                ALU_ctr<=0;
                if(inst_tag1==LB||inst_tag1==LBU||inst_tag1==LH||inst_tag1==LHU||inst_tag1==LW)begin
                    Write_ena<=1;
                    C_MUXD<=3'b010;
                    C_MUXADDR<=2'b01;
                end
                else Write_ena<=0;

                if(inst_tag1==LB)LT_ctr<=3'b001;
                else if(inst_tag1==LBU)LT_ctr<=3'b010;
                else if(inst_tag1==LH)LT_ctr<=3'b011;
                else if(inst_tag1==LHU)LT_ctr<=3'b100;
                else if(inst_tag1==LW)LT_ctr<=3'b000;
                
                if(inst_tag1==SB)DM_W<=2'b11;
                else if(inst_tag1==SH)DM_W<=2'b10;
                else if(inst_tag1==SW)DM_W<=2'b01;
            end

            SWB:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=1;
                ALU_ctr<=0;
                if(inst_tag==CLZ)C_MUXD<=3'b110;
                else C_MUXD<=3'b001;
                               
                if(inst_tag1==ADDI||inst_tag1==ADDIU||inst_tag1==ANDI||inst_tag1==ORI||inst_tag1==XORI||inst_tag1==LUI||inst_tag1==SLTI||inst_tag1==SLTIU)
                    C_MUXADDR<=2'b01;
                else C_MUXADDR<=2'b00; 
            end
            
            SCLZ:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=0;
                ALU_ctr<=0;
                C_MUXA<=1;
                CLZ_ctr<=1;
            end
            
            SMD:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=0;
                ALU_ctr<=0;
                HI_ctr<=1;
                LO_ctr<=1;
                if(inst_tag==MULT)begin
                    MUL_ctr<=1;
                    C_MUXH<=2'b000;
                    C_MUXL<=2'b000;
                end
                else if(inst_tag==MUL)begin
                    MUL_ctr<=1;
                    C_MUXH<=2'b000;
                    C_MUXL<=2'b000;
                end
                else if(inst_tag==MULTU)begin
                     MULTU_ctr<=1;
                     C_MUXH<=2'b001;
                     C_MUXL<=2'b001;
                end
                else if(inst_tag==DIV)begin
                     DIV_ctr<=1;
                     C_MUXH<=2'b010;
                     C_MUXL<=2'b010;
                end
                else if(inst_tag==DIVU)begin
                     DIVU_ctr<=1;
                     C_MUXH<=2'b011;
                     C_MUXL<=2'b011;
                end                
            end
            
            SHL:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=0;
                ALU_ctr<=0;
                if(inst_tag==MTLO)begin
                    C_MUXH<=3'b100;
                    C_MUXL<=3'b100;
                    HI_ctr<=0;
                    LO_ctr<=1;
                end
                if(inst_tag==MTHI)begin
                    C_MUXH<=3'b100;
                    C_MUXL<=3'b100;
                    HI_ctr<=1;
                    LO_ctr<=0;
                    end
                else if(inst_tag==MFLO)begin
                    HI_ctr<=0;
                    LO_ctr<=0;
                    C_MUXADDR<=2'b00;
                    C_MUXD<=3'b100;
                    Write_ena<=1;
                end
                else if(inst_tag==MUL)begin
                    HI_ctr<=0;
                    LO_ctr<=0;
                    C_MUXADDR<=2'b00;
                    C_MUXD<=3'b100;
                    Write_ena<=1;
                end
                else if(inst_tag==MFHI)begin
                     HI_ctr<=0;
                     LO_ctr<=0;
                     C_MUXADDR<=2'b00;
                     C_MUXD<=3'b011;
                     Write_ena<=1;
                end
                else if(inst_tag==MTC0)begin
                     if(CP0_tag==5'b00000)begin
                        mfc0<=1;
                        C_MUXADDR<=2'b01;
                        Write_ena<=1;
                        C_MUXD<=3'b101;
                     end
                     else begin
                        mtc0<=1;
                     end
                end
            end
            
            SBRK:begin
                PC_ctr<=1;
                PC_ena<=1;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=0;
                ALU_ctr<=0;
                C_MUXP<=2'b11;
                if(inst_tag==SYSCALL)begin
                    cause<=4'b1000;
                    expection<=1;
                end
                else if(inst_tag==TEQ)begin
                    cause<=4'b1101;
                    expection<=1;
                end
                else if(inst_tag==BREAK)begin
                    cause<=4'b1001;
                    expection<=1;
                end
                else if(inst_tag==ERET)begin
                    eret<=1;
                end
            end      
            
            SEXE_ALU:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=1;
                Write_ena<=0;
                ALU_ctr<=1;
                if(inst_tag==SLLV||inst_tag==SRLV||inst_tag==SRAV)C_MUXA<=2'b10;
                else if(inst_tag==SLL||inst_tag==SRL||inst_tag==SRA)     
                    C_MUXA<=2'b11;          
                else C_MUXA<=2'b01;
                
                if(inst_tag1==ADDI||inst_tag1==ADDIU||inst_tag1==ANDI||inst_tag1==ORI||inst_tag1==XORI||inst_tag1==LUI||inst_tag1==SLTI||inst_tag1==SLTIU)
                    C_MUXB<=2'b10;
                else C_MUXB<=2'b01;
                
                if(inst_tag==SLL||inst_tag==SRL||inst_tag==SRA)C_MUXC<=2'b10;
                else if(inst_tag1==ANDI||inst_tag1==ORI||inst_tag1==XORI||inst_tag1==SLTIU||inst_tag1==LUI)
                    C_MUXC<=2'b01;
                else if(inst_tag1==ADDI||inst_tag1==SLTI||inst_tag1==ADDIU)
                    C_MUXC<=2'b00;

                    
                if(inst_tag==ADD||inst_tag1==ADDI)ALU_op<=4'b0010;
                else if(inst_tag==ADDU||inst_tag1==ADDIU)ALU_op<=4'b0000;
                else if(inst_tag==AND||inst_tag1==ANDI)ALU_op<=4'b0100;
                else if(inst_tag==OR||inst_tag1==ORI)ALU_op<=4'b0101;
                else if(inst_tag==XOR||inst_tag1==XORI)ALU_op<=4'b0110;
                else if(inst_tag==SLT||inst_tag1==SLTI)ALU_op<=4'b1011;
                else if(inst_tag==SLTU||inst_tag1==SLTIU)ALU_op<=4'b1010;
                else if(inst_tag==NOR)ALU_op<=4'b0111;
                else if(inst_tag==SUB)ALU_op<=4'b0011;
                else if(inst_tag==SUBU)ALU_op<=4'b0001;
                else if(inst_tag1==LUI)ALU_op<=4'b1000;
                else if(inst_tag==SLL||inst_tag==SLLV)ALU_op<=4'b1110;
                else if(inst_tag==SRL||inst_tag==SRLV)ALU_op<=4'b1101;
                else if(inst_tag==SRA||inst_tag==SRAV)ALU_op<=4'b1100;
            end
        endcase
    end
endmodule
module ControlUnit(
    input clk,
    input reset,
    input [31:0] inst,
    input ALUzero,
    input ALUnega,
    
    output reg PC_ctr,
    output reg PC_ena,
    output reg IM_ctr,
    output reg Z_ctr,
    output reg Write_ena,
    output reg [3:0] ALU_op,
    output reg ALU_ctr,
    output reg II_ctr,
    output reg [1:0] C_MUXA,
    output reg [1:0] C_MUXB,
    output reg [1:0] C_MUXC,
    output reg [2:0] C_MUXD,
    output reg [2:0] C_MUXH,
    output reg [2:0] C_MUXL,
    output reg [1:0] C_MUXP,
    output reg [1:0] C_MUXADDR,
    output reg [1:0] DM_W,
    output reg [2:0] LT_ctr,
    output reg HI_ctr,
    output reg LO_ctr,
    output reg CLZ_ctr,
    output reg MUL_ctr,
    output reg MULTU_ctr,
    output reg DIV_ctr,
    output reg DIVU_ctr,
    output reg mfc0,
    output reg mtc0,
    output reg expection,
    output reg [3:0] cause,
    output reg eret,
    output reg finish,
    
    output reg state_out
    );

    parameter [3:0] SIF = 4'b0000,
	                  SID = 4'b0001,
                      SEXE_J = 4'b0010,
					  SEXE_ALU = 4'b0011,
					  SEXE_B = 4'b0100,
					  SEXE_B1 = 4'b0101,
					  SEXE_LS = 4'b0110,
					  SEXE_LS1 = 4'b0111,
					  SWB = 4'b1000,
					  SCLZ= 4'b1001,
				      SMD= 4'b1010,
				      SHL=4'b1011,
					  SBRK=4'b1100;
					  	  
	 parameter [5:0]ADDI = 6'b001000,
                     ADDIU = 6'b001001,
                     ANDI = 6'b001100,
                     ORI = 6'b001101,
                     SLTIU = 6'b001011,
                     LUI = 6'b001111,
                     XORI = 6'b001110,
                     SLTI = 6'b001010,
                     BEQ = 6'b000100,
                     BNE = 6'b000101,
                     J = 6'b000010,
                     JAL = 6'b000011,
                     LW = 6'b100011,
                     SW = 6'b101011,
                     LB = 6'b100000,
                     LBU = 6'b100100,
                     LHU = 6'b100101,
                     SB = 6'b101000,
                     SH = 6'b101001,
                     LH = 6'b100001,
                     BGEZ = 6'b000001;
                                     
    parameter [12:0] ADDU = 6'b000000_100001,
                       AND = 6'b000000_100100,
                       JR = 12'b000000_001000,
                       XOR = 12'b000000_100110,
                       NOR = 12'b000000_100111,
                       OR = 12'b000000_100101,
                       SLL = 12'b000000_000000,
                       SLLV = 12'b000000_000100,
                       SLTU = 12'b000000_101011,
                       SRA = 12'b000000_000011,
                       SRL = 12'b000000_000010,
                       SUBU = 12'b000000_100011,
                       ADD = 12'b000000_100000,
                       SUB = 12'b000000_100010,
                       SLT = 12'b000000_101010,
                       SRLV = 12'b000000_000110,
                       SRAV = 12'b000000_000111,
                       CLZ = 12'b011100_100000,
                       DIVU = 12'b000000_011011,
                       ERET = 12'b010000_011000,
                       JALR = 12'b000000_001001,
                       MFC0 = 12'b010000_000000,
                       MFHI = 12'b000000_010000,
                       MFLO = 12'b000000_010010,
                       MTC0 = 12'b010000_000000,
                       MTHI = 12'b000000_010001,
                       MTLO = 12'b000000_010011,

                       MUL = 12'b011100_000010,
                       MULT = 12'b000000_011000,
                       MULTU = 12'b000000_011001,
                       SYSCALL = 12'b000000_001100,
                       TEQ = 12'b000000_110100,
                       BREAK = 12'b000000_001101,
                       DIV = 12'b000000_011010;
                       
	 reg [3:0] state;
	 reg [3:0] next_state;
     reg [11:0] inst_tag;
     reg [5:0] inst_tag1;
     reg [4:0] jump_tag;
     reg [4:0] CP0_tag;
     
    always@(posedge clk or posedge reset)begin
        if(reset==1)begin
            state<=SIF;
            state_out<=1;
        end
        else 
            state<=next_state;
    end

    always@(*)begin
        case(state)
            SIF:next_state<=SID;

            SID:begin
                if(inst_tag1==JAL||inst_tag==JALR)
                    next_state<=SEXE_J;
                else if(inst_tag1==J||inst_tag==JR||inst==0)
                    next_state<=SIF;
                else if(inst_tag1==BEQ||inst_tag1==BNE||inst_tag1==BGEZ||inst_tag==TEQ)
                    next_state<=SEXE_B;
                else if(inst_tag1==LB||inst_tag1==LBU||inst_tag1==LH||inst_tag1==LHU||inst_tag1==LW||inst_tag1==SB||inst_tag1==SH||inst_tag1==SW)
                    next_state<=SEXE_LS;
                else if(inst_tag==CLZ)
                    next_state<=SCLZ;
                else if(inst_tag==MUL||inst_tag==MULTU||inst_tag==DIV||inst_tag==DIVU||inst_tag==MULT)
                    next_state<=SMD;
                else if(inst_tag==MFC0||inst_tag==MFHI||inst_tag==MFLO||inst_tag==MTC0||inst_tag==MTHI||inst_tag==MTLO)
                    next_state<=SHL;
                else if(inst_tag==SYSCALL||inst_tag==BREAK||inst_tag==ERET)
                    next_state<=SBRK;
                else next_state<=SEXE_ALU;
            end
            
            SBRK:next_state<=SIF;
            
            SHL:next_state<=SIF;
            
            SMD:begin
                if(inst_tag==MUL)
                    next_state<=SHL;
                else 
                    next_state<=SIF;
            end
            
            SEXE_J:next_state<=SIF;
            
            SEXE_B:begin
                if(inst_tag1==BEQ&&ALUzero==1)next_state<=SEXE_B1;
                else if(inst_tag1==BNE&&ALUzero==0)next_state<=SEXE_B1;
                else if(inst_tag1==BGEZ&&ALUnega==0)
                    next_state<=SEXE_B1;
                else if(inst_tag==TEQ&&ALUzero==1)next_state<=SBRK;
                else next_state<=SIF;
            end
            
            SEXE_B1:next_state<=SIF;
            
            SEXE_LS:next_state<=SEXE_LS1;
            
            SEXE_LS1:next_state<=SIF;
            
            SEXE_ALU:next_state<=SWB;
            
            SCLZ:next_state<=SWB;
            
            SWB:next_state<=SIF;
        endcase
        if(next_state==SIF)finish<=1;
        else finish<=0;
    end

    always@(*)begin
        if(reset)begin
            PC_ctr<=0;
            PC_ena<=0;
            IM_ctr<=0;
            Z_ctr<=0;
            Write_ena<=0;
            ALU_op<=4'b0000;
            ALU_ctr<=0;
            C_MUXA<=2'b00;
            C_MUXB<=2'b00;
            C_MUXC<=2'bzz;
            C_MUXD<=3'bzzz;
            C_MUXH<=3'bzzz;
            C_MUXL<=3'bzzz;
            C_MUXP<=2'b00;
            C_MUXADDR<=2'bzz;
            DM_W<=2'bzz;
            LT_ctr<=2'bzz;
            CLZ_ctr<=0;
            HI_ctr<=0;
            LO_ctr<=0;
            MUL_ctr<=0;
            MULTU_ctr<=0;
            DIV_ctr<=0;
            DIVU_ctr<=0;
            mtc0<=0;
            mfc0<=0;
            expection<=0;
            eret<=0;
            cause<=4'b0000;
            II_ctr<=0;
        end
        case(state)
            SIF:begin
                PC_ctr<=1;
                PC_ena<=0;
                IM_ctr<=1;
                Z_ctr<=1;
                Write_ena<=0;
                ALU_op<=4'b0000;
                ALU_ctr<=1;
                C_MUXA<=2'b00;
                C_MUXB<=2'b00;
                C_MUXC<=2'bzz;
                C_MUXP<=2'b00;
                C_MUXD<=3'bzzz;
                C_MUXH<=3'bzzz;
                C_MUXL<=3'bzzz;
                C_MUXADDR<=2'bzz;
                DM_W<=2'bzz;
                LT_ctr<=2'bzz;
                CLZ_ctr<=0;
                HI_ctr<=0;
                LO_ctr<=0;
                MUL_ctr<=0;
                MULTU_ctr<=0;
                DIV_ctr<=0;
                DIVU_ctr<=0;
                mtc0<=0;
                mfc0<=0;
                expection<=0;
                eret<=0;
                cause<=4'b0000;
                II_ctr<=0;
                
                inst_tag <= {inst[31:26],inst[5:0]};
                inst_tag1<=inst[31:26];
                jump_tag<=inst[20:16];
                CP0_tag<=inst[25:21];
            end

            SID:begin
                PC_ctr<=1;
                PC_ena<=1;
                              
                IM_ctr<=0;
                Z_ctr<=0;
                ALU_ctr<=0;
                if(inst_tag1==JAL)begin
                    II_ctr<=1;
                    Write_ena<=1;
                    C_MUXD<=3'b000;
                    C_MUXADDR<=2'b10;
                end
                else if(inst_tag==JALR)begin
                     Write_ena<=1;
                     C_MUXD<=3'b000;
                     if(jump_tag==5'b00000)C_MUXADDR<=2'b10;
                     else C_MUXADDR<=2'b00;
                     end
                else Write_ena<=0;
                
                if(inst_tag1==J)begin
                    C_MUXP<=2'b01;
                    II_ctr<=1;
                end
                else if(inst_tag==JR)C_MUXP<=2'b10;
                else C_MUXP<=2'b00;
            end

            SEXE_J:begin
                PC_ctr<=1;
                PC_ena<=1;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=0;
                ALU_ctr<=0;
                if(inst_tag1==JAL)C_MUXP<=2'b01;
                else if(inst_tag==JALR)C_MUXP<=2'b10;
            end

            SEXE_B:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=1;
                Write_ena<=0;
                ALU_op<=4'b0011;
                ALU_ctr<=1;
                C_MUXA<=2'b01;
                if(inst_tag1==BGEZ)C_MUXB<=2'b11;
                else C_MUXB<=2'b01;
            end

            SEXE_B1:begin
                PC_ctr<=1;
                PC_ena<=1;
                IM_ctr<=0;
                Z_ctr<=1;
                Write_ena<=0;
                ALU_op<=4'b0010;
                ALU_ctr<=1;
                C_MUXA<=2'b00;
                C_MUXB<=2'b10;
                C_MUXC<=2'b11;
                C_MUXP<=2'b00;
            end

            SEXE_LS:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=1;
                Write_ena<=0;
                ALU_op<=4'b0010;
                ALU_ctr<=1;
                C_MUXA<=2'b01;
                C_MUXB<=2'b10;
                C_MUXC<=2'b00;
            end

            SEXE_LS1:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=0;
                ALU_ctr<=0;
                if(inst_tag1==LB||inst_tag1==LBU||inst_tag1==LH||inst_tag1==LHU||inst_tag1==LW)begin
                    Write_ena<=1;
                    C_MUXD<=3'b010;
                    C_MUXADDR<=2'b01;
                end
                else Write_ena<=0;

                if(inst_tag1==LB)LT_ctr<=3'b001;
                else if(inst_tag1==LBU)LT_ctr<=3'b010;
                else if(inst_tag1==LH)LT_ctr<=3'b011;
                else if(inst_tag1==LHU)LT_ctr<=3'b100;
                else if(inst_tag1==LW)LT_ctr<=3'b000;
                
                if(inst_tag1==SB)DM_W<=2'b11;
                else if(inst_tag1==SH)DM_W<=2'b10;
                else if(inst_tag1==SW)DM_W<=2'b01;
            end

            SWB:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=1;
                ALU_ctr<=0;
                if(inst_tag==CLZ)C_MUXD<=3'b110;
                else C_MUXD<=3'b001;
                               
                if(inst_tag1==ADDI||inst_tag1==ADDIU||inst_tag1==ANDI||inst_tag1==ORI||inst_tag1==XORI||inst_tag1==LUI||inst_tag1==SLTI||inst_tag1==SLTIU)
                    C_MUXADDR<=2'b01;
                else C_MUXADDR<=2'b00; 
            end
            
            SCLZ:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=0;
                ALU_ctr<=0;
                C_MUXA<=1;
                CLZ_ctr<=1;
            end
            
            SMD:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=0;
                ALU_ctr<=0;
                HI_ctr<=1;
                LO_ctr<=1;
                if(inst_tag==MULT)begin
                    MUL_ctr<=1;
                    C_MUXH<=2'b000;
                    C_MUXL<=2'b000;
                end
                else if(inst_tag==MUL)begin
                    MUL_ctr<=1;
                    C_MUXH<=2'b000;
                    C_MUXL<=2'b000;
                end
                else if(inst_tag==MULTU)begin
                     MULTU_ctr<=1;
                     C_MUXH<=2'b001;
                     C_MUXL<=2'b001;
                end
                else if(inst_tag==DIV)begin
                     DIV_ctr<=1;
                     C_MUXH<=2'b010;
                     C_MUXL<=2'b010;
                end
                else if(inst_tag==DIVU)begin
                     DIVU_ctr<=1;
                     C_MUXH<=2'b011;
                     C_MUXL<=2'b011;
                end                
            end
            
            SHL:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=0;
                ALU_ctr<=0;
                if(inst_tag==MTLO)begin
                    C_MUXH<=3'b100;
                    C_MUXL<=3'b100;
                    HI_ctr<=0;
                    LO_ctr<=1;
                end
                if(inst_tag==MTHI)begin
                    C_MUXH<=3'b100;
                    C_MUXL<=3'b100;
                    HI_ctr<=1;
                    LO_ctr<=0;
                    end
                else if(inst_tag==MFLO)begin
                    HI_ctr<=0;
                    LO_ctr<=0;
                    C_MUXADDR<=2'b00;
                    C_MUXD<=3'b100;
                    Write_ena<=1;
                end
                else if(inst_tag==MUL)begin
                    HI_ctr<=0;
                    LO_ctr<=0;
                    C_MUXADDR<=2'b00;
                    C_MUXD<=3'b100;
                    Write_ena<=1;
                end
                else if(inst_tag==MFHI)begin
                     HI_ctr<=0;
                     LO_ctr<=0;
                     C_MUXADDR<=2'b00;
                     C_MUXD<=3'b011;
                     Write_ena<=1;
                end
                else if(inst_tag==MTC0)begin
                     if(CP0_tag==5'b00000)begin
                        mfc0<=1;
                        C_MUXADDR<=2'b01;
                        Write_ena<=1;
                        C_MUXD<=3'b101;
                     end
                     else begin
                        mtc0<=1;
                     end
                end
            end
            
            SBRK:begin
                PC_ctr<=1;
                PC_ena<=1;
                IM_ctr<=0;
                Z_ctr<=0;
                Write_ena<=0;
                ALU_ctr<=0;
                C_MUXP<=2'b11;
                if(inst_tag==SYSCALL)begin
                    cause<=4'b1000;
                    expection<=1;
                end
                else if(inst_tag==TEQ)begin
                    cause<=4'b1101;
                    expection<=1;
                end
                else if(inst_tag==BREAK)begin
                    cause<=4'b1001;
                    expection<=1;
                end
                else if(inst_tag==ERET)begin
                    eret<=1;
                end
            end      
            
            SEXE_ALU:begin
                PC_ctr<=0;
                PC_ena<=0;
                IM_ctr<=0;
                Z_ctr<=1;
                Write_ena<=0;
                ALU_ctr<=1;
                if(inst_tag==SLLV||inst_tag==SRLV||inst_tag==SRAV)C_MUXA<=2'b10;
                else if(inst_tag==SLL||inst_tag==SRL||inst_tag==SRA)     
                    C_MUXA<=2'b11;          
                else C_MUXA<=2'b01;
                
                if(inst_tag1==ADDI||inst_tag1==ADDIU||inst_tag1==ANDI||inst_tag1==ORI||inst_tag1==XORI||inst_tag1==LUI||inst_tag1==SLTI||inst_tag1==SLTIU)
                    C_MUXB<=2'b10;
                else C_MUXB<=2'b01;
                
                if(inst_tag==SLL||inst_tag==SRL||inst_tag==SRA)C_MUXC<=2'b10;
                else if(inst_tag1==ANDI||inst_tag1==ORI||inst_tag1==XORI||inst_tag1==SLTIU||inst_tag1==LUI)
                    C_MUXC<=2'b01;
                else if(inst_tag1==ADDI||inst_tag1==SLTI||inst_tag1==ADDIU)
                    C_MUXC<=2'b00;

                    
                if(inst_tag==ADD||inst_tag1==ADDI)ALU_op<=4'b0010;
                else if(inst_tag==ADDU||inst_tag1==ADDIU)ALU_op<=4'b0000;
                else if(inst_tag==AND||inst_tag1==ANDI)ALU_op<=4'b0100;
                else if(inst_tag==OR||inst_tag1==ORI)ALU_op<=4'b0101;
                else if(inst_tag==XOR||inst_tag1==XORI)ALU_op<=4'b0110;
                else if(inst_tag==SLT||inst_tag1==SLTI)ALU_op<=4'b1011;
                else if(inst_tag==SLTU||inst_tag1==SLTIU)ALU_op<=4'b1010;
                else if(inst_tag==NOR)ALU_op<=4'b0111;
                else if(inst_tag==SUB)ALU_op<=4'b0011;
                else if(inst_tag==SUBU)ALU_op<=4'b0001;
                else if(inst_tag1==LUI)ALU_op<=4'b1000;
                else if(inst_tag==SLL||inst_tag==SLLV)ALU_op<=4'b1110;
                else if(inst_tag==SRL||inst_tag==SRLV)ALU_op<=4'b1101;
                else if(inst_tag==SRA||inst_tag==SRAV)ALU_op<=4'b1100;
            end
        endcase
    end
endmodule