data/full_repos/permissive/20401628/spi.v
1: b'%Warning-WIDTH: data/full_repos/permissive/20401628/spi.v:16: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                            : ... In instance spi_module\nassign mode = {CPOL,CPHA};\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20401628/spi.v:37: Logical Operator IF expects 1 bit on the If, but If\'s CONST \'2\'h1\' generates 2 bits.\n                                                            : ... In instance spi_module\n   end else if (2\'b01) begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/20401628/spi.v:31: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h0\' generates 2 bits.\n                                                            : ... In instance spi_module\n case (mode)\n ^~~~\n%Error: Exiting due to 3 warning(s)\n'
module spi_module (
	input clk,
	input mclk,
	input mosi,
	input cs,
	input write,
	input [7:0] parain,
	output reg [7:0] paraout,
	output reg miso
);

parameter CPOL = 1'b0;
parameter CPHA = 1'b0;

wire [2:0] mode;
assign mode = {CPOL,CPHA};
reg mclk_prev;

reg [7:0] inbuf;
reg [7:0] outbuf;

reg cs_buf;

always @(posedge clk)
begin

	mclk_prev <= mclk;

	cs_buf <= cs;

	case (mode)
		2'h0: begin
			if ({cs_buf, cs} == 2'b10) begin
				if (write) begin
					outbuf <= parain;
				end
			end else if (2'b01) begin
				paraout <= inbuf;
			end
			if ({mclk_prev, mclk} == 2'b01) begin
				inbuf <= {inbuf[6:0], mosi};
				miso <= outbuf[7];
				outbuf[7:1] <= outbuf[6:0];
			end
		end
	endcase
end

endmodule
module spi_module (
	input clk,
	input mclk,
	input mosi,
	input cs,
	input write,
	input [7:0] parain,
	output reg [7:0] paraout,
	output reg miso
);


parameter CPOL = 1'b0;
parameter CPHA = 1'b0;

wire [2:0] mode;
assign mode = {CPOL,CPHA};
reg mclk_prev;

reg [7:0] inbuf;
reg [7:0] outbuf;

reg cs_buf;

always @(posedge clk)
begin

	mclk_prev <= mclk;

	cs_buf <= cs;

	case (mode)
		2'h0: begin
			if ({cs_buf, cs} == 2'b10) begin
				if (write) begin
					outbuf <= parain;
				end
			end else if (2'b01) begin
				paraout <= inbuf;
			end
			if ({mclk_prev, mclk} == 2'b01) begin
				inbuf <= {inbuf[6:0], mosi};
				miso <= outbuf[7];
				outbuf[7:1] <= outbuf[6:0];
			end
		end
	endcase
end

endmodule