data/full_repos/permissive/120518070/main/source/tb_outputToXor.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_outputToXor.sv:15: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_outputToXor.sv:17: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_outputToXor.sv:30: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_outputToXor.sv:33: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_outputToXor.sv:36: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_outputToXor.sv:39: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_outputToXor.sv:42: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_outputToXor.sv:45: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_outputToXor();
	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	
	reg [7:0] tb_rdata_i;
	reg tb_end_i;
	reg [7:0] tb_outputToXor_o;

	outputToXor DUT (.clk(tb_clk),.rdata_i(tb_rdata_i),.end_i(tb_end_i),.outputToXor_o(tb_outputToXor_o));
	initial
	begin
	tb_end_i = 1;
	tb_rdata_i = 44;
	@(negedge tb_clk);
	tb_end_i = 0;
	tb_rdata_i = 70;
	@(negedge tb_clk);
	tb_end_i = 1;
	tb_rdata_i = 90;
	@(negedge tb_clk);
	tb_end_i = 0;
	tb_rdata_i = 90;
	@(negedge tb_clk);
	tb_end_i = 0;
	tb_rdata_i = 100;
	@(negedge tb_clk);
	tb_end_i = 1;
	tb_rdata_i = 23;
	@(negedge tb_clk);
	tb_end_i = 0;
	tb_rdata_i = 70;
	end
endmodule
module tb_outputToXor();

	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	
	reg [7:0] tb_rdata_i;
	reg tb_end_i;
	reg [7:0] tb_outputToXor_o;

	outputToXor DUT (.clk(tb_clk),.rdata_i(tb_rdata_i),.end_i(tb_end_i),.outputToXor_o(tb_outputToXor_o));
	initial
	begin
	tb_end_i = 1;
	tb_rdata_i = 44;
	@(negedge tb_clk);
	tb_end_i = 0;
	tb_rdata_i = 70;
	@(negedge tb_clk);
	tb_end_i = 1;
	tb_rdata_i = 90;
	@(negedge tb_clk);
	tb_end_i = 0;
	tb_rdata_i = 90;
	@(negedge tb_clk);
	tb_end_i = 0;
	tb_rdata_i = 100;
	@(negedge tb_clk);
	tb_end_i = 1;
	tb_rdata_i = 23;
	@(negedge tb_clk);
	tb_end_i = 0;
	tb_rdata_i = 70;
	end
endmodule