data/full_repos/permissive/18477150/lib/shared/sonic_common_signal_clock_crosser.sv
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data/verilator_xmls/983a4990-f523-4553-ac60-7a4cac5edd2f.xml
module sonic_common_signal_clock_crosser # (
	parameter WIDTH = 8,
	parameter SHIFT_REGISTER_LENGTH = 3
	) (

	input logic inclock,
	input logic outclock,
	input logic inena,
	input logic outena,
	input logic reset,

	input logic [WIDTH-1:0] data,
	output logic [WIDTH-1:0] q
	);
	


	
	(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *)
	(* preserve *) reg [WIDTH-1:0] shift_register [0:SHIFT_REGISTER_LENGTH-1];
	
	int i_shift;

	always @ (posedge reset or posedge outclock) begin
		if (reset == 1'b1) begin
			for (int i = 0; i < SHIFT_REGISTER_LENGTH; i++) 
				shift_register[i] <= {WIDTH{1'b0}};
		end
		else begin
			for (i_shift = 0; i_shift <= SHIFT_REGISTER_LENGTH-2; i_shift=i_shift+1) begin
				shift_register[i_shift] <= shift_register[i_shift+1];
			end

			shift_register[SHIFT_REGISTER_LENGTH-1] <= data;
		end
	end


	assign q = shift_register[0];

endmodule
module sonic_common_signal_clock_crosser # (
	parameter WIDTH = 8,
	parameter SHIFT_REGISTER_LENGTH = 3
	) (

	input logic inclock,
	input logic outclock,
	input logic inena,
	input logic outena,
	input logic reset,

	input logic [WIDTH-1:0] data,
	output logic [WIDTH-1:0] q
	);

	


	
	(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *)
	(* preserve *) reg [WIDTH-1:0] shift_register [0:SHIFT_REGISTER_LENGTH-1];
	
	int i_shift;

	always @ (posedge reset or posedge outclock) begin
		if (reset == 1'b1) begin
			for (int i = 0; i < SHIFT_REGISTER_LENGTH; i++) 
				shift_register[i] <= {WIDTH{1'b0}};
		end
		else begin
			for (i_shift = 0; i_shift <= SHIFT_REGISTER_LENGTH-2; i_shift=i_shift+1) begin
				shift_register[i_shift] <= shift_register[i_shift+1];
			end

			shift_register[SHIFT_REGISTER_LENGTH-1] <= data;
		end
	end


	assign q = shift_register[0];

endmodule