data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sim_1/new/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sim_1/new/testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #22;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sim_1/new/testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sim_1/new/testbench.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #period;\n    ^\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sim_1/new/testbench.v:38: Cannot find file containing module: \'top\'\n    top dut(next,clk, reset,cloak, discu,SW,C,AN);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sim_1/new,data/full_repos/permissive/169258653/top\n             data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sim_1/new,data/full_repos/permissive/169258653/top.v\n             data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sim_1/new,data/full_repos/permissive/169258653/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

    reg next;
    reg clk;
    reg reset;
    reg cloak;
    wire [15:0] discu;
    reg [9:0] SW;
    wire [6:0] C;
    wire [7:0] AN;
    
    
    parameter period=5;
    

    top dut(next,clk, reset,cloak, discu,SW,C,AN);
    
    initial
    SW<=10'b0;
    
    initial
    next<=0;
    

    initial begin
    reset<=1;
    #22;
    reset<=0;
    end
    
    initial
    cloak<=1;
    

    always begin
    clk<=1;
    #period;
    clk<=0;
    #period;
    end
    


















endmodule
module testbench();


    reg next;
    reg clk;
    reg reset;
    reg cloak;
    wire [15:0] discu;
    reg [9:0] SW;
    wire [6:0] C;
    wire [7:0] AN;
    
    
    parameter period=5;
    

    top dut(next,clk, reset,cloak, discu,SW,C,AN);
    
    initial
    SW<=10'b0;
    
    initial
    next<=0;
    

    initial begin
    reset<=1;
    #22;
    reset<=0;
    end
    
    initial
    cloak<=1;
    

    always begin
    clk<=1;
    #period;
    clk<=0;
    #period;
    end
    


















endmodule