data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v
 line:56: before: ";"
1: b"%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:56: Define or directive not defined: '`DLY'\n  grand_dividend <= #`DLY 'd0;\n                     ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:56: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n  grand_dividend <= #`DLY 'd0;\n                             ^\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:57: Define or directive not defined: '`DLY'\n  grand_divisor <= #`DLY 'd0;\n                    ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:57: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n  grand_divisor <= #`DLY 'd0;\n                            ^\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:58: Define or directive not defined: '`DLY'\n  div_cnt <= #`DLY 'd0;\n              ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:58: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n  div_cnt <= #`DLY 'd0;\n                      ^\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:59: Define or directive not defined: '`DLY'\n  quotient <= #`DLY 'd0;\n               ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:59: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n  quotient <= #`DLY 'd0;\n                       ^\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:60: Define or directive not defined: '`DLY'\n  div_done <= #`DLY 1'b0;\n               ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:63: Define or directive not defined: '`DLY'\n  grand_dividend <= #`DLY dividend << DIV_R;\n                     ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:63: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\n  grand_dividend <= #`DLY dividend << DIV_R;\n                                   ^~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:64: Define or directive not defined: '`DLY'\n  grand_divisor  <= #`DLY divisor << (DIV_N+DIV_R-DIV_S-1);\n                     ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:64: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\n  grand_divisor  <= #`DLY divisor << (DIV_N+DIV_R-DIV_S-1);\n                                  ^~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:65: Define or directive not defined: '`DLY'\n  div_cnt <= #`DLY 'd0;\n              ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:65: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n  div_cnt <= #`DLY 'd0;\n                      ^\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:66: Define or directive not defined: '`DLY'\n  quotient <= #`DLY 'd0;\n               ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:66: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n  quotient <= #`DLY 'd0;\n                       ^\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:67: Define or directive not defined: '`DLY'\n  div_done <= #`DLY 1'b0;\n               ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:71: Define or directive not defined: '`DLY'\n   quotient <= #`DLY quotient_node;\n                ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:71: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n   quotient <= #`DLY quotient_node;\n                                  ^\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:72: Define or directive not defined: '`DLY'\n   div_done <= #`DLY 1;\n                ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:72: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n   div_done <= #`DLY 1;\n                      ^\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:76: Define or directive not defined: '`DLY'\n    grand_dividend <= #`DLY subtract_node;\n                       ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:76: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n    grand_dividend <= #`DLY subtract_node;\n                                         ^\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:77: Define or directive not defined: '`DLY'\n   quotient <= #`DLY quotient_node;\n                ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:77: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n   quotient <= #`DLY quotient_node;\n                                  ^\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:78: Define or directive not defined: '`DLY'\n   grand_divisor <= #`DLY divisor_node;\n                     ^~~~\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:78: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n   grand_divisor <= #`DLY divisor_node;\n                                      ^\n%Error: data/full_repos/permissive/165823960/pat_gen/HDMI_output_test.srcs/sources_1/imports/sources_1/ser_div.v:79: Define or directive not defined: '`DLY'\n   div_cnt <= #`DLY div_cnt + 1;\n               ^~~~\n%Error: Exiting due to 29 error(s)\n"
module ser_div (

   quotient, div_done,

   clk, rst_n, cal_trig, dividend, divisor
   );


parameter DIV_M = 16;
parameter DIV_N = 8;
parameter DIV_R = 0;
parameter DIV_S = 0;
parameter DIV_C = 5;

input                             clk;
input                             rst_n;
input                             cal_trig;
input  [DIV_M-1:0]                dividend;
input  [DIV_N-1:0]                divisor;

output [DIV_M+DIV_R-DIV_S-1:0]    quotient;
output                            div_done;

reg                               div_done;
reg    [DIV_M+DIV_R-1:0]          grand_dividend;
reg    [DIV_M+DIV_N+DIV_R-2:0]    grand_divisor;
reg    [DIV_M+DIV_R-DIV_S-1:0]    quotient;
reg    [DIV_C-1:0]                div_cnt;

wire   [DIV_M+DIV_N+DIV_R-1:0]    subtract_node;
wire   [DIV_M+DIV_R-1:0]          quotient_node;
wire   [DIV_M+DIV_N+DIV_R-2:0]    divisor_node;















assign subtract_node = {1'b0, grand_dividend} - {1'b0, grand_divisor};
assign quotient_node = 
  {quotient[DIV_M+DIV_R-DIV_S-2:0], ~subtract_node[DIV_M+DIV_N+DIV_R-1]};
assign divisor_node  = {1'b0, grand_divisor[DIV_M+DIV_N+DIV_R-2:1]};

always @(posedge clk or negedge rst_n) begin
	if (rst_n == 1'b0) begin
		grand_dividend <= #`DLY 'd0;
		grand_divisor <= #`DLY 'd0;
		div_cnt <= #`DLY 'd0;
		quotient <= #`DLY 'd0;
		div_done <= #`DLY 1'b0;
	end
	else if (cal_trig == 1'b1) begin 
		grand_dividend <= #`DLY dividend << DIV_R;
		grand_divisor  <= #`DLY divisor << (DIV_N+DIV_R-DIV_S-1);
		div_cnt <= #`DLY 'd0;
		quotient <= #`DLY 'd0;
		div_done <= #`DLY 1'b0;
	end
	else if (div_done == 1'b0) begin
		if (div_cnt == DIV_M+DIV_R-DIV_S-1) begin
			quotient <= #`DLY quotient_node;
			div_done <= #`DLY 1;
		end
		else begin 
			if (~subtract_node[DIV_M+DIV_N+DIV_R-1]) 
				grand_dividend <= #`DLY subtract_node;
			quotient <= #`DLY quotient_node;
			grand_divisor <= #`DLY divisor_node;
			div_cnt <= #`DLY div_cnt + 1;
		end
	end
end

endmodule
module ser_div (

   quotient, div_done,

   clk, rst_n, cal_trig, dividend, divisor
   );



parameter DIV_M = 16;
parameter DIV_N = 8;
parameter DIV_R = 0;
parameter DIV_S = 0;
parameter DIV_C = 5;

input                             clk;
input                             rst_n;
input                             cal_trig;
input  [DIV_M-1:0]                dividend;
input  [DIV_N-1:0]                divisor;

output [DIV_M+DIV_R-DIV_S-1:0]    quotient;
output                            div_done;

reg                               div_done;
reg    [DIV_M+DIV_R-1:0]          grand_dividend;
reg    [DIV_M+DIV_N+DIV_R-2:0]    grand_divisor;
reg    [DIV_M+DIV_R-DIV_S-1:0]    quotient;
reg    [DIV_C-1:0]                div_cnt;

wire   [DIV_M+DIV_N+DIV_R-1:0]    subtract_node;
wire   [DIV_M+DIV_R-1:0]          quotient_node;
wire   [DIV_M+DIV_N+DIV_R-2:0]    divisor_node;















assign subtract_node = {1'b0, grand_dividend} - {1'b0, grand_divisor};
assign quotient_node = 
  {quotient[DIV_M+DIV_R-DIV_S-2:0], ~subtract_node[DIV_M+DIV_N+DIV_R-1]};
assign divisor_node  = {1'b0, grand_divisor[DIV_M+DIV_N+DIV_R-2:1]};

always @(posedge clk or negedge rst_n) begin
	if (rst_n == 1'b0) begin
		grand_dividend <= #`DLY 'd0;
		grand_divisor <= #`DLY 'd0;
		div_cnt <= #`DLY 'd0;
		quotient <= #`DLY 'd0;
		div_done <= #`DLY 1'b0;
	end
	else if (cal_trig == 1'b1) begin 
		grand_dividend <= #`DLY dividend << DIV_R;
		grand_divisor  <= #`DLY divisor << (DIV_N+DIV_R-DIV_S-1);
		div_cnt <= #`DLY 'd0;
		quotient <= #`DLY 'd0;
		div_done <= #`DLY 1'b0;
	end
	else if (div_done == 1'b0) begin
		if (div_cnt == DIV_M+DIV_R-DIV_S-1) begin
			quotient <= #`DLY quotient_node;
			div_done <= #`DLY 1;
		end
		else begin 
			if (~subtract_node[DIV_M+DIV_N+DIV_R-1]) 
				grand_dividend <= #`DLY subtract_node;
			quotient <= #`DLY quotient_node;
			grand_divisor <= #`DLY divisor_node;
			div_cnt <= #`DLY div_cnt + 1;
		end
	end
end

endmodule