data/full_repos/permissive/160510184/InstructionMemory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h0\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h4\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h8\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hc\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h10\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h14\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h18\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h1c\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h20\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h24\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h28\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h2c\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h30\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h38\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h3c\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h40\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h44\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h48\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h4c\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h50\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h54\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h58\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h5c\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h60\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h64\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160510184/InstructionMemory.v:30: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h68\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Error: Exiting due to 26 warning(s)\n'
module InstructionMemory(Instruction, Address);
    input [63:0] Address;

    output [31:0] Instruction;

    reg [31:0] Instruction;
    
    always @ (Address) begin
        case(Address)
	63'h000: Instruction = 32'hF84003E9;
	63'h004: Instruction = 32'hF84083EA;
	63'h008: Instruction = 32'hF84103EB;
	63'h00c: Instruction = 32'hF84183EC;
	63'h010: Instruction = 32'hF84203ED;
	63'h014: Instruction = 32'hAA0B014A;
	63'h018: Instruction = 32'h8A0A018C;
	63'h01c: Instruction = 32'hB400008C;
	63'h020: Instruction = 32'h8B0901AD;
	63'h024: Instruction = 32'hCB09018C;
	63'h028: Instruction = 32'h17FFFFFD;
	63'h02c: Instruction = 32'hF80203ED;
	63'h030: Instruction = 32'hF84203ED;
	63'h038: Instruction = 32'h8B1F03E9; 
	63'h03c: Instruction = 32'hB2048D29; 
	63'h040: Instruction = 32'hD37F3129; 
	63'h044: Instruction = 32'hB2115929;
	63'h048: Instruction = 32'hD37F3129;
	63'h04c: Instruction = 32'hB21E2529; 
	63'h050: Instruction = 32'hD37F3129; 
	63'h054: Instruction = 32'hB22AF129; 
	63'h058: Instruction = 32'hD37F3129; 
	63'h05c: Instruction = 32'hB237BD29; 
	63'h060: Instruction = 32'hD37F1129; 
        63'h064: Instruction = 32'hF80283E9;
        63'h068: Instruction = 32'hF84283EA;
        default: Instruction = 32'hXXXXXXXX;
        endcase
    end
endmodule
module InstructionMemory(Instruction, Address);

    input [63:0] Address;

    output [31:0] Instruction;

    reg [31:0] Instruction;
    
    always @ (Address) begin
        case(Address)
	63'h000: Instruction = 32'hF84003E9;
	63'h004: Instruction = 32'hF84083EA;
	63'h008: Instruction = 32'hF84103EB;
	63'h00c: Instruction = 32'hF84183EC;
	63'h010: Instruction = 32'hF84203ED;
	63'h014: Instruction = 32'hAA0B014A;
	63'h018: Instruction = 32'h8A0A018C;
	63'h01c: Instruction = 32'hB400008C;
	63'h020: Instruction = 32'h8B0901AD;
	63'h024: Instruction = 32'hCB09018C;
	63'h028: Instruction = 32'h17FFFFFD;
	63'h02c: Instruction = 32'hF80203ED;
	63'h030: Instruction = 32'hF84203ED;
	63'h038: Instruction = 32'h8B1F03E9; 
	63'h03c: Instruction = 32'hB2048D29; 
	63'h040: Instruction = 32'hD37F3129; 
	63'h044: Instruction = 32'hB2115929;
	63'h048: Instruction = 32'hD37F3129;
	63'h04c: Instruction = 32'hB21E2529; 
	63'h050: Instruction = 32'hD37F3129; 
	63'h054: Instruction = 32'hB22AF129; 
	63'h058: Instruction = 32'hD37F3129; 
	63'h05c: Instruction = 32'hB237BD29; 
	63'h060: Instruction = 32'hD37F1129; 
        63'h064: Instruction = 32'hF80283E9;
        63'h068: Instruction = 32'hF84283EA;
        default: Instruction = 32'hXXXXXXXX;
        endcase
    end
endmodule