data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v
 line:20: before: "$"
1: b'%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_top.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_top);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #100000000\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:24: Unsupported: Ignoring delay on this delayed statement.\n    always #(RATE125/2.0)   clk125 = ~clk125;\n           ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:78: Unsupported: Verilog 1995 force\n        force i_top.axi4s_csi2_tuser  = axi4s_model_tuser;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:79: Unsupported: Verilog 1995 force\n        force i_top.axi4s_csi2_tlast  = axi4s_model_tlast;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:80: Unsupported: Verilog 1995 force\n        force i_top.axi4s_csi2_tdata  = {axi4s_model_tdata, 2\'d0};\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:81: Unsupported: Verilog 1995 force\n        force i_top.axi4s_csi2_tvalid = axi4s_model_tvalid;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:105: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_adr_i = wb_adr_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:106: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_dat_i = wb_dat_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:107: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_we_i  = wb_we_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:108: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_sel_i = wb_sel_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:109: Unsupported: Verilog 1995 force\n        force i_top.wb_peri_stb_i = wb_stb_o;\n        ^~~~~\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:130: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:136: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:138: syntax error, unexpected \'@\'\n                @(negedge wb_clk_i);\n                ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:152: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:158: syntax error, unexpected \'@\'\n        @(negedge wb_clk_i);\n        ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:160: syntax error, unexpected \'@\'\n                @(negedge wb_clk_i);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:174: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:177: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:226: Unsupported: Ignoring delay on this delayed statement.\n  #10000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:234: Unsupported: Ignoring delay on this delayed statement.\n    #100000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:245: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:251: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:257: Unsupported: Ignoring delay on this delayed statement.\n            #10000;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:260: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:271: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:276: Unsupported: Ignoring delay on this delayed statement.\n            #10000;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/sim/tb_top/tb_top.v:279: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Error: Exiting due to 17 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top();
    localparam RATE125 = 1000.0/125.0;
    
    initial begin
        $dumpfile("tb_top.vcd");
        $dumpvars(0, tb_top);
        
    #100000000
        $finish;
    end
    
    reg     clk125 = 1'b1;
    always #(RATE125/2.0)   clk125 = ~clk125;
    
    
    parameter   X_NUM = 2048;
    parameter   Y_NUM = 16;
    
    ultra96v2_imx219_stepper_motor
        i_top
            (
                .cam_clk_p      (),
                .cam_clk_n      (),
                .cam_data_p     (),
                .cam_data_n     (),
                
                .radio_led      ()
            );
    
    
    
    



    
    wire            axi4s_model_aresetn = i_top.axi4s_cam_aresetn;
    wire            axi4s_model_aclk    = i_top.axi4s_cam_aclk;
    wire    [0:0]   axi4s_model_tuser;
    wire            axi4s_model_tlast;
    wire    [7:0]   axi4s_model_tdata;
    wire            axi4s_model_tvalid;
    wire            axi4s_model_tready = i_top.axi4s_csi2_tready;
    
    jelly_axi4s_master_model
            #(
                .AXI4S_DATA_WIDTH   (8),
                .X_NUM              (X_NUM),
                .Y_NUM              (Y_NUM),

                .BUSY_RATE          (0),
                .RANDOM_SEED        (0)
            )
        i_axi4s_master_model
            (
                .aresetn            (axi4s_model_aresetn),
                .aclk               (axi4s_model_aclk),
                
                .m_axi4s_tuser      (axi4s_model_tuser),
                .m_axi4s_tlast      (axi4s_model_tlast),
                .m_axi4s_tdata      (axi4s_model_tdata),
                .m_axi4s_tvalid     (axi4s_model_tvalid),
                .m_axi4s_tready     (axi4s_model_tready)
            );
    
    initial begin
        force i_top.axi4s_csi2_tuser  = axi4s_model_tuser;
        force i_top.axi4s_csi2_tlast  = axi4s_model_tlast;
        force i_top.axi4s_csi2_tdata  = {axi4s_model_tdata, 2'd0};
        force i_top.axi4s_csi2_tvalid = axi4s_model_tvalid;
    end
    
    
    



    
    parameter   WB_ADR_WIDTH        = 30;
    parameter   WB_DAT_WIDTH        = 64;
    parameter   WB_SEL_WIDTH        = (WB_DAT_WIDTH / 8);
    
    wire                            wb_rst_i = i_top.wb_peri_rst_i;
    wire                            wb_clk_i = i_top.wb_peri_clk_i;
    reg     [WB_ADR_WIDTH-1:0]      wb_adr_o;
    wire    [WB_DAT_WIDTH-1:0]      wb_dat_i = i_top.wb_peri_dat_o;
    reg     [WB_DAT_WIDTH-1:0]      wb_dat_o;
    reg                             wb_we_o;
    reg     [WB_SEL_WIDTH-1:0]      wb_sel_o;
    reg                             wb_stb_o = 0;
    wire                            wb_ack_i = i_top.wb_peri_ack_o;
    
    initial begin
        force i_top.wb_peri_adr_i = wb_adr_o;
        force i_top.wb_peri_dat_i = wb_dat_o;
        force i_top.wb_peri_we_i  = wb_we_o;
        force i_top.wb_peri_sel_i = wb_sel_o;
        force i_top.wb_peri_stb_i = wb_stb_o;
    end
    
    
    reg     [WB_DAT_WIDTH-1:0]      reg_wb_dat;
    reg                             reg_wb_ack;
    always @(posedge wb_clk_i) begin
        if ( ~wb_we_o & wb_stb_o & wb_ack_i ) begin
            reg_wb_dat <= wb_dat_i;
        end
        reg_wb_ack <= wb_ack_i;
    end
    
    
    task wb_write(
                input [31:0]    adr,
                input [31:0]    dat,
                input [3:0]     sel
            );
    begin
        $display("WISHBONE_WRITE(adr:%h dat:%h sel:%b)", adr, dat, sel);
        @(negedge wb_clk_i);
            wb_adr_o = (adr >> 3);
            wb_dat_o = dat;
            wb_sel_o = sel;
            wb_we_o  = 1'b1;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
    end
    endtask
    
    task wb_read(
                input [31:0]    adr
            );
    begin
        @(negedge wb_clk_i);
            wb_adr_o = (adr >> 3);
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'b1}};
            wb_we_o  = 1'b0;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
            $display("WISHBONE_READ(adr:%h dat:%h)", adr, reg_wb_dat);
    end
    endtask
    
    
    
    initial begin
    #1000;
        $display("start");
    
    #1000;
        $display("read core ID");
        wb_read (32'h80000000);
        wb_read (32'h80010000);
        wb_read (32'h80011000);
        wb_read (32'h80021000);
        wb_read (32'h80030000);
        wb_read (32'h80030800);
        wb_read (32'h80031000);
        wb_read (32'h80031800);
        wb_read (32'h80037800);
        wb_read (32'h80041000);
        wb_read (32'h80042000);
        wb_read (32'h80070000);
        wb_read (32'h80071000);
        
        
        $display("STMC");
        wb_write(32'h80041000 + 8*8'h04, 9000000, 8'h0f);
        wb_write(32'h80041000 + 8*8'h06,   10000, 8'h0f);
        wb_write(32'h80041000 + 8*8'h07,   10000, 8'h0f);
        wb_write(32'h80041000 + 8*8'h09, 1000000, 8'h0f);
        wb_write(32'h80041000 + 8*8'h0a,   10000, 8'h0f);
        wb_write(32'h80041000 + 8*8'h0f,   20000, 8'h0f);

        wb_write(32'h80041000 + 8*8'h02,       1, 8'h0f);
        wb_write(32'h80041000 + 8*8'h01,       3, 8'h0f);
        
        















        
        
        
        
        
  #10000;
        $display("set format regularizer");
        wb_read (32'h80100000);
        wb_write(32'h80100080,        X_NUM, 4'b1111);
        wb_write(32'h80100088,        Y_NUM, 4'b1111);
        wb_write(32'h80100090,            0, 4'b1111);
        wb_write(32'h80100098,         1024, 4'b1111);
        wb_write(32'h80100020,            1, 4'b1111);
    #100000;
        
        $display("set write DMA");
        wb_read (32'h80210000);
        wb_write(32'h80210040, 32'h30000000, 4'b1111);
        wb_write(32'h80210048,      4*X_NUM, 4'b1111);
        wb_write(32'h80210050,        X_NUM, 4'b1111);
        wb_write(32'h80210058,        Y_NUM, 4'b1111);
        wb_write(32'h80210060,  X_NUM*Y_NUM, 4'b1111);
        wb_write(32'h80210068,           31, 4'b1111);
        wb_write(32'h80210020,            3, 4'b1111);
    #10000;
        wb_read (32'h80210028);
        wb_read (32'h80210028);
        wb_read (32'h80210028);
        wb_read (32'h80210028);
        
    #10000;
        wb_write(32'h80210020, 0, 4'b1111);
        

        wb_read(32'h80210028);
        while ( reg_wb_dat != 0 ) begin
            #10000;
            wb_read(32'h80210028);
        end
        #10000;
        
        

        wb_write(32'h80210040, 32'h30000000, 4'b1111);
        wb_write(32'h80210048,        4*128, 4'b1111);
        wb_write(32'h80210050,       256+64, 4'b1111);
        wb_write(32'h80210058,           64, 4'b1111);
        wb_write(32'h80210060,       256*64, 4'b1111);
        wb_write(32'h80210068,           31, 4'b1111);
        wb_write(32'h80210020,            7, 4'b1111);
    #10000;
        

        wb_read(32'h80210028);
        while ( reg_wb_dat != 0 ) begin
            #10000;
            wb_read(32'h80210028);
        end
    #10000;

    end
    
    
endmodule
module tb_top();

    localparam RATE125 = 1000.0/125.0;
    
    initial begin
        $dumpfile("tb_top.vcd");
        $dumpvars(0, tb_top);
        
    #100000000
        $finish;
    end
    
    reg     clk125 = 1'b1;
    always #(RATE125/2.0)   clk125 = ~clk125;
    
    
    parameter   X_NUM = 2048;
    parameter   Y_NUM = 16;
    
    ultra96v2_imx219_stepper_motor
        i_top
            (
                .cam_clk_p      (),
                .cam_clk_n      (),
                .cam_data_p     (),
                .cam_data_n     (),
                
                .radio_led      ()
            );
    
    
    
    



    
    wire            axi4s_model_aresetn = i_top.axi4s_cam_aresetn;
    wire            axi4s_model_aclk    = i_top.axi4s_cam_aclk;
    wire    [0:0]   axi4s_model_tuser;
    wire            axi4s_model_tlast;
    wire    [7:0]   axi4s_model_tdata;
    wire            axi4s_model_tvalid;
    wire            axi4s_model_tready = i_top.axi4s_csi2_tready;
    
    jelly_axi4s_master_model
            #(
                .AXI4S_DATA_WIDTH   (8),
                .X_NUM              (X_NUM),
                .Y_NUM              (Y_NUM),

                .BUSY_RATE          (0),
                .RANDOM_SEED        (0)
            )
        i_axi4s_master_model
            (
                .aresetn            (axi4s_model_aresetn),
                .aclk               (axi4s_model_aclk),
                
                .m_axi4s_tuser      (axi4s_model_tuser),
                .m_axi4s_tlast      (axi4s_model_tlast),
                .m_axi4s_tdata      (axi4s_model_tdata),
                .m_axi4s_tvalid     (axi4s_model_tvalid),
                .m_axi4s_tready     (axi4s_model_tready)
            );
    
    initial begin
        force i_top.axi4s_csi2_tuser  = axi4s_model_tuser;
        force i_top.axi4s_csi2_tlast  = axi4s_model_tlast;
        force i_top.axi4s_csi2_tdata  = {axi4s_model_tdata, 2'd0};
        force i_top.axi4s_csi2_tvalid = axi4s_model_tvalid;
    end
    
    
    



    
    parameter   WB_ADR_WIDTH        = 30;
    parameter   WB_DAT_WIDTH        = 64;
    parameter   WB_SEL_WIDTH        = (WB_DAT_WIDTH / 8);
    
    wire                            wb_rst_i = i_top.wb_peri_rst_i;
    wire                            wb_clk_i = i_top.wb_peri_clk_i;
    reg     [WB_ADR_WIDTH-1:0]      wb_adr_o;
    wire    [WB_DAT_WIDTH-1:0]      wb_dat_i = i_top.wb_peri_dat_o;
    reg     [WB_DAT_WIDTH-1:0]      wb_dat_o;
    reg                             wb_we_o;
    reg     [WB_SEL_WIDTH-1:0]      wb_sel_o;
    reg                             wb_stb_o = 0;
    wire                            wb_ack_i = i_top.wb_peri_ack_o;
    
    initial begin
        force i_top.wb_peri_adr_i = wb_adr_o;
        force i_top.wb_peri_dat_i = wb_dat_o;
        force i_top.wb_peri_we_i  = wb_we_o;
        force i_top.wb_peri_sel_i = wb_sel_o;
        force i_top.wb_peri_stb_i = wb_stb_o;
    end
    
    
    reg     [WB_DAT_WIDTH-1:0]      reg_wb_dat;
    reg                             reg_wb_ack;
    always @(posedge wb_clk_i) begin
        if ( ~wb_we_o & wb_stb_o & wb_ack_i ) begin
            reg_wb_dat <= wb_dat_i;
        end
        reg_wb_ack <= wb_ack_i;
    end
    
    
    task wb_write(
                input [31:0]    adr,
                input [31:0]    dat,
                input [3:0]     sel
            );
    begin
        $display("WISHBONE_WRITE(adr:%h dat:%h sel:%b)", adr, dat, sel);
        @(negedge wb_clk_i);
            wb_adr_o = (adr >> 3);
            wb_dat_o = dat;
            wb_sel_o = sel;
            wb_we_o  = 1'b1;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
    end
    endtask
    
    task wb_read(
                input [31:0]    adr
            );
    begin
        @(negedge wb_clk_i);
            wb_adr_o = (adr >> 3);
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'b1}};
            wb_we_o  = 1'b0;
            wb_stb_o = 1'b1;
        @(negedge wb_clk_i);
            while ( reg_wb_ack == 1'b0 ) begin
                @(negedge wb_clk_i);
            end
            wb_adr_o = {WB_ADR_WIDTH{1'bx}};
            wb_dat_o = {WB_DAT_WIDTH{1'bx}};
            wb_sel_o = {WB_SEL_WIDTH{1'bx}};
            wb_we_o  = 1'bx;
            wb_stb_o = 1'b0;
            $display("WISHBONE_READ(adr:%h dat:%h)", adr, reg_wb_dat);
    end
    endtask
    
    
    
    initial begin
    #1000;
        $display("start");
    
    #1000;
        $display("read core ID");
        wb_read (32'h80000000);
        wb_read (32'h80010000);
        wb_read (32'h80011000);
        wb_read (32'h80021000);
        wb_read (32'h80030000);
        wb_read (32'h80030800);
        wb_read (32'h80031000);
        wb_read (32'h80031800);
        wb_read (32'h80037800);
        wb_read (32'h80041000);
        wb_read (32'h80042000);
        wb_read (32'h80070000);
        wb_read (32'h80071000);
        
        
        $display("STMC");
        wb_write(32'h80041000 + 8*8'h04, 9000000, 8'h0f);
        wb_write(32'h80041000 + 8*8'h06,   10000, 8'h0f);
        wb_write(32'h80041000 + 8*8'h07,   10000, 8'h0f);
        wb_write(32'h80041000 + 8*8'h09, 1000000, 8'h0f);
        wb_write(32'h80041000 + 8*8'h0a,   10000, 8'h0f);
        wb_write(32'h80041000 + 8*8'h0f,   20000, 8'h0f);

        wb_write(32'h80041000 + 8*8'h02,       1, 8'h0f);
        wb_write(32'h80041000 + 8*8'h01,       3, 8'h0f);
        
        















        
        
        
        
        
  #10000;
        $display("set format regularizer");
        wb_read (32'h80100000);
        wb_write(32'h80100080,        X_NUM, 4'b1111);
        wb_write(32'h80100088,        Y_NUM, 4'b1111);
        wb_write(32'h80100090,            0, 4'b1111);
        wb_write(32'h80100098,         1024, 4'b1111);
        wb_write(32'h80100020,            1, 4'b1111);
    #100000;
        
        $display("set write DMA");
        wb_read (32'h80210000);
        wb_write(32'h80210040, 32'h30000000, 4'b1111);
        wb_write(32'h80210048,      4*X_NUM, 4'b1111);
        wb_write(32'h80210050,        X_NUM, 4'b1111);
        wb_write(32'h80210058,        Y_NUM, 4'b1111);
        wb_write(32'h80210060,  X_NUM*Y_NUM, 4'b1111);
        wb_write(32'h80210068,           31, 4'b1111);
        wb_write(32'h80210020,            3, 4'b1111);
    #10000;
        wb_read (32'h80210028);
        wb_read (32'h80210028);
        wb_read (32'h80210028);
        wb_read (32'h80210028);
        
    #10000;
        wb_write(32'h80210020, 0, 4'b1111);
        

        wb_read(32'h80210028);
        while ( reg_wb_dat != 0 ) begin
            #10000;
            wb_read(32'h80210028);
        end
        #10000;
        
        

        wb_write(32'h80210040, 32'h30000000, 4'b1111);
        wb_write(32'h80210048,        4*128, 4'b1111);
        wb_write(32'h80210050,       256+64, 4'b1111);
        wb_write(32'h80210058,           64, 4'b1111);
        wb_write(32'h80210060,       256*64, 4'b1111);
        wb_write(32'h80210068,           31, 4'b1111);
        wb_write(32'h80210020,            7, 4'b1111);
    #10000;
        

        wb_read(32'h80210028);
        while ( reg_wb_dat != 0 ) begin
            #10000;
            wb_read(32'h80210028);
        end
    #10000;

    end
    
    
endmodule