data/full_repos/permissive/123218339/demux.v
 line:27: before: ";"
1: b"%Error: data/full_repos/permissive/123218339/demux.v:27: Found definition of 'out0' as a VAR but expected a task/function\n        0 : out0;\n            ^~~~\n%Error: data/full_repos/permissive/123218339/demux.v:28: Found definition of 'out1' as a VAR but expected a task/function\n        1 : out1;\n            ^~~~\n%Error: data/full_repos/permissive/123218339/demux.v:29: Found definition of 'out2' as a VAR but expected a task/function\n        2 : out2;\n            ^~~~\n%Error: data/full_repos/permissive/123218339/demux.v:30: Found definition of 'out3' as a VAR but expected a task/function\n        3 : out3;\n            ^~~~\n%Error: data/full_repos/permissive/123218339/demux.v:31: Found definition of 'out4' as a VAR but expected a task/function\n        4 : out4;\n            ^~~~\n%Error: data/full_repos/permissive/123218339/demux.v:32: Found definition of 'out5' as a VAR but expected a task/function\n        5 : out5;\n            ^~~~\n%Error: data/full_repos/permissive/123218339/demux.v:33: Found definition of 'out6' as a VAR but expected a task/function\n        6 : out6;\n            ^~~~\n%Error: data/full_repos/permissive/123218339/demux.v:34: Found definition of 'out7' as a VAR but expected a task/function\n        7 : out7;\n            ^~~~\n%Error: Exiting due to 8 error(s)\n"
module demux(select, in, out0, out1, out2, out3, out4, out5, out6, out7);
	input [2:0] select;
	input[`WORD_WIDTH-1:0] in;
	output[`WORD_WIDTH-1:0] out0, out1, out2, out3, out4, out5, out6, out7;

	reg [`WORD_WIDTH-1:0] out0_buf, out1_buf, out2_buf, out3_buf, out4_buf, out5_buf, out6_buf, out7_buf;

	always @(select) begin
	   case(select)
	       0 : out0;
	       1 : out1;
	       2 : out2;
	       3 : out3;
	       4 : out4;
	       5 : out5;
	       6 : out6;
	       7 : out7;
	   endcase
	end
	assign out0 = out0_buf;
	assign out1 = out1_buf;
	assign out2 = out2_buf;
	assign out3 = out3_buf;
	assign out4 = out4_buf;
	assign out5 = out5_buf;
	assign out6 = out6_buf;
	assign out7 = out7_buf;
endmodule
module demux(select, in, out0, out1, out2, out3, out4, out5, out6, out7);

	input [2:0] select;
	input[`WORD_WIDTH-1:0] in;
	output[`WORD_WIDTH-1:0] out0, out1, out2, out3, out4, out5, out6, out7;

	reg [`WORD_WIDTH-1:0] out0_buf, out1_buf, out2_buf, out3_buf, out4_buf, out5_buf, out6_buf, out7_buf;

	always @(select) begin
	   case(select)
	       0 : out0;
	       1 : out1;
	       2 : out2;
	       3 : out3;
	       4 : out4;
	       5 : out5;
	       6 : out6;
	       7 : out7;
	   endcase
	end
	assign out0 = out0_buf;
	assign out1 = out1_buf;
	assign out2 = out2_buf;
	assign out3 = out3_buf;
	assign out4 = out4_buf;
	assign out5 = out5_buf;
	assign out6 = out6_buf;
	assign out7 = out7_buf;
endmodule