data/full_repos/permissive/128659832/verilog/font.v
data/verilator_xmls/74fdf539-cd39-48a4-9909-00f3dc0fe4c3.xml
module font (
    input  wire         i_clk,
    input  wire [10:0]  i_addr,
    input  wire [ 2:0]  i_bit,
    output wire         o_data
);

    parameter FONT_FILE = "font256x8x8.rom";

    reg [7:0] rom [0:256*8-1];
    
    initial begin
        $readmemb(FONT_FILE, rom);
    end

    reg [7:0] data_r;
    reg [2:0] bit_r;
    always @(posedge i_clk) begin
        data_r <= rom[i_addr];
        bit_r <= i_bit;
    end


    assign o_data = data_r[bit_r];
    
endmodule
module font (
    input  wire         i_clk,
    input  wire [10:0]  i_addr,
    input  wire [ 2:0]  i_bit,
    output wire         o_data
);


    parameter FONT_FILE = "font256x8x8.rom";

    reg [7:0] rom [0:256*8-1];
    
    initial begin
        $readmemb(FONT_FILE, rom);
    end

    reg [7:0] data_r;
    reg [2:0] bit_r;
    always @(posedge i_clk) begin
        data_r <= rom[i_addr];
        bit_r <= i_bit;
    end


    assign o_data = data_r[bit_r];
    
endmodule