data/full_repos/permissive/129527056/cores/gng/ver/jtgng_sound/jt03_dummy.v
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data/verilator_xmls/2318b004-4747-4dc8-ab2b-380752bfdda9.xml
module jt03 (
    input           rst,
    input           clk,
    input           cen,
    input   [7:0]   din,
    input           addr,
    input           cs_n,
    input           wr_n,

    output  [7:0]   dout,
    output          irq_n,

    output          [ 7:0] psg_A,
    output          [ 7:0] psg_B,
    output          [ 7:0] psg_C,
    output  signed  [15:0] fm_snd,

    output          [ 9:0] psg_snd,
    output  signed  [15:0]  snd,
    output          snd_sample
);

assign dout=8'd0, irq_n = 1'b1;
assign snd=16'd0;
assign snd_sample=1'b0;

reg last_wr_n;
reg [7:0] selection;


always @(posedge clk) if(cen) begin
    last_wr_n <= wr_n;
    if( !wr_n && last_wr_n && !cs_n ) begin
        if( !addr ) selection <= din;
        `ifdef DUMMY_PRINTALL
            if(  addr ) $display("%X, %X", selection, din );
        `else
            if(  addr && selection>=8'h20) $display("%X, %X", selection, din );
        `endif
    end
end

endmodule
module jt03 (
    input           rst,
    input           clk,
    input           cen,
    input   [7:0]   din,
    input           addr,
    input           cs_n,
    input           wr_n,

    output  [7:0]   dout,
    output          irq_n,

    output          [ 7:0] psg_A,
    output          [ 7:0] psg_B,
    output          [ 7:0] psg_C,
    output  signed  [15:0] fm_snd,

    output          [ 9:0] psg_snd,
    output  signed  [15:0]  snd,
    output          snd_sample
);


assign dout=8'd0, irq_n = 1'b1;
assign snd=16'd0;
assign snd_sample=1'b0;

reg last_wr_n;
reg [7:0] selection;


always @(posedge clk) if(cen) begin
    last_wr_n <= wr_n;
    if( !wr_n && last_wr_n && !cs_n ) begin
        if( !addr ) selection <= din;
        `ifdef DUMMY_PRINTALL
            if(  addr ) $display("%X, %X", selection, din );
        `else
            if(  addr && selection>=8'h20) $display("%X, %X", selection, din );
        `endif
    end
end

endmodule