data/full_repos/permissive/166008742/src/tb_mem.v
 line:68: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_mem.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/166008742/src/tb_mem.v:68: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_mem.v:70: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk)\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_mem.v:72: syntax error, unexpected \';\'\n        for (addr=0; addr < 1024; addr = addr+1) begin\n                                ^\n%Error: data/full_repos/permissive/166008742/src/tb_mem.v:72: syntax error, unexpected \')\', expecting \';\'\n        for (addr=0; addr < 1024; addr = addr+1) begin\n                                               ^\n%Error: data/full_repos/permissive/166008742/src/tb_mem.v:80: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/166008742/src/tb_mem.v:86: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mem ();
    parameter ADDR_WIDTH = 16;
    parameter DATA_WIDTH = 32;

    reg reset;
    reg clk;



    reg [ADDR_WIDTH-1:0] wbs_address;
    reg [DATA_WIDTH-1:0] wbs_writedata;
    reg wbs_strobe;
    reg wbs_cycle;
    reg wbs_write;


    wire wbs_ack;
    wire [DATA_WIDTH-1:0] wbs_readdata;


    reg [ADDR_WIDTH-1:0] addr;

    mem #(ADDR_WIDTH, DATA_WIDTH) dut(
        .reset(reset),
        .clk(clk),


        .wbs_address(wbs_address),
        .wbs_writedata(wbs_writedata),
        .wbs_readdata(wbs_readdata),
        .wbs_strobe(wbs_strobe),
        .wbs_cycle(wbs_cycle),
        .wbs_write(wbs_write),
        .wbs_ack(wbs_ack)
    );

    always begin
        #1;
        clk <= ~clk;
    end

    initial begin
            clk <= 0;
            reset <= 1;
            wbs_address <= 0;
            wbs_writedata <= 0;
            wbs_strobe <= 0;
            wbs_cycle <= 0;
            wbs_write <= 0;

        repeat (100) @(posedge clk);
            reset <= 0;
        repeat (100) @(posedge clk)

        for (addr=0; addr < 1024; addr = addr+1) begin
            @(posedge clk);
            wbs_address <= addr;
            wbs_writedata <= {DATA_WIDTH{1'b1}} - addr;
            wbs_write <= 1;
            wbs_strobe <= 1;
            wbs_cycle <= 1;

            @(posedge clk);
            wbs_strobe <= 0;
            wbs_cycle <= 0;
        end

        for (addr=0; addr < 1024; addr = addr+1) begin
            @(posedge clk);
            wbs_address <= addr;
            wbs_writedata <= 0;
            wbs_write <= 0;

            wbs_strobe <= 1;
            wbs_cycle <= 1;

            @(posedge clk);
            wbs_strobe <= 0;
            wbs_cycle <= 0;
        end
        #100;
    end

endmodule
module tb_mem ();

    parameter ADDR_WIDTH = 16;
    parameter DATA_WIDTH = 32;

    reg reset;
    reg clk;



    reg [ADDR_WIDTH-1:0] wbs_address;
    reg [DATA_WIDTH-1:0] wbs_writedata;
    reg wbs_strobe;
    reg wbs_cycle;
    reg wbs_write;


    wire wbs_ack;
    wire [DATA_WIDTH-1:0] wbs_readdata;


    reg [ADDR_WIDTH-1:0] addr;

    mem #(ADDR_WIDTH, DATA_WIDTH) dut(
        .reset(reset),
        .clk(clk),


        .wbs_address(wbs_address),
        .wbs_writedata(wbs_writedata),
        .wbs_readdata(wbs_readdata),
        .wbs_strobe(wbs_strobe),
        .wbs_cycle(wbs_cycle),
        .wbs_write(wbs_write),
        .wbs_ack(wbs_ack)
    );

    always begin
        #1;
        clk <= ~clk;
    end

    initial begin
            clk <= 0;
            reset <= 1;
            wbs_address <= 0;
            wbs_writedata <= 0;
            wbs_strobe <= 0;
            wbs_cycle <= 0;
            wbs_write <= 0;

        repeat (100) @(posedge clk);
            reset <= 0;
        repeat (100) @(posedge clk)

        for (addr=0; addr < 1024; addr = addr+1) begin
            @(posedge clk);
            wbs_address <= addr;
            wbs_writedata <= {DATA_WIDTH{1'b1}} - addr;
            wbs_write <= 1;
            wbs_strobe <= 1;
            wbs_cycle <= 1;

            @(posedge clk);
            wbs_strobe <= 0;
            wbs_cycle <= 0;
        end

        for (addr=0; addr < 1024; addr = addr+1) begin
            @(posedge clk);
            wbs_address <= addr;
            wbs_writedata <= 0;
            wbs_write <= 0;

            wbs_strobe <= 1;
            wbs_cycle <= 1;

            @(posedge clk);
            wbs_strobe <= 0;
            wbs_cycle <= 0;
        end
        #100;
    end

endmodule