data/full_repos/permissive/143278/vhdl_tests/pr2529315b.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/vhdl_tests/pr2529315b.v:70: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'CI\' generates 1 bits.\n                                                                            : ... In instance test.car0\nassign    {CO, unused} = A + B + CI;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/vhdl_tests/pr2529315b.v:55: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'CI\' generates 1 bits.\n                                                                            : ... In instance test.add2\nassign Z = A + B + CI;\n                 ^\n%Error: Exiting due to 2 warning(s)\n'
module adder32 (
   Z,
   A,
   B,
   CI);

input[31:0]   A;
input[31:0]   B;
input	      CI;
output [31:0] Z;

assign Z = A + B + CI;

endmodule
module adder32 (
   Z,
   A,
   B,
   CI);


input[31:0]   A;
input[31:0]   B;
input	      CI;
output [31:0] Z;

assign Z = A + B + CI;

endmodule