data/full_repos/permissive/159610434/i8255/testbench/breg_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/159610434/i8255/testbench/breg_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #TCQ\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159610434/i8255/testbench/breg_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #TCQ\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/159610434/i8255/testbench/breg_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #TCQ\n        ^\n%Error: data/full_repos/permissive/159610434/i8255/testbench/breg_tb.v:13: Cannot find file containing module: \'breg\'\n    breg uut (\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/159610434/i8255/testbench,data/full_repos/permissive/159610434/breg\n             data/full_repos/permissive/159610434/i8255/testbench,data/full_repos/permissive/159610434/breg.v\n             data/full_repos/permissive/159610434/i8255/testbench,data/full_repos/permissive/159610434/breg.sv\n             breg\n             breg.v\n             breg.sv\n             obj_dir/breg\n             obj_dir/breg.v\n             obj_dir/breg.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module breg_tb(
    );

    parameter TCQ = 10;

    reg reset;
    reg en;
    reg [7:0] d;
    wire [7:0] q;

    breg uut (
        .reset(reset),
        .en(en),
        .d(d),
        .q(q)
    );

    initial begin
        reset = 1'b1;
        en = 1'b0;
        d = 8'b0;
        #TCQ
            reset = 1'b0;
        #TCQ
            d = 8'ha5;
            en = 1'b1;
        #TCQ
            ;
    end

endmodule
module breg_tb(
    );


    parameter TCQ = 10;

    reg reset;
    reg en;
    reg [7:0] d;
    wire [7:0] q;

    breg uut (
        .reset(reset),
        .en(en),
        .d(d),
        .q(q)
    );

    initial begin
        reset = 1'b1;
        en = 1'b0;
        d = 8'b0;
        #TCQ
            reset = 1'b0;
        #TCQ
            d = 8'ha5;
            en = 1'b1;
        #TCQ
            ;
    end

endmodule