data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/reg_rst_n.v
data/verilator_xmls/f8b0bca5-ca99-4e97-b9c9-d4c93cc1de65.xml
module reg_rst_n
# (
    parameter w = 1
) 
(
    input                clk,
    input                rst_n,
    input      [w - 1:0] d,
    output reg [w - 1:0] q
);

    always @ (posedge clk or negedge rst_n)
        if (! rst_n)
            q <= { w { 1'b0 } };
        else
            q <= d;

endmodule
module reg_rst_n
# (
    parameter w = 1
) 
(
    input                clk,
    input                rst_n,
    input      [w - 1:0] d,
    output reg [w - 1:0] q
);


    always @ (posedge clk or negedge rst_n)
        if (! rst_n)
            q <= { w { 1'b0 } };
        else
            q <= d;

endmodule