data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:619: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:623: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:628: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  {temp[0], temp[31:1]} = out_left & key_left;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:596: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:600: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:604: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  {temp[0], temp[31:1]} = in_left & key_left;\n                                ^\n%Error: Exiting due to 14 warning(s)\n'
module Camellia_randomize( Kin, Din, Dout, EncDec, RSTn, EN, CLK, state, round, kl, ka, ka_out );
  input          CLK, RSTn, EN;
  input [3:0] 	 state;
  input [4:0] 	 round;
  input [127:0]  Din, Kin;
  input [127:0]  kl, ka;
  input 	 EncDec;
  output reg [127:0] Dout;
  output reg [127:0] ka_out;


  parameter ST_IDLE                = 4'h0;
  parameter ST_IDLE_READY          = 4'h1;


  parameter ST_KEY_GET             = 4'h3;
  parameter ST_KEY_F_FUNC          = 4'h4;
  parameter ST_KEY_XOR             = 4'h5;


  parameter ST_RANDOMIZE_GET         = 4'h7;
  parameter ST_RANDOMIZE_INITIAL_XOR = 4'h8;
  parameter ST_RANDOMIZE_FINAL_XOR   = 4'h9;
  parameter ST_RANDOMIZE_F_FUNC      = 4'ha;
  parameter ST_RANDOMIZE_FL_1        = 4'hb;
  parameter ST_RANDOMIZE_FL_2        = 4'hc;

  parameter Enc = 1'b0;
  parameter Dec = 1'b1;


  parameter SIGMA1 = 64'ha09e667f3bcc908b;
  parameter SIGMA2 = 64'hb67ae8584caa73b2;
  parameter SIGMA3 = 64'hc6ef372fe94f82be;
  parameter SIGMA4 = 64'h54ff53a5f1d36f1c;

  reg [127:0] 	 Dout_reg;
  reg 		 EncDec_reg;
  
  wire [63:0] 	 f_func_out;
  reg [63:0] 	 selected_key;
  reg [127:0] 	 key_kl_or_ka;

  wire [127:0] 	 feistel_out;
  wire [127:0] 	 xor_out;
  wire [127:0] 	 fl_out;

  always @(Dout_reg)
  begin
    Dout <= Dout_reg;
  end

  assign 	 feistel_out = {Dout_reg[63:0] ^ f_func_out, Dout_reg[127:64]};
  always @(feistel_out)
  begin
    ka_out <= feistel_out;
  end

  assign 	 xor_out = Dout_reg ^ key_kl_or_ka;

  always @(kl or ka or state or round or EncDec_reg)
  begin
    key_kl_or_ka <= kl_or_ka(kl, ka, state, round, EncDec_reg);
  end
  always @(key_kl_or_ka or state or round or EncDec_reg)
  begin
    selected_key <= select_key(key_kl_or_ka, state, round, EncDec_reg);
  end
  
  Camellia_f_func Camellia_f_func( .in  (Dout_reg[127:64]),
				   .out (f_func_out),
				   .key (selected_key) );
  Camellia_fl Camellia_fl( .in(Dout_reg),
			   .out(fl_out),
			   .key(key_kl_or_ka),
			   .EncDec_reg(EncDec_reg) );
  
  always @(posedge CLK) begin
    if(RSTn == 1'b0)
      Dout_reg <= 128'h00000000000000000000000000000000;
    else if(EN == 1)
      case(state)
	ST_KEY_GET                                                  : Dout_reg <= Kin;
	ST_KEY_F_FUNC                                               : Dout_reg <= feistel_out;
	ST_KEY_XOR, ST_RANDOMIZE_INITIAL_XOR, ST_RANDOMIZE_FINAL_XOR: Dout_reg <= xor_out;
	ST_RANDOMIZE_GET                                            : Dout_reg <= Din;
	ST_RANDOMIZE_FL_1, ST_RANDOMIZE_FL_2                        : Dout_reg <= fl_out;
	ST_RANDOMIZE_F_FUNC:

	  if(round == 5'd18)
	    Dout_reg <= {feistel_out[63:0], feistel_out[127:64]};
	  else
	    Dout_reg <= feistel_out;
	
      endcase
  end


  always @(posedge CLK) begin
    if(RSTn == 1'b0)
      EncDec_reg <= 1'b0;
    else if(EN == 1)
      if(state == ST_RANDOMIZE_GET) EncDec_reg <= EncDec;
  end


  function [127:0] kl_or_ka;
    input [127:0] kl;
    input [127:0] ka;
    input [3:0]   state;
    input [4:0]   round;
    input 	  EncDec_reg;

    case(state)
      ST_KEY_XOR                               : kl_or_ka = kl;
      ST_RANDOMIZE_FL_1, ST_RANDOMIZE_FINAL_XOR  : kl_or_ka = (EncDec_reg == Enc) ? ka : kl;
      ST_RANDOMIZE_FL_2, ST_RANDOMIZE_INITIAL_XOR: kl_or_ka = (EncDec_reg == Enc) ? kl : ka;
      ST_RANDOMIZE_F_FUNC:
	case(round)
	  5'd03, 5'd04, 5'd7, 5'd8, 5'd10, 5'd13, 5'd14, 5'd17, 5'd18:
	    kl_or_ka = (EncDec_reg == Enc) ? kl : ka;
	  default:
	    kl_or_ka = (EncDec_reg == Enc) ? ka : kl;
	endcase

      default:
	kl_or_ka = kl;
    endcase
  endfunction


  function [63:0] select_key;
    input [127:0] kl_or_ka;
    input [3:0]   state;
    input [4:0]   round;
    input 	  EncDec_reg;

    case(state)
      ST_KEY_F_FUNC:
	case(round)
	  5'd01:   select_key = SIGMA1;
	  5'd02:   select_key = SIGMA2;
	  5'd03:   select_key = SIGMA3;
	  default: select_key = SIGMA4;
	endcase

      ST_RANDOMIZE_F_FUNC:
	case(round)
	  5'd01, 5'd03, 5'd05, 5'd07, 5'd09, 5'd11, 5'd13, 5'd15, 5'd17:
	    select_key = (EncDec_reg == Enc) ? kl_or_ka[127:64] : kl_or_ka[ 63: 0];
	  default:
	    select_key = (EncDec_reg == Enc) ? kl_or_ka[ 63: 0] : kl_or_ka[127:64];
	endcase

      default:

	select_key = kl_or_ka[63:0];
    endcase
  endfunction
endmodule
module Camellia_randomize( Kin, Din, Dout, EncDec, RSTn, EN, CLK, state, round, kl, ka, ka_out );

  input          CLK, RSTn, EN;
  input [3:0] 	 state;
  input [4:0] 	 round;
  input [127:0]  Din, Kin;
  input [127:0]  kl, ka;
  input 	 EncDec;
  output reg [127:0] Dout;
  output reg [127:0] ka_out;


  parameter ST_IDLE                = 4'h0;
  parameter ST_IDLE_READY          = 4'h1;


  parameter ST_KEY_GET             = 4'h3;
  parameter ST_KEY_F_FUNC          = 4'h4;
  parameter ST_KEY_XOR             = 4'h5;


  parameter ST_RANDOMIZE_GET         = 4'h7;
  parameter ST_RANDOMIZE_INITIAL_XOR = 4'h8;
  parameter ST_RANDOMIZE_FINAL_XOR   = 4'h9;
  parameter ST_RANDOMIZE_F_FUNC      = 4'ha;
  parameter ST_RANDOMIZE_FL_1        = 4'hb;
  parameter ST_RANDOMIZE_FL_2        = 4'hc;

  parameter Enc = 1'b0;
  parameter Dec = 1'b1;


  parameter SIGMA1 = 64'ha09e667f3bcc908b;
  parameter SIGMA2 = 64'hb67ae8584caa73b2;
  parameter SIGMA3 = 64'hc6ef372fe94f82be;
  parameter SIGMA4 = 64'h54ff53a5f1d36f1c;

  reg [127:0] 	 Dout_reg;
  reg 		 EncDec_reg;
  
  wire [63:0] 	 f_func_out;
  reg [63:0] 	 selected_key;
  reg [127:0] 	 key_kl_or_ka;

  wire [127:0] 	 feistel_out;
  wire [127:0] 	 xor_out;
  wire [127:0] 	 fl_out;

  always @(Dout_reg)
  begin
    Dout <= Dout_reg;
  end

  assign 	 feistel_out = {Dout_reg[63:0] ^ f_func_out, Dout_reg[127:64]};
  always @(feistel_out)
  begin
    ka_out <= feistel_out;
  end

  assign 	 xor_out = Dout_reg ^ key_kl_or_ka;

  always @(kl or ka or state or round or EncDec_reg)
  begin
    key_kl_or_ka <= kl_or_ka(kl, ka, state, round, EncDec_reg);
  end
  always @(key_kl_or_ka or state or round or EncDec_reg)
  begin
    selected_key <= select_key(key_kl_or_ka, state, round, EncDec_reg);
  end
  
  Camellia_f_func Camellia_f_func( .in  (Dout_reg[127:64]),
				   .out (f_func_out),
				   .key (selected_key) );
  Camellia_fl Camellia_fl( .in(Dout_reg),
			   .out(fl_out),
			   .key(key_kl_or_ka),
			   .EncDec_reg(EncDec_reg) );
  
  always @(posedge CLK) begin
    if(RSTn == 1'b0)
      Dout_reg <= 128'h00000000000000000000000000000000;
    else if(EN == 1)
      case(state)
	ST_KEY_GET                                                  : Dout_reg <= Kin;
	ST_KEY_F_FUNC                                               : Dout_reg <= feistel_out;
	ST_KEY_XOR, ST_RANDOMIZE_INITIAL_XOR, ST_RANDOMIZE_FINAL_XOR: Dout_reg <= xor_out;
	ST_RANDOMIZE_GET                                            : Dout_reg <= Din;
	ST_RANDOMIZE_FL_1, ST_RANDOMIZE_FL_2                        : Dout_reg <= fl_out;
	ST_RANDOMIZE_F_FUNC:

	  if(round == 5'd18)
	    Dout_reg <= {feistel_out[63:0], feistel_out[127:64]};
	  else
	    Dout_reg <= feistel_out;
	
      endcase
  end


  always @(posedge CLK) begin
    if(RSTn == 1'b0)
      EncDec_reg <= 1'b0;
    else if(EN == 1)
      if(state == ST_RANDOMIZE_GET) EncDec_reg <= EncDec;
  end


  function [127:0] kl_or_ka;
    input [127:0] kl;
    input [127:0] ka;
    input [3:0]   state;
    input [4:0]   round;
    input 	  EncDec_reg;

    case(state)
      ST_KEY_XOR                               : kl_or_ka = kl;
      ST_RANDOMIZE_FL_1, ST_RANDOMIZE_FINAL_XOR  : kl_or_ka = (EncDec_reg == Enc) ? ka : kl;
      ST_RANDOMIZE_FL_2, ST_RANDOMIZE_INITIAL_XOR: kl_or_ka = (EncDec_reg == Enc) ? kl : ka;
      ST_RANDOMIZE_F_FUNC:
	case(round)
	  5'd03, 5'd04, 5'd7, 5'd8, 5'd10, 5'd13, 5'd14, 5'd17, 5'd18:
	    kl_or_ka = (EncDec_reg == Enc) ? kl : ka;
	  default:
	    kl_or_ka = (EncDec_reg == Enc) ? ka : kl;
	endcase

      default:
	kl_or_ka = kl;
    endcase
  endfunction


  function [63:0] select_key;
    input [127:0] kl_or_ka;
    input [3:0]   state;
    input [4:0]   round;
    input 	  EncDec_reg;

    case(state)
      ST_KEY_F_FUNC:
	case(round)
	  5'd01:   select_key = SIGMA1;
	  5'd02:   select_key = SIGMA2;
	  5'd03:   select_key = SIGMA3;
	  default: select_key = SIGMA4;
	endcase

      ST_RANDOMIZE_F_FUNC:
	case(round)
	  5'd01, 5'd03, 5'd05, 5'd07, 5'd09, 5'd11, 5'd13, 5'd15, 5'd17:
	    select_key = (EncDec_reg == Enc) ? kl_or_ka[127:64] : kl_or_ka[ 63: 0];
	  default:
	    select_key = (EncDec_reg == Enc) ? kl_or_ka[ 63: 0] : kl_or_ka[127:64];
	endcase

      default:

	select_key = kl_or_ka[63:0];
    endcase
  endfunction
endmodule