data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v
 line:37: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10 source = 32\'h00000002;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10 source = 32\'h00000003; interrupt = 1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10 source = 32\'h00000004;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10 interrupt = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #10 source = 32\'h00000005;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #10 source = 32\'h00000006;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10 interrupt = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10 source = 32\'h00000007;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10 source = 32\'h00000008;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/pc_sel_tb.v:14: Cannot find file containing module: \'pc_sel\'\n pc_sel pcsel(.I_clk(clk), .I_interrupt(interrupt), .I_mtvec(trap), .I_data(source), .O_data(destination));\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/pc_sel\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/pc_sel.v\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/pc_sel.sv\n             pc_sel\n             pc_sel.v\n             pc_sel.sv\n             obj_dir/pc_sel\n             obj_dir/pc_sel.v\n             obj_dir/pc_sel.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pc_sel_tb;
	

	reg clk;
	reg interrupt;
	reg [31:0] trap;
	reg [31:0] source;
	wire [31:0] destination;


	pc_sel pcsel(.I_clk(clk), .I_interrupt(interrupt), .I_mtvec(trap), .I_data(source), .O_data(destination));


	always begin
		#5 clk = ~clk;
	end

	initial begin

		clk = 1; interrupt = 0; trap = 32'h0000000f; source = 32'h00000001;
	

		#10 source = 32'h00000002;
		#10 source = 32'h00000003; interrupt = 1; 
		#10 source = 32'h00000004;
		#10 interrupt = 0;
		#10 source = 32'h00000005;
		#10 source = 32'h00000006;
        #10 interrupt = 1;
        #10 source = 32'h00000007;
        #10 source = 32'h00000008;
		

		#10 $finish;
	end
	
endmodule
module pc_sel_tb;

	

	reg clk;
	reg interrupt;
	reg [31:0] trap;
	reg [31:0] source;
	wire [31:0] destination;


	pc_sel pcsel(.I_clk(clk), .I_interrupt(interrupt), .I_mtvec(trap), .I_data(source), .O_data(destination));


	always begin
		#5 clk = ~clk;
	end

	initial begin

		clk = 1; interrupt = 0; trap = 32'h0000000f; source = 32'h00000001;
	

		#10 source = 32'h00000002;
		#10 source = 32'h00000003; interrupt = 1; 
		#10 source = 32'h00000004;
		#10 interrupt = 0;
		#10 source = 32'h00000005;
		#10 source = 32'h00000006;
        #10 interrupt = 1;
        #10 source = 32'h00000007;
        #10 source = 32'h00000008;
		

		#10 $finish;
	end
	
endmodule