data/full_repos/permissive/133819542/src/ex_mem.v
1: b'%Error: data/full_repos/permissive/133819542/src/ex_mem.v:7: Cannot find include file: const.v\n`include "const.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.sv\n             const.v\n             const.v.v\n             const.v.sv\n             obj_dir/const.v\n             obj_dir/const.v.v\n             obj_dir/const.v.sv\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:15: Define or directive not defined: \'`RegAddrBus\'\n    input  wire  [`RegAddrBus]      ex_waddr    ,\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input  wire  [`RegAddrBus]      ex_waddr    ,\n                             ^\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:16: Define or directive not defined: \'`RegBus\'\n    input  wire  [`RegBus    ]      ex_wdata    ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [`RegBus    ]      ex_hi       ,\n    ^~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:18: Define or directive not defined: \'`RegBus\'\n    input  wire  [`RegBus    ]      ex_hi       ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:19: Define or directive not defined: \'`RegBus\'\n    input  wire  [`RegBus    ]      ex_lo       ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:20: Define or directive not defined: \'`AluOpBus\'\n    input  wire  [`AluOpBus  ]      ex_aluop    ,\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:21: Define or directive not defined: \'`RegBus\'\n    input  wire  [`RegBus    ]      ex_mem_addr ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:22: Define or directive not defined: \'`RegBus\'\n    input  wire  [`RegBus    ]      ex_opv2     ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:25: Define or directive not defined: \'`StallBus\'\n    input  wire  [`StallBus  ]      stall       ,\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg  [`RegAddrBus]      mem_waddr   ,  \n    ^~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:29: Define or directive not defined: \'`RegAddrBus\'\n    output  reg  [`RegAddrBus]      mem_waddr   ,  \n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:30: Define or directive not defined: \'`RegBus\'\n    output  reg  [`RegBus    ]      mem_wdata   ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:32: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg  [`RegBus    ]      mem_hi      ,\n    ^~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:32: Define or directive not defined: \'`RegBus\'\n    output  reg  [`RegBus    ]      mem_hi      ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:33: Define or directive not defined: \'`RegBus\'\n    output  reg  [`RegBus    ]      mem_lo      ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:34: Define or directive not defined: \'`AluOpBus\'\n    output  reg  [`AluOpBus  ]      mem_aluop   ,\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:35: Define or directive not defined: \'`RegBus\'\n    output  reg  [`RegBus    ]      mem_mem_addr,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:36: Define or directive not defined: \'`RegBus\'\n    output  reg  [`RegBus    ]      mem_opv2     \n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:41: Define or directive not defined: \'`RESET_ENABLE\'\n        if(rst == `RESET_ENABLE || (stall[3] == `STOP && stall[4] == `NOSTOP)) begin \n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:41: Define or directive not defined: \'`STOP\'\n        if(rst == `RESET_ENABLE || (stall[3] == `STOP && stall[4] == `NOSTOP)) begin \n                                                ^~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:41: Define or directive not defined: \'`NOSTOP\'\n        if(rst == `RESET_ENABLE || (stall[3] == `STOP && stall[4] == `NOSTOP)) begin \n                                                                     ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:42: Define or directive not defined: \'`NOPRegAddr\'\n            mem_waddr  <=  `NOPRegAddr;\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:43: Define or directive not defined: \'`WRITE_DISABLE\'\n            mem_we     <=  `WRITE_DISABLE;\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:44: Define or directive not defined: \'`ZERO_WORD\'\n            mem_wdata  <=  `ZERO_WORD;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:45: Define or directive not defined: \'`WRITE_DISABLE\'\n            mem_whilo  <=  `WRITE_DISABLE;\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:46: Define or directive not defined: \'`ZERO_WORD\'\n            mem_hi     <=  `ZERO_WORD;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:47: Define or directive not defined: \'`ZERO_WORD\'\n            mem_lo     <=  `ZERO_WORD;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ex_mem.v:51: Define or directive not defined: \'`NOSTOP\'\n        end else if (stall[3] == `NOSTOP) begin \n                                 ^~~~~~~\n%Error: Exiting due to 30 error(s)\n'
module ex_mem (
    input  wire                     clk         ,
    input  wire                     rst         ,


    input  wire                     ex_we       ,
    input  wire  [`RegAddrBus]      ex_waddr    ,
    input  wire  [`RegBus    ]      ex_wdata    ,
    input  wire                     ex_whilo    ,
    input  wire  [`RegBus    ]      ex_hi       ,
    input  wire  [`RegBus    ]      ex_lo       ,
    input  wire  [`AluOpBus  ]      ex_aluop    ,
    input  wire  [`RegBus    ]      ex_mem_addr ,
    input  wire  [`RegBus    ]      ex_opv2     ,


    input  wire  [`StallBus  ]      stall       ,


    output  reg                     mem_we      ,
    output  reg  [`RegAddrBus]      mem_waddr   ,  
    output  reg  [`RegBus    ]      mem_wdata   ,
    output  reg                     mem_whilo   ,
    output  reg  [`RegBus    ]      mem_hi      ,
    output  reg  [`RegBus    ]      mem_lo      ,
    output  reg  [`AluOpBus  ]      mem_aluop   ,
    output  reg  [`RegBus    ]      mem_mem_addr,
    output  reg  [`RegBus    ]      mem_opv2     

);

    always @(posedge clk) begin
        if(rst == `RESET_ENABLE || (stall[3] == `STOP && stall[4] == `NOSTOP)) begin 
            mem_waddr  <=  `NOPRegAddr;
            mem_we     <=  `WRITE_DISABLE;
            mem_wdata  <=  `ZERO_WORD;
            mem_whilo  <=  `WRITE_DISABLE;
            mem_hi     <=  `ZERO_WORD;
            mem_lo     <=  `ZERO_WORD;
            mem_aluop     <=  0 ;            
            mem_mem_addr  <=  0 ;            
            mem_opv2      <=  0 ;
        end else if (stall[3] == `NOSTOP) begin 
            mem_waddr  <=  ex_waddr;
            mem_we     <=  ex_we;
            mem_wdata  <=  ex_wdata;
            mem_whilo  <=  ex_whilo; 
            mem_hi     <=  ex_hi;
            mem_lo     <=  ex_lo;
            mem_aluop    <=  ex_aluop   ;
            mem_mem_addr <=  ex_mem_addr;
            mem_opv2     <=  ex_opv2    ;
        end
    end

endmodule
module ex_mem (
    input  wire                     clk         ,
    input  wire                     rst         ,


    input  wire                     ex_we       ,
    input  wire  [`RegAddrBus]      ex_waddr    ,
    input  wire  [`RegBus    ]      ex_wdata    ,
    input  wire                     ex_whilo    ,
    input  wire  [`RegBus    ]      ex_hi       ,
    input  wire  [`RegBus    ]      ex_lo       ,
    input  wire  [`AluOpBus  ]      ex_aluop    ,
    input  wire  [`RegBus    ]      ex_mem_addr ,
    input  wire  [`RegBus    ]      ex_opv2     ,


    input  wire  [`StallBus  ]      stall       ,


    output  reg                     mem_we      ,
    output  reg  [`RegAddrBus]      mem_waddr   ,  
    output  reg  [`RegBus    ]      mem_wdata   ,
    output  reg                     mem_whilo   ,
    output  reg  [`RegBus    ]      mem_hi      ,
    output  reg  [`RegBus    ]      mem_lo      ,
    output  reg  [`AluOpBus  ]      mem_aluop   ,
    output  reg  [`RegBus    ]      mem_mem_addr,
    output  reg  [`RegBus    ]      mem_opv2     

);


    always @(posedge clk) begin
        if(rst == `RESET_ENABLE || (stall[3] == `STOP && stall[4] == `NOSTOP)) begin 
            mem_waddr  <=  `NOPRegAddr;
            mem_we     <=  `WRITE_DISABLE;
            mem_wdata  <=  `ZERO_WORD;
            mem_whilo  <=  `WRITE_DISABLE;
            mem_hi     <=  `ZERO_WORD;
            mem_lo     <=  `ZERO_WORD;
            mem_aluop     <=  0 ;            
            mem_mem_addr  <=  0 ;            
            mem_opv2      <=  0 ;
        end else if (stall[3] == `NOSTOP) begin 
            mem_waddr  <=  ex_waddr;
            mem_we     <=  ex_we;
            mem_wdata  <=  ex_wdata;
            mem_whilo  <=  ex_whilo; 
            mem_hi     <=  ex_hi;
            mem_lo     <=  ex_lo;
            mem_aluop    <=  ex_aluop   ;
            mem_mem_addr <=  ex_mem_addr;
            mem_opv2     <=  ex_opv2    ;
        end
    end

endmodule