data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v
 line:1119: before: "wire"
1: b'%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:72: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:88: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] disp_i_rs1,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:89: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0] disp_i_rs2,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:90: Define or directive not defined: \'`E203_DECINFO_WIDTH\'\n  input  [`E203_DECINFO_WIDTH-1:0]  disp_i_info,  \n          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:96: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0] disp_o_alu_rs1,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:97: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0] disp_o_alu_rs2,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:98: Define or directive not defined: \'`E203_DECINFO_WIDTH\'\n  output [`E203_DECINFO_WIDTH-1:0]  disp_o_alu_info,  \n          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:99: Define or directive not defined: \'`E203_PC_SIZE\'\n  output [`E203_PC_SIZE-1:0] disp_o_alu_pc,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:118: Define or directive not defined: \'`E203_DECINFO_GRP_WIDTH\'\n wire [`E203_DECINFO_GRP_WIDTH-1:0] disp_i_info_grp  = disp_i_info [`E203_DECINFO_GRP];\n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:118: Define or directive not defined: \'`E203_DECINFO_GRP\'\n wire [`E203_DECINFO_GRP_WIDTH-1:0] disp_i_info_grp  = disp_i_info [`E203_DECINFO_GRP];\n                                                                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`E203_DECINFO_GRP_WIDTH-1:0] disp_i_info_grp  = disp_i_info [`E203_DECINFO_GRP];\n                                                                                     ^\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:125: Define or directive not defined: \'`E203_DECINFO_GRP_CSR\'\n wire disp_csr = (disp_i_info_grp == `E203_DECINFO_GRP_CSR); \n                                     ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:125: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire disp_csr = (disp_i_info_grp == `E203_DECINFO_GRP_CSR); \n                                                          ^\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:127: Define or directive not defined: \'`E203_DECINFO_GRP_AGU\'\n wire disp_alu_longp_prdt = (disp_i_info_grp == `E203_DECINFO_GRP_AGU)  \n                                                ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:127: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire disp_alu_longp_prdt = (disp_i_info_grp == `E203_DECINFO_GRP_AGU)  \n                                                                     ^\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:131: Define or directive not defined: \'`E203_DECINFO_GRP_BJP\'\n wire disp_fence_fencei   = (disp_i_info_grp == `E203_DECINFO_GRP_BJP) & \n                                                ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:131: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire disp_fence_fencei   = (disp_i_info_grp == `E203_DECINFO_GRP_BJP) & \n                                                                     ^\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:132: Define or directive not defined: \'`E203_DECINFO_BJP_FENCE\'\n                ( disp_i_info [`E203_DECINFO_BJP_FENCE] | disp_i_info [`E203_DECINFO_BJP_FENCEI]);   \n                               ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:132: Define or directive not defined: \'`E203_DECINFO_BJP_FENCEI\'\n                ( disp_i_info [`E203_DECINFO_BJP_FENCE] | disp_i_info [`E203_DECINFO_BJP_FENCEI]);   \n                                                                       ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:223: Define or directive not defined: \'`E203_XLEN\'\n wire [`E203_XLEN-1:0] disp_i_rs1_msked = disp_i_rs1 & {`E203_XLEN{~disp_i_rs1x0}};\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:223: Define or directive not defined: \'`E203_XLEN\'\n wire [`E203_XLEN-1:0] disp_i_rs1_msked = disp_i_rs1 & {`E203_XLEN{~disp_i_rs1x0}};\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:224: Define or directive not defined: \'`E203_XLEN\'\n wire [`E203_XLEN-1:0] disp_i_rs2_msked = disp_i_rs2 & {`E203_XLEN{~disp_i_rs2x0}};\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_disp.v:224: Define or directive not defined: \'`E203_XLEN\'\n wire [`E203_XLEN-1:0] disp_i_rs2_msked = disp_i_rs2 & {`E203_XLEN{~disp_i_rs2x0}};\n                                                        ^~~~~~~~~~\n%Error: Exiting due to 23 error(s)\n'
module e203_exu_disp(
		input  wfi_halt_exu_req,
		output wfi_halt_exu_ack,

		input  oitf_empty,
		input  amo_wait,


		input  disp_i_valid,
		output disp_i_ready,


		input  disp_i_rs1x0,
		input  disp_i_rs2x0,
		input  [`E203_XLEN-1:0] disp_i_rs1,
		input  [`E203_XLEN-1:0] disp_i_rs2,
		input  [`E203_DECINFO_WIDTH-1:0]  disp_i_info,  


		output disp_o_alu_valid, 
		input  disp_o_alu_ready,
		input  disp_o_alu_longpipe,
		output [`E203_XLEN-1:0] disp_o_alu_rs1,
		output [`E203_XLEN-1:0] disp_o_alu_rs2,
		output [`E203_DECINFO_WIDTH-1:0]  disp_o_alu_info,  
		output [`E203_PC_SIZE-1:0] disp_o_alu_pc,



		input oitfrd_match_disprs1,
		input oitfrd_match_disprs2,
		input oitfrd_match_disprs3,
		input oitfrd_match_disprd,


		output disp_oitf_ena,
		input  disp_oitf_ready,

		
		input clk,
		input rst_n
	);


	wire [`E203_DECINFO_GRP_WIDTH-1:0] disp_i_info_grp  = disp_i_info [`E203_DECINFO_GRP];






	wire disp_csr = (disp_i_info_grp == `E203_DECINFO_GRP_CSR); 

	wire disp_alu_longp_prdt = (disp_i_info_grp == `E203_DECINFO_GRP_AGU)  
	wire disp_alu_longp_real = disp_o_alu_longpipe;


	wire disp_fence_fencei   = (disp_i_info_grp == `E203_DECINFO_GRP_BJP) & 
															 ( disp_i_info [`E203_DECINFO_BJP_FENCE] | disp_i_info [`E203_DECINFO_BJP_FENCEI]);   

	wire disp_i_valid_pos; 
	wire disp_i_ready_pos = disp_o_alu_ready;
	assign disp_o_alu_valid = disp_i_valid_pos; 
	
































	wire raw_dep =  ((oitfrd_match_disprs1) |
									 (oitfrd_match_disprs2) |
									 (oitfrd_match_disprs3)); 

















	

	wire waw_dep = (oitfrd_match_disprd); 
	wire dep = raw_dep | waw_dep;



	assign wfi_halt_exu_ack = oitf_empty & (~amo_wait);

	wire disp_condition = 





				(disp_csr ? oitf_empty : 1'b1)

				& (disp_fence_fencei ? oitf_empty : 1'b1)

				& (~wfi_halt_exu_req)   

				& (~dep)   





				& (disp_alu_longp_prdt ? disp_oitf_ready : 1'b1);

	assign disp_i_valid_pos = disp_condition & disp_i_valid; 
	assign disp_i_ready     = disp_condition & disp_i_ready_pos; 


	wire [`E203_XLEN-1:0] disp_i_rs1_msked = disp_i_rs1 & {`E203_XLEN{~disp_i_rs1x0}};
	wire [`E203_XLEN-1:0] disp_i_rs2_msked = disp_i_rs2 & {`E203_XLEN{~disp_i_rs2x0}};

	assign disp_o_alu_rs1   = disp_i_rs1_msked;
	assign disp_o_alu_rs2   = disp_i_rs2_msked;

	assign disp_o_alu_info  = disp_i_info;  
	


	assign disp_oitf_ena = disp_o_alu_valid & disp_o_alu_ready & disp_alu_longp_real;



endmodule
module e203_exu_disp(
		input  wfi_halt_exu_req,
		output wfi_halt_exu_ack,

		input  oitf_empty,
		input  amo_wait,


		input  disp_i_valid,
		output disp_i_ready,


		input  disp_i_rs1x0,
		input  disp_i_rs2x0,
		input  [`E203_XLEN-1:0] disp_i_rs1,
		input  [`E203_XLEN-1:0] disp_i_rs2,
		input  [`E203_DECINFO_WIDTH-1:0]  disp_i_info,  


		output disp_o_alu_valid, 
		input  disp_o_alu_ready,
		input  disp_o_alu_longpipe,
		output [`E203_XLEN-1:0] disp_o_alu_rs1,
		output [`E203_XLEN-1:0] disp_o_alu_rs2,
		output [`E203_DECINFO_WIDTH-1:0]  disp_o_alu_info,  
		output [`E203_PC_SIZE-1:0] disp_o_alu_pc,



		input oitfrd_match_disprs1,
		input oitfrd_match_disprs2,
		input oitfrd_match_disprs3,
		input oitfrd_match_disprd,


		output disp_oitf_ena,
		input  disp_oitf_ready,

		
		input clk,
		input rst_n
	);



	wire [`E203_DECINFO_GRP_WIDTH-1:0] disp_i_info_grp  = disp_i_info [`E203_DECINFO_GRP];






	wire disp_csr = (disp_i_info_grp == `E203_DECINFO_GRP_CSR); 

	wire disp_alu_longp_prdt = (disp_i_info_grp == `E203_DECINFO_GRP_AGU)  
	wire disp_alu_longp_real = disp_o_alu_longpipe;


	wire disp_fence_fencei   = (disp_i_info_grp == `E203_DECINFO_GRP_BJP) & 
															 ( disp_i_info [`E203_DECINFO_BJP_FENCE] | disp_i_info [`E203_DECINFO_BJP_FENCEI]);   

	wire disp_i_valid_pos; 
	wire disp_i_ready_pos = disp_o_alu_ready;
	assign disp_o_alu_valid = disp_i_valid_pos; 
	
































	wire raw_dep =  ((oitfrd_match_disprs1) |
									 (oitfrd_match_disprs2) |
									 (oitfrd_match_disprs3)); 

















	

	wire waw_dep = (oitfrd_match_disprd); 
	wire dep = raw_dep | waw_dep;



	assign wfi_halt_exu_ack = oitf_empty & (~amo_wait);

	wire disp_condition = 





				(disp_csr ? oitf_empty : 1'b1)

				& (disp_fence_fencei ? oitf_empty : 1'b1)

				& (~wfi_halt_exu_req)   

				& (~dep)   





				& (disp_alu_longp_prdt ? disp_oitf_ready : 1'b1);

	assign disp_i_valid_pos = disp_condition & disp_i_valid; 
	assign disp_i_ready     = disp_condition & disp_i_ready_pos; 


	wire [`E203_XLEN-1:0] disp_i_rs1_msked = disp_i_rs1 & {`E203_XLEN{~disp_i_rs1x0}};
	wire [`E203_XLEN-1:0] disp_i_rs2_msked = disp_i_rs2 & {`E203_XLEN{~disp_i_rs2x0}};

	assign disp_o_alu_rs1   = disp_i_rs1_msked;
	assign disp_o_alu_rs2   = disp_i_rs2_msked;

	assign disp_o_alu_info  = disp_i_info;  
	


	assign disp_oitf_ena = disp_o_alu_valid & disp_o_alu_ready & disp_alu_longp_real;



endmodule