data/full_repos/permissive/194847941/demo_v_5_6/11_SparkRoad/FPGA/sparkroad/src/rtl/top.v
1: b"%Error: data/full_repos/permissive/194847941/demo_v_5_6/11_SparkRoad/FPGA/sparkroad/src/rtl/top.v:52: Cannot find file containing module: 'uart'\nuart\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo_v_5_6/11_SparkRoad/FPGA/sparkroad/src/rtl,data/full_repos/permissive/194847941/uart\n             data/full_repos/permissive/194847941/demo_v_5_6/11_SparkRoad/FPGA/sparkroad/src/rtl,data/full_repos/permissive/194847941/uart.v\n             data/full_repos/permissive/194847941/demo_v_5_6/11_SparkRoad/FPGA/sparkroad/src/rtl,data/full_repos/permissive/194847941/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Error: data/full_repos/permissive/194847941/demo_v_5_6/11_SparkRoad/FPGA/sparkroad/src/rtl/top.v:84: Cannot find file containing module: 'flash_dri'\nflash_dri u_flash_dri\n^~~~~~~~~\n%Error: data/full_repos/permissive/194847941/demo_v_5_6/11_SparkRoad/FPGA/sparkroad/src/rtl/top.v:114: Cannot find file containing module: 'tube_dri'\ntube_dri u_tube_dri\n^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top
(
    input   wire        sclk,
    
    input   wire        key,
    

    input   wire        rxd,
    output  wire        txd,
    

    output  wire        flash_sck,
    output  wire        flash_cs,
    output  wire        flash_sdo,
    input   wire        flash_sdi,
    

    output  wire [7:0]  tube,
    output  wire [3:0]  tube_sel,
    

    output  wire[15:0]  led
);



wire start;
wire [2:0] mod_sel;
wire [23:0] fls_addr;
wire [7:0] fls_write;
wire [7:0] fls_read;
wire frd_en;
wire [23:0] frd_addr;
wire [7:0] frd_data;
wire [15:0] id;
wire busy;

wire [3:0] sm_bit1_num ;
wire [3:0] sm_bit2_num ;
wire [3:0] sm_bit3_num ;
wire [3:0] sm_bit4_num ;

uart
#(
    .BAUDRATE(115200        ),
    .CLK_RATE(24000000      )
)
u_uart
(
    .clk        (sclk       ),


    .rx         (rxd        ),
    .tx         (txd        ),
    

    .sm_bit1    (sm_bit1_num),
    .sm_bit2    (sm_bit2_num),
    .sm_bit3    (sm_bit3_num),
    .sm_bit4    (sm_bit4_num),
	

    .led        (led        ),
    

    .start      (start      ),
    .mod_sel    (mod_sel    ),
    .fls_addr   (fls_addr   ),
    .fls_write  (fls_write  ),
    .fls_read   (fls_read   ),
    .id         (id         ),
    .busy       (busy       )
);

flash_dri u_flash_dri
(
    .clk        (sclk       ),


    .fls_sck    (flash_sck  ),
    .fls_ncs    (flash_cs   ),
    .fls_sdo    (flash_sdo  ),
    .fls_sdi    (flash_sdi  ),


    .start      (start      ),
    .mod_sel    (mod_sel    ),


    .fls_addr   (fls_addr   ),
    .fls_write  (fls_write  ),
    .fls_read   (fls_read   ),
    

    .frd_en     (frd_en     ),
    .frd_addr   (frd_addr   ),
    .frd_data   (frd_data   ),


    .id         (id         ),
    .busy       (busy       )
);


tube_dri u_tube_dri
( 
    .clk_24m        (sclk       ),
                                
    .sm_seg         (tube       ),
    .sm_bit         (tube_sel   ),
                                
    .sm_bit1_num    (sm_bit1_num),
    .sm_bit2_num    (sm_bit2_num),
    .sm_bit3_num    (sm_bit3_num),
    .sm_bit4_num    (sm_bit4_num)
);

endmodule
module top
(
    input   wire        sclk,
    
    input   wire        key,
    

    input   wire        rxd,
    output  wire        txd,
    

    output  wire        flash_sck,
    output  wire        flash_cs,
    output  wire        flash_sdo,
    input   wire        flash_sdi,
    

    output  wire [7:0]  tube,
    output  wire [3:0]  tube_sel,
    

    output  wire[15:0]  led
);




wire start;
wire [2:0] mod_sel;
wire [23:0] fls_addr;
wire [7:0] fls_write;
wire [7:0] fls_read;
wire frd_en;
wire [23:0] frd_addr;
wire [7:0] frd_data;
wire [15:0] id;
wire busy;

wire [3:0] sm_bit1_num ;
wire [3:0] sm_bit2_num ;
wire [3:0] sm_bit3_num ;
wire [3:0] sm_bit4_num ;

uart
#(
    .BAUDRATE(115200        ),
    .CLK_RATE(24000000      )
)
u_uart
(
    .clk        (sclk       ),


    .rx         (rxd        ),
    .tx         (txd        ),
    

    .sm_bit1    (sm_bit1_num),
    .sm_bit2    (sm_bit2_num),
    .sm_bit3    (sm_bit3_num),
    .sm_bit4    (sm_bit4_num),
	

    .led        (led        ),
    

    .start      (start      ),
    .mod_sel    (mod_sel    ),
    .fls_addr   (fls_addr   ),
    .fls_write  (fls_write  ),
    .fls_read   (fls_read   ),
    .id         (id         ),
    .busy       (busy       )
);

flash_dri u_flash_dri
(
    .clk        (sclk       ),


    .fls_sck    (flash_sck  ),
    .fls_ncs    (flash_cs   ),
    .fls_sdo    (flash_sdo  ),
    .fls_sdi    (flash_sdi  ),


    .start      (start      ),
    .mod_sel    (mod_sel    ),


    .fls_addr   (fls_addr   ),
    .fls_write  (fls_write  ),
    .fls_read   (fls_read   ),
    

    .frd_en     (frd_en     ),
    .frd_addr   (frd_addr   ),
    .frd_data   (frd_data   ),


    .id         (id         ),
    .busy       (busy       )
);


tube_dri u_tube_dri
( 
    .clk_24m        (sclk       ),
                                
    .sm_seg         (tube       ),
    .sm_bit         (tube_sel   ),
                                
    .sm_bit1_num    (sm_bit1_num),
    .sm_bit2_num    (sm_bit2_num),
    .sm_bit3_num    (sm_bit3_num),
    .sm_bit4_num    (sm_bit4_num)
);

endmodule