data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sources_1/new/CLAgen_4bit.v
data/verilator_xmls/04eb216d-e5c4-4f1b-a3bc-30da9564129e.xml
module CLAgen_4bit(
input [3:0] G,
input [3:0] P,
input c_in,
output reg [4:1] C
);








always@(*)
begin
        C[1] <= G[0] | (P[0] & c_in);
        C[2] <= G[1] | (P[1] & (G[0])| (P[1] & P[0] & c_in));
        C[3] <= G[2] | (P[2] & (G[1] | (P[1] & (G[0]) | (P[1] & P[0] & c_in))));
        C[4] <= G[3] | (P[3] & (G[2] | (P[2] & (G[1] | (P[1] & (G[0]) | (P[1] & P[0] & c_in))))));
end
endmodule
module CLAgen_4bit(
input [3:0] G,
input [3:0] P,
input c_in,
output reg [4:1] C
);









always@(*)
begin
        C[1] <= G[0] | (P[0] & c_in);
        C[2] <= G[1] | (P[1] & (G[0])| (P[1] & P[0] & c_in));
        C[3] <= G[2] | (P[2] & (G[1] | (P[1] & (G[0]) | (P[1] & P[0] & c_in))));
        C[4] <= G[3] | (P[3] & (G[2] | (P[2] & (G[1] | (P[1] & (G[0]) | (P[1] & P[0] & c_in))))));
end
endmodule