data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v
1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n             MBScore_const.v\n             MBScore_const.v.v\n             MBScore_const.v.sv\n             obj_dir/MBScore_const.v\n             obj_dir/MBScore_const.v.v\n             obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:4: Define or directive not defined: \'`DATA_WIDTH\'\n    input  [`DATA_WIDTH-1:0]    data_wr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:5: Define or directive not defined: \'`ADDR_WIDTH\'\n    input  [`ADDR_WIDTH-1:0]    inst_addr,data_addr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:9: Define or directive not defined: \'`ADDR_WIDTH\'\n    output [`ADDR_WIDTH-1:0]    addr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:11: Define or directive not defined: \'`DATA_WIDTH\'\n    output [`DATA_WIDTH-1:0]    data_rd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:12: Define or directive not defined: \'`DATA_WIDTH\'\n    inout  [`DATA_WIDTH-1:0]    data\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:19: Define or directive not defined: \'`DATA_WIDTH\'\n    reg [`DATA_WIDTH-1:0]       data_r;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:20: Define or directive not defined: \'`DATA_WIDTH\'\n    assign data     = (ram_we == 1\'b1) ? data_wr : `DATA_WIDTH\'bz;\n                                                   ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module MBScore_bus_ctrl(
    input                       clk,
    input  [`DATA_WIDTH-1:0]    data_wr,
    input  [`ADDR_WIDTH-1:0]    inst_addr,data_addr,
    input                       data_sel,
    input                       inst_re,data_re,data_we,
    input                       cpu_sel,
    output [`ADDR_WIDTH-1:0]    addr,
    output                      ram_re,ram_we,
    output [`DATA_WIDTH-1:0]    data_rd,
    inout  [`DATA_WIDTH-1:0]    data
);

    assign addr = (data_sel == 1'b1)? data_addr : inst_addr;
    assign ram_we = data_we;
    assign ram_re = inst_re | data_re;

    reg [`DATA_WIDTH-1:0]       data_r;
    assign data     = (ram_we == 1'b1) ? data_wr : `DATA_WIDTH'bz;

    always @(data)
    if(ram_re && cpu_sel)
    data_r = data;
    
    assign data_rd  = data_r;

endmodule
module MBScore_bus_ctrl(
    input                       clk,
    input  [`DATA_WIDTH-1:0]    data_wr,
    input  [`ADDR_WIDTH-1:0]    inst_addr,data_addr,
    input                       data_sel,
    input                       inst_re,data_re,data_we,
    input                       cpu_sel,
    output [`ADDR_WIDTH-1:0]    addr,
    output                      ram_re,ram_we,
    output [`DATA_WIDTH-1:0]    data_rd,
    inout  [`DATA_WIDTH-1:0]    data
);


    assign addr = (data_sel == 1'b1)? data_addr : inst_addr;
    assign ram_we = data_we;
    assign ram_re = inst_re | data_re;

    reg [`DATA_WIDTH-1:0]       data_r;
    assign data     = (ram_we == 1'b1) ? data_wr : `DATA_WIDTH'bz;

    always @(data)
    if(ram_re && cpu_sel)
    data_r = data;
    
    assign data_rd  = data_r;

endmodule