data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #102  rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #2   rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #100  rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #2   rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #100  rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #2   rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #100 rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #2   rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n # 61  dataIn = 8\'hFF;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n # 121  dataIn = 8\'hF0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n # 181  dataIn = 8\'h0F;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n # 241 dataIn = 8\'hAB;\n ^\n%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/display2_top_tb.v:17: Cannot find file containing module: \'display2_top\'\ndisplay2_top #(SCWIDTH, RCWIDTH) uut(.clk(clk), .rst(rst), .dataIn(dataIn), .sevenSeg(sevenSeg), .anode(anode));\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display2,data/full_repos/permissive/214278225/display2_top\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display2,data/full_repos/permissive/214278225/display2_top.v\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display2,data/full_repos/permissive/214278225/display2_top.sv\n             display2_top\n             display2_top.v\n             display2_top.sv\n             obj_dir/display2_top\n             obj_dir/display2_top.v\n             obj_dir/display2_top.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module display2_top_tb;

parameter SCWIDTH = 1;
parameter RCWIDTH = 1;


reg clk;
reg rst;
reg [7:0] dataIn;


wire [7:0] sevenSeg;
wire [3:0] anode;


display2_top #(SCWIDTH, RCWIDTH) uut(.clk(clk), .rst(rst), .dataIn(dataIn), .sevenSeg(sevenSeg), .anode(anode));


initial begin
	clk = 0;
	forever
		#5 clk = ~clk;
end


initial begin
	rst = 0;
	#102  rst = 1;
	#2   rst = 0;
	#100  rst = 1;
	#2   rst = 0;
	#100  rst = 1;
	#2   rst = 0;
	#100 rst = 1;
	#2   rst = 0;
	#100;
	$finish;
end


initial begin
	dataIn = 0;
	# 61  dataIn = 8'hFF;
	# 121  dataIn = 8'hF0;
	# 181  dataIn = 8'h0F;
	# 241 dataIn = 8'hAB;
end
      
endmodule
module display2_top_tb;


parameter SCWIDTH = 1;
parameter RCWIDTH = 1;


reg clk;
reg rst;
reg [7:0] dataIn;


wire [7:0] sevenSeg;
wire [3:0] anode;


display2_top #(SCWIDTH, RCWIDTH) uut(.clk(clk), .rst(rst), .dataIn(dataIn), .sevenSeg(sevenSeg), .anode(anode));


initial begin
	clk = 0;
	forever
		#5 clk = ~clk;
end


initial begin
	rst = 0;
	#102  rst = 1;
	#2   rst = 0;
	#100  rst = 1;
	#2   rst = 0;
	#100  rst = 1;
	#2   rst = 0;
	#100 rst = 1;
	#2   rst = 0;
	#100;
	$finish;
end


initial begin
	dataIn = 0;
	# 61  dataIn = 8'hFF;
	# 121  dataIn = 8'hF0;
	# 181  dataIn = 8'h0F;
	# 241 dataIn = 8'hAB;
end
      
endmodule