data/full_repos/permissive/179980995/Lab2/main.v
data/verilator_xmls/ffe682a8-a3d9-41a3-a9f9-e88c87fa4fb3.xml
module alu(
input a,
input b,
input cin,
input m,
input [1:0] s,
output f,
output cout
);
wire g, h;
logic_unit u1(a, b, s, h);
arithmetic_unit u2(a, b, cin, s, g, cout);
mux_2to1 u3(g, h, m, f);
endmodule
module alu(
input a,
input b,
input cin,
input m,
input [1:0] s,
output f,
output cout
);

wire g, h;
logic_unit u1(a, b, s, h);
arithmetic_unit u2(a, b, cin, s, g, cout);
mux_2to1 u3(g, h, m, f);
endmodule