data/full_repos/permissive/11455462/Addder.v
data/verilator_xmls/70bfad6e-dad7-4083-988f-65745bf9e2a4.xml
module Adder(out,in,clk);
    input [3:0] in ;
    input [1:0] clk ;
    output reg[3:0] out ;
    
    initial
    out<=0 ;
    always @(posedge clk)
    begin
       out<=out+1;
    end
    
endmodule
module Adder(out,in,clk);

    input [3:0] in ;
    input [1:0] clk ;
    output reg[3:0] out ;
    
    initial
    out<=0 ;
    always @(posedge clk)
    begin
       out<=out+1;
    end
    
endmodule