data/full_repos/permissive/100822769/alu.v
1: b'%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:116: Comparison is constant due to unsigned arithmetic\n                                                                 : ... In instance alu\n     if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0)) \n                   ^~\n                   ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:116: Comparison is constant due to unsigned arithmetic\n                                                                 : ... In instance alu\n     if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0)) \n                                    ^~\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:116: Comparison is constant due to unsigned arithmetic\n                                                                 : ... In instance alu\n     if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0)) \n                                                   ^\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:116: Comparison is constant due to unsigned arithmetic\n                                                                 : ... In instance alu\n     if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0)) \n                                                                    ^\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:134: Comparison is constant due to unsigned arithmetic\n                                                                 : ... In instance alu\n     if ((operand0 >= 0 && operand1 < 0 && result < 0)||(operand0 < 0 && operand1 >= 0 && result >= 0)) \n                   ^~\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:134: Comparison is constant due to unsigned arithmetic\n                                                                 : ... In instance alu\n     if ((operand0 >= 0 && operand1 < 0 && result < 0)||(operand0 < 0 && operand1 >= 0 && result >= 0)) \n                                    ^\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:134: Comparison is constant due to unsigned arithmetic\n                                                                 : ... In instance alu\n     if ((operand0 >= 0 && operand1 < 0 && result < 0)||(operand0 < 0 && operand1 >= 0 && result >= 0)) \n                                                                  ^\n%Error: Exiting due to 7 warning(s)\n'
module alu

(
    control,
    operand0,
    operand1,
    result,
    overflow,
    zero
);

   
    input [3:0]	 control;
    input [31:0] operand0; 
    input [31:0] operand1;
	
   	
    output [31:0] result;
    output overflow;
    output zero;

      
   
    reg [31:0] result;
    reg overflow;
    reg zero;
	
   
	always @(control)
	begin
	
		case (control)
			4'b0000 :
				begin
					result = operand0 & operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end	
			4'b0001:
				begin
					result = operand0 | operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end	
			4'b0010:
				begin
					result = operand0 + operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b0011:
				begin
					result = operand0 ^ operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b0100:
				begin
					result = ~(operand0 | operand1);
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b0110:
				begin
					result = operand0 - operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b0111:
				begin
					result = (operand0 < operand1) ? -1 : 0;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b1000:
				begin
					result = operand0 << operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b1001:
				begin
					result = operand0 >> operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
		
				
			4'b1011:
				begin
					result = operand0 + operand1;

					
					if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0)) 
					   begin
						overflow = 1;
					   end 
					else 
					     begin
						   overflow = 0;
					     end
					
					zero = (result == 0) ? 1 : 0;
					
					
			       end
			4'b1100:
				begin
					result = operand0 - operand1;

					
					if ((operand0 >= 0 && operand1 < 0 && result < 0)||(operand0 < 0 && operand1 >= 0 && result >= 0)) 
					   begin
						overflow = 1;
					   end 
				        else 
					    begin
						overflow = 0;
					    end
					
					zero = (result == 0) ? 1 : 0;
					
				
				end
			default:
				begin
					zero = 0;
					overflow = 0;
				end				
		endcase
		
	end

	
	
    
 endmodule
module alu

(
    control,
    operand0,
    operand1,
    result,
    overflow,
    zero
);


   
    input [3:0]	 control;
    input [31:0] operand0; 
    input [31:0] operand1;
	
   	
    output [31:0] result;
    output overflow;
    output zero;

      
   
    reg [31:0] result;
    reg overflow;
    reg zero;
	
   
	always @(control)
	begin
	
		case (control)
			4'b0000 :
				begin
					result = operand0 & operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end	
			4'b0001:
				begin
					result = operand0 | operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end	
			4'b0010:
				begin
					result = operand0 + operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b0011:
				begin
					result = operand0 ^ operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b0100:
				begin
					result = ~(operand0 | operand1);
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b0110:
				begin
					result = operand0 - operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b0111:
				begin
					result = (operand0 < operand1) ? -1 : 0;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b1000:
				begin
					result = operand0 << operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
			4'b1001:
				begin
					result = operand0 >> operand1;
					overflow = 0;
					zero = (result == 0) ? 1 : 0;
				end
		
				
			4'b1011:
				begin
					result = operand0 + operand1;

					
					if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0)) 
					   begin
						overflow = 1;
					   end 
					else 
					     begin
						   overflow = 0;
					     end
					
					zero = (result == 0) ? 1 : 0;
					
					
			       end
			4'b1100:
				begin
					result = operand0 - operand1;

					
					if ((operand0 >= 0 && operand1 < 0 && result < 0)||(operand0 < 0 && operand1 >= 0 && result >= 0)) 
					   begin
						overflow = 1;
					   end 
				        else 
					    begin
						overflow = 0;
					    end
					
					zero = (result == 0) ? 1 : 0;
					
				
				end
			default:
				begin
					zero = 0;
					overflow = 0;
				end				
		endcase
		
	end

	
	
    
 endmodule