data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulation_main.v
 line:126: before: ","
1: b'%Warning-LITENDIAN: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulation_main.v:45: Little bit endian vector: MSB < LSB of bit range: 0:11\n output  [0:11]          dvi_d_o;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulation_main.v:55: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7]           ad_red_i;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulation_main.v:56: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7]           ad_green_i;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulation_main.v:57: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7]           ad_blue_i;\n       ^\n%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulation_main.v:167: Cannot find file containing module: \'video_in_v3\'\n video_in_v3 INPUT_VID (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/video_in_v3\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/video_in_v3.v\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/video_in_v3.sv\n             video_in_v3\n             video_in_v3.v\n             video_in_v3.sv\n             obj_dir/video_in_v3\n             obj_dir/video_in_v3.v\n             obj_dir/video_in_v3.sv\n%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulation_main.v:190: Cannot find file containing module: \'blk_mem_gen5\'\n blk_mem_gen5 input_buffer_BRAM( \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulation_main.v:199: Cannot find file containing module: \'CPS_v3\'\n CPS_v3 processing_erosion (\n ^~~~~~\n%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulation_main.v:223: Cannot find file containing module: \'blk_mem_gen5\'\n  blk_mem_gen5 output_buffer_BRAM (\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/symulation_main.v:232: Cannot find file containing module: \'VIDEO_OUT3\'\n  VIDEO_OUT3 OUTPUT_VID (\n  ^~~~~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module symulation_main(

		rst_Chrontel_o,
		dvi_d_o,
		x_clk_p_o,
		x_clk_n_o,
		dvi_de_o,
		dvi_hsync_o,
		dvi_vsync_o,

		ad_dataclk_i,
		ad_hsync_i,
		ad_vsync_i,
		ad_red_i,
		ad_green_i,
		ad_blue_i,
		Bus2IP_Clk,
		Bus2IP_Reset,
		column_max,
		line_max
		);


	output  												rst_Chrontel_o;
	output  [0:11]										dvi_d_o;
	output  												x_clk_p_o;
	output  												x_clk_n_o;
	output  												dvi_de_o;
	output  												dvi_hsync_o;
	output  												dvi_vsync_o;

	input 												ad_dataclk_i;
	input 												ad_hsync_i;
	input 												ad_vsync_i;
	input [0:7] 										ad_red_i;
	input [0:7] 										ad_green_i;
	input [0:7] 										ad_blue_i;
	input                                     Bus2IP_Clk;
	input                                     Bus2IP_Reset;		
	
	output wire [10:0] column_max;
	output wire [10:0] line_max;
	


	wire [ 9:0 ] H_FP;
	wire [ 9:0 ] H_BP;
	wire [ 9:0 ] H_sync;
	wire [ 9:0 ] H_VldDat;
	wire [ 9:0 ] COLUMNS;
	wire [ 9:0 ] V_FP;
	wire [ 9:0 ] V_BP;
	wire [ 9:0 ] V_sync;
	wire [ 9:0 ] V_VldDat;
	wire [ 9:0 ] LINES;
	wire H_active;
	wire V_active;
	wire [9:0] HighCol;
	wire [9:0] LowCol;
	wire [9:0] LowLine;
	wire [9:0] HighLine;
	wire [23:0] Color;


	wire 												vld_video_i,vld_video_o;
	wire 												vld_mem_i,vld_mem_o;
	wire 												rdy,vld;
	

	wire clka_bram12,clka_bram3;
	
	wire wea_bram3;
	wire [6:0] addra_bram3,addra_bram12;
	wire [383:0] dina_bram3,dina_bram12;
	
	wire [6:0] addrb_bram12_i;
	wire [6:0] addrb_bram12_o;
	wire [6:0] addrb_bram3_o;
	wire [6:0] addrb_bram3_i;

	wire clkb_bram12_i;
	wire clkb_bram12_o;
	wire clkb_bram3_o;
	wire clkb_bram3_i;
			  
	wire [383:0] doutb_bram12_i;
	wire [383:0] doutb_bram12_o;
	wire [383:0] doutb_bram3_i;
	wire [383:0] doutb_bram3_o;
	wire wea_bram12_i,wea_bram12_o;
	
	wire empty_i,empty_o;
	wire full_i,full_o;
	wire rdy_i,rdy_o;
	wire vld_i,vld_o;
	

	wire [26:0] 									elem_struct;
	wire												enable_processing;
	wire  											video_ACK;
	wire 												ENABLE_INPUT;
	wire 												readBRAM1;
	

  assign rst_Chrontel_o=1'b1;
  assign video_ACK=1'b1,elem_struct=27'b100100100100100100100100100,enable_processing=1'b1,
  ENABLE_INPUT=1'b1,readBRAM1=1'b0;
  
	assign 	H_FP=10'd16,
				H_BP=10'd120,
				H_sync=10'd64,
				H_VldDat=10'd640,
				COLUMNS=10'd840,
				V_FP=10'd1,
				V_BP=10'd16,
				V_sync=10'd3,
				V_VldDat=10'd480,
				LINES=10'd500,
				H_active=0,
				V_active=0,
				HighCol=10'd640,
				LowCol=0,
				LowLine=0,
				HighLine=10'd480,
				Color=24'hFFFFFF;
				
  assign	  addrb_bram12_i	= (enable_processing)? addrb_bram12_o : addrb_bram3_o,
			  addrb_bram3_i	= (enable_processing)? addrb_bram3_o  : 7'd0,
		
			  clkb_bram12_i	= (enable_processing)? clkb_bram12_o  : clkb_bram3_o,
			  clkb_bram3_i		= (enable_processing)? clkb_bram3_o	  : 1'd0,
			  
			  doutb_bram12_i	= (enable_processing)? doutb_bram12_o : 384'd0,
			  doutb_bram3_i	= (enable_processing)? doutb_bram3_o  : doutb_bram12_o,
			  
			  full_i				= (enable_processing)? full_o			  : 1'b0,
			  empty_i			= (enable_processing)? empty_o		  : 1'b0,
			  vld_i				= (enable_processing)? vld_o			  : 1'b1,
			  rdy_i				= (enable_processing)? rdy_o			  : 1'b1,
			  vld_mem_i			= (enable_processing)? vld_mem_o		  : 1'b1; 
			  
  assign	  wea_bram12_i		= (readBRAM1)			? 1'b0 			  : wea_bram12_o,
			  vld_video_i		= (readBRAM1)			? 1'b1			  : vld_video_o;		  
			  
	
				  
	video_in_v3 INPUT_VID (
			.pixel_clk_i(ad_dataclk_i), 
			.rst_i(Bus2IP_Reset), 

			.hsync_i(ad_hsync_i), 
			.vsync_i(ad_vsync_i),
			.red_i(ad_red_i), 
			.green_i(ad_green_i), 
			.blue_i(ad_blue_i), 

			.clka_bram12_o(clka_bram12), 
			.wea_bram12_o(wea_bram12_o),
			.addra_bram12_o(addra_bram12), 
			.dina_bram12_o(dina_bram12), 

			.vld_o(vld_o),
			.rdy_i(rdy_i),
			.vld_video_o(vld_video_o), 
			.column_max_o(column_max), 
			.line_max_o(line_max),

			.video_ACK_i(video_ACK));	
		 
	blk_mem_gen5 input_buffer_BRAM( 
	 .clka(clka_bram12), 
	 .clkb(clkb_bram12_i), 
	 .wea(wea_bram12_i), 
	 .addra(addra_bram12), 
	 .addrb(addrb_bram12_i), 
	 .dina(dina_bram12), 
	 .doutb(doutb_bram12_o));
		 
	CPS_v3 processing_erosion (
		 .rst_i(Bus2IP_Reset), 
		 .clk_i(Bus2IP_Clk), 
		 .video_ACK_i(video_ACK),
		 .vld_mem_o(vld_mem_o),

		 .vld_i(vld_i),
		 .en_read_i(vld_video_i),
		 .rdy_o(rdy_o),

		 .clkb_bram12_o(clkb_bram12_o), 
		 .addrb_bram12_o(addrb_bram12_o), 
		 .doutb_bram12_i(doutb_bram12_i), 

		 .wea_bram3_o(wea_bram3), 
		 .clka_bram3_o(clka_bram3), 
		 .addra_bram3_o(addra_bram3), 
		 .dina_bram3_o(dina_bram3),

		 .empty_i(empty_i),
		 .full_o(full_o),
		 .element_struct(elem_struct));

	 	 	
	 blk_mem_gen5 output_buffer_BRAM (
		 .clka(clka_bram3), 
		 .clkb(clkb_bram3_i),
		 .wea(wea_bram3),  
		 .addra(addra_bram3), 
		 .addrb(addrb_bram3_i), 
		 .dina(dina_bram3), 
		 .doutb(doutb_bram3_o));	
	 
	 VIDEO_OUT3 OUTPUT_VID (
			.clk_i(Bus2IP_Clk),
			.rst_i(Bus2IP_Reset),

			.clkb_bram3_o(clkb_bram3_o),
			.doutb_bram3_i(doutb_bram3_i),
			.addrb_bram3_o(addrb_bram3_o),
			.full_i(full_i), 
			.empty_o(empty_o),

			.video_ACK_i(video_ACK), 
			.VLD_VIDEO_i(vld_video_i), 
			.vld_mem_i(vld_mem_i),
			.vga_d_o(dvi_d_o), 
			.vga_de_o(dvi_de_o), 
			.vga_hsync_o(dvi_hsync_o), 
			.vga_vsync_o(dvi_vsync_o), 
			.x_clk_p_o(x_clk_p_o), 
			.x_clk_n_o(x_clk_n_o), 

			.H_FP(H_FP), 
			.H_BP(H_BP), 
			.H_sync(H_sync), 
			.H_VldDat(H_VldDat), 
			.COLUMNS(COLUMNS), 
			.V_FP(V_FP), 
			.V_BP(V_BP), 
			.V_sync(V_sync), 
			.V_VldDat(V_VldDat), 
			.LINES(LINES), 
			.H_active(H_active), 
			.V_active(V_active), 
			.Color(Color), 
			.HighLine(HighLine), 
			.LowLine(LowLine), 
			.HighCol(HighCol), 
			.LowCol(LowCol),
			.VideoInputActive(ENABLE_INPUT));
			
endmodule
module symulation_main(

		rst_Chrontel_o,
		dvi_d_o,
		x_clk_p_o,
		x_clk_n_o,
		dvi_de_o,
		dvi_hsync_o,
		dvi_vsync_o,

		ad_dataclk_i,
		ad_hsync_i,
		ad_vsync_i,
		ad_red_i,
		ad_green_i,
		ad_blue_i,
		Bus2IP_Clk,
		Bus2IP_Reset,
		column_max,
		line_max
		);



	output  												rst_Chrontel_o;
	output  [0:11]										dvi_d_o;
	output  												x_clk_p_o;
	output  												x_clk_n_o;
	output  												dvi_de_o;
	output  												dvi_hsync_o;
	output  												dvi_vsync_o;

	input 												ad_dataclk_i;
	input 												ad_hsync_i;
	input 												ad_vsync_i;
	input [0:7] 										ad_red_i;
	input [0:7] 										ad_green_i;
	input [0:7] 										ad_blue_i;
	input                                     Bus2IP_Clk;
	input                                     Bus2IP_Reset;		
	
	output wire [10:0] column_max;
	output wire [10:0] line_max;
	


	wire [ 9:0 ] H_FP;
	wire [ 9:0 ] H_BP;
	wire [ 9:0 ] H_sync;
	wire [ 9:0 ] H_VldDat;
	wire [ 9:0 ] COLUMNS;
	wire [ 9:0 ] V_FP;
	wire [ 9:0 ] V_BP;
	wire [ 9:0 ] V_sync;
	wire [ 9:0 ] V_VldDat;
	wire [ 9:0 ] LINES;
	wire H_active;
	wire V_active;
	wire [9:0] HighCol;
	wire [9:0] LowCol;
	wire [9:0] LowLine;
	wire [9:0] HighLine;
	wire [23:0] Color;


	wire 												vld_video_i,vld_video_o;
	wire 												vld_mem_i,vld_mem_o;
	wire 												rdy,vld;
	

	wire clka_bram12,clka_bram3;
	
	wire wea_bram3;
	wire [6:0] addra_bram3,addra_bram12;
	wire [383:0] dina_bram3,dina_bram12;
	
	wire [6:0] addrb_bram12_i;
	wire [6:0] addrb_bram12_o;
	wire [6:0] addrb_bram3_o;
	wire [6:0] addrb_bram3_i;

	wire clkb_bram12_i;
	wire clkb_bram12_o;
	wire clkb_bram3_o;
	wire clkb_bram3_i;
			  
	wire [383:0] doutb_bram12_i;
	wire [383:0] doutb_bram12_o;
	wire [383:0] doutb_bram3_i;
	wire [383:0] doutb_bram3_o;
	wire wea_bram12_i,wea_bram12_o;
	
	wire empty_i,empty_o;
	wire full_i,full_o;
	wire rdy_i,rdy_o;
	wire vld_i,vld_o;
	

	wire [26:0] 									elem_struct;
	wire												enable_processing;
	wire  											video_ACK;
	wire 												ENABLE_INPUT;
	wire 												readBRAM1;
	

  assign rst_Chrontel_o=1'b1;
  assign video_ACK=1'b1,elem_struct=27'b100100100100100100100100100,enable_processing=1'b1,
  ENABLE_INPUT=1'b1,readBRAM1=1'b0;
  
	assign 	H_FP=10'd16,
				H_BP=10'd120,
				H_sync=10'd64,
				H_VldDat=10'd640,
				COLUMNS=10'd840,
				V_FP=10'd1,
				V_BP=10'd16,
				V_sync=10'd3,
				V_VldDat=10'd480,
				LINES=10'd500,
				H_active=0,
				V_active=0,
				HighCol=10'd640,
				LowCol=0,
				LowLine=0,
				HighLine=10'd480,
				Color=24'hFFFFFF;
				
  assign	  addrb_bram12_i	= (enable_processing)? addrb_bram12_o : addrb_bram3_o,
			  addrb_bram3_i	= (enable_processing)? addrb_bram3_o  : 7'd0,
		
			  clkb_bram12_i	= (enable_processing)? clkb_bram12_o  : clkb_bram3_o,
			  clkb_bram3_i		= (enable_processing)? clkb_bram3_o	  : 1'd0,
			  
			  doutb_bram12_i	= (enable_processing)? doutb_bram12_o : 384'd0,
			  doutb_bram3_i	= (enable_processing)? doutb_bram3_o  : doutb_bram12_o,
			  
			  full_i				= (enable_processing)? full_o			  : 1'b0,
			  empty_i			= (enable_processing)? empty_o		  : 1'b0,
			  vld_i				= (enable_processing)? vld_o			  : 1'b1,
			  rdy_i				= (enable_processing)? rdy_o			  : 1'b1,
			  vld_mem_i			= (enable_processing)? vld_mem_o		  : 1'b1; 
			  
  assign	  wea_bram12_i		= (readBRAM1)			? 1'b0 			  : wea_bram12_o,
			  vld_video_i		= (readBRAM1)			? 1'b1			  : vld_video_o;		  
			  
	
				  
	video_in_v3 INPUT_VID (
			.pixel_clk_i(ad_dataclk_i), 
			.rst_i(Bus2IP_Reset), 

			.hsync_i(ad_hsync_i), 
			.vsync_i(ad_vsync_i),
			.red_i(ad_red_i), 
			.green_i(ad_green_i), 
			.blue_i(ad_blue_i), 

			.clka_bram12_o(clka_bram12), 
			.wea_bram12_o(wea_bram12_o),
			.addra_bram12_o(addra_bram12), 
			.dina_bram12_o(dina_bram12), 

			.vld_o(vld_o),
			.rdy_i(rdy_i),
			.vld_video_o(vld_video_o), 
			.column_max_o(column_max), 
			.line_max_o(line_max),

			.video_ACK_i(video_ACK));	
		 
	blk_mem_gen5 input_buffer_BRAM( 
	 .clka(clka_bram12), 
	 .clkb(clkb_bram12_i), 
	 .wea(wea_bram12_i), 
	 .addra(addra_bram12), 
	 .addrb(addrb_bram12_i), 
	 .dina(dina_bram12), 
	 .doutb(doutb_bram12_o));
		 
	CPS_v3 processing_erosion (
		 .rst_i(Bus2IP_Reset), 
		 .clk_i(Bus2IP_Clk), 
		 .video_ACK_i(video_ACK),
		 .vld_mem_o(vld_mem_o),

		 .vld_i(vld_i),
		 .en_read_i(vld_video_i),
		 .rdy_o(rdy_o),

		 .clkb_bram12_o(clkb_bram12_o), 
		 .addrb_bram12_o(addrb_bram12_o), 
		 .doutb_bram12_i(doutb_bram12_i), 

		 .wea_bram3_o(wea_bram3), 
		 .clka_bram3_o(clka_bram3), 
		 .addra_bram3_o(addra_bram3), 
		 .dina_bram3_o(dina_bram3),

		 .empty_i(empty_i),
		 .full_o(full_o),
		 .element_struct(elem_struct));

	 	 	
	 blk_mem_gen5 output_buffer_BRAM (
		 .clka(clka_bram3), 
		 .clkb(clkb_bram3_i),
		 .wea(wea_bram3),  
		 .addra(addra_bram3), 
		 .addrb(addrb_bram3_i), 
		 .dina(dina_bram3), 
		 .doutb(doutb_bram3_o));	
	 
	 VIDEO_OUT3 OUTPUT_VID (
			.clk_i(Bus2IP_Clk),
			.rst_i(Bus2IP_Reset),

			.clkb_bram3_o(clkb_bram3_o),
			.doutb_bram3_i(doutb_bram3_i),
			.addrb_bram3_o(addrb_bram3_o),
			.full_i(full_i), 
			.empty_o(empty_o),

			.video_ACK_i(video_ACK), 
			.VLD_VIDEO_i(vld_video_i), 
			.vld_mem_i(vld_mem_i),
			.vga_d_o(dvi_d_o), 
			.vga_de_o(dvi_de_o), 
			.vga_hsync_o(dvi_hsync_o), 
			.vga_vsync_o(dvi_vsync_o), 
			.x_clk_p_o(x_clk_p_o), 
			.x_clk_n_o(x_clk_n_o), 

			.H_FP(H_FP), 
			.H_BP(H_BP), 
			.H_sync(H_sync), 
			.H_VldDat(H_VldDat), 
			.COLUMNS(COLUMNS), 
			.V_FP(V_FP), 
			.V_BP(V_BP), 
			.V_sync(V_sync), 
			.V_VldDat(V_VldDat), 
			.LINES(LINES), 
			.H_active(H_active), 
			.V_active(V_active), 
			.Color(Color), 
			.HighLine(HighLine), 
			.LowLine(LowLine), 
			.HighCol(HighCol), 
			.LowCol(LowCol),
			.VideoInputActive(ENABLE_INPUT));
			
endmodule