data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/RGB565_YUV422.v
1: b'%Warning-WIDTH: data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/RGB565_YUV422.v:103: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 17 bits.\n                                                                                                                       : ... In instance RGB565_YUV422\n   YUV422_Y <= (YUV422_Y_reg>>>8) + 16;  \n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/RGB565_YUV422.v:106: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 17 bits.\n                                                                                                                       : ... In instance RGB565_YUV422\n    YUV422_Cb <= (YUV422_Cb_reg>>>8) + 128;  \n              ^~\n%Warning-WIDTH: data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/RGB565_YUV422.v:107: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 17 bits.\n                                                                                                                       : ... In instance RGB565_YUV422\n    YUV422_Cr <= (YUV422_Cr_reg>>>8) + 128;  \n              ^~\n%Warning-WIDTH: data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/RGB565_YUV422.v:113: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 9 bits.\n                                                                                                                       : ... In instance RGB565_YUV422\n wire [7:0] YUV422_Y_valid = (YUV422_Y<16)? 16 : (YUV422_Y>235)? 235 : YUV422_Y;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/RGB565_YUV422.v:114: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 9 bits.\n                                                                                                                       : ... In instance RGB565_YUV422\n wire [7:0] YUV422_Cb_valid = (YUV422_Cb<16)? 16 : (YUV422_Cb>240)? 240 : YUV422_Cb;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/RGB565_YUV422.v:115: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 9 bits.\n                                                                                                                       : ... In instance RGB565_YUV422\n wire [7:0] YUV422_Cr_valid = (YUV422_Cr<16)? 16 : (YUV422_Cr>240)? 240 : YUV422_Cr;\n                            ^\n%Error: Exiting due to 6 warning(s)\n'
module RGB565_YUV422
(

	input	wire			sys_clk, sys_rst_n,
	input	wire	[7:2]	KEY_safe,

	input	wire			RGB565_PCLK,
	input	wire			RGB565_HSYNC,
	input	wire			RGB565_VSYNC,
	input	wire	[15:0]	RGB565_D,
	input	wire			RGB565_DE,
	output	wire			YUV422_PCLK,
	output	reg		[15:0]	YUV422_D,
	output	reg				YUV422_DE,
	output	reg				YUV422_HSYNC,
	output	reg				YUV422_VSYNC
);


	reg		[15:0]	HSYNC;
	reg		[15:0]	VSYNC;
	reg		[15:0]	DE;
	always @(posedge RGB565_PCLK)
	begin
		HSYNC <= {HSYNC[14:0], RGB565_HSYNC};
		VSYNC <= {VSYNC[14:0], RGB565_VSYNC};
		DE <= {DE[14:0], RGB565_DE};
	end

	assign			YUV422_PCLK = RGB565_PCLK;


	reg		[10:0]	pix_cnt;
	reg		[7:0]	RGB888_R;
	reg		[7:0]	RGB888_G;
	reg		[7:0]	RGB888_B;
	always @(posedge RGB565_PCLK)
	begin
		if(RGB565_DE)
		begin
			RGB888_R <= {RGB565_D[15:11], 3'B000};
			RGB888_G <= {RGB565_D[10:5], 2'B00};
			RGB888_B <= {RGB565_D[4:0], 3'B000};
		end
	end

	reg		[16:0]	YUV422_Y_reg;
	reg		[16:0]	YUV422_Cb_reg;
	reg		[16:0]	YUV422_Cr_reg;



	reg		[16:0]	RGB888_R_66;
	reg		[16:0]	RGB888_R_38;
	reg		[16:0]	RGB888_R_112;
	reg		[16:0]	RGB888_G_129;
	reg		[16:0]	RGB888_G_74;
	reg		[16:0]	RGB888_G_94;
	reg		[16:0]	RGB888_B_25;
	reg		[16:0]	RGB888_B_112;
	reg		[16:0]	RGB888_B_18;
	always @(posedge YUV422_PCLK)
	begin
		RGB888_R_66 <= 9'D66*RGB888_R;
		RGB888_R_38 <= 9'D38*RGB888_R;
		RGB888_R_112 <= 9'D112*RGB888_R;
		RGB888_G_129 <= 9'D129*RGB888_G;
		RGB888_G_74 <= 9'D74*RGB888_G;
		RGB888_G_94 <= 9'D94*RGB888_G;
		RGB888_B_25 <= 9'D25*RGB888_B;
		RGB888_B_112 <= 9'D112*RGB888_B;
		RGB888_B_18 <= 9'D18*RGB888_B;
		
		YUV422_Y_reg <= RGB888_R_66 + RGB888_G_129 + RGB888_B_25;
		YUV422_Cb_reg <= - RGB888_R_38 - RGB888_G_74 + RGB888_B_112;
		YUV422_Cr_reg <= RGB888_R_112 - RGB888_G_94 - RGB888_B_18;
	end

	reg		[8:0]	YUV422_Y;
	reg		[8:0]	YUV422_Cb;
	reg		[8:0]	YUV422_Cr;
	always @(posedge YUV422_PCLK)
		if(!HSYNC[3])
			pix_cnt <= 0;
		else if(DE[3])
		begin
			YUV422_Y <= (YUV422_Y_reg>>>8) + 16;
			if(!pix_cnt[0])
			begin
				YUV422_Cb <= (YUV422_Cb_reg>>>8) + 128;
				YUV422_Cr <= (YUV422_Cr_reg>>>8) + 128;
			end
			
			pix_cnt <= pix_cnt + 1;
		end
	
	wire	[7:0]	YUV422_Y_valid = (YUV422_Y<16)? 16 : (YUV422_Y>235)? 235 : YUV422_Y;
	wire	[7:0]	YUV422_Cb_valid = (YUV422_Cb<16)? 16 : (YUV422_Cb>240)? 240 : YUV422_Cb;
	wire	[7:0]	YUV422_Cr_valid = (YUV422_Cr<16)? 16 : (YUV422_Cr>240)? 240 : YUV422_Cr;
	
	always @(posedge YUV422_PCLK)
	begin
		if(pix_cnt[0])
			YUV422_D <= {YUV422_Cb_valid, YUV422_Y_valid};
		else
			YUV422_D <= {YUV422_Cr_valid, YUV422_Y_valid};

		YUV422_DE <= DE[4];
		YUV422_HSYNC <= HSYNC[4];
		YUV422_VSYNC <= VSYNC[4];
	end	

	
endmodule
module RGB565_YUV422
(

	input	wire			sys_clk, sys_rst_n,
	input	wire	[7:2]	KEY_safe,

	input	wire			RGB565_PCLK,
	input	wire			RGB565_HSYNC,
	input	wire			RGB565_VSYNC,
	input	wire	[15:0]	RGB565_D,
	input	wire			RGB565_DE,
	output	wire			YUV422_PCLK,
	output	reg		[15:0]	YUV422_D,
	output	reg				YUV422_DE,
	output	reg				YUV422_HSYNC,
	output	reg				YUV422_VSYNC
);



	reg		[15:0]	HSYNC;
	reg		[15:0]	VSYNC;
	reg		[15:0]	DE;
	always @(posedge RGB565_PCLK)
	begin
		HSYNC <= {HSYNC[14:0], RGB565_HSYNC};
		VSYNC <= {VSYNC[14:0], RGB565_VSYNC};
		DE <= {DE[14:0], RGB565_DE};
	end

	assign			YUV422_PCLK = RGB565_PCLK;


	reg		[10:0]	pix_cnt;
	reg		[7:0]	RGB888_R;
	reg		[7:0]	RGB888_G;
	reg		[7:0]	RGB888_B;
	always @(posedge RGB565_PCLK)
	begin
		if(RGB565_DE)
		begin
			RGB888_R <= {RGB565_D[15:11], 3'B000};
			RGB888_G <= {RGB565_D[10:5], 2'B00};
			RGB888_B <= {RGB565_D[4:0], 3'B000};
		end
	end

	reg		[16:0]	YUV422_Y_reg;
	reg		[16:0]	YUV422_Cb_reg;
	reg		[16:0]	YUV422_Cr_reg;



	reg		[16:0]	RGB888_R_66;
	reg		[16:0]	RGB888_R_38;
	reg		[16:0]	RGB888_R_112;
	reg		[16:0]	RGB888_G_129;
	reg		[16:0]	RGB888_G_74;
	reg		[16:0]	RGB888_G_94;
	reg		[16:0]	RGB888_B_25;
	reg		[16:0]	RGB888_B_112;
	reg		[16:0]	RGB888_B_18;
	always @(posedge YUV422_PCLK)
	begin
		RGB888_R_66 <= 9'D66*RGB888_R;
		RGB888_R_38 <= 9'D38*RGB888_R;
		RGB888_R_112 <= 9'D112*RGB888_R;
		RGB888_G_129 <= 9'D129*RGB888_G;
		RGB888_G_74 <= 9'D74*RGB888_G;
		RGB888_G_94 <= 9'D94*RGB888_G;
		RGB888_B_25 <= 9'D25*RGB888_B;
		RGB888_B_112 <= 9'D112*RGB888_B;
		RGB888_B_18 <= 9'D18*RGB888_B;
		
		YUV422_Y_reg <= RGB888_R_66 + RGB888_G_129 + RGB888_B_25;
		YUV422_Cb_reg <= - RGB888_R_38 - RGB888_G_74 + RGB888_B_112;
		YUV422_Cr_reg <= RGB888_R_112 - RGB888_G_94 - RGB888_B_18;
	end

	reg		[8:0]	YUV422_Y;
	reg		[8:0]	YUV422_Cb;
	reg		[8:0]	YUV422_Cr;
	always @(posedge YUV422_PCLK)
		if(!HSYNC[3])
			pix_cnt <= 0;
		else if(DE[3])
		begin
			YUV422_Y <= (YUV422_Y_reg>>>8) + 16;
			if(!pix_cnt[0])
			begin
				YUV422_Cb <= (YUV422_Cb_reg>>>8) + 128;
				YUV422_Cr <= (YUV422_Cr_reg>>>8) + 128;
			end
			
			pix_cnt <= pix_cnt + 1;
		end
	
	wire	[7:0]	YUV422_Y_valid = (YUV422_Y<16)? 16 : (YUV422_Y>235)? 235 : YUV422_Y;
	wire	[7:0]	YUV422_Cb_valid = (YUV422_Cb<16)? 16 : (YUV422_Cb>240)? 240 : YUV422_Cb;
	wire	[7:0]	YUV422_Cr_valid = (YUV422_Cr<16)? 16 : (YUV422_Cr>240)? 240 : YUV422_Cr;
	
	always @(posedge YUV422_PCLK)
	begin
		if(pix_cnt[0])
			YUV422_D <= {YUV422_Cb_valid, YUV422_Y_valid};
		else
			YUV422_D <= {YUV422_Cr_valid, YUV422_Y_valid};

		YUV422_DE <= DE[4];
		YUV422_HSYNC <= HSYNC[4];
		YUV422_VSYNC <= VSYNC[4];
	end	

	
endmodule