data/full_repos/permissive/104305228/code/tb.v
 line:157: before: "$"
1: b'%Error: data/full_repos/permissive/104305228/code/tb.v:2: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/104305228/code/tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 CLOCK_50 = ~CLOCK_50;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104305228/code/tb.v:14: Define or directive not defined: \'`RstEnable\'\n  rst = `RstEnable;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/tb.v:14: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  rst = `RstEnable;\n                  ^\n%Error: data/full_repos/permissive/104305228/code/tb.v:15: Define or directive not defined: \'`RstDisable\'\n  #195 rst = `RstDisable;\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/tb.v:15: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  #195 rst = `RstDisable;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/104305228/code/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #195 rst = `RstDisable;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104305228/code/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #1000 $stop;\n  ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n'
module tb();

	reg CLOCK_50;
	reg rst;

	initial begin
		CLOCK_50 = 1'b0;
		forever #10 CLOCK_50 = ~CLOCK_50;
	end

	initial begin
		rst = `RstEnable;
		#195 rst = `RstDisable;
		#1000 $stop;
	end

	sopc sopc(
		.clk(CLOCK_50), .rst(rst)
	);
endmodule
module tb();


	reg CLOCK_50;
	reg rst;

	initial begin
		CLOCK_50 = 1'b0;
		forever #10 CLOCK_50 = ~CLOCK_50;
	end

	initial begin
		rst = `RstEnable;
		#195 rst = `RstDisable;
		#1000 $stop;
	end

	sopc sopc(
		.clk(CLOCK_50), .rst(rst)
	);
endmodule