data/full_repos/permissive/1191536/older_tb/alu_tb.v
 line:25: before: "#"
1: b'%Error: data/full_repos/permissive/1191536/older_tb/alu_tb.v:12: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #5 aluOp = 3\'b000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #5 aluOp = 3\'b001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #5 aluOp = 3\'b010;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #5 aluOp = 3\'b011;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #5 aluOp = 3\'b100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #5 aluOp = 3\'b101;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #5 aluOp = 3\'b110;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #5 address = \'d1023; collapse = |address[15:10];\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #5 address = \'d1024; collapse = |address[15:10];\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #5 address = \'d5000; collapse = |address[15:10];\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #5 address = \'d500; collapse = |address[15:10];\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/1191536/older_tb/alu_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vcpu_alu_tb;
	reg [2:0] aluOp;
	reg [7:0] aluA;
	reg [7:0] aluB;
	wire [7:0] aluC;
	wire aluEq;

	reg [15:0] address;
	reg collapse;

	initial begin
		$dumpvars;
		aluA = 'd23;
		aluB = 'd44;
		
		#5 aluOp = 3'b000;
		#5 aluOp = 3'b001;
		#5 aluOp = 3'b010;
		#5 aluOp = 3'b011;
		#5 aluOp = 3'b100;
		#5 aluOp = 3'b101;
		#5 aluOp = 3'b110;
		
		#5
		#5 address = 'd1023; collapse = |address[15:10];
		#5 address = 'd1024; collapse = |address[15:10];
		#5 address = 'd5000; collapse = |address[15:10];
		#5 address = 'd500; collapse = |address[15:10];
		#10 $finish;
	end

	vcpu_alu alu(.op(aluOp), .a(aluA), .b(aluB), .c(aluC), .flag_eq(aluEq));
endmodule
module vcpu_alu_tb;

	reg [2:0] aluOp;
	reg [7:0] aluA;
	reg [7:0] aluB;
	wire [7:0] aluC;
	wire aluEq;

	reg [15:0] address;
	reg collapse;

	initial begin
		$dumpvars;
		aluA = 'd23;
		aluB = 'd44;
		
		#5 aluOp = 3'b000;
		#5 aluOp = 3'b001;
		#5 aluOp = 3'b010;
		#5 aluOp = 3'b011;
		#5 aluOp = 3'b100;
		#5 aluOp = 3'b101;
		#5 aluOp = 3'b110;
		
		#5
		#5 address = 'd1023; collapse = |address[15:10];
		#5 address = 'd1024; collapse = |address[15:10];
		#5 address = 'd5000; collapse = |address[15:10];
		#5 address = 'd500; collapse = |address[15:10];
		#10 $finish;
	end

	vcpu_alu alu(.op(aluOp), .a(aluA), .b(aluB), .c(aluC), .flag_eq(aluEq));
endmodule