data/full_repos/permissive/173150157/rtl/demo/display_demo_dvi.v
1: b'%Error: data/full_repos/permissive/173150157/rtl/demo/display_demo_dvi.v:35: Cannot find file containing module: \'display_clocks\'\n    display_clocks #(                \n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173150157/rtl/demo,data/full_repos/permissive/173150157/display_clocks\n             data/full_repos/permissive/173150157/rtl/demo,data/full_repos/permissive/173150157/display_clocks.v\n             data/full_repos/permissive/173150157/rtl/demo,data/full_repos/permissive/173150157/display_clocks.sv\n             display_clocks\n             display_clocks.v\n             display_clocks.sv\n             obj_dir/display_clocks\n             obj_dir/display_clocks.v\n             obj_dir/display_clocks.sv\n%Error: data/full_repos/permissive/173150157/rtl/demo/display_demo_dvi.v:59: Cannot find file containing module: \'display_timings\'\n    display_timings #(               \n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173150157/rtl/demo/display_demo_dvi.v:88: Cannot find file containing module: \'test_card_simple\'\n    test_card_simple #(\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173150157/rtl/demo/display_demo_dvi.v:122: Cannot find file containing module: \'dvi_generator\'\n    dvi_generator dvi_out (\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173150157/rtl/demo/display_demo_dvi.v:140: Cannot find file containing module: \'OBUFDS\'\n    OBUFDS #(.IOSTANDARD("TMDS_33"))\n    ^~~~~~\n%Error: data/full_repos/permissive/173150157/rtl/demo/display_demo_dvi.v:142: Cannot find file containing module: \'OBUFDS\'\n    OBUFDS #(.IOSTANDARD("TMDS_33"))\n    ^~~~~~\n%Error: data/full_repos/permissive/173150157/rtl/demo/display_demo_dvi.v:144: Cannot find file containing module: \'OBUFDS\'\n    OBUFDS #(.IOSTANDARD("TMDS_33"))\n    ^~~~~~\n%Error: data/full_repos/permissive/173150157/rtl/demo/display_demo_dvi.v:146: Cannot find file containing module: \'OBUFDS\'\n    OBUFDS #(.IOSTANDARD("TMDS_33"))\n    ^~~~~~\n%Error: Exiting due to 8 error(s)\n'
module display_demo_dvi(
    input  wire CLK,
    input  wire RST_BTN,
    inout  wire hdmi_tx_cec,
    input  wire hdmi_tx_hpd,
    inout  wire hdmi_tx_rscl,
    inout  wire hdmi_tx_rsda,
    output wire hdmi_tx_clk_n,
    output wire hdmi_tx_clk_p,
    output wire [2:0] hdmi_tx_n,
    output wire [2:0] hdmi_tx_p
    );


    wire pix_clk;
    wire pix_clk_5x;
    wire clk_lock;

    display_clocks #(
        .MULT_MASTER(37.125),
        .DIV_MASTER(5),
        .DIV_5X(2.0),
        .DIV_1X(10),
        .IN_PERIOD(10.0)
    )
    display_clocks_inst
    (
       .i_clk(CLK),
       .i_rst(~RST_BTN),
       .o_clk_1x(pix_clk),
       .o_clk_5x(pix_clk_5x),
       .o_locked(clk_lock)
    );


    wire signed [15:0] sx;
    wire signed [15:0] sy;
    wire h_sync;
    wire v_sync;
    wire de;
    wire frame;

    display_timings #(
        .H_RES(1280),
        .V_RES(720),
        .H_FP(110),
        .H_SYNC(40),
        .H_BP(220),
        .V_FP(5),
        .V_SYNC(5),
        .V_BP(20),
        .H_POL(1),
        .V_POL(1)
    )
    display_timings_inst (
        .i_pix_clk(pix_clk),
        .i_rst(!clk_lock),
        .o_hs(h_sync),
        .o_vs(v_sync),
        .o_de(de),
        .o_frame(frame),
        .o_sx(sx),
        .o_sy(sy)
    );


    wire [7:0] red;
    wire [7:0] green;
    wire [7:0] blue;


    test_card_simple #(
        .H_RES(1280)
    ) test_card_inst (
        .i_x(sx),
        .o_red(red),
        .o_green(green),
        .o_blue(blue)
    );

























    wire tmds_ch0_serial, tmds_ch1_serial, tmds_ch2_serial, tmds_chc_serial;
    dvi_generator dvi_out (
        .i_pix_clk(pix_clk),
        .i_pix_clk_5x(pix_clk_5x),
        .i_rst(!clk_lock),
        .i_de(de),
        .i_data_ch0(blue),
        .i_data_ch1(green),
        .i_data_ch2(red),
        .i_ctrl_ch0({v_sync, h_sync}),
        .i_ctrl_ch1(2'b00),
        .i_ctrl_ch2(2'b00),
        .o_tmds_ch0_serial(tmds_ch0_serial),
        .o_tmds_ch1_serial(tmds_ch1_serial),
        .o_tmds_ch2_serial(tmds_ch2_serial),
        .o_tmds_chc_serial(tmds_chc_serial)
    );


    OBUFDS #(.IOSTANDARD("TMDS_33"))
        tmds_buf_ch0 (.I(tmds_ch0_serial), .O(hdmi_tx_p[0]), .OB(hdmi_tx_n[0]));
    OBUFDS #(.IOSTANDARD("TMDS_33"))
        tmds_buf_ch1 (.I(tmds_ch1_serial), .O(hdmi_tx_p[1]), .OB(hdmi_tx_n[1]));
    OBUFDS #(.IOSTANDARD("TMDS_33"))
        tmds_buf_ch2 (.I(tmds_ch2_serial), .O(hdmi_tx_p[2]), .OB(hdmi_tx_n[2]));
    OBUFDS #(.IOSTANDARD("TMDS_33"))
        tmds_buf_chc (.I(tmds_chc_serial), .O(hdmi_tx_clk_p), .OB(hdmi_tx_clk_n));

    assign hdmi_tx_cec   = 1'bz;
    assign hdmi_tx_rsda  = 1'bz;
    assign hdmi_tx_rscl  = 1'b1;
endmodule
module display_demo_dvi(
    input  wire CLK,
    input  wire RST_BTN,
    inout  wire hdmi_tx_cec,
    input  wire hdmi_tx_hpd,
    inout  wire hdmi_tx_rscl,
    inout  wire hdmi_tx_rsda,
    output wire hdmi_tx_clk_n,
    output wire hdmi_tx_clk_p,
    output wire [2:0] hdmi_tx_n,
    output wire [2:0] hdmi_tx_p
    );



    wire pix_clk;
    wire pix_clk_5x;
    wire clk_lock;

    display_clocks #(
        .MULT_MASTER(37.125),
        .DIV_MASTER(5),
        .DIV_5X(2.0),
        .DIV_1X(10),
        .IN_PERIOD(10.0)
    )
    display_clocks_inst
    (
       .i_clk(CLK),
       .i_rst(~RST_BTN),
       .o_clk_1x(pix_clk),
       .o_clk_5x(pix_clk_5x),
       .o_locked(clk_lock)
    );


    wire signed [15:0] sx;
    wire signed [15:0] sy;
    wire h_sync;
    wire v_sync;
    wire de;
    wire frame;

    display_timings #(
        .H_RES(1280),
        .V_RES(720),
        .H_FP(110),
        .H_SYNC(40),
        .H_BP(220),
        .V_FP(5),
        .V_SYNC(5),
        .V_BP(20),
        .H_POL(1),
        .V_POL(1)
    )
    display_timings_inst (
        .i_pix_clk(pix_clk),
        .i_rst(!clk_lock),
        .o_hs(h_sync),
        .o_vs(v_sync),
        .o_de(de),
        .o_frame(frame),
        .o_sx(sx),
        .o_sy(sy)
    );


    wire [7:0] red;
    wire [7:0] green;
    wire [7:0] blue;


    test_card_simple #(
        .H_RES(1280)
    ) test_card_inst (
        .i_x(sx),
        .o_red(red),
        .o_green(green),
        .o_blue(blue)
    );

























    wire tmds_ch0_serial, tmds_ch1_serial, tmds_ch2_serial, tmds_chc_serial;
    dvi_generator dvi_out (
        .i_pix_clk(pix_clk),
        .i_pix_clk_5x(pix_clk_5x),
        .i_rst(!clk_lock),
        .i_de(de),
        .i_data_ch0(blue),
        .i_data_ch1(green),
        .i_data_ch2(red),
        .i_ctrl_ch0({v_sync, h_sync}),
        .i_ctrl_ch1(2'b00),
        .i_ctrl_ch2(2'b00),
        .o_tmds_ch0_serial(tmds_ch0_serial),
        .o_tmds_ch1_serial(tmds_ch1_serial),
        .o_tmds_ch2_serial(tmds_ch2_serial),
        .o_tmds_chc_serial(tmds_chc_serial)
    );


    OBUFDS #(.IOSTANDARD("TMDS_33"))
        tmds_buf_ch0 (.I(tmds_ch0_serial), .O(hdmi_tx_p[0]), .OB(hdmi_tx_n[0]));
    OBUFDS #(.IOSTANDARD("TMDS_33"))
        tmds_buf_ch1 (.I(tmds_ch1_serial), .O(hdmi_tx_p[1]), .OB(hdmi_tx_n[1]));
    OBUFDS #(.IOSTANDARD("TMDS_33"))
        tmds_buf_ch2 (.I(tmds_ch2_serial), .O(hdmi_tx_p[2]), .OB(hdmi_tx_n[2]));
    OBUFDS #(.IOSTANDARD("TMDS_33"))
        tmds_buf_chc (.I(tmds_chc_serial), .O(hdmi_tx_clk_p), .OB(hdmi_tx_clk_n));

    assign hdmi_tx_cec   = 1'bz;
    assign hdmi_tx_rsda  = 1'bz;
    assign hdmi_tx_rscl  = 1'b1;
endmodule