data/full_repos/permissive/120043621/tests/tb_mandelbrot.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/120043621/tests/tb_mandelbrot.sv:28: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120043621/tests/tb_mandelbrot.sv:35: Unsupported: Ignoring delay on this delayed statement.\n        #1 rst = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/120043621/tests/tb_mandelbrot.sv:36: Unsupported: Ignoring delay on this delayed statement.\n        #1 start = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/120043621/tests/tb_mandelbrot.sv:39: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Error: data/full_repos/permissive/120043621/tests/tb_mandelbrot.sv:17: Cannot find file containing module: \'mandelbrot\'\n    mandelbrot MB(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120043621/tests,data/full_repos/permissive/120043621/mandelbrot\n             data/full_repos/permissive/120043621/tests,data/full_repos/permissive/120043621/mandelbrot.v\n             data/full_repos/permissive/120043621/tests,data/full_repos/permissive/120043621/mandelbrot.sv\n             mandelbrot\n             mandelbrot.v\n             mandelbrot.sv\n             obj_dir/mandelbrot\n             obj_dir/mandelbrot.v\n             obj_dir/mandelbrot.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mandelbrot();
    reg clk, rst, start;
    reg done;

    `ifdef HIGH_RES
    reg [8:0] vga_x;
    reg [7:0] vga_y;
    `else
    reg [7:0] vga_x;
    reg [6:0] vga_y;
    `endif
    reg [2:0] vga_colour;
    reg vga_plot;

    mandelbrot MB(
        .clk(clk),
        .rstn(rst),
        .start(start),
        .done(done),
        .vga_x(vga_x),
        .vga_y(vga_y),
        .vga_colour(vga_colour),
        .vga_plot(vga_plot)
    );

    always #1 clk = ~clk;

    initial begin
        clk = 1'b0;
        rst = 1'b0;
        start = 1'b0;

        #1 rst = 1'b1;
        #1 start = 1'b1;

        if (done == 1) begin
            #20;
            $stop;
        end
    end
endmodule
module tb_mandelbrot();

    reg clk, rst, start;
    reg done;

    `ifdef HIGH_RES
    reg [8:0] vga_x;
    reg [7:0] vga_y;
    `else
    reg [7:0] vga_x;
    reg [6:0] vga_y;
    `endif
    reg [2:0] vga_colour;
    reg vga_plot;

    mandelbrot MB(
        .clk(clk),
        .rstn(rst),
        .start(start),
        .done(done),
        .vga_x(vga_x),
        .vga_y(vga_y),
        .vga_colour(vga_colour),
        .vga_plot(vga_plot)
    );

    always #1 clk = ~clk;

    initial begin
        clk = 1'b0;
        rst = 1'b0;
        start = 1'b0;

        #1 rst = 1'b1;
        #1 start = 1'b1;

        if (done == 1) begin
            #20;
            $stop;
        end
    end
endmodule