data/full_repos/permissive/138713719/hdl/sram_test.v
1: b"%Error: data/full_repos/permissive/138713719/hdl/sram_test.v:69: Cannot find file containing module: 'data_bus_test'\n    data_bus_test data_bus_test_unit\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138713719/hdl,data/full_repos/permissive/138713719/data_bus_test\n             data/full_repos/permissive/138713719/hdl,data/full_repos/permissive/138713719/data_bus_test.v\n             data/full_repos/permissive/138713719/hdl,data/full_repos/permissive/138713719/data_bus_test.sv\n             data_bus_test\n             data_bus_test.v\n             data_bus_test.sv\n             obj_dir/data_bus_test\n             obj_dir/data_bus_test.v\n             obj_dir/data_bus_test.sv\n%Error: data/full_repos/permissive/138713719/hdl/sram_test.v:84: Cannot find file containing module: 'addr_bus_test'\n    addr_bus_test addr_bus_test_unit\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/138713719/hdl/sram_test.v:99: Cannot find file containing module: 'device_test'\n    device_test device_test_unit\n    ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module sram_test
    (
    input wire clk,
    input wire rst,
    
    output wire mem,
    output wire rw,
    input wire ready,
    
    output wire [19:0] addr,
    output wire [7:0] data2ram,
    input wire [7:0] data2fpga,
    
    output wire done,
    output wire [2:0] result
    );
    
    

    

    wire dbus_mem, abus_mem, dev_mem;
    wire dbus_rw, abus_rw, dev_rw;
    wire [19:0] dbus_addr, abus_addr, dev_addr;
    wire [7:0] dbus_data2ram, abus_data2ram, dev_data2ram;
    

    wire abus_en, dev_en;
    wire dbus_done, abus_done, dev_done;
    wire dbus_result, abus_result, dev_result;
    
    

    
    assign abus_en = dbus_done & dbus_result;
    assign dev_en = abus_done & abus_result;
    
    

    
    data_bus_test data_bus_test_unit
        (
        .clk(clk),
        .rst(rst),
        .en(1'b1),
        .mem(dbus_mem),
        .rw(dbus_rw),
        .ready(ready),
        .addr(dbus_addr),
        .data2ram(dbus_data2ram),
        .data2fpga(data2fpga),
        .done(dbus_done),
        .result(dbus_result)
        );
    
    addr_bus_test addr_bus_test_unit
        (
        .clk(clk),
        .rst(rst),
        .en(abus_en),
        .mem(abus_mem),
        .rw(abus_rw),
        .ready(ready),
        .addr(abus_addr),
        .data2ram(abus_data2ram),
        .data2fpga(data2fpga),
        .done(abus_done),
        .result(abus_result)
        );
    
    device_test device_test_unit
        (
        .clk(clk),
        .rst(rst),
        .en(dev_en),
        .mem(dev_mem),
        .rw(dev_rw),
        .ready(ready),
        .addr(dev_addr),
        .data2ram(dev_data2ram),
        .data2fpga(data2fpga),
        .done(dev_done),
        .result(dev_result)
        );
    
    



    assign mem = (dev_en)  ? dev_mem :
                 (abus_en) ? abus_mem :
                             dbus_mem;
    
    assign rw = (dev_en)  ? dev_rw :
                (abus_en) ? abus_rw :
                            dbus_rw;
    
    assign addr = (dev_en)  ? dev_addr :
                  (abus_en) ? abus_addr :
                              dbus_addr;
    
    assign data2ram = (dev_en)  ? dev_data2ram :
                      (abus_en) ? abus_data2ram :
                                  dbus_data2ram;
    

    assign done = dbus_done & abus_done & dev_done;
    assign result = {dev_result, abus_result, dbus_result};
    
endmodule
module sram_test
    (
    input wire clk,
    input wire rst,
    
    output wire mem,
    output wire rw,
    input wire ready,
    
    output wire [19:0] addr,
    output wire [7:0] data2ram,
    input wire [7:0] data2fpga,
    
    output wire done,
    output wire [2:0] result
    );

    
    

    

    wire dbus_mem, abus_mem, dev_mem;
    wire dbus_rw, abus_rw, dev_rw;
    wire [19:0] dbus_addr, abus_addr, dev_addr;
    wire [7:0] dbus_data2ram, abus_data2ram, dev_data2ram;
    

    wire abus_en, dev_en;
    wire dbus_done, abus_done, dev_done;
    wire dbus_result, abus_result, dev_result;
    
    

    
    assign abus_en = dbus_done & dbus_result;
    assign dev_en = abus_done & abus_result;
    
    

    
    data_bus_test data_bus_test_unit
        (
        .clk(clk),
        .rst(rst),
        .en(1'b1),
        .mem(dbus_mem),
        .rw(dbus_rw),
        .ready(ready),
        .addr(dbus_addr),
        .data2ram(dbus_data2ram),
        .data2fpga(data2fpga),
        .done(dbus_done),
        .result(dbus_result)
        );
    
    addr_bus_test addr_bus_test_unit
        (
        .clk(clk),
        .rst(rst),
        .en(abus_en),
        .mem(abus_mem),
        .rw(abus_rw),
        .ready(ready),
        .addr(abus_addr),
        .data2ram(abus_data2ram),
        .data2fpga(data2fpga),
        .done(abus_done),
        .result(abus_result)
        );
    
    device_test device_test_unit
        (
        .clk(clk),
        .rst(rst),
        .en(dev_en),
        .mem(dev_mem),
        .rw(dev_rw),
        .ready(ready),
        .addr(dev_addr),
        .data2ram(dev_data2ram),
        .data2fpga(data2fpga),
        .done(dev_done),
        .result(dev_result)
        );
    
    



    assign mem = (dev_en)  ? dev_mem :
                 (abus_en) ? abus_mem :
                             dbus_mem;
    
    assign rw = (dev_en)  ? dev_rw :
                (abus_en) ? abus_rw :
                            dbus_rw;
    
    assign addr = (dev_en)  ? dev_addr :
                  (abus_en) ? abus_addr :
                              dbus_addr;
    
    assign data2ram = (dev_en)  ? dev_data2ram :
                      (abus_en) ? abus_data2ram :
                                  dbus_data2ram;
    

    assign done = dbus_done & abus_done & dev_done;
    assign result = {dev_result, abus_result, dbus_result};
    
endmodule