data/full_repos/permissive/20289584/D009_20131209_ALARMCLK.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/20289584/D009_20131209_ALARMCLK.v:23: syntax error, unexpected '~', expecting TYPE-IDENTIFIER\nalways @(posedge clk or posedge ~rst)\n                                ^\n%Error: data/full_repos/permissive/20289584/D009_20131209_ALARMCLK.v:35: syntax error, unexpected '=', expecting IDENTIFIER\n    Borrow = 1;\n           ^\n%Error: data/full_repos/permissive/20289584/D009_20131209_ALARMCLK.v:40: syntax error, unexpected '=', expecting IDENTIFIER\n    Borrow = 0;\n           ^\n%Error: Cannot continue\n"
module D009_20131209_ALARMCLK(clk,rst,counterOut,Borrow);


parameter DownFrom = 3;
parameter Bitwidth = 4;


input clk,rst;
output [Bitwidth-1:0] counterOut;
output Borrow;


wire clk,rst;
wire [Bitwidth-1:0] counterOut;



reg [Bitwidth-1:0] Counter;
reg Borrow;

assign counterOut[Bitwidth-1:0] = Counter[Bitwidth-1:0]-1;

always @(posedge clk or posedge ~rst)
	begin
		if(rst==0)
		begin
			Counter =DownFrom;
			Borrow = 0;
		end
		else
		begin
			Counter = Counter-1;
			if(Counter == 0)
			begin
				Borrow = 1;
				Counter =DownFrom;
			end
			else
			begin
				Borrow = 0;
			end
		end
	end
endmodule
module D009_20131209_ALARMCLK(clk,rst,counterOut,Borrow);



parameter DownFrom = 3;
parameter Bitwidth = 4;


input clk,rst;
output [Bitwidth-1:0] counterOut;
output Borrow;


wire clk,rst;
wire [Bitwidth-1:0] counterOut;



reg [Bitwidth-1:0] Counter;
reg Borrow;

assign counterOut[Bitwidth-1:0] = Counter[Bitwidth-1:0]-1;

always @(posedge clk or posedge ~rst)
	begin
		if(rst==0)
		begin
			Counter =DownFrom;
			Borrow = 0;
		end
		else
		begin
			Counter = Counter-1;
			if(Counter == 0)
			begin
				Borrow = 1;
				Counter =DownFrom;
			end
			else
			begin
				Borrow = 0;
			end
		end
	end
endmodule