data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v
1: b'%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:3: Cannot find include file: ../../define/global_def.v\n`include "../../define/global_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v.v\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v.sv\n             ../../define/global_def.v\n             ../../define/global_def.v.v\n             ../../define/global_def.v.sv\n             obj_dir/../../define/global_def.v\n             obj_dir/../../define/global_def.v.v\n             obj_dir/../../define/global_def.v.sv\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:12: Define or directive not defined: \'`ADDR_BUS\'\n    input   wire[`ADDR_BUS]     pc,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`ADDR_BUS]     pc,\n                          ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:13: Define or directive not defined: \'`INST_BUS\'\n    input   wire[`INST_BUS]     inst,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:16: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     reg_val_mux_data_1,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:17: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     reg_val_mux_data_2,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:21: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg [`REG_ADDR_BUS] reg_addr_1,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:21: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  reg [`REG_ADDR_BUS] reg_addr_1,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg [`REG_ADDR_BUS] reg_addr_2,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:23: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  reg [`REG_ADDR_BUS] reg_addr_2,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`ADDR_BUS]     branch_addr,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:27: Define or directive not defined: \'`ADDR_BUS\'\n    output  wire[`ADDR_BUS]     branch_addr,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                ram_write_en,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:33: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                ram_read_flag,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:34: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  reg [`DATA_BUS]     operand_1,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:34: Define or directive not defined: \'`DATA_BUS\'\n    output  reg [`DATA_BUS]     operand_1,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:35: Define or directive not defined: \'`DATA_BUS\'\n    output  reg [`DATA_BUS]     operand_2,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:37: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg [`REG_ADDR_BUS] write_reg_addr\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:37: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  reg [`REG_ADDR_BUS] write_reg_addr\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:43: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] imm_reg_addr_1;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] imm_reg_addr_1;\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:45: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] imm_reg_addr_2;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] imm_reg_addr_2;\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:46: Define or directive not defined: \'`DATA_BUS\'\n    wire[`DATA_BUS]     imm_operand_1;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`DATA_BUS]     imm_operand_1;\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:47: Define or directive not defined: \'`DATA_BUS\'\n    wire[`DATA_BUS]     imm_operand_2;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`DATA_BUS]     imm_operand_2;\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:49: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] imm_write_reg_addr;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] imm_write_reg_addr;\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:54: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] branch_reg_addr_1;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:54: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] branch_reg_addr_1;\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:56: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] branch_reg_addr_2;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] branch_reg_addr_2;\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:57: Define or directive not defined: \'`DATA_BUS\'\n    wire[`DATA_BUS]     branch_operand_1;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`DATA_BUS]     branch_operand_1;\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:58: Define or directive not defined: \'`DATA_BUS\'\n    wire[`DATA_BUS]     branch_operand_2;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:58: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`DATA_BUS]     branch_operand_2;\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:60: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] branch_write_reg_addr;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:60: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] branch_write_reg_addr;\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:65: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] sl_reg_addr_1;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] sl_reg_addr_1;\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:67: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] sl_reg_addr_2;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:67: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] sl_reg_addr_2;\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:68: Define or directive not defined: \'`DATA_BUS\'\n    wire[`DATA_BUS]     sl_operand_1;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:68: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`DATA_BUS]     sl_operand_1;\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:69: Define or directive not defined: \'`DATA_BUS\'\n    wire[`DATA_BUS]     sl_operand_2;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:69: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`DATA_BUS]     sl_operand_2;\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:71: Define or directive not defined: \'`REG_ADDR_BUS\'\n    wire[`REG_ADDR_BUS] sl_write_reg_addr;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:71: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`REG_ADDR_BUS] sl_write_reg_addr;\n                      ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_I.v:166: syntax error, unexpected always\n    always @ (*)    begin\n    ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module  ID_I(
    input   wire                rst,
    

    output  wire                inst_i,


    input   wire[`ADDR_BUS]     pc,
    input   wire[`INST_BUS]     inst,


    input   wire[`DATA_BUS]     reg_val_mux_data_1,
    input   wire[`DATA_BUS]     reg_val_mux_data_2,


    output  reg                 reg_read_en_1,
    output  reg [`REG_ADDR_BUS] reg_addr_1,
    output  reg                 reg_read_en_2,
    output  reg [`REG_ADDR_BUS] reg_addr_2,


    output  wire                branch_flag,
    output  wire[`ADDR_BUS]     branch_addr,


    output  wire                ram_en,
    output  wire                ram_write_en,

    output  wire                ram_read_flag,
    output  reg [`DATA_BUS]     operand_1,
    output  reg [`DATA_BUS]     operand_2,
    output  reg                 write_reg_en,
    output  reg [`REG_ADDR_BUS] write_reg_addr
);


    wire                inst_immediate;
    wire                imm_reg_read_en_1;
    wire[`REG_ADDR_BUS] imm_reg_addr_1;
    wire                imm_reg_read_en_2;
    wire[`REG_ADDR_BUS] imm_reg_addr_2;
    wire[`DATA_BUS]     imm_operand_1;
    wire[`DATA_BUS]     imm_operand_2;
    wire                imm_write_reg_en;
    wire[`REG_ADDR_BUS] imm_write_reg_addr;


    wire                inst_branch;
    wire                branch_reg_read_en_1;
    wire[`REG_ADDR_BUS] branch_reg_addr_1;
    wire                branch_reg_read_en_2;
    wire[`REG_ADDR_BUS] branch_reg_addr_2;
    wire[`DATA_BUS]     branch_operand_1;
    wire[`DATA_BUS]     branch_operand_2;
    wire                branch_write_reg_en;
    wire[`REG_ADDR_BUS] branch_write_reg_addr;


    wire                inst_sl;
    wire                sl_reg_read_en_1;
    wire[`REG_ADDR_BUS] sl_reg_addr_1;
    wire                sl_reg_read_en_2;
    wire[`REG_ADDR_BUS] sl_reg_addr_2;
    wire[`DATA_BUS]     sl_operand_1;
    wire[`DATA_BUS]     sl_operand_2;
    wire                sl_write_reg_en;
    wire[`REG_ADDR_BUS] sl_write_reg_addr;

    assign  inst_i  = inst_immediate || inst_branch || inst_sl;

    ID_IMM  id_imm0(
        .rst                (rst),


        .inst_immediate      (inst_immediate),


        .inst               (inst),


        .reg_val_mux_data_1 (reg_val_mux_data_1),
        .reg_val_mux_data_2 (reg_val_mux_data_2),


        .reg_read_en_1      (imm_reg_read_en_1),
        .reg_addr_1         (imm_reg_addr_1),
        .reg_read_en_2      (imm_reg_read_en_2),
        .reg_addr_2         (imm_reg_addr_2),


        .operand_1          (imm_operand_1),
        .operand_2          (imm_operand_2),
        .write_reg_en       (imm_write_reg_en),
        .write_reg_addr     (imm_write_reg_addr)
    );

    ID_Branch   id_branch0(
        .rst                (rst),


        .inst_branch        (inst_branch),


        .pc                 (pc),
        .inst               (inst),


        .reg_val_mux_data_1 (reg_val_mux_data_1),
        .reg_val_mux_data_2 (reg_val_mux_data_2),


        .reg_read_en_1      (branch_reg_read_en_1),
        .reg_addr_1         (branch_reg_addr_1),
        .reg_read_en_2      (branch_reg_read_en_2),
        .reg_addr_2         (branch_reg_addr_2),


        .branch_flag        (branch_flag),
        .branch_addr        (branch_addr),


        .operand_1          (branch_operand_1),
        .operand_2          (branch_operand_2),
        .write_reg_en       (branch_write_reg_en),
        .write_reg_addr     (branch_write_reg_addr)
    );

    ID_SL   id_sl0(
        .rst                (rst),
        

        .inst_sl            (inst_sl),


        .pc                 (pc),
        .inst               (inst),
        

        .reg_val_mux_data_1 (reg_val_mux_data_1),
        .reg_val_mux_data_2 (reg_val_mux_data_2),
        

        .reg_read_en_1      (sl_reg_read_en_1),
        .reg_addr_1         (sl_reg_addr_1),
        .reg_read_en_2      (sl_reg_read_en_2),
        .reg_addr_2         (sl_reg_addr_2),


        .ram_en             (ram_en),
        .ram_write_en       (ram_write_en),


        .ram_read_flag      (ram_read_flag),
        .operand_1          (sl_operand_1),
        .operand_2          (sl_operand_2),
        .write_reg_en       (sl_write_reg_en),
        .write_reg_addr     (sl_write_reg_addr)
    );

    wire[2:0]   inst_type   = {inst_immediate, inst_branch, inst_sl};

    always @ (*)    begin
        case (inst_type)

            `TYPE_IMM:  begin
                reg_read_en_1   <= imm_reg_read_en_1;
                reg_addr_1      <= imm_reg_addr_1;
                reg_read_en_2   <= imm_reg_read_en_2;
                reg_addr_2      <= imm_reg_addr_2;
                operand_1       <= imm_operand_1;
                operand_2       <= imm_operand_2;
                write_reg_en    <= imm_write_reg_en;
                write_reg_addr  <= imm_write_reg_addr;
            end

            `TYPE_B:    begin
                reg_read_en_1   <= branch_reg_read_en_1;
                reg_addr_1      <= branch_reg_addr_1;
                reg_read_en_2   <= branch_reg_read_en_2;
                reg_addr_2      <= branch_reg_addr_2;
                operand_1       <= branch_operand_1;
                operand_2       <= branch_operand_2;
                write_reg_en    <= branch_write_reg_en;
                write_reg_addr  <= branch_write_reg_addr;
            end

            `TYPE_SL:   begin
                reg_read_en_1   <= sl_reg_read_en_1;
                reg_addr_1      <= sl_reg_addr_1;
                reg_read_en_2   <= sl_reg_read_en_2;
                reg_addr_2      <= sl_reg_addr_2;
                operand_1       <= sl_operand_1;
                operand_2       <= sl_operand_2;
                write_reg_en    <= sl_write_reg_en;
                write_reg_addr  <= sl_write_reg_addr;
            end

            default:    begin
                reg_read_en_1   <= `READ_DISABLE;
                reg_addr_1      <= `ZERO_REG_ADDR;
                reg_read_en_2   <= `READ_DISABLE;
                reg_addr_2      <= `ZERO_REG_ADDR;
                operand_1       <= `ZERO_WORD;
                operand_2       <= `ZERO_WORD;
                write_reg_en    <= `WRITE_DISABLE;
                write_reg_addr  <= `ZERO_REG_ADDR;
            end

        endcase
    end

endmodule
module  ID_I(
    input   wire                rst,
    

    output  wire                inst_i,


    input   wire[`ADDR_BUS]     pc,
    input   wire[`INST_BUS]     inst,


    input   wire[`DATA_BUS]     reg_val_mux_data_1,
    input   wire[`DATA_BUS]     reg_val_mux_data_2,


    output  reg                 reg_read_en_1,
    output  reg [`REG_ADDR_BUS] reg_addr_1,
    output  reg                 reg_read_en_2,
    output  reg [`REG_ADDR_BUS] reg_addr_2,


    output  wire                branch_flag,
    output  wire[`ADDR_BUS]     branch_addr,


    output  wire                ram_en,
    output  wire                ram_write_en,

    output  wire                ram_read_flag,
    output  reg [`DATA_BUS]     operand_1,
    output  reg [`DATA_BUS]     operand_2,
    output  reg                 write_reg_en,
    output  reg [`REG_ADDR_BUS] write_reg_addr
);



    wire                inst_immediate;
    wire                imm_reg_read_en_1;
    wire[`REG_ADDR_BUS] imm_reg_addr_1;
    wire                imm_reg_read_en_2;
    wire[`REG_ADDR_BUS] imm_reg_addr_2;
    wire[`DATA_BUS]     imm_operand_1;
    wire[`DATA_BUS]     imm_operand_2;
    wire                imm_write_reg_en;
    wire[`REG_ADDR_BUS] imm_write_reg_addr;


    wire                inst_branch;
    wire                branch_reg_read_en_1;
    wire[`REG_ADDR_BUS] branch_reg_addr_1;
    wire                branch_reg_read_en_2;
    wire[`REG_ADDR_BUS] branch_reg_addr_2;
    wire[`DATA_BUS]     branch_operand_1;
    wire[`DATA_BUS]     branch_operand_2;
    wire                branch_write_reg_en;
    wire[`REG_ADDR_BUS] branch_write_reg_addr;


    wire                inst_sl;
    wire                sl_reg_read_en_1;
    wire[`REG_ADDR_BUS] sl_reg_addr_1;
    wire                sl_reg_read_en_2;
    wire[`REG_ADDR_BUS] sl_reg_addr_2;
    wire[`DATA_BUS]     sl_operand_1;
    wire[`DATA_BUS]     sl_operand_2;
    wire                sl_write_reg_en;
    wire[`REG_ADDR_BUS] sl_write_reg_addr;

    assign  inst_i  = inst_immediate || inst_branch || inst_sl;

    ID_IMM  id_imm0(
        .rst                (rst),


        .inst_immediate      (inst_immediate),


        .inst               (inst),


        .reg_val_mux_data_1 (reg_val_mux_data_1),
        .reg_val_mux_data_2 (reg_val_mux_data_2),


        .reg_read_en_1      (imm_reg_read_en_1),
        .reg_addr_1         (imm_reg_addr_1),
        .reg_read_en_2      (imm_reg_read_en_2),
        .reg_addr_2         (imm_reg_addr_2),


        .operand_1          (imm_operand_1),
        .operand_2          (imm_operand_2),
        .write_reg_en       (imm_write_reg_en),
        .write_reg_addr     (imm_write_reg_addr)
    );

    ID_Branch   id_branch0(
        .rst                (rst),


        .inst_branch        (inst_branch),


        .pc                 (pc),
        .inst               (inst),


        .reg_val_mux_data_1 (reg_val_mux_data_1),
        .reg_val_mux_data_2 (reg_val_mux_data_2),


        .reg_read_en_1      (branch_reg_read_en_1),
        .reg_addr_1         (branch_reg_addr_1),
        .reg_read_en_2      (branch_reg_read_en_2),
        .reg_addr_2         (branch_reg_addr_2),


        .branch_flag        (branch_flag),
        .branch_addr        (branch_addr),


        .operand_1          (branch_operand_1),
        .operand_2          (branch_operand_2),
        .write_reg_en       (branch_write_reg_en),
        .write_reg_addr     (branch_write_reg_addr)
    );

    ID_SL   id_sl0(
        .rst                (rst),
        

        .inst_sl            (inst_sl),


        .pc                 (pc),
        .inst               (inst),
        

        .reg_val_mux_data_1 (reg_val_mux_data_1),
        .reg_val_mux_data_2 (reg_val_mux_data_2),
        

        .reg_read_en_1      (sl_reg_read_en_1),
        .reg_addr_1         (sl_reg_addr_1),
        .reg_read_en_2      (sl_reg_read_en_2),
        .reg_addr_2         (sl_reg_addr_2),


        .ram_en             (ram_en),
        .ram_write_en       (ram_write_en),


        .ram_read_flag      (ram_read_flag),
        .operand_1          (sl_operand_1),
        .operand_2          (sl_operand_2),
        .write_reg_en       (sl_write_reg_en),
        .write_reg_addr     (sl_write_reg_addr)
    );

    wire[2:0]   inst_type   = {inst_immediate, inst_branch, inst_sl};

    always @ (*)    begin
        case (inst_type)

            `TYPE_IMM:  begin
                reg_read_en_1   <= imm_reg_read_en_1;
                reg_addr_1      <= imm_reg_addr_1;
                reg_read_en_2   <= imm_reg_read_en_2;
                reg_addr_2      <= imm_reg_addr_2;
                operand_1       <= imm_operand_1;
                operand_2       <= imm_operand_2;
                write_reg_en    <= imm_write_reg_en;
                write_reg_addr  <= imm_write_reg_addr;
            end

            `TYPE_B:    begin
                reg_read_en_1   <= branch_reg_read_en_1;
                reg_addr_1      <= branch_reg_addr_1;
                reg_read_en_2   <= branch_reg_read_en_2;
                reg_addr_2      <= branch_reg_addr_2;
                operand_1       <= branch_operand_1;
                operand_2       <= branch_operand_2;
                write_reg_en    <= branch_write_reg_en;
                write_reg_addr  <= branch_write_reg_addr;
            end

            `TYPE_SL:   begin
                reg_read_en_1   <= sl_reg_read_en_1;
                reg_addr_1      <= sl_reg_addr_1;
                reg_read_en_2   <= sl_reg_read_en_2;
                reg_addr_2      <= sl_reg_addr_2;
                operand_1       <= sl_operand_1;
                operand_2       <= sl_operand_2;
                write_reg_en    <= sl_write_reg_en;
                write_reg_addr  <= sl_write_reg_addr;
            end

            default:    begin
                reg_read_en_1   <= `READ_DISABLE;
                reg_addr_1      <= `ZERO_REG_ADDR;
                reg_read_en_2   <= `READ_DISABLE;
                reg_addr_2      <= `ZERO_REG_ADDR;
                operand_1       <= `ZERO_WORD;
                operand_2       <= `ZERO_WORD;
                write_reg_en    <= `WRITE_DISABLE;
                write_reg_addr  <= `ZERO_REG_ADDR;
            end

        endcase
    end

endmodule