data/full_repos/permissive/143278/ivltests/bitsel7.v
 line:64: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/bitsel7.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("target0[%2d]=%b, mux0=%b", idx,   target0[idx],   mux0);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/bitsel7.v:33: Bit extraction of var[63:0] requires 6 bit index, not 7 bits.\n                                                                       : ... In instance main\n   wire       mux0 = target0[idx];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/bitsel7.v:64: Bit extraction of var[63:0] requires 6 bit index, not 7 bits.\n                                                                       : ... In instance main\n  #1 $display("target0[%2d]=%b, mux0=%b", idx,   target0[idx],   mux0);\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/bitsel7.v:67: Bit extraction of var[63:0] requires 6 bit index, not 7 bits.\n                                                                       : ... In instance main\n  if (target0[idx] !== mux0) begin\n             ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [63:0] target0 = 64'h0040_2000_0000_0000;
   reg [64:1] target1 = 64'h0040_2000_0000_0000;
   reg [6:0]  idx;

   wire       mux0 = target0[idx];
   wire       mux1 = target1[idx+1];

   initial begin
      $display( "Using constant indices:" );
      $display( "    %b=v[45]", target0[45] );
      if (target0[45] !== 1'b1) begin
	 $display("FAILED -- target0[45] != 1");
	 $finish;
      end

      $display( "    %b=v[54]", target0[54] );
      if (target0[54] !== 1'b1) begin
	 $display("FAILED -- target0[54] != 1");
	 $finish;
      end

      $display( "    %b=v[18]", target0[18] );
      if (target0[18] !== 1'b0) begin
	 $display("FAILED -- target0[18] != 0");
	 $finish;
      end

      $display( "    %b=v[ 9]", target0[9] );
      if (target0[9] !== 1'b0) begin
	 $display("FAILED -- target0[ 9] != 0");
	 $finish;
      end

      $display( "Using calcuated indices:" );
      for (idx = 0 ;  idx < 64 ;  idx = idx + 1) begin
	 #1 $display("target0[%2d]=%b, mux0=%b", idx,   target0[idx],   mux0);
	    $display("target1[%2d]=%b, mux1=%b", idx+1, target1[idx+1], mux1);

	 if (target0[idx] !== mux0) begin
	    $display("FAILED -- target0[idx] != mux0");
	    $finish;
	 end

	 if (target1[idx+1] !== mux1) begin
	    $display("FAILED -- target1[idx+1] != mux1");
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule
module main;


   reg [63:0] target0 = 64'h0040_2000_0000_0000;
   reg [64:1] target1 = 64'h0040_2000_0000_0000;
   reg [6:0]  idx;

   wire       mux0 = target0[idx];
   wire       mux1 = target1[idx+1];

   initial begin
      $display( "Using constant indices:" );
      $display( "    %b=v[45]", target0[45] );
      if (target0[45] !== 1'b1) begin
	 $display("FAILED -- target0[45] != 1");
	 $finish;
      end

      $display( "    %b=v[54]", target0[54] );
      if (target0[54] !== 1'b1) begin
	 $display("FAILED -- target0[54] != 1");
	 $finish;
      end

      $display( "    %b=v[18]", target0[18] );
      if (target0[18] !== 1'b0) begin
	 $display("FAILED -- target0[18] != 0");
	 $finish;
      end

      $display( "    %b=v[ 9]", target0[9] );
      if (target0[9] !== 1'b0) begin
	 $display("FAILED -- target0[ 9] != 0");
	 $finish;
      end

      $display( "Using calcuated indices:" );
      for (idx = 0 ;  idx < 64 ;  idx = idx + 1) begin
	 #1 $display("target0[%2d]=%b, mux0=%b", idx,   target0[idx],   mux0);
	    $display("target1[%2d]=%b, mux1=%b", idx+1, target1[idx+1], mux1);

	 if (target0[idx] !== mux0) begin
	    $display("FAILED -- target0[idx] != mux0");
	    $finish;
	 end

	 if (target1[idx+1] !== mux1) begin
	    $display("FAILED -- target1[idx+1] != mux1");
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule