data/full_repos/permissive/200314387/verilog/74138/test.v
 line:228: before: ">"
1: b'%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:7: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/74138,data/full_repos/permissive/200314387/../lib/assertion.v\n             data/full_repos/permissive/200314387/verilog/74138,data/full_repos/permissive/200314387/../lib/assertion.v.v\n             data/full_repos/permissive/200314387/verilog/74138,data/full_repos/permissive/200314387/../lib/assertion.v.sv\n             ../lib/assertion.v\n             ../lib/assertion.v.v\n             ../lib/assertion.v.sv\n             obj_dir/../lib/assertion.v\n             obj_dir/../lib/assertion.v.v\n             obj_dir/../lib/assertion.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:8: Cannot find include file: ./hct74138.v\n`include "./hct74138.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:20: Cannot find include file: ../lib/display_snippet.sv\n    `include "../lib/display_snippet.sv" \n             ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:23: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:24: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:40: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("initial");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:40: syntax error, unexpected \';\'\n        `DISPLAY("initial");\n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:41: Define or directive not defined: \'`Equals\'\n        `Equals(Y, 8\'bx)\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:41: syntax error, unexpected \',\'\n        `Equals(Y, 8\'bx)\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:43: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("setting address=0");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:48: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("disable");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:48: syntax error, unexpected \';\'\n        `DISPLAY("disable");\n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:53: Define or directive not defined: \'`Equals\'\n        `Equals(Y, 8\'b11111111)\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:53: syntax error, unexpected \',\'\n        `Equals(Y, 8\'b11111111)\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:55: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("enable");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:60: Define or directive not defined: \'`Equals\'\n        `Equals(Y, 8\'b11111110)\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:60: syntax error, unexpected \',\'\n        `Equals(Y, 8\'b11111110)\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:62: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("address=1");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:65: Define or directive not defined: \'`Equals\'\n        `Equals(Y, 8\'b11111101)\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:65: syntax error, unexpected \',\'\n        `Equals(Y, 8\'b11111101)\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:67: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("address=2");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:70: Define or directive not defined: \'`Equals\'\n        `Equals(Y, 8\'b11111011)\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:70: syntax error, unexpected \',\'\n        `Equals(Y, 8\'b11111011)\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:72: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("address=3");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:75: Define or directive not defined: \'`Equals\'\n        `Equals(Y, 8\'b11110111)\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:75: syntax error, unexpected \',\'\n        `Equals(Y, 8\'b11110111)\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:77: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("disable");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:80: Define or directive not defined: \'`Equals\'\n        `Equals(Y, 8\'b11111111)\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:80: syntax error, unexpected \',\'\n        `Equals(Y, 8\'b11111111)\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:82: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("enable output");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:97: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("change address");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:97: syntax error, unexpected \';\'\n        `DISPLAY("change address");\n                                  ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:111: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("all enables x");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:111: syntax error, unexpected \';\'\n        `DISPLAY("all enables x");\n                                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:116: Define or directive not defined: \'`Equals\'\n        `Equals(Y, 8\'bxxxxxxxx)\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:116: syntax error, unexpected \',\'\n        `Equals(Y, 8\'bxxxxxxxx)\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:118: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("if E1=disable then this overrides X in other fields - should be disabled");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:123: Define or directive not defined: \'`Equals\'\n        `Equals(Y, 8\'b11111111)\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:123: syntax error, unexpected \',\'\n        `Equals(Y, 8\'b11111111)\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:125: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("if E2=disable then this overrides X in other fields - should be disabled");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:130: Define or directive not defined: \'`Equals\'\n        `Equals(Y, 8\'b11111111)\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:130: syntax error, unexpected \',\'\n        `Equals(Y, 8\'b11111111)\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:133: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("A as x");\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:139: Define or directive not defined: \'`Equals\'\n        `Equals(Y, 8\'bxxxxxxxx)\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:139: syntax error, unexpected \',\'\n        `Equals(Y, 8\'bxxxxxxxx)\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74138/test.v:141: Define or directive not defined: \'`DISPLAY\'\n        `DISPLAY("done");\n        ^~~~~~~~\n%Error: Exiting due to 46 error(s)\n'
module test();

    reg [2:0] A;
    wire [7:0] Y;

    logic Enable1_bar;
    logic Enable2_bar;
    logic Enable3;

    `include "../lib/display_snippet.sv"

    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0, test);
    end
     
    time timer;

    hct74138 demux(
        .Enable1_bar,
        .Enable2_bar,
        .Enable3,
        .A,
        .Y
    );

    initial begin
      

        `DISPLAY("initial");
        `Equals(Y, 8'bx)

        `DISPLAY("setting address=0");
        A = 0;
        #400


        `DISPLAY("disable");
        Enable1_bar = 1;
        Enable2_bar = 1;
        Enable3 = 1;
        #40
        `Equals(Y, 8'b11111111)

        `DISPLAY("enable");
        Enable1_bar = 0;
        Enable2_bar = 0;
        Enable3 = 1;
        #40
        `Equals(Y, 8'b11111110)

        `DISPLAY("address=1");
        A = 1;
        #400
        `Equals(Y, 8'b11111101)

        `DISPLAY("address=2");
        A = 2;
        #400
        `Equals(Y, 8'b11111011)

        `DISPLAY("address=3");
        A = 3;
        #400
        `Equals(Y, 8'b11110111)

        `DISPLAY("disable");
        Enable1_bar = 1;
        #40
        `Equals(Y, 8'b11111111)
        
        `DISPLAY("enable output");
        timer=$time;
        Enable1_bar = 0;
`ifndef verilator
        wait(Y === 8'b11110111);
`endif
        if ($time - timer != 19) begin
            $display("BAD SPEED - EXPECTED 19ns - TOOK %-d", ($time - timer));
            $finish();
        end
        else
            $display("TOOK %-d", ($time - timer));
        
        #50

        `DISPLAY("change address");
        timer=$time;
        A = 0;
`ifndef verilator
        wait(Y === 8'b11111110);
`endif
        if ($time - timer != 17)  begin
            $display("BAD SPEED - EXPECTED 17ns - TOOK %-d", ($time - timer));
            $finish();
        end
        else
            $display("TOOK %-d", ($time - timer));

      #50
        `DISPLAY("all enables x");
        Enable1_bar = 'x;
        Enable2_bar = 'x;
        Enable3 = 'x;
        #40
        `Equals(Y, 8'bxxxxxxxx)
        
        `DISPLAY("if E1=disable then this overrides X in other fields - should be disabled");
        Enable1_bar = 1;
        Enable2_bar = 'x;
        Enable3 = 'x;
        #40
        `Equals(Y, 8'b11111111)

        `DISPLAY("if E2=disable then this overrides X in other fields - should be disabled");
        Enable1_bar = 'x;
        Enable2_bar = 1;
        Enable3 = 'x;
        #40
        `Equals(Y, 8'b11111111)

      #50
        `DISPLAY("A as x");
        Enable1_bar = '0;
        Enable2_bar = '0;
        Enable3 = '1;
        A = 3'b10x;
        #40
        `Equals(Y, 8'bxxxxxxxx)
        
        `DISPLAY("done");
        $finish;
    end

endmodule
module test();


    reg [2:0] A;
    wire [7:0] Y;

    logic Enable1_bar;
    logic Enable2_bar;
    logic Enable3;

    `include "../lib/display_snippet.sv"

    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0, test);
    end
     
    time timer;

    hct74138 demux(
        .Enable1_bar,
        .Enable2_bar,
        .Enable3,
        .A,
        .Y
    );

    initial begin
      

        `DISPLAY("initial");
        `Equals(Y, 8'bx)

        `DISPLAY("setting address=0");
        A = 0;
        #400


        `DISPLAY("disable");
        Enable1_bar = 1;
        Enable2_bar = 1;
        Enable3 = 1;
        #40
        `Equals(Y, 8'b11111111)

        `DISPLAY("enable");
        Enable1_bar = 0;
        Enable2_bar = 0;
        Enable3 = 1;
        #40
        `Equals(Y, 8'b11111110)

        `DISPLAY("address=1");
        A = 1;
        #400
        `Equals(Y, 8'b11111101)

        `DISPLAY("address=2");
        A = 2;
        #400
        `Equals(Y, 8'b11111011)

        `DISPLAY("address=3");
        A = 3;
        #400
        `Equals(Y, 8'b11110111)

        `DISPLAY("disable");
        Enable1_bar = 1;
        #40
        `Equals(Y, 8'b11111111)
        
        `DISPLAY("enable output");
        timer=$time;
        Enable1_bar = 0;
`ifndef verilator
        wait(Y === 8'b11110111);
`endif
        if ($time - timer != 19) begin
            $display("BAD SPEED - EXPECTED 19ns - TOOK %-d", ($time - timer));
            $finish();
        end
        else
            $display("TOOK %-d", ($time - timer));
        
        #50

        `DISPLAY("change address");
        timer=$time;
        A = 0;
`ifndef verilator
        wait(Y === 8'b11111110);
`endif
        if ($time - timer != 17)  begin
            $display("BAD SPEED - EXPECTED 17ns - TOOK %-d", ($time - timer));
            $finish();
        end
        else
            $display("TOOK %-d", ($time - timer));

      #50
        `DISPLAY("all enables x");
        Enable1_bar = 'x;
        Enable2_bar = 'x;
        Enable3 = 'x;
        #40
        `Equals(Y, 8'bxxxxxxxx)
        
        `DISPLAY("if E1=disable then this overrides X in other fields - should be disabled");
        Enable1_bar = 1;
        Enable2_bar = 'x;
        Enable3 = 'x;
        #40
        `Equals(Y, 8'b11111111)

        `DISPLAY("if E2=disable then this overrides X in other fields - should be disabled");
        Enable1_bar = 'x;
        Enable2_bar = 1;
        Enable3 = 'x;
        #40
        `Equals(Y, 8'b11111111)

      #50
        `DISPLAY("A as x");
        Enable1_bar = '0;
        Enable2_bar = '0;
        Enable3 = '1;
        A = 3'b10x;
        #40
        `Equals(Y, 8'bxxxxxxxx)
        
        `DISPLAY("done");
        $finish;
    end

endmodule