data/full_repos/permissive/132220215/carry_lookahead_unit.v
1: b"%Error: data/full_repos/permissive/132220215/carry_lookahead_unit.v:34: Can't find definition of variable: 'w1'\n                                                                      : ... Suggested alternative: 'w1_1'\n or(carry[1],G[0],w1); \n                  ^~\n%Error: Exiting due to 1 error(s)\n"
module CLU(
	input [3:0] A,
	input [3:0] B,
	input Ci,
	output Co);
 

 wire [3:0] P;
 wire [3:0] G;
 wire [4:0] carry;

 assign carry[0] = Ci;
 assign Co = carry[4]; 





 genvar i;

 generate
	 for(i=0;i<4;i=i+1)
	 begin
		or P_i(P[i],A[i],B[i]);
		and G_i(G[i],A[i],B[i]);
	 end
 endgenerate


 wire w1_1;
 and(w1_1,P[0],carry[0]);
 or(carry[1],G[0],w1); 
 

 wire w2_1,w2_2;
 and(w2_1,G[0],P[1]);
 and(w2_2,P[1],P[0],carry[0]);
 or(carry[2],G[1],w2_1,w2_2);


 wire w3_1,w3_2,w3_3;
 and(w3_1,G[1],P[2]);
 and(w3_2,G[0],P[1],P[2]);
 and(w3_3,P[2],P[1],P[0],carry[0]); 
 or(carry[3],G[2],w3_1,w3_2,w3_3);
 

 wire w4_1,w4_2,w4_3,w4_4;
 and(w4_1,G[2],P[3]);
 and(w4_2,G[1],P[2],P[3]);
 and(w4_3,G[0],P[1],P[2],P[3]);
 and(w4_4,P[3],P[2],P[1],P[0],carry[0]);
 or(carry[4],w4_1,w4_2,w4_3,w4_4);

endmodule
module CLU(
	input [3:0] A,
	input [3:0] B,
	input Ci,
	output Co);

 

 wire [3:0] P;
 wire [3:0] G;
 wire [4:0] carry;

 assign carry[0] = Ci;
 assign Co = carry[4]; 





 genvar i;

 generate
	 for(i=0;i<4;i=i+1)
	 begin
		or P_i(P[i],A[i],B[i]);
		and G_i(G[i],A[i],B[i]);
	 end
 endgenerate


 wire w1_1;
 and(w1_1,P[0],carry[0]);
 or(carry[1],G[0],w1); 
 

 wire w2_1,w2_2;
 and(w2_1,G[0],P[1]);
 and(w2_2,P[1],P[0],carry[0]);
 or(carry[2],G[1],w2_1,w2_2);


 wire w3_1,w3_2,w3_3;
 and(w3_1,G[1],P[2]);
 and(w3_2,G[0],P[1],P[2]);
 and(w3_3,P[2],P[1],P[0],carry[0]); 
 or(carry[3],G[2],w3_1,w3_2,w3_3);
 

 wire w4_1,w4_2,w4_3,w4_4;
 and(w4_1,G[2],P[3]);
 and(w4_2,G[1],P[2],P[3]);
 and(w4_3,G[0],P[1],P[2],P[3]);
 and(w4_4,P[3],P[2],P[1],P[0],carry[0]);
 or(carry[4],w4_1,w4_2,w4_3,w4_4);

endmodule