data/full_repos/permissive/197356760/CachCoherency/bus.v
None: at end of input
1: b'%Error: data/full_repos/permissive/197356760/CachCoherency/bus.v:9: Cannot find include file: parameter.v\n`include "parameter.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197356760/CachCoherency,data/full_repos/permissive/197356760/parameter.v\n             data/full_repos/permissive/197356760/CachCoherency,data/full_repos/permissive/197356760/parameter.v.v\n             data/full_repos/permissive/197356760/CachCoherency,data/full_repos/permissive/197356760/parameter.v.sv\n             parameter.v\n             parameter.v.v\n             parameter.v.sv\n             obj_dir/parameter.v\n             obj_dir/parameter.v.v\n             obj_dir/parameter.v.sv\n%Error: data/full_repos/permissive/197356760/CachCoherency/bus.v:32: Cannot find include file: parameter.v\n`include "parameter.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/bus.v:54: Cannot find include file: parameter.v\n`include "parameter.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/bus.v:11: Define or directive not defined: \'`data_siz\'\n input  wire[`data_siz-1:0] in0,in1,in2,in3; \n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/bus.v:12: Define or directive not defined: \'`sel_siz\'\n                                                                   : ... Suggested alternative: \'`elsif\'\n input  wire[`sel_siz-1:0] sel ;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/bus.v:13: Define or directive not defined: \'`data_siz\'\n output reg[`data_siz-1:0] out;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/bus.v:34: Define or directive not defined: \'`address_rang\'\n input  wire[`address_rang-1:0] in0,in1,in2,in3; \n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/bus.v:35: Define or directive not defined: \'`sel_siz\'\n                                                                   : ... Suggested alternative: \'`elsif\'\n input  wire[`sel_siz-1:0] sel ;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/bus.v:36: Define or directive not defined: \'`address_rang\'\n output reg[`address_rang-1:0] out;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/bus.v:57: Define or directive not defined: \'`sel_siz\'\n                                                                   : ... Suggested alternative: \'`elsif\'\n input  wire[`sel_siz-1:0] sel ;\n             ^~~~~~~~\n%Error: Exiting due to 10 error(s)\n'
module mux_data(in0,in1,in2,in3,sel,out);
`include "parameter.v"
	
	input  wire[`data_siz-1:0] in0,in1,in2,in3; 
	input  wire[`sel_siz-1:0] sel ;
	output reg[`data_siz-1:0] out;

	always @ (in0,in1,in2,in3,sel)
	begin
		if (sel== 2'b00)
			out= in0;
		else if (sel== 2'b01)
			out= in1;
		else if (sel== 2'b10)
			out= in2;
		else if (sel== 2'b11)
			out= in3;			

	end
endmodule
module mux_data(in0,in1,in2,in3,sel,out);

`include "parameter.v"
	
	input  wire[`data_siz-1:0] in0,in1,in2,in3; 
	input  wire[`sel_siz-1:0] sel ;
	output reg[`data_siz-1:0] out;

	always @ (in0,in1,in2,in3,sel)
	begin
		if (sel== 2'b00)
			out= in0;
		else if (sel== 2'b01)
			out= in1;
		else if (sel== 2'b10)
			out= in2;
		else if (sel== 2'b11)
			out= in3;			

	end
endmodule