data/full_repos/permissive/169382915/verif/tb/tb_scarv_cop_top.v
 line:48: before: "integer"
1: b'%Warning-STMTDLY: data/full_repos/permissive/169382915/verif/tb/tb_scarv_cop_top.v:29: Unsupported: Ignoring delay on this delayed statement.\ninitial #80 g_resetn = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169382915/verif/tb/tb_scarv_cop_top.v:30: Unsupported: Ignoring delay on this delayed statement.\nalways @(g_clk) #20 g_clk <= !g_clk;\n                ^\n%Error: data/full_repos/permissive/169382915/verif/tb/tb_scarv_cop_top.v:66: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile(wavesfile);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/169382915/verif/tb/tb_scarv_cop_top.v:67: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,tb_scarv_cop_top);\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_scarv_cop_top();

reg    g_clk    ;
wire   g_clk_req;
reg    g_resetn ;




initial g_resetn = 0;
initial g_clk    = 0;

initial #80 g_resetn = 1;
always @(g_clk) #20 g_clk <= !g_clk;

reg [10:0] clk_counter = 0;
always @(posedge g_clk) begin
    clk_counter = clk_counter + 1;

    if(clk_counter > TB_MAX_CYCLES) begin
        $finish;
    end
end

integer     TB_MAX_CYCLES = 100;
localparam  SIM_MEM_SIZE  = 128;

reg [255*8:0] wavesfile;
reg [255*8:0] imemfile;

initial begin
    integer i;
    
    if($value$plusargs("VECTOR=%s",imemfile)) begin
        $display("VECTOR:    %s", imemfile);
        for(i = 0; i < SIM_MEM_SIZE; i = i + 1)
            sim_instr_mem[i] = 0;
        $readmemh(imemfile, sim_instr_mem);
    end
    
    if($value$plusargs("TIMEOUT=%d",TB_MAX_CYCLES)) begin
        $display("TIMEOUT : %d", TB_MAX_CYCLES);
    end
    
    if($value$plusargs("WAVES=%s",wavesfile)) begin
    end else begin
        wavesfile="work/waves-icarus.vcd";
    end
    
    $dumpfile(wavesfile);
    $dumpvars(0,tb_scarv_cop_top);
end





reg  [31:0] sim_instr_mem [SIM_MEM_SIZE-1:0];
reg  [31:0] sim_instr_cnt;
wire [ 5:0] n_sim_instr_cnt = sim_instr_cnt + 1;






wire [31:0] cop_insn_enc = sim_instr_mem[sim_instr_cnt];



always @(posedge g_clk) begin
    if(!g_resetn) begin
        sim_instr_cnt <= 0;
    end else if(cop_insn_finish) begin
        sim_instr_cnt <= n_sim_instr_cnt;;
    end
end


always @(posedge g_clk) begin
    if(!g_resetn) begin
        cpu_insn_req <= 1'b0;

    end else if( cpu_insn_req &&  cop_insn_ack) begin
        cpu_insn_req <= $random & 1;
    
    end else if( cpu_insn_req && !cop_insn_ack) begin
        cpu_insn_req <= 1'b1;

    end else if(!cpu_insn_req &&  cop_insn_ack) begin
        cpu_insn_req <= $random & 1;

    end else if(!cpu_insn_req && !cop_insn_ack) begin
        cpu_insn_req <= $random & 1;

    end
end


initial cpu_rs1 = $random;
always @(posedge g_clk) if(cop_insn_finish) if($random & 1'b1)
    cpu_rs1 <= $random; else cpu_rs1 <= $random & 32'hFFFF_FFFC;


always @(posedge g_clk) begin
    if(!g_resetn) begin
        cpu_insn_ack <= 1'b0;
    end else begin
        cpu_insn_ack <= $random | 1'b1;
    end
end



always @(posedge g_clk) if(g_resetn)
    cop_mem_error <= 1'b0;
    else if(cop_mem_cen) cop_mem_error <= $random&'h7 == 0;
always @(posedge g_clk) cop_mem_stall <= $random;
always @(posedge g_clk) if(!cop_mem_stall) cop_mem_rdata <= $random;







reg              cpu_insn_req    ;
wire             cop_insn_ack    ;
reg  [31:0]      cpu_rs1         ;

wire             cop_wen         ;
wire [ 4:0]      cop_waddr       ;
wire [31:0]      cop_wdata       ;
wire [ 2:0]      cop_result      ;
wire             cop_insn_rsp    ;
reg              cpu_insn_ack    ;



wire             cop_mem_cen     ;
wire             cop_mem_wen     ;
wire [31:0]      cop_mem_addr    ;
wire [31:0]      cop_mem_wdata   ;
reg  [31:0]      cop_mem_rdata   ;
wire [ 3:0]      cop_mem_ben     ;
reg              cop_mem_stall   ;
reg              cop_mem_error   ;



wire cop_insn_valid  = cpu_insn_req && cop_insn_ack;
wire cop_insn_finish = cop_insn_rsp && cpu_insn_ack;





scarv_cop_top i_dut(
.g_clk         (g_clk        ) ,
.g_clk_req     (g_clk_req    ) ,
.g_resetn      (g_resetn     ) ,
.cpu_insn_req  (cpu_insn_req ) ,
.cop_insn_ack  (cop_insn_ack ) ,
.cpu_insn_enc  (cop_insn_enc ) ,
.cpu_rs1       (cpu_rs1      ) ,
.cop_wen       (cop_wen      ) ,
.cop_waddr     (cop_waddr    ) ,
.cop_wdata     (cop_wdata    ) ,
.cop_result    (cop_result   ) ,
.cop_insn_rsp  (cop_insn_rsp ) ,
.cpu_insn_ack  (cpu_insn_ack ) ,
.cop_mem_cen   (cop_mem_cen  ) ,
.cop_mem_wen   (cop_mem_wen  ) ,
.cop_mem_addr  (cop_mem_addr ) ,
.cop_mem_wdata (cop_mem_wdata) ,
.cop_mem_rdata (cop_mem_rdata) ,
.cop_mem_ben   (cop_mem_ben  ) ,
.cop_mem_stall (cop_mem_stall) ,
.cop_mem_error (cop_mem_error)
);

endmodule
module tb_scarv_cop_top();


reg    g_clk    ;
wire   g_clk_req;
reg    g_resetn ;




initial g_resetn = 0;
initial g_clk    = 0;

initial #80 g_resetn = 1;
always @(g_clk) #20 g_clk <= !g_clk;

reg [10:0] clk_counter = 0;
always @(posedge g_clk) begin
    clk_counter = clk_counter + 1;

    if(clk_counter > TB_MAX_CYCLES) begin
        $finish;
    end
end

integer     TB_MAX_CYCLES = 100;
localparam  SIM_MEM_SIZE  = 128;

reg [255*8:0] wavesfile;
reg [255*8:0] imemfile;

initial begin
    integer i;
    
    if($value$plusargs("VECTOR=%s",imemfile)) begin
        $display("VECTOR:    %s", imemfile);
        for(i = 0; i < SIM_MEM_SIZE; i = i + 1)
            sim_instr_mem[i] = 0;
        $readmemh(imemfile, sim_instr_mem);
    end
    
    if($value$plusargs("TIMEOUT=%d",TB_MAX_CYCLES)) begin
        $display("TIMEOUT : %d", TB_MAX_CYCLES);
    end
    
    if($value$plusargs("WAVES=%s",wavesfile)) begin
    end else begin
        wavesfile="work/waves-icarus.vcd";
    end
    
    $dumpfile(wavesfile);
    $dumpvars(0,tb_scarv_cop_top);
end





reg  [31:0] sim_instr_mem [SIM_MEM_SIZE-1:0];
reg  [31:0] sim_instr_cnt;
wire [ 5:0] n_sim_instr_cnt = sim_instr_cnt + 1;






wire [31:0] cop_insn_enc = sim_instr_mem[sim_instr_cnt];



always @(posedge g_clk) begin
    if(!g_resetn) begin
        sim_instr_cnt <= 0;
    end else if(cop_insn_finish) begin
        sim_instr_cnt <= n_sim_instr_cnt;;
    end
end


always @(posedge g_clk) begin
    if(!g_resetn) begin
        cpu_insn_req <= 1'b0;

    end else if( cpu_insn_req &&  cop_insn_ack) begin
        cpu_insn_req <= $random & 1;
    
    end else if( cpu_insn_req && !cop_insn_ack) begin
        cpu_insn_req <= 1'b1;

    end else if(!cpu_insn_req &&  cop_insn_ack) begin
        cpu_insn_req <= $random & 1;

    end else if(!cpu_insn_req && !cop_insn_ack) begin
        cpu_insn_req <= $random & 1;

    end
end


initial cpu_rs1 = $random;
always @(posedge g_clk) if(cop_insn_finish) if($random & 1'b1)
    cpu_rs1 <= $random; else cpu_rs1 <= $random & 32'hFFFF_FFFC;


always @(posedge g_clk) begin
    if(!g_resetn) begin
        cpu_insn_ack <= 1'b0;
    end else begin
        cpu_insn_ack <= $random | 1'b1;
    end
end



always @(posedge g_clk) if(g_resetn)
    cop_mem_error <= 1'b0;
    else if(cop_mem_cen) cop_mem_error <= $random&'h7 == 0;
always @(posedge g_clk) cop_mem_stall <= $random;
always @(posedge g_clk) if(!cop_mem_stall) cop_mem_rdata <= $random;







reg              cpu_insn_req    ;
wire             cop_insn_ack    ;
reg  [31:0]      cpu_rs1         ;

wire             cop_wen         ;
wire [ 4:0]      cop_waddr       ;
wire [31:0]      cop_wdata       ;
wire [ 2:0]      cop_result      ;
wire             cop_insn_rsp    ;
reg              cpu_insn_ack    ;



wire             cop_mem_cen     ;
wire             cop_mem_wen     ;
wire [31:0]      cop_mem_addr    ;
wire [31:0]      cop_mem_wdata   ;
reg  [31:0]      cop_mem_rdata   ;
wire [ 3:0]      cop_mem_ben     ;
reg              cop_mem_stall   ;
reg              cop_mem_error   ;



wire cop_insn_valid  = cpu_insn_req && cop_insn_ack;
wire cop_insn_finish = cop_insn_rsp && cpu_insn_ack;





scarv_cop_top i_dut(
.g_clk         (g_clk        ) ,
.g_clk_req     (g_clk_req    ) ,
.g_resetn      (g_resetn     ) ,
.cpu_insn_req  (cpu_insn_req ) ,
.cop_insn_ack  (cop_insn_ack ) ,
.cpu_insn_enc  (cop_insn_enc ) ,
.cpu_rs1       (cpu_rs1      ) ,
.cop_wen       (cop_wen      ) ,
.cop_waddr     (cop_waddr    ) ,
.cop_wdata     (cop_wdata    ) ,
.cop_result    (cop_result   ) ,
.cop_insn_rsp  (cop_insn_rsp ) ,
.cpu_insn_ack  (cpu_insn_ack ) ,
.cop_mem_cen   (cop_mem_cen  ) ,
.cop_mem_wen   (cop_mem_wen  ) ,
.cop_mem_addr  (cop_mem_addr ) ,
.cop_mem_wdata (cop_mem_wdata) ,
.cop_mem_rdata (cop_mem_rdata) ,
.cop_mem_ben   (cop_mem_ben  ) ,
.cop_mem_stall (cop_mem_stall) ,
.cop_mem_error (cop_mem_error)
);

endmodule