data/full_repos/permissive/148324174/FIFO/sync_r2w.v
data/verilator_xmls/c0ca97a6-55a0-4f2c-8336-0f63cbe84e85.xml
module sync_r2w #(
    parameter ADDRSIZE = 4
    )(
    output reg [ADDRSIZE:0] wrptr2,
    input      [ADDRSIZE:0] rptr,
    input                   wclk, wrst
    );

reg [ADDRSIZE:0] wrptr1;

always @(posedge wclk or posedge wrst) begin
    if (wrst) begin
        {wrptr2, wrptr1} <= 0;
    end
    else begin
        {wrptr2, wrptr1} <= {wrptr1, rptr};
    end
end

endmodule
module sync_r2w #(
    parameter ADDRSIZE = 4
    )(
    output reg [ADDRSIZE:0] wrptr2,
    input      [ADDRSIZE:0] rptr,
    input                   wclk, wrst
    );


reg [ADDRSIZE:0] wrptr1;

always @(posedge wclk or posedge wrst) begin
    if (wrst) begin
        {wrptr2, wrptr1} <= 0;
    end
    else begin
        {wrptr2, wrptr1} <= {wrptr1, rptr};
    end
end

endmodule