data/full_repos/permissive/199399537/sdr_test.v
 line:22: before: ")"
1: b"%Error: data/full_repos/permissive/199399537/sdr_test.v:22: syntax error, unexpected ')', expecting '['\n   );\n   ^\n%Error: data/full_repos/permissive/199399537/sdr_test.v:80: syntax error, unexpected IDENTIFIER\nsys_ctrl  uut_sysctrl(\n^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module sdr_test(
				rst_n,
				clk,
				clk_100m,
				sdram_clk,
				sdram_cke,
				sdram_cs_n,
				sdram_ras_n,
				sdram_cas_n,
				sdram_we_n,
				sdram_ba,
				sdram_addr,
				sdram_data,
				sdram_udqm,
				sdram_ldqm,	
				rs232_tx,
				tx_start,
				wrf_use,
				rdf_use,
			);

input 			clk;
input 			rst_n;
output 		clk_100m;
output 		sdram_clk;
output 		sdram_cke;
output 		sdram_cs_n;
output 		sdram_ras_n;
output 		sdram_cas_n;
output 		sdram_we_n;
output		[1:0] sdram_ba;
output		[12:0] sdram_addr;
output 		sdram_udqm;
output 		sdram_ldqm;
inout			[15:0] sdram_data;
output 		rs232_tx;
output 		tx_start;
output 		[8:0] wrf_use;
output 		[8:0] rdf_use;




wire sdram_wr_req;
wire sdram_rd_req;
wire sdram_wr_ack;
wire sdram_rd_ack;
wire[21:0] sys_addr;
wire[15:0] sys_data_in;

wire[15:0] sys_data_out;
wire sdram_busy;
wire sys_dout_rdy;


wire[15:0] wrf_din;
wire wrf_wrreq;

wire[15:0] rdf_dout;
wire rdf_rdreq;


wire clk_20m;
wire clk_100m;
wire sys_rst_n;
wire tx_start;

wire syswr_done;
wire [4:0] index;
wire  write;
wire [15:0] dat;


sys_ctrl		uut_sysctrl(
					.clk(clk),
					.rst_n(rst_n),
					.sys_rst_n(sys_rst_n),
					.clk_20m(clk_20m),
				   .clk_100m(clk_100m),
				   .sdram_clk(sdram_clk)
					);




sdram_top		uut_sdramtop(				
							.clk(clk_100m),
							.rst_n(sys_rst_n),
							.sdram_wr_req(sdram_wr_req),
							.sdram_rd_req(sdram_rd_req),
							.sdram_wr_ack(sdram_wr_ack),
							.sdram_rd_ack(sdram_rd_ack),	
							.sys_addr(sys_addr),
							.sys_data_in(sys_data_in),
							.sys_data_out(sys_data_out),
							.sdram_cke(sdram_cke),
							.sdram_cs_n(sdram_cs_n),
							.sdram_ras_n(sdram_ras_n),
							.sdram_cas_n(sdram_cas_n),
							.sdram_we_n(sdram_we_n),
							.sdram_ba(sdram_ba),
							.sdram_addr(sdram_addr),
							.sdram_data(sdram_data),
							.sdram_udqm(sdram_udqm),
							.sdram_ldqm(sdram_ldqm)
					);
	

sdfifo_ctrl			uut_sdffifoctrl(
						.clk_20m(clk_100m),
						.clk_100m(clk_100m),
						.wrf_din(wrf_din),
						.wrf_wrreq(wrf_wrreq),
						.sdram_wr_ack(sdram_wr_ack),					
						.sys_data_in(sys_data_in),
						.sdram_wr_req(sdram_wr_req),
						.sys_data_out(sys_data_out),
						.rdf_rdreq(rdf_rdreq),
						.sdram_rd_ack(sdram_rd_ack),
						.rdf_dout(rdf_dout),
						.sdram_rd_req(sdram_rd_req),
						.syswr_done(syswr_done),
						.tx_start(tx_start),					
						.wrf_use(wrf_use),
						.rdf_use(rdf_use),
						);	
						


datagene			uut_datagene(
						.clk_20m(clk_100m),
						.clk_100m(clk_100m),
						.rst_n(sys_rst_n),
						.wrf_din(wrf_din),
						.wrf_wrreq(wrf_wrreq),
						.moni_addr(sys_addr),
						.syswr_done(syswr_done),
						.sdram_rd_ack(sdram_rd_ack),
						.write(write),
						.index(index),
						.datain(dat)
					);


uart_ctrl		uut_uartctrl(
					.clk(clk_100m),
					.rst_n(sys_rst_n),
					.tx_data(rdf_dout[7:0]),
					.tx_start(tx_start),		
					.fifo232_rdreq(rdf_rdreq),
					.rs232_tx(rs232_tx)
					);
array    array(
	         .clk(clk_20m),
	         .write(write),
	         .index(index),
	         .dataout(dat)
);

endmodule
module sdr_test(
				rst_n,
				clk,
				clk_100m,
				sdram_clk,
				sdram_cke,
				sdram_cs_n,
				sdram_ras_n,
				sdram_cas_n,
				sdram_we_n,
				sdram_ba,
				sdram_addr,
				sdram_data,
				sdram_udqm,
				sdram_ldqm,	
				rs232_tx,
				tx_start,
				wrf_use,
				rdf_use,
			);


input 			clk;
input 			rst_n;
output 		clk_100m;
output 		sdram_clk;
output 		sdram_cke;
output 		sdram_cs_n;
output 		sdram_ras_n;
output 		sdram_cas_n;
output 		sdram_we_n;
output		[1:0] sdram_ba;
output		[12:0] sdram_addr;
output 		sdram_udqm;
output 		sdram_ldqm;
inout			[15:0] sdram_data;
output 		rs232_tx;
output 		tx_start;
output 		[8:0] wrf_use;
output 		[8:0] rdf_use;




wire sdram_wr_req;
wire sdram_rd_req;
wire sdram_wr_ack;
wire sdram_rd_ack;
wire[21:0] sys_addr;
wire[15:0] sys_data_in;

wire[15:0] sys_data_out;
wire sdram_busy;
wire sys_dout_rdy;


wire[15:0] wrf_din;
wire wrf_wrreq;

wire[15:0] rdf_dout;
wire rdf_rdreq;


wire clk_20m;
wire clk_100m;
wire sys_rst_n;
wire tx_start;

wire syswr_done;
wire [4:0] index;
wire  write;
wire [15:0] dat;


sys_ctrl		uut_sysctrl(
					.clk(clk),
					.rst_n(rst_n),
					.sys_rst_n(sys_rst_n),
					.clk_20m(clk_20m),
				   .clk_100m(clk_100m),
				   .sdram_clk(sdram_clk)
					);




sdram_top		uut_sdramtop(				
							.clk(clk_100m),
							.rst_n(sys_rst_n),
							.sdram_wr_req(sdram_wr_req),
							.sdram_rd_req(sdram_rd_req),
							.sdram_wr_ack(sdram_wr_ack),
							.sdram_rd_ack(sdram_rd_ack),	
							.sys_addr(sys_addr),
							.sys_data_in(sys_data_in),
							.sys_data_out(sys_data_out),
							.sdram_cke(sdram_cke),
							.sdram_cs_n(sdram_cs_n),
							.sdram_ras_n(sdram_ras_n),
							.sdram_cas_n(sdram_cas_n),
							.sdram_we_n(sdram_we_n),
							.sdram_ba(sdram_ba),
							.sdram_addr(sdram_addr),
							.sdram_data(sdram_data),
							.sdram_udqm(sdram_udqm),
							.sdram_ldqm(sdram_ldqm)
					);
	

sdfifo_ctrl			uut_sdffifoctrl(
						.clk_20m(clk_100m),
						.clk_100m(clk_100m),
						.wrf_din(wrf_din),
						.wrf_wrreq(wrf_wrreq),
						.sdram_wr_ack(sdram_wr_ack),					
						.sys_data_in(sys_data_in),
						.sdram_wr_req(sdram_wr_req),
						.sys_data_out(sys_data_out),
						.rdf_rdreq(rdf_rdreq),
						.sdram_rd_ack(sdram_rd_ack),
						.rdf_dout(rdf_dout),
						.sdram_rd_req(sdram_rd_req),
						.syswr_done(syswr_done),
						.tx_start(tx_start),					
						.wrf_use(wrf_use),
						.rdf_use(rdf_use),
						);	
						


datagene			uut_datagene(
						.clk_20m(clk_100m),
						.clk_100m(clk_100m),
						.rst_n(sys_rst_n),
						.wrf_din(wrf_din),
						.wrf_wrreq(wrf_wrreq),
						.moni_addr(sys_addr),
						.syswr_done(syswr_done),
						.sdram_rd_ack(sdram_rd_ack),
						.write(write),
						.index(index),
						.datain(dat)
					);


uart_ctrl		uut_uartctrl(
					.clk(clk_100m),
					.rst_n(sys_rst_n),
					.tx_data(rdf_dout[7:0]),
					.tx_start(tx_start),		
					.fifo232_rdreq(rdf_rdreq),
					.rs232_tx(rs232_tx)
					);
array    array(
	         .clk(clk_20m),
	         .write(write),
	         .index(index),
	         .dataout(dat)
);

endmodule