data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v
 line:72: before: "."
1: b'%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v:76: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v:78: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v:84: Signal definition not found, creating implicitly: \'two_ms\'\n           .timer_pulse(two_ms));\n                        ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v:314: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h1f\' generates 5 bits.\n                                                                                          : ... In instance fpga_top.joystick_inst\n         if (dataout_index == 5\'d31)  \n                           ^~\n%Error: data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v:66: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.v\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module fpga_top(

    output wire      CLK_OUT,
    output wire      MST_OUT_SLV_IN,
    input  wire      MST_IN_SLV_OUT,
    output wire      LOAD,
    input  wire      WF_CPU1,
    input  wire      WF_BUTTON
);




    reg [11:0] reds; 
    reg [11:0] greens; 
    reg        count83ms_pulse;
    reg [7:0]  seconds;
    reg [3:0]  count12;
    reg        count12_pulse;

    reg [11:0] circle_red;
    reg [11:0] circle_grn;
    reg [7:0]  slide_grn;
    reg [7:0]  slide_red;
    
   reg [5:0] count83ms;

   wire [7:0] slides;
   wire [4:0] joystick;





   wire      clk_en = 1'b1;
	

  SB_HFOSC OSC_i (
	    .CLKHFEN(clk_en),
	    .CLKHFPU(clk_en),
	    .CLKHF(clk));


   defparam OSC_i.CLKHF_DIV = "0b10";


  WF_timer #(.COUNT(119), .EVERY_CLK(1'b1)) ten_usec(
           .clk(clk),
           .enable(1'b1),
           .timer_pulse(ten_us));


     WF_timer #(.COUNT(199)) two_msec(
           .clk(clk),
           .enable(ten_us),
           .timer_pulse(two_ms));


     WF_joystick_board joystick_inst (
             .clk(clk),
             .scan_enable(two_ms),

             .slide_leds_red(slide_red),
             .slide_leds_green(slide_grn),
             .status_leds_red({joystick[2],joystick[1],joystick[4],joystick[0]}),
             .status_leds_blue(4'b000),
             .circle_leds_red(circle_red),
             .circle_leds_green(circle_grn),

             .slide_switches(slides),
             .joystick_switches(joystick),

             .header_outputs(slides),
             .header_inputs(),

             .LOAD(LOAD),
             .CLK_OUT(CLK_OUT),
             .MST_OUT_SLV_IN(MST_OUT_SLV_IN),
             .MST_IN_SLV_OUT(MST_IN_SLV_OUT) 
     );








   reg  [1:0] resets;
   always @ (posedge clk)
       if (resets == 2'b0)
         resets <= 2'b01;
        else
         resets <= {resets[0],resets[1]};

    wire second_mode = ~slides[2];


    always @ (posedge clk)
      if (resets==2'b0)
        begin
          reds   <= 12'hFFF;
          greens <= 12'h001;
        end
      else
        if (count83ms_pulse)
          greens <= second_mode ? {greens[10:0],1'b1} :
                                  {greens[10:0],greens[11]};
        else 
          if (count12_pulse && second_mode)
            greens <= 12'h001;

   wire [11:0] reds_wire = reds & ~greens;

  

    always @ (posedge clk)
      if (two_ms && ~joystick[3])
        count83ms <=count83ms + 'b1;
      else
        if (count83ms ==  42)
          begin
            count83ms <= 0;
            count83ms_pulse <= 1;
          end
        else
          count83ms_pulse <= 0;
           

    always @ (posedge clk)
      if  (count83ms_pulse)
        count12 <= count12 + 'b1;
      else
        if (count12 == 12)
          begin
            count12 <= 'b0;
            count12_pulse <= 1'b1;
          end
        else
          count12_pulse <= 1'b0;
          

    always @ (posedge clk)
      if (count12_pulse)
        seconds  <= seconds + 'b1;
        
          
    wire [1:0] mux_ctl = {slides[7],slides[0]};
       
    always @ (posedge clk)
      begin

        circle_red[11:0]  <= ~mux_ctl[0] ? greens      : reds_wire;
        circle_grn[11:0]  <= ~mux_ctl[0] ? reds_wire   : greens;

        slide_grn[7:0 ] <= mux_ctl[1] ? 
                       {seconds[0],seconds[1],seconds[2],seconds[3],
                        seconds[4],seconds[5],seconds[6],seconds[7]} : 8'h00;
        slide_red[7:0 ] <= mux_ctl[1] ? 8'h00 :
                       {seconds[0],seconds[1],seconds[2],seconds[3],
                        seconds[4],seconds[5],seconds[6],seconds[7]};
        end

endmodule
module fpga_top(

    output wire      CLK_OUT,
    output wire      MST_OUT_SLV_IN,
    input  wire      MST_IN_SLV_OUT,
    output wire      LOAD,
    input  wire      WF_CPU1,
    input  wire      WF_BUTTON
);





    reg [11:0] reds; 
    reg [11:0] greens; 
    reg        count83ms_pulse;
    reg [7:0]  seconds;
    reg [3:0]  count12;
    reg        count12_pulse;

    reg [11:0] circle_red;
    reg [11:0] circle_grn;
    reg [7:0]  slide_grn;
    reg [7:0]  slide_red;
    
   reg [5:0] count83ms;

   wire [7:0] slides;
   wire [4:0] joystick;





   wire      clk_en = 1'b1;
	

  SB_HFOSC OSC_i (
	    .CLKHFEN(clk_en),
	    .CLKHFPU(clk_en),
	    .CLKHF(clk));


   defparam OSC_i.CLKHF_DIV = "0b10";


  WF_timer #(.COUNT(119), .EVERY_CLK(1'b1)) ten_usec(
           .clk(clk),
           .enable(1'b1),
           .timer_pulse(ten_us));


     WF_timer #(.COUNT(199)) two_msec(
           .clk(clk),
           .enable(ten_us),
           .timer_pulse(two_ms));


     WF_joystick_board joystick_inst (
             .clk(clk),
             .scan_enable(two_ms),

             .slide_leds_red(slide_red),
             .slide_leds_green(slide_grn),
             .status_leds_red({joystick[2],joystick[1],joystick[4],joystick[0]}),
             .status_leds_blue(4'b000),
             .circle_leds_red(circle_red),
             .circle_leds_green(circle_grn),

             .slide_switches(slides),
             .joystick_switches(joystick),

             .header_outputs(slides),
             .header_inputs(),

             .LOAD(LOAD),
             .CLK_OUT(CLK_OUT),
             .MST_OUT_SLV_IN(MST_OUT_SLV_IN),
             .MST_IN_SLV_OUT(MST_IN_SLV_OUT) 
     );








   reg  [1:0] resets;
   always @ (posedge clk)
       if (resets == 2'b0)
         resets <= 2'b01;
        else
         resets <= {resets[0],resets[1]};

    wire second_mode = ~slides[2];


    always @ (posedge clk)
      if (resets==2'b0)
        begin
          reds   <= 12'hFFF;
          greens <= 12'h001;
        end
      else
        if (count83ms_pulse)
          greens <= second_mode ? {greens[10:0],1'b1} :
                                  {greens[10:0],greens[11]};
        else 
          if (count12_pulse && second_mode)
            greens <= 12'h001;

   wire [11:0] reds_wire = reds & ~greens;

  

    always @ (posedge clk)
      if (two_ms && ~joystick[3])
        count83ms <=count83ms + 'b1;
      else
        if (count83ms ==  42)
          begin
            count83ms <= 0;
            count83ms_pulse <= 1;
          end
        else
          count83ms_pulse <= 0;
           

    always @ (posedge clk)
      if  (count83ms_pulse)
        count12 <= count12 + 'b1;
      else
        if (count12 == 12)
          begin
            count12 <= 'b0;
            count12_pulse <= 1'b1;
          end
        else
          count12_pulse <= 1'b0;
          

    always @ (posedge clk)
      if (count12_pulse)
        seconds  <= seconds + 'b1;
        
          
    wire [1:0] mux_ctl = {slides[7],slides[0]};
       
    always @ (posedge clk)
      begin

        circle_red[11:0]  <= ~mux_ctl[0] ? greens      : reds_wire;
        circle_grn[11:0]  <= ~mux_ctl[0] ? reds_wire   : greens;

        slide_grn[7:0 ] <= mux_ctl[1] ? 
                       {seconds[0],seconds[1],seconds[2],seconds[3],
                        seconds[4],seconds[5],seconds[6],seconds[7]} : 8'h00;
        slide_red[7:0 ] <= mux_ctl[1] ? 8'h00 :
                       {seconds[0],seconds[1],seconds[2],seconds[3],
                        seconds[4],seconds[5],seconds[6],seconds[7]};
        end

endmodule