data/full_repos/permissive/141582589/src/common_rtl/video/line_buf_scaler.v
1: b"%Error: data/full_repos/permissive/141582589/src/common_rtl/video/line_buf_scaler.v:31: Cannot find file containing module: 'dp_ram'\ndp_ram#(.DATA_WIDTH(8),.MEM_SIZE(MEM_SIZE)) dp_ram_y\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/dp_ram\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/dp_ram.v\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/dp_ram.sv\n             dp_ram\n             dp_ram.v\n             dp_ram.sv\n             obj_dir/dp_ram\n             obj_dir/dp_ram.v\n             obj_dir/dp_ram.sv\n%Error: data/full_repos/permissive/141582589/src/common_rtl/video/line_buf_scaler.v:42: Cannot find file containing module: 'dp_ram'\ndp_ram#(.DATA_WIDTH(8),.MEM_SIZE(MEM_SIZE/2)) dp_ram_cr\n^~~~~~\n%Error: data/full_repos/permissive/141582589/src/common_rtl/video/line_buf_scaler.v:53: Cannot find file containing module: 'dp_ram'\ndp_ram#(.DATA_WIDTH(8),.MEM_SIZE(MEM_SIZE/2)) dp_ram_cb\n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module line_buf_scaler
#(
	parameter WITDH_2K = 0
)(
	data,
	rdaddress,
	rdclock,
	wraddress,
	wrclock,
	wren,
	q
);
	input	[15:0]  data;
	input	[10:0]  rdaddress;
	input	  rdclock;
	input	[10:0]  wraddress;
	input	  wrclock;
	input	  wren;
	output	[23:0]  q;
	wire [10:0] cr_rdaddress;
	assign cr_rdaddress = rdaddress;
localparam MEM_SIZE = WITDH_2K ? 2048 : 1024;
dp_ram#(.DATA_WIDTH(8),.MEM_SIZE(MEM_SIZE)) dp_ram_y
(
	.data(data[15:8]),
	.rdaddress(rdaddress),
	.rdclock(rdclock),
	.wraddress(wraddress),
	.wrclock(wrclock),
	.wren(wren),
	.q(q[23:16])
);

dp_ram#(.DATA_WIDTH(8),.MEM_SIZE(MEM_SIZE/2)) dp_ram_cr
(
	.data(data[7:0]),
	.rdaddress(cr_rdaddress[10:1]),
	.rdclock(rdclock),
	.wraddress(wraddress[10:1]),
	.wrclock(wrclock),
	.wren(wren & wraddress[0]),
	.q(q[7:0])
);

dp_ram#(.DATA_WIDTH(8),.MEM_SIZE(MEM_SIZE/2)) dp_ram_cb
(
	.data(data[7:0]),
	.rdaddress(rdaddress[10:1]),
	.rdclock(rdclock),
	.wraddress(wraddress[10:1]),
	.wrclock(wrclock),
	.wren(wren & ~wraddress[0]),
	.q(q[15:8])
);
	

endmodule
module line_buf_scaler
#(
	parameter WITDH_2K = 0
)(
	data,
	rdaddress,
	rdclock,
	wraddress,
	wrclock,
	wren,
	q
);

	input	[15:0]  data;
	input	[10:0]  rdaddress;
	input	  rdclock;
	input	[10:0]  wraddress;
	input	  wrclock;
	input	  wren;
	output	[23:0]  q;
	wire [10:0] cr_rdaddress;
	assign cr_rdaddress = rdaddress;
localparam MEM_SIZE = WITDH_2K ? 2048 : 1024;
dp_ram#(.DATA_WIDTH(8),.MEM_SIZE(MEM_SIZE)) dp_ram_y
(
	.data(data[15:8]),
	.rdaddress(rdaddress),
	.rdclock(rdclock),
	.wraddress(wraddress),
	.wrclock(wrclock),
	.wren(wren),
	.q(q[23:16])
);

dp_ram#(.DATA_WIDTH(8),.MEM_SIZE(MEM_SIZE/2)) dp_ram_cr
(
	.data(data[7:0]),
	.rdaddress(cr_rdaddress[10:1]),
	.rdclock(rdclock),
	.wraddress(wraddress[10:1]),
	.wrclock(wrclock),
	.wren(wren & wraddress[0]),
	.q(q[7:0])
);

dp_ram#(.DATA_WIDTH(8),.MEM_SIZE(MEM_SIZE/2)) dp_ram_cb
(
	.data(data[7:0]),
	.rdaddress(rdaddress[10:1]),
	.rdclock(rdclock),
	.wraddress(wraddress[10:1]),
	.wrclock(wrclock),
	.wren(wren & ~wraddress[0]),
	.q(q[15:8])
);
	

endmodule