data/full_repos/permissive/170402453/SMPS_ZVS/DCDCTest_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/170402453/SMPS_ZVS/DCDCTest_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/170402453/SMPS_ZVS/DCDCTest_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n always #2.5 clk=~clk;\n        ^\n%Error: data/full_repos/permissive/170402453/SMPS_ZVS/DCDCTest_tb.v:39: Cannot find file containing module: \'DCDCController\'\n DCDCController uut (\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170402453/SMPS_ZVS,data/full_repos/permissive/170402453/DCDCController\n             data/full_repos/permissive/170402453/SMPS_ZVS,data/full_repos/permissive/170402453/DCDCController.v\n             data/full_repos/permissive/170402453/SMPS_ZVS,data/full_repos/permissive/170402453/DCDCController.sv\n             DCDCController\n             DCDCController.v\n             DCDCController.sv\n             obj_dir/DCDCController\n             obj_dir/DCDCController.v\n             obj_dir/DCDCController.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DCDCTest_tb;


	reg clk;
	reg [15:0] voltageSet;
	reg [15:0] currentSet;
	reg [23:0] DCDC_VSense;
	reg [23:0] DCDC_CSense;


	wire DCDC_Driver;
	wire DCDC_CV;


	DCDCController uut (
		.clk(clk), 
		.voltageSet(voltageSet), 
		.currentSet(currentSet), 
		.DCDC_VSense(DCDC_VSense), 
		.DCDC_CSense(DCDC_CSense), 
		.DCDC_Driver(DCDC_Driver), 
		.DCDC_CV(DCDC_CV)
	);

	initial begin

		clk = 0;
		voltageSet = 0;
		currentSet = 0;
		DCDC_VSense = 0;
		DCDC_CSense = 0;


		#100;
        

		
		voltageSet = 35000;
		currentSet = 1000;
	end
	
	always #2.5 clk=~clk;
      
endmodule
module DCDCTest_tb;



	reg clk;
	reg [15:0] voltageSet;
	reg [15:0] currentSet;
	reg [23:0] DCDC_VSense;
	reg [23:0] DCDC_CSense;


	wire DCDC_Driver;
	wire DCDC_CV;


	DCDCController uut (
		.clk(clk), 
		.voltageSet(voltageSet), 
		.currentSet(currentSet), 
		.DCDC_VSense(DCDC_VSense), 
		.DCDC_CSense(DCDC_CSense), 
		.DCDC_Driver(DCDC_Driver), 
		.DCDC_CV(DCDC_CV)
	);

	initial begin

		clk = 0;
		voltageSet = 0;
		currentSet = 0;
		DCDC_VSense = 0;
		DCDC_CSense = 0;


		#100;
        

		
		voltageSet = 35000;
		currentSet = 1000;
	end
	
	always #2.5 clk=~clk;
      
endmodule