data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk=~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #101 rst <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #1000 push <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10 push <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #10 push <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #10 push <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #30 pop <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #20 pop <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #100 push <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #10 push <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #10 push <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #10 push <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #10 push <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n            #9 timeout = timeout + 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n            #1 if(!full)\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n            #9 timeout = timeout + 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:39: Can\'t find definition of \'linked_ram\' in dotted variable: \'dut.linked_ram\'\n            $display("%d : %d", i, dut.linked_ram[i]);\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:42: Can\'t find definition of \'r_beg\' in dotted variable: \'dut.r_beg\'\n            $display("%d : %d", i, dut.r_beg[i]);\n                                       ^~~~~\n%Error: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:45: Can\'t find definition of \'r_end\' in dotted variable: \'dut.r_end\'\n            $display("%d : %d", i, dut.r_end[i]);\n                                       ^~~~~\n%Error: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:139: Can\'t find definition of \'linked_ram\' in dotted variable: \'dut.linked_ram\'\n            linked_ram_delay[i] = dut.linked_ram[i];\n                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:141: Can\'t find definition of \'r_beg\' in dotted variable: \'dut.r_beg\'\n            r_beg_delay[i] = dut.r_beg[i];\n                                 ^~~~~\n%Error: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:143: Can\'t find definition of \'r_end\' in dotted variable: \'dut.r_end\'\n            r_end_delay[i] = dut.r_end[i];\n                                 ^~~~~\n%Error: data/full_repos/permissive/19478345/linked_fifo/linked_fifo_tb.v:146: Can\'t find definition of \'error\' in dotted variable: \'dut.error\'\n        if(dut.error == 1) begin\n               ^~~~~\n%Error: Exiting due to 7 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module linked_fifo_tb;
    `define WIDTH 8
    `define DEPTH 32
    `define FIFOS 8
    `define LOG2_FIFO log2(`FIFOS-1)
    reg rst, clk;
    reg push;
    reg [2:0] push_fifo;
    reg pop;
    reg [2:0] pop_fifo;
    reg [7:0] d;
    wire [7:0] q;
    wire empty;
    wire full;
    wire [3*8-1:0] count;
    wire [7:0] q_gold;
    wire empty_gold;
    wire full_gold;
    wire [3*8-1:0] count_gold;
    wire almost_full;


    linked_fifo #(`WIDTH, `DEPTH, `FIFOS) dut(rst, clk, push, push_fifo, pop, pop_fifo, d, q, empty, full,,almost_full);
    linked_fifo_gold #(`WIDTH, `DEPTH, `FIFOS) gold(rst, clk, push, push_fifo, pop, pop_fifo, d, q_gold, empty_gold, full_gold,);

    always @(posedge clk) begin


    end

    integer timeout;
    integer i;
    task print_linked_info;
    begin
        $display("linked_ram:");
        for(i = 0; i < 16; i = i + 1)
            $display("%d : %d", i, dut.linked_ram[i]);
        $display("r_beg:");
        for(i = 0; i < 8; i = i + 1)
            $display("%d : %d", i, dut.r_beg[i]);
        $display("r_end:");
        for(i = 0; i < 8; i = i + 1)
            $display("%d : %d", i, dut.r_end[i]);
    end
    endtask
    initial begin
        clk <= 0;
        forever #5 clk=~clk;
    end
    initial begin
        rst <= 1;
        push <= 0;
        push_fifo <= 0;
        pop <= 0;
        pop_fifo <= 0;
        d <= 0;
        #101 rst <= 0;
        #1000 push <= 1;
        $display("first push at %d", $time);
        d <= 5;
        #10 push <= 0;
        #10 push <= 1;
        d <= 6;
        #10 push <= 0;
        #30 pop <= 1;
        #20 pop <= 0;
        #100 push <= 1;
        push_fifo <= 1;
        d <= 1;
        #10 push <= 0;
        timeout = 0;
        #10 push <= 1;

        #10 push <= 0;
        $display("conituous push");
        while(!full && timeout != 64) begin
            push <= 1;
            #10;
            timeout = timeout+1;
        end
        $display("conituous push end");
        push <= 0;
        push_fifo <= 1;
        d <= 1;
        #10 push <= 0;
        timeout = 0;
        $display("conituous push");
        while(!full && timeout != 8) begin
            push <= 1;
            #10;
            timeout = timeout+1;
        end
        $display("conituous push end");
        timeout = 0;
        while(timeout != 8*64) begin
            pop_fifo = pop_fifo + 1;
            #1;
            if(!empty)
                pop = 1;
            else
                pop = 0;
            #9 timeout = timeout + 1;
        end
        timeout = 0;
        while(timeout != 1000*1000) begin
            pop_fifo = $random;
            push_fifo = $random;
            d = $random;
            #1 if(!full)
                push = $random;
            else
                push = 0;
            if(!empty)
                pop = $random;
            else
                pop = 0;
            #9 timeout = timeout + 1;
        end
        #100;
        $display("finished NO ERRORS");
        $finish;
    end

    reg [6:0] linked_ram_delay [0:2**6 - 1];
    reg [3:0] r_beg_delay [0:7];
    reg [3:0] r_end_delay [0:7];
    reg pop_delay;
    reg push_delay;
    reg full_delay;
    reg empty_delay;
    always @(posedge clk) begin
        pop_delay <= pop;
        push_delay <= push;
        full_delay <= full;
        empty_delay <= empty;
        for(i = 0; i < 2**6; i = i + 1)
            linked_ram_delay[i] = dut.linked_ram[i];
        for(i = 0; i < 8; i = i + 1)
            r_beg_delay[i] = dut.r_beg[i];
        for(i = 0; i < 8; i = i + 1)
            r_end_delay[i] = dut.r_end[i];
    end
    always @(posedge clk) begin
        if(dut.error == 1) begin
            $display("ERROR:");
            $display("delayed:");
            $display("pop_delay: %H", pop_delay);
            $display("push_delay: %H", push_delay);
            $display("full_delay: %H", full_delay);
            $display("empty_delay: %H", empty_delay);
            $display("current:");
            print_linked_info();
            
            $finish;
        end
    end

    always @(posedge clk) begin
        if(pop_delay && q != q_gold) begin
            $display("ERROR: output does not match gold model at %d", $time);
            $display("GOLD: %d ACTUAL: %d", q_gold, q);
        end
        if(pop_delay) begin

        end
    end
endmodule
module linked_fifo_tb;

    `define WIDTH 8
    `define DEPTH 32
    `define FIFOS 8
    `define LOG2_FIFO log2(`FIFOS-1)
    reg rst, clk;
    reg push;
    reg [2:0] push_fifo;
    reg pop;
    reg [2:0] pop_fifo;
    reg [7:0] d;
    wire [7:0] q;
    wire empty;
    wire full;
    wire [3*8-1:0] count;
    wire [7:0] q_gold;
    wire empty_gold;
    wire full_gold;
    wire [3*8-1:0] count_gold;
    wire almost_full;


    linked_fifo #(`WIDTH, `DEPTH, `FIFOS) dut(rst, clk, push, push_fifo, pop, pop_fifo, d, q, empty, full,,almost_full);
    linked_fifo_gold #(`WIDTH, `DEPTH, `FIFOS) gold(rst, clk, push, push_fifo, pop, pop_fifo, d, q_gold, empty_gold, full_gold,);

    always @(posedge clk) begin


    end

    integer timeout;
    integer i;
    task print_linked_info;
    begin
        $display("linked_ram:");
        for(i = 0; i < 16; i = i + 1)
            $display("%d : %d", i, dut.linked_ram[i]);
        $display("r_beg:");
        for(i = 0; i < 8; i = i + 1)
            $display("%d : %d", i, dut.r_beg[i]);
        $display("r_end:");
        for(i = 0; i < 8; i = i + 1)
            $display("%d : %d", i, dut.r_end[i]);
    end
    endtask
    initial begin
        clk <= 0;
        forever #5 clk=~clk;
    end
    initial begin
        rst <= 1;
        push <= 0;
        push_fifo <= 0;
        pop <= 0;
        pop_fifo <= 0;
        d <= 0;
        #101 rst <= 0;
        #1000 push <= 1;
        $display("first push at %d", $time);
        d <= 5;
        #10 push <= 0;
        #10 push <= 1;
        d <= 6;
        #10 push <= 0;
        #30 pop <= 1;
        #20 pop <= 0;
        #100 push <= 1;
        push_fifo <= 1;
        d <= 1;
        #10 push <= 0;
        timeout = 0;
        #10 push <= 1;

        #10 push <= 0;
        $display("conituous push");
        while(!full && timeout != 64) begin
            push <= 1;
            #10;
            timeout = timeout+1;
        end
        $display("conituous push end");
        push <= 0;
        push_fifo <= 1;
        d <= 1;
        #10 push <= 0;
        timeout = 0;
        $display("conituous push");
        while(!full && timeout != 8) begin
            push <= 1;
            #10;
            timeout = timeout+1;
        end
        $display("conituous push end");
        timeout = 0;
        while(timeout != 8*64) begin
            pop_fifo = pop_fifo + 1;
            #1;
            if(!empty)
                pop = 1;
            else
                pop = 0;
            #9 timeout = timeout + 1;
        end
        timeout = 0;
        while(timeout != 1000*1000) begin
            pop_fifo = $random;
            push_fifo = $random;
            d = $random;
            #1 if(!full)
                push = $random;
            else
                push = 0;
            if(!empty)
                pop = $random;
            else
                pop = 0;
            #9 timeout = timeout + 1;
        end
        #100;
        $display("finished NO ERRORS");
        $finish;
    end

    reg [6:0] linked_ram_delay [0:2**6 - 1];
    reg [3:0] r_beg_delay [0:7];
    reg [3:0] r_end_delay [0:7];
    reg pop_delay;
    reg push_delay;
    reg full_delay;
    reg empty_delay;
    always @(posedge clk) begin
        pop_delay <= pop;
        push_delay <= push;
        full_delay <= full;
        empty_delay <= empty;
        for(i = 0; i < 2**6; i = i + 1)
            linked_ram_delay[i] = dut.linked_ram[i];
        for(i = 0; i < 8; i = i + 1)
            r_beg_delay[i] = dut.r_beg[i];
        for(i = 0; i < 8; i = i + 1)
            r_end_delay[i] = dut.r_end[i];
    end
    always @(posedge clk) begin
        if(dut.error == 1) begin
            $display("ERROR:");
            $display("delayed:");
            $display("pop_delay: %H", pop_delay);
            $display("push_delay: %H", push_delay);
            $display("full_delay: %H", full_delay);
            $display("empty_delay: %H", empty_delay);
            $display("current:");
            print_linked_info();
            
            $finish;
        end
    end

    always @(posedge clk) begin
        if(pop_delay && q != q_gold) begin
            $display("ERROR: output does not match gold model at %d", $time);
            $display("GOLD: %d ACTUAL: %d", q_gold, q);
        end
        if(pop_delay) begin

        end
    end
endmodule