data/full_repos/permissive/152129793/comun/modulos.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:576: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.los_interruptores\n  wire [7:0] posx = hc - XINIT;   \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:577: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.los_interruptores\n  wire [7:0] posy = vc - YINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:503: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_leds\n  wire [7:0] pos = hc - XINIT;   \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:399: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n    posicion_caracter_en_pantalla = (hc - XINIT + 1)>>4;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:403: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n  wire [7:0] posx = hc - XINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:404: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n  wire [7:0] posy = vc - YINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:436: Bit extraction of array[127:0] requires 7 bit index, not 8 bits.\n                                                                        : ... In instance display.display_digitos\n        scan_actual <= chars[charaddr];\n                            ^\n%Warning-UNSIGNED: data/full_repos/permissive/152129793/comun/modulos.v:216: Comparison is constant due to unsigned arithmetic\n                                                                           : ... In instance display.sincronismos\n    if (hcont>=0 && hcont<HACTIVE && vcont>=0 && vcont<VACTIVE)\n             ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152129793/comun/modulos.v:216: Comparison is constant due to unsigned arithmetic\n                                                                           : ... In instance display.sincronismos\n    if (hcont>=0 && hcont<HACTIVE && vcont>=0 && vcont<VACTIVE)\n                                          ^~\n%Error: Exiting due to 9 warning(s)\n'
module leds (

  input wire [7:0] led,


  input wire [10:0] hc,
  input wire [10:0] vc,
  output reg [5:0] r,
  output reg [5:0] g,
  output reg [5:0] b
  );
  
  parameter YINIT = 424;
  
  localparam COLOR_LED_ON  = {6'h3F, 6'h3F, 6'h1F};
  localparam COLOR_LED_OFF = {6'h10, 6'h00, 6'h00};
  
  localparam ANCHO = 8*16 + 7*16;
  localparam XINIT = (640 - ANCHO) / 2;
  localparam XFIN  = XINIT + ANCHO - 1;
  localparam YFIN  = YINIT + 5;
  
  wire [7:0] pos = hc - XINIT;
  always @* begin
    if (hc >= XINIT && hc <= XFIN && vc >= YINIT && vc <= YFIN) begin
      if (pos[4] == 1'b0)
        if (led[~pos[7:5]] == 1'b1)
          {r,g,b} = COLOR_LED_ON;
        else
          {r,g,b} = COLOR_LED_OFF;
      else
        {r,g,b} = 18'h00000;
    end
    else
      {r,g,b} = 18'h00000;
  end
endmodule
module leds (

  input wire [7:0] led,


  input wire [10:0] hc,
  input wire [10:0] vc,
  output reg [5:0] r,
  output reg [5:0] g,
  output reg [5:0] b
  );

  
  parameter YINIT = 424;
  
  localparam COLOR_LED_ON  = {6'h3F, 6'h3F, 6'h1F};
  localparam COLOR_LED_OFF = {6'h10, 6'h00, 6'h00};
  
  localparam ANCHO = 8*16 + 7*16;
  localparam XINIT = (640 - ANCHO) / 2;
  localparam XFIN  = XINIT + ANCHO - 1;
  localparam YFIN  = YINIT + 5;
  
  wire [7:0] pos = hc - XINIT;
  always @* begin
    if (hc >= XINIT && hc <= XFIN && vc >= YINIT && vc <= YFIN) begin
      if (pos[4] == 1'b0)
        if (led[~pos[7:5]] == 1'b1)
          {r,g,b} = COLOR_LED_ON;
        else
          {r,g,b} = COLOR_LED_OFF;
      else
        {r,g,b} = 18'h00000;
    end
    else
      {r,g,b} = 18'h00000;
  end
endmodule