data/full_repos/permissive/193790231/lab01/lab01part01.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193790231/lab01/lab01part01.v:12: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab01/lab01part01.v:14: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab01/lab01part01.v:16: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab01/lab01part01.v:18: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testBenchT01;
	reg [17:0]sw;
	wire[17:0]ld;
	
	lab01part01 testingLab1Task1(sw, ld);
	initial begin
	#100;
	sw = 18'b000000000000000000;
	#100;
	sw = 18'b000000000000000001;
	#100;
	sw = 18'b000000000000001111;
	#100;
	end
	
endmodule
module testBenchT01;

	reg [17:0]sw;
	wire[17:0]ld;
	
	lab01part01 testingLab1Task1(sw, ld);
	initial begin
	#100;
	sw = 18'b000000000000000000;
	#100;
	sw = 18'b000000000000000001;
	#100;
	sw = 18'b000000000000001111;
	#100;
	end
	
endmodule