data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tmp/tb_RAM_sing_async.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tmp/tb_RAM_sing_async.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD/2) \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tmp/tb_RAM_sing_async.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*3);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tmp/tb_RAM_sing_async.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*3);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tmp/tb_RAM_sing_async.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*3);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tmp/tb_RAM_sing_async.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tmp/tb_RAM_sing_async.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*3);\n        ^\n%Error: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tmp/tb_RAM_sing_async.v:19: Cannot find file containing module: \'RAM_sing_async\'\n    RAM_sing_async utt(\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tmp,data/full_repos/permissive/212763527/RAM_sing_async\n             data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tmp,data/full_repos/permissive/212763527/RAM_sing_async.v\n             data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tmp,data/full_repos/permissive/212763527/RAM_sing_async.sv\n             RAM_sing_async\n             RAM_sing_async.v\n             RAM_sing_async.sv\n             obj_dir/RAM_sing_async\n             obj_dir/RAM_sing_async.v\n             obj_dir/RAM_sing_async.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_RAM_sing_async;

    reg clk;


    reg [7:0] data_in;
    reg [2:0] addr;
    reg we;


    wire [7:0] data_out;

    initial begin
        clk = 0;
    end
    
    RAM_sing_async utt(
        data_in,
        addr,
        clk,
        we,
        data_out
    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin
        we = 1'b1;

        data_in = 8'h0_0;
        addr = 0;
        
        #(CLK_PERIOD*3);

        data_in = 8'h0_1;
        addr = 1;

        #(CLK_PERIOD*3);

        we = 1'b0;
        addr = 0;

        #(CLK_PERIOD*3);

        #3;

        addr = 1;

        #(CLK_PERIOD*3);

        $finish;
    end

endmodule
module tb_RAM_sing_async;


    reg clk;


    reg [7:0] data_in;
    reg [2:0] addr;
    reg we;


    wire [7:0] data_out;

    initial begin
        clk = 0;
    end
    
    RAM_sing_async utt(
        data_in,
        addr,
        clk,
        we,
        data_out
    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin
        we = 1'b1;

        data_in = 8'h0_0;
        addr = 0;
        
        #(CLK_PERIOD*3);

        data_in = 8'h0_1;
        addr = 1;

        #(CLK_PERIOD*3);

        we = 1'b0;
        addr = 0;

        #(CLK_PERIOD*3);

        #3;

        addr = 1;

        #(CLK_PERIOD*3);

        $finish;
    end

endmodule