data/full_repos/permissive/191811344/src/milenet5/verilog/Version naïve/HDL/Convolution_v1_0.v
 line:179: before: ","
1: b'%Error: Cannot find file containing module: na\xc3\xafve/HDL,data/full_repos/permissive/191811344\n        ... Looked in:\n             data/full_repos/permissive/191811344/src/milenet5/verilog/Version/na\xc3\xafve/HDL,data/full_repos/permissive/191811344\n             data/full_repos/permissive/191811344/src/milenet5/verilog/Version/na\xc3\xafve/HDL,data/full_repos/permissive/191811344.v\n             data/full_repos/permissive/191811344/src/milenet5/verilog/Version/na\xc3\xafve/HDL,data/full_repos/permissive/191811344.sv\n             na\xc3\xafve/HDL,data/full_repos/permissive/191811344\n             na\xc3\xafve/HDL,data/full_repos/permissive/191811344.v\n             na\xc3\xafve/HDL,data/full_repos/permissive/191811344.sv\n             obj_dir/na\xc3\xafve/HDL,data/full_repos/permissive/191811344\n             obj_dir/na\xc3\xafve/HDL,data/full_repos/permissive/191811344.v\n             obj_dir/na\xc3\xafve/HDL,data/full_repos/permissive/191811344.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/191811344/src/milenet5/verilog/Version\n%Error: Cannot find file containing module: na\xc3\xafve/HDL/Convolution_v1_0.v\n%Error: Exiting due to 3 error(s)\n'
module SRAM #
(
    parameter ADDR_WIDTH = 8, DEPTH = 256
)
(
    input wire i_clk,
    input wire [ADDR_WIDTH-1:0] i_addr, 
    input wire i_write,
    input wire [31:0] i_data,
    output reg [31:0] o_data 
);
    
    reg [31:0] memory_array [0:DEPTH-1]; 
    
    always @ (posedge i_clk)
    begin
        if(i_write) begin
            memory_array[i_addr] <= i_data;
        end
        else begin
            o_data <= memory_array[i_addr];
        end     
    end
endmodule
module SRAM #
(
    parameter ADDR_WIDTH = 8, DEPTH = 256
)
(
    input wire i_clk,
    input wire [ADDR_WIDTH-1:0] i_addr, 
    input wire i_write,
    input wire [31:0] i_data,
    output reg [31:0] o_data 
);

    
    reg [31:0] memory_array [0:DEPTH-1]; 
    
    always @ (posedge i_clk)
    begin
        if(i_write) begin
            memory_array[i_addr] <= i_data;
        end
        else begin
            o_data <= memory_array[i_addr];
        end     
    end
endmodule