data/full_repos/permissive/125531440/core/src/main/verilog/loopback/chnl_tester.v
 line:57: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/chnl_tester.v:129: Operator DIV expects 32 bits on the LHS, but LHS\'s VARREF \'C_PCI_DATA_WIDTH\' generates 9 bits.\n                                                                                                     : ... In instance chnl_tester\n    rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);\n                                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/chnl_tester.v:137: Operator DIV expects 32 bits on the LHS, but LHS\'s VARREF \'C_PCI_DATA_WIDTH\' generates 9 bits.\n                                                                                                     : ... In instance chnl_tester\n   rCount <= #1 (C_PCI_DATA_WIDTH/32);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/chnl_tester.v:149: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                                     : ... In instance chnl_tester\n                                stop_cnt <= stop_cnt + 2\'b10;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/chnl_tester.v:153: Operator DIV expects 32 bits on the LHS, but LHS\'s VARREF \'C_PCI_DATA_WIDTH\' generates 9 bits.\n                                                                                                     : ... In instance chnl_tester\n    rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);\n                                           ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/chnl_tester.v:183: Extracting 64 bits from only 32 bit number\n                                                                                             : ... In instance chnl_tester\nassign rData[63:0] = ram_data_out;\n            ^\n%Warning-SELRANGE: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/chnl_tester.v:183: Selection index out of range: 63:0 outside 31:0\n                                                                                                        : ... In instance chnl_tester\nassign rData[63:0] = ram_data_out;\n            ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/chnl_tester.v:185: Cannot find file containing module: \'sp_mem_8192x64\'\nsp_mem_8192x64 u_sp_mem_8192x64(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/sp_mem_8192x64\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/sp_mem_8192x64.v\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/sp_mem_8192x64.sv\n             sp_mem_8192x64\n             sp_mem_8192x64.v\n             sp_mem_8192x64.sv\n             obj_dir/sp_mem_8192x64\n             obj_dir/sp_mem_8192x64.v\n             obj_dir/sp_mem_8192x64.sv\n%Error: Exiting due to 2 error(s), 5 warning(s)\n'
module chnl_tester #(
	parameter C_PCI_DATA_WIDTH = 9'd32
)
(
	input CLK,
	input RST,
	output CHNL_RX_CLK, 
(* mark_debug = "true" *)   input CHNL_RX, 
(* mark_debug = "true" *)   output CHNL_RX_ACK, 
(* mark_debug = "true" *)   input CHNL_RX_LAST, 
(* mark_debug = "true" *)   input [31:0] CHNL_RX_LEN, 
(* mark_debug = "true" *)   input [30:0] CHNL_RX_OFF, 
(* mark_debug = "true" *)   input [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA, 
(* mark_debug = "true" *)   input CHNL_RX_DATA_VALID, 
(* mark_debug = "true" *)   output CHNL_RX_DATA_REN,

output CHNL_TX_CLK, 
(* mark_debug = "true" *)   output CHNL_TX, 
(* mark_debug = "true" *)   input CHNL_TX_ACK, 
(* mark_debug = "true" *)   output CHNL_TX_LAST, 
(* mark_debug = "true" *)   output [31:0] CHNL_TX_LEN, 
(* mark_debug = "true" *)   output [30:0] CHNL_TX_OFF, 
(* mark_debug = "true" *)   output [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA, 
(* mark_debug = "true" *)   output CHNL_TX_DATA_VALID, 
(* mark_debug = "true" *)   input CHNL_TX_DATA_REN
);


wire [C_PCI_DATA_WIDTH-1:0] rData;
reg [31:0] rLen=0;
(* mark_debug = "true" *) reg [31:0] rCount=0;
reg [1:0] rState=0;
reg [1:0] rState_d1;
(* mark_debug = "true" *) reg [12:0] data_cnt;
wire [63:0] ram_data_out;
reg chnl_tx_data_ren_d1;
reg chnl_tx_data_ren_d2;
reg chnl_tx_data_valid_d1;
(* mark_debug = "true" *) reg [31:0] stop_cnt;
(* mark_debug = "true" *) wire [31:0] tx_end;

assign CHNL_RX_CLK = CLK;
assign CHNL_RX_ACK = (rState == 2'd1);
assign CHNL_RX_DATA_REN = (rState == 2'd1);

assign CHNL_TX_CLK = CLK;
assign CHNL_TX = (rState == 2'd3);
assign CHNL_TX_LAST = 1'd1;
assign CHNL_TX_LEN = rLen;
assign CHNL_TX_OFF = 0;
assign CHNL_TX_DATA = rData;

assign CHNL_TX_DATA_VALID = chnl_tx_data_ren_d1;

always @(posedge CLK or posedge RST) begin
	if (RST) begin
		rLen <= #1 0;
		rCount <= #1 0;
		rState <= #1 0;

                data_cnt <= 0;
                stop_cnt <= 0;
	end
	else begin
		case (rState)
		
		2'd0: begin
			if (CHNL_RX) begin
				rLen <= #1 CHNL_RX_LEN;
				rCount <= #1 0;
				rState <= #1 2'd1;
                                data_cnt <= 0;
                                stop_cnt <= 0;
			end
		end
		
		2'd1: begin
			if (CHNL_RX_DATA_VALID) begin

				rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);
                                data_cnt <= #1 data_cnt + 1'b1;
			end
			if (rCount >= rLen)
				rState <= #1 2'd2;
		end

		2'd2: begin
			rCount <= #1 (C_PCI_DATA_WIDTH/32);
			rState <= #1 2'd3;
                        data_cnt <= 0;
		end

		2'd3: begin

			if (CHNL_TX_DATA_REN) begin
                                data_cnt <= #1 data_cnt + 1'b1;
			end
                        else if (~CHNL_TX_DATA_REN&chnl_tx_data_ren_d1) begin
                                data_cnt <= #1 data_cnt - 1'b1;
                                stop_cnt <= stop_cnt + 2'b10;
                        end
			if (chnl_tx_data_ren_d1) begin

				rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);

				if (rCount >= tx_end)
					rState <= #1 2'd0;
			end
		end
		
		endcase
	end
end


assign tx_end = rLen + stop_cnt;

always @(posedge CLK or posedge RST)
	if (RST) begin
                rState_d1 <= 0;
                chnl_tx_data_ren_d1 <= 0;
                chnl_tx_data_ren_d2 <= 0;
                chnl_tx_data_valid_d1 <= 0;
        end
        else begin
                rState_d1 <= rState;
                chnl_tx_data_ren_d1 <= CHNL_TX_DATA_REN;
                chnl_tx_data_ren_d2 <= chnl_tx_data_ren_d1;
                chnl_tx_data_valid_d1 <= CHNL_TX_DATA_VALID;
        end



assign rData[63:0] = ram_data_out;

sp_mem_8192x64 u_sp_mem_8192x64(

        .clka(CLK),
        .ena(1'b1),
        .wea(CHNL_RX_DATA_VALID),
        .addra(data_cnt),
        .dina(CHNL_RX_DATA),
        .douta(ram_data_out)

);




endmodule
module chnl_tester #(
	parameter C_PCI_DATA_WIDTH = 9'd32
)
(
	input CLK,
	input RST,
	output CHNL_RX_CLK, 
(* mark_debug = "true" *)   input CHNL_RX, 
(* mark_debug = "true" *)   output CHNL_RX_ACK, 
(* mark_debug = "true" *)   input CHNL_RX_LAST, 
(* mark_debug = "true" *)   input [31:0] CHNL_RX_LEN, 
(* mark_debug = "true" *)   input [30:0] CHNL_RX_OFF, 
(* mark_debug = "true" *)   input [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA, 
(* mark_debug = "true" *)   input CHNL_RX_DATA_VALID, 
(* mark_debug = "true" *)   output CHNL_RX_DATA_REN,

output CHNL_TX_CLK, 
(* mark_debug = "true" *)   output CHNL_TX, 
(* mark_debug = "true" *)   input CHNL_TX_ACK, 
(* mark_debug = "true" *)   output CHNL_TX_LAST, 
(* mark_debug = "true" *)   output [31:0] CHNL_TX_LEN, 
(* mark_debug = "true" *)   output [30:0] CHNL_TX_OFF, 
(* mark_debug = "true" *)   output [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA, 
(* mark_debug = "true" *)   output CHNL_TX_DATA_VALID, 
(* mark_debug = "true" *)   input CHNL_TX_DATA_REN
);



wire [C_PCI_DATA_WIDTH-1:0] rData;
reg [31:0] rLen=0;
(* mark_debug = "true" *) reg [31:0] rCount=0;
reg [1:0] rState=0;
reg [1:0] rState_d1;
(* mark_debug = "true" *) reg [12:0] data_cnt;
wire [63:0] ram_data_out;
reg chnl_tx_data_ren_d1;
reg chnl_tx_data_ren_d2;
reg chnl_tx_data_valid_d1;
(* mark_debug = "true" *) reg [31:0] stop_cnt;
(* mark_debug = "true" *) wire [31:0] tx_end;

assign CHNL_RX_CLK = CLK;
assign CHNL_RX_ACK = (rState == 2'd1);
assign CHNL_RX_DATA_REN = (rState == 2'd1);

assign CHNL_TX_CLK = CLK;
assign CHNL_TX = (rState == 2'd3);
assign CHNL_TX_LAST = 1'd1;
assign CHNL_TX_LEN = rLen;
assign CHNL_TX_OFF = 0;
assign CHNL_TX_DATA = rData;

assign CHNL_TX_DATA_VALID = chnl_tx_data_ren_d1;

always @(posedge CLK or posedge RST) begin
	if (RST) begin
		rLen <= #1 0;
		rCount <= #1 0;
		rState <= #1 0;

                data_cnt <= 0;
                stop_cnt <= 0;
	end
	else begin
		case (rState)
		
		2'd0: begin
			if (CHNL_RX) begin
				rLen <= #1 CHNL_RX_LEN;
				rCount <= #1 0;
				rState <= #1 2'd1;
                                data_cnt <= 0;
                                stop_cnt <= 0;
			end
		end
		
		2'd1: begin
			if (CHNL_RX_DATA_VALID) begin

				rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);
                                data_cnt <= #1 data_cnt + 1'b1;
			end
			if (rCount >= rLen)
				rState <= #1 2'd2;
		end

		2'd2: begin
			rCount <= #1 (C_PCI_DATA_WIDTH/32);
			rState <= #1 2'd3;
                        data_cnt <= 0;
		end

		2'd3: begin

			if (CHNL_TX_DATA_REN) begin
                                data_cnt <= #1 data_cnt + 1'b1;
			end
                        else if (~CHNL_TX_DATA_REN&chnl_tx_data_ren_d1) begin
                                data_cnt <= #1 data_cnt - 1'b1;
                                stop_cnt <= stop_cnt + 2'b10;
                        end
			if (chnl_tx_data_ren_d1) begin

				rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);

				if (rCount >= tx_end)
					rState <= #1 2'd0;
			end
		end
		
		endcase
	end
end


assign tx_end = rLen + stop_cnt;

always @(posedge CLK or posedge RST)
	if (RST) begin
                rState_d1 <= 0;
                chnl_tx_data_ren_d1 <= 0;
                chnl_tx_data_ren_d2 <= 0;
                chnl_tx_data_valid_d1 <= 0;
        end
        else begin
                rState_d1 <= rState;
                chnl_tx_data_ren_d1 <= CHNL_TX_DATA_REN;
                chnl_tx_data_ren_d2 <= chnl_tx_data_ren_d1;
                chnl_tx_data_valid_d1 <= CHNL_TX_DATA_VALID;
        end



assign rData[63:0] = ram_data_out;

sp_mem_8192x64 u_sp_mem_8192x64(

        .clka(CLK),
        .ena(1'b1),
        .wea(CHNL_RX_DATA_VALID),
        .addra(data_cnt),
        .dina(CHNL_RX_DATA),
        .douta(ram_data_out)

);




endmodule