data/full_repos/permissive/175132042/tasks/uart_tasks.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:13: Cannot find include file: simulation_includes.vh\n`include "simulation_includes.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/tasks,data/full_repos/permissive/175132042/simulation_includes.vh\n             data/full_repos/permissive/175132042/tasks,data/full_repos/permissive/175132042/simulation_includes.vh.v\n             data/full_repos/permissive/175132042/tasks,data/full_repos/permissive/175132042/simulation_includes.vh.sv\n             simulation_includes.vh\n             simulation_includes.vh.v\n             simulation_includes.vh.sv\n             obj_dir/simulation_includes.vh\n             obj_dir/simulation_includes.vh.v\n             obj_dir/simulation_includes.vh.sv\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:24: syntax error, unexpected \'@\'\n         @(posedge `UART_CLK);\n         ^\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:24: Define or directive not defined: \'`UART_CLK\'\n         @(posedge `UART_CLK);\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:26: Define or directive not defined: \'`UART_MASTER0\'\n         `UART_MASTER0.wb_wr1(32\'hFFFF0001,    4\'h4, 32\'h00010000);\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:28: Define or directive not defined: \'`UART_CLK\'\n         @(posedge `UART_CLK);\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:30: Define or directive not defined: \'`UART_MASTER0\'\n         `UART_MASTER0.wb_wr1(32\'hFFFF0002,    4\'h2, 32\'h00000700);\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:32: Define or directive not defined: \'`UART_CLK\'\n         @(posedge `UART_CLK);\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:34: Define or directive not defined: \'`UART_MASTER0\'\n         `UART_MASTER0.wb_wr1(32\'hFFFF0003,    4\'h1, 32\'h00000080);\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:36: Define or directive not defined: \'`UART_CLK\'\n         @(posedge `UART_CLK);\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:38: Define or directive not defined: \'`UART_MASTER0\'\n         `UART_MASTER0.wb_wr1(32\'hFFFF0000,    4\'h0, 32\'h0000001A);  \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:40: Define or directive not defined: \'`UART_CLK\'\n         @(posedge `UART_CLK);\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:42: Define or directive not defined: \'`UART_MASTER0\'\n         `UART_MASTER0.wb_wr1(32\'hFFFF0001,    4\'h4, 32\'h00000000);\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:44: Define or directive not defined: \'`UART_CLK\'\n         @(posedge `UART_CLK);\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:46: Define or directive not defined: \'`UART_MASTER0\'\n         `UART_MASTER0.wb_wr1(32\'hFFFF0003,    4\'h1, 32\'h00000003);\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:61: syntax error, unexpected \'@\'\n         @(posedge `UART_CLK);\n         ^\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:61: Define or directive not defined: \'`UART_CLK\'\n         @(posedge `UART_CLK);\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:63: Define or directive not defined: \'`UART_MASTER0\'\n         `UART_MASTER0.wb_wr1(32\'hFFFF0000,    4\'h8, {char, 24\'h000000});\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:63: syntax error, unexpected \'.\'\n         `UART_MASTER0.wb_wr1(32\'hFFFF0000,    4\'h8, {char, 24\'h000000});\n                      ^\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:76: syntax error, unexpected \'@\'\n           @(posedge testbench.uart0_int);\n           ^\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:78: Define or directive not defined: \'`UART_MASTER0\'\n         `UART_MASTER0.wb_rd1(32\'hFFFF0000,    4\'h8, testbench.read_word);\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:83: Define or directive not defined: \'`TEST_FAILED\'\n              `TEST_FAILED <= 1;\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/tasks/uart_tasks.v:83: syntax error, unexpected <=\n              `TEST_FAILED <= 1;\n                           ^~\n%Error: Exiting due to 22 error(s)\n'
module uart_tasks;



   task uart_config;
      begin

         $display("\033[93mTASK: UART Configure\033[0m");

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0001,    4'h4, 32'h00010000);

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0002,    4'h2, 32'h00000700);

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0003,    4'h1, 32'h00000080);

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0000,    4'h0, 32'h0000001A);

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0001,    4'h4, 32'h00000000);

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0003,    4'h1, 32'h00000003);
      end
   endtask





   task uart_write_char;
      input [7:0] char;
      begin




         @(posedge `UART_CLK);
         $display("TASK: UART Write = %c @ %d", char, $time);
         `UART_MASTER0.wb_wr1(32'hFFFF0000,    4'h8, {char, 24'h000000});
      end
   endtask




   task uart_read_char;
      input [7:0] expected;
      begin
         $display("Reading 0x%x @ %d", expected, $time);
         
         if (!testbench.uart0_int)
           @(posedge testbench.uart0_int);
         
         `UART_MASTER0.wb_rd1(32'hFFFF0000,    4'h8, testbench.read_word);
         $display("TASK: UART Read = %c @ %d", testbench.read_word[31:24], $time);
         if (testbench.read_word[31:24] !== expected)
           begin
              $display("\033[1;31mFAIL: UART Read = 0x%h NOT 0x%h @ %d\033[0m", testbench.read_word[31:24], expected, $time);
              `TEST_FAILED <= 1;
           end
         @(posedge testbench.wb_clk);         
      end      
   endtask



endmodule
module uart_tasks;




   task uart_config;
      begin

         $display("\033[93mTASK: UART Configure\033[0m");

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0001,    4'h4, 32'h00010000);

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0002,    4'h2, 32'h00000700);

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0003,    4'h1, 32'h00000080);

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0000,    4'h0, 32'h0000001A);

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0001,    4'h4, 32'h00000000);

         @(posedge `UART_CLK);

         `UART_MASTER0.wb_wr1(32'hFFFF0003,    4'h1, 32'h00000003);
      end
   endtask





   task uart_write_char;
      input [7:0] char;
      begin




         @(posedge `UART_CLK);
         $display("TASK: UART Write = %c @ %d", char, $time);
         `UART_MASTER0.wb_wr1(32'hFFFF0000,    4'h8, {char, 24'h000000});
      end
   endtask




   task uart_read_char;
      input [7:0] expected;
      begin
         $display("Reading 0x%x @ %d", expected, $time);
         
         if (!testbench.uart0_int)
           @(posedge testbench.uart0_int);
         
         `UART_MASTER0.wb_rd1(32'hFFFF0000,    4'h8, testbench.read_word);
         $display("TASK: UART Read = %c @ %d", testbench.read_word[31:24], $time);
         if (testbench.read_word[31:24] !== expected)
           begin
              $display("\033[1;31mFAIL: UART Read = 0x%h NOT 0x%h @ %d\033[0m", testbench.read_word[31:24], expected, $time);
              `TEST_FAILED <= 1;
           end
         @(posedge testbench.wb_clk);         
      end      
   endtask



endmodule