data/full_repos/permissive/106408053/verilog/gray.v
 line:47: before: "prototypes"
1: b"%Error: data/full_repos/permissive/106408053/verilog/gray.v:84: Can't find definition of variable: 'WIDTH'\nfunction [WIDTH-1:0] gray2bin;\n          ^~~~~\n%Error: Exiting due to 1 error(s)\n"
function [WIDTH-1:0] bin2gray;
input [WIDTH-1:0] bin;
integer i;
begin

  for (i=0; i<WIDTH-1; i=i+1) bin2gray[i] = bin[i+1] ^ bin[i];
  bin2gray[WIDTH-1] = bin[WIDTH-1];
end
endfunction
function [WIDTH-1:0] bin2gray;

input [WIDTH-1:0] bin;
integer i;
begin

  for (i=0; i<WIDTH-1; i=i+1) bin2gray[i] = bin[i+1] ^ bin[i];
  bin2gray[WIDTH-1] = bin[WIDTH-1];
end
endfunction