data/full_repos/permissive/123304708/src/datapath/pc.v
data/verilator_xmls/a7992623-2ed0-4b93-a00c-71f14fe1636a.xml
module pc (
    input clk,
    input isPCWrite,

    input[31:0] data,
    output [31:0] PC
);
  reg[31:0] currentPC;
  initial
    currentPC = 32'h3000; 
  

    always @(posedge clk) 
    begin

            if(isPCWrite)
                currentPC = data[31:0];














    end

  assign PC = currentPC;
endmodule
module pc (
    input clk,
    input isPCWrite,

    input[31:0] data,
    output [31:0] PC
);

  reg[31:0] currentPC;
  initial
    currentPC = 32'h3000; 
  

    always @(posedge clk) 
    begin

            if(isPCWrite)
                currentPC = data[31:0];














    end

  assign PC = currentPC;
endmodule