data/full_repos/permissive/111993107/src/hms.v
data/verilator_xmls/8e98e030-7194-4f8a-aa98-71618cad396c.xml
module COUPLER #(parameter                           E_LOG = 2,
                 parameter                           DATW  = 64)
                (input  wire                         CLK,
                 input  wire                         RST,
                 input  wire                         IN_FULL,
                 input  wire [(DATW<<(E_LOG-1))-1:0] DIN,
                 input  wire                         DINEN,
                 output wire [(DATW<<E_LOG)-1:0]     DOT,
                 output wire                         DOTEN);


  reg stall; 
  always @(posedge CLK) stall <= IN_FULL;
  
  reg [(DATW<<E_LOG)-1:0] record_buf;
  reg                     record_buf_cnt;
  reg                     record_buf_en;
  
  always @(posedge CLK) begin
    if (DINEN) record_buf <= {DIN, record_buf[(DATW<<E_LOG)-1:(DATW<<(E_LOG-1))]};
  end
  always @(posedge CLK) begin
    if      (RST)   record_buf_cnt <= 0;
    else if (DINEN) record_buf_cnt <= ~record_buf_cnt;
  end
  always @(posedge CLK) if (!stall) record_buf_en <= &{DINEN, record_buf_cnt};


  assign DOT   = record_buf;
  assign DOTEN = &{record_buf_en, (~stall)};
  
endmodule
module COUPLER #(parameter                           E_LOG = 2,
                 parameter                           DATW  = 64)
                (input  wire                         CLK,
                 input  wire                         RST,
                 input  wire                         IN_FULL,
                 input  wire [(DATW<<(E_LOG-1))-1:0] DIN,
                 input  wire                         DINEN,
                 output wire [(DATW<<E_LOG)-1:0]     DOT,
                 output wire                         DOTEN);



  reg stall; 
  always @(posedge CLK) stall <= IN_FULL;
  
  reg [(DATW<<E_LOG)-1:0] record_buf;
  reg                     record_buf_cnt;
  reg                     record_buf_en;
  
  always @(posedge CLK) begin
    if (DINEN) record_buf <= {DIN, record_buf[(DATW<<E_LOG)-1:(DATW<<(E_LOG-1))]};
  end
  always @(posedge CLK) begin
    if      (RST)   record_buf_cnt <= 0;
    else if (DINEN) record_buf_cnt <= ~record_buf_cnt;
  end
  always @(posedge CLK) if (!stall) record_buf_en <= &{DINEN, record_buf_cnt};


  assign DOT   = record_buf;
  assign DOTEN = &{record_buf_en, (~stall)};
  
endmodule