data/full_repos/permissive/160156109/mips-work/testIFU.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160156109/mips-work/testIFU.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #5 reset = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160156109/mips-work/testIFU.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #5 reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160156109/mips-work/testIFU.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #20 clk =~ clk;\n    ^\n%Error: data/full_repos/permissive/160156109/mips-work/testIFU.v:8: Cannot find file containing module: \'ifu\'\n  ifu ifu1(clk, reset, nPC_sel, zero, ins, jumpCtr, tarAddr);\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/160156109/mips-work,data/full_repos/permissive/160156109/ifu\n             data/full_repos/permissive/160156109/mips-work,data/full_repos/permissive/160156109/ifu.v\n             data/full_repos/permissive/160156109/mips-work,data/full_repos/permissive/160156109/ifu.sv\n             ifu\n             ifu.v\n             ifu.sv\n             obj_dir/ifu\n             obj_dir/ifu.v\n             obj_dir/ifu.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testIFU;

  reg clk, reset, nPC_sel, zero, jumpCtr;
  wire [31:0] ins;
  reg [25:0] tarAddr;


  ifu ifu1(clk, reset, nPC_sel, zero, ins, jumpCtr, tarAddr);

  initial
  begin
    clk = 0;
    #5 reset = 0;
    #5 reset = 1;
  end

  always
    #20 clk =~ clk;

endmodule
module testIFU;


  reg clk, reset, nPC_sel, zero, jumpCtr;
  wire [31:0] ins;
  reg [25:0] tarAddr;


  ifu ifu1(clk, reset, nPC_sel, zero, ins, jumpCtr, tarAddr);

  initial
  begin
    clk = 0;
    #5 reset = 0;
    #5 reset = 1;
  end

  always
    #20 clk =~ clk;

endmodule