data/full_repos/permissive/184108896/fw_dummy.v
 line:134: before: "/"
1: b'%Error: data/full_repos/permissive/184108896/fw_dummy.v:16: Cannot find include file: params.v\n`include "params.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/184108896,data/full_repos/permissive/184108896/params.v\n             data/full_repos/permissive/184108896,data/full_repos/permissive/184108896/params.v.v\n             data/full_repos/permissive/184108896,data/full_repos/permissive/184108896/params.v.sv\n             params.v\n             params.v.v\n             params.v.sv\n             obj_dir/params.v\n             obj_dir/params.v.v\n             obj_dir/params.v.sv\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:35: Define or directive not defined: \'`L\'\ninput [`L*`WIDTH-1 : 0] inD;\n       ^~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:35: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\ninput [`L*`WIDTH-1 : 0] inD;\n         ^\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:35: Define or directive not defined: \'`WIDTH\'\ninput [`L*`WIDTH-1 : 0] inD;\n          ^~~~~~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:38: Define or directive not defined: \'`L\'\noutput [`L*`WIDTH-1 : 0] outD;\n        ^~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:38: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\noutput [`L*`WIDTH-1 : 0] outD;\n          ^\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:38: Define or directive not defined: \'`WIDTH\'\noutput [`L*`WIDTH-1 : 0] outD;\n           ^~~~~~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:41: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1 : 0] outD;\n     ^~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:41: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1 : 0] outD;\n       ^\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:41: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1 : 0] outD;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:42: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1 : 0] outD1;\n     ^~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:42: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1 : 0] outD1;\n       ^\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:42: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1 : 0] outD1;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:43: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1 : 0] outD2;\n     ^~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:43: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1 : 0] outD2;\n       ^\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:43: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1 : 0] outD2;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:44: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1 : 0] outD3;\n     ^~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:44: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1 : 0] outD3;\n       ^\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:44: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1 : 0] outD3;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:45: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1 : 0] outD4;\n     ^~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:45: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1 : 0] outD4;\n       ^\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:45: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1 : 0] outD4;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:46: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1 : 0] outD5;\n     ^~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:46: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1 : 0] outD5;\n       ^\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:46: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1 : 0] outD5;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:47: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1 : 0] outD6;\n     ^~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:47: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1 : 0] outD6;\n       ^\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:47: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1 : 0] outD6;\n        ^~~~~~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:48: Define or directive not defined: \'`L\'\nreg [`L*`WIDTH-1 : 0] outD7;\n     ^~\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:48: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\nreg [`L*`WIDTH-1 : 0] outD7;\n       ^\n%Error: data/full_repos/permissive/184108896/fw_dummy.v:48: Define or directive not defined: \'`WIDTH\'\nreg [`L*`WIDTH-1 : 0] outD7;\n        ^~~~~~\n%Error: Exiting due to 31 error(s)\n'
module fw(

	clk,
	reset,
	enable,
	inhibit,
	phase,

	inD,
	in_valid,

	outD,
	out_valid
);


input clk, reset, enable, in_valid, inhibit;
input [`L*`WIDTH-1 : 0] inD;
input [1:0] phase;

output [`L*`WIDTH-1 : 0] outD;
output out_valid;

reg [`L*`WIDTH-1 : 0] outD;
reg [`L*`WIDTH-1 : 0] outD1;
reg [`L*`WIDTH-1 : 0] outD2;
reg [`L*`WIDTH-1 : 0] outD3;
reg [`L*`WIDTH-1 : 0] outD4;
reg [`L*`WIDTH-1 : 0] outD5;
reg [`L*`WIDTH-1 : 0] outD6;
reg [`L*`WIDTH-1 : 0] outD7;
reg out_valid = 1'b0;
reg out_valid1 = 1'b0;
reg out_valid2 = 1'b0;
reg out_valid3 = 1'b0;
reg out_valid4 = 1'b0;
reg out_valid5 = 1'b0;
reg out_valid6 = 1'b0;
reg out_valid7 = 1'b0;


always @(posedge clk)
begin
	if (reset)
	begin
		out_valid <= 0;
	end
	else
	begin
		outD1 <= inD;
		outD2 <= outD1;
		outD3 <= outD2;
		outD4 <= outD3;
		outD5 <= outD4;
		outD6 <= outD5;
		outD7 <= outD6;
		outD  <= outD7;
		out_valid1 <= in_valid;
		out_valid2 <= out_valid1;
		out_valid3 <= out_valid2;
		out_valid4 <= out_valid3;
		out_valid5 <= out_valid4;
		out_valid6 <= out_valid5;
		out_valid7 <= out_valid6;
		out_valid  <= out_valid7;
	end
end

endmodule
module fw(

	clk,
	reset,
	enable,
	inhibit,
	phase,

	inD,
	in_valid,

	outD,
	out_valid
);



input clk, reset, enable, in_valid, inhibit;
input [`L*`WIDTH-1 : 0] inD;
input [1:0] phase;

output [`L*`WIDTH-1 : 0] outD;
output out_valid;

reg [`L*`WIDTH-1 : 0] outD;
reg [`L*`WIDTH-1 : 0] outD1;
reg [`L*`WIDTH-1 : 0] outD2;
reg [`L*`WIDTH-1 : 0] outD3;
reg [`L*`WIDTH-1 : 0] outD4;
reg [`L*`WIDTH-1 : 0] outD5;
reg [`L*`WIDTH-1 : 0] outD6;
reg [`L*`WIDTH-1 : 0] outD7;
reg out_valid = 1'b0;
reg out_valid1 = 1'b0;
reg out_valid2 = 1'b0;
reg out_valid3 = 1'b0;
reg out_valid4 = 1'b0;
reg out_valid5 = 1'b0;
reg out_valid6 = 1'b0;
reg out_valid7 = 1'b0;


always @(posedge clk)
begin
	if (reset)
	begin
		out_valid <= 0;
	end
	else
	begin
		outD1 <= inD;
		outD2 <= outD1;
		outD3 <= outD2;
		outD4 <= outD3;
		outD5 <= outD4;
		outD6 <= outD5;
		outD7 <= outD6;
		outD  <= outD7;
		out_valid1 <= in_valid;
		out_valid2 <= out_valid1;
		out_valid3 <= out_valid2;
		out_valid4 <= out_valid3;
		out_valid5 <= out_valid4;
		out_valid6 <= out_valid5;
		out_valid7 <= out_valid6;
		out_valid  <= out_valid7;
	end
end

endmodule