data/full_repos/permissive/151863926/src/clock_divider.v
 line:13: before: "integer"
1: b'%Error: data/full_repos/permissive/151863926/src/clock_divider.v:8: Cannot find include file: auxilary_functions.v\n    `include "auxilary_functions.v" \n             ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151863926/src,data/full_repos/permissive/151863926/auxilary_functions.v\n             data/full_repos/permissive/151863926/src,data/full_repos/permissive/151863926/auxilary_functions.v.v\n             data/full_repos/permissive/151863926/src,data/full_repos/permissive/151863926/auxilary_functions.v.sv\n             auxilary_functions.v\n             auxilary_functions.v.v\n             auxilary_functions.v.sv\n             obj_dir/auxilary_functions.v\n             obj_dir/auxilary_functions.v.v\n             obj_dir/auxilary_functions.v.sv\n%Error: Exiting due to 1 error(s)\n'
module clock_divider
(
    input clk_in,
    input rst,
    output reg clk_out
);

    `include "auxilary_functions.v"

    parameter divisor = 10;
    
    reg  [base2(divisor)-1:0] cnt = 0;
    
    always @(posedge clk_in) begin
        if (rst) begin
            cnt <= 0;
            clk_out <= 0;
        end
        else begin
            if (cnt >= divisor-1) begin
                cnt <= 0;
            end
            else begin
                cnt <= cnt + 1;
            end
            
            clk_out <= (cnt >= divisor/2);
        end
    end
    
endmodule
module clock_divider
(
    input clk_in,
    input rst,
    output reg clk_out
);


    `include "auxilary_functions.v"

    parameter divisor = 10;
    
    reg  [base2(divisor)-1:0] cnt = 0;
    
    always @(posedge clk_in) begin
        if (rst) begin
            cnt <= 0;
            clk_out <= 0;
        end
        else begin
            if (cnt >= divisor-1) begin
                cnt <= 0;
            end
            else begin
                cnt <= cnt + 1;
            end
            
            clk_out <= (cnt >= divisor/2);
        end
    end
    
endmodule