data/full_repos/permissive/207646620/MIPS_PIPELINE_FPGA/Modulos/PC.v
data/verilator_xmls/4ba0964a-8ddd-41ba-91f7-e568df31f95e.xml
module Pipeline_PC (entrada,saida,clk,reset,PC_Freeze);
  input[31:0]entrada;
  input clk,reset,PC_Freeze;
  output reg[31:0] saida;

  always @ (posedge clk) begin
    if(reset)begin
      saida <= 32'b0;
    end
    else begin
      saida = (PC_Freeze == 0) ? entrada : saida;
    end
  end

endmodule
module Pipeline_PC (entrada,saida,clk,reset,PC_Freeze);

  input[31:0]entrada;
  input clk,reset,PC_Freeze;
  output reg[31:0] saida;

  always @ (posedge clk) begin
    if(reset)begin
      saida <= 32'b0;
    end
    else begin
      saida = (PC_Freeze == 0) ? entrada : saida;
    end
  end

endmodule