data/full_repos/permissive/174155074/basic-code/sequential-logic/d-flip-flop/d-flip-flop.v
data/verilator_xmls/79f2da0a-4459-4f7a-ad19-107dd4a472ad.xml
module d_flip_flop (
    input       clk,
    input       en,
    input       d,
    output reg  q,
    output      q_bar
);

assign q_bar = ~q;


always @ (posedge clk) begin
    if (en) begin
        q <= d;
    end else begin
        q <= q;
    end
end

endmodule
module d_flip_flop (
    input       clk,
    input       en,
    input       d,
    output reg  q,
    output      q_bar
);


assign q_bar = ~q;


always @ (posedge clk) begin
    if (en) begin
        q <= d;
    end else begin
        q <= q;
    end
end

endmodule