data/full_repos/permissive/13953309/NW_vc_input_port.v
 line:47: before: "data_in"
1: b'%Error: data/full_repos/permissive/13953309/NW_vc_input_port.v:55: Cannot find include file: NW_functions.v\n   `include "NW_functions.v" \n            ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13953309,data/full_repos/permissive/13953309/NW_functions.v\n             data/full_repos/permissive/13953309,data/full_repos/permissive/13953309/NW_functions.v.v\n             data/full_repos/permissive/13953309,data/full_repos/permissive/13953309/NW_functions.v.sv\n             NW_functions.v\n             NW_functions.v.v\n             NW_functions.v.sv\n             obj_dir/NW_functions.v\n             obj_dir/NW_functions.v.v\n             obj_dir/NW_functions.v.sv\n%Error: data/full_repos/permissive/13953309/NW_vc_input_port.v:47: syntax error, unexpected IDENTIFIER, expecting \';\'\n   input  flit_t data_in;\n                 ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_vc_input_port.v:48: syntax error, unexpected IDENTIFIER, expecting \';\'\n   output flit_t data_out;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_vc_input_port.v:49: syntax error, unexpected IDENTIFIER, expecting \';\'\n   output output_port_t output_port [num_vcs-1:0];\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_vc_input_port.v:50: syntax error, unexpected IDENTIFIER, expecting \';\'\n   output flit_t data_in_reg;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_vc_input_port.v:52: syntax error, unexpected IDENTIFIER, expecting \';\'\n   output flit_t flit_buffer_out [num_vcs-1:0];\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_vc_input_port.v:61: syntax error, unexpected IDENTIFIER, expecting \';\'\n   output fifov_flags_t flags [num_vcs-1:0];\n                        ^~~~~\n%Error: Exiting due to 7 error(s)\n'
module NW_vc_input_port(push, pop, data_in, vc_id, select, data_out, output_port, data_in_reg, 
			flags, buf_finished_empty, 

			allocated_vc, allocated_vc_valid,

			vc_new, vc_new_valid,
			head_is_tail,
			flit_buffer_out, 
			clk, rst_n);


   parameter num_vcs = 4;
   

   parameter buffer_length = 8;


   parameter pipelined_vc_switch_alloc = 0;

   parameter explicit_pipe_registers = 0;

   input  push, clk, rst_n;
   input  [num_vcs-1:0] pop;
   input  flit_t data_in;
   output flit_t data_out;
   output output_port_t output_port [num_vcs-1:0];
   output flit_t data_in_reg;
   output [num_vcs-1:0] head_is_tail;
   output flit_t flit_buffer_out [num_vcs-1:0];
   output [num_vcs-1:0] buf_finished_empty;
   
   `include "NW_functions.v"

   input [clogb2(num_vcs)-1:0] vc_id;

   input [num_vcs-1:0] select;

   output fifov_flags_t flags [num_vcs-1:0];
   output [num_vcs-1:0] allocated_vc [num_vcs-1:0];
   output [num_vcs-1:0] allocated_vc_valid;
	 
   input [num_vcs-1:0][num_vcs-1:0] vc_new;
   input [num_vcs-1:0] 	vc_new_valid;

   logic [num_vcs-1:0] vc_reg [num_vcs-1:0];
   logic [num_vcs-1:0] allocated_vc_valid;

   flit_t buffer_data_out, routed;

   logic [clogb2(num_vcs)-1:0] select_bin;

   logic sel_allocated_vc_valid;
   logic [num_vcs-1:0] sel_vc_reg, sel_vc_new;
   
   integer i;
   genvar vc;

   assign select_bin = vc_index_t'(oh2bin(select));
   






   NW_vc_buffers #(.size(buffer_length),
		   .n(num_vcs),

		   .output_all_head_flits(1)) vc_bufsi
     (.push(push), .pop(pop), .data_in(data_in), .vc_id(vc_id), .select(select), 
      .data_out(buffer_data_out), .output_port(output_port), .data_in_reg(data_in_reg), 
      .flags(flags), .buf_finished_empty(buf_finished_empty),
      .head_is_tail(head_is_tail),
      .flit_buffer_out(flit_buffer_out), 
      .clk, .rst_n);

   generate
   for (vc=0; vc<num_vcs; vc++) begin:eachvc

      if ((pipelined_vc_switch_alloc)&&(!explicit_pipe_registers)) begin




	 assign allocated_vc[vc] = vc_reg[vc];
	 
      end else begin
	 

	 assign allocated_vc[vc] = vc_reg[vc];
      end
   end
   endgenerate

   always@(posedge clk) begin
      if (!rst_n) begin
	 for (i=0; i<num_vcs; i++) begin

	    allocated_vc_valid[i]<=1'b0;
	 end
      end else begin



	 



	 
	 for (i=0; i<num_vcs; i++) begin

	    if (flit_buffer_out[i].control.tail && pop[i]) begin



	       allocated_vc_valid[i]<=1'b0;
	       vc_reg[i]<='0;
	    end else begin



	       
	       if (vc_new_valid[i]) begin




		  allocated_vc_valid[i]<=1'b1;
		  vc_reg[i]<=vc_new[i];

		  assert (vc_new[i]!='0) else begin
		     $display ("New VC id. is blank?"); $fatal;
		  end
	       end
	    end
	 end
      end
   end


   assign sel_allocated_vc_valid = |(allocated_vc_valid & select);



   
   generate
      if (!explicit_pipe_registers) begin
	 NW_route rfn (.flit_in(buffer_data_out), .flit_out(routed), .clk, .rst_n);
	 
	 always_comb
	   begin
	      data_out = routed;

	      data_out.control.vc_id = (sel_allocated_vc_valid) ? vc_reg[select_bin] : vc_new[select_bin]; 
	      



	   end
      end
   endgenerate

endmodule
module NW_vc_input_port(push, pop, data_in, vc_id, select, data_out, output_port, data_in_reg, 
			flags, buf_finished_empty, 

			allocated_vc, allocated_vc_valid,

			vc_new, vc_new_valid,
			head_is_tail,
			flit_buffer_out, 
			clk, rst_n);



   parameter num_vcs = 4;
   

   parameter buffer_length = 8;


   parameter pipelined_vc_switch_alloc = 0;

   parameter explicit_pipe_registers = 0;

   input  push, clk, rst_n;
   input  [num_vcs-1:0] pop;
   input  flit_t data_in;
   output flit_t data_out;
   output output_port_t output_port [num_vcs-1:0];
   output flit_t data_in_reg;
   output [num_vcs-1:0] head_is_tail;
   output flit_t flit_buffer_out [num_vcs-1:0];
   output [num_vcs-1:0] buf_finished_empty;
   
   `include "NW_functions.v"

   input [clogb2(num_vcs)-1:0] vc_id;

   input [num_vcs-1:0] select;

   output fifov_flags_t flags [num_vcs-1:0];
   output [num_vcs-1:0] allocated_vc [num_vcs-1:0];
   output [num_vcs-1:0] allocated_vc_valid;
	 
   input [num_vcs-1:0][num_vcs-1:0] vc_new;
   input [num_vcs-1:0] 	vc_new_valid;

   logic [num_vcs-1:0] vc_reg [num_vcs-1:0];
   logic [num_vcs-1:0] allocated_vc_valid;

   flit_t buffer_data_out, routed;

   logic [clogb2(num_vcs)-1:0] select_bin;

   logic sel_allocated_vc_valid;
   logic [num_vcs-1:0] sel_vc_reg, sel_vc_new;
   
   integer i;
   genvar vc;

   assign select_bin = vc_index_t'(oh2bin(select));
   






   NW_vc_buffers #(.size(buffer_length),
		   .n(num_vcs),

		   .output_all_head_flits(1)) vc_bufsi
     (.push(push), .pop(pop), .data_in(data_in), .vc_id(vc_id), .select(select), 
      .data_out(buffer_data_out), .output_port(output_port), .data_in_reg(data_in_reg), 
      .flags(flags), .buf_finished_empty(buf_finished_empty),
      .head_is_tail(head_is_tail),
      .flit_buffer_out(flit_buffer_out), 
      .clk, .rst_n);

   generate
   for (vc=0; vc<num_vcs; vc++) begin:eachvc

      if ((pipelined_vc_switch_alloc)&&(!explicit_pipe_registers)) begin




	 assign allocated_vc[vc] = vc_reg[vc];
	 
      end else begin
	 

	 assign allocated_vc[vc] = vc_reg[vc];
      end
   end
   endgenerate

   always@(posedge clk) begin
      if (!rst_n) begin
	 for (i=0; i<num_vcs; i++) begin

	    allocated_vc_valid[i]<=1'b0;
	 end
      end else begin



	 



	 
	 for (i=0; i<num_vcs; i++) begin

	    if (flit_buffer_out[i].control.tail && pop[i]) begin



	       allocated_vc_valid[i]<=1'b0;
	       vc_reg[i]<='0;
	    end else begin



	       
	       if (vc_new_valid[i]) begin




		  allocated_vc_valid[i]<=1'b1;
		  vc_reg[i]<=vc_new[i];

		  assert (vc_new[i]!='0) else begin
		     $display ("New VC id. is blank?"); $fatal;
		  end
	       end
	    end
	 end
      end
   end


   assign sel_allocated_vc_valid = |(allocated_vc_valid & select);



   
   generate
      if (!explicit_pipe_registers) begin
	 NW_route rfn (.flit_in(buffer_data_out), .flit_out(routed), .clk, .rst_n);
	 
	 always_comb
	   begin
	      data_out = routed;

	      data_out.control.vc_id = (sel_allocated_vc_valid) ? vc_reg[select_bin] : vc_new[select_bin]; 
	      



	   end
      end
   endgenerate

endmodule