data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Reciprocal/Reciprocal_Pipelined.v
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1: b'%Error: Cannot find file containing module: Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Reciprocal/Reciprocal_Pipelined.v\n%Error: Exiting due to 3 error(s)\n'
module Reciprocal_Pipelined_ItoNR_unfold

		#(parameter 

						
						
						WL = 24,
						LUT_bits = 9,
						LUT_addWidth = 3,
						dWL = 27,
						dWL_s2 = 15,
						m = LUT_addWidth + 1,
						WLO = 25
						
		 ) 		

		(
			input CLK,
			input nRST,
			input CE,
			     
			input [WL-1:0] din,

			output [WLO-1:0] dout
		);
		

		wire [WL-1:0] 				  din_delay;
		reg  [LUT_bits   : 0]     LUT [2**LUT_addWidth-1 : 0];
		reg  [LUT_bits-1 : 0]	  B1;
		reg  [LUT_bits : 0]	  	  B1_real;
		wire [LUT_addWidth-1:0]   reg_cmp;
		reg  [WL-1 : 0]			  xHat;
		wire [LUT_bits+2-1 : 0]   iniValue, iniValue_delay;
		wire [dWL_s2-1 : 0]  	  mul2_net, mul3_net, mul3_net_delay;
		wire [dWL-1		: 0]  	  mul4_net;
		reg  [dWL-1		: 0]  	  mul4_net_r;
		reg  [dWL_s2-1 : 0]  	  mul2_net_r, mul2_net_r_delay;
		wire [dWL+dWL_s2-1 : 0]   Mul;






		assign reg_cmp = din[WL-2 : WL-1-LUT_addWidth];
		always @* begin
			if(~nRST) begin
					mul2_net_r <= 0;
					B1 <= 0;
					B1_real <= 0;
					xHat <= 0;
			end
			else begin
				if (CE) begin
					B1 <= LUT[reg_cmp];
					B1_real[LUT_bits-1 : 0] <= B1;
					B1_real[LUT_bits] <= 1'b0;
					xHat[WL-1:WL-m] <=  din[WL-1:WL-m];
					xHat[WL-(m+1):0] <= ~din[WL-(m+1):0];
					mul2_net_r <= ~mul2_net;
					mul4_net_r <= ~mul4_net;
				end
			end
		end

mult_unsigned #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(LUT_bits), .WIO(1), .WFO(LUT_bits+2-1)) multiplier_1 
				   (.CLK(CLK), .RST(nRST), .in1(xHat), .in2(B1_real), .out(iniValue));
				   
mult_unsigned_pipe #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(LUT_bits+2-1), .WIO(1), .WFO(dWL_s2-1)) multiplier_2 
				   (.CLK(CLK), .RST(nRST), .in1(din), .in2(iniValue), .out(mul2_net));
				   
mult_unsigned_pipe #(.WI1(1), .WF1(dWL_s2-1), .WI2(1), .WF2(LUT_bits+2-1), .WIO(1), .WFO(dWL_s2-1)) multiplier_3 
				   (.CLK(CLK), .RST(nRST), .in1(mul2_net_r), .in2(iniValue_delay), .out(mul3_net));

mult_unsigned_pipe #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(dWL_s2-1), .WIO(1), .WFO(dWL-1)) multiplier_4
				   (.CLK(CLK), .RST(nRST), .in1(din_delay), .in2(mul3_net), .out(mul4_net));

mult_unsigned_pipe #(.WI1(1), .WF1(dWL-1), .WI2(1), .WF2(dWL_s2-1), .WIO(1), .WFO(dWL+dWL_s2-1)) multiplier_5 
				   (.CLK(CLK), .RST(nRST), .in1(mul4_net_r), .in2(mul3_net_delay), .out(Mul));


		ux_round2nearest
			#(
				.WordLength(dWL+dWL_s2),
				.RoundLength(dWL+dWL_s2 - WLO)
			 )
		round_0 
			(
				.CLK(CLK),
				.RESET(nRST),
				.CE(CE),
				.x(Mul),
				.y(dout)
			 );


	localparam PIP_iniValue = 2;
	localparam PIP_din	= 4;
	localparam PIP_mul3_net = 2;
	reg [LUT_bits+2-1 : 0] buffer_iniValue [1: PIP_iniValue];
	reg [WL-1  : 0] buffer_din [1: PIP_din];
	reg [dWL_s2-1 : 0] buffer_mul3_net [1: PIP_mul3_net];
	integer i;
	
	always @(posedge CLK) begin
		if (!nRST) begin
			for (i=1; i<=PIP_iniValue; i=i+1)
				buffer_iniValue[i] <= 0;
				
			for (i=1; i<=PIP_din; i=i+1)
				buffer_din[i] <= 0;

			for (i=1; i<=PIP_mul3_net; i=i+1)
				buffer_mul3_net[i] <= 0;
				
		end else begin
			buffer_iniValue[1] <= iniValue;
			for (i=2; i<=PIP_iniValue; i=i+1)
				buffer_iniValue[i] <= buffer_iniValue[i-1];
				
			buffer_din[1] <= din;
			for (i=2; i<=PIP_din; i=i+1)
				buffer_din[i] <= buffer_din[i-1];

			buffer_mul3_net[1] <= mul3_net;
			for (i=2; i<=PIP_mul3_net; i=i+1)
				buffer_mul3_net[i] <= buffer_mul3_net[i-1];
		end
	end

	assign iniValue_delay = buffer_iniValue[PIP_iniValue];
	assign din_delay = buffer_din[PIP_din];
	assign mul3_net_delay = buffer_mul3_net[PIP_mul3_net];

endmodule
module Reciprocal_Pipelined_ItoNR_unfold

		#(parameter 

						
						
						WL = 24,
						LUT_bits = 9,
						LUT_addWidth = 3,
						dWL = 27,
						dWL_s2 = 15,
						m = LUT_addWidth + 1,
						WLO = 25
						
		 ) 		

		(
			input CLK,
			input nRST,
			input CE,
			     
			input [WL-1:0] din,

			output [WLO-1:0] dout
		);

		

		wire [WL-1:0] 				  din_delay;
		reg  [LUT_bits   : 0]     LUT [2**LUT_addWidth-1 : 0];
		reg  [LUT_bits-1 : 0]	  B1;
		reg  [LUT_bits : 0]	  	  B1_real;
		wire [LUT_addWidth-1:0]   reg_cmp;
		reg  [WL-1 : 0]			  xHat;
		wire [LUT_bits+2-1 : 0]   iniValue, iniValue_delay;
		wire [dWL_s2-1 : 0]  	  mul2_net, mul3_net, mul3_net_delay;
		wire [dWL-1		: 0]  	  mul4_net;
		reg  [dWL-1		: 0]  	  mul4_net_r;
		reg  [dWL_s2-1 : 0]  	  mul2_net_r, mul2_net_r_delay;
		wire [dWL+dWL_s2-1 : 0]   Mul;






		assign reg_cmp = din[WL-2 : WL-1-LUT_addWidth];
		always @* begin
			if(~nRST) begin
					mul2_net_r <= 0;
					B1 <= 0;
					B1_real <= 0;
					xHat <= 0;
			end
			else begin
				if (CE) begin
					B1 <= LUT[reg_cmp];
					B1_real[LUT_bits-1 : 0] <= B1;
					B1_real[LUT_bits] <= 1'b0;
					xHat[WL-1:WL-m] <=  din[WL-1:WL-m];
					xHat[WL-(m+1):0] <= ~din[WL-(m+1):0];
					mul2_net_r <= ~mul2_net;
					mul4_net_r <= ~mul4_net;
				end
			end
		end

mult_unsigned #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(LUT_bits), .WIO(1), .WFO(LUT_bits+2-1)) multiplier_1 
				   (.CLK(CLK), .RST(nRST), .in1(xHat), .in2(B1_real), .out(iniValue));
				   
mult_unsigned_pipe #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(LUT_bits+2-1), .WIO(1), .WFO(dWL_s2-1)) multiplier_2 
				   (.CLK(CLK), .RST(nRST), .in1(din), .in2(iniValue), .out(mul2_net));
				   
mult_unsigned_pipe #(.WI1(1), .WF1(dWL_s2-1), .WI2(1), .WF2(LUT_bits+2-1), .WIO(1), .WFO(dWL_s2-1)) multiplier_3 
				   (.CLK(CLK), .RST(nRST), .in1(mul2_net_r), .in2(iniValue_delay), .out(mul3_net));

mult_unsigned_pipe #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(dWL_s2-1), .WIO(1), .WFO(dWL-1)) multiplier_4
				   (.CLK(CLK), .RST(nRST), .in1(din_delay), .in2(mul3_net), .out(mul4_net));

mult_unsigned_pipe #(.WI1(1), .WF1(dWL-1), .WI2(1), .WF2(dWL_s2-1), .WIO(1), .WFO(dWL+dWL_s2-1)) multiplier_5 
				   (.CLK(CLK), .RST(nRST), .in1(mul4_net_r), .in2(mul3_net_delay), .out(Mul));


		ux_round2nearest
			#(
				.WordLength(dWL+dWL_s2),
				.RoundLength(dWL+dWL_s2 - WLO)
			 )
		round_0 
			(
				.CLK(CLK),
				.RESET(nRST),
				.CE(CE),
				.x(Mul),
				.y(dout)
			 );


	localparam PIP_iniValue = 2;
	localparam PIP_din	= 4;
	localparam PIP_mul3_net = 2;
	reg [LUT_bits+2-1 : 0] buffer_iniValue [1: PIP_iniValue];
	reg [WL-1  : 0] buffer_din [1: PIP_din];
	reg [dWL_s2-1 : 0] buffer_mul3_net [1: PIP_mul3_net];
	integer i;
	
	always @(posedge CLK) begin
		if (!nRST) begin
			for (i=1; i<=PIP_iniValue; i=i+1)
				buffer_iniValue[i] <= 0;
				
			for (i=1; i<=PIP_din; i=i+1)
				buffer_din[i] <= 0;

			for (i=1; i<=PIP_mul3_net; i=i+1)
				buffer_mul3_net[i] <= 0;
				
		end else begin
			buffer_iniValue[1] <= iniValue;
			for (i=2; i<=PIP_iniValue; i=i+1)
				buffer_iniValue[i] <= buffer_iniValue[i-1];
				
			buffer_din[1] <= din;
			for (i=2; i<=PIP_din; i=i+1)
				buffer_din[i] <= buffer_din[i-1];

			buffer_mul3_net[1] <= mul3_net;
			for (i=2; i<=PIP_mul3_net; i=i+1)
				buffer_mul3_net[i] <= buffer_mul3_net[i-1];
		end
	end

	assign iniValue_delay = buffer_iniValue[PIP_iniValue];
	assign din_delay = buffer_din[PIP_din];
	assign mul3_net_delay = buffer_mul3_net[PIP_mul3_net];

endmodule