data/full_repos/permissive/174642777/Experiments/Lab X5/2.1 S2P_4bit/S2P_4bit.v
 line:59 column:24: Illegal character "'"
1: b'%Error: Cannot find file containing module: X5/2.1\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X5/2.1\n             data/full_repos/permissive/174642777/Experiments/Lab/X5/2.1.v\n             data/full_repos/permissive/174642777/Experiments/Lab/X5/2.1.sv\n             X5/2.1\n             X5/2.1.v\n             X5/2.1.sv\n             obj_dir/X5/2.1\n             obj_dir/X5/2.1.v\n             obj_dir/X5/2.1.sv\n%Error: Cannot find file containing module: S2P_4bit,data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: S2P_4bit/S2P_4bit.v\n%Error: Exiting due to 4 error(s)\n'
module S2P_4bit(
  input wire CLK, CLR, D,
  output reg DR,
  output reg[3:0] Q
);

  reg[1:0] count;
  reg[3:0] dff_Q;
  reg[1:0] DR_begin;
  
  initial begin
    count <= 0;
    DR <= 0;
    dff_Q <= 0;
    Q <= 0;
    DR_begin <= 0;
  end
  
  always@(posedge CLK, posedge CLR) begin

    if(CLR) dff_Q[3] <= 0;
    else    dff_Q[3] <= D;
    

    if(CLR) dff_Q[2] <= 0;
    else    dff_Q[2] <= dff_Q[3];
    

    if(CLR) dff_Q[1] <= 0;
    else    dff_Q[1] <= dff_Q[2];
    

    if(CLR) dff_Q[0] <= 0;
    else    dff_Q[0] <= dff_Q[1];
  end
  
  always@(posedge CLK) begin

    count <= count + 2'b 01;
  end
  
  always@(posedge CLK) begin
    if(!count[1] & !count[0]) begin
      Q <= dff_Q;
      if(!DR_begin[1]) DR_begin = DR_begin + 2'b 01;
      else DR <= 1;
    end
    else DR <= 0;
  end

endmodule
module S2P_4bit(
  input wire CLK, CLR, D,
  output reg DR,
  output reg[3:0] Q
);


  reg[1:0] count;
  reg[3:0] dff_Q;
  reg[1:0] DR_begin;
  
  initial begin
    count <= 0;
    DR <= 0;
    dff_Q <= 0;
    Q <= 0;
    DR_begin <= 0;
  end
  
  always@(posedge CLK, posedge CLR) begin

    if(CLR) dff_Q[3] <= 0;
    else    dff_Q[3] <= D;
    

    if(CLR) dff_Q[2] <= 0;
    else    dff_Q[2] <= dff_Q[3];
    

    if(CLR) dff_Q[1] <= 0;
    else    dff_Q[1] <= dff_Q[2];
    

    if(CLR) dff_Q[0] <= 0;
    else    dff_Q[0] <= dff_Q[1];
  end
  
  always@(posedge CLK) begin

    count <= count + 2'b 01;
  end
  
  always@(posedge CLK) begin
    if(!count[1] & !count[0]) begin
      Q <= dff_Q;
      if(!DR_begin[1]) DR_begin = DR_begin + 2'b 01;
      else DR <= 1;
    end
    else DR <= 0;
  end

endmodule