data/full_repos/permissive/167856740/cpu/tb/cpu_tb.v
 line:175: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/cpu_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n  #500 CLK_I = ~CLK_I;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/cpu_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n        #1000 RST_I = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/cpu_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n        #6000 INT_I = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/cpu_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n        #1000 INT_I = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/cpu_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #10000 $finish;\n  ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/cpu_tb.v:65: Cannot find file containing module: \'cpu\'\n    cpu #(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/cpu\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/cpu.v\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/167856740/cpu/tb/cpu_tb.v:135: Cannot find file containing module: \'ram_wishbone\'\n    ram_wishbone ram (\n    ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_tb;
	

	reg CLK_I;
	reg RST_I;
	reg INT_I;
	
	wire WE_O;
    wire [31:0] ADR_O;
    wire [31:0] DAT_O;
    wire [31:0] DAT_I;































    wire [31:0] pc_out;















    



            

    cpu #(
        .RESET(32'h00000000),
        .VECTOR(32'h00000010),
        .INSTRUCTION_MEM("mret_test.mem"),
        .DATA_MEM("")
    )
    cpu (
        .CLK_I(CLK_I),
        .RST_I(RST_I),
        .INT_I(INT_I),
        

        .WE_O(WE_O),
        .ADR_O(ADR_O),
        .DAT_O(DAT_O),
        .DAT_I(DAT_I),
        

















        











        

        .pc_out(pc_out)















        



        );

    ram_wishbone ram (
        .CLK_I(CLK_I),
        .RST_I(RST_I),
        .STB_I(1'b1),
        .WE_I(WE_O),
        .ADR_I(ADR_O),
        .DAT_I(DAT_O),
        .DAT_O(DAT_I)
    );










	always begin
		#500 CLK_I = ~CLK_I;
		if(CLK_I == 1) begin

		end
	end

	initial begin

        CLK_I = 1; INT_I = 0; RST_I = 1;
        
        #1000 RST_I = 0;
        
        #6000 INT_I = 1;
        #1000 INT_I = 0;
 





		#10000 $finish;
	end
	
endmodule
module cpu_tb;

	

	reg CLK_I;
	reg RST_I;
	reg INT_I;
	
	wire WE_O;
    wire [31:0] ADR_O;
    wire [31:0] DAT_O;
    wire [31:0] DAT_I;































    wire [31:0] pc_out;















    



            

    cpu #(
        .RESET(32'h00000000),
        .VECTOR(32'h00000010),
        .INSTRUCTION_MEM("mret_test.mem"),
        .DATA_MEM("")
    )
    cpu (
        .CLK_I(CLK_I),
        .RST_I(RST_I),
        .INT_I(INT_I),
        

        .WE_O(WE_O),
        .ADR_O(ADR_O),
        .DAT_O(DAT_O),
        .DAT_I(DAT_I),
        

















        











        

        .pc_out(pc_out)















        



        );

    ram_wishbone ram (
        .CLK_I(CLK_I),
        .RST_I(RST_I),
        .STB_I(1'b1),
        .WE_I(WE_O),
        .ADR_I(ADR_O),
        .DAT_I(DAT_O),
        .DAT_O(DAT_I)
    );










	always begin
		#500 CLK_I = ~CLK_I;
		if(CLK_I == 1) begin

		end
	end

	initial begin

        CLK_I = 1; INT_I = 0; RST_I = 1;
        
        #1000 RST_I = 0;
        
        #6000 INT_I = 1;
        #1000 INT_I = 0;
 





		#10000 $finish;
	end
	
endmodule