data/full_repos/permissive/173003307/src/ROM.v
data/verilator_xmls/b17b7153-6645-42ac-aea7-2c76814d1925.xml
module ROM( 

                input CLK,

                output reg [7:0] DATA,
                input [7:0] ADDR
                );
                
    parameter RAMAddrWidth = 8;
    

    reg [7:0] ROM [2**RAMAddrWidth-1:0]; 
    

    initial 
        $readmemh("../additional_sources/rom.txt", ROM);     
        

    always@(posedge CLK) 
        DATA <= ROM[ADDR]; 
        
    endmodule
module ROM( 

                input CLK,

                output reg [7:0] DATA,
                input [7:0] ADDR
                );

                
    parameter RAMAddrWidth = 8;
    

    reg [7:0] ROM [2**RAMAddrWidth-1:0]; 
    

    initial 
        $readmemh("../additional_sources/rom.txt", ROM);     
        

    always@(posedge CLK) 
        DATA <= ROM[ADDR]; 
        
    endmodule