data/full_repos/permissive/174242803/controller/src/controller_tb.v
1: b'%Error: data/full_repos/permissive/174242803/controller/src/controller_tb.v:91: Unsupported or unknown PLI call: $monitor\n  $monitor ("TIME = %d, rst = %b, opcode = %b, state = %b", $time, rst, op, u1.state);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n        rst = 1; #WAIT; rst = 0; #WAIT;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n        rst = 1; #WAIT; rst = 0; #WAIT;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n        op = LB; #INSTR_WAIT; #EXEC_WAIT;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n        op = LB; #INSTR_WAIT; #EXEC_WAIT;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n        op = SB; #INSTR_WAIT; #EXEC_WAIT;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n        op = SB; #INSTR_WAIT; #EXEC_WAIT;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n        op = RTYPE; #INSTR_WAIT; #EXEC_WAIT;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n        op = RTYPE; #INSTR_WAIT; #EXEC_WAIT;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n        op = BEQ; #INSTR_WAIT; #EXEC_WAIT;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n        op = BEQ; #INSTR_WAIT; #EXEC_WAIT;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n        op = J; #INSTR_WAIT; #EXEC_WAIT;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n        op = J; #INSTR_WAIT; #EXEC_WAIT;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n        op = ADDI; #INSTR_WAIT; #EXEC_WAIT;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n        op = ADDI; #INSTR_WAIT; #EXEC_WAIT;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Error: data/full_repos/permissive/174242803/controller/src/controller_tb.v:119: Unsupported or unknown PLI call: $shm_open\n        $shm_open("controller_tb.db");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/174242803/controller/src/controller_tb.v:120: Unsupported or unknown PLI call: $shm_probe\n        $shm_probe(controller_tb, "AS");\n        ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174242803/controller/src/controller_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n        forever #1 clk = ~clk;\n                ^\n%Error: Exiting due to 3 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module controller_tb();

    parameter FINISH_TIME = 2000;
    parameter PERIOD      = 20;
    parameter WAIT        = 5;
    parameter INSTR_WAIT  = 5;
    parameter EXEC_WAIT   = 10;


    reg        clk;
    reg        rst;
    reg [5:0]  op;
    reg        zero;


    wire       memread;
    wire       memwrite;
    wire       alusrca;
    wire       memtoreg;
    wire       iord;
    wire       pcen;
    wire       regwrite;
    wire       regdst;
    wire [1:0] pcsource;
    wire [1:0] alsrcb;
    wire [1:0] aluop;
    wire [3:0] irwrite;
    

    wire [3:0] current_state;


    parameter FETCH1     = 4'b0001;
    parameter FETCH2     = 4'b0010;
    parameter FETCH3     = 4'b0011;
    parameter FETCH4     = 4'b0100;
    parameter DECODE     = 4'b0101;
    parameter MEMADR     = 4'b0110;
    parameter LBRD       = 4'b0111;
    parameter LBWR       = 4'b1000;   
    parameter SBWR       = 4'b1001;
    parameter RTYPEEX    = 4'b1010;
    parameter RTYPEWR    = 4'b1011;
    parameter BEQEX      = 4'b1100;
    parameter JEX        = 4'b1101;
    parameter ADDIWR     = 4'b1110;


    parameter LB        = 6'b100000;
    parameter SB        = 6'b101000;
    parameter RTYPE     = 6'b000000;
    parameter BEQ       = 6'b100100;
    parameter J         = 6'b100010;
    parameter ADDI      = 6'b001000;


    controller u1(.clk(clk),
               .rst(rst),
               .op(op),
               .memread(memread),
               .memwrite(memwrite),
               .alusrca(alusrca),
               .memtoreg(memtoreg),
               .iord(iord),
               .regwrite(regwrite),
               .regdst(regdst),
               .pcsource(pcsource),
               .alusrcb(alusrcb),
               .aluop(aluop),
               .irwrite(irwrite));



    
    initial begin
		$display ("-----------------------------------------------------");
		$display ("                                           AB");
		$display ("-----------------------------------------------------");
		$monitor ("TIME = %d, rst = %b, opcode = %b, state = %b", $time, rst, op, u1.state);
		clk  = 1'b0;
      rst  = 1'b0;
      op   = 6'b000000;
      zero = 1'b0;
	end


    initial begin

        #PERIOD;
        rst = 1; #WAIT; rst = 0; #WAIT;

        op = LB; #INSTR_WAIT; #EXEC_WAIT;
        op = SB; #INSTR_WAIT; #EXEC_WAIT;
        op = RTYPE; #INSTR_WAIT; #EXEC_WAIT;
        op = BEQ; #INSTR_WAIT; #EXEC_WAIT;
        op = J; #INSTR_WAIT; #EXEC_WAIT;
        op = ADDI; #INSTR_WAIT; #EXEC_WAIT;
        
        #PERIOD;
        $display("Finishing simulation due to end of testbench.");
        $display("Time is - %d", $time);
        $finish;
    end


    initial begin
        $shm_open("controller_tb.db");
        $shm_probe(controller_tb, "AS");
    end
    
    initial begin
        forever #1 clk = ~clk;
    end

endmodule
module controller_tb();


    parameter FINISH_TIME = 2000;
    parameter PERIOD      = 20;
    parameter WAIT        = 5;
    parameter INSTR_WAIT  = 5;
    parameter EXEC_WAIT   = 10;


    reg        clk;
    reg        rst;
    reg [5:0]  op;
    reg        zero;


    wire       memread;
    wire       memwrite;
    wire       alusrca;
    wire       memtoreg;
    wire       iord;
    wire       pcen;
    wire       regwrite;
    wire       regdst;
    wire [1:0] pcsource;
    wire [1:0] alsrcb;
    wire [1:0] aluop;
    wire [3:0] irwrite;
    

    wire [3:0] current_state;


    parameter FETCH1     = 4'b0001;
    parameter FETCH2     = 4'b0010;
    parameter FETCH3     = 4'b0011;
    parameter FETCH4     = 4'b0100;
    parameter DECODE     = 4'b0101;
    parameter MEMADR     = 4'b0110;
    parameter LBRD       = 4'b0111;
    parameter LBWR       = 4'b1000;   
    parameter SBWR       = 4'b1001;
    parameter RTYPEEX    = 4'b1010;
    parameter RTYPEWR    = 4'b1011;
    parameter BEQEX      = 4'b1100;
    parameter JEX        = 4'b1101;
    parameter ADDIWR     = 4'b1110;


    parameter LB        = 6'b100000;
    parameter SB        = 6'b101000;
    parameter RTYPE     = 6'b000000;
    parameter BEQ       = 6'b100100;
    parameter J         = 6'b100010;
    parameter ADDI      = 6'b001000;


    controller u1(.clk(clk),
               .rst(rst),
               .op(op),
               .memread(memread),
               .memwrite(memwrite),
               .alusrca(alusrca),
               .memtoreg(memtoreg),
               .iord(iord),
               .regwrite(regwrite),
               .regdst(regdst),
               .pcsource(pcsource),
               .alusrcb(alusrcb),
               .aluop(aluop),
               .irwrite(irwrite));



    
    initial begin
		$display ("-----------------------------------------------------");
		$display ("                                           AB");
		$display ("-----------------------------------------------------");
		$monitor ("TIME = %d, rst = %b, opcode = %b, state = %b", $time, rst, op, u1.state);
		clk  = 1'b0;
      rst  = 1'b0;
      op   = 6'b000000;
      zero = 1'b0;
	end


    initial begin

        #PERIOD;
        rst = 1; #WAIT; rst = 0; #WAIT;

        op = LB; #INSTR_WAIT; #EXEC_WAIT;
        op = SB; #INSTR_WAIT; #EXEC_WAIT;
        op = RTYPE; #INSTR_WAIT; #EXEC_WAIT;
        op = BEQ; #INSTR_WAIT; #EXEC_WAIT;
        op = J; #INSTR_WAIT; #EXEC_WAIT;
        op = ADDI; #INSTR_WAIT; #EXEC_WAIT;
        
        #PERIOD;
        $display("Finishing simulation due to end of testbench.");
        $display("Time is - %d", $time);
        $finish;
    end


    initial begin
        $shm_open("controller_tb.db");
        $shm_probe(controller_tb, "AS");
    end
    
    initial begin
        forever #1 clk = ~clk;
    end

endmodule