data/full_repos/permissive/117439233/hdl/src/CAS.v
data/verilator_xmls/ad5ca6c0-0c21-43d0-a7c2-ba564fdb1a8e.xml
module CAS(
	input [3:0] IN,
	output [3:0] OUT
	);
	wire A = IN[0] ^ IN[1];
	assign OUT[0] = ( A & IN[2] ) | ( IN[3] & ( A ^ IN[2] ) );
	assign OUT[1] = A ^ IN[2] ^ IN[3];
	assign OUT[2] = IN[1];
	assign OUT[3] = IN[0];
endmodule
module CAS(
	input [3:0] IN,
	output [3:0] OUT
	);

	wire A = IN[0] ^ IN[1];
	assign OUT[0] = ( A & IN[2] ) | ( IN[3] & ( A ^ IN[2] ) );
	assign OUT[1] = A ^ IN[2] ^ IN[3];
	assign OUT[2] = IN[1];
	assign OUT[3] = IN[0];
endmodule