data/full_repos/permissive/156609923/memoria/testbench.v
 line:39: before: "("
1: b'%Error: data/full_repos/permissive/156609923/memoria/testbench.v:2: Cannot find include file: probador.v\n`include"probador.v" \n        ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156609923/memoria,data/full_repos/permissive/156609923/probador.v\n             data/full_repos/permissive/156609923/memoria,data/full_repos/permissive/156609923/probador.v.v\n             data/full_repos/permissive/156609923/memoria,data/full_repos/permissive/156609923/probador.v.sv\n             probador.v\n             probador.v.v\n             probador.v.sv\n             obj_dir/probador.v\n             obj_dir/probador.v.v\n             obj_dir/probador.v.sv\n%Error: data/full_repos/permissive/156609923/memoria/testbench.v:3: Cannot find include file: memoria.v\n`include "memoria.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156609923/memoria/testbench.v:4: Cannot find include file: memoriaSynth.v\n`include "memoriaSynth.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156609923/memoria/testbench.v:5: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module testbench();
   parameter ADDR_WIDTH = 4;
   parameter BUS_SIZE = 4;

   parameter MEM_LENGTH = 1 << ADDR_WIDTH;
   


   wire [ADDR_WIDTH-1:0] addressR;
   wire [ADDR_WIDTH-1:0] addressW;
   wire			clk;
   wire [BUS_SIZE-1:0]	data_in;
   wire [BUS_SIZE-1:0]	data_out_synth;
   wire [BUS_SIZE-1:0]	data_out_cond;
   wire			read;
   wire			write;

   memoria mem (

		.data_out		(data_out_cond[BUS_SIZE-1:0]),

		.clk			(clk),
		.read			(read),
		.write			(write),
		.data_in		(data_in[BUS_SIZE-1:0]),
		.addressR		(addressR[ADDR_WIDTH-1:0]),
		.addressW		(addressW[ADDR_WIDTH-1:0]));
   memoriaSynth memSyn(

		       .data_out	(data_out_synth[3:0]),

		       .addressR	(addressR[3:0]),
		       .addressW	(addressW[3:0]),
		       .clk		(clk),
		       .data_in		(data_in[3:0]),
		       .read		(read),
		       .write		(write));
   
   probador prob(

		 .clk			(clk),
		 .read			(read),
		 .write			(write),
		 .data_in		(data_in[BUS_SIZE-1:0]),
		 .addressR		(addressR[ADDR_WIDTH-1:0]),
		 .addressW		(addressW[ADDR_WIDTH-1:0]),

		 .data_out_synth	(data_out_synth[BUS_SIZE-1:0]),
		 .data_out_cond		(data_out_cond[BUS_SIZE-1:0]));
   
   endmodule
module testbench();

   parameter ADDR_WIDTH = 4;
   parameter BUS_SIZE = 4;

   parameter MEM_LENGTH = 1 << ADDR_WIDTH;
   


   wire [ADDR_WIDTH-1:0] addressR;
   wire [ADDR_WIDTH-1:0] addressW;
   wire			clk;
   wire [BUS_SIZE-1:0]	data_in;
   wire [BUS_SIZE-1:0]	data_out_synth;
   wire [BUS_SIZE-1:0]	data_out_cond;
   wire			read;
   wire			write;

   memoria mem (

		.data_out		(data_out_cond[BUS_SIZE-1:0]),

		.clk			(clk),
		.read			(read),
		.write			(write),
		.data_in		(data_in[BUS_SIZE-1:0]),
		.addressR		(addressR[ADDR_WIDTH-1:0]),
		.addressW		(addressW[ADDR_WIDTH-1:0]));
   memoriaSynth memSyn(

		       .data_out	(data_out_synth[3:0]),

		       .addressR	(addressR[3:0]),
		       .addressW	(addressW[3:0]),
		       .clk		(clk),
		       .data_in		(data_in[3:0]),
		       .read		(read),
		       .write		(write));
   
   probador prob(

		 .clk			(clk),
		 .read			(read),
		 .write			(write),
		 .data_in		(data_in[BUS_SIZE-1:0]),
		 .addressR		(addressR[ADDR_WIDTH-1:0]),
		 .addressW		(addressW[ADDR_WIDTH-1:0]),

		 .data_out_synth	(data_out_synth[BUS_SIZE-1:0]),
		 .data_out_cond		(data_out_cond[BUS_SIZE-1:0]));
   
   endmodule