data/full_repos/permissive/219943485/control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/219943485/control.v:123: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                  : ... In instance control\n    calc_time_sec_h <= 4\'b0;\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/219943485/control.v:148: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                  : ... In instance control\n    time_out <= 4\'b0;\n             ^~\n%Error: Exiting due to 2 warning(s)\n'
module control(clk_100mhz,
               clk_100hz,
               rst_n, 
               sw_en,
               pause,
               clear,
               time_sec_h, 
               time_sec_l,
               time_msec_h, 
               time_msec_l, 
               time_out
               );
  
  input clk_100mhz, clk_100hz, rst_n;
  input sw_en, pause, clear;
  output[2:0] time_sec_h;
  output[3:0] time_sec_l;
  output[3:0] time_msec_h;
  output[3:0] time_msec_l;
  output time_out;
  


  reg time_out;
  
  reg[2:0] time_sec_h;
  reg[3:0] time_sec_l;
  reg[3:0] time_msec_h;
  reg[3:0] time_msec_l;
  
  reg[2:0] calc_time_sec_h;
  reg[3:0] calc_time_sec_l;
  reg[3:0] calc_time_msec_h;
  reg[3:0] calc_time_msec_l;






always @(posedge clk_100hz or negedge rst_n)  
  if(!rst_n)
    calc_time_msec_l <= 4'b0;
  else if(clear)
    calc_time_msec_l <= 4'b0;
  else if(calc_time_msec_l == 4'b1001)
    calc_time_msec_l <= 4'b0;
  else if(sw_en == 1)
    calc_time_msec_l <= calc_time_msec_l + 1;







always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
      calc_time_msec_h <= 4'b0;
  else if(clear)
    calc_time_msec_h <= 4'b0;
  else 
    begin
      if(calc_time_msec_l == 4'b1001 
       && calc_time_msec_h == 4'b1001
         )
        calc_time_msec_h <= 4'b0; 
      else if(calc_time_msec_l == 4'b1001)
        calc_time_msec_h <= calc_time_msec_h + 1; 
    end
    





always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
    calc_time_sec_l <= 4'b0;
  else if(clear)
    calc_time_sec_l <= 4'b0;
  else
    begin
      if(calc_time_msec_l == 4'b1001 
      && calc_time_msec_h == 4'b1001 
      && calc_time_sec_l == 4'b1001
         )
        calc_time_sec_l <= 4'b0;  
      else if(calc_time_msec_l == 4'b1001 
       && calc_time_msec_h == 4'b1001
         )
        calc_time_sec_l <= calc_time_sec_l + 1; 
    end
    





always @(posedge clk_100hz or negedge rst_n) 
  if(!rst_n)
    calc_time_sec_h <= 3'b0;
  else if(clear)
    calc_time_sec_h <= 4'b0;
  else
    begin
      if(calc_time_msec_l == 4'b1001
       && calc_time_msec_h == 4'b1001
       && calc_time_sec_l == 4'b1001 
       && calc_time_sec_h == 3'b101
         )
        calc_time_sec_h <= 3'b0;
      else if(calc_time_msec_l == 4'b1001 
       && calc_time_msec_h == 4'b1001 
       && calc_time_sec_l == 4'b1001
         )
         calc_time_sec_h <= calc_time_sec_h + 1; 
    end
    





always @(posedge clk_100hz or negedge rst_n) 
  if(!rst_n)
    time_out <= 0;
  else if(clear)
    time_out <= 4'b0;
  else if(calc_time_msec_l == 4'b0111
        && calc_time_msec_h == 4'b0101
        && calc_time_sec_l == 4'b1001
        && calc_time_sec_h == 3'b000
          )
    time_out <= 1;
  else if(calc_time_msec_l == 4'b0
        && calc_time_msec_h == 4'b0
        && calc_time_sec_l == 4'b0 
        && calc_time_sec_h == 3'b0
          )
    time_out <= 0;






always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
    time_msec_l <= 0;
  else if(clear)
    time_msec_l <= 0;
  else if(!pause)
    time_msec_l <= calc_time_msec_l;
    





always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
    time_msec_h <= 0;
  else if(clear)
    time_msec_h <= 0;
  else if(!pause)
    time_msec_h <= calc_time_msec_h;
    





always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
    time_sec_l <= 0;
  else if(clear)
    time_sec_l <= 0;
  else if(!pause)
    time_sec_l <= calc_time_sec_l;
    





always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
    time_sec_h <= 0;
  else if(clear)
    time_sec_h <= 0;
  else if(!pause)
    time_sec_h <= calc_time_sec_h;
    



































    













endmodule
module control(clk_100mhz,
               clk_100hz,
               rst_n, 
               sw_en,
               pause,
               clear,
               time_sec_h, 
               time_sec_l,
               time_msec_h, 
               time_msec_l, 
               time_out
               );

  
  input clk_100mhz, clk_100hz, rst_n;
  input sw_en, pause, clear;
  output[2:0] time_sec_h;
  output[3:0] time_sec_l;
  output[3:0] time_msec_h;
  output[3:0] time_msec_l;
  output time_out;
  


  reg time_out;
  
  reg[2:0] time_sec_h;
  reg[3:0] time_sec_l;
  reg[3:0] time_msec_h;
  reg[3:0] time_msec_l;
  
  reg[2:0] calc_time_sec_h;
  reg[3:0] calc_time_sec_l;
  reg[3:0] calc_time_msec_h;
  reg[3:0] calc_time_msec_l;






always @(posedge clk_100hz or negedge rst_n)  
  if(!rst_n)
    calc_time_msec_l <= 4'b0;
  else if(clear)
    calc_time_msec_l <= 4'b0;
  else if(calc_time_msec_l == 4'b1001)
    calc_time_msec_l <= 4'b0;
  else if(sw_en == 1)
    calc_time_msec_l <= calc_time_msec_l + 1;







always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
      calc_time_msec_h <= 4'b0;
  else if(clear)
    calc_time_msec_h <= 4'b0;
  else 
    begin
      if(calc_time_msec_l == 4'b1001 
       && calc_time_msec_h == 4'b1001
         )
        calc_time_msec_h <= 4'b0; 
      else if(calc_time_msec_l == 4'b1001)
        calc_time_msec_h <= calc_time_msec_h + 1; 
    end
    





always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
    calc_time_sec_l <= 4'b0;
  else if(clear)
    calc_time_sec_l <= 4'b0;
  else
    begin
      if(calc_time_msec_l == 4'b1001 
      && calc_time_msec_h == 4'b1001 
      && calc_time_sec_l == 4'b1001
         )
        calc_time_sec_l <= 4'b0;  
      else if(calc_time_msec_l == 4'b1001 
       && calc_time_msec_h == 4'b1001
         )
        calc_time_sec_l <= calc_time_sec_l + 1; 
    end
    





always @(posedge clk_100hz or negedge rst_n) 
  if(!rst_n)
    calc_time_sec_h <= 3'b0;
  else if(clear)
    calc_time_sec_h <= 4'b0;
  else
    begin
      if(calc_time_msec_l == 4'b1001
       && calc_time_msec_h == 4'b1001
       && calc_time_sec_l == 4'b1001 
       && calc_time_sec_h == 3'b101
         )
        calc_time_sec_h <= 3'b0;
      else if(calc_time_msec_l == 4'b1001 
       && calc_time_msec_h == 4'b1001 
       && calc_time_sec_l == 4'b1001
         )
         calc_time_sec_h <= calc_time_sec_h + 1; 
    end
    





always @(posedge clk_100hz or negedge rst_n) 
  if(!rst_n)
    time_out <= 0;
  else if(clear)
    time_out <= 4'b0;
  else if(calc_time_msec_l == 4'b0111
        && calc_time_msec_h == 4'b0101
        && calc_time_sec_l == 4'b1001
        && calc_time_sec_h == 3'b000
          )
    time_out <= 1;
  else if(calc_time_msec_l == 4'b0
        && calc_time_msec_h == 4'b0
        && calc_time_sec_l == 4'b0 
        && calc_time_sec_h == 3'b0
          )
    time_out <= 0;






always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
    time_msec_l <= 0;
  else if(clear)
    time_msec_l <= 0;
  else if(!pause)
    time_msec_l <= calc_time_msec_l;
    





always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
    time_msec_h <= 0;
  else if(clear)
    time_msec_h <= 0;
  else if(!pause)
    time_msec_h <= calc_time_msec_h;
    





always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
    time_sec_l <= 0;
  else if(clear)
    time_sec_l <= 0;
  else if(!pause)
    time_sec_l <= calc_time_sec_l;
    





always @(posedge clk_100hz or negedge rst_n)
  if(!rst_n)
    time_sec_h <= 0;
  else if(clear)
    time_sec_h <= 0;
  else if(!pause)
    time_sec_h <= calc_time_sec_h;
    



































    













endmodule