data/full_repos/permissive/210844779/lab2/2.5.2/pipo.v
data/verilator_xmls/164faa0b-1ac4-4ba8-827b-de8d4a492269.xml
module pipo(d,clk,load,q);
  input [7:0]d;
  input clk,load;
  output reg[7:0]q;
  

  
   always @(posedge clk ) 
   begin
     if (load)
       q <= d;
   else
     
      q<= {q[0],q[7:1]};
     
 end
 
endmodule
module pipo(d,clk,load,q);

  input [7:0]d;
  input clk,load;
  output reg[7:0]q;
  

  
   always @(posedge clk ) 
   begin
     if (load)
       q <= d;
   else
     
      q<= {q[0],q[7:1]};
     
 end
 
endmodule