data/full_repos/permissive/167489907/Testbenches/CLA_adder4bit_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/CLA_adder4bit_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/CLA_adder4bit_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/CLA_adder4bit_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/CLA_adder4bit_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/CLA_adder4bit_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/167489907/Testbenches/CLA_adder4bit_tb.v:8: Cannot find file containing module: \'CLA_adder4bit\'\nCLA_adder4bit uut (.Cin(Cin), .A(A), .B(B), .S(S), .Cout(Cout));\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/CLA_adder4bit\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/CLA_adder4bit.v\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/CLA_adder4bit.sv\n             CLA_adder4bit\n             CLA_adder4bit.v\n             CLA_adder4bit.sv\n             obj_dir/CLA_adder4bit\n             obj_dir/CLA_adder4bit.v\n             obj_dir/CLA_adder4bit.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CLA_adder4bit_tb;

reg Cin;
reg [3:0] A, B;
wire [3:0] S;
wire Cout;

CLA_adder4bit uut (.Cin(Cin), .A(A), .B(B), .S(S), .Cout(Cout));

initial
begin
	#10;
	Cin = 1'b0;
	A = 4'b1101;
	B = 4'b1011;
	#10;
	A = 4'b0100;
	B = 4'b0010;
	#10;
	A = 4'b0011;
	B = 4'b0011;
	#10;
	A = 4'b1111;
	B = 4'b1111;
	#10;
	$stop;
end
endmodule
module CLA_adder4bit_tb;


reg Cin;
reg [3:0] A, B;
wire [3:0] S;
wire Cout;

CLA_adder4bit uut (.Cin(Cin), .A(A), .B(B), .S(S), .Cout(Cout));

initial
begin
	#10;
	Cin = 1'b0;
	A = 4'b1101;
	B = 4'b1011;
	#10;
	A = 4'b0100;
	B = 4'b0010;
	#10;
	A = 4'b0011;
	B = 4'b0011;
	#10;
	A = 4'b1111;
	B = 4'b1111;
	#10;
	$stop;
end
endmodule