data/full_repos/permissive/139476920/testsuite/fastram/write_cycle.v
None: at end of input
1: b'%Error: data/full_repos/permissive/139476920/testsuite/fastram/write_cycle.v:29: Cannot find include file: common.vinc\n`include "common.vinc" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139476920/testsuite/fastram,data/full_repos/permissive/139476920/common.vinc\n             data/full_repos/permissive/139476920/testsuite/fastram,data/full_repos/permissive/139476920/common.vinc.v\n             data/full_repos/permissive/139476920/testsuite/fastram,data/full_repos/permissive/139476920/common.vinc.sv\n             common.vinc\n             common.vinc.v\n             common.vinc.sv\n             obj_dir/common.vinc\n             obj_dir/common.vinc.v\n             obj_dir/common.vinc.sv\n%Error: data/full_repos/permissive/139476920/testsuite/fastram/write_cycle.v:61: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("write_cycle.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/139476920/testsuite/fastram/write_cycle.v:62: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, write_cycle_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/139476920/testsuite/fastram/write_cycle.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139476920/testsuite/fastram/write_cycle.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #142;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/139476920/testsuite/fastram/write_cycle.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #142;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/139476920/testsuite/fastram/write_cycle.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #1000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139476920/testsuite/fastram/write_cycle.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #71; CLK14M = ~CLK14M;\n    ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module write_cycle_tb;
   

   reg RESET;
   reg CLK14M;
   wire CLK;
   
   reg AS20;
   reg DS20;
   reg RW20;
   
   reg [31:0] A;
   reg [31:0] D_OUT;
   
   reg [1:0]  SIZ;
   wire [1:0]  DSACK;

   wire       RAMOE;
   wire [1:0] RAS;
   wire [3:0] CAS;

   wire [31:0] D = RW20 ? {32{1'bz}} : D_OUT;


`include "common.vinc"
   

   ramcpld uut (
		  
   	        .CLKCPU(CLK), 
		.RESET(RESET),
					
		.AS20(AS20), 
		.DS20(DS20), 
		.RW20(RW20),
 
		.DSACK(DSACK),
		.PUNT (PUNT),
		.SIZ(SIZ), 

		.A(A[23:0]), 
			
		.D (D[31:24]),
		  
		.IDEINT ( 1'b0 ),

		.RAMOE	(RAMOE),
		.CAS	(CAS),
		.RAS	(RAS),
		.RAM_MUX(RAM_MUX)
		
	);

   integer     i;
	initial begin
	   
	   $dumpfile("write_cycle.vcd");
	   $dumpvars(0, write_cycle_tb);
	   
	   RESET = 1;
	   #10;
	   

	   CLK14M = 0;
	   RESET = 0;
	   

	   #142;
		
	   RESET = 1;

	   #142;
	   
	   SIZ = 2'b10;

	   write(32'h00E8004a, 32'h9_0000000);
	   write(32'h00E80048, 32'hE_0000000);
	   
	   write(32'h00E8004a, 32'h0_0000000);
	   write(32'h00E80048, 32'h2_0000000);

	   busidle();

	   for( i = 32'h200000; i < 32'h00210000; i++ ) begin
	   
	      write(i, 0);
	      busidle();
	      read(i);
	      busidle();
	   
	   end

		#1000000;
	   
	   $finish;
	end
   
assign CLK = CLK14M;

always 	begin
    #71; CLK14M = ~CLK14M;
end

PULLUP PUNT_pullup (
.O(PUNT)
);

PULLUP DSACK0_pullup (
.O(DSACK[0]) 
);

PULLUP DSACK1_pullup (
.O(DSACK[1]) 
);

   
endmodule
module write_cycle_tb;

   

   reg RESET;
   reg CLK14M;
   wire CLK;
   
   reg AS20;
   reg DS20;
   reg RW20;
   
   reg [31:0] A;
   reg [31:0] D_OUT;
   
   reg [1:0]  SIZ;
   wire [1:0]  DSACK;

   wire       RAMOE;
   wire [1:0] RAS;
   wire [3:0] CAS;

   wire [31:0] D = RW20 ? {32{1'bz}} : D_OUT;


`include "common.vinc"
   

   ramcpld uut (
		  
   	        .CLKCPU(CLK), 
		.RESET(RESET),
					
		.AS20(AS20), 
		.DS20(DS20), 
		.RW20(RW20),
 
		.DSACK(DSACK),
		.PUNT (PUNT),
		.SIZ(SIZ), 

		.A(A[23:0]), 
			
		.D (D[31:24]),
		  
		.IDEINT ( 1'b0 ),

		.RAMOE	(RAMOE),
		.CAS	(CAS),
		.RAS	(RAS),
		.RAM_MUX(RAM_MUX)
		
	);

   integer     i;
	initial begin
	   
	   $dumpfile("write_cycle.vcd");
	   $dumpvars(0, write_cycle_tb);
	   
	   RESET = 1;
	   #10;
	   

	   CLK14M = 0;
	   RESET = 0;
	   

	   #142;
		
	   RESET = 1;

	   #142;
	   
	   SIZ = 2'b10;

	   write(32'h00E8004a, 32'h9_0000000);
	   write(32'h00E80048, 32'hE_0000000);
	   
	   write(32'h00E8004a, 32'h0_0000000);
	   write(32'h00E80048, 32'h2_0000000);

	   busidle();

	   for( i = 32'h200000; i < 32'h00210000; i++ ) begin
	   
	      write(i, 0);
	      busidle();
	      read(i);
	      busidle();
	   
	   end

		#1000000;
	   
	   $finish;
	end
   
assign CLK = CLK14M;

always 	begin
    #71; CLK14M = ~CLK14M;
end

PULLUP PUNT_pullup (
.O(PUNT)
);

PULLUP DSACK0_pullup (
.O(DSACK[0]) 
);

PULLUP DSACK1_pullup (
.O(DSACK[1]) 
);

   
endmodule