data/full_repos/permissive/168395472/problems/08_cpu_v2/mem_ctrl.v
 line:7: before: "="
data/verilator_xmls/b4f9a316-a27e-4190-9527-fb5efc675698.xml
module mem_ctrl(
    input clk,
    input [31:0]addr,
    input [31:0]data,
    input we,

    output reg [15:0]data_out = 16'b0
);

always @(posedge clk) begin

end

endmodule
module mem_ctrl(
    input clk,
    input [31:0]addr,
    input [31:0]data,
    input we,

    output reg [15:0]data_out = 16'b0
);


always @(posedge clk) begin

end

endmodule