data/full_repos/permissive/136510272/component/rand32/rand32.v
data/verilator_xmls/beef46a4-237b-491d-b643-aa3c9a339906.xml
module rand32(

    input  wire        clock,
    output reg  [31:0] rnd

);

initial rnd = 32'h00000001;


wire next_bit = rnd[31] ^ rnd[30] ^ rnd[29] ^ rnd[27] ^ rnd[25] ^ rnd[0];


always @(posedge clock) rnd <= { next_bit, rnd[31:1] };

endmodule
module rand32(

    input  wire        clock,
    output reg  [31:0] rnd

);


initial rnd = 32'h00000001;


wire next_bit = rnd[31] ^ rnd[30] ^ rnd[29] ^ rnd[27] ^ rnd[25] ^ rnd[0];


always @(posedge clock) rnd <= { next_bit, rnd[31:1] };

endmodule