data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:9: Unsupported: classes\nclass apb_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:9: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_base_test extends uvm_test;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:10: Define or directive not defined: \'`uvm_component_utils\'\n    `uvm_component_utils(apb_base_test)\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:17: Unsupported: new constructor\n    function new(string name="apb_base_test", uvm_component parent=null);\n             ^~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:17: syntax error, unexpected IDENTIFIER, expecting \')\'\n    function new(string name="apb_base_test", uvm_component parent=null);\n                                                            ^~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:22: syntax error, unexpected IDENTIFIER, expecting \')\'\n    virtual function void build_phase(uvm_phase phase);\n                                                ^~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:31: Unsupported: virtual data type\n        if(!uvm_config_db#(virtual apb_interface)::get(this,"","APB_INTF", apb_env_cfg.apb_mstr_agnt_cfg.apb_intf)) begin\n                           ^~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:32: Define or directive not defined: \'`uvm_fatal\'\n            `uvm_fatal("INTERFACE NOT FOUND ERROR", $sformatf("Could not retrieve apb_interface from uvm_config_db"))\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:46: syntax error, unexpected IDENTIFIER, expecting \')\'\n    virtual function void connect_phase(uvm_phase phase);\n                                                  ^~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:51: syntax error, unexpected IDENTIFIER, expecting \')\'\n    virtual task run_phase(uvm_phase phase);\n                                     ^~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:63: Define or directive not defined: \'`ADDR_WIDTH\'\n    task rd_nd_compare_mem(input [`ADDR_WIDTH-1:0] addr, input [`DATA_WIDTH-1:0] exp_data);\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:63: Define or directive not defined: \'`DATA_WIDTH\'\n    task rd_nd_compare_mem(input [`ADDR_WIDTH-1:0] addr, input [`DATA_WIDTH-1:0] exp_data);\n                                                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:65: syntax error, unexpected IDENTIFIER\n        apb_rd_sequence  rd_seq;\n                         ^~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:68: syntax error, unexpected ::, expecting \';\'\n        rd_seq = apb_rd_sequence::type_id::create("rd_seq", this);\n                                ^~\n                                                                            : ... Perhaps \'apb_rd_sequence\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:87: Define or directive not defined: \'`ADDR_WIDTH\'\n    task rd_data_4m_mem(input [`ADDR_WIDTH-1:0] addr, input bit rand_addr);\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:89: syntax error, unexpected IDENTIFIER\n        apb_rd_sequence  rd_seq;\n                         ^~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:92: syntax error, unexpected ::, expecting \';\'\n        rd_seq = apb_rd_sequence::type_id::create("rd_seq", this);\n                                ^~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:111: Define or directive not defined: \'`ADDR_WIDTH\'\n    task wr_data_2_mem(input [`ADDR_WIDTH-1:0] addr, input [`DATA_WIDTH-1:0] data, input bit rand_addr, input bit rand_data);\n                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:111: Define or directive not defined: \'`DATA_WIDTH\'\n    task wr_data_2_mem(input [`ADDR_WIDTH-1:0] addr, input [`DATA_WIDTH-1:0] data, input bit rand_addr, input bit rand_data);\n                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:113: syntax error, unexpected IDENTIFIER\n        apb_wr_sequence  wr_seq;\n                         ^~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:116: syntax error, unexpected ::, expecting \';\'\n        wr_seq = apb_wr_sequence::type_id::create("wr_seq", this);\n                                ^~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:135: Define or directive not defined: \'`uvm_info\'\n  `uvm_info(get_full_name(), "Begin reset", UVM_NONE)\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:135: syntax error, unexpected \',\'\n  `uvm_info(get_full_name(), "Begin reset", UVM_NONE)\n                           ^\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:138: Define or directive not defined: \'`uvm_info\'\n        `uvm_info(get_full_name(), "Done reset", UVM_NONE)\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:138: syntax error, unexpected \',\'\n        `uvm_info(get_full_name(), "Done reset", UVM_NONE)\n                                 ^\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:148: Define or directive not defined: \'`ADDR_WIDTH\'\n    task generate_mem_rd_err(input [`ADDR_WIDTH-1:0] addr, input bit rand_addr);\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:153: syntax error, unexpected ::, expecting \';\'\n        rd_seq = apb_err_rd_sequence::type_id::create("rd_seq", this);\n                                    ^~\n%Warning-ENDLABEL: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:161: End label \'generate_mem_rd_err\' does not match begin label \'reset_dut\'\n    endtask: generate_mem_rd_err\n             ^~~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:172: Define or directive not defined: \'`ADDR_WIDTH\'\n    task generate_mem_wr_err(input [`ADDR_WIDTH-1:0] addr, input [`DATA_WIDTH-1:0] data, input bit rand_addr, input bit rand_data);\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:172: Define or directive not defined: \'`DATA_WIDTH\'\n    task generate_mem_wr_err(input [`ADDR_WIDTH-1:0] addr, input [`DATA_WIDTH-1:0] data, input bit rand_addr, input bit rand_data);\n                                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:174: syntax error, unexpected IDENTIFIER\n        apb_err_wr_sequence  wr_seq;\n                             ^~~~~~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:177: syntax error, unexpected ::, expecting \';\'\n        wr_seq = apb_err_wr_sequence::type_id::create("wr_seq", this);\n                                    ^~\n%Error: data/full_repos/permissive/178106827/verif/tests/apb_base_test.sv:189: syntax error, unexpected endclass\nendclass : apb_base_test\n^~~~~~~~\n%Error: Exiting due to 32 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function void connect_phase(uvm_phase phase);
        super.connect_phase(phase);
    endfunction
function void connect_phase(uvm_phase phase);

        super.connect_phase(phase);
    endfunction