data/full_repos/permissive/108698528/clock_divider.v
data/verilator_xmls/454edddd-b4e6-4385-90bb-8ab9f2df1e57.xml
module clock_divider(clk, out);


	parameter BITS = 8;
	parameter DIV  = 16;

	input clk;
	output reg out;

	reg [BITS-1:0] count;
	reg clr;

	

	initial begin
		out = 0;
		count = 0;
	end

	always @(posedge clk) begin
		if(count == (DIV - 1)) begin
			count <= 0;
			out <= ~out;
		end else begin
			count <= count + 1;
		end
	end

endmodule
module clock_divider(clk, out);



	parameter BITS = 8;
	parameter DIV  = 16;

	input clk;
	output reg out;

	reg [BITS-1:0] count;
	reg clr;

	

	initial begin
		out = 0;
		count = 0;
	end

	always @(posedge clk) begin
		if(count == (DIV - 1)) begin
			count <= 0;
			out <= ~out;
		end else begin
			count <= count + 1;
		end
	end

endmodule