data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:375: Cell has missing pin: \'alt_clockout\'\n simpledcm_SP #(.MULTIPLY(DCMMULTIPLY), .DIVIDE(DCMDIVIDE), .PERIOD(DCMPERIOD)) mydcm (\n                                                                                ^~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:100: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                    : ... Top module \'dummy_dcm_diff_input\'\nmodule dummy_dcm_diff_input #(\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                    : ... Top module \'simplepll_ADV\'\nmodule simplepll_ADV #(\n       ^~~~~~~~~~~~~\n                                                                                    : ... Top module \'simplepll_BASE\'\nmodule simplepll_BASE #(\n       ^~~~~~~~~~~~~~\n                                                                                    : ... Top module \'plldcm\'\nmodule plldcm #(parameter OVERALL_DIVIDE=1, PLLMULTIPLY=1, PLLDIVIDE=1, PLLPERIOD=10.0, DCMMULTIPLY=1, DCMDIVIDE=1, DCMPERIOD="10.0") (\n       ^~~~~~\n                                                                                    : ... Top module \'clock_select\'\nmodule clock_select #(\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:319: Cannot find file containing module: \'DCM_SP\'\n DCM_SP #(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/DCM_SP.sv\n             DCM_SP\n             DCM_SP.v\n             DCM_SP.sv\n             obj_dir/DCM_SP\n             obj_dir/DCM_SP.v\n             obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:256: Cannot find file containing module: \'DCM_CLKGEN\'\n DCM_CLKGEN #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:39: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:393: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_0s (.I0(clock[0]), .I1(clock[1]), .S(select[0]), .O(clock_0s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:394: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_1s (.I0(clock[2]), .I1(clock[3]), .S(select[0]), .O(clock_1s));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:395: Cannot find file containing module: \'BUFGMUX\'\n BUFGMUX #(.CLK_SEL_TYPE("SYNC")) clock_sel_sx (.I0(clock_0s), .I1(clock_1s), .S(select[1]), .O(clock_out));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:200: Cannot find file containing module: \'PLL_BASE\'\n PLL_BASE #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:113: Cannot find file containing module: \'PLL_ADV\'\n PLL_ADV #(\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:18: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS mybuf_raw1 (.I(clock_p), .IB(clock_n), .O(clock_raw1));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/plldcm.v:21: Cannot find file containing module: \'BUFG\'\n BUFG mybuf_raw2 (.I(clock_raw2), .O(clock_out));\n ^~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n'
module simpledcm_SP #(
	parameter ALT_CLOCKOUT_DIVIDE=2.0,
	parameter MULTIPLY=4,
	parameter DIVIDE=1,
	parameter PERIOD=10.0,
	parameter CLKIN_DIVIDE_BY_2 = "FALSE"
) (
	input clockin,
	input reset,
	output clockout,
	output clockout180,
	output alt_clockout,
	output locked
);
	wire fb;



	DCM_SP #(
		.CLKDV_DIVIDE(ALT_CLOCKOUT_DIVIDE),

		.CLKFX_DIVIDE(DIVIDE),
		.CLKFX_MULTIPLY(MULTIPLY),
		.CLKIN_DIVIDE_BY_2(CLKIN_DIVIDE_BY_2),
		.CLKIN_PERIOD(PERIOD),
		.CLKOUT_PHASE_SHIFT("NONE"),
		.CLK_FEEDBACK("1X"),
		.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),

		.DLL_FREQUENCY_MODE("LOW"),
		.DUTY_CYCLE_CORRECTION("TRUE"),
		.PHASE_SHIFT(0),
		.STARTUP_WAIT("FALSE")
	) DCM_SP_inst (
		.CLK0(fb),
		.CLK180(),
		.CLK270(),
		.CLK2X(),
		.CLK2X180(),
		.CLK90(),
		.CLKDV(alt_clockout),
		.CLKFX(clockout),
		.CLKFX180(clockout180),
		.LOCKED(locked),
		.PSDONE(),
		.STATUS(),
		.CLKFB(fb),
		.CLKIN(clockin),
		.PSCLK(1'b0),
		.PSEN(1'b0),
		.PSINCDEC(1'b0),
		.DSSEN(1'b0),
		.RST(reset)
	);
endmodule
module simpledcm_SP #(
	parameter ALT_CLOCKOUT_DIVIDE=2.0,
	parameter MULTIPLY=4,
	parameter DIVIDE=1,
	parameter PERIOD=10.0,
	parameter CLKIN_DIVIDE_BY_2 = "FALSE"
) (
	input clockin,
	input reset,
	output clockout,
	output clockout180,
	output alt_clockout,
	output locked
);

	wire fb;



	DCM_SP #(
		.CLKDV_DIVIDE(ALT_CLOCKOUT_DIVIDE),

		.CLKFX_DIVIDE(DIVIDE),
		.CLKFX_MULTIPLY(MULTIPLY),
		.CLKIN_DIVIDE_BY_2(CLKIN_DIVIDE_BY_2),
		.CLKIN_PERIOD(PERIOD),
		.CLKOUT_PHASE_SHIFT("NONE"),
		.CLK_FEEDBACK("1X"),
		.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),

		.DLL_FREQUENCY_MODE("LOW"),
		.DUTY_CYCLE_CORRECTION("TRUE"),
		.PHASE_SHIFT(0),
		.STARTUP_WAIT("FALSE")
	) DCM_SP_inst (
		.CLK0(fb),
		.CLK180(),
		.CLK270(),
		.CLK2X(),
		.CLK2X180(),
		.CLK90(),
		.CLKDV(alt_clockout),
		.CLKFX(clockout),
		.CLKFX180(clockout180),
		.LOCKED(locked),
		.PSDONE(),
		.STATUS(),
		.CLKFB(fb),
		.CLKIN(clockin),
		.PSCLK(1'b0),
		.PSEN(1'b0),
		.PSINCDEC(1'b0),
		.DSSEN(1'b0),
		.RST(reset)
	);
endmodule