data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/latch.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/latch.v:43: Multiple top level modules\n                                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                              : ... Top module \'LATCH\'\nmodule LATCH (\n       ^~~~~\n                                                                                                              : ... Top module \'LATCHR\'\nmodule LATCHR (\n       ^~~~~~\n                                                                                                              : ... Top module \'LATCHRN\'\nmodule LATCHRN (\n       ^~~~~~~\n                                                                                                              : ... Top module \'LATCHS\'\nmodule LATCHS (\n       ^~~~~~\n                                                                                                              : ... Top module \'LATCHSN\'\nmodule LATCHSN (\n       ^~~~~~~\n                                                                                                              : ... Top module \'LATCHSR\'\nmodule LATCHSR (\n       ^~~~~~~\n                                                                                                              : ... Top module \'LATCHSNRN\'\nmodule LATCHSNRN (\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module LATCHSNRN (
  input RSTN,
  input SETN,
  input WE,
  input D,
  output Q,
  output QN
);

reg q_reg;


always @ (RSTN or SETN or WE or D) begin
  if (~RSTN) begin
    q_reg <= 1'b0;
  end else if (~SETN) begin
    q_reg <= 1'b1;
  end else if (1'b1 == WE) begin
    q_reg <= D;
  end
end


`ifndef ENABLE_FORMAL_VERIFICATION
  assign Q = q_reg;
  assign QN = ~q_reg;
`else
  assign Q = 1'bZ;
  assign QN = !Q;
`endif

endmodule
module LATCHSNRN (
  input RSTN,
  input SETN,
  input WE,
  input D,
  output Q,
  output QN
);


reg q_reg;


always @ (RSTN or SETN or WE or D) begin
  if (~RSTN) begin
    q_reg <= 1'b0;
  end else if (~SETN) begin
    q_reg <= 1'b1;
  end else if (1'b1 == WE) begin
    q_reg <= D;
  end
end


`ifndef ENABLE_FORMAL_VERIFICATION
  assign Q = q_reg;
  assign QN = ~q_reg;
`else
  assign Q = 1'bZ;
  assign QN = !Q;
`endif

endmodule