data/full_repos/permissive/201224775/rtl/mem/scarv_soc_bram_dual_synth_lattice.v
1: b'%Warning-WIDTH: data/full_repos/permissive/201224775/rtl/mem/scarv_soc_bram_dual_synth_lattice.v:43: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                   : ... In instance scarv_soc_bram_dual\nwire [BRAM_ADDR_WIDTH-1:0] addra_idx = addra[BRAM_ADDR_WIDTH-1:2];\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/201224775/rtl/mem/scarv_soc_bram_dual_synth_lattice.v:58: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n                                                                                                   : ... In instance scarv_soc_bram_dual\n            BRAM_0[addra_idx]<= dina[0*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/201224775/rtl/mem/scarv_soc_bram_dual_synth_lattice.v:60: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n                                                                                                   : ... In instance scarv_soc_bram_dual\n        ram_data_a[0*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_0[addra_idx];\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/201224775/rtl/mem/scarv_soc_bram_dual_synth_lattice.v:66: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n                                                                                                   : ... In instance scarv_soc_bram_dual\n            BRAM_1[addra_idx]<= dina[1*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/201224775/rtl/mem/scarv_soc_bram_dual_synth_lattice.v:68: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n                                                                                                   : ... In instance scarv_soc_bram_dual\n        ram_data_a[1*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_1[addra_idx];\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/201224775/rtl/mem/scarv_soc_bram_dual_synth_lattice.v:74: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n                                                                                                   : ... In instance scarv_soc_bram_dual\n            BRAM_2[addra_idx]<= dina[2*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/201224775/rtl/mem/scarv_soc_bram_dual_synth_lattice.v:76: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n                                                                                                   : ... In instance scarv_soc_bram_dual\n        ram_data_a[2*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_2[addra_idx];\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/201224775/rtl/mem/scarv_soc_bram_dual_synth_lattice.v:82: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n                                                                                                   : ... In instance scarv_soc_bram_dual\n            BRAM_3[addra_idx]<= dina[3*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/201224775/rtl/mem/scarv_soc_bram_dual_synth_lattice.v:84: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n                                                                                                   : ... In instance scarv_soc_bram_dual\n        ram_data_a[3*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_3[addra_idx];\n                                                                ^\n%Error: Exiting due to 9 warning(s)\n'
module scarv_soc_bram_dual (

input  wire           clka        ,
input  wire           rsta        ,

input  wire           ena         ,
input  wire [   3:0]  wea         ,
input  wire [LW-1:0]  addra       ,
input  wire [  31:0]  dina        ,
output wire [  31:0]  douta       ,

input  wire           enb         ,
input  wire [   3:0]  web         ,
input  wire [LW-1:0]  addrb       ,
input  wire [  31:0]  dinb        ,
output wire [  31:0]  doutb        

);


parameter   WRITE_EN = 1;


parameter   DEPTH = 1024;
localparam  LW    = $clog2(DEPTH);


parameter [255*8:0] MEMH_FILE = "";

localparam BRAM_DATA_WIDTH = 32    ;
localparam BRAM_BYTE_WIDTH = 8     ;
localparam NB_COL          = BRAM_DATA_WIDTH/BRAM_BYTE_WIDTH;
localparam BRAM_DEPTH      = DEPTH / NB_COL;
localparam BRAM_ADDR_WIDTH = LW;

wire [BRAM_ADDR_WIDTH-1:0] addra_idx = addra[BRAM_ADDR_WIDTH-1:2];

reg [BRAM_BYTE_WIDTH-1:0] BRAM_0 [0:BRAM_DEPTH-1];
reg [BRAM_BYTE_WIDTH-1:0] BRAM_1 [0:BRAM_DEPTH-1];
reg [BRAM_BYTE_WIDTH-1:0] BRAM_2 [0:BRAM_DEPTH-1];
reg [BRAM_BYTE_WIDTH-1:0] BRAM_3 [0:BRAM_DEPTH-1];

reg [(NB_COL*BRAM_BYTE_WIDTH)-1:0] ram_data_a ;

assign douta = ram_data_a;
assign doutb = 0;

always @(posedge clka) begin
    if (ena) begin
        if (wea[0]) begin
            BRAM_0[addra_idx]<= dina[0*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];
        end
        ram_data_a[0*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_0[addra_idx];
    end
end
always @(posedge clka) begin
    if (ena) begin
        if (wea[1]) begin
            BRAM_1[addra_idx]<= dina[1*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];
        end
        ram_data_a[1*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_1[addra_idx];
    end
end
always @(posedge clka) begin
    if (ena) begin
        if (wea[2]) begin
            BRAM_2[addra_idx]<= dina[2*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];
        end
        ram_data_a[2*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_2[addra_idx];
    end
end
always @(posedge clka) begin
    if (ena) begin
        if (wea[3]) begin
            BRAM_3[addra_idx]<= dina[3*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];
        end
        ram_data_a[3*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_3[addra_idx];
    end
end

endmodule
module scarv_soc_bram_dual (

input  wire           clka        ,
input  wire           rsta        ,

input  wire           ena         ,
input  wire [   3:0]  wea         ,
input  wire [LW-1:0]  addra       ,
input  wire [  31:0]  dina        ,
output wire [  31:0]  douta       ,

input  wire           enb         ,
input  wire [   3:0]  web         ,
input  wire [LW-1:0]  addrb       ,
input  wire [  31:0]  dinb        ,
output wire [  31:0]  doutb        

);



parameter   WRITE_EN = 1;


parameter   DEPTH = 1024;
localparam  LW    = $clog2(DEPTH);


parameter [255*8:0] MEMH_FILE = "";

localparam BRAM_DATA_WIDTH = 32    ;
localparam BRAM_BYTE_WIDTH = 8     ;
localparam NB_COL          = BRAM_DATA_WIDTH/BRAM_BYTE_WIDTH;
localparam BRAM_DEPTH      = DEPTH / NB_COL;
localparam BRAM_ADDR_WIDTH = LW;

wire [BRAM_ADDR_WIDTH-1:0] addra_idx = addra[BRAM_ADDR_WIDTH-1:2];

reg [BRAM_BYTE_WIDTH-1:0] BRAM_0 [0:BRAM_DEPTH-1];
reg [BRAM_BYTE_WIDTH-1:0] BRAM_1 [0:BRAM_DEPTH-1];
reg [BRAM_BYTE_WIDTH-1:0] BRAM_2 [0:BRAM_DEPTH-1];
reg [BRAM_BYTE_WIDTH-1:0] BRAM_3 [0:BRAM_DEPTH-1];

reg [(NB_COL*BRAM_BYTE_WIDTH)-1:0] ram_data_a ;

assign douta = ram_data_a;
assign doutb = 0;

always @(posedge clka) begin
    if (ena) begin
        if (wea[0]) begin
            BRAM_0[addra_idx]<= dina[0*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];
        end
        ram_data_a[0*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_0[addra_idx];
    end
end
always @(posedge clka) begin
    if (ena) begin
        if (wea[1]) begin
            BRAM_1[addra_idx]<= dina[1*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];
        end
        ram_data_a[1*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_1[addra_idx];
    end
end
always @(posedge clka) begin
    if (ena) begin
        if (wea[2]) begin
            BRAM_2[addra_idx]<= dina[2*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];
        end
        ram_data_a[2*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_2[addra_idx];
    end
end
always @(posedge clka) begin
    if (ena) begin
        if (wea[3]) begin
            BRAM_3[addra_idx]<= dina[3*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH];
        end
        ram_data_a[3*BRAM_BYTE_WIDTH+:BRAM_BYTE_WIDTH] <= BRAM_3[addra_idx];
    end
end

endmodule