data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_WeightsRAM.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_WeightsRAM.v:30: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_WeightsRAM.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_WeightsRAM.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_WeightsRAM.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_WeightsRAM.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_WeightsRAM.v:28: Cannot find file containing module: \'WeightsRAM_R\'\n    WeightsRAM_R uut( .clk(clk), .addr(addr), .weights(weights));\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/WeightsRAM_R\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/WeightsRAM_R.v\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/WeightsRAM_R.sv\n             WeightsRAM_R\n             WeightsRAM_R.v\n             WeightsRAM_R.sv\n             obj_dir/WeightsRAM_R\n             obj_dir/WeightsRAM_R.v\n             obj_dir/WeightsRAM_R.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_WeightsRAM;
    reg clk;
    reg [2:0] addr;
    wire [127:0] weights;
    
    WeightsRAM_R uut( .clk(clk), .addr(addr), .weights(weights));
    
    always #5 clk = ~clk;
    
    initial begin
        clk = 0;
        addr = 3'd0;
        #10;
        addr = 3'd1;
        #10;
        addr = 3'd5;
        #10;
        addr = 3'd7;
        #10;
    end
    
    
endmodule
module TB_WeightsRAM;

    reg clk;
    reg [2:0] addr;
    wire [127:0] weights;
    
    WeightsRAM_R uut( .clk(clk), .addr(addr), .weights(weights));
    
    always #5 clk = ~clk;
    
    initial begin
        clk = 0;
        addr = 3'd0;
        #10;
        addr = 3'd1;
        #10;
        addr = 3'd5;
        #10;
        addr = 3'd7;
        #10;
    end
    
    
endmodule