data/full_repos/permissive/210844779/lab6/6.4/fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/210844779/lab6/6.4/fifo.v:23: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'count1\' generates 32 bits.\n                                                                       : ... In instance fifo\n        waddr=count1;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab6/6.4/fifo.v:24: Bit extraction of array[127:0] requires 7 bit index, not 8 bits.\n                                                                       : ... In instance fifo\n        mem[waddr]=din;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab6/6.4/fifo.v:30: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'count2\' generates 32 bits.\n                                                                       : ... In instance fifo\n        raddr=count2;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab6/6.4/fifo.v:31: Bit extraction of array[127:0] requires 7 bit index, not 8 bits.\n                                                                       : ... In instance fifo\n        dout=mem[raddr];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab6/6.4/fifo.v:38: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'count2\' generates 32 bits.\n                                                                       : ... In instance fifo\n        raddr=count2;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab6/6.4/fifo.v:39: Bit extraction of array[127:0] requires 7 bit index, not 8 bits.\n                                                                       : ... In instance fifo\n        dout=mem[raddr];\n                ^\n%Error: Exiting due to 6 warning(s)\n'
module fifo(din,clk,rst,we,re,full,emp,dout);
  input [7:0] din;
  input clk,rst,we,re;
  output reg full,emp;
  output reg [7:0]dout;
  
  reg [7:0]waddr,raddr;
  reg [7:0]mem[127:0];
  integer count,count1,count2;
  
  always@(posedge clk,posedge rst)
  begin
    if (rst)
      begin
        count=-1;
        count1=-1;
        count2=-1;
      end
    else if (we==1 && full==0)
      begin
        count=count+1;
        count1=count1+1;
        waddr=count1;
        mem[waddr]=din;
      end
      
    else if (re==1 && emp==0)
      begin
        count2=count2+1;
        raddr=count2;
        dout=mem[raddr];
         count=count-1;
      end
	  
	else if (re==1 && emp==0)
      begin
        count2=count2+1;
        raddr=count2;
        dout=mem[raddr];
         count=count-1;
	  end
    end
      
  
  always@(posedge clk,posedge rst)
  begin
    if (rst)
      begin
        full=0;
        emp=1;
      end
    else if (count==-1)
      emp=1;
    else if (count==127)
      full=1;
    else
      begin
        full=0;
        emp=0;
      end
  end
  
endmodule
module fifo(din,clk,rst,we,re,full,emp,dout);

  input [7:0] din;
  input clk,rst,we,re;
  output reg full,emp;
  output reg [7:0]dout;
  
  reg [7:0]waddr,raddr;
  reg [7:0]mem[127:0];
  integer count,count1,count2;
  
  always@(posedge clk,posedge rst)
  begin
    if (rst)
      begin
        count=-1;
        count1=-1;
        count2=-1;
      end
    else if (we==1 && full==0)
      begin
        count=count+1;
        count1=count1+1;
        waddr=count1;
        mem[waddr]=din;
      end
      
    else if (re==1 && emp==0)
      begin
        count2=count2+1;
        raddr=count2;
        dout=mem[raddr];
         count=count-1;
      end
	  
	else if (re==1 && emp==0)
      begin
        count2=count2+1;
        raddr=count2;
        dout=mem[raddr];
         count=count-1;
	  end
    end
      
  
  always@(posedge clk,posedge rst)
  begin
    if (rst)
      begin
        full=0;
        emp=1;
      end
    else if (count==-1)
      emp=1;
    else if (count==127)
      full=1;
    else
      begin
        full=0;
        emp=0;
      end
  end
  
endmodule