data/full_repos/permissive/100638358/leds.v
1: b'%Warning-WIDTH: data/full_repos/permissive/100638358/leds.v:10: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'soma\' generates 4 bits.\n                                                              : ... In instance top\n  counter<= counter+soma;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100638358/leds.v:23: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh14\' generates 32 or 5 bits.\n                                                              : ... In instance top\n   soma=20;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/100638358/leds.v:27: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh1e\' generates 32 or 5 bits.\n                                                              : ... In instance top\n   soma=30;\n       ^\n%Error: Exiting due to 3 warning(s)\n'
module top(input CLOCK_50, input [3:0]SW,  output reg [7:0]LEDR, output reg [0:0]LEDG);

reg[31:0] counter;
reg[3:0] soma=1;

always @(posedge CLOCK_50)
begin
	if(counter<=50000000)
	begin
		counter<= counter+soma;
	end
	else
	begin
		counter<=0;
		LEDR[0]<=~LEDR[0];
	end
		if(SW[0]==1)
		begin
			soma=10;
		end
		if(SW[1]==1)
		begin
			soma=20;
		end
		if(SW[2]==1)
		begin
			soma=30;
		end
	if(counter == 25000000)
	begin 
		LEDG <=~LEDG;
	end
		
	
end
endmodule
module top(input CLOCK_50, input [3:0]SW,  output reg [7:0]LEDR, output reg [0:0]LEDG);


reg[31:0] counter;
reg[3:0] soma=1;

always @(posedge CLOCK_50)
begin
	if(counter<=50000000)
	begin
		counter<= counter+soma;
	end
	else
	begin
		counter<=0;
		LEDR[0]<=~LEDR[0];
	end
		if(SW[0]==1)
		begin
			soma=10;
		end
		if(SW[1]==1)
		begin
			soma=20;
		end
		if(SW[2]==1)
		begin
			soma=30;
		end
	if(counter == 25000000)
	begin 
		LEDG <=~LEDG;
	end
		
	
end
endmodule