data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v
 line:46: before: ""DPI-C""
1: b'%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v:104: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n    transactor_log = $fopen("transactor_log.txt");\n                     ^~~~~~\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v:105: syntax error, unexpected \'@\'\n    @(posedge p.core.wb_clk);\n    ^\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v:118: syntax error, unexpected \'@\'\n    @(posedge wb_clk);\n    ^\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v:132: syntax error, unexpected \'@\'\n        @(posedge wb_clk);\n        ^\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v:135: Unsupported: wait statements\n        wait((ready_from_bus || error_from_bus) == 1\'b1);\n        ^~~~\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v:152: syntax error, unexpected \'@\'\n    @(posedge wb_clk);\n    ^\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v:161: syntax error, unexpected \'@\'\n    @(posedge wb_clk);\n    ^\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v:174: syntax error, unexpected \'@\'\n        @(posedge wb_clk);\n        ^\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v:177: Unsupported: wait statements\n        wait((ready_from_bus || error_from_bus) == 1\'b1);\n        ^~~~\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v:178: syntax error, unexpected \'@\'\n        @(posedge wb_clk);\n        ^\n%Error: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/core_wrapper.v:197: syntax error, unexpected \'@\'\n    @(posedge wb_clk);\n    ^\n%Error: Exiting due to 11 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module core_wrapper(

   input             wb_clk,
   input             wb_rst,
   input             wb_ack,
   input             wb_err,
   input             wb_stall,
   output            wb_cyc,
   output            wb_stb,
   input   [31:0]    wb_dat_i,
   output            wb_we,
   output   [3:0]    wb_sel,
   output  [31:0]    wb_adr,
   output  [31:0]    wb_dat_o

);


import "DPI-C" context task run_testbench();

reg        request;
reg        write;
reg [31:0] address;
reg [31:0] data_to_bus;
reg [3:0]  sel;
reg        reset;
reg        busy;
reg [31:0] data_from_bus;
reg        ready_from_bus;
reg        error_from_bus;

initial begin
   request      <= 1'b0;
   write        <= 1'b0;
   address      <= 32'b0;
   sel          <= 4'b0;
   data_to_bus  <= 32'b0;
end

buslayer_master master_interface(


   .wb_clk(wb_clk),
   .wb_rst(wb_rst),
   .wb_ack(wb_ack),
   .wb_err(wb_err),
   .wb_stall(wb_stall),
   .wb_cyc(wb_cyc),
   .wb_stb(wb_stb),
   .wb_dat_i(wb_dat_i),
   .wb_we(wb_we),
   .wb_sel(wb_sel),
   .wb_adr(wb_adr),
   .wb_dat_o(wb_dat_o),



   .request(request),
   .write(write),
   .address(address),
   .data_to_bus(data_to_bus),
   .byte_sel(sel),
   .reset(reset),
   .busy(busy),
   .data_from_bus(data_from_bus),
   .ready_from_bus(ready_from_bus),
   .error_from_bus(error_from_bus)
);





integer transactor_log;

initial begin
    transactor_log = $fopen("transactor_log.txt");
    @(posedge p.core.wb_clk);
    run_testbench();

    $fclose(p.core.transactor_log);
    $finish();
end


export "DPI-C" task write_transaction;
task write_transaction(input int addressIn, input int dataIn,
                      input byte byteSelIn, output byte errorOut);
begin

    @(posedge wb_clk);

    $fdisplay(transactor_log,
              "wishbone-WRITE (START): time:%0t\taddr:%x\tdata:%x\tbyteSel:%x",
              $time, addressIn, dataIn, byteSelIn);

    if (reset == 1'b0 && busy == 1'b0) begin


        address     <= addressIn;
        data_to_bus <= dataIn;
        sel         <= byteSelIn[3:0];
        write       <= 1'b1;
        request     <= 1'b1;
        @(posedge wb_clk);


        wait((ready_from_bus || error_from_bus) == 1'b1);



        request     <= 1'b0;
        write       <= 1'b0;
        sel         <= 4'b0;
        errorOut           <= {{7'b0}, {error_from_bus}};
        $fdisplay(transactor_log,
                  "wishbone-WRITE  (STOP): time:%0t\terror:%d",
                  $time, error_from_bus);
    end
    else begin
        errorOut    <= 8'b1;
        $fdisplay(transactor_log, "wishbone-WRITE  (STOP): time:%0t\terror:1", $time);
    end

    @(posedge wb_clk);
end
endtask;

export "DPI-C" task read_transaction;
task read_transaction(input int addressIn, input int byteSelIn,
                     output int dataOut, output byte errorOut);
begin

    @(posedge wb_clk);

    $fdisplay(transactor_log,
              "wishbone-READ  (START): time:%0t\taddr:%x\tbyteSel:%x",
              $time, addressIn, byteSelIn);

    if (reset == 1'b0 && busy == 1'b0) begin


        address     <= addressIn;
        sel         <= byteSelIn[3:0];
        write       <= 1'b0;
        request     <= 1'b1;
        @(posedge wb_clk);


        wait((ready_from_bus || error_from_bus) == 1'b1);
        @(posedge wb_clk);



        request     <= 1'b0;
        write       <= 1'b0;
        sel         <= 4'b0;
        errorOut           <= {{7'b0}, {error_from_bus}};
        dataOut            <= data_from_bus;

        $fdisplay(transactor_log,
                  "wishbone-READ   (STOP): time:%0t\tdata:%x\terror:%x",
                  $time, data_from_bus, error_from_bus);
    end
    else begin
        errorOut    <= 8'b1;
        $fdisplay(transactor_log, "wishbone-READ  (STOP): time:%0t\terror:1", $time);
    end

    @(posedge wb_clk);
end
endtask;


endmodule
module core_wrapper(

   input             wb_clk,
   input             wb_rst,
   input             wb_ack,
   input             wb_err,
   input             wb_stall,
   output            wb_cyc,
   output            wb_stb,
   input   [31:0]    wb_dat_i,
   output            wb_we,
   output   [3:0]    wb_sel,
   output  [31:0]    wb_adr,
   output  [31:0]    wb_dat_o

);



import "DPI-C" context task run_testbench();

reg        request;
reg        write;
reg [31:0] address;
reg [31:0] data_to_bus;
reg [3:0]  sel;
reg        reset;
reg        busy;
reg [31:0] data_from_bus;
reg        ready_from_bus;
reg        error_from_bus;

initial begin
   request      <= 1'b0;
   write        <= 1'b0;
   address      <= 32'b0;
   sel          <= 4'b0;
   data_to_bus  <= 32'b0;
end

buslayer_master master_interface(


   .wb_clk(wb_clk),
   .wb_rst(wb_rst),
   .wb_ack(wb_ack),
   .wb_err(wb_err),
   .wb_stall(wb_stall),
   .wb_cyc(wb_cyc),
   .wb_stb(wb_stb),
   .wb_dat_i(wb_dat_i),
   .wb_we(wb_we),
   .wb_sel(wb_sel),
   .wb_adr(wb_adr),
   .wb_dat_o(wb_dat_o),



   .request(request),
   .write(write),
   .address(address),
   .data_to_bus(data_to_bus),
   .byte_sel(sel),
   .reset(reset),
   .busy(busy),
   .data_from_bus(data_from_bus),
   .ready_from_bus(ready_from_bus),
   .error_from_bus(error_from_bus)
);





integer transactor_log;

initial begin
    transactor_log = $fopen("transactor_log.txt");
    @(posedge p.core.wb_clk);
    run_testbench();

    $fclose(p.core.transactor_log);
    $finish();
end


export "DPI-C" task write_transaction;
task write_transaction(input int addressIn, input int dataIn,
                      input byte byteSelIn, output byte errorOut);
begin

    @(posedge wb_clk);

    $fdisplay(transactor_log,
              "wishbone-WRITE (START): time:%0t\taddr:%x\tdata:%x\tbyteSel:%x",
              $time, addressIn, dataIn, byteSelIn);

    if (reset == 1'b0 && busy == 1'b0) begin


        address     <= addressIn;
        data_to_bus <= dataIn;
        sel         <= byteSelIn[3:0];
        write       <= 1'b1;
        request     <= 1'b1;
        @(posedge wb_clk);


        wait((ready_from_bus || error_from_bus) == 1'b1);



        request     <= 1'b0;
        write       <= 1'b0;
        sel         <= 4'b0;
        errorOut           <= {{7'b0}, {error_from_bus}};
        $fdisplay(transactor_log,
                  "wishbone-WRITE  (STOP): time:%0t\terror:%d",
                  $time, error_from_bus);
    end
    else begin
        errorOut    <= 8'b1;
        $fdisplay(transactor_log, "wishbone-WRITE  (STOP): time:%0t\terror:1", $time);
    end

    @(posedge wb_clk);
end
endtask;

export "DPI-C" task read_transaction;
task read_transaction(input int addressIn, input int byteSelIn,
                     output int dataOut, output byte errorOut);
begin

    @(posedge wb_clk);

    $fdisplay(transactor_log,
              "wishbone-READ  (START): time:%0t\taddr:%x\tbyteSel:%x",
              $time, addressIn, byteSelIn);

    if (reset == 1'b0 && busy == 1'b0) begin


        address     <= addressIn;
        sel         <= byteSelIn[3:0];
        write       <= 1'b0;
        request     <= 1'b1;
        @(posedge wb_clk);


        wait((ready_from_bus || error_from_bus) == 1'b1);
        @(posedge wb_clk);



        request     <= 1'b0;
        write       <= 1'b0;
        sel         <= 4'b0;
        errorOut           <= {{7'b0}, {error_from_bus}};
        dataOut            <= data_from_bus;

        $fdisplay(transactor_log,
                  "wishbone-READ   (STOP): time:%0t\tdata:%x\terror:%x",
                  $time, data_from_bus, error_from_bus);
    end
    else begin
        errorOut    <= 8'b1;
        $fdisplay(transactor_log, "wishbone-READ  (STOP): time:%0t\terror:1", $time);
    end

    @(posedge wb_clk);
end
endtask;


endmodule