data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/gpif2/gpif2_error_checker.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/gpif2/gpif2_error_checker.v:111: Cannot find file containing module: 'axi_packet_gate'\n    axi_packet_gate #(.WIDTH(32), .SIZE(SIZE), .USE_AS_BUFF(0)) gate_xfer\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/gpif2,data/full_repos/permissive/214858095/axi_packet_gate\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/gpif2,data/full_repos/permissive/214858095/axi_packet_gate.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/gpif2,data/full_repos/permissive/214858095/axi_packet_gate.sv\n             axi_packet_gate\n             axi_packet_gate.v\n             axi_packet_gate.sv\n             obj_dir/axi_packet_gate\n             obj_dir/axi_packet_gate.v\n             obj_dir/axi_packet_gate.sv\n%Error: Exiting due to 1 error(s)\n"
module gpif2_error_checker
  #(parameter SIZE = 9)
  (input clk, input reset, input clear,
   input [31:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
   output [31:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
   output bus_error, output [63:0] debug);

    wire [31:0] gate_tdata;
    wire gate_tlast, gate_terror;
    wire gate_tvalid, gate_tready;

    localparam STATE_HDR = 0;
    localparam STATE_FWD = 1;
    localparam STATE_EOF = 2;
    localparam STATE_WAIT = 3;
    reg [1:0] state;

    reg [15:0] lines32;
    reg [11:0] seq_id_ref;
    reg        seq_id_bad;
    reg        seq_id_wayoff;
   

    wire [15:0] hdr_bytes = i_tdata[15:0] + 3;
    wire [15:0] hdr_lines32 = {2'b0, hdr_bytes[15:2]};
    wire [11:0] seq_id_actual = i_tdata[27:16];
   
   
    wire obviously_bad_hdr = (hdr_lines32 == 16'h0) || (hdr_lines32 > (1 << SIZE));

    always @(posedge clk) begin
        if (reset | clear) begin
            state <= STATE_HDR;
            lines32 <= 16'b0;
	    seq_id_ref <= 12'h0;
	    seq_id_bad <= 0;
	    seq_id_wayoff <= 0;
	   
	   
        end
        else case (state)

        STATE_HDR: begin
            if (i_tvalid && i_tready) begin
                if (obviously_bad_hdr)           state <= STATE_WAIT;
                else if (hdr_lines32 == 16'h1)  state <= STATE_HDR;
                else if (hdr_lines32 == 16'h2)  state <= STATE_EOF;
                else                            state <= STATE_FWD;
	        seq_id_bad <= (seq_id_actual != seq_id_ref);
	        seq_id_wayoff <= (seq_id_actual != seq_id_ref) |
				(seq_id_actual != seq_id_ref+1) |
				(seq_id_actual != seq_id_ref+2) |
				(seq_id_actual != seq_id_ref+3);
	        if (seq_id_actual != seq_id_ref)
		 seq_id_ref <= seq_id_actual + 1;
	        else
		 seq_id_ref <= seq_id_ref + 1;
            end
            lines32 <= hdr_lines32;
	    
        end

        STATE_FWD: begin
            if (i_tvalid && i_tready) begin
                if (lines32 == 16'h3) state <= STATE_EOF;
                lines32 <= lines32 - 1'b1;
            end
        end

        STATE_EOF: begin
	   if (i_tvalid && i_tready) 
	     if (gate_tlast) state <= STATE_HDR;
	     else state <= STATE_WAIT;
        end

        STATE_WAIT: begin
            if (i_tvalid && i_tready && i_tlast) state <= STATE_HDR;
        end

        endcase
    end

    assign bus_error = (gate_terror && gate_tvalid && gate_tready) || ((state == STATE_HDR) && i_tvalid && i_tready && obviously_bad_hdr);
    assign gate_tlast = (state == STATE_HDR)? (hdr_lines32 == 16'h1) : (state == STATE_EOF);
    assign gate_tdata = i_tdata;
    assign gate_tvalid = i_tvalid && ((state == STATE_HDR)? !obviously_bad_hdr : (state != STATE_WAIT));
    assign i_tready = gate_tready;

    axi_packet_gate #(.WIDTH(32), .SIZE(SIZE), .USE_AS_BUFF(0)) gate_xfer
    (
        .clk(clk), .reset(reset), .clear(clear),
        .i_tdata(gate_tdata), .i_tlast(gate_tlast), .i_terror(1'b0), .i_tvalid(gate_tvalid), .i_tready(gate_tready),
        .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
    );
   assign  debug = {13'b0,
		    seq_id_wayoff,
		    gate_terror,
		    obviously_bad_hdr,
		    seq_id_bad,
		    seq_id_ref,
		    i_tlast,
		    i_tready,
		    i_tvalid,
		    i_tdata};
   

endmodule
module gpif2_error_checker
  #(parameter SIZE = 9)
  (input clk, input reset, input clear,
   input [31:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
   output [31:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
   output bus_error, output [63:0] debug);


    wire [31:0] gate_tdata;
    wire gate_tlast, gate_terror;
    wire gate_tvalid, gate_tready;

    localparam STATE_HDR = 0;
    localparam STATE_FWD = 1;
    localparam STATE_EOF = 2;
    localparam STATE_WAIT = 3;
    reg [1:0] state;

    reg [15:0] lines32;
    reg [11:0] seq_id_ref;
    reg        seq_id_bad;
    reg        seq_id_wayoff;
   

    wire [15:0] hdr_bytes = i_tdata[15:0] + 3;
    wire [15:0] hdr_lines32 = {2'b0, hdr_bytes[15:2]};
    wire [11:0] seq_id_actual = i_tdata[27:16];
   
   
    wire obviously_bad_hdr = (hdr_lines32 == 16'h0) || (hdr_lines32 > (1 << SIZE));

    always @(posedge clk) begin
        if (reset | clear) begin
            state <= STATE_HDR;
            lines32 <= 16'b0;
	    seq_id_ref <= 12'h0;
	    seq_id_bad <= 0;
	    seq_id_wayoff <= 0;
	   
	   
        end
        else case (state)

        STATE_HDR: begin
            if (i_tvalid && i_tready) begin
                if (obviously_bad_hdr)           state <= STATE_WAIT;
                else if (hdr_lines32 == 16'h1)  state <= STATE_HDR;
                else if (hdr_lines32 == 16'h2)  state <= STATE_EOF;
                else                            state <= STATE_FWD;
	        seq_id_bad <= (seq_id_actual != seq_id_ref);
	        seq_id_wayoff <= (seq_id_actual != seq_id_ref) |
				(seq_id_actual != seq_id_ref+1) |
				(seq_id_actual != seq_id_ref+2) |
				(seq_id_actual != seq_id_ref+3);
	        if (seq_id_actual != seq_id_ref)
		 seq_id_ref <= seq_id_actual + 1;
	        else
		 seq_id_ref <= seq_id_ref + 1;
            end
            lines32 <= hdr_lines32;
	    
        end

        STATE_FWD: begin
            if (i_tvalid && i_tready) begin
                if (lines32 == 16'h3) state <= STATE_EOF;
                lines32 <= lines32 - 1'b1;
            end
        end

        STATE_EOF: begin
	   if (i_tvalid && i_tready) 
	     if (gate_tlast) state <= STATE_HDR;
	     else state <= STATE_WAIT;
        end

        STATE_WAIT: begin
            if (i_tvalid && i_tready && i_tlast) state <= STATE_HDR;
        end

        endcase
    end

    assign bus_error = (gate_terror && gate_tvalid && gate_tready) || ((state == STATE_HDR) && i_tvalid && i_tready && obviously_bad_hdr);
    assign gate_tlast = (state == STATE_HDR)? (hdr_lines32 == 16'h1) : (state == STATE_EOF);
    assign gate_tdata = i_tdata;
    assign gate_tvalid = i_tvalid && ((state == STATE_HDR)? !obviously_bad_hdr : (state != STATE_WAIT));
    assign i_tready = gate_tready;

    axi_packet_gate #(.WIDTH(32), .SIZE(SIZE), .USE_AS_BUFF(0)) gate_xfer
    (
        .clk(clk), .reset(reset), .clear(clear),
        .i_tdata(gate_tdata), .i_tlast(gate_tlast), .i_terror(1'b0), .i_tvalid(gate_tvalid), .i_tready(gate_tready),
        .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
    );
   assign  debug = {13'b0,
		    seq_id_wayoff,
		    gate_terror,
		    obviously_bad_hdr,
		    seq_id_bad,
		    seq_id_ref,
		    i_tlast,
		    i_tready,
		    i_tvalid,
		    i_tdata};
   

endmodule