data/full_repos/permissive/102515926/Modules/CIRCUIT8.v
1: b"%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:19: Cannot find file containing module: 'DEC'\n    DEC #(64) dec1(a, e);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/DEC\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/DEC.v\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/DEC.sv\n             DEC\n             DEC.v\n             DEC.sv\n             obj_dir/DEC\n             obj_dir/DEC.v\n             obj_dir/DEC.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:20: Cannot find file containing module: 'INC'\n    INC #(64) inc1(c, f);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:21: Cannot find file containing module: 'MOD'\n    MOD #(64) mod1(a, c, g);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:22: Cannot find file containing module: 'COMP'\n    COMP #(64) comp1(g, zero, gGTz, gLTz, gEQz);\n    ^~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:23: Cannot find file containing module: 'MUX2x1'\n    MUX2x1 #(64) mux1(f, e, gEQz, zwire);\n    ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT8.v:24: Cannot find file containing module: 'REG'\n    REG #(64) reg1(zwire, Clk, Rst, z);\n    ^~~\n%Error: Exiting due to 6 error(s)\n"
module CIRCUIT8(a, b, c, zero, Clk, Rst, z);
    
    input Clk, Rst;
    input [63:0] a, b, c, zero;

    output [63:0] z;

    wire [63:0] e, f, g, zwire;
    wire gEQz, gLTz, gGTz;  
    
    DEC #(64) dec1(a, e);
    INC #(64) inc1(c, f);
    MOD #(64) mod1(a, c, g);
    COMP #(64) comp1(g, zero, gGTz, gLTz, gEQz);
    MUX2x1 #(64) mux1(f, e, gEQz, zwire);
    REG #(64) reg1(zwire, Clk, Rst, z);
    

endmodule
module CIRCUIT8(a, b, c, zero, Clk, Rst, z);

    
    input Clk, Rst;
    input [63:0] a, b, c, zero;

    output [63:0] z;

    wire [63:0] e, f, g, zwire;
    wire gEQz, gLTz, gGTz;  
    
    DEC #(64) dec1(a, e);
    INC #(64) inc1(c, f);
    MOD #(64) mod1(a, c, g);
    COMP #(64) comp1(g, zero, gGTz, gLTz, gEQz);
    MUX2x1 #(64) mux1(f, e, gEQz, zwire);
    REG #(64) reg1(zwire, Clk, Rst, z);
    

endmodule