data/full_repos/permissive/162533945/sra.v
data/verilator_xmls/69fdcba1-a746-4296-bdca-3144785d7d91.xml
module shifter_right_8(in, out);
	input [31:0] in;
	output [31:0] out;
	
	genvar i;
	generate
		for (i=0; i<24; i=i+1) begin: mux0
			assign out[i] = in[i+8];
		end
	endgenerate
	
	genvar j;
	generate
		for (j=24; j<32; j=j+1) begin: mux1
			assign out[j] = in[31];
		end
	endgenerate

endmodule
module shifter_right_8(in, out);

	input [31:0] in;
	output [31:0] out;
	
	genvar i;
	generate
		for (i=0; i<24; i=i+1) begin: mux0
			assign out[i] = in[i+8];
		end
	endgenerate
	
	genvar j;
	generate
		for (j=24; j<32; j=j+1) begin: mux1
			assign out[j] = in[31];
		end
	endgenerate

endmodule