data/full_repos/permissive/102955443/test.v
 line:32: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/102955443/test.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #(5) r_Clock <= !r_Clock;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/102955443/test.v:21: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("enigma.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/102955443/test.v:22: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,test);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/102955443/test.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #10\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/test.v:28: Unsupported: Ignoring delay on this delayed statement.\n   #30\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/test.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #260\n  ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();
	reg i_ready = 0;
	reg [7:0] inputData;
	reg r_Clock = 0;
	wire o_ready;
	wire [7:0] outputData;
	integer i;
	
	state_machine st(.i_clock(r_Clock),.i_ready(i_ready),.i_inputData(inputData),.o_ready(o_ready),.o_outputData(outputData));
	
	always
		#(5) r_Clock <= !r_Clock;
 
	always @(posedge o_ready)
	begin
		$display("data is [%c]",outputData);
	end

    initial
	begin
		$dumpfile("enigma.vcd");
		$dumpvars(0,test);
		inputData = "A";
		for (i = 0; i < 20; i = i + 1) 		
		begin
			#10
			i_ready = 1;
			#30
			i_ready = 0;
		end
		#260
		$finish;
	end
endmodule
module test();

	reg i_ready = 0;
	reg [7:0] inputData;
	reg r_Clock = 0;
	wire o_ready;
	wire [7:0] outputData;
	integer i;
	
	state_machine st(.i_clock(r_Clock),.i_ready(i_ready),.i_inputData(inputData),.o_ready(o_ready),.o_outputData(outputData));
	
	always
		#(5) r_Clock <= !r_Clock;
 
	always @(posedge o_ready)
	begin
		$display("data is [%c]",outputData);
	end

    initial
	begin
		$dumpfile("enigma.vcd");
		$dumpvars(0,test);
		inputData = "A";
		for (i = 0; i < 20; i = i + 1) 		
		begin
			#10
			i_ready = 1;
			#30
			i_ready = 0;
		end
		#260
		$finish;
	end
endmodule