data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog/okRegisterBridge.v
1: b'%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog/okRegisterBridge.v:23: Cannot find include file: mappings.v\n`include "mappings.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/mappings.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/mappings.v.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/mappings.v.sv\n             mappings.v\n             mappings.v.v\n             mappings.v.sv\n             obj_dir/mappings.v\n             obj_dir/mappings.v.v\n             obj_dir/mappings.v.sv\n%Error: Exiting due to 1 error(s)\n'
module okRegisterBridge(
	input  wire [112:0] okHE,
	output wire [64:0]  okEH,
	output wire [31:0]  ep_address,
	output wire         ep_write,
	output wire [31:0]  ep_dataout,
	output wire         ep_read,
	input  wire [31:0]  ep_datain
	);

`include "mappings.v"

assign ep_address = ti_reg_addr;
assign ep_write   = ti_reg_write;
assign ep_dataout = ti_reg_write_data;
assign ep_read    = ti_reg_read;

assign okEH[okEH_REGREADDATAH:okEH_REGREADDATAL] = ep_datain;
assign okEH[okEH_READY] = 1'b0;
assign okEH[okEH_DATAH:okEH_DATAL] = 32'h0;

endmodule
module okRegisterBridge(
	input  wire [112:0] okHE,
	output wire [64:0]  okEH,
	output wire [31:0]  ep_address,
	output wire         ep_write,
	output wire [31:0]  ep_dataout,
	output wire         ep_read,
	input  wire [31:0]  ep_datain
	);


`include "mappings.v"

assign ep_address = ti_reg_addr;
assign ep_write   = ti_reg_write;
assign ep_dataout = ti_reg_write_data;
assign ep_read    = ti_reg_read;

assign okEH[okEH_REGREADDATAH:okEH_REGREADDATAL] = ep_datain;
assign okEH[okEH_READY] = 1'b0;
assign okEH[okEH_DATAH:okEH_DATAL] = 32'h0;

endmodule