data/full_repos/permissive/14657119/bcd_counter.v
data/verilator_xmls/0bf5a3e5-7a1e-4d55-b198-5749fad1d194.xml
module bcd_counter(clock, reset, bcd, next);

	input clock, reset;
	output bcd, next;
	reg [3:0] bcd;
	reg next;
	wire not_reset;
	not(not_reset, reset);
	
	always @(posedge clock or posedge not_reset)
		begin
			if (not_reset == 1)
				bcd <= 0;
			else
			begin
				bcd <= bcd + 1;
				next <= 0;
				if (bcd > 8)
					begin
						bcd <= 0;
						next <= 1;
					end
			end
		end
endmodule
module bcd_counter(clock, reset, bcd, next);


	input clock, reset;
	output bcd, next;
	reg [3:0] bcd;
	reg next;
	wire not_reset;
	not(not_reset, reset);
	
	always @(posedge clock or posedge not_reset)
		begin
			if (not_reset == 1)
				bcd <= 0;
			else
			begin
				bcd <= bcd + 1;
				next <= 0;
				if (bcd > 8)
					begin
						bcd <= 0;
						next <= 1;
					end
			end
		end
endmodule