data/full_repos/permissive/185386477/verilog/ww_test.v
 line:125: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/185386477/verilog/ww_test.v:8: Unsupported: Ignoring delay on this delayed statement.\n  #500 reset = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/185386477/verilog/ww_test.v:11: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/185386477/verilog/ww_test.v:24: syntax error, unexpected \'@\'\n  @(reset);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/185386477/verilog/ww_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/185386477/verilog/ww_test.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/185386477/verilog/ww_test.v:87: syntax error, unexpected \'@\'\n  @(clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/185386477/verilog/ww_test.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/185386477/verilog/ww_test.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Error: data/full_repos/permissive/185386477/verilog/ww_test.v:122: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/185386477/verilog/ww_test.v:123: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars();\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/185386477/verilog/ww_test.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #20000 $finish;\n  ^\n%Error: Exiting due to 4 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock(output reg clk, output reg reset);
	initial begin
		clk = 0;
		reset = 1;
		#500 reset = 0;
	end

	always #10 clk = ~clk;
endmodule
module clock(output reg clk, output reg reset);

	initial begin
		clk = 0;
		reset = 1;
		#500 reset = 0;
	end

	always #10 clk = ~clk;
endmodule