data/full_repos/permissive/1840016/lab4/testbench.v
 line:38 column:2: Illegal character '\x00'
1: b'%Warning-STMTDLY: data/full_repos/permissive/1840016/lab4/testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #100 clk =~clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/1840016/lab4/testbench.v:30: Cannot find file containing module: \'mips_single\'\n   mips_single A1(clk, reset);\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/1840016/lab4,data/full_repos/permissive/1840016/mips_single\n             data/full_repos/permissive/1840016/lab4,data/full_repos/permissive/1840016/mips_single.v\n             data/full_repos/permissive/1840016/lab4,data/full_repos/permissive/1840016/mips_single.sv\n             mips_single\n             mips_single.v\n             mips_single.sv\n             obj_dir/mips_single\n             obj_dir/mips_single.v\n             obj_dir/mips_single.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    
   reg clk, reset;
   
   always
      #100 clk =~clk;
      
   initial begin
      clk = 1'b0;
      reset = 1'b1;
   end
   
   mips_single A1(clk, reset);
   



      
endmodule
module testbench;

    
   reg clk, reset;
   
   always
      #100 clk =~clk;
      
   initial begin
      clk = 1'b0;
      reset = 1'b1;
   end
   
   mips_single A1(clk, reset);
   



      
endmodule