data/full_repos/permissive/101237473/lab8/Source Code/led_controller.v
1: b'%Error: Cannot find file containing module: Code,data/full_repos/permissive/101237473\n        ... Looked in:\n             data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473\n             data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.v\n             data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.sv\n             Code,data/full_repos/permissive/101237473\n             Code,data/full_repos/permissive/101237473.v\n             Code,data/full_repos/permissive/101237473.sv\n             obj_dir/Code,data/full_repos/permissive/101237473\n             obj_dir/Code,data/full_repos/permissive/101237473.v\n             obj_dir/Code,data/full_repos/permissive/101237473.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/101237473/lab8/Source\n%Error: Cannot find file containing module: Code/led_controller.v\n%Error: Exiting due to 3 error(s)\n'
module led_controller( clk, reset, an, seg_sel );

	input clk, reset; 
	output reg [7:0] an;
	output reg [2:0] seg_sel;
	
	reg [2:0] present_state; 
	reg [2:0] next_state; 
	



	always @(present_state) 
	begin 
		case (present_state)
		3'b000	:	next_state = 3'b001; 
		3'b001	: 	next_state = 3'b010; 
		3'b010	: 	next_state = 3'b011; 
		3'b011	: 	next_state = 3'b100; 
		3'b100 	: 	next_state = 3'b101; 
		3'b101	: 	next_state = 3'b110; 
		3'b110	:  next_state = 3'b111; 
		3'b111	:  next_state = 3'b000; 
		default 	: 	next_state = 3'b000; 
		endcase 
	end 
	



	always @(posedge clk or posedge reset) 
		begin
			if (reset == 1'b1) 
			present_state = 3'b000; 
			else 
			present_state = next_state; 
		end	
		



	always @(present_state) 
	begin 
		case (present_state) 
		3'b000	: {seg_sel, an} = 11'b000_11111110; 
		3'b001	: {seg_sel, an} = 11'b001_11111101; 
		3'b010	: {seg_sel, an} = 11'b010_11111011; 
		3'b011	: {seg_sel, an} = 11'b011_11110111; 
		3'b100	: {seg_sel, an} = 11'b100_11101111; 
		3'b101 	: {seg_sel, an} = 11'b101_11011111; 
		3'b110	: {seg_sel, an} = 11'b110_10111111; 
		3'b111	: {seg_sel, an} = 11'b111_01111111;
		default 	: {seg_sel, an} = 11'b000_11111110; 
		endcase
	end 
	
endmodule
module led_controller( clk, reset, an, seg_sel );


	input clk, reset; 
	output reg [7:0] an;
	output reg [2:0] seg_sel;
	
	reg [2:0] present_state; 
	reg [2:0] next_state; 
	



	always @(present_state) 
	begin 
		case (present_state)
		3'b000	:	next_state = 3'b001; 
		3'b001	: 	next_state = 3'b010; 
		3'b010	: 	next_state = 3'b011; 
		3'b011	: 	next_state = 3'b100; 
		3'b100 	: 	next_state = 3'b101; 
		3'b101	: 	next_state = 3'b110; 
		3'b110	:  next_state = 3'b111; 
		3'b111	:  next_state = 3'b000; 
		default 	: 	next_state = 3'b000; 
		endcase 
	end 
	



	always @(posedge clk or posedge reset) 
		begin
			if (reset == 1'b1) 
			present_state = 3'b000; 
			else 
			present_state = next_state; 
		end	
		



	always @(present_state) 
	begin 
		case (present_state) 
		3'b000	: {seg_sel, an} = 11'b000_11111110; 
		3'b001	: {seg_sel, an} = 11'b001_11111101; 
		3'b010	: {seg_sel, an} = 11'b010_11111011; 
		3'b011	: {seg_sel, an} = 11'b011_11110111; 
		3'b100	: {seg_sel, an} = 11'b100_11101111; 
		3'b101 	: {seg_sel, an} = 11'b101_11011111; 
		3'b110	: {seg_sel, an} = 11'b110_10111111; 
		3'b111	: {seg_sel, an} = 11'b111_01111111;
		default 	: {seg_sel, an} = 11'b000_11111110; 
		endcase
	end 
	
endmodule