data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:98: Operator EQ expects 128 bits on the LHS, but LHS\'s VARREF \'STYLE\' generates 72 bits.\n                                                                                                                                                            : ... In instance lsu_wide_wrapper\nlocalparam ATOMIC_PIPELINED_LSU=(STYLE=="ATOMIC-PIPELINED");\n                                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:99: Operator EQ expects 120 bits on the LHS, but LHS\'s VARREF \'STYLE\' generates 72 bits.\n                                                                                                                                                            : ... In instance lsu_wide_wrapper\nlocalparam PIPELINED_LSU=( (STYLE=="PIPELINED") || (STYLE=="BASIC-COALESCED") || (STYLE=="BURST-COALESCED") || (STYLE=="BURST-NON-ALIGNED") );\n                                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:99: Operator EQ expects 120 bits on the LHS, but LHS\'s VARREF \'STYLE\' generates 72 bits.\n                                                                                                                                                            : ... In instance lsu_wide_wrapper\nlocalparam PIPELINED_LSU=( (STYLE=="PIPELINED") || (STYLE=="BASIC-COALESCED") || (STYLE=="BURST-COALESCED") || (STYLE=="BURST-NON-ALIGNED") );\n                                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:99: Operator EQ expects 136 bits on the LHS, but LHS\'s VARREF \'STYLE\' generates 72 bits.\n                                                                                                                                                            : ... In instance lsu_wide_wrapper\nlocalparam PIPELINED_LSU=( (STYLE=="PIPELINED") || (STYLE=="BASIC-COALESCED") || (STYLE=="BURST-COALESCED") || (STYLE=="BURST-NON-ALIGNED") );\n                                                                                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:100: Operator EQ expects 112 bits on the LHS, but LHS\'s VARREF \'STYLE\' generates 72 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\nlocalparam SUPPORTS_NOP=( (STYLE=="STREAMING") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") ||  (STYLE=="PREFETCHING") || FORCE_NOP_SUPPORT==1);\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:100: Operator EQ expects 136 bits on the LHS, but LHS\'s VARREF \'STYLE\' generates 72 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\nlocalparam SUPPORTS_NOP=( (STYLE=="STREAMING") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") ||  (STYLE=="PREFETCHING") || FORCE_NOP_SUPPORT==1);\n                                                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:100: Operator EQ expects 88 bits on the LHS, but LHS\'s VARREF \'STYLE\' generates 72 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\nlocalparam SUPPORTS_NOP=( (STYLE=="STREAMING") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") ||  (STYLE=="PREFETCHING") || FORCE_NOP_SUPPORT==1);\n                                                                                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:101: Operator EQ expects 120 bits on the LHS, but LHS\'s VARREF \'STYLE\' generates 72 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\nlocalparam SUPPORTS_BURSTS=( (STYLE=="STREAMING") || (STYLE=="BURST-COALESCED") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") || (STYLE=="PREFETCHING"));\n                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:101: Operator EQ expects 112 bits on the LHS, but LHS\'s VARREF \'STYLE\' generates 72 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\nlocalparam SUPPORTS_BURSTS=( (STYLE=="STREAMING") || (STYLE=="BURST-COALESCED") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") || (STYLE=="PREFETCHING"));\n                                                                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:101: Operator EQ expects 136 bits on the LHS, but LHS\'s VARREF \'STYLE\' generates 72 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\nlocalparam SUPPORTS_BURSTS=( (STYLE=="STREAMING") || (STYLE=="BURST-COALESCED") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") || (STYLE=="PREFETCHING"));\n                                                                                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:101: Operator EQ expects 88 bits on the LHS, but LHS\'s VARREF \'STYLE\' generates 72 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\nlocalparam SUPPORTS_BURSTS=( (STYLE=="STREAMING") || (STYLE=="BURST-COALESCED") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") || (STYLE=="PREFETCHING"));\n                                                                                                                                                      ^~\n%Error: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:180: Cannot find file containing module: \'lsu_top\'\n   lsu_top lsu_wide (\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/lsu_top\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/lsu_top.v\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/lsu_top.sv\n             lsu_top\n             lsu_top.v\n             lsu_top.sv\n             obj_dir/lsu_top\n             obj_dir/lsu_top.v\n             obj_dir/lsu_top.sv\n%Warning-LITENDIAN: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:257: Little bit endian vector: MSB < LSB of bit range: -1:0\n   reg [WIDE_INDEX_WIDTH-1:0] index;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:263: Little bit endian vector: MSB < LSB of bit range: -1:0\n   reg [WIDE_INDEX_WIDTH-1:0] output_index;  \n       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:289: Operator GTE expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'output_index\' generates 2 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\n     assign done_output = new_data && (output_index >= (WIDTH_RATIO-1));  \n                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:294: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\n         output_index <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:297: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'output_index\' generates 2 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\n         output_index <= new_data ? (output_index+1)%(WIDTH_RATIO): output_index;\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:297: Operator COND expects 32 or 6 bits on the Conditional False, but Conditional False\'s VARREF \'output_index\' generates 2 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\n         output_index <= new_data ? (output_index+1)%(WIDTH_RATIO): output_index;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:297: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 6 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\n         output_index <= new_data ? (output_index+1)%(WIDTH_RATIO): output_index;\n                      ^~\n%Error: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:310: [31:256] Range extract has backward bit ordering, perhaps you wanted [256:31]\n                                                                                                                                                     : ... In instance lsu_wide_wrapper\n         readdata_shiftreg <= new_data ? {avm_readdata,readdata_shiftreg[WIDTH-1:MWIDTH]} : readdata_shiftreg;     \n                                                                        ^\n%Error: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:310: Extracting 226 bits from only 32 bit number\n                                                                                                                                                     : ... In instance lsu_wide_wrapper\n         readdata_shiftreg <= new_data ? {avm_readdata,readdata_shiftreg[WIDTH-1:MWIDTH]} : readdata_shiftreg;     \n                                                                        ^\n%Warning-SELRANGE: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:310: Selection index out of range: 481:256 outside 31:0\n                                                                                                                                                                : ... In instance lsu_wide_wrapper\n         readdata_shiftreg <= new_data ? {avm_readdata,readdata_shiftreg[WIDTH-1:MWIDTH]} : readdata_shiftreg;     \n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:310: Operator COND expects 482 bits on the Conditional False, but Conditional False\'s VARREF \'readdata_shiftreg\' generates 32 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\n         readdata_shiftreg <= new_data ? {avm_readdata,readdata_shiftreg[WIDTH-1:MWIDTH]} : readdata_shiftreg;     \n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_wide_wrapper.v:310: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 482 bits.\n                                                                                                                                                             : ... In instance lsu_wide_wrapper\n         readdata_shiftreg <= new_data ? {avm_readdata,readdata_shiftreg[WIDTH-1:MWIDTH]} : readdata_shiftreg;     \n                           ^~\n%Error: Exiting due to 3 error(s), 21 warning(s)\n'
module lsu_wide_wrapper
(
    clock, clock2x, resetn, stream_base_addr, stream_size, stream_reset, i_atomic_op, o_stall, 
    i_valid, i_address, i_writedata, i_cmpdata, i_predicate, i_bitwiseor, i_stall, o_valid, o_readdata, avm_address, 
    avm_enable, avm_read, avm_readdata, avm_write, avm_writeack, avm_writedata, avm_byteenable, 
    avm_waitrequest, avm_readdatavalid, avm_burstcount,
    o_active,
    o_input_fifo_depth,
    o_writeack,
    i_byteenable,
    flush,

    profile_req_cache_hit_count,
    profile_extra_unaligned_reqs
);


parameter STYLE="PIPELINED";
parameter AWIDTH=32;
parameter ATOMIC_WIDTH=6;
parameter WIDTH_BYTES=4;
parameter MWIDTH_BYTES=32;
parameter WRITEDATAWIDTH_BYTES=32;

parameter ALIGNMENT_BYTES=2;
parameter READ=1;
parameter ATOMIC=0;
parameter BURSTCOUNT_WIDTH=6;
parameter KERNEL_SIDE_MEM_LATENCY=1;
parameter MEMORY_SIDE_MEM_LATENCY=1;
parameter USE_WRITE_ACK=0;
parameter USECACHING=0;
parameter USE_BYTE_EN=0;
parameter CACHESIZE=1024;
parameter PROFILE_ADDR_TOGGLE=0;
parameter USEINPUTFIFO=1;
parameter USEOUTPUTFIFO=1;
parameter FORCE_NOP_SUPPORT=0;
parameter HIGH_FMAX=1;

parameter ADDRSPACE=0;
 



parameter ACL_PROFILE=0;
parameter ACL_PROFILE_ID=1;
parameter ACL_PROFILE_INCREMENT_WIDTH=64;


parameter ENABLE_BANKED_MEMORY=0;
parameter ABITS_PER_LMEM_BANK=0;
parameter NUMBER_BANKS=1;
parameter LMEM_ADDR_PERMUTATION_STYLE=0;







localparam BANK_SELECT_BITS = (ENABLE_BANKED_MEMORY==1) ? $clog2(NUMBER_BANKS) : 1;
localparam HACKED_ABITS_PER_LMEM_BANK = (ENABLE_BANKED_MEMORY==1) ? ABITS_PER_LMEM_BANK : $clog2(MWIDTH_BYTES)+1;












parameter WIDTH=8*WIDTH_BYTES;
parameter MWIDTH=8*MWIDTH_BYTES;
parameter WRITEDATAWIDTH=8*WRITEDATAWIDTH_BYTES;
parameter ALIGNMENT_ABITS=$clog2(ALIGNMENT_BYTES);
localparam LSU_CAPACITY=256;

localparam WIDE_LSU = (WIDTH > MWIDTH); 
localparam LSU_WIDTH =  (WIDTH > MWIDTH) ? MWIDTH:  WIDTH;
localparam LSU_WIDTH_BYTES = LSU_WIDTH/8; 

localparam WIDTH_RATIO =  (WIDTH_BYTES/LSU_WIDTH_BYTES); 
localparam WIDE_INDEX_WIDTH = $clog2(WIDTH_RATIO);


parameter INPUTFIFO_USEDW_MAXBITS=8;


localparam ATOMIC_PIPELINED_LSU=(STYLE=="ATOMIC-PIPELINED");
localparam PIPELINED_LSU=( (STYLE=="PIPELINED") || (STYLE=="BASIC-COALESCED") || (STYLE=="BURST-COALESCED") || (STYLE=="BURST-NON-ALIGNED") );
localparam SUPPORTS_NOP=( (STYLE=="STREAMING") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") ||  (STYLE=="PREFETCHING") || FORCE_NOP_SUPPORT==1);
localparam SUPPORTS_BURSTS=( (STYLE=="STREAMING") || (STYLE=="BURST-COALESCED") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") || (STYLE=="PREFETCHING"));




input clock;
input clock2x;
input resetn;
input flush;


input [AWIDTH-1:0] stream_base_addr;
input [31:0] stream_size;
input stream_reset;


input [WIDTH-1:0] i_cmpdata;
input [ATOMIC_WIDTH-1:0] i_atomic_op;


output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
input i_predicate;
input [AWIDTH-1:0] i_bitwiseor;
input [WIDTH_BYTES-1:0] i_byteenable;


input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;


output [AWIDTH-1:0] avm_address;
output avm_enable;
output avm_read;
input [WRITEDATAWIDTH-1:0] avm_readdata;
output avm_write;
input avm_writeack;
output o_writeack;
output [WRITEDATAWIDTH-1:0] avm_writedata;
output [WRITEDATAWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
input avm_readdatavalid;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;

output reg o_active;


output [INPUTFIFO_USEDW_MAXBITS-1:0] o_input_fifo_depth;


output logic profile_req_cache_hit_count;
output logic profile_extra_unaligned_reqs;




localparam ADAPT_AT_AVM = 1;   
generate
if(ADAPT_AT_AVM) 
begin


   wire [ AWIDTH-1:0] avm_address_wrapped;
   wire avm_enable_wrapped;
   wire avm_read_wrapped;
   wire [WIDTH-1:0] avm_readdata_wrapped;
   wire avm_write_wrapped;
   wire avm_writeack_wrapped;
   wire [BURSTCOUNT_WIDTH-WIDE_INDEX_WIDTH-1:0] avm_burstcount_wrapped;
   wire [WIDTH-1:0] avm_writedata_wrapped;
   wire [WIDTH_BYTES-1:0]avm_byteenable_wrapped;
   wire avm_waitrequest_wrapped;
   reg avm_readdatavalid_wrapped;

   lsu_top lsu_wide (
     .clock(clock),
     .clock2x(clock2x),
     .resetn(resetn),
     .flush(flush),
     .stream_base_addr(stream_base_addr),
     .stream_size(stream_size),
     .stream_reset(stream_reset),
     .o_stall(o_stall),
     .i_valid(i_valid),
     .i_address(i_address),
     .i_writedata(i_writedata),
     .i_cmpdata(i_cmpdata),
     .i_predicate(i_predicate),
     .i_bitwiseor(i_bitwiseor),
     .i_byteenable(i_byteenable),
     .i_stall(i_stall),
     .o_valid(o_valid),
     .o_readdata(o_readdata),
     .o_input_fifo_depth(o_input_fifo_depth),
     .o_writeack(o_writeack),
     .i_atomic_op(i_atomic_op),
     .o_active(o_active),
     .avm_address(avm_address_wrapped),
     .avm_enable(avm_enable_wrapped),
     .avm_read(avm_read_wrapped),
     .avm_readdata(avm_readdata_wrapped),
     .avm_write(avm_write_wrapped),
     .avm_writeack(avm_writeack_wrapped),
     .avm_burstcount(avm_burstcount_wrapped),
     .avm_writedata(avm_writedata_wrapped),
     .avm_byteenable(avm_byteenable_wrapped),
     .avm_waitrequest(avm_waitrequest_wrapped),
     .avm_readdatavalid(avm_readdatavalid_wrapped),
     .profile_req_cache_hit_count(profile_req_cache_hit_count),
     .profile_extra_unaligned_reqs(profile_extra_unaligned_reqs)

   );

   defparam lsu_wide.STYLE = STYLE;
   defparam lsu_wide.AWIDTH = AWIDTH;
   defparam lsu_wide.ATOMIC_WIDTH = ATOMIC_WIDTH;
   defparam lsu_wide.WIDTH_BYTES = WIDTH_BYTES;
   defparam lsu_wide.MWIDTH_BYTES = WIDTH_BYTES;
   defparam lsu_wide.WRITEDATAWIDTH_BYTES = WIDTH_BYTES;
   defparam lsu_wide.ALIGNMENT_BYTES = ALIGNMENT_BYTES;
   defparam lsu_wide.READ = READ;
   defparam lsu_wide.ATOMIC = ATOMIC;
   defparam lsu_wide.BURSTCOUNT_WIDTH = BURSTCOUNT_WIDTH-WIDE_INDEX_WIDTH;
   defparam lsu_wide.USE_WRITE_ACK = USE_WRITE_ACK;
   defparam lsu_wide.USECACHING = USECACHING;
   defparam lsu_wide.USE_BYTE_EN = USE_BYTE_EN;
   defparam lsu_wide.CACHESIZE = CACHESIZE;
   defparam lsu_wide.PROFILE_ADDR_TOGGLE = PROFILE_ADDR_TOGGLE;
   defparam lsu_wide.USEINPUTFIFO = USEINPUTFIFO;
   defparam lsu_wide.USEOUTPUTFIFO = USEOUTPUTFIFO;
   defparam lsu_wide.FORCE_NOP_SUPPORT = FORCE_NOP_SUPPORT;
   defparam lsu_wide.HIGH_FMAX = HIGH_FMAX;
   defparam lsu_wide.ACL_PROFILE = ACL_PROFILE;
   defparam lsu_wide.ACL_PROFILE_INCREMENT_WIDTH = ACL_PROFILE_INCREMENT_WIDTH;
   defparam lsu_wide.ENABLE_BANKED_MEMORY = ENABLE_BANKED_MEMORY;
   defparam lsu_wide.ABITS_PER_LMEM_BANK = ABITS_PER_LMEM_BANK;
   defparam lsu_wide.NUMBER_BANKS = NUMBER_BANKS;
   defparam lsu_wide.WIDTH = WIDTH;
   defparam lsu_wide.MWIDTH = WIDTH;  
   defparam lsu_wide.MEMORY_SIDE_MEM_LATENCY = MEMORY_SIDE_MEM_LATENCY; 
   defparam lsu_wide.KERNEL_SIDE_MEM_LATENCY = KERNEL_SIDE_MEM_LATENCY; 
   defparam lsu_wide.WRITEDATAWIDTH = WIDTH;
   defparam lsu_wide.INPUTFIFO_USEDW_MAXBITS = INPUTFIFO_USEDW_MAXBITS;
   defparam lsu_wide.LMEM_ADDR_PERMUTATION_STYLE = LMEM_ADDR_PERMUTATION_STYLE;
   defparam lsu_wide.ADDRSPACE = ADDRSPACE;


   wire done;
   wire ready; 

   reg in_progress;
   reg [WIDE_INDEX_WIDTH-1:0] index;


   wire new_data;
   wire done_output;
   reg output_ready;
   reg [WIDE_INDEX_WIDTH-1:0] output_index;  
   reg [WIDTH-1:0] readdata_shiftreg; 

   reg [ AWIDTH-1:0] avm_address_reg;
   reg avm_read_reg;
   reg [WIDTH-1:0] avm_readdata_reg;
   reg avm_write_reg;
   reg [BURSTCOUNT_WIDTH-WIDE_INDEX_WIDTH-1:0] avm_burstcount_reg;
   reg [WIDTH-1:0] avm_writedata_reg;
   reg [WIDTH_BYTES-1:0]avm_byteenable_reg;
   
   
   
  if(READ) 
  begin
     assign avm_writedata =   0;
     assign avm_byteenable = 0;
     assign avm_address = avm_address_wrapped; 
     assign avm_burstcount = avm_burstcount_wrapped*WIDTH_RATIO;
     assign avm_write  = 0;
     assign avm_read = avm_read_wrapped;
     assign avm_enable = avm_enable_wrapped;
     
     assign avm_waitrequest_wrapped = avm_waitrequest; 

     assign new_data = avm_readdatavalid;
     assign done_output = new_data && (output_index >= (WIDTH_RATIO-1));

     always@(posedge clock or negedge resetn)
     begin
       if(!resetn)
         output_index <= 1'b0;
       else

         output_index <= new_data ? (output_index+1)%(WIDTH_RATIO): output_index;
     end

     always@(posedge clock or negedge resetn)
     begin
       if(!resetn)
       begin
         readdata_shiftreg <= 0;
         output_ready <= 0;
       end
       else
       begin

         readdata_shiftreg <= new_data ? {avm_readdata,readdata_shiftreg[WIDTH-1:MWIDTH]} : readdata_shiftreg;     
         output_ready <= done_output  ;
       end
     end

     assign avm_readdata_wrapped = readdata_shiftreg;
     assign avm_readdatavalid_wrapped = output_ready;
     
   end else begin 

     

     assign done  = in_progress && (index >= (WIDTH_RATIO-1)) && !avm_waitrequest;
     assign ready = (!in_progress || done);
     

     wire start = (avm_write_wrapped) && (!in_progress || done);

     always@(posedge clock or negedge resetn)
     begin
       if(!resetn)
       begin
         in_progress <= 0;
         index <= 0;
       end 
       else 
       begin

         in_progress <= start || (in_progress && !done);

         index <= (start || !in_progress) ? 1'b0 : ( avm_waitrequest ? index :index+1);
       end
     end
     reg [ WIDE_INDEX_WIDTH-1:0] write_ack_count;
     

     always@(posedge clock or negedge resetn)
     begin
       if(!resetn)
       begin
         write_ack_count   <= 0;        
       end
       else if (avm_writeack)
       begin
         write_ack_count   <= write_ack_count+1;
       end
       else
       begin
         write_ack_count   <= write_ack_count;
       end  
     end
     
       
     assign avm_writeack_wrapped = (write_ack_count  == {WIDE_INDEX_WIDTH{1'b1}} - 1 ) && avm_writeack; 
     

     always@(posedge clock or negedge resetn)
     begin
       if(!resetn)
       begin
         avm_address_reg   <= 0;
         avm_writedata_reg <= 0;
         avm_byteenable_reg <= 0;
         avm_burstcount_reg <= 0;

       end
       else if (start)
       begin
         avm_address_reg   <= avm_address_wrapped;
         avm_writedata_reg <= avm_writedata_wrapped;
         avm_byteenable_reg <= avm_byteenable_wrapped;
         avm_burstcount_reg <= avm_burstcount_wrapped;
       end
       else
       begin
         avm_address_reg   <= avm_address_reg;
         avm_writedata_reg <= avm_writedata_reg;
         avm_byteenable_reg <= avm_byteenable_reg;
         avm_burstcount_reg <= avm_burstcount_reg;
       end  
     end


     assign avm_waitrequest_wrapped = !ready;  
     assign avm_writedata =   avm_writedata_reg[((index+1)*MWIDTH-1)-:MWIDTH];
     assign avm_byteenable = avm_byteenable_reg[((index+1)*MWIDTH_BYTES-1)-:MWIDTH_BYTES];
     assign avm_address = avm_address_reg; 
     assign avm_burstcount = avm_burstcount_reg*WIDTH_RATIO;
     assign avm_write = in_progress;
     assign avm_read = 0;
     assign avm_enable = avm_enable_wrapped;
 
   end

end else begin
end
endgenerate

endmodule
module lsu_wide_wrapper
(
    clock, clock2x, resetn, stream_base_addr, stream_size, stream_reset, i_atomic_op, o_stall, 
    i_valid, i_address, i_writedata, i_cmpdata, i_predicate, i_bitwiseor, i_stall, o_valid, o_readdata, avm_address, 
    avm_enable, avm_read, avm_readdata, avm_write, avm_writeack, avm_writedata, avm_byteenable, 
    avm_waitrequest, avm_readdatavalid, avm_burstcount,
    o_active,
    o_input_fifo_depth,
    o_writeack,
    i_byteenable,
    flush,

    profile_req_cache_hit_count,
    profile_extra_unaligned_reqs
);



parameter STYLE="PIPELINED";
parameter AWIDTH=32;
parameter ATOMIC_WIDTH=6;
parameter WIDTH_BYTES=4;
parameter MWIDTH_BYTES=32;
parameter WRITEDATAWIDTH_BYTES=32;

parameter ALIGNMENT_BYTES=2;
parameter READ=1;
parameter ATOMIC=0;
parameter BURSTCOUNT_WIDTH=6;
parameter KERNEL_SIDE_MEM_LATENCY=1;
parameter MEMORY_SIDE_MEM_LATENCY=1;
parameter USE_WRITE_ACK=0;
parameter USECACHING=0;
parameter USE_BYTE_EN=0;
parameter CACHESIZE=1024;
parameter PROFILE_ADDR_TOGGLE=0;
parameter USEINPUTFIFO=1;
parameter USEOUTPUTFIFO=1;
parameter FORCE_NOP_SUPPORT=0;
parameter HIGH_FMAX=1;

parameter ADDRSPACE=0;
 



parameter ACL_PROFILE=0;
parameter ACL_PROFILE_ID=1;
parameter ACL_PROFILE_INCREMENT_WIDTH=64;


parameter ENABLE_BANKED_MEMORY=0;
parameter ABITS_PER_LMEM_BANK=0;
parameter NUMBER_BANKS=1;
parameter LMEM_ADDR_PERMUTATION_STYLE=0;







localparam BANK_SELECT_BITS = (ENABLE_BANKED_MEMORY==1) ? $clog2(NUMBER_BANKS) : 1;
localparam HACKED_ABITS_PER_LMEM_BANK = (ENABLE_BANKED_MEMORY==1) ? ABITS_PER_LMEM_BANK : $clog2(MWIDTH_BYTES)+1;












parameter WIDTH=8*WIDTH_BYTES;
parameter MWIDTH=8*MWIDTH_BYTES;
parameter WRITEDATAWIDTH=8*WRITEDATAWIDTH_BYTES;
parameter ALIGNMENT_ABITS=$clog2(ALIGNMENT_BYTES);
localparam LSU_CAPACITY=256;

localparam WIDE_LSU = (WIDTH > MWIDTH); 
localparam LSU_WIDTH =  (WIDTH > MWIDTH) ? MWIDTH:  WIDTH;
localparam LSU_WIDTH_BYTES = LSU_WIDTH/8; 

localparam WIDTH_RATIO =  (WIDTH_BYTES/LSU_WIDTH_BYTES); 
localparam WIDE_INDEX_WIDTH = $clog2(WIDTH_RATIO);


parameter INPUTFIFO_USEDW_MAXBITS=8;


localparam ATOMIC_PIPELINED_LSU=(STYLE=="ATOMIC-PIPELINED");
localparam PIPELINED_LSU=( (STYLE=="PIPELINED") || (STYLE=="BASIC-COALESCED") || (STYLE=="BURST-COALESCED") || (STYLE=="BURST-NON-ALIGNED") );
localparam SUPPORTS_NOP=( (STYLE=="STREAMING") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") ||  (STYLE=="PREFETCHING") || FORCE_NOP_SUPPORT==1);
localparam SUPPORTS_BURSTS=( (STYLE=="STREAMING") || (STYLE=="BURST-COALESCED") || (STYLE=="SEMI-STREAMING") || (STYLE=="BURST-NON-ALIGNED") || (STYLE=="PREFETCHING"));




input clock;
input clock2x;
input resetn;
input flush;


input [AWIDTH-1:0] stream_base_addr;
input [31:0] stream_size;
input stream_reset;


input [WIDTH-1:0] i_cmpdata;
input [ATOMIC_WIDTH-1:0] i_atomic_op;


output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
input i_predicate;
input [AWIDTH-1:0] i_bitwiseor;
input [WIDTH_BYTES-1:0] i_byteenable;


input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;


output [AWIDTH-1:0] avm_address;
output avm_enable;
output avm_read;
input [WRITEDATAWIDTH-1:0] avm_readdata;
output avm_write;
input avm_writeack;
output o_writeack;
output [WRITEDATAWIDTH-1:0] avm_writedata;
output [WRITEDATAWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
input avm_readdatavalid;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;

output reg o_active;


output [INPUTFIFO_USEDW_MAXBITS-1:0] o_input_fifo_depth;


output logic profile_req_cache_hit_count;
output logic profile_extra_unaligned_reqs;




localparam ADAPT_AT_AVM = 1;   
generate
if(ADAPT_AT_AVM) 
begin


   wire [ AWIDTH-1:0] avm_address_wrapped;
   wire avm_enable_wrapped;
   wire avm_read_wrapped;
   wire [WIDTH-1:0] avm_readdata_wrapped;
   wire avm_write_wrapped;
   wire avm_writeack_wrapped;
   wire [BURSTCOUNT_WIDTH-WIDE_INDEX_WIDTH-1:0] avm_burstcount_wrapped;
   wire [WIDTH-1:0] avm_writedata_wrapped;
   wire [WIDTH_BYTES-1:0]avm_byteenable_wrapped;
   wire avm_waitrequest_wrapped;
   reg avm_readdatavalid_wrapped;

   lsu_top lsu_wide (
     .clock(clock),
     .clock2x(clock2x),
     .resetn(resetn),
     .flush(flush),
     .stream_base_addr(stream_base_addr),
     .stream_size(stream_size),
     .stream_reset(stream_reset),
     .o_stall(o_stall),
     .i_valid(i_valid),
     .i_address(i_address),
     .i_writedata(i_writedata),
     .i_cmpdata(i_cmpdata),
     .i_predicate(i_predicate),
     .i_bitwiseor(i_bitwiseor),
     .i_byteenable(i_byteenable),
     .i_stall(i_stall),
     .o_valid(o_valid),
     .o_readdata(o_readdata),
     .o_input_fifo_depth(o_input_fifo_depth),
     .o_writeack(o_writeack),
     .i_atomic_op(i_atomic_op),
     .o_active(o_active),
     .avm_address(avm_address_wrapped),
     .avm_enable(avm_enable_wrapped),
     .avm_read(avm_read_wrapped),
     .avm_readdata(avm_readdata_wrapped),
     .avm_write(avm_write_wrapped),
     .avm_writeack(avm_writeack_wrapped),
     .avm_burstcount(avm_burstcount_wrapped),
     .avm_writedata(avm_writedata_wrapped),
     .avm_byteenable(avm_byteenable_wrapped),
     .avm_waitrequest(avm_waitrequest_wrapped),
     .avm_readdatavalid(avm_readdatavalid_wrapped),
     .profile_req_cache_hit_count(profile_req_cache_hit_count),
     .profile_extra_unaligned_reqs(profile_extra_unaligned_reqs)

   );

   defparam lsu_wide.STYLE = STYLE;
   defparam lsu_wide.AWIDTH = AWIDTH;
   defparam lsu_wide.ATOMIC_WIDTH = ATOMIC_WIDTH;
   defparam lsu_wide.WIDTH_BYTES = WIDTH_BYTES;
   defparam lsu_wide.MWIDTH_BYTES = WIDTH_BYTES;
   defparam lsu_wide.WRITEDATAWIDTH_BYTES = WIDTH_BYTES;
   defparam lsu_wide.ALIGNMENT_BYTES = ALIGNMENT_BYTES;
   defparam lsu_wide.READ = READ;
   defparam lsu_wide.ATOMIC = ATOMIC;
   defparam lsu_wide.BURSTCOUNT_WIDTH = BURSTCOUNT_WIDTH-WIDE_INDEX_WIDTH;
   defparam lsu_wide.USE_WRITE_ACK = USE_WRITE_ACK;
   defparam lsu_wide.USECACHING = USECACHING;
   defparam lsu_wide.USE_BYTE_EN = USE_BYTE_EN;
   defparam lsu_wide.CACHESIZE = CACHESIZE;
   defparam lsu_wide.PROFILE_ADDR_TOGGLE = PROFILE_ADDR_TOGGLE;
   defparam lsu_wide.USEINPUTFIFO = USEINPUTFIFO;
   defparam lsu_wide.USEOUTPUTFIFO = USEOUTPUTFIFO;
   defparam lsu_wide.FORCE_NOP_SUPPORT = FORCE_NOP_SUPPORT;
   defparam lsu_wide.HIGH_FMAX = HIGH_FMAX;
   defparam lsu_wide.ACL_PROFILE = ACL_PROFILE;
   defparam lsu_wide.ACL_PROFILE_INCREMENT_WIDTH = ACL_PROFILE_INCREMENT_WIDTH;
   defparam lsu_wide.ENABLE_BANKED_MEMORY = ENABLE_BANKED_MEMORY;
   defparam lsu_wide.ABITS_PER_LMEM_BANK = ABITS_PER_LMEM_BANK;
   defparam lsu_wide.NUMBER_BANKS = NUMBER_BANKS;
   defparam lsu_wide.WIDTH = WIDTH;
   defparam lsu_wide.MWIDTH = WIDTH;  
   defparam lsu_wide.MEMORY_SIDE_MEM_LATENCY = MEMORY_SIDE_MEM_LATENCY; 
   defparam lsu_wide.KERNEL_SIDE_MEM_LATENCY = KERNEL_SIDE_MEM_LATENCY; 
   defparam lsu_wide.WRITEDATAWIDTH = WIDTH;
   defparam lsu_wide.INPUTFIFO_USEDW_MAXBITS = INPUTFIFO_USEDW_MAXBITS;
   defparam lsu_wide.LMEM_ADDR_PERMUTATION_STYLE = LMEM_ADDR_PERMUTATION_STYLE;
   defparam lsu_wide.ADDRSPACE = ADDRSPACE;


   wire done;
   wire ready; 

   reg in_progress;
   reg [WIDE_INDEX_WIDTH-1:0] index;


   wire new_data;
   wire done_output;
   reg output_ready;
   reg [WIDE_INDEX_WIDTH-1:0] output_index;  
   reg [WIDTH-1:0] readdata_shiftreg; 

   reg [ AWIDTH-1:0] avm_address_reg;
   reg avm_read_reg;
   reg [WIDTH-1:0] avm_readdata_reg;
   reg avm_write_reg;
   reg [BURSTCOUNT_WIDTH-WIDE_INDEX_WIDTH-1:0] avm_burstcount_reg;
   reg [WIDTH-1:0] avm_writedata_reg;
   reg [WIDTH_BYTES-1:0]avm_byteenable_reg;
   
   
   
  if(READ) 
  begin
     assign avm_writedata =   0;
     assign avm_byteenable = 0;
     assign avm_address = avm_address_wrapped; 
     assign avm_burstcount = avm_burstcount_wrapped*WIDTH_RATIO;
     assign avm_write  = 0;
     assign avm_read = avm_read_wrapped;
     assign avm_enable = avm_enable_wrapped;
     
     assign avm_waitrequest_wrapped = avm_waitrequest; 

     assign new_data = avm_readdatavalid;
     assign done_output = new_data && (output_index >= (WIDTH_RATIO-1));

     always@(posedge clock or negedge resetn)
     begin
       if(!resetn)
         output_index <= 1'b0;
       else

         output_index <= new_data ? (output_index+1)%(WIDTH_RATIO): output_index;
     end

     always@(posedge clock or negedge resetn)
     begin
       if(!resetn)
       begin
         readdata_shiftreg <= 0;
         output_ready <= 0;
       end
       else
       begin

         readdata_shiftreg <= new_data ? {avm_readdata,readdata_shiftreg[WIDTH-1:MWIDTH]} : readdata_shiftreg;     
         output_ready <= done_output  ;
       end
     end

     assign avm_readdata_wrapped = readdata_shiftreg;
     assign avm_readdatavalid_wrapped = output_ready;
     
   end else begin 

     

     assign done  = in_progress && (index >= (WIDTH_RATIO-1)) && !avm_waitrequest;
     assign ready = (!in_progress || done);
     

     wire start = (avm_write_wrapped) && (!in_progress || done);

     always@(posedge clock or negedge resetn)
     begin
       if(!resetn)
       begin
         in_progress <= 0;
         index <= 0;
       end 
       else 
       begin

         in_progress <= start || (in_progress && !done);

         index <= (start || !in_progress) ? 1'b0 : ( avm_waitrequest ? index :index+1);
       end
     end
     reg [ WIDE_INDEX_WIDTH-1:0] write_ack_count;
     

     always@(posedge clock or negedge resetn)
     begin
       if(!resetn)
       begin
         write_ack_count   <= 0;        
       end
       else if (avm_writeack)
       begin
         write_ack_count   <= write_ack_count+1;
       end
       else
       begin
         write_ack_count   <= write_ack_count;
       end  
     end
     
       
     assign avm_writeack_wrapped = (write_ack_count  == {WIDE_INDEX_WIDTH{1'b1}} - 1 ) && avm_writeack; 
     

     always@(posedge clock or negedge resetn)
     begin
       if(!resetn)
       begin
         avm_address_reg   <= 0;
         avm_writedata_reg <= 0;
         avm_byteenable_reg <= 0;
         avm_burstcount_reg <= 0;

       end
       else if (start)
       begin
         avm_address_reg   <= avm_address_wrapped;
         avm_writedata_reg <= avm_writedata_wrapped;
         avm_byteenable_reg <= avm_byteenable_wrapped;
         avm_burstcount_reg <= avm_burstcount_wrapped;
       end
       else
       begin
         avm_address_reg   <= avm_address_reg;
         avm_writedata_reg <= avm_writedata_reg;
         avm_byteenable_reg <= avm_byteenable_reg;
         avm_burstcount_reg <= avm_burstcount_reg;
       end  
     end


     assign avm_waitrequest_wrapped = !ready;  
     assign avm_writedata =   avm_writedata_reg[((index+1)*MWIDTH-1)-:MWIDTH];
     assign avm_byteenable = avm_byteenable_reg[((index+1)*MWIDTH_BYTES-1)-:MWIDTH_BYTES];
     assign avm_address = avm_address_reg; 
     assign avm_burstcount = avm_burstcount_reg*WIDTH_RATIO;
     assign avm_write = in_progress;
     assign avm_read = 0;
     assign avm_enable = avm_enable_wrapped;
 
   end

end else begin
end
endgenerate

endmodule