data/full_repos/permissive/152128439/testbench.v
 line:60: before: "("
1: b'%Error: data/full_repos/permissive/152128439/testbench.v:50: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile ("dump.vcd");     \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/152128439/testbench.v:51: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars (0, testbench_spi);    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/152128439/testbench.v:61: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/152128439/testbench.v:64: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/152128439/testbench.v:67: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/152128439/testbench.v:69: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/152128439/testbench.v:72: syntax error, unexpected \'@\'\n      @(busy == 1\'b0);   \n      ^\n%Error: Exiting due to 7 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench_spi;
  reg clk, reset, read_master, write_master, write_slave;
  reg [7:0] din_master, din_slave;
  wire busy, sclk, miso, mosi;
  wire [7:0] dout_slave, dout_master;
  
  spi_master maestro (
    .clk(clk),
    .reset(reset),
    .din(din_master),
    .dout(dout_master),
    .read(read_master),
    .write(write_master),
    .busy(busy),
    .sclk(sclk),
    .miso(miso),
    .mosi(mosi)
  );
  
  spi_slave esclavo (
    .sclk(sclk),
    .mosi(mosi),
    .miso(miso),
    .din(din_slave),
    .dout(dout_slave),
    .write(write_slave)
  );
  
  initial begin
    $dumpfile ("dump.vcd");
    $dumpvars (0, testbench_spi);
    clk = 1'b0;
    reset = 1'b1;
    read_master = 1'b0;
    write_master = 1'b0;
    write_slave = 1'b0;
    din_slave = 8'hFF;
    din_master = 8'h00;
    
    repeat (2)
      @(posedge clk);
    reset = 1'b0;
    repeat (2)
      @(posedge clk);
    
    repeat (256) begin
      @(posedge clk);
      write_master = 1'b1;
      @(posedge clk);
      @(posedge clk);
      write_master = 1'b0;
      @(busy == 1'b0);
      @(posedge clk);
      din_master = din_master + 8'd1;
    end
    $finish;
  end
  
  always begin
    clk = #5 ~clk;
  end
endmodule
module testbench_spi;

  reg clk, reset, read_master, write_master, write_slave;
  reg [7:0] din_master, din_slave;
  wire busy, sclk, miso, mosi;
  wire [7:0] dout_slave, dout_master;
  
  spi_master maestro (
    .clk(clk),
    .reset(reset),
    .din(din_master),
    .dout(dout_master),
    .read(read_master),
    .write(write_master),
    .busy(busy),
    .sclk(sclk),
    .miso(miso),
    .mosi(mosi)
  );
  
  spi_slave esclavo (
    .sclk(sclk),
    .mosi(mosi),
    .miso(miso),
    .din(din_slave),
    .dout(dout_slave),
    .write(write_slave)
  );
  
  initial begin
    $dumpfile ("dump.vcd");
    $dumpvars (0, testbench_spi);
    clk = 1'b0;
    reset = 1'b1;
    read_master = 1'b0;
    write_master = 1'b0;
    write_slave = 1'b0;
    din_slave = 8'hFF;
    din_master = 8'h00;
    
    repeat (2)
      @(posedge clk);
    reset = 1'b0;
    repeat (2)
      @(posedge clk);
    
    repeat (256) begin
      @(posedge clk);
      write_master = 1'b1;
      @(posedge clk);
      @(posedge clk);
      write_master = 1'b0;
      @(busy == 1'b0);
      @(posedge clk);
      din_master = din_master + 8'd1;
    end
    $finish;
  end
  
  always begin
    clk = #5 ~clk;
  end
endmodule