data/full_repos/permissive/218779832/junk/pipeControl_main.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/218779832/junk/pipeControl_main.v:52: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'CCG1\'\nmodule CCG1\n       ^~~~\n                                                                                  : ... Top module \'CCG2\'\nmodule CCG2(\n       ^~~~\n                                                                                  : ... Top module \'CCG3\'\nmodule CCG3(\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/218779832/junk/pipeControl_main.v:134: Signal definition not found, creating implicitly: \'S82\'\nassign {S11, S10, S20, S30, S40, S50, S82, S81, S80} = muxBits;\n                                      ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/218779832/junk/pipeControl_main.v:134: Signal definition not found, creating implicitly: \'S81\'\n                                                                                   : ... Suggested alternative: \'S11\'\nassign {S11, S10, S20, S30, S40, S50, S82, S81, S80} = muxBits;\n                                           ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/218779832/junk/pipeControl_main.v:134: Signal definition not found, creating implicitly: \'S80\'\n                                                                                   : ... Suggested alternative: \'S10\'\nassign {S11, S10, S20, S30, S40, S50, S82, S81, S80} = muxBits;\n                                                ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/218779832/junk/pipeControl_main.v:92: Signal definition not found, creating implicitly: \'flagcheck\'\n                                                                                  : ... Suggested alternative: \'flagCheck\'\nassign flagcheck = FL_reg;\n       ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/218779832/junk/pipeControl_main.v:41: Signal definition not found, creating implicitly: \'flagCheck\'\n                                                                                  : ... Suggested alternative: \'flagCheck_1\'\nassign flagCheck = FL_reg;\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:134: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'muxBits\' generates 10 bits.\n                                                                                : ... In instance CCG3\nassign {S11, S10, S20, S30, S40, S50, S82, S81, S80} = muxBits;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:139: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n    muxBits = 9\'b000000000;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:148: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:153: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:159: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:164: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h80\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b01_0000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:169: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h180\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b11_0000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:174: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hc0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b01_1000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:179: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1c0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b11_1000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:184: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h140\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b10_1000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:190: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h80\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b01_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:194: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b00_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:200: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:205: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h5\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_101;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:210: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h3\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_011;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:215: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h6\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_110;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:222: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h21\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0100_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:230: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h180\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b11_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:233: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b00_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:241: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hc0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b01_1000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:244: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b00_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:252: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1c0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b11_1000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:255: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b00_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:262: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h21\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0100_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:268: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h140\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b10_1000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:271: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                : ... In instance CCG3\n            muxBits <= 9\'b00_0000_000;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:277: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h21\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0100_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:282: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h2\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_010;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:287: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:292: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h8\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0001_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:297: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h48\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_1001_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:302: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:308: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h4\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_100;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:313: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h44\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_1000_100;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:318: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:323: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:328: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:333: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:338: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:343: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:348: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:353: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:358: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:363: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:368: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:373: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:378: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0000_001;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/pipeControl_main.v:383: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h30\' generates 9 bits.\n                                                                                : ... In instance CCG3\n        muxBits <= 9\'b00_0110_000;\n                ^~\n%Error: Exiting due to 54 warning(s)\n'
module CCG2(
    input   clk,
    input   [7:0]  opcode_in_1,
    input   flagCheck_1,
    input   [7:0]  OR1,
    input   [7:0] NPC_in_1,
    output  [2:0] read_address,
    output  [7:0] opcode,
    output  flagCheck,
    output  [7:0] NPC_in, 
    output  [2:0] write_address,
    output   [7:0]  OR2
    
);

reg [7:0] OC_reg;
reg FL_reg;
reg [7:0] OR_reg;
reg [7:0] NPC;
reg [2:0] write;

initial begin
    FL_reg = 1'b0;
    OC_reg = 8'h00;
    OR_reg = 8'h00;


    NPC = 8'h00;
end

always @ (posedge clk)
begin
     FL_reg <=  flagCheck_1;
     OC_reg <=  opcode_in_1;
     OR_reg <=   OR1;
     NPC    <= NPC_in_1;
     write <= opcode_in_1[2:0];
end

assign opcode = OC_reg ;
assign flagcheck = FL_reg;
assign OR2 = OR_reg;
assign read_address = opcode_in_1[2:0];
assign write_address = write;
assign NPC_in = NPC;

endmodule
module CCG2(
    input   clk,
    input   [7:0]  opcode_in_1,
    input   flagCheck_1,
    input   [7:0]  OR1,
    input   [7:0] NPC_in_1,
    output  [2:0] read_address,
    output  [7:0] opcode,
    output  flagCheck,
    output  [7:0] NPC_in, 
    output  [2:0] write_address,
    output   [7:0]  OR2
    
);


reg [7:0] OC_reg;
reg FL_reg;
reg [7:0] OR_reg;
reg [7:0] NPC;
reg [2:0] write;

initial begin
    FL_reg = 1'b0;
    OC_reg = 8'h00;
    OR_reg = 8'h00;


    NPC = 8'h00;
end

always @ (posedge clk)
begin
     FL_reg <=  flagCheck_1;
     OC_reg <=  opcode_in_1;
     OR_reg <=   OR1;
     NPC    <= NPC_in_1;
     write <= opcode_in_1[2:0];
end

assign opcode = OC_reg ;
assign flagcheck = FL_reg;
assign OR2 = OR_reg;
assign read_address = opcode_in_1[2:0];
assign write_address = write;
assign NPC_in = NPC;

endmodule