data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v
 line:50: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #2.5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #2.5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #2.5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #2.5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #50 clk = ~ clk;\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:50: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #10 \n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:52: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:54: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:56: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:58: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:60: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:62: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:64: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:66: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:68: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:70: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:72: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:74: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:76: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:78: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:80: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:82: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:84: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:86: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:88: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:90: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:92: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/detector_tb.v:94: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: Exiting due to 23 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module detector_tb(

    );
    reg clk;
    reg w;
    wire z;
    wire [2:0] stage_no;
    detector ollo_detector(w,clk,z,stage_no);
    
    always
    begin
    clk =0;
    #2.5
    clk=1;
    #2.5
    clk=0;
    #2.5
    clk=1;
    #2.5
    clk=0;
    forever 
    #50 clk = ~ clk;
    end
    initial 
    begin
    w=0;
    #10 
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 0;

    end 
endmodule
module detector_tb(

    );

    reg clk;
    reg w;
    wire z;
    wire [2:0] stage_no;
    detector ollo_detector(w,clk,z,stage_no);
    
    always
    begin
    clk =0;
    #2.5
    clk=1;
    #2.5
    clk=0;
    #2.5
    clk=1;
    #2.5
    clk=0;
    forever 
    #50 clk = ~ clk;
    end
    initial 
    begin
    w=0;
    #10 
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 0;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 1;
    @(posedge clk);
    w <= 0;

    end 
endmodule