data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/sl2.v
data/verilator_xmls/3d20fcd3-5765-4f0b-ad2b-f3dd6713f592.xml
module sl2(
    input [29:0] a,
    output [31:0] y
    );
    
    assign #1 y={a,2'b00};
    
endmodule
module sl2(
    input [29:0] a,
    output [31:0] y
    );

    
    assign #1 y={a,2'b00};
    
endmodule