data/full_repos/permissive/105847195/top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/105847195/top.v:1: Cannot find include file: producer\n`include "producer" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105847195,data/full_repos/permissive/105847195/producer\n             data/full_repos/permissive/105847195,data/full_repos/permissive/105847195/producer.v\n             data/full_repos/permissive/105847195,data/full_repos/permissive/105847195/producer.sv\n             producer\n             producer.v\n             producer.sv\n             obj_dir/producer\n             obj_dir/producer.v\n             obj_dir/producer.sv\n%Error: data/full_repos/permissive/105847195/top.v:2: Cannot find include file: fifo\n`include "fifo" \n         ^~~~~~\n%Error: data/full_repos/permissive/105847195/top.v:3: Cannot find include file: consumer\n`include "consumer" \n         ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105847195/top.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #10 assign consumer_iclk = ~consumer_iclk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105847195/top.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #5 assign producer_iclk = ~producer_iclk;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/top.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1 assign clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/top.v:31: Unsupported: Ignoring delay on this delayed statement.\n          #50 $finish;\n          ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module top();
  
  
  reg consumer_iclk;
  reg producer_iclk;
  
  
  reg clk;
  
  
  
  
  
  
  always@(posedge clk)
    begin
      #10 assign consumer_iclk = ~consumer_iclk;
      #5 assign producer_iclk = ~producer_iclk;
      
    end
  
  always
    #1 assign clk = ~clk;
  
  
  initial
          #50 $finish;

endmodule
module top();

  
  
  reg consumer_iclk;
  reg producer_iclk;
  
  
  reg clk;
  
  
  
  
  
  
  always@(posedge clk)
    begin
      #10 assign consumer_iclk = ~consumer_iclk;
      #5 assign producer_iclk = ~producer_iclk;
      
    end
  
  always
    #1 assign clk = ~clk;
  
  
  initial
          #50 $finish;

endmodule