data/full_repos/permissive/206169433/pipeline/hazard_detection.v
1: b'%Warning-WIDTH: data/full_repos/permissive/206169433/pipeline/hazard_detection.v:30: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'EX_Rt\' generates 5 bits.\n                                                                                   : ... In instance hazard_detection\n        if (EX_memread && EX_Rt && ((ID_Rs == EX_Rt) || (ID_Rt == EX_Rt)) ) begin\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module hazard_detection(
    stall, flush,
    ID_branch_beq, ID_branch_bne,   
    ID_Rs, ID_Rt,
    EX_writeaddress, MEM_writeaddress,
    EX_Rt,
    MEM_memread,
    EX_memread,     
    EX_regwrite);

    input ID_branch_beq, ID_branch_bne,
          MEM_memread, EX_memread, EX_regwrite;
    input [4:0] ID_Rs, ID_Rt, EX_Rt,
                MEM_writeaddress, EX_writeaddress;
    output stall, flush;
    reg stall, flush;

    initial begin
      stall = 1'b0;
      flush = 1'b1;
    end

    always @ ( ID_branch_beq, ID_branch_bne, ID_Rs, ID_Rt,   
    EX_writeaddress, MEM_writeaddress, EX_Rt, MEM_memread,
    EX_memread, EX_regwrite)    begin


        if (EX_memread && EX_Rt && ((ID_Rs == EX_Rt) || (ID_Rt == EX_Rt)) ) begin
            stall = 1'b1; 
            flush = 1'b1;
        end

        else if (ID_branch_beq || ID_branch_bne) begin

            if (EX_regwrite && (EX_writeaddress!=0)
                && ((ID_Rs == EX_writeaddress) || (ID_Rt == EX_writeaddress)) ) begin
                stall = 1'b1;
                flush = 1'b1;
            end

            else if (MEM_memread && (MEM_writeaddress!=0)
                && ((ID_Rs == MEM_writeaddress) || (ID_Rt == MEM_writeaddress))) begin
                stall = 1'b1;
                flush = 1'b1;
            end
            else begin
                stall = 1'b0;
                flush = 1'b0;
            end
            end
        else begin
            stall = 1'b0;
            flush = 1'b0;
        end

    end

endmodule
module hazard_detection(
    stall, flush,
    ID_branch_beq, ID_branch_bne,   
    ID_Rs, ID_Rt,
    EX_writeaddress, MEM_writeaddress,
    EX_Rt,
    MEM_memread,
    EX_memread,     
    EX_regwrite);


    input ID_branch_beq, ID_branch_bne,
          MEM_memread, EX_memread, EX_regwrite;
    input [4:0] ID_Rs, ID_Rt, EX_Rt,
                MEM_writeaddress, EX_writeaddress;
    output stall, flush;
    reg stall, flush;

    initial begin
      stall = 1'b0;
      flush = 1'b1;
    end

    always @ ( ID_branch_beq, ID_branch_bne, ID_Rs, ID_Rt,   
    EX_writeaddress, MEM_writeaddress, EX_Rt, MEM_memread,
    EX_memread, EX_regwrite)    begin


        if (EX_memread && EX_Rt && ((ID_Rs == EX_Rt) || (ID_Rt == EX_Rt)) ) begin
            stall = 1'b1; 
            flush = 1'b1;
        end

        else if (ID_branch_beq || ID_branch_bne) begin

            if (EX_regwrite && (EX_writeaddress!=0)
                && ((ID_Rs == EX_writeaddress) || (ID_Rt == EX_writeaddress)) ) begin
                stall = 1'b1;
                flush = 1'b1;
            end

            else if (MEM_memread && (MEM_writeaddress!=0)
                && ((ID_Rs == MEM_writeaddress) || (ID_Rt == MEM_writeaddress))) begin
                stall = 1'b1;
                flush = 1'b1;
            end
            else begin
                stall = 1'b0;
                flush = 1'b0;
            end
            end
        else begin
            stall = 1'b0;
            flush = 1'b0;
        end

    end

endmodule