data/full_repos/permissive/159610434/i8255/rtl/breg.v
 line:1: before: "@"
data/verilator_xmls/36aef313-be5c-4bbc-8365-cef682c950f8.xml
module breg #(parameter INIT = 0) (
    input reset,
    input en,
    input [7:0] d,
    output reg [7:0] q
    );

    always @(*) begin
        if (reset)
            q <= INIT;
        else if (en)
            q <= d;
    end

endmodule
module breg #(parameter INIT = 0) (
    input reset,
    input en,
    input [7:0] d,
    output reg [7:0] q
    );


    always @(*) begin
        if (reset)
            q <= INIT;
        else if (en)
            q <= d;
    end

endmodule