data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/Tcounter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/Tcounter_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/Tcounter_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #50 clk = ~ clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/Tcounter_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/Tcounter_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n      #400\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/Tcounter_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #300\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/Tcounter_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #800\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/Tcounter_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #200\n      ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/Tcounter_tb.v:31: Cannot find file containing module: \'Tcounter\'\n    Tcounter #(5) counter(enable,restn,clk,Q);\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new,data/full_repos/permissive/165901145/Tcounter\n             data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new,data/full_repos/permissive/165901145/Tcounter.v\n             data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new,data/full_repos/permissive/165901145/Tcounter.sv\n             Tcounter\n             Tcounter.v\n             Tcounter.sv\n             obj_dir/Tcounter\n             obj_dir/Tcounter.v\n             obj_dir/Tcounter.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Tcounter_tb(

    );
    
    reg clk;
    reg restn;
    reg enable;
    wire [3:0] Q;
    Tcounter #(5) counter(enable,restn,clk,Q);
    
    always
    begin
    clk =0;
    #10
    clk=1;
    forever 
    #50 clk = ~ clk;
    end
    
    initial begin
      restn = 0;
      enable = 0;
      #10
      restn = 1;
      enable =1; 
      #400
      enable = 0;
      #300
      enable = 1;
      #800
      enable =0;
      #200
      enable = 1;
    end
endmodule
module Tcounter_tb(

    );

    
    reg clk;
    reg restn;
    reg enable;
    wire [3:0] Q;
    Tcounter #(5) counter(enable,restn,clk,Q);
    
    always
    begin
    clk =0;
    #10
    clk=1;
    forever 
    #50 clk = ~ clk;
    end
    
    initial begin
      restn = 0;
      enable = 0;
      #10
      restn = 1;
      enable =1; 
      #400
      enable = 0;
      #300
      enable = 1;
      #800
      enable =0;
      #200
      enable = 1;
    end
endmodule