data/full_repos/permissive/177334035/Source/DFF_1bit.v
data/verilator_xmls/ea943b44-947c-47a7-b015-78fe732a296a.xml
module DFF_1bit
(
    input  rst,
    input  clk,
    input  load,
    input  d,
    output reg q
);	
	 always @ (negedge clk or posedge rst)
	
	 if (rst)
	
		 q <= 0;
		
	 else if(load)
	
	  	 q <= d;

endmodule
module DFF_1bit
(
    input  rst,
    input  clk,
    input  load,
    input  d,
    output reg q
);
	
	 always @ (negedge clk or posedge rst)
	
	 if (rst)
	
		 q <= 0;
		
	 else if(load)
	
	  	 q <= d;

endmodule