data/full_repos/permissive/118895292/core/program_loader.v
1: b"%Error: data/full_repos/permissive/118895292/core/program_loader.v:27: Cannot find file containing module: 'baud_generator'\nbaud_generator rs232_baud(global_clk, baud_clk, baud_oversample_clk);\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/118895292/core,data/full_repos/permissive/118895292/baud_generator\n             data/full_repos/permissive/118895292/core,data/full_repos/permissive/118895292/baud_generator.v\n             data/full_repos/permissive/118895292/core,data/full_repos/permissive/118895292/baud_generator.sv\n             baud_generator\n             baud_generator.v\n             baud_generator.sv\n             obj_dir/baud_generator\n             obj_dir/baud_generator.v\n             obj_dir/baud_generator.sv\n%Error: data/full_repos/permissive/118895292/core/program_loader.v:32: Cannot find file containing module: 'byte_transmitter'\nbyte_transmitter rs232_transmitter(global_clk, baud_clk, byte_to_tx, tx_byte_now, rs232_tx);\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/118895292/core/program_loader.v:37: Cannot find file containing module: 'byte_receiver'\nbyte_receiver rx232_receiver(global_clk, baud_oversample_clk, byte_received_flag, byte_received, rs232_rx);\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module program_loader(
	global_clk,
	core_clk,
	rst,
	ram_addr_out,
	ram_data_out,
	ram_write_enable,
	rs232_tx,
	rs232_rx,
	load_complete);

parameter MAX_LOAD_ADDRESS = 16'hC000;

input global_clk;
input core_clk;
input rst;
output reg [15:0] ram_addr_out = 0;
output reg [15:0] ram_data_out = 0;
output reg ram_write_enable = 0;
output rs232_tx;
input rs232_rx;
output reg load_complete = 0;


wire baud_clk;
wire baud_oversample_clk;
baud_generator rs232_baud(global_clk, baud_clk, baud_oversample_clk);


reg tx_byte_now;
reg [7:0] byte_to_tx;
byte_transmitter rs232_transmitter(global_clk, baud_clk, byte_to_tx, tx_byte_now, rs232_tx);


wire byte_received_flag;
wire [7:0] byte_received;
byte_receiver rx232_receiver(global_clk, baud_oversample_clk, byte_received_flag, byte_received, rs232_rx);















reg [2:0] current_state = 0;
always @(posedge global_clk)
begin
	if (rst)
	begin
		current_state <= 0;
		ram_addr_out <= 0;
		ram_data_out <= 0;
		ram_write_enable <= 0;
		load_complete <= 0;
	end
	else
	begin
		case (current_state)
		0: begin

			byte_to_tx <= 8'h64;
			tx_byte_now <= 1;
			current_state <= 1;
		end
		1: begin

			tx_byte_now <= 0;
			current_state <= 2;
		end
		2: begin

			ram_write_enable <= 0;
			if (byte_received_flag && baud_clk)
			begin
				ram_data_out[15:8] <= byte_received;
				current_state <= 3;
			end
		end
		3: begin

			if (byte_received_flag && baud_clk)
			begin
				ram_data_out[7:0] <= byte_received;
				ram_write_enable <= 1;
				current_state <= 4;
			end
		end
		4: begin

			if (~byte_received_flag)
				current_state <= 5;
		end
		5: begin

			ram_write_enable <= 0;
			ram_addr_out <= ram_addr_out + 1;
			if (ram_addr_out < MAX_LOAD_ADDRESS)
			begin
				current_state <= 2;
			end
			else
			begin
				current_state <= 6;
			end
		end
		6: begin

			load_complete <= 1;
		end
		default: begin

			current_state <= 0;
		end
		endcase
	end
end

endmodule
module program_loader(
	global_clk,
	core_clk,
	rst,
	ram_addr_out,
	ram_data_out,
	ram_write_enable,
	rs232_tx,
	rs232_rx,
	load_complete);


parameter MAX_LOAD_ADDRESS = 16'hC000;

input global_clk;
input core_clk;
input rst;
output reg [15:0] ram_addr_out = 0;
output reg [15:0] ram_data_out = 0;
output reg ram_write_enable = 0;
output rs232_tx;
input rs232_rx;
output reg load_complete = 0;


wire baud_clk;
wire baud_oversample_clk;
baud_generator rs232_baud(global_clk, baud_clk, baud_oversample_clk);


reg tx_byte_now;
reg [7:0] byte_to_tx;
byte_transmitter rs232_transmitter(global_clk, baud_clk, byte_to_tx, tx_byte_now, rs232_tx);


wire byte_received_flag;
wire [7:0] byte_received;
byte_receiver rx232_receiver(global_clk, baud_oversample_clk, byte_received_flag, byte_received, rs232_rx);















reg [2:0] current_state = 0;
always @(posedge global_clk)
begin
	if (rst)
	begin
		current_state <= 0;
		ram_addr_out <= 0;
		ram_data_out <= 0;
		ram_write_enable <= 0;
		load_complete <= 0;
	end
	else
	begin
		case (current_state)
		0: begin

			byte_to_tx <= 8'h64;
			tx_byte_now <= 1;
			current_state <= 1;
		end
		1: begin

			tx_byte_now <= 0;
			current_state <= 2;
		end
		2: begin

			ram_write_enable <= 0;
			if (byte_received_flag && baud_clk)
			begin
				ram_data_out[15:8] <= byte_received;
				current_state <= 3;
			end
		end
		3: begin

			if (byte_received_flag && baud_clk)
			begin
				ram_data_out[7:0] <= byte_received;
				ram_write_enable <= 1;
				current_state <= 4;
			end
		end
		4: begin

			if (~byte_received_flag)
				current_state <= 5;
		end
		5: begin

			ram_write_enable <= 0;
			ram_addr_out <= ram_addr_out + 1;
			if (ram_addr_out < MAX_LOAD_ADDRESS)
			begin
				current_state <= 2;
			end
			else
			begin
				current_state <= 6;
			end
		end
		6: begin

			load_complete <= 1;
		end
		default: begin

			current_state <= 0;
		end
		endcase
	end
end

endmodule