data/full_repos/permissive/210844779/lab7/7.3/add_sub.v
 line:11: before: "#"
1: b'%Warning-WIDTH: data/full_repos/permissive/210844779/lab7/7.3/add_sub.v:6: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                         : ... In instance add_sub\nassign add = a + b + cin;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module add_sub(a,b,cin,add);
  output [3:0] add;
input [3:0] a;
input [3:0] b;
input cin;
assign add = a + b + cin;
endmodule
module add_sub(a,b,cin,add);

  output [3:0] add;
input [3:0] a;
input [3:0] b;
input cin;
assign add = a + b + cin;
endmodule