data/full_repos/permissive/155759747/mem.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/155759747/mem.v:41: Signal definition not found, creating implicitly: \'counter_out\'\n                                                                : ... Suggested alternative: \'counter_output\'\n assign counter_out = count;\n        ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/155759747/mem.v:26: Cannot find file containing module: \'ram256x16\'\n ram256x16 mem( \n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155759747,data/full_repos/permissive/155759747/ram256x16\n             data/full_repos/permissive/155759747,data/full_repos/permissive/155759747/ram256x16.v\n             data/full_repos/permissive/155759747,data/full_repos/permissive/155759747/ram256x16.sv\n             ram256x16\n             ram256x16.v\n             ram256x16.sv\n             obj_dir/ram256x16\n             obj_dir/ram256x16.v\n             obj_dir/ram256x16.sv\n%Warning-WIDTH: data/full_repos/permissive/155759747/mem.v:37: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                             : ... In instance mem\n   count <= 3\'d0 ;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/155759747/mem.v:41: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'count\' generates 4 bits.\n                                                             : ... In instance mem\n assign counter_out = count;\n                    ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module mem(
	address,
	clock,
	data,
	wren,
	counter_enable,
	counter_reset,
	counter_output,
	q
	);
	
	input	[7:0]  address;
	input	  clock;
	input	[15:0]  data;
	input	  wren;
	
	input counter_enable;
	input counter_reset;
	output counter_output; 
	output	[15:0]  q;
	
	reg [3:0] count;
	
	ram256x16 mem( 
		.address   	(address),
		.clock		(clock), 
		.data		(data), 
		.wren		(wren), 
		.q 			(q)
		);
	
	always @(posedge clock)
	begin
		if (counter_reset) 
			count <= 3'd0 ;
		else if (counter_enable) 
	    	count <= count + 3'd1;
	end
	assign counter_out = count;
	
		
endmodule
module mem(
	address,
	clock,
	data,
	wren,
	counter_enable,
	counter_reset,
	counter_output,
	q
	);

	
	input	[7:0]  address;
	input	  clock;
	input	[15:0]  data;
	input	  wren;
	
	input counter_enable;
	input counter_reset;
	output counter_output; 
	output	[15:0]  q;
	
	reg [3:0] count;
	
	ram256x16 mem( 
		.address   	(address),
		.clock		(clock), 
		.data		(data), 
		.wren		(wren), 
		.q 			(q)
		);
	
	always @(posedge clock)
	begin
		if (counter_reset) 
			count <= 3'd0 ;
		else if (counter_enable) 
	    	count <= count + 3'd1;
	end
	assign counter_out = count;
	
		
endmodule