data/full_repos/permissive/155085421/testbenches/clock_generator/testbench-clocks.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/155085421/testbenches/clock_generator/testbench-clocks.v:3: Cannot find include file: ../../clock_generator.v\n`include "../../clock_generator.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155085421/testbenches/clock_generator,data/full_repos/permissive/155085421/../../clock_generator.v\n             data/full_repos/permissive/155085421/testbenches/clock_generator,data/full_repos/permissive/155085421/../../clock_generator.v.v\n             data/full_repos/permissive/155085421/testbenches/clock_generator,data/full_repos/permissive/155085421/../../clock_generator.v.sv\n             ../../clock_generator.v\n             ../../clock_generator.v.v\n             ../../clock_generator.v.sv\n             obj_dir/../../clock_generator.v\n             obj_dir/../../clock_generator.v.v\n             obj_dir/../../clock_generator.v.sv\n%Error: data/full_repos/permissive/155085421/testbenches/clock_generator/testbench-clocks.v:7: Unsupported or unknown PLI call: $dumpvars\ninitial $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/clock_generator/testbench-clocks.v:15: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clock_144mhz <= ~clock_144mhz;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/clock_generator/testbench-clocks.v:16: Unsupported: Ignoring delay on this delayed statement.\nalways #12 clock_12mhz <= ~clock_12mhz;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/clock_generator/testbench-clocks.v:19: Unsupported: Ignoring delay on this delayed statement.\ninitial #24000 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/clock_generator/testbench-clocks.v:27: Unsupported: Ignoring delay on this delayed statement.\ninitial #500 uart_rx <= 1;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module test;

initial $dumpvars;

reg clock_144mhz;
reg clock_12mhz;
reg reset;

initial clock_144mhz <= 0;
initial clock_12mhz <= 0;
always #1 clock_144mhz <= ~clock_144mhz;
always #12 clock_12mhz <= ~clock_12mhz;


initial #24000 $finish;


reg uart_rx;
initial uart_rx <= 0;
initial #500 uart_rx <= 1;


wire bit_segment_clock, bit_clock, led_clock, framerate;

clock_generator clocks(
    .clock_144mhz(clock_144mhz),
    .clock_12mhz(clock_12mhz),
    .bit_segment_clock(bit_segment_clock),
    .bit_clock(bit_clock),
    .led_clock(led_clock),
    .framerate(framerate),
    .uart_rx(uart_rx)
    );

endmodule
module test;


initial $dumpvars;

reg clock_144mhz;
reg clock_12mhz;
reg reset;

initial clock_144mhz <= 0;
initial clock_12mhz <= 0;
always #1 clock_144mhz <= ~clock_144mhz;
always #12 clock_12mhz <= ~clock_12mhz;


initial #24000 $finish;


reg uart_rx;
initial uart_rx <= 0;
initial #500 uart_rx <= 1;


wire bit_segment_clock, bit_clock, led_clock, framerate;

clock_generator clocks(
    .clock_144mhz(clock_144mhz),
    .clock_12mhz(clock_12mhz),
    .bit_segment_clock(bit_segment_clock),
    .bit_clock(bit_clock),
    .led_clock(led_clock),
    .framerate(framerate),
    .uart_rx(uart_rx)
    );

endmodule