data/full_repos/permissive/123043192/FPGA/USB/Loopback-FPGA/USB_Loopback.srcs/sources_1/new/USBLoopBack.v
data/verilator_xmls/041ba038-82d6-4c24-9fd5-eadcce6a6cb0.xml
module USBLoopBack(
    input [7:0] InputData,
    output [7:0] OutputData,
    input Clock
    );
endmodule
module USBLoopBack(
    input [7:0] InputData,
    output [7:0] OutputData,
    input Clock
    );

endmodule