data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/ring_combiner/ring_combiner.sv
1: b"%Error: data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/ring_combiner/ring_combiner.sv:27: Cannot find file containing module: 'altera_std_synchronizer'\naltera_std_synchronizer #(\n^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/ring_combiner,data/full_repos/permissive/148200700/altera_std_synchronizer\n             data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/ring_combiner,data/full_repos/permissive/148200700/altera_std_synchronizer.v\n             data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/ring_combiner,data/full_repos/permissive/148200700/altera_std_synchronizer.sv\n             altera_std_synchronizer\n             altera_std_synchronizer.v\n             altera_std_synchronizer.sv\n             obj_dir/altera_std_synchronizer\n             obj_dir/altera_std_synchronizer.v\n             obj_dir/altera_std_synchronizer.sv\n%Error: data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/ring_combiner/ring_combiner.sv:36: Cannot find file containing module: 'altera_std_synchronizer'\naltera_std_synchronizer #(\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/ring_combiner/ring_combiner.sv:45: Cannot find file containing module: 'altera_std_synchronizer'\naltera_std_synchronizer #(\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module ring_combiner
#(
	parameter SYNC_DEPTH = 5
)(
	input  wire clk,
	input  wire reset,
	
	input  wire ring_osc_0,
	input  wire ring_osc_1,
	input  wire ring_osc_2,
	
	output reg  xor_out
);

wire ring_osc_0_sync;
wire ring_osc_1_sync;
wire ring_osc_2_sync;

always @(posedge clk or posedge reset) begin
	if(reset) begin
		xor_out <= 1'b0;
	end else begin
		xor_out <= ring_osc_0_sync ^ (ring_osc_1_sync ^ ring_osc_2_sync);
	end
end

altera_std_synchronizer #(
	.depth (SYNC_DEPTH)
) ring_osc_0_synchronizer (
	.clk (clk),
	.reset_n (~reset),
	.din (ring_osc_0),
	.dout (ring_osc_0_sync)
);

altera_std_synchronizer #(
	.depth (SYNC_DEPTH)
) ring_osc_1_synchronizer (
	.clk (clk),
	.reset_n (~reset),
	.din (ring_osc_1),
	.dout (ring_osc_1_sync)
);

altera_std_synchronizer #(
	.depth (SYNC_DEPTH)
) ring_osc_2_synchronizer (
	.clk (clk),
	.reset_n (~reset),
	.din (ring_osc_2),
	.dout (ring_osc_2_sync)
);

endmodule
module ring_combiner
#(
	parameter SYNC_DEPTH = 5
)(
	input  wire clk,
	input  wire reset,
	
	input  wire ring_osc_0,
	input  wire ring_osc_1,
	input  wire ring_osc_2,
	
	output reg  xor_out
);


wire ring_osc_0_sync;
wire ring_osc_1_sync;
wire ring_osc_2_sync;

always @(posedge clk or posedge reset) begin
	if(reset) begin
		xor_out <= 1'b0;
	end else begin
		xor_out <= ring_osc_0_sync ^ (ring_osc_1_sync ^ ring_osc_2_sync);
	end
end

altera_std_synchronizer #(
	.depth (SYNC_DEPTH)
) ring_osc_0_synchronizer (
	.clk (clk),
	.reset_n (~reset),
	.din (ring_osc_0),
	.dout (ring_osc_0_sync)
);

altera_std_synchronizer #(
	.depth (SYNC_DEPTH)
) ring_osc_1_synchronizer (
	.clk (clk),
	.reset_n (~reset),
	.din (ring_osc_1),
	.dout (ring_osc_1_sync)
);

altera_std_synchronizer #(
	.depth (SYNC_DEPTH)
) ring_osc_2_synchronizer (
	.clk (clk),
	.reset_n (~reset),
	.din (ring_osc_2),
	.dout (ring_osc_2_sync)
);

endmodule