data/full_repos/permissive/100638358/TRAB3_triangulo02.v
 line:69: before: "$"
1: b'%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:22: syntax error, unexpected inside, expecting \'[\'\n    output inside\n           ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:27: syntax error, unexpected assign\n    assign inside = (sign1 == 1 && sign2 == 1 && sign3 == 1) ? 1:0;\n    ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:38: syntax error, unexpected inside, expecting IDENTIFIER or do or final\n    wire inside;\n         ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:40: syntax error, unexpected inside, expecting \')\'\n    TestTriangle A(X1, Y1, X2, Y2, X3, Y3, X4, Y, inside);\n                                                  ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:44: Unsupported or unknown PLI call: $dumpvars\n           $dumpvars(0,A);\n           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:45: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:56: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:59: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:62: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:65: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:68: Unsupported: Ignoring delay on this delayed statement.\n           #40\n           ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n'
module Test;
    reg [11:0] X1, Y1, X2, Y2, X3, Y3, X4, Y;

    wire inside;

    TestTriangle A(X1, Y1, X2, Y2, X3, Y3, X4, Y, inside);

    initial
        begin
           $dumpvars(0,A);
           #1

           X1 <= 10;
           Y1 <= 10;
           X2 <= 30;
           Y2 <= 10;
           X3 <= 20;
           Y3 <= 30;
           X4 <= 15;
           Y <= 15;

           #1
           X4 <= 15;
           Y <= 15;
           #1
           X4 <= 9;
           Y <= 15;
           #1
           X4 <= 10;
           Y <= 11;
           #1
           X4 <= 30;
           Y <= 11;
           #40
           $finish;
        end
endmodule
module Test;

    reg [11:0] X1, Y1, X2, Y2, X3, Y3, X4, Y;

    wire inside;

    TestTriangle A(X1, Y1, X2, Y2, X3, Y3, X4, Y, inside);

    initial
        begin
           $dumpvars(0,A);
           #1

           X1 <= 10;
           Y1 <= 10;
           X2 <= 30;
           Y2 <= 10;
           X3 <= 20;
           Y3 <= 30;
           X4 <= 15;
           Y <= 15;

           #1
           X4 <= 15;
           Y <= 15;
           #1
           X4 <= 9;
           Y <= 15;
           #1
           X4 <= 10;
           Y <= 11;
           #1
           X4 <= 30;
           Y <= 11;
           #40
           $finish;
        end
endmodule