data/full_repos/permissive/140572461/hdl/cpu_core.v
 line:134: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/140572461/hdl/cpu_core.v:133: Unsupported: Ignoring delay on this delayed statement.\n    #50 reset <= 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/140572461/hdl/cpu_core.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #85 $display("addr %x: %s",\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/140572461/hdl/cpu_core.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #10000000 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/140572461/hdl/cpu_core.v:140: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk <= ~clk;\n       ^\n%Error: data/full_repos/permissive/140572461/hdl/cpu_core.v:38: Cannot find file containing module: \'ram\'\nram #(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/140572461/hdl,data/full_repos/permissive/140572461/ram\n             data/full_repos/permissive/140572461/hdl,data/full_repos/permissive/140572461/ram.v\n             data/full_repos/permissive/140572461/hdl,data/full_repos/permissive/140572461/ram.sv\n             ram\n             ram.v\n             ram.sv\n             obj_dir/ram\n             obj_dir/ram.v\n             obj_dir/ram.sv\n%Error: data/full_repos/permissive/140572461/hdl/cpu_core.v:57: Cannot find file containing module: \'rom\'\nrom #(\n^~~\n%Error: data/full_repos/permissive/140572461/hdl/cpu_core.v:75: Cannot find file containing module: \'gpio\'\ngpio gpio1_device(\n^~~~\n%Error: data/full_repos/permissive/140572461/hdl/cpu_core.v:86: Cannot find file containing module: \'cpu\'\ncpu cpu(\n^~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_core_tb;

reg clk = 0;
reg reset = 1;
wire [7:0] fakeled;

`ifndef LEDBLINKHEX
    `define LEDBLINKHEX "../../../../../asm/ledblink.hex"
`endif
cpu_core #(.ROM_FILE(`LEDBLINKHEX)) DUT(
    .clk (clk),
    .reset (reset),
    .gpio1 (fakeled)
);

`ifndef FINISHTIME
    `define FINISHTIME 10000000
`endif

initial begin
    #50 reset <= 0;
    #85 $display("addr %x: %s",
        DUT.addr,
        (DUT.addr == 16'hfc00) ? "OK" : "FAIL");
    #`FINISHTIME $stop;
end

always #10 clk <= ~clk;

always @(fakeled) $display("fakeled=%02x", fakeled);

endmodule
module cpu_core_tb;


reg clk = 0;
reg reset = 1;
wire [7:0] fakeled;

`ifndef LEDBLINKHEX
    `define LEDBLINKHEX "../../../../../asm/ledblink.hex"
`endif
cpu_core #(.ROM_FILE(`LEDBLINKHEX)) DUT(
    .clk (clk),
    .reset (reset),
    .gpio1 (fakeled)
);

`ifndef FINISHTIME
    `define FINISHTIME 10000000
`endif

initial begin
    #50 reset <= 0;
    #85 $display("addr %x: %s",
        DUT.addr,
        (DUT.addr == 16'hfc00) ? "OK" : "FAIL");
    #`FINISHTIME $stop;
end

always #10 clk <= ~clk;

always @(fakeled) $display("fakeled=%02x", fakeled);

endmodule