data/full_repos/permissive/161356276/hdl/testbench/top_ddr/dvi_colorbar_gen.sv
 line:86: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/testbench/top_ddr/dvi_colorbar_gen.sv:117: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                  : ... In instance colorbar_gen\n      b <= (xcount < g_xres && ycount <g_yres ? xcount + ycount : 0);\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module dvi_colorbar_gen
  ( output [3:0] TMDS,
    output [3:0] TMDSB );

   parameter g_pixel_clock = 100e6;
   parameter g_xres = 128;
   parameter g_yres = 128;
   parameter g_porch = 160;

   reg           hsync=0,vsync=0,de=0;
   reg  [7:0]         r,g,b;
   

   localparam period = 1s/g_pixel_clock;

   reg                pclkx10=0;
   reg                pclk= 0, pclkx2=0;
   wire                serdesstrobe;

   always #(period/2) pclkx10 <= ~pclkx10;
   integer                div5cnt=0;
   always@(posedge pclkx10)
     begin
      if(div5cnt == 2)
        pclkx2 <= 0;
      if(div5cnt == 4) begin
         pclkx2 <= 1;
         div5cnt <= 0;
      end else
        div5cnt<=div5cnt+1;
     end

   always@(posedge pclkx2)
     pclk <= ~pclk;

   reg pclkx2_d0=0;
   
   always@(posedge pclkx10)
        pclkx2_d0 <= pclkx2;
   
   assign   serdesstrobe = ~pclkx2_d0 && pclkx2;

   
   reg rst = 1;

   initial #100ns rst = 0;
   
   dvi_encoder_top U_Enc (
                          .pclk(pclk),
                          .pclkx2(pclkx2),
                          .pclkx10(pclkx10),
                          .serdesstrobe(serdesstrobe),
                          .rstin(rst),
                          .blue_din(b),
                          .green_din(g),
                          .red_din(r),
                          .hsync(hsync),
                          .vsync(vsync),
                          .de(de),
                          .TMDS(TMDS),
                          .TMDSB(TMDSB));
               
endmodule
module dvi_colorbar_gen
  ( output [3:0] TMDS,
    output [3:0] TMDSB );


   parameter g_pixel_clock = 100e6;
   parameter g_xres = 128;
   parameter g_yres = 128;
   parameter g_porch = 160;

   reg           hsync=0,vsync=0,de=0;
   reg  [7:0]         r,g,b;
   

   localparam period = 1s/g_pixel_clock;

   reg                pclkx10=0;
   reg                pclk= 0, pclkx2=0;
   wire                serdesstrobe;

   always #(period/2) pclkx10 <= ~pclkx10;
   integer                div5cnt=0;
   always@(posedge pclkx10)
     begin
      if(div5cnt == 2)
        pclkx2 <= 0;
      if(div5cnt == 4) begin
         pclkx2 <= 1;
         div5cnt <= 0;
      end else
        div5cnt<=div5cnt+1;
     end

   always@(posedge pclkx2)
     pclk <= ~pclk;

   reg pclkx2_d0=0;
   
   always@(posedge pclkx10)
        pclkx2_d0 <= pclkx2;
   
   assign   serdesstrobe = ~pclkx2_d0 && pclkx2;

   
   reg rst = 1;

   initial #100ns rst = 0;
   
   dvi_encoder_top U_Enc (
                          .pclk(pclk),
                          .pclkx2(pclkx2),
                          .pclkx10(pclkx10),
                          .serdesstrobe(serdesstrobe),
                          .rstin(rst),
                          .blue_din(b),
                          .green_din(g),
                          .red_din(r),
                          .hsync(hsync),
                          .vsync(vsync),
                          .de(de),
                          .TMDS(TMDS),
                          .TMDSB(TMDSB));
               
endmodule