data/full_repos/permissive/193530477/source codes/CNT138T.v
1: b'%Error: Cannot find file containing module: codes,data/full_repos/permissive/193530477\n        ... Looked in:\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.v\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.sv\n             codes,data/full_repos/permissive/193530477\n             codes,data/full_repos/permissive/193530477.v\n             codes,data/full_repos/permissive/193530477.sv\n             obj_dir/codes,data/full_repos/permissive/193530477\n             obj_dir/codes,data/full_repos/permissive/193530477.v\n             obj_dir/codes,data/full_repos/permissive/193530477.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/193530477/source\n%Error: Cannot find file containing module: codes/CNT138T.v\n%Error: Exiting due to 3 error(s)\n'
module CNT138T (CLK, STATE, end_addr, start_addr, CNT8);
	input CLK;
	input[3:0] STATE;
	input[9:0] end_addr;
	input[9:0] start_addr;
	output[9:0] CNT8;


	reg[9:0] CNT;
	reg LD = 1'b1;
	reg[3:0] pre_state = 4'b0001;
	


	always @ (posedge CLK or posedge LD) begin
		if( LD )	CNT <= start_addr;
		else if ( CNT >= end_addr ) CNT <= start_addr;
		else 	  CNT <= CNT + 1'b1;
	end
	
	

	always @ (STATE or CLK or start_addr or end_addr or pre_state) begin
		if (pre_state != STATE) begin
			LD <=  1'b1;
			pre_state <= STATE;
			end 
		else 	LD <=  1'b0;
	end 
	
	assign CNT8 = CNT;
endmodule
module CNT138T (CLK, STATE, end_addr, start_addr, CNT8);

	input CLK;
	input[3:0] STATE;
	input[9:0] end_addr;
	input[9:0] start_addr;
	output[9:0] CNT8;


	reg[9:0] CNT;
	reg LD = 1'b1;
	reg[3:0] pre_state = 4'b0001;
	


	always @ (posedge CLK or posedge LD) begin
		if( LD )	CNT <= start_addr;
		else if ( CNT >= end_addr ) CNT <= start_addr;
		else 	  CNT <= CNT + 1'b1;
	end
	
	

	always @ (STATE or CLK or start_addr or end_addr or pre_state) begin
		if (pre_state != STATE) begin
			LD <=  1'b1;
			pre_state <= STATE;
			end 
		else 	LD <=  1'b0;
	end 
	
	assign CNT8 = CNT;
endmodule