data/full_repos/permissive/179227721/daughterboard_demo/counter.v
1: b"%Error: data/full_repos/permissive/179227721/daughterboard_demo/counter.v:9: Duplicate declaration of signal: 'carry'\n                                                                           : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n   reg                       carry;\n                             ^~~~~\n        data/full_repos/permissive/179227721/daughterboard_demo/counter.v:5: ... Location of original declaration\n                output       carry\n                             ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module counter (
                input        clk,
                input        rst,
                output [3:0] cnt,
                output       carry
                );

   reg [4:0]                 counter;
   reg                       carry;

   always@(posedge clk, negedge rst)
     begin
        if (!rst)
          begin
             counter <= 0;
             carry <= 0;
          end
        else
          begin
             if (counter == 4'b1001)
               begin
                  counter <= 0;
                  carry <= 1;
               end
             else
               begin
                  counter <= counter + 1;
                  carry <= 0;
               end
          end
     end

   assign cnt = counter;
endmodule
module counter (
                input        clk,
                input        rst,
                output [3:0] cnt,
                output       carry
                );


   reg [4:0]                 counter;
   reg                       carry;

   always@(posedge clk, negedge rst)
     begin
        if (!rst)
          begin
             counter <= 0;
             carry <= 0;
          end
        else
          begin
             if (counter == 4'b1001)
               begin
                  counter <= 0;
                  carry <= 1;
               end
             else
               begin
                  counter <= counter + 1;
                  carry <= 0;
               end
          end
     end

   assign cnt = counter;
endmodule