data/full_repos/permissive/121803953/Lab2/lab2.v
data/verilator_xmls/d30f6656-4afb-4621-883b-a3d78d745bea.xml
module part2(a, b, c, d, Y);
    input a, b, c, d;
    output Y;
    wire x1, x2, x3;
    nand n1(x1, a, ~b);
    nand n2(x2, a, c, ~d);
    nand n3(x3, ~b, ~d);
    nand n4(Y, x1, x2, x3);
endmodule
module part2(a, b, c, d, Y);

    input a, b, c, d;
    output Y;
    wire x1, x2, x3;
    nand n1(x1, a, ~b);
    nand n2(x2, a, c, ~d);
    nand n3(x3, ~b, ~d);
    nand n4(Y, x1, x2, x3);
endmodule