data/full_repos/permissive/2084115/testbench/sim/rtos/tb_queue_fifo/tb_sim.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_queue_fifo/tb_sim.sv:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_sim.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_queue_fifo/tb_sim.sv:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_sim);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_queue_fifo/tb_sim.sv:19: Unsupported: Ignoring delay on this delayed statement.\n    #1000000\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_queue_fifo/tb_sim.sv:24: Unsupported: Ignoring delay on this delayed statement.\n    initial #(RATE*10) reset <= 1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/rtos/tb_queue_fifo/tb_sim.sv:27: Unsupported: Ignoring delay on this delayed statement.\n    always  #(RATE/2.0) clk  = ~clk;\n            ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sim();
    localparam RATE = 1000.0/200.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #1000000
        $finish;
    end
    
    logic     reset = 1'b1;
    initial #(RATE*10) reset <= 1'b0;

    logic     clk = 1'b1;
    always  #(RATE/2.0) clk  = ~clk;
    





    
    tb_sim_main
        i_sim_main
            (
                .*
            );
    
    


    
endmodule
module tb_sim();

    localparam RATE = 1000.0/200.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #1000000
        $finish;
    end
    
    logic     reset = 1'b1;
    initial #(RATE*10) reset <= 1'b0;

    logic     clk = 1'b1;
    always  #(RATE/2.0) clk  = ~clk;
    





    
    tb_sim_main
        i_sim_main
            (
                .*
            );
    
    


    
endmodule