data/full_repos/permissive/194007311/filter_basic_fixed.v
1: b'%Warning-WIDTH: data/full_repos/permissive/194007311/filter_basic_fixed.v:52: Operator ADD expects 36 bits on the LHS, but LHS\'s VARREF \'filter_out_prev\' generates 32 bits.\n                                                                            : ... In instance filter_basic\n  filter_out_temp <= filter_out_prev +( GAIN_1 * filter_input )+ (GAIN_2 * filter_output);\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module filter_basic( clk, rst, filter_input, filter_output );




parameter REG_MAX = 32;
parameter GAIN_1 = 1;
parameter GAIN_2 = 16;



input clk;
input rst;
input [REG_MAX - 1 :0] filter_input;



output reg [REG_MAX - 1: 0] filter_output = 0;



reg signed [REG_MAX - 1 : 0 ] filter_out_prev = 0;
reg signed [REG_MAX + 3 : 0 ] filter_out_temp = 0;

always @(posedge clk) begin
	if (rst) begin
		filter_out_prev <= 0;
		filter_output <= 0;
		filter_out_temp <= 0;
	end
	else begin
		filter_out_temp <= filter_out_prev +( GAIN_1 * filter_input )+ (GAIN_2 * filter_output);
		filter_output <= filter_out_temp[REG_MAX + 3 : 4 ];
		filter_out_prev <= filter_output;
	end
end


endmodule
module filter_basic( clk, rst, filter_input, filter_output );





parameter REG_MAX = 32;
parameter GAIN_1 = 1;
parameter GAIN_2 = 16;



input clk;
input rst;
input [REG_MAX - 1 :0] filter_input;



output reg [REG_MAX - 1: 0] filter_output = 0;



reg signed [REG_MAX - 1 : 0 ] filter_out_prev = 0;
reg signed [REG_MAX + 3 : 0 ] filter_out_temp = 0;

always @(posedge clk) begin
	if (rst) begin
		filter_out_prev <= 0;
		filter_output <= 0;
		filter_out_temp <= 0;
	end
	else begin
		filter_out_temp <= filter_out_prev +( GAIN_1 * filter_input )+ (GAIN_2 * filter_output);
		filter_output <= filter_out_temp[REG_MAX + 3 : 4 ];
		filter_out_prev <= filter_output;
	end
end


endmodule