data/full_repos/permissive/185301529/mp3_tb.sv
 line:3: before: "1"
1: b'%Warning-STMTDLY: data/full_repos/permissive/185301529/mp3_tb.sv:43: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/185301529/mp3_tb.sv:45: Can\'t find definition of \'datapath\' in dotted scope/variable: \'dut.datapath\'\nassign registers = dut.datapath.regfile.data;\n                       ^~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/185301529/mp3_tb.sv:45: Can\'t find definition of \'regfile\' in dotted scope/variable: \'dut.regfile\'\nassign registers = dut.datapath.regfile.data;\n                                ^~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/185301529/mp3_tb.sv:46: Can\'t find definition of \'datapath\' in dotted scope/variable: \'dut.datapath\'\nassign halt = dut.datapath.pcmux_sel & (dut.datapath.ex_pc_out == dut.datapath.if_pcmux_out);\n                  ^~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/185301529/mp3_tb.sv:46: Can\'t find definition of \'datapath\' in dotted scope/variable: \'dut.datapath\'\nassign halt = dut.datapath.pcmux_sel & (dut.datapath.ex_pc_out == dut.datapath.if_pcmux_out);\n                                            ^~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/185301529/mp3_tb.sv:46: Can\'t find definition of \'datapath\' in dotted scope/variable: \'dut.datapath\'\nassign halt = dut.datapath.pcmux_sel & (dut.datapath.ex_pc_out == dut.datapath.if_pcmux_out);\n                                                                      ^~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/185301529/mp3_tb.sv:60: Can\'t find definition of \'datapath\' in dotted scope/variable: \'dut.datapath\'\n    if (dut.datapath.pipeline_continue) order = order + 1;\n            ^~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: Exiting due to 6 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mp3_tb;

timeunit 1ns;
timeprecision 1ns;

logic clk;




logic write;
logic [15:0] errcode;
logic [31:0] registers [32];
logic halt;
logic [63:0] order;

logic [31:0] write_address;
logic [31:0] write_data;


logic read;
logic mem_write;
logic [31:0] address;
logic [255:0] wdata;
logic resp;
logic [255:0] rdata;

initial
begin
    clk = 0;
    order = 0;
end


always #5 clk = ~clk;

assign registers = dut.datapath.regfile.data;
assign halt = dut.datapath.pcmux_sel & (dut.datapath.ex_pc_out == dut.datapath.if_pcmux_out);

always @(posedge clk)
begin
    if (mem_write & resp) begin
        write_address = address;
        write_data = wdata;
        write = 1;
    end else begin
        write_address = 32'hx;
        write_data = 32'hx;
        write = 0;
    end
    if (halt) $finish;
    if (dut.datapath.pipeline_continue) order = order + 1;
end

mp3 dut
(
	.clk(clk),
	.read(read),
	.write(mem_write),
	.address(address),
	.wdata(wdata),
	.resp(resp),
	.rdata(rdata)
);

physical_memory memory
(
	.clk(clk),
	.read(read),
	.write(mem_write),
	.address(address),
	.wdata(wdata),
	.resp(resp),
	.rdata(rdata),
	.error()
);



endmodule
module mp3_tb;


timeunit 1ns;
timeprecision 1ns;

logic clk;




logic write;
logic [15:0] errcode;
logic [31:0] registers [32];
logic halt;
logic [63:0] order;

logic [31:0] write_address;
logic [31:0] write_data;


logic read;
logic mem_write;
logic [31:0] address;
logic [255:0] wdata;
logic resp;
logic [255:0] rdata;

initial
begin
    clk = 0;
    order = 0;
end


always #5 clk = ~clk;

assign registers = dut.datapath.regfile.data;
assign halt = dut.datapath.pcmux_sel & (dut.datapath.ex_pc_out == dut.datapath.if_pcmux_out);

always @(posedge clk)
begin
    if (mem_write & resp) begin
        write_address = address;
        write_data = wdata;
        write = 1;
    end else begin
        write_address = 32'hx;
        write_data = 32'hx;
        write = 0;
    end
    if (halt) $finish;
    if (dut.datapath.pipeline_continue) order = order + 1;
end

mp3 dut
(
	.clk(clk),
	.read(read),
	.write(mem_write),
	.address(address),
	.wdata(wdata),
	.resp(resp),
	.rdata(rdata)
);

physical_memory memory
(
	.clk(clk),
	.read(read),
	.write(mem_write),
	.address(address),
	.wdata(wdata),
	.resp(resp),
	.rdata(rdata),
	.error()
);



endmodule