data/full_repos/permissive/186528222/seven.v
1: b'%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:123: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'first\' generates 4 bits.\n                                                                : ... In instance seven\n     sseg = first;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:129: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'second\' generates 4 bits.\n                                                                : ... In instance seven\n     sseg = second;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:135: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'third\' generates 4 bits.\n                                                                : ... In instance seven\n     sseg = third; \n          ^\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:141: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'fourth\' generates 4 bits.\n                                                                : ... In instance seven\n     sseg = fourth; \n          ^\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:151: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                : ... In instance seven\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:151: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                : ... In instance seven\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:151: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n                                                                : ... In instance seven\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:151: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n                                                                : ... In instance seven\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:151: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                : ... In instance seven\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:151: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h5\' generates 4 bits.\n                                                                : ... In instance seven\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:151: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h6\' generates 4 bits.\n                                                                : ... In instance seven\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:151: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h7\' generates 4 bits.\n                                                                : ... In instance seven\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:151: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                : ... In instance seven\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/186528222/seven.v:151: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                : ... In instance seven\n  case(sseg)\n  ^~~~\n%Error: Exiting due to 14 warning(s)\n'
module seven(
    input clk,
    input rst,
    output reg rclk,
	 output a,
    output b,
    output c,
    output d,
    output e,
    output f,
    output g,
    output dp,
    output [3:0]an
    );

reg [3:0]first;
reg [3:0]second;
reg [3:0]third;
reg [3:0]fourth;

reg [26:0]count;
reg [6:0]min;
reg [6:0]sec;

always@(posedge clk)
begin
if(rst)
begin
count = 0;
rclk = 1'b1;
sec = 0;
min = 0;
end
count = count+1;
if(count == 50000000)
begin
rclk = !rclk;
sec = sec+1 ;
if(sec == 60)
begin
min = min+1;
sec = 0;
end
if(min == 60)
begin
min = 0;
end
count = 0;
end
end


always@(posedge rclk)
begin

if(rst)
begin
first <= 0;
second <= 0;
third <= 0;
fourth <= 0;
end

else if (first==4'd9) 
begin
first <= 0;
if (second == 4'd5)
begin
second <= 0;
third <= third + 1;
if (third == 4'd9)
begin
third <= 0;
fourth <= fourth + 1;
end
end
else
second <= second + 1;  
end
else
first <= first + 1;
end

localparam N = 18;
reg [N-1:0]co;

always @ (posedge clk)
begin
if (rst)
co <= 0;
else
co <= co + 1;
end

reg [6:0]sseg;
reg [3:0]an_temp;
always @ (*)
 begin
  case(count[N-1:N-2])
   
   2'b00 : 
    begin
     sseg = first;
     an_temp = 4'b1110;
    end
   
   2'b01:
    begin
     sseg = second;
     an_temp = 4'b1101;
    end
   
   2'b10:
    begin
     sseg = third; 
     an_temp = 4'b1011;
    end
    
   2'b11:
    begin
     sseg = fourth; 
     an_temp = 4'b0111;
    end
  endcase
 end
assign an = an_temp;

reg [6:0] sseg_temp; 
always @ (*)
 begin
  case(sseg)
   4'd0 : sseg_temp = 7'b1000000;
   4'd1 : sseg_temp = 7'b1111001;
   4'd2 : sseg_temp = 7'b0100100;
   4'd3 : sseg_temp = 7'b0110000;
   4'd4 : sseg_temp = 7'b0011001;
   4'd5 : sseg_temp = 7'b0010010;
   4'd6 : sseg_temp = 7'b0000010;
   4'd7 : sseg_temp = 7'b1111000;
   4'd8 : sseg_temp = 7'b0000000;
   4'd9 : sseg_temp = 7'b0010000;
   default : sseg_temp = 7'b0111111;
  endcase
 end
assign {g, f, e, d, c, b, a} = sseg_temp; 
assign dp = 1'b1;

endmodule
module seven(
    input clk,
    input rst,
    output reg rclk,
	 output a,
    output b,
    output c,
    output d,
    output e,
    output f,
    output g,
    output dp,
    output [3:0]an
    );


reg [3:0]first;
reg [3:0]second;
reg [3:0]third;
reg [3:0]fourth;

reg [26:0]count;
reg [6:0]min;
reg [6:0]sec;

always@(posedge clk)
begin
if(rst)
begin
count = 0;
rclk = 1'b1;
sec = 0;
min = 0;
end
count = count+1;
if(count == 50000000)
begin
rclk = !rclk;
sec = sec+1 ;
if(sec == 60)
begin
min = min+1;
sec = 0;
end
if(min == 60)
begin
min = 0;
end
count = 0;
end
end


always@(posedge rclk)
begin

if(rst)
begin
first <= 0;
second <= 0;
third <= 0;
fourth <= 0;
end

else if (first==4'd9) 
begin
first <= 0;
if (second == 4'd5)
begin
second <= 0;
third <= third + 1;
if (third == 4'd9)
begin
third <= 0;
fourth <= fourth + 1;
end
end
else
second <= second + 1;  
end
else
first <= first + 1;
end

localparam N = 18;
reg [N-1:0]co;

always @ (posedge clk)
begin
if (rst)
co <= 0;
else
co <= co + 1;
end

reg [6:0]sseg;
reg [3:0]an_temp;
always @ (*)
 begin
  case(count[N-1:N-2])
   
   2'b00 : 
    begin
     sseg = first;
     an_temp = 4'b1110;
    end
   
   2'b01:
    begin
     sseg = second;
     an_temp = 4'b1101;
    end
   
   2'b10:
    begin
     sseg = third; 
     an_temp = 4'b1011;
    end
    
   2'b11:
    begin
     sseg = fourth; 
     an_temp = 4'b0111;
    end
  endcase
 end
assign an = an_temp;

reg [6:0] sseg_temp; 
always @ (*)
 begin
  case(sseg)
   4'd0 : sseg_temp = 7'b1000000;
   4'd1 : sseg_temp = 7'b1111001;
   4'd2 : sseg_temp = 7'b0100100;
   4'd3 : sseg_temp = 7'b0110000;
   4'd4 : sseg_temp = 7'b0011001;
   4'd5 : sseg_temp = 7'b0010010;
   4'd6 : sseg_temp = 7'b0000010;
   4'd7 : sseg_temp = 7'b1111000;
   4'd8 : sseg_temp = 7'b0000000;
   4'd9 : sseg_temp = 7'b0010000;
   default : sseg_temp = 7'b0111111;
  endcase
 end
assign {g, f, e, d, c, b, a} = sseg_temp; 
assign dp = 1'b1;

endmodule