data/full_repos/permissive/186491764/Data_Memory.v
data/verilator_xmls/7c14a8d2-8678-41dc-a856-e7db6453653d.xml
module Data_Memory(
 input clk,
 input [7:0]   rom_address,
 input [7:0]   rom_write_data,
 input rom_write,
 input rom_read,
 output [7:0]  rom_data
    );
	 
 reg [7:0] memory [7:0];
wire [2:0] location=rom_address[2:0];

initial
 begin
 memory [0] = 8'b00001010;
 memory [1] = 8'b11111111;
 memory [2] = 8'b00000001;
 memory [3] = 8'b00000001;
 memory [4] = 8'b00000000;
 memory [5] = 8'b00000000;
 memory [6] = 8'b00000000;
 memory [7] = 8'b00000000;
 end
 
 always @(posedge clk) begin
  if (rom_write)
   memory[location] <= rom_write_data;
 end
 assign rom_data = (rom_read==1'b1) ? memory[location]: 8'd0; 

endmodule
module Data_Memory(
 input clk,
 input [7:0]   rom_address,
 input [7:0]   rom_write_data,
 input rom_write,
 input rom_read,
 output [7:0]  rom_data
    );

	 
 reg [7:0] memory [7:0];
wire [2:0] location=rom_address[2:0];

initial
 begin
 memory [0] = 8'b00001010;
 memory [1] = 8'b11111111;
 memory [2] = 8'b00000001;
 memory [3] = 8'b00000001;
 memory [4] = 8'b00000000;
 memory [5] = 8'b00000000;
 memory [6] = 8'b00000000;
 memory [7] = 8'b00000000;
 end
 
 always @(posedge clk) begin
  if (rom_write)
   memory[location] <= rom_write_data;
 end
 assign rom_data = (rom_read==1'b1) ? memory[location]: 8'd0; 

endmodule