data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #FINISH_TIME;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n        wa = 3\'d1; wd = 8\'b00000001; #WAIT;\n                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b0; #WAIT;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n        wa = 3\'d2; wd = 8\'b00000010; #WAIT;\n                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n        ra1 = 3\'d1; ra2 = 3\'d2; #WAIT;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n        a = ra1; b = ra2; #WAIT;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n        funct = 6\'b100000; #WAIT;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n        wa = 3\'d3; wd = result; #WAIT;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n        funct = 6\'b100010; #WAIT;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n        wa = 3\'d4; wd = result; #WAIT;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n        funct = 6\'b100100; #WAIT;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n        wa = 3\'d5; wd = result; #WAIT;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n        funct = 6\'b100101; #WAIT;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n        wa = 3\'d6; wd = result; #WAIT;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n        funct = 6\'b101010; #WAIT;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n        wa = 3\'d7; wd = result; #WAIT;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n        regwrite = 1\'b1; #WAIT; regwrite = 1\'b0; #WAIT;\n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n            #WAIT;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n        #PERIOD;\n        ^\n%Error: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:191: Unsupported or unknown PLI call: $shm_open\n        $shm_open("alu_tb.db");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:192: Unsupported or unknown PLI call: $shm_probe\n        $shm_probe(alu_tb, "AS");\n        ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174242803/alu_regf/src/alu_tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n        forever #1 clk = ~clk;\n                ^\n%Error: Exiting due to 2 error(s), 33 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb();

    parameter FINISH_TIME = 1000;
    parameter PERIOD      = 20;
    parameter WAIT        = 5;



    reg [7:0] a;
    reg [7:0] b;
    

    reg [1:0] aluop;
    reg [5:0] funct;
    

    reg clk;
    reg regwrite;
    reg [2:0] ra1;
    reg [2:0] ra2;
    reg [2:0] wa;
    reg [7:0] wd;



    wire [7:0] result;
    

    wire [7:0] rd1;
    wire [7:0] rd2;
    

    wire [2:0] alucont;
    
    integer i = 0;


    alu test_alu(.result(result),
                 .a(a),
                 .b(b),
                 .alucont(alucont)
                );
                
    alucontrol test_control(.alucont(alucont),
                            .aluop(aluop),
                            .funct(funct)
                           );
                           
    regfile test_reg(.rd1(rd1),
                     .rd2(rd2),
                     .clk(clk),
                     .regwrite(regwrite),
                     .ra1(ra1),
                     .ra2(ra2),
                     .wa(wa),
                     .wd(wd)
                    );


    initial begin

        a = 8'd0;
        b = 8'd0;
        

        aluop = 2'd0;
        funct = 6'd0;
        

        clk = 1'b0;
        regwrite = 1'b0;
        ra1 = 3'd0;
        ra2 = 3'd0;
        wa = 3'd0;
        wd = 8'd0;

        #FINISH_TIME;
        $display("Finishing simulation due to similation constraint.");
        $display("Time is - %d", $time);
        $finish;
    end


    initial begin

        #PERIOD;
        wa = 3'd1; wd = 8'b00000001; #WAIT;
        regwrite = 1'b1; #WAIT;
        regwrite = 1'b0; #WAIT;
        
        wa = 3'd2; wd = 8'b00000010; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        aluop = 2'b11;

        ra1 = 3'd1; ra2 = 3'd2; #WAIT;
        a = ra1; b = ra2; #WAIT;
        


        funct = 6'b100000; #WAIT;

        wa = 3'd3; wd = result; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        funct = 6'b100010; #WAIT;
        
        wa = 3'd4; wd = result; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        funct = 6'b100100; #WAIT;
        
        wa = 3'd5; wd = result; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        funct = 6'b100101; #WAIT;
        
        wa = 3'd6; wd = result; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        funct = 6'b101010; #WAIT;
        
        wa = 3'd7; wd = result; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        
        
        for (i = 0; i < 8; i = i + 2) begin
            ra1 = i;
            ra2 = i + 1;
            
            #WAIT;
            
            $display("$s%d = %d", ra1, rd1);
            $display("$s%d = %d", ra2, rd2);
            
            case (i)
                0:  begin
                        if (0 == rd1 & 1 == rd2)
                            $display("$s%d and $s%d are correct.", ra1, ra2);
                        else begin
                            $display("$s%d and $s%d are incorrect. Finishing.", ra1, ra2);
                            $finish;
                        end
                    end
                2:  begin
                        if (2 == rd1 & 3 == rd2)
                            $display("$s%d and $s%d are correct.", ra1, ra2);
                        else begin
                            $display("$s%d and $s%d are incorrect. Finishing.", ra1, ra2);
                            $finish;
                        end
                    end
                4:  begin
                        if (255 == rd1 & 0 == rd2)
                            $display("$s%d and $s%d are correct.", ra1, ra2);
                        else begin
                            $display("$s%d and $s%d are incorrect. Finishing.", ra1, ra2);
                            $finish;
                        end
                    end
                6:  begin
                        if (3 == rd1 & 1 == rd2)
                            $display("$s%d and $s%d are correct.", ra1, ra2);
                        else begin
                            $display("$s%d and $s%d are incorrect. Finishing.", ra1, ra2);
                            $finish;
                        end
                    end
            endcase
            
            
        end
        
        #PERIOD;
        $display("Finishing simulation due to end of testbench.");
        $display("Time is - %d", $time);
        $finish;
    end


    initial begin
        $shm_open("alu_tb.db");
        $shm_probe(alu_tb, "AS");
    end
    
    initial begin
        forever #1 clk = ~clk;
    end

endmodule
module alu_tb();


    parameter FINISH_TIME = 1000;
    parameter PERIOD      = 20;
    parameter WAIT        = 5;



    reg [7:0] a;
    reg [7:0] b;
    

    reg [1:0] aluop;
    reg [5:0] funct;
    

    reg clk;
    reg regwrite;
    reg [2:0] ra1;
    reg [2:0] ra2;
    reg [2:0] wa;
    reg [7:0] wd;



    wire [7:0] result;
    

    wire [7:0] rd1;
    wire [7:0] rd2;
    

    wire [2:0] alucont;
    
    integer i = 0;


    alu test_alu(.result(result),
                 .a(a),
                 .b(b),
                 .alucont(alucont)
                );
                
    alucontrol test_control(.alucont(alucont),
                            .aluop(aluop),
                            .funct(funct)
                           );
                           
    regfile test_reg(.rd1(rd1),
                     .rd2(rd2),
                     .clk(clk),
                     .regwrite(regwrite),
                     .ra1(ra1),
                     .ra2(ra2),
                     .wa(wa),
                     .wd(wd)
                    );


    initial begin

        a = 8'd0;
        b = 8'd0;
        

        aluop = 2'd0;
        funct = 6'd0;
        

        clk = 1'b0;
        regwrite = 1'b0;
        ra1 = 3'd0;
        ra2 = 3'd0;
        wa = 3'd0;
        wd = 8'd0;

        #FINISH_TIME;
        $display("Finishing simulation due to similation constraint.");
        $display("Time is - %d", $time);
        $finish;
    end


    initial begin

        #PERIOD;
        wa = 3'd1; wd = 8'b00000001; #WAIT;
        regwrite = 1'b1; #WAIT;
        regwrite = 1'b0; #WAIT;
        
        wa = 3'd2; wd = 8'b00000010; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        aluop = 2'b11;

        ra1 = 3'd1; ra2 = 3'd2; #WAIT;
        a = ra1; b = ra2; #WAIT;
        


        funct = 6'b100000; #WAIT;

        wa = 3'd3; wd = result; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        funct = 6'b100010; #WAIT;
        
        wa = 3'd4; wd = result; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        funct = 6'b100100; #WAIT;
        
        wa = 3'd5; wd = result; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        funct = 6'b100101; #WAIT;
        
        wa = 3'd6; wd = result; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        funct = 6'b101010; #WAIT;
        
        wa = 3'd7; wd = result; #WAIT;
        regwrite = 1'b1; #WAIT; regwrite = 1'b0; #WAIT;
        

        
        
        for (i = 0; i < 8; i = i + 2) begin
            ra1 = i;
            ra2 = i + 1;
            
            #WAIT;
            
            $display("$s%d = %d", ra1, rd1);
            $display("$s%d = %d", ra2, rd2);
            
            case (i)
                0:  begin
                        if (0 == rd1 & 1 == rd2)
                            $display("$s%d and $s%d are correct.", ra1, ra2);
                        else begin
                            $display("$s%d and $s%d are incorrect. Finishing.", ra1, ra2);
                            $finish;
                        end
                    end
                2:  begin
                        if (2 == rd1 & 3 == rd2)
                            $display("$s%d and $s%d are correct.", ra1, ra2);
                        else begin
                            $display("$s%d and $s%d are incorrect. Finishing.", ra1, ra2);
                            $finish;
                        end
                    end
                4:  begin
                        if (255 == rd1 & 0 == rd2)
                            $display("$s%d and $s%d are correct.", ra1, ra2);
                        else begin
                            $display("$s%d and $s%d are incorrect. Finishing.", ra1, ra2);
                            $finish;
                        end
                    end
                6:  begin
                        if (3 == rd1 & 1 == rd2)
                            $display("$s%d and $s%d are correct.", ra1, ra2);
                        else begin
                            $display("$s%d and $s%d are incorrect. Finishing.", ra1, ra2);
                            $finish;
                        end
                    end
            endcase
            
            
        end
        
        #PERIOD;
        $display("Finishing simulation due to end of testbench.");
        $display("Time is - %d", $time);
        $finish;
    end


    initial begin
        $shm_open("alu_tb.db");
        $shm_probe(alu_tb, "AS");
    end
    
    initial begin
        forever #1 clk = ~clk;
    end

endmodule