data/full_repos/permissive/136510272/projects/x8086/mem_cntrl.v
data/verilator_xmls/fe48d4a0-1252-4112-9739-db826e0f34dd.xml
module mem_cntrl(

    input   wire        clk,
    input   wire [19:0] i_addr,
    output  wire [7:0]  o_data,
    input   wire [7:0]  i_data,
    input   wire        i_write,


    input   wire [7:0]  i_mem_data,
    output  reg  [7:0]  o_mem_data,
    output  reg         o_mem_write,
    output  reg  [19:0] o_mem_addr

);

assign o_mem_addr  = i_addr;
assign o_data      = i_mem_data;
assign o_mem_data  = i_data;
assign o_mem_write = i_write;

always @(posedge clk) begin

    

end

endmodule
module mem_cntrl(

    input   wire        clk,
    input   wire [19:0] i_addr,
    output  wire [7:0]  o_data,
    input   wire [7:0]  i_data,
    input   wire        i_write,


    input   wire [7:0]  i_mem_data,
    output  reg  [7:0]  o_mem_data,
    output  reg         o_mem_write,
    output  reg  [19:0] o_mem_addr

);


assign o_mem_addr  = i_addr;
assign o_data      = i_mem_data;
assign o_mem_data  = i_data;
assign o_mem_write = i_write;

always @(posedge clk) begin

    

end

endmodule