data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_operation.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_operation.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #delay ab_and = a & b;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_operation.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #50 A = 16\'b10101010_01010101;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_operation.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #50 B = 16\'b00001111_00111100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_operation.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #50 A = 16\'b11001100_11001100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_operation.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #50 $finish;\n    ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module task_operation;

parameter delay = 10;
reg [15:0] A,B;
reg [15:0] AB_AND, AB_OR, AB_XOR;

always @(A or B)
begin



    bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B);
end


task bitwise_oper(output [15:0] ab_and, ab_or, ab_xor,
                  input [15:0] a, b);

begin
    #delay ab_and = a & b;
    ab_or = a| b;
    ab_xor = a ^ b;
end
endtask


initial
begin
    #50 A = 16'b10101010_01010101;
    #50 B = 16'b00001111_00111100;
    #50 A = 16'b11001100_11001100;
    #50 $finish;
end

endmodule
module task_operation;


parameter delay = 10;
reg [15:0] A,B;
reg [15:0] AB_AND, AB_OR, AB_XOR;

always @(A or B)
begin



    bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B);
end


task bitwise_oper(output [15:0] ab_and, ab_or, ab_xor,
                  input [15:0] a, b);

begin
    #delay ab_and = a & b;
    ab_or = a| b;
    ab_xor = a ^ b;
end
endtask


initial
begin
    #50 A = 16'b10101010_01010101;
    #50 B = 16'b00001111_00111100;
    #50 A = 16'b11001100_11001100;
    #50 $finish;
end

endmodule