data/full_repos/permissive/10379745/hard/muldiv.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/10379745/hard/muldiv.sv:70: Cannot find include file: hard/log2.inc\n`include "hard/log2.inc" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc\n             data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc.v\n             data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc.sv\n             hard/log2.inc\n             hard/log2.inc.v\n             hard/log2.inc.sv\n             obj_dir/hard/log2.inc\n             obj_dir/hard/log2.inc.v\n             obj_dir/hard/log2.inc.sv\n%Error: Exiting due to 1 error(s)\n'
module muldiv  ( input                CLK,
                 input                RESET,
                 input                EN,
                 input          [2:0] OP,
                 input  signed [31:0] A,
                 input  signed [31:0] B,
                 output        [31:0] HI,
                 output        [31:0] LO,
                 output               BUSY );

logic               busy_mul, busy_div, div_wr;
logic         [2:0] op_q;
logic signed [63:0] mt_hilo, hilo, hilo_q;
logic signed [63:0] s_mult, s_mult_q, s_mad_q;
logic        [31:0] quot, rem, a_q;

assign s_mult  = A*B;
assign s_mad_q = s_mult_q + hilo_q;

ffd #(  3)    op_reg(CLK, RESET, EN, OP, op_q);

ffd #( 32) mt_reg   ( CLK, RESET, EN,   A,                       a_q      );
ffd #( 64) mul_reg  ( CLK, RESET, EN,   s_mult,                  s_mult_q );
ffd #(  1) busym_reg( CLK, RESET, 1'b1, EN & (OP[1:0] != 2'b11), busy_mul );


assign mt_hilo = op_q[2] ? {a_q, hilo_q[31:0]} : {hilo_q[63:32], a_q};

mc_div #(32) mc_div ( .CLK      ( CLK                    ),
                      .RESET    ( RESET                  ),
                      .GO       ( EN & (OP[1:0] == 2'b11)),
                      .BUSY     ( busy_div               ),
                      .W_RESULT ( div_wr                 ),
                      .A        ( A                      ),
                      .B        ( B                      ),
                      .QUOT     ( quot                   ),
                      .REM      ( rem                    ) );

mux4 #(64) hilo_wr_mux ( .S  ( op_q[1:0]   ),
                         .D0 ( s_mult_q    ),
                         .D1 ( s_mad_q     ),
                         .D2 ( mt_hilo     ),
                         .D3 ( {rem, quot} ),
                         .Y  ( hilo        ) );

ffd #( 64) hi_lo_reg(CLK, RESET, busy_mul | div_wr, hilo, hilo_q);


assign HI = hilo_q[63:32];
assign LO = hilo_q[31:0];
assign BUSY = busy_mul | busy_div;

endmodule
module muldiv  ( input                CLK,
                 input                RESET,
                 input                EN,
                 input          [2:0] OP,
                 input  signed [31:0] A,
                 input  signed [31:0] B,
                 output        [31:0] HI,
                 output        [31:0] LO,
                 output               BUSY );


logic               busy_mul, busy_div, div_wr;
logic         [2:0] op_q;
logic signed [63:0] mt_hilo, hilo, hilo_q;
logic signed [63:0] s_mult, s_mult_q, s_mad_q;
logic        [31:0] quot, rem, a_q;

assign s_mult  = A*B;
assign s_mad_q = s_mult_q + hilo_q;

ffd #(  3)    op_reg(CLK, RESET, EN, OP, op_q);

ffd #( 32) mt_reg   ( CLK, RESET, EN,   A,                       a_q      );
ffd #( 64) mul_reg  ( CLK, RESET, EN,   s_mult,                  s_mult_q );
ffd #(  1) busym_reg( CLK, RESET, 1'b1, EN & (OP[1:0] != 2'b11), busy_mul );


assign mt_hilo = op_q[2] ? {a_q, hilo_q[31:0]} : {hilo_q[63:32], a_q};

mc_div #(32) mc_div ( .CLK      ( CLK                    ),
                      .RESET    ( RESET                  ),
                      .GO       ( EN & (OP[1:0] == 2'b11)),
                      .BUSY     ( busy_div               ),
                      .W_RESULT ( div_wr                 ),
                      .A        ( A                      ),
                      .B        ( B                      ),
                      .QUOT     ( quot                   ),
                      .REM      ( rem                    ) );

mux4 #(64) hilo_wr_mux ( .S  ( op_q[1:0]   ),
                         .D0 ( s_mult_q    ),
                         .D1 ( s_mad_q     ),
                         .D2 ( mt_hilo     ),
                         .D3 ( {rem, quot} ),
                         .Y  ( hilo        ) );

ffd #( 64) hi_lo_reg(CLK, RESET, busy_mul | div_wr, hilo, hilo_q);


assign HI = hilo_q[63:32];
assign LO = hilo_q[31:0];
assign BUSY = busy_mul | busy_div;

endmodule