data/full_repos/permissive/172912857/project_vga/vga1280x1024.v
data/verilator_xmls/2778807d-aa1c-414f-8c2f-e15471d43415.xml
module vga1280x1024(
	input wire dclk,
	input wire clr,
	output wire hsync,
	output wire vsync,
	output reg [3:0] red,
	output reg [3:0] green,
	output reg [3:0] blue
	);














parameter hpixels = 1688;
parameter vlines = 1066;
parameter hpulse = 112;
parameter vpulse = 3;
parameter hbp = 360;
parameter hfp = 1640;
parameter vbp = 35;
parameter vfp = 1059;



reg [10:0] hc;
reg [10:0] vc;

always @(posedge dclk or posedge clr)
begin
	if (clr == 1)
	begin
		hc <= 0;
		vc <= 0;
	end
	else
	begin
		if (hc < hpixels - 1)
			hc <= hc + 1;
		else
		begin
			hc <= 0;
			if (vc < vlines - 1)
				vc <= vc + 1;
			else
				vc <= 0;
		end
		
	end
end


assign hsync = (hc < hpulse) ? 0:1;
assign vsync = (vc < vpulse) ? 0:1;

always @(*)
begin

	if (vc >= vbp && vc < vfp)
	begin

		if (hc >= hbp && hc < (hbp+160))
		begin
			red = 4'b1111;
			green = 4'b1111;
			blue = 4'b1111;
		end

		else if (hc >= (hbp+160) && hc < (hbp+320))
		begin
			red = 4'b1111;
			green = 4'b1111;
			blue = 4'b0000;
		end

		else if (hc >= (hbp+320) && hc < (hbp+480))
		begin
			red = 4'b0000;
			green = 4'b1111;
			blue = 4'b1111;
		end

		else if (hc >= (hbp+480) && hc < (hbp+640))
		begin
			red = 4'b0000;
			green = 4'b1111;
			blue = 4'b0000;
		end

		else if (hc >= (hbp+640) && hc < (hbp+800))
		begin
			red = 4'b1111;
			green = 4'b0000;
			blue = 4'b1111;
		end

		else if (hc >= (hbp+800) && hc < (hbp+960))
		begin
			red = 4'b1111;
			green = 4'b0000;
			blue = 4'b0000;
		end

		else if (hc >= (hbp+960) && hc < (hbp+1120))
		begin
			red = 4'b0000;
			green = 4'b0000;
			blue = 4'b1111;
		end

		else if (hc >= (hbp+1120) && hc < (hbp+1280))
		begin
			red = 4'b0000;
			green = 4'b0000;
			blue = 4'b0000;
		end

		else
		begin
			red = 0;
			green = 0;
			blue = 0;
		end
	end

	else
	begin
		red = 0;
		green = 0;
		blue = 0;
	end
end

endmodule
module vga1280x1024(
	input wire dclk,
	input wire clr,
	output wire hsync,
	output wire vsync,
	output reg [3:0] red,
	output reg [3:0] green,
	output reg [3:0] blue
	);















parameter hpixels = 1688;
parameter vlines = 1066;
parameter hpulse = 112;
parameter vpulse = 3;
parameter hbp = 360;
parameter hfp = 1640;
parameter vbp = 35;
parameter vfp = 1059;



reg [10:0] hc;
reg [10:0] vc;

always @(posedge dclk or posedge clr)
begin
	if (clr == 1)
	begin
		hc <= 0;
		vc <= 0;
	end
	else
	begin
		if (hc < hpixels - 1)
			hc <= hc + 1;
		else
		begin
			hc <= 0;
			if (vc < vlines - 1)
				vc <= vc + 1;
			else
				vc <= 0;
		end
		
	end
end


assign hsync = (hc < hpulse) ? 0:1;
assign vsync = (vc < vpulse) ? 0:1;

always @(*)
begin

	if (vc >= vbp && vc < vfp)
	begin

		if (hc >= hbp && hc < (hbp+160))
		begin
			red = 4'b1111;
			green = 4'b1111;
			blue = 4'b1111;
		end

		else if (hc >= (hbp+160) && hc < (hbp+320))
		begin
			red = 4'b1111;
			green = 4'b1111;
			blue = 4'b0000;
		end

		else if (hc >= (hbp+320) && hc < (hbp+480))
		begin
			red = 4'b0000;
			green = 4'b1111;
			blue = 4'b1111;
		end

		else if (hc >= (hbp+480) && hc < (hbp+640))
		begin
			red = 4'b0000;
			green = 4'b1111;
			blue = 4'b0000;
		end

		else if (hc >= (hbp+640) && hc < (hbp+800))
		begin
			red = 4'b1111;
			green = 4'b0000;
			blue = 4'b1111;
		end

		else if (hc >= (hbp+800) && hc < (hbp+960))
		begin
			red = 4'b1111;
			green = 4'b0000;
			blue = 4'b0000;
		end

		else if (hc >= (hbp+960) && hc < (hbp+1120))
		begin
			red = 4'b0000;
			green = 4'b0000;
			blue = 4'b1111;
		end

		else if (hc >= (hbp+1120) && hc < (hbp+1280))
		begin
			red = 4'b0000;
			green = 4'b0000;
			blue = 4'b0000;
		end

		else
		begin
			red = 0;
			green = 0;
			blue = 0;
		end
	end

	else
	begin
		red = 0;
		green = 0;
		blue = 0;
	end
end

endmodule