data/full_repos/permissive/203526788/GoBoard/SPI_master/top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/top.v:3: Cannot find include file: Display.v\n`include "Display.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203526788/GoBoard/SPI_master,data/full_repos/permissive/203526788/Display.v\n             data/full_repos/permissive/203526788/GoBoard/SPI_master,data/full_repos/permissive/203526788/Display.v.v\n             data/full_repos/permissive/203526788/GoBoard/SPI_master,data/full_repos/permissive/203526788/Display.v.sv\n             Display.v\n             Display.v.v\n             Display.v.sv\n             obj_dir/Display.v\n             obj_dir/Display.v.v\n             obj_dir/Display.v.sv\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/top.v:4: Cannot find include file: SPI_Master.v\n`include "SPI_Master.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/top.v:5: Cannot find include file: Once.v\n`include "Once.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/top.v:6: Cannot find include file: Debounce_Single_Input.v\n`include "Debounce_Single_Input.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/top.v:26: syntax error, unexpected \')\', expecting \'[\'\n);\n^\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/top.v:33: syntax error, unexpected IDENTIFIER\n  DisplayNumber ns (CLK, SEG1, SEG2, out);\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/top.v:36: syntax error, unexpected IDENTIFIER\n  Debounce_Single_Input db (CLK, SW1, sw1);\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/top.v:39: syntax error, unexpected IDENTIFIER\n  Once once (CLK, sw1, enableOnce);\n  ^~~~\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/top.v:48: syntax error, unexpected IDENTIFIER\n  SPI_Master #(.SPI_MODE(SPI_MODE),\n  ^~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module top(
  	  input CLK,
	    output [6:0] SEG1,
	    output [6:0] SEG2,
	    output [3:0] LED,
      output SCK,
      input MISO,
      output MOSI,
      output CS,
      input SW1,
      input SW2,
);


  parameter SPI_MODE = 0;
  parameter CLKS_PER_HALF_BIT = 8;
  

  DisplayNumber ns (CLK, SEG1, SEG2, out);

  reg sw1;
  Debounce_Single_Input db (CLK, SW1, sw1);

  reg enableOnce;
  Once once (CLK, sw1, enableOnce);



  wire [7:0] in;
  reg [7:0] out = 8'd97;
  wire txready;
  wire rxready;

  SPI_Master #(.SPI_MODE(SPI_MODE),
    .CLKS_PER_HALF_BIT(CLKS_PER_HALF_BIT)) mater
  (

   .i_Rst_L(1'b1),
   .i_Clk(CLK),
   

   .i_TX_Byte(out),
   .i_TX_DV(enableOnce),
   .o_TX_Ready(txready),
   

   .o_RX_DV(rxready),
   .o_RX_Byte(in),


   .o_SPI_Clk(SCK),
   .i_SPI_MISO(MISO),
   .o_SPI_MOSI(MOSI)
   );


	always @(posedge CLK)
	begin    
    if (enableOnce) out <= out + 1;

    if (SW2) out <= 8'd97;
	end

  



endmodule
module top(
  	  input CLK,
	    output [6:0] SEG1,
	    output [6:0] SEG2,
	    output [3:0] LED,
      output SCK,
      input MISO,
      output MOSI,
      output CS,
      input SW1,
      input SW2,
);



  parameter SPI_MODE = 0;
  parameter CLKS_PER_HALF_BIT = 8;
  

  DisplayNumber ns (CLK, SEG1, SEG2, out);

  reg sw1;
  Debounce_Single_Input db (CLK, SW1, sw1);

  reg enableOnce;
  Once once (CLK, sw1, enableOnce);



  wire [7:0] in;
  reg [7:0] out = 8'd97;
  wire txready;
  wire rxready;

  SPI_Master #(.SPI_MODE(SPI_MODE),
    .CLKS_PER_HALF_BIT(CLKS_PER_HALF_BIT)) mater
  (

   .i_Rst_L(1'b1),
   .i_Clk(CLK),
   

   .i_TX_Byte(out),
   .i_TX_DV(enableOnce),
   .o_TX_Ready(txready),
   

   .o_RX_DV(rxready),
   .o_RX_Byte(in),


   .o_SPI_Clk(SCK),
   .i_SPI_MISO(MISO),
   .o_SPI_MOSI(MOSI)
   );


	always @(posedge CLK)
	begin    
    if (enableOnce) out <= out + 1;

    if (SW2) out <= 8'd97;
	end

  



endmodule