data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/IMemModule.v
1: b"%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/IMemModule.v:30: Cannot find file containing module: 'IMem'\nIMem u_IMem(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/IMem\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/IMem.v\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips,data/full_repos/permissive/115487336/IMem.sv\n             IMem\n             IMem.v\n             IMem.sv\n             obj_dir/IMem\n             obj_dir/IMem.v\n             obj_dir/IMem.sv\n%Error: Exiting due to 1 error(s)\n"
module IMemModule(
	input clk,
	input rst_n,
	input [31:0] addr,

	output reg [31:0] pc,
	output [31:0] ir
);

IMem u_IMem(
	clk,
	addr[8:2],
	ir
);

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
		pc<=32'h0;
	else
		pc<=addr;
end

endmodule
module IMemModule(
	input clk,
	input rst_n,
	input [31:0] addr,

	output reg [31:0] pc,
	output [31:0] ir
);


IMem u_IMem(
	clk,
	addr[8:2],
	ir
);

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
		pc<=32'h0;
	else
		pc<=addr;
end

endmodule