data/full_repos/permissive/132220215/mux.v
1: b"%Error: data/full_repos/permissive/132220215/mux.v:6: Duplicate declaration of signal: 'f'\n                                                    : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg f;\n    ^\n        data/full_repos/permissive/132220215/mux.v:5: ... Location of original declaration\n output f);\n        ^\n%Error: Exiting due to 1 error(s)\n"
module mux2to1 (
	input in0,in1,sel0,
	output f);
reg f;
 always @(*)
 begin
	 if(sel0)
		 f = in1;
	 else
		 f = in0;
 end
endmodule
module mux2to1 (
	input in0,in1,sel0,
	output f);

reg f;
 always @(*)
 begin
	 if(sel0)
		 f = in1;
	 else
		 f = in0;
 end
endmodule