data/full_repos/permissive/197356760/SequentialMultiplier/Parametrized_register.v
data/verilator_xmls/52626f72-263c-4ee6-bf86-213c84f4a219.xml
module register #(parameter n = 8)
						(input clk, rst, enable,
						input [n-1:0] reg_in,
						output reg [n-1:0] reg_out);
					
	always @(posedge clk) begin
		if (rst)
			reg_out <= 0;
		else if (enable)
			reg_out <= reg_in;	
	end
		
endmodule
module register #(parameter n = 8)
						(input clk, rst, enable,
						input [n-1:0] reg_in,
						output reg [n-1:0] reg_out);

					
	always @(posedge clk) begin
		if (rst)
			reg_out <= 0;
		else if (enable)
			reg_out <= reg_in;	
	end
		
endmodule