data/full_repos/permissive/170013753/src/ctrlunit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170013753/src/ctrlunit.v:28: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                      : ... In instance ctrlunit\n    aluOp = 2\'b00;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ctrlunit(
  input clk,
  input rst,
  input [3:0] opcode,

  output reg [2:0] aluOp,
  output reg [1:0] memToReg,
  output reg [1:0] aluSrcA,
  output reg [1:0] aluSrcB,
  output reg jump,
  output reg branch,
  output reg memRead,
  output reg memWrite,
  output reg regWrite,
  output reg signExt
);

always @(*) begin

  if(rst == 1'b1) begin
    aluOp = 2'b00;
    memToReg = 2'b0;
    aluSrcA = 2'b0;
    aluSrcB = 2'b0;
    branch = 1'b0;
    jump = 1'b0;
    memRead = 1'b0;
    memWrite = 1'b0;
    regWrite = 1'b0;
    signExt  = 1'b0;
  end
  else begin
    case(opcode)


      4'b0000: begin
        aluOp = 3'b000;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0001: begin
        aluOp = 3'b001;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0010: begin
        aluOp = 3'b010;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0011: begin
        aluOp = 3'b011;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0100: begin
        aluOp = 3'b100;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0101: begin
        aluOp = 3'b101;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0110: begin
        aluOp = 3'b110;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0111: begin
        aluOp = 3'b111;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b1000: begin
        aluOp = 3'b000;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b01;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b1001: begin
        aluOp = 3'b000;
        memToReg = 2'b00;
        aluSrcA = 2'b10;
        aluSrcB = 2'b10;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b1010: begin
        aluOp = 3'b000;
        memToReg = 2'b01;
        aluSrcA = 2'b00;
        aluSrcB = 2'b11;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b1;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b1011: begin
        aluOp = 3'b000;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b11;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b1;
        regWrite = 1'b0;
        signExt  = 1'b0;
      end


      4'b1100: begin
        aluOp = 3'b000;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b11;
        branch = 1'b1;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b0;
        signExt  = 1'b0;
      end


      4'b1101: begin
        aluOp = 3'b000;
        memToReg = 2'b10;
        aluSrcA = 2'b11;
        aluSrcB = 2'b11;
        branch = 1'b0;
        jump = 1'b1;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b1110: begin

      end


      4'b1111: begin

      end
    endcase
  end
end

endmodule
module ctrlunit(
  input clk,
  input rst,
  input [3:0] opcode,

  output reg [2:0] aluOp,
  output reg [1:0] memToReg,
  output reg [1:0] aluSrcA,
  output reg [1:0] aluSrcB,
  output reg jump,
  output reg branch,
  output reg memRead,
  output reg memWrite,
  output reg regWrite,
  output reg signExt
);


always @(*) begin

  if(rst == 1'b1) begin
    aluOp = 2'b00;
    memToReg = 2'b0;
    aluSrcA = 2'b0;
    aluSrcB = 2'b0;
    branch = 1'b0;
    jump = 1'b0;
    memRead = 1'b0;
    memWrite = 1'b0;
    regWrite = 1'b0;
    signExt  = 1'b0;
  end
  else begin
    case(opcode)


      4'b0000: begin
        aluOp = 3'b000;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0001: begin
        aluOp = 3'b001;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0010: begin
        aluOp = 3'b010;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0011: begin
        aluOp = 3'b011;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0100: begin
        aluOp = 3'b100;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0101: begin
        aluOp = 3'b101;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0110: begin
        aluOp = 3'b110;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b0111: begin
        aluOp = 3'b111;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b00;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b1000: begin
        aluOp = 3'b000;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b01;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b1001: begin
        aluOp = 3'b000;
        memToReg = 2'b00;
        aluSrcA = 2'b10;
        aluSrcB = 2'b10;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b1010: begin
        aluOp = 3'b000;
        memToReg = 2'b01;
        aluSrcA = 2'b00;
        aluSrcB = 2'b11;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b1;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b1011: begin
        aluOp = 3'b000;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b11;
        branch = 1'b0;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b1;
        regWrite = 1'b0;
        signExt  = 1'b0;
      end


      4'b1100: begin
        aluOp = 3'b000;
        memToReg = 2'b00;
        aluSrcA = 2'b00;
        aluSrcB = 2'b11;
        branch = 1'b1;
        jump = 1'b0;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b0;
        signExt  = 1'b0;
      end


      4'b1101: begin
        aluOp = 3'b000;
        memToReg = 2'b10;
        aluSrcA = 2'b11;
        aluSrcB = 2'b11;
        branch = 1'b0;
        jump = 1'b1;
        memRead = 1'b0;
        memWrite = 1'b0;
        regWrite = 1'b1;
        signExt  = 1'b0;
      end


      4'b1110: begin

      end


      4'b1111: begin

      end
    endcase
  end
end

endmodule