data/full_repos/permissive/143278/ivltests/pr993.v
 line:17: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr993.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("length=%3d, length_bits=%3d (%3d)",\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr993.v:9: Operator ADD expects 32 bits on the RHS, but RHS\'s NEQ generates 1 bits.\n                                                                    : ... In instance main\n   wire [31:0] length_bits  = ((length * 8 )/11)+(((length * 8 )%11) != 0);\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr993.v:15: Operator ADD expects 32 bits on the RHS, but RHS\'s NEQ generates 1 bits.\n                                                                     : ... In instance main\n  length_bits2 = ((length * 8 )/11)+(((length * 8 )%11) != 0);\n                                   ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   integer length;
   wire [31:0] length_bits  = ((length * 8 )/11)+(((length * 8 )%11) != 0);

   reg [31:0] length_bits2;

   initial begin
      for (length = 1 ;  length < 56 ;  length = length + 1) begin
	 length_bits2 = ((length * 8 )/11)+(((length * 8 )%11) != 0);

	 #1 $display("length=%3d, length_bits=%3d (%3d)",
		     length, length_bits, length_bits2);

	 if (length_bits != length_bits2) begin
	    $display("FAILED - Expressions have different results.");
	    $finish;
	 end
      end

      $finish(0);
   end

endmodule
module main;


   integer length;
   wire [31:0] length_bits  = ((length * 8 )/11)+(((length * 8 )%11) != 0);

   reg [31:0] length_bits2;

   initial begin
      for (length = 1 ;  length < 56 ;  length = length + 1) begin
	 length_bits2 = ((length * 8 )/11)+(((length * 8 )%11) != 0);

	 #1 $display("length=%3d, length_bits=%3d (%3d)",
		     length, length_bits, length_bits2);

	 if (length_bits != length_bits2) begin
	    $display("FAILED - Expressions have different results.");
	    $finish;
	 end
      end

      $finish(0);
   end

endmodule