data/full_repos/permissive/220229160/ql-qlf-plugin/tests/pp3_bram/pp3_bram.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/pp3_bram/pp3_bram.v:88: Multiple top level modules\n                                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                  : ... Top module \'top_bram_9_16\'\nmodule top_bram_9_16 (\n       ^~~~~~~~~~~~~\n                                                                                                  : ... Top module \'top_bram_9_32\'\nmodule top_bram_9_32 (\n       ^~~~~~~~~~~~~\n                                                                                                  : ... Top module \'top_bram_10_16\'\nmodule top_bram_10_16 (\n       ^~~~~~~~~~~~~~\n                                                                                                  : ... Top module \'top_bram_init\'\nmodule top_bram_init (\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/pp3_bram/pp3_bram.v:172: Cannot find file containing module: \'RAM_8K_BLK\'\n  RAM_8K_BLK #(\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220229160/ql-qlf-plugin/tests/pp3_bram,data/full_repos/permissive/220229160/RAM_8K_BLK\n             data/full_repos/permissive/220229160/ql-qlf-plugin/tests/pp3_bram,data/full_repos/permissive/220229160/RAM_8K_BLK.v\n             data/full_repos/permissive/220229160/ql-qlf-plugin/tests/pp3_bram,data/full_repos/permissive/220229160/RAM_8K_BLK.sv\n             RAM_8K_BLK\n             RAM_8K_BLK.v\n             RAM_8K_BLK.sv\n             obj_dir/RAM_8K_BLK\n             obj_dir/RAM_8K_BLK.v\n             obj_dir/RAM_8K_BLK.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module top_bram_9_32 (
    CLK,
    WADR,
    WDAT,
    WEN,
    RADR,
    RDAT
);

  input wire CLK;

  input wire [8 : 0] WADR;
  input wire [31:0] WDAT;
  input wire WEN;

  input wire [8 : 0] RADR;
  output wire [31:0] RDAT;

  my_ram #(
      .DBITS(32),
      .ABITS(9)
  ) the_ram (
      .CLK (CLK),
      .WADR(WADR),
      .WDAT(WDAT),
      .WEN (WEN),
      .RADR(RADR),
      .RDAT(RDAT),
      .REN (1'b0)
  );

endmodule
module top_bram_9_32 (
    CLK,
    WADR,
    WDAT,
    WEN,
    RADR,
    RDAT
);


  input wire CLK;

  input wire [8 : 0] WADR;
  input wire [31:0] WDAT;
  input wire WEN;

  input wire [8 : 0] RADR;
  output wire [31:0] RDAT;

  my_ram #(
      .DBITS(32),
      .ABITS(9)
  ) the_ram (
      .CLK (CLK),
      .WADR(WADR),
      .WDAT(WDAT),
      .WEN (WEN),
      .RADR(RADR),
      .RDAT(RDAT),
      .REN (1'b0)
  );

endmodule