data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v
 line:38: before: "$"
1: b'%Error: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:38: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #0\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:39: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:40: Unsupported or unknown PLI call: $monitor\n    $monitor("t=%3d x=%4b o=%4b",$time,i_operation_01, o_result_01);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP1-ALU-2019/Test/tb_ALU.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: Exiting due to 3 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_ALU();
  

  localparam    NB_DATA_01      = 8;
  localparam    NB_OP           = 6;


  reg [NB_OP-1:0] i_operation_01;
  reg [NB_DATA_01 - 1: 0] i_data_a_01;
  reg [NB_DATA_01 - 1: 0] i_data_b_01;

  wire signed [NB_DATA_01 - 1: 0] o_result_01;
  
  initial begin
    #0
    $dumpfile("dump.vcd");
    $dumpvars(1);
    $monitor("t=%3d x=%4b o=%4b",$time,i_operation_01, o_result_01);
    i_operation_01 = 6'b100000;
    i_data_a_01 = {NB_DATA_01{1'b0}};
    i_data_b_01 = {NB_DATA_01{1'b0}};
    #20
    i_operation_01 = 6'b100010;
    #20
    i_operation_01 = 6'b100100;
    #20
    i_operation_01 = 6'b100101;
    #20
    i_operation_01 = 6'b100110;
    #20
    i_operation_01 = 6'b000011;
    #20
    i_operation_01 = 6'b000010;
    #20
    i_operation_01 = 6'b100111;
    #20
    $finish;
  end

  always begin
  #10
    i_data_a_01 = $random;
    i_data_b_01 = $random;
  end

  ALU
  #(
    .NB_DATA (NB_DATA_01)
  )

  u_ALU_01
  (
    .i_operation (i_operation_01),
    .i_data_a (i_data_a_01),
    .i_data_b (i_data_b_01),
    .o_result (o_result_01)
  );

endmodule
module tb_ALU();

  

  localparam    NB_DATA_01      = 8;
  localparam    NB_OP           = 6;


  reg [NB_OP-1:0] i_operation_01;
  reg [NB_DATA_01 - 1: 0] i_data_a_01;
  reg [NB_DATA_01 - 1: 0] i_data_b_01;

  wire signed [NB_DATA_01 - 1: 0] o_result_01;
  
  initial begin
    #0
    $dumpfile("dump.vcd");
    $dumpvars(1);
    $monitor("t=%3d x=%4b o=%4b",$time,i_operation_01, o_result_01);
    i_operation_01 = 6'b100000;
    i_data_a_01 = {NB_DATA_01{1'b0}};
    i_data_b_01 = {NB_DATA_01{1'b0}};
    #20
    i_operation_01 = 6'b100010;
    #20
    i_operation_01 = 6'b100100;
    #20
    i_operation_01 = 6'b100101;
    #20
    i_operation_01 = 6'b100110;
    #20
    i_operation_01 = 6'b000011;
    #20
    i_operation_01 = 6'b000010;
    #20
    i_operation_01 = 6'b100111;
    #20
    $finish;
  end

  always begin
  #10
    i_data_a_01 = $random;
    i_data_b_01 = $random;
  end

  ALU
  #(
    .NB_DATA (NB_DATA_01)
  )

  u_ALU_01
  (
    .i_operation (i_operation_01),
    .i_data_a (i_data_a_01),
    .i_data_b (i_data_b_01),
    .o_result (o_result_01)
  );

endmodule