data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v
 line:32: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:7: Unsupported: Ignoring delay on this delayed statement.\nalways#(clock_period/2)Clk=~Clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #60 J=0;K=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=0;K=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=0;K=2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=0;K=3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=1;K=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=1;K=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=1;K=2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=1;K=3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=2;K=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=2;K=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=2;K=2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=2;K=3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=3;K=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=3;K=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=3;K=2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #20 J=3;K=3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:32: Unsupported: Ignoring delay on this delayed statement.\n #400 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #20 SD=2\'b00;RD=2\'b11;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #20 SD=2\'b11;RD=2\'b00;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #20 SD=2\'b11;RD=2\'b11;\n  ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:4: Little bit endian vector: MSB < LSB of bit range: 1:2\nreg [1:2]J,K,Clk,SD,RD;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:5: Little bit endian vector: MSB < LSB of bit range: 1:2\nwire [1:2]Q,QN;\n     ^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus/textbench112.v:42: Cannot find file containing module: \'HC112\'\nHC112 u1(J,K,Clk,SD,RD,Q,QN);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus,data/full_repos/permissive/165160692/HC112\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus,data/full_repos/permissive/165160692/HC112.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC112/stimulus,data/full_repos/permissive/165160692/HC112.sv\n             HC112\n             HC112.v\n             HC112.sv\n             obj_dir/HC112\n             obj_dir/HC112.v\n             obj_dir/HC112.sv\n%Error: Exiting due to 1 error(s), 23 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
reg [1:2]J,K,Clk,SD,RD;
wire [1:2]Q,QN;
parameter clock_period=20;
always#(clock_period/2)Clk=~Clk;

initial
 begin
  J=0;K=0;Clk=0;

  #60 J=0;K=0;
  #20 J=0;K=1;
  #20 J=0;K=2;
  #20 J=0;K=3;
  #20 J=1;K=0;
  #20 J=1;K=1;
  #20 J=1;K=2;
  #20 J=1;K=3;
  #20 J=2;K=0;
  #20 J=2;K=1;
  #20 J=2;K=2;
  #20 J=2;K=3;
  #20 J=3;K=0;
  #20 J=3;K=1;
  #20 J=3;K=2;
  #20 J=3;K=3;
 end

initial
 #400 $finish;

initial
 begin
  SD=2'b00;RD=2'b00;
  #20 SD=2'b00;RD=2'b11;
  #20 SD=2'b11;RD=2'b00;
  #20 SD=2'b11;RD=2'b11;
 end

HC112 u1(J,K,Clk,SD,RD,Q,QN);
endmodule
module testbench;

reg [1:2]J,K,Clk,SD,RD;
wire [1:2]Q,QN;
parameter clock_period=20;
always#(clock_period/2)Clk=~Clk;

initial
 begin
  J=0;K=0;Clk=0;

  #60 J=0;K=0;
  #20 J=0;K=1;
  #20 J=0;K=2;
  #20 J=0;K=3;
  #20 J=1;K=0;
  #20 J=1;K=1;
  #20 J=1;K=2;
  #20 J=1;K=3;
  #20 J=2;K=0;
  #20 J=2;K=1;
  #20 J=2;K=2;
  #20 J=2;K=3;
  #20 J=3;K=0;
  #20 J=3;K=1;
  #20 J=3;K=2;
  #20 J=3;K=3;
 end

initial
 #400 $finish;

initial
 begin
  SD=2'b00;RD=2'b00;
  #20 SD=2'b00;RD=2'b11;
  #20 SD=2'b11;RD=2'b00;
  #20 SD=2'b11;RD=2'b11;
 end

HC112 u1(J,K,Clk,SD,RD,Q,QN);
endmodule