data/full_repos/permissive/143278/ivltests/string9.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/143278/ivltests/string9.v:24: Little bit endian vector: MSB < LSB of bit range: 0:39\n reg [0:39] myReg40r;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/143278/ivltests/string9.v:25: Little bit endian vector: MSB < LSB of bit range: 0:38\n reg [0:38] myReg39r;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/string9.v:52: Operator ASSIGN expects 39 bits on the Assign RHS, but Assign RHS\'s CONST \'40\'h3132333435\' generates 40 bits.\n                                                                       : ... In instance main\n  myReg39r = "12345";\n           ^\n%Error: Exiting due to 3 warning(s)\n'
module main;

	integer myInt;
	reg [39:0] myReg40;
	reg [0:39] myReg40r;
	reg [0:38] myReg39r;
	reg [13:0] myReg14;
	reg [7:0] myReg8;

	initial begin
		$display("============================ myReg8 = 65");
		myReg8 = 65;
		$display(">|A|");
		$display("*|%c|", myReg8);

		$display("============================ myReg40 = \"12345\"");
		myReg40 = "12345";

		$display(">|5|");
		$display("*|%c|", myReg40);
		$display(">|5|");
		$display("*|%s|", myReg40[7:0]);

		$display("============================ myReg40r = \"12345\"");
		myReg40r = "12345";

		$display(">|5|");
		$display("*|%c|", myReg40r);
		$display(">|1|");
		$display("*|%c|", myReg40r[0:7]);

		$display("============================ myReg39r = \"12345\"");
		myReg39r = "12345";

		$display(">|5|");
		$display("*|%c|", myReg39r);
		$display(">|b|");
		$display("*|%c|", myReg39r[0:7]);

		$display("============================ myReg14 = 33*256+65");
		myReg14 = 33*256 + 65;
		$display(">|A|");
		$display("*|%c|", myReg14);
		$display(">|!|");
		$display("*|%c|", myReg14[13:8]);

		$display("============================ myInt = 66*256 + 65");
		myInt = 66*256 + 65;

		$display(">|A|");
		$display("*|%c|", myInt);
	end
endmodule
module main;


	integer myInt;
	reg [39:0] myReg40;
	reg [0:39] myReg40r;
	reg [0:38] myReg39r;
	reg [13:0] myReg14;
	reg [7:0] myReg8;

	initial begin
		$display("============================ myReg8 = 65");
		myReg8 = 65;
		$display(">|A|");
		$display("*|%c|", myReg8);

		$display("============================ myReg40 = \"12345\"");
		myReg40 = "12345";

		$display(">|5|");
		$display("*|%c|", myReg40);
		$display(">|5|");
		$display("*|%s|", myReg40[7:0]);

		$display("============================ myReg40r = \"12345\"");
		myReg40r = "12345";

		$display(">|5|");
		$display("*|%c|", myReg40r);
		$display(">|1|");
		$display("*|%c|", myReg40r[0:7]);

		$display("============================ myReg39r = \"12345\"");
		myReg39r = "12345";

		$display(">|5|");
		$display("*|%c|", myReg39r);
		$display(">|b|");
		$display("*|%c|", myReg39r[0:7]);

		$display("============================ myReg14 = 33*256+65");
		myReg14 = 33*256 + 65;
		$display(">|A|");
		$display("*|%c|", myReg14);
		$display(">|!|");
		$display("*|%c|", myReg14[13:8]);

		$display("============================ myInt = 66*256 + 65");
		myInt = 66*256 + 65;

		$display(">|A|");
		$display("*|%c|", myInt);
	end
endmodule