data/full_repos/permissive/167962127/s16_to_u16.v
data/verilator_xmls/3d8cb69b-cdc8-466a-9a31-558a13fd8da3.xml
module s16_to_u16(
  input i_clk,
  input signed [15:0] i_s16,
  output reg [15:0] o_u16
);

  always @ (posedge i_clk) begin
    o_u16 <= i_s16 + 16'd32767;
  end

endmodule
module s16_to_u16(
  input i_clk,
  input signed [15:0] i_s16,
  output reg [15:0] o_u16
);


  always @ (posedge i_clk) begin
    o_u16 <= i_s16 + 16'd32767;
  end

endmodule