data/full_repos/permissive/14432793/Memory/clock_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/14432793/Memory/clock_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk <= !clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14432793/Memory/clock_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #20000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/Memory/clock_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #6000000;\n      ^\n%Error: data/full_repos/permissive/14432793/Memory/clock_tb.v:9: Cannot find file containing module: \'clock_divider\'\n  clock_divider u1 (clk, reset, enabled, clk_out, clk_offset);\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14432793/Memory,data/full_repos/permissive/14432793/clock_divider\n             data/full_repos/permissive/14432793/Memory,data/full_repos/permissive/14432793/clock_divider.v\n             data/full_repos/permissive/14432793/Memory,data/full_repos/permissive/14432793/clock_divider.sv\n             clock_divider\n             clock_divider.v\n             clock_divider.sv\n             obj_dir/clock_divider\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock_test();

  reg clk;
  reg reset;
  reg enabled;
  wire clk_out;
  wire clk_offset;

  clock_divider u1 (clk, reset, enabled, clk_out, clk_offset);

  always
    begin
      #5 clk <= !clk;
    end

  initial
    begin
      clk = 0;
      reset = 0;
      enabled = 0;
      #20000
      reset = 1;
      enabled = 1;
      #6000000;
      $finish;
    end

endmodule
module clock_test();


  reg clk;
  reg reset;
  reg enabled;
  wire clk_out;
  wire clk_offset;

  clock_divider u1 (clk, reset, enabled, clk_out, clk_offset);

  always
    begin
      #5 clk <= !clk;
    end

  initial
    begin
      clk = 0;
      reset = 0;
      enabled = 0;
      #20000
      reset = 1;
      enabled = 1;
      #6000000;
      $finish;
    end

endmodule