data/full_repos/permissive/143278/ivltests/array_select.v
 line:8: before: "["
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/array_select.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/array_select.v:17: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                            : ... In instance top\n  initial for (idx = 0; idx < 8 ; idx = idx + 1) arr[idx] = idx+1;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/array_select.v:51: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                            : ... In instance top\n    res = arr[idx][0];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/array_select.v:57: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                            : ... In instance top\n    res = arr[0][idx];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/array_select.v:64: Bit extraction of var[7:0] requires 3 bit index, not 2 bits.\n                                                                            : ... In instance top\n    res = arr[0][idx2];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/array_select.v:64: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                            : ... In instance top\n    res = arr[0][idx2];\n        ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass = 1'b1;
  reg signed [7:0] arr [0:7];
  integer idx;
  reg signed [1:0] idx2;
  reg [7:0] res;

  real rarr [0:7];
  real rres;

  reg signed [2:0] a [0:3];
  wire signed [2:0] n [0:3];
  assign n[3] = 0;
  assign n[0] = -1;

  initial for (idx = 0; idx < 8 ; idx = idx + 1) rarr[idx] = idx+1.0;
  initial for (idx = 0; idx < 8 ; idx = idx + 1) arr[idx] = idx+1;
  initial begin
    #1;
    idx = 'bx;


    rres = rarr[idx];
    if (rres != 0.0) begin
      $display("Failed simple real array test, got %f.", rres);
      pass = 1'b0;
    end


    res = arr[idx];
    if (res !== 8'bx) begin
      $display("Failed simple array vector test, got %b.", res);
      pass = 1'b0;
    end


    res = arr[idx]+8'b1;
    if (res !== 8'bx) begin
      $display("Failed array vector plus constant test, got %b.", res);
      pass = 1'b0;
    end


    res = arr[idx]+8'sb1;
    if (res !== 8'bx) begin
      $display("Failed array vector plus signed constant test, got %b.", res);
      pass = 1'b0;
    end


    res = arr[idx][0];
    if (res !== 8'b0x) begin
      $display("Failed array vector bit select test 1, got %b.", res);
      pass = 1'b0;
    end

    res = arr[0][idx];
    if (res !== 8'b0x) begin
      $display("Failed array vector bit select test 2, got %b.", res);
      pass = 1'b0;
    end

    idx2 = -1;
    res = arr[0][idx2];
    if (res !== 8'b0x) begin
      $display("Failed array vector bit select test 3, got %b.", res);
      pass = 1'b0;
    end



    idx2 = -1;
    a[3] = 0;
    a[0] = -1;
    res = arr[a[idx2]];
    if (res !== 8'bx) begin
      $display("Failed: reg array select driving array select, got %b", res);
      pass = 1'b0;
    end


    res = arr[n[idx2]];
    if (res !== 8'bx) begin
      $display("Failed: wire array select driving array select, got %b", res);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass = 1'b1;
  reg signed [7:0] arr [0:7];
  integer idx;
  reg signed [1:0] idx2;
  reg [7:0] res;

  real rarr [0:7];
  real rres;

  reg signed [2:0] a [0:3];
  wire signed [2:0] n [0:3];
  assign n[3] = 0;
  assign n[0] = -1;

  initial for (idx = 0; idx < 8 ; idx = idx + 1) rarr[idx] = idx+1.0;
  initial for (idx = 0; idx < 8 ; idx = idx + 1) arr[idx] = idx+1;
  initial begin
    #1;
    idx = 'bx;


    rres = rarr[idx];
    if (rres != 0.0) begin
      $display("Failed simple real array test, got %f.", rres);
      pass = 1'b0;
    end


    res = arr[idx];
    if (res !== 8'bx) begin
      $display("Failed simple array vector test, got %b.", res);
      pass = 1'b0;
    end


    res = arr[idx]+8'b1;
    if (res !== 8'bx) begin
      $display("Failed array vector plus constant test, got %b.", res);
      pass = 1'b0;
    end


    res = arr[idx]+8'sb1;
    if (res !== 8'bx) begin
      $display("Failed array vector plus signed constant test, got %b.", res);
      pass = 1'b0;
    end


    res = arr[idx][0];
    if (res !== 8'b0x) begin
      $display("Failed array vector bit select test 1, got %b.", res);
      pass = 1'b0;
    end

    res = arr[0][idx];
    if (res !== 8'b0x) begin
      $display("Failed array vector bit select test 2, got %b.", res);
      pass = 1'b0;
    end

    idx2 = -1;
    res = arr[0][idx2];
    if (res !== 8'b0x) begin
      $display("Failed array vector bit select test 3, got %b.", res);
      pass = 1'b0;
    end



    idx2 = -1;
    a[3] = 0;
    a[0] = -1;
    res = arr[a[idx2]];
    if (res !== 8'bx) begin
      $display("Failed: reg array select driving array select, got %b", res);
      pass = 1'b0;
    end


    res = arr[n[idx2]];
    if (res !== 8'bx) begin
      $display("Failed: wire array select driving array select, got %b", res);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule