data/full_repos/permissive/170013753/src/reg16.v
data/verilator_xmls/8c861a94-fcb4-4a4b-8995-1e87068e65a5.xml
module reg16(
  input  clk,
  input  rst,
  input  en,
  input  selA,
  input  selB,
  input  [15:0] d,
  output [15:0] a,
  output [15:0] b
);

  reg [15:0] o;

  always @(posedge clk) begin
    if(rst)     o <= 16'b0;
    else if(en) o <= d;
    else        o <= o;
  end

  assign a = selA ? o : 16'bz;
  assign b = selB ? o : 16'bz;

endmodule
module reg16(
  input  clk,
  input  rst,
  input  en,
  input  selA,
  input  selB,
  input  [15:0] d,
  output [15:0] a,
  output [15:0] b
);


  reg [15:0] o;

  always @(posedge clk) begin
    if(rst)     o <= 16'b0;
    else if(en) o <= d;
    else        o <= o;
  end

  assign a = selA ? o : 16'bz;
  assign b = selB ? o : 16'bz;

endmodule