data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/regfile_37.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/regfile_37.v:30: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                          : ... In instance regfile_37\n  reg [255:0] M_map_d, M_map_q = 1\'h0;\n                                 ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/regfile_37.v:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                          : ... In instance regfile_37\n  reg [15:0] M_player_position_d, M_player_position_q = 1\'h0;\n                                                        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/regfile_37.v:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                          : ... In instance regfile_37\n  reg [7:0] M_win_position_d, M_win_position_q = 1\'h0;\n                                                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/regfile_37.v:69: Operator ASSIGNDLY expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                          : ... In instance regfile_37\n      M_map_q <= 1\'h0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/regfile_37.v:70: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                          : ... In instance regfile_37\n      M_player_position_q <= 1\'h0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/regfile_37.v:71: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                          : ... In instance regfile_37\n      M_win_position_q <= 1\'h0;\n                       ^~\n%Error: Exiting due to 6 warning(s)\n'
module regfile_37 (
    input clk,
    input rst,
    input [255:0] map_in,
    input [15:0] player_position_in,
    input [7:0] win_position_in,
    input win_bool_in,
    input loss_bool_in,
    input portrait_orientation_in,
    input horizontal_orientation_in,
    input vertical_orientation_in,
    output reg [255:0] map_out,
    output reg [15:0] player_position_out,
    output reg [7:0] win_position_out,
    output reg win_bool_out,
    output reg loss_bool_out,
    output reg portrait_orientation_out,
    output reg horizontal_orientation_out,
    output reg vertical_orientation_out
  );
  
  
  
  reg [255:0] M_map_d, M_map_q = 1'h0;
  reg [15:0] M_player_position_d, M_player_position_q = 1'h0;
  reg [7:0] M_win_position_d, M_win_position_q = 1'h0;
  reg M_win_bool_d, M_win_bool_q = 1'h0;
  reg M_loss_bool_d, M_loss_bool_q = 1'h0;
  reg M_portrait_orientation_d, M_portrait_orientation_q = 1'h0;
  reg M_horizontal_orientation_d, M_horizontal_orientation_q = 1'h0;
  reg M_vertical_orientation_d, M_vertical_orientation_q = 1'h0;
  
  always @* begin
    M_player_position_d = M_player_position_q;
    M_vertical_orientation_d = M_vertical_orientation_q;
    M_portrait_orientation_d = M_portrait_orientation_q;
    M_loss_bool_d = M_loss_bool_q;
    M_map_d = M_map_q;
    M_win_position_d = M_win_position_q;
    M_horizontal_orientation_d = M_horizontal_orientation_q;
    M_win_bool_d = M_win_bool_q;
    
    M_map_d = map_in;
    map_out = M_map_q;
    M_player_position_d = player_position_in;
    player_position_out = M_player_position_q;
    M_win_position_d = win_position_in;
    win_position_out = M_win_position_q;
    M_win_bool_d = win_bool_in;
    win_bool_out = M_win_bool_q;
    M_loss_bool_d = loss_bool_in;
    loss_bool_out = M_loss_bool_q;
    M_portrait_orientation_d = portrait_orientation_in;
    portrait_orientation_out = M_portrait_orientation_q;
    M_horizontal_orientation_d = horizontal_orientation_in;
    horizontal_orientation_out = M_horizontal_orientation_q;
    M_vertical_orientation_d = vertical_orientation_in;
    vertical_orientation_out = M_vertical_orientation_q;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_map_q <= 1'h0;
      M_player_position_q <= 1'h0;
      M_win_position_q <= 1'h0;
      M_win_bool_q <= 1'h0;
      M_loss_bool_q <= 1'h0;
      M_portrait_orientation_q <= 1'h0;
      M_horizontal_orientation_q <= 1'h0;
      M_vertical_orientation_q <= 1'h0;
    end else begin
      M_map_q <= M_map_d;
      M_player_position_q <= M_player_position_d;
      M_win_position_q <= M_win_position_d;
      M_win_bool_q <= M_win_bool_d;
      M_loss_bool_q <= M_loss_bool_d;
      M_portrait_orientation_q <= M_portrait_orientation_d;
      M_horizontal_orientation_q <= M_horizontal_orientation_d;
      M_vertical_orientation_q <= M_vertical_orientation_d;
    end
  end
  
endmodule
module regfile_37 (
    input clk,
    input rst,
    input [255:0] map_in,
    input [15:0] player_position_in,
    input [7:0] win_position_in,
    input win_bool_in,
    input loss_bool_in,
    input portrait_orientation_in,
    input horizontal_orientation_in,
    input vertical_orientation_in,
    output reg [255:0] map_out,
    output reg [15:0] player_position_out,
    output reg [7:0] win_position_out,
    output reg win_bool_out,
    output reg loss_bool_out,
    output reg portrait_orientation_out,
    output reg horizontal_orientation_out,
    output reg vertical_orientation_out
  );

  
  
  
  reg [255:0] M_map_d, M_map_q = 1'h0;
  reg [15:0] M_player_position_d, M_player_position_q = 1'h0;
  reg [7:0] M_win_position_d, M_win_position_q = 1'h0;
  reg M_win_bool_d, M_win_bool_q = 1'h0;
  reg M_loss_bool_d, M_loss_bool_q = 1'h0;
  reg M_portrait_orientation_d, M_portrait_orientation_q = 1'h0;
  reg M_horizontal_orientation_d, M_horizontal_orientation_q = 1'h0;
  reg M_vertical_orientation_d, M_vertical_orientation_q = 1'h0;
  
  always @* begin
    M_player_position_d = M_player_position_q;
    M_vertical_orientation_d = M_vertical_orientation_q;
    M_portrait_orientation_d = M_portrait_orientation_q;
    M_loss_bool_d = M_loss_bool_q;
    M_map_d = M_map_q;
    M_win_position_d = M_win_position_q;
    M_horizontal_orientation_d = M_horizontal_orientation_q;
    M_win_bool_d = M_win_bool_q;
    
    M_map_d = map_in;
    map_out = M_map_q;
    M_player_position_d = player_position_in;
    player_position_out = M_player_position_q;
    M_win_position_d = win_position_in;
    win_position_out = M_win_position_q;
    M_win_bool_d = win_bool_in;
    win_bool_out = M_win_bool_q;
    M_loss_bool_d = loss_bool_in;
    loss_bool_out = M_loss_bool_q;
    M_portrait_orientation_d = portrait_orientation_in;
    portrait_orientation_out = M_portrait_orientation_q;
    M_horizontal_orientation_d = horizontal_orientation_in;
    horizontal_orientation_out = M_horizontal_orientation_q;
    M_vertical_orientation_d = vertical_orientation_in;
    vertical_orientation_out = M_vertical_orientation_q;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_map_q <= 1'h0;
      M_player_position_q <= 1'h0;
      M_win_position_q <= 1'h0;
      M_win_bool_q <= 1'h0;
      M_loss_bool_q <= 1'h0;
      M_portrait_orientation_q <= 1'h0;
      M_horizontal_orientation_q <= 1'h0;
      M_vertical_orientation_q <= 1'h0;
    end else begin
      M_map_q <= M_map_d;
      M_player_position_q <= M_player_position_d;
      M_win_position_q <= M_win_position_d;
      M_win_bool_q <= M_win_bool_d;
      M_loss_bool_q <= M_loss_bool_d;
      M_portrait_orientation_q <= M_portrait_orientation_d;
      M_horizontal_orientation_q <= M_horizontal_orientation_d;
      M_vertical_orientation_q <= M_vertical_orientation_d;
    end
  end
  
endmodule