data/full_repos/permissive/143278/ivltests/pr1925363b.v
139: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1925363b.v:8: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                         : ... In instance top\n    rpass = {(wid-8){ 8\'b0}};  \n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1925363b.v:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates -56 bits.\n                                                                         : ... In instance top\n    rfail = {(wid-16){8\'b0}};  \n          ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/143278/ivltests/pr1925363b.v:9: More than a 8k bit replication is probably wrong: 4294967289\n                                                                               : ... In instance top\n    rfail = {(wid-16){8\'b0}};  \n                     ^\nSegmentation fault\n%Error: Command Failed /usr/bin/verilator_bin --xml-output data/verilator_xmls/fcf4b865-c49f-4e49-bf1c-395d48e57512.xml --y data/full_repos/permissive/143278/ivltests\\,data/full_repos/permissive/143278 data/full_repos/permissive/143278/ivltests/pr1925363b.v\n'
module top;
  parameter wid = 9;

  reg [31:0] rpass;
  reg [31:0] rfail;

  initial begin
    rpass = {(wid-8){ 8'b0}};
    rfail = {(wid-16){8'b0}};
  end
endmodule
module top;

  parameter wid = 9;

  reg [31:0] rpass;
  reg [31:0] rfail;

  initial begin
    rpass = {(wid-8){ 8'b0}};
    rfail = {(wid-16){8'b0}};
  end
endmodule