data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:29: Signal definition not found, creating implicitly: \'switch_debounced\'\n                                                                                        : ... Suggested alternative: \'switch_debounced_d\'\n    switch_debounced_d <= switch_debounced;   \n                          ^~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:46: Signal definition not found, creating implicitly: \'ten_ms\'\n      .sample_en(ten_ms),      \n                 ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:56: Signal definition not found, creating implicitly: \'ten_us\'\n                                                                                        : ... Suggested alternative: \'ten_ms\'\n        .timer_pulse(ten_us));\n                     ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:18: Operator EQ expects 25 bits on the RHS, but RHS\'s REPLICATE generates 24 bits.\n                                                                                     : ... In instance fpga_top\n       if (counter == ( {blink_cnt, 20\'h42400} )) begin    \n                   ^~\n%Error: Exiting due to 4 warning(s)\n'
module fpga_top(output reg WF_LED, input WF_CLK, input WF_BUTTON);
    reg  [24:0] counter;
    wire        switch_pushed;
    wire        switch_released;
    reg         switch_debounced_d;
    reg  [3:0]  blink_cnt;


    always @ (posedge WF_CLK) begin



       if (counter == ( {blink_cnt, 20'h42400} )) begin    
            WF_LED   <= ~WF_LED;
            counter  <= 'b0;
        end else begin
            counter  <= counter + 'b1;
        end
    end
    
    

  always @ (posedge WF_CLK)
    switch_debounced_d <= switch_debounced;
    
 
  assign switch_pushed   = ~switch_debounced &&  switch_debounced_d;
  assign switch_released =  switch_debounced && ~switch_debounced_d;

  always @ (posedge WF_CLK)
     if (blink_cnt == 0)
       blink_cnt <= 4'b0001;
     else
        if (switch_pushed)

         blink_cnt <= { blink_cnt[2:0],blink_cnt[3]};


    WF_switch_debounce switch_deb1 (
      .clk(WF_CLK),
      .sample_en(ten_ms),
      .switch_in(WF_BUTTON),
      .switch_out(switch_debounced),
      .switch_pushed(),
      .switch_released() );
      
      
    WF_timer #(.COUNT(159), .EVERY_CLK(1'b1)) ten_usec(
        .clk(WF_CLK),
        .enable(1'b1),
        .timer_pulse(ten_us));


    WF_timer #(.COUNT(999)) ten_msec(
        .clk(WF_CLK),
        .enable(ten_us),
        .timer_pulse(ten_ms));

endmodule
module fpga_top(output reg WF_LED, input WF_CLK, input WF_BUTTON);

    reg  [24:0] counter;
    wire        switch_pushed;
    wire        switch_released;
    reg         switch_debounced_d;
    reg  [3:0]  blink_cnt;


    always @ (posedge WF_CLK) begin



       if (counter == ( {blink_cnt, 20'h42400} )) begin    
            WF_LED   <= ~WF_LED;
            counter  <= 'b0;
        end else begin
            counter  <= counter + 'b1;
        end
    end
    
    

  always @ (posedge WF_CLK)
    switch_debounced_d <= switch_debounced;
    
 
  assign switch_pushed   = ~switch_debounced &&  switch_debounced_d;
  assign switch_released =  switch_debounced && ~switch_debounced_d;

  always @ (posedge WF_CLK)
     if (blink_cnt == 0)
       blink_cnt <= 4'b0001;
     else
        if (switch_pushed)

         blink_cnt <= { blink_cnt[2:0],blink_cnt[3]};


    WF_switch_debounce switch_deb1 (
      .clk(WF_CLK),
      .sample_en(ten_ms),
      .switch_in(WF_BUTTON),
      .switch_out(switch_debounced),
      .switch_pushed(),
      .switch_released() );
      
      
    WF_timer #(.COUNT(159), .EVERY_CLK(1'b1)) ten_usec(
        .clk(WF_CLK),
        .enable(1'b1),
        .timer_pulse(ten_us));


    WF_timer #(.COUNT(999)) ten_msec(
        .clk(WF_CLK),
        .enable(ten_us),
        .timer_pulse(ten_ms));

endmodule