data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0301/lab0301.srcs/sim_1/new/Ctr_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0301/lab0301.srcs/sim_1/new/Ctr_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0301/lab0301.srcs/sim_1/new/Ctr_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0301/lab0301.srcs/sim_1/new/Ctr_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0301/lab0301.srcs/sim_1/new/Ctr_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0301/lab0301.srcs/sim_1/new/Ctr_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0301/lab0301.srcs/sim_1/new/Ctr_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0301/lab0301.srcs/sim_1/new/Ctr_tb.v:28: Cannot find file containing module: \'Ctr\'\n    Ctr u0(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0301/lab0301.srcs/sim_1/new,data/full_repos/permissive/194376374/Ctr\n             data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0301/lab0301.srcs/sim_1/new,data/full_repos/permissive/194376374/Ctr.v\n             data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0301/lab0301.srcs/sim_1/new,data/full_repos/permissive/194376374/Ctr.sv\n             Ctr\n             Ctr.v\n             Ctr.sv\n             obj_dir/Ctr\n             obj_dir/Ctr.v\n             obj_dir/Ctr.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Ctr_tb(

    );
    reg [5:0] OpCode;
    
    Ctr u0(
    .OpCode(OpCode)
    );
    
    initial begin

    OpCode=0;
    

    #100;
    
    #100
    OpCode=6'b000000;
    
    #100
    OpCode=6'b100011;
    
    #100
    OpCode=6'b101011;
    
    #100
    OpCode=6'b000100;
    
    #100
    OpCode=6'b000010;
    
    end
endmodule
module Ctr_tb(

    );

    reg [5:0] OpCode;
    
    Ctr u0(
    .OpCode(OpCode)
    );
    
    initial begin

    OpCode=0;
    

    #100;
    
    #100
    OpCode=6'b000000;
    
    #100
    OpCode=6'b100011;
    
    #100
    OpCode=6'b101011;
    
    #100
    OpCode=6'b000100;
    
    #100
    OpCode=6'b000010;
    
    end
endmodule