data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v
 line:90: before: ":"
1: b'%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:2: Cannot find include file: definitions.vh\n`include "definitions.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh.v\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh.sv\n             definitions.vh\n             definitions.vh.v\n             definitions.vh.sv\n             obj_dir/definitions.vh\n             obj_dir/definitions.vh.v\n             obj_dir/definitions.vh.sv\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:9: Define or directive not defined: \'`REG_DST_LENGTH\'\n           input  wire[`REG_DST_LENGTH - 1:0] cu_reg_dst,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:16: Define or directive not defined: \'`REG_31_ADDR\'\nassign reg_31 = `REG_31_ADDR;\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:16: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign reg_31 = `REG_31_ADDR;\n                            ^\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:19: Define or directive not defined: \'`REG_DST_RT\'\n       (cu_reg_dst == `REG_DST_RT    ) ? rt :\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:19: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n       (cu_reg_dst == `REG_DST_RT    ) ? rt :\n                                     ^\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:20: Define or directive not defined: \'`REG_DST_RD\'\n       (cu_reg_dst == `REG_DST_RD    ) ? rd :\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:21: Define or directive not defined: \'`REG_DST_REG_31\'\n       (cu_reg_dst == `REG_DST_REG_31) ? reg_31 :\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:33: Define or directive not defined: \'`ALU_SRC_REG\'\nassign mux_out = (cu_alu_src == `ALU_SRC_REG) ? rt : imm;\n                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:33: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign mux_out = (cu_alu_src == `ALU_SRC_REG) ? rt : imm;\n                                            ^\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:37: Define or directive not defined: \'`REG_SRC_LENGTH\'\n           input  wire[`REG_SRC_LENGTH - 1:0] cu_reg_src,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:47: Define or directive not defined: \'`REG_SRC_ALU\'\n       (cu_reg_src == `REG_SRC_ALU    ) ? alu_result :\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:47: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n       (cu_reg_src == `REG_SRC_ALU    ) ? alu_result :\n                                      ^\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:48: Define or directive not defined: \'`REG_SRC_MEM\'\n       (cu_reg_src == `REG_SRC_MEM    ) ? read_mem_data :\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:49: Define or directive not defined: \'`REG_SRC_IMM\'\n       (cu_reg_src == `REG_SRC_IMM    ) ? extend_imm :\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:50: Define or directive not defined: \'`REG_SRC_JMP_DST\'\n       (cu_reg_src == `REG_SRC_JMP_DST) ? jmp_dst :\n                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:64: Define or directive not defined: \'`FORWARD_ONE_CYCLE\'\n        (forward_C == `FORWARD_ONE_CYCLE) ? alu_result :\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:64: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        (forward_C == `FORWARD_ONE_CYCLE) ? alu_result :\n                                        ^\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/mux.v:65: Define or directive not defined: \'`FORWARD_TWO_CYCLE\'\n        (forward_C == `FORWARD_TWO_CYCLE) ? write_data :\n                      ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module reg_dst_mux(
           input  wire[`REG_DST_LENGTH - 1:0] cu_reg_dst,
           input  wire[4:0]                   rt,
           input  wire[4:0]                   rd,
                  
           output wire[4:0]                   mux_out
       );
wire[4:0] reg_31;
assign reg_31 = `REG_31_ADDR;

assign mux_out = 
       (cu_reg_dst == `REG_DST_RT    ) ? rt :
       (cu_reg_dst == `REG_DST_RD    ) ? rd :
       (cu_reg_dst == `REG_DST_REG_31) ? reg_31 :
       rt;
endmodule
module reg_dst_mux(
           input  wire[`REG_DST_LENGTH - 1:0] cu_reg_dst,
           input  wire[4:0]                   rt,
           input  wire[4:0]                   rd,
                  
           output wire[4:0]                   mux_out
       );

wire[4:0] reg_31;
assign reg_31 = `REG_31_ADDR;

assign mux_out = 
       (cu_reg_dst == `REG_DST_RT    ) ? rt :
       (cu_reg_dst == `REG_DST_RD    ) ? rd :
       (cu_reg_dst == `REG_DST_REG_31) ? reg_31 :
       rt;
endmodule