data/full_repos/permissive/191241380/common/vgatext.v
1: b"%Error: data/full_repos/permissive/191241380/common/vgatext.v:38: Cannot find file containing module: 'videosyncs'\n  videosyncs sincronismos (   \n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191241380/common,data/full_repos/permissive/191241380/videosyncs\n             data/full_repos/permissive/191241380/common,data/full_repos/permissive/191241380/videosyncs.v\n             data/full_repos/permissive/191241380/common,data/full_repos/permissive/191241380/videosyncs.sv\n             videosyncs\n             videosyncs.v\n             videosyncs.sv\n             obj_dir/videosyncs\n             obj_dir/videosyncs.v\n             obj_dir/videosyncs.sv\n%Error: Exiting due to 1 error(s)\n"
module vga_text (
  input wire vclk,

	input wire [11:0] addr,
  input wire [7:0] din,
  input wire we,
  output wire [7:0] dout,

  output reg red,
  output reg green,
  output reg blue,
  output wire hsync,
  output wire vsync
  );

  wire [10:0] hc,vc;

  videosyncs sincronismos (
    .clk(vclk),
    .hs(hsync),
    .vs(vsync),
 	  .hc(hc),
	  .vc(vc),
    .display_enable()
  );

  reg [10:0] vaddr;
  wire [7:0] character,attr;
  wire [11:0] bmaddr = {character,vc[3:0]};
  wire [7:0] bitmap;

  vram memoria_video (
    .clk(vclk),

    .addr_sys(addr),
    .din_sys(din),
    .we_sys(we),
    .dout_sys(dout),

    .addr_video(vaddr),
    .char_video(character),
    .attr_video(attr),

    .bmaddr(bmaddr),
    .bitmap(bitmap)
  );








  reg [7:0] sr,attrout;
  wire pixel = sr[7];
  always @(posedge vclk) begin
    if (hc[2:0] != 3'd7)
      sr <= {sr[6:0], 1'b0};
    if (hc == 11'd0 && vc == 11'd480)
      vaddr <= 11'h000;
    else if (vc >= 11'd32 && vc < 11'd432 && hc >= 11'd0 && hc < 11'd640) begin
      if (hc[2:0] == 3'd7) begin
        attrout <= attr;
        sr <= bitmap;
        vaddr <= vaddr + 11'd1;
      end
    end
    else if (vc >= 11'd32 && vc < 11'd432 && hc == 11'd648) begin
      if (vc[3:0] != 4'd15)
        vaddr <= vaddr - 11'd80;
    end
  end    

  always @* begin
    if (vc >= 11'd32 && vc < 11'd432 && hc >= 11'd8 && hc < 11'd648) begin
      if (pixel == 1'b1)
        {red, green, blue} = attrout[2:0];
      else
        {red, green, blue} = attrout[6:4];
    end
    else
      {red, green, blue} = 3'b000;
  end
endmodule
module vga_text (
  input wire vclk,

	input wire [11:0] addr,
  input wire [7:0] din,
  input wire we,
  output wire [7:0] dout,

  output reg red,
  output reg green,
  output reg blue,
  output wire hsync,
  output wire vsync
  );


  wire [10:0] hc,vc;

  videosyncs sincronismos (
    .clk(vclk),
    .hs(hsync),
    .vs(vsync),
 	  .hc(hc),
	  .vc(vc),
    .display_enable()
  );

  reg [10:0] vaddr;
  wire [7:0] character,attr;
  wire [11:0] bmaddr = {character,vc[3:0]};
  wire [7:0] bitmap;

  vram memoria_video (
    .clk(vclk),

    .addr_sys(addr),
    .din_sys(din),
    .we_sys(we),
    .dout_sys(dout),

    .addr_video(vaddr),
    .char_video(character),
    .attr_video(attr),

    .bmaddr(bmaddr),
    .bitmap(bitmap)
  );








  reg [7:0] sr,attrout;
  wire pixel = sr[7];
  always @(posedge vclk) begin
    if (hc[2:0] != 3'd7)
      sr <= {sr[6:0], 1'b0};
    if (hc == 11'd0 && vc == 11'd480)
      vaddr <= 11'h000;
    else if (vc >= 11'd32 && vc < 11'd432 && hc >= 11'd0 && hc < 11'd640) begin
      if (hc[2:0] == 3'd7) begin
        attrout <= attr;
        sr <= bitmap;
        vaddr <= vaddr + 11'd1;
      end
    end
    else if (vc >= 11'd32 && vc < 11'd432 && hc == 11'd648) begin
      if (vc[3:0] != 4'd15)
        vaddr <= vaddr - 11'd80;
    end
  end    

  always @* begin
    if (vc >= 11'd32 && vc < 11'd432 && hc >= 11'd8 && hc < 11'd648) begin
      if (pixel == 1'b1)
        {red, green, blue} = attrout[2:0];
      else
        {red, green, blue} = attrout[6:4];
    end
    else
      {red, green, blue} = 3'b000;
  end
endmodule