data/full_repos/permissive/175808891/verilog/dct.v
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1: b'%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:103: Cell has missing pin: \'en\'\nbutterfly b1(x01,x71,x[0],x[7]);\n          ^~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:104: Cell has missing pin: \'en\'\nbutterfly b2(x11,x61,x[1],x[6]);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:105: Cell has missing pin: \'en\'\nbutterfly b3(x21,x51,x[2],x[5]);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:106: Cell has missing pin: \'en\'\nbutterfly b4(x31,x41,x[3],x[4]);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:109: Cell has missing pin: \'en\'\nbutterfly b5(x02,x32,x01,x31);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:110: Cell has missing pin: \'en\'\nbutterfly b6(x12,x22,x11,x21);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:128: Cell has missing pin: \'en\'\nbutterfly b9(x03,x13,x02,x12);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:137: Cell has missing pin: \'en\'\nbutterfly b11(x43,x53,x42,x52);\n          ^~~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:138: Cell has missing pin: \'en\'\nbutterfly b12(x63,x73,x62,x72);\n          ^~~\n%Error: data/full_repos/permissive/175808891/verilog/dct.v:140: Can\'t find definition of variable: \'sqrt8\'\n                                                              : ... Suggested alternative: \'sqrt2\'\nassign x1=(x03*sqrt8);\n               ^~~~~\n%Error: Exiting due to 1 error(s), 9 warning(s)\n'
module dct(
	input clk,
	input reset,
	input wr,
	input oe,
	input [7:0]data_in,
	input [2:0]add,
	output reg [7:0]data_out
	);	                                        

wire signed [7:0] x01,x11,x21,x31,x41,x51,x61,x71;
wire signed [7:0] x02,x12,x22,x32,x42,x52,x62,x72;
wire signed [7:0] x03,x13,x23,x33,x43,x53,x63,x73,x57,x56;
wire signed [15:0] x04,x14,x24,x34,x44,x54,x64;
wire signed [15:0] x55,x65,x75;
wire signed [31:0] x1,x2;
wire signed [15:0] xx1,xx2,xx3,xx4,xx5,xx6,yy1,yy2,yy3,yy4,yy5,yy6;

wire [7:0] 	c5= 8'd55,
		c6= 8'd38,
		c7= 8'd19;
		
wire [7:0] 	s5=8'd83,
		s6=8'd92,
		s7=8'd98;
				
wire [7:0] sqrt8_inv=8'd35;
wire [15:0] sqrt2=16'b0101_1001_1001_1001;

reg [7:0]x[7:0];


always @( posedge clk) 
begin
if(reset)
x[add]=0;
else if(wr)
x[add]= data_in;
end


butterfly b1(x01,x71,x[0],x[7]);
butterfly b2(x11,x61,x[1],x[6]);
butterfly b3(x21,x51,x[2],x[5]);
butterfly b4(x31,x41,x[3],x[4]);


butterfly b5(x02,x32,x01,x31);
butterfly b6(x12,x22,x11,x21);
signed_mult sm1(.a(x41),.b(c7),.y(xx1));
signed_mult sm2(.a(x41),.b(s7),.y(xx2));
signed_mult sm3(.a(x71),.b(c7),.y(yy1));
signed_mult sm4(.a(x71),.b(s7),.y(yy2));

assign x42=xx1+yy2;
assign x72=-xx2+yy1;

signed_mult sm5(.a(x51),.b(c5),.y(xx3));
signed_mult sm6(.a(x51),.b(s5),.y(xx4));
signed_mult sm7(.a(x61),.b(c5),.y(yy3));
signed_mult sm8(.a(x61),.b(s5),.y(yy4));

assign x52=xx3+yy4;
assign x62=yy3-xx4;


butterfly b9(x03,x13,x02,x12);

signed_mult sm9(.a(x22),.b(c6),.y(xx5));
signed_mult sm10(.a(x22),.b(s6),.y(xx6));
signed_mult sm11(.a(x32),.b(c6),.y(yy5));
signed_mult sm12(.a(x32),.b(s6),.y(yy6));
assign x23=xx5+yy6;
assign x33=-xx6+yy5;

butterfly b11(x43,x53,x42,x52);
butterfly b12(x63,x73,x62,x72);

assign x1=(x03*sqrt8);
assign x04=x1>>16;


signed_mult sm14(.a(x13),.b(sqrt8_inv),.y(x14));


assign x24= (x23>>1);
assign x34 = (x33>>1);
assign x44= (x43>>1);


assign x54 = x53 + x63;
assign x64 = x53 - x63;   
assign x2=(x54*sqrt8);
assign x55=x2>>16;	
assign x56=x55>>2;
assign x57=x56>>4;

signed_mult sm16(.a(x64),.b(sqrt8_inv),.y(x65));



assign x75 = (x73>>1);


always @(add)
begin
if(oe)
case(add)
	3'b000: data_out=x04;
	3'b001: data_out=x44;
	3'b010: data_out=x24;
	3'b011: data_out=x65;
	3'b100: data_out=x14;
	3'b101: data_out=x57;
	3'b110: data_out=x34;
	3'b111: data_out=x75;
	default: data_out=0;
endcase
else
data_out=0;
end
endmodule
module dct(
	input clk,
	input reset,
	input wr,
	input oe,
	input [7:0]data_in,
	input [2:0]add,
	output reg [7:0]data_out
	);
	                                        

wire signed [7:0] x01,x11,x21,x31,x41,x51,x61,x71;
wire signed [7:0] x02,x12,x22,x32,x42,x52,x62,x72;
wire signed [7:0] x03,x13,x23,x33,x43,x53,x63,x73,x57,x56;
wire signed [15:0] x04,x14,x24,x34,x44,x54,x64;
wire signed [15:0] x55,x65,x75;
wire signed [31:0] x1,x2;
wire signed [15:0] xx1,xx2,xx3,xx4,xx5,xx6,yy1,yy2,yy3,yy4,yy5,yy6;

wire [7:0] 	c5= 8'd55,
		c6= 8'd38,
		c7= 8'd19;
		
wire [7:0] 	s5=8'd83,
		s6=8'd92,
		s7=8'd98;
				
wire [7:0] sqrt8_inv=8'd35;
wire [15:0] sqrt2=16'b0101_1001_1001_1001;

reg [7:0]x[7:0];


always @( posedge clk) 
begin
if(reset)
x[add]=0;
else if(wr)
x[add]= data_in;
end


butterfly b1(x01,x71,x[0],x[7]);
butterfly b2(x11,x61,x[1],x[6]);
butterfly b3(x21,x51,x[2],x[5]);
butterfly b4(x31,x41,x[3],x[4]);


butterfly b5(x02,x32,x01,x31);
butterfly b6(x12,x22,x11,x21);
signed_mult sm1(.a(x41),.b(c7),.y(xx1));
signed_mult sm2(.a(x41),.b(s7),.y(xx2));
signed_mult sm3(.a(x71),.b(c7),.y(yy1));
signed_mult sm4(.a(x71),.b(s7),.y(yy2));

assign x42=xx1+yy2;
assign x72=-xx2+yy1;

signed_mult sm5(.a(x51),.b(c5),.y(xx3));
signed_mult sm6(.a(x51),.b(s5),.y(xx4));
signed_mult sm7(.a(x61),.b(c5),.y(yy3));
signed_mult sm8(.a(x61),.b(s5),.y(yy4));

assign x52=xx3+yy4;
assign x62=yy3-xx4;


butterfly b9(x03,x13,x02,x12);

signed_mult sm9(.a(x22),.b(c6),.y(xx5));
signed_mult sm10(.a(x22),.b(s6),.y(xx6));
signed_mult sm11(.a(x32),.b(c6),.y(yy5));
signed_mult sm12(.a(x32),.b(s6),.y(yy6));
assign x23=xx5+yy6;
assign x33=-xx6+yy5;

butterfly b11(x43,x53,x42,x52);
butterfly b12(x63,x73,x62,x72);

assign x1=(x03*sqrt8);
assign x04=x1>>16;


signed_mult sm14(.a(x13),.b(sqrt8_inv),.y(x14));


assign x24= (x23>>1);
assign x34 = (x33>>1);
assign x44= (x43>>1);


assign x54 = x53 + x63;
assign x64 = x53 - x63;   
assign x2=(x54*sqrt8);
assign x55=x2>>16;	
assign x56=x55>>2;
assign x57=x56>>4;

signed_mult sm16(.a(x64),.b(sqrt8_inv),.y(x65));



assign x75 = (x73>>1);


always @(add)
begin
if(oe)
case(add)
	3'b000: data_out=x04;
	3'b001: data_out=x44;
	3'b010: data_out=x24;
	3'b011: data_out=x65;
	3'b100: data_out=x14;
	3'b101: data_out=x57;
	3'b110: data_out=x34;
	3'b111: data_out=x75;
	default: data_out=0;
endcase
else
data_out=0;
end
endmodule