data/full_repos/permissive/143278/ivltests/pr2425055a.v
data/verilator_xmls/658441a6-a953-477f-8f34-5c80536976ba.xml
module main;

  reg [31:0] a, b, c;

  initial begin
    a = 1;
    b = 1;
    b[2] = 1'bx;
    c = a << b;

    if (c != 32'bx) $display("FAILED");
    else $display("PASSED");
  end
endmodule
module main;


  reg [31:0] a, b, c;

  initial begin
    a = 1;
    b = 1;
    b[2] = 1'bx;
    c = a << b;

    if (c != 32'bx) $display("FAILED");
    else $display("PASSED");
  end
endmodule