data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v
 line:70: before: "data_wr_en"
1: b'%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n   #2\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n   #2\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n   #2\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:68: Unsupported: wait statements\n  wait(memory_controll.bus_busy == 0);  \n  ^~~~\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:69: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:73: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:76: Unsupported: wait statements\n  wait(memory_controll.bus_busy == 0);  \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:77: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:81: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:84: Unsupported: wait statements\n  wait(memory_controll.bus_busy == 0);  \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:85: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:88: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:91: Unsupported: wait statements\n  wait(memory_controll.bus_busy == 0);  \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:92: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:95: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:98: Unsupported: wait statements\n  wait(memory_controll.bus_busy == 0);  \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/data_memory_controller_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Error: Exiting due to 13 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module data_memory_controller_tb;
/
	.clk(clk),
	.rst_n(rst_n),
	.data_rd_en(data_rd_en),
	.data_wr_en(data_wr_en),
	.data_addr(data_addr),
	.data_out(data_out),
	.data_in(data_in),

	.dram_dq_in(dram_dq_in),
	.dram_dq_out(dram_dq_out),
	.dram_addr(dram_addr),
	.dram_dqm(dram_dqm),
	.dram_we_n(dram_we_n),
	.dram_cas_n(dram_cas_n),
	.dram_ras_n(dram_ras_n),
	.dram_cs_n(dram_cs_n),
	.dram_ba(dram_ba),
	.dram_clk(dram_clk),
	.dram_cke(dram_cke)
  );

mt48lc8m16a2
  #(
    .data_bits(16),
    .addr_bits(SDRAM_ADDR_WIDTH)
  ) 
  sdram_memory_2  
  (
    .Dq(dram_dq[31:16]),
    .Addr(dram_addr),
    .Ba(dram_ba),
    .Clk(dram_clk),
    .Cke(dram_cke),
    .Cs_n(dram_cs_n),
    .Ras_n(dram_ras_n),
    .Cas_n(dram_cas_n),
    .We_n(dram_we_n),
    .Dqm(dram_dqm)
  );

  mt48lc8m16a2
  #(
    .data_bits(16),
    .addr_bits(SDRAM_ADDR_WIDTH)
  ) 
  sdram_memory_1  
  (
    .Dq(dram_dq[15:0]),
    .Addr(dram_addr),
    .Ba(dram_ba),
    .Clk(dram_clk),
    .Cke(dram_cke),
    .Cs_n(dram_cs_n),
    .Ras_n(dram_ras_n),
    .Cas_n(dram_cas_n),
    .We_n(dram_we_n),
    .Dqm(dram_dqm)
  );
  
endmodule
module data_memory_controller_tb;

/
	.clk(clk),
	.rst_n(rst_n),
	.data_rd_en(data_rd_en),
	.data_wr_en(data_wr_en),
	.data_addr(data_addr),
	.data_out(data_out),
	.data_in(data_in),

	.dram_dq_in(dram_dq_in),
	.dram_dq_out(dram_dq_out),
	.dram_addr(dram_addr),
	.dram_dqm(dram_dqm),
	.dram_we_n(dram_we_n),
	.dram_cas_n(dram_cas_n),
	.dram_ras_n(dram_ras_n),
	.dram_cs_n(dram_cs_n),
	.dram_ba(dram_ba),
	.dram_clk(dram_clk),
	.dram_cke(dram_cke)
  );

mt48lc8m16a2
  #(
    .data_bits(16),
    .addr_bits(SDRAM_ADDR_WIDTH)
  ) 
  sdram_memory_2  
  (
    .Dq(dram_dq[31:16]),
    .Addr(dram_addr),
    .Ba(dram_ba),
    .Clk(dram_clk),
    .Cke(dram_cke),
    .Cs_n(dram_cs_n),
    .Ras_n(dram_ras_n),
    .Cas_n(dram_cas_n),
    .We_n(dram_we_n),
    .Dqm(dram_dqm)
  );

  mt48lc8m16a2
  #(
    .data_bits(16),
    .addr_bits(SDRAM_ADDR_WIDTH)
  ) 
  sdram_memory_1  
  (
    .Dq(dram_dq[15:0]),
    .Addr(dram_addr),
    .Ba(dram_ba),
    .Clk(dram_clk),
    .Cke(dram_cke),
    .Cs_n(dram_cs_n),
    .Ras_n(dram_ras_n),
    .Cas_n(dram_cas_n),
    .We_n(dram_we_n),
    .Dqm(dram_dqm)
  );
  
endmodule