data/full_repos/permissive/220262286/src/alu.v
 line:12: before: ":"
1: b"%Error: data/full_repos/permissive/220262286/src/alu.v:12: Define or directive not defined: '`ALU_OP_AND'\n        `ALU_OP_AND: begin\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220262286/src/alu.v:12: syntax error, unexpected ':', expecting endcase\n        `ALU_OP_AND: begin\n                   ^\n%Error: data/full_repos/permissive/220262286/src/alu.v:15: Define or directive not defined: '`ALU_OP_OR'\n        `ALU_OP_OR: begin\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/220262286/src/alu.v:15: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        `ALU_OP_OR: begin\n                    ^~~~~\n%Error: data/full_repos/permissive/220262286/src/alu.v:18: Define or directive not defined: '`ALU_OP_ADD'\n        `ALU_OP_ADD: begin\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220262286/src/alu.v:18: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        `ALU_OP_ADD: begin\n                     ^~~~~\n%Error: data/full_repos/permissive/220262286/src/alu.v:21: Define or directive not defined: '`ALU_OP_SUB'\n        `ALU_OP_SUB: begin\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220262286/src/alu.v:21: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        `ALU_OP_SUB: begin\n                     ^~~~~\n%Error: data/full_repos/permissive/220262286/src/alu.v:24: Define or directive not defined: '`ALU_OP_SLT'\n        `ALU_OP_SLT: begin\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220262286/src/alu.v:24: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        `ALU_OP_SLT: begin\n                     ^~~~~\n%Error: Cannot continue\n"
module ALU(
    input [2:0] op,
    input [31:0] a,
    input [31:0] b,
    output reg [31:0] x,
    output zero
);

assign zero = (x == 32'h0) ? 1 : 0;
always @* begin
    case(op)
        `ALU_OP_AND: begin
            x = a & b;
        end
        `ALU_OP_OR: begin
            x = a | b;
        end
        `ALU_OP_ADD: begin
            x = a + b;
        end
        `ALU_OP_SUB: begin
            x = a - b;
        end
        `ALU_OP_SLT: begin
            if(a < b) begin
                x = 31'b1;
            end
            else begin
                x = 31'b0;
            end
        end
        default: begin
            x = 3'bx;
        end
    endcase
end

endmodule
module ALU(
    input [2:0] op,
    input [31:0] a,
    input [31:0] b,
    output reg [31:0] x,
    output zero
);


assign zero = (x == 32'h0) ? 1 : 0;
always @* begin
    case(op)
        `ALU_OP_AND: begin
            x = a & b;
        end
        `ALU_OP_OR: begin
            x = a | b;
        end
        `ALU_OP_ADD: begin
            x = a + b;
        end
        `ALU_OP_SUB: begin
            x = a - b;
        end
        `ALU_OP_SLT: begin
            if(a < b) begin
                x = 31'b1;
            end
            else begin
                x = 31'b0;
            end
        end
        default: begin
            x = 3'bx;
        end
    endcase
end

endmodule