data/full_repos/permissive/123339956/Labtest_1/seqgen.v
 line:20: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:10: Unsupported: Ignoring delay on this delayed statement.\n always #10 clock = ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #20 reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #40 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #100 reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #40 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #800 \n  ^\n%Error: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:25: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("seqgen.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:26: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_seqgen();

	reg reset,clock;
	wire [3:0] out;

	seqgen uut(out,reset,clock);

	always #10 clock = ~clock;
		
	initial
		begin
		clock = 0; reset=0;
		#20 reset = 1;
		#40 reset = 0;
		#100 reset = 1;
		#40 reset = 0;
		#800 
		$stop;
		end
			
	initial
		begin
		$dumpfile("seqgen.vcd");
		$dumpvars;
		end
			
endmodule
module tb_seqgen();


	reg reset,clock;
	wire [3:0] out;

	seqgen uut(out,reset,clock);

	always #10 clock = ~clock;
		
	initial
		begin
		clock = 0; reset=0;
		#20 reset = 1;
		#40 reset = 0;
		#100 reset = 1;
		#40 reset = 0;
		#800 
		$stop;
		end
			
	initial
		begin
		$dumpfile("seqgen.vcd");
		$dumpvars;
		end
			
endmodule