data/full_repos/permissive/129155059/05-yosys_register/synth.v
1: b'%Error: data/full_repos/permissive/129155059/05-yosys_register/synth.v:1: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/05-yosys_register,data/full_repos/permissive/129155059/cmos_cells.v\n             data/full_repos/permissive/129155059/05-yosys_register,data/full_repos/permissive/129155059/cmos_cells.v.v\n             data/full_repos/permissive/129155059/05-yosys_register,data/full_repos/permissive/129155059/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: Exiting due to 1 error(s)\n'
module registro_yosys(Q, S_OUT, D, MODO, CLK, ENB, DIR, S_IN);
  wire [3:0] _000_;
  wire _001_;
  wire _002_;
  wire _003_;
  wire _004_;
  wire _005_;
  wire _006_;
  wire _007_;
  wire _008_;
  wire _009_;
  wire _010_;
  wire _011_;
  wire _012_;
  wire _013_;
  wire _014_;
  wire _015_;
  wire _016_;
  wire _017_;
  wire _018_;
  wire _019_;
  wire _020_;
  wire _021_;
  wire _022_;
  wire _023_;
  wire _024_;
  wire _025_;
  wire _026_;
  wire _027_;
  wire _028_;
  wire _029_;
  wire _030_;
  wire _031_;
  wire _032_;
  wire _033_;
  wire _034_;
  wire _035_;
  wire _036_;
  wire _037_;
  wire _038_;
  wire _039_;
  wire _040_;
  wire _041_;
  wire _042_;
  wire _043_;
  wire _044_;
  wire _045_;
  wire _046_;
  wire _047_;
  wire _048_;
  wire _049_;
  wire _050_;
  wire _051_;
  wire _052_;
  input CLK;
  input [3:0] D;
  input DIR;
  input ENB;
  input [1:0] MODO;
  output [3:0] Q;
  reg [3:0] Q;
  input S_IN;
  output S_OUT;
  reg S_OUT;
  NOT _053_ (
    .A(MODO[1]),
    .Y(_002_)
  );
  NOT _054_ (
    .A(MODO[0]),
    .Y(_003_)
  );
  NOT _055_ (
    .A(DIR),
    .Y(_004_)
  );
  NOT _056_ (
    .A(ENB),
    .Y(_005_)
  );
  NOR _057_ (
    .A(Q[0]),
    .B(ENB),
    .Y(_006_)
  );
  NOR _058_ (
    .A(MODO[1]),
    .B(_003_),
    .Y(_007_)
  );
  NAND _059_ (
    .A(Q[1]),
    .B(DIR),
    .Y(_008_)
  );
  NAND _060_ (
    .A(_004_),
    .B(Q[3]),
    .Y(_009_)
  );
  NAND _061_ (
    .A(_008_),
    .B(_009_),
    .Y(_010_)
  );
  NAND _062_ (
    .A(_007_),
    .B(_010_),
    .Y(_011_)
  );
  NOR _063_ (
    .A(MODO[1]),
    .B(MODO[0]),
    .Y(_012_)
  );
  NAND _064_ (
    .A(S_IN),
    .B(_004_),
    .Y(_013_)
  );
  NAND _065_ (
    .A(_008_),
    .B(_013_),
    .Y(_014_)
  );
  NAND _066_ (
    .A(_012_),
    .B(_014_),
    .Y(_015_)
  );
  NAND _067_ (
    .A(MODO[1]),
    .B(D[0]),
    .Y(_016_)
  );
  NAND _068_ (
    .A(_011_),
    .B(_016_),
    .Y(_017_)
  );
  NAND _069_ (
    .A(ENB),
    .B(_015_),
    .Y(_018_)
  );
  NOR _070_ (
    .A(_017_),
    .B(_018_),
    .Y(_019_)
  );
  NOR _071_ (
    .A(_006_),
    .B(_019_),
    .Y(_000_[0])
  );
  NAND _072_ (
    .A(MODO[1]),
    .B(D[1]),
    .Y(_020_)
  );
  NAND _073_ (
    .A(_004_),
    .B(Q[0]),
    .Y(_021_)
  );
  NAND _074_ (
    .A(DIR),
    .B(Q[2]),
    .Y(_022_)
  );
  NAND _075_ (
    .A(_021_),
    .B(_022_),
    .Y(_023_)
  );
  NAND _076_ (
    .A(_002_),
    .B(_023_),
    .Y(_024_)
  );
  NAND _077_ (
    .A(_020_),
    .B(_024_),
    .Y(_025_)
  );
  NAND _078_ (
    .A(ENB),
    .B(_025_),
    .Y(_026_)
  );
  NAND _079_ (
    .A(Q[1]),
    .B(_005_),
    .Y(_027_)
  );
  NAND _080_ (
    .A(_026_),
    .B(_027_),
    .Y(_000_[1])
  );
  NAND _081_ (
    .A(MODO[1]),
    .B(D[2]),
    .Y(_028_)
  );
  NAND _082_ (
    .A(Q[1]),
    .B(_004_),
    .Y(_029_)
  );
  NAND _083_ (
    .A(DIR),
    .B(Q[3]),
    .Y(_030_)
  );
  NAND _084_ (
    .A(_029_),
    .B(_030_),
    .Y(_031_)
  );
  NAND _085_ (
    .A(_002_),
    .B(_031_),
    .Y(_032_)
  );
  NAND _086_ (
    .A(_028_),
    .B(_032_),
    .Y(_033_)
  );
  NAND _087_ (
    .A(ENB),
    .B(_033_),
    .Y(_034_)
  );
  NAND _088_ (
    .A(Q[2]),
    .B(_005_),
    .Y(_035_)
  );
  NAND _089_ (
    .A(_034_),
    .B(_035_),
    .Y(_000_[2])
  );
  NOR _090_ (
    .A(Q[3]),
    .B(ENB),
    .Y(_036_)
  );
  NAND _091_ (
    .A(_004_),
    .B(Q[2]),
    .Y(_037_)
  );
  NAND _092_ (
    .A(DIR),
    .B(Q[0]),
    .Y(_038_)
  );
  NAND _093_ (
    .A(_037_),
    .B(_038_),
    .Y(_039_)
  );
  NAND _094_ (
    .A(_007_),
    .B(_039_),
    .Y(_040_)
  );
  NAND _095_ (
    .A(S_IN),
    .B(DIR),
    .Y(_041_)
  );
  NAND _096_ (
    .A(_037_),
    .B(_041_),
    .Y(_042_)
  );
  NAND _097_ (
    .A(_012_),
    .B(_042_),
    .Y(_043_)
  );
  NAND _098_ (
    .A(MODO[1]),
    .B(D[3]),
    .Y(_044_)
  );
  NAND _099_ (
    .A(_040_),
    .B(_044_),
    .Y(_045_)
  );
  NAND _100_ (
    .A(ENB),
    .B(_043_),
    .Y(_046_)
  );
  NOR _101_ (
    .A(_045_),
    .B(_046_),
    .Y(_047_)
  );
  NOR _102_ (
    .A(_036_),
    .B(_047_),
    .Y(_000_[3])
  );
  NAND _103_ (
    .A(_009_),
    .B(_038_),
    .Y(_048_)
  );
  NAND _104_ (
    .A(_012_),
    .B(_048_),
    .Y(_049_)
  );
  NAND _105_ (
    .A(ENB),
    .B(_049_),
    .Y(_050_)
  );
  NOT _106_ (
    .A(_050_),
    .Y(_051_)
  );
  NOR _107_ (
    .A(ENB),
    .B(S_OUT),
    .Y(_052_)
  );
  NOR _108_ (
    .A(_051_),
    .B(_052_),
    .Y(_001_)
  );
  always @(posedge CLK)
      Q[0] <= _000_[0];
  always @(posedge CLK)
      Q[1] <= _000_[1];
  always @(posedge CLK)
      Q[2] <= _000_[2];
  always @(posedge CLK)
      Q[3] <= _000_[3];
  always @(posedge CLK)
      S_OUT <= _001_;

parameter PwrC = 3;
always @(posedge Q or negedge Q) begin
  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;
end
endmodule
module registro_yosys(Q, S_OUT, D, MODO, CLK, ENB, DIR, S_IN);

  wire [3:0] _000_;
  wire _001_;
  wire _002_;
  wire _003_;
  wire _004_;
  wire _005_;
  wire _006_;
  wire _007_;
  wire _008_;
  wire _009_;
  wire _010_;
  wire _011_;
  wire _012_;
  wire _013_;
  wire _014_;
  wire _015_;
  wire _016_;
  wire _017_;
  wire _018_;
  wire _019_;
  wire _020_;
  wire _021_;
  wire _022_;
  wire _023_;
  wire _024_;
  wire _025_;
  wire _026_;
  wire _027_;
  wire _028_;
  wire _029_;
  wire _030_;
  wire _031_;
  wire _032_;
  wire _033_;
  wire _034_;
  wire _035_;
  wire _036_;
  wire _037_;
  wire _038_;
  wire _039_;
  wire _040_;
  wire _041_;
  wire _042_;
  wire _043_;
  wire _044_;
  wire _045_;
  wire _046_;
  wire _047_;
  wire _048_;
  wire _049_;
  wire _050_;
  wire _051_;
  wire _052_;
  input CLK;
  input [3:0] D;
  input DIR;
  input ENB;
  input [1:0] MODO;
  output [3:0] Q;
  reg [3:0] Q;
  input S_IN;
  output S_OUT;
  reg S_OUT;
  NOT _053_ (
    .A(MODO[1]),
    .Y(_002_)
  );
  NOT _054_ (
    .A(MODO[0]),
    .Y(_003_)
  );
  NOT _055_ (
    .A(DIR),
    .Y(_004_)
  );
  NOT _056_ (
    .A(ENB),
    .Y(_005_)
  );
  NOR _057_ (
    .A(Q[0]),
    .B(ENB),
    .Y(_006_)
  );
  NOR _058_ (
    .A(MODO[1]),
    .B(_003_),
    .Y(_007_)
  );
  NAND _059_ (
    .A(Q[1]),
    .B(DIR),
    .Y(_008_)
  );
  NAND _060_ (
    .A(_004_),
    .B(Q[3]),
    .Y(_009_)
  );
  NAND _061_ (
    .A(_008_),
    .B(_009_),
    .Y(_010_)
  );
  NAND _062_ (
    .A(_007_),
    .B(_010_),
    .Y(_011_)
  );
  NOR _063_ (
    .A(MODO[1]),
    .B(MODO[0]),
    .Y(_012_)
  );
  NAND _064_ (
    .A(S_IN),
    .B(_004_),
    .Y(_013_)
  );
  NAND _065_ (
    .A(_008_),
    .B(_013_),
    .Y(_014_)
  );
  NAND _066_ (
    .A(_012_),
    .B(_014_),
    .Y(_015_)
  );
  NAND _067_ (
    .A(MODO[1]),
    .B(D[0]),
    .Y(_016_)
  );
  NAND _068_ (
    .A(_011_),
    .B(_016_),
    .Y(_017_)
  );
  NAND _069_ (
    .A(ENB),
    .B(_015_),
    .Y(_018_)
  );
  NOR _070_ (
    .A(_017_),
    .B(_018_),
    .Y(_019_)
  );
  NOR _071_ (
    .A(_006_),
    .B(_019_),
    .Y(_000_[0])
  );
  NAND _072_ (
    .A(MODO[1]),
    .B(D[1]),
    .Y(_020_)
  );
  NAND _073_ (
    .A(_004_),
    .B(Q[0]),
    .Y(_021_)
  );
  NAND _074_ (
    .A(DIR),
    .B(Q[2]),
    .Y(_022_)
  );
  NAND _075_ (
    .A(_021_),
    .B(_022_),
    .Y(_023_)
  );
  NAND _076_ (
    .A(_002_),
    .B(_023_),
    .Y(_024_)
  );
  NAND _077_ (
    .A(_020_),
    .B(_024_),
    .Y(_025_)
  );
  NAND _078_ (
    .A(ENB),
    .B(_025_),
    .Y(_026_)
  );
  NAND _079_ (
    .A(Q[1]),
    .B(_005_),
    .Y(_027_)
  );
  NAND _080_ (
    .A(_026_),
    .B(_027_),
    .Y(_000_[1])
  );
  NAND _081_ (
    .A(MODO[1]),
    .B(D[2]),
    .Y(_028_)
  );
  NAND _082_ (
    .A(Q[1]),
    .B(_004_),
    .Y(_029_)
  );
  NAND _083_ (
    .A(DIR),
    .B(Q[3]),
    .Y(_030_)
  );
  NAND _084_ (
    .A(_029_),
    .B(_030_),
    .Y(_031_)
  );
  NAND _085_ (
    .A(_002_),
    .B(_031_),
    .Y(_032_)
  );
  NAND _086_ (
    .A(_028_),
    .B(_032_),
    .Y(_033_)
  );
  NAND _087_ (
    .A(ENB),
    .B(_033_),
    .Y(_034_)
  );
  NAND _088_ (
    .A(Q[2]),
    .B(_005_),
    .Y(_035_)
  );
  NAND _089_ (
    .A(_034_),
    .B(_035_),
    .Y(_000_[2])
  );
  NOR _090_ (
    .A(Q[3]),
    .B(ENB),
    .Y(_036_)
  );
  NAND _091_ (
    .A(_004_),
    .B(Q[2]),
    .Y(_037_)
  );
  NAND _092_ (
    .A(DIR),
    .B(Q[0]),
    .Y(_038_)
  );
  NAND _093_ (
    .A(_037_),
    .B(_038_),
    .Y(_039_)
  );
  NAND _094_ (
    .A(_007_),
    .B(_039_),
    .Y(_040_)
  );
  NAND _095_ (
    .A(S_IN),
    .B(DIR),
    .Y(_041_)
  );
  NAND _096_ (
    .A(_037_),
    .B(_041_),
    .Y(_042_)
  );
  NAND _097_ (
    .A(_012_),
    .B(_042_),
    .Y(_043_)
  );
  NAND _098_ (
    .A(MODO[1]),
    .B(D[3]),
    .Y(_044_)
  );
  NAND _099_ (
    .A(_040_),
    .B(_044_),
    .Y(_045_)
  );
  NAND _100_ (
    .A(ENB),
    .B(_043_),
    .Y(_046_)
  );
  NOR _101_ (
    .A(_045_),
    .B(_046_),
    .Y(_047_)
  );
  NOR _102_ (
    .A(_036_),
    .B(_047_),
    .Y(_000_[3])
  );
  NAND _103_ (
    .A(_009_),
    .B(_038_),
    .Y(_048_)
  );
  NAND _104_ (
    .A(_012_),
    .B(_048_),
    .Y(_049_)
  );
  NAND _105_ (
    .A(ENB),
    .B(_049_),
    .Y(_050_)
  );
  NOT _106_ (
    .A(_050_),
    .Y(_051_)
  );
  NOR _107_ (
    .A(ENB),
    .B(S_OUT),
    .Y(_052_)
  );
  NOR _108_ (
    .A(_051_),
    .B(_052_),
    .Y(_001_)
  );
  always @(posedge CLK)
      Q[0] <= _000_[0];
  always @(posedge CLK)
      Q[1] <= _000_[1];
  always @(posedge CLK)
      Q[2] <= _000_[2];
  always @(posedge CLK)
      Q[3] <= _000_[3];
  always @(posedge CLK)
      S_OUT <= _001_;

parameter PwrC = 3;
always @(posedge Q or negedge Q) begin
  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;
end
endmodule