data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_camera_if.sv
Syntax Error
1: b'%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_camera_if.sv:62: Cannot find include file: camera_model.sv\n    `include "camera_model.sv" \n             ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/204736068/SoM/RTL/vision/tb,data/full_repos/permissive/204736068/camera_model.sv\n             data/full_repos/permissive/204736068/SoM/RTL/vision/tb,data/full_repos/permissive/204736068/camera_model.sv.v\n             data/full_repos/permissive/204736068/SoM/RTL/vision/tb,data/full_repos/permissive/204736068/camera_model.sv.sv\n             camera_model.sv\n             camera_model.sv.v\n             camera_model.sv.sv\n             obj_dir/camera_model.sv\n             obj_dir/camera_model.sv.v\n             obj_dir/camera_model.sv.sv\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_camera_if.sv:72: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_camera_if.sv:73: Unsupported: Ignoring delay on this delayed statement.\n    always #50 pixel_clk = ~pixel_clk;\n           ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_camera_if.sv:77: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_camera_if.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_camera_if.sv:78: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_camera_if);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_camera_if.sv:80: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_camera_if.sv:82: syntax error, unexpected \'@\'\n        repeat (5) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_camera_if.sv:85: syntax error, unexpected \'@\'\n        repeat (5) @(posedge clk);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_camera_if.sv:88: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module tb_camera_if;


    parameter ROWS = 12;
    parameter COLS = 16;
        
    logic              clk=0;
    logic              rst;


    logic       pixel_clk = 0;
    logic [7:0] pixel_dat    ;
    logic       frame_vld    ;
    logic       line_vld     ;


    logic       sof  ;
    logic       eof  ;
    logic [7:0] o_dat;
    logic       o_vld;

    `include "camera_model.sv"


    logic [$clog2(COLS):0] num_rows;
    logic [$clog2(ROWS):0] num_cols;


    camera_if #(.COLS(COLS), .ROWS(ROWS)) u_camera_if (.*);
    

    always #10 clk = ~clk;
    always #50 pixel_clk = ~pixel_clk;

    initial begin
        $display("Starting simulation");
        $dumpfile("tb_camera_if.vcd");
        $dumpvars(0, tb_camera_if);
         
        #100;
        rst = 1;
        repeat (5) @(posedge clk);
        rst = 0;

        repeat (5) @(posedge clk);
        send_incr_frame;
        
        #1000;
        $display("Number of rows: %d", num_rows);
        $display("Number of cols: %d", num_cols);
        $display("Ending simulation");
        
        $finish;
    end
    
endmodule
module tb_camera_if;



    parameter ROWS = 12;
    parameter COLS = 16;
        
    logic              clk=0;
    logic              rst;


    logic       pixel_clk = 0;
    logic [7:0] pixel_dat    ;
    logic       frame_vld    ;
    logic       line_vld     ;


    logic       sof  ;
    logic       eof  ;
    logic [7:0] o_dat;
    logic       o_vld;

    `include "camera_model.sv"


    logic [$clog2(COLS):0] num_rows;
    logic [$clog2(ROWS):0] num_cols;


    camera_if #(.COLS(COLS), .ROWS(ROWS)) u_camera_if (.*);
    

    always #10 clk = ~clk;
    always #50 pixel_clk = ~pixel_clk;

    initial begin
        $display("Starting simulation");
        $dumpfile("tb_camera_if.vcd");
        $dumpvars(0, tb_camera_if);
         
        #100;
        rst = 1;
        repeat (5) @(posedge clk);
        rst = 0;

        repeat (5) @(posedge clk);
        send_incr_frame;
        
        #1000;
        $display("Number of rows: %d", num_rows);
        $display("Number of cols: %d", num_cols);
        $display("Ending simulation");
        
        $finish;
    end
    
endmodule