data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/top.sv
'utf-8' codec can't decode byte 0xa9 in position 185: invalid start byte
1: b'%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/top.sv:24: Cannot find include file: ../sonic_custom_avalon_master.v\n`include "../sonic_custom_avalon_master.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic,data/full_repos/permissive/18477150/../sonic_custom_avalon_master.v\n             data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic,data/full_repos/permissive/18477150/../sonic_custom_avalon_master.v.v\n             data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic,data/full_repos/permissive/18477150/../sonic_custom_avalon_master.v.sv\n             ../sonic_custom_avalon_master.v\n             ../sonic_custom_avalon_master.v.v\n             ../sonic_custom_avalon_master.v.sv\n             obj_dir/../sonic_custom_avalon_master.v\n             obj_dir/../sonic_custom_avalon_master.v.v\n             obj_dir/../sonic_custom_avalon_master.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/top.sv:143: Unsupported: Ignoring delay on this delayed statement.\nalways #4 clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module top;
  
timeunit 1ns; timeprecision 1ps;

parameter DATA_WIDTH = 32;
parameter ADDRESS_WIDTH = 6;

reg clk;
reg reset;

wire control_mode;
wire control_fixed_location;
wire control_go;
wire control_done;
wire control_early_done;

wire [ADDRESS_WIDTH-1:0] control_base;
wire [ADDRESS_WIDTH-1:0] control_length;

wire user_read_buffer;
wire user_write_buffer;
wire [DATA_WIDTH-1:0] user_buffer_input_data;
wire [DATA_WIDTH-1:0] user_buffer_output_data;
wire user_data_available;
wire user_buffer_full;

wire [ADDRESS_WIDTH-1:0] master_address;
wire master_read;
wire master_write;
wire [DATA_WIDTH-1:0] master_readdata;
wire master_readdatavalid;
wire [DATA_WIDTH-1:0] master_writedata;

wire mdc;
wire mdio_in;
wire mdio_out;
wire mdio_oen;


sonic_custom_avalon_master  _sonic_custom_avalon_master (
	.clk(clk),
	.reset(reset),

	.control_mode(control_mode),
	.control_fixed_location(control_fixed_location),
	.control_base(control_base),
	.control_length(control_length),
	.control_go(control_go),
	.control_done(control_done),
	.control_early_done(control_early_done),

	.user_read_buffer(user_read_buffer),
	.user_write_buffer(user_write_buffer),
	.user_buffer_input_data(user_buffer_input_data),
	.user_buffer_output_data(user_buffer_output_data),
	.user_data_available(user_data_available),
	.user_buffer_full(user_buffer_full),
	
	.master_address(master_address),
	.master_read(master_read),
	.master_write(master_write),
	.master_readdata(master_readdata),
	.master_readdatavalid(master_readdatavalid),
	.master_writedata(master_writedata),
	.master_waitrequest(master_waitrequest)
	);

sonic_eth_mdio mdio(
	.clk(clk),
	.reset(reset),

	.csr_read(master_read),
	.csr_write(master_write),
	.csr_address(master_address),
	.csr_writedata(master_writedata),
	.csr_readdata(master_readdata),
	.csr_waitrequest(master_waitrequest),

	.mdc(mdc),
	.mdio_in(mdio_in),
	.mdio_out(mdio_out),
	.mdio_oen(mdio_oen)
	);


test_sonic_custom_avalon_master test(                                                    
	.clk(clk),
	.reset(reset),

	.control_mode(control_mode),
	.control_fixed_location(control_fixed_location),
	.control_base(control_base),
	.control_length(control_length),
	.control_go(control_go),
	.control_done(control_done),
	.control_early_done(control_early_done),

	.user_read_buffer(user_read_buffer),
	.user_write_buffer(user_write_buffer),
	.user_buffer_input_data(user_buffer_input_data),
	.user_buffer_output_data(user_buffer_output_data),
	.user_data_available(user_data_available),
	.user_buffer_full(user_buffer_full),
	
	.mdc(mdc),
	.mdio_in(mdio_in),
	.mdio_out(mdio_out),
	.mdio_oen(mdio_oen)
	);


initial begin
  clk <= 1'b1;
end


always #4 clk <= ~clk;

endmodule
module top;

  
timeunit 1ns; timeprecision 1ps;

parameter DATA_WIDTH = 32;
parameter ADDRESS_WIDTH = 6;

reg clk;
reg reset;

wire control_mode;
wire control_fixed_location;
wire control_go;
wire control_done;
wire control_early_done;

wire [ADDRESS_WIDTH-1:0] control_base;
wire [ADDRESS_WIDTH-1:0] control_length;

wire user_read_buffer;
wire user_write_buffer;
wire [DATA_WIDTH-1:0] user_buffer_input_data;
wire [DATA_WIDTH-1:0] user_buffer_output_data;
wire user_data_available;
wire user_buffer_full;

wire [ADDRESS_WIDTH-1:0] master_address;
wire master_read;
wire master_write;
wire [DATA_WIDTH-1:0] master_readdata;
wire master_readdatavalid;
wire [DATA_WIDTH-1:0] master_writedata;

wire mdc;
wire mdio_in;
wire mdio_out;
wire mdio_oen;


sonic_custom_avalon_master  _sonic_custom_avalon_master (
	.clk(clk),
	.reset(reset),

	.control_mode(control_mode),
	.control_fixed_location(control_fixed_location),
	.control_base(control_base),
	.control_length(control_length),
	.control_go(control_go),
	.control_done(control_done),
	.control_early_done(control_early_done),

	.user_read_buffer(user_read_buffer),
	.user_write_buffer(user_write_buffer),
	.user_buffer_input_data(user_buffer_input_data),
	.user_buffer_output_data(user_buffer_output_data),
	.user_data_available(user_data_available),
	.user_buffer_full(user_buffer_full),
	
	.master_address(master_address),
	.master_read(master_read),
	.master_write(master_write),
	.master_readdata(master_readdata),
	.master_readdatavalid(master_readdatavalid),
	.master_writedata(master_writedata),
	.master_waitrequest(master_waitrequest)
	);

sonic_eth_mdio mdio(
	.clk(clk),
	.reset(reset),

	.csr_read(master_read),
	.csr_write(master_write),
	.csr_address(master_address),
	.csr_writedata(master_writedata),
	.csr_readdata(master_readdata),
	.csr_waitrequest(master_waitrequest),

	.mdc(mdc),
	.mdio_in(mdio_in),
	.mdio_out(mdio_out),
	.mdio_oen(mdio_oen)
	);


test_sonic_custom_avalon_master test(                                                    
	.clk(clk),
	.reset(reset),

	.control_mode(control_mode),
	.control_fixed_location(control_fixed_location),
	.control_base(control_base),
	.control_length(control_length),
	.control_go(control_go),
	.control_done(control_done),
	.control_early_done(control_early_done),

	.user_read_buffer(user_read_buffer),
	.user_write_buffer(user_write_buffer),
	.user_buffer_input_data(user_buffer_input_data),
	.user_buffer_output_data(user_buffer_output_data),
	.user_data_available(user_data_available),
	.user_buffer_full(user_buffer_full),
	
	.mdc(mdc),
	.mdio_in(mdio_in),
	.mdio_out(mdio_out),
	.mdio_oen(mdio_oen)
	);


initial begin
  clk <= 1'b1;
end


always #4 clk <= ~clk;

endmodule