data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sources_1/new/RegFile.v
1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n        ... Looked in:\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new/RegFile.v\n%Error: Exiting due to 3 error(s)\n'
module RegFile(
    input clk,

    input RegWre,
    input [9:0] ReadReg1,ReadReg2,WriteReg,
    input [31:0] WriteData,
    input [31:0] ReadData1,ReadData2 
    );
    
    reg [31:0] regFile [1:1023];
    integer i;
    assign ReadData1 = (ReadReg1 == 0)? 0: regFile[ReadReg1];
    assign ReadData2 = (ReadReg2 == 0)? 0: regFile[ReadReg2];
    always@(posedge clk)
    begin






        if(RegWre == 1 && WriteReg != 0)
            regFile[WriteReg] <= WriteData;
    end
endmodule
module RegFile(
    input clk,

    input RegWre,
    input [9:0] ReadReg1,ReadReg2,WriteReg,
    input [31:0] WriteData,
    input [31:0] ReadData1,ReadData2 
    );

    
    reg [31:0] regFile [1:1023];
    integer i;
    assign ReadData1 = (ReadReg1 == 0)? 0: regFile[ReadReg1];
    assign ReadData2 = (ReadReg2 == 0)? 0: regFile[ReadReg2];
    always@(posedge clk)
    begin






        if(RegWre == 1 && WriteReg != 0)
            regFile[WriteReg] <= WriteData;
    end
endmodule