data/full_repos/permissive/146618947/valid_tarea6/mux.v
data/verilator_xmls/3144a71f-1f6b-44c0-82a2-a5b970268ad6.xml
module mux (
            input            clk,
            input            reset_L,
            input [3:0]      data_0,
            input [3:0]      data_1,
            input            valid_0,
            input            valid_1,
            output reg valid_out,
            output reg [3:0] data_out
            );

   reg                       selector;

   initial
     begin
        data_out = 0;
        selector = 0;
     end

   always @ (*)
     begin

        if (reset_L) begin
           if (selector) begin
              valid_out = valid_0;
           end else begin
              valid_out = valid_1;
           end
        end else begin
           valid_out = 0;
        end
     end

   always @ (posedge clk)
     begin

         if (!reset_L) begin

           data_out <= 0;
           selector <= 0;
        end

        if (reset_L) begin
           selector <= ~selector;
           if (selector) begin
              if (valid_0) begin
                 data_out <= data_0;
              end
           end else begin
              if (valid_1) begin
                 data_out <= data_1;
              end
           end
        end

     end

   endmodule
module mux (
            input            clk,
            input            reset_L,
            input [3:0]      data_0,
            input [3:0]      data_1,
            input            valid_0,
            input            valid_1,
            output reg valid_out,
            output reg [3:0] data_out
            );


   reg                       selector;

   initial
     begin
        data_out = 0;
        selector = 0;
     end

   always @ (*)
     begin

        if (reset_L) begin
           if (selector) begin
              valid_out = valid_0;
           end else begin
              valid_out = valid_1;
           end
        end else begin
           valid_out = 0;
        end
     end

   always @ (posedge clk)
     begin

         if (!reset_L) begin

           data_out <= 0;
           selector <= 0;
        end

        if (reset_L) begin
           selector <= ~selector;
           if (selector) begin
              if (valid_0) begin
                 data_out <= data_0;
              end
           end else begin
              if (valid_1) begin
                 data_out <= data_1;
              end
           end
        end

     end

   endmodule