data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v
 line:133: before: "("
1: b'%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:1: Cannot find include file: definitions.v\n`include"definitions.v" \n        ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/02-shift_register,data/full_repos/permissive/129155059/definitions.v\n             data/full_repos/permissive/129155059/02-shift_register,data/full_repos/permissive/129155059/definitions.v.v\n             data/full_repos/permissive/129155059/02-shift_register,data/full_repos/permissive/129155059/definitions.v.sv\n             definitions.v\n             definitions.v.v\n             definitions.v.sv\n             obj_dir/definitions.v\n             obj_dir/definitions.v.v\n             obj_dir/definitions.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n      repeat(4) #5 CLK = ~CLK;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n      forever #5 CLK = ~CLK;\n              ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:130: syntax error, unexpected \'@\'\n      @(posedge ENB);\n      ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:132: Define or directive not defined: \'`LOAD\'\n      MODO = `LOAD;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:132: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `LOAD;\n                  ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:135: syntax error, unexpected \'@\'\n      repeat(15) @(posedge CLK);\n                 ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:139: Define or directive not defined: \'`PUSH\'\n      MODO = `PUSH;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:139: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `PUSH;\n                  ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:140: syntax error, unexpected \'@\'\n      repeat(35) @(posedge CLK);\n                 ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:144: Define or directive not defined: \'`PUSH\'\n      MODO = `PUSH;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:144: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `PUSH;\n                  ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:145: syntax error, unexpected \'@\'\n      repeat(35) @(posedge CLK);\n                 ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:148: Define or directive not defined: \'`LOAD\'\n      MODO = `LOAD;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:148: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `LOAD;\n                  ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:149: syntax error, unexpected \'@\'\n      repeat(3) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:152: Define or directive not defined: \'`CYCLE\'\n      MODO = `CYCLE;\n             ^~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:152: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `CYCLE;\n                   ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:153: syntax error, unexpected \'@\'\n      repeat(35) @(posedge CLK);\n                 ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:156: Define or directive not defined: \'`LOAD\'\n      MODO = `LOAD;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:156: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `LOAD;\n                  ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:157: syntax error, unexpected \'@\'\n      repeat(3) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:160: Define or directive not defined: \'`CYCLE\'\n      MODO = `CYCLE;\n             ^~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:160: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `CYCLE;\n                   ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:161: syntax error, unexpected \'@\'\n      repeat(35) @(posedge CLK);\n                 ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:166: Unsupported or unknown PLI call: $monitor\n        $monitor("At time %t, Q = %h (%0d), S_OUT = %h (%0d)",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:170: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("registro32.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32_tb.v:171: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, registro32_tb);\n        ^~~~~~~~~\n%Error: Exiting due to 26 error(s), 2 warning(s)\n'
module registro32_tb();


  parameter  WIDTH = 32;


    reg ENB;
    reg DIR;
    reg S_IN;
    reg [1 : 0]          MODO;
    reg [WIDTH - 1 : 0]  D;
    reg CLK;

    wire [WIDTH - 1 : 0] Q;
    wire                 S_OUT;


    wire [7 : 1]         S_OUT_IN;


    registro #(4) r0
    (
      .Q(Q[3:0]),
      .S_OUT(S_OUT_IN[1]),
      .D(D[3:0]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_IN)
      );

    registro #(4) r1
    (
      .Q(Q[7:4]),
      .S_OUT(S_OUT_IN[2]),
      .D(D[7:4]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[1])
      );

    registro #(4) r2
    (
      .Q(Q[11:8]),
      .S_OUT(S_OUT_IN[3]),
      .D(D[11:8]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[2])
      );

    registro #(4) r3
    (
      .Q(Q[15:12]),
      .S_OUT(S_OUT_IN[4]),
      .D(D[15:12]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[3])
      );

    registro #(4) r4
    (
      .Q(Q[19:16]),
      .S_OUT(S_OUT_IN[5]),
      .D(D[19:16]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[4])
      );

    registro #(4) r5
    (
      .Q(Q[23:20]),
      .S_OUT(S_OUT_IN[6]),
      .D(D[23:20]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[5])
      );

    registro #(4) r6
    (
      .Q(Q[27:24]),
      .S_OUT(S_OUT_IN[7]),
      .D(D[27:24]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[6])
      );

    registro #(4) r7
    (
      .Q(Q[WIDTH - 1: 28]),
      .S_OUT(S_OUT),
      .D(D[WIDTH - 1: 28]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[7])
      );



    initial begin
      CLK = 1'b0;
      ENB = 1'b0;
      repeat(4) #5 CLK = ~CLK;
      ENB = 1'b1;
      forever #5 CLK = ~CLK;
    end

    initial begin

      @(posedge ENB);
      D = 32'b11011101110111011101110111011101;
      MODO = `LOAD;
      S_IN = 1'b0;
      DIR = 0;
      repeat(15) @(posedge CLK);

      S_IN = 1'b0;
      DIR = 0;
      MODO = `PUSH;
      repeat(35) @(posedge CLK);

      S_IN = 1'b1;
      DIR = 1;
      MODO = `PUSH;
      repeat(35) @(posedge CLK);

      D = 32'b10101010101010101010101010101010;
      MODO = `LOAD;
      repeat(3) @(posedge CLK);

      DIR = 0;
      MODO = `CYCLE;
      repeat(35) @(posedge CLK);

      D = 32'b01100110011001100110011001100110;
      MODO = `LOAD;
      repeat(3) @(posedge CLK);

      DIR = 1;
      MODO = `CYCLE;
      repeat(35) @(posedge CLK);
      $finish;
    end

    initial
        $monitor("At time %t, Q = %h (%0d), S_OUT = %h (%0d)",
                 $time, Q, Q, S_OUT, S_OUT);

    initial begin
        $dumpfile ("registro32.vcd");
        $dumpvars(1, registro32_tb);
    end

endmodule
module registro32_tb();



  parameter  WIDTH = 32;


    reg ENB;
    reg DIR;
    reg S_IN;
    reg [1 : 0]          MODO;
    reg [WIDTH - 1 : 0]  D;
    reg CLK;

    wire [WIDTH - 1 : 0] Q;
    wire                 S_OUT;


    wire [7 : 1]         S_OUT_IN;


    registro #(4) r0
    (
      .Q(Q[3:0]),
      .S_OUT(S_OUT_IN[1]),
      .D(D[3:0]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_IN)
      );

    registro #(4) r1
    (
      .Q(Q[7:4]),
      .S_OUT(S_OUT_IN[2]),
      .D(D[7:4]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[1])
      );

    registro #(4) r2
    (
      .Q(Q[11:8]),
      .S_OUT(S_OUT_IN[3]),
      .D(D[11:8]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[2])
      );

    registro #(4) r3
    (
      .Q(Q[15:12]),
      .S_OUT(S_OUT_IN[4]),
      .D(D[15:12]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[3])
      );

    registro #(4) r4
    (
      .Q(Q[19:16]),
      .S_OUT(S_OUT_IN[5]),
      .D(D[19:16]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[4])
      );

    registro #(4) r5
    (
      .Q(Q[23:20]),
      .S_OUT(S_OUT_IN[6]),
      .D(D[23:20]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[5])
      );

    registro #(4) r6
    (
      .Q(Q[27:24]),
      .S_OUT(S_OUT_IN[7]),
      .D(D[27:24]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[6])
      );

    registro #(4) r7
    (
      .Q(Q[WIDTH - 1: 28]),
      .S_OUT(S_OUT),
      .D(D[WIDTH - 1: 28]),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_OUT_IN[7])
      );



    initial begin
      CLK = 1'b0;
      ENB = 1'b0;
      repeat(4) #5 CLK = ~CLK;
      ENB = 1'b1;
      forever #5 CLK = ~CLK;
    end

    initial begin

      @(posedge ENB);
      D = 32'b11011101110111011101110111011101;
      MODO = `LOAD;
      S_IN = 1'b0;
      DIR = 0;
      repeat(15) @(posedge CLK);

      S_IN = 1'b0;
      DIR = 0;
      MODO = `PUSH;
      repeat(35) @(posedge CLK);

      S_IN = 1'b1;
      DIR = 1;
      MODO = `PUSH;
      repeat(35) @(posedge CLK);

      D = 32'b10101010101010101010101010101010;
      MODO = `LOAD;
      repeat(3) @(posedge CLK);

      DIR = 0;
      MODO = `CYCLE;
      repeat(35) @(posedge CLK);

      D = 32'b01100110011001100110011001100110;
      MODO = `LOAD;
      repeat(3) @(posedge CLK);

      DIR = 1;
      MODO = `CYCLE;
      repeat(35) @(posedge CLK);
      $finish;
    end

    initial
        $monitor("At time %t, Q = %h (%0d), S_OUT = %h (%0d)",
                 $time, Q, Q, S_OUT, S_OUT);

    initial begin
        $dumpfile ("registro32.vcd");
        $dumpvars(1, registro32_tb);
    end

endmodule