data/full_repos/permissive/125927162/digital_comparitor/comp.v
data/verilator_xmls/0d254076-7d74-4fec-9dcd-f3a94a45842d.xml
module comp (a, b, gt, eq, lt);
   parameter WIDTH = 4;
   input [WIDTH-1:0] a;
   input [WIDTH-1:0] b;
   output 	     gt;
   output 	     eq;
   output 	     lt;

   assign gt = a > b;
   assign eq = a == b;
   assign lt = a < b;
endmodule
module comp (a, b, gt, eq, lt);

   parameter WIDTH = 4;
   input [WIDTH-1:0] a;
   input [WIDTH-1:0] b;
   output 	     gt;
   output 	     eq;
   output 	     lt;

   assign gt = a > b;
   assign eq = a == b;
   assign lt = a < b;
endmodule