data/full_repos/permissive/135077285/main.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/135077285/main.v:465: Multiple top level modules\n                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                  : ... Top module \'main\'\nmodule main (clock, instr, reset);\n       ^~~~\n                                                                  : ... Top module \'setSeg\'\nmodule setSeg(in, out);\n       ^~~~~~\n%Error: data/full_repos/permissive/135077285/main.v:127: Input/output/inout does not appear in port list: \'regWriteMemWb\'\n  input wire regWriteMemWb;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135077285/main.v:128: Input/output/inout does not appear in port list: \'memToRegMemWb\'\n  input wire memToRegMemWb;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135077285/main.v:130: Input/output/inout does not appear in port list: \'readDataMemoryMemWb\'\n  input wire [31:0] readDataMemoryMemWb;\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135077285/main.v:131: Input/output/inout does not appear in port list: \'aluResultMemWb\'\n  input wire [31:0] aluResultMemWb;\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135077285/main.v:132: Input/output/inout does not appear in port list: \'writeRegisterMemWb\'\n  input wire [4:0] writeRegisterMemWb;\n                   ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module setSeg(in, out);
	input wire[3:0]in;
	output reg[6:0] out = 7'b1000000;

	always @ * begin
		case(in)
			4'b0000: out = 7'b1000000;
			4'b0001: out = 7'b1111001;
			4'b0010: out = 7'b0100100;
			4'b0011: out = 7'b0110000;
			4'b0100: out = 7'b0011001;
			4'b0101: out = 7'b0010010;
			4'b0110: out = 7'b0000010;
			4'b0111: out = 7'b1111000;
			4'b1000: out = 7'b0000000;
			4'b1001: out = 7'b0011000;
			4'b1010: out = 7'b0001000;
			4'b1011: out = 7'b0000011;
			4'b1100: out = 7'b1000110;
			4'b1101: out = 7'b0100001;
			4'b1110: out = 7'b0000110;
			4'b1111: out = 7'b0001110;

		endcase
	end
endmodule
module setSeg(in, out);

	input wire[3:0]in;
	output reg[6:0] out = 7'b1000000;

	always @ * begin
		case(in)
			4'b0000: out = 7'b1000000;
			4'b0001: out = 7'b1111001;
			4'b0010: out = 7'b0100100;
			4'b0011: out = 7'b0110000;
			4'b0100: out = 7'b0011001;
			4'b0101: out = 7'b0010010;
			4'b0110: out = 7'b0000010;
			4'b0111: out = 7'b1111000;
			4'b1000: out = 7'b0000000;
			4'b1001: out = 7'b0011000;
			4'b1010: out = 7'b0001000;
			4'b1011: out = 7'b0000011;
			4'b1100: out = 7'b1000110;
			4'b1101: out = 7'b0100001;
			4'b1110: out = 7'b0000110;
			4'b1111: out = 7'b0001110;

		endcase
	end
endmodule