data/full_repos/permissive/121785750/rsflipflop.v
data/verilator_xmls/9448693e-318a-4fba-a6cd-cb7ff4b64f4f.xml
module control_ff(Clock, ff_in, Set, Clear,Reset, Q);
	input Clock, ff_in, Set, Clear,Reset;
	output reg Q;
	always @(posedge Clock)
	begin
		if (Set^(Clear|Reset)) Q <= Set;
		else Q<=ff_in;
	end	
endmodule
module control_ff(Clock, ff_in, Set, Clear,Reset, Q);

	input Clock, ff_in, Set, Clear,Reset;
	output reg Q;
	always @(posedge Clock)
	begin
		if (Set^(Clear|Reset)) Q <= Set;
		else Q<=ff_in;
	end	
endmodule