data/full_repos/permissive/140357212/Tomasulo/count.v
data/verilator_xmls/32978d75-4d17-4372-a9a0-2886c14dfb9e.xml
module Count_tomasulo(clk,q);
	input clk;
	output reg [20:0]q;
	initial
		q = 0;
		
	always@(posedge clk) begin
			q = q + 1;
	end
endmodule
module Count_tomasulo(clk,q);

	input clk;
	output reg [20:0]q;
	initial
		q = 0;
		
	always@(posedge clk) begin
			q = q + 1;
	end
endmodule