data/full_repos/permissive/149848590/src/cpu/mmu/MMU.v
1: b'%Warning-UNSIGNED: data/full_repos/permissive/149848590/src/cpu/mmu/MMU.v:18: Comparison is constant due to unsigned arithmetic\n                                                                            : ... In instance MMU\n            if (read_addr_in[31:28] >= (4\'h0) && read_addr_in[31:28] <= (4\'h7)) begin\n                                    ^~\n                   ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.\n%Warning-UNSIGNED: data/full_repos/permissive/149848590/src/cpu/mmu/MMU.v:41: Comparison is constant due to unsigned arithmetic\n                                                                            : ... In instance MMU\n            if (write_addr_in[31:28] >= (4\'h0) && write_addr_in[31:28] <= (4\'h7)) begin\n                                     ^~\n%Error: Exiting due to 2 warning(s)\n'
module MMU(
    input rst,
    input [31:0] read_addr_in,
    input [31:0] write_addr_in,
    output reg[31:0] read_addr_out,
    output reg[31:0] write_addr_out
);

    always @(*) begin
        if (!rst) begin
            read_addr_out <= 0;
        end
        else begin
            if (`IN_RANGE(read_addr_in, 4'h0, 4'h7)) begin
                read_addr_out <= read_addr_in;
            end
            else if (`IN_RANGE(read_addr_in, 4'h8, 4'h9)) begin
                read_addr_out <= {read_addr_in[31:28] - 4'h8, read_addr_in[27:0]};
            end
            else if (`IN_RANGE(read_addr_in, 4'ha, 4'hb)) begin
                read_addr_out <= {read_addr_in[31:28] - 4'ha, read_addr_in[27:0]};
            end
            else if (`IN_RANGE(read_addr_in, 4'hc, 4'hd)) begin
                read_addr_out <= read_addr_in;
            end
            else begin
                read_addr_out <= read_addr_in;
            end
        end
    end

    always @(*) begin
        if (!rst) begin
            write_addr_out <= 0;
        end
        else begin
            if (`IN_RANGE(write_addr_in, 4'h0, 4'h7)) begin
                write_addr_out <= write_addr_in;
            end
            else if (`IN_RANGE(write_addr_in, 4'h8, 4'h9)) begin
                write_addr_out <= {write_addr_in[31:28] - 4'h8, write_addr_in[27:0]};
            end
            else if (`IN_RANGE(write_addr_in, 4'ha, 4'hb)) begin
                write_addr_out <= {write_addr_in[31:28] - 4'ha, write_addr_in[27:0]};
            end
            else if (`IN_RANGE(write_addr_in, 4'hc, 4'hd)) begin
                write_addr_out <= write_addr_in;
            end
            else begin
                write_addr_out <= write_addr_in;
            end
        end
    end

endmodule
module MMU(
    input rst,
    input [31:0] read_addr_in,
    input [31:0] write_addr_in,
    output reg[31:0] read_addr_out,
    output reg[31:0] write_addr_out
);


    always @(*) begin
        if (!rst) begin
            read_addr_out <= 0;
        end
        else begin
            if (`IN_RANGE(read_addr_in, 4'h0, 4'h7)) begin
                read_addr_out <= read_addr_in;
            end
            else if (`IN_RANGE(read_addr_in, 4'h8, 4'h9)) begin
                read_addr_out <= {read_addr_in[31:28] - 4'h8, read_addr_in[27:0]};
            end
            else if (`IN_RANGE(read_addr_in, 4'ha, 4'hb)) begin
                read_addr_out <= {read_addr_in[31:28] - 4'ha, read_addr_in[27:0]};
            end
            else if (`IN_RANGE(read_addr_in, 4'hc, 4'hd)) begin
                read_addr_out <= read_addr_in;
            end
            else begin
                read_addr_out <= read_addr_in;
            end
        end
    end

    always @(*) begin
        if (!rst) begin
            write_addr_out <= 0;
        end
        else begin
            if (`IN_RANGE(write_addr_in, 4'h0, 4'h7)) begin
                write_addr_out <= write_addr_in;
            end
            else if (`IN_RANGE(write_addr_in, 4'h8, 4'h9)) begin
                write_addr_out <= {write_addr_in[31:28] - 4'h8, write_addr_in[27:0]};
            end
            else if (`IN_RANGE(write_addr_in, 4'ha, 4'hb)) begin
                write_addr_out <= {write_addr_in[31:28] - 4'ha, write_addr_in[27:0]};
            end
            else if (`IN_RANGE(write_addr_in, 4'hc, 4'hd)) begin
                write_addr_out <= write_addr_in;
            end
            else begin
                write_addr_out <= write_addr_in;
            end
        end
    end

endmodule