data/full_repos/permissive/196412397/default_reg_writer_tb.v
1: b'%Error: data/full_repos/permissive/196412397/default_reg_writer_tb.v:11: Cannot find include file: clock_enable_param.v\n`include "clock_enable_param.v"  \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/clock_enable_param.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/clock_enable_param.v.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/clock_enable_param.v.sv\n             clock_enable_param.v\n             clock_enable_param.v.v\n             clock_enable_param.v.sv\n             obj_dir/clock_enable_param.v\n             obj_dir/clock_enable_param.v.v\n             obj_dir/clock_enable_param.v.sv\n%Error: data/full_repos/permissive/196412397/default_reg_writer_tb.v:13: Cannot find include file: default_reg_writer.v\n`include "default_reg_writer.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/196412397/default_reg_writer_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/196412397/default_reg_writer_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #0_500; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/default_reg_writer_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #0_020;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/default_reg_writer_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #0_500; \n    ^\n%Error: data/full_repos/permissive/196412397/default_reg_writer_tb.v:63: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/196412397/default_reg_writer_tb.v:64: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0);\n    ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module default_reg_writer_tb();



reg clk = 1'b0;
wire w_enable;
reg reset = 0;



always #0.5 clk <= ~clk;


default_reg_writer uut_sender(
    .clk(clk),
    .i_enable(w_enable),
    .i_reset(reset)
);

clock_enable_param #(


  ) clock_enable1 (
    .clk(clk),
    .enable(w_enable)
);

initial 
  begin 
    #0_500; 
    $display("*");
    reset = 1;
    #0_020;
    reset = 0;
    #0_500; 

    $display(" ");
    $display("Use this command to open timing diagram:");
    $display("gtkwave -f wave.vcd");
    $display("----------------------------------------------");
    $finish();
end

initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
end

endmodule
module default_reg_writer_tb();




reg clk = 1'b0;
wire w_enable;
reg reset = 0;



always #0.5 clk <= ~clk;


default_reg_writer uut_sender(
    .clk(clk),
    .i_enable(w_enable),
    .i_reset(reset)
);

clock_enable_param #(


  ) clock_enable1 (
    .clk(clk),
    .enable(w_enable)
);

initial 
  begin 
    #0_500; 
    $display("*");
    reset = 1;
    #0_020;
    reset = 0;
    #0_500; 

    $display(" ");
    $display("Use this command to open timing diagram:");
    $display("gtkwave -f wave.vcd");
    $display("----------------------------------------------");
    $finish();
end

initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
end

endmodule