data/full_repos/permissive/189940829/Lab2-Single Cycle Compter with IO/source/out_port_translator.v
1: b'%Error: Cannot find file containing module: Cycle\n        ... Looked in:\n             data/full_repos/permissive/189940829/Lab2-Single/Cycle\n             data/full_repos/permissive/189940829/Lab2-Single/Cycle.v\n             data/full_repos/permissive/189940829/Lab2-Single/Cycle.sv\n             Cycle\n             Cycle.v\n             Cycle.sv\n             obj_dir/Cycle\n             obj_dir/Cycle.v\n             obj_dir/Cycle.sv\n%Error: Cannot find file containing module: Compter\n%Error: Cannot find file containing module: with\n%Error: Cannot find file containing module: IO/source,data/full_repos/permissive/189940829\n%Error: Cannot find file containing module: data/full_repos/permissive/189940829/Lab2-Single\n%Error: Cannot find file containing module: IO/source/out_port_translator.v\n%Error: Exiting due to 6 error(s)\n'
module sevenseg ( data, ledsegments);
  input [3:0] data;
  output [6:0] ledsegments;
  reg [6:0] ledsegments;
  always @ (data)
    case(data)


      0: ledsegments = 7'b100_0000;
      1: ledsegments = 7'b111_1001;
      2: ledsegments = 7'b010_0100;
      3: ledsegments = 7'b011_0000;
      4: ledsegments = 7'b001_1001;
      5: ledsegments = 7'b001_0010;
      6: ledsegments = 7'b000_0010;
      7: ledsegments = 7'b111_1000;
      8: ledsegments = 7'b000_0000;
      9: ledsegments = 7'b001_0000;
      default: ledsegments = 7'b111_1111;
    endcase
endmodule
module sevenseg ( data, ledsegments);

  input [3:0] data;
  output [6:0] ledsegments;
  reg [6:0] ledsegments;
  always @ (data)
    case(data)


      0: ledsegments = 7'b100_0000;
      1: ledsegments = 7'b111_1001;
      2: ledsegments = 7'b010_0100;
      3: ledsegments = 7'b011_0000;
      4: ledsegments = 7'b001_1001;
      5: ledsegments = 7'b001_0010;
      6: ledsegments = 7'b000_0010;
      7: ledsegments = 7'b111_1000;
      8: ledsegments = 7'b000_0000;
      9: ledsegments = 7'b001_0000;
      default: ledsegments = 7'b111_1111;
    endcase
endmodule