data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/vga_timing.v
data/verilator_xmls/52aaed13-c900-4a4d-8fcc-3ea8672e0327.xml
module vga_timing
 (
   input  wire         reset,
   input  wire         clk_dot,
   output reg          vid_new_frame,
   output reg          vid_new_line,
   output reg          vid_active,  
   output reg          vga_hsync,
   output reg          vga_vsync
 );


`define def_h_sync     16'd128
`define def_h_bp       16'd88 
`define def_h_actv     16'd800
`define def_h_fp       16'd40
`define def_h_total    16'd1056

`define def_v_sync     16'd4  
`define def_v_bp       16'd23 
`define def_v_actv     16'd600
`define def_v_fp       16'd1 
`define def_v_total    16'd628 








`define state_h_sync   2'd0
`define state_h_bp     2'd1
`define state_h_actv   2'd2
`define state_h_fp     2'd3

`define state_v_sync   2'd0
`define state_v_bp     2'd1
`define state_v_actv   2'd2
`define state_v_fp     2'd3

 reg  [15:0]   cnt_h;
 reg  [15:0]   cnt_v;
 reg  [1:0]    fsm_h;
 reg  [1:0]    fsm_v;
 reg           hsync_loc;
 reg           vsync_loc;
 reg           vsync_loc_p1;
 reg           h_rollover;





always @ (posedge clk_dot  or posedge reset ) begin : proc_dout
 if ( reset == 1 ) begin
   vga_hsync    <= 1'b0;
   vga_vsync    <= 1'b0;
   vsync_loc_p1 <= 1'b0;
 end else begin
   vga_hsync    <= hsync_loc;
   vga_vsync    <= vsync_loc;
   vsync_loc_p1 <= vsync_loc;
 end
end

                                                                                



always @ (posedge clk_dot  or posedge reset ) begin : proc_vga_h
 if ( reset == 1 ) begin
   hsync_loc     <= 1'b0;
   vid_new_line  <= 1'b0;
   vid_new_frame <= 1'b0;
   vid_active    <= 1'b0;
   cnt_h         <= 16'd1;
   fsm_h         <= `state_h_sync;
   h_rollover    <= 1'b1;
 end else begin
   h_rollover    <= 1'b0;
   vid_new_line  <= 1'b0;
   vid_new_frame <= 1'b0;
   vid_active    <= 1'b0;
   hsync_loc     <= 1'b0;
   cnt_h         <= cnt_h + 16'd1;

   if ( fsm_h == `state_h_sync ) begin
     hsync_loc  <= 1'b1;
   end
   if ( fsm_h == `state_h_actv && fsm_v == `state_v_actv ) begin
     vid_active   <= 1'b1;
   end

   if ( fsm_h == `state_h_sync && cnt_h == `def_h_sync ) begin
     cnt_h        <= 16'd1;
     fsm_h        <= fsm_h + 2'd1;
   end
   if ( fsm_h == `state_h_bp   && cnt_h == `def_h_bp   ) begin
     cnt_h        <= 16'd1;
     fsm_h        <= fsm_h + 2'd1;
     vid_new_line <= 1'b1;
     if ( fsm_v == `state_v_actv && cnt_v == 16'd2 ) begin
       vid_new_frame <= 1'b1;
     end
   end
   if ( fsm_h == `state_h_actv   && cnt_h == `def_h_actv ) begin
     cnt_h        <= 16'd1;
     fsm_h        <= fsm_h + 2'd1;
   end
   if ( fsm_h == `state_h_fp     && cnt_h == `def_h_fp   ) begin
     cnt_h        <= 16'd1;
     fsm_h        <= fsm_h + 2'd1;
     h_rollover   <= 1'b1;
   end
 end
end





always @ (posedge clk_dot  or posedge reset ) begin : proc_vga_v
 if ( reset == 1 ) begin
   cnt_v      <= 16'd1;
   vsync_loc  <= 1'b0;
   fsm_v      <= `state_v_fp;
 end else begin
   if ( h_rollover == 1'b1 ) begin
     cnt_v     <= cnt_v + 16'd1;
     vsync_loc <= 1'b0;
     if ( fsm_v == `state_v_sync && cnt_v == `def_v_sync ) begin
       cnt_v <= 16'd1;
       fsm_v <= fsm_v + 2'd1;
     end
     if ( fsm_v == `state_v_bp   && cnt_v == `def_v_bp   ) begin
       cnt_v <= 16'd1;
       fsm_v <= fsm_v + 2'd1;
     end
     if ( fsm_v == `state_v_actv && cnt_v == `def_v_actv ) begin
       cnt_v <= 16'd1;
       fsm_v <= fsm_v + 2'd1;
     end
     if ( fsm_v == `state_v_fp   && cnt_v == `def_v_fp ) begin
       cnt_v      <= 16'd1;
       fsm_v      <= fsm_v + 2'd1;
       vsync_loc  <= 1'b1;
     end

     if ( fsm_v == `state_v_sync && cnt_v != `def_v_sync ) begin
       vsync_loc  <= 1'b1;
     end
   end
 end
end
                                                                                

endmodule
module vga_timing
 (
   input  wire         reset,
   input  wire         clk_dot,
   output reg          vid_new_frame,
   output reg          vid_new_line,
   output reg          vid_active,  
   output reg          vga_hsync,
   output reg          vga_vsync
 );



`define def_h_sync     16'd128
`define def_h_bp       16'd88 
`define def_h_actv     16'd800
`define def_h_fp       16'd40
`define def_h_total    16'd1056

`define def_v_sync     16'd4  
`define def_v_bp       16'd23 
`define def_v_actv     16'd600
`define def_v_fp       16'd1 
`define def_v_total    16'd628 








`define state_h_sync   2'd0
`define state_h_bp     2'd1
`define state_h_actv   2'd2
`define state_h_fp     2'd3

`define state_v_sync   2'd0
`define state_v_bp     2'd1
`define state_v_actv   2'd2
`define state_v_fp     2'd3

 reg  [15:0]   cnt_h;
 reg  [15:0]   cnt_v;
 reg  [1:0]    fsm_h;
 reg  [1:0]    fsm_v;
 reg           hsync_loc;
 reg           vsync_loc;
 reg           vsync_loc_p1;
 reg           h_rollover;





always @ (posedge clk_dot  or posedge reset ) begin : proc_dout
 if ( reset == 1 ) begin
   vga_hsync    <= 1'b0;
   vga_vsync    <= 1'b0;
   vsync_loc_p1 <= 1'b0;
 end else begin
   vga_hsync    <= hsync_loc;
   vga_vsync    <= vsync_loc;
   vsync_loc_p1 <= vsync_loc;
 end
end

                                                                                



always @ (posedge clk_dot  or posedge reset ) begin : proc_vga_h
 if ( reset == 1 ) begin
   hsync_loc     <= 1'b0;
   vid_new_line  <= 1'b0;
   vid_new_frame <= 1'b0;
   vid_active    <= 1'b0;
   cnt_h         <= 16'd1;
   fsm_h         <= `state_h_sync;
   h_rollover    <= 1'b1;
 end else begin
   h_rollover    <= 1'b0;
   vid_new_line  <= 1'b0;
   vid_new_frame <= 1'b0;
   vid_active    <= 1'b0;
   hsync_loc     <= 1'b0;
   cnt_h         <= cnt_h + 16'd1;

   if ( fsm_h == `state_h_sync ) begin
     hsync_loc  <= 1'b1;
   end
   if ( fsm_h == `state_h_actv && fsm_v == `state_v_actv ) begin
     vid_active   <= 1'b1;
   end

   if ( fsm_h == `state_h_sync && cnt_h == `def_h_sync ) begin
     cnt_h        <= 16'd1;
     fsm_h        <= fsm_h + 2'd1;
   end
   if ( fsm_h == `state_h_bp   && cnt_h == `def_h_bp   ) begin
     cnt_h        <= 16'd1;
     fsm_h        <= fsm_h + 2'd1;
     vid_new_line <= 1'b1;
     if ( fsm_v == `state_v_actv && cnt_v == 16'd2 ) begin
       vid_new_frame <= 1'b1;
     end
   end
   if ( fsm_h == `state_h_actv   && cnt_h == `def_h_actv ) begin
     cnt_h        <= 16'd1;
     fsm_h        <= fsm_h + 2'd1;
   end
   if ( fsm_h == `state_h_fp     && cnt_h == `def_h_fp   ) begin
     cnt_h        <= 16'd1;
     fsm_h        <= fsm_h + 2'd1;
     h_rollover   <= 1'b1;
   end
 end
end





always @ (posedge clk_dot  or posedge reset ) begin : proc_vga_v
 if ( reset == 1 ) begin
   cnt_v      <= 16'd1;
   vsync_loc  <= 1'b0;
   fsm_v      <= `state_v_fp;
 end else begin
   if ( h_rollover == 1'b1 ) begin
     cnt_v     <= cnt_v + 16'd1;
     vsync_loc <= 1'b0;
     if ( fsm_v == `state_v_sync && cnt_v == `def_v_sync ) begin
       cnt_v <= 16'd1;
       fsm_v <= fsm_v + 2'd1;
     end
     if ( fsm_v == `state_v_bp   && cnt_v == `def_v_bp   ) begin
       cnt_v <= 16'd1;
       fsm_v <= fsm_v + 2'd1;
     end
     if ( fsm_v == `state_v_actv && cnt_v == `def_v_actv ) begin
       cnt_v <= 16'd1;
       fsm_v <= fsm_v + 2'd1;
     end
     if ( fsm_v == `state_v_fp   && cnt_v == `def_v_fp ) begin
       cnt_v      <= 16'd1;
       fsm_v      <= fsm_v + 2'd1;
       vsync_loc  <= 1'b1;
     end

     if ( fsm_v == `state_v_sync && cnt_v != `def_v_sync ) begin
       vsync_loc  <= 1'b1;
     end
   end
 end
end
                                                                                

endmodule