data/full_repos/permissive/149769583/clkdiv_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/149769583/clkdiv_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n          #5 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/149769583/clkdiv_tb.v:7: Cannot find file containing module: \'clkdiv2\'\n    clkdiv2 DUT (.clk(clk), .invclk2(clk1), .clk2(clk2));\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/clkdiv2\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/clkdiv2.v\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/clkdiv2.sv\n             clkdiv2\n             clkdiv2.v\n             clkdiv2.sv\n             obj_dir/clkdiv2\n             obj_dir/clkdiv2.v\n             obj_dir/clkdiv2.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clkdiv_tb();

    reg clk;
    wire clk1,clk2;

    clkdiv2 DUT (.clk(clk), .invclk2(clk1), .clk2(clk2));

    initial begin
            clk = 0;
    end

    always begin
          #5 clk = ~clk;
           end

endmodule
module clkdiv_tb();


    reg clk;
    wire clk1,clk2;

    clkdiv2 DUT (.clk(clk), .invclk2(clk1), .clk2(clk2));

    initial begin
            clk = 0;
    end

    always begin
          #5 clk = ~clk;
           end

endmodule