data/full_repos/permissive/154804262/testBench/BpsClkGen_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/BpsClkGen_tb.v:7: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/BpsClkGen_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #50000 countEnable = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/BpsClkGen_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n   #80000 countEnable = 1\'b1;\n   ^\n%Error: data/full_repos/permissive/154804262/testBench/BpsClkGen_tb.v:22: Cannot find file containing module: \'BpsClkGen\'\n    BpsClkGen ins(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154804262/testBench,data/full_repos/permissive/154804262/BpsClkGen\n             data/full_repos/permissive/154804262/testBench,data/full_repos/permissive/154804262/BpsClkGen.v\n             data/full_repos/permissive/154804262/testBench,data/full_repos/permissive/154804262/BpsClkGen.sv\n             BpsClkGen\n             BpsClkGen.v\n             BpsClkGen.sv\n             obj_dir/BpsClkGen\n             obj_dir/BpsClkGen.v\n             obj_dir/BpsClkGen.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module BpsClkGen_tb;

	reg clk;
	initial
		clk = 1'b0;
	always
		#5 clk = ~clk;

	reg reset;
	initial
		reset = 1'b1;

	reg countEnable;
	initial
		begin
			countEnable = 1'b1;
			#50000 countEnable = 1'b0;
			#80000 countEnable = 1'b1;
		end

	wire bpsClk;
   	BpsClkGen ins(
		.clk(clk),
		.reset(reset),
		.countEnable(countEnable),
		.bpsClk(bpsClk)
		);
		 
endmodule
module BpsClkGen_tb;


	reg clk;
	initial
		clk = 1'b0;
	always
		#5 clk = ~clk;

	reg reset;
	initial
		reset = 1'b1;

	reg countEnable;
	initial
		begin
			countEnable = 1'b1;
			#50000 countEnable = 1'b0;
			#80000 countEnable = 1'b1;
		end

	wire bpsClk;
   	BpsClkGen ins(
		.clk(clk),
		.reset(reset),
		.countEnable(countEnable),
		.bpsClk(bpsClk)
		);
		 
endmodule