data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v
 line:15: before: "$"
1: b'%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:26: Cannot find include file: RV2T_common.vh\n`include "RV2T_common.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source,data/full_repos/permissive/158824477/RV2T_common.vh\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source,data/full_repos/permissive/158824477/RV2T_common.vh.v\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source,data/full_repos/permissive/158824477/RV2T_common.vh.sv\n             RV2T_common.vh\n             RV2T_common.vh.v\n             RV2T_common.vh.sv\n             obj_dir/RV2T_common.vh\n             obj_dir/RV2T_common.vh.v\n             obj_dir/RV2T_common.vh.sv\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:47: Define or directive not defined: \'`MEM_ADDR_BITS\'\n        input   wire  [`MEM_ADDR_BITS - 1 : 0]                          ocd_rw_addr,\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:48: Define or directive not defined: \'`XLEN\'\n        input   wire  [`XLEN - 1 : 0]                                   ocd_write_word,\n                       ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:54: Define or directive not defined: \'`MEM_ADDR_BITS\'\n        input   wire  [`MEM_ADDR_BITS - 1 : 0]                          code_read_addr,\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:60: Define or directive not defined: \'`XLEN_BYTES\'\n        input   wire  [`XLEN_BYTES - 1 : 0]                             data_write_enable,\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:62: Define or directive not defined: \'`MEM_ADDR_BITS\'\n        input   wire  [`MEM_ADDR_BITS - 1 : 0]                          data_rw_addr,\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:63: Define or directive not defined: \'`XLEN\'\n        input   wire  [`XLEN - 1 : 0]                                   data_write_word,\n                       ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:70: Define or directive not defined: \'`XLEN\'\n        output  wire  [`XLEN - 1 : 0]                                   word_out,\n                       ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:72: Define or directive not defined: \'`MEM_ADDR_BITS\'\n        output  wire  [`MEM_ADDR_BITS - 1 : 0]                          mem_addr,\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:73: Define or directive not defined: \'`XLEN_BYTES\'\n        output  wire [`XLEN_BYTES - 1 : 0]                              mem_write_en,\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:74: Define or directive not defined: \'`XLEN\'\n        output  wire [`XLEN - 1 : 0]                                    mem_write_data,\n                      ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:76: Define or directive not defined: \'`XLEN\'\n        input   wire [`XLEN - 1 : 0]                                    mem_read_data\n                      ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:85: Define or directive not defined: \'`MEM_ADDR_BITS\'\n            reg  [`MEM_ADDR_BITS - 1 : 0]     addr;\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:86: Define or directive not defined: \'`XLEN\'\n            wire [`XLEN - 1 : 0]              din;\n                  ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:87: Define or directive not defined: \'`XLEN_BYTES\'\n            wire [`XLEN_BYTES - 1 : 0]        write_en;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:95: Define or directive not defined: \'`XLEN_BYTES\'\n            assign write_en = {(`XLEN_BYTES){ocd_write_enable}} | data_write_enable;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_memory.v:95: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            assign write_en = {(`XLEN_BYTES){ocd_write_enable}} | data_write_enable;\n                                           ^\n%Error: Exiting due to 17 error(s)\n'
module RV2T_memory (
    




        input   wire                                                    clk,
        input   wire                                                    reset_n,
        input   wire                                                    sync_reset,




        
        input   wire                                                    ocd_read_enable,
        input   wire                                                    ocd_write_enable,
        
        input   wire  [`MEM_ADDR_BITS - 1 : 0]                          ocd_rw_addr,
        input   wire  [`XLEN - 1 : 0]                                   ocd_write_word,
        



        input   wire                                                    code_read_enable,
        input   wire  [`MEM_ADDR_BITS - 1 : 0]                          code_read_addr,
                



        input   wire                                                    data_read_enable,
        input   wire  [`XLEN_BYTES - 1 : 0]                             data_write_enable,
        
        input   wire  [`MEM_ADDR_BITS - 1 : 0]                          data_rw_addr,
        input   wire  [`XLEN - 1 : 0]                                   data_write_word,
        
        



        output  reg                                                     enable_out,
        output  wire  [`XLEN - 1 : 0]                                   word_out,
        
        output  wire  [`MEM_ADDR_BITS - 1 : 0]                          mem_addr,
        output  wire [`XLEN_BYTES - 1 : 0]                              mem_write_en,
        output  wire [`XLEN - 1 : 0]                                    mem_write_data,
        
        input   wire [`XLEN - 1 : 0]                                    mem_read_data
            
        
);





            reg  [`MEM_ADDR_BITS - 1 : 0]     addr;
            wire [`XLEN - 1 : 0]              din;
            wire [`XLEN_BYTES - 1 : 0]        write_en;
            wire [15 : 0]                     dout_high;
            wire [15 : 0]                     dout_low;
                        



            
            assign write_en = {(`XLEN_BYTES){ocd_write_enable}} | data_write_enable;
            
            always @(*) begin : addr_proc
                if (ocd_read_enable | ocd_write_enable) begin
                    addr = ocd_rw_addr;
                end else if (code_read_enable) begin
                    addr = code_read_addr;
                end else begin
                    addr = data_rw_addr;
                end
            end

            assign din = ocd_write_enable ? ocd_write_word : data_write_word;



            

           
            assign word_out = mem_read_data;
            
            always @(posedge clk, negedge reset_n) begin : output_proc
                if (!reset_n) begin
                    enable_out <= 0;
                end else begin
                    enable_out <= ocd_read_enable | code_read_enable | data_read_enable;
                end
            end

            assign mem_addr = addr;
            assign mem_write_en = write_en;
            assign mem_write_data = din;
        
endmodule
module RV2T_memory (
    




        input   wire                                                    clk,
        input   wire                                                    reset_n,
        input   wire                                                    sync_reset,




        
        input   wire                                                    ocd_read_enable,
        input   wire                                                    ocd_write_enable,
        
        input   wire  [`MEM_ADDR_BITS - 1 : 0]                          ocd_rw_addr,
        input   wire  [`XLEN - 1 : 0]                                   ocd_write_word,
        



        input   wire                                                    code_read_enable,
        input   wire  [`MEM_ADDR_BITS - 1 : 0]                          code_read_addr,
                



        input   wire                                                    data_read_enable,
        input   wire  [`XLEN_BYTES - 1 : 0]                             data_write_enable,
        
        input   wire  [`MEM_ADDR_BITS - 1 : 0]                          data_rw_addr,
        input   wire  [`XLEN - 1 : 0]                                   data_write_word,
        
        



        output  reg                                                     enable_out,
        output  wire  [`XLEN - 1 : 0]                                   word_out,
        
        output  wire  [`MEM_ADDR_BITS - 1 : 0]                          mem_addr,
        output  wire [`XLEN_BYTES - 1 : 0]                              mem_write_en,
        output  wire [`XLEN - 1 : 0]                                    mem_write_data,
        
        input   wire [`XLEN - 1 : 0]                                    mem_read_data
            
        
);






            reg  [`MEM_ADDR_BITS - 1 : 0]     addr;
            wire [`XLEN - 1 : 0]              din;
            wire [`XLEN_BYTES - 1 : 0]        write_en;
            wire [15 : 0]                     dout_high;
            wire [15 : 0]                     dout_low;
                        



            
            assign write_en = {(`XLEN_BYTES){ocd_write_enable}} | data_write_enable;
            
            always @(*) begin : addr_proc
                if (ocd_read_enable | ocd_write_enable) begin
                    addr = ocd_rw_addr;
                end else if (code_read_enable) begin
                    addr = code_read_addr;
                end else begin
                    addr = data_rw_addr;
                end
            end

            assign din = ocd_write_enable ? ocd_write_word : data_write_word;



            

           
            assign word_out = mem_read_data;
            
            always @(posedge clk, negedge reset_n) begin : output_proc
                if (!reset_n) begin
                    enable_out <= 0;
                end else begin
                    enable_out <= ocd_read_enable | code_read_enable | data_read_enable;
                end
            end

            assign mem_addr = addr;
            assign mem_write_en = write_en;
            assign mem_write_data = din;
        
endmodule