data/full_repos/permissive/158922207/Verilog Design/modules/ForwardingUnit.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/ForwardingUnit.v\n%Error: Exiting due to 3 error(s)\n'
module ForwardingUnit_ID(ForwardA, ForwardB, Branch, EX_MEM_RegWrite, IF_ID_rs, IF_ID_rt, EX_MEM_rd, ID_EX_rd,ID_EX_RegWrite);
input Branch, EX_MEM_RegWrite,ID_EX_RegWrite;
input [4:0] IF_ID_rs, IF_ID_rt, EX_MEM_rd,ID_EX_rd;
output [1:0] ForwardA, ForwardB;
    
reg [1:0] conditionA, conditionB;
    
always @(*) begin
conditionA = 2'b00;
conditionB = 2'b00;
        
if (Branch) begin
    if ((EX_MEM_RegWrite && EX_MEM_rd != 5'd0) && (EX_MEM_rd == IF_ID_rs))
		conditionA = 2'b10;
	else if ((ID_EX_RegWrite && ID_EX_rd != 5'd0) && (ID_EX_rd == IF_ID_rs))
		conditionA = 2'b01;
	
	if ((EX_MEM_RegWrite && EX_MEM_rd != 5'd0) && (EX_MEM_rd == IF_ID_rt))
		conditionB = 2'b10;
	else if ((ID_EX_RegWrite && ID_EX_rd != 5'd0) && (ID_EX_rd == IF_ID_rt))
		conditionB = 2'b01;   

end
end

assign ForwardA = conditionA;
assign ForwardB = conditionB;

endmodule
module ForwardingUnit_ID(ForwardA, ForwardB, Branch, EX_MEM_RegWrite, IF_ID_rs, IF_ID_rt, EX_MEM_rd, ID_EX_rd,ID_EX_RegWrite);

input Branch, EX_MEM_RegWrite,ID_EX_RegWrite;
input [4:0] IF_ID_rs, IF_ID_rt, EX_MEM_rd,ID_EX_rd;
output [1:0] ForwardA, ForwardB;
    
reg [1:0] conditionA, conditionB;
    
always @(*) begin
conditionA = 2'b00;
conditionB = 2'b00;
        
if (Branch) begin
    if ((EX_MEM_RegWrite && EX_MEM_rd != 5'd0) && (EX_MEM_rd == IF_ID_rs))
		conditionA = 2'b10;
	else if ((ID_EX_RegWrite && ID_EX_rd != 5'd0) && (ID_EX_rd == IF_ID_rs))
		conditionA = 2'b01;
	
	if ((EX_MEM_RegWrite && EX_MEM_rd != 5'd0) && (EX_MEM_rd == IF_ID_rt))
		conditionB = 2'b10;
	else if ((ID_EX_RegWrite && ID_EX_rd != 5'd0) && (ID_EX_rd == IF_ID_rt))
		conditionB = 2'b01;   

end
end

assign ForwardA = conditionA;
assign ForwardB = conditionB;

endmodule