data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPRfunct.sv
 line:12: before: "S9"
1: b'%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPRfunct.sv:52: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPRfunct.sv:52: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPRfunct.sv:57: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                                             : ... In instance testbenchPPRfunct\n       currentvec = vectors[vectornum];\n                           ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbenchPPRfunct();
  logic clk;
  logic [8:0] PP0,PP1,PP2,PP3;
  logic Sign0;
  logic Sign1;
  logic Sign2;
  logic C0;
  logic C1;
  logic C10;
  logic C11;
  logic C12;
  logic C2;
  logic C3;
  logic C4;
  logic C5;
  logic C6;
  logic C7;
  logic C8;
  logic C9;
  logic S0;
  logic S1;
  logic S10;
  logic S11;
  logic S12;
  logic S2;
  logic S3;
  logic S4;
  logic S5;
  logic S6;
  logic S7;
  logic S8;
  logic S9;
    
    logic [9:0] vectors[1023:0], currentvec;
    logic [11:0] vectornum, errors;
    integer outC;
    

    functPPR dut(PP0, PP1, PP2, PP3, Sign0, Sign1, Sign2, C0, C1, C10, C11, C12, C2, 
      C3, C4, C5, C6, C7, C8, C9, S0, S1, S10, S11, S12, S2, S3, S4, S5, S6, 
      S7, S8, S9);
    

    initial begin
       $readmemb("lakis.txt", vectors);
       outC = $fopen("checkOUT.txt","w");
       vectornum = 0; errors = 0;
    end

    always begin
       clk = 1; #10; clk = 0; #10;
    end
      

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
       $display("%h%h%h%h%h%h%h%h%h%h", 
       currentvec[9], 
       currentvec[8] ,
       currentvec[7] ,
       currentvec[6] ,
       currentvec[5] ,
       currentvec[4] ,
       currentvec[3] ,
       currentvec[2] ,
       currentvec[1] ,
       currentvec[0] );

       PP3[8] = 0;
       PP3[6] = 0;
       PP3[4] = 1;
       PP3[2] = 0;
       PP3[0] = 0;
       PP3[1] = 1;
       PP3[3] = 0;
       PP3[5] = 0;
       PP3[7] = 0;
       

       Sign2= 1;
       PP2[8] = 0;
       PP2[6] = currentvec[9];
       PP2[4] = currentvec[8];
       PP2[2] = currentvec[7];
       PP2[0] = currentvec[6];
       PP2[1] = 1;
       PP2[3] = 1;
       PP2[5] = 1;
       PP2[7] = 1;

       Sign1 = 0;
       PP1[8] = 0;
       PP1[6] = 0;
       PP1[4] = 1;
       PP1[2] = 0;
       PP1[0] = 0;
       PP1[1] = 1;
       PP1[3] = 0;
       PP1[5] = 0;
       PP1[7] = 0;

       Sign0 = currentvec[5];
       PP0[8] = currentvec[4];
       PP0[6] = currentvec[3];
       PP0[4] = currentvec[2];
       PP0[2] = currentvec[1];
       PP0[0] = currentvec[0];
       PP0[1] = 0;
       PP0[3] = 0;
       PP0[5] = 0;
       PP0[7] = 1;
           
       
       if (vectornum === 1023) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
                  $fclose(outC);   
         $stop;
       end
    end
    

    always @(negedge clk) begin
       $fwrite(outC, "%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h\n", 
      C0, C1, C10, C11, C12, C2, 
      C3, C4, C5, C6, C7, C8, C9, S0, S1, S10, S11, S12, S2, S3, S4, S5, S6, 
      S7, S8, S9);
       vectornum = vectornum + 1;
    end
endmodule
module testbenchPPRfunct();

  logic clk;
  logic [8:0] PP0,PP1,PP2,PP3;
  logic Sign0;
  logic Sign1;
  logic Sign2;
  logic C0;
  logic C1;
  logic C10;
  logic C11;
  logic C12;
  logic C2;
  logic C3;
  logic C4;
  logic C5;
  logic C6;
  logic C7;
  logic C8;
  logic C9;
  logic S0;
  logic S1;
  logic S10;
  logic S11;
  logic S12;
  logic S2;
  logic S3;
  logic S4;
  logic S5;
  logic S6;
  logic S7;
  logic S8;
  logic S9;
    
    logic [9:0] vectors[1023:0], currentvec;
    logic [11:0] vectornum, errors;
    integer outC;
    

    functPPR dut(PP0, PP1, PP2, PP3, Sign0, Sign1, Sign2, C0, C1, C10, C11, C12, C2, 
      C3, C4, C5, C6, C7, C8, C9, S0, S1, S10, S11, S12, S2, S3, S4, S5, S6, 
      S7, S8, S9);
    

    initial begin
       $readmemb("lakis.txt", vectors);
       outC = $fopen("checkOUT.txt","w");
       vectornum = 0; errors = 0;
    end

    always begin
       clk = 1; #10; clk = 0; #10;
    end
      

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
       $display("%h%h%h%h%h%h%h%h%h%h", 
       currentvec[9], 
       currentvec[8] ,
       currentvec[7] ,
       currentvec[6] ,
       currentvec[5] ,
       currentvec[4] ,
       currentvec[3] ,
       currentvec[2] ,
       currentvec[1] ,
       currentvec[0] );

       PP3[8] = 0;
       PP3[6] = 0;
       PP3[4] = 1;
       PP3[2] = 0;
       PP3[0] = 0;
       PP3[1] = 1;
       PP3[3] = 0;
       PP3[5] = 0;
       PP3[7] = 0;
       

       Sign2= 1;
       PP2[8] = 0;
       PP2[6] = currentvec[9];
       PP2[4] = currentvec[8];
       PP2[2] = currentvec[7];
       PP2[0] = currentvec[6];
       PP2[1] = 1;
       PP2[3] = 1;
       PP2[5] = 1;
       PP2[7] = 1;

       Sign1 = 0;
       PP1[8] = 0;
       PP1[6] = 0;
       PP1[4] = 1;
       PP1[2] = 0;
       PP1[0] = 0;
       PP1[1] = 1;
       PP1[3] = 0;
       PP1[5] = 0;
       PP1[7] = 0;

       Sign0 = currentvec[5];
       PP0[8] = currentvec[4];
       PP0[6] = currentvec[3];
       PP0[4] = currentvec[2];
       PP0[2] = currentvec[1];
       PP0[0] = currentvec[0];
       PP0[1] = 0;
       PP0[3] = 0;
       PP0[5] = 0;
       PP0[7] = 1;
           
       
       if (vectornum === 1023) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
                  $fclose(outC);   
         $stop;
       end
    end
    

    always @(negedge clk) begin
       $fwrite(outC, "%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h%h\n", 
      C0, C1, C10, C11, C12, C2, 
      C3, C4, C5, C6, C7, C8, C9, S0, S1, S10, S11, S12, S2, S3, S4, S5, S6, 
      S7, S8, S9);
       vectornum = vectornum + 1;
    end
endmodule