data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:42: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("secuencia_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:43: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #5   reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #15  reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #450 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-4_secuencias/secuencia_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #20  reset = 0;\n        ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();

    reg ck = 0;
    reg reset = 0;
    reg x = 0;
    wire z_mealy;
    wire z_moore;


    reg [0:31] in = 32'b00100111_00001110_10010010_01010011;
    integer n = 32;
    integer i = 0;


    seq_mealy uut_mealy (ck, reset, x, z_mealy);
    seq_moore uut_moore (ck, reset, x, z_moore);


    initial begin
        $dumpfile("secuencia_tb.vcd");
        $dumpvars(0, test);
    end


    always begin
        #10

        ck = 0;
        x = in[i];

        #10

        ck = 1;
        i = i + 1;
        if (i == n)
            $finish;
    end



    initial begin
        #5   reset = 1;
        #15  reset = 0;
        #450 reset = 1;
        #20  reset = 0;
    end
endmodule
module test ();


    reg ck = 0;
    reg reset = 0;
    reg x = 0;
    wire z_mealy;
    wire z_moore;


    reg [0:31] in = 32'b00100111_00001110_10010010_01010011;
    integer n = 32;
    integer i = 0;


    seq_mealy uut_mealy (ck, reset, x, z_mealy);
    seq_moore uut_moore (ck, reset, x, z_moore);


    initial begin
        $dumpfile("secuencia_tb.vcd");
        $dumpvars(0, test);
    end


    always begin
        #10

        ck = 0;
        x = in[i];

        #10

        ck = 1;
        i = i + 1;
        if (i == n)
            $finish;
    end



    initial begin
        #5   reset = 1;
        #15  reset = 0;
        #450 reset = 1;
        #20  reset = 0;
    end
endmodule