data/full_repos/permissive/128659832/verilog/WAIT_tb.v
 line:32 column:21: Illegal character "'"
1: b'%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/WAIT_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/128659832/verilog/WAIT_tb.v:27: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile(  "WAIT_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/128659832/verilog/WAIT_tb.v:28: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, WAIT_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/WAIT_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #4  rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/WAIT_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #4  din = 8\'h 03;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/WAIT_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #4  start = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/WAIT_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #2  start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/WAIT_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #500 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module WAIT_tb;


	reg [7:0]  din = 0;
	reg        start = 0;

	wire       busy;

	reg        clk = 0;
	reg        rst = 1;


    WAIT WAIT0 (
        .din(din),
        .start(start),
        .busy(busy),
        .clk(clk),
        .rst(rst)
    );


    always #1 clk = ~clk;


    initial begin

        $dumpfile(  "WAIT_tb.vcd");
        $dumpvars(0, WAIT_tb);

        #4  rst = 0;

        #4  din = 8'h 03;

        #4  start = 1;
        #2  start = 0;

        #500 $finish;
    end

endmodule
module WAIT_tb;



	reg [7:0]  din = 0;
	reg        start = 0;

	wire       busy;

	reg        clk = 0;
	reg        rst = 1;


    WAIT WAIT0 (
        .din(din),
        .start(start),
        .busy(busy),
        .clk(clk),
        .rst(rst)
    );


    always #1 clk = ~clk;


    initial begin

        $dumpfile(  "WAIT_tb.vcd");
        $dumpvars(0, WAIT_tb);

        #4  rst = 0;

        #4  din = 8'h 03;

        #4  start = 1;
        #2  start = 0;

        #500 $finish;
    end

endmodule