data/full_repos/permissive/135820056/sys/video_freak.sv
 line:47: before: "reg"
1: b'%Error: data/full_repos/permissive/135820056/sys/video_freak.sv:165: Cannot find file containing module: \'sys_udiv\'\nsys_udiv #(24,12) div(CLK_VIDEO,div_start,div_run, div_num,div_den,div_res);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135820056/sys,data/full_repos/permissive/135820056/sys_udiv\n             data/full_repos/permissive/135820056/sys,data/full_repos/permissive/135820056/sys_udiv.v\n             data/full_repos/permissive/135820056/sys,data/full_repos/permissive/135820056/sys_udiv.sv\n             sys_udiv\n             sys_udiv.v\n             sys_udiv.sv\n             obj_dir/sys_udiv\n             obj_dir/sys_udiv.v\n             obj_dir/sys_udiv.sv\n%Error: data/full_repos/permissive/135820056/sys/video_freak.sv:171: Cannot find file containing module: \'sys_umul\'\nsys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);\n^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:185: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'arx_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n  arxf <= arx_i;\n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:186: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'ary_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n  aryf <= ary_i;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:192: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'HDMI_HEIGHT\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     div_num   <= HDMI_HEIGHT;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:200: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'arx_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     arxf      <= arx_i;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:201: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'ary_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     aryf      <= ary_i;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:197: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n   1: if(!div_res[11:0]) begin\n         ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:212: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'ary_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     if(!ary_i) begin\n        ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:237: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     mul_arg2  <= div_res[11:0] ? div_res[11:0] : 12\'d1;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:241: Operator LTE expects 24 bits on the RHS, but RHS\'s VARREF \'HDMI_WIDTH\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n   7: if(mul_res <= HDMI_WIDTH) begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:246: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'HDMI_WIDTH\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     div_num   <= HDMI_WIDTH;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:253: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s SEL generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n     mul_arg2  <= div_res[11:0] ? div_res[11:0] : 12\'d1;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:184: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'SCALE\' generates 3 bits.\n                                                                           : ... In instance video_freak.scale\n if (!SCALE || (!ary_i && arx_i)) begin\n     ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:184: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'ary_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n if (!SCALE || (!ary_i && arx_i)) begin\n                ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:184: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'arx_i\' generates 12 bits.\n                                                                           : ... In instance video_freak.scale\n if (!SCALE || (!ary_i && arx_i)) begin\n                       ^~\n%Error: data/full_repos/permissive/135820056/sys/video_freak.sv:39: Cannot find file containing module: \'sys_umul\'\nsys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);\n^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:68: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'vcpt\' generates 12 bits.\n                                                                          : ... In instance video_freak\n   if(!vcpt) hsize <= hcpt;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:76: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'vcrop\' generates 12 bits.\n                                                                          : ... In instance video_freak\n vsize <= vcrop ? vcrop : vtot;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:84: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'vcalc\' generates 2 bits.\n                                                                          : ... In instance video_freak\n else if (vcalc) begin\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:80: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'vcrop\' generates 12 bits.\n                                                                          : ... In instance video_freak\n if(!vcrop || !ary || !arx) begin\n    ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:80: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'ary\' generates 12 bits.\n                                                                          : ... In instance video_freak\n if(!vcrop || !ary || !arx) begin\n              ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:80: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'arx\' generates 12 bits.\n                                                                          : ... In instance video_freak\n if(!vcrop || !ary || !arx) begin\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:117: Operator COND expects 12 bits on the Conditional False, but Conditional False\'s SEL generates 11 bits.\n                                                                           : ... In instance video_freak\n voff <= vadj[11] ? 12\'d0 : ((vadj[11:1] + vcrop) > vtot) ? vtot-vcrop : vadj[11:1];\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freak.sv:118: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'vcrop\' generates 12 bits.\n                                                                           : ... In instance video_freak\n ovde <= ((vcpt >= voff) && (vcpt < (vcrop + voff))) || !vcrop;\n                                                        ^\n%Error: Exiting due to 3 error(s), 22 warning(s)\n'
module video_freak
(
	input             CLK_VIDEO,
	input             CE_PIXEL,
	input             VGA_VS,
	input      [11:0] HDMI_WIDTH,
	input      [11:0] HDMI_HEIGHT,
	output            VGA_DE,
	output reg [12:0] VIDEO_ARX,
	output reg [12:0] VIDEO_ARY,

	input             VGA_DE_IN,
	input      [11:0] ARX,
	input      [11:0] ARY,
	input      [11:0] CROP_SIZE,
	input       [4:0] CROP_OFF,
	input       [2:0] SCALE
);

reg         mul_start;
wire        mul_run;
reg  [11:0] mul_arg1, mul_arg2;
wire [23:0] mul_res;
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);

reg        vde;
reg [11:0] arxo,aryo;
reg [11:0] vsize;
reg [11:0] hsize;

always @(posedge CLK_VIDEO) begin
	reg        old_de, old_vs,ovde;
	reg [11:0] vtot,vcpt,vcrop,voff;
	reg [11:0] hcpt;
	reg [11:0] vadj;
	reg [23:0] ARXG,ARYG;
	reg [11:0] arx,ary;
	reg  [1:0] vcalc;

	if (CE_PIXEL) begin
		old_de <= VGA_DE_IN;
		old_vs <= VGA_VS;
		if (VGA_VS & ~old_vs) begin
			vcpt  <= 0;
			vtot  <= vcpt;
			vcalc <= 1;
			vcrop <= (CROP_SIZE >= vcpt) ? 12'd0 : CROP_SIZE;
		end
		
		if (VGA_DE_IN) hcpt <= hcpt + 1'd1;
		if (~VGA_DE_IN & old_de) begin
			vcpt <= vcpt + 1'd1;
			if(!vcpt) hsize <= hcpt;
			hcpt <= 0;
		end
	end

	arx <= ARX;
	ary <= ARY;

	vsize <= vcrop ? vcrop : vtot;
	
	mul_start <= 0;

	if(!vcrop || !ary || !arx) begin
		arxo  <= arx;
		aryo  <= ary;
	end
	else if (vcalc) begin
		if(~mul_start & ~mul_run) begin
			vcalc <= vcalc + 1'd1;
			case(vcalc)
				1: begin
						mul_arg1  <= arx;
						mul_arg2  <= vtot;
						mul_start <= 1;
					end

				2: begin
						ARXG      <= mul_res;
						mul_arg1  <= ary;
						mul_arg2  <= vcrop;
						mul_start <= 1;
					end

				3: begin
						ARYG      <= mul_res;
					end
			endcase
		end
	end
	else if (ARXG[23] | ARYG[23]) begin
		arxo <= ARXG[23:12];
		aryo <= ARYG[23:12];
	end
	else begin
		ARXG <= ARXG << 1;
		ARYG <= ARYG << 1;
	end

	vadj <= (vtot-vcrop) + {{6{CROP_OFF[4]}},CROP_OFF,1'b0};
	voff <= vadj[11] ? 12'd0 : ((vadj[11:1] + vcrop) > vtot) ? vtot-vcrop : vadj[11:1];
	ovde <= ((vcpt >= voff) && (vcpt < (vcrop + voff))) || !vcrop;
	vde  <= ovde;
end

assign VGA_DE = vde & VGA_DE_IN;

video_scale_int scale
(
	.CLK_VIDEO(CLK_VIDEO),
	.HDMI_WIDTH(HDMI_WIDTH),
	.HDMI_HEIGHT(HDMI_HEIGHT),
	.SCALE(SCALE),
	.hsize(hsize),
	.vsize(vsize),
	.arx_i(arxo),
	.ary_i(aryo),
	.arx_o(VIDEO_ARX),
	.ary_o(VIDEO_ARY)
);

endmodule
module video_freak
(
	input             CLK_VIDEO,
	input             CE_PIXEL,
	input             VGA_VS,
	input      [11:0] HDMI_WIDTH,
	input      [11:0] HDMI_HEIGHT,
	output            VGA_DE,
	output reg [12:0] VIDEO_ARX,
	output reg [12:0] VIDEO_ARY,

	input             VGA_DE_IN,
	input      [11:0] ARX,
	input      [11:0] ARY,
	input      [11:0] CROP_SIZE,
	input       [4:0] CROP_OFF,
	input       [2:0] SCALE
);


reg         mul_start;
wire        mul_run;
reg  [11:0] mul_arg1, mul_arg2;
wire [23:0] mul_res;
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);

reg        vde;
reg [11:0] arxo,aryo;
reg [11:0] vsize;
reg [11:0] hsize;

always @(posedge CLK_VIDEO) begin
	reg        old_de, old_vs,ovde;
	reg [11:0] vtot,vcpt,vcrop,voff;
	reg [11:0] hcpt;
	reg [11:0] vadj;
	reg [23:0] ARXG,ARYG;
	reg [11:0] arx,ary;
	reg  [1:0] vcalc;

	if (CE_PIXEL) begin
		old_de <= VGA_DE_IN;
		old_vs <= VGA_VS;
		if (VGA_VS & ~old_vs) begin
			vcpt  <= 0;
			vtot  <= vcpt;
			vcalc <= 1;
			vcrop <= (CROP_SIZE >= vcpt) ? 12'd0 : CROP_SIZE;
		end
		
		if (VGA_DE_IN) hcpt <= hcpt + 1'd1;
		if (~VGA_DE_IN & old_de) begin
			vcpt <= vcpt + 1'd1;
			if(!vcpt) hsize <= hcpt;
			hcpt <= 0;
		end
	end

	arx <= ARX;
	ary <= ARY;

	vsize <= vcrop ? vcrop : vtot;
	
	mul_start <= 0;

	if(!vcrop || !ary || !arx) begin
		arxo  <= arx;
		aryo  <= ary;
	end
	else if (vcalc) begin
		if(~mul_start & ~mul_run) begin
			vcalc <= vcalc + 1'd1;
			case(vcalc)
				1: begin
						mul_arg1  <= arx;
						mul_arg2  <= vtot;
						mul_start <= 1;
					end

				2: begin
						ARXG      <= mul_res;
						mul_arg1  <= ary;
						mul_arg2  <= vcrop;
						mul_start <= 1;
					end

				3: begin
						ARYG      <= mul_res;
					end
			endcase
		end
	end
	else if (ARXG[23] | ARYG[23]) begin
		arxo <= ARXG[23:12];
		aryo <= ARYG[23:12];
	end
	else begin
		ARXG <= ARXG << 1;
		ARYG <= ARYG << 1;
	end

	vadj <= (vtot-vcrop) + {{6{CROP_OFF[4]}},CROP_OFF,1'b0};
	voff <= vadj[11] ? 12'd0 : ((vadj[11:1] + vcrop) > vtot) ? vtot-vcrop : vadj[11:1];
	ovde <= ((vcpt >= voff) && (vcpt < (vcrop + voff))) || !vcrop;
	vde  <= ovde;
end

assign VGA_DE = vde & VGA_DE_IN;

video_scale_int scale
(
	.CLK_VIDEO(CLK_VIDEO),
	.HDMI_WIDTH(HDMI_WIDTH),
	.HDMI_HEIGHT(HDMI_HEIGHT),
	.SCALE(SCALE),
	.hsize(hsize),
	.vsize(vsize),
	.arx_i(arxo),
	.ary_i(aryo),
	.arx_o(VIDEO_ARX),
	.ary_o(VIDEO_ARY)
);

endmodule