data/full_repos/permissive/167489907/Memory/Register File/regfile32x64.v
1: b'%Error: Cannot find file containing module: File,data/full_repos/permissive/167489907\n        ... Looked in:\n             data/full_repos/permissive/167489907/Memory/Register/File,data/full_repos/permissive/167489907\n             data/full_repos/permissive/167489907/Memory/Register/File,data/full_repos/permissive/167489907.v\n             data/full_repos/permissive/167489907/Memory/Register/File,data/full_repos/permissive/167489907.sv\n             File,data/full_repos/permissive/167489907\n             File,data/full_repos/permissive/167489907.v\n             File,data/full_repos/permissive/167489907.sv\n             obj_dir/File,data/full_repos/permissive/167489907\n             obj_dir/File,data/full_repos/permissive/167489907.v\n             obj_dir/File,data/full_repos/permissive/167489907.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/167489907/Memory/Register\n%Error: Cannot find file containing module: File/regfile32x64.v\n%Error: Exiting due to 3 error(s)\n'
module regfile32x64(
	input clk,
	input write,
	input reset,
	input [4:0] wrAddr,
	input [63:0] wrData,
   input [4:0] rdAddrA,
   output [63:0] rdDataA,
   input [4:0] rdAddrB,
   output [63:0] rdDataB,
	output [15:0] r0, r1, r2, r3, r4, r5, r6, r7);





				 
reg [63:0] reg0, reg1,  reg2, reg3, reg4, reg5, reg6, reg7, 
			  reg8, reg9, reg10,reg11,reg12,reg13,reg14,reg15,
			  reg16,reg17,reg18,reg19,reg20,reg21,reg22,reg23,
			  reg24,reg25,reg26,reg27,reg28,reg29,reg30,reg31;
assign rdDataA = rdAddrA == 0  ? reg0  :
					  rdAddrA == 1  ? reg1  :
					  rdAddrA == 2  ? reg2  :
					  rdAddrA == 3  ? reg3  :
					  rdAddrA == 4  ? reg4  :
					  rdAddrA == 5  ? reg5  :
					  rdAddrA == 6  ? reg6  :
					  rdAddrA == 7  ? reg7  :
					  rdAddrA == 8  ? reg8  :
					  rdAddrA == 9  ? reg9  :
					  rdAddrA == 10 ? reg10 :
					  rdAddrA == 11 ? reg11 :
					  rdAddrA == 12 ? reg12 :
					  rdAddrA == 13 ? reg13 :
					  rdAddrA == 14 ? reg14 :
					  rdAddrA == 15 ? reg15 :
					  rdAddrA == 16 ? reg16 :
					  rdAddrA == 17 ? reg17 :
					  rdAddrA == 18 ? reg18 :
					  rdAddrA == 19 ? reg19 :
					  rdAddrA == 20 ? reg20 :
					  rdAddrA == 21 ? reg21 :
					  rdAddrA == 22 ? reg22 :
					  rdAddrA == 23 ? reg23 :
					  rdAddrA == 24 ? reg24 :
					  rdAddrA == 25 ? reg25 :
					  rdAddrA == 26 ? reg26 :
					  rdAddrA == 27 ? reg27 :
					  rdAddrA == 28 ? reg28 :
					  rdAddrA == 29 ? reg29 :
					  rdAddrA == 30 ? reg30 : 0;
assign rdDataB = rdAddrB == 0  ? reg0  :
					  rdAddrB == 1  ? reg1  :
					  rdAddrB == 2  ? reg2  :
					  rdAddrB == 3  ? reg3  :
					  rdAddrB == 4  ? reg4  :
					  rdAddrB == 5  ? reg5  :
					  rdAddrB == 6  ? reg6  :
					  rdAddrB == 7  ? reg7  :
					  rdAddrB == 8  ? reg8  :
					  rdAddrB == 9  ? reg9  :
					  rdAddrB == 10 ? reg10 :
					  rdAddrB == 11 ? reg11 :
					  rdAddrB == 12 ? reg12 :
					  rdAddrB == 13 ? reg13 :
					  rdAddrB == 14 ? reg14 :
					  rdAddrB == 15 ? reg15 :
					  rdAddrB == 16 ? reg16 :
					  rdAddrB == 17 ? reg17 :
					  rdAddrB == 18 ? reg18 :
					  rdAddrB == 19 ? reg19 :
					  rdAddrB == 20 ? reg20 :
					  rdAddrB == 21 ? reg21 :
					  rdAddrB == 22 ? reg22 :
					  rdAddrB == 23 ? reg23 :
					  rdAddrB == 24 ? reg24 :
					  rdAddrB == 25 ? reg25 :
					  rdAddrB == 26 ? reg26 :
					  rdAddrB == 27 ? reg27 :
					  rdAddrB == 28 ? reg28 :
					  rdAddrB == 29 ? reg29 :
					  rdAddrB == 30 ? reg30 : 0;

always @(posedge clk or posedge reset) 
	if (reset) begin
		reg0 <= 0; reg1 <= 0; reg2 <= 0; reg3 <= 0;
		reg4 <= 0; reg5 <= 0; reg6 <= 0; reg7 <= 0;
		reg8 <= 0; reg9 <= 0; reg10 <= 0; reg11 <= 0;
		reg12 <= 0; reg13 <= 0; reg14 <= 0; reg15 <= 0;
		reg16 <= 0; reg17 <= 0; reg18 <= 0; reg19 <= 0;
		reg20 <= 0; reg21 <= 0; reg22 <= 0; reg23 <= 0;
		reg24 <= 0; reg25 <= 0; reg26 <= 0; reg27 <= 0;
		reg28 <= 0; reg29 <= 0; reg30 <= 0; reg31 <= 0;
	end else if (write) begin
		case(wrAddr)
			0: begin
				reg0 <= wrData;
			end
			1: begin
				reg1 <= wrData;
			end
			2: begin
				reg2 <= wrData;
			end
			3: begin
				reg3 <= wrData;
			end
			4: begin
				reg4 <= wrData;
			end
			5: begin
				reg5 <= wrData;
			end
			6: begin
				reg6 <= wrData;
			end
			7: begin
				reg7 <= wrData;
			end
			8: begin
				reg8 <= wrData;
			end
			9: begin
				reg9 <= wrData;
			end
			10: begin
				reg10 <= wrData;
			end
			11: begin
				reg11 <= wrData;
			end
			12: begin
				reg12 <= wrData;
			end
			13: begin
				reg13 <= wrData;
			end
			14: begin
				reg14 <= wrData;
			end
			15: begin
				reg15 <= wrData;
			end
			16: begin
				reg16 <= wrData;
			end
			17: begin
				reg17 <= wrData;
			end
			18: begin
				reg18 <= wrData;
			end
			19: begin
				reg19 <= wrData;
			end
			20: begin
				reg20 <= wrData;
			end
			21: begin
				reg21 <= wrData;
			end
			22: begin
				reg22 <= wrData;
			end
			23: begin
				reg23 <= wrData;
			end
			24: begin
				reg24 <= wrData;
			end
			25: begin
				reg25 <= wrData;
			end
			26: begin
				reg26 <= wrData;
			end
			27: begin
				reg27 <= wrData;
			end
			28: begin
				reg28 <= wrData;
			end
			29: begin
				reg29 <= wrData;
			end
			30: begin
				reg30 <= wrData;
			end
		endcase
	end
	
	assign r0 = reg0[15:0];
	assign r1 = reg1[15:0];
	assign r2 = reg2[15:0];
	assign r3 = reg3[15:0];
	assign r4 = reg4[15:0];
	assign r5 = reg5[15:0];
	assign r6 = reg6[15:0];
	assign r7 = reg7[15:0];

endmodule
module regfile32x64(
	input clk,
	input write,
	input reset,
	input [4:0] wrAddr,
	input [63:0] wrData,
   input [4:0] rdAddrA,
   output [63:0] rdDataA,
   input [4:0] rdAddrB,
   output [63:0] rdDataB,
	output [15:0] r0, r1, r2, r3, r4, r5, r6, r7);






				 
reg [63:0] reg0, reg1,  reg2, reg3, reg4, reg5, reg6, reg7, 
			  reg8, reg9, reg10,reg11,reg12,reg13,reg14,reg15,
			  reg16,reg17,reg18,reg19,reg20,reg21,reg22,reg23,
			  reg24,reg25,reg26,reg27,reg28,reg29,reg30,reg31;
assign rdDataA = rdAddrA == 0  ? reg0  :
					  rdAddrA == 1  ? reg1  :
					  rdAddrA == 2  ? reg2  :
					  rdAddrA == 3  ? reg3  :
					  rdAddrA == 4  ? reg4  :
					  rdAddrA == 5  ? reg5  :
					  rdAddrA == 6  ? reg6  :
					  rdAddrA == 7  ? reg7  :
					  rdAddrA == 8  ? reg8  :
					  rdAddrA == 9  ? reg9  :
					  rdAddrA == 10 ? reg10 :
					  rdAddrA == 11 ? reg11 :
					  rdAddrA == 12 ? reg12 :
					  rdAddrA == 13 ? reg13 :
					  rdAddrA == 14 ? reg14 :
					  rdAddrA == 15 ? reg15 :
					  rdAddrA == 16 ? reg16 :
					  rdAddrA == 17 ? reg17 :
					  rdAddrA == 18 ? reg18 :
					  rdAddrA == 19 ? reg19 :
					  rdAddrA == 20 ? reg20 :
					  rdAddrA == 21 ? reg21 :
					  rdAddrA == 22 ? reg22 :
					  rdAddrA == 23 ? reg23 :
					  rdAddrA == 24 ? reg24 :
					  rdAddrA == 25 ? reg25 :
					  rdAddrA == 26 ? reg26 :
					  rdAddrA == 27 ? reg27 :
					  rdAddrA == 28 ? reg28 :
					  rdAddrA == 29 ? reg29 :
					  rdAddrA == 30 ? reg30 : 0;
assign rdDataB = rdAddrB == 0  ? reg0  :
					  rdAddrB == 1  ? reg1  :
					  rdAddrB == 2  ? reg2  :
					  rdAddrB == 3  ? reg3  :
					  rdAddrB == 4  ? reg4  :
					  rdAddrB == 5  ? reg5  :
					  rdAddrB == 6  ? reg6  :
					  rdAddrB == 7  ? reg7  :
					  rdAddrB == 8  ? reg8  :
					  rdAddrB == 9  ? reg9  :
					  rdAddrB == 10 ? reg10 :
					  rdAddrB == 11 ? reg11 :
					  rdAddrB == 12 ? reg12 :
					  rdAddrB == 13 ? reg13 :
					  rdAddrB == 14 ? reg14 :
					  rdAddrB == 15 ? reg15 :
					  rdAddrB == 16 ? reg16 :
					  rdAddrB == 17 ? reg17 :
					  rdAddrB == 18 ? reg18 :
					  rdAddrB == 19 ? reg19 :
					  rdAddrB == 20 ? reg20 :
					  rdAddrB == 21 ? reg21 :
					  rdAddrB == 22 ? reg22 :
					  rdAddrB == 23 ? reg23 :
					  rdAddrB == 24 ? reg24 :
					  rdAddrB == 25 ? reg25 :
					  rdAddrB == 26 ? reg26 :
					  rdAddrB == 27 ? reg27 :
					  rdAddrB == 28 ? reg28 :
					  rdAddrB == 29 ? reg29 :
					  rdAddrB == 30 ? reg30 : 0;

always @(posedge clk or posedge reset) 
	if (reset) begin
		reg0 <= 0; reg1 <= 0; reg2 <= 0; reg3 <= 0;
		reg4 <= 0; reg5 <= 0; reg6 <= 0; reg7 <= 0;
		reg8 <= 0; reg9 <= 0; reg10 <= 0; reg11 <= 0;
		reg12 <= 0; reg13 <= 0; reg14 <= 0; reg15 <= 0;
		reg16 <= 0; reg17 <= 0; reg18 <= 0; reg19 <= 0;
		reg20 <= 0; reg21 <= 0; reg22 <= 0; reg23 <= 0;
		reg24 <= 0; reg25 <= 0; reg26 <= 0; reg27 <= 0;
		reg28 <= 0; reg29 <= 0; reg30 <= 0; reg31 <= 0;
	end else if (write) begin
		case(wrAddr)
			0: begin
				reg0 <= wrData;
			end
			1: begin
				reg1 <= wrData;
			end
			2: begin
				reg2 <= wrData;
			end
			3: begin
				reg3 <= wrData;
			end
			4: begin
				reg4 <= wrData;
			end
			5: begin
				reg5 <= wrData;
			end
			6: begin
				reg6 <= wrData;
			end
			7: begin
				reg7 <= wrData;
			end
			8: begin
				reg8 <= wrData;
			end
			9: begin
				reg9 <= wrData;
			end
			10: begin
				reg10 <= wrData;
			end
			11: begin
				reg11 <= wrData;
			end
			12: begin
				reg12 <= wrData;
			end
			13: begin
				reg13 <= wrData;
			end
			14: begin
				reg14 <= wrData;
			end
			15: begin
				reg15 <= wrData;
			end
			16: begin
				reg16 <= wrData;
			end
			17: begin
				reg17 <= wrData;
			end
			18: begin
				reg18 <= wrData;
			end
			19: begin
				reg19 <= wrData;
			end
			20: begin
				reg20 <= wrData;
			end
			21: begin
				reg21 <= wrData;
			end
			22: begin
				reg22 <= wrData;
			end
			23: begin
				reg23 <= wrData;
			end
			24: begin
				reg24 <= wrData;
			end
			25: begin
				reg25 <= wrData;
			end
			26: begin
				reg26 <= wrData;
			end
			27: begin
				reg27 <= wrData;
			end
			28: begin
				reg28 <= wrData;
			end
			29: begin
				reg29 <= wrData;
			end
			30: begin
				reg30 <= wrData;
			end
		endcase
	end
	
	assign r0 = reg0[15:0];
	assign r1 = reg1[15:0];
	assign r2 = reg2[15:0];
	assign r3 = reg3[15:0];
	assign r4 = reg4[15:0];
	assign r5 = reg5[15:0];
	assign r6 = reg6[15:0];
	assign r7 = reg7[15:0];

endmodule