data/full_repos/permissive/12880408/proc.v
 line:143: before: ":"
1: b"%Error: data/full_repos/permissive/12880408/proc.v:231: syntax error, unexpected default\n    default:\n    ^~~~~~~\n%Error: data/full_repos/permissive/12880408/proc.v:245: syntax error, unexpected endcase\n   endcase\n   ^~~~~~~\n%Error: data/full_repos/permissive/12880408/proc.v:275: syntax error, unexpected endcase\n  endcase\n  ^~~~~~~\n%Error: data/full_repos/permissive/12880408/proc.v:363: syntax error, unexpected '=', expecting IDENTIFIER\n   Rin = Rin | regX;\n       ^\n%Error: data/full_repos/permissive/12880408/proc.v:367: syntax error, unexpected '=', expecting IDENTIFIER\n   Rin = Rin | regY;\n       ^\n%Error: data/full_repos/permissive/12880408/proc.v:375: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n   reg1: BusWires <= R1;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/12880408/proc.v:376: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n   reg2: BusWires <= R2;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/12880408/proc.v:377: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n   reg3: BusWires <= R3;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/12880408/proc.v:378: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n   reg4: BusWires <= R4;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/12880408/proc.v:379: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n   reg5: BusWires <= R5;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/12880408/proc.v:380: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n   reg6: BusWires <= R6;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/12880408/proc.v:381: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n   reg7: BusWires <= R7;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/12880408/proc.v:382: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n   gout: BusWires <= GoutWires;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/12880408/proc.v:383: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n   dinout: BusWires <= DIN;\n           ^~~~~~~~\n%Error: Cannot continue\n"
module proc (DIN, Resetn, Clock, Run, Done, DOUT, ADDR, W);
	input [8:0] DIN;
	input Resetn, Clock, Run;
	output reg Done, W;
	output reg [8:0] DOUT, ADDR;


	parameter T0 = 3'b000, T1 = 3'b001, T2 = 3'b010, T3 = 3'b011, T4 = 3'b100;
	parameter mv = 3'b000, mvi = 3'b001, add = 3'b010, sub = 3'b011, ld = 3'b100, st = 3'b101, mvnz = 3'b110;
	parameter reg0 = 10'b1000000000,
				 reg1 = 10'b0100000000,
				 reg2 = 10'b0010000000,
				 reg3 = 10'b0001000000,
				 reg4 = 10'b0000100000,
				 reg5 = 10'b0000010000,
				 reg6 = 10'b0000001000,
				 reg7 = 10'b0000000100,
				 gout = 10'b0000000010,
				 dinout = 10'b0000000001;
	

	reg [1:0] Tstep_Q;
	reg [1:0] Tstep_D;
	wire [2:0] I;
	wire [0:7] regX, regY;
	wire [8:0] IRoutWires;
	wire [8:0] GinWires, GoutWires;
	wire [8:0] AoutWires;
	wire GNZ;
	and(GNZ, GoutWires[0],
				GoutWires[1],
				GoutWires[2],
				GoutWires[3],
				GoutWires[4],
				GoutWires[5],
				GoutWires[6],
				GoutWires[7],
				GoutWires[8]
	);

	reg [0:7] Rin;
	reg [0:9] busDriver;
	

	reg IRin, DINout, RYout, RYin, RXout, RXin, Ain, Gin, Gout, AddSub,
		 PCincr, ADDRin, DOUTin;
 
	assign I = IRoutWires[8:6];
	dec3to8 decX (IRoutWires[5:3], 1'b1, regX);
	dec3to8 decY (IRoutWires[2:0], 1'b1, regY);
		

    always @(Tstep_Q, Run, Done)
    begin
		if(Done) begin
			Tstep_D <= T0;
		end
		else begin
        case (Tstep_Q)
            T0:
				begin
				if(!Run)
					Tstep_D <= T0;
				else
					Tstep_D <= T1;
				end
            T1:
				begin
					Tstep_D <= T2;
				end
				T2:
				begin
					Tstep_D <= T3;
				end
				T3:
				begin
					Tstep_D <= T4;
				end
				T4:
				begin
					Tstep_D <=T0;
				end
        endcase
	  end
    end


	always @(Tstep_Q or I or regX or regY)
	begin

		IRin <= 0;
		Done <= 0;
		DINout <= 0;
		RYout <= 0;
		RYin <= 0;
		RXout <= 0;
		RXin <= 0;
		Ain <= 0;
		Gin <= 0;
		Gout <= 0;
		AddSub <= 0;

		case (Tstep_Q)
		T0:
			begin

				PCout <= 1;
				ADDRin <= 1;
			end
		T1:
			begin
				IRin <=1;
				PCincr <=1;
		T2:
			case (I)
				mv: 
				begin
					RYout <= 1;
					RXin <= 1;
					Done <= 1;			
				end
				mvi:
				begin
					PCout <=1;
					ADDRin <=1;
				end
				add:
				begin
					RXout <= 1;
					Ain <= 1;
				end
				sub:
				begin
					RXout <= 1;
					Ain <= 1;
				end
				ld:
				begin
					RYout <=1;
					ADDRin <=1;
				end
				st:
				begin
					RYout <=1;
					ADDRin <=1;
				end
				mvnz:
				begin
					if(GNZ)
					begin
						RYout <=1;
						ADDRin <=1;
					end
					else Done <= 1;
				end
				default:
				begin
				IRin <= 0;
				Done <= 0;
				DINout <= 0;
				RYout <= 0;
				RYin <= 0;
				RXout <= 0;
				RXin <= 0;
				Ain <= 0;
				Gin <= 0;
				Gout <= 0;
				AddSub <= 0;
				end
			endcase
		T3:
			case (I)
				mvi:
				begin	
					PCincr <=1;
					DINout <=1;
					RXin <=1;
					Done <=1;
				add:
				begin
					RYout <= 1;
					Gin <= 1;				
				end
				sub:
				begin
					RYout <= 1;
					Gin <= 1;
					AddSub <= 1;
				end
				ld:
				begin
					DINout <=1;
					RXin <=1;
					Done <=1;
				end
				st:
				begin	
					RXout <=1;
					DOUTin <=1;
					W_D <=1;
					Done <=1;
				default:
				begin
					IRin <= 0;
					Done <= 0;
					DINout <= 0;
					RYout <= 0;
					RYin <= 0;
					RXout <= 0;
					RXin <= 0;
					Ain <= 0;
					Gin <= 0;
					Gout <= 0;
					AddSub <= 0;
				end
			endcase
		T4:
			case (I)
				add:
				begin
					Done <= 1;
					Gout <= 1;
					RXin <= 1;
				end
				sub:
				begin
					Done <= 1;
					RXin <= 1;
					Gout <= 1;				
				end
				default:
				begin
					IRin <= 0;
					Done <= 0;
					DINout <= 0;
					RYout <= 0;
					RYin <= 0;
					RXout <= 0;
					RXin <= 0;
					Ain <= 0;
					Gin <= 0;
					Gout <= 0;
					AddSub <= 0;
				end
			endcase
		endcase
	end
	

	always @(posedge Clock, negedge Resetn) begin
		if (!Resetn) begin


		end
		else Tstep_Q <= Tstep_D;
		
	end
	

	

	wire [8:0] R0, R1, R2, R3, R4, R5, R6, R7;
	

	regn reg_0(BusWires, Rin[0], Clock, R0);

	regn reg_1(BusWires, Rin[1], Clock, R1);				
	
	regn reg_2(BusWires, Rin[2], Clock, R2);
				
	regn reg_3(BusWires, Rin[3], Clock, R3);
	
	regn reg_4(BusWires, Rin[4], Clock, R4);
	
	regn reg_5(BusWires, Rin[5], Clock, R5);
	
	regn reg_6(BusWires, Rin[6], Clock, R6);
	
	counter reg_pc(Clock, Resetn, PCincr, Rin[7], R7);
	

	regn reg_a(BusWires, Ain, Clock, AoutWires);
	


	regn reg_g(GinWires, Gin, Clock, GoutWires);
	

	regn reg_ir(DIN, IRin, Clock, IRoutWires);
	
	addsub Addsub(AddSub, AoutWires, BusWires, GinWires);
	

	always @ (RXout, RYout, Gout, DINout, regX, regY)
	begin


			if(DINout && !(RXout || RYout || Gout)) begin
				busDriver = 10'b0000000001;
			end
			else if(RXout && !(DINout || RYout || Gout)) begin
				busDriver = {regX, 1'b0, 1'b0};
			end
			else if(RYout && !(RXout || DINout || Gout)) begin
				busDriver = {regY, 1'b0, 1'b0};
			end
			else if(Gout && !(RXout || RYout || DINout)) begin
				busDriver = 10'b0000000010;
			end
			else begin
				$display("Ambiguous bus driver!! Setting to DINout\n");
				busDriver = 10'b0000000001;
			end
			
	end
	
	always @ (RXin, RYin, regX, regY)
	begin
		Rin = 8'b00000000;
		if(RXin) begin
			Rin = Rin | regX;
		end
		
		if(RYin) begin
			Rin = Rin | regY;
		end
	end
	

	always @ (busDriver, R0, R1, R2, R3, R4, R5, R6, R7, GoutWires, DIN) begin
		case(busDriver)
			reg0: BusWires <= R0;
			reg1: BusWires <= R1;
			reg2: BusWires <= R2;
			reg3: BusWires <= R3;
			reg4: BusWires <= R4;
			reg5: BusWires <= R5;
			reg6: BusWires <= R6;
			reg7: BusWires <= R7;
			gout: BusWires <= GoutWires;
			dinout: BusWires <= DIN;
			default:
			begin
				$display("Undefined bus driver!! Defaulting to DIN!!\n");
				BusWires <= DIN;
			end
		endcase
	end
	

	
	
endmodule
module proc (DIN, Resetn, Clock, Run, Done, DOUT, ADDR, W);

	input [8:0] DIN;
	input Resetn, Clock, Run;
	output reg Done, W;
	output reg [8:0] DOUT, ADDR;


	parameter T0 = 3'b000, T1 = 3'b001, T2 = 3'b010, T3 = 3'b011, T4 = 3'b100;
	parameter mv = 3'b000, mvi = 3'b001, add = 3'b010, sub = 3'b011, ld = 3'b100, st = 3'b101, mvnz = 3'b110;
	parameter reg0 = 10'b1000000000,
				 reg1 = 10'b0100000000,
				 reg2 = 10'b0010000000,
				 reg3 = 10'b0001000000,
				 reg4 = 10'b0000100000,
				 reg5 = 10'b0000010000,
				 reg6 = 10'b0000001000,
				 reg7 = 10'b0000000100,
				 gout = 10'b0000000010,
				 dinout = 10'b0000000001;
	

	reg [1:0] Tstep_Q;
	reg [1:0] Tstep_D;
	wire [2:0] I;
	wire [0:7] regX, regY;
	wire [8:0] IRoutWires;
	wire [8:0] GinWires, GoutWires;
	wire [8:0] AoutWires;
	wire GNZ;
	and(GNZ, GoutWires[0],
				GoutWires[1],
				GoutWires[2],
				GoutWires[3],
				GoutWires[4],
				GoutWires[5],
				GoutWires[6],
				GoutWires[7],
				GoutWires[8]
	);

	reg [0:7] Rin;
	reg [0:9] busDriver;
	

	reg IRin, DINout, RYout, RYin, RXout, RXin, Ain, Gin, Gout, AddSub,
		 PCincr, ADDRin, DOUTin;
 
	assign I = IRoutWires[8:6];
	dec3to8 decX (IRoutWires[5:3], 1'b1, regX);
	dec3to8 decY (IRoutWires[2:0], 1'b1, regY);
		

    always @(Tstep_Q, Run, Done)
    begin
		if(Done) begin
			Tstep_D <= T0;
		end
		else begin
        case (Tstep_Q)
            T0:
				begin
				if(!Run)
					Tstep_D <= T0;
				else
					Tstep_D <= T1;
				end
            T1:
				begin
					Tstep_D <= T2;
				end
				T2:
				begin
					Tstep_D <= T3;
				end
				T3:
				begin
					Tstep_D <= T4;
				end
				T4:
				begin
					Tstep_D <=T0;
				end
        endcase
	  end
    end


	always @(Tstep_Q or I or regX or regY)
	begin

		IRin <= 0;
		Done <= 0;
		DINout <= 0;
		RYout <= 0;
		RYin <= 0;
		RXout <= 0;
		RXin <= 0;
		Ain <= 0;
		Gin <= 0;
		Gout <= 0;
		AddSub <= 0;

		case (Tstep_Q)
		T0:
			begin

				PCout <= 1;
				ADDRin <= 1;
			end
		T1:
			begin
				IRin <=1;
				PCincr <=1;
		T2:
			case (I)
				mv: 
				begin
					RYout <= 1;
					RXin <= 1;
					Done <= 1;			
				end
				mvi:
				begin
					PCout <=1;
					ADDRin <=1;
				end
				add:
				begin
					RXout <= 1;
					Ain <= 1;
				end
				sub:
				begin
					RXout <= 1;
					Ain <= 1;
				end
				ld:
				begin
					RYout <=1;
					ADDRin <=1;
				end
				st:
				begin
					RYout <=1;
					ADDRin <=1;
				end
				mvnz:
				begin
					if(GNZ)
					begin
						RYout <=1;
						ADDRin <=1;
					end
					else Done <= 1;
				end
				default:
				begin
				IRin <= 0;
				Done <= 0;
				DINout <= 0;
				RYout <= 0;
				RYin <= 0;
				RXout <= 0;
				RXin <= 0;
				Ain <= 0;
				Gin <= 0;
				Gout <= 0;
				AddSub <= 0;
				end
			endcase
		T3:
			case (I)
				mvi:
				begin	
					PCincr <=1;
					DINout <=1;
					RXin <=1;
					Done <=1;
				add:
				begin
					RYout <= 1;
					Gin <= 1;				
				end
				sub:
				begin
					RYout <= 1;
					Gin <= 1;
					AddSub <= 1;
				end
				ld:
				begin
					DINout <=1;
					RXin <=1;
					Done <=1;
				end
				st:
				begin	
					RXout <=1;
					DOUTin <=1;
					W_D <=1;
					Done <=1;
				default:
				begin
					IRin <= 0;
					Done <= 0;
					DINout <= 0;
					RYout <= 0;
					RYin <= 0;
					RXout <= 0;
					RXin <= 0;
					Ain <= 0;
					Gin <= 0;
					Gout <= 0;
					AddSub <= 0;
				end
			endcase
		T4:
			case (I)
				add:
				begin
					Done <= 1;
					Gout <= 1;
					RXin <= 1;
				end
				sub:
				begin
					Done <= 1;
					RXin <= 1;
					Gout <= 1;				
				end
				default:
				begin
					IRin <= 0;
					Done <= 0;
					DINout <= 0;
					RYout <= 0;
					RYin <= 0;
					RXout <= 0;
					RXin <= 0;
					Ain <= 0;
					Gin <= 0;
					Gout <= 0;
					AddSub <= 0;
				end
			endcase
		endcase
	end
	

	always @(posedge Clock, negedge Resetn) begin
		if (!Resetn) begin


		end
		else Tstep_Q <= Tstep_D;
		
	end
	

	

	wire [8:0] R0, R1, R2, R3, R4, R5, R6, R7;
	

	regn reg_0(BusWires, Rin[0], Clock, R0);

	regn reg_1(BusWires, Rin[1], Clock, R1);				
	
	regn reg_2(BusWires, Rin[2], Clock, R2);
				
	regn reg_3(BusWires, Rin[3], Clock, R3);
	
	regn reg_4(BusWires, Rin[4], Clock, R4);
	
	regn reg_5(BusWires, Rin[5], Clock, R5);
	
	regn reg_6(BusWires, Rin[6], Clock, R6);
	
	counter reg_pc(Clock, Resetn, PCincr, Rin[7], R7);
	

	regn reg_a(BusWires, Ain, Clock, AoutWires);
	


	regn reg_g(GinWires, Gin, Clock, GoutWires);
	

	regn reg_ir(DIN, IRin, Clock, IRoutWires);
	
	addsub Addsub(AddSub, AoutWires, BusWires, GinWires);
	

	always @ (RXout, RYout, Gout, DINout, regX, regY)
	begin


			if(DINout && !(RXout || RYout || Gout)) begin
				busDriver = 10'b0000000001;
			end
			else if(RXout && !(DINout || RYout || Gout)) begin
				busDriver = {regX, 1'b0, 1'b0};
			end
			else if(RYout && !(RXout || DINout || Gout)) begin
				busDriver = {regY, 1'b0, 1'b0};
			end
			else if(Gout && !(RXout || RYout || DINout)) begin
				busDriver = 10'b0000000010;
			end
			else begin
				$display("Ambiguous bus driver!! Setting to DINout\n");
				busDriver = 10'b0000000001;
			end
			
	end
	
	always @ (RXin, RYin, regX, regY)
	begin
		Rin = 8'b00000000;
		if(RXin) begin
			Rin = Rin | regX;
		end
		
		if(RYin) begin
			Rin = Rin | regY;
		end
	end
	

	always @ (busDriver, R0, R1, R2, R3, R4, R5, R6, R7, GoutWires, DIN) begin
		case(busDriver)
			reg0: BusWires <= R0;
			reg1: BusWires <= R1;
			reg2: BusWires <= R2;
			reg3: BusWires <= R3;
			reg4: BusWires <= R4;
			reg5: BusWires <= R5;
			reg6: BusWires <= R6;
			reg7: BusWires <= R7;
			gout: BusWires <= GoutWires;
			dinout: BusWires <= DIN;
			default:
			begin
				$display("Undefined bus driver!! Defaulting to DIN!!\n");
				BusWires <= DIN;
			end
		endcase
	end
	

	
	
endmodule