data/full_repos/permissive/110151336/lab_05/src/02_adder_synchronized/common/register.v
data/verilator_xmls/722f6514-58ad-4d2a-be65-3494bbea2949.xml
module register
# (
    parameter WIDTH = 8
)
(
    input                      clock,
    input                      reset,
    input                      load,
    input 	   [ WIDTH - 1:0 ] data_in,
    output reg [ WIDTH - 1:0 ] data_out
);

	always @ ( posedge clock, negedge reset )
		if ( ~reset )
            data_out <= { WIDTH { 1'b0 } };
        else if ( load )
            data_out <= data_in;
endmodule
module register
# (
    parameter WIDTH = 8
)
(
    input                      clock,
    input                      reset,
    input                      load,
    input 	   [ WIDTH - 1:0 ] data_in,
    output reg [ WIDTH - 1:0 ] data_out
);


	always @ ( posedge clock, negedge reset )
		if ( ~reset )
            data_out <= { WIDTH { 1'b0 } };
        else if ( load )
            data_out <= data_in;
endmodule