data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v
 line:18: before: "("
1: b'%Error: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:11: Unsupported: Verilog 1995 gate primitive: tranif1\ntranif1 #(dly1, dly2)   buf1(o[1], i, en);\n                        ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:12: Unsupported: Verilog 1995 gate primitive: tranif1\ntranif1 #(dly2, dly1)   buf2(o[2], i, en);\n                        ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:13: Unsupported: Verilog 1995 gate primitive: tranif1\ntranif1 #(dly1, dly3)   buf3(o[3], i, en);\n                        ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:14: Unsupported: Verilog 1995 gate primitive: tranif1\ntranif1 #(dly3, dly1)   buf4(o[4], i, en);\n                        ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:15: Unsupported: Verilog 1995 gate primitive: tranif1\ntranif1 #(dly2, dly3+1) buf5(o[5], i, en);\n                        ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:16: Unsupported: Verilog 1995 gate primitive: tranif1\ntranif1 #(4,    2)      buf6(o[6], i, en);\n                        ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:30: Unsupported or unknown PLI call: $monitor\n  #1 $monitor($time,,en,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);\n     ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:30: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  #1 $monitor($time,,en,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1 $monitor($time,,en,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #0      if (!check(1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx, 1\'bx)) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'b1, 1\'bx, 1\'b1, 1\'bx, 1\'bx, 1\'bx)) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'b1, 1\'bx, 1\'b1, 1\'bx, 1\'bx, 1\'bx)) failed = 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'bx, 1\'b1, 1\'bx)) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'bx, 1\'b1, 1\'bx)) failed = 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'bx)) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'bx)) failed = 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #0      if (!check(1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1, 1\'b1)) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'b1, 1\'bz, 1\'b1, 1\'bz, 1\'b1, 1\'b1)) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'b1, 1\'bz, 1\'b1, 1\'bz, 1\'b1, 1\'b1)) failed = 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'bz, 1\'bz, 1\'b1, 1\'bz, 1\'b1, 1\'bz)) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'bz, 1\'bz, 1\'b1, 1\'bz, 1\'b1, 1\'bz)) failed = 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'b1, 1\'bz)) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'b1, 1\'bz)) failed = 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz)) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #1;  #0 if (!check(1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz, 1\'bz)) failed = 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rise_fall_delay3.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 8 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

localparam [7:0] dly1 = 1;
wire       [7:0] dly2 = 2;
reg        [7:0] dly3 = 3;

reg        en;
wire       i = 1;
wire [6:1] o;

tranif1 #(dly1, dly2)   buf1(o[1], i, en);
tranif1 #(dly2, dly1)   buf2(o[2], i, en);
tranif1 #(dly1, dly3)   buf3(o[3], i, en);
tranif1 #(dly3, dly1)   buf4(o[4], i, en);
tranif1 #(dly2, dly3+1) buf5(o[5], i, en);
tranif1 #(4,    2)      buf6(o[6], i, en);

function check(input o1, input o2, input o3, input o4, input o5, input o6);

begin
  check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3)
       && (o[4] == o4) && (o[5] == o5) && (o[6] == o6);
end

endfunction

reg failed = 0;

initial begin
  #1 $monitor($time,,en,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);

  en = 1'b1;
  #0      if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
  #1;  #0 if (!check(1'b1, 1'bx, 1'b1, 1'bx, 1'bx, 1'bx)) failed = 1;
  #1;  #0 if (!check(1'b1, 1'b1, 1'b1, 1'bx, 1'b1, 1'bx)) failed = 1;
  #1;  #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1;
  #1;  #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;

  en = 1'b0;
  #0      if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
  #1;  #0 if (!check(1'b1, 1'bz, 1'b1, 1'bz, 1'b1, 1'b1)) failed = 1;
  #1;  #0 if (!check(1'bz, 1'bz, 1'b1, 1'bz, 1'b1, 1'bz)) failed = 1;
  #1;  #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'b1, 1'bz)) failed = 1;
  #1;  #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1;

  #1;
  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module test();


localparam [7:0] dly1 = 1;
wire       [7:0] dly2 = 2;
reg        [7:0] dly3 = 3;

reg        en;
wire       i = 1;
wire [6:1] o;

tranif1 #(dly1, dly2)   buf1(o[1], i, en);
tranif1 #(dly2, dly1)   buf2(o[2], i, en);
tranif1 #(dly1, dly3)   buf3(o[3], i, en);
tranif1 #(dly3, dly1)   buf4(o[4], i, en);
tranif1 #(dly2, dly3+1) buf5(o[5], i, en);
tranif1 #(4,    2)      buf6(o[6], i, en);

function check(input o1, input o2, input o3, input o4, input o5, input o6);

begin
  check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3)
       && (o[4] == o4) && (o[5] == o5) && (o[6] == o6);
end

endfunction

reg failed = 0;

initial begin
  #1 $monitor($time,,en,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);

  en = 1'b1;
  #0      if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
  #1;  #0 if (!check(1'b1, 1'bx, 1'b1, 1'bx, 1'bx, 1'bx)) failed = 1;
  #1;  #0 if (!check(1'b1, 1'b1, 1'b1, 1'bx, 1'b1, 1'bx)) failed = 1;
  #1;  #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1;
  #1;  #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;

  en = 1'b0;
  #0      if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
  #1;  #0 if (!check(1'b1, 1'bz, 1'b1, 1'bz, 1'b1, 1'b1)) failed = 1;
  #1;  #0 if (!check(1'bz, 1'bz, 1'b1, 1'bz, 1'b1, 1'bz)) failed = 1;
  #1;  #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'b1, 1'bz)) failed = 1;
  #1;  #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1;

  #1;
  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule