data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v
1: b'%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:1: Cannot find include file: src/main/Define/op_def.v\n`include "src/main/Define/op_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115074071/src/main/Controller,data/full_repos/permissive/115074071/src/main/Define/op_def.v\n             data/full_repos/permissive/115074071/src/main/Controller,data/full_repos/permissive/115074071/src/main/Define/op_def.v.v\n             data/full_repos/permissive/115074071/src/main/Controller,data/full_repos/permissive/115074071/src/main/Define/op_def.v.sv\n             src/main/Define/op_def.v\n             src/main/Define/op_def.v.v\n             src/main/Define/op_def.v.sv\n             obj_dir/src/main/Define/op_def.v\n             obj_dir/src/main/Define/op_def.v.v\n             obj_dir/src/main/Define/op_def.v.sv\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:16: Define or directive not defined: \'`OP_LBU\'\n            `OP_LBU, `OP_LHU:\n            ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:16: syntax error, unexpected \',\', expecting endcase\n            `OP_LBU, `OP_LHU:\n                   ^\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:16: Define or directive not defined: \'`OP_LHU\'\n            `OP_LBU, `OP_LHU:\n                     ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:23: Define or directive not defined: \'`OP_LB\'\n            `OP_LB, `OP_LBU, `OP_SB:\n            ^~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:23: Define or directive not defined: \'`OP_LBU\'\n            `OP_LB, `OP_LBU, `OP_SB:\n                    ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:23: Define or directive not defined: \'`OP_SB\'\n            `OP_LB, `OP_LBU, `OP_SB:\n                             ^~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:36: Define or directive not defined: \'`OP_LH\'\n            `OP_LH, `OP_LHU, `OP_SH:\n            ^~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:36: Define or directive not defined: \'`OP_LHU\'\n            `OP_LH, `OP_LHU, `OP_SH:\n                    ^~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:36: Define or directive not defined: \'`OP_SH\'\n            `OP_LH, `OP_LHU, `OP_SH:\n                             ^~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:45: Define or directive not defined: \'`OP_LW\'\n            `OP_LW, `OP_SW:\n            ^~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Controller/BECtrl.v:45: Define or directive not defined: \'`OP_SW\'\n            `OP_LW, `OP_SW:\n                    ^~~~~~\n%Error: Cannot continue\n'
module BECtrl(
    input   [5:0]       OP,
    input   [31:0]      addr,

    output  reg[3:0]    BE,
    output  reg[11:0]   fakeAddr,
    output  reg         MemReadSigned
);
    always@(*) begin
        fakeAddr = addr[11:0];


        case(OP)
            `OP_LBU, `OP_LHU:
                MemReadSigned   =   0;
            default:
                MemReadSigned   =   1;
        endcase

        case(OP)
            `OP_LB, `OP_LBU, `OP_SB:
                case(addr[1:0])
                    2'b00:
                        BE = 4'b0001;
                    2'b01:
                        BE = 4'b0010;
                    2'b10:
                        BE = 4'b0100;
                    2'b11:
                        BE = 4'b1000;
                    default:
                        BE = 4'b0001;
                endcase
            `OP_LH, `OP_LHU, `OP_SH:
                case(addr[1:0])
                    2'b00:
                        BE = 4'b0011;
                    2'b10:
                        BE = 4'b1100;
                    default:
                        BE = 4'b0011;
                endcase
            `OP_LW, `OP_SW:
                BE = 4'b1111;
            default:
                BE = 4'b1111;
        endcase
    end



endmodule
module BECtrl(
    input   [5:0]       OP,
    input   [31:0]      addr,

    output  reg[3:0]    BE,
    output  reg[11:0]   fakeAddr,
    output  reg         MemReadSigned
);

    always@(*) begin
        fakeAddr = addr[11:0];


        case(OP)
            `OP_LBU, `OP_LHU:
                MemReadSigned   =   0;
            default:
                MemReadSigned   =   1;
        endcase

        case(OP)
            `OP_LB, `OP_LBU, `OP_SB:
                case(addr[1:0])
                    2'b00:
                        BE = 4'b0001;
                    2'b01:
                        BE = 4'b0010;
                    2'b10:
                        BE = 4'b0100;
                    2'b11:
                        BE = 4'b1000;
                    default:
                        BE = 4'b0001;
                endcase
            `OP_LH, `OP_LHU, `OP_SH:
                case(addr[1:0])
                    2'b00:
                        BE = 4'b0011;
                    2'b10:
                        BE = 4'b1100;
                    default:
                        BE = 4'b0011;
                endcase
            `OP_LW, `OP_SW:
                BE = 4'b1111;
            default:
                BE = 4'b1111;
        endcase
    end



endmodule