data/full_repos/permissive/106330868/verilog/controller/controller_tb.v
 line:68: before: "$"
1: b'%Error: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:52: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("controller.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:53: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #300000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/controller_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = !clk;\n        ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CONTROLLER_TB;
    reg clk, rst_an; 
    
    reg [5:0] data_in;
    reg data_stb, serve_next;
    reg period_done;
    wire clear_states;
    
    wire ldq;
    wire [9:0] coeff;
    wire coeff_load;
    wire [7:0]  period;
    wire [15:0] amp;
    wire [7:0]  dur;

    CONTROLLER u_controller (
        .clk        (clk),
        .rst_an     (rst_an),
        .ldq        (ldq),
        .data_in    (data_in),
        .data_stb   (data_stb),
        .period_out (period),
        .amp_out    (amp),
        .coeff_out  (coeff),
        .coeff_stb  (coeff_load),
        .clear_states (clear_states),
        .period_done_in (period_done)
    );

    initial
    begin
        $dumpfile ("controller.vcd");
        $dumpvars;
        clk = 0;
        rst_an = 0;
        data_in = 6;
        data_stb = 0;
        period_done = 0;
        #5
        rst_an = 1;
        #5

        data_stb = 1;
        #10
        data_stb = 0;
        serve_next = 1;
        #300000
        $finish;
    end

    always @(posedge clk)
    begin   
        ;
    end

    always
        #5 clk = !clk;

endmodule
module CONTROLLER_TB;

    reg clk, rst_an; 
    
    reg [5:0] data_in;
    reg data_stb, serve_next;
    reg period_done;
    wire clear_states;
    
    wire ldq;
    wire [9:0] coeff;
    wire coeff_load;
    wire [7:0]  period;
    wire [15:0] amp;
    wire [7:0]  dur;

    CONTROLLER u_controller (
        .clk        (clk),
        .rst_an     (rst_an),
        .ldq        (ldq),
        .data_in    (data_in),
        .data_stb   (data_stb),
        .period_out (period),
        .amp_out    (amp),
        .coeff_out  (coeff),
        .coeff_stb  (coeff_load),
        .clear_states (clear_states),
        .period_done_in (period_done)
    );

    initial
    begin
        $dumpfile ("controller.vcd");
        $dumpvars;
        clk = 0;
        rst_an = 0;
        data_in = 6;
        data_stb = 0;
        period_done = 0;
        #5
        rst_an = 1;
        #5

        data_stb = 1;
        #10
        data_stb = 0;
        serve_next = 1;
        #300000
        $finish;
    end

    always @(posedge clk)
    begin   
        ;
    end

    always
        #5 clk = !clk;

endmodule