data/full_repos/permissive/109846502/Numerator.v
1: b'%Error: data/full_repos/permissive/109846502/Numerator.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/Numerator.v:59: Define or directive not defined: \'`KEY_0\'\n else if(enabled == 1\'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))\n                                   ^~~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:59: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n else if(enabled == 1\'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))\n                                          ^~\n%Error: data/full_repos/permissive/109846502/Numerator.v:59: Define or directive not defined: \'`KEY_9\'\n else if(enabled == 1\'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))\n                                                    ^~~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:59: Define or directive not defined: \'`SL_A\'\n else if(enabled == 1\'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))\n                                                                       ^~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:59: Define or directive not defined: \'`SL_B\'\n else if(enabled == 1\'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))\n                                                                                        ^~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:62: Define or directive not defined: \'`SL_A\'\n   2\'d0: if(ST_L == `SL_A) A1 <= key[3:0]; else B1 <= key[3:0];\n                    ^~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:63: Define or directive not defined: \'`SL_A\'\n   2\'d1: if(ST_L == `SL_A) A2 <= key[3:0]; else B2 <= key[3:0];\n                    ^~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:64: Define or directive not defined: \'`SL_A\'\n   2\'d2: if(ST_L == `SL_A) A3 <= key[3:0]; else B3 <= key[3:0];\n                    ^~~~~\n%Error: data/full_repos/permissive/109846502/Numerator.v:65: Define or directive not defined: \'`SL_A\'\n   2\'d3: if(ST_L == `SL_A) A4 <= key[3:0]; else B4 <= key[3:0];\n                    ^~~~~\n%Error: Cannot continue\n'
module Numerator(
		input [1:0] index,
		input enabled,
		input [4:0] key,
		input [2:0] ST_L,
		input clk,
		input rst,
		output reg [3:0] A1,A2,A3,A4,B1,B2,B3,B4
		
		,
		input set,
		input [15:0] setVal 
    );
	 
always @(posedge clk, posedge rst)
begin
	if(rst)
	begin
		A1 <= 4'd0;
		A2 <= 4'd0;
		A3 <= 4'd0;
		A4 <= 4'd0;
		B1 <= 4'd0;
		B2 <= 4'd0;
		B3 <= 4'd0;
		B4 <= 4'd0;
	end
	else if(set) begin
		A1 <= setVal[3:0];
		A2 <= setVal[7:4];
		A3 <= setVal[11:8];
		A4 <= setVal[15:12];
		B1 <= 4'd0;
		B2 <= 4'd0;
		B3 <= 4'd0;
		B4 <= 4'd0;
	end
	else if(enabled == 1'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))
	begin
		case(index)
			2'd0: if(ST_L == `SL_A) A1 <= key[3:0]; else B1 <= key[3:0];
			2'd1: if(ST_L == `SL_A) A2 <= key[3:0]; else B2 <= key[3:0];
			2'd2: if(ST_L == `SL_A) A3 <= key[3:0]; else B3 <= key[3:0];
			2'd3: if(ST_L == `SL_A) A4 <= key[3:0]; else B4 <= key[3:0];
		endcase	
	end	
end
	 



endmodule
module Numerator(
		input [1:0] index,
		input enabled,
		input [4:0] key,
		input [2:0] ST_L,
		input clk,
		input rst,
		output reg [3:0] A1,A2,A3,A4,B1,B2,B3,B4
		
		,
		input set,
		input [15:0] setVal 
    );

	 
always @(posedge clk, posedge rst)
begin
	if(rst)
	begin
		A1 <= 4'd0;
		A2 <= 4'd0;
		A3 <= 4'd0;
		A4 <= 4'd0;
		B1 <= 4'd0;
		B2 <= 4'd0;
		B3 <= 4'd0;
		B4 <= 4'd0;
	end
	else if(set) begin
		A1 <= setVal[3:0];
		A2 <= setVal[7:4];
		A3 <= setVal[11:8];
		A4 <= setVal[15:12];
		B1 <= 4'd0;
		B2 <= 4'd0;
		B3 <= 4'd0;
		B4 <= 4'd0;
	end
	else if(enabled == 1'b1 && key >= `KEY_0 && key <= `KEY_9 && (ST_L == `SL_A || ST_L == `SL_B))
	begin
		case(index)
			2'd0: if(ST_L == `SL_A) A1 <= key[3:0]; else B1 <= key[3:0];
			2'd1: if(ST_L == `SL_A) A2 <= key[3:0]; else B2 <= key[3:0];
			2'd2: if(ST_L == `SL_A) A3 <= key[3:0]; else B3 <= key[3:0];
			2'd3: if(ST_L == `SL_A) A4 <= key[3:0]; else B4 <= key[3:0];
		endcase	
	end	
end
	 



endmodule