data/full_repos/permissive/150642927/VerilogSrc/Sources/multiply_and_add.v
data/verilator_xmls/1775098e-9af1-458b-a25f-5cd36945ffd2.xml
module multiply_and_add #(
    parameter DATA_WIDTH = 8,
    parameter RESULT_WIDTH = 16
    ) (
    input wire signed [RESULT_WIDTH-1:0] add_value,
    input wire signed [DATA_WIDTH-1:0] input_value,
    input wire signed [7:0] weight_value,
    output wire signed [RESULT_WIDTH-1:0] output_value
    );
    
assign output_value = add_value + input_value * weight_value;

endmodule
module multiply_and_add #(
    parameter DATA_WIDTH = 8,
    parameter RESULT_WIDTH = 16
    ) (
    input wire signed [RESULT_WIDTH-1:0] add_value,
    input wire signed [DATA_WIDTH-1:0] input_value,
    input wire signed [7:0] weight_value,
    output wire signed [RESULT_WIDTH-1:0] output_value
    );

    
assign output_value = add_value + input_value * weight_value;

endmodule