data/full_repos/permissive/197356760/CachCoherency/cache_l2.v
None: at end of input
1: b'%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:9: Cannot find include file: parameter.v\n`include "parameter.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197356760/CachCoherency,data/full_repos/permissive/197356760/parameter.v\n             data/full_repos/permissive/197356760/CachCoherency,data/full_repos/permissive/197356760/parameter.v.v\n             data/full_repos/permissive/197356760/CachCoherency,data/full_repos/permissive/197356760/parameter.v.sv\n             parameter.v\n             parameter.v.v\n             parameter.v.sv\n             obj_dir/parameter.v\n             obj_dir/parameter.v.v\n             obj_dir/parameter.v.sv\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:12: Define or directive not defined: \'`address_rang\'\n input  wire[`address_rang-1:0] address; \n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:13: Define or directive not defined: \'`data_siz\'\n input  wire[`data_siz-1:0] data_in;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:16: Define or directive not defined: \'`sel_siz\'\n                                                                        : ... Suggested alternative: \'`elsif\'\n input  wire[`sel_siz-1:0] ctrl_l1_id ;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:17: Define or directive not defined: \'`address_rang\'\n output reg[`address_rang-1:0] address_out; \n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:18: Define or directive not defined: \'`data_siz\'\n output reg[`data_siz-1:0] data_out;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:22: Define or directive not defined: \'`data_siz\'\n reg[`data_siz-1:0] cache2 [`cach_size-1:0];\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:22: Define or directive not defined: \'`cach_size\'\n reg[`data_siz-1:0] cache2 [`cach_size-1:0];\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:31: Define or directive not defined: \'`cach_size\'\n  for (k = 0; k < `cach_size ; k = k + 1)\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:31: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  for (k = 0; k < `cach_size ; k = k + 1)\n                             ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:31: syntax error, unexpected \')\', expecting \';\'\n  for (k = 0; k < `cach_size ; k = k + 1)\n                                        ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:47: syntax error, unexpected \'=\', expecting IDENTIFIER\n     ns = write_s;\n        ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:49: syntax error, unexpected \'=\', expecting IDENTIFIER\n     ns = read_s;\n        ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:51: syntax error, unexpected \'=\', expecting IDENTIFIER\n     ps= init_s;\n       ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:55: syntax error, unexpected \'[\', expecting IDENTIFIER\n     cache2[address][`data_siz-2:0] = data_in[`data_siz-2:0];  \n           ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:55: Define or directive not defined: \'`data_siz\'\n     cache2[address][`data_siz-2:0] = data_in[`data_siz-2:0];  \n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:55: Define or directive not defined: \'`data_siz\'\n     cache2[address][`data_siz-2:0] = data_in[`data_siz-2:0];  \n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:56: Define or directive not defined: \'`data_siz\'\n     cache2[address][`data_siz-1] = 1;  \n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:62: syntax error, unexpected \'=\', expecting IDENTIFIER\n     address_out = address;\n                 ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:63: Define or directive not defined: \'`data_siz\'\n     data_out = cache2[address][`data_siz-1:0];\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:65: syntax error, unexpected \'=\', expecting IDENTIFIER\n      w_select_0= 1;\n                ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:67: syntax error, unexpected \'=\', expecting IDENTIFIER\n      w_select_1= 1;\n                ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:69: syntax error, unexpected \'=\', expecting IDENTIFIER\n      w_select_2= 1;\n                ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:71: syntax error, unexpected \'=\', expecting IDENTIFIER\n      w_select_3= 1;\n                ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/cache_l2.v:75: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    ns = init_s;\n                       ^\n%Error: Cannot continue\n'
module cache_l2(data_out, data_in, address, address_out, write, read, ctrl_l1_id, w_select_0, w_select_1, w_select_2, w_select_3, clk, rst);
`include "parameter.v"

	
	input  wire[`address_rang-1:0] address; 
	input  wire[`data_siz-1:0] data_in;
	input  clk,rst ;
	input  wire read,write ;
	input  wire[`sel_siz-1:0] ctrl_l1_id ;
	output reg[`address_rang-1:0] address_out; 
	output reg[`data_siz-1:0] data_out;
	output reg  w_select_0,w_select_1,w_select_2,w_select_3 ;

	integer i=0,k=0;
	reg[`data_siz-1:0] cache2 [`cach_size-1:0];

	
	
	reg [1:0] ps,ns;
	parameter init_s=0,write_s=1, read_s=2 ;
	
	
	initial begin
		for (k = 0; k < `cach_size ; k = k + 1)
			begin
				cache2[k] = k ;
		end
	end	
	
	
	always @ (ps,write,read,address,data_in,ctrl_l1_id)
	 begin
		  w_select_0= 0;
		  w_select_1= 0;
		  w_select_2= 0;
		  w_select_3= 0;
          case (ps)
               init_s:begin
				if (write)
					ns = write_s;
				else if (read)
					ns = read_s;
				else
					ps= init_s;
				
				end
               write_s:begin
					cache2[address][`data_siz-2:0] = data_in[`data_siz-2:0];
					cache2[address][`data_siz-1] = 1;

					ns =init_s;
				end
				
               read_s:begin
					address_out = address;
					data_out = cache2[address][`data_siz-1:0];
					if (ctrl_l1_id == 2'b00)
						w_select_0= 1;
					else if (ctrl_l1_id == 2'b01)	 
						w_select_1= 1;
					else if (ctrl_l1_id == 2'b10)	 
						w_select_2= 1;
					else if (ctrl_l1_id == 2'b11)	 
						w_select_3= 1;
					ns =init_s;
				end	
               default:
                    ns = init_s;
          endcase
     end


	always @ (posedge clk or posedge rst) begin
		if (rst == 1)
			ns=init_s;
		else
			ps=ns;
	end
endmodule
module cache_l2(data_out, data_in, address, address_out, write, read, ctrl_l1_id, w_select_0, w_select_1, w_select_2, w_select_3, clk, rst);

`include "parameter.v"

	
	input  wire[`address_rang-1:0] address; 
	input  wire[`data_siz-1:0] data_in;
	input  clk,rst ;
	input  wire read,write ;
	input  wire[`sel_siz-1:0] ctrl_l1_id ;
	output reg[`address_rang-1:0] address_out; 
	output reg[`data_siz-1:0] data_out;
	output reg  w_select_0,w_select_1,w_select_2,w_select_3 ;

	integer i=0,k=0;
	reg[`data_siz-1:0] cache2 [`cach_size-1:0];

	
	
	reg [1:0] ps,ns;
	parameter init_s=0,write_s=1, read_s=2 ;
	
	
	initial begin
		for (k = 0; k < `cach_size ; k = k + 1)
			begin
				cache2[k] = k ;
		end
	end	
	
	
	always @ (ps,write,read,address,data_in,ctrl_l1_id)
	 begin
		  w_select_0= 0;
		  w_select_1= 0;
		  w_select_2= 0;
		  w_select_3= 0;
          case (ps)
               init_s:begin
				if (write)
					ns = write_s;
				else if (read)
					ns = read_s;
				else
					ps= init_s;
				
				end
               write_s:begin
					cache2[address][`data_siz-2:0] = data_in[`data_siz-2:0];
					cache2[address][`data_siz-1] = 1;

					ns =init_s;
				end
				
               read_s:begin
					address_out = address;
					data_out = cache2[address][`data_siz-1:0];
					if (ctrl_l1_id == 2'b00)
						w_select_0= 1;
					else if (ctrl_l1_id == 2'b01)	 
						w_select_1= 1;
					else if (ctrl_l1_id == 2'b10)	 
						w_select_2= 1;
					else if (ctrl_l1_id == 2'b11)	 
						w_select_3= 1;
					ns =init_s;
				end	
               default:
                    ns = init_s;
          endcase
     end


	always @ (posedge clk or posedge rst) begin
		if (rst == 1)
			ns=init_s;
		else
			ps=ns;
	end
endmodule