data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v
 line:122: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:37: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("instruction_cache.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:38: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars;\n   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n   #5\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n   #2\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n   #20\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n   #2\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #20\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #2\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n   #20\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #2\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #2\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #2\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n   #20\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #2\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #2\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172705897/simulation/instruction_cache_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #40\n  ^\n%Error: Exiting due to 2 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module instruction_cache_tb();
	reg clk = 0;
	reg[31:0] addr;
	wire[31:0] out;
	wire clk_stall;


	wire[8:0] block_addr;
	wire[255:0] new_line_read;
	wire readmem;

	instruction_cache instr_cache_inst(
		.clk(clk),
		.addr(addr),
		.out(out),
		.clk_stall(clk_stall),
		.mem_block_addr(block_addr),
		.new_line(new_line_read),
		.readmem(readmem)
	);

	main_memory main_mem(
		.clk(clk),
		.block_addr(block_addr),
		.readmem(readmem),
		.writemem(1'b0),
		.data_write(256'b0),
		.data_read(new_line_read)
	);



	always
	 #1 clk = ~clk;

	initial begin
		$dumpfile ("instruction_cache.vcd");
	 	$dumpvars;

	 	#5


	 	addr = 32'b0;

	 	#2


	 	addr = 32'b1;

	 	#20


	 	addr = 32'b10;

	 	#2


	 	addr = 32'b11;

	 	#20


	 	addr = 32'b100;

		#2


	 	addr = 32'b101;

	 	#20


	 	addr = 32'b110;

		#2


	 	addr = 32'b111;

		#20


	 	addr = 32'b1000;

		#2


	 	addr = 32'b1001;

		#20


	 	addr = 32'b1010;

		#2


	 	addr = 32'b1011;

	 	#20


	 	addr = 32'b1100;

		#2


	 	addr = 32'b1101;

		#20


	 	addr = 32'b1110;

		#2


	 	addr = 32'b1111;

		#40

	 	$finish;
	end

endmodule
module instruction_cache_tb();

	reg clk = 0;
	reg[31:0] addr;
	wire[31:0] out;
	wire clk_stall;


	wire[8:0] block_addr;
	wire[255:0] new_line_read;
	wire readmem;

	instruction_cache instr_cache_inst(
		.clk(clk),
		.addr(addr),
		.out(out),
		.clk_stall(clk_stall),
		.mem_block_addr(block_addr),
		.new_line(new_line_read),
		.readmem(readmem)
	);

	main_memory main_mem(
		.clk(clk),
		.block_addr(block_addr),
		.readmem(readmem),
		.writemem(1'b0),
		.data_write(256'b0),
		.data_read(new_line_read)
	);



	always
	 #1 clk = ~clk;

	initial begin
		$dumpfile ("instruction_cache.vcd");
	 	$dumpvars;

	 	#5


	 	addr = 32'b0;

	 	#2


	 	addr = 32'b1;

	 	#20


	 	addr = 32'b10;

	 	#2


	 	addr = 32'b11;

	 	#20


	 	addr = 32'b100;

		#2


	 	addr = 32'b101;

	 	#20


	 	addr = 32'b110;

		#2


	 	addr = 32'b111;

		#20


	 	addr = 32'b1000;

		#2


	 	addr = 32'b1001;

		#20


	 	addr = 32'b1010;

		#2


	 	addr = 32'b1011;

	 	#20


	 	addr = 32'b1100;

		#2


	 	addr = 32'b1101;

		#20


	 	addr = 32'b1110;

		#2


	 	addr = 32'b1111;

		#40

	 	$finish;
	end

endmodule