data/full_repos/permissive/156407853/Files/Verilog/switch/spio_switch.v
data/verilator_xmls/604b8194-3bf6-4f29-8392-354d8cea36fb.xml
module spio_switch#(
                     parameter PKT_BITS = 72

                   , parameter NUM_PORTS = 2
                   )
                   ( input wire CLK_IN
                   , input wire RESET_IN


                   ,   input  wire [PKT_BITS-1:0]  IN_DATA_IN
                   ,   input  wire                 IN_VLD_IN
                   ,   output wire                 IN_RDY_OUT




                   ,   input  wire [NUM_PORTS-1:0] IN_OUTPUT_SELECT_IN


                   , output reg  [(PKT_BITS*NUM_PORTS)-1:0] OUT_DATA_OUT
                   , output reg  [NUM_PORTS-1:0]            OUT_VLD_OUT
                   , input  wire [NUM_PORTS-1:0]            OUT_RDY_IN





                   ,   output wire [NUM_PORTS-1:0] BLOCKED_OUTPUTS_OUT





                   ,   output wire [NUM_PORTS-1:0] SELECTED_OUTPUTS_OUT




                   , input wire DROP_IN




                   ,   output reg [PKT_BITS-1:0] DROPPED_DATA_OUT





                   ,   output reg [NUM_PORTS-1:0] DROPPED_OUTPUTS_OUT


                   ,   output reg DROPPED_VLD_OUT
                   );

genvar i;








































localparam RUN    = 1'b0;
localparam PARKED = 1'b1;
reg inputstate_i;


reg [PKT_BITS-1:0]  parked_data_i;
reg [NUM_PORTS-1:0] parked_output_select_i;



wire [PKT_BITS-1:0]  data_i          = (inputstate_i == PARKED) ? parked_data_i          : IN_DATA_IN;
wire [NUM_PORTS-1:0] output_select_i = (inputstate_i == PARKED) ? parked_output_select_i : IN_OUTPUT_SELECT_IN;
wire                 vld_i           = (inputstate_i == PARKED) ? 1'b1                   : IN_VLD_IN;



wire [NUM_PORTS-1:0] wait_i = OUT_VLD_OUT & ~OUT_RDY_IN;


wire [NUM_PORTS-1:0] transfer_i = OUT_VLD_OUT & OUT_RDY_IN;



reg [NUM_PORTS-1:0] accepted_outputs_i;



wire sent_i = ( !(|( (wait_i & ~accepted_outputs_i)
                   & output_select_i))
              | DROP_IN)
            & vld_i;



wire park_i = IN_RDY_OUT && IN_VLD_IN && |(wait_i & output_select_i);


assign IN_RDY_OUT = inputstate_i == RUN;



wire [NUM_PORTS-1:0] send_now_i = {NUM_PORTS{vld_i}}
                                & ~accepted_outputs_i
                                & output_select_i
                                & ~wait_i
                                ;



assign BLOCKED_OUTPUTS_OUT = vld_i ? (output_select_i & wait_i & ~accepted_outputs_i)
                                   : {NUM_PORTS{1'b0}};


assign SELECTED_OUTPUTS_OUT = output_select_i;
















always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		inputstate_i <= RUN;
	else
		case (inputstate_i)
			RUN:    if (park_i) inputstate_i <= PARKED;
			PARKED: if (sent_i) inputstate_i <= RUN;
		endcase


always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			parked_data_i          <= {PKT_BITS{1'bX}};
			parked_output_select_i <= {NUM_PORTS{1'bX}};
		end
	else if (park_i)
		begin
			parked_data_i          <= IN_DATA_IN;
			parked_output_select_i <= IN_OUTPUT_SELECT_IN;
		end






always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		accepted_outputs_i <= {NUM_PORTS{1'b0}};
	else

		if (sent_i)
			accepted_outputs_i <= {NUM_PORTS{1'b0}};


		else if (vld_i)
			accepted_outputs_i <= accepted_outputs_i | ~wait_i;






generate for (i = 0; i < NUM_PORTS; i = i + 1)
	begin : output_registers
		
		always @ (posedge CLK_IN, posedge RESET_IN)
			if (RESET_IN)
				begin
					OUT_DATA_OUT[PKT_BITS*i+:PKT_BITS] <= {PKT_BITS{1'bX}};
					OUT_VLD_OUT[i] <= 1'b0;
				end
			else


				if (send_now_i[i])
					begin
						OUT_DATA_OUT[PKT_BITS*i+:PKT_BITS] <= data_i;
						OUT_VLD_OUT[i] <= 1'b1;
					end
				else if (transfer_i[i])
					begin
						OUT_DATA_OUT[PKT_BITS*i+:PKT_BITS] <= {PKT_BITS{1'bX}};
						OUT_VLD_OUT[i] <= 1'b0;
					end
	
	end
endgenerate






always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			DROPPED_DATA_OUT    <= {PKT_BITS{1'bX}};
			DROPPED_OUTPUTS_OUT <= {NUM_PORTS{1'bX}};
			DROPPED_VLD_OUT     <= 1'b0;
		end
	else
		if (DROP_IN || (output_select_i == {NUM_PORTS{1'b0}} && vld_i))
			begin
				DROPPED_DATA_OUT    <= data_i;
				DROPPED_OUTPUTS_OUT <= wait_i & ~accepted_outputs_i & output_select_i;
				DROPPED_VLD_OUT     <= 1'b1;
			end
		else
			begin
				DROPPED_DATA_OUT    <= {PKT_BITS{1'bX}};
				DROPPED_OUTPUTS_OUT <= {NUM_PORTS{1'bX}};
				DROPPED_VLD_OUT     <= 1'b0;
			end


endmodule
module spio_switch#(
                     parameter PKT_BITS = 72

                   , parameter NUM_PORTS = 2
                   )
                   ( input wire CLK_IN
                   , input wire RESET_IN


                   ,   input  wire [PKT_BITS-1:0]  IN_DATA_IN
                   ,   input  wire                 IN_VLD_IN
                   ,   output wire                 IN_RDY_OUT




                   ,   input  wire [NUM_PORTS-1:0] IN_OUTPUT_SELECT_IN


                   , output reg  [(PKT_BITS*NUM_PORTS)-1:0] OUT_DATA_OUT
                   , output reg  [NUM_PORTS-1:0]            OUT_VLD_OUT
                   , input  wire [NUM_PORTS-1:0]            OUT_RDY_IN





                   ,   output wire [NUM_PORTS-1:0] BLOCKED_OUTPUTS_OUT





                   ,   output wire [NUM_PORTS-1:0] SELECTED_OUTPUTS_OUT




                   , input wire DROP_IN




                   ,   output reg [PKT_BITS-1:0] DROPPED_DATA_OUT





                   ,   output reg [NUM_PORTS-1:0] DROPPED_OUTPUTS_OUT


                   ,   output reg DROPPED_VLD_OUT
                   );


genvar i;








































localparam RUN    = 1'b0;
localparam PARKED = 1'b1;
reg inputstate_i;


reg [PKT_BITS-1:0]  parked_data_i;
reg [NUM_PORTS-1:0] parked_output_select_i;



wire [PKT_BITS-1:0]  data_i          = (inputstate_i == PARKED) ? parked_data_i          : IN_DATA_IN;
wire [NUM_PORTS-1:0] output_select_i = (inputstate_i == PARKED) ? parked_output_select_i : IN_OUTPUT_SELECT_IN;
wire                 vld_i           = (inputstate_i == PARKED) ? 1'b1                   : IN_VLD_IN;



wire [NUM_PORTS-1:0] wait_i = OUT_VLD_OUT & ~OUT_RDY_IN;


wire [NUM_PORTS-1:0] transfer_i = OUT_VLD_OUT & OUT_RDY_IN;



reg [NUM_PORTS-1:0] accepted_outputs_i;



wire sent_i = ( !(|( (wait_i & ~accepted_outputs_i)
                   & output_select_i))
              | DROP_IN)
            & vld_i;



wire park_i = IN_RDY_OUT && IN_VLD_IN && |(wait_i & output_select_i);


assign IN_RDY_OUT = inputstate_i == RUN;



wire [NUM_PORTS-1:0] send_now_i = {NUM_PORTS{vld_i}}
                                & ~accepted_outputs_i
                                & output_select_i
                                & ~wait_i
                                ;



assign BLOCKED_OUTPUTS_OUT = vld_i ? (output_select_i & wait_i & ~accepted_outputs_i)
                                   : {NUM_PORTS{1'b0}};


assign SELECTED_OUTPUTS_OUT = output_select_i;
















always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		inputstate_i <= RUN;
	else
		case (inputstate_i)
			RUN:    if (park_i) inputstate_i <= PARKED;
			PARKED: if (sent_i) inputstate_i <= RUN;
		endcase


always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			parked_data_i          <= {PKT_BITS{1'bX}};
			parked_output_select_i <= {NUM_PORTS{1'bX}};
		end
	else if (park_i)
		begin
			parked_data_i          <= IN_DATA_IN;
			parked_output_select_i <= IN_OUTPUT_SELECT_IN;
		end






always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		accepted_outputs_i <= {NUM_PORTS{1'b0}};
	else

		if (sent_i)
			accepted_outputs_i <= {NUM_PORTS{1'b0}};


		else if (vld_i)
			accepted_outputs_i <= accepted_outputs_i | ~wait_i;






generate for (i = 0; i < NUM_PORTS; i = i + 1)
	begin : output_registers
		
		always @ (posedge CLK_IN, posedge RESET_IN)
			if (RESET_IN)
				begin
					OUT_DATA_OUT[PKT_BITS*i+:PKT_BITS] <= {PKT_BITS{1'bX}};
					OUT_VLD_OUT[i] <= 1'b0;
				end
			else


				if (send_now_i[i])
					begin
						OUT_DATA_OUT[PKT_BITS*i+:PKT_BITS] <= data_i;
						OUT_VLD_OUT[i] <= 1'b1;
					end
				else if (transfer_i[i])
					begin
						OUT_DATA_OUT[PKT_BITS*i+:PKT_BITS] <= {PKT_BITS{1'bX}};
						OUT_VLD_OUT[i] <= 1'b0;
					end
	
	end
endgenerate






always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			DROPPED_DATA_OUT    <= {PKT_BITS{1'bX}};
			DROPPED_OUTPUTS_OUT <= {NUM_PORTS{1'bX}};
			DROPPED_VLD_OUT     <= 1'b0;
		end
	else
		if (DROP_IN || (output_select_i == {NUM_PORTS{1'b0}} && vld_i))
			begin
				DROPPED_DATA_OUT    <= data_i;
				DROPPED_OUTPUTS_OUT <= wait_i & ~accepted_outputs_i & output_select_i;
				DROPPED_VLD_OUT     <= 1'b1;
			end
		else
			begin
				DROPPED_DATA_OUT    <= {PKT_BITS{1'bX}};
				DROPPED_OUTPUTS_OUT <= {NUM_PORTS{1'bX}};
				DROPPED_VLD_OUT     <= 1'b0;
			end


endmodule