data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v
None: at end of input
1: b'%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v:2: Cannot find include file: files.vh\n`include "files.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory,data/full_repos/permissive/180413071/files.vh\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory,data/full_repos/permissive/180413071/files.vh.v\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory,data/full_repos/permissive/180413071/files.vh.sv\n             files.vh\n             files.vh.v\n             files.vh.sv\n             obj_dir/files.vh\n             obj_dir/files.vh.v\n             obj_dir/files.vh.sv\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v:3: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v:6: Define or directive not defined: \'`RAM_FILE\'\nmodule data_memory #(parameter PATH=`RAM_FILE, parameter SIZE=1024)(\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v:6: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nmodule data_memory #(parameter PATH=`RAM_FILE, parameter SIZE=1024)(\n                                             ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v:6: syntax error, unexpected \')\', expecting \';\'\nmodule data_memory #(parameter PATH=`RAM_FILE, parameter SIZE=1024)(\n                                                                  ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v:12: Define or directive not defined: \'`WORD\'\n    input      [`WORD-1:0] address,\n                ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v:13: Define or directive not defined: \'`WORD\'\n    input      [`WORD-1:0] write_data,\n                ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v:14: Define or directive not defined: \'`WORD\'\n    output reg [`WORD-1:0] read_data\n                ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v:15: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v:17: Define or directive not defined: \'`WORD\'\n    reg [`WORD-1:0] data_mem [SIZE-1:0];\n         ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/data_memory.v:19: syntax error, unexpected initial\n    initial \n    ^~~~~~~\n%Error: Exiting due to 11 error(s)\n'
module data_memory #(parameter PATH=`RAM_FILE, parameter SIZE=1024)(
    input                  read_clk,
    input                  write_clk,
    input                  reset,
    input                  mem_read,
    input                  mem_write,
    input      [`WORD-1:0] address,
    input      [`WORD-1:0] write_data,
    output reg [`WORD-1:0] read_data
);

    reg [`WORD-1:0] data_mem [SIZE-1:0];
    
    initial 
        $readmemb(PATH, data_mem);
    
    always @(posedge read_clk, reset)
        if (!reset) 
            read_data <= (mem_read ? data_mem[address / 8] : 64'bZ);
        
    always @(posedge write_clk, reset)
        if (!reset && mem_write) 
            data_mem[address / 8] <= write_data;

endmodule
module data_memory #(parameter PATH=`RAM_FILE, parameter SIZE=1024)(
    input                  read_clk,
    input                  write_clk,
    input                  reset,
    input                  mem_read,
    input                  mem_write,
    input      [`WORD-1:0] address,
    input      [`WORD-1:0] write_data,
    output reg [`WORD-1:0] read_data
);


    reg [`WORD-1:0] data_mem [SIZE-1:0];
    
    initial 
        $readmemb(PATH, data_mem);
    
    always @(posedge read_clk, reset)
        if (!reset) 
            read_data <= (mem_read ? data_mem[address / 8] : 64'bZ);
        
    always @(posedge write_clk, reset)
        if (!reset && mem_write) 
            data_mem[address / 8] <= write_data;

endmodule