data/full_repos/permissive/20803096/rslatch.v
data/verilator_xmls/1f6f085b-2fe6-4c46-9a9a-78a560740b76.xml
module rslatch (r, s, c, q, nq);
	input r;
	input s;
	input c;
	output q;
	output nq;

	wire w1, w2;

	nand (w1, s, c);
	nand (w2, r, c);

	nand (nq, q, w2);
	nand (q, nq, w1);
endmodule
module rslatch (r, s, c, q, nq);

	input r;
	input s;
	input c;
	output q;
	output nq;

	wire w1, w2;

	nand (w1, s, c);
	nand (w2, r, c);

	nand (nq, q, w2);
	nand (q, nq, w1);
endmodule