data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/ice40.v
1: b"%Error: data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/ice40.v:29: Cannot find file containing module: 'pll_12_25'\npll_12_25 pll0(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/pll_12_25\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/pll_12_25.v\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/pll_12_25.sv\n             pll_12_25\n             pll_12_25.v\n             pll_12_25.sv\n             obj_dir/pll_12_25\n             obj_dir/pll_12_25.v\n             obj_dir/pll_12_25.sv\n%Error: data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/ice40.v:79: Cannot find file containing module: 'cpu16'\ncpu16 cpu(\n^~~~~\n%Error: data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/ice40.v:102: Cannot find file containing module: 'spi_debug_ifc'\nspi_debug_ifc sdi(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/ice40.v:165: Cannot find file containing module: 'vga40x30x2'\nvga40x30x2 vga(\n^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module sram(
	input clk,
	input [15:0]raddr,
	output [15:0]rdata,
	input re,
	input [15:0]waddr,
	input [15:0]wdata,
	input we
	);

`ifndef uselatticeprim
reg [15:0]mem[255:0];
reg [15:0]ra;
always @(posedge clk) begin
	if (we)
		mem[waddr[7:0]] <= wdata;
	if (re)
		ra <= raddr;
end
assign rdata = mem[ra[7:0]];
`else
SB_RAM256x16 sram_inst(
	.RDATA(rdata),
	.RADDR(raddr[7:0]),
	.RCLK(clk),
	.RCLKE(1'b1),
	.RE(re),
	.WADDR(waddr[7:0]),
	.WDATA(wdata),
	.WCLK(clk),
	.WCLKE(1'b1),
	.WE(we),
	.MASK()
	);
`endif

endmodule
module sram(
	input clk,
	input [15:0]raddr,
	output [15:0]rdata,
	input re,
	input [15:0]waddr,
	input [15:0]wdata,
	input we
	);


`ifndef uselatticeprim
reg [15:0]mem[255:0];
reg [15:0]ra;
always @(posedge clk) begin
	if (we)
		mem[waddr[7:0]] <= wdata;
	if (re)
		ra <= raddr;
end
assign rdata = mem[ra[7:0]];
`else
SB_RAM256x16 sram_inst(
	.RDATA(rdata),
	.RADDR(raddr[7:0]),
	.RCLK(clk),
	.RCLKE(1'b1),
	.RE(re),
	.WADDR(waddr[7:0]),
	.WDATA(wdata),
	.WCLK(clk),
	.WCLKE(1'b1),
	.WE(we),
	.MASK()
	);
`endif

endmodule