data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v:112: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v:114: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module or1200_spram_512x20(
`ifdef OR1200_BIST

	mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif

	clk, rst, ce, we, oe, addr, di, doq
);




parameter aw = 9;
parameter dw = 20;

`ifdef OR1200_BIST



input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif




input			clk;
input			rst;
input			ce;
input			we;
input			oe;
input 	[aw-1:0]	addr;
input	[dw-1:0]	di;
output	[dw-1:0]	doq;




`ifdef OR1200_XILINX_RAMB4
wire	[3:0]		unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire	[11:0]		unconnected;
`endif
`endif

`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif

`ifdef OR1200_ARTISAN_SSP






`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST

	.mbist_si_i(mbist_si_i),
	.mbist_so_o(mbist_so_o),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.CLK(clk),
	.CEN(~ce),
	.WEN(~we),
	.A(addr),
	.D(di),
	.OEN(~oe),
	.Q(doq)
);

`else

`ifdef OR1200_AVANT_ATP






avant_atp avant_atp(
	.web(~we),
	.reb(),
	.oeb(~oe),
	.rcsb(),
	.wcsb(),
	.ra(addr),
	.wa(addr),
	.di(di),
	.doq(doq)
);

`else

`ifdef OR1200_VIRAGE_SSP






virage_ssp virage_ssp(
	.clk(clk),
	.adr(addr),
	.d(di),
	.we(we),
	.oe(oe),
	.me(ce),
	.q(doq)
);

`else

`ifdef OR1200_VIRTUALSILICON_SSP






`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST

	.mbist_si_i(mbist_si_i),
	.mbist_so_o(mbist_so_o),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.CK(clk),
	.ADR(addr),
	.DI(di),
	.WEN(~we),
	.CEN(~ce),
	.OEN(~oe),
	.DOUT(doq)
);

`else

`ifdef OR1200_XILINX_RAMB4










RAMB4_S8 ramb4_s8_0(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[7:0]),
	.EN(ce),
	.WE(we),
	.DO(doq[7:0])
);




RAMB4_S8 ramb4_s8_1(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[15:8]),
	.EN(ce),
	.WE(we),
	.DO(doq[15:8])
);




RAMB4_S8 ramb4_s8_2(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI({4'b0000, di[19:16]}),
	.EN(ce),
	.WE(we),
	.DO({unconnected, doq[19:16]})
);

`else

`ifdef OR1200_XILINX_RAMB16









RAMB16_S36 ramb16_s36(
	.CLK(clk),
	.SSR(rst),
	.ADDR(addr),
	.DI({12'h000,di}),
	.DIP(4'h0),
	.EN(ce),
	.WE(we),
	.DO({unconnected,doq}),
	.DOP()
);

`else

`ifdef OR1200_ALTERA_LPM









wire    wr;

assign  wr = ce & we;

initial $display("Using Altera LPM.");

lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(doq)
);

defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";


`else








reg	[dw-1:0]	mem [(1<<aw)-1:0];
reg	[aw-1:0]	addr_reg;




assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};




always @(posedge clk or posedge rst)
	if (rst)
		addr_reg <= #1 {aw{1'b0}};
	else if (ce)
		addr_reg <= #1 addr;




always @(posedge clk)
	if (ce && we)
		mem[addr] <= #1 di;

`endif
`endif
`endif
`endif
`endif
`endif
`endif

endmodule
module or1200_spram_512x20(
`ifdef OR1200_BIST

	mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif

	clk, rst, ce, we, oe, addr, di, doq
);





parameter aw = 9;
parameter dw = 20;

`ifdef OR1200_BIST



input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif




input			clk;
input			rst;
input			ce;
input			we;
input			oe;
input 	[aw-1:0]	addr;
input	[dw-1:0]	di;
output	[dw-1:0]	doq;




`ifdef OR1200_XILINX_RAMB4
wire	[3:0]		unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire	[11:0]		unconnected;
`endif
`endif

`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif

`ifdef OR1200_ARTISAN_SSP






`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST

	.mbist_si_i(mbist_si_i),
	.mbist_so_o(mbist_so_o),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.CLK(clk),
	.CEN(~ce),
	.WEN(~we),
	.A(addr),
	.D(di),
	.OEN(~oe),
	.Q(doq)
);

`else

`ifdef OR1200_AVANT_ATP






avant_atp avant_atp(
	.web(~we),
	.reb(),
	.oeb(~oe),
	.rcsb(),
	.wcsb(),
	.ra(addr),
	.wa(addr),
	.di(di),
	.doq(doq)
);

`else

`ifdef OR1200_VIRAGE_SSP






virage_ssp virage_ssp(
	.clk(clk),
	.adr(addr),
	.d(di),
	.we(we),
	.oe(oe),
	.me(ce),
	.q(doq)
);

`else

`ifdef OR1200_VIRTUALSILICON_SSP






`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST

	.mbist_si_i(mbist_si_i),
	.mbist_so_o(mbist_so_o),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.CK(clk),
	.ADR(addr),
	.DI(di),
	.WEN(~we),
	.CEN(~ce),
	.OEN(~oe),
	.DOUT(doq)
);

`else

`ifdef OR1200_XILINX_RAMB4










RAMB4_S8 ramb4_s8_0(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[7:0]),
	.EN(ce),
	.WE(we),
	.DO(doq[7:0])
);




RAMB4_S8 ramb4_s8_1(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI(di[15:8]),
	.EN(ce),
	.WE(we),
	.DO(doq[15:8])
);




RAMB4_S8 ramb4_s8_2(
	.CLK(clk),
	.RST(rst),
	.ADDR(addr),
	.DI({4'b0000, di[19:16]}),
	.EN(ce),
	.WE(we),
	.DO({unconnected, doq[19:16]})
);

`else

`ifdef OR1200_XILINX_RAMB16









RAMB16_S36 ramb16_s36(
	.CLK(clk),
	.SSR(rst),
	.ADDR(addr),
	.DI({12'h000,di}),
	.DIP(4'h0),
	.EN(ce),
	.WE(we),
	.DO({unconnected,doq}),
	.DOP()
);

`else

`ifdef OR1200_ALTERA_LPM









wire    wr;

assign  wr = ce & we;

initial $display("Using Altera LPM.");

lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(doq)
);

defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";


`else








reg	[dw-1:0]	mem [(1<<aw)-1:0];
reg	[aw-1:0]	addr_reg;




assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};




always @(posedge clk or posedge rst)
	if (rst)
		addr_reg <= #1 {aw{1'b0}};
	else if (ce)
		addr_reg <= #1 addr;




always @(posedge clk)
	if (ce && we)
		mem[addr] <= #1 di;

`endif
`endif
`endif
`endif
`endif
`endif
`endif

endmodule