data/full_repos/permissive/128100618/SV/FP_operations_design.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/128100618/SV/FP_operations_design.v:280: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'DE2_Top\'\nmodule DE2_Top (\n       ^~~~~~~\n                                                                                     : ... Top module \'fpneg\'\nmodule fpneg(fout, f1) ;\n       ^~~~~\n                                                                                     : ... Top module \'int2fp\'\nmodule int2fp(fp_out, int_in, scale_in) ;\n       ^~~~~~\n                                                                                     : ... Top module \'fp2int\'\nmodule fp2int(int_out, fp_in, scale_in) ;\n       ^~~~~~\n                                                                                     : ... Top module \'fpinv\'\nmodule fpinv (fout, f1);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FP_operations_design.v:263: Input port connection \'num\' expects 4 bits on the pin connection, but pin connection\'s SEL generates 1 bits.\n                                                                                  : ... In instance DE2_Top\n HexDigit d2(HEX2, disp[8]);\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FP_operations_design.v:619: Operator SHIFTR expects 10 bits on the LHS, but LHS\'s VARREF \'m_in\' generates 9 bits.\n                                                                                  : ... In instance fp2int\n assign abs_int = (e_in>8\'h80)? (m_in >> (8\'h89 - e_in)) : 10\'d0 ;\n                                      ^~\n%Error: Exiting due to 3 warning(s)\n'
module int2fp(fp_out, int_in, scale_in) ;
	input signed  [9:0] int_in ;
	input signed  [7:0] scale_in ;
	output wire [17:0] fp_out ; 
	
	wire [9:0] abs_int ;
	reg sign ;
	reg [8:0] mout ;
	reg [7:0] eout ;
	reg [7:0] num_zeros ;
	

	assign abs_int = (int_in[9])? (~int_in)+10'd1 : int_in ;
	

	assign fp_out = {sign, eout, mout} ;
	 



	always @(*)
	begin
		if (abs_int[8:0] == 0)
		begin
			eout = 0 ;
			mout = 0 ;
			sign = 0 ;
			num_zeros = 8'd0 ;
		end 
		else
		begin
			casex (abs_int[8:0])
				9'b1xxxxxxxx: num_zeros = 8'd0 ;
				9'b01xxxxxxx: num_zeros = 8'd1 ;
				9'b001xxxxxx: num_zeros = 8'd2 ;
				9'b0001xxxxx: num_zeros = 8'd3 ;
				9'b00001xxxx: num_zeros = 8'd4 ;
				9'b000001xxx: num_zeros = 8'd5 ;
				9'b0000001xx: num_zeros = 8'd6 ;
				9'b00000001x: num_zeros = 8'd7 ;
				9'b000000001: num_zeros = 8'd8 ;
				default:       num_zeros = 8'd9 ;
			endcase 
			mout = abs_int[8:0] << num_zeros ; 
			eout = scale_in + (8'h89 - num_zeros) ;
			sign = int_in[9] ;
		end
	end
	
endmodule
module int2fp(fp_out, int_in, scale_in) ;

	input signed  [9:0] int_in ;
	input signed  [7:0] scale_in ;
	output wire [17:0] fp_out ; 
	
	wire [9:0] abs_int ;
	reg sign ;
	reg [8:0] mout ;
	reg [7:0] eout ;
	reg [7:0] num_zeros ;
	

	assign abs_int = (int_in[9])? (~int_in)+10'd1 : int_in ;
	

	assign fp_out = {sign, eout, mout} ;
	 



	always @(*)
	begin
		if (abs_int[8:0] == 0)
		begin
			eout = 0 ;
			mout = 0 ;
			sign = 0 ;
			num_zeros = 8'd0 ;
		end 
		else
		begin
			casex (abs_int[8:0])
				9'b1xxxxxxxx: num_zeros = 8'd0 ;
				9'b01xxxxxxx: num_zeros = 8'd1 ;
				9'b001xxxxxx: num_zeros = 8'd2 ;
				9'b0001xxxxx: num_zeros = 8'd3 ;
				9'b00001xxxx: num_zeros = 8'd4 ;
				9'b000001xxx: num_zeros = 8'd5 ;
				9'b0000001xx: num_zeros = 8'd6 ;
				9'b00000001x: num_zeros = 8'd7 ;
				9'b000000001: num_zeros = 8'd8 ;
				default:       num_zeros = 8'd9 ;
			endcase 
			mout = abs_int[8:0] << num_zeros ; 
			eout = scale_in + (8'h89 - num_zeros) ;
			sign = int_in[9] ;
		end
	end
	
endmodule