data/full_repos/permissive/205055389/test/verga/uops.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/uops.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205055389/test/verga/uops.v:10: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                         : ... In instance top\n      a = x;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/205055389/test/verga/uops.v:11: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s NOT generates 32 bits.\n                                                                         : ... In instance top\n      b = ~x;\n        ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg a,b;
  reg [31:0] x;
  reg [31:0] r;

 
  initial
    begin
      x = ~0;
      a = x;
      b = ~x;
      #1;
      $display("a=%h  b=%h",a,b);
      if (a) $display("a is true.");
      if (~a) $display("~a is true.");
      if (!a) $display("!a is true.");
      if (b) $display("b is true.");
      if (~b) $display("~b is true.");
      if (!b) $display("!b is true.");

      r = 32'hz;
      $display("r='h%h   r='o%o",r,r);
    end

endmodule
module top;

  reg a,b;
  reg [31:0] x;
  reg [31:0] r;

 
  initial
    begin
      x = ~0;
      a = x;
      b = ~x;
      #1;
      $display("a=%h  b=%h",a,b);
      if (a) $display("a is true.");
      if (~a) $display("~a is true.");
      if (!a) $display("!a is true.");
      if (b) $display("b is true.");
      if (~b) $display("~b is true.");
      if (!b) $display("!b is true.");

      r = 32'hz;
      $display("r='h%h   r='o%o",r,r);
    end

endmodule