data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:104: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                           : ... In instance axi_wr_fifo\n      wr_pt <= 4\'h0 ;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:105: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                           : ... In instance axi_wr_fifo\n      rd_pt <= 4\'h0 ;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:136: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                                           : ... In instance axi_wr_fifo\nwire fifo_flush_cond = |fill_lvl && !wr_val_i && !dat_cnt[3:1];\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:167: Operator SUB expects 34 bits on the LHS, but LHS\'s REPLICATE generates 30 bits.\n                                                                                           : ... In instance axi_wr_fifo\nwire [AW  :0] next_stop_address  = {1\'b0,sys_stop_addr_r[AW-1:3]} - next_address[AW:3] - {{AW-FW+1{1\'h0}},fill_lvl} ;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:167: Operator SUB expects 34 bits on the RHS, but RHS\'s SEL generates 30 bits.\n                                                                                           : ... In instance axi_wr_fifo\nwire [AW  :0] next_stop_address  = {1\'b0,sys_stop_addr_r[AW-1:3]} - next_address[AW:3] - {{AW-FW+1{1\'h0}},fill_lvl} ;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:167: Operator ASSIGNW expects 33 bits on the Assign RHS, but Assign RHS\'s SUB generates 34 bits.\n                                                                                           : ... In instance axi_wr_fifo\nwire [AW  :0] next_stop_address  = {1\'b0,sys_stop_addr_r[AW-1:3]} - next_address[AW:3] - {{AW-FW+1{1\'h0}},fill_lvl} ;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:170: Operator ADD expects 34 bits on the LHS, but LHS\'s REPLICATE generates 31 bits.\n                                                                                           : ... In instance axi_wr_fifo\nwire [AW+1:0] boundary_condition = {1\'b0,next_address[AW:3]} + {{AW-FW+1{1\'h0}},fill_lvl} - {1\'b0,sys_stop_addr_r[AW-1:3]} ;\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:170: Operator SUB expects 34 bits on the RHS, but RHS\'s REPLICATE generates 30 bits.\n                                                                                           : ... In instance axi_wr_fifo\nwire [AW+1:0] boundary_condition = {1\'b0,next_address[AW:3]} + {{AW-FW+1{1\'h0}},fill_lvl} - {1\'b0,sys_stop_addr_r[AW-1:3]} ;\n                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:187: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'fill_lvl\' generates 6 bits.\n                                                                                           : ... In instance axi_wr_fifo\n      single_burst   <= (!fill_lvl && !fifo_flush && !dat_cnt && data_in_reg) ;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:187: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'dat_cnt\' generates 4 bits.\n                                                                                           : ... In instance axi_wr_fifo\n      single_burst   <= (!fill_lvl && !fifo_flush && !dat_cnt && data_in_reg) ;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:193: Operator GTE expects 6 bits on the RHS, but RHS\'s REPLICATE generates 5 bits.\n                                                                                           : ... In instance axi_wr_fifo\nassign new_burst = (((fifo_flush && axi_wrdy_i) || (fill_lvl >= {{FW-4{1\'b0}},sys_trig_size_r})) && !dat_cnt && |fill_lvl \n                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:193: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'dat_cnt\' generates 4 bits.\n                                                                                           : ... In instance axi_wr_fifo\nassign new_burst = (((fifo_flush && axi_wrdy_i) || (fill_lvl >= {{FW-4{1\'b0}},sys_trig_size_r})) && !dat_cnt && |fill_lvl \n                                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:208: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                           : ... In instance axi_wr_fifo\n            if (fill_lvl[FW:4] && !boundary_cross[1:0]) begin   \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:208: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                           : ... In instance axi_wr_fifo\n            if (fill_lvl[FW:4] && !boundary_cross[1:0]) begin   \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:207: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                           : ... In instance axi_wr_fifo\n         if (boundary_cross[1:0] || fill_lvl[FW:4]) begin\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:207: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                           : ... In instance axi_wr_fifo\n         if (boundary_cross[1:0] || fill_lvl[FW:4]) begin\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:237: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'dat_cnt\' generates 4 bits.\n                                                                                           : ... In instance axi_wr_fifo\n      else if (axi_wrdy_i && axi_wvalid_o && dat_cnt) begin\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:253: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'fill_lvl\' generates 6 bits.\n                                                                                           : ... In instance axi_wr_fifo\nassign pop =  (!data_in_reg && fill_lvl) || ((|dat_cnt || (new_burst && axi_wvalid_o)) \n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:254: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'fill_lvl\' generates 6 bits.\n                                                                                           : ... In instance axi_wr_fifo\n            && axi_wrdy_i && axi_wvalid_o && fill_lvl) ;\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:268: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'fill_lvl\' generates 6 bits.\n                                                                                           : ... In instance axi_wr_fifo\n          ( (new_burst && axi_wrdy_i) || (|dat_cnt && axi_wrdy_i && fill_lvl) ) ) begin   \n                                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/axi_wr_fifo.v:296: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'next_address\' generates 33 bits.\n                                                                                           : ... In instance axi_wr_fifo\nassign stat_cur_addr_o = next_address ;  \n                       ^\n%Error: Exiting due to 21 warning(s)\n'
module axi_wr_fifo #(
  parameter   DW  =  64      ,
  parameter   AW  =  32      ,
  parameter   FW  =   5      ,
  parameter   SW  = DW >> 3
)
(

   input                  axi_clk_i          ,
   input                  axi_rstn_i         ,


   output reg  [ AW-1: 0] axi_waddr_o        ,
   output reg  [ DW-1: 0] axi_wdata_o        ,
   output reg  [ SW-1: 0] axi_wsel_o         ,
   output reg             axi_wvalid_o       ,
   output reg  [  4-1: 0] axi_wlen_o         ,
   output reg             axi_wfixed_o       ,
   input                  axi_werr_i         ,
   input                  axi_wrdy_i         ,


   input       [ DW-1: 0] wr_data_i          ,
   input                  wr_val_i           ,
   input       [ AW-1: 0] ctrl_start_addr_i  ,
   input       [ AW-1: 0] ctrl_stop_addr_i   ,
   input       [  4-1: 0] ctrl_trig_size_i   ,
   input                  ctrl_wrap_i        ,
   input                  ctrl_clr_i         ,
   output reg             stat_overflow_o    ,
   output      [ AW-1: 0] stat_cur_addr_o    ,
   output reg             stat_write_data_o
);








reg  [ FW-1: 0] wr_pt              ;
reg  [ FW-1: 0] rd_pt              ;
reg  [ FW  : 0] fill_lvl           ;
reg  [ DW-1: 0] fifo[(1<<FW)-1:0]  ;
reg             data_in_reg        ;
reg             clear              ;
reg  [  4-1: 0] dat_cnt            ;
reg  [ AW  : 0] next_address       ;
reg             fifo_flush         ;
reg  [ AW-1: 0] sys_start_addr_r   ;
reg  [ AW-1: 0] sys_stop_addr_r    ;
reg  [  4-1: 0] sys_trig_size_r    ;

wire push = wr_val_i && !fill_lvl[FW] ;
wire pop ;
wire new_burst ;


always @ (posedge axi_clk_i)
begin
   if (!axi_rstn_i) begin
      stat_overflow_o <= 'h0 ;
   end
   else begin
      stat_overflow_o <= fill_lvl[FW] && wr_val_i;
   end
end

reg clear_do ;
always @ (posedge axi_clk_i)
begin
   if (!axi_rstn_i) begin
      clear    <= 1'h1 ;
      clear_do <= 1'b0 ;
   end
   else begin 
      if (ctrl_clr_i)
         clear_do <= 1'b1 ;
      else if (clear)
         clear_do <= 1'b0 ;

      clear <= clear_do && !axi_wvalid_o && !new_burst;
   end
end



always @ (posedge axi_clk_i)
begin
   if (clear) begin
      wr_pt <= 4'h0 ;
      rd_pt <= 4'h0 ;
   end
   else begin
      if (push) begin
         fifo[wr_pt] <= wr_data_i                  ;
         wr_pt       <= wr_pt + {{FW-1{1'b0}},1'b1} ;
      end

      if (pop) begin
         axi_wdata_o <= fifo[rd_pt]                 ;
         rd_pt       <= rd_pt + {{FW-1{1'b0}},1'b1} ;
      end
   end
end



always @(posedge axi_clk_i)
begin
   if (!axi_rstn_i) begin
      data_in_reg <= 'h0 ;
   end
   else begin
      if (pop)
         data_in_reg <= 1'b1 ;
      else if ((axi_wrdy_i && axi_wvalid_o) || clear)
         data_in_reg <= 1'b0 ;
   end
end


wire fifo_flush_cond = |fill_lvl && !wr_val_i && !dat_cnt[3:1];

always @(posedge axi_clk_i)
begin
   if (clear) begin
      fill_lvl   <= {FW+1{1'h0}} ;
      fifo_flush <= 1'h0 ;
   end
   else begin
      if (push && !pop)
         fill_lvl <= fill_lvl + {{FW{1'b0}}, 1'h1} ;
      else if(!push && pop)
         fill_lvl <= fill_lvl - {{FW{1'b0}}, 1'h1} ;

      if (fifo_flush_cond)
         fifo_flush <= 1'b1 ;
      else if (axi_wrdy_i)
         fifo_flush <= 1'b0 ;
   end
end










wire [8   :0] next_end_address   = next_address[10:3] + {3'h0,fill_lvl} ;
wire [AW  :0] next_stop_address  = {1'b0,sys_stop_addr_r[AW-1:3]} - next_address[AW:3] - {{AW-FW+1{1'h0}},fill_lvl} ;


wire [AW+1:0] boundary_condition = {1'b0,next_address[AW:3]} + {{AW-FW+1{1'h0}},fill_lvl} - {1'b0,sys_stop_addr_r[AW-1:3]} ;


wire [2   :0] boundary_cross     = {boundary_condition[AW+1], next_end_address[8],next_stop_address[AW]} ;


reg  single_burst    ;
reg  single_burst_r  ;
wire single_burst_posedge = !single_burst_r && single_burst;

always @(posedge axi_clk_i)
begin
   if (clear) begin
      single_burst   <= 'h0 ;
      single_burst_r <= 'h0 ;
   end
   else begin
      single_burst   <= (!fill_lvl && !fifo_flush && !dat_cnt && data_in_reg) ;
      single_burst_r <= single_burst ;
   end
end


assign new_burst = (((fifo_flush && axi_wrdy_i) || (fill_lvl >= {{FW-4{1'b0}},sys_trig_size_r})) && !dat_cnt && |fill_lvl 
                 || single_burst_posedge)
                 && !clear_do;

always @(posedge axi_clk_i)
begin
   if (clear) begin
      dat_cnt      <= 4'h0 ;
      axi_wsel_o   <= {SW{1'b1}} ;
      axi_wfixed_o <= 1'b0 ;
      axi_wlen_o   <= 4'h0 ;
   end
   else begin
      if (new_burst && (next_address <= {1'b0,sys_stop_addr_r})) begin
         if (boundary_cross[1:0] || fill_lvl[FW:4]) begin
            if (fill_lvl[FW:4] && !boundary_cross[1:0]) begin
               dat_cnt    <= 4'hF ;
               axi_wlen_o <= 4'hF ;
            end
            else begin



               if (boundary_cross[2]) begin
                  dat_cnt    <= 4'hF - next_address[6:3];
                  axi_wlen_o <= 4'hF - next_address[6:3];
               end
               else begin
                  dat_cnt    <= sys_stop_addr_r[6:3] - next_address[6:3];
                  axi_wlen_o <= sys_stop_addr_r[6:3] - next_address[6:3];
               end
            end
         end
         else begin
            if (fifo_flush || fifo_flush_cond) begin
               dat_cnt    <= fill_lvl[3:0] - 4'h1 ;
               axi_wlen_o <= fill_lvl[3:0] - 4'h1 ;
            end
            else begin
               dat_cnt    <= fill_lvl[3:0] ;
               axi_wlen_o <= fill_lvl[3:0] ;
            end
         end
      end
      else if (axi_wrdy_i && axi_wvalid_o && dat_cnt) begin
         dat_cnt    <= dat_cnt    - 4'h1;
         axi_wlen_o <= axi_wlen_o - 4'h1;
      end
   end
end


wire [4-1: 0] aaaa = 4'hF - next_address[6:3];
wire [4-1: 0] bbbb = sys_stop_addr_r[6:3] - next_address[6:3];
wire [4-1: 0] cccc = fill_lvl[3:0] - 4'h1;
wire [4-1: 0] dddd = fill_lvl[3:0];




assign pop =  (!data_in_reg && fill_lvl) || ((|dat_cnt || (new_burst && axi_wvalid_o)) 
            && axi_wrdy_i && axi_wvalid_o && fill_lvl) ;

always @(posedge axi_clk_i)
begin
   if (clear) begin
      axi_wvalid_o     <= 1'h0                     ;
      axi_waddr_o      <= ctrl_start_addr_i        ;
      next_address     <= {1'b0,ctrl_start_addr_i} ;
      sys_start_addr_r <= ctrl_start_addr_i        ;
      sys_stop_addr_r  <= ctrl_stop_addr_i         ;
      sys_trig_size_r  <= ctrl_trig_size_i         ;
   end
   else begin
      if ((next_address <= {1'b0,sys_stop_addr_r}) &&
          ( (new_burst && axi_wrdy_i) || (|dat_cnt && axi_wrdy_i && fill_lvl) ) ) begin
         axi_wvalid_o <= 1'h1 ;
         next_address <= next_address + DW/8  ;
         axi_waddr_o  <= next_address[AW-1:0] ;
      end
      else if (ctrl_wrap_i && new_burst && (axi_waddr_o==sys_stop_addr_r)) begin
         axi_wvalid_o <= 1'h1 ;
         next_address <= {1'b0,sys_start_addr_r} + DW/8  ;
         axi_waddr_o  <= sys_start_addr_r ;
      end
      else if (axi_wrdy_i) begin
         axi_wvalid_o <= 1'h0 ;
      end
   end
end



always @(posedge axi_clk_i)
begin
   if (!axi_rstn_i) begin
      stat_write_data_o <= 'h0 ;
   end
   else begin
      stat_write_data_o <= (next_address <= {1'b0,sys_stop_addr_r}) ;
   end
end

assign stat_cur_addr_o = next_address ;



endmodule
module axi_wr_fifo #(
  parameter   DW  =  64      ,
  parameter   AW  =  32      ,
  parameter   FW  =   5      ,
  parameter   SW  = DW >> 3
)
(

   input                  axi_clk_i          ,
   input                  axi_rstn_i         ,


   output reg  [ AW-1: 0] axi_waddr_o        ,
   output reg  [ DW-1: 0] axi_wdata_o        ,
   output reg  [ SW-1: 0] axi_wsel_o         ,
   output reg             axi_wvalid_o       ,
   output reg  [  4-1: 0] axi_wlen_o         ,
   output reg             axi_wfixed_o       ,
   input                  axi_werr_i         ,
   input                  axi_wrdy_i         ,


   input       [ DW-1: 0] wr_data_i          ,
   input                  wr_val_i           ,
   input       [ AW-1: 0] ctrl_start_addr_i  ,
   input       [ AW-1: 0] ctrl_stop_addr_i   ,
   input       [  4-1: 0] ctrl_trig_size_i   ,
   input                  ctrl_wrap_i        ,
   input                  ctrl_clr_i         ,
   output reg             stat_overflow_o    ,
   output      [ AW-1: 0] stat_cur_addr_o    ,
   output reg             stat_write_data_o
);









reg  [ FW-1: 0] wr_pt              ;
reg  [ FW-1: 0] rd_pt              ;
reg  [ FW  : 0] fill_lvl           ;
reg  [ DW-1: 0] fifo[(1<<FW)-1:0]  ;
reg             data_in_reg        ;
reg             clear              ;
reg  [  4-1: 0] dat_cnt            ;
reg  [ AW  : 0] next_address       ;
reg             fifo_flush         ;
reg  [ AW-1: 0] sys_start_addr_r   ;
reg  [ AW-1: 0] sys_stop_addr_r    ;
reg  [  4-1: 0] sys_trig_size_r    ;

wire push = wr_val_i && !fill_lvl[FW] ;
wire pop ;
wire new_burst ;


always @ (posedge axi_clk_i)
begin
   if (!axi_rstn_i) begin
      stat_overflow_o <= 'h0 ;
   end
   else begin
      stat_overflow_o <= fill_lvl[FW] && wr_val_i;
   end
end

reg clear_do ;
always @ (posedge axi_clk_i)
begin
   if (!axi_rstn_i) begin
      clear    <= 1'h1 ;
      clear_do <= 1'b0 ;
   end
   else begin 
      if (ctrl_clr_i)
         clear_do <= 1'b1 ;
      else if (clear)
         clear_do <= 1'b0 ;

      clear <= clear_do && !axi_wvalid_o && !new_burst;
   end
end



always @ (posedge axi_clk_i)
begin
   if (clear) begin
      wr_pt <= 4'h0 ;
      rd_pt <= 4'h0 ;
   end
   else begin
      if (push) begin
         fifo[wr_pt] <= wr_data_i                  ;
         wr_pt       <= wr_pt + {{FW-1{1'b0}},1'b1} ;
      end

      if (pop) begin
         axi_wdata_o <= fifo[rd_pt]                 ;
         rd_pt       <= rd_pt + {{FW-1{1'b0}},1'b1} ;
      end
   end
end



always @(posedge axi_clk_i)
begin
   if (!axi_rstn_i) begin
      data_in_reg <= 'h0 ;
   end
   else begin
      if (pop)
         data_in_reg <= 1'b1 ;
      else if ((axi_wrdy_i && axi_wvalid_o) || clear)
         data_in_reg <= 1'b0 ;
   end
end


wire fifo_flush_cond = |fill_lvl && !wr_val_i && !dat_cnt[3:1];

always @(posedge axi_clk_i)
begin
   if (clear) begin
      fill_lvl   <= {FW+1{1'h0}} ;
      fifo_flush <= 1'h0 ;
   end
   else begin
      if (push && !pop)
         fill_lvl <= fill_lvl + {{FW{1'b0}}, 1'h1} ;
      else if(!push && pop)
         fill_lvl <= fill_lvl - {{FW{1'b0}}, 1'h1} ;

      if (fifo_flush_cond)
         fifo_flush <= 1'b1 ;
      else if (axi_wrdy_i)
         fifo_flush <= 1'b0 ;
   end
end










wire [8   :0] next_end_address   = next_address[10:3] + {3'h0,fill_lvl} ;
wire [AW  :0] next_stop_address  = {1'b0,sys_stop_addr_r[AW-1:3]} - next_address[AW:3] - {{AW-FW+1{1'h0}},fill_lvl} ;


wire [AW+1:0] boundary_condition = {1'b0,next_address[AW:3]} + {{AW-FW+1{1'h0}},fill_lvl} - {1'b0,sys_stop_addr_r[AW-1:3]} ;


wire [2   :0] boundary_cross     = {boundary_condition[AW+1], next_end_address[8],next_stop_address[AW]} ;


reg  single_burst    ;
reg  single_burst_r  ;
wire single_burst_posedge = !single_burst_r && single_burst;

always @(posedge axi_clk_i)
begin
   if (clear) begin
      single_burst   <= 'h0 ;
      single_burst_r <= 'h0 ;
   end
   else begin
      single_burst   <= (!fill_lvl && !fifo_flush && !dat_cnt && data_in_reg) ;
      single_burst_r <= single_burst ;
   end
end


assign new_burst = (((fifo_flush && axi_wrdy_i) || (fill_lvl >= {{FW-4{1'b0}},sys_trig_size_r})) && !dat_cnt && |fill_lvl 
                 || single_burst_posedge)
                 && !clear_do;

always @(posedge axi_clk_i)
begin
   if (clear) begin
      dat_cnt      <= 4'h0 ;
      axi_wsel_o   <= {SW{1'b1}} ;
      axi_wfixed_o <= 1'b0 ;
      axi_wlen_o   <= 4'h0 ;
   end
   else begin
      if (new_burst && (next_address <= {1'b0,sys_stop_addr_r})) begin
         if (boundary_cross[1:0] || fill_lvl[FW:4]) begin
            if (fill_lvl[FW:4] && !boundary_cross[1:0]) begin
               dat_cnt    <= 4'hF ;
               axi_wlen_o <= 4'hF ;
            end
            else begin



               if (boundary_cross[2]) begin
                  dat_cnt    <= 4'hF - next_address[6:3];
                  axi_wlen_o <= 4'hF - next_address[6:3];
               end
               else begin
                  dat_cnt    <= sys_stop_addr_r[6:3] - next_address[6:3];
                  axi_wlen_o <= sys_stop_addr_r[6:3] - next_address[6:3];
               end
            end
         end
         else begin
            if (fifo_flush || fifo_flush_cond) begin
               dat_cnt    <= fill_lvl[3:0] - 4'h1 ;
               axi_wlen_o <= fill_lvl[3:0] - 4'h1 ;
            end
            else begin
               dat_cnt    <= fill_lvl[3:0] ;
               axi_wlen_o <= fill_lvl[3:0] ;
            end
         end
      end
      else if (axi_wrdy_i && axi_wvalid_o && dat_cnt) begin
         dat_cnt    <= dat_cnt    - 4'h1;
         axi_wlen_o <= axi_wlen_o - 4'h1;
      end
   end
end


wire [4-1: 0] aaaa = 4'hF - next_address[6:3];
wire [4-1: 0] bbbb = sys_stop_addr_r[6:3] - next_address[6:3];
wire [4-1: 0] cccc = fill_lvl[3:0] - 4'h1;
wire [4-1: 0] dddd = fill_lvl[3:0];




assign pop =  (!data_in_reg && fill_lvl) || ((|dat_cnt || (new_burst && axi_wvalid_o)) 
            && axi_wrdy_i && axi_wvalid_o && fill_lvl) ;

always @(posedge axi_clk_i)
begin
   if (clear) begin
      axi_wvalid_o     <= 1'h0                     ;
      axi_waddr_o      <= ctrl_start_addr_i        ;
      next_address     <= {1'b0,ctrl_start_addr_i} ;
      sys_start_addr_r <= ctrl_start_addr_i        ;
      sys_stop_addr_r  <= ctrl_stop_addr_i         ;
      sys_trig_size_r  <= ctrl_trig_size_i         ;
   end
   else begin
      if ((next_address <= {1'b0,sys_stop_addr_r}) &&
          ( (new_burst && axi_wrdy_i) || (|dat_cnt && axi_wrdy_i && fill_lvl) ) ) begin
         axi_wvalid_o <= 1'h1 ;
         next_address <= next_address + DW/8  ;
         axi_waddr_o  <= next_address[AW-1:0] ;
      end
      else if (ctrl_wrap_i && new_burst && (axi_waddr_o==sys_stop_addr_r)) begin
         axi_wvalid_o <= 1'h1 ;
         next_address <= {1'b0,sys_start_addr_r} + DW/8  ;
         axi_waddr_o  <= sys_start_addr_r ;
      end
      else if (axi_wrdy_i) begin
         axi_wvalid_o <= 1'h0 ;
      end
   end
end



always @(posedge axi_clk_i)
begin
   if (!axi_rstn_i) begin
      stat_write_data_o <= 'h0 ;
   end
   else begin
      stat_write_data_o <= (next_address <= {1'b0,sys_stop_addr_r}) ;
   end
end

assign stat_cur_addr_o = next_address ;



endmodule