data/full_repos/permissive/128426084/src/sources_1/new/Title_Screen.v
1: b'%Error: data/full_repos/permissive/128426084/src/sources_1/new/Title_Screen.v:21: Cannot find include file: verilog_macro_bus.vh\n`include "verilog_macro_bus.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.v\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.sv\n             verilog_macro_bus.vh\n             verilog_macro_bus.vh.v\n             verilog_macro_bus.vh.sv\n             obj_dir/verilog_macro_bus.vh\n             obj_dir/verilog_macro_bus.vh.v\n             obj_dir/verilog_macro_bus.vh.sv\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/Title_Screen.v:25: Define or directive not defined: \'`VGA_BUS_SIZE\'\n    input wire [`VGA_BUS_SIZE-1:0] vga_in,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/Title_Screen.v:26: Define or directive not defined: \'`VGA_BUS_SIZE\'\n    output wire [`VGA_BUS_SIZE-1:0] vga_out,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/Title_Screen.v:31: Define or directive not defined: \'`VGA_BUS_SIZE\'\n    wire [`VGA_BUS_SIZE - 1 : 0] vga_bus [1:0];\n          ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module Title_Screen(
    input wire pclk,
    input wire [`VGA_BUS_SIZE-1:0] vga_in,
    output wire [`VGA_BUS_SIZE-1:0] vga_out,
    input wire playerCount

    );
    
    wire [`VGA_BUS_SIZE - 1 : 0] vga_bus [1:0];
      wire [18:0] address;
      wire [3:0] rgb_back;
      
      wire [6:0] char_code;
      wire [7:0] char_line_pixels;  
      wire [7:0] char_xy;
      wire [3:0] char_line;
    
  draw_background my_background(
        .vga_in(vga_in[37:0]),
        .vga_out(vga_bus[0]),
        .address(address),
        .rgb(rgb_back)
        );
    
          draw_rect_char rect_char(
            .pclk(pclk),
            .vga_in(vga_bus[0]),
            .char_pixels(char_line_pixels),
            .char_xy(char_xy),
            .char_line(char_line),
            .vga_out(vga_out),
            .playerCount(playerCount)
        );
        
        font_rom  font_rom(
            .addr({char_code,char_line}),
            .data(char_line_pixels)
        );
        
        char_rom_16x16 char_rom(
            .char_xy(char_xy),
            .code(char_code)
        );
      
      start_screen screen(
        .address(address),
        .rgb(rgb_back)
      );

    
endmodule
module Title_Screen(
    input wire pclk,
    input wire [`VGA_BUS_SIZE-1:0] vga_in,
    output wire [`VGA_BUS_SIZE-1:0] vga_out,
    input wire playerCount

    );

    
    wire [`VGA_BUS_SIZE - 1 : 0] vga_bus [1:0];
      wire [18:0] address;
      wire [3:0] rgb_back;
      
      wire [6:0] char_code;
      wire [7:0] char_line_pixels;  
      wire [7:0] char_xy;
      wire [3:0] char_line;
    
  draw_background my_background(
        .vga_in(vga_in[37:0]),
        .vga_out(vga_bus[0]),
        .address(address),
        .rgb(rgb_back)
        );
    
          draw_rect_char rect_char(
            .pclk(pclk),
            .vga_in(vga_bus[0]),
            .char_pixels(char_line_pixels),
            .char_xy(char_xy),
            .char_line(char_line),
            .vga_out(vga_out),
            .playerCount(playerCount)
        );
        
        font_rom  font_rom(
            .addr({char_code,char_line}),
            .data(char_line_pixels)
        );
        
        char_rom_16x16 char_rom(
            .char_xy(char_xy),
            .code(char_code)
        );
      
      start_screen screen(
        .address(address),
        .rgb(rgb_back)
      );

    
endmodule