data/full_repos/permissive/127511545/src/ForwardingUnit.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:13: Signal definition not found, creating implicitly: \'A\'\n or #(50) o0(A, MEM_WriteRegister[4], MEM_WriteRegister[3], MEM_WriteRegister[2], MEM_WriteRegister[1], MEM_WriteRegister[0]);   \n             ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:15: Signal definition not found, creating implicitly: \'B\'\n and #(50) a0(X, MEM_RegisterWrite, A, B);    \n                                       ^\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:15: Signal definition not found, creating implicitly: \'X\'\n and #(50) a0(X, MEM_RegisterWrite, A, B);    \n              ^\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:17: Signal definition not found, creating implicitly: \'C\'\n or #(50) o1(C, WB_WriteRegister[4], WB_WriteRegister[3], WB_WriteRegister[2], WB_WriteRegister[1], WB_WriteRegister[0]);   \n             ^\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:19: Signal definition not found, creating implicitly: \'D\'\n and #(50) a1(Y, WB_RegisterWrite, C, D);    \n                                      ^\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:19: Signal definition not found, creating implicitly: \'Y\'\n and #(50) a1(Y, WB_RegisterWrite, C, D);    \n              ^\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:22: Signal definition not found, creating implicitly: \'NotX\'\n not #(50) inv0(NotX, X);\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:27: Signal definition not found, creating implicitly: \'B1\'\n                                                                               : ... Suggested alternative: \'B\'\n and #(50) a3(X1, MEM_RegisterWrite, A, B1);\n                                        ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:27: Signal definition not found, creating implicitly: \'X1\'\n                                                                               : ... Suggested alternative: \'B1\'\n and #(50) a3(X1, MEM_RegisterWrite, A, B1);\n              ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:28: Signal definition not found, creating implicitly: \'D1\'\n                                                                               : ... Suggested alternative: \'B1\'\n and #(50) a4(Y1, WB_RegisterWrite, C, D1);\n                                       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:28: Signal definition not found, creating implicitly: \'Y1\'\n                                                                               : ... Suggested alternative: \'B1\'\n and #(50) a4(Y1, WB_RegisterWrite, C, D1);\n              ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/ForwardingUnit.v:31: Signal definition not found, creating implicitly: \'NotX1\'\n                                                                               : ... Suggested alternative: \'NotX\'\n not #(50) inv1(NotX1, X1);\n                ^~~~~\n%Error: data/full_repos/permissive/127511545/src/ForwardingUnit.v:14: Cannot find file containing module: \'CompareAddress\'\n CompareAddress CompMEM_WriteReg_EXrs(B, MEM_WriteRegister, EX_rs);\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/CompareAddress\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/CompareAddress.v\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/CompareAddress.sv\n             CompareAddress\n             CompareAddress.v\n             CompareAddress.sv\n             obj_dir/CompareAddress\n             obj_dir/CompareAddress.v\n             obj_dir/CompareAddress.sv\n%Error: data/full_repos/permissive/127511545/src/ForwardingUnit.v:18: Cannot find file containing module: \'CompareAddress\'\n CompareAddress CompWB_WriteReg_EXrs(D, WB_WriteRegister, EX_rs);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127511545/src/ForwardingUnit.v:25: Cannot find file containing module: \'CompareAddress\'\n CompareAddress CompMEM_WriteReg_EXrt(B1, MEM_WriteRegister, EX_rt);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127511545/src/ForwardingUnit.v:26: Cannot find file containing module: \'CompareAddress\'\n CompareAddress CompWB_WriteReg_EXrt(D1, WB_WriteRegister, EX_rt);\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 12 warning(s)\n'
module ForwardingUnit(ForwardA, ForwardB, MEM_RegisterWrite, WB_RegisterWrite, MEM_WriteRegister, WB_WriteRegister, EX_rs, EX_rt);

	output[1:0] ForwardA, ForwardB;
	wire[1:0] ForwardA, ForwardB;
	input MEM_RegisterWrite, WB_RegisterWrite;
	input[4:0] MEM_WriteRegister, WB_WriteRegister, EX_rs, EX_rt;

	or #(50) o0(A, MEM_WriteRegister[4], MEM_WriteRegister[3], MEM_WriteRegister[2], MEM_WriteRegister[1], MEM_WriteRegister[0]);
	CompareAddress CompMEM_WriteReg_EXrs(B, MEM_WriteRegister, EX_rs);
	and #(50) a0(X, MEM_RegisterWrite, A, B);

	or #(50) o1(C, WB_WriteRegister[4], WB_WriteRegister[3], WB_WriteRegister[2], WB_WriteRegister[1], WB_WriteRegister[0]);
	CompareAddress CompWB_WriteReg_EXrs(D, WB_WriteRegister, EX_rs);
	and #(50) a1(Y, WB_RegisterWrite, C, D);

	assign ForwardA[1] = X;
	not #(50) inv0(NotX, X);
	and #(50) a2(ForwardA[0], NotX, Y);

	CompareAddress CompMEM_WriteReg_EXrt(B1, MEM_WriteRegister, EX_rt);
	CompareAddress CompWB_WriteReg_EXrt(D1, WB_WriteRegister, EX_rt);
	and #(50) a3(X1, MEM_RegisterWrite, A, B1);
	and #(50) a4(Y1, WB_RegisterWrite, C, D1);

	assign ForwardB[1] = X1;
	not #(50) inv1(NotX1, X1);
	and #(50) a5(ForwardB[0], NotX1, Y1);

endmodule
module ForwardingUnit(ForwardA, ForwardB, MEM_RegisterWrite, WB_RegisterWrite, MEM_WriteRegister, WB_WriteRegister, EX_rs, EX_rt);


	output[1:0] ForwardA, ForwardB;
	wire[1:0] ForwardA, ForwardB;
	input MEM_RegisterWrite, WB_RegisterWrite;
	input[4:0] MEM_WriteRegister, WB_WriteRegister, EX_rs, EX_rt;

	or #(50) o0(A, MEM_WriteRegister[4], MEM_WriteRegister[3], MEM_WriteRegister[2], MEM_WriteRegister[1], MEM_WriteRegister[0]);
	CompareAddress CompMEM_WriteReg_EXrs(B, MEM_WriteRegister, EX_rs);
	and #(50) a0(X, MEM_RegisterWrite, A, B);

	or #(50) o1(C, WB_WriteRegister[4], WB_WriteRegister[3], WB_WriteRegister[2], WB_WriteRegister[1], WB_WriteRegister[0]);
	CompareAddress CompWB_WriteReg_EXrs(D, WB_WriteRegister, EX_rs);
	and #(50) a1(Y, WB_RegisterWrite, C, D);

	assign ForwardA[1] = X;
	not #(50) inv0(NotX, X);
	and #(50) a2(ForwardA[0], NotX, Y);

	CompareAddress CompMEM_WriteReg_EXrt(B1, MEM_WriteRegister, EX_rt);
	CompareAddress CompWB_WriteReg_EXrt(D1, WB_WriteRegister, EX_rt);
	and #(50) a3(X1, MEM_RegisterWrite, A, B1);
	and #(50) a4(Y1, WB_RegisterWrite, C, D1);

	assign ForwardB[1] = X1;
	not #(50) inv1(NotX1, X1);
	and #(50) a5(ForwardB[0], NotX1, Y1);

endmodule