data/full_repos/permissive/20270692/labs/lab7/res/mux81b.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/20270692/labs/lab7/res/mux81b.v:4: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input [0:7] I;\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/20270692/labs/lab7/res/mux81b.v:7: Little bit endian vector: MSB < LSB of bit range: 0:2\n  input [0:2] S;  \n        ^\n%Error: Exiting due to 2 warning(s)\n'
module mux81b (I,S,Y);
  input [0:7] I;
  wire [0:7] I;

  input [0:2] S;
  wire [0:2] S;
  output Y;
  wire Y;

  wire A,B,C;

  assign A=S[0];
  assign B=S[1];
  assign C=S[2];

  assign Y=A?(B?(C?(I[7]):(I[6])):(C?(I[5]):(I[4]))):
  (B?(C?(I[3]):(I[2])):(C?(I[1]):(I[0])));

endmodule
module mux81b (I,S,Y);

  input [0:7] I;
  wire [0:7] I;

  input [0:2] S;
  wire [0:2] S;
  output Y;
  wire Y;

  wire A,B,C;

  assign A=S[0];
  assign B=S[1];
  assign C=S[2];

  assign Y=A?(B?(C?(I[7]):(I[6])):(C?(I[5]):(I[4]))):
  (B?(C?(I[3]):(I[2])):(C?(I[1]):(I[0])));

endmodule