data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b9.v
 line:112: before: "/"
1: b'%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b9.v:18: Cannot find file containing module: \'jt74194\'\n jt74194 u_4A(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74194\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74194.v\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74194.sv\n             jt74194\n             jt74194.v\n             jt74194.sv\n             obj_dir/jt74194\n             obj_dir/jt74194.v\n             obj_dir/jt74194.sv\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b9.v:28: Cannot find file containing module: \'jt74194\'\n jt74194 u_4B(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_b9.v:82: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 15 bits.\n                                                                                 : ... In instance jt_gng_b9\n addr = { AS, addr_lsb };\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module shift8(
	input [7:0] D,
	output Y,
	input [1:0] S,
	input SEL,
	input clk
);
	wire [3:0] Q4A, Q4B;

	jt74194 u_4A(
		.D		( { D[0], D[1], D[2], D[3] }	),
		.R		( 1'b0		),
		.L		( Q4B[0]	),
		.cl_b	( 1'b1		),
		.clk	( clk		),
		.S		( S			),
		.Q		( Q4A		)
	);

	jt74194 u_4B(
		.D		( { D[4], D[5], D[6], D[7] }	),
		.R		( Q4A[3]	),
		.L		( 1'b0		),
		.cl_b	( 1'b1		),
		.clk	( clk		),
		.S		( S			),
		.Q		( Q4B		)
	);
	assign Y = SEL ? Q4B[3] : Q4A[0];
endmodule
module shift8(
	input [7:0] D,
	output Y,
	input [1:0] S,
	input SEL,
	input clk
);

	wire [3:0] Q4A, Q4B;

	jt74194 u_4A(
		.D		( { D[0], D[1], D[2], D[3] }	),
		.R		( 1'b0		),
		.L		( Q4B[0]	),
		.cl_b	( 1'b1		),
		.clk	( clk		),
		.S		( S			),
		.Q		( Q4A		)
	);

	jt74194 u_4B(
		.D		( { D[4], D[5], D[6], D[7] }	),
		.R		( Q4A[3]	),
		.L		( 1'b0		),
		.cl_b	( 1'b1		),
		.clk	( clk		),
		.S		( S			),
		.Q		( Q4B		)
	);
	assign Y = SEL ? Q4B[3] : Q4A[0];
endmodule