data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:55: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:60: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:62: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:69: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:71: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:73: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:78: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:80: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:82: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Error: data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/alu32_testbench.v:87: Unsupported or unknown PLI call: $monitor\n$monitor("Selector : %1b%1b%1b\\n     A = %32b\\n     B = %32b\\n\\nResult = %32b  Zero Bit : %1b  OverFlow : %1b\\n", ALUselector2, ALUselector1, ALUselector0, a, b, result, ZeroBit, V);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu32_testbench(); 
reg [31:0]a, b;
reg ALUselector2, ALUselector1, ALUselector0;

wire [31:0]result;
wire ZeroBit,V;

alu32 alu32tb(ALUselector2, ALUselector1, ALUselector0, a, b, result, ZeroBit, V);

initial begin


ALUselector2 = 1'b0; ALUselector1 = 1'b0; ALUselector0 = 1'b0;
a = 32'hAF00_0001; b = 32'hADE0_0001;
#10;
a = 32'hABC0_DF02; b = 32'h1FA0_C001;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;


ALUselector2 = 1'b0; ALUselector1 = 1'b0; ALUselector0 = 1'b1;
a = 32'hAF00_0001; b = 32'hADE0_0001;
#10;
a = 32'hABC0_DF02; b = 32'h1FA0_C001;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;


ALUselector2 = 1'b0; ALUselector1 = 1'b1; ALUselector0 = 1'b0;
a = 32'hAF00_0001; b = 32'hADE0_0001;
#10;
a = 32'hABC0_DF02; b = 32'h0000_C001;
#10;
a = 32'h1234_5678; b = 32'h000F_CB01;
#10;
 

ALUselector2 = 1'b0; ALUselector1 = 1'b1; ALUselector0 = 1'b1;
a = 32'hAF00_0001; b = 32'hADE0_0001;
#10;
a = 32'hABC0_DF02; b = 32'h1FA0_C001;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;
 

ALUselector2 = 1'b1; ALUselector1 = 1'b0; ALUselector0 = 1'b0;
a = 32'hAF00_0501; b = 32'hAD00_0001;
#10;
a = 32'hABC0_DF02; b = 32'h1FA0_C001;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;


ALUselector2 = 1'b1; ALUselector1 = 1'b0; ALUselector0 = 1'b1;
a = 32'hAF00_0001; b = 32'h0000_0002;
#10;
a = 32'hABC0_DF02; b = 32'h0000_001F;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;


ALUselector2 = 1'b1; ALUselector1 = 1'b1; ALUselector0 = 1'b0;
a = 32'hAF00_CD01; b = 32'h0000_0001;
#10;
a = 32'hABC0_DF03; b = 32'h0000_001F;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;


ALUselector2 = 1'b1; ALUselector1 = 1'b1; ALUselector0 = 1'b1;
a = 32'hAF00_0001; b = 32'hADE0_F0A1;
#10;
a = 32'hABC0_DF02; b = 32'h1FA0_C0B1;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;

end

initial begin
$monitor("Selector : %1b%1b%1b\n     A = %32b\n     B = %32b\n\nResult = %32b  Zero Bit : %1b  OverFlow : %1b\n", ALUselector2, ALUselector1, ALUselector0, a, b, result, ZeroBit, V);
end
endmodule
module alu32_testbench();
 
reg [31:0]a, b;
reg ALUselector2, ALUselector1, ALUselector0;

wire [31:0]result;
wire ZeroBit,V;

alu32 alu32tb(ALUselector2, ALUselector1, ALUselector0, a, b, result, ZeroBit, V);

initial begin


ALUselector2 = 1'b0; ALUselector1 = 1'b0; ALUselector0 = 1'b0;
a = 32'hAF00_0001; b = 32'hADE0_0001;
#10;
a = 32'hABC0_DF02; b = 32'h1FA0_C001;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;


ALUselector2 = 1'b0; ALUselector1 = 1'b0; ALUselector0 = 1'b1;
a = 32'hAF00_0001; b = 32'hADE0_0001;
#10;
a = 32'hABC0_DF02; b = 32'h1FA0_C001;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;


ALUselector2 = 1'b0; ALUselector1 = 1'b1; ALUselector0 = 1'b0;
a = 32'hAF00_0001; b = 32'hADE0_0001;
#10;
a = 32'hABC0_DF02; b = 32'h0000_C001;
#10;
a = 32'h1234_5678; b = 32'h000F_CB01;
#10;
 

ALUselector2 = 1'b0; ALUselector1 = 1'b1; ALUselector0 = 1'b1;
a = 32'hAF00_0001; b = 32'hADE0_0001;
#10;
a = 32'hABC0_DF02; b = 32'h1FA0_C001;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;
 

ALUselector2 = 1'b1; ALUselector1 = 1'b0; ALUselector0 = 1'b0;
a = 32'hAF00_0501; b = 32'hAD00_0001;
#10;
a = 32'hABC0_DF02; b = 32'h1FA0_C001;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;


ALUselector2 = 1'b1; ALUselector1 = 1'b0; ALUselector0 = 1'b1;
a = 32'hAF00_0001; b = 32'h0000_0002;
#10;
a = 32'hABC0_DF02; b = 32'h0000_001F;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;


ALUselector2 = 1'b1; ALUselector1 = 1'b1; ALUselector0 = 1'b0;
a = 32'hAF00_CD01; b = 32'h0000_0001;
#10;
a = 32'hABC0_DF03; b = 32'h0000_001F;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;


ALUselector2 = 1'b1; ALUselector1 = 1'b1; ALUselector0 = 1'b1;
a = 32'hAF00_0001; b = 32'hADE0_F0A1;
#10;
a = 32'hABC0_DF02; b = 32'h1FA0_C0B1;
#10;
a = 32'h1234_5678; b = 32'hD59F_CB01;
#10;

end

initial begin
$monitor("Selector : %1b%1b%1b\n     A = %32b\n     B = %32b\n\nResult = %32b  Zero Bit : %1b  OverFlow : %1b\n", ALUselector2, ALUselector1, ALUselector0, a, b, result, ZeroBit, V);
end
endmodule