data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v:58: Bit extraction of array[511:0] requires 9 bit index, not 30 bits.\n                                                                                                                                             : ... In instance dmem\n    rd<={RAM[{adr[31:4],2\'b11}],\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v:59: Bit extraction of array[511:0] requires 9 bit index, not 30 bits.\n                                                                                                                                             : ... In instance dmem\n         RAM[{adr[31:4],2\'b10}],\n            ^\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v:60: Bit extraction of array[511:0] requires 9 bit index, not 30 bits.\n                                                                                                                                             : ... In instance dmem\n         RAM[{adr[31:4],2\'b01}],\n            ^\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v:61: Bit extraction of array[511:0] requires 9 bit index, not 30 bits.\n                                                                                                                                             : ... In instance dmem\n         RAM[{adr[31:4],2\'b00}]};\n            ^\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v:66: Bit extraction of array[511:0] requires 9 bit index, not 30 bits.\n                                                                                                                                             : ... In instance dmem\n        {RAM[{adr[31:4],2\'b11}],\n            ^\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v:67: Bit extraction of array[511:0] requires 9 bit index, not 30 bits.\n                                                                                                                                             : ... In instance dmem\n         RAM[{adr[31:4],2\'b10}],\n            ^\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v:68: Bit extraction of array[511:0] requires 9 bit index, not 30 bits.\n                                                                                                                                             : ... In instance dmem\n         RAM[{adr[31:4],2\'b01}],\n            ^\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v:69: Bit extraction of array[511:0] requires 9 bit index, not 30 bits.\n                                                                                                                                             : ... In instance dmem\n         RAM[{adr[31:4],2\'b00}]}<=wd;    \n            ^\n%Error: Exiting due to 8 warning(s)\n'
module dmem(
    input clk,we,reset,
    input [31:0] adr,
    input [127:0] wd,
    output reg [127:0] rd,
    output reg ready,
    input [6:0] SW,
    output reg [31:0] t
    );
    
    reg [31:0] RAM[511:0];
    
    reg [2:0] count;
    reg [31:0] oldadr;
    
    always@(posedge clk)
    if(reset)
    begin count<=3'b0;oldadr=32'b0; end
    else
        if(oldadr==adr)
        begin
            if(count==3'b111) count<=count;
            else count<=count+1;
        end
        else
        begin count<=3'b0;oldadr<=adr; end
    
    always@(posedge clk)
    if(count==3'b111)
        ready<=1'b1;
    else
        ready<=1'b0;
    

    always@(*)
    rd<={RAM[{adr[31:4],2'b11}],
         RAM[{adr[31:4],2'b10}],
         RAM[{adr[31:4],2'b01}],
         RAM[{adr[31:4],2'b00}]};
    

    always@(posedge clk)
    if(we)
        {RAM[{adr[31:4],2'b11}],
         RAM[{adr[31:4],2'b10}],
         RAM[{adr[31:4],2'b01}],
         RAM[{adr[31:4],2'b00}]}<=wd;    


    always@(*)
        t<=RAM[{2'b00,SW}];

    
endmodule
module dmem(
    input clk,we,reset,
    input [31:0] adr,
    input [127:0] wd,
    output reg [127:0] rd,
    output reg ready,
    input [6:0] SW,
    output reg [31:0] t
    );

    
    reg [31:0] RAM[511:0];
    
    reg [2:0] count;
    reg [31:0] oldadr;
    
    always@(posedge clk)
    if(reset)
    begin count<=3'b0;oldadr=32'b0; end
    else
        if(oldadr==adr)
        begin
            if(count==3'b111) count<=count;
            else count<=count+1;
        end
        else
        begin count<=3'b0;oldadr<=adr; end
    
    always@(posedge clk)
    if(count==3'b111)
        ready<=1'b1;
    else
        ready<=1'b0;
    

    always@(*)
    rd<={RAM[{adr[31:4],2'b11}],
         RAM[{adr[31:4],2'b10}],
         RAM[{adr[31:4],2'b01}],
         RAM[{adr[31:4],2'b00}]};
    

    always@(posedge clk)
    if(we)
        {RAM[{adr[31:4],2'b11}],
         RAM[{adr[31:4],2'b10}],
         RAM[{adr[31:4],2'b01}],
         RAM[{adr[31:4],2'b00}]}<=wd;    


    always@(*)
        t<=RAM[{2'b00,SW}];

    
endmodule