data/full_repos/permissive/157049472/Verilog Source Files/RegisterBank.v
1: b'%Error: Cannot find file containing module: Source\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Source\n             data/full_repos/permissive/157049472/Verilog/Source.v\n             data/full_repos/permissive/157049472/Verilog/Source.sv\n             Source\n             Source.v\n             Source.sv\n             obj_dir/Source\n             obj_dir/Source.v\n             obj_dir/Source.sv\n%Error: Cannot find file containing module: Files,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Files/RegisterBank.v\n%Error: Exiting due to 4 error(s)\n'
module RegisterBank(input wire clk,input wire rst,input wire regWriteEnable, input wire [31:0] regWriteData,
						  input wire [4:0] regAddr_1, output wire [31:0] regReadData_1,
						  input wire [4:0] regAddr_2, output wire [31:0] regReadData_2, input wire[4:0] regWriteAddr);
	
	reg [31:0] regArray [31:0];
	integer i; 

	always @ (posedge clk or posedge rst)
	begin
		if(rst)
		begin
			for(i=0;i<32;i=i+1)
				regArray[i] <= 32'd0;
		end
		else
		begin
			if(regWriteEnable) 
			begin
				regArray[regWriteAddr] <= regWriteData;
			end
		end
	end
	assign regReadData_1 = regArray[regAddr_1];
	assign regReadData_2 = regArray[regAddr_2];

endmodule
module RegisterBank(input wire clk,input wire rst,input wire regWriteEnable, input wire [31:0] regWriteData,
						  input wire [4:0] regAddr_1, output wire [31:0] regReadData_1,
						  input wire [4:0] regAddr_2, output wire [31:0] regReadData_2, input wire[4:0] regWriteAddr);

	
	reg [31:0] regArray [31:0];
	integer i; 

	always @ (posedge clk or posedge rst)
	begin
		if(rst)
		begin
			for(i=0;i<32;i=i+1)
				regArray[i] <= 32'd0;
		end
		else
		begin
			if(regWriteEnable) 
			begin
				regArray[regWriteAddr] <= regWriteData;
			end
		end
	end
	assign regReadData_1 = regArray[regAddr_1];
	assign regReadData_2 = regArray[regAddr_2];

endmodule