data/full_repos/permissive/187464337/five_stage_pipelined_computer/pipeline_registers.v
None: at end of input
1: b'%Warning-MULTITOP: data/full_repos/permissive/187464337/five_stage_pipelined_computer/pipeline_registers.v:20: Multiple top level modules\n                                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                             : ... Top module \'if_id_reg\'\nmodule if_id_reg(\n       ^~~~~~~~~\n                                                                                                             : ... Top module \'id_ex_reg\'\nmodule id_ex_reg(\n       ^~~~~~~~~\n                                                                                                             : ... Top module \'ex_mem_reg\'\nmodule ex_mem_reg(\n       ^~~~~~~~~~\n                                                                                                             : ... Top module \'mem_wb_reg\'\nmodule mem_wb_reg(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module id_ex_reg(
   input clk, input resetn, input wreg_in, input m2reg_in, input wmem_in, input jal_in,
   input [3:0] aluc_in, input aluimm_in, input shift_in, input [31:0] pc4_in,
   input [31:0] alu_a_in, input [31:0] alu_b_in, input [31:0] imm_in,
   input [4:0] write_reg_num_in,
   output reg wreg, output reg m2reg, output reg wmem, output reg jal,
   output reg [3:0] aluc, output reg aluimm, output reg shift,
   output reg [31:0] pc4, output reg [31:0] alu_a, output reg [31:0] alu_b,
   output reg [31:0] imm, output reg [4:0] write_reg_num
);
   always @(posedge clk) begin

      if (~resetn) begin
         wreg <= 0;
         m2reg <= 0;
         wmem <= 0;
         jal <= 0;
         aluc <= 0;
         aluimm <= 0;
         shift <= 0;

         pc4 <= 0;
         alu_a <= 0;
         alu_b <= 0;
         imm <= 0;
         write_reg_num <= 0;
      end else begin
         wreg <= wreg_in;
         m2reg <= m2reg_in;
         wmem <= wmem_in;
         jal <= jal_in;
         aluc <= aluc_in;
         aluimm <= aluimm_in;
         shift <= shift_in;

         pc4 <= pc4_in;
         alu_a <= alu_a_in;
         alu_b <= alu_b_in;
         imm <= imm_in;
         write_reg_num <= write_reg_num_in;
      end
   end
endmodule
module id_ex_reg(
   input clk, input resetn, input wreg_in, input m2reg_in, input wmem_in, input jal_in,
   input [3:0] aluc_in, input aluimm_in, input shift_in, input [31:0] pc4_in,
   input [31:0] alu_a_in, input [31:0] alu_b_in, input [31:0] imm_in,
   input [4:0] write_reg_num_in,
   output reg wreg, output reg m2reg, output reg wmem, output reg jal,
   output reg [3:0] aluc, output reg aluimm, output reg shift,
   output reg [31:0] pc4, output reg [31:0] alu_a, output reg [31:0] alu_b,
   output reg [31:0] imm, output reg [4:0] write_reg_num
);

   always @(posedge clk) begin

      if (~resetn) begin
         wreg <= 0;
         m2reg <= 0;
         wmem <= 0;
         jal <= 0;
         aluc <= 0;
         aluimm <= 0;
         shift <= 0;

         pc4 <= 0;
         alu_a <= 0;
         alu_b <= 0;
         imm <= 0;
         write_reg_num <= 0;
      end else begin
         wreg <= wreg_in;
         m2reg <= m2reg_in;
         wmem <= wmem_in;
         jal <= jal_in;
         aluc <= aluc_in;
         aluimm <= aluimm_in;
         shift <= shift_in;

         pc4 <= pc4_in;
         alu_a <= alu_a_in;
         alu_b <= alu_b_in;
         imm <= imm_in;
         write_reg_num <= write_reg_num_in;
      end
   end
endmodule