data/full_repos/permissive/147466718/LC3_RegisterFile.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/a7dcc5fc-19ed-436f-a543-db411d1e1be6.xml
module LC3_RegisterFile(
    input [15:0] data,
    input [2:0] DR,
    input LD,
	 input clk, 
    input [2:0] SR2,
    input [2:0] SR1,
    output reg [15:0] SR2OUT,
    output reg [15:0] SR1OUT
    );

    reg R[7:0] [15:0];
    integer i;
	 
    always @(posedge clk) begin
        if (LD) begin
	    for (i = 0; i < 16; i = i + 1) begin
		    R[DR][i] <= data[i];
	    end
        end
    end
	 
    always @(*) begin
        for (i = 0; i < 16; i = i + 1) begin
            SR1OUT[i] = R[SR1][i];
	    SR2OUT[i] = R[SR2][i];
	end
    end
endmodule
module LC3_RegisterFile(
    input [15:0] data,
    input [2:0] DR,
    input LD,
	 input clk, 
    input [2:0] SR2,
    input [2:0] SR1,
    output reg [15:0] SR2OUT,
    output reg [15:0] SR1OUT
    );


    reg R[7:0] [15:0];
    integer i;
	 
    always @(posedge clk) begin
        if (LD) begin
	    for (i = 0; i < 16; i = i + 1) begin
		    R[DR][i] <= data[i];
	    end
        end
    end
	 
    always @(*) begin
        for (i = 0; i < 16; i = i + 1) begin
            SR1OUT[i] = R[SR1][i];
	    SR2OUT[i] = R[SR2][i];
	end
    end
endmodule