data/full_repos/permissive/155004694/src/control_unit.v
None: at end of input
1: b'%Error: data/full_repos/permissive/155004694/src/control_unit.v:3: Cannot find include file: src/microcode_mod.v\n`include "src/microcode_mod.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155004694/src,data/full_repos/permissive/155004694/src/microcode_mod.v\n             data/full_repos/permissive/155004694/src,data/full_repos/permissive/155004694/src/microcode_mod.v.v\n             data/full_repos/permissive/155004694/src,data/full_repos/permissive/155004694/src/microcode_mod.v.sv\n             src/microcode_mod.v\n             src/microcode_mod.v.v\n             src/microcode_mod.v.sv\n             obj_dir/src/microcode_mod.v\n             obj_dir/src/microcode_mod.v.v\n             obj_dir/src/microcode_mod.v.sv\n%Error: Exiting due to 1 error(s)\n'
module control_unit(
    input clk,
    input reset,

    input [4:0] inst,

    output [CS_N:0] control_signals
    );

    parameter CS_N = 1;

    wire [3:0] opcode;

    reg [3:0] metadata_vec [31:0];

    reg pipeline_state;

    microcode_mod ucode_mod(
        .opcode(opcode),
        .control_signals(control_signals)
    );

    initial $readmemh("src/metadata_vector.txt", metadata_vec);

    initial begin
        pipeline_state = 'd0;
    end

    assign opcode = (pipeline_state == 'd0) ? 'd0 : metadata_vec[inst];

    always @(posedge clk) begin

        if (reset == 'd0) begin
            pipeline_state <= 'd0;
        end else begin
            pipeline_state <= ~pipeline_state;
        end
    end

endmodule
module control_unit(
    input clk,
    input reset,

    input [4:0] inst,

    output [CS_N:0] control_signals
    );


    parameter CS_N = 1;

    wire [3:0] opcode;

    reg [3:0] metadata_vec [31:0];

    reg pipeline_state;

    microcode_mod ucode_mod(
        .opcode(opcode),
        .control_signals(control_signals)
    );

    initial $readmemh("src/metadata_vector.txt", metadata_vec);

    initial begin
        pipeline_state = 'd0;
    end

    assign opcode = (pipeline_state == 'd0) ? 'd0 : metadata_vec[inst];

    always @(posedge clk) begin

        if (reset == 'd0) begin
            pipeline_state <= 'd0;
        end else begin
            pipeline_state <= ~pipeline_state;
        end
    end

endmodule