data/full_repos/permissive/212981921/rtl/srlatch.v
data/verilator_xmls/ed2680c0-7902-4038-bb9e-c0111149fc1e.xml
module srlatch
(
    input wire mclk, _s, _r,
    output wire q,
    output wire _q
);

reg val;
initial val = 1'b0;

always @(posedge mclk) begin
    case({_s, _r})
        {1'b0, 1'b0}: val <= 1'bx;
        {1'b0, 1'b1}: val <= 1'b1;
        {1'b1, 1'b0}: val <= 1'b0;
        {1'b1, 1'b1}: val <= val;
    endcase
end

assign q = val;
assign _q = ~q;

endmodule
module srlatch
(
    input wire mclk, _s, _r,
    output wire q,
    output wire _q
);


reg val;
initial val = 1'b0;

always @(posedge mclk) begin
    case({_s, _r})
        {1'b0, 1'b0}: val <= 1'bx;
        {1'b0, 1'b1}: val <= 1'b1;
        {1'b1, 1'b0}: val <= 1'b0;
        {1'b1, 1'b1}: val <= val;
    endcase
end

assign q = val;
assign _q = ~q;

endmodule