data/full_repos/permissive/168753118/rtl/misc/MUX_B.v
None: at end of input
data/verilator_xmls/0ac6f9bf-0814-4727-88c0-3b28a879b2e5.xml
module MUX_B
  #(parameter DATA_WIDTH = 32) (

    input [1:0] data_sel_in,


    input [DATA_WIDTH-1:0] a_data_src_in,
    input [DATA_WIDTH-1:0] b_data_src_in,
    input [DATA_WIDTH-1:0] c_data_src_in,
    input [DATA_WIDTH-1:0] d_data_src_in,


    output [DATA_WIDTH-1:0] data_out
  );


  reg [DATA_WIDTH-1:0] mux_output_reg;


  always @ ( * )
    begin
      case (data_sel_in)
        2'b00: mux_output_reg = a_data_src_in;
        2'b01: mux_output_reg = b_data_src_in;
        2'b10: mux_output_reg = c_data_src_in;
        2'b11: mux_output_reg = d_data_src_in;
      endcase
    end


  assign data_out = mux_output_reg;

endmodule
module MUX_B
  #(parameter DATA_WIDTH = 32) (

    input [1:0] data_sel_in,


    input [DATA_WIDTH-1:0] a_data_src_in,
    input [DATA_WIDTH-1:0] b_data_src_in,
    input [DATA_WIDTH-1:0] c_data_src_in,
    input [DATA_WIDTH-1:0] d_data_src_in,


    output [DATA_WIDTH-1:0] data_out
  );



  reg [DATA_WIDTH-1:0] mux_output_reg;


  always @ ( * )
    begin
      case (data_sel_in)
        2'b00: mux_output_reg = a_data_src_in;
        2'b01: mux_output_reg = b_data_src_in;
        2'b10: mux_output_reg = c_data_src_in;
        2'b11: mux_output_reg = d_data_src_in;
      endcase
    end


  assign data_out = mux_output_reg;

endmodule