data/full_repos/permissive/121592400/tb_randomGenerator.v
 line:233: before: "$"
1: b'%Error: data/full_repos/permissive/121592400/tb_randomGenerator.v:1: Cannot find include file: randomGenerator.v\n`include "randomGenerator.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/121592400,data/full_repos/permissive/121592400/randomGenerator.v\n             data/full_repos/permissive/121592400,data/full_repos/permissive/121592400/randomGenerator.v.v\n             data/full_repos/permissive/121592400,data/full_repos/permissive/121592400/randomGenerator.v.sv\n             randomGenerator.v\n             randomGenerator.v.v\n             randomGenerator.v.sv\n             obj_dir/randomGenerator.v\n             obj_dir/randomGenerator.v.v\n             obj_dir/randomGenerator.v.sv\n%Error: data/full_repos/permissive/121592400/tb_randomGenerator.v:2: Cannot find include file: memory.v\n`include "memory.v" \n         ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_randomGenerator.v:14: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clock = ~clock;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_randomGenerator.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #15;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_randomGenerator.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #20 nrst = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_randomGenerator.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #20 en_rng = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_randomGenerator.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #20 en_rng = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_randomGenerator.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #100 en_rng = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_randomGenerator.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #20 en_rng = 0;\n        ^\n%Error: data/full_repos/permissive/121592400/tb_randomGenerator.v:29: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_randomGenerator.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/121592400/tb_randomGenerator.v:30: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_randomGenerator);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_randomGenerator.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #500\n        ^\n%Error: Exiting due to 4 error(s), 8 warning(s)\n'
module tb_randomGenerator();
    reg clock, nrst, en_rng;
    wire [15:0] rng_out, rng_out_4bit;
    wire done;

    randomGenerator rng1(clock, nrst, rng_out, rng_out_4bit, en_rng, done);


    initial begin
        clock = 0;
        forever #10 clock = ~clock;
    end


    initial begin
        #15;
        nrst = 0;
        #20 nrst = 1;
        #20 en_rng = 1;
        #20 en_rng = 0;
        #100 en_rng = 1;
        #20 en_rng = 0;
    end

    initial begin
        $dumpfile("tb_randomGenerator.vcd");
        $dumpvars(0, tb_randomGenerator);
        #500
        $finish;
    end
endmodule
module tb_randomGenerator();

    reg clock, nrst, en_rng;
    wire [15:0] rng_out, rng_out_4bit;
    wire done;

    randomGenerator rng1(clock, nrst, rng_out, rng_out_4bit, en_rng, done);


    initial begin
        clock = 0;
        forever #10 clock = ~clock;
    end


    initial begin
        #15;
        nrst = 0;
        #20 nrst = 1;
        #20 en_rng = 1;
        #20 en_rng = 0;
        #100 en_rng = 1;
        #20 en_rng = 0;
    end

    initial begin
        $dumpfile("tb_randomGenerator.vcd");
        $dumpvars(0, tb_randomGenerator);
        #500
        $finish;
    end
endmodule