data/full_repos/permissive/143278/ivltests/br_gh22.v
 line:14: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh22.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b", y);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug();

reg  [1:0] a;
reg  [2:0] b;
wire [3:0] y;

assign y = {a >> {22{b}}, a << (0 <<< b)};

initial begin
  b = 7;
  a = 3;
  #1 $display("%b", y);
  if (y === 4'b0011)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module bug();


reg  [1:0] a;
reg  [2:0] b;
wire [3:0] y;

assign y = {a >> {22{b}}, a << (0 <<< b)};

initial begin
  b = 7;
  a = 3;
  #1 $display("%b", y);
  if (y === 4'b0011)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule