data/full_repos/permissive/183345139/verilog_tutorial/8_Speed_Controller/speed_controller.v
 line:1 column:1: Illegal character '\x00'
1: b"%Error: data/full_repos/permissive/183345139/verilog_tutorial/8_Speed_Controller/speed_controller.v:44: Cannot find file containing module: 'comparator'\ncomparator comp_inst1\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/183345139/verilog_tutorial/8_Speed_Controller,data/full_repos/permissive/183345139/comparator\n             data/full_repos/permissive/183345139/verilog_tutorial/8_Speed_Controller,data/full_repos/permissive/183345139/comparator.v\n             data/full_repos/permissive/183345139/verilog_tutorial/8_Speed_Controller,data/full_repos/permissive/183345139/comparator.sv\n             comparator\n             comparator.v\n             comparator.sv\n             obj_dir/comparator\n             obj_dir/comparator.v\n             obj_dir/comparator.sv\n%Error: data/full_repos/permissive/183345139/verilog_tutorial/8_Speed_Controller/speed_controller.v:58: Cannot find file containing module: 'comparator'\ncomparator comp_inst2\n^~~~~~~~~~\n%Error: data/full_repos/permissive/183345139/verilog_tutorial/8_Speed_Controller/speed_controller.v:71: Cannot find file containing module: 'up_down_counter'\nup_down_counter up_down_counter_inst\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module speed_controller
(
    input wire clk,
    input wire reset,
    input wire en,

    input wire [7:0] actual_speed,
    input wire [7:0] desired_speed,

    input wire [7:0] init_pwm,

    output wire [7:0] pwm_value
);



wire speed_too_slow;
wire speed_too_fast;
wire slowing;
wire speeding_up;

reg [7:0] previous_speed;

wire up = speed_too_slow & ~speeding_up;
wire down = speed_too_fast & ~slowing;

reg [7:0] init_pwm_reg;
reg load;




comparator comp_inst1
(
    .clk(clk),
    .reset(reset),
    .en(en),
    .in1(actual_speed),
    .in2(desired_speed),

    .less_than(speed_too_slow),

    .greater_than(speed_too_fast)
);


comparator comp_inst2
(
    .clk(clk),
    .reset(reset),
    .en(en),
    .in1(actual_speed),
    .in2(previous_speed),

    .less_than(slowing),

    .greater_than(speeding_up)
);

up_down_counter up_down_counter_inst
(
    .clk(clk),
    .reset(reset),
    .en(en),
    .load(load),

    .init_value(init_pwm_reg),
    .up(up),
    .down(down),

    .out_value(pwm_value)
);




always @ (posedge clk)
begin
    if (reset) begin
        previous_speed <= 0;
    end else begin
        if (en) begin
            previous_speed <= actual_speed;
        end
    end
end


always @ (posedge clk)
begin
    if (reset) begin
        init_pwm_reg <= 0;
        load <= 0;
    end else begin
        init_pwm_reg <= init_pwm;
        load <= 0;
        if (init_pwm_reg != init_pwm) begin

            load <= 1;
        end
    end
end


endmodule
module speed_controller
(
    input wire clk,
    input wire reset,
    input wire en,

    input wire [7:0] actual_speed,
    input wire [7:0] desired_speed,

    input wire [7:0] init_pwm,

    output wire [7:0] pwm_value
);




wire speed_too_slow;
wire speed_too_fast;
wire slowing;
wire speeding_up;

reg [7:0] previous_speed;

wire up = speed_too_slow & ~speeding_up;
wire down = speed_too_fast & ~slowing;

reg [7:0] init_pwm_reg;
reg load;




comparator comp_inst1
(
    .clk(clk),
    .reset(reset),
    .en(en),
    .in1(actual_speed),
    .in2(desired_speed),

    .less_than(speed_too_slow),

    .greater_than(speed_too_fast)
);


comparator comp_inst2
(
    .clk(clk),
    .reset(reset),
    .en(en),
    .in1(actual_speed),
    .in2(previous_speed),

    .less_than(slowing),

    .greater_than(speeding_up)
);

up_down_counter up_down_counter_inst
(
    .clk(clk),
    .reset(reset),
    .en(en),
    .load(load),

    .init_value(init_pwm_reg),
    .up(up),
    .down(down),

    .out_value(pwm_value)
);




always @ (posedge clk)
begin
    if (reset) begin
        previous_speed <= 0;
    end else begin
        if (en) begin
            previous_speed <= actual_speed;
        end
    end
end


always @ (posedge clk)
begin
    if (reset) begin
        init_pwm_reg <= 0;
        load <= 0;
    end else begin
        init_pwm_reg <= init_pwm;
        load <= 0;
        if (init_pwm_reg != init_pwm) begin

            load <= 1;
        end
    end
end


endmodule