data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/Crosslink_DualCSI2toRaw10/source/control_capture_lane4_bb.v
data/verilator_xmls/101024fa-9273-4c0d-902d-3ffb3960c302.xml
module control_capture_lane4 #(
		parameter bus_width = 10,
		parameter lane_width = 4,
		parameter format = "RAW10"		
)
(
     input                               rstn    ,
     input                               clk     ,
     input  [8*lane_width-1:0]           din     ,   


     output                              fv      , 
     output                              lv      ,
     output [8*lane_width-1:0]           dout    , 
     output reg [1:0]                    vc      ,
     output reg [5:0]                    dt      ,
     output reg [15:0]                   wc      ,
     output reg [7:0]                    ecc     ,
	 output reg                          error   ,
	 output dt_correct,
	 output wc_correct,
	 input                               line_length_detect,
	 input  [15:0]                       line_length
);

endmodule
module control_capture_lane4 #(
		parameter bus_width = 10,
		parameter lane_width = 4,
		parameter format = "RAW10"		
)
(
     input                               rstn    ,
     input                               clk     ,
     input  [8*lane_width-1:0]           din     ,   


     output                              fv      , 
     output                              lv      ,
     output [8*lane_width-1:0]           dout    , 
     output reg [1:0]                    vc      ,
     output reg [5:0]                    dt      ,
     output reg [15:0]                   wc      ,
     output reg [7:0]                    ecc     ,
	 output reg                          error   ,
	 output dt_correct,
	 output wc_correct,
	 input                               line_length_detect,
	 input  [15:0]                       line_length
);


endmodule