data/full_repos/permissive/143278/ivltests/port-test6.v
 line:62: before: "nput"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test6.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("has_ports (%b, %b, %b)", res, a, b);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test6.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("has_ports (%b, %b, %b)", res, a, b);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test6.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("has_ports (%b, %b, %b)", res, a, b);\n      ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module has_ports (output reg [8:0] o,
		  input wire [7:0] a,
		  input wire [7:0] b);

   always @* o <= a + b;

endmodule
module has_ports (output reg [8:0] o,
		  input wire [7:0] a,
		  input wire [7:0] b);


   always @* o <= a + b;

endmodule