data/full_repos/permissive/201488448/1_verilog/01_wire.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/2232b30f-2f49-4596-bbf9-f188f6b97f40.xml
module top_module( input in, output out );
	
	assign out = in;
	
endmodule
module top_module( input in, output out );

	
	assign out = in;
	
endmodule