data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Division/Div_Radix4_tb.v
 line:50: before: "integer"
1: b'%Error: Cannot find file containing module: Project/SourceCode/Division,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Division,data/full_repos/permissive/119107706\n             Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Division/Div_Radix4_tb.v\n%Error: Exiting due to 3 error(s)\n'
module Div_Radix4_tb;


	parameter WL = 24;
	parameter WF = 23;
	parameter RADIX = 4;
	parameter N = 12;
	parameter LUT_size = 8;
	parameter LUT_bits = 7;
	parameter LUT_addWidth = RADIX;


	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din_x;
	reg [WL-1:0] din_d;


	wire [WL-1:0] dout;

	real real_din_x, real_din_d, real_dout;


	function integer log2;
		input integer n;
		begin
			log2 = 0;
			while (2**log2<n) begin
				log2 = log2 + 1;
			end
		end
	endfunction



	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction



	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;



	Div_Radix4
	#(
		.WL(WL),
		.WF(WF),
		.RADIX(RADIX),
		.N(N),
		.LUT_size(LUT_size),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
	)
	Fang_Div_Radix4
	(
		.CLK(CLK),
		.nRST(nRST),
		.CE(CE),
		.din_x(din_x), 								
		.din_d(din_d), 								
		.dout(dout)
	);

	integer count;

	initial begin

		$readmemb("LUT_Radix_4_m2.txt", Div_Radix4_tb.Fang_Div_Radix4.LUT_m2);
		$readmemb("LUT_Radix_4_m1.txt", Div_Radix4_tb.Fang_Div_Radix4.LUT_m1);
		$readmemb("LUT_Radix_4_m0.txt", Div_Radix4_tb.Fang_Div_Radix4.LUT_m0);
		$readmemb("LUT_Radix_4_mm1.txt", Div_Radix4_tb.Fang_Div_Radix4.LUT_mm1);
		

		nRST = 0; @(posedge CLK);
		CE = 1; nRST = 1;
		din_x = 24'b0011_0011_0011_0011_0011_0011;
		din_d = 24'b0101_1001_1001_1001_1001_1001;
		for (count = 0; count <= WL/log2(RADIX)-1; count = count+1) begin		
			@(posedge CLK);
		end
		din_x = 24'b0001_0011_0011_0011_0011_0011;
		din_d = 24'b0101_1000_0101_0001_1110_1011;
		for (count = 0; count <= WL/log2(RADIX)-1; count = count+1) begin		
			@(posedge CLK);
		end
		din_x = 24'b0101_1110_1011_1000_0101_0001;
		din_d = 24'b0111_1110_1011_1000_0101_0001;
		for (count = 0; count <= WL/log2(RADIX)-1; count = count+1) begin		
			@(posedge CLK);
		end

		@(posedge CLK); @(posedge CLK); @(posedge CLK); $finish; 
        


	end


	always @ din_x real_din_x = unsigned_fixedToFloat(din_x, 1, WL-1);
	always @ din_d real_din_d = unsigned_fixedToFloat(din_d, 1, WL-1);


	always @ dout real_dout = unsigned_fixedToFloat(dout, 1, WL-1);
      
endmodule
module Div_Radix4_tb;



	parameter WL = 24;
	parameter WF = 23;
	parameter RADIX = 4;
	parameter N = 12;
	parameter LUT_size = 8;
	parameter LUT_bits = 7;
	parameter LUT_addWidth = RADIX;


	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din_x;
	reg [WL-1:0] din_d;


	wire [WL-1:0] dout;

	real real_din_x, real_din_d, real_dout;


	function integer log2;
		input integer n;
		begin
			log2 = 0;
			while (2**log2<n) begin
				log2 = log2 + 1;
			end
		end
	endfunction



	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction



	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;



	Div_Radix4
	#(
		.WL(WL),
		.WF(WF),
		.RADIX(RADIX),
		.N(N),
		.LUT_size(LUT_size),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
	)
	Fang_Div_Radix4
	(
		.CLK(CLK),
		.nRST(nRST),
		.CE(CE),
		.din_x(din_x), 								
		.din_d(din_d), 								
		.dout(dout)
	);

	integer count;

	initial begin

		$readmemb("LUT_Radix_4_m2.txt", Div_Radix4_tb.Fang_Div_Radix4.LUT_m2);
		$readmemb("LUT_Radix_4_m1.txt", Div_Radix4_tb.Fang_Div_Radix4.LUT_m1);
		$readmemb("LUT_Radix_4_m0.txt", Div_Radix4_tb.Fang_Div_Radix4.LUT_m0);
		$readmemb("LUT_Radix_4_mm1.txt", Div_Radix4_tb.Fang_Div_Radix4.LUT_mm1);
		

		nRST = 0; @(posedge CLK);
		CE = 1; nRST = 1;
		din_x = 24'b0011_0011_0011_0011_0011_0011;
		din_d = 24'b0101_1001_1001_1001_1001_1001;
		for (count = 0; count <= WL/log2(RADIX)-1; count = count+1) begin		
			@(posedge CLK);
		end
		din_x = 24'b0001_0011_0011_0011_0011_0011;
		din_d = 24'b0101_1000_0101_0001_1110_1011;
		for (count = 0; count <= WL/log2(RADIX)-1; count = count+1) begin		
			@(posedge CLK);
		end
		din_x = 24'b0101_1110_1011_1000_0101_0001;
		din_d = 24'b0111_1110_1011_1000_0101_0001;
		for (count = 0; count <= WL/log2(RADIX)-1; count = count+1) begin		
			@(posedge CLK);
		end

		@(posedge CLK); @(posedge CLK); @(posedge CLK); $finish; 
        


	end


	always @ din_x real_din_x = unsigned_fixedToFloat(din_x, 1, WL-1);
	always @ din_d real_din_d = unsigned_fixedToFloat(din_d, 1, WL-1);


	always @ dout real_dout = unsigned_fixedToFloat(dout, 1, WL-1);
      
endmodule