data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/milliSecondCounter.v
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/milliSecondCounter.v\n%Error: Exiting due to 4 error(s)\n'
module milliSecondCounter(
	input clock,
	input reset,
	input [15:0] toCount,
	output reg countRdy
    );
	 

	parameter idle 				= 0;
	parameter latchData			= 1;
	parameter startCount			= 2;
	parameter countingState 	= 3;
	parameter displayState 		= 4;

	reg[2:0] NS 					= 0;
	reg[2:0] PS 					= 0;
	reg[31:0] count 				= 0;
	 

	always@(posedge clock)
	begin

		if(reset)
			PS 	<= idle;
		else
			PS 	<= NS;
	end
	
	

	
	always@(*)
	begin
		NS <= 0;
		case(PS)
		

			idle				:	NS <= (toCount != 0)			? 	latchData		:	idle;
			
			latchData		: NS <=  startCount;

			startCount		:	NS <= countingState;
			

			countingState	:	NS	<=	(count 	<=	 1)		?	displayState	:	countingState;

			displayState	:	NS	<=	(toCount	!= 0)			?	startCount			:	displayState;
			default			:	NS <= idle;
		endcase
	
	end
	



	

	always@(posedge clock)
	begin
		if (reset)
			begin
				count 	<= 0;
				countRdy <= 0;
			end	
		else
		begin	
			countRdy	<=	0;
			case(PS)
				idle				:	begin	

											count 	<= 0;
											countRdy <= 0;
											count <= toCount;
										end
				latchData		: 	begin

											countRdy <=0;
											if(toCount > 0)
												count <= toCount;
											
										end	
				startCount		:	begin
														




											count 	<= count * 50000 - 3;
											countRdy <= 0;
										end
				countingState	:	begin

											count 	<= count - 1;
											countRdy <= 0;
										end
				displayState	:	begin


											count 	<= toCount;
											countRdy <= 1;
										end
				default			:	begin
											count 	<= 0;
											countRdy <= 0;
										end
			endcase
		end
	end
	 
	 
	 


endmodule
module milliSecondCounter(
	input clock,
	input reset,
	input [15:0] toCount,
	output reg countRdy
    );

	 

	parameter idle 				= 0;
	parameter latchData			= 1;
	parameter startCount			= 2;
	parameter countingState 	= 3;
	parameter displayState 		= 4;

	reg[2:0] NS 					= 0;
	reg[2:0] PS 					= 0;
	reg[31:0] count 				= 0;
	 

	always@(posedge clock)
	begin

		if(reset)
			PS 	<= idle;
		else
			PS 	<= NS;
	end
	
	

	
	always@(*)
	begin
		NS <= 0;
		case(PS)
		

			idle				:	NS <= (toCount != 0)			? 	latchData		:	idle;
			
			latchData		: NS <=  startCount;

			startCount		:	NS <= countingState;
			

			countingState	:	NS	<=	(count 	<=	 1)		?	displayState	:	countingState;

			displayState	:	NS	<=	(toCount	!= 0)			?	startCount			:	displayState;
			default			:	NS <= idle;
		endcase
	
	end
	



	

	always@(posedge clock)
	begin
		if (reset)
			begin
				count 	<= 0;
				countRdy <= 0;
			end	
		else
		begin	
			countRdy	<=	0;
			case(PS)
				idle				:	begin	

											count 	<= 0;
											countRdy <= 0;
											count <= toCount;
										end
				latchData		: 	begin

											countRdy <=0;
											if(toCount > 0)
												count <= toCount;
											
										end	
				startCount		:	begin
														




											count 	<= count * 50000 - 3;
											countRdy <= 0;
										end
				countingState	:	begin

											count 	<= count - 1;
											countRdy <= 0;
										end
				displayState	:	begin


											count 	<= toCount;
											countRdy <= 1;
										end
				default			:	begin
											count 	<= 0;
											countRdy <= 0;
										end
			endcase
		end
	end
	 
	 
	 


endmodule