data/full_repos/permissive/143278/ivltests/dotinid.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dotinid.v:33: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module a;
   wire \a.b ;
   m    \c.d (\a.b );
   initial
     begin
	\c.d . \y.z  <= 1'b1;
	#1;
	if (\a.b  === 1'b1)
	  $display("PASSED");
	else
	  $display("FAILED");
     end
endmodule
module a;

   wire \a.b ;
   m    \c.d (\a.b );
   initial
     begin
	\c.d . \y.z  <= 1'b1;
	#1;
	if (\a.b  === 1'b1)
	  $display("PASSED");
	else
	  $display("FAILED");
     end
endmodule