data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v
1: b'%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:45: Cannot find include file: openMSP430_defines.v\n`include "openMSP430_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/openMSP430_defines.v\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/openMSP430_defines.v.v\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/openMSP430_defines.v.sv\n             openMSP430_defines.v\n             openMSP430_defines.v.v\n             openMSP430_defines.v.sv\n             obj_dir/openMSP430_defines.v\n             obj_dir/openMSP430_defines.v.v\n             obj_dir/openMSP430_defines.v.sv\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:297: Cannot find include file: openMSP430_undefines.v\n`include "openMSP430_undefines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:167: Define or directive not defined: \'`DBG_UART_WR\'\n                                (xfer_buf_nxt[`DBG_UART_WR]  ?\n                                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:167: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                                (xfer_buf_nxt[`DBG_UART_WR]  ?\n                                                          ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:168: Define or directive not defined: \'`DBG_UART_BW\'\n                                (xfer_buf_nxt[`DBG_UART_BW]  ? RX_DATA2 : RX_DATA1) :\n                                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:169: Define or directive not defined: \'`DBG_UART_BW\'\n                                (xfer_buf_nxt[`DBG_UART_BW]  ? TX_DATA2 : TX_DATA1));\n                                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:219: Define or directive not defined: \'`DBG_UART_XFER_CNT_W\'\nwire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;\n      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:219: Define or directive not defined: \'`DBG_UART_CNT\'\nwire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;\n                                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:219: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nwire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;\n                                                           ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:230: Define or directive not defined: \'`DBG_UART_XFER_CNT_W\'\nreg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;\n     ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:234: Define or directive not defined: \'`DBG_UART_XFER_CNT_W\'\nwire       xfer_bit_inc = (xfer_bit!=4\'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1\'b0}});\n                                                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:244: Define or directive not defined: \'`DBG_UART_XFER_CNT_W\'\n  if (dbg_rst)                       xfer_cnt <=  {`DBG_UART_XFER_CNT_W{1\'b0}};\n                                                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:245: Define or directive not defined: \'`DBG_UART_XFER_CNT_W\'\n  else if (rx_active & rxd_edge)     xfer_cnt <=  {1\'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};\n                                                                     ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:247: Define or directive not defined: \'`DBG_UART_XFER_CNT_W\'\n  else if (|xfer_cnt)                xfer_cnt <=  xfer_cnt+{`DBG_UART_XFER_CNT_W{1\'b1}};\n                                                            ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:276: Define or directive not defined: \'`DBG_UART_ADDR\'\n  else if (cmd_valid) dbg_addr <=  xfer_buf_nxt[`DBG_UART_ADDR];\n                                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:276: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  else if (cmd_valid) dbg_addr <=  xfer_buf_nxt[`DBG_UART_ADDR];\n                                                              ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:281: Define or directive not defined: \'`DBG_UART_BW\'\n  else if (cmd_valid) dbg_bw   <=  xfer_buf_nxt[`DBG_UART_BW];\n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:281: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  else if (cmd_valid) dbg_bw   <=  xfer_buf_nxt[`DBG_UART_BW];\n                                                            ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:289: Define or directive not defined: \'`DBG_UART_WR\'\n                                     (cmd_valid & ~xfer_buf_nxt[`DBG_UART_WR]) | mem_burst_rd;\n                                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_dbg_uart.v:289: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                                     (cmd_valid & ~xfer_buf_nxt[`DBG_UART_WR]) | mem_burst_rd;\n                                                                            ^\n%Error: Exiting due to 20 error(s)\n'
module  omsp_dbg_uart (


    dbg_addr,
    dbg_din,
    dbg_rd,
    dbg_uart_txd,
    dbg_wr,


    dbg_clk,
    dbg_dout,
    dbg_rd_rdy,
    dbg_rst,
    dbg_uart_rxd,
    mem_burst,
    mem_burst_end,
    mem_burst_rd,
    mem_burst_wr,
    mem_bw
);



output        [5:0] dbg_addr;
output       [15:0] dbg_din;
output              dbg_rd;
output              dbg_uart_txd;
output              dbg_wr;



input               dbg_clk;
input        [15:0] dbg_dout;
input               dbg_rd_rdy;
input               dbg_rst;
input               dbg_uart_rxd;
input               mem_burst;
input               mem_burst_end;
input               mem_burst_rd;
input               mem_burst_wr;
input               mem_bw;








`ifdef SYNC_DBG_UART_RXD

    wire uart_rxd_n;

    omsp_sync_cell sync_cell_uart_rxd (
        .data_out  (uart_rxd_n),
        .data_in   (~dbg_uart_rxd),
        .clk       (dbg_clk),
        .rst       (dbg_rst)
    );
    wire uart_rxd = ~uart_rxd_n;
`else
    wire uart_rxd = dbg_uart_rxd;
`endif



reg  [1:0] rxd_buf;
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst) rxd_buf <=  2'h3;
  else         rxd_buf <=  {rxd_buf[0], uart_rxd};



reg        rxd_maj;

wire       rxd_maj_nxt = (uart_rxd   & rxd_buf[0]) |
                         (uart_rxd   & rxd_buf[1]) |
                         (rxd_buf[0] & rxd_buf[1]);

always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst) rxd_maj <=  1'b1;
  else         rxd_maj <=  rxd_maj_nxt;

wire rxd_s    =  rxd_maj;
wire rxd_fe   =  rxd_maj & ~rxd_maj_nxt;
wire rxd_re   = ~rxd_maj &  rxd_maj_nxt;
wire rxd_edge =  rxd_maj ^  rxd_maj_nxt;







reg   [2:0] uart_state;
reg   [2:0] uart_state_nxt;

wire        sync_done;
wire        xfer_done;
reg  [19:0] xfer_buf;
wire [19:0] xfer_buf_nxt;


parameter  RX_SYNC  = 3'h0;
parameter  RX_CMD   = 3'h1;
parameter  RX_DATA1 = 3'h2;
parameter  RX_DATA2 = 3'h3;
parameter  TX_DATA1 = 3'h4;
parameter  TX_DATA2 = 3'h5;


always @(uart_state or xfer_buf_nxt or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
  case (uart_state)
    RX_SYNC  : uart_state_nxt =  RX_CMD;
    RX_CMD   : uart_state_nxt =  mem_burst_wr                ?
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
                                 mem_burst_rd                ?
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
                                (xfer_buf_nxt[`DBG_UART_WR]  ?
                                (xfer_buf_nxt[`DBG_UART_BW]  ? RX_DATA2 : RX_DATA1) :
                                (xfer_buf_nxt[`DBG_UART_BW]  ? TX_DATA2 : TX_DATA1));
    RX_DATA1 : uart_state_nxt =  RX_DATA2;
    RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
                                 RX_CMD;
    TX_DATA1 : uart_state_nxt =  TX_DATA2;
    TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
                                 RX_CMD;

    default  : uart_state_nxt =  RX_CMD;

  endcase


always @(posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                          uart_state <= RX_SYNC;
  else if (xfer_done    | sync_done |
           mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;


wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
wire rx_active = (uart_state==RX_DATA1) | (uart_state==RX_DATA2) | (uart_state==RX_CMD);
wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);









reg        sync_busy;
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                             sync_busy <=  1'b0;
  else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <=  1'b1;
  else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <=  1'b0;

assign sync_done =  (uart_state==RX_SYNC) & rxd_re & sync_busy;

`ifdef DBG_UART_AUTO_SYNC

reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                                     sync_cnt <=  {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
  else if (sync_busy | (~sync_busy & sync_cnt[2])) sync_cnt <=  sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};

wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
`else
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
`endif








reg                      [3:0] xfer_bit;
reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;

wire       txd_start    = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
wire       rxd_start    = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
wire       xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
assign     xfer_done    = rx_active ? (xfer_bit==4'ha) : (xfer_bit==4'hb);

always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                       xfer_bit <=  4'h0;
  else if (txd_start | rxd_start)    xfer_bit <=  4'h1;
  else if (xfer_done)                xfer_bit <=  4'h0;
  else if (xfer_bit_inc)             xfer_bit <=  xfer_bit+4'h1;

always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                       xfer_cnt <=  {`DBG_UART_XFER_CNT_W{1'b0}};
  else if (rx_active & rxd_edge)     xfer_cnt <=  {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
  else if (txd_start | xfer_bit_inc) xfer_cnt <=  bit_cnt_max;
  else if (|xfer_cnt)                xfer_cnt <=  xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};




assign xfer_buf_nxt =  {rxd_s, xfer_buf[19:1]};

always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)           xfer_buf <=  20'h00000;
  else if (dbg_rd_rdy)   xfer_buf <=  {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
  else if (xfer_bit_inc) xfer_buf <=  xfer_buf_nxt;




reg dbg_uart_txd;

always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                       dbg_uart_txd <=  1'b1;
  else if (xfer_bit_inc & tx_active) dbg_uart_txd <=  xfer_buf[0];






reg [5:0] dbg_addr;
 always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)        dbg_addr <=  6'h00;
  else if (cmd_valid) dbg_addr <=  xfer_buf_nxt[`DBG_UART_ADDR];

reg       dbg_bw;
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)        dbg_bw   <=  1'b0;
  else if (cmd_valid) dbg_bw   <=  xfer_buf_nxt[`DBG_UART_BW];

wire        dbg_din_bw =  mem_burst  ? mem_bw : dbg_bw;

wire [15:0] dbg_din    =  dbg_din_bw ? {8'h00,           xfer_buf_nxt[18:11]} :
                                       {xfer_buf_nxt[18:11], xfer_buf_nxt[9:2]};
wire        dbg_wr     = (xfer_done & (uart_state==RX_DATA2));
wire        dbg_rd     = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
                                     (cmd_valid & ~xfer_buf_nxt[`DBG_UART_WR]) | mem_burst_rd;



endmodule
module  omsp_dbg_uart (


    dbg_addr,
    dbg_din,
    dbg_rd,
    dbg_uart_txd,
    dbg_wr,


    dbg_clk,
    dbg_dout,
    dbg_rd_rdy,
    dbg_rst,
    dbg_uart_rxd,
    mem_burst,
    mem_burst_end,
    mem_burst_rd,
    mem_burst_wr,
    mem_bw
);




output        [5:0] dbg_addr;
output       [15:0] dbg_din;
output              dbg_rd;
output              dbg_uart_txd;
output              dbg_wr;



input               dbg_clk;
input        [15:0] dbg_dout;
input               dbg_rd_rdy;
input               dbg_rst;
input               dbg_uart_rxd;
input               mem_burst;
input               mem_burst_end;
input               mem_burst_rd;
input               mem_burst_wr;
input               mem_bw;








`ifdef SYNC_DBG_UART_RXD

    wire uart_rxd_n;

    omsp_sync_cell sync_cell_uart_rxd (
        .data_out  (uart_rxd_n),
        .data_in   (~dbg_uart_rxd),
        .clk       (dbg_clk),
        .rst       (dbg_rst)
    );
    wire uart_rxd = ~uart_rxd_n;
`else
    wire uart_rxd = dbg_uart_rxd;
`endif



reg  [1:0] rxd_buf;
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst) rxd_buf <=  2'h3;
  else         rxd_buf <=  {rxd_buf[0], uart_rxd};



reg        rxd_maj;

wire       rxd_maj_nxt = (uart_rxd   & rxd_buf[0]) |
                         (uart_rxd   & rxd_buf[1]) |
                         (rxd_buf[0] & rxd_buf[1]);

always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst) rxd_maj <=  1'b1;
  else         rxd_maj <=  rxd_maj_nxt;

wire rxd_s    =  rxd_maj;
wire rxd_fe   =  rxd_maj & ~rxd_maj_nxt;
wire rxd_re   = ~rxd_maj &  rxd_maj_nxt;
wire rxd_edge =  rxd_maj ^  rxd_maj_nxt;







reg   [2:0] uart_state;
reg   [2:0] uart_state_nxt;

wire        sync_done;
wire        xfer_done;
reg  [19:0] xfer_buf;
wire [19:0] xfer_buf_nxt;


parameter  RX_SYNC  = 3'h0;
parameter  RX_CMD   = 3'h1;
parameter  RX_DATA1 = 3'h2;
parameter  RX_DATA2 = 3'h3;
parameter  TX_DATA1 = 3'h4;
parameter  TX_DATA2 = 3'h5;


always @(uart_state or xfer_buf_nxt or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
  case (uart_state)
    RX_SYNC  : uart_state_nxt =  RX_CMD;
    RX_CMD   : uart_state_nxt =  mem_burst_wr                ?
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
                                 mem_burst_rd                ?
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
                                (xfer_buf_nxt[`DBG_UART_WR]  ?
                                (xfer_buf_nxt[`DBG_UART_BW]  ? RX_DATA2 : RX_DATA1) :
                                (xfer_buf_nxt[`DBG_UART_BW]  ? TX_DATA2 : TX_DATA1));
    RX_DATA1 : uart_state_nxt =  RX_DATA2;
    RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
                                 RX_CMD;
    TX_DATA1 : uart_state_nxt =  TX_DATA2;
    TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
                                 RX_CMD;

    default  : uart_state_nxt =  RX_CMD;

  endcase


always @(posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                          uart_state <= RX_SYNC;
  else if (xfer_done    | sync_done |
           mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;


wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
wire rx_active = (uart_state==RX_DATA1) | (uart_state==RX_DATA2) | (uart_state==RX_CMD);
wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);









reg        sync_busy;
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                             sync_busy <=  1'b0;
  else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <=  1'b1;
  else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <=  1'b0;

assign sync_done =  (uart_state==RX_SYNC) & rxd_re & sync_busy;

`ifdef DBG_UART_AUTO_SYNC

reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                                     sync_cnt <=  {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
  else if (sync_busy | (~sync_busy & sync_cnt[2])) sync_cnt <=  sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};

wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
`else
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
`endif








reg                      [3:0] xfer_bit;
reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;

wire       txd_start    = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
wire       rxd_start    = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
wire       xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
assign     xfer_done    = rx_active ? (xfer_bit==4'ha) : (xfer_bit==4'hb);

always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                       xfer_bit <=  4'h0;
  else if (txd_start | rxd_start)    xfer_bit <=  4'h1;
  else if (xfer_done)                xfer_bit <=  4'h0;
  else if (xfer_bit_inc)             xfer_bit <=  xfer_bit+4'h1;

always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                       xfer_cnt <=  {`DBG_UART_XFER_CNT_W{1'b0}};
  else if (rx_active & rxd_edge)     xfer_cnt <=  {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
  else if (txd_start | xfer_bit_inc) xfer_cnt <=  bit_cnt_max;
  else if (|xfer_cnt)                xfer_cnt <=  xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};




assign xfer_buf_nxt =  {rxd_s, xfer_buf[19:1]};

always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)           xfer_buf <=  20'h00000;
  else if (dbg_rd_rdy)   xfer_buf <=  {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
  else if (xfer_bit_inc) xfer_buf <=  xfer_buf_nxt;




reg dbg_uart_txd;

always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                       dbg_uart_txd <=  1'b1;
  else if (xfer_bit_inc & tx_active) dbg_uart_txd <=  xfer_buf[0];






reg [5:0] dbg_addr;
 always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)        dbg_addr <=  6'h00;
  else if (cmd_valid) dbg_addr <=  xfer_buf_nxt[`DBG_UART_ADDR];

reg       dbg_bw;
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)        dbg_bw   <=  1'b0;
  else if (cmd_valid) dbg_bw   <=  xfer_buf_nxt[`DBG_UART_BW];

wire        dbg_din_bw =  mem_burst  ? mem_bw : dbg_bw;

wire [15:0] dbg_din    =  dbg_din_bw ? {8'h00,           xfer_buf_nxt[18:11]} :
                                       {xfer_buf_nxt[18:11], xfer_buf_nxt[9:2]};
wire        dbg_wr     = (xfer_done & (uart_state==RX_DATA2));
wire        dbg_rd     = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
                                     (cmd_valid & ~xfer_buf_nxt[`DBG_UART_WR]) | mem_burst_rd;



endmodule