data/full_repos/permissive/178601407/common-modules/divider.sv
Syntax Error
data/verilator_xmls/8de4ed59-8bf2-4099-9c99-8d648369549a.xml
module divider #(parameter COUNT = 3300000)
(input logic clk, input logic input_clk, output logic output_clk);
logic [$clog2(COUNT):0] counter = 0;
initial output_clk = 0;

always_ff @(posedge clk)
begin
	if (input_clk == 1'b1)
	begin
		if (counter != COUNT)
		begin
			counter++;
			output_clk <= 1'b0;
		end
		else
		begin
			counter <= 0;
			output_clk <= 1'b1;
		end
	end
	else
		output_clk <= output_clk;
end
endmodule
module divider #(parameter COUNT = 3300000)
(input logic clk, input logic input_clk, output logic output_clk);

logic [$clog2(COUNT):0] counter = 0;
initial output_clk = 0;

always_ff @(posedge clk)
begin
	if (input_clk == 1'b1)
	begin
		if (counter != COUNT)
		begin
			counter++;
			output_clk <= 1'b0;
		end
		else
		begin
			counter <= 0;
			output_clk <= 1'b1;
		end
	end
	else
		output_clk <= output_clk;
end
endmodule