data/full_repos/permissive/194847941/demo/7_uart_rd_ram/al_ip/Double_RAM_uut_sim.v
1: b"%Error: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/al_ip/Double_RAM_uut_sim.v:25: Cannot find file containing module: 'EG_PHY_CONFIG'\n  EG_PHY_CONFIG #(\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/7_uart_rd_ram/al_ip,data/full_repos/permissive/194847941/EG_PHY_CONFIG\n             data/full_repos/permissive/194847941/demo/7_uart_rd_ram/al_ip,data/full_repos/permissive/194847941/EG_PHY_CONFIG.v\n             data/full_repos/permissive/194847941/demo/7_uart_rd_ram/al_ip,data/full_repos/permissive/194847941/EG_PHY_CONFIG.sv\n             EG_PHY_CONFIG\n             EG_PHY_CONFIG.v\n             EG_PHY_CONFIG.sv\n             obj_dir/EG_PHY_CONFIG\n             obj_dir/EG_PHY_CONFIG.v\n             obj_dir/EG_PHY_CONFIG.sv\n%Error: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/al_ip/Double_RAM_uut_sim.v:32: Cannot find file containing module: 'EG_PHY_BRAM'\n  EG_PHY_BRAM #(\n  ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Double_RAM_uut
  (
  addra,
  addrb,
  ceb,
  clka,
  clkb,
  dia,
  dob
  );

  input [7:0] addra;
  input [7:0] addrb;
  input ceb;
  input clka;
  input clkb;
  input [7:0] dia;
  output [7:0] dob;


  EG_PHY_CONFIG #(
    .DONE_PERSISTN("ENABLE"),
    .INIT_PERSISTN("ENABLE"),
    .JTAG_PERSISTN("DISABLE"),
    .PROGRAMN_PERSISTN("DISABLE"))
    config_inst ();

  EG_PHY_BRAM #(
    .CEAMUX("1"),
    .CSA0("1"),
    .CSA1("1"),
    .CSA2("1"),
    .CSB0("1"),
    .CSB1("1"),
    .CSB2("1"),
    .DATA_WIDTH_A("9"),
    .DATA_WIDTH_B("9"),
    .MODE("DP8K"),
    .OCEAMUX("0"),
    .OCEBMUX("0"),
    .REGMODE_A("NOREG"),
    .REGMODE_B("NOREG"),
    .RESETMODE("SYNC"),
    .RSTAMUX("0"),
    .RSTBMUX("0"),
    .WEAMUX("1"),
    .WEBMUX("0"),
    .WRITEMODE_A("NORMAL"),
    .WRITEMODE_B("NORMAL"))
    inst_256x8_sub_000000_000 (
    .addra({2'b00,addra,3'b111}),
    .addrb({2'b00,addrb,3'b111}),
    .ceb(ceb),
    .clka(clka),
    .clkb(clkb),
    .dia({open_n54,dia}),
    .dob({open_n79,dob}));

endmodule
module Double_RAM_uut
  (
  addra,
  addrb,
  ceb,
  clka,
  clkb,
  dia,
  dob
  );


  input [7:0] addra;
  input [7:0] addrb;
  input ceb;
  input clka;
  input clkb;
  input [7:0] dia;
  output [7:0] dob;


  EG_PHY_CONFIG #(
    .DONE_PERSISTN("ENABLE"),
    .INIT_PERSISTN("ENABLE"),
    .JTAG_PERSISTN("DISABLE"),
    .PROGRAMN_PERSISTN("DISABLE"))
    config_inst ();

  EG_PHY_BRAM #(
    .CEAMUX("1"),
    .CSA0("1"),
    .CSA1("1"),
    .CSA2("1"),
    .CSB0("1"),
    .CSB1("1"),
    .CSB2("1"),
    .DATA_WIDTH_A("9"),
    .DATA_WIDTH_B("9"),
    .MODE("DP8K"),
    .OCEAMUX("0"),
    .OCEBMUX("0"),
    .REGMODE_A("NOREG"),
    .REGMODE_B("NOREG"),
    .RESETMODE("SYNC"),
    .RSTAMUX("0"),
    .RSTBMUX("0"),
    .WEAMUX("1"),
    .WEBMUX("0"),
    .WRITEMODE_A("NORMAL"),
    .WRITEMODE_B("NORMAL"))
    inst_256x8_sub_000000_000 (
    .addra({2'b00,addra,3'b111}),
    .addrb({2'b00,addrb,3'b111}),
    .ceb(ceb),
    .clka(clka),
    .clkb(clkb),
    .dia({open_n54,dia}),
    .dob({open_n79,dob}));

endmodule