data/full_repos/permissive/170402453/Average8_14Bit.v
 line:42: before: "("
1: b'%Error: data/full_repos/permissive/170402453/Average8_14Bit.v:36: syntax error, unexpected new, expecting IDENTIFIER or do or final\n  wire new;  \n          ^\n%Error: Exiting due to 1 error(s)\n'
module Average8_14Bit(
	 input CLK,
    input [13:0] DATA_IN,
    output [13:0] AVG_OUT
    );
	 
	 reg [13:0] AVGMem [0:7];
	 reg [2:0] AVGIndex;
	 reg [23:0] AVGAccumulator;
	 reg [2:0] i;
	 
	 reg OUT_;
	 assign AVG_OUT=OUT_;
	 
	 wire new;
	 
	 initial begin
		AVGIndex = 0;
		AVGAccumulator = 0;
		i=0;
		repeat(8) begin
			AVGAccumulator = 0;
			i=i+1;
		end
	 end
	 

	 always @(posedge CLK) begin
		AVGMem[AVGIndex] = DATA_IN;
		AVGIndex = AVGIndex+1;
		


		i=0;
		repeat(8) begin
			AVGAccumulator = AVGAccumulator + AVGMem[i];
			i=i+1;
		end
		OUT_ = AVGAccumulator >> 3;
	 end

endmodule
module Average8_14Bit(
	 input CLK,
    input [13:0] DATA_IN,
    output [13:0] AVG_OUT
    );

	 
	 reg [13:0] AVGMem [0:7];
	 reg [2:0] AVGIndex;
	 reg [23:0] AVGAccumulator;
	 reg [2:0] i;
	 
	 reg OUT_;
	 assign AVG_OUT=OUT_;
	 
	 wire new;
	 
	 initial begin
		AVGIndex = 0;
		AVGAccumulator = 0;
		i=0;
		repeat(8) begin
			AVGAccumulator = 0;
			i=i+1;
		end
	 end
	 

	 always @(posedge CLK) begin
		AVGMem[AVGIndex] = DATA_IN;
		AVGIndex = AVGIndex+1;
		


		i=0;
		repeat(8) begin
			AVGAccumulator = AVGAccumulator + AVGMem[i];
			i=i+1;
		end
		OUT_ = AVGAccumulator >> 3;
	 end

endmodule