data/full_repos/permissive/113780415/src/top_test.v
 line:1736: before: "&&"
1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(posedge clk && enable == 1'b1)\n                                   ^~\n%Error: Cannot continue\n"
module counter(clk, clear_b, stop, q, enable);

    input clk;

    input clear_b;

    input enable;

    input stop;

    output reg [4:0] q = 0;

    

    always @(posedge clk)

    begin

        if (stop == 1'b1 && enable == 1'b1)

        	begin

	    	if (clear_b == 1'b0)

	        	q <= 0;

	    	else if (q == 5'b10100)

	        	q <= 0;

	    	else

	        	q <= q + 1'b1;

	        end

    end

endmodule
module counter(clk, clear_b, stop, q, enable);


    input clk;

    input clear_b;

    input enable;

    input stop;

    output reg [4:0] q = 0;

    

    always @(posedge clk)

    begin

        if (stop == 1'b1 && enable == 1'b1)

        	begin

	    	if (clear_b == 1'b0)

	        	q <= 0;

	    	else if (q == 5'b10100)

	        	q <= 0;

	    	else

	        	q <= q + 1'b1;

	        end

    end

endmodule