data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/ClockDivider.v
data/verilator_xmls/3889a5cc-f68c-46f2-90f2-ed4a02020483.xml
module ClockDivider #(
    parameter TARGET_CLOCK_FREQ = 10,
    parameter SOUREC_CLK_FREQ = 100000000
    ) (
    input CLK,
    input RST_N,
    output reg CLK_Out
    );
    localparam COUNTS_PER_CLOCK = SOUREC_CLK_FREQ / (2 * TARGET_CLOCK_FREQ);

    reg [31:0] count;
    
    always @ (posedge CLK) begin
        if (!RST_N) begin 
            count <= 0;
            CLK_Out <= 0;
        end
        else if (count == COUNTS_PER_CLOCK) begin
            count <= 0;
            CLK_Out <= ~CLK_Out;
        end        
        else begin
            count <= count + 1;
        end
    end

endmodule
module ClockDivider #(
    parameter TARGET_CLOCK_FREQ = 10,
    parameter SOUREC_CLK_FREQ = 100000000
    ) (
    input CLK,
    input RST_N,
    output reg CLK_Out
    );

    localparam COUNTS_PER_CLOCK = SOUREC_CLK_FREQ / (2 * TARGET_CLOCK_FREQ);

    reg [31:0] count;
    
    always @ (posedge CLK) begin
        if (!RST_N) begin 
            count <= 0;
            CLK_Out <= 0;
        end
        else if (count == COUNTS_PER_CLOCK) begin
            count <= 0;
            CLK_Out <= ~CLK_Out;
        end        
        else begin
            count <= count + 1;
        end
    end

endmodule