data/full_repos/permissive/136422019/src/computerP2_tb.v
 line:42: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #99   \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:187: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:199: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:216: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:219: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:223: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:241: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:246: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:255: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:260: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:268: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:272: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:276: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:285: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:292: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:296: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:301: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:305: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:310: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:314: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:319: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:328: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:333: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:337: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:342: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:351: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:355: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:358: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:362: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:366: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:369: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:378: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:381: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:384: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:388: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:392: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:408: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:411: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:414: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:417: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:420: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:432: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:435: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:438: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:448: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:451: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:454: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:457: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:460: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:463: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:466: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:478: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:481: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:484: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:487: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:490: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:500: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:503: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:506: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:509: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:512: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:515: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:518: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:532: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:535: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:538: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:552: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:558: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:570: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:583: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:585: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:587: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:589: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:601: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:613: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:627: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computerP2_tb.v:639: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/136422019/src/computerP2_tb.v:29: Cannot find file containing module: \'computer\'\ncomputer cp(clkOut, conFF_Out,\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/computer\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/computer.v\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/computer.sv\n             computer\n             computer.v\n             computer.sv\n             obj_dir/computer\n             obj_dir/computer.v\n             obj_dir/computer.sv\n%Warning-WIDTH: data/full_repos/permissive/136422019/src/computerP2_tb.v:110: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'address\' generates 10 bits.\n                                                                            : ... In instance computerP2_tb\n setControlLow; busDataIn <= address; InPortOut <= 1; MARIn <= 1; \n                          ^~\n%Error: Exiting due to 1 error(s), 102 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module computerP2_tb;


reg [31:0] cycle;
reg [31:0] test;


wire clkOut, conFF_Out;
wire [31:0] busDataOut;
wire [31:0] PC_test, IR_test, MAR_test, MDR_test, cSign_test, outPort_test, r0_test, r1_test, r2_test, r3_test, r4_test, r5_test, r6_test, r7_test, r8_test, r9_test, 
	r10_test, r11_test, r12_test, r13_test, r14_test, r15_test, HI_test, LO_test, Zhigh_test, 
	Zlow_test, Y_test;
	

reg clr, PCinc_en, read, write;


reg HIIn, LOIn, PCIn, IRIn, MARIn, MDRIn, conIn, outPortIn, Y_en, Z_en;


reg HIOut, LOOut, PCOut, IROut, MAROut, MDROut, InPortOut, cOut, Zlow_en, Zhigh_en;


reg Gra, Grb, Grc, Rin, Rout, BAout;
reg [4:0] opcode;
reg [31:0] busDataIn;

computer cp(clkOut, conFF_Out,
	MAR_test, MDR_test, outPort_test, cSign_test, r0_test, r1_test, r2_test, r3_test, r4_test, r5_test, 
		r6_test, r7_test, r8_test, r9_test, r10_test, r11_test, r12_test, r13_test, r14_test, 
		r15_test, HI_test, LO_test, PC_test, Zhigh_test, Zlow_test, Y_test, IR_test, busDataOut, 
	clr, PCinc_en, read, write, Y_en, Z_en, Zlow_en, Zhigh_en, 
	HIIn, LOIn, PCIn, IRIn, MARIn, MDRIn, conIn, outPortIn,
	HIOut, LOOut, PCOut, IROut, MAROut, MDROut, InPortOut, cOut,
	Gra, Grb, Grc, Rin, Rout, BAout,
	opcode,
	busDataIn
);

initial begin
	setControlLow;
	clr <= 1;
	#99
	setControlLow;
	#100
	setPC(20);
	initRAM;
	ldTest;
	stTest;
	aluTest;
	brTest;
	jumpTest;
	mfTest;
	portTest;
end
	
	

task setControlLow; begin

	HIIn <= 0; LOIn <= 0; PCIn <= 0; IRIn <= 0; MARIn <= 0; MDRIn <= 0; Z_en <= 0; Y_en <= 0;
	conIn <= 0; outPortIn <= 0;

	HIOut <= 0; LOOut <= 0; PCOut <= 0; IROut <= 0; MAROut <= 0; MDROut <= 0; InPortOut <= 0; 
		Zlow_en <= 0; Zhigh_en <= 0; cOut <= 0;

	clr <= 0; PCinc_en <= 0; read <= 0; write <= 0;
	Gra <= 0; Grb <= 0; Grc <= 0; Rin <= 0; Rout <= 0; BAout <= 0;
	opcode <= 5'b00000;
	busDataIn <= 32'bzzzzzzzz_zzzzzzzz_zzzzzzzz_zzzzzzzz;
end
endtask



task initRAM; begin

	setRAM(20, 10);
	setRAM(21, 11);
	setRAM(22, 12);
	setRAM(23, 13);
	setRAM(24, 14);
	setRAM(25, 15);
	setRAM(26, 16);
	setRAM(27, 17);
	setRAM(28, 18);
	setRAM(29, 19);
	setRAM(30, 20);
	setRAM(31, 21);
	setRAM(32, 22);
	setRAM(33, 23);
	setRAM(34, 24);
	setRAM(35, 25);

	setRAM(60, 200);
	setRAM(65, 5);
	setRAM(90, 120);
end
endtask



task setRAM;
	input[9:0] address;
	input[31:0] value;
	begin
	setControlLow; busDataIn <= value; InPortOut <= 1; MDRIn <= 1;
	#100
	setControlLow; busDataIn <= address; InPortOut <= 1; MARIn <= 1; 
	#100
	setControlLow; write <= 1;
	#100;
	end
endtask



task setReg;
	input[3:0] register;
	input[31:0] value;
	begin
	setControlLow; busDataIn <= 0; busDataIn[26:23] <= register; InPortOut <= 1; IRIn <= 1;
	#100
	setControlLow; busDataIn <= value; InPortOut <= 1; Gra <= 1; Rin <= 1;
	#100;
	end
endtask



task setPC; 
	input[31:0] value;
	begin
	setControlLow; busDataIn <= value; InPortOut <= 1; PCIn <= 1;
	#100;
	end
endtask



task instructionFetch; begin

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; read <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1;
	#100;
end
endtask







task ldTest; begin

		#100
		test <= 1;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0001_0000_0000000000001000001; InPortOut <= 1; IRIn <= 1;
		#100
		ldInstruction;
		

		#100
		test <= 2;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0000_0001_0000000000000110111; InPortOut <= 1; IRIn <= 1;
		#100
		ldInstruction;
		

		#100
		test <= 3;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0001_0000_0000000000001000001; InPortOut <= 1; IRIn <= 1;
		#100
		ldiInstruction;
		

		#100
		test <= 4;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0001_0001_0000000000000110111; InPortOut <= 1; IRIn <= 1;
		#100
		ldiInstruction;
	

		#100
		test <= 5;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0000_0000_0000000000001000001; InPortOut <= 1; IRIn <= 1;
		#100
		ldrInstruction;
end
endtask



task stTest; begin

		#100
		test <= 6;
		cycle <= -2; setReg(4,15);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0100_0000_0000000000001011010; InPortOut <= 1; IRIn <= 1;
		#100
		stInstruction;

		#100

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0101_0000_0000000000001011010; InPortOut <= 1; IRIn <= 1;
		#100
		ldInstruction;
		

		#100
		test <= 7;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0100_0100_0000000000001011010; InPortOut <= 1; IRIn <= 1;
		#100
		stInstruction;


		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0011_0000_0000000000001101001; InPortOut <= 1; IRIn <= 1;
		#100
		ldInstruction;
		

		#100
		test <= 8;
		cycle <= -2; setReg(4,25);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0100_0100_0000000000001011010; InPortOut <= 1; IRIn <= 1;
		#100
		strInstruction;


		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0000_0000000000001111000; InPortOut <= 1; IRIn <= 1;
		#100
		ldInstruction;
end
endtask



task aluTest; begin

		#100
		test <= 9;
		cycle <= -2; setReg(3,100);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_0011_0000000000000011001; InPortOut <= 1; IRIn <= 1;
		#100
		aluInstruction(9);
		

		#100
		test <= 10;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_0011_0000000000000011001; InPortOut <= 1; IRIn <= 1;
		#100
		aluInstruction(7);
		

		#100
		test <= 11;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_0011_0000000000000011001; InPortOut <= 1; IRIn <= 1;
		#100
		aluInstruction(8);
end
endtask



task brTest; begin

		#100
		test <= 12;
		cycle <= -4; setPC(20);
		cycle <= -3; setReg(6, 0);
		cycle <= -2; setReg(5, 25);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0101_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		brInstruction;
		

		#100
		test <= 13;
		cycle <= -2; setPC(20);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0101_0000000000000000001; InPortOut <= 1; IRIn <= 1;
		#100
		brInstruction;
		

		#100
		test <= 14;
		cycle <= -2; setReg(6, -30);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0101_0000000000000000011; InPortOut <= 1; IRIn <= 1;
		#100
		brInstruction;
		

		#100
		test <= 15;
		cycle <= -2; setPC(20);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0101_0000000000000000010; InPortOut <= 1; IRIn <= 1;
		#100
		brInstruction;
end
endtask



task jumpTest; begin

		#100
		test <= 16;
		cycle <= -2; setReg(2, 30);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_0000_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		jumpInstruction;
		

		#100
		test <= 17;
		cycle <= -2; setPC(20);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_1110_0000000000000000100; InPortOut <= 1; IRIn <= 1;
		#100
		jalInstruction;
end
endtask



task mfTest; begin

		#100
		test <= 18;

		cycle <= -2; setControlLow; busDataIn <= 300; InPortOut <= 1; HIIn <= 1;
		#100

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0100_0000_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		mfhiInstruction;
		

		#100
		test <= 19;

		cycle <= -2; setControlLow; busDataIn <= 500; InPortOut <= 1; LOIn <= 1;
		#100

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0000_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		mfloInstruction;
end
endtask



task portTest; begin

		#100
		test <= 20;
		cycle <= -2; setReg(2, 80);
		#100

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_0000_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		outportInstruction;
		

		#100
		test <= 21;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0011_0000_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		inportInstruction;
end
endtask







task ldInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; BAout <= 1; Grb <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; MARIn <= 1;
	#100

	cycle <= 6; setControlLow; read <= 1; MDRIn <= 1;
	#100

	cycle <= 7; setControlLow; MDROut <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask




task ldiInstruction; begin

	instructionFetch;  

	cycle <= 3; setControlLow; BAout <= 1; Grb <= 1;  Y_en <= 1;
	#100

	cycle <= 4; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask




task ldrInstruction; begin

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; Y_en <= 1; read <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1;
	#100

	cycle <= 3; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 4; setControlLow; Zlow_en <= 1; MARIn <= 1;
	#100

	cycle <= 5; setControlLow; read <= 1; MDRIn <= 1;
	#100

	cycle <= 6; setControlLow; MDROut <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask




task stInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; BAout <= 1; Grb <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; MARIn <= 1;
	#100

	cycle <= 6; setControlLow; Gra <= 1; Rout <= 1; MDRIn <= 1;
	#100

	cycle <= 7; setControlLow; write <= 1;
	#100;
end
endtask




task strInstruction; begin

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; Y_en <= 1; read <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1;
	#100

	cycle <= 3; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 4; setControlLow; Zlow_en <= 1; MARIn <= 1;
	#100

	cycle <= 5; setControlLow; Gra <= 1; Rout <= 1; MDRIn <= 1;
	#100

	cycle <= 6; setControlLow; write <= 1;
	#100;
end
endtask




task aluInstruction; 
	input[4:0] opcodeIn;
	begin

	instructionFetch;

	cycle <= 3; setControlLow; Grb <= 1; Rout <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; cOut <= 1; opcode <= opcodeIn; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; Gra <= 1; Rin <= 1;
	#100;
	end
endtask






task brInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; Gra <= 1; Rout <= 1; conIn <= 1;
	#100

	cycle <= 4; setControlLow; Grb <= 1; Rout <= 1; 
	if(conFF_Out == 1) begin
		PCIn <= 1;
	end
	#100;
end
endtask




task jumpInstruction; begin 

	instructionFetch;

	cycle <= 3; setControlLow; Gra <= 1; Rout <= 1; PCIn <= 1;
	#100;
end
endtask





task jalInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; PCOut <= 1; Y_en <= 1;
	#100
	cycle <= 4; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100
	cycle <= 5; setControlLow; Zlow_en <= 1; Grb <= 1; Rin <= 1;
	#100
	cycle <= 6; setControlLow; Gra <= 1; Rout <= 1; PCIn <= 1; 
	#100;
end
endtask




task mfhiInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; HIOut <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask




task mfloInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; LOOut <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask




task outportInstruction; begin

	cycle <= -1; busDataIn <= 75; InPortOut <= 1; Gra <= 1; Rin <= 1;

	instructionFetch;

	cycle <= 3; setControlLow; Gra <= 1; Rout <= 1; outPortIn <= 1;
	#100;
end
endtask




task inportInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; busDataIn <= 450; InPortOut <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask


endmodule
module computerP2_tb;



reg [31:0] cycle;
reg [31:0] test;


wire clkOut, conFF_Out;
wire [31:0] busDataOut;
wire [31:0] PC_test, IR_test, MAR_test, MDR_test, cSign_test, outPort_test, r0_test, r1_test, r2_test, r3_test, r4_test, r5_test, r6_test, r7_test, r8_test, r9_test, 
	r10_test, r11_test, r12_test, r13_test, r14_test, r15_test, HI_test, LO_test, Zhigh_test, 
	Zlow_test, Y_test;
	

reg clr, PCinc_en, read, write;


reg HIIn, LOIn, PCIn, IRIn, MARIn, MDRIn, conIn, outPortIn, Y_en, Z_en;


reg HIOut, LOOut, PCOut, IROut, MAROut, MDROut, InPortOut, cOut, Zlow_en, Zhigh_en;


reg Gra, Grb, Grc, Rin, Rout, BAout;
reg [4:0] opcode;
reg [31:0] busDataIn;

computer cp(clkOut, conFF_Out,
	MAR_test, MDR_test, outPort_test, cSign_test, r0_test, r1_test, r2_test, r3_test, r4_test, r5_test, 
		r6_test, r7_test, r8_test, r9_test, r10_test, r11_test, r12_test, r13_test, r14_test, 
		r15_test, HI_test, LO_test, PC_test, Zhigh_test, Zlow_test, Y_test, IR_test, busDataOut, 
	clr, PCinc_en, read, write, Y_en, Z_en, Zlow_en, Zhigh_en, 
	HIIn, LOIn, PCIn, IRIn, MARIn, MDRIn, conIn, outPortIn,
	HIOut, LOOut, PCOut, IROut, MAROut, MDROut, InPortOut, cOut,
	Gra, Grb, Grc, Rin, Rout, BAout,
	opcode,
	busDataIn
);

initial begin
	setControlLow;
	clr <= 1;
	#99
	setControlLow;
	#100
	setPC(20);
	initRAM;
	ldTest;
	stTest;
	aluTest;
	brTest;
	jumpTest;
	mfTest;
	portTest;
end
	
	

task setControlLow; begin

	HIIn <= 0; LOIn <= 0; PCIn <= 0; IRIn <= 0; MARIn <= 0; MDRIn <= 0; Z_en <= 0; Y_en <= 0;
	conIn <= 0; outPortIn <= 0;

	HIOut <= 0; LOOut <= 0; PCOut <= 0; IROut <= 0; MAROut <= 0; MDROut <= 0; InPortOut <= 0; 
		Zlow_en <= 0; Zhigh_en <= 0; cOut <= 0;

	clr <= 0; PCinc_en <= 0; read <= 0; write <= 0;
	Gra <= 0; Grb <= 0; Grc <= 0; Rin <= 0; Rout <= 0; BAout <= 0;
	opcode <= 5'b00000;
	busDataIn <= 32'bzzzzzzzz_zzzzzzzz_zzzzzzzz_zzzzzzzz;
end
endtask



task initRAM; begin

	setRAM(20, 10);
	setRAM(21, 11);
	setRAM(22, 12);
	setRAM(23, 13);
	setRAM(24, 14);
	setRAM(25, 15);
	setRAM(26, 16);
	setRAM(27, 17);
	setRAM(28, 18);
	setRAM(29, 19);
	setRAM(30, 20);
	setRAM(31, 21);
	setRAM(32, 22);
	setRAM(33, 23);
	setRAM(34, 24);
	setRAM(35, 25);

	setRAM(60, 200);
	setRAM(65, 5);
	setRAM(90, 120);
end
endtask



task setRAM;
	input[9:0] address;
	input[31:0] value;
	begin
	setControlLow; busDataIn <= value; InPortOut <= 1; MDRIn <= 1;
	#100
	setControlLow; busDataIn <= address; InPortOut <= 1; MARIn <= 1; 
	#100
	setControlLow; write <= 1;
	#100;
	end
endtask



task setReg;
	input[3:0] register;
	input[31:0] value;
	begin
	setControlLow; busDataIn <= 0; busDataIn[26:23] <= register; InPortOut <= 1; IRIn <= 1;
	#100
	setControlLow; busDataIn <= value; InPortOut <= 1; Gra <= 1; Rin <= 1;
	#100;
	end
endtask



task setPC; 
	input[31:0] value;
	begin
	setControlLow; busDataIn <= value; InPortOut <= 1; PCIn <= 1;
	#100;
	end
endtask



task instructionFetch; begin

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; read <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1;
	#100;
end
endtask







task ldTest; begin

		#100
		test <= 1;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0001_0000_0000000000001000001; InPortOut <= 1; IRIn <= 1;
		#100
		ldInstruction;
		

		#100
		test <= 2;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0000_0001_0000000000000110111; InPortOut <= 1; IRIn <= 1;
		#100
		ldInstruction;
		

		#100
		test <= 3;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0001_0000_0000000000001000001; InPortOut <= 1; IRIn <= 1;
		#100
		ldiInstruction;
		

		#100
		test <= 4;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0001_0001_0000000000000110111; InPortOut <= 1; IRIn <= 1;
		#100
		ldiInstruction;
	

		#100
		test <= 5;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0000_0000_0000000000001000001; InPortOut <= 1; IRIn <= 1;
		#100
		ldrInstruction;
end
endtask



task stTest; begin

		#100
		test <= 6;
		cycle <= -2; setReg(4,15);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0100_0000_0000000000001011010; InPortOut <= 1; IRIn <= 1;
		#100
		stInstruction;

		#100

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0101_0000_0000000000001011010; InPortOut <= 1; IRIn <= 1;
		#100
		ldInstruction;
		

		#100
		test <= 7;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0100_0100_0000000000001011010; InPortOut <= 1; IRIn <= 1;
		#100
		stInstruction;


		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0011_0000_0000000000001101001; InPortOut <= 1; IRIn <= 1;
		#100
		ldInstruction;
		

		#100
		test <= 8;
		cycle <= -2; setReg(4,25);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0100_0100_0000000000001011010; InPortOut <= 1; IRIn <= 1;
		#100
		strInstruction;


		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0000_0000000000001111000; InPortOut <= 1; IRIn <= 1;
		#100
		ldInstruction;
end
endtask



task aluTest; begin

		#100
		test <= 9;
		cycle <= -2; setReg(3,100);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_0011_0000000000000011001; InPortOut <= 1; IRIn <= 1;
		#100
		aluInstruction(9);
		

		#100
		test <= 10;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_0011_0000000000000011001; InPortOut <= 1; IRIn <= 1;
		#100
		aluInstruction(7);
		

		#100
		test <= 11;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_0011_0000000000000011001; InPortOut <= 1; IRIn <= 1;
		#100
		aluInstruction(8);
end
endtask



task brTest; begin

		#100
		test <= 12;
		cycle <= -4; setPC(20);
		cycle <= -3; setReg(6, 0);
		cycle <= -2; setReg(5, 25);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0101_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		brInstruction;
		

		#100
		test <= 13;
		cycle <= -2; setPC(20);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0101_0000000000000000001; InPortOut <= 1; IRIn <= 1;
		#100
		brInstruction;
		

		#100
		test <= 14;
		cycle <= -2; setReg(6, -30);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0101_0000000000000000011; InPortOut <= 1; IRIn <= 1;
		#100
		brInstruction;
		

		#100
		test <= 15;
		cycle <= -2; setPC(20);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0101_0000000000000000010; InPortOut <= 1; IRIn <= 1;
		#100
		brInstruction;
end
endtask



task jumpTest; begin

		#100
		test <= 16;
		cycle <= -2; setReg(2, 30);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_0000_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		jumpInstruction;
		

		#100
		test <= 17;
		cycle <= -2; setPC(20);

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_1110_0000000000000000100; InPortOut <= 1; IRIn <= 1;
		#100
		jalInstruction;
end
endtask



task mfTest; begin

		#100
		test <= 18;

		cycle <= -2; setControlLow; busDataIn <= 300; InPortOut <= 1; HIIn <= 1;
		#100

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0100_0000_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		mfhiInstruction;
		

		#100
		test <= 19;

		cycle <= -2; setControlLow; busDataIn <= 500; InPortOut <= 1; LOIn <= 1;
		#100

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0110_0000_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		mfloInstruction;
end
endtask



task portTest; begin

		#100
		test <= 20;
		cycle <= -2; setReg(2, 80);
		#100

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0010_0000_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		outportInstruction;
		

		#100
		test <= 21;

		cycle <= -1; setControlLow; busDataIn <= 32'b00000_0011_0000_0000000000000000000; InPortOut <= 1; IRIn <= 1;
		#100
		inportInstruction;
end
endtask







task ldInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; BAout <= 1; Grb <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; MARIn <= 1;
	#100

	cycle <= 6; setControlLow; read <= 1; MDRIn <= 1;
	#100

	cycle <= 7; setControlLow; MDROut <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask




task ldiInstruction; begin

	instructionFetch;  

	cycle <= 3; setControlLow; BAout <= 1; Grb <= 1;  Y_en <= 1;
	#100

	cycle <= 4; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask




task ldrInstruction; begin

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; Y_en <= 1; read <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1;
	#100

	cycle <= 3; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 4; setControlLow; Zlow_en <= 1; MARIn <= 1;
	#100

	cycle <= 5; setControlLow; read <= 1; MDRIn <= 1;
	#100

	cycle <= 6; setControlLow; MDROut <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask




task stInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; BAout <= 1; Grb <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; MARIn <= 1;
	#100

	cycle <= 6; setControlLow; Gra <= 1; Rout <= 1; MDRIn <= 1;
	#100

	cycle <= 7; setControlLow; write <= 1;
	#100;
end
endtask




task strInstruction; begin

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; Y_en <= 1; read <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1;
	#100

	cycle <= 3; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 4; setControlLow; Zlow_en <= 1; MARIn <= 1;
	#100

	cycle <= 5; setControlLow; Gra <= 1; Rout <= 1; MDRIn <= 1;
	#100

	cycle <= 6; setControlLow; write <= 1;
	#100;
end
endtask




task aluInstruction; 
	input[4:0] opcodeIn;
	begin

	instructionFetch;

	cycle <= 3; setControlLow; Grb <= 1; Rout <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; cOut <= 1; opcode <= opcodeIn; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; Gra <= 1; Rin <= 1;
	#100;
	end
endtask






task brInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; Gra <= 1; Rout <= 1; conIn <= 1;
	#100

	cycle <= 4; setControlLow; Grb <= 1; Rout <= 1; 
	if(conFF_Out == 1) begin
		PCIn <= 1;
	end
	#100;
end
endtask




task jumpInstruction; begin 

	instructionFetch;

	cycle <= 3; setControlLow; Gra <= 1; Rout <= 1; PCIn <= 1;
	#100;
end
endtask





task jalInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; PCOut <= 1; Y_en <= 1;
	#100
	cycle <= 4; setControlLow; cOut <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100
	cycle <= 5; setControlLow; Zlow_en <= 1; Grb <= 1; Rin <= 1;
	#100
	cycle <= 6; setControlLow; Gra <= 1; Rout <= 1; PCIn <= 1; 
	#100;
end
endtask




task mfhiInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; HIOut <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask




task mfloInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; LOOut <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask




task outportInstruction; begin

	cycle <= -1; busDataIn <= 75; InPortOut <= 1; Gra <= 1; Rin <= 1;

	instructionFetch;

	cycle <= 3; setControlLow; Gra <= 1; Rout <= 1; outPortIn <= 1;
	#100;
end
endtask




task inportInstruction; begin

	instructionFetch;

	cycle <= 3; setControlLow; busDataIn <= 450; InPortOut <= 1; Gra <= 1; Rin <= 1;
	#100;
end
endtask


endmodule