data/full_repos/permissive/211316121/lab5_2/x7seg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/211316121/lab5_2/x7seg.v:29: Bit extraction of var[7:0] requires 3 bit index, not 2 bits.\n                                                                      : ... In instance x7seg\n           an[s] = 0;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/211316121/lab5_2/x7seg.v:28: Bit extraction of var[7:0] requires 3 bit index, not 2 bits.\n                                                                      : ... In instance x7seg\n       if(aen[s] == 1)\n             ^\n%Error: data/full_repos/permissive/211316121/lab5_2/x7seg.v:32: Cannot find file containing module: \'Hex7Seg\'\n    Hex7Seg s7(.data(digit), .a2g(a2g));    \n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab5_2,data/full_repos/permissive/211316121/Hex7Seg\n             data/full_repos/permissive/211316121/lab5_2,data/full_repos/permissive/211316121/Hex7Seg.v\n             data/full_repos/permissive/211316121/lab5_2,data/full_repos/permissive/211316121/Hex7Seg.sv\n             Hex7Seg\n             Hex7Seg.v\n             Hex7Seg.sv\n             obj_dir/Hex7Seg\n             obj_dir/Hex7Seg.v\n             obj_dir/Hex7Seg.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module x7seg(
    input   [15:0] x,
    input   clk,
    input [1:0]s,
    output wire [6:0] a2g,
    output  reg [7:0] an,
    output  wire dp ); 

    reg [3:0] digit;
   wire [7:0] aen;
   

    assign dp = 1;           
    assign aen = 'b11111111;    

    always@(*)
    case(s)
        0:digit = x[3:0];
        1:digit = x[7:4];
        2:digit = x[11:8];
        3:digit = x[15:12];
        default: digit = x[3:0];
    endcase

    always@(*)
    begin
       an = 'b11111111;
       if(aen[s] == 1)
           an[s] = 0;
    end
 
    Hex7Seg s7(.data(digit), .a2g(a2g));    
endmodule
module x7seg(
    input   [15:0] x,
    input   clk,
    input [1:0]s,
    output wire [6:0] a2g,
    output  reg [7:0] an,
    output  wire dp );
 

    reg [3:0] digit;
   wire [7:0] aen;
   

    assign dp = 1;           
    assign aen = 'b11111111;    

    always@(*)
    case(s)
        0:digit = x[3:0];
        1:digit = x[7:4];
        2:digit = x[11:8];
        3:digit = x[15:12];
        default: digit = x[3:0];
    endcase

    always@(*)
    begin
       an = 'b11111111;
       if(aen[s] == 1)
           an[s] = 0;
    end
 
    Hex7Seg s7(.data(digit), .a2g(a2g));    
endmodule