data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter.v
1: b"%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter.v:56: Cannot find file containing module: 'sonic_vc_timing_adapter_fifo'\n   sonic_vc_timing_adapter_fifo sonic_vc_timing_adapter_fifo \n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules,data/full_repos/permissive/18477150/sonic_vc_timing_adapter_fifo\n             data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules,data/full_repos/permissive/18477150/sonic_vc_timing_adapter_fifo.v\n             data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules,data/full_repos/permissive/18477150/sonic_vc_timing_adapter_fifo.sv\n             sonic_vc_timing_adapter_fifo\n             sonic_vc_timing_adapter_fifo.v\n             sonic_vc_timing_adapter_fifo.sv\n             obj_dir/sonic_vc_timing_adapter_fifo\n             obj_dir/sonic_vc_timing_adapter_fifo.v\n             obj_dir/sonic_vc_timing_adapter_fifo.sv\n%Error: Exiting due to 1 error(s)\n"
module sonic_vc_timing_adapter (
    

      input              clk,

      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [127: 0] in_data,
      input              in_error,
      input              in_startofpacket,
      input              in_endofpacket,
      input      [ 1: 0] in_empty,

      input              out_ready,
      output reg         out_valid,
      output reg [127: 0] out_data,
      output reg         out_error,
      output reg         out_startofpacket,
      output reg         out_endofpacket,
      output reg [ 1: 0] out_empty
);








   reg  [132: 0] in_payload;
   wire [132: 0] out_payload;
   wire         in_ready_wire;
   wire         out_valid_wire;
   wire [ 3: 0] fifo_fill;
   reg  [ 0: 0] ready;





   always @* begin
     in_payload = {in_data,in_error,in_startofpacket,in_endofpacket,in_empty};
     {out_data,out_error,out_startofpacket,out_endofpacket,out_empty} = out_payload;
   end




   sonic_vc_timing_adapter_fifo sonic_vc_timing_adapter_fifo 
     ( 
       .clk        (clk),
       .reset_n    (reset_n),
       .in_ready   (),
       .in_valid   (in_valid),      
       .in_data    (in_payload),
       .out_ready  (ready[0]),
       .out_valid  (out_valid_wire),      
       .out_data   (out_payload),
       .fill_level (fifo_fill)
       );




   always @* begin
      in_ready = (fifo_fill < 4 );
      out_valid = out_valid_wire;
      ready[0] = out_ready;
   end



endmodule
module sonic_vc_timing_adapter (
    

      input              clk,

      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [127: 0] in_data,
      input              in_error,
      input              in_startofpacket,
      input              in_endofpacket,
      input      [ 1: 0] in_empty,

      input              out_ready,
      output reg         out_valid,
      output reg [127: 0] out_data,
      output reg         out_error,
      output reg         out_startofpacket,
      output reg         out_endofpacket,
      output reg [ 1: 0] out_empty
);









   reg  [132: 0] in_payload;
   wire [132: 0] out_payload;
   wire         in_ready_wire;
   wire         out_valid_wire;
   wire [ 3: 0] fifo_fill;
   reg  [ 0: 0] ready;





   always @* begin
     in_payload = {in_data,in_error,in_startofpacket,in_endofpacket,in_empty};
     {out_data,out_error,out_startofpacket,out_endofpacket,out_empty} = out_payload;
   end




   sonic_vc_timing_adapter_fifo sonic_vc_timing_adapter_fifo 
     ( 
       .clk        (clk),
       .reset_n    (reset_n),
       .in_ready   (),
       .in_valid   (in_valid),      
       .in_data    (in_payload),
       .out_ready  (ready[0]),
       .out_valid  (out_valid_wire),      
       .out_data   (out_payload),
       .fill_level (fifo_fill)
       );




   always @* begin
      in_ready = (fifo_fill < 4 );
      out_valid = out_valid_wire;
      ready[0] = out_ready;
   end



endmodule