data/full_repos/permissive/139213403/FPGA/parity_calculator_testbench.v
 line:26: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/parity_calculator_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #200;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/parity_calculator_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n   #200;\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/parity_calculator_testbench.v:10: Cannot find file containing module: \'parity_calculator\'\nparity_calculator #(.DBIT(8)) uut1(.data(test_i), .dbit(dbit), .pbit(0), .parity(test_d));\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/parity_calculator\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/parity_calculator.v\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/parity_calculator.sv\n             parity_calculator\n             parity_calculator.v\n             parity_calculator.sv\n             obj_dir/parity_calculator\n             obj_dir/parity_calculator.v\n             obj_dir/parity_calculator.sv\n%Error: data/full_repos/permissive/139213403/FPGA/parity_calculator_testbench.v:11: Cannot find file containing module: \'parity_calculator\'\nparity_calculator #(.DBIT(8)) uut2(.data(test_i), .dbit(dbit), .pbit(1), .parity(test_e));\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/139213403/FPGA/parity_calculator_testbench.v:12: Cannot find file containing module: \'parity_calculator\'\nparity_calculator #(.DBIT(8)) uut3(.data(test_i), .dbit(dbit), .pbit(2), .parity(test_o));\n^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/parity_calculator_testbench.v:18: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                          : ... In instance parity_calculator_testbench\n   test_i = i;\n          ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module parity_calculator_testbench;

integer i;
reg [7:0] test_i;
reg [3:0] dbit;
wire test_d, test_o, test_e;

parity_calculator #(.DBIT(8)) uut1(.data(test_i), .dbit(dbit), .pbit(0), .parity(test_d));
parity_calculator #(.DBIT(8)) uut2(.data(test_i), .dbit(dbit), .pbit(1), .parity(test_e));
parity_calculator #(.DBIT(8)) uut3(.data(test_i), .dbit(dbit), .pbit(2), .parity(test_o));

initial
begin
	for (i = 0; i <= 255; i = i + 1)
		begin
			test_i = i;
			dbit = 7;
			#200;
			dbit = 8;
			#200;
		end
end

endmodule
module parity_calculator_testbench;


integer i;
reg [7:0] test_i;
reg [3:0] dbit;
wire test_d, test_o, test_e;

parity_calculator #(.DBIT(8)) uut1(.data(test_i), .dbit(dbit), .pbit(0), .parity(test_d));
parity_calculator #(.DBIT(8)) uut2(.data(test_i), .dbit(dbit), .pbit(1), .parity(test_e));
parity_calculator #(.DBIT(8)) uut3(.data(test_i), .dbit(dbit), .pbit(2), .parity(test_o));

initial
begin
	for (i = 0; i <= 255; i = i + 1)
		begin
			test_i = i;
			dbit = 7;
			#200;
			dbit = 8;
			#200;
		end
end

endmodule