data/full_repos/permissive/143278/ivltests/pr1903324.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1903324.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass = 1'b1;

  reg [7:0] d_reg = 8'b10100101;
  wire [7:0] d_wire = 8'b01011010;

  test tstr(d_reg);
  test tstw(d_wire);

  initial begin
    #1;

    if (tstr.data_in_array[3] != d_reg)  begin
      $display("FAILED: with a register value.");
      pass = 1'b0;
    end


    if (tstw.data_in_array[3] != d_wire)  begin
      $display("FAILED: with a net value.");
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass = 1'b1;

  reg [7:0] d_reg = 8'b10100101;
  wire [7:0] d_wire = 8'b01011010;

  test tstr(d_reg);
  test tstw(d_wire);

  initial begin
    #1;

    if (tstr.data_in_array[3] != d_reg)  begin
      $display("FAILED: with a register value.");
      pass = 1'b0;
    end


    if (tstw.data_in_array[3] != d_wire)  begin
      $display("FAILED: with a net value.");
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule