data/full_repos/permissive/208556773/boards/upduino3/pwm_pll.v
1: b"%Error: data/full_repos/permissive/208556773/boards/upduino3/pwm_pll.v:20: Cannot find file containing module: 'SB_PLL40_2_PAD'\nSB_PLL40_2_PAD #(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208556773/boards/upduino3,data/full_repos/permissive/208556773/SB_PLL40_2_PAD\n             data/full_repos/permissive/208556773/boards/upduino3,data/full_repos/permissive/208556773/SB_PLL40_2_PAD.v\n             data/full_repos/permissive/208556773/boards/upduino3,data/full_repos/permissive/208556773/SB_PLL40_2_PAD.sv\n             SB_PLL40_2_PAD\n             SB_PLL40_2_PAD.v\n             SB_PLL40_2_PAD.sv\n             obj_dir/SB_PLL40_2_PAD\n             obj_dir/SB_PLL40_2_PAD.v\n             obj_dir/SB_PLL40_2_PAD.sv\n%Error: Exiting due to 1 error(s)\n"
module pwm_pll(
	input  clock_in,
	output clock_out,
  output wire clock_out_buffered,
	output locked
	);

SB_PLL40_2_PAD #(
		.FEEDBACK_PATH("SIMPLE"),
		.DIVR(4'b0000),
		.DIVF(7'b0101110),
		.DIVQ(3'b010),
		.FILTER_RANGE(3'b001)
	) uut (
		.LOCK(locked),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.PACKAGEPIN(clock_in),
		.PLLOUTGLOBALA(clock_out),
    .PLLOUTGLOBALB(clock_out_buffered)
		);

endmodule
module pwm_pll(
	input  clock_in,
	output clock_out,
  output wire clock_out_buffered,
	output locked
	);


SB_PLL40_2_PAD #(
		.FEEDBACK_PATH("SIMPLE"),
		.DIVR(4'b0000),
		.DIVF(7'b0101110),
		.DIVQ(3'b010),
		.FILTER_RANGE(3'b001)
	) uut (
		.LOCK(locked),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.PACKAGEPIN(clock_in),
		.PLLOUTGLOBALA(clock_out),
    .PLLOUTGLOBALB(clock_out_buffered)
		);

endmodule