data/full_repos/permissive/116308238/hdl/wordalign.v
data/verilator_xmls/a7b25c3d-7f92-45cd-ae46-18d9a73bcf0a.xml
module wordalign # (
  parameter integer MAX_CHANNEL_DELAY = 2
)
(
  input wire clk,
  input wire resetn,

  input wire dl0_rxvalidhs,
  input wire dl1_rxvalidhs,
  input wire [7:0] dl0_rxdatahs,
  input wire [7:0] dl1_rxdatahs,
  output wire [15:0] word_out,
  output reg word_valid
);


  reg[15:0] word_delay[MAX_CHANNEL_DELAY+1:0];

  reg[1:0] sync_delay[MAX_CHANNEL_DELAY+1:0];

  reg[1:0] valid_delay[MAX_CHANNEL_DELAY+1:0];

  wire locked;
  reg[7:0] byte_lane0;
  reg[7:0] byte_lane1;

  integer i;

  always @(posedge clk) begin
    if(~resetn) begin
      byte_lane0 <= 0;
      byte_lane1 <= 0;
      for(i = 0; i <= MAX_CHANNEL_DELAY; i = i+1) begin
        word_delay[i] <= 0;
        sync_delay[i] <= 2'b00;
        valid_delay[i] <= 2'b00;
      end
      word_valid <= 1'b0;
    end
    else begin

      word_delay[0] <= {dl0_rxdatahs, dl1_rxdatahs};
      word_delay[1] <= word_delay[0];
      word_delay[2] <= word_delay[1];

      valid_delay[0] <= {dl0_rxvalidhs, dl1_rxvalidhs};
      valid_delay[1] <= valid_delay[0];
      valid_delay[2] <= valid_delay[1];
  




      if(~locked) begin
        sync_delay[0] <= {dl0_rxvalidhs != valid_delay[0][1],
                          dl1_rxvalidhs != valid_delay[0][0]};
        sync_delay[1] <= sync_delay[0];
        sync_delay[2] <= sync_delay[1];
      end


      word_valid <= locked;


      if(sync_delay[0][1])
        byte_lane0 <= word_delay[0][15:8];
      else if(sync_delay[1][1])
        byte_lane0 <= word_delay[1][15:8];
      else if(sync_delay[2][1])
        byte_lane0 <= word_delay[2][15:8];
      else
        byte_lane0 <= 0;
      
      if(sync_delay[0][0])
        byte_lane1 <= word_delay[0][7:0];
      else if(sync_delay[1][0])
        byte_lane1 <= word_delay[1][7:0];
      else if(sync_delay[2][0])
        byte_lane1 <= word_delay[2][7:0];
      else
        byte_lane1 <= 0;
    end
  end




  assign locked = ((sync_delay[0][0] & valid_delay[0][0]) | 
                   (sync_delay[1][0] & valid_delay[1][0]) | 
                   (sync_delay[2][0] & valid_delay[2][0])) &
                  ((sync_delay[0][1] & valid_delay[0][1]) | 
                   (sync_delay[1][1] & valid_delay[1][1]) | 
                   (sync_delay[2][1] & valid_delay[2][1]));
 
  assign word_out = {byte_lane0, byte_lane1};

endmodule
module wordalign # (
  parameter integer MAX_CHANNEL_DELAY = 2
)
(
  input wire clk,
  input wire resetn,

  input wire dl0_rxvalidhs,
  input wire dl1_rxvalidhs,
  input wire [7:0] dl0_rxdatahs,
  input wire [7:0] dl1_rxdatahs,
  output wire [15:0] word_out,
  output reg word_valid
);



  reg[15:0] word_delay[MAX_CHANNEL_DELAY+1:0];

  reg[1:0] sync_delay[MAX_CHANNEL_DELAY+1:0];

  reg[1:0] valid_delay[MAX_CHANNEL_DELAY+1:0];

  wire locked;
  reg[7:0] byte_lane0;
  reg[7:0] byte_lane1;

  integer i;

  always @(posedge clk) begin
    if(~resetn) begin
      byte_lane0 <= 0;
      byte_lane1 <= 0;
      for(i = 0; i <= MAX_CHANNEL_DELAY; i = i+1) begin
        word_delay[i] <= 0;
        sync_delay[i] <= 2'b00;
        valid_delay[i] <= 2'b00;
      end
      word_valid <= 1'b0;
    end
    else begin

      word_delay[0] <= {dl0_rxdatahs, dl1_rxdatahs};
      word_delay[1] <= word_delay[0];
      word_delay[2] <= word_delay[1];

      valid_delay[0] <= {dl0_rxvalidhs, dl1_rxvalidhs};
      valid_delay[1] <= valid_delay[0];
      valid_delay[2] <= valid_delay[1];
  




      if(~locked) begin
        sync_delay[0] <= {dl0_rxvalidhs != valid_delay[0][1],
                          dl1_rxvalidhs != valid_delay[0][0]};
        sync_delay[1] <= sync_delay[0];
        sync_delay[2] <= sync_delay[1];
      end


      word_valid <= locked;


      if(sync_delay[0][1])
        byte_lane0 <= word_delay[0][15:8];
      else if(sync_delay[1][1])
        byte_lane0 <= word_delay[1][15:8];
      else if(sync_delay[2][1])
        byte_lane0 <= word_delay[2][15:8];
      else
        byte_lane0 <= 0;
      
      if(sync_delay[0][0])
        byte_lane1 <= word_delay[0][7:0];
      else if(sync_delay[1][0])
        byte_lane1 <= word_delay[1][7:0];
      else if(sync_delay[2][0])
        byte_lane1 <= word_delay[2][7:0];
      else
        byte_lane1 <= 0;
    end
  end




  assign locked = ((sync_delay[0][0] & valid_delay[0][0]) | 
                   (sync_delay[1][0] & valid_delay[1][0]) | 
                   (sync_delay[2][0] & valid_delay[2][0])) &
                  ((sync_delay[0][1] & valid_delay[0][1]) | 
                   (sync_delay[1][1] & valid_delay[1][1]) | 
                   (sync_delay[2][1] & valid_delay[2][1]));
 
  assign word_out = {byte_lane0, byte_lane1};

endmodule