data/full_repos/permissive/157608247/src/candy_if.v
 line:153: before: "/"
1: b'%Error: data/full_repos/permissive/157608247/src/candy_if.v:1: Cannot find include file: candy_defines.v\n`include "candy_defines.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157608247/src,data/full_repos/permissive/157608247/candy_defines.v\n             data/full_repos/permissive/157608247/src,data/full_repos/permissive/157608247/candy_defines.v.v\n             data/full_repos/permissive/157608247/src,data/full_repos/permissive/157608247/candy_defines.v.sv\n             candy_defines.v\n             candy_defines.v.v\n             candy_defines.v.sv\n             obj_dir/candy_defines.v\n             obj_dir/candy_defines.v.v\n             obj_dir/candy_defines.v.sv\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:6: Define or directive not defined: \'`SRAMAddrWidth\'\n    input wire [`SRAMAddrWidth] pc,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`SRAMAddrWidth] pc,\n                              ^\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire data_ready,\n    ^~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [`SRAMDataWidth] sram_data,\n    ^~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:11: Define or directive not defined: \'`SRAMDataWidth\'\n    input wire [`SRAMDataWidth] sram_data,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:13: Define or directive not defined: \'`SRAMDataWidth\'\n    output reg [`SRAMDataWidth] inst,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:14: Define or directive not defined: \'`SRAMAddrWidth\'\n    output reg [`SRAMAddrWidth] sram_addr,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:16: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg is_mem\n    ^~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:21: Define or directive not defined: \'`RstEnable\'\n    if(rst == `RstEnable) begin\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:24: Define or directive not defined: \'`ReadDisable\'\n        sram_read_enable <= `ReadDisable;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:27: Define or directive not defined: \'`LoadEnable\'\n        if(if_enable == `LoadEnable) begin\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:28: Define or directive not defined: \'`ReadEnable\'\n            sram_read_enable <= `ReadEnable;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:30: Define or directive not defined: \'`ReadReady\'\n            if(data_ready == `ReadReady) begin\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_if.v:35: Define or directive not defined: \'`ReadDisable\'\n            sram_read_enable <= `ReadDisable;\n                                ^~~~~~~~~~~~\n%Error: Exiting due to 15 error(s)\n'
module candy_if(
    input wire clk,
    input wire rst,
    input wire [`SRAMAddrWidth] pc,
    
    input wire if_enable,

    input wire data_ready,
    input wire [`SRAMDataWidth] sram_data,

    output reg [`SRAMDataWidth] inst,
    output reg [`SRAMAddrWidth] sram_addr,
    output reg sram_read_enable,
    output reg is_mem
);

always @ (posedge clk) begin
    is_mem <= 1'b1;
    if(rst == `RstEnable) begin
        sram_addr <= 17'b0;
        inst <= 24'b0;
        sram_read_enable <= `ReadDisable;
    end
    else begin
        if(if_enable == `LoadEnable) begin
            sram_read_enable <= `ReadEnable;
            sram_addr <= pc;
            if(data_ready == `ReadReady) begin
                inst <= sram_data;
            end
        end
        else begin
            sram_read_enable <= `ReadDisable;
        end
    end
end

endmodule
module candy_if(
    input wire clk,
    input wire rst,
    input wire [`SRAMAddrWidth] pc,
    
    input wire if_enable,

    input wire data_ready,
    input wire [`SRAMDataWidth] sram_data,

    output reg [`SRAMDataWidth] inst,
    output reg [`SRAMAddrWidth] sram_addr,
    output reg sram_read_enable,
    output reg is_mem
);


always @ (posedge clk) begin
    is_mem <= 1'b1;
    if(rst == `RstEnable) begin
        sram_addr <= 17'b0;
        inst <= 24'b0;
        sram_read_enable <= `ReadDisable;
    end
    else begin
        if(if_enable == `LoadEnable) begin
            sram_read_enable <= `ReadEnable;
            sram_addr <= pc;
            if(data_ready == `ReadReady) begin
                inst <= sram_data;
            end
        end
        else begin
            sram_read_enable <= `ReadDisable;
        end
    end
end

endmodule