data/full_repos/permissive/141596082/voice_core/rtl/wb_dac/dac_fsm.v
1: b'%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_dac/dac_fsm.v:28: Value too wide for 32-bits expected in this context 72\'h6d616e6461746f7278\n  input [DATA_WIDTH-1:0] bit_frame_number,\n                   ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_dac/dac_fsm.v:28: Width of bit range is huge; vector of over 1billion bits: 0x746f7279\n  input [DATA_WIDTH-1:0] bit_frame_number,\n        ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_dac/dac_fsm.v:36: Value too wide for 32-bits expected in this context 72\'h6d616e6461746f7278\n  reg [DATA_WIDTH-1:0] dac_counter;\n                 ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_dac/dac_fsm.v:36: Width of bit range is huge; vector of over 1billion bits: 0x746f7279\n  reg [DATA_WIDTH-1:0] dac_counter;\n      ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_dac/dac_fsm.v:37: Value too wide for 32-bits expected in this context 72\'h6d616e6461746f7278\n  reg [DATA_WIDTH-1:0] sigma_count;\n                 ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_dac/dac_fsm.v:37: Width of bit range is huge; vector of over 1billion bits: 0x746f7279\n  reg [DATA_WIDTH-1:0] sigma_count;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_dac/dac_fsm.v:69: Operator EQ expects 746f7279 bits on the RHS, but RHS\'s VARREF \'SAMP_DAC\' generates 48 bits.\n                                                                                       : ... In instance dac_fsm\n  assign time_trigger = (dac_counter == SAMP_DAC);\n                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module dac_fsm #(
  parameter DATA_WIDTH = "mandatory",
  parameter SAMP_DAC = "mandatory"
)(
  input                  clk             ,
  input                  resetn          ,
  input                  empty           ,
  input                  ready           ,
  input [DATA_WIDTH-1:0] bit_frame_number,

  output reg             load_data       ,
  output reg             load_sigma      ,
  output reg             reset_sigma     ,
  output reg             channel_sel
);

  reg [DATA_WIDTH-1:0] dac_counter;
  reg [DATA_WIDTH-1:0] sigma_count;

  wire time_trigger,dac_complete;

  reg [2:0] state;

  localparam [2:0] S_IDLE        = 3'd0;
  localparam [2:0] S_CHARGE_DATA_L = 3'd1;
  localparam [2:0] S_CHARGE_DATA_R = 3'd2;
  localparam [2:0] S_WAIT        = 3'd3;
  localparam [2:0] S_LOAD_SIGMA  = 3'd4;


  always @(posedge clk or posedge resetn) begin
    if(resetn | time_trigger | load_data)
      dac_counter <= 0;
    else
      dac_counter <= dac_counter + 1;
  end

  always @(posedge clk or posedge resetn) begin
    if(resetn | load_data) begin
      sigma_count <= 0;
    end else begin
      if(load_sigma) begin
        sigma_count <= sigma_count + 1;
      end else begin
        sigma_count <= sigma_count;
      end
    end
  end

  assign time_trigger = (dac_counter == SAMP_DAC);
  assign dac_complete = (sigma_count == bit_frame_number);

  always @(posedge clk or posedge resetn) begin
    if(resetn)
      state <= S_IDLE;
    else begin
      case(state)
        S_IDLE :
          if(empty)
            state <= S_IDLE;
        else if(ready)
          state <= S_CHARGE_DATA_L;

        S_CHARGE_DATA_L :
          state <= S_CHARGE_DATA_R;
        
        S_CHARGE_DATA_R :
          state <= S_WAIT;

        S_WAIT :
          if(time_trigger)
            state <= S_LOAD_SIGMA;
        else
          state <= S_WAIT;

        S_LOAD_SIGMA :
          if(dac_complete & ~empty)
            state <= S_CHARGE_DATA_L;
        else if(dac_complete & empty)
          state <= S_IDLE;
        else
          state <= S_WAIT;

        default :
          state <= S_IDLE;
      endcase
    end
  end

  always @(state) begin
    load_data   = 1'b0;
    load_sigma  = 1'b0;
    reset_sigma = 1'b0;
    channel_sel = 1'b0;
    case(state)
      S_IDLE : begin
        load_data   = 1'b0;
        load_sigma  = 1'b0;
        reset_sigma = 1'b1;
        channel_sel = 1'b0;
      end
      S_CHARGE_DATA_L : begin
        load_data   = 1'b1;
        load_sigma  = 1'b0;
        reset_sigma = 1'b0;
        channel_sel = 1'b0;
      end
      S_CHARGE_DATA_R : begin
        load_data   = 1'b1;
        load_sigma  = 1'b0;
        reset_sigma = 1'b0;
        channel_sel = 1'b1;
      end
      S_WAIT : begin
        load_data   = 1'b0;
        load_sigma  = 1'b0;
        reset_sigma = 1'b0;
        channel_sel = 1'b0;
      end
      S_LOAD_SIGMA : begin
        load_data   = 1'b0;
        load_sigma  = 1'b1;
        reset_sigma = 1'b0;
        channel_sel = 1'b0;
      end
      default : begin
        load_data   = 1'b0;
        load_sigma  = 1'b0;
        reset_sigma = 1'b0;
        channel_sel = 1'b0;
      end
    endcase
  end

endmodule
module dac_fsm #(
  parameter DATA_WIDTH = "mandatory",
  parameter SAMP_DAC = "mandatory"
)(
  input                  clk             ,
  input                  resetn          ,
  input                  empty           ,
  input                  ready           ,
  input [DATA_WIDTH-1:0] bit_frame_number,

  output reg             load_data       ,
  output reg             load_sigma      ,
  output reg             reset_sigma     ,
  output reg             channel_sel
);


  reg [DATA_WIDTH-1:0] dac_counter;
  reg [DATA_WIDTH-1:0] sigma_count;

  wire time_trigger,dac_complete;

  reg [2:0] state;

  localparam [2:0] S_IDLE        = 3'd0;
  localparam [2:0] S_CHARGE_DATA_L = 3'd1;
  localparam [2:0] S_CHARGE_DATA_R = 3'd2;
  localparam [2:0] S_WAIT        = 3'd3;
  localparam [2:0] S_LOAD_SIGMA  = 3'd4;


  always @(posedge clk or posedge resetn) begin
    if(resetn | time_trigger | load_data)
      dac_counter <= 0;
    else
      dac_counter <= dac_counter + 1;
  end

  always @(posedge clk or posedge resetn) begin
    if(resetn | load_data) begin
      sigma_count <= 0;
    end else begin
      if(load_sigma) begin
        sigma_count <= sigma_count + 1;
      end else begin
        sigma_count <= sigma_count;
      end
    end
  end

  assign time_trigger = (dac_counter == SAMP_DAC);
  assign dac_complete = (sigma_count == bit_frame_number);

  always @(posedge clk or posedge resetn) begin
    if(resetn)
      state <= S_IDLE;
    else begin
      case(state)
        S_IDLE :
          if(empty)
            state <= S_IDLE;
        else if(ready)
          state <= S_CHARGE_DATA_L;

        S_CHARGE_DATA_L :
          state <= S_CHARGE_DATA_R;
        
        S_CHARGE_DATA_R :
          state <= S_WAIT;

        S_WAIT :
          if(time_trigger)
            state <= S_LOAD_SIGMA;
        else
          state <= S_WAIT;

        S_LOAD_SIGMA :
          if(dac_complete & ~empty)
            state <= S_CHARGE_DATA_L;
        else if(dac_complete & empty)
          state <= S_IDLE;
        else
          state <= S_WAIT;

        default :
          state <= S_IDLE;
      endcase
    end
  end

  always @(state) begin
    load_data   = 1'b0;
    load_sigma  = 1'b0;
    reset_sigma = 1'b0;
    channel_sel = 1'b0;
    case(state)
      S_IDLE : begin
        load_data   = 1'b0;
        load_sigma  = 1'b0;
        reset_sigma = 1'b1;
        channel_sel = 1'b0;
      end
      S_CHARGE_DATA_L : begin
        load_data   = 1'b1;
        load_sigma  = 1'b0;
        reset_sigma = 1'b0;
        channel_sel = 1'b0;
      end
      S_CHARGE_DATA_R : begin
        load_data   = 1'b1;
        load_sigma  = 1'b0;
        reset_sigma = 1'b0;
        channel_sel = 1'b1;
      end
      S_WAIT : begin
        load_data   = 1'b0;
        load_sigma  = 1'b0;
        reset_sigma = 1'b0;
        channel_sel = 1'b0;
      end
      S_LOAD_SIGMA : begin
        load_data   = 1'b0;
        load_sigma  = 1'b1;
        reset_sigma = 1'b0;
        channel_sel = 1'b0;
      end
      default : begin
        load_data   = 1'b0;
        load_sigma  = 1'b0;
        reset_sigma = 1'b0;
        channel_sel = 1'b0;
      end
    endcase
  end

endmodule