data/full_repos/permissive/154352170/CMP.v
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data/verilator_xmls/56c832db-dae8-40af-9805-c265cb9e7f22.xml
module CMP(
    input [31:0] RD1,
    input [31:0] RD2,
	 output Zero,
	 output Bgezalr
    );
	 
	 assign Zero = (RD1 == RD2) ? 1 : 0;
    assign Bgezalr = (RD1[31] == 1) ? 0 : 1;
endmodule
module CMP(
    input [31:0] RD1,
    input [31:0] RD2,
	 output Zero,
	 output Bgezalr
    );

	 
	 assign Zero = (RD1 == RD2) ? 1 : 0;
    assign Bgezalr = (RD1[31] == 1) ? 0 : 1;
endmodule