data/full_repos/permissive/174263347/JamaOneChip/hdl/scanconv.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/174263347/JamaOneChip/hdl/scanconv.v:36: Cannot find file containing module: 'vga'\nvga         ivga (  .clk(clk), \n^~~\n        ... Looked in:\n             data/full_repos/permissive/174263347/JamaOneChip/hdl,data/full_repos/permissive/174263347/vga\n             data/full_repos/permissive/174263347/JamaOneChip/hdl,data/full_repos/permissive/174263347/vga.v\n             data/full_repos/permissive/174263347/JamaOneChip/hdl,data/full_repos/permissive/174263347/vga.sv\n             vga\n             vga.v\n             vga.sv\n             obj_dir/vga\n             obj_dir/vga.v\n             obj_dir/vga.sv\n%Error: data/full_repos/permissive/174263347/JamaOneChip/hdl/scanconv.v:46: Cannot find file containing module: 'memory'\nmemory      imemory(.clk(clk), \n^~~~~~\n%Error: data/full_repos/permissive/174263347/JamaOneChip/hdl/scanconv.v:65: Cannot find file containing module: 'cgaega'\ncgaega      icgaega(.clk(clk), \n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module scanconv ( clk, nReset, nHsync, nVsync, ega, iVideo, oVideo, csync, relay, aMem, dMem, nCs, nOe, nWe );


    input   nHsync, nVsync;
    input   clk,  nReset, iVideo;
    output  csync, relay, oVideo;
    input   ega;

    output  [15:0] aMem;
    inout   [7:0]  dMem;
    output  nCs, nOe, nWe;


    wire    hsync, vsync;
    wire    save;
    wire    reset;


    assign  hsync = ~nHsync;
    assign  vsync = ~nVsync;
    assign  reset = ~nReset;

    wire    [7:0] dVga, dCga;
    wire    [15:0] aVga, aCga;
    wire    wrVga, wrVgaReq;
    wire    dirout;
    wire    [7:0] dMemOut;
    wire    halfclk;
    wire    access;

vga         ivga (  .clk(clk), 
                    .video(iVideo), 
                    .hsync(hsync), 
                    .vsync(vsync), 
                    .dVga(dVga),
                    .aVga(aVga), 
                    .wrVga(wrVga), 
                    .wrVgaReq(wrVgaReq) 
                 );

memory      imemory(.clk(clk), 
                    .reset(~nReset), 
                    .wrVga(wrVga), 
                    .dVga(dVga), 
                    .aVga(aVga), 
                    .dCga(dCga), 
                    .aCga(aCga), 
                    .dMemIn(dMem),
                    .dMemOut(dMemOut), 
                    .aMem(aMem), 
                    .dirout(dirout),
                    .nCsMem(nCs), 
                    .nOeMem(nOe), 
                    .nWeMem(nWe), 
                    .t3(access), 
                    .halfclk(halfclk),
                    .wrVgaReq(wrVgaReq)
                   );

cgaega      icgaega(.clk(clk), 
                    .reset(~nReset), 
                    .access(access), 
                    .halfclk(halfclk), 
                    .ega(ega), 
                    .dCga(dCga), 
                    .aCga(aCga), 
                    .csync(csync), 
                    .video(oVideo));

assign dMem[7:0] = dirout ? 8'bzzzzzzzz : dMemOut;

assign relay = 1;

endmodule
module scanconv ( clk, nReset, nHsync, nVsync, ega, iVideo, oVideo, csync, relay, aMem, dMem, nCs, nOe, nWe );



    input   nHsync, nVsync;
    input   clk,  nReset, iVideo;
    output  csync, relay, oVideo;
    input   ega;

    output  [15:0] aMem;
    inout   [7:0]  dMem;
    output  nCs, nOe, nWe;


    wire    hsync, vsync;
    wire    save;
    wire    reset;


    assign  hsync = ~nHsync;
    assign  vsync = ~nVsync;
    assign  reset = ~nReset;

    wire    [7:0] dVga, dCga;
    wire    [15:0] aVga, aCga;
    wire    wrVga, wrVgaReq;
    wire    dirout;
    wire    [7:0] dMemOut;
    wire    halfclk;
    wire    access;

vga         ivga (  .clk(clk), 
                    .video(iVideo), 
                    .hsync(hsync), 
                    .vsync(vsync), 
                    .dVga(dVga),
                    .aVga(aVga), 
                    .wrVga(wrVga), 
                    .wrVgaReq(wrVgaReq) 
                 );

memory      imemory(.clk(clk), 
                    .reset(~nReset), 
                    .wrVga(wrVga), 
                    .dVga(dVga), 
                    .aVga(aVga), 
                    .dCga(dCga), 
                    .aCga(aCga), 
                    .dMemIn(dMem),
                    .dMemOut(dMemOut), 
                    .aMem(aMem), 
                    .dirout(dirout),
                    .nCsMem(nCs), 
                    .nOeMem(nOe), 
                    .nWeMem(nWe), 
                    .t3(access), 
                    .halfclk(halfclk),
                    .wrVgaReq(wrVgaReq)
                   );

cgaega      icgaega(.clk(clk), 
                    .reset(~nReset), 
                    .access(access), 
                    .halfclk(halfclk), 
                    .ega(ega), 
                    .dCga(dCga), 
                    .aCga(aCga), 
                    .csync(csync), 
                    .video(oVideo));

assign dMem[7:0] = dirout ? 8'bzzzzzzzz : dMemOut;

assign relay = 1;

endmodule