data/full_repos/permissive/189158787/add/posit_add_8bit_tb.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/189158787/add/posit_add_8bit_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100 i=0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/189158787/add/posit_add_8bit_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #20 start = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189158787/add/posit_add_8bit_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n                #655500 start = 0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/189158787/add/posit_add_8bit_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189158787/add/posit_add_8bit_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk=~clk;\n        ^\n%Error: data/full_repos/permissive/189158787/add/posit_add_8bit_tb.v:30: Cannot find file containing module: \'posit_add\'\nposit_add #(.N(N), .es(es)) uut (in1, in2, start, out, inf, zero, done);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/189158787/add,data/full_repos/permissive/189158787/posit_add\n             data/full_repos/permissive/189158787/add,data/full_repos/permissive/189158787/posit_add.v\n             data/full_repos/permissive/189158787/add,data/full_repos/permissive/189158787/posit_add.sv\n             posit_add\n             posit_add.v\n             posit_add.sv\n             obj_dir/posit_add\n             obj_dir/posit_add.v\n             obj_dir/posit_add.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module posit_add_8bit_tb_v;

function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction

parameter N=8;
parameter Bs=log2(N);
parameter es=4;

reg [N-1:0] in1, in2;
reg start; 
wire out_s;
wire [Bs-1:0] out_r;
wire [Bs+es-1:0]out_e;
wire [N-1:0] out_m, out;
wire done;

	reg clk;
	integer outfile;



posit_add #(.N(N), .es(es)) uut (in1, in2, start, out, inf, zero, done);

reg [N-1:0] data1 [1:65536];
reg [N-1:0] data2 [1:65536];
initial $readmemb("Pin1_8bit.txt",data1);
initial $readmemb("Pin2_8bit.txt",data2);

reg [15:0] i;
	
	initial begin

		in1 = 0;
		in2 = 0;
		clk = 0;
		start = 0;
	
		

		#100 i=0;
		#20 start = 1;
                #655500 start = 0;
		#100;
		
		$fclose(outfile);
		$finish;
	end
	
 always #5 clk=~clk;

  always @(posedge clk) begin			
 	in1=data1[i];	
	in2=data2[i];
	if(i==16'hffff)
  	      $finish;
	else i = i + 1;
 end

initial outfile = $fopen("error_8bit.txt", "wb");

reg [N-1:0] result [1:65536];
initial $readmemb("Pout_8bit_ES4.txt",result);
reg [N-1:0] diff;
always @(negedge clk) begin
	if(start)begin
     	diff = (result[i-1] > out) ? result[i-1]-out : out-result[i-1];

     	$fwrite(outfile, "%d\n",diff);
     	end
end
endmodule
module posit_add_8bit_tb_v;


function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction

parameter N=8;
parameter Bs=log2(N);
parameter es=4;

reg [N-1:0] in1, in2;
reg start; 
wire out_s;
wire [Bs-1:0] out_r;
wire [Bs+es-1:0]out_e;
wire [N-1:0] out_m, out;
wire done;

	reg clk;
	integer outfile;



posit_add #(.N(N), .es(es)) uut (in1, in2, start, out, inf, zero, done);

reg [N-1:0] data1 [1:65536];
reg [N-1:0] data2 [1:65536];
initial $readmemb("Pin1_8bit.txt",data1);
initial $readmemb("Pin2_8bit.txt",data2);

reg [15:0] i;
	
	initial begin

		in1 = 0;
		in2 = 0;
		clk = 0;
		start = 0;
	
		

		#100 i=0;
		#20 start = 1;
                #655500 start = 0;
		#100;
		
		$fclose(outfile);
		$finish;
	end
	
 always #5 clk=~clk;

  always @(posedge clk) begin			
 	in1=data1[i];	
	in2=data2[i];
	if(i==16'hffff)
  	      $finish;
	else i = i + 1;
 end

initial outfile = $fopen("error_8bit.txt", "wb");

reg [N-1:0] result [1:65536];
initial $readmemb("Pout_8bit_ES4.txt",result);
reg [N-1:0] diff;
always @(negedge clk) begin
	if(start)begin
     	diff = (result[i-1] > out) ? result[i-1]-out : out-result[i-1];

     	$fwrite(outfile, "%d\n",diff);
     	end
end
endmodule