data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/correlator/correlate_cos_sin_DSP.v
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/correlator/correlate_cos_sin_DSP.v:90: Cannot find file containing module: 'DSP48E1'\n   DSP48E1\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/correlator,data/full_repos/permissive/20430511/DSP48E1\n             data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/correlator,data/full_repos/permissive/20430511/DSP48E1.v\n             data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/correlator,data/full_repos/permissive/20430511/DSP48E1.sv\n             DSP48E1\n             DSP48E1.v\n             DSP48E1.sv\n             obj_dir/DSP48E1\n             obj_dir/DSP48E1.v\n             obj_dir/DSP48E1.sv\n%Error: Exiting due to 1 error(s)\n"
module correlate_cos_sin_DSP
  #( parameter ACCUM = 24,
     parameter MSB   = ACCUM-1,
     parameter XSB   = ACCUM+MSB,
     parameter SUMHI = 0,
     parameter DELAY = 3)
   (
    input          clk,
    input          clr,
    input          en,
    input          vld,

    input          hi,
    input          ar,
    input          br,
    input          bi,

    input [MSB:0]  dcos,
    input [MSB:0]  dsin,
    output [MSB:0] qcos,
    output [MSB:0] qsin
    );




   wire [6:0] opmode = 7'b0110011;
   wire [3:0] alumode = 4'b0000;
   wire [4:0] inmode = 5'b00000;

   wire [17:0] d = {6'b0, dsin[23:12]};
   wire [17:0] a = {dsin[11:0], dcos[23:18]};
   wire [17:0] b = dcos[17:0];
   
`ifdef __USE_SWAPPED_MEANS
   wire        c0 = SUMHI && hi ? br == 1'b1 : ar == br;
   wire        c1 = SUMHI && hi ? ar == 1'b1 : ar == bi;
`else
   wire        c0 = SUMHI && hi ? ar == 1'b1 : ar == br;
   wire        c1 = SUMHI && hi ? br == 1'b1 : ar == bi;
`endif
   wire [XSB:0] c = {{MSB{1'b0}}, c1, {MSB{1'b0}}, c0};






   DSP48E1
     #(  .OPMODEREG(0),
         .CARRYINREG(0),
         .AREG (1),
         .BREG (1),
         .CREG (1),
         .DREG (1),
         .MREG (0),
         .PREG (1)
       ) DSPCS
       ( .CLK(clk),
         .RSTM(1'b0),

         .CECARRYIN(vld),
         .CECTRL(1'b0),
         .CEM(1'b0),
         .CARRYIN(1'b0),
         .PCIN(48'b0),

         .ALUMODE(alumode),
         .OPMODE(opmode),
         .INMODE(inmode),


         .RSTA(clr),
         .CEA2(en),
         .A(a),
         .RSTB(clr),
         .CEB2(en),
         .B(b),
         .RSTD(clr),
         .CED(en),
         .D(d),

         .RSTC(1'b0),
         .CEC(en),
         .C(c),

         .RSTP(1'b0),
         .CEP(vld),
         .P({qsin, qcos})
         );


endmodule
module correlate_cos_sin_DSP
  #( parameter ACCUM = 24,
     parameter MSB   = ACCUM-1,
     parameter XSB   = ACCUM+MSB,
     parameter SUMHI = 0,
     parameter DELAY = 3)
   (
    input          clk,
    input          clr,
    input          en,
    input          vld,

    input          hi,
    input          ar,
    input          br,
    input          bi,

    input [MSB:0]  dcos,
    input [MSB:0]  dsin,
    output [MSB:0] qcos,
    output [MSB:0] qsin
    );





   wire [6:0] opmode = 7'b0110011;
   wire [3:0] alumode = 4'b0000;
   wire [4:0] inmode = 5'b00000;

   wire [17:0] d = {6'b0, dsin[23:12]};
   wire [17:0] a = {dsin[11:0], dcos[23:18]};
   wire [17:0] b = dcos[17:0];
   
`ifdef __USE_SWAPPED_MEANS
   wire        c0 = SUMHI && hi ? br == 1'b1 : ar == br;
   wire        c1 = SUMHI && hi ? ar == 1'b1 : ar == bi;
`else
   wire        c0 = SUMHI && hi ? ar == 1'b1 : ar == br;
   wire        c1 = SUMHI && hi ? br == 1'b1 : ar == bi;
`endif
   wire [XSB:0] c = {{MSB{1'b0}}, c1, {MSB{1'b0}}, c0};






   DSP48E1
     #(  .OPMODEREG(0),
         .CARRYINREG(0),
         .AREG (1),
         .BREG (1),
         .CREG (1),
         .DREG (1),
         .MREG (0),
         .PREG (1)
       ) DSPCS
       ( .CLK(clk),
         .RSTM(1'b0),

         .CECARRYIN(vld),
         .CECTRL(1'b0),
         .CEM(1'b0),
         .CARRYIN(1'b0),
         .PCIN(48'b0),

         .ALUMODE(alumode),
         .OPMODE(opmode),
         .INMODE(inmode),


         .RSTA(clr),
         .CEA2(en),
         .A(a),
         .RSTB(clr),
         .CEB2(en),
         .B(b),
         .RSTD(clr),
         .CED(en),
         .D(d),

         .RSTC(1'b0),
         .CEC(en),
         .C(c),

         .RSTP(1'b0),
         .CEP(vld),
         .P({qsin, qcos})
         );


endmodule