data/full_repos/permissive/123796236/hazrd_detection.v
1: b"%Error: data/full_repos/permissive/123796236/hazrd_detection.v:6: Duplicate declaration of signal: 'ID_EX_RegisterRt'\ninput [4:0] ID_EX_RegisterRt, IF_ID_RegisterRs, ID_EX_RegisterRt, IF_ID_RegisterRt;\n                                                ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/123796236/hazrd_detection.v:6: ... Location of original declaration\ninput [4:0] ID_EX_RegisterRt, IF_ID_RegisterRs, ID_EX_RegisterRt, IF_ID_RegisterRt;\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/123796236/hazrd_detection.v:2: Duplicate declaration of port: 'ID_EX_RegisterRt'\nID_EX_MemRead, ID_EX_RegisterRt, IF_ID_RegisterRs, ID_EX_RegisterRt, IF_ID_RegisterRt);\n                                                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/123796236/hazrd_detection.v:6: ... Location of original declaration\ninput [4:0] ID_EX_RegisterRt, IF_ID_RegisterRs, ID_EX_RegisterRt, IF_ID_RegisterRt;\n            ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module hazrd_detection_unit(muxCtrl, PCWrite, IF_ID_Write,
ID_EX_MemRead, ID_EX_RegisterRt, IF_ID_RegisterRs, ID_EX_RegisterRt, IF_ID_RegisterRt);

output reg muxCtrl, PCWrite, IF_ID_Write;
input ID_EX_MemRead;
input [4:0] ID_EX_RegisterRt, IF_ID_RegisterRs, ID_EX_RegisterRt, IF_ID_RegisterRt;

initial begin
		PCWrite = 1'b1;
		IF_ID_Write = 1'b1;
		muxCtrl = 1'b1;
end

always @(ID_EX_MemRead or ID_EX_RegisterRt or IF_ID_RegisterRs or ID_EX_RegisterRt or IF_ID_RegisterRt)
begin
if (ID_EX_MemRead 
&& ((ID_EX_RegisterRt == IF_ID_RegisterRs) 
|| (ID_EX_RegisterRt == IF_ID_RegisterRt)))
	begin	
		PCWrite = 1'b0;
		IF_ID_Write = 1'b0;
		muxCtrl = 1'b0;
	end
else 
	begin
		PCWrite = 1'b1;
		IF_ID_Write = 1'b1;
		muxCtrl = 1'b1;
	end
end

endmodule
module hazrd_detection_unit(muxCtrl, PCWrite, IF_ID_Write,
ID_EX_MemRead, ID_EX_RegisterRt, IF_ID_RegisterRs, ID_EX_RegisterRt, IF_ID_RegisterRt);


output reg muxCtrl, PCWrite, IF_ID_Write;
input ID_EX_MemRead;
input [4:0] ID_EX_RegisterRt, IF_ID_RegisterRs, ID_EX_RegisterRt, IF_ID_RegisterRt;

initial begin
		PCWrite = 1'b1;
		IF_ID_Write = 1'b1;
		muxCtrl = 1'b1;
end

always @(ID_EX_MemRead or ID_EX_RegisterRt or IF_ID_RegisterRs or ID_EX_RegisterRt or IF_ID_RegisterRt)
begin
if (ID_EX_MemRead 
&& ((ID_EX_RegisterRt == IF_ID_RegisterRs) 
|| (ID_EX_RegisterRt == IF_ID_RegisterRt)))
	begin	
		PCWrite = 1'b0;
		IF_ID_Write = 1'b0;
		muxCtrl = 1'b0;
	end
else 
	begin
		PCWrite = 1'b1;
		IF_ID_Write = 1'b1;
		muxCtrl = 1'b1;
	end
end

endmodule