data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/spcl_regs.v
1: b'%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/spcl_regs.v:96: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'port_en_b\' generates 8 bits.\n                                                                                                                                : ... In instance spcl_regs\n  else if(port_en_b) \n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/spcl_regs.v:106: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'port_en_c\' generates 8 bits.\n                                                                                                                                 : ... In instance spcl_regs\n  else if(port_en_c) \n       ^~\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/spcl_regs.v:117: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                                                 : ... In instance spcl_regs\n      port_en_b = 1\'b1;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/spcl_regs.v:120: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                 : ... In instance spcl_regs\n      port_en_b = 1\'b0;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/spcl_regs.v:129: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                                                 : ... In instance spcl_regs\n      port_en_c = 1\'b1;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/158500878/project/eight_bit_uc.srcs/sources_1/imports/eight_bit_uc_xpr/spcl_regs.v:132: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                 : ... In instance spcl_regs\n      port_en_c = 1\'b0;\n                ^\n%Error: Exiting due to 6 warning(s)\n'
module spcl_regs ( clk1, clk4, resetn, aluz, alu_cout, skip,
                   w_we, status_c_we, status_z_we,
						 tris_we, f_we, aluout, romdata,
						 fsel, fin, port_int_a, port_int_b, 
						 port_int_c, trisa, trisb, trisc,
						 status, w, fsr, inst );
 

input clk1, clk4, resetn, aluz, alu_cout, skip,
      w_we, status_c_we, status_z_we,
		tris_we, f_we ;
reg[11:0] inst_in;
input [7:0] aluout;
input [11:0] romdata;
input [4:0] fsel;
input [7:0] fin;

output  [7:0] port_int_a;
output [7:0] port_int_b;
output [7:0] port_int_c;

output  [7:0] trisa;
output [7:0] trisb;
output [7:0] trisc;

output [7:0] status;
output [7:0] w;
output [7:0] fsr;
output [11:0] inst;


reg [7:0] port_int_a, port_int_b, port_int_c;
reg [7:0]  port_en_b, port_en_c;

reg [7:0]  trisa, trisb, trisc;

reg [7:0] status;

reg [7:0] w;

reg [11:0] inst;

wire [7:0] status_in;

wire special_we;

wire  reset = ~resetn;

wire       regfile_fsel;

reg [ 7:0]  fsr;





assign regfile_fsel = fsel[4] | fsel[3] ;

assign special_we = f_we & ~regfile_fsel;

always @(posedge clk4 or posedge reset)
begin
  if (reset)  begin
  trisa <= 8'b11111111;
  trisb <= 8'b11111111;
  trisc <= 8'b11111111;
  end
  else 
    begin
      if(tris_we == 1'b1 &&  fsel[2:0] == 3'd5)
      trisa <= aluout;
	  if(tris_we == 1'b1 &&  fsel[2:0] == 3'd6)
      trisb <= aluout;
	  if(tris_we == 1'b1 &&  fsel[2:0] == 3'd7)
      trisc <= aluout;
    end
end




always@(posedge clk4 or posedge reset)
begin
  if(reset)
    port_int_a <= 8'b00000000;
  else if(f_we == 1'b1 && fsel[2:0] == 3'd5) 
   begin
      port_int_a <= aluout;
   end
end
  
always@(posedge clk4 or posedge reset)
begin
  if(reset)
    port_int_b <= 8'b00000000;
  else if(port_en_b) 
   begin
      port_int_b <= aluout;
   end
end
  
always@(posedge clk4 or posedge reset)
begin
  if(reset)
    port_int_c <= 8'b00000000;
  else if(port_en_c) 
   begin
      port_int_c <= aluout;
   end
end
  



always @(special_we or fsel[2:0]) begin
   if (special_we == 1'b1 && fsel[2:0] == 3'd6) begin
      port_en_b = 1'b1;
   end
   else begin
      port_en_b = 1'b0;
   end   
end




always @(special_we or fsel[2:0]) begin
   if (special_we == 1'b1 && fsel[2:0] == 3'd7) begin
      port_en_c = 1'b1;
   end
   else begin
      port_en_c = 1'b0;
   end   
end




always@(posedge clk4 or posedge reset)
begin
  if(reset)
     begin
          status <= 8'b00000000;
	 end
  else
      begin
           status <= status_in;
	  end

end




assign status_in[7:3] = 5'b00000;
assign status_in[1]   = 1'b0;
assign status_in[2]   = (status_z_we & aluz) |
                        (~status_z_we & status[2]);
assign status_in[0]   = (status_c_we & alu_cout) |
                        (~status_c_we & status[0]);



always@(posedge clk4 or posedge reset)
begin
  if(reset)
    w <= 8'b00000000;
  else if(w_we) 
   begin
      w <= aluout;
   end
end


always@(posedge clk4 or posedge reset)
begin
  if(reset)
    fsr <= 8'b00000000;
  else if(f_we == 1'b1 && fsel == 5'b00100 ) 
   begin
      fsr <= fin;
   end
end

always@(posedge clk1 or posedge reset)
begin
 if(reset == 1'b1)
   inst <= 12'b000000000000;
 else 
   inst <= inst_in;
end



always @(skip or romdata) begin
   if (skip == 1'b1) 
      inst_in = 12'b000000000000;
   else
      inst_in = romdata;
end



endmodule
module spcl_regs ( clk1, clk4, resetn, aluz, alu_cout, skip,
                   w_we, status_c_we, status_z_we,
						 tris_we, f_we, aluout, romdata,
						 fsel, fin, port_int_a, port_int_b, 
						 port_int_c, trisa, trisb, trisc,
						 status, w, fsr, inst );

 

input clk1, clk4, resetn, aluz, alu_cout, skip,
      w_we, status_c_we, status_z_we,
		tris_we, f_we ;
reg[11:0] inst_in;
input [7:0] aluout;
input [11:0] romdata;
input [4:0] fsel;
input [7:0] fin;

output  [7:0] port_int_a;
output [7:0] port_int_b;
output [7:0] port_int_c;

output  [7:0] trisa;
output [7:0] trisb;
output [7:0] trisc;

output [7:0] status;
output [7:0] w;
output [7:0] fsr;
output [11:0] inst;


reg [7:0] port_int_a, port_int_b, port_int_c;
reg [7:0]  port_en_b, port_en_c;

reg [7:0]  trisa, trisb, trisc;

reg [7:0] status;

reg [7:0] w;

reg [11:0] inst;

wire [7:0] status_in;

wire special_we;

wire  reset = ~resetn;

wire       regfile_fsel;

reg [ 7:0]  fsr;





assign regfile_fsel = fsel[4] | fsel[3] ;

assign special_we = f_we & ~regfile_fsel;

always @(posedge clk4 or posedge reset)
begin
  if (reset)  begin
  trisa <= 8'b11111111;
  trisb <= 8'b11111111;
  trisc <= 8'b11111111;
  end
  else 
    begin
      if(tris_we == 1'b1 &&  fsel[2:0] == 3'd5)
      trisa <= aluout;
	  if(tris_we == 1'b1 &&  fsel[2:0] == 3'd6)
      trisb <= aluout;
	  if(tris_we == 1'b1 &&  fsel[2:0] == 3'd7)
      trisc <= aluout;
    end
end




always@(posedge clk4 or posedge reset)
begin
  if(reset)
    port_int_a <= 8'b00000000;
  else if(f_we == 1'b1 && fsel[2:0] == 3'd5) 
   begin
      port_int_a <= aluout;
   end
end
  
always@(posedge clk4 or posedge reset)
begin
  if(reset)
    port_int_b <= 8'b00000000;
  else if(port_en_b) 
   begin
      port_int_b <= aluout;
   end
end
  
always@(posedge clk4 or posedge reset)
begin
  if(reset)
    port_int_c <= 8'b00000000;
  else if(port_en_c) 
   begin
      port_int_c <= aluout;
   end
end
  



always @(special_we or fsel[2:0]) begin
   if (special_we == 1'b1 && fsel[2:0] == 3'd6) begin
      port_en_b = 1'b1;
   end
   else begin
      port_en_b = 1'b0;
   end   
end




always @(special_we or fsel[2:0]) begin
   if (special_we == 1'b1 && fsel[2:0] == 3'd7) begin
      port_en_c = 1'b1;
   end
   else begin
      port_en_c = 1'b0;
   end   
end




always@(posedge clk4 or posedge reset)
begin
  if(reset)
     begin
          status <= 8'b00000000;
	 end
  else
      begin
           status <= status_in;
	  end

end




assign status_in[7:3] = 5'b00000;
assign status_in[1]   = 1'b0;
assign status_in[2]   = (status_z_we & aluz) |
                        (~status_z_we & status[2]);
assign status_in[0]   = (status_c_we & alu_cout) |
                        (~status_c_we & status[0]);



always@(posedge clk4 or posedge reset)
begin
  if(reset)
    w <= 8'b00000000;
  else if(w_we) 
   begin
      w <= aluout;
   end
end


always@(posedge clk4 or posedge reset)
begin
  if(reset)
    fsr <= 8'b00000000;
  else if(f_we == 1'b1 && fsel == 5'b00100 ) 
   begin
      fsr <= fin;
   end
end

always@(posedge clk1 or posedge reset)
begin
 if(reset == 1'b1)
   inst <= 12'b000000000000;
 else 
   inst <= inst_in;
end



always @(skip or romdata) begin
   if (skip == 1'b1) 
      inst_in = 12'b000000000000;
   else
      inst_in = romdata;
end



endmodule