data/full_repos/permissive/163494071/analog/analog.v
 line:349: before: "["
1: b'%Warning-MULTITOP: data/full_repos/permissive/163494071/analog/analog.v:322: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'analog\'\nmodule analog(clk,rst,start,change_map,direction1,direction2,direction3,direction4,time_sign,row,g_col,r_col,suc,step_cnt);\n       ^~~~~~\n                                                                           : ... Top module \'two_ten\'\nmodule two_ten(clk,num,ten,one);\n       ^~~~~~~\n                                                                           : ... Top module \'debounce\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n       ^~~~~~~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                ^~~\n        data/full_repos/permissive/163494071/analog/analog.v:355: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                       ^~~\n        data/full_repos/permissive/163494071/analog/analog.v:355: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                              ^~~\n        data/full_repos/permissive/163494071/analog/analog.v:355: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key_pulse\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                  ^~~~~~~~~\n        data/full_repos/permissive/163494071/analog/analog.v:356: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key_pulse\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                               ^~~~~~~~~\n        data/full_repos/permissive/163494071/analog/analog.v:356: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key_pulse\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                                            ^~~~~~~~~\n        data/full_repos/permissive/163494071/analog/analog.v:356: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module analog(clk,rst,start,change_map,direction1,direction2,direction3,direction4,time_sign,row,g_col,r_col,suc,step_cnt);
	input clk;
	input start;
	input rst;
	input change_map;
	input direction1;
	input direction2;
	input direction3;
	input direction4;
	input [4:0] time_sign;

	output reg [7:0] row;
	output reg [7:0] g_col;
	output reg [7:0] r_col;
	output reg suc=1'b0;
	output reg [6:0] step_cnt=7'b000_0000;
	reg [7:0] map_row [7:0];
	reg [7:0] map_row_1 [7:0];
	reg [7:0] map_row_2 [7:0];

	
	initial
	begin
	map_row_1[0]=8'b1111_1000;
	map_row_1[1]=8'b1000_0011;
	map_row_1[2]=8'b1011_1111;
	map_row_1[3]=8'b1010_0001;
	map_row_1[4]=8'b1000_1101;
	map_row_1[5]=8'b1111_1101;
	map_row_1[6]=8'b0000_0001;
	map_row_1[7]=8'b1111_1111;

	map_row_2[0]=8'b1111_1111;
	map_row_2[1]=8'b0001_1100;
	map_row_2[2]=8'b1100_0101;
	map_row_2[3]=8'b0101_0101;
	map_row_2[4]=8'b0101_0101;
	map_row_2[5]=8'b0101_1101;
	map_row_2[6]=8'b0100_0001;
	map_row_2[7]=8'b0111_1111;
	
	end

	reg [2:0] start_point_col;
	reg [2:0] start_point_row;
	reg [2:0] terminal_point_row;
	reg [7:0] terminal_point_col;
	reg [7:0] start_point_1=6'b110_111;
	reg [5:0] terminal_point_1=6'b000_000;
	reg [5:0] start_point_2=6'b001_000;
	reg [5:0] terminal_point_2=6'b001_111;

	reg [2:0] location_row_num;
	reg [2:0] location_col_num;


	wire [2:0] maze_con;
	reg start_con=1'b0;
	reg map_con=1'b0;
	reg mode_con=1'b0;

	assign maze_con = {mode_con,map_con,start_con};

	wire start_lock;
	wire change_map_lock;
	sw a1(.clk(clk),.key_in(start),.key_out(start_lock));
	sw a2(.clk(clk),.key_in(change_map),.key_out(change_map_lock));

	always @(posedge start_lock) begin
		if(start_lock==1) begin
			start_con<=1'b1;
		end
	end

	always @(change_map_lock) begin
		if(change_map_lock==1) begin
			map_con<=1'b1;
		end
		else begin
			map_con<=1'b0;
		end
	end

	always @(posedge clk) begin
		if(map_con==0) begin
			map_row[0]=map_row_1[0];
			map_row[1]=map_row_1[1];
			map_row[2]=map_row_1[2];
			map_row[3]=map_row_1[3];
			map_row[4]=map_row_1[4];
			map_row[5]=map_row_1[5];
			map_row[6]=map_row_1[6];
			map_row[7]=map_row_1[7];
			start_point_row=start_point_1[5:3];
			start_point_col=start_point_1[2:0];
			terminal_point_row=terminal_point_1[5:3];
			terminal_point_col=terminal_point_1[2:0];
		end
		else if(map_con==1)begin
			map_row[0]=map_row_2[0];
			map_row[1]=map_row_2[1];
			map_row[2]=map_row_2[2];
			map_row[3]=map_row_2[3];
			map_row[4]=map_row_2[4];
			map_row[5]=map_row_2[5];
			map_row[6]=map_row_2[6];
			map_row[7]=map_row_2[7];
			start_point_row=start_point_2[5:3];
			start_point_col=start_point_2[2:0];
			terminal_point_row=terminal_point_2[5:3];
			terminal_point_col=terminal_point_2[2:0];
		end
	end

	wire direction_lock1;
	wire direction_lock2;
	wire direction_lock3;
	wire direction_lock4;


	
	sw c1(.clk(clk),.key_in(direction1),.key_out(direction_lock1));
	sw c2(.clk(clk),.key_in(direction2),.key_out(direction_lock2));
	sw c3(.clk(clk),.key_in(direction3),.key_out(direction_lock3));
	sw c4(.clk(clk),.key_in(direction4),.key_out(direction_lock4));

	always @(posedge clk) 
	begin
	if(start_lock==1) begin
		step_cnt<=7'b0000000;
		location_row_num=start_point_row;
		location_col_num=start_point_col;
	end
	
		if(location_row_num!=terminal_point_row||location_col_num!=terminal_point_col)
		begin
			if(direction_lock1&&location_row_num<7)
			
				begin
							if(map_row[location_row_num+1][location_col_num]==0)
							begin
								step_cnt<=step_cnt+1;
								location_row_num=location_row_num+1;
							end
							else begin
								location_col_num=location_col_num;
								location_row_num=location_row_num;
							end
					end
				if(direction_lock2&&location_row_num>0)
					begin
						if(map_row[location_row_num-1][location_col_num]==0) begin
								step_cnt<=step_cnt+1;
								location_row_num=location_row_num-1;
								end
								else begin
									location_row_num=location_row_num;
									location_col_num=location_col_num;
								end
					end
				if(direction_lock3&&location_col_num>0)
			
					begin
						if(map_row[location_row_num][location_col_num-1]==0)
						begin
								step_cnt<=step_cnt+1;
								location_col_num=location_col_num-1;
							end
							else begin
								location_col_num=location_col_num;
								location_row_num=location_row_num;
							end
					end
				if(direction_lock4&&location_col_num<7)
					begin
							if(map_row[location_row_num][location_col_num+1]==0)
							begin
								step_cnt<=step_cnt+1;
								location_col_num=location_col_num+1;
							end
							else begin
								location_row_num=location_row_num;
								location_col_num=location_col_num;
							end
					end
		end


end


	always @(posedge clk) begin
	if((location_row_num==terminal_point_row)&&(location_col_num==terminal_point_col)) begin
			suc<=1'b1;
		end
	else
		suc<=1'b0;
	end

	reg [31:0] count=32'd0;
	reg clk_1kHz;

	always @(posedge clk) begin
		if(count==2) begin
			count<=32'd0;
			clk_1kHz<=~clk_1kHz;
		end
		else begin
			count<=count+1;
		end
	end

	reg [3:0] row_num=4'b0000; 
	
	always @(posedge clk_1kHz) begin
	if(row_num!=4'b0111) begin
		row_num<=row_num+1;
	end
	else row_num<=4'b0000;
	end

	always @(posedge clk_1kHz) begin
	case(row_num)
	4'h0: begin
		row<=8'b1111_1110;
	end
	4'h1: begin
		row<=8'b1111_1101;
	end
	4'h2: begin
		row<=8'b1111_1011;
	end
	4'h3: begin
		row<=8'b1111_0111;
	end
	4'h4: begin
		row<=8'b1110_1111;
	end
	4'h5: begin
		row<=8'b1101_1111;
	end
	4'h6: begin
		row<=8'b1011_1111;
	end
	4'h7: begin
		row<=8'b0111_1111;
	end
	endcase
	end
	always @(posedge clk_1kHz) begin
		if(start_con==0) begin
			r_col<=8'b000_0000;
			g_col<=8'b000_0000;
		end
		else if(start_con==1&&time_sign!=0&&suc==0) begin
			case(row_num)
			4'd0:r_col<=map_row[0];
			4'd1:r_col<=map_row[1];
			4'd2:r_col<=map_row[2];
			4'd3:r_col<=map_row[3];
			4'd4:r_col<=map_row[4];
			4'd5:r_col<=map_row[5];
			4'd6:r_col<=map_row[6];
			4'd7:r_col<=map_row[7];
		endcase
		if(row_num==location_row_num) begin
			case(location_col_num)
				3'd0:g_col<=8'b0000_0001;
				3'd1:g_col<=8'b0000_0010;
				3'd2:g_col<=8'b0000_0100;
				3'd3:g_col<=8'b0000_1000;
				3'd4:g_col<=8'b0001_0000;
				3'd5:g_col<=8'b0010_0000;
				3'd6:g_col<=8'b0100_0000;
				3'd7:g_col<=8'b1000_0000;
			endcase
		end
		if((row_num)!=location_row_num)
		begin
			g_col<=8'b0000_0000;
		end
		end
		else if(start_con==1&&time_sign==0&&suc==0) begin
			case(row_num)
				4'd0:r_col<=8'b0000_0000;
				4'd1:r_col<=8'b0100_0010;
				4'd2:r_col<=8'b0011_1100;
				4'd3:r_col<=8'b0000_0000;
				4'd4:r_col<=8'b0110_0110;
				4'd5:r_col<=8'b0110_0110;
				4'd6:r_col<=8'b0000_0000;
				4'd7:r_col<=8'b0000_0000;
			endcase
			g_col<=8'b0000_0000;
		end
		else if(start_con==1&&time_sign!=0&&suc==1) begin
			case(row_num)
				4'd0:g_col<=8'b0000_0000;
				4'd1:g_col<=8'b0011_1100;
				4'd2:g_col<=8'b0100_0010;
				4'd3:g_col<=8'b0000_0000;
				4'd4:g_col<=8'b0110_0110;
				4'd5:g_col<=8'b0110_0110;
				4'd6:g_col<=8'b0000_0000;
				4'd7:g_col<=8'b0000_0000;
			endcase
			r_col<=8'b0000_0000;
		end
	end

endmodule
module analog(clk,rst,start,change_map,direction1,direction2,direction3,direction4,time_sign,row,g_col,r_col,suc,step_cnt);

	input clk;
	input start;
	input rst;
	input change_map;
	input direction1;
	input direction2;
	input direction3;
	input direction4;
	input [4:0] time_sign;

	output reg [7:0] row;
	output reg [7:0] g_col;
	output reg [7:0] r_col;
	output reg suc=1'b0;
	output reg [6:0] step_cnt=7'b000_0000;
	reg [7:0] map_row [7:0];
	reg [7:0] map_row_1 [7:0];
	reg [7:0] map_row_2 [7:0];

	
	initial
	begin
	map_row_1[0]=8'b1111_1000;
	map_row_1[1]=8'b1000_0011;
	map_row_1[2]=8'b1011_1111;
	map_row_1[3]=8'b1010_0001;
	map_row_1[4]=8'b1000_1101;
	map_row_1[5]=8'b1111_1101;
	map_row_1[6]=8'b0000_0001;
	map_row_1[7]=8'b1111_1111;

	map_row_2[0]=8'b1111_1111;
	map_row_2[1]=8'b0001_1100;
	map_row_2[2]=8'b1100_0101;
	map_row_2[3]=8'b0101_0101;
	map_row_2[4]=8'b0101_0101;
	map_row_2[5]=8'b0101_1101;
	map_row_2[6]=8'b0100_0001;
	map_row_2[7]=8'b0111_1111;
	
	end

	reg [2:0] start_point_col;
	reg [2:0] start_point_row;
	reg [2:0] terminal_point_row;
	reg [7:0] terminal_point_col;
	reg [7:0] start_point_1=6'b110_111;
	reg [5:0] terminal_point_1=6'b000_000;
	reg [5:0] start_point_2=6'b001_000;
	reg [5:0] terminal_point_2=6'b001_111;

	reg [2:0] location_row_num;
	reg [2:0] location_col_num;


	wire [2:0] maze_con;
	reg start_con=1'b0;
	reg map_con=1'b0;
	reg mode_con=1'b0;

	assign maze_con = {mode_con,map_con,start_con};

	wire start_lock;
	wire change_map_lock;
	sw a1(.clk(clk),.key_in(start),.key_out(start_lock));
	sw a2(.clk(clk),.key_in(change_map),.key_out(change_map_lock));

	always @(posedge start_lock) begin
		if(start_lock==1) begin
			start_con<=1'b1;
		end
	end

	always @(change_map_lock) begin
		if(change_map_lock==1) begin
			map_con<=1'b1;
		end
		else begin
			map_con<=1'b0;
		end
	end

	always @(posedge clk) begin
		if(map_con==0) begin
			map_row[0]=map_row_1[0];
			map_row[1]=map_row_1[1];
			map_row[2]=map_row_1[2];
			map_row[3]=map_row_1[3];
			map_row[4]=map_row_1[4];
			map_row[5]=map_row_1[5];
			map_row[6]=map_row_1[6];
			map_row[7]=map_row_1[7];
			start_point_row=start_point_1[5:3];
			start_point_col=start_point_1[2:0];
			terminal_point_row=terminal_point_1[5:3];
			terminal_point_col=terminal_point_1[2:0];
		end
		else if(map_con==1)begin
			map_row[0]=map_row_2[0];
			map_row[1]=map_row_2[1];
			map_row[2]=map_row_2[2];
			map_row[3]=map_row_2[3];
			map_row[4]=map_row_2[4];
			map_row[5]=map_row_2[5];
			map_row[6]=map_row_2[6];
			map_row[7]=map_row_2[7];
			start_point_row=start_point_2[5:3];
			start_point_col=start_point_2[2:0];
			terminal_point_row=terminal_point_2[5:3];
			terminal_point_col=terminal_point_2[2:0];
		end
	end

	wire direction_lock1;
	wire direction_lock2;
	wire direction_lock3;
	wire direction_lock4;


	
	sw c1(.clk(clk),.key_in(direction1),.key_out(direction_lock1));
	sw c2(.clk(clk),.key_in(direction2),.key_out(direction_lock2));
	sw c3(.clk(clk),.key_in(direction3),.key_out(direction_lock3));
	sw c4(.clk(clk),.key_in(direction4),.key_out(direction_lock4));

	always @(posedge clk) 
	begin
	if(start_lock==1) begin
		step_cnt<=7'b0000000;
		location_row_num=start_point_row;
		location_col_num=start_point_col;
	end
	
		if(location_row_num!=terminal_point_row||location_col_num!=terminal_point_col)
		begin
			if(direction_lock1&&location_row_num<7)
			
				begin
							if(map_row[location_row_num+1][location_col_num]==0)
							begin
								step_cnt<=step_cnt+1;
								location_row_num=location_row_num+1;
							end
							else begin
								location_col_num=location_col_num;
								location_row_num=location_row_num;
							end
					end
				if(direction_lock2&&location_row_num>0)
					begin
						if(map_row[location_row_num-1][location_col_num]==0) begin
								step_cnt<=step_cnt+1;
								location_row_num=location_row_num-1;
								end
								else begin
									location_row_num=location_row_num;
									location_col_num=location_col_num;
								end
					end
				if(direction_lock3&&location_col_num>0)
			
					begin
						if(map_row[location_row_num][location_col_num-1]==0)
						begin
								step_cnt<=step_cnt+1;
								location_col_num=location_col_num-1;
							end
							else begin
								location_col_num=location_col_num;
								location_row_num=location_row_num;
							end
					end
				if(direction_lock4&&location_col_num<7)
					begin
							if(map_row[location_row_num][location_col_num+1]==0)
							begin
								step_cnt<=step_cnt+1;
								location_col_num=location_col_num+1;
							end
							else begin
								location_row_num=location_row_num;
								location_col_num=location_col_num;
							end
					end
		end


end


	always @(posedge clk) begin
	if((location_row_num==terminal_point_row)&&(location_col_num==terminal_point_col)) begin
			suc<=1'b1;
		end
	else
		suc<=1'b0;
	end

	reg [31:0] count=32'd0;
	reg clk_1kHz;

	always @(posedge clk) begin
		if(count==2) begin
			count<=32'd0;
			clk_1kHz<=~clk_1kHz;
		end
		else begin
			count<=count+1;
		end
	end

	reg [3:0] row_num=4'b0000; 
	
	always @(posedge clk_1kHz) begin
	if(row_num!=4'b0111) begin
		row_num<=row_num+1;
	end
	else row_num<=4'b0000;
	end

	always @(posedge clk_1kHz) begin
	case(row_num)
	4'h0: begin
		row<=8'b1111_1110;
	end
	4'h1: begin
		row<=8'b1111_1101;
	end
	4'h2: begin
		row<=8'b1111_1011;
	end
	4'h3: begin
		row<=8'b1111_0111;
	end
	4'h4: begin
		row<=8'b1110_1111;
	end
	4'h5: begin
		row<=8'b1101_1111;
	end
	4'h6: begin
		row<=8'b1011_1111;
	end
	4'h7: begin
		row<=8'b0111_1111;
	end
	endcase
	end
	always @(posedge clk_1kHz) begin
		if(start_con==0) begin
			r_col<=8'b000_0000;
			g_col<=8'b000_0000;
		end
		else if(start_con==1&&time_sign!=0&&suc==0) begin
			case(row_num)
			4'd0:r_col<=map_row[0];
			4'd1:r_col<=map_row[1];
			4'd2:r_col<=map_row[2];
			4'd3:r_col<=map_row[3];
			4'd4:r_col<=map_row[4];
			4'd5:r_col<=map_row[5];
			4'd6:r_col<=map_row[6];
			4'd7:r_col<=map_row[7];
		endcase
		if(row_num==location_row_num) begin
			case(location_col_num)
				3'd0:g_col<=8'b0000_0001;
				3'd1:g_col<=8'b0000_0010;
				3'd2:g_col<=8'b0000_0100;
				3'd3:g_col<=8'b0000_1000;
				3'd4:g_col<=8'b0001_0000;
				3'd5:g_col<=8'b0010_0000;
				3'd6:g_col<=8'b0100_0000;
				3'd7:g_col<=8'b1000_0000;
			endcase
		end
		if((row_num)!=location_row_num)
		begin
			g_col<=8'b0000_0000;
		end
		end
		else if(start_con==1&&time_sign==0&&suc==0) begin
			case(row_num)
				4'd0:r_col<=8'b0000_0000;
				4'd1:r_col<=8'b0100_0010;
				4'd2:r_col<=8'b0011_1100;
				4'd3:r_col<=8'b0000_0000;
				4'd4:r_col<=8'b0110_0110;
				4'd5:r_col<=8'b0110_0110;
				4'd6:r_col<=8'b0000_0000;
				4'd7:r_col<=8'b0000_0000;
			endcase
			g_col<=8'b0000_0000;
		end
		else if(start_con==1&&time_sign!=0&&suc==1) begin
			case(row_num)
				4'd0:g_col<=8'b0000_0000;
				4'd1:g_col<=8'b0011_1100;
				4'd2:g_col<=8'b0100_0010;
				4'd3:g_col<=8'b0000_0000;
				4'd4:g_col<=8'b0110_0110;
				4'd5:g_col<=8'b0110_0110;
				4'd6:g_col<=8'b0000_0000;
				4'd7:g_col<=8'b0000_0000;
			endcase
			r_col<=8'b0000_0000;
		end
	end

endmodule