data/full_repos/permissive/125927162/LFSR/LFSR_tb.v
 line:21: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/LFSR/LFSR_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("LFSR.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/LFSR/LFSR_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/LFSR/LFSR_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #2\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/LFSR/LFSR_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #1000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/LFSR/LFSR_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk = !clk;\n          ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LFSR_tb();
   reg clk;
   reg rst;
   wire q;

   LFSR DUT(
	    .clk(clk),
	    .rst(rst),
	    .q(q));

   initial begin
      $dumpfile("LFSR.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      rst = 1;
      #2
	rst = 0;
      #1000
	$finish;
   end

   always #1 clk = !clk;
endmodule
module LFSR_tb();

   reg clk;
   reg rst;
   wire q;

   LFSR DUT(
	    .clk(clk),
	    .rst(rst),
	    .q(q));

   initial begin
      $dumpfile("LFSR.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      rst = 1;
      #2
	rst = 0;
      #1000
	$finish;
   end

   always #1 clk = !clk;
endmodule