data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6310-Verilog/pipe_out_check.v
1: b"%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6310-Verilog/pipe_out_check.v:31: Cannot find file containing module: 'pattern_gen'\npattern_gen #(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6310-Verilog,data/full_repos/permissive/120539939/pattern_gen\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6310-Verilog,data/full_repos/permissive/120539939/pattern_gen.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6310-Verilog,data/full_repos/permissive/120539939/pattern_gen.sv\n             pattern_gen\n             pattern_gen.v\n             pattern_gen.sv\n             obj_dir/pattern_gen\n             obj_dir/pattern_gen.v\n             obj_dir/pattern_gen.sv\n%Error: Exiting due to 1 error(s)\n"
module pipe_out_check(
	input  wire            clk,
	input  wire            reset,
	input  wire            pipe_out_read,
	output reg  [31:0]     pipe_out_data,
	output reg             pipe_out_ready,
	input  wire            throttle_set,
	input  wire [31:0]     throttle_val,
	input  wire [2:0]      pattern
	);


reg  [63:0]  lfsr;
reg  [31:0]  lfsr_p1;
reg  [31:0]  throttle;
reg  [15:0]  level;
wire [31:0]  pg_dout;


pattern_gen #(
		.WIDTH    (32)
	) pg0 (
		.clk      (clk),
		.reset    (reset),
		.enable   (pipe_out_read),
		.mode     (pattern),
		.dout     (pg_dout)
	);


always @(posedge clk) begin
	if (reset == 1'b1) begin
		throttle       <= throttle_val;
		pipe_out_ready <= 1'b0;
		level          <= 16'd0;
	end else begin
		if (pipe_out_read) begin
			pipe_out_data <= pg_dout;
		end

		if (level >= 16'd1024) begin
			pipe_out_ready <= 1'b1;
		end else begin
			pipe_out_ready <= 1'b0;
		end
	

		case ({pipe_out_read, throttle[0]})
			2'b00: begin
			end
			

			2'b01: begin
				if (level < 16'd65535) begin
					level <= level + 1'b1;
				end
			end
			

			2'b10: begin
				if (level > 16'd0) begin
					level <= level - 1'b1;
				end
			end
			

			2'b11: begin
			end
		endcase
	





		if (throttle_set == 1'b1) begin
			throttle <= throttle_val;
		end else begin
			throttle <= {throttle[0], throttle[31:1]};
		end
	end
end

endmodule
module pipe_out_check(
	input  wire            clk,
	input  wire            reset,
	input  wire            pipe_out_read,
	output reg  [31:0]     pipe_out_data,
	output reg             pipe_out_ready,
	input  wire            throttle_set,
	input  wire [31:0]     throttle_val,
	input  wire [2:0]      pattern
	);



reg  [63:0]  lfsr;
reg  [31:0]  lfsr_p1;
reg  [31:0]  throttle;
reg  [15:0]  level;
wire [31:0]  pg_dout;


pattern_gen #(
		.WIDTH    (32)
	) pg0 (
		.clk      (clk),
		.reset    (reset),
		.enable   (pipe_out_read),
		.mode     (pattern),
		.dout     (pg_dout)
	);


always @(posedge clk) begin
	if (reset == 1'b1) begin
		throttle       <= throttle_val;
		pipe_out_ready <= 1'b0;
		level          <= 16'd0;
	end else begin
		if (pipe_out_read) begin
			pipe_out_data <= pg_dout;
		end

		if (level >= 16'd1024) begin
			pipe_out_ready <= 1'b1;
		end else begin
			pipe_out_ready <= 1'b0;
		end
	

		case ({pipe_out_read, throttle[0]})
			2'b00: begin
			end
			

			2'b01: begin
				if (level < 16'd65535) begin
					level <= level + 1'b1;
				end
			end
			

			2'b10: begin
				if (level > 16'd0) begin
					level <= level - 1'b1;
				end
			end
			

			2'b11: begin
			end
		endcase
	





		if (throttle_set == 1'b1) begin
			throttle <= throttle_val;
		end else begin
			throttle <= {throttle[0], throttle[31:1]};
		end
	end
end

endmodule