data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:59: Signal definition not found, creating implicitly: \'pdm_conndition\'\n                                                                                                 : ... Suggested alternative: \'pdm_codition\'\n  assign pdm_conndition = (sys_count == PDM_RATIO);\n         ^~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:37: Value too wide for 32-bits expected in this context 72\'h6d616e6461746f7278\n  input [DATA_WIDTH-1:0]sample_rate,\n                   ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:37: Width of bit range is huge; vector of over 1billion bits: 0x746f7279\n  input [DATA_WIDTH-1:0]sample_rate,\n        ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:54: Value too wide for 32-bits expected in this context 72\'h6d616e6461746f7278\n  reg  [ DATA_WIDTH-1:0] comb_count                     ;\n                   ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:54: Width of bit range is huge; vector of over 1billion bits: 0x746f7279\n  reg  [ DATA_WIDTH-1:0] comb_count                     ;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 48 bits.\n                                                                                              : ... In instance cic_sync\n  wire [COUNTER_WIDTH:0] pdm_half_ratio = PDM_RATIO >> 1;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:59: Operator EQ expects 48 bits on the LHS, but LHS\'s VARREF \'sys_count\' generates 1 bits.\n                                                                                              : ... In instance cic_sync\n  assign pdm_conndition = (sys_count == PDM_RATIO);\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:90: Operator EQ expects 48 bits on the LHS, but LHS\'s VARREF \'sys_count\' generates 1 bits.\n                                                                                              : ... In instance cic_sync\n          if( sys_count == PDM_READING_TIME)\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:102: Operator EQ expects 48 bits on the LHS, but LHS\'s VARREF \'channel\' generates 47 bits.\n                                                                                               : ... In instance cic_sync\n          if(channel == (CHANNELS-1))\n                     ^~\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:114: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                                       : ... In instance cic_sync\n      sys_count <= {COUNTER_WIDTH{1\'b0}};\n                                 ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:117: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                                       : ... In instance cic_sync\n        sys_count <= {COUNTER_WIDTH{1\'b0}};\n                                   ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:136: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                                       : ... In instance cic_sync\n      comb_count <= {COUNTER_WIDTH{1\'b0}};\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_mic_array/cic_sync.v:136: Operator ASSIGNDLY expects 746f7279 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n                                                                                               : ... In instance cic_sync\n      comb_count <= {COUNTER_WIDTH{1\'b0}};\n                 ^~\n%Error: Exiting due to 7 error(s), 6 warning(s)\n'
module cic_sync #(
  parameter SYS_FREQ_HZ = "mandatory",
  parameter PDM_FREQ_HZ = "mandatory",
  parameter CHANNELS    = "mandatory",
  parameter DATA_WIDTH = "mandatory",
  parameter PDM_READING_TIME = "mandatory",
  parameter PDM_RATIO = "mandatory",
  parameter COUNTER_WIDTH = $clog2(SYS_FREQ_HZ/PDM_FREQ_HZ),
  parameter CHANNELS_WIDTH = $clog2(CHANNELS)
 ) (
  input      clk,
  input      resetn,

  input [DATA_WIDTH-1:0]sample_rate,
  input [$clog2(CHANNELS)-1:0] channel,

  input cic_finish,
  output reg pdm_clk,
  output reg read_enable,
  output reg integrator_enable,
  output comb_enable
);

  localparam [2:0] S_IDLE         = 3'd0;
  localparam [2:0] S_READING_TIME = 3'd1;
  localparam [2:0] S_COMPUTE      = 3'd2;
  localparam [2:0] S_HOLD         = 3'd3;


  reg  [COUNTER_WIDTH:0] sys_count                      ;
  reg  [ DATA_WIDTH-1:0] comb_count                     ;
  wire                   pdm_codition                   ;
  wire                   comb_condition                 ;
  wire [COUNTER_WIDTH:0] pdm_half_ratio = PDM_RATIO >> 1;

  assign pdm_conndition = (sys_count == PDM_RATIO);
  assign comb_condition = (comb_count == sample_rate);
  assign comb_enable    = comb_condition;

  reg [2:0] state;

  always @(state) begin
    case(state)
      S_IDLE :
        {integrator_enable,read_enable} = {1'b0,1'b0};

      S_READING_TIME :
        {integrator_enable,read_enable}= {1'b0,1'b1};

      S_COMPUTE :
        {integrator_enable,read_enable} = {1'b1,1'b0};

      S_HOLD :
        {integrator_enable,read_enable} = {1'b1,1'b0};

      default :
        {integrator_enable,read_enable} = {1'b0,1'b0};
    endcase
  end

  always @(posedge clk or posedge resetn) begin
    if(resetn)
      state <= S_IDLE;
    else begin
      case(state)
        S_IDLE :
          if( sys_count == PDM_READING_TIME)
            state <= S_READING_TIME;
        else
          state <= S_IDLE;

        S_READING_TIME :
          state <= S_COMPUTE;

        S_COMPUTE :
          state <= S_HOLD;

        S_HOLD :
          if(channel == (CHANNELS-1))
            state <= S_IDLE;
        else
          state <= S_COMPUTE;
        default :
          state <= S_IDLE;
      endcase
    end
  end

  always @(posedge clk or posedge resetn) begin
    if (resetn)
      sys_count <= {COUNTER_WIDTH{1'b0}};
    else begin
      if (pdm_conndition)
        sys_count <= {COUNTER_WIDTH{1'b0}};
      else
        sys_count <= sys_count + 1'b1;
    end
  end

  always @(posedge clk or posedge resetn) begin
    if (resetn | pdm_conndition)
      pdm_clk <= 1'b1;
    else begin
      if (sys_count == pdm_half_ratio)
        pdm_clk <= 1'b0;
      else
        pdm_clk <= pdm_clk;
    end
  end

  always @(posedge clk or posedge resetn) begin
    if (resetn)
      comb_count <= {COUNTER_WIDTH{1'b0}};
    else
      if (pdm_conndition) begin
        if(comb_condition)
          comb_count <= 0;
        else
          comb_count <= comb_count + 1;
      end
  end

endmodule
module cic_sync #(
  parameter SYS_FREQ_HZ = "mandatory",
  parameter PDM_FREQ_HZ = "mandatory",
  parameter CHANNELS    = "mandatory",
  parameter DATA_WIDTH = "mandatory",
  parameter PDM_READING_TIME = "mandatory",
  parameter PDM_RATIO = "mandatory",
  parameter COUNTER_WIDTH = $clog2(SYS_FREQ_HZ/PDM_FREQ_HZ),
  parameter CHANNELS_WIDTH = $clog2(CHANNELS)
 ) (
  input      clk,
  input      resetn,

  input [DATA_WIDTH-1:0]sample_rate,
  input [$clog2(CHANNELS)-1:0] channel,

  input cic_finish,
  output reg pdm_clk,
  output reg read_enable,
  output reg integrator_enable,
  output comb_enable
);


  localparam [2:0] S_IDLE         = 3'd0;
  localparam [2:0] S_READING_TIME = 3'd1;
  localparam [2:0] S_COMPUTE      = 3'd2;
  localparam [2:0] S_HOLD         = 3'd3;


  reg  [COUNTER_WIDTH:0] sys_count                      ;
  reg  [ DATA_WIDTH-1:0] comb_count                     ;
  wire                   pdm_codition                   ;
  wire                   comb_condition                 ;
  wire [COUNTER_WIDTH:0] pdm_half_ratio = PDM_RATIO >> 1;

  assign pdm_conndition = (sys_count == PDM_RATIO);
  assign comb_condition = (comb_count == sample_rate);
  assign comb_enable    = comb_condition;

  reg [2:0] state;

  always @(state) begin
    case(state)
      S_IDLE :
        {integrator_enable,read_enable} = {1'b0,1'b0};

      S_READING_TIME :
        {integrator_enable,read_enable}= {1'b0,1'b1};

      S_COMPUTE :
        {integrator_enable,read_enable} = {1'b1,1'b0};

      S_HOLD :
        {integrator_enable,read_enable} = {1'b1,1'b0};

      default :
        {integrator_enable,read_enable} = {1'b0,1'b0};
    endcase
  end

  always @(posedge clk or posedge resetn) begin
    if(resetn)
      state <= S_IDLE;
    else begin
      case(state)
        S_IDLE :
          if( sys_count == PDM_READING_TIME)
            state <= S_READING_TIME;
        else
          state <= S_IDLE;

        S_READING_TIME :
          state <= S_COMPUTE;

        S_COMPUTE :
          state <= S_HOLD;

        S_HOLD :
          if(channel == (CHANNELS-1))
            state <= S_IDLE;
        else
          state <= S_COMPUTE;
        default :
          state <= S_IDLE;
      endcase
    end
  end

  always @(posedge clk or posedge resetn) begin
    if (resetn)
      sys_count <= {COUNTER_WIDTH{1'b0}};
    else begin
      if (pdm_conndition)
        sys_count <= {COUNTER_WIDTH{1'b0}};
      else
        sys_count <= sys_count + 1'b1;
    end
  end

  always @(posedge clk or posedge resetn) begin
    if (resetn | pdm_conndition)
      pdm_clk <= 1'b1;
    else begin
      if (sys_count == pdm_half_ratio)
        pdm_clk <= 1'b0;
      else
        pdm_clk <= pdm_clk;
    end
  end

  always @(posedge clk or posedge resetn) begin
    if (resetn)
      comb_count <= {COUNTER_WIDTH{1'b0}};
    else
      if (pdm_conndition) begin
        if(comb_condition)
          comb_count <= 0;
        else
          comb_count <= comb_count + 1;
      end
  end

endmodule