data/full_repos/permissive/143278/ivltests/pr3465541.v
 line:42: before: "#"
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr3465541.v:42: syntax error, unexpected (-for-strength, expecting \'(\'\n   not (strong0, pull1) #16 not1 (op, in1);\n        ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3465541.v:64: Unsupported: Ignoring delay on this delayed statement.\n      # 100;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3465541.v:72: Unsupported: Ignoring delay on this delayed statement.\n      # 100;\n      ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module top;

   reg        d;

   wire       w;
   wire [1:0] b;

   reg        pass;

   dtl_inv u_1 (.op(w),    .in1(d));
   dtl_inv u_2 (.op(b[0]), .in1(d));
   dtl_inv u_3 (.op(b[1]), .in1(b[0]));


   initial begin

      pass = 1'b1;

      d  = 1'b0;
      # 100;

      if ((w !== 1'b1) || (b[0] !== 1'b1) || (b[1] !== 1'b0)) begin
         $display("Failed (w !== b[0]): d = %b,  w = %b, b = %b", d, w, b);
         pass = 1'b0;
      end

      d  = 1'b1;
      # 100;
      if ((w !== 1'b0) || (b[0] !== 1'b0) || (b[1] !== 1'b1)) begin
         $display("Failed (w !== b[0]): d = %b,  w = %b, b = %b", d, w, b);
         pass = 1'b0;
      end

      if (pass) $display("PASSED");
   end

endmodule
module top;


   reg        d;

   wire       w;
   wire [1:0] b;

   reg        pass;

   dtl_inv u_1 (.op(w),    .in1(d));
   dtl_inv u_2 (.op(b[0]), .in1(d));
   dtl_inv u_3 (.op(b[1]), .in1(b[0]));


   initial begin

      pass = 1'b1;

      d  = 1'b0;
      # 100;

      if ((w !== 1'b1) || (b[0] !== 1'b1) || (b[1] !== 1'b0)) begin
         $display("Failed (w !== b[0]): d = %b,  w = %b, b = %b", d, w, b);
         pass = 1'b0;
      end

      d  = 1'b1;
      # 100;
      if ((w !== 1'b0) || (b[0] !== 1'b0) || (b[1] !== 1'b1)) begin
         $display("Failed (w !== b[0]): d = %b,  w = %b, b = %b", d, w, b);
         pass = 1'b0;
      end

      if (pass) $display("PASSED");
   end

endmodule