data/full_repos/permissive/220262286/src/test_kanade32.v
 line:24: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/220262286/src/test_kanade32.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK) clk <= ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/220262286/src/test_kanade32.v:15: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, TEST_KANADE32);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/220262286/src/test_kanade32.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/220262286/src/test_kanade32.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1 reset_n <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/220262286/src/test_kanade32.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK * 2) reset_n <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/220262286/src/test_kanade32.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #500 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TEST_KANADE32();

parameter CLK = 10;

reg reset_n;
reg clk;

always begin
    #(CLK) clk <= ~clk;
end

initial begin
    $dumpvars(0, TEST_KANADE32);
    
    #0;
    reset_n <= 1;
    clk <= 0;
    
    #1 reset_n <= 0;
    #(CLK * 2) reset_n <= 1;
    
    #500 $finish;
end

KANADE32 kanade(
    .reset_n(reset_n),
    .clk(clk)
);

endmodule
module TEST_KANADE32();


parameter CLK = 10;

reg reset_n;
reg clk;

always begin
    #(CLK) clk <= ~clk;
end

initial begin
    $dumpvars(0, TEST_KANADE32);
    
    #0;
    reset_n <= 1;
    clk <= 0;
    
    #1 reset_n <= 0;
    #(CLK * 2) reset_n <= 1;
    
    #500 $finish;
end

KANADE32 kanade(
    .reset_n(reset_n),
    .clk(clk)
);

endmodule