data/full_repos/permissive/170067905/hw3_2/rca_4b.v
1: b"%Error: data/full_repos/permissive/170067905/hw3_2/rca_4b.v:20: Cannot find file containing module: 'fullAdder_1b'\n    fullAdder_1b one(\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170067905/hw3_2,data/full_repos/permissive/170067905/fullAdder_1b\n             data/full_repos/permissive/170067905/hw3_2,data/full_repos/permissive/170067905/fullAdder_1b.v\n             data/full_repos/permissive/170067905/hw3_2,data/full_repos/permissive/170067905/fullAdder_1b.sv\n             fullAdder_1b\n             fullAdder_1b.v\n             fullAdder_1b.sv\n             obj_dir/fullAdder_1b\n             obj_dir/fullAdder_1b.v\n             obj_dir/fullAdder_1b.sv\n%Error: data/full_repos/permissive/170067905/hw3_2/rca_4b.v:29: Cannot find file containing module: 'fullAdder_1b'\n    fullAdder_1b two(\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/170067905/hw3_2/rca_4b.v:38: Cannot find file containing module: 'fullAdder_1b'\n   fullAdder_1b three(\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/170067905/hw3_2/rca_4b.v:47: Cannot find file containing module: 'fullAdder_1b'\n   fullAdder_1b four(\n   ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module rca_4b(A, B, C_in, S, C_out);


    parameter   N = 4;

    input [N-1: 0] A, B;
    input          C_in;
    output [N-1:0] S;
    output         C_out;

    wire 	   c1, c2, c3;


    fullAdder_1b one(

		     .S			(S[0]),
		     .C_out		(c1),

		     .A			(A[0]),
		     .B			(B[0]),
		     .C_in		(C_in));

    fullAdder_1b two(

		     .S			(S[1]),
		     .C_out		(c2),

		     .A			(A[1]),
		     .B			(B[1]),
		     .C_in		(c1));

   fullAdder_1b three(

		     .S			(S[2]),
		     .C_out		(c3),

		     .A			(A[2]),
		     .B			(B[2]),
		     .C_in		(c2));

   fullAdder_1b four(

		     .S			(S[3]),
		     .C_out		(C_out),

		     .A			(A[3]),
		     .B			(B[3]),
		     .C_in		(c3));

endmodule
module rca_4b(A, B, C_in, S, C_out);



    parameter   N = 4;

    input [N-1: 0] A, B;
    input          C_in;
    output [N-1:0] S;
    output         C_out;

    wire 	   c1, c2, c3;


    fullAdder_1b one(

		     .S			(S[0]),
		     .C_out		(c1),

		     .A			(A[0]),
		     .B			(B[0]),
		     .C_in		(C_in));

    fullAdder_1b two(

		     .S			(S[1]),
		     .C_out		(c2),

		     .A			(A[1]),
		     .B			(B[1]),
		     .C_in		(c1));

   fullAdder_1b three(

		     .S			(S[2]),
		     .C_out		(c3),

		     .A			(A[2]),
		     .B			(B[2]),
		     .C_in		(c2));

   fullAdder_1b four(

		     .S			(S[3]),
		     .C_out		(C_out),

		     .A			(A[3]),
		     .B			(B[3]),
		     .C_in		(c3));

endmodule