data/full_repos/permissive/146246005/RISC-y Processor/RISCY_TB.sv
 line:29: before: "$"
1: b'%Error: Cannot find file containing module: Processor,data/full_repos/permissive/146246005\n        ... Looked in:\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.v\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.sv\n             Processor,data/full_repos/permissive/146246005\n             Processor,data/full_repos/permissive/146246005.v\n             Processor,data/full_repos/permissive/146246005.sv\n             obj_dir/Processor,data/full_repos/permissive/146246005\n             obj_dir/Processor,data/full_repos/permissive/146246005.v\n             obj_dir/Processor,data/full_repos/permissive/146246005.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/RISC-y\n%Error: Cannot find file containing module: Processor/RISCY_TB.sv\n%Error: Exiting due to 3 error(s)\n'
module RISCY_TB();
	reg CLK, RST;
	wire [7:0] IO;
	reg [7:0] Data_In;
	integer i;
	
	RISCY UUT(CLK, RST, IO);
	
	initial CLK = 1'b0;
	
	always #10 CLK = !CLK;
	
	assign IO = UUT.PORT_RD ? Data_In: 8'bz;
	
	initial begin
		$vcdpluson;
		$readmemb("ROM_DATA.txt", UUT.ROM32.memory);
	end
	
	initial begin
		RST = 1'b0; Data_In = 8'h55;
		#50 RST = 1'b1;
		#20000

		$finish;
	end
endmodule
module RISCY_TB();

	reg CLK, RST;
	wire [7:0] IO;
	reg [7:0] Data_In;
	integer i;
	
	RISCY UUT(CLK, RST, IO);
	
	initial CLK = 1'b0;
	
	always #10 CLK = !CLK;
	
	assign IO = UUT.PORT_RD ? Data_In: 8'bz;
	
	initial begin
		$vcdpluson;
		$readmemb("ROM_DATA.txt", UUT.ROM32.memory);
	end
	
	initial begin
		RST = 1'b0; Data_In = 8'h55;
		#50 RST = 1'b1;
		#20000

		$finish;
	end
endmodule