data/full_repos/permissive/143278/ivltests/pr2790236.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2790236.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test (a, b);
  output a;
  reg a = 1'b0;
  output reg b = 1'b1;
endmodule
module test (a, b);

  output a;
  reg a = 1'b0;
  output reg b = 1'b1;
endmodule