data/full_repos/permissive/125592111/verilog/EX_MEM.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:47: Duplicate declaration of signal: 'RegWrite_out'\n                                                                : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg RegWrite_out;\n     ^~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:38: ... Location of original declaration\n output RegWrite_out, \n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:48: Duplicate declaration of signal: 'MemtoReg_out'\n reg [1:0] MemtoReg_out, RegDst_out;\n           ^~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:39: ... Location of original declaration\n output [1:0] MemtoReg_out, RegDst_out,\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:48: Duplicate declaration of signal: 'RegDst_out'\n reg [1:0] MemtoReg_out, RegDst_out;\n                         ^~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:39: ... Location of original declaration\n output [1:0] MemtoReg_out, RegDst_out,\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:49: Duplicate declaration of signal: 'Branch_out'\n reg Branch_out, MemRead_out, MemWrite_out, Jump_out;\n     ^~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:40: ... Location of original declaration\n output Branch_out, MemRead_out, MemWrite_out, Jump_out,\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:49: Duplicate declaration of signal: 'MemRead_out'\n reg Branch_out, MemRead_out, MemWrite_out, Jump_out;\n                 ^~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:40: ... Location of original declaration\n output Branch_out, MemRead_out, MemWrite_out, Jump_out,\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:49: Duplicate declaration of signal: 'MemWrite_out'\n reg Branch_out, MemRead_out, MemWrite_out, Jump_out;\n                              ^~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:40: ... Location of original declaration\n output Branch_out, MemRead_out, MemWrite_out, Jump_out,\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:49: Duplicate declaration of signal: 'Jump_out'\n reg Branch_out, MemRead_out, MemWrite_out, Jump_out;\n                                            ^~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:40: ... Location of original declaration\n output Branch_out, MemRead_out, MemWrite_out, Jump_out,\n                                               ^~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:50: Duplicate declaration of signal: 'jump_addr_out'\n reg [31:0] jump_addr_out, branch_addr_out, PC_plus_4_out;\n            ^~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:41: ... Location of original declaration\n output [31:0] jump_addr_out, branch_addr_out, PC_plus_4_out,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:50: Duplicate declaration of signal: 'branch_addr_out'\n reg [31:0] jump_addr_out, branch_addr_out, PC_plus_4_out;\n                           ^~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:41: ... Location of original declaration\n output [31:0] jump_addr_out, branch_addr_out, PC_plus_4_out,\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:50: Duplicate declaration of signal: 'PC_plus_4_out'\n reg [31:0] jump_addr_out, branch_addr_out, PC_plus_4_out;\n                                            ^~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:41: ... Location of original declaration\n output [31:0] jump_addr_out, branch_addr_out, PC_plus_4_out,\n                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:51: Duplicate declaration of signal: 'ALU_zero_out'\n reg ALU_zero_out;\n     ^~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:42: ... Location of original declaration\n output ALU_zero_out,\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:52: Duplicate declaration of signal: 'ALU_result_out'\n reg [31:0] ALU_result_out, reg_read_data_2_out;\n            ^~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:43: ... Location of original declaration\n output [31:0] ALU_result_out, reg_read_data_2_out,\n               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:52: Duplicate declaration of signal: 'reg_read_data_2_out'\n reg [31:0] ALU_result_out, reg_read_data_2_out;\n                            ^~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:43: ... Location of original declaration\n output [31:0] ALU_result_out, reg_read_data_2_out,\n                               ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/EX_MEM.v:53: Duplicate declaration of signal: 'EX_MEM_RegisterRd_out'\n reg [4:0] EX_MEM_RegisterRd_out;\n           ^~~~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/EX_MEM.v:44: ... Location of original declaration\n output [4:0] EX_MEM_RegisterRd_out\n              ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n"
module EX_MEM (	
	input clk, rst,
	input EX_Flush,
	input RegWrite_in,  
	input [1:0] MemtoReg_in, RegDst_in,
	input Branch_in, MemRead_in, MemWrite_in, Jump_in,
	input [31:0] jump_addr_in, branch_addr_in, PC_plus_4_in,
	input ALU_zero_in,
	input [31:0] ALU_result_in, reg_read_data_2_in, 
	input [4:0] ID_EX_RegisterRd_in,
	
	output RegWrite_out, 
	output [1:0] MemtoReg_out, RegDst_out,
	output Branch_out, MemRead_out, MemWrite_out, Jump_out,
	output [31:0] jump_addr_out, branch_addr_out, PC_plus_4_out,
	output ALU_zero_out,
	output [31:0] ALU_result_out, reg_read_data_2_out,
	output [4:0] EX_MEM_RegisterRd_out
);

	reg RegWrite_out;
	reg [1:0] MemtoReg_out, RegDst_out;
	reg Branch_out, MemRead_out, MemWrite_out, Jump_out;
	reg [31:0] jump_addr_out, branch_addr_out, PC_plus_4_out;
	reg ALU_zero_out;
	reg [31:0] ALU_result_out, reg_read_data_2_out;
	reg [4:0] EX_MEM_RegisterRd_out;

	always @(negedge clk) begin
		if (rst == 1'b1) begin
		  RegWrite_out <= 1'b0;
		  MemtoReg_out <= 2'b00;
		  RegDst_out <= 2'b00;
		  Branch_out <= 1'b0;
		  MemRead_out <= 1'b0;
		  MemWrite_out <= 1'b0;
		  Jump_out <= 1'b0;
		  jump_addr_out <= 32'b0;
		  PC_plus_4_out <= 32'b0;
		  branch_addr_out <= 32'b0;
		  ALU_zero_out <= 1'b0;
		  ALU_result_out <= 32'b0;
		  reg_read_data_2_out <= 32'b0;
		  EX_MEM_RegisterRd_out <= 5'b0; 
		end

		else begin

			RegWrite_out <= RegWrite_in;
		 	MemtoReg_out <= MemtoReg_in;
			RegDst_out <= RegDst_in;
		  	Branch_out <= Branch_in;
		  	MemRead_out <= MemRead_in;
		  	MemWrite_out <= MemWrite_in;
		  	Jump_out <= Jump_in;
		  	jump_addr_out <= jump_addr_in;
		  	branch_addr_out <= branch_addr_in;
		  	PC_plus_4_out <= PC_plus_4_in;
		  	ALU_zero_out <= ALU_zero_in;
		  	ALU_result_out <= ALU_result_in;
		  	reg_read_data_2_out <= reg_read_data_2_in;
		  	EX_MEM_RegisterRd_out <= ID_EX_RegisterRd_in;

			if (EX_Flush == 1'b1) begin

				RegWrite_out <= 1'b0;
			  	MemtoReg_out <= 2'b00;
				RegDst_out <= 2'b00;
			  	Branch_out <= 1'b0;
			  	MemRead_out <= 1'b0;
			  	MemWrite_out <= 1'b0;
			  	Jump_out <= 1'b0;

			end
		end
	end
endmodule
module EX_MEM (	
	input clk, rst,
	input EX_Flush,
	input RegWrite_in,  
	input [1:0] MemtoReg_in, RegDst_in,
	input Branch_in, MemRead_in, MemWrite_in, Jump_in,
	input [31:0] jump_addr_in, branch_addr_in, PC_plus_4_in,
	input ALU_zero_in,
	input [31:0] ALU_result_in, reg_read_data_2_in, 
	input [4:0] ID_EX_RegisterRd_in,
	
	output RegWrite_out, 
	output [1:0] MemtoReg_out, RegDst_out,
	output Branch_out, MemRead_out, MemWrite_out, Jump_out,
	output [31:0] jump_addr_out, branch_addr_out, PC_plus_4_out,
	output ALU_zero_out,
	output [31:0] ALU_result_out, reg_read_data_2_out,
	output [4:0] EX_MEM_RegisterRd_out
);


	reg RegWrite_out;
	reg [1:0] MemtoReg_out, RegDst_out;
	reg Branch_out, MemRead_out, MemWrite_out, Jump_out;
	reg [31:0] jump_addr_out, branch_addr_out, PC_plus_4_out;
	reg ALU_zero_out;
	reg [31:0] ALU_result_out, reg_read_data_2_out;
	reg [4:0] EX_MEM_RegisterRd_out;

	always @(negedge clk) begin
		if (rst == 1'b1) begin
		  RegWrite_out <= 1'b0;
		  MemtoReg_out <= 2'b00;
		  RegDst_out <= 2'b00;
		  Branch_out <= 1'b0;
		  MemRead_out <= 1'b0;
		  MemWrite_out <= 1'b0;
		  Jump_out <= 1'b0;
		  jump_addr_out <= 32'b0;
		  PC_plus_4_out <= 32'b0;
		  branch_addr_out <= 32'b0;
		  ALU_zero_out <= 1'b0;
		  ALU_result_out <= 32'b0;
		  reg_read_data_2_out <= 32'b0;
		  EX_MEM_RegisterRd_out <= 5'b0; 
		end

		else begin

			RegWrite_out <= RegWrite_in;
		 	MemtoReg_out <= MemtoReg_in;
			RegDst_out <= RegDst_in;
		  	Branch_out <= Branch_in;
		  	MemRead_out <= MemRead_in;
		  	MemWrite_out <= MemWrite_in;
		  	Jump_out <= Jump_in;
		  	jump_addr_out <= jump_addr_in;
		  	branch_addr_out <= branch_addr_in;
		  	PC_plus_4_out <= PC_plus_4_in;
		  	ALU_zero_out <= ALU_zero_in;
		  	ALU_result_out <= ALU_result_in;
		  	reg_read_data_2_out <= reg_read_data_2_in;
		  	EX_MEM_RegisterRd_out <= ID_EX_RegisterRd_in;

			if (EX_Flush == 1'b1) begin

				RegWrite_out <= 1'b0;
			  	MemtoReg_out <= 2'b00;
				RegDst_out <= 2'b00;
			  	Branch_out <= 1'b0;
			  	MemRead_out <= 1'b0;
			  	MemWrite_out <= 1'b0;
			  	Jump_out <= 1'b0;

			end
		end
	end
endmodule