data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v
 line:93: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n            #(T_clk / 2);\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n            #(T_clk / 2);\n            ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:97: syntax error, unexpected \'@\'\n            @(posedge done);\n            ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:108: syntax error, unexpected \'@\'\n            @(posedge mem);              \n            ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:122: syntax error, unexpected \'@\'\n                    @(posedge clk);      \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n                    #(T_wp) sram[sram_ctrl_addr] = sram_ctrl_data2ram;\n                    ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:126: syntax error, unexpected \'@\'\n                    @(posedge clk);      \n                    ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:132: syntax error, unexpected \'@\'\n                    @(posedge clk);      \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n            #(T_clk / 2) rst = 0;\n            ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:168: syntax error, unexpected \'@\'\n            @(posedge clk) en = 1;\n            ^\n%Error: Exiting due to 6 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function [4:0] bit2addr(input [19:0] addr);
        integer a;
        begin            
            a = 0;
            
            while(addr)
                begin
                    addr = addr >> 1;
                    a = a + 1;
                end
            
            bit2addr = a;
        end
    endfunction
function [4:0] bit2addr(input [19:0] addr);

        integer a;
        begin            
            a = 0;
            
            while(addr)
                begin
                    addr = addr >> 1;
                    a = a + 1;
                end
            
            bit2addr = a;
        end
    endfunction