data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb.sv:81: Unsupported: Ignoring delay on this delayed statement.\n   #10  clk = ~clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb.sv:86: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb.sv:88: Unsupported: Ignoring delay on this delayed statement.\n#30;\n^\n%Error: data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb.sv:89: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb.sv:90: Unsupported: Ignoring delay on this delayed statement.\n#1\n^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tosco_tb;


reg clk, rst_n;


localparam DATA_WIDTH = 32;
localparam INST_ADDR_WIDTH = 20;
localparam DATA_ADDR_WIDTH = 32;


wire data_rd_en;
wire data_wr_en;
wire [DATA_WIDTH-1:0] data_read;
wire [DATA_WIDTH-1:0] data_write;
wire [DATA_ADDR_WIDTH-1:0] data_addr;

wire instr_rd_en;
wire [INST_ADDR_WIDTH-1:0] instr_addr;
wire [DATA_WIDTH-1:0] instruction;

dlx_processor
#(
   .DATA_WIDTH(DATA_WIDTH),
   .INST_ADDR_WIDTH(INST_ADDR_WIDTH),
   .DATA_ADDR_WIDTH(DATA_ADDR_WIDTH)
)
dlx_processor_u0
(
   .clk(clk),
   .rst_n(rst_n),
   .instr_rd_en(instr_rd_en),
   .instr_addr(instr_addr),
   .instruction(instruction),
   .data_rd_en(data_rd_en),
   .data_wr_en(data_wr_en),
   .data_addr(data_addr),
   .data_read(data_read),
   .data_write(data_write)
);



rom
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(10)
)
rom_u0
(
   .clk(clk),
   .rst_n(rst_n),
   .rd_ena(instr_rd_en),
   .address(instr_addr[15:2]),
   .data(instruction)
);


sp_ram
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(10)
)
sp_ram_u0
(
   .clk(clk),
   .rd_ena(data_rd_en),
   .wr_ena(data_wr_en),
   .address(data_addr[DATA_ADDR_WIDTH-1:2]),
   .wr_data(data_write),
   .rd_data(data_read)
);



initial begin
 clk = 0;
end
   
always begin
   #10  clk = ~clk;
end

initial begin
rst_n = 1;
#10;
rst_n = 0;
#30;
@(posedge clk);
#1
rst_n = 1;
end

endmodule
module tosco_tb;



reg clk, rst_n;


localparam DATA_WIDTH = 32;
localparam INST_ADDR_WIDTH = 20;
localparam DATA_ADDR_WIDTH = 32;


wire data_rd_en;
wire data_wr_en;
wire [DATA_WIDTH-1:0] data_read;
wire [DATA_WIDTH-1:0] data_write;
wire [DATA_ADDR_WIDTH-1:0] data_addr;

wire instr_rd_en;
wire [INST_ADDR_WIDTH-1:0] instr_addr;
wire [DATA_WIDTH-1:0] instruction;

dlx_processor
#(
   .DATA_WIDTH(DATA_WIDTH),
   .INST_ADDR_WIDTH(INST_ADDR_WIDTH),
   .DATA_ADDR_WIDTH(DATA_ADDR_WIDTH)
)
dlx_processor_u0
(
   .clk(clk),
   .rst_n(rst_n),
   .instr_rd_en(instr_rd_en),
   .instr_addr(instr_addr),
   .instruction(instruction),
   .data_rd_en(data_rd_en),
   .data_wr_en(data_wr_en),
   .data_addr(data_addr),
   .data_read(data_read),
   .data_write(data_write)
);



rom
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(10)
)
rom_u0
(
   .clk(clk),
   .rst_n(rst_n),
   .rd_ena(instr_rd_en),
   .address(instr_addr[15:2]),
   .data(instruction)
);


sp_ram
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(10)
)
sp_ram_u0
(
   .clk(clk),
   .rd_ena(data_rd_en),
   .wr_ena(data_wr_en),
   .address(data_addr[DATA_ADDR_WIDTH-1:2]),
   .wr_data(data_write),
   .rd_data(data_read)
);



initial begin
 clk = 0;
end
   
always begin
   #10  clk = ~clk;
end

initial begin
rst_n = 1;
#10;
rst_n = 0;
#30;
@(posedge clk);
#1
rst_n = 1;
end

endmodule