data/full_repos/permissive/192241640/testbench.v
 line:51: before: "("
1: b'%Error: data/full_repos/permissive/192241640/testbench.v:12: syntax error, unexpected break, expecting IDENTIFIER or \'=\' or do or final\n reg break;     \n     ^~~~~\n%Error: data/full_repos/permissive/192241640/testbench.v:23: syntax error, unexpected break\n  .break(break),    \n   ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/192241640/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #271.27 txclk = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/192241640/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #271.27 txclk = 1;\n  ^\n%Error: data/full_repos/permissive/192241640/testbench.v:36: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("testbench.lxt");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/192241640/testbench.v:37: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/192241640/testbench.v:45: syntax error, unexpected \'=\', expecting \';\'\n  break = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/192241640/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #250 reset = 0;\n  ^\n%Error: data/full_repos/permissive/192241640/testbench.v:52: Unsupported: wait statements\n  wait(empty);\n  ^~~~\n%Error: data/full_repos/permissive/192241640/testbench.v:57: Unsupported: wait statements\n  wait(empty);\n  ^~~~\n%Error: data/full_repos/permissive/192241640/testbench.v:61: Unsupported: wait statements\n  wait(empty);\n  ^~~~\n%Error: data/full_repos/permissive/192241640/testbench.v:64: syntax error, unexpected \'=\', expecting \';\'\n  #250 break = 1;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/192241640/testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #250 break = 1;\n  ^\n%Error: data/full_repos/permissive/192241640/testbench.v:65: syntax error, unexpected \'=\', expecting \';\'\n  #20000 break = 0;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/192241640/testbench.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #20000 break = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/192241640/testbench.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #5000 $display("finished");\n  ^\n%Error: data/full_repos/permissive/192241640/testbench.v:77: Unsupported: wait statements\n   wait(!txclk);\n   ^~~~\n%Error: data/full_repos/permissive/192241640/testbench.v:78: Unsupported: wait statements\n   wait(txclk); #1 din = {parity_bit, char};\n   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/192241640/testbench.v:78: Unsupported: Ignoring delay on this delayed statement.\n   wait(txclk); #1 din = {parity_bit, char};\n                ^\n%Error: data/full_repos/permissive/192241640/testbench.v:80: Unsupported: wait statements\n   wait(!txclk);\n   ^~~~\n%Error: data/full_repos/permissive/192241640/testbench.v:81: Unsupported: wait statements\n   wait(txclk); #1 we = 1;\n   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/192241640/testbench.v:81: Unsupported: Ignoring delay on this delayed statement.\n   wait(txclk); #1 we = 1;\n                ^\n%Error: data/full_repos/permissive/192241640/testbench.v:82: Unsupported: wait statements\n   wait(!txclk);\n   ^~~~\n%Error: data/full_repos/permissive/192241640/testbench.v:83: Unsupported: wait statements\n   wait(txclk); #1 we = 0;\n   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/192241640/testbench.v:83: Unsupported: Ignoring delay on this delayed statement.\n   wait(txclk); #1 we = 0;\n                ^\n%Error: data/full_repos/permissive/192241640/testbench.v:85: Unsupported: wait statements\n   wait(!txclk);\n   ^~~~\n%Error: data/full_repos/permissive/192241640/testbench.v:86: Unsupported: wait statements\n   wait(txclk); #1 din = 9\'hx;\n   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/192241640/testbench.v:86: Unsupported: Ignoring delay on this delayed statement.\n   wait(txclk); #1 din = 9\'hx;\n                ^\n%Error: Exiting due to 18 error(s), 10 warning(s)\n'
module testbench;

	reg txclk;
	reg reset;

	reg we;
	reg [8:0] din;
	reg parity;

	reg break;
	wire sout;
	wire empty;


	uart_tx uut (
		.txclk(txclk),
		.reset(reset),
		.we(we),
		.din(din),
		.parity(parity),
		.break(break),
		.sout(sout),
		.empty(empty)
	);


	always begin
		#271.27 txclk = 0;
		#271.27 txclk = 1;
	end

	initial begin

		$dumpfile("testbench.lxt");
		$dumpvars;


		txclk = 1;
		reset = 1;
		we = 0;
		din = 9'hx;
		parity = 0;
		break = 0;


		#250 reset = 0;


		send(0, 8'h64);
		wait(empty);


		parity = 1;
		send(1, 8'h64);
		wait(empty);


		send(0, 8'hA5);
		wait(empty);


		#250 break = 1;
		#20000 break = 0;


		#5000 $display("finished");
		$finish;
	end


	task send;
		input parity_bit;
		input [7:0] char;
		begin
			wait(!txclk);
			wait(txclk); #1 din = {parity_bit, char};

			wait(!txclk);
			wait(txclk); #1 we = 1;
			wait(!txclk);
			wait(txclk); #1 we = 0;

			wait(!txclk);
			wait(txclk); #1 din = 9'hx;
		end
	endtask

endmodule
module testbench;


	reg txclk;
	reg reset;

	reg we;
	reg [8:0] din;
	reg parity;

	reg break;
	wire sout;
	wire empty;


	uart_tx uut (
		.txclk(txclk),
		.reset(reset),
		.we(we),
		.din(din),
		.parity(parity),
		.break(break),
		.sout(sout),
		.empty(empty)
	);


	always begin
		#271.27 txclk = 0;
		#271.27 txclk = 1;
	end

	initial begin

		$dumpfile("testbench.lxt");
		$dumpvars;


		txclk = 1;
		reset = 1;
		we = 0;
		din = 9'hx;
		parity = 0;
		break = 0;


		#250 reset = 0;


		send(0, 8'h64);
		wait(empty);


		parity = 1;
		send(1, 8'h64);
		wait(empty);


		send(0, 8'hA5);
		wait(empty);


		#250 break = 1;
		#20000 break = 0;


		#5000 $display("finished");
		$finish;
	end


	task send;
		input parity_bit;
		input [7:0] char;
		begin
			wait(!txclk);
			wait(txclk); #1 din = {parity_bit, char};

			wait(!txclk);
			wait(txclk); #1 we = 1;
			wait(!txclk);
			wait(txclk); #1 we = 0;

			wait(!txclk);
			wait(txclk); #1 din = 9'hx;
		end
	endtask

endmodule