data/full_repos/permissive/136510272/component/audio_pwm/audio_pwm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/component/audio_pwm/audio_pwm.v:19: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s REPLICATE generates 2 bits.\n                                                                                       : ... In instance audio_pwm\n        DeltaB = {SigmaLatch[9], SigmaLatch[9]} << (8);\n                                                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/component/audio_pwm/audio_pwm.v:22: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'vol\' generates 8 bits.\n                                                                                       : ... In instance audio_pwm\n        DeltaAdder = vol + DeltaB;\n                         ^\n%Error: Exiting due to 2 warning(s)\n'
module audio_pwm(

    input  wire       clk,
    input  wire [7:0] vol,
    output reg        pwm

);
       
    reg [9:0] DeltaAdder;
    reg [9:0] SigmaAdder;
    reg [9:0] SigmaLatch;
    reg [9:0] DeltaB;
    
    always @(SigmaLatch) 
        DeltaB = {SigmaLatch[9], SigmaLatch[9]} << (8);
    
    always @(vol or DeltaB) 
        DeltaAdder = vol + DeltaB;
        
    always @(DeltaAdder or SigmaLatch) 
        SigmaAdder = DeltaAdder + SigmaLatch;
        
    always @(posedge clk)
    begin
        SigmaLatch <= SigmaAdder;
        pwm <=  SigmaLatch[9];
    end

endmodule
module audio_pwm(

    input  wire       clk,
    input  wire [7:0] vol,
    output reg        pwm

);

       
    reg [9:0] DeltaAdder;
    reg [9:0] SigmaAdder;
    reg [9:0] SigmaLatch;
    reg [9:0] DeltaB;
    
    always @(SigmaLatch) 
        DeltaB = {SigmaLatch[9], SigmaLatch[9]} << (8);
    
    always @(vol or DeltaB) 
        DeltaAdder = vol + DeltaB;
        
    always @(DeltaAdder or SigmaLatch) 
        SigmaAdder = DeltaAdder + SigmaLatch;
        
    always @(posedge clk)
    begin
        SigmaLatch <= SigmaAdder;
        pwm <=  SigmaLatch[9];
    end

endmodule