data/full_repos/permissive/117851934/ddr_layout_V5/ip/old/SPI_Master.v
 line:62: before: "("
1: b"%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/old/SPI_Master.v:62: syntax error, unexpected '^', expecting ')'\n  always @ (posedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_word_send) begin\n                          ^\n%Error: Exiting due to 1 error(s)\n"
module SPI_Master ( miso, mosi, sclk, ss, data_bus, CS, addr, pro_clk, WR, RD);
  
  inout [7:0] data_bus;
  input pro_clk;
  input miso;
  input [1:0] addr;
  input CS;
  input WR, RD;
  
  output mosi;
  output sclk;
  output [7:0] ss;
  
  reg [7:0] shift_register;
  reg [7:0] txdata;
  reg [7:0] rxdata;
  reg [7:0] data_out;
  reg [7:0] data_out_en;
  reg [7:0] control, status;

  
  reg [7:0] clk_divide;
  reg [3:0] count;
  reg sclk;                        
  reg slave_cs;
  reg mosi;
  reg spi_word_send;
  
  wire [7:0] data_bus;
  wire [7:0] data_in = data_bus;
  wire spi_clk_gen;
  wire [2:0] divide_factor = control[2:0];
  wire CPOL = control[3];          
  wire CPHA = control[4];
  wire [7:0]ss; 
  
  

  assign ss[7] = ~( control[7] &  control[6] &  control[5] & (~slave_cs)); 
  assign ss[6] = ~( control[7] &  control[6] & ~control[5] & (~slave_cs)); 
  assign ss[5] = ~( control[7] & ~control[6] &  control[5] & (~slave_cs)); 
  assign ss[4] = ~( control[7] & ~control[6] & ~control[5] & (~slave_cs)); 
  assign ss[3] = ~(~control[7] &  control[6] &  control[5] & (~slave_cs)); 
  assign ss[2] = ~(~control[7] &  control[6] & ~control[5] & (~slave_cs)); 
  assign ss[1] = ~(~control[7] & ~control[6] &  control[5] & (~slave_cs)); 
  assign ss[0] = ~(~control[7] & ~control[6] & ~control[5] & (~slave_cs)); 
  

  assign spi_clk_gen = clk_divide[divide_factor];
  

  always @ (negedge pro_clk) begin
      clk_divide = clk_divide + 1;     
  end
  

  always @ (posedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_word_send) begin
      if (spi_word_send) begin
          shift_register[7:0] = txdata;
      end else begin 
          shift_register = shift_register << 1;
          shift_register[0] <= miso;
      end
  end
  

  always @ (negedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_word_send) begin
      if (spi_word_send) begin
          mosi = txdata[7];
      end else begin 
          mosi = shift_register[7];
      end
  end
  

  always @ (posedge slave_cs or posedge spi_word_send) begin
      if (spi_word_send) begin
          status[0] = 0;
      end else begin
        status = 8'h01;
      rxdata = shift_register;
    end
  end
     

  always @ (posedge pro_clk) begin
      if (spi_word_send) begin
          slave_cs <= 0;
      end else if ((count == 8) & ~(sclk ^ CPOL)) begin
          slave_cs <= 1;
      end    
  end
  

  always @ (posedge pro_clk) begin
      if (CS & WR & addr[1] & ~addr[0]) begin
          spi_word_send <=1;
      end else begin
          spi_word_send <=0;
      end
  end
  

  always @ (posedge spi_clk_gen) begin
      if (~slave_cs) begin
          sclk = ~sclk;
      end else if (~CPOL) begin
          sclk = 0; 
      end else begin
          sclk = 1;
      end
  end
  

  always @ (posedge sclk or posedge slave_cs) begin
      if (slave_cs) begin
          count = 0;
      end else begin   
          count = count + 1;
      end
  end
  

  always @ (posedge pro_clk) begin
      if (CS) begin
          case (addr) 
          2'b00 : if (WR) control <= data_in;
          2'b01 : if (RD) data_out <= status;
        2'b10 : if (WR) txdata <= data_in;
        2'b11 : if (RD) data_out <= rxdata;
          endcase
      end
  end
  

  always @ (RD or data_out) begin
      if (RD) 
      data_out_en = data_out;
      else
      data_out_en = 8'bz;
  end
  
  assign data_bus = data_out_en;
  
  initial 
  begin
      mosi = 0;

      control = 0;
      count = 0;
      slave_cs = 1;
      txdata = 0;
      rxdata = 0;
      clk_divide = 0;
      data_out = 0;
  end
  
  endmodule
module SPI_Master ( miso, mosi, sclk, ss, data_bus, CS, addr, pro_clk, WR, RD);

  
  inout [7:0] data_bus;
  input pro_clk;
  input miso;
  input [1:0] addr;
  input CS;
  input WR, RD;
  
  output mosi;
  output sclk;
  output [7:0] ss;
  
  reg [7:0] shift_register;
  reg [7:0] txdata;
  reg [7:0] rxdata;
  reg [7:0] data_out;
  reg [7:0] data_out_en;
  reg [7:0] control, status;

  
  reg [7:0] clk_divide;
  reg [3:0] count;
  reg sclk;                        
  reg slave_cs;
  reg mosi;
  reg spi_word_send;
  
  wire [7:0] data_bus;
  wire [7:0] data_in = data_bus;
  wire spi_clk_gen;
  wire [2:0] divide_factor = control[2:0];
  wire CPOL = control[3];          
  wire CPHA = control[4];
  wire [7:0]ss; 
  
  

  assign ss[7] = ~( control[7] &  control[6] &  control[5] & (~slave_cs)); 
  assign ss[6] = ~( control[7] &  control[6] & ~control[5] & (~slave_cs)); 
  assign ss[5] = ~( control[7] & ~control[6] &  control[5] & (~slave_cs)); 
  assign ss[4] = ~( control[7] & ~control[6] & ~control[5] & (~slave_cs)); 
  assign ss[3] = ~(~control[7] &  control[6] &  control[5] & (~slave_cs)); 
  assign ss[2] = ~(~control[7] &  control[6] & ~control[5] & (~slave_cs)); 
  assign ss[1] = ~(~control[7] & ~control[6] &  control[5] & (~slave_cs)); 
  assign ss[0] = ~(~control[7] & ~control[6] & ~control[5] & (~slave_cs)); 
  

  assign spi_clk_gen = clk_divide[divide_factor];
  

  always @ (negedge pro_clk) begin
      clk_divide = clk_divide + 1;     
  end
  

  always @ (posedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_word_send) begin
      if (spi_word_send) begin
          shift_register[7:0] = txdata;
      end else begin 
          shift_register = shift_register << 1;
          shift_register[0] <= miso;
      end
  end
  

  always @ (negedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_word_send) begin
      if (spi_word_send) begin
          mosi = txdata[7];
      end else begin 
          mosi = shift_register[7];
      end
  end
  

  always @ (posedge slave_cs or posedge spi_word_send) begin
      if (spi_word_send) begin
          status[0] = 0;
      end else begin
        status = 8'h01;
      rxdata = shift_register;
    end
  end
     

  always @ (posedge pro_clk) begin
      if (spi_word_send) begin
          slave_cs <= 0;
      end else if ((count == 8) & ~(sclk ^ CPOL)) begin
          slave_cs <= 1;
      end    
  end
  

  always @ (posedge pro_clk) begin
      if (CS & WR & addr[1] & ~addr[0]) begin
          spi_word_send <=1;
      end else begin
          spi_word_send <=0;
      end
  end
  

  always @ (posedge spi_clk_gen) begin
      if (~slave_cs) begin
          sclk = ~sclk;
      end else if (~CPOL) begin
          sclk = 0; 
      end else begin
          sclk = 1;
      end
  end
  

  always @ (posedge sclk or posedge slave_cs) begin
      if (slave_cs) begin
          count = 0;
      end else begin   
          count = count + 1;
      end
  end
  

  always @ (posedge pro_clk) begin
      if (CS) begin
          case (addr) 
          2'b00 : if (WR) control <= data_in;
          2'b01 : if (RD) data_out <= status;
        2'b10 : if (WR) txdata <= data_in;
        2'b11 : if (RD) data_out <= rxdata;
          endcase
      end
  end
  

  always @ (RD or data_out) begin
      if (RD) 
      data_out_en = data_out;
      else
      data_out_en = 8'bz;
  end
  
  assign data_bus = data_out_en;
  
  initial 
  begin
      mosi = 0;

      control = 0;
      count = 0;
      slave_cs = 1;
      txdata = 0;
      rxdata = 0;
      clk_divide = 0;
      data_out = 0;
  end
  
  endmodule