data/full_repos/permissive/143278/ivltests/enum_ports.v
 line:22: before: "typedef"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/enum_ports.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/enum_ports.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/enum_ports.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_unit();
t_var var_in, var_out;
reg result;

enum_ports dut(var_in, var_out, result);

initial begin
    #1;

    if(var_out !== var_presence) begin
        $display("FAILED 1");
        $finish();
    end

    var_in = var_1;
    #1;
    if(result !== 1'b0) begin
        $display("FAILED 2");
        $finish();
    end

    var_in = var_rst;
    #1
    if(result !== 1'b1) begin
        $display("FAILED 3");
        $finish();
    end

    $display("PASSED");
end

endmodule
module test_unit();

t_var var_in, var_out;
reg result;

enum_ports dut(var_in, var_out, result);

initial begin
    #1;

    if(var_out !== var_presence) begin
        $display("FAILED 1");
        $finish();
    end

    var_in = var_1;
    #1;
    if(result !== 1'b0) begin
        $display("FAILED 2");
        $finish();
    end

    var_in = var_rst;
    #1
    if(result !== 1'b1) begin
        $display("FAILED 3");
        $finish();
    end

    $display("PASSED");
end

endmodule