data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v
 line:21: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  repeat(4) #10 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:34: syntax error, unexpected \'@\'\n  @(negedge reset);\n  ^\n%Error: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:37: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n   #1 $display("input=%h, output=%h, output_exp=%h, v=%b, v_exp=%b, ph_sel=%b, ph_sel_exp=%b",\n   ^\n%Error: data/full_repos/permissive/116308238/unit_tests/ph_finder_tb.v:41: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ph_finder_tb;
	reg clk, reset, din_valid;
	reg [15:0] din;
	wire [31:0] dout;
	wire dout_valid, ph_select;

	integer fd, status;
	reg [31:0] d_exp;
	reg v_exp, ph_exp;

	ph_finder DUT(clk, reset, din, din_valid, dout, dout_valid, ph_select);


	initial begin
		clk = 0; reset = 1;
		repeat(4) #10 clk = ~clk;
		reset = 0;
		forever #10 clk = ~clk;
	end


	initial begin
		fd = $fopen("ph_finder_testvec.txt", "r");
	end


	initial begin
		din = 0; din_valid = 1;
		@(negedge reset);
		while(!$feof(fd)) begin
			status = $fscanf(fd, "%h, %h, %h, %h, %h\n", din, din_valid, d_exp, v_exp, ph_exp);
			@(posedge clk);
			#1 $display("input=%h, output=%h, output_exp=%h, v=%b, v_exp=%b, ph_sel=%b, ph_sel_exp=%b",
				din, dout, d_exp, dout_valid, v_exp, ph_select, ph_exp);
		end
		@(posedge clk);
		$fclose(fd);
		$finish;
	end
endmodule
module ph_finder_tb;

	reg clk, reset, din_valid;
	reg [15:0] din;
	wire [31:0] dout;
	wire dout_valid, ph_select;

	integer fd, status;
	reg [31:0] d_exp;
	reg v_exp, ph_exp;

	ph_finder DUT(clk, reset, din, din_valid, dout, dout_valid, ph_select);


	initial begin
		clk = 0; reset = 1;
		repeat(4) #10 clk = ~clk;
		reset = 0;
		forever #10 clk = ~clk;
	end


	initial begin
		fd = $fopen("ph_finder_testvec.txt", "r");
	end


	initial begin
		din = 0; din_valid = 1;
		@(negedge reset);
		while(!$feof(fd)) begin
			status = $fscanf(fd, "%h, %h, %h, %h, %h\n", din, din_valid, d_exp, v_exp, ph_exp);
			@(posedge clk);
			#1 $display("input=%h, output=%h, output_exp=%h, v=%b, v_exp=%b, ph_sel=%b, ph_sel_exp=%b",
				din, dout, d_exp, dout_valid, v_exp, ph_select, ph_exp);
		end
		@(posedge clk);
		$fclose(fd);
		$finish;
	end
endmodule