data/full_repos/permissive/167962127/noise_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167962127/noise_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #10 r_clk = !r_clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/167962127/noise_tb.v:8: Cannot find file containing module: \'noise\'\n  noise UUT(\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/noise\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/noise.v\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/noise.sv\n             noise\n             noise.v\n             noise.sv\n             obj_dir/noise\n             obj_dir/noise.v\n             obj_dir/noise.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module noise_tb();
  
  reg r_clk = 0;
  wire [15:0] w_data;

  noise UUT(
    .i_clk(r_clk),
    .o_data(w_data)
  );

  always begin
    #10 r_clk = !r_clk;
  end

endmodule
module noise_tb();

  
  reg r_clk = 0;
  wire [15:0] w_data;

  noise UUT(
    .i_clk(r_clk),
    .o_data(w_data)
  );

  always begin
    #10 r_clk = !r_clk;
  end

endmodule