data/full_repos/permissive/143278/ivltests/br_gh316b.v
 line:8: before: "="
1: b'%Error: data/full_repos/permissive/143278/ivltests/br_gh316b.v:31: Unsupported or unknown PLI call: $monitor\n  $monitor($time,,EN1,,I1,,EN2,,I2,,O);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/br_gh316b.v:31: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  $monitor($time,,EN1,,I1,,EN2,,I2,,O);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #4;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #0 if (O !== 0) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #0 if (O !== 0) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #0 if (O !== 1) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #0 if (O !== 1) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #0 if (O !== 0) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #0 if (O !== 0) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #0 if (O !== 1) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #0 if (O !== 1) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316b.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 2 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

reg     EN1;
reg     EN2;
reg     I1;
reg     I2;
tri     O;

pulldown(O);

dut dut(EN1, I1, O, EN2, I2, O);

reg failed = 0;

initial begin
  $monitor($time,,EN1,,I1,,EN2,,I2,,O);
  EN1 = 0;
  EN2 = 0;
  #4;
  #0 if (O !== 0) failed = 1;
  I1 = 1;
  I2 = 1;
  #1;
  EN1 = 1;
  #3;
  #0 if (O !== 0) failed = 1;
  #1;
  #0 if (O !== 1) failed = 1;
  I1 = 0;
  #1;
  #0 if (O !== 1) failed = 1;
  #1;
  #0 if (O !== 0) failed = 1;
  EN1 = 0;
  EN2 = 1;
  #3;
  #0 if (O !== 0) failed = 1;
  #1;
  #0 if (O !== 1) failed = 1;
  I2 = 0;
  #2;
  #0 if (O !== 1) failed = 1;
  #1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module test();


reg     EN1;
reg     EN2;
reg     I1;
reg     I2;
tri     O;

pulldown(O);

dut dut(EN1, I1, O, EN2, I2, O);

reg failed = 0;

initial begin
  $monitor($time,,EN1,,I1,,EN2,,I2,,O);
  EN1 = 0;
  EN2 = 0;
  #4;
  #0 if (O !== 0) failed = 1;
  I1 = 1;
  I2 = 1;
  #1;
  EN1 = 1;
  #3;
  #0 if (O !== 0) failed = 1;
  #1;
  #0 if (O !== 1) failed = 1;
  I1 = 0;
  #1;
  #0 if (O !== 1) failed = 1;
  #1;
  #0 if (O !== 0) failed = 1;
  EN1 = 0;
  EN2 = 1;
  #3;
  #0 if (O !== 0) failed = 1;
  #1;
  #0 if (O !== 1) failed = 1;
  I2 = 0;
  #2;
  #0 if (O !== 1) failed = 1;
  #1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule