data/full_repos/permissive/13201424/vlog/ps2_if.v
data/verilator_xmls/f329a4c6-ca9a-458a-909b-9d5f2c79364a.xml
module ps2_if(
	input clk,
	input rst,
	input [4:0] btn,
	

	input ps2_k_clk_in,
	input ps2_k_d_in,
	input ps2_m_clk_in,
	input ps2_m_d_in,
	

	output reg ps2_k_act_out,
	output reg ps2_m_act_out,
	
	output reg wr_en_out,
	output reg [63:0] wr_d_out,
	input wr_full_in
);

	localparam COUNT_SIZE = 16;


	reg [4:0] btn_r;
	reg [COUNT_SIZE:0] count;
	


	reg btn_rdy;
	
	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			count <= 0;
			btn_r <= 0;
			btn_rdy <= 0;
			
		end else begin
			if ((btn != btn_r) && (count[COUNT_SIZE])) begin
				btn_r <= btn;
				btn_rdy <= 1'b1;
				count <= 0;
			end else begin
				btn_rdy <= 1'b0;
				if (!count[COUNT_SIZE])
					count <= count + 1'd1;
			end
		end
	end
	















































	
	reg [3:0] ps2_m_bit_count;
	reg [1:0] ps2_m_frame_count;
	reg [7:0] ps2_m_clk_last;
	reg [23:0] ps2_m_r;
	reg ps2_m_rdy;
	
	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			ps2_m_bit_count <= 0;
			ps2_m_frame_count <= 0;
			ps2_m_clk_last <= 0;
			ps2_m_r <= 0;
			ps2_m_rdy <= 0;
			ps2_m_act_out <= 0;
			
		end else begin
		
			ps2_m_clk_last <= {ps2_m_clk_last[6:0], ps2_m_clk_in};
			
			if (ps2_m_clk_last == 8'hf0) begin

				case (ps2_m_bit_count)
					4'd0: begin

						ps2_m_bit_count <= (ps2_m_d_in) ? 4'd0 : 4'd1;
						ps2_m_rdy <= 1'b0;
					end
					4'd9: begin


						ps2_m_bit_count <= 4'd10;
						ps2_m_rdy <= 1'b0;
					end
					4'd10: begin

						ps2_m_bit_count <= (ps2_m_d_in) ? 4'd0 : 4'd10;


						if (ps2_m_frame_count == 2'd2) begin
							ps2_m_rdy <= 1'b1;
							ps2_m_frame_count <= 0;
						end else begin
							ps2_m_rdy <= 1'b0;
							ps2_m_frame_count <= ps2_m_frame_count + 1'd1;
						end
						ps2_m_act_out <= 1'b0;
					end
					default: begin


						ps2_m_r <= {ps2_m_d_in, ps2_m_r[23:1]};
						ps2_m_bit_count <= ps2_m_bit_count + 1'd1;
						ps2_m_rdy <= 1'b0;
						ps2_m_act_out <= 1'b1;
					end
				endcase
			end else begin

				ps2_m_rdy <= 1'b0;
			end
		end
	end
	
	reg [3:0] ps2_k_bit_count;
	reg [7:0] ps2_k_clk_last;
	reg [31:0] ps2_k_r;
	reg ps2_k_rdy;
	
	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			ps2_k_bit_count <= 0;
			ps2_k_clk_last <= 0;
			ps2_k_r <= 0;
			ps2_k_rdy <= 0;
			ps2_k_act_out <= 0;
			
		end else begin
		
			ps2_k_clk_last <= {ps2_k_clk_last[6:0], ps2_k_clk_in};
			
			if (ps2_k_rdy) begin
				ps2_k_r <= 0;
				ps2_k_rdy <= 0;
			end else if (ps2_k_clk_last == 8'hf0) begin

				case (ps2_k_bit_count)
					4'd0: begin

						ps2_k_bit_count <= (ps2_k_d_in) ? 4'd0 : 4'd1;
						ps2_k_rdy <= 1'b0;
					end
					4'd9: begin


						ps2_k_bit_count <= 4'd10;
						ps2_k_rdy <= 1'b0;
					end
					4'd10: begin

						ps2_k_bit_count <= (ps2_k_d_in) ? 4'd0 : 4'd10;



						ps2_k_rdy <= !ps2_k_r[31];
						ps2_k_act_out <= 1'b0;
					end
					default: begin


						ps2_k_r <= {ps2_k_d_in, ps2_k_r[31:1]};
						ps2_k_bit_count <= ps2_k_bit_count + 1'd1;
						ps2_k_rdy <= 1'b0;
						ps2_k_act_out <= 1'b1;
					end
				endcase
			end else begin

				ps2_k_rdy <= 1'b0;
			end
		end
	end
	





	
	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			wr_en_out <= 0;
			wr_d_out <= 0;
		end else begin
			if (btn_rdy) begin
				wr_en_out <= 1;
				wr_d_out <= {59'h0, btn};
			end else if (ps2_k_rdy) begin
				wr_en_out <= 1;

				wr_d_out <= {32'h0, ps2_k_r[7:0], ps2_k_r[15:8], ps2_k_r[23:16], ps2_k_r[31:24]};
			end else if (ps2_m_rdy) begin
				wr_en_out <= 1;

				wr_d_out <= {40'h0, ps2_m_r[7:0], ps2_m_r[15:8], ps2_m_r[23:16]};
			end else begin
				wr_en_out <= 0;
				wr_d_out <= 0;
			end
		end
	end
	
endmodule
module ps2_if(
	input clk,
	input rst,
	input [4:0] btn,
	

	input ps2_k_clk_in,
	input ps2_k_d_in,
	input ps2_m_clk_in,
	input ps2_m_d_in,
	

	output reg ps2_k_act_out,
	output reg ps2_m_act_out,
	
	output reg wr_en_out,
	output reg [63:0] wr_d_out,
	input wr_full_in
);


	localparam COUNT_SIZE = 16;


	reg [4:0] btn_r;
	reg [COUNT_SIZE:0] count;
	


	reg btn_rdy;
	
	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			count <= 0;
			btn_r <= 0;
			btn_rdy <= 0;
			
		end else begin
			if ((btn != btn_r) && (count[COUNT_SIZE])) begin
				btn_r <= btn;
				btn_rdy <= 1'b1;
				count <= 0;
			end else begin
				btn_rdy <= 1'b0;
				if (!count[COUNT_SIZE])
					count <= count + 1'd1;
			end
		end
	end
	















































	
	reg [3:0] ps2_m_bit_count;
	reg [1:0] ps2_m_frame_count;
	reg [7:0] ps2_m_clk_last;
	reg [23:0] ps2_m_r;
	reg ps2_m_rdy;
	
	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			ps2_m_bit_count <= 0;
			ps2_m_frame_count <= 0;
			ps2_m_clk_last <= 0;
			ps2_m_r <= 0;
			ps2_m_rdy <= 0;
			ps2_m_act_out <= 0;
			
		end else begin
		
			ps2_m_clk_last <= {ps2_m_clk_last[6:0], ps2_m_clk_in};
			
			if (ps2_m_clk_last == 8'hf0) begin

				case (ps2_m_bit_count)
					4'd0: begin

						ps2_m_bit_count <= (ps2_m_d_in) ? 4'd0 : 4'd1;
						ps2_m_rdy <= 1'b0;
					end
					4'd9: begin


						ps2_m_bit_count <= 4'd10;
						ps2_m_rdy <= 1'b0;
					end
					4'd10: begin

						ps2_m_bit_count <= (ps2_m_d_in) ? 4'd0 : 4'd10;


						if (ps2_m_frame_count == 2'd2) begin
							ps2_m_rdy <= 1'b1;
							ps2_m_frame_count <= 0;
						end else begin
							ps2_m_rdy <= 1'b0;
							ps2_m_frame_count <= ps2_m_frame_count + 1'd1;
						end
						ps2_m_act_out <= 1'b0;
					end
					default: begin


						ps2_m_r <= {ps2_m_d_in, ps2_m_r[23:1]};
						ps2_m_bit_count <= ps2_m_bit_count + 1'd1;
						ps2_m_rdy <= 1'b0;
						ps2_m_act_out <= 1'b1;
					end
				endcase
			end else begin

				ps2_m_rdy <= 1'b0;
			end
		end
	end
	
	reg [3:0] ps2_k_bit_count;
	reg [7:0] ps2_k_clk_last;
	reg [31:0] ps2_k_r;
	reg ps2_k_rdy;
	
	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			ps2_k_bit_count <= 0;
			ps2_k_clk_last <= 0;
			ps2_k_r <= 0;
			ps2_k_rdy <= 0;
			ps2_k_act_out <= 0;
			
		end else begin
		
			ps2_k_clk_last <= {ps2_k_clk_last[6:0], ps2_k_clk_in};
			
			if (ps2_k_rdy) begin
				ps2_k_r <= 0;
				ps2_k_rdy <= 0;
			end else if (ps2_k_clk_last == 8'hf0) begin

				case (ps2_k_bit_count)
					4'd0: begin

						ps2_k_bit_count <= (ps2_k_d_in) ? 4'd0 : 4'd1;
						ps2_k_rdy <= 1'b0;
					end
					4'd9: begin


						ps2_k_bit_count <= 4'd10;
						ps2_k_rdy <= 1'b0;
					end
					4'd10: begin

						ps2_k_bit_count <= (ps2_k_d_in) ? 4'd0 : 4'd10;



						ps2_k_rdy <= !ps2_k_r[31];
						ps2_k_act_out <= 1'b0;
					end
					default: begin


						ps2_k_r <= {ps2_k_d_in, ps2_k_r[31:1]};
						ps2_k_bit_count <= ps2_k_bit_count + 1'd1;
						ps2_k_rdy <= 1'b0;
						ps2_k_act_out <= 1'b1;
					end
				endcase
			end else begin

				ps2_k_rdy <= 1'b0;
			end
		end
	end
	





	
	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			wr_en_out <= 0;
			wr_d_out <= 0;
		end else begin
			if (btn_rdy) begin
				wr_en_out <= 1;
				wr_d_out <= {59'h0, btn};
			end else if (ps2_k_rdy) begin
				wr_en_out <= 1;

				wr_d_out <= {32'h0, ps2_k_r[7:0], ps2_k_r[15:8], ps2_k_r[23:16], ps2_k_r[31:24]};
			end else if (ps2_m_rdy) begin
				wr_en_out <= 1;

				wr_d_out <= {40'h0, ps2_m_r[7:0], ps2_m_r[15:8], ps2_m_r[23:16]};
			end else begin
				wr_en_out <= 0;
				wr_d_out <= 0;
			end
		end
	end
	
endmodule