data/full_repos/permissive/143278/ivltests/pr710.v
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr710.v:9: Unsupported: wait statements\n wait (foo == idx) begin\n ^~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [5:0] idx, mask;
   wire [5:0] foo = idx & mask;

   initial begin
      mask = 5'h1f;
      for (idx = 0 ;  idx < 5 ;  idx = idx+1)
	wait (foo == idx) begin
	   $display("foo=%d, idx=%d", foo, idx);
	   if (foo !== idx) begin
	      $display("FAILED");
	      $finish;
	   end
	end

      $display("PASSED");
   end

endmodule
module main;


   reg [5:0] idx, mask;
   wire [5:0] foo = idx & mask;

   initial begin
      mask = 5'h1f;
      for (idx = 0 ;  idx < 5 ;  idx = idx+1)
	wait (foo == idx) begin
	   $display("foo=%d, idx=%d", foo, idx);
	   if (foo !== idx) begin
	      $display("FAILED");
	      $finish;
	   end
	end

      $display("PASSED");
   end

endmodule