data/full_repos/permissive/143278/ivltests/function3.11D.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/function3.11D.v:39: Unsupported: Ignoring delay on this delayed statement.\n    # 1 ;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/function3.11D.v:47: Unsupported: Ignoring delay on this delayed statement.\n    # 1 ;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/function3.11D.v:29: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'in1\' generates 32 bits.\n                                                                             : ... In instance main\n  myfunc = in1;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/function3.11D.v:33: Operator FUNCREF \'myfunc\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'val2\' generates 4 bits.\n                                                                             : ... In instance main\nassign val1 = myfunc(val2);\n              ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/function3.11D.v:46: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h8\' generates 32 bits.\n                                                                             : ... In instance main\n    val2 = 32\'h8;\n         ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ();

reg error;
reg [3:0] val2;


function [3:0] myfunc ;
  input [31:0] in1 ;
  myfunc = in1;
endfunction

wire [3:0] val1;
assign val1 = myfunc(val2);

initial
  begin
    error = 0;
    val2 = 4'h0;
    # 1 ;
    if(val1 !== 4'b0)
      begin
        $display("FAILED - function3.11D - function within continuous assign(1)");
        error = 1;
      end

    val2 = 32'h8;
    # 1 ;
    if(val1 !== val2)
      begin
        $display("FAILED - function3.11D - function within continuous assign(2)");
        error = 1;
      end

    if(error == 0)
       $display("PASSED");
  end

endmodule
module main ();


reg error;
reg [3:0] val2;


function [3:0] myfunc ;
  input [31:0] in1 ;
  myfunc = in1;
endfunction

wire [3:0] val1;
assign val1 = myfunc(val2);

initial
  begin
    error = 0;
    val2 = 4'h0;
    # 1 ;
    if(val1 !== 4'b0)
      begin
        $display("FAILED - function3.11D - function within continuous assign(1)");
        error = 1;
      end

    val2 = 32'h8;
    # 1 ;
    if(val1 !== val2)
      begin
        $display("FAILED - function3.11D - function within continuous assign(2)");
        error = 1;
      end

    if(error == 0)
       $display("PASSED");
  end

endmodule