data/full_repos/permissive/168228981/dec.v
data/verilator_xmls/3ffad89e-16f2-46df-8a89-0c0245dd6d2a.xml
module dec(decin,seg0,seg1);
input [4:0] decin;
output reg [3:0] seg0;
output reg [3:0] seg1;


   reg [12:0] shift;
   integer i;
   
   always @(decin)
   begin

      shift[12:5] = 0;
      shift[4:0] = decin;
      

      for (i=0; i<5; i=i+1) begin
         if (shift[8:5] >= 5)
            shift[8:5] = shift[8:5] + 3;
            
         if (shift[12:9] >= 5)
            shift[12:9] = shift[12:9] + 3;                
         

         shift = shift << 1;
      end
      

      seg1 = shift[12:9];
      seg0 = shift[8:5];
  end
endmodule
module dec(decin,seg0,seg1);

input [4:0] decin;
output reg [3:0] seg0;
output reg [3:0] seg1;


   reg [12:0] shift;
   integer i;
   
   always @(decin)
   begin

      shift[12:5] = 0;
      shift[4:0] = decin;
      

      for (i=0; i<5; i=i+1) begin
         if (shift[8:5] >= 5)
            shift[8:5] = shift[8:5] + 3;
            
         if (shift[12:9] >= 5)
            shift[12:9] = shift[12:9] + 3;                
         

         shift = shift << 1;
      end
      

      seg1 = shift[12:9];
      seg0 = shift[8:5];
  end
endmodule