data/full_repos/permissive/147265957/src/maccumulator.v
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data/verilator_xmls/367b01e9-0027-489d-a1cf-40f31b4ab502.xml
module maccumulator (
    clk, lock, rst, onesig, tensig, moneyv
);
    input clk;
    input rst;
    input onesig;
    input tensig;
    input lock;
    output reg [7:0] moneyv;
    initial moneyv = 0;
    reg lastonesig, lasttensig;
    initial lastonesig = 0;
    initial lasttensig = 0;
    always @(posedge clk) begin
        if(rst) moneyv <= 0;
        else if(onesig & ~lastonesig & ~tensig & ~rst & ~lock) moneyv <= moneyv + 2;
        else if(tensig & ~lasttensig & ~onesig & ~rst & ~lock) moneyv <= moneyv + 20;
        lastonesig = onesig;
        lasttensig = tensig;
    end
endmodule
module maccumulator (
    clk, lock, rst, onesig, tensig, moneyv
);

    input clk;
    input rst;
    input onesig;
    input tensig;
    input lock;
    output reg [7:0] moneyv;
    initial moneyv = 0;
    reg lastonesig, lasttensig;
    initial lastonesig = 0;
    initial lasttensig = 0;
    always @(posedge clk) begin
        if(rst) moneyv <= 0;
        else if(onesig & ~lastonesig & ~tensig & ~rst & ~lock) moneyv <= moneyv + 2;
        else if(tensig & ~lasttensig & ~onesig & ~rst & ~lock) moneyv <= moneyv + 20;
        lastonesig = onesig;
        lasttensig = tensig;
    end
endmodule