data/full_repos/permissive/13953309/NW_fifo.v
 line:103: before: "typedef"
1: b"%Error: data/full_repos/permissive/13953309/NW_fifo.v:110: syntax error, unexpected IDENTIFIER, expecting '.' or ';'\ntypedef flit_t fifo_elements_t;\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:134: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:135: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out, second_data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:275: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:276: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out, second_data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:513: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:514: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:515: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t second_data_out;\n                             ^~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module NW_fifo_v (push, pop, data_in, data_out, second_data_out, flags, clk, rst_n);
   

   parameter init_fifo_contents = 0;


  


   parameter size = 8;

   parameter output_reg = 1;

   parameter input_reg = 0;

   parameter low_power = 0;

   parameter generate_second_data_out = 1;
   
   input     push, pop;
   output    fifov_flags_t flags;
   input     fifo_elements_t data_in;
   output    fifo_elements_t data_out, second_data_out;
   input     clk, rst_n;

   fifo_elements_t second;
   
   logic is_push, select_bypass, fifo_push, fifo_pop;
   fifo_elements_t in_reg, fifo_data_out;

   generate
   if (input_reg==0) begin
   
      fifo_r #(.init_fifo_contents(init_fifo_contents),

	       .size(size),
	       .output_reg(output_reg),
	       .low_power(low_power)) fifo_r
	(push, pop, data_in, data_out, second, clk, rst_n);

   end else if (input_reg==1) begin




      fifo_r #(.init_fifo_contents(init_fifo_contents),

	       .size(size),
	       .output_reg(output_reg),
	       .low_power(low_power)) fifo_r
	(fifo_push, fifo_pop, data_in, data_out, second, clk, rst_n);
      
   end else if (input_reg==2) begin 




      fifo_r #(.init_fifo_contents(init_fifo_contents),

	       .size(size),
	       .output_reg(output_reg),
	       .low_power(low_power)) fifo_r
	(fifo_push, fifo_pop, in_reg, fifo_data_out, second, clk, rst_n);
      



      always@(posedge clk) 
	begin
           if (!rst_n) begin
              in_reg<='0;
           end else begin
	      if (push) begin
		in_reg<=data_in;
	      end else
		in_reg<='0;
	   end
	end
      
      assign data_out = (select_bypass) ? in_reg : fifo_data_out;
   end 
   
   endgenerate

   generate



      if (!low_power && !(output_reg && input_reg!=0)) begin

	 assign fifo_push = is_push;
	 assign fifo_pop = pop;
      end else begin


	 assign fifo_push = is_push && !(select_bypass && pop);

	 assign fifo_pop = pop && !select_bypass;
      end
   endgenerate
   
   always@(posedge clk) begin

      if (!rst_n) begin
	 is_push <= 1'b0;
	 select_bypass <= 1'b1;
      end else begin
	 is_push <= push;

	 select_bypass <= flags.empty || (flags.nearly_empty && pop);
      end
   end
   

   fifo_flags #(.size(size), 
		.init_fifo_contents(init_fifo_contents)) genflags 
     (push, pop, flags, clk, rst_n);


   generate
      if (generate_second_data_out) begin
	 assign second_data_out = second;
      end else begin
	 assign second_data_out = 'x;
      end
   endgenerate
endmodule
module NW_fifo_v (push, pop, data_in, data_out, second_data_out, flags, clk, rst_n);

   

   parameter init_fifo_contents = 0;


  


   parameter size = 8;

   parameter output_reg = 1;

   parameter input_reg = 0;

   parameter low_power = 0;

   parameter generate_second_data_out = 1;
   
   input     push, pop;
   output    fifov_flags_t flags;
   input     fifo_elements_t data_in;
   output    fifo_elements_t data_out, second_data_out;
   input     clk, rst_n;

   fifo_elements_t second;
   
   logic is_push, select_bypass, fifo_push, fifo_pop;
   fifo_elements_t in_reg, fifo_data_out;

   generate
   if (input_reg==0) begin
   
      fifo_r #(.init_fifo_contents(init_fifo_contents),

	       .size(size),
	       .output_reg(output_reg),
	       .low_power(low_power)) fifo_r
	(push, pop, data_in, data_out, second, clk, rst_n);

   end else if (input_reg==1) begin




      fifo_r #(.init_fifo_contents(init_fifo_contents),

	       .size(size),
	       .output_reg(output_reg),
	       .low_power(low_power)) fifo_r
	(fifo_push, fifo_pop, data_in, data_out, second, clk, rst_n);
      
   end else if (input_reg==2) begin 




      fifo_r #(.init_fifo_contents(init_fifo_contents),

	       .size(size),
	       .output_reg(output_reg),
	       .low_power(low_power)) fifo_r
	(fifo_push, fifo_pop, in_reg, fifo_data_out, second, clk, rst_n);
      



      always@(posedge clk) 
	begin
           if (!rst_n) begin
              in_reg<='0;
           end else begin
	      if (push) begin
		in_reg<=data_in;
	      end else
		in_reg<='0;
	   end
	end
      
      assign data_out = (select_bypass) ? in_reg : fifo_data_out;
   end 
   
   endgenerate

   generate



      if (!low_power && !(output_reg && input_reg!=0)) begin

	 assign fifo_push = is_push;
	 assign fifo_pop = pop;
      end else begin


	 assign fifo_push = is_push && !(select_bypass && pop);

	 assign fifo_pop = pop && !select_bypass;
      end
   endgenerate
   
   always@(posedge clk) begin

      if (!rst_n) begin
	 is_push <= 1'b0;
	 select_bypass <= 1'b1;
      end else begin
	 is_push <= push;

	 select_bypass <= flags.empty || (flags.nearly_empty && pop);
      end
   end
   

   fifo_flags #(.size(size), 
		.init_fifo_contents(init_fifo_contents)) genflags 
     (push, pop, flags, clk, rst_n);


   generate
      if (generate_second_data_out) begin
	 assign second_data_out = second;
      end else begin
	 assign second_data_out = 'x;
      end
   endgenerate
endmodule