data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:3: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/src/cpu/core/stage/id,data/full_repos/permissive/201275379/bus.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/id,data/full_repos/permissive/201275379/bus.v.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/id,data/full_repos/permissive/201275379/bus.v.sv\n             bus.v\n             bus.v.v\n             bus.v.sv\n             obj_dir/bus.v\n             obj_dir/bus.v.v\n             obj_dir/bus.v.sv\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:4: Cannot find include file: opcode.v\n`include "opcode.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:5: Cannot find include file: cp0.v\n`include "cp0.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:10: Define or directive not defined: \'`INST_OP_BUS\'\n  input   [`INST_OP_BUS]  op,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input   [`INST_OP_BUS]  op,\n                       ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:11: Define or directive not defined: \'`REG_ADDR_BUS\'\n  input   [`REG_ADDR_BUS] rs,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:12: Define or directive not defined: \'`REG_ADDR_BUS\'\n  input   [`REG_ADDR_BUS] rd,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:13: Define or directive not defined: \'`CP0_SEL_BUS\'\n  input   [`CP0_SEL_BUS]  sel,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:18: Define or directive not defined: \'`CP0_ADDR_BUS\'\n  output  [`CP0_ADDR_BUS] cp0_addr\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:22: Define or directive not defined: \'`CP0_ADDR_BUS\'\n  reg[`CP0_ADDR_BUS] cp0_addr;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`CP0_ADDR_BUS] cp0_addr;\n                   ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:33: Define or directive not defined: \'`OP_CP0\'\n        `OP_CP0: begin\n        ^~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:34: Define or directive not defined: \'`CP0_MTC0\'\n          if (rs == `CP0_MTC0 && is_cp0) begin\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/CP0Gen.v:39: Define or directive not defined: \'`CP0_MFC0\'\n          else if (rs == `CP0_MFC0 && is_cp0) begin\n                         ^~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module CP0Gen(
  input                   rst,

  input   [`INST_OP_BUS]  op,
  input   [`REG_ADDR_BUS] rs,
  input   [`REG_ADDR_BUS] rd,
  input   [`CP0_SEL_BUS]  sel,
  input                   is_cp0,

  output                  cp0_read_flag,
  output                  cp0_write_flag,
  output  [`CP0_ADDR_BUS] cp0_addr
);

  reg cp0_read_flag, cp0_write_flag;
  reg[`CP0_ADDR_BUS] cp0_addr;


  always @(*) begin
    if (!rst) begin
      cp0_read_flag <= 0;
      cp0_write_flag <= 0;
      cp0_addr <= 0;
    end
    else begin
      case (op)
        `OP_CP0: begin
          if (rs == `CP0_MTC0 && is_cp0) begin
            cp0_read_flag <= 0;
            cp0_write_flag <= 1;
            cp0_addr <= {rd, sel};
          end
          else if (rs == `CP0_MFC0 && is_cp0) begin
            cp0_read_flag <= 1;
            cp0_write_flag <= 0;
            cp0_addr <= {rd, sel};
          end
          else begin
            cp0_read_flag <= 0;
            cp0_write_flag <= 0;
            cp0_addr <= 0;
          end
        end
        default: begin
          cp0_read_flag <= 0;
          cp0_write_flag <= 0;
          cp0_addr <= 0;
        end
      endcase
    end
  end

endmodule
module CP0Gen(
  input                   rst,

  input   [`INST_OP_BUS]  op,
  input   [`REG_ADDR_BUS] rs,
  input   [`REG_ADDR_BUS] rd,
  input   [`CP0_SEL_BUS]  sel,
  input                   is_cp0,

  output                  cp0_read_flag,
  output                  cp0_write_flag,
  output  [`CP0_ADDR_BUS] cp0_addr
);


  reg cp0_read_flag, cp0_write_flag;
  reg[`CP0_ADDR_BUS] cp0_addr;


  always @(*) begin
    if (!rst) begin
      cp0_read_flag <= 0;
      cp0_write_flag <= 0;
      cp0_addr <= 0;
    end
    else begin
      case (op)
        `OP_CP0: begin
          if (rs == `CP0_MTC0 && is_cp0) begin
            cp0_read_flag <= 0;
            cp0_write_flag <= 1;
            cp0_addr <= {rd, sel};
          end
          else if (rs == `CP0_MFC0 && is_cp0) begin
            cp0_read_flag <= 1;
            cp0_write_flag <= 0;
            cp0_addr <= {rd, sel};
          end
          else begin
            cp0_read_flag <= 0;
            cp0_write_flag <= 0;
            cp0_addr <= 0;
          end
        end
        default: begin
          cp0_read_flag <= 0;
          cp0_write_flag <= 0;
          cp0_addr <= 0;
        end
      endcase
    end
  end

endmodule