data/full_repos/permissive/169258653/multicycle/MIPS_multi_cycle_32bit/MIPS_multi_cycle_32bit.srcs/sources_1/new/MUX4.v
data/verilator_xmls/db671125-3dd4-4fde-8d18-3a3b259a60fe.xml
module MUX4 #(parameter WIDTH=8)
    (
    input [WIDTH-1:0] d00,d01,d10,d11,
    input [1:0] s,
    output reg [WIDTH-1:0] y
    );
    
    always@(*)
    begin
        case(s)
        2'b00:y<=d00;
        2'b01:y<=d01;
        2'b10:y<=d10;
        2'b11:y<=d11;
        endcase
    end
    
endmodule
module MUX4 #(parameter WIDTH=8)
    (
    input [WIDTH-1:0] d00,d01,d10,d11,
    input [1:0] s,
    output reg [WIDTH-1:0] y
    );

    
    always@(*)
    begin
        case(s)
        2'b00:y<=d00;
        2'b01:y<=d01;
        2'b10:y<=d10;
        2'b11:y<=d11;
        endcase
    end
    
endmodule