data/full_repos/permissive/127311496/src/v/CPU/Regs.v
1: b"%Error: data/full_repos/permissive/127311496/src/v/CPU/Regs.v:13: Cannot find file containing module: 'RAM32M'\n RAM32M U0[15:0] (.WCLK(clk), .WE(|rdAddr & ~stall),\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/v/CPU,data/full_repos/permissive/127311496/RAM32M\n             data/full_repos/permissive/127311496/src/v/CPU,data/full_repos/permissive/127311496/RAM32M.v\n             data/full_repos/permissive/127311496/src/v/CPU,data/full_repos/permissive/127311496/RAM32M.sv\n             RAM32M\n             RAM32M.v\n             RAM32M.sv\n             obj_dir/RAM32M\n             obj_dir/RAM32M.v\n             obj_dir/RAM32M.sv\n%Error: Exiting due to 1 error(s)\n"
module RegFile(
	input clk, input rst, input stall,
	input [4:0] rsAddr, input [4:0] rtAddr, input [4:0] rdAddr, input [4:0] rtAddrDelay,
	output [31:0] rs, output [31:0] rt, output [31:0] rtDelay, input [31:0] rd
);
	
	RAM32M U0[15:0] (.WCLK(clk), .WE(|rdAddr & ~stall),
        .ADDRA(rsAddr), .ADDRB(rtAddr), .ADDRC(rtAddrDelay), .ADDRD(rdAddr),
        .DIA(rd), .DIB(rd), .DIC(rd), .DID(rd),
        .DOA(rs), .DOB(rt), .DOC(rtDelay));
	
endmodule
module RegFile(
	input clk, input rst, input stall,
	input [4:0] rsAddr, input [4:0] rtAddr, input [4:0] rdAddr, input [4:0] rtAddrDelay,
	output [31:0] rs, output [31:0] rt, output [31:0] rtDelay, input [31:0] rd
);

	
	RAM32M U0[15:0] (.WCLK(clk), .WE(|rdAddr & ~stall),
        .ADDRA(rsAddr), .ADDRB(rtAddr), .ADDRC(rtAddrDelay), .ADDRD(rdAddr),
        .DIA(rd), .DIB(rd), .DIC(rd), .DID(rd),
        .DOA(rs), .DOB(rt), .DOC(rtDelay));
	
endmodule