data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:23: Unsupported or unknown PLI call: $fsdbDumpfile\n  $fsdbDumpfile("dual_clock_fifo");\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:24: Unsupported or unknown PLI call: $fsdbDumpvars\n  $fsdbDumpvars;\n  ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n   always #11000 slow_clk <= ~slow_clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n   always  #7000 fast_clk <= ~fast_clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n   initial #95000 rst <= 0;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n      #95000 rst = 0;\n      ^\n%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:96: Unsupported: fork statements\n      fork\n      ^~~~\n%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:102: Unsupported: fork statements\n      fork\n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n      #123 rst = 1\'b0;\n      ^\n%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:112: Unsupported: fork statements\n      fork\n      ^~~~\n%Error: data/full_repos/permissive/111393021/test/dual_clock_fifo_tb.v:118: Unsupported: fork statements\n      fork\n      ^~~~\n%Error: Exiting due to 6 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dual_clock_fifo_tb
  #(parameter data_width  = 16,
    parameter depth_width = 8);

	initial begin
		$fsdbDumpfile("dual_clock_fifo");
		$fsdbDumpvars;
	end	

   localparam DEPTH = 1<<depth_width;

   reg slow_clk = 1'b1;
   reg fast_clk = 1'b1;
   reg rst = 1'b1;

   reg 		 faster_write_clk = 1'b0;
   wire 	 wr_clk;
   wire 	 rd_clk;


   always #11000 slow_clk <= ~slow_clk;
   always  #7000 fast_clk <= ~fast_clk;
   initial #95000 rst <= 0;

   assign wr_clk = faster_write_clk ? fast_clk : slow_clk;
   assign rd_clk = faster_write_clk ? slow_clk : fast_clk;

   wire [data_width-1:0] wr_data;
   wire 	 wr_en;
   wire [data_width-1:0] rd_data;
   wire 	 rd_en;
   wire 	 full;
   wire 	 empty;

   dual_clock_fifo
     #(.ADDR_WIDTH (depth_width),
       .DATA_WIDTH (data_width))
   dut
     (

      .wr_clk_i  (wr_clk),
      .wr_rst_i (rst),
      .wr_en_i   (wr_en & !full),
      .wr_data_i (wr_data),
      .full_o    (full),

      .rd_clk_i  (rd_clk),
      .rd_rst_i (rst),
      .rd_en_i   (rd_en & !empty),
      .rd_data_o (rd_data),
      .empty_o   (empty));

   fifo_tester
     #(.DEPTH   (DEPTH),
       .DW      (data_width))
   tester
     (.rst_i     (rst),
      .wr_clk_i  (wr_clk),
      .wr_en_o   (wr_en),
      .wr_data_o (wr_data),
      .full_i    (full),

      .rd_clk_i  (rd_clk),
      .rd_en_o   (rd_en),
      .rd_data_i (rd_data),
      .empty_i   (empty));

   integer 	 transactions = 10000;

   integer 	 errors;

   initial begin
      if($value$plusargs("transactions=%d", transactions)) begin
	 $display("Setting number of transactions to %0d", transactions);
      end

      #95000 rst = 0;
      $display("Testing slow write clock, fast write rate");
      fork
	 tester.fifo_write(transactions , 0.9);
	 tester.fifo_verify(transactions, 0.1, errors);
      join

      $display("Testing slow write clock, slow write rate");
      fork
	 tester.fifo_write(transactions , 0.1);
	 tester.fifo_verify(transactions, 0.9, errors);
      join

      rst = 1'b1;
      faster_write_clk = 1;
      #123 rst = 1'b0;

      $display("Testing fast write clock, fast write rate");
      fork
	 tester.fifo_write(transactions , 0.9);
	 tester.fifo_verify(transactions, 0.1, errors);
      join

      $display("Testing fast write clock, fast write rate");
      fork
	 tester.fifo_write(transactions , 0.1);
	 tester.fifo_verify(transactions, 0.9, errors);
      join
      $finish;
   end

endmodule
module dual_clock_fifo_tb
  #(parameter data_width  = 16,
    parameter depth_width = 8);


	initial begin
		$fsdbDumpfile("dual_clock_fifo");
		$fsdbDumpvars;
	end	

   localparam DEPTH = 1<<depth_width;

   reg slow_clk = 1'b1;
   reg fast_clk = 1'b1;
   reg rst = 1'b1;

   reg 		 faster_write_clk = 1'b0;
   wire 	 wr_clk;
   wire 	 rd_clk;


   always #11000 slow_clk <= ~slow_clk;
   always  #7000 fast_clk <= ~fast_clk;
   initial #95000 rst <= 0;

   assign wr_clk = faster_write_clk ? fast_clk : slow_clk;
   assign rd_clk = faster_write_clk ? slow_clk : fast_clk;

   wire [data_width-1:0] wr_data;
   wire 	 wr_en;
   wire [data_width-1:0] rd_data;
   wire 	 rd_en;
   wire 	 full;
   wire 	 empty;

   dual_clock_fifo
     #(.ADDR_WIDTH (depth_width),
       .DATA_WIDTH (data_width))
   dut
     (

      .wr_clk_i  (wr_clk),
      .wr_rst_i (rst),
      .wr_en_i   (wr_en & !full),
      .wr_data_i (wr_data),
      .full_o    (full),

      .rd_clk_i  (rd_clk),
      .rd_rst_i (rst),
      .rd_en_i   (rd_en & !empty),
      .rd_data_o (rd_data),
      .empty_o   (empty));

   fifo_tester
     #(.DEPTH   (DEPTH),
       .DW      (data_width))
   tester
     (.rst_i     (rst),
      .wr_clk_i  (wr_clk),
      .wr_en_o   (wr_en),
      .wr_data_o (wr_data),
      .full_i    (full),

      .rd_clk_i  (rd_clk),
      .rd_en_o   (rd_en),
      .rd_data_i (rd_data),
      .empty_i   (empty));

   integer 	 transactions = 10000;

   integer 	 errors;

   initial begin
      if($value$plusargs("transactions=%d", transactions)) begin
	 $display("Setting number of transactions to %0d", transactions);
      end

      #95000 rst = 0;
      $display("Testing slow write clock, fast write rate");
      fork
	 tester.fifo_write(transactions , 0.9);
	 tester.fifo_verify(transactions, 0.1, errors);
      join

      $display("Testing slow write clock, slow write rate");
      fork
	 tester.fifo_write(transactions , 0.1);
	 tester.fifo_verify(transactions, 0.9, errors);
      join

      rst = 1'b1;
      faster_write_clk = 1;
      #123 rst = 1'b0;

      $display("Testing fast write clock, fast write rate");
      fork
	 tester.fifo_write(transactions , 0.9);
	 tester.fifo_verify(transactions, 0.1, errors);
      join

      $display("Testing fast write clock, fast write rate");
      fork
	 tester.fifo_write(transactions , 0.1);
	 tester.fifo_verify(transactions, 0.9, errors);
      join
      $finish;
   end

endmodule