data/full_repos/permissive/170013753/src/cpu.v
 line:499: before: "+"
1: b'%Error: data/full_repos/permissive/170013753/src/cpu.v:8: Cannot find include file: alu.v\n`include "alu.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170013753/src,data/full_repos/permissive/170013753/alu.v\n             data/full_repos/permissive/170013753/src,data/full_repos/permissive/170013753/alu.v.v\n             data/full_repos/permissive/170013753/src,data/full_repos/permissive/170013753/alu.v.sv\n             alu.v\n             alu.v.v\n             alu.v.sv\n             obj_dir/alu.v\n             obj_dir/alu.v.v\n             obj_dir/alu.v.sv\n%Error: data/full_repos/permissive/170013753/src/cpu.v:9: Cannot find include file: ctrlunit.v\n`include "ctrlunit.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/170013753/src/cpu.v:10: Cannot find include file: regfile.v\n`include "regfile.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/170013753/src/cpu.v:11: Cannot find include file: ram.v\n`include "ram.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/170013753/src/cpu.v:12: Cannot find include file: rom.v\n`include "rom.v" \n         ^~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module cpu(
  input clk,
  input rst,

  output [15:0] tb_pc,
  output [15:0] tb_ir,
  output [15:0] tb_rd,
  output [15:0] tb_rs,
  output [15:0] tb_rt,
  output [3:0]  tb_aluStatus
);

wire [15:0] instruction;
wire [15:0] ramOut;
wire signed [15:0] rtShift;
wire [15:0] immExt;


reg [15:0] pcCur;
wire [15:0] pcNext;
wire [15:0] pc2;
wire [15:0] pcBrz;


wire [2:0] aluOp;
wire [1:0] memToReg, aluSrcA, aluSrcB;
wire jump, branch, memRead, memWrite, regWrite, signExt;


wire [3:0] selRd, selRs, selRt;
wire [15:0] rd, rs, rt;


wire [15:0] aluOperandA, aluOperandB;
wire [15:0] aluResult;
wire [3:0]  aluStatus;



always @(posedge clk or posedge rst) begin
  if(rst)
    pcCur <= 16'b0;
  else
    pcCur <= pcNext;
end

rom rom( .addr(pcCur), .o(instruction) );

ctrlunit ctrlunit( .clk(clk), .rst(rst), .opcode(instruction[15:12]), .aluOp(aluOp), 
  .memToReg(memToReg), .aluSrcA(aluSrcA), .aluSrcB(aluSrcB), .jump(jump), .branch(branch), 
  .memRead(memRead), .memWrite(memWrite), .regWrite(regWrite), .signExt(signExt) );



assign selRd = instruction[11:8];
assign selRs = (instruction[15:12] == 4'b1000) ? instruction[11:8] : instruction[7:4];
assign selRt = instruction[3:0];


regfile regfile( .clk(clk), .rst(rst), .wen(regWrite), .selRd(selRd),
  .selRs(selRs), .selRt(selRt), .rd(rd), .rs(rs), .rt(rt) );



assign aluOperandA = (aluSrcA == 2'b00) ? rs
                      : (aluSrcA == 2'b01) ? immExt
                       : (aluSrcA == 2'b10) ? {rs[7:0], 8'b0}
                        : 16'b0;

assign aluOperandB = (aluSrcB == 2'b00) ? rt
                      : (aluSrcB == 2'b01) ? immExt
                       : (aluSrcB == 2'b10) ? {8'b0, rt[7:0]}
                        : 16'b0;


alu alu( .a(aluOperandA), .b(aluOperandB), .op(aluOp), .fZ(aluStatus[0]), 
  .fC(aluStatus[1]), .fN(aluStatus[2]), .fV(aluStatus[3]), .o(aluResult) );



assign immExt = {((signExt == 1'b1) ? {8{instruction[7]}} : {8{1'b0}}), instruction[7:0]};



assign rtShift = {rt[14:0], 1'b0};
assign pc2 = pcCur + 16'd2;
assign pcBrz = (rtShift[15] == 1'b1) ? (pc2 - (~(rtShift) + 1'b1)) : (pc2 + rtShift);
assign pcNext = ((branch & aluStatus[0]) == 1'b1) ? pcBrz
                : (jump == 1'b1) ? rs
                  : pc2;


ram ram( .clk(clk), .wen(memWrite), .ren(memRead), .din(rt), .addr(aluResult), .dout(ramOut) );


assign rd = (regWrite == 1'b0) ? rd
            : (memToReg == 2'b01) ? ramOut
              : (memToReg == 2'b10) ? pcCur + 16'd2
                : aluResult;



assign tb_pc = pcCur;
assign tb_ir = instruction;
assign tb_rd = rd;
assign tb_rs = rs;
assign tb_rt = rt;
assign tb_aluStatus = aluStatus;

endmodule
module cpu(
  input clk,
  input rst,

  output [15:0] tb_pc,
  output [15:0] tb_ir,
  output [15:0] tb_rd,
  output [15:0] tb_rs,
  output [15:0] tb_rt,
  output [3:0]  tb_aluStatus
);


wire [15:0] instruction;
wire [15:0] ramOut;
wire signed [15:0] rtShift;
wire [15:0] immExt;


reg [15:0] pcCur;
wire [15:0] pcNext;
wire [15:0] pc2;
wire [15:0] pcBrz;


wire [2:0] aluOp;
wire [1:0] memToReg, aluSrcA, aluSrcB;
wire jump, branch, memRead, memWrite, regWrite, signExt;


wire [3:0] selRd, selRs, selRt;
wire [15:0] rd, rs, rt;


wire [15:0] aluOperandA, aluOperandB;
wire [15:0] aluResult;
wire [3:0]  aluStatus;



always @(posedge clk or posedge rst) begin
  if(rst)
    pcCur <= 16'b0;
  else
    pcCur <= pcNext;
end

rom rom( .addr(pcCur), .o(instruction) );

ctrlunit ctrlunit( .clk(clk), .rst(rst), .opcode(instruction[15:12]), .aluOp(aluOp), 
  .memToReg(memToReg), .aluSrcA(aluSrcA), .aluSrcB(aluSrcB), .jump(jump), .branch(branch), 
  .memRead(memRead), .memWrite(memWrite), .regWrite(regWrite), .signExt(signExt) );



assign selRd = instruction[11:8];
assign selRs = (instruction[15:12] == 4'b1000) ? instruction[11:8] : instruction[7:4];
assign selRt = instruction[3:0];


regfile regfile( .clk(clk), .rst(rst), .wen(regWrite), .selRd(selRd),
  .selRs(selRs), .selRt(selRt), .rd(rd), .rs(rs), .rt(rt) );



assign aluOperandA = (aluSrcA == 2'b00) ? rs
                      : (aluSrcA == 2'b01) ? immExt
                       : (aluSrcA == 2'b10) ? {rs[7:0], 8'b0}
                        : 16'b0;

assign aluOperandB = (aluSrcB == 2'b00) ? rt
                      : (aluSrcB == 2'b01) ? immExt
                       : (aluSrcB == 2'b10) ? {8'b0, rt[7:0]}
                        : 16'b0;


alu alu( .a(aluOperandA), .b(aluOperandB), .op(aluOp), .fZ(aluStatus[0]), 
  .fC(aluStatus[1]), .fN(aluStatus[2]), .fV(aluStatus[3]), .o(aluResult) );



assign immExt = {((signExt == 1'b1) ? {8{instruction[7]}} : {8{1'b0}}), instruction[7:0]};



assign rtShift = {rt[14:0], 1'b0};
assign pc2 = pcCur + 16'd2;
assign pcBrz = (rtShift[15] == 1'b1) ? (pc2 - (~(rtShift) + 1'b1)) : (pc2 + rtShift);
assign pcNext = ((branch & aluStatus[0]) == 1'b1) ? pcBrz
                : (jump == 1'b1) ? rs
                  : pc2;


ram ram( .clk(clk), .wen(memWrite), .ren(memRead), .din(rt), .addr(aluResult), .dout(ramOut) );


assign rd = (regWrite == 1'b0) ? rd
            : (memToReg == 2'b01) ? ramOut
              : (memToReg == 2'b10) ? pcCur + 16'd2
                : aluResult;



assign tb_pc = pcCur;
assign tb_ir = instruction;
assign tb_rd = rd;
assign tb_rs = rs;
assign tb_rt = rt;
assign tb_aluStatus = aluStatus;

endmodule