data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/mux8.v
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/mux8.v\n%Error: Exiting due to 4 error(s)\n'
module mux8 #(parameter WIDTH = 16)
             (input      [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
              input      [2:0]       s, 
              output reg [WIDTH-1:0] y);

   always @(*)
      case(s)
         3'b000: y <= d0;
         3'b001: y <= d1;
         3'b010: y <= d2;
         3'b011: y <= d3;
			3'b100: y <= d4;
			3'b101: y <= d5;
			3'b110: y <= d6;
			3'b111: y <= d7;
      endcase
		
endmodule
module mux8 #(parameter WIDTH = 16)
             (input      [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
              input      [2:0]       s, 
              output reg [WIDTH-1:0] y);


   always @(*)
      case(s)
         3'b000: y <= d0;
         3'b001: y <= d1;
         3'b010: y <= d2;
         3'b011: y <= d3;
			3'b100: y <= d4;
			3'b101: y <= d5;
			3'b110: y <= d6;
			3'b111: y <= d7;
      endcase
		
endmodule