data/full_repos/permissive/122184933/FPGA/clock_hs_phy.v
 line:39: before: "count"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/clock_hs_phy.v:37: Signal definition not found, creating implicitly: \'ddr_out\'\nassign out = hi_z ? 1\'bZ : ddr_out;\n                           ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/122184933/FPGA/clock_hs_phy.v:35: Cannot find file containing module: \'ODDRXE\'\nODDRXE ddr (.D0(enable_reg), .D1(1\'b0), .Q(ddr_out), .SCLK(bit_clk), .RST(bit_rst));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/ODDRXE\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/ODDRXE.v\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/ODDRXE.sv\n             ODDRXE\n             ODDRXE.v\n             ODDRXE.sv\n             obj_dir/ODDRXE\n             obj_dir/ODDRXE.v\n             obj_dir/ODDRXE.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module clock_hs_phy (

	input wire byte_clk, 

	input wire bit_clk, 

	input wire byte_rst, bit_rst,
	

	input wire enable,

	input wire hi_z,
	

	output wire out
);


reg enable_reg;


always @ (posedge byte_clk or posedge byte_rst)
begin

	if (byte_rst) begin
		enable_reg <= 0;

	end else begin
		enable_reg <= enable;
	end
end


ODDRXE ddr (.D0(enable_reg), .D1(1'b0), .Q(ddr_out), .SCLK(bit_clk), .RST(bit_rst));

assign out = hi_z ? 1'bZ : ddr_out;

endmodule
module clock_hs_phy (

	input wire byte_clk, 

	input wire bit_clk, 

	input wire byte_rst, bit_rst,
	

	input wire enable,

	input wire hi_z,
	

	output wire out
);



reg enable_reg;


always @ (posedge byte_clk or posedge byte_rst)
begin

	if (byte_rst) begin
		enable_reg <= 0;

	end else begin
		enable_reg <= enable;
	end
end


ODDRXE ddr (.D0(enable_reg), .D1(1'b0), .Q(ddr_out), .SCLK(bit_clk), .RST(bit_rst));

assign out = hi_z ? 1'bZ : ddr_out;

endmodule