data/full_repos/permissive/121277233/ons20-gsg-1-procsys/vivado/onets_7020_procsys/sources/onetswitch_top.v
1: b"%Error: data/full_repos/permissive/121277233/ons20-gsg-1-procsys/vivado/onets_7020_procsys/sources/onetswitch_top.v:72: Cannot find file containing module: 'onets_7020_procsys_wrapper'\nonets_7020_procsys_wrapper onets_7020_procsys_wrapper(\n^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/121277233/ons20-gsg-1-procsys/vivado/onets_7020_procsys/sources,data/full_repos/permissive/121277233/onets_7020_procsys_wrapper\n             data/full_repos/permissive/121277233/ons20-gsg-1-procsys/vivado/onets_7020_procsys/sources,data/full_repos/permissive/121277233/onets_7020_procsys_wrapper.v\n             data/full_repos/permissive/121277233/ons20-gsg-1-procsys/vivado/onets_7020_procsys/sources,data/full_repos/permissive/121277233/onets_7020_procsys_wrapper.sv\n             onets_7020_procsys_wrapper\n             onets_7020_procsys_wrapper.v\n             onets_7020_procsys_wrapper.sv\n             obj_dir/onets_7020_procsys_wrapper\n             obj_dir/onets_7020_procsys_wrapper.v\n             obj_dir/onets_7020_procsys_wrapper.sv\n%Error: Exiting due to 1 error(s)\n"
module onetswitch_top(
        inout [14:0]DDR_addr,
        inout [2:0]DDR_ba,
        inout DDR_cas_n,
        inout DDR_ck_n,
        inout DDR_ck_p,
        inout DDR_cke,
        inout DDR_cs_n,
        inout [3:0]DDR_dm,
        inout [31:0]DDR_dq,
        inout [3:0]DDR_dqs_n,
        inout [3:0]DDR_dqs_p,
        inout DDR_odt,
        inout DDR_ras_n,
        inout DDR_reset_n,
        inout DDR_we_n,
        inout FIXED_IO_ddr_vrn,
        inout FIXED_IO_ddr_vrp,
        inout [53:0]FIXED_IO_mio,
        inout FIXED_IO_ps_clk,
        inout FIXED_IO_ps_porb,
        inout FIXED_IO_ps_srstb,
        output    [1:0]   pl_led,
        output             pl_pmod
    );

reg   [23:0]   cnt_0;
reg   [23:0]   cnt_1;
reg   [23:0]   cnt_2;


wire           bd_fclk0_125m;
wire           bd_fclk1_75m;
wire           bd_fclk2_200m;

always@(posedge bd_fclk0_125m)
   cnt_0 <= cnt_0 + 1'b1;
   
always@(posedge bd_fclk1_75m)
   cnt_1 <= cnt_1 + 1'b1;    
    
always@(posedge bd_fclk2_200m)
   cnt_2 <= cnt_2 + 1'b1;    

    
assign pl_led[0] = cnt_0[23];
assign pl_led[1] = cnt_1[23];
assign pl_pmod   = cnt_2[23];
   
onets_7020_procsys_wrapper onets_7020_procsys_wrapper(

        .FCLK_CLK0_125MHz        (bd_fclk0_125m),
        .FCLK_CLK1_75MHz         (bd_fclk1_75m),
        .FCLK_CLK2_200MHz        (bd_fclk2_200m),
                              
         .DDR_addr               (DDR_addr),
         .DDR_ba                 (DDR_ba),
         .DDR_cas_n              (DDR_cas_n),
         .DDR_ck_n               (DDR_ck_n),
         .DDR_ck_p               (DDR_ck_p),
         .DDR_cke                (DDR_cke),
         .DDR_cs_n               (DDR_cs_n),
         .DDR_dm                 (DDR_dm),
         .DDR_dq                 (DDR_dq),
         .DDR_dqs_n              (DDR_dqs_n),
         .DDR_dqs_p              (DDR_dqs_p),
         .DDR_odt                (DDR_odt),
         .DDR_ras_n              (DDR_ras_n),
         .DDR_reset_n            (DDR_reset_n),
         .DDR_we_n               (DDR_we_n),
         
         .FIXED_IO_ddr_vrn       (FIXED_IO_ddr_vrn) ,
         .FIXED_IO_ddr_vrp       (FIXED_IO_ddr_vrp),
         .FIXED_IO_ps_srstb      (FIXED_IO_ps_srstb),
         .FIXED_IO_ps_clk        (FIXED_IO_ps_clk),
         .FIXED_IO_ps_porb       (FIXED_IO_ps_porb)
);
endmodule
module onetswitch_top(
        inout [14:0]DDR_addr,
        inout [2:0]DDR_ba,
        inout DDR_cas_n,
        inout DDR_ck_n,
        inout DDR_ck_p,
        inout DDR_cke,
        inout DDR_cs_n,
        inout [3:0]DDR_dm,
        inout [31:0]DDR_dq,
        inout [3:0]DDR_dqs_n,
        inout [3:0]DDR_dqs_p,
        inout DDR_odt,
        inout DDR_ras_n,
        inout DDR_reset_n,
        inout DDR_we_n,
        inout FIXED_IO_ddr_vrn,
        inout FIXED_IO_ddr_vrp,
        inout [53:0]FIXED_IO_mio,
        inout FIXED_IO_ps_clk,
        inout FIXED_IO_ps_porb,
        inout FIXED_IO_ps_srstb,
        output    [1:0]   pl_led,
        output             pl_pmod
    );


reg   [23:0]   cnt_0;
reg   [23:0]   cnt_1;
reg   [23:0]   cnt_2;


wire           bd_fclk0_125m;
wire           bd_fclk1_75m;
wire           bd_fclk2_200m;

always@(posedge bd_fclk0_125m)
   cnt_0 <= cnt_0 + 1'b1;
   
always@(posedge bd_fclk1_75m)
   cnt_1 <= cnt_1 + 1'b1;    
    
always@(posedge bd_fclk2_200m)
   cnt_2 <= cnt_2 + 1'b1;    

    
assign pl_led[0] = cnt_0[23];
assign pl_led[1] = cnt_1[23];
assign pl_pmod   = cnt_2[23];
   
onets_7020_procsys_wrapper onets_7020_procsys_wrapper(

        .FCLK_CLK0_125MHz        (bd_fclk0_125m),
        .FCLK_CLK1_75MHz         (bd_fclk1_75m),
        .FCLK_CLK2_200MHz        (bd_fclk2_200m),
                              
         .DDR_addr               (DDR_addr),
         .DDR_ba                 (DDR_ba),
         .DDR_cas_n              (DDR_cas_n),
         .DDR_ck_n               (DDR_ck_n),
         .DDR_ck_p               (DDR_ck_p),
         .DDR_cke                (DDR_cke),
         .DDR_cs_n               (DDR_cs_n),
         .DDR_dm                 (DDR_dm),
         .DDR_dq                 (DDR_dq),
         .DDR_dqs_n              (DDR_dqs_n),
         .DDR_dqs_p              (DDR_dqs_p),
         .DDR_odt                (DDR_odt),
         .DDR_ras_n              (DDR_ras_n),
         .DDR_reset_n            (DDR_reset_n),
         .DDR_we_n               (DDR_we_n),
         
         .FIXED_IO_ddr_vrn       (FIXED_IO_ddr_vrn) ,
         .FIXED_IO_ddr_vrp       (FIXED_IO_ddr_vrp),
         .FIXED_IO_ps_srstb      (FIXED_IO_ps_srstb),
         .FIXED_IO_ps_clk        (FIXED_IO_ps_clk),
         .FIXED_IO_ps_porb       (FIXED_IO_ps_porb)
);
endmodule