data/full_repos/permissive/193790231/lab08/lab08part05.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193790231/lab08/lab08part05.v:22: Unsupported: Ignoring delay on this delayed statement.\n  forever #50 clk=~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab08/lab08part05.v:36: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab08/lab08part05.v:42: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: data/full_repos/permissive/193790231/lab08/lab08part05.v:8: Cannot find file containing module: \'lpmRAM2port\'\n    lpmRAM2port my2pRAM(CLK, dataIN, addrREAD, addrWRITE, wrEN, dataOUT);\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193790231/lab08,data/full_repos/permissive/193790231/lpmRAM2port\n             data/full_repos/permissive/193790231/lab08,data/full_repos/permissive/193790231/lpmRAM2port.v\n             data/full_repos/permissive/193790231/lab08,data/full_repos/permissive/193790231/lpmRAM2port.sv\n             lpmRAM2port\n             lpmRAM2port.v\n             lpmRAM2port.sv\n             obj_dir/lpmRAM2port\n             obj_dir/lpmRAM2port.v\n             obj_dir/lpmRAM2port.sv\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab08/lab08part05.v:30: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                           : ... In instance tbtesl8p5\n    addrR = i-1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab08/lab08part05.v:32: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance tbtesl8p5\n    addrR = i;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab08/lab08part05.v:34: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance tbtesl8p5\n   addrW = i;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab08/lab08part05.v:35: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance tbtesl8p5\n   dataIN = i;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab08/lab08part05.v:41: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance tbtesl8p5\n   addrR = i;\n         ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lab08part05(
    output [7:0]dataOUT,
    input  CLK,
    input  [7:0]dataIN,
    input  [4:0]addrREAD, addrWRITE,
    input  wrEN
);
    lpmRAM2port	my2pRAM(CLK, dataIN, addrREAD, addrWRITE, wrEN, dataOUT);
endmodule
module lab08part05(
    output [7:0]dataOUT,
    input  CLK,
    input  [7:0]dataIN,
    input  [4:0]addrREAD, addrWRITE,
    input  wrEN
);

    lpmRAM2port	my2pRAM(CLK, dataIN, addrREAD, addrWRITE, wrEN, dataOUT);
endmodule