data/full_repos/permissive/136510272/projects/mkalc/marsohod2.v
 line:100: before: ")"
1: b"%Error: data/full_repos/permissive/136510272/projects/mkalc/marsohod2.v:73: Cannot find file containing module: 'pll'\npll PLL(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/projects/mkalc,data/full_repos/permissive/136510272/pll\n             data/full_repos/permissive/136510272/projects/mkalc,data/full_repos/permissive/136510272/pll.v\n             data/full_repos/permissive/136510272/projects/mkalc,data/full_repos/permissive/136510272/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/136510272/projects/mkalc/marsohod2.v:89: Cannot find file containing module: 'rom'\nrom PRGROM(\n^~~\n%Error: data/full_repos/permissive/136510272/projects/mkalc/marsohod2.v:118: Cannot find file containing module: 'processor'\nprocessor PROC6502(\n^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module marsohod2(




    input   wire        clk,


    output  wire [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);




wire locked;
wire clock_25;
wire clock_12;
wire clock_6;
 
pll PLL(

    .clk        (clk),
    .locked     (locked),
    .c0         (clock_25),
    .c1         (clock_12),
    .c2         (clock_6)

);



wire cntl_w;
 
rom PRGROM(

    .clock   (clk),
    .addr_rd (o_addr[13:0]),
    .q       (i_data),

    .addr_wr (o_addr[13:0]),
    .data_wr (o_data),
    .wren    (cntl_w),


);



reg [2:0] cntl_mw = 3'b000;
assign    cntl_w  = cntl_mw == 3'b011 && o_wr;
always @(posedge clk) cntl_mw <= {cntl_mw[1:0], clock_25}; 




wire [7:0]  i_data;
wire [15:0] o_addr;
wire [7:0]  o_data;
wire        o_wr;

processor PROC6502(

	.clock_25   (locked & clock_25),
	.i_data     (i_data),
	.o_addr     (o_addr),
    .o_data     (o_data),
    .o_wr       (o_wr),

);

endmodule
module marsohod2(




    input   wire        clk,


    output  wire [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);





wire locked;
wire clock_25;
wire clock_12;
wire clock_6;
 
pll PLL(

    .clk        (clk),
    .locked     (locked),
    .c0         (clock_25),
    .c1         (clock_12),
    .c2         (clock_6)

);



wire cntl_w;
 
rom PRGROM(

    .clock   (clk),
    .addr_rd (o_addr[13:0]),
    .q       (i_data),

    .addr_wr (o_addr[13:0]),
    .data_wr (o_data),
    .wren    (cntl_w),


);



reg [2:0] cntl_mw = 3'b000;
assign    cntl_w  = cntl_mw == 3'b011 && o_wr;
always @(posedge clk) cntl_mw <= {cntl_mw[1:0], clock_25}; 




wire [7:0]  i_data;
wire [15:0] o_addr;
wire [7:0]  o_data;
wire        o_wr;

processor PROC6502(

	.clock_25   (locked & clock_25),
	.i_data     (i_data),
	.o_addr     (o_addr),
    .o_data     (o_data),
    .o_wr       (o_wr),

);

endmodule