data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:24: Little bit endian vector: MSB < LSB of bit range: 0:14\n  input [0:14] addr_a,\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:25: Little bit endian vector: MSB < LSB of bit range: 0:14\n  input [0:14] addr_b,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:26: Little bit endian vector: MSB < LSB of bit range: 0:31\n  input [0:31] data_a,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:27: Little bit endian vector: MSB < LSB of bit range: 0:31\n  input [0:31] data_b,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:30: Little bit endian vector: MSB < LSB of bit range: 0:31\n  output reg [0:31] q_a,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:31: Little bit endian vector: MSB < LSB of bit range: 0:31\n  output reg [0:31] q_b,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:33: Little bit endian vector: MSB < LSB of bit range: 0:3\n  input [0:3] mode);\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:35: Little bit endian vector: MSB < LSB of bit range: 0:9\n  reg [0:9] ram_a [0:31];\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:36: Little bit endian vector: MSB < LSB of bit range: 0:9\n  reg [0:9] ram_b [0:31];\n      ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:42: Bit extraction of array[31:0] requires 5 bit index, not 9 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        ram_a[addr_a[0:8]] <= data_a;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:42: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_a\' generates 32 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        ram_a[addr_a[0:8]] <= data_a;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:43: Bit extraction of array[31:0] requires 5 bit index, not 9 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        ram_b[addr_a[0:8]] <= data_b;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:43: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_b\' generates 32 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        ram_b[addr_a[0:8]] <= data_b;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:47: Bit extraction of array[31:0] requires 5 bit index, not 9 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        q_a <= ram_a[addr_a[0:8]];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:47: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        q_a <= ram_a[addr_a[0:8]];\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:48: Bit extraction of array[31:0] requires 5 bit index, not 9 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        q_b <= ram_b[addr_a[0:8]];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:48: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        q_b <= ram_b[addr_a[0:8]];\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:53: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        ram_a[addr_a[0:9]] <= data_a;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:53: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_a\' generates 32 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        ram_a[addr_a[0:9]] <= data_a;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:55: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        q_a <= ram_a[addr_a[0:9]];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:55: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n        q_a <= ram_a[addr_a[0:9]];\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:61: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          1\'b0 : ram_a[addr_a[0:9]][0:15] <= data_a[0:15];\n                      ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:61: Extracting 16 bits from only 10 bit number\n                                                                                                          : ... In instance frac_mem_32k\n          1\'b0 : ram_a[addr_a[0:9]][0:15] <= data_a[0:15];\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:62: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          1\'b1 : ram_a[addr_a[0:9]][16:31] <= data_a[0:15];\n                      ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:62: Extracting 16 bits from only 10 bit number\n                                                                                                          : ... In instance frac_mem_32k\n          1\'b1 : ram_a[addr_a[0:9]][16:31] <= data_a[0:15];\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:66: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          1\'b0 : q_a <= ram_a[addr_a[0:9]][0:15];\n                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:66: Extracting 16 bits from only 10 bit number\n                                                                                                          : ... In instance frac_mem_32k\n          1\'b0 : q_a <= ram_a[addr_a[0:9]][0:15];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:66: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          1\'b0 : q_a <= ram_a[addr_a[0:9]][0:15];\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:67: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          1\'b1 : q_a <= ram_a[addr_a[0:9]][16:31];\n                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:67: Extracting 16 bits from only 10 bit number\n                                                                                                          : ... In instance frac_mem_32k\n          1\'b1 : q_a <= ram_a[addr_a[0:9]][16:31];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:67: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          1\'b1 : q_a <= ram_a[addr_a[0:9]][16:31];\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:74: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b00 : ram_a[addr_a[0:9]][0:7] <= data_a[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:75: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b01 : ram_a[addr_a[0:9]][8:15] <= data_a[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:76: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b10 : ram_a[addr_a[0:9]][16:23] <= data_a[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:77: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b11 : ram_a[addr_a[0:9]][24:31] <= data_a[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:81: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b00 : q_a <= ram_a[addr_a[0:9]][0:7];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:81: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b00 : q_a <= ram_a[addr_a[0:9]][0:7];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:82: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b01 : q_a <= ram_a[addr_a[0:9]][8:15];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:82: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b01 : q_a <= ram_a[addr_a[0:9]][8:15];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:83: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b10 : q_a <= ram_a[addr_a[0:9]][16:23];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:83: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b10 : q_a <= ram_a[addr_a[0:9]][16:23];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:84: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b11 : q_a <= ram_a[addr_a[0:9]][24:31];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:84: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          2\'b11 : q_a <= ram_a[addr_a[0:9]][24:31];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:91: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          3\'b000 : ram_a[addr_a[0:9]][0:3] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:92: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          3\'b001 : ram_a[addr_a[0:9]][4:7] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:93: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          3\'b010 : ram_a[addr_a[0:9]][8:11] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:94: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          3\'b011 : ram_a[addr_a[0:9]][12:15] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:95: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          3\'b100 : ram_a[addr_a[0:9]][16:19] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:96: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          3\'b101 : ram_a[addr_a[0:9]][20:23] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:97: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          3\'b110 : ram_a[addr_a[0:9]][24:27] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:98: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                  : ... In instance frac_mem_32k\n          3\'b111 : ram_a[addr_a[0:9]][28:31] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:102: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b000 : q_a <= ram_a[addr_a[0:9]][0:3];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:102: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b000 : q_a <= ram_a[addr_a[0:9]][0:3];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:103: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b001 : q_a <= ram_a[addr_a[0:9]][4:7];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:103: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b001 : q_a <= ram_a[addr_a[0:9]][4:7];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:104: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b010 : q_a <= ram_a[addr_a[0:9]][8:11];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:104: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b010 : q_a <= ram_a[addr_a[0:9]][8:11];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:105: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b011 : q_a <= ram_a[addr_a[0:9]][12:15];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:105: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b011 : q_a <= ram_a[addr_a[0:9]][12:15];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:106: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b100 : q_a <= ram_a[addr_a[0:9]][16:19];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:106: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b100 : q_a <= ram_a[addr_a[0:9]][16:19];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:107: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b101 : q_a <= ram_a[addr_a[0:9]][20:23];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:107: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b101 : q_a <= ram_a[addr_a[0:9]][20:23];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:108: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b110 : q_a <= ram_a[addr_a[0:9]][24:27];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:108: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b110 : q_a <= ram_a[addr_a[0:9]][24:27];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:109: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b111 : q_a <= ram_a[addr_a[0:9]][28:31];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:109: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b111 : q_a <= ram_a[addr_a[0:9]][28:31];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:116: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0000 : ram_a[addr_a[0:9]][0:1] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:117: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0001 : ram_a[addr_a[0:9]][2:3] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:118: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0010 : ram_a[addr_a[0:9]][4:5] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:119: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0011 : ram_a[addr_a[0:9]][6:7] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:120: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0100 : ram_a[addr_a[0:9]][8:9] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:121: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0101 : ram_a[addr_a[0:9]][10:11] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:122: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0110 : ram_a[addr_a[0:9]][12:13] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:123: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0111 : ram_a[addr_a[0:9]][14:15] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:124: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1000 : ram_a[addr_a[0:9]][16:17] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:125: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1001 : ram_a[addr_a[0:9]][18:19] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:126: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1010 : ram_a[addr_a[0:9]][20:21] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:127: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1011 : ram_a[addr_a[0:9]][22:23] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:128: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1100 : ram_a[addr_a[0:9]][24:25] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:129: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1101 : ram_a[addr_a[0:9]][26:27] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:130: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1110 : ram_a[addr_a[0:9]][28:29] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:131: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1111 : ram_a[addr_a[0:9]][30:31] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:135: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:135: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:136: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:136: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:137: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:137: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:138: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:138: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:139: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:139: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:140: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:140: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:141: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:141: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:142: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:142: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:143: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:143: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:144: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:144: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:145: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:145: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:146: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:146: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:147: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:147: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:148: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:148: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:149: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:149: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:150: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:150: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:156: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        ram_a[addr_a[0:9]][addr_a[10:14]] = data_a[0:0];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:158: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:158: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:163: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        ram_a[addr_a[0:9]] <= data_a;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:163: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_a\' generates 32 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        ram_a[addr_a[0:9]] <= data_a;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:166: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        q_a <= ram_a[addr_a[0:9]];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:166: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        q_a <= ram_a[addr_a[0:9]];\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:170: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        ram_b[addr_b[0:9]] <= data_b;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:170: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_b\' generates 32 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        ram_b[addr_b[0:9]] <= data_b;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:173: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        q_b <= ram_b[addr_b[0:9]];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:173: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        q_b <= ram_b[addr_b[0:9]];\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:179: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b0 : ram_a[addr_a[0:9]][0:15] <= data_a;\n                      ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:179: Extracting 16 bits from only 10 bit number\n                                                                                                           : ... In instance frac_mem_32k\n          1\'b0 : ram_a[addr_a[0:9]][0:15] <= data_a;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:179: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_a\' generates 32 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b0 : ram_a[addr_a[0:9]][0:15] <= data_a;\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:180: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b1 : ram_a[addr_a[0:9]][16:31] <= data_a;\n                      ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:180: Extracting 16 bits from only 10 bit number\n                                                                                                           : ... In instance frac_mem_32k\n          1\'b1 : ram_a[addr_a[0:9]][16:31] <= data_a;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:180: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_a\' generates 32 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b1 : ram_a[addr_a[0:9]][16:31] <= data_a;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:184: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b0 : q_a <= ram_a[addr_a[0:9]][0:15];\n                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:184: Extracting 16 bits from only 10 bit number\n                                                                                                           : ... In instance frac_mem_32k\n          1\'b0 : q_a <= ram_a[addr_a[0:9]][0:15];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:184: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b0 : q_a <= ram_a[addr_a[0:9]][0:15];\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:185: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b1 : q_a <= ram_a[addr_a[0:9]][16:31];\n                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:185: Extracting 16 bits from only 10 bit number\n                                                                                                           : ... In instance frac_mem_32k\n          1\'b1 : q_a <= ram_a[addr_a[0:9]][16:31];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:185: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b1 : q_a <= ram_a[addr_a[0:9]][16:31];\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:191: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b0 : ram_b[addr_b[0:9]][0:15] <= data_b;\n                      ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:191: Extracting 16 bits from only 10 bit number\n                                                                                                           : ... In instance frac_mem_32k\n          1\'b0 : ram_b[addr_b[0:9]][0:15] <= data_b;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:191: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_b\' generates 32 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b0 : ram_b[addr_b[0:9]][0:15] <= data_b;\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:192: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b1 : ram_b[addr_b[0:9]][16:31] <= data_b;\n                      ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:192: Extracting 16 bits from only 10 bit number\n                                                                                                           : ... In instance frac_mem_32k\n          1\'b1 : ram_b[addr_b[0:9]][16:31] <= data_b;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:192: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_b\' generates 32 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b1 : ram_b[addr_b[0:9]][16:31] <= data_b;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:196: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b0 : q_b <= ram_b[addr_b[0:9]][0:15];\n                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:196: Extracting 16 bits from only 10 bit number\n                                                                                                           : ... In instance frac_mem_32k\n          1\'b0 : q_b <= ram_b[addr_b[0:9]][0:15];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:196: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b0 : q_b <= ram_b[addr_b[0:9]][0:15];\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:197: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b1 : q_b <= ram_b[addr_b[0:9]][16:31];\n                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:197: Extracting 16 bits from only 10 bit number\n                                                                                                           : ... In instance frac_mem_32k\n          1\'b1 : q_b <= ram_b[addr_b[0:9]][16:31];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:197: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          1\'b1 : q_b <= ram_b[addr_b[0:9]][16:31];\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:204: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b00 : ram_a[addr_a[0:9]][0:7] <= data_a[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:205: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b01 : ram_a[addr_a[0:9]][8:15] <= data_a[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:206: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b10 : ram_a[addr_a[0:9]][16:23] <= data_a[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:207: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b11 : ram_a[addr_a[0:9]][24:31] <= data_a[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:211: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b00 : q_a <= ram_a[addr_a[0:9]][0:7];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:211: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b00 : q_a <= ram_a[addr_a[0:9]][0:7];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:212: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b01 : q_a <= ram_a[addr_a[0:9]][8:15];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:212: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b01 : q_a <= ram_a[addr_a[0:9]][8:15];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:213: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b10 : q_a <= ram_a[addr_a[0:9]][16:23];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:213: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b10 : q_a <= ram_a[addr_a[0:9]][16:23];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:214: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b11 : q_a <= ram_a[addr_a[0:9]][24:31];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:214: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b11 : q_a <= ram_a[addr_a[0:9]][24:31];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:220: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b00 : ram_b[addr_b[0:9]][0:7] <= data_b[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:221: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b01 : ram_b[addr_b[0:9]][8:15] <= data_b[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:222: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b10 : ram_b[addr_b[0:9]][16:23] <= data_b[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:223: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b11 : ram_b[addr_b[0:9]][24:31] <= data_b[0:7];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:227: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b00 : q_b <= ram_b[addr_b[0:9]][0:7];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:227: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b00 : q_b <= ram_b[addr_b[0:9]][0:7];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:228: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b01 : q_b <= ram_b[addr_b[0:9]][8:15];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:228: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b01 : q_b <= ram_b[addr_b[0:9]][8:15];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:229: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b10 : q_b <= ram_b[addr_b[0:9]][16:23];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:229: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b10 : q_b <= ram_b[addr_b[0:9]][16:23];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:230: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b11 : q_b <= ram_b[addr_b[0:9]][24:31];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:230: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          2\'b11 : q_b <= ram_b[addr_b[0:9]][24:31];\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:237: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b000 : ram_a[addr_a[0:9]][0:3] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:238: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b001 : ram_a[addr_a[0:9]][4:7] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:239: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b010 : ram_a[addr_a[0:9]][8:11] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:240: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b011 : ram_a[addr_a[0:9]][12:15] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:241: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b100 : ram_a[addr_a[0:9]][16:19] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:242: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b101 : ram_a[addr_a[0:9]][20:23] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:243: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b110 : ram_a[addr_a[0:9]][24:27] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:244: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b111 : ram_a[addr_a[0:9]][28:31] <= data_a[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:248: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b000 : q_a <= ram_a[addr_a[0:9]][0:3];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:248: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b000 : q_a <= ram_a[addr_a[0:9]][0:3];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:249: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b001 : q_a <= ram_a[addr_a[0:9]][4:7];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:249: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b001 : q_a <= ram_a[addr_a[0:9]][4:7];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:250: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b010 : q_a <= ram_a[addr_a[0:9]][8:11];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:250: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b010 : q_a <= ram_a[addr_a[0:9]][8:11];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:251: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b011 : q_a <= ram_a[addr_a[0:9]][12:15];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:251: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b011 : q_a <= ram_a[addr_a[0:9]][12:15];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:252: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b100 : q_a <= ram_a[addr_a[0:9]][16:19];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:252: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b100 : q_a <= ram_a[addr_a[0:9]][16:19];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:253: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b101 : q_a <= ram_a[addr_a[0:9]][20:23];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:253: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b101 : q_a <= ram_a[addr_a[0:9]][20:23];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:254: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b110 : q_a <= ram_a[addr_a[0:9]][24:27];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:254: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b110 : q_a <= ram_a[addr_a[0:9]][24:27];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:255: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b111 : q_a <= ram_a[addr_a[0:9]][28:31];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:255: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b111 : q_a <= ram_a[addr_a[0:9]][28:31];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:260: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b000 : ram_b[addr_b[0:9]][0:3] <= data_b[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:261: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b001 : ram_b[addr_b[0:9]][4:7] <= data_b[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:262: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b010 : ram_b[addr_b[0:9]][8:11] <= data_b[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:263: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b011 : ram_b[addr_b[0:9]][12:15] <= data_b[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:264: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b100 : ram_b[addr_b[0:9]][16:19] <= data_b[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:265: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b101 : ram_b[addr_b[0:9]][20:23] <= data_b[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:266: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b110 : ram_b[addr_b[0:9]][24:27] <= data_b[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:267: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b111 : ram_b[addr_b[0:9]][28:31] <= data_b[0:3];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:271: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b000 : q_b <= ram_b[addr_b[0:9]][0:3];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:271: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b000 : q_b <= ram_b[addr_b[0:9]][0:3];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:272: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b001 : q_b <= ram_b[addr_b[0:9]][4:7];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:272: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b001 : q_b <= ram_b[addr_b[0:9]][4:7];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:273: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b010 : q_b <= ram_b[addr_b[0:9]][8:11];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:273: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b010 : q_b <= ram_b[addr_b[0:9]][8:11];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:274: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b011 : q_b <= ram_b[addr_b[0:9]][12:15];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:274: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b011 : q_b <= ram_b[addr_b[0:9]][12:15];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:275: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b100 : q_b <= ram_b[addr_b[0:9]][16:19];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:275: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b100 : q_b <= ram_b[addr_b[0:9]][16:19];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:276: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b101 : q_b <= ram_b[addr_b[0:9]][20:23];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:276: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b101 : q_b <= ram_b[addr_b[0:9]][20:23];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:277: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b110 : q_b <= ram_b[addr_b[0:9]][24:27];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:277: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b110 : q_b <= ram_b[addr_b[0:9]][24:27];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:278: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b111 : q_b <= ram_b[addr_b[0:9]][28:31];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:278: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          3\'b111 : q_b <= ram_b[addr_b[0:9]][28:31];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:285: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0000 : ram_a[addr_a[0:9]][0:1] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:286: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0001 : ram_a[addr_a[0:9]][2:3] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:287: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0010 : ram_a[addr_a[0:9]][4:5] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:288: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0011 : ram_a[addr_a[0:9]][6:7] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:289: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0100 : ram_a[addr_a[0:9]][8:9] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:290: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0101 : ram_a[addr_a[0:9]][10:11] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:291: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0110 : ram_a[addr_a[0:9]][12:13] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:292: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0111 : ram_a[addr_a[0:9]][14:15] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:293: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1000 : ram_a[addr_a[0:9]][16:17] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:294: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1001 : ram_a[addr_a[0:9]][18:19] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:295: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1010 : ram_a[addr_a[0:9]][20:21] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:296: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1011 : ram_a[addr_a[0:9]][22:23] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:297: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1100 : ram_a[addr_a[0:9]][24:25] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:298: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1101 : ram_a[addr_a[0:9]][26:27] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:299: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1110 : ram_a[addr_a[0:9]][28:29] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:300: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1111 : ram_a[addr_a[0:9]][30:31] <= data_a[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:304: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:304: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:305: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:305: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:306: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:306: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:307: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:307: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:308: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:308: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:309: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:309: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:310: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:310: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:311: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:311: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:312: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:312: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:313: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:313: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:314: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:314: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:315: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:315: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:316: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:316: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:317: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:317: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:318: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:318: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:319: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:319: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:324: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0000 : ram_b[addr_b[0:9]][0:1] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:325: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0001 : ram_b[addr_b[0:9]][2:3] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:326: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0010 : ram_b[addr_b[0:9]][4:5] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:327: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0011 : ram_b[addr_b[0:9]][6:7] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:328: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0100 : ram_b[addr_b[0:9]][8:9] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:329: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0101 : ram_b[addr_b[0:9]][10:11] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:330: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0110 : ram_b[addr_b[0:9]][12:13] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:331: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0111 : ram_b[addr_b[0:9]][14:15] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:332: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1000 : ram_b[addr_b[0:9]][16:17] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:333: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1001 : ram_b[addr_b[0:9]][18:19] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:334: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1010 : ram_b[addr_b[0:9]][20:21] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:335: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1011 : ram_b[addr_b[0:9]][22:23] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:336: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1100 : ram_b[addr_b[0:9]][24:25] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:337: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1101 : ram_b[addr_b[0:9]][26:27] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:338: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1110 : ram_b[addr_b[0:9]][28:29] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:339: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1111 : ram_b[addr_b[0:9]][30:31] <= data_b[0:1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:343: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0000 : q_b <= ram_b[addr_b[0:9]][0:1];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:343: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0000 : q_b <= ram_b[addr_b[0:9]][0:1];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:344: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0001 : q_b <= ram_b[addr_b[0:9]][2:3];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:344: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0001 : q_b <= ram_b[addr_b[0:9]][2:3];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:345: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0010 : q_b <= ram_b[addr_b[0:9]][4:5];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:345: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0010 : q_b <= ram_b[addr_b[0:9]][4:5];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:346: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0011 : q_b <= ram_b[addr_b[0:9]][6:7];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:346: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0011 : q_b <= ram_b[addr_b[0:9]][6:7];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:347: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0100 : q_b <= ram_b[addr_b[0:9]][8:9];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:347: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0100 : q_b <= ram_b[addr_b[0:9]][8:9];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:348: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0101 : q_b <= ram_b[addr_b[0:9]][10:11];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:348: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0101 : q_b <= ram_b[addr_b[0:9]][10:11];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:349: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0110 : q_b <= ram_b[addr_b[0:9]][12:13];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:349: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0110 : q_b <= ram_b[addr_b[0:9]][12:13];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:350: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0111 : q_b <= ram_b[addr_b[0:9]][14:15];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:350: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b0111 : q_b <= ram_b[addr_b[0:9]][14:15];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:351: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1000 : q_b <= ram_b[addr_b[0:9]][16:17];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:351: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1000 : q_b <= ram_b[addr_b[0:9]][16:17];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:352: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1001 : q_b <= ram_b[addr_b[0:9]][18:19];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:352: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1001 : q_b <= ram_b[addr_b[0:9]][18:19];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:353: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1010 : q_b <= ram_b[addr_b[0:9]][20:21];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:353: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1010 : q_b <= ram_b[addr_b[0:9]][20:21];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:354: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1011 : q_b <= ram_b[addr_b[0:9]][22:23];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:354: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1011 : q_b <= ram_b[addr_b[0:9]][22:23];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:355: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1100 : q_b <= ram_b[addr_b[0:9]][24:25];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:355: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1100 : q_b <= ram_b[addr_b[0:9]][24:25];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:356: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1101 : q_b <= ram_b[addr_b[0:9]][26:27];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:356: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1101 : q_b <= ram_b[addr_b[0:9]][26:27];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:357: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1110 : q_b <= ram_b[addr_b[0:9]][28:29];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:357: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1110 : q_b <= ram_b[addr_b[0:9]][28:29];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:358: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1111 : q_b <= ram_b[addr_b[0:9]][30:31];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:358: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n          4\'b1111 : q_b <= ram_b[addr_b[0:9]][30:31];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:364: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        ram_a[addr_a[0:9]][addr_a[10:14]] = data_a[0:0];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:366: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:366: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:369: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        ram_b[addr_b[0:9]][addr_b[10:14]] = data_b[0:0];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:371: Bit extraction of array[31:0] requires 5 bit index, not 10 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        q_b <= ram_b[addr_b[0:9]][addr_b[10:14]];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v:371: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                                                                   : ... In instance frac_mem_32k\n        q_b <= ram_b[addr_b[0:9]][addr_b[10:14]];\n            ^~\n%Error: Exiting due to 12 error(s), 312 warning(s)\n'
module frac_mem_32k (
  input [0:14] addr_a,
  input [0:14] addr_b,
  input [0:31] data_a,
  input [0:31] data_b,
  input we_a,
  input we_b,
  output reg [0:31] q_a,
  output reg [0:31] q_b,
  input clk,
  input [0:3] mode);

  reg [0:9] ram_a [0:31];
  reg [0:9] ram_b [0:31];

  always @(posedge clk) begin

    if (4'b0000 == mode) begin 
      if (we_a) begin
        ram_a[addr_a[0:8]] <= data_a;
        ram_b[addr_a[0:8]] <= data_b;
        q_a <= data_a;
        q_b <= data_b;
      end else begin
        q_a <= ram_a[addr_a[0:8]];
        q_b <= ram_b[addr_a[0:8]];
      end 

    end else if (4'b0001 == mode) begin
      if (we_a) begin
        ram_a[addr_a[0:9]] <= data_a;
      end else begin
        q_a <= ram_a[addr_a[0:9]];
      end

    end else if (4'b0010 == mode) begin
      if (we_a) begin
        case (addr_a[10:10])
          1'b0 : ram_a[addr_a[0:9]][0:15] <= data_a[0:15];
          1'b1 : ram_a[addr_a[0:9]][16:31] <= data_a[0:15];
        endcase
      end else begin
        case (addr_a[10:10])
          1'b0 : q_a <= ram_a[addr_a[0:9]][0:15];
          1'b1 : q_a <= ram_a[addr_a[0:9]][16:31];
        endcase
      end

    end else if (4'b0011 == mode) begin
      if (we_a) begin
        case (addr_a[10:11])
          2'b00 : ram_a[addr_a[0:9]][0:7] <= data_a[0:7];
          2'b01 : ram_a[addr_a[0:9]][8:15] <= data_a[0:7];
          2'b10 : ram_a[addr_a[0:9]][16:23] <= data_a[0:7];
          2'b11 : ram_a[addr_a[0:9]][24:31] <= data_a[0:7];
        endcase
      end else begin
        case (addr_a[10:11])
          2'b00 : q_a <= ram_a[addr_a[0:9]][0:7];
          2'b01 : q_a <= ram_a[addr_a[0:9]][8:15];
          2'b10 : q_a <= ram_a[addr_a[0:9]][16:23];
          2'b11 : q_a <= ram_a[addr_a[0:9]][24:31];
        endcase
      end

    end else if (4'b0100 == mode) begin
      if (we_a) begin
        case (addr_a[10:12])
          3'b000 : ram_a[addr_a[0:9]][0:3] <= data_a[0:3];
          3'b001 : ram_a[addr_a[0:9]][4:7] <= data_a[0:3];
          3'b010 : ram_a[addr_a[0:9]][8:11] <= data_a[0:3];
          3'b011 : ram_a[addr_a[0:9]][12:15] <= data_a[0:3];
          3'b100 : ram_a[addr_a[0:9]][16:19] <= data_a[0:3];
          3'b101 : ram_a[addr_a[0:9]][20:23] <= data_a[0:3];
          3'b110 : ram_a[addr_a[0:9]][24:27] <= data_a[0:3];
          3'b111 : ram_a[addr_a[0:9]][28:31] <= data_a[0:3];
        endcase
      end else begin
        case (addr_a[10:12])
          3'b000 : q_a <= ram_a[addr_a[0:9]][0:3];
          3'b001 : q_a <= ram_a[addr_a[0:9]][4:7];
          3'b010 : q_a <= ram_a[addr_a[0:9]][8:11];
          3'b011 : q_a <= ram_a[addr_a[0:9]][12:15];
          3'b100 : q_a <= ram_a[addr_a[0:9]][16:19];
          3'b101 : q_a <= ram_a[addr_a[0:9]][20:23];
          3'b110 : q_a <= ram_a[addr_a[0:9]][24:27];
          3'b111 : q_a <= ram_a[addr_a[0:9]][28:31];
        endcase
      end

    end else if (4'b0101 == mode) begin
      if (we_a) begin
        case (addr_a[10:13])
          4'b0000 : ram_a[addr_a[0:9]][0:1] <= data_a[0:1];
          4'b0001 : ram_a[addr_a[0:9]][2:3] <= data_a[0:1];
          4'b0010 : ram_a[addr_a[0:9]][4:5] <= data_a[0:1];
          4'b0011 : ram_a[addr_a[0:9]][6:7] <= data_a[0:1];
          4'b0100 : ram_a[addr_a[0:9]][8:9] <= data_a[0:1];
          4'b0101 : ram_a[addr_a[0:9]][10:11] <= data_a[0:1];
          4'b0110 : ram_a[addr_a[0:9]][12:13] <= data_a[0:1];
          4'b0111 : ram_a[addr_a[0:9]][14:15] <= data_a[0:1];
          4'b1000 : ram_a[addr_a[0:9]][16:17] <= data_a[0:1];
          4'b1001 : ram_a[addr_a[0:9]][18:19] <= data_a[0:1];
          4'b1010 : ram_a[addr_a[0:9]][20:21] <= data_a[0:1];
          4'b1011 : ram_a[addr_a[0:9]][22:23] <= data_a[0:1];
          4'b1100 : ram_a[addr_a[0:9]][24:25] <= data_a[0:1];
          4'b1101 : ram_a[addr_a[0:9]][26:27] <= data_a[0:1];
          4'b1110 : ram_a[addr_a[0:9]][28:29] <= data_a[0:1];
          4'b1111 : ram_a[addr_a[0:9]][30:31] <= data_a[0:1];
        endcase
      end else begin
        case (addr_a[10:13])
          4'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];
          4'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];
          4'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];
          4'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];
          4'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];
          4'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];
          4'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];
          4'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];
          4'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];
          4'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];
          4'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];
          4'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];
          4'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];
          4'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];
          4'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];
          4'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];
        endcase
      end

    end else if (4'b0110 == mode) begin
      if (we_a) begin
        ram_a[addr_a[0:9]][addr_a[10:14]] = data_a[0:0];
      end else begin
        q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];
      end

    end else if (4'b0111 == mode) begin 
      if (we_a) begin
        ram_a[addr_a[0:9]] <= data_a;
        q_a <= data_a;
      end else begin
        q_a <= ram_a[addr_a[0:9]];
      end
      
      if (we_b) begin
        ram_b[addr_b[0:9]] <= data_b;
        q_b <= data_b;
      end else begin
        q_b <= ram_b[addr_b[0:9]];
      end

    end else if (4'b1000 == mode) begin
      if (we_a) begin
        case (addr_a[10:10])
          1'b0 : ram_a[addr_a[0:9]][0:15] <= data_a;
          1'b1 : ram_a[addr_a[0:9]][16:31] <= data_a;
        endcase
      end else begin
        case (addr_a[10:10])
          1'b0 : q_a <= ram_a[addr_a[0:9]][0:15];
          1'b1 : q_a <= ram_a[addr_a[0:9]][16:31];
        endcase
      end

      if (we_b) begin
        case (addr_b[10:10])
          1'b0 : ram_b[addr_b[0:9]][0:15] <= data_b;
          1'b1 : ram_b[addr_b[0:9]][16:31] <= data_b;
        endcase
      end else begin
        case (addr_b[10:10])
          1'b0 : q_b <= ram_b[addr_b[0:9]][0:15];
          1'b1 : q_b <= ram_b[addr_b[0:9]][16:31];
        endcase
      end

    end else if (4'b1001 == mode) begin
      if (we_a) begin
        case (addr_a[10:11])
          2'b00 : ram_a[addr_a[0:9]][0:7] <= data_a[0:7];
          2'b01 : ram_a[addr_a[0:9]][8:15] <= data_a[0:7];
          2'b10 : ram_a[addr_a[0:9]][16:23] <= data_a[0:7];
          2'b11 : ram_a[addr_a[0:9]][24:31] <= data_a[0:7];
        endcase
      end else begin
        case (addr_a[10:11])
          2'b00 : q_a <= ram_a[addr_a[0:9]][0:7];
          2'b01 : q_a <= ram_a[addr_a[0:9]][8:15];
          2'b10 : q_a <= ram_a[addr_a[0:9]][16:23];
          2'b11 : q_a <= ram_a[addr_a[0:9]][24:31];
        endcase
      end

      if (we_b) begin
        case (addr_b[10:11])
          2'b00 : ram_b[addr_b[0:9]][0:7] <= data_b[0:7];
          2'b01 : ram_b[addr_b[0:9]][8:15] <= data_b[0:7];
          2'b10 : ram_b[addr_b[0:9]][16:23] <= data_b[0:7];
          2'b11 : ram_b[addr_b[0:9]][24:31] <= data_b[0:7];
        endcase
      end else begin
        case (addr_b[10:11])
          2'b00 : q_b <= ram_b[addr_b[0:9]][0:7];
          2'b01 : q_b <= ram_b[addr_b[0:9]][8:15];
          2'b10 : q_b <= ram_b[addr_b[0:9]][16:23];
          2'b11 : q_b <= ram_b[addr_b[0:9]][24:31];
        endcase
      end

    end else if (4'b1011 == mode) begin
      if (we_a) begin
        case (addr_a[10:12])
          3'b000 : ram_a[addr_a[0:9]][0:3] <= data_a[0:3];
          3'b001 : ram_a[addr_a[0:9]][4:7] <= data_a[0:3];
          3'b010 : ram_a[addr_a[0:9]][8:11] <= data_a[0:3];
          3'b011 : ram_a[addr_a[0:9]][12:15] <= data_a[0:3];
          3'b100 : ram_a[addr_a[0:9]][16:19] <= data_a[0:3];
          3'b101 : ram_a[addr_a[0:9]][20:23] <= data_a[0:3];
          3'b110 : ram_a[addr_a[0:9]][24:27] <= data_a[0:3];
          3'b111 : ram_a[addr_a[0:9]][28:31] <= data_a[0:3];
        endcase
      end else begin
        case (addr_a[10:12])
          3'b000 : q_a <= ram_a[addr_a[0:9]][0:3];
          3'b001 : q_a <= ram_a[addr_a[0:9]][4:7];
          3'b010 : q_a <= ram_a[addr_a[0:9]][8:11];
          3'b011 : q_a <= ram_a[addr_a[0:9]][12:15];
          3'b100 : q_a <= ram_a[addr_a[0:9]][16:19];
          3'b101 : q_a <= ram_a[addr_a[0:9]][20:23];
          3'b110 : q_a <= ram_a[addr_a[0:9]][24:27];
          3'b111 : q_a <= ram_a[addr_a[0:9]][28:31];
        endcase
      end
      if (we_b) begin
        case (addr_b[10:12])
          3'b000 : ram_b[addr_b[0:9]][0:3] <= data_b[0:3];
          3'b001 : ram_b[addr_b[0:9]][4:7] <= data_b[0:3];
          3'b010 : ram_b[addr_b[0:9]][8:11] <= data_b[0:3];
          3'b011 : ram_b[addr_b[0:9]][12:15] <= data_b[0:3];
          3'b100 : ram_b[addr_b[0:9]][16:19] <= data_b[0:3];
          3'b101 : ram_b[addr_b[0:9]][20:23] <= data_b[0:3];
          3'b110 : ram_b[addr_b[0:9]][24:27] <= data_b[0:3];
          3'b111 : ram_b[addr_b[0:9]][28:31] <= data_b[0:3];
        endcase
      end else begin
        case (addr_b[10:12])
          3'b000 : q_b <= ram_b[addr_b[0:9]][0:3];
          3'b001 : q_b <= ram_b[addr_b[0:9]][4:7];
          3'b010 : q_b <= ram_b[addr_b[0:9]][8:11];
          3'b011 : q_b <= ram_b[addr_b[0:9]][12:15];
          3'b100 : q_b <= ram_b[addr_b[0:9]][16:19];
          3'b101 : q_b <= ram_b[addr_b[0:9]][20:23];
          3'b110 : q_b <= ram_b[addr_b[0:9]][24:27];
          3'b111 : q_b <= ram_b[addr_b[0:9]][28:31];
        endcase
      end

    end else if (4'b1100 == mode) begin
      if (we_a) begin
        case (addr_a[10:13])
          4'b0000 : ram_a[addr_a[0:9]][0:1] <= data_a[0:1];
          4'b0001 : ram_a[addr_a[0:9]][2:3] <= data_a[0:1];
          4'b0010 : ram_a[addr_a[0:9]][4:5] <= data_a[0:1];
          4'b0011 : ram_a[addr_a[0:9]][6:7] <= data_a[0:1];
          4'b0100 : ram_a[addr_a[0:9]][8:9] <= data_a[0:1];
          4'b0101 : ram_a[addr_a[0:9]][10:11] <= data_a[0:1];
          4'b0110 : ram_a[addr_a[0:9]][12:13] <= data_a[0:1];
          4'b0111 : ram_a[addr_a[0:9]][14:15] <= data_a[0:1];
          4'b1000 : ram_a[addr_a[0:9]][16:17] <= data_a[0:1];
          4'b1001 : ram_a[addr_a[0:9]][18:19] <= data_a[0:1];
          4'b1010 : ram_a[addr_a[0:9]][20:21] <= data_a[0:1];
          4'b1011 : ram_a[addr_a[0:9]][22:23] <= data_a[0:1];
          4'b1100 : ram_a[addr_a[0:9]][24:25] <= data_a[0:1];
          4'b1101 : ram_a[addr_a[0:9]][26:27] <= data_a[0:1];
          4'b1110 : ram_a[addr_a[0:9]][28:29] <= data_a[0:1];
          4'b1111 : ram_a[addr_a[0:9]][30:31] <= data_a[0:1];
        endcase
      end else begin
        case (addr_a[10:13])
          4'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];
          4'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];
          4'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];
          4'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];
          4'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];
          4'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];
          4'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];
          4'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];
          4'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];
          4'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];
          4'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];
          4'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];
          4'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];
          4'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];
          4'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];
          4'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];
        endcase
      end
      if (we_b) begin
        case (addr_b[10:13])
          4'b0000 : ram_b[addr_b[0:9]][0:1] <= data_b[0:1];
          4'b0001 : ram_b[addr_b[0:9]][2:3] <= data_b[0:1];
          4'b0010 : ram_b[addr_b[0:9]][4:5] <= data_b[0:1];
          4'b0011 : ram_b[addr_b[0:9]][6:7] <= data_b[0:1];
          4'b0100 : ram_b[addr_b[0:9]][8:9] <= data_b[0:1];
          4'b0101 : ram_b[addr_b[0:9]][10:11] <= data_b[0:1];
          4'b0110 : ram_b[addr_b[0:9]][12:13] <= data_b[0:1];
          4'b0111 : ram_b[addr_b[0:9]][14:15] <= data_b[0:1];
          4'b1000 : ram_b[addr_b[0:9]][16:17] <= data_b[0:1];
          4'b1001 : ram_b[addr_b[0:9]][18:19] <= data_b[0:1];
          4'b1010 : ram_b[addr_b[0:9]][20:21] <= data_b[0:1];
          4'b1011 : ram_b[addr_b[0:9]][22:23] <= data_b[0:1];
          4'b1100 : ram_b[addr_b[0:9]][24:25] <= data_b[0:1];
          4'b1101 : ram_b[addr_b[0:9]][26:27] <= data_b[0:1];
          4'b1110 : ram_b[addr_b[0:9]][28:29] <= data_b[0:1];
          4'b1111 : ram_b[addr_b[0:9]][30:31] <= data_b[0:1];
        endcase
      end else begin
        case (addr_b[10:13])
          4'b0000 : q_b <= ram_b[addr_b[0:9]][0:1];
          4'b0001 : q_b <= ram_b[addr_b[0:9]][2:3];
          4'b0010 : q_b <= ram_b[addr_b[0:9]][4:5];
          4'b0011 : q_b <= ram_b[addr_b[0:9]][6:7];
          4'b0100 : q_b <= ram_b[addr_b[0:9]][8:9];
          4'b0101 : q_b <= ram_b[addr_b[0:9]][10:11];
          4'b0110 : q_b <= ram_b[addr_b[0:9]][12:13];
          4'b0111 : q_b <= ram_b[addr_b[0:9]][14:15];
          4'b1000 : q_b <= ram_b[addr_b[0:9]][16:17];
          4'b1001 : q_b <= ram_b[addr_b[0:9]][18:19];
          4'b1010 : q_b <= ram_b[addr_b[0:9]][20:21];
          4'b1011 : q_b <= ram_b[addr_b[0:9]][22:23];
          4'b1100 : q_b <= ram_b[addr_b[0:9]][24:25];
          4'b1101 : q_b <= ram_b[addr_b[0:9]][26:27];
          4'b1110 : q_b <= ram_b[addr_b[0:9]][28:29];
          4'b1111 : q_b <= ram_b[addr_b[0:9]][30:31];
        endcase
      end

    end else if (4'b1101 == mode) begin
      if (we_a) begin
        ram_a[addr_a[0:9]][addr_a[10:14]] = data_a[0:0];
      end else begin
        q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];
      end
      if (we_b) begin
        ram_b[addr_b[0:9]][addr_b[10:14]] = data_b[0:0];
      end else begin
        q_b <= ram_b[addr_b[0:9]][addr_b[10:14]];
      end
    end
  end
endmodule
module frac_mem_32k (
  input [0:14] addr_a,
  input [0:14] addr_b,
  input [0:31] data_a,
  input [0:31] data_b,
  input we_a,
  input we_b,
  output reg [0:31] q_a,
  output reg [0:31] q_b,
  input clk,
  input [0:3] mode);


  reg [0:9] ram_a [0:31];
  reg [0:9] ram_b [0:31];

  always @(posedge clk) begin

    if (4'b0000 == mode) begin 
      if (we_a) begin
        ram_a[addr_a[0:8]] <= data_a;
        ram_b[addr_a[0:8]] <= data_b;
        q_a <= data_a;
        q_b <= data_b;
      end else begin
        q_a <= ram_a[addr_a[0:8]];
        q_b <= ram_b[addr_a[0:8]];
      end 

    end else if (4'b0001 == mode) begin
      if (we_a) begin
        ram_a[addr_a[0:9]] <= data_a;
      end else begin
        q_a <= ram_a[addr_a[0:9]];
      end

    end else if (4'b0010 == mode) begin
      if (we_a) begin
        case (addr_a[10:10])
          1'b0 : ram_a[addr_a[0:9]][0:15] <= data_a[0:15];
          1'b1 : ram_a[addr_a[0:9]][16:31] <= data_a[0:15];
        endcase
      end else begin
        case (addr_a[10:10])
          1'b0 : q_a <= ram_a[addr_a[0:9]][0:15];
          1'b1 : q_a <= ram_a[addr_a[0:9]][16:31];
        endcase
      end

    end else if (4'b0011 == mode) begin
      if (we_a) begin
        case (addr_a[10:11])
          2'b00 : ram_a[addr_a[0:9]][0:7] <= data_a[0:7];
          2'b01 : ram_a[addr_a[0:9]][8:15] <= data_a[0:7];
          2'b10 : ram_a[addr_a[0:9]][16:23] <= data_a[0:7];
          2'b11 : ram_a[addr_a[0:9]][24:31] <= data_a[0:7];
        endcase
      end else begin
        case (addr_a[10:11])
          2'b00 : q_a <= ram_a[addr_a[0:9]][0:7];
          2'b01 : q_a <= ram_a[addr_a[0:9]][8:15];
          2'b10 : q_a <= ram_a[addr_a[0:9]][16:23];
          2'b11 : q_a <= ram_a[addr_a[0:9]][24:31];
        endcase
      end

    end else if (4'b0100 == mode) begin
      if (we_a) begin
        case (addr_a[10:12])
          3'b000 : ram_a[addr_a[0:9]][0:3] <= data_a[0:3];
          3'b001 : ram_a[addr_a[0:9]][4:7] <= data_a[0:3];
          3'b010 : ram_a[addr_a[0:9]][8:11] <= data_a[0:3];
          3'b011 : ram_a[addr_a[0:9]][12:15] <= data_a[0:3];
          3'b100 : ram_a[addr_a[0:9]][16:19] <= data_a[0:3];
          3'b101 : ram_a[addr_a[0:9]][20:23] <= data_a[0:3];
          3'b110 : ram_a[addr_a[0:9]][24:27] <= data_a[0:3];
          3'b111 : ram_a[addr_a[0:9]][28:31] <= data_a[0:3];
        endcase
      end else begin
        case (addr_a[10:12])
          3'b000 : q_a <= ram_a[addr_a[0:9]][0:3];
          3'b001 : q_a <= ram_a[addr_a[0:9]][4:7];
          3'b010 : q_a <= ram_a[addr_a[0:9]][8:11];
          3'b011 : q_a <= ram_a[addr_a[0:9]][12:15];
          3'b100 : q_a <= ram_a[addr_a[0:9]][16:19];
          3'b101 : q_a <= ram_a[addr_a[0:9]][20:23];
          3'b110 : q_a <= ram_a[addr_a[0:9]][24:27];
          3'b111 : q_a <= ram_a[addr_a[0:9]][28:31];
        endcase
      end

    end else if (4'b0101 == mode) begin
      if (we_a) begin
        case (addr_a[10:13])
          4'b0000 : ram_a[addr_a[0:9]][0:1] <= data_a[0:1];
          4'b0001 : ram_a[addr_a[0:9]][2:3] <= data_a[0:1];
          4'b0010 : ram_a[addr_a[0:9]][4:5] <= data_a[0:1];
          4'b0011 : ram_a[addr_a[0:9]][6:7] <= data_a[0:1];
          4'b0100 : ram_a[addr_a[0:9]][8:9] <= data_a[0:1];
          4'b0101 : ram_a[addr_a[0:9]][10:11] <= data_a[0:1];
          4'b0110 : ram_a[addr_a[0:9]][12:13] <= data_a[0:1];
          4'b0111 : ram_a[addr_a[0:9]][14:15] <= data_a[0:1];
          4'b1000 : ram_a[addr_a[0:9]][16:17] <= data_a[0:1];
          4'b1001 : ram_a[addr_a[0:9]][18:19] <= data_a[0:1];
          4'b1010 : ram_a[addr_a[0:9]][20:21] <= data_a[0:1];
          4'b1011 : ram_a[addr_a[0:9]][22:23] <= data_a[0:1];
          4'b1100 : ram_a[addr_a[0:9]][24:25] <= data_a[0:1];
          4'b1101 : ram_a[addr_a[0:9]][26:27] <= data_a[0:1];
          4'b1110 : ram_a[addr_a[0:9]][28:29] <= data_a[0:1];
          4'b1111 : ram_a[addr_a[0:9]][30:31] <= data_a[0:1];
        endcase
      end else begin
        case (addr_a[10:13])
          4'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];
          4'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];
          4'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];
          4'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];
          4'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];
          4'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];
          4'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];
          4'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];
          4'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];
          4'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];
          4'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];
          4'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];
          4'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];
          4'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];
          4'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];
          4'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];
        endcase
      end

    end else if (4'b0110 == mode) begin
      if (we_a) begin
        ram_a[addr_a[0:9]][addr_a[10:14]] = data_a[0:0];
      end else begin
        q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];
      end

    end else if (4'b0111 == mode) begin 
      if (we_a) begin
        ram_a[addr_a[0:9]] <= data_a;
        q_a <= data_a;
      end else begin
        q_a <= ram_a[addr_a[0:9]];
      end
      
      if (we_b) begin
        ram_b[addr_b[0:9]] <= data_b;
        q_b <= data_b;
      end else begin
        q_b <= ram_b[addr_b[0:9]];
      end

    end else if (4'b1000 == mode) begin
      if (we_a) begin
        case (addr_a[10:10])
          1'b0 : ram_a[addr_a[0:9]][0:15] <= data_a;
          1'b1 : ram_a[addr_a[0:9]][16:31] <= data_a;
        endcase
      end else begin
        case (addr_a[10:10])
          1'b0 : q_a <= ram_a[addr_a[0:9]][0:15];
          1'b1 : q_a <= ram_a[addr_a[0:9]][16:31];
        endcase
      end

      if (we_b) begin
        case (addr_b[10:10])
          1'b0 : ram_b[addr_b[0:9]][0:15] <= data_b;
          1'b1 : ram_b[addr_b[0:9]][16:31] <= data_b;
        endcase
      end else begin
        case (addr_b[10:10])
          1'b0 : q_b <= ram_b[addr_b[0:9]][0:15];
          1'b1 : q_b <= ram_b[addr_b[0:9]][16:31];
        endcase
      end

    end else if (4'b1001 == mode) begin
      if (we_a) begin
        case (addr_a[10:11])
          2'b00 : ram_a[addr_a[0:9]][0:7] <= data_a[0:7];
          2'b01 : ram_a[addr_a[0:9]][8:15] <= data_a[0:7];
          2'b10 : ram_a[addr_a[0:9]][16:23] <= data_a[0:7];
          2'b11 : ram_a[addr_a[0:9]][24:31] <= data_a[0:7];
        endcase
      end else begin
        case (addr_a[10:11])
          2'b00 : q_a <= ram_a[addr_a[0:9]][0:7];
          2'b01 : q_a <= ram_a[addr_a[0:9]][8:15];
          2'b10 : q_a <= ram_a[addr_a[0:9]][16:23];
          2'b11 : q_a <= ram_a[addr_a[0:9]][24:31];
        endcase
      end

      if (we_b) begin
        case (addr_b[10:11])
          2'b00 : ram_b[addr_b[0:9]][0:7] <= data_b[0:7];
          2'b01 : ram_b[addr_b[0:9]][8:15] <= data_b[0:7];
          2'b10 : ram_b[addr_b[0:9]][16:23] <= data_b[0:7];
          2'b11 : ram_b[addr_b[0:9]][24:31] <= data_b[0:7];
        endcase
      end else begin
        case (addr_b[10:11])
          2'b00 : q_b <= ram_b[addr_b[0:9]][0:7];
          2'b01 : q_b <= ram_b[addr_b[0:9]][8:15];
          2'b10 : q_b <= ram_b[addr_b[0:9]][16:23];
          2'b11 : q_b <= ram_b[addr_b[0:9]][24:31];
        endcase
      end

    end else if (4'b1011 == mode) begin
      if (we_a) begin
        case (addr_a[10:12])
          3'b000 : ram_a[addr_a[0:9]][0:3] <= data_a[0:3];
          3'b001 : ram_a[addr_a[0:9]][4:7] <= data_a[0:3];
          3'b010 : ram_a[addr_a[0:9]][8:11] <= data_a[0:3];
          3'b011 : ram_a[addr_a[0:9]][12:15] <= data_a[0:3];
          3'b100 : ram_a[addr_a[0:9]][16:19] <= data_a[0:3];
          3'b101 : ram_a[addr_a[0:9]][20:23] <= data_a[0:3];
          3'b110 : ram_a[addr_a[0:9]][24:27] <= data_a[0:3];
          3'b111 : ram_a[addr_a[0:9]][28:31] <= data_a[0:3];
        endcase
      end else begin
        case (addr_a[10:12])
          3'b000 : q_a <= ram_a[addr_a[0:9]][0:3];
          3'b001 : q_a <= ram_a[addr_a[0:9]][4:7];
          3'b010 : q_a <= ram_a[addr_a[0:9]][8:11];
          3'b011 : q_a <= ram_a[addr_a[0:9]][12:15];
          3'b100 : q_a <= ram_a[addr_a[0:9]][16:19];
          3'b101 : q_a <= ram_a[addr_a[0:9]][20:23];
          3'b110 : q_a <= ram_a[addr_a[0:9]][24:27];
          3'b111 : q_a <= ram_a[addr_a[0:9]][28:31];
        endcase
      end
      if (we_b) begin
        case (addr_b[10:12])
          3'b000 : ram_b[addr_b[0:9]][0:3] <= data_b[0:3];
          3'b001 : ram_b[addr_b[0:9]][4:7] <= data_b[0:3];
          3'b010 : ram_b[addr_b[0:9]][8:11] <= data_b[0:3];
          3'b011 : ram_b[addr_b[0:9]][12:15] <= data_b[0:3];
          3'b100 : ram_b[addr_b[0:9]][16:19] <= data_b[0:3];
          3'b101 : ram_b[addr_b[0:9]][20:23] <= data_b[0:3];
          3'b110 : ram_b[addr_b[0:9]][24:27] <= data_b[0:3];
          3'b111 : ram_b[addr_b[0:9]][28:31] <= data_b[0:3];
        endcase
      end else begin
        case (addr_b[10:12])
          3'b000 : q_b <= ram_b[addr_b[0:9]][0:3];
          3'b001 : q_b <= ram_b[addr_b[0:9]][4:7];
          3'b010 : q_b <= ram_b[addr_b[0:9]][8:11];
          3'b011 : q_b <= ram_b[addr_b[0:9]][12:15];
          3'b100 : q_b <= ram_b[addr_b[0:9]][16:19];
          3'b101 : q_b <= ram_b[addr_b[0:9]][20:23];
          3'b110 : q_b <= ram_b[addr_b[0:9]][24:27];
          3'b111 : q_b <= ram_b[addr_b[0:9]][28:31];
        endcase
      end

    end else if (4'b1100 == mode) begin
      if (we_a) begin
        case (addr_a[10:13])
          4'b0000 : ram_a[addr_a[0:9]][0:1] <= data_a[0:1];
          4'b0001 : ram_a[addr_a[0:9]][2:3] <= data_a[0:1];
          4'b0010 : ram_a[addr_a[0:9]][4:5] <= data_a[0:1];
          4'b0011 : ram_a[addr_a[0:9]][6:7] <= data_a[0:1];
          4'b0100 : ram_a[addr_a[0:9]][8:9] <= data_a[0:1];
          4'b0101 : ram_a[addr_a[0:9]][10:11] <= data_a[0:1];
          4'b0110 : ram_a[addr_a[0:9]][12:13] <= data_a[0:1];
          4'b0111 : ram_a[addr_a[0:9]][14:15] <= data_a[0:1];
          4'b1000 : ram_a[addr_a[0:9]][16:17] <= data_a[0:1];
          4'b1001 : ram_a[addr_a[0:9]][18:19] <= data_a[0:1];
          4'b1010 : ram_a[addr_a[0:9]][20:21] <= data_a[0:1];
          4'b1011 : ram_a[addr_a[0:9]][22:23] <= data_a[0:1];
          4'b1100 : ram_a[addr_a[0:9]][24:25] <= data_a[0:1];
          4'b1101 : ram_a[addr_a[0:9]][26:27] <= data_a[0:1];
          4'b1110 : ram_a[addr_a[0:9]][28:29] <= data_a[0:1];
          4'b1111 : ram_a[addr_a[0:9]][30:31] <= data_a[0:1];
        endcase
      end else begin
        case (addr_a[10:13])
          4'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];
          4'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];
          4'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];
          4'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];
          4'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];
          4'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];
          4'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];
          4'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];
          4'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];
          4'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];
          4'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];
          4'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];
          4'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];
          4'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];
          4'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];
          4'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];
        endcase
      end
      if (we_b) begin
        case (addr_b[10:13])
          4'b0000 : ram_b[addr_b[0:9]][0:1] <= data_b[0:1];
          4'b0001 : ram_b[addr_b[0:9]][2:3] <= data_b[0:1];
          4'b0010 : ram_b[addr_b[0:9]][4:5] <= data_b[0:1];
          4'b0011 : ram_b[addr_b[0:9]][6:7] <= data_b[0:1];
          4'b0100 : ram_b[addr_b[0:9]][8:9] <= data_b[0:1];
          4'b0101 : ram_b[addr_b[0:9]][10:11] <= data_b[0:1];
          4'b0110 : ram_b[addr_b[0:9]][12:13] <= data_b[0:1];
          4'b0111 : ram_b[addr_b[0:9]][14:15] <= data_b[0:1];
          4'b1000 : ram_b[addr_b[0:9]][16:17] <= data_b[0:1];
          4'b1001 : ram_b[addr_b[0:9]][18:19] <= data_b[0:1];
          4'b1010 : ram_b[addr_b[0:9]][20:21] <= data_b[0:1];
          4'b1011 : ram_b[addr_b[0:9]][22:23] <= data_b[0:1];
          4'b1100 : ram_b[addr_b[0:9]][24:25] <= data_b[0:1];
          4'b1101 : ram_b[addr_b[0:9]][26:27] <= data_b[0:1];
          4'b1110 : ram_b[addr_b[0:9]][28:29] <= data_b[0:1];
          4'b1111 : ram_b[addr_b[0:9]][30:31] <= data_b[0:1];
        endcase
      end else begin
        case (addr_b[10:13])
          4'b0000 : q_b <= ram_b[addr_b[0:9]][0:1];
          4'b0001 : q_b <= ram_b[addr_b[0:9]][2:3];
          4'b0010 : q_b <= ram_b[addr_b[0:9]][4:5];
          4'b0011 : q_b <= ram_b[addr_b[0:9]][6:7];
          4'b0100 : q_b <= ram_b[addr_b[0:9]][8:9];
          4'b0101 : q_b <= ram_b[addr_b[0:9]][10:11];
          4'b0110 : q_b <= ram_b[addr_b[0:9]][12:13];
          4'b0111 : q_b <= ram_b[addr_b[0:9]][14:15];
          4'b1000 : q_b <= ram_b[addr_b[0:9]][16:17];
          4'b1001 : q_b <= ram_b[addr_b[0:9]][18:19];
          4'b1010 : q_b <= ram_b[addr_b[0:9]][20:21];
          4'b1011 : q_b <= ram_b[addr_b[0:9]][22:23];
          4'b1100 : q_b <= ram_b[addr_b[0:9]][24:25];
          4'b1101 : q_b <= ram_b[addr_b[0:9]][26:27];
          4'b1110 : q_b <= ram_b[addr_b[0:9]][28:29];
          4'b1111 : q_b <= ram_b[addr_b[0:9]][30:31];
        endcase
      end

    end else if (4'b1101 == mode) begin
      if (we_a) begin
        ram_a[addr_a[0:9]][addr_a[10:14]] = data_a[0:0];
      end else begin
        q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];
      end
      if (we_b) begin
        ram_b[addr_b[0:9]][addr_b[10:14]] = data_b[0:0];
      end else begin
        q_b <= ram_b[addr_b[0:9]][addr_b[10:14]];
      end
    end
  end
endmodule