data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v
'utf-8' codec can't decode byte 0xc1 in position 1843: invalid start byte
1: b'%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:36: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v.v\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:47: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] exception_new_pc,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegBus] exception_new_pc,\n                   ^\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:51: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] branch_target_address_i,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:51: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] branch_target_address_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:54: Define or directive not defined: \'`PhyAddrBus\'\n input wire[`PhyAddrBus] next_inst_phy_addr_i,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:58: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[`RegBus] pc,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:58: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] pc,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:59: Define or directive not defined: \'`PhyAddrBus\'\n output reg[`PhyAddrBus] inst_phy_addr_o,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:65: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] next_inst_vir_addr_o,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:65: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] next_inst_vir_addr_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:69: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[`ExceptionTypeBus] excepttype_o\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:69: Define or directive not defined: \'`ExceptionTypeBus\'\n output reg[`ExceptionTypeBus] excepttype_o\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:72: Define or directive not defined: \'`ChipEnable\'\n assign pc_ce_o = `ChipEnable;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:75: Define or directive not defined: \'`RstEnable\'\n  if (rst_n == `RstEnable)\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:76: Define or directive not defined: \'`StartInstAddr\'\n   next_inst_vir_addr_o <= `StartInstAddr;\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:77: Define or directive not defined: \'`ChipDisable\'\n  else if (ce == `ChipDisable)\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:78: Define or directive not defined: \'`StartInstAddr\'\n   next_inst_vir_addr_o <= `StartInstAddr;\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:79: Define or directive not defined: \'`Flush\'\n  else if(flush == `Flush)\n                   ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:83: Define or directive not defined: \'`Branch\'\n   if(branch_flag_i == `Branch)\n                       ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:89: Define or directive not defined: \'`ExceptionTypeBus\'\n reg[`ExceptionTypeBus] excepttype;\n     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:91: Define or directive not defined: \'`RstEnable\'\n  if (rst_n == `RstEnable)\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:93: Define or directive not defined: \'`ZeroWord\'\n   excepttype <= `ZeroWord;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:97: Define or directive not defined: \'`ZeroWord\'\n   excepttype <= `ZeroWord;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:99: Define or directive not defined: \'`Exception_INST_MISALIGNED\'\n   excepttype[`Exception_INST_MISALIGNED] <= (next_inst_vir_addr_o[1:0] != 2\'b00);\n              ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:100: Define or directive not defined: \'`Exception_INST_ACCESS_FAULT\'\n   excepttype[`Exception_INST_ACCESS_FAULT] <= next_inst_tlb_exception_i;\n              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:105: Define or directive not defined: \'`RstEnable\'\n  if (rst_n == `RstEnable)\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:107: Define or directive not defined: \'`StartInstAddr\'\n   pc <= `StartInstAddr;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:109: Define or directive not defined: \'`ChipDisable\'\n   ce <= `ChipDisable;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:110: Define or directive not defined: \'`ZeroWord\'\n   inst_phy_addr_o <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:111: Define or directive not defined: \'`ZeroWord\'\n   excepttype_o <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:113: Define or directive not defined: \'`Flush\'\n  else if(flush == `Flush)\n                   ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:117: Define or directive not defined: \'`ChipEnable\'\n   ce <= `ChipEnable;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:121: Define or directive not defined: \'`NoStop\'\n  else if(stall[0] == `NoStop)\n                      ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/pc_reg.v:125: Define or directive not defined: \'`ChipEnable\'\n   ce <= `ChipEnable;\n         ^~~~~~~~~~~\n%Error: Exiting due to 35 error(s)\n'
module pc_reg(

	input wire clk,
	input wire rst_n,


	input wire[5:0] stall,

	input wire flush,
	input wire[`RegBus] exception_new_pc,


	input wire branch_flag_i,
	input wire[`RegBus] branch_target_address_i,


	input wire[`PhyAddrBus] next_inst_phy_addr_i,
	input wire next_inst_tlb_exception_i,


	output reg[`RegBus] pc,
	output reg[`PhyAddrBus] inst_phy_addr_o,
	

	output reg ce,


	output reg[`RegBus] next_inst_vir_addr_o,
	output wire pc_ce_o,


	output reg[`ExceptionTypeBus] excepttype_o
);

	assign pc_ce_o = `ChipEnable;
	
	always @ (*)
		if (rst_n == `RstEnable)
			next_inst_vir_addr_o <= `StartInstAddr;
		else if (ce == `ChipDisable)
			next_inst_vir_addr_o <= `StartInstAddr;
		else if(flush == `Flush)
			next_inst_vir_addr_o <= exception_new_pc;
		else
		begin
			if(branch_flag_i == `Branch)
				next_inst_vir_addr_o <= branch_target_address_i;
			else
	 			next_inst_vir_addr_o <= pc + 4'h4;
	 	end

	reg[`ExceptionTypeBus] excepttype;
	always @(*)
		if (rst_n == `RstEnable)
		begin
			excepttype <= `ZeroWord;
		end
		else
		begin
			excepttype <= `ZeroWord;

			excepttype[`Exception_INST_MISALIGNED] <= (next_inst_vir_addr_o[1:0] != 2'b00);
			excepttype[`Exception_INST_ACCESS_FAULT] <= next_inst_tlb_exception_i;
		end

	always @ (posedge clk or negedge rst_n)
	begin
		if (rst_n == `RstEnable)
		begin
			pc <= `StartInstAddr;

			ce <= `ChipDisable;
			inst_phy_addr_o <= `ZeroWord;
			excepttype_o <= `ZeroWord;
		end
		else if(flush == `Flush)
		begin
			pc <= next_inst_vir_addr_o;

			ce <= `ChipEnable;
			inst_phy_addr_o <= next_inst_phy_addr_i;
			excepttype_o <= excepttype;
		end
		else if(stall[0] == `NoStop)
		begin
			pc <= next_inst_vir_addr_o;

			ce <= `ChipEnable;
			inst_phy_addr_o <= next_inst_phy_addr_i;
			excepttype_o <= excepttype;
		end

	end
	
endmodule
module pc_reg(

	input wire clk,
	input wire rst_n,


	input wire[5:0] stall,

	input wire flush,
	input wire[`RegBus] exception_new_pc,


	input wire branch_flag_i,
	input wire[`RegBus] branch_target_address_i,


	input wire[`PhyAddrBus] next_inst_phy_addr_i,
	input wire next_inst_tlb_exception_i,


	output reg[`RegBus] pc,
	output reg[`PhyAddrBus] inst_phy_addr_o,
	

	output reg ce,


	output reg[`RegBus] next_inst_vir_addr_o,
	output wire pc_ce_o,


	output reg[`ExceptionTypeBus] excepttype_o
);


	assign pc_ce_o = `ChipEnable;
	
	always @ (*)
		if (rst_n == `RstEnable)
			next_inst_vir_addr_o <= `StartInstAddr;
		else if (ce == `ChipDisable)
			next_inst_vir_addr_o <= `StartInstAddr;
		else if(flush == `Flush)
			next_inst_vir_addr_o <= exception_new_pc;
		else
		begin
			if(branch_flag_i == `Branch)
				next_inst_vir_addr_o <= branch_target_address_i;
			else
	 			next_inst_vir_addr_o <= pc + 4'h4;
	 	end

	reg[`ExceptionTypeBus] excepttype;
	always @(*)
		if (rst_n == `RstEnable)
		begin
			excepttype <= `ZeroWord;
		end
		else
		begin
			excepttype <= `ZeroWord;

			excepttype[`Exception_INST_MISALIGNED] <= (next_inst_vir_addr_o[1:0] != 2'b00);
			excepttype[`Exception_INST_ACCESS_FAULT] <= next_inst_tlb_exception_i;
		end

	always @ (posedge clk or negedge rst_n)
	begin
		if (rst_n == `RstEnable)
		begin
			pc <= `StartInstAddr;

			ce <= `ChipDisable;
			inst_phy_addr_o <= `ZeroWord;
			excepttype_o <= `ZeroWord;
		end
		else if(flush == `Flush)
		begin
			pc <= next_inst_vir_addr_o;

			ce <= `ChipEnable;
			inst_phy_addr_o <= next_inst_phy_addr_i;
			excepttype_o <= excepttype;
		end
		else if(stall[0] == `NoStop)
		begin
			pc <= next_inst_vir_addr_o;

			ce <= `ChipEnable;
			inst_phy_addr_o <= next_inst_phy_addr_i;
			excepttype_o <= excepttype;
		end

	end
	
endmodule