data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:66: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog,data/full_repos/permissive/19905110/timescale.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog,data/full_repos/permissive/19905110/timescale.v.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog,data/full_repos/permissive/19905110/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:67: Cannot find include file: eth_phy_defines.v\n`include "eth_phy_defines.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:68: Cannot find include file: tb_eth_defines.v\n`include "tb_eth_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:150: Define or directive not defined: \'`SUPPORTED_SPEED_AND_PORT\'\nwire   [15:9]  status_bit15_9 = `SUPPORTED_SPEED_AND_PORT;\n                                ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:150: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nwire   [15:9]  status_bit15_9 = `SUPPORTED_SPEED_AND_PORT;\n                                                         ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:151: Define or directive not defined: \'`EXTENDED_STATUS\'\nwire           status_bit8    = `EXTENDED_STATUS;\n                                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:151: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nwire           status_bit8    = `EXTENDED_STATUS;\n                                                ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:155: Define or directive not defined: \'`PHY_ID1\'\nwire   [15:0]  phy_id1        = `PHY_ID1;\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:155: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nwire   [15:0]  phy_id1        = `PHY_ID1;\n                                        ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:157: Define or directive not defined: \'`PHY_ID2\'\nwire   [15:0]  phy_id2        = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};\n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:157: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nwire   [15:0]  phy_id2        = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};\n                                         ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:157: Define or directive not defined: \'`MAN_MODEL_NUM\'\nwire   [15:0]  phy_id2        = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};\n                                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:157: Define or directive not defined: \'`MAN_REVISION_NUM\'\nwire   [15:0]  phy_id2        = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};\n                                                           ^~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:182: Unsupported: Ignoring delay on this delayed statement.\n    #1 rx_link_down_halfperiod = ({$random} % 243) + 13;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:203: Define or directive not defined: \'`LED_CFG1\'\nassign eth_speed = ( (control_bit14_10[13]) && !((`LED_CFG1) && (`LED_CFG2)) );\n                                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:203: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign eth_speed = ( (control_bit14_10[13]) && !((`LED_CFG1) && (`LED_CFG2)) );\n                                                           ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:203: Define or directive not defined: \'`LED_CFG2\'\nassign eth_speed = ( (control_bit14_10[13]) && !((`LED_CFG1) && (`LED_CFG2)) );\n                                                                 ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #7;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:229: Unsupported: Ignoring delay on this delayed statement.\n      #20 mtx_clk_o = ~mtx_clk_o;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:233: Unsupported: Ignoring delay on this delayed statement.\n      #200 mtx_clk_o = ~mtx_clk_o;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:242: Unsupported: Ignoring delay on this delayed statement.\n  #7;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:247: Unsupported: Ignoring delay on this delayed statement.\n      #20 mrx_clk_o = ~mrx_clk_o;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:251: Unsupported: Ignoring delay on this delayed statement.\n      #200 mrx_clk_o = ~mrx_clk_o;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:414: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:421: Unsupported: Ignoring delay on this delayed statement.\n      #4 md_put_reg_data_in = 1\'b0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:424: Unsupported: Ignoring delay on this delayed statement.\n        #1 md_transfer_cnt_reset = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:428: Unsupported: Ignoring delay on this delayed statement.\n        #1 md_transfer_cnt_reset = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:437: Unsupported: Ignoring delay on this delayed statement.\n        #4 md_put_reg_data_in = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:440: Unsupported: Ignoring delay on this delayed statement.\n          #1 md_transfer_cnt_reset = 1\'b0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:444: Unsupported: Ignoring delay on this delayed statement.\n          #1 md_transfer_cnt_reset = 1\'b1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:452: Unsupported: Ignoring delay on this delayed statement.\n            #10 $stop;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:458: Unsupported: Ignoring delay on this delayed statement.\n        #4 ;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:470: Unsupported: Ignoring delay on this delayed statement.\n          #10 $stop;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:477: Unsupported: Ignoring delay on this delayed statement.\n      #4;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:481: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:488: Unsupported: Ignoring delay on this delayed statement.\n        #10 $stop;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:504: Unsupported: Ignoring delay on this delayed statement.\n      #4;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:507: Unsupported: Ignoring delay on this delayed statement.\n        #1 md_io_rd_wr = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:511: Unsupported: Ignoring delay on this delayed statement.\n        #1 md_io_rd_wr = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:517: Unsupported: Ignoring delay on this delayed statement.\n      #4;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:520: Unsupported: Ignoring delay on this delayed statement.\n        #1 md_io_rd_wr = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:527: Unsupported: Ignoring delay on this delayed statement.\n        #1 md_io_rd_wr = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:538: Unsupported: Ignoring delay on this delayed statement.\n        #10 $stop;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:542: Unsupported: Ignoring delay on this delayed statement.\n        #1 md_get_phy_address = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:549: Unsupported: Ignoring delay on this delayed statement.\n      #4 md_get_phy_address = 1\'b0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:551: Unsupported: Ignoring delay on this delayed statement.\n      #1 md_get_reg_address = 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:558: Unsupported: Ignoring delay on this delayed statement.\n      #4 md_get_reg_address = 1\'b0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:559: Unsupported: Ignoring delay on this delayed statement.\n      #1 md_put_reg_data_out = 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:566: Unsupported: Ignoring delay on this delayed statement.\n      #4 md_put_reg_data_out = 1\'b0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:575: Unsupported: Ignoring delay on this delayed statement.\n          #10 $stop;\n          ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:577: Define or directive not defined: \'`ETH_PHY_ADDR\'\n        if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr)  \n                             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:577: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr)  \n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:593: Unsupported: Ignoring delay on this delayed statement.\n        #1 md_io_enable = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:602: Unsupported: Ignoring delay on this delayed statement.\n          #10 $stop;\n          ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:608: syntax error, unexpected else\n    else if (md_transfer_cnt == 48)\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:613: Unsupported: Ignoring delay on this delayed statement.\n        #1 md_get_reg_data_in = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:622: Unsupported: Ignoring delay on this delayed statement.\n          #10 $stop;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:627: Unsupported: Ignoring delay on this delayed statement.\n        #1 md_get_reg_data_in = 1\'b0;\n        ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:634: syntax error, unexpected else\n    else if (md_transfer_cnt == 64)\n    ^~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:640: Define or directive not defined: \'`ETH_PHY_ADDR\'\n        if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr)  \n                             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:640: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr)  \n                                          ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:655: syntax error, unexpected end\n      end\n      ^~~\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:726: Unsupported: Ignoring delay on this delayed statement.\n  #1 status_bit6_0[6] = no_preamble;\n  ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:802: Define or directive not defined: \'`LED_CFG1\'\n      control_bit14_10 <= #1 {1\'b0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 2\'b0};\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:802: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n      control_bit14_10 <= #1 {1\'b0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 2\'b0};\n                                               ^~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:802: Define or directive not defined: \'`LED_CFG2\'\n      control_bit14_10 <= #1 {1\'b0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 2\'b0};\n                                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:802: Define or directive not defined: \'`LED_CFG1\'\n      control_bit14_10 <= #1 {1\'b0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 2\'b0};\n                                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:804: Define or directive not defined: \'`LED_CFG3\'\n      control_bit8_0   <= #1 {`LED_CFG3, 8\'b0};\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:804: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      control_bit8_0   <= #1 {`LED_CFG3, 8\'b0};\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1160: Unsupported: Ignoring delay on this delayed statement.\n  #1 tx_mem_addr_in = tx_mem_address;\n  ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1191: syntax error, unexpected \'@\'\n      @(posedge mrx_clk_o);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1194: Unsupported: Ignoring delay on this delayed statement.\n        #1 mcrs_rx = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1196: Unsupported: Ignoring delay on this delayed statement.\n        #1 mcrs_rx = 0;\n        ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1197: syntax error, unexpected \'@\'\n      @(posedge mrx_clk_o);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1198: Unsupported: Ignoring delay on this delayed statement.\n      #1 mcrs_rx = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1199: Unsupported: Ignoring delay on this delayed statement.\n      #1 mrxdv_o = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1209: Unsupported: Ignoring delay on this delayed statement.\n        #1 mrxd_o = preamble_data[3:0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1210: Unsupported: Ignoring delay on this delayed statement.\n        #1 preamble_data = preamble_data >> 4;\n        ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1211: syntax error, unexpected \'@\'\n        @(posedge mrx_clk_o);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1217: Unsupported: Ignoring delay on this delayed statement.\n        #1 mrxd_o = sfd_data[3:0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1218: Unsupported: Ignoring delay on this delayed statement.\n        #1 sfd_data = sfd_data >> 4;\n        ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1219: syntax error, unexpected \'@\'\n        @(posedge mrx_clk_o);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1227: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1230: syntax error, unexpected \'@\'\n        @(posedge mrx_clk_o);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1231: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1234: syntax error, unexpected \'@\'\n        @(posedge mrx_clk_o);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1235: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1241: syntax error, unexpected \'@\'\n        @(posedge mrx_clk_o);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1246: Unsupported: Ignoring delay on this delayed statement.\n      #1 mcrs_rx = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1247: Unsupported: Ignoring delay on this delayed statement.\n      #1 mrxdv_o = 0;\n      ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1248: syntax error, unexpected \'@\'\n      @(posedge mrx_clk_o);\n      ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1263: syntax error, unexpected \'@\'\n    @ (posedge mrx_clk_o);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1264: Unsupported: Ignoring delay on this delayed statement.\n    #1 mrxdv_o=1\'b1;\n    ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1269: syntax error, unexpected \'@\'\n      @ (posedge mrx_clk_o);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1270: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1277: syntax error, unexpected \'@\'\n      @ (posedge mrx_clk_o);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1278: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1279: Define or directive not defined: \'`UNICAST_XFR\'\n      if(TransferType == `UNICAST_XFR && tt == 1)\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1279: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n      if(TransferType == `UNICAST_XFR && tt == 1)\n                                      ^~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1281: Define or directive not defined: \'`BROADCAST_XFR\'\n      else if(TransferType == `BROADCAST_XFR && tt < 7)\n                              ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1287: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1289: Define or directive not defined: \'`BROADCAST_XFR\'\n      if(TransferType == `BROADCAST_XFR && tt == 6)\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1289: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n      if(TransferType == `BROADCAST_XFR && tt == 6)\n                                        ^~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1293: Define or directive not defined: \'`BROADCAST_XFR\'\n      if(TransferType == `BROADCAST_XFR && tt < 7)\n                         ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1300: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1316: Unsupported: Ignoring delay on this delayed statement.\n  #1 status_bit6_0[2] = test_op;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1324: Unsupported: Ignoring delay on this delayed statement.\n  #1 mrxerr_o = test_op;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1338: Unsupported: Ignoring delay on this delayed statement.\n  #1 task_mcoll = test_op;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1346: Unsupported: Ignoring delay on this delayed statement.\n  #1 task_mcrs = test_op;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1354: Unsupported: Ignoring delay on this delayed statement.\n  #1 task_mcrs_lost = test_op;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1362: Unsupported: Ignoring delay on this delayed statement.\n  #1 no_collision_in_half_duplex = test_op;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1370: Unsupported: Ignoring delay on this delayed statement.\n  #1 collision_in_full_duplex = test_op;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1378: Unsupported: Ignoring delay on this delayed statement.\n  #1 no_carrier_sense_in_tx_half_duplex = test_op;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1386: Unsupported: Ignoring delay on this delayed statement.\n  #1 no_carrier_sense_in_rx_half_duplex = test_op;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1394: Unsupported: Ignoring delay on this delayed statement.\n  #1 carrier_sense_in_tx_full_duplex = test_op;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1402: Unsupported: Ignoring delay on this delayed statement.\n  #1 no_carrier_sense_in_rx_full_duplex = test_op;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1410: Unsupported: Ignoring delay on this delayed statement.\n  #1 real_carrier_sense = test_op;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1424: Unsupported: Ignoring delay on this delayed statement.\n  #1 registers_addr_data_test_operation = test_op;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1435: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_mem[i] = 16\'h0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1444: Unsupported: Ignoring delay on this delayed statement.\n  #1 no_preamble = test_op;\n  ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1446: syntax error, unexpected \'@\'\n  @(posedge mdc_i);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v:1447: Unsupported: Ignoring delay on this delayed statement.\n  #1 md_transfer_cnt_reset = 1\'b0;\n  ^\n%Error: Exiting due to 47 error(s), 75 warning(s)\n'
module eth_phy
(

        m_rst_n_i,


        mtx_clk_o,
        mtxd_i,
        mtxen_i,
        mtxerr_i,


        mrx_clk_o,
        mrxd_o,
        mrxdv_o,
        mrxerr_o,

        mcoll_o,
        mcrs_o,


        mdc_i,
        md_io,


        phy_log
);








input           m_rst_n_i;

output          mtx_clk_o;
input   [3:0]   mtxd_i;
input           mtxen_i;
input           mtxerr_i;

output          mrx_clk_o;
output  [3:0]   mrxd_o;
output          mrxdv_o;
output          mrxerr_o;

output          mcoll_o;
output          mcrs_o;

input           mdc_i;
inout           md_io;

input   [31:0]  phy_log;






















reg            control_bit15;
reg    [14:10] control_bit14_10;
reg            control_bit9;
reg    [8:0]   control_bit8_0;

wire   [15:9]  status_bit15_9 = `SUPPORTED_SPEED_AND_PORT;
wire           status_bit8    = `EXTENDED_STATUS;
wire           status_bit7    = 1'b0;
reg    [6:0]   status_bit6_0;

wire   [15:0]  phy_id1        = `PHY_ID1;

wire   [15:0]  phy_id2        = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};



reg    [15:0]  data_mem [0:31];










reg       mtx_clk_o;
reg       mrx_clk_o;


real      rx_link_down_halfperiod;

always@(status_bit6_0[2])
begin
  if (!status_bit6_0[2])
  begin
    #1 rx_link_down_halfperiod = ({$random} % 243) + 13;
    `ifdef VERBOSE
    #1 $fdisplay(phy_log, "   (%0t)(%m)MAC RX clock is %f MHz while ethernet link is down!", 
                 $time, (1000/(rx_link_down_halfperiod*2)) );
    `endif
  end
end

`ifdef VERBOSE
always@(status_bit6_0[2])
begin
  if (!status_bit6_0[2])
    #1 $fdisplay(phy_log, "   (%0t)(%m)Ethernet link is down!", $time);
  else
    #1 $fdisplay(phy_log, "   (%0t)(%m)Ethernet link is up!", $time);
end
`endif


wire      eth_speed;

assign eth_speed = ( (control_bit14_10[13]) && !((`LED_CFG1) && (`LED_CFG2)) );

`ifdef VERBOSE
always@(eth_speed)
begin
  if (eth_speed)
    #1 $fdisplay(phy_log, "   (%0t)(%m)PHY configured to 100 Mbps!", $time);
  else
    #1 $fdisplay(phy_log, "   (%0t)(%m)PHY configured tp 10 Mbps!", $time);
end
`endif




always
begin
  mtx_clk_o = 0;
  #7;
  forever
  begin
    if (eth_speed)
    begin
      #20 mtx_clk_o = ~mtx_clk_o;
    end
    else
    begin
      #200 mtx_clk_o = ~mtx_clk_o;
    end
  end
end

always
begin

  mrx_clk_o = 0;
  #7;
  forever
  begin
    if (eth_speed)
    begin
      #20 mrx_clk_o = ~mrx_clk_o;
    end
    else
    begin
      #200 mrx_clk_o = ~mrx_clk_o;
    end
  end







end









reg             respond_to_all_phy_addr;
reg             no_preamble;

integer         md_transfer_cnt;
reg             md_transfer_cnt_reset;
reg             md_io_reg;
reg             md_io_output;
reg             md_io_rd_wr;
reg             md_io_enable;
reg     [4:0]   phy_address;
reg     [4:0]   reg_address;
reg             md_get_phy_address;
reg             md_get_reg_address;
reg     [15:0]  reg_data_in;
reg             md_get_reg_data_in;
reg             md_put_reg_data_in;
reg     [15:0]  reg_data_out;
reg             md_put_reg_data_out;

wire    [15:0]  register_bus_in;
reg     [15:0]  register_bus_out;

initial
begin
  md_io_enable = 1'b0;
  respond_to_all_phy_addr = 1'b0;
  no_preamble = 1'b0;
end


assign #1 md_io = (m_rst_n_i && md_io_enable) ? md_io_output : 1'bz ;


always@(posedge mdc_i or negedge m_rst_n_i)
begin
  if (!m_rst_n_i)
    md_io_reg <= #1 0;
  else
    md_io_reg <= #1 md_io;
end



always@(posedge mdc_i or negedge m_rst_n_i)
begin
  if (!m_rst_n_i)
  begin
    phy_address <= 0;
    reg_address <= 0;
    reg_data_in <= 0;
    reg_data_out <= 0;
    md_io_output <= 0;
  end
  else
  begin
    if (md_get_phy_address)
    begin
      phy_address[4:1] <= phy_address[3:0];
      phy_address[0]   <= md_io;
    end
    if (md_get_reg_address)
    begin
      reg_address[4:1] <= reg_address[3:0];
      reg_address[0]   <= md_io;
    end
    if (md_get_reg_data_in)
    begin
      reg_data_in[15:1] <= reg_data_in[14:0];
      reg_data_in[0]    <= md_io;
    end
    if (md_put_reg_data_out)
    begin
      reg_data_out <= register_bus_out;
    end
    if (md_io_enable)
    begin
      md_io_output       <= reg_data_out[15];
      reg_data_out[15:1] <= reg_data_out[14:0];
      reg_data_out[0]    <= 1'b0;
    end
  end
end

assign #1 register_bus_in = reg_data_in;


always@(posedge mdc_i or negedge m_rst_n_i)
begin
  if (!m_rst_n_i)
  begin
    if (no_preamble)
      md_transfer_cnt <= 33;
    else
      md_transfer_cnt <= 1;
  end
  else
  begin
    if (md_transfer_cnt_reset)
    begin
      if (no_preamble)
        md_transfer_cnt <= 33;
      else
        md_transfer_cnt <= 1;
    end
    else if (md_transfer_cnt < 64)
    begin
      md_transfer_cnt <= md_transfer_cnt + 1'b1;
    end
    else
    begin
      if (no_preamble)
        md_transfer_cnt <= 33;
      else
        md_transfer_cnt <= 1;
    end
  end
end


always@(m_rst_n_i or md_transfer_cnt or md_io_reg or md_io_rd_wr or 
        phy_address or respond_to_all_phy_addr or no_preamble)
begin
  #1;
  while ((m_rst_n_i) && (md_transfer_cnt <= 64))
  begin


    if (md_transfer_cnt < 33)
    begin
      #4 md_put_reg_data_in = 1'b0;
      if (md_io_reg !== 1'b1)
      begin
        #1 md_transfer_cnt_reset = 1'b1;
      end
      else
      begin
        #1 md_transfer_cnt_reset = 1'b0;
      end
    end


    else if (md_transfer_cnt == 33)
    begin
      if (no_preamble)
      begin
        #4 md_put_reg_data_in = 1'b0;
        if (md_io_reg === 1'b0)
        begin
          #1 md_transfer_cnt_reset = 1'b0;
        end
        else
        begin
          #1 md_transfer_cnt_reset = 1'b1;

          if (md_io_reg !== 1'bz)
          begin

            `ifdef VERBOSE
            $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong first start bit (without preamble)", $time);
            `endif
            #10 $stop;
          end
        end
      end
      else
      begin
        #4 ;
        `ifdef VERBOSE
        $fdisplay(phy_log, "   (%0t)(%m)MIIM - 32-bit preamble received", $time);
        `endif


        if ((md_io_reg !== 1'b0) && (md_transfer_cnt_reset == 1'b0))
        begin

          `ifdef VERBOSE
          $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong first start bit", $time);
          `endif
          #10 $stop;
        end
      end
    end

    else if (md_transfer_cnt == 34)
    begin
      #4;
      if (md_io_reg !== 1'b1)
      begin

        #1;
        `ifdef VERBOSE
        if (no_preamble)
          $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong second start bit (without preamble)", $time);
        else
          $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong second start bit", $time);
        `endif
        #10 $stop;
      end
      else
      begin
        `ifdef VERBOSE
        if (no_preamble)
          #1 $fdisplay(phy_log, "   (%0t)(%m)MIIM - 2 start bits received (without preamble)", $time);
        else
          #1 $fdisplay(phy_log, "   (%0t)(%m)MIIM - 2 start bits received", $time);
        `endif
      end
    end


    else if (md_transfer_cnt == 35)
    begin
      #4;
      if (md_io_reg === 1'b1)
      begin
        #1 md_io_rd_wr = 1'b1;
      end
      else 
      begin
        #1 md_io_rd_wr = 1'b0;
      end
    end

    else if (md_transfer_cnt == 36)
    begin
      #4;
      if ((md_io_reg === 1'b0) && (md_io_rd_wr == 1'b1))
      begin
        #1 md_io_rd_wr = 1'b1;
        `ifdef VERBOSE
        $fdisplay(phy_log, "   (%0t)(%m)MIIM - op-code for READING from registers", $time);
        `endif
      end
      else if ((md_io_reg === 1'b1) && (md_io_rd_wr == 1'b0))
      begin
        #1 md_io_rd_wr = 1'b0;
        `ifdef VERBOSE
        $fdisplay(phy_log, "   (%0t)(%m)MIIM - op-code for WRITING to registers", $time);
        `endif
      end
      else
      begin

        `ifdef VERBOSE
        #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong OP-CODE", $time);
        `endif
        #10 $stop;
      end

      begin
        #1 md_get_phy_address = 1'b1;
      end
    end


    else if (md_transfer_cnt == 41)
    begin
      #4 md_get_phy_address = 1'b0;

      #1 md_get_reg_address = 1'b1;
    end



    else if (md_transfer_cnt == 46)
    begin
      #4 md_get_reg_address = 1'b0;
      #1 md_put_reg_data_out = 1'b1;
    end



    else if (md_transfer_cnt == 47)
    begin
      #4 md_put_reg_data_out = 1'b0;
      if (md_io_rd_wr)
      begin
        if (md_io_reg !== 1'bz)
        begin

          `ifdef VERBOSE
          #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong turn-around cycle before reading data out", $time);
          `endif
          #10 $stop;
        end
        if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr)
        begin
          #1 md_io_enable = 1'b1;
          `ifdef VERBOSE
          $fdisplay(phy_log, "   (%0t)(%m)MIIM - received correct PHY ADDRESS: %x", $time, phy_address);
          `endif
        end
        else
        begin
          `ifdef VERBOSE
          #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - received different PHY ADDRESS: %x", $time, phy_address);
          `endif
        end
      end
      else
      begin
        #1 md_io_enable = 1'b0;

        if (md_io_reg !== 1'b1) 
        begin

          `ifdef VERBOSE
          #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong 1. turn-around cycle before writing data in", 
                       $time);
          `endif
          #10 $stop;
        end
      end
    end


    else if (md_transfer_cnt == 48)
    begin
      #4;
      if (!md_io_rd_wr)
      begin
        #1 md_get_reg_data_in = 1'b1;

        if (md_io_reg !== 1'b0)
        begin

          `ifdef VERBOSE
          #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong 2. turn-around cycle before writing data in", 
                       $time);
          `endif
          #10 $stop;
        end
      end
      else
      begin
        #1 md_get_reg_data_in = 1'b0;
      end
    end




    else if (md_transfer_cnt == 64)
    begin
      #1 md_io_enable = 1'b0;
      #4 md_get_reg_data_in = 1'b0;
      if (!md_io_rd_wr)
      begin
        if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr)
        begin
          #1 md_put_reg_data_in = 1'b1;
          `ifdef VERBOSE
          $fdisplay(phy_log, "   (%0t)(%m)MIIM - received correct PHY ADDRESS: %x", $time, phy_address);
          $fdisplay(phy_log, "   (%0t)(%m)MIIM - WRITING to register %x COMPLETED!", $time, reg_address);
          `endif
        end
        else
        begin
          `ifdef VERBOSE
          #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - received different PHY ADDRESS: %x", $time, phy_address);
          $fdisplay(phy_log, "*W (%0t)(%m)MIIM - NO WRITING to register %x !", $time, reg_address);
          `endif
        end
      end
      else
      begin
        `ifdef VERBOSE
        if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr)
          #1 $fdisplay(phy_log, "   (%0t)(%m)MIIM - READING from register %x COMPLETED!", 
                       $time, reg_address);
        else
          #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - NO READING from register %x !", $time, reg_address);
        `endif
      end
    end


    @(posedge mdc_i)
      #1;
  end 
end
















































reg     registers_addr_data_test_operation;


initial
begin
  #1 status_bit6_0[6] = no_preamble;
  status_bit6_0[5] = 1'b0;
  status_bit6_0[3] = 1'b1;
  status_bit6_0[0] = 1'b1;
end
always@(posedge mrx_clk_o)
begin
  status_bit6_0[4] <= #1 1'b0;
  status_bit6_0[1] <= #1 1'b0;
end
initial
begin
  status_bit6_0[2] = 1'b1;
  registers_addr_data_test_operation = 0;
end


always@(reg_address or registers_addr_data_test_operation or md_put_reg_data_out or
        control_bit15 or control_bit14_10 or control_bit9 or control_bit8_0 or 
        status_bit15_9 or status_bit8 or status_bit7 or status_bit6_0 or
        phy_id1 or phy_id2)
begin
  if (registers_addr_data_test_operation)
  begin
    if (md_put_reg_data_out)
    begin
      register_bus_out = #1 data_mem[reg_address];
    end
  end
  else
  begin
    if (md_put_reg_data_out)
    begin
      case (reg_address)
      5'h0:    register_bus_out = #1 {control_bit15, control_bit14_10, control_bit9, control_bit8_0};
      5'h1:    register_bus_out = #1 {status_bit15_9, status_bit8, status_bit7, status_bit6_0};
      5'h2:    register_bus_out = #1 phy_id1;
      5'h3:    register_bus_out = #1 phy_id2;
      default: register_bus_out = #1 16'hDEAD;
      endcase
    end
  end
end


reg    self_clear_d0;
reg    self_clear_d1;
reg    self_clear_d2;
reg    self_clear_d3;

always@(posedge mdc_i or negedge m_rst_n_i)
begin
  if (!m_rst_n_i)
  begin
    self_clear_d0    <= #1 0;
    self_clear_d1    <= #1 0;
    self_clear_d2    <= #1 0;
    self_clear_d3    <= #1 0;
  end
  else
  begin
    self_clear_d0    <= #1 md_put_reg_data_in;
    self_clear_d1    <= #1 self_clear_d0;
    self_clear_d2    <= #1 self_clear_d1;
    self_clear_d3    <= #1 self_clear_d2;
  end
end


always@(posedge mdc_i or negedge m_rst_n_i)
begin
  if ((!m_rst_n_i) || (control_bit15))
  begin
    if (!registers_addr_data_test_operation)
    begin
      control_bit15    <= #1 0;
      control_bit14_10 <= #1 {1'b0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 2'b0};
      control_bit9     <= #1 0;
      control_bit8_0   <= #1 {`LED_CFG3, 8'b0};
    end
  end
  else
  begin
    if (registers_addr_data_test_operation)
    begin
      if (md_put_reg_data_in)
      begin
        data_mem[reg_address] <= #1 register_bus_in[15:0];
      end
    end
    else
    begin

      if (md_put_reg_data_in)
      begin
        case (reg_address)
        5'h0: 
        begin
          control_bit14_10 <= #1 register_bus_in[14:10];
          control_bit8_0   <= #1 register_bus_in[8:0];
        end
        default:
        begin
        end
        endcase
      end

      if ((md_put_reg_data_in) && (reg_address == 5'h0))
      begin
        control_bit15 <= #1 register_bus_in[15];
        control_bit9  <= #1 register_bus_in[9];
      end
      else if (self_clear_d3)
      begin
        control_bit15 <= #1 1'b0;
        control_bit9  <= #1 1'b0;
      end
    end
  end
end










reg             mcoll_o;
reg             mcrs_o;


reg             mcrs_rx;
reg             mcrs_tx;

reg             mtxen_d1;
reg             mtxen_d2;
reg             mtxen_d3;
reg             mtxen_d4;
reg             mtxen_d5;
reg             mtxen_d6;

reg             task_mcoll;

reg             task_mcrs;
reg             task_mcrs_lost;

reg             no_collision_in_half_duplex;

reg             collision_in_full_duplex;

reg             no_carrier_sense_in_tx_half_duplex;
reg             no_carrier_sense_in_rx_half_duplex;

reg             carrier_sense_in_tx_full_duplex;

reg             no_carrier_sense_in_rx_full_duplex;

reg             real_carrier_sense;

initial
begin
  mcrs_rx = 0;
  mcrs_tx = 0;
  task_mcoll = 0;
  task_mcrs = 0;
  task_mcrs_lost = 0;
  no_collision_in_half_duplex = 0;
  collision_in_full_duplex = 0;
  no_carrier_sense_in_tx_half_duplex = 0;
  no_carrier_sense_in_rx_half_duplex = 0;
  carrier_sense_in_tx_full_duplex = 0;
  no_carrier_sense_in_rx_full_duplex = 0;
  real_carrier_sense = 0;
end


always@(m_rst_n_i or control_bit8_0 or collision_in_full_duplex or 
        mcrs_rx or mcrs_tx or task_mcoll or no_collision_in_half_duplex
        )
begin
  if (!m_rst_n_i)
    mcoll_o = 0;
  else
  begin
    if (control_bit8_0[8])
    begin
      if (collision_in_full_duplex)
      begin
        mcoll_o = ((mcrs_rx && mcrs_tx) || task_mcoll);
        `ifdef VERBOSE
        if (mcrs_rx && mcrs_tx)
          $fdisplay(phy_log, "   (%0t)(%m) Collision set in FullDuplex!", $time);
        if (task_mcoll)
          $fdisplay(phy_log, "   (%0t)(%m) Collision set in FullDuplex from TASK!", $time);
        `endif
      end
      else
      begin
        mcoll_o = task_mcoll;
        `ifdef VERBOSE
        if (task_mcoll)
          $fdisplay(phy_log, "   (%0t)(%m) Collision set in FullDuplex from TASK!", $time);
        `endif
      end
    end
    else
    begin
      mcoll_o = ((mcrs_rx && mcrs_tx && !no_collision_in_half_duplex) || 
                  task_mcoll);
      `ifdef VERBOSE
      if (mcrs_rx && mcrs_tx)
        $fdisplay(phy_log, "   (%0t)(%m) Collision set in HalfDuplex!", $time);
      if (task_mcoll)
        $fdisplay(phy_log, "   (%0t)(%m) Collision set in HalfDuplex from TASK!", $time);
      `endif
    end
  end
end


always@(m_rst_n_i or control_bit8_0 or carrier_sense_in_tx_full_duplex or
        no_carrier_sense_in_rx_full_duplex or
        no_carrier_sense_in_tx_half_duplex or 
        no_carrier_sense_in_rx_half_duplex or 
        mcrs_rx or mcrs_tx or task_mcrs or task_mcrs_lost
        )
begin
  if (!m_rst_n_i)
    mcrs_o = 0;
  else
  begin
    if (control_bit8_0[8])
    begin
      if (carrier_sense_in_tx_full_duplex)
        mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_full_duplex) || 
                   mcrs_tx || task_mcrs) && !task_mcrs_lost;
      else
        mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_full_duplex) || 
                   task_mcrs) && !task_mcrs_lost;
    end
    else
    begin
      mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_half_duplex) || 
                (mcrs_tx && !no_carrier_sense_in_tx_half_duplex) || 
                 task_mcrs) && !task_mcrs_lost;
    end
  end
end




reg     [7:0]  tx_mem [0:4194303];
reg    [31:0]  tx_mem_addr_in;
reg     [7:0]  tx_mem_data_in;
reg    [31:0]  tx_cnt;


reg            tx_preamble_ok;
reg            tx_sfd_ok;

reg            tx_byte_aligned_ok;

reg    [31:0]  tx_len;

reg    [31:0]  tx_len_err;


always@(posedge mtx_clk_o)
begin

  if (!m_rst_n_i)
  begin
    tx_cnt <= 0;
    tx_preamble_ok <= 0;
    tx_sfd_ok <= 0;
    tx_len <= 0;
    tx_len_err <= 0;
  end
  else
  begin
    if (!mtxen_i)
    begin
      tx_cnt <= 0;
    end
    else
    begin

      tx_cnt <= tx_cnt + 1;

      if (tx_cnt == 0)
      begin
        `ifdef VERBOSE
        $fdisplay(phy_log, "   (%0t)(%m) TX frame started with tx_en set!", $time);
        `endif
        if (mtxd_i == 4'h5)
          tx_preamble_ok <= 1;
        else
          tx_preamble_ok <= 0;
        tx_sfd_ok <= 0;
        tx_byte_aligned_ok <= 0;
        tx_len <= 0;
        tx_len_err <= 0;

      end


      if ((tx_cnt > 0) && (tx_cnt <= 13))
      begin
        if ((tx_preamble_ok != 1) || (mtxd_i != 4'h5))
          tx_preamble_ok <= 0;
      end

      if (tx_cnt == 14)
      begin
        `ifdef VERBOSE
        if (tx_preamble_ok == 1)
          $fdisplay(phy_log, "   (%0t)(%m) TX frame preamble OK!", $time);
        else
          $fdisplay(phy_log, "*E (%0t)(%m) TX frame preamble NOT OK!", $time);
        `endif
        if (mtxd_i == 4'h5)
          tx_sfd_ok <= 1;
        else
          tx_sfd_ok <= 0;
      end
      if (tx_cnt == 15)
      begin
        if ((tx_sfd_ok != 1) || (mtxd_i != 4'hD))
          tx_sfd_ok <= 0;
      end


      if (tx_cnt > 15)
      begin
        if (tx_cnt == 16)
        begin
          `ifdef VERBOSE
          if (tx_sfd_ok == 1)
            $fdisplay(phy_log, "   (%0t)(%m) TX frame SFD OK!", $time);
          else
            $fdisplay(phy_log, "*E (%0t)(%m) TX frame SFD NOT OK!", $time);
          `endif
        end

        if (tx_cnt[0] == 0)
        begin
          tx_mem_data_in[3:0] <= mtxd_i;
          tx_byte_aligned_ok <= 0;
        end
        else
        begin
          tx_mem[tx_mem_addr_in[21:0]] <= {mtxd_i, tx_mem_data_in[3:0]};
          tx_len <= tx_len + 1;
          tx_byte_aligned_ok <= 1;
          tx_mem_addr_in <= tx_mem_addr_in + 1'b1;
        end

        if (mtxerr_i)
          tx_len_err <= tx_len;
      end
    end
  end


  if (!m_rst_n_i)
  begin
    mcrs_tx  <= 0;
    mtxen_d1 <= 0;
    mtxen_d2 <= 0;
    mtxen_d3 <= 0;
    mtxen_d4 <= 0;
    mtxen_d5 <= 0;
    mtxen_d6 <= 0;
  end
  else
  begin
    mtxen_d1 <= mtxen_i;
    mtxen_d2 <= mtxen_d1;
    mtxen_d3 <= mtxen_d2;
    mtxen_d4 <= mtxen_d3;
    mtxen_d5 <= mtxen_d4;
    mtxen_d6 <= mtxen_d5;
    if (real_carrier_sense)
      mcrs_tx  <= mtxen_d6;
    else
      mcrs_tx  <= mtxen_i;
  end
end

`ifdef VERBOSE
reg             frame_started;

initial
begin
  frame_started = 0;
end
always@(posedge mtxen_i)
begin
  frame_started <= 1;
end
always@(negedge mtxen_i)
begin
  if (frame_started)
  begin
    $fdisplay(phy_log, "   (%0t)(%m) TX frame ended with tx_en reset!", $time);
    frame_started <= 0;
  end
end

always@(posedge mrxerr_o)
begin
  $fdisplay(phy_log, "   (%0t)(%m) RX frame ERROR signal was set!", $time);
end
`endif







initial
begin
  tx_mem_addr_in = 0;
end


task set_tx_mem_addr;
  input [31:0] tx_mem_address;
begin
  #1 tx_mem_addr_in = tx_mem_address;
end
endtask


reg     [7:0]  rx_mem [0:4194303];


reg     [3:0]   mrxd_o;
reg             mrxdv_o;
reg             mrxerr_o;

initial
begin
  mrxd_o = 0;
  mrxdv_o = 0;
  mrxerr_o = 0;
  mcrs_rx = 0;
end

task send_rx_packet;
  input  [(8*8)-1:0] preamble_data;
  input   [3:0] preamble_len;
  input   [7:0] sfd_data;
  input  [31:0] start_addr;
  input  [31:0] len;
  input         plus_drible_nibble;
  integer       rx_cnt;
  reg    [31:0] rx_mem_addr_in;
  reg     [7:0] rx_mem_data_out;
begin
      @(posedge mrx_clk_o);

      if (real_carrier_sense)
        #1 mcrs_rx = 1;
      else
        #1 mcrs_rx = 0;
      @(posedge mrx_clk_o);
      #1 mcrs_rx = 1;
      #1 mrxdv_o = 1;
      `ifdef VERBOSE
      $fdisplay(phy_log, "   (%0t)(%m) RX frame started with rx_dv set!", $time);
      `endif

      rx_mem_addr_in = start_addr;
    

      for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
      begin
        #1 mrxd_o = preamble_data[3:0];
        #1 preamble_data = preamble_data >> 4;
        @(posedge mrx_clk_o);
      end
    

      for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1)
      begin
        #1 mrxd_o = sfd_data[3:0];
        #1 sfd_data = sfd_data >> 4;
        @(posedge mrx_clk_o);
      end
      `ifdef VERBOSE
      $fdisplay(phy_log, "   (%0t)(%m) RX frame preamble and SFD sent!", $time);
      `endif

      for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
      begin
        #1;
        rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
        mrxd_o = rx_mem_data_out[3:0];
        @(posedge mrx_clk_o);
        #1;
        mrxd_o = rx_mem_data_out[7:4];
        rx_mem_addr_in = rx_mem_addr_in + 1;
        @(posedge mrx_clk_o);
        #1;
      end
      if (plus_drible_nibble)
      begin
        rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
        mrxd_o = rx_mem_data_out[3:0];
        @(posedge mrx_clk_o);
      end
      `ifdef VERBOSE
      $fdisplay(phy_log, "   (%0t)(%m) RX frame addresses, type/length, data and FCS sent!", $time);
      `endif
      #1 mcrs_rx = 0;
      #1 mrxdv_o = 0;
      @(posedge mrx_clk_o);
      `ifdef VERBOSE
      $fdisplay(phy_log, "   (%0t)(%m) RX frame ended with rx_dv reset!", $time);
      `endif
end
endtask



task GetDataOnMRxD;
  input [15:0] Len;
  input [31:0] TransferType;
  integer tt;

  begin
    @ (posedge mrx_clk_o);
    #1 mrxdv_o=1'b1;

    for(tt=0; tt<15; tt=tt+1)
    begin
      mrxd_o=4'h5;
      @ (posedge mrx_clk_o);
      #1;
    end

    mrxd_o=4'hd;

    for(tt=1; tt<(Len+1); tt=tt+1)
    begin
      @ (posedge mrx_clk_o);
      #1;
      if(TransferType == `UNICAST_XFR && tt == 1)
        mrxd_o = 4'h0;
      else if(TransferType == `BROADCAST_XFR && tt < 7)
        mrxd_o = 4'hf;
      else
        mrxd_o = tt[3:0];

      @ (posedge mrx_clk_o);
      #1;

      if(TransferType == `BROADCAST_XFR && tt == 6)
        mrxd_o = 4'he;
      else

      if(TransferType == `BROADCAST_XFR && tt < 7)
        mrxd_o = 4'hf;
      else
        mrxd_o = tt[7:4];
    end

    @ (posedge mrx_clk_o);
    #1;
    mrxdv_o = 1'b0;
  end
endtask









task link_up_down;
  input   test_op;
begin
  #1 status_bit6_0[2] = test_op;
end
endtask


task rx_err;
  input   test_op;
begin
  #1 mrxerr_o = test_op;
end
endtask








task collision;
  input   test_op;
begin
  #1 task_mcoll = test_op;
end
endtask


task carrier_sense;
  input   test_op;
begin
  #1 task_mcrs = test_op;
end
endtask


task carrier_sense_lost;
  input   test_op;
begin
  #1 task_mcrs_lost = test_op;
end
endtask


task no_collision_hd_detect;
  input   test_op;
begin
  #1 no_collision_in_half_duplex = test_op;
end
endtask


task collision_fd_detect;
  input   test_op;
begin
  #1 collision_in_full_duplex = test_op;
end
endtask


task no_carrier_sense_tx_hd_detect;
  input   test_op;
begin
  #1 no_carrier_sense_in_tx_half_duplex = test_op;
end
endtask


task no_carrier_sense_rx_hd_detect;
  input   test_op;
begin
  #1 no_carrier_sense_in_rx_half_duplex = test_op;
end
endtask


task carrier_sense_tx_fd_detect;
  input   test_op;
begin
  #1 carrier_sense_in_tx_full_duplex = test_op;
end
endtask


task no_carrier_sense_rx_fd_detect;
  input   test_op;
begin
  #1 no_carrier_sense_in_rx_full_duplex = test_op;
end
endtask


task carrier_sense_real_delay;
  input   test_op;
begin
  #1 real_carrier_sense = test_op;
end
endtask








task test_regs;
  input   test_op;
begin
  #1 registers_addr_data_test_operation = test_op;
  respond_to_all_phy_addr = test_op;
end
endtask


task clear_test_regs;
  integer i;
begin
  for (i = 0; i < 32; i = i + 1)
  begin
    #1 data_mem[i] = 16'h0;
  end
end
endtask


task preamble_suppresed;
  input   test_op;
begin
  #1 no_preamble = test_op;
  md_transfer_cnt_reset = 1'b1;
  @(posedge mdc_i);
  #1 md_transfer_cnt_reset = 1'b0;
end
endtask





endmodule
module eth_phy
(

        m_rst_n_i,


        mtx_clk_o,
        mtxd_i,
        mtxen_i,
        mtxerr_i,


        mrx_clk_o,
        mrxd_o,
        mrxdv_o,
        mrxerr_o,

        mcoll_o,
        mcrs_o,


        mdc_i,
        md_io,


        phy_log
);









input           m_rst_n_i;

output          mtx_clk_o;
input   [3:0]   mtxd_i;
input           mtxen_i;
input           mtxerr_i;

output          mrx_clk_o;
output  [3:0]   mrxd_o;
output          mrxdv_o;
output          mrxerr_o;

output          mcoll_o;
output          mcrs_o;

input           mdc_i;
inout           md_io;

input   [31:0]  phy_log;






















reg            control_bit15;
reg    [14:10] control_bit14_10;
reg            control_bit9;
reg    [8:0]   control_bit8_0;

wire   [15:9]  status_bit15_9 = `SUPPORTED_SPEED_AND_PORT;
wire           status_bit8    = `EXTENDED_STATUS;
wire           status_bit7    = 1'b0;
reg    [6:0]   status_bit6_0;

wire   [15:0]  phy_id1        = `PHY_ID1;

wire   [15:0]  phy_id2        = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};



reg    [15:0]  data_mem [0:31];










reg       mtx_clk_o;
reg       mrx_clk_o;


real      rx_link_down_halfperiod;

always@(status_bit6_0[2])
begin
  if (!status_bit6_0[2])
  begin
    #1 rx_link_down_halfperiod = ({$random} % 243) + 13;
    `ifdef VERBOSE
    #1 $fdisplay(phy_log, "   (%0t)(%m)MAC RX clock is %f MHz while ethernet link is down!", 
                 $time, (1000/(rx_link_down_halfperiod*2)) );
    `endif
  end
end

`ifdef VERBOSE
always@(status_bit6_0[2])
begin
  if (!status_bit6_0[2])
    #1 $fdisplay(phy_log, "   (%0t)(%m)Ethernet link is down!", $time);
  else
    #1 $fdisplay(phy_log, "   (%0t)(%m)Ethernet link is up!", $time);
end
`endif


wire      eth_speed;

assign eth_speed = ( (control_bit14_10[13]) && !((`LED_CFG1) && (`LED_CFG2)) );

`ifdef VERBOSE
always@(eth_speed)
begin
  if (eth_speed)
    #1 $fdisplay(phy_log, "   (%0t)(%m)PHY configured to 100 Mbps!", $time);
  else
    #1 $fdisplay(phy_log, "   (%0t)(%m)PHY configured tp 10 Mbps!", $time);
end
`endif




always
begin
  mtx_clk_o = 0;
  #7;
  forever
  begin
    if (eth_speed)
    begin
      #20 mtx_clk_o = ~mtx_clk_o;
    end
    else
    begin
      #200 mtx_clk_o = ~mtx_clk_o;
    end
  end
end

always
begin

  mrx_clk_o = 0;
  #7;
  forever
  begin
    if (eth_speed)
    begin
      #20 mrx_clk_o = ~mrx_clk_o;
    end
    else
    begin
      #200 mrx_clk_o = ~mrx_clk_o;
    end
  end







end









reg             respond_to_all_phy_addr;
reg             no_preamble;

integer         md_transfer_cnt;
reg             md_transfer_cnt_reset;
reg             md_io_reg;
reg             md_io_output;
reg             md_io_rd_wr;
reg             md_io_enable;
reg     [4:0]   phy_address;
reg     [4:0]   reg_address;
reg             md_get_phy_address;
reg             md_get_reg_address;
reg     [15:0]  reg_data_in;
reg             md_get_reg_data_in;
reg             md_put_reg_data_in;
reg     [15:0]  reg_data_out;
reg             md_put_reg_data_out;

wire    [15:0]  register_bus_in;
reg     [15:0]  register_bus_out;

initial
begin
  md_io_enable = 1'b0;
  respond_to_all_phy_addr = 1'b0;
  no_preamble = 1'b0;
end


assign #1 md_io = (m_rst_n_i && md_io_enable) ? md_io_output : 1'bz ;


always@(posedge mdc_i or negedge m_rst_n_i)
begin
  if (!m_rst_n_i)
    md_io_reg <= #1 0;
  else
    md_io_reg <= #1 md_io;
end



always@(posedge mdc_i or negedge m_rst_n_i)
begin
  if (!m_rst_n_i)
  begin
    phy_address <= 0;
    reg_address <= 0;
    reg_data_in <= 0;
    reg_data_out <= 0;
    md_io_output <= 0;
  end
  else
  begin
    if (md_get_phy_address)
    begin
      phy_address[4:1] <= phy_address[3:0];
      phy_address[0]   <= md_io;
    end
    if (md_get_reg_address)
    begin
      reg_address[4:1] <= reg_address[3:0];
      reg_address[0]   <= md_io;
    end
    if (md_get_reg_data_in)
    begin
      reg_data_in[15:1] <= reg_data_in[14:0];
      reg_data_in[0]    <= md_io;
    end
    if (md_put_reg_data_out)
    begin
      reg_data_out <= register_bus_out;
    end
    if (md_io_enable)
    begin
      md_io_output       <= reg_data_out[15];
      reg_data_out[15:1] <= reg_data_out[14:0];
      reg_data_out[0]    <= 1'b0;
    end
  end
end

assign #1 register_bus_in = reg_data_in;


always@(posedge mdc_i or negedge m_rst_n_i)
begin
  if (!m_rst_n_i)
  begin
    if (no_preamble)
      md_transfer_cnt <= 33;
    else
      md_transfer_cnt <= 1;
  end
  else
  begin
    if (md_transfer_cnt_reset)
    begin
      if (no_preamble)
        md_transfer_cnt <= 33;
      else
        md_transfer_cnt <= 1;
    end
    else if (md_transfer_cnt < 64)
    begin
      md_transfer_cnt <= md_transfer_cnt + 1'b1;
    end
    else
    begin
      if (no_preamble)
        md_transfer_cnt <= 33;
      else
        md_transfer_cnt <= 1;
    end
  end
end


always@(m_rst_n_i or md_transfer_cnt or md_io_reg or md_io_rd_wr or 
        phy_address or respond_to_all_phy_addr or no_preamble)
begin
  #1;
  while ((m_rst_n_i) && (md_transfer_cnt <= 64))
  begin


    if (md_transfer_cnt < 33)
    begin
      #4 md_put_reg_data_in = 1'b0;
      if (md_io_reg !== 1'b1)
      begin
        #1 md_transfer_cnt_reset = 1'b1;
      end
      else
      begin
        #1 md_transfer_cnt_reset = 1'b0;
      end
    end


    else if (md_transfer_cnt == 33)
    begin
      if (no_preamble)
      begin
        #4 md_put_reg_data_in = 1'b0;
        if (md_io_reg === 1'b0)
        begin
          #1 md_transfer_cnt_reset = 1'b0;
        end
        else
        begin
          #1 md_transfer_cnt_reset = 1'b1;

          if (md_io_reg !== 1'bz)
          begin

            `ifdef VERBOSE
            $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong first start bit (without preamble)", $time);
            `endif
            #10 $stop;
          end
        end
      end
      else
      begin
        #4 ;
        `ifdef VERBOSE
        $fdisplay(phy_log, "   (%0t)(%m)MIIM - 32-bit preamble received", $time);
        `endif


        if ((md_io_reg !== 1'b0) && (md_transfer_cnt_reset == 1'b0))
        begin

          `ifdef VERBOSE
          $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong first start bit", $time);
          `endif
          #10 $stop;
        end
      end
    end

    else if (md_transfer_cnt == 34)
    begin
      #4;
      if (md_io_reg !== 1'b1)
      begin

        #1;
        `ifdef VERBOSE
        if (no_preamble)
          $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong second start bit (without preamble)", $time);
        else
          $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong second start bit", $time);
        `endif
        #10 $stop;
      end
      else
      begin
        `ifdef VERBOSE
        if (no_preamble)
          #1 $fdisplay(phy_log, "   (%0t)(%m)MIIM - 2 start bits received (without preamble)", $time);
        else
          #1 $fdisplay(phy_log, "   (%0t)(%m)MIIM - 2 start bits received", $time);
        `endif
      end
    end


    else if (md_transfer_cnt == 35)
    begin
      #4;
      if (md_io_reg === 1'b1)
      begin
        #1 md_io_rd_wr = 1'b1;
      end
      else 
      begin
        #1 md_io_rd_wr = 1'b0;
      end
    end

    else if (md_transfer_cnt == 36)
    begin
      #4;
      if ((md_io_reg === 1'b0) && (md_io_rd_wr == 1'b1))
      begin
        #1 md_io_rd_wr = 1'b1;
        `ifdef VERBOSE
        $fdisplay(phy_log, "   (%0t)(%m)MIIM - op-code for READING from registers", $time);
        `endif
      end
      else if ((md_io_reg === 1'b1) && (md_io_rd_wr == 1'b0))
      begin
        #1 md_io_rd_wr = 1'b0;
        `ifdef VERBOSE
        $fdisplay(phy_log, "   (%0t)(%m)MIIM - op-code for WRITING to registers", $time);
        `endif
      end
      else
      begin

        `ifdef VERBOSE
        #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong OP-CODE", $time);
        `endif
        #10 $stop;
      end

      begin
        #1 md_get_phy_address = 1'b1;
      end
    end


    else if (md_transfer_cnt == 41)
    begin
      #4 md_get_phy_address = 1'b0;

      #1 md_get_reg_address = 1'b1;
    end



    else if (md_transfer_cnt == 46)
    begin
      #4 md_get_reg_address = 1'b0;
      #1 md_put_reg_data_out = 1'b1;
    end



    else if (md_transfer_cnt == 47)
    begin
      #4 md_put_reg_data_out = 1'b0;
      if (md_io_rd_wr)
      begin
        if (md_io_reg !== 1'bz)
        begin

          `ifdef VERBOSE
          #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong turn-around cycle before reading data out", $time);
          `endif
          #10 $stop;
        end
        if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr)
        begin
          #1 md_io_enable = 1'b1;
          `ifdef VERBOSE
          $fdisplay(phy_log, "   (%0t)(%m)MIIM - received correct PHY ADDRESS: %x", $time, phy_address);
          `endif
        end
        else
        begin
          `ifdef VERBOSE
          #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - received different PHY ADDRESS: %x", $time, phy_address);
          `endif
        end
      end
      else
      begin
        #1 md_io_enable = 1'b0;

        if (md_io_reg !== 1'b1) 
        begin

          `ifdef VERBOSE
          #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong 1. turn-around cycle before writing data in", 
                       $time);
          `endif
          #10 $stop;
        end
      end
    end


    else if (md_transfer_cnt == 48)
    begin
      #4;
      if (!md_io_rd_wr)
      begin
        #1 md_get_reg_data_in = 1'b1;

        if (md_io_reg !== 1'b0)
        begin

          `ifdef VERBOSE
          #1 $fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong 2. turn-around cycle before writing data in", 
                       $time);
          `endif
          #10 $stop;
        end
      end
      else
      begin
        #1 md_get_reg_data_in = 1'b0;
      end
    end




    else if (md_transfer_cnt == 64)
    begin
      #1 md_io_enable = 1'b0;
      #4 md_get_reg_data_in = 1'b0;
      if (!md_io_rd_wr)
      begin
        if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr)
        begin
          #1 md_put_reg_data_in = 1'b1;
          `ifdef VERBOSE
          $fdisplay(phy_log, "   (%0t)(%m)MIIM - received correct PHY ADDRESS: %x", $time, phy_address);
          $fdisplay(phy_log, "   (%0t)(%m)MIIM - WRITING to register %x COMPLETED!", $time, reg_address);
          `endif
        end
        else
        begin
          `ifdef VERBOSE
          #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - received different PHY ADDRESS: %x", $time, phy_address);
          $fdisplay(phy_log, "*W (%0t)(%m)MIIM - NO WRITING to register %x !", $time, reg_address);
          `endif
        end
      end
      else
      begin
        `ifdef VERBOSE
        if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr)
          #1 $fdisplay(phy_log, "   (%0t)(%m)MIIM - READING from register %x COMPLETED!", 
                       $time, reg_address);
        else
          #1 $fdisplay(phy_log, "*W (%0t)(%m)MIIM - NO READING from register %x !", $time, reg_address);
        `endif
      end
    end


    @(posedge mdc_i)
      #1;
  end 
end
















































reg     registers_addr_data_test_operation;


initial
begin
  #1 status_bit6_0[6] = no_preamble;
  status_bit6_0[5] = 1'b0;
  status_bit6_0[3] = 1'b1;
  status_bit6_0[0] = 1'b1;
end
always@(posedge mrx_clk_o)
begin
  status_bit6_0[4] <= #1 1'b0;
  status_bit6_0[1] <= #1 1'b0;
end
initial
begin
  status_bit6_0[2] = 1'b1;
  registers_addr_data_test_operation = 0;
end


always@(reg_address or registers_addr_data_test_operation or md_put_reg_data_out or
        control_bit15 or control_bit14_10 or control_bit9 or control_bit8_0 or 
        status_bit15_9 or status_bit8 or status_bit7 or status_bit6_0 or
        phy_id1 or phy_id2)
begin
  if (registers_addr_data_test_operation)
  begin
    if (md_put_reg_data_out)
    begin
      register_bus_out = #1 data_mem[reg_address];
    end
  end
  else
  begin
    if (md_put_reg_data_out)
    begin
      case (reg_address)
      5'h0:    register_bus_out = #1 {control_bit15, control_bit14_10, control_bit9, control_bit8_0};
      5'h1:    register_bus_out = #1 {status_bit15_9, status_bit8, status_bit7, status_bit6_0};
      5'h2:    register_bus_out = #1 phy_id1;
      5'h3:    register_bus_out = #1 phy_id2;
      default: register_bus_out = #1 16'hDEAD;
      endcase
    end
  end
end


reg    self_clear_d0;
reg    self_clear_d1;
reg    self_clear_d2;
reg    self_clear_d3;

always@(posedge mdc_i or negedge m_rst_n_i)
begin
  if (!m_rst_n_i)
  begin
    self_clear_d0    <= #1 0;
    self_clear_d1    <= #1 0;
    self_clear_d2    <= #1 0;
    self_clear_d3    <= #1 0;
  end
  else
  begin
    self_clear_d0    <= #1 md_put_reg_data_in;
    self_clear_d1    <= #1 self_clear_d0;
    self_clear_d2    <= #1 self_clear_d1;
    self_clear_d3    <= #1 self_clear_d2;
  end
end


always@(posedge mdc_i or negedge m_rst_n_i)
begin
  if ((!m_rst_n_i) || (control_bit15))
  begin
    if (!registers_addr_data_test_operation)
    begin
      control_bit15    <= #1 0;
      control_bit14_10 <= #1 {1'b0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 2'b0};
      control_bit9     <= #1 0;
      control_bit8_0   <= #1 {`LED_CFG3, 8'b0};
    end
  end
  else
  begin
    if (registers_addr_data_test_operation)
    begin
      if (md_put_reg_data_in)
      begin
        data_mem[reg_address] <= #1 register_bus_in[15:0];
      end
    end
    else
    begin

      if (md_put_reg_data_in)
      begin
        case (reg_address)
        5'h0: 
        begin
          control_bit14_10 <= #1 register_bus_in[14:10];
          control_bit8_0   <= #1 register_bus_in[8:0];
        end
        default:
        begin
        end
        endcase
      end

      if ((md_put_reg_data_in) && (reg_address == 5'h0))
      begin
        control_bit15 <= #1 register_bus_in[15];
        control_bit9  <= #1 register_bus_in[9];
      end
      else if (self_clear_d3)
      begin
        control_bit15 <= #1 1'b0;
        control_bit9  <= #1 1'b0;
      end
    end
  end
end










reg             mcoll_o;
reg             mcrs_o;


reg             mcrs_rx;
reg             mcrs_tx;

reg             mtxen_d1;
reg             mtxen_d2;
reg             mtxen_d3;
reg             mtxen_d4;
reg             mtxen_d5;
reg             mtxen_d6;

reg             task_mcoll;

reg             task_mcrs;
reg             task_mcrs_lost;

reg             no_collision_in_half_duplex;

reg             collision_in_full_duplex;

reg             no_carrier_sense_in_tx_half_duplex;
reg             no_carrier_sense_in_rx_half_duplex;

reg             carrier_sense_in_tx_full_duplex;

reg             no_carrier_sense_in_rx_full_duplex;

reg             real_carrier_sense;

initial
begin
  mcrs_rx = 0;
  mcrs_tx = 0;
  task_mcoll = 0;
  task_mcrs = 0;
  task_mcrs_lost = 0;
  no_collision_in_half_duplex = 0;
  collision_in_full_duplex = 0;
  no_carrier_sense_in_tx_half_duplex = 0;
  no_carrier_sense_in_rx_half_duplex = 0;
  carrier_sense_in_tx_full_duplex = 0;
  no_carrier_sense_in_rx_full_duplex = 0;
  real_carrier_sense = 0;
end


always@(m_rst_n_i or control_bit8_0 or collision_in_full_duplex or 
        mcrs_rx or mcrs_tx or task_mcoll or no_collision_in_half_duplex
        )
begin
  if (!m_rst_n_i)
    mcoll_o = 0;
  else
  begin
    if (control_bit8_0[8])
    begin
      if (collision_in_full_duplex)
      begin
        mcoll_o = ((mcrs_rx && mcrs_tx) || task_mcoll);
        `ifdef VERBOSE
        if (mcrs_rx && mcrs_tx)
          $fdisplay(phy_log, "   (%0t)(%m) Collision set in FullDuplex!", $time);
        if (task_mcoll)
          $fdisplay(phy_log, "   (%0t)(%m) Collision set in FullDuplex from TASK!", $time);
        `endif
      end
      else
      begin
        mcoll_o = task_mcoll;
        `ifdef VERBOSE
        if (task_mcoll)
          $fdisplay(phy_log, "   (%0t)(%m) Collision set in FullDuplex from TASK!", $time);
        `endif
      end
    end
    else
    begin
      mcoll_o = ((mcrs_rx && mcrs_tx && !no_collision_in_half_duplex) || 
                  task_mcoll);
      `ifdef VERBOSE
      if (mcrs_rx && mcrs_tx)
        $fdisplay(phy_log, "   (%0t)(%m) Collision set in HalfDuplex!", $time);
      if (task_mcoll)
        $fdisplay(phy_log, "   (%0t)(%m) Collision set in HalfDuplex from TASK!", $time);
      `endif
    end
  end
end


always@(m_rst_n_i or control_bit8_0 or carrier_sense_in_tx_full_duplex or
        no_carrier_sense_in_rx_full_duplex or
        no_carrier_sense_in_tx_half_duplex or 
        no_carrier_sense_in_rx_half_duplex or 
        mcrs_rx or mcrs_tx or task_mcrs or task_mcrs_lost
        )
begin
  if (!m_rst_n_i)
    mcrs_o = 0;
  else
  begin
    if (control_bit8_0[8])
    begin
      if (carrier_sense_in_tx_full_duplex)
        mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_full_duplex) || 
                   mcrs_tx || task_mcrs) && !task_mcrs_lost;
      else
        mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_full_duplex) || 
                   task_mcrs) && !task_mcrs_lost;
    end
    else
    begin
      mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_half_duplex) || 
                (mcrs_tx && !no_carrier_sense_in_tx_half_duplex) || 
                 task_mcrs) && !task_mcrs_lost;
    end
  end
end




reg     [7:0]  tx_mem [0:4194303];
reg    [31:0]  tx_mem_addr_in;
reg     [7:0]  tx_mem_data_in;
reg    [31:0]  tx_cnt;


reg            tx_preamble_ok;
reg            tx_sfd_ok;

reg            tx_byte_aligned_ok;

reg    [31:0]  tx_len;

reg    [31:0]  tx_len_err;


always@(posedge mtx_clk_o)
begin

  if (!m_rst_n_i)
  begin
    tx_cnt <= 0;
    tx_preamble_ok <= 0;
    tx_sfd_ok <= 0;
    tx_len <= 0;
    tx_len_err <= 0;
  end
  else
  begin
    if (!mtxen_i)
    begin
      tx_cnt <= 0;
    end
    else
    begin

      tx_cnt <= tx_cnt + 1;

      if (tx_cnt == 0)
      begin
        `ifdef VERBOSE
        $fdisplay(phy_log, "   (%0t)(%m) TX frame started with tx_en set!", $time);
        `endif
        if (mtxd_i == 4'h5)
          tx_preamble_ok <= 1;
        else
          tx_preamble_ok <= 0;
        tx_sfd_ok <= 0;
        tx_byte_aligned_ok <= 0;
        tx_len <= 0;
        tx_len_err <= 0;

      end


      if ((tx_cnt > 0) && (tx_cnt <= 13))
      begin
        if ((tx_preamble_ok != 1) || (mtxd_i != 4'h5))
          tx_preamble_ok <= 0;
      end

      if (tx_cnt == 14)
      begin
        `ifdef VERBOSE
        if (tx_preamble_ok == 1)
          $fdisplay(phy_log, "   (%0t)(%m) TX frame preamble OK!", $time);
        else
          $fdisplay(phy_log, "*E (%0t)(%m) TX frame preamble NOT OK!", $time);
        `endif
        if (mtxd_i == 4'h5)
          tx_sfd_ok <= 1;
        else
          tx_sfd_ok <= 0;
      end
      if (tx_cnt == 15)
      begin
        if ((tx_sfd_ok != 1) || (mtxd_i != 4'hD))
          tx_sfd_ok <= 0;
      end


      if (tx_cnt > 15)
      begin
        if (tx_cnt == 16)
        begin
          `ifdef VERBOSE
          if (tx_sfd_ok == 1)
            $fdisplay(phy_log, "   (%0t)(%m) TX frame SFD OK!", $time);
          else
            $fdisplay(phy_log, "*E (%0t)(%m) TX frame SFD NOT OK!", $time);
          `endif
        end

        if (tx_cnt[0] == 0)
        begin
          tx_mem_data_in[3:0] <= mtxd_i;
          tx_byte_aligned_ok <= 0;
        end
        else
        begin
          tx_mem[tx_mem_addr_in[21:0]] <= {mtxd_i, tx_mem_data_in[3:0]};
          tx_len <= tx_len + 1;
          tx_byte_aligned_ok <= 1;
          tx_mem_addr_in <= tx_mem_addr_in + 1'b1;
        end

        if (mtxerr_i)
          tx_len_err <= tx_len;
      end
    end
  end


  if (!m_rst_n_i)
  begin
    mcrs_tx  <= 0;
    mtxen_d1 <= 0;
    mtxen_d2 <= 0;
    mtxen_d3 <= 0;
    mtxen_d4 <= 0;
    mtxen_d5 <= 0;
    mtxen_d6 <= 0;
  end
  else
  begin
    mtxen_d1 <= mtxen_i;
    mtxen_d2 <= mtxen_d1;
    mtxen_d3 <= mtxen_d2;
    mtxen_d4 <= mtxen_d3;
    mtxen_d5 <= mtxen_d4;
    mtxen_d6 <= mtxen_d5;
    if (real_carrier_sense)
      mcrs_tx  <= mtxen_d6;
    else
      mcrs_tx  <= mtxen_i;
  end
end

`ifdef VERBOSE
reg             frame_started;

initial
begin
  frame_started = 0;
end
always@(posedge mtxen_i)
begin
  frame_started <= 1;
end
always@(negedge mtxen_i)
begin
  if (frame_started)
  begin
    $fdisplay(phy_log, "   (%0t)(%m) TX frame ended with tx_en reset!", $time);
    frame_started <= 0;
  end
end

always@(posedge mrxerr_o)
begin
  $fdisplay(phy_log, "   (%0t)(%m) RX frame ERROR signal was set!", $time);
end
`endif







initial
begin
  tx_mem_addr_in = 0;
end


task set_tx_mem_addr;
  input [31:0] tx_mem_address;
begin
  #1 tx_mem_addr_in = tx_mem_address;
end
endtask


reg     [7:0]  rx_mem [0:4194303];


reg     [3:0]   mrxd_o;
reg             mrxdv_o;
reg             mrxerr_o;

initial
begin
  mrxd_o = 0;
  mrxdv_o = 0;
  mrxerr_o = 0;
  mcrs_rx = 0;
end

task send_rx_packet;
  input  [(8*8)-1:0] preamble_data;
  input   [3:0] preamble_len;
  input   [7:0] sfd_data;
  input  [31:0] start_addr;
  input  [31:0] len;
  input         plus_drible_nibble;
  integer       rx_cnt;
  reg    [31:0] rx_mem_addr_in;
  reg     [7:0] rx_mem_data_out;
begin
      @(posedge mrx_clk_o);

      if (real_carrier_sense)
        #1 mcrs_rx = 1;
      else
        #1 mcrs_rx = 0;
      @(posedge mrx_clk_o);
      #1 mcrs_rx = 1;
      #1 mrxdv_o = 1;
      `ifdef VERBOSE
      $fdisplay(phy_log, "   (%0t)(%m) RX frame started with rx_dv set!", $time);
      `endif

      rx_mem_addr_in = start_addr;
    

      for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
      begin
        #1 mrxd_o = preamble_data[3:0];
        #1 preamble_data = preamble_data >> 4;
        @(posedge mrx_clk_o);
      end
    

      for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1)
      begin
        #1 mrxd_o = sfd_data[3:0];
        #1 sfd_data = sfd_data >> 4;
        @(posedge mrx_clk_o);
      end
      `ifdef VERBOSE
      $fdisplay(phy_log, "   (%0t)(%m) RX frame preamble and SFD sent!", $time);
      `endif

      for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
      begin
        #1;
        rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
        mrxd_o = rx_mem_data_out[3:0];
        @(posedge mrx_clk_o);
        #1;
        mrxd_o = rx_mem_data_out[7:4];
        rx_mem_addr_in = rx_mem_addr_in + 1;
        @(posedge mrx_clk_o);
        #1;
      end
      if (plus_drible_nibble)
      begin
        rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
        mrxd_o = rx_mem_data_out[3:0];
        @(posedge mrx_clk_o);
      end
      `ifdef VERBOSE
      $fdisplay(phy_log, "   (%0t)(%m) RX frame addresses, type/length, data and FCS sent!", $time);
      `endif
      #1 mcrs_rx = 0;
      #1 mrxdv_o = 0;
      @(posedge mrx_clk_o);
      `ifdef VERBOSE
      $fdisplay(phy_log, "   (%0t)(%m) RX frame ended with rx_dv reset!", $time);
      `endif
end
endtask



task GetDataOnMRxD;
  input [15:0] Len;
  input [31:0] TransferType;
  integer tt;

  begin
    @ (posedge mrx_clk_o);
    #1 mrxdv_o=1'b1;

    for(tt=0; tt<15; tt=tt+1)
    begin
      mrxd_o=4'h5;
      @ (posedge mrx_clk_o);
      #1;
    end

    mrxd_o=4'hd;

    for(tt=1; tt<(Len+1); tt=tt+1)
    begin
      @ (posedge mrx_clk_o);
      #1;
      if(TransferType == `UNICAST_XFR && tt == 1)
        mrxd_o = 4'h0;
      else if(TransferType == `BROADCAST_XFR && tt < 7)
        mrxd_o = 4'hf;
      else
        mrxd_o = tt[3:0];

      @ (posedge mrx_clk_o);
      #1;

      if(TransferType == `BROADCAST_XFR && tt == 6)
        mrxd_o = 4'he;
      else

      if(TransferType == `BROADCAST_XFR && tt < 7)
        mrxd_o = 4'hf;
      else
        mrxd_o = tt[7:4];
    end

    @ (posedge mrx_clk_o);
    #1;
    mrxdv_o = 1'b0;
  end
endtask









task link_up_down;
  input   test_op;
begin
  #1 status_bit6_0[2] = test_op;
end
endtask


task rx_err;
  input   test_op;
begin
  #1 mrxerr_o = test_op;
end
endtask








task collision;
  input   test_op;
begin
  #1 task_mcoll = test_op;
end
endtask


task carrier_sense;
  input   test_op;
begin
  #1 task_mcrs = test_op;
end
endtask


task carrier_sense_lost;
  input   test_op;
begin
  #1 task_mcrs_lost = test_op;
end
endtask


task no_collision_hd_detect;
  input   test_op;
begin
  #1 no_collision_in_half_duplex = test_op;
end
endtask


task collision_fd_detect;
  input   test_op;
begin
  #1 collision_in_full_duplex = test_op;
end
endtask


task no_carrier_sense_tx_hd_detect;
  input   test_op;
begin
  #1 no_carrier_sense_in_tx_half_duplex = test_op;
end
endtask


task no_carrier_sense_rx_hd_detect;
  input   test_op;
begin
  #1 no_carrier_sense_in_rx_half_duplex = test_op;
end
endtask


task carrier_sense_tx_fd_detect;
  input   test_op;
begin
  #1 carrier_sense_in_tx_full_duplex = test_op;
end
endtask


task no_carrier_sense_rx_fd_detect;
  input   test_op;
begin
  #1 no_carrier_sense_in_rx_full_duplex = test_op;
end
endtask


task carrier_sense_real_delay;
  input   test_op;
begin
  #1 real_carrier_sense = test_op;
end
endtask








task test_regs;
  input   test_op;
begin
  #1 registers_addr_data_test_operation = test_op;
  respond_to_all_phy_addr = test_op;
end
endtask


task clear_test_regs;
  integer i;
begin
  for (i = 0; i < 32; i = i + 1)
  begin
    #1 data_mem[i] = 16'h0;
  end
end
endtask


task preamble_suppresed;
  input   test_op;
begin
  #1 no_preamble = test_op;
  md_transfer_cnt_reset = 1'b1;
  @(posedge mdc_i);
  #1 md_transfer_cnt_reset = 1'b0;
end
endtask





endmodule