data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:1: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Mips/Type/Word.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Mips/Type/Word.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Mips/Type/Word.v.sv\n             Mips/Type/Word.v\n             Mips/Type/Word.v.v\n             Mips/Type/Word.v.sv\n             obj_dir/Mips/Type/Word.v\n             obj_dir/Mips/Type/Word.v.v\n             obj_dir/Mips/Type/Word.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:2: Cannot find include file: Mips/Type/RegAddr.v\n`include "Mips/Type/RegAddr.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:3: Cannot find include file: Mips/Type/RegPorts.v\n`include "Mips/Type/RegPorts.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:5: Cannot find include file: Mips/Control/Control.v\n`include "Mips/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:6: Cannot find include file: Mips/Control/Signal/Register/Control.v\n`include "Mips/Control/Signal/Register/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:8: Cannot find include file: Mips/Datapath/Register/rd1Addr.v\n`include "Mips/Datapath/Register/rd1Addr.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:9: Cannot find include file: Mips/Datapath/Register/rd2Addr.v\n`include "Mips/Datapath/Register/rd2Addr.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:10: Cannot find include file: Mips/Datapath/Register/wrAddr.v\n`include "Mips/Datapath/Register/wrAddr.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:13: Define or directive not defined: \'`Mips_Type_RegPorts_T\'\n ( `Mips_Type_RegPorts_T (output) ports\n   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:13: syntax error, unexpected \'(\', expecting \'[\'\n ( `Mips_Type_RegPorts_T (output) ports\n                          ^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:14: Define or directive not defined: \'`Mips_Control_Control_T\'\n , `Mips_Control_Control_T (input) control\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:15: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input) instruction\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:18: Define or directive not defined: \'`Mips_Control_Signal_Register_Control_T\'\n`Mips_Control_Signal_Register_Control_T(wire) regControl;\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:19: Define or directive not defined: \'`Mips_Control_Control_Register\'\nassign regControl = `Mips_Control_Control_Register(control);\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:21: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n`Mips_Type_RegAddr_T (wire) rd1Addr;\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:27: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n`Mips_Type_RegAddr_T (wire) rd2Addr;\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:33: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n`Mips_Type_RegAddr_T (wire) wrAddr;\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:35: Define or directive not defined: \'`Mips_Control_Signal_Register_Control_WriteAddrSource\'\n ( .control     (`Mips_Control_Signal_Register_Control_WriteAddrSource(regControl))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:44: Define or directive not defined: \'`Mips_Control_Signal_Register_Control_WriteDataSource\'\n , .writeData (`Mips_Control_Signal_Register_Control_WriteDataSource(regControl))\n               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/ports.v:45: Define or directive not defined: \'`Mips_Control_Signal_Register_Control_WriteEnable\'\n , .writeEn (`Mips_Control_Signal_Register_Control_WriteEnable(regControl))\n             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 20 error(s)\n'
module Mips_Datapath_Register_ports
	( `Mips_Type_RegPorts_T (output) ports
	, `Mips_Control_Control_T (input) control
	, `Mips_Type_Word_T (input) instruction
	);

`Mips_Control_Signal_Register_Control_T(wire) regControl;
assign regControl = `Mips_Control_Control_Register(control);

`Mips_Type_RegAddr_T (wire) rd1Addr;
Mips_Datapath_Register_rd1Addr RD1A
	( .instruction (instruction)
	, .rd1Addr     (rd1Addr)
	);

`Mips_Type_RegAddr_T (wire) rd2Addr;
Mips_Datapath_Register_rd2Addr RD2A
	( .instruction (instruction)
	, .rd2Addr     (rd2Addr)
	);

`Mips_Type_RegAddr_T (wire) wrAddr;
Mips_Datapath_Register_wrAddr WRA
	( .control     (`Mips_Control_Signal_Register_Control_WriteAddrSource(regControl))
	, .instruction (instruction)
	, .wrAddr      (wrAddr)
	);

Mips_Type_RegPorts_pack PORTS
	( .read1Addr (rd1Addr)
	, .read2Addr (rd2Addr)
	, .writeAddr (wrAddr)
	, .writeData (`Mips_Control_Signal_Register_Control_WriteDataSource(regControl))
	, .writeEn (`Mips_Control_Signal_Register_Control_WriteEnable(regControl))
	, .out (ports)
	);

endmodule
module Mips_Datapath_Register_ports
	( `Mips_Type_RegPorts_T (output) ports
	, `Mips_Control_Control_T (input) control
	, `Mips_Type_Word_T (input) instruction
	);


`Mips_Control_Signal_Register_Control_T(wire) regControl;
assign regControl = `Mips_Control_Control_Register(control);

`Mips_Type_RegAddr_T (wire) rd1Addr;
Mips_Datapath_Register_rd1Addr RD1A
	( .instruction (instruction)
	, .rd1Addr     (rd1Addr)
	);

`Mips_Type_RegAddr_T (wire) rd2Addr;
Mips_Datapath_Register_rd2Addr RD2A
	( .instruction (instruction)
	, .rd2Addr     (rd2Addr)
	);

`Mips_Type_RegAddr_T (wire) wrAddr;
Mips_Datapath_Register_wrAddr WRA
	( .control     (`Mips_Control_Signal_Register_Control_WriteAddrSource(regControl))
	, .instruction (instruction)
	, .wrAddr      (wrAddr)
	);

Mips_Type_RegPorts_pack PORTS
	( .read1Addr (rd1Addr)
	, .read2Addr (rd2Addr)
	, .writeAddr (wrAddr)
	, .writeData (`Mips_Control_Signal_Register_Control_WriteDataSource(regControl))
	, .writeEn (`Mips_Control_Signal_Register_Control_WriteEnable(regControl))
	, .out (ports)
	);

endmodule