data/full_repos/permissive/195227969/work/cold_store/decompressattempts/old_m_decompress.v
 line:239: before: "["
1: b"%Error: data/full_repos/permissive/195227969/work/cold_store/decompressattempts/old_m_decompress.v:241: syntax error, unexpected '}', expecting ')' or ','\n   };\n   ^\n%Error: data/full_repos/permissive/195227969/work/cold_store/decompressattempts/old_m_decompress.v:248: syntax error, unexpected assign\n   assign aDi[31:16] = s[5] ? Di[15:0] : Di[31:16];\n   ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module m_decompress
  (
   input [31:0]      Di,
   input             s[5:0],
   output reg [31:0] I
   };
   wire [31:0]       aDi;
   wire [31:0]       uDi;
   wire [1:0]        seltype;
   wire [4:0]        rd_rs1;
   wire              rd_rs1_EQ_2;
   
   assign aDi[31:16] = s[5] ? Di[15:0] : Di[31:16];
   assign aDi[15:0]  = s[4] ? Di[31:16] : Di[15:0];

   always @(Di) 
     casez ( {aDi[1:0],aDi[15:13]} )
       5'b01_011 : seltype = 2'b01;
       5'b01_100 : seltype = 2'b10;
       5'b10_100 : seltype = 2'b11;
       5'b11_??? : seltype = 2'b??;
       default   : seltype = 2'b00;
     endcase

   assign rd_rs1 = aDi[11:7];
   assign rd_rs1_EQ_2 = rd_rs1 == 5'h2 ? 1'b1 : 1'b0;
   
   always @()
     if ( seltype == 2'b00 ) begin
        sel =  {Di[1:0],Di[15:13]};
     end else if ( seltype == 2'b01 ) begin
        sel =  {rd_rs1_EQ_2, Di[0], Di[15:13]};
     end else if ( seltype == 2'b10 ) begin
        
     end else begin
     end
endmodule
module m_decompress
  (
   input [31:0]      Di,
   input             s[5:0],
   output reg [31:0] I
   };

   wire [31:0]       aDi;
   wire [31:0]       uDi;
   wire [1:0]        seltype;
   wire [4:0]        rd_rs1;
   wire              rd_rs1_EQ_2;
   
   assign aDi[31:16] = s[5] ? Di[15:0] : Di[31:16];
   assign aDi[15:0]  = s[4] ? Di[31:16] : Di[15:0];

   always @(Di) 
     casez ( {aDi[1:0],aDi[15:13]} )
       5'b01_011 : seltype = 2'b01;
       5'b01_100 : seltype = 2'b10;
       5'b10_100 : seltype = 2'b11;
       5'b11_??? : seltype = 2'b??;
       default   : seltype = 2'b00;
     endcase

   assign rd_rs1 = aDi[11:7];
   assign rd_rs1_EQ_2 = rd_rs1 == 5'h2 ? 1'b1 : 1'b0;
   
   always @()
     if ( seltype == 2'b00 ) begin
        sel =  {Di[1:0],Di[15:13]};
     end else if ( seltype == 2'b01 ) begin
        sel =  {rd_rs1_EQ_2, Di[0], Di[15:13]};
     end else if ( seltype == 2'b10 ) begin
        
     end else begin
     end
endmodule