data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v
 line:88: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_reset_01 = 1\'b1;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:91: Unsupported: Ignoring delay on this delayed statement.\n    always #1 i_clk_01=~i_clk_01;  \n           ^\n%Error: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:93: Cannot find file containing module: \'interface_circuit\'\n    interface_circuit #(\n    ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/interface_circuit\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/interface_circuit.v\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/interface_circuit.sv\n             interface_circuit\n             interface_circuit.v\n             interface_circuit.sv\n             obj_dir/interface_circuit\n             obj_dir/interface_circuit.v\n             obj_dir/interface_circuit.sv\n%Error: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_interface_circuit.v:110: Cannot find file containing module: \'ALU\'\n    ALU #(\n    ^~~\n%Error: Exiting due to 2 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_interface_circuit();
    
    parameter  DBIT_01  = 8;
    parameter  NB_OP_01 = 6;
	           

    reg                        i_clk_01;
    reg                        i_reset_01;
    reg                        i_rx_done_tick_01;
    reg      [DBIT_01-1:0]     i_rx_data_in_01;
    wire      [DBIT_01-1:0]     i_alu_data_in_01;

	wire    [DBIT_01-1 : 0]    o_data_a_01;
	wire    [DBIT_01-1 : 0]    o_data_b_01;
	wire    [NB_OP_01-1 : 0]   o_operation_01;
    wire                       o_tx_start_01;
    wire    [DBIT_01-1:0]      o_data_out_01;

    initial begin
        i_clk_01 = 1'b0; 
        i_reset_01 = 1'b0;
        i_rx_done_tick_01 = 1'b0;
        i_rx_data_in_01 = {DBIT_01{1'b0}};


        #10 i_reset_01 = 1'b1;
        

        #10
        i_rx_data_in_01 = 8'b10010110;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        #10
        i_rx_data_in_01 = 8'b01101001;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        #10
        i_rx_data_in_01 = 8'b00100101;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        

        #10
        i_rx_data_in_01 = 8'd21;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        #10
        i_rx_data_in_01 = 8'd34;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        #10
        i_rx_data_in_01 = 8'b11100010;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        
        


        
        #10 $finish;
    end
    
    always #1 i_clk_01=~i_clk_01;

    interface_circuit #(
        .DBIT       (DBIT_01),
        .NB_OP      (NB_OP_01)
    )
    tb_interface_circuit_01 (
        .i_clk              (i_clk_01),
        .i_reset            (i_reset_01),
        .i_rx_done_tick     (i_rx_done_tick_01),
        .i_rx_data_in       (i_rx_data_in_01),
        .i_alu_data_in      (i_alu_data_in_01),
        .o_data_a           (o_data_a_01),
        .o_data_b           (o_data_b_01),
        .o_operation        (o_operation_01),
        .o_tx_start         (o_tx_start_01),
        .o_data_out         (o_data_out_01)
    );
    
    ALU #(
        .NB_DATA (DBIT_01)
    )

    u_ALU_01 (
        .i_operation (o_operation_01),
        .i_data_a (o_data_a_01),
        .i_data_b (o_data_b_01),
        .o_result (i_alu_data_in_01)
    );

endmodule
module tb_interface_circuit();

    
    parameter  DBIT_01  = 8;
    parameter  NB_OP_01 = 6;
	           

    reg                        i_clk_01;
    reg                        i_reset_01;
    reg                        i_rx_done_tick_01;
    reg      [DBIT_01-1:0]     i_rx_data_in_01;
    wire      [DBIT_01-1:0]     i_alu_data_in_01;

	wire    [DBIT_01-1 : 0]    o_data_a_01;
	wire    [DBIT_01-1 : 0]    o_data_b_01;
	wire    [NB_OP_01-1 : 0]   o_operation_01;
    wire                       o_tx_start_01;
    wire    [DBIT_01-1:0]      o_data_out_01;

    initial begin
        i_clk_01 = 1'b0; 
        i_reset_01 = 1'b0;
        i_rx_done_tick_01 = 1'b0;
        i_rx_data_in_01 = {DBIT_01{1'b0}};


        #10 i_reset_01 = 1'b1;
        

        #10
        i_rx_data_in_01 = 8'b10010110;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        #10
        i_rx_data_in_01 = 8'b01101001;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        #10
        i_rx_data_in_01 = 8'b00100101;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        

        #10
        i_rx_data_in_01 = 8'd21;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        #10
        i_rx_data_in_01 = 8'd34;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        #10
        i_rx_data_in_01 = 8'b11100010;
        i_rx_done_tick_01 = 1'b1;
        #1
        i_rx_done_tick_01 = 1'b0;
        
        


        
        #10 $finish;
    end
    
    always #1 i_clk_01=~i_clk_01;

    interface_circuit #(
        .DBIT       (DBIT_01),
        .NB_OP      (NB_OP_01)
    )
    tb_interface_circuit_01 (
        .i_clk              (i_clk_01),
        .i_reset            (i_reset_01),
        .i_rx_done_tick     (i_rx_done_tick_01),
        .i_rx_data_in       (i_rx_data_in_01),
        .i_alu_data_in      (i_alu_data_in_01),
        .o_data_a           (o_data_a_01),
        .o_data_b           (o_data_b_01),
        .o_operation        (o_operation_01),
        .o_tx_start         (o_tx_start_01),
        .o_data_out         (o_data_out_01)
    );
    
    ALU #(
        .NB_DATA (DBIT_01)
    )

    u_ALU_01 (
        .i_operation (o_operation_01),
        .i_data_a (o_data_a_01),
        .i_data_b (o_data_b_01),
        .o_result (i_alu_data_in_01)
    );

endmodule