data/full_repos/permissive/157587577/Basics/verilog/Assignments/assignments_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/157587577/Basics/verilog/Assignments/assignments_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157587577/Basics/verilog/Assignments/assignments_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #200\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157587577/Basics/verilog/Assignments/assignments_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #50 clk <= ~clk;\n    ^\n%Error: data/full_repos/permissive/157587577/Basics/verilog/Assignments/assignments_tb.v:10: Cannot find file containing module: \'assignments\'\nassignments uut(.clk(clk), .rst(rst), .data_nba(data_nba), .data_ba(data_ba));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157587577/Basics/verilog/Assignments,data/full_repos/permissive/157587577/assignments\n             data/full_repos/permissive/157587577/Basics/verilog/Assignments,data/full_repos/permissive/157587577/assignments.v\n             data/full_repos/permissive/157587577/Basics/verilog/Assignments,data/full_repos/permissive/157587577/assignments.sv\n             assignments\n             assignments.v\n             assignments.sv\n             obj_dir/assignments\n             obj_dir/assignments.v\n             obj_dir/assignments.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module assignments_tb();

    reg clk;
    reg rst;
    wire[7:0] data_nba;
    wire[7:0] data_ba;

assignments uut(.clk(clk), .rst(rst), .data_nba(data_nba), .data_ba(data_ba));

initial
begin
    rst = 1;
    clk = 0;
    #200
    rst = 0;
    #200
    rst = 1;
end

always
begin
    #50 clk <= ~clk;
end

endmodule
module assignments_tb();


    reg clk;
    reg rst;
    wire[7:0] data_nba;
    wire[7:0] data_ba;

assignments uut(.clk(clk), .rst(rst), .data_nba(data_nba), .data_ba(data_ba));

initial
begin
    rst = 1;
    clk = 0;
    #200
    rst = 0;
    #200
    rst = 1;
end

always
begin
    #50 clk <= ~clk;
end

endmodule