data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:46: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("votador-f_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:47: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test2);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = ~a;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #10 b = ~b;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-2_votador2/votador-f_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #20 c = ~c;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test2 ();




    reg a, b, c;
    wire v, v_f;



    votador uut (.v(v), .a(a), .b(b), .c(c));
    votador_f uutf (.v(v_f), .a(a), .b(b), .c(c));


    initial begin

        a = 0;
        b = 0;
        c = 0;


        $dumpfile("votador-f_tb.vcd");
        $dumpvars(0, test2);


        #100 $finish;
    end


    always
        #5 a = ~a;
    always
        #10 b = ~b;
    always
        #20 c = ~c;

endmodule
module test2 ();





    reg a, b, c;
    wire v, v_f;



    votador uut (.v(v), .a(a), .b(b), .c(c));
    votador_f uutf (.v(v_f), .a(a), .b(b), .c(c));


    initial begin

        a = 0;
        b = 0;
        c = 0;


        $dumpfile("votador-f_tb.vcd");
        $dumpvars(0, test2);


        #100 $finish;
    end


    always
        #5 a = ~a;
    always
        #10 b = ~b;
    always
        #20 c = ~c;

endmodule