data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'block_ram_sp\'\nmodule  block_ram_sp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'block_ram_dp\'\nmodule  block_ram_dp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'dist_ram_dp\'\nmodule  dist_ram_dp(\n        ^~~~~~~~~~~\n                                                                                             : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n                                                                                          : ... In instance per_dp2_0_r\n  counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n                                             ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module  mem_addr_ctrl_dp2_per0(
in_start,                          
counter_in,                         
wen_out,                         
out_start,                         
mem_addr_out_0,                         
mem_addr_out_1,                         
clk,                             
rst                              
);                               
  input in_start, clk, rst;                   
  input [4:0] counter_in; 
  output [4:0] mem_addr_out_0;            
  output [4:0] mem_addr_out_1;            
  output wen_out;
  output reg out_start;
  
  reg [1:0] state;        
  reg flag;        

  wire [4:0] mem_addr_out_tmp_0;   
  wire [4:0] mem_addr_out_tmp_1;   
  wire [4:0] mem_addr_out_w;        
  wire [0:0] mem_addr_out_w_h;        
  wire [3:0] mem_addr_out_w_l;        
  
  mem_addr_gen_dp2_mem0_per0 top_mem_addr_gen_inst (.clk(clk),.rst(rst),.addr_out(mem_addr_out_w), .counter_in(counter_in)); 

  assign mem_addr_out_w_h = mem_addr_out_w[4:4];        
  assign mem_addr_out_w_l = mem_addr_out_w[3:0];   
  assign mem_addr_out_tmp_0 = {mem_addr_out_w_h[0],mem_addr_out_w_l}; 
  assign mem_addr_out_tmp_1 = {~mem_addr_out_w_h[0],mem_addr_out_w_l}; 
  assign mem_addr_out_0 = ((flag == 1'b0) ? mem_addr_out_tmp_0 : counter_in); 
  assign mem_addr_out_1 = ((flag == 1'b0) ? mem_addr_out_tmp_1 : counter_in); 
  
  assign wen_out = state[0];        
  always@(posedge clk)             
  begin                            
    if(rst) begin                    
      out_start <= 1'b0; 
end
    else begin                        
      out_start <= (state == 2'b01) && (counter_in[4:0] == {5{1'b1}}); 
end                              
end                              

  always@(posedge clk)             
  begin                            
    if(rst) begin                    
      state <= 2'b0;            
      flag <= 1'b0;            
      end
    else begin                        
      case (state)              
        2'b00: begin              
          if (in_start)  begin              
            state <= 2'b01;              
            end
        end
        2'b01: begin              
          if (!in_start && counter_in == {5{1'b1}})  begin 
            state <= 2'b11;              
          end
          if (counter_in == {5{1'b1}})  begin 
            flag <= !flag;              
          end
        end
        2'b11: begin              
          if (counter_in == {5{1'b1}})  begin 
            state <= 2'b00;              
          end
        end
        default: state <= 2'b00;       
      endcase
    end
  end                              

endmodule
module  mem_addr_ctrl_dp2_per0(
in_start,                          
counter_in,                         
wen_out,                         
out_start,                         
mem_addr_out_0,                         
mem_addr_out_1,                         
clk,                             
rst                              
);
                               
  input in_start, clk, rst;                   
  input [4:0] counter_in; 
  output [4:0] mem_addr_out_0;            
  output [4:0] mem_addr_out_1;            
  output wen_out;
  output reg out_start;
  
  reg [1:0] state;        
  reg flag;        

  wire [4:0] mem_addr_out_tmp_0;   
  wire [4:0] mem_addr_out_tmp_1;   
  wire [4:0] mem_addr_out_w;        
  wire [0:0] mem_addr_out_w_h;        
  wire [3:0] mem_addr_out_w_l;        
  
  mem_addr_gen_dp2_mem0_per0 top_mem_addr_gen_inst (.clk(clk),.rst(rst),.addr_out(mem_addr_out_w), .counter_in(counter_in)); 

  assign mem_addr_out_w_h = mem_addr_out_w[4:4];        
  assign mem_addr_out_w_l = mem_addr_out_w[3:0];   
  assign mem_addr_out_tmp_0 = {mem_addr_out_w_h[0],mem_addr_out_w_l}; 
  assign mem_addr_out_tmp_1 = {~mem_addr_out_w_h[0],mem_addr_out_w_l}; 
  assign mem_addr_out_0 = ((flag == 1'b0) ? mem_addr_out_tmp_0 : counter_in); 
  assign mem_addr_out_1 = ((flag == 1'b0) ? mem_addr_out_tmp_1 : counter_in); 
  
  assign wen_out = state[0];        
  always@(posedge clk)             
  begin                            
    if(rst) begin                    
      out_start <= 1'b0; 
end
    else begin                        
      out_start <= (state == 2'b01) && (counter_in[4:0] == {5{1'b1}}); 
end                              
end                              

  always@(posedge clk)             
  begin                            
    if(rst) begin                    
      state <= 2'b0;            
      flag <= 1'b0;            
      end
    else begin                        
      case (state)              
        2'b00: begin              
          if (in_start)  begin              
            state <= 2'b01;              
            end
        end
        2'b01: begin              
          if (!in_start && counter_in == {5{1'b1}})  begin 
            state <= 2'b11;              
          end
          if (counter_in == {5{1'b1}})  begin 
            flag <= !flag;              
          end
        end
        2'b11: begin              
          if (counter_in == {5{1'b1}})  begin 
            state <= 2'b00;              
          end
        end
        default: state <= 2'b00;       
      endcase
    end
  end                              

endmodule