data/full_repos/permissive/132220215/testbenches/half_subtractor_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/132220215/testbenches/half_subtractor_tb.v:3: Cannot find include file: ../half_subtractor.v\n`include "../half_subtractor.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../half_subtractor.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../half_subtractor.v.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../half_subtractor.v.sv\n             ../half_subtractor.v\n             ../half_subtractor.v.v\n             ../half_subtractor.v.sv\n             obj_dir/../half_subtractor.v\n             obj_dir/../half_subtractor.v.v\n             obj_dir/../half_subtractor.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/half_subtractor_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #5 A_sig = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/half_subtractor_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #5 A_sig = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/half_subtractor_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #5 A_sig = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/half_subtractor_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #5 $finish;\n  ^\n%Error: data/full_repos/permissive/132220215/testbenches/half_subtractor_tb.v:30: Unsupported or unknown PLI call: $monitor\n  $monitor("TIME : %g A : %b B : %b D : %b Bo : %b",$time,A_sig,B_sig,diff_sig,bor_sig);\n  ^~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module half_sub_tb;

 input diff_sig,bor_sig;
 output reg A_sig,B_sig;

 half_subtract HS(.A(A_sig),.B(B_sig),.D(diff_sig),.Bo(bor_sig));

 initial 
 begin
	 A_sig = 1'b0;
	 B_sig = 1'b0;
	 
	 #5 A_sig = 1'b0;
	    B_sig = 1'b1;

	 #5 A_sig = 1'b1;
	    B_sig = 1'b0;

	 #5 A_sig = 1'b1;
	    B_sig = 1'b1;

	 #5 $finish;
 end

 initial
	 $monitor("TIME : %g A : %b B : %b D : %b Bo : %b",$time,A_sig,B_sig,diff_sig,bor_sig);

endmodule
module half_sub_tb;


 input diff_sig,bor_sig;
 output reg A_sig,B_sig;

 half_subtract HS(.A(A_sig),.B(B_sig),.D(diff_sig),.Bo(bor_sig));

 initial 
 begin
	 A_sig = 1'b0;
	 B_sig = 1'b0;
	 
	 #5 A_sig = 1'b0;
	    B_sig = 1'b1;

	 #5 A_sig = 1'b1;
	    B_sig = 1'b0;

	 #5 A_sig = 1'b1;
	    B_sig = 1'b1;

	 #5 $finish;
 end

 initial
	 $monitor("TIME : %g A : %b B : %b D : %b Bo : %b",$time,A_sig,B_sig,diff_sig,bor_sig);

endmodule