data/full_repos/permissive/127311496/src/platform/SWORD4/ShiftReg.v
1: b"%Error: data/full_repos/permissive/127311496/src/platform/SWORD4/ShiftReg.v:28: Cannot find file containing module: 'ODDR'\n ODDR #(\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/platform/SWORD4,data/full_repos/permissive/127311496/ODDR\n             data/full_repos/permissive/127311496/src/platform/SWORD4,data/full_repos/permissive/127311496/ODDR.v\n             data/full_repos/permissive/127311496/src/platform/SWORD4,data/full_repos/permissive/127311496/ODDR.sv\n             ODDR\n             ODDR.v\n             ODDR.sv\n             obj_dir/ODDR\n             obj_dir/ODDR.v\n             obj_dir/ODDR.sv\n%Error: Exiting due to 1 error(s)\n"
module ShiftReg #(
	parameter WIDTH = 16,
	parameter DELAY = 12,
	parameter DIRECTION = 1,
	parameter ONTIME = {DELAY{1'b1}},
	parameter inv = 1
)(
	input clk, input [WIDTH-1:0] pdata, output [2:0] sout
);
	wire sck;
	reg sdat;
	reg oe;
	assign sout = {sck, sdat, oe};
	
	reg [WIDTH-1:0] shift = 0;
	reg [DELAY-1:0] counter = -1;
	wire sckEn;
	
	assign sckEn = |shift;
	ODDR #(
		.INIT(1'b0)
	) sr_clk_fwd (
		.Q(sck),
		.C(clk),
		.CE(sckEn),
		.D1(1'b0),
		.D2(1'b1),
		.R(1'b0),
		.S(1'b0)
	);
	
	always @ (posedge clk)
	begin
		if(sckEn)
		begin
			shift <= DIRECTION? {shift[WIDTH-2:0], 1'b0}: {1'b0, shift[WIDTH-1:1]};
			sdat <= DIRECTION? shift[WIDTH-1]: shift[0];
		end
		else
		begin
			if(&counter)
			begin
				shift <= DIRECTION? {pdata[WIDTH-2:0], 1'b1}: {1'b1, pdata[WIDTH-1:1]};
				sdat <= DIRECTION? pdata[WIDTH-1]: pdata[0];
				oe <= 1'b0;
			end
			else
				oe <= (counter < ONTIME);
			counter <= counter + 1'b1;
		end
	end

endmodule
module ShiftReg #(
	parameter WIDTH = 16,
	parameter DELAY = 12,
	parameter DIRECTION = 1,
	parameter ONTIME = {DELAY{1'b1}},
	parameter inv = 1
)(
	input clk, input [WIDTH-1:0] pdata, output [2:0] sout
);

	wire sck;
	reg sdat;
	reg oe;
	assign sout = {sck, sdat, oe};
	
	reg [WIDTH-1:0] shift = 0;
	reg [DELAY-1:0] counter = -1;
	wire sckEn;
	
	assign sckEn = |shift;
	ODDR #(
		.INIT(1'b0)
	) sr_clk_fwd (
		.Q(sck),
		.C(clk),
		.CE(sckEn),
		.D1(1'b0),
		.D2(1'b1),
		.R(1'b0),
		.S(1'b0)
	);
	
	always @ (posedge clk)
	begin
		if(sckEn)
		begin
			shift <= DIRECTION? {shift[WIDTH-2:0], 1'b0}: {1'b0, shift[WIDTH-1:1]};
			sdat <= DIRECTION? shift[WIDTH-1]: shift[0];
		end
		else
		begin
			if(&counter)
			begin
				shift <= DIRECTION? {pdata[WIDTH-2:0], 1'b1}: {1'b1, pdata[WIDTH-1:1]};
				sdat <= DIRECTION? pdata[WIDTH-1]: pdata[0];
				oe <= 1'b0;
			end
			else
				oe <= (counter < ONTIME);
			counter <= counter + 1'b1;
		end
	end

endmodule