data/full_repos/permissive/127437148/FSM.v
1: b'%Error: data/full_repos/permissive/127437148/FSM.v:14: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("FSM.vcd"); \n^~~~~~~~~\n%Error: data/full_repos/permissive/127437148/FSM.v:15: Unsupported or unknown PLI call: $dumpvars\n$dumpvars; \n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/127437148/FSM.v:20: Unsupported: Ignoring delay on this delayed statement.\n#00 clk <= 1\'b0 ; \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/127437148/FSM.v:21: Unsupported: Ignoring delay on this delayed statement.\nforever #50 clk <= ~ clk ; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127437148/FSM.v:26: Unsupported: Ignoring delay on this delayed statement.\n#0000 rst = 1\'b1; #0050 rst = 1\'b0; #0010 op = 4\'b1000; #0000 func = 4\'b0000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/127437148/FSM.v:26: Unsupported: Ignoring delay on this delayed statement.\n#0000 rst = 1\'b1; #0050 rst = 1\'b0; #0010 op = 4\'b1000; #0000 func = 4\'b0000;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/127437148/FSM.v:26: Unsupported: Ignoring delay on this delayed statement.\n#0000 rst = 1\'b1; #0050 rst = 1\'b0; #0010 op = 4\'b1000; #0000 func = 4\'b0000;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/127437148/FSM.v:26: Unsupported: Ignoring delay on this delayed statement.\n#0000 rst = 1\'b1; #0050 rst = 1\'b0; #0010 op = 4\'b1000; #0000 func = 4\'b0000;\n                                                        ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_FSM();

reg [3:0]op, func;
reg clk, rst;
wire IntMemRead, PCWrite, PCWriteCond, FlagSel, IRWrite, PCSrc, IRRead, RegRead, MemtoReg, ExOp, RegWrite, MemRead, MemWrite;
wire [1:0]ALUSrc1, ALUSrc2;
wire [2:0] ALUop;

FSM uut (ALUSrc1, ALUSrc2, ALUop, IntMemRead, PCWrite, PCWriteCond, FlagSel, IRWrite, PCSrc, IRRead, RegRead, MemtoReg, ExOp, RegWrite, MemRead, MemWrite, clk, rst, op, func);

initial 
begin 
$dumpfile("FSM.vcd"); 
$dumpvars; 
end

initial 
begin 
#00 clk <= 1'b0 ; 
forever #50 clk <= ~ clk ; 
end

initial 
begin 
#0000 rst = 1'b1; #0050 rst = 1'b0; #0010 op = 4'b1000; #0000 func = 4'b0000;
end 
endmodule
module tb_FSM();


reg [3:0]op, func;
reg clk, rst;
wire IntMemRead, PCWrite, PCWriteCond, FlagSel, IRWrite, PCSrc, IRRead, RegRead, MemtoReg, ExOp, RegWrite, MemRead, MemWrite;
wire [1:0]ALUSrc1, ALUSrc2;
wire [2:0] ALUop;

FSM uut (ALUSrc1, ALUSrc2, ALUop, IntMemRead, PCWrite, PCWriteCond, FlagSel, IRWrite, PCSrc, IRRead, RegRead, MemtoReg, ExOp, RegWrite, MemRead, MemWrite, clk, rst, op, func);

initial 
begin 
$dumpfile("FSM.vcd"); 
$dumpvars; 
end

initial 
begin 
#00 clk <= 1'b0 ; 
forever #50 clk <= ~ clk ; 
end

initial 
begin 
#0000 rst = 1'b1; #0050 rst = 1'b0; #0010 op = 4'b1000; #0000 func = 4'b0000;
end 
endmodule