data/full_repos/permissive/114459345/srcCache/mem.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/mem.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:9: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] aluop_i,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`AluOpBus] aluop_i,\n                     ^\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:10: Define or directive not defined: \'`AluFunct3Bus\'\n input wire[`AluFunct3Bus] alufunct3_i,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`MemAddrBus] maddr_i, \n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:12: Define or directive not defined: \'`MemAddrBus\'\n input wire[`MemAddrBus] maddr_i, \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] wd_i,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:14: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] wd_i,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] wdata_i,  \n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:19: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`ValidBitBus] rvalid_bit,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:19: Define or directive not defined: \'`ValidBitBus\'\n output reg[`ValidBitBus] rvalid_bit,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:20: Define or directive not defined: \'`MemAddrBus\'\n output reg[`MemAddrBus] raddr_m,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:21: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] rdata_m,   \n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`ValidBitBus] wvalid_bit,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:23: Define or directive not defined: \'`ValidBitBus\'\n output reg[`ValidBitBus] wvalid_bit,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:24: Define or directive not defined: \'`MemAddrBus\'\n output reg[`MemAddrBus] waddr_m,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:25: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus] wdata_m,   \n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] wd_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:29: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_o,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:30: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wdata_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] wd_f,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:34: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_f,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:35: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wdata_f\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:39: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] mout;\n     ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] mout;\n            ^\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:43: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:44: Define or directive not defined: \'`ReadDisable\'\n   re_m <= `ReadDisable;\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:45: Define or directive not defined: \'`ZeroValidBit\'\n   rvalid_bit <= `ZeroValidBit;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:46: Define or directive not defined: \'`NopMem\'\n   raddr_m <= `NopMem;\n              ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:47: Define or directive not defined: \'`WriteDisable\'\n   we_m <= `WriteDisable;\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:48: Define or directive not defined: \'`ZeroValidBit\'\n   wvalid_bit <= `ZeroValidBit;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:49: Define or directive not defined: \'`NopMem\'\n   waddr_m <= `NopMem;\n              ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:50: Define or directive not defined: \'`ZeroWord\'\n   wdata_m <= `ZeroWord; \n              ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:53: Define or directive not defined: \'`ReadDisable\'\n   re_m <= `ReadDisable;\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:54: Define or directive not defined: \'`ZeroValidBit\'\n   rvalid_bit <= `ZeroValidBit;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:55: Define or directive not defined: \'`NopMem\'\n   raddr_m <= `NopMem;\n              ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:56: Define or directive not defined: \'`WriteDisable\'\n   we_m <= `WriteDisable;\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:57: Define or directive not defined: \'`ZeroValidBit\'\n   wvalid_bit <= `ZeroValidBit;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:58: Define or directive not defined: \'`NopMem\'\n   waddr_m <= `NopMem;\n              ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:59: Define or directive not defined: \'`ZeroWord\'\n   wdata_m <= `ZeroWord;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:61: Define or directive not defined: \'`MemEnable\'\n   if(me_i == `MemEnable) begin\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:63: Define or directive not defined: \'`LOAD\'\n     `LOAD : begin\n     ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:64: Define or directive not defined: \'`ReadEnable\'\n      re_m <= `ReadEnable;\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:67: Define or directive not defined: \'`LB\'\n       `LB : begin\n       ^~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:68: Define or directive not defined: \'`Byte\'\n        rvalid_bit <= `Byte;\n                      ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:70: Define or directive not defined: \'`LH\'\n       `LH : begin\n       ^~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:71: Define or directive not defined: \'`Half\'\n        rvalid_bit <= `Half;       \n                      ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:73: Define or directive not defined: \'`LW\'\n       `LW : begin\n       ^~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:74: Define or directive not defined: \'`Word\'\n        rvalid_bit <= `Word;\n                      ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:76: Define or directive not defined: \'`LBU\'\n       `LBU : begin\n       ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mem(

	input wire rst,
	

	input wire[`AluOpBus] aluop_i,
	input wire[`AluFunct3Bus] alufunct3_i,
	input wire me_i,
	input wire[`MemAddrBus] maddr_i,
	input wire wreg_i,
	input wire[`RegAddrBus] wd_i,
	input wire[`RegBus] wdata_i,
	

	output reg re_m,
	output reg[`ValidBitBus] rvalid_bit,
	output reg[`MemAddrBus] raddr_m,
	input wire[`DataBus] rdata_m,
	output reg we_m,
	output reg[`ValidBitBus] wvalid_bit,
	output reg[`MemAddrBus] waddr_m,
	output reg[`DataBus] wdata_m,


	output reg wreg_o,
	output reg[`RegAddrBus] wd_o,
	output reg[`RegBus] wdata_o,
	

	output reg wreg_f,
	output reg[`RegAddrBus] wd_f,
	output reg[`RegBus] wdata_f

);

	reg[`RegBus] mout;


	always @ (*) begin
		if(rst == `RstEnable) begin
			re_m <= `ReadDisable;
			rvalid_bit <= `ZeroValidBit;
			raddr_m <= `NopMem;
			we_m <= `WriteDisable;
			wvalid_bit <= `ZeroValidBit;
			waddr_m <= `NopMem;
			wdata_m <= `ZeroWord;	
		end
		else begin
			re_m <= `ReadDisable;
			rvalid_bit <= `ZeroValidBit;
			raddr_m <= `NopMem;
			we_m <= `WriteDisable;
			wvalid_bit <= `ZeroValidBit;
			waddr_m <= `NopMem;
			wdata_m <= `ZeroWord;
			
			if(me_i == `MemEnable) begin
				case(aluop_i)
					`LOAD : begin
						re_m <= `ReadEnable;
						raddr_m <= maddr_i;
						case(alufunct3_i)
							`LB : begin
								rvalid_bit <= `Byte;
							end
							`LH : begin
								rvalid_bit <= `Half;							
							end
							`LW : begin
								rvalid_bit <= `Word;
							end
							`LBU : begin
								rvalid_bit <= `Byte;
							end
							`LHU : begin
								rvalid_bit <= `Half;
							end
						endcase
					end
					`STORE : begin
						case(alufunct3_i)
							`SB : begin
								we_m <= `WriteEnable;
								wvalid_bit <= `Byte;
								waddr_m <= maddr_i;
								wdata_m <= {{24{1'b0}}, wdata_i[7:0]};
							end
							`SH : begin
								we_m <= `WriteEnable;
								wvalid_bit <= `Half;
								waddr_m <= maddr_i;
								wdata_m <= {{16{1'b0}}, wdata_i[15:0]};	
							end
							`SW : begin
								we_m <= `WriteEnable;
								wvalid_bit <= `Word;
								waddr_m <= maddr_i;
								wdata_m <= wdata_i[31:0];
							end
						endcase					
					end
					default : begin

					end
				endcase
			end		
		end
	end


	always @ (*) begin
		if(rst == `RstEnable) begin
			mout <= `ZeroWord;
		end
		else begin
			mout <= `ZeroWord;
			if(aluop_i == `LOAD) begin
				case(alufunct3_i)
					`LB : begin
						mout <= {{24{rdata_m[7]}},rdata_m[7:0]};
					end
					`LH : begin
						mout <= {{16{rdata_m[15]}},rdata_m[15:0]};
					end
					`LW : begin
						mout <= rdata_m;
					end
					`LBU : begin
						mout <= {{24{1'b0}},rdata_m[7:0]};					
					end
					`LHU : begin					
						mout <= {{16{1'b0}},rdata_m[15:0]};
					end
					default : begin

					end
				endcase
			end
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			wreg_o <= `WriteDisable;
			wd_o <= `NopRegAddr;
			wdata_o <= `ZeroWord;
		end
		else begin
			wreg_o <= wreg_i;
			wd_o <= wd_i;
			if(aluop_i == `LOAD) begin
				wdata_o <= mout;
			end
			else begin
				wdata_o <= wdata_i;
			end
		end
	end
	

	always @ (*) begin 
		if(rst == `RstEnable) begin
			wreg_f <= `WriteDisable;
			wd_f <= `NopRegAddr;
			wdata_f <= `ZeroWord;
		end
		else begin
			wreg_f <= wreg_o;
			wd_f <= wd_o;
			wdata_f <= wdata_o;	
		end
	end

endmodule
module mem(

	input wire rst,
	

	input wire[`AluOpBus] aluop_i,
	input wire[`AluFunct3Bus] alufunct3_i,
	input wire me_i,
	input wire[`MemAddrBus] maddr_i,
	input wire wreg_i,
	input wire[`RegAddrBus] wd_i,
	input wire[`RegBus] wdata_i,
	

	output reg re_m,
	output reg[`ValidBitBus] rvalid_bit,
	output reg[`MemAddrBus] raddr_m,
	input wire[`DataBus] rdata_m,
	output reg we_m,
	output reg[`ValidBitBus] wvalid_bit,
	output reg[`MemAddrBus] waddr_m,
	output reg[`DataBus] wdata_m,


	output reg wreg_o,
	output reg[`RegAddrBus] wd_o,
	output reg[`RegBus] wdata_o,
	

	output reg wreg_f,
	output reg[`RegAddrBus] wd_f,
	output reg[`RegBus] wdata_f

);


	reg[`RegBus] mout;


	always @ (*) begin
		if(rst == `RstEnable) begin
			re_m <= `ReadDisable;
			rvalid_bit <= `ZeroValidBit;
			raddr_m <= `NopMem;
			we_m <= `WriteDisable;
			wvalid_bit <= `ZeroValidBit;
			waddr_m <= `NopMem;
			wdata_m <= `ZeroWord;	
		end
		else begin
			re_m <= `ReadDisable;
			rvalid_bit <= `ZeroValidBit;
			raddr_m <= `NopMem;
			we_m <= `WriteDisable;
			wvalid_bit <= `ZeroValidBit;
			waddr_m <= `NopMem;
			wdata_m <= `ZeroWord;
			
			if(me_i == `MemEnable) begin
				case(aluop_i)
					`LOAD : begin
						re_m <= `ReadEnable;
						raddr_m <= maddr_i;
						case(alufunct3_i)
							`LB : begin
								rvalid_bit <= `Byte;
							end
							`LH : begin
								rvalid_bit <= `Half;							
							end
							`LW : begin
								rvalid_bit <= `Word;
							end
							`LBU : begin
								rvalid_bit <= `Byte;
							end
							`LHU : begin
								rvalid_bit <= `Half;
							end
						endcase
					end
					`STORE : begin
						case(alufunct3_i)
							`SB : begin
								we_m <= `WriteEnable;
								wvalid_bit <= `Byte;
								waddr_m <= maddr_i;
								wdata_m <= {{24{1'b0}}, wdata_i[7:0]};
							end
							`SH : begin
								we_m <= `WriteEnable;
								wvalid_bit <= `Half;
								waddr_m <= maddr_i;
								wdata_m <= {{16{1'b0}}, wdata_i[15:0]};	
							end
							`SW : begin
								we_m <= `WriteEnable;
								wvalid_bit <= `Word;
								waddr_m <= maddr_i;
								wdata_m <= wdata_i[31:0];
							end
						endcase					
					end
					default : begin

					end
				endcase
			end		
		end
	end


	always @ (*) begin
		if(rst == `RstEnable) begin
			mout <= `ZeroWord;
		end
		else begin
			mout <= `ZeroWord;
			if(aluop_i == `LOAD) begin
				case(alufunct3_i)
					`LB : begin
						mout <= {{24{rdata_m[7]}},rdata_m[7:0]};
					end
					`LH : begin
						mout <= {{16{rdata_m[15]}},rdata_m[15:0]};
					end
					`LW : begin
						mout <= rdata_m;
					end
					`LBU : begin
						mout <= {{24{1'b0}},rdata_m[7:0]};					
					end
					`LHU : begin					
						mout <= {{16{1'b0}},rdata_m[15:0]};
					end
					default : begin

					end
				endcase
			end
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			wreg_o <= `WriteDisable;
			wd_o <= `NopRegAddr;
			wdata_o <= `ZeroWord;
		end
		else begin
			wreg_o <= wreg_i;
			wd_o <= wd_i;
			if(aluop_i == `LOAD) begin
				wdata_o <= mout;
			end
			else begin
				wdata_o <= wdata_i;
			end
		end
	end
	

	always @ (*) begin 
		if(rst == `RstEnable) begin
			wreg_f <= `WriteDisable;
			wd_f <= `NopRegAddr;
			wdata_f <= `ZeroWord;
		end
		else begin
			wreg_f <= wreg_o;
			wd_f <= wd_o;
			wdata_f <= wdata_o;	
		end
	end

endmodule