data/full_repos/permissive/201488448/2_circuits/2_sequential/31_lfsr3.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/31_lfsr3.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'LEDR'\n                                                                                             : ... In instance top_module\n        LEDR <= D;\n        ^~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
	input [2:0] SW,
	input [1:0] KEY,
	output [2:0] LEDR);

    reg	[2:0]	D;
    
    always@(posedge KEY[0]) begin
       	LEDR <= D;
    end
    
    assign	D[0] = KEY[1]?SW[0]:LEDR[2];
    assign	D[1] = KEY[1]?SW[1]:LEDR[0];
    assign	D[2] = KEY[1]?SW[2]:(LEDR[2]^LEDR[1]);
    
endmodule
module top_module (
	input [2:0] SW,
	input [1:0] KEY,
	output [2:0] LEDR);


    reg	[2:0]	D;
    
    always@(posedge KEY[0]) begin
       	LEDR <= D;
    end
    
    assign	D[0] = KEY[1]?SW[0]:LEDR[2];
    assign	D[1] = KEY[1]?SW[1]:LEDR[0];
    assign	D[2] = KEY[1]?SW[2]:(LEDR[2]^LEDR[1]);
    
endmodule