data/full_repos/permissive/143278/ivltests/pr1603313.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603313.v:11: Unsupported: Ignoring delay on this delayed statement.\n    forever #0.5 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603313.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1603313.v:76: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 4 bits.\n                                                                         : ... In instance TestMultiplier.mul\n    exp[2:0] <= sumExp + 3;\n             ^~\n%Warning-INFINITELOOP: data/full_repos/permissive/143278/ivltests/pr1603313.v:11: Infinite loop (condition always true)\n                                                                                : ... In instance TestMultiplier\n    forever #0.5 clk = ~clk;\n    ^~~~~~~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Multiplier(clk,
                  left, right,
                  exp);
  input clk;
  input[5:0] left, right;

  output[2:0] exp;
  reg[2:0] exp;




  wire signed[2:0] expl = left[5:3] - 3;
  wire signed[2:0] expr = right[5:3] - 3;


  reg signed[3:0] sumExp;


  always @ (posedge clk) begin




    sumExp <= (expl + expr) < -2

            ? -3
            : expl + expr;

    exp[2:0] <= sumExp + 3;
  end
endmodule
module Multiplier(clk,
                  left, right,
                  exp);

  input clk;
  input[5:0] left, right;

  output[2:0] exp;
  reg[2:0] exp;




  wire signed[2:0] expl = left[5:3] - 3;
  wire signed[2:0] expr = right[5:3] - 3;


  reg signed[3:0] sumExp;


  always @ (posedge clk) begin




    sumExp <= (expl + expr) < -2

            ? -3
            : expl + expr;

    exp[2:0] <= sumExp + 3;
  end
endmodule