data/full_repos/permissive/136197078/hardware/ip/nt_timestamp/hdl/nt_timestamp.v
data/verilator_xmls/f3772f5f-2874-45d1-bf6a-bf0d1968a7ff.xml
module nt_timestamp (

  input wire        clk,
  input wire        rstn,


  input wire [7:0]  cycles_per_tick_i,


  output reg [23:0] timestamp_o
);

  reg [7:0] tick_cntr;



  always @(posedge clk) begin
    if (~rstn) begin
      timestamp_o <= 24'b0;
    end else begin
      if (tick_cntr == (cycles_per_tick_i - 1)) begin
        if (timestamp_o == 24'hFFFFFF) begin
          timestamp_o <= 24'b0;
        end else begin
          timestamp_o <= timestamp_o + 24'b1;
        end
      end else begin
        timestamp_o <= timestamp_o;
      end
    end
  end



  always @(posedge clk) begin
    if (~rstn) begin
      tick_cntr <= 8'b0;
    end else begin
      if (tick_cntr >= (cycles_per_tick_i - 1)) begin
        tick_cntr <= 8'b0;
      end else begin
        tick_cntr <= tick_cntr + 8'b1;
      end
    end
  end

endmodule
module nt_timestamp (

  input wire        clk,
  input wire        rstn,


  input wire [7:0]  cycles_per_tick_i,


  output reg [23:0] timestamp_o
);


  reg [7:0] tick_cntr;



  always @(posedge clk) begin
    if (~rstn) begin
      timestamp_o <= 24'b0;
    end else begin
      if (tick_cntr == (cycles_per_tick_i - 1)) begin
        if (timestamp_o == 24'hFFFFFF) begin
          timestamp_o <= 24'b0;
        end else begin
          timestamp_o <= timestamp_o + 24'b1;
        end
      end else begin
        timestamp_o <= timestamp_o;
      end
    end
  end



  always @(posedge clk) begin
    if (~rstn) begin
      tick_cntr <= 8'b0;
    end else begin
      if (tick_cntr >= (cycles_per_tick_i - 1)) begin
        tick_cntr <= 8'b0;
      end else begin
        tick_cntr <= tick_cntr + 8'b1;
      end
    end
  end

endmodule