data/full_repos/permissive/18770871/pc.v
data/verilator_xmls/ff2f6b1c-1b46-4c78-8491-b58cb83d8458.xml
module pc(in, out, clk, rst, stall);
    input[15:0] in;
    input clk;
    input rst;
    input stall;
    output [15:0] out;
    
    reg[15:0] value;
    
    always@(posedge clk or posedge rst) begin
        if(rst)
            begin
            value <= 16'b0000000000000000;
            end
        else
            begin
                if(stall!==1'b1) begin value <= in; end
            end
    end
    assign out = value;
endmodule
module pc(in, out, clk, rst, stall);

    input[15:0] in;
    input clk;
    input rst;
    input stall;
    output [15:0] out;
    
    reg[15:0] value;
    
    always@(posedge clk or posedge rst) begin
        if(rst)
            begin
            value <= 16'b0000000000000000;
            end
        else
            begin
                if(stall!==1'b1) begin value <= in; end
            end
    end
    assign out = value;
endmodule