data/full_repos/permissive/143278/ivltests/always_comb.v
 line:5: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always_comb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always_comb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always_comb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always_comb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always_comb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always_comb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg y, a, b, flip, hidden;
  reg pass;

  function f_and (input i1, i2);
    reg  partial;
    begin
      partial = i1 & i2;
      f_and = partial | hidden;
    end
  endfunction

  reg intr;
  always_comb begin
    intr = flip;
    y = f_and(a, b) ^ intr;
  end

  initial begin
    pass = 1'b1;

    flip = 1'b0;
    hidden = 1'b0;
    a = 1'b0;
    b = 1'b0;
    #1;
    if (y !== 1'b0) begin
      $display("FAILED: a=1'b0, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y);
      pass = 1'b0;
    end

    a = 1'b0;
    b = 1'b1;
    #1;
    if (y !== 1'b0) begin
      $display("FAILED: a=1'b0, b=1'b1, hidden=1'b0, expected 1'b0, got %b", y);
      pass = 1'b0;
    end

    a = 1'b1;
    b = 1'b0;
    #1;
    if (y !== 1'b0) begin
      $display("FAILED: a=1'b1, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y);
      pass = 1'b0;
    end

    a = 1'b1;
    b = 1'b1;
    #1;
    if (y !== 1'b1) begin
      $display("FAILED: a=1'b1, b=1'b1, hidden=1'b0, expected 1'b1, got %b", y);
      pass = 1'b0;
    end

    hidden = 1'b0;
    a = 1'b0;
    b = 1'b0;
    #1;
    if (y !== 1'b0) begin
      $display("FAILED: a=1'b0, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y);
      pass = 1'b0;
    end

    hidden = 1'b1;
    a = 1'b0;
    b = 1'b0;
    #1;
    if (y !== 1'b1) begin
      $display("FAILED: a=1'b0, b=1'b0, hidden=1'b1, expected 1'b1, got %b", y);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg y, a, b, flip, hidden;
  reg pass;

  function f_and (input i1, i2);
    reg  partial;
    begin
      partial = i1 & i2;
      f_and = partial | hidden;
    end
  endfunction

  reg intr;
  always_comb begin
    intr = flip;
    y = f_and(a, b) ^ intr;
  end

  initial begin
    pass = 1'b1;

    flip = 1'b0;
    hidden = 1'b0;
    a = 1'b0;
    b = 1'b0;
    #1;
    if (y !== 1'b0) begin
      $display("FAILED: a=1'b0, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y);
      pass = 1'b0;
    end

    a = 1'b0;
    b = 1'b1;
    #1;
    if (y !== 1'b0) begin
      $display("FAILED: a=1'b0, b=1'b1, hidden=1'b0, expected 1'b0, got %b", y);
      pass = 1'b0;
    end

    a = 1'b1;
    b = 1'b0;
    #1;
    if (y !== 1'b0) begin
      $display("FAILED: a=1'b1, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y);
      pass = 1'b0;
    end

    a = 1'b1;
    b = 1'b1;
    #1;
    if (y !== 1'b1) begin
      $display("FAILED: a=1'b1, b=1'b1, hidden=1'b0, expected 1'b1, got %b", y);
      pass = 1'b0;
    end

    hidden = 1'b0;
    a = 1'b0;
    b = 1'b0;
    #1;
    if (y !== 1'b0) begin
      $display("FAILED: a=1'b0, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y);
      pass = 1'b0;
    end

    hidden = 1'b1;
    a = 1'b0;
    b = 1'b0;
    #1;
    if (y !== 1'b1) begin
      $display("FAILED: a=1'b0, b=1'b0, hidden=1'b1, expected 1'b1, got %b", y);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule