data/full_repos/permissive/187199324/stannel/ResumeState.v
1: b'%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:4: Define or directive not defined: \'`ADDRESS_BITS\'\nmodule ResumeState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:4: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nmodule ResumeState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                       ^\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:4: Define or directive not defined: \'`DATA_BITS\'\nmodule ResumeState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:4: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule ResumeState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                                                        ^\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:7: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                reset,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:8: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [dataBits-1:0] dataOut,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:9: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [addrBits-1:0] address,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:10: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                rwMode,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:11: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                finished,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [addrBits-1:0] stackPointer,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [addrBits-1:0] callStackPointer,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [8:0]          programCounter,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [3:0]          aluFlags\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:17: syntax error, unexpected \')\', expecting \',\' or \';\'\n  );\n  ^\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:25: syntax error, unexpected assign\n  assign stackPointer     = rStackPointer;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:31: syntax error, unexpected assign\n  assign address = wAddress;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:32: Define or directive not defined: \'`RAM_READ\'\n  assign rwMode = `RAM_READ;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:34: Define or directive not defined: \'`RAM_READ\'\n  assign rwMode = `RAM_READ;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:43: syntax error, unexpected assign\n  assign finished = rState == LOAD_DONE;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/ResumeState.v:50: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: Exiting due to 21 error(s)\n'
module ResumeState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    input  wire [dataBits-1:0] dataOut,
    output wire [addrBits-1:0] address,
    output wire                rwMode,
    output wire                finished,

    output wire [addrBits-1:0] stackPointer,
    output wire [addrBits-1:0] callStackPointer,
    output wire [8:0]          programCounter,
    output wire [3:0]          aluFlags
  );



  reg [addrBits-1:0] rStackPointer, rCallStackPointer;
  reg [8:0] rProgramCounter;
  reg [3:0] rAluFlags;

  assign stackPointer     = rStackPointer;
  assign callStackPointer = rCallStackPointer;
  assign programCounter   = rProgramCounter;
  assign aluFlags         = rAluFlags;

  reg [addrBits-1:0] wAddress;
  assign address = wAddress;
  assign rwMode = `RAM_READ;

  assign rwMode = `RAM_READ;

  reg rRamCycle;
  reg [1:0] rState;

  localparam LOAD_STACK_POINTERS            = 2'd0;
  localparam LOAD_PROGRAM_COUNTER_AND_FLAGS = 2'd1;
  localparam LOAD_DONE                      = 2'd2;

  assign finished = rState == LOAD_DONE;

  reg wUpdateStackPointers;
  reg wUpdateProgramCounterAndAlu;



  always @(posedge clk)
  begin
    if (!reset)
      rRamCycle <= 0;
    else
      rRamCycle <= rRamCycle + 1;

    if (wUpdateStackPointers)
    begin
      rStackPointer     <= dataOut[15:8];
      rCallStackPointer <= dataOut[7:0] + 8'd2;
    end

    if (wUpdateProgramCounterAndAlu)
    begin
      rProgramCounter   <= dataOut[8:0];
      rAluFlags         <= dataOut[15:12];
    end

    if (!reset)
      rState <= 0;
    else if (rRamCycle)
      rState <= rState + 1;
  end

  always @(*)
  begin
    wUpdateStackPointers = 0;
    wUpdateProgramCounterAndAlu = 0;
    wAddress = {addrBits{1'bx}};
    case (rState)
      LOAD_STACK_POINTERS:
      begin
        wAddress = 0;
        wUpdateStackPointers = rRamCycle;
      end
      LOAD_PROGRAM_COUNTER_AND_FLAGS:
      begin
        wAddress = 1;
        wUpdateProgramCounterAndAlu = rRamCycle;
      end
      default:
      begin
      end
    endcase
  end
endmodule
module ResumeState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    input  wire [dataBits-1:0] dataOut,
    output wire [addrBits-1:0] address,
    output wire                rwMode,
    output wire                finished,

    output wire [addrBits-1:0] stackPointer,
    output wire [addrBits-1:0] callStackPointer,
    output wire [8:0]          programCounter,
    output wire [3:0]          aluFlags
  );




  reg [addrBits-1:0] rStackPointer, rCallStackPointer;
  reg [8:0] rProgramCounter;
  reg [3:0] rAluFlags;

  assign stackPointer     = rStackPointer;
  assign callStackPointer = rCallStackPointer;
  assign programCounter   = rProgramCounter;
  assign aluFlags         = rAluFlags;

  reg [addrBits-1:0] wAddress;
  assign address = wAddress;
  assign rwMode = `RAM_READ;

  assign rwMode = `RAM_READ;

  reg rRamCycle;
  reg [1:0] rState;

  localparam LOAD_STACK_POINTERS            = 2'd0;
  localparam LOAD_PROGRAM_COUNTER_AND_FLAGS = 2'd1;
  localparam LOAD_DONE                      = 2'd2;

  assign finished = rState == LOAD_DONE;

  reg wUpdateStackPointers;
  reg wUpdateProgramCounterAndAlu;



  always @(posedge clk)
  begin
    if (!reset)
      rRamCycle <= 0;
    else
      rRamCycle <= rRamCycle + 1;

    if (wUpdateStackPointers)
    begin
      rStackPointer     <= dataOut[15:8];
      rCallStackPointer <= dataOut[7:0] + 8'd2;
    end

    if (wUpdateProgramCounterAndAlu)
    begin
      rProgramCounter   <= dataOut[8:0];
      rAluFlags         <= dataOut[15:12];
    end

    if (!reset)
      rState <= 0;
    else if (rRamCycle)
      rState <= rState + 1;
  end

  always @(*)
  begin
    wUpdateStackPointers = 0;
    wUpdateProgramCounterAndAlu = 0;
    wAddress = {addrBits{1'bx}};
    case (rState)
      LOAD_STACK_POINTERS:
      begin
        wAddress = 0;
        wUpdateStackPointers = rRamCycle;
      end
      LOAD_PROGRAM_COUNTER_AND_FLAGS:
      begin
        wAddress = 1;
        wUpdateProgramCounterAndAlu = rRamCycle;
      end
      default:
      begin
      end
    endcase
  end
endmodule