data/full_repos/permissive/211878730/atlys/practice/register4_sync_reset.v
data/verilator_xmls/111b51c5-a288-4229-b60a-6001fa5363bf.xml
module register4_sync_reset(
	input  wire clk,
	input  wire reset,
	input  wire [3:0] data,
	output reg [3:0] q
    );
	 
	always @ (posedge clk) begin
		if (reset == 1'b0) begin
			q <= 4'b0;
		end else begin
			q <= data;
		end
	end
endmodule
module register4_sync_reset(
	input  wire clk,
	input  wire reset,
	input  wire [3:0] data,
	output reg [3:0] q
    );

	 
	always @ (posedge clk) begin
		if (reset == 1'b0) begin
			q <= 4'b0;
		end else begin
			q <= data;
		end
	end
endmodule