data/full_repos/permissive/155713836/tb/tb_fifo.v
 line:44: before: "$"
1: b'%Error: data/full_repos/permissive/155713836/tb/tb_fifo.v:23: Unsupported or unknown PLI call: $monitor\n    $monitor ("%g wr:%h wr_data:%h rd:%h rd_data:%h", \n    ^~~~~~~~\n%Error: data/full_repos/permissive/155713836/tb/tb_fifo.v:29: syntax error, unexpected \'@\'\n    @ (negedge clk);\n    ^\n%Error: data/full_repos/permissive/155713836/tb/tb_fifo.v:34: syntax error, unexpected \'@\'\n      @ (negedge clk);\n      ^\n%Error: data/full_repos/permissive/155713836/tb/tb_fifo.v:37: syntax error, unexpected \'@\'\n    @ (negedge clk);\n    ^\n%Error: data/full_repos/permissive/155713836/tb/tb_fifo.v:41: syntax error, unexpected \'@\'\n      @ (negedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/155713836/tb/tb_fifo.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/155713836/tb/tb_fifo.v:48: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = !clk;\n         ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_fifo ();


  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;

  reg clk, rd_en, wr_en;
  reg [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] data_in ;
  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] data_out ;
  wire empty, full;
  integer i;

  initial begin
    $monitor ("%g wr:%h wr_data:%h rd:%h rd_data:%h", 
    $time, wr_en, data_in,  rd_en, data_out);
    clk = 0;
    rd_en = 0;
    wr_en = 0;
    data_in = 0;
    @ (negedge clk);
    wr_en = 1;

    for (i = 0 ; i < 70; i = i + 1) begin
      data_in  = i;
      @ (negedge clk);
    end
    wr_en  = 0;
    @ (negedge clk);
    rd_en = 1;

    for (i = 0 ; i < 70; i = i + 1) begin
      @ (negedge clk);
    end
    rd_en = 0;
    #100 $finish;
  end  


  always #1 clk = !clk;


  fifo strawfifo(
    .clk(clk),

    .i_read_packet_en(rd_en),
    .i_write_packet_en(wr_en),
    .i_write_packet(data_in),

    .o_read_packet(data_out),
    .o_empty_flag(empty),
    .o_full_flag(full)
  );   


  endmodule
module tb_fifo ();



  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;

  reg clk, rd_en, wr_en;
  reg [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] data_in ;
  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] data_out ;
  wire empty, full;
  integer i;

  initial begin
    $monitor ("%g wr:%h wr_data:%h rd:%h rd_data:%h", 
    $time, wr_en, data_in,  rd_en, data_out);
    clk = 0;
    rd_en = 0;
    wr_en = 0;
    data_in = 0;
    @ (negedge clk);
    wr_en = 1;

    for (i = 0 ; i < 70; i = i + 1) begin
      data_in  = i;
      @ (negedge clk);
    end
    wr_en  = 0;
    @ (negedge clk);
    rd_en = 1;

    for (i = 0 ; i < 70; i = i + 1) begin
      @ (negedge clk);
    end
    rd_en = 0;
    #100 $finish;
  end  


  always #1 clk = !clk;


  fifo strawfifo(
    .clk(clk),

    .i_read_packet_en(rd_en),
    .i_write_packet_en(wr_en),
    .i_write_packet(data_in),

    .o_read_packet(data_out),
    .o_empty_flag(empty),
    .o_full_flag(full)
  );   


  endmodule