data/full_repos/permissive/177233467/reg_file.v
data/verilator_xmls/ba319ed2-ea2f-4b54-ad04-1e3bf498c1a2.xml
module reg_file(
    input wire clk, resetn,
    input wire [reg_addr_width - 1:0] rf_rs1, rf_rs2,
    input wire [reg_width - 1: 0] rf_wd,
    input wire [reg_addr_width - 1:0] rf_ws,
    input wire rf_we,
    input wire [reg_width - 1: 0] pc,
    output reg [reg_width - 1:0] rf_d1, rf_d2
);
parameter nreg = 16;
parameter reg_width = 32;
parameter reg_addr_width = 4;

reg [reg_width - 1:0] rf[0:nreg - 1];

  always @(posedge clk) begin


    rf_d1 <= rf[rf_rs1];
    rf_d2 <= rf[rf_rs2];

    if (resetn && rf_we && (rf_ws != 15))
      rf[rf_ws] <= rf_wd;
  end

endmodule
module reg_file(
    input wire clk, resetn,
    input wire [reg_addr_width - 1:0] rf_rs1, rf_rs2,
    input wire [reg_width - 1: 0] rf_wd,
    input wire [reg_addr_width - 1:0] rf_ws,
    input wire rf_we,
    input wire [reg_width - 1: 0] pc,
    output reg [reg_width - 1:0] rf_d1, rf_d2
);

parameter nreg = 16;
parameter reg_width = 32;
parameter reg_addr_width = 4;

reg [reg_width - 1:0] rf[0:nreg - 1];

  always @(posedge clk) begin


    rf_d1 <= rf[rf_rs1];
    rf_d2 <= rf[rf_rs2];

    if (resetn && rf_we && (rf_ws != 15))
      rf[rf_ws] <= rf_wd;
  end

endmodule