data/full_repos/permissive/163494071/led/led.v
1: b'%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:37: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                 : ... In instance led\n  r_buf <= 255 - wheel_pos;\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:39: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'wheel_pos\' generates 16 bits.\n                                                                 : ... In instance led\n  b_buf <= wheel_pos;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:44: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                 : ... In instance led\n  g_buf <= (wheel_pos - 255);\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:45: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                 : ... In instance led\n  b_buf <= 255 - (wheel_pos - 255);\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:49: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                 : ... In instance led\n  r_buf <= (wheel_pos - 510);\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/163494071/led/led.v:50: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                 : ... In instance led\n  g_buf <= 255 - (wheel_pos - 510);\n        ^~\n%Error: Exiting due to 6 warning(s)\n'
module pwm(out, duty, clk);
output reg out;
input [7:0] duty;
input clk;
reg [7:0] buffer;

always@(posedge clk)
begin
	buffer <= buffer + 1;
	if(buffer < duty)
	begin
		out <= 0;
	end
	else
	begin
		out <= 1;
	end
end
endmodule
module pwm(out, duty, clk);

output reg out;
input [7:0] duty;
input clk;
reg [7:0] buffer;

always@(posedge clk)
begin
	buffer <= buffer + 1;
	if(buffer < duty)
	begin
		out <= 0;
	end
	else
	begin
		out <= 1;
	end
end
endmodule