data/full_repos/permissive/20662519/Servo_Rom.v
1: b'%Warning-WIDTH: data/full_repos/permissive/20662519/Servo_Rom.v:13: Operator COND expects 13 bits on the Conditional False, but Conditional False\'s CONST \'8\'h0\' generates 8 bits.\n                                                                  : ... In instance Servo_Rom\n  data <= (address<=255||address>=0)? mem[address] : 8\'b0;\n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-UNSIGNED: data/full_repos/permissive/20662519/Servo_Rom.v:13: Comparison is constant due to unsigned arithmetic\n                                                                     : ... In instance Servo_Rom\n  data <= (address<=255||address>=0)? mem[address] : 8\'b0;\n                                ^~\n%Error: Exiting due to 2 warning(s)\n'
module Servo_Rom #(
  parameter ADDR_LEN = 8,
  parameter DATA_LEN = 13
)(
  input clock               ,
  input [ADDR_LEN-1:0] address       ,
  output reg [DATA_LEN-1:0] data
);
      
reg [13-1:0] mem [0:255] ;  

always@(posedge clock)begin
  data <= (address<=255||address>=0)? mem[address] : 8'b0;
end

initial begin
  $readmemb("Servo_Test_Values_50DUT.hex", mem);
end

endmodule
module Servo_Rom #(
  parameter ADDR_LEN = 8,
  parameter DATA_LEN = 13
)(
  input clock               ,
  input [ADDR_LEN-1:0] address       ,
  output reg [DATA_LEN-1:0] data
);

      
reg [13-1:0] mem [0:255] ;  

always@(posedge clock)begin
  data <= (address<=255||address>=0)? mem[address] : 8'b0;
end

initial begin
  $readmemb("Servo_Test_Values_50DUT.hex", mem);
end

endmodule