data/full_repos/permissive/201488448/2_circuits/1_combinational/34_sop_pos.v
data/verilator_xmls/2d95712d-16f7-4e2e-9e3c-55092163f399.xml
module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
); 

    assign	out_sop = c&d | (~a)&(~b)&c;
    assign	out_pos = c&((~a)|(~c)|d)&(a|(~b)|(~c)|d);
    
endmodule
module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
);
 

    assign	out_sop = c&d | (~a)&(~b)&c;
    assign	out_pos = c&((~a)|(~c)|d)&(a|(~b)|(~c)|d);
    
endmodule