data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_writer_eof.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_writer_eof.sv:74: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module dma_writer_eof #(
  parameter DataBits      = 64,
  parameter AddrBits      = 32,
  parameter BurstSize     = 16,
  parameter FifoDepth     = 32)
(
  input                       clk,
  input                       rst,

  input                       din_valid,
  output                      din_ready,
  input [DataBits-1:0]        din_data,
  input                       din_eof,

  input                       cfg_valid,
  output                      cfg_ready,
  input [AddrBits-1:0]        cfg_addr,

  output logic                mst_awvalid,
  input                       mst_awready,
  output [3:0]                mst_awid,
  output logic [AddrBits-1:0] mst_awaddr,
  output logic [3:0]          mst_awlen,
  output [2:0]                mst_awsize,
  output [1:0]                mst_awburst,
  output [1:0]                mst_awlock,

  output                      mst_wvalid,
  input                       mst_wready,
  output [3:0]                mst_wid,
  output [DataBits/8-1:0]     mst_wstrb,
  output                      mst_wlast,
  output [DataBits-1:0]       mst_wdata,

  input                       mst_bvalid,
  output                      mst_bready,
  input [3:0]                 mst_bid,
  input [1:0]                 mst_bresp,

  output logic                done,
  output logic [1:0]          error);

`include "util.vh"

  localparam BurstBits = $clog2(BurstSize + 1);
  localparam BytesPerWord = DataBits / 8;





  logic [1:0] split_valid, split_ready;
  stream_split split (
    .in_valid  (din_valid),
    .in_ready  (din_ready),
    .out_valid (split_valid),
    .out_ready (split_ready));






  logic                           fifo_valid, fifo_ready, fifo_eof;
  logic [DataBits-1:0]            fifo_data;
  logic [$clog2(FifoDepth+1)-1:0] fifo_used;

  stream_fifo_1clk #(
    .Width (DataBits + 1),
    .Depth (FifoDepth))
  fifo (
    .clk        (clk),
    .rst        (rst),

    .din_valid  (split_valid[0]),
    .din_ready  (split_ready[0]),
    .din_data   ({din_eof, din_data}),

    .dout_valid (fifo_valid),
    .dout_ready (fifo_ready),
    .dout_data  ({fifo_eof, fifo_data}),
    .used       (fifo_used));








  logic eof_valid, eof_ready;
  stream_buf_v #(
    .DataBits (1))
  lbuf (
    .clk       (clk),
    .rst       (rst),
    .in_valid  (split_valid[1] & din_eof),
    .in_ready  (split_ready[1]),
    .in_data   (1'b0),
    .out_valid (eof_valid),
    .out_ready (eof_ready),
    .out_data  ( ));




  logic                 mst_wvalid_i, mst_wready_i, mst_wlast_i;
  logic [DataBits-1:0]  mst_wdata_i;
  logic [BurstBits-1:0] burst_remain;
  logic [AddrBits-1:0]  next_addr;
  logic [9:0]           until_4k;
  logic                 final_burst;

  enum {Idle, PrepBurst1, PrepBurst2, WaitFifo,
        IssueBurst, DoBurst, WaitFinal} state;

  always_ff @(posedge clk) begin


    eof_ready <= '0;
    done      <= '0;


    if (mst_awready) begin
      mst_awvalid <= '0;
    end

    case (state)

      Idle:
        if (cfg_valid) begin
          next_addr   <= cfg_addr;
          final_burst <= '0;
          state       <= PrepBurst1;
        end

      PrepBurst1:
        begin

          until_4k <= (13'h1000 - next_addr[11:0]) / BytesPerWord;
          state    <= PrepBurst2;
        end

      PrepBurst2:
        begin
          burst_remain <= min(BurstSize, until_4k);
          state        <= WaitFifo;
        end

      WaitFifo:
        begin



          if (eof_valid && (fifo_used <= burst_remain)) begin
            eof_ready    <= '1;
            final_burst  <= '1;
            burst_remain <= fifo_used;
            state        <= IssueBurst;
          end else if (fifo_used >= burst_remain) begin
            state <= IssueBurst;
          end
        end

      IssueBurst:
        if (!mst_awvalid || mst_awready) begin
          mst_awvalid <= '1;
          mst_awlen   <= burst_remain - 1;
          mst_awaddr  <= next_addr;
          next_addr   <= next_addr + (burst_remain * BytesPerWord);
          state       <= DoBurst;
        end

      DoBurst:
        if (mst_wready_i && mst_wvalid_i) begin
          burst_remain <= burst_remain - 1;
          if (burst_remain == 1)
            state <= (final_burst) ? WaitFinal : PrepBurst1;
        end

      WaitFinal:

        if (!mst_wvalid) begin
          done  <= '1;
          state <= Idle;
        end
    endcase


    if (mst_bvalid && mst_bready) begin
      error <= mst_bresp;
    end

    if (rst) begin
      state        <= Idle;
      mst_awvalid  <= '0;
      done         <= '0;
      error        <= '0;
      eof_ready    <= '0;
    end
  end

  assign cfg_ready = (state == Idle);


  assign mst_wvalid_i  = (state == DoBurst) ? fifo_valid   : 0;
  assign fifo_ready    = (state == DoBurst) ? mst_wready_i : 0;
  assign mst_wdata_i   = fifo_data;
  assign mst_wlast_i   = (burst_remain == 1) ? 1 : 0;


  stream_buf_v #(
    .DataBits(DataBits+1))
  obuf (
    .clk       (clk),
    .rst       (rst),
    .in_valid  (mst_wvalid_i),
    .in_ready  (mst_wready_i),
    .in_data   ({mst_wlast_i, mst_wdata_i}),
    .out_valid (mst_wvalid),
    .out_ready (mst_wready),
    .out_data  ({mst_wlast, mst_wdata}));


  assign mst_bready = 1'b1;


  assign mst_awid    = 4'b0;
  assign mst_awsize  = clog2(BytesPerWord);
  assign mst_awlock  = 2'b00;
  assign mst_awburst = 2'b01;
  assign mst_wid     = 4'b0;
  assign mst_wstrb   = '1;

endmodule
module dma_writer_eof #(
  parameter DataBits      = 64,
  parameter AddrBits      = 32,
  parameter BurstSize     = 16,
  parameter FifoDepth     = 32)
(
  input                       clk,
  input                       rst,

  input                       din_valid,
  output                      din_ready,
  input [DataBits-1:0]        din_data,
  input                       din_eof,

  input                       cfg_valid,
  output                      cfg_ready,
  input [AddrBits-1:0]        cfg_addr,

  output logic                mst_awvalid,
  input                       mst_awready,
  output [3:0]                mst_awid,
  output logic [AddrBits-1:0] mst_awaddr,
  output logic [3:0]          mst_awlen,
  output [2:0]                mst_awsize,
  output [1:0]                mst_awburst,
  output [1:0]                mst_awlock,

  output                      mst_wvalid,
  input                       mst_wready,
  output [3:0]                mst_wid,
  output [DataBits/8-1:0]     mst_wstrb,
  output                      mst_wlast,
  output [DataBits-1:0]       mst_wdata,

  input                       mst_bvalid,
  output                      mst_bready,
  input [3:0]                 mst_bid,
  input [1:0]                 mst_bresp,

  output logic                done,
  output logic [1:0]          error);


`include "util.vh"

  localparam BurstBits = $clog2(BurstSize + 1);
  localparam BytesPerWord = DataBits / 8;





  logic [1:0] split_valid, split_ready;
  stream_split split (
    .in_valid  (din_valid),
    .in_ready  (din_ready),
    .out_valid (split_valid),
    .out_ready (split_ready));






  logic                           fifo_valid, fifo_ready, fifo_eof;
  logic [DataBits-1:0]            fifo_data;
  logic [$clog2(FifoDepth+1)-1:0] fifo_used;

  stream_fifo_1clk #(
    .Width (DataBits + 1),
    .Depth (FifoDepth))
  fifo (
    .clk        (clk),
    .rst        (rst),

    .din_valid  (split_valid[0]),
    .din_ready  (split_ready[0]),
    .din_data   ({din_eof, din_data}),

    .dout_valid (fifo_valid),
    .dout_ready (fifo_ready),
    .dout_data  ({fifo_eof, fifo_data}),
    .used       (fifo_used));








  logic eof_valid, eof_ready;
  stream_buf_v #(
    .DataBits (1))
  lbuf (
    .clk       (clk),
    .rst       (rst),
    .in_valid  (split_valid[1] & din_eof),
    .in_ready  (split_ready[1]),
    .in_data   (1'b0),
    .out_valid (eof_valid),
    .out_ready (eof_ready),
    .out_data  ( ));




  logic                 mst_wvalid_i, mst_wready_i, mst_wlast_i;
  logic [DataBits-1:0]  mst_wdata_i;
  logic [BurstBits-1:0] burst_remain;
  logic [AddrBits-1:0]  next_addr;
  logic [9:0]           until_4k;
  logic                 final_burst;

  enum {Idle, PrepBurst1, PrepBurst2, WaitFifo,
        IssueBurst, DoBurst, WaitFinal} state;

  always_ff @(posedge clk) begin


    eof_ready <= '0;
    done      <= '0;


    if (mst_awready) begin
      mst_awvalid <= '0;
    end

    case (state)

      Idle:
        if (cfg_valid) begin
          next_addr   <= cfg_addr;
          final_burst <= '0;
          state       <= PrepBurst1;
        end

      PrepBurst1:
        begin

          until_4k <= (13'h1000 - next_addr[11:0]) / BytesPerWord;
          state    <= PrepBurst2;
        end

      PrepBurst2:
        begin
          burst_remain <= min(BurstSize, until_4k);
          state        <= WaitFifo;
        end

      WaitFifo:
        begin



          if (eof_valid && (fifo_used <= burst_remain)) begin
            eof_ready    <= '1;
            final_burst  <= '1;
            burst_remain <= fifo_used;
            state        <= IssueBurst;
          end else if (fifo_used >= burst_remain) begin
            state <= IssueBurst;
          end
        end

      IssueBurst:
        if (!mst_awvalid || mst_awready) begin
          mst_awvalid <= '1;
          mst_awlen   <= burst_remain - 1;
          mst_awaddr  <= next_addr;
          next_addr   <= next_addr + (burst_remain * BytesPerWord);
          state       <= DoBurst;
        end

      DoBurst:
        if (mst_wready_i && mst_wvalid_i) begin
          burst_remain <= burst_remain - 1;
          if (burst_remain == 1)
            state <= (final_burst) ? WaitFinal : PrepBurst1;
        end

      WaitFinal:

        if (!mst_wvalid) begin
          done  <= '1;
          state <= Idle;
        end
    endcase


    if (mst_bvalid && mst_bready) begin
      error <= mst_bresp;
    end

    if (rst) begin
      state        <= Idle;
      mst_awvalid  <= '0;
      done         <= '0;
      error        <= '0;
      eof_ready    <= '0;
    end
  end

  assign cfg_ready = (state == Idle);


  assign mst_wvalid_i  = (state == DoBurst) ? fifo_valid   : 0;
  assign fifo_ready    = (state == DoBurst) ? mst_wready_i : 0;
  assign mst_wdata_i   = fifo_data;
  assign mst_wlast_i   = (burst_remain == 1) ? 1 : 0;


  stream_buf_v #(
    .DataBits(DataBits+1))
  obuf (
    .clk       (clk),
    .rst       (rst),
    .in_valid  (mst_wvalid_i),
    .in_ready  (mst_wready_i),
    .in_data   ({mst_wlast_i, mst_wdata_i}),
    .out_valid (mst_wvalid),
    .out_ready (mst_wready),
    .out_data  ({mst_wlast, mst_wdata}));


  assign mst_bready = 1'b1;


  assign mst_awid    = 4'b0;
  assign mst_awsize  = clog2(BytesPerWord);
  assign mst_awlock  = 2'b00;
  assign mst_awburst = 2'b01;
  assign mst_wid     = 4'b0;
  assign mst_wstrb   = '1;

endmodule