data/full_repos/permissive/181665138/verilog/capitolo_ii/Rete_Combinatoria_3.v
1: b'%Warning-WIDTH: data/full_repos/permissive/181665138/verilog/capitolo_ii/Rete_Combinatoria_3.v:53: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0\' generates 32 bits.\n                                                                                                 : ... In instance Rete_Combinatoria_3\n            \'B010   : F=\'BX0;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181665138/verilog/capitolo_ii/Rete_Combinatoria_3.v:55: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1\' generates 32 bits.\n                                                                                                 : ... In instance Rete_Combinatoria_3\n            \'B110   : F=\'BX1;\n                       ^\n%Error: Exiting due to 2 warning(s)\n'
module Rete_Combinatoria_3(x2, x1, x0, z1, z0);
    input x2, x1, x0;
    output z1, z0;

    assign {z1, z0} = F(x2, x1, x0);

    function [1:0] F;
        input x2, x1, x0;

        casex({x2, x1, x0})
            'B001   : F='B01;
            'B011   : F='B10;
            'B010   : F='BX0;
            'B111   : F='B11;
            'B110   : F='BX1;
            default : F='B00;
        endcase
    endfunction
endmodule
module Rete_Combinatoria_3(x2, x1, x0, z1, z0);

    input x2, x1, x0;
    output z1, z0;

    assign {z1, z0} = F(x2, x1, x0);

    function [1:0] F;
        input x2, x1, x0;

        casex({x2, x1, x0})
            'B001   : F='B01;
            'B011   : F='B10;
            'B010   : F='BX0;
            'B111   : F='B11;
            'B110   : F='BX1;
            default : F='B00;
        endcase
    endfunction
endmodule