data/full_repos/permissive/167856740/seg/seg_wishbone.v
data/verilator_xmls/5930344b-5231-45af-80ac-c39017bf0d94.xml
module seg_wishbone #(parameter CLOCKFREQ=1000000000)(

	input wire CLK_I,
	input wire RST_I,
	input wire [31:0] DAT_I,
	input wire STB_I,
	input wire WE_I,
    output wire [31:0] DAT_O,
	

	output reg [6:0] O_cathode,
	output reg [7:0] O_anode
    );
    
    assign DAT_O = current_number;
    

    reg [31:0] current_number;
    

    reg [17:0] refresh_counter;
    reg [3:0] LED_BCD;
    wire [2:0] LED_activating_counter;
    


    assign LED_activating_counter = refresh_counter[17:15];
   

     initial begin
        current_number = 32'h15170144;
     end
    
     always @(posedge CLK_I) begin 
         if(RST_I==1) begin
             refresh_counter <= 0;
             O_anode <= 8'b11111111;
         end
         else begin
             refresh_counter <= refresh_counter + 1;
             
             case(LED_activating_counter)
                3'b000: begin
                            O_anode <= 8'b11111110;
                            LED_BCD <= current_number[3:0];
                end
                3'b001: begin
                            O_anode <= 8'b11111101;
                            LED_BCD <= current_number[7:4];
                        end
                3'b010: begin
                            O_anode <= 8'b11111011;
                            LED_BCD <= current_number[11:8];
                        end
                3'b011: begin
                            O_anode <= 8'b11110111;
                            LED_BCD <= current_number[15:12];
                        end
                3'b100: begin
                            O_anode <= 8'b11101111;
                            LED_BCD <= current_number[19:16];
                        end
                3'b101: begin
                            O_anode <= 8'b11011111;
                            LED_BCD <= current_number[23:20];
                        end
                3'b110: begin
                            O_anode <= 8'b10111111;
                            LED_BCD <= current_number[27:24];
                        end
                3'b111: begin
                            O_anode <= 8'b01111111;
                            LED_BCD <= current_number[31:28];
                        end
                default: begin
                            O_anode <= 8'b11111110;
                            LED_BCD <= current_number[3:0];
                         end               
             endcase
         end
     end 
    

    always @(*) begin
        case(LED_BCD)
        4'h0: O_cathode = 7'b0000001;
        4'h1: O_cathode = 7'b1001111;
        4'h2: O_cathode = 7'b0010010;
        4'h3: O_cathode = 7'b0000110;
        4'h4: O_cathode = 7'b1001100;
        4'h5: O_cathode = 7'b0100100;
        4'h6: O_cathode = 7'b0100000;
        4'h7: O_cathode = 7'b0001111;
        4'h8: O_cathode = 7'b0000000;
        4'h9: O_cathode = 7'b0000100;
        4'hA: O_cathode = 7'b0001000;
        4'hB: O_cathode = 7'b1100000;
        4'hC: O_cathode = 7'b0110001;
        4'hD: O_cathode = 7'b1000010;
        4'hE: O_cathode = 7'b0110000;
        4'hF: O_cathode = 7'b0111000;
        default: O_cathode = 7'b0000001;
        endcase
    end
    

    always @ (posedge CLK_I) begin
        if (STB_I) begin
            if (WE_I) begin
                current_number <= DAT_I[31:0];
            end
        end
    end
endmodule
module seg_wishbone #(parameter CLOCKFREQ=1000000000)(

	input wire CLK_I,
	input wire RST_I,
	input wire [31:0] DAT_I,
	input wire STB_I,
	input wire WE_I,
    output wire [31:0] DAT_O,
	

	output reg [6:0] O_cathode,
	output reg [7:0] O_anode
    );

    
    assign DAT_O = current_number;
    

    reg [31:0] current_number;
    

    reg [17:0] refresh_counter;
    reg [3:0] LED_BCD;
    wire [2:0] LED_activating_counter;
    


    assign LED_activating_counter = refresh_counter[17:15];
   

     initial begin
        current_number = 32'h15170144;
     end
    
     always @(posedge CLK_I) begin 
         if(RST_I==1) begin
             refresh_counter <= 0;
             O_anode <= 8'b11111111;
         end
         else begin
             refresh_counter <= refresh_counter + 1;
             
             case(LED_activating_counter)
                3'b000: begin
                            O_anode <= 8'b11111110;
                            LED_BCD <= current_number[3:0];
                end
                3'b001: begin
                            O_anode <= 8'b11111101;
                            LED_BCD <= current_number[7:4];
                        end
                3'b010: begin
                            O_anode <= 8'b11111011;
                            LED_BCD <= current_number[11:8];
                        end
                3'b011: begin
                            O_anode <= 8'b11110111;
                            LED_BCD <= current_number[15:12];
                        end
                3'b100: begin
                            O_anode <= 8'b11101111;
                            LED_BCD <= current_number[19:16];
                        end
                3'b101: begin
                            O_anode <= 8'b11011111;
                            LED_BCD <= current_number[23:20];
                        end
                3'b110: begin
                            O_anode <= 8'b10111111;
                            LED_BCD <= current_number[27:24];
                        end
                3'b111: begin
                            O_anode <= 8'b01111111;
                            LED_BCD <= current_number[31:28];
                        end
                default: begin
                            O_anode <= 8'b11111110;
                            LED_BCD <= current_number[3:0];
                         end               
             endcase
         end
     end 
    

    always @(*) begin
        case(LED_BCD)
        4'h0: O_cathode = 7'b0000001;
        4'h1: O_cathode = 7'b1001111;
        4'h2: O_cathode = 7'b0010010;
        4'h3: O_cathode = 7'b0000110;
        4'h4: O_cathode = 7'b1001100;
        4'h5: O_cathode = 7'b0100100;
        4'h6: O_cathode = 7'b0100000;
        4'h7: O_cathode = 7'b0001111;
        4'h8: O_cathode = 7'b0000000;
        4'h9: O_cathode = 7'b0000100;
        4'hA: O_cathode = 7'b0001000;
        4'hB: O_cathode = 7'b1100000;
        4'hC: O_cathode = 7'b0110001;
        4'hD: O_cathode = 7'b1000010;
        4'hE: O_cathode = 7'b0110000;
        4'hF: O_cathode = 7'b0111000;
        default: O_cathode = 7'b0000001;
        endcase
    end
    

    always @ (posedge CLK_I) begin
        if (STB_I) begin
            if (WE_I) begin
                current_number <= DAT_I[31:0];
            end
        end
    end
endmodule