data/full_repos/permissive/119715647/sim/Timer/LFSRTimer_1ms_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/LFSRTimer_1ms_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/LFSRTimer_1ms_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/LFSRTimer_1ms_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/LFSRTimer_1ms_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #40;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/LFSRTimer_1ms_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #40;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/LFSRTimer_1ms_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #40;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/LFSRTimer_1ms_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #40;\n    ^\n%Error: data/full_repos/permissive/119715647/sim/Timer/LFSRTimer_1ms_tb.v:8: Cannot find file containing module: \'LFSRTimer_1ms\'\n  LFSRTimer_1ms DUT_LFSRTimer_1ms(clk, rst, enable, pulseOut);\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119715647/sim/Timer,data/full_repos/permissive/119715647/LFSRTimer_1ms\n             data/full_repos/permissive/119715647/sim/Timer,data/full_repos/permissive/119715647/LFSRTimer_1ms.v\n             data/full_repos/permissive/119715647/sim/Timer,data/full_repos/permissive/119715647/LFSRTimer_1ms.sv\n             LFSRTimer_1ms\n             LFSRTimer_1ms.v\n             LFSRTimer_1ms.sv\n             obj_dir/LFSRTimer_1ms\n             obj_dir/LFSRTimer_1ms.v\n             obj_dir/LFSRTimer_1ms.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LFSRTimer_1ms_tb();

  reg clk, rst, enable;
  wire pulseOut;

  LFSRTimer_1ms DUT_LFSRTimer_1ms(clk, rst, enable, pulseOut);

  always begin
    clk = 1;
    #10;
    clk = 0;
    #10;
  end

  initial begin
    #5;
    #40;
    rst = 0;
    enable = 0;
    #40;
    rst = 1;
    #40;
    enable = 1;
    #40;
  end
endmodule
module LFSRTimer_1ms_tb();


  reg clk, rst, enable;
  wire pulseOut;

  LFSRTimer_1ms DUT_LFSRTimer_1ms(clk, rst, enable, pulseOut);

  always begin
    clk = 1;
    #10;
    clk = 0;
    #10;
  end

  initial begin
    #5;
    #40;
    rst = 0;
    enable = 0;
    #40;
    rst = 1;
    #40;
    enable = 1;
    #40;
  end
endmodule