data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:11: Cannot find include file: sim_exec_report.vh\n`include "sim_exec_report.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line,data/full_repos/permissive/214858095/sim_exec_report.vh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line,data/full_repos/permissive/214858095/sim_exec_report.vh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line,data/full_repos/permissive/214858095/sim_exec_report.vh.sv\n             sim_exec_report.vh\n             sim_exec_report.vh.v\n             sim_exec_report.vh.sv\n             obj_dir/sim_exec_report.vh\n             obj_dir/sim_exec_report.vh.v\n             obj_dir/sim_exec_report.vh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:12: Cannot find include file: sim_clks_rsts.vh\n`include "sim_clks_rsts.vh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:13: Cannot find include file: sim_axis_lib.svh\n`include "sim_axis_lib.svh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:16: Define or directive not defined: \'`TEST_BENCH_INIT\'\n  `TEST_BENCH_INIT("variable_delay_line_tb", 4, 1);\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:16: syntax error, unexpected \'(\'\n  `TEST_BENCH_INIT("variable_delay_line_tb", 4, 1);\n                   ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:18: Define or directive not defined: \'`DEFINE_CLK\'\n  `DEFINE_CLK(clk, CLK_PERIOD, 50);\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:18: syntax error, unexpected \'(\'\n  `DEFINE_CLK(clk, CLK_PERIOD, 50);\n              ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:19: Define or directive not defined: \'`DEFINE_RESET\'\n  `DEFINE_RESET(reset, 0, 100);\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:37: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:45: syntax error, unexpected \'@\'\n      @(posedge clk);                \n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:46: syntax error, unexpected \'@\'\n      if (inst/(NUM_INST/2) == 1) @(posedge clk);  \n                                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:67: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for Reset");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:67: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for Reset");\n                                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:72: syntax error, unexpected \'@\'\n      while (reset) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:73: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(~reset);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:73: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(~reset);\n                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:75: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Check startup state of delay line");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:75: syntax error, unexpected \';\'\n    `TEST_CASE_START("Check startup state of delay line");\n                                                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:80: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(out_samp[k] == DEFAULT, "Transient delay value incorrect");\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:80: syntax error, unexpected \',\'\n          `ASSERT_ERROR(out_samp[k] == DEFAULT, "Transient delay value incorrect");\n                                              ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:83: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:83: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:85: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Check partially filled delay line");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:85: syntax error, unexpected \';\'\n    `TEST_CASE_START("Check partially filled delay line");\n                                                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:93: Define or directive not defined: \'`ASSERT_ERROR\'\n            `ASSERT_ERROR(out_samp[k] == (j>i ? DEFAULT : i - j), s);\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:93: syntax error, unexpected \',\'\n            `ASSERT_ERROR(out_samp[k] == (j>i ? DEFAULT : i - j), s);\n                                                                ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:97: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:97: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:99: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Check steady state delay line");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:99: syntax error, unexpected \';\'\n    `TEST_CASE_START("Check steady state delay line");\n                                                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:107: Define or directive not defined: \'`ASSERT_ERROR\'\n            `ASSERT_ERROR(out_samp[k] == DELAYS[k] + i - j, s);\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:107: syntax error, unexpected \',\'\n            `ASSERT_ERROR(out_samp[k] == DELAYS[k] + i - j, s);\n                                                          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:111: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:111: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/dsp/variable_delay_line/variable_delay_line_tb.sv:114: Define or directive not defined: \'`TEST_BENCH_DONE\'\n    `TEST_BENCH_DONE;\n    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 35 error(s)\n'
module variable_delay_line_tb();
  `TEST_BENCH_INIT("variable_delay_line_tb", `NUM_TEST_CASES, `NS_PER_TICK);
  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
  `DEFINE_CLK(clk, CLK_PERIOD, 50);
  `DEFINE_RESET(reset, 0, 100);

  localparam             WIDTH                = 32;
  localparam [WIDTH-1:0] DEFAULT              = 32'hDEADBEEF;
  localparam integer     NUM_INST             = 24;
  localparam integer     DELAYS[0:NUM_INST-1] = {3, 14, 15, 16, 17, 30, 31, 32, 33, 127, 256, 511,
                                                 3, 14, 15, 16, 17, 30, 31, 32, 33, 127, 256, 511};

  logic             in_stb   [0:NUM_INST-1];
  logic [WIDTH-1:0] in_samp  [0:NUM_INST-1];
  wire  [WIDTH-1:0] out_samp [0:NUM_INST-1];
  logic [31:0]      out_delay[0:NUM_INST-1];

  task push_samp(logic [WIDTH-1:0] word, integer inst);
    begin

      in_samp[inst] = word;
      in_stb[inst] = 1'b1;
      @(posedge clk);
      in_stb[inst] = 1'b0;
    end
  endtask

  task change_delay(logic [31:0] delay, integer inst);
    begin
      out_delay[inst] = delay;
      @(posedge clk);
      if (inst/(NUM_INST/2) == 1) @(posedge clk);
      @(negedge clk);

    end
  endtask

  genvar d;
  generate for (d = 0; d < NUM_INST; d=d+1) begin: inst
    variable_delay_line #(
      .WIDTH(WIDTH), .DEPTH(DELAYS[d]),
      .DYNAMIC_DELAY(1), .DEFAULT_DATA(DEFAULT), .OUT_REG(d / (NUM_INST/2))
    ) dut (
      .clk(clk), .clk_en(1'b1), .reset(reset),
      .data_in(in_samp[d]), .stb_in(in_stb[d]),
      .delay(out_delay[d]), .data_out(out_samp[d])
    );
  end endgenerate

  initial begin : tb_main
    string s;

    `TEST_CASE_START("Wait for Reset");
      for (int k = 0; k < NUM_INST; k=k+1) begin
        in_stb[k]    = 1'b0;
        out_delay[k] = 0;
      end
      while (reset) @(posedge clk);
    `TEST_CASE_DONE(~reset);

    `TEST_CASE_START("Check startup state of delay line");
      for (int k = 0; k < NUM_INST; k=k+1) begin
        $display("Validating delay line with DEPTH=%0d, OUT_REG=%0d...", DELAYS[k], k/(NUM_INST/2));
        for (int j = 0; j < DELAYS[k]; j=j+1) begin
          change_delay(j, k);
          `ASSERT_ERROR(out_samp[k] == DEFAULT, "Transient delay value incorrect");
        end
      end
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Check partially filled delay line");
      for (int k = 0; k < NUM_INST; k=k+1) begin
        $display("Validating delay line with DEPTH=%0d, OUT_REG=%0d...", DELAYS[k], k/(NUM_INST/2));
        for (int i = 0; i < DELAYS[k]; i=i+1) begin
          push_samp(i, k);
          for (int j = 0; j < DELAYS[k]; j=j+1) begin
            change_delay(j, k);
            $sformat(s, "Incorrect data. Samp = %0d, Delay = %0d, Data = %08x", i, j, out_samp[k]);
            `ASSERT_ERROR(out_samp[k] == (j>i ? DEFAULT : i - j), s);
          end
        end
      end
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Check steady state delay line");
      for (int k = 0; k < NUM_INST; k=k+1) begin
        $display("Validating delay line with DEPTH=%0d, OUT_REG=%0d...", DELAYS[k], k/(NUM_INST/2));
        for (int i = 0; i < DELAYS[k]; i=i+1) begin
          push_samp(i + DELAYS[k], k);
          for (int j = 0; j < DELAYS[k]; j=j+1) begin
            change_delay(j, k);
            $sformat(s, "Incorrect data. Samp = %0d, Delay = %0d, Data = %08x", i, j, out_samp[k]);
            `ASSERT_ERROR(out_samp[k] == DELAYS[k] + i - j, s);
          end
        end
      end
    `TEST_CASE_DONE(1);


    `TEST_BENCH_DONE;

  end
endmodule
module variable_delay_line_tb();

  `TEST_BENCH_INIT("variable_delay_line_tb", `NUM_TEST_CASES, `NS_PER_TICK);
  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
  `DEFINE_CLK(clk, CLK_PERIOD, 50);
  `DEFINE_RESET(reset, 0, 100);

  localparam             WIDTH                = 32;
  localparam [WIDTH-1:0] DEFAULT              = 32'hDEADBEEF;
  localparam integer     NUM_INST             = 24;
  localparam integer     DELAYS[0:NUM_INST-1] = {3, 14, 15, 16, 17, 30, 31, 32, 33, 127, 256, 511,
                                                 3, 14, 15, 16, 17, 30, 31, 32, 33, 127, 256, 511};

  logic             in_stb   [0:NUM_INST-1];
  logic [WIDTH-1:0] in_samp  [0:NUM_INST-1];
  wire  [WIDTH-1:0] out_samp [0:NUM_INST-1];
  logic [31:0]      out_delay[0:NUM_INST-1];

  task push_samp(logic [WIDTH-1:0] word, integer inst);
    begin

      in_samp[inst] = word;
      in_stb[inst] = 1'b1;
      @(posedge clk);
      in_stb[inst] = 1'b0;
    end
  endtask

  task change_delay(logic [31:0] delay, integer inst);
    begin
      out_delay[inst] = delay;
      @(posedge clk);
      if (inst/(NUM_INST/2) == 1) @(posedge clk);
      @(negedge clk);

    end
  endtask

  genvar d;
  generate for (d = 0; d < NUM_INST; d=d+1) begin: inst
    variable_delay_line #(
      .WIDTH(WIDTH), .DEPTH(DELAYS[d]),
      .DYNAMIC_DELAY(1), .DEFAULT_DATA(DEFAULT), .OUT_REG(d / (NUM_INST/2))
    ) dut (
      .clk(clk), .clk_en(1'b1), .reset(reset),
      .data_in(in_samp[d]), .stb_in(in_stb[d]),
      .delay(out_delay[d]), .data_out(out_samp[d])
    );
  end endgenerate

  initial begin : tb_main
    string s;

    `TEST_CASE_START("Wait for Reset");
      for (int k = 0; k < NUM_INST; k=k+1) begin
        in_stb[k]    = 1'b0;
        out_delay[k] = 0;
      end
      while (reset) @(posedge clk);
    `TEST_CASE_DONE(~reset);

    `TEST_CASE_START("Check startup state of delay line");
      for (int k = 0; k < NUM_INST; k=k+1) begin
        $display("Validating delay line with DEPTH=%0d, OUT_REG=%0d...", DELAYS[k], k/(NUM_INST/2));
        for (int j = 0; j < DELAYS[k]; j=j+1) begin
          change_delay(j, k);
          `ASSERT_ERROR(out_samp[k] == DEFAULT, "Transient delay value incorrect");
        end
      end
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Check partially filled delay line");
      for (int k = 0; k < NUM_INST; k=k+1) begin
        $display("Validating delay line with DEPTH=%0d, OUT_REG=%0d...", DELAYS[k], k/(NUM_INST/2));
        for (int i = 0; i < DELAYS[k]; i=i+1) begin
          push_samp(i, k);
          for (int j = 0; j < DELAYS[k]; j=j+1) begin
            change_delay(j, k);
            $sformat(s, "Incorrect data. Samp = %0d, Delay = %0d, Data = %08x", i, j, out_samp[k]);
            `ASSERT_ERROR(out_samp[k] == (j>i ? DEFAULT : i - j), s);
          end
        end
      end
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Check steady state delay line");
      for (int k = 0; k < NUM_INST; k=k+1) begin
        $display("Validating delay line with DEPTH=%0d, OUT_REG=%0d...", DELAYS[k], k/(NUM_INST/2));
        for (int i = 0; i < DELAYS[k]; i=i+1) begin
          push_samp(i + DELAYS[k], k);
          for (int j = 0; j < DELAYS[k]; j=j+1) begin
            change_delay(j, k);
            $sformat(s, "Incorrect data. Samp = %0d, Delay = %0d, Data = %08x", i, j, out_samp[k]);
            `ASSERT_ERROR(out_samp[k] == DELAYS[k] + i - j, s);
          end
        end
      end
    `TEST_CASE_DONE(1);


    `TEST_BENCH_DONE;

  end
endmodule