data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_timer.v
1: b'%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_timer.v:22: Cannot find include file: urv_defs.v\n`include "urv_defs.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v.sv\n             urv_defs.v\n             urv_defs.v.v\n             urv_defs.v.sv\n             obj_dir/urv_defs.v\n             obj_dir/urv_defs.v.v\n             obj_dir/urv_defs.v.sv\n%Error: Exiting due to 1 error(s)\n'
module urv_timer
  (
   input 	 clk_i,
   input 	 rst_i,

   output [39:0] csr_time_o,
   output [39:0] csr_cycles_o,
  
   output 	 sys_tick_o
   );

   parameter g_timer_frequency = 1000;
   parameter g_clock_frequency = 62500000;

   localparam g_prescaler = (g_clock_frequency / g_timer_frequency ) - 1;
   
   reg [23:0] 	 presc;
   reg 		 presc_tick;
   
   reg [39:0] 	 cycles;
   reg [39:0] 	 ticks;
   
   always@(posedge clk_i)
     if(rst_i)
       begin
	  presc <= 0;
	  presc_tick <= 0;
       end else begin
	  if(presc == g_prescaler) begin
	     presc <= 0;
	     presc_tick <= 1;
	  end else begin
	     presc_tick <= 0;
	     presc <= presc + 1;
	  end
       end

   always @(posedge clk_i)
     if (rst_i)
       ticks <= 0;
     else if (presc_tick)
       ticks <= ticks + 1;
   
   always @(posedge clk_i)
     if (rst_i)
       cycles <= 0;
     else
       cycles <= cycles + 1;
   
   
   assign csr_time_o = ticks;
   assign csr_cycles_o = cycles;
   assign sys_tick_o = presc_tick;
   
endmodule
module urv_timer
  (
   input 	 clk_i,
   input 	 rst_i,

   output [39:0] csr_time_o,
   output [39:0] csr_cycles_o,
  
   output 	 sys_tick_o
   );


   parameter g_timer_frequency = 1000;
   parameter g_clock_frequency = 62500000;

   localparam g_prescaler = (g_clock_frequency / g_timer_frequency ) - 1;
   
   reg [23:0] 	 presc;
   reg 		 presc_tick;
   
   reg [39:0] 	 cycles;
   reg [39:0] 	 ticks;
   
   always@(posedge clk_i)
     if(rst_i)
       begin
	  presc <= 0;
	  presc_tick <= 0;
       end else begin
	  if(presc == g_prescaler) begin
	     presc <= 0;
	     presc_tick <= 1;
	  end else begin
	     presc_tick <= 0;
	     presc <= presc + 1;
	  end
       end

   always @(posedge clk_i)
     if (rst_i)
       ticks <= 0;
     else if (presc_tick)
       ticks <= ticks + 1;
   
   always @(posedge clk_i)
     if (rst_i)
       cycles <= 0;
     else
       cycles <= cycles + 1;
   
   
   assign csr_time_o = ticks;
   assign csr_cycles_o = cycles;
   assign sys_tick_o = presc_tick;
   
endmodule