data/full_repos/permissive/211891954/Finite States Machine/Maquina de Moore/Exemplo 4/moore.v
 line:17: before: "rst"
1: b'%Error: Cannot find file containing module: States\n        ... Looked in:\n             data/full_repos/permissive/211891954/Finite/States\n             data/full_repos/permissive/211891954/Finite/States.v\n             data/full_repos/permissive/211891954/Finite/States.sv\n             States\n             States.v\n             States.sv\n             obj_dir/States\n             obj_dir/States.v\n             obj_dir/States.sv\n%Error: Cannot find file containing module: Machine/Maquina\n%Error: Cannot find file containing module: de\n%Error: Cannot find file containing module: Moore/Exemplo\n%Error: Cannot find file containing module: 4,data/full_repos/permissive/211891954\n%Error: Cannot find file containing module: data/full_repos/permissive/211891954/Finite\n%Error: Cannot find file containing module: 4/moore.v\n%Error: Exiting due to 7 error(s)\n'
module par(clk,rst,in,out);
    input wire clk,rst,in;
    output reg out;
    reg count = 0;

    parameter  S0 = 3'b000,
               S1 = 3'b001,
               S2 = 3'b010,
               S3 = 3'b011,
              odd = 3'b100,
             even = 3'b101,
            error = 3'b110;

    reg [2:0] states;
    reg [2:0] next_state;

    always @(posedge clk or rst or in) begin
        if(rst)begin
            states = S0;
        end 
        else begin
            case (states)
                S0:begin
                    if(in == 1'b0)begin
                         count = count + 1'b1;
                         next_state = odd;
                    end
                    else
                        next_state = S1;
                end 
                
                S1:begin
                    if(in == 1'b0) begin
                         count = count + 1'b1;
                         next_state = odd;
                    end
                    else
                        next_state = error;
                end
            
                S2:begin
                    if(in == 1'b0)begin
                        count = count + 1'b1;
                        next_state = even ;
                    end
                    else
                        next_state = error;
                end

                S3:begin
                    if(in == 1'b0)begin
                        count = count + 1'b1;
                        next_state = odd;
                    end
                    else 
                        next_state = error;
                end

                odd:begin
                    if(in == 1'b0)begin
                        count = count + 1'b1;
                        next_state = even ;
                    end 
                    else
                        next_state = S2;   
                end

                even:begin
                    next_state = S3;    
                end

                error:begin
                    next_state = error;
                end    
            endcase
        end
    end

    always@(states)begin
        out = count;
    end
endmodule
module par(clk,rst,in,out);

    input wire clk,rst,in;
    output reg out;
    reg count = 0;

    parameter  S0 = 3'b000,
               S1 = 3'b001,
               S2 = 3'b010,
               S3 = 3'b011,
              odd = 3'b100,
             even = 3'b101,
            error = 3'b110;

    reg [2:0] states;
    reg [2:0] next_state;

    always @(posedge clk or rst or in) begin
        if(rst)begin
            states = S0;
        end 
        else begin
            case (states)
                S0:begin
                    if(in == 1'b0)begin
                         count = count + 1'b1;
                         next_state = odd;
                    end
                    else
                        next_state = S1;
                end 
                
                S1:begin
                    if(in == 1'b0) begin
                         count = count + 1'b1;
                         next_state = odd;
                    end
                    else
                        next_state = error;
                end
            
                S2:begin
                    if(in == 1'b0)begin
                        count = count + 1'b1;
                        next_state = even ;
                    end
                    else
                        next_state = error;
                end

                S3:begin
                    if(in == 1'b0)begin
                        count = count + 1'b1;
                        next_state = odd;
                    end
                    else 
                        next_state = error;
                end

                odd:begin
                    if(in == 1'b0)begin
                        count = count + 1'b1;
                        next_state = even ;
                    end 
                    else
                        next_state = S2;   
                end

                even:begin
                    next_state = S3;    
                end

                error:begin
                    next_state = error;
                end    
            endcase
        end
    end

    always@(states)begin
        out = count;
    end
endmodule