data/full_repos/permissive/204736068/SoM/RTL/vision/synth/source/impl_1/stream_dual_clock_fifo.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/204736068/SoM/RTL/vision/synth/source/impl_1/stream_dual_clock_fifo.v:6: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input [DW-1:0]  stream_s_data_i, \n          ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/204736068/SoM/RTL/vision/synth/source/impl_1/stream_dual_clock_fifo.v:12: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output [DW-1:0] stream_m_data_o,\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/204736068/SoM/RTL/vision/synth/source/impl_1/stream_dual_clock_fifo.v:19: Little bit endian vector: MSB < LSB of bit range: -1:0\n   wire [DW-1:0]    fifo_dout;\n        ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/synth/source/impl_1/stream_dual_clock_fifo.v:27: Cannot find file containing module: \'dual_clock_fifo\'\n   dual_clock_fifo\n   ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/204736068/SoM/RTL/vision/synth/source/impl_1,data/full_repos/permissive/204736068/dual_clock_fifo\n             data/full_repos/permissive/204736068/SoM/RTL/vision/synth/source/impl_1,data/full_repos/permissive/204736068/dual_clock_fifo.v\n             data/full_repos/permissive/204736068/SoM/RTL/vision/synth/source/impl_1,data/full_repos/permissive/204736068/dual_clock_fifo.sv\n             dual_clock_fifo\n             dual_clock_fifo.v\n             dual_clock_fifo.sv\n             obj_dir/dual_clock_fifo\n             obj_dir/dual_clock_fifo.v\n             obj_dir/dual_clock_fifo.sv\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/synth/source/impl_1/stream_dual_clock_fifo.v:43: Cannot find file containing module: \'stream_fifo_if\'\n   stream_fifo_if\n   ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module stream_dual_clock_fifo
  #(parameter DW = 0,
    parameter AW = 0)
   (input 	    wr_clk,
    input 	    wr_rst,
    input [DW-1:0]  stream_s_data_i, 
    input 	    stream_s_valid_i,
    output 	    stream_s_ready_o,

    input 	    rd_clk,
    input 	    rd_rst,
    output [DW-1:0] stream_m_data_o,
    output 	    stream_m_valid_o,
    input 	    stream_m_ready_i);
   
   

   wire 	    fifo_rd_en;
   wire [DW-1:0]    fifo_dout;
   wire 	    fifo_empty;
   wire 	    full;
   
   assign stream_s_ready_o = !(full | wr_rst);
   
	

   dual_clock_fifo
     #(.ADDR_WIDTH (AW),
       .DATA_WIDTH (DW))
   dual_clock_fifo
     (.wr_rst_i  (wr_rst),       
      .wr_clk_i  (wr_clk),
      .wr_en_i   (stream_s_valid_i & stream_s_ready_o),
      .wr_data_i (stream_s_data_i),
      .full_o    (full),

      .rd_rst_i  (rd_rst),       
      .rd_clk_i  (rd_clk),
      .rd_en_i   (fifo_rd_en),
      .rd_data_o (fifo_dout),
      .empty_o   (fifo_empty));

   stream_fifo_if
     #(.DW (DW))
   stream_if
   (.clk              (rd_clk),
    .rst              (rd_rst),
    .fifo_data_i      (fifo_dout),
    .fifo_rd_en_o     (fifo_rd_en),
    .fifo_empty_i     (fifo_empty),
    .stream_m_data_o  (stream_m_data_o),
    .stream_m_valid_o (stream_m_valid_o),
    .stream_m_ready_i (stream_m_ready_i));
   
endmodule
module stream_dual_clock_fifo
  #(parameter DW = 0,
    parameter AW = 0)
   (input 	    wr_clk,
    input 	    wr_rst,
    input [DW-1:0]  stream_s_data_i, 
    input 	    stream_s_valid_i,
    output 	    stream_s_ready_o,

    input 	    rd_clk,
    input 	    rd_rst,
    output [DW-1:0] stream_m_data_o,
    output 	    stream_m_valid_o,
    input 	    stream_m_ready_i);

   
   

   wire 	    fifo_rd_en;
   wire [DW-1:0]    fifo_dout;
   wire 	    fifo_empty;
   wire 	    full;
   
   assign stream_s_ready_o = !(full | wr_rst);
   
	

   dual_clock_fifo
     #(.ADDR_WIDTH (AW),
       .DATA_WIDTH (DW))
   dual_clock_fifo
     (.wr_rst_i  (wr_rst),       
      .wr_clk_i  (wr_clk),
      .wr_en_i   (stream_s_valid_i & stream_s_ready_o),
      .wr_data_i (stream_s_data_i),
      .full_o    (full),

      .rd_rst_i  (rd_rst),       
      .rd_clk_i  (rd_clk),
      .rd_en_i   (fifo_rd_en),
      .rd_data_o (fifo_dout),
      .empty_o   (fifo_empty));

   stream_fifo_if
     #(.DW (DW))
   stream_if
   (.clk              (rd_clk),
    .rst              (rd_rst),
    .fifo_data_i      (fifo_dout),
    .fifo_rd_en_o     (fifo_rd_en),
    .fifo_empty_i     (fifo_empty),
    .stream_m_data_o  (stream_m_data_o),
    .stream_m_valid_o (stream_m_valid_o),
    .stream_m_ready_i (stream_m_ready_i));
   
endmodule