data/full_repos/permissive/202776140/bat_amateur_tb.v
1: b"%Error: data/full_repos/permissive/202776140/bat_amateur_tb.v:14: Cannot find file containing module: 'bat_amateur'\nbat_amateur my_bat_amateur (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202776140,data/full_repos/permissive/202776140/bat_amateur\n             data/full_repos/permissive/202776140,data/full_repos/permissive/202776140/bat_amateur.v\n             data/full_repos/permissive/202776140,data/full_repos/permissive/202776140/bat_amateur.sv\n             bat_amateur\n             bat_amateur.v\n             bat_amateur.sv\n             obj_dir/bat_amateur\n             obj_dir/bat_amateur.v\n             obj_dir/bat_amateur.sv\n%Error: data/full_repos/permissive/202776140/bat_amateur_tb.v:25: Cannot find file containing module: 'bat_amateur_stim'\nbat_amateur_stim my_bat_amateur_stim (\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module bat_amateur_tb ();
parameter ADDRESS_WIDTH = 16;

wire CLK;
wire RESET;
wire HALT;
wire RAM_RW;
wire [15:0] DATA_BUS;
wire [ADDRESS_WIDTH-1:0] ADDRESS_BUS;
wire [15:0] OUTPUT_BUS;

bat_amateur my_bat_amateur (
    .DATA(DATA_BUS),
    .ADDRESS(ADDRESS_BUS),
    .EXT_RAM_RW(RAM_RW),
    .EXT_RAM_EN(HALT),
    .HALT(HALT),
    .CLK(CLK),
    .RST(RESET),
    .OUT(OUTPUT_BUS)
);

bat_amateur_stim my_bat_amateur_stim (
    .HALT(HALT),
    .CLK(CLK),
    .RESET(RESET),
    .RAM_RW(RAM_RW),
    .RAM_EN(RAM_EN),
    .DATA_BUS(DATA_BUS),
    .ADDRESS_BUS(ADDRESS_BUS),
    .OUTPUT_BUS(OUTPUT_BUS)
);

endmodule
module bat_amateur_tb ();

parameter ADDRESS_WIDTH = 16;

wire CLK;
wire RESET;
wire HALT;
wire RAM_RW;
wire [15:0] DATA_BUS;
wire [ADDRESS_WIDTH-1:0] ADDRESS_BUS;
wire [15:0] OUTPUT_BUS;

bat_amateur my_bat_amateur (
    .DATA(DATA_BUS),
    .ADDRESS(ADDRESS_BUS),
    .EXT_RAM_RW(RAM_RW),
    .EXT_RAM_EN(HALT),
    .HALT(HALT),
    .CLK(CLK),
    .RST(RESET),
    .OUT(OUTPUT_BUS)
);

bat_amateur_stim my_bat_amateur_stim (
    .HALT(HALT),
    .CLK(CLK),
    .RESET(RESET),
    .RAM_RW(RAM_RW),
    .RAM_EN(RAM_EN),
    .DATA_BUS(DATA_BUS),
    .ADDRESS_BUS(ADDRESS_BUS),
    .OUTPUT_BUS(OUTPUT_BUS)
);

endmodule