data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:46: Unsupported: event data types\n event           start_Monitor;\n ^~~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:60: syntax error, unexpected ->\n  ->start_Monitor;               \n  ^~\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:59: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:64: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n  results_file=$fopen("../out/top_results.txt");\n               ^~~~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:73: syntax error, unexpected \'@\'\n   @(posedge clk_write);\n   ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:78: syntax error, unexpected \'@\'\n   @(posedge clk_read);\n   ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:89: Unsupported or unknown PLI call: $timeformat\n   $timeformat(-9, 0, " ns", 9);\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:90: syntax error, unexpected \'@\'\n   @(start_Monitor)\n   ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:102: syntax error, unexpected endtask\n endtask    \n ^~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:108: syntax error, unexpected \'@\'\n  @ (posedge clk_write);\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:110: syntax error, unexpected \'@\'\n  @ (posedge clk_write);\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_circular_buffer.sv:112: syntax error, unexpected \'@\'\n  @ (posedge clk_write);\n  ^\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module    test_sonic_circular_buffer (


        input   logic            clk_read,                                             
		input   logic            clk_write,
        input   logic            almost_empty,
		input   logic            almost_full,
		input   logic            empty,
        input   logic            full,


        output  logic [39:0]    data_in,
	    output  logic [127:0]     data_out,
        output  logic            read_enable,
        output  logic            reset,
        output  logic            write_enable
        );

	event           start_Monitor;

	integer		results_file;
	int cnt;


	initial
	begin

		$display("Initialize Signals");
		reset <= 0;

		$display("Wait for 100 ns");
		#100
		->start_Monitor;
		CpuReset;
		

		results_file=$fopen("../out/top_results.txt");
		$fdisplay(results_file, " test_sonic_circular_buffer testbench results");
		$fwrite(results_file, "\n");
		DisplayHeader;
		

		for (cnt = 0; cnt <= 100; cnt = cnt + 1) begin
			write_enable = 1'b1;
			data_in = cnt + 128'h123456789ABCDEFFFFFFFF0000;
			@(posedge clk_write);
		end	

		for (cnt = 0; cnt <= 100; cnt = cnt + 1) begin
			if(empty == 0) read_enable = 1'b1;
			@(posedge clk_read);
		end

		
		$fclose(results_file);
		$stop;
	end


	always 
	begin: Monitor
	  $timeformat(-9, 0, " ns", 9);
	  @(start_Monitor)
	  forever @(negedge clk_write)
	  begin

	  end
	end



	task DisplayHeader;
	  $fdisplay(results_file,"                       data_in      data_out ");
	  $fdisplay(results_file,"                 ============================");
	endtask    

	task CpuReset;
	begin
		@ (posedge clk_write);
		reset = 0;
		@ (posedge clk_write);
		reset = 1;
		@ (posedge clk_write);
		reset = 0;
		@ (posedge clk_write);

	end
	endtask

endmodule
module    test_sonic_circular_buffer (


        input   logic            clk_read,                                             
		input   logic            clk_write,
        input   logic            almost_empty,
		input   logic            almost_full,
		input   logic            empty,
        input   logic            full,


        output  logic [39:0]    data_in,
	    output  logic [127:0]     data_out,
        output  logic            read_enable,
        output  logic            reset,
        output  logic            write_enable
        );


	event           start_Monitor;

	integer		results_file;
	int cnt;


	initial
	begin

		$display("Initialize Signals");
		reset <= 0;

		$display("Wait for 100 ns");
		#100
		->start_Monitor;
		CpuReset;
		

		results_file=$fopen("../out/top_results.txt");
		$fdisplay(results_file, " test_sonic_circular_buffer testbench results");
		$fwrite(results_file, "\n");
		DisplayHeader;
		

		for (cnt = 0; cnt <= 100; cnt = cnt + 1) begin
			write_enable = 1'b1;
			data_in = cnt + 128'h123456789ABCDEFFFFFFFF0000;
			@(posedge clk_write);
		end	

		for (cnt = 0; cnt <= 100; cnt = cnt + 1) begin
			if(empty == 0) read_enable = 1'b1;
			@(posedge clk_read);
		end

		
		$fclose(results_file);
		$stop;
	end


	always 
	begin: Monitor
	  $timeformat(-9, 0, " ns", 9);
	  @(start_Monitor)
	  forever @(negedge clk_write)
	  begin

	  end
	end



	task DisplayHeader;
	  $fdisplay(results_file,"                       data_in      data_out ");
	  $fdisplay(results_file,"                 ============================");
	endtask    

	task CpuReset;
	begin
		@ (posedge clk_write);
		reset = 0;
		@ (posedge clk_write);
		reset = 1;
		@ (posedge clk_write);
		reset = 0;
		@ (posedge clk_write);

	end
	endtask

endmodule