data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:3: Cannot find include file: tb.v\n`include "tb.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/test/storage,data/full_repos/permissive/201275379/tb.v\n             data/full_repos/permissive/201275379/test/storage,data/full_repos/permissive/201275379/tb.v.v\n             data/full_repos/permissive/201275379/test/storage,data/full_repos/permissive/201275379/tb.v.sv\n             tb.v\n             tb.v.v\n             tb.v.sv\n             obj_dir/tb.v\n             obj_dir/tb.v.v\n             obj_dir/tb.v.sv\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:4: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:5: Cannot find include file: branch.v\n`include "branch.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:6: Cannot find include file: rob.v\n`include "rob.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:7: Cannot find include file: opgen.v\n`include "opgen.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:14: Define or directive not defined: \'`GEN_TICK\'\n  `GEN_TICK(clk, rst);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:14: syntax error, unexpected \'(\'\n  `GEN_TICK(clk, rst);\n            ^~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:20: Define or directive not defined: \'`ROB_ADDR_BUS\'\n  reg[`ROB_ADDR_BUS]  update_addr;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`ROB_ADDR_BUS]  update_addr;\n                   ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:23: Define or directive not defined: \'`ROB_ADDR_BUS\'\n  reg[`ROB_ADDR_BUS]  erase_from_addr;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`ROB_ADDR_BUS]  erase_from_addr;\n                   ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:24: Define or directive not defined: \'`ADDR_BUS\'\n  reg[`ADDR_BUS]      pc;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`ADDR_BUS]      pc;\n               ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:28: Define or directive not defined: \'`ROB_ADDR_BUS\'\n  wire[`ROB_ADDR_BUS] read_rob_addr_out;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`ROB_ADDR_BUS] read_rob_addr_out;\n                    ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:30: Define or directive not defined: \'`GHR_BUS\'\n  wire[`GHR_BUS]      read_pht_index_out;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`GHR_BUS]      read_pht_index_out;\n               ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:31: Define or directive not defined: \'`ADDR_BUS\'\n  wire[`ADDR_BUS]     read_inst_branch_target_out;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`ADDR_BUS]     read_inst_branch_target_out;\n                ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:36: Define or directive not defined: \'`DATA_BUS\'\n  wire[`DATA_BUS]     read_mem_offset_out;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`DATA_BUS]     read_mem_offset_out;\n                ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:39: Define or directive not defined: \'`CP0_ADDR_BUS\'\n  wire[`CP0_ADDR_BUS] read_cp0_addr_out;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`CP0_ADDR_BUS] read_cp0_addr_out;\n                    ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:40: Define or directive not defined: \'`EXC_TYPE_BUS\'\n  wire[`EXC_TYPE_BUS] read_exception_type_out;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`EXC_TYPE_BUS] read_exception_type_out;\n                    ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:41: Define or directive not defined: \'`OPGEN_BUS\'\n  wire[`OPGEN_BUS]    read_opgen_out;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`OPGEN_BUS]    read_opgen_out;\n                 ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:42: Define or directive not defined: \'`SHAMT_BUS\'\n  wire[`SHAMT_BUS]    read_shamt_out;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`SHAMT_BUS]    read_shamt_out;\n                 ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:45: Define or directive not defined: \'`DATA_BUS\'\n  wire[`DATA_BUS]     read_operand_data_1_out;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`DATA_BUS]     read_operand_data_1_out;\n                ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:46: Define or directive not defined: \'`DATA_BUS\'\n  wire[`DATA_BUS]     read_operand_data_2_out;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`DATA_BUS]     read_operand_data_2_out;\n                ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:47: Define or directive not defined: \'`ADDR_BUS\'\n  wire[`ADDR_BUS]     read_pc_out;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`ADDR_BUS]     read_pc_out;\n                ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:49: Define or directive not defined: \'`ROB_ADDR_BUS\'\n  wire[`ROB_ADDR_BUS] write_rob_addr_out;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`ROB_ADDR_BUS] write_rob_addr_out;\n                    ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:52: Define or directive not defined: \'`REG_ADDR_BUS\'\n  wire[`REG_ADDR_BUS] commit_reg_write_addr_out;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`REG_ADDR_BUS] commit_reg_write_addr_out;\n                    ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:53: Define or directive not defined: \'`DATA_BUS\'\n  wire[`DATA_BUS]     commit_reg_write_data_out;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`DATA_BUS]     commit_reg_write_data_out;\n                ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:54: Define or directive not defined: \'`EXC_TYPE_BUS\'\n  wire[`EXC_TYPE_BUS] commit_exception_type_out;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:54: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`EXC_TYPE_BUS] commit_exception_type_out;\n                    ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:56: Define or directive not defined: \'`ADDR_BUS\'\n  wire[`ADDR_BUS]     commit_pc_out;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`ADDR_BUS]     commit_pc_out;\n                ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:143: Define or directive not defined: \'`TICK\'\n      case (`TICK)\n            ^~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:143: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      case (`TICK)\n                 ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:154: syntax error, unexpected \':\'\n        1: begin\n         ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:164: syntax error, unexpected INTEGER NUMBER\n        2: begin\n        ^\n%Error: data/full_repos/permissive/201275379/test/storage/ReorderBuffer_tb.v:206: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("can_read            ", can_read);\n    ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ReorderBuffer_tb(
  input clk,
  input rst
);

  `GEN_TICK(clk, rst);


  reg                 read_en;
  reg                 write_en;
  reg                 update_en;
  reg[`ROB_ADDR_BUS]  update_addr;
  reg                 commit_en;
  reg                 erase_en;
  reg[`ROB_ADDR_BUS]  erase_from_addr;
  reg[`ADDR_BUS]      pc;


  wire                can_read;
  wire[`ROB_ADDR_BUS] read_rob_addr_out;
  wire                read_is_branch_taken_out;
  wire[`GHR_BUS]      read_pht_index_out;
  wire[`ADDR_BUS]     read_inst_branch_target_out;
  wire                read_mem_write_flag_out;
  wire                read_mem_read_flag_out;
  wire                read_mem_sign_ext_flag_out;
  wire[3:0]           read_mem_sel_out;
  wire[`DATA_BUS]     read_mem_offset_out;
  wire                read_cp0_read_flag_out;
  wire                read_cp0_write_flag_out;
  wire[`CP0_ADDR_BUS] read_cp0_addr_out;
  wire[`EXC_TYPE_BUS] read_exception_type_out;
  wire[`OPGEN_BUS]    read_opgen_out;
  wire[`SHAMT_BUS]    read_shamt_out;
  wire                read_operand_is_ref_1_out;
  wire                read_operand_is_ref_2_out;
  wire[`DATA_BUS]     read_operand_data_1_out;
  wire[`DATA_BUS]     read_operand_data_2_out;
  wire[`ADDR_BUS]     read_pc_out;
  wire                can_write;
  wire[`ROB_ADDR_BUS] write_rob_addr_out;
  wire                can_commit;
  wire                commit_reg_write_en_out;
  wire[`REG_ADDR_BUS] commit_reg_write_addr_out;
  wire[`DATA_BUS]     commit_reg_write_data_out;
  wire[`EXC_TYPE_BUS] commit_exception_type_out;
  wire                commit_is_delayslot_out;
  wire[`ADDR_BUS]     commit_pc_out;

  ReorderBuffer reorder_buffer(
    .clk                          (clk),
    .rst                          (rst),

    .read_en                      (read_en),
    .can_read                     (can_read),
    .read_rob_addr_out            (read_rob_addr_out),
    .read_is_branch_taken_out     (read_is_branch_taken_out),
    .read_pht_index_out           (read_pht_index_out),
    .read_inst_branch_target_out  (read_inst_branch_target_out),
    .read_mem_write_flag_out      (read_mem_write_flag_out),
    .read_mem_read_flag_out       (read_mem_read_flag_out),
    .read_mem_sign_ext_flag_out   (read_mem_sign_ext_flag_out),
    .read_mem_sel_out             (read_mem_sel_out),
    .read_mem_offset_out          (read_mem_offset_out),
    .read_cp0_read_flag_out       (read_cp0_read_flag_out),
    .read_cp0_write_flag_out      (read_cp0_write_flag_out),
    .read_cp0_addr_out            (read_cp0_addr_out),
    .read_exception_type_out      (read_exception_type_out),
    .read_opgen_out               (read_opgen_out),
    .read_shamt_out               (read_shamt_out),
    .read_operand_is_ref_1_out    (read_operand_is_ref_1_out),
    .read_operand_is_ref_2_out    (read_operand_is_ref_2_out),
    .read_operand_data_1_out      (read_operand_data_1_out),
    .read_operand_data_2_out      (read_operand_data_2_out),
    .read_pc_out                  (read_pc_out),

    .write_en                     (write_en),
    .can_write                    (can_write),
    .write_rob_addr_out           (write_rob_addr_out),
    .write_reg_write_en_in        (0),
    .write_reg_write_addr_in      (0),
    .write_is_branch_taken_in     (0),
    .write_pht_index_in           (0),
    .write_inst_branch_target_in  (0),
    .write_mem_write_flag_in      (0),
    .write_mem_read_flag_in       (0),
    .write_mem_sign_ext_flag_in   (0),
    .write_mem_sel_in             (0),
    .write_mem_offset_in          (0),
    .write_cp0_read_flag_in       (0),
    .write_cp0_write_flag_in      (0),
    .write_cp0_addr_in            (0),
    .write_exception_type_in      (0),
    .write_is_delayslot_in        (0),
    .write_opgen_in               (0),
    .write_shamt_in               (0),
    .write_operand_is_ref_1_in    (0),
    .write_operand_is_ref_2_in    (0),
    .write_operand_data_1_in      (0),
    .write_operand_data_2_in      (0),
    .write_pc_in                  (pc),

    .update_en                    (update_en),
    .update_addr                  (update_addr),
    .update_reg_write_data_in     (0),
    .update_exception_type_in     (0),

    .commit_en                    (commit_en),
    .can_commit                   (can_commit),
    .commit_reg_write_en_out      (commit_reg_write_en_out),
    .commit_reg_write_addr_out    (commit_reg_write_addr_out),
    .commit_reg_write_data_out    (commit_reg_write_data_out),
    .commit_exception_type_out    (commit_exception_type_out),
    .commit_is_delayslot_out      (commit_is_delayslot_out),
    .commit_pc_out                (commit_pc_out),

    .erase_en                     (erase_en),
    .erase_from_addr              (erase_from_addr)
  );

  always @(posedge clk) begin
    if (!rst) begin
      read_en <= 0;
      write_en <= 0;
      update_en <= 0;
      update_addr <= 0;
      commit_en <= 0;
      erase_en <= 0;
      erase_from_addr <= 0;
      pc <= 32'hbfc00000;
    end
    else begin
      pc <= pc + 4;
      
      case (`TICK)
        0: begin
          $display(">>>>>> write");
          read_en <= 0;
          write_en <= 1;
          update_en <= 0;
          update_addr <= 0;
          commit_en <= 0;
          erase_en <= 0;
          erase_from_addr <= 0;
        end
        1: begin
          $display(">>>>>> write");
          read_en <= 0;
          write_en <= 1;
          update_en <= 0;
          update_addr <= 0;
          commit_en <= 0;
          erase_en <= 0;
          erase_from_addr <= 0;
        end
        2: begin
          $display(">>>>>> read");
          read_en <= 1;
          write_en <= 0;
          update_en <= 0;
          update_addr <= 0;
          commit_en <= 0;
          erase_en <= 0;
          erase_from_addr <= 0;
        end
        3: begin
          $display(">>>>>> update");
          read_en <= 0;
          write_en <= 0;
          update_en <= 1;
          update_addr <= 0;
          commit_en <= 0;
          erase_en <= 0;
          erase_from_addr <= 0;
        end
        4: begin
          $display(">>>>>> read, write, update, commit");
          read_en <= 1;
          write_en <= 1;
          update_en <= 1;
          update_addr <= 1;
          commit_en <= 1;
          erase_en <= 0;
          erase_from_addr <= 0;
        end
        5: begin
          $display(">>>>>> erase");
          read_en <= 0;
          write_en <= 0;
          update_en <= 0;
          update_addr <= 0;
          commit_en <= 0;
          erase_en <= 1;
          erase_from_addr <= 1;
        end
      endcase
      
    `DISPLAY("can_read            ", can_read);
    `DISPLAY("can_write           ", can_write);
    `DISPLAY("can_commit          ", can_commit);
    `DISPLAY("read_rob_addr_out   ", read_rob_addr_out);
    `DISPLAY("write_rob_addr_out  ", write_rob_addr_out);
    `DISPLAY("pc                  ", pc);
    `DISPLAY("read_pc_out         ", read_pc_out);
    `DISPLAY("commit_pc_out       ", commit_pc_out);
    $display("");
    `END_AT_TICK(6);
    end
  end

endmodule
module ReorderBuffer_tb(
  input clk,
  input rst
);


  `GEN_TICK(clk, rst);


  reg                 read_en;
  reg                 write_en;
  reg                 update_en;
  reg[`ROB_ADDR_BUS]  update_addr;
  reg                 commit_en;
  reg                 erase_en;
  reg[`ROB_ADDR_BUS]  erase_from_addr;
  reg[`ADDR_BUS]      pc;


  wire                can_read;
  wire[`ROB_ADDR_BUS] read_rob_addr_out;
  wire                read_is_branch_taken_out;
  wire[`GHR_BUS]      read_pht_index_out;
  wire[`ADDR_BUS]     read_inst_branch_target_out;
  wire                read_mem_write_flag_out;
  wire                read_mem_read_flag_out;
  wire                read_mem_sign_ext_flag_out;
  wire[3:0]           read_mem_sel_out;
  wire[`DATA_BUS]     read_mem_offset_out;
  wire                read_cp0_read_flag_out;
  wire                read_cp0_write_flag_out;
  wire[`CP0_ADDR_BUS] read_cp0_addr_out;
  wire[`EXC_TYPE_BUS] read_exception_type_out;
  wire[`OPGEN_BUS]    read_opgen_out;
  wire[`SHAMT_BUS]    read_shamt_out;
  wire                read_operand_is_ref_1_out;
  wire                read_operand_is_ref_2_out;
  wire[`DATA_BUS]     read_operand_data_1_out;
  wire[`DATA_BUS]     read_operand_data_2_out;
  wire[`ADDR_BUS]     read_pc_out;
  wire                can_write;
  wire[`ROB_ADDR_BUS] write_rob_addr_out;
  wire                can_commit;
  wire                commit_reg_write_en_out;
  wire[`REG_ADDR_BUS] commit_reg_write_addr_out;
  wire[`DATA_BUS]     commit_reg_write_data_out;
  wire[`EXC_TYPE_BUS] commit_exception_type_out;
  wire                commit_is_delayslot_out;
  wire[`ADDR_BUS]     commit_pc_out;

  ReorderBuffer reorder_buffer(
    .clk                          (clk),
    .rst                          (rst),

    .read_en                      (read_en),
    .can_read                     (can_read),
    .read_rob_addr_out            (read_rob_addr_out),
    .read_is_branch_taken_out     (read_is_branch_taken_out),
    .read_pht_index_out           (read_pht_index_out),
    .read_inst_branch_target_out  (read_inst_branch_target_out),
    .read_mem_write_flag_out      (read_mem_write_flag_out),
    .read_mem_read_flag_out       (read_mem_read_flag_out),
    .read_mem_sign_ext_flag_out   (read_mem_sign_ext_flag_out),
    .read_mem_sel_out             (read_mem_sel_out),
    .read_mem_offset_out          (read_mem_offset_out),
    .read_cp0_read_flag_out       (read_cp0_read_flag_out),
    .read_cp0_write_flag_out      (read_cp0_write_flag_out),
    .read_cp0_addr_out            (read_cp0_addr_out),
    .read_exception_type_out      (read_exception_type_out),
    .read_opgen_out               (read_opgen_out),
    .read_shamt_out               (read_shamt_out),
    .read_operand_is_ref_1_out    (read_operand_is_ref_1_out),
    .read_operand_is_ref_2_out    (read_operand_is_ref_2_out),
    .read_operand_data_1_out      (read_operand_data_1_out),
    .read_operand_data_2_out      (read_operand_data_2_out),
    .read_pc_out                  (read_pc_out),

    .write_en                     (write_en),
    .can_write                    (can_write),
    .write_rob_addr_out           (write_rob_addr_out),
    .write_reg_write_en_in        (0),
    .write_reg_write_addr_in      (0),
    .write_is_branch_taken_in     (0),
    .write_pht_index_in           (0),
    .write_inst_branch_target_in  (0),
    .write_mem_write_flag_in      (0),
    .write_mem_read_flag_in       (0),
    .write_mem_sign_ext_flag_in   (0),
    .write_mem_sel_in             (0),
    .write_mem_offset_in          (0),
    .write_cp0_read_flag_in       (0),
    .write_cp0_write_flag_in      (0),
    .write_cp0_addr_in            (0),
    .write_exception_type_in      (0),
    .write_is_delayslot_in        (0),
    .write_opgen_in               (0),
    .write_shamt_in               (0),
    .write_operand_is_ref_1_in    (0),
    .write_operand_is_ref_2_in    (0),
    .write_operand_data_1_in      (0),
    .write_operand_data_2_in      (0),
    .write_pc_in                  (pc),

    .update_en                    (update_en),
    .update_addr                  (update_addr),
    .update_reg_write_data_in     (0),
    .update_exception_type_in     (0),

    .commit_en                    (commit_en),
    .can_commit                   (can_commit),
    .commit_reg_write_en_out      (commit_reg_write_en_out),
    .commit_reg_write_addr_out    (commit_reg_write_addr_out),
    .commit_reg_write_data_out    (commit_reg_write_data_out),
    .commit_exception_type_out    (commit_exception_type_out),
    .commit_is_delayslot_out      (commit_is_delayslot_out),
    .commit_pc_out                (commit_pc_out),

    .erase_en                     (erase_en),
    .erase_from_addr              (erase_from_addr)
  );

  always @(posedge clk) begin
    if (!rst) begin
      read_en <= 0;
      write_en <= 0;
      update_en <= 0;
      update_addr <= 0;
      commit_en <= 0;
      erase_en <= 0;
      erase_from_addr <= 0;
      pc <= 32'hbfc00000;
    end
    else begin
      pc <= pc + 4;
      
      case (`TICK)
        0: begin
          $display(">>>>>> write");
          read_en <= 0;
          write_en <= 1;
          update_en <= 0;
          update_addr <= 0;
          commit_en <= 0;
          erase_en <= 0;
          erase_from_addr <= 0;
        end
        1: begin
          $display(">>>>>> write");
          read_en <= 0;
          write_en <= 1;
          update_en <= 0;
          update_addr <= 0;
          commit_en <= 0;
          erase_en <= 0;
          erase_from_addr <= 0;
        end
        2: begin
          $display(">>>>>> read");
          read_en <= 1;
          write_en <= 0;
          update_en <= 0;
          update_addr <= 0;
          commit_en <= 0;
          erase_en <= 0;
          erase_from_addr <= 0;
        end
        3: begin
          $display(">>>>>> update");
          read_en <= 0;
          write_en <= 0;
          update_en <= 1;
          update_addr <= 0;
          commit_en <= 0;
          erase_en <= 0;
          erase_from_addr <= 0;
        end
        4: begin
          $display(">>>>>> read, write, update, commit");
          read_en <= 1;
          write_en <= 1;
          update_en <= 1;
          update_addr <= 1;
          commit_en <= 1;
          erase_en <= 0;
          erase_from_addr <= 0;
        end
        5: begin
          $display(">>>>>> erase");
          read_en <= 0;
          write_en <= 0;
          update_en <= 0;
          update_addr <= 0;
          commit_en <= 0;
          erase_en <= 1;
          erase_from_addr <= 1;
        end
      endcase
      
    `DISPLAY("can_read            ", can_read);
    `DISPLAY("can_write           ", can_write);
    `DISPLAY("can_commit          ", can_commit);
    `DISPLAY("read_rob_addr_out   ", read_rob_addr_out);
    `DISPLAY("write_rob_addr_out  ", write_rob_addr_out);
    `DISPLAY("pc                  ", pc);
    `DISPLAY("read_pc_out         ", read_pc_out);
    `DISPLAY("commit_pc_out       ", commit_pc_out);
    $display("");
    `END_AT_TICK(6);
    end
  end

endmodule