data/full_repos/permissive/136660017/tut-04-busses.v
1: b'%Error: data/full_repos/permissive/136660017/tut-04-busses.v:10: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,bench);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-04-busses.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-04-busses.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #4;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-04-busses.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #4;\n  ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bench;
 reg [3:0]A,B,C,D;
 wire [3:0]X;
 wire [7:0]Y;
 
 assign X=A+B;
 assign Y=C*D;
 
 initial begin
  $dumpvars(0,bench);
  #1;
  A=2;
  B=-1;
  C=2;
  D=3;
  #4;
  A=11;
  B=6;
  C=5;
  D=5;
  #4;
  $finish;
 end
endmodule
module bench;

 reg [3:0]A,B,C,D;
 wire [3:0]X;
 wire [7:0]Y;
 
 assign X=A+B;
 assign Y=C*D;
 
 initial begin
  $dumpvars(0,bench);
  #1;
  A=2;
  B=-1;
  C=2;
  D=3;
  #4;
  A=11;
  B=6;
  C=5;
  D=5;
  #4;
  $finish;
 end
endmodule