data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v:11: Multiple top level modules\n                                                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                  : ... Top module \'$_DFF_P_\'\nmodule \\$_DFF_P_ (D, C, Q);\n       ^~~~~~~~~\n                                                                                                                  : ... Top module \'$_DFF_PP0_\'\nmodule \\$_DFF_PP0_ (D, C, R, Q);\n       ^~~~~~~~~~~\n                                                                                                                  : ... Top module \'$_DFF_PN0_\'\nmodule \\$_DFF_PN0_ (D, C, R, Q);\n       ^~~~~~~~~~~\n                                                                                                                  : ... Top module \'$_DFFE_PP0P_\'\nmodule  \\$_DFFE_PP0P_ (D, C, E, R, Q);\n        ^~~~~~~~~~~~~\n                                                                                                                  : ... Top module \'$_DLATCH_PP0_\'\nmodule  \\$_DLATCH_PP0_ (input E, R, D, output Q);\n        ^~~~~~~~~~~~~~\n                                                                                                                  : ... Top module \'$_DFF_N_\'\nmodule \\$_DFF_N_ (D, CN, Q);\n       ^~~~~~~~~\n                                                                                                                  : ... Top module \'$_DFF_NP0_\'\nmodule \\$_DFF_NP0_ (D, C, R, Q);\n       ^~~~~~~~~~~\n                                                                                                                  : ... Top module \'$_DFFE_NP0P_\'\nmodule  \\$_DFFE_NP0P_ (D, C, E, R, Q);\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v:74: Cannot find file containing module: \'dffre\'\n    dffre  #(.IS_C_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib,data/full_repos/permissive/137416811/dffre\n             data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib,data/full_repos/permissive/137416811/dffre.v\n             data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib,data/full_repos/permissive/137416811/dffre.sv\n             dffre\n             dffre.v\n             dffre.sv\n             obj_dir/dffre\n             obj_dir/dffre.v\n             obj_dir/dffre.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v:64: Cannot find file containing module: \'dffnr\'\n    dffnr #(.IS_C_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CN(C), .R(R));\n    ^~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v:55: Cannot find file containing module: \'dff\'\n    dff #(.IS_C_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN));\n    ^~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v:44: Cannot find file containing module: \'latchre\'\n    latchre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1\'b1), .G(E),  .R(R));\n    ^~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v:38: Cannot find file containing module: \'dffre\'\n    dffre  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));\n    ^~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v:27: Cannot find file containing module: \'dffrn\'\n    dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));\n    ^~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v:17: Cannot find file containing module: \'dffr\'\n    dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));\n    ^~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v:7: Cannot find file containing module: \'dff\'\n    dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));\n    ^~~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module \$_DFF_N_ (D, CN, Q);
    input D;
    input CN;
    output Q;
    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
    dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN));
endmodule
module \$_DFF_N_ (D, CN, Q);

    input D;
    input CN;
    output Q;
    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
    dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN));
endmodule