data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v
 line:38 column:28: Illegal character "'"
1: b'%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:1: Cannot find include file: ../defines.v\n`include "../defines.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169155753/source/pll,data/full_repos/permissive/169155753/../defines.v\n             data/full_repos/permissive/169155753/source/pll,data/full_repos/permissive/169155753/../defines.v.v\n             data/full_repos/permissive/169155753/source/pll,data/full_repos/permissive/169155753/../defines.v.sv\n             ../defines.v\n             ../defines.v.v\n             ../defines.v.sv\n             obj_dir/../defines.v\n             obj_dir/../defines.v.v\n             obj_dir/../defines.v.sv\n%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:47: Cannot find include file: config/148_5_Mhz.v\n                `include "config/148_5_Mhz.v" \n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:50: Cannot find include file: config/74_25_MHz.v\n                `include "config/74_25_MHz.v" \n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:53: Cannot find include file: config/74_25_MHz.v\n                `include "config/74_25_MHz.v" \n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:56: Cannot find include file: config/27_MHz.v\n                `include "config/27_MHz.v" \n                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:59: Cannot find include file: config/27_MHz.v\n                `include "config/27_MHz.v" \n                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:46: Define or directive not defined: \'`MODE_1080p\'\n            `MODE_1080p: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:46: syntax error, unexpected \':\', expecting endcase\n            `MODE_1080p: begin\n                       ^\n%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:49: Define or directive not defined: \'`MODE_1080i\'\n            `MODE_1080i: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:52: Define or directive not defined: \'`MODE_720p\'\n            `MODE_720p: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:55: Define or directive not defined: \'`MODE_480p\'\n            `MODE_480p: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/pll/pll_reconf_rom.v:58: Define or directive not defined: \'`MODE_480i\'\n            `MODE_480i: begin\n            ^~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module pll_reconf_rom (
    input clock,
    input [7:0] address,
    input read_ena,
    input [7:0] data,
    input pll_reconf_busy,

    output q,
    output reconfig,
    output reg trigger_read
);

    reg _read_ena = 0;
    reg q_reg;
    reg q_reg_2;
    reg doReconfig;
    reg doReconfig_2;
    reg doReconfig_3;

    reg [7:0] data_req = 8'h_FF;

    assign q = q_reg_2;
    assign reconfig = doReconfig_3;

    always @(posedge clock) begin
        _read_ena <= read_ena;

        if (_read_ena && ~read_ena) begin
            doReconfig <= 1;
        end else begin
            doReconfig <= 0;
        end

        if (~pll_reconf_busy && data != data_req) begin
            data_req <= data;
            trigger_read <= 1'b1;
        end else begin
            trigger_read <= 1'b0;
        end


        case (data_req)

            `MODE_1080p: begin
                `include "config/148_5_Mhz.v"
            end
            `MODE_1080i: begin
                `include "config/74_25_MHz.v"
            end
            `MODE_720p: begin
                `include "config/74_25_MHz.v"
            end
            `MODE_480p: begin
                `include "config/27_MHz.v"
            end
            `MODE_480i: begin
                `include "config/27_MHz.v"
            end
        endcase


        q_reg_2 <= q_reg;
        doReconfig_2 <= doReconfig;
        doReconfig_3 <= doReconfig_2;
    end

endmodule
module pll_reconf_rom (
    input clock,
    input [7:0] address,
    input read_ena,
    input [7:0] data,
    input pll_reconf_busy,

    output q,
    output reconfig,
    output reg trigger_read
);


    reg _read_ena = 0;
    reg q_reg;
    reg q_reg_2;
    reg doReconfig;
    reg doReconfig_2;
    reg doReconfig_3;

    reg [7:0] data_req = 8'h_FF;

    assign q = q_reg_2;
    assign reconfig = doReconfig_3;

    always @(posedge clock) begin
        _read_ena <= read_ena;

        if (_read_ena && ~read_ena) begin
            doReconfig <= 1;
        end else begin
            doReconfig <= 0;
        end

        if (~pll_reconf_busy && data != data_req) begin
            data_req <= data;
            trigger_read <= 1'b1;
        end else begin
            trigger_read <= 1'b0;
        end


        case (data_req)

            `MODE_1080p: begin
                `include "config/148_5_Mhz.v"
            end
            `MODE_1080i: begin
                `include "config/74_25_MHz.v"
            end
            `MODE_720p: begin
                `include "config/74_25_MHz.v"
            end
            `MODE_480p: begin
                `include "config/27_MHz.v"
            end
            `MODE_480i: begin
                `include "config/27_MHz.v"
            end
        endcase


        q_reg_2 <= q_reg;
        doReconfig_2 <= doReconfig;
        doReconfig_3 <= doReconfig_2;
    end

endmodule