data/full_repos/permissive/201488448/2_circuits/2_sequential/36_rule90.v
1: b'%Warning-WIDTH: data/full_repos/permissive/201488448/2_circuits/2_sequential/36_rule90.v:18: Operator XOR expects 512 bits on the LHS, but LHS\'s SEL generates 511 bits.\n                                                                                           : ... In instance top_module\n   q <= q[511:1] ^ {q[510:0], 1\'b0} ;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top_module(
	input clk,
	input load,
	input [511:0] data,
	output reg [511:0] q);
	
	always @(posedge clk) begin
		if (load)
			q <= data;
		else begin




			


			q <= q[511:1] ^ {q[510:0], 1'b0} ;
		end
	end
endmodule
module top_module(
	input clk,
	input load,
	input [511:0] data,
	output reg [511:0] q);

	
	always @(posedge clk) begin
		if (load)
			q <= data;
		else begin




			


			q <= q[511:1] ^ {q[510:0], 1'b0} ;
		end
	end
endmodule