data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:1: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Data/Control/Control.v\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Data/Control/Control.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Data/Control/Control.v.sv\n             Data/Control/Control.v\n             Data/Control/Control.v.v\n             Data/Control/Control.v.sv\n             obj_dir/Data/Control/Control.v\n             obj_dir/Data/Control/Control.v.v\n             obj_dir/Data/Control/Control.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:2: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:4: Cannot find include file: Mips/Pipeline/Fwd/Ex.v\n`include "Mips/Pipeline/Fwd/Ex.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:5: Cannot find include file: Mips/Pipeline/Reg/Ex.v\n`include "Mips/Pipeline/Reg/Ex.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:6: Cannot find include file: Mips/Pipeline/Ex/Mem.v\n`include "Mips/Pipeline/Ex/Mem.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:7: Cannot find include file: Mips/Pipeline/Ex/Fwd.v\n`include "Mips/Pipeline/Ex/Fwd.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:8: Cannot find include file: Mips/Pipeline/Ex/Haz.v\n`include "Mips/Pipeline/Ex/Haz.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:10: Cannot find include file: Mips/Datapath/Alu/datapath.v\n`include "Mips/Datapath/Alu/datapath.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:15: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T (input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:15: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Control_Control_T (input) ctrl\n                            ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:16: Define or directive not defined: \'`Mips_Pipeline_RegEx_T\'\n , `Mips_Pipeline_RegEx_T (input) pipeRegEx\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:17: Define or directive not defined: \'`Mips_Pipeline_FwdEx_T\'\n , `Mips_Pipeline_FwdEx_T (input) pipeFwdEx\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:18: Define or directive not defined: \'`Mips_Pipeline_ExHaz_T\'\n , `Mips_Pipeline_ExHaz_T (output) pipeExHaz\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:19: Define or directive not defined: \'`Mips_Pipeline_ExMem_T\'\n , `Mips_Pipeline_ExMem_T (output) pipeExMem\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:20: Define or directive not defined: \'`Mips_Pipeline_ExFwd_T\'\n , `Mips_Pipeline_ExFwd_T (output) pipeExFwd\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:23: Define or directive not defined: \'`Mips_Pipeline_RegEx_Decl_Defaults\'\n`Mips_Pipeline_RegEx_Decl_Defaults\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:34: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) regPort1Fwd;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:35: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) regPort2Fwd;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/ex.v:42: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) aluResult;\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module Mips_Stage_ex #
	( parameter DELAYED = 1
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Pipeline_RegEx_T (input) pipeRegEx
	, `Mips_Pipeline_FwdEx_T (input) pipeFwdEx
	, `Mips_Pipeline_ExHaz_T (output) pipeExHaz
	, `Mips_Pipeline_ExMem_T (output) pipeExMem
	, `Mips_Pipeline_ExFwd_T (output) pipeExFwd
	);

`Mips_Pipeline_RegEx_Decl_Defaults
Mips_Pipeline_RegEx_unpack REGEX
	( .in (pipeRegEx)
	, .instruction (instruction)
	, .pcAddr      (pcAddr)
	, .regPort1    (regPort1)
	, .regPort2    (regPort2)
	, .regPorts    (regPorts)
	, .control     (control)
	);

`Mips_Type_Word_T (wire) regPort1Fwd;
`Mips_Type_Word_T (wire) regPort2Fwd;
Mips_Pipeline_FwdEx_unpack FWDEX
	( .in (pipeFwdEx)
	, .regPort1 (regPort1Fwd)
	, .regPort2 (regPort2Fwd)
	);

`Mips_Type_Word_T (wire) aluResult;
Mips_Datapath_Alu_datapath ALU
	( .ctrl (ctrl)
	, .instruction (instruction)
	, .regPort1    (regPort1Fwd)
	, .regPort2    (regPort2Fwd)
	, .control     (control)
	, .result      (aluResult)
	, .status      ()
	);

Mips_Pipeline_ExMem_generate #
	( .DELAYED (DELAYED)
	) EXMEM
	( .ctrl (ctrl)
	, .instruction (instruction)
	, .pcAddr      (pcAddr)
	, .control     (control)
	, .regPort2    (regPort2)
	, .regPorts    (regPorts)
	, .aluResult   (aluResult)
	, .out         (pipeExMem)
	);

Mips_Pipeline_ExFwd_pack EXFWD
	( .out (pipeExFwd)
	, .regPort1 (regPort1)
	, .regPort2 (regPort2)
	, .regPorts (regPorts)
	);

Mips_Pipeline_ExHaz_pack EXHAZ
	( .out (pipeExHaz)
	, .regPorts (regPorts)
	);

endmodule
module Mips_Stage_ex #
	( parameter DELAYED = 1
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Pipeline_RegEx_T (input) pipeRegEx
	, `Mips_Pipeline_FwdEx_T (input) pipeFwdEx
	, `Mips_Pipeline_ExHaz_T (output) pipeExHaz
	, `Mips_Pipeline_ExMem_T (output) pipeExMem
	, `Mips_Pipeline_ExFwd_T (output) pipeExFwd
	);


`Mips_Pipeline_RegEx_Decl_Defaults
Mips_Pipeline_RegEx_unpack REGEX
	( .in (pipeRegEx)
	, .instruction (instruction)
	, .pcAddr      (pcAddr)
	, .regPort1    (regPort1)
	, .regPort2    (regPort2)
	, .regPorts    (regPorts)
	, .control     (control)
	);

`Mips_Type_Word_T (wire) regPort1Fwd;
`Mips_Type_Word_T (wire) regPort2Fwd;
Mips_Pipeline_FwdEx_unpack FWDEX
	( .in (pipeFwdEx)
	, .regPort1 (regPort1Fwd)
	, .regPort2 (regPort2Fwd)
	);

`Mips_Type_Word_T (wire) aluResult;
Mips_Datapath_Alu_datapath ALU
	( .ctrl (ctrl)
	, .instruction (instruction)
	, .regPort1    (regPort1Fwd)
	, .regPort2    (regPort2Fwd)
	, .control     (control)
	, .result      (aluResult)
	, .status      ()
	);

Mips_Pipeline_ExMem_generate #
	( .DELAYED (DELAYED)
	) EXMEM
	( .ctrl (ctrl)
	, .instruction (instruction)
	, .pcAddr      (pcAddr)
	, .control     (control)
	, .regPort2    (regPort2)
	, .regPorts    (regPorts)
	, .aluResult   (aluResult)
	, .out         (pipeExMem)
	);

Mips_Pipeline_ExFwd_pack EXFWD
	( .out (pipeExFwd)
	, .regPort1 (regPort1)
	, .regPort2 (regPort2)
	, .regPorts (regPorts)
	);

Mips_Pipeline_ExHaz_pack EXHAZ
	( .out (pipeExHaz)
	, .regPorts (regPorts)
	);

endmodule