data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v
1: b'%Error: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:89: Cannot find file containing module: \'InstMemory\'\n    InstMemory u2(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new,data/full_repos/permissive/194376374/InstMemory\n             data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new,data/full_repos/permissive/194376374/InstMemory.v\n             data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new,data/full_repos/permissive/194376374/InstMemory.sv\n             InstMemory\n             InstMemory.v\n             InstMemory.sv\n             obj_dir/InstMemory\n             obj_dir/InstMemory.v\n             obj_dir/InstMemory.sv\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:96: Cannot find file containing module: \'Ctr\'\n    Ctr mainCtr(\n    ^~~\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:110: Cannot find file containing module: \'signext\'\n    signext u1(\n    ^~~~~~~\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:116: Cannot find file containing module: \'registers\'\n    registers u0(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:129: Cannot find file containing module: \'ALUctr\'\n    ALUctr u3(\n    ^~~~~~\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:136: Cannot find file containing module: \'ALU\'\n    ALU u4(\n    ^~~\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:145: Cannot find file containing module: \'dataMemory\'\n    dataMemory u5(\n    ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:154: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'S3_BRANCH\' generates 1 bits.\n                                                                                                    : ... In instance Top\n     assign PC_SRC=S3_ALU_ZERO & S3_BRANCH;  \n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:154: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                                    : ... In instance Top\n     assign PC_SRC=S3_ALU_ZERO & S3_BRANCH;  \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:257: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'EX_ALU_ZERO\' generates 1 bits.\n                                                                                                    : ... In instance Top\n   S3_ALU_ZERO = EX_ALU_ZERO;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:276: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                                                    : ... In instance Top\n   S2_REG_ADDR_HIGH = S1_INST[20:16];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/194376374/0521_LJX_lab6/lab5.srcs/sources_1/new/Top.v:277: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                                                    : ... In instance Top\n   S2_REG_ADDR_LOW = S1_INST[15:11];\n                   ^\n%Error: Exiting due to 7 error(s), 5 warning(s)\n'
module Top(
    input Clk,
    input reset
);
    
    reg [31:0] PC;


	 reg[31:0] S1_PC_ADD4;
	 reg[31:0] S1_INST;

	 reg S2_REG_WRITE, S2_MEM_TO_REG;
	 reg S2_BRANCH, S2_MEM_READ, S2_MEM_WRITE;
	 reg S2_REG_DST, S2_ALU_SRC;
	 reg [1:0] S2_ALU_OP;
	 reg[31:0] S2_PC_ADD4;
	 reg[31:0] S2_READ_DATA1;
	 reg[31:0] S2_READ_DATA2;
	 reg[31:0] S2_SIGNEXT_IMME;
	 reg[5:0] S2_REG_ADDR_HIGH;
	 reg[5:0] S2_REG_ADDR_LOW;

	 reg S3_REG_WRITE, S3_MEM_TO_REG;
	 reg S3_BRANCH, S3_MEM_READ, S3_MEM_WRITE;
	 reg[31:0] S3_BRANCH_ADDR;
	 reg[31:0] S3_ALU_RES;
	 reg[31:0] S3_ALU_ZERO;
	 reg[31:0] S3_MEM_WRITE_DATA;
	 reg[5:0]  S3_REG_ADDR;

	 reg S4_REG_WRITE, S4_MEM_TO_REG;
	 reg[31:0] S4_MEM_READ_DATA;
	 reg[31:0] S4_ALU_RES;
	 reg[5:0]  S4_REG_ADDR;

	 wire PC_SRC;
	 wire[31:0] IF_INST;

	 wire ID_REG_DST;
	 wire ID_ALU_SRC;
	 wire ID_MEM_TO_REG;
	 wire ID_REG_WRITE;
	 wire ID_MEM_READ;
	 wire ID_MEM_WRITE;
	 wire ID_BRANCH;
	 wire[1:0] ID_ALU_OP;
	 wire[31:0] ID_READ_DATA1;
	 wire[31:0] ID_READ_DATA2;
	 wire[31:0] ID_SIGNEXT_IMME;
	 wire JUMP;
	 
	 wire[31:0] MEM_MEM_READ_DATA;
	 

	 wire[3:0] EX_ALU_CTR;
	 wire EX_ALU_ZERO;
	 wire[31:0] EX_ALU_RES;

    

    initial begin
    PC=0;

    end    
    

    InstMemory u2(
        .INST(IF_INST),
        .PC(PC),
        .reset(reset)
    );
        

    Ctr mainCtr(
        .OpCode(S1_INST[31:26]),
        .RegDst(ID_REG_DST),
        .Jump(JUMP),
        .Branch(ID_BRANCH),
        .MemRead(ID_MEM_READ),
        .MemToReg(ID_MEM_TO_REG),
        .ALUOp(ID_ALU_OP),
        .MemWrite(ID_MEM_WRITE),
        .ALUSrc(ID_ALU_SRC),
        .RegWrite(ID_REG_WRITE)
    );
                  

    signext u1(
        .inst(S1_INST[15:0]),
        .data(ID_SIGNEXT_IMME)
    );    
    

    registers u0(
        .readReg1(S1_INST[25:21]),
        .readReg2(S1_INST[20:16]),
        .writeReg(S4_REG_ADDR),
        .writeData(S4_MEM_TO_REG ? S4_MEM_READ_DATA : S4_ALU_RES),
        .regWrite(S4_REG_WRITE),
        .Clk(Clk),
        
        .readData1(ID_READ_DATA1),
        .readData2(ID_READ_DATA2)
    );
    

    ALUctr u3(
        .Funct(S2_SIGNEXT_IMME[5:0]),
        .ALUOp(S2_ALU_OP),
        .ALUCtrOut(EX_ALU_CTR)   
    );
        

    ALU u4(
        .input1(S2_READ_DATA1),
        .input2(S2_ALU_SRC ? S2_SIGNEXT_IMME : S2_READ_DATA2),
        .aluCtr(EX_ALU_CTR),
        .aluRes(EX_ALU_RES),
        .zero(EX_ALU_ZERO)
    );   
        

    dataMemory u5(
        .Clk(Clk),
        .address(S3_ALU_RES),
        .writeData(S3_MEM_WRITE_DATA),
        .memWrite(S3_MEM_WRITE),
        .memRead(S3_MEM_READ),
        .readData(MEM_MEM_READ_DATA)
    );
                  
     assign PC_SRC=S3_ALU_ZERO & S3_BRANCH;  

     always @ (posedge Clk)
        begin
		if (reset) 
		    begin
		    PC<=0;

			S1_PC_ADD4=0;
			S1_INST=32'b00000011111111111111100000100000;
			

			S2_REG_WRITE=0;
			S2_MEM_TO_REG=0;
				 
			S2_BRANCH=0;
			S2_MEM_READ=0;
			S2_MEM_WRITE=0;
				 
			S2_REG_DST=0;
			S2_ALU_SRC=0;
			S2_ALU_OP=0;
			
			S2_PC_ADD4=0;
			S2_READ_DATA1=0;
			S2_READ_DATA2=0;
			S2_SIGNEXT_IMME=0;
			S2_REG_ADDR_HIGH=0;
			S2_REG_ADDR_LOW=0;
			
			

			S3_REG_WRITE=0;
			S3_MEM_TO_REG=0;
			S3_BRANCH=0;
			S3_MEM_READ=0;
			S3_MEM_WRITE=0;
			
			S3_BRANCH_ADDR=0;
			S3_ALU_RES=0;
			S3_ALU_ZERO=0;
			S3_MEM_WRITE_DATA=0;
			S3_REG_ADDR=0;
			
			

			S4_REG_WRITE=0;
			S4_MEM_TO_REG=0;
			
			S4_MEM_READ_DATA=0;
			S4_ALU_RES=0;
			S4_REG_ADDR=0;		
		    end
		else 		
		begin













	        



		    
		

			S4_REG_WRITE = S3_REG_WRITE;
			S4_MEM_TO_REG = S3_MEM_TO_REG;
		
			S4_MEM_READ_DATA = MEM_MEM_READ_DATA;
			S4_ALU_RES = S3_ALU_RES;
			S4_REG_ADDR = S3_REG_ADDR;
			
			



			PC = PC_SRC ? S3_BRANCH_ADDR: PC+4;
		    PC =PC % (14<<2);





		    

			S3_REG_WRITE = S2_REG_WRITE;
			S3_MEM_TO_REG = S2_MEM_TO_REG;
			S3_BRANCH = S2_BRANCH;
			S3_MEM_READ = S2_MEM_READ;
			S3_MEM_WRITE = S2_MEM_WRITE;
		
			S3_BRANCH_ADDR = S2_PC_ADD4 + (S2_SIGNEXT_IMME<<2);
			S3_ALU_RES = EX_ALU_RES;
			S3_ALU_ZERO = EX_ALU_ZERO;
			S3_MEM_WRITE_DATA = S2_READ_DATA2;
			S3_REG_ADDR = S2_REG_DST ? S2_REG_ADDR_LOW : S2_REG_ADDR_HIGH;
		 
			

			S2_REG_DST = ID_REG_DST;
			S2_ALU_SRC = ID_ALU_SRC;
			S2_MEM_TO_REG = ID_MEM_TO_REG;
			S2_REG_WRITE = ID_REG_WRITE;
			S2_MEM_READ = ID_MEM_READ;
			S2_MEM_WRITE = ID_MEM_WRITE;
			S2_BRANCH = ID_BRANCH;
			S2_ALU_OP = ID_ALU_OP;
			
			S2_PC_ADD4 = S1_PC_ADD4;
			S2_READ_DATA1 = ID_READ_DATA1;
			S2_READ_DATA2 = ID_READ_DATA2;
			S2_SIGNEXT_IMME = ID_SIGNEXT_IMME;
			S2_REG_ADDR_HIGH = S1_INST[20:16];
			S2_REG_ADDR_LOW = S1_INST[15:11];
			
			

			S1_PC_ADD4 = PC+4;
			S1_INST = IF_INST;
		end
        end


endmodule
module Top(
    input Clk,
    input reset
);

    
    reg [31:0] PC;


	 reg[31:0] S1_PC_ADD4;
	 reg[31:0] S1_INST;

	 reg S2_REG_WRITE, S2_MEM_TO_REG;
	 reg S2_BRANCH, S2_MEM_READ, S2_MEM_WRITE;
	 reg S2_REG_DST, S2_ALU_SRC;
	 reg [1:0] S2_ALU_OP;
	 reg[31:0] S2_PC_ADD4;
	 reg[31:0] S2_READ_DATA1;
	 reg[31:0] S2_READ_DATA2;
	 reg[31:0] S2_SIGNEXT_IMME;
	 reg[5:0] S2_REG_ADDR_HIGH;
	 reg[5:0] S2_REG_ADDR_LOW;

	 reg S3_REG_WRITE, S3_MEM_TO_REG;
	 reg S3_BRANCH, S3_MEM_READ, S3_MEM_WRITE;
	 reg[31:0] S3_BRANCH_ADDR;
	 reg[31:0] S3_ALU_RES;
	 reg[31:0] S3_ALU_ZERO;
	 reg[31:0] S3_MEM_WRITE_DATA;
	 reg[5:0]  S3_REG_ADDR;

	 reg S4_REG_WRITE, S4_MEM_TO_REG;
	 reg[31:0] S4_MEM_READ_DATA;
	 reg[31:0] S4_ALU_RES;
	 reg[5:0]  S4_REG_ADDR;

	 wire PC_SRC;
	 wire[31:0] IF_INST;

	 wire ID_REG_DST;
	 wire ID_ALU_SRC;
	 wire ID_MEM_TO_REG;
	 wire ID_REG_WRITE;
	 wire ID_MEM_READ;
	 wire ID_MEM_WRITE;
	 wire ID_BRANCH;
	 wire[1:0] ID_ALU_OP;
	 wire[31:0] ID_READ_DATA1;
	 wire[31:0] ID_READ_DATA2;
	 wire[31:0] ID_SIGNEXT_IMME;
	 wire JUMP;
	 
	 wire[31:0] MEM_MEM_READ_DATA;
	 

	 wire[3:0] EX_ALU_CTR;
	 wire EX_ALU_ZERO;
	 wire[31:0] EX_ALU_RES;

    

    initial begin
    PC=0;

    end    
    

    InstMemory u2(
        .INST(IF_INST),
        .PC(PC),
        .reset(reset)
    );
        

    Ctr mainCtr(
        .OpCode(S1_INST[31:26]),
        .RegDst(ID_REG_DST),
        .Jump(JUMP),
        .Branch(ID_BRANCH),
        .MemRead(ID_MEM_READ),
        .MemToReg(ID_MEM_TO_REG),
        .ALUOp(ID_ALU_OP),
        .MemWrite(ID_MEM_WRITE),
        .ALUSrc(ID_ALU_SRC),
        .RegWrite(ID_REG_WRITE)
    );
                  

    signext u1(
        .inst(S1_INST[15:0]),
        .data(ID_SIGNEXT_IMME)
    );    
    

    registers u0(
        .readReg1(S1_INST[25:21]),
        .readReg2(S1_INST[20:16]),
        .writeReg(S4_REG_ADDR),
        .writeData(S4_MEM_TO_REG ? S4_MEM_READ_DATA : S4_ALU_RES),
        .regWrite(S4_REG_WRITE),
        .Clk(Clk),
        
        .readData1(ID_READ_DATA1),
        .readData2(ID_READ_DATA2)
    );
    

    ALUctr u3(
        .Funct(S2_SIGNEXT_IMME[5:0]),
        .ALUOp(S2_ALU_OP),
        .ALUCtrOut(EX_ALU_CTR)   
    );
        

    ALU u4(
        .input1(S2_READ_DATA1),
        .input2(S2_ALU_SRC ? S2_SIGNEXT_IMME : S2_READ_DATA2),
        .aluCtr(EX_ALU_CTR),
        .aluRes(EX_ALU_RES),
        .zero(EX_ALU_ZERO)
    );   
        

    dataMemory u5(
        .Clk(Clk),
        .address(S3_ALU_RES),
        .writeData(S3_MEM_WRITE_DATA),
        .memWrite(S3_MEM_WRITE),
        .memRead(S3_MEM_READ),
        .readData(MEM_MEM_READ_DATA)
    );
                  
     assign PC_SRC=S3_ALU_ZERO & S3_BRANCH;  

     always @ (posedge Clk)
        begin
		if (reset) 
		    begin
		    PC<=0;

			S1_PC_ADD4=0;
			S1_INST=32'b00000011111111111111100000100000;
			

			S2_REG_WRITE=0;
			S2_MEM_TO_REG=0;
				 
			S2_BRANCH=0;
			S2_MEM_READ=0;
			S2_MEM_WRITE=0;
				 
			S2_REG_DST=0;
			S2_ALU_SRC=0;
			S2_ALU_OP=0;
			
			S2_PC_ADD4=0;
			S2_READ_DATA1=0;
			S2_READ_DATA2=0;
			S2_SIGNEXT_IMME=0;
			S2_REG_ADDR_HIGH=0;
			S2_REG_ADDR_LOW=0;
			
			

			S3_REG_WRITE=0;
			S3_MEM_TO_REG=0;
			S3_BRANCH=0;
			S3_MEM_READ=0;
			S3_MEM_WRITE=0;
			
			S3_BRANCH_ADDR=0;
			S3_ALU_RES=0;
			S3_ALU_ZERO=0;
			S3_MEM_WRITE_DATA=0;
			S3_REG_ADDR=0;
			
			

			S4_REG_WRITE=0;
			S4_MEM_TO_REG=0;
			
			S4_MEM_READ_DATA=0;
			S4_ALU_RES=0;
			S4_REG_ADDR=0;		
		    end
		else 		
		begin













	        



		    
		

			S4_REG_WRITE = S3_REG_WRITE;
			S4_MEM_TO_REG = S3_MEM_TO_REG;
		
			S4_MEM_READ_DATA = MEM_MEM_READ_DATA;
			S4_ALU_RES = S3_ALU_RES;
			S4_REG_ADDR = S3_REG_ADDR;
			
			



			PC = PC_SRC ? S3_BRANCH_ADDR: PC+4;
		    PC =PC % (14<<2);





		    

			S3_REG_WRITE = S2_REG_WRITE;
			S3_MEM_TO_REG = S2_MEM_TO_REG;
			S3_BRANCH = S2_BRANCH;
			S3_MEM_READ = S2_MEM_READ;
			S3_MEM_WRITE = S2_MEM_WRITE;
		
			S3_BRANCH_ADDR = S2_PC_ADD4 + (S2_SIGNEXT_IMME<<2);
			S3_ALU_RES = EX_ALU_RES;
			S3_ALU_ZERO = EX_ALU_ZERO;
			S3_MEM_WRITE_DATA = S2_READ_DATA2;
			S3_REG_ADDR = S2_REG_DST ? S2_REG_ADDR_LOW : S2_REG_ADDR_HIGH;
		 
			

			S2_REG_DST = ID_REG_DST;
			S2_ALU_SRC = ID_ALU_SRC;
			S2_MEM_TO_REG = ID_MEM_TO_REG;
			S2_REG_WRITE = ID_REG_WRITE;
			S2_MEM_READ = ID_MEM_READ;
			S2_MEM_WRITE = ID_MEM_WRITE;
			S2_BRANCH = ID_BRANCH;
			S2_ALU_OP = ID_ALU_OP;
			
			S2_PC_ADD4 = S1_PC_ADD4;
			S2_READ_DATA1 = ID_READ_DATA1;
			S2_READ_DATA2 = ID_READ_DATA2;
			S2_SIGNEXT_IMME = ID_SIGNEXT_IMME;
			S2_REG_ADDR_HIGH = S1_INST[20:16];
			S2_REG_ADDR_LOW = S1_INST[15:11];
			
			

			S1_PC_ADD4 = PC+4;
			S1_INST = IF_INST;
		end
        end


endmodule