data/full_repos/permissive/117026779/src/VGA.v
1: b"%Error: data/full_repos/permissive/117026779/src/VGA.v:93: syntax error, unexpected '(', expecting IDENTIFIER\n    .clk(clk),\n    ^\n%Error: Exiting due to 1 error(s)\n"
module PixelClock(
    input wire clk100Mhz,
    input wire rst,
    output reg pclk
);



parameter FREQ_IN         = 100_000_000;
parameter FREQ_OUT        =  25_000_000;
parameter HOLD_TICK_COUNT = (FREQ_IN/FREQ_OUT)/2;



reg [15:0] count;












always @(posedge clk100Mhz or posedge rst)
begin
    if(rst)
    begin
        count = 0;
        pclk  = 0;
    end
    else
    begin
       count = count + 1;
       if(count == HOLD_TICK_COUNT)
       begin
          count = 0;
          pclk = !pclk;
       end
    end
end
endmodule
module PixelClock(
    input wire clk100Mhz,
    input wire rst,
    output reg pclk
);




parameter FREQ_IN         = 100_000_000;
parameter FREQ_OUT        =  25_000_000;
parameter HOLD_TICK_COUNT = (FREQ_IN/FREQ_OUT)/2;



reg [15:0] count;












always @(posedge clk100Mhz or posedge rst)
begin
    if(rst)
    begin
        count = 0;
        pclk  = 0;
    end
    else
    begin
       count = count + 1;
       if(count == HOLD_TICK_COUNT)
       begin
          count = 0;
          pclk = !pclk;
       end
    end
end
endmodule