data/full_repos/permissive/123075301/top_vga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/123075301/top_vga.v:66: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                 : ... In instance top_vga\n    RGB_reg = 2\'b0;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/123075301/top_vga.v:73: Cannot find file containing module: \'sync_module\'\n sync_module SYNC(  .pixel_clock(pixel_clk),\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123075301,data/full_repos/permissive/123075301/sync_module\n             data/full_repos/permissive/123075301,data/full_repos/permissive/123075301/sync_module.v\n             data/full_repos/permissive/123075301,data/full_repos/permissive/123075301/sync_module.sv\n             sync_module\n             sync_module.v\n             sync_module.sv\n             obj_dir/sync_module\n             obj_dir/sync_module.v\n             obj_dir/sync_module.sv\n%Error: data/full_repos/permissive/123075301/top_vga.v:82: Cannot find file containing module: \'welcome_text\'\n welcome_text WELCOME(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/123075301/top_vga.v:90: Cannot find file containing module: \'process_text\'\n process_text PROCESS(\n ^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module top_vga(		reset, 
							clk, 
							v_sync, 
							h_sync, 
							RGB,
							welcome_trig,
							print_line,
							data_temp_disp,
							q_val_op,
							i_val_op
							);

	input [5:0]print_line;
	input [23:0] data_temp_disp;
	input [48:0] q_val_op,i_val_op;

	input clk, reset;
	input welcome_trig;

	output v_sync, h_sync;
	output [2:0] RGB;
	
	wire video_on, blank;
	wire [9:0] pixel_x, pixel_y;
	
	reg pixel_clk = 1'b0;
	wire [2:0] rgb_welcome;
	wire [2:0] rgb_process;
	reg [2:0] RGB_reg;
	
	assign video_on = ~blank;
	always @ (posedge clk)
	begin
		pixel_clk = ~pixel_clk;
	end
	
	always @ (posedge clk)
	begin
	if (pixel_clk)
		begin
			if(welcome_trig== 1'b1)
				RGB_reg = rgb_welcome;
			else if(welcome_trig == 1'b0)
				RGB_reg = rgb_process;
			else 
				RGB_reg = 2'b0;
			end
	end
		
assign RGB = RGB_reg;	


	sync_module SYNC(		.pixel_clock(pixel_clk),
								.reset(reset),
								.h_synch(h_sync),
								.v_synch(v_sync),
								.blank(blank),
								.pixel_count(pixel_x),
								.line_count(pixel_y)
								);

	welcome_text WELCOME(
						.clk(clk),
						.pix_x(pixel_x), 
						.pix_y(pixel_y),
						.video_on(video_on),
						.text_rgb(rgb_welcome)
	);

	process_text PROCESS(
						.clk(clk),
						.pix_x(pixel_x), 
						.pix_y(pixel_y),
						.video_on(video_on),
						.text_rgb(rgb_process),
						.ip_device_on1(print_line[0]),
						.error_on1(print_line[1]),
						.value_enter_key_on1(print_line[2]),
						.value_enter_rot_on1(print_line[3]),
						.result_on1(print_line[4]),
						.keep_disp_msg1(print_line[5]),
						.data_temp_disp(data_temp_disp),
						.q_val_op(q_val_op),
						.i_val_op(i_val_op)
						);


endmodule
module top_vga(		reset, 
							clk, 
							v_sync, 
							h_sync, 
							RGB,
							welcome_trig,
							print_line,
							data_temp_disp,
							q_val_op,
							i_val_op
							);


	input [5:0]print_line;
	input [23:0] data_temp_disp;
	input [48:0] q_val_op,i_val_op;

	input clk, reset;
	input welcome_trig;

	output v_sync, h_sync;
	output [2:0] RGB;
	
	wire video_on, blank;
	wire [9:0] pixel_x, pixel_y;
	
	reg pixel_clk = 1'b0;
	wire [2:0] rgb_welcome;
	wire [2:0] rgb_process;
	reg [2:0] RGB_reg;
	
	assign video_on = ~blank;
	always @ (posedge clk)
	begin
		pixel_clk = ~pixel_clk;
	end
	
	always @ (posedge clk)
	begin
	if (pixel_clk)
		begin
			if(welcome_trig== 1'b1)
				RGB_reg = rgb_welcome;
			else if(welcome_trig == 1'b0)
				RGB_reg = rgb_process;
			else 
				RGB_reg = 2'b0;
			end
	end
		
assign RGB = RGB_reg;	


	sync_module SYNC(		.pixel_clock(pixel_clk),
								.reset(reset),
								.h_synch(h_sync),
								.v_synch(v_sync),
								.blank(blank),
								.pixel_count(pixel_x),
								.line_count(pixel_y)
								);

	welcome_text WELCOME(
						.clk(clk),
						.pix_x(pixel_x), 
						.pix_y(pixel_y),
						.video_on(video_on),
						.text_rgb(rgb_welcome)
	);

	process_text PROCESS(
						.clk(clk),
						.pix_x(pixel_x), 
						.pix_y(pixel_y),
						.video_on(video_on),
						.text_rgb(rgb_process),
						.ip_device_on1(print_line[0]),
						.error_on1(print_line[1]),
						.value_enter_key_on1(print_line[2]),
						.value_enter_rot_on1(print_line[3]),
						.result_on1(print_line[4]),
						.keep_disp_msg1(print_line[5]),
						.data_temp_disp(data_temp_disp),
						.q_val_op(q_val_op),
						.i_val_op(i_val_op)
						);


endmodule