data/full_repos/permissive/160895047/Register.v
data/verilator_xmls/a19a13c5-7796-4b8e-a92c-d8af07bfb86e.xml
module Register(
	CLOCK,
	D,
	Q
);
input CLOCK;
input [31:0] D;
output [31:0] Q;

wire CLOCK;
wire [31:0] D;
reg [31:0] Q;

always @ (negedge CLOCK)
begin
	Q <= D;
end
endmodule
module Register(
	CLOCK,
	D,
	Q
);

input CLOCK;
input [31:0] D;
output [31:0] Q;

wire CLOCK;
wire [31:0] D;
reg [31:0] Q;

always @ (negedge CLOCK)
begin
	Q <= D;
end
endmodule