data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v
 line:122: before: ";"
1: b'%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:122: Unsupported: event data types\nevent stimulus_ended;\n^~~~~\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:128: syntax error, unexpected \'@\'\n @(negedge reset_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:132: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0001; in_vld_i<=1\'b1; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0001; in_vld_i<=1\'b1; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:133: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0010;                                                                      #100 @(posedge clk_i);\n                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0010;                                                                      #100 @(posedge clk_i);\n                                                                                                   ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:134: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0100;                                                                      #100 @(posedge clk_i);\n                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0100;                                                                      #100 @(posedge clk_i);\n                                                                                                   ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:135: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b1000;                                                                      #100 @(posedge clk_i);\n                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b1000;                                                                      #100 @(posedge clk_i);\n                                                                                                   ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:138: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0000; in_vld_i<=1\'b1; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b1; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0000; in_vld_i<=1\'b1; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b1; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:139: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0000; in_vld_i<=1\'b1; out_rdy_i<=4\'b0000; drop_i<=1\'b0; should_drop_i<=1\'b1; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0000; in_vld_i<=1\'b1; out_rdy_i<=4\'b0000; drop_i<=1\'b0; should_drop_i<=1\'b1; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:142: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0001; in_vld_i<=1\'b1; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0001; in_vld_i<=1\'b1; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:143: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0011;                                                                      #100 @(posedge clk_i);\n                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0011;                                                                      #100 @(posedge clk_i);\n                                                                                                   ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:144: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0111;                                                                      #100 @(posedge clk_i);\n                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0111;                                                                      #100 @(posedge clk_i);\n                                                                                                   ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:145: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b1111;                                                                      #100 @(posedge clk_i);\n                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b1111;                                                                      #100 @(posedge clk_i);\n                                                                                                   ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:146: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b1110;                                                                      #100 @(posedge clk_i);\n                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b1110;                                                                      #100 @(posedge clk_i);\n                                                                                                   ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:147: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b1100;                                                                      #100 @(posedge clk_i);\n                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b1100;                                                                      #100 @(posedge clk_i);\n                                                                                                   ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:148: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b1000;                                                                      #100 @(posedge clk_i);\n                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b1000;                                                                      #100 @(posedge clk_i);\n                                                                                                   ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:151: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0001; in_vld_i<=1\'b1; out_rdy_i<=4\'b0001; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0001; in_vld_i<=1\'b1; out_rdy_i<=4\'b0001; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:152: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b0000;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b0000;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:153: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b0001;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b0001;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:154: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0010;             out_rdy_i<=4\'b0010;                                           #100 @(posedge clk_i);\n                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0010;             out_rdy_i<=4\'b0010;                                           #100 @(posedge clk_i);\n                                                                                                        ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:155: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b0000;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b0000;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:156: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b0010;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b0010;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:157: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0100;             out_rdy_i<=4\'b0100;                                           #100 @(posedge clk_i);\n                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0100;             out_rdy_i<=4\'b0100;                                           #100 @(posedge clk_i);\n                                                                                                        ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:158: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b0000;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b0000;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:159: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b0100;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b0100;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:160: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b1000;             out_rdy_i<=4\'b1000;                                           #100 @(posedge clk_i);\n                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b1000;             out_rdy_i<=4\'b1000;                                           #100 @(posedge clk_i);\n                                                                                                        ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:161: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b0000;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b0000;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:162: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b1000;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b1000;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:165: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b1111; in_vld_i<=1\'b1; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b1111; in_vld_i<=1\'b1; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:166: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b0000;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b0000;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:167: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:170: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b1111; in_vld_i<=1\'b1; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b1111; in_vld_i<=1\'b1; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:171: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b1110;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b1110;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:172: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:173: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b1111;             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b1111;             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                                        ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:174: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b1101;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b1101;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:175: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:176: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b1111;             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b1111;             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                                        ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:177: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b1011;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b1011;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:178: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:179: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b1111;             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b1111;             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                                        ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:180: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b0111;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b0111;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:181: syntax error, unexpected \'@\'\n                             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n                             out_rdy_i<=4\'b1111;                                           #100 @(posedge clk_i);\n                                                                                           ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:186: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0000; in_vld_i<=1\'b0; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0000; in_vld_i<=1\'b0; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:187: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0001; in_vld_i<=1\'b1; out_rdy_i<=4\'b0000; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000; @(posedge clk_i);\n                                                                                                                                 ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:188: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0001; in_vld_i<=1\'b1; out_rdy_i<=4\'b0000; drop_i<=1\'b0; should_drop_i<=1\'b1; outputs_to_drop_i<=4\'b0001; @(posedge clk_i);\n                                                                                                                                 ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:189: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0000; in_vld_i<=1\'b0; out_rdy_i<=4\'b0000; drop_i<=1\'b1; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000; @(posedge clk_i);\n                                                                                                                                 ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:190: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0000; in_vld_i<=1\'b0; out_rdy_i<=4\'b0000; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000; @(posedge clk_i);\n                                                                                                                                 ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:191: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0000; in_vld_i<=1\'b0; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000; @(posedge clk_i);\n                                                                                                                                 ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:197: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0000; in_vld_i<=1\'b0; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n in_output_select_i<=4\'b0000; in_vld_i<=1\'b0; out_rdy_i<=4\'b1111; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000;#100 @(posedge clk_i);\n                                                                                                                                ^\n%Error: data/full_repos/permissive/19591557/modules/switch/spio_switch_tb.v:198: syntax error, unexpected \'@\'\n in_output_select_i<=4\'b0001; in_vld_i<=1\'b1; out_rdy_i<=4\'b0000; drop_i<=1\'b0; should_drop_i<=1\'b0; outputs_to_drop_i<=4\'b0000; @(posedge clk_i);\n                                                                                                                                 ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
module spio_switch_tb;

localparam PKT_BITS = 72;

genvar i;

reg clk_i;
reg reset_i;


wire [PKT_BITS-1:0] in_data_i;
reg  [3:0]          in_output_select_i;
reg                 in_vld_i;
wire                in_rdy_i;


wire [(4*PKT_BITS)-1:0] out_data_bus_i;
wire [PKT_BITS-1:0]     out_data_i [3:0];
wire [3:0]              out_vld_i;
reg  [3:0]              out_rdy_i;


assign out_data_i[0] = out_data_bus_i[0*PKT_BITS+:PKT_BITS];
assign out_data_i[1] = out_data_bus_i[1*PKT_BITS+:PKT_BITS];
assign out_data_i[2] = out_data_bus_i[2*PKT_BITS+:PKT_BITS];
assign out_data_i[3] = out_data_bus_i[3*PKT_BITS+:PKT_BITS];


wire [3:0] blocked_outputs_i;
wire [3:0] selected_outputs_i;


reg drop_i;


wire [PKT_BITS-1:0] drop_data_i;
wire [3:0]          drop_outputs_i;
wire                drop_vld_i;






spio_switch #( .PKT_BITS(PKT_BITS)
             , .NUM_PORTS(4)
             )
spio_switch_i( .CLK_IN              (clk_i)
             , .RESET_IN            (reset_i)

             , .IN_DATA_IN          (in_data_i)
             , .IN_OUTPUT_SELECT_IN (in_output_select_i)
             , .IN_VLD_IN           (in_vld_i)
             , .IN_RDY_OUT          (in_rdy_i)

             , .OUT_DATA_OUT        (out_data_bus_i)
             , .OUT_VLD_OUT         (out_vld_i)
             , .OUT_RDY_IN          (out_rdy_i)

             , .BLOCKED_OUTPUTS_OUT (blocked_outputs_i)
             , .SELECTED_OUTPUTS_OUT(selected_outputs_i)
             , .DROP_IN             (drop_i)

             , .DROPPED_DATA_OUT    (drop_data_i)
             , .DROPPED_OUTPUTS_OUT (drop_outputs_i)
             , .DROPPED_VLD_OUT     (drop_vld_i)
             );






localparam CNTR_WIDTH = 16;


reg [CNTR_WIDTH-1:0] input_counter_i;


always @ (posedge clk_i, posedge reset_i)
	if (reset_i)
		input_counter_i <= 0;
	else
		if (in_vld_i && in_rdy_i)
				input_counter_i <= input_counter_i + 1;


reg       should_drop_i;
reg [3:0] outputs_to_drop_i;



assign in_data_i = { {(PKT_BITS-4-CNTR_WIDTH-4-1){1'b0}}
                   , should_drop_i
                   , outputs_to_drop_i
                   , input_counter_i
                   , in_output_select_i
                   };


`define OSEL  in_output_select_i
`define VLD   in_vld_i
`define RDY   out_rdy_i
`define DRP   drop_i
`define SHDRP should_drop_i
`define TODRP outputs_to_drop_i


`define TICK @(posedge clk_i)


`define MTICK #100 @(posedge clk_i)


event stimulus_ended;

initial
	begin

	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;
	@(negedge reset_i)
	`MTICK;
	

	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	`OSEL<=4'b0010;                                                                      `MTICK;
	`OSEL<=4'b0100;                                                                      `MTICK;
	`OSEL<=4'b1000;                                                                      `MTICK;
	

	`OSEL<=4'b0000; `VLD<=1'b1; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b1; `TODRP<=4'b0000;`MTICK;
	`OSEL<=4'b0000; `VLD<=1'b1; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b1; `TODRP<=4'b0000;`MTICK;
	

	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	`OSEL<=4'b0011;                                                                      `MTICK;
	`OSEL<=4'b0111;                                                                      `MTICK;
	`OSEL<=4'b1111;                                                                      `MTICK;
	`OSEL<=4'b1110;                                                                      `MTICK;
	`OSEL<=4'b1100;                                                                      `MTICK;
	`OSEL<=4'b1000;                                                                      `MTICK;
	

	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b0001; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	                            `RDY<=4'b0000;                                           `MTICK;
	                            `RDY<=4'b0001;                                           `MTICK;
	`OSEL<=4'b0010;             `RDY<=4'b0010;                                           `MTICK;
	                            `RDY<=4'b0000;                                           `MTICK;
	                            `RDY<=4'b0010;                                           `MTICK;
	`OSEL<=4'b0100;             `RDY<=4'b0100;                                           `MTICK;
	                            `RDY<=4'b0000;                                           `MTICK;
	                            `RDY<=4'b0100;                                           `MTICK;
	`OSEL<=4'b1000;             `RDY<=4'b1000;                                           `MTICK;
	                            `RDY<=4'b0000;                                           `MTICK;
	                            `RDY<=4'b1000;                                           `MTICK;
	

	`OSEL<=4'b1111; `VLD<=1'b1; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	                            `RDY<=4'b0000;                                           `MTICK;
	                            `RDY<=4'b1111;                                           `MTICK;
	

	`OSEL<=4'b1111; `VLD<=1'b1; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	                            `RDY<=4'b1110;                                           `MTICK;
	                            `RDY<=4'b1111;                                           `MTICK;
	`OSEL<=4'b1111;             `RDY<=4'b1111;                                           `MTICK;
	                            `RDY<=4'b1101;                                           `MTICK;
	                            `RDY<=4'b1111;                                           `MTICK;
	`OSEL<=4'b1111;             `RDY<=4'b1111;                                           `MTICK;
	                            `RDY<=4'b1011;                                           `MTICK;
	                            `RDY<=4'b1111;                                           `MTICK;
	`OSEL<=4'b1111;             `RDY<=4'b1111;                                           `MTICK;
	                            `RDY<=4'b0111;                                           `MTICK;
	                            `RDY<=4'b1111;                                           `MTICK;
	



	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b1; `TODRP<=4'b0001; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b0000; `DRP<=1'b1; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	




	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b1111; `VLD<=1'b1; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b1; `TODRP<=4'b0001; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b0000; `DRP<=1'b1; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	

	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	

	->stimulus_ended;
	#0
	$finish;
	end








reg packet_expected [3:0][(1<<CNTR_WIDTH)-1:0];




reg [4:0] drop_expected [(1<<CNTR_WIDTH)-1:0];


initial
	begin : packet_expected_init
		integer j; integer k;
		

		for (k = 0; k < 4; k = k + 1)
			for (j = 0; j < (1<<CNTR_WIDTH); j = j + 1)
				packet_expected[k][j] = 0;
		

		for (j = 0; j < (1<<CNTR_WIDTH); j = j + 1)
			drop_expected[j] = 0;
		
		
	end


initial
	begin : packet_expected_final_check
		integer j; integer k;
		
		@(stimulus_ended);
		

		for (k = 0; k < 4; k = k + 1)
			for (j = 0; j < (1<<CNTR_WIDTH); j = j + 1)
				if (packet_expected[k][j] != 0)
					$display( "Time=%08d: ERROR: Packet with number %x was never delivered to output %x."
					        , $time, j, k);
		

		for (j = 0; j < (1<<CNTR_WIDTH); j = j + 1)
			drop_expected[j] = 0;
			if (drop_expected[j][4] != 0)
				$display( "Time=%08d: ERROR: Packet with number %x was never dropped from output %x."
				        , $time, j, drop_expected[j][3:0]);
			else if (drop_expected[j][3:0] != 0)
				$display( "Time=%08d: ERROR: Packet with number %x was never dropped from some outputs %x."
				        , $time, j, drop_expected[j][3:0]);
		
		
	end


generate for (i = 0; i < 4; i = i + 1)
	begin : output_checker

		always @ (posedge clk_i, posedge reset_i)
			if (!reset_i && in_vld_i && in_rdy_i && ( in_output_select_i[i]
			                                        & !outputs_to_drop_i[i]
			                                        & !(should_drop_i && outputs_to_drop_i == 4'h0)
			                                        ))
				packet_expected[i][input_counter_i] <= 1'b1;
		

		always @ (posedge clk_i, posedge reset_i)
			if (!reset_i && out_vld_i[i] && out_rdy_i[i])
				begin

					if (out_data_i[i][i] != 1'b1)
						$display( "Time=%08d: ERROR: Packet %018x unexpected on output %x."
						        , $time
						        , out_data_i[i]
						        , i
						        );
					

					if (out_data_i[i][i+CNTR_WIDTH+4] == 1'b1)
						$display( "Time=%08d: ERROR: Packet %018x at output %x should have been dropped."
						        , $time
						        , out_data_i[i]
						        , i
						        );
					

					if (packet_expected[i][out_data_i[i][4+:CNTR_WIDTH]] != 1'b1)
						$display( "Time=%08d: ERROR: Unexpected packet %018x with number %x at output %x."
						        , $time
						        , out_data_i[i]
						        , out_data_i[i][4+:CNTR_WIDTH]
						        , i
						        );
					

					packet_expected[i][out_data_i[i][4+:CNTR_WIDTH]] <= 1'b0;
				end
	end
endgenerate


always @ (posedge clk_i, posedge reset_i)
	if (!reset_i && in_vld_i && in_rdy_i && should_drop_i)
		drop_expected[input_counter_i] <= outputs_to_drop_i ? outputs_to_drop_i : 5'b10000;


always @ (posedge clk_i, posedge reset_i)
	if (!reset_i && drop_vld_i)
		begin

			if (drop_data_i[4+CNTR_WIDTH+4] != 1'b1)
				$display( "Time=%08d: ERROR: Packet %018x should not have been dropped."
				        , $time
				        , drop_data_i
				        );
			


			if (drop_data_i[CNTR_WIDTH+4+:4] != drop_outputs_i)
				$display( "Time=%08d: ERROR: Packet %018x dropped due to outputs %x, should have been %x."
				        , $time
				        , drop_data_i
				        , drop_outputs_i
				        , drop_data_i[CNTR_WIDTH+4+:4]
				        );
			

			if (!( ( (drop_expected[drop_data_i[4+:CNTR_WIDTH]] == 5'b10000)
			         && drop_outputs_i == 4'h0)
			     ||( (drop_expected[drop_data_i[4+:CNTR_WIDTH]][3:0] == drop_outputs_i)
			         && drop_outputs_i != 4'h0)
			     ))
				$display( "Time=%08d: ERROR: Unexpected packet dropped %018x with number %x."
				        , $time
				        , drop_data_i
				        , drop_data_i[4+:CNTR_WIDTH]
				        );
			

			drop_expected[drop_data_i[4+:CNTR_WIDTH]][4] <= 1'b0;
			drop_expected[drop_data_i[4+:CNTR_WIDTH]][3:0] <=
				drop_expected[drop_data_i[4+:CNTR_WIDTH]][3:0] & ~drop_outputs_i;
		end











initial
	begin
	clk_i = 1'b0;
	forever
		#5 clk_i = ~clk_i;
	end



initial
	begin
		reset_i <= 1'b1;
		#100
		reset_i <= 1'b0;
	end


endmodule
module spio_switch_tb;


localparam PKT_BITS = 72;

genvar i;

reg clk_i;
reg reset_i;


wire [PKT_BITS-1:0] in_data_i;
reg  [3:0]          in_output_select_i;
reg                 in_vld_i;
wire                in_rdy_i;


wire [(4*PKT_BITS)-1:0] out_data_bus_i;
wire [PKT_BITS-1:0]     out_data_i [3:0];
wire [3:0]              out_vld_i;
reg  [3:0]              out_rdy_i;


assign out_data_i[0] = out_data_bus_i[0*PKT_BITS+:PKT_BITS];
assign out_data_i[1] = out_data_bus_i[1*PKT_BITS+:PKT_BITS];
assign out_data_i[2] = out_data_bus_i[2*PKT_BITS+:PKT_BITS];
assign out_data_i[3] = out_data_bus_i[3*PKT_BITS+:PKT_BITS];


wire [3:0] blocked_outputs_i;
wire [3:0] selected_outputs_i;


reg drop_i;


wire [PKT_BITS-1:0] drop_data_i;
wire [3:0]          drop_outputs_i;
wire                drop_vld_i;






spio_switch #( .PKT_BITS(PKT_BITS)
             , .NUM_PORTS(4)
             )
spio_switch_i( .CLK_IN              (clk_i)
             , .RESET_IN            (reset_i)

             , .IN_DATA_IN          (in_data_i)
             , .IN_OUTPUT_SELECT_IN (in_output_select_i)
             , .IN_VLD_IN           (in_vld_i)
             , .IN_RDY_OUT          (in_rdy_i)

             , .OUT_DATA_OUT        (out_data_bus_i)
             , .OUT_VLD_OUT         (out_vld_i)
             , .OUT_RDY_IN          (out_rdy_i)

             , .BLOCKED_OUTPUTS_OUT (blocked_outputs_i)
             , .SELECTED_OUTPUTS_OUT(selected_outputs_i)
             , .DROP_IN             (drop_i)

             , .DROPPED_DATA_OUT    (drop_data_i)
             , .DROPPED_OUTPUTS_OUT (drop_outputs_i)
             , .DROPPED_VLD_OUT     (drop_vld_i)
             );






localparam CNTR_WIDTH = 16;


reg [CNTR_WIDTH-1:0] input_counter_i;


always @ (posedge clk_i, posedge reset_i)
	if (reset_i)
		input_counter_i <= 0;
	else
		if (in_vld_i && in_rdy_i)
				input_counter_i <= input_counter_i + 1;


reg       should_drop_i;
reg [3:0] outputs_to_drop_i;



assign in_data_i = { {(PKT_BITS-4-CNTR_WIDTH-4-1){1'b0}}
                   , should_drop_i
                   , outputs_to_drop_i
                   , input_counter_i
                   , in_output_select_i
                   };


`define OSEL  in_output_select_i
`define VLD   in_vld_i
`define RDY   out_rdy_i
`define DRP   drop_i
`define SHDRP should_drop_i
`define TODRP outputs_to_drop_i


`define TICK @(posedge clk_i)


`define MTICK #100 @(posedge clk_i)


event stimulus_ended;

initial
	begin

	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;
	@(negedge reset_i)
	`MTICK;
	

	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	`OSEL<=4'b0010;                                                                      `MTICK;
	`OSEL<=4'b0100;                                                                      `MTICK;
	`OSEL<=4'b1000;                                                                      `MTICK;
	

	`OSEL<=4'b0000; `VLD<=1'b1; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b1; `TODRP<=4'b0000;`MTICK;
	`OSEL<=4'b0000; `VLD<=1'b1; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b1; `TODRP<=4'b0000;`MTICK;
	

	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	`OSEL<=4'b0011;                                                                      `MTICK;
	`OSEL<=4'b0111;                                                                      `MTICK;
	`OSEL<=4'b1111;                                                                      `MTICK;
	`OSEL<=4'b1110;                                                                      `MTICK;
	`OSEL<=4'b1100;                                                                      `MTICK;
	`OSEL<=4'b1000;                                                                      `MTICK;
	

	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b0001; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	                            `RDY<=4'b0000;                                           `MTICK;
	                            `RDY<=4'b0001;                                           `MTICK;
	`OSEL<=4'b0010;             `RDY<=4'b0010;                                           `MTICK;
	                            `RDY<=4'b0000;                                           `MTICK;
	                            `RDY<=4'b0010;                                           `MTICK;
	`OSEL<=4'b0100;             `RDY<=4'b0100;                                           `MTICK;
	                            `RDY<=4'b0000;                                           `MTICK;
	                            `RDY<=4'b0100;                                           `MTICK;
	`OSEL<=4'b1000;             `RDY<=4'b1000;                                           `MTICK;
	                            `RDY<=4'b0000;                                           `MTICK;
	                            `RDY<=4'b1000;                                           `MTICK;
	

	`OSEL<=4'b1111; `VLD<=1'b1; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	                            `RDY<=4'b0000;                                           `MTICK;
	                            `RDY<=4'b1111;                                           `MTICK;
	

	`OSEL<=4'b1111; `VLD<=1'b1; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	                            `RDY<=4'b1110;                                           `MTICK;
	                            `RDY<=4'b1111;                                           `MTICK;
	`OSEL<=4'b1111;             `RDY<=4'b1111;                                           `MTICK;
	                            `RDY<=4'b1101;                                           `MTICK;
	                            `RDY<=4'b1111;                                           `MTICK;
	`OSEL<=4'b1111;             `RDY<=4'b1111;                                           `MTICK;
	                            `RDY<=4'b1011;                                           `MTICK;
	                            `RDY<=4'b1111;                                           `MTICK;
	`OSEL<=4'b1111;             `RDY<=4'b1111;                                           `MTICK;
	                            `RDY<=4'b0111;                                           `MTICK;
	                            `RDY<=4'b1111;                                           `MTICK;
	



	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b1; `TODRP<=4'b0001; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b0000; `DRP<=1'b1; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	




	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	`OSEL<=4'b0001; `VLD<=1'b1; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b1111; `VLD<=1'b1; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b1; `TODRP<=4'b0001; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b0000; `DRP<=1'b1; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b0000; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000; `TICK;
	

	`OSEL<=4'b0000; `VLD<=1'b0; `RDY<=4'b1111; `DRP<=1'b0; `SHDRP<=1'b0; `TODRP<=4'b0000;`MTICK;
	

	->stimulus_ended;
	#0
	$finish;
	end








reg packet_expected [3:0][(1<<CNTR_WIDTH)-1:0];




reg [4:0] drop_expected [(1<<CNTR_WIDTH)-1:0];


initial
	begin : packet_expected_init
		integer j; integer k;
		

		for (k = 0; k < 4; k = k + 1)
			for (j = 0; j < (1<<CNTR_WIDTH); j = j + 1)
				packet_expected[k][j] = 0;
		

		for (j = 0; j < (1<<CNTR_WIDTH); j = j + 1)
			drop_expected[j] = 0;
		
		
	end


initial
	begin : packet_expected_final_check
		integer j; integer k;
		
		@(stimulus_ended);
		

		for (k = 0; k < 4; k = k + 1)
			for (j = 0; j < (1<<CNTR_WIDTH); j = j + 1)
				if (packet_expected[k][j] != 0)
					$display( "Time=%08d: ERROR: Packet with number %x was never delivered to output %x."
					        , $time, j, k);
		

		for (j = 0; j < (1<<CNTR_WIDTH); j = j + 1)
			drop_expected[j] = 0;
			if (drop_expected[j][4] != 0)
				$display( "Time=%08d: ERROR: Packet with number %x was never dropped from output %x."
				        , $time, j, drop_expected[j][3:0]);
			else if (drop_expected[j][3:0] != 0)
				$display( "Time=%08d: ERROR: Packet with number %x was never dropped from some outputs %x."
				        , $time, j, drop_expected[j][3:0]);
		
		
	end


generate for (i = 0; i < 4; i = i + 1)
	begin : output_checker

		always @ (posedge clk_i, posedge reset_i)
			if (!reset_i && in_vld_i && in_rdy_i && ( in_output_select_i[i]
			                                        & !outputs_to_drop_i[i]
			                                        & !(should_drop_i && outputs_to_drop_i == 4'h0)
			                                        ))
				packet_expected[i][input_counter_i] <= 1'b1;
		

		always @ (posedge clk_i, posedge reset_i)
			if (!reset_i && out_vld_i[i] && out_rdy_i[i])
				begin

					if (out_data_i[i][i] != 1'b1)
						$display( "Time=%08d: ERROR: Packet %018x unexpected on output %x."
						        , $time
						        , out_data_i[i]
						        , i
						        );
					

					if (out_data_i[i][i+CNTR_WIDTH+4] == 1'b1)
						$display( "Time=%08d: ERROR: Packet %018x at output %x should have been dropped."
						        , $time
						        , out_data_i[i]
						        , i
						        );
					

					if (packet_expected[i][out_data_i[i][4+:CNTR_WIDTH]] != 1'b1)
						$display( "Time=%08d: ERROR: Unexpected packet %018x with number %x at output %x."
						        , $time
						        , out_data_i[i]
						        , out_data_i[i][4+:CNTR_WIDTH]
						        , i
						        );
					

					packet_expected[i][out_data_i[i][4+:CNTR_WIDTH]] <= 1'b0;
				end
	end
endgenerate


always @ (posedge clk_i, posedge reset_i)
	if (!reset_i && in_vld_i && in_rdy_i && should_drop_i)
		drop_expected[input_counter_i] <= outputs_to_drop_i ? outputs_to_drop_i : 5'b10000;


always @ (posedge clk_i, posedge reset_i)
	if (!reset_i && drop_vld_i)
		begin

			if (drop_data_i[4+CNTR_WIDTH+4] != 1'b1)
				$display( "Time=%08d: ERROR: Packet %018x should not have been dropped."
				        , $time
				        , drop_data_i
				        );
			


			if (drop_data_i[CNTR_WIDTH+4+:4] != drop_outputs_i)
				$display( "Time=%08d: ERROR: Packet %018x dropped due to outputs %x, should have been %x."
				        , $time
				        , drop_data_i
				        , drop_outputs_i
				        , drop_data_i[CNTR_WIDTH+4+:4]
				        );
			

			if (!( ( (drop_expected[drop_data_i[4+:CNTR_WIDTH]] == 5'b10000)
			         && drop_outputs_i == 4'h0)
			     ||( (drop_expected[drop_data_i[4+:CNTR_WIDTH]][3:0] == drop_outputs_i)
			         && drop_outputs_i != 4'h0)
			     ))
				$display( "Time=%08d: ERROR: Unexpected packet dropped %018x with number %x."
				        , $time
				        , drop_data_i
				        , drop_data_i[4+:CNTR_WIDTH]
				        );
			

			drop_expected[drop_data_i[4+:CNTR_WIDTH]][4] <= 1'b0;
			drop_expected[drop_data_i[4+:CNTR_WIDTH]][3:0] <=
				drop_expected[drop_data_i[4+:CNTR_WIDTH]][3:0] & ~drop_outputs_i;
		end











initial
	begin
	clk_i = 1'b0;
	forever
		#5 clk_i = ~clk_i;
	end



initial
	begin
		reset_i <= 1'b1;
		#100
		reset_i <= 1'b0;
	end


endmodule