data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/ControlUnit.v
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1: b"%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/ControlUnit.v:53: Cannot find file containing module: 'DFlipFlop'\n    DFlipFlop dFlipFlop(RST, CLK, InputState, OutputState);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new,data/full_repos/permissive/139299103/DFlipFlop\n             data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new,data/full_repos/permissive/139299103/DFlipFlop.v\n             data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new,data/full_repos/permissive/139299103/DFlipFlop.sv\n             DFlipFlop\n             DFlipFlop.v\n             DFlipFlop.sv\n             obj_dir/DFlipFlop\n             obj_dir/DFlipFlop.v\n             obj_dir/DFlipFlop.sv\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/ControlUnit.v:55: Cannot find file containing module: 'NextState'\n    NextState nextState(OutputState, opcode, InputState);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/ControlUnit.v:57: Cannot find file containing module: 'OutputFunc'\n   OutputFunc outputFunc(\n   ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module ControlUnit(
zero,  RST,  CLK, mRD,  mWR, DBDataSrc,
ExtSel, PCWre, IRWre, InsMemRW, opcode, WrRegDSrc,
RegDst,  RegWre,  ALUOp,  PCSrc, sign,  ALUSrcA, ALUSrcB 
);
        
    input  zero; 
    input  RST;
    input  CLK;
    output  mRD;
    output mWR; 
    output  DBDataSrc;
    output  ExtSel;
    output  PCWre;
    output IRWre;
    output  InsMemRW;
    input  [5:0] opcode; 
    output  WrRegDSrc; 
    output  [1:0]RegDst;
    output RegWre;
    output  [2:0]ALUOp;
    output  [1:0]PCSrc;
    input sign;
    output  ALUSrcA;
    output  ALUSrcB;
      
    wire [2:0] InputState;
    wire [2:0] OutputState;
   

    DFlipFlop dFlipFlop(RST, CLK, InputState, OutputState);

    NextState nextState(OutputState, opcode, InputState);

   OutputFunc outputFunc(
        opcode, zero, sign, OutputState,DBDataSrc, mWR, mRD,ExtSel, PCWre,
        IRWre, InsMemRW, WrRegDSrc, RegDst, RegWre, ALUOp, PCSrc, ALUSrcA, ALUSrcB  
    );
endmodule
module ControlUnit(
zero,  RST,  CLK, mRD,  mWR, DBDataSrc,
ExtSel, PCWre, IRWre, InsMemRW, opcode, WrRegDSrc,
RegDst,  RegWre,  ALUOp,  PCSrc, sign,  ALUSrcA, ALUSrcB 
);

        
    input  zero; 
    input  RST;
    input  CLK;
    output  mRD;
    output mWR; 
    output  DBDataSrc;
    output  ExtSel;
    output  PCWre;
    output IRWre;
    output  InsMemRW;
    input  [5:0] opcode; 
    output  WrRegDSrc; 
    output  [1:0]RegDst;
    output RegWre;
    output  [2:0]ALUOp;
    output  [1:0]PCSrc;
    input sign;
    output  ALUSrcA;
    output  ALUSrcB;
      
    wire [2:0] InputState;
    wire [2:0] OutputState;
   

    DFlipFlop dFlipFlop(RST, CLK, InputState, OutputState);

    NextState nextState(OutputState, opcode, InputState);

   OutputFunc outputFunc(
        opcode, zero, sign, OutputState,DBDataSrc, mWR, mRD,ExtSel, PCWre,
        IRWre, InsMemRW, WrRegDSrc, RegDst, RegWre, ALUOp, PCSrc, ALUSrcA, ALUSrcB  
    );
endmodule