data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_stop_time)\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:137: Unsupported: Ignoring delay on this delayed statement.\n      #25241995.176\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:144: Unsupported: Ignoring delay on this delayed statement.\n      #20.176\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:146: Unsupported: Ignoring delay on this delayed statement.\n      #25098147\n      ^\n%Error: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:156: Too many digits for 32 bit number: 25241995176\n        ... As that number was unsized (\'d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n        ... Suggest adding a size to it.\n    #25241995176 $finish;\n     ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:156: Unsupported: Ignoring delay on this delayed statement.\n    #25241995176 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:193: Unsupported: Ignoring delay on this delayed statement.\n      #((jRise + maxLH - minLH));\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:203: Unsupported: Ignoring delay on this delayed statement.\n      #((jFall + maxHL - minHL));\n      ^\n%Error: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:210: syntax error, unexpected \'@\'\n    @(posedge tb_status[0])\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:233: Unsupported: Ignoring delay on this delayed statement.\n        #(offset + (minLH - jRise/2))\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:240: Unsupported: Ignoring delay on this delayed statement.\n        #((jRise/2 + maxLH) + (offset))\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:242: Unsupported: Ignoring delay on this delayed statement.\n        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2)))\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:245: Unsupported: Ignoring delay on this delayed statement.\n        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2)))\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:252: Unsupported: Ignoring delay on this delayed statement.\n        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2)))\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:255: Unsupported: Ignoring delay on this delayed statement.\n        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2)))\n        ^\n%Error: data/full_repos/permissive/174263347/JamaOneChip/stimulus/egavga.v:286: syntax error, unexpected $end, expecting \')\'\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module stimulus(aMem,dMem,clk,hsync,vsync,ega,nReset,csync,iVideo,oVideo,relay,nCs,nOe,nWe);

input [15:0] aMem;
input [7:0] dMem;
output  clk;
output  hsync;
output  vsync;
output  ega;
reg  ega;
output  nReset;
reg  nReset;
input  csync;
output  iVideo;
reg  iVideo;
input  oVideo;
input  relay;
input  nCs;
input  nOe;
input  nWe;


wire [1:0] tb_status;
reg [1:0] tb_status_driver;
assign tb_status = tb_status_driver;

parameter tb_stop_time = 2.5242e+007;


real vsync_JFall;
real vsync_JRise;
real vsync_MaxHL;
real vsync_MaxLH;
real vsync_MinHL;
real vsync_MinLH;
real vsync_Duty;
real vsync_Period;
real vsync_Offset;
real hsync_JFall;
real hsync_JRise;
real hsync_MaxHL;
real hsync_MaxLH;
real hsync_MinHL;
real hsync_MinLH;
real hsync_Duty;
real hsync_Period;
real hsync_Offset;
real clk_JFall;
real clk_JRise;
real clk_MaxHL;
real clk_MaxLH;
real clk_MinHL;
real clk_MinLH;
real clk_Duty;
real clk_Period;
real clk_Offset;

task AssignExpressions;
  begin
  vsync_JFall = 0.0;
  vsync_JRise = 0.0;
  vsync_MaxHL = 0.0;
  vsync_MaxLH = 0.0;
  vsync_MinHL = 0.0;
  vsync_MinLH = 0.0;
  vsync_Duty = 99.4;
  vsync_Period = 16666666.67;
  vsync_Offset = 0.0;
  hsync_JFall = 0.0;
  hsync_JRise = 0.0;
  hsync_MaxHL = 0.0;
  hsync_MaxLH = 0.0;
  hsync_MinHL = 0.0;
  hsync_MinLH = 0.0;
  hsync_Duty = 99.0;
  hsync_Period = 32000.0;
  hsync_Offset = 0.0;
  clk_JFall = 0.0;
  clk_JRise = 0.0;
  clk_MaxHL = 0.0;
  clk_MaxLH = 0.0;
  clk_MinHL = 0.0;
  clk_MinLH = 0.0;
  clk_Duty = 50.0;
  clk_Period = 40.0;
  clk_Offset = 0.0;
  end
endtask

initial
  begin
  AssignExpressions;
  tb_status_driver <= 1'b1;
  #(tb_stop_time)
  tb_status_driver <= 1'b0;
  end

tb_clock_minmax #(1) tb_clk(tb_status[1:0],
                            clk,
                            $realtobits(clk_Offset),
                            $realtobits(clk_Period),
                            $realtobits(clk_Duty),
                            $realtobits(clk_MinLH),
                            $realtobits(clk_MaxLH),
                            $realtobits(clk_MinHL),
                            $realtobits(clk_MaxHL),
                            $realtobits(clk_JRise),
                            $realtobits(clk_JFall));

tb_clock_minmax #(1) tb_hsync(tb_status[1:0],
                              hsync,
                              $realtobits(hsync_Offset),
                              $realtobits(hsync_Period),
                              $realtobits(hsync_Duty),
                              $realtobits(hsync_MinLH),
                              $realtobits(hsync_MaxLH),
                              $realtobits(hsync_MinHL),
                              $realtobits(hsync_MaxHL),
                              $realtobits(hsync_JRise),
                              $realtobits(hsync_JFall));

tb_clock_minmax #(1) tb_vsync(tb_status[1:0],
                              vsync,
                              $realtobits(vsync_Offset),
                              $realtobits(vsync_Period),
                              $realtobits(vsync_Duty),
                              $realtobits(vsync_MinLH),
                              $realtobits(vsync_MaxLH),
                              $realtobits(vsync_MinHL),
                              $realtobits(vsync_MaxHL),
                              $realtobits(vsync_JRise),
                              $realtobits(vsync_JFall));

initial
  begin
        ega = 1'b0;
      #25241995.176
        ;
  end

initial
  begin
        nReset = 1'b0;
      #20.176
        nReset = 1'b1;
      #25098147
        ;
  end

initial
  begin
        iVideo = 1'bz;
  end

  initial
    #25241995176 $finish;

endmodule
module stimulus(aMem,dMem,clk,hsync,vsync,ega,nReset,csync,iVideo,oVideo,relay,nCs,nOe,nWe);


input [15:0] aMem;
input [7:0] dMem;
output  clk;
output  hsync;
output  vsync;
output  ega;
reg  ega;
output  nReset;
reg  nReset;
input  csync;
output  iVideo;
reg  iVideo;
input  oVideo;
input  relay;
input  nCs;
input  nOe;
input  nWe;


wire [1:0] tb_status;
reg [1:0] tb_status_driver;
assign tb_status = tb_status_driver;

parameter tb_stop_time = 2.5242e+007;


real vsync_JFall;
real vsync_JRise;
real vsync_MaxHL;
real vsync_MaxLH;
real vsync_MinHL;
real vsync_MinLH;
real vsync_Duty;
real vsync_Period;
real vsync_Offset;
real hsync_JFall;
real hsync_JRise;
real hsync_MaxHL;
real hsync_MaxLH;
real hsync_MinHL;
real hsync_MinLH;
real hsync_Duty;
real hsync_Period;
real hsync_Offset;
real clk_JFall;
real clk_JRise;
real clk_MaxHL;
real clk_MaxLH;
real clk_MinHL;
real clk_MinLH;
real clk_Duty;
real clk_Period;
real clk_Offset;

task AssignExpressions;
  begin
  vsync_JFall = 0.0;
  vsync_JRise = 0.0;
  vsync_MaxHL = 0.0;
  vsync_MaxLH = 0.0;
  vsync_MinHL = 0.0;
  vsync_MinLH = 0.0;
  vsync_Duty = 99.4;
  vsync_Period = 16666666.67;
  vsync_Offset = 0.0;
  hsync_JFall = 0.0;
  hsync_JRise = 0.0;
  hsync_MaxHL = 0.0;
  hsync_MaxLH = 0.0;
  hsync_MinHL = 0.0;
  hsync_MinLH = 0.0;
  hsync_Duty = 99.0;
  hsync_Period = 32000.0;
  hsync_Offset = 0.0;
  clk_JFall = 0.0;
  clk_JRise = 0.0;
  clk_MaxHL = 0.0;
  clk_MaxLH = 0.0;
  clk_MinHL = 0.0;
  clk_MinLH = 0.0;
  clk_Duty = 50.0;
  clk_Period = 40.0;
  clk_Offset = 0.0;
  end
endtask

initial
  begin
  AssignExpressions;
  tb_status_driver <= 1'b1;
  #(tb_stop_time)
  tb_status_driver <= 1'b0;
  end

tb_clock_minmax #(1) tb_clk(tb_status[1:0],
                            clk,
                            $realtobits(clk_Offset),
                            $realtobits(clk_Period),
                            $realtobits(clk_Duty),
                            $realtobits(clk_MinLH),
                            $realtobits(clk_MaxLH),
                            $realtobits(clk_MinHL),
                            $realtobits(clk_MaxHL),
                            $realtobits(clk_JRise),
                            $realtobits(clk_JFall));

tb_clock_minmax #(1) tb_hsync(tb_status[1:0],
                              hsync,
                              $realtobits(hsync_Offset),
                              $realtobits(hsync_Period),
                              $realtobits(hsync_Duty),
                              $realtobits(hsync_MinLH),
                              $realtobits(hsync_MaxLH),
                              $realtobits(hsync_MinHL),
                              $realtobits(hsync_MaxHL),
                              $realtobits(hsync_JRise),
                              $realtobits(hsync_JFall));

tb_clock_minmax #(1) tb_vsync(tb_status[1:0],
                              vsync,
                              $realtobits(vsync_Offset),
                              $realtobits(vsync_Period),
                              $realtobits(vsync_Duty),
                              $realtobits(vsync_MinLH),
                              $realtobits(vsync_MaxLH),
                              $realtobits(vsync_MinHL),
                              $realtobits(vsync_MaxHL),
                              $realtobits(vsync_JRise),
                              $realtobits(vsync_JFall));

initial
  begin
        ega = 1'b0;
      #25241995.176
        ;
  end

initial
  begin
        nReset = 1'b0;
      #20.176
        nReset = 1'b1;
      #25098147
        ;
  end

initial
  begin
        iVideo = 1'bz;
  end

  initial
    #25241995176 $finish;

endmodule