data/full_repos/permissive/10136357/hardware/src/inst_decoder.v
1: b'%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n             consts.vh\n             consts.vh.v\n             consts.vh.sv\n             obj_dir/consts.vh\n             obj_dir/consts.vh.v\n             obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: Define or directive not defined: \'`STR_LEN\'\n output reg [(`STR_LEN * 8) - 1:0] str,\n              ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n output reg [(`STR_LEN * 8) - 1:0] str,\n                       ^\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:174: syntax error, unexpected type, expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] type;\n           ^~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:187: syntax error, unexpected IDENTIFIER\n reg_decoder r1(wd_s, wd);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:200: Define or directive not defined: \'`OPCODE_OP\'\n   `OPCODE_OP:\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:201: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] = \n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:204: Define or directive not defined: \'`OPCODE_OP_IMM\'\n   `OPCODE_OP_IMM: begin\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:206: Define or directive not defined: \'`STR_LEN\'\n     str[(`STR_LEN - 8) * 8 - 1:0] = \n          ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:209: Define or directive not defined: \'`STR_LEN\'\n     str[(`STR_LEN - 8) * 8 - 1:0] = "";\n          ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:212: Define or directive not defined: \'`OPCODE_LUI\'\n   `OPCODE_LUI:\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:213: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_J\'\n   `OPCODE_J, `OPCODE_JAL:\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_JAL\'\n   `OPCODE_J, `OPCODE_JAL:\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:217: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:220: Define or directive not defined: \'`OPCODE_JALR\'\n   `OPCODE_JALR:\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:222: Define or directive not defined: \'`STR_LEN\'\n     str[(`STR_LEN - 8) * 8 - 1:0] =\n          ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:225: Define or directive not defined: \'`STR_LEN\'\n     str[(`STR_LEN - 8) * 8 - 1:0] = "";\n          ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:227: Define or directive not defined: \'`OPCODE_BRANCH\'\n   `OPCODE_BRANCH:\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:228: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:231: Define or directive not defined: \'`OPCODE_LOAD\'\n   `OPCODE_LOAD:\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:232: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:235: Define or directive not defined: \'`OPCODE_STORE\'\n   `OPCODE_STORE:\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:236: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:239: Define or directive not defined: \'`OPCODE_PCR\'\n   `OPCODE_PCR:\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:240: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:244: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] = "";\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:250: Define or directive not defined: \'`OPCODE_OP\'\n   `OPCODE_OP:\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:253: Define or directive not defined: \'`F3_MUL\'\n      `F3_MUL:    op_s = "mul     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:254: Define or directive not defined: \'`F3_MULH\'\n      `F3_MULH:   op_s = "mulh    ";\n      ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:255: Define or directive not defined: \'`F3_MULHSU\'\n      `F3_MULHSU: op_s = "mulhsu  ";\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:256: Define or directive not defined: \'`F3_MULHU\'\n      `F3_MULHU:  op_s = "mulhu   ";\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:257: Define or directive not defined: \'`F3_DIV\'\n      `F3_DIV:    op_s = "div     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:258: Define or directive not defined: \'`F3_DIVU\'\n      `F3_DIVU:   op_s = "divu    ";\n      ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:259: Define or directive not defined: \'`F3_REM\'\n      `F3_REM:    op_s = "rem     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:260: Define or directive not defined: \'`F3_REMU\'\n      `F3_REMU:   op_s = "remu    ";\n      ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:265: Define or directive not defined: \'`F3_ADD\'\n      `F3_ADD:  op_s = inst[16] ? "sub     " : "add     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:266: Define or directive not defined: \'`F3_SLL\'\n      `F3_SLL:  op_s = "sll     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:267: Define or directive not defined: \'`F3_SLT\'\n      `F3_SLT:  op_s = "slt     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:268: Define or directive not defined: \'`F3_SLTU\'\n      `F3_SLTU: op_s = "sltu    ";\n      ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:269: Define or directive not defined: \'`F3_XOR\'\n      `F3_XOR:  op_s = "xor     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:270: Define or directive not defined: \'`F3_SR\'\n      `F3_SR:   op_s = inst[16] ? "sra     " : "srl     ";\n      ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:271: Define or directive not defined: \'`F3_OR\'\n      `F3_OR:   op_s = "or      ";\n      ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:272: Define or directive not defined: \'`F3_AND\'\n      `F3_AND:  op_s = "and     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:277: Define or directive not defined: \'`OPCODE_OP_IMM\'\n   `OPCODE_OP_IMM:\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:279: Define or directive not defined: \'`F3_ADD\'\n     `F3_ADD:  op_s = inst == 32\'h00000013 ? "nop     " : "addi    ";\n     ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:280: Define or directive not defined: \'`F3_SLL\'\n     `F3_SLL:  op_s = "slli    ";\n     ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:281: Define or directive not defined: \'`F3_SLT\'\n     `F3_SLT:  op_s = "slti    ";\n     ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:282: Define or directive not defined: \'`F3_SLTU\'\n     `F3_SLTU: op_s = "sltiu   ";\n     ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:283: Define or directive not defined: \'`F3_XOR\'\n     `F3_XOR:  op_s = "xori    ";\n     ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module imm_decoder (
	output [47:0] str,
	input [11:0] imm12
);
	wire [11:0] imm = imm12[11] ? -$signed(imm12) : imm12;

	wire [3:0] d0 = imm[3:0];
	wire [3:0] d1 = imm[7:4];
	wire [3:0] d2 = imm[11:8];

	wire [7:0] d0_s = d0 <= 9 ? "0" + d0 : "A" + d0 - 10;
	wire [7:0] d1_s = d1 <= 9 ? "0" + d1 : "A" + d1 - 10;
	wire [7:0] d2_s = d2 <= 9 ? "0" + d2 : "A" + d2 - 10;

	assign str = {imm12[11] ? "-" : " ", "0x", d2_s, d1_s, d0_s}; 

endmodule
module imm_decoder (
	output [47:0] str,
	input [11:0] imm12
);

	wire [11:0] imm = imm12[11] ? -$signed(imm12) : imm12;

	wire [3:0] d0 = imm[3:0];
	wire [3:0] d1 = imm[7:4];
	wire [3:0] d2 = imm[11:8];

	wire [7:0] d0_s = d0 <= 9 ? "0" + d0 : "A" + d0 - 10;
	wire [7:0] d1_s = d1 <= 9 ? "0" + d1 : "A" + d1 - 10;
	wire [7:0] d2_s = d2 <= 9 ? "0" + d2 : "A" + d2 - 10;

	assign str = {imm12[11] ? "-" : " ", "0x", d2_s, d1_s, d0_s}; 

endmodule