data/full_repos/permissive/185824253/rtl/myCPU/mux_2.v
data/verilator_xmls/d9568a16-c773-458d-b51f-e13b25693fa7.xml
module mux_2 (data_0, data_1, condition, data_out);
	parameter WIDTH = 32;

	input  [WIDTH-1:0] data_0;
	input  [WIDTH-1:0] data_1;
	input              condition;
	output [WIDTH-1:0] data_out;

	assign data_out = ({WIDTH{condition==1'd0}} & data_0)
					| ({WIDTH{condition==1'd1}} & data_1);
endmodule
module mux_2 (data_0, data_1, condition, data_out);

	parameter WIDTH = 32;

	input  [WIDTH-1:0] data_0;
	input  [WIDTH-1:0] data_1;
	input              condition;
	output [WIDTH-1:0] data_out;

	assign data_out = ({WIDTH{condition==1'd0}} & data_0)
					| ({WIDTH{condition==1'd1}} & data_1);
endmodule