data/full_repos/permissive/143278/ivltests/pr2352834.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2352834.v:11: Operator POW expects 129 bits on the LHS, but LHS\'s VARREF \'in1\' generates 32 bits.\n                                                                         : ... In instance top\n    res = in1 ** in2;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2352834.v:12: Operator NEGATE expects 129 bits on the LHS, but LHS\'s CONST \'128\'sh8000000000000000\' generates 128 bits.\n                                                                         : ... In instance top\n    if (res !== -128\'sd9223372036854775808) begin\n                ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2352834.v:18: Operator POW expects 129 bits on the LHS, but LHS\'s VARREF \'in1\' generates 32 bits.\n                                                                         : ... In instance top\n    res = in1 ** in2;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2352834.v:19: Operator NEGATE expects 129 bits on the LHS, but LHS\'s CONST \'128\'sh20000000000000000\' generates 128 bits.\n                                                                         : ... In instance top\n    if (res !== -128\'sd36893488147419103232) begin\n                ^\n%Error: Exiting due to 4 warning(s)\n'
module top;
  reg pass;
  reg [31:0] in2;
  integer in1;
  reg signed [128:0] res;

  initial begin
    pass = 1'b1;

    in1 = -2; in2 = 63;
    res = in1 ** in2;
    if (res !== -128'sd9223372036854775808) begin
      $display("Failed: -2 ** 65, expected -9223372036854775808, got %0d", res);
      pass = 1'b0;
    end

    in1 = -2; in2 = 65;
    res = in1 ** in2;
    if (res !== -128'sd36893488147419103232) begin
      $display("Failed: -2 ** 65, expected -36893488147419103232, got %0d", res);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  reg [31:0] in2;
  integer in1;
  reg signed [128:0] res;

  initial begin
    pass = 1'b1;

    in1 = -2; in2 = 63;
    res = in1 ** in2;
    if (res !== -128'sd9223372036854775808) begin
      $display("Failed: -2 ** 65, expected -9223372036854775808, got %0d", res);
      pass = 1'b0;
    end

    in1 = -2; in2 = 65;
    res = in1 ** in2;
    if (res !== -128'sd36893488147419103232) begin
      $display("Failed: -2 ** 65, expected -36893488147419103232, got %0d", res);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule