data/full_repos/permissive/216654561/HW/OvCAM_S_AXI.v
1: b'%Warning-WIDTH: data/full_repos/permissive/216654561/HW/OvCAM_S_AXI.v:308: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                         : ... In instance OvCAM_S_AXI\n       axi_araddr  <= 32\'b0;\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module OvCAM_S_AXI #
	(
		
		parameter integer S_AXI_DATA_WIDTH	= 32,
		parameter integer C_S_AXI_ADDR_WIDTH	= 4
		
	)
	(
        output reg [9:0] xLoc,
        output reg [9:0] yLoc,
        output reg [1:0]output_sel,        
		input wire  active_pixel,
        input wire i2c_ready,
        input wire [7:0] pixel_out,

		


		
		input wire ACLK,
		
		input wire  ARESETN,
		

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
		 

		input wire [2 : 0] S_AXI_AWPROT,
		

		input wire  S_AXI_AWVALID,
		

		output wire  S_AXI_AWREADY,
		

		input wire [S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
		 

		input wire [(S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
		

		input wire  S_AXI_WVALID,
		

		output wire  S_AXI_WREADY,
		

		output wire [1 : 0] S_AXI_BRESP,
		

		output wire  S_AXI_BVALID,
		

		input wire  S_AXI_BREADY,
		

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
		 

		input wire [2 : 0] S_AXI_ARPROT,
		

		input wire  S_AXI_ARVALID,
		

   		output wire  S_AXI_ARREADY,
		

		output wire [S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
		

		output wire [1 : 0] S_AXI_RRESP,
		

		output wire  S_AXI_RVALID,
		

		input wire  S_AXI_RREADY
	);


	
	
	
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready; 
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [S_AXI_DATA_WIDTH-1 : 0] 	axi_rDATA;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;

	




	localparam integer ADDR_LSB = (S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 1; 




	reg [S_AXI_DATA_WIDTH-1:0]	slv_reg0;
	reg [S_AXI_DATA_WIDTH-1:0]	slv_reg1;  
	reg [S_AXI_DATA_WIDTH-1:0]	slv_reg2;
	reg [S_AXI_DATA_WIDTH-1:0]	slv_reg3;
	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [S_AXI_DATA_WIDTH-1:0]	 reg_DATA_out;
	integer	 byte_index;



	assign S_AXI_AWREADY	= axi_awready; 
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rDATA;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;
	
	
	



	

	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0; 
	    end 
	  else
	    begin    


	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID) 
	        begin

	          axi_awready <= 1'b1;
	        end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       



	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       



	
	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
	        begin

	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin

	      slv_reg0 <= 0;
	      slv_reg1 <= 0;
	      slv_reg2 <= 0;
	      slv_reg3 <= 0;
	    end 
	  else begin
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	          2'h0:
	            for ( byte_index = 0; byte_index <= (S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) 
				  begin


	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          2'h1:
	            for ( byte_index = 0; byte_index <= (S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          2'h2:
	            for ( byte_index = 0; byte_index <= (S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          2'h3:
	            for ( byte_index = 0; byte_index <= (S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end
	          default : begin
	                      slv_reg0 <= slv_reg0;
	                      slv_reg1 <= slv_reg1;
	                      slv_reg2 <= slv_reg2;
	                      slv_reg3 <= slv_reg3;
	                    end
	        endcase
	      end
	  end
	end    







	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 

	           
	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    




	
	
	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) 
	        2'h0   : reg_DATA_out <= slv_reg0;
	        2'h1   : reg_DATA_out <= {23'b0,pixel_out[7:0],i2c_ready};
	        2'h2   : reg_DATA_out <= slv_reg2;
	        2'h3   : reg_DATA_out <= slv_reg3;
	        default : reg_DATA_out <= 0;
	      endcase
	end


	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_rDATA  <= 0;
	    end 
	  else
	    begin    


	     
	      if (slv_reg_rden)
	        begin
	          axi_rDATA <= reg_DATA_out;
	        end   
	    end
	end    

	

    always @(slv_reg0, pixel_out, i2c_ready)
    begin
        yLoc = slv_reg0[23:14]; 
        xLoc = slv_reg0[13:4]; 
        output_sel = slv_reg0[1:0];
    end


	endmodule
module OvCAM_S_AXI #
	(
		
		parameter integer S_AXI_DATA_WIDTH	= 32,
		parameter integer C_S_AXI_ADDR_WIDTH	= 4
		
	)
	(
        output reg [9:0] xLoc,
        output reg [9:0] yLoc,
        output reg [1:0]output_sel,        
		input wire  active_pixel,
        input wire i2c_ready,
        input wire [7:0] pixel_out,

		


		
		input wire ACLK,
		
		input wire  ARESETN,
		

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
		 

		input wire [2 : 0] S_AXI_AWPROT,
		

		input wire  S_AXI_AWVALID,
		

		output wire  S_AXI_AWREADY,
		

		input wire [S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
		 

		input wire [(S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
		

		input wire  S_AXI_WVALID,
		

		output wire  S_AXI_WREADY,
		

		output wire [1 : 0] S_AXI_BRESP,
		

		output wire  S_AXI_BVALID,
		

		input wire  S_AXI_BREADY,
		

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
		 

		input wire [2 : 0] S_AXI_ARPROT,
		

		input wire  S_AXI_ARVALID,
		

   		output wire  S_AXI_ARREADY,
		

		output wire [S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
		

		output wire [1 : 0] S_AXI_RRESP,
		

		output wire  S_AXI_RVALID,
		

		input wire  S_AXI_RREADY
	);



	
	
	
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready; 
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [S_AXI_DATA_WIDTH-1 : 0] 	axi_rDATA;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;

	




	localparam integer ADDR_LSB = (S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 1; 




	reg [S_AXI_DATA_WIDTH-1:0]	slv_reg0;
	reg [S_AXI_DATA_WIDTH-1:0]	slv_reg1;  
	reg [S_AXI_DATA_WIDTH-1:0]	slv_reg2;
	reg [S_AXI_DATA_WIDTH-1:0]	slv_reg3;
	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [S_AXI_DATA_WIDTH-1:0]	 reg_DATA_out;
	integer	 byte_index;



	assign S_AXI_AWREADY	= axi_awready; 
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rDATA;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;
	
	
	



	

	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0; 
	    end 
	  else
	    begin    


	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID) 
	        begin

	          axi_awready <= 1'b1;
	        end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       



	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       



	
	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
	        begin

	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin

	      slv_reg0 <= 0;
	      slv_reg1 <= 0;
	      slv_reg2 <= 0;
	      slv_reg3 <= 0;
	    end 
	  else begin
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	          2'h0:
	            for ( byte_index = 0; byte_index <= (S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) 
				  begin


	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          2'h1:
	            for ( byte_index = 0; byte_index <= (S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          2'h2:
	            for ( byte_index = 0; byte_index <= (S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          2'h3:
	            for ( byte_index = 0; byte_index <= (S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end
	          default : begin
	                      slv_reg0 <= slv_reg0;
	                      slv_reg1 <= slv_reg1;
	                      slv_reg2 <= slv_reg2;
	                      slv_reg3 <= slv_reg3;
	                    end
	        endcase
	      end
	  end
	end    







	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 

	           
	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    




	
	
	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) 
	        2'h0   : reg_DATA_out <= slv_reg0;
	        2'h1   : reg_DATA_out <= {23'b0,pixel_out[7:0],i2c_ready};
	        2'h2   : reg_DATA_out <= slv_reg2;
	        2'h3   : reg_DATA_out <= slv_reg3;
	        default : reg_DATA_out <= 0;
	      endcase
	end


	always @( posedge ACLK )
	begin
	  if ( ARESETN == 1'b0 )
	    begin
	      axi_rDATA  <= 0;
	    end 
	  else
	    begin    


	     
	      if (slv_reg_rden)
	        begin
	          axi_rDATA <= reg_DATA_out;
	        end   
	    end
	end    

	

    always @(slv_reg0, pixel_out, i2c_ready)
    begin
        yLoc = slv_reg0[23:14]; 
        xLoc = slv_reg0[13:4]; 
        output_sel = slv_reg0[1:0];
    end


	endmodule