data/full_repos/permissive/19591557/modules/uart/spio_uart_fifo.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_fifo.v:10: Cannot find include file: spio_uart_common.h\n`include "spio_uart_common.h" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/modules/uart,data/full_repos/permissive/19591557/spio_uart_common.h\n             data/full_repos/permissive/19591557/modules/uart,data/full_repos/permissive/19591557/spio_uart_common.h.v\n             data/full_repos/permissive/19591557/modules/uart,data/full_repos/permissive/19591557/spio_uart_common.h.sv\n             spio_uart_common.h\n             spio_uart_common.h.v\n             spio_uart_common.h.sv\n             obj_dir/spio_uart_common.h\n             obj_dir/spio_uart_common.h.v\n             obj_dir/spio_uart_common.h.sv\n%Error: Exiting due to 1 error(s)\n'
module spio_uart_fifo#(


                        parameter BUFFER_ADDR_BITS = 4

                      , parameter WORD_SIZE = 8
                      )
                      (
                        input wire CLK_IN

                      , input wire RESET_IN

                      , output wire [BUFFER_ADDR_BITS-1:0] OCCUPANCY_OUT

                      ,   input  wire [WORD_SIZE-1:0] IN_DATA_IN
                      ,   input  wire                 IN_VLD_IN
                      ,   output wire                 IN_RDY_OUT

                      ,   output wire [WORD_SIZE-1:0] OUT_DATA_OUT
                      ,   output wire                 OUT_VLD_OUT
                      ,   input  wire                 OUT_RDY_IN
                      );



reg [WORD_SIZE-1:0]        buffer_i [(1<<BUFFER_ADDR_BITS)-1:0];
reg [BUFFER_ADDR_BITS-1:0] head_i;
reg [BUFFER_ADDR_BITS-1:0] tail_i;


assign OUT_VLD_OUT = head_i != tail_i;


assign IN_RDY_OUT = head_i != (tail_i - 1);


assign OUT_DATA_OUT = (head_i != tail_i) ? buffer_i[tail_i] : {WORD_SIZE{1'bX}};



assign OCCUPANCY_OUT = head_i - tail_i;


always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		head_i <= {BUFFER_ADDR_BITS{1'b0}};
	else
		if (IN_RDY_OUT && IN_VLD_IN)
			begin
				head_i           <= head_i + 1;
				buffer_i[head_i] <= IN_DATA_IN;
			end



always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		tail_i <= {BUFFER_ADDR_BITS{1'b0}};
	else
		if (OUT_RDY_IN && OUT_VLD_OUT)
			tail_i <= tail_i + 1;

endmodule
module spio_uart_fifo#(


                        parameter BUFFER_ADDR_BITS = 4

                      , parameter WORD_SIZE = 8
                      )
                      (
                        input wire CLK_IN

                      , input wire RESET_IN

                      , output wire [BUFFER_ADDR_BITS-1:0] OCCUPANCY_OUT

                      ,   input  wire [WORD_SIZE-1:0] IN_DATA_IN
                      ,   input  wire                 IN_VLD_IN
                      ,   output wire                 IN_RDY_OUT

                      ,   output wire [WORD_SIZE-1:0] OUT_DATA_OUT
                      ,   output wire                 OUT_VLD_OUT
                      ,   input  wire                 OUT_RDY_IN
                      );




reg [WORD_SIZE-1:0]        buffer_i [(1<<BUFFER_ADDR_BITS)-1:0];
reg [BUFFER_ADDR_BITS-1:0] head_i;
reg [BUFFER_ADDR_BITS-1:0] tail_i;


assign OUT_VLD_OUT = head_i != tail_i;


assign IN_RDY_OUT = head_i != (tail_i - 1);


assign OUT_DATA_OUT = (head_i != tail_i) ? buffer_i[tail_i] : {WORD_SIZE{1'bX}};



assign OCCUPANCY_OUT = head_i - tail_i;


always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		head_i <= {BUFFER_ADDR_BITS{1'b0}};
	else
		if (IN_RDY_OUT && IN_VLD_IN)
			begin
				head_i           <= head_i + 1;
				buffer_i[head_i] <= IN_DATA_IN;
			end



always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		tail_i <= {BUFFER_ADDR_BITS{1'b0}};
	else
		if (OUT_RDY_IN && OUT_VLD_OUT)
			tail_i <= tail_i + 1;

endmodule