data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/rom_test_8.v
data/verilator_xmls/f407ff27-1ccd-42d4-bc9b-2c21f4b93fc4.xml
module rom_test_8 (
    input [3:0] address,
    output reg [7:0] letter
  );
  
  
  
  localparam TEXT = 88'h48656c6c6f576f726c6421;
  
  always @* begin
    letter = TEXT[(address)*8+7-:8];
  end
endmodule
module rom_test_8 (
    input [3:0] address,
    output reg [7:0] letter
  );

  
  
  
  localparam TEXT = 88'h48656c6c6f576f726c6421;
  
  always @* begin
    letter = TEXT[(address)*8+7-:8];
  end
endmodule