data/full_repos/permissive/147790758/tb1_b27s.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_b27s.v:11: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_b27s.v:13: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_b27s.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_b27s.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_b27s.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb1_b27s.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/147790758/tb1_b27s.v:7: Cannot find file containing module: \'b27s\'\nb27s DUT (.sw(datain), .led(dataout));\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b27s\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b27s.v\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b27s.sv\n             b27s\n             b27s.v\n             b27s.sv\n             obj_dir/b27s\n             obj_dir/b27s.v\n             obj_dir/b27s.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb1_b27s();
	reg [3:0] datain;
	wire [6:0] dataout;
	
b27s DUT (.sw(datain), .led(dataout));

initial begin 
	datain = 4'd0;
	#10;
	datain = 4'd7;
	#10;
	datain = 4'd12;
	#10;
	datain = 4'd3;
	#10;
	datain = 4'd10;
	#10;
	datain = 4'd15;
	#10;
end 
endmodule
module tb1_b27s();

	reg [3:0] datain;
	wire [6:0] dataout;
	
b27s DUT (.sw(datain), .led(dataout));

initial begin 
	datain = 4'd0;
	#10;
	datain = 4'd7;
	#10;
	datain = 4'd12;
	#10;
	datain = 4'd3;
	#10;
	datain = 4'd10;
	#10;
	datain = 4'd15;
	#10;
end 
endmodule