data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v
1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v:10: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.v\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.sv\n             sm_settings.vh\n             sm_settings.vh.v\n             sm_settings.vh.sv\n             obj_dir/sm_settings.vh\n             obj_dir/sm_settings.vh.v\n             obj_dir/sm_settings.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v:39: Define or directive not defined: \'`SM_CONFIG_BUSY_RAM_DELAY\'\n    sm_delay #(`SM_CONFIG_BUSY_RAM_DELAY) dly \n               ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module sm_ram_outbuf
#(
    parameter WIDTH = 6
)
(
    input         clk,
    input         rst_n,
    input  [31:0] a,
    input         we,
    input  [31:0] wd,
    input         valid,
    output        ready,
    output [31:0] rd
);
    wire [31:0] ram_rd;

    sm_ram #(WIDTH) ram
    (
        .clk ( clk    ),
        .a   ( a      ),
        .we  ( we     ),
        .wd  ( wd     ),
        .rd  ( ram_rd )
    );
    assign ready = 1'b1;

    sm_register_we #(32) r_ram_rd (clk, rst_n, valid, ram_rd, rd);

endmodule
module sm_ram_outbuf
#(
    parameter WIDTH = 6
)
(
    input         clk,
    input         rst_n,
    input  [31:0] a,
    input         we,
    input  [31:0] wd,
    input         valid,
    output        ready,
    output [31:0] rd
);

    wire [31:0] ram_rd;

    sm_ram #(WIDTH) ram
    (
        .clk ( clk    ),
        .a   ( a      ),
        .we  ( we     ),
        .wd  ( wd     ),
        .rd  ( ram_rd )
    );
    assign ready = 1'b1;

    sm_register_we #(32) r_ram_rd (clk, rst_n, valid, ram_rd, rd);

endmodule