data/full_repos/permissive/201224775/rtl/lattice/lattice_top.v
 line:110 column:2: Illegal character '\x00'
1: b"%Error: data/full_repos/permissive/201224775/rtl/lattice/lattice_top.v:35: Cannot find file containing module: 'SB_GB'\nSB_GB i_clk_gb (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/201224775/rtl/lattice,data/full_repos/permissive/201224775/SB_GB\n             data/full_repos/permissive/201224775/rtl/lattice,data/full_repos/permissive/201224775/SB_GB.v\n             data/full_repos/permissive/201224775/rtl/lattice,data/full_repos/permissive/201224775/SB_GB.sv\n             SB_GB\n             SB_GB.v\n             SB_GB.sv\n             obj_dir/SB_GB\n             obj_dir/SB_GB.v\n             obj_dir/SB_GB.sv\n%Error: data/full_repos/permissive/201224775/rtl/lattice/lattice_top.v:76: Cannot find file containing module: 'scarv_soc'\nscarv_soc #(\n^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module lattice_top (

input  wire        clki             ,
input  wire        resetn            

);



parameter           BRAM_ROM_SIZE      = 1024;


parameter           BRAM_RAM_SIZE      = 1024;


parameter           IC_ENABLE_AXI_BRIDGE = 0;





wire g_clk      ;
wire g_resetn   ;

assign g_resetn = resetn;


SB_GB i_clk_gb (
.USER_SIGNAL_TO_GLOBAL_BUFFER(clki  ),
.GLOBAL_BUFFER_OUTPUT        (g_clk )
);





wire        cpu_int_nmi       = 0;
wire        cpu_int_external  = 0;
wire [ 3:0] cpu_int_ext_cause = 0;
wire        cpu_int_software  = 0;
                             




wire        m0_awvalid           ;
wire        m0_awready        = 0;
wire [31:0] m0_awaddr            ;
wire [ 2:0] m0_awprot            ;
wire        m0_wvalid            ;
wire        m0_wready         = 0;
wire [31:0] m0_wdata             ;
wire [ 3:0] m0_wstrb             ;
wire        m0_bvalid         = 0;
wire        m0_bready            ;
wire [ 1:0] m0_bresp          = 0;
wire        m0_arvalid           ;
wire        m0_arready        = 0;
wire [31:0] m0_araddr            ;
wire [ 2:0] m0_arprot            ;
wire        m0_rvalid         = 0;
wire        m0_rready            ;
wire [ 1:0] m0_rresp          = 0;
wire [31:0] m0_rdata          = 0;




scarv_soc #(
.BRAM_ROM_SIZE(BRAM_ROM_SIZE),
.BRAM_RAM_SIZE(BRAM_RAM_SIZE),
.IC_ENABLE_AXI_BRIDGE(IC_ENABLE_AXI_BRIDGE)
) i_scarv_soc (
.g_clk            (g_clk            ),
.g_resetn         (g_resetn         ),
.cpu_int_nmi      (cpu_int_nmi      ),
.cpu_int_external (cpu_int_external ),
.cpu_int_ext_cause(cpu_int_ext_cause),
.cpu_int_software (cpu_int_software ),
.m0_awvalid       (m0_awvalid       ),
.m0_awready       (m0_awready       ),
.m0_awaddr        (m0_awaddr        ),
.m0_awprot        (m0_awprot        ),
.m0_wvalid        (m0_wvalid        ),
.m0_wready        (m0_wready        ),
.m0_wdata         (m0_wdata         ),
.m0_wstrb         (m0_wstrb         ),
.m0_bvalid        (m0_bvalid        ),
.m0_bready        (m0_bready        ),
.m0_bresp         (m0_bresp         ),
.m0_arvalid       (m0_arvalid       ),
.m0_arready       (m0_arready       ),
.m0_araddr        (m0_araddr        ),
.m0_arprot        (m0_arprot        ),
.m0_rvalid        (m0_rvalid        ),
.m0_rready        (m0_rready        ),
.m0_rresp         (m0_rresp         ),
.m0_rdata         (m0_rdata         )
);


endmodule
module lattice_top (

input  wire        clki             ,
input  wire        resetn            

);




parameter           BRAM_ROM_SIZE      = 1024;


parameter           BRAM_RAM_SIZE      = 1024;


parameter           IC_ENABLE_AXI_BRIDGE = 0;





wire g_clk      ;
wire g_resetn   ;

assign g_resetn = resetn;


SB_GB i_clk_gb (
.USER_SIGNAL_TO_GLOBAL_BUFFER(clki  ),
.GLOBAL_BUFFER_OUTPUT        (g_clk )
);





wire        cpu_int_nmi       = 0;
wire        cpu_int_external  = 0;
wire [ 3:0] cpu_int_ext_cause = 0;
wire        cpu_int_software  = 0;
                             




wire        m0_awvalid           ;
wire        m0_awready        = 0;
wire [31:0] m0_awaddr            ;
wire [ 2:0] m0_awprot            ;
wire        m0_wvalid            ;
wire        m0_wready         = 0;
wire [31:0] m0_wdata             ;
wire [ 3:0] m0_wstrb             ;
wire        m0_bvalid         = 0;
wire        m0_bready            ;
wire [ 1:0] m0_bresp          = 0;
wire        m0_arvalid           ;
wire        m0_arready        = 0;
wire [31:0] m0_araddr            ;
wire [ 2:0] m0_arprot            ;
wire        m0_rvalid         = 0;
wire        m0_rready            ;
wire [ 1:0] m0_rresp          = 0;
wire [31:0] m0_rdata          = 0;




scarv_soc #(
.BRAM_ROM_SIZE(BRAM_ROM_SIZE),
.BRAM_RAM_SIZE(BRAM_RAM_SIZE),
.IC_ENABLE_AXI_BRIDGE(IC_ENABLE_AXI_BRIDGE)
) i_scarv_soc (
.g_clk            (g_clk            ),
.g_resetn         (g_resetn         ),
.cpu_int_nmi      (cpu_int_nmi      ),
.cpu_int_external (cpu_int_external ),
.cpu_int_ext_cause(cpu_int_ext_cause),
.cpu_int_software (cpu_int_software ),
.m0_awvalid       (m0_awvalid       ),
.m0_awready       (m0_awready       ),
.m0_awaddr        (m0_awaddr        ),
.m0_awprot        (m0_awprot        ),
.m0_wvalid        (m0_wvalid        ),
.m0_wready        (m0_wready        ),
.m0_wdata         (m0_wdata         ),
.m0_wstrb         (m0_wstrb         ),
.m0_bvalid        (m0_bvalid        ),
.m0_bready        (m0_bready        ),
.m0_bresp         (m0_bresp         ),
.m0_arvalid       (m0_arvalid       ),
.m0_arready       (m0_arready       ),
.m0_araddr        (m0_araddr        ),
.m0_arprot        (m0_arprot        ),
.m0_rvalid        (m0_rvalid        ),
.m0_rready        (m0_rready        ),
.m0_rresp         (m0_rresp         ),
.m0_rdata         (m0_rdata         )
);


endmodule