data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v
1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:11: Cannot find include file: sm_cpu.vh\n`include "sm_cpu.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.v\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n             sm_cpu.vh\n             sm_cpu.vh.v\n             sm_cpu.vh.sv\n             obj_dir/sm_cpu.vh\n             obj_dir/sm_cpu.vh.v\n             obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:12: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: Define or directive not defined: \'`PC_EXC\'\n    assign pc_new = pcExc == `PC_EXC  ?  cp0_ExcHandler :\n                             ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n    assign pc_new = pcExc == `PC_EXC  ?  cp0_ExcHandler :\n                                      ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:179: Define or directive not defined: \'`PC_ERET\'\n                    pcExc == `PC_ERET ?  cp0_EPC        :\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: Define or directive not defined: \'`PC_EXC\'\n    assign pcExc = exception      ? `PC_EXC  :\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign pcExc = exception      ? `PC_EXC  :\n                                             ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_ERET\'\n                   cw_cpzExcEret  ? `PC_ERET : `PC_FLOW;\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_FLOW\'\n                   cw_cpzExcEret  ? `PC_ERET : `PC_FLOW;\n                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: Define or directive not defined: \'`ALU_ADD\'\n        aluControl  = `ALU_ADD;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        aluControl  = `ALU_ADD;\n                              ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n                     ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`F_ADDU\'\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n                        ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`ALU_ADD\'\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n                                                                                                       ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_OR,   `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR;   end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`F_OR\'\n            { `C_SPEC,  `F_OR,   `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR;   end\n                        ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_OR,   `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR;   end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`ALU_OR\'\n            { `C_SPEC,  `F_OR,   `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR;   end\n                                                                                               ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_SRL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL;  end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`F_SRL\'\n            { `C_SPEC,  `F_SRL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL;  end\n                        ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_SRL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL;  end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`ALU_SRL\'\n            { `C_SPEC,  `F_SRL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL;  end\n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_SLL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL;  end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`F_SLL\'\n            { `C_SPEC,  `F_SLL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL;  end\n                        ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_SLL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL;  end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`ALU_SLL\'\n            { `C_SPEC,  `F_SLL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL;  end\n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`F_SLTU\'\n            { `C_SPEC,  `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n                        ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`ALU_SLTU\'\n            { `C_SPEC,  `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n                                                                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`F_SUBU\'\n            { `C_SPEC,  `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n                        ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`ALU_SUBU\'\n            { `C_SPEC,  `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n                                                                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`C_ADDIU\'\n            { `C_ADDIU, `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD;  end\n              ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`F_ANY\'\n            { `C_ADDIU, `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD;  end\n                        ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`S_ANY\'\n            { `C_ADDIU, `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD;  end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`ALU_ADD\'\n            { `C_ADDIU, `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD;  end\n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`C_LUI\'\n            { `C_LUI,   `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI;  end\n              ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`F_ANY\'\n            { `C_LUI,   `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI;  end\n                        ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`S_ANY\'\n            { `C_LUI,   `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI;  end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`ALU_LUI\'\n            { `C_LUI,   `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI;  end\n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`C_LW\'\n            { `C_LW,    `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n              ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`F_ANY\'\n            { `C_LW,    `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n                        ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`S_ANY\'\n            { `C_LW,    `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`ALU_ADD\'\n            { `C_LW,    `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:267: Define or directive not defined: \'`C_SW\'\n            { `C_SW,    `F_ANY,  `S_ANY } : begin memWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n              ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module sm_control
(
    input      [5:0] cmdOper,
    input      [4:0] cmdRegS,
    input      [5:0] cmdFunk,
    input            aluZero,
    output           pcSrc,
    output     [1:0] pcExc,
    output reg       regDst,
    output reg       regWrite,
    output reg       aluSrc,
    output reg [2:0] aluControl,
    output reg       memWrite,
    output reg       memToReg,
    output reg       memAccess,
    output reg       branch,
    output reg       cw_cpzToReg,
    output reg       cw_cpzRegWrite,
    output reg       cw_cpzExcEret,
    input            excAsync,
    input            excSync,
    output           cw_epcSrc,
    output reg       excRiFound
);
    reg          condZero;

    assign pcSrc = branch & (aluZero == condZero);

    assign cw_epcSrc = excSync;

    wire   exception = excAsync | excSync;
    assign pcExc = exception      ? `PC_EXC  :
                   cw_cpzExcEret  ? `PC_ERET : `PC_FLOW;

    always @ (*) begin
        branch      = 1'b0;
        condZero    = 1'b0;
        regDst      = 1'b0;
        regWrite    = 1'b0;
        aluSrc      = 1'b0;
        aluControl  = `ALU_ADD;
        memWrite    = 1'b0;
        memToReg    = 1'b0;
        memAccess   = 1'b0;
        cw_cpzToReg    = 1'b0;
        cw_cpzRegWrite = 1'b0;
        cw_cpzExcEret  = 1'b0;
        excRiFound  = 1'b0;

        casez( {cmdOper,cmdFunk, cmdRegS} )
            default               : excRiFound = 1'b1;

            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_ADD;  end
            { `C_SPEC,  `F_OR,   `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_OR;   end
            { `C_SPEC,  `F_SRL,  `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRL;  end
            { `C_SPEC,  `F_SLL,  `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLL;  end
            { `C_SPEC,  `F_SLTU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLTU; end
            { `C_SPEC,  `F_SUBU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SUBU; end

            { `C_ADDIU, `F_ANY,  `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD;  end
            { `C_LUI,   `F_ANY,  `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_LUI;  end
            { `C_LW,    `F_ANY,  `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD; 
                                                  memToReg = 1'b1; memAccess = 1'b1; end
            { `C_SW,    `F_ANY,  `S_ANY } : begin memWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD; 
                                                  memAccess = 1'b1; end

            { `C_BEQ,   `F_ANY,  `S_ANY } : begin branch = 1'b1; condZero = 1'b1; aluControl = `ALU_SUBU; end
            { `C_BNE,   `F_ANY,  `S_ANY } : begin branch = 1'b1; aluControl = `ALU_SUBU; end

            { `C_COP0, `F_ANY, `S_COP0_MF } : begin cw_cpzToReg = 1'b1; regWrite = 1'b1; end
            { `C_COP0, `F_ANY, `S_COP0_MT } : begin cw_cpzRegWrite = 1'b1; end
            { `C_COP0, `F_ERET, `S_ERET   } : begin cw_cpzExcEret  = 1'b1; end
            { `C_NOP,  `F_NOP,  `S_NOP    } : ;
        endcase
    end
endmodule
module sm_control
(
    input      [5:0] cmdOper,
    input      [4:0] cmdRegS,
    input      [5:0] cmdFunk,
    input            aluZero,
    output           pcSrc,
    output     [1:0] pcExc,
    output reg       regDst,
    output reg       regWrite,
    output reg       aluSrc,
    output reg [2:0] aluControl,
    output reg       memWrite,
    output reg       memToReg,
    output reg       memAccess,
    output reg       branch,
    output reg       cw_cpzToReg,
    output reg       cw_cpzRegWrite,
    output reg       cw_cpzExcEret,
    input            excAsync,
    input            excSync,
    output           cw_epcSrc,
    output reg       excRiFound
);

    reg          condZero;

    assign pcSrc = branch & (aluZero == condZero);

    assign cw_epcSrc = excSync;

    wire   exception = excAsync | excSync;
    assign pcExc = exception      ? `PC_EXC  :
                   cw_cpzExcEret  ? `PC_ERET : `PC_FLOW;

    always @ (*) begin
        branch      = 1'b0;
        condZero    = 1'b0;
        regDst      = 1'b0;
        regWrite    = 1'b0;
        aluSrc      = 1'b0;
        aluControl  = `ALU_ADD;
        memWrite    = 1'b0;
        memToReg    = 1'b0;
        memAccess   = 1'b0;
        cw_cpzToReg    = 1'b0;
        cw_cpzRegWrite = 1'b0;
        cw_cpzExcEret  = 1'b0;
        excRiFound  = 1'b0;

        casez( {cmdOper,cmdFunk, cmdRegS} )
            default               : excRiFound = 1'b1;

            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_ADD;  end
            { `C_SPEC,  `F_OR,   `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_OR;   end
            { `C_SPEC,  `F_SRL,  `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRL;  end
            { `C_SPEC,  `F_SLL,  `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLL;  end
            { `C_SPEC,  `F_SLTU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLTU; end
            { `C_SPEC,  `F_SUBU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SUBU; end

            { `C_ADDIU, `F_ANY,  `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD;  end
            { `C_LUI,   `F_ANY,  `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_LUI;  end
            { `C_LW,    `F_ANY,  `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD; 
                                                  memToReg = 1'b1; memAccess = 1'b1; end
            { `C_SW,    `F_ANY,  `S_ANY } : begin memWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD; 
                                                  memAccess = 1'b1; end

            { `C_BEQ,   `F_ANY,  `S_ANY } : begin branch = 1'b1; condZero = 1'b1; aluControl = `ALU_SUBU; end
            { `C_BNE,   `F_ANY,  `S_ANY } : begin branch = 1'b1; aluControl = `ALU_SUBU; end

            { `C_COP0, `F_ANY, `S_COP0_MF } : begin cw_cpzToReg = 1'b1; regWrite = 1'b1; end
            { `C_COP0, `F_ANY, `S_COP0_MT } : begin cw_cpzRegWrite = 1'b1; end
            { `C_COP0, `F_ERET, `S_ERET   } : begin cw_cpzExcEret  = 1'b1; end
            { `C_NOP,  `F_NOP,  `S_NOP    } : ;
        endcase
    end
endmodule