data/full_repos/permissive/107057345/Morse Encoder Synthesized/Design Project 3 synthesis.srcs/sources_1/imports/Design 3/code_reg.v
None: at end of input
1: b'%Error: Cannot find file containing module: Encoder\n        ... Looked in:\n             data/full_repos/permissive/107057345/Morse/Encoder\n             data/full_repos/permissive/107057345/Morse/Encoder.v\n             data/full_repos/permissive/107057345/Morse/Encoder.sv\n             Encoder\n             Encoder.v\n             Encoder.sv\n             obj_dir/Encoder\n             obj_dir/Encoder.v\n             obj_dir/Encoder.sv\n%Error: Cannot find file containing module: Synthesized/Design\n%Error: Cannot find file containing module: Project\n%Error: Cannot find file containing module: 3\n%Error: Cannot find file containing module: synthesis.srcs/sources_1/imports/Design\n%Error: Cannot find file containing module: 3,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/Morse\n%Error: Cannot find file containing module: 3/code_reg.v\n%Error: Exiting due to 8 error(s)\n'
module code_reg(
		input [7:0]  charcode_data,
		input [3:0]  charlen_data,
		input 	     char_load, shft_cnt,
		output [3:0] cntr_data, 
		output 	     shft_data,
		input 	     reset, clock
		 );




   reg [7:0] 	     shftr_o, shftr_i;
   reg [3:0] 	     cntr_o, cntr_i;

   always @(posedge clock) begin
      shftr_o <= shftr_i;
      cntr_o <= cntr_i;
   end

   wire		     shft_data;
   wire [3:0] 	     cntr_data;

   always @(*) begin
      if (reset) begin
	 shftr_i = 8'b00000000;
          cntr_i = 4'b0000;
      end
      else begin
	 if (char_load) begin
       if(charlen_data == 4'b0000) begin
         cntr_i = 4'b0111;
         shftr_i = charcode_data;
       end
       else begin
	   shftr_i = charcode_data;
       cntr_i = charlen_data;
       end
	 end
	 else begin
	    if (shft_cnt) begin
          if(cntr_o == 4'b0000) begin
			cntr_i = cntr_o;
            shftr_i = shftr_o;
          end
          else begin
            shftr_i = shftr_o << 1;
            cntr_i = cntr_o - 4'b0001;
          end
	    end
	    else begin
          if(charlen_data == 4'b0000) begin
             cntr_i = cntr_o - 4'b0001;
          end
          else begin
	    shftr_i = shftr_o;
        cntr_i = cntr_o;
          end
	    end
	 end
      end
   end

   assign cntr_data = cntr_o;
   assign shft_data = shftr_o[7];
   
endmodule
module code_reg(
		input [7:0]  charcode_data,
		input [3:0]  charlen_data,
		input 	     char_load, shft_cnt,
		output [3:0] cntr_data, 
		output 	     shft_data,
		input 	     reset, clock
		 );





   reg [7:0] 	     shftr_o, shftr_i;
   reg [3:0] 	     cntr_o, cntr_i;

   always @(posedge clock) begin
      shftr_o <= shftr_i;
      cntr_o <= cntr_i;
   end

   wire		     shft_data;
   wire [3:0] 	     cntr_data;

   always @(*) begin
      if (reset) begin
	 shftr_i = 8'b00000000;
          cntr_i = 4'b0000;
      end
      else begin
	 if (char_load) begin
       if(charlen_data == 4'b0000) begin
         cntr_i = 4'b0111;
         shftr_i = charcode_data;
       end
       else begin
	   shftr_i = charcode_data;
       cntr_i = charlen_data;
       end
	 end
	 else begin
	    if (shft_cnt) begin
          if(cntr_o == 4'b0000) begin
			cntr_i = cntr_o;
            shftr_i = shftr_o;
          end
          else begin
            shftr_i = shftr_o << 1;
            cntr_i = cntr_o - 4'b0001;
          end
	    end
	    else begin
          if(charlen_data == 4'b0000) begin
             cntr_i = cntr_o - 4'b0001;
          end
          else begin
	    shftr_i = shftr_o;
        cntr_i = cntr_o;
          end
	    end
	 end
      end
   end

   assign cntr_data = cntr_o;
   assign shft_data = shftr_o[7];
   
endmodule