data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v
1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                         ^~~~~~\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                               ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                      ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                 ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                            ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                       ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                                  ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                                             ^\n%Error: Exiting due to 8 warning(s)\n'
module seven_segment(
    input [3:0] data,
    output reg [6:0] a2g
    );
    
    always @(*)
    case(data)
        'h0: a2g = 7'b1000000; 
        'h1: a2g = 7'b1111001; 
        'h2: a2g = 7'b0100100; 
        'h3: a2g = 7'b0110000; 
        'h4: a2g = 7'b0011001; 
        'h5: a2g = 7'b0010010; 
        'h6: a2g = 7'b0000010; 
        'h7: a2g = 7'b1111000; 
        'h8: a2g = 7'b0000000; 
        'h9: a2g = 7'b0011000; 
        default: a2g = 7'b1000000;
    endcase
endmodule
module seven_segment(
    input [3:0] data,
    output reg [6:0] a2g
    );

    
    always @(*)
    case(data)
        'h0: a2g = 7'b1000000; 
        'h1: a2g = 7'b1111001; 
        'h2: a2g = 7'b0100100; 
        'h3: a2g = 7'b0110000; 
        'h4: a2g = 7'b0011001; 
        'h5: a2g = 7'b0010010; 
        'h6: a2g = 7'b0000010; 
        'h7: a2g = 7'b1111000; 
        'h8: a2g = 7'b0000000; 
        'h9: a2g = 7'b0011000; 
        default: a2g = 7'b1000000;
    endcase
endmodule