data/full_repos/permissive/123796236/pipeline_control.v
1: b'%Error: data/full_repos/permissive/123796236/pipeline_control.v:91: Unsupported or unknown PLI call: $monitor\n  $monitor("opcode = %b\\n----\\nRegDst = %b\\nBranch = %b\\njump = %b\\nRegWrite = %b\\nALUSrc = %b\\nMemRead = %b\\nMemWrite = %b\\nMemtoReg = %b\\nALUOp = %b\\n****\\n",\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/123796236/pipeline_control.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123796236/pipeline_control.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/pipeline_control.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/pipeline_control.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_unit(opcode, RegDst, Branch, jump, RegWrite, ALUSrc, ALUOp,
	MemRead, MemWrite, MemtoReg);	 
	
	input wire [5:0] opcode;
	output reg RegDst, Branch, jump, RegWrite, ALUSrc,
	MemRead, MemWrite, MemtoReg;
	output reg [1:0] ALUOp;
	
	always@(*)
		begin
		case(opcode)   

			6'b000000:	begin
						RegDst   = 1'b1;
						ALUSrc   = 1'b0;
						MemtoReg = 1'b0;
						RegWrite = 1'b1;
						MemRead  = 1'b0;
						MemWrite = 1'b0;
						Branch   = 1'b0;
						jump	 = 1'b0;
						ALUOp[1] = 1'b1;
						ALUOp[0] = 1'b0;
			end

			 6'b100011: begin
						RegDst   = 1'b0;
						ALUSrc   = 1'b1;
						MemtoReg = 1'b1;
						RegWrite = 1'b1;
						MemRead  = 1'b1;
						MemWrite = 1'b0;
						Branch   = 1'b0;
						jump	 = 1'b0;
						ALUOp[1] = 1'b0;
						ALUOp[0] = 1'b0;
			 end		

			 6'b101011:	begin
				 		RegDst   = 1'bx;
						ALUSrc   = 1'b1;
						MemtoReg = 1'bx;
						RegWrite = 1'b0;
						MemRead  = 1'b0;
						MemWrite = 1'b1;
						Branch   = 1'b0; 
						jump	 = 1'b0;
						ALUOp[1] = 1'b0;
						ALUOp[0] = 1'b0;
			 end   

			 6'b000100: begin
				 		RegDst   = 1'bx;
						ALUSrc   = 1'b0;
						MemtoReg = 1'bx;
						RegWrite = 1'b0;
						MemRead  = 1'b0;
						MemWrite = 1'b0;
						Branch   = 1'b1;
						jump	 = 1'b0;
						ALUOp[1] = 1'b0;
						ALUOp[0] = 1'b1;
			 end	

			 6'b000010: begin
				 		RegDst   = 1'bx;
						ALUSrc   = 1'bx;
						MemtoReg = 1'bx;
						RegWrite = 1'bx;
						MemRead  = 1'bx;
						MemWrite = 1'bx;
						Branch   = 1'bx;
						jump	 = 1'b1;
						ALUOp[1] = 1'bx;
						ALUOp[0] = 1'bx;
			 end
			endcase
		end
endmodule
module control_unit(opcode, RegDst, Branch, jump, RegWrite, ALUSrc, ALUOp,
	MemRead, MemWrite, MemtoReg);
	 
	
	input wire [5:0] opcode;
	output reg RegDst, Branch, jump, RegWrite, ALUSrc,
	MemRead, MemWrite, MemtoReg;
	output reg [1:0] ALUOp;
	
	always@(*)
		begin
		case(opcode)   

			6'b000000:	begin
						RegDst   = 1'b1;
						ALUSrc   = 1'b0;
						MemtoReg = 1'b0;
						RegWrite = 1'b1;
						MemRead  = 1'b0;
						MemWrite = 1'b0;
						Branch   = 1'b0;
						jump	 = 1'b0;
						ALUOp[1] = 1'b1;
						ALUOp[0] = 1'b0;
			end

			 6'b100011: begin
						RegDst   = 1'b0;
						ALUSrc   = 1'b1;
						MemtoReg = 1'b1;
						RegWrite = 1'b1;
						MemRead  = 1'b1;
						MemWrite = 1'b0;
						Branch   = 1'b0;
						jump	 = 1'b0;
						ALUOp[1] = 1'b0;
						ALUOp[0] = 1'b0;
			 end		

			 6'b101011:	begin
				 		RegDst   = 1'bx;
						ALUSrc   = 1'b1;
						MemtoReg = 1'bx;
						RegWrite = 1'b0;
						MemRead  = 1'b0;
						MemWrite = 1'b1;
						Branch   = 1'b0; 
						jump	 = 1'b0;
						ALUOp[1] = 1'b0;
						ALUOp[0] = 1'b0;
			 end   

			 6'b000100: begin
				 		RegDst   = 1'bx;
						ALUSrc   = 1'b0;
						MemtoReg = 1'bx;
						RegWrite = 1'b0;
						MemRead  = 1'b0;
						MemWrite = 1'b0;
						Branch   = 1'b1;
						jump	 = 1'b0;
						ALUOp[1] = 1'b0;
						ALUOp[0] = 1'b1;
			 end	

			 6'b000010: begin
				 		RegDst   = 1'bx;
						ALUSrc   = 1'bx;
						MemtoReg = 1'bx;
						RegWrite = 1'bx;
						MemRead  = 1'bx;
						MemWrite = 1'bx;
						Branch   = 1'bx;
						jump	 = 1'b1;
						ALUOp[1] = 1'bx;
						ALUOp[0] = 1'bx;
			 end
			endcase
		end
endmodule