data/full_repos/permissive/20270692/labs/lab7/res/mux21a.v
data/verilator_xmls/5ad63753-af95-49ef-a77b-b714e754cf98.xml
module mux21a (a,b,s,y);


  input a,b,s;
  wire a,b,s;
  output y;
  wire y;
  wire sb, w1, w2;


  and A1(w1,a,sb);
  and A2(w2,s,b);
  not N1(sb,s);
  or O1(y,w1,w2);

endmodule
module mux21a (a,b,s,y);



  input a,b,s;
  wire a,b,s;
  output y;
  wire y;
  wire sb, w1, w2;


  and A1(w1,a,sb);
  and A2(w2,s,b);
  not N1(sb,s);
  or O1(y,w1,w2);

endmodule