data/full_repos/permissive/136584400/lab04&05-Data_path_and_FSM/sources/latch.v
data/verilator_xmls/adaf36b7-59c1-4b42-8310-a647ac195e62.xml
module latch(clk, rst, ld, d, q);
  parameter WIDTH = 32;

  input clk, rst, ld;
  input [WIDTH-1:0] d;
  output reg [WIDTH-1:0] q;

initial begin
  q <= 0;
end

always @(posedge clk) begin
  if (rst)
    q <= 0;
  else if (ld)
    q <= d;
end
endmodule
module latch(clk, rst, ld, d, q);

  parameter WIDTH = 32;

  input clk, rst, ld;
  input [WIDTH-1:0] d;
  output reg [WIDTH-1:0] q;

initial begin
  q <= 0;
end

always @(posedge clk) begin
  if (rst)
    q <= 0;
  else if (ld)
    q <= d;
end
endmodule