data/full_repos/permissive/200478172/source/dmem.v
data/verilator_xmls/b7d24e90-6cd8-40cb-b558-d9142e55f55f.xml
module dmem(
    input [7:0] addr,
    input [31:0] wdata,
    input clk,
    input [1:0] DM_W,
    output [31:0] rdata
    );
    reg [7:0] ram [255:0];
    reg [31:0] temp;
    always @(negedge clk)
    begin
        if(DM_W==2'b01)
        begin
            ram[addr]<=wdata[7:0];
            ram[addr+1]<=wdata[15:8];
            ram[addr+2]<=wdata[23:16];
            ram[addr+3]<=wdata[31:24];
            temp<=wdata;
        end
        else if(DM_W==2'b10)
        begin
            ram[addr]<=wdata[7:0];
            ram[addr+1]<=wdata[15:8];
            temp<=wdata;    
        end
        else if(DM_W==2'b11)
        begin
            ram[addr]<=wdata[7:0];
            temp<=wdata;
        end
        else begin
            temp<={ram[addr+3],ram[addr+2],ram[addr+1],ram[addr]};
        end
    end
    assign rdata=temp;
endmodule
module dmem(
    input [7:0] addr,
    input [31:0] wdata,
    input clk,
    input [1:0] DM_W,
    output [31:0] rdata
    );

    reg [7:0] ram [255:0];
    reg [31:0] temp;
    always @(negedge clk)
    begin
        if(DM_W==2'b01)
        begin
            ram[addr]<=wdata[7:0];
            ram[addr+1]<=wdata[15:8];
            ram[addr+2]<=wdata[23:16];
            ram[addr+3]<=wdata[31:24];
            temp<=wdata;
        end
        else if(DM_W==2'b10)
        begin
            ram[addr]<=wdata[7:0];
            ram[addr+1]<=wdata[15:8];
            temp<=wdata;    
        end
        else if(DM_W==2'b11)
        begin
            ram[addr]<=wdata[7:0];
            temp<=wdata;
        end
        else begin
            temp<={ram[addr+3],ram[addr+2],ram[addr+1],ram[addr]};
        end
    end
    assign rdata=temp;
endmodule