data/full_repos/permissive/101423580/v/MUX2T1_4.v
data/verilator_xmls/632f423a-5947-4e2d-8f72-f308a0ff2478.xml
module MUX2T1_4( input S,
					input [3:0]D0,
					input [3:0]D1,
					output reg [3:0]Dout
    );
	 
	 always @ * begin
		case(S)
			1'd0: Dout <= D0;
			1'd1: Dout <= D1;
			default: ;
		endcase
	end


endmodule
module MUX2T1_4( input S,
					input [3:0]D0,
					input [3:0]D1,
					output reg [3:0]Dout
    );

	 
	 always @ * begin
		case(S)
			1'd0: Dout <= D0;
			1'd1: Dout <= D1;
			default: ;
		endcase
	end


endmodule