data/full_repos/permissive/174323821/hdl/cpu/j68/j68_loop.v
None: at end of input
data/verilator_xmls/d626412a-cb1d-4e6a-b6ef-f291ee06eef2.xml
module j68_loop
(

    input             rst,
    input             clk,
input clk_ena,

    input      [19:0] inst_in,
    input             i_fetch,
    input      [5:0]  a_src,
    input      [10:0] pc_in,
    output     [10:0] pc_out,
    output            branch,
    output            skip,
    output      [3:0] lcount
);

    reg [10:0] r_loop_st;
    reg [10:0] r_loop_end;
    reg  [5:0] r_loop_cnt;
    reg        r_loop_ena;
    reg        r_branch;
    reg  [3:0] r_lcount;

    always @(posedge rst or posedge clk) begin : HW_LOOP
    
        if (rst) begin
            r_loop_st   = 11'd0;
            r_loop_end  = 11'd0;
            r_loop_cnt  = 6'd0;
            r_loop_ena  = 1'b0;
            r_branch   <= 1'b0;
            r_lcount   <= 4'd0;
        end
        else if (clk_ena) begin

            if (inst_in[19:17] == 3'b000) begin

                r_loop_st  = pc_in;

                r_loop_end = inst_in[10:0];
                if (inst_in[11]) begin

                    r_loop_cnt = a_src[5:0] - 6'd1;

                    r_loop_ena = ~skip;
                end
                else begin

                    r_loop_cnt = 6'd15;

                    r_loop_ena = 1'b1;
                end
            end

            r_lcount <= r_loop_cnt[3:0];
            
            if (r_loop_ena) begin
                if (i_fetch) begin

                    if (r_loop_end == pc_in) begin
                        if (r_loop_cnt == 6'd0) begin

                            r_branch   <= 1'b0;
                            r_loop_ena  = 1'b0;
                        end
                        else begin

                            r_branch   <= 1'b1;
                            r_loop_cnt  = r_loop_cnt - 6'd1;
                        end
                    end
                    else begin
                        r_branch <= 1'b0;
                    end
                end
            end
            else begin
                r_branch <= 1'b0;
            end
        end
    end
  
    assign branch = r_branch;
    assign lcount = r_lcount;

    assign pc_out = r_loop_st;

    assign skip   = (a_src[5:0] == 6'd0) ? inst_in[11] : 1'b0;

endmodule
module j68_loop
(

    input             rst,
    input             clk,
input clk_ena,

    input      [19:0] inst_in,
    input             i_fetch,
    input      [5:0]  a_src,
    input      [10:0] pc_in,
    output     [10:0] pc_out,
    output            branch,
    output            skip,
    output      [3:0] lcount
);


    reg [10:0] r_loop_st;
    reg [10:0] r_loop_end;
    reg  [5:0] r_loop_cnt;
    reg        r_loop_ena;
    reg        r_branch;
    reg  [3:0] r_lcount;

    always @(posedge rst or posedge clk) begin : HW_LOOP
    
        if (rst) begin
            r_loop_st   = 11'd0;
            r_loop_end  = 11'd0;
            r_loop_cnt  = 6'd0;
            r_loop_ena  = 1'b0;
            r_branch   <= 1'b0;
            r_lcount   <= 4'd0;
        end
        else if (clk_ena) begin

            if (inst_in[19:17] == 3'b000) begin

                r_loop_st  = pc_in;

                r_loop_end = inst_in[10:0];
                if (inst_in[11]) begin

                    r_loop_cnt = a_src[5:0] - 6'd1;

                    r_loop_ena = ~skip;
                end
                else begin

                    r_loop_cnt = 6'd15;

                    r_loop_ena = 1'b1;
                end
            end

            r_lcount <= r_loop_cnt[3:0];
            
            if (r_loop_ena) begin
                if (i_fetch) begin

                    if (r_loop_end == pc_in) begin
                        if (r_loop_cnt == 6'd0) begin

                            r_branch   <= 1'b0;
                            r_loop_ena  = 1'b0;
                        end
                        else begin

                            r_branch   <= 1'b1;
                            r_loop_cnt  = r_loop_cnt - 6'd1;
                        end
                    end
                    else begin
                        r_branch <= 1'b0;
                    end
                end
            end
            else begin
                r_branch <= 1'b0;
            end
        end
    end
  
    assign branch = r_branch;
    assign lcount = r_lcount;

    assign pc_out = r_loop_st;

    assign skip   = (a_src[5:0] == 6'd0) ? inst_in[11] : 1'b0;

endmodule