data/full_repos/permissive/120845848/001-counter/src/counter.v
data/verilator_xmls/b65e975d-908e-4322-83c3-42679e748c5e.xml
module counter(clk,en,nclr,countv);
	input clk;
	input en;
	input nclr;
	output [3:0]countv;
	
	reg [3:0]cnt;
	
	always@(posedge clk,negedge nclr)
	if (!nclr)
		cnt <= 4'd0;
	else if(en)
		cnt <= cnt + 4'd1;
	
	assign countv = cnt;

endmodule
module counter(clk,en,nclr,countv);

	input clk;
	input en;
	input nclr;
	output [3:0]countv;
	
	reg [3:0]cnt;
	
	always@(posedge clk,negedge nclr)
	if (!nclr)
		cnt <= 4'd0;
	else if(en)
		cnt <= cnt + 4'd1;
	
	assign countv = cnt;

endmodule