data/full_repos/permissive/208741034/ip_core/sim/ipcore.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/208741034/ip_core/sim/ipcore.v:17: Unsupported: Ignoring delay on this delayed statement.\nalways #(SYSPERIOD / 2) begin\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/208741034/ip_core/sim/ipcore.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #(20 * SYSPERIOD)\n    ^\n%Error: data/full_repos/permissive/208741034/ip_core/sim/ipcore.v:31: Cannot find file containing module: \'ip_pll\'\nip_pll   u_ip_pll(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208741034/ip_core/sim,data/full_repos/permissive/208741034/ip_pll\n             data/full_repos/permissive/208741034/ip_core/sim,data/full_repos/permissive/208741034/ip_pll.v\n             data/full_repos/permissive/208741034/ip_core/sim,data/full_repos/permissive/208741034/ip_pll.sv\n             ip_pll\n             ip_pll.v\n             ip_pll.sv\n             obj_dir/ip_pll\n             obj_dir/ip_pll.v\n             obj_dir/ip_pll.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ipcore;

parameter SYSPERIOD = 20 ;

reg clk;
reg rst_n;


wire clk1;
wire clk2;
wire clk3;
wire clk4;


always #(SYSPERIOD / 2) begin
    clk <= ~clk;
    
end


initial begin
    clk <= 1'b0;
    rst_n <= 1'b0;

    #(20 * SYSPERIOD)
    rst_n <= 1'b1;
end

ip_pll   u_ip_pll(

.clk   (clk),
.rst_n (rst_n),
.clk1  (clk1),
.clk2  (clk2),
.clk3  (clk3),
.clk4  (clk4)
);


endmodule
module ipcore;


parameter SYSPERIOD = 20 ;

reg clk;
reg rst_n;


wire clk1;
wire clk2;
wire clk3;
wire clk4;


always #(SYSPERIOD / 2) begin
    clk <= ~clk;
    
end


initial begin
    clk <= 1'b0;
    rst_n <= 1'b0;

    #(20 * SYSPERIOD)
    rst_n <= 1'b1;
end

ip_pll   u_ip_pll(

.clk   (clk),
.rst_n (rst_n),
.clk1  (clk1),
.clk2  (clk2),
.clk3  (clk3),
.clk4  (clk4)
);


endmodule