data/full_repos/permissive/204736068/SoM/RTL/servo/servo.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/204736068/SoM/RTL/servo/servo.sv:26: Operator EQ expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'clk_ctr\' generates 8 bits.\n                                                                              : ... In instance servo\n    always @(posedge clk) tick <= (clk_ctr == CLK_COUNT-2);\n                                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module servo
#(

    parameter CLK_FREQUENCY = 12000000
)
(
    input logic clk,
    input logic rst,
    input logic [7:0] pos,
    output logic pwm
);

    localparam CLK_COUNT = CLK_FREQUENCY/(256*1000);


    logic [7:0] clk_ctr;
    logic tick;


    always @(posedge clk) tick <= (clk_ctr == CLK_COUNT-2);

    always @(posedge clk) 
    if (rst | tick)
        clk_ctr <= '0;
    else
        clk_ctr <= clk_ctr + 'd1;


    logic [11:0] pwm_ctr;
    always @(posedge clk)
    if (rst)
        pwm_ctr <= '0;
    else if (tick)
        pwm_ctr <= pwm_ctr + 'd1;


    always @(posedge clk)
        pwm <= (pwm_ctr < {4'b0001, pos});    

endmodule
module servo
#(

    parameter CLK_FREQUENCY = 12000000
)
(
    input logic clk,
    input logic rst,
    input logic [7:0] pos,
    output logic pwm
);


    localparam CLK_COUNT = CLK_FREQUENCY/(256*1000);


    logic [7:0] clk_ctr;
    logic tick;


    always @(posedge clk) tick <= (clk_ctr == CLK_COUNT-2);

    always @(posedge clk) 
    if (rst | tick)
        clk_ctr <= '0;
    else
        clk_ctr <= clk_ctr + 'd1;


    logic [11:0] pwm_ctr;
    always @(posedge clk)
    if (rst)
        pwm_ctr <= '0;
    else if (tick)
        pwm_ctr <= pwm_ctr + 'd1;


    always @(posedge clk)
        pwm <= (pwm_ctr < {4'b0001, pos});    

endmodule