data/full_repos/permissive/18477150/lib/shared/sonic_common_logic_vector_delay.sv
 line:33: before: ";"
data/verilator_xmls/25a379cc-9b94-4618-a11c-e12a57b4c654.xml
module sonic_common_logic_vector_delay # (
	parameter WIDTH = 1,
	parameter DELAY = 0
	)(

	input logic clock,
	input logic reset,
	input logic ena,

	input logic [WIDTH-1:0] data,
	output logic [WIDTH-1:0] q
	);
	
	int i;

	generate 

		if (DELAY == 1'b0) begin
			assign q = data;
		end


		else begin
			logic [WIDTH-1:0] shift_register [0:DELAY-1];
			
			always @ (posedge reset or posedge clock) begin
				if (reset == 1'b1) begin
					for (int i = 0; i < DELAY; i++)
						shift_register[i] <= {WIDTH{1'b0}};
				end
				else begin
					if (ena == 1'b1) begin
						for (i = 0; i <= DELAY-2; i=i+1) begin
							shift_register[i] <= shift_register[i+1];
						end
						shift_register[DELAY-1] <= data;
					end
				end
			end

			assign q = shift_register[0];
		end
	endgenerate
endmodule
module sonic_common_logic_vector_delay # (
	parameter WIDTH = 1,
	parameter DELAY = 0
	)(

	input logic clock,
	input logic reset,
	input logic ena,

	input logic [WIDTH-1:0] data,
	output logic [WIDTH-1:0] q
	);

	
	int i;

	generate 

		if (DELAY == 1'b0) begin
			assign q = data;
		end


		else begin
			logic [WIDTH-1:0] shift_register [0:DELAY-1];
			
			always @ (posedge reset or posedge clock) begin
				if (reset == 1'b1) begin
					for (int i = 0; i < DELAY; i++)
						shift_register[i] <= {WIDTH{1'b0}};
				end
				else begin
					if (ena == 1'b1) begin
						for (i = 0; i <= DELAY-2; i=i+1) begin
							shift_register[i] <= shift_register[i+1];
						end
						shift_register[DELAY-1] <= data;
					end
				end
			end

			assign q = shift_register[0];
		end
	endgenerate
endmodule