data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/parallel_interface.v
1: b'%Error: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/parallel_interface.v:176: Unsupported: fork statements\n always @(negedge scaler[8]) fork  \n                             ^~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module parallel_interface(

    input rst_n,
    input clk,
    

    input [15:0] sw,
    output reg [15:0] led_out_hardware,
    input [4:0] buttons,
    output [7:0] seg,
    output [3:0] an,
    

    input read_enable,
    input write_enable,
    inout [31:0] data_bus,
    input [19:0] address_bus,
    

    output parallel_irq_n
    );


	reg [1:0] control = 0;
	wire interrupt_enable = control[1];
	wire hex_decode = control[0];


	reg int_ack = 0;


	reg [15:0] old_sw[1:0];
	reg [4:0] old_buttons[1:0];


	reg [7:0] ssd_values[3:0];
	

	reg [1:0] index;
	reg [9:0] scaler;
	reg [7:0] SSDraw;
    reg [7:0] SSDhex;
    reg [3:0] anode;
    reg [7:0] SSDout;
    
    assign an = anode;
    assign seg = hex_decode ? SSDhex : ~SSDraw[7:0];

	reg [31:0] data;
	assign data_bus = read_enable ? data : 32'hzzzzzzzz;

	assign parallel_irq_n = ~int_ack;

    initial begin
	    led_out_hardware = 0;
	    index = 0;
	    scaler = 0;
	    control = 1;
	    ssd_values[0] = 0;
	    ssd_values[1] = 0;
	    ssd_values[2] = 0;
	    ssd_values[3] = 0;
	end


    always @(posedge clk) begin
        old_sw[1] = old_sw[0];
        old_sw[0] = sw;
        old_buttons[1] = old_buttons[0];
        old_buttons[0] = buttons[3:1];
    end
    
    wire sw_or_buttons_changed = 
        old_sw[1] != old_sw[0] ||
        old_buttons[1] != old_buttons[0];



	always @(posedge clk) begin
		if (!rst_n) begin
		    data = 0;
		    control = 1;
		    int_ack = 0;
		    led_out_hardware = 0;
		    ssd_values[0] = 0;
		    ssd_values[1] = 0;
		    ssd_values[2] = 0;
		    ssd_values[3] = 0;
		end
		
		if (sw_or_buttons_changed && interrupt_enable) begin
            int_ack = 1;
		end
        
	  	scaler = scaler + 1;
		data = 32'h00000000;
		case (address_bus[11:0])
		    0: begin
		        data[15:0] = sw;
		    end

		    1: begin
		        data[4:0] = buttons[3:1];
		    end

		    4: begin
		        if (write_enable)
		            control = data_bus[1:0];
		        else data[1:0] = control;
		    end

		    5: begin
		        if (write_enable)
		            int_ack = data_bus[0];
		        else data[0] = int_ack;
		    end

		    6: begin
		        if (write_enable)
		            ssd_values[0] = data_bus[7:0];
		        else data[7:0] = ssd_values[0];
		    end
		    7: begin
		        if (write_enable)
		            ssd_values[1] = data_bus[7:0];
		        else data[7:0] = ssd_values[1];
		    end


		    2, 8: begin
		        if (write_enable)
		            ssd_values[2] = data_bus[7:0];
		        else data[7:0] = ssd_values[2];
		    end


		    3, 9: begin
		        if (write_enable)
		            ssd_values[3] = data_bus[7:0];
		        else data[7:0] = ssd_values[3];
		    end

		    10: begin
		        if (write_enable)
		            led_out_hardware = data_bus[15:0];
		        else data[15:0] = led_out_hardware;
		    end
		endcase
	end



	always @(negedge scaler[8]) fork
	
	    case (index)
	        2'b00   : SSDraw = ssd_values[0];
	        2'b01   : SSDraw = ssd_values[1];
	        2'b10   : SSDraw = ssd_values[2];
	        2'b11   : SSDraw = ssd_values[3];
	    endcase
	            
	    case (SSDraw[3:0])
	        4'h0: SSDhex = 8'b11000000;
	        4'h1: SSDhex = 8'b11111001;
	        4'h2: SSDhex = 8'b10100100;
	        4'h3: SSDhex = 8'b10110000;
	        4'h4: SSDhex = 8'b10011001;
	        4'h5: SSDhex = 8'b10010010;
	        4'h6: SSDhex = 8'b10000010;
	        4'h7: SSDhex = 8'b11111000;
	        4'h8: SSDhex = 8'b10000000;
	        4'h9: SSDhex = 8'b10010000;
	        4'hA: SSDhex = 8'b10001000;
	        4'hB: SSDhex = 8'b10000011;
	        4'hC: SSDhex = 8'b11000110;
	        4'hD: SSDhex = 8'b10100001;
	        4'hE: SSDhex = 8'b10000110;
	        4'hF: SSDhex = 8'b10001110;
	    endcase
	    
	    case(index)
	        2'b00 : anode = 4'b0111;
	        2'b01 : anode = 4'b1011;
	        2'b10 : anode = 4'b1101;
	        2'b11 : anode = 4'b1110;
	    endcase
	    
	    index = index + 1;    
	join
    
endmodule
module parallel_interface(

    input rst_n,
    input clk,
    

    input [15:0] sw,
    output reg [15:0] led_out_hardware,
    input [4:0] buttons,
    output [7:0] seg,
    output [3:0] an,
    

    input read_enable,
    input write_enable,
    inout [31:0] data_bus,
    input [19:0] address_bus,
    

    output parallel_irq_n
    );



	reg [1:0] control = 0;
	wire interrupt_enable = control[1];
	wire hex_decode = control[0];


	reg int_ack = 0;


	reg [15:0] old_sw[1:0];
	reg [4:0] old_buttons[1:0];


	reg [7:0] ssd_values[3:0];
	

	reg [1:0] index;
	reg [9:0] scaler;
	reg [7:0] SSDraw;
    reg [7:0] SSDhex;
    reg [3:0] anode;
    reg [7:0] SSDout;
    
    assign an = anode;
    assign seg = hex_decode ? SSDhex : ~SSDraw[7:0];

	reg [31:0] data;
	assign data_bus = read_enable ? data : 32'hzzzzzzzz;

	assign parallel_irq_n = ~int_ack;

    initial begin
	    led_out_hardware = 0;
	    index = 0;
	    scaler = 0;
	    control = 1;
	    ssd_values[0] = 0;
	    ssd_values[1] = 0;
	    ssd_values[2] = 0;
	    ssd_values[3] = 0;
	end


    always @(posedge clk) begin
        old_sw[1] = old_sw[0];
        old_sw[0] = sw;
        old_buttons[1] = old_buttons[0];
        old_buttons[0] = buttons[3:1];
    end
    
    wire sw_or_buttons_changed = 
        old_sw[1] != old_sw[0] ||
        old_buttons[1] != old_buttons[0];



	always @(posedge clk) begin
		if (!rst_n) begin
		    data = 0;
		    control = 1;
		    int_ack = 0;
		    led_out_hardware = 0;
		    ssd_values[0] = 0;
		    ssd_values[1] = 0;
		    ssd_values[2] = 0;
		    ssd_values[3] = 0;
		end
		
		if (sw_or_buttons_changed && interrupt_enable) begin
            int_ack = 1;
		end
        
	  	scaler = scaler + 1;
		data = 32'h00000000;
		case (address_bus[11:0])
		    0: begin
		        data[15:0] = sw;
		    end

		    1: begin
		        data[4:0] = buttons[3:1];
		    end

		    4: begin
		        if (write_enable)
		            control = data_bus[1:0];
		        else data[1:0] = control;
		    end

		    5: begin
		        if (write_enable)
		            int_ack = data_bus[0];
		        else data[0] = int_ack;
		    end

		    6: begin
		        if (write_enable)
		            ssd_values[0] = data_bus[7:0];
		        else data[7:0] = ssd_values[0];
		    end
		    7: begin
		        if (write_enable)
		            ssd_values[1] = data_bus[7:0];
		        else data[7:0] = ssd_values[1];
		    end


		    2, 8: begin
		        if (write_enable)
		            ssd_values[2] = data_bus[7:0];
		        else data[7:0] = ssd_values[2];
		    end


		    3, 9: begin
		        if (write_enable)
		            ssd_values[3] = data_bus[7:0];
		        else data[7:0] = ssd_values[3];
		    end

		    10: begin
		        if (write_enable)
		            led_out_hardware = data_bus[15:0];
		        else data[15:0] = led_out_hardware;
		    end
		endcase
	end



	always @(negedge scaler[8]) fork
	
	    case (index)
	        2'b00   : SSDraw = ssd_values[0];
	        2'b01   : SSDraw = ssd_values[1];
	        2'b10   : SSDraw = ssd_values[2];
	        2'b11   : SSDraw = ssd_values[3];
	    endcase
	            
	    case (SSDraw[3:0])
	        4'h0: SSDhex = 8'b11000000;
	        4'h1: SSDhex = 8'b11111001;
	        4'h2: SSDhex = 8'b10100100;
	        4'h3: SSDhex = 8'b10110000;
	        4'h4: SSDhex = 8'b10011001;
	        4'h5: SSDhex = 8'b10010010;
	        4'h6: SSDhex = 8'b10000010;
	        4'h7: SSDhex = 8'b11111000;
	        4'h8: SSDhex = 8'b10000000;
	        4'h9: SSDhex = 8'b10010000;
	        4'hA: SSDhex = 8'b10001000;
	        4'hB: SSDhex = 8'b10000011;
	        4'hC: SSDhex = 8'b11000110;
	        4'hD: SSDhex = 8'b10100001;
	        4'hE: SSDhex = 8'b10000110;
	        4'hF: SSDhex = 8'b10001110;
	    endcase
	    
	    case(index)
	        2'b00 : anode = 4'b0111;
	        2'b01 : anode = 4'b1011;
	        2'b10 : anode = 4'b1101;
	        2'b11 : anode = 4'b1110;
	    endcase
	    
	    index = index + 1;    
	join
    
endmodule