data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v
1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n             char_def.vh\n             char_def.vh.v\n             char_def.vh.sv\n             obj_dir/char_def.vh\n             obj_dir/char_def.vh.v\n             obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:58: Define or directive not defined: \'`Wait1_e\'\n    assign fin = (current_state == `Wait1_e) ? 1 : 0;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:58: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign fin = (current_state == `Wait1_e) ? 1 : 0;\n                                           ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:87: Define or directive not defined: \'`Idle_e\'\n            current_state <= `Idle_e;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:87: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            current_state <= `Idle_e;\n                                    ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:88: Define or directive not defined: \'`Idle_e\'\n            after_state <= `Idle_e;\n                           ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            after_state <= `Idle_e;\n                                  ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:89: Define or directive not defined: \'`Idle_e\'\n            after_page_state <= `Idle_e;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:89: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            after_page_state <= `Idle_e;\n                                       ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:90: Define or directive not defined: \'`Idle_e\'\n            after_char_state <= `Idle_e;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:90: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            after_char_state <= `Idle_e;\n                                       ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:91: Define or directive not defined: \'`Idle_e\'\n            after_update_state <= `Idle_e;\n                                  ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            after_update_state <= `Idle_e;\n                                         ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:103: Define or directive not defined: \'`Idle_e\'\n                `Idle_e: begin\n                ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:103: syntax error, unexpected \':\', expecting endcase\n                `Idle_e: begin\n                       ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:105: Define or directive not defined: \'`ClearDC\'\n                        current_state <= `ClearDC;\n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:106: Define or directive not defined: \'`STR1\'\n                        after_page_state <= `STR1;\n                                            ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:106: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                        after_page_state <= `STR1;\n                                                 ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:111: Define or directive not defined: \'`STR1\'\n                `STR1: begin\n                ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:111: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `STR1: begin\n                       ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:112: Define or directive not defined: \'`UpdateScreen\'\n                    current_state <= `UpdateScreen;\n                                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:113: Define or directive not defined: \'`Wait1_e\'\n                    after_update_state <= `Wait1_e;\n                                          ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:113: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    after_update_state <= `Wait1_e;\n                                                  ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:118: Define or directive not defined: \'`Wait1_e\'\n                `Wait1_e: begin\n                ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:118: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `Wait1_e: begin\n                          ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:120: Define or directive not defined: \'`Idle_e\'\n                        current_state <= `Idle_e;\n                                         ^~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:123: Define or directive not defined: \'`Transition3_e\'\n                        current_state <= `Transition3_e;\n                                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:124: Define or directive not defined: \'`STR1\'\n                        after_state <= `STR1;\n                                       ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:128: Define or directive not defined: \'`UpdateScreen\'\n                `UpdateScreen: begin\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:130: Define or directive not defined: \'`SendChar1\'\n                    current_state <= `SendChar1;\n                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:132: syntax error, unexpected <=, expecting IDENTIFIER\n                        t_index <= 0;\n                                ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:134: Define or directive not defined: \'`ClearDC\'\n                        after_char_state <= `ClearDC;\n                                            ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:136: syntax error, unexpected <=, expecting IDENTIFIER\n                            after_page_state <= after_update_state;\n                                             ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:138: syntax error, unexpected <=, expecting IDENTIFIER\n                            after_page_state <= `UpdateScreen;\n                                             ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:138: Define or directive not defined: \'`UpdateScreen\'\n                            after_page_state <= `UpdateScreen;\n                                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:141: syntax error, unexpected <=, expecting IDENTIFIER\n                        t_index <= t_index + 1;\n                                ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:142: Define or directive not defined: \'`UpdateScreen\'\n                        after_char_state <= `UpdateScreen;\n                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:146: Define or directive not defined: \'`ClearDC\'\n                `ClearDC: begin\n                ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:148: Define or directive not defined: \'`SetPage\'\n                    current_state <= `SetPage;\n                                     ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:150: Define or directive not defined: \'`SetPage\'\n                `SetPage: begin\n                ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:152: Define or directive not defined: \'`Transition1_e\'\n                    current_state <= `Transition1_e;\n                                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:153: Define or directive not defined: \'`PageNum\'\n                    after_state <= `PageNum;\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:155: Define or directive not defined: \'`PageNum\'\n                `PageNum: begin\n                ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:157: Define or directive not defined: \'`Transition1_e\'\n                    current_state <= `Transition1_e;\n                                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:158: Define or directive not defined: \'`LeftColumn1\'\n                    after_state <= `LeftColumn1;\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:160: Define or directive not defined: \'`LeftColumn1\'\n                `LeftColumn1: begin\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:162: Define or directive not defined: \'`Transition1_e\'\n                    current_state <= `Transition1_e;\n                                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:163: Define or directive not defined: \'`LeftColumn2\'\n                    after_state <= `LeftColumn2;\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/oled_exam.v:165: Define or directive not defined: \'`LeftColumn2\'\n                `LeftColumn2: begin\n                ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module oled_exam(
    clk,
    rst,
    en,
    cs,
    sdo,
    sclk,
    dc,
    fin,
    char_data
    );
    input wire clk, rst, en;
    output wire cs, sdo, sclk, dc, fin;
    input wire [64*8-1:0] char_data;

    reg t_dc;
    reg [4:0] current_state, after_state, after_page_state,
                after_char_state, after_update_state;
    reg spi_en, delay_en;
    reg [7:0] spi_data;
    reg [7:0] current_screen [0:63];
    reg [11:0] delay_ms;

    reg [7:0] t_char;
    reg [10:0] t_addr;
    wire [7:0] dout;
    reg [1:0] t_page;
    reg [3:0] t_index;

    wire spi_fin, delay_fin;

    integer i;

    assign dc = t_dc;
    assign fin = (current_state == `Wait1_e) ? 1 : 0;

    spi_ctrl sctrl(
    .clk(clk),
    .rst(rst),
    .spi_en(spi_en),
    .spi_data(spi_data),
    .cs(cs),
    .sdo(sdo),
    .sclk(sclk),
    .spi_fin(spi_fin)
    );

    delay_gen dgen(
    .clk(clk),
    .rst(rst),
    .delay_ms(delay_ms),
    .delay_en(delay_en),
    .delay_fin(delay_fin)
    );

    char_rom crom(
    .rst(rst),
    .addr(t_addr),
    .dout(dout)
    );

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            current_state <= `Idle_e;
            after_state <= `Idle_e;
            after_page_state <= `Idle_e;
            after_char_state <= `Idle_e;
            after_update_state <= `Idle_e;
            spi_data <= 8'b0;
            delay_ms <= 12'b0;
            t_char <= 8'b0;
            t_addr <= 11'b0;
            t_page <= 2'b0;
            t_index <= 4'b0;
            t_dc <= 0;
            spi_en <= 0;
            delay_en <= 0;
        end else begin
            case(current_state)
                `Idle_e: begin
                    if(en) begin
                        current_state <= `ClearDC;
                        after_page_state <= `STR1;
                        t_page <= 2'b0;
                        t_index <= 4'b0;
                    end
                end
                `STR1: begin
                    current_state <= `UpdateScreen;
                    after_update_state <= `Wait1_e;
                    for(i=63;i>=0;i=i-1) begin
                        current_screen[63-i] <= char_data[(8*i) +: 7];
                    end
                end
                `Wait1_e: begin
                    if(!en) begin
                        current_state <= `Idle_e;
                    end else begin
                        delay_ms <= 12'b000001100100;
                        current_state <= `Transition3_e;
                        after_state <= `STR1;
                    end
                end

                `UpdateScreen: begin
                    t_char <= current_screen[t_page*16+t_index];
                    current_state <= `SendChar1;
                    if(t_index == 4'b1111) begin
                        t_index <= 0;
                        t_page <= t_page + 1;
                        after_char_state <= `ClearDC;
                        if(t_page == 2'b11) begin
                            after_page_state <= after_update_state;
                        end else begin
                            after_page_state <= `UpdateScreen;
                        end
                    end else begin
                        t_index <= t_index + 1;
                        after_char_state <= `UpdateScreen;
                    end
                end

                `ClearDC: begin
                    t_dc <= 0;
                    current_state <= `SetPage;
                end
                `SetPage: begin
                    spi_data <= 8'b00100010;
                    current_state <= `Transition1_e;
                    after_state <= `PageNum;
                end
                `PageNum: begin
                    spi_data <= {6'b000000, t_page};
                    current_state <= `Transition1_e;
                    after_state <= `LeftColumn1;
                end
                `LeftColumn1: begin
                    spi_data <= 8'b00000000;
                    current_state <= `Transition1_e;
                    after_state <= `LeftColumn2;
                end
                `LeftColumn2: begin
                    spi_data <= 8'b00010000;
                    current_state <= `Transition1_e;
                    after_state <= `SetDC;
                end
                `SetDC: begin
                    t_dc <= 1;
                    current_state <= after_page_state;
                end

                `SendChar1: begin
                    t_addr <= {t_char, 3'b000};
                    current_state <= `ReadMem;
                    after_state <= `SendChar2;
                end
                `SendChar2: begin
                    t_addr <= {t_char, 3'b001};
                    current_state <= `ReadMem;
                    after_state <= `SendChar3;
                end
                `SendChar3: begin
                    t_addr <= {t_char, 3'b010};
                    current_state <= `ReadMem;
                    after_state <= `SendChar4;
                end
                `SendChar4: begin
                    t_addr <= {t_char, 3'b011};
                    current_state <= `ReadMem;
                    after_state <= `SendChar5;
                end
                `SendChar5: begin
                    t_addr <= {t_char, 3'b100};
                    current_state <= `ReadMem;
                    after_state <= `SendChar6;
                end
                `SendChar6: begin
                    t_addr <= {t_char, 3'b101};
                    current_state <= `ReadMem;
                    after_state <= `SendChar7;
                end
                `SendChar7: begin
                    t_addr <= {t_char, 3'b110};
                    current_state <= `ReadMem;
                    after_state <= `SendChar8;
                end
                `SendChar8: begin
                    t_addr <= {t_char, 3'b111};
                    current_state <= `ReadMem;
                    after_state <= after_char_state;
                end
                `ReadMem: begin
                    current_state <= `ReadMem2;
                end
                `ReadMem2: begin
                    spi_data <= dout;
                    current_state <= `Transition1_e;
                end

                `Transition1_e: begin
                    spi_en <= 1;
                    current_state <= `Transition2_e;
                end
                `Transition2_e: begin
                    if(spi_fin) begin
                        current_state <= `Transition5_e;
                    end
                end

                `Transition3_e: begin
                    delay_en <= 1;
                    current_state <= `Transition4_e;
                end
                `Transition4_e: begin
                    if(delay_fin) begin
                        current_state <= `Transition5_e;
                    end
                end

                `Transition5_e: begin
                    spi_en <= 0;
                    delay_en <= 0;
                    current_state <= after_state;
                end

                default: begin
                    current_state <= `Idle_e;
                end
            endcase
        end
    end
endmodule
module oled_exam(
    clk,
    rst,
    en,
    cs,
    sdo,
    sclk,
    dc,
    fin,
    char_data
    );

    input wire clk, rst, en;
    output wire cs, sdo, sclk, dc, fin;
    input wire [64*8-1:0] char_data;

    reg t_dc;
    reg [4:0] current_state, after_state, after_page_state,
                after_char_state, after_update_state;
    reg spi_en, delay_en;
    reg [7:0] spi_data;
    reg [7:0] current_screen [0:63];
    reg [11:0] delay_ms;

    reg [7:0] t_char;
    reg [10:0] t_addr;
    wire [7:0] dout;
    reg [1:0] t_page;
    reg [3:0] t_index;

    wire spi_fin, delay_fin;

    integer i;

    assign dc = t_dc;
    assign fin = (current_state == `Wait1_e) ? 1 : 0;

    spi_ctrl sctrl(
    .clk(clk),
    .rst(rst),
    .spi_en(spi_en),
    .spi_data(spi_data),
    .cs(cs),
    .sdo(sdo),
    .sclk(sclk),
    .spi_fin(spi_fin)
    );

    delay_gen dgen(
    .clk(clk),
    .rst(rst),
    .delay_ms(delay_ms),
    .delay_en(delay_en),
    .delay_fin(delay_fin)
    );

    char_rom crom(
    .rst(rst),
    .addr(t_addr),
    .dout(dout)
    );

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            current_state <= `Idle_e;
            after_state <= `Idle_e;
            after_page_state <= `Idle_e;
            after_char_state <= `Idle_e;
            after_update_state <= `Idle_e;
            spi_data <= 8'b0;
            delay_ms <= 12'b0;
            t_char <= 8'b0;
            t_addr <= 11'b0;
            t_page <= 2'b0;
            t_index <= 4'b0;
            t_dc <= 0;
            spi_en <= 0;
            delay_en <= 0;
        end else begin
            case(current_state)
                `Idle_e: begin
                    if(en) begin
                        current_state <= `ClearDC;
                        after_page_state <= `STR1;
                        t_page <= 2'b0;
                        t_index <= 4'b0;
                    end
                end
                `STR1: begin
                    current_state <= `UpdateScreen;
                    after_update_state <= `Wait1_e;
                    for(i=63;i>=0;i=i-1) begin
                        current_screen[63-i] <= char_data[(8*i) +: 7];
                    end
                end
                `Wait1_e: begin
                    if(!en) begin
                        current_state <= `Idle_e;
                    end else begin
                        delay_ms <= 12'b000001100100;
                        current_state <= `Transition3_e;
                        after_state <= `STR1;
                    end
                end

                `UpdateScreen: begin
                    t_char <= current_screen[t_page*16+t_index];
                    current_state <= `SendChar1;
                    if(t_index == 4'b1111) begin
                        t_index <= 0;
                        t_page <= t_page + 1;
                        after_char_state <= `ClearDC;
                        if(t_page == 2'b11) begin
                            after_page_state <= after_update_state;
                        end else begin
                            after_page_state <= `UpdateScreen;
                        end
                    end else begin
                        t_index <= t_index + 1;
                        after_char_state <= `UpdateScreen;
                    end
                end

                `ClearDC: begin
                    t_dc <= 0;
                    current_state <= `SetPage;
                end
                `SetPage: begin
                    spi_data <= 8'b00100010;
                    current_state <= `Transition1_e;
                    after_state <= `PageNum;
                end
                `PageNum: begin
                    spi_data <= {6'b000000, t_page};
                    current_state <= `Transition1_e;
                    after_state <= `LeftColumn1;
                end
                `LeftColumn1: begin
                    spi_data <= 8'b00000000;
                    current_state <= `Transition1_e;
                    after_state <= `LeftColumn2;
                end
                `LeftColumn2: begin
                    spi_data <= 8'b00010000;
                    current_state <= `Transition1_e;
                    after_state <= `SetDC;
                end
                `SetDC: begin
                    t_dc <= 1;
                    current_state <= after_page_state;
                end

                `SendChar1: begin
                    t_addr <= {t_char, 3'b000};
                    current_state <= `ReadMem;
                    after_state <= `SendChar2;
                end
                `SendChar2: begin
                    t_addr <= {t_char, 3'b001};
                    current_state <= `ReadMem;
                    after_state <= `SendChar3;
                end
                `SendChar3: begin
                    t_addr <= {t_char, 3'b010};
                    current_state <= `ReadMem;
                    after_state <= `SendChar4;
                end
                `SendChar4: begin
                    t_addr <= {t_char, 3'b011};
                    current_state <= `ReadMem;
                    after_state <= `SendChar5;
                end
                `SendChar5: begin
                    t_addr <= {t_char, 3'b100};
                    current_state <= `ReadMem;
                    after_state <= `SendChar6;
                end
                `SendChar6: begin
                    t_addr <= {t_char, 3'b101};
                    current_state <= `ReadMem;
                    after_state <= `SendChar7;
                end
                `SendChar7: begin
                    t_addr <= {t_char, 3'b110};
                    current_state <= `ReadMem;
                    after_state <= `SendChar8;
                end
                `SendChar8: begin
                    t_addr <= {t_char, 3'b111};
                    current_state <= `ReadMem;
                    after_state <= after_char_state;
                end
                `ReadMem: begin
                    current_state <= `ReadMem2;
                end
                `ReadMem2: begin
                    spi_data <= dout;
                    current_state <= `Transition1_e;
                end

                `Transition1_e: begin
                    spi_en <= 1;
                    current_state <= `Transition2_e;
                end
                `Transition2_e: begin
                    if(spi_fin) begin
                        current_state <= `Transition5_e;
                    end
                end

                `Transition3_e: begin
                    delay_en <= 1;
                    current_state <= `Transition4_e;
                end
                `Transition4_e: begin
                    if(delay_fin) begin
                        current_state <= `Transition5_e;
                    end
                end

                `Transition5_e: begin
                    spi_en <= 0;
                    delay_en <= 0;
                    current_state <= after_state;
                end

                default: begin
                    current_state <= `Idle_e;
                end
            endcase
        end
    end
endmodule