data/full_repos/permissive/218463548/hardware/hdl/oc/ram_true_dual.v
data/verilator_xmls/fa22c39d-d585-47d3-9661-c224a1e67c81.xml
module ram_true_dual #(parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 5, parameter DISTR = 0) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);

   parameter DEPTH = 2**ADDR_WIDTH;

   input clka,clkb,ena,enb,wea,web;
   input [ADDR_WIDTH-1:0] addra,addrb;
   input [DATA_WIDTH-1:0] dia,dib;
   output [DATA_WIDTH-1:0] doa,dob;
   reg [DATA_WIDTH-1:0] doa,dob;


   generate
     if (DISTR) begin : distributed_ram
       (* ram_style = "distributed" *)reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
       integer i;
       initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;

       always @(posedge clka)
       begin
         if (ena)
           begin
             if (wea)
               ram[addra] <= dia;
             doa <= ram[addra];
           end 
       end

       always @(posedge clkb)
       begin
         if (enb)
           begin
             if (web)
               ram[addrb] <= dib;
             dob <= ram[addrb];
           end
       end
     end

     else begin : block_ram
       integer i;
       reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
       initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;

       always @(posedge clka)
       begin
         if (ena)
           begin
             if (wea)
               ram[addra] <= dia;
             doa <= ram[addra];
           end 
       end

       always @(posedge clkb)
       begin
         if (enb)
           begin
             if (web)
               ram[addrb] <= dib;
             dob <= ram[addrb];
           end
       end
     end
   endgenerate


endmodule
module ram_true_dual #(parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 5, parameter DISTR = 0) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);


   parameter DEPTH = 2**ADDR_WIDTH;

   input clka,clkb,ena,enb,wea,web;
   input [ADDR_WIDTH-1:0] addra,addrb;
   input [DATA_WIDTH-1:0] dia,dib;
   output [DATA_WIDTH-1:0] doa,dob;
   reg [DATA_WIDTH-1:0] doa,dob;


   generate
     if (DISTR) begin : distributed_ram
       (* ram_style = "distributed" *)reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
       integer i;
       initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;

       always @(posedge clka)
       begin
         if (ena)
           begin
             if (wea)
               ram[addra] <= dia;
             doa <= ram[addra];
           end 
       end

       always @(posedge clkb)
       begin
         if (enb)
           begin
             if (web)
               ram[addrb] <= dib;
             dob <= ram[addrb];
           end
       end
     end

     else begin : block_ram
       integer i;
       reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
       initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;

       always @(posedge clka)
       begin
         if (ena)
           begin
             if (wea)
               ram[addra] <= dia;
             doa <= ram[addra];
           end 
       end

       always @(posedge clkb)
       begin
         if (enb)
           begin
             if (web)
               ram[addrb] <= dib;
             dob <= ram[addrb];
           end
       end
     end
   endgenerate


endmodule