data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'block_ram_sp\'\nmodule  block_ram_sp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'block_ram_dp\'\nmodule  block_ram_dp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'dist_ram_dp\'\nmodule  dist_ram_dp(\n        ^~~~~~~~~~~\n                                                                                             : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n                                                                                          : ... In instance per_dp2_0_r\n  counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n                                             ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module  counter_64(
in_start,                         
counter_out,                         
clk,                             
rst                              
);                               
  input in_start, clk, rst;                   
  output [5:0] counter_out;            
  
  reg [5:0] counter_r;        
  reg status_couting;        

  assign counter_out = counter_r;        
  
  always@(posedge clk)             
  begin                            
    if(rst) begin                    
      counter_r <= 6'b0;    
      status_couting <= 1'b0;            
    end
    else begin                        
      if (status_couting == 1'b1)                
        counter_r <= counter_r + 1'b1;                   
      if (counter_r[5:0] == 63) begin  
        status_couting <= 1'b0;                 
        counter_r <= 6'b0;         
      end                                    
      if (in_start) begin                     
        status_couting <= 1'b1;                 
      counter_r <= 6'b0;                
      end                                    
    end
  end                              

endmodule
module  counter_64(
in_start,                         
counter_out,                         
clk,                             
rst                              
);
                               
  input in_start, clk, rst;                   
  output [5:0] counter_out;            
  
  reg [5:0] counter_r;        
  reg status_couting;        

  assign counter_out = counter_r;        
  
  always@(posedge clk)             
  begin                            
    if(rst) begin                    
      counter_r <= 6'b0;    
      status_couting <= 1'b0;            
    end
    else begin                        
      if (status_couting == 1'b1)                
        counter_r <= counter_r + 1'b1;                   
      if (counter_r[5:0] == 63) begin  
        status_couting <= 1'b0;                 
        counter_r <= 6'b0;         
      end                                    
      if (in_start) begin                     
        status_couting <= 1'b1;                 
      counter_r <= 6'b0;                
      end                                    
    end
  end                              

endmodule