data/full_repos/permissive/174546493/TestBench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/174546493/TestBench.v:92: Unsupported: Ignoring delay on this delayed statement.\n   #10 reset=0;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174546493/TestBench.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Error: data/full_repos/permissive/174546493/TestBench.v:8: Cannot find file containing module: \'ControlUnit\'\n   ControlUnit CU(.clk(clk),\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174546493,data/full_repos/permissive/174546493/ControlUnit\n             data/full_repos/permissive/174546493,data/full_repos/permissive/174546493/ControlUnit.v\n             data/full_repos/permissive/174546493,data/full_repos/permissive/174546493/ControlUnit.sv\n             ControlUnit\n             ControlUnit.v\n             ControlUnit.sv\n             obj_dir/ControlUnit\n             obj_dir/ControlUnit.v\n             obj_dir/ControlUnit.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testBench;
      reg clk;
	  reg reset;
	  reg [5:0] funct;
	  reg [5:0] opcode;
	  reg overflow;
	  ControlUnit CU(.clk(clk),
	                 .reset(reset),
					 .funct(funct),
					 .opcode(opcode),
					 .overflow(overflow));
	  initial
	     begin
		    clk = 1'b1;
			reset = 1'b1;



			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			



			



			
			funct = 6'b111111;
			opcode = 6'b111111;
			overflow = 0;
			#10 reset=0;
		 end
	  
	  always
        begin
		#10 clk = ~clk;
        end	
endmodule
module testBench;

      reg clk;
	  reg reset;
	  reg [5:0] funct;
	  reg [5:0] opcode;
	  reg overflow;
	  ControlUnit CU(.clk(clk),
	                 .reset(reset),
					 .funct(funct),
					 .opcode(opcode),
					 .overflow(overflow));
	  initial
	     begin
		    clk = 1'b1;
			reset = 1'b1;



			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			


			



			



			
			funct = 6'b111111;
			opcode = 6'b111111;
			overflow = 0;
			#10 reset=0;
		 end
	  
	  always
        begin
		#10 clk = ~clk;
        end	
endmodule