data/full_repos/permissive/167856740/vga/tb/vga_wishbone_tb.v
 line:59: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167856740/vga/tb/vga_wishbone_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #20 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167856740/vga/tb/vga_wishbone_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #40 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/vga/tb/vga_wishbone_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #40 address = 32\'h00002580; data = 32\'h00000001; write_enable = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/vga/tb/vga_wishbone_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #40 address = 32\'h00000000; data = 32\'h00000000; write_enable = 0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/vga/tb/vga_wishbone_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #15412000 address = 32\'h00002582; data = 32\'h00000001; write_enable = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/vga/tb/vga_wishbone_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #40 address = 32\'h00000000; data = 32\'h00000000; write_enable = 0;   \n        ^\n%Error: data/full_repos/permissive/167856740/vga/tb/vga_wishbone_tb.v:56: Unsupported or unknown PLI call: $monitor\n        $monitor(interrupt);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/167856740/vga/tb/vga_wishbone_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #51000000 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vga_wishbone_tb;
    reg clk;
    reg rst;
    
    reg write_enable;
    reg [31:0] address;
    reg [31:0] data;
    
    wire interrupt;
    
    wire hsync;
    wire vsync;
    wire [3:0] red;
    wire [3:0] green;
    wire [3:0] blue;


    vga_wishbone vga(

        .CLK_I(clk),
        .RST_I(rst),
        .STB_I(1'b1),
        .WE_I(write_enable),
        .ADR_I(address),
        .DAT_I(data),
        .INT_O(interrupt),
    

        .mode(1'b0),
        .hsync(hsync),
        .vsync(vsync),
        .red(red),
        .green(green),
        .blue(blue)
    );


	always begin
		#20 clk = ~clk;
	end

	initial begin

		clk = 0; rst = 1;
		address = 32'h00000000; data = 32'h00000000; write_enable = 0; 

        #40 rst = 0;
        #40 address = 32'h00002580; data = 32'h00000001; write_enable = 1;
        #40 address = 32'h00000000; data = 32'h00000000; write_enable = 0;  
        
        #15412000 address = 32'h00002582; data = 32'h00000001; write_enable = 1;
        #40 address = 32'h00000000; data = 32'h00000000; write_enable = 0;   
        $monitor(interrupt);
        

		#51000000 $finish;
	end
	
endmodule
module vga_wishbone_tb;

    reg clk;
    reg rst;
    
    reg write_enable;
    reg [31:0] address;
    reg [31:0] data;
    
    wire interrupt;
    
    wire hsync;
    wire vsync;
    wire [3:0] red;
    wire [3:0] green;
    wire [3:0] blue;


    vga_wishbone vga(

        .CLK_I(clk),
        .RST_I(rst),
        .STB_I(1'b1),
        .WE_I(write_enable),
        .ADR_I(address),
        .DAT_I(data),
        .INT_O(interrupt),
    

        .mode(1'b0),
        .hsync(hsync),
        .vsync(vsync),
        .red(red),
        .green(green),
        .blue(blue)
    );


	always begin
		#20 clk = ~clk;
	end

	initial begin

		clk = 0; rst = 1;
		address = 32'h00000000; data = 32'h00000000; write_enable = 0; 

        #40 rst = 0;
        #40 address = 32'h00002580; data = 32'h00000001; write_enable = 1;
        #40 address = 32'h00000000; data = 32'h00000000; write_enable = 0;  
        
        #15412000 address = 32'h00002582; data = 32'h00000001; write_enable = 1;
        #40 address = 32'h00000000; data = 32'h00000000; write_enable = 0;   
        $monitor(interrupt);
        

		#51000000 $finish;
	end
	
endmodule