data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:38: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clock = ~clock;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:19: Cannot find file containing module: \'RegisterFile\'\n    RegisterFile RegisterAccess (\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/RegisterFile\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/RegisterFile.v\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/RegisterFile.sv\n             RegisterFile\n             RegisterFile.v\n             RegisterFile.sv\n             obj_dir/RegisterFile\n             obj_dir/RegisterFile.v\n             obj_dir/RegisterFile.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_RegisterFile ();
    reg         clock;
    reg [2:0]   result;


    reg         reset;
    reg [4:0]   read_reg1;
    reg [4:0]   read_reg2;
    reg [4:0]   wb_rt_rd;
    reg         wb_reg_write;
    reg [31:0]  wb_write_data;


    wire [31:0] id_reg1_data;
    wire [31:0] id_reg2_data;

    RegisterFile RegisterAccess (
        .clock          (clock),
        .reset          (reset),

        .read_reg1      (read_reg1),
        .read_reg2      (read_reg2),

        .wb_reg_write   (wb_reg_write),
        .wb_rt_rd       (wb_rt_rd),
        .wb_write_data  (wb_write_data),

        .id_reg1_data   (id_reg1_data),
        .id_reg2_data   (id_reg2_data)
    );

    initial begin
        clock = 1;
    end

    always #10 clock = ~clock;

    initial begin
        reset <= 0;
        result <= 3'd0;


        read_reg1       <= 5'd3;
        read_reg2       <= 5'd0;

        wb_reg_write    <= 1'd1;
        wb_rt_rd        <= 5'd3;
        wb_write_data   <= 32'd500;

        #20

        read_reg1       <= 5'd3;
        read_reg2       <= 5'd0;

        wb_reg_write    <= 1'd0;
        wb_rt_rd        <= 5'd4;
        wb_write_data   <= 32'd500;

        #10
        if (id_reg1_data == 32'd500)
            result[0] <= 1;

        #10

        read_reg1       <= 5'd4;
        read_reg2       <= 5'd0;

        wb_reg_write    <= 1'd1;
        wb_rt_rd        <= 5'd0;
        wb_write_data   <= 32'd500;
        
        #10
        if (id_reg1_data == 32'd0)
            result[1] <= 1;

        #10

        read_reg1       <= 5'd3;
        read_reg2       <= 5'd0;

        wb_reg_write    <= 1'd0;
        wb_rt_rd        <= 5'd3;
        wb_write_data   <= 32'd500;

        #10
        if (id_reg1_data == 32'd500 & id_reg2_data == 32'd0)
            result[2] <= 1;

        #20

        if (result == 3'd7)
            $display("All Tests Passed");
        else
            $display("Some tests didn't pass");

    end

endmodule
module TB_RegisterFile ();

    reg         clock;
    reg [2:0]   result;


    reg         reset;
    reg [4:0]   read_reg1;
    reg [4:0]   read_reg2;
    reg [4:0]   wb_rt_rd;
    reg         wb_reg_write;
    reg [31:0]  wb_write_data;


    wire [31:0] id_reg1_data;
    wire [31:0] id_reg2_data;

    RegisterFile RegisterAccess (
        .clock          (clock),
        .reset          (reset),

        .read_reg1      (read_reg1),
        .read_reg2      (read_reg2),

        .wb_reg_write   (wb_reg_write),
        .wb_rt_rd       (wb_rt_rd),
        .wb_write_data  (wb_write_data),

        .id_reg1_data   (id_reg1_data),
        .id_reg2_data   (id_reg2_data)
    );

    initial begin
        clock = 1;
    end

    always #10 clock = ~clock;

    initial begin
        reset <= 0;
        result <= 3'd0;


        read_reg1       <= 5'd3;
        read_reg2       <= 5'd0;

        wb_reg_write    <= 1'd1;
        wb_rt_rd        <= 5'd3;
        wb_write_data   <= 32'd500;

        #20

        read_reg1       <= 5'd3;
        read_reg2       <= 5'd0;

        wb_reg_write    <= 1'd0;
        wb_rt_rd        <= 5'd4;
        wb_write_data   <= 32'd500;

        #10
        if (id_reg1_data == 32'd500)
            result[0] <= 1;

        #10

        read_reg1       <= 5'd4;
        read_reg2       <= 5'd0;

        wb_reg_write    <= 1'd1;
        wb_rt_rd        <= 5'd0;
        wb_write_data   <= 32'd500;
        
        #10
        if (id_reg1_data == 32'd0)
            result[1] <= 1;

        #10

        read_reg1       <= 5'd3;
        read_reg2       <= 5'd0;

        wb_reg_write    <= 1'd0;
        wb_rt_rd        <= 5'd3;
        wb_write_data   <= 32'd500;

        #10
        if (id_reg1_data == 32'd500 & id_reg2_data == 32'd0)
            result[2] <= 1;

        #20

        if (result == 3'd7)
            $display("All Tests Passed");
        else
            $display("Some tests didn't pass");

    end

endmodule