data/full_repos/permissive/136510272/projects/z80.proc/icarus.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/z80.proc/icarus.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 i_clk         = ~i_clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/z80.proc/icarus.v:9: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 o_clk         = ~o_clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/z80.proc/icarus.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #2000 $finish; \n    ^\n%Error: data/full_repos/permissive/136510272/projects/z80.proc/icarus.v:17: Unsupported or unknown PLI call: $dumpfile\ninitial begin $dumpfile("result.vcd"); $dumpvars(0, main); end\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/z80.proc/icarus.v:17: Unsupported or unknown PLI call: $dumpvars\ninitial begin $dumpfile("result.vcd"); $dumpvars(0, main); end\n                                       ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;


reg         i_clk;
reg         o_clk;
always #0.5 i_clk         = ~i_clk;
always #0.5 o_clk         = ~o_clk;

initial begin
    i_clk = 1; 
    o_clk = 0; 
    #2000 $finish; 
end

initial begin $dumpfile("result.vcd"); $dumpvars(0, main); end


reg  [7:0]  i_data;
wire [7:0]  o_data;
wire [15:0] o_addr;
wire        o_wr;
wire [15:0] port;
wire [7:0]  port_in; 
wire [7:0]  port_out;
wire        port_clk;

z80 IZ80(
    1'b0,
    i_clk,
    1'b0,
    i_data,
    o_data,
    o_addr,
    o_wr,    
    port,
    port_in,
    port_out,
    port_clk
);


reg [7:0] memory[65535:0];

initial begin
    $readmemh("rom.hex", memory);
end


always @(posedge o_clk) begin

    i_data <= memory[ o_addr ];    
    if (o_wr) memory[ o_addr ] <= o_data;

end

endmodule
module main;



reg         i_clk;
reg         o_clk;
always #0.5 i_clk         = ~i_clk;
always #0.5 o_clk         = ~o_clk;

initial begin
    i_clk = 1; 
    o_clk = 0; 
    #2000 $finish; 
end

initial begin $dumpfile("result.vcd"); $dumpvars(0, main); end


reg  [7:0]  i_data;
wire [7:0]  o_data;
wire [15:0] o_addr;
wire        o_wr;
wire [15:0] port;
wire [7:0]  port_in; 
wire [7:0]  port_out;
wire        port_clk;

z80 IZ80(
    1'b0,
    i_clk,
    1'b0,
    i_data,
    o_data,
    o_addr,
    o_wr,    
    port,
    port_in,
    port_out,
    port_clk
);


reg [7:0] memory[65535:0];

initial begin
    $readmemh("rom.hex", memory);
end


always @(posedge o_clk) begin

    i_data <= memory[ o_addr ];    
    if (o_wr) memory[ o_addr ] <= o_data;

end

endmodule