data/full_repos/permissive/160794640/example/clocking2.v
 line:4: before: "<="
data/verilator_xmls/dc74fd1a-90b4-4c91-8643-bbdb78875a6f.xml
module clocking_edge(input clk, output logic mem_axi_arready);
   
    task handle_axi_arvalid;
        mem_axi_arready <= 1'h1;
    endtask
   
      always@(negedge clk) 
        begin
           if (mem_axi_arready) handle_axi_arvalid;
	end
   
      always @(posedge clk)
	begin
	   mem_axi_arready <= 1'h0;
	end

endmodule
module clocking_edge(input clk, output logic mem_axi_arready);

   
    task handle_axi_arvalid;
        mem_axi_arready <= 1'h1;
    endtask
   
      always@(negedge clk) 
        begin
           if (mem_axi_arready) handle_axi_arvalid;
	end
   
      always @(posedge clk)
	begin
	   mem_axi_arready <= 1'h0;
	end

endmodule