data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v
None: at end of input
1: b'%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:77: Cannot find include file: clogb2.vh\n`include "clogb2.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2,data/full_repos/permissive/197252258/clogb2.vh\n             data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2,data/full_repos/permissive/197252258/clogb2.vh.v\n             data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2,data/full_repos/permissive/197252258/clogb2.vh.sv\n             clogb2.vh\n             clogb2.vh.v\n             clogb2.vh.sv\n             obj_dir/clogb2.vh\n             obj_dir/clogb2.vh.v\n             obj_dir/clogb2.vh.sv\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:6: Define or directive not defined: \'`TIME_W\'\n    input   [`TIME_W-1:0]           now,\n             ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:7: Define or directive not defined: \'`FLOW_WIN_SIZE\'\n    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:8: Define or directive not defined: \'`FLOW_WIN_SIZE\'\n    input   [`FLOW_WIN_SIZE-1:0]    rtx_wnd_in,\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:9: Define or directive not defined: \'`TX_CNT_WIN_SIZE\'\n    input   [`TX_CNT_WIN_SIZE-1:0]  tx_cnt_wnd_in,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:10: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:11: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\n    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:12: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   next_new_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:13: Define or directive not defined: \'`TIMER_W\'\n    input   [`TIMER_W-1:0]          rtx_timer_amnt_in,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:14: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   total_tx_cnt_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:15: Define or directive not defined: \'`USER_CONTEXT_W\'\n    input   [`USER_CONTEXT_W-1:0]   user_cntxt_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:18: Define or directive not defined: \'`FLAG_W\'\n    output  [`FLAG_W-1:0]           mark_rtx,\n             ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:19: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_start,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:20: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_end,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:21: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\n    output  [`FLOW_WIN_SIZE_W-1:0]  wnd_size_out,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:22: Define or directive not defined: \'`TIMER_W\'\n    output  [`TIMER_W-1:0]          rtx_timer_amnt_out,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:23: Define or directive not defined: \'`USER_CONTEXT_W\'\n    output  [`USER_CONTEXT_W-1:0]   user_cntxt_out\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:29: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire    [`FLOW_WIN_SIZE_W-1:0]  wnd_two;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:32: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire   [`FLOW_WIN_SIZE_W-1:0]  dup_acks_in;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:33: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire   [`FLOW_WIN_SIZE_W-1:0]  ss_thresh_in;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:34: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire   [`FLOW_WIN_SIZE_W-1:0]  wnd_inc_cntr_in;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:35: Define or directive not defined: \'`FLAG_W\'\nwire   [`FLAG_W-1:0]           in_timeout_in;\n        ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:36: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\nwire   [`FLOW_SEQ_NUM_W-1:0]   recover_in;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:37: Define or directive not defined: \'`FLAG_W\'\nwire   [`FLAG_W-1:0]           in_recovery_in;\n        ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:38: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\nwire   [`FLOW_SEQ_NUM_W-1:0]   prev_hgst_ack_in;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:40: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire   [`FLOW_WIN_SIZE_W-1:0]  dup_acks_out;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:41: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire   [`FLOW_WIN_SIZE_W-1:0]  ss_thresh_out;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:42: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire   [`FLOW_WIN_SIZE_W-1:0]  wnd_inc_cntr_out;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:43: Define or directive not defined: \'`FLAG_W\'\nwire   [`FLAG_W-1:0]           in_timeout_out;\n        ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:44: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\nwire   [`FLOW_SEQ_NUM_W-1:0]   recover_out;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:45: Define or directive not defined: \'`FLAG_W\'\nwire   [`FLAG_W-1:0]           in_recovery_out;\n        ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:46: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\nwire   [`FLOW_SEQ_NUM_W-1:0]   prev_hgst_ack_out;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:60: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nassign  wnd_two = {{(`FLOW_WIN_SIZE_W-2){1\'b0}}, {2\'d2}};\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:66: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nassign wnd_size_out = timeout_expired ? {{(`FLOW_WIN_SIZE_W-1){1\'b0}}, 1\'b1} : wnd_size_in;\n                                           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:68: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nassign dup_acks_out = {`FLOW_WIN_SIZE_W{1\'b0}};\n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:69: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nassign ss_thresh_out = wnd_size_in > wnd_two ? {1\'b0, wnd_size_in[`FLOW_WIN_SIZE_W-1:1]} : wnd_two;\n                                                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/nreno_2/user_defined_timeout.v:70: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nassign wnd_inc_cntr_out = {`FLOW_WIN_SIZE_W{1\'b0}};\n                           ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 37 error(s)\n'
module user_defined_timeout (

    input                           timeout_expired,
    input   [`TIME_W-1:0]           now,
    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,
    input   [`FLOW_WIN_SIZE-1:0]    rtx_wnd_in,
    input   [`TX_CNT_WIN_SIZE-1:0]  tx_cnt_wnd_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,
    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   next_new_in,
    input   [`TIMER_W-1:0]          rtx_timer_amnt_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   total_tx_cnt_in,
    input   [`USER_CONTEXT_W-1:0]   user_cntxt_in,
    

    output  [`FLAG_W-1:0]           mark_rtx,
    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_start,
    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_end,
    output  [`FLOW_WIN_SIZE_W-1:0]  wnd_size_out,
    output  [`TIMER_W-1:0]          rtx_timer_amnt_out,
    output  [`USER_CONTEXT_W-1:0]   user_cntxt_out
);
 



wire    [`FLOW_WIN_SIZE_W-1:0]  wnd_two;


wire   [`FLOW_WIN_SIZE_W-1:0]  dup_acks_in;
wire   [`FLOW_WIN_SIZE_W-1:0]  ss_thresh_in;
wire   [`FLOW_WIN_SIZE_W-1:0]  wnd_inc_cntr_in;
wire   [`FLAG_W-1:0]           in_timeout_in;
wire   [`FLOW_SEQ_NUM_W-1:0]   recover_in;
wire   [`FLAG_W-1:0]           in_recovery_in;
wire   [`FLOW_SEQ_NUM_W-1:0]   prev_hgst_ack_in;

wire   [`FLOW_WIN_SIZE_W-1:0]  dup_acks_out;
wire   [`FLOW_WIN_SIZE_W-1:0]  ss_thresh_out;
wire   [`FLOW_WIN_SIZE_W-1:0]  wnd_inc_cntr_out;
wire   [`FLAG_W-1:0]           in_timeout_out;
wire   [`FLOW_SEQ_NUM_W-1:0]   recover_out;
wire   [`FLAG_W-1:0]           in_recovery_out;
wire   [`FLOW_SEQ_NUM_W-1:0]   prev_hgst_ack_out;





assign {prev_hgst_ack_in, in_recovery_in, recover_in,
        in_timeout_in, wnd_inc_cntr_in, ss_thresh_in,
        dup_acks_in} = user_cntxt_in;

assign user_cntxt_out =  timeout_expired ? {prev_hgst_ack_out, in_recovery_out, recover_out,
                          in_timeout_out, wnd_inc_cntr_out, ss_thresh_out,
                          dup_acks_out} : user_cntxt_in;

assign  wnd_two = {{(`FLOW_WIN_SIZE_W-2){1'b0}}, {2'd2}};

assign mark_rtx  = timeout_expired;
assign rtx_start = wnd_start_in;
assign rtx_end = wnd_start_in + 1;

assign wnd_size_out = timeout_expired ? {{(`FLOW_WIN_SIZE_W-1){1'b0}}, 1'b1} : wnd_size_in;
assign rtx_timer_amnt_out = rtx_timer_amnt_in;
assign dup_acks_out = {`FLOW_WIN_SIZE_W{1'b0}};
assign ss_thresh_out = wnd_size_in > wnd_two ? {1'b0, wnd_size_in[`FLOW_WIN_SIZE_W-1:1]} : wnd_two;
assign wnd_inc_cntr_out = {`FLOW_WIN_SIZE_W{1'b0}};
assign in_timeout_out = 1'b1;
assign recover_out = next_new_in - 1;
assign in_recovery_out = in_recovery_in;
assign prev_hgst_ack_out = prev_hgst_ack_in;
  

`include "clogb2.vh"

endmodule
module user_defined_timeout (

    input                           timeout_expired,
    input   [`TIME_W-1:0]           now,
    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,
    input   [`FLOW_WIN_SIZE-1:0]    rtx_wnd_in,
    input   [`TX_CNT_WIN_SIZE-1:0]  tx_cnt_wnd_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,
    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   next_new_in,
    input   [`TIMER_W-1:0]          rtx_timer_amnt_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   total_tx_cnt_in,
    input   [`USER_CONTEXT_W-1:0]   user_cntxt_in,
    

    output  [`FLAG_W-1:0]           mark_rtx,
    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_start,
    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_end,
    output  [`FLOW_WIN_SIZE_W-1:0]  wnd_size_out,
    output  [`TIMER_W-1:0]          rtx_timer_amnt_out,
    output  [`USER_CONTEXT_W-1:0]   user_cntxt_out
);

 



wire    [`FLOW_WIN_SIZE_W-1:0]  wnd_two;


wire   [`FLOW_WIN_SIZE_W-1:0]  dup_acks_in;
wire   [`FLOW_WIN_SIZE_W-1:0]  ss_thresh_in;
wire   [`FLOW_WIN_SIZE_W-1:0]  wnd_inc_cntr_in;
wire   [`FLAG_W-1:0]           in_timeout_in;
wire   [`FLOW_SEQ_NUM_W-1:0]   recover_in;
wire   [`FLAG_W-1:0]           in_recovery_in;
wire   [`FLOW_SEQ_NUM_W-1:0]   prev_hgst_ack_in;

wire   [`FLOW_WIN_SIZE_W-1:0]  dup_acks_out;
wire   [`FLOW_WIN_SIZE_W-1:0]  ss_thresh_out;
wire   [`FLOW_WIN_SIZE_W-1:0]  wnd_inc_cntr_out;
wire   [`FLAG_W-1:0]           in_timeout_out;
wire   [`FLOW_SEQ_NUM_W-1:0]   recover_out;
wire   [`FLAG_W-1:0]           in_recovery_out;
wire   [`FLOW_SEQ_NUM_W-1:0]   prev_hgst_ack_out;





assign {prev_hgst_ack_in, in_recovery_in, recover_in,
        in_timeout_in, wnd_inc_cntr_in, ss_thresh_in,
        dup_acks_in} = user_cntxt_in;

assign user_cntxt_out =  timeout_expired ? {prev_hgst_ack_out, in_recovery_out, recover_out,
                          in_timeout_out, wnd_inc_cntr_out, ss_thresh_out,
                          dup_acks_out} : user_cntxt_in;

assign  wnd_two = {{(`FLOW_WIN_SIZE_W-2){1'b0}}, {2'd2}};

assign mark_rtx  = timeout_expired;
assign rtx_start = wnd_start_in;
assign rtx_end = wnd_start_in + 1;

assign wnd_size_out = timeout_expired ? {{(`FLOW_WIN_SIZE_W-1){1'b0}}, 1'b1} : wnd_size_in;
assign rtx_timer_amnt_out = rtx_timer_amnt_in;
assign dup_acks_out = {`FLOW_WIN_SIZE_W{1'b0}};
assign ss_thresh_out = wnd_size_in > wnd_two ? {1'b0, wnd_size_in[`FLOW_WIN_SIZE_W-1:1]} : wnd_two;
assign wnd_inc_cntr_out = {`FLOW_WIN_SIZE_W{1'b0}};
assign in_timeout_out = 1'b1;
assign recover_out = next_new_in - 1;
assign in_recovery_out = in_recovery_in;
assign prev_hgst_ack_out = prev_hgst_ack_in;
  

`include "clogb2.vh"

endmodule