data/full_repos/permissive/116266634/sign_extender_26_to_32.v
1: b'%Warning-WIDTH: data/full_repos/permissive/116266634/sign_extender_26_to_32.v:12: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h3f\' generates 16 bits.\n                                                                                : ... In instance sign_extender_26_to_32\n  out[31:26] = 16\'b111111;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116266634/sign_extender_26_to_32.v:14: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                : ... In instance sign_extender_26_to_32\n  out[31:26] = 16\'b000000;\n             ^\n%Error: Exiting due to 2 warning(s)\n'
module sign_extender_26_to_32
(
	input [25:0] in,
	output reg [31:0] out
);


always @ (in) begin

	out[25:0] = in[25:0];
	if (in[15] == 1'b1)
		out[31:26] = 16'b111111;
	else
		out[31:26] = 16'b000000;

end 

endmodule
module sign_extender_26_to_32
(
	input [25:0] in,
	output reg [31:0] out
);



always @ (in) begin

	out[25:0] = in[25:0];
	if (in[15] == 1'b1)
		out[31:26] = 16'b111111;
	else
		out[31:26] = 16'b000000;

end 

endmodule