data/full_repos/permissive/119758565/freqDivide.v
data/verilator_xmls/0859eb7d-6fd9-4a32-9253-a1afa0568d33.xml
module freqDivide #(parameter POW = 24, parameter SHIFT = 0) (
    input clk,
    input rst,
    output out_clk
    );
	 reg [POW - 1:0] counter;
	 
	 initial begin
  			counter <= #POW'd0 + SHIFT;
	 end

    always @(posedge clk)
       begin
      if (~rst) begin
  			counter <= #POW'd0 + SHIFT;
      end else begin
	      counter <= counter + 1;
      end
	 end
	
    assign out_clk = counter[POW-1];
    

endmodule
module freqDivide #(parameter POW = 24, parameter SHIFT = 0) (
    input clk,
    input rst,
    output out_clk
    );

	 reg [POW - 1:0] counter;
	 
	 initial begin
  			counter <= #POW'd0 + SHIFT;
	 end

    always @(posedge clk)
       begin
      if (~rst) begin
  			counter <= #POW'd0 + SHIFT;
      end else begin
	      counter <= counter + 1;
      end
	 end
	
    assign out_clk = counter[POW-1];
    

endmodule