data/full_repos/permissive/220330507/rtl/regfile.v
 line:50: before: "+"
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/220330507/rtl/regfile.v:27: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_src1'\n                                                                         : ... In instance regfile\n        out_src1 = registers[in_src1_idx];\n        ^~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/220330507/rtl/regfile.v:33: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_src2'\n                                                                         : ... In instance regfile\n        out_src2 = registers[in_src2_idx];\n        ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module regfile #(parameter WORD_WIDTH=16, IDX_WIDTH=4) 
       (
       input                   clock,
       input                   reset,
       input                   in_write,
       input  [IDX_WIDTH-1:0]  in_src1_idx,
       input  [IDX_WIDTH-1:0]  in_src2_idx,
       input  [IDX_WIDTH-1:0]  in_dst_idx,
       input  [WORD_WIDTH-1:0] in_dst,
       output [WORD_WIDTH-1:0] out_src1,
       output [WORD_WIDTH-1:0] out_src2
       );

    localparam NUM_REGS = (1<<IDX_WIDTH);

    integer i;

    reg [WORD_WIDTH-1:0] registers [NUM_REGS-1:0];



    always @(*)
    begin
        out_src1 = registers[in_src1_idx];
    end


    always @(*)
    begin
        out_src2 = registers[in_src2_idx];
    end


    always @(posedge clock or posedge reset)
    begin
        if (!reset)
        begin
            if (in_write)
            begin
                if (in_dst_idx > 0) begin
                    registers[in_dst_idx] <= in_dst;
                end
            end
        end
        else
        begin
            for (i=0; i<NUM_REGS; i++)
            begin
                registers[i] = 0;
            end
        end
    end


endmodule
module regfile #(parameter WORD_WIDTH=16, IDX_WIDTH=4) 
       (
       input                   clock,
       input                   reset,
       input                   in_write,
       input  [IDX_WIDTH-1:0]  in_src1_idx,
       input  [IDX_WIDTH-1:0]  in_src2_idx,
       input  [IDX_WIDTH-1:0]  in_dst_idx,
       input  [WORD_WIDTH-1:0] in_dst,
       output [WORD_WIDTH-1:0] out_src1,
       output [WORD_WIDTH-1:0] out_src2
       );


    localparam NUM_REGS = (1<<IDX_WIDTH);

    integer i;

    reg [WORD_WIDTH-1:0] registers [NUM_REGS-1:0];



    always @(*)
    begin
        out_src1 = registers[in_src1_idx];
    end


    always @(*)
    begin
        out_src2 = registers[in_src2_idx];
    end


    always @(posedge clock or posedge reset)
    begin
        if (!reset)
        begin
            if (in_write)
            begin
                if (in_dst_idx > 0) begin
                    registers[in_dst_idx] <= in_dst;
                end
            end
        end
        else
        begin
            for (i=0; i<NUM_REGS; i++)
            begin
                registers[i] = 0;
            end
        end
    end


endmodule