data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/pipe_out_check.v
data/verilator_xmls/fef57fb7-d24c-4f79-84cd-c25575f205ab.xml
module pipe_out_check(
	input  wire            clk,
	input  wire            reset,
	input  wire            pipe_out_read,
	output wire [15:0]     pipe_out_data,
	output reg             pipe_out_ready,
	input  wire            throttle_set,
	input  wire [31:0]     throttle_val,
	input  wire            mode
	);


reg  [63:0]  lfsr;
reg  [15:0]  lfsr_p1;
reg  [31:0]  throttle;
reg  [15:0]  level;

assign pipe_out_data = lfsr_p1;







reg [31:0] temp;
always @(posedge clk) begin
	if (reset == 1'b1) begin
		throttle <= throttle_val;
		pipe_out_ready <= 1'b0;
		level <= 16'd0;

		if (mode == 1'b1) begin
			lfsr  <= 64'h0D0C0B0A04030201;
		end else begin
			lfsr  <= 64'h0000000100000001;
		end
	end else begin
		lfsr_p1 <= lfsr[15:0];
		
		if (level >= 16'd1024) begin
			pipe_out_ready <= 1'b1;
		end else begin
			pipe_out_ready <= 1'b0;
		end
	

		case ({pipe_out_read, throttle[0]})
			2'b00: begin
			end
			

			2'b01: begin
				if (level < 16'd65535) begin
					level <= level + 1'b1;
				end
			end
			

			2'b10: begin
				if (level > 16'd0) begin
					level <= level - 1'b1;
				end
			end
			

			2'b11: begin
			end
		endcase
	





		if (throttle_set == 1'b1) begin
			throttle <= throttle_val;
		end else begin
			throttle <= {throttle[0], throttle[31:1]};
		end
		

		if (pipe_out_read == 1'b1) begin
			if (mode == 1'b1) begin
				temp = lfsr[31:0];
				lfsr[31:0]  <= {temp[30:0], temp[31] ^ temp[21] ^ temp[1]};
				temp = lfsr[63:32];
				lfsr[63:32] <= {temp[30:0], temp[31] ^ temp[21] ^ temp[1]};
			end else begin
				lfsr[31:0]  <= lfsr[31:0]  + 1'b1;
				lfsr[63:32] <= lfsr[63:32] + 1'b1;
			end
		end
	end
end

endmodule
module pipe_out_check(
	input  wire            clk,
	input  wire            reset,
	input  wire            pipe_out_read,
	output wire [15:0]     pipe_out_data,
	output reg             pipe_out_ready,
	input  wire            throttle_set,
	input  wire [31:0]     throttle_val,
	input  wire            mode
	);



reg  [63:0]  lfsr;
reg  [15:0]  lfsr_p1;
reg  [31:0]  throttle;
reg  [15:0]  level;

assign pipe_out_data = lfsr_p1;







reg [31:0] temp;
always @(posedge clk) begin
	if (reset == 1'b1) begin
		throttle <= throttle_val;
		pipe_out_ready <= 1'b0;
		level <= 16'd0;

		if (mode == 1'b1) begin
			lfsr  <= 64'h0D0C0B0A04030201;
		end else begin
			lfsr  <= 64'h0000000100000001;
		end
	end else begin
		lfsr_p1 <= lfsr[15:0];
		
		if (level >= 16'd1024) begin
			pipe_out_ready <= 1'b1;
		end else begin
			pipe_out_ready <= 1'b0;
		end
	

		case ({pipe_out_read, throttle[0]})
			2'b00: begin
			end
			

			2'b01: begin
				if (level < 16'd65535) begin
					level <= level + 1'b1;
				end
			end
			

			2'b10: begin
				if (level > 16'd0) begin
					level <= level - 1'b1;
				end
			end
			

			2'b11: begin
			end
		endcase
	





		if (throttle_set == 1'b1) begin
			throttle <= throttle_val;
		end else begin
			throttle <= {throttle[0], throttle[31:1]};
		end
		

		if (pipe_out_read == 1'b1) begin
			if (mode == 1'b1) begin
				temp = lfsr[31:0];
				lfsr[31:0]  <= {temp[30:0], temp[31] ^ temp[21] ^ temp[1]};
				temp = lfsr[63:32];
				lfsr[63:32] <= {temp[30:0], temp[31] ^ temp[21] ^ temp[1]};
			end else begin
				lfsr[31:0]  <= lfsr[31:0]  + 1'b1;
				lfsr[63:32] <= lfsr[63:32] + 1'b1;
			end
		end
	end
end

endmodule