data/full_repos/permissive/161931498/project/DMA_simulation/DMA_simulation.srcs/sources_1/bd/myip_v1_0_bfm_1/ipshared/ed9d/src/fifo.v
data/verilator_xmls/e90298b7-4ae9-462e-8410-424dfecd0e69.xml
module fifo #
(
	parameter integer data_width = 32
)
(
	input rst,
	input clk,  
	input wr_en,
	input rd_en,
	input [data_width-1:0] data_in,      
	output wire [data_width-1:0] data_out,   
	output wire full,
	output wire empty,
	output wire almost_full,	
	output wire almost_empty
);

reg [data_width-1:0] memory[0:1023]; 

reg [10:0] fifo_cnt; 

reg [9:0] rd_p,wr_p;

assign full  = (fifo_cnt == 1024)?1'b1:1'b0; 
assign empty = (fifo_cnt == 0)?1'b1:1'b0;  
assign almost_full  = (fifo_cnt == 1023)?1'b1:1'b0; 
assign almost_empty = (fifo_cnt == 1)?1'b1:1'b0;  
  
always @(posedge clk)
begin  
    if(!rst)  
        fifo_cnt <= 0;  
    else if((!full&&wr_en)&&(!empty&&rd_en)) 
        fifo_cnt <= fifo_cnt;  
    else if(!full && wr_en)         
        fifo_cnt <= fifo_cnt + 1;  
    else if(!empty&& rd_en) 
        fifo_cnt <= fifo_cnt-1;  
    else   
        fifo_cnt <= fifo_cnt;  
end  
  
assign data_out = memory[rd_p];
  
always @(posedge clk) 
begin 
    if(wr_en && !full)  
        memory[wr_p] <= data_in;  
end  
  
always @(posedge clk) 
begin  
    if(!rst)  
        wr_p <= 0;    
    else  
    begin
        if(!full && wr_en)  
            wr_p <= wr_p + 1;  
        else
            wr_p <= wr_p;
    end  
end 

always @(posedge clk) 
begin  
    if(!rst)   
        rd_p <= 0;   
    else 
    begin  
        if(!empty && rd_en)  
            rd_p <= rd_p + 1; 
        else
            rd_p <= rd_p;
    end  
end  

endmodule
module fifo #
(
	parameter integer data_width = 32
)
(
	input rst,
	input clk,  
	input wr_en,
	input rd_en,
	input [data_width-1:0] data_in,      
	output wire [data_width-1:0] data_out,   
	output wire full,
	output wire empty,
	output wire almost_full,	
	output wire almost_empty
);


reg [data_width-1:0] memory[0:1023]; 

reg [10:0] fifo_cnt; 

reg [9:0] rd_p,wr_p;

assign full  = (fifo_cnt == 1024)?1'b1:1'b0; 
assign empty = (fifo_cnt == 0)?1'b1:1'b0;  
assign almost_full  = (fifo_cnt == 1023)?1'b1:1'b0; 
assign almost_empty = (fifo_cnt == 1)?1'b1:1'b0;  
  
always @(posedge clk)
begin  
    if(!rst)  
        fifo_cnt <= 0;  
    else if((!full&&wr_en)&&(!empty&&rd_en)) 
        fifo_cnt <= fifo_cnt;  
    else if(!full && wr_en)         
        fifo_cnt <= fifo_cnt + 1;  
    else if(!empty&& rd_en) 
        fifo_cnt <= fifo_cnt-1;  
    else   
        fifo_cnt <= fifo_cnt;  
end  
  
assign data_out = memory[rd_p];
  
always @(posedge clk) 
begin 
    if(wr_en && !full)  
        memory[wr_p] <= data_in;  
end  
  
always @(posedge clk) 
begin  
    if(!rst)  
        wr_p <= 0;    
    else  
    begin
        if(!full && wr_en)  
            wr_p <= wr_p + 1;  
        else
            wr_p <= wr_p;
    end  
end 

always @(posedge clk) 
begin  
    if(!rst)   
        rd_p <= 0;   
    else 
    begin  
        if(!empty && rd_en)  
            rd_p <= rd_p + 1; 
        else
            rd_p <= rd_p;
    end  
end  

endmodule