data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v
 line:78: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst= 1\'b1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #160 i_rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #5000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:82: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clk=~clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:83: Unsupported: Ignoring delay on this delayed statement.\nalways #5 tick=~tick;\n       ^\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:88: Cannot find file containing module: \'cpu\'\ncpu\n^~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/BIP/Simulacion,data/full_repos/permissive/205673649/cpu\n             data/full_repos/permissive/205673649/BIP/Simulacion,data/full_repos/permissive/205673649/cpu.v\n             data/full_repos/permissive/205673649/BIP/Simulacion,data/full_repos/permissive/205673649/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:108: Cannot find file containing module: \'program_memory\'\n    program_memory\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:122: Cannot find file containing module: \'data_memory\'\n   data_memory\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:138: Cannot find file containing module: \'count_clock\'\n    count_clock\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:152: Cannot find file containing module: \'interfaz\'\ninterfaz\n^~~~~~~~\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:174: Cannot find file containing module: \'tx\'\ntx #(.NB_DATA(DATA), .SB_TICK(TICK))\n^~\n%Error: data/full_repos/permissive/205673649/BIP/Simulacion/tb_general.v:186: Cannot find file containing module: \'rx\'\nrx #(.NB_DATA(DATA), .SB_TICK(TICK))\n^~\n%Error: Exiting due to 7 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_general();

localparam DECODER_SEL_A=5;
localparam DATA = 8;
localparam ADDR =11;
localparam OPCODE =5;
localparam OPERANDO =11;
localparam RAM =16;
localparam TICK= 16;
localparam DEPTH=2048;
localparam RAM_PER= "LOW_LATENCY";
localparam FILE_PM ="/home/andres/Facultad/Arquitectura_de_Computadoras/Andres/Arqui/BIP/Source/instrucciones.txt" ;


reg clk;
reg rst;
reg tick;
wire i_int_tx;
wire [DATA-1:0] i_interfaz_tx_data;
reg i_rx;
wire o_tx_interfaz_done_data;
wire o_tx;
wire o_rx_interfaz_done_data;
wire [DATA-1:0] o_rx_interfaz_data;
wire [OPCODE-1:0] opcode_pm;
wire [OPERANDO-1:0] operando_pm;
wire [RAM-1:0] instruction_pm;
wire [RAM-1:0] o_data_dm;
wire [ADDR-1:0] o_counter;
wire wr_en;
wire [RAM-1:0] in_data_dm;
wire [ADDR-1:0] addr_pm;
wire reset;

initial
begin
    clk = 1'b0;
    tick = 1'b0;
    rst = 1'b0;
    i_rx= 1'b1;
    #10 rst= 1'b1;
    #160 i_rx = 1'b0;
            
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b1;
    #160 i_rx = 1'b1;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    
    #160 i_rx = 1'b1;
    
    
    #5000 $finish;
end


always #2.5 clk=~clk;
always #5 tick=~tick;

assign opcode_pm = instruction_pm [RAM -1 -: OPCODE];
assign operando_pm = instruction_pm [OPERANDO-1 : 0];

cpu
#(  
    .NB_DECODER_SEL_A(DECODER_SEL_A),
    .NB_OPCODE(OPCODE),
    .NB_ADDR(ADDR),
    .NB_OPERANDO(OPERANDO),
    .RAM_WIDTH(RAM)
)
    u_cpu
(
    .i_clk(clk),
    .i_rst(reset),
    .i_opcode_pm(opcode_pm),
    .i_operando_pm(operando_pm),
    .i_data(o_data_dm),
    .o_wr_en(wr_en),
    .o_data(in_data_dm),
    .o_addr_pm(addr_pm)
);
    
    program_memory
#(
    .RAM_WIDTH(RAM),
    .RAM_DEPTH(DEPTH),
    .RAM_PERFORMANCE(RAM_PER),
    .INIT_FILE(FILE_PM)
)
    u_program_memory
(
    .i_clk(clk),
    .i_addr(addr_pm),
    .o_data(instruction_pm)
);

   data_memory
#(
    .RAM_WIDTH(RAM),
    .RAM_DEPTH(DEPTH),
    .RAM_PERFORMANCE(RAM_PER),
    .INIT_FILE("")
)
     u_data_memory
(
     .i_clk(clk),
     .i_addr(operando_pm),
     .i_data(in_data_dm),
     .i_wea(wr_en),
     .o_data(o_data_dm)
);

    count_clock
#(
    .NB_OPCODE(OPCODE),
    .NB_ADDR(ADDR)
)
    u_count2_clock
(
    .i_clk(clk),
    .i_rst(reset),
    .i_opcode(opcode_pm),
    .o_counter(o_counter)
);


interfaz
#(
    .NB_DATA(DATA),
    .NB_OPCODE(OPCODE),
    .NB_ADDR(ADDR),
    .RAM_WIDTH(RAM)
)
u_agu
(
    .i_clk(clk),
    .i_rst(rst),
    .i_data(o_rx_interfaz_data),
    .i_done_data(o_rx_interfaz_done_data),
    .i_opcode(opcode_pm),
    .i_acc(in_data_dm),
    .i_pc(o_counter),
    .i_done_tx(o_tx_interfaz_done_data),
    .o_int_tx(i_int_tx),
    .o_uart(i_interfaz_tx_data),
    .o_ctrl_reset(reset)
);

tx #(.NB_DATA(DATA), .SB_TICK(TICK))
u_agu1
(
    .i_clk(clk),
    .i_rst(rst),
    .i_tx_start(i_int_tx),
    .i_tick(tick),
    .i_data(i_interfaz_tx_data),       
    .o_done_tx(o_tx_interfaz_done_data),       
    .o_tx(o_tx) 
);

rx #(.NB_DATA(DATA), .SB_TICK(TICK))
u_agu2
(
    .i_clk(clk),
    .i_rst(rst),
    .i_bit(i_rx),                  
    .i_tick(tick),
    .o_done_data(o_rx_interfaz_done_data),  
    .o_data(o_rx_interfaz_data)      
);

endmodule
module tb_general();


localparam DECODER_SEL_A=5;
localparam DATA = 8;
localparam ADDR =11;
localparam OPCODE =5;
localparam OPERANDO =11;
localparam RAM =16;
localparam TICK= 16;
localparam DEPTH=2048;
localparam RAM_PER= "LOW_LATENCY";
localparam FILE_PM ="/home/andres/Facultad/Arquitectura_de_Computadoras/Andres/Arqui/BIP/Source/instrucciones.txt" ;


reg clk;
reg rst;
reg tick;
wire i_int_tx;
wire [DATA-1:0] i_interfaz_tx_data;
reg i_rx;
wire o_tx_interfaz_done_data;
wire o_tx;
wire o_rx_interfaz_done_data;
wire [DATA-1:0] o_rx_interfaz_data;
wire [OPCODE-1:0] opcode_pm;
wire [OPERANDO-1:0] operando_pm;
wire [RAM-1:0] instruction_pm;
wire [RAM-1:0] o_data_dm;
wire [ADDR-1:0] o_counter;
wire wr_en;
wire [RAM-1:0] in_data_dm;
wire [ADDR-1:0] addr_pm;
wire reset;

initial
begin
    clk = 1'b0;
    tick = 1'b0;
    rst = 1'b0;
    i_rx= 1'b1;
    #10 rst= 1'b1;
    #160 i_rx = 1'b0;
            
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b1;
    #160 i_rx = 1'b1;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    #160 i_rx = 1'b0;
    
    #160 i_rx = 1'b1;
    
    
    #5000 $finish;
end


always #2.5 clk=~clk;
always #5 tick=~tick;

assign opcode_pm = instruction_pm [RAM -1 -: OPCODE];
assign operando_pm = instruction_pm [OPERANDO-1 : 0];

cpu
#(  
    .NB_DECODER_SEL_A(DECODER_SEL_A),
    .NB_OPCODE(OPCODE),
    .NB_ADDR(ADDR),
    .NB_OPERANDO(OPERANDO),
    .RAM_WIDTH(RAM)
)
    u_cpu
(
    .i_clk(clk),
    .i_rst(reset),
    .i_opcode_pm(opcode_pm),
    .i_operando_pm(operando_pm),
    .i_data(o_data_dm),
    .o_wr_en(wr_en),
    .o_data(in_data_dm),
    .o_addr_pm(addr_pm)
);
    
    program_memory
#(
    .RAM_WIDTH(RAM),
    .RAM_DEPTH(DEPTH),
    .RAM_PERFORMANCE(RAM_PER),
    .INIT_FILE(FILE_PM)
)
    u_program_memory
(
    .i_clk(clk),
    .i_addr(addr_pm),
    .o_data(instruction_pm)
);

   data_memory
#(
    .RAM_WIDTH(RAM),
    .RAM_DEPTH(DEPTH),
    .RAM_PERFORMANCE(RAM_PER),
    .INIT_FILE("")
)
     u_data_memory
(
     .i_clk(clk),
     .i_addr(operando_pm),
     .i_data(in_data_dm),
     .i_wea(wr_en),
     .o_data(o_data_dm)
);

    count_clock
#(
    .NB_OPCODE(OPCODE),
    .NB_ADDR(ADDR)
)
    u_count2_clock
(
    .i_clk(clk),
    .i_rst(reset),
    .i_opcode(opcode_pm),
    .o_counter(o_counter)
);


interfaz
#(
    .NB_DATA(DATA),
    .NB_OPCODE(OPCODE),
    .NB_ADDR(ADDR),
    .RAM_WIDTH(RAM)
)
u_agu
(
    .i_clk(clk),
    .i_rst(rst),
    .i_data(o_rx_interfaz_data),
    .i_done_data(o_rx_interfaz_done_data),
    .i_opcode(opcode_pm),
    .i_acc(in_data_dm),
    .i_pc(o_counter),
    .i_done_tx(o_tx_interfaz_done_data),
    .o_int_tx(i_int_tx),
    .o_uart(i_interfaz_tx_data),
    .o_ctrl_reset(reset)
);

tx #(.NB_DATA(DATA), .SB_TICK(TICK))
u_agu1
(
    .i_clk(clk),
    .i_rst(rst),
    .i_tx_start(i_int_tx),
    .i_tick(tick),
    .i_data(i_interfaz_tx_data),       
    .o_done_tx(o_tx_interfaz_done_data),       
    .o_tx(o_tx) 
);

rx #(.NB_DATA(DATA), .SB_TICK(TICK))
u_agu2
(
    .i_clk(clk),
    .i_rst(rst),
    .i_bit(i_rx),                  
    .i_tick(tick),
    .o_done_data(o_rx_interfaz_done_data),  
    .o_data(o_rx_interfaz_data)      
);

endmodule