data/full_repos/permissive/137416864/benchmarks/techmapping/tigfet/sclib_tigfet10_hpnw4_tt_0p70v_25c.v
None: at end of input
data/verilator_xmls/66fbbc70-176b-43e7-9514-2e141670a68b.xml
module AOI21_HPNW4 (Y, A0, A1, B0);
	output Y;
	input A0, A1, B0;


	buf (Y, 1'b0);


	specify
		(A0 => Y) = 0;
		(A1 => Y) = 0;
		if ((A0 & ~A1))
			(B0 => Y) = 0;
		if ((~A0 & A1))
			(B0 => Y) = 0;
		if ((~A0 & ~A1))
			(B0 => Y) = 0;
		ifnone (B0 => Y) = 0;
	endspecify
endmodule
module AOI21_HPNW4 (Y, A0, A1, B0);

	output Y;
	input A0, A1, B0;


	buf (Y, 1'b0);


	specify
		(A0 => Y) = 0;
		(A1 => Y) = 0;
		if ((A0 & ~A1))
			(B0 => Y) = 0;
		if ((~A0 & A1))
			(B0 => Y) = 0;
		if ((~A0 & ~A1))
			(B0 => Y) = 0;
		ifnone (B0 => Y) = 0;
	endspecify
endmodule