data/full_repos/permissive/136510272/projects/03_zx_spectrum_video/vga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/03_zx_spectrum_video/vga.v:40: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance vga\nreg [9:0] x = 1\'b0;  \n              ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/03_zx_spectrum_video/vga.v:41: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance vga\nreg [9:0] y = 1\'b0;\n              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/03_zx_spectrum_video/vga.v:54: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 9 bits.\n                                                                                           : ... In instance vga\nwire [7:0] X = x[9:1] - 24;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/03_zx_spectrum_video/vga.v:55: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 9 bits.\n                                                                                           : ... In instance vga\nwire [7:0] Y = y[9:1] - 24;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/03_zx_spectrum_video/vga.v:86: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance vga\n        timer <= 1\'b0; \n              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/03_zx_spectrum_video/vga.v:100: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                            : ... In instance vga\n    x <= x == (horiz_whole - 1) ? 1\'b0 : (x + 1\'b1);\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/03_zx_spectrum_video/vga.v:106: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                            : ... In instance vga\n        y <= y == (vert_whole - 1) ? 1\'b0 : (y + 1\'b1);\n                                   ^\n%Error: Exiting due to 7 warning(s)\n'
module vga(


    input   wire        clk,


    output  reg  [4:0]  red,
    output  reg  [5:0]  green,
    output  reg  [4:0]  blue,
    output  wire        hs,
    output  wire        vs,


    output  reg  [12:0] video_addr,
    input   wire [ 7:0] video_data,
    input   wire [ 2:0] border
    
);


parameter horiz_visible = 640;
parameter horiz_back    = 48;
parameter horiz_sync    = 96;
parameter horiz_front   = 16;
parameter horiz_whole   = 800;



parameter vert_visible = 480;
parameter vert_back    = 33;
parameter vert_sync    = 2;
parameter vert_front   = 10;
parameter vert_whole   = 525;


assign hs = x >= (horiz_visible + horiz_front) && x < (horiz_visible + horiz_front + horiz_sync);
assign vs = y >= (vert_visible  + vert_front)  && y < (vert_visible  + vert_front  + vert_sync);


reg [9:0] x = 1'b0;
reg [9:0] y = 1'b0;

reg [7:0] current_char;
reg [7:0] current_attr;
reg [7:0] tmp_current_char;


reg [1:0] clock_divider;


always @(posedge clk) clock_divider <= clock_divider + 1'b1;


wire [7:0] X = x[9:1] - 24;
wire [7:0] Y = y[9:1] - 24;


wire current_bit = current_char[ 7 ^ X[2:0] ];


wire flashed_bit = (current_attr[7] & flash) ^ current_bit;



wire [2:0] src_color = flashed_bit ? current_attr[2:0] : current_attr[5:3];


wire [15:0] color = {


src_color[1] ? (current_attr[6] ? 5'h1F : 5'h0F) : 5'h03,
src_color[2] ? (current_attr[6] ? 6'h3F : 6'h1F) : 6'h03,
src_color[0] ? (current_attr[6] ? 5'h1F : 5'h0F) : 5'h03};


wire [15:0] bgcolor = {border[1] ? 5'h0F : 5'h03,
                       border[2] ? 6'h1F : 6'h03,
                       border[0] ? 5'h0F : 5'h03};

reg        flash;
reg [23:0] timer;

always @(posedge clock_divider[1]) begin

    if (timer == 24'd12500000) begin
        timer <= 1'b0; 
        flash <= flash ^ 1'b1;
    end else begin
        timer <= timer + 1'b1;
    end
    
end



always @(posedge clock_divider[1]) begin



    x <= x == (horiz_whole - 1) ? 1'b0 : (x + 1'b1);
    

    if (x == (horiz_whole - 1)) begin
    

        y <= y == (vert_whole - 1) ? 1'b0 : (y + 1'b1);

    end
    


    
    case (x[3:0])
    



                

        4'b0000: video_addr <= { Y[7:6], Y[2:0],   Y[5:3],   X[7:3] };
        

        4'b0001: tmp_current_char <= video_data;
        


        4'b0010: video_addr <= { 3'b110, Y[7:3], X[7:3] };
        

        4'b1111: begin
        

            current_char <= tmp_current_char;
            




            




            
            current_attr <= video_data;
        
        end

    endcase
    

    if (x < horiz_visible && y < vert_visible) begin
    
        if (x >= 64 && x < (64 + 512) && y >= 48 && y < (48 + 384)) begin
        



            {red, green, blue} <= color;
        

        end else begin
        
            {red, green, blue} <= bgcolor; 
        
        end
    


    end else {red, green, blue} <= 16'h0000;
    
end

endmodule
module vga(


    input   wire        clk,


    output  reg  [4:0]  red,
    output  reg  [5:0]  green,
    output  reg  [4:0]  blue,
    output  wire        hs,
    output  wire        vs,


    output  reg  [12:0] video_addr,
    input   wire [ 7:0] video_data,
    input   wire [ 2:0] border
    
);



parameter horiz_visible = 640;
parameter horiz_back    = 48;
parameter horiz_sync    = 96;
parameter horiz_front   = 16;
parameter horiz_whole   = 800;



parameter vert_visible = 480;
parameter vert_back    = 33;
parameter vert_sync    = 2;
parameter vert_front   = 10;
parameter vert_whole   = 525;


assign hs = x >= (horiz_visible + horiz_front) && x < (horiz_visible + horiz_front + horiz_sync);
assign vs = y >= (vert_visible  + vert_front)  && y < (vert_visible  + vert_front  + vert_sync);


reg [9:0] x = 1'b0;
reg [9:0] y = 1'b0;

reg [7:0] current_char;
reg [7:0] current_attr;
reg [7:0] tmp_current_char;


reg [1:0] clock_divider;


always @(posedge clk) clock_divider <= clock_divider + 1'b1;


wire [7:0] X = x[9:1] - 24;
wire [7:0] Y = y[9:1] - 24;


wire current_bit = current_char[ 7 ^ X[2:0] ];


wire flashed_bit = (current_attr[7] & flash) ^ current_bit;



wire [2:0] src_color = flashed_bit ? current_attr[2:0] : current_attr[5:3];


wire [15:0] color = {


src_color[1] ? (current_attr[6] ? 5'h1F : 5'h0F) : 5'h03,
src_color[2] ? (current_attr[6] ? 6'h3F : 6'h1F) : 6'h03,
src_color[0] ? (current_attr[6] ? 5'h1F : 5'h0F) : 5'h03};


wire [15:0] bgcolor = {border[1] ? 5'h0F : 5'h03,
                       border[2] ? 6'h1F : 6'h03,
                       border[0] ? 5'h0F : 5'h03};

reg        flash;
reg [23:0] timer;

always @(posedge clock_divider[1]) begin

    if (timer == 24'd12500000) begin
        timer <= 1'b0; 
        flash <= flash ^ 1'b1;
    end else begin
        timer <= timer + 1'b1;
    end
    
end



always @(posedge clock_divider[1]) begin



    x <= x == (horiz_whole - 1) ? 1'b0 : (x + 1'b1);
    

    if (x == (horiz_whole - 1)) begin
    

        y <= y == (vert_whole - 1) ? 1'b0 : (y + 1'b1);

    end
    


    
    case (x[3:0])
    



                

        4'b0000: video_addr <= { Y[7:6], Y[2:0],   Y[5:3],   X[7:3] };
        

        4'b0001: tmp_current_char <= video_data;
        


        4'b0010: video_addr <= { 3'b110, Y[7:3], X[7:3] };
        

        4'b1111: begin
        

            current_char <= tmp_current_char;
            




            




            
            current_attr <= video_data;
        
        end

    endcase
    

    if (x < horiz_visible && y < vert_visible) begin
    
        if (x >= 64 && x < (64 + 512) && y >= 48 && y < (48 + 384)) begin
        



            {red, green, blue} <= color;
        

        end else begin
        
            {red, green, blue} <= bgcolor; 
        
        end
    


    end else {red, green, blue} <= 16'h0000;
    
end

endmodule