data/full_repos/permissive/217768747/reduction.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-IMPLICIT: data/full_repos/permissive/217768747/reduction.v:43: Signal definition not found, creating implicitly: \'done_prev\'\n  if(done_prev==1)\n     ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/reduction.v:59: Signal definition not found, creating implicitly: \'carry\'\n    new_sum<={carry,temp_sum};\n              ^~~~~\n%Error: data/full_repos/permissive/217768747/reduction.v:17: Cannot find file containing module: \'divison\'\ndivison div(reg_page_rank,reg_out_deg,clk,reset,quotient,done_prev);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/divison\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/divison.v\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/divison.sv\n             divison\n             divison.v\n             divison.sv\n             obj_dir/divison\n             obj_dir/divison.v\n             obj_dir/divison.sv\n%Error: data/full_repos/permissive/217768747/reduction.v:18: Cannot find file containing module: \'Adder_32\'\nAdder_32 add(sum,quotient,0,temp_sum,carry);\n^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/217768747/reduction.v:59: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 33 bits.\n                                                                   : ... In instance Single_Reduction\n    new_sum<={carry,temp_sum};\n           ^~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module Single_Reduction(sum,page_rank,out_deg,clk,reset,new_sum,done);

input [31:0] sum;
input [31:0] page_rank;
input [31:0] out_deg;
input clk;
input reset;
output reg [31:0] new_sum;
output reg [0:0] done;
reg [31:0] final_quotient;
reg [1:0] state;
reg [31:0] reg_page_rank, reg_out_deg, reg_sum;
parameter s_wait=2'b00, compute_quotient=2'b01,compute_sum=2'b10;
wire [31:0] quotient,temp_sum;
reg [0:0] valid;

divison div(reg_page_rank,reg_out_deg,clk,reset,quotient,done_prev);
Adder_32 add(sum,quotient,0,temp_sum,carry);

always @(posedge clk, negedge reset)
begin
	state <= s_wait;
	if(!reset)
	begin
		new_sum<=0;
		valid<=1;		
	end
	else
	begin
		case(state)	
		s_wait: begin
		reg_page_rank <= page_rank;  
		reg_out_deg <= out_deg;
		reg_sum<=sum;
		state<=compute_quotient;
		valid<=0;

		end
			

		compute_quotient: begin

		if(done_prev==1)
		begin

			final_quotient<=quotient;
			state<=compute_sum;
			valid<=1;


		end
		else begin
			done<=done_prev;
		end
		end
		compute_sum: begin
			if(valid==1)
			begin
				new_sum<={carry,temp_sum};
				done<=1;
			end
		end
		endcase

	end

end

endmodule
module Single_Reduction(sum,page_rank,out_deg,clk,reset,new_sum,done);


input [31:0] sum;
input [31:0] page_rank;
input [31:0] out_deg;
input clk;
input reset;
output reg [31:0] new_sum;
output reg [0:0] done;
reg [31:0] final_quotient;
reg [1:0] state;
reg [31:0] reg_page_rank, reg_out_deg, reg_sum;
parameter s_wait=2'b00, compute_quotient=2'b01,compute_sum=2'b10;
wire [31:0] quotient,temp_sum;
reg [0:0] valid;

divison div(reg_page_rank,reg_out_deg,clk,reset,quotient,done_prev);
Adder_32 add(sum,quotient,0,temp_sum,carry);

always @(posedge clk, negedge reset)
begin
	state <= s_wait;
	if(!reset)
	begin
		new_sum<=0;
		valid<=1;		
	end
	else
	begin
		case(state)	
		s_wait: begin
		reg_page_rank <= page_rank;  
		reg_out_deg <= out_deg;
		reg_sum<=sum;
		state<=compute_quotient;
		valid<=0;

		end
			

		compute_quotient: begin

		if(done_prev==1)
		begin

			final_quotient<=quotient;
			state<=compute_sum;
			valid<=1;


		end
		else begin
			done<=done_prev;
		end
		end
		compute_sum: begin
			if(valid==1)
			begin
				new_sum<={carry,temp_sum};
				done<=1;
			end
		end
		endcase

	end

end

endmodule