data/full_repos/permissive/19340845/test/ALUTest.v
 line:49: before: "$"
1: b'%Error: data/full_repos/permissive/19340845/test/ALUTest.v:11: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("aluTest.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19340845/test/ALUTest.v:12: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, ALUTEST);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19340845/test/ALUTest.v:13: Unsupported or unknown PLI call: $monitor\n      $monitor ("%t: %b, %b -> %b :: %d, %d -> %d (%b), %b", $time, a, b, aout, a, b, aout, fout, fwrite);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d5; b = 16\'d8;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d10; b = 16\'d20;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d123; b = 16\'d234;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d1234; b = 16\'d4321;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d20000; b = 16\'d20000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d40000; b = 16\'d40000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d12345; b = 16\'d54321;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d30000; b = 16\'d35536;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d35; b = 16\'d34;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d34; b = 16\'d35;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d234; b = 16\'d123;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d9999; b = 16\'d9999;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d40000; b = 16\'d30000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'d30000; b = 16\'d40000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d2;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d3;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d4;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d6;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d7;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d8;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d9;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d2;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:53: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d3;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d4;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:55: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d6;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:57: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d7;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:58: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d8;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:59: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d9;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:60: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:61: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:65: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:66: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d2;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:67: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d3;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d4;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:69: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:70: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d6;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:71: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d7;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:72: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d8;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:73: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d9;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:74: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:75: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:79: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:80: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d2;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:81: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d3;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:82: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d4;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:83: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:84: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d6;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:85: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d7;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:86: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d8;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:87: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d9;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:88: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:89: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 16\'b0000000011111111; b = 16\'d0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:90: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:91: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d2;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:92: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d3;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:93: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d4;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:94: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:95: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d6;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:96: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d7;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:97: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d8;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d9;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:99: Unsupported: Ignoring delay on this delayed statement.\n      #10 b = 16\'d10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ALUTest.v:101: Unsupported: Ignoring delay on this delayed statement.\n      #10 $finish;\n      ^\n%Error: Exiting due to 3 error(s), 69 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALUTEST;
   reg [15:0] a, b;
   reg [3:0]  salu;
   wire [15:0] aout;
   wire [3:0]  fout;
   wire fwrite;
   
   ALU alu (a, b, salu, aout, fout, fwrite);

   initial begin
      $dumpfile("aluTest.vcd");
      $dumpvars(0, ALUTEST);
      $monitor ("%t: %b, %b -> %b :: %d, %d -> %d (%b), %b", $time, a, b, aout, a, b, aout, fout, fwrite);

      $display(" --- IADD ---");
      salu = 4'b0000; a = 16'd0; b = 16'd0;
      #10 a = 16'd5; b = 16'd8;
      #10 a = 16'd10; b = 16'd20;
      #10 a = 16'd123; b = 16'd234;
      #10 a = 16'd1234; b = 16'd4321;
      #10 a = 16'd20000; b = 16'd20000;
      #10 a = 16'd40000; b = 16'd40000;
      #10 a = 16'd12345; b = 16'd54321;
      #10 a = 16'd30000; b = 16'd35536;
      
      $display(" --- ISUB ---");
      salu = 4'b0001; a = 16'd0; b = 16'd0;
      #10 a = 16'd35; b = 16'd34;
      #10 a = 16'd34; b = 16'd35;
      #10 a = 16'd234; b = 16'd123;
      #10 a = 16'd9999; b = 16'd9999;
      #10 a = 16'd40000; b = 16'd30000;
      #10 a = 16'd30000; b = 16'd40000;
      
      $display(" --- ISLL ---");
      salu = 4'b1000; a = 16'b1111111100000000; b = 16'd0;
      #10 b = 16'd1;
      #10 b = 16'd2;
      #10 b = 16'd3;
      #10 b = 16'd4;
      #10 b = 16'd5;
      #10 b = 16'd6;
      #10 b = 16'd7;
      #10 b = 16'd8;
      #10 b = 16'd9;
      #10 b = 16'd10;
      #10
      
      $display(" --- ISLR ---");
      salu = 4'b1001; a = 16'b1111111100000000; b = 16'd0;
      #10 b = 16'd1;
      #10 b = 16'd2;
      #10 b = 16'd3;
      #10 b = 16'd4;
      #10 b = 16'd5;
      #10 b = 16'd6;
      #10 b = 16'd7;
      #10 b = 16'd8;
      #10 b = 16'd9;
      #10 b = 16'd10;
      #10
      
      $display(" --- ISRL ---");
      salu = 4'b1010; a = 16'b1111111100000000; b = 16'd0;
      #10 b = 16'd1;
      #10 b = 16'd2;
      #10 b = 16'd3;
      #10 b = 16'd4;
      #10 b = 16'd5;
      #10 b = 16'd6;
      #10 b = 16'd7;
      #10 b = 16'd8;
      #10 b = 16'd9;
      #10 b = 16'd10;
      #10
      
      $display(" --- ISRA ---");
      salu = 4'b1011; a = 16'b1111111100000000; b = 16'd0;
      #10 b = 16'd1;
      #10 b = 16'd2;
      #10 b = 16'd3;
      #10 b = 16'd4;
      #10 b = 16'd5;
      #10 b = 16'd6;
      #10 b = 16'd7;
      #10 b = 16'd8;
      #10 b = 16'd9;
      #10 b = 16'd10;
      #10 a = 16'b0000000011111111; b = 16'd0;
      #10 b = 16'd1;
      #10 b = 16'd2;
      #10 b = 16'd3;
      #10 b = 16'd4;
      #10 b = 16'd5;
      #10 b = 16'd6;
      #10 b = 16'd7;
      #10 b = 16'd8;
      #10 b = 16'd9;
      #10 b = 16'd10;
      
      #10 $finish;
      
   end
endmodule
module ALUTEST;

   reg [15:0] a, b;
   reg [3:0]  salu;
   wire [15:0] aout;
   wire [3:0]  fout;
   wire fwrite;
   
   ALU alu (a, b, salu, aout, fout, fwrite);

   initial begin
      $dumpfile("aluTest.vcd");
      $dumpvars(0, ALUTEST);
      $monitor ("%t: %b, %b -> %b :: %d, %d -> %d (%b), %b", $time, a, b, aout, a, b, aout, fout, fwrite);

      $display(" --- IADD ---");
      salu = 4'b0000; a = 16'd0; b = 16'd0;
      #10 a = 16'd5; b = 16'd8;
      #10 a = 16'd10; b = 16'd20;
      #10 a = 16'd123; b = 16'd234;
      #10 a = 16'd1234; b = 16'd4321;
      #10 a = 16'd20000; b = 16'd20000;
      #10 a = 16'd40000; b = 16'd40000;
      #10 a = 16'd12345; b = 16'd54321;
      #10 a = 16'd30000; b = 16'd35536;
      
      $display(" --- ISUB ---");
      salu = 4'b0001; a = 16'd0; b = 16'd0;
      #10 a = 16'd35; b = 16'd34;
      #10 a = 16'd34; b = 16'd35;
      #10 a = 16'd234; b = 16'd123;
      #10 a = 16'd9999; b = 16'd9999;
      #10 a = 16'd40000; b = 16'd30000;
      #10 a = 16'd30000; b = 16'd40000;
      
      $display(" --- ISLL ---");
      salu = 4'b1000; a = 16'b1111111100000000; b = 16'd0;
      #10 b = 16'd1;
      #10 b = 16'd2;
      #10 b = 16'd3;
      #10 b = 16'd4;
      #10 b = 16'd5;
      #10 b = 16'd6;
      #10 b = 16'd7;
      #10 b = 16'd8;
      #10 b = 16'd9;
      #10 b = 16'd10;
      #10
      
      $display(" --- ISLR ---");
      salu = 4'b1001; a = 16'b1111111100000000; b = 16'd0;
      #10 b = 16'd1;
      #10 b = 16'd2;
      #10 b = 16'd3;
      #10 b = 16'd4;
      #10 b = 16'd5;
      #10 b = 16'd6;
      #10 b = 16'd7;
      #10 b = 16'd8;
      #10 b = 16'd9;
      #10 b = 16'd10;
      #10
      
      $display(" --- ISRL ---");
      salu = 4'b1010; a = 16'b1111111100000000; b = 16'd0;
      #10 b = 16'd1;
      #10 b = 16'd2;
      #10 b = 16'd3;
      #10 b = 16'd4;
      #10 b = 16'd5;
      #10 b = 16'd6;
      #10 b = 16'd7;
      #10 b = 16'd8;
      #10 b = 16'd9;
      #10 b = 16'd10;
      #10
      
      $display(" --- ISRA ---");
      salu = 4'b1011; a = 16'b1111111100000000; b = 16'd0;
      #10 b = 16'd1;
      #10 b = 16'd2;
      #10 b = 16'd3;
      #10 b = 16'd4;
      #10 b = 16'd5;
      #10 b = 16'd6;
      #10 b = 16'd7;
      #10 b = 16'd8;
      #10 b = 16'd9;
      #10 b = 16'd10;
      #10 a = 16'b0000000011111111; b = 16'd0;
      #10 b = 16'd1;
      #10 b = 16'd2;
      #10 b = 16'd3;
      #10 b = 16'd4;
      #10 b = 16'd5;
      #10 b = 16'd6;
      #10 b = 16'd7;
      #10 b = 16'd8;
      #10 b = 16'd9;
      #10 b = 16'd10;
      
      #10 $finish;
      
   end
endmodule