data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit.v
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data/verilator_xmls/ad4fab92-a57c-4e71-9602-c1ffe0c6842d.xml
module RAM_64bit(clock, address, data, chip_select, write_enable, output_enable, size);


	








	




	


	parameter ADDR_WIDTH = 8;
	input clock;
	input [ADDR_WIDTH-1:0] address;
	inout [63:0] data;
	input chip_select, write_enable, output_enable;
	input [1:0] size;
	
	wire [63:0] ram_out;
	wire [63:0] data_out;
	wire [63:0] ram_in;
	

	assign data = (chip_select & output_enable & ~write_enable) ? data_out : 64'bz;
	

	byte_barrel_shifter output_shifter (.out(data_out), .shift_amount(address[2:0]), .in(ram_out));











	wire [2:0]left;
	assign left[0] = address[0];
	assign left[1] = address[1] ^ address[0];
	assign left[2] = address[2] ^ (address[1] | address[0]);
	byte_barrel_shifter input_shifter (.out(ram_in), .shift_amount(left), .in(data));

	wire [ADDR_WIDTH-4:0] a_plus_one;
	assign a_plus_one = address[ADDR_WIDTH-1:3] + 1'b1;
	
	wire [7:0] mask;
	mask_generate mask_inst (mask, size);
	wire [7:0] cs;
	bit_barrel_shifter mask_shifter (.out(cs) , .shift_amount(left), .in(mask));
	wire [7:0] a_select;
	address_select a_select_inst (.out(a_select), .byte_offset(address[2:0]));
	wire [ADDR_WIDTH-4:0] ram0_address, ram1_address, ram2_address, ram3_address, ram4_address, ram5_address, ram6_address, ram7_address;


	assign ram0_address = a_select[0] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram1_address = a_select[1] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram2_address = a_select[2] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram3_address = a_select[3] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram4_address = a_select[4] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram5_address = a_select[5] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram6_address = a_select[6] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram7_address = a_select[7] ? a_plus_one : address[ADDR_WIDTH-1:3];

	RAM_8bit ram0 (ram_out[ 7: 0], clock, ram0_address, ram_in[ 7: 0], cs[0] & chip_select, write_enable);
	RAM_8bit ram1 (ram_out[15: 8], clock, ram1_address, ram_in[15: 8], cs[1] & chip_select, write_enable);
	RAM_8bit ram2 (ram_out[23:16], clock, ram2_address, ram_in[23:16], cs[2] & chip_select, write_enable);
	RAM_8bit ram3 (ram_out[31:24], clock, ram3_address, ram_in[31:24], cs[3] & chip_select, write_enable);
	RAM_8bit ram4 (ram_out[39:32], clock, ram4_address, ram_in[39:32], cs[4] & chip_select, write_enable);
	RAM_8bit ram5 (ram_out[47:40], clock, ram5_address, ram_in[47:40], cs[5] & chip_select, write_enable);
	RAM_8bit ram6 (ram_out[55:48], clock, ram6_address, ram_in[55:48], cs[6] & chip_select, write_enable);
	RAM_8bit ram7 (ram_out[63:56], clock, ram7_address, ram_in[63:56], cs[7] & chip_select, write_enable);

	defparam ram0.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram1.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram2.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram3.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram4.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram5.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram6.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram7.ADDR_WIDTH = ADDR_WIDTH - 3;
endmodule
module RAM_64bit(clock, address, data, chip_select, write_enable, output_enable, size);



	








	




	


	parameter ADDR_WIDTH = 8;
	input clock;
	input [ADDR_WIDTH-1:0] address;
	inout [63:0] data;
	input chip_select, write_enable, output_enable;
	input [1:0] size;
	
	wire [63:0] ram_out;
	wire [63:0] data_out;
	wire [63:0] ram_in;
	

	assign data = (chip_select & output_enable & ~write_enable) ? data_out : 64'bz;
	

	byte_barrel_shifter output_shifter (.out(data_out), .shift_amount(address[2:0]), .in(ram_out));











	wire [2:0]left;
	assign left[0] = address[0];
	assign left[1] = address[1] ^ address[0];
	assign left[2] = address[2] ^ (address[1] | address[0]);
	byte_barrel_shifter input_shifter (.out(ram_in), .shift_amount(left), .in(data));

	wire [ADDR_WIDTH-4:0] a_plus_one;
	assign a_plus_one = address[ADDR_WIDTH-1:3] + 1'b1;
	
	wire [7:0] mask;
	mask_generate mask_inst (mask, size);
	wire [7:0] cs;
	bit_barrel_shifter mask_shifter (.out(cs) , .shift_amount(left), .in(mask));
	wire [7:0] a_select;
	address_select a_select_inst (.out(a_select), .byte_offset(address[2:0]));
	wire [ADDR_WIDTH-4:0] ram0_address, ram1_address, ram2_address, ram3_address, ram4_address, ram5_address, ram6_address, ram7_address;


	assign ram0_address = a_select[0] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram1_address = a_select[1] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram2_address = a_select[2] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram3_address = a_select[3] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram4_address = a_select[4] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram5_address = a_select[5] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram6_address = a_select[6] ? a_plus_one : address[ADDR_WIDTH-1:3];
	assign ram7_address = a_select[7] ? a_plus_one : address[ADDR_WIDTH-1:3];

	RAM_8bit ram0 (ram_out[ 7: 0], clock, ram0_address, ram_in[ 7: 0], cs[0] & chip_select, write_enable);
	RAM_8bit ram1 (ram_out[15: 8], clock, ram1_address, ram_in[15: 8], cs[1] & chip_select, write_enable);
	RAM_8bit ram2 (ram_out[23:16], clock, ram2_address, ram_in[23:16], cs[2] & chip_select, write_enable);
	RAM_8bit ram3 (ram_out[31:24], clock, ram3_address, ram_in[31:24], cs[3] & chip_select, write_enable);
	RAM_8bit ram4 (ram_out[39:32], clock, ram4_address, ram_in[39:32], cs[4] & chip_select, write_enable);
	RAM_8bit ram5 (ram_out[47:40], clock, ram5_address, ram_in[47:40], cs[5] & chip_select, write_enable);
	RAM_8bit ram6 (ram_out[55:48], clock, ram6_address, ram_in[55:48], cs[6] & chip_select, write_enable);
	RAM_8bit ram7 (ram_out[63:56], clock, ram7_address, ram_in[63:56], cs[7] & chip_select, write_enable);

	defparam ram0.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram1.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram2.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram3.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram4.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram5.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram6.ADDR_WIDTH = ADDR_WIDTH - 3;
	defparam ram7.ADDR_WIDTH = ADDR_WIDTH - 3;
endmodule