data/full_repos/permissive/20270692/labs/lab3/half_adder_tb.v
 line:66: before: ","
1: b'%Error: data/full_repos/permissive/20270692/labs/lab3/half_adder_tb.v:7: Cannot find include file: half_adder.v\n`include "half_adder.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab3,data/full_repos/permissive/20270692/half_adder.v\n             data/full_repos/permissive/20270692/labs/lab3,data/full_repos/permissive/20270692/half_adder.v.v\n             data/full_repos/permissive/20270692/labs/lab3,data/full_repos/permissive/20270692/half_adder.v.sv\n             half_adder.v\n             half_adder.v.v\n             half_adder.v.sv\n             obj_dir/half_adder.v\n             obj_dir/half_adder.v.v\n             obj_dir/half_adder.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab3/half_adder_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    forever #5 t_clock=~t_clock;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20270692/labs/lab3/half_adder_tb.v:51: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n    fp=$fopen("half_adder_tb.out");\n       ^~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab3/half_adder_tb.v:52: Unsupported or unknown PLI call: $fmonitor\n    $fmonitor(fp, "time=%0d", $time,, "A=%b B=%b S=%b C=%b", A, B, S, C);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab3/half_adder_tb.v:52: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    $fmonitor(fp, "time=%0d", $time,, "A=%b B=%b S=%b C=%b", A, B, S, C);\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab3/half_adder_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #1000\n    ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module half_adder_tb (A, B);

  output A, B;
  reg A, B;

  wire S, C;

  reg t_A [5000:0];
  reg t_B [5000:0];
  reg t_clock;
  reg [31:0] vectornum;

        integer fp;

  half_adder I1 (A, B, S, C);



  initial
  begin
    t_clock=0;
    forever #5 t_clock=~t_clock;
  end

  initial
  begin
    $readmemb("./bit_str_a_0.txt",t_A);
    $readmemb("./bit_str_a_1.txt",t_B);
    vectornum=0;
  end

  always @(negedge t_clock)
  begin
    A<=t_A[vectornum];
    B<=t_B[vectornum];
    vectornum<=vectornum+1;
  end

  initial
  begin
    fp=$fopen("half_adder_tb.out");
    $fmonitor(fp, "time=%0d", $time,, "A=%b B=%b S=%b C=%b", A, B, S, C);
    #1000
    $fclose(fp);
    $finish;
  end

endmodule
module half_adder_tb (A, B);


  output A, B;
  reg A, B;

  wire S, C;

  reg t_A [5000:0];
  reg t_B [5000:0];
  reg t_clock;
  reg [31:0] vectornum;

        integer fp;

  half_adder I1 (A, B, S, C);



  initial
  begin
    t_clock=0;
    forever #5 t_clock=~t_clock;
  end

  initial
  begin
    $readmemb("./bit_str_a_0.txt",t_A);
    $readmemb("./bit_str_a_1.txt",t_B);
    vectornum=0;
  end

  always @(negedge t_clock)
  begin
    A<=t_A[vectornum];
    B<=t_B[vectornum];
    vectornum<=vectornum+1;
  end

  initial
  begin
    fp=$fopen("half_adder_tb.out");
    $fmonitor(fp, "time=%0d", $time,, "A=%b B=%b S=%b C=%b", A, B, S, C);
    #1000
    $fclose(fp);
    $finish;
  end

endmodule