data/full_repos/permissive/175070965/lib/basic/dff.v
None: at end of input
1: b'%Error: data/full_repos/permissive/175070965/lib/basic/dff.v:25: Cannot find include file: timescale.inc\n`include "timescale.inc" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175070965/lib/basic,data/full_repos/permissive/175070965/timescale.inc\n             data/full_repos/permissive/175070965/lib/basic,data/full_repos/permissive/175070965/timescale.inc.v\n             data/full_repos/permissive/175070965/lib/basic,data/full_repos/permissive/175070965/timescale.inc.sv\n             timescale.inc\n             timescale.inc.v\n             timescale.inc.sv\n             obj_dir/timescale.inc\n             obj_dir/timescale.inc.v\n             obj_dir/timescale.inc.sv\n%Error: data/full_repos/permissive/175070965/lib/basic/dff.v:26: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module dffpr0(clk, rst, Q, D);
parameter   [31:0]  N = 32'd32;
input wire              clk;
input wire              rst;
input wire    [N-1:0]   D;
output reg    [N-1:0]   Q;

always @(posedge clk or posedge rst)
begin
    if (rst) begin
        Q <= {N{1'b0}};
    end else begin
        Q <= D;
    end
end
endmodule
module dffpr0(clk, rst, Q, D);

parameter   [31:0]  N = 32'd32;
input wire              clk;
input wire              rst;
input wire    [N-1:0]   D;
output reg    [N-1:0]   Q;

always @(posedge clk or posedge rst)
begin
    if (rst) begin
        Q <= {N{1'b0}};
    end else begin
        Q <= D;
    end
end
endmodule