data/full_repos/permissive/217697217/problems/01_sign_ext/sign_ext2.v
data/verilator_xmls/ad81d1e8-cb12-461a-a188-86cc1c0a297f.xml
module sign_ext2(
    input [11:0]imm,

    output [31:0]ext_imm
);



wire msb = imm[11] ? 1 : 0;
wire [19:0]ext = {20{msb}};
assign ext_imm = {ext, imm};

endmodule
module sign_ext2(
    input [11:0]imm,

    output [31:0]ext_imm
);




wire msb = imm[11] ? 1 : 0;
wire [19:0]ext = {20{msb}};
assign ext_imm = {ext, imm};

endmodule