data/full_repos/permissive/144334019/vga_data_controller.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/144334019/vga_data_controller.v:83: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'x_div\' generates 6 bits.\n                                                                             : ... In instance vga_data_controller\n assign calc_addr = x_div - 6\'d15 + (y_div << 3) + (y_div << 1);\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/144334019/vga_data_controller.v:83: Operator SUB expects 8 bits on the RHS, but RHS\'s CONST \'6\'hf\' generates 6 bits.\n                                                                             : ... In instance vga_data_controller\n assign calc_addr = x_div - 6\'d15 + (y_div << 3) + (y_div << 1);\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/144334019/vga_data_controller.v:83: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'y_div\' generates 6 bits.\n                                                                             : ... In instance vga_data_controller\n assign calc_addr = x_div - 6\'d15 + (y_div << 3) + (y_div << 1);\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/144334019/vga_data_controller.v:83: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'y_div\' generates 6 bits.\n                                                                             : ... In instance vga_data_controller\n assign calc_addr = x_div - 6\'d15 + (y_div << 3) + (y_div << 1);\n                                                          ^~\n%Error: data/full_repos/permissive/144334019/vga_data_controller.v:89: Cannot find file containing module: \'my_RAM_2\'\n my_RAM_2 ourRam (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/144334019,data/full_repos/permissive/144334019/my_RAM_2\n             data/full_repos/permissive/144334019,data/full_repos/permissive/144334019/my_RAM_2.v\n             data/full_repos/permissive/144334019,data/full_repos/permissive/144334019/my_RAM_2.sv\n             my_RAM_2\n             my_RAM_2.v\n             my_RAM_2.sv\n             obj_dir/my_RAM_2\n             obj_dir/my_RAM_2.v\n             obj_dir/my_RAM_2.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module vga_data_controller
	(
	input 	wire			ptick,
	input 	wire			clk,
	input		wire			rst,
	input		wire	[7:0]	pico_addr,
	input		wire	[7:0]	pico_data_in,
	input		wire			pico_write_strobe,
	input		wire			pico_read_strobe,
	input 	wire	[5:0]	x_div,
	input		wire	[5:0]	y_div,
	
	output	wire	[7:0]	pico_data_out,
	output	wire	[7:0]	vga_out	
	);
	
	reg 		  ram_en;
	wire [7:0] ram_dinb;
	wire [7:0] ram_addrb;
	reg  [7:0] timer;
	(*KEEP="TRUE"*)reg  [7:0] adress;
	wire [7:0] ram_out;
	reg [4:0] ptick_div;
	wire [7:0] calc_addr;
	reg	[7:0] color_out;
	always @(posedge ptick, posedge rst)
	begin
		if(rst) ptick_div <= 0;
		else ptick_div <= ptick_div + 1;
	end
	
	always @ (posedge ptick_div[3], posedge rst)
	begin
		if(rst)
		begin
			ram_en	<= 0;
			adress 	<= 0;
		end
		else
		begin
			
			if ((x_div >= 6'd15) && (x_div < 6'd25) && (y_div < 6'd22) ) 
			begin				
				adress <= calc_addr;
				ram_en	<= 1;
			end
			else
			begin
				adress 	<=  0;
				ram_en 	<=  0;
			end
		end
	end
	
	always@(*)
	begin

		case(ram_out[2:0])
		 3'h7: color_out <= 8'hc4;
		 3'h1: color_out <= 8'h03;
		 3'h2: color_out <= 8'he3;
		 3'h3: color_out <= 8'he0;
	
		 3'h4: color_out <= 8'h1c;
		 3'h5: color_out <= 8'h1B;
		 3'h6: color_out <= 8'hFC;
		 default: color_out <= 8'h00;
	 endcase


	end
	
	always@(posedge clk)
	begin
		if(rst) timer <= timer + 1;
		else 	timer <= 0;
	end 
	
	assign vga_out = ram_en ? color_out : 8'b01001001;
	
	assign calc_addr = x_div - 6'd15 + (y_div << 3) + (y_div << 1);
	
	assign ram_addrb = rst ? timer : pico_addr;
	
	assign ram_dinb = rst ? 8'h00 : pico_data_in;
	
	my_RAM_2 ourRam (
			.clka(ptick),
			.wea(1'b0),
			.addra(adress),
			.dina(8'hZZ),
		   .douta(ram_out),
			.clkb(clk),
			.web(pico_write_strobe|rst),
			.addrb(ram_addrb),
			.dinb(ram_dinb),
		  .doutb(pico_data_out)
		);	
endmodule
module vga_data_controller
	(
	input 	wire			ptick,
	input 	wire			clk,
	input		wire			rst,
	input		wire	[7:0]	pico_addr,
	input		wire	[7:0]	pico_data_in,
	input		wire			pico_write_strobe,
	input		wire			pico_read_strobe,
	input 	wire	[5:0]	x_div,
	input		wire	[5:0]	y_div,
	
	output	wire	[7:0]	pico_data_out,
	output	wire	[7:0]	vga_out	
	);

	
	reg 		  ram_en;
	wire [7:0] ram_dinb;
	wire [7:0] ram_addrb;
	reg  [7:0] timer;
	(*KEEP="TRUE"*)reg  [7:0] adress;
	wire [7:0] ram_out;
	reg [4:0] ptick_div;
	wire [7:0] calc_addr;
	reg	[7:0] color_out;
	always @(posedge ptick, posedge rst)
	begin
		if(rst) ptick_div <= 0;
		else ptick_div <= ptick_div + 1;
	end
	
	always @ (posedge ptick_div[3], posedge rst)
	begin
		if(rst)
		begin
			ram_en	<= 0;
			adress 	<= 0;
		end
		else
		begin
			
			if ((x_div >= 6'd15) && (x_div < 6'd25) && (y_div < 6'd22) ) 
			begin				
				adress <= calc_addr;
				ram_en	<= 1;
			end
			else
			begin
				adress 	<=  0;
				ram_en 	<=  0;
			end
		end
	end
	
	always@(*)
	begin

		case(ram_out[2:0])
		 3'h7: color_out <= 8'hc4;
		 3'h1: color_out <= 8'h03;
		 3'h2: color_out <= 8'he3;
		 3'h3: color_out <= 8'he0;
	
		 3'h4: color_out <= 8'h1c;
		 3'h5: color_out <= 8'h1B;
		 3'h6: color_out <= 8'hFC;
		 default: color_out <= 8'h00;
	 endcase


	end
	
	always@(posedge clk)
	begin
		if(rst) timer <= timer + 1;
		else 	timer <= 0;
	end 
	
	assign vga_out = ram_en ? color_out : 8'b01001001;
	
	assign calc_addr = x_div - 6'd15 + (y_div << 3) + (y_div << 1);
	
	assign ram_addrb = rst ? timer : pico_addr;
	
	assign ram_dinb = rst ? 8'h00 : pico_data_in;
	
	my_RAM_2 ourRam (
			.clka(ptick),
			.wea(1'b0),
			.addra(adress),
			.dina(8'hZZ),
		   .douta(ram_out),
			.clkb(clk),
			.web(pico_write_strobe|rst),
			.addrb(ram_addrb),
			.dinb(ram_dinb),
		  .doutb(pico_data_out)
		);	
endmodule