data/full_repos/permissive/202080108/test/cpu/loop_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/202080108/test/cpu/loop_tb.v:1: Cannot find include file: assert.vh\n`include "assert.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202080108/test/cpu,data/full_repos/permissive/202080108/assert.vh\n             data/full_repos/permissive/202080108/test/cpu,data/full_repos/permissive/202080108/assert.vh.v\n             data/full_repos/permissive/202080108/test/cpu,data/full_repos/permissive/202080108/assert.vh.sv\n             assert.vh\n             assert.vh.v\n             assert.vh.sv\n             obj_dir/assert.vh\n             obj_dir/assert.vh.v\n             obj_dir/assert.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/202080108/test/cpu/loop_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/202080108/test/cpu/loop_tb.v:76: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("loop_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202080108/test/cpu/loop_tb.v:77: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, cpu_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202080108/test/cpu/loop_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Error: data/full_repos/permissive/202080108/test/cpu/loop_tb.v:83: Define or directive not defined: \'`assert\'\n    `assert(result, 3);\n    ^~~~~~~\n%Error: data/full_repos/permissive/202080108/test/cpu/loop_tb.v:83: syntax error, unexpected \',\'\n    `assert(result, 3);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/202080108/test/cpu/loop_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #247\n    ^\n%Error: data/full_repos/permissive/202080108/test/cpu/loop_tb.v:84: Define or directive not defined: \'`assert\'\n    `assert(result_empty, 0);\n    ^~~~~~~\n%Error: data/full_repos/permissive/202080108/test/cpu/loop_tb.v:84: syntax error, unexpected \',\'\n    `assert(result_empty, 0);\n                        ^\n%Error: Exiting due to 7 error(s), 3 warning(s)\n'
module cpu_tb();

  reg clk = 0;






  localparam MEM_ADDR    = 6;
  localparam MEM_EXTRA   = 4;
  localparam STACK_DEPTH = 7;

  reg  [      MEM_ADDR  :0] mem_addr;
  reg  [     MEM_EXTRA-1:0] mem_extra;
  reg  [      MEM_ADDR  :0] rom_lower_bound = 0;
  reg  [      MEM_ADDR  :0] rom_upper_bound = ~0;
  wire [2**MEM_EXTRA*8-1:0] mem_data;
  wire                      mem_error;

  genrom #(
    .ROMFILE("loop.hex"),
    .AW(MEM_ADDR),
    .DW(8),
    .EXTRA(MEM_EXTRA)
  )
  ROM (
    .clk(clk),
    .addr(mem_addr),
    .extra(mem_extra),
    .lower_bound(rom_lower_bound),
    .upper_bound(rom_upper_bound),
    .data(mem_data),
    .error(mem_error)
  );






  reg                  reset = 1;
  reg  [   MEM_ADDR:0] pc    = 17;
  reg  [STACK_DEPTH:0] index = 1;
  wire [         63:0] result;
  wire [          1:0] result_type;
  wire                 result_empty;
  wire [          3:0] trap;

  cpu #(
    .MEM_DEPTH(MEM_ADDR),
    .STACK_DEPTH(STACK_DEPTH)
  )
  dut
  (
    .clk(clk),
    .reset(reset),
    .pc(pc),
    .index(index),
    .result(result),
    .result_type(result_type),
    .result_empty(result_empty),
    .trap(trap),
    .mem_addr(mem_addr),
    .mem_extra(mem_extra),
    .mem_data(mem_data),
    .mem_error(mem_error)
  );

  always #1 clk = ~clk;

  initial begin
    $dumpfile("loop_tb.vcd");
    $dumpvars(0, cpu_tb);

    #1
    reset <= 0;

    #247
    `assert(result, 3);
    `assert(result_empty, 0);

    $finish;
  end

endmodule
module cpu_tb();


  reg clk = 0;






  localparam MEM_ADDR    = 6;
  localparam MEM_EXTRA   = 4;
  localparam STACK_DEPTH = 7;

  reg  [      MEM_ADDR  :0] mem_addr;
  reg  [     MEM_EXTRA-1:0] mem_extra;
  reg  [      MEM_ADDR  :0] rom_lower_bound = 0;
  reg  [      MEM_ADDR  :0] rom_upper_bound = ~0;
  wire [2**MEM_EXTRA*8-1:0] mem_data;
  wire                      mem_error;

  genrom #(
    .ROMFILE("loop.hex"),
    .AW(MEM_ADDR),
    .DW(8),
    .EXTRA(MEM_EXTRA)
  )
  ROM (
    .clk(clk),
    .addr(mem_addr),
    .extra(mem_extra),
    .lower_bound(rom_lower_bound),
    .upper_bound(rom_upper_bound),
    .data(mem_data),
    .error(mem_error)
  );






  reg                  reset = 1;
  reg  [   MEM_ADDR:0] pc    = 17;
  reg  [STACK_DEPTH:0] index = 1;
  wire [         63:0] result;
  wire [          1:0] result_type;
  wire                 result_empty;
  wire [          3:0] trap;

  cpu #(
    .MEM_DEPTH(MEM_ADDR),
    .STACK_DEPTH(STACK_DEPTH)
  )
  dut
  (
    .clk(clk),
    .reset(reset),
    .pc(pc),
    .index(index),
    .result(result),
    .result_type(result_type),
    .result_empty(result_empty),
    .trap(trap),
    .mem_addr(mem_addr),
    .mem_extra(mem_extra),
    .mem_data(mem_data),
    .mem_error(mem_error)
  );

  always #1 clk = ~clk;

  initial begin
    $dumpfile("loop_tb.vcd");
    $dumpvars(0, cpu_tb);

    #1
    reset <= 0;

    #247
    `assert(result, 3);
    `assert(result_empty, 0);

    $finish;
  end

endmodule