data/full_repos/permissive/156539908/gray/gray.v
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data/verilator_xmls/46384b8e-54c1-4876-8e03-e6a92b77755b.xml
module top (input CLK, output LEDG_N, output LEDR_N);

    reg  [3:0] binary;
    reg        ok;
    wire [3:0] gray;
    wire [3:0] bin2;

    to_gray uut1 (.clk(CLK), .enable(1), .binary(binary), .gray(gray));
    to_binary uut2 (.clk(CLK), .enable(1), .gray(gray), .binary(bin2));

    initial
        binary = 0;

    always @(posedge CLK) begin
        binary <= binary + 1;
        ok <= bin2 + 4'd2 == binary;
    end

    assign LEDG_N = ~ok;
    assign LEDR_N = ok;

endmodule
module top (input CLK, output LEDG_N, output LEDR_N);


    reg  [3:0] binary;
    reg        ok;
    wire [3:0] gray;
    wire [3:0] bin2;

    to_gray uut1 (.clk(CLK), .enable(1), .binary(binary), .gray(gray));
    to_binary uut2 (.clk(CLK), .enable(1), .gray(gray), .binary(bin2));

    initial
        binary = 0;

    always @(posedge CLK) begin
        binary <= binary + 1;
        ok <= bin2 + 4'd2 == binary;
    end

    assign LEDG_N = ~ok;
    assign LEDR_N = ok;

endmodule