data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/m2014_q4a.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/m2014_q4a.v:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out1'\n                                                                                                                           : ... In instance top_module\n        out1 = ~(out2 | (~d)&ena);\n        ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/m2014_q4a.v:8: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out2'\n                                                                                                                           : ... In instance top_module\n        out2 = ~(out1 | d&ena);\n        ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/m2014_q4a.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                                           : ... In instance top_module\n        q = out1;\n        ^\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input d, 
    input ena,
    output q);
    wire in,out1,out2;
    always @(*) begin
        out1 = ~(out2 | (~d)&ena);
        out2 = ~(out1 | d&ena);
        q = out1;
    end
endmodule
module top_module (
    input d, 
    input ena,
    output q);

    wire in,out1,out2;
    always @(*) begin
        out1 = ~(out2 | (~d)&ena);
        out2 = ~(out1 | d&ena);
        q = out1;
    end
endmodule