data/full_repos/permissive/121803953/Lab1/lab1.v
data/verilator_xmls/012f2d9a-376f-4eca-8f5d-548a280b9e02.xml
module part1(a, b, c, R);
	input a, b, c;
	output R;
	wire x;
	or or1(x, a, b);
	or or2(R, x, c);
endmodule
module part1(a, b, c, R);

	input a, b, c;
	output R;
	wire x;
	or or1(x, a, b);
	or or2(R, x, c);
endmodule