data/full_repos/permissive/201753306/src_v/dbg_bridge.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/201753306/src_v/dbg_bridge.v:154: Cannot find file containing module: 'dbg_bridge_uart'\ndbg_bridge_uart\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201753306/src_v,data/full_repos/permissive/201753306/dbg_bridge_uart\n             data/full_repos/permissive/201753306/src_v,data/full_repos/permissive/201753306/dbg_bridge_uart.v\n             data/full_repos/permissive/201753306/src_v,data/full_repos/permissive/201753306/dbg_bridge_uart.sv\n             dbg_bridge_uart\n             dbg_bridge_uart.v\n             dbg_bridge_uart.sv\n             obj_dir/dbg_bridge_uart\n             obj_dir/dbg_bridge_uart.v\n             obj_dir/dbg_bridge_uart.sv\n%Error: data/full_repos/permissive/201753306/src_v/dbg_bridge.v:187: Cannot find file containing module: 'dbg_bridge_fifo'\ndbg_bridge_fifo\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201753306/src_v/dbg_bridge.v:212: Cannot find file containing module: 'dbg_bridge_fifo'\ndbg_bridge_fifo\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module dbg_bridge



#(
     parameter CLK_FREQ         = 14745600
    ,parameter UART_SPEED       = 115200
    ,parameter AXI_ID           = 4'd0
    ,parameter GPIO_ADDRESS     = 32'hf0000000
    ,parameter STS_ADDRESS      = 32'hf0000004
)



(

     input           clk_i
    ,input           rst_i
    ,input           uart_rxd_i
    ,input           mem_awready_i
    ,input           mem_wready_i
    ,input           mem_bvalid_i
    ,input  [  1:0]  mem_bresp_i
    ,input  [  3:0]  mem_bid_i
    ,input           mem_arready_i
    ,input           mem_rvalid_i
    ,input  [ 31:0]  mem_rdata_i
    ,input  [  1:0]  mem_rresp_i
    ,input  [  3:0]  mem_rid_i
    ,input           mem_rlast_i
    ,input  [ 31:0]  gpio_inputs_i


    ,output          uart_txd_o
    ,output          mem_awvalid_o
    ,output [ 31:0]  mem_awaddr_o
    ,output [  3:0]  mem_awid_o
    ,output [  7:0]  mem_awlen_o
    ,output [  1:0]  mem_awburst_o
    ,output          mem_wvalid_o
    ,output [ 31:0]  mem_wdata_o
    ,output [  3:0]  mem_wstrb_o
    ,output          mem_wlast_o
    ,output          mem_bready_o
    ,output          mem_arvalid_o
    ,output [ 31:0]  mem_araddr_o
    ,output [  3:0]  mem_arid_o
    ,output [  7:0]  mem_arlen_o
    ,output [  1:0]  mem_arburst_o
    ,output          mem_rready_o
    ,output [ 31:0]  gpio_outputs_o
);






localparam REQ_WRITE        = 8'h10;
localparam REQ_READ         = 8'h11;

`define STATE_W        4
`define STATE_R        3:0
localparam STATE_IDLE       = 4'd0;
localparam STATE_LEN        = 4'd2;
localparam STATE_ADDR0      = 4'd3;
localparam STATE_ADDR1      = 4'd4;
localparam STATE_ADDR2      = 4'd5;
localparam STATE_ADDR3      = 4'd6;
localparam STATE_WRITE      = 4'd7;
localparam STATE_READ       = 4'd8;
localparam STATE_DATA0      = 4'd9;
localparam STATE_DATA1      = 4'd10;
localparam STATE_DATA2      = 4'd11;
localparam STATE_DATA3      = 4'd12;




wire       uart_wr_w;
wire [7:0] uart_wr_data_w;
wire       uart_wr_busy_w;

wire       uart_rd_w;
wire [7:0] uart_rd_data_w;
wire       uart_rd_valid_w;

wire       uart_rx_error_w;

wire       tx_valid_w;
wire [7:0] tx_data_w;
wire       tx_accept_w;
wire       read_skip_w;

wire       rx_valid_w;
wire [7:0] rx_data_w;
wire       rx_accept_w;

reg [31:0] mem_addr_q;
reg        mem_busy_q;
reg        mem_wr_q;

reg [7:0]  len_q;


reg [1:0]  data_idx_q;


reg [31:0] data_q;

wire magic_addr_w = (mem_addr_q == GPIO_ADDRESS || mem_addr_q == STS_ADDRESS);




dbg_bridge_uart
#( .UART_DIVISOR_W(32) )
u_uart
(
    .clk_i(clk_i),
    .rst_i(rst_i),


    .bit_div_i((CLK_FREQ / UART_SPEED) - 1),
    .stop_bits_i(1'b0),


    .wr_i(uart_wr_w),
    .data_i(uart_wr_data_w),
    .tx_busy_o(uart_wr_busy_w),


    .rd_i(uart_rd_w),
    .data_o(uart_rd_data_w),
    .rx_ready_o(uart_rd_valid_w),

    .rx_err_o(uart_rx_error_w),


    .rxd_i(uart_rxd_i),
    .txd_o(uart_txd_o)
);




wire uart_tx_pop_w = ~uart_wr_busy_w;

dbg_bridge_fifo
#(
    .WIDTH(8),
    .DEPTH(8),
    .ADDR_W(3)
)
u_fifo_tx
(
    .clk_i(clk_i),
    .rst_i(rst_i),


    .push_i(tx_valid_w),
    .data_in_i(tx_data_w),
    .accept_o(tx_accept_w),


    .pop_i(uart_tx_pop_w),
    .data_out_o(uart_wr_data_w),
    .valid_o(uart_wr_w)
);




dbg_bridge_fifo
#(
    .WIDTH(8),
    .DEPTH(8),
    .ADDR_W(3)
)
u_fifo_rx
(
    .clk_i(clk_i),
    .rst_i(rst_i),


    .push_i(uart_rd_valid_w),
    .data_in_i(uart_rd_data_w),
    .accept_o(uart_rd_w),


    .pop_i(rx_accept_w),
    .data_out_o(rx_data_w),
    .valid_o(rx_valid_w)
);




reg [`STATE_R] state_q;
reg [`STATE_R] next_state_r;

always @ *
begin
    next_state_r = state_q;

    case (next_state_r)



    STATE_IDLE:
    begin
        if (rx_valid_w)
        begin
            case (rx_data_w)
            REQ_WRITE,
            REQ_READ:
                next_state_r = STATE_LEN;
            default:
                ;
            endcase
        end
    end



    STATE_LEN :
    begin
        if (rx_valid_w)
            next_state_r  = STATE_ADDR0;
    end



    STATE_ADDR0 : if (rx_valid_w) next_state_r  = STATE_ADDR1;
    STATE_ADDR1 : if (rx_valid_w) next_state_r  = STATE_ADDR2;
    STATE_ADDR2 : if (rx_valid_w) next_state_r  = STATE_ADDR3;
    STATE_ADDR3 :
    begin
        if (rx_valid_w && mem_wr_q) 
            next_state_r  = STATE_WRITE;
        else if (rx_valid_w) 
            next_state_r  = STATE_READ;            
    end



    STATE_WRITE :
    begin
        if (len_q == 8'b0 && (mem_bvalid_i || magic_addr_w))
            next_state_r  = STATE_IDLE;
        else
            next_state_r  = STATE_WRITE;
    end



    STATE_READ :
    begin

        if (mem_rvalid_i || magic_addr_w)
            next_state_r  = STATE_DATA0;
    end



    STATE_DATA0 :
    begin
        if (read_skip_w)
            next_state_r  = STATE_DATA1;
        else if (tx_accept_w && (len_q == 8'b0))
            next_state_r  = STATE_IDLE;
        else if (tx_accept_w)
            next_state_r  = STATE_DATA1;
    end
    STATE_DATA1 :
    begin
        if (read_skip_w)
            next_state_r  = STATE_DATA2;
        else if (tx_accept_w && (len_q == 8'b0))
            next_state_r  = STATE_IDLE;
        else if (tx_accept_w)
            next_state_r  = STATE_DATA2;
    end
    STATE_DATA2 :
    begin
        if (read_skip_w)
            next_state_r  = STATE_DATA3;
        else if (tx_accept_w && (len_q == 8'b0))
            next_state_r  = STATE_IDLE;
        else if (tx_accept_w)
            next_state_r  = STATE_DATA3;
    end
    STATE_DATA3 :
    begin
        if (tx_accept_w && (len_q != 8'b0))
            next_state_r  = STATE_READ;
        else if (tx_accept_w)
            next_state_r  = STATE_IDLE;
    end
    default:
        ;
    endcase
end


always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    state_q <= STATE_IDLE;
else
    state_q <= next_state_r;






assign tx_valid_w = ((state_q == STATE_DATA0) |
                    (state_q == STATE_DATA1) |
                    (state_q == STATE_DATA2) |
                    (state_q == STATE_DATA3)) && !read_skip_w;


assign rx_accept_w = (state_q == STATE_IDLE) |
                     (state_q == STATE_LEN) |
                     (state_q == STATE_ADDR0) |
                     (state_q == STATE_ADDR1) |
                     (state_q == STATE_ADDR2) |
                     (state_q == STATE_ADDR3) |
                     (state_q == STATE_WRITE && !mem_busy_q);




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    len_q       <= 8'd0;
else if (state_q == STATE_LEN && rx_valid_w)
    len_q[7:0]  <= rx_data_w;
else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
    len_q       <= len_q - 8'd1;
else if (state_q == STATE_READ && ((mem_busy_q && mem_rvalid_i) || magic_addr_w))
    len_q       <= len_q - 8'd1;
else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && (tx_accept_w && !read_skip_w))
    len_q       <= len_q - 8'd1;




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    mem_addr_q        <= 'd0;
else if (state_q == STATE_ADDR0 && rx_valid_w)
    mem_addr_q[31:24] <= rx_data_w;
else if (state_q == STATE_ADDR1 && rx_valid_w)
    mem_addr_q[23:16] <= rx_data_w;
else if (state_q == STATE_ADDR2 && rx_valid_w)
    mem_addr_q[15:8]  <= rx_data_w;
else if (state_q == STATE_ADDR3 && rx_valid_w)
    mem_addr_q[7:0]   <= rx_data_w;

else if (state_q == STATE_WRITE && (mem_busy_q && mem_bvalid_i))
    mem_addr_q        <= {mem_addr_q[31:2], 2'b0} + 'd4;
else if (state_q == STATE_READ && (mem_busy_q && mem_rvalid_i))
    mem_addr_q        <= {mem_addr_q[31:2], 2'b0} + 'd4;




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    data_idx_q <= 2'b0;
else if (state_q == STATE_ADDR3)
    data_idx_q <= rx_data_w[1:0];
else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
    data_idx_q <= data_idx_q + 2'd1;
else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && tx_accept_w && (data_idx_q != 2'b0))
    data_idx_q <= data_idx_q - 2'd1;

assign read_skip_w = (data_idx_q != 2'b0);




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    data_q <= 32'b0;

else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
begin
    case (data_idx_q)
        2'd0: data_q[7:0]   <= rx_data_w;
        2'd1: data_q[15:8]  <= rx_data_w;
        2'd2: data_q[23:16] <= rx_data_w;
        2'd3: data_q[31:24] <= rx_data_w;
    endcase  
end

else if (state_q == STATE_READ && mem_addr_q == GPIO_ADDRESS)
begin
    data_q <= {{(32-32){1'b0}}, gpio_inputs_i};
end

else if (state_q == STATE_READ && mem_addr_q == STS_ADDRESS)
    data_q <= {16'hcafe, 15'd0, mem_busy_q};

else if (state_q == STATE_READ && mem_rvalid_i)
    data_q <= mem_rdata_i;

else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && (tx_accept_w || read_skip_w))
    data_q <= {8'b0, data_q[31:8]};

assign tx_data_w  = data_q[7:0];                  

assign mem_wdata_o = data_q;




reg mem_awvalid_q;
reg mem_awvalid_r;

reg mem_wvalid_q;
reg mem_wvalid_r;

always @ *
begin
    mem_awvalid_r = 1'b0;
    mem_wvalid_r  = 1'b0;


    if (mem_awvalid_o && !mem_awready_i)
        mem_awvalid_r = mem_awvalid_q;
    else if (mem_awvalid_o)
        mem_awvalid_r = 1'b0;

    else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
        mem_awvalid_r = !magic_addr_w;


    if (mem_wvalid_o && !mem_wready_i)
        mem_wvalid_r = mem_wvalid_q;
    else if (mem_wvalid_o)
        mem_wvalid_r = 1'b0;

    else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
        mem_wvalid_r = !magic_addr_w;
end

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    mem_awvalid_q <= 1'b0;
    mem_wvalid_q  <= 1'b0;
end
else
begin
    mem_awvalid_q <= mem_awvalid_r;
    mem_wvalid_q  <= mem_wvalid_r;
end

assign mem_awvalid_o = mem_awvalid_q;
assign mem_wvalid_o  = mem_wvalid_q;
assign mem_awaddr_o  = {mem_addr_q[31:2], 2'b0};
assign mem_awid_o    = AXI_ID;
assign mem_awlen_o   = 8'b0;
assign mem_awburst_o = 2'b01;
assign mem_wlast_o   = 1'b1;

assign mem_bready_o = 1'b1;




reg mem_arvalid_q;
reg mem_arvalid_r;

always @ *
begin
    mem_arvalid_r = 1'b0;


    if (mem_arvalid_o && !mem_arready_i)
        mem_arvalid_r = mem_arvalid_q;
    else if (mem_arvalid_o)
        mem_arvalid_r = 1'b0;
    else if (state_q == STATE_READ && !mem_busy_q)
        mem_arvalid_r = !magic_addr_w;
end

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    mem_arvalid_q <= 1'b0;
else
    mem_arvalid_q <= mem_arvalid_r;

assign mem_arvalid_o = mem_arvalid_q;
assign mem_araddr_o  = {mem_addr_q[31:2], 2'b0};
assign mem_arid_o    = AXI_ID;
assign mem_arlen_o   = 8'b0;
assign mem_arburst_o = 2'b01;

assign mem_rready_o  = 1'b1;




reg [3:0] mem_sel_q;
reg [3:0] mem_sel_r;

always @ *
begin
    mem_sel_r = 4'b1111;

    case (data_idx_q)
    2'd0: mem_sel_r = 4'b0001;
    2'd1: mem_sel_r = 4'b0011;
    2'd2: mem_sel_r = 4'b0111;
    2'd3: mem_sel_r = 4'b1111;
    endcase

    case (mem_addr_q[1:0])
    2'd0: mem_sel_r = mem_sel_r & 4'b1111;
    2'd1: mem_sel_r = mem_sel_r & 4'b1110;
    2'd2: mem_sel_r = mem_sel_r & 4'b1100;
    2'd3: mem_sel_r = mem_sel_r & 4'b1000;
    endcase
end

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    mem_sel_q    <= 4'b0;

else if (state_q == STATE_IDLE)
    mem_sel_q   <= 4'b1111;

else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 8'd1))
    mem_sel_q   <= mem_sel_r;

assign mem_wstrb_o  = mem_sel_q;




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    mem_wr_q    <= 1'b0;
else if (state_q == STATE_IDLE && rx_valid_w)
    mem_wr_q    <= (rx_data_w == REQ_WRITE);




always @ (posedge clk_i or posedge rst_i)
if (rst_i == 1'b1)
    mem_busy_q <= 1'b0;
else if (mem_arvalid_o || mem_awvalid_o)
    mem_busy_q <= 1'b1;
else if (mem_bvalid_i || mem_rvalid_i)
    mem_busy_q <= 1'b0;




reg gpio_wr_q;
reg [31:0] gpio_output_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    gpio_wr_q <= 1'b0;
else if (mem_addr_q == GPIO_ADDRESS && state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
    gpio_wr_q <= 1'b1;
else
    gpio_wr_q <= 1'b0;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    gpio_output_q <= 32'h0;
else if (gpio_wr_q)
    gpio_output_q <= data_q[31:0];

assign gpio_outputs_o = gpio_output_q;



endmodule
module dbg_bridge



#(
     parameter CLK_FREQ         = 14745600
    ,parameter UART_SPEED       = 115200
    ,parameter AXI_ID           = 4'd0
    ,parameter GPIO_ADDRESS     = 32'hf0000000
    ,parameter STS_ADDRESS      = 32'hf0000004
)



(

     input           clk_i
    ,input           rst_i
    ,input           uart_rxd_i
    ,input           mem_awready_i
    ,input           mem_wready_i
    ,input           mem_bvalid_i
    ,input  [  1:0]  mem_bresp_i
    ,input  [  3:0]  mem_bid_i
    ,input           mem_arready_i
    ,input           mem_rvalid_i
    ,input  [ 31:0]  mem_rdata_i
    ,input  [  1:0]  mem_rresp_i
    ,input  [  3:0]  mem_rid_i
    ,input           mem_rlast_i
    ,input  [ 31:0]  gpio_inputs_i


    ,output          uart_txd_o
    ,output          mem_awvalid_o
    ,output [ 31:0]  mem_awaddr_o
    ,output [  3:0]  mem_awid_o
    ,output [  7:0]  mem_awlen_o
    ,output [  1:0]  mem_awburst_o
    ,output          mem_wvalid_o
    ,output [ 31:0]  mem_wdata_o
    ,output [  3:0]  mem_wstrb_o
    ,output          mem_wlast_o
    ,output          mem_bready_o
    ,output          mem_arvalid_o
    ,output [ 31:0]  mem_araddr_o
    ,output [  3:0]  mem_arid_o
    ,output [  7:0]  mem_arlen_o
    ,output [  1:0]  mem_arburst_o
    ,output          mem_rready_o
    ,output [ 31:0]  gpio_outputs_o
);







localparam REQ_WRITE        = 8'h10;
localparam REQ_READ         = 8'h11;

`define STATE_W        4
`define STATE_R        3:0
localparam STATE_IDLE       = 4'd0;
localparam STATE_LEN        = 4'd2;
localparam STATE_ADDR0      = 4'd3;
localparam STATE_ADDR1      = 4'd4;
localparam STATE_ADDR2      = 4'd5;
localparam STATE_ADDR3      = 4'd6;
localparam STATE_WRITE      = 4'd7;
localparam STATE_READ       = 4'd8;
localparam STATE_DATA0      = 4'd9;
localparam STATE_DATA1      = 4'd10;
localparam STATE_DATA2      = 4'd11;
localparam STATE_DATA3      = 4'd12;




wire       uart_wr_w;
wire [7:0] uart_wr_data_w;
wire       uart_wr_busy_w;

wire       uart_rd_w;
wire [7:0] uart_rd_data_w;
wire       uart_rd_valid_w;

wire       uart_rx_error_w;

wire       tx_valid_w;
wire [7:0] tx_data_w;
wire       tx_accept_w;
wire       read_skip_w;

wire       rx_valid_w;
wire [7:0] rx_data_w;
wire       rx_accept_w;

reg [31:0] mem_addr_q;
reg        mem_busy_q;
reg        mem_wr_q;

reg [7:0]  len_q;


reg [1:0]  data_idx_q;


reg [31:0] data_q;

wire magic_addr_w = (mem_addr_q == GPIO_ADDRESS || mem_addr_q == STS_ADDRESS);




dbg_bridge_uart
#( .UART_DIVISOR_W(32) )
u_uart
(
    .clk_i(clk_i),
    .rst_i(rst_i),


    .bit_div_i((CLK_FREQ / UART_SPEED) - 1),
    .stop_bits_i(1'b0),


    .wr_i(uart_wr_w),
    .data_i(uart_wr_data_w),
    .tx_busy_o(uart_wr_busy_w),


    .rd_i(uart_rd_w),
    .data_o(uart_rd_data_w),
    .rx_ready_o(uart_rd_valid_w),

    .rx_err_o(uart_rx_error_w),


    .rxd_i(uart_rxd_i),
    .txd_o(uart_txd_o)
);




wire uart_tx_pop_w = ~uart_wr_busy_w;

dbg_bridge_fifo
#(
    .WIDTH(8),
    .DEPTH(8),
    .ADDR_W(3)
)
u_fifo_tx
(
    .clk_i(clk_i),
    .rst_i(rst_i),


    .push_i(tx_valid_w),
    .data_in_i(tx_data_w),
    .accept_o(tx_accept_w),


    .pop_i(uart_tx_pop_w),
    .data_out_o(uart_wr_data_w),
    .valid_o(uart_wr_w)
);




dbg_bridge_fifo
#(
    .WIDTH(8),
    .DEPTH(8),
    .ADDR_W(3)
)
u_fifo_rx
(
    .clk_i(clk_i),
    .rst_i(rst_i),


    .push_i(uart_rd_valid_w),
    .data_in_i(uart_rd_data_w),
    .accept_o(uart_rd_w),


    .pop_i(rx_accept_w),
    .data_out_o(rx_data_w),
    .valid_o(rx_valid_w)
);




reg [`STATE_R] state_q;
reg [`STATE_R] next_state_r;

always @ *
begin
    next_state_r = state_q;

    case (next_state_r)



    STATE_IDLE:
    begin
        if (rx_valid_w)
        begin
            case (rx_data_w)
            REQ_WRITE,
            REQ_READ:
                next_state_r = STATE_LEN;
            default:
                ;
            endcase
        end
    end



    STATE_LEN :
    begin
        if (rx_valid_w)
            next_state_r  = STATE_ADDR0;
    end



    STATE_ADDR0 : if (rx_valid_w) next_state_r  = STATE_ADDR1;
    STATE_ADDR1 : if (rx_valid_w) next_state_r  = STATE_ADDR2;
    STATE_ADDR2 : if (rx_valid_w) next_state_r  = STATE_ADDR3;
    STATE_ADDR3 :
    begin
        if (rx_valid_w && mem_wr_q) 
            next_state_r  = STATE_WRITE;
        else if (rx_valid_w) 
            next_state_r  = STATE_READ;            
    end



    STATE_WRITE :
    begin
        if (len_q == 8'b0 && (mem_bvalid_i || magic_addr_w))
            next_state_r  = STATE_IDLE;
        else
            next_state_r  = STATE_WRITE;
    end



    STATE_READ :
    begin

        if (mem_rvalid_i || magic_addr_w)
            next_state_r  = STATE_DATA0;
    end



    STATE_DATA0 :
    begin
        if (read_skip_w)
            next_state_r  = STATE_DATA1;
        else if (tx_accept_w && (len_q == 8'b0))
            next_state_r  = STATE_IDLE;
        else if (tx_accept_w)
            next_state_r  = STATE_DATA1;
    end
    STATE_DATA1 :
    begin
        if (read_skip_w)
            next_state_r  = STATE_DATA2;
        else if (tx_accept_w && (len_q == 8'b0))
            next_state_r  = STATE_IDLE;
        else if (tx_accept_w)
            next_state_r  = STATE_DATA2;
    end
    STATE_DATA2 :
    begin
        if (read_skip_w)
            next_state_r  = STATE_DATA3;
        else if (tx_accept_w && (len_q == 8'b0))
            next_state_r  = STATE_IDLE;
        else if (tx_accept_w)
            next_state_r  = STATE_DATA3;
    end
    STATE_DATA3 :
    begin
        if (tx_accept_w && (len_q != 8'b0))
            next_state_r  = STATE_READ;
        else if (tx_accept_w)
            next_state_r  = STATE_IDLE;
    end
    default:
        ;
    endcase
end


always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    state_q <= STATE_IDLE;
else
    state_q <= next_state_r;






assign tx_valid_w = ((state_q == STATE_DATA0) |
                    (state_q == STATE_DATA1) |
                    (state_q == STATE_DATA2) |
                    (state_q == STATE_DATA3)) && !read_skip_w;


assign rx_accept_w = (state_q == STATE_IDLE) |
                     (state_q == STATE_LEN) |
                     (state_q == STATE_ADDR0) |
                     (state_q == STATE_ADDR1) |
                     (state_q == STATE_ADDR2) |
                     (state_q == STATE_ADDR3) |
                     (state_q == STATE_WRITE && !mem_busy_q);




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    len_q       <= 8'd0;
else if (state_q == STATE_LEN && rx_valid_w)
    len_q[7:0]  <= rx_data_w;
else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
    len_q       <= len_q - 8'd1;
else if (state_q == STATE_READ && ((mem_busy_q && mem_rvalid_i) || magic_addr_w))
    len_q       <= len_q - 8'd1;
else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && (tx_accept_w && !read_skip_w))
    len_q       <= len_q - 8'd1;




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    mem_addr_q        <= 'd0;
else if (state_q == STATE_ADDR0 && rx_valid_w)
    mem_addr_q[31:24] <= rx_data_w;
else if (state_q == STATE_ADDR1 && rx_valid_w)
    mem_addr_q[23:16] <= rx_data_w;
else if (state_q == STATE_ADDR2 && rx_valid_w)
    mem_addr_q[15:8]  <= rx_data_w;
else if (state_q == STATE_ADDR3 && rx_valid_w)
    mem_addr_q[7:0]   <= rx_data_w;

else if (state_q == STATE_WRITE && (mem_busy_q && mem_bvalid_i))
    mem_addr_q        <= {mem_addr_q[31:2], 2'b0} + 'd4;
else if (state_q == STATE_READ && (mem_busy_q && mem_rvalid_i))
    mem_addr_q        <= {mem_addr_q[31:2], 2'b0} + 'd4;




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    data_idx_q <= 2'b0;
else if (state_q == STATE_ADDR3)
    data_idx_q <= rx_data_w[1:0];
else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
    data_idx_q <= data_idx_q + 2'd1;
else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && tx_accept_w && (data_idx_q != 2'b0))
    data_idx_q <= data_idx_q - 2'd1;

assign read_skip_w = (data_idx_q != 2'b0);




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    data_q <= 32'b0;

else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
begin
    case (data_idx_q)
        2'd0: data_q[7:0]   <= rx_data_w;
        2'd1: data_q[15:8]  <= rx_data_w;
        2'd2: data_q[23:16] <= rx_data_w;
        2'd3: data_q[31:24] <= rx_data_w;
    endcase  
end

else if (state_q == STATE_READ && mem_addr_q == GPIO_ADDRESS)
begin
    data_q <= {{(32-32){1'b0}}, gpio_inputs_i};
end

else if (state_q == STATE_READ && mem_addr_q == STS_ADDRESS)
    data_q <= {16'hcafe, 15'd0, mem_busy_q};

else if (state_q == STATE_READ && mem_rvalid_i)
    data_q <= mem_rdata_i;

else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && (tx_accept_w || read_skip_w))
    data_q <= {8'b0, data_q[31:8]};

assign tx_data_w  = data_q[7:0];                  

assign mem_wdata_o = data_q;




reg mem_awvalid_q;
reg mem_awvalid_r;

reg mem_wvalid_q;
reg mem_wvalid_r;

always @ *
begin
    mem_awvalid_r = 1'b0;
    mem_wvalid_r  = 1'b0;


    if (mem_awvalid_o && !mem_awready_i)
        mem_awvalid_r = mem_awvalid_q;
    else if (mem_awvalid_o)
        mem_awvalid_r = 1'b0;

    else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
        mem_awvalid_r = !magic_addr_w;


    if (mem_wvalid_o && !mem_wready_i)
        mem_wvalid_r = mem_wvalid_q;
    else if (mem_wvalid_o)
        mem_wvalid_r = 1'b0;

    else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
        mem_wvalid_r = !magic_addr_w;
end

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    mem_awvalid_q <= 1'b0;
    mem_wvalid_q  <= 1'b0;
end
else
begin
    mem_awvalid_q <= mem_awvalid_r;
    mem_wvalid_q  <= mem_wvalid_r;
end

assign mem_awvalid_o = mem_awvalid_q;
assign mem_wvalid_o  = mem_wvalid_q;
assign mem_awaddr_o  = {mem_addr_q[31:2], 2'b0};
assign mem_awid_o    = AXI_ID;
assign mem_awlen_o   = 8'b0;
assign mem_awburst_o = 2'b01;
assign mem_wlast_o   = 1'b1;

assign mem_bready_o = 1'b1;




reg mem_arvalid_q;
reg mem_arvalid_r;

always @ *
begin
    mem_arvalid_r = 1'b0;


    if (mem_arvalid_o && !mem_arready_i)
        mem_arvalid_r = mem_arvalid_q;
    else if (mem_arvalid_o)
        mem_arvalid_r = 1'b0;
    else if (state_q == STATE_READ && !mem_busy_q)
        mem_arvalid_r = !magic_addr_w;
end

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    mem_arvalid_q <= 1'b0;
else
    mem_arvalid_q <= mem_arvalid_r;

assign mem_arvalid_o = mem_arvalid_q;
assign mem_araddr_o  = {mem_addr_q[31:2], 2'b0};
assign mem_arid_o    = AXI_ID;
assign mem_arlen_o   = 8'b0;
assign mem_arburst_o = 2'b01;

assign mem_rready_o  = 1'b1;




reg [3:0] mem_sel_q;
reg [3:0] mem_sel_r;

always @ *
begin
    mem_sel_r = 4'b1111;

    case (data_idx_q)
    2'd0: mem_sel_r = 4'b0001;
    2'd1: mem_sel_r = 4'b0011;
    2'd2: mem_sel_r = 4'b0111;
    2'd3: mem_sel_r = 4'b1111;
    endcase

    case (mem_addr_q[1:0])
    2'd0: mem_sel_r = mem_sel_r & 4'b1111;
    2'd1: mem_sel_r = mem_sel_r & 4'b1110;
    2'd2: mem_sel_r = mem_sel_r & 4'b1100;
    2'd3: mem_sel_r = mem_sel_r & 4'b1000;
    endcase
end

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    mem_sel_q    <= 4'b0;

else if (state_q == STATE_IDLE)
    mem_sel_q   <= 4'b1111;

else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 8'd1))
    mem_sel_q   <= mem_sel_r;

assign mem_wstrb_o  = mem_sel_q;




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    mem_wr_q    <= 1'b0;
else if (state_q == STATE_IDLE && rx_valid_w)
    mem_wr_q    <= (rx_data_w == REQ_WRITE);




always @ (posedge clk_i or posedge rst_i)
if (rst_i == 1'b1)
    mem_busy_q <= 1'b0;
else if (mem_arvalid_o || mem_awvalid_o)
    mem_busy_q <= 1'b1;
else if (mem_bvalid_i || mem_rvalid_i)
    mem_busy_q <= 1'b0;




reg gpio_wr_q;
reg [31:0] gpio_output_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    gpio_wr_q <= 1'b0;
else if (mem_addr_q == GPIO_ADDRESS && state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
    gpio_wr_q <= 1'b1;
else
    gpio_wr_q <= 1'b0;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    gpio_output_q <= 32'h0;
else if (gpio_wr_q)
    gpio_output_q <= data_q[31:0];

assign gpio_outputs_o = gpio_output_q;



endmodule