data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/mt2015_muxdff.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/mt2015_muxdff.v:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out1'\n                                                                                                                               : ... In instance top_module\n        out1 = out2 ^ in;\n        ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/mt2015_muxdff.v:8: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out2'\n                                                                                                                               : ... In instance top_module\n        out2 = out1;\n        ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/mt2015_muxdff.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                               : ... In instance top_module\n        out = out2;\n        ^~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input in, 
    output out);
    wire out1,out2;
    always @(posedge clk) begin
        out1 = out2 ^ in;
        out2 = out1;
        out = out2;
    end
endmodule
module top_module (
    input clk,
    input in, 
    output out);

    wire out1,out2;
    always @(posedge clk) begin
        out1 = out2 ^ in;
        out2 = out1;
        out = out2;
    end
endmodule