data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim/fifo_2clk_tb.v
 line:30: before: "forever"
1: b'%Warning-STMTDLY: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim/fifo_2clk_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #3 forever din_clk = #3 ~din_clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim/fifo_2clk_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #4 forever dout_clk = #4 ~dout_clk;\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim/fifo_2clk_tb.v:42: syntax error, unexpected \'@\'\n      @(negedge din_clk);\n      ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifo_2clk_tb;




  reg din_clk, dout_clk;
  reg rst;

  initial begin
    din_clk = 0;
    #3 forever din_clk = #3 ~din_clk;
  end

  initial begin
    dout_clk = 0;
    #4 forever dout_clk = #4 ~dout_clk;
  end

  integer i;
  initial begin
    rst <= 1;
    for (i=1; i<3; i=i+1)
      @(negedge din_clk);
    rst <= 0;
  end




  wire       din_valid, din_ready;
  wire [7:0] din_data;
  stream_source #(
    .Filename    ("in.dat"),
    .NumSymbols (1),
    .SymbolBits ({32'd8}))
  src (
    .clk       (din_clk),
    .rst       (rst),
    .dout_ready(din_ready),
    .dout_valid(din_valid),
    .dout_data (din_data));




  wire        dout_valid, dout_ready;
  wire [7:0]  dout_data;

  stream_fifo_2clk #(
    .Width    (8),
    .Depth    (64))
  fifo(
    .din_clk   (din_clk),
    .din_rst   (rst),
    .din_valid (din_valid),
    .din_ready (din_ready),
    .din_data  (din_data),
    .din_free  ( ),

    .dout_clk  (dout_clk),
    .dout_rst  (rst),
    .dout_valid(dout_valid),
    .dout_ready(dout_ready),
    .dout_data (dout_data),
    .dout_used ( ));




  wire       done, err;
  stream_sink #(
    .FilenameDump ("out.dat"),
    .FilenameRef  ("ref.dat"),
    .CheckData    (1),
    .NumSymbols   (1),
    .SymbolBits   ({32'd8}))
  snk (
    .clk       (dout_clk),
    .rst       (rst),
    .din_ready (dout_ready),
    .din_valid (dout_valid),
    .din_data  (dout_data),
    .done      (done),
    .err       (err));




  reg        finished;
  always @(posedge dout_clk) begin
    if (!finished) begin
      if (done) begin
        if (err)
          $display("***SIMULATION FAILED***");
        else
          $display("***SIMULATION PASSED***");

        finished = 1;
      end
    end
    if (rst)
      finished = 0;
  end


endmodule
module fifo_2clk_tb;





  reg din_clk, dout_clk;
  reg rst;

  initial begin
    din_clk = 0;
    #3 forever din_clk = #3 ~din_clk;
  end

  initial begin
    dout_clk = 0;
    #4 forever dout_clk = #4 ~dout_clk;
  end

  integer i;
  initial begin
    rst <= 1;
    for (i=1; i<3; i=i+1)
      @(negedge din_clk);
    rst <= 0;
  end




  wire       din_valid, din_ready;
  wire [7:0] din_data;
  stream_source #(
    .Filename    ("in.dat"),
    .NumSymbols (1),
    .SymbolBits ({32'd8}))
  src (
    .clk       (din_clk),
    .rst       (rst),
    .dout_ready(din_ready),
    .dout_valid(din_valid),
    .dout_data (din_data));




  wire        dout_valid, dout_ready;
  wire [7:0]  dout_data;

  stream_fifo_2clk #(
    .Width    (8),
    .Depth    (64))
  fifo(
    .din_clk   (din_clk),
    .din_rst   (rst),
    .din_valid (din_valid),
    .din_ready (din_ready),
    .din_data  (din_data),
    .din_free  ( ),

    .dout_clk  (dout_clk),
    .dout_rst  (rst),
    .dout_valid(dout_valid),
    .dout_ready(dout_ready),
    .dout_data (dout_data),
    .dout_used ( ));




  wire       done, err;
  stream_sink #(
    .FilenameDump ("out.dat"),
    .FilenameRef  ("ref.dat"),
    .CheckData    (1),
    .NumSymbols   (1),
    .SymbolBits   ({32'd8}))
  snk (
    .clk       (dout_clk),
    .rst       (rst),
    .din_ready (dout_ready),
    .din_valid (dout_valid),
    .din_data  (dout_data),
    .done      (done),
    .err       (err));




  reg        finished;
  always @(posedge dout_clk) begin
    if (!finished) begin
      if (done) begin
        if (err)
          $display("***SIMULATION FAILED***");
        else
          $display("***SIMULATION PASSED***");

        finished = 1;
      end
    end
    if (rst)
      finished = 0;
  end


endmodule