data/full_repos/permissive/12298861/ver/uut_1_bytep.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/12298861/ver/uut_1_bytep.v:77: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sof_o'\n                                                                            : ... In instance uut_1_bytep\n        sof_o        = sof_z4;\n        ^~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module uut_1_bytep
(
    output wire [31:0] data_o,
    output wire        sof_o,

    input  wire [7:0]  data_i,
    input  wire        sof_i,
    input  wire        pclk_i
);



    reg  [7:0]   data_z1;
    reg          sof_z1;

    reg  [7:0]   data_z2;
    reg          sof_z2;

    reg  [7:0]   data_z3;
    reg          sof_z3;

    reg  [7:0]   data_z4;
    reg          sof_z4;




    always @ (posedge pclk_i) begin
        data_z1[7:0] <= data_i[7:0];
        sof_z1       <= sof_i;

        data_z2[7:0] <= data_z1[7:0];
        sof_z2       <= sof_z1;

        data_z3[7:0] <= data_z2[7:0];
        sof_z3       <= sof_z2;

        data_z4[7:0] <= data_z3[7:0];
        sof_z4       <= sof_z3;
    end


    always @ (*)
    begin
        data_o[31:0] = {data_z4[7:0], data_z3[7:0], data_z2[7:0], data_z1[7:0]};
        sof_o        = sof_z4;
    end

endmodule
module uut_1_bytep
(
    output wire [31:0] data_o,
    output wire        sof_o,

    input  wire [7:0]  data_i,
    input  wire        sof_i,
    input  wire        pclk_i
);




    reg  [7:0]   data_z1;
    reg          sof_z1;

    reg  [7:0]   data_z2;
    reg          sof_z2;

    reg  [7:0]   data_z3;
    reg          sof_z3;

    reg  [7:0]   data_z4;
    reg          sof_z4;




    always @ (posedge pclk_i) begin
        data_z1[7:0] <= data_i[7:0];
        sof_z1       <= sof_i;

        data_z2[7:0] <= data_z1[7:0];
        sof_z2       <= sof_z1;

        data_z3[7:0] <= data_z2[7:0];
        sof_z3       <= sof_z2;

        data_z4[7:0] <= data_z3[7:0];
        sof_z4       <= sof_z3;
    end


    always @ (*)
    begin
        data_o[31:0] = {data_z4[7:0], data_z3[7:0], data_z2[7:0], data_z1[7:0]};
        sof_o        = sof_z4;
    end

endmodule