data/full_repos/permissive/17247495/src/rtl/uart.v
1: b"%Error: data/full_repos/permissive/17247495/src/rtl/uart.v:136: Cannot find file containing module: 'uart_core'\n  uart_core core(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17247495/src/rtl,data/full_repos/permissive/17247495/uart_core\n             data/full_repos/permissive/17247495/src/rtl,data/full_repos/permissive/17247495/uart_core.v\n             data/full_repos/permissive/17247495/src/rtl,data/full_repos/permissive/17247495/uart_core.sv\n             uart_core\n             uart_core.v\n             uart_core.sv\n             obj_dir/uart_core\n             obj_dir/uart_core.v\n             obj_dir/uart_core.sv\n%Error: Exiting due to 1 error(s)\n"
module uart(
            input wire           clk,
            input wire           reset_n,

            input wire           cs,
            input wire           we,
            input wire [7 : 0]   address,
            input wire [31 : 0]  write_data,
            output wire [31 : 0] read_data,

            input wire           rxd,
            output wire          txd
           );





  localparam ADDR_CORE_NAME0   = 8'h00;
  localparam ADDR_CORE_NAME1   = 8'h01;
  localparam ADDR_CORE_VERSION = 8'h02;

  localparam ADDR_BIT_RATE     = 8'h10;
  localparam ADDR_DATA_BITS    = 8'h11;
  localparam ADDR_STOP_BITS    = 8'h12;

  localparam ADDR_RX_STATUS    = 8'h20;
  localparam ADDR_RX_DATA      = 8'h21;

  localparam ADDR_TX_STATUS    = 8'h40;
  localparam ADDR_TX_DATA      = 8'h41;


  localparam CORE_NAME0   = 32'h75617274;
  localparam CORE_NAME1   = 32'h20202020;
  localparam CORE_VERSION = 32'h302e3032;







  localparam DEFAULT_BIT_RATE  = 16'd5208;
  localparam DEFAULT_DATA_BITS = 4'h8;
  localparam DEFAULT_STOP_BITS = 2'h1;





  reg [15 : 0] bit_rate_reg;
  reg          bit_rate_we;

  reg [3 : 0]  data_bits_reg;
  reg          data_bits_we;

  reg [1 : 0]  stop_bits_reg;
  reg          stop_bits_we;





  wire          core_rxd_syn;
  wire [7 : 0]  core_rxd_data;
  reg           core_rxd_ack;

  reg           core_txd_syn;
  reg [7 : 0]   core_txd_data;
  wire          core_txd_ack;

  reg [31 : 0]  tmp_read_data;





  assign read_data     = tmp_read_data;







  uart_core core(
                 .clk(clk),
                 .reset_n(reset_n),


                 .bit_rate(bit_rate_reg),
                 .data_bits(data_bits_reg),
                 .stop_bits(stop_bits_reg),


                 .rxd(rxd),
                 .txd(txd),


                 .rxd_syn(core_rxd_syn),
                 .rxd_data(core_rxd_data),
                 .rxd_ack(core_rxd_ack),


                 .txd_syn(core_txd_syn),
                 .txd_data(core_txd_data),
                 .txd_ack(core_txd_ack)
                );









  always @ (posedge clk)
    begin: reg_update
      if (!reset_n)
        begin
          bit_rate_reg  <= DEFAULT_BIT_RATE;
          data_bits_reg <= DEFAULT_DATA_BITS;
          stop_bits_reg <= DEFAULT_STOP_BITS;
        end
      else
        begin
          if (bit_rate_we) begin
            bit_rate_reg  <= write_data[15 : 0];
          end

          if (data_bits_we) begin
            data_bits_reg  <= write_data[3 : 0];
          end

          if (stop_bits_we) begin
            stop_bits_reg  <= write_data[1 : 0];
          end
        end
    end








  always @*
    begin: api

      bit_rate_we   = 1'h0;
      data_bits_we  = 1'h0;
      stop_bits_we  = 1'h0;
      core_rxd_ack  = 1'h0;
      core_txd_syn  = 1'h0;
      tmp_read_data = 32'h0;

      core_txd_data = write_data[7 : 0];

      if (cs) begin
        if (we) begin
          case (address)
            ADDR_BIT_RATE: begin
              bit_rate_we  = 1;
            end

            ADDR_DATA_BITS: begin
              data_bits_we  = 1;
            end

            ADDR_STOP_BITS: begin
              stop_bits_we  = 1;
            end

	    ADDR_TX_DATA: begin
	      core_txd_syn = 1'h1;
	    end

            default: begin
            end
          endcase
        end

	else begin
          case (address)
            ADDR_CORE_NAME0: begin
              tmp_read_data = CORE_NAME0;
            end

            ADDR_CORE_NAME1: begin
              tmp_read_data = CORE_NAME1;
            end

            ADDR_CORE_VERSION: begin
              tmp_read_data = CORE_VERSION;
            end

            ADDR_BIT_RATE: begin
              tmp_read_data = {16'h0, bit_rate_reg};
            end

            ADDR_DATA_BITS: begin
              tmp_read_data = {28'h0, data_bits_reg};
            end

            ADDR_STOP_BITS: begin
              tmp_read_data = {30'h0, stop_bits_reg};
            end

	    ADDR_RX_STATUS: begin
              tmp_read_data = {31'h0, core_rxd_syn};
	    end

	    ADDR_RX_DATA: begin
	      core_rxd_ack  = 1'h1;
              tmp_read_data = {24'h0, core_rxd_data};
	    end

	    ADDR_TX_STATUS: begin
              tmp_read_data = {31'h0, core_txd_ack};
	    end

            default: begin
            end
          endcase
        end
      end
    end

endmodule
module uart(
            input wire           clk,
            input wire           reset_n,

            input wire           cs,
            input wire           we,
            input wire [7 : 0]   address,
            input wire [31 : 0]  write_data,
            output wire [31 : 0] read_data,

            input wire           rxd,
            output wire          txd
           );






  localparam ADDR_CORE_NAME0   = 8'h00;
  localparam ADDR_CORE_NAME1   = 8'h01;
  localparam ADDR_CORE_VERSION = 8'h02;

  localparam ADDR_BIT_RATE     = 8'h10;
  localparam ADDR_DATA_BITS    = 8'h11;
  localparam ADDR_STOP_BITS    = 8'h12;

  localparam ADDR_RX_STATUS    = 8'h20;
  localparam ADDR_RX_DATA      = 8'h21;

  localparam ADDR_TX_STATUS    = 8'h40;
  localparam ADDR_TX_DATA      = 8'h41;


  localparam CORE_NAME0   = 32'h75617274;
  localparam CORE_NAME1   = 32'h20202020;
  localparam CORE_VERSION = 32'h302e3032;







  localparam DEFAULT_BIT_RATE  = 16'd5208;
  localparam DEFAULT_DATA_BITS = 4'h8;
  localparam DEFAULT_STOP_BITS = 2'h1;





  reg [15 : 0] bit_rate_reg;
  reg          bit_rate_we;

  reg [3 : 0]  data_bits_reg;
  reg          data_bits_we;

  reg [1 : 0]  stop_bits_reg;
  reg          stop_bits_we;





  wire          core_rxd_syn;
  wire [7 : 0]  core_rxd_data;
  reg           core_rxd_ack;

  reg           core_txd_syn;
  reg [7 : 0]   core_txd_data;
  wire          core_txd_ack;

  reg [31 : 0]  tmp_read_data;





  assign read_data     = tmp_read_data;







  uart_core core(
                 .clk(clk),
                 .reset_n(reset_n),


                 .bit_rate(bit_rate_reg),
                 .data_bits(data_bits_reg),
                 .stop_bits(stop_bits_reg),


                 .rxd(rxd),
                 .txd(txd),


                 .rxd_syn(core_rxd_syn),
                 .rxd_data(core_rxd_data),
                 .rxd_ack(core_rxd_ack),


                 .txd_syn(core_txd_syn),
                 .txd_data(core_txd_data),
                 .txd_ack(core_txd_ack)
                );









  always @ (posedge clk)
    begin: reg_update
      if (!reset_n)
        begin
          bit_rate_reg  <= DEFAULT_BIT_RATE;
          data_bits_reg <= DEFAULT_DATA_BITS;
          stop_bits_reg <= DEFAULT_STOP_BITS;
        end
      else
        begin
          if (bit_rate_we) begin
            bit_rate_reg  <= write_data[15 : 0];
          end

          if (data_bits_we) begin
            data_bits_reg  <= write_data[3 : 0];
          end

          if (stop_bits_we) begin
            stop_bits_reg  <= write_data[1 : 0];
          end
        end
    end








  always @*
    begin: api

      bit_rate_we   = 1'h0;
      data_bits_we  = 1'h0;
      stop_bits_we  = 1'h0;
      core_rxd_ack  = 1'h0;
      core_txd_syn  = 1'h0;
      tmp_read_data = 32'h0;

      core_txd_data = write_data[7 : 0];

      if (cs) begin
        if (we) begin
          case (address)
            ADDR_BIT_RATE: begin
              bit_rate_we  = 1;
            end

            ADDR_DATA_BITS: begin
              data_bits_we  = 1;
            end

            ADDR_STOP_BITS: begin
              stop_bits_we  = 1;
            end

	    ADDR_TX_DATA: begin
	      core_txd_syn = 1'h1;
	    end

            default: begin
            end
          endcase
        end

	else begin
          case (address)
            ADDR_CORE_NAME0: begin
              tmp_read_data = CORE_NAME0;
            end

            ADDR_CORE_NAME1: begin
              tmp_read_data = CORE_NAME1;
            end

            ADDR_CORE_VERSION: begin
              tmp_read_data = CORE_VERSION;
            end

            ADDR_BIT_RATE: begin
              tmp_read_data = {16'h0, bit_rate_reg};
            end

            ADDR_DATA_BITS: begin
              tmp_read_data = {28'h0, data_bits_reg};
            end

            ADDR_STOP_BITS: begin
              tmp_read_data = {30'h0, stop_bits_reg};
            end

	    ADDR_RX_STATUS: begin
              tmp_read_data = {31'h0, core_rxd_syn};
	    end

	    ADDR_RX_DATA: begin
	      core_rxd_ack  = 1'h1;
              tmp_read_data = {24'h0, core_rxd_data};
	    end

	    ADDR_TX_STATUS: begin
              tmp_read_data = {31'h0, core_txd_ack};
	    end

            default: begin
            end
          endcase
        end
      end
    end

endmodule