data/full_repos/permissive/143278/ivltests/udp_prop.v
 line:14: before: "d"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_prop.v:9: Unsupported: Ignoring delay on this delayed statement.\n   always begin #5 cp=0; #5 cp=1; end\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_prop.v:9: Unsupported: Ignoring delay on this delayed statement.\n   always begin #5 cp=0; #5 cp=1; end\n                         ^\n%Error: data/full_repos/permissive/143278/ivltests/udp_prop.v:13: syntax error, unexpected \'@\'\n @(negedge cp)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_prop.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #1 $finish;\n        ^\n%Error: data/full_repos/permissive/143278/ivltests/udp_prop.v:22: syntax error, unexpected end\n     end\n     ^~~\n%Error: data/full_repos/permissive/143278/ivltests/udp_prop.v:32: Unsupported or unknown PLI call: $monitor\n   initial $monitor($time,,cp,,d,,q);\n           ^~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   reg  cp;
   reg	d;
   wire q;

   dff ff(q, cp, d);

   always begin #5 cp=0; #5 cp=1; end

   always
     begin
	@(negedge cp)
	  d <= ~d;

	@(posedge cp)
	  if (q !== 'bx && d === q)
	    begin
	       $display("FAILED, d=%b, q=%b", d, q);
	       #1 $finish;
	    end
     end

   initial
     begin
	#1 d <= 1;
	#22;
	$display("PASSED");
	$finish;
     end

   initial $monitor($time,,cp,,d,,q);

endmodule
module test;


   reg  cp;
   reg	d;
   wire q;

   dff ff(q, cp, d);

   always begin #5 cp=0; #5 cp=1; end

   always
     begin
	@(negedge cp)
	  d <= ~d;

	@(posedge cp)
	  if (q !== 'bx && d === q)
	    begin
	       $display("FAILED, d=%b, q=%b", d, q);
	       #1 $finish;
	    end
     end

   initial
     begin
	#1 d <= 1;
	#22;
	$display("PASSED");
	$finish;
     end

   initial $monitor($time,,cp,,d,,q);

endmodule