data/full_repos/permissive/159830616/YJ431_PL.srcs/sources_1/new/FB_LED.v
'utf-8' codec can't decode byte 0xd7 in position 622: invalid continuation byte
1: b'%Warning-MULTITOP: data/full_repos/permissive/159830616/YJ431_PL.srcs/sources_1/new/FB_LED.v:171: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'FB_BZLEDREG\'\nmodule FB_BZLEDREG(\n       ^~~~~~~~~~~\n                                                                                                : ... Top module \'BZLED\'\nmodule BZLED(\n       ^~~~~\n%Error: Exiting due to 1 warning(s)\n'
module FB_BZLEDREG(
	RST_n,
	BUS_ADDR,
	BUS_DATA,
	BUS_CS,

	BUS_read,
	BUS_write,

	BZLED_BASE,


	FREQ_Cnt_Reg,
	BZ_Puty_Reg,
	LEDR_Puty_Reg,
	LEDG_Puty_Reg,
	LEDB_Puty_Reg
    );


input RST_n;
input [31:0] BUS_ADDR;
inout [31:0] BUS_DATA;
input BUS_CS;

input BUS_read;
input BUS_write;

input [9:0]BZLED_BASE;


output reg [31:0] FREQ_Cnt_Reg = 32'd100000;
output reg [31:0] BZ_Puty_Reg = 32'd1000000000;
output reg [31:0] LEDR_Puty_Reg = 32'd50000;
output reg [31:0] LEDG_Puty_Reg = 32'd50000;
output reg [31:0] LEDB_Puty_Reg = 32'd80000;



wire AD_TRI_n;
wire ADD_COMF;



reg [31:0] BUS_DATA_REG = 32'b0;


assign ADD_COMF = ( BUS_ADDR[31:22] == BZLED_BASE[9:0] ) ? 1'b1:1'b0;

assign AD_TRI_n = ADD_COMF & ~BUS_CS & BUS_read ;



assign BUS_DATA = AD_TRI_n ? BUS_DATA_REG : 32'bz;




always@( posedge BUS_CS or negedge RST_n )
	if ( !RST_n ) begin
		FREQ_Cnt_Reg <= 32'd1;
		BZ_Puty_Reg <= 32'b0;
		LEDR_Puty_Reg <= 32'b0;
		LEDG_Puty_Reg <= 32'b0;
		LEDB_Puty_Reg <= 32'b0;
	end
	else begin
		if ( ADD_COMF ) begin
			if ( BUS_write == 1'b1 ) begin
				case(BUS_ADDR[21:0])
					22'b00000: begin				
                        FREQ_Cnt_Reg [31:0] <= BUS_DATA [31:0];
                        BZ_Puty_Reg   <= BZ_Puty_Reg;
                        LEDR_Puty_Reg <= LEDR_Puty_Reg;
                        LEDG_Puty_Reg <= LEDG_Puty_Reg;
                        LEDB_Puty_Reg <= LEDB_Puty_Reg;	
					end				
					22'b00100: begin
                        FREQ_Cnt_Reg  <= FREQ_Cnt_Reg;
                        BZ_Puty_Reg [31:0] <= BUS_DATA [31:0];
                        LEDR_Puty_Reg <= LEDR_Puty_Reg;
                        LEDG_Puty_Reg <= LEDG_Puty_Reg;
                        LEDB_Puty_Reg <= LEDB_Puty_Reg;
					end
					22'b01000: begin
                        FREQ_Cnt_Reg  <= FREQ_Cnt_Reg;
                        BZ_Puty_Reg   <= BZ_Puty_Reg;
                        if ( BUS_DATA [31:0] < FREQ_Cnt_Reg [31:0] ) begin
                            LEDR_Puty_Reg[31:0] <= BUS_DATA [31:0];
                        end
                        LEDG_Puty_Reg <= LEDG_Puty_Reg;
                        LEDB_Puty_Reg <= LEDB_Puty_Reg;
					end
					22'b01100: begin
                        FREQ_Cnt_Reg  <= FREQ_Cnt_Reg;
                        BZ_Puty_Reg   <= BZ_Puty_Reg;
                        LEDR_Puty_Reg <= LEDR_Puty_Reg;
                        if ( BUS_DATA [31:0] < FREQ_Cnt_Reg [31:0] ) begin
                            LEDG_Puty_Reg[31:0] <= BUS_DATA [31:0];
                        end
                        LEDB_Puty_Reg <= LEDB_Puty_Reg;
					end
					22'b10000: begin
                        FREQ_Cnt_Reg  <= FREQ_Cnt_Reg;
                        BZ_Puty_Reg   <= BZ_Puty_Reg;
                        LEDR_Puty_Reg <= LEDR_Puty_Reg;
                        LEDG_Puty_Reg <= LEDG_Puty_Reg;
                        if ( BUS_DATA [31:0] < FREQ_Cnt_Reg [31:0] ) begin
                            LEDB_Puty_Reg[31:0] <= BUS_DATA [31:0];
                        end
					end
				endcase
			end		
		end
	end



always@( negedge BUS_CS or negedge RST_n )
	if ( !RST_n ) begin
		BUS_DATA_REG <= 32'b0;
	end

	else begin
		if ( ADD_COMF ) begin
			if ( BUS_write == 1'b0 ) begin
				case(BUS_ADDR[21:0])
					22'b00000:
					BUS_DATA_REG [31:0] <= FREQ_Cnt_Reg [31:0];
					22'b00100:
					BUS_DATA_REG [31:0] <= BZ_Puty_Reg [31:0];
					22'b01000:
					BUS_DATA_REG [31:0] <= LEDR_Puty_Reg[31:0];
					22'b01100:
					BUS_DATA_REG [31:0] <= LEDG_Puty_Reg[31:0];
					22'b10000:
					BUS_DATA_REG [31:0] <= LEDB_Puty_Reg[31:0];
					default:
					BUS_DATA_REG[31:0] <=  32'hffffffff;
				endcase
			end
		end
	end

endmodule
module FB_BZLEDREG(
	RST_n,
	BUS_ADDR,
	BUS_DATA,
	BUS_CS,

	BUS_read,
	BUS_write,

	BZLED_BASE,


	FREQ_Cnt_Reg,
	BZ_Puty_Reg,
	LEDR_Puty_Reg,
	LEDG_Puty_Reg,
	LEDB_Puty_Reg
    );



input RST_n;
input [31:0] BUS_ADDR;
inout [31:0] BUS_DATA;
input BUS_CS;

input BUS_read;
input BUS_write;

input [9:0]BZLED_BASE;


output reg [31:0] FREQ_Cnt_Reg = 32'd100000;
output reg [31:0] BZ_Puty_Reg = 32'd1000000000;
output reg [31:0] LEDR_Puty_Reg = 32'd50000;
output reg [31:0] LEDG_Puty_Reg = 32'd50000;
output reg [31:0] LEDB_Puty_Reg = 32'd80000;



wire AD_TRI_n;
wire ADD_COMF;



reg [31:0] BUS_DATA_REG = 32'b0;


assign ADD_COMF = ( BUS_ADDR[31:22] == BZLED_BASE[9:0] ) ? 1'b1:1'b0;

assign AD_TRI_n = ADD_COMF & ~BUS_CS & BUS_read ;



assign BUS_DATA = AD_TRI_n ? BUS_DATA_REG : 32'bz;




always@( posedge BUS_CS or negedge RST_n )
	if ( !RST_n ) begin
		FREQ_Cnt_Reg <= 32'd1;
		BZ_Puty_Reg <= 32'b0;
		LEDR_Puty_Reg <= 32'b0;
		LEDG_Puty_Reg <= 32'b0;
		LEDB_Puty_Reg <= 32'b0;
	end
	else begin
		if ( ADD_COMF ) begin
			if ( BUS_write == 1'b1 ) begin
				case(BUS_ADDR[21:0])
					22'b00000: begin				
                        FREQ_Cnt_Reg [31:0] <= BUS_DATA [31:0];
                        BZ_Puty_Reg   <= BZ_Puty_Reg;
                        LEDR_Puty_Reg <= LEDR_Puty_Reg;
                        LEDG_Puty_Reg <= LEDG_Puty_Reg;
                        LEDB_Puty_Reg <= LEDB_Puty_Reg;	
					end				
					22'b00100: begin
                        FREQ_Cnt_Reg  <= FREQ_Cnt_Reg;
                        BZ_Puty_Reg [31:0] <= BUS_DATA [31:0];
                        LEDR_Puty_Reg <= LEDR_Puty_Reg;
                        LEDG_Puty_Reg <= LEDG_Puty_Reg;
                        LEDB_Puty_Reg <= LEDB_Puty_Reg;
					end
					22'b01000: begin
                        FREQ_Cnt_Reg  <= FREQ_Cnt_Reg;
                        BZ_Puty_Reg   <= BZ_Puty_Reg;
                        if ( BUS_DATA [31:0] < FREQ_Cnt_Reg [31:0] ) begin
                            LEDR_Puty_Reg[31:0] <= BUS_DATA [31:0];
                        end
                        LEDG_Puty_Reg <= LEDG_Puty_Reg;
                        LEDB_Puty_Reg <= LEDB_Puty_Reg;
					end
					22'b01100: begin
                        FREQ_Cnt_Reg  <= FREQ_Cnt_Reg;
                        BZ_Puty_Reg   <= BZ_Puty_Reg;
                        LEDR_Puty_Reg <= LEDR_Puty_Reg;
                        if ( BUS_DATA [31:0] < FREQ_Cnt_Reg [31:0] ) begin
                            LEDG_Puty_Reg[31:0] <= BUS_DATA [31:0];
                        end
                        LEDB_Puty_Reg <= LEDB_Puty_Reg;
					end
					22'b10000: begin
                        FREQ_Cnt_Reg  <= FREQ_Cnt_Reg;
                        BZ_Puty_Reg   <= BZ_Puty_Reg;
                        LEDR_Puty_Reg <= LEDR_Puty_Reg;
                        LEDG_Puty_Reg <= LEDG_Puty_Reg;
                        if ( BUS_DATA [31:0] < FREQ_Cnt_Reg [31:0] ) begin
                            LEDB_Puty_Reg[31:0] <= BUS_DATA [31:0];
                        end
					end
				endcase
			end		
		end
	end



always@( negedge BUS_CS or negedge RST_n )
	if ( !RST_n ) begin
		BUS_DATA_REG <= 32'b0;
	end

	else begin
		if ( ADD_COMF ) begin
			if ( BUS_write == 1'b0 ) begin
				case(BUS_ADDR[21:0])
					22'b00000:
					BUS_DATA_REG [31:0] <= FREQ_Cnt_Reg [31:0];
					22'b00100:
					BUS_DATA_REG [31:0] <= BZ_Puty_Reg [31:0];
					22'b01000:
					BUS_DATA_REG [31:0] <= LEDR_Puty_Reg[31:0];
					22'b01100:
					BUS_DATA_REG [31:0] <= LEDG_Puty_Reg[31:0];
					22'b10000:
					BUS_DATA_REG [31:0] <= LEDB_Puty_Reg[31:0];
					default:
					BUS_DATA_REG[31:0] <=  32'hffffffff;
				endcase
			end
		end
	end

endmodule