data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_dma_irq_generator.sv
'utf-8' codec can't decode byte 0xa9 in position 210: invalid start byte
1: b'%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_dma_irq_generator.sv:42: Unsupported: event data types\n event start_Monitor;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_dma_irq_generator.sv:57: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_dma_irq_generator.sv:62: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n  results_file=$fopen("../out/top_results.txt");\n               ^~~~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_dma_irq_generator.sv:76: syntax error, unexpected \'@\'\n   @(posedge clk_in);\n   ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_dma_irq_generator.sv:87: syntax error, unexpected \'@\'\n   @(posedge clk_in);\n   ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_dma_irq_generator.sv:97: Unsupported or unknown PLI call: $timeformat\n   $timeformat(-9, 0, " ns", 9);\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_dma_irq_generator.sv:98: syntax error, unexpected \'@\'\n   @(start_Monitor)\n   ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_dma_irq_generator.sv:110: syntax error, unexpected endtask\n endtask    \n ^~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_dma_irq_generator.sv:116: syntax error, unexpected \'@\'\n  @ (posedge clk_in);\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/pcie/examples/sonic_chaining_dma/testbench/sonic/test_sonic_dma_irq_generator.sv:118: syntax error, unexpected \'@\'\n  @ (posedge clk_in);\n  ^\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module    test_sonic_dma_irq_generator	(

	input   logic			clk_in,
	input   logic  [31:0]	data_available,
	input   logic			irq,


	output  logic            rstn,
	output  logic  [12:0]    rp,
	output  logic  [12:0]    wp
	);

	event start_Monitor;


	integer		results_file;

	int cnt;


	initial
	begin

		$display("Initialize Signals");
		rstn <= 0;

		$display("Wait for 100 ns");
		#100

		CpuReset;
		

		results_file=$fopen("../out/top_results.txt");
		$fdisplay(results_file, " test_sonic_dma_irq_generator testbench results");
		$fwrite(results_file, "\n");
		DisplayHeader;
		
		rp = 0;
		wp = 0;
		for (cnt=0; cnt < 2000; cnt=cnt+1) begin
			if(wp == 25600) begin
				wp <= 0;
			end
			else begin
				wp <= wp+1;
			end
			@(posedge clk_in);
		end
	

		for (cnt =0 ; cnt < 2000; cnt=cnt+1) begin
			if(rp == 8000) begin
				rp <= 0;
			end
			else begin
				rp <= rp+1;
			end
			@(posedge clk_in);
		end

		$fclose(results_file);
		$stop;
	end


	always 
	begin: Monitor
	  $timeformat(-9, 0, " ns", 9);
	  @(start_Monitor)
	  forever @(negedge clk_in)
	  begin

	  end
	end



	task DisplayHeader;
	  $fdisplay(results_file,"                       data_in      data_out ");
	  $fdisplay(results_file,"                 ============================");
	endtask    

	task CpuReset;
	begin
		@ (posedge clk_in);
		rstn = 0;
		@ (posedge clk_in);
		rstn = 1;
		@ (posedge clk_in);
	end
	endtask

endmodule
module    test_sonic_dma_irq_generator	(

	input   logic			clk_in,
	input   logic  [31:0]	data_available,
	input   logic			irq,


	output  logic            rstn,
	output  logic  [12:0]    rp,
	output  logic  [12:0]    wp
	);


	event start_Monitor;


	integer		results_file;

	int cnt;


	initial
	begin

		$display("Initialize Signals");
		rstn <= 0;

		$display("Wait for 100 ns");
		#100

		CpuReset;
		

		results_file=$fopen("../out/top_results.txt");
		$fdisplay(results_file, " test_sonic_dma_irq_generator testbench results");
		$fwrite(results_file, "\n");
		DisplayHeader;
		
		rp = 0;
		wp = 0;
		for (cnt=0; cnt < 2000; cnt=cnt+1) begin
			if(wp == 25600) begin
				wp <= 0;
			end
			else begin
				wp <= wp+1;
			end
			@(posedge clk_in);
		end
	

		for (cnt =0 ; cnt < 2000; cnt=cnt+1) begin
			if(rp == 8000) begin
				rp <= 0;
			end
			else begin
				rp <= rp+1;
			end
			@(posedge clk_in);
		end

		$fclose(results_file);
		$stop;
	end


	always 
	begin: Monitor
	  $timeformat(-9, 0, " ns", 9);
	  @(start_Monitor)
	  forever @(negedge clk_in)
	  begin

	  end
	end



	task DisplayHeader;
	  $fdisplay(results_file,"                       data_in      data_out ");
	  $fdisplay(results_file,"                 ============================");
	endtask    

	task CpuReset;
	begin
		@ (posedge clk_in);
		rstn = 0;
		@ (posedge clk_in);
		rstn = 1;
		@ (posedge clk_in);
	end
	endtask

endmodule