data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v
1: b'%Warning-WIDTH: data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v:138: Operator COND expects 33 bits on the Conditional False, but Conditional False\'s VARREF \'B\' generates 32 bits.\n                                                                                             : ... In instance ALU.Shift.Sra\nassign sra_1 = A[0]? ({1\'h1, B} >> 1\'d1): B;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v:138: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 33 bits.\n                                                                                             : ... In instance ALU.Shift.Sra\nassign sra_1 = A[0]? ({1\'h1, B} >> 1\'d1): B;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v:139: Operator COND expects 34 bits on the Conditional False, but Conditional False\'s VARREF \'sra_1\' generates 32 bits.\n                                                                                             : ... In instance ALU.Shift.Sra\nassign sra_2 = A[1]? ({2\'h3, sra_1} >> 2\'d2): sra_1;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v:139: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 34 bits.\n                                                                                             : ... In instance ALU.Shift.Sra\nassign sra_2 = A[1]? ({2\'h3, sra_1} >> 2\'d2): sra_1;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v:140: Operator COND expects 36 bits on the Conditional False, but Conditional False\'s VARREF \'sra_2\' generates 32 bits.\n                                                                                             : ... In instance ALU.Shift.Sra\nassign sra_4 = A[2]? ({4\'hf, sra_2} >> 3\'d4): sra_2;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v:140: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 36 bits.\n                                                                                             : ... In instance ALU.Shift.Sra\nassign sra_4 = A[2]? ({4\'hf, sra_2} >> 3\'d4): sra_2;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v:141: Operator COND expects 40 bits on the Conditional False, but Conditional False\'s VARREF \'sra_4\' generates 32 bits.\n                                                                                             : ... In instance ALU.Shift.Sra\nassign sra_8 = A[3]? ({8\'hff, sra_4} >> 4\'d8): sra_4;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v:141: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 40 bits.\n                                                                                             : ... In instance ALU.Shift.Sra\nassign sra_8 = A[3]? ({8\'hff, sra_4} >> 4\'d8): sra_4;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v:142: Operator COND expects 48 bits on the Conditional False, but Conditional False\'s VARREF \'sra_8\' generates 32 bits.\n                                                                                             : ... In instance ALU.Shift.Sra\nassign S = A[4]? ({16\'hffff, sra_8} >> 5\'d16): sra_8;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v:142: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 48 bits.\n                                                                                             : ... In instance ALU.Shift.Sra\nassign S = A[4]? ({16\'hffff, sra_8} >> 5\'d16): sra_8;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/124803629/src/ALU/ALU_satisfied_requirements.v:9: Output port connection \'S\' expects 33 bits on the pin connection, but pin connection\'s VARREF \'S0\' generates 32 bits.\n                                                                                           : ... In instance ALU\nAddSub AddSub(.A(A), .B(B), .ALUFun(ALUFun), .Sign(Sign), .Z(zero), .N(neg), .S(S0));\n                                                                              ^\n%Error: Exiting due to 11 warning(s)\n'
module ALU(A, B, ALUFun, Sign, Z);
input Sign;
input [5:0] ALUFun;
input [31:0] A, B;
output [31:0] Z;
wire zero,neg;
wire [31:0] S0, S1, S2, S3;
  
AddSub AddSub(.A(A), .B(B), .ALUFun(ALUFun), .Sign(Sign), .Z(zero), .N(neg), .S(S0));
Cmp Cmp(.ALUFun(ALUFun), .Sign(Sign), .Z(zero), .N(neg), .S(S1));
Logic Logic(.A(A), .B(B), .ALUFun(ALUFun), .S(S2));
Shift Shift(.A(A), .B(B), .ALUFun(ALUFun), .S(S3));

assign Z =
(ALUFun[5:4] == 2'b00)? S0:
(ALUFun[5:4] == 2'b10)? S3:
(ALUFun[5:4] == 2'b01)? S2: S1;

endmodule
module ALU(A, B, ALUFun, Sign, Z);

input Sign;
input [5:0] ALUFun;
input [31:0] A, B;
output [31:0] Z;
wire zero,neg;
wire [31:0] S0, S1, S2, S3;
  
AddSub AddSub(.A(A), .B(B), .ALUFun(ALUFun), .Sign(Sign), .Z(zero), .N(neg), .S(S0));
Cmp Cmp(.ALUFun(ALUFun), .Sign(Sign), .Z(zero), .N(neg), .S(S1));
Logic Logic(.A(A), .B(B), .ALUFun(ALUFun), .S(S2));
Shift Shift(.A(A), .B(B), .ALUFun(ALUFun), .S(S3));

assign Z =
(ALUFun[5:4] == 2'b00)? S0:
(ALUFun[5:4] == 2'b10)? S3:
(ALUFun[5:4] == 2'b01)? S2: S1;

endmodule