data/full_repos/permissive/105729015/Prime_finder_32_bit.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:74: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:82: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:90: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:106: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:112: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:120: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:128: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:138: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:144: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:150: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:155: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:170: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:194: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:197: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:200: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:211: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:214: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:222: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:225: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:227: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:231: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:234: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:236: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:238: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:240: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:245: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:247: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:258: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:265: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:272: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:278: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:290: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:292: Unsupported: Ignoring delay on this delayed statement.\n   #3;\n   ^\n%Warning-IMPLICIT: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:201: Signal definition not found, creating implicitly: \'rem0\'\n                                                                                 : ... Suggested alternative: \'rem00\'\n    $display("Num: %d, Den: %d, Done: %d, Rem0: %d", numerator, denominator, done, rem0);\n                                                                                   ^~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:34: Cannot find file containing module: \'edge_detector_rising\'\n edge_detector_rising edge_detector_rising1(.clk(clk), .input_signal(input_signal), .rising_transition(rising_transition));\n ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/edge_detector_rising\n             data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/edge_detector_rising.v\n             data/full_repos/permissive/105729015,data/full_repos/permissive/105729015/edge_detector_rising.sv\n             edge_detector_rising\n             edge_detector_rising.v\n             edge_detector_rising.sv\n             obj_dir/edge_detector_rising\n             obj_dir/edge_detector_rising.v\n             obj_dir/edge_detector_rising.sv\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:35: Cannot find file containing module: \'edge_detector_falling\'\n edge_detector_falling edge_detector_falling1(.clk(clk), .input_signal(input_signal), .falling_transition(falling_transition));\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:36: Cannot find file containing module: \'number_generator\'\n number_generator gen1(.clk(clk), .rst(rst), .sample(sample), .debug(debug), .value(value));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:37: Cannot find file containing module: \'remainder_test\'\n remainder_test remainder1 (.clk(clk), .rst(rst), .numerator(numerator), .denominator(denominator), .done(done), .rem0(rem0));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:40: Cannot find file containing module: \'prime_tester\'\n prime_tester prime0(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[0]), .is_prime(is_prime[0]), .count(count_0), .start_val(32\'d2), .end_val((dividend >> 2)), .rem0(rem00));  \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:41: Cannot find file containing module: \'prime_tester\'\n prime_tester prime1(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[1]), .is_prime(is_prime[1]), .count(count_1), .start_val((dividend >> 2)), .end_val((dividend >> 1)), .rem0(rem01));  \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:42: Cannot find file containing module: \'prime_tester\'\n prime_tester prime2(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[2]), .is_prime(is_prime[2]), .count(count_2), .start_val((dividend >> 1)), .end_val((dividend >> 1) + (dividend >> 2)), .rem0(rem02));  \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:43: Cannot find file containing module: \'prime_tester\'\n prime_tester prime3(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[3]), .is_prime(is_prime[3]), .count(count_3), .start_val((dividend >> 1) + (dividend >> 2)), .end_val((dividend >> 1) + 1\'b1), .rem0(rem03));  \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:52: Cannot find file containing module: \'serializer\'\n serializer ser1(.clk(clk), .rst(rst), .save(save), .data_in(data_in), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:57: Cannot find file containing module: \'output_ram\'\n output_ram ram1(.clk(clk), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr), .read_addr(read_addr), .read_data(read_data));\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:248: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'inc\' generates 32 bits.\n                                                                              : ... In instance lab7_tb\n   inc = inc + 64\'b1;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/105729015/Prime_finder_32_bit.v:248: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s ADD generates 64 bits.\n                                                                              : ... In instance lab7_tb\n   inc = inc + 64\'b1;\n       ^\n%Error: Exiting due to 10 error(s), 45 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lab7_tb();
	

	reg clk, rst;
	reg input_signal;
	reg sample;
	reg [1:0] debug;
	reg [31:0] numerator, denominator;
	

	wire rising_transition, falling_transition;
	wire [31:0] value;
	wire done;
	wire [31:0] remainder;

	
	integer i, j;
	reg [31:0] inc;
	
	reg [31:0] dividend;
	reg start;
	wire [3:0] done_prime, is_prime;
	wire [32:0] count_0, count_1, count_2, count_3;
	wire prime_falling_transition;
	wire [31:0] remainder_prime;
	wire [23:0] remainder_prime_done;
	reg run;
	wire [23:0] rem00, rem01, rem02, rem03;
	
	edge_detector_rising edge_detector_rising1(.clk(clk), .input_signal(input_signal), .rising_transition(rising_transition));
	edge_detector_falling edge_detector_falling1(.clk(clk), .input_signal(input_signal), .falling_transition(falling_transition));
	number_generator gen1(.clk(clk), .rst(rst), .sample(sample), .debug(debug), .value(value));
	remainder_test remainder1 (.clk(clk), .rst(rst), .numerator(numerator), .denominator(denominator), .done(done), .rem0(rem0));
	

	prime_tester prime0(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[0]), .is_prime(is_prime[0]), .count(count_0), .start_val(32'd2), .end_val((dividend >> 2)), .rem0(rem00));
	prime_tester prime1(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[1]), .is_prime(is_prime[1]), .count(count_1), .start_val((dividend >> 2)), .end_val((dividend >> 1)), .rem0(rem01));
	prime_tester prime2(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[2]), .is_prime(is_prime[2]), .count(count_2), .start_val((dividend >> 1)), .end_val((dividend >> 1) + (dividend >> 2)), .rem0(rem02));
	prime_tester prime3(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[3]), .is_prime(is_prime[3]), .count(count_3), .start_val((dividend >> 1) + (dividend >> 2)), .end_val((dividend >> 1) + 1'b1), .rem0(rem03));
	

	reg save;
	reg [31:0] data_in;
	wire [7:0] write_data;
	wire write_enable;
	wire [1:0] write_addr;
	
	serializer ser1(.clk(clk), .rst(rst), .save(save), .data_in(data_in), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr));
	

	reg [1:0] read_addr;
	wire [7:0] read_data;
	output_ram ram1(.clk(clk), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr), .read_addr(read_addr), .read_data(read_data));
	
	initial begin
		
		#3;
		

		$display("Test Edge Detector");
		input_signal = 1'b0;
		clk = 1'b0;
		
		#3;
		
		$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
		
		repeat(5) begin
			clk = ~clk;
			#3;
			$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
		end
		
		input_signal = 1'b1;
		
		repeat(5) begin
			clk = ~clk;
			#3;
			$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
		end
		
		input_signal = 1'b0;
		
		repeat(5) begin
			clk = ~clk;
			#3;
			$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
		end
		

		$display("Random Number Generator");
		#1;
		debug = 2'b00;
		clk = 1'b0;
		rst = 1'b1;
		run = 1'b1;
		#3;
		
		rst = 1'b0;
		
		repeat(20) begin
			#1;
			clk = ~clk;
		end
		
		debug = 2'b01;
		repeat(20) begin
			#1;
			clk = ~clk;
		end
		#1;
		$display("Debug: %b, value: %d", debug, value);
		
		debug = 2'b10;
		repeat(20) begin
			#1;
			clk = ~clk;
		end
		#1;
		$display("Debug: %b, value: %d", debug, value);
		
		debug = 2'b11;
		repeat(20) begin
			#1;
			clk = ~clk;
		end
		#1;
		$display("Debug: %b, value: %d", debug, value);
		
		debug = 2'b00;
		sample = 1'b1;

		repeat(2000) begin
			#1;
			clk = ~clk;
		end
		
		sample = 1'b0;
		repeat(4000) begin
			#1;
			clk = ~clk;
		end
		
		sample = 1'b1;
		repeat(6000) begin
			#1;
			clk = ~clk;
		end
		
		
		#1;
		$display("Debug: %b, value: %d", debug, value);
		

		$display("Remainder Test");
		numerator = 5;
		denominator = 6;
		clk = 1'b0;
		rst = 1'b0;
		#1;
		rst = 1'b1;
		

		
		repeat(2) begin
			#1;
			clk = ~clk;
			$display("Num: %d, Den: %d, Rem: %d, Done: %d", numerator, denominator, remainder, done);
		end
		rst = 1'b0;
		#1;
		
		for (i = 1; i < 10; i = i + 1) begin
			for (j = 1; j < 10; j = j + 1) begin

				numerator = i;
				denominator = j;
				#1;
			
				while (done == 1'b0) begin
					#1;
					clk = ~clk;
				end
				#1;
				$display("Num: %d, Den: %d, Done: %d, Rem0: %d", numerator, denominator, done, rem0);
			end
		end
		
		

		$display("Test Prime Number");
		
			clk = 1'b0;
			rst = 1'b0;
			#3;
			clk = 1'b1;
			rst = 1'b1;
			#3;
			rst = 1'b0;
		
		inc = 32'd2;
		repeat (100) begin
			
			clk = 1'b0;
			rst = 1'b0;
			#3;
			clk = 1'b1;
			rst = 1'b1;
			#3;
			rst = 1'b0;
			#3;
			
			start = 1'b1;
			repeat(3) begin
				#3;
				clk = ~clk;
			end
			#3;
			start = 1'b0;
			#3;
			dividend = inc;
			#3;
			while (done_prime != 4'b1111) begin
				#3;
				clk = ~clk;
				

			end
			#3;
			$display("inc: %d, isPrime: %b, done: %b", inc, &is_prime, done_prime);
			#3;
			inc = inc + 64'b1;
		end
		
		$display("Test Serializer, Output RAM");

		clk = 1'b0;
		save = 1'b0;
		rst = 1'b0;
		data_in = 32'b11111111111111101111110011111000;
		repeat(6) begin
			#3;
			clk = ~clk;
		end
		
		rst = 1'b1;
		
		repeat(6) begin
				#3;
				clk = ~clk;
		end
		
		rst = 1'b0;
		
		repeat(6) begin
			#3;
			clk = ~clk;
		end
		
		save = 1'b1;
		repeat(20) begin
			#3;
			clk = ~clk;
			if (clk == 1'b1) begin
				$display("write_data: %b, write_enable: %b, write_addr: %b", write_data, write_enable, write_addr);
				
			end
			
		end
		
		$display("Test Output RAM");
		read_addr = 2'b00;
		repeat(4) begin
			#3;
			clk = ~clk;
			#3;
			$display("read_addr: %b, read_data: %b", read_addr, read_data);
			read_addr = read_addr + 1'b1;
		end
		
	end
	
endmodule
module lab7_tb();

	

	reg clk, rst;
	reg input_signal;
	reg sample;
	reg [1:0] debug;
	reg [31:0] numerator, denominator;
	

	wire rising_transition, falling_transition;
	wire [31:0] value;
	wire done;
	wire [31:0] remainder;

	
	integer i, j;
	reg [31:0] inc;
	
	reg [31:0] dividend;
	reg start;
	wire [3:0] done_prime, is_prime;
	wire [32:0] count_0, count_1, count_2, count_3;
	wire prime_falling_transition;
	wire [31:0] remainder_prime;
	wire [23:0] remainder_prime_done;
	reg run;
	wire [23:0] rem00, rem01, rem02, rem03;
	
	edge_detector_rising edge_detector_rising1(.clk(clk), .input_signal(input_signal), .rising_transition(rising_transition));
	edge_detector_falling edge_detector_falling1(.clk(clk), .input_signal(input_signal), .falling_transition(falling_transition));
	number_generator gen1(.clk(clk), .rst(rst), .sample(sample), .debug(debug), .value(value));
	remainder_test remainder1 (.clk(clk), .rst(rst), .numerator(numerator), .denominator(denominator), .done(done), .rem0(rem0));
	

	prime_tester prime0(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[0]), .is_prime(is_prime[0]), .count(count_0), .start_val(32'd2), .end_val((dividend >> 2)), .rem0(rem00));
	prime_tester prime1(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[1]), .is_prime(is_prime[1]), .count(count_1), .start_val((dividend >> 2)), .end_val((dividend >> 1)), .rem0(rem01));
	prime_tester prime2(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[2]), .is_prime(is_prime[2]), .count(count_2), .start_val((dividend >> 1)), .end_val((dividend >> 1) + (dividend >> 2)), .rem0(rem02));
	prime_tester prime3(.clk(clk), .rst(rst), .dividend(dividend), .start(start), .done(done_prime[3]), .is_prime(is_prime[3]), .count(count_3), .start_val((dividend >> 1) + (dividend >> 2)), .end_val((dividend >> 1) + 1'b1), .rem0(rem03));
	

	reg save;
	reg [31:0] data_in;
	wire [7:0] write_data;
	wire write_enable;
	wire [1:0] write_addr;
	
	serializer ser1(.clk(clk), .rst(rst), .save(save), .data_in(data_in), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr));
	

	reg [1:0] read_addr;
	wire [7:0] read_data;
	output_ram ram1(.clk(clk), .write_data(write_data), .write_enable(write_enable), .write_addr(write_addr), .read_addr(read_addr), .read_data(read_data));
	
	initial begin
		
		#3;
		

		$display("Test Edge Detector");
		input_signal = 1'b0;
		clk = 1'b0;
		
		#3;
		
		$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
		
		repeat(5) begin
			clk = ~clk;
			#3;
			$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
		end
		
		input_signal = 1'b1;
		
		repeat(5) begin
			clk = ~clk;
			#3;
			$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
		end
		
		input_signal = 1'b0;
		
		repeat(5) begin
			clk = ~clk;
			#3;
			$display("clk: %b, input_signal: %b, rising_transition: %b, falling_transition: %b", clk, input_signal, rising_transition, falling_transition);
		end
		

		$display("Random Number Generator");
		#1;
		debug = 2'b00;
		clk = 1'b0;
		rst = 1'b1;
		run = 1'b1;
		#3;
		
		rst = 1'b0;
		
		repeat(20) begin
			#1;
			clk = ~clk;
		end
		
		debug = 2'b01;
		repeat(20) begin
			#1;
			clk = ~clk;
		end
		#1;
		$display("Debug: %b, value: %d", debug, value);
		
		debug = 2'b10;
		repeat(20) begin
			#1;
			clk = ~clk;
		end
		#1;
		$display("Debug: %b, value: %d", debug, value);
		
		debug = 2'b11;
		repeat(20) begin
			#1;
			clk = ~clk;
		end
		#1;
		$display("Debug: %b, value: %d", debug, value);
		
		debug = 2'b00;
		sample = 1'b1;

		repeat(2000) begin
			#1;
			clk = ~clk;
		end
		
		sample = 1'b0;
		repeat(4000) begin
			#1;
			clk = ~clk;
		end
		
		sample = 1'b1;
		repeat(6000) begin
			#1;
			clk = ~clk;
		end
		
		
		#1;
		$display("Debug: %b, value: %d", debug, value);
		

		$display("Remainder Test");
		numerator = 5;
		denominator = 6;
		clk = 1'b0;
		rst = 1'b0;
		#1;
		rst = 1'b1;
		

		
		repeat(2) begin
			#1;
			clk = ~clk;
			$display("Num: %d, Den: %d, Rem: %d, Done: %d", numerator, denominator, remainder, done);
		end
		rst = 1'b0;
		#1;
		
		for (i = 1; i < 10; i = i + 1) begin
			for (j = 1; j < 10; j = j + 1) begin

				numerator = i;
				denominator = j;
				#1;
			
				while (done == 1'b0) begin
					#1;
					clk = ~clk;
				end
				#1;
				$display("Num: %d, Den: %d, Done: %d, Rem0: %d", numerator, denominator, done, rem0);
			end
		end
		
		

		$display("Test Prime Number");
		
			clk = 1'b0;
			rst = 1'b0;
			#3;
			clk = 1'b1;
			rst = 1'b1;
			#3;
			rst = 1'b0;
		
		inc = 32'd2;
		repeat (100) begin
			
			clk = 1'b0;
			rst = 1'b0;
			#3;
			clk = 1'b1;
			rst = 1'b1;
			#3;
			rst = 1'b0;
			#3;
			
			start = 1'b1;
			repeat(3) begin
				#3;
				clk = ~clk;
			end
			#3;
			start = 1'b0;
			#3;
			dividend = inc;
			#3;
			while (done_prime != 4'b1111) begin
				#3;
				clk = ~clk;
				

			end
			#3;
			$display("inc: %d, isPrime: %b, done: %b", inc, &is_prime, done_prime);
			#3;
			inc = inc + 64'b1;
		end
		
		$display("Test Serializer, Output RAM");

		clk = 1'b0;
		save = 1'b0;
		rst = 1'b0;
		data_in = 32'b11111111111111101111110011111000;
		repeat(6) begin
			#3;
			clk = ~clk;
		end
		
		rst = 1'b1;
		
		repeat(6) begin
				#3;
				clk = ~clk;
		end
		
		rst = 1'b0;
		
		repeat(6) begin
			#3;
			clk = ~clk;
		end
		
		save = 1'b1;
		repeat(20) begin
			#3;
			clk = ~clk;
			if (clk == 1'b1) begin
				$display("write_data: %b, write_enable: %b, write_addr: %b", write_data, write_enable, write_addr);
				
			end
			
		end
		
		$display("Test Output RAM");
		read_addr = 2'b00;
		repeat(4) begin
			#3;
			clk = ~clk;
			#3;
			$display("read_addr: %b, read_data: %b", read_addr, read_data);
			read_addr = read_addr + 1'b1;
		end
		
	end
	
endmodule