data/full_repos/permissive/126216465/aes_keygen_sub.v
1: b'%Error: data/full_repos/permissive/126216465/aes_keygen_sub.v:32: Cannot find file containing module: \'aes_sbox\'\naes_sbox sbox(.sboxw1(xin2[31:0]), .new_sboxw1(sbox_result),\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/126216465,data/full_repos/permissive/126216465/aes_sbox\n             data/full_repos/permissive/126216465,data/full_repos/permissive/126216465/aes_sbox.v\n             data/full_repos/permissive/126216465,data/full_repos/permissive/126216465/aes_sbox.sv\n             aes_sbox\n             aes_sbox.v\n             aes_sbox.sv\n             obj_dir/aes_sbox\n             obj_dir/aes_sbox.v\n             obj_dir/aes_sbox.sv\n%Warning-WIDTH: data/full_repos/permissive/126216465/aes_keygen_sub.v:35: Operator XOR expects 8 bits on the RHS, but RHS\'s VARREF \'rcon\' generates 4 bits.\n                                                                        : ... In instance aes_genkey_sub\nassign rot_result = {sbox_result[23:16] ^ rcon, sbox_result[15:8], sbox_result[7:0], sbox_result[31:24]};    \n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module aes_genkey_sub(input clk, input [3:0] rcon, input [127:0] xin0, input [127:0] xin2, output [127:0] xout0, output [127:0] xout2);

wire [31:0] sbox_result;
wire [31:0] sbox_result2;
wire [31:0] rot_result;
wire [127:0] temp;

aes_sbox sbox(.sboxw1(xin2[31:0]), .new_sboxw1(sbox_result),
              .sboxw2(temp[31:0] ^ rot_result), .new_sboxw2(sbox_result2));

assign rot_result = {sbox_result[23:16] ^ rcon, sbox_result[15:8], sbox_result[7:0], sbox_result[31:24]};

assign temp = {xin0[127:96], xin0[127:96] ^ xin0[95:64], 
              xin0[127:96] ^ xin0[95:64] ^ xin0[63:32],
              xin0[127:96] ^ xin0[95:64] ^ xin0[63:32] ^ xin0[31:0]};
assign xout0 = temp ^ {rot_result,rot_result,rot_result,rot_result};




assign xout2 = {xin2[127:96] ^ sbox_result2, xin2[127:96] ^ xin2[95:64] ^ sbox_result2, 
              xin2[127:96] ^ xin2[95:64] ^ xin2[63:32] ^ sbox_result2,
              xin2[127:96] ^ xin2[95:64] ^ xin2[63:32] ^ xin2[31:0] ^ sbox_result2};

endmodule
module aes_genkey_sub(input clk, input [3:0] rcon, input [127:0] xin0, input [127:0] xin2, output [127:0] xout0, output [127:0] xout2);


wire [31:0] sbox_result;
wire [31:0] sbox_result2;
wire [31:0] rot_result;
wire [127:0] temp;

aes_sbox sbox(.sboxw1(xin2[31:0]), .new_sboxw1(sbox_result),
              .sboxw2(temp[31:0] ^ rot_result), .new_sboxw2(sbox_result2));

assign rot_result = {sbox_result[23:16] ^ rcon, sbox_result[15:8], sbox_result[7:0], sbox_result[31:24]};

assign temp = {xin0[127:96], xin0[127:96] ^ xin0[95:64], 
              xin0[127:96] ^ xin0[95:64] ^ xin0[63:32],
              xin0[127:96] ^ xin0[95:64] ^ xin0[63:32] ^ xin0[31:0]};
assign xout0 = temp ^ {rot_result,rot_result,rot_result,rot_result};




assign xout2 = {xin2[127:96] ^ sbox_result2, xin2[127:96] ^ xin2[95:64] ^ sbox_result2, 
              xin2[127:96] ^ xin2[95:64] ^ xin2[63:32] ^ sbox_result2,
              xin2[127:96] ^ xin2[95:64] ^ xin2[63:32] ^ xin2[31:0] ^ sbox_result2};

endmodule