data/full_repos/permissive/173003307/sim/u_proc_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173003307/sim/u_proc_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #5 CLK <= ~CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173003307/sim/u_proc_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #10 RESET = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173003307/sim/u_proc_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10 RESET = 1\'b0;\n        ^\n%Error: data/full_repos/permissive/173003307/sim/u_proc_tb.v:33: Cannot find file containing module: \'processor_wrapper\'\n    processor_wrapper ut(\n    ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173003307/sim,data/full_repos/permissive/173003307/processor_wrapper\n             data/full_repos/permissive/173003307/sim,data/full_repos/permissive/173003307/processor_wrapper.v\n             data/full_repos/permissive/173003307/sim,data/full_repos/permissive/173003307/processor_wrapper.sv\n             processor_wrapper\n             processor_wrapper.v\n             processor_wrapper.sv\n             obj_dir/processor_wrapper\n             obj_dir/processor_wrapper.v\n             obj_dir/processor_wrapper.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module u_proc_tb(

    );
    
    reg CLK;
    reg RESET;
    wire VGA_VS;
    wire VGA_HS;
    wire [7:0] VGA_COLOUR;
    
    processor_wrapper ut(
                        .CLK(CLK),
                        .RESET(RESET),
                        .VGA_COLOUR(VGA_COLOUR),
                        .VGA_HS(VGA_HS),
                        .VGA_VS(VGA_VS)
        );
    
    
    initial
        CLK = 1'b0;
        
    always
        #5 CLK <= ~CLK;
        
        
    initial begin
        RESET = 1'b0;
        #10 RESET = 1'b1;
        #10 RESET = 1'b0;
    end
    
endmodule
module u_proc_tb(

    );

    
    reg CLK;
    reg RESET;
    wire VGA_VS;
    wire VGA_HS;
    wire [7:0] VGA_COLOUR;
    
    processor_wrapper ut(
                        .CLK(CLK),
                        .RESET(RESET),
                        .VGA_COLOUR(VGA_COLOUR),
                        .VGA_HS(VGA_HS),
                        .VGA_VS(VGA_VS)
        );
    
    
    initial
        CLK = 1'b0;
        
    always
        #5 CLK <= ~CLK;
        
        
    initial begin
        RESET = 1'b0;
        #10 RESET = 1'b1;
        #10 RESET = 1'b0;
    end
    
endmodule