data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ahb_master.v
1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ahb_master.v:12: Cannot find include file: ahb_lite.vh\n`include "ahb_lite.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.v\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.sv\n             ahb_lite.vh\n             ahb_lite.vh.v\n             ahb_lite.vh.sv\n             obj_dir/ahb_lite.vh\n             obj_dir/ahb_lite.vh.v\n             obj_dir/ahb_lite.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ahb_master.v:39: Define or directive not defined: \'`HTRANS_NONSEQ\'\n    assign HTRANS   = valid ? `HTRANS_NONSEQ : `HTRANS_IDLE;  \n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ahb_master.v:39: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign HTRANS   = valid ? `HTRANS_NONSEQ : `HTRANS_IDLE;  \n                                             ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ahb_master.v:39: Define or directive not defined: \'`HTRANS_IDLE\'\n    assign HTRANS   = valid ? `HTRANS_NONSEQ : `HTRANS_IDLE;  \n                                               ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module sm_ahb_master
(
    input             clk,
    input             rst_n,

    input      [31:0] a,
    input             we,
    input      [31:0] wd,
    input             valid,
    output            ready,
    output     [31:0] rd,

    output            HCLK,
    output            HRESETn,
    output            HWRITE,
    output     [ 1:0] HTRANS,
    output     [31:0] HADDR,
    input      [31:0] HRDATA,
    output     [31:0] HWDATA,
    input             HREADY,
    input             HRESP          
);
    assign HCLK     = clk;
    assign HRESETn  = rst_n;
    assign HWRITE   = we;
    assign HTRANS   = valid ? `HTRANS_NONSEQ : `HTRANS_IDLE;
    assign HADDR    = a;

    wire ahbReady = HREADY & ~HRESP;
    wire memStart =  valid;
    wire memEnd   = ~valid & ahbReady;


    wire memWait;
    wire memWait_next = memStart ? 1 :
                        memEnd   ? 0 : memWait;
    sm_register_c r_memWait(clk, rst_n, memWait_next, memWait);


    assign ready    = memWait ? ahbReady : 1'b1; 
    assign rd       = HRDATA;

    sm_register_we #(32) r_hwdata (clk, rst_n, valid, wd, HWDATA);
endmodule
module sm_ahb_master
(
    input             clk,
    input             rst_n,

    input      [31:0] a,
    input             we,
    input      [31:0] wd,
    input             valid,
    output            ready,
    output     [31:0] rd,

    output            HCLK,
    output            HRESETn,
    output            HWRITE,
    output     [ 1:0] HTRANS,
    output     [31:0] HADDR,
    input      [31:0] HRDATA,
    output     [31:0] HWDATA,
    input             HREADY,
    input             HRESP          
);

    assign HCLK     = clk;
    assign HRESETn  = rst_n;
    assign HWRITE   = we;
    assign HTRANS   = valid ? `HTRANS_NONSEQ : `HTRANS_IDLE;
    assign HADDR    = a;

    wire ahbReady = HREADY & ~HRESP;
    wire memStart =  valid;
    wire memEnd   = ~valid & ahbReady;


    wire memWait;
    wire memWait_next = memStart ? 1 :
                        memEnd   ? 0 : memWait;
    sm_register_c r_memWait(clk, rst_n, memWait_next, memWait);


    assign ready    = memWait ? ahbReady : 1'b1; 
    assign rd       = HRDATA;

    sm_register_we #(32) r_hwdata (clk, rst_n, valid, wd, HWDATA);
endmodule