data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v
 line:60: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #20;                   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #300 $finish;\n  ^\n%Error: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:65: Unsupported or unknown PLI call: $monitor\n       $monitor("data_in=%b addr=%b we=%b clk=%b data_out=%b addr_out=%b", \n       ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_07/src/lab7_1/simulation/testbench.v:70: Unsupported or unknown PLI call: $dumpvars\n       $dumpvars;   \n       ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;


	reg [5:0] data_in;
	reg [3:0] addr;
	reg we;
	reg clk;
	wire [5:0] data_out;
	wire [3:0] addr_out;




    lab7_1 dut (data_in, addr, we, clk, data_out, addr_out);
	
initial 
	begin

		clk = 0;
		we = 1;
		addr = 4'b0000;
		data_in = 6'b000000; 
		

		#20;
			we = 0;
		#20;
			addr = 4'b0001; data_in = 6'b000001;
		#20;
			addr = 4'b0010; data_in = 6'b000010;
		#20;
			addr = 4'b0011; data_in = 6'b000011;
		#20;
			addr = 4'b0100; data_in = 6'b000100;
		#20;
			addr = 4'b0101; data_in = 6'b000101;

		#20;
			we = 1;
		#20;
			addr = 4'b0000;
		#20;
			addr = 4'b0010;
		#20;
			addr = 4'b0011;
		#20;
			addr = 4'b0100;
		#20;
			addr = 4'b0101;
	end
	

	always #10 clk = ~clk;
	
	initial 
		#300 $finish;
	


   initial 
       $monitor("data_in=%b addr=%b we=%b clk=%b data_out=%b addr_out=%b", 
			data_in, addr, we, clk, data_out, addr_out);


   initial 
       $dumpvars;

endmodule
module testbench;



	reg [5:0] data_in;
	reg [3:0] addr;
	reg we;
	reg clk;
	wire [5:0] data_out;
	wire [3:0] addr_out;




    lab7_1 dut (data_in, addr, we, clk, data_out, addr_out);
	
initial 
	begin

		clk = 0;
		we = 1;
		addr = 4'b0000;
		data_in = 6'b000000; 
		

		#20;
			we = 0;
		#20;
			addr = 4'b0001; data_in = 6'b000001;
		#20;
			addr = 4'b0010; data_in = 6'b000010;
		#20;
			addr = 4'b0011; data_in = 6'b000011;
		#20;
			addr = 4'b0100; data_in = 6'b000100;
		#20;
			addr = 4'b0101; data_in = 6'b000101;

		#20;
			we = 1;
		#20;
			addr = 4'b0000;
		#20;
			addr = 4'b0010;
		#20;
			addr = 4'b0011;
		#20;
			addr = 4'b0100;
		#20;
			addr = 4'b0101;
	end
	

	always #10 clk = ~clk;
	
	initial 
		#300 $finish;
	


   initial 
       $monitor("data_in=%b addr=%b we=%b clk=%b data_out=%b addr_out=%b", 
			data_in, addr, we, clk, data_out, addr_out);


   initial 
       $dumpvars;

endmodule