data/full_repos/permissive/111021593/ClockDivider.v
data/verilator_xmls/d67c762c-d7be-46f3-b7f7-51a087184909.xml
module ClockDivider (clk, reset, newClock);

input wire clk, reset;
output reg newClock;

reg counterClock;

always @ (posedge clk or posedge reset) begin
	if (reset == 1'b1)
	begin
		newClock <= 1'b0;
		counterClock <= 1'b0;
	end
	else begin
		counterClock <= counterClock + 1'b1;
		if (counterClock == 1'b0)
		begin
			newClock <= ~newClock;
		end
	end
end

endmodule
module ClockDivider (clk, reset, newClock);


input wire clk, reset;
output reg newClock;

reg counterClock;

always @ (posedge clk or posedge reset) begin
	if (reset == 1'b1)
	begin
		newClock <= 1'b0;
		counterClock <= 1'b0;
	end
	else begin
		counterClock <= counterClock + 1'b1;
		if (counterClock == 1'b0)
		begin
			newClock <= ~newClock;
		end
	end
end

endmodule