data/full_repos/permissive/148324174/CombLogic/alu_tb.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/alu_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #100 a = {$random}%256;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/alu_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #100 $finish;\n ^\n%Error: data/full_repos/permissive/148324174/CombLogic/alu_tb.v:11: Cannot find file containing module: \'alu\'\nalu U1(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/148324174/CombLogic,data/full_repos/permissive/148324174/alu\n             data/full_repos/permissive/148324174/CombLogic,data/full_repos/permissive/148324174/alu.v\n             data/full_repos/permissive/148324174/CombLogic,data/full_repos/permissive/148324174/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Warning-WIDTH: data/full_repos/permissive/148324174/CombLogic/alu_tb.v:19: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                          : ... In instance alu_tb\n a = {$random}%256;\n   ^\n%Warning-WIDTH: data/full_repos/permissive/148324174/CombLogic/alu_tb.v:20: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                          : ... In instance alu_tb\n b = {$random}%256;\n   ^\n%Warning-WIDTH: data/full_repos/permissive/148324174/CombLogic/alu_tb.v:24: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                          : ... In instance alu_tb\n  #100 a = {$random}%256;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/148324174/CombLogic/alu_tb.v:25: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                          : ... In instance alu_tb\n       b = {$random}%256;\n         ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb;

reg [7:0] a,b;
reg [2:0] opcode;
wire [7:0] out;

localparam times=5;

alu U1(
    .out(out),
    .opcode(opcode),
    .a(a),
    .b(b)
    );

initial begin
	a = {$random}%256;
	b = {$random}%256;

	opcode=3'd0;
	repeat(times) begin
		#100 a = {$random}%256;
		     b = {$random}%256;
		     opcode = opcode+1;
	end
	#100 $finish;
end
endmodule
module alu_tb;


reg [7:0] a,b;
reg [2:0] opcode;
wire [7:0] out;

localparam times=5;

alu U1(
    .out(out),
    .opcode(opcode),
    .a(a),
    .b(b)
    );

initial begin
	a = {$random}%256;
	b = {$random}%256;

	opcode=3'd0;
	repeat(times) begin
		#100 a = {$random}%256;
		     b = {$random}%256;
		     opcode = opcode+1;
	end
	#100 $finish;
end
endmodule