data/full_repos/permissive/198643510/prewish_mentor.v
data/verilator_xmls/bdf6cb7d-1abe-4a3f-b045-d3ac1ad36807.xml
module prewish_mentor(
    input CLK_I,
    input RST_I,
    output STB_O,
    output[7:0] DAT_O,
    input STB_I,
    input[7:0] DAT_I,
    output o_alive
);
    reg[1:0] state = 2'b00;
    reg strobe_reg = 0;
    reg[7:0] dat_reg = 8'b00000000;

    reg alivereg = 0;


    always @(posedge CLK_I) begin
        if(RST_I == 1) begin
            strobe_reg <= 0;
            state <= 2'b00;
        end else begin

            case (state)
                2'b00 : begin


                    strobe_reg <= 0;
                    if(STB_I == 1) begin
                        alivereg <= ~alivereg;
                        dat_reg <= DAT_I;
                        state <= 2'b01;
                    end
                end

                2'b01 : begin

                    if(~STB_I) begin
                        strobe_reg <= 1;
                        state <= 2'b11;
                    end
                end

                2'b11 : begin

                    state <= 2'b00;
                end

                2'b10 : begin

                    strobe_reg <= 0;
                    state <= 2'b00;
                end
            endcase

        end
    end

    assign STB_O = strobe_reg;
    assign DAT_O = dat_reg;

    assign o_alive = ~alivereg;
endmodule
module prewish_mentor(
    input CLK_I,
    input RST_I,
    output STB_O,
    output[7:0] DAT_O,
    input STB_I,
    input[7:0] DAT_I,
    output o_alive
);

    reg[1:0] state = 2'b00;
    reg strobe_reg = 0;
    reg[7:0] dat_reg = 8'b00000000;

    reg alivereg = 0;


    always @(posedge CLK_I) begin
        if(RST_I == 1) begin
            strobe_reg <= 0;
            state <= 2'b00;
        end else begin

            case (state)
                2'b00 : begin


                    strobe_reg <= 0;
                    if(STB_I == 1) begin
                        alivereg <= ~alivereg;
                        dat_reg <= DAT_I;
                        state <= 2'b01;
                    end
                end

                2'b01 : begin

                    if(~STB_I) begin
                        strobe_reg <= 1;
                        state <= 2'b11;
                    end
                end

                2'b11 : begin

                    state <= 2'b00;
                end

                2'b10 : begin

                    strobe_reg <= 0;
                    state <= 2'b00;
                end
            endcase

        end
    end

    assign STB_O = strobe_reg;
    assign DAT_O = dat_reg;

    assign o_alive = ~alivereg;
endmodule