data/full_repos/permissive/143278/fpga_tests/cell_ld_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/cell_ld_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (Q !== 0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/cell_ld_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (Q !== 1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/cell_ld_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (Q !== 1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/cell_ld_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (Q !== 1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/cell_ld_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (Q !== 0) begin\n      ^\n%Error: data/full_repos/permissive/143278/fpga_tests/cell_ld_tb.v:8: Cannot find file containing module: \'LD\'\n   LD u1 (.Q(Q), .D(D), .G(G));\n   ^~\n        ... Looked in:\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/LD\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/LD.v\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/LD.sv\n             LD\n             LD.v\n             LD.sv\n             obj_dir/LD\n             obj_dir/LD.v\n             obj_dir/LD.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire Q;
   reg	D, G;

   LD u1 (.Q(Q), .D(D), .G(G));

   initial begin
      D = 0;
      G = 1;
      #1 if (Q !== 0) begin
	 $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
	 $finish;
      end

      D = 1;
      #1 if (Q !== 1) begin
	 $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
	 $finish;
      end

      G = 0;
      #1 if (Q !== 1) begin
	 $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
	 $finish;
      end

      D = 0;
      #1 if (Q !== 1) begin
	 $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
	 $finish;
      end

      G = 1;
      #1 if (Q !== 0) begin
	 $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   wire Q;
   reg	D, G;

   LD u1 (.Q(Q), .D(D), .G(G));

   initial begin
      D = 0;
      G = 1;
      #1 if (Q !== 0) begin
	 $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
	 $finish;
      end

      D = 1;
      #1 if (Q !== 1) begin
	 $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
	 $finish;
      end

      G = 0;
      #1 if (Q !== 1) begin
	 $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
	 $finish;
      end

      D = 0;
      #1 if (Q !== 1) begin
	 $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
	 $finish;
      end

      G = 1;
      #1 if (Q !== 0) begin
	 $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
	 $finish;
      end

      $display("PASSED");
   end

endmodule