data/full_repos/permissive/136584400/digital_logic_labs/lab03/3/sources/3.v
1: b"%Error: data/full_repos/permissive/136584400/digital_logic_labs/lab03/3/sources/3.v:16: Cannot find file containing module: 'divider'\n  divider divider(.clk(clk), .clk_N(clk_N));\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136584400/digital_logic_labs/lab03/3/sources,data/full_repos/permissive/136584400/divider\n             data/full_repos/permissive/136584400/digital_logic_labs/lab03/3/sources,data/full_repos/permissive/136584400/divider.v\n             data/full_repos/permissive/136584400/digital_logic_labs/lab03/3/sources,data/full_repos/permissive/136584400/divider.sv\n             divider\n             divider.v\n             divider.sv\n             obj_dir/divider\n             obj_dir/divider.v\n             obj_dir/divider.sv\n%Error: Exiting due to 1 error(s)\n"
module pipe3b(sig_nsyn, clk, q1, q2, sig_syn);
  input clk;
  input sig_nsyn;
  output reg q1, q2, sig_syn;
  wire clk_N;

  divider divider(.clk(clk), .clk_N(clk_N));

initial begin
  q1 = 0;
  q2 = 0;
  sig_syn = 0;
end

always@(posedge clk_N) begin
  sig_syn <= q2;
  q2 <= q1;
  q1 <= sig_nsyn;
end

endmodule
module pipe3b(sig_nsyn, clk, q1, q2, sig_syn);

  input clk;
  input sig_nsyn;
  output reg q1, q2, sig_syn;
  wire clk_N;

  divider divider(.clk(clk), .clk_N(clk_N));

initial begin
  q1 = 0;
  q2 = 0;
  sig_syn = 0;
end

always@(posedge clk_N) begin
  sig_syn <= q2;
  q2 <= q1;
  q1 <= sig_nsyn;
end

endmodule