data/full_repos/permissive/167632244/FlappyBird/clkdiv.v
data/verilator_xmls/578443e0-e019-46c3-9871-9d63e6a91149.xml
module clkdiv(
    input clk,
    input rst,
    output reg[31:0] clkdiv
		);
    always @ (posedge clk or posedge rst) begin
      if(rst) clkdiv<=0;
      else clkdiv <= clkdiv +1'b1;
    end
endmodule
module clkdiv(
    input clk,
    input rst,
    output reg[31:0] clkdiv
		);

    always @ (posedge clk or posedge rst) begin
      if(rst) clkdiv<=0;
      else clkdiv <= clkdiv +1'b1;
    end
endmodule