data/full_repos/permissive/201488448/2_circuits/2_sequential/16_bothedge.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/16_bothedge.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'anyedge'\n                                                                                                : ... In instance top_module\n        anyedge <= in&(~d_last) | (~in)&d_last;\n        ^~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg	[7:0]	d_last;
    always@(posedge clk) begin
        d_last <= in;
        anyedge <= in&(~d_last) | (~in)&d_last;
    end
endmodule
module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);

    reg	[7:0]	d_last;
    always@(posedge clk) begin
        d_last <= in;
        anyedge <= in&(~d_last) | (~in)&d_last;
    end
endmodule