data/full_repos/permissive/155656868/tb/cpu_tb.v
 line:39: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/155656868/tb/cpu_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/155656868/tb/cpu_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155656868/tb/cpu_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #500\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155656868/tb/cpu_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/155656868/tb/cpu_tb.v:28: Cannot find file containing module: \'cpu\'\n    cpu TU(.clk(clk),\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/155656868/tb,data/full_repos/permissive/155656868/cpu\n             data/full_repos/permissive/155656868/tb,data/full_repos/permissive/155656868/cpu.v\n             data/full_repos/permissive/155656868/tb,data/full_repos/permissive/155656868/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_tb();

    reg clk, reset;

    cpu TU(.clk(clk),
           .rst(reset));

    initial begin
        clk = 1'b0;
        reset = 1'b0;
        #10
        reset = 1'b1;
        #10
        reset = 1'b0;
        #500
        $finish;
    end

    always #10 clk = ~clk;

endmodule
module cpu_tb();


    reg clk, reset;

    cpu TU(.clk(clk),
           .rst(reset));

    initial begin
        clk = 1'b0;
        reset = 1'b0;
        #10
        reset = 1'b1;
        #10
        reset = 1'b0;
        #500
        $finish;
    end

    always #10 clk = ~clk;

endmodule