data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:63: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n reg [15:0] sequence = 0;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:63: syntax error, unexpected INTEGER NUMBER, expecting new or new-then-paren\n reg [15:0] sequence = 0;\n                       ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:89: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'h0    : sequence <= 16'b0000000011111111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:89: syntax error, unexpected <=\n   4'h0    : sequence <= 16'b0000000011111111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:90: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'h1    : sequence <= 16'b1100111111111111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:90: syntax error, unexpected <=\n   4'h1    : sequence <= 16'b1100111111111111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:91: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'h2    : sequence <= 16'b0001000111100111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:91: syntax error, unexpected <=\n   4'h2    : sequence <= 16'b0001000111100111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:92: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'h3    : sequence <= 16'b0000001111100111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:92: syntax error, unexpected <=\n   4'h3    : sequence <= 16'b0000001111100111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:93: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'h4    : sequence <= 16'b1100111011100111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:93: syntax error, unexpected <=\n   4'h4    : sequence <= 16'b1100111011100111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:94: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'h5    : sequence <= 16'b0010001011100111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:94: syntax error, unexpected <=\n   4'h5    : sequence <= 16'b0010001011100111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:95: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'h6    : sequence <= 16'b0010000011100111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:95: syntax error, unexpected <=\n   4'h6    : sequence <= 16'b0010000011100111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:96: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'h7    : sequence <= 16'b0000111111111111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:96: syntax error, unexpected <=\n   4'h7    : sequence <= 16'b0000111111111111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:97: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'h8    : sequence <= 16'b0000000011100111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:97: syntax error, unexpected <=\n   4'h8    : sequence <= 16'b0000000011100111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:98: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'h9    : sequence <= 16'b0000001011100111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:98: syntax error, unexpected <=\n   4'h9    : sequence <= 16'b0000001011100111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:99: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'ha    : sequence <= 16'b0000110011100111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:99: syntax error, unexpected <=\n   4'ha    : sequence <= 16'b0000110011100111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:100: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'hb    : sequence <= 16'b1110000011100111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:100: syntax error, unexpected <=\n   4'hb    : sequence <= 16'b1110000011100111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:101: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'hc    : sequence <= 16'b0011000011111111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:101: syntax error, unexpected <=\n   4'hc    : sequence <= 16'b0011000011111111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:102: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'hd    : sequence <= 16'b1100000111100111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:102: syntax error, unexpected <=\n   4'hd    : sequence <= 16'b1100000111100111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:103: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   4'he    : sequence <= 16'b0011000011101111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:103: syntax error, unexpected <=\n   4'he    : sequence <= 16'b0011000011101111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:104: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n   default : sequence <= 16'b0011110011101111;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:104: syntax error, unexpected <=\n   default : sequence <= 16'b0011110011101111;\n                      ^~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:128: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n    4'h0    : begin segment_a <= sequence[15]; segment_r <= 1; end  \n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:128: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n    4'h0    : begin segment_a <= sequence[15]; segment_r <= 1; end  \n                                         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:129: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n    4'h1    : begin segment_b <= sequence[14]; segment_a <= 1; end  \n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:129: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n    4'h1    : begin segment_b <= sequence[14]; segment_a <= 1; end  \n                                         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:130: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n    4'h2    : begin segment_c <= sequence[13]; segment_b <= 1; end  \n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:130: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n    4'h2    : begin segment_c <= sequence[13]; segment_b <= 1; end  \n                                         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:131: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n    4'h3    : begin segment_d <= sequence[12]; segment_c <= 1; end  \n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:131: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n    4'h3    : begin segment_d <= sequence[12]; segment_c <= 1; end  \n                                         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:132: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n    4'h4    : begin segment_e <= sequence[11]; segment_d <= 1; end  \n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:132: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n    4'h4    : begin segment_e <= sequence[11]; segment_d <= 1; end  \n                                         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:133: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n    4'h5    : begin segment_f <= sequence[10]; segment_e <= 1; end  \n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:133: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n    4'h5    : begin segment_f <= sequence[10]; segment_e <= 1; end  \n                                         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:134: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n    4'h6    : begin segment_g <= sequence[09]; segment_f <= 1; end  \n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:134: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n    4'h6    : begin segment_g <= sequence[09]; segment_f <= 1; end  \n                                         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:135: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n    4'h7    : begin segment_h <= sequence[08]; segment_g <= 1; end  \n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test004.16-segment-driver.v:135: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\n    4'h7    : begin segment_h <= sequence[08]; segment_g <= 1; end  \n                                         ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n"
module top (
	input CLK,
	output reg LED1 = 0,
	output reg LED2 = 0,
	output reg LED3 = 0,
	output reg LED4 = 0,
	output reg LED5 = 0,
	output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
	output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
	output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10
);
	reg segment_a = 0;
	reg segment_b = 0;
	reg segment_c = 0;
	reg segment_d = 0;
	reg segment_e = 0;
	reg segment_f = 0;
	reg segment_g = 0;
	reg segment_h = 0;
	reg segment_k = 0;
	reg segment_m = 0;
	reg segment_n = 0;
	reg segment_u = 0;
	reg segment_p = 0;
	reg segment_t = 0;
	reg segment_s = 0;
	reg segment_r = 0;
	reg segment_dp = 0;
	assign J2_7  = segment_a;
	assign J2_2  = segment_b;
	assign J2_4  = segment_c;
	assign J1_5  = segment_d;
	assign J3_8  = segment_e;
	assign J3_7  = segment_f;
	assign J3_5  = segment_g;
	assign J3_4  = segment_h;
	assign J3_3  = segment_k;
	assign J2_1  = segment_m;
	assign J2_10 = segment_n;
	assign J1_4  = segment_u;
	assign J1_3  = segment_p;
	assign J3_6  = segment_t;
	assign J1_7  = segment_s;
	assign J1_6  = segment_r;
	assign J1_8  = segment_dp;
	assign J2_9  = 1;
	assign J1_9  = 1;
	assign J2_3  = 1;
	assign J1_10 = 1;
	assign J2_8  = 1;
	assign J3_9  = 1;
	assign J3_10 = 1;
	reg [31:0] raw_counter = 0;
	reg dot_clock = 0;
	reg [3:0] dot_counter = 0;
	reg clock_1Hz = 0;
	reg [3:0] counter_1Hz = 0;
	reg [15:0] sequence = 0;
	reg reset = 0;
	always @(posedge CLK) begin
		if (raw_counter[31:12]==0) begin
			reset <= 1;
			LED1 <= 0;
			LED2 <= 0;
			LED3 <= 0;
			LED4 <= 0;
			LED5 <= 0;
		end else begin
			LED5 <= dot_clock;
			reset <= 0;
		end
		raw_counter++;
	end
	always begin
		dot_clock <= raw_counter[12];
		dot_counter <= raw_counter[16:13];
	end
	always begin
		clock_1Hz <= raw_counter[23];
		counter_1Hz <= raw_counter[27:24];
	end
	always @(posedge clock_1Hz) begin
		case(counter_1Hz[3:0])
			4'h0    : sequence <= 16'b0000000011111111;
			4'h1    : sequence <= 16'b1100111111111111;
			4'h2    : sequence <= 16'b0001000111100111;
			4'h3    : sequence <= 16'b0000001111100111;
			4'h4    : sequence <= 16'b1100111011100111;
			4'h5    : sequence <= 16'b0010001011100111;
			4'h6    : sequence <= 16'b0010000011100111;
			4'h7    : sequence <= 16'b0000111111111111;
			4'h8    : sequence <= 16'b0000000011100111;
			4'h9    : sequence <= 16'b0000001011100111;
			4'ha    : sequence <= 16'b0000110011100111;
			4'hb    : sequence <= 16'b1110000011100111;
			4'hc    : sequence <= 16'b0011000011111111;
			4'hd    : sequence <= 16'b1100000111100111;
			4'he    : sequence <= 16'b0011000011101111;
			default : sequence <= 16'b0011110011101111;
		endcase
	end
	always @(posedge dot_clock) begin
		if (reset==1) begin
			segment_a  <= 1;
			segment_b  <= 1;
			segment_c  <= 1;
			segment_d  <= 1;
			segment_e  <= 1;
			segment_f  <= 1;
			segment_g  <= 1;
			segment_h  <= 1;
			segment_k  <= 1;
			segment_m  <= 1;
			segment_n  <= 1;
			segment_u  <= 1;
			segment_p  <= 1;
			segment_t  <= 1;
			segment_s  <= 1;
			segment_r  <= 1;
			segment_dp <= 1;
		end else begin
			case(dot_counter)
				4'h0    : begin segment_a <= sequence[15]; segment_r <= 1; end
				4'h1    : begin segment_b <= sequence[14]; segment_a <= 1; end
				4'h2    : begin segment_c <= sequence[13]; segment_b <= 1; end
				4'h3    : begin segment_d <= sequence[12]; segment_c <= 1; end
				4'h4    : begin segment_e <= sequence[11]; segment_d <= 1; end
				4'h5    : begin segment_f <= sequence[10]; segment_e <= 1; end
				4'h6    : begin segment_g <= sequence[09]; segment_f <= 1; end
				4'h7    : begin segment_h <= sequence[08]; segment_g <= 1; end
				4'h8    : begin segment_k <= sequence[07]; segment_h <= 1; end
				4'h9    : begin segment_m <= sequence[06]; segment_k <= 1; end
				4'ha    : begin segment_n <= sequence[05]; segment_m <= 1; end
				4'hb    : begin segment_u <= sequence[04]; segment_n <= 1; end
				4'hc    : begin segment_p <= sequence[03]; segment_u <= 1; end
				4'hd    : begin segment_t <= sequence[02]; segment_p <= 1; end
				4'he    : begin segment_s <= sequence[01]; segment_t <= 1; end
				default : begin segment_r <= sequence[00]; segment_s <= 1; end
			endcase
		end
	end
endmodule
module top (
	input CLK,
	output reg LED1 = 0,
	output reg LED2 = 0,
	output reg LED3 = 0,
	output reg LED4 = 0,
	output reg LED5 = 0,
	output J1_3, J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10,
	output J2_1, J2_2, J2_3, J2_4, J2_7, J2_8, J2_9, J2_10,
	output J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10
);

	reg segment_a = 0;
	reg segment_b = 0;
	reg segment_c = 0;
	reg segment_d = 0;
	reg segment_e = 0;
	reg segment_f = 0;
	reg segment_g = 0;
	reg segment_h = 0;
	reg segment_k = 0;
	reg segment_m = 0;
	reg segment_n = 0;
	reg segment_u = 0;
	reg segment_p = 0;
	reg segment_t = 0;
	reg segment_s = 0;
	reg segment_r = 0;
	reg segment_dp = 0;
	assign J2_7  = segment_a;
	assign J2_2  = segment_b;
	assign J2_4  = segment_c;
	assign J1_5  = segment_d;
	assign J3_8  = segment_e;
	assign J3_7  = segment_f;
	assign J3_5  = segment_g;
	assign J3_4  = segment_h;
	assign J3_3  = segment_k;
	assign J2_1  = segment_m;
	assign J2_10 = segment_n;
	assign J1_4  = segment_u;
	assign J1_3  = segment_p;
	assign J3_6  = segment_t;
	assign J1_7  = segment_s;
	assign J1_6  = segment_r;
	assign J1_8  = segment_dp;
	assign J2_9  = 1;
	assign J1_9  = 1;
	assign J2_3  = 1;
	assign J1_10 = 1;
	assign J2_8  = 1;
	assign J3_9  = 1;
	assign J3_10 = 1;
	reg [31:0] raw_counter = 0;
	reg dot_clock = 0;
	reg [3:0] dot_counter = 0;
	reg clock_1Hz = 0;
	reg [3:0] counter_1Hz = 0;
	reg [15:0] sequence = 0;
	reg reset = 0;
	always @(posedge CLK) begin
		if (raw_counter[31:12]==0) begin
			reset <= 1;
			LED1 <= 0;
			LED2 <= 0;
			LED3 <= 0;
			LED4 <= 0;
			LED5 <= 0;
		end else begin
			LED5 <= dot_clock;
			reset <= 0;
		end
		raw_counter++;
	end
	always begin
		dot_clock <= raw_counter[12];
		dot_counter <= raw_counter[16:13];
	end
	always begin
		clock_1Hz <= raw_counter[23];
		counter_1Hz <= raw_counter[27:24];
	end
	always @(posedge clock_1Hz) begin
		case(counter_1Hz[3:0])
			4'h0    : sequence <= 16'b0000000011111111;
			4'h1    : sequence <= 16'b1100111111111111;
			4'h2    : sequence <= 16'b0001000111100111;
			4'h3    : sequence <= 16'b0000001111100111;
			4'h4    : sequence <= 16'b1100111011100111;
			4'h5    : sequence <= 16'b0010001011100111;
			4'h6    : sequence <= 16'b0010000011100111;
			4'h7    : sequence <= 16'b0000111111111111;
			4'h8    : sequence <= 16'b0000000011100111;
			4'h9    : sequence <= 16'b0000001011100111;
			4'ha    : sequence <= 16'b0000110011100111;
			4'hb    : sequence <= 16'b1110000011100111;
			4'hc    : sequence <= 16'b0011000011111111;
			4'hd    : sequence <= 16'b1100000111100111;
			4'he    : sequence <= 16'b0011000011101111;
			default : sequence <= 16'b0011110011101111;
		endcase
	end
	always @(posedge dot_clock) begin
		if (reset==1) begin
			segment_a  <= 1;
			segment_b  <= 1;
			segment_c  <= 1;
			segment_d  <= 1;
			segment_e  <= 1;
			segment_f  <= 1;
			segment_g  <= 1;
			segment_h  <= 1;
			segment_k  <= 1;
			segment_m  <= 1;
			segment_n  <= 1;
			segment_u  <= 1;
			segment_p  <= 1;
			segment_t  <= 1;
			segment_s  <= 1;
			segment_r  <= 1;
			segment_dp <= 1;
		end else begin
			case(dot_counter)
				4'h0    : begin segment_a <= sequence[15]; segment_r <= 1; end
				4'h1    : begin segment_b <= sequence[14]; segment_a <= 1; end
				4'h2    : begin segment_c <= sequence[13]; segment_b <= 1; end
				4'h3    : begin segment_d <= sequence[12]; segment_c <= 1; end
				4'h4    : begin segment_e <= sequence[11]; segment_d <= 1; end
				4'h5    : begin segment_f <= sequence[10]; segment_e <= 1; end
				4'h6    : begin segment_g <= sequence[09]; segment_f <= 1; end
				4'h7    : begin segment_h <= sequence[08]; segment_g <= 1; end
				4'h8    : begin segment_k <= sequence[07]; segment_h <= 1; end
				4'h9    : begin segment_m <= sequence[06]; segment_k <= 1; end
				4'ha    : begin segment_n <= sequence[05]; segment_m <= 1; end
				4'hb    : begin segment_u <= sequence[04]; segment_n <= 1; end
				4'hc    : begin segment_p <= sequence[03]; segment_u <= 1; end
				4'hd    : begin segment_t <= sequence[02]; segment_p <= 1; end
				4'he    : begin segment_s <= sequence[01]; segment_t <= 1; end
				default : begin segment_r <= sequence[00]; segment_s <= 1; end
			endcase
		end
	end
endmodule