data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/shifter_27.v
data/verilator_xmls/1ad82d7d-3f57-4f1d-83ca-59462388926f.xml
module shifter_27 (
    input [5:0] alufn,
    input [15:0] a,
    input [15:0] b,
    output reg [15:0] c
  );
  
  
  
  always @* begin
    
    case (alufn[0+5-:6])
      6'h20: begin
        c = a << b[0+2-:3];
      end
      6'h21: begin
        c = a >> b[0+2-:3];
      end
      6'h23: begin
        c = $signed(a) >>> b[0+2-:3];
      end
      default: begin
        c = a;
      end
    endcase
  end
endmodule
module shifter_27 (
    input [5:0] alufn,
    input [15:0] a,
    input [15:0] b,
    output reg [15:0] c
  );

  
  
  
  always @* begin
    
    case (alufn[0+5-:6])
      6'h20: begin
        c = a << b[0+2-:3];
      end
      6'h21: begin
        c = a >> b[0+2-:3];
      end
      6'h23: begin
        c = $signed(a) >>> b[0+2-:3];
      end
      default: begin
        c = a;
      end
    endcase
  end
endmodule