data/full_repos/permissive/131573849/fpga_verilog/test_uart.v
 line:13: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_uart.v:13: Unsupported: Ignoring delay on this delayed statement.\n  always #(HALF_STEP) begin  \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_uart.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #(SERIAL_1BIT_TIME);\n      ^\n%Error: data/full_repos/permissive/131573849/fpga_verilog/test_uart.v:39: Unsupported: wait statements\n      wait(serial_tx == 0);  \n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_uart.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #(SERIAL_1BIT_TIME);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_uart.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #(SERIAL_1BIT_TIME / 2);  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_uart.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #(SERIAL_1BIT_TIME);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_uart.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #(SERIAL_1BIT_TIME);  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_uart.v:65: Unsupported: Ignoring delay on this delayed statement.\n      #(STEP * 10);      \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_uart.v:67: Unsupported: Ignoring delay on this delayed statement.\n      #(STEP * 10);      \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_uart.v:73: Unsupported: Ignoring delay on this delayed statement.\n      #(STEP * 7000);   \n      ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_uart();

  parameter STEP = 20;
  parameter HALF_STEP = 10;
  parameter SERIAL_1BIT_TIME = 8680;

  reg rst = 1;
  reg clk = 0;
  wire serial_tx;
  reg serial_rx = 1;

  always #(HALF_STEP) begin
    clk <= ~clk;
  end
  task send_bit;
    input data;
    begin
      serial_rx <= data;
      #(SERIAL_1BIT_TIME);
    end
  endtask
  task serial_send_byte;
    input [7:0] data;
    begin
      integer i;
      send_bit(0);
      for (i = 0; i < 8; i = i + 1) begin
        send_bit(data[i]);
      end
      send_bit(1);
    end
  endtask

  task serial_recv_byte;
    output [7:0] data;
    begin
      integer i;
      wait(serial_tx == 0);
      #(SERIAL_1BIT_TIME);
      #(SERIAL_1BIT_TIME / 2);
      for (i = 0; i < 8; i = i + 1) begin
        data[i] <= serial_tx;
        #(SERIAL_1BIT_TIME);
      end
      #(SERIAL_1BIT_TIME);
    end
  endtask

  top top (
    .input_clk(clk),
    .rst(rst),
    .serial_rx(serial_rx),
    .serial_tx(serial_tx));

  initial begin
    forever begin
      reg [7:0] data;
      serial_recv_byte(data);
      $display("RECV_DATA = %x", data);
    end
  end

  initial begin
      #(STEP * 10);
      rst <= 0;
      #(STEP * 10);
      serial_send_byte(8'hAC);
      serial_send_byte(8'hCA);
      serial_send_byte(8'h55);
      serial_send_byte(8'h00);
      serial_send_byte(8'hFF);
      #(STEP * 7000);
      $finish;
  end

endmodule
module test_uart();


  parameter STEP = 20;
  parameter HALF_STEP = 10;
  parameter SERIAL_1BIT_TIME = 8680;

  reg rst = 1;
  reg clk = 0;
  wire serial_tx;
  reg serial_rx = 1;

  always #(HALF_STEP) begin
    clk <= ~clk;
  end
  task send_bit;
    input data;
    begin
      serial_rx <= data;
      #(SERIAL_1BIT_TIME);
    end
  endtask
  task serial_send_byte;
    input [7:0] data;
    begin
      integer i;
      send_bit(0);
      for (i = 0; i < 8; i = i + 1) begin
        send_bit(data[i]);
      end
      send_bit(1);
    end
  endtask

  task serial_recv_byte;
    output [7:0] data;
    begin
      integer i;
      wait(serial_tx == 0);
      #(SERIAL_1BIT_TIME);
      #(SERIAL_1BIT_TIME / 2);
      for (i = 0; i < 8; i = i + 1) begin
        data[i] <= serial_tx;
        #(SERIAL_1BIT_TIME);
      end
      #(SERIAL_1BIT_TIME);
    end
  endtask

  top top (
    .input_clk(clk),
    .rst(rst),
    .serial_rx(serial_rx),
    .serial_tx(serial_tx));

  initial begin
    forever begin
      reg [7:0] data;
      serial_recv_byte(data);
      $display("RECV_DATA = %x", data);
    end
  end

  initial begin
      #(STEP * 10);
      rst <= 0;
      #(STEP * 10);
      serial_send_byte(8'hAC);
      serial_send_byte(8'hCA);
      serial_send_byte(8'h55);
      serial_send_byte(8'h00);
      serial_send_byte(8'hFF);
      #(STEP * 7000);
      $finish;
  end

endmodule