data/full_repos/permissive/143278/ivltests/pr1873372.v
 line:2: before: "real"
data/verilator_xmls/43a8eb9d-f82b-4315-98b4-82af0bb9d62b.xml
module top;
  wire real sml;
  wire real big;
  wire real prec;

  assign sml = 1e-20;
  assign big = 1e20;
  assign prec = 0.123456789;

  initial $display("big: %g, small: %g, precision: %0.11f", big, sml, prec);
endmodule
module top;

  wire real sml;
  wire real big;
  wire real prec;

  assign sml = 1e-20;
  assign big = 1e20;
  assign prec = 0.123456789;

  initial $display("big: %g, small: %g, precision: %0.11f", big, sml, prec);
endmodule