data/full_repos/permissive/211316121/lab5_4_nexys4/74LS194.v
data/verilator_xmls/72844cc1-2a5b-49c9-8cdc-211970544e33.xml
module CLKDIV(
    input clkstd,
    output clk
);
reg [26:0] q;

always@(posedge clkstd)
    q<=q+1;

assign clk=q[26];

endmodule
module CLKDIV(
    input clkstd,
    output clk
);

reg [26:0] q;

always@(posedge clkstd)
    q<=q+1;

assign clk=q[26];

endmodule