data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim/file_reader.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim/file_reader.v:29: Cannot find include file: stream_common.vh\n`include "stream_common.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh.sv\n             stream_common.vh\n             stream_common.vh.v\n             stream_common.vh.sv\n             obj_dir/stream_common.vh\n             obj_dir/stream_common.vh.v\n             obj_dir/stream_common.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module file_reader (clk, rst, rd_en, rd_valid, rd_data, done);
`include "stream_common.vh"

  parameter Filename   = "undefined";
  parameter NumSymbols = 2;
  parameter SymbolBits = {32'd8,32'd1};


  localparam TotalWidth = calc_total(NumSymbols, SymbolBits);

  input                       clk;
  input                       rst;
  input                       rd_en;
  output                      rd_valid;
  output reg [TotalWidth-1:0] rd_data;
  output                      done;





  integer fp;
  initial begin
    fp  = $fopen(Filename, "r");
    if (!fp) begin
      $display("Error: unable to open file \"%s\"", Filename);
      $display("***SIMULATION FAILED***");
      $finish;
    end
  end




  integer              col_width;
  integer              col_val;
  reg                  started;
  reg                  eof;
  reg [TotalWidth-1:0] data_i;
  reg [256*8-1:0]      junk;
  integer              i, r;

  always @(posedge clk) begin
    if (rst) begin
      started  <= 1'b0;
      eof      <= 1'b0;
    end else begin
      if (!eof && (!started || rd_en)) begin
        started <= 1'b1;


        data_i   = 0;
        for (i=NumSymbols-1; i >= 0; i=i-1) begin
          r          = $fscanf(fp, "%d", col_val);
          col_width  = get_symbol_width(NumSymbols, SymbolBits, i);
          data_i     = (data_i << col_width) | col_val;
        end
        rd_data  <= data_i;


        r = $fgets(junk, fp);
        if ($feof(fp)) begin
          eof <= 1'b1;
          $fclose(fp);
        end

      end
    end
  end

  assign done     = eof;
  assign rd_valid = started & ~done;

endmodule
module file_reader (clk, rst, rd_en, rd_valid, rd_data, done);

`include "stream_common.vh"

  parameter Filename   = "undefined";
  parameter NumSymbols = 2;
  parameter SymbolBits = {32'd8,32'd1};


  localparam TotalWidth = calc_total(NumSymbols, SymbolBits);

  input                       clk;
  input                       rst;
  input                       rd_en;
  output                      rd_valid;
  output reg [TotalWidth-1:0] rd_data;
  output                      done;





  integer fp;
  initial begin
    fp  = $fopen(Filename, "r");
    if (!fp) begin
      $display("Error: unable to open file \"%s\"", Filename);
      $display("***SIMULATION FAILED***");
      $finish;
    end
  end




  integer              col_width;
  integer              col_val;
  reg                  started;
  reg                  eof;
  reg [TotalWidth-1:0] data_i;
  reg [256*8-1:0]      junk;
  integer              i, r;

  always @(posedge clk) begin
    if (rst) begin
      started  <= 1'b0;
      eof      <= 1'b0;
    end else begin
      if (!eof && (!started || rd_en)) begin
        started <= 1'b1;


        data_i   = 0;
        for (i=NumSymbols-1; i >= 0; i=i-1) begin
          r          = $fscanf(fp, "%d", col_val);
          col_width  = get_symbol_width(NumSymbols, SymbolBits, i);
          data_i     = (data_i << col_width) | col_val;
        end
        rd_data  <= data_i;


        r = $fgets(junk, fp);
        if ($feof(fp)) begin
          eof <= 1'b1;
          $fclose(fp);
        end

      end
    end
  end

  assign done     = eof;
  assign rd_valid = started & ~done;

endmodule