data/full_repos/permissive/203165721/base_generator.v
1: b"%Error: data/full_repos/permissive/203165721/base_generator.v:50: Cannot find file containing module: 'mult16'\nmult16 m1(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203165721,data/full_repos/permissive/203165721/mult16\n             data/full_repos/permissive/203165721,data/full_repos/permissive/203165721/mult16.v\n             data/full_repos/permissive/203165721,data/full_repos/permissive/203165721/mult16.sv\n             mult16\n             mult16.v\n             mult16.sv\n             obj_dir/mult16\n             obj_dir/mult16.v\n             obj_dir/mult16.sv\n%Error: data/full_repos/permissive/203165721/base_generator.v:56: Cannot find file containing module: 'mult16'\nmult16 m2(\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module base_generator
#(
parameter FPGA_FAMILY = "ALTERA"	,
parameter	X_W	=	16				,
parameter	E_W	=	16				,
parameter	W_W	=	16				
)
(
	input						clk			,
	input						rst_n		,
	input						en			,
	
	input	signed	[X_W-1:0]xin			,
	input	signed	[E_W-1:0]err			,
	output 	   signed  [X_W+W_W-1:0]yout	,
	output reg signed  [W_W-1:0]wout		,
	output	reg			update
);

wire signed [X_W+E_W-1:0]	coef_tmp		;
reg  signed [X_W+E_W:0]	coef_nxt		;
reg  signed [X_W+E_W-1:0]	coef			;
reg  signed [X_W-1:0]	x_r				;
reg  signed [E_W-1:0]	e_r				;
reg	[2:0]			state			;


generate if (FPGA_FAMILY == "ALTERA")
begin
mult16 m1(
	.dataa	(x_r),
	.datab	(e_r),
	.result	(coef_tmp)
);

mult16 m2(
	.dataa	(x_r),
	.datab	(wout),
	.result	(yout)
);
end
else
begin
assign coef_tmp = x_r * e_r;
assign yout = x_r * wout;
end
endgenerate

always @ (posedge clk or negedge rst_n)
begin
	if (!rst_n)
	begin
		state		<=	'd0;
		coef_nxt	<=	'd0;
		coef		<=	'd0;
		wout		<=	'd0;
		update		<=	'd0;
		x_r			<=	'd0;
		e_r			<=	'd0;
	end
	else 
	case (state)
	3'd0: 
	begin
		if (en)
		begin
			state	<=	3'd1;
			x_r	<=	xin	;
			e_r	<=	err	;
		end
		update	<=	1'b0;
	end
	3'd1:
	begin
		coef_nxt	<=	coef_tmp + coef;
		coef	<=	coef_nxt[X_W-1+E_W:0];
		wout	<=	coef_nxt[X_W-1+E_W-:W_W];
		state	<=	3'd0;
		update	<=	1'b1;
	end
	default: state	<=	3'd0;
	endcase
end

endmodule
module base_generator
#(
parameter FPGA_FAMILY = "ALTERA"	,
parameter	X_W	=	16				,
parameter	E_W	=	16				,
parameter	W_W	=	16				
)
(
	input						clk			,
	input						rst_n		,
	input						en			,
	
	input	signed	[X_W-1:0]xin			,
	input	signed	[E_W-1:0]err			,
	output 	   signed  [X_W+W_W-1:0]yout	,
	output reg signed  [W_W-1:0]wout		,
	output	reg			update
);


wire signed [X_W+E_W-1:0]	coef_tmp		;
reg  signed [X_W+E_W:0]	coef_nxt		;
reg  signed [X_W+E_W-1:0]	coef			;
reg  signed [X_W-1:0]	x_r				;
reg  signed [E_W-1:0]	e_r				;
reg	[2:0]			state			;


generate if (FPGA_FAMILY == "ALTERA")
begin
mult16 m1(
	.dataa	(x_r),
	.datab	(e_r),
	.result	(coef_tmp)
);

mult16 m2(
	.dataa	(x_r),
	.datab	(wout),
	.result	(yout)
);
end
else
begin
assign coef_tmp = x_r * e_r;
assign yout = x_r * wout;
end
endgenerate

always @ (posedge clk or negedge rst_n)
begin
	if (!rst_n)
	begin
		state		<=	'd0;
		coef_nxt	<=	'd0;
		coef		<=	'd0;
		wout		<=	'd0;
		update		<=	'd0;
		x_r			<=	'd0;
		e_r			<=	'd0;
	end
	else 
	case (state)
	3'd0: 
	begin
		if (en)
		begin
			state	<=	3'd1;
			x_r	<=	xin	;
			e_r	<=	err	;
		end
		update	<=	1'b0;
	end
	3'd1:
	begin
		coef_nxt	<=	coef_tmp + coef;
		coef	<=	coef_nxt[X_W-1+E_W:0];
		wout	<=	coef_nxt[X_W-1+E_W-:W_W];
		state	<=	3'd0;
		update	<=	1'b1;
	end
	default: state	<=	3'd0;
	endcase
end

endmodule