data/full_repos/permissive/148324174/SeqLogic/ShiftReg_tb.v
 line:30: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/ShiftReg_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/ShiftReg_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n #3.2 Din = ~Din;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/ShiftReg_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1.8 Din = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/ShiftReg_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #5 shift_ena = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/ShiftReg_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #180 rst = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/ShiftReg_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish;\n ^\n%Error: data/full_repos/permissive/148324174/SeqLogic/ShiftReg_tb.v:8: Cannot find file containing module: \'ShiftReg\'\nShiftReg shift_U1(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/148324174/SeqLogic,data/full_repos/permissive/148324174/ShiftReg\n             data/full_repos/permissive/148324174/SeqLogic,data/full_repos/permissive/148324174/ShiftReg.v\n             data/full_repos/permissive/148324174/SeqLogic,data/full_repos/permissive/148324174/ShiftReg.sv\n             ShiftReg\n             ShiftReg.v\n             ShiftReg.sv\n             obj_dir/ShiftReg\n             obj_dir/ShiftReg.v\n             obj_dir/ShiftReg.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ShiftReg_tb;

reg Din, shift_ena, clk, rst;
wire Qout;

ShiftReg shift_U1(
	.Din(Din),
	.shift_ena(shift_ena),
	.clk(clk),
	.rst(rst),
	.Qout(Qout)
	);

always #1 clk = ~clk;
always begin
	#3.2 Din = ~Din;
	#1.8 Din = 0;
end

initial begin
	Din = 1'b0;
	shift_ena = 1'b0;
	clk = 1'b1;
	rst = 1'b1;

	#5 shift_ena = 1'b1;
	#180 rst = 1'b0;
	#200 $finish;
end

endmodule
module ShiftReg_tb;


reg Din, shift_ena, clk, rst;
wire Qout;

ShiftReg shift_U1(
	.Din(Din),
	.shift_ena(shift_ena),
	.clk(clk),
	.rst(rst),
	.Qout(Qout)
	);

always #1 clk = ~clk;
always begin
	#3.2 Din = ~Din;
	#1.8 Din = 0;
end

initial begin
	Din = 1'b0;
	shift_ena = 1'b0;
	clk = 1'b1;
	rst = 1'b1;

	#5 shift_ena = 1'b1;
	#180 rst = 1'b0;
	#200 $finish;
end

endmodule