data/full_repos/permissive/143278/ivltests/drive_strength3.v
 line:60: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/drive_strength3.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #100 if (bit !== 1\'b0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/drive_strength3.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #100 if (bit !== 1\'b1) begin\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/drive_strength3.v:60: syntax error, unexpected (-for-strength, expecting \'(\'\n   buf (weak0,weak1) #(1,1) (O,A);\n        ^~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire bit;
   PULLDOWN pd(bit);

   reg	drv;
   assign bit = drv;

   initial begin
      drv = 0;
      #100 if (bit !== 1'b0) begin
	 $display("FAILED -- 0 bit = %b", bit);
	 $finish;
      end

      drv = 1;
      #100 if (bit !== 1'b1) begin
	 $display("FAILED -- 1 bit = %b", bit);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   wire bit;
   PULLDOWN pd(bit);

   reg	drv;
   assign bit = drv;

   initial begin
      drv = 0;
      #100 if (bit !== 1'b0) begin
	 $display("FAILED -- 0 bit = %b", bit);
	 $finish;
      end

      drv = 1;
      #100 if (bit !== 1'b1) begin
	 $display("FAILED -- 1 bit = %b", bit);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule