data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src/ImmOperandUnit.v
 line:65: before: "input"
1: b'%Error: data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src/ImmOperandUnit.v:12: Cannot find include file: Parameters.v\n`include "Parameters.v"    \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v.v\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v.sv\n             Parameters.v\n             Parameters.v.v\n             Parameters.v.sv\n             obj_dir/Parameters.v\n             obj_dir/Parameters.v.v\n             obj_dir/Parameters.v.sv\n%Error: data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src/ImmOperandUnit.v:22: Define or directive not defined: \'`ITYPE\'\n            `ITYPE: Out<={ {21{In[31]}}, In[30:20] };\n            ^~~~~~\n%Error: data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src/ImmOperandUnit.v:22: syntax error, unexpected \':\', expecting endcase\n            `ITYPE: Out<={ {21{In[31]}}, In[30:20] };\n                  ^\n%Error: Cannot continue\n'
module ImmOperandUnit(
    input wire [31:7] In,
    input wire [2:0] Type,
    output reg [31:0] Out
    );

    always@(*)
    begin
        case(Type)
            `ITYPE: Out<={ {21{In[31]}}, In[30:20] };

            default:Out<=32'hxxxxxxxx;
        endcase
    end
    
endmodule
module ImmOperandUnit(
    input wire [31:7] In,
    input wire [2:0] Type,
    output reg [31:0] Out
    );


    always@(*)
    begin
        case(Type)
            `ITYPE: Out<={ {21{In[31]}}, In[30:20] };

            default:Out<=32'hxxxxxxxx;
        endcase
    end
    
endmodule