data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v
 line:78: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v:182: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'one_hot_to_binary\' generates 32 bits.\n                                                                                                                                           : ... In instance ctrlport_combiner\n            slave_sel <= one_hot_to_binary(next_slave_one_hot);\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v:185: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'slave_sel\' generates 1 bits.\n                                                                                                                                           : ... In instance ctrlport_combiner\n          else if(slave_sel == NUM_MASTERS-1)\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v:199: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'one_hot_to_binary\' generates 32 bits.\n                                                                                                                                           : ... In instance ctrlport_combiner\n            slave_sel <= one_hot_to_binary(next_slave_one_hot);\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v:201: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'slave_sel\' generates 1 bits.\n                                                                                                                                           : ... In instance ctrlport_combiner\n          else if (slave_sel == NUM_MASTERS-1)\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v:251: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'slave_sel\' generates 1 bits.\n                                                                                                                                           : ... In instance ctrlport_combiner\n        if (i == slave_sel && m_ctrlport_resp_ack) begin\n              ^~\n%Error: Exiting due to 5 warning(s)\n'
function integer one_hot_to_binary(input [NUM_MASTERS-1:0] one_hot_vec);
    integer i, total;
  begin
    total = 0;
    for (i = 0; i <= NUM_MASTERS-1; i = i + 1) begin
      if (one_hot_vec[i]) begin
        total = total + i;
      end
    end
    one_hot_to_binary = total;
  end
  endfunction
function integer one_hot_to_binary(input [NUM_MASTERS-1:0] one_hot_vec);

    integer i, total;
  begin
    total = 0;
    for (i = 0; i <= NUM_MASTERS-1; i = i + 1) begin
      if (one_hot_vec[i]) begin
        total = total + i;
      end
    end
    one_hot_to_binary = total;
  end
  endfunction