data/full_repos/permissive/168395472/labs/02_dff/testbench.v
 line:42: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/168395472/labs/02_dff/testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/168395472/labs/02_dff/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/168395472/labs/02_dff/testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #5 d = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/168395472/labs/02_dff/testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #4.5 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/168395472/labs/02_dff/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #0.25 rst = 1;\n    ^\n%Error: data/full_repos/permissive/168395472/labs/02_dff/testbench.v:40: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;       \n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/168395472/labs/02_dff/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;     \n    ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

reg clk = 1'b0;

always begin
    #1 clk = ~clk;
end

wire q;
wire q2;
reg d;
reg rst;

initial begin
    d = 0;
    #2 d = 1;
    #5 d = 0;
end

initial begin
    rst = 1;
    #4.5 rst = 0;
    #0.25 rst = 1;
end

dff dff(.clk(clk), .d(d), .q(q));
dff2 dff2(.clk(clk), .d(d), .q(q2), .reset(rst));

initial begin
    $dumpvars;
    $display("Test started...");
    #10 $finish;
end

endmodule
module testbench();


reg clk = 1'b0;

always begin
    #1 clk = ~clk;
end

wire q;
wire q2;
reg d;
reg rst;

initial begin
    d = 0;
    #2 d = 1;
    #5 d = 0;
end

initial begin
    rst = 1;
    #4.5 rst = 0;
    #0.25 rst = 1;
end

dff dff(.clk(clk), .d(d), .q(q));
dff2 dff2(.clk(clk), .d(d), .q(q2), .reset(rst));

initial begin
    $dumpvars;
    $display("Test started...");
    #10 $finish;
end

endmodule