data/full_repos/permissive/217441787/fpga/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/217441787/fpga/testbench.v:155: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/217441787/fpga/testbench.v:162: Unsupported: Ignoring delay on this delayed statement.\n        #5 CLK_OSC = !CLK_OSC;\n        ^\n%Error: data/full_repos/permissive/217441787/fpga/testbench.v:77: Cannot find file containing module: \'pano_top\'\n    pano_top uut (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217441787/fpga,data/full_repos/permissive/217441787/pano_top\n             data/full_repos/permissive/217441787/fpga,data/full_repos/permissive/217441787/pano_top.v\n             data/full_repos/permissive/217441787/fpga,data/full_repos/permissive/217441787/pano_top.sv\n             pano_top\n             pano_top.v\n             pano_top.sv\n             obj_dir/pano_top\n             obj_dir/pano_top.v\n             obj_dir/pano_top.sv\n%Error: data/full_repos/permissive/217441787/fpga/testbench.v:123: Cannot find file containing module: \'mobile_ddr\'\n    mobile_ddr mobile_ddr\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/217441787/fpga/testbench.v:139: Cannot find file containing module: \'spiflash\'\n    spiflash spiflash (\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;


    reg CLK_OSC;
    reg PB;
    wire SPI_MISO;
    reg USB_IRQ;


    wire LED_RED;
    wire LED_GREEN;
    wire LED_BLUE;
    wire SPI_CS_B;
    wire SPI_SCK;
    wire SPI_MOSI;
    wire AUDIO_MCLK;
    wire AUDIO_BCLK;
    wire AUDIO_DACDATA;
    wire AUDIO_DACLRCK;
    wire AUDIO_SCL;
    wire AUDIO_SDA;
    wire [11:0] LPDDR_A;
    wire LPDDR_CK_P;
    wire LPDDR_CK_N;
    wire LPDDR_CKE;
    wire LPDDR_WE_B;
    wire LPDDR_CAS_B;
    wire LPDDR_RAS_B;
    wire [3:0] LPDDR_DM;
    wire [1:0] LPDDR_BA;
    wire VGA_CLK;
    wire VGA_VSYNC;
    wire VGA_HSYNC;
    wire VGA_BLANK_B;
    wire [7:0] VGA_R;
    wire [7:0] VGA_G;
    wire [7:0] VGA_B;
    wire USB_CLKIN;
    wire USB_RESET_B;
    wire USB_CS_B;
    wire USB_RD_B;
    wire USB_WR_B;
    wire [17:1] USB_A;


    wire [31:0] LPDDR_DQ;
    wire [3:0] LPDDR_DQS;
    wire VGA_SCL;
    wire VGA_SDA;
    wire [15:0] USB_D;


    pano_top uut (
        .CLK_OSC(CLK_OSC), 
        .LED_RED(LED_RED), 
        .LED_GREEN(LED_GREEN), 
        .LED_BLUE(LED_BLUE), 
        .PB(PB), 
        .SPI_CS_B(SPI_CS_B),
        .SPI_SCK(SPI_SCK),
        .SPI_MOSI(SPI_MOSI),
        .SPI_MISO(SPI_MISO),
        .AUDIO_MCLK(AUDIO_MCLK),
        .AUDIO_BCLK(AUDIO_BCLK),
        .AUDIO_DACDATA(AUDIO_DACDATA),
        .AUDIO_DACLRCK(AUDIO_DACLRCK),
        .AUDIO_SCL(AUDIO_SCL),
        .AUDIO_SDA(AUDIO_SDA),
        .LPDDR_A(LPDDR_A), 
        .LPDDR_CK_P(LPDDR_CK_P), 
        .LPDDR_CK_N(LPDDR_CK_N), 
        .LPDDR_CKE(LPDDR_CKE), 
        .LPDDR_WE_B(LPDDR_WE_B), 
        .LPDDR_CAS_B(LPDDR_CAS_B), 
        .LPDDR_RAS_B(LPDDR_RAS_B), 
        .LPDDR_DM(LPDDR_DM), 
        .LPDDR_BA(LPDDR_BA), 
        .LPDDR_DQ(LPDDR_DQ), 
        .LPDDR_DQS(LPDDR_DQS), 
        .VGA_CLK(VGA_CLK), 
        .VGA_VSYNC(VGA_VSYNC), 
        .VGA_HSYNC(VGA_HSYNC), 
        .VGA_BLANK_B(VGA_BLANK_B), 
        .VGA_SCL(VGA_SCL), 
        .VGA_SDA(VGA_SDA), 
        .VGA_R(VGA_R), 
        .VGA_G(VGA_G), 
        .VGA_B(VGA_B),
        .USB_CLKIN(USB_CLKIN),
        .USB_RESET_B(USB_RESET_B),
        .USB_CS_B(USB_CS_B),
        .USB_RD_B(USB_RD_B),
        .USB_WR_B(USB_WR_B),
        .USB_IRQ(USB_IRQ),
        .USB_A(USB_A),
        .USB_D(USB_D)
    );
    
    mobile_ddr mobile_ddr
    (
        .Dq    (LPDDR_DQ),
        .Dqs   (LPDDR_DQS),
        .Addr  (LPDDR_A),
        .Ba    (LPDDR_BA),
        .Clk   (LPDDR_CK_P),
        .Clk_n (LPDDR_CK_N),
        .Cke   (LPDDR_CKE),
        .Cs_n  (1'b0),
        .Ras_n (LPDDR_RAS_B),
        .Cas_n (LPDDR_CAS_B),
        .We_n  (LPDDR_WE_B),
        .Dm    (LPDDR_DM)
    );

    spiflash spiflash (
        .csb(SPI_CS_B),
        .clk(SPI_SCK),
        .io0(SPI_MOSI),
        .io1(SPI_MISO),
        .io2(),
        .io3()
    );

    initial begin

        CLK_OSC = 0;
        PB = 1;
        USB_IRQ = 0;


        #100;
        

        PB = 0;
    end
    
    always begin
        #5 CLK_OSC = !CLK_OSC;
    end
endmodule
module testbench;



    reg CLK_OSC;
    reg PB;
    wire SPI_MISO;
    reg USB_IRQ;


    wire LED_RED;
    wire LED_GREEN;
    wire LED_BLUE;
    wire SPI_CS_B;
    wire SPI_SCK;
    wire SPI_MOSI;
    wire AUDIO_MCLK;
    wire AUDIO_BCLK;
    wire AUDIO_DACDATA;
    wire AUDIO_DACLRCK;
    wire AUDIO_SCL;
    wire AUDIO_SDA;
    wire [11:0] LPDDR_A;
    wire LPDDR_CK_P;
    wire LPDDR_CK_N;
    wire LPDDR_CKE;
    wire LPDDR_WE_B;
    wire LPDDR_CAS_B;
    wire LPDDR_RAS_B;
    wire [3:0] LPDDR_DM;
    wire [1:0] LPDDR_BA;
    wire VGA_CLK;
    wire VGA_VSYNC;
    wire VGA_HSYNC;
    wire VGA_BLANK_B;
    wire [7:0] VGA_R;
    wire [7:0] VGA_G;
    wire [7:0] VGA_B;
    wire USB_CLKIN;
    wire USB_RESET_B;
    wire USB_CS_B;
    wire USB_RD_B;
    wire USB_WR_B;
    wire [17:1] USB_A;


    wire [31:0] LPDDR_DQ;
    wire [3:0] LPDDR_DQS;
    wire VGA_SCL;
    wire VGA_SDA;
    wire [15:0] USB_D;


    pano_top uut (
        .CLK_OSC(CLK_OSC), 
        .LED_RED(LED_RED), 
        .LED_GREEN(LED_GREEN), 
        .LED_BLUE(LED_BLUE), 
        .PB(PB), 
        .SPI_CS_B(SPI_CS_B),
        .SPI_SCK(SPI_SCK),
        .SPI_MOSI(SPI_MOSI),
        .SPI_MISO(SPI_MISO),
        .AUDIO_MCLK(AUDIO_MCLK),
        .AUDIO_BCLK(AUDIO_BCLK),
        .AUDIO_DACDATA(AUDIO_DACDATA),
        .AUDIO_DACLRCK(AUDIO_DACLRCK),
        .AUDIO_SCL(AUDIO_SCL),
        .AUDIO_SDA(AUDIO_SDA),
        .LPDDR_A(LPDDR_A), 
        .LPDDR_CK_P(LPDDR_CK_P), 
        .LPDDR_CK_N(LPDDR_CK_N), 
        .LPDDR_CKE(LPDDR_CKE), 
        .LPDDR_WE_B(LPDDR_WE_B), 
        .LPDDR_CAS_B(LPDDR_CAS_B), 
        .LPDDR_RAS_B(LPDDR_RAS_B), 
        .LPDDR_DM(LPDDR_DM), 
        .LPDDR_BA(LPDDR_BA), 
        .LPDDR_DQ(LPDDR_DQ), 
        .LPDDR_DQS(LPDDR_DQS), 
        .VGA_CLK(VGA_CLK), 
        .VGA_VSYNC(VGA_VSYNC), 
        .VGA_HSYNC(VGA_HSYNC), 
        .VGA_BLANK_B(VGA_BLANK_B), 
        .VGA_SCL(VGA_SCL), 
        .VGA_SDA(VGA_SDA), 
        .VGA_R(VGA_R), 
        .VGA_G(VGA_G), 
        .VGA_B(VGA_B),
        .USB_CLKIN(USB_CLKIN),
        .USB_RESET_B(USB_RESET_B),
        .USB_CS_B(USB_CS_B),
        .USB_RD_B(USB_RD_B),
        .USB_WR_B(USB_WR_B),
        .USB_IRQ(USB_IRQ),
        .USB_A(USB_A),
        .USB_D(USB_D)
    );
    
    mobile_ddr mobile_ddr
    (
        .Dq    (LPDDR_DQ),
        .Dqs   (LPDDR_DQS),
        .Addr  (LPDDR_A),
        .Ba    (LPDDR_BA),
        .Clk   (LPDDR_CK_P),
        .Clk_n (LPDDR_CK_N),
        .Cke   (LPDDR_CKE),
        .Cs_n  (1'b0),
        .Ras_n (LPDDR_RAS_B),
        .Cas_n (LPDDR_CAS_B),
        .We_n  (LPDDR_WE_B),
        .Dm    (LPDDR_DM)
    );

    spiflash spiflash (
        .csb(SPI_CS_B),
        .clk(SPI_SCK),
        .io0(SPI_MOSI),
        .io1(SPI_MISO),
        .io2(),
        .io3()
    );

    initial begin

        CLK_OSC = 0;
        PB = 1;
        USB_IRQ = 0;


        #100;
        

        PB = 0;
    end
    
    always begin
        #5 CLK_OSC = !CLK_OSC;
    end
endmodule