data/full_repos/permissive/159555381/encoder.v
 line:26: before: ","
1: b'%Error: data/full_repos/permissive/159555381/encoder.v:24: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("encoder.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/159555381/encoder.v:25: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars (0, Test);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/159555381/encoder.v:26: Unsupported or unknown PLI call: $monitor\n  $monitor($time,, "IP = %b A1 = %b A2 = %b A3 = %b", inp, a1, a2, a3);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/159555381/encoder.v:26: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  $monitor($time,, "IP = %b A1 = %b A2 = %b A3 = %b", inp, a1, a2, a3);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/encoder.v:28: Unsupported: Ignoring delay on this delayed statement.\n         #2 { b8, b7, b6, b5, b4, b3, b2, b1} = { 1\'b0, 1\'b1, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0 };\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159555381/encoder.v:29: Unsupported: Ignoring delay on this delayed statement.\n         #2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1\'b0, 1\'b0, 1\'b1, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0 };\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/encoder.v:30: Unsupported: Ignoring delay on this delayed statement.\n         #2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1\'b0, 1\'b0, 1\'b0, 1\'b1, 1\'b0, 1\'b0, 1\'b0, 1\'b0 };\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/encoder.v:31: Unsupported: Ignoring delay on this delayed statement.\n         #2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0 };\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/encoder.v:32: Unsupported: Ignoring delay on this delayed statement.\n         #5 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1\'b0, 1\'b0, 1\'b1, 1\'b0, 1\'b1, 1\'b0, 1\'b0, 1\'b0 };\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/encoder.v:33: Unsupported: Ignoring delay on this delayed statement.\n         #2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b0, 1\'b1, 1\'b0, 1\'b0 };\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/encoder.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #2 $finish;\n  ^\n%Error: Exiting due to 4 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test(
	output reg b1, b2, b3, b4, b5, b6, b7, b8,
	input a1, a2, a3);
	
	wire [7:0] inp;
	assign inp = {b1, b2, b3, b4, b5, b6, b7, b8};
	initial begin 
		$dumpfile ("encoder.vcd");
		$dumpvars (0, Test);
		$monitor($time,, "IP = %b A1 = %b A2 = %b A3 = %b", inp, a1, a2, a3);
		{ b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
        	#2 { b8, b7, b6, b5, b4, b3, b2, b1} = { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
        	#2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
        	#2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 };
        	#2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
        	#5 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 };
        	#2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 };
		#2 $finish;
	end
endmodule
module Test(
	output reg b1, b2, b3, b4, b5, b6, b7, b8,
	input a1, a2, a3);

	
	wire [7:0] inp;
	assign inp = {b1, b2, b3, b4, b5, b6, b7, b8};
	initial begin 
		$dumpfile ("encoder.vcd");
		$dumpvars (0, Test);
		$monitor($time,, "IP = %b A1 = %b A2 = %b A3 = %b", inp, a1, a2, a3);
		{ b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
        	#2 { b8, b7, b6, b5, b4, b3, b2, b1} = { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
        	#2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
        	#2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 };
        	#2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
        	#5 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 };
        	#2 { b8, b7, b6, b5, b4, b3, b2, b1 } = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 };
		#2 $finish;
	end
endmodule