data/full_repos/permissive/125927162/UART/UART_TX.v
1: b'%Warning-WIDTH: data/full_repos/permissive/125927162/UART/UART_TX.v:71: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                      : ... In instance UART_TX\n       tx <= send_data[bits_sent];\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module UART_TX(clk, rst, data, data_ready, data_sent, tx);
   parameter BITS = 8;
   parameter STOPBITS = 1;
   parameter PARITY = 0;
   
   localparam BITLEN = 16;

   localparam STATE_WAIT = 1;
   localparam STATE_START = 2;
   localparam STATE_SEND = 4;
   localparam STATE_PARITY = 8;
   localparam STATE_STOP = 16;
   localparam NUM_STATES = 5;

   input 	      clk;
   input [BITS - 1:0] data;
   input 	      data_ready;
   input 	      rst;
   output reg 	      data_sent; 	      
   output reg	      tx;

   reg [BITS - 1:0]   send_data;
   reg [NUM_STATES - 1:0] STATE;
   reg [$clog2(BITS + 1) - 1:0]        bits_sent;   
   reg [$clog2(BITLEN * STOPBITS + 1) - 1:0] 	  counter;
   
   always @ (posedge clk) begin
      if (rst) begin
	 STATE <= STATE_WAIT;
	 bits_sent <= 0;
	 send_data <= 0;
	 counter <= 0;
	 data_sent <= 0;
      end
      else begin
	 case (STATE)
	   STATE_WAIT: begin
	     if (data_ready) begin
		STATE <= STATE_START;
		data_sent <= 0;
		send_data <= data;
		counter <= 0;
	     end
	   end
	   STATE_START: begin
	      tx <= 0;
	      counter <= counter + 1;
	      if (counter == BITLEN - 1) begin
		 counter <= 0;
		 STATE <= STATE_SEND;
		 bits_sent <= 0;
	      end
	   end
	   STATE_SEND: begin
	      counter <= counter + 1;
	      tx <= send_data[bits_sent];
	      if (counter == BITLEN - 1) begin
		 counter <= 0;
		 bits_sent <= bits_sent + 1;
		 if (bits_sent == BITS - 1) begin
		    bits_sent <= 0;
		    STATE <= (PARITY == 0) ? STATE_STOP : STATE_PARITY;
		 end


	      end
	   end
	   STATE_PARITY: begin
	      counter <= counter + 1;
	      tx <= (PARITY == 1)? ~^send_data : ^send_data;
	      if (counter == BITLEN - 1) begin
		 counter <= 0;
		 STATE <= STATE_STOP;
	      end
	   end
	   STATE_STOP: begin
	      counter <= counter + 1;
	      tx <= 1;
	      if (counter == (BITLEN - 1) * STOPBITS) begin
		 STATE <= STATE_WAIT;
		 tx <= 1'bZ;
		 data_sent <= 1;
	      end
	   end
	 endcase
      end
   end

endmodule
module UART_TX(clk, rst, data, data_ready, data_sent, tx);

   parameter BITS = 8;
   parameter STOPBITS = 1;
   parameter PARITY = 0;
   
   localparam BITLEN = 16;

   localparam STATE_WAIT = 1;
   localparam STATE_START = 2;
   localparam STATE_SEND = 4;
   localparam STATE_PARITY = 8;
   localparam STATE_STOP = 16;
   localparam NUM_STATES = 5;

   input 	      clk;
   input [BITS - 1:0] data;
   input 	      data_ready;
   input 	      rst;
   output reg 	      data_sent; 	      
   output reg	      tx;

   reg [BITS - 1:0]   send_data;
   reg [NUM_STATES - 1:0] STATE;
   reg [$clog2(BITS + 1) - 1:0]        bits_sent;   
   reg [$clog2(BITLEN * STOPBITS + 1) - 1:0] 	  counter;
   
   always @ (posedge clk) begin
      if (rst) begin
	 STATE <= STATE_WAIT;
	 bits_sent <= 0;
	 send_data <= 0;
	 counter <= 0;
	 data_sent <= 0;
      end
      else begin
	 case (STATE)
	   STATE_WAIT: begin
	     if (data_ready) begin
		STATE <= STATE_START;
		data_sent <= 0;
		send_data <= data;
		counter <= 0;
	     end
	   end
	   STATE_START: begin
	      tx <= 0;
	      counter <= counter + 1;
	      if (counter == BITLEN - 1) begin
		 counter <= 0;
		 STATE <= STATE_SEND;
		 bits_sent <= 0;
	      end
	   end
	   STATE_SEND: begin
	      counter <= counter + 1;
	      tx <= send_data[bits_sent];
	      if (counter == BITLEN - 1) begin
		 counter <= 0;
		 bits_sent <= bits_sent + 1;
		 if (bits_sent == BITS - 1) begin
		    bits_sent <= 0;
		    STATE <= (PARITY == 0) ? STATE_STOP : STATE_PARITY;
		 end


	      end
	   end
	   STATE_PARITY: begin
	      counter <= counter + 1;
	      tx <= (PARITY == 1)? ~^send_data : ^send_data;
	      if (counter == BITLEN - 1) begin
		 counter <= 0;
		 STATE <= STATE_STOP;
	      end
	   end
	   STATE_STOP: begin
	      counter <= counter + 1;
	      tx <= 1;
	      if (counter == (BITLEN - 1) * STOPBITS) begin
		 STATE <= STATE_WAIT;
		 tx <= 1'bZ;
		 data_sent <= 1;
	      end
	   end
	 endcase
      end
   end

endmodule