data/full_repos/permissive/109936328/top/top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/top/top.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/top,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/top/top.v:2: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:3: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:14: Define or directive not defined: \'`WORD_W\'\n  output logic [`WORD_W - 1:0] peripheral\n                ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:16: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 1:0] instr_req_addr;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:17: Define or directive not defined: \'`INSTR_W\'\n  wire [`INSTR_W - 1:0] instr_res_data;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:19: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 1:0] mem_req_addr;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:20: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] mem_req_wr_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:22: Define or directive not defined: \'`MEM_COUNT_W\'\n  wire [`MEM_COUNT_W - 1:0] mem_req_count;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:24: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] mem_res_rd_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:25: Define or directive not defined: \'`MEM_CODE_W\'\n  wire [`MEM_CODE_W - 1:0] mem_res_code;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:60: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] dmem_req_addr;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:61: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] dmem_req_wr_data;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:63: Define or directive not defined: \'`MEM_COUNT_W\'\n  reg [`MEM_COUNT_W - 1:0] dmem_req_count;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:64: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] dmem_res_rd_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/top/top.v:65: Define or directive not defined: \'`MEM_CODE_W\'\n  wire [`MEM_CODE_W - 1:0] dmem_res_code;\n        ^~~~~~~~~~~\n%Error: Exiting due to 16 error(s)\n'
module top#(
  parameter INSTR_MAX = 100,
  parameter INSTR_FILE = "program.instr",
  parameter MEMORY_WORD_COUNT = 100
)(
  input clk,
  input reset,
  input aresetn,

  output logic [`WORD_W - 1:0] peripheral
);
  wire [`ADDR_W - 1:0] instr_req_addr;
  wire [`INSTR_W - 1:0] instr_res_data;

  wire [`ADDR_W - 1:0] mem_req_addr;
  wire [`WORD_W - 1:0] mem_req_wr_data;
  wire mem_req_wr_en;
  wire [`MEM_COUNT_W - 1:0] mem_req_count;

  wire [`WORD_W - 1:0] mem_res_rd_data;
  wire [`MEM_CODE_W - 1:0] mem_res_code;

  pipeline processor(
    .clk(clk),
    .reset(reset),
    .aresetn(aresetn),

    .o_instr_req_addr(instr_req_addr),
    .i_instr_res_data(instr_res_data),

    .o_mem_req_addr(mem_req_addr),
    .o_mem_req_wr_data(mem_req_wr_data),
    .o_mem_req_wr_en(mem_req_wr_en),
    .o_mem_req_count(mem_req_count),
    
    .i_mem_res_rd_data(mem_res_rd_data),
    .i_mem_res_code(mem_res_code)
  );

  dmem_bus#(
    .WORD_COUNT(MEMORY_WORD_COUNT),
    .PERIPH_ADDR({MEMORY_WORD_COUNT, 2'b00})
  ) dmem(
    .clk(clk),
    .aresetn(aresetn),

    .i_mem_req_addr(mem_req_addr),
    .i_mem_req_wr_data(mem_req_wr_data),
    .i_mem_req_wr_en(mem_req_wr_en),
    .i_mem_req_count(mem_req_count),

    .o_mem_res_rd_data(mem_res_rd_data),
    .o_mem_res_code(mem_res_code)
  );
  
  reg [`ADDR_W - 1:0] dmem_req_addr;
  reg [`WORD_W - 1:0] dmem_req_wr_data;
  reg dmem_req_wr_en;
  reg [`MEM_COUNT_W - 1:0] dmem_req_count;
  wire [`WORD_W - 1:0] dmem_res_rd_data;
  wire [`MEM_CODE_W - 1:0] dmem_res_code;

  instruction_memory#(
    .INSTR_MAX(INSTR_MAX),
    .INSTR_FILE(INSTR_FILE)
  ) imem(
    .clk(clk),

    .i_req_addr(instr_req_addr),

    .o_res_data(instr_res_data)
  );
endmodule
module top#(
  parameter INSTR_MAX = 100,
  parameter INSTR_FILE = "program.instr",
  parameter MEMORY_WORD_COUNT = 100
)(
  input clk,
  input reset,
  input aresetn,

  output logic [`WORD_W - 1:0] peripheral
);

  wire [`ADDR_W - 1:0] instr_req_addr;
  wire [`INSTR_W - 1:0] instr_res_data;

  wire [`ADDR_W - 1:0] mem_req_addr;
  wire [`WORD_W - 1:0] mem_req_wr_data;
  wire mem_req_wr_en;
  wire [`MEM_COUNT_W - 1:0] mem_req_count;

  wire [`WORD_W - 1:0] mem_res_rd_data;
  wire [`MEM_CODE_W - 1:0] mem_res_code;

  pipeline processor(
    .clk(clk),
    .reset(reset),
    .aresetn(aresetn),

    .o_instr_req_addr(instr_req_addr),
    .i_instr_res_data(instr_res_data),

    .o_mem_req_addr(mem_req_addr),
    .o_mem_req_wr_data(mem_req_wr_data),
    .o_mem_req_wr_en(mem_req_wr_en),
    .o_mem_req_count(mem_req_count),
    
    .i_mem_res_rd_data(mem_res_rd_data),
    .i_mem_res_code(mem_res_code)
  );

  dmem_bus#(
    .WORD_COUNT(MEMORY_WORD_COUNT),
    .PERIPH_ADDR({MEMORY_WORD_COUNT, 2'b00})
  ) dmem(
    .clk(clk),
    .aresetn(aresetn),

    .i_mem_req_addr(mem_req_addr),
    .i_mem_req_wr_data(mem_req_wr_data),
    .i_mem_req_wr_en(mem_req_wr_en),
    .i_mem_req_count(mem_req_count),

    .o_mem_res_rd_data(mem_res_rd_data),
    .o_mem_res_code(mem_res_code)
  );
  
  reg [`ADDR_W - 1:0] dmem_req_addr;
  reg [`WORD_W - 1:0] dmem_req_wr_data;
  reg dmem_req_wr_en;
  reg [`MEM_COUNT_W - 1:0] dmem_req_count;
  wire [`WORD_W - 1:0] dmem_res_rd_data;
  wire [`MEM_CODE_W - 1:0] dmem_res_code;

  instruction_memory#(
    .INSTR_MAX(INSTR_MAX),
    .INSTR_FILE(INSTR_FILE)
  ) imem(
    .clk(clk),

    .i_req_addr(instr_req_addr),

    .o_res_data(instr_res_data)
  );
endmodule