data/full_repos/permissive/129973551/work2/tb.sv
 line:45: before: ";"
1: b'%Error: data/full_repos/permissive/129973551/work2/tb.sv:26: syntax error, unexpected \'@\'\n  @(posedge rd_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129973551/work2/tb.sv:28: Unsupported: Ignoring delay on this delayed statement.\n  #((RD_CYCLE/2)-1);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/129973551/work2/tb.sv:29: Unsupported or unknown PLI call: $strobe\n  $strobe(data_out, empty, full);\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129973551/work2/tb.sv:46: Unsupported: Ignoring delay on this delayed statement.\n  #(WR_CYCLE*4.5);     \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129973551/work2/tb.sv:49: Unsupported: Ignoring delay on this delayed statement.\n  #(WR_CYCLE);  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129973551/work2/tb.sv:52: Unsupported: Ignoring delay on this delayed statement.\n  #(WR_CYCLE);  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129973551/work2/tb.sv:55: Unsupported: Ignoring delay on this delayed statement.\n  #(WR_CYCLE);  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129973551/work2/tb.sv:58: Unsupported: Ignoring delay on this delayed statement.\n  #(WR_CYCLE);  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129973551/work2/tb.sv:69: Unsupported: Ignoring delay on this delayed statement.\n  forever #(WR_CYCLE/2) wr_clk = ~wr_clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/129973551/work2/tb.sv:75: Unsupported: Ignoring delay on this delayed statement.\n  forever #(RD_CYCLE/2) rd_clk = ~rd_clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/129973551/work2/tb.sv:82: Unsupported: Ignoring delay on this delayed statement.\n    #(WR_CYCLE * 1.5) reset_n = 1\'b1;  \n    ^\n%Error: data/full_repos/permissive/129973551/work2/tb.sv:106: syntax error, unexpected \'@\'\n      @(negedge wr_clk);\n      ^\n%Error: data/full_repos/permissive/129973551/work2/tb.sv:111: syntax error, unexpected \'@\'\n      @(negedge wr_clk);\n      ^\n%Error: data/full_repos/permissive/129973551/work2/tb.sv:123: syntax error, unexpected \'@\'\n      @(negedge rd_clk);\n      ^\n%Error: data/full_repos/permissive/129973551/work2/tb.sv:128: syntax error, unexpected \'@\'\n      @(negedge rd_clk);\n      ^\n%Error: Exiting due to 6 error(s), 9 warning(s)\n'
module tb;

integer input_file, output_file, in, out;

integer i;

parameter WR_CYCLE = 20;
parameter RD_CYCLE = 30; 

reg rd_clk, wr_clk, reset_n;
reg wr, rd;
reg full, empty;
reg [7:0] data_in; 
reg [7:0] data_out;

initial begin

  while(1) begin
  @(posedge rd_clk);
  @(negedge rd_clk);
  #((RD_CYCLE/2)-1);
  $strobe(data_out, empty, full);
  end
end












initial begin
  initalize;
  #(WR_CYCLE*4.5);
  wrstim(8);
  rdstim(8);
  #(WR_CYCLE);
  wrstim(7);
  rdstim(7);
  #(WR_CYCLE);
  wrstim(6);
  rdstim(6);
  #(WR_CYCLE);
  wrstim(5);
  rdstim(5);
  #(WR_CYCLE);
  wrstim(4);
  rdstim(4);
  $fclose(input_file);
  $fclose(output_file);
  $finish;
end


initial begin
  wr_clk <= 0; rd_clk <= 0;
  forever #(WR_CYCLE/2) wr_clk = ~wr_clk;
end


initial begin
  rd_clk <= 0;
  forever #(RD_CYCLE/2) rd_clk = ~rd_clk;
end



initial begin
    reset_n <= 0;
    #(WR_CYCLE * 1.5) reset_n = 1'b1;
  end

fifo fifo_0(.*);

task initalize;
  begin
    wr=0;
    rd=0;
    data_in='x;
    input_file  = $fopen("input_data", "rb");
    if (input_file==0) begin 
      $display("ERROR : CAN NOT OPEN input_file"); 
    end
    output_file = $fopen("output_data", "wb");
    if (output_file==0) begin 
      $display("ERROR : CAN NOT OPEN output_file"); 
    end
  end
endtask

task wrstim (input [7:0] rep);
  begin
    for(i=0;i<rep;i++) begin
      @(negedge wr_clk);
      $fscanf(input_file,"%h",data_in);
      wr<=1'b1;


      @(negedge wr_clk);


      wr<=1'b0;
      data_in=8'bx;
  end
end
endtask

task rdstim(input [7:0] rep);
  begin
    for(i=0;i<rep;i++) begin
      @(negedge rd_clk);
      rd=1'b1;


      $fwrite(output_file,"%h\n",data_out);
      @(negedge rd_clk);

      rd=1'b0;
    end
  end
endtask

endmodule
module tb;


integer input_file, output_file, in, out;

integer i;

parameter WR_CYCLE = 20;
parameter RD_CYCLE = 30; 

reg rd_clk, wr_clk, reset_n;
reg wr, rd;
reg full, empty;
reg [7:0] data_in; 
reg [7:0] data_out;

initial begin

  while(1) begin
  @(posedge rd_clk);
  @(negedge rd_clk);
  #((RD_CYCLE/2)-1);
  $strobe(data_out, empty, full);
  end
end












initial begin
  initalize;
  #(WR_CYCLE*4.5);
  wrstim(8);
  rdstim(8);
  #(WR_CYCLE);
  wrstim(7);
  rdstim(7);
  #(WR_CYCLE);
  wrstim(6);
  rdstim(6);
  #(WR_CYCLE);
  wrstim(5);
  rdstim(5);
  #(WR_CYCLE);
  wrstim(4);
  rdstim(4);
  $fclose(input_file);
  $fclose(output_file);
  $finish;
end


initial begin
  wr_clk <= 0; rd_clk <= 0;
  forever #(WR_CYCLE/2) wr_clk = ~wr_clk;
end


initial begin
  rd_clk <= 0;
  forever #(RD_CYCLE/2) rd_clk = ~rd_clk;
end



initial begin
    reset_n <= 0;
    #(WR_CYCLE * 1.5) reset_n = 1'b1;
  end

fifo fifo_0(.*);

task initalize;
  begin
    wr=0;
    rd=0;
    data_in='x;
    input_file  = $fopen("input_data", "rb");
    if (input_file==0) begin 
      $display("ERROR : CAN NOT OPEN input_file"); 
    end
    output_file = $fopen("output_data", "wb");
    if (output_file==0) begin 
      $display("ERROR : CAN NOT OPEN output_file"); 
    end
  end
endtask

task wrstim (input [7:0] rep);
  begin
    for(i=0;i<rep;i++) begin
      @(negedge wr_clk);
      $fscanf(input_file,"%h",data_in);
      wr<=1'b1;


      @(negedge wr_clk);


      wr<=1'b0;
      data_in=8'bx;
  end
end
endtask

task rdstim(input [7:0] rep);
  begin
    for(i=0;i<rep;i++) begin
      @(negedge rd_clk);
      rd=1'b1;


      $fwrite(output_file,"%h\n",data_out);
      @(negedge rd_clk);

      rd=1'b0;
    end
  end
endtask

endmodule