data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:8: Define or directive not defined: \'`AluOpWidth\'\n  input wire[`AluOpWidth-1:0] aluop_i,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:9: Define or directive not defined: \'`AluSelWidth\'\n  input wire[`AluSelWidth-1:0] alusel_i,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:10: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] reg1_i,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:11: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] reg2_i,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:12: Define or directive not defined: \'`RegAddrWidth\'\n  input wire[`RegAddrWidth-1:0] wd_i,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:14: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] addr_base,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:15: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] addr_off,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:22: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] wdata_o, \n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:23: Define or directive not defined: \'`RegAddrWidth\'\n  output reg[`RegAddrWidth-1:0] wd_o,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:25: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] addr_o,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:30: Define or directive not defined: \'`RegDataWidth\'\n reg[`RegDataWidth-1:0] logicout;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:31: Define or directive not defined: \'`RegDataWidth\'\n reg[`RegDataWidth-1:0] arithout;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:32: Define or directive not defined: \'`RegDataWidth\'\n reg[`RegDataWidth-1:0] shiftout;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:34: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] reg2_comp;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:35: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] sub_res;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:36: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] sum_res;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:42: Define or directive not defined: \'`EXE_SLT_OP\'\n assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP || aluop_i == `EXE_SGE_OP ?\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:42: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP || aluop_i == `EXE_SGE_OP ?\n                                               ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:42: Define or directive not defined: \'`EXE_SGE_OP\'\n assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP || aluop_i == `EXE_SGE_OP ?\n                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:52: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (rst == `RstEnable) begin\n                       ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:53: Define or directive not defined: \'`ZeroWord\'\n   addr_o <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:54: Define or directive not defined: \'`NoJump\'\n  end else if (jump_type_i != `NoJump || memop_o != `MEM_NOP) begin\n                              ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:54: Define or directive not defined: \'`MEM_NOP\'\n  end else if (jump_type_i != `NoJump || memop_o != `MEM_NOP) begin\n                                                    ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:57: Define or directive not defined: \'`ZeroWord\'\n   addr_o <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:64: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:65: Define or directive not defined: \'`ZeroWord\'\n   logicout <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:66: Define or directive not defined: \'`ZeroWord\'\n   arithout <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:67: Define or directive not defined: \'`ZeroWord\'\n   shiftout <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:69: Define or directive not defined: \'`ZeroWord\'\n   logicout <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:70: Define or directive not defined: \'`ZeroWord\'\n   arithout <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:71: Define or directive not defined: \'`ZeroWord\'\n   shiftout <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:73: Define or directive not defined: \'`EXE_ADD_OP\'\n    `EXE_ADD_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:73: syntax error, unexpected \':\', expecting endcase\n    `EXE_ADD_OP: begin\n               ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:76: Define or directive not defined: \'`EXE_SUB_OP\'\n    `EXE_SUB_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:79: Define or directive not defined: \'`EXE_SLT_OP\'\n    `EXE_SLT_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:82: Define or directive not defined: \'`EXE_SLTU_OP\'\n    `EXE_SLTU_OP: begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:85: Define or directive not defined: \'`EXE_XOR_OP\'\n    `EXE_XOR_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:88: Define or directive not defined: \'`EXE_OR_OP\'\n    `EXE_OR_OP: begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:91: Define or directive not defined: \'`EXE_AND_OP\'\n    `EXE_AND_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:94: Define or directive not defined: \'`EXE_SLL_OP\'\n    `EXE_SLL_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:97: Define or directive not defined: \'`EXE_SRL_OP\'\n    `EXE_SRL_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:100: Define or directive not defined: \'`EXE_SRA_OP\'\n    `EXE_SRA_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:104: Define or directive not defined: \'`EXE_SEQ_OP\'\n    `EXE_SEQ_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:107: Define or directive not defined: \'`EXE_SNE_OP\'\n    `EXE_SNE_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:110: Define or directive not defined: \'`EXE_SGE_OP\'\n    `EXE_SGE_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:113: Define or directive not defined: \'`EXE_SGEU_OP\'\n    `EXE_SGEU_OP: begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:128: Define or directive not defined: \'`EXE_LOGIC_RES\'\n   `EXE_LOGIC_RES: begin\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:128: syntax error, unexpected \':\', expecting endcase\n   `EXE_LOGIC_RES: begin\n                 ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ex(
		input wire rst,
		

		input wire[`AluOpWidth-1:0] aluop_i,
		input wire[`AluSelWidth-1:0] alusel_i,
		input wire[`RegDataWidth-1:0] reg1_i,
		input wire[`RegDataWidth-1:0] reg2_i,
		input wire[`RegAddrWidth-1:0] wd_i,
		input wire wreg_i,
		input wire[`RegDataWidth-1:0] addr_base,
		input wire[`RegDataWidth-1:0] addr_off,
		input wire[1:0] jump_type_i,
		input wire[1:0] memop_i,
		input wire[2:0] memfunct_i,
		


		output reg[`RegDataWidth-1:0] wdata_o,	
		output reg[`RegAddrWidth-1:0] wd_o,
		output reg wreg_o,
		output reg[`RegDataWidth-1:0] addr_o,
		output reg[1:0] memop_o,
		output reg[2:0] memfunct_o
	);
	
	reg[`RegDataWidth-1:0] logicout;
	reg[`RegDataWidth-1:0] arithout;
	reg[`RegDataWidth-1:0] shiftout;

	wire[`RegDataWidth-1:0] reg2_comp;
	wire[`RegDataWidth-1:0] sub_res;
	wire[`RegDataWidth-1:0] sum_res;
	wire reg1_eq_reg2;
	wire reg1_lt_reg2;

	assign sub_res = reg1_i + (~reg2_i) + 1;
	assign reg1_eq_reg2 = (reg1_i == reg2_i);
	assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP || aluop_i == `EXE_SGE_OP ?
					(   (reg1_i[31] && !reg2_i[31]) 
					 || (reg1_i[31] && reg2_i[31] && sub_res[31])
					 || (!reg1_i[31] && !reg2_i[31] && sub_res[31])
					) : (reg1_i < reg2_i));



	always @ (*) 
	begin
		if (rst == `RstEnable) begin
			addr_o <= `ZeroWord;
		end else if (jump_type_i != `NoJump || memop_o != `MEM_NOP) begin
			addr_o <= addr_base + addr_off;
		end else begin
			addr_o <= `ZeroWord;
		end
	end


	always @ (*) 
	begin
		if (rst == `RstEnable) begin
			logicout <= `ZeroWord;
			arithout <= `ZeroWord;
			shiftout <= `ZeroWord;
		end else begin
			logicout <= `ZeroWord;
			arithout <= `ZeroWord;
			shiftout <= `ZeroWord;
			case (aluop_i)
				`EXE_ADD_OP: begin
					arithout <= reg1_i + reg2_i;
				end
				`EXE_SUB_OP: begin
					arithout <= sub_res;
				end
				`EXE_SLT_OP: begin
					arithout <= {31'b0, reg1_lt_reg2};
				end
				`EXE_SLTU_OP: begin
					arithout <= {31'b0, reg1_lt_reg2};
				end
				`EXE_XOR_OP: begin
					logicout <= reg1_i ^ reg2_i;
				end
				`EXE_OR_OP: begin
					logicout <= reg1_i | reg2_i;
				end
				`EXE_AND_OP: begin
					logicout <= reg1_i & reg2_i;
				end
				`EXE_SLL_OP: begin
					shiftout <= reg1_i << reg2_i[4:0];
				end
				`EXE_SRL_OP: begin
					shiftout <= reg1_i >> reg2_i[4:0];
				end
				`EXE_SRA_OP: begin
					shiftout <= (reg1_i >> reg2_i[4:0])
							  | ({32{reg1_i[31]}} << (6'd32 - {1'b0, reg2_i[4:0]}));
				end
				`EXE_SEQ_OP: begin
					arithout <= {31'b0, reg1_eq_reg2};
				end
				`EXE_SNE_OP: begin
					arithout <= {31'b0, !reg1_eq_reg2};
				end
				`EXE_SGE_OP: begin
					arithout <= {31'b0, !reg1_lt_reg2};
				end
				`EXE_SGEU_OP: begin
					arithout <= {31'b0, !reg1_lt_reg2};
				end
			endcase
		end
	end
	

	always @ (*)
	begin
		wd_o <= wd_i;
		wreg_o <= wreg_i;
		memop_o <= memop_i;
		memfunct_o <= memfunct_i;
		case (alusel_i)
			`EXE_LOGIC_RES: begin
				wdata_o <= logicout;
			end 
			`EXE_ARITH_RES: begin
				wdata_o <= arithout;
			end
			`EXE_SHIFT_RES: begin
				wdata_o <= shiftout;
			end
			default: begin
				wdata_o <= `ZeroWord;
			end
		endcase
	end
	
endmodule
module ex(
		input wire rst,
		

		input wire[`AluOpWidth-1:0] aluop_i,
		input wire[`AluSelWidth-1:0] alusel_i,
		input wire[`RegDataWidth-1:0] reg1_i,
		input wire[`RegDataWidth-1:0] reg2_i,
		input wire[`RegAddrWidth-1:0] wd_i,
		input wire wreg_i,
		input wire[`RegDataWidth-1:0] addr_base,
		input wire[`RegDataWidth-1:0] addr_off,
		input wire[1:0] jump_type_i,
		input wire[1:0] memop_i,
		input wire[2:0] memfunct_i,
		


		output reg[`RegDataWidth-1:0] wdata_o,	
		output reg[`RegAddrWidth-1:0] wd_o,
		output reg wreg_o,
		output reg[`RegDataWidth-1:0] addr_o,
		output reg[1:0] memop_o,
		output reg[2:0] memfunct_o
	);

	
	reg[`RegDataWidth-1:0] logicout;
	reg[`RegDataWidth-1:0] arithout;
	reg[`RegDataWidth-1:0] shiftout;

	wire[`RegDataWidth-1:0] reg2_comp;
	wire[`RegDataWidth-1:0] sub_res;
	wire[`RegDataWidth-1:0] sum_res;
	wire reg1_eq_reg2;
	wire reg1_lt_reg2;

	assign sub_res = reg1_i + (~reg2_i) + 1;
	assign reg1_eq_reg2 = (reg1_i == reg2_i);
	assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP || aluop_i == `EXE_SGE_OP ?
					(   (reg1_i[31] && !reg2_i[31]) 
					 || (reg1_i[31] && reg2_i[31] && sub_res[31])
					 || (!reg1_i[31] && !reg2_i[31] && sub_res[31])
					) : (reg1_i < reg2_i));



	always @ (*) 
	begin
		if (rst == `RstEnable) begin
			addr_o <= `ZeroWord;
		end else if (jump_type_i != `NoJump || memop_o != `MEM_NOP) begin
			addr_o <= addr_base + addr_off;
		end else begin
			addr_o <= `ZeroWord;
		end
	end


	always @ (*) 
	begin
		if (rst == `RstEnable) begin
			logicout <= `ZeroWord;
			arithout <= `ZeroWord;
			shiftout <= `ZeroWord;
		end else begin
			logicout <= `ZeroWord;
			arithout <= `ZeroWord;
			shiftout <= `ZeroWord;
			case (aluop_i)
				`EXE_ADD_OP: begin
					arithout <= reg1_i + reg2_i;
				end
				`EXE_SUB_OP: begin
					arithout <= sub_res;
				end
				`EXE_SLT_OP: begin
					arithout <= {31'b0, reg1_lt_reg2};
				end
				`EXE_SLTU_OP: begin
					arithout <= {31'b0, reg1_lt_reg2};
				end
				`EXE_XOR_OP: begin
					logicout <= reg1_i ^ reg2_i;
				end
				`EXE_OR_OP: begin
					logicout <= reg1_i | reg2_i;
				end
				`EXE_AND_OP: begin
					logicout <= reg1_i & reg2_i;
				end
				`EXE_SLL_OP: begin
					shiftout <= reg1_i << reg2_i[4:0];
				end
				`EXE_SRL_OP: begin
					shiftout <= reg1_i >> reg2_i[4:0];
				end
				`EXE_SRA_OP: begin
					shiftout <= (reg1_i >> reg2_i[4:0])
							  | ({32{reg1_i[31]}} << (6'd32 - {1'b0, reg2_i[4:0]}));
				end
				`EXE_SEQ_OP: begin
					arithout <= {31'b0, reg1_eq_reg2};
				end
				`EXE_SNE_OP: begin
					arithout <= {31'b0, !reg1_eq_reg2};
				end
				`EXE_SGE_OP: begin
					arithout <= {31'b0, !reg1_lt_reg2};
				end
				`EXE_SGEU_OP: begin
					arithout <= {31'b0, !reg1_lt_reg2};
				end
			endcase
		end
	end
	

	always @ (*)
	begin
		wd_o <= wd_i;
		wreg_o <= wreg_i;
		memop_o <= memop_i;
		memfunct_o <= memfunct_i;
		case (alusel_i)
			`EXE_LOGIC_RES: begin
				wdata_o <= logicout;
			end 
			`EXE_ARITH_RES: begin
				wdata_o <= arithout;
			end
			`EXE_SHIFT_RES: begin
				wdata_o <= shiftout;
			end
			default: begin
				wdata_o <= `ZeroWord;
			end
		endcase
	end
	
endmodule