data/full_repos/permissive/119387855/mips_is_branch_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_is_branch_testbench.v:10: Unsupported: Ignoring delay on this delayed statement.\n #10 branch = 2\'b00; zero = 1\'b0; \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_is_branch_testbench.v:11: Unsupported: Ignoring delay on this delayed statement.\n #10 branch = 2\'b00; zero = 1\'b1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_is_branch_testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n #10 branch = 2\'b01; zero = 1\'b0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_is_branch_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n #10 branch = 2\'b01; zero = 1\'b1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_is_branch_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10 branch = 2\'b10; zero = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_is_branch_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10 branch = 2\'b10; zero = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_is_branch_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n #10 branch = 2\'b11; zero = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_is_branch_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10 branch = 2\'b11; zero = 1\'b1;\n ^\n%Error: data/full_repos/permissive/119387855/mips_is_branch_testbench.v:23: Unsupported or unknown PLI call: $monitor\n $monitor("branch: %b, zero: %b, is_branch %b",branch, zero, is_branch);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_is_branch_testbench();
	
	wire is_branch;
	reg [1:0] branch;
	reg zero;
	
	mips_is_branch is(is_branch, branch, zero);
	
	initial begin
	#10 branch = 2'b00; zero = 1'b0; 
	#10 branch = 2'b00; zero = 1'b1; 
	#10 branch = 2'b01; zero = 1'b0; 
	#10 branch = 2'b01; zero = 1'b1; 
	#10 branch = 2'b10; zero = 1'b0;
	#10 branch = 2'b10; zero = 1'b1;
	#10 branch = 2'b11; zero = 1'b0;
	#10 branch = 2'b11; zero = 1'b1;
	
		
end

initial begin
	$monitor("branch: %b, zero: %b, is_branch %b",branch, zero, is_branch);
end
	
endmodule
module mips_is_branch_testbench();

	
	wire is_branch;
	reg [1:0] branch;
	reg zero;
	
	mips_is_branch is(is_branch, branch, zero);
	
	initial begin
	#10 branch = 2'b00; zero = 1'b0; 
	#10 branch = 2'b00; zero = 1'b1; 
	#10 branch = 2'b01; zero = 1'b0; 
	#10 branch = 2'b01; zero = 1'b1; 
	#10 branch = 2'b10; zero = 1'b0;
	#10 branch = 2'b10; zero = 1'b1;
	#10 branch = 2'b11; zero = 1'b0;
	#10 branch = 2'b11; zero = 1'b1;
	
		
end

initial begin
	$monitor("branch: %b, zero: %b, is_branch %b",branch, zero, is_branch);
end
	
endmodule