data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu_testbench.v
 line:51: before: "$"
1: b'%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu_testbench.v:14: Unsupported or unknown PLI call: $monitor\n    $monitor(x, y, alu_ctrl, result, zero);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/alu_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_testbench;

reg [31:0]x;
reg [31:0]y;
reg [3:0] alu_ctrl;
wire [31:0] result;
wire zero;

alu uut(.x(x), .y(y), .alu_ctrl(alu_ctrl), .result(result), .zero(zero));

initial begin
    $monitor(x, y, alu_ctrl, result, zero);
    

    x=32'd100;
    y=32'd20;
    

    alu_ctrl=4'b0000;
    #5

    alu_ctrl=4'b0001;
    #5

    alu_ctrl=4'b0010;
    #5

    alu_ctrl=4'b0110;
    #5

    alu_ctrl=4'b0011;
    #5

    alu_ctrl=4'b1000;
    #5

    alu_ctrl=4'b1001;
    #5

    alu_ctrl=4'b0111;
    #5
    





    
    $finish;
    end
endmodule
module alu_testbench;


reg [31:0]x;
reg [31:0]y;
reg [3:0] alu_ctrl;
wire [31:0] result;
wire zero;

alu uut(.x(x), .y(y), .alu_ctrl(alu_ctrl), .result(result), .zero(zero));

initial begin
    $monitor(x, y, alu_ctrl, result, zero);
    

    x=32'd100;
    y=32'd20;
    

    alu_ctrl=4'b0000;
    #5

    alu_ctrl=4'b0001;
    #5

    alu_ctrl=4'b0010;
    #5

    alu_ctrl=4'b0110;
    #5

    alu_ctrl=4'b0011;
    #5

    alu_ctrl=4'b1000;
    #5

    alu_ctrl=4'b1001;
    #5

    alu_ctrl=4'b0111;
    #5
    





    
    $finish;
    end
endmodule