data/full_repos/permissive/183345139/serial_fpga/serial_fpga.v
1: b'%Error: data/full_repos/permissive/183345139/serial_fpga/serial_fpga.v:139: Cannot find file containing module: \'buart\'\nbuart # (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/183345139/serial_fpga,data/full_repos/permissive/183345139/buart\n             data/full_repos/permissive/183345139/serial_fpga,data/full_repos/permissive/183345139/buart.v\n             data/full_repos/permissive/183345139/serial_fpga,data/full_repos/permissive/183345139/buart.sv\n             buart\n             buart.v\n             buart.sv\n             obj_dir/buart\n             obj_dir/buart.v\n             obj_dir/buart.sv\n%Error: data/full_repos/permissive/183345139/serial_fpga/serial_fpga.v:158: Cannot find file containing module: \'send_recv\'\nsend_recv send_recv_inst\n^~~~~~~~~\n%Error: data/full_repos/permissive/183345139/serial_fpga/serial_fpga.v:181: Cannot find file containing module: \'hba_master\'\nhba_master #\n^~~~~~~~~~\n%Error: data/full_repos/permissive/183345139/serial_fpga/serial_fpga.v:210: Cannot find file containing module: \'hba_reg_bank\'\nhba_reg_bank #\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/183345139/serial_fpga/serial_fpga.v:453: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'count_to_1ms\' generates 16 bits.\n                                                                                  : ... In instance serial_fpga\n        if (count_to_1ms == (ONE_MS_COUNT-1)) begin\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module serial_fpga #
(
    parameter integer CLK_FREQUENCY = 50_000_000,
    parameter integer BAUD = 32'd115_200,

    parameter integer DBUS_WIDTH = 8,
    parameter integer PERIPH_ADDR_WIDTH = 4,
    parameter integer REG_ADDR_WIDTH = 8,
    parameter integer PERIPH_ADDR = 0,

    parameter integer ADDR_WIDTH = PERIPH_ADDR_WIDTH + REG_ADDR_WIDTH
)
(

    input wire  io_rxd,
    output wire io_txd,
    output reg  io_intr,


    input wire [15:0] slave_interrupt,


    input wire hba_clk,
    input wire hba_reset,
    input wire hba_rnw,
    input wire hba_select,
    input wire [ADDR_WIDTH-1:0] hba_abus,
    input wire [DBUS_WIDTH-1:0] hba_dbus,

    output wire [DBUS_WIDTH-1:0] hba_dbus_slave,
    output wire hba_xferack_slave,






    input wire hba_xferack,
    input wire hba_mgrant,
    output wire hba_mrequest,
    output wire [ADDR_WIDTH-1:0] hba_abus_master,
    output wire hba_rnw_master,
    output wire hba_select_master,
    output wire [DBUS_WIDTH-1:0] hba_dbus_master

);



wire uart0_rd;
wire uart0_wr;
wire [7:0] tx_data;

wire rx_valid;
wire tx_busy;
wire [7:0] rx_data;


reg [PERIPH_ADDR_WIDTH-1:0] app_core_addr;
reg [REG_ADDR_WIDTH-1:0] app_reg_addr;
reg [DBUS_WIDTH-1:0] app_data_in;
reg app_rnw;
reg app_en_strobe;
wire [DBUS_WIDTH-1:0] app_data_out;
wire app_valid_out;


reg [7:0] serial_tx_data;
reg serial_wr;
reg serial_rd;
wire serial_valid;
wire [7:0] serial_rx_data;


reg slv_wr_en;


wire [DBUS_WIDTH-1:0] reg_intr0;
reg [DBUS_WIDTH-1:0] reg_intr0_in;


wire [DBUS_WIDTH-1:0] reg_intr1;
reg [DBUS_WIDTH-1:0] reg_intr1_in;

wire [DBUS_WIDTH-1:0] reg_rate_ms;



buart # (
    .CLKFREQ(CLK_FREQUENCY)
) uart_inst (

   .clk(hba_clk),
   .resetq(~hba_reset),
   .baud(BAUD),
   .rx(io_rxd),
   .rd(uart0_rd),
   .wr(uart0_wr),
   .tx_data(tx_data),


   .tx(io_txd),
   .valid(rx_valid),
   .busy(tx_busy),
   .rx_data(rx_data)
);

send_recv send_recv_inst
(
    .clk(hba_clk),
    .reset(hba_reset),


    .serial_tx_data(serial_tx_data),
    .serial_wr(serial_wr),
    .serial_rd(serial_rd),
    .serial_valid(serial_valid),
    .serial_rx_data(serial_rx_data),


    .tx_data(tx_data),
    .tx_wr_strobe(uart0_wr),
    .tx_busy(tx_busy),


    .rx_data(rx_data),
    .rx_valid(rx_valid),
    .rx_rd_strobe(uart0_rd)
);

hba_master #
(
    .DBUS_WIDTH(DBUS_WIDTH),
    .PERIPH_ADDR_WIDTH(PERIPH_ADDR_WIDTH),
    .REG_ADDR_WIDTH(REG_ADDR_WIDTH)
) hba_master_inst
(

    .app_core_addr(app_core_addr),
    .app_reg_addr(app_reg_addr),
    .app_data_in(app_data_in),
    .app_rnw(app_rnw),
    .app_en_strobe(app_en_strobe),
    .app_data_out(app_data_out),
    .app_valid_out(app_valid_out),


    .hba_clk(hba_clk),
    .hba_reset(hba_reset),
    .hba_mgrant(hba_mgrant),
    .hba_xferack(hba_xferack),
    .hba_dbus(hba_dbus),
    .hba_mrequest(hba_mrequest),
    .hba_abus_master(hba_abus_master),
    .hba_rnw_master(hba_rnw_master),
    .hba_select_master(hba_select_master),
    .hba_dbus_master(hba_dbus_master)
);

hba_reg_bank #
(
    .DBUS_WIDTH(DBUS_WIDTH),
    .PERIPH_ADDR_WIDTH(PERIPH_ADDR_WIDTH),
    .REG_ADDR_WIDTH(REG_ADDR_WIDTH),
    .PERIPH_ADDR(PERIPH_ADDR)
) hba_reg_bank_inst
(

    .hba_clk(hba_clk),
    .hba_reset(hba_reset),
    .hba_rnw(hba_rnw),
    .hba_select(hba_select),
    .hba_abus(hba_abus),
    .hba_dbus(hba_dbus),

    .hba_dbus_slave(hba_dbus_slave),
    .hba_xferack_slave(hba_xferack_slave),




    .slv_reg0(reg_intr0),
    .slv_reg0_in(reg_intr0_in),

    .slv_reg1(reg_intr1),
    .slv_reg1_in(reg_intr1_in),

    .slv_reg2(reg_rate_ms),

    .slv_wr_en(slv_wr_en),
    .slv_wr_mask(4'b011),
    .slv_autoclr_mask(4'b011)
);





reg [3:0] serial_state;

reg [7:0] cmd_byte;
reg [7:0] regaddr_byte;
reg [3:0] transfer_num;

wire rnw_bit;
wire [2:0] num_bytes_bits;
wire [3:0] core_addr_bits;

assign rnw_bit = cmd_byte[7];
assign num_bytes_bits = cmd_byte[6:4];
assign core_addr_bits = cmd_byte[3:0];


localparam IDLE                     = 0;
localparam REG_ADDR                 = 1;
localparam ECHO_CMD                 = 2;
localparam ECHO_RAD                 = 3;
localparam HBA_SETUP                = 4;
localparam HBA_SERIAL_READ          = 5;
localparam HBA_WAIT                 = 6;
localparam HBA_WAIT2                = 7;
localparam ACK                      = 8;
localparam DONE                     = 9;


localparam RPI_WRITE            = 0;
localparam RPI_READ             = 1;


localparam ACK_CHAR         =8'hAC;
localparam NACK_CHAR        =8'h56;

always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        serial_state <= IDLE;
        cmd_byte <= 0;
        regaddr_byte <= 0;
        transfer_num <= 0;

        app_core_addr <= 0;
        app_reg_addr <= 0;
        app_data_in <= 0;
        app_rnw <= 0;
        app_en_strobe <= 0;

        serial_tx_data <= 0;
        serial_wr <= 0;
        serial_rd <= 0;

    end else begin
        case (serial_state)
            IDLE : begin
                serial_wr <= 0;
                transfer_num <= 0;
                app_en_strobe <= 0;


                serial_rd <= 1;
                if (serial_valid) begin
                    serial_rd <= 0;
                    cmd_byte <= serial_rx_data;
                    serial_state <= REG_ADDR;
                end
            end
            REG_ADDR : begin

                serial_rd <= 1;
                if (serial_valid) begin
                    serial_rd <= 0;
                    transfer_num <= num_bytes_bits + 1;
                    regaddr_byte <= serial_rx_data;
                    if (rnw_bit == RPI_READ) begin
                        serial_state <= ECHO_CMD;
                    end else begin
                        serial_state <= HBA_SETUP;
                    end
                end
            end
            ECHO_CMD : begin

                serial_tx_data <= cmd_byte;
                serial_wr <= 1;
                if (serial_valid) begin
                    serial_wr <= 0;
                    serial_state <= ECHO_RAD;
                end
            end
            ECHO_RAD : begin

                serial_tx_data <= regaddr_byte;
                serial_wr <= 1;
                if (serial_valid) begin
                    serial_wr <= 0;
                    serial_state <= HBA_SETUP;
                end
            end
            HBA_SETUP : begin
                serial_wr <= 0;

                app_en_strobe <= 0;


                if (transfer_num == 0) begin
                    if (rnw_bit == RPI_READ) begin
                        serial_state <= DONE;
                    end else begin

                        serial_state <= ACK;
                    end
                end else begin

                    transfer_num <= transfer_num - 1;


                    app_core_addr <= core_addr_bits;
                    app_reg_addr <= regaddr_byte;
                    app_rnw <= rnw_bit;


                    regaddr_byte <= regaddr_byte + 1;


                    if (rnw_bit == RPI_WRITE) begin

                        serial_rd <= 1;
                        serial_state <= HBA_SERIAL_READ;
                    end else begin

                        app_en_strobe <= 1;
                        serial_state <= HBA_WAIT;
                    end
                end

            end
            HBA_SERIAL_READ : begin
                if (serial_valid) begin
                    serial_rd <= 0;
                    app_data_in <= serial_rx_data;
                    app_en_strobe <= 1;
                    serial_state <= HBA_WAIT;
                end
            end
            HBA_WAIT : begin
                app_en_strobe <= 0;

                if (app_valid_out) begin
                    if (rnw_bit == RPI_WRITE) begin
                        serial_state <= HBA_SETUP;
                    end else begin

                        serial_tx_data <= app_data_out;
                        serial_wr <= 1;
                        serial_state <= HBA_WAIT2;
                    end
                end
            end
            HBA_WAIT2 : begin
                if (serial_valid) begin
                    serial_wr <= 0;
                    serial_state <= HBA_SETUP;
                end
            end
            ACK : begin
                serial_tx_data <= ACK_CHAR;
                serial_wr <= 1;
                if (serial_valid) begin
                    serial_wr <= 0;
                    serial_state <= DONE;
                end
            end
            DONE : begin
                if (!serial_valid) begin
                    serial_state <= IDLE;
                end
            end
            default : begin
                serial_state <= IDLE;
            end
        endcase
    end
end


localparam ONE_MS_COUNT = ( CLK_FREQUENCY / 1000 );
localparam COUNT_BITS = $clog2(ONE_MS_COUNT);
reg [COUNT_BITS-1:0] count_to_1ms;
reg [7:0] count_1ms;
reg io_intr_en;
always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        count_to_1ms <= 0;
        count_1ms <= 0;
        io_intr_en <= 0;
    end else begin
        io_intr_en <= 0;
        count_to_1ms <= count_to_1ms + 1;
        if (count_to_1ms == (ONE_MS_COUNT-1)) begin
            count_to_1ms <= 0;
            count_1ms <= count_1ms + 1;
        end
        if (count_1ms == reg_rate_ms) begin
            count_1ms <= 0;
            io_intr_en <= 1;
        end
    end
end


integer i;
always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        slv_wr_en <= 0;
        reg_intr0_in <= 0;
        reg_intr1_in <= 0;
        io_intr <= 0;
    end else begin

        if (io_intr == 0) begin
            if (io_intr_en) begin
                io_intr <= (|reg_intr0) | (|reg_intr1);
            end
        end else begin

            io_intr <= (|reg_intr0) | (|reg_intr1);
        end


        slv_wr_en <= 0;

        for (i=0; i <8; i=i+1)
        begin
            if (slave_interrupt[i]) begin
                reg_intr0_in[i] <= 1'b1;
                slv_wr_en <= 1;
            end
            if (slave_interrupt[i+8]) begin
                reg_intr1_in[i] <= 1'b1;
                slv_wr_en <= 1;
            end
        end
    end
end

endmodule
module serial_fpga #
(
    parameter integer CLK_FREQUENCY = 50_000_000,
    parameter integer BAUD = 32'd115_200,

    parameter integer DBUS_WIDTH = 8,
    parameter integer PERIPH_ADDR_WIDTH = 4,
    parameter integer REG_ADDR_WIDTH = 8,
    parameter integer PERIPH_ADDR = 0,

    parameter integer ADDR_WIDTH = PERIPH_ADDR_WIDTH + REG_ADDR_WIDTH
)
(

    input wire  io_rxd,
    output wire io_txd,
    output reg  io_intr,


    input wire [15:0] slave_interrupt,


    input wire hba_clk,
    input wire hba_reset,
    input wire hba_rnw,
    input wire hba_select,
    input wire [ADDR_WIDTH-1:0] hba_abus,
    input wire [DBUS_WIDTH-1:0] hba_dbus,

    output wire [DBUS_WIDTH-1:0] hba_dbus_slave,
    output wire hba_xferack_slave,






    input wire hba_xferack,
    input wire hba_mgrant,
    output wire hba_mrequest,
    output wire [ADDR_WIDTH-1:0] hba_abus_master,
    output wire hba_rnw_master,
    output wire hba_select_master,
    output wire [DBUS_WIDTH-1:0] hba_dbus_master

);




wire uart0_rd;
wire uart0_wr;
wire [7:0] tx_data;

wire rx_valid;
wire tx_busy;
wire [7:0] rx_data;


reg [PERIPH_ADDR_WIDTH-1:0] app_core_addr;
reg [REG_ADDR_WIDTH-1:0] app_reg_addr;
reg [DBUS_WIDTH-1:0] app_data_in;
reg app_rnw;
reg app_en_strobe;
wire [DBUS_WIDTH-1:0] app_data_out;
wire app_valid_out;


reg [7:0] serial_tx_data;
reg serial_wr;
reg serial_rd;
wire serial_valid;
wire [7:0] serial_rx_data;


reg slv_wr_en;


wire [DBUS_WIDTH-1:0] reg_intr0;
reg [DBUS_WIDTH-1:0] reg_intr0_in;


wire [DBUS_WIDTH-1:0] reg_intr1;
reg [DBUS_WIDTH-1:0] reg_intr1_in;

wire [DBUS_WIDTH-1:0] reg_rate_ms;



buart # (
    .CLKFREQ(CLK_FREQUENCY)
) uart_inst (

   .clk(hba_clk),
   .resetq(~hba_reset),
   .baud(BAUD),
   .rx(io_rxd),
   .rd(uart0_rd),
   .wr(uart0_wr),
   .tx_data(tx_data),


   .tx(io_txd),
   .valid(rx_valid),
   .busy(tx_busy),
   .rx_data(rx_data)
);

send_recv send_recv_inst
(
    .clk(hba_clk),
    .reset(hba_reset),


    .serial_tx_data(serial_tx_data),
    .serial_wr(serial_wr),
    .serial_rd(serial_rd),
    .serial_valid(serial_valid),
    .serial_rx_data(serial_rx_data),


    .tx_data(tx_data),
    .tx_wr_strobe(uart0_wr),
    .tx_busy(tx_busy),


    .rx_data(rx_data),
    .rx_valid(rx_valid),
    .rx_rd_strobe(uart0_rd)
);

hba_master #
(
    .DBUS_WIDTH(DBUS_WIDTH),
    .PERIPH_ADDR_WIDTH(PERIPH_ADDR_WIDTH),
    .REG_ADDR_WIDTH(REG_ADDR_WIDTH)
) hba_master_inst
(

    .app_core_addr(app_core_addr),
    .app_reg_addr(app_reg_addr),
    .app_data_in(app_data_in),
    .app_rnw(app_rnw),
    .app_en_strobe(app_en_strobe),
    .app_data_out(app_data_out),
    .app_valid_out(app_valid_out),


    .hba_clk(hba_clk),
    .hba_reset(hba_reset),
    .hba_mgrant(hba_mgrant),
    .hba_xferack(hba_xferack),
    .hba_dbus(hba_dbus),
    .hba_mrequest(hba_mrequest),
    .hba_abus_master(hba_abus_master),
    .hba_rnw_master(hba_rnw_master),
    .hba_select_master(hba_select_master),
    .hba_dbus_master(hba_dbus_master)
);

hba_reg_bank #
(
    .DBUS_WIDTH(DBUS_WIDTH),
    .PERIPH_ADDR_WIDTH(PERIPH_ADDR_WIDTH),
    .REG_ADDR_WIDTH(REG_ADDR_WIDTH),
    .PERIPH_ADDR(PERIPH_ADDR)
) hba_reg_bank_inst
(

    .hba_clk(hba_clk),
    .hba_reset(hba_reset),
    .hba_rnw(hba_rnw),
    .hba_select(hba_select),
    .hba_abus(hba_abus),
    .hba_dbus(hba_dbus),

    .hba_dbus_slave(hba_dbus_slave),
    .hba_xferack_slave(hba_xferack_slave),




    .slv_reg0(reg_intr0),
    .slv_reg0_in(reg_intr0_in),

    .slv_reg1(reg_intr1),
    .slv_reg1_in(reg_intr1_in),

    .slv_reg2(reg_rate_ms),

    .slv_wr_en(slv_wr_en),
    .slv_wr_mask(4'b011),
    .slv_autoclr_mask(4'b011)
);





reg [3:0] serial_state;

reg [7:0] cmd_byte;
reg [7:0] regaddr_byte;
reg [3:0] transfer_num;

wire rnw_bit;
wire [2:0] num_bytes_bits;
wire [3:0] core_addr_bits;

assign rnw_bit = cmd_byte[7];
assign num_bytes_bits = cmd_byte[6:4];
assign core_addr_bits = cmd_byte[3:0];


localparam IDLE                     = 0;
localparam REG_ADDR                 = 1;
localparam ECHO_CMD                 = 2;
localparam ECHO_RAD                 = 3;
localparam HBA_SETUP                = 4;
localparam HBA_SERIAL_READ          = 5;
localparam HBA_WAIT                 = 6;
localparam HBA_WAIT2                = 7;
localparam ACK                      = 8;
localparam DONE                     = 9;


localparam RPI_WRITE            = 0;
localparam RPI_READ             = 1;


localparam ACK_CHAR         =8'hAC;
localparam NACK_CHAR        =8'h56;

always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        serial_state <= IDLE;
        cmd_byte <= 0;
        regaddr_byte <= 0;
        transfer_num <= 0;

        app_core_addr <= 0;
        app_reg_addr <= 0;
        app_data_in <= 0;
        app_rnw <= 0;
        app_en_strobe <= 0;

        serial_tx_data <= 0;
        serial_wr <= 0;
        serial_rd <= 0;

    end else begin
        case (serial_state)
            IDLE : begin
                serial_wr <= 0;
                transfer_num <= 0;
                app_en_strobe <= 0;


                serial_rd <= 1;
                if (serial_valid) begin
                    serial_rd <= 0;
                    cmd_byte <= serial_rx_data;
                    serial_state <= REG_ADDR;
                end
            end
            REG_ADDR : begin

                serial_rd <= 1;
                if (serial_valid) begin
                    serial_rd <= 0;
                    transfer_num <= num_bytes_bits + 1;
                    regaddr_byte <= serial_rx_data;
                    if (rnw_bit == RPI_READ) begin
                        serial_state <= ECHO_CMD;
                    end else begin
                        serial_state <= HBA_SETUP;
                    end
                end
            end
            ECHO_CMD : begin

                serial_tx_data <= cmd_byte;
                serial_wr <= 1;
                if (serial_valid) begin
                    serial_wr <= 0;
                    serial_state <= ECHO_RAD;
                end
            end
            ECHO_RAD : begin

                serial_tx_data <= regaddr_byte;
                serial_wr <= 1;
                if (serial_valid) begin
                    serial_wr <= 0;
                    serial_state <= HBA_SETUP;
                end
            end
            HBA_SETUP : begin
                serial_wr <= 0;

                app_en_strobe <= 0;


                if (transfer_num == 0) begin
                    if (rnw_bit == RPI_READ) begin
                        serial_state <= DONE;
                    end else begin

                        serial_state <= ACK;
                    end
                end else begin

                    transfer_num <= transfer_num - 1;


                    app_core_addr <= core_addr_bits;
                    app_reg_addr <= regaddr_byte;
                    app_rnw <= rnw_bit;


                    regaddr_byte <= regaddr_byte + 1;


                    if (rnw_bit == RPI_WRITE) begin

                        serial_rd <= 1;
                        serial_state <= HBA_SERIAL_READ;
                    end else begin

                        app_en_strobe <= 1;
                        serial_state <= HBA_WAIT;
                    end
                end

            end
            HBA_SERIAL_READ : begin
                if (serial_valid) begin
                    serial_rd <= 0;
                    app_data_in <= serial_rx_data;
                    app_en_strobe <= 1;
                    serial_state <= HBA_WAIT;
                end
            end
            HBA_WAIT : begin
                app_en_strobe <= 0;

                if (app_valid_out) begin
                    if (rnw_bit == RPI_WRITE) begin
                        serial_state <= HBA_SETUP;
                    end else begin

                        serial_tx_data <= app_data_out;
                        serial_wr <= 1;
                        serial_state <= HBA_WAIT2;
                    end
                end
            end
            HBA_WAIT2 : begin
                if (serial_valid) begin
                    serial_wr <= 0;
                    serial_state <= HBA_SETUP;
                end
            end
            ACK : begin
                serial_tx_data <= ACK_CHAR;
                serial_wr <= 1;
                if (serial_valid) begin
                    serial_wr <= 0;
                    serial_state <= DONE;
                end
            end
            DONE : begin
                if (!serial_valid) begin
                    serial_state <= IDLE;
                end
            end
            default : begin
                serial_state <= IDLE;
            end
        endcase
    end
end


localparam ONE_MS_COUNT = ( CLK_FREQUENCY / 1000 );
localparam COUNT_BITS = $clog2(ONE_MS_COUNT);
reg [COUNT_BITS-1:0] count_to_1ms;
reg [7:0] count_1ms;
reg io_intr_en;
always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        count_to_1ms <= 0;
        count_1ms <= 0;
        io_intr_en <= 0;
    end else begin
        io_intr_en <= 0;
        count_to_1ms <= count_to_1ms + 1;
        if (count_to_1ms == (ONE_MS_COUNT-1)) begin
            count_to_1ms <= 0;
            count_1ms <= count_1ms + 1;
        end
        if (count_1ms == reg_rate_ms) begin
            count_1ms <= 0;
            io_intr_en <= 1;
        end
    end
end


integer i;
always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        slv_wr_en <= 0;
        reg_intr0_in <= 0;
        reg_intr1_in <= 0;
        io_intr <= 0;
    end else begin

        if (io_intr == 0) begin
            if (io_intr_en) begin
                io_intr <= (|reg_intr0) | (|reg_intr1);
            end
        end else begin

            io_intr <= (|reg_intr0) | (|reg_intr1);
        end


        slv_wr_en <= 0;

        for (i=0; i <8; i=i+1)
        begin
            if (slave_interrupt[i]) begin
                reg_intr0_in[i] <= 1'b1;
                slv_wr_en <= 1;
            end
            if (slave_interrupt[i+8]) begin
                reg_intr1_in[i] <= 1'b1;
                slv_wr_en <= 1;
            end
        end
    end
end

endmodule