data/full_repos/permissive/160510184/SignExtend.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160510184/SignExtend.v:37: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s CONST \'11\'h69a\' generates 11 bits.\n                                                                    : ... In instance SignExtend\nelse if(Instruction[31:21] == 11\'b11010011011 || 11\'b11010011010)\n                                              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module SignExtend(Instruction, extended);

input [31:0] Instruction;
output reg [63:0] extended;

always @ (*)
begin
if (Instruction[31:26] == `BOPCODE)				
	extended = {{38{Instruction[25]}}, Instruction[25:0]};

else if(Instruction[31:24] == `CBZOPCODE)
	extended = {{45{Instruction[23]}}, Instruction[23:5]};

else if(Instruction[31:21] == `LDUROPCODE || Instruction[31:21] == `STUROPCODE)
	extended = {{55{Instruction[20]}}, Instruction[20:12]};

else if(Instruction[31:21] == `LSLOPCODE || `LSROPCODE)
	extended = {{58{1'b0}}, Instruction[15:10]};

else
	extended = {{32{Instruction[31]}},Instruction};
end
endmodule
module SignExtend(Instruction, extended);


input [31:0] Instruction;
output reg [63:0] extended;

always @ (*)
begin
if (Instruction[31:26] == `BOPCODE)				
	extended = {{38{Instruction[25]}}, Instruction[25:0]};

else if(Instruction[31:24] == `CBZOPCODE)
	extended = {{45{Instruction[23]}}, Instruction[23:5]};

else if(Instruction[31:21] == `LDUROPCODE || Instruction[31:21] == `STUROPCODE)
	extended = {{55{Instruction[20]}}, Instruction[20:12]};

else if(Instruction[31:21] == `LSLOPCODE || `LSROPCODE)
	extended = {{58{1'b0}}, Instruction[15:10]};

else
	extended = {{32{Instruction[31]}},Instruction};
end
endmodule