data/full_repos/permissive/158096953/z80_cpu.v
1: b"%Error: data/full_repos/permissive/158096953/z80_cpu.v:20: syntax error, unexpected ',', expecting IDENTIFIER or do or final\n int,\n    ^\n%Error: data/full_repos/permissive/158096953/z80_cpu.v:41: syntax error, unexpected output\noutput reg m1;\n^~~~~~\n%Error: data/full_repos/permissive/158096953/z80_cpu.v:42: syntax error, unexpected output\noutput reg wr;\n^~~~~~\n%Error: data/full_repos/permissive/158096953/z80_cpu.v:43: syntax error, unexpected output\noutput reg rd;\n^~~~~~\n%Error: data/full_repos/permissive/158096953/z80_cpu.v:44: syntax error, unexpected output\noutput reg mreq;\n^~~~~~\n%Error: data/full_repos/permissive/158096953/z80_cpu.v:45: syntax error, unexpected output\noutput reg iorq;\n^~~~~~\n%Error: data/full_repos/permissive/158096953/z80_cpu.v:46: syntax error, unexpected output\noutput halt; \n^~~~~~\n%Error: data/full_repos/permissive/158096953/z80_cpu.v:105: syntax error, unexpected IDENTIFIER\ninstr_fetch if_0(\n^~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module z80_cpu(
	clk,
	reset,
	nmi,
	int,
	data_input,
	data_output_output,
	data_bus_os,
	address,
	m1,
	wr,
	rd,
	mreq,
	iorq,
	halt
);
input clk;
input reset;
input nmi;
input int;
input [7:0] data_input;

output [7:0] data_output_output;
output [7:0] data_bus_os;
output reg [15:0] address;
output reg m1;
output reg wr;
output reg rd;
output reg mreq;
output reg iorq;
output halt; 



wire       fsm_if_en;
wire       fsm_if_pc_modify;

wire       if_fsm_instr_finish;
wire [2:0] if_fsm_num_bytes;

wire       fsm_of_le_en;

wire       fsm_of_mem_rd;
wire       fsm_of_load_en;
wire       fsm_of_input;
wire [7:0] fsm_of_operation_type;
wire [7:0] fsm_of_des;
wire [7:0] fsm_of_sou;

wire [7:0] ie_fsm_flag_reg;
wire fsm_ie_en;

wire fsm_os_output;
wire fsm_os_mem_wr;
wire fsm_os_IFF2;
wire fsm_os_int;


wire [15:0] if_of_pc;

wire [15:0] of_if_pc;
wire [31:0] instruction;



wire [7:0] of_ie_operand_des;
wire [7:0] of_ie_operand_des_high;
wire [7:0] of_ie_operand_sou;
wire [7:0] of_ie_operand_sou_high;
wire [7:0] of_ie_flag_reg;
wire [4:0] of_ie_operation;


wire [7:0] ie_os_result;
wire [7:0] ie_os_result_high;
wire [7:0] ie_os_flag_reg;






wire [15:0] address_bus_if;
wire [15:0] address_bus_of;
wire [15:0] address_input;
wire [15:0] address_bus_os;
wire [15:0] address_output;


instr_fetch if_0(
	.clk(clk),
	.reset(reset),
	.data_input(data_input),

	.fsm_if_en(fsm_if_en),
	.fsm_if_pc_modify(fsm_if_pc_modify),
	.address_bus_if(address_bus_if),


	.if_of_pc(if_of_pc),
	.of_if_pc(of_if_pc),

	.if_fsm_num_bytes(if_fsm_num_bytes),
	.if_fsm_instr_finish(if_fsm_instr_finish),
	.instruction(instruction)
);

fsm_control fsm_0(
	.clk(clk),
	.reset(reset),
	.int(int),
	.nmi(nmi),
	.halt_o(halt),

	.fsm_if_en(fsm_if_en),

	.if_fsm_instr_finish(if_fsm_instr_finish),
	.if_fsm_num_bytes(if_fsm_num_bytes),
	.instruction(instruction),
	
	.ie_fsm_flag_reg(ie_fsm_flag_reg),
	.fsm_of_le_en(fsm_of_le_en),
	.fsm_if_pc_modify(fsm_if_pc_modify),
	.fsm_of_mem_rd(fsm_of_mem_rd),
	.fsm_of_load_en(fsm_of_load_en),
	.fsm_of_input(fsm_of_input),
	.fsm_of_operation_type(fsm_of_operation_type),
	.fsm_of_des(fsm_of_des),
	.fsm_of_sou(fsm_of_sou),	
	.fsm_ie_en(fsm_ie_en),
	.fsm_os_output(fsm_os_output),
	.fsm_os_mem_wr(fsm_os_mem_wr),
	.fsm_os_IFF2(fsm_os_IFF2),
	.fsm_os_int(fsm_os_int)


);

opera_fetch_opera_store of_os_0(
	.clk(clk),
	.reset(reset),

	.fsm_of_le_en(fsm_of_le_en),

	.fsm_of_mem_rd(fsm_of_mem_rd),
	.fsm_of_load_en(fsm_of_load_en),
	.fsm_of_input(fsm_of_input),
	.fsm_of_operation_type(fsm_of_operation_type),
	.fsm_of_des(fsm_of_des),
	.fsm_of_sou(fsm_of_sou),

	.of_ie_operand_des(of_ie_operand_des),
	.of_ie_operand_des_high(of_ie_operand_des_high),
	.of_ie_operand_sou(of_ie_operand_sou),
	.of_ie_operand_sou_high(of_ie_operand_sou_high),
	.of_ie_flag_reg(of_ie_flag_reg),
	.of_ie_operation(of_ie_operation),

	.address_input(address_input),
	.address_bus_of(address_bus_of),
	.data_bus_of(data_input),
	.if_of_pc(if_of_pc),
	.of_if_pc(of_if_pc),


	.fsm_os_mem_wr(fsm_os_mem_wr),
	.fsm_os_IFF2(fsm_os_IFF2),
	.fsm_os_int(fsm_os_int),
	.ie_os_result(ie_os_result),
	.ie_os_result_high(ie_os_result_high),
	.ie_os_flag_reg(ie_os_flag_reg),
	.address_output(address_output),
	.address_bus_os(address_bus_os),
	.data_output(data_output_output),
	.data_bus_os(data_bus_os)
);

instr_excute ie_0(
	.clk(clk),
	.reset(reset),
	.fsm_ie_en(fsm_ie_en),	
	.of_ie_operand_des(of_ie_operand_des),
	.of_ie_operand_des_high(of_ie_operand_des_high),
	.of_ie_operand_sou(of_ie_operand_sou),
	.of_ie_operand_sou_high(of_ie_operand_sou_high),
	.of_ie_flag_reg(of_ie_flag_reg),
	.of_ie_operation(of_ie_operation),
	.ie_os_result(ie_os_result),
	.ie_os_result_high(ie_os_result_high),
	.ie_os_flag_reg(ie_os_flag_reg),
	.ie_fsm_flag_reg(ie_fsm_flag_reg)
);






always @* begin
	case({fsm_if_en, fsm_of_mem_rd, fsm_of_input, fsm_os_mem_wr, fsm_os_output})
		5'b10000:begin
			iorq = 1'b1;
			m1   = 1'b0;
			wr   = 1'b1;
			rd   = 1'b0;
			mreq = 1'b0;
			address = address_bus_if;
		end
		5'b01000:begin
			iorq = 1'b1;
			m1   = 1'b1;
			wr   = 1'b1;
			rd   = 1'b0;
			mreq = 1'b0;
			address = address_bus_of;
		end
		5'b00100:begin
			iorq = 1'b0;
			m1   = 1'b1;
			wr   = 1'b1;
			rd   = 1'b0;
			mreq = 1'b1;
			address = address_input;
		end
		5'b00010:begin
			iorq = 1'b1;
			m1   = 1'b1;
			wr   = 1'b0;
			rd   = 1'b1;
			mreq = 1'b0;
			address = address_bus_os;
		end
		5'b00001:begin
			iorq = 1'b0;
			m1   = 1'b1;
			wr   = 1'b0;
			rd   = 1'b1;
			mreq = 1'b1;
			address = address_output;
		end
		default:begin
			iorq = 1'b1;
			m1   = 1'b1;
			wr   = 1'b1;
			rd   = 1'b1;
			mreq = 1'b1;
			address = 16'h0000;		
		end
	endcase
end











endmodule
module z80_cpu(
	clk,
	reset,
	nmi,
	int,
	data_input,
	data_output_output,
	data_bus_os,
	address,
	m1,
	wr,
	rd,
	mreq,
	iorq,
	halt
);

input clk;
input reset;
input nmi;
input int;
input [7:0] data_input;

output [7:0] data_output_output;
output [7:0] data_bus_os;
output reg [15:0] address;
output reg m1;
output reg wr;
output reg rd;
output reg mreq;
output reg iorq;
output halt; 



wire       fsm_if_en;
wire       fsm_if_pc_modify;

wire       if_fsm_instr_finish;
wire [2:0] if_fsm_num_bytes;

wire       fsm_of_le_en;

wire       fsm_of_mem_rd;
wire       fsm_of_load_en;
wire       fsm_of_input;
wire [7:0] fsm_of_operation_type;
wire [7:0] fsm_of_des;
wire [7:0] fsm_of_sou;

wire [7:0] ie_fsm_flag_reg;
wire fsm_ie_en;

wire fsm_os_output;
wire fsm_os_mem_wr;
wire fsm_os_IFF2;
wire fsm_os_int;


wire [15:0] if_of_pc;

wire [15:0] of_if_pc;
wire [31:0] instruction;



wire [7:0] of_ie_operand_des;
wire [7:0] of_ie_operand_des_high;
wire [7:0] of_ie_operand_sou;
wire [7:0] of_ie_operand_sou_high;
wire [7:0] of_ie_flag_reg;
wire [4:0] of_ie_operation;


wire [7:0] ie_os_result;
wire [7:0] ie_os_result_high;
wire [7:0] ie_os_flag_reg;






wire [15:0] address_bus_if;
wire [15:0] address_bus_of;
wire [15:0] address_input;
wire [15:0] address_bus_os;
wire [15:0] address_output;


instr_fetch if_0(
	.clk(clk),
	.reset(reset),
	.data_input(data_input),

	.fsm_if_en(fsm_if_en),
	.fsm_if_pc_modify(fsm_if_pc_modify),
	.address_bus_if(address_bus_if),


	.if_of_pc(if_of_pc),
	.of_if_pc(of_if_pc),

	.if_fsm_num_bytes(if_fsm_num_bytes),
	.if_fsm_instr_finish(if_fsm_instr_finish),
	.instruction(instruction)
);

fsm_control fsm_0(
	.clk(clk),
	.reset(reset),
	.int(int),
	.nmi(nmi),
	.halt_o(halt),

	.fsm_if_en(fsm_if_en),

	.if_fsm_instr_finish(if_fsm_instr_finish),
	.if_fsm_num_bytes(if_fsm_num_bytes),
	.instruction(instruction),
	
	.ie_fsm_flag_reg(ie_fsm_flag_reg),
	.fsm_of_le_en(fsm_of_le_en),
	.fsm_if_pc_modify(fsm_if_pc_modify),
	.fsm_of_mem_rd(fsm_of_mem_rd),
	.fsm_of_load_en(fsm_of_load_en),
	.fsm_of_input(fsm_of_input),
	.fsm_of_operation_type(fsm_of_operation_type),
	.fsm_of_des(fsm_of_des),
	.fsm_of_sou(fsm_of_sou),	
	.fsm_ie_en(fsm_ie_en),
	.fsm_os_output(fsm_os_output),
	.fsm_os_mem_wr(fsm_os_mem_wr),
	.fsm_os_IFF2(fsm_os_IFF2),
	.fsm_os_int(fsm_os_int)


);

opera_fetch_opera_store of_os_0(
	.clk(clk),
	.reset(reset),

	.fsm_of_le_en(fsm_of_le_en),

	.fsm_of_mem_rd(fsm_of_mem_rd),
	.fsm_of_load_en(fsm_of_load_en),
	.fsm_of_input(fsm_of_input),
	.fsm_of_operation_type(fsm_of_operation_type),
	.fsm_of_des(fsm_of_des),
	.fsm_of_sou(fsm_of_sou),

	.of_ie_operand_des(of_ie_operand_des),
	.of_ie_operand_des_high(of_ie_operand_des_high),
	.of_ie_operand_sou(of_ie_operand_sou),
	.of_ie_operand_sou_high(of_ie_operand_sou_high),
	.of_ie_flag_reg(of_ie_flag_reg),
	.of_ie_operation(of_ie_operation),

	.address_input(address_input),
	.address_bus_of(address_bus_of),
	.data_bus_of(data_input),
	.if_of_pc(if_of_pc),
	.of_if_pc(of_if_pc),


	.fsm_os_mem_wr(fsm_os_mem_wr),
	.fsm_os_IFF2(fsm_os_IFF2),
	.fsm_os_int(fsm_os_int),
	.ie_os_result(ie_os_result),
	.ie_os_result_high(ie_os_result_high),
	.ie_os_flag_reg(ie_os_flag_reg),
	.address_output(address_output),
	.address_bus_os(address_bus_os),
	.data_output(data_output_output),
	.data_bus_os(data_bus_os)
);

instr_excute ie_0(
	.clk(clk),
	.reset(reset),
	.fsm_ie_en(fsm_ie_en),	
	.of_ie_operand_des(of_ie_operand_des),
	.of_ie_operand_des_high(of_ie_operand_des_high),
	.of_ie_operand_sou(of_ie_operand_sou),
	.of_ie_operand_sou_high(of_ie_operand_sou_high),
	.of_ie_flag_reg(of_ie_flag_reg),
	.of_ie_operation(of_ie_operation),
	.ie_os_result(ie_os_result),
	.ie_os_result_high(ie_os_result_high),
	.ie_os_flag_reg(ie_os_flag_reg),
	.ie_fsm_flag_reg(ie_fsm_flag_reg)
);






always @* begin
	case({fsm_if_en, fsm_of_mem_rd, fsm_of_input, fsm_os_mem_wr, fsm_os_output})
		5'b10000:begin
			iorq = 1'b1;
			m1   = 1'b0;
			wr   = 1'b1;
			rd   = 1'b0;
			mreq = 1'b0;
			address = address_bus_if;
		end
		5'b01000:begin
			iorq = 1'b1;
			m1   = 1'b1;
			wr   = 1'b1;
			rd   = 1'b0;
			mreq = 1'b0;
			address = address_bus_of;
		end
		5'b00100:begin
			iorq = 1'b0;
			m1   = 1'b1;
			wr   = 1'b1;
			rd   = 1'b0;
			mreq = 1'b1;
			address = address_input;
		end
		5'b00010:begin
			iorq = 1'b1;
			m1   = 1'b1;
			wr   = 1'b0;
			rd   = 1'b1;
			mreq = 1'b0;
			address = address_bus_os;
		end
		5'b00001:begin
			iorq = 1'b0;
			m1   = 1'b1;
			wr   = 1'b0;
			rd   = 1'b1;
			mreq = 1'b1;
			address = address_output;
		end
		default:begin
			iorq = 1'b1;
			m1   = 1'b1;
			wr   = 1'b1;
			rd   = 1'b1;
			mreq = 1'b1;
			address = 16'h0000;		
		end
	endcase
end











endmodule