data/full_repos/permissive/155085421/memory.v
data/verilator_xmls/eb74bc54-559b-423d-a83b-05623117c450.xml
module memory(
    input clock,

    input perform_read,
    input [8:0] read_address,
    output reg[23:0] read_data,
    output reg read_data_ready,


    input perform_write,
    input [8:0] write_address,
    input [23:0] write_data
    );


reg[7:0] mem0[0:511];
reg[7:0] mem1[0:511];
reg[7:0] mem2[0:511];

always @(posedge clock)
begin

    if (perform_read)
    begin

        read_data[23:16] <= mem2[read_address];
        read_data[15:8] <= mem1[read_address];
        read_data[7:0] <= mem0[read_address];
    end


    if (perform_write)
    begin
        mem2[write_address] <= write_data[23:16];
        mem1[write_address] <= write_data[15:8];
        mem0[write_address] <= write_data[7:0];
    end
end


always @(posedge clock) read_data_ready <= perform_read;

endmodule
module memory(
    input clock,

    input perform_read,
    input [8:0] read_address,
    output reg[23:0] read_data,
    output reg read_data_ready,


    input perform_write,
    input [8:0] write_address,
    input [23:0] write_data
    );



reg[7:0] mem0[0:511];
reg[7:0] mem1[0:511];
reg[7:0] mem2[0:511];

always @(posedge clock)
begin

    if (perform_read)
    begin

        read_data[23:16] <= mem2[read_address];
        read_data[15:8] <= mem1[read_address];
        read_data[7:0] <= mem0[read_address];
    end


    if (perform_write)
    begin
        mem2[write_address] <= write_data[23:16];
        mem1[write_address] <= write_data[15:8];
        mem0[write_address] <= write_data[7:0];
    end
end


always @(posedge clock) read_data_ready <= perform_read;

endmodule