data/full_repos/permissive/131069375/nano-risc/verilog/auto_reset.v
data/verilator_xmls/db1c7785-3eaa-4da4-bf20-8f4888365a20.xml
module auto_reset(
    input clock,
    output reset
);
  reg [9:0] shift_reg = 10'b1111111111;
  
  always @(posedge clock)
    shift_reg <= {shift_reg[8:0], 1'b0};
    
  assign reset = shift_reg[9];
endmodule
module auto_reset(
    input clock,
    output reset
);

  reg [9:0] shift_reg = 10'b1111111111;
  
  always @(posedge clock)
    shift_reg <= {shift_reg[8:0], 1'b0};
    
  assign reset = shift_reg[9];
endmodule