data/full_repos/permissive/165663914/firmware/MDIO.v
1: b'%Warning-WIDTH: data/full_repos/permissive/165663914/firmware/MDIO.v:193: Bit extraction of array[1:0] requires 1 bit index, not 5 bits.\n                                                                        : ... In instance MDIO\n   MDIO <= REG_address[loop_count][mask - 1\'b1];\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/165663914/firmware/MDIO.v:193: Bit extraction of var[4:0] requires 3 bit index, not 7 bits.\n                                                                        : ... In instance MDIO\n   MDIO <= REG_address[loop_count][mask - 1\'b1];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/165663914/firmware/MDIO.v:212: Bit extraction of array[1:0] requires 1 bit index, not 5 bits.\n                                                                        : ... In instance MDIO\n   MDIO <= REG_data[loop_count][mask - 1\'b1];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/165663914/firmware/MDIO.v:212: Bit extraction of var[15:0] requires 4 bit index, not 7 bits.\n                                                                        : ... In instance MDIO\n   MDIO <= REG_data[loop_count][mask - 1\'b1];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/165663914/firmware/MDIO.v:252: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                        : ... In instance MDIO\n  read <= 1\'b1;\n       ^~\n%Error: Exiting due to 5 warning(s)\n'
module MDIO (clk, write_PHY, write_done, read_PHY, clock, MDIO_inout, read_done, read_reg_address, register_data, speed);

input write_PHY;
input read_PHY;
input clk;
input [4:0]read_reg_address;
input speed;

output clock;
output read_done;
output [15:0]register_data;
output write_done;

inout MDIO_inout;

localparam data_size = 1;

reg MDIO;
reg [5:0] write;
reg [6:0] preamble;
reg [2:0] address;
reg [6:0] mask;
reg [4:0] REG_address[0:data_size];			
reg [15:0]REG_data[0:data_size];
reg [4:0] loop_count;
reg read_done;
reg write_done;
reg [15:0] temp_reg_data;
reg previous_speed;



always @ (negedge clk)
begin







REG_address[0] <= 5'd0;  REG_data[0] <= 16'h1000;				
REG_address[1] <= 5'd0;  REG_data[1] <= 16'h1000;	


case (write)

0:	begin
		if (write_PHY | (speed != previous_speed)) begin
			write_done <= 0;
			write <= 1;
		end 
		else begin
			MDIO <= 1'b0;
			address <= 0;
			write <= 0;
			loop_count <= 0;
			preamble <= 0;
		end 
	end

1:  begin 
		if (preamble != 32) begin
			preamble <= preamble + 1'b1;
			MDIO <= 1'b1;
			write <= 1; 
		end
		else
		begin
			MDIO <= 1'b0;
			write <= 2;
		end 
	end 
	
2:	begin
	MDIO <= 1'b1;
	write <= write + 1'b1;
	end
	
3:	begin 
	MDIO <= 1'b0;
	write <= write + 1'b1;
	end

4:	begin
	MDIO <= 1'b1;
	write <= write + 1'b1;
	end
		

5:	begin
	 if (address != 4) begin
		MDIO <= 0;
		address <= address + 1'b1;
		write <= 5;
	 end 
	 else begin
		MDIO <= 1'b1;
		mask <= 5;
		write <= write + 1'b1;
	 end
	 end 


6:	begin
		if (mask != 0) begin
			MDIO <= REG_address[loop_count][mask - 1'b1];
			mask <= mask - 1'b1;
			write <= 6;
		end 
		else begin
			MDIO <= 1'b1;
			write <= write + 1'b1;
		end 
	end
	
7:	begin
	MDIO <= 1'b0;
	mask <= 16;
	write <= write + 1'b1;
	end 
	

8:	begin
		if (mask != 0) begin
			MDIO <= REG_data[loop_count][mask - 1'b1];
			mask <= mask - 1'b1;
			write <= 8;
		end 
		else begin
			if (loop_count == data_size) begin						
				write_done <= 1'b1;
				previous_speed <= speed;
				write <= 0;
			end
			else begin
				loop_count <= loop_count + 1'b1;
				address <= 0;
				preamble <= 0;
				write <= 1;
			end
		end 
	end
endcase
end 	
	
	

reg [4:0]read;
reg [5:0]preamble2;
reg [4:0]read_count;
reg [2:0]address2;
reg [15:0]register_data;
reg [4:0]temp_address;
reg MDIO2;
always @(negedge clk)
begin 
case (read)	

0: begin 
	if (read_PHY)begin
		address2 <= 0;
		read_done <= 0;
		read_count <= 0;
		preamble2 <= 0;
		read <= 1'b1;
		temp_address <= read_reg_address;
	end 
	else read <= 0;
   end 

1:  begin 
		if (preamble2 != 32) begin
			preamble2 <= preamble2 + 1'b1;
			MDIO2 <= 1'b1;
			read <= 1; 
		end
		else
		begin
			MDIO2 <= 1'b0;
			read <= read + 1'b1;
		end 
	end 
	
2:	begin
	MDIO2 <= 1'b1;
	read <= read + 1'b1;
	end
	
3:	begin 
	MDIO2 <= 1'b1;
	read <= read + 1'b1;
	end

4:	begin
	MDIO2 <= 1'b0;
	read <= read + 1'b1;
	end 
	

5:	begin
	 if (address2 != 4) begin
		MDIO2 <= 0;
		address2 <= address2 + 1'b1;
		read <= 5;
	 end 
	 else begin
		MDIO2 <= 1'b1;
		address2 <= 0;
		read <= read + 1'b1;
	 end
	 end 


6:	begin
	 if (address2 != 5) begin
		MDIO2 <= temp_address[4];
		temp_address <= {temp_address[3:0],1'b0};
		address2 <= address2 + 1'b1;
		read <= 6;
	 end 
	 else read <= read + 1'b1;
	end



	
7: begin	
	if (read_count != 17) begin
		temp_reg_data <= {temp_reg_data[14:0],MDIO_inout};
		read_count <= read_count + 1'b1;
	end 
    else begin 
		register_data <= temp_reg_data;
		read_done <= 1'b1;
		read <= 0;
	end
   end
endcase
end 


assign clock = (write > 0 || read > 0) ? clk : 1'b0;
assign MDIO_inout  = (write > 0 ) ? MDIO : (read > 0 && read < 7 ? MDIO2 : 1'bZ); 

endmodule
module MDIO (clk, write_PHY, write_done, read_PHY, clock, MDIO_inout, read_done, read_reg_address, register_data, speed);


input write_PHY;
input read_PHY;
input clk;
input [4:0]read_reg_address;
input speed;

output clock;
output read_done;
output [15:0]register_data;
output write_done;

inout MDIO_inout;

localparam data_size = 1;

reg MDIO;
reg [5:0] write;
reg [6:0] preamble;
reg [2:0] address;
reg [6:0] mask;
reg [4:0] REG_address[0:data_size];			
reg [15:0]REG_data[0:data_size];
reg [4:0] loop_count;
reg read_done;
reg write_done;
reg [15:0] temp_reg_data;
reg previous_speed;



always @ (negedge clk)
begin







REG_address[0] <= 5'd0;  REG_data[0] <= 16'h1000;				
REG_address[1] <= 5'd0;  REG_data[1] <= 16'h1000;	


case (write)

0:	begin
		if (write_PHY | (speed != previous_speed)) begin
			write_done <= 0;
			write <= 1;
		end 
		else begin
			MDIO <= 1'b0;
			address <= 0;
			write <= 0;
			loop_count <= 0;
			preamble <= 0;
		end 
	end

1:  begin 
		if (preamble != 32) begin
			preamble <= preamble + 1'b1;
			MDIO <= 1'b1;
			write <= 1; 
		end
		else
		begin
			MDIO <= 1'b0;
			write <= 2;
		end 
	end 
	
2:	begin
	MDIO <= 1'b1;
	write <= write + 1'b1;
	end
	
3:	begin 
	MDIO <= 1'b0;
	write <= write + 1'b1;
	end

4:	begin
	MDIO <= 1'b1;
	write <= write + 1'b1;
	end
		

5:	begin
	 if (address != 4) begin
		MDIO <= 0;
		address <= address + 1'b1;
		write <= 5;
	 end 
	 else begin
		MDIO <= 1'b1;
		mask <= 5;
		write <= write + 1'b1;
	 end
	 end 


6:	begin
		if (mask != 0) begin
			MDIO <= REG_address[loop_count][mask - 1'b1];
			mask <= mask - 1'b1;
			write <= 6;
		end 
		else begin
			MDIO <= 1'b1;
			write <= write + 1'b1;
		end 
	end
	
7:	begin
	MDIO <= 1'b0;
	mask <= 16;
	write <= write + 1'b1;
	end 
	

8:	begin
		if (mask != 0) begin
			MDIO <= REG_data[loop_count][mask - 1'b1];
			mask <= mask - 1'b1;
			write <= 8;
		end 
		else begin
			if (loop_count == data_size) begin						
				write_done <= 1'b1;
				previous_speed <= speed;
				write <= 0;
			end
			else begin
				loop_count <= loop_count + 1'b1;
				address <= 0;
				preamble <= 0;
				write <= 1;
			end
		end 
	end
endcase
end 	
	
	

reg [4:0]read;
reg [5:0]preamble2;
reg [4:0]read_count;
reg [2:0]address2;
reg [15:0]register_data;
reg [4:0]temp_address;
reg MDIO2;
always @(negedge clk)
begin 
case (read)	

0: begin 
	if (read_PHY)begin
		address2 <= 0;
		read_done <= 0;
		read_count <= 0;
		preamble2 <= 0;
		read <= 1'b1;
		temp_address <= read_reg_address;
	end 
	else read <= 0;
   end 

1:  begin 
		if (preamble2 != 32) begin
			preamble2 <= preamble2 + 1'b1;
			MDIO2 <= 1'b1;
			read <= 1; 
		end
		else
		begin
			MDIO2 <= 1'b0;
			read <= read + 1'b1;
		end 
	end 
	
2:	begin
	MDIO2 <= 1'b1;
	read <= read + 1'b1;
	end
	
3:	begin 
	MDIO2 <= 1'b1;
	read <= read + 1'b1;
	end

4:	begin
	MDIO2 <= 1'b0;
	read <= read + 1'b1;
	end 
	

5:	begin
	 if (address2 != 4) begin
		MDIO2 <= 0;
		address2 <= address2 + 1'b1;
		read <= 5;
	 end 
	 else begin
		MDIO2 <= 1'b1;
		address2 <= 0;
		read <= read + 1'b1;
	 end
	 end 


6:	begin
	 if (address2 != 5) begin
		MDIO2 <= temp_address[4];
		temp_address <= {temp_address[3:0],1'b0};
		address2 <= address2 + 1'b1;
		read <= 6;
	 end 
	 else read <= read + 1'b1;
	end



	
7: begin	
	if (read_count != 17) begin
		temp_reg_data <= {temp_reg_data[14:0],MDIO_inout};
		read_count <= read_count + 1'b1;
	end 
    else begin 
		register_data <= temp_reg_data;
		read_done <= 1'b1;
		read <= 0;
	end
   end
endcase
end 


assign clock = (write > 0 || read > 0) ? clk : 1'b0;
assign MDIO_inout  = (write > 0 ) ? MDIO : (read > 0 && read < 7 ? MDIO2 : 1'bZ); 

endmodule