data/full_repos/permissive/162924824/test2/comun/fondo.v
 line:44 column:2: Illegal character '`'
data/verilator_xmls/a945283a-2320-4d0b-804c-da0674cc9dbb.xml
module fondo (
  input wire [10:0] hc,
  input wire [10:0] vc,
  input wire display_enable,
  output reg [7:0] r,
  output reg [7:0] g,
  output reg [7:0] b
  );

  always @* begin
    if (display_enable == 1'b1) begin
      r = hc[7:0] ^ vc[7:0];
      g = hc[7:0] ^ vc[7:0];
      b = {hc[7], vc[7], 6'b000000};
    end
    else begin
      r = 8'h00;
      g = 8'h00;
      b = 8'h00;
    end
  end
endmodule
module fondo (
  input wire [10:0] hc,
  input wire [10:0] vc,
  input wire display_enable,
  output reg [7:0] r,
  output reg [7:0] g,
  output reg [7:0] b
  );


  always @* begin
    if (display_enable == 1'b1) begin
      r = hc[7:0] ^ vc[7:0];
      g = hc[7:0] ^ vc[7:0];
      b = {hc[7], vc[7], 6'b000000};
    end
    else begin
      r = 8'h00;
      g = 8'h00;
      b = 8'h00;
    end
  end
endmodule