data/full_repos/permissive/129447112/pratica2/proc.v
 line:9: before: "["
1: b"%Error: data/full_repos/permissive/129447112/pratica2/proc.v:9: syntax error, unexpected '[', expecting IDENTIFIER or '=' or do or final\n reg [7:0]Xreg, [7:0]Yreg;\n                ^\n%Error: data/full_repos/permissive/129447112/pratica2/proc.v:12: syntax error, unexpected '.', expecting TYPE-IDENTIFIER\n wire Clear = ...\n              ^\n%Error: data/full_repos/permissive/129447112/pratica2/proc.v:21: syntax error, unexpected '.'\n  ... specify initial values\n  ^\n%Error: Cannot continue\n"
module proc (DIN, Resetn, Clock, Run, Done, BusWires);
	input [15:0] DIN;
	input Resetn, Clock, Run;
	
	output Done;
	output [15:0] BusWires;
	
	reg [1:0]Tstep_Q;
	reg [7:0]Xreg, [7:0]Yreg;
	
	wire [0:3]I;
	wire Clear = ...
	
	contador Tstep (Clear, Clock, Tstep_Q);
	assign I = IR[0:2];
	dec3to8 decX (IR[3:5], 1, Xreg);
	dec3to8 decY (IR[6:8], 1, Yreg);
	
	always @(Tstep_Q or I or Xreg or Yreg)
	begin
		... specify initial values
		case (Tstep_Q)
			00:
			begin
				IRin = 1;
			end
			01:
				case (I)
					...
				endcase
			10:
				case (I)
					...
				endcase
			11:
				case (I)
					...
				endcase
		endcase
	end
	
	regn reg_0 (BusWires, Rin[0], Clock, R0);
	... instantiate other registers and the adder/subtracter unit
	
	... define the bus

endmodule
module proc (DIN, Resetn, Clock, Run, Done, BusWires);

	input [15:0] DIN;
	input Resetn, Clock, Run;
	
	output Done;
	output [15:0] BusWires;
	
	reg [1:0]Tstep_Q;
	reg [7:0]Xreg, [7:0]Yreg;
	
	wire [0:3]I;
	wire Clear = ...
	
	contador Tstep (Clear, Clock, Tstep_Q);
	assign I = IR[0:2];
	dec3to8 decX (IR[3:5], 1, Xreg);
	dec3to8 decY (IR[6:8], 1, Yreg);
	
	always @(Tstep_Q or I or Xreg or Yreg)
	begin
		... specify initial values
		case (Tstep_Q)
			00:
			begin
				IRin = 1;
			end
			01:
				case (I)
					...
				endcase
			10:
				case (I)
					...
				endcase
			11:
				case (I)
					...
				endcase
		endcase
	end
	
	regn reg_0 (BusWires, Rin[0], Clock, R0);
	... instantiate other registers and the adder/subtracter unit
	
	... define the bus

endmodule