data/full_repos/permissive/174263347/crtv10/hdl/crt_measure.v
1: b"%Error: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure.v:27: Cannot find file containing module: 'onefextractor'\n    onefextractor hsig_obj( clk, reset, 1'b1, hsync, hris);\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/onefextractor\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/onefextractor.v\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/onefextractor.sv\n             onefextractor\n             onefextractor.v\n             onefextractor.sv\n             obj_dir/onefextractor\n             obj_dir/onefextractor.v\n             obj_dir/onefextractor.sv\n%Error: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure.v:28: Cannot find file containing module: 'onefextractor'\n    onefextractor vsig_obj( clk, reset, 1'b1, vsync, vris);\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module crt_measure ( clk, reset, start, mode, hsync,  vsync, measure, q);

    input           clk, reset, start, mode, vsync, hsync;
    output  [9:0]   q;
    output          measure;

    wire    test_sig;
    wire    sync_sig;
    wire    hris;
    wire    vris;

    onefextractor hsig_obj( clk, reset, 1'b1, hsync, hris);
    onefextractor vsig_obj( clk, reset, 1'b1, vsync, vris);

    assign  test_sig = mode ? vris : hris;
    assign  sync_sig = mode ? hris : 1;

    reg     [9:0]   count;
    reg             check, prepare;



    always @ (posedge reset or posedge clk)
        if (reset)
                count <= 0;
        else if(sync_sig)
            if(check)
                count <= count + 1;
            else if(prepare)
                count <= 0;



    always @ (posedge reset or posedge clk )
        if (reset)
            prepare <= 0;
        else 
        begin
            if(start)
                prepare <= 1;
            else if(check & test_sig)
                prepare <= 0;
        end


    always @ (posedge reset or posedge clk)
        if (reset)
            check <= 0;
        else if (test_sig)
            if (prepare)
                check <= ~check;


    assign measure = prepare;
    assign q = count;

endmodule
module crt_measure ( clk, reset, start, mode, hsync,  vsync, measure, q);


    input           clk, reset, start, mode, vsync, hsync;
    output  [9:0]   q;
    output          measure;

    wire    test_sig;
    wire    sync_sig;
    wire    hris;
    wire    vris;

    onefextractor hsig_obj( clk, reset, 1'b1, hsync, hris);
    onefextractor vsig_obj( clk, reset, 1'b1, vsync, vris);

    assign  test_sig = mode ? vris : hris;
    assign  sync_sig = mode ? hris : 1;

    reg     [9:0]   count;
    reg             check, prepare;



    always @ (posedge reset or posedge clk)
        if (reset)
                count <= 0;
        else if(sync_sig)
            if(check)
                count <= count + 1;
            else if(prepare)
                count <= 0;



    always @ (posedge reset or posedge clk )
        if (reset)
            prepare <= 0;
        else 
        begin
            if(start)
                prepare <= 1;
            else if(check & test_sig)
                prepare <= 0;
        end


    always @ (posedge reset or posedge clk)
        if (reset)
            check <= 0;
        else if (test_sig)
            if (prepare)
                check <= ~check;


    assign measure = prepare;
    assign q = count;

endmodule