data/full_repos/permissive/136510272/projects/z80.proc/marsohod2.v
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1: b'%Error: data/full_repos/permissive/136510272/projects/z80.proc/marsohod2.v:85: Cannot find file containing module: \'z80\'\nz80 Z80(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/projects/z80.proc,data/full_repos/permissive/136510272/z80\n             data/full_repos/permissive/136510272/projects/z80.proc,data/full_repos/permissive/136510272/z80.v\n             data/full_repos/permissive/136510272/projects/z80.proc,data/full_repos/permissive/136510272/z80.sv\n             z80\n             z80.v\n             z80.sv\n             obj_dir/z80\n             obj_dir/z80.v\n             obj_dir/z80.sv\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/z80.proc/marsohod2.v:115: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance marsohod2\nreg  [15:0] rom_i_addr = 1\'b0;\n                         ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/z80.proc/marsohod2.v:116: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance marsohod2\nreg  [7:0]  prg_i_data = 1\'b0;\n                         ^~~~\n%Error: data/full_repos/permissive/136510272/projects/z80.proc/marsohod2.v:118: Cannot find file containing module: \'rom\'\nrom ROM16K(\n^~~\n%Error: data/full_repos/permissive/136510272/projects/z80.proc/marsohod2.v:141: Cannot find file containing module: \'ram\'\nram RAM16K(\n^~~\n%Error: data/full_repos/permissive/136510272/projects/z80.proc/marsohod2.v:162: Cannot find file containing module: \'vadapter\'\nvadapter VGA(\n^~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/z80.proc/marsohod2.v:186: Cannot find file containing module: \'pll\'\npll PLL(\n^~~\n%Error: data/full_repos/permissive/136510272/projects/z80.proc/marsohod2.v:206: Cannot find file containing module: \'serial\'\nserial SERIAL(\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/z80.proc/marsohod2.v:229: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance marsohod2\nreg [7:0]  t_prg_i_data = 1\'b0;\n                          ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/z80.proc/marsohod2.v:230: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance marsohod2\nreg [15:0] t_rom_i_addr = 1\'b0;\n                          ^~~~\n%Error: Exiting due to 6 error(s), 4 warning(s)\n'
module marsohod2(




    input   wire        clk,


    output  reg  [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);



initial led = 4'b0000;

wire [15:0] o_addr;
wire [ 7:0] o_data;


wire [ 7:0] i_data = o_addr[15:14] == 2'b00 ? i_data_0 :
                     o_addr[15:14] == 2'b01 ? i_data_1 : 8'hFF;

wire [ 7:0] i_data_0;
wire [ 7:0] i_data_1;
wire        o_wr;
reg         programm  = 1'b0;

wire [15:0] port;
wire [ 7:0] port_in;
wire [ 7:0] port_out;
wire        port_clk;

z80 Z80(

    .reset    (programm | !keys[0]),
    .clk      (clk),
    .turbo    (1'b0),
    .i_data   (i_data),
    .o_data   (o_data),
    .o_addr   (o_addr),
    .o_wr     (o_wr),    
    .port     (port),
    .port_in  (port_in),
    .port_out (port_out),
    .port_clk (port_clk),

);




always @(posedge port_clk) begin

    if (port[7:0] == 8'hFE) begin   
        vga_border[2:0] <= port_out[2:0];    
    end

end




reg  [15:0] rom_i_addr = 1'b0;
reg  [7:0]  prg_i_data = 1'b0;

rom ROM16K(

    .clock   (clk),
    .addr_rd (o_addr[13:0]),
    .q       (i_data_0),


    .wren    (rom_bank_wr & (rom_i_addr[15:14] == 2'b00)),
    .addr_wr (rom_i_addr[13:0]),
    .data_wr (prg_i_data)

);




wire        wr_idata = programm ? (rom_bank_wr & (rom_i_addr[15:14] == 2'b01)) : (o_wr & (o_addr[15:14] == 2'b01));
wire [13:0] wr_oaddr = programm ? rom_i_addr[13:0] : o_addr[13:0];
wire [7:0]  wr_odata = programm ? prg_i_data[7:0]  : o_data[7:0];




ram RAM16K(

    .clock   (clk),
    .wren    (wr_idata),
    .addr_wr (wr_oaddr),
    .data_wr (wr_odata),
    .qw      (i_data_1),


    .addr_rd (rd_addr),
    .q       (d8_chr)

);




wire [7:0]  d8_chr;
wire [13:0] rd_addr;
reg  [2:0]  vga_border = 3'b111;

vadapter VGA(

    .clock      (clk),
    .addr       (rd_addr),
    .d8_chr     (d8_chr),
    .vga_border (vga_border),
    .r          (vga_red),
    .g          (vga_green),
    .b          (vga_blue),
    .hs         (vga_hs),
    .vs         (vga_vs)
);





wire locked;
wire clock_25;
wire clock_12;
wire clock_6;

pll PLL(

    .clk        (clk),
    .locked     (locked),
    .c0         (clock_25),
    .c1         (clock_12),
    .c2         (clock_6)

);



wire [7:0]  rx_byte;
wire        rx_ready;
wire        clk12;
reg         rom_bank_wr;

serial SERIAL(

	.clk12    (locked & clock_12),
	.rx       (ftdi_rx),
	.rx_byte  (rx_byte),
	.rx_ready (rx_ready)

);


always @(posedge clk) begin

    if (!clock_12) begin

        programm    <= t_programm;
        rom_bank_wr <= t_rom_bank_wr;
        rom_i_addr  <= t_rom_i_addr;
        prg_i_data  <= t_prg_i_data;
        
    end

end

reg [7:0]  t_prg_i_data = 1'b0;
reg [15:0] t_rom_i_addr = 1'b0;
reg        t_rom_bank_wr = 1'b0;
reg        t_programm = 1'b0;


always @(posedge rx_ready) begin
    
    t_prg_i_data <= rx_byte;

    if (t_programm == 1'b0) begin

        t_programm    <= 1'b1;
        t_rom_bank_wr <= 1'b1;
        t_rom_i_addr  <= 16'h0000;
        led[0]        <= 1'b1;

    end
    else begin

        if (t_rom_i_addr == 16'h7FFE) begin
            t_programm    <= 1'b0;
            t_rom_bank_wr <= 1'b0;
            led[0]        <= 1'b0;
        end

        t_rom_i_addr <= t_rom_i_addr + 1'b1;

    end

end







endmodule
module marsohod2(




    input   wire        clk,


    output  reg  [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);




initial led = 4'b0000;

wire [15:0] o_addr;
wire [ 7:0] o_data;


wire [ 7:0] i_data = o_addr[15:14] == 2'b00 ? i_data_0 :
                     o_addr[15:14] == 2'b01 ? i_data_1 : 8'hFF;

wire [ 7:0] i_data_0;
wire [ 7:0] i_data_1;
wire        o_wr;
reg         programm  = 1'b0;

wire [15:0] port;
wire [ 7:0] port_in;
wire [ 7:0] port_out;
wire        port_clk;

z80 Z80(

    .reset    (programm | !keys[0]),
    .clk      (clk),
    .turbo    (1'b0),
    .i_data   (i_data),
    .o_data   (o_data),
    .o_addr   (o_addr),
    .o_wr     (o_wr),    
    .port     (port),
    .port_in  (port_in),
    .port_out (port_out),
    .port_clk (port_clk),

);




always @(posedge port_clk) begin

    if (port[7:0] == 8'hFE) begin   
        vga_border[2:0] <= port_out[2:0];    
    end

end




reg  [15:0] rom_i_addr = 1'b0;
reg  [7:0]  prg_i_data = 1'b0;

rom ROM16K(

    .clock   (clk),
    .addr_rd (o_addr[13:0]),
    .q       (i_data_0),


    .wren    (rom_bank_wr & (rom_i_addr[15:14] == 2'b00)),
    .addr_wr (rom_i_addr[13:0]),
    .data_wr (prg_i_data)

);




wire        wr_idata = programm ? (rom_bank_wr & (rom_i_addr[15:14] == 2'b01)) : (o_wr & (o_addr[15:14] == 2'b01));
wire [13:0] wr_oaddr = programm ? rom_i_addr[13:0] : o_addr[13:0];
wire [7:0]  wr_odata = programm ? prg_i_data[7:0]  : o_data[7:0];




ram RAM16K(

    .clock   (clk),
    .wren    (wr_idata),
    .addr_wr (wr_oaddr),
    .data_wr (wr_odata),
    .qw      (i_data_1),


    .addr_rd (rd_addr),
    .q       (d8_chr)

);




wire [7:0]  d8_chr;
wire [13:0] rd_addr;
reg  [2:0]  vga_border = 3'b111;

vadapter VGA(

    .clock      (clk),
    .addr       (rd_addr),
    .d8_chr     (d8_chr),
    .vga_border (vga_border),
    .r          (vga_red),
    .g          (vga_green),
    .b          (vga_blue),
    .hs         (vga_hs),
    .vs         (vga_vs)
);





wire locked;
wire clock_25;
wire clock_12;
wire clock_6;

pll PLL(

    .clk        (clk),
    .locked     (locked),
    .c0         (clock_25),
    .c1         (clock_12),
    .c2         (clock_6)

);



wire [7:0]  rx_byte;
wire        rx_ready;
wire        clk12;
reg         rom_bank_wr;

serial SERIAL(

	.clk12    (locked & clock_12),
	.rx       (ftdi_rx),
	.rx_byte  (rx_byte),
	.rx_ready (rx_ready)

);


always @(posedge clk) begin

    if (!clock_12) begin

        programm    <= t_programm;
        rom_bank_wr <= t_rom_bank_wr;
        rom_i_addr  <= t_rom_i_addr;
        prg_i_data  <= t_prg_i_data;
        
    end

end

reg [7:0]  t_prg_i_data = 1'b0;
reg [15:0] t_rom_i_addr = 1'b0;
reg        t_rom_bank_wr = 1'b0;
reg        t_programm = 1'b0;


always @(posedge rx_ready) begin
    
    t_prg_i_data <= rx_byte;

    if (t_programm == 1'b0) begin

        t_programm    <= 1'b1;
        t_rom_bank_wr <= 1'b1;
        t_rom_i_addr  <= 16'h0000;
        led[0]        <= 1'b1;

    end
    else begin

        if (t_rom_i_addr == 16'h7FFE) begin
            t_programm    <= 1'b0;
            t_rom_bank_wr <= 1'b0;
            led[0]        <= 1'b0;
        end

        t_rom_i_addr <= t_rom_i_addr + 1'b1;

    end

end







endmodule