data/full_repos/permissive/115837888/source-7400/7420.v
 line:16: before: "+"
1: b"%Error: data/full_repos/permissive/115837888/source-7400/7420.v:21: Define or directive not defined: '`ASSIGN_UNPACK_ARRAY'\n`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/7420.v:21: syntax error, unexpected '('\n`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)\n                     ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ttl_7420 #(parameter BLOCKS = 2, WIDTH_IN = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
  input [BLOCKS*WIDTH_IN-1:0] A_2D,
  output [BLOCKS-1:0] Y
);


wire [WIDTH_IN-1:0] A [0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;

always @(*)
begin
  for (i = 0; i < BLOCKS; i++)
    computed[i] = ~(&A[i]);
end


`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;

endmodule
module ttl_7420 #(parameter BLOCKS = 2, WIDTH_IN = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
  input [BLOCKS*WIDTH_IN-1:0] A_2D,
  output [BLOCKS-1:0] Y
);



wire [WIDTH_IN-1:0] A [0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;

always @(*)
begin
  for (i = 0; i < BLOCKS; i++)
    computed[i] = ~(&A[i]);
end


`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;

endmodule