data/full_repos/permissive/201488448/3_verification/1_sim/09_comb4.v
data/verilator_xmls/6857fb6b-c41f-484d-be61-28c8815dea28.xml
module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );

    assign q = b | c;

endmodule
module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );


    assign q = b | c;

endmodule