data/full_repos/permissive/113002755/verilog/Torpedo.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/113002755/verilog/Torpedo.v:34: Cannot find file containing module: \'torpedoSprite\'\ntorpedoSprite ts\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/torpedoSprite\n             data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/torpedoSprite.v\n             data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/torpedoSprite.sv\n             torpedoSprite\n             torpedoSprite.v\n             torpedoSprite.sv\n             obj_dir/torpedoSprite\n             obj_dir/torpedoSprite.v\n             obj_dir/torpedoSprite.sv\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:117: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n                                                                          : ... In instance Torpedo\nassign col = iVGA_X - pos_X;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:118: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n                                                                          : ... In instance Torpedo\nassign row = iVGA_Y - pos_Y;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:128: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance Torpedo\n pos_X = 10\'b1111111111;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:129: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance Torpedo\n pos_Y = 10\'b1111111111;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:156: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance Torpedo\n  pos_X = 10\'b1111111111;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:157: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance Torpedo\n  pos_Y = 10\'b1111111111;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:163: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance Torpedo\n  pos_X = 10\'b1111111111;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:164: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance Torpedo\n  pos_Y = 10\'b1111111111;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:211: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance Torpedo\n     pos_X = 10\'b1111111111;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:212: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance Torpedo\n     pos_Y = 10\'b1111111111;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:168: Operator EQ expects 11 bits on the RHS, but RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance Torpedo\n  if(pos_X == 10\'b1111111111)\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:226: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance Torpedo\n  pos_X = 10\'b1111111111;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Torpedo.v:227: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance Torpedo\n  pos_Y = 10\'b1111111111;\n        ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n'
module Torpedo (
		iRst,
		iMemClk,
		iPClk,

		iDir,
		iFireTorpedo,

		iVGA_X,
		iVGA_Y,
		oDrawPixel,
		iCollision
);




torpedoSprite ts
(  
	tAddr,
	iMemClk,
	current
);


input [2:0]		iDir;
input 			iMemClk;
input				iPClk;
input 			iRst;
input [10:0]	iVGA_X;
input [10:0]	iVGA_Y;
input				iFireTorpedo;
input				iCollision;


output			oDrawPixel;
wire				oDrawPixel;


reg collided;
reg rstCollided;
reg collision;
wire didCollide;
reg fired;
wire firing;
reg done;
reg [2:0]	direction;
reg [10:0] pos_X;
reg [10:0] pos_Y;
wire [2:0] col;
wire [2:0] row;
wire inPosition;
wire drawTorpedo;
wire	[2:0]  tAddr;
wire  [4:0] current;
reg [19:0] cnt;
wire [19:0] maxCount;


parameter [10:0] INIT_X = 320;
parameter [10:0] INIT_Y = 240;



assign didCollide = collided ^ rstCollided;

always@( negedge iPClk)
begin
	if(iCollision == 1 && oDrawPixel == 1)
	begin
		collision = 1;
	end
	else
	begin
		collision = 0;
	end
end


always@(posedge collision)
begin
	collided = ~collided;
end


assign firing = fired ^ done;

always@(posedge iFireTorpedo)
begin
	if(!firing)
	begin
		direction = iDir;
		fired = ~fired;
	end
	else
	begin
	end
end


assign col = iVGA_X - pos_X;
assign row = iVGA_Y - pos_Y;

assign inPosition = ((iVGA_X - pos_X)) < 5 && ((iVGA_Y - pos_Y) < 5);
assign drawTorpedo = inPosition && firing;
assign oDrawPixel = (drawTorpedo) ? current[col] : 0 ;

initial
begin
	fired = 0;
	done = 0;
	pos_X = 10'b1111111111;
	pos_Y = 10'b1111111111;
end



assign maxCount = ((direction%2) == 1) ? 20'h7FFFF : 20'h5A826 ;
assign tAddr =  row;


always@(posedge iMemClk or negedge iRst)
begin
	if(!iRst)
	begin
		if (didCollide)
		begin
			rstCollided = ~rstCollided;
		end
		else
		begin
		end
		if(firing)
		begin
			done = ~done;
		end
		else
		begin
		end
		pos_X = 10'b1111111111;
		pos_Y = 10'b1111111111;
	end
	else if(didCollide)
	begin
		rstCollided = ~rstCollided;
		done = ~done;
		pos_X = 10'b1111111111;
		pos_Y = 10'b1111111111;
	end
	else if(firing)
	begin
		if(pos_X == 10'b1111111111)
		begin
			pos_X = INIT_X;
			pos_Y = INIT_Y;
			cnt = 0;
		end
		else
		begin
			if(cnt < maxCount)
				cnt = cnt + 1'b1;
			else
				cnt = 0;
				
			if (cnt == 0)
			begin
				case (direction)
					3'b000 :  pos_Y = pos_Y - 1'b1;
					3'b001 :  pos_Y = pos_Y - 1'b1;
					3'b010 :  pos_Y = pos_Y;
					3'b011 :  pos_Y = pos_Y + 1'b1;
					3'b100 :  pos_Y = pos_Y + 1'b1;
					3'b101 :  pos_Y = pos_Y + 1'b1;
					3'b110 :  pos_Y = pos_Y;
					3'b111 :  pos_Y = pos_Y - 1'b1;
				default: begin end
				endcase
				
				case (direction)
					3'b000 :  pos_X = pos_X;
					3'b001 :  pos_X = pos_X - 1'b1;
					3'b010 :  pos_X = pos_X - 1'b1;
					3'b011 :  pos_X = pos_X - 1'b1;
					3'b100 :  pos_X = pos_X;
					3'b101 :  pos_X = pos_X + 1'b1;
					3'b110 :  pos_X = pos_X + 1'b1;
					3'b111 :  pos_X = pos_X + 1'b1;	
				default: begin end
				endcase

				if(pos_Y > 480 || pos_X > 640)
				begin

					done = ~done;
					pos_X = 10'b1111111111;
					pos_Y = 10'b1111111111;
				end
				else
				begin
				end
			end
			else
			begin
			end
		end
	end
	else
	begin

		pos_X = 10'b1111111111;
		pos_Y = 10'b1111111111;
	end
end
endmodule
module Torpedo (
		iRst,
		iMemClk,
		iPClk,

		iDir,
		iFireTorpedo,

		iVGA_X,
		iVGA_Y,
		oDrawPixel,
		iCollision
);





torpedoSprite ts
(  
	tAddr,
	iMemClk,
	current
);


input [2:0]		iDir;
input 			iMemClk;
input				iPClk;
input 			iRst;
input [10:0]	iVGA_X;
input [10:0]	iVGA_Y;
input				iFireTorpedo;
input				iCollision;


output			oDrawPixel;
wire				oDrawPixel;


reg collided;
reg rstCollided;
reg collision;
wire didCollide;
reg fired;
wire firing;
reg done;
reg [2:0]	direction;
reg [10:0] pos_X;
reg [10:0] pos_Y;
wire [2:0] col;
wire [2:0] row;
wire inPosition;
wire drawTorpedo;
wire	[2:0]  tAddr;
wire  [4:0] current;
reg [19:0] cnt;
wire [19:0] maxCount;


parameter [10:0] INIT_X = 320;
parameter [10:0] INIT_Y = 240;



assign didCollide = collided ^ rstCollided;

always@( negedge iPClk)
begin
	if(iCollision == 1 && oDrawPixel == 1)
	begin
		collision = 1;
	end
	else
	begin
		collision = 0;
	end
end


always@(posedge collision)
begin
	collided = ~collided;
end


assign firing = fired ^ done;

always@(posedge iFireTorpedo)
begin
	if(!firing)
	begin
		direction = iDir;
		fired = ~fired;
	end
	else
	begin
	end
end


assign col = iVGA_X - pos_X;
assign row = iVGA_Y - pos_Y;

assign inPosition = ((iVGA_X - pos_X)) < 5 && ((iVGA_Y - pos_Y) < 5);
assign drawTorpedo = inPosition && firing;
assign oDrawPixel = (drawTorpedo) ? current[col] : 0 ;

initial
begin
	fired = 0;
	done = 0;
	pos_X = 10'b1111111111;
	pos_Y = 10'b1111111111;
end



assign maxCount = ((direction%2) == 1) ? 20'h7FFFF : 20'h5A826 ;
assign tAddr =  row;


always@(posedge iMemClk or negedge iRst)
begin
	if(!iRst)
	begin
		if (didCollide)
		begin
			rstCollided = ~rstCollided;
		end
		else
		begin
		end
		if(firing)
		begin
			done = ~done;
		end
		else
		begin
		end
		pos_X = 10'b1111111111;
		pos_Y = 10'b1111111111;
	end
	else if(didCollide)
	begin
		rstCollided = ~rstCollided;
		done = ~done;
		pos_X = 10'b1111111111;
		pos_Y = 10'b1111111111;
	end
	else if(firing)
	begin
		if(pos_X == 10'b1111111111)
		begin
			pos_X = INIT_X;
			pos_Y = INIT_Y;
			cnt = 0;
		end
		else
		begin
			if(cnt < maxCount)
				cnt = cnt + 1'b1;
			else
				cnt = 0;
				
			if (cnt == 0)
			begin
				case (direction)
					3'b000 :  pos_Y = pos_Y - 1'b1;
					3'b001 :  pos_Y = pos_Y - 1'b1;
					3'b010 :  pos_Y = pos_Y;
					3'b011 :  pos_Y = pos_Y + 1'b1;
					3'b100 :  pos_Y = pos_Y + 1'b1;
					3'b101 :  pos_Y = pos_Y + 1'b1;
					3'b110 :  pos_Y = pos_Y;
					3'b111 :  pos_Y = pos_Y - 1'b1;
				default: begin end
				endcase
				
				case (direction)
					3'b000 :  pos_X = pos_X;
					3'b001 :  pos_X = pos_X - 1'b1;
					3'b010 :  pos_X = pos_X - 1'b1;
					3'b011 :  pos_X = pos_X - 1'b1;
					3'b100 :  pos_X = pos_X;
					3'b101 :  pos_X = pos_X + 1'b1;
					3'b110 :  pos_X = pos_X + 1'b1;
					3'b111 :  pos_X = pos_X + 1'b1;	
				default: begin end
				endcase

				if(pos_Y > 480 || pos_X > 640)
				begin

					done = ~done;
					pos_X = 10'b1111111111;
					pos_Y = 10'b1111111111;
				end
				else
				begin
				end
			end
			else
			begin
			end
		end
	end
	else
	begin

		pos_X = 10'b1111111111;
		pos_Y = 10'b1111111111;
	end
end
endmodule