data/full_repos/permissive/188024377/practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/alu32.v
1: b'%Warning-WIDTH: data/full_repos/permissive/188024377/practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/alu32.v:27: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                                                     : ... In instance alu\n assign S = A + Bout + F[2];\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/188024377/practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/alu32.v:34: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                                                                                     : ... In instance alu\n   2\'b11: Y <= S[31];\n            ^~\n%Error: Exiting due to 2 warning(s)\n'
module alu(	input [31:0] A, B, input [2:0] F, 
					output reg [31:0] Y, output Zero);
	
	wire [31:0] S, Bout;
	
	assign Bout = F[2] ? ~B : B;
	assign S = A + Bout + F[2];

	always @ ( * )
		case (F[1:0])
			2'b00: Y <= A & Bout;
			2'b01: Y <= A | Bout;
			2'b10: Y <= S;
			2'b11: Y <= S[31];
		endcase
	
	assign Zero = (Y == 32'b0);



endmodule
module alu(	input [31:0] A, B, input [2:0] F, 
					output reg [31:0] Y, output Zero);

	
	wire [31:0] S, Bout;
	
	assign Bout = F[2] ? ~B : B;
	assign S = A + Bout + F[2];

	always @ ( * )
		case (F[1:0])
			2'b00: Y <= A & Bout;
			2'b01: Y <= A | Bout;
			2'b10: Y <= S;
			2'b11: Y <= S[31];
		endcase
	
	assign Zero = (Y == 32'b0);



endmodule