data/full_repos/permissive/175197601/hdl/jtpopeye_buf.v
1: b'%Warning-WIDTH: data/full_repos/permissive/175197601/hdl/jtpopeye_buf.v:69: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                          : ... In instance jtpopeye_buf\nwire [8:0] objy   = DO[15:8];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/175197601/hdl/jtpopeye_buf.v:84: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                          : ... In instance jtpopeye_buf\n    inzone0 = objy + V;\n            ^\n%Error: data/full_repos/permissive/175197601/hdl/jtpopeye_buf.v:125: Cannot find file containing module: \'jtframe_ram\'\njtframe_ram #(.aw(6), .dw(18),.simhexfile("objtest.hex")) u_ram0(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175197601/hdl,data/full_repos/permissive/175197601/jtframe_ram\n             data/full_repos/permissive/175197601/hdl,data/full_repos/permissive/175197601/jtframe_ram.v\n             data/full_repos/permissive/175197601/hdl,data/full_repos/permissive/175197601/jtframe_ram.sv\n             jtframe_ram\n             jtframe_ram.v\n             jtframe_ram.sv\n             obj_dir/jtframe_ram\n             obj_dir/jtframe_ram.v\n             obj_dir/jtframe_ram.sv\n%Error: data/full_repos/permissive/175197601/hdl/jtpopeye_buf.v:135: Cannot find file containing module: \'jtframe_ram\'\njtframe_ram #(.aw(6), .dw(18),.simhexfile("objtest.hex")) u_ram1(\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module jtpopeye_buf(    
    input               rst_n,
    input               clk,
    input               H0_cen,
    input               pxl_cen,

    input               ROHVS,
    input               ROHVCK,
    input               RV_n,

    input      [ 7:0]   H,
    input               HB,
    input      [ 7:0]   V,
    input               H2O,
    input      [28:0]   DO,

    output reg [ 8:0]   ROVI,
    output reg [17:0]   DJ
);



reg [2:0] adder_data;

always @(*) begin
    ROVI =  { 1'b0, DO[15:8] } + { 1'b0, V[7:0] } 
        + { 8'd0, RV_n ^ ROHVCK };

    adder_data = {3{DO[27]}} ^ ROVI[2:0];
end

reg [17:0] ram0_din, ram1_din;

wire [5:0] scan_addr = { H[7:3], H2O };
wire [5:0] wr_addr   = DO[7:2];

reg [5:0] ADR0, ADR1;
wire [17:0] DJ0, DJ1;
wire line_sel0 =  V[0];
wire line_sel1 = ~V[0];

reg we0, we1;




wire [8:0] objy   = DO[15:8];
`ifdef SIMULATION
wire [7:0] objx   = DO[ 7:0];
wire    objbank   = DO[28];
wire [2:0] objpal = DO[26:24];
wire    hflip     = DO[23];
wire    vflip     = DO[27];
wire [6:0] objid  = DO[22:16];
`endif

reg [7:0] inzone0;
reg [3:0] inzone1;
reg       inzone_b;

always @(*) begin
    inzone0 = objy + V;
    { inzone_b, inzone1 } = { 1'b0, inzone0[7:4] } + 5'hf + {4'h0, inzone0[3] };
end

wire we_cmp = H[0]==1'b0 && !inzone_b && !ROHVS;

always @(posedge clk) begin
    ADR0 <= line_sel0 ? scan_addr : wr_addr;
    ADR1 <= line_sel1 ? scan_addr : wr_addr;

    `ifndef OBJTEST
    we0      <= line_sel0 ? (H[1:0]==2'b11 && !HB): we_cmp;
    we1      <= line_sel1 ? (H[1:0]==2'b11 && !HB): we_cmp;
    `else 
    we0 <= 1'b0;
    we1 <= 1'b0;
    `endif
    ram0_din <= { DO[28], DO[26:24]&{3{~line_sel0}},
            DO[1:0], DO[23:21], DO[20:16], 
            adder_data, DO[27] };

    ram1_din <= { 
            DO[28],
            DO[26:24]&{3{~line_sel1}},
            DO[1:0],
            DO[23],
            DO[22:16],
            adder_data,
            DO[27] };
end









wire [2:0] objy0, objy1;

jtframe_ram #(.aw(6), .dw(18),.simhexfile("objtest.hex")) u_ram0(
    .clk    ( clk            ),
    .cen    ( pxl_cen        ),
    .data   ( ram0_din       ),
    .addr   ( ADR0           ),
    .we     ( we0            ),
    .q      ( DJ0[17:0]      )
);


jtframe_ram #(.aw(6), .dw(18),.simhexfile("objtest.hex")) u_ram1(
    .clk    ( clk            ),
    .cen    ( pxl_cen        ),
    .data   ( ram1_din       ),
    .addr   ( ADR1           ),
    .we     ( we1            ),
    .q      ( DJ1[17:0]      )
);




always @(posedge clk) if(pxl_cen)
    if( !H[0] ) DJ <= line_sel1 ? DJ1 : DJ0;

endmodule
module jtpopeye_buf(    
    input               rst_n,
    input               clk,
    input               H0_cen,
    input               pxl_cen,

    input               ROHVS,
    input               ROHVCK,
    input               RV_n,

    input      [ 7:0]   H,
    input               HB,
    input      [ 7:0]   V,
    input               H2O,
    input      [28:0]   DO,

    output reg [ 8:0]   ROVI,
    output reg [17:0]   DJ
);




reg [2:0] adder_data;

always @(*) begin
    ROVI =  { 1'b0, DO[15:8] } + { 1'b0, V[7:0] } 
        + { 8'd0, RV_n ^ ROHVCK };

    adder_data = {3{DO[27]}} ^ ROVI[2:0];
end

reg [17:0] ram0_din, ram1_din;

wire [5:0] scan_addr = { H[7:3], H2O };
wire [5:0] wr_addr   = DO[7:2];

reg [5:0] ADR0, ADR1;
wire [17:0] DJ0, DJ1;
wire line_sel0 =  V[0];
wire line_sel1 = ~V[0];

reg we0, we1;




wire [8:0] objy   = DO[15:8];
`ifdef SIMULATION
wire [7:0] objx   = DO[ 7:0];
wire    objbank   = DO[28];
wire [2:0] objpal = DO[26:24];
wire    hflip     = DO[23];
wire    vflip     = DO[27];
wire [6:0] objid  = DO[22:16];
`endif

reg [7:0] inzone0;
reg [3:0] inzone1;
reg       inzone_b;

always @(*) begin
    inzone0 = objy + V;
    { inzone_b, inzone1 } = { 1'b0, inzone0[7:4] } + 5'hf + {4'h0, inzone0[3] };
end

wire we_cmp = H[0]==1'b0 && !inzone_b && !ROHVS;

always @(posedge clk) begin
    ADR0 <= line_sel0 ? scan_addr : wr_addr;
    ADR1 <= line_sel1 ? scan_addr : wr_addr;

    `ifndef OBJTEST
    we0      <= line_sel0 ? (H[1:0]==2'b11 && !HB): we_cmp;
    we1      <= line_sel1 ? (H[1:0]==2'b11 && !HB): we_cmp;
    `else 
    we0 <= 1'b0;
    we1 <= 1'b0;
    `endif
    ram0_din <= { DO[28], DO[26:24]&{3{~line_sel0}},
            DO[1:0], DO[23:21], DO[20:16], 
            adder_data, DO[27] };

    ram1_din <= { 
            DO[28],
            DO[26:24]&{3{~line_sel1}},
            DO[1:0],
            DO[23],
            DO[22:16],
            adder_data,
            DO[27] };
end









wire [2:0] objy0, objy1;

jtframe_ram #(.aw(6), .dw(18),.simhexfile("objtest.hex")) u_ram0(
    .clk    ( clk            ),
    .cen    ( pxl_cen        ),
    .data   ( ram0_din       ),
    .addr   ( ADR0           ),
    .we     ( we0            ),
    .q      ( DJ0[17:0]      )
);


jtframe_ram #(.aw(6), .dw(18),.simhexfile("objtest.hex")) u_ram1(
    .clk    ( clk            ),
    .cen    ( pxl_cen        ),
    .data   ( ram1_din       ),
    .addr   ( ADR1           ),
    .we     ( we1            ),
    .q      ( DJ1[17:0]      )
);




always @(posedge clk) if(pxl_cen)
    if( !H[0] ) DJ <= line_sel1 ? DJ1 : DJ0;

endmodule