data/full_repos/permissive/217347804/DE2-115/part1.v
1: b"%Error: data/full_repos/permissive/217347804/DE2-115/part1.v:82: Cannot find file containing module: 'UART_RX'\n  UART_RX uart_1(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217347804/DE2-115,data/full_repos/permissive/217347804/UART_RX\n             data/full_repos/permissive/217347804/DE2-115,data/full_repos/permissive/217347804/UART_RX.v\n             data/full_repos/permissive/217347804/DE2-115,data/full_repos/permissive/217347804/UART_RX.sv\n             UART_RX\n             UART_RX.v\n             UART_RX.sv\n             obj_dir/UART_RX\n             obj_dir/UART_RX.v\n             obj_dir/UART_RX.sv\n%Error: data/full_repos/permissive/217347804/DE2-115/part1.v:107: Cannot find file containing module: 'clock_generator'\n clock_generator my_clock_gen(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/217347804/DE2-115/part1.v:116: Cannot find file containing module: 'audio_and_video_config'\n audio_and_video_config cfg(\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/217347804/DE2-115/part1.v:126: Cannot find file containing module: 'audio_codec'\n audio_codec codec(\n ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module part1 (CLOCK_50, CLOCK2_50, KEY, SW, I2C_SCLK, I2C_SDAT, AUD_XCK,
	AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK, AUD_ADCDAT, AUD_DACDAT, GPIO, LEDG);
	


	input CLOCK_50, CLOCK2_50;
	input [0:0] KEY;
	input [1:0] SW;
	output [0:0] LEDG;

	output I2C_SCLK;
	inout I2C_SDAT;

	output AUD_XCK;
	input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK;
	input AUD_ADCDAT;
	output AUD_DACDAT;

	inout [35:0] GPIO;


	wire read_ready, write_ready, read, write;
	wire [23:0] readdata_left, readdata_right;
	reg [23:0] writedata_left, writedata_right;
	wire reset = ~KEY[0];

	wire [7:0] dial;
	wire [23:0] scaleFactor;
	reg [3:0] zeroByteL = 4'd0;
	reg [11:0] zeroByteR = 12'd0;




	

	assign GPIO[3] = 1'b1;
	

	assign LEDG[0] = KEY[0];
	

	assign read = read_ready && write_ready;
	assign write = read_ready && write_ready;
	

	assign scaleFactor = {zeroByteL, dial, zeroByteR};

	always @(*)
	begin
		
		writedata_left <= (readdata_left * scaleFactor) / scaleFactor;
		writedata_right <= (readdata_right * scaleFactor) / scaleFactor;
		

	end
	
	

	 UART_RX uart_1(

	 	CLOCK_50, 
	 	reset, 
	 	GPIO[1], 
	 	

	 	dial
	 );
















	clock_generator my_clock_gen(

	CLOCK2_50,
	reset,


	AUD_XCK
	);

	audio_and_video_config cfg(

	CLOCK_50,
	reset,


	I2C_SDAT,
	I2C_SCLK
	);

	audio_codec codec(

	CLOCK_50,
	reset,

	read,	write,
	writedata_left, writedata_right,

	AUD_ADCDAT,


	AUD_BCLK,
	AUD_ADCLRCK,
	AUD_DACLRCK,


	read_ready, write_ready,
	readdata_left, readdata_right,
	AUD_DACDAT
	);

endmodule
module part1 (CLOCK_50, CLOCK2_50, KEY, SW, I2C_SCLK, I2C_SDAT, AUD_XCK,
	AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK, AUD_ADCDAT, AUD_DACDAT, GPIO, LEDG);

	


	input CLOCK_50, CLOCK2_50;
	input [0:0] KEY;
	input [1:0] SW;
	output [0:0] LEDG;

	output I2C_SCLK;
	inout I2C_SDAT;

	output AUD_XCK;
	input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK;
	input AUD_ADCDAT;
	output AUD_DACDAT;

	inout [35:0] GPIO;


	wire read_ready, write_ready, read, write;
	wire [23:0] readdata_left, readdata_right;
	reg [23:0] writedata_left, writedata_right;
	wire reset = ~KEY[0];

	wire [7:0] dial;
	wire [23:0] scaleFactor;
	reg [3:0] zeroByteL = 4'd0;
	reg [11:0] zeroByteR = 12'd0;




	

	assign GPIO[3] = 1'b1;
	

	assign LEDG[0] = KEY[0];
	

	assign read = read_ready && write_ready;
	assign write = read_ready && write_ready;
	

	assign scaleFactor = {zeroByteL, dial, zeroByteR};

	always @(*)
	begin
		
		writedata_left <= (readdata_left * scaleFactor) / scaleFactor;
		writedata_right <= (readdata_right * scaleFactor) / scaleFactor;
		

	end
	
	

	 UART_RX uart_1(

	 	CLOCK_50, 
	 	reset, 
	 	GPIO[1], 
	 	

	 	dial
	 );
















	clock_generator my_clock_gen(

	CLOCK2_50,
	reset,


	AUD_XCK
	);

	audio_and_video_config cfg(

	CLOCK_50,
	reset,


	I2C_SDAT,
	I2C_SCLK
	);

	audio_codec codec(

	CLOCK_50,
	reset,

	read,	write,
	writedata_left, writedata_right,

	AUD_ADCDAT,


	AUD_BCLK,
	AUD_ADCLRCK,
	AUD_DACLRCK,


	read_ready, write_ready,
	readdata_left, readdata_right,
	AUD_DACDAT
	);

endmodule