data/full_repos/permissive/151959236/FullAdder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/151959236/FullAdder.v:25: Unsupported: Ignoring delay on this delayed statement.\n #5 A=1\'b0;B=1\'b1;Cin=1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/151959236/FullAdder.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 A=1\'b1;B=1\'b0;Cin=1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/151959236/FullAdder.v:27: Unsupported: Ignoring delay on this delayed statement.\n #5 A=1\'b1;B=1\'b1;Cin=1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/151959236/FullAdder.v:28: Unsupported: Ignoring delay on this delayed statement.\n #5 A=1\'b0;B=1\'b0;Cin=1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/151959236/FullAdder.v:29: Unsupported: Ignoring delay on this delayed statement.\n #5 A=1\'b0;B=1\'b1;Cin=1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/151959236/FullAdder.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 A=1\'b1;B=1\'b0;Cin=1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/151959236/FullAdder.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5 A=1\'b1;B=1\'b1;Cin=1\'b1;\n ^\n%Error: data/full_repos/permissive/151959236/FullAdder.v:35: Unsupported or unknown PLI call: $monitor\n $monitor($time,"A=%b,B=%b,Cin=%b---S=%b,Cout=%b",A,B,Cin,S,Cout);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Hatest;
reg A,B;
reg Cin;
wire S;
wire Cout;

FullAdder fa1(A,B,Cin,S,Cout);

initial 
begin
	A=1'b0;B=1'b0;Cin=1'b0;
	#5 A=1'b0;B=1'b1;Cin=1'b0;
	#5 A=1'b1;B=1'b0;Cin=1'b0;
	#5 A=1'b1;B=1'b1;Cin=1'b0;
	#5 A=1'b0;B=1'b0;Cin=1'b1;
	#5 A=1'b0;B=1'b1;Cin=1'b1;
	#5 A=1'b1;B=1'b0;Cin=1'b1;
	#5 A=1'b1;B=1'b1;Cin=1'b1;
end

initial 
	$monitor($time,"A=%b,B=%b,Cin=%b---S=%b,Cout=%b",A,B,Cin,S,Cout);

endmodule
module Hatest;

reg A,B;
reg Cin;
wire S;
wire Cout;

FullAdder fa1(A,B,Cin,S,Cout);

initial 
begin
	A=1'b0;B=1'b0;Cin=1'b0;
	#5 A=1'b0;B=1'b1;Cin=1'b0;
	#5 A=1'b1;B=1'b0;Cin=1'b0;
	#5 A=1'b1;B=1'b1;Cin=1'b0;
	#5 A=1'b0;B=1'b0;Cin=1'b1;
	#5 A=1'b0;B=1'b1;Cin=1'b1;
	#5 A=1'b1;B=1'b0;Cin=1'b1;
	#5 A=1'b1;B=1'b1;Cin=1'b1;
end

initial 
	$monitor($time,"A=%b,B=%b,Cin=%b---S=%b,Cout=%b",A,B,Cin,S,Cout);

endmodule