data/full_repos/permissive/216344104/sincos.v
data/verilator_xmls/39f14954-b1c9-495b-be31-1e6ec62b0dd1.xml
module hmadd(
  input signed [15:0] a,
  input signed [15:0] b,
  input signed [15:0] c,
  output signed [15:0] p);
  wire [31:0] xx = a * b;
  assign p = xx[31:16] + c;
endmodule
module hmadd(
  input signed [15:0] a,
  input signed [15:0] b,
  input signed [15:0] c,
  output signed [15:0] p);

  wire [31:0] xx = a * b;
  assign p = xx[31:16] + c;
endmodule