data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v
None: at end of input
1: b'%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:2: Cannot find include file: ./build/sintetizado.v\n  `include "./build/sintetizado.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100331186/tarea5/sin-retrasos/src,data/full_repos/permissive/100331186/./build/sintetizado.v\n             data/full_repos/permissive/100331186/tarea5/sin-retrasos/src,data/full_repos/permissive/100331186/./build/sintetizado.v.v\n             data/full_repos/permissive/100331186/tarea5/sin-retrasos/src,data/full_repos/permissive/100331186/./build/sintetizado.v.sv\n             ./build/sintetizado.v\n             ./build/sintetizado.v.v\n             ./build/sintetizado.v.sv\n             obj_dir/./build/sintetizado.v\n             obj_dir/./build/sintetizado.v.v\n             obj_dir/./build/sintetizado.v.sv\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:5: Cannot find include file: ./modulos/sreg.v\n  `include "./modulos/sreg.v" \n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:7: Cannot find include file: ./lib/cmos_cells.v\n`include "./lib/cmos_cells.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:58: Unsupported: Ignoring delay on this delayed statement.\n  initial # 50 clk = 0;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n  always # 17.4 clk = ~clk;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:77: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:78: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:89: Unsupported: Ignoring delay on this delayed statement.\n    # 10;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:91: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:97: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:99: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:104: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:106: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:111: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:113: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:118: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:120: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:125: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:127: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:133: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:135: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:140: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:142: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:147: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:149: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:154: Unsupported: Ignoring delay on this delayed statement.\n    # 50;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:156: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:163: Unsupported: Ignoring delay on this delayed statement.\n    # 200\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:167: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:173: Unsupported: Ignoring delay on this delayed statement.\n    # 400\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:175: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:178: Unsupported: Ignoring delay on this delayed statement.\n    # 400\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:181: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:185: Unsupported: Ignoring delay on this delayed statement.\n    # 400\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:187: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:190: Unsupported: Ignoring delay on this delayed statement.\n    # 90\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:192: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:195: Unsupported: Ignoring delay on this delayed statement.\n    # 60\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:197: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:200: Unsupported: Ignoring delay on this delayed statement.\n    # 40\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:202: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:205: Unsupported: Ignoring delay on this delayed statement.\n    # 550;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:206: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:210: Unsupported: Ignoring delay on this delayed statement.\n    # 60;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:212: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:220: Unsupported: Ignoring delay on this delayed statement.\n    # 200\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:223: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:228: Unsupported: Ignoring delay on this delayed statement.\n    # 400\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:230: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:233: Unsupported: Ignoring delay on this delayed statement.\n    # 550;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:234: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:245: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tests/rdesplazante.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:246: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:251: Unsupported or unknown PLI call: $monitor\n    $monitor            ("%t| %b   | %b   | %b    | %b   | %b | %b | %b     | %f ns",\n    ^~~~~~~~\n%Error: Exiting due to 29 error(s), 25 warning(s)\n'
module testregistro4bits ();

  wire [3:0] qe;
  wire s_oute;

  reg clk;
  reg enb;
  reg dir;
  reg s_in;

  reg [1:0] modo;
  reg [3:0] d;

  wire [3:0] qc;
  wire s_outc;

  real cambioqc;
  real cambioqe;
  real cambiosoc;
  real cambiosoe;
  real tp = 43;
  integer contador = 0;


rdesplazante estructural(
  .CLK(clk),
  .ENB(enb),
  .DIR(dir),
  .S_IN(s_in),
  .MODE(modo),
  .D(d),
  .Q(qe),
  .S_OUT(s_oute)
);

rdesplazanteconduct conductual(
  .CLK(clk),
  .ENB(enb),
  .DIR(dir),
  .S_IN(s_in),
  .MODE(modo),
  .D(d),
  .Q(qc),
  .S_OUT(s_outc)
);


  initial # 50 clk = 0;

  always # 17.4 clk = ~clk;

  always @(qe) cambioqe = $time;
  always @(qc) cambioqc = $time;
  always @(s_outc) cambiosoc = $time;
  always @(s_oute) cambiosoe = $time;

  always @(qe, qc) begin
    if (qe != qc) $display("<<<<<<<<<<<<<<<<Hay diferencias entre las salidas  q  >>>>>>>>>>>>>>>>>>>");
  end

  always @(s_outc, s_oute) begin
    if (s_outc != s_oute) $display("<<<<<<<<<<<<<<<<Hay diferencias entre las salidas s_out  >>>>>>>>>>>>>>>>>>>");
  end

  initial begin

    # 50;
    @(posedge clk);
    modo <= 2'b00;









    # 10;
    $display("se carga 0000");
    @(posedge clk);
      enb <= 1;
      modo <= 2'b10;
      d <= 4'b0000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0001");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0001;
      dir <= 1'bx;

    # 50;
    $display("se carga 0010");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0010;
      dir <= 1'bx;

    # 50;
    $display("se carga 0100");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0100;
      dir <= 1'bx;

    # 50;
    $display("se carga 1000");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b1000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0000");
    @(posedge clk);
      enb <= 1;
      modo <= 2'b10;
      d <= 4'b0000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0001");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0001;
      dir <= 1'bx;

    # 50;
    $display("se carga 0011");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0011;
      dir <= 1'bx;

    # 50;
    $display("se carga 0111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0111;
      dir <= 1'bx;

    # 50;
    $display("se carga 1111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b1111;
      dir <= 1'bx;



    # 200
    $display("---\nModo de Carga en Serie\n---");
    $display("Hacia la izquierda");
    $display("con s_in = 0");
    @(posedge clk);
      d <= 4'bzzzz;
      modo <= 2'b00;
      dir <= 1'b0;
      s_in <= 2'b0;

    # 400
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1;

    # 400
    $display("Hacia la derecha");
    $display("con s_in = 0");
    @(posedge clk);
      dir <= 1'b1;
      s_in <= 0;

    # 400
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b1;

    # 90
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b0;

    # 60
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b1;

    # 40
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b0;

    # 550;
    @(posedge clk);


   $display("Hacemos otra carga paralela antes de la rotacion circular");
    # 60;
    $display("se carga 0111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0111;
      dir <= 1'bx;




    # 200
    $display("---\nModo de rotacion circular\n---");
    $display("Hacia la izquierda");
    @(posedge clk);
      d <= 4'bzzzz;
      modo <= 2'b01;
      dir <= 1'b0;

    # 400
    $display("Hacia la derecha");
    @(posedge clk);
      dir <= 1'b1;

    # 550;
    @(posedge clk);

    $display("------------------------------------------------------------------------------------------");
    $display("## FIN COMPARACION DE SINTESIS SIN TIEMPOS DE RETRASO DE YOSYS Y DESCRIPCION CONDUCTUAL ##");
    $display("------------------------------------------------------------------------------------------");
    $display("Cantidad de diferencias totales: %d", contador);
    $finish;
  end

  initial
    begin
    $dumpfile("tests/rdesplazante.vcd");
    $dumpvars;
    $display("------------------------------------");
    $display("-- Test para modulo rdesplazante  --");
    $display("------------------------------------");
    $display ("\t     tiempo | enb | dir | s_in | modo | d    | q    | s_out | tiempo");
    $monitor            ("%t| %b   | %b   | %b    | %b   | %b | %b | %b     | %f ns",
                          $time, enb, dir, s_in, modo, d, qc, s_outc , $realtime);
  end
endmodule
module testregistro4bits ();


  wire [3:0] qe;
  wire s_oute;

  reg clk;
  reg enb;
  reg dir;
  reg s_in;

  reg [1:0] modo;
  reg [3:0] d;

  wire [3:0] qc;
  wire s_outc;

  real cambioqc;
  real cambioqe;
  real cambiosoc;
  real cambiosoe;
  real tp = 43;
  integer contador = 0;


rdesplazante estructural(
  .CLK(clk),
  .ENB(enb),
  .DIR(dir),
  .S_IN(s_in),
  .MODE(modo),
  .D(d),
  .Q(qe),
  .S_OUT(s_oute)
);

rdesplazanteconduct conductual(
  .CLK(clk),
  .ENB(enb),
  .DIR(dir),
  .S_IN(s_in),
  .MODE(modo),
  .D(d),
  .Q(qc),
  .S_OUT(s_outc)
);


  initial # 50 clk = 0;

  always # 17.4 clk = ~clk;

  always @(qe) cambioqe = $time;
  always @(qc) cambioqc = $time;
  always @(s_outc) cambiosoc = $time;
  always @(s_oute) cambiosoe = $time;

  always @(qe, qc) begin
    if (qe != qc) $display("<<<<<<<<<<<<<<<<Hay diferencias entre las salidas  q  >>>>>>>>>>>>>>>>>>>");
  end

  always @(s_outc, s_oute) begin
    if (s_outc != s_oute) $display("<<<<<<<<<<<<<<<<Hay diferencias entre las salidas s_out  >>>>>>>>>>>>>>>>>>>");
  end

  initial begin

    # 50;
    @(posedge clk);
    modo <= 2'b00;









    # 10;
    $display("se carga 0000");
    @(posedge clk);
      enb <= 1;
      modo <= 2'b10;
      d <= 4'b0000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0001");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0001;
      dir <= 1'bx;

    # 50;
    $display("se carga 0010");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0010;
      dir <= 1'bx;

    # 50;
    $display("se carga 0100");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0100;
      dir <= 1'bx;

    # 50;
    $display("se carga 1000");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b1000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0000");
    @(posedge clk);
      enb <= 1;
      modo <= 2'b10;
      d <= 4'b0000;
      dir <= 1'bx;

    # 50;
    $display("se carga 0001");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0001;
      dir <= 1'bx;

    # 50;
    $display("se carga 0011");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0011;
      dir <= 1'bx;

    # 50;
    $display("se carga 0111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0111;
      dir <= 1'bx;

    # 50;
    $display("se carga 1111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b1111;
      dir <= 1'bx;



    # 200
    $display("---\nModo de Carga en Serie\n---");
    $display("Hacia la izquierda");
    $display("con s_in = 0");
    @(posedge clk);
      d <= 4'bzzzz;
      modo <= 2'b00;
      dir <= 1'b0;
      s_in <= 2'b0;

    # 400
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1;

    # 400
    $display("Hacia la derecha");
    $display("con s_in = 0");
    @(posedge clk);
      dir <= 1'b1;
      s_in <= 0;

    # 400
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b1;

    # 90
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b0;

    # 60
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b1;

    # 40
    $display("con s_in = 1");
    @(posedge clk);
      s_in <= 1'b0;

    # 550;
    @(posedge clk);


   $display("Hacemos otra carga paralela antes de la rotacion circular");
    # 60;
    $display("se carga 0111");
    @(posedge clk);
      modo <= 2'b10;
      d <= 4'b0111;
      dir <= 1'bx;




    # 200
    $display("---\nModo de rotacion circular\n---");
    $display("Hacia la izquierda");
    @(posedge clk);
      d <= 4'bzzzz;
      modo <= 2'b01;
      dir <= 1'b0;

    # 400
    $display("Hacia la derecha");
    @(posedge clk);
      dir <= 1'b1;

    # 550;
    @(posedge clk);

    $display("------------------------------------------------------------------------------------------");
    $display("## FIN COMPARACION DE SINTESIS SIN TIEMPOS DE RETRASO DE YOSYS Y DESCRIPCION CONDUCTUAL ##");
    $display("------------------------------------------------------------------------------------------");
    $display("Cantidad de diferencias totales: %d", contador);
    $finish;
  end

  initial
    begin
    $dumpfile("tests/rdesplazante.vcd");
    $dumpvars;
    $display("------------------------------------");
    $display("-- Test para modulo rdesplazante  --");
    $display("------------------------------------");
    $display ("\t     tiempo | enb | dir | s_in | modo | d    | q    | s_out | tiempo");
    $monitor            ("%t| %b   | %b   | %b    | %b   | %b | %b | %b     | %f ns",
                          $time, enb, dir, s_in, modo, d, qc, s_outc , $realtime);
  end
endmodule