data/full_repos/permissive/143278/ivltests/sbyte_test.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:69: Unsupported: Ignoring delay on this delayed statement.\n    # 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/143278/ivltests/sbyte_test.v:92: Unsupported: Verilog 1995 force\n        force bu = ui;\n        ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/143278/ivltests/sbyte_test.v:100: Unsupported: Verilog 1995 release\n    release bu;\n    ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/143278/ivltests/sbyte_test.v:108: Unsupported: Verilog 1995 force\n        force bu = si;\n        ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/143278/ivltests/sbyte_test.v:116: Unsupported: Verilog 1995 release\n    release bu;\n    ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:127: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/143278/ivltests/sbyte_test.v:128: Unsupported: Verilog 1995 force\n        force bu_xz = si;\n        ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/143278/ivltests/sbyte_test.v:136: Unsupported: Verilog 1995 release\n    release bu_xz;\n    ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:175: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:178: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:180: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:203: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:206: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:241: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/143278/ivltests/sbyte_test.v:243: Unsupported: Verilog 1995 force\n        force bu = slice;\n        ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:245: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/143278/ivltests/sbyte_test.v:252: Unsupported: Verilog 1995 release\n    release bu;\n    ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sbyte_test.v:253: Unsupported: Ignoring delay on this delayed statement.\n    # 1;\n    ^\n%Error: Exiting due to 8 error(s), 25 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function [LEN-1:0] xz_inject (input signed [LEN-1:0] value);
      integer i, temp;
      begin
        temp = {$random} % 2*(MAX+1);
        for (i=0; i<LEN; i=i+1)
          begin
             if (temp[i] == 1'b1)
               begin
                 temp = $random % MAX;
                 if (temp <= 0)
                    value[i] = 1'bx;
                 else
                    value[i] = 1'bz;
               end
          end
          xz_inject = value;
      end
  endfunction
function [LEN-1:0] xz_inject (input signed [LEN-1:0] value);

      integer i, temp;
      begin
        temp = {$random} % 2*(MAX+1);
        for (i=0; i<LEN; i=i+1)
          begin
             if (temp[i] == 1'b1)
               begin
                 temp = $random % MAX;
                 if (temp <= 0)
                    value[i] = 1'bx;
                 else
                    value[i] = 1'bz;
               end
          end
          xz_inject = value;
      end
  endfunction