data/full_repos/permissive/126366342/verilog modules/des_top2.v
1: b'%Error: Cannot find file containing module: modules,data/full_repos/permissive/126366342\n        ... Looked in:\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342.v\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342.sv\n             modules,data/full_repos/permissive/126366342\n             modules,data/full_repos/permissive/126366342.v\n             modules,data/full_repos/permissive/126366342.sv\n             obj_dir/modules,data/full_repos/permissive/126366342\n             obj_dir/modules,data/full_repos/permissive/126366342.v\n             obj_dir/modules,data/full_repos/permissive/126366342.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/126366342/verilog\n%Error: Cannot find file containing module: modules/des_top2.v\n%Error: Exiting due to 3 error(s)\n'
module des_top2(input [1:32] data, input [0:2] decision, output reg [1:32] data_out);

reg [1:64] data_reg;
reg [1:64]key_reg;
wire [1:64] des_wire;
reg [1:32] dumb;
initial data_reg = 64'd0;
initial key_reg = 64'd0;

always@(decision or data)
begin
 if(decision == 3'b000)
 begin
	data_reg [1:32]<= data; 
	
 end
 else if(decision == 3'b001)
 begin
	data_reg[33:64] <= data;
	
 end
 else if(decision == 3'b010)
begin
	key_reg [1:32] <= data;
	
end

else if(decision == 3'b011)
begin
	key_reg[33:64] <= data;
	
end
else
begin
	dumb = 0;
end

end

des_topmodule des2(.plaintext(data_reg),.primaryKey(key_reg),.desOutput(des_wire));
always@(decision or des_wire)
begin

if(decision == 3'b000)
 begin
	
	data_out <= des_wire[1:32];
 end
 else if(decision == 3'b001)
 begin
	
	data_out <= des_wire[33:64];
 end
 else if(decision == 3'b010)
begin
	
	data_out <= des_wire[1:32];
end

else if(decision == 3'b011)
begin
	
	data_out <= des_wire[33:64];
end
else
begin
	dumb = 0;
end


end




endmodule
module des_top2(input [1:32] data, input [0:2] decision, output reg [1:32] data_out);


reg [1:64] data_reg;
reg [1:64]key_reg;
wire [1:64] des_wire;
reg [1:32] dumb;
initial data_reg = 64'd0;
initial key_reg = 64'd0;

always@(decision or data)
begin
 if(decision == 3'b000)
 begin
	data_reg [1:32]<= data; 
	
 end
 else if(decision == 3'b001)
 begin
	data_reg[33:64] <= data;
	
 end
 else if(decision == 3'b010)
begin
	key_reg [1:32] <= data;
	
end

else if(decision == 3'b011)
begin
	key_reg[33:64] <= data;
	
end
else
begin
	dumb = 0;
end

end

des_topmodule des2(.plaintext(data_reg),.primaryKey(key_reg),.desOutput(des_wire));
always@(decision or des_wire)
begin

if(decision == 3'b000)
 begin
	
	data_out <= des_wire[1:32];
 end
 else if(decision == 3'b001)
 begin
	
	data_out <= des_wire[33:64];
 end
 else if(decision == 3'b010)
begin
	
	data_out <= des_wire[1:32];
end

else if(decision == 3'b011)
begin
	
	data_out <= des_wire[33:64];
end
else
begin
	dumb = 0;
end


end




endmodule