data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/xilinx_bram_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/xilinx_bram_fifo.v:5: Operator VAR \'ALMOST_FULL_OFFSET\' expects 32 bits on the Initial value, but Initial value\'s CONST \'9\'h80\' generates 9 bits.\n                                                                                                                               : ... In instance xilinx_bram_fifo\n    parameter integer ALMOST_FULL_OFFSET        = 9\'h080,\n                      ^~~~~~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/xilinx_bram_fifo.v:6: Operator VAR \'ALMOST_EMPTY_OFFSET\' expects 32 bits on the Initial value, but Initial value\'s CONST \'9\'h80\' generates 9 bits.\n                                                                                                                               : ... In instance xilinx_bram_fifo\n    parameter integer ALMOST_EMPTY_OFFSET       = 9\'h080,\n                      ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/xilinx_bram_fifo.v:40: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'MODE\' generates 24 bits.\n                                                                                                                                : ... In instance xilinx_bram_fifo\nif (MODE == "FPGA" || MODE == "fpga")\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/xilinx_bram_fifo.v:40: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'MODE\' generates 24 bits.\n                                                                                                                                : ... In instance xilinx_bram_fifo\nif (MODE == "FPGA" || MODE == "fpga")\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/xilinx_bram_fifo.v:73: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'FIFO_count\' generates 9 bits.\n                                                                                                                                : ... In instance xilinx_bram_fifo\n    assign RD_COUNT       = FIFO_count;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/xilinx_bram_fifo.v:74: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'FIFO_count\' generates 9 bits.\n                                                                                                                                : ... In instance xilinx_bram_fifo\n    assign WR_COUNT       = FIFO_count;\n                          ^\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/xilinx_bram_fifo.v:78: Cannot find file containing module: \'fifo\'\n    fifo #(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO,data/full_repos/permissive/150133337/fifo\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO,data/full_repos/permissive/150133337/fifo.v\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO,data/full_repos/permissive/150133337/fifo.sv\n             fifo\n             fifo.v\n             fifo.sv\n             obj_dir/fifo\n             obj_dir/fifo.v\n             obj_dir/fifo.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module xilinx_bram_fifo 
#(
    parameter integer DATA_WIDTH                = 64,
    parameter integer ALMOST_FULL_OFFSET        = 9'h080,
    parameter integer ALMOST_EMPTY_OFFSET       = 9'h080,
    parameter         FIFO_SIZE                 = "36Kb",
    parameter         FIRST_WORD_FALL_THROUGH   = "FALSE",
    parameter         MODE                      = "SIM"
)(
    input  wire                         RESET,

    input  wire                         RD_CLK,
    input  wire                         RD_EN,
    output wire                         RD_EMPTY,
    output wire                         RD_ALMOSTEMPTY,
    output wire [ DATA_WIDTH -1 : 0 ]   RD_DATA,
    output wire [ COUNT_WIDTH   : 0 ]   RD_COUNT,
    output wire                         RD_ERR,

    input  wire                         WR_CLK,
    input  wire                         WR_EN,
    output wire                         WR_FULL,
    output wire                         WR_ALMOSTFULL,
    input  wire [ DATA_WIDTH -1 : 0 ]   WR_DATA,
    output wire [ COUNT_WIDTH   : 0 ]   WR_COUNT,
    output wire                         WR_ERR
);    

localparam COUNT_WIDTH = ( (FIFO_SIZE == "18Kb") ? 
                         ( (DATA_WIDTH <= 4) ? 12 : (DATA_WIDTH > 4 && DATA_WIDTH <= 9) ? 11 : 
                         (DATA_WIDTH > 9 && DATA_WIDTH <= 18) ? 10 : (DATA_WIDTH > 18 && DATA_WIDTH <= 36) ? 9 : 12 ) : 
                         (FIFO_SIZE == "36Kb") ? 
                         ( (DATA_WIDTH <= 4) ? 13 : (DATA_WIDTH > 4 && DATA_WIDTH <=9) ? 12 : 
                         (DATA_WIDTH > 9 && DATA_WIDTH <= 18) ? 11 : (DATA_WIDTH > 18 && DATA_WIDTH <= 36) ? 10 : 
                         (DATA_WIDTH > 36 && DATA_WIDTH <= 72) ? 9 : 13 ) : 13 );

generate

if (MODE == "FPGA" || MODE == "fpga")
begin : BRAM_MACRO



    FIFO_DUALCLOCK_MACRO  #(
        .ALMOST_EMPTY_OFFSET        ( ALMOST_EMPTY_OFFSET       ),
        .ALMOST_FULL_OFFSET         ( ALMOST_FULL_OFFSET        ),
        .DATA_WIDTH                 ( DATA_WIDTH                ),
        .DEVICE                     ( "7SERIES"                 ),
        .FIFO_SIZE                  ( FIFO_SIZE                 ),
        .FIRST_WORD_FALL_THROUGH    ( FIRST_WORD_FALL_THROUGH   )
    ) FIFO_DUALCLOCK_MACRO_inst (
        .RST                        ( RESET                     ),
        .RDCLK                      ( RD_CLK                    ),
        .RDEN                       ( RD_EN                     ),
        .EMPTY                      ( RD_EMPTY                  ),
        .ALMOSTEMPTY                ( RD_ALMOSTEMPTY            ),
        .DI                         ( RD_DATA                   ),
        .RDCOUNT                    ( RD_COUNT                  ),
        .RDERR                      ( RD_ERR                    ),
        .WRCLK                      ( WR_CLK                    ),
        .WREN                       ( WR_EN                     ),
        .FULL                       ( WR_FULL                   ),
        .ALMOSTFULL                 ( WR_ALMOSTFULL             ),
        .DO                         ( WR_DATA                   ),
        .WRCOUNT                    ( WR_COUNT                  ),
        .WRERR                      ( WR_ERR                    )
    );
end else begin

    wire [COUNT_WIDTH-1:0]  FIFO_count;

    assign RD_COUNT       = FIFO_count;
    assign WR_COUNT       = FIFO_count;
    assign RD_ALMOSTEMPTY = RD_EMPTY;
    assign WR_ALMOSTFULL  = WR_FULL;

    fifo #(
        .DATA_WIDTH                 ( DATA_WIDTH                ),
        .ADDR_WIDTH                 ( COUNT_WIDTH-1             )
    ) fifo_sim (
        .clk                        ( RD_CLK                    ),
        .reset                      ( RESET                     ),
        .pop                        ( RD_EN                     ),
        .data_out                   ( RD_DATA                   ),
        .empty                      ( RD_EMPTY                  ),
        .push                       ( WR_EN                     ),
        .data_in                    ( WR_DATA                   ),
        .full                       ( WR_FULL                   ),
        .fifo_count                 ( FIFO_count                )
    );
end
endgenerate

endmodule
module xilinx_bram_fifo 
#(
    parameter integer DATA_WIDTH                = 64,
    parameter integer ALMOST_FULL_OFFSET        = 9'h080,
    parameter integer ALMOST_EMPTY_OFFSET       = 9'h080,
    parameter         FIFO_SIZE                 = "36Kb",
    parameter         FIRST_WORD_FALL_THROUGH   = "FALSE",
    parameter         MODE                      = "SIM"
)(
    input  wire                         RESET,

    input  wire                         RD_CLK,
    input  wire                         RD_EN,
    output wire                         RD_EMPTY,
    output wire                         RD_ALMOSTEMPTY,
    output wire [ DATA_WIDTH -1 : 0 ]   RD_DATA,
    output wire [ COUNT_WIDTH   : 0 ]   RD_COUNT,
    output wire                         RD_ERR,

    input  wire                         WR_CLK,
    input  wire                         WR_EN,
    output wire                         WR_FULL,
    output wire                         WR_ALMOSTFULL,
    input  wire [ DATA_WIDTH -1 : 0 ]   WR_DATA,
    output wire [ COUNT_WIDTH   : 0 ]   WR_COUNT,
    output wire                         WR_ERR
);
    

localparam COUNT_WIDTH = ( (FIFO_SIZE == "18Kb") ? 
                         ( (DATA_WIDTH <= 4) ? 12 : (DATA_WIDTH > 4 && DATA_WIDTH <= 9) ? 11 : 
                         (DATA_WIDTH > 9 && DATA_WIDTH <= 18) ? 10 : (DATA_WIDTH > 18 && DATA_WIDTH <= 36) ? 9 : 12 ) : 
                         (FIFO_SIZE == "36Kb") ? 
                         ( (DATA_WIDTH <= 4) ? 13 : (DATA_WIDTH > 4 && DATA_WIDTH <=9) ? 12 : 
                         (DATA_WIDTH > 9 && DATA_WIDTH <= 18) ? 11 : (DATA_WIDTH > 18 && DATA_WIDTH <= 36) ? 10 : 
                         (DATA_WIDTH > 36 && DATA_WIDTH <= 72) ? 9 : 13 ) : 13 );

generate

if (MODE == "FPGA" || MODE == "fpga")
begin : BRAM_MACRO



    FIFO_DUALCLOCK_MACRO  #(
        .ALMOST_EMPTY_OFFSET        ( ALMOST_EMPTY_OFFSET       ),
        .ALMOST_FULL_OFFSET         ( ALMOST_FULL_OFFSET        ),
        .DATA_WIDTH                 ( DATA_WIDTH                ),
        .DEVICE                     ( "7SERIES"                 ),
        .FIFO_SIZE                  ( FIFO_SIZE                 ),
        .FIRST_WORD_FALL_THROUGH    ( FIRST_WORD_FALL_THROUGH   )
    ) FIFO_DUALCLOCK_MACRO_inst (
        .RST                        ( RESET                     ),
        .RDCLK                      ( RD_CLK                    ),
        .RDEN                       ( RD_EN                     ),
        .EMPTY                      ( RD_EMPTY                  ),
        .ALMOSTEMPTY                ( RD_ALMOSTEMPTY            ),
        .DI                         ( RD_DATA                   ),
        .RDCOUNT                    ( RD_COUNT                  ),
        .RDERR                      ( RD_ERR                    ),
        .WRCLK                      ( WR_CLK                    ),
        .WREN                       ( WR_EN                     ),
        .FULL                       ( WR_FULL                   ),
        .ALMOSTFULL                 ( WR_ALMOSTFULL             ),
        .DO                         ( WR_DATA                   ),
        .WRCOUNT                    ( WR_COUNT                  ),
        .WRERR                      ( WR_ERR                    )
    );
end else begin

    wire [COUNT_WIDTH-1:0]  FIFO_count;

    assign RD_COUNT       = FIFO_count;
    assign WR_COUNT       = FIFO_count;
    assign RD_ALMOSTEMPTY = RD_EMPTY;
    assign WR_ALMOSTFULL  = WR_FULL;

    fifo #(
        .DATA_WIDTH                 ( DATA_WIDTH                ),
        .ADDR_WIDTH                 ( COUNT_WIDTH-1             )
    ) fifo_sim (
        .clk                        ( RD_CLK                    ),
        .reset                      ( RESET                     ),
        .pop                        ( RD_EN                     ),
        .data_out                   ( RD_DATA                   ),
        .empty                      ( RD_EMPTY                  ),
        .push                       ( WR_EN                     ),
        .data_in                    ( WR_DATA                   ),
        .full                       ( WR_FULL                   ),
        .fifo_count                 ( FIFO_count                )
    );
end
endgenerate

endmodule