data/full_repos/permissive/187712539/testbenches/tb_ALU32.v
 line:107: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/187712539/testbenches/tb_ALU32.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/187712539/testbenches/tb_ALU32.v:42: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/187712539/testbenches/tb_ALU32.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/187712539/testbenches/tb_ALU32.v:66: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/187712539/testbenches/tb_ALU32.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/187712539/testbenches/tb_ALU32.v:88: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/187712539/testbenches/tb_ALU32.v:99: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/187712539/testbenches/tb_ALU32.v:107: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/187712539/testbenches/tb_ALU32.v:110: Unsupported: Ignoring delay on this delayed statement.\n #1 clk=!clk;\n ^\n%Error: data/full_repos/permissive/187712539/testbenches/tb_ALU32.v:114: Unsupported or unknown PLI call: $monitor\n $monitor("RegFile: input1 = %d input2 = %d \\nMux: slc = %d imData = %d \\nALU: ctrl=%d output=%d overflow = %d (clk=%d) \\n ------", dataR1,dataR2,slc,Idata,ctrl,outA,ovf,clk);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_ALU32();
reg clk;
reg [4:0] rgAddR1, rgAddR2, rgAddW;
reg [31:0] dataW;
wire [31:0] dataR1, dataR2;

regfile32x32 U1 (clk,rgAddR1,rgAddR2,dataR1,dataR2,rgAddW,dataW);

reg [15:0] Idata;
reg slc;
wire [31:0] outM;

multiplaxer2x1 U2 (dataR2,Idata,slc,outM);

reg [3:0] ctrl;
wire ovf;
wire [31:0] outA;

alu32 U3 (dataR1,outM,ctrl,ovf,outA);

initial
begin
	clk=1;
	rgAddR1 = 10;
	rgAddR2 = 11;
	rgAddW = 10;

	slc = 0;
	ctrl = 0;
	
	#1
	clk=0;
	dataW = outA;


	
	rgAddR1 = 10;
	rgAddR2 = 15;

	ctrl = 1;
	
	#1
	clk=0;
	dataW = outA;


	
	rgAddR1 = 10;
	Idata = 5;
	
	slc = 1;
	ctrl = 2;

	#1
	clk=0;
	dataW = outA;


	
	rgAddR1 = 10;
	rgAddR2 = 15;

	slc = 0;
	ctrl = 6;
	
	#1
	clk=0;
	dataW = outA;


	
	rgAddR1 = 10;
	rgAddR2 = 8;

	ctrl = 7;
		
	#1
	clk=0;
	dataW = outA;


		
	rgAddR1 = 10;
	rgAddR2 = 23;

	ctrl = 12;
	
	#1
	clk=0;
	dataW = outA;


	
	rgAddR1 = 24;
	rgAddR2 = 25;

	ctrl = 2;

	#1
	clk=0;
	rgAddW = 24;
	dataW = outA;

end

initial
	#10 $finish;

always
	#1 clk=!clk;

initial
begin
	$monitor("RegFile: input1 = %d input2 = %d \nMux: slc = %d imData = %d \nALU: ctrl=%d output=%d overflow = %d (clk=%d) \n ------", dataR1,dataR2,slc,Idata,ctrl,outA,ovf,clk);
end

endmodule
module tb_ALU32();

reg clk;
reg [4:0] rgAddR1, rgAddR2, rgAddW;
reg [31:0] dataW;
wire [31:0] dataR1, dataR2;

regfile32x32 U1 (clk,rgAddR1,rgAddR2,dataR1,dataR2,rgAddW,dataW);

reg [15:0] Idata;
reg slc;
wire [31:0] outM;

multiplaxer2x1 U2 (dataR2,Idata,slc,outM);

reg [3:0] ctrl;
wire ovf;
wire [31:0] outA;

alu32 U3 (dataR1,outM,ctrl,ovf,outA);

initial
begin
	clk=1;
	rgAddR1 = 10;
	rgAddR2 = 11;
	rgAddW = 10;

	slc = 0;
	ctrl = 0;
	
	#1
	clk=0;
	dataW = outA;


	
	rgAddR1 = 10;
	rgAddR2 = 15;

	ctrl = 1;
	
	#1
	clk=0;
	dataW = outA;


	
	rgAddR1 = 10;
	Idata = 5;
	
	slc = 1;
	ctrl = 2;

	#1
	clk=0;
	dataW = outA;


	
	rgAddR1 = 10;
	rgAddR2 = 15;

	slc = 0;
	ctrl = 6;
	
	#1
	clk=0;
	dataW = outA;


	
	rgAddR1 = 10;
	rgAddR2 = 8;

	ctrl = 7;
		
	#1
	clk=0;
	dataW = outA;


		
	rgAddR1 = 10;
	rgAddR2 = 23;

	ctrl = 12;
	
	#1
	clk=0;
	dataW = outA;


	
	rgAddR1 = 24;
	rgAddR2 = 25;

	ctrl = 2;

	#1
	clk=0;
	rgAddW = 24;
	dataW = outA;

end

initial
	#10 $finish;

always
	#1 clk=!clk;

initial
begin
	$monitor("RegFile: input1 = %d input2 = %d \nMux: slc = %d imData = %d \nALU: ctrl=%d output=%d overflow = %d (clk=%d) \n ------", dataR1,dataR2,slc,Idata,ctrl,outA,ovf,clk);
end

endmodule