data/full_repos/permissive/206169433/pipeline/alu_mux.v
data/verilator_xmls/3c5deba2-6a71-45d1-b52d-0502e4267985.xml
module alu_mux(
    input       [1:0] forward,
    output reg  [31:0] out,
    input       [31:0] EX_in, WB_in, MEM_in
);    
    
    always @ (EX_in, WB_in, MEM_in, forward) begin
      if (forward == 2'b00)
        out = EX_in;
      else if (forward == 2'b01)
        out = WB_in;
      else if (forward == 2'b10)
        out = MEM_in;





    end

endmodule
module alu_mux(
    input       [1:0] forward,
    output reg  [31:0] out,
    input       [31:0] EX_in, WB_in, MEM_in
);
    
    
    always @ (EX_in, WB_in, MEM_in, forward) begin
      if (forward == 2'b00)
        out = EX_in;
      else if (forward == 2'b01)
        out = WB_in;
      else if (forward == 2'b10)
        out = MEM_in;





    end

endmodule