data/full_repos/permissive/159555381/alu.v
 line:109: before: ","
1: b'%Error: data/full_repos/permissive/159555381/alu.v:109: Unsupported or unknown PLI call: $monitor\n  $monitor($time,,, "\\n Opcode: %b A: %b B: %b Summ : %b carry: %b\\n", op, a, b, c, carry);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/159555381/alu.v:109: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  $monitor($time,,, "\\n Opcode: %b A: %b B: %b Summ : %b carry: %b\\n", op, a, b, c, carry);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/alu.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #02 op = 3\'d1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159555381/alu.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #02 op = 3\'d2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/alu.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #02 op = 3\'d3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/alu.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #02 op = 3\'d4;\n  ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MyALU(
	output [3:0] s,
	output carry,
	input [2:0] op,
	input [3:0] a, b);
	
	wire [3:0] w1, w2, w3, w4, w5;
	wire w6, w7;
	MyAdder add(w1, w6, a, b, 1'b0);
	MyAdder sub(w2, w7, a, b, 1'b1);
	MyAnd mand(w3, a, b);
	MyOr mor(w4, a, b);
	MyNot mnot(w5, a);
	MyMux mux1(s[0], w1[0], w2[0], w3[0], w4[0], w5[0], op);
	MyMux mux2(s[1], w1[1], w2[1], w3[1], w4[1], w5[1], op);
	MyMux mux3(s[2], w1[2], w2[2], w3[2], w4[2], w5[2], op);
	MyMux mux4(s[3], w1[3], w2[3], w3[3], w4[3], w5[3], op);
	assign carry = ((~op[0] & w6) | (op[0] & w7));
endmodule
module MyALU(
	output [3:0] s,
	output carry,
	input [2:0] op,
	input [3:0] a, b);

	
	wire [3:0] w1, w2, w3, w4, w5;
	wire w6, w7;
	MyAdder add(w1, w6, a, b, 1'b0);
	MyAdder sub(w2, w7, a, b, 1'b1);
	MyAnd mand(w3, a, b);
	MyOr mor(w4, a, b);
	MyNot mnot(w5, a);
	MyMux mux1(s[0], w1[0], w2[0], w3[0], w4[0], w5[0], op);
	MyMux mux2(s[1], w1[1], w2[1], w3[1], w4[1], w5[1], op);
	MyMux mux3(s[2], w1[2], w2[2], w3[2], w4[2], w5[2], op);
	MyMux mux4(s[3], w1[3], w2[3], w3[3], w4[3], w5[3], op);
	assign carry = ((~op[0] & w6) | (op[0] & w7));
endmodule