data/full_repos/permissive/126689099/top_view.v
'utf-8' codec can't decode byte 0xb9 in position 96: invalid start byte
1: b"%Error: data/full_repos/permissive/126689099/top_view.v:81: Cannot find file containing module: 'ClkSpliterN'\nClkSpliterN clk_div_50k(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/126689099,data/full_repos/permissive/126689099/ClkSpliterN\n             data/full_repos/permissive/126689099,data/full_repos/permissive/126689099/ClkSpliterN.v\n             data/full_repos/permissive/126689099,data/full_repos/permissive/126689099/ClkSpliterN.sv\n             ClkSpliterN\n             ClkSpliterN.v\n             ClkSpliterN.sv\n             obj_dir/ClkSpliterN\n             obj_dir/ClkSpliterN.v\n             obj_dir/ClkSpliterN.sv\n%Error: data/full_repos/permissive/126689099/top_view.v:90: Cannot find file containing module: 'ip_sin_cos'\nip_sin_cos sin_cos_1M(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/126689099/top_view.v:100: Cannot find file containing module: 'ip_sin_cos'\nip_sin_cos sin_cos_500K(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/126689099/top_view.v:134: Cannot find file containing module: 'delay_clk_div_50k'\ndelay_clk_div_50k delay_50k(\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/126689099/top_view.v:141: Cannot find file containing module: 'delay_clk_div_50k'\ndelay_clk_div_50k delay_50k_two(\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/126689099/top_view.v:180: Cannot find file containing module: 'chirp'\nchirp chirp_instance(\n^~~~~\n%Error: data/full_repos/permissive/126689099/top_view.v:186: Cannot find file containing module: 'da2'\nda2 da_instance(\n^~~\n%Error: data/full_repos/permissive/126689099/top_view.v:196: Cannot find file containing module: 'ad'\nad ad_instance(\n^~\n%Error: Exiting due to 8 error(s)\n"
module top_view
(
	input clk,
	input rst_n,

	output led0,
	output [13 : 0] da1data,
   output da1_clk,
   output da1_wrt,
   output [13 : 0] da2data,
   output da2_clk,
   output da2_wrt,

   input [11:0] ad1_in,
   output ad1_clk,
   input [11:0] ad2_in,
   output ad2_clk




);

parameter IP_SIN_1M_DATA = 29'd1342000;
parameter IP_SIN_1K_DATA = 29'd2684;
parameter IP_SIN_10K_DATA = 29'd13420;
parameter IP_SIN_500K_DATA = 29'd671000;

wire clk25M;
wire clk50k;
wire delay_clk50k;
wire delay_clk50k_after;
reg clk_dpsk;
reg clk_dpsk_last;

wire[13:0] reg_dadata1;
wire[13:0] reg_dadata2;
wire[11:0] ad_ch1;
wire[11:0] ad_ch2;
wire [7:0] ch1_sig;
wire [7:0] ch2_sig;
wire [19:0] ch1_dec;
wire [19:0] ch2_dec;

wire[13:0] cosine_1M;
wire[13:0] sine_1M;
wire[13:0] cosine_500K;




reg[13:0] da_2ask;
reg[13:0] da_2fsk;
reg[13:0] da_bpsk;
reg[13:0] da_2dpsk;







assign ad1_clk=clk50k;
assign ad2_clk=clk50k;


assign da1_clk=clk;
assign da1_wrt=clk;
assign da2_clk=clk;
assign da2_wrt=clk;

assign da1data = reg_dadata1;
assign da2data = reg_dadata2;

assign led0 = clk_dpsk;


ClkSpliterN clk_div_50k(
    .SYSTEM_CLK(clk),
    .RST_N(rst_n),
	 .SPLITER_N(1000),
    .CLK_IN(clk),
    .CLK_OUT(clk50k)
);


ip_sin_cos sin_cos_1M(
	.clk(clk),
	.we(1'b1),
	.data(IP_SIN_1M_DATA),
	.cosine(cosine_1M),
	.sine(sine_1M),
	.phase_out()
);


ip_sin_cos sin_cos_500K(
	.clk(clk),
	.we(1'b1),
	.data(IP_SIN_500K_DATA),
	.cosine(cosine_500K),
	.sine(),
	.phase_out()
);


always@(*)
begin
	da_2ask <= cosine_1M * clk50k;
end


always@(*)
begin
	if (clk50k == 1'b0)
		da_2fsk <= cosine_1M;
	else if(clk50k == 1'b1)
		da_2fsk <= cosine_500K;
end


always@(*)
begin
	if (clk50k == 1'b0)
		da_bpsk <= cosine_1M;
	else if(clk50k == 1'b1)
		da_bpsk <= -(cosine_1M);
end


delay_clk_div_50k delay_50k(
    .clk50m(clk),
	 .rst_n(rst_n),
	 .clk50k(delay_clk50k),
	 .delay(199)
	 );

delay_clk_div_50k delay_50k_two(
    .clk50m(clk),
	 .rst_n(rst_n),
	 .clk50k(delay_clk50k_after),
	 .delay(299)
	 );

always@(posedge delay_clk50k_after or negedge rst_n)
begin
	if(!rst_n)
	begin
		clk_dpsk_last <= 0;	
	end
	else
		clk_dpsk_last <= clk_dpsk;
end

always@(posedge delay_clk50k or negedge rst_n)
begin
	if(!rst_n)
		clk_dpsk <= 0;
	else
		clk_dpsk <= clk_dpsk_last ^ clk50k;
end




wire[13:0] chirp_out_tmp;

chirp chirp_instance(
	.clk(clk),
	.rst_n(rst_n),
	.chirp_out(chirp_out_tmp)
	);

da2 da_instance(
	.clk(clk),
	.rst_n(rst_n),
	.real_da1(cosine_500K), 
	.real_da2(chirp_out_tmp), 
	.dadata1(reg_dadata1),
	.dadata2(reg_dadata2)
);


ad ad_instance(
	.ad_clk(clk),                           
	.ad1_in(ad1_in),
	.ad2_in(ad2_in),
   .ad_ch1(ad_ch1),
   .ad_ch2(ad_ch2)
);

endmodule
module top_view
(
	input clk,
	input rst_n,

	output led0,
	output [13 : 0] da1data,
   output da1_clk,
   output da1_wrt,
   output [13 : 0] da2data,
   output da2_clk,
   output da2_wrt,

   input [11:0] ad1_in,
   output ad1_clk,
   input [11:0] ad2_in,
   output ad2_clk




);


parameter IP_SIN_1M_DATA = 29'd1342000;
parameter IP_SIN_1K_DATA = 29'd2684;
parameter IP_SIN_10K_DATA = 29'd13420;
parameter IP_SIN_500K_DATA = 29'd671000;

wire clk25M;
wire clk50k;
wire delay_clk50k;
wire delay_clk50k_after;
reg clk_dpsk;
reg clk_dpsk_last;

wire[13:0] reg_dadata1;
wire[13:0] reg_dadata2;
wire[11:0] ad_ch1;
wire[11:0] ad_ch2;
wire [7:0] ch1_sig;
wire [7:0] ch2_sig;
wire [19:0] ch1_dec;
wire [19:0] ch2_dec;

wire[13:0] cosine_1M;
wire[13:0] sine_1M;
wire[13:0] cosine_500K;




reg[13:0] da_2ask;
reg[13:0] da_2fsk;
reg[13:0] da_bpsk;
reg[13:0] da_2dpsk;







assign ad1_clk=clk50k;
assign ad2_clk=clk50k;


assign da1_clk=clk;
assign da1_wrt=clk;
assign da2_clk=clk;
assign da2_wrt=clk;

assign da1data = reg_dadata1;
assign da2data = reg_dadata2;

assign led0 = clk_dpsk;


ClkSpliterN clk_div_50k(
    .SYSTEM_CLK(clk),
    .RST_N(rst_n),
	 .SPLITER_N(1000),
    .CLK_IN(clk),
    .CLK_OUT(clk50k)
);


ip_sin_cos sin_cos_1M(
	.clk(clk),
	.we(1'b1),
	.data(IP_SIN_1M_DATA),
	.cosine(cosine_1M),
	.sine(sine_1M),
	.phase_out()
);


ip_sin_cos sin_cos_500K(
	.clk(clk),
	.we(1'b1),
	.data(IP_SIN_500K_DATA),
	.cosine(cosine_500K),
	.sine(),
	.phase_out()
);


always@(*)
begin
	da_2ask <= cosine_1M * clk50k;
end


always@(*)
begin
	if (clk50k == 1'b0)
		da_2fsk <= cosine_1M;
	else if(clk50k == 1'b1)
		da_2fsk <= cosine_500K;
end


always@(*)
begin
	if (clk50k == 1'b0)
		da_bpsk <= cosine_1M;
	else if(clk50k == 1'b1)
		da_bpsk <= -(cosine_1M);
end


delay_clk_div_50k delay_50k(
    .clk50m(clk),
	 .rst_n(rst_n),
	 .clk50k(delay_clk50k),
	 .delay(199)
	 );

delay_clk_div_50k delay_50k_two(
    .clk50m(clk),
	 .rst_n(rst_n),
	 .clk50k(delay_clk50k_after),
	 .delay(299)
	 );

always@(posedge delay_clk50k_after or negedge rst_n)
begin
	if(!rst_n)
	begin
		clk_dpsk_last <= 0;	
	end
	else
		clk_dpsk_last <= clk_dpsk;
end

always@(posedge delay_clk50k or negedge rst_n)
begin
	if(!rst_n)
		clk_dpsk <= 0;
	else
		clk_dpsk <= clk_dpsk_last ^ clk50k;
end




wire[13:0] chirp_out_tmp;

chirp chirp_instance(
	.clk(clk),
	.rst_n(rst_n),
	.chirp_out(chirp_out_tmp)
	);

da2 da_instance(
	.clk(clk),
	.rst_n(rst_n),
	.real_da1(cosine_500K), 
	.real_da2(chirp_out_tmp), 
	.dadata1(reg_dadata1),
	.dadata2(reg_dadata2)
);


ad ad_instance(
	.ad_clk(clk),                           
	.ad1_in(ad1_in),
	.ad2_in(ad2_in),
   .ad_ch1(ad_ch1),
   .ad_ch2(ad_ch2)
);

endmodule