data/full_repos/permissive/129527056/cores/sectionz/ver/dma/test.v
 line:35: before: "flit"
1: b'%Warning-STMTDLY: data/full_repos/permissive/129527056/cores/sectionz/ver/dma/test.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #100 rst=0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129527056/cores/sectionz/ver/dma/test.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #400 OKOUT = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129527056/cores/sectionz/ver/dma/test.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #500 OKOUT = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129527056/cores/sectionz/ver/dma/test.v:29: Unsupported: Ignoring delay on this delayed statement.\n    forever #10 clk = ~clk;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/129527056/cores/sectionz/ver/dma/test.v:33: Unsupported: Ignoring delay on this delayed statement.\n    if(!rst) #100 $finish;\n             ^\n%Error: data/full_repos/permissive/129527056/cores/sectionz/ver/dma/test.v:54: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test.lxt");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/sectionz/ver/dma/test.v:55: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,test);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/sectionz/ver/dma/test.v:56: Unsupported or unknown PLI call: $dumpon\n    $dumpon;\n    ^~~~~~~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

parameter AW = 9, OBJMAX=512;

wire [AW-1:0]  AB;

reg  rst, clk, OKOUT, cen;
wire bus_req;
reg  bus_ack;

always @(posedge clk) begin
    bus_ack <= bus_req;
    cen     <= ~cen;
end

initial begin
    rst = 1;
    OKOUT = 0;
    #100 rst=0;
    #400 OKOUT = 1;
    #500 OKOUT = 0;
end

initial begin
    clk = 0;
    cen = 0;
    forever #10 clk = ~clk;
end

always @(negedge blen ) begin
    if(!rst) #100 $finish;
end

jtgng_objdma #(.AW(AW),.OBJMAX(OBJMAX)) UUT  (
    .rst    ( rst       ),
    .clk    ( clk       ),
    .cen    ( cen       ),


    .AB     ( AB        ),
    .DB     ( AB[7:0]   ),
    .OKOUT  ( OKOUT     ),
    .bus_req( bus_req   ),
    .bus_ack( bus_ack   ),
    .blen   ( blen      ),

    .pre_scan( AB       ),
    .dma_dout(          )
);

initial begin
    $dumpfile("test.lxt");
    $dumpvars(0,test);
    $dumpon;
end

endmodule
module test;


parameter AW = 9, OBJMAX=512;

wire [AW-1:0]  AB;

reg  rst, clk, OKOUT, cen;
wire bus_req;
reg  bus_ack;

always @(posedge clk) begin
    bus_ack <= bus_req;
    cen     <= ~cen;
end

initial begin
    rst = 1;
    OKOUT = 0;
    #100 rst=0;
    #400 OKOUT = 1;
    #500 OKOUT = 0;
end

initial begin
    clk = 0;
    cen = 0;
    forever #10 clk = ~clk;
end

always @(negedge blen ) begin
    if(!rst) #100 $finish;
end

jtgng_objdma #(.AW(AW),.OBJMAX(OBJMAX)) UUT  (
    .rst    ( rst       ),
    .clk    ( clk       ),
    .cen    ( cen       ),


    .AB     ( AB        ),
    .DB     ( AB[7:0]   ),
    .OKOUT  ( OKOUT     ),
    .bus_req( bus_req   ),
    .bus_ack( bus_ack   ),
    .blen   ( blen      ),

    .pre_scan( AB       ),
    .dma_dout(          )
);

initial begin
    $dumpfile("test.lxt");
    $dumpvars(0,test);
    $dumpon;
end

endmodule