data/full_repos/permissive/128659832/verilog/RAND.v
 line:26 column:19: Illegal character "'"
data/verilator_xmls/5a7cd2db-978e-45b5-be07-0bcb69fe935c.xml
module CA_cell(i, rule, o);
    input wire[2:0] i;
    input wire[7:0] rule;
    output wire o;

    assign o = rule[i];
endmodule
module CA_cell(i, rule, o);

    input wire[2:0] i;
    input wire[7:0] rule;
    output wire o;

    assign o = rule[i];
endmodule