data/full_repos/permissive/147656480/src/butterfly_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/147656480/src/butterfly_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/147656480/src/butterfly_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n   #5 clock = !clock;\n   ^\n%Error: data/full_repos/permissive/147656480/src/butterfly_tb.v:43: Cannot find file containing module: \'butterfly\'\n butterfly uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147656480/src,data/full_repos/permissive/147656480/butterfly\n             data/full_repos/permissive/147656480/src,data/full_repos/permissive/147656480/butterfly.v\n             data/full_repos/permissive/147656480/src,data/full_repos/permissive/147656480/butterfly.sv\n             butterfly\n             butterfly.v\n             butterfly.sv\n             obj_dir/butterfly\n             obj_dir/butterfly.v\n             obj_dir/butterfly.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module butterfly_tb;


	reg clock;
	reg [15:0] x1;
	reg [15:0] y1;
	reg [15:0] x2;
	reg [15:0] y2;
	reg [31:0] zangle;


	wire [15:0] xout1;
	wire [15:0] yout1;
	wire [15:0] xout2;
	wire [15:0] yout2;
	wire done;


	butterfly uut (
		.clock(clock), 
		.x1(x1), 
		.y1(y1), 
		.x2(x2), 
		.y2(y2), 
		.zangle(zangle), 
		.xout1(xout1), 
		.yout1(yout1), 
		.xout2(xout2), 
		.yout2(yout2),
		.done(done)
	);

	initial begin

		clock = 0;
		x1 = 0;
		y1 = 0;
		x2 = 0;
		y2 = 0;
		zangle = 0;


		#100;
        


		x1 =3200;
		y1 = 0;
		x2 = 3200;
		y2 = 0;

		zangle = 'b11100000000000000000000000000000;

		
		 clock = 'b0;
		 forever
		 begin
			#5 clock = !clock;
		 end
		
	end
      
endmodule
module butterfly_tb;



	reg clock;
	reg [15:0] x1;
	reg [15:0] y1;
	reg [15:0] x2;
	reg [15:0] y2;
	reg [31:0] zangle;


	wire [15:0] xout1;
	wire [15:0] yout1;
	wire [15:0] xout2;
	wire [15:0] yout2;
	wire done;


	butterfly uut (
		.clock(clock), 
		.x1(x1), 
		.y1(y1), 
		.x2(x2), 
		.y2(y2), 
		.zangle(zangle), 
		.xout1(xout1), 
		.yout1(yout1), 
		.xout2(xout2), 
		.yout2(yout2),
		.done(done)
	);

	initial begin

		clock = 0;
		x1 = 0;
		y1 = 0;
		x2 = 0;
		y2 = 0;
		zangle = 0;


		#100;
        


		x1 =3200;
		y1 = 0;
		x2 = 3200;
		y2 = 0;

		zangle = 'b11100000000000000000000000000000;

		
		 clock = 'b0;
		 forever
		 begin
			#5 clock = !clock;
		 end
		
	end
      
endmodule