data/full_repos/permissive/147265957/testbench/seller_simu.v
 line:55: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #4 start = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #4 start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #4 sel25 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #4 sel25 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #20 start = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #4 start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb10 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb10 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #4 sel5 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #4 sel5 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #20 start = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #4 start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb10 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #4 rmb10 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #4 cancel = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #4 cancel = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #20 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/seller_simu.v:60: Unsupported: Ignoring delay on this delayed statement.\n            #2 cp = ~cp;\n            ^\n%Error: data/full_repos/permissive/147265957/testbench/seller_simu.v:63: Cannot find file containing module: \'sellersm\'\n    sellersm s(cp, led, sdpsel, sdpdisp, rst, rmb1, rmb10, sel5, sel25, start, ~cancel);\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147265957/testbench,data/full_repos/permissive/147265957/sellersm\n             data/full_repos/permissive/147265957/testbench,data/full_repos/permissive/147265957/sellersm.v\n             data/full_repos/permissive/147265957/testbench,data/full_repos/permissive/147265957/sellersm.sv\n             sellersm\n             sellersm.v\n             sellersm.sv\n             obj_dir/sellersm\n             obj_dir/sellersm.v\n             obj_dir/sellersm.sv\n%Error: Exiting due to 1 error(s), 26 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sellersimu(
);
    reg [31:0] counter;
    reg cp;
    reg rst;
    reg rmb1;
    reg rmb10;
    reg start;
    reg sel5;
    reg sel25;
    reg cancel;
    wire [3:0] led;
    wire [7:0] sdpsel;
    wire [7:0] sdpdisp;

    initial begin
        counter = 0;
        cp = 0;
        rst = 0;
        rmb1 = 0;
        rmb10 = 0;
        start = 0;
        sel5 = 0;
        sel25 = 0;
        cancel = 0;

        #4 start = 1;
        #4 start = 0;
        #4 rmb1 = 1;
        #4 rmb1 = 0;
        #4 rmb1 = 1;
        #4 rmb1 = 0;
        #4 rmb1 = 1;
        #4 rmb1 = 0;
        #4 sel25 = 1;
        #4 sel25 = 0;

        #20 start = 1;
        #4 start = 0;
        #4 rmb10 = 1;
        #4 rmb10 = 0;
        #4 sel5 = 1;
        #4 sel5 = 0;

        #20 start = 1;
        #4 start = 0;
        #4 rmb1 = 1;
        #4 rmb1 = 0;
        #4 rmb10 = 1;
        #4 rmb10 = 0;
        #4 cancel = 1;
        #4 cancel = 0;
        #20 $finish;
    end

    initial begin
        for(counter = 0 ; counter < 999; counter = counter + 1) begin
            #2 cp = ~cp;
        end
    end
    sellersm s(cp, led, sdpsel, sdpdisp, rst, rmb1, rmb10, sel5, sel25, start, ~cancel);

endmodule
module sellersimu(
);

    reg [31:0] counter;
    reg cp;
    reg rst;
    reg rmb1;
    reg rmb10;
    reg start;
    reg sel5;
    reg sel25;
    reg cancel;
    wire [3:0] led;
    wire [7:0] sdpsel;
    wire [7:0] sdpdisp;

    initial begin
        counter = 0;
        cp = 0;
        rst = 0;
        rmb1 = 0;
        rmb10 = 0;
        start = 0;
        sel5 = 0;
        sel25 = 0;
        cancel = 0;

        #4 start = 1;
        #4 start = 0;
        #4 rmb1 = 1;
        #4 rmb1 = 0;
        #4 rmb1 = 1;
        #4 rmb1 = 0;
        #4 rmb1 = 1;
        #4 rmb1 = 0;
        #4 sel25 = 1;
        #4 sel25 = 0;

        #20 start = 1;
        #4 start = 0;
        #4 rmb10 = 1;
        #4 rmb10 = 0;
        #4 sel5 = 1;
        #4 sel5 = 0;

        #20 start = 1;
        #4 start = 0;
        #4 rmb1 = 1;
        #4 rmb1 = 0;
        #4 rmb10 = 1;
        #4 rmb10 = 0;
        #4 cancel = 1;
        #4 cancel = 0;
        #20 $finish;
    end

    initial begin
        for(counter = 0 ; counter < 999; counter = counter + 1) begin
            #2 cp = ~cp;
        end
    end
    sellersm s(cp, led, sdpsel, sdpdisp, rst, rmb1, rmb10, sel5, sel25, start, ~cancel);

endmodule