data/full_repos/permissive/179844171/rtl/mirfak_decoder.v
 line:17: before: "parameter"
1: b'%Error: data/full_repos/permissive/179844171/rtl/mirfak_decoder.v:8: Cannot find include file: mirfak_defines.v\n`include "mirfak_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179844171/rtl,data/full_repos/permissive/179844171/mirfak_defines.v\n             data/full_repos/permissive/179844171/rtl,data/full_repos/permissive/179844171/mirfak_defines.v.v\n             data/full_repos/permissive/179844171/rtl,data/full_repos/permissive/179844171/mirfak_defines.v.sv\n             mirfak_defines.v\n             mirfak_defines.v.v\n             mirfak_defines.v.sv\n             obj_dir/mirfak_defines.v\n             obj_dir/mirfak_defines.v.v\n             obj_dir/mirfak_defines.v.sv\n%Error: data/full_repos/permissive/179844171/rtl/mirfak_decoder.v:15: Define or directive not defined: \'`CTRL_SZ\'\n                          output reg [`CTRL_SZ] id_control_o\n                                      ^~~~~~~~\n%Error: data/full_repos/permissive/179844171/rtl/mirfak_decoder.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                          output reg [`CTRL_SZ] id_control_o\n                                              ^\n%Error: data/full_repos/permissive/179844171/rtl/mirfak_decoder.v:21: syntax error, unexpected assign\n    assign is_lui     = id_instruction_i[6:0] == 7\'b0110111;\n    ^~~~~~\n%Error: Exiting due to 4 error(s)\n'
module mirfak_decoder #(
                        parameter [0:0]  ENABLE_MULTDIV = 1
                        )(
                          input wire [31:0]     id_instruction_i,

                          output reg [`CTRL_SZ] id_control_o
                          );

    wire           is_lui, is_auipc, is_jal, is_jalr, is_branch, is_load;
    wire           is_store, is_ri, is_rr, is_fence, is_system, is_m;

    assign is_lui     = id_instruction_i[6:0] == 7'b0110111;
    assign is_auipc   = id_instruction_i[6:0] == 7'b0010111;
    assign is_jal     = id_instruction_i[6:0] == 7'b1101111;
    assign is_jalr    = id_instruction_i[6:0] == 7'b1100111;
    assign is_branch  = id_instruction_i[6:0] == 7'b1100011;
    assign is_load    = id_instruction_i[6:0] == 7'b0000011;
    assign is_store   = id_instruction_i[6:0] == 7'b0100011;
    assign is_ri      = id_instruction_i[6:0] == 7'b0010011 && ((id_instruction_i[13:12] == 2'b01) ? (!id_instruction_i[31] && id_instruction_i[29:25] == 5'b00000) : 1);
    assign is_rr      = id_instruction_i[6:0] == 7'b0110011 && !id_instruction_i[31] && id_instruction_i[29:25] == 5'b00000;
    assign is_fence   = id_instruction_i[6:0] == 7'b0001111;
    assign is_system  = id_instruction_i[6:0] == 7'b1110011;
    assign is_m       = id_instruction_i[6:0] == 7'b0110011 && id_instruction_i[31:25] == 7'b0000001 && ENABLE_MULTDIV;

    always @(*) begin


        case (1'b1)
            is_lui:    begin
                id_control_o = 32'b00001000000000000000000000110111;
            end
            is_auipc:  begin
                id_control_o = 32'b00001000000000000000000000110101;
            end
            is_jal:    begin
                id_control_o = 32'b00001100000000000000000111000101;
            end
            is_jalr:   begin
                id_control_o = 32'b00001100000000000000000110000100;
            end
            is_branch: begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o  = 32'b00000000000100000000000000100101;
                    3'b001: id_control_o  = 32'b00000000001000000000000000100101;
                    3'b100: id_control_o  = 32'b00000000010000000000000000100101;
                    3'b101: id_control_o  = 32'b00000000100000000000000000100101;
                    3'b110: id_control_o  = 32'b00000001000000000000000000100101;
                    3'b111: id_control_o  = 32'b00000010000000000000000000100101;
                    default: id_control_o = 32'b10000000000000000000000000000000;
                endcase
            end
            is_load:   begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o  = 32'b00001000000000010000000010000100;
                    3'b001: id_control_o  = 32'b00001000000000010000000010000100;
                    3'b010: id_control_o  = 32'b00001000000000010000000010000100;
                    3'b100: id_control_o  = 32'b00001000000000010000000010000100;
                    3'b101: id_control_o  = 32'b00001000000000010000000010000100;
                    default: id_control_o = 32'b10000000000000000000000000000000;
                endcase
            end
            is_store:  begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o  = 32'b00000000000000110000000000010100;
                    3'b001: id_control_o  = 32'b00000000000000110000000000010100;
                    3'b010: id_control_o  = 32'b00000000000000110000000000010100;
                    default: id_control_o = 32'b10000000000000000000000000000000;
                endcase
            end
            is_ri:     begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o = 32'b00001000000000000000000000000100;
                    3'b001: id_control_o = 32'b00001000000000001000000000000100;
                    3'b010: id_control_o = 32'b00001000000000001110000000000100;
                    3'b011: id_control_o = 32'b00001000000000001100000000000100;
                    3'b100: id_control_o = 32'b00001000000000000100100000000100;
                    3'b101: id_control_o = 32'b00001000000000001001000000000100;
                    3'b110: id_control_o = 32'b00001000000000000100010000000100;
                    3'b111: id_control_o = 32'b00001000000000000100000000000100;
                endcase
            end
            is_rr:     begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o = 32'b00001000000000000000001000000000;
                    3'b001: id_control_o = 32'b00001000000000001000000000000000;
                    3'b010: id_control_o = 32'b00001000000000001110000000000000;
                    3'b011: id_control_o = 32'b00001000000000001100000000000000;
                    3'b100: id_control_o = 32'b00001000000000000100100000000000;
                    3'b101: id_control_o = 32'b00001000000000001001000000000000;
                    3'b110: id_control_o = 32'b00001000000000000100010000000000;
                    3'b111: id_control_o = 32'b00001000000000000100000000000000;
                endcase
            end
            is_fence:  begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o  = 32'b00000000000000000000000000000000;
                    3'b001: id_control_o  = 32'b00100000000000000000000000000000;
                    default: id_control_o = 32'b10000000000000000000000000000000;
                endcase
            end
            is_system: begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o  = 32'b00010000000000000000000000000000;
                    3'b001: id_control_o  = 32'b00001000000001000000000100001100;
                    3'b010: id_control_o  = 32'b00001000000010000000000100001100;
                    3'b011: id_control_o  = 32'b00001000000011000000000100001100;
                    3'b101: id_control_o  = 32'b00001000000001000000000100001100;
                    3'b110: id_control_o  = 32'b00001000000010000000000100001100;
                    3'b111: id_control_o  = 32'b00001000000011000000000100001100;
                    default: id_control_o = 32'b10000000000000000000000000000000;
                endcase
            end
            is_m:      begin
                id_control_o = 32'b01001000000000000000000000000000;
            end
            default:   begin
                id_control_o = 32'b10000000000000000000000000000000;
            end
        endcase
    end

endmodule
module mirfak_decoder #(
                        parameter [0:0]  ENABLE_MULTDIV = 1
                        )(
                          input wire [31:0]     id_instruction_i,

                          output reg [`CTRL_SZ] id_control_o
                          );


    wire           is_lui, is_auipc, is_jal, is_jalr, is_branch, is_load;
    wire           is_store, is_ri, is_rr, is_fence, is_system, is_m;

    assign is_lui     = id_instruction_i[6:0] == 7'b0110111;
    assign is_auipc   = id_instruction_i[6:0] == 7'b0010111;
    assign is_jal     = id_instruction_i[6:0] == 7'b1101111;
    assign is_jalr    = id_instruction_i[6:0] == 7'b1100111;
    assign is_branch  = id_instruction_i[6:0] == 7'b1100011;
    assign is_load    = id_instruction_i[6:0] == 7'b0000011;
    assign is_store   = id_instruction_i[6:0] == 7'b0100011;
    assign is_ri      = id_instruction_i[6:0] == 7'b0010011 && ((id_instruction_i[13:12] == 2'b01) ? (!id_instruction_i[31] && id_instruction_i[29:25] == 5'b00000) : 1);
    assign is_rr      = id_instruction_i[6:0] == 7'b0110011 && !id_instruction_i[31] && id_instruction_i[29:25] == 5'b00000;
    assign is_fence   = id_instruction_i[6:0] == 7'b0001111;
    assign is_system  = id_instruction_i[6:0] == 7'b1110011;
    assign is_m       = id_instruction_i[6:0] == 7'b0110011 && id_instruction_i[31:25] == 7'b0000001 && ENABLE_MULTDIV;

    always @(*) begin


        case (1'b1)
            is_lui:    begin
                id_control_o = 32'b00001000000000000000000000110111;
            end
            is_auipc:  begin
                id_control_o = 32'b00001000000000000000000000110101;
            end
            is_jal:    begin
                id_control_o = 32'b00001100000000000000000111000101;
            end
            is_jalr:   begin
                id_control_o = 32'b00001100000000000000000110000100;
            end
            is_branch: begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o  = 32'b00000000000100000000000000100101;
                    3'b001: id_control_o  = 32'b00000000001000000000000000100101;
                    3'b100: id_control_o  = 32'b00000000010000000000000000100101;
                    3'b101: id_control_o  = 32'b00000000100000000000000000100101;
                    3'b110: id_control_o  = 32'b00000001000000000000000000100101;
                    3'b111: id_control_o  = 32'b00000010000000000000000000100101;
                    default: id_control_o = 32'b10000000000000000000000000000000;
                endcase
            end
            is_load:   begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o  = 32'b00001000000000010000000010000100;
                    3'b001: id_control_o  = 32'b00001000000000010000000010000100;
                    3'b010: id_control_o  = 32'b00001000000000010000000010000100;
                    3'b100: id_control_o  = 32'b00001000000000010000000010000100;
                    3'b101: id_control_o  = 32'b00001000000000010000000010000100;
                    default: id_control_o = 32'b10000000000000000000000000000000;
                endcase
            end
            is_store:  begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o  = 32'b00000000000000110000000000010100;
                    3'b001: id_control_o  = 32'b00000000000000110000000000010100;
                    3'b010: id_control_o  = 32'b00000000000000110000000000010100;
                    default: id_control_o = 32'b10000000000000000000000000000000;
                endcase
            end
            is_ri:     begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o = 32'b00001000000000000000000000000100;
                    3'b001: id_control_o = 32'b00001000000000001000000000000100;
                    3'b010: id_control_o = 32'b00001000000000001110000000000100;
                    3'b011: id_control_o = 32'b00001000000000001100000000000100;
                    3'b100: id_control_o = 32'b00001000000000000100100000000100;
                    3'b101: id_control_o = 32'b00001000000000001001000000000100;
                    3'b110: id_control_o = 32'b00001000000000000100010000000100;
                    3'b111: id_control_o = 32'b00001000000000000100000000000100;
                endcase
            end
            is_rr:     begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o = 32'b00001000000000000000001000000000;
                    3'b001: id_control_o = 32'b00001000000000001000000000000000;
                    3'b010: id_control_o = 32'b00001000000000001110000000000000;
                    3'b011: id_control_o = 32'b00001000000000001100000000000000;
                    3'b100: id_control_o = 32'b00001000000000000100100000000000;
                    3'b101: id_control_o = 32'b00001000000000001001000000000000;
                    3'b110: id_control_o = 32'b00001000000000000100010000000000;
                    3'b111: id_control_o = 32'b00001000000000000100000000000000;
                endcase
            end
            is_fence:  begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o  = 32'b00000000000000000000000000000000;
                    3'b001: id_control_o  = 32'b00100000000000000000000000000000;
                    default: id_control_o = 32'b10000000000000000000000000000000;
                endcase
            end
            is_system: begin
                case (id_instruction_i[14:12])
                    3'b000: id_control_o  = 32'b00010000000000000000000000000000;
                    3'b001: id_control_o  = 32'b00001000000001000000000100001100;
                    3'b010: id_control_o  = 32'b00001000000010000000000100001100;
                    3'b011: id_control_o  = 32'b00001000000011000000000100001100;
                    3'b101: id_control_o  = 32'b00001000000001000000000100001100;
                    3'b110: id_control_o  = 32'b00001000000010000000000100001100;
                    3'b111: id_control_o  = 32'b00001000000011000000000100001100;
                    default: id_control_o = 32'b10000000000000000000000000000000;
                endcase
            end
            is_m:      begin
                id_control_o = 32'b01001000000000000000000000000000;
            end
            default:   begin
                id_control_o = 32'b10000000000000000000000000000000;
            end
        endcase
    end

endmodule