data/full_repos/permissive/179980995/Lab2/main.v
data/verilator_xmls/ffe682a8-a3d9-41a3-a9f9-e88c87fa4fb3.xml
module mux_2to1(
input g,
input h,
input m,
output reg f
);
always@(*) begin
case(m)
1'b0: f = h;
1'b1: f = g;
endcase
end
endmodule
module mux_2to1(
input g,
input h,
input m,
output reg f
);

always@(*) begin
case(m)
1'b0: f = h;
1'b1: f = g;
endcase
end
endmodule