data/full_repos/permissive/118895561/Project 1/mdctrl.v
1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561.sv\n             1,data/full_repos/permissive/118895561\n             1,data/full_repos/permissive/118895561.v\n             1,data/full_repos/permissive/118895561.sv\n             obj_dir/1,data/full_repos/permissive/118895561\n             obj_dir/1,data/full_repos/permissive/118895561.v\n             obj_dir/1,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 1/mdctrl.v\n%Error: Exiting due to 3 error(s)\n'
module mdctrl(
    input   [31:0] Instr,
    output  Start,
    output  HiLo,
    output  WriteEnabled,
    output  [1:0] MDU_Op,
	 output  Add
    );
	 
	wire [31:0] Op;
	assign Op	= Instr[31:26];
	wire [5:0] Func;
	assign Func	= Instr[5:0];
	 
	reg [5:0] ctrl;
	assign {Start, HiLo, WriteEnabled, MDU_Op, Add}= ctrl;
	
	always @(*) begin
		if(Op == 0) 
			case (Func)
				6'b011010 : ctrl <= 6'b1_0_0_11_0;
				6'b011011 : ctrl <= 6'b1_0_0_10_0;
				6'b011000 : ctrl <= 6'b1_0_0_01_0;
				6'b011001 : ctrl <= 6'b1_0_0_00_0;
				6'b010000 : ctrl <= 6'b0_0_0_00_0;
				6'b010010 : ctrl <= 6'b0_1_0_00_0;
				6'b010001 : ctrl <= 6'b0_0_1_00_0;
				6'b010011 : ctrl <= 6'b0_1_1_00_0;
				default: ctrl <= 6'bx;
			endcase
		else if(Op == 6'b011100 & Func == 000000)
			ctrl <= 6'b0_0_0_00_1;
	   else
			ctrl <= 6'bx;
	end
endmodule
module mdctrl(
    input   [31:0] Instr,
    output  Start,
    output  HiLo,
    output  WriteEnabled,
    output  [1:0] MDU_Op,
	 output  Add
    );

	 
	wire [31:0] Op;
	assign Op	= Instr[31:26];
	wire [5:0] Func;
	assign Func	= Instr[5:0];
	 
	reg [5:0] ctrl;
	assign {Start, HiLo, WriteEnabled, MDU_Op, Add}= ctrl;
	
	always @(*) begin
		if(Op == 0) 
			case (Func)
				6'b011010 : ctrl <= 6'b1_0_0_11_0;
				6'b011011 : ctrl <= 6'b1_0_0_10_0;
				6'b011000 : ctrl <= 6'b1_0_0_01_0;
				6'b011001 : ctrl <= 6'b1_0_0_00_0;
				6'b010000 : ctrl <= 6'b0_0_0_00_0;
				6'b010010 : ctrl <= 6'b0_1_0_00_0;
				6'b010001 : ctrl <= 6'b0_0_1_00_0;
				6'b010011 : ctrl <= 6'b0_1_1_00_0;
				default: ctrl <= 6'bx;
			endcase
		else if(Op == 6'b011100 & Func == 000000)
			ctrl <= 6'b0_0_0_00_1;
	   else
			ctrl <= 6'bx;
	end
endmodule