data/full_repos/permissive/150947952/scratch/cyclone10/ip/QUAD_ENCODER/QE_TB.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/150947952/scratch/cyclone10/ip/QUAD_ENCODER/QE_TB.v:8: Unsupported: Ignoring delay on this delayed statement.\n#1 rCLK<= !rCLK;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/150947952/scratch/cyclone10/ip/QUAD_ENCODER/QE_TB.v:19: Cannot find file containing module: \'QUAD_ENCODER\'\nQUAD_ENCODER #(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150947952/scratch/cyclone10/ip/QUAD_ENCODER,data/full_repos/permissive/150947952/QUAD_ENCODER\n             data/full_repos/permissive/150947952/scratch/cyclone10/ip/QUAD_ENCODER,data/full_repos/permissive/150947952/QUAD_ENCODER.v\n             data/full_repos/permissive/150947952/scratch/cyclone10/ip/QUAD_ENCODER,data/full_repos/permissive/150947952/QUAD_ENCODER.sv\n             QUAD_ENCODER\n             QUAD_ENCODER.v\n             QUAD_ENCODER.sv\n             obj_dir/QUAD_ENCODER\n             obj_dir/QUAD_ENCODER.v\n             obj_dir/QUAD_ENCODER.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module QE_TB();

reg rCLK;

initial rCLK <=0;

always 
#1 rCLK<= !rCLK;

reg [9:0] rCOUNTER;
initial rCOUNTER<=0;

always @(posedge rCLK)
begin
  rCOUNTER<= rCOUNTER+1;

end

QUAD_ENCODER #(
    .pENCODERS(5)
  ) dut (
    .iCLK(rCLK),
    .iRESET(0),

    .iAVL_ADDRESS(rCOUNTER),
    .iAVL_READ(1),
    .oAVL_READ_DATA(),

    .iENCODER_A({5{rCOUNTER[4]^rCOUNTER[5],rCOUNTER[5]}}),
    .iENCODER_B({5{rCOUNTER[5],rCOUNTER[4]^rCOUNTER[5]}})
  );

endmodule
module QE_TB();


reg rCLK;

initial rCLK <=0;

always 
#1 rCLK<= !rCLK;

reg [9:0] rCOUNTER;
initial rCOUNTER<=0;

always @(posedge rCLK)
begin
  rCOUNTER<= rCOUNTER+1;

end

QUAD_ENCODER #(
    .pENCODERS(5)
  ) dut (
    .iCLK(rCLK),
    .iRESET(0),

    .iAVL_ADDRESS(rCOUNTER),
    .iAVL_READ(1),
    .oAVL_READ_DATA(),

    .iENCODER_A({5{rCOUNTER[4]^rCOUNTER[5],rCOUNTER[5]}}),
    .iENCODER_B({5{rCOUNTER[5],rCOUNTER[4]^rCOUNTER[5]}})
  );

endmodule