data/full_repos/permissive/217768747/comp_2.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:5: Signal definition not found, creating implicitly: \'lt1\'\nassign lt1= (~a[1])&&b[1];\n       ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:6: Signal definition not found, creating implicitly: \'lt2\'\n                                                                  : ... Suggested alternative: \'lt1\'\nassign lt2= (~a[0]) && (~a[1]) && b[0];\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:7: Signal definition not found, creating implicitly: \'lt3\'\n                                                                  : ... Suggested alternative: \'lt1\'\nassign lt3= (~a[0])&& b[1] && b[0];\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:9: Signal definition not found, creating implicitly: \'gt1\'\n                                                                  : ... Suggested alternative: \'lt1\'\nassign gt1=a[0] && (~b[1]) && (~b[0]);\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:10: Signal definition not found, creating implicitly: \'gt2\'\n                                                                   : ... Suggested alternative: \'gt1\'\nassign gt2= a[1] && (~b[1]);\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:11: Signal definition not found, creating implicitly: \'gt3\'\n                                                                   : ... Suggested alternative: \'gt1\'\nassign gt3= a[0] && a[1] && (~b[0]);\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:13: Signal definition not found, creating implicitly: \'e1\'\n                                                                   : ... Suggested alternative: \'eq\'\nassign e1=a[0]&&b[0];\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:14: Signal definition not found, creating implicitly: \'e2\'\n                                                                   : ... Suggested alternative: \'eq\'\nassign e2=(~a[0])&&(~b[0]);\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:15: Signal definition not found, creating implicitly: \'eq1\'\n                                                                   : ... Suggested alternative: \'eq\'\nassign eq1=e1 | e2;\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:16: Signal definition not found, creating implicitly: \'e3\'\n                                                                   : ... Suggested alternative: \'eq\'\nassign e3= a[1] && b[1];\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:17: Signal definition not found, creating implicitly: \'e4\'\n                                                                   : ... Suggested alternative: \'eq\'\nassign e4= (~a[1]) && (~b[1]);\n       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_2.v:18: Signal definition not found, creating implicitly: \'eq2\'\n                                                                   : ... Suggested alternative: \'eq\'\nassign eq2= e3 | e4;\n       ^~~\n%Error: Exiting due to 12 warning(s)\n'
module comp_2(a,b,l,g,eq);
input [1:0] a;
input [1:0] b;
output l,g,eq;
assign lt1= (~a[1])&&b[1];
assign lt2= (~a[0]) && (~a[1]) && b[0];
assign lt3= (~a[0])&& b[1] && b[0];
assign l= lt1 | lt2 | lt3;
assign gt1=a[0] && (~b[1]) && (~b[0]);
assign gt2= a[1] && (~b[1]);
assign gt3= a[0] && a[1] && (~b[0]);
assign g= gt1 | gt2 | gt3;
assign e1=a[0]&&b[0];
assign e2=(~a[0])&&(~b[0]);
assign eq1=e1 | e2;
assign e3= a[1] && b[1];
assign e4= (~a[1]) && (~b[1]);
assign eq2= e3 | e4;
assign eq= eq1 && eq2;
endmodule
module comp_2(a,b,l,g,eq);

input [1:0] a;
input [1:0] b;
output l,g,eq;
assign lt1= (~a[1])&&b[1];
assign lt2= (~a[0]) && (~a[1]) && b[0];
assign lt3= (~a[0])&& b[1] && b[0];
assign l= lt1 | lt2 | lt3;
assign gt1=a[0] && (~b[1]) && (~b[0]);
assign gt2= a[1] && (~b[1]);
assign gt3= a[0] && a[1] && (~b[0]);
assign g= gt1 | gt2 | gt3;
assign e1=a[0]&&b[0];
assign e2=(~a[0])&&(~b[0]);
assign eq1=e1 | e2;
assign e3= a[1] && b[1];
assign e4= (~a[1]) && (~b[1]);
assign eq2= e3 | e4;
assign eq= eq1 && eq2;
endmodule