data/full_repos/permissive/20688874/andy/tb/xor2tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:202: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:207: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: data/full_repos/permissive/20688874/andy/tb/xor2tb.v:77: Cannot find file containing module: \'xor2_2bit\'\n xor2_2bit xor22 (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/andy/tb,data/full_repos/permissive/20688874/xor2_2bit\n             data/full_repos/permissive/20688874/andy/tb,data/full_repos/permissive/20688874/xor2_2bit.v\n             data/full_repos/permissive/20688874/andy/tb,data/full_repos/permissive/20688874/xor2_2bit.sv\n             xor2_2bit\n             xor2_2bit.v\n             xor2_2bit.sv\n             obj_dir/xor2_2bit\n             obj_dir/xor2_2bit.v\n             obj_dir/xor2_2bit.sv\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_xor2_2bit();

	

	wire [1:0] y;
	
	

	reg [1:0] a;
	reg [1:0] b;
	
	
	

	xor2_2bit xor22 (


		a,b,y);
	
	
	
	
		
	
	

	

	initial
	begin

		$display(" << Starting the simulation >>");

		a = 2'd0;
		b = 2'd0;
		
		

		#10
		a = 2'd0;
		b = 2'd1;
		
		

		#10
		a = 2'd1;
		b = 2'd0;
		
		

		#10
		a = 2'd1;
		b = 2'd1;
		

		

		#10
		a = 2'd2;
		b = 2'd0;
		
		

		#10
		a = 2'd0;
		b = 2'd2;
		
		

		#10
		a = 2'd1;
		b = 2'd2;
		
		

		#10
		a = 2'd2;
		b = 2'd1;
		
		

		#10
		a = 2'd2;
		b = 2'd2;
		

		

		#10
		a = 2'd3;
		b = 2'd0;
		
		

		#10
		a = 2'd0;
		b = 2'd3;
		
		

		#10
		a = 2'd3;
		b = 2'd1;
		
		

		#10
		a = 2'd1;
		b = 2'd3;
		
		

		#10
		a = 2'd3;
		b = 2'd2;
		
		

		#10
		a = 2'd2;
		b = 2'd3;
		
		

		#10
		a = 2'd3;
		b = 2'd3;
		
		
		#20;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_xor2_2bit();


	

	wire [1:0] y;
	
	

	reg [1:0] a;
	reg [1:0] b;
	
	
	

	xor2_2bit xor22 (


		a,b,y);
	
	
	
	
		
	
	

	

	initial
	begin

		$display(" << Starting the simulation >>");

		a = 2'd0;
		b = 2'd0;
		
		

		#10
		a = 2'd0;
		b = 2'd1;
		
		

		#10
		a = 2'd1;
		b = 2'd0;
		
		

		#10
		a = 2'd1;
		b = 2'd1;
		

		

		#10
		a = 2'd2;
		b = 2'd0;
		
		

		#10
		a = 2'd0;
		b = 2'd2;
		
		

		#10
		a = 2'd1;
		b = 2'd2;
		
		

		#10
		a = 2'd2;
		b = 2'd1;
		
		

		#10
		a = 2'd2;
		b = 2'd2;
		

		

		#10
		a = 2'd3;
		b = 2'd0;
		
		

		#10
		a = 2'd0;
		b = 2'd3;
		
		

		#10
		a = 2'd3;
		b = 2'd1;
		
		

		#10
		a = 2'd1;
		b = 2'd3;
		
		

		#10
		a = 2'd3;
		b = 2'd2;
		
		

		#10
		a = 2'd2;
		b = 2'd3;
		
		

		#10
		a = 2'd3;
		b = 2'd3;
		
		
		#20;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule