data/full_repos/permissive/123043192/FPGA/USB/Sync245/Loopback-FPGA/fpga_usb_sync_245.srcs/sources_1/new/async_fifo.v
1: b"%Error: data/full_repos/permissive/123043192/FPGA/USB/Sync245/Loopback-FPGA/fpga_usb_sync_245.srcs/sources_1/new/async_fifo.v:75: Cannot find file containing module: 'graycounter'\n    graycounter #(.counterwidth(addresswidth)) pWrite_counter(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/Loopback-FPGA/fpga_usb_sync_245.srcs/sources_1/new,data/full_repos/permissive/123043192/graycounter\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/Loopback-FPGA/fpga_usb_sync_245.srcs/sources_1/new,data/full_repos/permissive/123043192/graycounter.v\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/Loopback-FPGA/fpga_usb_sync_245.srcs/sources_1/new,data/full_repos/permissive/123043192/graycounter.sv\n             graycounter\n             graycounter.v\n             graycounter.sv\n             obj_dir/graycounter\n             obj_dir/graycounter.v\n             obj_dir/graycounter.sv\n%Error: data/full_repos/permissive/123043192/FPGA/USB/Sync245/Loopback-FPGA/fpga_usb_sync_245.srcs/sources_1/new/async_fifo.v:83: Cannot find file containing module: 'graycounter'\n    graycounter #(.counterwidth(addresswidth)) pRead_counter(\n    ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module async_fifo#(parameter datawidth = 8, parameter DATADEPTH = 32, parameter addresswidth = 5)(
    input wire reset,
    

    input wire read_clk,
    input wire read_en,
    output reg [datawidth-1:0] outputData,
    

    input wire write_clk,
    input wire write_en,
    input wire [datawidth-1:0] inputData,
    

    output reg full,
    output reg empty
    );
    
    reg[datawidth - 1:0] memory[DATADEPTH-1:0];
    wire [addresswidth-1:0] pNextToWrite, pNextToRead;
    wire equalAddresses;
    wire NextWriteAddr_en,NextReadAddr_en;
    wire set_Status, rst_Status;
    reg status = 0;
    wire presetFull,presetEmpty;
    
    


    always @(negedge read_clk) begin
        if (read_en & !empty) begin
            outputData <= memory[pNextToRead];
        end
    end
    

    always @(negedge write_clk) begin
        if (write_en & !full) begin
            memory[pNextToWrite] <= inputData;
        end
    end 
    
    assign NextWriteAddr_en = write_en & ~full;
    assign NextReadAddr_en = read_en & ~empty;
    

    graycounter #(.counterwidth(addresswidth)) pWrite_counter(
        .graycount(pNextToWrite),
        .enable(NextWriteAddr_en),
        .clear(reset),
        .clk(write_clk)
    );
    

    graycounter #(.counterwidth(addresswidth)) pRead_counter(
        .graycount(pNextToRead),
        .enable(NextReadAddr_en),
        .clear(reset),
        .clk(read_clk)
    );
    
    assign equalAddresses = (pNextToRead == pNextToWrite);
    
    assign set_Status = (pNextToWrite[addresswidth- 2] ~^pNextToRead[addresswidth-1]) & (pNextToWrite[addresswidth-1] ^  pNextToRead[addresswidth-2]);
    
    assign rst_Status = (pNextToWrite[addresswidth-2] ^  pNextToRead[addresswidth-1]) & (pNextToWrite[addresswidth-1] ~^ pNextToRead[addresswidth-2]);

    always @ (set_Status, rst_Status, reset) begin
        if(rst_Status | reset) begin
            status = 0;
        end
        else if(set_Status) begin
            status = 1;
        end
    end
    

    assign presetFull = status & equalAddresses;
    
    always @(posedge write_clk, posedge presetFull) begin
        if(presetFull) begin
            full <= 1;
        end
        else begin
            full <= 0;
        end
    end
    

    assign presetEmpty = ~status & equalAddresses;
    
    always @(posedge read_clk,posedge presetEmpty) begin
        if (presetEmpty) begin
            empty <= 1;
        end
        else begin
            empty <= 0;
        end
    end
    
endmodule
module async_fifo#(parameter datawidth = 8, parameter DATADEPTH = 32, parameter addresswidth = 5)(
    input wire reset,
    

    input wire read_clk,
    input wire read_en,
    output reg [datawidth-1:0] outputData,
    

    input wire write_clk,
    input wire write_en,
    input wire [datawidth-1:0] inputData,
    

    output reg full,
    output reg empty
    );

    
    reg[datawidth - 1:0] memory[DATADEPTH-1:0];
    wire [addresswidth-1:0] pNextToWrite, pNextToRead;
    wire equalAddresses;
    wire NextWriteAddr_en,NextReadAddr_en;
    wire set_Status, rst_Status;
    reg status = 0;
    wire presetFull,presetEmpty;
    
    


    always @(negedge read_clk) begin
        if (read_en & !empty) begin
            outputData <= memory[pNextToRead];
        end
    end
    

    always @(negedge write_clk) begin
        if (write_en & !full) begin
            memory[pNextToWrite] <= inputData;
        end
    end 
    
    assign NextWriteAddr_en = write_en & ~full;
    assign NextReadAddr_en = read_en & ~empty;
    

    graycounter #(.counterwidth(addresswidth)) pWrite_counter(
        .graycount(pNextToWrite),
        .enable(NextWriteAddr_en),
        .clear(reset),
        .clk(write_clk)
    );
    

    graycounter #(.counterwidth(addresswidth)) pRead_counter(
        .graycount(pNextToRead),
        .enable(NextReadAddr_en),
        .clear(reset),
        .clk(read_clk)
    );
    
    assign equalAddresses = (pNextToRead == pNextToWrite);
    
    assign set_Status = (pNextToWrite[addresswidth- 2] ~^pNextToRead[addresswidth-1]) & (pNextToWrite[addresswidth-1] ^  pNextToRead[addresswidth-2]);
    
    assign rst_Status = (pNextToWrite[addresswidth-2] ^  pNextToRead[addresswidth-1]) & (pNextToWrite[addresswidth-1] ~^ pNextToRead[addresswidth-2]);

    always @ (set_Status, rst_Status, reset) begin
        if(rst_Status | reset) begin
            status = 0;
        end
        else if(set_Status) begin
            status = 1;
        end
    end
    

    assign presetFull = status & equalAddresses;
    
    always @(posedge write_clk, posedge presetFull) begin
        if(presetFull) begin
            full <= 1;
        end
        else begin
            full <= 0;
        end
    end
    

    assign presetEmpty = ~status & equalAddresses;
    
    always @(posedge read_clk,posedge presetEmpty) begin
        if (presetEmpty) begin
            empty <= 1;
        end
        else begin
            empty <= 0;
        end
    end
    
endmodule