data/full_repos/permissive/174323821/hdl/sdram/jtframe_sdram_bank_core.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-WIDTH: data/full_repos/permissive/174323821/hdl/sdram/jtframe_sdram_bank_core.v:173: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                            : ... In instance jtframe_sdram_bank_core\n    activate = ( (!all_st[READ_ST] && rd ) || (!all_st[STW-2:(HF?2:1)] && wr)) && !rfshing;\n                                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/174323821/hdl/sdram/jtframe_sdram_bank_core.v:187: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 6 bits.\n                                                                                            : ... In instance jtframe_sdram_bank_core\n    refresh  = !all_st[STW-1:1] && rfsh_en && !rd && !wr && !rfshing;\n               ^\n%Error: Exiting due to 2 warning(s)\n'
module jtframe_sdram_bank_core #(
    parameter AW=22,
              HF=1,

              SHIFTED=0
)(
    input               rst,
    input               clk,

    input      [AW-1:0] addr,
    input               rd,
    input               wr,
    input               rfsh_en,
    input      [   1:0] ba_rq,
    output reg [   1:0] ba_rdy,
    input      [  15:0] din,
    input      [   1:0] din_m,

    output reg          ack,
    output reg          rdy,
    output     [  31:0] dout,






    inout       [15:0]  sdram_dq,
    output reg  [12:0]  sdram_a,
    output              sdram_dqml,
    output              sdram_dqmh,
    output reg  [ 1:0]  sdram_ba,
    output              sdram_nwe,
    output              sdram_ncas,
    output              sdram_nras,
    output              sdram_ncs,
    output              sdram_cke
);

localparam ROW=13,
           COW= AW==22 ? 9 : 10,
           STW = (HF ? 7 : 6) - (SHIFTED ? 1:0),

           BQL = 4,
           READ_ST = HF ? 2 : 1,
           DQLO_ST = (HF ? 5 : 4)- (SHIFTED ? 1:0),
           DQHI_ST = (HF ? 6 : 5)- (SHIFTED ? 1:0),
           FIFO_SEL= HF ? 0 : 1;


localparam CMD_LOAD_MODE   = 4'b0___0____0____0,
           CMD_REFRESH     = 4'b0___0____0____1,
           CMD_PRECHARGE   = 4'b0___0____1____0,
           CMD_ACTIVE      = 4'b0___0____1____1,
           CMD_WRITE       = 4'b0___1____0____0,
           CMD_READ        = 4'b0___1____0____1,
           CMD_STOP        = 4'b0___1____1____0,
           CMD_NOP         = 4'b0___1____1____1,
           CMD_INHIBIT     = 4'b1___0____0____0;

localparam [13:0] INIT_WAIT = HF ? 14'd10_000 : 14'd5_000;

`ifdef MISTER
`define JTFRAME_SDRAM_ADQM
`endif

`ifdef JTFRAME_SDRAM_ADQM
localparam ADQM = 1;
`else
localparam ADQM = 0;
`endif


reg [13:0] wait_cnt;
reg [ 2:0] init_st;
reg [ 3:0] init_cmd;
reg        init;

reg   [STW-1:0] ba0_st, ba1_st, ba2_st, ba3_st, all_st;
reg             activate, read, get_low, get_high, post_act, wrtng;
reg             hold_bus;
reg       [3:0] cmd;
reg       [1:0] dqm;
reg       [1:0] wrmask;
reg      [15:0] dq_pad, dq_ff, dq_ff0;
reg             rfshing, refresh, end_rfsh;

reg [  COW-1:0] col_fifo[0:1];
reg [      1:0] ba_fifo[0:1];
reg [BQL*2-1:0] ba_queue;

wire      [1:0] req_a12;
wire            dqmbusy;


assign {sdram_ncs, sdram_nras, sdram_ncas, sdram_nwe } = cmd;
assign sdram_cke = 1;
assign sdram_dq = dq_pad;

assign req_a12 = AW==22 ? addr[AW-1:AW-2] : addr[AW-2:AW-3];
assign { sdram_dqmh, sdram_dqml } =  ADQM ? sdram_a[12:11] : dqm;

assign dout = { dq_ff, dq_ff0 };
assign dqmbusy = all_st[HF ? 3 : 2];

`ifdef SIMULATION
wire [9:0] col_fifo0 = col_fifo[0];
wire [9:0] col_fifo1 = col_fifo[1];
wire [1:0] ba_fifo0  = ba_fifo[0];
wire [1:0] ba_fifo1  = ba_fifo[1];

`endif
reg  [STW-1:0] next_ba0;
reg  [STW-1:0] next_ba1;
reg  [STW-1:0] next_ba2;
reg  [STW-1:0] next_ba3;

function [STW-1:0] next;
    input [STW-1:0] cur;
    input [1:0] ba;



    next =    ((activate && ba_rq==ba)
           || (read && ba_fifo[HF?0:1]==ba)
           || (!cur[0] && !cur[READ_ST]) )
           || rfshing ?
                        { cur[STW-2:0], cur[STW-1] } :
                        cur;
endfunction

always @(*) begin
    all_st   =  ba0_st | ba1_st | ba2_st | ba3_st;
    activate = ( (!all_st[READ_ST] && rd ) || (!all_st[STW-2:(HF?2:1)] && wr)) && !rfshing;
    case( ba_rq )
        2'd0: if( !ba0_st[0] ) activate = 0;
        2'd1: if( !ba1_st[0] ) activate = 0;
        2'd2: if( !ba2_st[0] ) activate = 0;
        2'd3: if( !ba3_st[0] ) activate = 0;
    endcase
    read     = all_st[READ_ST] && !all_st[READ_ST+1] && !rfshing;


    if( dqmbusy && req_a12 != 2'd00 && ADQM ) begin
        activate = 0;
        read     = 0;
    end
    refresh  = !all_st[STW-1:1] && rfsh_en && !rd && !wr && !rfshing;
    end_rfsh = rfshing && all_st[STW-1];
    get_low  = all_st[DQLO_ST] && !rfshing;
    get_high = all_st[DQHI_ST] && !rfshing;
    ack      = (HF ? post_act : activate) && !init;
    next_ba0 = next( ba0_st, 2'd0 );
    next_ba1 = next( ba1_st, 2'd1 );
    next_ba2 = next( ba2_st, 2'd2 );
    next_ba3 = next( ba3_st, 2'd3 );
end

always @(posedge clk, posedge rst) begin
    if( rst ) begin
        ba0_st   <= { {STW-1{1'b0}}, 1'd1 };
        ba1_st   <= { {STW-1{1'b0}}, 1'd1 };
        ba2_st   <= { {STW-1{1'b0}}, 1'd1 };
        ba3_st   <= { {STW-1{1'b0}}, 1'd1 };
        rfshing  <= 0;
        wrtng    <= 0;
        post_act <= 0;

        init     <= 1;
        wait_cnt <= INIT_WAIT;
        init_st  <= 3'd0;
        init_cmd <= CMD_NOP;

        cmd      <= CMD_NOP;
        dq_pad   <= 16'hzzzz;
        sdram_a  <= 13'd0;
        sdram_ba <= 2'd0;

        rdy      <= 0;
        ba_rdy   <= 0;
        ba_queue <= {BQL*2{1'b0}};
        dq_ff    <= 16'd0;
        dq_ff0   <= 16'd0;
    end else if( init ) begin
        if( |wait_cnt ) begin
            wait_cnt <= wait_cnt-14'd1;
            init_cmd <= CMD_NOP;
            cmd      <= init_cmd;
        end else begin
            sdram_a  <= 13'd0;
            if(!init_st[2]) init_st <= init_st+3'd1;
            case(init_st)
                3'd0: begin
                    init_cmd   <= CMD_PRECHARGE;
                    sdram_a[10]<= 1;
                    wait_cnt   <= 14'd2;
                end
                3'd1: begin
                    init_cmd <= CMD_REFRESH;
                    wait_cnt <= 14'd11;
                end
                3'd2: begin
                    init_cmd <= CMD_REFRESH;
                    wait_cnt <= 14'd11;
                end
                3'd3: begin
                    init_cmd <= CMD_LOAD_MODE;
                    sdram_a  <= 13'b00_1_00_010_0_001;
                    wait_cnt <= 14'd3;
                end
                3'd4: begin
                    init <= 0;
                end
                default: begin
                    cmd  <= init_cmd;
                    init <= 0;
                end
            endcase
        end
    end else begin
        if(!wrtng) dq_pad <= 16'hzzzz;
        ba0_st <= next_ba0;
        ba1_st <= next_ba1;
        ba2_st <= next_ba2;
        ba3_st <= next_ba3;
        ba_queue[ (BQL-1)*2-1: 0 ] <= ba_queue[ BQL*2-1: 2 ];

        cmd    <= CMD_NOP;

        if( refresh ) begin
            cmd         <= CMD_REFRESH;
            sdram_a[10] <= 1;
            rfshing     <= 1;
        end else if( end_rfsh ) begin
            rfshing  <= 0;
        end
        if( activate ) begin
            cmd           <= CMD_ACTIVE;
            sdram_ba      <= ba_rq;
            ba_fifo[1]    <= ba_rq;
            wrtng         <= wr;
            wrmask        <= din_m;
            post_act      <= 1;


            { sdram_a, col_fifo[1] } <= AW==22 ? addr : { addr[AW-2:9], addr[AW-1], addr[8:0] };
        end else begin
            post_act    <= 0;
        end
        if( post_act ) begin
            col_fifo[0] <= col_fifo[1];
            ba_fifo[0]  <= ba_fifo[1];
        end
        if( read ) begin
            sdram_a[10] <= 1;
            if( ADQM )

                sdram_a[12:11] <= wrtng ? wrmask : 2'b00;
            else begin
                dqm            <= wrtng ? wrmask : 2'b00;
                sdram_a[12:11] <= 2'd0;
            end
            if( wrtng ) begin
                dq_pad <= din;
                cmd    <= CMD_WRITE;
            end else begin
                cmd    <= CMD_READ;
            end
            sdram_a[COW-1:0] <= col_fifo[FIFO_SEL];
            sdram_ba <= ba_fifo[FIFO_SEL];
            ba_queue[BQL*2-1:(BQL-1)*2] <= ba_fifo[FIFO_SEL];
        end
        if( get_low ) begin
            dq_ff  <= sdram_dq;
        end
        if( get_high ) begin
            dq_ff0 <= dq_ff;
            dq_ff  <= sdram_dq;

            rdy    <= 1;
            ba_rdy <= SHIFTED ? ba_queue[3:2] : ba_queue[1:0];
        end
        else rdy <= 0;
    end
end

`ifdef SIMULATION
initial begin
    $display("INFO: SDRAM bank core parameters: HF=%0d SHIFTED=%0d\n",HF, SHIFTED);
end
`endif

endmodule
module jtframe_sdram_bank_core #(
    parameter AW=22,
              HF=1,

              SHIFTED=0
)(
    input               rst,
    input               clk,

    input      [AW-1:0] addr,
    input               rd,
    input               wr,
    input               rfsh_en,
    input      [   1:0] ba_rq,
    output reg [   1:0] ba_rdy,
    input      [  15:0] din,
    input      [   1:0] din_m,

    output reg          ack,
    output reg          rdy,
    output     [  31:0] dout,






    inout       [15:0]  sdram_dq,
    output reg  [12:0]  sdram_a,
    output              sdram_dqml,
    output              sdram_dqmh,
    output reg  [ 1:0]  sdram_ba,
    output              sdram_nwe,
    output              sdram_ncas,
    output              sdram_nras,
    output              sdram_ncs,
    output              sdram_cke
);


localparam ROW=13,
           COW= AW==22 ? 9 : 10,
           STW = (HF ? 7 : 6) - (SHIFTED ? 1:0),

           BQL = 4,
           READ_ST = HF ? 2 : 1,
           DQLO_ST = (HF ? 5 : 4)- (SHIFTED ? 1:0),
           DQHI_ST = (HF ? 6 : 5)- (SHIFTED ? 1:0),
           FIFO_SEL= HF ? 0 : 1;


localparam CMD_LOAD_MODE   = 4'b0___0____0____0,
           CMD_REFRESH     = 4'b0___0____0____1,
           CMD_PRECHARGE   = 4'b0___0____1____0,
           CMD_ACTIVE      = 4'b0___0____1____1,
           CMD_WRITE       = 4'b0___1____0____0,
           CMD_READ        = 4'b0___1____0____1,
           CMD_STOP        = 4'b0___1____1____0,
           CMD_NOP         = 4'b0___1____1____1,
           CMD_INHIBIT     = 4'b1___0____0____0;

localparam [13:0] INIT_WAIT = HF ? 14'd10_000 : 14'd5_000;

`ifdef MISTER
`define JTFRAME_SDRAM_ADQM
`endif

`ifdef JTFRAME_SDRAM_ADQM
localparam ADQM = 1;
`else
localparam ADQM = 0;
`endif


reg [13:0] wait_cnt;
reg [ 2:0] init_st;
reg [ 3:0] init_cmd;
reg        init;

reg   [STW-1:0] ba0_st, ba1_st, ba2_st, ba3_st, all_st;
reg             activate, read, get_low, get_high, post_act, wrtng;
reg             hold_bus;
reg       [3:0] cmd;
reg       [1:0] dqm;
reg       [1:0] wrmask;
reg      [15:0] dq_pad, dq_ff, dq_ff0;
reg             rfshing, refresh, end_rfsh;

reg [  COW-1:0] col_fifo[0:1];
reg [      1:0] ba_fifo[0:1];
reg [BQL*2-1:0] ba_queue;

wire      [1:0] req_a12;
wire            dqmbusy;


assign {sdram_ncs, sdram_nras, sdram_ncas, sdram_nwe } = cmd;
assign sdram_cke = 1;
assign sdram_dq = dq_pad;

assign req_a12 = AW==22 ? addr[AW-1:AW-2] : addr[AW-2:AW-3];
assign { sdram_dqmh, sdram_dqml } =  ADQM ? sdram_a[12:11] : dqm;

assign dout = { dq_ff, dq_ff0 };
assign dqmbusy = all_st[HF ? 3 : 2];

`ifdef SIMULATION
wire [9:0] col_fifo0 = col_fifo[0];
wire [9:0] col_fifo1 = col_fifo[1];
wire [1:0] ba_fifo0  = ba_fifo[0];
wire [1:0] ba_fifo1  = ba_fifo[1];

`endif
reg  [STW-1:0] next_ba0;
reg  [STW-1:0] next_ba1;
reg  [STW-1:0] next_ba2;
reg  [STW-1:0] next_ba3;

function [STW-1:0] next;
    input [STW-1:0] cur;
    input [1:0] ba;



    next =    ((activate && ba_rq==ba)
           || (read && ba_fifo[HF?0:1]==ba)
           || (!cur[0] && !cur[READ_ST]) )
           || rfshing ?
                        { cur[STW-2:0], cur[STW-1] } :
                        cur;
endfunction

always @(*) begin
    all_st   =  ba0_st | ba1_st | ba2_st | ba3_st;
    activate = ( (!all_st[READ_ST] && rd ) || (!all_st[STW-2:(HF?2:1)] && wr)) && !rfshing;
    case( ba_rq )
        2'd0: if( !ba0_st[0] ) activate = 0;
        2'd1: if( !ba1_st[0] ) activate = 0;
        2'd2: if( !ba2_st[0] ) activate = 0;
        2'd3: if( !ba3_st[0] ) activate = 0;
    endcase
    read     = all_st[READ_ST] && !all_st[READ_ST+1] && !rfshing;


    if( dqmbusy && req_a12 != 2'd00 && ADQM ) begin
        activate = 0;
        read     = 0;
    end
    refresh  = !all_st[STW-1:1] && rfsh_en && !rd && !wr && !rfshing;
    end_rfsh = rfshing && all_st[STW-1];
    get_low  = all_st[DQLO_ST] && !rfshing;
    get_high = all_st[DQHI_ST] && !rfshing;
    ack      = (HF ? post_act : activate) && !init;
    next_ba0 = next( ba0_st, 2'd0 );
    next_ba1 = next( ba1_st, 2'd1 );
    next_ba2 = next( ba2_st, 2'd2 );
    next_ba3 = next( ba3_st, 2'd3 );
end

always @(posedge clk, posedge rst) begin
    if( rst ) begin
        ba0_st   <= { {STW-1{1'b0}}, 1'd1 };
        ba1_st   <= { {STW-1{1'b0}}, 1'd1 };
        ba2_st   <= { {STW-1{1'b0}}, 1'd1 };
        ba3_st   <= { {STW-1{1'b0}}, 1'd1 };
        rfshing  <= 0;
        wrtng    <= 0;
        post_act <= 0;

        init     <= 1;
        wait_cnt <= INIT_WAIT;
        init_st  <= 3'd0;
        init_cmd <= CMD_NOP;

        cmd      <= CMD_NOP;
        dq_pad   <= 16'hzzzz;
        sdram_a  <= 13'd0;
        sdram_ba <= 2'd0;

        rdy      <= 0;
        ba_rdy   <= 0;
        ba_queue <= {BQL*2{1'b0}};
        dq_ff    <= 16'd0;
        dq_ff0   <= 16'd0;
    end else if( init ) begin
        if( |wait_cnt ) begin
            wait_cnt <= wait_cnt-14'd1;
            init_cmd <= CMD_NOP;
            cmd      <= init_cmd;
        end else begin
            sdram_a  <= 13'd0;
            if(!init_st[2]) init_st <= init_st+3'd1;
            case(init_st)
                3'd0: begin
                    init_cmd   <= CMD_PRECHARGE;
                    sdram_a[10]<= 1;
                    wait_cnt   <= 14'd2;
                end
                3'd1: begin
                    init_cmd <= CMD_REFRESH;
                    wait_cnt <= 14'd11;
                end
                3'd2: begin
                    init_cmd <= CMD_REFRESH;
                    wait_cnt <= 14'd11;
                end
                3'd3: begin
                    init_cmd <= CMD_LOAD_MODE;
                    sdram_a  <= 13'b00_1_00_010_0_001;
                    wait_cnt <= 14'd3;
                end
                3'd4: begin
                    init <= 0;
                end
                default: begin
                    cmd  <= init_cmd;
                    init <= 0;
                end
            endcase
        end
    end else begin
        if(!wrtng) dq_pad <= 16'hzzzz;
        ba0_st <= next_ba0;
        ba1_st <= next_ba1;
        ba2_st <= next_ba2;
        ba3_st <= next_ba3;
        ba_queue[ (BQL-1)*2-1: 0 ] <= ba_queue[ BQL*2-1: 2 ];

        cmd    <= CMD_NOP;

        if( refresh ) begin
            cmd         <= CMD_REFRESH;
            sdram_a[10] <= 1;
            rfshing     <= 1;
        end else if( end_rfsh ) begin
            rfshing  <= 0;
        end
        if( activate ) begin
            cmd           <= CMD_ACTIVE;
            sdram_ba      <= ba_rq;
            ba_fifo[1]    <= ba_rq;
            wrtng         <= wr;
            wrmask        <= din_m;
            post_act      <= 1;


            { sdram_a, col_fifo[1] } <= AW==22 ? addr : { addr[AW-2:9], addr[AW-1], addr[8:0] };
        end else begin
            post_act    <= 0;
        end
        if( post_act ) begin
            col_fifo[0] <= col_fifo[1];
            ba_fifo[0]  <= ba_fifo[1];
        end
        if( read ) begin
            sdram_a[10] <= 1;
            if( ADQM )

                sdram_a[12:11] <= wrtng ? wrmask : 2'b00;
            else begin
                dqm            <= wrtng ? wrmask : 2'b00;
                sdram_a[12:11] <= 2'd0;
            end
            if( wrtng ) begin
                dq_pad <= din;
                cmd    <= CMD_WRITE;
            end else begin
                cmd    <= CMD_READ;
            end
            sdram_a[COW-1:0] <= col_fifo[FIFO_SEL];
            sdram_ba <= ba_fifo[FIFO_SEL];
            ba_queue[BQL*2-1:(BQL-1)*2] <= ba_fifo[FIFO_SEL];
        end
        if( get_low ) begin
            dq_ff  <= sdram_dq;
        end
        if( get_high ) begin
            dq_ff0 <= dq_ff;
            dq_ff  <= sdram_dq;

            rdy    <= 1;
            ba_rdy <= SHIFTED ? ba_queue[3:2] : ba_queue[1:0];
        end
        else rdy <= 0;
    end
end

`ifdef SIMULATION
initial begin
    $display("INFO: SDRAM bank core parameters: HF=%0d SHIFTED=%0d\n",HF, SHIFTED);
end
`endif

endmodule