data/full_repos/permissive/166008742/src/arb_rr.v
data/verilator_xmls/6198db18-28cd-43d9-a34b-cbcf728758c9.xml
module arb_rr #(parameter PORTS_NUM = 4)
(
    input reset,
    input clk,

    input  [PORTS_NUM-1:0] req,
    output [PORTS_NUM-1:0] gnt
);

    reg [PORTS_NUM-1:0] rr_cnt;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            rr_cnt <= 1;
        end
        else begin
            if (gnt == 0) begin
                rr_cnt <= {rr_cnt[PORTS_NUM-2:0], rr_cnt[PORTS_NUM-1]};
            end
        end
    end

    assign gnt = req & rr_cnt;
endmodule
module arb_rr #(parameter PORTS_NUM = 4)
(
    input reset,
    input clk,

    input  [PORTS_NUM-1:0] req,
    output [PORTS_NUM-1:0] gnt
);


    reg [PORTS_NUM-1:0] rr_cnt;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            rr_cnt <= 1;
        end
        else begin
            if (gnt == 0) begin
                rr_cnt <= {rr_cnt[PORTS_NUM-2:0], rr_cnt[PORTS_NUM-1]};
            end
        end
    end

    assign gnt = req & rr_cnt;
endmodule