data/full_repos/permissive/184916587/ALU_RECV.v
data/verilator_xmls/11c131a4-5f02-45c9-b967-521eab3318de.xml
module srl_32(
	input[31:0] srl_rs1,
	input[31:0] srl_rs2,
	output[31:0] srl_rd
);
	assign srl_rd=srl_rs1>>srl_rs2[4:0];
endmodule
module srl_32(
	input[31:0] srl_rs1,
	input[31:0] srl_rs2,
	output[31:0] srl_rd
);

	assign srl_rd=srl_rs1>>srl_rs2[4:0];
endmodule