data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:78: Signal definition not found, creating implicitly: \'w1_0\'\n                                                                                                      : ... Suggested alternative: \'wo_0\'\nassign w1_0 = w[4];\n       ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:79: Signal definition not found, creating implicitly: \'w1_1\'\n                                                                                                      : ... Suggested alternative: \'wo_1\'\nassign w1_1 = w[5];\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:80: Signal definition not found, creating implicitly: \'w1_2\'\n                                                                                                      : ... Suggested alternative: \'wo_2\'\nassign w1_2 = w[6];\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:81: Signal definition not found, creating implicitly: \'w1_3\'\n                                                                                                      : ... Suggested alternative: \'wo_3\'\nassign w1_3 = w[7];\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:78: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                                                   : ... In instance aes_key_expand_128\nassign w1_0 = w[4];\n            ^\n%Warning-WIDTH: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:79: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                                                   : ... In instance aes_key_expand_128\nassign w1_1 = w[5];\n            ^\n%Warning-WIDTH: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:80: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                                                   : ... In instance aes_key_expand_128\nassign w1_2 = w[6];\n            ^\n%Warning-WIDTH: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:81: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                                                   : ... In instance aes_key_expand_128\nassign w1_3 = w[7];\n            ^\n%Error: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:104: Cannot find file containing module: \'aes_sbox\'\naes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24]));\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl,data/full_repos/permissive/175063152/aes_sbox\n             data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl,data/full_repos/permissive/175063152/aes_sbox.v\n             data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl,data/full_repos/permissive/175063152/aes_sbox.sv\n             aes_sbox\n             aes_sbox.v\n             aes_sbox.sv\n             obj_dir/aes_sbox\n             obj_dir/aes_sbox.v\n             obj_dir/aes_sbox.sv\n%Error: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:105: Cannot find file containing module: \'aes_sbox\'\naes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));\n^~~~~~~~\n%Error: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:106: Cannot find file containing module: \'aes_sbox\'\naes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));\n^~~~~~~~\n%Error: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:107: Cannot find file containing module: \'aes_sbox\'\naes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00])); \n^~~~~~~~\n%Error: data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_key_expand_128.v:108: Cannot find file containing module: \'aes_rcon\'\naes_rcon r0( .clk(clk), .kld(kld), .out(rcon[31:24]));\n^~~~~~~~\n%Error: Exiting due to 5 error(s), 8 warning(s)\n'
module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);


input		clk;
input		kld;
input	[127:0]	key;

output	[31:0]	wo_0, wo_1, wo_2, wo_3;


reg	[31:0]	w[7:0];
wire	[31:0]	tmp_w;
wire	[31:0]	subword;
wire	[31:0]	rcon;

assign wo_0 = w[0];
assign wo_1 = w[1];
assign wo_2 = w[2];
assign wo_3 = w[3];

assign w1_0 = w[4];
assign w1_1 = w[5];
assign w1_2 = w[6];
assign w1_3 = w[7];



always @(posedge clk)
		begin 
								w[0] <=  kld ? key[127:096] : w[0]^subword^{rcon[31:24],24'b0};
								w[1] <=  kld ? key[095:064] : w[0]^w[1]^subword^{rcon[31:24],24'b0};
								w[2] <=  kld ? key[063:032] : w[0]^w[2]^w[1]^subword^{rcon[31:24],24'b0};
								w[3] <=  kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^{rcon[31:24],24'b0};
		end

		

assign tmp_w = w[3];



aes_sbox u0(	.a(tmp_w[23:16]), .d(subword[31:24]));
aes_sbox u1(	.a(tmp_w[15:08]), .d(subword[23:16]));
aes_sbox u2(	.a(tmp_w[07:00]), .d(subword[15:08]));
aes_sbox u3(	.a(tmp_w[31:24]), .d(subword[07:00])); 
aes_rcon r0(	.clk(clk), .kld(kld), .out(rcon[31:24]));


endmodule
module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);



input		clk;
input		kld;
input	[127:0]	key;

output	[31:0]	wo_0, wo_1, wo_2, wo_3;


reg	[31:0]	w[7:0];
wire	[31:0]	tmp_w;
wire	[31:0]	subword;
wire	[31:0]	rcon;

assign wo_0 = w[0];
assign wo_1 = w[1];
assign wo_2 = w[2];
assign wo_3 = w[3];

assign w1_0 = w[4];
assign w1_1 = w[5];
assign w1_2 = w[6];
assign w1_3 = w[7];



always @(posedge clk)
		begin 
								w[0] <=  kld ? key[127:096] : w[0]^subword^{rcon[31:24],24'b0};
								w[1] <=  kld ? key[095:064] : w[0]^w[1]^subword^{rcon[31:24],24'b0};
								w[2] <=  kld ? key[063:032] : w[0]^w[2]^w[1]^subword^{rcon[31:24],24'b0};
								w[3] <=  kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^{rcon[31:24],24'b0};
		end

		

assign tmp_w = w[3];



aes_sbox u0(	.a(tmp_w[23:16]), .d(subword[31:24]));
aes_sbox u1(	.a(tmp_w[15:08]), .d(subword[23:16]));
aes_sbox u2(	.a(tmp_w[07:00]), .d(subword[15:08]));
aes_sbox u3(	.a(tmp_w[31:24]), .d(subword[07:00])); 
aes_rcon r0(	.clk(clk), .kld(kld), .out(rcon[31:24]));


endmodule