data/full_repos/permissive/181738725/wavetrace/verilog/wave_capture.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/wave_capture.v:69: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module wave_capture #(
  parameter  DataBits      = 32,
  parameter  PreTrigDepth  = 64,
  parameter  CaptDepth     = 512,
  parameter  ClockHz       = 80000000)
(
  input                    clk,
  input                    rst,

  input [DataBits-1:0]     din_data,

  input [31:0]             cfg_paddr,
  input                    cfg_pwrite,
  input [31:0]             cfg_pwdata,
  input                    cfg_psel,
  input                    cfg_penable,
  output reg               cfg_pready,
  output reg [31:0]        cfg_prdata,
  output                   cfg_pslverr
);

`include "util.vh"

  localparam CaptAddrBits  = clog2(CaptDepth);

  localparam NumBanks = (DataBits + 31) / 32;
  localparam BankAddrBits = clog2(NumBanks);
  localparam TrigRegs = NumBanks;




  localparam
    WhoAmIAddr       = 0,
    CaptDepthAddr    = 1,
    PreTrigDepthAddr = 2,
    DataBitsAddr     = 3,
    ClockHzAddr      = 4,
    TrigModeAddr     = 5,
    TrigCountAddr    = 6,
    CaptCountAddr    = 7,
    SubSampleAddr    = 8,
    GoAddr           = 9,
    CaptStateAddr    = 10,

    TrigMask1Addr    = 16,
    TrigMask2Addr    = 16 + 1*TrigRegs,
    TrigVal1Addr     = 16 + 2*TrigRegs,
    TrigVal2Addr     = 16 + 3*TrigRegs,

    StoreMaskAddr    = 16 + 4*TrigRegs,
    StoreValAddr     = 16 + 5*TrigRegs,
    CaptMemoryAddr   = CaptDepth << BankAddrBits;


  localparam None       = 0,
             Single     = 1,
             Continuous = 2;


  localparam Idle      = 0,
             PreFill   = 1,
             ShiftOut  = 2,
             Capture   = 3,
             Done      = 4,
             NumStates = 5;

  reg [clog2(NumStates)-1:0] state, state_n;




  assign cfg_pslverr = 0;

  reg [1:0]               trig_mode;
  reg [31:0]              trig_count, capt_count;
  reg                     capt_done, go;
  reg                     mem_rd;
  wire [31:0]             mem_data_mux;
  reg [4*TrigRegs*32-1:0] trig_setup_regs;
  reg [2*TrigRegs*32-1:0] store_setup_regs;
  reg [31:0]              sample_ratio;
  wire                    trig_hit, trig_hit_d;

  always @(posedge clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;


    mem_rd     <= 0;
    cfg_pready <= 0;


    if (capt_done) begin
      capt_count <= capt_count + 1;
    end
    if (trig_hit_d & go) begin
      trig_count <= trig_count + 1;
    end

    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        cfg_pready <= 1;
        if (addr_i < 16) begin
          case (addr_i)
            TrigModeAddr:  trig_mode    <= cfg_pwdata;
            TrigCountAddr: trig_count   <= cfg_pwdata;
            CaptCountAddr: capt_count   <= cfg_pwdata;
            SubSampleAddr: sample_ratio <= cfg_pwdata;
            GoAddr:        go           <= cfg_pwdata;
          endcase
        end else if (addr_i < 16 + 4*TrigRegs) begin
          trig_setup_regs[32*(addr_i - 16) +: 32] <= cfg_pwdata;
        end else if (addr_i < 16 + 6*TrigRegs) begin
          store_setup_regs[32*(addr_i - 16 - 4*TrigRegs) +: 32] <= cfg_pwdata;
        end

      end else begin
        if (addr_i < CaptMemoryAddr) begin
          cfg_pready <= 1;
          if (addr_i < 16) begin
            case (addr_i)
              WhoAmIAddr:       cfg_prdata <= 32'hABCD1234;
              CaptDepthAddr:    cfg_prdata <= CaptDepth;
              PreTrigDepthAddr: cfg_prdata <= PreTrigDepth;
              DataBitsAddr:     cfg_prdata <= DataBits;
              ClockHzAddr:      cfg_prdata <= ClockHz;
              TrigModeAddr:     cfg_prdata <= trig_mode;
              GoAddr:           cfg_prdata <= go;
              SubSampleAddr:    cfg_prdata <= sample_ratio;
              TrigCountAddr:    cfg_prdata <= trig_count;
              CaptCountAddr:    cfg_prdata <= capt_count;
              CaptStateAddr:    cfg_prdata <= state;
              default:          cfg_prdata <= 32'hDEADDEAD;
            endcase
          end else if (addr_i < 16 + 4*TrigRegs) begin
            cfg_prdata <= trig_setup_regs[32*(addr_i - 16) +: 32];
          end else if (addr_i < 16 + 6*TrigRegs) begin
            cfg_prdata <= store_setup_regs[32*(addr_i - 16 - 4*TrigRegs) +: 32];
          end else begin
            cfg_prdata <= 32'hDEADDEAD;
          end
        end else begin

          mem_rd <= 1;
        end
      end
    end


    if (mem_rd) begin
      cfg_prdata <= mem_data_mux;
      cfg_pready <= 1;
    end

    if (rst) begin
      trig_mode        <= None;
      trig_setup_regs  <= 0;
      store_setup_regs <= 0;
      trig_count       <= 0;
      capt_count       <= 0;
      go               <= 0;
      sample_ratio     <= 1;
    end
  end


  wire [DataBits-1:0] trig_mask1, trig_mask2, trig_val1, trig_val2, store_mask, store_val;
  assign trig_mask1 = trig_setup_regs[            0 +: DataBits];
  assign trig_mask2 = trig_setup_regs[  TrigRegs*32 +: DataBits];
  assign trig_val1  = trig_setup_regs[2*TrigRegs*32 +: DataBits];
  assign trig_val2  = trig_setup_regs[3*TrigRegs*32 +: DataBits];
  assign store_mask = store_setup_regs[          0 +: DataBits];
  assign store_val  = store_setup_regs[TrigRegs*32 +: DataBits];










  wire                trig1_result, trig2_result, trig_valid;
  wire [DataBits-1:0] trig_data;
  reg [DataBits-1:0]  din_data_d, din_data_dd;



  always @(posedge clk) begin
    din_data_d  <= din_data;
    din_data_dd <= din_data_d;
  end

  mask_compare #(
    .DataBits (DataBits))
  trig_comp1(
    .rst       (rst),
    .clk       (clk),
    .din_valid (1'b1),
    .din_data  (din_data_dd),
    .din_sync  (1'b0),
    .mask      (trig_mask1),
    .value     (trig_val1),
    .dout_valid( ),
    .dout_data ( ),
    .dout_sync ( ),
    .result    (trig1_result));

  mask_compare #(
    .DataBits (DataBits))
  trig_comp2(
    .rst       (rst),
    .clk       (clk),
    .din_valid (1'b1),
    .din_data  (din_data_d),
    .din_sync  (1'b0),
    .mask      (trig_mask2),
    .value     (trig_val2),
    .dout_valid(trig_valid),
    .dout_data (trig_data),
    .dout_sync ( ),
    .result    (trig2_result));


  assign trig_hit = trig_valid & trig1_result & trig2_result & (trig_mode != None);




  wire                store_valid, store_result;
  wire [DataBits-1:0] store_data;

  mask_compare #(
    .DataBits (DataBits))
  store_comp(
    .rst       (rst),
    .clk       (clk),
    .din_valid (trig_valid),
    .din_data  (trig_data),
    .din_sync  (trig_hit),
    .mask      (store_mask),
    .value     (store_val),
    .dout_valid(store_valid),
    .dout_data (store_data),
    .dout_sync (trig_hit_d),
    .result    (store_result));









  wire qual_valid = store_valid & (trig_hit_d || store_result);







  reg [31:0] sample_count;
  always @(posedge clk) begin
    if (qual_valid) begin
      if (sample_ratio > 1) begin
        if (trig_hit_d)
          sample_count <= 1;
        else if (sample_count == sample_ratio - 1)
          sample_count <= 0;
        else
          sample_count <= sample_count + 1;
      end else begin
        sample_count <= 0;
      end
    end
    if (rst) begin
      sample_count <= 0;
    end
  end

  wire sample_valid = (sample_count == 0 || trig_hit_d) ? qual_valid : 0;








  localparam UsedBits  = clog2(PreTrigDepth+2);

  wire                fifo_valid;
  wire [DataBits-1:0] fifo_data;
  wire [UsedBits-1:0] fifo_used;
  reg                 fifo_ready;

  stream_fifo_1clk #(
    .Width    (DataBits),
    .Depth    (PreTrigDepth+2))
  fifo(
    .rst       (rst),
    .clk       (clk),

    .din_valid (sample_valid),
    .din_ready ( ),
    .din_data  (store_data),

    .dout_valid(fifo_valid),
    .dout_ready(fifo_ready),
    .dout_data (fifo_data),
    .used      (fifo_used));




  reg [CaptAddrBits-1:0]     wr_addr, wr_addr_n;
  reg                        wr_en;

  always @(*) begin

    state_n     = state;
    wr_addr_n   = wr_addr;
    wr_en       = 0;
    capt_done   = 0;
    fifo_ready  = 1;

    case (state)

      Idle:
        begin
          if (go) begin
            state_n = PreFill;
          end
        end

      PreFill:
        begin
          fifo_ready = 0;
          if (trig_hit_d || trig_mode == None) begin
            state_n   = Capture;
            wr_addr_n = 0;
          end else if (fifo_used >= PreTrigDepth+1) begin
            state_n = ShiftOut;
          end
          if (!go) state_n = Idle;
        end

      ShiftOut:
        begin
          fifo_ready = sample_valid;
          if (trig_hit_d) begin
            state_n   = Capture;
            wr_addr_n = 0;
          end
          if (!go) state_n = Idle;
        end

      Capture:
        begin
          wr_en       = fifo_valid;
          wr_addr_n   = wr_addr + wr_en;
          if (trig_mode == Continuous && trig_hit_d) begin

            wr_addr_n = 0;
          end else if (wr_addr == CaptDepth-1 && wr_en) begin
            capt_done = 1;
            state_n   = (trig_mode == Continuous) ? PreFill : Done;
          end
          if (!go) state_n  = Idle;
        end

      Done:
        begin
          if (!go) state_n = Idle;
        end
    endcase
  end

  always @(posedge clk) begin
    state   <= state_n;
    wr_addr <= wr_addr_n;
    if (rst) begin
      state <= Idle;
    end
  end




  wire [DataBits-1:0]     mem_data;
  wire [CaptAddrBits-1:0] rd_addr = cfg_paddr[2 +: CaptAddrBits];

  ram_1c_1r_1w #(
    .Width (DataBits),
    .Depth (CaptDepth))
  mem(
    .clk     (clk),
    .wr_en   (wr_en),
    .wr_addr (wr_addr),
    .wr_data (fifo_data),
    .rd_addr (rd_addr),
    .rd_data (mem_data));

  generate
    if (NumBanks > 1) begin :multi_banks

      wire [NumBanks*32-1:0]  mem_data_padded = mem_data;
      wire [BankAddrBits-1:0] bank_addr = cfg_paddr[CaptAddrBits+2 +: BankAddrBits];
      assign mem_data_mux = mem_data_padded[bank_addr*32 +: 32];
    end else begin :one_bank
      assign mem_data_mux = mem_data;
    end
  endgenerate

endmodule
module wave_capture #(
  parameter  DataBits      = 32,
  parameter  PreTrigDepth  = 64,
  parameter  CaptDepth     = 512,
  parameter  ClockHz       = 80000000)
(
  input                    clk,
  input                    rst,

  input [DataBits-1:0]     din_data,

  input [31:0]             cfg_paddr,
  input                    cfg_pwrite,
  input [31:0]             cfg_pwdata,
  input                    cfg_psel,
  input                    cfg_penable,
  output reg               cfg_pready,
  output reg [31:0]        cfg_prdata,
  output                   cfg_pslverr
);


`include "util.vh"

  localparam CaptAddrBits  = clog2(CaptDepth);

  localparam NumBanks = (DataBits + 31) / 32;
  localparam BankAddrBits = clog2(NumBanks);
  localparam TrigRegs = NumBanks;




  localparam
    WhoAmIAddr       = 0,
    CaptDepthAddr    = 1,
    PreTrigDepthAddr = 2,
    DataBitsAddr     = 3,
    ClockHzAddr      = 4,
    TrigModeAddr     = 5,
    TrigCountAddr    = 6,
    CaptCountAddr    = 7,
    SubSampleAddr    = 8,
    GoAddr           = 9,
    CaptStateAddr    = 10,

    TrigMask1Addr    = 16,
    TrigMask2Addr    = 16 + 1*TrigRegs,
    TrigVal1Addr     = 16 + 2*TrigRegs,
    TrigVal2Addr     = 16 + 3*TrigRegs,

    StoreMaskAddr    = 16 + 4*TrigRegs,
    StoreValAddr     = 16 + 5*TrigRegs,
    CaptMemoryAddr   = CaptDepth << BankAddrBits;


  localparam None       = 0,
             Single     = 1,
             Continuous = 2;


  localparam Idle      = 0,
             PreFill   = 1,
             ShiftOut  = 2,
             Capture   = 3,
             Done      = 4,
             NumStates = 5;

  reg [clog2(NumStates)-1:0] state, state_n;




  assign cfg_pslverr = 0;

  reg [1:0]               trig_mode;
  reg [31:0]              trig_count, capt_count;
  reg                     capt_done, go;
  reg                     mem_rd;
  wire [31:0]             mem_data_mux;
  reg [4*TrigRegs*32-1:0] trig_setup_regs;
  reg [2*TrigRegs*32-1:0] store_setup_regs;
  reg [31:0]              sample_ratio;
  wire                    trig_hit, trig_hit_d;

  always @(posedge clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;


    mem_rd     <= 0;
    cfg_pready <= 0;


    if (capt_done) begin
      capt_count <= capt_count + 1;
    end
    if (trig_hit_d & go) begin
      trig_count <= trig_count + 1;
    end

    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        cfg_pready <= 1;
        if (addr_i < 16) begin
          case (addr_i)
            TrigModeAddr:  trig_mode    <= cfg_pwdata;
            TrigCountAddr: trig_count   <= cfg_pwdata;
            CaptCountAddr: capt_count   <= cfg_pwdata;
            SubSampleAddr: sample_ratio <= cfg_pwdata;
            GoAddr:        go           <= cfg_pwdata;
          endcase
        end else if (addr_i < 16 + 4*TrigRegs) begin
          trig_setup_regs[32*(addr_i - 16) +: 32] <= cfg_pwdata;
        end else if (addr_i < 16 + 6*TrigRegs) begin
          store_setup_regs[32*(addr_i - 16 - 4*TrigRegs) +: 32] <= cfg_pwdata;
        end

      end else begin
        if (addr_i < CaptMemoryAddr) begin
          cfg_pready <= 1;
          if (addr_i < 16) begin
            case (addr_i)
              WhoAmIAddr:       cfg_prdata <= 32'hABCD1234;
              CaptDepthAddr:    cfg_prdata <= CaptDepth;
              PreTrigDepthAddr: cfg_prdata <= PreTrigDepth;
              DataBitsAddr:     cfg_prdata <= DataBits;
              ClockHzAddr:      cfg_prdata <= ClockHz;
              TrigModeAddr:     cfg_prdata <= trig_mode;
              GoAddr:           cfg_prdata <= go;
              SubSampleAddr:    cfg_prdata <= sample_ratio;
              TrigCountAddr:    cfg_prdata <= trig_count;
              CaptCountAddr:    cfg_prdata <= capt_count;
              CaptStateAddr:    cfg_prdata <= state;
              default:          cfg_prdata <= 32'hDEADDEAD;
            endcase
          end else if (addr_i < 16 + 4*TrigRegs) begin
            cfg_prdata <= trig_setup_regs[32*(addr_i - 16) +: 32];
          end else if (addr_i < 16 + 6*TrigRegs) begin
            cfg_prdata <= store_setup_regs[32*(addr_i - 16 - 4*TrigRegs) +: 32];
          end else begin
            cfg_prdata <= 32'hDEADDEAD;
          end
        end else begin

          mem_rd <= 1;
        end
      end
    end


    if (mem_rd) begin
      cfg_prdata <= mem_data_mux;
      cfg_pready <= 1;
    end

    if (rst) begin
      trig_mode        <= None;
      trig_setup_regs  <= 0;
      store_setup_regs <= 0;
      trig_count       <= 0;
      capt_count       <= 0;
      go               <= 0;
      sample_ratio     <= 1;
    end
  end


  wire [DataBits-1:0] trig_mask1, trig_mask2, trig_val1, trig_val2, store_mask, store_val;
  assign trig_mask1 = trig_setup_regs[            0 +: DataBits];
  assign trig_mask2 = trig_setup_regs[  TrigRegs*32 +: DataBits];
  assign trig_val1  = trig_setup_regs[2*TrigRegs*32 +: DataBits];
  assign trig_val2  = trig_setup_regs[3*TrigRegs*32 +: DataBits];
  assign store_mask = store_setup_regs[          0 +: DataBits];
  assign store_val  = store_setup_regs[TrigRegs*32 +: DataBits];










  wire                trig1_result, trig2_result, trig_valid;
  wire [DataBits-1:0] trig_data;
  reg [DataBits-1:0]  din_data_d, din_data_dd;



  always @(posedge clk) begin
    din_data_d  <= din_data;
    din_data_dd <= din_data_d;
  end

  mask_compare #(
    .DataBits (DataBits))
  trig_comp1(
    .rst       (rst),
    .clk       (clk),
    .din_valid (1'b1),
    .din_data  (din_data_dd),
    .din_sync  (1'b0),
    .mask      (trig_mask1),
    .value     (trig_val1),
    .dout_valid( ),
    .dout_data ( ),
    .dout_sync ( ),
    .result    (trig1_result));

  mask_compare #(
    .DataBits (DataBits))
  trig_comp2(
    .rst       (rst),
    .clk       (clk),
    .din_valid (1'b1),
    .din_data  (din_data_d),
    .din_sync  (1'b0),
    .mask      (trig_mask2),
    .value     (trig_val2),
    .dout_valid(trig_valid),
    .dout_data (trig_data),
    .dout_sync ( ),
    .result    (trig2_result));


  assign trig_hit = trig_valid & trig1_result & trig2_result & (trig_mode != None);




  wire                store_valid, store_result;
  wire [DataBits-1:0] store_data;

  mask_compare #(
    .DataBits (DataBits))
  store_comp(
    .rst       (rst),
    .clk       (clk),
    .din_valid (trig_valid),
    .din_data  (trig_data),
    .din_sync  (trig_hit),
    .mask      (store_mask),
    .value     (store_val),
    .dout_valid(store_valid),
    .dout_data (store_data),
    .dout_sync (trig_hit_d),
    .result    (store_result));









  wire qual_valid = store_valid & (trig_hit_d || store_result);







  reg [31:0] sample_count;
  always @(posedge clk) begin
    if (qual_valid) begin
      if (sample_ratio > 1) begin
        if (trig_hit_d)
          sample_count <= 1;
        else if (sample_count == sample_ratio - 1)
          sample_count <= 0;
        else
          sample_count <= sample_count + 1;
      end else begin
        sample_count <= 0;
      end
    end
    if (rst) begin
      sample_count <= 0;
    end
  end

  wire sample_valid = (sample_count == 0 || trig_hit_d) ? qual_valid : 0;








  localparam UsedBits  = clog2(PreTrigDepth+2);

  wire                fifo_valid;
  wire [DataBits-1:0] fifo_data;
  wire [UsedBits-1:0] fifo_used;
  reg                 fifo_ready;

  stream_fifo_1clk #(
    .Width    (DataBits),
    .Depth    (PreTrigDepth+2))
  fifo(
    .rst       (rst),
    .clk       (clk),

    .din_valid (sample_valid),
    .din_ready ( ),
    .din_data  (store_data),

    .dout_valid(fifo_valid),
    .dout_ready(fifo_ready),
    .dout_data (fifo_data),
    .used      (fifo_used));




  reg [CaptAddrBits-1:0]     wr_addr, wr_addr_n;
  reg                        wr_en;

  always @(*) begin

    state_n     = state;
    wr_addr_n   = wr_addr;
    wr_en       = 0;
    capt_done   = 0;
    fifo_ready  = 1;

    case (state)

      Idle:
        begin
          if (go) begin
            state_n = PreFill;
          end
        end

      PreFill:
        begin
          fifo_ready = 0;
          if (trig_hit_d || trig_mode == None) begin
            state_n   = Capture;
            wr_addr_n = 0;
          end else if (fifo_used >= PreTrigDepth+1) begin
            state_n = ShiftOut;
          end
          if (!go) state_n = Idle;
        end

      ShiftOut:
        begin
          fifo_ready = sample_valid;
          if (trig_hit_d) begin
            state_n   = Capture;
            wr_addr_n = 0;
          end
          if (!go) state_n = Idle;
        end

      Capture:
        begin
          wr_en       = fifo_valid;
          wr_addr_n   = wr_addr + wr_en;
          if (trig_mode == Continuous && trig_hit_d) begin

            wr_addr_n = 0;
          end else if (wr_addr == CaptDepth-1 && wr_en) begin
            capt_done = 1;
            state_n   = (trig_mode == Continuous) ? PreFill : Done;
          end
          if (!go) state_n  = Idle;
        end

      Done:
        begin
          if (!go) state_n = Idle;
        end
    endcase
  end

  always @(posedge clk) begin
    state   <= state_n;
    wr_addr <= wr_addr_n;
    if (rst) begin
      state <= Idle;
    end
  end




  wire [DataBits-1:0]     mem_data;
  wire [CaptAddrBits-1:0] rd_addr = cfg_paddr[2 +: CaptAddrBits];

  ram_1c_1r_1w #(
    .Width (DataBits),
    .Depth (CaptDepth))
  mem(
    .clk     (clk),
    .wr_en   (wr_en),
    .wr_addr (wr_addr),
    .wr_data (fifo_data),
    .rd_addr (rd_addr),
    .rd_data (mem_data));

  generate
    if (NumBanks > 1) begin :multi_banks

      wire [NumBanks*32-1:0]  mem_data_padded = mem_data;
      wire [BankAddrBits-1:0] bank_addr = cfg_paddr[CaptAddrBits+2 +: BankAddrBits];
      assign mem_data_mux = mem_data_padded[bank_addr*32 +: 32];
    end else begin :one_bank
      assign mem_data_mux = mem_data;
    end
  endgenerate

endmodule