data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Reg.v
data/verilator_xmls/c55b84cc-9f4c-481e-8629-4bb4fc80647f.xml
module Reg #(
        parameter DATA_WIDTH = 32
    )(
        input [DATA_WIDTH - 1:0] data_in,
        input enable,
        input clk,
        input rst,
        output reg [DATA_WIDTH - 1:0] data_out
    );

    initial begin
        data_out = 0;
    end

    always @(posedge clk or posedge rst) begin
        if (rst == 1) begin
            data_out = 0;
        end
        else if (enable != 0) begin
            data_out <= data_in;
        end
    end
endmodule
module Reg #(
        parameter DATA_WIDTH = 32
    )(
        input [DATA_WIDTH - 1:0] data_in,
        input enable,
        input clk,
        input rst,
        output reg [DATA_WIDTH - 1:0] data_out
    );


    initial begin
        data_out = 0;
    end

    always @(posedge clk or posedge rst) begin
        if (rst == 1) begin
            data_out = 0;
        end
        else if (enable != 0) begin
            data_out <= data_in;
        end
    end
endmodule