data/full_repos/permissive/202237519/verilog/ripple_carry_adder/ripple_carry_adder_tb.v
 line:59: before: "$"
1: b'%Error: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/ripple_carry_adder_tb.v:1: Cannot find include file: ripple_carry_adder.v\n`include "ripple_carry_adder.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/ripple_carry_adder.v\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/ripple_carry_adder.v.v\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/ripple_carry_adder.v.sv\n             ripple_carry_adder.v\n             ripple_carry_adder.v.v\n             ripple_carry_adder.v.sv\n             obj_dir/ripple_carry_adder.v\n             obj_dir/ripple_carry_adder.v.v\n             obj_dir/ripple_carry_adder.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/ripple_carry_adder_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("ripple_carry_adder_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/ripple_carry_adder_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,ripple_carry_adder_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/ripple_carry_adder_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5  A <= 10\'d31; B <= 10\'d41; C_in <= 10\'d1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/ripple_carry_adder_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module ripple_carry_adder_tb;

reg [9:0] A,B;
reg C_in;
wire [9:0] Sum;
wire C_out;

ripple_carry_adder rca(A,B,C_in,Sum,C_out);

initial begin
$dumpfile("ripple_carry_adder_tb.vcd");
$dumpvars(0,ripple_carry_adder_tb);

    A <= 10'd20; B <= 10'd30; C_in <= 10'd0;
#5  A <= 10'd31; B <= 10'd41; C_in <= 10'd1;
#5
$finish;
end




endmodule
module ripple_carry_adder_tb;


reg [9:0] A,B;
reg C_in;
wire [9:0] Sum;
wire C_out;

ripple_carry_adder rca(A,B,C_in,Sum,C_out);

initial begin
$dumpfile("ripple_carry_adder_tb.vcd");
$dumpvars(0,ripple_carry_adder_tb);

    A <= 10'd20; B <= 10'd30; C_in <= 10'd0;
#5  A <= 10'd31; B <= 10'd41; C_in <= 10'd1;
#5
$finish;
end




endmodule