data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/testbench/Simon_bit_serial_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/testbench/Simon_bit_serial_testbench.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #110;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/testbench/Simon_bit_serial_testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/testbench/Simon_bit_serial_testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n   #20;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/testbench/Simon_bit_serial_testbench.v:74: Unsupported: Ignoring delay on this delayed statement.\n   #20;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/testbench/Simon_bit_serial_testbench.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/testbench/Simon_bit_serial_testbench.v:88: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/testbench/Simon_bit_serial_testbench.v:42: Cannot find file containing module: \'top_module\'\n top_module uut (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/testbench,data/full_repos/permissive/137416811/top_module\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/testbench,data/full_repos/permissive/137416811/top_module.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/testbench,data/full_repos/permissive/137416811/top_module.sv\n             top_module\n             top_module.v\n             top_module.sv\n             obj_dir/top_module\n             obj_dir/top_module.v\n             obj_dir/top_module.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_module_test;


	reg clk;
	reg data_in;
	reg [1:0] data_rdy;


	wire cipher_out;
	

	reg [127:0] plaintext = 128'h63736564207372656c6c657661727420;
	reg [127:0] key = 128'h0f0e0d0c0b0a09080706050403020100;
	
	integer i;


	top_module uut (
		.clk(clk), 
		.data_in(data_in), 
		.data_rdy(data_rdy), 
		.cipher_out(cipher_out)
	);

	initial begin

		clk = 0;
		data_in = 0;
		data_rdy = 0;

		#110;
		#5;

		data_rdy=1;
		

		for(i=0;i<128;i = i+1)
		begin
			data_in = plaintext[i];
			#20;
		end
		

		data_rdy = 2;
			

		for(i=0;i<128;i = i+1)
		begin
			data_in = key[i];
			#20;
		end

		data_rdy = 0;
		#20;
		

		data_rdy = 3;


	end
	

	
	always #10 clk = ~clk;
        

      
endmodule
module top_module_test;



	reg clk;
	reg data_in;
	reg [1:0] data_rdy;


	wire cipher_out;
	

	reg [127:0] plaintext = 128'h63736564207372656c6c657661727420;
	reg [127:0] key = 128'h0f0e0d0c0b0a09080706050403020100;
	
	integer i;


	top_module uut (
		.clk(clk), 
		.data_in(data_in), 
		.data_rdy(data_rdy), 
		.cipher_out(cipher_out)
	);

	initial begin

		clk = 0;
		data_in = 0;
		data_rdy = 0;

		#110;
		#5;

		data_rdy=1;
		

		for(i=0;i<128;i = i+1)
		begin
			data_in = plaintext[i];
			#20;
		end
		

		data_rdy = 2;
			

		for(i=0;i<128;i = i+1)
		begin
			data_in = key[i];
			#20;
		end

		data_rdy = 0;
		#20;
		

		data_rdy = 3;


	end
	

	
	always #10 clk = ~clk;
        

      
endmodule