data/full_repos/permissive/159891569/swDac.t.v
 line:32: before: "+"
1: b'%Error: data/full_repos/permissive/159891569/swDac.t.v:1: Cannot find include file: swDac.v\n`include "swDac.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/swDac.v\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/swDac.v.v\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/swDac.v.sv\n             swDac.v\n             swDac.v.v\n             swDac.v.sv\n             obj_dir/swDac.v\n             obj_dir/swDac.v.v\n             obj_dir/swDac.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/159891569/swDac.t.v:19: Unsupported: Ignoring delay on this delayed statement.\n   #1000;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module testSwDac();

	reg [3:0] left, right;
	reg [31:0] i;

	swDac dut(left, right);

	initial begin
		left = 0; right = 0;


		for (i = 0; i < 4194304; i += `PERIOD) begin
			left += 1;
			right += 1;
			#`PERIOD;
		end

		$finish;
	end

endmodule
module testSwDac();


	reg [3:0] left, right;
	reg [31:0] i;

	swDac dut(left, right);

	initial begin
		left = 0; right = 0;


		for (i = 0; i < 4194304; i += `PERIOD) begin
			left += 1;
			right += 1;
			#`PERIOD;
		end

		$finish;
	end

endmodule