data/full_repos/permissive/143278/ivltests/signed8.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/signed8.v:46: Unsupported: Ignoring delay on this delayed statement.\n         #1 if(p !== prod[15:0]) begin\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed8.v:26: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 5 bits.\n                                                                       : ... In instance test_mult.dut\nassign ta = a;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed8.v:29: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'pt\' generates 13 bits.\n                                                                       : ... In instance test_mult.dut\nassign p=pt;\n        ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mult58s(input [4:0] a, input signed [7:0] b, output signed [15:0] p);

wire signed [12:0] pt;

wire signed [5:0] ta;

assign ta = a;
assign pt =  b * ta;

assign p=pt;

endmodule
module mult58s(input [4:0] a, input signed [7:0] b, output signed [15:0] p);


wire signed [12:0] pt;

wire signed [5:0] ta;

assign ta = a;
assign pt =  b * ta;

assign p=pt;

endmodule