data/full_repos/permissive/109216392/src/cjg_clkgen.v
1: b"%Error: data/full_repos/permissive/109216392/src/cjg_clkgen.v:25: Cannot find file containing module: 'CLKBUFX4'\nCLKBUFX4 clk_p1_buf (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109216392/src,data/full_repos/permissive/109216392/CLKBUFX4\n             data/full_repos/permissive/109216392/src,data/full_repos/permissive/109216392/CLKBUFX4.v\n             data/full_repos/permissive/109216392/src,data/full_repos/permissive/109216392/CLKBUFX4.sv\n             CLKBUFX4\n             CLKBUFX4.v\n             CLKBUFX4.sv\n             obj_dir/CLKBUFX4\n             obj_dir/CLKBUFX4.v\n             obj_dir/CLKBUFX4.sv\n%Error: data/full_repos/permissive/109216392/src/cjg_clkgen.v:31: Cannot find file containing module: 'CLKBUFX4'\nCLKBUFX4 clk_p2_buf (\n^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module cjg_clkgen (

    input reset,
    input clk,


    output clk_p1,
    output clk_p2,


    input scan_in0,
    input scan_en,
    input test_mode,
    output scan_out0
);


reg[1:0] clk_cnt;


wire pre_p1 = (~clk_cnt[1] & ~clk_cnt[0]);
wire pre_p2 = (clk_cnt[1] & ~clk_cnt[0]);


CLKBUFX4 clk_p1_buf (
    .A(pre_p1),
    .Y(clk_p1)
);


CLKBUFX4 clk_p2_buf (
    .A(pre_p2),
    .Y(clk_p2)
);


always @ (posedge clk, negedge reset) begin
    if(~reset) begin
        clk_cnt <= 2'h0;
    end 
    else begin
        clk_cnt <= clk_cnt + 1'b1;
    end
end

endmodule
module cjg_clkgen (

    input reset,
    input clk,


    output clk_p1,
    output clk_p2,


    input scan_in0,
    input scan_en,
    input test_mode,
    output scan_out0
);



reg[1:0] clk_cnt;


wire pre_p1 = (~clk_cnt[1] & ~clk_cnt[0]);
wire pre_p2 = (clk_cnt[1] & ~clk_cnt[0]);


CLKBUFX4 clk_p1_buf (
    .A(pre_p1),
    .Y(clk_p1)
);


CLKBUFX4 clk_p2_buf (
    .A(pre_p2),
    .Y(clk_p2)
);


always @ (posedge clk, negedge reset) begin
    if(~reset) begin
        clk_cnt <= 2'h0;
    end 
    else begin
        clk_cnt <= clk_cnt + 1'b1;
    end
end

endmodule