data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/pxlCount.v
1: b"%Error: data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/pxlCount.v:34: Cannot find file containing module: 'syncCorrector'\nsyncCorrector corrector1(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181415525/danmaku_de2/overlay_logic,data/full_repos/permissive/181415525/syncCorrector\n             data/full_repos/permissive/181415525/danmaku_de2/overlay_logic,data/full_repos/permissive/181415525/syncCorrector.v\n             data/full_repos/permissive/181415525/danmaku_de2/overlay_logic,data/full_repos/permissive/181415525/syncCorrector.sv\n             syncCorrector\n             syncCorrector.v\n             syncCorrector.sv\n             obj_dir/syncCorrector\n             obj_dir/syncCorrector.v\n             obj_dir/syncCorrector.sv\n%Error: Exiting due to 1 error(s)\n"
module pxlCounter(
  input wire odck,
  input wire scdt,
  input wire vsyncIn,
  input wire hsyncIn,
  input wire deIn,
  input wire rst,

  output reg [15:0] nowX,
  output reg [15:0] nowY,
  output reg [31:0] nowPxl,

  output reg [15:0] screenX,
  output reg [15:0] screenY,
  output reg [31:0] screenPxl,
  
  output wire ovf
);

reg ovfX, ovfY;
reg thisOvfX, thisOvfY, thisOvfZ;
reg lastDe, lastVsync;

wire vsync, hsync, de;

syncCorrector corrector1(
  odck,
  rst,
  
  vsyncIn,
  hsyncIn,
  deIn,
  
  vsync,
  hsync,
  de
);

assign ovf = ovfX | ovfY;


always @(posedge odck or negedge rst) begin

  if (rst == 0) begin
    nowX <= 0;
    nowY <= 0;
    nowPxl <= 0;
    screenX <= 0;
    screenY <= 0;
    screenPxl <= 0;
    lastDe <= 0;
    ovfX <= 0;
    ovfY <= 0;
  end else if (scdt == 0) begin
    nowX <= 0;
    nowY <= 0;
    nowPxl <= 0;
    screenX <= 0;
    screenY <= 0;
    screenPxl <= 0;
    lastDe <= 0;
  end else begin
  
    lastVsync <= vsync;
    lastDe <= de;

    if(de) begin
      nowX <= nowX + 1;
    end else begin
      if(lastDe)begin
        screenX <= nowX;
      end
      nowX <= 0;
    end
    

    
    if(!de) begin
      if(lastDe)begin
        nowY <= nowY + 1;
      end else if(!vsync) begin
        if(lastVsync) begin
          screenY  <= nowY;
        end
        nowY <= 0;
      end 
    end
    

    
    if(de) begin 
      nowPxl <= nowPxl + 1;
    end else begin
      if(!vsync) begin
        if(lastVsync) begin
          screenPxl <= nowPxl;
        end
        nowPxl <= 0;
      end
    end
  end

end



endmodule
module pxlCounter(
  input wire odck,
  input wire scdt,
  input wire vsyncIn,
  input wire hsyncIn,
  input wire deIn,
  input wire rst,

  output reg [15:0] nowX,
  output reg [15:0] nowY,
  output reg [31:0] nowPxl,

  output reg [15:0] screenX,
  output reg [15:0] screenY,
  output reg [31:0] screenPxl,
  
  output wire ovf
);


reg ovfX, ovfY;
reg thisOvfX, thisOvfY, thisOvfZ;
reg lastDe, lastVsync;

wire vsync, hsync, de;

syncCorrector corrector1(
  odck,
  rst,
  
  vsyncIn,
  hsyncIn,
  deIn,
  
  vsync,
  hsync,
  de
);

assign ovf = ovfX | ovfY;


always @(posedge odck or negedge rst) begin

  if (rst == 0) begin
    nowX <= 0;
    nowY <= 0;
    nowPxl <= 0;
    screenX <= 0;
    screenY <= 0;
    screenPxl <= 0;
    lastDe <= 0;
    ovfX <= 0;
    ovfY <= 0;
  end else if (scdt == 0) begin
    nowX <= 0;
    nowY <= 0;
    nowPxl <= 0;
    screenX <= 0;
    screenY <= 0;
    screenPxl <= 0;
    lastDe <= 0;
  end else begin
  
    lastVsync <= vsync;
    lastDe <= de;

    if(de) begin
      nowX <= nowX + 1;
    end else begin
      if(lastDe)begin
        screenX <= nowX;
      end
      nowX <= 0;
    end
    

    
    if(!de) begin
      if(lastDe)begin
        nowY <= nowY + 1;
      end else if(!vsync) begin
        if(lastVsync) begin
          screenY  <= nowY;
        end
        nowY <= 0;
      end 
    end
    

    
    if(de) begin 
      nowPxl <= nowPxl + 1;
    end else begin
      if(!vsync) begin
        if(lastVsync) begin
          screenPxl <= nowPxl;
        end
        nowPxl <= 0;
      end
    end
  end

end



endmodule