data/full_repos/permissive/165217789/FusionAccel/testbench/scmp_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/testbench/scmp_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/testbench/scmp_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #20 rst = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/testbench/scmp_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/testbench/scmp_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #100 pool_valid = 1;\n    ^\n%Error: data/full_repos/permissive/165217789/FusionAccel/testbench/scmp_tb.v:27: Cannot find file containing module: \'scmp\'\nscmp scmp_(  \n^~~~\n        ... Looked in:\n             data/full_repos/permissive/165217789/FusionAccel/testbench,data/full_repos/permissive/165217789/scmp\n             data/full_repos/permissive/165217789/FusionAccel/testbench,data/full_repos/permissive/165217789/scmp.v\n             data/full_repos/permissive/165217789/FusionAccel/testbench,data/full_repos/permissive/165217789/scmp.sv\n             scmp\n             scmp.v\n             scmp.sv\n             obj_dir/scmp\n             obj_dir/scmp.v\n             obj_dir/scmp.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module scmp_tb;

reg clk;
reg rst;
reg [15:0] data;
wire [15:0] result;
reg pool_valid;
wire pool_ready;
wire data_valid;
reg data_ready;

reg [15:0] data_fifo [0:8];

initial begin
    data_fifo[0] = 16'h4600;
    data_fifo[1] = 16'h4200;
    data_fifo[2] = 16'h4000;
    data_fifo[3] = 16'h4800;
    data_fifo[4] = 16'h4400;
    data_fifo[5] = 16'h4880;
    data_fifo[6] = 16'h4700;
    data_fifo[7] = 16'h4500;
    data_fifo[8] = 16'h3c00;
end

scmp scmp_(
    .clk (clk),
    .rst (rst),
    .data (data),
    .result (result),
    .pool_valid (pool_valid),
    .pool_ready (pool_ready),
    .data_ready (data_ready),
    .data_valid (data_valid)
);

always #5 clk = ~clk;
integer i;
initial begin
    rst = 1;
    clk = 0;
    i = 0;
    pool_valid = 0;
    data = 16'h0000;
    data_ready = 0;
    #20 rst = 1;
    #10 rst = 0;
    #100 pool_valid = 1;
end

always @(posedge pool_ready) pool_valid <= 0;

always @(posedge clk) begin
    if(data_valid && pool_valid) begin
        data_ready <= 1;
        data <= data_fifo[i];
        if(i < 9) i <= i + 1;
        else data_ready <= 0;
    end
end

endmodule
module scmp_tb;


reg clk;
reg rst;
reg [15:0] data;
wire [15:0] result;
reg pool_valid;
wire pool_ready;
wire data_valid;
reg data_ready;

reg [15:0] data_fifo [0:8];

initial begin
    data_fifo[0] = 16'h4600;
    data_fifo[1] = 16'h4200;
    data_fifo[2] = 16'h4000;
    data_fifo[3] = 16'h4800;
    data_fifo[4] = 16'h4400;
    data_fifo[5] = 16'h4880;
    data_fifo[6] = 16'h4700;
    data_fifo[7] = 16'h4500;
    data_fifo[8] = 16'h3c00;
end

scmp scmp_(
    .clk (clk),
    .rst (rst),
    .data (data),
    .result (result),
    .pool_valid (pool_valid),
    .pool_ready (pool_ready),
    .data_ready (data_ready),
    .data_valid (data_valid)
);

always #5 clk = ~clk;
integer i;
initial begin
    rst = 1;
    clk = 0;
    i = 0;
    pool_valid = 0;
    data = 16'h0000;
    data_ready = 0;
    #20 rst = 1;
    #10 rst = 0;
    #100 pool_valid = 1;
end

always @(posedge pool_ready) pool_valid <= 0;

always @(posedge clk) begin
    if(data_valid && pool_valid) begin
        data_ready <= 1;
        data <= data_fifo[i];
        if(i < 9) i <= i + 1;
        else data_ready <= 0;
    end
end

endmodule