data/full_repos/permissive/115487336/mycode/Mips/MonoCycle-Mips/pc.v
data/verilator_xmls/1c8c90c4-3b12-4549-ba21-7eee5169f30b.xml
module pc(
	input clk,
	input rst_n,
	input muxer,
	input [31:0] addr,
	output [31:0] now_addr
);

assign now_addr=nowaddr;

reg [31:0] nowaddr;
reg [31:0] nextaddr;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		nowaddr<=32'hFFFF_FFFB;
	end
	else
	begin
		if(nextaddr==32'hFFFF_FFFF)
			nowaddr<=0;
		else
			nowaddr<= ( muxer ? addr : nextaddr);
	end
end



always@(*)
begin
	nextaddr=nowaddr+32'h4;
end


endmodule
module pc(
	input clk,
	input rst_n,
	input muxer,
	input [31:0] addr,
	output [31:0] now_addr
);


assign now_addr=nowaddr;

reg [31:0] nowaddr;
reg [31:0] nextaddr;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		nowaddr<=32'hFFFF_FFFB;
	end
	else
	begin
		if(nextaddr==32'hFFFF_FFFF)
			nowaddr<=0;
		else
			nowaddr<= ( muxer ? addr : nextaddr);
	end
end



always@(*)
begin
	nextaddr=nowaddr+32'h4;
end


endmodule