data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v
 line:68: before: "#"
1: b'%Error: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:27: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("jeff-74x161-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:28: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, jeff_74x161_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #15; CLR_BAR = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #20; CLR_BAR = 1; LD_BAR = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #20 LD_BAR = 1;     \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #300\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #20; CLR_BAR = 1; LD_BAR = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #300\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #20 LD_BAR = 1;     \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161-tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Error: Exiting due to 2 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module jeff_74x161_tb;


reg        CLR_BAR, LD_BAR;
reg        ENT, ENP;
reg        CLK;
reg        A, B, C, D;
wire       QA, QB, QC, QD;
wire       RCO;


jeff_74x161 uut(
    .clr_bar(CLR_BAR), .ld_bar(LD_BAR),
    .ent(ENT), .enp(ENP),
    .clk(CLK),
    .a(A), .b(B), .c(C), .d(D),
    .qa(QA), .qb(QB), .qc(QC), .qd(QD),
    .rco(RCO)
);


initial begin
    $dumpfile("jeff-74x161-tb.vcd");
    $dumpvars(0, jeff_74x161_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLR_BAR = 1; LD_BAR = 1;
    ENT = 0; ENP = 0;
    CLK = 0;
    D = 0; C = 0; B = 0; A = 0;


    #15; CLR_BAR = 0;


    #20; CLR_BAR = 1; LD_BAR = 0;
         D = 1; C = 1; B = 0; A = 0;
    #20 LD_BAR = 1;     


    #100


    ENT = 1; ENP = 1;
    #300


    ENT = 0; ENP = 0;
    #100


    ENT = 1; ENP = 1;
    #300


    #20; CLR_BAR = 1; LD_BAR = 0;
         D = 0; C = 1; B = 0; A = 1;
    #20 LD_BAR = 1;     


    #100

    $display("test complete");
    $finish;
end

endmodule
module jeff_74x161_tb;



reg        CLR_BAR, LD_BAR;
reg        ENT, ENP;
reg        CLK;
reg        A, B, C, D;
wire       QA, QB, QC, QD;
wire       RCO;


jeff_74x161 uut(
    .clr_bar(CLR_BAR), .ld_bar(LD_BAR),
    .ent(ENT), .enp(ENP),
    .clk(CLK),
    .a(A), .b(B), .c(C), .d(D),
    .qa(QA), .qb(QB), .qc(QC), .qd(QD),
    .rco(RCO)
);


initial begin
    $dumpfile("jeff-74x161-tb.vcd");
    $dumpvars(0, jeff_74x161_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLR_BAR = 1; LD_BAR = 1;
    ENT = 0; ENP = 0;
    CLK = 0;
    D = 0; C = 0; B = 0; A = 0;


    #15; CLR_BAR = 0;


    #20; CLR_BAR = 1; LD_BAR = 0;
         D = 1; C = 1; B = 0; A = 0;
    #20 LD_BAR = 1;     


    #100


    ENT = 1; ENP = 1;
    #300


    ENT = 0; ENP = 0;
    #100


    ENT = 1; ENP = 1;
    #300


    #20; CLR_BAR = 1; LD_BAR = 0;
         D = 0; C = 1; B = 0; A = 1;
    #20 LD_BAR = 1;     


    #100

    $display("test complete");
    $finish;
end

endmodule