data/full_repos/permissive/107757225/ps2_kb/Dreg.sv
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/09f24a76-ed84-4545-ae28-4b9f58f350f3.xml
module Dreg ( input Clk, Load, Reset, D,
				  output logic Q );
				  
always @ (posedge Clk or posedge Reset ) 
begin 
	Q = Q;
	if (Reset) 
		Q = 1'b0;
	else if (Load) 
		Q = D;
end

endmodule
module Dreg ( input Clk, Load, Reset, D,
				  output logic Q );

				  
always @ (posedge Clk or posedge Reset ) 
begin 
	Q = Q;
	if (Reset) 
		Q = 1'b0;
	else if (Load) 
		Q = D;
end

endmodule