data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Error: data/full_repos/permissive/172201645/test_benches/tb_skew_channels.v:110: Cannot find file containing module: \'skew_channels\'\nskew_channels  i_skew_channels(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/skew_channels\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/skew_channels.v\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/skew_channels.sv\n             skew_channels\n             skew_channels.v\n             skew_channels.sv\n             obj_dir/skew_channels\n             obj_dir/skew_channels.v\n             obj_dir/skew_channels.sv\n%Error: Exiting due to 1 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_skew_channels;

    reg clk = 1'b1;

    reg  [79:0] in_data;
    wire [79:0] out_data;

initial begin
    
    in_data      = 80'b0;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
   
    forever begin
        #1
        in_data = 80'h44444333332222211111;
        #3
        clk = ~clk;
        #4
        clk = ~clk;
        #1
        in_data = 80'b0;
        #3
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
    end
end

skew_channels  i_skew_channels(
    .clk      (clk),
    .in_data  (in_data),
    .out_data (out_data)
);

endmodule
module tb_skew_channels;


    reg clk = 1'b1;

    reg  [79:0] in_data;
    wire [79:0] out_data;

initial begin
    
    in_data      = 80'b0;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
   
    forever begin
        #1
        in_data = 80'h44444333332222211111;
        #3
        clk = ~clk;
        #4
        clk = ~clk;
        #1
        in_data = 80'b0;
        #3
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
    end
end

skew_channels  i_skew_channels(
    .clk      (clk),
    .in_data  (in_data),
    .out_data (out_data)
);

endmodule