data/full_repos/permissive/167274925/RegisterFile.v
data/verilator_xmls/05619ec5-d94b-439b-81e3-0b67c46eec38.xml
module RegisterFile(ReadRegister1, ReadRegister2, WriteRegister, WriteData, RegWrite, Clk, ReadData1, ReadData2);
input [4:0] ReadRegister1, ReadRegister2, WriteRegister; 
input Clk;
input RegWrite;
input [31:0] WriteData;
output reg [31:0] ReadData1, ReadData2;
reg  [31:0]REG[0:31];
    integer i;
    initial begin 
        for(i=0;i<32;i=i+1)begin 
          REG[i]<=0;
        end 
    end 

    always@(posedge Clk)begin
    if(RegWrite==1)begin 
     REG[WriteRegister]<=WriteData;
     end 
    end 
   
 always@(negedge Clk)begin 
    ReadData1<=REG[ReadRegister1];
    ReadData2<=REG[ReadRegister2];
    end 




endmodule
module RegisterFile(ReadRegister1, ReadRegister2, WriteRegister, WriteData, RegWrite, Clk, ReadData1, ReadData2);

input [4:0] ReadRegister1, ReadRegister2, WriteRegister; 
input Clk;
input RegWrite;
input [31:0] WriteData;
output reg [31:0] ReadData1, ReadData2;
reg  [31:0]REG[0:31];
    integer i;
    initial begin 
        for(i=0;i<32;i=i+1)begin 
          REG[i]<=0;
        end 
    end 

    always@(posedge Clk)begin
    if(RegWrite==1)begin 
     REG[WriteRegister]<=WriteData;
     end 
    end 
   
 always@(negedge Clk)begin 
    ReadData1<=REG[ReadRegister1];
    ReadData2<=REG[ReadRegister2];
    end 




endmodule