data/full_repos/permissive/152883307/Project/Subtractor.v
data/verilator_xmls/eb0a42e7-8afa-4697-94ba-26bda735aaa2.xml
module Subtractor(
	input		[11:0] 	A,
	input		[11:0] 	B,
	input				 	clk,
	output	[12:0] 	Y
);
assign Y=A-B;

endmodule
module Subtractor(
	input		[11:0] 	A,
	input		[11:0] 	B,
	input				 	clk,
	output	[12:0] 	Y
);

assign Y=A-B;

endmodule