data/full_repos/permissive/135820056/sys/video_freezer.sv
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-PINMISSING: data/full_repos/permissive/135820056/sys/video_freezer.sv:39: Cell has missing pin: \'sync_pt\'\nsync_lock #(33) vs_lock\n                ^~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/135820056/sys/video_freezer.sv:39: Cell has missing pin: \'valid\'\nsync_lock #(33) vs_lock\n                ^~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/135820056/sys/video_freezer.sv:50: Cell has missing pin: \'valid\'\nsync_lock #(21) hs_lock\n                ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freezer.sv:128: Operator ADD expects 33 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                             : ... In instance video_freezer.vs_lock\n if(old_sync & ~sync_in & sync_valid) cnto <= s_len + 2\'d2;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/sys/video_freezer.sv:128: Operator ADD expects 21 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                             : ... In instance video_freezer.hs_lock\n if(old_sync & ~sync_in & sync_valid) cnto <= s_len + 2\'d2;\n                                                    ^\n%Error: Exiting due to 5 warning(s)\n'
module video_freezer
(
	input  clk,

	output sync,
	input  freeze,

	input  hs_in,
	input  vs_in,
	input  hbl_in,
	input  vbl_in,

	output hs_out,
	output vs_out,
	output hbl_out,
	output vbl_out
);

sync_lock #(33) vs_lock
(
	.clk(clk),
	.sync_in(vs_in),
	.sync_out(vs_out),
	.de_in(vbl_in),
	.de_out(vbl_out),
	.freeze(freeze)
);

wire sync_pt;
sync_lock #(21) hs_lock
(
	.clk(clk),
	.sync_in(hs_in),
	.sync_out(hs_out),
	.de_in(hbl_in),
	.de_out(hbl_out),
	.freeze(freeze),
	.sync_pt(sync_pt)
);

reg sync_o;
always @(posedge clk) begin
	reg old_hs, old_vs;
	reg vs_sync;

	old_vs <= vs_out;
	
	if(~old_vs & vs_out) vs_sync <= 1;
	if(sync_pt & vs_sync) begin
		vs_sync <= 0;
		sync_o <= ~sync_o;
	end
end

assign sync = sync_o; 

endmodule
module video_freezer
(
	input  clk,

	output sync,
	input  freeze,

	input  hs_in,
	input  vs_in,
	input  hbl_in,
	input  vbl_in,

	output hs_out,
	output vs_out,
	output hbl_out,
	output vbl_out
);


sync_lock #(33) vs_lock
(
	.clk(clk),
	.sync_in(vs_in),
	.sync_out(vs_out),
	.de_in(vbl_in),
	.de_out(vbl_out),
	.freeze(freeze)
);

wire sync_pt;
sync_lock #(21) hs_lock
(
	.clk(clk),
	.sync_in(hs_in),
	.sync_out(hs_out),
	.de_in(hbl_in),
	.de_out(hbl_out),
	.freeze(freeze),
	.sync_pt(sync_pt)
);

reg sync_o;
always @(posedge clk) begin
	reg old_hs, old_vs;
	reg vs_sync;

	old_vs <= vs_out;
	
	if(~old_vs & vs_out) vs_sync <= 1;
	if(sync_pt & vs_sync) begin
		vs_sync <= 0;
		sync_o <= ~sync_o;
	end
end

assign sync = sync_o; 

endmodule