data/full_repos/permissive/10003806/stack_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/stack_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = 0;\n        ^\n%Error: data/full_repos/permissive/10003806/stack_tb.v:36: Cannot find file containing module: \'stack\'\n    stack uut (\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/stack\n             data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/stack.v\n             data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/stack.sv\n             stack\n             stack.v\n             stack.sv\n             obj_dir/stack\n             obj_dir/stack.v\n             obj_dir/stack.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stack_tb;


    reg clk;
    reg rst;
    reg [15:0] pushd;
    reg push_en;
    reg pop_en;


    wire [15:0] top;


    stack uut (
        .top(top),
        .clk(clk),
        .rst(rst),
        .pushd(pushd),
        .push_en(push_en),
        .pop_en(pop_en)
    );

    initial begin

        clk = 0;
        rst = 0;
        pushd = 0;
        push_en = 0;
        pop_en = 0;


        rst = 1;
        clk = 1;
        #10 clk = 0;
        rst = 0;


        pushd = 16'hBEEF;
        push_en = 1;
        #10 clk = 1;
        #10 clk = 0;

        pushd = 16'hDEAD;
        push_en = 1;
        #10 clk = 1;
        #10 clk = 0;


        push_en = 0;
        pop_en = 1;
        #10 clk = 1;
        #10 clk = 0;
        #10 clk = 1;
        #10 clk = 0;
    end
endmodule
module stack_tb;



    reg clk;
    reg rst;
    reg [15:0] pushd;
    reg push_en;
    reg pop_en;


    wire [15:0] top;


    stack uut (
        .top(top),
        .clk(clk),
        .rst(rst),
        .pushd(pushd),
        .push_en(push_en),
        .pop_en(pop_en)
    );

    initial begin

        clk = 0;
        rst = 0;
        pushd = 0;
        push_en = 0;
        pop_en = 0;


        rst = 1;
        clk = 1;
        #10 clk = 0;
        rst = 0;


        pushd = 16'hBEEF;
        push_en = 1;
        #10 clk = 1;
        #10 clk = 0;

        pushd = 16'hDEAD;
        push_en = 1;
        #10 clk = 1;
        #10 clk = 0;


        push_en = 0;
        pop_en = 1;
        #10 clk = 1;
        #10 clk = 0;
        #10 clk = 1;
        #10 clk = 0;
    end
endmodule