data/full_repos/permissive/143278/ivltests/ivlh_event.v
 line:17: before: "$"
1: b'%Error: data/full_repos/permissive/143278/ivltests/ivlh_event.v:6: Unsupported or unknown PLI call: $ivlh_attribute_event\n      if ($ivlh_attribute_event(a))\n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/ivlh_event.v:8: Unsupported or unknown PLI call: $ivlh_attribute_event\n      if ($ivlh_attribute_event(b))\n          ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ivlh_event.v:13: Unsupported: Ignoring delay on this delayed statement.\n      #1 a <= 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ivlh_event.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #1 b <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ivlh_event.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #1 a <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ivlh_event.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #1 b <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ivlh_event.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #1 $finish(0);\n      ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg a, b;

   always @(a or b) begin
      if ($ivlh_attribute_event(a))
	$display("%0t: EVENT on a", $time);
      if ($ivlh_attribute_event(b))
	$display("%0t: EVENT on b", $time);
   end

   initial begin
      #1 a <= 1;
      #1 b <= 1;
      #1 a <= 0;
      #1 b <= 0;
      #1 $finish(0);
   end

endmodule
module main;


   reg a, b;

   always @(a or b) begin
      if ($ivlh_attribute_event(a))
	$display("%0t: EVENT on a", $time);
      if ($ivlh_attribute_event(b))
	$display("%0t: EVENT on b", $time);
   end

   initial begin
      #1 a <= 1;
      #1 b <= 1;
      #1 a <= 0;
      #1 b <= 0;
      #1 $finish(0);
   end

endmodule