data/full_repos/permissive/143278/ivltests/implicit-port7.v
 line:13: before: "*"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/implicit-port7.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #1 if (b !== x || d !== ~x) begin\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/implicit-port7.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #1 a = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/implicit-port7.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #1 if (b !== x || d !== ~x) begin\n   ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module m(input a, output b, output c, output d, output e);
assign b = a;
assign c = ~a;
assign d = ~a;
assign e = ~a;
endmodule
module m(input a, output b, output c, output d, output e);

assign b = a;
assign c = ~a;
assign d = ~a;
assign e = ~a;
endmodule