data/full_repos/permissive/143278/ivltests/full_case2.v
 line:10: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/full_case2.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (out !== 2\'b10) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/full_case2.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (out !== 2\'b00) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/full_case2.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (out !== 2\'b01) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/full_case2.v:12: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance main\n       2\'b10: out = in[0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/full_case2.v:13: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance main\n       2\'b11: out = in[1];\n                  ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [1:0] sel, in;
   reg [1:0] out;

   (* ivl_combinational *)
   always @* begin
     (* ivl_full_case *) case (sel)
       2'b01: out = 2'b10;
       2'b10: out = in[0];
       2'b11: out = in[1];
     endcase
   end
   (* ivl_synthesis_off *)
   initial begin
      in = 2'b10;

      sel = 1;
      #1 if (out !== 2'b10) begin
	 $display("FAILED -- sel=%b, out=%b", sel, out);
	 $finish;
      end

      sel = 2;
      #1 if (out !== 2'b00) begin
	 $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
	 $finish;
      end

      sel = 3;
      #1 if (out !== 2'b01) begin
	 $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;


   reg [1:0] sel, in;
   reg [1:0] out;

   (* ivl_combinational *)
   always @* begin
     (* ivl_full_case *) case (sel)
       2'b01: out = 2'b10;
       2'b10: out = in[0];
       2'b11: out = in[1];
     endcase
   end
   (* ivl_synthesis_off *)
   initial begin
      in = 2'b10;

      sel = 1;
      #1 if (out !== 2'b10) begin
	 $display("FAILED -- sel=%b, out=%b", sel, out);
	 $finish;
      end

      sel = 2;
      #1 if (out !== 2'b00) begin
	 $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
	 $finish;
      end

      sel = 3;
      #1 if (out !== 2'b01) begin
	 $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
	 $finish;
      end

      $display("PASSED");
   end
endmodule