data/full_repos/permissive/143278/ivltests/time1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/time1.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #5 d = c;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/time1.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/time1.v:52: Unsupported: Ignoring delay on this delayed statement.\n    # 3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/time1.v:54: Unsupported: Ignoring delay on this delayed statement.\n    # 10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/time1.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ();

reg a;
reg error;
wire c;
reg d;

assign c = a;
always @(c)
  #5 d = c;



always @(posedge d)
     error <= 1'b1;

initial
  begin

    a =1'b0;
    error = 1'b0;
    #10;

    a = 1'b1;
    # 3;
    a = 1'b0;
    # 10;

    if(error)
       $display("FAILED");
    else
       $display("PASSED");
    #5;
    $finish ;
  end


endmodule
module main ();


reg a;
reg error;
wire c;
reg d;

assign c = a;
always @(c)
  #5 d = c;



always @(posedge d)
     error <= 1'b1;

initial
  begin

    a =1'b0;
    error = 1'b0;
    #10;

    a = 1'b1;
    # 3;
    a = 1'b0;
    # 10;

    if(error)
       $display("FAILED");
    else
       $display("PASSED");
    #5;
    $finish ;
  end


endmodule