data/full_repos/permissive/117088385/rtl/e203/general/sirv_gnrl_ram.v
1: b"%Error: data/full_repos/permissive/117088385/rtl/e203/general/sirv_gnrl_ram.v:72: Cannot find file containing module: 'sirv_sim_ram'\nsirv_sim_ram #(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117088385/rtl/e203/general,data/full_repos/permissive/117088385/sirv_sim_ram\n             data/full_repos/permissive/117088385/rtl/e203/general,data/full_repos/permissive/117088385/sirv_sim_ram.v\n             data/full_repos/permissive/117088385/rtl/e203/general,data/full_repos/permissive/117088385/sirv_sim_ram.sv\n             sirv_sim_ram\n             sirv_sim_ram.v\n             sirv_sim_ram.sv\n             obj_dir/sirv_sim_ram\n             obj_dir/sirv_sim_ram.v\n             obj_dir/sirv_sim_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module sirv_gnrl_ram 
#(parameter DP = 32,
  parameter DW = 256,
  parameter AW = 5 
  ) (
  input            sd,
  input            ds,
  input            ls,

  input            clk,
  input            cs,
  input            we,
  input [AW-1:0]   addr,
  input [DW-1:0]   din,
  input [DW/8-1:0] wem,
  output[DW-1:0]   dout
);




`ifdef FPGA_SOURCE
sirv_sim_ram #(
    .DP (DP),
    .AW (AW),
    .DW (DW) 
)u_sirv_sim_ram (
    .clk   (clk),
    .din   (din),
    .addr  (addr),
    .cs    (cs),
    .we    (we),
    .wem   (wem),
    .dout  (dout)
);
`else

sirv_sim_ram #(
    .DP (DP),
    .AW (AW),
    .DW (DW) 
)u_sirv_sim_ram (
    .clk   (clk),
    .din   (din),
    .addr  (addr),
    .cs    (cs),
    .we    (we),
    .wem   (wem),
    .dout  (dout)
);
`endif

endmodule
module sirv_gnrl_ram 
#(parameter DP = 32,
  parameter DW = 256,
  parameter AW = 5 
  ) (
  input            sd,
  input            ds,
  input            ls,

  input            clk,
  input            cs,
  input            we,
  input [AW-1:0]   addr,
  input [DW-1:0]   din,
  input [DW/8-1:0] wem,
  output[DW-1:0]   dout
);





`ifdef FPGA_SOURCE
sirv_sim_ram #(
    .DP (DP),
    .AW (AW),
    .DW (DW) 
)u_sirv_sim_ram (
    .clk   (clk),
    .din   (din),
    .addr  (addr),
    .cs    (cs),
    .we    (we),
    .wem   (wem),
    .dout  (dout)
);
`else

sirv_sim_ram #(
    .DP (DP),
    .AW (AW),
    .DW (DW) 
)u_sirv_sim_ram (
    .clk   (clk),
    .din   (din),
    .addr  (addr),
    .cs    (cs),
    .we    (we),
    .wem   (wem),
    .dout  (dout)
);
`endif

endmodule