data/full_repos/permissive/163115503/lightswitch/top.v
data/verilator_xmls/1fef247a-85a9-41d6-aa09-701d17dd25a2.xml
module top (
	input CLK,
	input PIN_1,
	output LED,
	output USBPU
);


    assign USBPU = 0;


    reg led_state;


    always @(posedge CLK) begin
        if (PIN_1) begin
            led_state <= 1;
        end else begin
            led_state <= 0;
        end
    end


    assign LED = led_state;

endmodule
module top (
	input CLK,
	input PIN_1,
	output LED,
	output USBPU
);



    assign USBPU = 0;


    reg led_state;


    always @(posedge CLK) begin
        if (PIN_1) begin
            led_state <= 1;
        end else begin
            led_state <= 0;
        end
    end


    assign LED = led_state;

endmodule