data/full_repos/permissive/163728837/src/sprite.v
 line:381: before: "signed"
1: b'%Error: data/full_repos/permissive/163728837/src/sprite.v:46: Cannot find file containing module: \'simple_dual_ram\'\nsimple_dual_ram #(.SIZE(40), .DEPTH(SPRITE_COUNT)) smeta_ram (\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/163728837/src,data/full_repos/permissive/163728837/simple_dual_ram\n             data/full_repos/permissive/163728837/src,data/full_repos/permissive/163728837/simple_dual_ram.v\n             data/full_repos/permissive/163728837/src,data/full_repos/permissive/163728837/simple_dual_ram.sv\n             simple_dual_ram\n             simple_dual_ram.v\n             simple_dual_ram.sv\n             obj_dir/simple_dual_ram\n             obj_dir/simple_dual_ram.v\n             obj_dir/simple_dual_ram.sv\n%Error: data/full_repos/permissive/163728837/src/sprite.v:63: Cannot find file containing module: \'simple_dual_ram\'\nsimple_dual_ram #(.SIZE(120), .DEPTH(SPRITE_COUNT)) stmeta_ram (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/163728837/src/sprite.v:77: Cannot find file containing module: \'idist_rom\'\nidist_rom idist_rom (\n^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/sprite.v:185: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'map_pos_x\' generates 16 bits.\n                                                                     : ... In instance sprite\n                map_posx_d = map_pos_x <<< 8;\n                                       ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/sprite.v:186: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'map_pos_y\' generates 16 bits.\n                                                                     : ... In instance sprite\n                map_posy_d = map_pos_y <<< 8;\n                                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/sprite.v:209: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                     : ... In instance sprite\n            spritex_d = (smeta_read_data[31:16] << 8) - map_posx_q;\n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/sprite.v:210: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                     : ... In instance sprite\n            spritey_d = (smeta_read_data[15:0] << 8) - map_posy_q;\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/sprite.v:280: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 12 bits.\n                                                                     : ... In instance sprite\n            idist_addr = mul_res_q[21:10];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/sprite.v:285: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'idist\' generates 16 bits.\n                                                                     : ... In instance sprite\n            mul_arg2_d = idist << 8;  \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/sprite.v:299: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 32 bits.\n                                                                     : ... In instance sprite\n            sprite_screenx_d = mul_res_q >>> 16;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/sprite.v:311: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                     : ... In instance sprite\n                sprite_height_d = (~mul_res_q) + 1\'b1 >> 16;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/sprite.v:313: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                     : ... In instance sprite\n                sprite_height_d = mul_res_q >> 16;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/sprite.v:332: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'count_q\' generates 7 bits.\n                                                                     : ... In instance sprite\n            if (count_q == SPRITE_COUNT-1) begin\n                        ^~\n%Error: Exiting due to 3 error(s), 10 warning(s)\n'
function signed [31:0] trunc_fixed_mul(input signed [63:0] mulres);
  trunc_fixed_mul = mulres[47:16];
endfunction
function signed [31:0] trunc_fixed_mul(input signed [63:0] mulres);

  trunc_fixed_mul = mulres[47:16];
endfunction