data/full_repos/permissive/20759093/test_rom_a.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/20759093/test_rom_a.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_rom_a.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr <= addr + 1;\n  ^\n%Error: data/full_repos/permissive/20759093/test_rom_a.v:34: Cannot find file containing module: \'ROM_A\'\n ROM_A uut (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/ROM_A\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/ROM_A.v\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/ROM_A.sv\n             ROM_A\n             ROM_A.v\n             ROM_A.sv\n             obj_dir/ROM_A\n             obj_dir/ROM_A.v\n             obj_dir/ROM_A.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_rom_a;


	reg [31:0] addr;


	wire [31:0] inst;


	ROM_A uut (
		.addr(addr), 
		.inst(inst)
	);

	initial begin

		addr = 0;


		#100;
      

		
	end
	
	always @* begin
		#10 addr <= addr + 1;
	end
      
endmodule
module test_rom_a;



	reg [31:0] addr;


	wire [31:0] inst;


	ROM_A uut (
		.addr(addr), 
		.inst(inst)
	);

	initial begin

		addr = 0;


		#100;
      

		
	end
	
	always @* begin
		#10 addr <= addr + 1;
	end
      
endmodule