data/full_repos/permissive/201488448/2_circuits/1_combinational/21_mux256.v
data/verilator_xmls/ce2e95d4-ab76-474e-8385-7daa276bdd70.xml
module top_module (
	input [255:0] in,
	input [7:0] sel,
	output  out
);


	assign out = in[sel];
	
endmodule
module top_module (
	input [255:0] in,
	input [7:0] sel,
	output  out
);



	assign out = in[sel];
	
endmodule