data/full_repos/permissive/163115503/somesound/top.v
data/verilator_xmls/db7df1dd-a119-4048-97d6-e5033ceb776a.xml
module top(
    input CLK,
    input PIN_2,
    output PIN_1
);
    
    reg [23:0] count;
    reg [23:0] freq = 440;
    reg pin_state;


    always @(posedge CLK) begin
        count <= count + 1;

        if (PIN_2) begin
            freq <= ((freq + 1) % 16000);
        end

        if (count == (16000000/freq)) begin
            count <= 0;
            pin_state = !pin_state;
        end
    end

    assign PIN_1 = pin_state;
endmodule
module top(
    input CLK,
    input PIN_2,
    output PIN_1
);

    
    reg [23:0] count;
    reg [23:0] freq = 440;
    reg pin_state;


    always @(posedge CLK) begin
        count <= count + 1;

        if (PIN_2) begin
            freq <= ((freq + 1) % 16000);
        end

        if (count == (16000000/freq)) begin
            count <= 0;
            pin_state = !pin_state;
        end
    end

    assign PIN_1 = pin_state;
endmodule