data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons.v:21: Multiple top level modules\n                                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                            : ... Top module \'button_sync_push_release\'\nmodule button_sync_push_release (\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                            : ... Top module \'button_sync_clock_pulse\'\nmodule button_sync_clock_pulse (\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                            : ... Top module \'button_sync_two_presses\'\nmodule button_sync_two_presses (\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                            : ... Top module \'button_async_clock_pulse\'\nmodule button_async_clock_pulse (\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                            : ... Top module \'button_async_two_presses\'\nmodule button_async_two_presses (\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module button_sync_two_presses (
    input           clk,
    input           pressed,
    output          out
);

reg lock = 0;
reg toggle = 0;

assign out = toggle;

always @ (posedge clk) begin
    if (pressed & ~lock) begin
        lock <= 1'b1;
        toggle <= ~toggle;
    end else if (~pressed & lock) begin
        lock <= 1'b0;
    end
end

endmodule
module button_sync_two_presses (
    input           clk,
    input           pressed,
    output          out
);


reg lock = 0;
reg toggle = 0;

assign out = toggle;

always @ (posedge clk) begin
    if (pressed & ~lock) begin
        lock <= 1'b1;
        toggle <= ~toggle;
    end else if (~pressed & lock) begin
        lock <= 1'b0;
    end
end

endmodule