data/full_repos/permissive/113839829/Source/CPU/if_id.v
'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte
1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:5: Cannot find include file: defines.v\n `include "defines.v" \n          ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:14: Define or directive not defined: \'`InstAddrBus\'\n   input wire [`InstAddrBus] if_pc,\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   input wire [`InstAddrBus] if_pc,\n                           ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:15: Define or directive not defined: \'`InstBus\'\n   input wire [`InstBus]     if_inst,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n   input wire       which_pdt_i,\n   ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n   input wire [9:0]       history_i,\n   ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n   output reg [`InstAddrBus] id_pc,\n   ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:21: Define or directive not defined: \'`InstAddrBus\'\n   output reg [`InstAddrBus] id_pc,\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:22: Define or directive not defined: \'`InstBus\'\n   output reg [`InstBus]     id_inst,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n   output reg        which_pdt_o,\n   ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n   output reg [9:0]       history_o\n   ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:27: syntax error, unexpected \')\', expecting \',\' or \';\'\n   );\n   ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:32: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) \n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:34: Define or directive not defined: \'`ZeroWord\'\n      id_pc <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:35: Define or directive not defined: \'`ZeroWord\'\n      id_inst <= `ZeroWord;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:42: Define or directive not defined: \'`ZeroWord\'\n      id_pc <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:43: Define or directive not defined: \'`ZeroWord\'\n      id_inst <= `ZeroWord;\n                 ^~~~~~~~~\n%Error: Exiting due to 17 error(s)\n'
module if_id
  (
   input wire 		     clk,
   input wire 		     rst,

   input wire [5:0] 	     stall,

   input wire [`InstAddrBus] if_pc,
   input wire [`InstBus]     if_inst,

   input wire 		     pdt_res_i,
   input wire		     which_pdt_i,
   input wire [9:0] 	     history_i,
   
   output reg [`InstAddrBus] id_pc,
   output reg [`InstBus]     id_inst,

   output reg 		     pdt_res_o,
   output reg 		     which_pdt_o,
   output reg [9:0] 	     history_o
   );

   always @ (posedge clk)
     begin

	if (rst == `RstEnable) 
	  begin
	     id_pc <= `ZeroWord;
	     id_inst <= `ZeroWord;
	     pdt_res_o <= 0;
	     which_pdt_o <= 0;
	     history_o <= 10'b0;
	  end
	else if (stall[1] == 1'b1&&stall[2] == 1'b0)
	  begin
	     id_pc <= `ZeroWord;
	     id_inst <= `ZeroWord;
	     pdt_res_o <= 0;
	     which_pdt_o <= 0;
	     history_o <= 10'b0;
	  end
	else if (stall[1] == 1'b0)
	  begin
	     id_pc <= if_pc;
	     id_inst <= if_inst;
	     pdt_res_o <= pdt_res_i;
	     which_pdt_o <= which_pdt_i;
	     history_o <= history_i;
	  end
	
     end

endmodule
module if_id
  (
   input wire 		     clk,
   input wire 		     rst,

   input wire [5:0] 	     stall,

   input wire [`InstAddrBus] if_pc,
   input wire [`InstBus]     if_inst,

   input wire 		     pdt_res_i,
   input wire		     which_pdt_i,
   input wire [9:0] 	     history_i,
   
   output reg [`InstAddrBus] id_pc,
   output reg [`InstBus]     id_inst,

   output reg 		     pdt_res_o,
   output reg 		     which_pdt_o,
   output reg [9:0] 	     history_o
   );


   always @ (posedge clk)
     begin

	if (rst == `RstEnable) 
	  begin
	     id_pc <= `ZeroWord;
	     id_inst <= `ZeroWord;
	     pdt_res_o <= 0;
	     which_pdt_o <= 0;
	     history_o <= 10'b0;
	  end
	else if (stall[1] == 1'b1&&stall[2] == 1'b0)
	  begin
	     id_pc <= `ZeroWord;
	     id_inst <= `ZeroWord;
	     pdt_res_o <= 0;
	     which_pdt_o <= 0;
	     history_o <= 10'b0;
	  end
	else if (stall[1] == 1'b0)
	  begin
	     id_pc <= if_pc;
	     id_inst <= if_inst;
	     pdt_res_o <= pdt_res_i;
	     which_pdt_o <= which_pdt_i;
	     history_o <= history_i;
	  end
	
     end

endmodule