data/full_repos/permissive/120518070/main/source/temp.sv
data/verilator_xmls/8ba0e6b6-306b-418d-be96-8f0481fed24e.xml
module temp(
	input wire clk,
	input wire [7:0] rdata_i,
	input wire store_temp_i,
	output reg [7:0] temp_o
);



always_ff @(posedge clk)
begin
	if (store_temp_i == 1)
	begin
		temp_o <= rdata_i;
	end
	else
	begin
		temp_o <= temp_o;
	end
end
endmodule
module temp(
	input wire clk,
	input wire [7:0] rdata_i,
	input wire store_temp_i,
	output reg [7:0] temp_o
);




always_ff @(posedge clk)
begin
	if (store_temp_i == 1)
	begin
		temp_o <= rdata_i;
	end
	else
	begin
		temp_o <= temp_o;
	end
end
endmodule