data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_DAC.v
1: b'%Warning-WIDTH: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_DAC.v:99: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_WIDTH\' generates 32 or 6 bits.\n                                                                                                                      : ... In instance AUDIO_DAC\n    bit_index = DATA_WIDTH;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_DAC.v:109: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'bit_index\' generates 5 bits.\n                                                                                                                       : ... In instance AUDIO_DAC\n   if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))\n                                      ^~\n%Error: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_DAC.v:128: Cannot find file containing module: \'audio_fifo\'\naudio_fifo dac_fifo(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo\n             data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo.v\n             data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo.sv\n             audio_fifo\n             audio_fifo.v\n             audio_fifo.sv\n             obj_dir/audio_fifo\n             obj_dir/audio_fifo.v\n             obj_dir/audio_fifo.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module AUDIO_DAC(

	clk,
	reset,
	write,
	writedata,
	full,
	clear,

	bclk,
	daclrc,
	dacdat
);


parameter	DATA_WIDTH = 32;


input						clk;
input						reset;
input						write;
input	[(DATA_WIDTH-1):0]	writedata;
output						full;
input						clear;

input						bclk;
input						daclrc;
output						dacdat;








reg							request_bit;
reg							bit_to_dac;
reg		[4:0]				bit_index;
reg							dac_is_left;
reg		[(DATA_WIDTH-1):0]	data_to_dac;		
reg		[(DATA_WIDTH-1):0]	shift_data_to_dac;	


wire						dacfifo_empty;
wire 						dacfifo_read;
wire	[(DATA_WIDTH-1):0]	dacfifo_readdata;
wire						is_left_ch;








assign dacfifo_read = (dacfifo_empty)?1'b0:1'b1;

always @ (negedge is_left_ch)
begin
	if (dacfifo_empty)
		data_to_dac = 0;
	else
		data_to_dac = dacfifo_readdata;
end


assign is_left_ch = ~daclrc;
always @ (negedge bclk) 
begin
	if (reset || clear)
	begin
		request_bit = 0;
		bit_index = 0;
		dac_is_left = is_left_ch;
		bit_to_dac = 1'b0;
	end
	else
	begin
		if (dac_is_left ^ is_left_ch)
		begin
			dac_is_left = is_left_ch;
			request_bit = 1; 
			if (dac_is_left)
			begin
				shift_data_to_dac = data_to_dac;
				bit_index = DATA_WIDTH;
			end
		end
		
		

		if (request_bit)
		begin
			bit_index = bit_index - 1'b1;
			bit_to_dac = shift_data_to_dac[bit_index];
			if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
				request_bit = 0;
		end			
		else
			bit_to_dac = 1'b0;
	end
end




assign	dacdat = bit_to_dac;



audio_fifo dac_fifo(

	.wrclk(clk),
	.wrreq(write),
	.data(writedata),
	.wrfull(full),
	.aclr(clear),


	.rdclk(is_left_ch),
	.rdreq(dacfifo_read),
	.q(dacfifo_readdata),
	.rdempty(dacfifo_empty)
);

endmodule
module AUDIO_DAC(

	clk,
	reset,
	write,
	writedata,
	full,
	clear,

	bclk,
	daclrc,
	dacdat
);



parameter	DATA_WIDTH = 32;


input						clk;
input						reset;
input						write;
input	[(DATA_WIDTH-1):0]	writedata;
output						full;
input						clear;

input						bclk;
input						daclrc;
output						dacdat;








reg							request_bit;
reg							bit_to_dac;
reg		[4:0]				bit_index;
reg							dac_is_left;
reg		[(DATA_WIDTH-1):0]	data_to_dac;		
reg		[(DATA_WIDTH-1):0]	shift_data_to_dac;	


wire						dacfifo_empty;
wire 						dacfifo_read;
wire	[(DATA_WIDTH-1):0]	dacfifo_readdata;
wire						is_left_ch;








assign dacfifo_read = (dacfifo_empty)?1'b0:1'b1;

always @ (negedge is_left_ch)
begin
	if (dacfifo_empty)
		data_to_dac = 0;
	else
		data_to_dac = dacfifo_readdata;
end


assign is_left_ch = ~daclrc;
always @ (negedge bclk) 
begin
	if (reset || clear)
	begin
		request_bit = 0;
		bit_index = 0;
		dac_is_left = is_left_ch;
		bit_to_dac = 1'b0;
	end
	else
	begin
		if (dac_is_left ^ is_left_ch)
		begin
			dac_is_left = is_left_ch;
			request_bit = 1; 
			if (dac_is_left)
			begin
				shift_data_to_dac = data_to_dac;
				bit_index = DATA_WIDTH;
			end
		end
		
		

		if (request_bit)
		begin
			bit_index = bit_index - 1'b1;
			bit_to_dac = shift_data_to_dac[bit_index];
			if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
				request_bit = 0;
		end			
		else
			bit_to_dac = 1'b0;
	end
end




assign	dacdat = bit_to_dac;



audio_fifo dac_fifo(

	.wrclk(clk),
	.wrreq(write),
	.data(writedata),
	.wrfull(full),
	.aclr(clear),


	.rdclk(is_left_ch),
	.rdreq(dacfifo_read),
	.q(dacfifo_readdata),
	.rdempty(dacfifo_empty)
);

endmodule