data/full_repos/permissive/188068190/ridecore-src-buggy/imem_outa.v
data/verilator_xmls/6f07cdbe-f47f-4679-9135-ae9081c2e18b.xml
module imem_outa
  (
   input [27:0]       pc,
   output reg [127:0] idata
   );

   always @ (*) begin
      case(pc)
	28'h0: idata = 128'h00202023001081130010202304100093;
	28'h1: idata = 128'h0000000000000000ffdff06f00202423;
	default: idata = 128'h0;
      endcase
   end
endmodule
module imem_outa
  (
   input [27:0]       pc,
   output reg [127:0] idata
   );


   always @ (*) begin
      case(pc)
	28'h0: idata = 128'h00202023001081130010202304100093;
	28'h1: idata = 128'h0000000000000000ffdff06f00202423;
	default: idata = 128'h0;
      endcase
   end
endmodule