data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips/mips_top.v
1: b"%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips/mips_top.v:16: Cannot find file containing module: 'mips'\n    mips mips (\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips,data/full_repos/permissive/168234415/mips\n             data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips,data/full_repos/permissive/168234415/mips.v\n             data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips,data/full_repos/permissive/168234415/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips/mips_top.v:29: Cannot find file containing module: 'imem'\n    imem imem (\n    ^~~~\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips/mips_top.v:34: Cannot find file containing module: 'dmem'\n    dmem dmem (\n    ^~~~\n%Error: Exiting due to 3 error(s)\n"
module mips_top (
        input  wire        clk,
        input  wire        rst,
        input  wire [4:0]  ra3,
        output wire        we_dm,
        output wire [31:0] pc_current,
        output wire [31:0] instr,
        output wire [31:0] alu_out,
        output wire [31:0] wd_dm,
        output wire [31:0] rd_dm,
        output wire [31:0] rd3
    );

    wire [31:0] DONT_USE;

    mips mips (
            .clk            (clk),
            .rst            (rst),
            .ra3            (ra3),
            .instr          (instr),
            .rd_dm          (rd_dm),
            .we_dm          (we_dm),
            .pc_current     (pc_current),
            .alu_out        (alu_out),
            .wd_dm          (wd_dm),
            .rd3            (rd3)
        );

    imem imem (
            .a              (pc_current[7:2]),
            .y              (instr)
        );

    dmem dmem (
            .clk            (clk),
            .we             (we_dm),
            .a              (alu_out[7:2]),
            .d              (wd_dm),
            .q              (rd_dm)
        );

endmodule
module mips_top (
        input  wire        clk,
        input  wire        rst,
        input  wire [4:0]  ra3,
        output wire        we_dm,
        output wire [31:0] pc_current,
        output wire [31:0] instr,
        output wire [31:0] alu_out,
        output wire [31:0] wd_dm,
        output wire [31:0] rd_dm,
        output wire [31:0] rd3
    );


    wire [31:0] DONT_USE;

    mips mips (
            .clk            (clk),
            .rst            (rst),
            .ra3            (ra3),
            .instr          (instr),
            .rd_dm          (rd_dm),
            .we_dm          (we_dm),
            .pc_current     (pc_current),
            .alu_out        (alu_out),
            .wd_dm          (wd_dm),
            .rd3            (rd3)
        );

    imem imem (
            .a              (pc_current[7:2]),
            .y              (instr)
        );

    dmem dmem (
            .clk            (clk),
            .we             (we_dm),
            .a              (alu_out[7:2]),
            .d              (wd_dm),
            .q              (rd_dm)
        );

endmodule