data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:2: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/timescale.v\n             data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/timescale.v.v\n             data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog,data/full_repos/permissive/109400221/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:3: Cannot find include file: sd_defines.v\n`include "sd_defines.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:18: Define or directive not defined: \'`FIFO_TX_MEM_DEPTH\'\n   reg [32-1:0] ram [0:`FIFO_TX_MEM_DEPTH-1];  \n                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:19: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n   reg [`FIFO_TX_MEM_ADR_SIZE-1:0] adr_i, adr_o;\n        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:30: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n       ram[adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0]] <= ram_din;\n                 ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:34: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n       adr_i <= `FIFO_TX_MEM_ADR_SIZE\'h0;\n                ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:37: Define or directive not defined: \'`FIFO_TX_MEM_DEPTH\'\n        if (adr_i == `FIFO_TX_MEM_DEPTH-1) begin\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:38: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n         adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;    \n               ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:39: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n         adr_i[`FIFO_TX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_TX_MEM_ADR_SIZE-1];\n               ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:39: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n         adr_i[`FIFO_TX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_TX_MEM_ADR_SIZE-1];\n                                                ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:42: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n       adr_i <= adr_i + `FIFO_TX_MEM_ADR_SIZE\'h1;\n                        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:47: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n       adr_o <= `FIFO_TX_MEM_ADR_SIZE\'h0;\n                ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:51: Define or directive not defined: \'`FIFO_TX_MEM_DEPTH\'\n  if (adr_o == `FIFO_TX_MEM_DEPTH-1) begin\n               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:52: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n     adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;\n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:53: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n     adr_o[`FIFO_TX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_TX_MEM_ADR_SIZE-1];\n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:53: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n     adr_o[`FIFO_TX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_TX_MEM_ADR_SIZE-1];\n                                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:56: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n    adr_o <= adr_o + `FIFO_TX_MEM_ADR_SIZE\'h1;\n                     ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:66: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n   assign full=  ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) &  (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;\n                         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:66: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n   assign full=  ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) &  (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;\n                                                             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:66: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n   assign full=  ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) &  (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;\n                                                                                                    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:66: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n   assign full=  ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) &  (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;\n                                                                                                                                     ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109400221/originals/OpenCoresSDCard/rtl/sdc_dma/verilog/sd_tx_fifo.v:70: Define or directive not defined: \'`FIFO_TX_MEM_ADR_SIZE\'\n   assign q = ram[adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0]];\n                        ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module sd_tx_fifo
  (
   input [32-1:0] d,
   input wr,
   input wclk,
   output [32-1:0] q,
   input rd,
   output full,
   output empty,
   output [5:0] mem_empt,
   input rclk,
   input rst
   );
   
   reg [32-1:0] ram [0:`FIFO_TX_MEM_DEPTH-1];
   reg [`FIFO_TX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
   wire ram_we;
   wire [32-1:0] ram_din;
    

       
   assign ram_we = wr & ~full;
   assign ram_din = d;
   
   always @ (posedge wclk)
     if (ram_we)
       ram[adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0]] <= ram_din;
   
   always @ (posedge wclk or posedge rst)
     if (rst)
       adr_i <= `FIFO_TX_MEM_ADR_SIZE'h0;
     else
       if (ram_we)
      	 if (adr_i == `FIFO_TX_MEM_DEPTH-1) begin
	        adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;	   
	        adr_i[`FIFO_TX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_TX_MEM_ADR_SIZE-1];
	    end  
	     else
	      adr_i <= adr_i + `FIFO_TX_MEM_ADR_SIZE'h1;
	   
	   
   always @ (posedge rclk or posedge rst)
     if (rst)
       adr_o <= `FIFO_TX_MEM_ADR_SIZE'h0;
     else
       if (!empty & rd) begin
	
	 if (adr_o == `FIFO_TX_MEM_DEPTH-1) begin
	    adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
	    adr_o[`FIFO_TX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_TX_MEM_ADR_SIZE-1];
	 end  
	 else
	   adr_o <= adr_o + `FIFO_TX_MEM_ADR_SIZE'h1;
	 end






	   
	   
   assign full=  ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) &  (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;
   assign empty = (adr_i == adr_o) ;
   
   assign mem_empt = ( adr_i-adr_o);
   assign q = ram[adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0]];
endmodule
module sd_tx_fifo
  (
   input [32-1:0] d,
   input wr,
   input wclk,
   output [32-1:0] q,
   input rd,
   output full,
   output empty,
   output [5:0] mem_empt,
   input rclk,
   input rst
   );

   
   reg [32-1:0] ram [0:`FIFO_TX_MEM_DEPTH-1];
   reg [`FIFO_TX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
   wire ram_we;
   wire [32-1:0] ram_din;
    

       
   assign ram_we = wr & ~full;
   assign ram_din = d;
   
   always @ (posedge wclk)
     if (ram_we)
       ram[adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0]] <= ram_din;
   
   always @ (posedge wclk or posedge rst)
     if (rst)
       adr_i <= `FIFO_TX_MEM_ADR_SIZE'h0;
     else
       if (ram_we)
      	 if (adr_i == `FIFO_TX_MEM_DEPTH-1) begin
	        adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;	   
	        adr_i[`FIFO_TX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_TX_MEM_ADR_SIZE-1];
	    end  
	     else
	      adr_i <= adr_i + `FIFO_TX_MEM_ADR_SIZE'h1;
	   
	   
   always @ (posedge rclk or posedge rst)
     if (rst)
       adr_o <= `FIFO_TX_MEM_ADR_SIZE'h0;
     else
       if (!empty & rd) begin
	
	 if (adr_o == `FIFO_TX_MEM_DEPTH-1) begin
	    adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
	    adr_o[`FIFO_TX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_TX_MEM_ADR_SIZE-1];
	 end  
	 else
	   adr_o <= adr_o + `FIFO_TX_MEM_ADR_SIZE'h1;
	 end






	   
	   
   assign full=  ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) &  (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;
   assign empty = (adr_i == adr_o) ;
   
   assign mem_empt = ( adr_i-adr_o);
   assign q = ram[adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0]];
endmodule