data/full_repos/permissive/132220215/Bidirect_shiftReg.v
 line:25: before: "clr"
1: b'%Error: data/full_repos/permissive/132220215/Bidirect_shiftReg.v:4: Cannot find include file: mux2.v\n`include "mux2.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/mux2.v\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/mux2.v.v\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/mux2.v.sv\n             mux2.v\n             mux2.v.v\n             mux2.v.sv\n             obj_dir/mux2.v\n             obj_dir/mux2.v.v\n             obj_dir/mux2.v.sv\n%Error: data/full_repos/permissive/132220215/Bidirect_shiftReg.v:5: Cannot find include file: d_ff_asyn_clr.v\n`include "d_ff_asyn_clr.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module Bi_Shift_Reg #(parameter N = 8) (
	 input L_R,
	 input Din_L,
	 input Din_R,
	 input clk,
	 input asyn_clr,
	 output Dout_L,
	 output Dout_R);
 
  wire [N:-1] wr;
  wire [N-1:0] mux_out;



  assign wr[-1] = Din_R;
  assign Dout_R =wr[N];
  assign wr[N] = Din_L;
  assign Dout_L = wr[-1];

  genvar i;




  generate
	 for(i=0;i<N;i=i+1)
		 mux2to1 DIR(.sel(L_R),.in({wr[i-1],wr[i+1]}),.f(mux_out[i]));
  endgenerate


  genvar j;
  generate 
	  for(j=0;j<N;j=j+1)
		  D_FF DFF(.clr(asyn_clr),.clk(clk),.D(mux_out[j]),.Q(wr[j]));

  endgenerate


endmodule
module Bi_Shift_Reg #(parameter N = 8) (
	 input L_R,
	 input Din_L,
	 input Din_R,
	 input clk,
	 input asyn_clr,
	 output Dout_L,
	 output Dout_R);

 
  wire [N:-1] wr;
  wire [N-1:0] mux_out;



  assign wr[-1] = Din_R;
  assign Dout_R =wr[N];
  assign wr[N] = Din_L;
  assign Dout_L = wr[-1];

  genvar i;




  generate
	 for(i=0;i<N;i=i+1)
		 mux2to1 DIR(.sel(L_R),.in({wr[i-1],wr[i+1]}),.f(mux_out[i]));
  endgenerate


  genvar j;
  generate 
	  for(j=0;j<N;j=j+1)
		  D_FF DFF(.clr(asyn_clr),.clk(clk),.D(mux_out[j]),.Q(wr[j]));

  endgenerate


endmodule