data/full_repos/permissive/179227721/led_counter/led_counter.v
1: b"%Error: data/full_repos/permissive/179227721/led_counter/led_counter.v:24: Cannot find file containing module: 'counter'\n   counter counter1 (clkdiv[CLKDIV], rst, led);\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179227721/led_counter,data/full_repos/permissive/179227721/counter\n             data/full_repos/permissive/179227721/led_counter,data/full_repos/permissive/179227721/counter.v\n             data/full_repos/permissive/179227721/led_counter,data/full_repos/permissive/179227721/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: Exiting due to 1 error(s)\n"
module top (
	input  clk,
  input  rst,
	output LED0,
	output LED1,
	output LED2,
	output LED3,
	output LED4,
	output LED5,
	output LED6,
	output LED7
);

   localparam CLKDIV = 21;

   reg [CLKDIV:0] clkdiv;
   wire [7:0]     led;

   always@(posedge clk)
     begin
        clkdiv <= clkdiv + 1;
     end

   counter counter1 (clkdiv[CLKDIV], rst, led);

   assign {LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7} = led;
endmodule
module top (
	input  clk,
  input  rst,
	output LED0,
	output LED1,
	output LED2,
	output LED3,
	output LED4,
	output LED5,
	output LED6,
	output LED7
);


   localparam CLKDIV = 21;

   reg [CLKDIV:0] clkdiv;
   wire [7:0]     led;

   always@(posedge clk)
     begin
        clkdiv <= clkdiv + 1;
     end

   counter counter1 (clkdiv[CLKDIV], rst, led);

   assign {LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7} = led;
endmodule