data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v
 line:118: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:210: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:225: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:230: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:240: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:245: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:250: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:255: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:260: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:265: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:270: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:275: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:280: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:285: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:290: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:295: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:299: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/decode_tb.v:41: Cannot find file containing module: \'decode\'\ndecode #(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/decode\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/decode.v\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/decode.sv\n             decode\n             decode.v\n             decode.sv\n             obj_dir/decode\n             obj_dir/decode.v\n             obj_dir/decode.sv\n%Error: Exiting due to 1 error(s), 34 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decode_tb();

parameter NOP = 32'b000000000000_00000_000_00000_0010011;
parameter ADDRESS_BITS = 16;


reg [ADDRESS_BITS-1:0] PC;
reg [31:0] instruction;


reg [ADDRESS_BITS-1:0] JALR_target;
reg branch;


wire next_PC_select;
wire [ADDRESS_BITS-1:0] target_PC;


wire [4:0] read_sel1;
wire [4:0] read_sel2;
wire [4:0] write_sel;
wire wEn;


wire branch_op;
wire [31:0] imm32;
wire [1:0] op_A_sel;
wire op_B_sel;
wire [5:0] ALU_Control;


wire mem_wEn;


wire wb_sel;

decode #(
  .ADDRESS_BITS(ADDRESS_BITS)
) uut (


  .PC(PC),
  .instruction(instruction),


  .JALR_target(JALR_target),
  .branch(branch),


  .next_PC_select(next_PC_select),
  .target_PC(target_PC),


  .read_sel1(read_sel1),
  .read_sel2(read_sel2),
  .write_sel(write_sel),
  .wEn(wEn),


  .branch_op(branch_op),
  .imm32(imm32),
  .op_A_sel(op_A_sel),
  .op_B_sel(op_B_sel),
  .ALU_Control(ALU_Control),


  .mem_wEn(mem_wEn),


  .wb_sel(wb_sel)

);



task print_state;
  begin

    $display("Time:         %0d", $time);
    $display("instruction:  %b", instruction);
    $display("PC:           %h", PC);
    $display("JALR_target:  %h", JALR_target);
    $display("branch        %b", branch);
    $display("next_PC_sel   %b", next_PC_select);
    $display("target_PC     %h", target_PC);
    $display("read_sel1:    %d", read_sel1);
    $display("read_sel2:    %d", read_sel2);
    $display("write_sel:    %d", write_sel);
    $display("wEn:          %b", wEn);
    $display("branch_op:    %b", branch_op);
    $display("imm32:        %b", imm32);
    $display("op_A_sel:     %b", op_A_sel);
    $display("op_B_sel:     %b", op_B_sel);
    $display("ALU_Control:  %b", ALU_Control);
    $display("mem_wEn:      %b", mem_wEn);
    $display("wb_sel:       %b", wb_sel);
    $display("--------------------------------------------------------------------------------");
    $display("\n\n");
  end
endtask



initial begin
  $display("Starting Decode Test");
  $display("--------------------------------------------------------------------------------");
  instruction = NOP;
  PC          = 0;
  JALR_target = 0;
  branch      = 0;

  #10

  $display("addi zero, zero, 0");
  print_state();

  instruction = 32'b111111111111_00000_000_01011_0010011;

  #10



  $display("addi a1, zero, -1");
  print_state();
  instruction = 32'b0000000_01100_01011_000_10000_0110011;

  #10
  $display("add a6, a1, a2");
  print_state();
  instruction = 32'b0100000_01110_01100_000_10001_0110011;

  #10
  $display("sub a7, a2, a4");
  print_state();
  instruction = 32'b0000000_01111_01011_010_01010_0110011;

  #10
  $display("slt a0, a1, a5");
  print_state();
  instruction = 32'b0000000_01111_01011_100_01110_0110011;

  #10
  $display("xor a4, a1, a5");
  print_state();
  instruction = 32'b0000000_01011_01101_111_01101_0110011;

  #10
  $display("and a3, a3, a1");
  print_state();
  instruction = 32'b011000000000_00000_000_01011_0010011;

  #10
  $display("addi a1, zero, 1536");
  print_state();
  instruction = 32'b0000000_01100_01011_010_00000_0100011;

  #10
  $display("sw a2, 0(a1)");
  print_state();
  instruction = 32'b000000000000_01011_010_10010_0000011;

  #10
  $display("lw s2, 0(a1)");
  print_state();
  instruction = NOP;

  PC = 16'h0114;
  instruction = 32'h0140006f;

  #10
  $display("jal	zero, 20");
  print_state();

  JALR_target = 16'h0154;
  PC = 16'h0094;
  instruction = 32'h0c4080e7;

  #10
  $display("jalr ra,196(ra)");
  print_state();


  
  instruction = 32'b00000000000000100000_00010_0110111;

  #10
  $display("lui 32, x2");
  print_state();
  
  PC = 16'h0004;
  
  instruction = 32'b00000000000000000100_00010_0010111;

  #10
  $display("AUIPC 4, x2");
  print_state();
  instruction = 32'b0000001_00010_00001_000_00000_1100011;
  
  #10
  $display("BEQ x2, x1, 16");
  print_state();
  instruction = 32'b0000001_00010_00001_001_00000_1100011;
  
  #10
  $display("BNE x2, x1, 16");
  print_state();
  instruction = 32'b0000001_00010_00001_100_00000_1100011;
  
  #10
  $display("BLT x2, x1, 16");
  print_state();
  instruction = 32'b0000001_00010_00001_101_00000_1100011;
  
  #10
  $display("BGE x2, x1, 16");
  print_state();
  instruction = 32'b0000001_00010_00001_110_00000_1100011;
  
  #10
  $display("BLTU x2, x1, 16");
  print_state();
  instruction = 32'b0000001_00010_00001_111_00000_1100011;
  
  #10
  $display("BGEU x2, x1, 16");
  print_state();
  instruction = 32'b000000000100_00010_010_00001_0010011;
  
  #10
  $display("slti x2, x1, 4 ");
  print_state();
  instruction = 32'b000000001000_00010_011_00001_0010011;
  
  #10
  $display("sltiu x2, x1, 8 ");
  print_state();
  instruction = 32'b000000000100_00010_100_00001_0010011;
  
  #10
  $display("xori x2, x1, 4");
  print_state();
  instruction = 32'b000000001000_00010_110_00001_0010011;
  
  #10
  $display("ori x2, x1, 8");
  print_state();
  instruction = 32'b000000010000_00010_111_00001_0010011;
  
  #10
  $display("andi x2, x1, 16");
  print_state();
  instruction = 32'b0000000_00001_00010_001_00001_0010011;
  
  #10
  $display("slli x2, x1, 1 ");
  print_state();
  instruction = 32'b0000000_00010_00010_101_00001_0010011;
  
  #10
  $display("srli x2, x1, 2 ");
  print_state();
  instruction = 32'b0100000_00100_00010_101_00001_0010011;
  
  #10
  $display("srai x2, x1, 4 ");
  print_state();
  instruction = 32'b0000000_00010_00011_001_00100_0110011;
  
  #10
  $display("sll x4, x3, x2");
  print_state();
  instruction = 32'b0000000_00010_00011_011_00100_0110011;
  
  #10
  $display("sltu x4, x3, x2");
  print_state();
  instruction = 32'b0000000_00010_00011_101_00100_0110011;
  
  #10
  $display("srl x4, x3, x2");
  print_state();
  instruction = 32'b0100000_00010_00011_101_00100_0110011;
  
  #10
  $display("sra x4, x3, x2");
  print_state();
  instruction = 32'b0000000_00010_00011_110_00100_0110011;
  
  #10
  $display("or x4, x3, x2");
  print_state();
  
  #10
  $stop();
end

endmodule
module decode_tb();


parameter NOP = 32'b000000000000_00000_000_00000_0010011;
parameter ADDRESS_BITS = 16;


reg [ADDRESS_BITS-1:0] PC;
reg [31:0] instruction;


reg [ADDRESS_BITS-1:0] JALR_target;
reg branch;


wire next_PC_select;
wire [ADDRESS_BITS-1:0] target_PC;


wire [4:0] read_sel1;
wire [4:0] read_sel2;
wire [4:0] write_sel;
wire wEn;


wire branch_op;
wire [31:0] imm32;
wire [1:0] op_A_sel;
wire op_B_sel;
wire [5:0] ALU_Control;


wire mem_wEn;


wire wb_sel;

decode #(
  .ADDRESS_BITS(ADDRESS_BITS)
) uut (


  .PC(PC),
  .instruction(instruction),


  .JALR_target(JALR_target),
  .branch(branch),


  .next_PC_select(next_PC_select),
  .target_PC(target_PC),


  .read_sel1(read_sel1),
  .read_sel2(read_sel2),
  .write_sel(write_sel),
  .wEn(wEn),


  .branch_op(branch_op),
  .imm32(imm32),
  .op_A_sel(op_A_sel),
  .op_B_sel(op_B_sel),
  .ALU_Control(ALU_Control),


  .mem_wEn(mem_wEn),


  .wb_sel(wb_sel)

);



task print_state;
  begin

    $display("Time:         %0d", $time);
    $display("instruction:  %b", instruction);
    $display("PC:           %h", PC);
    $display("JALR_target:  %h", JALR_target);
    $display("branch        %b", branch);
    $display("next_PC_sel   %b", next_PC_select);
    $display("target_PC     %h", target_PC);
    $display("read_sel1:    %d", read_sel1);
    $display("read_sel2:    %d", read_sel2);
    $display("write_sel:    %d", write_sel);
    $display("wEn:          %b", wEn);
    $display("branch_op:    %b", branch_op);
    $display("imm32:        %b", imm32);
    $display("op_A_sel:     %b", op_A_sel);
    $display("op_B_sel:     %b", op_B_sel);
    $display("ALU_Control:  %b", ALU_Control);
    $display("mem_wEn:      %b", mem_wEn);
    $display("wb_sel:       %b", wb_sel);
    $display("--------------------------------------------------------------------------------");
    $display("\n\n");
  end
endtask



initial begin
  $display("Starting Decode Test");
  $display("--------------------------------------------------------------------------------");
  instruction = NOP;
  PC          = 0;
  JALR_target = 0;
  branch      = 0;

  #10

  $display("addi zero, zero, 0");
  print_state();

  instruction = 32'b111111111111_00000_000_01011_0010011;

  #10



  $display("addi a1, zero, -1");
  print_state();
  instruction = 32'b0000000_01100_01011_000_10000_0110011;

  #10
  $display("add a6, a1, a2");
  print_state();
  instruction = 32'b0100000_01110_01100_000_10001_0110011;

  #10
  $display("sub a7, a2, a4");
  print_state();
  instruction = 32'b0000000_01111_01011_010_01010_0110011;

  #10
  $display("slt a0, a1, a5");
  print_state();
  instruction = 32'b0000000_01111_01011_100_01110_0110011;

  #10
  $display("xor a4, a1, a5");
  print_state();
  instruction = 32'b0000000_01011_01101_111_01101_0110011;

  #10
  $display("and a3, a3, a1");
  print_state();
  instruction = 32'b011000000000_00000_000_01011_0010011;

  #10
  $display("addi a1, zero, 1536");
  print_state();
  instruction = 32'b0000000_01100_01011_010_00000_0100011;

  #10
  $display("sw a2, 0(a1)");
  print_state();
  instruction = 32'b000000000000_01011_010_10010_0000011;

  #10
  $display("lw s2, 0(a1)");
  print_state();
  instruction = NOP;

  PC = 16'h0114;
  instruction = 32'h0140006f;

  #10
  $display("jal	zero, 20");
  print_state();

  JALR_target = 16'h0154;
  PC = 16'h0094;
  instruction = 32'h0c4080e7;

  #10
  $display("jalr ra,196(ra)");
  print_state();


  
  instruction = 32'b00000000000000100000_00010_0110111;

  #10
  $display("lui 32, x2");
  print_state();
  
  PC = 16'h0004;
  
  instruction = 32'b00000000000000000100_00010_0010111;

  #10
  $display("AUIPC 4, x2");
  print_state();
  instruction = 32'b0000001_00010_00001_000_00000_1100011;
  
  #10
  $display("BEQ x2, x1, 16");
  print_state();
  instruction = 32'b0000001_00010_00001_001_00000_1100011;
  
  #10
  $display("BNE x2, x1, 16");
  print_state();
  instruction = 32'b0000001_00010_00001_100_00000_1100011;
  
  #10
  $display("BLT x2, x1, 16");
  print_state();
  instruction = 32'b0000001_00010_00001_101_00000_1100011;
  
  #10
  $display("BGE x2, x1, 16");
  print_state();
  instruction = 32'b0000001_00010_00001_110_00000_1100011;
  
  #10
  $display("BLTU x2, x1, 16");
  print_state();
  instruction = 32'b0000001_00010_00001_111_00000_1100011;
  
  #10
  $display("BGEU x2, x1, 16");
  print_state();
  instruction = 32'b000000000100_00010_010_00001_0010011;
  
  #10
  $display("slti x2, x1, 4 ");
  print_state();
  instruction = 32'b000000001000_00010_011_00001_0010011;
  
  #10
  $display("sltiu x2, x1, 8 ");
  print_state();
  instruction = 32'b000000000100_00010_100_00001_0010011;
  
  #10
  $display("xori x2, x1, 4");
  print_state();
  instruction = 32'b000000001000_00010_110_00001_0010011;
  
  #10
  $display("ori x2, x1, 8");
  print_state();
  instruction = 32'b000000010000_00010_111_00001_0010011;
  
  #10
  $display("andi x2, x1, 16");
  print_state();
  instruction = 32'b0000000_00001_00010_001_00001_0010011;
  
  #10
  $display("slli x2, x1, 1 ");
  print_state();
  instruction = 32'b0000000_00010_00010_101_00001_0010011;
  
  #10
  $display("srli x2, x1, 2 ");
  print_state();
  instruction = 32'b0100000_00100_00010_101_00001_0010011;
  
  #10
  $display("srai x2, x1, 4 ");
  print_state();
  instruction = 32'b0000000_00010_00011_001_00100_0110011;
  
  #10
  $display("sll x4, x3, x2");
  print_state();
  instruction = 32'b0000000_00010_00011_011_00100_0110011;
  
  #10
  $display("sltu x4, x3, x2");
  print_state();
  instruction = 32'b0000000_00010_00011_101_00100_0110011;
  
  #10
  $display("srl x4, x3, x2");
  print_state();
  instruction = 32'b0100000_00010_00011_101_00100_0110011;
  
  #10
  $display("sra x4, x3, x2");
  print_state();
  instruction = 32'b0000000_00010_00011_110_00100_0110011;
  
  #10
  $display("or x4, x3, x2");
  print_state();
  
  #10
  $stop();
end

endmodule