data/full_repos/permissive/113839829/Source/CPU/ctrl.v
'utf-8' codec can't decode byte 0xbe in position 112: invalid start byte
1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/ctrl.v:5: Cannot find include file: defines.v\n `include "defines.v" \n          ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/ctrl.v:20: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) stall <= 6\'b000000;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ctrl.v:20: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(rst == `RstEnable) stall <= 6\'b000000;\n                     ^\n%Error: Exiting due to 3 error(s)\n'
module ctrl
  (
   input wire 	    rst,
   input wire 	    stallreq_from_id1,
   input wire 	    stallreq_from_id2,
   input wire 	    stallreq_from_if_cache,
   input wire 	    stallreq_from_mem_cache,

   output reg [5:0] stall
   );

   always @ (*) 
     begin
	if(rst == `RstEnable) stall <= 6'b000000;
	else if (stallreq_from_mem_cache == 1'b1) 
	     stall <= 6'b011111;
	else if (stallreq_from_if_cache == 1'b1)  
	     stall <= 6'b000111;
	else if (stallreq_from_id2 == 1'b1) 
	     stall <= 6'b000111;
	else if (stallreq_from_id1 == 1'b1) 
	     stall <= 6'b000010;
	else stall <= 6'b000000;
     end
   
endmodule
module ctrl
  (
   input wire 	    rst,
   input wire 	    stallreq_from_id1,
   input wire 	    stallreq_from_id2,
   input wire 	    stallreq_from_if_cache,
   input wire 	    stallreq_from_mem_cache,

   output reg [5:0] stall
   );


   always @ (*) 
     begin
	if(rst == `RstEnable) stall <= 6'b000000;
	else if (stallreq_from_mem_cache == 1'b1) 
	     stall <= 6'b011111;
	else if (stallreq_from_if_cache == 1'b1)  
	     stall <= 6'b000111;
	else if (stallreq_from_id2 == 1'b1) 
	     stall <= 6'b000111;
	else if (stallreq_from_id1 == 1'b1) 
	     stall <= 6'b000010;
	else stall <= 6'b000000;
     end
   
endmodule