data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/sq_mult.v
1: b"%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/sq_mult.v:29: syntax error, unexpected ref, expecting '['\n    input                  ref,\n                           ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/sq_mult.v:36: syntax error, unexpected assign\n    assign plus_in  =  in          ;\n    ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module sq_mult #(parameter R=14)
    (
    input clk,rst,
    input                  ref,
    input  signed [ R-1:0] in,
    output signed [ R-1:0] out
    );
    
    wire  signed [R-1:0] plus_in, minus_in ;
    
    assign plus_in  =  in          ;
    assign minus_in = {R{1'b0}}-$signed(in) ;
    
    assign out = ref ? plus_in : minus_in ; 
    

    
endmodule
module sq_mult #(parameter R=14)
    (
    input clk,rst,
    input                  ref,
    input  signed [ R-1:0] in,
    output signed [ R-1:0] out
    );

    
    wire  signed [R-1:0] plus_in, minus_in ;
    
    assign plus_in  =  in          ;
    assign minus_in = {R{1'b0}}-$signed(in) ;
    
    assign out = ref ? plus_in : minus_in ; 
    

    
endmodule