data/full_repos/permissive/202237519/verilog/digitalsystem project/counter.v
1: b'%Error: Cannot find file containing module: project,data/full_repos/permissive/202237519\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519.sv\n             project,data/full_repos/permissive/202237519\n             project,data/full_repos/permissive/202237519.v\n             project,data/full_repos/permissive/202237519.sv\n             obj_dir/project,data/full_repos/permissive/202237519\n             obj_dir/project,data/full_repos/permissive/202237519.v\n             obj_dir/project,data/full_repos/permissive/202237519.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/202237519/verilog/digitalsystem\n%Error: Cannot find file containing module: project/counter.v\n%Error: Exiting due to 3 error(s)\n'
module counter_100bit (reset, clk, c_out);

input reset, clk;
output c_out;

reg [5:0]count = 6'b000000;
reg q = 1'b0;
assign c_out = q;

always@(posedge clk) begin
    if(reset) begin
        count <= 6'b000000;
        q <= 1'b0;
        end
    else begin
        count = count + 1;
        if(count == 6'b110010) begin
            q <= ~q;
            count <= 6'b000000;
        end
    end
end

endmodule
module counter_100bit (reset, clk, c_out);


input reset, clk;
output c_out;

reg [5:0]count = 6'b000000;
reg q = 1'b0;
assign c_out = q;

always@(posedge clk) begin
    if(reset) begin
        count <= 6'b000000;
        q <= 1'b0;
        end
    else begin
        count = count + 1;
        if(count == 6'b110010) begin
            q <= ~q;
            count <= 6'b000000;
        end
    end
end

endmodule