data/full_repos/permissive/124803629/src/Single_Cycle_CPU/CPU_clk.v
data/verilator_xmls/75c8303c-2ac1-4d8e-a794-e3b8e0ed2ad5.xml
module CPU_clk (sysclk, reset, clk);
input sysclk, reset;
output reg clk;


always @(posedge sysclk or negedge reset) begin
	if(~reset)
		clk <= 0;
	else
		clk <= ~clk;
end

endmodule
module CPU_clk (sysclk, reset, clk);

input sysclk, reset;
output reg clk;


always @(posedge sysclk or negedge reset) begin
	if(~reset)
		clk <= 0;
	else
		clk <= ~clk;
end

endmodule