data/full_repos/permissive/152883307/Project/Scale.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152883307/Project/Scale.v:9: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 13 bits.\n                                                                      : ... In instance Scale\n  if(!in[12]) out<=256+(in>>4);\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/152883307/Project/Scale.v:10: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 13 bits.\n                                                                       : ... In instance Scale\n  else   out<=256-(~in>>4);\n            ^~\n%Error: Exiting due to 2 warning(s)\n'
module Scale(
	input			[12:0] in,
	input					 clk,
	output reg	[8:0]  out
);

always@(negedge clk)
begin
		if(!in[12]) out<=256+(in>>4);
		else			out<=256-(~in>>4);
end
endmodule
module Scale(
	input			[12:0] in,
	input					 clk,
	output reg	[8:0]  out
);


always@(negedge clk)
begin
		if(!in[12]) out<=256+(in>>4);
		else			out<=256-(~in>>4);
end
endmodule