data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/mem/ddr3_parameters.vh
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/1a968e26-cf8d-4e89-93ef-8047b9533cb1.xml
function [3:0] min_cl;
    input period;
    real period;
    reg [3:0] cwl;
    reg [3:0] cl;
    begin
        cwl = min_cwl(period);
        for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin
            if (valid_cl(cl, cwl)) begin
                min_cl = cl;
            end
        end
    end
endfunction
function [3:0] min_cl;

    input period;
    real period;
    reg [3:0] cwl;
    reg [3:0] cl;
    begin
        cwl = min_cwl(period);
        for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin
            if (valid_cl(cl, cwl)) begin
                min_cl = cl;
            end
        end
    end
endfunction