data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-3_analisis/analisis.v
1: b"%Error: data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-3_analisis/analisis.v:60: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n    nand nand_1( );\n                 ^\n%Error: Exiting due to 1 error(s)\n"
module sistema (
    input  wire x,
    input  wire y,
    input  wire z,
    output wire f
    );



    dec4 dec4_1();
    nand nand_1();
    mux2 mux2_1();

endmodule
module sistema (
    input  wire x,
    input  wire y,
    input  wire z,
    output wire f
    );




    dec4 dec4_1();
    nand nand_1();
    mux2 mux2_1();

endmodule