data/full_repos/permissive/10379745/testbench.sv
 line:9: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/10379745/testbench.sv:9: Unsupported: Ignoring delay on this delayed statement.\n   #10ns;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/10379745/testbench.sv:17: Unsupported: Ignoring delay on this delayed statement.\n   #100ns;\n   ^\n%Error: data/full_repos/permissive/10379745/testbench.sv:22: Can\'t find definition of \'INT_BTN\' in dotted variable: \'IO.INT_BTN\'\nassign IO.INT_BTN = 0;\n          ^~~~~~~\n%Error: data/full_repos/permissive/10379745/testbench.sv:23: Can\'t find definition of \'LEDS_RD\' in dotted variable: \'IO.LEDS_RD\'\nassign IO.LEDS_RD = 0;\n          ^~~~~~~\n%Error: data/full_repos/permissive/10379745/testbench.sv:26: Can\'t find definition of \'LEDS_WE\' in dotted variable: \'IO.LEDS_WE\'\n   if(IO.LEDS_WE) leds <= IO.LEDS_WD[7:0];\n         ^~~~~~~\n%Error: data/full_repos/permissive/10379745/testbench.sv:26: Can\'t find definition of \'LEDS_WD\' in dotted variable: \'IO.LEDS_WD\'\n   if(IO.LEDS_WE) leds <= IO.LEDS_WD[7:0];\n                             ^~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

logic       CLK, RESET;
logic [7:0] leds;
if_io       IO();

always
   begin
   #10ns;
   CLK = ~CLK;
   end

initial
   begin
   CLK = 0;
   RESET = 1;
   #100ns;
   RESET = 0;
   end


assign IO.INT_BTN = 0;
assign IO.LEDS_RD = 0;

always@(posedge CLK)
   if(IO.LEDS_WE) leds <= IO.LEDS_WD[7:0];

mcpu the_cpu(CLK, RESET, IO);

endmodule
module testbench;


logic       CLK, RESET;
logic [7:0] leds;
if_io       IO();

always
   begin
   #10ns;
   CLK = ~CLK;
   end

initial
   begin
   CLK = 0;
   RESET = 1;
   #100ns;
   RESET = 0;
   end


assign IO.INT_BTN = 0;
assign IO.LEDS_RD = 0;

always@(posedge CLK)
   if(IO.LEDS_WE) leds <= IO.LEDS_WD[7:0];

mcpu the_cpu(CLK, RESET, IO);

endmodule