data/full_repos/permissive/143278/ivltests/pr1864110c.v
 line:2: before: "real"
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr1864110c.v:13: Unsupported or unknown PLI call: $monitor\n    $monitor("%g %h", result, bits);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1864110c.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1 bits = {1\'b0,{62{1\'b1}}};\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  wire real result;
  reg [63:0] bits;






  assign result = $bitstoreal(bits);

  initial begin
    $monitor("%g %h", result, bits);

       bits = 64'b0;
    #1 bits = {1'b0,{62{1'b1}}};
  end
endmodule
module top;

  wire real result;
  reg [63:0] bits;






  assign result = $bitstoreal(bits);

  initial begin
    $monitor("%g %h", result, bits);

       bits = 64'b0;
    #1 bits = {1'b0,{62{1'b1}}};
  end
endmodule