data/full_repos/permissive/114814262/IC 2015-2016/HARDWARE/[DEPRECATED] sistema_controle_alarme v1.0.0/[FPGA] sistema_para_controle_de_alarme/v1.0.0/controle2.v
1: b'%Error: Cannot find file containing module: 2015-2016/HARDWARE/[DEPRECATED]\n        ... Looked in:\n             data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED]\n             data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED].v\n             data/full_repos/permissive/114814262/IC/2015-2016/HARDWARE/[DEPRECATED].sv\n             2015-2016/HARDWARE/[DEPRECATED]\n             2015-2016/HARDWARE/[DEPRECATED].v\n             2015-2016/HARDWARE/[DEPRECATED].sv\n             obj_dir/2015-2016/HARDWARE/[DEPRECATED]\n             obj_dir/2015-2016/HARDWARE/[DEPRECATED].v\n             obj_dir/2015-2016/HARDWARE/[DEPRECATED].sv\n%Error: Cannot find file containing module: sistema_controle_alarme\n%Error: Cannot find file containing module: v1.0.0/[FPGA]\n%Error: Cannot find file containing module: sistema_para_controle_de_alarme/v1.0.0,data/full_repos/permissive/114814262\n%Error: Cannot find file containing module: data/full_repos/permissive/114814262/IC\n%Error: Cannot find file containing module: sistema_para_controle_de_alarme/v1.0.0/controle2.v\n%Error: Exiting due to 6 error(s)\n'
module controle2(saida, crianca, communication, button, clk);

input clk, button, communication, crianca;
output[2:0] saida;
reg[2:0] saida=3'b000;

reg [2:0] state=3'b000;


reg[32:0] count;


parameter WAIT=3'b000,
			STAND_BY= 3'b001,
			LED=3'b010,
			LED_VIBRA1=3'b011,
			LED_VIBRA2=3'b100,
			LED_VIBRA_APITA=3'b101;


parameter 	nula=3'b000,
				led0=3'b001,
				led_vibra0=3'b011,
				led_vibra_apita0=3'b111;
				
				
always @(posedge clk)
begin
	case(state)
		WAIT 				: begin
								if(communication==1'b0 && crianca==1'b0) 
								begin
									state<=STAND_BY;
									saida<=nula;
								end else
								if(communication==1'b0 && crianca==1'b1)
								begin
									state<=LED;
									saida<=led0;
								end else
										begin 
											state<=WAIT;
											saida<=nula;
										end
							 end
		STAND_BY 		: begin
								if(communication==1'b1)
								begin
									state<=WAIT;
									saida<=nula;
								end 
							 end											
		LED				: begin
								if(crianca==1'b0 && communication==1'b1)
								begin
									state<=WAIT;
									saida<=nula;
								end else
								if(button==1'b1)
								begin




									state<=#5 LED_VIBRA2;
									saida<=#5 led_vibra0;
								end else
										begin




											state<=#5 LED_VIBRA1;
											saida<=#5 led_vibra0;
										end
						 end
		LED_VIBRA1 		: begin
								if(crianca==1'b0 && communication==1'b1)
								begin
									state<=WAIT;
									saida<=nula;
								end else
								if(button==1'b1)
								begin
									state<=LED_VIBRA2;
									saida<=led_vibra0;
								end else		
										begin




											state<=#5 LED_VIBRA_APITA;
											saida<=#5 led_vibra_apita0;
										end
							 end
		LED_VIBRA_APITA: begin
								if(crianca==1'b0 && communication==1'b1)
								begin
									state<=WAIT;
									saida<=nula;
								end else
								if(button==1'b1)
								begin
									state<=LED_VIBRA2;
									saida<=led_vibra0;
								end else
										begin
											state<=LED_VIBRA_APITA;
											saida<=led_vibra_apita0;
										end
							 end
		LED_VIBRA2		: begin
								if(crianca==1'b0 && communication==1'b1)
								begin
									state<=WAIT;
									saida<=nula;
								end else
										begin



											state<=#5 LED_VIBRA_APITA;
											saida<=#5 led_vibra_apita0;
										end
								
							 end
		default			: begin	
								state<=WAIT;
								saida<=nula;
							 end
		endcase
end
endmodule
module controle2(saida, crianca, communication, button, clk);


input clk, button, communication, crianca;
output[2:0] saida;
reg[2:0] saida=3'b000;

reg [2:0] state=3'b000;


reg[32:0] count;


parameter WAIT=3'b000,
			STAND_BY= 3'b001,
			LED=3'b010,
			LED_VIBRA1=3'b011,
			LED_VIBRA2=3'b100,
			LED_VIBRA_APITA=3'b101;


parameter 	nula=3'b000,
				led0=3'b001,
				led_vibra0=3'b011,
				led_vibra_apita0=3'b111;
				
				
always @(posedge clk)
begin
	case(state)
		WAIT 				: begin
								if(communication==1'b0 && crianca==1'b0) 
								begin
									state<=STAND_BY;
									saida<=nula;
								end else
								if(communication==1'b0 && crianca==1'b1)
								begin
									state<=LED;
									saida<=led0;
								end else
										begin 
											state<=WAIT;
											saida<=nula;
										end
							 end
		STAND_BY 		: begin
								if(communication==1'b1)
								begin
									state<=WAIT;
									saida<=nula;
								end 
							 end											
		LED				: begin
								if(crianca==1'b0 && communication==1'b1)
								begin
									state<=WAIT;
									saida<=nula;
								end else
								if(button==1'b1)
								begin




									state<=#5 LED_VIBRA2;
									saida<=#5 led_vibra0;
								end else
										begin




											state<=#5 LED_VIBRA1;
											saida<=#5 led_vibra0;
										end
						 end
		LED_VIBRA1 		: begin
								if(crianca==1'b0 && communication==1'b1)
								begin
									state<=WAIT;
									saida<=nula;
								end else
								if(button==1'b1)
								begin
									state<=LED_VIBRA2;
									saida<=led_vibra0;
								end else		
										begin




											state<=#5 LED_VIBRA_APITA;
											saida<=#5 led_vibra_apita0;
										end
							 end
		LED_VIBRA_APITA: begin
								if(crianca==1'b0 && communication==1'b1)
								begin
									state<=WAIT;
									saida<=nula;
								end else
								if(button==1'b1)
								begin
									state<=LED_VIBRA2;
									saida<=led_vibra0;
								end else
										begin
											state<=LED_VIBRA_APITA;
											saida<=led_vibra_apita0;
										end
							 end
		LED_VIBRA2		: begin
								if(crianca==1'b0 && communication==1'b1)
								begin
									state<=WAIT;
									saida<=nula;
								end else
										begin



											state<=#5 LED_VIBRA_APITA;
											saida<=#5 led_vibra_apita0;
										end
								
							 end
		default			: begin	
								state<=WAIT;
								saida<=nula;
							 end
		endcase
end
endmodule