data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/tb/testbench.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/tb/testbench.sv:42: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/tb/testbench.sv:44: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/tb/testbench.sv:46: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/tb/testbench.sv:48: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/tb/testbench.sv:50: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/tb/testbench.sv:52: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/tb/testbench.sv:54: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Error: data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/tb/testbench.sv:60: Unsupported or unknown PLI call: $monitor\n        $monitor("sel=%b din=%b dout_0=%b dout_1=%b",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/tb/testbench.sv:61: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                  sel,   din,   dout_0,   dout_1,  );\n                                                   ^\n%Error: data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/tb/testbench.sv:64: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;   \n        ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

    reg       [1:0] din;
    reg       [1:0] sel;
    wire [3:0][1:0] dout_0;
    wire [3:0][1:0] dout_1;

    b2_demux_1_4_univ
    #(
        .MODE  ( "CASE"      )
    )
    case_0
    (
        .din   ( din         ),
        .sel   ( sel         ),
        .dout0 ( dout_0 [0]  ),
        .dout1 ( dout_0 [1]  ),
        .dout2 ( dout_0 [2]  ),
        .dout3 ( dout_0 [3]  )
    );

    b2_demux_1_4_univ
    #(
        .MODE  ( "SV" )
    )
    case_1
    (
        .din   ( din         ),
        .sel   ( sel         ),
        .dout0 ( dout_1 [0]  ),
        .dout1 ( dout_1 [1]  ),
        .dout2 ( dout_1 [2]  ),
        .dout3 ( dout_1 [3]  )
    );

    initial
        begin
            din = 2'b11;
            #5;
            sel = 2'b00;
            #10;
            sel = 2'b01;
            #10
            sel = 2'b10;
            #10;
            sel = 2'b11;
            #10;
            din = 2'b10;
            #10;
            din = 2'b01;
            #10;
            $finish();
        end


    initial 
        $monitor("sel=%b din=%b dout_0=%b dout_1=%b",
                  sel,   din,   dout_0,   dout_1,  );

    initial 
        $dumpvars;
endmodule
module testbench;


    reg       [1:0] din;
    reg       [1:0] sel;
    wire [3:0][1:0] dout_0;
    wire [3:0][1:0] dout_1;

    b2_demux_1_4_univ
    #(
        .MODE  ( "CASE"      )
    )
    case_0
    (
        .din   ( din         ),
        .sel   ( sel         ),
        .dout0 ( dout_0 [0]  ),
        .dout1 ( dout_0 [1]  ),
        .dout2 ( dout_0 [2]  ),
        .dout3 ( dout_0 [3]  )
    );

    b2_demux_1_4_univ
    #(
        .MODE  ( "SV" )
    )
    case_1
    (
        .din   ( din         ),
        .sel   ( sel         ),
        .dout0 ( dout_1 [0]  ),
        .dout1 ( dout_1 [1]  ),
        .dout2 ( dout_1 [2]  ),
        .dout3 ( dout_1 [3]  )
    );

    initial
        begin
            din = 2'b11;
            #5;
            sel = 2'b00;
            #10;
            sel = 2'b01;
            #10
            sel = 2'b10;
            #10;
            sel = 2'b11;
            #10;
            din = 2'b10;
            #10;
            din = 2'b01;
            #10;
            $finish();
        end


    initial 
        $monitor("sel=%b din=%b dout_0=%b dout_1=%b",
                  sel,   din,   dout_0,   dout_1,  );

    initial 
        $dumpvars;
endmodule