data/full_repos/permissive/143278/ivltests/select2.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/select2.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (b !== 0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/select2.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (b !== 1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/select2.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (b !== 1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/select2.v:53: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (b !== 0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/select2.v:59: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (b !== 1\'bx) begin\n      ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg  [3:0] a = 4'b0110;
   reg [1:0]  s = 0;

   wire       b = a[s];

   initial begin
      #1 if (b !== 0) begin
	 $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
	 $finish;
      end

      s = 1;

      #1 if (b !== 1) begin
	 $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
	 $finish;
      end

      s = 2;

      #1 if (b !== 1) begin
	 $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
	 $finish;
      end

      s = 3;

      #1 if (b !== 0) begin
	 $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
	 $finish;
      end

      s = 2'bxx;
      #1 if (b !== 1'bx) begin
	 $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg  [3:0] a = 4'b0110;
   reg [1:0]  s = 0;

   wire       b = a[s];

   initial begin
      #1 if (b !== 0) begin
	 $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
	 $finish;
      end

      s = 1;

      #1 if (b !== 1) begin
	 $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
	 $finish;
      end

      s = 2;

      #1 if (b !== 1) begin
	 $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
	 $finish;
      end

      s = 3;

      #1 if (b !== 0) begin
	 $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
	 $finish;
      end

      s = 2'bxx;
      #1 if (b !== 1'bx) begin
	 $display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
	 $finish;
      end

      $display("PASSED");
   end

endmodule