data/full_repos/permissive/174323821/hdl/clocking/jtframe_rst_sync.v
data/verilator_xmls/efb3b8d9-505a-4d2c-bf10-830b24fb51b4.xml
module jtframe_rst_sync(
    input   rst,
    input   clk,
    output  rst_sync
);

reg [1:0] s;

assign rst_sync = s[1];

always @(posedge clk) begin
    s <= { s[0], rst };
end

endmodule
module jtframe_rst_sync(
    input   rst,
    input   clk,
    output  rst_sync
);


reg [1:0] s;

assign rst_sync = s[1];

always @(posedge clk) begin
    s <= { s[0], rst };
end

endmodule