data/full_repos/permissive/157436936/ex3/Top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #1000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #3000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #2500000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #3500000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #2000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157436936/ex3/Top_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n always #1 sys_clk = ~sys_clk;\n        ^\n%Error: data/full_repos/permissive/157436936/ex3/Top_tb.v:19: Cannot find file containing module: \'Top\'\n Top uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/157436936/ex3,data/full_repos/permissive/157436936/Top\n             data/full_repos/permissive/157436936/ex3,data/full_repos/permissive/157436936/Top.v\n             data/full_repos/permissive/157436936/ex3,data/full_repos/permissive/157436936/Top.sv\n             Top\n             Top.v\n             Top.sv\n             obj_dir/Top\n             obj_dir/Top.v\n             obj_dir/Top.sv\n%Error: Exiting due to 1 error(s), 21 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Top_tb;


	reg sys_clk;
	reg sys_rst;
	reg [1:0] switch;
	reg [1:0] key;
	reg Uart_Rx;


	wire [1:0] com;
	wire [7:0] seg;
	wire [3:0] led;
	wire Uart_Tx;


	Top uut (
		.sys_clk(sys_clk), 
		.sys_rst(sys_rst), 
		.switch(switch), 
		.key(key), 
		.com(com), 
		.seg(seg), 
		.led(led), 
		.Uart_Tx(Uart_Tx), 
		.Uart_Rx(Uart_Rx)
	);

	initial begin

		sys_clk = 0;
		sys_rst = 1;
		switch = 0;
		key = 0;
		Uart_Rx = 0;


		#100;

		sys_rst = 0;
		#10;
		sys_rst = 1;
		#10;
		switch = 2'b00;
		#10;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#10;
		switch = 2'b01;
		#10;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#1000000;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#3000000;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#2500000;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#3500000;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#100;
		switch = 2'b00;
		#100;
		switch = 2'b10;
		#100;
		key = 2'b10;
		#2000000;
		key = 2'b00;
	end
	
	always #1 sys_clk = ~sys_clk;
      
endmodule
module Top_tb;



	reg sys_clk;
	reg sys_rst;
	reg [1:0] switch;
	reg [1:0] key;
	reg Uart_Rx;


	wire [1:0] com;
	wire [7:0] seg;
	wire [3:0] led;
	wire Uart_Tx;


	Top uut (
		.sys_clk(sys_clk), 
		.sys_rst(sys_rst), 
		.switch(switch), 
		.key(key), 
		.com(com), 
		.seg(seg), 
		.led(led), 
		.Uart_Tx(Uart_Tx), 
		.Uart_Rx(Uart_Rx)
	);

	initial begin

		sys_clk = 0;
		sys_rst = 1;
		switch = 0;
		key = 0;
		Uart_Rx = 0;


		#100;

		sys_rst = 0;
		#10;
		sys_rst = 1;
		#10;
		switch = 2'b00;
		#10;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#10;
		switch = 2'b01;
		#10;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#1000000;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#3000000;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#2500000;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#3500000;
		key = 2'b01;
		#2000000;
		key = 2'b00;
		#100;
		switch = 2'b00;
		#100;
		switch = 2'b10;
		#100;
		key = 2'b10;
		#2000000;
		key = 2'b00;
	end
	
	always #1 sys_clk = ~sys_clk;
      
endmodule