data/full_repos/permissive/101428364/clk_div.v
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data/verilator_xmls/a813a316-ec82-48e5-b91e-ca89bfeb71a8.xml
module clk_div(input clk,
					input rst,
					input SW2,
					input SW15,
					input keyReady,
					input [3:0] BTN_OK,
					output reg[31:0]clkdiv,
					output Clk_CPU,
					output reg readn
					);
					

	
	wire auto_clk;
	reg [31:0] step;
	reg [4:0] counter;
	reg wasReady;
	


	always @ (posedge clk or posedge rst) begin 
		if (rst) clkdiv <= 0;
		else clkdiv <= clkdiv + 1'b1; 
	end
	
	assign auto_clk =(SW2)? clkdiv[24] : clkdiv[4];
	assign Clk_CPU = (SW15) ? step[0] : auto_clk;
	
	always @ (posedge clk or posedge rst) begin
		if(rst) begin
			step <= 0;
			counter <= 0;
		end
		else begin
			if(counter != 0 && clkdiv[24]) begin
				step <= step + 1'b1;
				counter <= counter - 1'b1;
			end
			else begin
				wasReady <= keyReady;
				readn <= 1;
				if(!wasReady && keyReady) begin
					readn <= 0;
					if(BTN_OK[0]) counter <= 5'd2;
					else if(BTN_OK[1]) counter <= 5'd4;
					else if(BTN_OK[2]) counter <= 5'd10;
					else if(BTN_OK[3]) counter <= 5'd20;
				end
			end
		end
	end
	
	
	
	
endmodule
module clk_div(input clk,
					input rst,
					input SW2,
					input SW15,
					input keyReady,
					input [3:0] BTN_OK,
					output reg[31:0]clkdiv,
					output Clk_CPU,
					output reg readn
					);

					

	
	wire auto_clk;
	reg [31:0] step;
	reg [4:0] counter;
	reg wasReady;
	


	always @ (posedge clk or posedge rst) begin 
		if (rst) clkdiv <= 0;
		else clkdiv <= clkdiv + 1'b1; 
	end
	
	assign auto_clk =(SW2)? clkdiv[24] : clkdiv[4];
	assign Clk_CPU = (SW15) ? step[0] : auto_clk;
	
	always @ (posedge clk or posedge rst) begin
		if(rst) begin
			step <= 0;
			counter <= 0;
		end
		else begin
			if(counter != 0 && clkdiv[24]) begin
				step <= step + 1'b1;
				counter <= counter - 1'b1;
			end
			else begin
				wasReady <= keyReady;
				readn <= 1;
				if(!wasReady && keyReady) begin
					readn <= 0;
					if(BTN_OK[0]) counter <= 5'd2;
					else if(BTN_OK[1]) counter <= 5'd4;
					else if(BTN_OK[2]) counter <= 5'd10;
					else if(BTN_OK[3]) counter <= 5'd20;
				end
			end
		end
	end
	
	
	
	
endmodule