data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv
 line:116: before: "unsigned"
1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:26: Cannot find file containing module: 'inv_ld_counter'\ninv_ld_counter #(7)  len_cnt( .CLK  ( CLK          ),  \n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter\n             data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter.v\n             data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter.sv\n             inv_ld_counter\n             inv_ld_counter.v\n             inv_ld_counter.sv\n             obj_dir/inv_ld_counter\n             obj_dir/inv_ld_counter.v\n             obj_dir/inv_ld_counter.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:32: Cannot find file containing module: 'inv_ld_counter'\ninv_ld_counter #(7) wlen_cnt( .CLK  ( CLK          ), \n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:38: Cannot find file containing module: 'ffd'\nffd #(1) nack_hack_fd(CLK, RESET, ld_wlen, DATA_IN[7], nack_hack);\n^~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:42: Cannot find file containing module: 'counter'\ncounter #(6) time_count(CLK, s_idle | half_period, 1'b1, time_cnt);\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:44: Cannot find file containing module: 'shift_out_reg_left'\nshift_out_reg_left #(8) sr_out(  .CLK    ( CLK                                  ), \n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:53: Cannot find file containing module: 'shift_in_reg_left'\nshift_in_reg_left   #(8) sr_in(  .CLK   ( CLK                                ),\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:88: Cannot find file containing module: 'ffds'\nffds #(1) scl_fd(CLK, l_scl, scl_q);\n^~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:89: Cannot find file containing module: 'ffds'\nffds #(1) sda_fd(CLK, l_sda, sda_q);\n^~~~\n%Error: Exiting due to 8 error(s)\n"
module i2c_fsm (  input CLK,
                  input RESET,

                  input  START,
                  input  TIME,
                  input  L_DONE,
                  input  W_DONE,
                  output LD_LEN,
                  output LD_WLEN,
                  output S_DATA_LO,
                  output S_DATA_HI,
                  output S_ACK_LO,
                  output S_ACK_HI,
                  output S_START,
                  output S_STOP_LO,
                  output S_STOP_HI,
                  output S_IDLE );



enum int unsigned { ST_IDLE       = 0,
                    ST_RD_LEN     = 1,
                    ST_RD_WLEN    = 2,
                    ST_START      = 3, 
                    ST_DATA_LO    = 4,
                    ST_DATA_HI    = 5,
                    ST_ACK_LO     = 6,
                    ST_ACK_HI     = 7,
                    ST_STOP_LO    = 8,
                    ST_STOP_HI    = 9,
                    ST_WAIT       = 10 } state, next;

always_ff@(posedge CLK)
  if(RESET) state <= ST_IDLE;
  else      state <= next;

always_comb
   case(state)
   ST_IDLE:    if(START)     next = ST_RD_LEN;
               else          next = state;

   ST_RD_LEN:                next = ST_RD_WLEN;

   ST_RD_WLEN: if(L_DONE)    next = ST_IDLE;
               else          next = ST_START;

   ST_START:   if(TIME)      next = ST_DATA_LO;
               else          next = state;

   ST_DATA_LO: if(TIME)      next = ST_DATA_HI;
               else          next = state;

   ST_DATA_HI: if(TIME)    
                  begin
                  if(W_DONE) next = ST_ACK_LO;
                  else       next = ST_DATA_LO;
                  end
               else          next = state;

   ST_ACK_LO:  if(TIME)      next = ST_ACK_HI;
               else          next = state;

   ST_ACK_HI:  if(TIME)
                  begin
                  if(L_DONE) next = ST_STOP_LO;
                  else       next = ST_DATA_LO;
                  end
               else          next = state;

   ST_STOP_LO: if(TIME)      next = ST_STOP_HI;
               else          next = state;

   ST_STOP_HI: if(TIME)      next = ST_WAIT;
               else          next = state;


   ST_WAIT:    if(TIME)      next = ST_RD_LEN;
               else          next = state;

   default:                  next = ST_IDLE;

   endcase

assign LD_LEN    = (state == ST_RD_LEN);
assign LD_WLEN   = (state == ST_RD_WLEN); 
assign S_DATA_LO = (state == ST_DATA_LO);
assign S_DATA_HI = (state == ST_DATA_HI);
assign S_ACK_LO  = (state == ST_ACK_LO);
assign S_ACK_HI  = (state == ST_ACK_HI);
assign S_START   = (state == ST_START);
assign S_STOP_LO = (state == ST_STOP_LO);
assign S_STOP_HI = (state == ST_STOP_HI);
assign S_IDLE    = (state == ST_IDLE);

endmodule
module i2c_fsm (  input CLK,
                  input RESET,

                  input  START,
                  input  TIME,
                  input  L_DONE,
                  input  W_DONE,
                  output LD_LEN,
                  output LD_WLEN,
                  output S_DATA_LO,
                  output S_DATA_HI,
                  output S_ACK_LO,
                  output S_ACK_HI,
                  output S_START,
                  output S_STOP_LO,
                  output S_STOP_HI,
                  output S_IDLE );




enum int unsigned { ST_IDLE       = 0,
                    ST_RD_LEN     = 1,
                    ST_RD_WLEN    = 2,
                    ST_START      = 3, 
                    ST_DATA_LO    = 4,
                    ST_DATA_HI    = 5,
                    ST_ACK_LO     = 6,
                    ST_ACK_HI     = 7,
                    ST_STOP_LO    = 8,
                    ST_STOP_HI    = 9,
                    ST_WAIT       = 10 } state, next;

always_ff@(posedge CLK)
  if(RESET) state <= ST_IDLE;
  else      state <= next;

always_comb
   case(state)
   ST_IDLE:    if(START)     next = ST_RD_LEN;
               else          next = state;

   ST_RD_LEN:                next = ST_RD_WLEN;

   ST_RD_WLEN: if(L_DONE)    next = ST_IDLE;
               else          next = ST_START;

   ST_START:   if(TIME)      next = ST_DATA_LO;
               else          next = state;

   ST_DATA_LO: if(TIME)      next = ST_DATA_HI;
               else          next = state;

   ST_DATA_HI: if(TIME)    
                  begin
                  if(W_DONE) next = ST_ACK_LO;
                  else       next = ST_DATA_LO;
                  end
               else          next = state;

   ST_ACK_LO:  if(TIME)      next = ST_ACK_HI;
               else          next = state;

   ST_ACK_HI:  if(TIME)
                  begin
                  if(L_DONE) next = ST_STOP_LO;
                  else       next = ST_DATA_LO;
                  end
               else          next = state;

   ST_STOP_LO: if(TIME)      next = ST_STOP_HI;
               else          next = state;

   ST_STOP_HI: if(TIME)      next = ST_WAIT;
               else          next = state;


   ST_WAIT:    if(TIME)      next = ST_RD_LEN;
               else          next = state;

   default:                  next = ST_IDLE;

   endcase

assign LD_LEN    = (state == ST_RD_LEN);
assign LD_WLEN   = (state == ST_RD_WLEN); 
assign S_DATA_LO = (state == ST_DATA_LO);
assign S_DATA_HI = (state == ST_DATA_HI);
assign S_ACK_LO  = (state == ST_ACK_LO);
assign S_ACK_HI  = (state == ST_ACK_HI);
assign S_START   = (state == ST_START);
assign S_STOP_LO = (state == ST_STOP_LO);
assign S_STOP_HI = (state == ST_STOP_HI);
assign S_IDLE    = (state == ST_IDLE);

endmodule