data/full_repos/permissive/193419875/src/IDEX.v
data/verilator_xmls/518b3703-d349-44b6-8bd1-fa9c9db69f2f.xml
module IDEX
(
	input CLOCK,
	input [1:0] ALUop_in,
	input ALUsrc_in,
	input isBranch_in,
	input memRead_in,
	input memWrite_in,
	input regWrite_in,
	input memToReg_in,
	input [63:0] programCounter_in,
	input [63:0] regData1_in,
	input [63:0] regData2_in,
	input [63:0] signExtend_in,
	input [10:0] ALUcontrol_in,
	input [4:0] registerRm_in,
	input [4:0] registerRn_in,
	input [4:0] writeReg_in,
	output reg [1:0] ALUop_out,
	output reg ALUsrc_out,
	output reg isBranch_out,
	output reg memRead_out,
	output reg memWrite_out,
	output reg regWrite_out,
	output reg memToReg_out,
	output reg [63:0] programCounter_out,
	output reg [63:0] regData1_out,
	output reg [63:0] regData2_out,
	output reg [63:0] signExtend_out,
	output reg [10:0] ALUcontrol_out,
	output reg [4:0] registerRm_out,
	output reg [4:0] registerRn_out,
	output reg [4:0] writeReg_out
);

	always @(posedge CLOCK) begin

		ALUop_out <= ALUop_in;
		ALUsrc_out <= ALUsrc_in;


		isBranch_out <= isBranch_in;
		memRead_out <= memRead_in;
		memWrite_out <= memWrite_in;


		regWrite_out <= regWrite_in;
		memToReg_out <= memToReg_in;


		programCounter_out <= programCounter_in;
		regData1_out <= regData1_in;
		regData2_out <= regData2_in;


		signExtend_out <= signExtend_in;
		ALUcontrol_out <= ALUcontrol_in;
		writeReg_out <= writeReg_in;
		registerRm_out <= registerRm_in;
	    registerRn_out <= registerRn_in;
	end
endmodule
module IDEX
(
	input CLOCK,
	input [1:0] ALUop_in,
	input ALUsrc_in,
	input isBranch_in,
	input memRead_in,
	input memWrite_in,
	input regWrite_in,
	input memToReg_in,
	input [63:0] programCounter_in,
	input [63:0] regData1_in,
	input [63:0] regData2_in,
	input [63:0] signExtend_in,
	input [10:0] ALUcontrol_in,
	input [4:0] registerRm_in,
	input [4:0] registerRn_in,
	input [4:0] writeReg_in,
	output reg [1:0] ALUop_out,
	output reg ALUsrc_out,
	output reg isBranch_out,
	output reg memRead_out,
	output reg memWrite_out,
	output reg regWrite_out,
	output reg memToReg_out,
	output reg [63:0] programCounter_out,
	output reg [63:0] regData1_out,
	output reg [63:0] regData2_out,
	output reg [63:0] signExtend_out,
	output reg [10:0] ALUcontrol_out,
	output reg [4:0] registerRm_out,
	output reg [4:0] registerRn_out,
	output reg [4:0] writeReg_out
);


	always @(posedge CLOCK) begin

		ALUop_out <= ALUop_in;
		ALUsrc_out <= ALUsrc_in;


		isBranch_out <= isBranch_in;
		memRead_out <= memRead_in;
		memWrite_out <= memWrite_in;


		regWrite_out <= regWrite_in;
		memToReg_out <= memToReg_in;


		programCounter_out <= programCounter_in;
		regData1_out <= regData1_in;
		regData2_out <= regData2_in;


		signExtend_out <= signExtend_in;
		ALUcontrol_out <= ALUcontrol_in;
		writeReg_out <= writeReg_in;
		registerRm_out <= registerRm_in;
	    registerRn_out <= registerRn_in;
	end
endmodule