data/full_repos/permissive/14593708/data/alu/alu.v
1: b"%Error: data/full_repos/permissive/14593708/data/alu/alu.v:12: Cannot find file containing module: 'logic_and'\n    logic_and             and_0(a, b, logic_and_out);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14593708/data/alu,data/full_repos/permissive/14593708/logic_and\n             data/full_repos/permissive/14593708/data/alu,data/full_repos/permissive/14593708/logic_and.v\n             data/full_repos/permissive/14593708/data/alu,data/full_repos/permissive/14593708/logic_and.sv\n             logic_and\n             logic_and.v\n             logic_and.sv\n             obj_dir/logic_and\n             obj_dir/logic_and.v\n             obj_dir/logic_and.sv\n%Error: data/full_repos/permissive/14593708/data/alu/alu.v:13: Cannot find file containing module: 'logic_or'\n    logic_or              or_0(a, b, logic_or_out);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/14593708/data/alu/alu.v:14: Cannot find file containing module: 'arithmetic_adder'\n    arithmetic_adder#(32) adder_0(a, b, opcode[0], adder_out, carry);\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/14593708/data/alu/alu.v:16: Cannot find file containing module: 'multiplexor_2x1'\n    multiplexor_2x1 opcode_mux_0(opcode[0], logic_and_out,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/14593708/data/alu/alu.v:18: Cannot find file containing module: 'multiplexor_2x1'\n    multiplexor_2x1 opcode_mux_1(opcode[1], logic_out, adder_out, out);\n    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module alu(input[1:0]   opcode,
           input[31:0]  a,
           input[31:0]  b,
           output[31:0] out,
           output       carry);

    wire[31:0] logic_and_out;
    wire[31:0] logic_or_out;
    wire[31:0] logic_out;
    wire[31:0] adder_out;

    logic_and             and_0(a, b, logic_and_out);
    logic_or              or_0(a, b, logic_or_out);
    arithmetic_adder#(32) adder_0(a, b, opcode[0], adder_out, carry);

    multiplexor_2x1 opcode_mux_0(opcode[0], logic_and_out,
                                 logic_or_out, logic_out);
    multiplexor_2x1 opcode_mux_1(opcode[1], logic_out, adder_out, out);

endmodule
module alu(input[1:0]   opcode,
           input[31:0]  a,
           input[31:0]  b,
           output[31:0] out,
           output       carry);


    wire[31:0] logic_and_out;
    wire[31:0] logic_or_out;
    wire[31:0] logic_out;
    wire[31:0] adder_out;

    logic_and             and_0(a, b, logic_and_out);
    logic_or              or_0(a, b, logic_or_out);
    arithmetic_adder#(32) adder_0(a, b, opcode[0], adder_out, carry);

    multiplexor_2x1 opcode_mux_0(opcode[0], logic_and_out,
                                 logic_or_out, logic_out);
    multiplexor_2x1 opcode_mux_1(opcode[1], logic_out, adder_out, out);

endmodule