data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/synchronizer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/synchronizer.v:73: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'Synchronizer\'\nmodule Synchronizer(clk, nRST, en, IN, OUT);\n       ^~~~~~~~~~~~\n                                                                                             : ... Top module \'Synchronizer2\'\nmodule Synchronizer2(clk, nRST, en, IN, OUT);\n       ^~~~~~~~~~~~~\n                                                                                             : ... Top module \'Synchronizer3\'\nmodule Synchronizer3(clk, nRST, en, IN, OUT);\n       ^~~~~~~~~~~~~\n                                                                                             : ... Top module \'Synchronizer_set_en\'\nmodule Synchronizer_set_en(clk, nRST, en, IN, OUT);\n       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/synchronizer.v:147: Cannot find file containing module: \'DFF_set\'\n    DFF_set    #(.n(1)) SYNCH1(.clk(clk) , .nSET(nRST), .D(synchIn), .Q(interStage));\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl,data/full_repos/permissive/175070965/DFF_set\n             data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl,data/full_repos/permissive/175070965/DFF_set.v\n             data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl,data/full_repos/permissive/175070965/DFF_set.sv\n             DFF_set\n             DFF_set.v\n             DFF_set.sv\n             obj_dir/DFF_set\n             obj_dir/DFF_set.v\n             obj_dir/DFF_set.sv\n%Error: data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/synchronizer.v:148: Cannot find file containing module: \'DFF_set\'\n    DFF_set    #(.n(1)) SYNCH2(.clk(clk) , .nSET(nRST), .D(interStage), .Q(OUT));\n    ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/synchronizer.v:115: Cannot find file containing module: \'DFF_rst\'\n    DFF_rst     #(.n(1)) SYNCH1(.clk(clk) , .nRST(nRST), .D(synchIn), .Q(interStage));\n    ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/synchronizer.v:116: Cannot find file containing module: \'DFF_rst\'\n    DFF_rst     #(.n(1)) SYNCH2(.clk(clk) , .nRST(nRST), .D(interStage), .Q(OUT));\n    ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/synchronizer.v:84: Cannot find file containing module: \'DFF_rst\'\n    DFF_rst     #(.n(1)) SYNCH1(.clk(clk) , .nRST(nRST), .D(synchIn), .Q(interStage));\n    ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/synchronizer.v:85: Cannot find file containing module: \'DFF_rst\'\n    DFF_rst     #(.n(1)) SYNCH2(.clk(clk) , .nRST(nRST), .D(interStage), .Q(OUT));\n    ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/synchronizer.v:53: Cannot find file containing module: \'DFF_rst\'\n    DFF_rst    #(.n(1)) SYNCH1(.clk(clk) , .nRST(nRST), .D(synchIn), .Q(interStage));\n    ^~~~~~~\n%Error: data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/synchronizer.v:54: Cannot find file containing module: \'DFF_rst\'\n    DFF_rst    #(.n(1)) SYNCH2(.clk(clk) , .nRST(nRST), .D(interStage), .Q(OUT));\n    ^~~~~~~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module Synchronizer3(clk, nRST, en, IN, OUT);
    input wire IN;
    input wire en,clk,nRST;
    output wire OUT;

    wire    interStage;
    wire    synchIn;

    assign  synchIn = en ? IN : 1'b1;


    DFF_rst     #(.n(1)) SYNCH1(.clk(clk) , .nRST(nRST), .D(synchIn), .Q(interStage));
    DFF_rst     #(.n(1)) SYNCH2(.clk(clk) , .nRST(nRST), .D(interStage), .Q(OUT));
endmodule
module Synchronizer3(clk, nRST, en, IN, OUT);

    input wire IN;
    input wire en,clk,nRST;
    output wire OUT;

    wire    interStage;
    wire    synchIn;

    assign  synchIn = en ? IN : 1'b1;


    DFF_rst     #(.n(1)) SYNCH1(.clk(clk) , .nRST(nRST), .D(synchIn), .Q(interStage));
    DFF_rst     #(.n(1)) SYNCH2(.clk(clk) , .nRST(nRST), .D(interStage), .Q(OUT));
endmodule