data/full_repos/permissive/136794488/source/dff32.v
data/verilator_xmls/24559d71-dc30-4327-921b-0c7d52f47db4.xml
module dff32 (d,clk,clrn,q);
   input  [31:0] d;
   input         clk,clrn;
   output [31:0] q;
	
   reg [31:0]    q;
	
	initial
	begin
		q = 0;
	end
	
   always @ (negedge clrn or posedge clk)
      if (clrn == 0) begin
          q <= 0;
      end else begin
          q <= d;
      end
endmodule
module dff32 (d,clk,clrn,q);

   input  [31:0] d;
   input         clk,clrn;
   output [31:0] q;
	
   reg [31:0]    q;
	
	initial
	begin
		q = 0;
	end
	
   always @ (negedge clrn or posedge clk)
      if (clrn == 0) begin
          q <= 0;
      end else begin
          q <= d;
      end
endmodule