data/full_repos/permissive/127311496/src/v/Cache/DCache.v
 line:112: before: "="
1: b"%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:136: Cannot find file containing module: 'DCacheTag'\n DCacheTag cacheTag(.clka(clk), .wea(tagWe),\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/DCacheTag\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/DCacheTag.v\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/DCacheTag.sv\n             DCacheTag\n             DCacheTag.v\n             DCacheTag.sv\n             obj_dir/DCacheTag\n             obj_dir/DCacheTag.v\n             obj_dir/DCacheTag.sv\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:138: Cannot find file containing module: 'CacheLRUBit'\n CacheLRUBit cacheLRU(.clk(clk), .req(req_reg), .addr(tagAddr), .hit({hit1, hit0}), .flag(LRUBit));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:60: Cannot find file containing module: 'DCacheData'\n DCacheData way0Data(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:65: Cannot find file containing module: 'DCacheData'\n DCacheData way1Data(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:88: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceTypeCross (.clki(clkCPU), .clko(clkDDR), .i(replaceType_CPU), .o(replaceType_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:89: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceIndexCross[9:0](.clki(clkCPU), .clko(clkDDR), .i(replaceIndex_CPU), .o(replaceIndex_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:90: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) oldTagCross[16:0](.clki(clkCPU), .clko(clkDDR), .i(oldTag_CPU), .o(oldTag_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:91: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) newTagCross[16:0](.clki(clkCPU), .clko(clkDDR), .i(newTag_CPU), .o(newTag_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:93: Cannot find file containing module: 'AsyncHandshake'\n AsyncHandshake #(.STB_FREQ(1000 / CLKCPU_PERIOD), .ACK_FREQ(1000 / CLKDDR_PERIOD))\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:97: Cannot find file containing module: 'AsyncHandshake'\n AsyncHandshake #(.STB_FREQ(1000 / CLKDDR_PERIOD), .ACK_FREQ(1000 / CLKCPU_PERIOD))\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module DCacheFSM_CPU(
	input clk, input rst,

	input [31:0] addrIn, input req, input write,
	output [31:0] dataOut, output stall, input invalidateReq,

	output [1:0] writeReject, input [31:0] douta0, input [31:0] douta1,

	output reg replaceStb = 0, output reg replaceType = 0, input replaceAck, input completeStb,
	output reg [9:0] replaceIndex = 0, output reg [16:0] oldTag = 0, output reg [16:0] newTag = 0
);
	reg [16:0] requestedTag = 0;
	reg req_reg = 0;
	reg write_reg = 0;
	reg invalidateReq_reg = 0;
	reg wayInterleave = 0;
		
	wire [17:0] tag0, tag1;
	wire LRUBit;
	wire tagWSel;
	
	reg [35:0] tagDin;
	reg [1:0] tagWe;
	
	wire invalidHit0 = (tag0[16:0] == requestedTag);
	wire invalidHit1 = (tag1[16:0] == requestedTag);
	wire hit0 = invalidHit0 & (write_reg | tag0[17]);
	wire hit1 = invalidHit1 & (write_reg | tag1[17]);
	assign dataOut = (hit1 ^ wayInterleave)? douta1: douta0;
	
	reg [8:0] tagAddr = 0;
	
	DCacheTag cacheTag(.clka(clk), .wea(tagWe),
		.addra(tagWSel? tagAddr: addrIn[14:6]), .dina(tagDin), .douta({tag1, tag0}));
	CacheLRUBit cacheLRU(.clk(clk), .req(req_reg), .addr(tagAddr), .hit({hit1, hit0}), .flag(LRUBit));
	
	wire [1:0] _writeReject;
	assign _writeReject[0] = ~invalidHit0 & write_reg;
	assign _writeReject[1] = ~invalidHit1 & write_reg;
	assign writeReject = wayInterleave? {_writeReject[0], _writeReject[1]}: _writeReject;
	
	localparam STATE_IDLE = 2'h0;
	localparam STATE_WAIT = 2'h1;
	localparam STATE_INVALIDATE = 2'h2;
	reg [1:0] state = STATE_IDLE;
	
	wire reqMiss = req_reg & ~(hit0 | hit1);
	wire invHit = invalidateReq_reg & (invalidHit0 | invalidHit1);
	assign stall = reqMiss | invHit | (state != STATE_IDLE);
	assign tagWSel = rst | (state != STATE_IDLE);
	
	always @ (posedge clk)
	if(rst)
	begin
		tagAddr <= tagAddr + 1'b1;
		requestedTag <= 17'h0;
		wayInterleave <= 1'b0;
		req_reg <= 1'b0;
		write_reg <= 1'b0;
	end
	else if(~stall)
	begin
		tagAddr <= addrIn[14:6];
		wayInterleave <= addrIn[5];
		requestedTag <= addrIn[31:15];
		req_reg <= req;
		write_reg <= write;
	end
	
	always @ (posedge clk)
	if(rst | stall)
		invalidateReq_reg <= 1'b0;
	else
		invalidateReq_reg <= invalidateReq;
	
	always @ (posedge clk)
	if(rst)
		state <= STATE_IDLE;
	else
	case(state)
	STATE_IDLE: begin
		if(reqMiss | invHit)
		begin
			state <= reqMiss? STATE_WAIT: STATE_INVALIDATE;
			replaceType <= reqMiss? ~write_reg: 1'b0;
			replaceStb <= 1'b1;
			replaceIndex[8:0] <= tagAddr;
			oldTag <= (invalidHit0 | invalidHit1)? requestedTag: (LRUBit? tag1[16:0]: tag0[16:0]);
			newTag <= requestedTag;
			replaceIndex[9] <= (invalidHit0 | invalidHit1)? invalidHit1: LRUBit;
		end
	end
	STATE_WAIT: begin
		replaceStb <= 1'b0;
		if((~replaceType & replaceAck) | completeStb)
			state <= STATE_IDLE;
	end
	STATE_INVALIDATE: begin
		if(replaceAck)
			state <= STATE_IDLE;
		replaceStb <= 1'b0;
	end
	default: state <= STATE_IDLE;
	endcase
	
	always @*
	case(state)
	STATE_WAIT: begin
		tagDin <={2{~write_reg, requestedTag}};
		tagWe <= {replaceIndex[9], ~replaceIndex[9]};
	end
	STATE_INVALIDATE: begin
		tagDin <= {tag1, tag0};
		tagWe <= 2'b00;
	end
	STATE_IDLE: begin
		tagWe <= {2{rst}};
		tagDin <= 36'h000040000;
	end
	default: begin
		tagWe <= {2{rst}};
		tagDin <= 36'h000040000;
	end
	endcase

endmodule
module DCacheFSM_CPU(
	input clk, input rst,

	input [31:0] addrIn, input req, input write,
	output [31:0] dataOut, output stall, input invalidateReq,

	output [1:0] writeReject, input [31:0] douta0, input [31:0] douta1,

	output reg replaceStb = 0, output reg replaceType = 0, input replaceAck, input completeStb,
	output reg [9:0] replaceIndex = 0, output reg [16:0] oldTag = 0, output reg [16:0] newTag = 0
);

	reg [16:0] requestedTag = 0;
	reg req_reg = 0;
	reg write_reg = 0;
	reg invalidateReq_reg = 0;
	reg wayInterleave = 0;
		
	wire [17:0] tag0, tag1;
	wire LRUBit;
	wire tagWSel;
	
	reg [35:0] tagDin;
	reg [1:0] tagWe;
	
	wire invalidHit0 = (tag0[16:0] == requestedTag);
	wire invalidHit1 = (tag1[16:0] == requestedTag);
	wire hit0 = invalidHit0 & (write_reg | tag0[17]);
	wire hit1 = invalidHit1 & (write_reg | tag1[17]);
	assign dataOut = (hit1 ^ wayInterleave)? douta1: douta0;
	
	reg [8:0] tagAddr = 0;
	
	DCacheTag cacheTag(.clka(clk), .wea(tagWe),
		.addra(tagWSel? tagAddr: addrIn[14:6]), .dina(tagDin), .douta({tag1, tag0}));
	CacheLRUBit cacheLRU(.clk(clk), .req(req_reg), .addr(tagAddr), .hit({hit1, hit0}), .flag(LRUBit));
	
	wire [1:0] _writeReject;
	assign _writeReject[0] = ~invalidHit0 & write_reg;
	assign _writeReject[1] = ~invalidHit1 & write_reg;
	assign writeReject = wayInterleave? {_writeReject[0], _writeReject[1]}: _writeReject;
	
	localparam STATE_IDLE = 2'h0;
	localparam STATE_WAIT = 2'h1;
	localparam STATE_INVALIDATE = 2'h2;
	reg [1:0] state = STATE_IDLE;
	
	wire reqMiss = req_reg & ~(hit0 | hit1);
	wire invHit = invalidateReq_reg & (invalidHit0 | invalidHit1);
	assign stall = reqMiss | invHit | (state != STATE_IDLE);
	assign tagWSel = rst | (state != STATE_IDLE);
	
	always @ (posedge clk)
	if(rst)
	begin
		tagAddr <= tagAddr + 1'b1;
		requestedTag <= 17'h0;
		wayInterleave <= 1'b0;
		req_reg <= 1'b0;
		write_reg <= 1'b0;
	end
	else if(~stall)
	begin
		tagAddr <= addrIn[14:6];
		wayInterleave <= addrIn[5];
		requestedTag <= addrIn[31:15];
		req_reg <= req;
		write_reg <= write;
	end
	
	always @ (posedge clk)
	if(rst | stall)
		invalidateReq_reg <= 1'b0;
	else
		invalidateReq_reg <= invalidateReq;
	
	always @ (posedge clk)
	if(rst)
		state <= STATE_IDLE;
	else
	case(state)
	STATE_IDLE: begin
		if(reqMiss | invHit)
		begin
			state <= reqMiss? STATE_WAIT: STATE_INVALIDATE;
			replaceType <= reqMiss? ~write_reg: 1'b0;
			replaceStb <= 1'b1;
			replaceIndex[8:0] <= tagAddr;
			oldTag <= (invalidHit0 | invalidHit1)? requestedTag: (LRUBit? tag1[16:0]: tag0[16:0]);
			newTag <= requestedTag;
			replaceIndex[9] <= (invalidHit0 | invalidHit1)? invalidHit1: LRUBit;
		end
	end
	STATE_WAIT: begin
		replaceStb <= 1'b0;
		if((~replaceType & replaceAck) | completeStb)
			state <= STATE_IDLE;
	end
	STATE_INVALIDATE: begin
		if(replaceAck)
			state <= STATE_IDLE;
		replaceStb <= 1'b0;
	end
	default: state <= STATE_IDLE;
	endcase
	
	always @*
	case(state)
	STATE_WAIT: begin
		tagDin <={2{~write_reg, requestedTag}};
		tagWe <= {replaceIndex[9], ~replaceIndex[9]};
	end
	STATE_INVALIDATE: begin
		tagDin <= {tag1, tag0};
		tagWe <= 2'b00;
	end
	STATE_IDLE: begin
		tagWe <= {2{rst}};
		tagDin <= 36'h000040000;
	end
	default: begin
		tagWe <= {2{rst}};
		tagDin <= 36'h000040000;
	end
	endcase

endmodule