data/full_repos/permissive/168234415/A6_Processor_Hardware_Validation/Lab 6 Materials/basys3_single_cycle_mips_validation/clk_gen.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: 6\n        ... Looked in:\n             data/full_repos/permissive/168234415/A6_Processor_Hardware_Validation/Lab/6\n             data/full_repos/permissive/168234415/A6_Processor_Hardware_Validation/Lab/6.v\n             data/full_repos/permissive/168234415/A6_Processor_Hardware_Validation/Lab/6.sv\n             6\n             6.v\n             6.sv\n             obj_dir/6\n             obj_dir/6.v\n             obj_dir/6.sv\n%Error: Cannot find file containing module: Materials/basys3_single_cycle_mips_validation,data/full_repos/permissive/168234415\n%Error: Cannot find file containing module: data/full_repos/permissive/168234415/A6_Processor_Hardware_Validation/Lab\n%Error: Cannot find file containing module: Materials/basys3_single_cycle_mips_validation/clk_gen.v\n%Error: Exiting due to 4 error(s)\n'
module clk_gen (
        input  wire clk100MHz,
        input  wire rst,
        output reg  clk_4sec,
        output reg  clk_5KHz
    );

    integer count1, count2;

    always @ (posedge clk100MHz) begin
        if (rst) begin
            count1 = 0;
            count2 = 0;
            clk_5KHz = 0;
            clk_4sec = 0;
        end
        else begin
            if (count1 == 200000000) begin
                clk_4sec = ~clk_4sec;
                count1 = 0;
            end

            if (count2 == 10000) begin
                clk_5KHz = ~clk_5KHz;
                count2 = 0;
            end

            count1 = count1 + 1;
            count2 = count2 + 1;            
        end
    end

endmodule
module clk_gen (
        input  wire clk100MHz,
        input  wire rst,
        output reg  clk_4sec,
        output reg  clk_5KHz
    );


    integer count1, count2;

    always @ (posedge clk100MHz) begin
        if (rst) begin
            count1 = 0;
            count2 = 0;
            clk_5KHz = 0;
            clk_4sec = 0;
        end
        else begin
            if (count1 == 200000000) begin
                clk_4sec = ~clk_4sec;
                count1 = 0;
            end

            if (count2 == 10000) begin
                clk_5KHz = ~clk_5KHz;
                count2 = 0;
            end

            count1 = count1 + 1;
            count2 = count2 + 1;            
        end
    end

endmodule