data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v
1: b'%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:71: Cannot find include file: riscv_defs.v\n`include "riscv_defs.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205693645/src_v/riscv,data/full_repos/permissive/205693645/riscv_defs.v\n             data/full_repos/permissive/205693645/src_v/riscv,data/full_repos/permissive/205693645/riscv_defs.v.v\n             data/full_repos/permissive/205693645/src_v/riscv,data/full_repos/permissive/205693645/riscv_defs.v.sv\n             riscv_defs.v\n             riscv_defs.v.v\n             riscv_defs.v.sv\n             obj_dir/riscv_defs.v\n             obj_dir/riscv_defs.v.v\n             obj_dir/riscv_defs.v.sv\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:108: Define or directive not defined: \'`ALU_NONE\'\n    alu_func_r     = `ALU_NONE;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    alu_func_r     = `ALU_NONE;\n                              ^\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:113: Define or directive not defined: \'`ENUM_INST_ADD\'\n    if (opcode_instr_i[`ENUM_INST_ADD])  \n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:113: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    if (opcode_instr_i[`ENUM_INST_ADD])  \n                                     ^\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:115: Define or directive not defined: \'`ALU_ADD\'\n        alu_func_r     = `ALU_ADD;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:120: syntax error, unexpected else\n    else if (opcode_instr_i[`ENUM_INST_AND])  \n    ^~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:120: Define or directive not defined: \'`ENUM_INST_AND\'\n    else if (opcode_instr_i[`ENUM_INST_AND])  \n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:122: Define or directive not defined: \'`ALU_AND\'\n        alu_func_r     = `ALU_AND;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:127: Define or directive not defined: \'`ENUM_INST_OR\'\n    else if (opcode_instr_i[`ENUM_INST_OR])  \n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:129: Define or directive not defined: \'`ALU_OR\'\n        alu_func_r     = `ALU_OR;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:134: Define or directive not defined: \'`ENUM_INST_SLL\'\n    else if (opcode_instr_i[`ENUM_INST_SLL])  \n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:136: Define or directive not defined: \'`ALU_SHIFTL\'\n        alu_func_r     = `ALU_SHIFTL;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:141: Define or directive not defined: \'`ENUM_INST_SRA\'\n    else if (opcode_instr_i[`ENUM_INST_SRA])  \n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:143: Define or directive not defined: \'`ALU_SHIFTR_ARITH\'\n        alu_func_r     = `ALU_SHIFTR_ARITH;\n                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:148: Define or directive not defined: \'`ENUM_INST_SRL\'\n    else if (opcode_instr_i[`ENUM_INST_SRL])  \n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:150: Define or directive not defined: \'`ALU_SHIFTR\'\n        alu_func_r     = `ALU_SHIFTR;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:155: Define or directive not defined: \'`ENUM_INST_SUB\'\n    else if (opcode_instr_i[`ENUM_INST_SUB])  \n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:157: Define or directive not defined: \'`ALU_SUB\'\n        alu_func_r     = `ALU_SUB;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:162: Define or directive not defined: \'`ENUM_INST_XOR\'\n    else if (opcode_instr_i[`ENUM_INST_XOR])  \n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:164: Define or directive not defined: \'`ALU_XOR\'\n        alu_func_r     = `ALU_XOR;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:169: Define or directive not defined: \'`ENUM_INST_SLT\'\n    else if (opcode_instr_i[`ENUM_INST_SLT])  \n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:171: Define or directive not defined: \'`ALU_LESS_THAN_SIGNED\'\n        alu_func_r     = `ALU_LESS_THAN_SIGNED;\n                         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:176: Define or directive not defined: \'`ENUM_INST_SLTU\'\n    else if (opcode_instr_i[`ENUM_INST_SLTU])  \n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:178: Define or directive not defined: \'`ALU_LESS_THAN\'\n        alu_func_r     = `ALU_LESS_THAN;\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:183: Define or directive not defined: \'`ENUM_INST_ADDI\'\n    else if (opcode_instr_i[`ENUM_INST_ADDI])  \n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:185: Define or directive not defined: \'`ALU_ADD\'\n        alu_func_r     = `ALU_ADD;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:190: Define or directive not defined: \'`ENUM_INST_ANDI\'\n    else if (opcode_instr_i[`ENUM_INST_ANDI])  \n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:192: Define or directive not defined: \'`ALU_AND\'\n        alu_func_r     = `ALU_AND;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:197: Define or directive not defined: \'`ENUM_INST_SLTI\'\n    else if (opcode_instr_i[`ENUM_INST_SLTI])  \n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:199: Define or directive not defined: \'`ALU_LESS_THAN_SIGNED\'\n        alu_func_r     = `ALU_LESS_THAN_SIGNED;\n                         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:204: Define or directive not defined: \'`ENUM_INST_SLTIU\'\n    else if (opcode_instr_i[`ENUM_INST_SLTIU])  \n                            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:206: Define or directive not defined: \'`ALU_LESS_THAN\'\n        alu_func_r     = `ALU_LESS_THAN;\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:211: Define or directive not defined: \'`ENUM_INST_ORI\'\n    else if (opcode_instr_i[`ENUM_INST_ORI])  \n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:213: Define or directive not defined: \'`ALU_OR\'\n        alu_func_r     = `ALU_OR;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:218: Define or directive not defined: \'`ENUM_INST_XORI\'\n    else if (opcode_instr_i[`ENUM_INST_XORI])  \n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:220: Define or directive not defined: \'`ALU_XOR\'\n        alu_func_r     = `ALU_XOR;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:225: Define or directive not defined: \'`ENUM_INST_SLLI\'\n    else if (opcode_instr_i[`ENUM_INST_SLLI])  \n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:227: Define or directive not defined: \'`ALU_SHIFTL\'\n        alu_func_r     = `ALU_SHIFTL;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:232: Define or directive not defined: \'`ENUM_INST_SRLI\'\n    else if (opcode_instr_i[`ENUM_INST_SRLI])  \n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:234: Define or directive not defined: \'`ALU_SHIFTR\'\n        alu_func_r     = `ALU_SHIFTR;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:239: Define or directive not defined: \'`ENUM_INST_SRAI\'\n    else if (opcode_instr_i[`ENUM_INST_SRAI])  \n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:241: Define or directive not defined: \'`ALU_SHIFTR_ARITH\'\n        alu_func_r     = `ALU_SHIFTR_ARITH;\n                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:246: Define or directive not defined: \'`ENUM_INST_LUI\'\n    else if (opcode_instr_i[`ENUM_INST_LUI])  \n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:251: Define or directive not defined: \'`ENUM_INST_AUIPC\'\n    else if (opcode_instr_i[`ENUM_INST_AUIPC])  \n                            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:253: Define or directive not defined: \'`ALU_ADD\'\n        alu_func_r     = `ALU_ADD;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:258: Define or directive not defined: \'`ENUM_INST_JAL\'\n    else if (opcode_instr_i[`ENUM_INST_JAL] || opcode_instr_i[`ENUM_INST_JALR])  \n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:258: Define or directive not defined: \'`ENUM_INST_JALR\'\n    else if (opcode_instr_i[`ENUM_INST_JAL] || opcode_instr_i[`ENUM_INST_JALR])  \n                                                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:260: Define or directive not defined: \'`ALU_ADD\'\n        alu_func_r     = `ALU_ADD;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/205693645/src_v/riscv/riscv_exec.v:276: syntax error, unexpected begin\nbegin\n^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module riscv_exec
(

     input           clk_i
    ,input           rst_i
    ,input           opcode_valid_i
    ,input  [ 57:0]  opcode_instr_i
    ,input  [ 31:0]  opcode_opcode_i
    ,input  [ 31:0]  opcode_pc_i
    ,input  [  4:0]  opcode_rd_idx_i
    ,input  [  4:0]  opcode_ra_idx_i
    ,input  [  4:0]  opcode_rb_idx_i
    ,input  [ 31:0]  opcode_ra_operand_i
    ,input  [ 31:0]  opcode_rb_operand_i


    ,output          branch_request_o
    ,output [ 31:0]  branch_pc_o
    ,output [  4:0]  writeback_idx_o
    ,output          writeback_squash_o
    ,output [ 31:0]  writeback_value_o
    ,output          stall_o
);






`include "riscv_defs.v"




reg [4:0]   rd_x_q;




reg [31:0]  imm20_r;
reg [31:0]  imm12_r;
reg [31:0]  bimm_r;
reg [31:0]  jimm20_r;
reg [4:0]   shamt_r;
reg [31:0]  storeimm_r;

always @ *
begin
    imm20_r     = {opcode_opcode_i[31:12], 12'b0};
    imm12_r     = {{20{opcode_opcode_i[31]}}, opcode_opcode_i[31:20]};
    bimm_r      = {{19{opcode_opcode_i[31]}}, opcode_opcode_i[31], opcode_opcode_i[7], opcode_opcode_i[30:25], opcode_opcode_i[11:8], 1'b0};
    jimm20_r    = {{12{opcode_opcode_i[31]}}, opcode_opcode_i[19:12], opcode_opcode_i[20], opcode_opcode_i[30:25], opcode_opcode_i[24:21], 1'b0};
    storeimm_r  = {{20{opcode_opcode_i[31]}}, opcode_opcode_i[31:25], opcode_opcode_i[11:7]};
    shamt_r     = opcode_opcode_i[24:20];
end




reg [3:0]  alu_func_r;
reg [31:0] alu_input_a_r;
reg [31:0] alu_input_b_r;
reg        write_rd_r;

always @ *
begin
    alu_func_r     = `ALU_NONE;
    alu_input_a_r  = 32'b0;
    alu_input_b_r  = 32'b0;
    write_rd_r     = 1'b0;

    if (opcode_instr_i[`ENUM_INST_ADD])
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_AND])
    begin
        alu_func_r     = `ALU_AND;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_OR])
    begin
        alu_func_r     = `ALU_OR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLL])
    begin
        alu_func_r     = `ALU_SHIFTL;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SRA])
    begin
        alu_func_r     = `ALU_SHIFTR_ARITH;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SRL])
    begin
        alu_func_r     = `ALU_SHIFTR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SUB])
    begin
        alu_func_r     = `ALU_SUB;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_XOR])
    begin
        alu_func_r     = `ALU_XOR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLT])
    begin
        alu_func_r     = `ALU_LESS_THAN_SIGNED;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLTU])
    begin
        alu_func_r     = `ALU_LESS_THAN;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_ADDI])
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_ANDI])
    begin
        alu_func_r     = `ALU_AND;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLTI])
    begin
        alu_func_r     = `ALU_LESS_THAN_SIGNED;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLTIU])
    begin
        alu_func_r     = `ALU_LESS_THAN;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_ORI])
    begin
        alu_func_r     = `ALU_OR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_XORI])
    begin
        alu_func_r     = `ALU_XOR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLLI])
    begin
        alu_func_r     = `ALU_SHIFTL;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SRLI])
    begin
        alu_func_r     = `ALU_SHIFTR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SRAI])
    begin
        alu_func_r     = `ALU_SHIFTR_ARITH;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_LUI])
    begin
        alu_input_a_r  = imm20_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_AUIPC])
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_pc_i;
        alu_input_b_r  = imm20_r;
        write_rd_r     = 1'b1;
    end     
    else if (opcode_instr_i[`ENUM_INST_JAL] || opcode_instr_i[`ENUM_INST_JALR])
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_pc_i;
        alu_input_b_r  = 32'd4;
        write_rd_r     = 1'b1;
    end
end






function [0:0] less_than_signed;
    input  [31:0] x;
    input  [31:0] y;
    reg [31:0] v;
begin
    v = (x - y);
    if (x[31] != y[31])
        less_than_signed = x[31];
    else
        less_than_signed = v[31];
end
endfunction






function [0:0] greater_than_signed;
    input  [31:0] x;
    input  [31:0] y;
    reg [31:0] v;
begin
    v = (y - x);
    if (x[31] != y[31])
        greater_than_signed = y[31];
    else
        greater_than_signed = v[31];
end
endfunction




reg        branch_r;
reg [31:0] branch_target_r;

always @ *
begin
    branch_r        = 1'b0;


    branch_target_r = opcode_pc_i + bimm_r;

    if (opcode_instr_i[`ENUM_INST_JAL])
    begin
        branch_r        = 1'b1;
        branch_target_r = opcode_pc_i + jimm20_r;
    end
    else if (opcode_instr_i[`ENUM_INST_JALR])
    begin
        branch_r            = 1'b1;
        branch_target_r     = opcode_ra_operand_i + imm12_r;
        branch_target_r[0]  = 1'b0;
    end
    else if (opcode_instr_i[`ENUM_INST_BEQ])
        branch_r      = (opcode_ra_operand_i == opcode_rb_operand_i);
    else if (opcode_instr_i[`ENUM_INST_BNE])
        branch_r      = (opcode_ra_operand_i != opcode_rb_operand_i);
    else if (opcode_instr_i[`ENUM_INST_BLT])
        branch_r      = less_than_signed(opcode_ra_operand_i, opcode_rb_operand_i);
    else if (opcode_instr_i[`ENUM_INST_BGE])
        branch_r      = greater_than_signed(opcode_ra_operand_i,opcode_rb_operand_i) | (opcode_ra_operand_i == opcode_rb_operand_i);
    else if (opcode_instr_i[`ENUM_INST_BLTU])
        branch_r      = (opcode_ra_operand_i < opcode_rb_operand_i);
    else if (opcode_instr_i[`ENUM_INST_BGEU])
        branch_r      = (opcode_ra_operand_i >= opcode_rb_operand_i);
end

assign branch_request_o = branch_r && opcode_valid_i;
assign branch_pc_o      = branch_target_r;




always @ (posedge clk_i )
if (rst_i)
    rd_x_q       <= 5'b0;
else
begin
    if (opcode_valid_i && write_rd_r)
        rd_x_q   <= opcode_rd_idx_i;
    else
        rd_x_q   <= 5'b0;
end





wire [31:0]  alu_p_w;
riscv_alu
u_alu
(
    .alu_op_i(alu_func_r),
    .alu_a_i(alu_input_a_r),
    .alu_b_i(alu_input_b_r),
    .alu_p_o(alu_p_w)
);




reg [31:0] result_q;
always @ (posedge clk_i )
if (rst_i)
    result_q  <= 32'b0;
else
    result_q <= alu_p_w;

assign writeback_value_o  = result_q;




assign writeback_idx_o    = rd_x_q;
assign writeback_squash_o = 1'b0;
assign stall_o            = 1'b0;




`ifdef verilator
reg        v_dbg_valid_q;
reg [31:0] v_dbg_pc_q;

always @ (posedge clk_i )
if (rst_i)
begin
    v_dbg_valid_q  <= 1'b0;
    v_dbg_pc_q     <= 32'b0;
end
else
begin
    v_dbg_valid_q  <= opcode_valid_i;
    v_dbg_pc_q     <= opcode_pc_i;
end




function [0:0] get_valid;
begin
    get_valid = v_dbg_valid_q;
end
endfunction



function [31:0] get_pc;
begin
    get_pc = v_dbg_pc_q;
end
endfunction
`endif


endmodule
module riscv_exec
(

     input           clk_i
    ,input           rst_i
    ,input           opcode_valid_i
    ,input  [ 57:0]  opcode_instr_i
    ,input  [ 31:0]  opcode_opcode_i
    ,input  [ 31:0]  opcode_pc_i
    ,input  [  4:0]  opcode_rd_idx_i
    ,input  [  4:0]  opcode_ra_idx_i
    ,input  [  4:0]  opcode_rb_idx_i
    ,input  [ 31:0]  opcode_ra_operand_i
    ,input  [ 31:0]  opcode_rb_operand_i


    ,output          branch_request_o
    ,output [ 31:0]  branch_pc_o
    ,output [  4:0]  writeback_idx_o
    ,output          writeback_squash_o
    ,output [ 31:0]  writeback_value_o
    ,output          stall_o
);







`include "riscv_defs.v"




reg [4:0]   rd_x_q;




reg [31:0]  imm20_r;
reg [31:0]  imm12_r;
reg [31:0]  bimm_r;
reg [31:0]  jimm20_r;
reg [4:0]   shamt_r;
reg [31:0]  storeimm_r;

always @ *
begin
    imm20_r     = {opcode_opcode_i[31:12], 12'b0};
    imm12_r     = {{20{opcode_opcode_i[31]}}, opcode_opcode_i[31:20]};
    bimm_r      = {{19{opcode_opcode_i[31]}}, opcode_opcode_i[31], opcode_opcode_i[7], opcode_opcode_i[30:25], opcode_opcode_i[11:8], 1'b0};
    jimm20_r    = {{12{opcode_opcode_i[31]}}, opcode_opcode_i[19:12], opcode_opcode_i[20], opcode_opcode_i[30:25], opcode_opcode_i[24:21], 1'b0};
    storeimm_r  = {{20{opcode_opcode_i[31]}}, opcode_opcode_i[31:25], opcode_opcode_i[11:7]};
    shamt_r     = opcode_opcode_i[24:20];
end




reg [3:0]  alu_func_r;
reg [31:0] alu_input_a_r;
reg [31:0] alu_input_b_r;
reg        write_rd_r;

always @ *
begin
    alu_func_r     = `ALU_NONE;
    alu_input_a_r  = 32'b0;
    alu_input_b_r  = 32'b0;
    write_rd_r     = 1'b0;

    if (opcode_instr_i[`ENUM_INST_ADD])
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_AND])
    begin
        alu_func_r     = `ALU_AND;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_OR])
    begin
        alu_func_r     = `ALU_OR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLL])
    begin
        alu_func_r     = `ALU_SHIFTL;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SRA])
    begin
        alu_func_r     = `ALU_SHIFTR_ARITH;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SRL])
    begin
        alu_func_r     = `ALU_SHIFTR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SUB])
    begin
        alu_func_r     = `ALU_SUB;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_XOR])
    begin
        alu_func_r     = `ALU_XOR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLT])
    begin
        alu_func_r     = `ALU_LESS_THAN_SIGNED;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLTU])
    begin
        alu_func_r     = `ALU_LESS_THAN;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_ADDI])
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_ANDI])
    begin
        alu_func_r     = `ALU_AND;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLTI])
    begin
        alu_func_r     = `ALU_LESS_THAN_SIGNED;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLTIU])
    begin
        alu_func_r     = `ALU_LESS_THAN;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_ORI])
    begin
        alu_func_r     = `ALU_OR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_XORI])
    begin
        alu_func_r     = `ALU_XOR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SLLI])
    begin
        alu_func_r     = `ALU_SHIFTL;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SRLI])
    begin
        alu_func_r     = `ALU_SHIFTR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_SRAI])
    begin
        alu_func_r     = `ALU_SHIFTR_ARITH;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_LUI])
    begin
        alu_input_a_r  = imm20_r;
        write_rd_r     = 1'b1;
    end
    else if (opcode_instr_i[`ENUM_INST_AUIPC])
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_pc_i;
        alu_input_b_r  = imm20_r;
        write_rd_r     = 1'b1;
    end     
    else if (opcode_instr_i[`ENUM_INST_JAL] || opcode_instr_i[`ENUM_INST_JALR])
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_pc_i;
        alu_input_b_r  = 32'd4;
        write_rd_r     = 1'b1;
    end
end






function [0:0] less_than_signed;
    input  [31:0] x;
    input  [31:0] y;
    reg [31:0] v;
begin
    v = (x - y);
    if (x[31] != y[31])
        less_than_signed = x[31];
    else
        less_than_signed = v[31];
end
endfunction






function [0:0] greater_than_signed;
    input  [31:0] x;
    input  [31:0] y;
    reg [31:0] v;
begin
    v = (y - x);
    if (x[31] != y[31])
        greater_than_signed = y[31];
    else
        greater_than_signed = v[31];
end
endfunction




reg        branch_r;
reg [31:0] branch_target_r;

always @ *
begin
    branch_r        = 1'b0;


    branch_target_r = opcode_pc_i + bimm_r;

    if (opcode_instr_i[`ENUM_INST_JAL])
    begin
        branch_r        = 1'b1;
        branch_target_r = opcode_pc_i + jimm20_r;
    end
    else if (opcode_instr_i[`ENUM_INST_JALR])
    begin
        branch_r            = 1'b1;
        branch_target_r     = opcode_ra_operand_i + imm12_r;
        branch_target_r[0]  = 1'b0;
    end
    else if (opcode_instr_i[`ENUM_INST_BEQ])
        branch_r      = (opcode_ra_operand_i == opcode_rb_operand_i);
    else if (opcode_instr_i[`ENUM_INST_BNE])
        branch_r      = (opcode_ra_operand_i != opcode_rb_operand_i);
    else if (opcode_instr_i[`ENUM_INST_BLT])
        branch_r      = less_than_signed(opcode_ra_operand_i, opcode_rb_operand_i);
    else if (opcode_instr_i[`ENUM_INST_BGE])
        branch_r      = greater_than_signed(opcode_ra_operand_i,opcode_rb_operand_i) | (opcode_ra_operand_i == opcode_rb_operand_i);
    else if (opcode_instr_i[`ENUM_INST_BLTU])
        branch_r      = (opcode_ra_operand_i < opcode_rb_operand_i);
    else if (opcode_instr_i[`ENUM_INST_BGEU])
        branch_r      = (opcode_ra_operand_i >= opcode_rb_operand_i);
end

assign branch_request_o = branch_r && opcode_valid_i;
assign branch_pc_o      = branch_target_r;




always @ (posedge clk_i )
if (rst_i)
    rd_x_q       <= 5'b0;
else
begin
    if (opcode_valid_i && write_rd_r)
        rd_x_q   <= opcode_rd_idx_i;
    else
        rd_x_q   <= 5'b0;
end





wire [31:0]  alu_p_w;
riscv_alu
u_alu
(
    .alu_op_i(alu_func_r),
    .alu_a_i(alu_input_a_r),
    .alu_b_i(alu_input_b_r),
    .alu_p_o(alu_p_w)
);




reg [31:0] result_q;
always @ (posedge clk_i )
if (rst_i)
    result_q  <= 32'b0;
else
    result_q <= alu_p_w;

assign writeback_value_o  = result_q;




assign writeback_idx_o    = rd_x_q;
assign writeback_squash_o = 1'b0;
assign stall_o            = 1'b0;




`ifdef verilator
reg        v_dbg_valid_q;
reg [31:0] v_dbg_pc_q;

always @ (posedge clk_i )
if (rst_i)
begin
    v_dbg_valid_q  <= 1'b0;
    v_dbg_pc_q     <= 32'b0;
end
else
begin
    v_dbg_valid_q  <= opcode_valid_i;
    v_dbg_pc_q     <= opcode_pc_i;
end




function [0:0] get_valid;
begin
    get_valid = v_dbg_valid_q;
end
endfunction



function [31:0] get_pc;
begin
    get_pc = v_dbg_pc_q;
end
endfunction
`endif


endmodule