data/full_repos/permissive/154350027/rtl/tcpip/arp_resp.v
 line:52: before: "="
1: b'%Error: data/full_repos/permissive/154350027/rtl/tcpip/arp_resp.v:53: Unsupported: Replication to form \'logic[7:0]$[0:71]\' data type\n                                                                    : ... In instance arp_resp\n  {\n  ^\n%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/arp_resp.v:53: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 576 bits.\n                                                                            : ... In instance arp_resp\n  {\n  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/arp_resp.v:150: Operator EQ expects 10 bits on the RHS, but RHS\'s CONST \'7\'h47\' generates 7 bits.\n                                                                             : ... In instance arp_resp\n if(arp_send_cnt == 7\'d71)arp_ns = DONE;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/arp_resp.v:194: Bit extraction of array[71:0] requires 7 bit index, not 10 bits.\n                                                                             : ... In instance arp_resp\n txd <= resp[arp_send_cnt];\n            ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module arp_resp
  (
   input wire 	     rx_clk,
   input wire 	     ip_pkt_end,
   input wire [15:0] ip_prot_type,
   
   input wire 	     clk,
   input wire 	     rst_n,
   input wire 	     tx_busy,

   output reg 	     tx_en,
   output reg [7:0]  txd 
   );


  reg 		     arp_req_en;
  reg [1:0] 	     expand_cnt;
  always@(posedge rx_clk, negedge rst_n)
    if(!rst_n)
      arp_req_en <= 1'b0;
    else if(ip_pkt_end && ip_prot_type == 16'h0806)
      arp_req_en <= 1'b1;
    else if(expand_cnt == 2'b11)
      arp_req_en <= 1'b0;

  always@(posedge rx_clk, negedge rst_n)
    if(!rst_n)
      expand_cnt <= 2'b0;
    else if(ip_pkt_end && ip_prot_type == 16'h0806)
      expand_cnt <= expand_cnt + 1'b1;
    else if(expand_cnt != 2'b0)
      expand_cnt <= expand_cnt + 1'b1;

  reg 		     arp_req_en_dly1;
  reg 		     arp_req_en_dly2;
  wire 		     arp_req_en_rising;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      begin
	arp_req_en_dly1 <= 1'b0;
	arp_req_en_dly2 <= 1'b0;
      end
    else
      begin
	arp_req_en_dly1 <= arp_req_en;
	arp_req_en_dly2 <= arp_req_en_dly1;
      end

  assign arp_req_en_rising = arp_req_en_dly1 & ~arp_req_en_dly2;


  reg [7:0] resp [0:71] = 
  {
   8'h55, 8'h55, 8'h55, 8'h55, 8'h55, 8'h55, 8'h55, 8'hd5,
   8'h6c, 8'h62, 8'h6d, 8'h80, 8'h27, 8'h01,
   8'h00, 8'h0a, 8'h35, 8'h02, 8'h88, 8'h46,
   8'h08, 8'h06,
   8'h00, 8'h01,
   8'h08, 8'h00,
   8'h06, 8'h04,
   8'h00, 8'h02,
   8'h00, 8'h0a, 8'h35, 8'h02, 8'h88, 8'h46,
   8'hc0, 8'ha8, 8'h00, 8'hae,
   8'h6c, 8'h62, 8'h6d, 8'h80, 8'h27, 8'h01,
   8'hc0, 8'ha8, 8'h00, 8'haf,
   8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00,
   8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00,
   8'h00, 8'h00, 
   8'h43, 8'h50, 8'h76, 8'h14
   };














































  
  reg [2:0] arp_cs;
  reg [2:0] arp_ns;

  parameter IDLE  = 3'd0;
  parameter START = 3'd1;
  parameter WAIT  = 3'd2;
  parameter SEND  = 3'd3;



  parameter DONE  = 3'd4;
  
  reg [9:0] arp_send_cnt;

  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      arp_cs <= IDLE;
    else
      arp_cs <= arp_ns;

  always@(*)
    case(arp_cs)
      IDLE:
	if(arp_req_en_rising)arp_ns = START;
	else arp_ns = IDLE;
      START:
	arp_ns = WAIT;
      WAIT:
	if(!tx_busy)arp_ns = SEND;
	else arp_ns = WAIT;
      SEND:
	if(arp_send_cnt == 7'd71)arp_ns = DONE;
	else arp_ns = SEND;









      DONE:
	arp_ns = IDLE;
      default:
	arp_ns = IDLE;
    endcase

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      arp_send_cnt <= 10'd0;

    else if(arp_cs == SEND)
      arp_send_cnt <= arp_send_cnt + 1'b1;
    else
      arp_send_cnt <= 10'd0;








 
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      begin
	tx_en <= 1'b0;
	txd <= 8'b0;
      end
    else if(arp_cs == SEND)
      begin
	tx_en <= 1'b1;
	txd <= resp[arp_send_cnt];
      end





    else
      begin
	tx_en <= 1'b0;
	txd <= 8'b0;
      end
  
  
endmodule
module arp_resp
  (
   input wire 	     rx_clk,
   input wire 	     ip_pkt_end,
   input wire [15:0] ip_prot_type,
   
   input wire 	     clk,
   input wire 	     rst_n,
   input wire 	     tx_busy,

   output reg 	     tx_en,
   output reg [7:0]  txd 
   );



  reg 		     arp_req_en;
  reg [1:0] 	     expand_cnt;
  always@(posedge rx_clk, negedge rst_n)
    if(!rst_n)
      arp_req_en <= 1'b0;
    else if(ip_pkt_end && ip_prot_type == 16'h0806)
      arp_req_en <= 1'b1;
    else if(expand_cnt == 2'b11)
      arp_req_en <= 1'b0;

  always@(posedge rx_clk, negedge rst_n)
    if(!rst_n)
      expand_cnt <= 2'b0;
    else if(ip_pkt_end && ip_prot_type == 16'h0806)
      expand_cnt <= expand_cnt + 1'b1;
    else if(expand_cnt != 2'b0)
      expand_cnt <= expand_cnt + 1'b1;

  reg 		     arp_req_en_dly1;
  reg 		     arp_req_en_dly2;
  wire 		     arp_req_en_rising;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      begin
	arp_req_en_dly1 <= 1'b0;
	arp_req_en_dly2 <= 1'b0;
      end
    else
      begin
	arp_req_en_dly1 <= arp_req_en;
	arp_req_en_dly2 <= arp_req_en_dly1;
      end

  assign arp_req_en_rising = arp_req_en_dly1 & ~arp_req_en_dly2;


  reg [7:0] resp [0:71] = 
  {
   8'h55, 8'h55, 8'h55, 8'h55, 8'h55, 8'h55, 8'h55, 8'hd5,
   8'h6c, 8'h62, 8'h6d, 8'h80, 8'h27, 8'h01,
   8'h00, 8'h0a, 8'h35, 8'h02, 8'h88, 8'h46,
   8'h08, 8'h06,
   8'h00, 8'h01,
   8'h08, 8'h00,
   8'h06, 8'h04,
   8'h00, 8'h02,
   8'h00, 8'h0a, 8'h35, 8'h02, 8'h88, 8'h46,
   8'hc0, 8'ha8, 8'h00, 8'hae,
   8'h6c, 8'h62, 8'h6d, 8'h80, 8'h27, 8'h01,
   8'hc0, 8'ha8, 8'h00, 8'haf,
   8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00,
   8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00,
   8'h00, 8'h00, 
   8'h43, 8'h50, 8'h76, 8'h14
   };














































  
  reg [2:0] arp_cs;
  reg [2:0] arp_ns;

  parameter IDLE  = 3'd0;
  parameter START = 3'd1;
  parameter WAIT  = 3'd2;
  parameter SEND  = 3'd3;



  parameter DONE  = 3'd4;
  
  reg [9:0] arp_send_cnt;

  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      arp_cs <= IDLE;
    else
      arp_cs <= arp_ns;

  always@(*)
    case(arp_cs)
      IDLE:
	if(arp_req_en_rising)arp_ns = START;
	else arp_ns = IDLE;
      START:
	arp_ns = WAIT;
      WAIT:
	if(!tx_busy)arp_ns = SEND;
	else arp_ns = WAIT;
      SEND:
	if(arp_send_cnt == 7'd71)arp_ns = DONE;
	else arp_ns = SEND;









      DONE:
	arp_ns = IDLE;
      default:
	arp_ns = IDLE;
    endcase

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      arp_send_cnt <= 10'd0;

    else if(arp_cs == SEND)
      arp_send_cnt <= arp_send_cnt + 1'b1;
    else
      arp_send_cnt <= 10'd0;








 
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      begin
	tx_en <= 1'b0;
	txd <= 8'b0;
      end
    else if(arp_cs == SEND)
      begin
	tx_en <= 1'b1;
	txd <= resp[arp_send_cnt];
      end





    else
      begin
	tx_en <= 1'b0;
	txd <= 8'b0;
      end
  
  
endmodule