data/full_repos/permissive/121410129/7seg/7seg/NewClockGenerator.v
data/verilator_xmls/9007ccfe-92ab-41b9-bf4a-a4b1f2e0b9af.xml
module NewClockGenerator (clock, reset, newClock);

input wire clock, reset;
output reg newClock;

reg [2:0]counterClock;

always @ (posedge clock or posedge reset)
begin
	if (reset == 1)
		begin
			newClock <= 0;
			counterClock <= 0;
		end
	else
		begin
			counterClock <= counterClock + 3'b001;
			if (counterClock == 3'b000) newClock <= ~newClock;
		end
end
endmodule
module NewClockGenerator (clock, reset, newClock);


input wire clock, reset;
output reg newClock;

reg [2:0]counterClock;

always @ (posedge clock or posedge reset)
begin
	if (reset == 1)
		begin
			newClock <= 0;
			counterClock <= 0;
		end
	else
		begin
			counterClock <= counterClock + 3'b001;
			if (counterClock == 3'b000) newClock <= ~newClock;
		end
end
endmodule