data/full_repos/permissive/20016915/quartus/avgai/SRAM.v
data/verilator_xmls/452db98e-a091-45ed-a371-e9f3eabd8e77.xml
module SRAM(input clk, read, write, 
				input [7:0] X, Y, input [11:0] DATIN,
				output [11:0] DATOUT, output reg wAck,
				output reg [11:0] wDbg);
	parameter W = 200, H = 150;
	reg [11:0] mem[W*H-1:0];
	reg [11:0] DATOUTINV;


	assign DATOUT = ~DATOUTINV;





	always @(posedge clk) begin
		if (read)
			DATOUTINV <= mem[Y*W + X];
		else if (write) begin
			mem[Y*W + X] <= ~DATIN;
			wDbg <= DATIN;
			wAck <= 1;
		end else
			wAck <= 0;
	end
endmodule
module SRAM(input clk, read, write, 
				input [7:0] X, Y, input [11:0] DATIN,
				output [11:0] DATOUT, output reg wAck,
				output reg [11:0] wDbg);

	parameter W = 200, H = 150;
	reg [11:0] mem[W*H-1:0];
	reg [11:0] DATOUTINV;


	assign DATOUT = ~DATOUTINV;





	always @(posedge clk) begin
		if (read)
			DATOUTINV <= mem[Y*W + X];
		else if (write) begin
			mem[Y*W + X] <= ~DATIN;
			wDbg <= DATIN;
			wAck <= 1;
		end else
			wAck <= 0;
	end
endmodule