data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/DataExt.v
'utf-8' codec can't decode byte 0xb2 in position 1363: invalid start byte
1: b'%Error: data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/DataExt.v:29: Cannot find include file: Parameters.v\n`include "Parameters.v"     \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog,data/full_repos/permissive/175780824/Parameters.v\n             data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog,data/full_repos/permissive/175780824/Parameters.v.v\n             data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog,data/full_repos/permissive/175780824/Parameters.v.sv\n             Parameters.v\n             Parameters.v.v\n             Parameters.v.sv\n             obj_dir/Parameters.v\n             obj_dir/Parameters.v.v\n             obj_dir/Parameters.v.sv\n%Error: Exiting due to 1 error(s)\n'
module DataExt(
    input wire [31:0] IN,
    input wire [1:0] ADDR,
    input wire [2:0] WE3,
    output reg [31:0] OUT
    );
`include "Parameters.v"    
    wire [31:0] LB_IN;
    wire [31:0] LH_IN;
    assign LB_IN = (IN >> (ADDR * 32'h08)) & 32'h000000ff;
    assign LH_IN = (IN >> (ADDR * 32'h08)) & 32'h0000ffff;
    always @(*)
    begin
        case(WE3)
            LB:
                begin
                    OUT[7:0]<=LB_IN[7:0];
                    OUT[31:8]<={24{LB_IN[7]}};
                end
            LH:
                begin
                    OUT[15:0]<=LH_IN[15:0];
                    OUT[31:16]<={16{LH_IN[15]}};
                end
            LW:
                begin
                    OUT<=IN;
                end
            LBU:
                begin
                    OUT[7:0]<=LB_IN[7:0];
                    OUT[31:8]<=24'b0;
                end
            LHU:
                begin
                    OUT[15:0]<=LH_IN[15:0];
                    OUT[31:16]<=16'b0;
                end
            default:       
                begin

                end
        endcase
    end
    
endmodule
module DataExt(
    input wire [31:0] IN,
    input wire [1:0] ADDR,
    input wire [2:0] WE3,
    output reg [31:0] OUT
    );

`include "Parameters.v"    
    wire [31:0] LB_IN;
    wire [31:0] LH_IN;
    assign LB_IN = (IN >> (ADDR * 32'h08)) & 32'h000000ff;
    assign LH_IN = (IN >> (ADDR * 32'h08)) & 32'h0000ffff;
    always @(*)
    begin
        case(WE3)
            LB:
                begin
                    OUT[7:0]<=LB_IN[7:0];
                    OUT[31:8]<={24{LB_IN[7]}};
                end
            LH:
                begin
                    OUT[15:0]<=LH_IN[15:0];
                    OUT[31:16]<={16{LH_IN[15]}};
                end
            LW:
                begin
                    OUT<=IN;
                end
            LBU:
                begin
                    OUT[7:0]<=LB_IN[7:0];
                    OUT[31:8]<=24'b0;
                end
            LHU:
                begin
                    OUT[15:0]<=LH_IN[15:0];
                    OUT[31:16]<=16'b0;
                end
            default:       
                begin

                end
        endcase
    end
    
endmodule