data/full_repos/permissive/195330302/ScreamAtSnake/score_to_display.v
1: b'%Warning-WIDTH: data/full_repos/permissive/195330302/ScreamAtSnake/score_to_display.v:134: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'29\'h0\' generates 29 bits.\n                                                                                         : ... In instance score_to_display.decoder_0\n   default: pixels[29:0]  = 29\'b0;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/195330302/ScreamAtSnake/score_to_display.v:12: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                                        : ... In instance score_to_display\n   value_2 <= (score_input / 100) % 10;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/195330302/ScreamAtSnake/score_to_display.v:13: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                                        : ... In instance score_to_display\n   value_1 <= (score_input / 10) % 10;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/195330302/ScreamAtSnake/score_to_display.v:14: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                                        : ... In instance score_to_display\n   value_0 <= score_input % 10 ;\n           ^~\n%Error: Exiting due to 4 warning(s)\n'
module score_to_display(
    output [89:0] score_display,
    input [7:0] score_input
);

	wire [29:0] digit_2, digit_1, digit_0;
	reg [3:0] value_2, value_1, value_0;
	

	always @(*)
	begin
		 value_2 <= (score_input / 100) % 10;
		 value_1 <= (score_input / 10) % 10;
		 value_0 <= score_input % 10 ;
	end


	digit_decoder decoder_2 (
		 .OUT(digit_2),
		 .IN(value_2)
	);

	digit_decoder decoder_1 (
		 .OUT(digit_1),
		 .IN(value_1)
	);

	digit_decoder decoder_0 (
		 .OUT(digit_0),
		 .IN(value_0)
	);


	assign score_display = {digit_0, digit_1, digit_2};

endmodule
module score_to_display(
    output [89:0] score_display,
    input [7:0] score_input
);


	wire [29:0] digit_2, digit_1, digit_0;
	reg [3:0] value_2, value_1, value_0;
	

	always @(*)
	begin
		 value_2 <= (score_input / 100) % 10;
		 value_1 <= (score_input / 10) % 10;
		 value_0 <= score_input % 10 ;
	end


	digit_decoder decoder_2 (
		 .OUT(digit_2),
		 .IN(value_2)
	);

	digit_decoder decoder_1 (
		 .OUT(digit_1),
		 .IN(value_1)
	);

	digit_decoder decoder_0 (
		 .OUT(digit_0),
		 .IN(value_0)
	);


	assign score_display = {digit_0, digit_1, digit_2};

endmodule