data/full_repos/permissive/193753641/subbytes.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193753641/subbytes.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #10 res[i+:8]=term;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/193753641/subbytes.v:35: Cannot find file containing module: \'substitute\'\nsubstitute S(temp,term);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193753641,data/full_repos/permissive/193753641/substitute\n             data/full_repos/permissive/193753641,data/full_repos/permissive/193753641/substitute.v\n             data/full_repos/permissive/193753641,data/full_repos/permissive/193753641/substitute.sv\n             substitute\n             substitute.v\n             substitute.sv\n             obj_dir/substitute\n             obj_dir/substitute.v\n             obj_dir/substitute.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module subbytes(a,res);
input [127:0] a;
output reg [127:0] res;


reg [7:0] temp;
reg [7:0] term;
integer i;
always@(*) begin
	for(i=0;i<32;i=i+8) begin
		temp=a[i+:8];
		#10 res[i+:8]=term;
	end
end
substitute S(temp,term);
endmodule
module subbytes(a,res);

input [127:0] a;
output reg [127:0] res;


reg [7:0] temp;
reg [7:0] term;
integer i;
always@(*) begin
	for(i=0;i<32;i=i+8) begin
		temp=a[i+:8];
		#10 res[i+:8]=term;
	end
end
substitute S(temp,term);
endmodule