data/full_repos/permissive/131358616/test/uart_tx_tb.v
 line:46: before: "("
1: b'%Error: data/full_repos/permissive/131358616/test/uart_tx_tb.v:35: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,uart_tx);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/uart_tx_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\nalways #(clk_pulse_width/2) clk = !clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/131358616/test/uart_tx_tb.v:43: Unsupported or unknown PLI call: $monitor\n $monitor("Time %d", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/uart_tx_tb.v:46: syntax error, unexpected \'@\'\n repeat (5) @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/131358616/test/uart_tx_tb.v:54: Unsupported: wait statements\n wait( rst_n );\n ^~~~\n%Error: data/full_repos/permissive/131358616/test/uart_tx_tb.v:55: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/131358616/test/uart_tx_tb.v:56: Unsupported or unknown PLI call: $monitor\n $monitor("[Time %d]: Started testbench", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/uart_tx_tb.v:61: syntax error, unexpected \'@\'\n repeat (10) @(negedge clk);\n             ^\n%Error: data/full_repos/permissive/131358616/test/uart_tx_tb.v:64: Unsupported: wait statements\n wait ( !busy );\n ^~~~\n%Error: data/full_repos/permissive/131358616/test/uart_tx_tb.v:65: syntax error, unexpected \'@\'\n repeat (100) @(negedge clk);\n              ^\n%Error: Exiting due to 9 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_tx_tb;

reg clk, rst_n;
reg start;
reg [7:0] data;
wire tx, busy;

localparam clock_frequency = 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

uart_tx uart_tx(
	.rst_n(rst_n),
	.clk(clk),
	.start(start),
	.data(data),
	.tx(tx),
	.busy(busy)
);


initial begin

    $dumpvars(0,uart_tx);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	start = 0;
	data = 8'h00;
	wait( rst_n );
	@(negedge clk);
	$monitor("[Time %d]: Started testbench", $time);

	data = 8'b10101010;
	start = 1;
	
	repeat (10) @(negedge clk);
	start = 0;

	wait ( !busy );
	repeat (100) @(negedge clk);
	$finish;
end

endmodule
module uart_tx_tb;


reg clk, rst_n;
reg start;
reg [7:0] data;
wire tx, busy;

localparam clock_frequency = 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

uart_tx uart_tx(
	.rst_n(rst_n),
	.clk(clk),
	.start(start),
	.data(data),
	.tx(tx),
	.busy(busy)
);


initial begin

    $dumpvars(0,uart_tx);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	start = 0;
	data = 8'h00;
	wait( rst_n );
	@(negedge clk);
	$monitor("[Time %d]: Started testbench", $time);

	data = 8'b10101010;
	start = 1;
	
	repeat (10) @(negedge clk);
	start = 0;

	wait ( !busy );
	repeat (100) @(negedge clk);
	$finish;
end

endmodule