data/full_repos/permissive/157005262/verilog/traffic.v
data/verilator_xmls/0f3a6b3b-4432-429f-a518-4781c5466174.xml
module traffic(input wire  clk,
               input wire  go,
               output wire red,
               output wire yellow,
               output wire green);

endmodule
module traffic(input wire  clk,
               input wire  go,
               output wire red,
               output wire yellow,
               output wire green);


endmodule