data/full_repos/permissive/21051978/final/src/pipe3.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe3.v:13: Little bit endian vector: MSB < LSB of bit range: 0:127\n input [0:127] dataOut_in;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe3.v:14: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] wbyteen_in;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe3.v:16: Little bit endian vector: MSB < LSB of bit range: 0:4\n input [0:4] rwraddrd_in;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe3.v:18: Little bit endian vector: MSB < LSB of bit range: 0:127\n input [0:127] aluOut_in;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe3.v:19: Little bit endian vector: MSB < LSB of bit range: 0:31\n input [0:31] instruction_in;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe3.v:25: Little bit endian vector: MSB < LSB of bit range: 0:127\n output [0:127] dataOut_out;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe3.v:26: Little bit endian vector: MSB < LSB of bit range: 0:15\n output [0:15] wbyteen_out;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe3.v:28: Little bit endian vector: MSB < LSB of bit range: 0:15\n output [0:15] rwraddrd_out;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe3.v:30: Little bit endian vector: MSB < LSB of bit range: 0:127\n output [0:127] aluOut_out;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe3.v:31: Little bit endian vector: MSB < LSB of bit range: 0:31\n output [0:31] instruction_out;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/final/src/pipe3.v:49: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                        : ... In instance pipe3\n   rwraddrd_out<=5\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/21051978/final/src/pipe3.v:59: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'rwraddrd_in\' generates 5 bits.\n                                                                        : ... In instance pipe3\n   rwraddrd_out<=rwraddrd_in;\n               ^~\n%Error: Exiting due to 12 warning(s)\n'
module pipe3(dataOut_in, dataOut_out, wbyteen_in, wbyteen_out, 
		 regwren_in, regwren_out, rwraddrd_in, rwraddrd_out, 
		 reginmuxop_in, reginmuxop_out, aluOut_in, aluOut_out,
		 instruction_in, instruction_out, clk, reset);
	

	input [0:127] dataOut_in;
	input [0:15] wbyteen_in;
	input regwren_in;
	input [0:4] rwraddrd_in;
	input reginmuxop_in;
	input [0:127] aluOut_in;
	input [0:31] instruction_in;


	input clk, reset;
	

	output [0:127] dataOut_out;
	output [0:15] wbyteen_out;
	output regwren_out;
	output [0:15] rwraddrd_out;
	output reginmuxop_out;
	output [0:127] aluOut_out;
	output [0:31] instruction_out;
	

	reg [0:127] dataOut_out;
	reg [0:15] wbyteen_out;
	reg regwren_out;
	reg [0:4] rwraddrd_out;
	reg reginmuxop_out;
	reg [0:127] aluOut_out;
	reg [0:31] instruction_out;
	
	always @ (posedge clk)
		begin
		if (reset == 1'b1)
			begin
			dataOut_out<=128'b0;
			wbyteen_out<=16'b0;
			regwren_out<=1'b0;
			rwraddrd_out<=5'b0;
			reginmuxop_out<=1'b0;
			aluOut_out<=128'b0;
			instruction_out<=32'b0;
			end
		else
			begin
			dataOut_out<=dataOut_in;
			wbyteen_out<=wbyteen_in;
			regwren_out<=regwren_in;
			rwraddrd_out<=rwraddrd_in;
			reginmuxop_out<=reginmuxop_in;
			aluOut_out<=aluOut_in;
			instruction_out<=instruction_in;
			end
		end

endmodule
module pipe3(dataOut_in, dataOut_out, wbyteen_in, wbyteen_out, 
		 regwren_in, regwren_out, rwraddrd_in, rwraddrd_out, 
		 reginmuxop_in, reginmuxop_out, aluOut_in, aluOut_out,
		 instruction_in, instruction_out, clk, reset);

	

	input [0:127] dataOut_in;
	input [0:15] wbyteen_in;
	input regwren_in;
	input [0:4] rwraddrd_in;
	input reginmuxop_in;
	input [0:127] aluOut_in;
	input [0:31] instruction_in;


	input clk, reset;
	

	output [0:127] dataOut_out;
	output [0:15] wbyteen_out;
	output regwren_out;
	output [0:15] rwraddrd_out;
	output reginmuxop_out;
	output [0:127] aluOut_out;
	output [0:31] instruction_out;
	

	reg [0:127] dataOut_out;
	reg [0:15] wbyteen_out;
	reg regwren_out;
	reg [0:4] rwraddrd_out;
	reg reginmuxop_out;
	reg [0:127] aluOut_out;
	reg [0:31] instruction_out;
	
	always @ (posedge clk)
		begin
		if (reset == 1'b1)
			begin
			dataOut_out<=128'b0;
			wbyteen_out<=16'b0;
			regwren_out<=1'b0;
			rwraddrd_out<=5'b0;
			reginmuxop_out<=1'b0;
			aluOut_out<=128'b0;
			instruction_out<=32'b0;
			end
		else
			begin
			dataOut_out<=dataOut_in;
			wbyteen_out<=wbyteen_in;
			regwren_out<=regwren_in;
			rwraddrd_out<=rwraddrd_in;
			reginmuxop_out<=reginmuxop_in;
			aluOut_out<=aluOut_in;
			instruction_out<=instruction_in;
			end
		end

endmodule