data/full_repos/permissive/143278/ivltests/br955.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br955.v:92: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br955.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br955.v:89: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'lp\' generates 32 bits.\n                                                                     : ... In instance top\n      sel = lp;\n          ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_n_to_1
  #(
    parameter sel_w = 4,
    parameter n_inputs = 2**sel_w
  )
  (
    input [n_inputs-1:0] inputs_i,
    input [sel_w-1:0] sel_i,
    output output_o
  );

  genvar i,j;
  generate
  if(sel_w == 1) begin
    mux_2_to_1 mux_simple
      (
        .sel_i(sel_i),
        .dat_i(inputs_i),
        .dat_o(output_o)
      );
  end else begin
    wire [n_inputs-2:0] inter_w;

    for(i=0; i<sel_w; i=i+1) begin : SELECT_STAGE
      if(i==0) begin
        for(j=0; j<n_inputs/2; j=j+1) begin : FIRST_STAGE
          mux_2_to_1 mux_first_stage
            (
              .sel_i(sel_i[i]),
              .dat_i(inputs_i[2*j+1:2*j]),
              .dat_o(inter_w[j])
            );
        end
      end else begin
        for(j=0; j<(n_inputs/(2**(i+1))); j=j+1) begin : INTERMEDIARY_STAGE
          mux_2_to_1 mux_intermediary_stages
            (
              .sel_i(sel_i[i]),
              .dat_i(inter_w[ (n_inputs/(2**(i-1)))*((2**(i-1))-1) + 2*j + 1 : (n_inputs/(2**(i-1)))*((2**(i-1))-1) + 2*j ]),
              .dat_o(inter_w[ (n_inputs/(2**i))*((2**i)-1) + j ])
            );
        end
      end
    end
    assign output_o = inter_w[ (n_inputs/(2**(sel_w-1)))*((2**(sel_w-1))-1) ];
  end
  endgenerate
endmodule
module mux_n_to_1
  #(
    parameter sel_w = 4,
    parameter n_inputs = 2**sel_w
  )
  (
    input [n_inputs-1:0] inputs_i,
    input [sel_w-1:0] sel_i,
    output output_o
  );


  genvar i,j;
  generate
  if(sel_w == 1) begin
    mux_2_to_1 mux_simple
      (
        .sel_i(sel_i),
        .dat_i(inputs_i),
        .dat_o(output_o)
      );
  end else begin
    wire [n_inputs-2:0] inter_w;

    for(i=0; i<sel_w; i=i+1) begin : SELECT_STAGE
      if(i==0) begin
        for(j=0; j<n_inputs/2; j=j+1) begin : FIRST_STAGE
          mux_2_to_1 mux_first_stage
            (
              .sel_i(sel_i[i]),
              .dat_i(inputs_i[2*j+1:2*j]),
              .dat_o(inter_w[j])
            );
        end
      end else begin
        for(j=0; j<(n_inputs/(2**(i+1))); j=j+1) begin : INTERMEDIARY_STAGE
          mux_2_to_1 mux_intermediary_stages
            (
              .sel_i(sel_i[i]),
              .dat_i(inter_w[ (n_inputs/(2**(i-1)))*((2**(i-1))-1) + 2*j + 1 : (n_inputs/(2**(i-1)))*((2**(i-1))-1) + 2*j ]),
              .dat_o(inter_w[ (n_inputs/(2**i))*((2**i)-1) + j ])
            );
        end
      end
    end
    assign output_o = inter_w[ (n_inputs/(2**(sel_w-1)))*((2**(sel_w-1))-1) ];
  end
  endgenerate
endmodule