data/full_repos/permissive/160066183/verilog/act.v
 line:14: before: ","
1: b"%Error: data/full_repos/permissive/160066183/verilog/act.v:14: syntax error, unexpected ','\n        for(k=0; k <n,k=k+1)\n                     ^\n%Error: data/full_repos/permissive/160066183/verilog/act.v:19: syntax error, unexpected '=', expecting IDENTIFIER\n        carryout =C[n];\n                 ^\n%Error: data/full_repos/permissive/160066183/verilog/act.v:38: syntax error, unexpected endmodule, expecting ',' or ';'\nendmodule  \n^~~~~~~~~\n%Error: data/full_repos/permissive/160066183/verilog/act.v:58: syntax error, unexpected ';', expecting ')' or ','\n    input [3:0] W;\n                 ^\n%Error: data/full_repos/permissive/160066183/verilog/act.v:64: syntax error, unexpected IDENTIFIER\n    dec2to4 Dec1 (W[3:2],M[0:3],En);\n    ^~~~~~~\n%Error: data/full_repos/permissive/160066183/verilog/act.v:73: syntax error, unexpected ';', expecting ')' or ','\n    input [2:0] S;\n                 ^\n%Error: data/full_repos/permissive/160066183/verilog/act.v:76: syntax error, unexpected ')'\n);\n^\n%Error: data/full_repos/permissive/160066183/verilog/act.v:94: syntax error, unexpected ';', expecting ')' or ','\n    input D,Clk;\n               ^\n%Error: data/full_repos/permissive/160066183/verilog/act.v:96: syntax error, unexpected ')'\n);\n^\n%Error: Exiting due to 9 error(s)\n"
module dec2to4(
    input [1:0]   W,
    input En,
    output reg [0:3] Y
);

    always @(W,En)
        case ({En,Y})
            3'b100: Y = 4'b1000;
            3'b101: Y = 4'b0100;
            3'b110: Y = 4'b0010;
            3'b111: Y = 4'b0001;
            default: Y = 4'b0000;
        endcase

endmodule
module dec2to4(
    input [1:0]   W,
    input En,
    output reg [0:3] Y
);


    always @(W,En)
        case ({En,Y})
            3'b100: Y = 4'b1000;
            3'b101: Y = 4'b0100;
            3'b110: Y = 4'b0010;
            3'b111: Y = 4'b0001;
            default: Y = 4'b0000;
        endcase

endmodule