data/full_repos/permissive/20759093/test_alu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/20759093/test_alu.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_alu.v:57: Unsupported: Ignoring delay on this delayed statement.\n  # 100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_alu.v:59: Unsupported: Ignoring delay on this delayed statement.\n  # 100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_alu.v:61: Unsupported: Ignoring delay on this delayed statement.\n  # 100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_alu.v:63: Unsupported: Ignoring delay on this delayed statement.\n  # 100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_alu.v:65: Unsupported: Ignoring delay on this delayed statement.\n  # 100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_alu.v:67: Unsupported: Ignoring delay on this delayed statement.\n  # 100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_alu.v:69: Unsupported: Ignoring delay on this delayed statement.\n  # 100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_alu.v:71: Unsupported: Ignoring delay on this delayed statement.\n  # 100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_alu.v:73: Unsupported: Ignoring delay on this delayed statement.\n  # 100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_alu.v:75: Unsupported: Ignoring delay on this delayed statement.\n  # 100;\n  ^\n%Error: data/full_repos/permissive/20759093/test_alu.v:37: Cannot find file containing module: \'alu\'\n alu uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/alu\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/alu.v\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_alu;


	reg [3:0] alu_ctl;
	reg [31:0] A;
	reg [31:0] B;


	wire zero;
	wire [31:0] result;


	alu uut (
		.alu_ctl(alu_ctl), 
		.A(A), 
		.B(B), 
		.zero(zero), 
		.result(result)
	);

	initial begin

		alu_ctl = 0;
		A = 0;
		B = 0;


		#100;
        

		A = 32'h01234567;
		B = 32'h3456789A;
		# 100;
		alu_ctl = 4'b0001;
		# 100;
		alu_ctl = 4'b0010;
		# 100;
		alu_ctl = 4'b0011;
		# 100;
		alu_ctl = 4'b0100;
		# 100;
		alu_ctl = 4'b0101;
		# 100;
		alu_ctl = 4'b0110;
		# 100;
		alu_ctl = 4'b0111;
		# 100;
		alu_ctl = 4'b1000;
		# 100;
		alu_ctl = 4'b1001;
		# 100;
	end
      
endmodule
module test_alu;



	reg [3:0] alu_ctl;
	reg [31:0] A;
	reg [31:0] B;


	wire zero;
	wire [31:0] result;


	alu uut (
		.alu_ctl(alu_ctl), 
		.A(A), 
		.B(B), 
		.zero(zero), 
		.result(result)
	);

	initial begin

		alu_ctl = 0;
		A = 0;
		B = 0;


		#100;
        

		A = 32'h01234567;
		B = 32'h3456789A;
		# 100;
		alu_ctl = 4'b0001;
		# 100;
		alu_ctl = 4'b0010;
		# 100;
		alu_ctl = 4'b0011;
		# 100;
		alu_ctl = 4'b0100;
		# 100;
		alu_ctl = 4'b0101;
		# 100;
		alu_ctl = 4'b0110;
		# 100;
		alu_ctl = 4'b0111;
		# 100;
		alu_ctl = 4'b1000;
		# 100;
		alu_ctl = 4'b1001;
		# 100;
	end
      
endmodule