data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/read_filter.sv
 line:46: before: "integer"
1: b'%Warning-WIDTH: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/read_filter.sv:123: Operator ASSIGN expects 31 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                          : ... In instance read_filter\n   control_read_base_next   = DDR_BASE+((lock_read_fifo_q[63:32]>>log_2_num_workers_in)<<5); \n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/read_filter.sv:198: Cannot find file containing module: \'float_cmp\'\nfloat_cmp fcomp (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0,data/full_repos/permissive/13196823/float_cmp\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0,data/full_repos/permissive/13196823/float_cmp.v\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0,data/full_repos/permissive/13196823/float_cmp.sv\n             float_cmp\n             float_cmp.v\n             float_cmp.sv\n             obj_dir/float_cmp\n             obj_dir/float_cmp.v\n             obj_dir/float_cmp.sv\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/read_filter.sv:209: Cannot find file containing module: \'float_cmp\'\nfloat_cmp comp_inst (\n^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module read_filter #(
	parameter DDR_BASE=0,
	parameter DEFAULT_READ_LENGTH=256,
        parameter ADDRESS_WIDTH = 31,
	parameter DATA_WIDTH=32,
	parameter LOCK_READ_FIFO_WIDTH=(64+1),
	parameter READ_COMPUTE_FIFO_WIDTH=(1+1+32+256),
	parameter UPDATE_MODE=0,
	parameter ACCUM_MODE=1
) (
	input clk,
	input reset,


	input [LOCK_READ_FIFO_WIDTH-1:0] 	lock_read_fifo_q,
	input 					lock_read_fifo_empty,
	output reg				lock_read_fifo_rdreq,


	output reg[READ_COMPUTE_FIFO_WIDTH-1:0] read_compute_fifo_data,
	input 					read_compute_fifo_full,
	output reg				read_compute_fifo_wrreq,


	output reg 				user_read_buffer,
	input wire 				user_data_available,
	input [255:0] 				user_buffer_data,
	
	output wire			      	control_fixed_location,
	output reg [ADDRESS_WIDTH-1:0]        	control_read_base,	
	output reg                             	control_go,
	output reg [ADDRESS_WIDTH-1:0]         	control_read_length,
	input wire 			       	control_done,

	input [31:0] 				log_2_num_workers_in,
	input [31:0]				threshold,
	input [31:0]				filter_threshold

);

function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
endfunction

assign control_fixed_location = 0;

localparam NUM_STATES		=7;
localparam IDLE			=0;
localparam READ_FIFO		=1;
localparam PLACE_READ		=2;
localparam WAIT_READ		=3;
localparam RECORD_PROC		=4;
localparam COMPARE_KEY		=5;
localparam WRITE_FIFO		=6;


reg [log2(NUM_STATES)-1:0]	state, state_next;

reg					lock_read_fifo_rdreq_next;
reg [READ_COMPUTE_FIFO_WIDTH-1:0] 	read_compute_fifo_data_next;
reg					read_compute_fifo_wrreq_next;

reg [ADDRESS_WIDTH-1:0]         control_read_base_next;	
reg [ADDRESS_WIDTH-1:0]         control_read_length_next;
reg                             control_go_next;

reg [255:0] 	key_record,key_record_next;
reg 		mod_bit, mod_bit_next;
reg [31:0] 	msg, msg_next;
reg 		user_read_buffer_next;

wire delta_val_greater_than_threshold;
wire delta_val_greater_than_filter_threshold;






always@(*)
begin

	state_next = state;
	read_compute_fifo_data_next = read_compute_fifo_data;
	read_compute_fifo_wrreq_next = 0;
	lock_read_fifo_rdreq_next = 0;

	user_read_buffer_next = 0;
        control_go_next = 0;
	control_read_base_next = control_read_base;
        control_read_length_next = control_read_length;

	key_record_next = key_record;
	mod_bit_next	= mod_bit;
	msg_next	= msg;	

	case(state)
		IDLE: begin
			if(!lock_read_fifo_empty) begin
				lock_read_fifo_rdreq_next = 1;
				state_next = READ_FIFO;
			end
		end

		READ_FIFO: begin
			state_next = PLACE_READ;
		end

		PLACE_READ: begin
			mod_bit_next			= lock_read_fifo_q[64];
			msg_next			= lock_read_fifo_q[31:0];

			control_read_base_next 		= DDR_BASE+((lock_read_fifo_q[63:32]>>log_2_num_workers_in)<<5); 
                        control_read_length_next 	= DEFAULT_READ_LENGTH;
                        control_go_next 		= 1'b1;
			state_next 			= WAIT_READ;
		end

		WAIT_READ: begin
			if(user_data_available) begin
                                user_read_buffer_next 	= 1'b1;
                                state_next 		= RECORD_PROC;
                        end
		end						

		RECORD_PROC: begin
			key_record_next	      = user_buffer_data;
			state_next 	      = COMPARE_KEY;
		end

		COMPARE_KEY: begin
			state_next = WRITE_FIFO;
		end

		WRITE_FIFO: begin
			if(!read_compute_fifo_full) begin
				
				state_next = IDLE;
				read_compute_fifo_wrreq_next = 1;
					


				if(delta_val_greater_than_threshold & delta_val_greater_than_filter_threshold) begin


					read_compute_fifo_data_next = {mod_bit,1'b0,msg,key_record};
				end
				else begin
					read_compute_fifo_data_next = {mod_bit,1'b1,msg,key_record};
				end
			end
		end

	endcase
end

always@(posedge clk) begin
	if(reset) begin
		state 				<= IDLE;
		read_compute_fifo_data		<= 0;
		read_compute_fifo_wrreq		<= 0;
		lock_read_fifo_rdreq		<= 0;
		user_read_buffer 		<= 0;
        	control_go 			<= 0;
        	control_read_base 		<= 0;
	        control_read_length 		<= 0;
		key_record			<= 0;
		mod_bit				<= 0;
		msg				<= 0;	
	end
	else begin
		state 				<= state_next;
        	control_go 			<= control_go_next;
        	control_read_length 		<= control_read_length_next;
		user_read_buffer 		<= user_read_buffer_next;
		read_compute_fifo_data		<= read_compute_fifo_data_next;
		read_compute_fifo_wrreq		<= read_compute_fifo_wrreq_next;
		lock_read_fifo_rdreq		<= lock_read_fifo_rdreq_next;
 		control_read_base 		<= control_read_base_next;
		key_record			<= key_record_next;
		mod_bit				<= mod_bit_next;
		msg				<= msg_next;	
	end
end



float_cmp fcomp (
        .clk_en         (1'b1),
        .clock          (clk),
        .dataa          (key_record[95:64]),
	.datab          (threshold),

        .ageb           (delta_val_greater_than_threshold)
);



float_cmp comp_inst (
        .clk_en         (1'b1),
        .clock          (clk),
        .dataa          (key_record[95:64]),
        .datab          (filter_threshold),
        .ageb           (delta_val_greater_than_filter_threshold)
);


endmodule
module read_filter #(
	parameter DDR_BASE=0,
	parameter DEFAULT_READ_LENGTH=256,
        parameter ADDRESS_WIDTH = 31,
	parameter DATA_WIDTH=32,
	parameter LOCK_READ_FIFO_WIDTH=(64+1),
	parameter READ_COMPUTE_FIFO_WIDTH=(1+1+32+256),
	parameter UPDATE_MODE=0,
	parameter ACCUM_MODE=1
) (
	input clk,
	input reset,


	input [LOCK_READ_FIFO_WIDTH-1:0] 	lock_read_fifo_q,
	input 					lock_read_fifo_empty,
	output reg				lock_read_fifo_rdreq,


	output reg[READ_COMPUTE_FIFO_WIDTH-1:0] read_compute_fifo_data,
	input 					read_compute_fifo_full,
	output reg				read_compute_fifo_wrreq,


	output reg 				user_read_buffer,
	input wire 				user_data_available,
	input [255:0] 				user_buffer_data,
	
	output wire			      	control_fixed_location,
	output reg [ADDRESS_WIDTH-1:0]        	control_read_base,	
	output reg                             	control_go,
	output reg [ADDRESS_WIDTH-1:0]         	control_read_length,
	input wire 			       	control_done,

	input [31:0] 				log_2_num_workers_in,
	input [31:0]				threshold,
	input [31:0]				filter_threshold

);


function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
endfunction

assign control_fixed_location = 0;

localparam NUM_STATES		=7;
localparam IDLE			=0;
localparam READ_FIFO		=1;
localparam PLACE_READ		=2;
localparam WAIT_READ		=3;
localparam RECORD_PROC		=4;
localparam COMPARE_KEY		=5;
localparam WRITE_FIFO		=6;


reg [log2(NUM_STATES)-1:0]	state, state_next;

reg					lock_read_fifo_rdreq_next;
reg [READ_COMPUTE_FIFO_WIDTH-1:0] 	read_compute_fifo_data_next;
reg					read_compute_fifo_wrreq_next;

reg [ADDRESS_WIDTH-1:0]         control_read_base_next;	
reg [ADDRESS_WIDTH-1:0]         control_read_length_next;
reg                             control_go_next;

reg [255:0] 	key_record,key_record_next;
reg 		mod_bit, mod_bit_next;
reg [31:0] 	msg, msg_next;
reg 		user_read_buffer_next;

wire delta_val_greater_than_threshold;
wire delta_val_greater_than_filter_threshold;






always@(*)
begin

	state_next = state;
	read_compute_fifo_data_next = read_compute_fifo_data;
	read_compute_fifo_wrreq_next = 0;
	lock_read_fifo_rdreq_next = 0;

	user_read_buffer_next = 0;
        control_go_next = 0;
	control_read_base_next = control_read_base;
        control_read_length_next = control_read_length;

	key_record_next = key_record;
	mod_bit_next	= mod_bit;
	msg_next	= msg;	

	case(state)
		IDLE: begin
			if(!lock_read_fifo_empty) begin
				lock_read_fifo_rdreq_next = 1;
				state_next = READ_FIFO;
			end
		end

		READ_FIFO: begin
			state_next = PLACE_READ;
		end

		PLACE_READ: begin
			mod_bit_next			= lock_read_fifo_q[64];
			msg_next			= lock_read_fifo_q[31:0];

			control_read_base_next 		= DDR_BASE+((lock_read_fifo_q[63:32]>>log_2_num_workers_in)<<5); 
                        control_read_length_next 	= DEFAULT_READ_LENGTH;
                        control_go_next 		= 1'b1;
			state_next 			= WAIT_READ;
		end

		WAIT_READ: begin
			if(user_data_available) begin
                                user_read_buffer_next 	= 1'b1;
                                state_next 		= RECORD_PROC;
                        end
		end						

		RECORD_PROC: begin
			key_record_next	      = user_buffer_data;
			state_next 	      = COMPARE_KEY;
		end

		COMPARE_KEY: begin
			state_next = WRITE_FIFO;
		end

		WRITE_FIFO: begin
			if(!read_compute_fifo_full) begin
				
				state_next = IDLE;
				read_compute_fifo_wrreq_next = 1;
					


				if(delta_val_greater_than_threshold & delta_val_greater_than_filter_threshold) begin


					read_compute_fifo_data_next = {mod_bit,1'b0,msg,key_record};
				end
				else begin
					read_compute_fifo_data_next = {mod_bit,1'b1,msg,key_record};
				end
			end
		end

	endcase
end

always@(posedge clk) begin
	if(reset) begin
		state 				<= IDLE;
		read_compute_fifo_data		<= 0;
		read_compute_fifo_wrreq		<= 0;
		lock_read_fifo_rdreq		<= 0;
		user_read_buffer 		<= 0;
        	control_go 			<= 0;
        	control_read_base 		<= 0;
	        control_read_length 		<= 0;
		key_record			<= 0;
		mod_bit				<= 0;
		msg				<= 0;	
	end
	else begin
		state 				<= state_next;
        	control_go 			<= control_go_next;
        	control_read_length 		<= control_read_length_next;
		user_read_buffer 		<= user_read_buffer_next;
		read_compute_fifo_data		<= read_compute_fifo_data_next;
		read_compute_fifo_wrreq		<= read_compute_fifo_wrreq_next;
		lock_read_fifo_rdreq		<= lock_read_fifo_rdreq_next;
 		control_read_base 		<= control_read_base_next;
		key_record			<= key_record_next;
		mod_bit				<= mod_bit_next;
		msg				<= msg_next;	
	end
end



float_cmp fcomp (
        .clk_en         (1'b1),
        .clock          (clk),
        .dataa          (key_record[95:64]),
	.datab          (threshold),

        .ageb           (delta_val_greater_than_threshold)
);



float_cmp comp_inst (
        .clk_en         (1'b1),
        .clock          (clk),
        .dataa          (key_record[95:64]),
        .datab          (filter_threshold),
        .ageb           (delta_val_greater_than_filter_threshold)
);


endmodule