data/full_repos/permissive/218103167/code/s5/si570_controller/i2c_reg_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/218103167/code/s5/si570_controller/i2c_reg_controller.v:193: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 4 bits.\n                                                                                                      : ... In instance i2c_reg_controller\nassign HS_DIV_reg = new_hs_div - 3\'b100 ;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/218103167/code/s5/si570_controller/i2c_reg_controller.v:194: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                                                      : ... In instance i2c_reg_controller\nassign N1_reg = new_n1 - 1\'b1 ;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/218103167/code/s5/si570_controller/i2c_reg_controller.v:345: Operator DIV expects 35 bits on the RHS, but RHS\'s VARREF \'f1\' generates 28 bits.\n                                                                                                      : ... In instance i2c_reg_controller\n    pre_fratio <= {fdco, 7\'h00} / f1 ;   \n                                ^\n%Error: data/full_repos/permissive/218103167/code/s5/si570_controller/i2c_reg_controller.v:495: Cannot find file containing module: \'edge_detector\'\nedge_detector u1(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/218103167/code/s5/si570_controller,data/full_repos/permissive/218103167/edge_detector\n             data/full_repos/permissive/218103167/code/s5/si570_controller,data/full_repos/permissive/218103167/edge_detector.v\n             data/full_repos/permissive/218103167/code/s5/si570_controller,data/full_repos/permissive/218103167/edge_detector.sv\n             edge_detector\n             edge_detector.v\n             edge_detector.sv\n             obj_dir/edge_detector\n             obj_dir/edge_detector.v\n             obj_dir/edge_detector.sv\n%Error: data/full_repos/permissive/218103167/code/s5/si570_controller/i2c_reg_controller.v:504: Cannot find file containing module: \'edge_detector\'\nedge_detector i2c_state_rising(\n^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module i2c_reg_controller(

iCLK,
iRST_n,
iENABLE,
iI2C_CONTROLLER_STATE,
iI2C_CONTROLLER_CONFIG_DONE,
oController_Ready,
iFREQ_MODE,
oSLAVE_ADDR, 
oBYTE_ADDR,
oBYTE_DATA,
oWR_CMD,
oStart,
HS_DIV_reg,
N1_reg,
RFREG_reg,
oSI570_ONE_CLK_CONFIG_DONE,
i2c_read_data,
i2c_read_data_rdy
);




parameter write_cmd = 1'b1;
parameter read_cmd = 1'b0;	




input iCLK;
input iRST_n;
input iENABLE;
input iI2C_CONTROLLER_STATE;
input iI2C_CONTROLLER_CONFIG_DONE;
input [2:0] iFREQ_MODE;
output  [6:0] oSLAVE_ADDR;
output [7:0] oBYTE_ADDR;
output [7:0] oBYTE_DATA ;
output oWR_CMD;
output oStart;
output oSI570_ONE_CLK_CONFIG_DONE;	
output [2:0] HS_DIV_reg;
output [6:0] N1_reg;
output [37:0] RFREG_reg; 
output	oController_Ready;
input [7:0] i2c_read_data ;
input i2c_read_data_rdy ;

wire [7:0] i2c_read_data ;





wire [2:0] iFREQ_MODE;
wire [2:0] HS_DIV_reg;
wire [6:0] N1_reg;
wire [37:0] RFREG_reg; 

reg i2c_read_data_rdy_n ;
reg read_latch ;
reg [2:0] startup_hs_div_reg ;
reg [6:0] startup_n1_reg ;
wire [3:0] startup_hs_div ;
wire [7:0] startup_n1 ;
reg [37:0] startup_refeq ;
reg [3:0] new_hs_div ;
reg [7:0] new_n1 ;
reg [27:0] fdco ;
reg [11:0] n1xhsdiv ;
reg [27:0] f1 ;
reg [34:0] pre_fratio ;
wire [8:0] fratio ;
reg [48:0] new_refeq_49b ;
wire [37:0] new_refeq ;




wire [7:0] reg0_data = 8'h10;
wire [7:0] reg1_data = {HS_DIV_reg,N1_reg[6:2]};
wire [7:0] reg2_data = {N1_reg[1:0],RFREG_reg[37:32]};
wire [7:0] reg3_data = RFREG_reg[31:24];
wire [7:0] reg4_data = RFREG_reg[23:16];
wire [7:0] reg5_data = RFREG_reg[15:8];
wire [7:0] reg6_data = RFREG_reg[7:0];
wire [7:0] reg7_data = 8'h00;
wire [7:0] reg8_data = 8'h40;




wire [7:0] byte_addr0 = 8'd137;
wire [7:0] byte_addr1 = 8'd7;
wire [7:0] byte_addr2 = 8'd8;
wire [7:0] byte_addr3 = 8'd9;
wire [7:0] byte_addr4 = 8'd10;
wire [7:0] byte_addr5 = 8'd11;
wire [7:0] byte_addr6 = 8'd12;
wire [7:0] byte_addr7 = 8'd137;
wire [7:0] byte_addr8 = 8'd135;

wire [6:0] slave_addr = 0;

reg [19:0]  delay_cnt ;
reg delay_10m ;
reg config_done_keep ;
reg [`REG_NUM/2:0] i2c_reg_state;
reg [23:0] 	i2c_ctrl_data;
reg state_ready ;

wire [6:0] oSLAVE_ADDR = i2c_ctrl_data[23:17];
wire [7:0] oBYTE_ADDR = i2c_ctrl_data[16:9];
wire [7:0] oBYTE_DATA = i2c_ctrl_data[8:1];
wire  oWR_CMD = i2c_ctrl_data[0];

reg next_cmd ;
wire i2c_controller_state_rising ;
wire access_next_i2c_reg_cmd ;
wire oStart = access_next_i2c_reg_cmd;
wire i2c_controller_config_done;

wire access_i2c_reg_start;
wire oSI570_ONE_CLK_CONFIG_DONE;
reg	oController_Ready;








assign HS_DIV_reg = new_hs_div - 3'b100 ;
assign N1_reg = new_n1 - 1'b1 ;
assign RFREG_reg = new_refeq ;

always @(*)
  begin
    case(iFREQ_MODE)
      3'h0 :
        begin
          new_hs_div = 4'b0101 ;
          new_n1 = 8'b0000_1010 ;
          fdco = 28'h004_E200 ;
        end
      3'h1 :
        begin
          new_hs_div = 4'b0101 ;
          new_n1 = 8'b0000_1000 ;
          fdco = 28'h004_E200 ;
        end
      3'h2 :
        begin
          new_hs_div = 4'b0100 ;
          new_n1 = 8'b0000_1000 ;
          fdco = 28'h004_E200 ;
        end			
      3'h3 :
        begin
          new_hs_div = 4'b0101 ;
          new_n1 = 8'b0000_0100 ;
          fdco = 28'h004_E200 ;
        end
      3'h4 :
        begin
          new_hs_div = 4'b0100 ;
          new_n1 = 8'b0000_0100 ;
          fdco = 28'h004_E200 ;
        end	
      3'h5 :
        begin
          new_hs_div = 4'b0100 ;
          new_n1 = 8'b0000_0100 ;
          fdco = 28'h005_0910 ;
        end			
      3'h6 :
        begin
          new_hs_div = 4'b0100 ;
          new_n1 = 8'b0000_0010 ;
          fdco = 28'h005_0910 ;
        end			
      default :
        begin
          new_hs_div = 4'b0101 ;
          new_n1 = 8'b0000_1010 ;
          fdco = 28'h004_E200 ;
        end			
    endcase
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      i2c_read_data_rdy_n <= 1'b0 ;
    else
      i2c_read_data_rdy_n <= i2c_read_data_rdy ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      read_latch <= 1'b0 ;
    else
      if (i2c_read_data_rdy && !i2c_read_data_rdy_n)
        read_latch <= 1'b1 ;
      else
        read_latch <= 1'b0 ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      startup_hs_div_reg <= 'b0 ;
    else
      if (read_latch && (oBYTE_ADDR == 8'h07))
        startup_hs_div_reg <= i2c_read_data[7:5] ;
      else
        startup_hs_div_reg <= startup_hs_div_reg ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      startup_n1_reg <= 'b0 ;
    else
      if (read_latch)
        case(oBYTE_ADDR)
          8'h07 : startup_n1_reg <= {i2c_read_data[4:0], startup_n1_reg[1:0]} ;
          8'h08 : startup_n1_reg <= {startup_n1_reg[6:2], i2c_read_data[7:6]} ;
          default : startup_n1_reg <= startup_n1_reg ;
        endcase
      else
        startup_n1_reg <= startup_n1_reg ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      startup_refeq <= 'b0 ;
    else
      if (read_latch)
        case(oBYTE_ADDR)
          8'h08 : startup_refeq <= {i2c_read_data[5:0], startup_refeq[31:0]} ;
          8'h09 : startup_refeq <= {startup_refeq[37:32], i2c_read_data[7:0], startup_refeq[23:0]} ;
          8'h0a : startup_refeq <= {startup_refeq[37:24], i2c_read_data[7:0], startup_refeq[15:0]} ;
          8'h0b : startup_refeq <= {startup_refeq[37:16], i2c_read_data[7:0], startup_refeq[7:0]} ;
          8'h0c : startup_refeq <= {startup_refeq[37:8], i2c_read_data[7:0]} ;
          default : startup_refeq <= startup_refeq ;
        endcase
      else
        startup_refeq <= startup_refeq ;
  end

assign startup_hs_div = startup_hs_div_reg + 3'b100 ;
assign startup_n1 = startup_n1_reg + 1'b1 ;






always @(posedge iCLK)
  begin
    n1xhsdiv <= startup_hs_div * startup_n1 ;
  end






always @(posedge iCLK)
  begin
    f1 <= n1xhsdiv * 16'h1900 ;
  end







always @(posedge iCLK)
  begin
    pre_fratio <= {fdco, 7'h00} / f1 ;
  end

assign fratio = pre_fratio[8:0] ;






always @(posedge iCLK)
  begin
    new_refeq_49b <= fratio * {2'b0, startup_refeq} ;
  end

assign new_refeq = new_refeq_49b[6:0] >= 64 ? new_refeq_49b[44:7]+1'b1 : new_refeq_49b[44:7] ;






always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      delay_cnt <= 'b0 ;
    else
      if (i2c_reg_state == 1)
        if (delay_cnt == 20'h3_ffff)
          delay_cnt <= delay_cnt ;
        else
          delay_cnt <= delay_cnt + 1'b1 ;
      else
        delay_cnt <= 'b0 ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      delay_10m <= 1'b0 ;
    else
      if (i2c_reg_state == 1)
        if (delay_cnt == 20'h3_fffe)
          delay_10m <= 1'b1 ;
        else
          delay_10m <= 1'b0 ;
      else
        delay_10m <= 'b0 ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      config_done_keep <= 1'b0 ;
    else
      if (i2c_reg_state == 1)
        if (i2c_controller_config_done)
          config_done_keep <= 1'b1 ;
        else
          if (delay_10m)
            config_done_keep <= 1'b0 ;
          else
            config_done_keep <= config_done_keep ;
      else
        config_done_keep <= 'b0 ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      i2c_reg_state <= 0;
    else
      begin
        if (access_i2c_reg_start)
          i2c_reg_state <= 1 ;
        else
          if (i2c_controller_config_done || config_done_keep)
            if (i2c_reg_state == 1)
              if (delay_10m)
                i2c_reg_state <= i2c_reg_state+1 ;
              else
                i2c_reg_state <= i2c_reg_state ;
            else
              i2c_reg_state <= i2c_reg_state+1 ;
          else
            if (i2c_reg_state == (`REG_NUM+1))
              i2c_reg_state <= 0 ;
            else
              i2c_reg_state <= i2c_reg_state ;
      end
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      state_ready <= 1'b0 ;
    else
      begin
        if (next_cmd)
          state_ready <= 1'b0 ;
        else
          if (access_i2c_reg_start)
            state_ready <= 1'b1 ;
          else
            if (i2c_controller_config_done || config_done_keep)
              if (i2c_reg_state == 1)
                if (delay_10m)
                  state_ready <= 1'b1 ;
                else
                  state_ready <= state_ready ;
              else
                state_ready <= 1'b1 ;
            else
              if (i2c_reg_state == (`REG_NUM+1))
                state_ready <= 1'b0 ;
              else
                state_ready <= state_ready ;
      end
  end





always@(*)
  begin
    i2c_ctrl_data = 0;
    case (i2c_reg_state)
      0:  i2c_ctrl_data = 0;
      1:  i2c_ctrl_data = {slave_addr,byte_addr8,    8'h80,write_cmd};	
      2:  i2c_ctrl_data = {slave_addr,byte_addr1,    8'h00,read_cmd};
      3:  i2c_ctrl_data = {slave_addr,byte_addr2,    8'h00,read_cmd};
      4:  i2c_ctrl_data = {slave_addr,byte_addr3,    8'h00,read_cmd};
      5:  i2c_ctrl_data = {slave_addr,byte_addr4,    8'h00,read_cmd};
      6:  i2c_ctrl_data = {slave_addr,byte_addr5,    8'h00,read_cmd};		
      7:  i2c_ctrl_data = {slave_addr,byte_addr6,    8'h00,read_cmd};
      8:  i2c_ctrl_data = {slave_addr,byte_addr0,reg0_data,write_cmd};
      9:  i2c_ctrl_data = {slave_addr,byte_addr1,reg1_data,write_cmd};
     10:  i2c_ctrl_data = {slave_addr,byte_addr2,reg2_data,write_cmd};
     11:  i2c_ctrl_data = {slave_addr,byte_addr3,reg3_data,write_cmd};
     12:  i2c_ctrl_data = {slave_addr,byte_addr4,reg4_data,write_cmd};
     13:  i2c_ctrl_data = {slave_addr,byte_addr5,reg5_data,write_cmd};		
     14:  i2c_ctrl_data = {slave_addr,byte_addr6,reg6_data,write_cmd};
     15:  i2c_ctrl_data = {slave_addr,byte_addr7,reg7_data,write_cmd};
     16:  i2c_ctrl_data = {slave_addr,byte_addr8,reg8_data,write_cmd};	

    endcase	
  end 


edge_detector u1(

.iCLK(iCLK),
.iRST_n(iRST_n),
.iIn(iI2C_CONTROLLER_CONFIG_DONE),
.oFallING_EDGE(),
.oRISING_EDGE(i2c_controller_config_done)
);

edge_detector i2c_state_rising(

.iCLK(iCLK),
.iRST_n(iRST_n),
.iIn(iI2C_CONTROLLER_STATE),
.oFallING_EDGE(),
.oRISING_EDGE(i2c_controller_state_rising)
);


always@(posedge iCLK or negedge iRST_n)
	begin
		if (!iRST_n)
			begin
				oController_Ready <= 1'b1;
			end
		else if (i2c_reg_state == `REG_NUM+1)	
			begin
				oController_Ready <= 1'b1;
			end
		else if (i2c_reg_state >0)
			begin
				oController_Ready <= 1'b0;
			end
	end


always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      next_cmd <= 1'b0 ;
    else
      if (i2c_controller_state_rising)
        next_cmd <= 1'b0 ;
      else
        if (state_ready && !iI2C_CONTROLLER_STATE)
          next_cmd <= 1'b1 ;
        else
          next_cmd <= next_cmd ;
  end

assign oSI570_ONE_CLK_CONFIG_DONE = ((i2c_reg_state == `REG_NUM) &&(i2c_controller_config_done)) ? 1'b1 : 1'b0;
assign access_next_i2c_reg_cmd = (next_cmd &&
                                  ((i2c_reg_state <= `REG_NUM) && (i2c_reg_state > 0))
                                 ) ? 1'b1 : 1'b0;
assign access_i2c_reg_start = ((iENABLE == 1'b1)&&(iI2C_CONTROLLER_STATE == 1'b0)) ? 1'b1 : 1'b0;
		
		
		
endmodule
module i2c_reg_controller(

iCLK,
iRST_n,
iENABLE,
iI2C_CONTROLLER_STATE,
iI2C_CONTROLLER_CONFIG_DONE,
oController_Ready,
iFREQ_MODE,
oSLAVE_ADDR, 
oBYTE_ADDR,
oBYTE_DATA,
oWR_CMD,
oStart,
HS_DIV_reg,
N1_reg,
RFREG_reg,
oSI570_ONE_CLK_CONFIG_DONE,
i2c_read_data,
i2c_read_data_rdy
);





parameter write_cmd = 1'b1;
parameter read_cmd = 1'b0;	




input iCLK;
input iRST_n;
input iENABLE;
input iI2C_CONTROLLER_STATE;
input iI2C_CONTROLLER_CONFIG_DONE;
input [2:0] iFREQ_MODE;
output  [6:0] oSLAVE_ADDR;
output [7:0] oBYTE_ADDR;
output [7:0] oBYTE_DATA ;
output oWR_CMD;
output oStart;
output oSI570_ONE_CLK_CONFIG_DONE;	
output [2:0] HS_DIV_reg;
output [6:0] N1_reg;
output [37:0] RFREG_reg; 
output	oController_Ready;
input [7:0] i2c_read_data ;
input i2c_read_data_rdy ;

wire [7:0] i2c_read_data ;





wire [2:0] iFREQ_MODE;
wire [2:0] HS_DIV_reg;
wire [6:0] N1_reg;
wire [37:0] RFREG_reg; 

reg i2c_read_data_rdy_n ;
reg read_latch ;
reg [2:0] startup_hs_div_reg ;
reg [6:0] startup_n1_reg ;
wire [3:0] startup_hs_div ;
wire [7:0] startup_n1 ;
reg [37:0] startup_refeq ;
reg [3:0] new_hs_div ;
reg [7:0] new_n1 ;
reg [27:0] fdco ;
reg [11:0] n1xhsdiv ;
reg [27:0] f1 ;
reg [34:0] pre_fratio ;
wire [8:0] fratio ;
reg [48:0] new_refeq_49b ;
wire [37:0] new_refeq ;




wire [7:0] reg0_data = 8'h10;
wire [7:0] reg1_data = {HS_DIV_reg,N1_reg[6:2]};
wire [7:0] reg2_data = {N1_reg[1:0],RFREG_reg[37:32]};
wire [7:0] reg3_data = RFREG_reg[31:24];
wire [7:0] reg4_data = RFREG_reg[23:16];
wire [7:0] reg5_data = RFREG_reg[15:8];
wire [7:0] reg6_data = RFREG_reg[7:0];
wire [7:0] reg7_data = 8'h00;
wire [7:0] reg8_data = 8'h40;




wire [7:0] byte_addr0 = 8'd137;
wire [7:0] byte_addr1 = 8'd7;
wire [7:0] byte_addr2 = 8'd8;
wire [7:0] byte_addr3 = 8'd9;
wire [7:0] byte_addr4 = 8'd10;
wire [7:0] byte_addr5 = 8'd11;
wire [7:0] byte_addr6 = 8'd12;
wire [7:0] byte_addr7 = 8'd137;
wire [7:0] byte_addr8 = 8'd135;

wire [6:0] slave_addr = 0;

reg [19:0]  delay_cnt ;
reg delay_10m ;
reg config_done_keep ;
reg [`REG_NUM/2:0] i2c_reg_state;
reg [23:0] 	i2c_ctrl_data;
reg state_ready ;

wire [6:0] oSLAVE_ADDR = i2c_ctrl_data[23:17];
wire [7:0] oBYTE_ADDR = i2c_ctrl_data[16:9];
wire [7:0] oBYTE_DATA = i2c_ctrl_data[8:1];
wire  oWR_CMD = i2c_ctrl_data[0];

reg next_cmd ;
wire i2c_controller_state_rising ;
wire access_next_i2c_reg_cmd ;
wire oStart = access_next_i2c_reg_cmd;
wire i2c_controller_config_done;

wire access_i2c_reg_start;
wire oSI570_ONE_CLK_CONFIG_DONE;
reg	oController_Ready;








assign HS_DIV_reg = new_hs_div - 3'b100 ;
assign N1_reg = new_n1 - 1'b1 ;
assign RFREG_reg = new_refeq ;

always @(*)
  begin
    case(iFREQ_MODE)
      3'h0 :
        begin
          new_hs_div = 4'b0101 ;
          new_n1 = 8'b0000_1010 ;
          fdco = 28'h004_E200 ;
        end
      3'h1 :
        begin
          new_hs_div = 4'b0101 ;
          new_n1 = 8'b0000_1000 ;
          fdco = 28'h004_E200 ;
        end
      3'h2 :
        begin
          new_hs_div = 4'b0100 ;
          new_n1 = 8'b0000_1000 ;
          fdco = 28'h004_E200 ;
        end			
      3'h3 :
        begin
          new_hs_div = 4'b0101 ;
          new_n1 = 8'b0000_0100 ;
          fdco = 28'h004_E200 ;
        end
      3'h4 :
        begin
          new_hs_div = 4'b0100 ;
          new_n1 = 8'b0000_0100 ;
          fdco = 28'h004_E200 ;
        end	
      3'h5 :
        begin
          new_hs_div = 4'b0100 ;
          new_n1 = 8'b0000_0100 ;
          fdco = 28'h005_0910 ;
        end			
      3'h6 :
        begin
          new_hs_div = 4'b0100 ;
          new_n1 = 8'b0000_0010 ;
          fdco = 28'h005_0910 ;
        end			
      default :
        begin
          new_hs_div = 4'b0101 ;
          new_n1 = 8'b0000_1010 ;
          fdco = 28'h004_E200 ;
        end			
    endcase
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      i2c_read_data_rdy_n <= 1'b0 ;
    else
      i2c_read_data_rdy_n <= i2c_read_data_rdy ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      read_latch <= 1'b0 ;
    else
      if (i2c_read_data_rdy && !i2c_read_data_rdy_n)
        read_latch <= 1'b1 ;
      else
        read_latch <= 1'b0 ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      startup_hs_div_reg <= 'b0 ;
    else
      if (read_latch && (oBYTE_ADDR == 8'h07))
        startup_hs_div_reg <= i2c_read_data[7:5] ;
      else
        startup_hs_div_reg <= startup_hs_div_reg ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      startup_n1_reg <= 'b0 ;
    else
      if (read_latch)
        case(oBYTE_ADDR)
          8'h07 : startup_n1_reg <= {i2c_read_data[4:0], startup_n1_reg[1:0]} ;
          8'h08 : startup_n1_reg <= {startup_n1_reg[6:2], i2c_read_data[7:6]} ;
          default : startup_n1_reg <= startup_n1_reg ;
        endcase
      else
        startup_n1_reg <= startup_n1_reg ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      startup_refeq <= 'b0 ;
    else
      if (read_latch)
        case(oBYTE_ADDR)
          8'h08 : startup_refeq <= {i2c_read_data[5:0], startup_refeq[31:0]} ;
          8'h09 : startup_refeq <= {startup_refeq[37:32], i2c_read_data[7:0], startup_refeq[23:0]} ;
          8'h0a : startup_refeq <= {startup_refeq[37:24], i2c_read_data[7:0], startup_refeq[15:0]} ;
          8'h0b : startup_refeq <= {startup_refeq[37:16], i2c_read_data[7:0], startup_refeq[7:0]} ;
          8'h0c : startup_refeq <= {startup_refeq[37:8], i2c_read_data[7:0]} ;
          default : startup_refeq <= startup_refeq ;
        endcase
      else
        startup_refeq <= startup_refeq ;
  end

assign startup_hs_div = startup_hs_div_reg + 3'b100 ;
assign startup_n1 = startup_n1_reg + 1'b1 ;






always @(posedge iCLK)
  begin
    n1xhsdiv <= startup_hs_div * startup_n1 ;
  end






always @(posedge iCLK)
  begin
    f1 <= n1xhsdiv * 16'h1900 ;
  end







always @(posedge iCLK)
  begin
    pre_fratio <= {fdco, 7'h00} / f1 ;
  end

assign fratio = pre_fratio[8:0] ;






always @(posedge iCLK)
  begin
    new_refeq_49b <= fratio * {2'b0, startup_refeq} ;
  end

assign new_refeq = new_refeq_49b[6:0] >= 64 ? new_refeq_49b[44:7]+1'b1 : new_refeq_49b[44:7] ;






always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      delay_cnt <= 'b0 ;
    else
      if (i2c_reg_state == 1)
        if (delay_cnt == 20'h3_ffff)
          delay_cnt <= delay_cnt ;
        else
          delay_cnt <= delay_cnt + 1'b1 ;
      else
        delay_cnt <= 'b0 ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      delay_10m <= 1'b0 ;
    else
      if (i2c_reg_state == 1)
        if (delay_cnt == 20'h3_fffe)
          delay_10m <= 1'b1 ;
        else
          delay_10m <= 1'b0 ;
      else
        delay_10m <= 'b0 ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      config_done_keep <= 1'b0 ;
    else
      if (i2c_reg_state == 1)
        if (i2c_controller_config_done)
          config_done_keep <= 1'b1 ;
        else
          if (delay_10m)
            config_done_keep <= 1'b0 ;
          else
            config_done_keep <= config_done_keep ;
      else
        config_done_keep <= 'b0 ;
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      i2c_reg_state <= 0;
    else
      begin
        if (access_i2c_reg_start)
          i2c_reg_state <= 1 ;
        else
          if (i2c_controller_config_done || config_done_keep)
            if (i2c_reg_state == 1)
              if (delay_10m)
                i2c_reg_state <= i2c_reg_state+1 ;
              else
                i2c_reg_state <= i2c_reg_state ;
            else
              i2c_reg_state <= i2c_reg_state+1 ;
          else
            if (i2c_reg_state == (`REG_NUM+1))
              i2c_reg_state <= 0 ;
            else
              i2c_reg_state <= i2c_reg_state ;
      end
  end

always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      state_ready <= 1'b0 ;
    else
      begin
        if (next_cmd)
          state_ready <= 1'b0 ;
        else
          if (access_i2c_reg_start)
            state_ready <= 1'b1 ;
          else
            if (i2c_controller_config_done || config_done_keep)
              if (i2c_reg_state == 1)
                if (delay_10m)
                  state_ready <= 1'b1 ;
                else
                  state_ready <= state_ready ;
              else
                state_ready <= 1'b1 ;
            else
              if (i2c_reg_state == (`REG_NUM+1))
                state_ready <= 1'b0 ;
              else
                state_ready <= state_ready ;
      end
  end





always@(*)
  begin
    i2c_ctrl_data = 0;
    case (i2c_reg_state)
      0:  i2c_ctrl_data = 0;
      1:  i2c_ctrl_data = {slave_addr,byte_addr8,    8'h80,write_cmd};	
      2:  i2c_ctrl_data = {slave_addr,byte_addr1,    8'h00,read_cmd};
      3:  i2c_ctrl_data = {slave_addr,byte_addr2,    8'h00,read_cmd};
      4:  i2c_ctrl_data = {slave_addr,byte_addr3,    8'h00,read_cmd};
      5:  i2c_ctrl_data = {slave_addr,byte_addr4,    8'h00,read_cmd};
      6:  i2c_ctrl_data = {slave_addr,byte_addr5,    8'h00,read_cmd};		
      7:  i2c_ctrl_data = {slave_addr,byte_addr6,    8'h00,read_cmd};
      8:  i2c_ctrl_data = {slave_addr,byte_addr0,reg0_data,write_cmd};
      9:  i2c_ctrl_data = {slave_addr,byte_addr1,reg1_data,write_cmd};
     10:  i2c_ctrl_data = {slave_addr,byte_addr2,reg2_data,write_cmd};
     11:  i2c_ctrl_data = {slave_addr,byte_addr3,reg3_data,write_cmd};
     12:  i2c_ctrl_data = {slave_addr,byte_addr4,reg4_data,write_cmd};
     13:  i2c_ctrl_data = {slave_addr,byte_addr5,reg5_data,write_cmd};		
     14:  i2c_ctrl_data = {slave_addr,byte_addr6,reg6_data,write_cmd};
     15:  i2c_ctrl_data = {slave_addr,byte_addr7,reg7_data,write_cmd};
     16:  i2c_ctrl_data = {slave_addr,byte_addr8,reg8_data,write_cmd};	

    endcase	
  end 


edge_detector u1(

.iCLK(iCLK),
.iRST_n(iRST_n),
.iIn(iI2C_CONTROLLER_CONFIG_DONE),
.oFallING_EDGE(),
.oRISING_EDGE(i2c_controller_config_done)
);

edge_detector i2c_state_rising(

.iCLK(iCLK),
.iRST_n(iRST_n),
.iIn(iI2C_CONTROLLER_STATE),
.oFallING_EDGE(),
.oRISING_EDGE(i2c_controller_state_rising)
);


always@(posedge iCLK or negedge iRST_n)
	begin
		if (!iRST_n)
			begin
				oController_Ready <= 1'b1;
			end
		else if (i2c_reg_state == `REG_NUM+1)	
			begin
				oController_Ready <= 1'b1;
			end
		else if (i2c_reg_state >0)
			begin
				oController_Ready <= 1'b0;
			end
	end


always @(posedge iCLK or negedge iRST_n)
  begin
    if (!iRST_n)
      next_cmd <= 1'b0 ;
    else
      if (i2c_controller_state_rising)
        next_cmd <= 1'b0 ;
      else
        if (state_ready && !iI2C_CONTROLLER_STATE)
          next_cmd <= 1'b1 ;
        else
          next_cmd <= next_cmd ;
  end

assign oSI570_ONE_CLK_CONFIG_DONE = ((i2c_reg_state == `REG_NUM) &&(i2c_controller_config_done)) ? 1'b1 : 1'b0;
assign access_next_i2c_reg_cmd = (next_cmd &&
                                  ((i2c_reg_state <= `REG_NUM) && (i2c_reg_state > 0))
                                 ) ? 1'b1 : 1'b0;
assign access_i2c_reg_start = ((iENABLE == 1'b1)&&(iI2C_CONTROLLER_STATE == 1'b0)) ? 1'b1 : 1'b0;
		
		
		
endmodule