data/full_repos/permissive/211316121/lab8_1/RAM.v
data/verilator_xmls/5b6ce63a-5309-4219-a4c9-4264290deb83.xml
module MUX2_1(
    input [3:0] a,
    input [3:0] b,
    input sel,
    output reg [3:0] yout
);
always@(*)
case (sel)
  'b0:yout=a;
  'b1:yout=b;
  default:yout=a;
endcase
endmodule
module MUX2_1(
    input [3:0] a,
    input [3:0] b,
    input sel,
    output reg [3:0] yout
);

always@(*)
case (sel)
  'b0:yout=a;
  'b1:yout=b;
  default:yout=a;
endcase
endmodule