data/full_repos/permissive/129155059/counter/counter_tb.v
 line:11: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/129155059/counter/counter_tb.v:7: Unsupported: Ignoring delay on this delayed statement.\n        # 17 ireset = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/counter/counter_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n        # 11 ireset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/counter/counter_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n        # 29 ireset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/counter/counter_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n        # 11 ireset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/counter/counter_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        # 100 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/counter/counter_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    always #5 iclk = !iclk;\n           ^\n%Error: data/full_repos/permissive/129155059/counter/counter_tb.v:21: Unsupported or unknown PLI call: $monitor\n        $monitor("At time %t, ovalue = %h (%0d)",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/129155059/counter/counter_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("counter.vcd"); \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/counter/counter_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, counter_tb); \n        ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb;

    reg ireset = 0;
    initial begin

        # 17 ireset = 1;
        # 11 ireset = 0;
        # 29 ireset = 1;
        # 11 ireset = 0;
        # 100 $finish;
    end

    reg iclk = 0;
    always #5 iclk = !iclk;

    wire [7:0] ovalue;
    counter c1 (ovalue, iclk, ireset);

    initial
        $monitor("At time %t, ovalue = %h (%0d)",
                 $time, ovalue, ovalue);

    initial begin
        $dumpfile ("counter.vcd"); 
        $dumpvars(1, counter_tb); 
    end

endmodule
module counter_tb;


    reg ireset = 0;
    initial begin

        # 17 ireset = 1;
        # 11 ireset = 0;
        # 29 ireset = 1;
        # 11 ireset = 0;
        # 100 $finish;
    end

    reg iclk = 0;
    always #5 iclk = !iclk;

    wire [7:0] ovalue;
    counter c1 (ovalue, iclk, ireset);

    initial
        $monitor("At time %t, ovalue = %h (%0d)",
                 $time, ovalue, ovalue);

    initial begin
        $dumpfile ("counter.vcd"); 
        $dumpvars(1, counter_tb); 
    end

endmodule