data/full_repos/permissive/143278/ivltests/pr2117473.v
 line:16: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2117473.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("(%0d)*(%0d) = %0d", A, B, Y);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multiply();

reg signed [31:0] A;
reg signed [31:0] B;

wire signed [63:0] Y;

assign Y = A * B;

initial begin
  A = -1;
  B = -1;
  #1 $display("(%0d)*(%0d) = %0d", A, B, Y);
  if (Y !== 64'd1) begin
     $display("FAILED");
     $finish;
  end
  $display("PASSED");
end

endmodule
module multiply();


reg signed [31:0] A;
reg signed [31:0] B;

wire signed [63:0] Y;

assign Y = A * B;

initial begin
  A = -1;
  B = -1;
  #1 $display("(%0d)*(%0d) = %0d", A, B, Y);
  if (Y !== 64'd1) begin
     $display("FAILED");
     $finish;
  end
  $display("PASSED");
end

endmodule