data/full_repos/permissive/172912857/project_bcd_7dig/bcd_7dig.v
 line:115: before: "("
data/verilator_xmls/2c5f037e-d35a-4abe-b4b8-0ad997fa253c.xml
module ClkDivider (
    input clk,
    input rst,
    output reg clk_div
    );
     
localparam constantNumber = 50000;


reg [31:0] count;
 
always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        count <= 32'b0;
    else if (count == constantNumber - 1)
        count <= 32'b0;
    else
        count <= count + 1;
end

always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        clk_div <= 1'b0;
    else if (count == constantNumber - 1)
        clk_div <= ~clk_div;
    else
        clk_div <= clk_div;
end 
endmodule
module ClkDivider (
    input clk,
    input rst,
    output reg clk_div
    );

     
localparam constantNumber = 50000;


reg [31:0] count;
 
always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        count <= 32'b0;
    else if (count == constantNumber - 1)
        count <= 32'b0;
    else
        count <= count + 1;
end

always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        clk_div <= 1'b0;
    else if (count == constantNumber - 1)
        clk_div <= ~clk_div;
    else
        clk_div <= clk_div;
end 
endmodule