data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-pmod-i2s2/szg-i2s2-pmod-top.v
1: b"%Error: data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-pmod-i2s2/szg-i2s2-pmod-top.v:49: Cannot find file containing module: 'szg_i2s2_pmod_phy'\nszg_i2s2_pmod_phy szg_i2s2_phy(\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-pmod-i2s2,data/full_repos/permissive/141490569/szg_i2s2_pmod_phy\n             data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-pmod-i2s2,data/full_repos/permissive/141490569/szg_i2s2_pmod_phy.v\n             data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-pmod-i2s2,data/full_repos/permissive/141490569/szg_i2s2_pmod_phy.sv\n             szg_i2s2_pmod_phy\n             szg_i2s2_pmod_phy.v\n             szg_i2s2_pmod_phy.sv\n             obj_dir/szg_i2s2_pmod_phy\n             obj_dir/szg_i2s2_pmod_phy.v\n             obj_dir/szg_i2s2_pmod_phy.sv\n%Error: Exiting due to 1 error(s)\n"
module szg_i2s2_pmod_top(
	input  wire        clk,
	input  wire        reset,


	input  wire        volume,


	output wire        rx_mclk,
	output wire        rx_lrck,
	output wire        rx_sclk,
	input  wire        rx_sdin,

	output reg  [23:0] data
);


wire [23:0] r_channel, l_channel;
szg_i2s2_pmod_phy szg_i2s2_phy(
	.clk       (clk),
	.reset     (reset),
	.mclk      (rx_mclk),
	.lrck      (rx_lrck),
	.sclk      (rx_sclk),
	.sdin      (rx_sdin),
	
	.r_channel (r_channel),
	.l_channel (l_channel)
);

always @(posedge clk)
	data <= (r_channel + l_channel) / 2;

endmodule
module szg_i2s2_pmod_top(
	input  wire        clk,
	input  wire        reset,


	input  wire        volume,


	output wire        rx_mclk,
	output wire        rx_lrck,
	output wire        rx_sclk,
	input  wire        rx_sdin,

	output reg  [23:0] data
);



wire [23:0] r_channel, l_channel;
szg_i2s2_pmod_phy szg_i2s2_phy(
	.clk       (clk),
	.reset     (reset),
	.mclk      (rx_mclk),
	.lrck      (rx_lrck),
	.sclk      (rx_sclk),
	.sdin      (rx_sdin),
	
	.r_channel (r_channel),
	.l_channel (l_channel)
);

always @(posedge clk)
	data <= (r_channel + l_channel) / 2;

endmodule