data/full_repos/permissive/19572582/Lab3/lab3_part4.v
data/verilator_xmls/f14d0b31-9c3f-4766-8601-f5340d00a4bb.xml
module Dflop (D, Clk, Q);
  input D, Clk;
  output reg Q;

  always @ (D, Clk)
	if (Clk)
		Q = D;
		
endmodule
module Dflop (D, Clk, Q);

  input D, Clk;
  output reg Q;

  always @ (D, Clk)
	if (Clk)
		Q = D;
		
endmodule