data/full_repos/permissive/211866113/RAM_Tester.v
 line:110: before: "!="
1: b'%Error: data/full_repos/permissive/211866113/RAM_Tester.v:1: Cannot find include file: RAM.v\n`include "RAM.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/RAM.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/RAM.v.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/RAM.v.sv\n             RAM.v\n             RAM.v.v\n             RAM.v.sv\n             obj_dir/RAM.v\n             obj_dir/RAM.v.v\n             obj_dir/RAM.v.sv\n%Error: data/full_repos/permissive/211866113/RAM_Tester.v:2: Cannot find include file: word_gen.v\n`include "word_gen.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/211866113/RAM_Tester.v:38: syntax error, unexpected !=, expecting \')\' or \',\' or or\n    always @ ( OUT != {Word_size{1\'bz}} && CS ) begin\n                   ^~\n%Error: data/full_repos/permissive/211866113/RAM_Tester.v:46: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("simple_RAM_test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/211866113/RAM_Tester.v:47: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0);  \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/211866113/RAM_Tester.v:49: Unsupported or unknown PLI call: $monitor\n        $monitor($time, "\\t%b\\t%b\\t%b\\t%b\\t%b\\t%b\\t%b", CS, WE, OE, ADDRESS, DATA, OUT, word_reg);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/211866113/RAM_Tester.v:59: syntax error, unexpected \'#\'\n            #3 gen_next = FALSE;\n            ^\n%Error: data/full_repos/permissive/211866113/RAM_Tester.v:71: syntax error, unexpected \'#\'\n            #3 OE = TRUE;\n            ^\n%Error: Cannot continue\n'
module RAM_basic_tester ();
    parameter FALSE = 1'b0;
    parameter TRUE = 1'b1;


    parameter Address_size = 2;
    parameter Word_size = 3;


    integer i;


    reg [Address_size-1:0] ADDRESS;
    wire [Word_size-1:0]   DATA;
    wire [Word_size-1:0]   OUT;

    reg 		   CS, WE, OE;

    reg [Word_size-1:0]    word_reg;


    reg 		   gen_next;

    RAM_module my_RAM(ADDRESS, DATA, OUT, CS, WE, OE);
    word_gen my_gen(gen_next, DATA);



    always @ ( OUT != {Word_size{1'bz}} && CS ) begin
        if (OE) begin
            $display("Entered the block!");
            word_reg <= OUT ;
        end
    end

    initial begin
        $dumpfile("simple_RAM_test.vcd");
        $dumpvars(0);
        $display("\t\ttime \tCS\tWE\tOE\tADDRESS\tDATA\tOUT\tword_reg");
        $monitor($time, "\t%b\t%b\t%b\t%b\t%b\t%b\t%b", CS, WE, OE, ADDRESS, DATA, OUT, word_reg);

        OE = FALSE;
        WE = FALSE;
        CS = FALSE;
        gen_next = FALSE;
        word_reg = {Word_size{1'bx}};
        ADDRESS = {Address_size{1'b0}};

        for (i = 0; i< Address_size ** 2; i = i + 1) begin
            #3 gen_next = FALSE;
            WE = TRUE;
            CS = TRUE;
            #1 WE = FALSE;
            CS = FALSE;
            #1 ADDRESS++;
            gen_next = TRUE;
        end


        #5 ADDRESS = {Address_size{1'b0}};
        for (i = 0; i< Address_size ** 2; i = i + 1) begin
            #3 OE = TRUE;
            CS = TRUE;
            #1 OE = FALSE;
            CS = FALSE;
            #1 ADDRESS++;
        end
        #5 $finish;
    end

endmodule
module RAM_basic_tester ();

    parameter FALSE = 1'b0;
    parameter TRUE = 1'b1;


    parameter Address_size = 2;
    parameter Word_size = 3;


    integer i;


    reg [Address_size-1:0] ADDRESS;
    wire [Word_size-1:0]   DATA;
    wire [Word_size-1:0]   OUT;

    reg 		   CS, WE, OE;

    reg [Word_size-1:0]    word_reg;


    reg 		   gen_next;

    RAM_module my_RAM(ADDRESS, DATA, OUT, CS, WE, OE);
    word_gen my_gen(gen_next, DATA);



    always @ ( OUT != {Word_size{1'bz}} && CS ) begin
        if (OE) begin
            $display("Entered the block!");
            word_reg <= OUT ;
        end
    end

    initial begin
        $dumpfile("simple_RAM_test.vcd");
        $dumpvars(0);
        $display("\t\ttime \tCS\tWE\tOE\tADDRESS\tDATA\tOUT\tword_reg");
        $monitor($time, "\t%b\t%b\t%b\t%b\t%b\t%b\t%b", CS, WE, OE, ADDRESS, DATA, OUT, word_reg);

        OE = FALSE;
        WE = FALSE;
        CS = FALSE;
        gen_next = FALSE;
        word_reg = {Word_size{1'bx}};
        ADDRESS = {Address_size{1'b0}};

        for (i = 0; i< Address_size ** 2; i = i + 1) begin
            #3 gen_next = FALSE;
            WE = TRUE;
            CS = TRUE;
            #1 WE = FALSE;
            CS = FALSE;
            #1 ADDRESS++;
            gen_next = TRUE;
        end


        #5 ADDRESS = {Address_size{1'b0}};
        for (i = 0; i< Address_size ** 2; i = i + 1) begin
            #3 OE = TRUE;
            CS = TRUE;
            #1 OE = FALSE;
            CS = FALSE;
            #1 ADDRESS++;
        end
        #5 $finish;
    end

endmodule