data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Multiplexers/mux2to1.v
data/verilator_xmls/c50be96e-5d38-4711-bd39-959e1431da13.xml
module top_module (
	input a,
	input b,
	input sel,
	output out
);

	assign out = (sel & b) | (~sel & a);
	


	
endmodule
module top_module (
	input a,
	input b,
	input sel,
	output out
);


	assign out = (sel & b) | (~sel & a);
	


	
endmodule