data/full_repos/permissive/174263347/JamaOneChip/hdl/quad_counter.v
1: b"%Error: data/full_repos/permissive/174263347/JamaOneChip/hdl/quad_counter.v:32: Cannot find file containing module: 'lcel'\nlcel lcelem(plusin, plus);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/174263347/JamaOneChip/hdl,data/full_repos/permissive/174263347/lcel\n             data/full_repos/permissive/174263347/JamaOneChip/hdl,data/full_repos/permissive/174263347/lcel.v\n             data/full_repos/permissive/174263347/JamaOneChip/hdl,data/full_repos/permissive/174263347/lcel.sv\n             lcel\n             lcel.v\n             lcel.sv\n             obj_dir/lcel\n             obj_dir/lcel.v\n             obj_dir/lcel.sv\n%Error: Exiting due to 1 error(s)\n"
module QUAD_COUNTER ( clk, enable, inA, inB, clrn, q);

	input 			clk, enable, inA, inB, clrn;
	output	[6:0]	q;

	reg 	[6:0] 	cnt;
	reg		[3:0]	ballRise;
	wire 	[1:0] 	rise;
	wire	 		plus, plusin;
	wire			ena;





always @ (posedge clk or negedge clrn) 
begin
	if(~clrn)
		ballRise <= 0;
	else if (enable)
		ballRise <= {ballRise[1:0], inB, inA};
end

assign rise[1]	= ballRise[3] ^ ballRise[1];
assign rise[0]	= ballRise[2] ^ ballRise[0];
assign plusin   = ( rise[0] & (inA !=  inB) ) | ( rise[1] & (inA == inB) );

lcel lcelem(plusin, plus);

assign ena 		= (rise[0] | rise[1]) & enable;





always @ (posedge clk or negedge clrn) 
begin
	if(~clrn)
		cnt <= 0;
	else if (ena)
		if(plus)
			cnt	<= cnt + 1;
		else
			cnt	<= cnt - 1; 
end

assign 	q	= cnt;

endmodule
module QUAD_COUNTER ( clk, enable, inA, inB, clrn, q);


	input 			clk, enable, inA, inB, clrn;
	output	[6:0]	q;

	reg 	[6:0] 	cnt;
	reg		[3:0]	ballRise;
	wire 	[1:0] 	rise;
	wire	 		plus, plusin;
	wire			ena;





always @ (posedge clk or negedge clrn) 
begin
	if(~clrn)
		ballRise <= 0;
	else if (enable)
		ballRise <= {ballRise[1:0], inB, inA};
end

assign rise[1]	= ballRise[3] ^ ballRise[1];
assign rise[0]	= ballRise[2] ^ ballRise[0];
assign plusin   = ( rise[0] & (inA !=  inB) ) | ( rise[1] & (inA == inB) );

lcel lcelem(plusin, plus);

assign ena 		= (rise[0] | rise[1]) & enable;





always @ (posedge clk or negedge clrn) 
begin
	if(~clrn)
		cnt <= 0;
	else if (ena)
		if(plus)
			cnt	<= cnt + 1;
		else
			cnt	<= cnt - 1; 
end

assign 	q	= cnt;

endmodule