data/full_repos/permissive/167746421/test_global_controller/genesis/clocker.svp
 line:41: before: "("
1: b"%Error: data/full_repos/permissive/167746421/test_global_controller/genesis/clocker.svp:40: Define or directive not defined: '`mname'\nmodule `mname`\n       ^~~~~~\n%Error: data/full_repos/permissive/167746421/test_global_controller/genesis/clocker.svp:40: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule `mname`\n             ^\n%Error: data/full_repos/permissive/167746421/test_global_controller/genesis/clocker.svp:42: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic Reset);\n    ^~~~~~\n%Error: data/full_repos/permissive/167746421/test_global_controller/genesis/clocker.svp:44: Unsupported or unknown PLI call: $clk_period\n   always #`$clk_period/2` Clk <= ~Clk;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/167746421/test_global_controller/genesis/clocker.svp:48: Unsupported or unknown PLI call: $reset_period\n      repeat(`$reset_period`) @(posedge Clk);\n              ^~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module `mname`
   (output logic Clk,
    output logic Reset);

   always #`$clk_period/2` Clk <= ~Clk;
   initial begin
      Clk <= 1'b0;
      Reset <= 1'b1;
      repeat(`$reset_period`) @(posedge Clk);
      Reset <= 1'b0;
   end
endmodule
module `mname`
   (output logic Clk,
    output logic Reset);


   always #`$clk_period/2` Clk <= ~Clk;
   initial begin
      Clk <= 1'b0;
      Reset <= 1'b1;
      repeat(`$reset_period`) @(posedge Clk);
      Reset <= 1'b0;
   end
endmodule