data/full_repos/permissive/159902111/PCPU_experiment/Add.v
data/verilator_xmls/b9175bdd-5539-4875-bc2b-b5b00a2d76f9.xml
module Add(
  input  [31:0] src0_i,
  input  [31:0] src1_i,
  output [31:0] outcome_o
  );
  reg [31:0] outcome;
  always@(*)
  begin
    outcome = src0_i + src1_i;
  end
  assign outcome_o = outcome;
endmodule
module Add(
  input  [31:0] src0_i,
  input  [31:0] src1_i,
  output [31:0] outcome_o
  );

  reg [31:0] outcome;
  always@(*)
  begin
    outcome = src0_i + src1_i;
  end
  assign outcome_o = outcome;
endmodule