data/full_repos/permissive/187712539/modules/addAlu.v
data/verilator_xmls/9c0f8744-b140-4b4b-97a8-18880746fb5a.xml
module addAlu(inA,inB,out);
input [31:0] inA, inB;
output [31:0] out;

assign out = inA + inB;

endmodule
module addAlu(inA,inB,out);

input [31:0] inA, inB;
output [31:0] out;

assign out = inA + inB;

endmodule