data/full_repos/permissive/162533945/sra.v
data/verilator_xmls/69fdcba1-a746-4296-bdca-3144785d7d91.xml
module mux_2to1_1bit(a, b, sel, out);
	
	input a, b, sel;
	output out;
	
	wire nsel, t0, t1;
	not not0(nsel, sel);
	
	and and0(t0, nsel, a);
	and and1(t1, sel, b);
	or or0(out, t0, t1);
	
endmodule
module mux_2to1_1bit(a, b, sel, out);

	
	input a, b, sel;
	output out;
	
	wire nsel, t0, t1;
	not not0(nsel, sel);
	
	and and0(t0, nsel, a);
	and and1(t1, sel, b);
	or or0(out, t0, t1);
	
endmodule