data/full_repos/permissive/116563702/fsm/snail_pattern_1101/mealy.v
data/verilator_xmls/ce4600e6-a7af-418d-b9dc-5147f4c34c69.xml
module snail_mealy_1101( input d,
			 input 	clk,
			 input reset,
			 output y);

   parameter S0 = 3'd0;
   parameter S1 = 3'd1;
   parameter S2 = 3'd2;
   parameter S3 = 3'd3;

   reg [2:0] 			state, nextstate;
   

   always @(posedge clk or posedge reset)
     begin
	if (reset) state <= S0;
	else	   state <= nextstate;
     end


   always @(*)
     begin
	case (state)
	  S0 :
	    if (d) nextstate = S1;
	    else   nextstate = S0;

	  S1 :
	    if (d) nextstate = S2;
	    else   nextstate = S0;

	  S2 :
	    if (~d) nextstate = S3;
	    else   nextstate = S2;
	  
	  S3 :
	    if (d) nextstate = S1;
	    else   nextstate = S0;

	  default :
		   nextstate = S0;
	endcase
     end


   assign y = (d & state == S3);
endmodule
module snail_mealy_1101( input d,
			 input 	clk,
			 input reset,
			 output y);


   parameter S0 = 3'd0;
   parameter S1 = 3'd1;
   parameter S2 = 3'd2;
   parameter S3 = 3'd3;

   reg [2:0] 			state, nextstate;
   

   always @(posedge clk or posedge reset)
     begin
	if (reset) state <= S0;
	else	   state <= nextstate;
     end


   always @(*)
     begin
	case (state)
	  S0 :
	    if (d) nextstate = S1;
	    else   nextstate = S0;

	  S1 :
	    if (d) nextstate = S2;
	    else   nextstate = S0;

	  S2 :
	    if (~d) nextstate = S3;
	    else   nextstate = S2;
	  
	  S3 :
	    if (d) nextstate = S1;
	    else   nextstate = S0;

	  default :
		   nextstate = S0;
	endcase
     end


   assign y = (d & state == S3);
endmodule