data/full_repos/permissive/119209630/src/cpu_example.v
None: at end of input
1: b'%Error: data/full_repos/permissive/119209630/src/cpu_example.v:20: Cannot find include file: cpu_example_instructions.h\n`include "cpu_example_instructions.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119209630/src,data/full_repos/permissive/119209630/cpu_example_instructions.h\n             data/full_repos/permissive/119209630/src,data/full_repos/permissive/119209630/cpu_example_instructions.h.v\n             data/full_repos/permissive/119209630/src,data/full_repos/permissive/119209630/cpu_example_instructions.h.sv\n             cpu_example_instructions.h\n             cpu_example_instructions.h.v\n             cpu_example_instructions.h.sv\n             obj_dir/cpu_example_instructions.h\n             obj_dir/cpu_example_instructions.h.v\n             obj_dir/cpu_example_instructions.h.sv\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:51: syntax error, unexpected const, expecting IDENTIFIER or \'=\' or do or final\n reg [7:0] const;\n                ^\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:66: syntax error, unexpected const\n  const = {arg1, arg2};\n        ^\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:83: Define or directive not defined: \'`LOAD\'\n   `LOAD: begin\n   ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:83: syntax error, unexpected \':\', expecting endcase\n   `LOAD: begin\n        ^\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:88: Define or directive not defined: \'`STORE\'\n   `STORE: begin\n   ^~~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:88: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `STORE: begin\n           ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:93: Define or directive not defined: \'`SET\'\n   `SET: begin\n   ^~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:93: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `SET: begin\n         ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:96: Define or directive not defined: \'`LT\'\n   `LT: begin\n   ^~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:96: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `LT: begin\n        ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:99: Define or directive not defined: \'`EQ\'\n   `EQ: begin\n   ^~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:99: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `EQ: begin\n        ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:102: Define or directive not defined: \'`BEQ\'\n   `BEQ: begin\n   ^~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:102: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `BEQ: begin\n         ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:106: Define or directive not defined: \'`BNEQ\'\n   `BNEQ: begin\n   ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:106: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `BNEQ: begin\n          ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:110: Define or directive not defined: \'`ADD\'\n   `ADD: begin\n   ^~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:110: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `ADD: begin\n         ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:113: Define or directive not defined: \'`SUB\'\n   `SUB: begin\n   ^~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:113: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `SUB: begin\n         ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:116: Define or directive not defined: \'`SHL\'\n   `SHL: begin\n   ^~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:116: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `SHL: begin\n         ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:119: Define or directive not defined: \'`SHR\'\n   `SHR: begin\n   ^~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:119: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `SHR: begin\n         ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:122: Define or directive not defined: \'`AND\'\n   `AND: begin\n   ^~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:122: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `AND: begin\n         ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:125: Define or directive not defined: \'`OR\'\n   `OR: begin\n   ^~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:125: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `OR: begin\n        ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:128: Define or directive not defined: \'`INV\'\n   `INV: begin\n   ^~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:128: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `INV: begin\n         ^~~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:131: Define or directive not defined: \'`XOR\'\n   `XOR: begin\n   ^~~~\n%Error: data/full_repos/permissive/119209630/src/cpu_example.v:131: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `XOR: begin\n         ^~~~~\n%Error: Cannot continue\n'
module cpu_example(
		input clk,
		input rst,
		output [7:0] addr,
		output read,
		input [7:0] din,
		output write,
		output [7:0] dout
	);


	reg read;
	reg write;
	reg [7:0] dout;
	reg [7:0] addr;


	integer i;


	reg [7:0] reg_d [15:0];
	reg [7:0] reg_q [15:0];


	wire [15:0] inst;
	reg [3:0] op;
	reg [3:0] dest;
	reg [3:0] arg1;
	reg [3:0] arg2;
	reg [7:0] const;

	cpu_example_rom rom (
		.clk(clk),
		.addr(reg_q[0]),
		.data(inst)
	);

	always @(posedge clk) begin


		op = inst[15:12];
		dest = inst[11:8];
		arg1 = inst[7:4];
		arg2 = inst[3:0];
		const = {arg1, arg2};


		read = 1'b0;
		write = 1'b0;
		dout = 8'hxx;
		addr = 8'hxx;
		

		reg_d[0] = reg_q[0] + 8'd1;

		for (i=1; i<16; i=i+1) begin
			reg_d[i] = reg_q[i];
		end


		case (op)
			`LOAD: begin
				read = 1'b1;
				addr = reg_q[arg1] + arg2;
				reg_d[dest] = din;
			end
			`STORE: begin
				write = 1'b1;
				addr = reg_q[arg1] + arg2;
				dout = reg_q[dest];
			end
			`SET: begin
				reg_d[dest] = const;
			end
			`LT: begin
				reg_d[dest] = reg_q[arg1] < reg_q[arg2];
			end
			`EQ: begin
				reg_d[dest] = reg_q[arg1] == reg_q[arg2];
			end
			`BEQ: begin
				if (reg_q[dest] == const)
					reg_d[0] = reg_q[0] + 8'd2;
			end
			`BNEQ: begin
				if (reg_q[dest] != const)
					reg_d[0] = reg_q[0] + 8'd2;
			end
			`ADD: begin
				reg_d[dest] = reg_q[arg1] + reg_q[arg2];
			end
			`SUB: begin
				reg_d[dest] = reg_q[arg1] + reg_q[arg2];
			end
			`SHL: begin
				reg_d[dest] = reg_q[arg1] << reg_q[arg2];
			end
			`SHR: begin
				reg_d[dest] = reg_q[arg1] >> reg_q[arg2];
			end
			`AND: begin
				reg_d[dest] = reg_q[arg1] & reg_q[arg2];
			end
			`OR: begin
				reg_d[dest] = reg_q[arg1] | reg_q[arg2];
			end
			`INV: begin
				reg_d[dest] = ~reg_q[arg1];
			end
			`XOR: begin
				reg_d[dest] = reg_q[arg1] ^ reg_q[arg2];
			end
		endcase





	end
	
	always @(posedge clk) begin

		for (i=0; i<16; i=i+1) begin
			reg_q[i] <= reg_d[i];
		end
	end

endmodule
module cpu_example(
		input clk,
		input rst,
		output [7:0] addr,
		output read,
		input [7:0] din,
		output write,
		output [7:0] dout
	);



	reg read;
	reg write;
	reg [7:0] dout;
	reg [7:0] addr;


	integer i;


	reg [7:0] reg_d [15:0];
	reg [7:0] reg_q [15:0];


	wire [15:0] inst;
	reg [3:0] op;
	reg [3:0] dest;
	reg [3:0] arg1;
	reg [3:0] arg2;
	reg [7:0] const;

	cpu_example_rom rom (
		.clk(clk),
		.addr(reg_q[0]),
		.data(inst)
	);

	always @(posedge clk) begin


		op = inst[15:12];
		dest = inst[11:8];
		arg1 = inst[7:4];
		arg2 = inst[3:0];
		const = {arg1, arg2};


		read = 1'b0;
		write = 1'b0;
		dout = 8'hxx;
		addr = 8'hxx;
		

		reg_d[0] = reg_q[0] + 8'd1;

		for (i=1; i<16; i=i+1) begin
			reg_d[i] = reg_q[i];
		end


		case (op)
			`LOAD: begin
				read = 1'b1;
				addr = reg_q[arg1] + arg2;
				reg_d[dest] = din;
			end
			`STORE: begin
				write = 1'b1;
				addr = reg_q[arg1] + arg2;
				dout = reg_q[dest];
			end
			`SET: begin
				reg_d[dest] = const;
			end
			`LT: begin
				reg_d[dest] = reg_q[arg1] < reg_q[arg2];
			end
			`EQ: begin
				reg_d[dest] = reg_q[arg1] == reg_q[arg2];
			end
			`BEQ: begin
				if (reg_q[dest] == const)
					reg_d[0] = reg_q[0] + 8'd2;
			end
			`BNEQ: begin
				if (reg_q[dest] != const)
					reg_d[0] = reg_q[0] + 8'd2;
			end
			`ADD: begin
				reg_d[dest] = reg_q[arg1] + reg_q[arg2];
			end
			`SUB: begin
				reg_d[dest] = reg_q[arg1] + reg_q[arg2];
			end
			`SHL: begin
				reg_d[dest] = reg_q[arg1] << reg_q[arg2];
			end
			`SHR: begin
				reg_d[dest] = reg_q[arg1] >> reg_q[arg2];
			end
			`AND: begin
				reg_d[dest] = reg_q[arg1] & reg_q[arg2];
			end
			`OR: begin
				reg_d[dest] = reg_q[arg1] | reg_q[arg2];
			end
			`INV: begin
				reg_d[dest] = ~reg_q[arg1];
			end
			`XOR: begin
				reg_d[dest] = reg_q[arg1] ^ reg_q[arg2];
			end
		endcase





	end
	
	always @(posedge clk) begin

		for (i=0; i<16; i=i+1) begin
			reg_q[i] <= reg_d[i];
		end
	end

endmodule