data/full_repos/permissive/174323821/hdl/cpu/63701/jt63701.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/174323821/hdl/cpu/63701/jt63701.v:88: Signal definition not found, creating implicitly: \'cen_rise2\'\n    .cen_rise2   ( cen_rise2     ),\n                   ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/174323821/hdl/cpu/63701/jt63701.v:89: Signal definition not found, creating implicitly: \'cen_fall2\'\n    .cen_fall2   ( cen_fall2     ),\n                   ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/174323821/hdl/cpu/63701/jt63701.v:139: Signal definition not found, creating implicitly: \'cen_fall\'\n                                                                                   : ... Suggested alternative: \'cen_fall2\'\n    core_cen0 <= cen_fall & waitn & halted_n;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/jt63701.v:140: Can\'t find definition of variable: \'cen_rise\'\n                                                                        : ... Suggested alternative: \'cen_rise2\'\n    core_cen1 <= cen_rise & waitn & halted_n;\n                 ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module HD63701_IOPort (
    input              rst,
    input              clk,
    input       [15:0] mcu_ad,
    input              mcu_wr,
    input        [7:0] mcu_do,

    output             en_io,
    output reg   [7:0] iod,

    input        [7:0] PI1,
    input        [4:0] PI2,
    input        [7:0] PI6,

    output reg   [7:0] PO1,
    output reg   [4:0] PO2,
    output reg   [7:0] PO6
);

    always @( posedge clk or posedge rst ) begin
        if (rst) begin
                PO1 <= 8'hFF;
                PO2 <= 5'h1F;
                PO6 <= 8'hFF;
            end else begin
            if (mcu_wr) begin
                case( mcu_ad )
                    16'h02: PO1 <= mcu_do;
                    16'h03: PO2 <= mcu_do[4:0];
                    16'h17: PO6 <= mcu_do;
                endcase
            end
        end
    end

    assign en_io = (mcu_ad==16'h2)|(mcu_ad==16'h3)|(mcu_ad==16'h17);

    always @(*) begin
        case( mcu_ad[4:0] )
            5'h02:   iod = PI1;
            5'h03:   iod = {3'b111,PI2};
            5'h17:   iod = PI6;
            default: iod = 8'hff;
        endcase
    end
endmodule
module HD63701_IOPort (
    input              rst,
    input              clk,
    input       [15:0] mcu_ad,
    input              mcu_wr,
    input        [7:0] mcu_do,

    output             en_io,
    output reg   [7:0] iod,

    input        [7:0] PI1,
    input        [4:0] PI2,
    input        [7:0] PI6,

    output reg   [7:0] PO1,
    output reg   [4:0] PO2,
    output reg   [7:0] PO6
);


    always @( posedge clk or posedge rst ) begin
        if (rst) begin
                PO1 <= 8'hFF;
                PO2 <= 5'h1F;
                PO6 <= 8'hFF;
            end else begin
            if (mcu_wr) begin
                case( mcu_ad )
                    16'h02: PO1 <= mcu_do;
                    16'h03: PO2 <= mcu_do[4:0];
                    16'h17: PO6 <= mcu_do;
                endcase
            end
        end
    end

    assign en_io = (mcu_ad==16'h2)|(mcu_ad==16'h3)|(mcu_ad==16'h17);

    always @(*) begin
        case( mcu_ad[4:0] )
            5'h02:   iod = PI1;
            5'h03:   iod = {3'b111,PI2};
            5'h17:   iod = PI6;
            default: iod = 8'hff;
        endcase
    end
endmodule