data/full_repos/permissive/104784866/SBox/Verilog/src/SBox.v
1: b"%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox.v:116: Cannot find file containing module: 'MDimMux'\n   MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104784866/SBox/Verilog/src,data/full_repos/permissive/104784866/MDimMux\n             data/full_repos/permissive/104784866/SBox/Verilog/src,data/full_repos/permissive/104784866/MDimMux.v\n             data/full_repos/permissive/104784866/SBox/Verilog/src,data/full_repos/permissive/104784866/MDimMux.sv\n             MDimMux\n             MDimMux.v\n             MDimMux.sv\n             obj_dir/MDimMux\n             obj_dir/MDimMux.v\n             obj_dir/MDimMux.sv\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox.v:129: Cannot find file containing module: 'MDimMux'\n   MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(\n   ^~~~~~~\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox.v:142: Cannot find file containing module: 'MDimMux'\n   MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(\n   ^~~~~~~\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox.v:155: Cannot find file containing module: 'MDimMux'\n   MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(\n   ^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module SBox#(

		parameter UID = 0,

		parameter DIMENSION = 4,

		parameter CH_UP_WIDTH = 2,

		parameter CH_DN_WIDTH = 2,

		parameter UID_WIDTH = 16,

		parameter DIMENSION_WIDTH = 2,

		parameter CH_WIDTH_WIDTH = 2
	) (

		mode,
		c_clk,
		c_bus,
		c_uid,
		c_dimension,


		ch_up_n,
		ch_up_s,
		ch_dn_n,
		ch_dn_s,


		ch_lt_n,
		ch_lt_s,
		ch_rt_n,
		ch_rt_s
	);


	parameter CONFIG_WORD_WIDTH = (DIMENSION*(CH_WIDTH_WIDTH+1))+(CH_WIDTH_WIDTH+1);


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [UID_WIDTH-1:0] c_uid;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	output [CH_UP_WIDTH-1:0] ch_up_n;
	input [CH_UP_WIDTH-1:0] ch_up_s;
	input [CH_DN_WIDTH-1:0] ch_dn_n;
	output [CH_DN_WIDTH-1:0] ch_dn_s;


	output [CH_UP_WIDTH-1:0] ch_lt_n;
	input [CH_UP_WIDTH-1:0] ch_lt_s;
	input [CH_DN_WIDTH-1:0] ch_rt_n;
	output [CH_DN_WIDTH-1:0] ch_rt_s;


	genvar i;
	generate

		for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : MDimMuxGen
			wire filteredClk = c_clk && (i == `C_BUS_MUX_ADDR) && (UID == c_uid);
			MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus(`C_BUS_MUX_SWITCH),
				.c_dimension(c_dimension),

				.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
				.ch_out(ch_up_n[i])
			);
		end

		for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : MDimMuxGen2
			wire filteredClk = c_clk && ((i + CH_UP_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
			MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus(`C_BUS_MUX_SWITCH),
				.c_dimension(c_dimension),

				.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
				.ch_out(ch_lt_n[i])
			);
		end

		for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : MDimMuxGen3
			wire filteredClk = c_clk && ((i + CH_UP_WIDTH + CH_UP_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
			MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus(`C_BUS_MUX_SWITCH),
				.c_dimension(c_dimension),

				.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
				.ch_out(ch_dn_s[i])
			);
		end

		for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : MDimMuxGen4
			wire filteredClk = c_clk && ((i + CH_UP_WIDTH + CH_UP_WIDTH + CH_DN_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
			MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus(`C_BUS_MUX_SWITCH),
				.c_dimension(c_dimension),

				.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
				.ch_out(ch_rt_s[i])
			);
		end
	endgenerate

endmodule
module SBox#(

		parameter UID = 0,

		parameter DIMENSION = 4,

		parameter CH_UP_WIDTH = 2,

		parameter CH_DN_WIDTH = 2,

		parameter UID_WIDTH = 16,

		parameter DIMENSION_WIDTH = 2,

		parameter CH_WIDTH_WIDTH = 2
	) (

		mode,
		c_clk,
		c_bus,
		c_uid,
		c_dimension,


		ch_up_n,
		ch_up_s,
		ch_dn_n,
		ch_dn_s,


		ch_lt_n,
		ch_lt_s,
		ch_rt_n,
		ch_rt_s
	);



	parameter CONFIG_WORD_WIDTH = (DIMENSION*(CH_WIDTH_WIDTH+1))+(CH_WIDTH_WIDTH+1);


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [UID_WIDTH-1:0] c_uid;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	output [CH_UP_WIDTH-1:0] ch_up_n;
	input [CH_UP_WIDTH-1:0] ch_up_s;
	input [CH_DN_WIDTH-1:0] ch_dn_n;
	output [CH_DN_WIDTH-1:0] ch_dn_s;


	output [CH_UP_WIDTH-1:0] ch_lt_n;
	input [CH_UP_WIDTH-1:0] ch_lt_s;
	input [CH_DN_WIDTH-1:0] ch_rt_n;
	output [CH_DN_WIDTH-1:0] ch_rt_s;


	genvar i;
	generate

		for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : MDimMuxGen
			wire filteredClk = c_clk && (i == `C_BUS_MUX_ADDR) && (UID == c_uid);
			MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus(`C_BUS_MUX_SWITCH),
				.c_dimension(c_dimension),

				.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
				.ch_out(ch_up_n[i])
			);
		end

		for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : MDimMuxGen2
			wire filteredClk = c_clk && ((i + CH_UP_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
			MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus(`C_BUS_MUX_SWITCH),
				.c_dimension(c_dimension),

				.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
				.ch_out(ch_lt_n[i])
			);
		end

		for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : MDimMuxGen3
			wire filteredClk = c_clk && ((i + CH_UP_WIDTH + CH_UP_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
			MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus(`C_BUS_MUX_SWITCH),
				.c_dimension(c_dimension),

				.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
				.ch_out(ch_dn_s[i])
			);
		end

		for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : MDimMuxGen4
			wire filteredClk = c_clk && ((i + CH_UP_WIDTH + CH_UP_WIDTH + CH_DN_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
			MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus(`C_BUS_MUX_SWITCH),
				.c_dimension(c_dimension),

				.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
				.ch_out(ch_rt_s[i])
			);
		end
	endgenerate

endmodule