data/full_repos/permissive/122125962/floodcasting/verilog/audio_dac_tb.v
 line:30: before: "@"
1: b'%Error: data/full_repos/permissive/122125962/floodcasting/verilog/audio_dac_tb.v:29: syntax error, unexpected \'@\'\n @ (posedge clk)\n ^\n%Error: data/full_repos/permissive/122125962/floodcasting/verilog/audio_dac_tb.v:40: syntax error, unexpected \'@\'\n @ (posedge clk)\n ^\n%Error: data/full_repos/permissive/122125962/floodcasting/verilog/audio_dac_tb.v:51: syntax error, unexpected \'@\'\n @ (posedge clk)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/122125962/floodcasting/verilog/audio_dac_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module testbench();

reg		clk, resetn;
reg		[15:0] data_a, data_b;
reg		start;
reg		debug;
reg		[2:0] command;
reg		[2:0] addr;
wire	ready;
wire	ldac;
wire	clr;
wire	din;
wire	sclk;
wire	sync;

audio_dac_write dac0( clk, resetn, data_a, data_b, start, debug, command, addr, ready, ldac, clr, din, sclk, sync);

initial
begin
	clk = 0;
	resetn = 1;
	data_a = 0;
	data_b = 0;
	start = 0;
	debug = 0;
	command = 0;
	addr = 0;

	@ (posedge clk)
	@ (posedge clk)
	@ (posedge clk)
		#1 resetn = 0;

	@ (posedge clk)
	@ (posedge clk)
	@ (posedge clk)
		#1 resetn = 1;
		data_a = 16'habcd;
		data_b = 16'h1234;
	@ (posedge clk)
		#1 start = 1;
	@ (negedge ready)
		start = 0;
	
	@ (posedge ready)
		#100 
		data_a = 16'hfa5f;
		addr = 3'b110;
		command = 3'b010;
		debug = 1;
	@ (posedge clk)
		#1 start = 1;
	@ (negedge ready)
		start = 0;
	
	@ (posedge ready)
		#100 $stop;

	
		
	
	
end

always #5 clk = ~clk;
endmodule
module testbench();


reg		clk, resetn;
reg		[15:0] data_a, data_b;
reg		start;
reg		debug;
reg		[2:0] command;
reg		[2:0] addr;
wire	ready;
wire	ldac;
wire	clr;
wire	din;
wire	sclk;
wire	sync;

audio_dac_write dac0( clk, resetn, data_a, data_b, start, debug, command, addr, ready, ldac, clr, din, sclk, sync);

initial
begin
	clk = 0;
	resetn = 1;
	data_a = 0;
	data_b = 0;
	start = 0;
	debug = 0;
	command = 0;
	addr = 0;

	@ (posedge clk)
	@ (posedge clk)
	@ (posedge clk)
		#1 resetn = 0;

	@ (posedge clk)
	@ (posedge clk)
	@ (posedge clk)
		#1 resetn = 1;
		data_a = 16'habcd;
		data_b = 16'h1234;
	@ (posedge clk)
		#1 start = 1;
	@ (negedge ready)
		start = 0;
	
	@ (posedge ready)
		#100 
		data_a = 16'hfa5f;
		addr = 3'b110;
		command = 3'b010;
		debug = 1;
	@ (posedge clk)
		#1 start = 1;
	@ (negedge ready)
		start = 0;
	
	@ (posedge ready)
		#100 $stop;

	
		
	
	
end

always #5 clk = ~clk;
endmodule