data/full_repos/permissive/179451217/fifo_async.v
1: b"%Error: data/full_repos/permissive/179451217/fifo_async.v:101: Cannot find file containing module: 'ram_dp'\nram_dp #(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179451217,data/full_repos/permissive/179451217/ram_dp\n             data/full_repos/permissive/179451217,data/full_repos/permissive/179451217/ram_dp.v\n             data/full_repos/permissive/179451217,data/full_repos/permissive/179451217/ram_dp.sv\n             ram_dp\n             ram_dp.v\n             ram_dp.sv\n             obj_dir/ram_dp\n             obj_dir/ram_dp.v\n             obj_dir/ram_dp.sv\n%Error: data/full_repos/permissive/179451217/fifo_async.v:133: Cannot find file containing module: 'synchronizer'\nsynchronizer #(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/179451217/fifo_async.v:145: Cannot find file containing module: 'synchronizer'\nsynchronizer #(\n^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module fifo_async #(
    parameter DataWidth = 16,
    parameter DataDepth = 1024,
    parameter AddrWidth = 10,
    parameter SyncStages = 2,
    parameter InitFile = "",
    parameter InitCount = 0,
    parameter VendorImpl = ""
) (
    input wire write_clk,
    input wire write_reset,
    input wire write_en,
    input wire [DataWidth-1:0] write_data,
    output reg fifo_full,

    input wire read_clk,
    input wire read_reset,
    input wire read_en,
    output wire [DataWidth-1:0] read_data,
    output reg fifo_empty
);

function [AddrWidth:0] bin_to_gray;
    input [AddrWidth:0] bin;
    bin_to_gray = {bin[AddrWidth], bin[AddrWidth:1] ^ bin[AddrWidth-1:0]};
endfunction




reg [AddrWidth:0] write_addr, write_addr_D;
reg [AddrWidth:0] write_addr_gray, write_addr_gray_D;
wire [AddrWidth:0] read_addr_gray_sync;
reg fifo_full_D;

wire write_en_not_full = (write_en == 1'b1 && fifo_full == 1'b0);




reg [AddrWidth:0] read_addr, read_addr_D;
reg [AddrWidth:0] read_addr_gray, read_addr_gray_D;
wire [AddrWidth:0] write_addr_gray_sync;
reg fifo_empty_D;

wire read_en_not_empty = (read_en == 1'b1 && fifo_empty == 1'b0);




ram_dp #(
    .DataWidth(DataWidth),
    .DataDepth(DataDepth),
    .AddrWidth(AddrWidth),
    .InitFile(InitFile),
    .InitValue(0),
    .InitCount(InitCount),
    .VendorImpl(VendorImpl)
) mem (
    .write_clk(write_clk),
    .write_en(write_en_not_full),
    .write_addr(write_addr[AddrWidth-1:0]),
    .write_data(write_data),
    .read_clk(read_clk),
    .read_en(1'b1),
    .read_addr(read_addr_D[AddrWidth-1:0]),
    .read_data(read_data)
);


generate
if(InitCount > 0) initial begin
    write_addr = InitCount;
    write_addr_gray = bin_to_gray(InitCount);
    read_addr = 0;
    read_addr_gray = 0;
    fifo_full = (InitCount == DataDepth);
    fifo_empty = 0;
end
endgenerate


synchronizer #(
    .Width(AddrWidth+1),
    .Stages(SyncStages),
    .Init(InitCount),
    .InitValue(0)
) write_clk_sync (
    .clk(write_clk),
    .reset(write_reset),
    .in(read_addr_gray),
    .out(read_addr_gray_sync)
);

synchronizer #(
    .Width(AddrWidth+1),
    .Stages(SyncStages),
    .Init(InitCount),
    .InitValue(bin_to_gray(InitCount))
) read_clk_sync (
    .clk(read_clk),
    .reset(read_reset),
    .in(write_addr_gray),
    .out(write_addr_gray_sync)
);


always @* begin

    write_addr_D = write_addr;
    if(write_en_not_full) begin
        write_addr_D = write_addr + 1;
    end

    write_addr_gray_D = bin_to_gray(write_addr_D);
    

    fifo_full_D = 
        (write_addr_gray_D == {~read_addr_gray_sync[AddrWidth:AddrWidth-1],
                                read_addr_gray_sync[AddrWidth-2:0]});


    read_addr_D = read_addr;
    if(read_en_not_empty) begin
        read_addr_D = read_addr + 1;
    end

    read_addr_gray_D = bin_to_gray(read_addr_D);
    

    fifo_empty_D = (read_addr_gray_D == write_addr_gray_sync);
end


always @(posedge write_clk or posedge write_reset) begin
    if(write_reset) begin
        write_addr <= 0;
        write_addr_gray <= 0;
        fifo_full <= 1'b0;
    end else begin
        write_addr <= write_addr_D;
        write_addr_gray <= write_addr_gray_D;
        fifo_full <= fifo_full_D;
    end
end


always @(posedge read_clk or posedge read_reset) begin
    if(read_reset) begin
        read_addr <= 0;
        read_addr_gray <= 0;
        fifo_empty <= 1'b1;
    end else begin
        read_addr <= read_addr_D;
        read_addr_gray <= read_addr_gray_D;
        fifo_empty <= fifo_empty_D;
    end
end

endmodule
module fifo_async #(
    parameter DataWidth = 16,
    parameter DataDepth = 1024,
    parameter AddrWidth = 10,
    parameter SyncStages = 2,
    parameter InitFile = "",
    parameter InitCount = 0,
    parameter VendorImpl = ""
) (
    input wire write_clk,
    input wire write_reset,
    input wire write_en,
    input wire [DataWidth-1:0] write_data,
    output reg fifo_full,

    input wire read_clk,
    input wire read_reset,
    input wire read_en,
    output wire [DataWidth-1:0] read_data,
    output reg fifo_empty
);


function [AddrWidth:0] bin_to_gray;
    input [AddrWidth:0] bin;
    bin_to_gray = {bin[AddrWidth], bin[AddrWidth:1] ^ bin[AddrWidth-1:0]};
endfunction




reg [AddrWidth:0] write_addr, write_addr_D;
reg [AddrWidth:0] write_addr_gray, write_addr_gray_D;
wire [AddrWidth:0] read_addr_gray_sync;
reg fifo_full_D;

wire write_en_not_full = (write_en == 1'b1 && fifo_full == 1'b0);




reg [AddrWidth:0] read_addr, read_addr_D;
reg [AddrWidth:0] read_addr_gray, read_addr_gray_D;
wire [AddrWidth:0] write_addr_gray_sync;
reg fifo_empty_D;

wire read_en_not_empty = (read_en == 1'b1 && fifo_empty == 1'b0);




ram_dp #(
    .DataWidth(DataWidth),
    .DataDepth(DataDepth),
    .AddrWidth(AddrWidth),
    .InitFile(InitFile),
    .InitValue(0),
    .InitCount(InitCount),
    .VendorImpl(VendorImpl)
) mem (
    .write_clk(write_clk),
    .write_en(write_en_not_full),
    .write_addr(write_addr[AddrWidth-1:0]),
    .write_data(write_data),
    .read_clk(read_clk),
    .read_en(1'b1),
    .read_addr(read_addr_D[AddrWidth-1:0]),
    .read_data(read_data)
);


generate
if(InitCount > 0) initial begin
    write_addr = InitCount;
    write_addr_gray = bin_to_gray(InitCount);
    read_addr = 0;
    read_addr_gray = 0;
    fifo_full = (InitCount == DataDepth);
    fifo_empty = 0;
end
endgenerate


synchronizer #(
    .Width(AddrWidth+1),
    .Stages(SyncStages),
    .Init(InitCount),
    .InitValue(0)
) write_clk_sync (
    .clk(write_clk),
    .reset(write_reset),
    .in(read_addr_gray),
    .out(read_addr_gray_sync)
);

synchronizer #(
    .Width(AddrWidth+1),
    .Stages(SyncStages),
    .Init(InitCount),
    .InitValue(bin_to_gray(InitCount))
) read_clk_sync (
    .clk(read_clk),
    .reset(read_reset),
    .in(write_addr_gray),
    .out(write_addr_gray_sync)
);


always @* begin

    write_addr_D = write_addr;
    if(write_en_not_full) begin
        write_addr_D = write_addr + 1;
    end

    write_addr_gray_D = bin_to_gray(write_addr_D);
    

    fifo_full_D = 
        (write_addr_gray_D == {~read_addr_gray_sync[AddrWidth:AddrWidth-1],
                                read_addr_gray_sync[AddrWidth-2:0]});


    read_addr_D = read_addr;
    if(read_en_not_empty) begin
        read_addr_D = read_addr + 1;
    end

    read_addr_gray_D = bin_to_gray(read_addr_D);
    

    fifo_empty_D = (read_addr_gray_D == write_addr_gray_sync);
end


always @(posedge write_clk or posedge write_reset) begin
    if(write_reset) begin
        write_addr <= 0;
        write_addr_gray <= 0;
        fifo_full <= 1'b0;
    end else begin
        write_addr <= write_addr_D;
        write_addr_gray <= write_addr_gray_D;
        fifo_full <= fifo_full_D;
    end
end


always @(posedge read_clk or posedge read_reset) begin
    if(read_reset) begin
        read_addr <= 0;
        read_addr_gray <= 0;
        fifo_empty <= 1'b1;
    end else begin
        read_addr <= read_addr_D;
        read_addr_gray <= read_addr_gray_D;
        fifo_empty <= fifo_empty_D;
    end
end

endmodule