data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v
None: at end of input
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:49: Cannot find include file: uart_defines.v\n`include "uart_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog,data/full_repos/permissive/17099167/uart_defines.v\n             data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog,data/full_repos/permissive/17099167/uart_defines.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog,data/full_repos/permissive/17099167/uart_defines.v.sv\n             uart_defines.v\n             uart_defines.v.v\n             uart_defines.v.sv\n             obj_dir/uart_defines.v\n             obj_dir/uart_defines.v.v\n             obj_dir/uart_defines.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:50: Cannot find include file: uart_testbench_defines.v\n`include "uart_testbench_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:51: Cannot find include file: wb_model_defines.v\n`include "wb_model_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:52: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:64: Define or directive not defined: \'`UTILS_MSG\'\n    `UTILS_MSG("RESET signal asynchronously set.");\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:64: syntax error, unexpected \';\'\n    `UTILS_MSG("RESET signal asynchronously set.");\n                                                  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:71: syntax error, unexpected \'@\'\n    @(posedge testbench.wb_clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:74: Define or directive not defined: \'`UTILS_MSG\'\n    `UTILS_MSG("RESET signal released synchronously to WB clk.");\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:74: syntax error, unexpected \';\'\n    `UTILS_MSG("RESET signal released synchronously to WB clk.");\n                                                                ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:85: Define or directive not defined: \'`UTILS_MSG\'\n    `UTILS_MSG("Following clocks are DISABLED:");\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:85: syntax error, unexpected \';\'\n    `UTILS_MSG("Following clocks are DISABLED:");\n                                                ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:89: Define or directive not defined: \'`UTILS_MSG\'\n      `UTILS_MSG("- WB_clk");\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:89: syntax error, unexpected \';\'\n      `UTILS_MSG("- WB_clk");\n                            ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:94: Define or directive not defined: \'`UTILS_MSG\'\n      `UTILS_MSG("- RX_clk");\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:94: syntax error, unexpected \';\'\n      `UTILS_MSG("- RX_clk");\n                            ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:99: Define or directive not defined: \'`UTILS_MSG\'\n      `UTILS_MSG("- TX_clk");\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:99: syntax error, unexpected \';\'\n      `UTILS_MSG("- TX_clk");\n                            ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:104: Define or directive not defined: \'`UTILS_MSG\'\n      `UTILS_MSG("- TX_clk_divided");\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:104: syntax error, unexpected \';\'\n      `UTILS_MSG("- TX_clk_divided");\n                                    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:108: Define or directive not defined: \'`UTILS_MSG\'\n      `UTILS_MSG("- NO clocks DISABLED");\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:108: syntax error, unexpected \';\'\n      `UTILS_MSG("- NO clocks DISABLED");\n                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:120: Define or directive not defined: \'`UTILS_MSG\'\n    `UTILS_MSG("Following clocks are ENABLED:");\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:120: syntax error, unexpected \';\'\n    `UTILS_MSG("Following clocks are ENABLED:");\n                                               ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:124: Define or directive not defined: \'`UTILS_MSG\'\n      `UTILS_MSG("- WB_clk");\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:124: syntax error, unexpected \';\'\n      `UTILS_MSG("- WB_clk");\n                            ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:129: Define or directive not defined: \'`UTILS_MSG\'\n      `UTILS_MSG("- RX_clk");\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:129: syntax error, unexpected \';\'\n      `UTILS_MSG("- RX_clk");\n                            ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:134: Define or directive not defined: \'`UTILS_MSG\'\n      `UTILS_MSG("- TX_clk");\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:134: syntax error, unexpected \';\'\n      `UTILS_MSG("- TX_clk");\n                            ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:139: Define or directive not defined: \'`UTILS_MSG\'\n      `UTILS_MSG("- TX_clk_divided");\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:139: syntax error, unexpected \';\'\n      `UTILS_MSG("- TX_clk_divided");\n                                    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:143: Define or directive not defined: \'`UTILS_MSG\'\n      `UTILS_MSG("- NO clocks ENABLED");\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:143: syntax error, unexpected \';\'\n      `UTILS_MSG("- NO clocks ENABLED");\n                                       ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:153: Define or directive not defined: \'`UTILS_VAL1\'\n    `UTILS_VAL1("UART DEVICE TX/RX clock period:", clk_period);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:153: syntax error, unexpected \',\'\n    `UTILS_VAL1("UART DEVICE TX/RX clock period:", clk_period);\n                                                 ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:162: Define or directive not defined: \'`UTILS_VAL1\'\n    `UTILS_VAL1("UART DEVICE TX clock delay:", tx_clk_delay);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:162: syntax error, unexpected \',\'\n    `UTILS_VAL1("UART DEVICE TX clock delay:", tx_clk_delay);\n                                             ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:171: Define or directive not defined: \'`UTILS_VAL1\'\n    `UTILS_VAL1("UART DEVICE TX/RX clock divisor:", clk_divisor);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:171: syntax error, unexpected \',\'\n    `UTILS_VAL1("UART DEVICE TX/RX clock divisor:", clk_divisor);\n                                                  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:181: Define or directive not defined: \'`UTILS_VAL1\'\n    `UTILS_VAL1("WB & UART DEVICE TX/RX clock period:", clk_period);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:181: syntax error, unexpected \',\'\n    `UTILS_VAL1("WB & UART DEVICE TX/RX clock period:", clk_period);\n                                                      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:191: syntax error, unexpected \'@\'\n    @(posedge testbench.wb_clk);\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:193: syntax error, unexpected \'@\'\n    @(posedge testbench.i_uart_device.rx_clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:194: Unsupported: Ignoring delay on this delayed statement.\n    #time_delay testbench.wb_clk = 1\'b1;\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:196: Define or directive not defined: \'`UTILS_VAL1\'\n    `UTILS_VAL1("WB followed UART DEVICE rising edge RX clock for time delay:", time_delay);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:196: syntax error, unexpected \',\'\n    `UTILS_VAL1("WB followed UART DEVICE rising edge RX clock for time delay:", time_delay);\n                                                                              ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:206: syntax error, unexpected \'@\'\n    @(posedge testbench.i_uart_device.rx_clk);\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:208: syntax error, unexpected \'@\'\n    @(posedge testbench.wb_clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:209: Unsupported: Ignoring delay on this delayed statement.\n    #time_delay testbench.i_uart_device.rx_clk = 1\'b1;\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:211: Define or directive not defined: \'`UTILS_VAL1\'\n    `UTILS_VAL1("UART DEVICE RX followed WB rising edge clock for time delay:", time_delay);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:211: syntax error, unexpected \',\'\n    `UTILS_VAL1("UART DEVICE RX followed WB rising edge clock for time delay:", time_delay);\n                                                                              ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/uart_testbench_utilities.v:224: Define or directive not defined: \'`UTILS_VAL1\'\n    `UTILS_VAL1("Waiting for following number of WB CLK periods:", num_of_clk);\n    ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module testbench_utilities;





  task do_reset;
  begin
    testbench.wb_reset = 1'b1;
    #1;
    `UTILS_MSG("RESET signal asynchronously set.");
  end
  endtask


  task release_reset;
  begin
    @(posedge testbench.wb_clk);
    #1;
    testbench.wb_reset = 1'b0;
    `UTILS_MSG("RESET signal released synchronously to WB clk.");
  end
  endtask


  task disable_clk_generators;
    input         wb_clk_disable;
    input         rx_clk_disable;
    input         tx_clk_disable;
    input         tx_clk_divided_disable;
  begin
    `UTILS_MSG("Following clocks are DISABLED:");
    if (wb_clk_disable)
    begin
      testbench.wb_clk_en = 1'b0;
      `UTILS_MSG("- WB_clk");
    end
    if (rx_clk_disable)
    begin
      testbench.i_uart_device.rx_clk_en = 1'b0;
      `UTILS_MSG("- RX_clk");
    end
    if (tx_clk_disable)
    begin
      testbench.i_uart_device.tx_clk_en = 1'b0;
      `UTILS_MSG("- TX_clk");
    end
    if (tx_clk_divided_disable)
    begin
      testbench.i_uart_device.tx_clk_divided_en = 1'b0;
      `UTILS_MSG("- TX_clk_divided");
    end
    if (~wb_clk_disable && ~rx_clk_disable && ~tx_clk_disable && ~tx_clk_divided_disable)
    begin
      `UTILS_MSG("- NO clocks DISABLED");
    end
  end
  endtask


  task enable_clk_generators;
    input         wb_clk_enable;
    input         rx_clk_enable;
    input         tx_clk_enable;
    input         tx_clk_divided_enable;
  begin
    `UTILS_MSG("Following clocks are ENABLED:");
    if (wb_clk_enable)
    begin
      testbench.wb_clk_en = 1'b1;
      `UTILS_MSG("- WB_clk");
    end
    if (rx_clk_enable)
    begin
      testbench.i_uart_device.rx_clk_en = 1'b1;
      `UTILS_MSG("- RX_clk");
    end
    if (tx_clk_enable)
    begin
      testbench.i_uart_device.tx_clk_en = 1'b1;
      `UTILS_MSG("- TX_clk");
    end
    if (tx_clk_divided_enable)
    begin
      testbench.i_uart_device.tx_clk_divided_en = 1'b1;
      `UTILS_MSG("- TX_clk_divided");
    end
    if (~wb_clk_enable && ~rx_clk_enable && ~tx_clk_enable && ~tx_clk_divided_enable)
    begin
      `UTILS_MSG("- NO clocks ENABLED");
    end
  end
  endtask


  task set_device_tx_rx_clk_period;
    input [31:0]  clk_period;
  begin
    testbench.i_uart_device.T_clk_period = clk_period;
    `UTILS_VAL1("UART DEVICE TX/RX clock period:", clk_period);
  end
  endtask


  task set_device_tx_clk_delay;
    input [31:0]  tx_clk_delay;
  begin
    testbench.i_uart_device.T_clk_delay = tx_clk_delay;
    `UTILS_VAL1("UART DEVICE TX clock delay:", tx_clk_delay);
  end
  endtask


  task set_device_tx_rx_clk_divisor;
    input [31:0]  clk_divisor;
  begin
    testbench.i_uart_device.T_divisor = clk_divisor;
    `UTILS_VAL1("UART DEVICE TX/RX clock divisor:", clk_divisor);
  end
  endtask


  task set_wb_clock_period;
    input [31:0]  clk_period;
  begin
    testbench.T_wb_clk_period = clk_period;
    testbench.i_uart_device.T_clk_period = clk_period;
    `UTILS_VAL1("WB & UART DEVICE TX/RX clock period:", clk_period);
  end
  endtask


  task wb_clk_follows_device_rx_clk;
    input [31:0]  time_delay_i;
    integer       time_delay;
  begin
    time_delay = time_delay_i;
    @(posedge testbench.wb_clk);
    testbench.wb_clk_en = 1'b0;
    @(posedge testbench.i_uart_device.rx_clk);
    #time_delay testbench.wb_clk = 1'b1;
    testbench.wb_clk_en = 1'b1;
    `UTILS_VAL1("WB followed UART DEVICE rising edge RX clock for time delay:", time_delay);
  end
  endtask


  task device_rx_clk_follows_wb_clk;
    input [31:0]  time_delay_i;
    integer       time_delay;
  begin
    time_delay = time_delay_i;
    @(posedge testbench.i_uart_device.rx_clk);
    testbench.i_uart_device.rx_clk_en = 1'b0;
    @(posedge testbench.wb_clk);
    #time_delay testbench.i_uart_device.rx_clk = 1'b1;
    testbench.i_uart_device.rx_clk_en = 1'b1;
    `UTILS_VAL1("UART DEVICE RX followed WB rising edge clock for time delay:", time_delay);
  end
  endtask
  




  task wait_for_num_of_wb_clk;
    input [31:0]  num_of_clk;
    integer       count;
  begin
    count = 0;
    `UTILS_VAL1("Waiting for following number of WB CLK periods:", num_of_clk);
    while (count < num_of_clk)
    begin
      @(testbench.wb_clk);
      count = count + 1'b1;
      #1;
    end
    `UTILS_MSG("Waiting expired.");
  end
  endtask


  task wait_rx_fifo_full_regardless_int;
    integer count;
  begin
    count = 0;
    `UTILS_MSG("Waiting for RX FIFO to get full regardless of interrupt.");
    fork
    begin:fifo_full_loop
      while (testbench.i_uart_top.regs.receiver.fifo_rx.count <
             testbench.i_uart_top.regs.receiver.fifo_rx.fifo_depth)
      begin
        @(testbench.wb_clk);
      end
      disable counter;
      `UTILS_MSG("RX FIFO got full.");
    end
    begin:counter
      while (count < testbench.max_wait_cnt)
      begin
        @(testbench.wb_clk);
        count = count + 1'b1;
        #1;
      end
      disable fifo_full_loop;
      `UTILS_ERROR("WAIT counter exceeded max value.");
    end
    join
  end
  endtask


  task wait_rx_fifo_full_unless_int;
    integer count;
  begin
    count = 0;
    `UTILS_MSG("Waiting for RX FIFO to get full unless interrupt occures before.");
    fork
    begin:fifo_full_loop
      while (testbench.i_uart_top.regs.receiver.fifo_rx.count <
             testbench.i_uart_top.regs.receiver.fifo_rx.fifo_depth)
      begin
        @(testbench.wb_clk);
      end
      disable counter;
      disable int_loop;
      `UTILS_MSG("RX FIFO got full.");
    end
    begin:int_loop
      if (testbench.ier_reg[3:0] == 4'h0)
      begin
        `UTILS_MSG("All interrupts are disabled.");
      end
      else
      begin
        `UTILS_MSG("Interrupts are enabled in IE Register.");
        `UTILS_VAL1("IER:", testbench.ier_reg);
        @(testbench.int_aserted);
        `UTILS_MSG("Interrupt is asserted. The pending interrupt of highest priority is in II Register.");
        `UTILS_VAL1("IIR:", testbench.iir_reg);
        disable counter;
        disable fifo_full_loop;
      end
    end
    begin:counter
      while (count < testbench.max_wait_cnt)
      begin
        @(testbench.wb_clk);
        count = count + 1'b1;
        #1;
      end
      disable int_loop;
      disable fifo_full_loop;
      `UTILS_ERROR("WAIT counter exceeded max value.");
    end
    join
  end
  endtask








endmodule
module testbench_utilities;






  task do_reset;
  begin
    testbench.wb_reset = 1'b1;
    #1;
    `UTILS_MSG("RESET signal asynchronously set.");
  end
  endtask


  task release_reset;
  begin
    @(posedge testbench.wb_clk);
    #1;
    testbench.wb_reset = 1'b0;
    `UTILS_MSG("RESET signal released synchronously to WB clk.");
  end
  endtask


  task disable_clk_generators;
    input         wb_clk_disable;
    input         rx_clk_disable;
    input         tx_clk_disable;
    input         tx_clk_divided_disable;
  begin
    `UTILS_MSG("Following clocks are DISABLED:");
    if (wb_clk_disable)
    begin
      testbench.wb_clk_en = 1'b0;
      `UTILS_MSG("- WB_clk");
    end
    if (rx_clk_disable)
    begin
      testbench.i_uart_device.rx_clk_en = 1'b0;
      `UTILS_MSG("- RX_clk");
    end
    if (tx_clk_disable)
    begin
      testbench.i_uart_device.tx_clk_en = 1'b0;
      `UTILS_MSG("- TX_clk");
    end
    if (tx_clk_divided_disable)
    begin
      testbench.i_uart_device.tx_clk_divided_en = 1'b0;
      `UTILS_MSG("- TX_clk_divided");
    end
    if (~wb_clk_disable && ~rx_clk_disable && ~tx_clk_disable && ~tx_clk_divided_disable)
    begin
      `UTILS_MSG("- NO clocks DISABLED");
    end
  end
  endtask


  task enable_clk_generators;
    input         wb_clk_enable;
    input         rx_clk_enable;
    input         tx_clk_enable;
    input         tx_clk_divided_enable;
  begin
    `UTILS_MSG("Following clocks are ENABLED:");
    if (wb_clk_enable)
    begin
      testbench.wb_clk_en = 1'b1;
      `UTILS_MSG("- WB_clk");
    end
    if (rx_clk_enable)
    begin
      testbench.i_uart_device.rx_clk_en = 1'b1;
      `UTILS_MSG("- RX_clk");
    end
    if (tx_clk_enable)
    begin
      testbench.i_uart_device.tx_clk_en = 1'b1;
      `UTILS_MSG("- TX_clk");
    end
    if (tx_clk_divided_enable)
    begin
      testbench.i_uart_device.tx_clk_divided_en = 1'b1;
      `UTILS_MSG("- TX_clk_divided");
    end
    if (~wb_clk_enable && ~rx_clk_enable && ~tx_clk_enable && ~tx_clk_divided_enable)
    begin
      `UTILS_MSG("- NO clocks ENABLED");
    end
  end
  endtask


  task set_device_tx_rx_clk_period;
    input [31:0]  clk_period;
  begin
    testbench.i_uart_device.T_clk_period = clk_period;
    `UTILS_VAL1("UART DEVICE TX/RX clock period:", clk_period);
  end
  endtask


  task set_device_tx_clk_delay;
    input [31:0]  tx_clk_delay;
  begin
    testbench.i_uart_device.T_clk_delay = tx_clk_delay;
    `UTILS_VAL1("UART DEVICE TX clock delay:", tx_clk_delay);
  end
  endtask


  task set_device_tx_rx_clk_divisor;
    input [31:0]  clk_divisor;
  begin
    testbench.i_uart_device.T_divisor = clk_divisor;
    `UTILS_VAL1("UART DEVICE TX/RX clock divisor:", clk_divisor);
  end
  endtask


  task set_wb_clock_period;
    input [31:0]  clk_period;
  begin
    testbench.T_wb_clk_period = clk_period;
    testbench.i_uart_device.T_clk_period = clk_period;
    `UTILS_VAL1("WB & UART DEVICE TX/RX clock period:", clk_period);
  end
  endtask


  task wb_clk_follows_device_rx_clk;
    input [31:0]  time_delay_i;
    integer       time_delay;
  begin
    time_delay = time_delay_i;
    @(posedge testbench.wb_clk);
    testbench.wb_clk_en = 1'b0;
    @(posedge testbench.i_uart_device.rx_clk);
    #time_delay testbench.wb_clk = 1'b1;
    testbench.wb_clk_en = 1'b1;
    `UTILS_VAL1("WB followed UART DEVICE rising edge RX clock for time delay:", time_delay);
  end
  endtask


  task device_rx_clk_follows_wb_clk;
    input [31:0]  time_delay_i;
    integer       time_delay;
  begin
    time_delay = time_delay_i;
    @(posedge testbench.i_uart_device.rx_clk);
    testbench.i_uart_device.rx_clk_en = 1'b0;
    @(posedge testbench.wb_clk);
    #time_delay testbench.i_uart_device.rx_clk = 1'b1;
    testbench.i_uart_device.rx_clk_en = 1'b1;
    `UTILS_VAL1("UART DEVICE RX followed WB rising edge clock for time delay:", time_delay);
  end
  endtask
  




  task wait_for_num_of_wb_clk;
    input [31:0]  num_of_clk;
    integer       count;
  begin
    count = 0;
    `UTILS_VAL1("Waiting for following number of WB CLK periods:", num_of_clk);
    while (count < num_of_clk)
    begin
      @(testbench.wb_clk);
      count = count + 1'b1;
      #1;
    end
    `UTILS_MSG("Waiting expired.");
  end
  endtask


  task wait_rx_fifo_full_regardless_int;
    integer count;
  begin
    count = 0;
    `UTILS_MSG("Waiting for RX FIFO to get full regardless of interrupt.");
    fork
    begin:fifo_full_loop
      while (testbench.i_uart_top.regs.receiver.fifo_rx.count <
             testbench.i_uart_top.regs.receiver.fifo_rx.fifo_depth)
      begin
        @(testbench.wb_clk);
      end
      disable counter;
      `UTILS_MSG("RX FIFO got full.");
    end
    begin:counter
      while (count < testbench.max_wait_cnt)
      begin
        @(testbench.wb_clk);
        count = count + 1'b1;
        #1;
      end
      disable fifo_full_loop;
      `UTILS_ERROR("WAIT counter exceeded max value.");
    end
    join
  end
  endtask


  task wait_rx_fifo_full_unless_int;
    integer count;
  begin
    count = 0;
    `UTILS_MSG("Waiting for RX FIFO to get full unless interrupt occures before.");
    fork
    begin:fifo_full_loop
      while (testbench.i_uart_top.regs.receiver.fifo_rx.count <
             testbench.i_uart_top.regs.receiver.fifo_rx.fifo_depth)
      begin
        @(testbench.wb_clk);
      end
      disable counter;
      disable int_loop;
      `UTILS_MSG("RX FIFO got full.");
    end
    begin:int_loop
      if (testbench.ier_reg[3:0] == 4'h0)
      begin
        `UTILS_MSG("All interrupts are disabled.");
      end
      else
      begin
        `UTILS_MSG("Interrupts are enabled in IE Register.");
        `UTILS_VAL1("IER:", testbench.ier_reg);
        @(testbench.int_aserted);
        `UTILS_MSG("Interrupt is asserted. The pending interrupt of highest priority is in II Register.");
        `UTILS_VAL1("IIR:", testbench.iir_reg);
        disable counter;
        disable fifo_full_loop;
      end
    end
    begin:counter
      while (count < testbench.max_wait_cnt)
      begin
        @(testbench.wb_clk);
        count = count + 1'b1;
        #1;
      end
      disable int_loop;
      disable fifo_full_loop;
      `UTILS_ERROR("WAIT counter exceeded max value.");
    end
    join
  end
  endtask








endmodule