data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v
 line:64: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:110: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:114: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:64: Unsupported: Ignoring delay on this delayed statement.\ninitial #200 begin\n        ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:134: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    Mem[Address] = DataIn[7:0];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:138: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    Mem[Address] = DataIn[15:8];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:145: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    Mem[Address] = DataIn[31:24];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:155: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        Mem[Address] = DataIn[31:24];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:179: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        DataOut[7:0] = Mem[Address];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:189: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        DataOut[7:0] = Mem[Address];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:174: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    if(Mem[Address][7] == 1\'b1)\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:200: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        DataOut[15:8] = Mem[Address];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:209: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        DataOut[15:8] = Mem[Address];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:196: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    if(Mem[Address][7] == 1\'b1)\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:218: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    DataOut[31:24] = Mem[Address];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:228: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    DataOut[7:0] = Mem[Address];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:234: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    DataOut[15:8] = Mem[Address];\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:243: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        DataOut[31:24] = Mem[Address];\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:17: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                        : ... In instance Ram_access\n        ram1.Mem[Address] = data;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:17: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'data\' generates 32 bits.\n                                                                                        : ... In instance Ram_access\n        ram1.Mem[Address] = data;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:40: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                        : ... In instance Ram_access\n    $display("data in ram: address %h, data is %b", Address, ram1.Mem[Address]);\n                                                                     ^\n%Error: Exiting due to 36 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Ram_access;
integer fi, fo, code, i; reg [31:0] data;
reg Enable; reg [31:0] DataIn; wire almostdone, done;
reg [5:0] opcode;
reg [8:0] Address; wire [31:0] DataOut;
reg preload_done;
reg [4:0] count;

ram512x8 ram1 (DataOut, Enable, Address, DataIn, opcode, almostdone, done);

initial begin
    fi = $fopen("input_file.txt", "r");
    Address = 9'b000000000;
    while (!$feof(fi)) begin
        code = $fscanf(fi, "%b", data);
        ram1.Mem[Address] = data;
        Address = Address + 1;
    end
    $fclose(fi); 
    count = 5'd0;
end


always @ (posedge done) begin
    count = count + 1;
    if(opcode[5:3]==3'b101) begin
    case(opcode[2:0])
        3'b000: begin
        $display("%d: store byte:", count[3:0]);
        end
        3'b001: begin
        $display("%d: store halfword:", count[3:0]);
        end
        3'b011: begin
        $display("%d: store word:", count[3:0]);
        end
    endcase
    $display("sent to ram: opcode= %b, address= %h, data=%b", opcode, Address, DataIn);
    $display("data in ram: address %h, data is %b", Address, ram1.Mem[Address]);
    $display("store done");
    $display("----------------------------------------------------");
    end else begin
    case(opcode[2:0])
        3'b000: begin
        $display("%d: load byte:", count[3:0]);
        end
        3'b001: begin
        $display("%d: load halfword:", count[3:0]);
        end
        3'b011: begin
        $display("%d: load word:", count[3:0]);
        end
    endcase
    $display("sent to ram: opcode= %b, address= %h", opcode, Address);
    $display("data received: address %h, data is %b", Address, DataOut);

    $display("load done");
    $display("----------------------------------------------------");    
    end
end


initial #200 begin
    $display("enter");
    Address = 9'd4;

    opcode = 6'b100001;
    #2 Enable = 1'b0;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd0;
    opcode = 6'b101000;
    DataIn = 32'b10101010;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd2;
    opcode = 6'b101001;
    DataIn = 32'b0010101011111111;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd4;
    opcode = 6'b101001;
    DataIn = 32'b0111111110101010;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd8;
    opcode = 6'b101011;
    DataIn = 32'b10101010111111111010101011111111;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd0;
    opcode = 6'b100000;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd2;
    opcode = 6'b100001;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd4;
    opcode = 6'b100001;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd8;
    opcode = 6'b100011;
    #3 Enable = 1'b1;

end
endmodule
module Ram_access;

integer fi, fo, code, i; reg [31:0] data;
reg Enable; reg [31:0] DataIn; wire almostdone, done;
reg [5:0] opcode;
reg [8:0] Address; wire [31:0] DataOut;
reg preload_done;
reg [4:0] count;

ram512x8 ram1 (DataOut, Enable, Address, DataIn, opcode, almostdone, done);

initial begin
    fi = $fopen("input_file.txt", "r");
    Address = 9'b000000000;
    while (!$feof(fi)) begin
        code = $fscanf(fi, "%b", data);
        ram1.Mem[Address] = data;
        Address = Address + 1;
    end
    $fclose(fi); 
    count = 5'd0;
end


always @ (posedge done) begin
    count = count + 1;
    if(opcode[5:3]==3'b101) begin
    case(opcode[2:0])
        3'b000: begin
        $display("%d: store byte:", count[3:0]);
        end
        3'b001: begin
        $display("%d: store halfword:", count[3:0]);
        end
        3'b011: begin
        $display("%d: store word:", count[3:0]);
        end
    endcase
    $display("sent to ram: opcode= %b, address= %h, data=%b", opcode, Address, DataIn);
    $display("data in ram: address %h, data is %b", Address, ram1.Mem[Address]);
    $display("store done");
    $display("----------------------------------------------------");
    end else begin
    case(opcode[2:0])
        3'b000: begin
        $display("%d: load byte:", count[3:0]);
        end
        3'b001: begin
        $display("%d: load halfword:", count[3:0]);
        end
        3'b011: begin
        $display("%d: load word:", count[3:0]);
        end
    endcase
    $display("sent to ram: opcode= %b, address= %h", opcode, Address);
    $display("data received: address %h, data is %b", Address, DataOut);

    $display("load done");
    $display("----------------------------------------------------");    
    end
end


initial #200 begin
    $display("enter");
    Address = 9'd4;

    opcode = 6'b100001;
    #2 Enable = 1'b0;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd0;
    opcode = 6'b101000;
    DataIn = 32'b10101010;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd2;
    opcode = 6'b101001;
    DataIn = 32'b0010101011111111;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd4;
    opcode = 6'b101001;
    DataIn = 32'b0111111110101010;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd8;
    opcode = 6'b101011;
    DataIn = 32'b10101010111111111010101011111111;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd0;
    opcode = 6'b100000;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd2;
    opcode = 6'b100001;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd4;
    opcode = 6'b100001;
    #3 Enable = 1'b1;
    #2 Enable = 1'b0;

    Address = 9'd8;
    opcode = 6'b100011;
    #3 Enable = 1'b1;

end
endmodule