data/full_repos/permissive/181658840/2_Counter.v
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1: b'%Error: data/full_repos/permissive/181658840/2_Counter.v:5: Cannot find include file: 1_Adders.v\n`include "1_Adders.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181658840,data/full_repos/permissive/181658840/1_Adders.v\n             data/full_repos/permissive/181658840,data/full_repos/permissive/181658840/1_Adders.v.v\n             data/full_repos/permissive/181658840,data/full_repos/permissive/181658840/1_Adders.v.sv\n             1_Adders.v\n             1_Adders.v.v\n             1_Adders.v.sv\n             obj_dir/1_Adders.v\n             obj_dir/1_Adders.v.v\n             obj_dir/1_Adders.v.sv\n%Error: data/full_repos/permissive/181658840/2_Counter.v:18: syntax error, unexpected \',\'\n    adder #(.N(N)) counter_adder(.a(count), .b({31\'b0, 1\'b1}, .c(count_out));\n                                                            ^\n%Error: data/full_repos/permissive/181658840/2_Counter.v:19: syntax error, unexpected \',\'\n    adder #(.N(N)) clock_adder(.a(clock_in), .b({31\'b0, 1\'b1}, .c(clock_out));\n                                                             ^\n%Error: Exiting due to 3 error(s)\n'
module counter(input clk, input reset, input enable, count);
    parameter N_CLK = 100;
    parameter N = 32;

    output[N-1:0] count;
    reg[N-1:0] count;

    wire[N-1:0] count_out, clock_out;
    reg[N-1:0] clock_in;

    adder #(.N(N)) counter_adder(.a(count), .b({31'b0, 1'b1}, .c(count_out));
    adder #(.N(N)) clock_adder(.a(clock_in), .b({31'b0, 1'b1}, .c(clock_out));

    always @(posedge clk) begin
        if(reset) begin
            clock_in <= 0; count <= 0;

        end else if (clock_in == N_CLK) begin
            count <= count_out;
            clock_in <= 0;

        end

        if (enable)
            clock_in <= clock_out;
    end
endmodule
module counter(input clk, input reset, input enable, count);

    parameter N_CLK = 100;
    parameter N = 32;

    output[N-1:0] count;
    reg[N-1:0] count;

    wire[N-1:0] count_out, clock_out;
    reg[N-1:0] clock_in;

    adder #(.N(N)) counter_adder(.a(count), .b({31'b0, 1'b1}, .c(count_out));
    adder #(.N(N)) clock_adder(.a(clock_in), .b({31'b0, 1'b1}, .c(clock_out));

    always @(posedge clk) begin
        if(reset) begin
            clock_in <= 0; count <= 0;

        end else if (clock_in == N_CLK) begin
            count <= count_out;
            clock_in <= 0;

        end

        if (enable)
            clock_in <= clock_out;
    end
endmodule