data/full_repos/permissive/139213403/FPGA/pwm.v
data/verilator_xmls/8be9545a-4af4-4903-b7d1-d977b8c218bb.xml
module pwm

#(
	parameter N = 4,
	          M = 1
)
(
	input wire clk, reset,
	input wire [M-1:0] in,
	input wire [N-1:0] w,
	output wire [M-1:0] out
);

	reg [N-1:0] counter_reg, counter_next;

	always @(posedge clk, posedge reset)
		if (reset)
			counter_reg <= 0;
		else
			counter_reg <= counter_next;
			
	always @*
		counter_next = counter_reg + 1'b1;
		
	assign out = (counter_reg > w || w == 0) ? 0 : in;

endmodule
module pwm

#(
	parameter N = 4,
	          M = 1
)
(
	input wire clk, reset,
	input wire [M-1:0] in,
	input wire [N-1:0] w,
	output wire [M-1:0] out
);


	reg [N-1:0] counter_reg, counter_next;

	always @(posedge clk, posedge reset)
		if (reset)
			counter_reg <= 0;
		else
			counter_reg <= counter_next;
			
	always @*
		counter_next = counter_reg + 1'b1;
		
	assign out = (counter_reg > w || w == 0) ? 0 : in;

endmodule