data/full_repos/permissive/127683055/src/bcd_counter.v
data/verilator_xmls/64d1cf95-1ebc-4244-b300-5e8734cc9e96.xml
module bcd_counter(
  input clk,
  input rst,
  input increment,
  output reg [3:0] digit2,
  output reg [3:0] digit1,
  output reg [3:0] digit0
    );
          
  always @(posedge clk) begin
    if (rst) begin

      digit2 <= 4'b0;
      digit1 <= 4'b0;
      digit0 <= 4'b1;
    end else if (increment) begin

      if (digit0 != 4'd9) begin

        digit0 <= digit0 + 1'b1;
      end else begin

        digit0 <= 4'd0;
        if (digit1 != 4'd9) begin

            digit1 <= digit1 + 1'b1;
        end else begin

          digit1 <= 4'd0;
          digit2 <= digit2 + 1'b1;
        end
      end
    end
  end


endmodule
module bcd_counter(
  input clk,
  input rst,
  input increment,
  output reg [3:0] digit2,
  output reg [3:0] digit1,
  output reg [3:0] digit0
    );

          
  always @(posedge clk) begin
    if (rst) begin

      digit2 <= 4'b0;
      digit1 <= 4'b0;
      digit0 <= 4'b1;
    end else if (increment) begin

      if (digit0 != 4'd9) begin

        digit0 <= digit0 + 1'b1;
      end else begin

        digit0 <= 4'd0;
        if (digit1 != 4'd9) begin

            digit1 <= digit1 + 1'b1;
        end else begin

          digit1 <= 4'd0;
          digit2 <= digit2 + 1'b1;
        end
      end
    end
  end


endmodule