data/full_repos/permissive/133149315/clk_mux/sim/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #100; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #100; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #101;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #121;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #221;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #221;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #221;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #221;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #221;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #221;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #221;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #221;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #221;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:54: Unsupported: Ignoring delay on this delayed statement.\nalways #3.3 clk0 = ~clk0;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:55: Unsupported: Ignoring delay on this delayed statement.\nalways #8.7 clk1 = ~clk1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:56: Unsupported: Ignoring delay on this delayed statement.\nalways #4.7 clk2 = ~clk2;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:57: Unsupported: Ignoring delay on this delayed statement.\nalways #5.7 clk3 = ~clk3;\n       ^\n%Error: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:83: Unsupported or unknown PLI call: $fsdbDumpfile\n     $fsdbDumpfile("tb.fsdb");\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133149315/clk_mux/sim/tb.v:84: Unsupported or unknown PLI call: $fsdbDumpvars\n     $fsdbDumpvars();\n     ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;

reg clk0;
reg clk1;
reg clk2;
reg clk3;
reg rstn;
reg [1:0] sel;


initial begin
  clk0 = 1'b0;
  clk1 = 1'b0;
  clk2 = 1'b0;
  clk3 = 1'b0;
  rstn = 1'b1;

  sel  = 1'b0;
  #100; 
  rstn = 1'b0;
  #100; 
  rstn = 1'b1;

  $display("%t, sel switch start...",$time);

  #101;
  sel  = 2'h2;
  #121;
  sel  = 2'h1;
  #221;
  sel  = 2'h0;
  #221;
  sel  = 2'h3;
  #221;
  sel  = 2'h2;
  #221;
  sel  = 2'h0;
  #221;
  sel  = 2'h3;
  #221;
  sel  = 2'h1;
  #221;
  sel  = 2'h2;
  #221;
  sel  = 2'h3;
  #221;
  sel  = 2'h0;
  #1000;
  $finish;
end

always #3.3 clk0 = ~clk0;
always #8.7 clk1 = ~clk1;
always #4.7 clk2 = ~clk2;
always #5.7 clk3 = ~clk3;

wire clk_out2;

clk_mux i_clk_mux(
.i_clk0 (clk0   ),
.i_clk1 (clk1   ),
.i_sel  (sel[0] ),
.i_rstn (rstn   ),
.o_clk  (clk_out2)
);


wire clk_out4;
clk_mux4  i_clk_mux4(
.i_clk0 (clk0   ),
.i_clk1 (clk1   ),
.i_clk2 (clk2   ),
.i_clk3 (clk3   ),
.i_sel  (sel    ),
.i_rstn (rstn   ),
.o_clk  (clk_out4)
);


initial begin
     $fsdbDumpfile("tb.fsdb");
     $fsdbDumpvars();
end

endmodule
module tb;


reg clk0;
reg clk1;
reg clk2;
reg clk3;
reg rstn;
reg [1:0] sel;


initial begin
  clk0 = 1'b0;
  clk1 = 1'b0;
  clk2 = 1'b0;
  clk3 = 1'b0;
  rstn = 1'b1;

  sel  = 1'b0;
  #100; 
  rstn = 1'b0;
  #100; 
  rstn = 1'b1;

  $display("%t, sel switch start...",$time);

  #101;
  sel  = 2'h2;
  #121;
  sel  = 2'h1;
  #221;
  sel  = 2'h0;
  #221;
  sel  = 2'h3;
  #221;
  sel  = 2'h2;
  #221;
  sel  = 2'h0;
  #221;
  sel  = 2'h3;
  #221;
  sel  = 2'h1;
  #221;
  sel  = 2'h2;
  #221;
  sel  = 2'h3;
  #221;
  sel  = 2'h0;
  #1000;
  $finish;
end

always #3.3 clk0 = ~clk0;
always #8.7 clk1 = ~clk1;
always #4.7 clk2 = ~clk2;
always #5.7 clk3 = ~clk3;

wire clk_out2;

clk_mux i_clk_mux(
.i_clk0 (clk0   ),
.i_clk1 (clk1   ),
.i_sel  (sel[0] ),
.i_rstn (rstn   ),
.o_clk  (clk_out2)
);


wire clk_out4;
clk_mux4  i_clk_mux4(
.i_clk0 (clk0   ),
.i_clk1 (clk1   ),
.i_clk2 (clk2   ),
.i_clk3 (clk3   ),
.i_sel  (sel    ),
.i_rstn (rstn   ),
.o_clk  (clk_out4)
);


initial begin
     $fsdbDumpfile("tb.fsdb");
     $fsdbDumpvars();
end

endmodule