data/full_repos/permissive/143278/contrib/div16.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:176: Unsupported: Ignoring delay on this delayed statement.\n   #200;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/contrib/div16.v:221: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:222: Unsupported: Ignoring delay on this delayed statement.\n      #1 start = 1;\n      ^\n%Error: data/full_repos/permissive/143278/contrib/div16.v:223: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:224: Unsupported: Ignoring delay on this delayed statement.\n      #1 start = 0;\n      ^\n%Error: data/full_repos/permissive/143278/contrib/div16.v:225: syntax error, unexpected \'@\'\n      while (~done) @(posedge clk);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:226: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:245: Unsupported: Ignoring delay on this delayed statement.\n      #10 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:246: Unsupported: Ignoring delay on this delayed statement.\n      #10 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:252: Unsupported: Ignoring delay on this delayed statement.\n   #133 resetb = 1;\n   ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_div16;
reg		clk;
reg		resetb;
reg		start;
reg [15:0]	a;
reg [15:0]	b;
wire [15:0]	q;
wire [15:0]	r;
wire		done;

integer		num_errors;

div16 div16 (
   .clk(clk),
   .resetb(resetb),
   .start(start),
   .a(a),
   .b(b),
   .q(q),
   .r(r),
   .done(done)
);

initial begin
   num_errors = 0;

   start = 0;


   #200;


   $display ("16-bit Dividend, 8-bit divisor");
   repeat (25) begin
      do_divide ($random, $random & 255);
   end


   $display ("\n16-bit Dividend, 12-bit divisor");
   repeat (25) begin
      do_divide ($random, $random & 4095);
   end


   $display ("\n16-bit Dividend, 16-bit divisor");
   repeat (25) begin
      do_divide ($random, $random);
   end


   $display ("\nSpecial Cases:");
   do_divide (16'hFFFF,  16'hFFFF);
   do_divide (312,  1);
   do_divide (  0, 42);
   do_divide (312,  0);


   if (num_errors === 0) begin
      $display ("\n\nPASSED");
   end
   else begin
      $display ("\n\nFAILED - There were %0d Errors.", num_errors);
   end

   $finish;
end

task do_divide;
   input [15:0] arga;
   input [15:0] argb;

   begin
      a = arga;
      b = argb;
      @(posedge clk);
      #1 start = 1;
      @(posedge clk);
      #1 start = 0;
      while (~done) @(posedge clk);
      #1;

      $display ("Circuit: %0d / %0d = %0d, rem = %0d\t\t......... Reality: %0d, rem = %0d", arga, argb, q, r, a/b, a%b);
      if (b !== 0) begin
         if (q !== a/b) begin
            $display ("   Error!  Unexpected Quotient\n\n");
            num_errors = num_errors + 1;
         end
         if (r !== a % b) begin
            $display ("   Error!  Unexpected Remainder\n\n");
            num_errors = num_errors + 1;
         end
      end
   end
endtask

initial begin
   clk = 0;
   forever begin
      #10 clk = 1;
      #10 clk = 0;
   end
end

initial begin
   resetb = 0;
   #133 resetb = 1;
end






endmodule
module test_div16;

reg		clk;
reg		resetb;
reg		start;
reg [15:0]	a;
reg [15:0]	b;
wire [15:0]	q;
wire [15:0]	r;
wire		done;

integer		num_errors;

div16 div16 (
   .clk(clk),
   .resetb(resetb),
   .start(start),
   .a(a),
   .b(b),
   .q(q),
   .r(r),
   .done(done)
);

initial begin
   num_errors = 0;

   start = 0;


   #200;


   $display ("16-bit Dividend, 8-bit divisor");
   repeat (25) begin
      do_divide ($random, $random & 255);
   end


   $display ("\n16-bit Dividend, 12-bit divisor");
   repeat (25) begin
      do_divide ($random, $random & 4095);
   end


   $display ("\n16-bit Dividend, 16-bit divisor");
   repeat (25) begin
      do_divide ($random, $random);
   end


   $display ("\nSpecial Cases:");
   do_divide (16'hFFFF,  16'hFFFF);
   do_divide (312,  1);
   do_divide (  0, 42);
   do_divide (312,  0);


   if (num_errors === 0) begin
      $display ("\n\nPASSED");
   end
   else begin
      $display ("\n\nFAILED - There were %0d Errors.", num_errors);
   end

   $finish;
end

task do_divide;
   input [15:0] arga;
   input [15:0] argb;

   begin
      a = arga;
      b = argb;
      @(posedge clk);
      #1 start = 1;
      @(posedge clk);
      #1 start = 0;
      while (~done) @(posedge clk);
      #1;

      $display ("Circuit: %0d / %0d = %0d, rem = %0d\t\t......... Reality: %0d, rem = %0d", arga, argb, q, r, a/b, a%b);
      if (b !== 0) begin
         if (q !== a/b) begin
            $display ("   Error!  Unexpected Quotient\n\n");
            num_errors = num_errors + 1;
         end
         if (r !== a % b) begin
            $display ("   Error!  Unexpected Remainder\n\n");
            num_errors = num_errors + 1;
         end
      end
   end
endtask

initial begin
   clk = 0;
   forever begin
      #10 clk = 1;
      #10 clk = 0;
   end
end

initial begin
   resetb = 0;
   #133 resetb = 1;
end






endmodule