data/full_repos/permissive/17877624/src/hardware/lab3/synthesis/submodules/lab3_master_0_p2b_adapter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/lab3/synthesis/submodules/lab3_master_0_p2b_adapter.v:41: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'in_channel\' generates 1 bits.\n                                                                                                                         : ... In instance lab3_master_0_p2b_adapter\n      out_channel        = in_channel;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module lab3_master_0_p2b_adapter (
    

      input              clk,

      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [ 7: 0] in_data,
      input              in_startofpacket,
      input              in_endofpacket,

      input              out_ready,
      output reg         out_valid,
      output reg [ 7: 0] out_data,
      output reg         out_startofpacket,
      output reg         out_endofpacket,
      output reg [ 7: 0] out_channel
);


   reg          in_channel = 0;




   always @* begin
      in_ready = out_ready;
      out_valid = in_valid;
      out_data = in_data;
      out_startofpacket = in_startofpacket;
      out_endofpacket = in_endofpacket;

      out_channel = 0;
      out_channel        = in_channel;
   end

endmodule
module lab3_master_0_p2b_adapter (
    

      input              clk,

      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [ 7: 0] in_data,
      input              in_startofpacket,
      input              in_endofpacket,

      input              out_ready,
      output reg         out_valid,
      output reg [ 7: 0] out_data,
      output reg         out_startofpacket,
      output reg         out_endofpacket,
      output reg [ 7: 0] out_channel
);



   reg          in_channel = 0;




   always @* begin
      in_ready = out_ready;
      out_valid = in_valid;
      out_data = in_data;
      out_startofpacket = in_startofpacket;
      out_endofpacket = in_endofpacket;

      out_channel = 0;
      out_channel        = in_channel;
   end

endmodule