data/full_repos/permissive/154553572/Memory.v
 line:4: before: "["
data/verilator_xmls/cb2f2ab1-399b-4ace-b8fc-6d6e22dc0832.xml
module Memory(
		output 
			[9:0] ReadData1,
			[9:0] ReadData2,
		input
			WriteEn,
			Clk,
			[8:0] ReadAdd1,
			[8:0] ReadAdd2,
			[9:0] WriteData,
			[8:0] WriteAdd);

	reg [9:0] Data[511:0];

	always @(posedge Clk)
	begin
		if (WriteEn)
			Data[WriteAdd]<= WriteData;
	end
	

	assign ReadData1= Data[ReadAdd1];
	assign ReadData2= Data[ReadAdd2];
endmodule
module Memory(
		output 
			[9:0] ReadData1,
			[9:0] ReadData2,
		input
			WriteEn,
			Clk,
			[8:0] ReadAdd1,
			[8:0] ReadAdd2,
			[9:0] WriteData,
			[8:0] WriteAdd);


	reg [9:0] Data[511:0];

	always @(posedge Clk)
	begin
		if (WriteEn)
			Data[WriteAdd]<= WriteData;
	end
	

	assign ReadData1= Data[ReadAdd1];
	assign ReadData2= Data[ReadAdd2];
endmodule