data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/counter_6.v
data/verilator_xmls/07774c3c-f1e3-4518-beff-d721d592aebf.xml
module counter_6(count, clk, rst);
parameter n=5;
 
  output reg [n:0] count;
  input clk;
  input rst;
 

  initial
    count = 0;
 

  always @(posedge clk )
   
      count = count + 1;


endmodule
module counter_6(count, clk, rst);

parameter n=5;
 
  output reg [n:0] count;
  input clk;
  input rst;
 

  initial
    count = 0;
 

  always @(posedge clk )
   
      count = count + 1;


endmodule