data/full_repos/permissive/216192770/Rom.v
data/verilator_xmls/10e3c399-1bd7-41c1-b6c9-86d348ba7f0a.xml
module Rom
#(
    parameter Width = 16,
    parameter AddrWidth = 8
)
(
	output reg [Width - 1:0] data,
	input [AddrWidth - 1:0] addr,
    input cs,
    input re
);

    reg[7:0] addrtmp;
    integer i = 0;

	reg [Width - 1:0] rom[(1<<AddrWidth) - 1:0];
    

    initial
        $readmemb("init.mem", rom);












    always@(posedge re)
        if(cs)
            data <= rom[addr];
        else
            data <= data;

endmodule
module Rom
#(
    parameter Width = 16,
    parameter AddrWidth = 8
)
(
	output reg [Width - 1:0] data,
	input [AddrWidth - 1:0] addr,
    input cs,
    input re
);


    reg[7:0] addrtmp;
    integer i = 0;

	reg [Width - 1:0] rom[(1<<AddrWidth) - 1:0];
    

    initial
        $readmemb("init.mem", rom);












    always@(posedge re)
        if(cs)
            data <= rom[addr];
        else
            data <= data;

endmodule