data/full_repos/permissive/154590168/rtl_cpu/DmCont.v
1: b'%Error: data/full_repos/permissive/154590168/rtl_cpu/DmCont.v:77: Cannot find include file: OpNumber.v\n`include "OpNumber.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v.v\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v.sv\n             OpNumber.v\n             OpNumber.v.v\n             OpNumber.v.sv\n             obj_dir/OpNumber.v\n             obj_dir/OpNumber.v.v\n             obj_dir/OpNumber.v.sv\n%Error: Exiting due to 1 error(s)\n'
module  DmCont (
    input               clock,
    input               reset,
    input       [7:0]   dm_rdata,
    input       [7:0]   io_rdata,
    input       [7:0]   rf_rdata,
    input       [7:0]   sreg,
    input       [15:0]  sp,
    input       [15:0]  pc,
    input       [15:0]  ir,
    input       [1:0]   cycle,
    input       [15:0]  ptr_ai,
    input       [15:0]  ptr_ro,
    input       [7:0]   bsc_ro,
    input       [0:82]  op_decode,
    input               tim_dm_re,
    input               tim_dm_we,
    output  reg [15:0]  dm_addr,
    output  reg         dm_re,
    output  reg         dm_we,
    output  reg [7:0]   dm_wdata,
    output  reg [7:0]   io_addr,
    output  reg         io_re,
    output  reg         io_we,
    output  reg [7:0]   io_wdata,
    output              mm_sp_l_we,
    output              mm_sp_h_we,
    output              mm_sreg_we,
    output      [7:0]   mm_io_wdata,
    output      [7:0]   mm_io_rdata,
    output      [7:0]   mm_rdata,
    output  reg         mm_rdata_en
);




wire[15:0]  mm_addr;
wire        mm_pre_op;
wire        mm_post_op;
wire        mm_op;
wire[15:0]  ac_dm_addr;
wire        ac_dm_en;
wire[7:0]   ac_io_addr;
wire        ac_io_en;
wire        io_5bit_op;
wire        io_6bit_op;
wire[7:0]   mx_io_addr;
wire        mx_io_en;
wire        em_io_en;
wire        em_sp_l_en;
wire        em_sp_h_en;
wire        em_sreg_en;
wire        tm_dm_re;
wire        tm_dm_we;
wire        tm_io_re;
wire        tm_io_we;
wire        tm_sp_l_re;
wire        tm_sp_l_we;
wire        tm_sp_h_re;
wire        tm_sp_h_we;
wire        tm_sreg_re;
wire        tm_sreg_we;
wire[7:0]   mm_wdata;
wire        mm_wd_pc_h;
wire        mm_wd_pc_l;
wire        mm_wd_rf;
wire        mm_wd_bsc;
reg         mm_sp_l_re;
reg         mm_sp_h_re;
reg         mm_sreg_re;


`include "OpNumber.v"
wire    op_call   = op_decode[B_CALL  ];
wire    op_rcall  = op_decode[B_RCALL ];
wire    op_icall  = op_decode[B_ICALL ];
wire    op_ret    = op_decode[B_RET   ];
wire    op_reti   = op_decode[B_RETI  ];
wire    op_lds    = op_decode[B_LDS   ];
wire    op_ldx    = op_decode[B_LDX   ];
wire    op_ldxi   = op_decode[B_LDXI  ];
wire    op_ldxd   = op_decode[B_LDXD  ];
wire    op_ldyi   = op_decode[B_LDYI  ];
wire    op_ldyd   = op_decode[B_LDYD  ];
wire    op_lddy   = op_decode[B_LDDY  ];
wire    op_ldzi   = op_decode[B_LDZI  ];
wire    op_ldzd   = op_decode[B_LDZD  ];
wire    op_lddz   = op_decode[B_LDDZ  ];
wire    op_sts    = op_decode[B_STS   ];
wire    op_stx    = op_decode[B_STX   ];
wire    op_stxi   = op_decode[B_STXI  ];
wire    op_stxd   = op_decode[B_STXD  ];
wire    op_styi   = op_decode[B_STYI  ];
wire    op_styd   = op_decode[B_STYD  ];
wire    op_stdy   = op_decode[B_STDY  ];
wire    op_stzi   = op_decode[B_STZI  ];
wire    op_stzd   = op_decode[B_STZD  ];
wire    op_stdz   = op_decode[B_STDZ  ];
wire    op_push   = op_decode[B_PUSH  ];
wire    op_pop    = op_decode[B_POP   ];
wire    op_in     = op_decode[B_IN    ];
wire    op_out    = op_decode[B_OUT   ];
wire    op_sbic   = op_decode[B_SBIC  ];
wire    op_sbis   = op_decode[B_SBIS  ];
wire    op_sbi    = op_decode[B_SBI   ];
wire    op_cbi    = op_decode[B_CBI   ];




DmAdConv AC (
    .mm_addr    (mm_addr    ),
    .mm_en      (mm_op      ),
    .dm_addr    (ac_dm_addr ),
    .dm_en      (ac_dm_en   ),
    .io_addr    (ac_io_addr ),
    .io_en      (ac_io_en   )
);

assign  mm_addr = (mm_pre_op  ? ptr_ro : 16'h0000)
                | (mm_post_op ? ptr_ai : 16'h0000);

assign  mm_pre_op   = op_lds
                    | op_ldx
                    | op_ldxd
                    | op_ldyd
                    | op_ldzd
                    | op_lddy
                    | op_lddz
                    | op_sts
                    | op_stx
                    | op_stxd
                    | op_styd
                    | op_stzd
                    | op_stdy
                    | op_stdz
                    | op_ret
                    | op_reti
                    | op_pop;

assign  mm_post_op  = op_ldxi
                    | op_ldyi
                    | op_ldzi
                    | op_stxi
                    | op_styi
                    | op_stzi
                    | op_call
                    | op_rcall
                    | op_icall
                    | op_push;


assign  mm_op = mm_pre_op | mm_post_op;




assign  io_5bit_op  = op_sbic
                    | op_sbis
                    | op_sbi
                    | op_cbi;

assign  io_6bit_op  = op_in
                    | op_out;

assign  mx_io_addr = (mm_op      ? ac_io_addr                : 8'h00)
                   | (io_5bit_op ? {3'h0, ir[7:3]}           : 8'h00)
                   | (io_6bit_op ? {2'h0, ir[10:9], ir[3:0]} : 8'h00);

assign  mx_io_en = ac_io_en | io_5bit_op | io_6bit_op;


DmEnMask EM (
    .io_addr    (mx_io_addr ),
    .io_en_i    (mx_io_en   ),
    .io_en_o    (em_io_en   ),
    .sp_l_en    (em_sp_l_en ),
    .sp_h_en    (em_sp_h_en ),
    .sreg_en    (em_sreg_en )
);


assign  tm_dm_re = ac_dm_en & tim_dm_re;
assign  tm_dm_we = ac_dm_en & tim_dm_we;
assign  tm_io_re = em_io_en & tim_dm_re;
assign  tm_io_we = em_io_en & tim_dm_we;
assign  tm_sp_l_re = em_sp_l_en & tim_dm_re;
assign  tm_sp_l_we = em_sp_l_en & tim_dm_we;
assign  tm_sp_h_re = em_sp_h_en & tim_dm_re;
assign  tm_sp_h_we = em_sp_h_en & tim_dm_we;
assign  tm_sreg_re = em_sreg_en & tim_dm_re;
assign  tm_sreg_we = em_sreg_en & tim_dm_we;





always @(posedge clock or posedge reset) begin
    if (reset) begin
        dm_addr <= 16'h0000;
        dm_re <= 1'b0;
        dm_we <= 1'b0;
        dm_wdata <= 8'h00;
    end else begin
        dm_addr <= (tm_dm_re | tm_dm_we) ? ac_dm_addr : dm_addr;
        dm_re <= tm_dm_re;
        dm_we <= tm_dm_we;
        dm_wdata <= tm_dm_we ? mm_wdata : dm_wdata;
    end
end


always @(posedge clock or posedge reset) begin
    if (reset) begin
        io_addr <= 8'h00;
        io_re <= 1'b0;
        io_we <= 1'b0;
        io_wdata <= 8'h00;
    end else begin
        io_addr <= (tm_io_re | tm_io_we) ? mx_io_addr : io_addr;
        io_re <= tm_io_re;
        io_we <= tm_io_we;
        io_wdata <= tm_io_we ? mm_wdata : io_wdata;
    end
end

assign  mm_wdata = (mm_wd_pc_h ? pc[15:8] : 8'h00)
                 | (mm_wd_pc_l ? pc[7:0]  : 8'h00)
                 | (mm_wd_rf   ? rf_rdata : 8'h00)
                 | (mm_wd_bsc  ? bsc_ro   : 8'h00);

assign  mm_wd_pc_h  = (op_call & (cycle == 2'd1))
                    | (op_rcall & (cycle == 2'd0))
                    | (op_icall & (cycle == 2'd0));

assign  mm_wd_pc_l  = (op_call & (cycle == 2'd2))
                    | (op_rcall & (cycle == 2'd1))
                    | (op_icall & (cycle == 2'd1));

assign  mm_wd_rf    = op_sts
                    | op_stx
                    | op_stxi
                    | op_stxd
                    | op_styi
                    | op_styd
                    | op_stdy
                    | op_stzi
                    | op_stzd
                    | op_stdz
                    | op_push
                    | op_out;

assign  mm_wd_bsc   = op_sbi
                    | op_cbi;




assign  mm_sp_l_we = tm_sp_l_we;
assign  mm_sp_h_we = tm_sp_h_we;
assign  mm_sreg_we = tm_sreg_we;
assign  mm_io_wdata = mm_wdata;


always @(posedge clock) begin
    mm_sp_l_re <= tm_sp_l_re;
    mm_sp_h_re <= tm_sp_h_re;
    mm_sreg_re <= tm_sreg_re;
end

assign  mm_io_rdata = (io_re      ? io_rdata : 8'h00)
                    | (mm_sp_l_re ? sp[7:0]  : 8'h00)
                    | (mm_sp_h_re ? sp[15:8] : 8'h00)
                    | (mm_sreg_re ? sreg     : 8'h00);

assign  mm_rdata = mm_io_rdata
                 | (dm_re ? dm_rdata : 8'h00);

always @(posedge clock) begin
    mm_rdata_en <= tim_dm_re;
end

endmodule
module  DmCont (
    input               clock,
    input               reset,
    input       [7:0]   dm_rdata,
    input       [7:0]   io_rdata,
    input       [7:0]   rf_rdata,
    input       [7:0]   sreg,
    input       [15:0]  sp,
    input       [15:0]  pc,
    input       [15:0]  ir,
    input       [1:0]   cycle,
    input       [15:0]  ptr_ai,
    input       [15:0]  ptr_ro,
    input       [7:0]   bsc_ro,
    input       [0:82]  op_decode,
    input               tim_dm_re,
    input               tim_dm_we,
    output  reg [15:0]  dm_addr,
    output  reg         dm_re,
    output  reg         dm_we,
    output  reg [7:0]   dm_wdata,
    output  reg [7:0]   io_addr,
    output  reg         io_re,
    output  reg         io_we,
    output  reg [7:0]   io_wdata,
    output              mm_sp_l_we,
    output              mm_sp_h_we,
    output              mm_sreg_we,
    output      [7:0]   mm_io_wdata,
    output      [7:0]   mm_io_rdata,
    output      [7:0]   mm_rdata,
    output  reg         mm_rdata_en
);





wire[15:0]  mm_addr;
wire        mm_pre_op;
wire        mm_post_op;
wire        mm_op;
wire[15:0]  ac_dm_addr;
wire        ac_dm_en;
wire[7:0]   ac_io_addr;
wire        ac_io_en;
wire        io_5bit_op;
wire        io_6bit_op;
wire[7:0]   mx_io_addr;
wire        mx_io_en;
wire        em_io_en;
wire        em_sp_l_en;
wire        em_sp_h_en;
wire        em_sreg_en;
wire        tm_dm_re;
wire        tm_dm_we;
wire        tm_io_re;
wire        tm_io_we;
wire        tm_sp_l_re;
wire        tm_sp_l_we;
wire        tm_sp_h_re;
wire        tm_sp_h_we;
wire        tm_sreg_re;
wire        tm_sreg_we;
wire[7:0]   mm_wdata;
wire        mm_wd_pc_h;
wire        mm_wd_pc_l;
wire        mm_wd_rf;
wire        mm_wd_bsc;
reg         mm_sp_l_re;
reg         mm_sp_h_re;
reg         mm_sreg_re;


`include "OpNumber.v"
wire    op_call   = op_decode[B_CALL  ];
wire    op_rcall  = op_decode[B_RCALL ];
wire    op_icall  = op_decode[B_ICALL ];
wire    op_ret    = op_decode[B_RET   ];
wire    op_reti   = op_decode[B_RETI  ];
wire    op_lds    = op_decode[B_LDS   ];
wire    op_ldx    = op_decode[B_LDX   ];
wire    op_ldxi   = op_decode[B_LDXI  ];
wire    op_ldxd   = op_decode[B_LDXD  ];
wire    op_ldyi   = op_decode[B_LDYI  ];
wire    op_ldyd   = op_decode[B_LDYD  ];
wire    op_lddy   = op_decode[B_LDDY  ];
wire    op_ldzi   = op_decode[B_LDZI  ];
wire    op_ldzd   = op_decode[B_LDZD  ];
wire    op_lddz   = op_decode[B_LDDZ  ];
wire    op_sts    = op_decode[B_STS   ];
wire    op_stx    = op_decode[B_STX   ];
wire    op_stxi   = op_decode[B_STXI  ];
wire    op_stxd   = op_decode[B_STXD  ];
wire    op_styi   = op_decode[B_STYI  ];
wire    op_styd   = op_decode[B_STYD  ];
wire    op_stdy   = op_decode[B_STDY  ];
wire    op_stzi   = op_decode[B_STZI  ];
wire    op_stzd   = op_decode[B_STZD  ];
wire    op_stdz   = op_decode[B_STDZ  ];
wire    op_push   = op_decode[B_PUSH  ];
wire    op_pop    = op_decode[B_POP   ];
wire    op_in     = op_decode[B_IN    ];
wire    op_out    = op_decode[B_OUT   ];
wire    op_sbic   = op_decode[B_SBIC  ];
wire    op_sbis   = op_decode[B_SBIS  ];
wire    op_sbi    = op_decode[B_SBI   ];
wire    op_cbi    = op_decode[B_CBI   ];




DmAdConv AC (
    .mm_addr    (mm_addr    ),
    .mm_en      (mm_op      ),
    .dm_addr    (ac_dm_addr ),
    .dm_en      (ac_dm_en   ),
    .io_addr    (ac_io_addr ),
    .io_en      (ac_io_en   )
);

assign  mm_addr = (mm_pre_op  ? ptr_ro : 16'h0000)
                | (mm_post_op ? ptr_ai : 16'h0000);

assign  mm_pre_op   = op_lds
                    | op_ldx
                    | op_ldxd
                    | op_ldyd
                    | op_ldzd
                    | op_lddy
                    | op_lddz
                    | op_sts
                    | op_stx
                    | op_stxd
                    | op_styd
                    | op_stzd
                    | op_stdy
                    | op_stdz
                    | op_ret
                    | op_reti
                    | op_pop;

assign  mm_post_op  = op_ldxi
                    | op_ldyi
                    | op_ldzi
                    | op_stxi
                    | op_styi
                    | op_stzi
                    | op_call
                    | op_rcall
                    | op_icall
                    | op_push;


assign  mm_op = mm_pre_op | mm_post_op;




assign  io_5bit_op  = op_sbic
                    | op_sbis
                    | op_sbi
                    | op_cbi;

assign  io_6bit_op  = op_in
                    | op_out;

assign  mx_io_addr = (mm_op      ? ac_io_addr                : 8'h00)
                   | (io_5bit_op ? {3'h0, ir[7:3]}           : 8'h00)
                   | (io_6bit_op ? {2'h0, ir[10:9], ir[3:0]} : 8'h00);

assign  mx_io_en = ac_io_en | io_5bit_op | io_6bit_op;


DmEnMask EM (
    .io_addr    (mx_io_addr ),
    .io_en_i    (mx_io_en   ),
    .io_en_o    (em_io_en   ),
    .sp_l_en    (em_sp_l_en ),
    .sp_h_en    (em_sp_h_en ),
    .sreg_en    (em_sreg_en )
);


assign  tm_dm_re = ac_dm_en & tim_dm_re;
assign  tm_dm_we = ac_dm_en & tim_dm_we;
assign  tm_io_re = em_io_en & tim_dm_re;
assign  tm_io_we = em_io_en & tim_dm_we;
assign  tm_sp_l_re = em_sp_l_en & tim_dm_re;
assign  tm_sp_l_we = em_sp_l_en & tim_dm_we;
assign  tm_sp_h_re = em_sp_h_en & tim_dm_re;
assign  tm_sp_h_we = em_sp_h_en & tim_dm_we;
assign  tm_sreg_re = em_sreg_en & tim_dm_re;
assign  tm_sreg_we = em_sreg_en & tim_dm_we;





always @(posedge clock or posedge reset) begin
    if (reset) begin
        dm_addr <= 16'h0000;
        dm_re <= 1'b0;
        dm_we <= 1'b0;
        dm_wdata <= 8'h00;
    end else begin
        dm_addr <= (tm_dm_re | tm_dm_we) ? ac_dm_addr : dm_addr;
        dm_re <= tm_dm_re;
        dm_we <= tm_dm_we;
        dm_wdata <= tm_dm_we ? mm_wdata : dm_wdata;
    end
end


always @(posedge clock or posedge reset) begin
    if (reset) begin
        io_addr <= 8'h00;
        io_re <= 1'b0;
        io_we <= 1'b0;
        io_wdata <= 8'h00;
    end else begin
        io_addr <= (tm_io_re | tm_io_we) ? mx_io_addr : io_addr;
        io_re <= tm_io_re;
        io_we <= tm_io_we;
        io_wdata <= tm_io_we ? mm_wdata : io_wdata;
    end
end

assign  mm_wdata = (mm_wd_pc_h ? pc[15:8] : 8'h00)
                 | (mm_wd_pc_l ? pc[7:0]  : 8'h00)
                 | (mm_wd_rf   ? rf_rdata : 8'h00)
                 | (mm_wd_bsc  ? bsc_ro   : 8'h00);

assign  mm_wd_pc_h  = (op_call & (cycle == 2'd1))
                    | (op_rcall & (cycle == 2'd0))
                    | (op_icall & (cycle == 2'd0));

assign  mm_wd_pc_l  = (op_call & (cycle == 2'd2))
                    | (op_rcall & (cycle == 2'd1))
                    | (op_icall & (cycle == 2'd1));

assign  mm_wd_rf    = op_sts
                    | op_stx
                    | op_stxi
                    | op_stxd
                    | op_styi
                    | op_styd
                    | op_stdy
                    | op_stzi
                    | op_stzd
                    | op_stdz
                    | op_push
                    | op_out;

assign  mm_wd_bsc   = op_sbi
                    | op_cbi;




assign  mm_sp_l_we = tm_sp_l_we;
assign  mm_sp_h_we = tm_sp_h_we;
assign  mm_sreg_we = tm_sreg_we;
assign  mm_io_wdata = mm_wdata;


always @(posedge clock) begin
    mm_sp_l_re <= tm_sp_l_re;
    mm_sp_h_re <= tm_sp_h_re;
    mm_sreg_re <= tm_sreg_re;
end

assign  mm_io_rdata = (io_re      ? io_rdata : 8'h00)
                    | (mm_sp_l_re ? sp[7:0]  : 8'h00)
                    | (mm_sp_h_re ? sp[15:8] : 8'h00)
                    | (mm_sreg_re ? sreg     : 8'h00);

assign  mm_rdata = mm_io_rdata
                 | (dm_re ? dm_rdata : 8'h00);

always @(posedge clock) begin
    mm_rdata_en <= tim_dm_re;
end

endmodule