data/full_repos/permissive/160073872/fpga/sw/tb/clk_mock.v
data/verilator_xmls/60a22321-3cbe-45e8-a52d-1cc4cf49a321.xml
module clk_wiz_0(
	input wire clk_in_200,
	output wire clk_out_10,
	input wire reset
);

assign clk_out_10 = clk_in_200;

endmodule
module clk_wiz_0(
	input wire clk_in_200,
	output wire clk_out_10,
	input wire reset
);


assign clk_out_10 = clk_in_200;

endmodule