data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/and4/and4.v
data/verilator_xmls/8a05c309-01bf-4948-87ad-96d140b97cf2.xml
module and4(
  a,
  b,
  c,
  d,
  e);

input wire a;
input wire b;
input wire c;
input wire d;
output wire e;

assign e = a & b & c & d;

endmodule
module and4(
  a,
  b,
  c,
  d,
  e);


input wire a;
input wire b;
input wire c;
input wire d;
output wire e;

assign e = a & b & c & d;

endmodule