data/full_repos/permissive/147790758/tb2f_sum.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2f_sum.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147790758/tb2f_sum.v:11: Cannot find file containing module: \'sum\'\nsum #(.WIDTH(4)) DUT (.data_a(term1), .data_b(term2), .c_out(actual[4]), .sum(actual[3:0]));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/sum\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/sum.v\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/sum.sv\n             sum\n             sum.v\n             sum.sv\n             obj_dir/sum\n             obj_dir/sum.v\n             obj_dir/sum.sv\n%Warning-WIDTH: data/full_repos/permissive/147790758/tb2f_sum.v:21: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 5 bits.\n                                                                  : ... In instance tb2f_sum\n  term1 = input_mem[2*i];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/147790758/tb2f_sum.v:22: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 5 bits.\n                                                                  : ... In instance tb2f_sum\n  term2 = input_mem[2*i+1];\n        ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb2f_sum();
	reg [3:0]term1;
	reg [3:0]term2;
	wire [4:0]actual;
	integer i;
	reg [4:0] input_mem [0:9];
	reg [4:0] expected_mem [0:4];
	
sum #(.WIDTH(4)) DUT	(.data_a(term1), .data_b(term2), .c_out(actual[4]), .sum(actual[3:0]));

initial begin: read_dataFile
	$display("**UNIT TEST STARTED**");
	$readmemb("input_sum.dat", input_mem);
	$readmemb("exp_sum.dat", expected_mem);
end

initial begin: test_work
	for (i=0; i<=4; i=i+1) begin
		term1 = input_mem[2*i];
		term2 = input_mem[2*i+1];
		#10;
		$display("Now testing with inputs: %b %b, Expected result: %b Actual result: %b",term1,term2,expected_mem[i],actual);
		if (actual != expected_mem[i]) begin
			$display("ERROR: Expected %b, but got %b. Inputs were: %b and %b", expected_mem[i], actual, term1, term2);
			$display("**ERROR: UNIT DOES NOT WORK PROPERLY**");
			$stop;
		end 
	end
	$display("**ALL TESTS PASSED**");
	$stop;
end

endmodule
module tb2f_sum();

	reg [3:0]term1;
	reg [3:0]term2;
	wire [4:0]actual;
	integer i;
	reg [4:0] input_mem [0:9];
	reg [4:0] expected_mem [0:4];
	
sum #(.WIDTH(4)) DUT	(.data_a(term1), .data_b(term2), .c_out(actual[4]), .sum(actual[3:0]));

initial begin: read_dataFile
	$display("**UNIT TEST STARTED**");
	$readmemb("input_sum.dat", input_mem);
	$readmemb("exp_sum.dat", expected_mem);
end

initial begin: test_work
	for (i=0; i<=4; i=i+1) begin
		term1 = input_mem[2*i];
		term2 = input_mem[2*i+1];
		#10;
		$display("Now testing with inputs: %b %b, Expected result: %b Actual result: %b",term1,term2,expected_mem[i],actual);
		if (actual != expected_mem[i]) begin
			$display("ERROR: Expected %b, but got %b. Inputs were: %b and %b", expected_mem[i], actual, term1, term2);
			$display("**ERROR: UNIT DOES NOT WORK PROPERLY**");
			$stop;
		end 
	end
	$display("**ALL TESTS PASSED**");
	$stop;
end

endmodule