data/full_repos/permissive/177715876/verilog/source/binaryStreamer.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/177715876/verilog/source/binaryStreamer.v:47: Cannot find file containing module: \'c_accum_0\'\n    c_accum_0 myAccumulator(adcInput, clk, accumRst, byteStream);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/177715876/verilog/source,data/full_repos/permissive/177715876/c_accum_0\n             data/full_repos/permissive/177715876/verilog/source,data/full_repos/permissive/177715876/c_accum_0.v\n             data/full_repos/permissive/177715876/verilog/source,data/full_repos/permissive/177715876/c_accum_0.sv\n             c_accum_0\n             c_accum_0.v\n             c_accum_0.sv\n             obj_dir/c_accum_0\n             obj_dir/c_accum_0.v\n             obj_dir/c_accum_0.sv\n%Error: data/full_repos/permissive/177715876/verilog/source/binaryStreamer.v:48: Cannot find file containing module: \'fifo_generator_0\'\n    fifo_generator_0 myFifo(clk, rst, byteStream, fifoWriteEnable, fifoReadEnable, streamerData, fifoFull, fifoEmpty);\n    ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/177715876/verilog/source/binaryStreamer.v:73: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance binaryStreamer\n                counter <= 1\'b0;\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module binaryStreamer
(
    input clk,
    input rst,
    input adcInput,
    input fifoReadEnable,

    output[7:0] streamerData,
    output fifoEmpty,
    output fifoFull
);

    wire[7:0] byteStream;

    reg[31:0] counter;
    reg fifoWriteEnable;
    reg accumRst;


    c_accum_0 myAccumulator(adcInput, clk, accumRst, byteStream);
    fifo_generator_0 myFifo(clk, rst, byteStream, fifoWriteEnable, fifoReadEnable, streamerData, fifoFull, fifoEmpty);


    always@(posedge clk, posedge rst)
    begin
        if(rst == 1'b1)
        begin
            counter <= 32'b0;
            fifoWriteEnable <= 1'b0;
            accumRst <= 1'b1;
        end

        else
        begin
            if(counter < 32'd256)
            begin
                counter <= counter + 1'b1;
                fifoWriteEnable <= 1'b0;
                accumRst <= 1'b0;
            end

            else
            begin
                fifoWriteEnable <= 1'b1;
                accumRst <= 1'b1;
                counter <= 1'b0;
            end
        end
    end
endmodule
module binaryStreamer
(
    input clk,
    input rst,
    input adcInput,
    input fifoReadEnable,

    output[7:0] streamerData,
    output fifoEmpty,
    output fifoFull
);


    wire[7:0] byteStream;

    reg[31:0] counter;
    reg fifoWriteEnable;
    reg accumRst;


    c_accum_0 myAccumulator(adcInput, clk, accumRst, byteStream);
    fifo_generator_0 myFifo(clk, rst, byteStream, fifoWriteEnable, fifoReadEnable, streamerData, fifoFull, fifoEmpty);


    always@(posedge clk, posedge rst)
    begin
        if(rst == 1'b1)
        begin
            counter <= 32'b0;
            fifoWriteEnable <= 1'b0;
            accumRst <= 1'b1;
        end

        else
        begin
            if(counter < 32'd256)
            begin
                counter <= counter + 1'b1;
                fifoWriteEnable <= 1'b0;
                accumRst <= 1'b0;
            end

            else
            begin
                fifoWriteEnable <= 1'b1;
                accumRst <= 1'b1;
                counter <= 1'b0;
            end
        end
    end
endmodule