data/full_repos/permissive/211316121/lab6_1/sources_1/new/Sim_74LS163.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_1/sources_1/new/Sim_74LS163.v:9: Unsupported: Ignoring delay on this delayed statement.\nCP=1;#20;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_1/sources_1/new/Sim_74LS163.v:10: Unsupported: Ignoring delay on this delayed statement.\nCP=0;#20;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_1/sources_1/new/Sim_74LS163.v:20: Unsupported: Ignoring delay on this delayed statement.\n#30;\n^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_1/sources_1/new/Sim_74LS163.v:22: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_1/sources_1/new/Sim_74LS163.v:24: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_1/sources_1/new/Sim_74LS163.v:26: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_1/sources_1/new/Sim_74LS163.v:28: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_1/sources_1/new/Sim_74LS163.v:30: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab6_1/sources_1/new/Sim_74LS163.v:33: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Error: data/full_repos/permissive/211316121/lab6_1/sources_1/new/Sim_74LS163.v:37: Cannot find file containing module: \'_74LS163\'\n_74LS163 sim(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab6_1/sources_1/new,data/full_repos/permissive/211316121/_74LS163\n             data/full_repos/permissive/211316121/lab6_1/sources_1/new,data/full_repos/permissive/211316121/_74LS163.v\n             data/full_repos/permissive/211316121/lab6_1/sources_1/new,data/full_repos/permissive/211316121/_74LS163.sv\n             _74LS163\n             _74LS163.v\n             _74LS163.sv\n             obj_dir/_74LS163\n             obj_dir/_74LS163.v\n             obj_dir/_74LS163.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Sim_74LS163();
reg CP,CR_n,LD_n,EP,ET;
reg [3:0] D;
wire [3:0] Q;
always
begin
CP=1;#20;
CP=0;#20;
end

initial
begin
CR_n=1;
LD_n=0;
EP=1;
ET=1;
D='b0000;
#30;
LD_n=1;
#50;
EP=0;
#50;
EP=1;
#50;
CR_n=0;
#50;
CR_n=1;
#50;
D='b1101;
LD_n=0;
#50;
LD_n=1;
end

_74LS163 sim(
CP,
CR_n,
LD_n,
EP,
ET,
D,
Q);

endmodule
module Sim_74LS163();

reg CP,CR_n,LD_n,EP,ET;
reg [3:0] D;
wire [3:0] Q;
always
begin
CP=1;#20;
CP=0;#20;
end

initial
begin
CR_n=1;
LD_n=0;
EP=1;
ET=1;
D='b0000;
#30;
LD_n=1;
#50;
EP=0;
#50;
EP=1;
#50;
CR_n=0;
#50;
CR_n=1;
#50;
D='b1101;
LD_n=0;
#50;
LD_n=1;
end

_74LS163 sim(
CP,
CR_n,
LD_n,
EP,
ET,
D,
Q);

endmodule