data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v
 line:100: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n             ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n            ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n                ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n                                                                                              : ... In instance multicpu.alu\n   zero = ALUResult ? 0 : 1;\n                    ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegisterFile(
    input [4:0] rs,rt,rd,
	input [31:0] WriteData,
	input [1:0] RegDst,
	input clk,RegWre,
	output reg [31:0] ReadData1,ReadData2
    );
	reg [31:0] register[0:31];
	reg [4:0] WriteReg;
	integer i;
	
	initial
		begin
			for(i=0;i<32;i=i+1) register[i]=0;
		end
		
	always@(negedge clk)
		begin
			case(RegDst)
				2'b00:WriteReg = 5'b11111;
				2'b01:WriteReg = rt;
				2'b10:WriteReg = rd;
			endcase
			assign ReadData1=register[rs];
			assign ReadData2=register[rt];
		end
	always@(posedge clk)
		begin
			if(WriteReg != 0 && RegWre) register[WriteReg] = WriteData;
		end
endmodule
module RegisterFile(
    input [4:0] rs,rt,rd,
	input [31:0] WriteData,
	input [1:0] RegDst,
	input clk,RegWre,
	output reg [31:0] ReadData1,ReadData2
    );

	reg [31:0] register[0:31];
	reg [4:0] WriteReg;
	integer i;
	
	initial
		begin
			for(i=0;i<32;i=i+1) register[i]=0;
		end
		
	always@(negedge clk)
		begin
			case(RegDst)
				2'b00:WriteReg = 5'b11111;
				2'b01:WriteReg = rt;
				2'b10:WriteReg = rd;
			endcase
			assign ReadData1=register[rs];
			assign ReadData2=register[rt];
		end
	always@(posedge clk)
		begin
			if(WriteReg != 0 && RegWre) register[WriteReg] = WriteData;
		end
endmodule