data/full_repos/permissive/113654920/hdl/chip.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/113654920/hdl/chip.v:661: Signal definition not found, creating implicitly: \'IDE_DSTB\'\n                                                                      : ... Suggested alternative: \'IDE_CS\'\n  if (IDE_DSTB == 1\'b1) DIn2  <= DIn1;\n      ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:206: Cannot find file containing module: \'dcm3\'\ndcm3 Inst_DCM(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/dcm3\n             data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/dcm3.v\n             data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/dcm3.sv\n             dcm3\n             dcm3.v\n             dcm3.sv\n             obj_dir/dcm3\n             obj_dir/dcm3.v\n             obj_dir/dcm3.sv\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:216: Cannot find file containing module: \'TF_Stub\'\nTF_Stub Inst_TF_Stub(\n^~~~~~~\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:230: Cannot find file containing module: \'Top\'\nTop dna1 (\n^~~\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:239: Cannot find file containing module: \'Reg38\'\nReg38 R_38(\n^~~~~\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:252: Cannot find file containing module: \'PS2_DMA\'\nPS2_DMA PS2DMA(\n^~~~~~~\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:276: Cannot find file containing module: \'D_RAM\'\nD_RAM  DMARAM(\n^~~~~\n%Error: data/full_repos/permissive/113654920/hdl/chip.v:318: Cannot find file containing module: \'IDE_DMA\'\nIDE_DMA IDEDMA (\n^~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n'
module chip(
	inout [15:0] iD	,


	output [2:0] iA,

	output ibCS0		,
	output ibCS1		,
	output ibRST		,
	input	iIRQ		,
	output ibWr		,
	output ibRd		,
	input iDQ 		,
	output ibDK		,
	input iRdy		,
	input ibDASP	,

	input CLKin		,
	input bCSRST	,
	input bCRST		,
	inout [15:0] cDP		,


	inout [15:0] cAP		,



	input bcCS		,
	input bcWr		,
	input bcRd		,
	input bCRT		,

	output	bcWait 	,
	output	bcIRQ		,
	output	cDQ		,
	input		cDK		,

	output	DR245		,
	output	OE245		,



	input ACS_LED  ,
	input HDD_ACK  ,








	inout		TFD0	,
	inout		TFD1	,
	inout 	TFD2	,
	inout		TFD3	,
	output	TFCLK	,
	input		TFSENSE	,
	output	TFCMD		,






	output	JT_Result		,
	output	JT_Pin1		,
	input		JT_bTest
);

wire DCM_RST,CLK1,CLK4,DCM_LOCKED ;

reg DWrite;
wire IDERd,IDEWr;
reg iIRQ1;
reg iDQ1,SiIRQ,SiDQ;
wire iDMARd,iDMAWr ;
wire BufEmpty ;
wire PA_HvSpace,PA_OD_Rdy ;
wire PB_HvSpace,PB_OD_Rdy ;
wire WithinBBlock,BBurstEnd;
wire WithinABlock;

wire iCS0,iCS1,cWr,cRd,iWr,iRd,iDK ;
wire [15:0] RegData;
wire [31:0] DMARAMQ;
reg  [31:0] DMARAMD;
reg  [15:0] DIn1,DIn2;
wire cDMA_OE ;
wire cRdt;
wire RegEB;






wire	[7:0] Reg0038 ;

wire	[15:0] Reg0028 ;



reg	[7:0] Reg002A;
wire [7:0] Reg002E;
reg [7:0] Reg0064;


wire cDOE,cAOE ;
wire IDE_CS;
reg DMA_ARM,DMARMC,PS2WrIDE ;
wire PA_AlmostFull ;
wire [3:0] BufSize;
reg [2:0] R44;
wire INT9,INT9OE,DMA_IrqCond;
reg DMA_IrqMask, DMA_IrqFF;
wire DMA_IrqCTRL ;
wire bHardReset;
reg ATV1,ATV2,ATV;
wire UDMAC,CmdIsEF,UDMA_SEL,MDMA_SEL,D_UnChg ;
reg R42Is03,R44Is2X,R44Is4X;
wire [2:0] UDMA,MDMA;
reg  [2:0] UDO;
reg [2:1] MDO;

wire Combo_CS,Combo_OE ;
reg cWr1,cRd1,ScWr,ScRd,ScWr1,ScRd1 ;
wire [15:0] cAi,cDi,CRC_Q,iDi,iDO,DOutA;
wire iDOEnb,CRC_MUX ;
wire IDEiOE,iDMA_OE ;
reg [6:0] cRgA;
reg [7:0] cRgD;
wire cRgRd2E,cRgWr;
reg bcRd2E;
reg cRgWrEnb ;
reg [5:0] Rd2ECnt;
reg [3:0] cWaitCnt;
reg cWait;

wire iD_245_In,IDE_Rd_Env ;
reg SiRdy2,SiRdy1;
reg IgnoreIRdyPin;
reg Ph0,Ph1,Ph2,Phase3;

wire Reg002E_0, Reg002E_1, Reg002E_2, Reg002E_3, Reg002E_5, Reg002E_6, Reg002E_7;
reg Reg002E_4;
assign Reg002E = {Reg002E_7, Reg002E_6, Reg002E_5, Reg002E_4, Reg002E_3, Reg002E_2, Reg002E_1, Reg002E_0};














wire	DNA_Pass,DNA_RST;
wire [3:0] KILL;




















dcm3	Inst_DCM(
	.CLKIN_IN		(CLKin),
	.RST_IN			(DCM_RST),
	.CLKFX_OUT		(CLK4),
	.CLKIN_IBUFG_OUT(),
	.CLK0_OUT		(CLK1),
	.LOCKED_OUT		(DCM_LOCKED)
);


TF_Stub	Inst_TF_Stub(
	.RESET (DNA_RST),
	.CLK4	(CLK4),
	.TFD0	(TFD0),
	.TFD1	(TFD1),
	.TFD2	(TFD2),
	.TFD3	(TFD3),
	.TF_CLK		(TFCLK),
   .TF_CMD		(TFCMD), 
	.TF_SENSE	(TFSENSE)
);



Top dna1 (
    .reset(DNA_RST), 
    .clk4(CLK4),
	 .IDE_CS(IDE_CS),
    .dna_pass(DNA_Pass),
	 .KILL(KILL)
    );


Reg38	R_38(
	.UDMAC		(UDMAC),
	.PS2WrIDE	(PS2WrIDE),
	.iIRQ			(SiIRQ),
	.cDQ			(cDQ),
	.iDQ			(SiDQ),
	.iDK			(iDK),
	.BufEmpty	(BufEmpty),
	.PB_HvSpace	(PB_HvSpace),
	.BufSize		(BufSize),
	.DOut			(Reg0038)
);

PS2_DMA	PS2DMA(

	.CLK4			(CLK4),
	.Phase3		(Phase3),

	.cDQ			(cDQ),
	.cDK			(cDK),
	.cRd			(cRd),
	.DWrite		(DWrite),

	.DMA_ARM		(DMA_ARM),
	.PS2WrIDE	(PS2WrIDE),

	.PB_HvSpace	(PB_HvSpace),
	.PB_OD_Rdy	(PB_OD_Rdy),

	.WithinBBlock	(WithinBBlock),
	.BBurstEnd	(BBurstEnd),
	.IncAddrB	(IncAddrB),
	.RegEB		(RegEB),
	.EnbB			(EnbB),
	.WrB			(WrB )
);

D_RAM		DMARAM(
	.CLK4			(CLK4),
	.DMA_ARM		(DMA_ARM),
	.PS2WrIDE	(PS2WrIDE),

	.CRC_ARM		(CRC_ARM),
	.CRC_ENB		(CRC_ENB),
	.CRC_Q		(CRC_Q),

	.PA_HvSpace	(PA_HvSpace),
	.PA_OD_Rdy	(PA_OD_Rdy),
	.PA_AlmostFull	(PA_AlmostFull),
	.PA_Full		(PA_Full),
	.PA_Empty	(PA_Empty),
	.WithinABlock	(WithinABlock),

	.PB_HvSpace	(PB_HvSpace),
	.PB_OD_Rdy	(PB_OD_Rdy),

	.BufSize		(BufSize),
	.BufEmpty	(BufEmpty),

	.DInA			(DIn2),
	.DOutA		(DOutA),
	.DInB 		(DMARAMD), 

	.A0			(A0),
	.HWOE			(HWOE),
	.IncAddrA	(IncAddrA),
	.EnbA		(EnbA),
	.WrA			(WrA),
	.RegEA	(RegEA),

	.WithinBBlock	(WithinBBlock),
	.BBurstEnd	(BBurstEnd),
	.IncAddrB		(IncAddrB),
	.EnbB			(EnbB),
	.RegEB			(RegEB),
	.WrB 			(WrB),  
	.DOutB 		(DMARAMQ)
);

IDE_DMA	IDEDMA (

	.CLK4		(CLK4),
	.Phase3	(Phase3),

	.iDK		(iDK),
	.iDQ		(SiDQ),
	.SiRdy1	(SiRdy1),
	.SiRdy2	(SiRdy2),

	.DMA_ARM(DMA_ARM),
	.PS2WrIDE	(PS2WrIDE),
	.UDMA 		(UDMA),
	.MDMA		(MDMA),
	.iDMARd	(iDMARd),
	.iDMAWr	(iDMAWr),
	.iDMA_OE	(iDMA_OE),
	.iD_245_In	(iD_245_In),
	.CRC_MUX	(CRC_MUX),
	.CRC_ARM	(CRC_ARM),
	.CRC_ENB	(CRC_ENB),

	.PA_HvSpace	(PA_HvSpace),
	.PA_OD_Rdy	(PA_OD_Rdy),
	.WithinABlock	(WithinABlock),
	.PA_AlmostFull(PA_AlmostFull),
	.PA_Full		(PA_Full),
	.PA_Empty	(PA_Empty),
	.IDE_DSTB	(IDE_DSTB),
	.IncAddrA	(IncAddrA),
	.A0		(A0),
	.HWOE		(HWOE),
	.EnbA		(EnbA),
	.WrA			(WrA),
	.RegEA	(RegEA)
);






assign JT_Result	= (JT_bTest == 1'b0) ? ( ~DNA_Pass ) : ( HDD_ACK | ACS_LED | ibDASP | bCRT );
assign JT_Pin1		=  TFCLK;








assign DCM_RST		= ~bCRST | ~bCSRST;
assign bHardReset	=  bCRST & DCM_LOCKED;
assign DNA_RST		= ~DCM_LOCKED;

always @(negedge CLK1) begin
	if (DCM_LOCKED == 1'b0) begin
		Ph0 <= 1'b0;
	end else begin
		Ph0 <= ~Ph0;
	end
end

always @(negedge CLK4) begin
	Ph1	<=	Ph0;
	Ph2	<= Ph1;
end

always @(posedge CLK4) begin
	Phase3	<= Ph1 ^ Ph2;
end


	



	assign ibRST	= ~(Reg0064[7]);
	assign ibCS0	= ~(iCS0);
	assign ibCS1	= ~(iCS1);
	assign ibRd		= ~(iRd);
	assign ibWr		= ~(iWr);
	assign ibDK		= ~(iDK);

	assign iRd	= ( IDERd & ~iDK ) | (iDMARd & iDK);
	assign iWr	= ( IDEWr & ~iDK ) | (iDMAWr & iDK);


	assign cRd	= ~bcRd & ~KILL[0];
	assign cRdt	= ~bCRT & ~KILL[0];
	assign cWr	= ~bcWr & ~KILL[0];



	assign INT9OE	= Reg002A[1] | Reg002A[0];
	assign bcIRQ	= (INT9OE == 1'b1) ? ~(INT9) : 1'bZ;
	assign INT9		= (SiIRQ & Reg002A[0]) | (DMA_IrqFF & DMA_IrqCTRL);

	assign cDMA_OE	=	cRdt & cDK;
	assign cDOE	= ATV & (cDMA_OE | Combo_OE);
	assign cDP 	=	(cDOE		== 1'b0) ?	{16{1'bZ}}		:
						(cDK 		== 1'b1) ?	DMARAMQ[15:0]	:
						(IDE_CS	== 1'b1)	?	iDi[15:0]		:	RegData[15:0];
	assign cDi	= cDP;

	assign cAOE	= ATV &  cDMA_OE;
	assign cAP 	=	(cAOE == 1'b0) ? {16{1'bZ}}		: DMARAMQ[31:16];
	assign cAi	= cAP;










	assign Combo_CS = ATV & ~cDK & ~(bcCS | cAi[15] | cAi[14] | cAi[13] | cAi[12] |
												cAi[11] |	cAi[10] | cAi[9] | cAi[8] | cAi[7]);
	assign Combo_OE = cRd & Combo_CS;
	









	assign iD[15:0]	= (iDOEnb == 1'b1) ? iDO[15:0] : {16{1'bZ}};
	assign iDOEnb		= IDEiOE | iDMA_OE;
	assign iDi[15:0]	= iD[15:0];
	assign iDO[15:0]	=	(IDE_CS  == 1'b1) ?	 cDi[15:0] : 
								(CRC_MUX == 1'b1) ? CRC_Q[15:0] : DOutA[15:0];















assign IDE_CS	= Combo_CS & ~iDK & cAi[6] & ~cAi[5];
assign iCS1		= IDE_CS &  cAi[4] & ~KILL[2];
assign iCS0		= IDE_CS & ~cAi[4] & ~KILL[2];
assign iA[2]	= IDE_CS & cAi[3] & ~KILL[1];
assign iA[1]	= IDE_CS & cAi[2] & ~KILL[2];
assign iA[0]	= IDE_CS & cAi[1] & ~KILL[3];
assign IDERd	= IDE_CS & cRd & ~KILL[1];
assign IDEWr	= IDE_CS & cWr & ~KILL[2];
assign IDEiOE	= IDE_CS & cWr;

assign IDE_Rd_Env	= IDE_CS & cRd;












	assign Reg0028[15]	= BufSize[3];
	assign Reg0028[14]	= BufEmpty;



	assign Reg0028[13:2] = 12'b0000_0000_0000;
	assign Reg0028[1]	= cDQ;
	assign Reg0028[0]	= SiIRQ;


	assign RegData[15:8] =	(cAi[6:0] == 7'h28)	?	Reg0028[15:8]	: 8'h00;

	assign RegData[7:0]	=	(cAi[6:0] == 7'h02)	?	8'h13 			:
									(cAi[6:0] == 7'h04)	?	8'h0B 			:
									(cAi[6:0] == 7'h0E)	?	8'h02				:
									(cAi[6:0] == 7'h28)	?	Reg0028[7:0]	:
									(cAi[6:0] == 7'h2A)	?	Reg002A[7:0]	:

									(cAi[6:0] == 7'h2E)	?	Reg002E[7:0]	:
									(cAi[6:0] == 7'h38)	?	Reg0038[7:0]	:
									(cAi[6:0] == 7'h64)	?	Reg0064[7:0]	: 8'h00;




	assign DMA_IrqCond	=	(~(PS2WrIDE) & PB_OD_Rdy) | (PS2WrIDE & PB_HvSpace);
	assign DMA_IrqCTRL	= Reg002A[1];
	

	assign UDMAC	= UDO[2] | UDO[1] | UDO[0];





assign CmdIsEF		= cRgD[7] & cRgD[6] & cRgD[5] & ~(cRgD[4]) &	cRgD[3] & cRgD[2] & cRgD[1] & cRgD[0];
assign UDMA_SEL	= CmdIsEF & R44Is4X & R42Is03;
assign MDMA_SEL 	= CmdIsEF & R44Is2X & R42Is03;
assign D_UnChg		= ~(UDMA_SEL | MDMA_SEL);
assign UDMA[2:0]	= UDO[2:0];
assign MDMA[2] 	= MDO[2];
assign MDMA[1]		= MDO[1];
assign MDMA[0]		= ~(UDO[2] | UDO[1] | UDO[0] | MDO[2] | MDO[1]);

assign Reg002E_7 = 1'b1;
assign Reg002E_6 = 1'b1;
assign Reg002E_5 = 1'b0;

assign Reg002E_3 = 1'b1;
assign Reg002E_2 = 1'b1;
assign Reg002E_1 = 1'b1;
assign Reg002E_0 = 1'b0;



assign cRgWr	= ATV & ScWr1 & ~(ScWr) & cRgWrEnb;
assign cRgRd2E	= ATV & ScRd1 & ~(ScRd) & bcRd2E;

assign OE245	= ~(ATV);
assign DR245	= ~(IDE_Rd_Env | iD_245_In);


always @(posedge bcWr) begin
	cRgWrEnb		<=	Combo_CS & ScWr & ScWr1;
	cRgA[6:0]	<= cAi[6:0];
	cRgD[7:0]	<= cDi[7:0];
end

always @(posedge bcRd) begin
	bcRd2E	<= Combo_CS & ScRd & ScRd1 & ~(cAi[6]) & cAi[5] & ~(cAi[4]) & cAi[3] & cAi[2] & cAi[1] & ~(cAi[0]);
end






always @(posedge CLK4) begin
	if ((Ph1 ^ Ph2) == 1'b1) begin
		DMARAMD[15:0] 	<= cDi[15:0];
		DMARAMD[31:16]	<= cAi[15:0];
	end
end

always @(posedge CLK1) begin
	DWrite	<= cWr & cDK;
end




assign bcWait	= (IDE_CS == 1'b1) ? ~cWait : 1'bZ;

always @(posedge CLK4) begin
	if (IDE_CS == 1'b0) begin
		cWaitCnt	<= 4'b0000;
		cWait		<= 1'b1;
		IgnoreIRdyPin	<= ~SiRdy2;
	end else begin
		if (cWaitCnt == 4'b1010) begin 

			if ((IgnoreIRdyPin == 1'b1) || (SiRdy2 == 1'b1)) begin
				cWait	<= 1'b0;
			end
		end else begin
			cWaitCnt <= cWaitCnt + 1;
		end
	end
end



always @(posedge CLK4) begin

	if (bHardReset == 1'b0) begin

		Reg002A		<= 8'h00;
		Reg002E_4	<= 1'b0;
		Rd2ECnt		<= 6'b000001;
		Reg0064		<= 8'h80;
		DMA_IrqMask	<= 1'b0;
		DMA_IrqFF 	<= 1'b0;
		PS2WrIDE	 	<= 1'b0;
		MDO[2]		<= 1'b0;
		MDO[1]		<= 1'b0;
		UDO			<= 3'b000;
		DMARMC		<= 1'b0;
		DMA_ARM		<= 1'b0;

		iDQ1			<= 1'b0;
		iIRQ1			<= 1'b0;
		cWr1			<= 1'b0;
		cRd1			<= 1'b0;
		SiRdy1		<= 1'b1;

		SiDQ			<= 1'b0;
		SiIRQ			<= 1'b0;
		ScWr			<= 1'b0;
		ScRd			<= 1'b0;
		SiRdy2		<= 1'b1;

		ScRd1			<= 1'b0;
		ScWr1			<= 1'b0;

		ATV1			<= 1'b0;
		ATV2			<= 1'b0;
		ATV			<= 1'b0;



	end else begin
		ATV1			<= 1'b1;
		ATV2			<= ATV1;
		ATV			<= ATV2;

		iDQ1		<= iDQ;
		iIRQ1		<= iIRQ;
		cWr1		<= cWr;
		cRd1 		<= cRd;
		SiRdy1	<= iRdy;
		DIn1		<= iDi;


		SiDQ		<= iDQ1;
		SiIRQ		<= iIRQ1;
		ScWr		<= cWr1;
		ScRd		<= cRd1;
		SiRdy2	<= SiRdy1;
		if (IDE_DSTB == 1'b1) DIn2		<= DIn1;

		ScRd1		<= ScRd;
		ScWr1		<= ScWr;








		if (cRgRd2E == 1'b1) begin
			if ((Rd2ECnt == 6'b000110) || (Rd2ECnt == 6'b010010) || (Rd2ECnt == 6'b010011) || (Rd2ECnt == 6'b010101) ||
				(Rd2ECnt == 6'b010111) || (Rd2ECnt == 6'b011100) || (Rd2ECnt == 6'b011101) || (Rd2ECnt == 6'b011110) ||
				(Rd2ECnt == 6'b011111) || (Rd2ECnt == 6'b100000) || (Rd2ECnt == 6'b100011) || (Rd2ECnt == 6'b100100) ||
				(Rd2ECnt == 6'b100101) || (Rd2ECnt == 6'b100110) || (Rd2ECnt == 6'b100111) || (Rd2ECnt == 6'b101000) ||
				(Rd2ECnt == 6'b101001) || (Rd2ECnt == 6'b101110) || (Rd2ECnt == 6'b110000) || (Rd2ECnt == 6'b110001) ||
				(Rd2ECnt == 6'b110011) || (Rd2ECnt == 6'b110101) || (Rd2ECnt == 6'b110110) || (Rd2ECnt == 6'b111000) ||
				(Rd2ECnt == 6'b111001) || (Rd2ECnt == 6'b111011) || (Rd2ECnt == 6'b111110))
			begin
				Reg002E_4	<= 1'b1;
			end else begin
				Reg002E_4	<= 1'b0;
			end
			Rd2ECnt <= Rd2ECnt + 1;
		end

		if (cRgWr == 1'b0) begin

			DMARMC	<= ATV;
			DMA_ARM	<= DMARMC;

			if (DMA_IrqMask == 1'b1) begin
				DMA_IrqMask <= DMA_IrqCond;
			end
			if ((DMA_IrqCond == 1'b1) && (DMA_IrqMask == 1'b0)) begin
				DMA_IrqMask	<= DMA_IrqCTRL;
				DMA_IrqFF 	<= DMA_IrqCTRL;
			end
		end else begin

		case (cRgA[6:0])
			7'b0101010: begin
				Reg002A[7:0] <= cRgD[7:0];
				if (cRgD[7:0] == 8'h00) DMA_IrqFF <= 1'b0;
			end

			7'b0101100: begin
				if (cRgD == 8'hE1) begin
					Rd2ECnt <= 6'b00_0001;

				end
			end

			7'b0110010: begin
				DMARMC		<= 1'b0;
				DMA_ARM		<= 1'b0;
				DMA_IrqFF	<= 1'b0;
				Reg0064[2]	<= 1'b0;
				PS2WrIDE		<= cRgD[0];
			end







			7'b1000010: begin
				R42Is03	<= ~(cRgD[7] | cRgD[6] | cRgD[5] | cRgD[4] | cRgD[3] | cRgD[2]) & cRgD[1] & cRgD[0];
			end

			7'b1000100: begin
				R44Is2X	<= ~(cRgD[7] | cRgD[6] | cRgD[4] | cRgD[3]) & cRgD[5];
				R44Is4X	<= ~(cRgD[7] | cRgD[5] | cRgD[4] | cRgD[3]) & cRgD[6];
				R44[2]	<= cRgD[2];
				R44[1]	<= cRgD[1];
				R44[0]	<= cRgD[0];
			end

			7'b1001110: begin
				UDO[2]	<= (D_UnChg & UDO[2]) | (~(D_UnChg) & UDMA_SEL & R44[2]);
				UDO[1]	<= (D_UnChg & UDO[1]) | (~(D_UnChg) & UDMA_SEL & R44[1]);
				UDO[0]	<= (D_UnChg & UDO[0]) | (~(D_UnChg) & UDMA_SEL & R44[0]);
				MDO[2]	<= (D_UnChg & MDO[2]) | (~(D_UnChg) & MDMA_SEL & R44[2]);
				MDO[1]	<= (D_UnChg & MDO[1]) | (~(D_UnChg) & MDMA_SEL & R44[1]);
			end

			7'b1100100: begin
				Reg0064[7:0] <= cRgD[7:0];
			end
		endcase
		end
	end
end
endmodule
module chip(
	inout [15:0] iD	,


	output [2:0] iA,

	output ibCS0		,
	output ibCS1		,
	output ibRST		,
	input	iIRQ		,
	output ibWr		,
	output ibRd		,
	input iDQ 		,
	output ibDK		,
	input iRdy		,
	input ibDASP	,

	input CLKin		,
	input bCSRST	,
	input bCRST		,
	inout [15:0] cDP		,


	inout [15:0] cAP		,



	input bcCS		,
	input bcWr		,
	input bcRd		,
	input bCRT		,

	output	bcWait 	,
	output	bcIRQ		,
	output	cDQ		,
	input		cDK		,

	output	DR245		,
	output	OE245		,



	input ACS_LED  ,
	input HDD_ACK  ,








	inout		TFD0	,
	inout		TFD1	,
	inout 	TFD2	,
	inout		TFD3	,
	output	TFCLK	,
	input		TFSENSE	,
	output	TFCMD		,






	output	JT_Result		,
	output	JT_Pin1		,
	input		JT_bTest
);


wire DCM_RST,CLK1,CLK4,DCM_LOCKED ;

reg DWrite;
wire IDERd,IDEWr;
reg iIRQ1;
reg iDQ1,SiIRQ,SiDQ;
wire iDMARd,iDMAWr ;
wire BufEmpty ;
wire PA_HvSpace,PA_OD_Rdy ;
wire PB_HvSpace,PB_OD_Rdy ;
wire WithinBBlock,BBurstEnd;
wire WithinABlock;

wire iCS0,iCS1,cWr,cRd,iWr,iRd,iDK ;
wire [15:0] RegData;
wire [31:0] DMARAMQ;
reg  [31:0] DMARAMD;
reg  [15:0] DIn1,DIn2;
wire cDMA_OE ;
wire cRdt;
wire RegEB;






wire	[7:0] Reg0038 ;

wire	[15:0] Reg0028 ;



reg	[7:0] Reg002A;
wire [7:0] Reg002E;
reg [7:0] Reg0064;


wire cDOE,cAOE ;
wire IDE_CS;
reg DMA_ARM,DMARMC,PS2WrIDE ;
wire PA_AlmostFull ;
wire [3:0] BufSize;
reg [2:0] R44;
wire INT9,INT9OE,DMA_IrqCond;
reg DMA_IrqMask, DMA_IrqFF;
wire DMA_IrqCTRL ;
wire bHardReset;
reg ATV1,ATV2,ATV;
wire UDMAC,CmdIsEF,UDMA_SEL,MDMA_SEL,D_UnChg ;
reg R42Is03,R44Is2X,R44Is4X;
wire [2:0] UDMA,MDMA;
reg  [2:0] UDO;
reg [2:1] MDO;

wire Combo_CS,Combo_OE ;
reg cWr1,cRd1,ScWr,ScRd,ScWr1,ScRd1 ;
wire [15:0] cAi,cDi,CRC_Q,iDi,iDO,DOutA;
wire iDOEnb,CRC_MUX ;
wire IDEiOE,iDMA_OE ;
reg [6:0] cRgA;
reg [7:0] cRgD;
wire cRgRd2E,cRgWr;
reg bcRd2E;
reg cRgWrEnb ;
reg [5:0] Rd2ECnt;
reg [3:0] cWaitCnt;
reg cWait;

wire iD_245_In,IDE_Rd_Env ;
reg SiRdy2,SiRdy1;
reg IgnoreIRdyPin;
reg Ph0,Ph1,Ph2,Phase3;

wire Reg002E_0, Reg002E_1, Reg002E_2, Reg002E_3, Reg002E_5, Reg002E_6, Reg002E_7;
reg Reg002E_4;
assign Reg002E = {Reg002E_7, Reg002E_6, Reg002E_5, Reg002E_4, Reg002E_3, Reg002E_2, Reg002E_1, Reg002E_0};














wire	DNA_Pass,DNA_RST;
wire [3:0] KILL;




















dcm3	Inst_DCM(
	.CLKIN_IN		(CLKin),
	.RST_IN			(DCM_RST),
	.CLKFX_OUT		(CLK4),
	.CLKIN_IBUFG_OUT(),
	.CLK0_OUT		(CLK1),
	.LOCKED_OUT		(DCM_LOCKED)
);


TF_Stub	Inst_TF_Stub(
	.RESET (DNA_RST),
	.CLK4	(CLK4),
	.TFD0	(TFD0),
	.TFD1	(TFD1),
	.TFD2	(TFD2),
	.TFD3	(TFD3),
	.TF_CLK		(TFCLK),
   .TF_CMD		(TFCMD), 
	.TF_SENSE	(TFSENSE)
);



Top dna1 (
    .reset(DNA_RST), 
    .clk4(CLK4),
	 .IDE_CS(IDE_CS),
    .dna_pass(DNA_Pass),
	 .KILL(KILL)
    );


Reg38	R_38(
	.UDMAC		(UDMAC),
	.PS2WrIDE	(PS2WrIDE),
	.iIRQ			(SiIRQ),
	.cDQ			(cDQ),
	.iDQ			(SiDQ),
	.iDK			(iDK),
	.BufEmpty	(BufEmpty),
	.PB_HvSpace	(PB_HvSpace),
	.BufSize		(BufSize),
	.DOut			(Reg0038)
);

PS2_DMA	PS2DMA(

	.CLK4			(CLK4),
	.Phase3		(Phase3),

	.cDQ			(cDQ),
	.cDK			(cDK),
	.cRd			(cRd),
	.DWrite		(DWrite),

	.DMA_ARM		(DMA_ARM),
	.PS2WrIDE	(PS2WrIDE),

	.PB_HvSpace	(PB_HvSpace),
	.PB_OD_Rdy	(PB_OD_Rdy),

	.WithinBBlock	(WithinBBlock),
	.BBurstEnd	(BBurstEnd),
	.IncAddrB	(IncAddrB),
	.RegEB		(RegEB),
	.EnbB			(EnbB),
	.WrB			(WrB )
);

D_RAM		DMARAM(
	.CLK4			(CLK4),
	.DMA_ARM		(DMA_ARM),
	.PS2WrIDE	(PS2WrIDE),

	.CRC_ARM		(CRC_ARM),
	.CRC_ENB		(CRC_ENB),
	.CRC_Q		(CRC_Q),

	.PA_HvSpace	(PA_HvSpace),
	.PA_OD_Rdy	(PA_OD_Rdy),
	.PA_AlmostFull	(PA_AlmostFull),
	.PA_Full		(PA_Full),
	.PA_Empty	(PA_Empty),
	.WithinABlock	(WithinABlock),

	.PB_HvSpace	(PB_HvSpace),
	.PB_OD_Rdy	(PB_OD_Rdy),

	.BufSize		(BufSize),
	.BufEmpty	(BufEmpty),

	.DInA			(DIn2),
	.DOutA		(DOutA),
	.DInB 		(DMARAMD), 

	.A0			(A0),
	.HWOE			(HWOE),
	.IncAddrA	(IncAddrA),
	.EnbA		(EnbA),
	.WrA			(WrA),
	.RegEA	(RegEA),

	.WithinBBlock	(WithinBBlock),
	.BBurstEnd	(BBurstEnd),
	.IncAddrB		(IncAddrB),
	.EnbB			(EnbB),
	.RegEB			(RegEB),
	.WrB 			(WrB),  
	.DOutB 		(DMARAMQ)
);

IDE_DMA	IDEDMA (

	.CLK4		(CLK4),
	.Phase3	(Phase3),

	.iDK		(iDK),
	.iDQ		(SiDQ),
	.SiRdy1	(SiRdy1),
	.SiRdy2	(SiRdy2),

	.DMA_ARM(DMA_ARM),
	.PS2WrIDE	(PS2WrIDE),
	.UDMA 		(UDMA),
	.MDMA		(MDMA),
	.iDMARd	(iDMARd),
	.iDMAWr	(iDMAWr),
	.iDMA_OE	(iDMA_OE),
	.iD_245_In	(iD_245_In),
	.CRC_MUX	(CRC_MUX),
	.CRC_ARM	(CRC_ARM),
	.CRC_ENB	(CRC_ENB),

	.PA_HvSpace	(PA_HvSpace),
	.PA_OD_Rdy	(PA_OD_Rdy),
	.WithinABlock	(WithinABlock),
	.PA_AlmostFull(PA_AlmostFull),
	.PA_Full		(PA_Full),
	.PA_Empty	(PA_Empty),
	.IDE_DSTB	(IDE_DSTB),
	.IncAddrA	(IncAddrA),
	.A0		(A0),
	.HWOE		(HWOE),
	.EnbA		(EnbA),
	.WrA			(WrA),
	.RegEA	(RegEA)
);






assign JT_Result	= (JT_bTest == 1'b0) ? ( ~DNA_Pass ) : ( HDD_ACK | ACS_LED | ibDASP | bCRT );
assign JT_Pin1		=  TFCLK;








assign DCM_RST		= ~bCRST | ~bCSRST;
assign bHardReset	=  bCRST & DCM_LOCKED;
assign DNA_RST		= ~DCM_LOCKED;

always @(negedge CLK1) begin
	if (DCM_LOCKED == 1'b0) begin
		Ph0 <= 1'b0;
	end else begin
		Ph0 <= ~Ph0;
	end
end

always @(negedge CLK4) begin
	Ph1	<=	Ph0;
	Ph2	<= Ph1;
end

always @(posedge CLK4) begin
	Phase3	<= Ph1 ^ Ph2;
end


	



	assign ibRST	= ~(Reg0064[7]);
	assign ibCS0	= ~(iCS0);
	assign ibCS1	= ~(iCS1);
	assign ibRd		= ~(iRd);
	assign ibWr		= ~(iWr);
	assign ibDK		= ~(iDK);

	assign iRd	= ( IDERd & ~iDK ) | (iDMARd & iDK);
	assign iWr	= ( IDEWr & ~iDK ) | (iDMAWr & iDK);


	assign cRd	= ~bcRd & ~KILL[0];
	assign cRdt	= ~bCRT & ~KILL[0];
	assign cWr	= ~bcWr & ~KILL[0];



	assign INT9OE	= Reg002A[1] | Reg002A[0];
	assign bcIRQ	= (INT9OE == 1'b1) ? ~(INT9) : 1'bZ;
	assign INT9		= (SiIRQ & Reg002A[0]) | (DMA_IrqFF & DMA_IrqCTRL);

	assign cDMA_OE	=	cRdt & cDK;
	assign cDOE	= ATV & (cDMA_OE | Combo_OE);
	assign cDP 	=	(cDOE		== 1'b0) ?	{16{1'bZ}}		:
						(cDK 		== 1'b1) ?	DMARAMQ[15:0]	:
						(IDE_CS	== 1'b1)	?	iDi[15:0]		:	RegData[15:0];
	assign cDi	= cDP;

	assign cAOE	= ATV &  cDMA_OE;
	assign cAP 	=	(cAOE == 1'b0) ? {16{1'bZ}}		: DMARAMQ[31:16];
	assign cAi	= cAP;










	assign Combo_CS = ATV & ~cDK & ~(bcCS | cAi[15] | cAi[14] | cAi[13] | cAi[12] |
												cAi[11] |	cAi[10] | cAi[9] | cAi[8] | cAi[7]);
	assign Combo_OE = cRd & Combo_CS;
	









	assign iD[15:0]	= (iDOEnb == 1'b1) ? iDO[15:0] : {16{1'bZ}};
	assign iDOEnb		= IDEiOE | iDMA_OE;
	assign iDi[15:0]	= iD[15:0];
	assign iDO[15:0]	=	(IDE_CS  == 1'b1) ?	 cDi[15:0] : 
								(CRC_MUX == 1'b1) ? CRC_Q[15:0] : DOutA[15:0];















assign IDE_CS	= Combo_CS & ~iDK & cAi[6] & ~cAi[5];
assign iCS1		= IDE_CS &  cAi[4] & ~KILL[2];
assign iCS0		= IDE_CS & ~cAi[4] & ~KILL[2];
assign iA[2]	= IDE_CS & cAi[3] & ~KILL[1];
assign iA[1]	= IDE_CS & cAi[2] & ~KILL[2];
assign iA[0]	= IDE_CS & cAi[1] & ~KILL[3];
assign IDERd	= IDE_CS & cRd & ~KILL[1];
assign IDEWr	= IDE_CS & cWr & ~KILL[2];
assign IDEiOE	= IDE_CS & cWr;

assign IDE_Rd_Env	= IDE_CS & cRd;












	assign Reg0028[15]	= BufSize[3];
	assign Reg0028[14]	= BufEmpty;



	assign Reg0028[13:2] = 12'b0000_0000_0000;
	assign Reg0028[1]	= cDQ;
	assign Reg0028[0]	= SiIRQ;


	assign RegData[15:8] =	(cAi[6:0] == 7'h28)	?	Reg0028[15:8]	: 8'h00;

	assign RegData[7:0]	=	(cAi[6:0] == 7'h02)	?	8'h13 			:
									(cAi[6:0] == 7'h04)	?	8'h0B 			:
									(cAi[6:0] == 7'h0E)	?	8'h02				:
									(cAi[6:0] == 7'h28)	?	Reg0028[7:0]	:
									(cAi[6:0] == 7'h2A)	?	Reg002A[7:0]	:

									(cAi[6:0] == 7'h2E)	?	Reg002E[7:0]	:
									(cAi[6:0] == 7'h38)	?	Reg0038[7:0]	:
									(cAi[6:0] == 7'h64)	?	Reg0064[7:0]	: 8'h00;




	assign DMA_IrqCond	=	(~(PS2WrIDE) & PB_OD_Rdy) | (PS2WrIDE & PB_HvSpace);
	assign DMA_IrqCTRL	= Reg002A[1];
	

	assign UDMAC	= UDO[2] | UDO[1] | UDO[0];





assign CmdIsEF		= cRgD[7] & cRgD[6] & cRgD[5] & ~(cRgD[4]) &	cRgD[3] & cRgD[2] & cRgD[1] & cRgD[0];
assign UDMA_SEL	= CmdIsEF & R44Is4X & R42Is03;
assign MDMA_SEL 	= CmdIsEF & R44Is2X & R42Is03;
assign D_UnChg		= ~(UDMA_SEL | MDMA_SEL);
assign UDMA[2:0]	= UDO[2:0];
assign MDMA[2] 	= MDO[2];
assign MDMA[1]		= MDO[1];
assign MDMA[0]		= ~(UDO[2] | UDO[1] | UDO[0] | MDO[2] | MDO[1]);

assign Reg002E_7 = 1'b1;
assign Reg002E_6 = 1'b1;
assign Reg002E_5 = 1'b0;

assign Reg002E_3 = 1'b1;
assign Reg002E_2 = 1'b1;
assign Reg002E_1 = 1'b1;
assign Reg002E_0 = 1'b0;



assign cRgWr	= ATV & ScWr1 & ~(ScWr) & cRgWrEnb;
assign cRgRd2E	= ATV & ScRd1 & ~(ScRd) & bcRd2E;

assign OE245	= ~(ATV);
assign DR245	= ~(IDE_Rd_Env | iD_245_In);


always @(posedge bcWr) begin
	cRgWrEnb		<=	Combo_CS & ScWr & ScWr1;
	cRgA[6:0]	<= cAi[6:0];
	cRgD[7:0]	<= cDi[7:0];
end

always @(posedge bcRd) begin
	bcRd2E	<= Combo_CS & ScRd & ScRd1 & ~(cAi[6]) & cAi[5] & ~(cAi[4]) & cAi[3] & cAi[2] & cAi[1] & ~(cAi[0]);
end






always @(posedge CLK4) begin
	if ((Ph1 ^ Ph2) == 1'b1) begin
		DMARAMD[15:0] 	<= cDi[15:0];
		DMARAMD[31:16]	<= cAi[15:0];
	end
end

always @(posedge CLK1) begin
	DWrite	<= cWr & cDK;
end




assign bcWait	= (IDE_CS == 1'b1) ? ~cWait : 1'bZ;

always @(posedge CLK4) begin
	if (IDE_CS == 1'b0) begin
		cWaitCnt	<= 4'b0000;
		cWait		<= 1'b1;
		IgnoreIRdyPin	<= ~SiRdy2;
	end else begin
		if (cWaitCnt == 4'b1010) begin 

			if ((IgnoreIRdyPin == 1'b1) || (SiRdy2 == 1'b1)) begin
				cWait	<= 1'b0;
			end
		end else begin
			cWaitCnt <= cWaitCnt + 1;
		end
	end
end



always @(posedge CLK4) begin

	if (bHardReset == 1'b0) begin

		Reg002A		<= 8'h00;
		Reg002E_4	<= 1'b0;
		Rd2ECnt		<= 6'b000001;
		Reg0064		<= 8'h80;
		DMA_IrqMask	<= 1'b0;
		DMA_IrqFF 	<= 1'b0;
		PS2WrIDE	 	<= 1'b0;
		MDO[2]		<= 1'b0;
		MDO[1]		<= 1'b0;
		UDO			<= 3'b000;
		DMARMC		<= 1'b0;
		DMA_ARM		<= 1'b0;

		iDQ1			<= 1'b0;
		iIRQ1			<= 1'b0;
		cWr1			<= 1'b0;
		cRd1			<= 1'b0;
		SiRdy1		<= 1'b1;

		SiDQ			<= 1'b0;
		SiIRQ			<= 1'b0;
		ScWr			<= 1'b0;
		ScRd			<= 1'b0;
		SiRdy2		<= 1'b1;

		ScRd1			<= 1'b0;
		ScWr1			<= 1'b0;

		ATV1			<= 1'b0;
		ATV2			<= 1'b0;
		ATV			<= 1'b0;



	end else begin
		ATV1			<= 1'b1;
		ATV2			<= ATV1;
		ATV			<= ATV2;

		iDQ1		<= iDQ;
		iIRQ1		<= iIRQ;
		cWr1		<= cWr;
		cRd1 		<= cRd;
		SiRdy1	<= iRdy;
		DIn1		<= iDi;


		SiDQ		<= iDQ1;
		SiIRQ		<= iIRQ1;
		ScWr		<= cWr1;
		ScRd		<= cRd1;
		SiRdy2	<= SiRdy1;
		if (IDE_DSTB == 1'b1) DIn2		<= DIn1;

		ScRd1		<= ScRd;
		ScWr1		<= ScWr;








		if (cRgRd2E == 1'b1) begin
			if ((Rd2ECnt == 6'b000110) || (Rd2ECnt == 6'b010010) || (Rd2ECnt == 6'b010011) || (Rd2ECnt == 6'b010101) ||
				(Rd2ECnt == 6'b010111) || (Rd2ECnt == 6'b011100) || (Rd2ECnt == 6'b011101) || (Rd2ECnt == 6'b011110) ||
				(Rd2ECnt == 6'b011111) || (Rd2ECnt == 6'b100000) || (Rd2ECnt == 6'b100011) || (Rd2ECnt == 6'b100100) ||
				(Rd2ECnt == 6'b100101) || (Rd2ECnt == 6'b100110) || (Rd2ECnt == 6'b100111) || (Rd2ECnt == 6'b101000) ||
				(Rd2ECnt == 6'b101001) || (Rd2ECnt == 6'b101110) || (Rd2ECnt == 6'b110000) || (Rd2ECnt == 6'b110001) ||
				(Rd2ECnt == 6'b110011) || (Rd2ECnt == 6'b110101) || (Rd2ECnt == 6'b110110) || (Rd2ECnt == 6'b111000) ||
				(Rd2ECnt == 6'b111001) || (Rd2ECnt == 6'b111011) || (Rd2ECnt == 6'b111110))
			begin
				Reg002E_4	<= 1'b1;
			end else begin
				Reg002E_4	<= 1'b0;
			end
			Rd2ECnt <= Rd2ECnt + 1;
		end

		if (cRgWr == 1'b0) begin

			DMARMC	<= ATV;
			DMA_ARM	<= DMARMC;

			if (DMA_IrqMask == 1'b1) begin
				DMA_IrqMask <= DMA_IrqCond;
			end
			if ((DMA_IrqCond == 1'b1) && (DMA_IrqMask == 1'b0)) begin
				DMA_IrqMask	<= DMA_IrqCTRL;
				DMA_IrqFF 	<= DMA_IrqCTRL;
			end
		end else begin

		case (cRgA[6:0])
			7'b0101010: begin
				Reg002A[7:0] <= cRgD[7:0];
				if (cRgD[7:0] == 8'h00) DMA_IrqFF <= 1'b0;
			end

			7'b0101100: begin
				if (cRgD == 8'hE1) begin
					Rd2ECnt <= 6'b00_0001;

				end
			end

			7'b0110010: begin
				DMARMC		<= 1'b0;
				DMA_ARM		<= 1'b0;
				DMA_IrqFF	<= 1'b0;
				Reg0064[2]	<= 1'b0;
				PS2WrIDE		<= cRgD[0];
			end







			7'b1000010: begin
				R42Is03	<= ~(cRgD[7] | cRgD[6] | cRgD[5] | cRgD[4] | cRgD[3] | cRgD[2]) & cRgD[1] & cRgD[0];
			end

			7'b1000100: begin
				R44Is2X	<= ~(cRgD[7] | cRgD[6] | cRgD[4] | cRgD[3]) & cRgD[5];
				R44Is4X	<= ~(cRgD[7] | cRgD[5] | cRgD[4] | cRgD[3]) & cRgD[6];
				R44[2]	<= cRgD[2];
				R44[1]	<= cRgD[1];
				R44[0]	<= cRgD[0];
			end

			7'b1001110: begin
				UDO[2]	<= (D_UnChg & UDO[2]) | (~(D_UnChg) & UDMA_SEL & R44[2]);
				UDO[1]	<= (D_UnChg & UDO[1]) | (~(D_UnChg) & UDMA_SEL & R44[1]);
				UDO[0]	<= (D_UnChg & UDO[0]) | (~(D_UnChg) & UDMA_SEL & R44[0]);
				MDO[2]	<= (D_UnChg & MDO[2]) | (~(D_UnChg) & MDMA_SEL & R44[2]);
				MDO[1]	<= (D_UnChg & MDO[1]) | (~(D_UnChg) & MDMA_SEL & R44[1]);
			end

			7'b1100100: begin
				Reg0064[7:0] <= cRgD[7:0];
			end
		endcase
		end
	end
end
endmodule