data/full_repos/permissive/111393021/ifmap_spad.v
data/verilator_xmls/991f273f-7c45-41e1-bf57-16033f7cc4fb.xml
module ifmap_spad(clk, addr, we, data_port);

	input clk;
	input [3:0] addr;
	input we;
	inout [15:0] data_port;
	reg [15:0] data_out;
	reg [15:0] mem [11:0];

	assign data_port = !we ? data_out : 16'bz;

	always @ (posedge clk)	
	begin
		if (we)
			mem[addr] <= data_port;
		else
		begin
			data_out <= mem[addr];
		end

	end
endmodule
module ifmap_spad(clk, addr, we, data_port);


	input clk;
	input [3:0] addr;
	input we;
	inout [15:0] data_port;
	reg [15:0] data_out;
	reg [15:0] mem [11:0];

	assign data_port = !we ? data_out : 16'bz;

	always @ (posedge clk)	
	begin
		if (we)
			mem[addr] <= data_port;
		else
		begin
			data_out <= mem[addr];
		end

	end
endmodule