data/full_repos/permissive/208113388/dlx/ocx_dlx_rx_main.v
1: b"%Error: data/full_repos/permissive/208113388/dlx/ocx_dlx_rx_main.v:356: Cannot find file containing module: 'ocx_dlx_crc'\nocx_dlx_crc crc_mod (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208113388/dlx,data/full_repos/permissive/208113388/ocx_dlx_crc\n             data/full_repos/permissive/208113388/dlx,data/full_repos/permissive/208113388/ocx_dlx_crc.v\n             data/full_repos/permissive/208113388/dlx,data/full_repos/permissive/208113388/ocx_dlx_crc.sv\n             ocx_dlx_crc\n             ocx_dlx_crc.v\n             ocx_dlx_crc.sv\n             obj_dir/ocx_dlx_crc\n             obj_dir/ocx_dlx_crc.v\n             obj_dir/ocx_dlx_crc.sv\n%Error: Exiting due to 1 error(s)\n"
module ocx_dlx_rx_main (

  reset
 ,training_enable
 ,train_ts2
 ,train_ts67

 ,ln0_data
 ,ln1_data
 ,ln2_data
 ,ln3_data
 ,ln4_data
 ,ln5_data
 ,ln6_data
 ,ln7_data
 ,data_flit
 ,disabled_lanes
 ,ctl_header

 ,deskew_valid
 ,deskew_overflow
 ,deskew_all_valid_l0
 ,deskew_all_valid_l1
 ,deskew_all_valid_l2
 ,deskew_all_valid_l3
 ,deskew_all_valid_l4
 ,deskew_all_valid_l5
 ,deskew_all_valid_l6
 ,deskew_all_valid_l7
 ,deskew_reset

 ,flit_out
 ,valid_out
 ,tlx_crc_error
 ,tx_crc_error
 ,rx_TS1
 ,rx_tx_retrain
 ,x4_rx_good_evens
 ,x4_rx_good_odds

 ,nack_out
 ,ack_ptr_vld_out
 ,ack_ptr_out
 ,ack_rtn_out
 ,ack_inc_out

 ,deskew_done_out
 ,lane_swap_out
 ,linkup_out
 ,tl_linkup_out
 ,dlx_config_info
 ,cfg_transmit_order

 ,rx_clk_in



);



input           reset;
input           training_enable;
input           train_ts2;
input           train_ts67;

input [63:0]    ln0_data;
input [63:0]    ln1_data;
input [63:0]    ln2_data;
input [63:0]    ln3_data;
input [63:0]    ln4_data;
input [63:0]    ln5_data;
input [63:0]    ln6_data;
input [63:0]    ln7_data;
input [7:0]     data_flit;
input [7:0]     disabled_lanes;
input [7:0]     ctl_header;

input [7:0]     deskew_valid;
input [7:0]     deskew_overflow;
output          deskew_all_valid_l0;
output          deskew_all_valid_l1;
output          deskew_all_valid_l2;
output          deskew_all_valid_l3;
output          deskew_all_valid_l4;
output          deskew_all_valid_l5;
output          deskew_all_valid_l6;
output          deskew_all_valid_l7;
output          deskew_reset;

output [511:0]  flit_out;
output          valid_out;
output          tlx_crc_error;
output          tx_crc_error;
input  [7:0]    rx_TS1;
output          rx_tx_retrain;
output          x4_rx_good_evens;
output          x4_rx_good_odds;

output          nack_out;
output          ack_ptr_vld_out;
output [6:0]    ack_ptr_out;
output [4:0]    ack_rtn_out;
output [3:0]    ack_inc_out;

output          deskew_done_out;
output          lane_swap_out;
output          linkup_out;
output          tl_linkup_out;
output [31:0]   dlx_config_info;   
input           cfg_transmit_order;

input           rx_clk_in;










reg  [511:0]    flit_q ;
reg  [35:0]     crc_bits0_q;
reg  [35:0]     crc_bits1_q;
reg             crc_init_q;
reg  [3:0]      run_length_q;
reg             flit_vld_q;
reg             tlx_crc_error_q;
reg             tx_crc_error_q;
reg             replay_pending_q;
reg             replay_ip_q;

reg  [6:0]      rx_ack_ptr_q;
reg  [6:0]      rx_curr_ptr_q;
reg             nack_q;
reg             tx_ack_ptr_vld_q;
reg  [6:0]      tx_ack_ptr_q;
reg  [4:0]      tx_ack_rtn_q;
reg  [3:0]      ack_cnt_q;
reg  [3:0]      tx_ack_inc_q;
reg             deskew_reset_q;
reg  [63:0]     ln0_data_d1_q; 
reg  [63:0]     ln1_data_d1_q;
reg  [4:0]      ln2_data_d1_q;
reg  [4:0]      ln3_data_d1_q;
reg             deskew_all_valid_d1_q; 
reg             deskew_all_valid_q;
reg             deskew_all_valid_l0_q;
reg             deskew_all_valid_l1_q;
reg             deskew_all_valid_l2_q;
reg             deskew_all_valid_l3_q;
reg             deskew_all_valid_l4_q;
reg             deskew_all_valid_l5_q;
reg             deskew_all_valid_l6_q;
reg             deskew_all_valid_l7_q;
reg  [7:0]      replay_deskew_cntr_q ;
reg  [23:5]     prev_deskew_q;
reg             deskew_done_q;
reg             lane_swap_q;
reg             linkup_q;
reg             tl_linkup_q;
reg             link_is_tl_q;
reg             link_is_tl_d1_q;
reg             link_is_tl_d2_q;
reg             link_is_tl_d3_q;
wire [511:0]    flit_din;
wire [511:0]    flit_to_tl_din;
reg  [511:0]    flit_to_tl_q;
wire [35:0]     crc_bits, crc_bits0_din, crc_bits1_din;
wire [35:0]     crc_bits0_out, crc_bits1_out;
wire            crc_init_din;
wire [3:0]      run_length_din;
wire            flit_vld_din;
wire            tlx_crc_error_din;
wire            tx_crc_error_din;
wire            replay_pending_din;
wire            replay_ip_din;
wire [31:0]     dlx_config_din;
reg  [31:0]     dlx_config_q;
wire [7:0]      dlx_link_error_din;
reg  [7:0]      dlx_link_error_q;
wire [7:0]      disabled_lanes_din;
reg  [7:0]      disabled_lanes_q;
wire            good_evens_only_din;
reg             good_evens_only_q;
wire            good_odds_only_din;
reg             good_odds_only_q;
wire            x4_not_x8_rx_mode_din;
reg             x4_not_x8_rx_mode_q;
wire            flit_cycle_odd_din;
reg             flit_cycle_odd_q;
wire            is_crc_data_flit_din;
reg             is_crc_data_flit_q;
wire [6:0]      rx_ack_ptr_din;
wire [6:0]      rx_curr_ptr_din;
wire            nack_din;
wire            tx_ack_ptr_vld_din;
wire [6:0]      tx_ack_ptr_din;
wire [4:0]      tx_ack_rtn_din;
wire [3:0]      ack_cnt_din;
wire [3:0]      tx_ack_inc_din;
wire            deskew_reset_din;
wire [63:0]     ln0_data_d1_din; 
wire [63:0]     ln1_data_d1_din;
wire [4:0]      ln2_data_d1_din;
wire [4:0]      ln3_data_d1_din;
wire            deskew_all_valid_d1_din; 
wire            deskew_all_valid_din;
wire            deskew_all_valid_l0_din;
wire            deskew_all_valid_l1_din;
wire            deskew_all_valid_l2_din;
wire            deskew_all_valid_l3_din;
wire            deskew_all_valid_l4_din;
wire            deskew_all_valid_l5_din;
wire            deskew_all_valid_l6_din;
wire            deskew_all_valid_l7_din;
wire [7:0]      replay_deskew_cntr_din;
wire [23:5]     prev_deskew_din;
wire            deskew_done_din;
wire            lane_swap_din;
wire            linkup_din;
wire            tl_linkup_din;
wire            link_is_tl_din;
wire            link_is_tl_d1_din;
wire            link_is_tl_d2_din;
wire            link_is_tl_d3_din;
wire            retrain_din;
reg             retrain_q;
wire            retrain_d1_din;
reg             retrain_d1_q;
wire            retrain_d2_din;
reg             retrain_d2_q;
wire            retrain_d3_din;
reg             retrain_d3_q;
wire [511:0]    flit;
wire            master_valid;
wire            master_valid_din;
reg             master_valid_q;
wire            master_valid_dly_din;
reg             master_valid_dly_q;
wire [3:0]      num_good_flits_rcvd;
wire            replay_pending;
wire            replay_ip;
wire            crc_nonzero;


wire            nack_dly_din;
reg             nack_dly_q;
wire            crc_error;
wire            is_data_flit;
wire            is_ctrl_flit;
wire            is_dl2dl_flit;
wire            is_replay_flit;
wire            is_idle_flit;
wire            are_deskew;
wire            matching_deskew;
wire            good_odds;
wire            good_evens;
wire            valid_crc_din;
wire            is_crc_data_flit;
wire  [3:0]     sum_ctl_headers;
wire  [15:0]    crc_error_cntr_din;
wire            start_cycle;
reg [15:0] crc_error_cntr_q; 








assign flit[511:0] =  {ln7_data[63:0] , ln6_data[63:0] , ln5_data[63:0] , ln4_data[63:0] , ln3_data[63:0] , ln2_data[63:0] , ln1_data[63:0] , ln0_data[63:0] } ;

assign deskew_all_valid_d1_din = deskew_all_valid_q;
assign ln0_data_d1_din[63:0]   = ln0_data[63:0];
assign ln1_data_d1_din[63:0]   = ln1_data[63:0];
assign ln2_data_d1_din[4:0]    = ln2_data[4:0];
assign ln3_data_d1_din[4:0]    = ln3_data[4:0];

assign flit_din[511:0] = flit[511:0];

assign flit_to_tl_din[511:0] = is_data_flit ? flit_q[511:0]:
                                              {46'b0, flit_q[465:0]};

assign flit_out[511:0] = flit_to_tl_q[511:0];



assign start_cycle =  (({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b1000) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b0100) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b0010) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b0001) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b0000) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b1000) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b0100) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b0010) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b0001) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b0000)) &
                     ~(({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b1110) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b0111) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b1011) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b1101) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b1111) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b1110) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b0111) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b1011) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b1101) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b1111));

assign flit_cycle_odd_din = start_cycle                     ? 1'b0:
                             master_valid                   ? ~flit_cycle_odd_q:
                                                               flit_cycle_odd_q;


assign x4_rx_good_evens =  good_evens_only_q ; 
assign x4_rx_good_odds  =  good_odds_only_q ; 


assign valid_crc_din = (flit_cycle_odd_q & master_valid) | ~x4_not_x8_rx_mode_q;




ocx_dlx_crc crc_mod (
  .init                 (crc_init_q)
 ,.checkbits_in         (crc_bits)
 ,.data                 (flit[511:0])
 ,.checkbits0_out        (crc_bits0_out[35:0])
 ,.checkbits1_out        (crc_bits1_out[35:0])

);

assign crc_bits = crc_bits0_q ^ crc_bits1_q;


assign crc_bits0_din[35:0] =                                                                    reset ? 36'h000000000:
                             master_valid & valid_crc_din & (flit_cycle_odd_q | ~x4_not_x8_rx_mode_q) ? crc_bits0_out[35:0]:
                                                                                                        crc_bits0_q[35:0];
assign crc_bits1_din[35:0] =                                                                    reset ? 36'h000000000:
                             master_valid & valid_crc_din & (flit_cycle_odd_q | ~x4_not_x8_rx_mode_q) ? crc_bits1_out[35:0]:
                                                                                                        crc_bits1_q[35:0];



assign is_crc_data_flit   = ~x4_not_x8_rx_mode_q ?                     (run_length_din[3:0] != 4'b0000):
                                                   flit_cycle_odd_q  & (run_length_q[3:0]   != 4'b0000);                                           


assign is_crc_data_flit_din = master_valid ? is_crc_data_flit:
                                             is_crc_data_flit_q;



assign crc_init_din = (master_valid & ~is_crc_data_flit & ~(is_crc_data_flit_q & x4_not_x8_rx_mode_q)) | reset | ~link_is_tl_d3_q;


assign crc_nonzero = (|crc_bits) & linkup_q;

assign crc_error          =  ~x4_not_x8_rx_mode_q ?                      master_valid_q & ~is_crc_data_flit_q & crc_nonzero:
                                                    ~flit_cycle_odd_q & (master_valid_q & ~is_crc_data_flit_q & crc_nonzero);

assign replay_pending     = ~is_replay_flit & (crc_error | replay_pending_q) & ~reset;

assign replay_ip          = is_replay_flit | (replay_ip_q & (rx_curr_ptr_q[6:0] != rx_ack_ptr_q[6:0]));



assign replay_pending_din = replay_pending;
assign replay_ip_din      = replay_ip;

assign flit_vld_din       = (is_data_flit | is_ctrl_flit) & ~(replay_pending | replay_ip) & linkup_q ;
assign crc_error_cntr_din[15:0] = reset     ? 16'h0000 :
                                  crc_error ? crc_error_cntr_q[15:0] + 16'h0001 :
                                              crc_error_cntr_q[15:0];


assign tlx_crc_error_din  = is_replay_flit | crc_error;
assign tx_crc_error_din   = crc_error | (replay_pending_q & (&(replay_deskew_cntr_q[7:0])));



assign valid_out        = flit_vld_q;
assign tlx_crc_error    = tlx_crc_error_q;
assign tx_crc_error     = tx_crc_error_q;



assign nack_din            = (is_replay_flit & flit_q[468]);
assign tx_ack_ptr_vld_din  = is_replay_flit;
assign tx_ack_ptr_din[6:0] = {7{is_replay_flit}} & flit_q[422:416];

assign tx_ack_rtn_din[4:0] = ((is_ctrl_flit | is_dl2dl_flit) & ~replay_pending_q & train_ts67)  ? flit_q[475:471]:
                                                                                                  5'b0;



assign ack_cnt_din[3:0] = (~reset & is_data_flit)                  ? (ack_cnt_q[3:0] + 4'b0001) :
                          (x4_not_x8_rx_mode_q & flit_cycle_odd_q) ? ack_cnt_q[3:0]:
                          (~reset & ~master_valid_q)               ? ack_cnt_q[3:0] :
                                                                     4'b0;

assign num_good_flits_rcvd[3:0] = (~reset & is_ctrl_flit & linkup_q) ? (ack_cnt_q[3:0] + 4'b0001) :
                                                                        4'b0;

assign tx_ack_inc_din[3:0] = ( ~(replay_pending | replay_ip) & master_valid_q ) ? num_good_flits_rcvd[3:0] :
                                                                                4'b0;


assign rx_ack_ptr_din[6:0] = {7{~reset}} & (rx_ack_ptr_q[6:0] + {3'b0, tx_ack_inc_din[3:0]});
assign rx_curr_ptr_din[6:0] = reset            ? 7'b0 :
                              (is_replay_flit) ? flit_q[438:432] :
                                                 (rx_curr_ptr_q[6:0] + {3'b0, num_good_flits_rcvd[3:0]});


assign nack_out   =  master_valid_dly_q ? nack_q:
                                          nack_dly_q;

assign nack_dly_din = master_valid_dly_q ? nack_q:
                                           nack_dly_q; 

assign ack_ptr_vld_out          = tx_ack_ptr_vld_q & train_ts67;
assign ack_ptr_out[6:0]         = tx_ack_ptr_q[6:0];
assign ack_rtn_out[4:0]         = tx_ack_rtn_q[4:0];
assign ack_inc_out[3:0]         = tx_ack_inc_q[3:0];





assign deskew_reset_din = |(deskew_overflow[7:0] & ~disabled_lanes_q[7:0]) | reset;

assign deskew_all_valid_l0_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l1_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l2_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l3_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l4_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l5_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l6_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l7_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;

assign are_deskew = good_evens ? deskew_all_valid_d1_q & (ln0_data_d1_q[63:24] == 40'h4B1E1E1E1E):
                                 deskew_all_valid_d1_q & (ln1_data_d1_q[63:24] == 40'h4B1E1E1E1E);

assign matching_deskew = good_evens ? are_deskew & (ln0_data_d1_q[23:5] == prev_deskew_q[23:5]):
                                      are_deskew & (ln1_data_d1_q[23:5] == prev_deskew_q[23:5]);

assign prev_deskew_din[23:5] = (good_evens & are_deskew) ? ln0_data_d1_q[23:5] :
                                              are_deskew ? ln1_data_d1_q[23:5] :
                                                           (prev_deskew_q[23:5] & {19{~reset}});

assign replay_deskew_cntr_din[7:0] = (reset | (replay_pending_din & ~replay_pending_q))       ? 8'b0 :
                                     ((training_enable & matching_deskew) | (replay_pending)) ? (replay_deskew_cntr_q[7:0] + 8'b00000001) :
                                                                                                 replay_deskew_cntr_q[7:0];


assign deskew_done_din = ((deskew_all_valid_q & (&(replay_deskew_cntr_q[2:0]))) | deskew_done_q) & ~reset;
                



assign lane_swap_din = ~reset & ( lane_swap_q | (matching_deskew &
                                ((good_evens & (ln0_data_d1_q[4:0] == 5'b00111)  & (ln2_data_d1_q[4:0] == 5'b00101)) | (good_odds & (ln1_data_d1_q[4:0] == 5'b00110) & (ln3_data_d1_q[4:0] == 5'b00100))) ));

assign linkup_din     = ~(reset | (retrain_q & retrain_d1_q & retrain_d2_q)) & (linkup_q | ((&(data_flit[7:0] | disabled_lanes_q[7:0])) & train_ts67));
assign tl_linkup_din  = ~reset & (tl_linkup_q | ( (&(data_flit[7:0] | disabled_lanes_q[7:0]))  & train_ts67) );

assign link_is_tl_din    = ~reset & ~train_ts2 & (link_is_tl_q | (train_ts67 & ~start_cycle));
assign link_is_tl_d1_din = reset ? 1'b0 : deskew_all_valid_q ? link_is_tl_q    : link_is_tl_d1_q;
assign link_is_tl_d2_din = reset ? 1'b0 : deskew_all_valid_q ? link_is_tl_d1_q : link_is_tl_d2_q;
assign link_is_tl_d3_din = reset ? 1'b0 : deskew_all_valid_q ? link_is_tl_d2_q : link_is_tl_d3_q;



assign sum_ctl_headers[3:0] = {3'b000, (ctl_header[7] & ~disabled_lanes_q[7])} +
                              {3'b000, (ctl_header[6] & ~disabled_lanes_q[6])} +
                              {3'b000, (ctl_header[5] & ~disabled_lanes_q[5])} +
                              {3'b000, (ctl_header[4] & ~disabled_lanes_q[4])} +
                              {3'b000, (ctl_header[3] & ~disabled_lanes_q[3])} +
                              {3'b000, (ctl_header[2] & ~disabled_lanes_q[2])} +
                              {3'b000, (ctl_header[1] & ~disabled_lanes_q[1])} +
                              {3'b000, (ctl_header[0] & ~disabled_lanes_q[0])};

assign retrain_din    = (link_is_tl_q     & (|sum_ctl_headers[3:1]) & ~training_enable) | (train_ts67 & ~link_is_tl_q & (|(ctl_header[7:0] & rx_TS1[7:0] & ~disabled_lanes_q[7:0])));
assign retrain_d1_din = retrain_q;   
assign retrain_d2_din = retrain_d1_q;
assign retrain_d3_din = retrain_d2_q;

assign rx_tx_retrain = retrain_q & retrain_d1_q & retrain_d2_q;


assign disabled_lanes_din = disabled_lanes;

assign good_odds                   = ~(disabled_lanes_q[7] | disabled_lanes_q[5] | disabled_lanes_q[3] | disabled_lanes_q[1]); 
assign good_evens                  = ~(disabled_lanes_q[6] | disabled_lanes_q[4] | disabled_lanes_q[2] | disabled_lanes_q[0]); 

assign good_odds_only_din          = reset ? 1'b0 :
                                             good_odds & ~good_evens;

assign good_evens_only_din         = reset ? 1'b0 :
                                             good_evens & ~good_odds;

assign x4_not_x8_rx_mode_din       = good_odds_only_q || good_evens_only_q;


assign deskew_all_valid_l0 = deskew_all_valid_l0_q;
assign deskew_all_valid_l1 = deskew_all_valid_l1_q;
assign deskew_all_valid_l2 = deskew_all_valid_l2_q;
assign deskew_all_valid_l3 = deskew_all_valid_l3_q;
assign deskew_all_valid_l4 = deskew_all_valid_l4_q;
assign deskew_all_valid_l5 = deskew_all_valid_l5_q;
assign deskew_all_valid_l6 = deskew_all_valid_l6_q;
assign deskew_all_valid_l7 = deskew_all_valid_l7_q;
assign deskew_reset        = deskew_reset_q;
assign deskew_done_out     = deskew_done_q;
assign lane_swap_out       = lane_swap_q;
assign linkup_out          = linkup_q;
assign tl_linkup_out       = tl_linkup_q;





assign master_valid         = deskew_all_valid_q & link_is_tl_d3_q & ~reset;
assign master_valid_din     = master_valid;
assign master_valid_dly_din = master_valid_q;

assign is_data_flit   = ~x4_not_x8_rx_mode_q ?                     master_valid_q & linkup_q & (run_length_q[3:0] != 4'b0000):
                                               ~flit_cycle_odd_q & master_valid_q & linkup_q & (run_length_q[3:0] != 4'b0000);                                           

assign is_ctrl_flit   = ~x4_not_x8_rx_mode_q ?                     master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] <= 4'b1000):
                                               ~flit_cycle_odd_q & master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] <= 4'b1000);  

assign is_dl2dl_flit  = ~x4_not_x8_rx_mode_q ?                     master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] > 4'b1000):
                                               ~flit_cycle_odd_q & master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] > 4'b1000);   

assign is_replay_flit = ~x4_not_x8_rx_mode_q ?                     master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] == 4'hA):
                                               ~flit_cycle_odd_q & master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] == 4'hA);  

assign is_idle_flit   = ~x4_not_x8_rx_mode_q ?                     master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] == 4'hF):
                                               ~flit_cycle_odd_q & master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] == 4'hF);  


assign run_length_din[3:0] = ~train_ts67                                  ? 4'b0000:
                             is_data_flit                                 ? (run_length_q[3:0] - 4'b0001):
                             is_ctrl_flit & ~flit_q[467]                  ? flit_q[451:448]:
                             is_replay_flit & ~flit_q[467]                ? flit_q[455:452]:
                             is_idle_flit & ~(flit_q[455:452] == 4'b0000) ? flit_q[455:452]:
                             ~master_valid_q & ~reset                     ? run_length_q[3:0]:
                             flit_cycle_odd_q                             ? run_length_q[3:0]:
                                                                            4'b0000;




assign dlx_link_error_din[7:0] = is_replay_flit ? flit_q[463:456]:
                                                  dlx_link_error_q[7:0];

assign dlx_config_din[31:0] = is_replay_flit ? flit_q[415:384]:
                                               dlx_config_q[31:0];

assign dlx_config_info[31:0] = dlx_config_q[31:0];

always @(posedge rx_clk_in) begin
flit_q[511:0]              <= flit_din[511:0];
flit_to_tl_q[511:0]        <= flit_to_tl_din[511:0];
flit_cycle_odd_q           <= flit_cycle_odd_din;
crc_bits0_q[35:0]          <= crc_bits0_din[35:0];
crc_bits1_q[35:0]          <= crc_bits1_din[35:0];
crc_init_q                 <= crc_init_din;
replay_pending_q           <= replay_pending_din;
replay_ip_q                <= replay_ip_din;
flit_vld_q                 <= flit_vld_din;
tlx_crc_error_q            <= tlx_crc_error_din;
tx_crc_error_q             <= tx_crc_error_din;
deskew_reset_q             <= deskew_reset_din;
deskew_all_valid_d1_q      <= deskew_all_valid_d1_din;
ln0_data_d1_q[63:0]        <= ln0_data_d1_din[63:0];
ln1_data_d1_q[63:0]        <= ln1_data_d1_din[63:0];
ln2_data_d1_q[4:0]         <= ln2_data_d1_din[4:0];
ln3_data_d1_q[4:0]         <= ln3_data_d1_din[4:0];
deskew_all_valid_q         <= deskew_all_valid_din;
deskew_all_valid_l0_q      <= deskew_all_valid_l0_din;
deskew_all_valid_l1_q      <= deskew_all_valid_l1_din;
deskew_all_valid_l2_q      <= deskew_all_valid_l2_din;
deskew_all_valid_l3_q      <= deskew_all_valid_l3_din;
deskew_all_valid_l4_q      <= deskew_all_valid_l4_din;
deskew_all_valid_l5_q      <= deskew_all_valid_l5_din;
deskew_all_valid_l6_q      <= deskew_all_valid_l6_din;
deskew_all_valid_l7_q      <= deskew_all_valid_l7_din;
prev_deskew_q[23:5]        <= prev_deskew_din[23:5];
replay_deskew_cntr_q[7:0]  <= replay_deskew_cntr_din[7:0];
deskew_done_q              <= deskew_done_din;
lane_swap_q                <= lane_swap_din;
linkup_q                   <= linkup_din;
tl_linkup_q                <= tl_linkup_din;
link_is_tl_q               <= link_is_tl_din;
link_is_tl_d1_q            <= link_is_tl_d1_din;
link_is_tl_d2_q            <= link_is_tl_d2_din;
link_is_tl_d3_q            <= link_is_tl_d3_din;
retrain_q                  <= retrain_din;
retrain_d1_q               <= retrain_d1_din;
retrain_d2_q               <= retrain_d2_din;
retrain_d3_q               <= retrain_d3_din;
disabled_lanes_q           <= disabled_lanes_din;
good_evens_only_q          <= good_evens_only_din;
good_odds_only_q           <= good_odds_only_din;
x4_not_x8_rx_mode_q        <= x4_not_x8_rx_mode_din;
nack_q                     <= nack_din;
tx_ack_ptr_vld_q           <= tx_ack_ptr_vld_din;
tx_ack_ptr_q[6:0]          <= tx_ack_ptr_din[6:0];
tx_ack_rtn_q[4:0]          <= tx_ack_rtn_din[4:0];
ack_cnt_q[3:0]             <= ack_cnt_din[3:0];
tx_ack_inc_q[3:0]          <= tx_ack_inc_din[3:0];
rx_ack_ptr_q[6:0]          <= rx_ack_ptr_din[6:0];
rx_curr_ptr_q[6:0]         <= rx_curr_ptr_din[6:0];
run_length_q[3:0]          <= run_length_din[3:0];
dlx_config_q[31:0]         <= dlx_config_din[31:0];
dlx_link_error_q[7:0]      <= dlx_link_error_din[7:0];
is_crc_data_flit_q         <= is_crc_data_flit_din;
master_valid_q             <= master_valid_din;
master_valid_dly_q         <= master_valid_dly_din;

nack_dly_q                 <= nack_dly_din;
crc_error_cntr_q[15:0]     <= crc_error_cntr_din[15:0];
end

endmodule
module ocx_dlx_rx_main (

  reset
 ,training_enable
 ,train_ts2
 ,train_ts67

 ,ln0_data
 ,ln1_data
 ,ln2_data
 ,ln3_data
 ,ln4_data
 ,ln5_data
 ,ln6_data
 ,ln7_data
 ,data_flit
 ,disabled_lanes
 ,ctl_header

 ,deskew_valid
 ,deskew_overflow
 ,deskew_all_valid_l0
 ,deskew_all_valid_l1
 ,deskew_all_valid_l2
 ,deskew_all_valid_l3
 ,deskew_all_valid_l4
 ,deskew_all_valid_l5
 ,deskew_all_valid_l6
 ,deskew_all_valid_l7
 ,deskew_reset

 ,flit_out
 ,valid_out
 ,tlx_crc_error
 ,tx_crc_error
 ,rx_TS1
 ,rx_tx_retrain
 ,x4_rx_good_evens
 ,x4_rx_good_odds

 ,nack_out
 ,ack_ptr_vld_out
 ,ack_ptr_out
 ,ack_rtn_out
 ,ack_inc_out

 ,deskew_done_out
 ,lane_swap_out
 ,linkup_out
 ,tl_linkup_out
 ,dlx_config_info
 ,cfg_transmit_order

 ,rx_clk_in



);




input           reset;
input           training_enable;
input           train_ts2;
input           train_ts67;

input [63:0]    ln0_data;
input [63:0]    ln1_data;
input [63:0]    ln2_data;
input [63:0]    ln3_data;
input [63:0]    ln4_data;
input [63:0]    ln5_data;
input [63:0]    ln6_data;
input [63:0]    ln7_data;
input [7:0]     data_flit;
input [7:0]     disabled_lanes;
input [7:0]     ctl_header;

input [7:0]     deskew_valid;
input [7:0]     deskew_overflow;
output          deskew_all_valid_l0;
output          deskew_all_valid_l1;
output          deskew_all_valid_l2;
output          deskew_all_valid_l3;
output          deskew_all_valid_l4;
output          deskew_all_valid_l5;
output          deskew_all_valid_l6;
output          deskew_all_valid_l7;
output          deskew_reset;

output [511:0]  flit_out;
output          valid_out;
output          tlx_crc_error;
output          tx_crc_error;
input  [7:0]    rx_TS1;
output          rx_tx_retrain;
output          x4_rx_good_evens;
output          x4_rx_good_odds;

output          nack_out;
output          ack_ptr_vld_out;
output [6:0]    ack_ptr_out;
output [4:0]    ack_rtn_out;
output [3:0]    ack_inc_out;

output          deskew_done_out;
output          lane_swap_out;
output          linkup_out;
output          tl_linkup_out;
output [31:0]   dlx_config_info;   
input           cfg_transmit_order;

input           rx_clk_in;










reg  [511:0]    flit_q ;
reg  [35:0]     crc_bits0_q;
reg  [35:0]     crc_bits1_q;
reg             crc_init_q;
reg  [3:0]      run_length_q;
reg             flit_vld_q;
reg             tlx_crc_error_q;
reg             tx_crc_error_q;
reg             replay_pending_q;
reg             replay_ip_q;

reg  [6:0]      rx_ack_ptr_q;
reg  [6:0]      rx_curr_ptr_q;
reg             nack_q;
reg             tx_ack_ptr_vld_q;
reg  [6:0]      tx_ack_ptr_q;
reg  [4:0]      tx_ack_rtn_q;
reg  [3:0]      ack_cnt_q;
reg  [3:0]      tx_ack_inc_q;
reg             deskew_reset_q;
reg  [63:0]     ln0_data_d1_q; 
reg  [63:0]     ln1_data_d1_q;
reg  [4:0]      ln2_data_d1_q;
reg  [4:0]      ln3_data_d1_q;
reg             deskew_all_valid_d1_q; 
reg             deskew_all_valid_q;
reg             deskew_all_valid_l0_q;
reg             deskew_all_valid_l1_q;
reg             deskew_all_valid_l2_q;
reg             deskew_all_valid_l3_q;
reg             deskew_all_valid_l4_q;
reg             deskew_all_valid_l5_q;
reg             deskew_all_valid_l6_q;
reg             deskew_all_valid_l7_q;
reg  [7:0]      replay_deskew_cntr_q ;
reg  [23:5]     prev_deskew_q;
reg             deskew_done_q;
reg             lane_swap_q;
reg             linkup_q;
reg             tl_linkup_q;
reg             link_is_tl_q;
reg             link_is_tl_d1_q;
reg             link_is_tl_d2_q;
reg             link_is_tl_d3_q;
wire [511:0]    flit_din;
wire [511:0]    flit_to_tl_din;
reg  [511:0]    flit_to_tl_q;
wire [35:0]     crc_bits, crc_bits0_din, crc_bits1_din;
wire [35:0]     crc_bits0_out, crc_bits1_out;
wire            crc_init_din;
wire [3:0]      run_length_din;
wire            flit_vld_din;
wire            tlx_crc_error_din;
wire            tx_crc_error_din;
wire            replay_pending_din;
wire            replay_ip_din;
wire [31:0]     dlx_config_din;
reg  [31:0]     dlx_config_q;
wire [7:0]      dlx_link_error_din;
reg  [7:0]      dlx_link_error_q;
wire [7:0]      disabled_lanes_din;
reg  [7:0]      disabled_lanes_q;
wire            good_evens_only_din;
reg             good_evens_only_q;
wire            good_odds_only_din;
reg             good_odds_only_q;
wire            x4_not_x8_rx_mode_din;
reg             x4_not_x8_rx_mode_q;
wire            flit_cycle_odd_din;
reg             flit_cycle_odd_q;
wire            is_crc_data_flit_din;
reg             is_crc_data_flit_q;
wire [6:0]      rx_ack_ptr_din;
wire [6:0]      rx_curr_ptr_din;
wire            nack_din;
wire            tx_ack_ptr_vld_din;
wire [6:0]      tx_ack_ptr_din;
wire [4:0]      tx_ack_rtn_din;
wire [3:0]      ack_cnt_din;
wire [3:0]      tx_ack_inc_din;
wire            deskew_reset_din;
wire [63:0]     ln0_data_d1_din; 
wire [63:0]     ln1_data_d1_din;
wire [4:0]      ln2_data_d1_din;
wire [4:0]      ln3_data_d1_din;
wire            deskew_all_valid_d1_din; 
wire            deskew_all_valid_din;
wire            deskew_all_valid_l0_din;
wire            deskew_all_valid_l1_din;
wire            deskew_all_valid_l2_din;
wire            deskew_all_valid_l3_din;
wire            deskew_all_valid_l4_din;
wire            deskew_all_valid_l5_din;
wire            deskew_all_valid_l6_din;
wire            deskew_all_valid_l7_din;
wire [7:0]      replay_deskew_cntr_din;
wire [23:5]     prev_deskew_din;
wire            deskew_done_din;
wire            lane_swap_din;
wire            linkup_din;
wire            tl_linkup_din;
wire            link_is_tl_din;
wire            link_is_tl_d1_din;
wire            link_is_tl_d2_din;
wire            link_is_tl_d3_din;
wire            retrain_din;
reg             retrain_q;
wire            retrain_d1_din;
reg             retrain_d1_q;
wire            retrain_d2_din;
reg             retrain_d2_q;
wire            retrain_d3_din;
reg             retrain_d3_q;
wire [511:0]    flit;
wire            master_valid;
wire            master_valid_din;
reg             master_valid_q;
wire            master_valid_dly_din;
reg             master_valid_dly_q;
wire [3:0]      num_good_flits_rcvd;
wire            replay_pending;
wire            replay_ip;
wire            crc_nonzero;


wire            nack_dly_din;
reg             nack_dly_q;
wire            crc_error;
wire            is_data_flit;
wire            is_ctrl_flit;
wire            is_dl2dl_flit;
wire            is_replay_flit;
wire            is_idle_flit;
wire            are_deskew;
wire            matching_deskew;
wire            good_odds;
wire            good_evens;
wire            valid_crc_din;
wire            is_crc_data_flit;
wire  [3:0]     sum_ctl_headers;
wire  [15:0]    crc_error_cntr_din;
wire            start_cycle;
reg [15:0] crc_error_cntr_q; 








assign flit[511:0] =  {ln7_data[63:0] , ln6_data[63:0] , ln5_data[63:0] , ln4_data[63:0] , ln3_data[63:0] , ln2_data[63:0] , ln1_data[63:0] , ln0_data[63:0] } ;

assign deskew_all_valid_d1_din = deskew_all_valid_q;
assign ln0_data_d1_din[63:0]   = ln0_data[63:0];
assign ln1_data_d1_din[63:0]   = ln1_data[63:0];
assign ln2_data_d1_din[4:0]    = ln2_data[4:0];
assign ln3_data_d1_din[4:0]    = ln3_data[4:0];

assign flit_din[511:0] = flit[511:0];

assign flit_to_tl_din[511:0] = is_data_flit ? flit_q[511:0]:
                                              {46'b0, flit_q[465:0]};

assign flit_out[511:0] = flit_to_tl_q[511:0];



assign start_cycle =  (({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b1000) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b0100) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b0010) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b0001) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b0000) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b1000) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b0100) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b0010) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b0001) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b0000)) &
                     ~(({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b1110) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b0111) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b1011) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b1101) |
                       ({data_flit[7], data_flit[5], data_flit[3], data_flit[1]} == 4'b1111) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b1110) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b0111) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b1011) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b1101) |
                       ({data_flit[6], data_flit[4], data_flit[2], data_flit[0]} == 4'b1111));

assign flit_cycle_odd_din = start_cycle                     ? 1'b0:
                             master_valid                   ? ~flit_cycle_odd_q:
                                                               flit_cycle_odd_q;


assign x4_rx_good_evens =  good_evens_only_q ; 
assign x4_rx_good_odds  =  good_odds_only_q ; 


assign valid_crc_din = (flit_cycle_odd_q & master_valid) | ~x4_not_x8_rx_mode_q;




ocx_dlx_crc crc_mod (
  .init                 (crc_init_q)
 ,.checkbits_in         (crc_bits)
 ,.data                 (flit[511:0])
 ,.checkbits0_out        (crc_bits0_out[35:0])
 ,.checkbits1_out        (crc_bits1_out[35:0])

);

assign crc_bits = crc_bits0_q ^ crc_bits1_q;


assign crc_bits0_din[35:0] =                                                                    reset ? 36'h000000000:
                             master_valid & valid_crc_din & (flit_cycle_odd_q | ~x4_not_x8_rx_mode_q) ? crc_bits0_out[35:0]:
                                                                                                        crc_bits0_q[35:0];
assign crc_bits1_din[35:0] =                                                                    reset ? 36'h000000000:
                             master_valid & valid_crc_din & (flit_cycle_odd_q | ~x4_not_x8_rx_mode_q) ? crc_bits1_out[35:0]:
                                                                                                        crc_bits1_q[35:0];



assign is_crc_data_flit   = ~x4_not_x8_rx_mode_q ?                     (run_length_din[3:0] != 4'b0000):
                                                   flit_cycle_odd_q  & (run_length_q[3:0]   != 4'b0000);                                           


assign is_crc_data_flit_din = master_valid ? is_crc_data_flit:
                                             is_crc_data_flit_q;



assign crc_init_din = (master_valid & ~is_crc_data_flit & ~(is_crc_data_flit_q & x4_not_x8_rx_mode_q)) | reset | ~link_is_tl_d3_q;


assign crc_nonzero = (|crc_bits) & linkup_q;

assign crc_error          =  ~x4_not_x8_rx_mode_q ?                      master_valid_q & ~is_crc_data_flit_q & crc_nonzero:
                                                    ~flit_cycle_odd_q & (master_valid_q & ~is_crc_data_flit_q & crc_nonzero);

assign replay_pending     = ~is_replay_flit & (crc_error | replay_pending_q) & ~reset;

assign replay_ip          = is_replay_flit | (replay_ip_q & (rx_curr_ptr_q[6:0] != rx_ack_ptr_q[6:0]));



assign replay_pending_din = replay_pending;
assign replay_ip_din      = replay_ip;

assign flit_vld_din       = (is_data_flit | is_ctrl_flit) & ~(replay_pending | replay_ip) & linkup_q ;
assign crc_error_cntr_din[15:0] = reset     ? 16'h0000 :
                                  crc_error ? crc_error_cntr_q[15:0] + 16'h0001 :
                                              crc_error_cntr_q[15:0];


assign tlx_crc_error_din  = is_replay_flit | crc_error;
assign tx_crc_error_din   = crc_error | (replay_pending_q & (&(replay_deskew_cntr_q[7:0])));



assign valid_out        = flit_vld_q;
assign tlx_crc_error    = tlx_crc_error_q;
assign tx_crc_error     = tx_crc_error_q;



assign nack_din            = (is_replay_flit & flit_q[468]);
assign tx_ack_ptr_vld_din  = is_replay_flit;
assign tx_ack_ptr_din[6:0] = {7{is_replay_flit}} & flit_q[422:416];

assign tx_ack_rtn_din[4:0] = ((is_ctrl_flit | is_dl2dl_flit) & ~replay_pending_q & train_ts67)  ? flit_q[475:471]:
                                                                                                  5'b0;



assign ack_cnt_din[3:0] = (~reset & is_data_flit)                  ? (ack_cnt_q[3:0] + 4'b0001) :
                          (x4_not_x8_rx_mode_q & flit_cycle_odd_q) ? ack_cnt_q[3:0]:
                          (~reset & ~master_valid_q)               ? ack_cnt_q[3:0] :
                                                                     4'b0;

assign num_good_flits_rcvd[3:0] = (~reset & is_ctrl_flit & linkup_q) ? (ack_cnt_q[3:0] + 4'b0001) :
                                                                        4'b0;

assign tx_ack_inc_din[3:0] = ( ~(replay_pending | replay_ip) & master_valid_q ) ? num_good_flits_rcvd[3:0] :
                                                                                4'b0;


assign rx_ack_ptr_din[6:0] = {7{~reset}} & (rx_ack_ptr_q[6:0] + {3'b0, tx_ack_inc_din[3:0]});
assign rx_curr_ptr_din[6:0] = reset            ? 7'b0 :
                              (is_replay_flit) ? flit_q[438:432] :
                                                 (rx_curr_ptr_q[6:0] + {3'b0, num_good_flits_rcvd[3:0]});


assign nack_out   =  master_valid_dly_q ? nack_q:
                                          nack_dly_q;

assign nack_dly_din = master_valid_dly_q ? nack_q:
                                           nack_dly_q; 

assign ack_ptr_vld_out          = tx_ack_ptr_vld_q & train_ts67;
assign ack_ptr_out[6:0]         = tx_ack_ptr_q[6:0];
assign ack_rtn_out[4:0]         = tx_ack_rtn_q[4:0];
assign ack_inc_out[3:0]         = tx_ack_inc_q[3:0];





assign deskew_reset_din = |(deskew_overflow[7:0] & ~disabled_lanes_q[7:0]) | reset;

assign deskew_all_valid_l0_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l1_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l2_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l3_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l4_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l5_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l6_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_l7_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;
assign deskew_all_valid_din = &(deskew_valid[7:0] | disabled_lanes_q[7:0]) & ~deskew_reset_din;

assign are_deskew = good_evens ? deskew_all_valid_d1_q & (ln0_data_d1_q[63:24] == 40'h4B1E1E1E1E):
                                 deskew_all_valid_d1_q & (ln1_data_d1_q[63:24] == 40'h4B1E1E1E1E);

assign matching_deskew = good_evens ? are_deskew & (ln0_data_d1_q[23:5] == prev_deskew_q[23:5]):
                                      are_deskew & (ln1_data_d1_q[23:5] == prev_deskew_q[23:5]);

assign prev_deskew_din[23:5] = (good_evens & are_deskew) ? ln0_data_d1_q[23:5] :
                                              are_deskew ? ln1_data_d1_q[23:5] :
                                                           (prev_deskew_q[23:5] & {19{~reset}});

assign replay_deskew_cntr_din[7:0] = (reset | (replay_pending_din & ~replay_pending_q))       ? 8'b0 :
                                     ((training_enable & matching_deskew) | (replay_pending)) ? (replay_deskew_cntr_q[7:0] + 8'b00000001) :
                                                                                                 replay_deskew_cntr_q[7:0];


assign deskew_done_din = ((deskew_all_valid_q & (&(replay_deskew_cntr_q[2:0]))) | deskew_done_q) & ~reset;
                



assign lane_swap_din = ~reset & ( lane_swap_q | (matching_deskew &
                                ((good_evens & (ln0_data_d1_q[4:0] == 5'b00111)  & (ln2_data_d1_q[4:0] == 5'b00101)) | (good_odds & (ln1_data_d1_q[4:0] == 5'b00110) & (ln3_data_d1_q[4:0] == 5'b00100))) ));

assign linkup_din     = ~(reset | (retrain_q & retrain_d1_q & retrain_d2_q)) & (linkup_q | ((&(data_flit[7:0] | disabled_lanes_q[7:0])) & train_ts67));
assign tl_linkup_din  = ~reset & (tl_linkup_q | ( (&(data_flit[7:0] | disabled_lanes_q[7:0]))  & train_ts67) );

assign link_is_tl_din    = ~reset & ~train_ts2 & (link_is_tl_q | (train_ts67 & ~start_cycle));
assign link_is_tl_d1_din = reset ? 1'b0 : deskew_all_valid_q ? link_is_tl_q    : link_is_tl_d1_q;
assign link_is_tl_d2_din = reset ? 1'b0 : deskew_all_valid_q ? link_is_tl_d1_q : link_is_tl_d2_q;
assign link_is_tl_d3_din = reset ? 1'b0 : deskew_all_valid_q ? link_is_tl_d2_q : link_is_tl_d3_q;



assign sum_ctl_headers[3:0] = {3'b000, (ctl_header[7] & ~disabled_lanes_q[7])} +
                              {3'b000, (ctl_header[6] & ~disabled_lanes_q[6])} +
                              {3'b000, (ctl_header[5] & ~disabled_lanes_q[5])} +
                              {3'b000, (ctl_header[4] & ~disabled_lanes_q[4])} +
                              {3'b000, (ctl_header[3] & ~disabled_lanes_q[3])} +
                              {3'b000, (ctl_header[2] & ~disabled_lanes_q[2])} +
                              {3'b000, (ctl_header[1] & ~disabled_lanes_q[1])} +
                              {3'b000, (ctl_header[0] & ~disabled_lanes_q[0])};

assign retrain_din    = (link_is_tl_q     & (|sum_ctl_headers[3:1]) & ~training_enable) | (train_ts67 & ~link_is_tl_q & (|(ctl_header[7:0] & rx_TS1[7:0] & ~disabled_lanes_q[7:0])));
assign retrain_d1_din = retrain_q;   
assign retrain_d2_din = retrain_d1_q;
assign retrain_d3_din = retrain_d2_q;

assign rx_tx_retrain = retrain_q & retrain_d1_q & retrain_d2_q;


assign disabled_lanes_din = disabled_lanes;

assign good_odds                   = ~(disabled_lanes_q[7] | disabled_lanes_q[5] | disabled_lanes_q[3] | disabled_lanes_q[1]); 
assign good_evens                  = ~(disabled_lanes_q[6] | disabled_lanes_q[4] | disabled_lanes_q[2] | disabled_lanes_q[0]); 

assign good_odds_only_din          = reset ? 1'b0 :
                                             good_odds & ~good_evens;

assign good_evens_only_din         = reset ? 1'b0 :
                                             good_evens & ~good_odds;

assign x4_not_x8_rx_mode_din       = good_odds_only_q || good_evens_only_q;


assign deskew_all_valid_l0 = deskew_all_valid_l0_q;
assign deskew_all_valid_l1 = deskew_all_valid_l1_q;
assign deskew_all_valid_l2 = deskew_all_valid_l2_q;
assign deskew_all_valid_l3 = deskew_all_valid_l3_q;
assign deskew_all_valid_l4 = deskew_all_valid_l4_q;
assign deskew_all_valid_l5 = deskew_all_valid_l5_q;
assign deskew_all_valid_l6 = deskew_all_valid_l6_q;
assign deskew_all_valid_l7 = deskew_all_valid_l7_q;
assign deskew_reset        = deskew_reset_q;
assign deskew_done_out     = deskew_done_q;
assign lane_swap_out       = lane_swap_q;
assign linkup_out          = linkup_q;
assign tl_linkup_out       = tl_linkup_q;





assign master_valid         = deskew_all_valid_q & link_is_tl_d3_q & ~reset;
assign master_valid_din     = master_valid;
assign master_valid_dly_din = master_valid_q;

assign is_data_flit   = ~x4_not_x8_rx_mode_q ?                     master_valid_q & linkup_q & (run_length_q[3:0] != 4'b0000):
                                               ~flit_cycle_odd_q & master_valid_q & linkup_q & (run_length_q[3:0] != 4'b0000);                                           

assign is_ctrl_flit   = ~x4_not_x8_rx_mode_q ?                     master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] <= 4'b1000):
                                               ~flit_cycle_odd_q & master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] <= 4'b1000);  

assign is_dl2dl_flit  = ~x4_not_x8_rx_mode_q ?                     master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] > 4'b1000):
                                               ~flit_cycle_odd_q & master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] > 4'b1000);   

assign is_replay_flit = ~x4_not_x8_rx_mode_q ?                     master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] == 4'hA):
                                               ~flit_cycle_odd_q & master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] == 4'hA);  

assign is_idle_flit   = ~x4_not_x8_rx_mode_q ?                     master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] == 4'hF):
                                               ~flit_cycle_odd_q & master_valid_q & linkup_q & ~crc_error & (run_length_q[3:0] == 4'b0000) & (flit_q[451:448] == 4'hF);  


assign run_length_din[3:0] = ~train_ts67                                  ? 4'b0000:
                             is_data_flit                                 ? (run_length_q[3:0] - 4'b0001):
                             is_ctrl_flit & ~flit_q[467]                  ? flit_q[451:448]:
                             is_replay_flit & ~flit_q[467]                ? flit_q[455:452]:
                             is_idle_flit & ~(flit_q[455:452] == 4'b0000) ? flit_q[455:452]:
                             ~master_valid_q & ~reset                     ? run_length_q[3:0]:
                             flit_cycle_odd_q                             ? run_length_q[3:0]:
                                                                            4'b0000;




assign dlx_link_error_din[7:0] = is_replay_flit ? flit_q[463:456]:
                                                  dlx_link_error_q[7:0];

assign dlx_config_din[31:0] = is_replay_flit ? flit_q[415:384]:
                                               dlx_config_q[31:0];

assign dlx_config_info[31:0] = dlx_config_q[31:0];

always @(posedge rx_clk_in) begin
flit_q[511:0]              <= flit_din[511:0];
flit_to_tl_q[511:0]        <= flit_to_tl_din[511:0];
flit_cycle_odd_q           <= flit_cycle_odd_din;
crc_bits0_q[35:0]          <= crc_bits0_din[35:0];
crc_bits1_q[35:0]          <= crc_bits1_din[35:0];
crc_init_q                 <= crc_init_din;
replay_pending_q           <= replay_pending_din;
replay_ip_q                <= replay_ip_din;
flit_vld_q                 <= flit_vld_din;
tlx_crc_error_q            <= tlx_crc_error_din;
tx_crc_error_q             <= tx_crc_error_din;
deskew_reset_q             <= deskew_reset_din;
deskew_all_valid_d1_q      <= deskew_all_valid_d1_din;
ln0_data_d1_q[63:0]        <= ln0_data_d1_din[63:0];
ln1_data_d1_q[63:0]        <= ln1_data_d1_din[63:0];
ln2_data_d1_q[4:0]         <= ln2_data_d1_din[4:0];
ln3_data_d1_q[4:0]         <= ln3_data_d1_din[4:0];
deskew_all_valid_q         <= deskew_all_valid_din;
deskew_all_valid_l0_q      <= deskew_all_valid_l0_din;
deskew_all_valid_l1_q      <= deskew_all_valid_l1_din;
deskew_all_valid_l2_q      <= deskew_all_valid_l2_din;
deskew_all_valid_l3_q      <= deskew_all_valid_l3_din;
deskew_all_valid_l4_q      <= deskew_all_valid_l4_din;
deskew_all_valid_l5_q      <= deskew_all_valid_l5_din;
deskew_all_valid_l6_q      <= deskew_all_valid_l6_din;
deskew_all_valid_l7_q      <= deskew_all_valid_l7_din;
prev_deskew_q[23:5]        <= prev_deskew_din[23:5];
replay_deskew_cntr_q[7:0]  <= replay_deskew_cntr_din[7:0];
deskew_done_q              <= deskew_done_din;
lane_swap_q                <= lane_swap_din;
linkup_q                   <= linkup_din;
tl_linkup_q                <= tl_linkup_din;
link_is_tl_q               <= link_is_tl_din;
link_is_tl_d1_q            <= link_is_tl_d1_din;
link_is_tl_d2_q            <= link_is_tl_d2_din;
link_is_tl_d3_q            <= link_is_tl_d3_din;
retrain_q                  <= retrain_din;
retrain_d1_q               <= retrain_d1_din;
retrain_d2_q               <= retrain_d2_din;
retrain_d3_q               <= retrain_d3_din;
disabled_lanes_q           <= disabled_lanes_din;
good_evens_only_q          <= good_evens_only_din;
good_odds_only_q           <= good_odds_only_din;
x4_not_x8_rx_mode_q        <= x4_not_x8_rx_mode_din;
nack_q                     <= nack_din;
tx_ack_ptr_vld_q           <= tx_ack_ptr_vld_din;
tx_ack_ptr_q[6:0]          <= tx_ack_ptr_din[6:0];
tx_ack_rtn_q[4:0]          <= tx_ack_rtn_din[4:0];
ack_cnt_q[3:0]             <= ack_cnt_din[3:0];
tx_ack_inc_q[3:0]          <= tx_ack_inc_din[3:0];
rx_ack_ptr_q[6:0]          <= rx_ack_ptr_din[6:0];
rx_curr_ptr_q[6:0]         <= rx_curr_ptr_din[6:0];
run_length_q[3:0]          <= run_length_din[3:0];
dlx_config_q[31:0]         <= dlx_config_din[31:0];
dlx_link_error_q[7:0]      <= dlx_link_error_din[7:0];
is_crc_data_flit_q         <= is_crc_data_flit_din;
master_valid_q             <= master_valid_din;
master_valid_dly_q         <= master_valid_dly_din;

nack_dly_q                 <= nack_dly_din;
crc_error_cntr_q[15:0]     <= crc_error_cntr_din[15:0];
end

endmodule