data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v:164: Bit extraction of var[5:0] requires 3 bit index, not 2 bits.\n                                                                                     : ... In instance Z80Reg.WSelectR\n    if(rstatus[{1\'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3\'b010};   \n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v:167: Bit extraction of var[5:0] requires 3 bit index, not 2 bits.\n                                                                                     : ... In instance Z80Reg.WSelectR\n    case({rstatus[5:4], rstatus[{1\'b1, rstatus[1]}]})\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/169848838/prj/rtl/NextZ80/NextZ80Reg.v:106: Operator ADD expects 16 bits on the RHS, but RHS\'s LOGNOT generates 1 bits.\n                                                                                     : ... In instance Z80Reg\n wire [15:0]ADDR1 = ADDR + !ALU16OP[2];  \n                         ^\n%Error: Exiting due to 3 warning(s)\n'
module Z80Reg(
	input wire [7:0]rstatus,
	input wire M1,
	input wire [5:0]WE,
	input wire CLK,
	input wire [15:0]ALU8OUT,
	input wire [7:0]DI,
	output reg [7:0]DO,
	input wire [15:0]ADDR,
	input wire [7:0]CONST,
	output reg [7:0]ALU80,
	output reg [7:0]ALU81,
	output reg [15:0]ALU160,
	output wire[7:0]ALU161,
	input wire [7:0]ALU8FLAGS,			
	output wire [7:0]FLAGS,
	
	input wire [1:0]DO_SEL,
	input wire ALU160_sel,
	input wire [3:0]REG_WSEL,
	input wire [3:0]REG_RSEL,
	input wire DINW_SEL,
	input wire XMASK,
	input wire [2:0]ALU16OP,
	input wire WAIT
	);
	

	reg [15:0]pc=0;
	reg [15:0]sp;
	reg [7:0]r;
	reg [15:0]flg = 0;
	reg [7:0]th;


	wire [15:0]rdor;
	wire [15:0]rdow;
	wire [3:0]SELW;
	wire [3:0]SELR;
	reg  [15:0]DIN;
	reg [15:0]mux_rdor;
	


   RAM16X8D_regs regs_lo (
      .DPO(rdor[7:0]),
      .SPO(rdow[7:0]),
      .A(SELW),
      .D(DIN[7:0]),
      .DPRA(SELR),
      .WCLK(CLK),
      .WE(WE[0] & !WAIT)
   );

   RAM16X8D_regs regs_hi (
      .DPO(rdor[15:8]),
      .SPO(rdow[15:8]),
      .A(SELW),
      .D(DIN[15:8]),
      .DPRA(SELR),
      .WCLK(CLK),
      .WE(WE[1] & !WAIT)
   );

	wire [15:0]ADDR1 = ADDR + !ALU16OP[2];
	wire [7:0]flgmux = {ALU8FLAGS[7:3], SELR[3:0] == 4'b0100 ? rstatus[7] : ALU8FLAGS[2], ALU8FLAGS[1:0]};
	always @(posedge CLK)
		if(!WAIT) begin
			if(WE[2]) th <= DI;
			if(WE[3]) sp <= ADDR1;
			if(WE[4]) pc <= ADDR1;
			if({REG_WSEL, WE[0]} == 5'b10011) r <= ALU8OUT[7:0]; 
			else if(M1) r[6:0] <= r[6:0] + 1;
			if(WE[5])
				if(rstatus[0]) flg[15:8] <= flgmux;
				else flg[7:0] <= flgmux;
		end
	
	assign ALU161 = th;
	assign FLAGS = rstatus[0] ? flg[15:8] : flg[7:0];
	
	always @* begin
		DIN = DINW_SEL ? {DI, DI} : ALU8OUT;
		ALU80 = REG_WSEL[0] ? rdow[7:0] : rdow[15:8];
		ALU81 = REG_RSEL[0] ? mux_rdor[7:0] : mux_rdor[15:8];
		ALU160 = ALU160_sel ? pc : mux_rdor;
	
		case({REG_WSEL[3], DO_SEL})
			0:	DO = ALU80;
			1:	DO = th;
			2: DO = FLAGS;
			3: DO = ALU8OUT[7:0];
			4: DO = pc[15:8];
			5: DO = pc[7:0];
			6:	DO = sp[15:8];
			7: DO = sp[7:0];
		endcase
		case({ALU16OP == 4, REG_RSEL[3:0]})
			5'b01001, 5'b11001:								mux_rdor = {rdor[15:8], r};
			5'b01010, 5'b01011: 								mux_rdor = sp;
			5'b01100, 5'b01101, 5'b11100, 5'b11101:	mux_rdor = {8'b0, CONST};
			default:		mux_rdor = rdor;
		endcase 
	end
	
	RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus({rstatus[5], rstatus[4] & XMASK, rstatus[3:0]}));
	RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus[5:0]));

endmodule
module Z80Reg(
	input wire [7:0]rstatus,
	input wire M1,
	input wire [5:0]WE,
	input wire CLK,
	input wire [15:0]ALU8OUT,
	input wire [7:0]DI,
	output reg [7:0]DO,
	input wire [15:0]ADDR,
	input wire [7:0]CONST,
	output reg [7:0]ALU80,
	output reg [7:0]ALU81,
	output reg [15:0]ALU160,
	output wire[7:0]ALU161,
	input wire [7:0]ALU8FLAGS,			
	output wire [7:0]FLAGS,
	
	input wire [1:0]DO_SEL,
	input wire ALU160_sel,
	input wire [3:0]REG_WSEL,
	input wire [3:0]REG_RSEL,
	input wire DINW_SEL,
	input wire XMASK,
	input wire [2:0]ALU16OP,
	input wire WAIT
	);

	

	reg [15:0]pc=0;
	reg [15:0]sp;
	reg [7:0]r;
	reg [15:0]flg = 0;
	reg [7:0]th;


	wire [15:0]rdor;
	wire [15:0]rdow;
	wire [3:0]SELW;
	wire [3:0]SELR;
	reg  [15:0]DIN;
	reg [15:0]mux_rdor;
	


   RAM16X8D_regs regs_lo (
      .DPO(rdor[7:0]),
      .SPO(rdow[7:0]),
      .A(SELW),
      .D(DIN[7:0]),
      .DPRA(SELR),
      .WCLK(CLK),
      .WE(WE[0] & !WAIT)
   );

   RAM16X8D_regs regs_hi (
      .DPO(rdor[15:8]),
      .SPO(rdow[15:8]),
      .A(SELW),
      .D(DIN[15:8]),
      .DPRA(SELR),
      .WCLK(CLK),
      .WE(WE[1] & !WAIT)
   );

	wire [15:0]ADDR1 = ADDR + !ALU16OP[2];
	wire [7:0]flgmux = {ALU8FLAGS[7:3], SELR[3:0] == 4'b0100 ? rstatus[7] : ALU8FLAGS[2], ALU8FLAGS[1:0]};
	always @(posedge CLK)
		if(!WAIT) begin
			if(WE[2]) th <= DI;
			if(WE[3]) sp <= ADDR1;
			if(WE[4]) pc <= ADDR1;
			if({REG_WSEL, WE[0]} == 5'b10011) r <= ALU8OUT[7:0]; 
			else if(M1) r[6:0] <= r[6:0] + 1;
			if(WE[5])
				if(rstatus[0]) flg[15:8] <= flgmux;
				else flg[7:0] <= flgmux;
		end
	
	assign ALU161 = th;
	assign FLAGS = rstatus[0] ? flg[15:8] : flg[7:0];
	
	always @* begin
		DIN = DINW_SEL ? {DI, DI} : ALU8OUT;
		ALU80 = REG_WSEL[0] ? rdow[7:0] : rdow[15:8];
		ALU81 = REG_RSEL[0] ? mux_rdor[7:0] : mux_rdor[15:8];
		ALU160 = ALU160_sel ? pc : mux_rdor;
	
		case({REG_WSEL[3], DO_SEL})
			0:	DO = ALU80;
			1:	DO = th;
			2: DO = FLAGS;
			3: DO = ALU8OUT[7:0];
			4: DO = pc[15:8];
			5: DO = pc[7:0];
			6:	DO = sp[15:8];
			7: DO = sp[7:0];
		endcase
		case({ALU16OP == 4, REG_RSEL[3:0]})
			5'b01001, 5'b11001:								mux_rdor = {rdor[15:8], r};
			5'b01010, 5'b01011: 								mux_rdor = sp;
			5'b01100, 5'b01101, 5'b11100, 5'b11101:	mux_rdor = {8'b0, CONST};
			default:		mux_rdor = rdor;
		endcase 
	end
	
	RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus({rstatus[5], rstatus[4] & XMASK, rstatus[3:0]}));
	RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus[5:0]));

endmodule