data/full_repos/permissive/1840016/lab1/flipflop.v
data/verilator_xmls/b2d715db-6755-4a05-87ee-2a4b4702743a.xml
module flipflop (clk, d_in, d_out);


	
	input clk;
	input d_in;
	output d_out;
	reg d_out;
	
	always @(posedge clk)
	begin
		d_out <= d_in;
	end

endmodule
module flipflop (clk, d_in, d_out);



	
	input clk;
	input d_in;
	output d_out;
	reg d_out;
	
	always @(posedge clk)
	begin
		d_out <= d_in;
	end

endmodule