data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v
None: at end of input
1: b'%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:28: Cannot find include file: spio_spinnaker_link.h\n`include "spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.v\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.sv\n             spio_spinnaker_link.h\n             spio_spinnaker_link.h.v\n             spio_spinnaker_link.h.sv\n             obj_dir/spio_spinnaker_link.h\n             obj_dir/spio_spinnaker_link.h.v\n             obj_dir/spio_spinnaker_link.h.sv\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:49: Define or directive not defined: \'`PKT_BITS\'\n  output wire [`PKT_BITS - 1:0] PKT_DATA_OUT,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:510: Define or directive not defined: \'`PKT_BITS\'\n  output reg  [`PKT_BITS - 1:0] PKT_DATA_OUT,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:538: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] bad_pkt;        \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:550: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] pkt_buf;    \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:650: Define or directive not defined: \'`PKT_BITS\'\n      pkt_buf <= {flt_data_bin, pkt_buf[`PKT_BITS - 1:4]};\n                                        ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module flit_input_if
(
  input                         CLK_IN,
  input                         RESET_IN,


  output reg                    GCH_ERR_OUT,


  input                   [6:0] SL_DATA_2OF7_IN,
  output reg                    SL_ACK_OUT,


  output reg              [6:0] flt_data_bad,
  output reg              [3:0] flt_data_bin,
  output reg                    flt_dat,
  output reg                    flt_bad,
  output reg                    flt_eop,
  input                         flt_cts
);




  localparam STATE_BITS = 2;
  localparam STRT_ST    = 0;
  localparam IDLE_ST    = STRT_ST + 1;
  localparam RECV_ST    = IDLE_ST + 1;
  localparam EOPW_ST    = RECV_ST + 1;





  reg send_ack;

  reg dat_flit;
  reg err_flit;
  reg eop_flit;

  reg new_flit;
  reg bad_flit;
  reg err_seen;

  reg [3:0] new_data;
 
  reg [6:0] old_data_2of7;

  reg [6:0] rtz_data;

  reg [STATE_BITS - 1:0] state;





  function data_2of7 ;
    input [6:0] data;

    case (data)
      7'b0010001: data_2of7 = 1;
      7'b0010010: data_2of7 = 1;
      7'b0010100: data_2of7 = 1;
      7'b0011000: data_2of7 = 1;
      7'b0100001: data_2of7 = 1;
      7'b0100010: data_2of7 = 1;
      7'b0100100: data_2of7 = 1;
      7'b0101000: data_2of7 = 1;
      7'b1000001: data_2of7 = 1;
      7'b1000010: data_2of7 = 1;
      7'b1000100: data_2of7 = 1;
      7'b1001000: data_2of7 = 1;
      7'b0000011: data_2of7 = 1;
      7'b0000110: data_2of7 = 1;
      7'b0001100: data_2of7 = 1;
      7'b0001001: data_2of7 = 1;
      default:    data_2of7 = 0;
    endcase
  endfunction





  function eop_2of7 ;
    input [6:0] data;

    case (data)
      7'b1100000: eop_2of7 = 1;
      default:    eop_2of7 = 0;
    endcase
  endfunction





  function error_2of7 ;
    input [6:0] data;

    case (data)
      7'b0010001: error_2of7 = 0;
      7'b0010010: error_2of7 = 0;
      7'b0010100: error_2of7 = 0;
      7'b0011000: error_2of7 = 0;
      7'b0100001: error_2of7 = 0;
      7'b0100010: error_2of7 = 0;
      7'b0100100: error_2of7 = 0;
      7'b0101000: error_2of7 = 0;
      7'b1000001: error_2of7 = 0;
      7'b1000010: error_2of7 = 0;
      7'b1000100: error_2of7 = 0;
      7'b1001000: error_2of7 = 0;
      7'b0000011: error_2of7 = 0;
      7'b0000110: error_2of7 = 0;
      7'b0001100: error_2of7 = 0;
      7'b0001001: error_2of7 = 0;
      7'b1100000: error_2of7 = 0;
      0, 1, 2, 4,
      8, 16, 32,
      64:         error_2of7 = 0;
      default:    error_2of7 = 1;
    endcase
  endfunction





  function [3:0] decode_2of7 ;
    input [6:0] data;

    case (data)
      7'b0010001: decode_2of7 = 0;
      7'b0010010: decode_2of7 = 1;
      7'b0010100: decode_2of7 = 2;
      7'b0011000: decode_2of7 = 3;
      7'b0100001: decode_2of7 = 4;
      7'b0100010: decode_2of7 = 5;
      7'b0100100: decode_2of7 = 6;
      7'b0101000: decode_2of7 = 7;
      7'b1000001: decode_2of7 = 8;
      7'b1000010: decode_2of7 = 9;
      7'b1000100: decode_2of7 = 10;
      7'b1001000: decode_2of7 = 11;
      7'b0000011: decode_2of7 = 12;
      7'b0000110: decode_2of7 = 13;
      7'b0001100: decode_2of7 = 14;
      7'b0001001: decode_2of7 = 15;
      default:    decode_2of7 = 4'hx;
    endcase
  endfunction





  always @(*)
    rtz_data = SL_DATA_2OF7_IN ^ old_data_2of7;





  always @(*)
    dat_flit = data_2of7 (rtz_data);





  always @(*)
    eop_flit = eop_2of7 (rtz_data);





  always @(*)
    err_flit = error_2of7 (rtz_data);





  always @(*)
    bad_flit = err_flit && err_seen;





  always @(*)
    new_flit = dat_flit || eop_flit || bad_flit;





  always @(*)
    new_data = decode_2of7 (rtz_data);





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      SL_ACK_OUT <= 1'b0;
    else
      if (send_ack)
        SL_ACK_OUT <= ~SL_ACK_OUT;





  always @(*)
    case (state)
      STRT_ST:   send_ack = 1'b1;

      IDLE_ST,
      RECV_ST: if (new_flit && flt_cts)
                 send_ack = 1'b1;
               else
                 send_ack = 1'b0;

      EOPW_ST:   send_ack = 1'b0;
    endcase 





  always @(posedge CLK_IN)
    case (state)
      STRT_ST:
          old_data_2of7 <= SL_DATA_2OF7_IN;

      IDLE_ST,
      RECV_ST:
        if (new_flit && flt_cts)
          old_data_2of7 <= SL_DATA_2OF7_IN;
    endcase 





  always @(posedge CLK_IN)
    flt_data_bad <= rtz_data;





  always @(posedge CLK_IN)
    case (state)
      IDLE_ST,
      RECV_ST:  if (dat_flit && flt_cts)
                  flt_data_bin <= new_data;
    endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_dat <= 1'b0;
    else
      case (state)
        IDLE_ST,
        RECV_ST:  if (dat_flit && flt_cts)
                    flt_dat <= 1'b1;
                  else
                    flt_dat <= 1'b0;

        default:    flt_dat <= 1'b0;
      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_bad <= 1'b0;
    else
      case (state)
        IDLE_ST,
        RECV_ST:  if (bad_flit && flt_cts)
                    flt_bad <= 1'b1;
                  else
                    flt_bad <= 1'b0;

        default:    flt_bad <= 1'b0;
      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_eop <= 1'b0;
    else
      case (state)
        IDLE_ST,
        RECV_ST:  if (eop_flit && flt_cts)
                    flt_eop <= 1'b1;
                  else
                    flt_eop <= 1'b0;

        default:    flt_eop <= 1'b0;
      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      err_seen <= 1'b0;
    else
      if (err_flit && !err_seen)
        err_seen <= 1'b1;
      else
        err_seen <= 1'b0;





  reg gch_err_ext;
  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      gch_err_ext <= 1'b0;
    else
      gch_err_ext <= GCH_ERR_OUT;

  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      GCH_ERR_OUT <= 1'b0;
    else
      if (err_seen)
        GCH_ERR_OUT <= 1'b1;
      else if (gch_err_ext)
        GCH_ERR_OUT <= 1'b0;






  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      state <= STRT_ST;
    else
      case (state)
        IDLE_ST:
          casex ({flt_cts, dat_flit, eop_flit, bad_flit})
            4'b11xx,
            4'b1xx1: state <= RECV_ST;

            4'b1x1x: state <= EOPW_ST;
          endcase

        RECV_ST: if (eop_flit)
                   state <= EOPW_ST;

        default:   state <= IDLE_ST;
      endcase 
endmodule
module flit_input_if
(
  input                         CLK_IN,
  input                         RESET_IN,


  output reg                    GCH_ERR_OUT,


  input                   [6:0] SL_DATA_2OF7_IN,
  output reg                    SL_ACK_OUT,


  output reg              [6:0] flt_data_bad,
  output reg              [3:0] flt_data_bin,
  output reg                    flt_dat,
  output reg                    flt_bad,
  output reg                    flt_eop,
  input                         flt_cts
);





  localparam STATE_BITS = 2;
  localparam STRT_ST    = 0;
  localparam IDLE_ST    = STRT_ST + 1;
  localparam RECV_ST    = IDLE_ST + 1;
  localparam EOPW_ST    = RECV_ST + 1;





  reg send_ack;

  reg dat_flit;
  reg err_flit;
  reg eop_flit;

  reg new_flit;
  reg bad_flit;
  reg err_seen;

  reg [3:0] new_data;
 
  reg [6:0] old_data_2of7;

  reg [6:0] rtz_data;

  reg [STATE_BITS - 1:0] state;





  function data_2of7 ;
    input [6:0] data;

    case (data)
      7'b0010001: data_2of7 = 1;
      7'b0010010: data_2of7 = 1;
      7'b0010100: data_2of7 = 1;
      7'b0011000: data_2of7 = 1;
      7'b0100001: data_2of7 = 1;
      7'b0100010: data_2of7 = 1;
      7'b0100100: data_2of7 = 1;
      7'b0101000: data_2of7 = 1;
      7'b1000001: data_2of7 = 1;
      7'b1000010: data_2of7 = 1;
      7'b1000100: data_2of7 = 1;
      7'b1001000: data_2of7 = 1;
      7'b0000011: data_2of7 = 1;
      7'b0000110: data_2of7 = 1;
      7'b0001100: data_2of7 = 1;
      7'b0001001: data_2of7 = 1;
      default:    data_2of7 = 0;
    endcase
  endfunction





  function eop_2of7 ;
    input [6:0] data;

    case (data)
      7'b1100000: eop_2of7 = 1;
      default:    eop_2of7 = 0;
    endcase
  endfunction





  function error_2of7 ;
    input [6:0] data;

    case (data)
      7'b0010001: error_2of7 = 0;
      7'b0010010: error_2of7 = 0;
      7'b0010100: error_2of7 = 0;
      7'b0011000: error_2of7 = 0;
      7'b0100001: error_2of7 = 0;
      7'b0100010: error_2of7 = 0;
      7'b0100100: error_2of7 = 0;
      7'b0101000: error_2of7 = 0;
      7'b1000001: error_2of7 = 0;
      7'b1000010: error_2of7 = 0;
      7'b1000100: error_2of7 = 0;
      7'b1001000: error_2of7 = 0;
      7'b0000011: error_2of7 = 0;
      7'b0000110: error_2of7 = 0;
      7'b0001100: error_2of7 = 0;
      7'b0001001: error_2of7 = 0;
      7'b1100000: error_2of7 = 0;
      0, 1, 2, 4,
      8, 16, 32,
      64:         error_2of7 = 0;
      default:    error_2of7 = 1;
    endcase
  endfunction





  function [3:0] decode_2of7 ;
    input [6:0] data;

    case (data)
      7'b0010001: decode_2of7 = 0;
      7'b0010010: decode_2of7 = 1;
      7'b0010100: decode_2of7 = 2;
      7'b0011000: decode_2of7 = 3;
      7'b0100001: decode_2of7 = 4;
      7'b0100010: decode_2of7 = 5;
      7'b0100100: decode_2of7 = 6;
      7'b0101000: decode_2of7 = 7;
      7'b1000001: decode_2of7 = 8;
      7'b1000010: decode_2of7 = 9;
      7'b1000100: decode_2of7 = 10;
      7'b1001000: decode_2of7 = 11;
      7'b0000011: decode_2of7 = 12;
      7'b0000110: decode_2of7 = 13;
      7'b0001100: decode_2of7 = 14;
      7'b0001001: decode_2of7 = 15;
      default:    decode_2of7 = 4'hx;
    endcase
  endfunction





  always @(*)
    rtz_data = SL_DATA_2OF7_IN ^ old_data_2of7;





  always @(*)
    dat_flit = data_2of7 (rtz_data);





  always @(*)
    eop_flit = eop_2of7 (rtz_data);





  always @(*)
    err_flit = error_2of7 (rtz_data);





  always @(*)
    bad_flit = err_flit && err_seen;





  always @(*)
    new_flit = dat_flit || eop_flit || bad_flit;





  always @(*)
    new_data = decode_2of7 (rtz_data);





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      SL_ACK_OUT <= 1'b0;
    else
      if (send_ack)
        SL_ACK_OUT <= ~SL_ACK_OUT;





  always @(*)
    case (state)
      STRT_ST:   send_ack = 1'b1;

      IDLE_ST,
      RECV_ST: if (new_flit && flt_cts)
                 send_ack = 1'b1;
               else
                 send_ack = 1'b0;

      EOPW_ST:   send_ack = 1'b0;
    endcase 





  always @(posedge CLK_IN)
    case (state)
      STRT_ST:
          old_data_2of7 <= SL_DATA_2OF7_IN;

      IDLE_ST,
      RECV_ST:
        if (new_flit && flt_cts)
          old_data_2of7 <= SL_DATA_2OF7_IN;
    endcase 





  always @(posedge CLK_IN)
    flt_data_bad <= rtz_data;





  always @(posedge CLK_IN)
    case (state)
      IDLE_ST,
      RECV_ST:  if (dat_flit && flt_cts)
                  flt_data_bin <= new_data;
    endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_dat <= 1'b0;
    else
      case (state)
        IDLE_ST,
        RECV_ST:  if (dat_flit && flt_cts)
                    flt_dat <= 1'b1;
                  else
                    flt_dat <= 1'b0;

        default:    flt_dat <= 1'b0;
      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_bad <= 1'b0;
    else
      case (state)
        IDLE_ST,
        RECV_ST:  if (bad_flit && flt_cts)
                    flt_bad <= 1'b1;
                  else
                    flt_bad <= 1'b0;

        default:    flt_bad <= 1'b0;
      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_eop <= 1'b0;
    else
      case (state)
        IDLE_ST,
        RECV_ST:  if (eop_flit && flt_cts)
                    flt_eop <= 1'b1;
                  else
                    flt_eop <= 1'b0;

        default:    flt_eop <= 1'b0;
      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      err_seen <= 1'b0;
    else
      if (err_flit && !err_seen)
        err_seen <= 1'b1;
      else
        err_seen <= 1'b0;





  reg gch_err_ext;
  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      gch_err_ext <= 1'b0;
    else
      gch_err_ext <= GCH_ERR_OUT;

  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      GCH_ERR_OUT <= 1'b0;
    else
      if (err_seen)
        GCH_ERR_OUT <= 1'b1;
      else if (gch_err_ext)
        GCH_ERR_OUT <= 1'b0;






  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      state <= STRT_ST;
    else
      case (state)
        IDLE_ST:
          casex ({flt_cts, dat_flit, eop_flit, bad_flit})
            4'b11xx,
            4'b1xx1: state <= RECV_ST;

            4'b1x1x: state <= EOPW_ST;
          endcase

        RECV_ST: if (eop_flit)
                   state <= EOPW_ST;

        default:   state <= IDLE_ST;
      endcase 
endmodule