data/full_repos/permissive/160437780/Source/irSensor.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160437780/Source/irSensor.v:35: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                         : ... In instance irSensor\n        counter <= 24\'d0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module irSensor(
    input CLK100MHZ,
    input ir_FLAG,
    

    output reg [1:0] iFlag
    );
    
    reg [25:0] counter = 26'd0;
    parameter loop_count = 26'd30000000;   
    parameter timerFlag   = 26'd1000;
    
    reg [25:0] count = 26'd0;       
    parameter maxThreshold = 26'd300000;
    
    always @ (posedge CLK100MHZ) begin
    
    if (counter < timerFlag) begin
        count <= 0;

        counter <= counter + 1;
    end else if (counter < loop_count) begin

        counter <= counter + 1;
        
        if (ir_FLAG) begin
            count <= count + 1;
        end
        

        end else begin
        counter <= 24'd0;

        
        if (count < maxThreshold) begin

            iFlag <= 2'b10;
            end
        else
            iFlag <= 2'b01;
    end
    end
endmodule
module irSensor(
    input CLK100MHZ,
    input ir_FLAG,
    

    output reg [1:0] iFlag
    );

    
    reg [25:0] counter = 26'd0;
    parameter loop_count = 26'd30000000;   
    parameter timerFlag   = 26'd1000;
    
    reg [25:0] count = 26'd0;       
    parameter maxThreshold = 26'd300000;
    
    always @ (posedge CLK100MHZ) begin
    
    if (counter < timerFlag) begin
        count <= 0;

        counter <= counter + 1;
    end else if (counter < loop_count) begin

        counter <= counter + 1;
        
        if (ir_FLAG) begin
            count <= count + 1;
        end
        

        end else begin
        counter <= 24'd0;

        
        if (count < maxThreshold) begin

            iFlag <= 2'b10;
            end
        else
            iFlag <= 2'b01;
    end
    end
endmodule