data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:1: Cannot find include file: top.vh\n`include "top.vh" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105546923/projects/chip8/sim,data/full_repos/permissive/105546923/top.vh\n             data/full_repos/permissive/105546923/projects/chip8/sim,data/full_repos/permissive/105546923/top.vh.v\n             data/full_repos/permissive/105546923/projects/chip8/sim,data/full_repos/permissive/105546923/top.vh.sv\n             top.vh\n             top.vh.v\n             top.vh.sv\n             obj_dir/top.vh\n             obj_dir/top.vh.v\n             obj_dir/top.vh.sv\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:2: Cannot find include file: uart.vh\n`include "uart.vh" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:19: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./build/iverilog/chip8.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:20: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,top_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n # 1000 $finish;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk_i = ~clk_i;\n          ^\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:40: Define or directive not defined: \'`UART_CLK_RX_FREQ\'\n   .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:40: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n   .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n                        ^\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:40: Define or directive not defined: \'`UART_RX_SAMPLE_RATE\'\n   .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)\n                          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:49: Define or directive not defined: \'`UART_CLK_TX_FREQ\'\n   .T(`UART_CLK_TX_FREQ / 2)\n      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/chip8/sim/top_tb.v:49: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n   .T(`UART_CLK_TX_FREQ / 2)\n                        ^\n%Error: Exiting due to 9 error(s), 2 warning(s)\n'
module top_tb;
   
   reg clk_i = 0;
   reg rst_i = 1;
   reg [4:0] rx_i_ctr = 0;
   reg [19:0] rx_tmp = 20'b10100011101010010000;
   reg 	      tmp_rx_bit = 1;
   
   wire [7:0] led_o;
   wire       clk_uart_tx;
   wire       clk_uart_rx, rs232_rx_i;
   
   initial
     begin
	
	$dumpfile("./build/iverilog/chip8.vcd");
	$dumpvars(0,top_tb);
	
	rst_i <= 0;
	
	# 1000 $finish;
	
     end

   always #1 clk_i = ~clk_i;
   
   top tb (
	   .ice_clk_i (clk_i),
	   .rstn_i(rst_i),
	   .rs232_rx_i(rs232_rx_i),
	   .led_o (led_o)
	   );
   
   clks #(
	  .PLL_EN(0),
	  .GBUFF_EN(0),
	  .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
	  )clk_uart_rx_gen(
			   .clk_i (clk_i),
			   .clk_o (clk_uart_rx)
			   );

   clks #(
	  .PLL_EN(0),
	  .GBUFF_EN(0),
	  .T(`UART_CLK_TX_FREQ / 2)
	  )clk_uart_tx_gen(
			   .clk_i (clk_i),
			   .clk_o (clk_uart_tx)
			   );
   
   
   assign rs232_rx_i =tmp_rx_bit;
   
   always @ (posedge (clk_uart_tx))
     begin
	tmp_rx_bit <=  rst_i ? 1'b1 : rx_tmp[rx_i_ctr];
     end
   
   always @ (posedge clk_uart_tx)
     begin
	if (rx_i_ctr == 19 | rst_i)
	  begin
	     rx_i_ctr <= 0;
	  end
	else
	  begin
	     rx_i_ctr <= rx_i_ctr + 1;
	  end
     end   
   
endmodule
module top_tb;

   
   reg clk_i = 0;
   reg rst_i = 1;
   reg [4:0] rx_i_ctr = 0;
   reg [19:0] rx_tmp = 20'b10100011101010010000;
   reg 	      tmp_rx_bit = 1;
   
   wire [7:0] led_o;
   wire       clk_uart_tx;
   wire       clk_uart_rx, rs232_rx_i;
   
   initial
     begin
	
	$dumpfile("./build/iverilog/chip8.vcd");
	$dumpvars(0,top_tb);
	
	rst_i <= 0;
	
	# 1000 $finish;
	
     end

   always #1 clk_i = ~clk_i;
   
   top tb (
	   .ice_clk_i (clk_i),
	   .rstn_i(rst_i),
	   .rs232_rx_i(rs232_rx_i),
	   .led_o (led_o)
	   );
   
   clks #(
	  .PLL_EN(0),
	  .GBUFF_EN(0),
	  .T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
	  )clk_uart_rx_gen(
			   .clk_i (clk_i),
			   .clk_o (clk_uart_rx)
			   );

   clks #(
	  .PLL_EN(0),
	  .GBUFF_EN(0),
	  .T(`UART_CLK_TX_FREQ / 2)
	  )clk_uart_tx_gen(
			   .clk_i (clk_i),
			   .clk_o (clk_uart_tx)
			   );
   
   
   assign rs232_rx_i =tmp_rx_bit;
   
   always @ (posedge (clk_uart_tx))
     begin
	tmp_rx_bit <=  rst_i ? 1'b1 : rx_tmp[rx_i_ctr];
     end
   
   always @ (posedge clk_uart_tx)
     begin
	if (rx_i_ctr == 19 | rst_i)
	  begin
	     rx_i_ctr <= 0;
	  end
	else
	  begin
	     rx_i_ctr <= rx_i_ctr + 1;
	  end
     end   
   
endmodule