data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_BT2.v
data/verilator_xmls/ed19fa30-4101-4e13-963e-1504b5f81c11.xml
module PMOD_BT2 (
    input CLK,
    input RST_N,
    
    input  RTS,
    output reg RXD,
    input  TXD,
    output reg CTS,
    input  STS,
    output wire RST_N_Out,
    
    input [7:0] char_in,
    output reg [7:0] char_out,
    input send,
    output reg sent,
    output reg receive,
    input received
    );
    
    parameter BAUD = 115200;
    parameter CLK_FREQ = 100000000;
    localparam CLKS_PER_BAUD = CLK_FREQ / BAUD;
    
    localparam [1:0] STATE_IDLE = 0;
    localparam [1:0] STATE_START = 1;
    localparam [1:0] STATE_BIT = 2;
    localparam [1:0] STATE_STOP = 3;

    assign RST_N_Out = RST_N;
    
    reg [1:0] send_state;
    reg [2:0] send_bitnum;
    reg [31:0] send_count;
    
    reg [1:0] receive_state;
    reg [2:0] receive_bitnum;
    reg [31:0] receive_count;
    


    reg TXD_buf1;
    reg TXD_buf2;
    always @(posedge CLK) begin
        TXD_buf1 <= TXD;
        TXD_buf2 <= TXD_buf1;
    end
    

    always @(posedge CLK) begin
        if (send) begin
            if (send_state == STATE_STOP && send_count == 0) begin
                sent <= 1;
            end
        end
        else begin
            sent <= 0;
        end
    end
    


    wire start_send = send && !sent && !RTS;
    

    always @(posedge CLK) begin
        if (!RST_N) begin
            send_state <= STATE_START;
            send_bitnum <= 0;
            send_count <= 0;
        end

        else if (send_count == 0) begin
            case (send_state)

                STATE_IDLE: begin
                    send_state <= STATE_START;
                end
                

                STATE_START: begin
                    if (start_send) begin
                        send_state <= STATE_BIT;
                        send_bitnum <= 0;
                        send_count <= CLKS_PER_BAUD;
                    end
                    else begin
                        send_state <= STATE_START;
                        send_bitnum <= 0;
                        send_count <= 0;
                    end
                end


                STATE_BIT: begin
                    if (send_bitnum < 7) begin
                        send_bitnum <= send_bitnum + 1;
                    end
                    else begin
                        send_bitnum <= 0;
                        send_state <= STATE_STOP;
                    end
                    send_count <= CLKS_PER_BAUD;
                end
                

                STATE_STOP: begin
                    send_state <= STATE_START;
                    send_count <= CLKS_PER_BAUD;
                end
            endcase
        end
        else if (send_count > 0) begin
            send_count <= send_count - 1;
        end
    end
    

    always @(posedge CLK) begin
        if (!RST_N) begin

            RXD <= 1;
        end
        else begin

            if (send_count == 0) begin
                case (send_state)

                    STATE_START: begin
                        if (start_send) begin
                            RXD <= 0;
                        end
                        else begin
                            RXD <= 1;
                        end
                    end


                    STATE_BIT: begin
                        RXD <= char_in[send_bitnum];
                    end
                    

                    STATE_STOP: begin
                        RXD <= 1;
                    end
                endcase
            end
        end
    end
    

    wire start_receive = TXD_buf2 == 0 && !receive && !received;


    always @(posedge CLK) begin
        if (!RST_N) begin
            receive_state <= STATE_START;
            receive_bitnum <= 0;
            receive_count <= 0;
        end

        else if (receive_count == 0) begin
            case (receive_state)

                STATE_IDLE: begin
                    receive_state <= STATE_START;
                end
                

                STATE_START: begin
                    if (start_receive) begin
                        receive_bitnum <= 0;
                        receive_count <= CLKS_PER_BAUD + (CLKS_PER_BAUD / 3);
                        receive_state <= STATE_BIT;
                    end
                end


                STATE_BIT: begin
                    if (receive_bitnum < 7) begin
                        receive_bitnum <= receive_bitnum + 1;
                    end
                    else begin
                        receive_bitnum <= 0;
                        receive_state <= STATE_STOP;
                    end

                    receive_count <= CLKS_PER_BAUD;
                end




                STATE_STOP: begin
                    receive_state <= STATE_START;
                    receive_count <= 3 * (CLKS_PER_BAUD / 4);
                end
            endcase
        end
        else if (receive_count > 0) begin
            receive_count <= receive_count - 1;
        end
    end
    

    always @(posedge CLK) begin
        if (!RST_N) begin
            char_out <= 0;
        end

        else if (receive_count == 0) begin
            case (receive_state)

                STATE_START: begin
                    if (start_receive) begin
                        char_out <= 0;
                    end
                end


                STATE_BIT: begin            
                    char_out[receive_bitnum] <= TXD_buf2;
                end
                

            endcase
        end
    end
    
    always @(posedge CLK) begin
        if (!RST_N) begin
            receive <= 0;
        end
        else begin

            if (receive_state == STATE_STOP && receive_count == 0) begin

                if (TXD_buf2) begin

                    receive <= 1;
                end
                else begin

                    receive <= 0;
                end
            end

            else if (receive) begin
                if (received) begin
                    receive <= 0;
                end
            end
        end
    end



    always @(posedge CLK) begin
        if (!RST_N) begin

            CTS <= 1;
        end
        else begin

            CTS <= receive_state != STATE_START || receive_count > 0 || receive || received;
        end
    end
    
endmodule
module PMOD_BT2 (
    input CLK,
    input RST_N,
    
    input  RTS,
    output reg RXD,
    input  TXD,
    output reg CTS,
    input  STS,
    output wire RST_N_Out,
    
    input [7:0] char_in,
    output reg [7:0] char_out,
    input send,
    output reg sent,
    output reg receive,
    input received
    );

    
    parameter BAUD = 115200;
    parameter CLK_FREQ = 100000000;
    localparam CLKS_PER_BAUD = CLK_FREQ / BAUD;
    
    localparam [1:0] STATE_IDLE = 0;
    localparam [1:0] STATE_START = 1;
    localparam [1:0] STATE_BIT = 2;
    localparam [1:0] STATE_STOP = 3;

    assign RST_N_Out = RST_N;
    
    reg [1:0] send_state;
    reg [2:0] send_bitnum;
    reg [31:0] send_count;
    
    reg [1:0] receive_state;
    reg [2:0] receive_bitnum;
    reg [31:0] receive_count;
    


    reg TXD_buf1;
    reg TXD_buf2;
    always @(posedge CLK) begin
        TXD_buf1 <= TXD;
        TXD_buf2 <= TXD_buf1;
    end
    

    always @(posedge CLK) begin
        if (send) begin
            if (send_state == STATE_STOP && send_count == 0) begin
                sent <= 1;
            end
        end
        else begin
            sent <= 0;
        end
    end
    


    wire start_send = send && !sent && !RTS;
    

    always @(posedge CLK) begin
        if (!RST_N) begin
            send_state <= STATE_START;
            send_bitnum <= 0;
            send_count <= 0;
        end

        else if (send_count == 0) begin
            case (send_state)

                STATE_IDLE: begin
                    send_state <= STATE_START;
                end
                

                STATE_START: begin
                    if (start_send) begin
                        send_state <= STATE_BIT;
                        send_bitnum <= 0;
                        send_count <= CLKS_PER_BAUD;
                    end
                    else begin
                        send_state <= STATE_START;
                        send_bitnum <= 0;
                        send_count <= 0;
                    end
                end


                STATE_BIT: begin
                    if (send_bitnum < 7) begin
                        send_bitnum <= send_bitnum + 1;
                    end
                    else begin
                        send_bitnum <= 0;
                        send_state <= STATE_STOP;
                    end
                    send_count <= CLKS_PER_BAUD;
                end
                

                STATE_STOP: begin
                    send_state <= STATE_START;
                    send_count <= CLKS_PER_BAUD;
                end
            endcase
        end
        else if (send_count > 0) begin
            send_count <= send_count - 1;
        end
    end
    

    always @(posedge CLK) begin
        if (!RST_N) begin

            RXD <= 1;
        end
        else begin

            if (send_count == 0) begin
                case (send_state)

                    STATE_START: begin
                        if (start_send) begin
                            RXD <= 0;
                        end
                        else begin
                            RXD <= 1;
                        end
                    end


                    STATE_BIT: begin
                        RXD <= char_in[send_bitnum];
                    end
                    

                    STATE_STOP: begin
                        RXD <= 1;
                    end
                endcase
            end
        end
    end
    

    wire start_receive = TXD_buf2 == 0 && !receive && !received;


    always @(posedge CLK) begin
        if (!RST_N) begin
            receive_state <= STATE_START;
            receive_bitnum <= 0;
            receive_count <= 0;
        end

        else if (receive_count == 0) begin
            case (receive_state)

                STATE_IDLE: begin
                    receive_state <= STATE_START;
                end
                

                STATE_START: begin
                    if (start_receive) begin
                        receive_bitnum <= 0;
                        receive_count <= CLKS_PER_BAUD + (CLKS_PER_BAUD / 3);
                        receive_state <= STATE_BIT;
                    end
                end


                STATE_BIT: begin
                    if (receive_bitnum < 7) begin
                        receive_bitnum <= receive_bitnum + 1;
                    end
                    else begin
                        receive_bitnum <= 0;
                        receive_state <= STATE_STOP;
                    end

                    receive_count <= CLKS_PER_BAUD;
                end




                STATE_STOP: begin
                    receive_state <= STATE_START;
                    receive_count <= 3 * (CLKS_PER_BAUD / 4);
                end
            endcase
        end
        else if (receive_count > 0) begin
            receive_count <= receive_count - 1;
        end
    end
    

    always @(posedge CLK) begin
        if (!RST_N) begin
            char_out <= 0;
        end

        else if (receive_count == 0) begin
            case (receive_state)

                STATE_START: begin
                    if (start_receive) begin
                        char_out <= 0;
                    end
                end


                STATE_BIT: begin            
                    char_out[receive_bitnum] <= TXD_buf2;
                end
                

            endcase
        end
    end
    
    always @(posedge CLK) begin
        if (!RST_N) begin
            receive <= 0;
        end
        else begin

            if (receive_state == STATE_STOP && receive_count == 0) begin

                if (TXD_buf2) begin

                    receive <= 1;
                end
                else begin

                    receive <= 0;
                end
            end

            else if (receive) begin
                if (received) begin
                    receive <= 0;
                end
            end
        end
    end



    always @(posedge CLK) begin
        if (!RST_N) begin

            CTS <= 1;
        end
        else begin

            CTS <= receive_state != STATE_START || receive_count > 0 || receive || received;
        end
    end
    
endmodule