data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v
1: b'%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:18: Cannot find include file: baudgen.vh\n`include "baudgen.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149070951/tests/04-test-echo,data/full_repos/permissive/149070951/baudgen.vh\n             data/full_repos/permissive/149070951/tests/04-test-echo,data/full_repos/permissive/149070951/baudgen.vh.v\n             data/full_repos/permissive/149070951/tests/04-test-echo,data/full_repos/permissive/149070951/baudgen.vh.sv\n             baudgen.vh\n             baudgen.vh.v\n             baudgen.vh.sv\n             obj_dir/baudgen.vh\n             obj_dir/baudgen.vh.v\n             obj_dir/baudgen.vh.sv\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:22: Define or directive not defined: \'`B115200\'\n         parameter BAUDRATE = `B115200    \n                              ^~~~~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:23: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n)(\n^\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n         input wire rstn,         \n         ^~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n         input wire rx,           \n         ^~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n         output reg rcv,          \n         ^~~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:28: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n         output reg [7:0] data    \n         ^~~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:29: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:48: syntax error, unexpected always\nalways @(posedge clk)\n^~~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:63: syntax error, unexpected always\nalways @(posedge clk)\n^~~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:73: syntax error, unexpected always\nalways @(posedge clk)\n^~~~~~\n%Error: data/full_repos/permissive/149070951/tests/04-test-echo/uart_rx.v:99: syntax error, unexpected always\nalways @(posedge clk)\n^~~~~~\n%Error: Exiting due to 12 error(s)\n'
module uart_rx #(
         parameter BAUDRATE = `B115200
)(
         input wire clk,
         input wire rstn,
         input wire rx,
         output reg rcv,
         output reg [7:0] data
);


wire clk_baud;


reg bauden;
reg clear;
reg load;








reg rx_r;

always @(posedge clk)
  rx_r <= rx;


baudgen_rx #(BAUDRATE)
  baudgen0 (
    .rstn(rstn),
    .clk(clk),
    .clk_ena(bauden),
    .clk_out(clk_baud)
  );


reg [3:0] bitc;

always @(posedge clk)
  if (clear)
    bitc <= 4'd0;
  else if (clear == 0 && clk_baud == 1)
    bitc <= bitc + 1;



reg [9:0] raw_data;

always @(posedge clk)
  if (clk_baud == 1)
    raw_data <= {rx_r, raw_data[9:1]};


always @(posedge clk)
  if (rstn == 0)
    data <= 0;
  else if (load)
    data <= raw_data[8:1];






localparam IDLE = 2'd0;
localparam RECV = 2'd1;
localparam LOAD = 2'd2;
localparam DAV = 2'd3;


reg [1:0] state;
reg [1:0] next_state;


always @(posedge clk)
  if (!rstn)
    state <= IDLE;
  else
    state <= next_state;


always @(*) begin


  next_state = state;
  bauden = 0;
  clear = 0;
  load = 0;

  case(state)



    IDLE: begin
      clear = 1;
      rcv = 0;
      if (rx_r == 0)
        next_state = RECV;
    end



    RECV: begin
      bauden = 1;
      rcv = 0;
      if (bitc == 4'd10)
        next_state = LOAD;
    end


    LOAD: begin
      load = 1;
      rcv = 0;
      next_state = DAV;
    end


    DAV: begin
      rcv = 1;
      next_state = IDLE;
    end

    default:
      rcv = 0;

  endcase

end

endmodule
module uart_rx #(
         parameter BAUDRATE = `B115200
)(
         input wire clk,
         input wire rstn,
         input wire rx,
         output reg rcv,
         output reg [7:0] data
);



wire clk_baud;


reg bauden;
reg clear;
reg load;








reg rx_r;

always @(posedge clk)
  rx_r <= rx;


baudgen_rx #(BAUDRATE)
  baudgen0 (
    .rstn(rstn),
    .clk(clk),
    .clk_ena(bauden),
    .clk_out(clk_baud)
  );


reg [3:0] bitc;

always @(posedge clk)
  if (clear)
    bitc <= 4'd0;
  else if (clear == 0 && clk_baud == 1)
    bitc <= bitc + 1;



reg [9:0] raw_data;

always @(posedge clk)
  if (clk_baud == 1)
    raw_data <= {rx_r, raw_data[9:1]};


always @(posedge clk)
  if (rstn == 0)
    data <= 0;
  else if (load)
    data <= raw_data[8:1];






localparam IDLE = 2'd0;
localparam RECV = 2'd1;
localparam LOAD = 2'd2;
localparam DAV = 2'd3;


reg [1:0] state;
reg [1:0] next_state;


always @(posedge clk)
  if (!rstn)
    state <= IDLE;
  else
    state <= next_state;


always @(*) begin


  next_state = state;
  bauden = 0;
  clear = 0;
  load = 0;

  case(state)



    IDLE: begin
      clear = 1;
      rcv = 0;
      if (rx_r == 0)
        next_state = RECV;
    end



    RECV: begin
      bauden = 1;
      rcv = 0;
      if (bitc == 4'd10)
        next_state = LOAD;
    end


    LOAD: begin
      load = 1;
      rcv = 0;
      next_state = DAV;
    end


    DAV: begin
      rcv = 1;
      next_state = IDLE;
    end

    default:
      rcv = 0;

  endcase

end

endmodule