data/full_repos/permissive/201488448/2_circuits/2_sequential/17_edgecapture.v
 line:19: before: "i"
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/17_edgecapture.v:17: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                    : ... In instance top_module\n                out <= 32'b0;\n                ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/17_edgecapture.v:21: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                    : ... In instance top_module\n                        out[i] <= 1'b1;\n                        ^~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] d_last1, d_last2;
    
    always@(posedge clk) begin
       d_last1 <= in; 
    end
    assign d_last2 = ~in & d_last1;
    
    always@(posedge clk)
        begin
            if(reset)
                out <= 32'b0;
            else begin
                for(int i=0; i<32; i=i+1) begin
                    if(d_last2[i])
                        out[i] <= 1'b1;
                end
			end
        end
            
endmodule
module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);

    reg [31:0] d_last1, d_last2;
    
    always@(posedge clk) begin
       d_last1 <= in; 
    end
    assign d_last2 = ~in & d_last1;
    
    always@(posedge clk)
        begin
            if(reset)
                out <= 32'b0;
            else begin
                for(int i=0; i<32; i=i+1) begin
                    if(d_last2[i])
                        out[i] <= 1'b1;
                end
			end
        end
            
endmodule