data/full_repos/permissive/219219909/Radix-3/src/mul.v
data/verilator_xmls/dfeea3d3-f213-40aa-b073-49ec14d87eb8.xml
module mul(
    input [31:0] a,
    output [31:0] a_out
    );
assign a_out[31]=~a[31];
assign a_out[30:23]=a[30:23]-8'b00000001;
assign a_out[22:0]=a[22:0];

endmodule
module mul(
    input [31:0] a,
    output [31:0] a_out
    );

assign a_out[31]=~a[31];
assign a_out[30:23]=a[30:23]-8'b00000001;
assign a_out[22:0]=a[22:0];

endmodule