data/full_repos/permissive/21051978/processor/syn/src/datamem.v
None: at end of input
1: b'%Error: data/full_repos/permissive/21051978/processor/syn/src/datamem.v:10: Cannot find include file: control.h\n`include "control.h" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor/syn/src,data/full_repos/permissive/21051978/control.h\n             data/full_repos/permissive/21051978/processor/syn/src,data/full_repos/permissive/21051978/control.h.v\n             data/full_repos/permissive/21051978/processor/syn/src,data/full_repos/permissive/21051978/control.h.sv\n             control.h\n             control.h.v\n             control.h.sv\n             obj_dir/control.h\n             obj_dir/control.h.v\n             obj_dir/control.h.sv\n%Error: data/full_repos/permissive/21051978/processor/syn/src/datamem.v:90: Define or directive not defined: \'`memwld\'\n   `memwld:\n   ^~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/syn/src/datamem.v:90: syntax error, unexpected \':\', expecting endcase\n   `memwld:\n          ^\n%Error: data/full_repos/permissive/21051978/processor/syn/src/datamem.v:95: Define or directive not defined: \'`memwst\'\n   `memwst:\n   ^~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/syn/src/datamem.v:96: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    begin\n    ^~~~~\n%Error: data/full_repos/permissive/21051978/processor/syn/src/datamem.v:100: Define or directive not defined: \'`memnop\'\n   `memnop:\n   ^~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/syn/src/datamem.v:101: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    begin\n    ^~~~~\n%Error: data/full_repos/permissive/21051978/processor/syn/src/datamem.v:104: syntax error, unexpected \':\', expecting clocking\n   default:\n          ^\n%Error: Cannot continue\n'
module data_mem (data_out,data_in,mem_ctrl_addr,clk,dm_ctrl_sig);




	


	output [0:127] data_out;
	
	
	



	input [0:127] data_in;

	input [0:31] mem_ctrl_addr;

	input clk;

	input [0:1] dm_ctrl_sig;
	
	
	



	
	
	
	






	


	reg [0:31] data_out;

	reg [0:127] data_mem [0:255];

	
	
	

	
	initial
	begin

		$readmemh("rf1.fill",data_mem);
	end
	
	

	always @(posedge clk)
	begin

		case(dm_ctrl_sig)
			`memwld:
				begin

					data_out<=data_mem[mem_ctrl_addr];
				end
			`memwst:
				begin

					data_mem[mem_ctrl_addr]<=data_in;
				end
			`memnop:
				begin
					data_out<=128'd0;
				end
			default:
				begin
					data_out<=128'd0;
				end
		endcase
	end
	
	
endmodule
module data_mem (data_out,data_in,mem_ctrl_addr,clk,dm_ctrl_sig);





	


	output [0:127] data_out;
	
	
	



	input [0:127] data_in;

	input [0:31] mem_ctrl_addr;

	input clk;

	input [0:1] dm_ctrl_sig;
	
	
	



	
	
	
	






	


	reg [0:31] data_out;

	reg [0:127] data_mem [0:255];

	
	
	

	
	initial
	begin

		$readmemh("rf1.fill",data_mem);
	end
	
	

	always @(posedge clk)
	begin

		case(dm_ctrl_sig)
			`memwld:
				begin

					data_out<=data_mem[mem_ctrl_addr];
				end
			`memwst:
				begin

					data_mem[mem_ctrl_addr]<=data_in;
				end
			`memnop:
				begin
					data_out<=128'd0;
				end
			default:
				begin
					data_out<=128'd0;
				end
		endcase
	end
	
	
endmodule