data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100; $stop;\n ^\n%Error: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:13: Can\'t find definition of variable: \'write\'\n write = 1\'b0;\n ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:14: Can\'t find definition of variable: \'wrAddr\'\n wrAddr = 3\'b0;\n ^~~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:15: Can\'t find definition of variable: \'wrData\'\n wrData = 16\'b0;\n ^~~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:55: Can\'t find definition of variable: \'rdAddrA\'\n rdAddrA = 3\'b000;\n ^~~~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/regfile32x64_testbench.v:56: Can\'t find definition of variable: \'rdAddrB\'\n                                                                                    : ... Suggested alternative: \'rdAddrA\'\n rdAddrB = 3\'b001;\n ^~~~~~~\n%Error: Exiting due to 5 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regfile32x64_testbench;

	reg [4:0]SA, SB, DA;
	reg [63:0]D;
	reg W, reset, clock;

	wire [63:0]A, B;
	
regfile32x64 dut (.rdDataA(A), .rdDataB(B), .rdAddrA(SA), .rdAddrB(SB), .wrData(D), .wrAddr(DA), .write(W), .reset(reset), .clk(clock));

initial begin
	reset = 1'b1;
	write = 1'b0;
	wrAddr = 3'b0;
	wrData = 16'b0;
	#100;
	reset = 1'b0;
	#100;
	wrAddr = 3'b000;
	#100;
	wrData = 16'hFFFF;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b001;
	#100;
	wrData = 16'hAAAA;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b010;
	#100;
	wrData = 16'hCCCC;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b011;
	#100;
	wrData = 16'hF0F0;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	rdAddrA = 3'b000;
	rdAddrB = 3'b001;
	#100;
	rdAddrA = 3'b010;
	rdAddrB = 3'b011;
	#100; $stop;
end
endmodule
module regfile32x64_testbench;


	reg [4:0]SA, SB, DA;
	reg [63:0]D;
	reg W, reset, clock;

	wire [63:0]A, B;
	
regfile32x64 dut (.rdDataA(A), .rdDataB(B), .rdAddrA(SA), .rdAddrB(SB), .wrData(D), .wrAddr(DA), .write(W), .reset(reset), .clk(clock));

initial begin
	reset = 1'b1;
	write = 1'b0;
	wrAddr = 3'b0;
	wrData = 16'b0;
	#100;
	reset = 1'b0;
	#100;
	wrAddr = 3'b000;
	#100;
	wrData = 16'hFFFF;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b001;
	#100;
	wrData = 16'hAAAA;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b010;
	#100;
	wrData = 16'hCCCC;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b011;
	#100;
	wrData = 16'hF0F0;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	rdAddrA = 3'b000;
	rdAddrB = 3'b001;
	#100;
	rdAddrA = 3'b010;
	rdAddrB = 3'b011;
	#100; $stop;
end
endmodule