data/full_repos/permissive/216615048/src/reger.v
1: b'%Error: data/full_repos/permissive/216615048/src/reger.v:73: Cannot find file containing module: \'register\'\n            register regriar(clk, writedata, rst, load[i], out[i]);\n            ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216615048/src,data/full_repos/permissive/216615048/register\n             data/full_repos/permissive/216615048/src,data/full_repos/permissive/216615048/register.v\n             data/full_repos/permissive/216615048/src,data/full_repos/permissive/216615048/register.sv\n             register\n             register.v\n             register.sv\n             obj_dir/register\n             obj_dir/register.v\n             obj_dir/register.sv\n%Warning-WIDTH: data/full_repos/permissive/216615048/src/reger.v:82: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'writereg\' generates 5 bits.\n                                                                   : ... In instance RegFile\n    assign load = regwrite && writereg ? 1 << writereg : 0;\n                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module RegFile (
input clk, rst, input [4:0] readreg1, readreg2, writereg, input [31:0] writedata, input regwrite, output [31:0] readdata1, readdata2 );

    wire [31:0]load;
    wire [31:0]out[0:31];
    
    genvar i;
    generate
        for (i = 0; i < 32; i = i + 1) begin
            register regriar(clk, writedata, rst, load[i], out[i]);
        end
    endgenerate
    

    assign readdata1 = out[readreg1];
    assign readdata2 = out[readreg2];

        
    assign load = regwrite && writereg ? 1 << writereg : 0;
    
endmodule
module RegFile (
input clk, rst, input [4:0] readreg1, readreg2, writereg, input [31:0] writedata, input regwrite, output [31:0] readdata1, readdata2 );


    wire [31:0]load;
    wire [31:0]out[0:31];
    
    genvar i;
    generate
        for (i = 0; i < 32; i = i + 1) begin
            register regriar(clk, writedata, rst, load[i], out[i]);
        end
    endgenerate
    

    assign readdata1 = out[readreg1];
    assign readdata2 = out[readreg2];

        
    assign load = regwrite && writereg ? 1 << writereg : 0;
    
endmodule