data/full_repos/permissive/1840016/lab2/proj2_testbench_2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/1840016/lab2/proj2_testbench_2.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #10 clk =~clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/1840016/lab2/proj2_testbench_2.v:27: Cannot find file containing module: \'add16_LA\'\n   add16_LA A1(A, B, 1\'b0, sum1, cout1, P, G); \n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/1840016/lab2,data/full_repos/permissive/1840016/add16_LA\n             data/full_repos/permissive/1840016/lab2,data/full_repos/permissive/1840016/add16_LA.v\n             data/full_repos/permissive/1840016/lab2,data/full_repos/permissive/1840016/add16_LA.sv\n             add16_LA\n             add16_LA.v\n             add16_LA.sv\n             obj_dir/add16_LA\n             obj_dir/add16_LA.v\n             obj_dir/add16_LA.sv\n%Error: data/full_repos/permissive/1840016/lab2/proj2_testbench_2.v:29: Cannot find file containing module: \'ripple_adder\'\n   ripple_adder DUT1(A[7:0],B[7:0], 1\'b0, sum2[7:0], add1_to_add2);\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/1840016/lab2/proj2_testbench_2.v:30: Cannot find file containing module: \'ripple_adder\'\n   ripple_adder DUT2(A[15:8],B[15:8], add1_to_add2, sum2[15:8], cout2);\n   ^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module proj2_testbench_2;

   reg clk;
   wire [15:0] sum1, sum2;
   reg [15:0] A, B;
   wire cout1;
   wire cout2;
   wire P, G;
  
   add16_LA A1(A, B, 1'b0, sum1, cout1, P, G); 
   
   ripple_adder DUT1(A[7:0],B[7:0], 1'b0, sum2[7:0], add1_to_add2);
   ripple_adder DUT2(A[15:8],B[15:8], add1_to_add2, sum2[15:8], cout2);

   always
   #10 clk =~clk;

   initial begin
      clk = 1'b0;
      A = 16'h1;
      B = 16'h1;
   end

   always @(posedge clk)
   A=A+1;

endmodule
module proj2_testbench_2;


   reg clk;
   wire [15:0] sum1, sum2;
   reg [15:0] A, B;
   wire cout1;
   wire cout2;
   wire P, G;
  
   add16_LA A1(A, B, 1'b0, sum1, cout1, P, G); 
   
   ripple_adder DUT1(A[7:0],B[7:0], 1'b0, sum2[7:0], add1_to_add2);
   ripple_adder DUT2(A[15:8],B[15:8], add1_to_add2, sum2[15:8], cout2);

   always
   #10 clk =~clk;

   initial begin
      clk = 1'b0;
      A = 16'h1;
      B = 16'h1;
   end

   always @(posedge clk)
   A=A+1;

endmodule