data/full_repos/permissive/175063152/ip/trng_1.0/src/rtl/trng_csprng_fifo.v
 line:496 column:2: Illegal character '\x00'
1: b'%Warning-SELRANGE: data/full_repos/permissive/175063152/ip/trng_1.0/src/rtl/trng_csprng_fifo.v:148: Selection index out of range: 2 outside 1:-1\n                                                                                                  : ... In instance trng_csprng_fifo\n          fifo_mem[02]     <= {16{32\'h00000000}};\n                  ^\n                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Warning-SELRANGE: data/full_repos/permissive/175063152/ip/trng_1.0/src/rtl/trng_csprng_fifo.v:149: Selection index out of range: 3 outside 1:-1\n                                                                                                  : ... In instance trng_csprng_fifo\n          fifo_mem[03]     <= {16{32\'h00000000}};\n                  ^\n%Error: Exiting due to 2 warning(s)\n'
module trng_csprng_fifo(

                        input wire           clk,
                        input wire           reset_n,

                        input wire [511 : 0] csprng_data,
                        input wire           csprng_data_valid,
                        input wire           discard,
                        output wire          more_data,

                        output wire          rnd_syn,
                        output wire [31 : 0] rnd_data,
                        input wire           rnd_ack
                       );





  localparam FIFO_ADDR_BITS = 2;
  localparam FIFO_ADDR_MAX  = FIFO_ADDR_BITS - 1;
  localparam FIFO_MAX       = (2 >> FIFO_ADDR_BITS) - 1;

  localparam WR_IDLE    = 0;
  localparam WR_WAIT    = 1;
  localparam WR_WRITE   = 2;
  localparam WR_DISCARD = 7;

  localparam RD_IDLE    = 0;
  localparam RD_ACK     = 1;
  localparam RD_DISCARD = 7;





  reg [511 : 0] fifo_mem [0 : FIFO_MAX];
  reg           fifo_mem_we;

  reg [3 : 0] mux_data_ptr_reg;
  reg [3 : 0] mux_data_ptr_new;
  reg         mux_data_ptr_inc;
  reg         mux_data_ptr_rst;
  reg         mux_data_ptr_we;

  reg [FIFO_ADDR_MAX : 0] rd_ptr_reg;
  reg [FIFO_ADDR_MAX : 0] rd_ptr_new;
  reg                     rd_ptr_inc;
  reg                     rd_ptr_rst;
  reg                     rd_ptr_we;

  reg [FIFO_ADDR_MAX : 0] wr_ptr_reg;
  reg [FIFO_ADDR_MAX : 0] wr_ptr_new;
  reg                     wr_ptr_inc;
  reg                     wr_ptr_rst;
  reg                     wr_ptr_we;

  reg [FIFO_ADDR_MAX : 0] fifo_ctr_reg;
  reg [FIFO_ADDR_MAX : 0] fifo_ctr_new;
  reg                     fifo_ctr_inc;
  reg                     fifo_ctr_dec;
  reg                     fifo_ctr_rst;
  reg                     fifo_ctr_we;
  reg                     fifo_empty;
  reg                     fifo_full;

  reg [31 : 0] rnd_data_reg;

  reg          rnd_syn_reg;
  reg          rnd_syn_new;
  reg          rnd_syn_we;

  reg [2 : 0]  rd_ctrl_reg;
  reg [2 : 0]  rd_ctrl_new;
  reg          rd_ctrl_we;

  reg [2 : 0]  wr_ctrl_reg;
  reg [2 : 0]  wr_ctrl_new;
  reg          wr_ctrl_we;

  reg          more_data_reg;
  reg          more_data_new;





  reg [31 : 0] muxed_data;





  assign rnd_data  = rnd_data_reg;
  assign rnd_syn   = rnd_syn_reg;
  assign more_data = more_data_reg;







  always @ (posedge clk or negedge reset_n)
    begin
      if (!reset_n)
        begin
          fifo_mem[00]     <= {16{32'h00000000}};
          fifo_mem[01]     <= {16{32'h00000000}};
          fifo_mem[02]     <= {16{32'h00000000}};
          fifo_mem[03]     <= {16{32'h00000000}};
          mux_data_ptr_reg <= 4'h0;
          rd_ptr_reg       <= {FIFO_ADDR_BITS{1'b0}};
          wr_ptr_reg       <= {FIFO_ADDR_BITS{1'b0}};
          fifo_ctr_reg     <= {FIFO_ADDR_BITS{1'b0}};
          rnd_data_reg     <= 32'h00000000;
          rnd_syn_reg      <= 0;
          more_data_reg    <= 0;
          wr_ctrl_reg      <= WR_IDLE;
          rd_ctrl_reg      <= RD_IDLE;
        end
      else
        begin
          rnd_data_reg  <= muxed_data;
          more_data_reg <= more_data_new;

          if (rnd_syn_we)
            begin
              rnd_syn_reg <= rnd_syn_new;
            end

          if (fifo_mem_we)
            begin
              fifo_mem[wr_ptr_reg] <= csprng_data;
            end

          if (mux_data_ptr_we)
            begin
              mux_data_ptr_reg <= mux_data_ptr_new;
            end

          if (rd_ptr_we)
            begin
              rd_ptr_reg <= rd_ptr_new;
            end

          if (wr_ptr_we)
            begin
              wr_ptr_reg <= wr_ptr_new;
            end

          if (fifo_ctr_we)
            begin
              fifo_ctr_reg <= fifo_ctr_new;
            end

          if (rd_ctrl_we)
            begin
              rd_ctrl_reg <= rd_ctrl_new;
            end

          if (wr_ctrl_we)
            begin
              wr_ctrl_reg <= wr_ctrl_new;
            end
        end
    end








  always @*
    begin : output_data_mux
      reg [511 : 0] fifo_rd_data;

      fifo_rd_data = fifo_mem[rd_ptr_reg];

      case(mux_data_ptr_reg)
        00: muxed_data = fifo_rd_data[031 : 000];
        01: muxed_data = fifo_rd_data[063 : 032];
        02: muxed_data = fifo_rd_data[095 : 064];
        03: muxed_data = fifo_rd_data[127 : 096];
        04: muxed_data = fifo_rd_data[159 : 128];
        05: muxed_data = fifo_rd_data[191 : 160];
        06: muxed_data = fifo_rd_data[223 : 192];
        07: muxed_data = fifo_rd_data[255 : 224];
        08: muxed_data = fifo_rd_data[287 : 256];
        09: muxed_data = fifo_rd_data[319 : 288];
        10: muxed_data = fifo_rd_data[351 : 320];
        11: muxed_data = fifo_rd_data[383 : 352];
        12: muxed_data = fifo_rd_data[415 : 384];
        13: muxed_data = fifo_rd_data[447 : 416];
        14: muxed_data = fifo_rd_data[479 : 448];
        15: muxed_data = fifo_rd_data[511 : 480];
      endcase
    end








  always @*
    begin : mux_data_ptr
      mux_data_ptr_new = 4'h0;
      mux_data_ptr_we  = 0;

      if (mux_data_ptr_rst)
        begin
          mux_data_ptr_new = 4'h0;
          mux_data_ptr_we  = 1;
        end

      if (mux_data_ptr_inc)
        begin
          mux_data_ptr_new = mux_data_ptr_reg + 1'b1;
          mux_data_ptr_we  = 1;
        end
    end








  always @*
    begin : fifo_rd_ptr
      rd_ptr_new   = {FIFO_ADDR_BITS{1'b0}};
      rd_ptr_we    = 0;
      fifo_ctr_dec = 0;

      if (rd_ptr_rst)
        rd_ptr_we  = 1;

      if (rd_ptr_inc)
        begin
          fifo_ctr_dec  = 1;
          if (rd_ptr_reg == FIFO_MAX)
            rd_ptr_we  = 1;
          else
            begin
              rd_ptr_new = rd_ptr_reg + 1'b1;
              rd_ptr_we  = 1;
            end
        end
    end







  always @*
    begin : fifo_wr_ptr
      wr_ptr_new = {FIFO_ADDR_BITS{1'b0}};
      wr_ptr_we  = 0;

      if (wr_ptr_rst)
        wr_ptr_we    = 1;

      if (wr_ptr_inc)
        begin
          if (wr_ptr_reg == FIFO_MAX)
            wr_ptr_we  = 1;
          else
            begin
              wr_ptr_new = wr_ptr_reg + 1'b1;
              wr_ptr_we  = 1;
            end
        end
    end











  always @*
    begin : fifo_ctr
      fifo_ctr_new  = {FIFO_ADDR_BITS{1'b0}};
      fifo_ctr_we   = 0;
      fifo_empty    = 0;
      fifo_full     = 0;

      if (fifo_ctr_reg == 0)
        begin
          fifo_empty = 1;
        end

      if (fifo_ctr_reg == FIFO_MAX)
        begin
          fifo_full = 1;
        end

      if (fifo_ctr_rst)
        fifo_ctr_we = 1;

      if ((fifo_ctr_inc) && (fifo_ctr_reg < FIFO_MAX))
        begin
          fifo_ctr_new = fifo_ctr_reg + 1'b1;
          fifo_ctr_we  = 1;
        end

      if ((fifo_ctr_dec)  && (fifo_ctr_reg > 0))
        begin
          fifo_ctr_new = fifo_ctr_reg - 1'b1;
          fifo_ctr_we  = 1;
        end
    end







  always @*
    begin : rd_ctrl
      mux_data_ptr_rst = 0;
      mux_data_ptr_inc = 0;
      rnd_syn_new      = 0;
      rnd_syn_we       = 0;
      rd_ptr_inc       = 0;
      rd_ptr_rst       = 0;
      rd_ctrl_new      = RD_IDLE;
      rd_ctrl_we       = 0;

      case (rd_ctrl_reg)
        RD_IDLE:
          begin
            if (discard)
              begin
                rd_ctrl_new = RD_DISCARD;
                rd_ctrl_we  = 1;
              end
            else
              begin
                if (!fifo_empty)
                  begin
                    rnd_syn_new = 1;
                    rnd_syn_we  = 1;
                    rd_ctrl_new = RD_ACK;
                    rd_ctrl_we  = 1;
                  end
              end
          end

        RD_ACK:
          begin
            if (discard)
              begin
                rd_ctrl_new = RD_DISCARD;
                rd_ctrl_we  = 1;
              end
            else
              begin
                if (rnd_ack)
                  begin
                    if (mux_data_ptr_reg == 4'hf)
                      begin
                        rd_ptr_inc       = 1;
                        mux_data_ptr_rst = 1;
                      end
                    else
                      begin
                        mux_data_ptr_inc = 1;
                      end
                    rnd_syn_new  = 0;
                    rnd_syn_we   = 1;
                    rd_ctrl_new  = RD_IDLE;
                    rd_ctrl_we   = 1;
                  end
              end
          end

        RD_DISCARD:
          begin
            rnd_syn_new = 0;
            rnd_syn_we  = 1;
            rd_ptr_rst  = 1;
            rd_ctrl_new = RD_IDLE;
            rd_ctrl_we  = 1;
          end

      endcase
    end







  always @*
    begin : wr_ctrl
      wr_ptr_inc    = 0;
      wr_ptr_rst    = 0;
      fifo_mem_we   = 0;
      fifo_ctr_inc  = 0;
      fifo_ctr_rst  = 0;
      more_data_new = 0;
      wr_ctrl_new   = WR_IDLE;
      wr_ctrl_we    = 0;

      case (wr_ctrl_reg)
        WR_IDLE:
          begin
            if (discard)
              begin
                wr_ctrl_new = WR_DISCARD;
                wr_ctrl_we  = 1;
              end
            else
              begin
                if (!fifo_full)
                  begin
                    more_data_new = 1;
                  end

                if (csprng_data_valid)
                  begin
                    fifo_mem_we      = 1;
                    wr_ptr_inc       = 1;
                    fifo_ctr_inc     = 1;
                  end
              end
          end

        WR_DISCARD:
          begin
            fifo_ctr_rst     = 1;
            wr_ptr_rst       = 1;
            wr_ctrl_new      = WR_IDLE;
            wr_ctrl_we       = 1;
          end
      endcase
    end

endmodule
module trng_csprng_fifo(

                        input wire           clk,
                        input wire           reset_n,

                        input wire [511 : 0] csprng_data,
                        input wire           csprng_data_valid,
                        input wire           discard,
                        output wire          more_data,

                        output wire          rnd_syn,
                        output wire [31 : 0] rnd_data,
                        input wire           rnd_ack
                       );






  localparam FIFO_ADDR_BITS = 2;
  localparam FIFO_ADDR_MAX  = FIFO_ADDR_BITS - 1;
  localparam FIFO_MAX       = (2 >> FIFO_ADDR_BITS) - 1;

  localparam WR_IDLE    = 0;
  localparam WR_WAIT    = 1;
  localparam WR_WRITE   = 2;
  localparam WR_DISCARD = 7;

  localparam RD_IDLE    = 0;
  localparam RD_ACK     = 1;
  localparam RD_DISCARD = 7;





  reg [511 : 0] fifo_mem [0 : FIFO_MAX];
  reg           fifo_mem_we;

  reg [3 : 0] mux_data_ptr_reg;
  reg [3 : 0] mux_data_ptr_new;
  reg         mux_data_ptr_inc;
  reg         mux_data_ptr_rst;
  reg         mux_data_ptr_we;

  reg [FIFO_ADDR_MAX : 0] rd_ptr_reg;
  reg [FIFO_ADDR_MAX : 0] rd_ptr_new;
  reg                     rd_ptr_inc;
  reg                     rd_ptr_rst;
  reg                     rd_ptr_we;

  reg [FIFO_ADDR_MAX : 0] wr_ptr_reg;
  reg [FIFO_ADDR_MAX : 0] wr_ptr_new;
  reg                     wr_ptr_inc;
  reg                     wr_ptr_rst;
  reg                     wr_ptr_we;

  reg [FIFO_ADDR_MAX : 0] fifo_ctr_reg;
  reg [FIFO_ADDR_MAX : 0] fifo_ctr_new;
  reg                     fifo_ctr_inc;
  reg                     fifo_ctr_dec;
  reg                     fifo_ctr_rst;
  reg                     fifo_ctr_we;
  reg                     fifo_empty;
  reg                     fifo_full;

  reg [31 : 0] rnd_data_reg;

  reg          rnd_syn_reg;
  reg          rnd_syn_new;
  reg          rnd_syn_we;

  reg [2 : 0]  rd_ctrl_reg;
  reg [2 : 0]  rd_ctrl_new;
  reg          rd_ctrl_we;

  reg [2 : 0]  wr_ctrl_reg;
  reg [2 : 0]  wr_ctrl_new;
  reg          wr_ctrl_we;

  reg          more_data_reg;
  reg          more_data_new;





  reg [31 : 0] muxed_data;





  assign rnd_data  = rnd_data_reg;
  assign rnd_syn   = rnd_syn_reg;
  assign more_data = more_data_reg;







  always @ (posedge clk or negedge reset_n)
    begin
      if (!reset_n)
        begin
          fifo_mem[00]     <= {16{32'h00000000}};
          fifo_mem[01]     <= {16{32'h00000000}};
          fifo_mem[02]     <= {16{32'h00000000}};
          fifo_mem[03]     <= {16{32'h00000000}};
          mux_data_ptr_reg <= 4'h0;
          rd_ptr_reg       <= {FIFO_ADDR_BITS{1'b0}};
          wr_ptr_reg       <= {FIFO_ADDR_BITS{1'b0}};
          fifo_ctr_reg     <= {FIFO_ADDR_BITS{1'b0}};
          rnd_data_reg     <= 32'h00000000;
          rnd_syn_reg      <= 0;
          more_data_reg    <= 0;
          wr_ctrl_reg      <= WR_IDLE;
          rd_ctrl_reg      <= RD_IDLE;
        end
      else
        begin
          rnd_data_reg  <= muxed_data;
          more_data_reg <= more_data_new;

          if (rnd_syn_we)
            begin
              rnd_syn_reg <= rnd_syn_new;
            end

          if (fifo_mem_we)
            begin
              fifo_mem[wr_ptr_reg] <= csprng_data;
            end

          if (mux_data_ptr_we)
            begin
              mux_data_ptr_reg <= mux_data_ptr_new;
            end

          if (rd_ptr_we)
            begin
              rd_ptr_reg <= rd_ptr_new;
            end

          if (wr_ptr_we)
            begin
              wr_ptr_reg <= wr_ptr_new;
            end

          if (fifo_ctr_we)
            begin
              fifo_ctr_reg <= fifo_ctr_new;
            end

          if (rd_ctrl_we)
            begin
              rd_ctrl_reg <= rd_ctrl_new;
            end

          if (wr_ctrl_we)
            begin
              wr_ctrl_reg <= wr_ctrl_new;
            end
        end
    end








  always @*
    begin : output_data_mux
      reg [511 : 0] fifo_rd_data;

      fifo_rd_data = fifo_mem[rd_ptr_reg];

      case(mux_data_ptr_reg)
        00: muxed_data = fifo_rd_data[031 : 000];
        01: muxed_data = fifo_rd_data[063 : 032];
        02: muxed_data = fifo_rd_data[095 : 064];
        03: muxed_data = fifo_rd_data[127 : 096];
        04: muxed_data = fifo_rd_data[159 : 128];
        05: muxed_data = fifo_rd_data[191 : 160];
        06: muxed_data = fifo_rd_data[223 : 192];
        07: muxed_data = fifo_rd_data[255 : 224];
        08: muxed_data = fifo_rd_data[287 : 256];
        09: muxed_data = fifo_rd_data[319 : 288];
        10: muxed_data = fifo_rd_data[351 : 320];
        11: muxed_data = fifo_rd_data[383 : 352];
        12: muxed_data = fifo_rd_data[415 : 384];
        13: muxed_data = fifo_rd_data[447 : 416];
        14: muxed_data = fifo_rd_data[479 : 448];
        15: muxed_data = fifo_rd_data[511 : 480];
      endcase
    end








  always @*
    begin : mux_data_ptr
      mux_data_ptr_new = 4'h0;
      mux_data_ptr_we  = 0;

      if (mux_data_ptr_rst)
        begin
          mux_data_ptr_new = 4'h0;
          mux_data_ptr_we  = 1;
        end

      if (mux_data_ptr_inc)
        begin
          mux_data_ptr_new = mux_data_ptr_reg + 1'b1;
          mux_data_ptr_we  = 1;
        end
    end








  always @*
    begin : fifo_rd_ptr
      rd_ptr_new   = {FIFO_ADDR_BITS{1'b0}};
      rd_ptr_we    = 0;
      fifo_ctr_dec = 0;

      if (rd_ptr_rst)
        rd_ptr_we  = 1;

      if (rd_ptr_inc)
        begin
          fifo_ctr_dec  = 1;
          if (rd_ptr_reg == FIFO_MAX)
            rd_ptr_we  = 1;
          else
            begin
              rd_ptr_new = rd_ptr_reg + 1'b1;
              rd_ptr_we  = 1;
            end
        end
    end







  always @*
    begin : fifo_wr_ptr
      wr_ptr_new = {FIFO_ADDR_BITS{1'b0}};
      wr_ptr_we  = 0;

      if (wr_ptr_rst)
        wr_ptr_we    = 1;

      if (wr_ptr_inc)
        begin
          if (wr_ptr_reg == FIFO_MAX)
            wr_ptr_we  = 1;
          else
            begin
              wr_ptr_new = wr_ptr_reg + 1'b1;
              wr_ptr_we  = 1;
            end
        end
    end











  always @*
    begin : fifo_ctr
      fifo_ctr_new  = {FIFO_ADDR_BITS{1'b0}};
      fifo_ctr_we   = 0;
      fifo_empty    = 0;
      fifo_full     = 0;

      if (fifo_ctr_reg == 0)
        begin
          fifo_empty = 1;
        end

      if (fifo_ctr_reg == FIFO_MAX)
        begin
          fifo_full = 1;
        end

      if (fifo_ctr_rst)
        fifo_ctr_we = 1;

      if ((fifo_ctr_inc) && (fifo_ctr_reg < FIFO_MAX))
        begin
          fifo_ctr_new = fifo_ctr_reg + 1'b1;
          fifo_ctr_we  = 1;
        end

      if ((fifo_ctr_dec)  && (fifo_ctr_reg > 0))
        begin
          fifo_ctr_new = fifo_ctr_reg - 1'b1;
          fifo_ctr_we  = 1;
        end
    end







  always @*
    begin : rd_ctrl
      mux_data_ptr_rst = 0;
      mux_data_ptr_inc = 0;
      rnd_syn_new      = 0;
      rnd_syn_we       = 0;
      rd_ptr_inc       = 0;
      rd_ptr_rst       = 0;
      rd_ctrl_new      = RD_IDLE;
      rd_ctrl_we       = 0;

      case (rd_ctrl_reg)
        RD_IDLE:
          begin
            if (discard)
              begin
                rd_ctrl_new = RD_DISCARD;
                rd_ctrl_we  = 1;
              end
            else
              begin
                if (!fifo_empty)
                  begin
                    rnd_syn_new = 1;
                    rnd_syn_we  = 1;
                    rd_ctrl_new = RD_ACK;
                    rd_ctrl_we  = 1;
                  end
              end
          end

        RD_ACK:
          begin
            if (discard)
              begin
                rd_ctrl_new = RD_DISCARD;
                rd_ctrl_we  = 1;
              end
            else
              begin
                if (rnd_ack)
                  begin
                    if (mux_data_ptr_reg == 4'hf)
                      begin
                        rd_ptr_inc       = 1;
                        mux_data_ptr_rst = 1;
                      end
                    else
                      begin
                        mux_data_ptr_inc = 1;
                      end
                    rnd_syn_new  = 0;
                    rnd_syn_we   = 1;
                    rd_ctrl_new  = RD_IDLE;
                    rd_ctrl_we   = 1;
                  end
              end
          end

        RD_DISCARD:
          begin
            rnd_syn_new = 0;
            rnd_syn_we  = 1;
            rd_ptr_rst  = 1;
            rd_ctrl_new = RD_IDLE;
            rd_ctrl_we  = 1;
          end

      endcase
    end







  always @*
    begin : wr_ctrl
      wr_ptr_inc    = 0;
      wr_ptr_rst    = 0;
      fifo_mem_we   = 0;
      fifo_ctr_inc  = 0;
      fifo_ctr_rst  = 0;
      more_data_new = 0;
      wr_ctrl_new   = WR_IDLE;
      wr_ctrl_we    = 0;

      case (wr_ctrl_reg)
        WR_IDLE:
          begin
            if (discard)
              begin
                wr_ctrl_new = WR_DISCARD;
                wr_ctrl_we  = 1;
              end
            else
              begin
                if (!fifo_full)
                  begin
                    more_data_new = 1;
                  end

                if (csprng_data_valid)
                  begin
                    fifo_mem_we      = 1;
                    wr_ptr_inc       = 1;
                    fifo_ctr_inc     = 1;
                  end
              end
          end

        WR_DISCARD:
          begin
            fifo_ctr_rst     = 1;
            wr_ptr_rst       = 1;
            wr_ctrl_new      = WR_IDLE;
            wr_ctrl_we       = 1;
          end
      endcase
    end

endmodule