data/full_repos/permissive/205673649/BIP/Source/program_memory.v
None: at end of input
data/verilator_xmls/8a537f7b-bc9a-4fb1-b87e-a521b08d46e7.xml
module program_memory
#(
  parameter RAM_WIDTH = 16,
  parameter RAM_DEPTH = 2048,
  parameter RAM_PERFORMANCE = "LOW_LATENCY",
  parameter INIT_FILE = ""
)
(
  input [clogb2(RAM_DEPTH-1) - 1 : 0] i_addr,

  input i_clk,




  output [RAM_WIDTH - 1 : 0] o_data
);
  
  wire ena = 1 ;
  wire wea = 0 ;
  wire rsta = 0 ;
  wire regcea = 1;
  wire [RAM_WIDTH - 1 : 0] dina = 0;

  reg [RAM_WIDTH - 1 : 0] BRAM [RAM_DEPTH - 1 : 0];
  reg [RAM_WIDTH - 1 : 0] ram_data = {RAM_WIDTH {1'b0}};


  generate
    if (INIT_FILE != "") begin: use_init_file
      initial
        $readmemb(INIT_FILE, BRAM, 0, RAM_DEPTH - 1);
    end 
    else begin: init_bram_to_zero
      integer ram_index;
      initial
        for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
          BRAM[ram_index] = {RAM_WIDTH {1'b0}};
    end
  endgenerate

  always @(posedge i_clk)
    if (ena)
      if (wea)
        BRAM [i_addr] <= dina;
      else
        ram_data <= BRAM [i_addr];


  generate
    if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register


       assign o_data = ram_data;

    end 
    else begin: output_register



      reg [RAM_WIDTH - 1 : 0] reg_data_out = {RAM_WIDTH {1'b0}};

      always @(posedge i_clk)
        if (rsta)
          reg_data_out <= {RAM_WIDTH {1'b0}};
        else if (regcea)
          reg_data_out <= ram_data;

      assign o_data = reg_data_out;

    end
  endgenerate


  function integer clogb2;
    input integer depth;
      for (clogb2 = 0; depth > 0; clogb2 = clogb2+1)
        depth = depth >> 1;
  endfunction

endmodule
module program_memory
#(
  parameter RAM_WIDTH = 16,
  parameter RAM_DEPTH = 2048,
  parameter RAM_PERFORMANCE = "LOW_LATENCY",
  parameter INIT_FILE = ""
)
(
  input [clogb2(RAM_DEPTH-1) - 1 : 0] i_addr,

  input i_clk,




  output [RAM_WIDTH - 1 : 0] o_data
);

  
  wire ena = 1 ;
  wire wea = 0 ;
  wire rsta = 0 ;
  wire regcea = 1;
  wire [RAM_WIDTH - 1 : 0] dina = 0;

  reg [RAM_WIDTH - 1 : 0] BRAM [RAM_DEPTH - 1 : 0];
  reg [RAM_WIDTH - 1 : 0] ram_data = {RAM_WIDTH {1'b0}};


  generate
    if (INIT_FILE != "") begin: use_init_file
      initial
        $readmemb(INIT_FILE, BRAM, 0, RAM_DEPTH - 1);
    end 
    else begin: init_bram_to_zero
      integer ram_index;
      initial
        for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
          BRAM[ram_index] = {RAM_WIDTH {1'b0}};
    end
  endgenerate

  always @(posedge i_clk)
    if (ena)
      if (wea)
        BRAM [i_addr] <= dina;
      else
        ram_data <= BRAM [i_addr];


  generate
    if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register


       assign o_data = ram_data;

    end 
    else begin: output_register



      reg [RAM_WIDTH - 1 : 0] reg_data_out = {RAM_WIDTH {1'b0}};

      always @(posedge i_clk)
        if (rsta)
          reg_data_out <= {RAM_WIDTH {1'b0}};
        else if (regcea)
          reg_data_out <= ram_data;

      assign o_data = reg_data_out;

    end
  endgenerate


  function integer clogb2;
    input integer depth;
      for (clogb2 = 0; depth > 0; clogb2 = clogb2+1)
        depth = depth >> 1;
  endfunction

endmodule