data/full_repos/permissive/174369527/FF/ff-rtl.v
 line:7: before: "="
data/verilator_xmls/6279f01a-d71c-4c3e-bee9-093e91f7ee76.xml
module ff
	(
	input wire [0:0] clk,
	input wire [0:0] d,
	output reg [0:0] q = 1'b0
	);

	always @ (posedge clk) q <= d;
	
endmodule
module ff
	(
	input wire [0:0] clk,
	input wire [0:0] d,
	output reg [0:0] q = 1'b0
	);


	always @ (posedge clk) q <= d;
	
endmodule