data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:36: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n     coaxinreg[i]<=coax_in[i];\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:36: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n     coaxinreg[i]<=coax_in[i];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:39: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n  if (i==8) coax_out[i] <= (Tin[0]>0);  \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:40: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n  else if (i==10) coax_out[i] <= ext_trig_out;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:41: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n  else coax_out[i] <= coaxinreg[i];  \n               ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:41: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n  else coax_out[i] <= coaxinreg[i];  \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:43: Bit extraction of array[7:0] requires 3 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n  if (i<8) histosout[i]<=histos[i][histostosend2];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:43: Bit extraction of array[7:0] requires 3 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n  if (i<8) histosout[i]<=histos[i][histostosend2];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:43: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n  if (i<8) histosout[i]<=histos[i][histostosend2];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:83: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n     Tin[j] <= 20;  \n        ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:84: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n     if (!resethist) histos[4][j] <= histos[4][j]+1;  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:84: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n     if (!resethist) histos[4][j] <= histos[4][j]+1;  \n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:88: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n    if (Tin[j]>0) Tin[j] <= Tin[j]-1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:88: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n    if (Tin[j]>0) Tin[j] <= Tin[j]-1;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:88: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n    if (Tin[j]>0) Tin[j] <= Tin[j]-1;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:82: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n   if (coaxinreg[j]) begin\n                ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:92: Bit extraction of array[7:0] requires 3 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n     histos[i][j] <= 0;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/135622446/trig3_board_trigger_de0nano_lvds-firmware/LED_4.v:92: Bit extraction of array[15:0] requires 4 bit index, not 8 bits.\n                                                                                                         : ... In instance LED_4\n     histos[i][j] <= 0;\n              ^\n%Error: Exiting due to 18 warning(s)\n'
module LED_4(
	input nrst,
	input clk,
	output reg [3:0] led,
	input [16-1:0] coax_in,
	output [16-1:0] coax_out,	
	input [7:0] calibticks, input [7:0] histostosend,
	input clk_adc, output reg[31:0] histosout[8], input resethist, output spareleft, output reg [2:0] delaycounter[16],
	input clk_locked,
	output ext_trig_out,
	input reg[31:0] randnum, input reg[31:0] prescale, input dorolling
	);

reg[7:0] i;
reg[7:0] j;
reg[31:0] histos[8][16];
reg [16-1:0] coaxinreg;
reg pass_prescale;
reg[7:0] triedtofire=0;
reg[7:0] ext_trig_out_counter=0;
reg[31:0] autocounter=0;
reg [7:0] histostosend2;
reg [7:0] calibticks2;
reg [31:0] prescale2;

always@(posedge clk_adc) begin
	
	pass_prescale <= (randnum<=prescale2);
	histostosend2<=histostosend;
	calibticks2<=calibticks;
	prescale2<=prescale;
	
	i=0; while (i<16) begin
		

		   coaxinreg[i]<=coax_in[i];

		
		if (i==8) coax_out[i] <= (Tin[0]>0);
		else if (i==10) coax_out[i] <= ext_trig_out;
		else coax_out[i] <= coaxinreg[i];
		
		if (i<8) histosout[i]<=histos[i][histostosend2];
		





		
		i=i+1;
	end
	if (triedtofire==0 && (Tin[0]>0 && Tin[1]>0)) begin
		if (pass_prescale) begin
			ext_trig_out_counter <= 4;
			autocounter <= 0;
		end
		else begin
			if (ext_trig_out_counter>0) ext_trig_out_counter <= ext_trig_out_counter - 1;
		end
		triedtofire <= 20;
	end
	else begin
		if (autocounter[25]) begin
			if (dorolling) ext_trig_out_counter <= 4;
			autocounter <= 0;
		end
		else begin
			if (ext_trig_out_counter>0) ext_trig_out_counter <= ext_trig_out_counter - 1;
			autocounter <= autocounter+1;
		end
		if (triedtofire>0) triedtofire <= triedtofire-1;
	end
	ext_trig_out <= (ext_trig_out_counter>0);
end


reg[5:0] Tin[16];
always @(posedge clk_adc) begin
		
		j=0; while (j<16) begin
			if (coaxinreg[j]) begin
					Tin[j] <= 20;
					if (!resethist) histos[4][j] <= histos[4][j]+1;
			end
			else begin

				if (Tin[j]>0) Tin[j] <= Tin[j]-1;
			end
			if (resethist) begin
				i=0; while (i<8) begin
					histos[i][j] <= 0;
					i=i+1;
				end
			end
			j=j+1;
		end
		
end



reg [1:0] ledi=0;
reg[31:0] counter=0;
always@(posedge clk) begin
	counter<=counter+1;
	if (counter[25]) begin			
		counter<=0;
		ledi<=ledi+2'b01;
		case (ledi)
		0:	begin led <= 4'b0001; end
		1:	begin led <= 4'b0010; end
		2:	begin led <= 4'b0100; end
		3:	begin led <= 4'b1000; end
		endcase
	end
end
	
endmodule
module LED_4(
	input nrst,
	input clk,
	output reg [3:0] led,
	input [16-1:0] coax_in,
	output [16-1:0] coax_out,	
	input [7:0] calibticks, input [7:0] histostosend,
	input clk_adc, output reg[31:0] histosout[8], input resethist, output spareleft, output reg [2:0] delaycounter[16],
	input clk_locked,
	output ext_trig_out,
	input reg[31:0] randnum, input reg[31:0] prescale, input dorolling
	);


reg[7:0] i;
reg[7:0] j;
reg[31:0] histos[8][16];
reg [16-1:0] coaxinreg;
reg pass_prescale;
reg[7:0] triedtofire=0;
reg[7:0] ext_trig_out_counter=0;
reg[31:0] autocounter=0;
reg [7:0] histostosend2;
reg [7:0] calibticks2;
reg [31:0] prescale2;

always@(posedge clk_adc) begin
	
	pass_prescale <= (randnum<=prescale2);
	histostosend2<=histostosend;
	calibticks2<=calibticks;
	prescale2<=prescale;
	
	i=0; while (i<16) begin
		

		   coaxinreg[i]<=coax_in[i];

		
		if (i==8) coax_out[i] <= (Tin[0]>0);
		else if (i==10) coax_out[i] <= ext_trig_out;
		else coax_out[i] <= coaxinreg[i];
		
		if (i<8) histosout[i]<=histos[i][histostosend2];
		





		
		i=i+1;
	end
	if (triedtofire==0 && (Tin[0]>0 && Tin[1]>0)) begin
		if (pass_prescale) begin
			ext_trig_out_counter <= 4;
			autocounter <= 0;
		end
		else begin
			if (ext_trig_out_counter>0) ext_trig_out_counter <= ext_trig_out_counter - 1;
		end
		triedtofire <= 20;
	end
	else begin
		if (autocounter[25]) begin
			if (dorolling) ext_trig_out_counter <= 4;
			autocounter <= 0;
		end
		else begin
			if (ext_trig_out_counter>0) ext_trig_out_counter <= ext_trig_out_counter - 1;
			autocounter <= autocounter+1;
		end
		if (triedtofire>0) triedtofire <= triedtofire-1;
	end
	ext_trig_out <= (ext_trig_out_counter>0);
end


reg[5:0] Tin[16];
always @(posedge clk_adc) begin
		
		j=0; while (j<16) begin
			if (coaxinreg[j]) begin
					Tin[j] <= 20;
					if (!resethist) histos[4][j] <= histos[4][j]+1;
			end
			else begin

				if (Tin[j]>0) Tin[j] <= Tin[j]-1;
			end
			if (resethist) begin
				i=0; while (i<8) begin
					histos[i][j] <= 0;
					i=i+1;
				end
			end
			j=j+1;
		end
		
end



reg [1:0] ledi=0;
reg[31:0] counter=0;
always@(posedge clk) begin
	counter<=counter+1;
	if (counter[25]) begin			
		counter<=0;
		ledi<=ledi+2'b01;
		case (ledi)
		0:	begin led <= 4'b0001; end
		1:	begin led <= 4'b0010; end
		2:	begin led <= 4'b0100; end
		3:	begin led <= 4'b1000; end
		endcase
	end
end
	
endmodule