data/full_repos/permissive/101423580/v/vgademo.v
'utf-8' codec can't decode byte 0xd0 in position 758: invalid continuation byte
1: b"%Error: data/full_repos/permissive/101423580/v/vgademo.v:37: Duplicate declaration of signal: 'vga_data'\n                                                           : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg [11:0] vga_data;\n           ^~~~~~~~\n        data/full_repos/permissive/101423580/v/vgademo.v:29: ... Location of original declaration\n       output [11:0]vga_data,\n                    ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module vgademo(		input clk,
							input rst,
							input keyReady,
							input [4:0]keyCode,
							input [15:0]SW,
							input [8:0]row,
							input [9:0]col,
							
							output [11:0]vga_data,
							output [31:0]Ccircle,
							output reg rdn
    );

reg [9:0] x;
reg [8:0] y;

reg [11:0] vga_data;
wire [19:0] x_sqr, y_sqr, r_sqr;
reg wasReady;
reg [9:0] radius = 10'd100;

	assign Ccircle = {7'b0, x, 8'b0, y};
	always @(posedge clk) begin
		if(rst) begin
			x <= 10'd320;
			y <= 9'd240;
			radius <= 10'd100;
		end 
		else begin
			wasReady <= keyReady;
			rdn <= 0;
			if(!wasReady && keyReady) begin
				rdn <= 1;
				case(keyCode)
					5'hc: radius <= radius - 10'd5;
					5'he: radius <= radius + 10'd5;
					5'h8: x <= x - 10'd20;
					5'ha: x <= x + 10'd20;
					5'h5: y <= y - 9'd20;
					5'hd: y <= y + 9'd20;
					default : ;
				endcase
			end
		end
	end
	
	assign x_sqr = (x - col) * (x - col);
	assign y_sqr = (y - row) * (y - row);
	assign r_sqr = radius * radius;
	
	always @ (*) begin 
		if ((x_sqr + y_sqr < r_sqr))
			vga_data <= SW[12:1] ;
		else 	if(SW[14]) vga_data <= {row[8:0], col[9:7]};
				else vga_data <= 12'hfff;
		end

endmodule
module vgademo(		input clk,
							input rst,
							input keyReady,
							input [4:0]keyCode,
							input [15:0]SW,
							input [8:0]row,
							input [9:0]col,
							
							output [11:0]vga_data,
							output [31:0]Ccircle,
							output reg rdn
    );


reg [9:0] x;
reg [8:0] y;

reg [11:0] vga_data;
wire [19:0] x_sqr, y_sqr, r_sqr;
reg wasReady;
reg [9:0] radius = 10'd100;

	assign Ccircle = {7'b0, x, 8'b0, y};
	always @(posedge clk) begin
		if(rst) begin
			x <= 10'd320;
			y <= 9'd240;
			radius <= 10'd100;
		end 
		else begin
			wasReady <= keyReady;
			rdn <= 0;
			if(!wasReady && keyReady) begin
				rdn <= 1;
				case(keyCode)
					5'hc: radius <= radius - 10'd5;
					5'he: radius <= radius + 10'd5;
					5'h8: x <= x - 10'd20;
					5'ha: x <= x + 10'd20;
					5'h5: y <= y - 9'd20;
					5'hd: y <= y + 9'd20;
					default : ;
				endcase
			end
		end
	end
	
	assign x_sqr = (x - col) * (x - col);
	assign y_sqr = (y - row) * (y - row);
	assign r_sqr = radius * radius;
	
	always @ (*) begin 
		if ((x_sqr + y_sqr < r_sqr))
			vga_data <= SW[12:1] ;
		else 	if(SW[14]) vga_data <= {row[8:0], col[9:7]};
				else vga_data <= 12'hfff;
		end

endmodule