data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv
 line:116: before: "unsigned"
1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:26: Cannot find file containing module: 'inv_ld_counter'\ninv_ld_counter #(7)  len_cnt( .CLK  ( CLK          ),  \n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter\n             data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter.v\n             data/full_repos/permissive/10379745/hw_de0/hard/i2c,data/full_repos/permissive/10379745/inv_ld_counter.sv\n             inv_ld_counter\n             inv_ld_counter.v\n             inv_ld_counter.sv\n             obj_dir/inv_ld_counter\n             obj_dir/inv_ld_counter.v\n             obj_dir/inv_ld_counter.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:32: Cannot find file containing module: 'inv_ld_counter'\ninv_ld_counter #(7) wlen_cnt( .CLK  ( CLK          ), \n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:38: Cannot find file containing module: 'ffd'\nffd #(1) nack_hack_fd(CLK, RESET, ld_wlen, DATA_IN[7], nack_hack);\n^~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:42: Cannot find file containing module: 'counter'\ncounter #(6) time_count(CLK, s_idle | half_period, 1'b1, time_cnt);\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:44: Cannot find file containing module: 'shift_out_reg_left'\nshift_out_reg_left #(8) sr_out(  .CLK    ( CLK                                  ), \n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:53: Cannot find file containing module: 'shift_in_reg_left'\nshift_in_reg_left   #(8) sr_in(  .CLK   ( CLK                                ),\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:88: Cannot find file containing module: 'ffds'\nffds #(1) scl_fd(CLK, l_scl, scl_q);\n^~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/i2c/i2c.sv:89: Cannot find file containing module: 'ffds'\nffds #(1) sda_fd(CLK, l_sda, sda_q);\n^~~~\n%Error: Exiting due to 8 error(s)\n"
module i2c   ( input        CLK,
               input        RESET,

               input        START,     
               output       BUSY,

               input  [7:0] DATA_IN,  
               output [7:0] DATA_OUT,  
               output       RD_ADV,
               output       WR_ADV,

               inout        SDA,
               inout        SCL );

parameter TAU = 63;

logic ld_len, ld_wlen, adv, l_done, byte_done, read_mode, half_period;
logic l_scl, l_sda, scl_q, sda_q, l_data, l_ack, sreg_out, next_byte, adv_wlen;
logic s_idle, s_start, s_stop_lo, s_stop_hi, s_data_lo, s_data_hi, s_ack_lo, s_ack_hi;
logic shift_in, nack_hack;

assign next_byte = ( half_period & s_data_hi & byte_done & ~l_done );
assign adv_wlen = ( half_period & s_ack_hi & byte_done & ~read_mode);
assign RD_ADV = (next_byte & ~read_mode) | ld_len | ld_wlen;

inv_ld_counter #(7)  len_cnt( .CLK  ( CLK          ),  
                              .SET  ( ld_len       ), 
                              .IN   ( DATA_IN[6:0] ), 
                              .EN   ( next_byte    ),    
                              .ZERO ( l_done       ) );

inv_ld_counter #(7) wlen_cnt( .CLK  ( CLK          ), 
                              .SET  ( ld_wlen      ), 
                              .IN   ( DATA_IN[6:0] ), 
                              .EN   ( adv_wlen     ), 
                              .ZERO ( read_mode    ));

ffd #(1) nack_hack_fd(CLK, RESET, ld_wlen, DATA_IN[7], nack_hack);

logic [5:0] time_cnt;
assign half_period = (time_cnt == TAU);
counter #(6) time_count(CLK, s_idle | half_period, 1'b1, time_cnt);

shift_out_reg_left #(8) sr_out(  .CLK    ( CLK                                  ), 
                                 .UPDATE ( half_period & (s_start | s_ack_hi)   ), 
                                 .SHIFT  ( half_period & s_data_hi & ~byte_done ), 
                                 .DATA   ( DATA_IN                              ), 
                                 .OUT    ( sreg_out                             ),  
                                 .EMPTY  ( byte_done                            ));

assign shift_in = read_mode & half_period & s_data_hi;
assign WR_ADV = read_mode & half_period & s_ack_hi & byte_done;
shift_in_reg_left   #(8) sr_in(  .CLK   ( CLK                                ),
                                 .RESET ( half_period & (s_start | s_ack_hi) ),
                                 .SHIFT ( shift_in                           ),
                                 .IN    ( SDA                                ),
                                 .DATA  ( DATA_OUT                           ));

 i2c_fsm  i2c_fsm(  .CLK       ( CLK         ),
                    .RESET     ( RESET       ),
                    .START     ( START       ),
                    .TIME      ( half_period ),
                    .L_DONE    ( l_done      ),
                    .W_DONE    ( byte_done   ),
                    .LD_LEN    ( ld_len      ),
                    .LD_WLEN   ( ld_wlen     ),
                    .S_DATA_LO ( s_data_lo   ),
                    .S_DATA_HI ( s_data_hi   ),
                    .S_ACK_LO  ( s_ack_lo    ),
                    .S_ACK_HI  ( s_ack_hi    ),
                    .S_START   ( s_start     ),
                    .S_STOP_LO ( s_stop_lo   ),
                    .S_STOP_HI ( s_stop_hi   ),
                    .S_IDLE    ( s_idle      ));

assign BUSY = ~s_idle;
assign l_scl = (s_data_lo | s_ack_lo | s_stop_lo) ? 1'b0 : 1'b1;


assign l_data = sreg_out | read_mode;
assign l_ack  = ~read_mode ^ (nack_hack & l_done);

assign l_sda = (s_start   | s_stop_lo | s_stop_hi ) ? 1'b0   :
               (s_data_lo | s_data_hi)              ? l_data :
               (s_ack_lo  | s_ack_hi )              ? l_ack  : 
                                                      1'b1;

ffds #(1) scl_fd(CLK, l_scl, scl_q);
ffds #(1) sda_fd(CLK, l_sda, sda_q);

assign SDA = sda_q ? 1'bZ : 1'b0;
assign SCL = scl_q ? 1'bZ : 1'b0;

endmodule
module i2c   ( input        CLK,
               input        RESET,

               input        START,     
               output       BUSY,

               input  [7:0] DATA_IN,  
               output [7:0] DATA_OUT,  
               output       RD_ADV,
               output       WR_ADV,

               inout        SDA,
               inout        SCL );


parameter TAU = 63;

logic ld_len, ld_wlen, adv, l_done, byte_done, read_mode, half_period;
logic l_scl, l_sda, scl_q, sda_q, l_data, l_ack, sreg_out, next_byte, adv_wlen;
logic s_idle, s_start, s_stop_lo, s_stop_hi, s_data_lo, s_data_hi, s_ack_lo, s_ack_hi;
logic shift_in, nack_hack;

assign next_byte = ( half_period & s_data_hi & byte_done & ~l_done );
assign adv_wlen = ( half_period & s_ack_hi & byte_done & ~read_mode);
assign RD_ADV = (next_byte & ~read_mode) | ld_len | ld_wlen;

inv_ld_counter #(7)  len_cnt( .CLK  ( CLK          ),  
                              .SET  ( ld_len       ), 
                              .IN   ( DATA_IN[6:0] ), 
                              .EN   ( next_byte    ),    
                              .ZERO ( l_done       ) );

inv_ld_counter #(7) wlen_cnt( .CLK  ( CLK          ), 
                              .SET  ( ld_wlen      ), 
                              .IN   ( DATA_IN[6:0] ), 
                              .EN   ( adv_wlen     ), 
                              .ZERO ( read_mode    ));

ffd #(1) nack_hack_fd(CLK, RESET, ld_wlen, DATA_IN[7], nack_hack);

logic [5:0] time_cnt;
assign half_period = (time_cnt == TAU);
counter #(6) time_count(CLK, s_idle | half_period, 1'b1, time_cnt);

shift_out_reg_left #(8) sr_out(  .CLK    ( CLK                                  ), 
                                 .UPDATE ( half_period & (s_start | s_ack_hi)   ), 
                                 .SHIFT  ( half_period & s_data_hi & ~byte_done ), 
                                 .DATA   ( DATA_IN                              ), 
                                 .OUT    ( sreg_out                             ),  
                                 .EMPTY  ( byte_done                            ));

assign shift_in = read_mode & half_period & s_data_hi;
assign WR_ADV = read_mode & half_period & s_ack_hi & byte_done;
shift_in_reg_left   #(8) sr_in(  .CLK   ( CLK                                ),
                                 .RESET ( half_period & (s_start | s_ack_hi) ),
                                 .SHIFT ( shift_in                           ),
                                 .IN    ( SDA                                ),
                                 .DATA  ( DATA_OUT                           ));

 i2c_fsm  i2c_fsm(  .CLK       ( CLK         ),
                    .RESET     ( RESET       ),
                    .START     ( START       ),
                    .TIME      ( half_period ),
                    .L_DONE    ( l_done      ),
                    .W_DONE    ( byte_done   ),
                    .LD_LEN    ( ld_len      ),
                    .LD_WLEN   ( ld_wlen     ),
                    .S_DATA_LO ( s_data_lo   ),
                    .S_DATA_HI ( s_data_hi   ),
                    .S_ACK_LO  ( s_ack_lo    ),
                    .S_ACK_HI  ( s_ack_hi    ),
                    .S_START   ( s_start     ),
                    .S_STOP_LO ( s_stop_lo   ),
                    .S_STOP_HI ( s_stop_hi   ),
                    .S_IDLE    ( s_idle      ));

assign BUSY = ~s_idle;
assign l_scl = (s_data_lo | s_ack_lo | s_stop_lo) ? 1'b0 : 1'b1;


assign l_data = sreg_out | read_mode;
assign l_ack  = ~read_mode ^ (nack_hack & l_done);

assign l_sda = (s_start   | s_stop_lo | s_stop_hi ) ? 1'b0   :
               (s_data_lo | s_data_hi)              ? l_data :
               (s_ack_lo  | s_ack_hi )              ? l_ack  : 
                                                      1'b1;

ffds #(1) scl_fd(CLK, l_scl, scl_q);
ffds #(1) sda_fd(CLK, l_sda, sda_q);

assign SDA = sda_q ? 1'bZ : 1'b0;
assign SCL = scl_q ? 1'bZ : 1'b0;

endmodule