data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:15: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:17: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:53: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:59: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:65: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:71: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:77: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:83: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:86: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:95: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:111: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_ps_state.sv:114: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: Exiting due to 10 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_RC4_gen_ps_state();
	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end


	reg tb_n_reset_i;
	reg tb_genStateArr_i;
	reg tb_genVal_i;
	reg [7:0] tb_counterI_i;
	reg tb_sarrGenerated_o;
	reg tb_valReady_o;
	reg tb_clearCounterJ_o;
	reg tb_clear_i_o;
	reg tb_enable_counterI_o;
	reg tb_det_j_o;
	reg tb_swap_o;
	reg tb_det_j_2_o;
	reg tb_store_temp_o;

	reg tb_end_o;
	reg tb_gen_final_o;
	reg tb_val_init_o;
	
	RC4_gen_ps_state DUT (.clk(tb_clk),.n_rst_i(tb_n_reset_i),.genStateArr_i(tb_genStateArr_i),.genVal_i(tb_genVal_i),.counterI_i(tb_counterI_i),.sarrGenerated_o(tb_sarrGenerated_o)
				,.valReady_o(tb_valReady_o),.clearCounterJ_o(tb_clearCounterJ_o),.clear_i_o(tb_clear_i_o),.enable_counterI_o(tb_enable_counterI_o),
				.det_j_o(tb_det_j_o),.swap_o(tb_swap_o),.det_j_2_o(tb_det_j_2_o),.store_temp_o(tb_store_temp_o),.end_o(tb_end_o),
				.gen_final_o(tb_gen_final_o),.val_init_o(tb_val_init_o));

initial
begin



	tb_n_reset_i = 0;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_counterI_i = 0;
	@(negedge tb_clk);

	tb_n_reset_i = 1;
	tb_genStateArr_i = 1;
	tb_genVal_i = 0;
	tb_counterI_i = 0;
	@(negedge tb_clk);

	tb_n_reset_i = 1;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_counterI_i = 0;
	@(negedge tb_clk);

	tb_n_reset_i = 1;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_counterI_i = 1;
	@(negedge tb_clk);

	tb_n_reset_i = 1;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_counterI_i = 1;
	@(negedge tb_clk);

	tb_n_reset_i = 1;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_counterI_i = 255;
	@(negedge tb_clk);

	tb_counterI_i = 0;
	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	tb_counterI_i = 255;
	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	$info("Generation of one value");
	tb_genVal_i = 1;
	@(negedge tb_clk);
	tb_genVal_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);




end
endmodule
module tb_RC4_gen_ps_state();

	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end


	reg tb_n_reset_i;
	reg tb_genStateArr_i;
	reg tb_genVal_i;
	reg [7:0] tb_counterI_i;
	reg tb_sarrGenerated_o;
	reg tb_valReady_o;
	reg tb_clearCounterJ_o;
	reg tb_clear_i_o;
	reg tb_enable_counterI_o;
	reg tb_det_j_o;
	reg tb_swap_o;
	reg tb_det_j_2_o;
	reg tb_store_temp_o;

	reg tb_end_o;
	reg tb_gen_final_o;
	reg tb_val_init_o;
	
	RC4_gen_ps_state DUT (.clk(tb_clk),.n_rst_i(tb_n_reset_i),.genStateArr_i(tb_genStateArr_i),.genVal_i(tb_genVal_i),.counterI_i(tb_counterI_i),.sarrGenerated_o(tb_sarrGenerated_o)
				,.valReady_o(tb_valReady_o),.clearCounterJ_o(tb_clearCounterJ_o),.clear_i_o(tb_clear_i_o),.enable_counterI_o(tb_enable_counterI_o),
				.det_j_o(tb_det_j_o),.swap_o(tb_swap_o),.det_j_2_o(tb_det_j_2_o),.store_temp_o(tb_store_temp_o),.end_o(tb_end_o),
				.gen_final_o(tb_gen_final_o),.val_init_o(tb_val_init_o));

initial
begin



	tb_n_reset_i = 0;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_counterI_i = 0;
	@(negedge tb_clk);

	tb_n_reset_i = 1;
	tb_genStateArr_i = 1;
	tb_genVal_i = 0;
	tb_counterI_i = 0;
	@(negedge tb_clk);

	tb_n_reset_i = 1;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_counterI_i = 0;
	@(negedge tb_clk);

	tb_n_reset_i = 1;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_counterI_i = 1;
	@(negedge tb_clk);

	tb_n_reset_i = 1;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_counterI_i = 1;
	@(negedge tb_clk);

	tb_n_reset_i = 1;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_counterI_i = 255;
	@(negedge tb_clk);

	tb_counterI_i = 0;
	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	tb_counterI_i = 255;
	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	$info("Generation of one value");
	tb_genVal_i = 1;
	@(negedge tb_clk);
	tb_genVal_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);

	@(negedge tb_clk);




end
endmodule