data/full_repos/permissive/101171422/sim/trainsim.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #5 rst = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #1 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:169: Unsupported: Ignoring delay on this delayed statement.\n initial forever #0.5 clk = !clk;\n                 ^\n%Warning-INFINITELOOP: data/full_repos/permissive/101171422/sim/trainsim.v:169: Infinite loop (condition always true)\n                                                                              : ... In instance trainsim_test\n initial forever #0.5 clk = !clk;\n         ^~~~~~~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trainsim_test();
	reg        rst, clk;
	wire [7:0] rnd;
	wire [4:0] sensor;
	wire [2:0] sw;
	wire [1:0] dira, dirb;
	
	initial begin
		clk = 0;
		#5 rst = 1;
		#1 rst = 0;
	end
		
	initial forever #0.5 clk = !clk;
	
	assign sensor = rnd[4:0];
	
	LFSR8_11D l(clk, rnd);
	trainsim t(rst, clk, sensor, sw, dira, dirb);
	
endmodule
module trainsim_test();

	reg        rst, clk;
	wire [7:0] rnd;
	wire [4:0] sensor;
	wire [2:0] sw;
	wire [1:0] dira, dirb;
	
	initial begin
		clk = 0;
		#5 rst = 1;
		#1 rst = 0;
	end
		
	initial forever #0.5 clk = !clk;
	
	assign sensor = rnd[4:0];
	
	LFSR8_11D l(clk, rnd);
	trainsim t(rst, clk, sensor, sw, dira, dirb);
	
endmodule