data/full_repos/permissive/109936328/pipe_util/alu.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:10: Cannot find include file: alu_op.vh\n  `include "alu_op.vh" \n           ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/pipe_util,data/full_repos/permissive/109936328/alu_op.vh\n             data/full_repos/permissive/109936328/pipe_util,data/full_repos/permissive/109936328/alu_op.vh.v\n             data/full_repos/permissive/109936328/pipe_util,data/full_repos/permissive/109936328/alu_op.vh.sv\n             alu_op.vh\n             alu_op.vh.v\n             alu_op.vh.sv\n             obj_dir/alu_op.vh\n             obj_dir/alu_op.vh.v\n             obj_dir/alu_op.vh.sv\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:13: Define or directive not defined: \'`ALU_OP_W\'\n  localparam ALU_OP_W = `ALU_OP_W;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:13: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam ALU_OP_W = `ALU_OP_W;\n                                 ^\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:27: Define or directive not defined: \'`ALU_ADD\'\n      `ALU_ADD: eval = opp_a + opp_b;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:27: syntax error, unexpected \':\', expecting endcase\n      `ALU_ADD: eval = opp_a + opp_b;\n              ^\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:28: Define or directive not defined: \'`ALU_SUB\'\n      `ALU_SUB: eval = opp_a - opp_b;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:29: Define or directive not defined: \'`ALU_AND\'\n      `ALU_AND: eval = opp_a & opp_b;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:30: Define or directive not defined: \'`ALU_OR\'\n      `ALU_OR: eval = opp_a | opp_b;\n      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:31: Define or directive not defined: \'`ALU_XOR\'\n      `ALU_XOR: eval = opp_a ^ opp_b;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:32: Define or directive not defined: \'`ALU_SLT\'\n      `ALU_SLT: eval = $signed(opp_a) < $signed(opp_b);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:33: Define or directive not defined: \'`ALU_SLTU\'\n      `ALU_SLTU: eval = opp_a < opp_b;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:34: Define or directive not defined: \'`ALU_SGE\'\n      `ALU_SGE: eval = $signed(opp_a) >= $signed(opp_b);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:35: Define or directive not defined: \'`ALU_SGEU\'\n      `ALU_SGEU: eval = opp_a >= opp_b;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/alu.v:36: Define or directive not defined: \'`ALU_SNE\'\n      `ALU_SNE: eval = opp_a != opp_b;\n      ^~~~~~~~\n%Error: Cannot continue\n'
module alu(
  opp_a,
  opp_b,

  op,

  eval,
  zero
);
  `include "alu_op.vh"

  parameter DATA_W = 32;
  localparam ALU_OP_W = `ALU_OP_W;

  input [DATA_W - 1:0] opp_a;
  input [DATA_W - 1:0] opp_b;

  input [ALU_OP_W - 1:0] op;

  output reg [DATA_W - 1:0] eval;
  output zero;

  assign zero = (eval == 0);

  always@(*) begin
    case(op)
      `ALU_ADD: eval = opp_a + opp_b;
      `ALU_SUB: eval = opp_a - opp_b;
      `ALU_AND: eval = opp_a & opp_b;
      `ALU_OR: eval = opp_a | opp_b;
      `ALU_XOR: eval = opp_a ^ opp_b;
      `ALU_SLT: eval = $signed(opp_a) < $signed(opp_b);
      `ALU_SLTU: eval = opp_a < opp_b;
      `ALU_SGE: eval = $signed(opp_a) >= $signed(opp_b);
      `ALU_SGEU: eval = opp_a >= opp_b;
      `ALU_SNE: eval = opp_a != opp_b;
      default: eval = 0;
    endcase
  end

endmodule
module alu(
  opp_a,
  opp_b,

  op,

  eval,
  zero
);

  `include "alu_op.vh"

  parameter DATA_W = 32;
  localparam ALU_OP_W = `ALU_OP_W;

  input [DATA_W - 1:0] opp_a;
  input [DATA_W - 1:0] opp_b;

  input [ALU_OP_W - 1:0] op;

  output reg [DATA_W - 1:0] eval;
  output zero;

  assign zero = (eval == 0);

  always@(*) begin
    case(op)
      `ALU_ADD: eval = opp_a + opp_b;
      `ALU_SUB: eval = opp_a - opp_b;
      `ALU_AND: eval = opp_a & opp_b;
      `ALU_OR: eval = opp_a | opp_b;
      `ALU_XOR: eval = opp_a ^ opp_b;
      `ALU_SLT: eval = $signed(opp_a) < $signed(opp_b);
      `ALU_SLTU: eval = opp_a < opp_b;
      `ALU_SGE: eval = $signed(opp_a) >= $signed(opp_b);
      `ALU_SGEU: eval = opp_a >= opp_b;
      `ALU_SNE: eval = opp_a != opp_b;
      default: eval = 0;
    endcase
  end

endmodule