data/full_repos/permissive/211316121/lab8_1/RAM.v
data/verilator_xmls/5b6ce63a-5309-4219-a4c9-4264290deb83.xml
module _74LS377(
    input clk,
    input en,
    input [3:0] d,
    output reg [3:0] q
);
always@(posedge clk)
    if (en)
        q<=q;
    else
        q<=d;
endmodule
module _74LS377(
    input clk,
    input en,
    input [3:0] d,
    output reg [3:0] q
);

always@(posedge clk)
    if (en)
        q<=q;
    else
        q<=d;
endmodule