data/full_repos/permissive/167274925/MEWBReg.v
data/verilator_xmls/2f84f0c9-40dc-493e-89d5-c93958722fe7.xml
module MEWBReg(Reset,Clk,in,out);
input Reset;
input Clk;
input [142:0]in;
output reg [142:0]out;
always@(posedge Clk)begin 
if(Reset)begin
out<=143'd0; 
end 
else begin 
out<=in; 
end 

end 
endmodule
module MEWBReg(Reset,Clk,in,out);

input Reset;
input Clk;
input [142:0]in;
output reg [142:0]out;
always@(posedge Clk)begin 
if(Reset)begin
out<=143'd0; 
end 
else begin 
out<=in; 
end 

end 
endmodule