data/full_repos/permissive/146246005/Sequence Controller/SeqConTB.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: Controller,data/full_repos/permissive/146246005\n        ... Looked in:\n             data/full_repos/permissive/146246005/Sequence/Controller,data/full_repos/permissive/146246005\n             data/full_repos/permissive/146246005/Sequence/Controller,data/full_repos/permissive/146246005.v\n             data/full_repos/permissive/146246005/Sequence/Controller,data/full_repos/permissive/146246005.sv\n             Controller,data/full_repos/permissive/146246005\n             Controller,data/full_repos/permissive/146246005.v\n             Controller,data/full_repos/permissive/146246005.sv\n             obj_dir/Controller,data/full_repos/permissive/146246005\n             obj_dir/Controller,data/full_repos/permissive/146246005.v\n             obj_dir/Controller,data/full_repos/permissive/146246005.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/Sequence\n%Error: Cannot find file containing module: Controller/SeqConTB.sv\n%Error: Exiting due to 3 error(s)\n'
module toplevel_tb();

	reg [6:0] ADDR;
	reg I_FLAG,ZF,NF,OF,CF,RST,CLK,EN;
	wire IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS;
	enum reg[3:0] {LOAD, STORE, ADD, SUB, AND, OR, XOR, NOT, B, BZ, BN, BV, BC} OPCODE;

	toplevel UUT(ADDR,OPCODE,I_FLAG,ZF,NF,OF,CF,IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS,CLK,RST,EN);


initial
begin
	CLK=1'b0;
forever #10 CLK=~CLK;
end

initial
begin
  $monitor("OUTPUTS: %d ns\tIR_EN=%d A_EN=%d B_EN=%d PDR_EN=%d PORT_EN=%d PORT_RD=%d PC_EN=%d PC_LOAD=%d ALU_EN=%d ALU_OE=%d RAM_OE=%d RDR_EN=%d RAM_CS=%d",$time,IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS);
    $vcdpluson;


end

initial begin
  $monitoroff;
	RST = 1'b0; ADDR = 64; CF = 0; OF = 0; NF = 0; ZF = 0; I_FLAG = 1; OPCODE = 0; EN=1'b0;
	#10 RST = 1'b1; 
	#110 $monitoron;
	#70 ADDR = 65;
	#80 ADDR = 66;
	#80 ADDR = 67;
	#80 I_FLAG = 0; ADDR = 64;
	#80 OPCODE = 1; ADDR = 64;
	#80 OPCODE = 1; ADDR = 67;
	#80 OPCODE = 2;
	#80 OPCODE = 8; CF = 0; OF = 0; NF = 0; ZF = 0;
	#80 OPCODE = 9;
	#80 OPCODE = 10;
	#80 OPCODE = 11;
	#80 OPCODE = 12;
	$finish;
end
endmodule
module toplevel_tb();


	reg [6:0] ADDR;
	reg I_FLAG,ZF,NF,OF,CF,RST,CLK,EN;
	wire IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS;
	enum reg[3:0] {LOAD, STORE, ADD, SUB, AND, OR, XOR, NOT, B, BZ, BN, BV, BC} OPCODE;

	toplevel UUT(ADDR,OPCODE,I_FLAG,ZF,NF,OF,CF,IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS,CLK,RST,EN);


initial
begin
	CLK=1'b0;
forever #10 CLK=~CLK;
end

initial
begin
  $monitor("OUTPUTS: %d ns\tIR_EN=%d A_EN=%d B_EN=%d PDR_EN=%d PORT_EN=%d PORT_RD=%d PC_EN=%d PC_LOAD=%d ALU_EN=%d ALU_OE=%d RAM_OE=%d RDR_EN=%d RAM_CS=%d",$time,IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS);
    $vcdpluson;


end

initial begin
  $monitoroff;
	RST = 1'b0; ADDR = 64; CF = 0; OF = 0; NF = 0; ZF = 0; I_FLAG = 1; OPCODE = 0; EN=1'b0;
	#10 RST = 1'b1; 
	#110 $monitoron;
	#70 ADDR = 65;
	#80 ADDR = 66;
	#80 ADDR = 67;
	#80 I_FLAG = 0; ADDR = 64;
	#80 OPCODE = 1; ADDR = 64;
	#80 OPCODE = 1; ADDR = 67;
	#80 OPCODE = 2;
	#80 OPCODE = 8; CF = 0; OF = 0; NF = 0; ZF = 0;
	#80 OPCODE = 9;
	#80 OPCODE = 10;
	#80 OPCODE = 11;
	#80 OPCODE = 12;
	$finish;
end
endmodule