data/full_repos/permissive/151044151/Reconf_S6LX45.v
 line:11: before: "("
1: b"%Error: data/full_repos/permissive/151044151/Reconf_S6LX45.v:65: Cannot find file containing module: 'ICAP_SPARTAN6'\nICAP_SPARTAN6 #(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151044151,data/full_repos/permissive/151044151/ICAP_SPARTAN6\n             data/full_repos/permissive/151044151,data/full_repos/permissive/151044151/ICAP_SPARTAN6.v\n             data/full_repos/permissive/151044151,data/full_repos/permissive/151044151/ICAP_SPARTAN6.sv\n             ICAP_SPARTAN6\n             ICAP_SPARTAN6.v\n             ICAP_SPARTAN6.sv\n             obj_dir/ICAP_SPARTAN6\n             obj_dir/ICAP_SPARTAN6.v\n             obj_dir/ICAP_SPARTAN6.sv\n%Error: Exiting due to 1 error(s)\n"
module RECONF_S6LX45
(
	input 		 RESET,
	input			 CLK,
	input			 START,
	input [23:0] BSADRi
);
`define DEVID	32'h04008093

reg [23:0] BSADR;
function [15:0] ReconfSeq (input [3:0] A);
`define	OPC 8'h0B
	case(A)
	4'h0: ReconfSeq = 16'hFFFF;
	4'h1: ReconfSeq = 16'hAA99;
	4'h2: ReconfSeq = 16'h5566;

	4'h3: ReconfSeq = 16'h3261;
	4'h4: ReconfSeq = BSADR[15:0];
	4'h5: ReconfSeq = 16'h3281;
	4'h6: ReconfSeq = {`OPC,BSADR[23:16]};

	4'h7: ReconfSeq = 16'h32A1;
	4'h8: ReconfSeq = BSADR[15:0];
	4'h9: ReconfSeq = 16'h32C1;
	4'hA: ReconfSeq = {`OPC,BSADR[23:16]};
	
	4'hB: ReconfSeq = 16'h30A1;
	4'hC: ReconfSeq = 16'h000E;
	4'hD: ReconfSeq = 16'h2000;

	default: ReconfSeq = 16'h2000;
	endcase
endfunction

reg        ACTIVE = 0;
reg		  RCENB = 0;
reg [ 3:0] RCADR = 0;
reg [15:0] RCSEQ = 0;
always @(negedge CLK or posedge RESET) begin
	if (RESET) begin
		ACTIVE <= 0;
		 RCADR <= 0;
		 RCSEQ <= 0;
		 RCENB <= 0;
	end
	else begin
		if (ACTIVE) begin
			RCSEQ <= ReconfSeq(RCADR);
			RCADR <= (RCADR!=15) ? (RCADR+1) : RCADR;
			RCENB <= (RCADR!=15);
		end
		else if (START) begin
			ACTIVE <= 1'b1;
			BSADR  <= BSADRi;
		end
	end
end
wire [15:0] RCSQD = {
	RCSEQ[ 8],RCSEQ[ 9],RCSEQ[10],RCSEQ[11],RCSEQ[12],RCSEQ[13],RCSEQ[14],RCSEQ[15],
	RCSEQ[ 0],RCSEQ[ 1],RCSEQ[ 2],RCSEQ[ 3],RCSEQ[ 4],RCSEQ[ 5],RCSEQ[ 6],RCSEQ[ 7]
};


ICAP_SPARTAN6 #(
	.DEVICE_ID(`DEVID)
)
reconf (
	.BUSY(),
	.O(),
	.CE(~RCENB),
	.CLK(CLK),
	.I(RCSQD),
	.WRITE(1'b0)
);

endmodule
module RECONF_S6LX45
(
	input 		 RESET,
	input			 CLK,
	input			 START,
	input [23:0] BSADRi
);

`define DEVID	32'h04008093

reg [23:0] BSADR;
function [15:0] ReconfSeq (input [3:0] A);
`define	OPC 8'h0B
	case(A)
	4'h0: ReconfSeq = 16'hFFFF;
	4'h1: ReconfSeq = 16'hAA99;
	4'h2: ReconfSeq = 16'h5566;

	4'h3: ReconfSeq = 16'h3261;
	4'h4: ReconfSeq = BSADR[15:0];
	4'h5: ReconfSeq = 16'h3281;
	4'h6: ReconfSeq = {`OPC,BSADR[23:16]};

	4'h7: ReconfSeq = 16'h32A1;
	4'h8: ReconfSeq = BSADR[15:0];
	4'h9: ReconfSeq = 16'h32C1;
	4'hA: ReconfSeq = {`OPC,BSADR[23:16]};
	
	4'hB: ReconfSeq = 16'h30A1;
	4'hC: ReconfSeq = 16'h000E;
	4'hD: ReconfSeq = 16'h2000;

	default: ReconfSeq = 16'h2000;
	endcase
endfunction

reg        ACTIVE = 0;
reg		  RCENB = 0;
reg [ 3:0] RCADR = 0;
reg [15:0] RCSEQ = 0;
always @(negedge CLK or posedge RESET) begin
	if (RESET) begin
		ACTIVE <= 0;
		 RCADR <= 0;
		 RCSEQ <= 0;
		 RCENB <= 0;
	end
	else begin
		if (ACTIVE) begin
			RCSEQ <= ReconfSeq(RCADR);
			RCADR <= (RCADR!=15) ? (RCADR+1) : RCADR;
			RCENB <= (RCADR!=15);
		end
		else if (START) begin
			ACTIVE <= 1'b1;
			BSADR  <= BSADRi;
		end
	end
end
wire [15:0] RCSQD = {
	RCSEQ[ 8],RCSEQ[ 9],RCSEQ[10],RCSEQ[11],RCSEQ[12],RCSEQ[13],RCSEQ[14],RCSEQ[15],
	RCSEQ[ 0],RCSEQ[ 1],RCSEQ[ 2],RCSEQ[ 3],RCSEQ[ 4],RCSEQ[ 5],RCSEQ[ 6],RCSEQ[ 7]
};


ICAP_SPARTAN6 #(
	.DEVICE_ID(`DEVID)
)
reconf (
	.BUSY(),
	.O(),
	.CE(~RCENB),
	.CLK(CLK),
	.I(RCSQD),
	.WRITE(1'b0)
);

endmodule