data/full_repos/permissive/132439949/sources_1/new/gen_delay.v
1: b'%Warning-WIDTH: data/full_repos/permissive/132439949/sources_1/new/gen_delay.v:37: Bit extraction of array[9999:0] requires 14 bit index, not 26 bits.\n                                                                                 : ... In instance gen_delay\n            memory[i] <= data_in;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/132439949/sources_1/new/gen_delay.v:46: Bit extraction of array[9999:0] requires 14 bit index, not 26 bits.\n                                                                                 : ... In instance gen_delay\n            data_out <= memory[j];\n                              ^\n%Error: Exiting due to 2 warning(s)\n'
module gen_delay(
    input CLOCK,
    input [11:0] data_in,
    output reg [11:0] data_out
    );
    
    initial begin
       data_out = 12'b0;
    end
        
    reg [25:0] i = 0;
    reg [11:0] memory [0:9999];
    
    always @ (posedge CLOCK) begin
            memory[i] <= data_in;
            i <= (i==9999) ? 0 : i+1;
    end
        
        

    reg [25:0] j = 1; 

    always @ (posedge CLOCK) begin
            data_out <= memory[j];
            j <= (j==9999) ? 0 : j+1;
    end
    
endmodule
module gen_delay(
    input CLOCK,
    input [11:0] data_in,
    output reg [11:0] data_out
    );

    
    initial begin
       data_out = 12'b0;
    end
        
    reg [25:0] i = 0;
    reg [11:0] memory [0:9999];
    
    always @ (posedge CLOCK) begin
            memory[i] <= data_in;
            i <= (i==9999) ? 0 : i+1;
    end
        
        

    reg [25:0] j = 1; 

    always @ (posedge CLOCK) begin
            data_out <= memory[j];
            j <= (j==9999) ? 0 : j+1;
    end
    
endmodule