data/full_repos/permissive/108698528/ram.v
 line:47: before: "/"
data/verilator_xmls/1bc899f4-8fd1-4c1a-8d09-2f8b7b6fa9c7.xml
module simple_ram(mem_bus_in, mem_bus_out, address, r_e, w_e, clk);


	parameter BYTE_W = 8;
	parameter ADDR_W = 8;
	parameter NUM_ADDR = 1 << ADDR_W;

	input [BYTE_W - 1:0] mem_bus_in;
	output reg [BYTE_W - 1:0] mem_bus_out;
	input [ADDR_W - 1:0] address;
	input r_e, w_e;
	input clk;
	tri [BYTE_W - 1: 0] mem_bus;
	reg [BYTE_W - 1:0] mem_storage [0:NUM_ADDR - 1];








	always @(posedge clk) begin
		if(w_e) mem_storage[address] <= mem_bus_in;
		else if(r_e) mem_bus_out <= mem_storage[address];
		else mem_bus_out <= 0;
	end
	
endmodule
module simple_ram(mem_bus_in, mem_bus_out, address, r_e, w_e, clk);



	parameter BYTE_W = 8;
	parameter ADDR_W = 8;
	parameter NUM_ADDR = 1 << ADDR_W;

	input [BYTE_W - 1:0] mem_bus_in;
	output reg [BYTE_W - 1:0] mem_bus_out;
	input [ADDR_W - 1:0] address;
	input r_e, w_e;
	input clk;
	tri [BYTE_W - 1: 0] mem_bus;
	reg [BYTE_W - 1:0] mem_storage [0:NUM_ADDR - 1];








	always @(posedge clk) begin
		if(w_e) mem_storage[address] <= mem_bus_in;
		else if(r_e) mem_bus_out <= mem_storage[address];
		else mem_bus_out <= 0;
	end
	
endmodule