data/full_repos/permissive/136610640/soc_system/submodules/alt_vipitc130_common_sample_counter.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/136610640/soc_system/submodules/alt_vipitc130_common_sample_counter.v:16: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks);\n                ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/136610640/soc_system/submodules/alt_vipitc130_common_sample_counter.v:24: Little bit endian vector: MSB < LSB of bit range: -1:0\n        reg [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] count_valids;\n            ^\n%Error: data/full_repos/permissive/136610640/soc_system/submodules/alt_vipitc130_common_sample_counter.v:31: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                                                           : ... In instance alt_vipitc130_common_sample_counter\n                count_valids <= {LOG2_NUMBER_OF_COLOUR_PLANES{1\'b0}};\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/136610640/soc_system/submodules/alt_vipitc130_common_sample_counter.v:31: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n                                                                                                                   : ... In instance alt_vipitc130_common_sample_counter\n                count_valids <= {LOG2_NUMBER_OF_COLOUR_PLANES{1\'b0}};\n                             ^~\n%Error: Internal Error: data/full_repos/permissive/136610640/soc_system/submodules/alt_vipitc130_common_sample_counter.v:34: ../V3Width.cpp:3809: Under node REPLICATE has no expected width?? Missing Visitor func?\n                                                                                                                           : ... In instance alt_vipitc130_common_sample_counter\n                    count_valids <= {{LOG2_NUMBER_OF_COLOUR_PLANES-1{1\'b0}}, count_cycle};\n                                    ^\n'
module alt_vipitc130_common_sample_counter
    #(parameter
        NUMBER_OF_COLOUR_PLANES = 0,
        COLOUR_PLANES_ARE_IN_PARALLEL = 0,
        LOG2_NUMBER_OF_COLOUR_PLANES = 0)
    (
    input wire rst,
    input wire clk, 
    input wire sclr,
    
    input wire count_cycle,
    input wire hd_sdn,
    
    output wire count_sample,
    output wire start_of_sample,
    output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks);

generate
    if(NUMBER_OF_COLOUR_PLANES == 1) begin
        assign count_sample = count_cycle;
        assign start_of_sample = 1'b1;
        assign sample_ticks = 1'b0;
    end else begin
        reg [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] count_valids;
        wire new_sample;
        
        assign new_sample = count_valids == (NUMBER_OF_COLOUR_PLANES - 1);
        
        always @ (posedge rst or posedge clk) begin
            if(rst) begin
                count_valids <= {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}};
            end else begin
                if(sclr)
                    count_valids <= {{LOG2_NUMBER_OF_COLOUR_PLANES-1{1'b0}}, count_cycle};
                else
                    count_valids <= (count_cycle) ? (new_sample) ? {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}} : count_valids + 1 : count_valids;
            end
        end
        
        assign count_sample = (hd_sdn) ? count_cycle : count_cycle & new_sample; 
        assign start_of_sample = (hd_sdn) ? 1'b1 : (count_valids == {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}});
        assign sample_ticks = count_valids;
    end
endgenerate

endmodule
module alt_vipitc130_common_sample_counter
    #(parameter
        NUMBER_OF_COLOUR_PLANES = 0,
        COLOUR_PLANES_ARE_IN_PARALLEL = 0,
        LOG2_NUMBER_OF_COLOUR_PLANES = 0)
    (
    input wire rst,
    input wire clk, 
    input wire sclr,
    
    input wire count_cycle,
    input wire hd_sdn,
    
    output wire count_sample,
    output wire start_of_sample,
    output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks);


generate
    if(NUMBER_OF_COLOUR_PLANES == 1) begin
        assign count_sample = count_cycle;
        assign start_of_sample = 1'b1;
        assign sample_ticks = 1'b0;
    end else begin
        reg [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] count_valids;
        wire new_sample;
        
        assign new_sample = count_valids == (NUMBER_OF_COLOUR_PLANES - 1);
        
        always @ (posedge rst or posedge clk) begin
            if(rst) begin
                count_valids <= {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}};
            end else begin
                if(sclr)
                    count_valids <= {{LOG2_NUMBER_OF_COLOUR_PLANES-1{1'b0}}, count_cycle};
                else
                    count_valids <= (count_cycle) ? (new_sample) ? {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}} : count_valids + 1 : count_valids;
            end
        end
        
        assign count_sample = (hd_sdn) ? count_cycle : count_cycle & new_sample; 
        assign start_of_sample = (hd_sdn) ? 1'b1 : (count_valids == {LOG2_NUMBER_OF_COLOUR_PLANES{1'b0}});
        assign sample_ticks = count_valids;
    end
endgenerate

endmodule