data/full_repos/permissive/122125962/hardware/SDRv2_src_asyn_rst_apb/max2831_spi.v
None: at end of input
1: b"%Error: data/full_repos/permissive/122125962/hardware/SDRv2_src_asyn_rst_apb/max2831_spi.v:72: Cannot find file containing module: 'spi_tx'\nspi_tx t0(.clk(PCLK), .resetn(PRESETn), .data_in(data_reg), .start(spi_start), .data_out(DATOUT), .clk_out(CLKOUT), .en_out(ENOUT));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122125962/hardware/SDRv2_src_asyn_rst_apb,data/full_repos/permissive/122125962/spi_tx\n             data/full_repos/permissive/122125962/hardware/SDRv2_src_asyn_rst_apb,data/full_repos/permissive/122125962/spi_tx.v\n             data/full_repos/permissive/122125962/hardware/SDRv2_src_asyn_rst_apb,data/full_repos/permissive/122125962/spi_tx.sv\n             spi_tx\n             spi_tx.v\n             spi_tx.sv\n             obj_dir/spi_tx\n             obj_dir/spi_tx.v\n             obj_dir/spi_tx.sv\n%Error: Exiting due to 1 error(s)\n"
module max2831_spi(	

	input	PCLK,
	input	PRESETn, 
	input	[31:0] PADDR, 
	input	PSELx, 
	input	PENABLE,
	input	PWRITE, 
	input	[31:0] PWDATA, 
	output	reg PREADY, 
	output	[31:0] PRDATA,
	output	PSLVERR,

	output	DATOUT, 
	output	CLKOUT, 
	output	ENOUT,
					
	input	rx_agc_sel, 
	input	[6:0] rx_gain, 
	output	reg rx_gain_rdy, 
	output	reg rx_agc_data_got
);

assign PSLVERR = 1'b0;

reg		[6:0] rx_gain_dat;

reg		spi_start;

reg		[2:0]	fsm;
reg		[17:0]	data_reg;


assign	PRDATA		= {14'b0, data_reg};

spi_tx t0(.clk(PCLK), .resetn(PRESETn), .data_in(data_reg), .start(spi_start), .data_out(DATOUT), .clk_out(CLKOUT), .en_out(ENOUT));

always @ (posedge PCLK or negedge PRESETn)
begin
    if (~PRESETn)
    begin
		fsm			<= 0;
		data_reg    <= 0;
		PREADY		<= 0;
		rx_gain_dat	<= 0;
		rx_gain_rdy <= 1;
		rx_agc_data_got <= 0;
    end
    else
    begin
		case (fsm)
		    0:
		    begin
				if (PSELx & PENABLE)
					fsm				<= 1;
				else if (rx_agc_sel)
				begin
					fsm				<= 1;
					rx_gain_dat		<= rx_gain;
					rx_agc_data_got	<= 1;
				end
		    end
		    
		    1:
		    begin
				rx_gain_rdy	<= 0;
				if (PWRITE | rx_agc_data_got)
				begin
					spi_start	<= 1;
					if (rx_agc_data_got)
						data_reg <= {7'b0, rx_gain_dat, 4'b1011};
					else
						data_reg <= {PWDATA[13:0], PADDR[5:2]};
					fsm <= 2;
				end
				else
				begin
					fsm <= 3;
				end

			end

			2:
			begin
				if (ENOUT==0)
				begin
					spi_start <= 0;
					fsm <= 3;
				end
			end

			3:
			begin
                if (ENOUT==1)
                begin
					rx_gain_rdy <= 1;
					if (rx_agc_data_got)
					begin
						rx_agc_data_got	<= 0;
						fsm <= 0;
					end
					else
					begin
						PREADY <= 1;
						fsm <= 4;
					end
                end
			end

			4:
			begin
				if (~PSELx)
				begin
					PREADY <= 0;
					fsm <= 0;
				end
			end
		
		endcase
    end
end

endmodule
module max2831_spi(	

	input	PCLK,
	input	PRESETn, 
	input	[31:0] PADDR, 
	input	PSELx, 
	input	PENABLE,
	input	PWRITE, 
	input	[31:0] PWDATA, 
	output	reg PREADY, 
	output	[31:0] PRDATA,
	output	PSLVERR,

	output	DATOUT, 
	output	CLKOUT, 
	output	ENOUT,
					
	input	rx_agc_sel, 
	input	[6:0] rx_gain, 
	output	reg rx_gain_rdy, 
	output	reg rx_agc_data_got
);


assign PSLVERR = 1'b0;

reg		[6:0] rx_gain_dat;

reg		spi_start;

reg		[2:0]	fsm;
reg		[17:0]	data_reg;


assign	PRDATA		= {14'b0, data_reg};

spi_tx t0(.clk(PCLK), .resetn(PRESETn), .data_in(data_reg), .start(spi_start), .data_out(DATOUT), .clk_out(CLKOUT), .en_out(ENOUT));

always @ (posedge PCLK or negedge PRESETn)
begin
    if (~PRESETn)
    begin
		fsm			<= 0;
		data_reg    <= 0;
		PREADY		<= 0;
		rx_gain_dat	<= 0;
		rx_gain_rdy <= 1;
		rx_agc_data_got <= 0;
    end
    else
    begin
		case (fsm)
		    0:
		    begin
				if (PSELx & PENABLE)
					fsm				<= 1;
				else if (rx_agc_sel)
				begin
					fsm				<= 1;
					rx_gain_dat		<= rx_gain;
					rx_agc_data_got	<= 1;
				end
		    end
		    
		    1:
		    begin
				rx_gain_rdy	<= 0;
				if (PWRITE | rx_agc_data_got)
				begin
					spi_start	<= 1;
					if (rx_agc_data_got)
						data_reg <= {7'b0, rx_gain_dat, 4'b1011};
					else
						data_reg <= {PWDATA[13:0], PADDR[5:2]};
					fsm <= 2;
				end
				else
				begin
					fsm <= 3;
				end

			end

			2:
			begin
				if (ENOUT==0)
				begin
					spi_start <= 0;
					fsm <= 3;
				end
			end

			3:
			begin
                if (ENOUT==1)
                begin
					rx_gain_rdy <= 1;
					if (rx_agc_data_got)
					begin
						rx_agc_data_got	<= 0;
						fsm <= 0;
					end
					else
					begin
						PREADY <= 1;
						fsm <= 4;
					end
                end
			end

			4:
			begin
				if (~PSELx)
				begin
					PREADY <= 0;
					fsm <= 0;
				end
			end
		
		endcase
    end
end

endmodule