data/full_repos/permissive/201488448/1_verilog/40_adder100.v
data/verilator_xmls/115abbde-6d6a-4941-a67f-9d86dc3a9547.xml
module add1 ( input a, input b, input cin,   output sum, output cout );
	assign	sum = a^b^cin;
    assign	cout = a&b | a&cin | b&cin;
endmodule
module add1 ( input a, input b, input cin,   output sum, output cout );

	assign	sum = a^b^cin;
    assign	cout = a&b | a&cin | b&cin;
endmodule