data/full_repos/permissive/128497744/fsm_calculator_part3/Full_Calculator/Full_Calculator.srcs/sources_1/new/mux4.v
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data/verilator_xmls/544a4ae2-68b8-4bc2-97d3-334772246ce7.xml
module MUX4 #(parameter Data_width = 4)(
input [Data_width - 1:0] d0, d1, d2, d3,
input [1:0] sel,
output reg [Data_width - 1:0] out 
);

always @ (d0, d1, d2, d3, sel)
begin
       case (sel)
            2'b00: out <= d0;
            2'b01: out <= d1;
            2'b10: out <= d2;
            2'b11: out <= d3;
        endcase
end
endmodule
module MUX4 #(parameter Data_width = 4)(
input [Data_width - 1:0] d0, d1, d2, d3,
input [1:0] sel,
output reg [Data_width - 1:0] out 
);


always @ (d0, d1, d2, d3, sel)
begin
       case (sel)
            2'b00: out <= d0;
            2'b01: out <= d1;
            2'b10: out <= d2;
            2'b11: out <= d3;
        endcase
end
endmodule