data/full_repos/permissive/129973551/work2/mult.sv
None: at end of input
1: b"%Error: data/full_repos/permissive/129973551/work2/mult.sv:45: Cannot find file containing module: 'mult3_ctl'\nmult3_ctl mult3_ctl_0(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129973551/work2,data/full_repos/permissive/129973551/mult3_ctl\n             data/full_repos/permissive/129973551/work2,data/full_repos/permissive/129973551/mult3_ctl.v\n             data/full_repos/permissive/129973551/work2,data/full_repos/permissive/129973551/mult3_ctl.sv\n             mult3_ctl\n             mult3_ctl.v\n             mult3_ctl.sv\n             obj_dir/mult3_ctl\n             obj_dir/mult3_ctl.v\n             obj_dir/mult3_ctl.sv\n%Error: Exiting due to 1 error(s)\n"
module mult(
	input reset,
	input clk,
	input [31:0] a_in,
	input [31:0] b_in,
	input start,
	output logic [63:0] product,
	output logic done);

logic [31:0] reg_a;
logic [31:0] prod_reg_high;
logic [31:0] prod_reg_low;
logic prod_reg_ld_high;
logic prod_reg_shift_rt;
logic [4:0] cycle_cnt;


assign product = {prod_reg_high, prod_reg_low};


always_ff @(posedge clk, posedge reset) begin
	if (reset)		reg_a <= '0;
	else if(start)	reg_a <= a_in;
end


always_ff @(posedge clk, posedge reset) begin
	unique if (reset)			prod_reg_high <= '0;
	else if (start)				prod_reg_high <= '0;
	else if (prod_reg_ld_high)	prod_reg_high <= reg_a + prod_reg_high;
	else if (prod_reg_shift_rt)	prod_reg_high <= {1'b0, prod_reg_high[31:1]};
	else						prod_reg_high <= prod_reg_high;
end


always_ff @(posedge clk, posedge reset) begin
	unique if (reset)			prod_reg_low <= '0;
	else if (start)				prod_reg_low <= b_in;
	else if (prod_reg_shift_rt) prod_reg_low <= {prod_reg_high[0], prod_reg_low[31:1]};
	else						prod_reg_low <= prod_reg_low;
end


mult3_ctl mult3_ctl_0(
	. reset 			( reset ) ,
	. clk 				( clk ),
	. start 			( start ) ,
	. multiplier_bit0 	( prod_reg_low [0] ) ,
	. prod_reg_ld_high 	( prod_reg_ld_high ),
	. prod_reg_shift_rt ( prod_reg_shift_rt ),
	. done 				( done ));

endmodule
module mult(
	input reset,
	input clk,
	input [31:0] a_in,
	input [31:0] b_in,
	input start,
	output logic [63:0] product,
	output logic done);


logic [31:0] reg_a;
logic [31:0] prod_reg_high;
logic [31:0] prod_reg_low;
logic prod_reg_ld_high;
logic prod_reg_shift_rt;
logic [4:0] cycle_cnt;


assign product = {prod_reg_high, prod_reg_low};


always_ff @(posedge clk, posedge reset) begin
	if (reset)		reg_a <= '0;
	else if(start)	reg_a <= a_in;
end


always_ff @(posedge clk, posedge reset) begin
	unique if (reset)			prod_reg_high <= '0;
	else if (start)				prod_reg_high <= '0;
	else if (prod_reg_ld_high)	prod_reg_high <= reg_a + prod_reg_high;
	else if (prod_reg_shift_rt)	prod_reg_high <= {1'b0, prod_reg_high[31:1]};
	else						prod_reg_high <= prod_reg_high;
end


always_ff @(posedge clk, posedge reset) begin
	unique if (reset)			prod_reg_low <= '0;
	else if (start)				prod_reg_low <= b_in;
	else if (prod_reg_shift_rt) prod_reg_low <= {prod_reg_high[0], prod_reg_low[31:1]};
	else						prod_reg_low <= prod_reg_low;
end


mult3_ctl mult3_ctl_0(
	. reset 			( reset ) ,
	. clk 				( clk ),
	. start 			( start ) ,
	. multiplier_bit0 	( prod_reg_low [0] ) ,
	. prod_reg_ld_high 	( prod_reg_ld_high ),
	. prod_reg_shift_rt ( prod_reg_shift_rt ),
	. done 				( done ));

endmodule