data/full_repos/permissive/216615048/src/simulation/mux_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/mux_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/216615048/src/simulation/mux_tb.v:28: Cannot find file containing module: \'multiplexer\'\nmultiplexer mtb(a,b,sel,out);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/multiplexer\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/multiplexer.v\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/multiplexer.sv\n             multiplexer\n             multiplexer.v\n             multiplexer.sv\n             obj_dir/multiplexer\n             obj_dir/multiplexer.v\n             obj_dir/multiplexer.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_tb();
reg [31:0]a;
reg [31:0]b;
reg sel;
wire [31:0]out;
multiplexer mtb(a,b,sel,out);


initial begin
a=32'h0000ffff;
b=32'haaaa0000;

sel=1;
#100

sel=0;







end
endmodule
module mux_tb();

reg [31:0]a;
reg [31:0]b;
reg sel;
wire [31:0]out;
multiplexer mtb(a,b,sel,out);


initial begin
a=32'h0000ffff;
b=32'haaaa0000;

sel=1;
#100

sel=0;







end
endmodule