data/full_repos/permissive/21051978/processor/spare/build3/umult8.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/21051978/processor/spare/build3/umult8.v:3: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7] reg_A, reg_B;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/processor/spare/build3/umult8.v:6: Little bit endian vector: MSB < LSB of bit range: 0:15\n output [0:15] result;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/processor/spare/build3/umult8.v:9: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] p8a_0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/processor/spare/build3/umult8.v:10: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] p8b_0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/processor/spare/build3/umult8.v:11: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] pt;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/spare/build3/umult8.v:50: Operator SUB expects 32 bits on the LHS, but LHS\'s CONST \'8\'hf\' generates 8 bits.\n                                                                                      : ... In instance umult8\n   pt=pt+(p8a_0[i]?(p8b_0<<(8\'d15-i)):16\'b0);\n                                 ^\n%Error: Exiting due to 6 warning(s)\n'
module umult8(reg_A, reg_B, result);

	input [0:7] reg_A, reg_B;
	

	output [0:15] result;
	

	reg [0:15] p8a_0;
	reg [0:15] p8b_0;
	reg [0:15] pt;
	reg [0:15] result;
	

	integer i;

	always @ (reg_A or reg_B)
		begin




		
		p8a_0=16'b0;
		p8b_0=16'b0;
		pt=16'b0;
		
		

		p8b_0={{8{1'b0}},reg_B[0:7]};
		

		p8a_0={{8{1'b0}},reg_A[0:7]};




		for (i=15; i>7; i=i-1)
			begin
			pt=pt+(p8a_0[i]?(p8b_0<<(8'd15-i)):16'b0);
			end

		result<=pt;
		end
endmodule
module umult8(reg_A, reg_B, result);


	input [0:7] reg_A, reg_B;
	

	output [0:15] result;
	

	reg [0:15] p8a_0;
	reg [0:15] p8b_0;
	reg [0:15] pt;
	reg [0:15] result;
	

	integer i;

	always @ (reg_A or reg_B)
		begin




		
		p8a_0=16'b0;
		p8b_0=16'b0;
		pt=16'b0;
		
		

		p8b_0={{8{1'b0}},reg_B[0:7]};
		

		p8a_0={{8{1'b0}},reg_A[0:7]};




		for (i=15; i>7; i=i-1)
			begin
			pt=pt+(p8a_0[i]?(p8b_0<<(8'd15-i)):16'b0);
			end

		result<=pt;
		end
endmodule