data/full_repos/permissive/143278/vhdl_tests/pr2555831.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/pr2555831.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top ();
  reg [31:0] din;
  wire [31:0] dout;

  test t(din, dout);

  initial begin
    din = 5;
    #1;
    $display("dout=%d", dout);
    if (dout == 5)
      $display("PASSED");
    else
      $display("FAILED");
  end

endmodule
module top ();

  reg [31:0] din;
  wire [31:0] dout;

  test t(din, dout);

  initial begin
    din = 5;
    #1;
    $display("dout=%d", dout);
    if (dout == 5)
      $display("PASSED");
    else
      $display("FAILED");
  end

endmodule