data/full_repos/permissive/19572582/Lab3/lab3_part5.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:118: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output reg [0:6] SSD;\n             ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:67: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:92: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H0 (SW[3:0], HEX0);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:93: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H1 (SW[7:4], HEX1);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:94: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H2 (SW[11:8], HEX2);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:95: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H3 (SW[15:12], HEX3);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:96: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H4 (R[3:0], HEX4);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:97: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H5 (R[7:4], HEX5);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:98: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H6 (R[11:8], HEX6);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab3/lab3_part5.v:99: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab3_part5\n  hex_ssd H7 (R[15:12], HEX7);\n               ^\n%Error: Exiting due to 10 warning(s)\n'
module lab3_part5 (SW, HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, KEY);
  input [3:0] KEY;
  input [17:0] SW;
  output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;
  
  reg [15:0] R;
  wire [15:0] Q;

  D_ff_with_sync_clr F0  (~KEY[1], SW[0],  Q[0],  ~KEY[0]);
  D_ff_with_sync_clr F1  (~KEY[1], SW[1],  Q[1],  ~KEY[0]);
  D_ff_with_sync_clr F2  (~KEY[1], SW[2],  Q[2],  ~KEY[0]);
  D_ff_with_sync_clr F3  (~KEY[1], SW[3],  Q[3],  ~KEY[0]);
  D_ff_with_sync_clr F4  (~KEY[1], SW[4],  Q[4],  ~KEY[0]);
  D_ff_with_sync_clr F5  (~KEY[1], SW[5],  Q[5],  ~KEY[0]);
  D_ff_with_sync_clr F6  (~KEY[1], SW[6],  Q[6],  ~KEY[0]);
  D_ff_with_sync_clr F7  (~KEY[1], SW[7],  Q[7],  ~KEY[0]);
  D_ff_with_sync_clr F8  (~KEY[1], SW[8],  Q[8],  ~KEY[0]);
  D_ff_with_sync_clr F9  (~KEY[1], SW[9],  Q[9],  ~KEY[0]);
  D_ff_with_sync_clr F10 (~KEY[1], SW[10], Q[10], ~KEY[0]);
  D_ff_with_sync_clr F11 (~KEY[1], SW[11], Q[11], ~KEY[0]);
  D_ff_with_sync_clr F12 (~KEY[1], SW[12], Q[12], ~KEY[0]);
  D_ff_with_sync_clr F13 (~KEY[1], SW[13], Q[13], ~KEY[0]);
  D_ff_with_sync_clr F14 (~KEY[1], SW[14], Q[14], ~KEY[0]);
  D_ff_with_sync_clr F15 (~KEY[1], SW[15], Q[15], ~KEY[0]);
  
  always
    R = Q;

  hex_ssd H0 (SW[3:0], HEX0);
  hex_ssd H1 (SW[7:4], HEX1);
  hex_ssd H2 (SW[11:8], HEX2);
  hex_ssd H3 (SW[15:12], HEX3);
  hex_ssd H4 (R[3:0], HEX4);
  hex_ssd H5 (R[7:4], HEX5);
  hex_ssd H6 (R[11:8], HEX6);
  hex_ssd H7 (R[15:12], HEX7);

endmodule
module lab3_part5 (SW, HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, KEY);

  input [3:0] KEY;
  input [17:0] SW;
  output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;
  
  reg [15:0] R;
  wire [15:0] Q;

  D_ff_with_sync_clr F0  (~KEY[1], SW[0],  Q[0],  ~KEY[0]);
  D_ff_with_sync_clr F1  (~KEY[1], SW[1],  Q[1],  ~KEY[0]);
  D_ff_with_sync_clr F2  (~KEY[1], SW[2],  Q[2],  ~KEY[0]);
  D_ff_with_sync_clr F3  (~KEY[1], SW[3],  Q[3],  ~KEY[0]);
  D_ff_with_sync_clr F4  (~KEY[1], SW[4],  Q[4],  ~KEY[0]);
  D_ff_with_sync_clr F5  (~KEY[1], SW[5],  Q[5],  ~KEY[0]);
  D_ff_with_sync_clr F6  (~KEY[1], SW[6],  Q[6],  ~KEY[0]);
  D_ff_with_sync_clr F7  (~KEY[1], SW[7],  Q[7],  ~KEY[0]);
  D_ff_with_sync_clr F8  (~KEY[1], SW[8],  Q[8],  ~KEY[0]);
  D_ff_with_sync_clr F9  (~KEY[1], SW[9],  Q[9],  ~KEY[0]);
  D_ff_with_sync_clr F10 (~KEY[1], SW[10], Q[10], ~KEY[0]);
  D_ff_with_sync_clr F11 (~KEY[1], SW[11], Q[11], ~KEY[0]);
  D_ff_with_sync_clr F12 (~KEY[1], SW[12], Q[12], ~KEY[0]);
  D_ff_with_sync_clr F13 (~KEY[1], SW[13], Q[13], ~KEY[0]);
  D_ff_with_sync_clr F14 (~KEY[1], SW[14], Q[14], ~KEY[0]);
  D_ff_with_sync_clr F15 (~KEY[1], SW[15], Q[15], ~KEY[0]);
  
  always
    R = Q;

  hex_ssd H0 (SW[3:0], HEX0);
  hex_ssd H1 (SW[7:4], HEX1);
  hex_ssd H2 (SW[11:8], HEX2);
  hex_ssd H3 (SW[15:12], HEX3);
  hex_ssd H4 (R[3:0], HEX4);
  hex_ssd H5 (R[7:4], HEX5);
  hex_ssd H6 (R[11:8], HEX6);
  hex_ssd H7 (R[15:12], HEX7);

endmodule