data/full_repos/permissive/184332405/accumulator.v
data/verilator_xmls/521bcd49-b5e3-4c90-b97e-146dcaa14760.xml
module accumulator(s, a, clk);

input clk;
input [7:0] a;
output reg [7:0] s;

always @( negedge clk ) begin
		s <= a;
end

endmodule
module accumulator(s, a, clk);


input clk;
input [7:0] a;
output reg [7:0] s;

always @( negedge clk ) begin
		s <= a;
end

endmodule