data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ValGen.v
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ValGen.v\n%Error: Exiting due to 4 error(s)\n'
module ValGen(
    input clk,
    input reset,
    output [15:0] value,
    output [15:0] command
    );
	
	reg [11:0] cnt;
	reg [4:0] clkCnt;
	
	assign tick = (clkCnt == 31);
	assign value = {{4{0}},cnt};
	assign command = 16'b0000110000000000;
	
	always@(posedge clk)
		if (reset) cnt = 0;
		else if (tick) cnt = cnt + 1;
	
	always@(posedge clk)
		if (reset) clkCnt = 0;
		else clkCnt = clkCnt +1;
		
endmodule
module ValGen(
    input clk,
    input reset,
    output [15:0] value,
    output [15:0] command
    );

	
	reg [11:0] cnt;
	reg [4:0] clkCnt;
	
	assign tick = (clkCnt == 31);
	assign value = {{4{0}},cnt};
	assign command = 16'b0000110000000000;
	
	always@(posedge clk)
		if (reset) cnt = 0;
		else if (tick) cnt = cnt + 1;
	
	always@(posedge clk)
		if (reset) clkCnt = 0;
		else clkCnt = clkCnt +1;
		
endmodule