data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/mux2.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/mux2.v:65: Multiple top level modules\n                                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                             : ... Top module \'MUX2\'\nmodule MUX2(\n       ^~~~\n                                                                                                             : ... Top module \'CARRY_MUX2\'\nmodule CARRY_MUX2(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module MUX2(


	input [0:0] A,
	input [0:0] B,
	input [0:0] S0,
	output [0:0] Y
	);
  
	assign Y = S0 ? B : A;









`ifdef ENABLE_TIMING

	specify
		(A => Y) = (0.001, 0.001);
		(B => Y) = (0.001, 0.001);
		(S0 => Y) = (0.001, 0.001);
	endspecify

`endif

`ifdef ENABLE_SIGNAL_INITIALIZATION

	initial begin
	`ifdef ENABLE_FORMAL_VERIFICATION
		$deposit(A, 1'b0);
		$deposit(B, 1'b0);
		$deposit(S0, 1'b0);
	`else
		$deposit(A, $random);
		$deposit(B, $random);
		$deposit(S0, $random);
	`endif

	end

`endif

endmodule
module MUX2(


	input [0:0] A,
	input [0:0] B,
	input [0:0] S0,
	output [0:0] Y
	);

  
	assign Y = S0 ? B : A;









`ifdef ENABLE_TIMING

	specify
		(A => Y) = (0.001, 0.001);
		(B => Y) = (0.001, 0.001);
		(S0 => Y) = (0.001, 0.001);
	endspecify

`endif

`ifdef ENABLE_SIGNAL_INITIALIZATION

	initial begin
	`ifdef ENABLE_FORMAL_VERIFICATION
		$deposit(A, 1'b0);
		$deposit(B, 1'b0);
		$deposit(S0, 1'b0);
	`else
		$deposit(A, $random);
		$deposit(B, $random);
		$deposit(S0, $random);
	`endif

	end

`endif

endmodule