data/full_repos/permissive/211316121/lab8_2_nexys4/Display.v
data/verilator_xmls/6768e043-c1d4-4bd6-ae9b-77158dc57bba.xml
module Display(
    input CLK100MHZ,
    input [9:0] SW,
    output CA,
    output CB,
    output CC,
    output CD,
    output CE,
    output CF,
    output CG,
    output [7:0] AN,
    output DP
    );
assign DP=1;
    
wire [6:0] SEG;
assign SEG = { CG, CF, CE, CD, CC, CB, CA };

wire [2:0] clk_seg;
clkdiv_7seg clkseg(CLK100MHZ,clk_seg);

wire clk_ram;
clkdiv clkram(CLK100MHZ,clk_ram);

wire clr=SW[9];
wire wr=SW[8];
wire [3:0] addr=SW[7:4];
wire [3:0] din=SW[3:0];
wire [3:0] qout;

RAM ram(clk_ram,wr,clr,din,addr,qout);
BCD_7Seg sevenseg(addr,qout,clr,clk_seg,SEG,AN);

endmodule
module Display(
    input CLK100MHZ,
    input [9:0] SW,
    output CA,
    output CB,
    output CC,
    output CD,
    output CE,
    output CF,
    output CG,
    output [7:0] AN,
    output DP
    );

assign DP=1;
    
wire [6:0] SEG;
assign SEG = { CG, CF, CE, CD, CC, CB, CA };

wire [2:0] clk_seg;
clkdiv_7seg clkseg(CLK100MHZ,clk_seg);

wire clk_ram;
clkdiv clkram(CLK100MHZ,clk_ram);

wire clr=SW[9];
wire wr=SW[8];
wire [3:0] addr=SW[7:4];
wire [3:0] din=SW[3:0];
wire [3:0] qout;

RAM ram(clk_ram,wr,clr,din,addr,qout);
BCD_7Seg sevenseg(addr,qout,clr,clk_seg,SEG,AN);

endmodule