data/full_repos/permissive/102039998/tests.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/102039998/tests.v:1: Cannot find include file: processor.v\n`include "processor.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/processor.v\n             data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/processor.v.v\n             data/full_repos/permissive/102039998,data/full_repos/permissive/102039998/processor.v.sv\n             processor.v\n             processor.v.v\n             processor.v.sv\n             obj_dir/processor.v\n             obj_dir/processor.v.v\n             obj_dir/processor.v.sv\n%Error: data/full_repos/permissive/102039998/tests.v:2: Cannot find include file: mips.h\n`include "mips.h" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:35: Define or directive not defined: \'`op\'\n  control control(instruction[`op], regdst, jump, branch, memread, memtoreg,\n                              ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  control control(instruction[`op], regdst, jump, branch, memread, memtoreg,\n                                 ^\n%Error: data/full_repos/permissive/102039998/tests.v:40: Define or directive not defined: \'`rs\'\n  registers register_file(instruction[`rs], instruction[`rt],\n                                      ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  registers register_file(instruction[`rs], instruction[`rt],\n                                         ^\n%Error: data/full_repos/permissive/102039998/tests.v:40: Define or directive not defined: \'`rt\'\n  registers register_file(instruction[`rs], instruction[`rt],\n                                                        ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:45: Define or directive not defined: \'`rd\'\n  mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);\n                                ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);\n                                   ^\n%Error: data/full_repos/permissive/102039998/tests.v:45: Define or directive not defined: \'`rt\'\n  mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);\n                                                  ^~~\n%Error: data/full_repos/permissive/102039998/tests.v:50: Define or directive not defined: \'`function\'\n  ALU_control alu_control(aluop_from_control, instruction[`function], rtype, aluop_to_alu);\n                                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  ALU_control alu_control(aluop_from_control, instruction[`function], rtype, aluop_to_alu);\n                                                                   ^\n%Error: data/full_repos/permissive/102039998/tests.v:57: Define or directive not defined: \'`target\'\n  jump_address_constructor jump_constructor(instruction[`target], pc_adder_mux[31:28], jump_address);\n                                                        ^~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:57: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  jump_address_constructor jump_constructor(instruction[`target], pc_adder_mux[31:28], jump_address);\n                                                               ^\n%Error: data/full_repos/permissive/102039998/tests.v:77: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("processor.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/102039998/tests.v:78: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, processor);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/102039998/tests.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #2000; $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 16 error(s), 1 warning(s)\n'
module complete_processor(output [31:0] instruction, output clock);

  wire clock;
  wire [31:0] pc_adder_mux, branch_adder_mux;
  wire [31:0] mux_pc;
  wire [31:0] instruction;
  reg [31:0] four;
  wire [31:0] address;

  wire [31:0] jump_address, branch_address;

  wire [3:0] aluop_from_control, aluop_to_alu;
  wire [31:0] read_data1,read_data2, alusrc_mux_output, alu_result;

  wire regdst, jump, branch, memread, memtoreg, rtype, regwrite, alusrc, memwrite, invertzero;
  wire syscall;
  wire branch_zero_and_output, branch_mux_control;


  wire [4:0] regdst_mux_output;
  wire [31:0] memtoreg_mux_output;


  wire [31:0] read_data;



  clock_gen clk(clock);
  PC p_counter(mux_pc, clock, address);
  adder pc_incrementer(address, four, pc_adder_mux);
  instruction_memory imem(address, instruction);
  control control(instruction[`op], regdst, jump, branch, memread, memtoreg,
                  aluop_from_control, rtype, memwrite, alusrc, regwrite, invertzero);

  SYSCALL_controller syscaller(instruction, clock, syscall);

  registers register_file(instruction[`rs], instruction[`rt],
                          regdst_mux_output, memtoreg_mux_output,
                          regwrite, syscall, clock,
                          read_data1, read_data2);
  mux32_2 memtoreg_mux(read_data, alu_result, memtoreg, memtoreg_mux_output);
  mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);

  data_memory dmem(alu_result, read_data2, memwrite, memread, clock, read_data);


  ALU_control alu_control(aluop_from_control, instruction[`function], rtype, aluop_to_alu);
  ALU alu(aluop_to_alu, read_data1, alusrc_mux_output, alu_result, zero);
  mux32_2 alusrc_mux({16'h0, instruction[15:0]},
                      read_data2, alusrc, alusrc_mux_output);


  mux32_2 jump_mux(jump_address, branch_address, jump, mux_pc);
  jump_address_constructor jump_constructor(instruction[`target], pc_adder_mux[31:28], jump_address);


  and1_2 branch_zero_and(branch, zero, branch_zero_and_output);

  inverter invertzero_inverter(branch_zero_and_output, invertzero, branch_mux_control);
  mux32_2 branch_mux(branch_adder_mux, pc_adder_mux, branch_mux_control, branch_address);
  adder branch_adder(pc_adder_mux,
                    {16'h0, instruction[15:0]}<<2,
                    branch_adder_mux);
  initial
    four = 4;
endmodule
module complete_processor(output [31:0] instruction, output clock);


  wire clock;
  wire [31:0] pc_adder_mux, branch_adder_mux;
  wire [31:0] mux_pc;
  wire [31:0] instruction;
  reg [31:0] four;
  wire [31:0] address;

  wire [31:0] jump_address, branch_address;

  wire [3:0] aluop_from_control, aluop_to_alu;
  wire [31:0] read_data1,read_data2, alusrc_mux_output, alu_result;

  wire regdst, jump, branch, memread, memtoreg, rtype, regwrite, alusrc, memwrite, invertzero;
  wire syscall;
  wire branch_zero_and_output, branch_mux_control;


  wire [4:0] regdst_mux_output;
  wire [31:0] memtoreg_mux_output;


  wire [31:0] read_data;



  clock_gen clk(clock);
  PC p_counter(mux_pc, clock, address);
  adder pc_incrementer(address, four, pc_adder_mux);
  instruction_memory imem(address, instruction);
  control control(instruction[`op], regdst, jump, branch, memread, memtoreg,
                  aluop_from_control, rtype, memwrite, alusrc, regwrite, invertzero);

  SYSCALL_controller syscaller(instruction, clock, syscall);

  registers register_file(instruction[`rs], instruction[`rt],
                          regdst_mux_output, memtoreg_mux_output,
                          regwrite, syscall, clock,
                          read_data1, read_data2);
  mux32_2 memtoreg_mux(read_data, alu_result, memtoreg, memtoreg_mux_output);
  mux5_2 regdst_mux(instruction[`rd], instruction[`rt], regdst, regdst_mux_output);

  data_memory dmem(alu_result, read_data2, memwrite, memread, clock, read_data);


  ALU_control alu_control(aluop_from_control, instruction[`function], rtype, aluop_to_alu);
  ALU alu(aluop_to_alu, read_data1, alusrc_mux_output, alu_result, zero);
  mux32_2 alusrc_mux({16'h0, instruction[15:0]},
                      read_data2, alusrc, alusrc_mux_output);


  mux32_2 jump_mux(jump_address, branch_address, jump, mux_pc);
  jump_address_constructor jump_constructor(instruction[`target], pc_adder_mux[31:28], jump_address);


  and1_2 branch_zero_and(branch, zero, branch_zero_and_output);

  inverter invertzero_inverter(branch_zero_and_output, invertzero, branch_mux_control);
  mux32_2 branch_mux(branch_adder_mux, pc_adder_mux, branch_mux_control, branch_address);
  adder branch_adder(pc_adder_mux,
                    {16'h0, instruction[15:0]}<<2,
                    branch_adder_mux);
  initial
    four = 4;
endmodule