data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_offset.v
1: b'%Error: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_offset.v:77: Cannot find file containing module: \'jelly_pipeline_insert_ff\'\n        jelly_pipeline_insert_ff\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/legacy,data/full_repos/permissive/2084115/jelly_pipeline_insert_ff\n             data/full_repos/permissive/2084115/rtl/legacy,data/full_repos/permissive/2084115/jelly_pipeline_insert_ff.v\n             data/full_repos/permissive/2084115/rtl/legacy,data/full_repos/permissive/2084115/jelly_pipeline_insert_ff.sv\n             jelly_pipeline_insert_ff\n             jelly_pipeline_insert_ff.v\n             jelly_pipeline_insert_ff.sv\n             obj_dir/jelly_pipeline_insert_ff\n             obj_dir/jelly_pipeline_insert_ff.v\n             obj_dir/jelly_pipeline_insert_ff.sv\n%Error: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_offset.v:101: Cannot find file containing module: \'jelly_pipeline_insert_ff\'\n        jelly_pipeline_insert_ff\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_offset.v:132: Operator SHIFTL expects 49 bits on the LHS, but LHS\'s VARREF \'ff_s_addr\' generates 46 bits.\n                                                                                         : ... In instance jelly_axi_addr_offset\n        assign ff_m_addr  = ((ff_s_addr << S_UNIT_SIZE) + (param_offset << OFFSET_SIZE)) >> M_UNIT_SIZE;\n                                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/legacy/jelly_axi_addr_offset.v:132: Operator SHIFTL expects 49 bits on the LHS, but LHS\'s VARREF \'param_offset\' generates 32 bits.\n                                                                                         : ... In instance jelly_axi_addr_offset\n        assign ff_m_addr  = ((ff_s_addr << S_UNIT_SIZE) + (param_offset << OFFSET_SIZE)) >> M_UNIT_SIZE;\n                                                                        ^~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module jelly_axi_addr_offset
        #(
            parameter   BYPASS        = 0,
            parameter   USER_WIDTH    = 0,
            parameter   OFFSET_SIZE   = 0,
            parameter   OFFSET_WIDTH  = 32,
            parameter   S_UNIT_SIZE   = 3,
            parameter   S_ADDR_WIDTH  = 46,
            parameter   M_UNIT_SIZE   = 0,
            parameter   M_ADDR_WIDTH  = S_ADDR_WIDTH + S_UNIT_SIZE - M_UNIT_SIZE,
            parameter   S_REGS        = 1,
            parameter   M_REGS        = 1,
            

            parameter   USER_BITS     = USER_WIDTH > 0 ? USER_WIDTH : 1
        )
        (
            input   wire                        aresetn,
            input   wire                        aclk,
            input   wire                        aclken,
            
            output  wire                        busy,
            
            input   wire    [OFFSET_WIDTH-1:0]  param_offset,
            
            input   wire    [USER_BITS-1:0]     s_user,
            input   wire    [S_ADDR_WIDTH-1:0]  s_addr,
            input   wire                        s_valid,
            output  wire                        s_ready,
            
            output  wire    [USER_BITS-1:0]     m_user,
            output  wire    [M_ADDR_WIDTH-1:0]  m_addr,
            output  wire                        m_valid,
            input   wire                        m_ready
        );
        
    generate
    if ( BYPASS ) begin : blk_bypass
        assign m_user  = s_user;
        assign m_addr  = (s_addr << S_UNIT_SIZE) >> M_UNIT_SIZE;
        assign m_valid = s_valid;
        assign s_ready = m_ready;
        
        assign  busy    = 1'b0;
    end
    else begin : blk_offset
        



        
        wire    [USER_BITS-1:0]     ff_s_user;
        wire    [S_ADDR_WIDTH-1:0]  ff_s_addr;
        wire                        ff_s_valid;
        wire                        ff_s_ready;
        
        wire    [USER_BITS-1:0]     ff_m_user;
        wire    [M_ADDR_WIDTH-1:0]  ff_m_addr;
        wire                        ff_m_valid;
        wire                        ff_m_ready;
        
        jelly_pipeline_insert_ff
                #(
                    .DATA_WIDTH         (USER_BITS+S_ADDR_WIDTH),
                    .SLAVE_REGS         (S_REGS),
                    .MASTER_REGS        (0)
                )
            i_pipeline_insert_ff_s
                (
                    .reset              (~aresetn),
                    .clk                (aclk),
                    .cke                (aclken),
                    
                    .s_data             ({s_user, s_addr}),
                    .s_valid            (s_valid),
                    .s_ready            (s_ready),
                    
                    .m_data             ({ff_s_user, ff_s_addr}),
                    .m_valid            (ff_s_valid),
                    .m_ready            (ff_s_ready),
                    
                    .buffered           (),
                    .s_ready_next       ()
                );
        
        jelly_pipeline_insert_ff
                #(
                    .DATA_WIDTH         (USER_BITS+M_ADDR_WIDTH),
                    .SLAVE_REGS         (0),
                    .MASTER_REGS        (M_REGS)
                )
            i_pipeline_insert_ff_m
                (
                    .reset              (~aresetn),
                    .clk                (aclk),
                    .cke                (aclken),
                    
                    .s_data             ({ff_m_user, ff_m_addr}),
                    .s_valid            (ff_m_valid),
                    .s_ready            (ff_m_ready),
                    
                    .m_data             ({m_user, m_addr}),
                    .m_valid            (m_valid),
                    .m_ready            (m_ready),
                    
                    .buffered           (),
                    .s_ready_next       ()
                );
        
        
        



        
        assign ff_m_user  = ff_s_user;
        assign ff_m_addr  = ((ff_s_addr << S_UNIT_SIZE) + (param_offset << OFFSET_SIZE)) >> M_UNIT_SIZE;
        assign ff_m_valid = ff_s_valid;
        assign ff_s_ready = ff_m_ready;
        
        assign busy       = ff_s_valid;
    end
    endgenerate
    
    
endmodule
module jelly_axi_addr_offset
        #(
            parameter   BYPASS        = 0,
            parameter   USER_WIDTH    = 0,
            parameter   OFFSET_SIZE   = 0,
            parameter   OFFSET_WIDTH  = 32,
            parameter   S_UNIT_SIZE   = 3,
            parameter   S_ADDR_WIDTH  = 46,
            parameter   M_UNIT_SIZE   = 0,
            parameter   M_ADDR_WIDTH  = S_ADDR_WIDTH + S_UNIT_SIZE - M_UNIT_SIZE,
            parameter   S_REGS        = 1,
            parameter   M_REGS        = 1,
            

            parameter   USER_BITS     = USER_WIDTH > 0 ? USER_WIDTH : 1
        )
        (
            input   wire                        aresetn,
            input   wire                        aclk,
            input   wire                        aclken,
            
            output  wire                        busy,
            
            input   wire    [OFFSET_WIDTH-1:0]  param_offset,
            
            input   wire    [USER_BITS-1:0]     s_user,
            input   wire    [S_ADDR_WIDTH-1:0]  s_addr,
            input   wire                        s_valid,
            output  wire                        s_ready,
            
            output  wire    [USER_BITS-1:0]     m_user,
            output  wire    [M_ADDR_WIDTH-1:0]  m_addr,
            output  wire                        m_valid,
            input   wire                        m_ready
        );

        
    generate
    if ( BYPASS ) begin : blk_bypass
        assign m_user  = s_user;
        assign m_addr  = (s_addr << S_UNIT_SIZE) >> M_UNIT_SIZE;
        assign m_valid = s_valid;
        assign s_ready = m_ready;
        
        assign  busy    = 1'b0;
    end
    else begin : blk_offset
        



        
        wire    [USER_BITS-1:0]     ff_s_user;
        wire    [S_ADDR_WIDTH-1:0]  ff_s_addr;
        wire                        ff_s_valid;
        wire                        ff_s_ready;
        
        wire    [USER_BITS-1:0]     ff_m_user;
        wire    [M_ADDR_WIDTH-1:0]  ff_m_addr;
        wire                        ff_m_valid;
        wire                        ff_m_ready;
        
        jelly_pipeline_insert_ff
                #(
                    .DATA_WIDTH         (USER_BITS+S_ADDR_WIDTH),
                    .SLAVE_REGS         (S_REGS),
                    .MASTER_REGS        (0)
                )
            i_pipeline_insert_ff_s
                (
                    .reset              (~aresetn),
                    .clk                (aclk),
                    .cke                (aclken),
                    
                    .s_data             ({s_user, s_addr}),
                    .s_valid            (s_valid),
                    .s_ready            (s_ready),
                    
                    .m_data             ({ff_s_user, ff_s_addr}),
                    .m_valid            (ff_s_valid),
                    .m_ready            (ff_s_ready),
                    
                    .buffered           (),
                    .s_ready_next       ()
                );
        
        jelly_pipeline_insert_ff
                #(
                    .DATA_WIDTH         (USER_BITS+M_ADDR_WIDTH),
                    .SLAVE_REGS         (0),
                    .MASTER_REGS        (M_REGS)
                )
            i_pipeline_insert_ff_m
                (
                    .reset              (~aresetn),
                    .clk                (aclk),
                    .cke                (aclken),
                    
                    .s_data             ({ff_m_user, ff_m_addr}),
                    .s_valid            (ff_m_valid),
                    .s_ready            (ff_m_ready),
                    
                    .m_data             ({m_user, m_addr}),
                    .m_valid            (m_valid),
                    .m_ready            (m_ready),
                    
                    .buffered           (),
                    .s_ready_next       ()
                );
        
        
        



        
        assign ff_m_user  = ff_s_user;
        assign ff_m_addr  = ((ff_s_addr << S_UNIT_SIZE) + (param_offset << OFFSET_SIZE)) >> M_UNIT_SIZE;
        assign ff_m_valid = ff_s_valid;
        assign ff_s_ready = ff_m_ready;
        
        assign busy       = ff_s_valid;
    end
    endgenerate
    
    
endmodule