data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_DW_lsd.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_DW_lsd.v:23: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 4 bits.\n                                                                                         : ... In instance NV_DW_lsd\n  temp_enc = a_width-1;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_DW_lsd.v:24: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 4 bits.\n                                                                                         : ... In instance NV_DW_lsd\n  for (i=a_width-2; done==0; i=i-1) begin\n        ^\n%Warning-WIDTH: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_DW_lsd.v:26: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 4 bits.\n                                                                                         : ... In instance NV_DW_lsd\n      temp_enc = a_width - i -2;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_DW_lsd.v:30: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 4 bits.\n                                                                                         : ... In instance NV_DW_lsd\n        temp_enc = a_width-1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_DW_lsd.v:44: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 4 bits.\n                                                                                         : ... In instance NV_DW_lsd\n  temp = b_width - temp_enc;\n       ^\n%Error: Exiting due to 5 warning(s)\n'
module NV_DW_lsd (a, dec, enc);
  parameter a_width = 8;
  parameter b_width = a_width-1;
  localparam enc_width = ((a_width>16)?((a_width>64)?((a_width>128)?8:7):((a_width>32)?6:5)):((a_width>4)?((a_width>8)?4:3):((a_width>2)?2:1)));
  input [a_width-1:0] a;
  output [a_width-1:0] dec;
  output [enc_width-1:0] enc;

function [enc_width-1:0] DWF_lsd_enc (input [a_width-1:0] A);
  reg [enc_width-1:0] temp_enc;
  reg [enc_width-1:0] i;
  reg done;
  begin
  done =0;
  temp_enc = a_width-1;
  for (i=a_width-2; done==0; i=i-1) begin
    if (A[i+1] != A[i]) begin
      temp_enc = a_width - i -2;
      done =1;
    end
    else if(i==0) begin
        temp_enc = a_width-1;
        done =1;
    end
  end
  DWF_lsd_enc = temp_enc;
  end
endfunction

function [a_width-1:0] DWF_lsd (input [a_width-1:0] A);
  reg [enc_width-1:0] temp_enc;
  reg [a_width-1:0] temp_dec;
  reg [enc_width-1:0] temp;
  temp_enc = DWF_lsd_enc (A);
  temp_dec = {a_width{1'b0}};
  temp = b_width - temp_enc;
  temp_dec[temp] = 1'b1;
  DWF_lsd = temp_dec;
endfunction
assign enc = DWF_lsd_enc (a);
assign dec = DWF_lsd (a);
endmodule
module NV_DW_lsd (a, dec, enc);

  parameter a_width = 8;
  parameter b_width = a_width-1;
  localparam enc_width = ((a_width>16)?((a_width>64)?((a_width>128)?8:7):((a_width>32)?6:5)):((a_width>4)?((a_width>8)?4:3):((a_width>2)?2:1)));
  input [a_width-1:0] a;
  output [a_width-1:0] dec;
  output [enc_width-1:0] enc;

function [enc_width-1:0] DWF_lsd_enc (input [a_width-1:0] A);
  reg [enc_width-1:0] temp_enc;
  reg [enc_width-1:0] i;
  reg done;
  begin
  done =0;
  temp_enc = a_width-1;
  for (i=a_width-2; done==0; i=i-1) begin
    if (A[i+1] != A[i]) begin
      temp_enc = a_width - i -2;
      done =1;
    end
    else if(i==0) begin
        temp_enc = a_width-1;
        done =1;
    end
  end
  DWF_lsd_enc = temp_enc;
  end
endfunction

function [a_width-1:0] DWF_lsd (input [a_width-1:0] A);
  reg [enc_width-1:0] temp_enc;
  reg [a_width-1:0] temp_dec;
  reg [enc_width-1:0] temp;
  temp_enc = DWF_lsd_enc (A);
  temp_dec = {a_width{1'b0}};
  temp = b_width - temp_enc;
  temp_dec[temp] = 1'b1;
  DWF_lsd = temp_dec;
endfunction
assign enc = DWF_lsd_enc (a);
assign dec = DWF_lsd (a);
endmodule