data/full_repos/permissive/135701568/instructionMemory.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/9bf975aa-6767-4df3-94f9-7fd3ca058209.xml
module instructionMemory(PC, outInst, halt);
  input[11:0] PC;
  output [18:0] outInst;
  output halt;
  reg[18:0] insMemory[0:4095];
  assign outInst = insMemory[PC];
  assign halt = ~(|(outInst));

  initial begin
    insMemory[0] = 19'b1000000100001100100;
    insMemory[1] = 19'b1000001000001100110;
    insMemory[2] = 19'b0000001100101000000;
    insMemory[3] = 19'b1000101100001101000;
    insMemory[4] = 19'b1000000100001100101;
    insMemory[5] = 19'b1000001000001100111;
    insMemory[6] = 19'b0000101100101000000;
    insMemory[7] = 19'b1000101100001101001;
  end
endmodule
module instructionMemory(PC, outInst, halt);

  input[11:0] PC;
  output [18:0] outInst;
  output halt;
  reg[18:0] insMemory[0:4095];
  assign outInst = insMemory[PC];
  assign halt = ~(|(outInst));

  initial begin
    insMemory[0] = 19'b1000000100001100100;
    insMemory[1] = 19'b1000001000001100110;
    insMemory[2] = 19'b0000001100101000000;
    insMemory[3] = 19'b1000101100001101000;
    insMemory[4] = 19'b1000000100001100101;
    insMemory[5] = 19'b1000001000001100111;
    insMemory[6] = 19'b0000101100101000000;
    insMemory[7] = 19'b1000101100001101001;
  end
endmodule