data/full_repos/permissive/169738435/System/c1_wait.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169738435/System/c1_wait.v:39: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'WAIT_CNT\' generates 2 bits.\n                                                                        : ... In instance c1_wait\n   if (WAIT_CNT) WAIT_CNT <= WAIT_CNT - 1\'b1;\n   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169738435/System/c1_wait.v:44: Operator NOT expects 2 bits on the LHS, but LHS\'s VARREF \'nROMWAIT\' generates 1 bits.\n                                                                        : ... In instance c1_wait\n    WAIT_CNT <= ~nROMWAIT;     \n                ^\n%Error: Exiting due to 2 warning(s)\n'
module c1_wait(
	input CLK_68KCLK, nAS,
	input nROM_ZONE, nPORT_ZONE, nCARD_ZONE,
	input nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
	output nDTACK
);

	reg [1:0] WAIT_CNT;
	


	assign nDTACK = nAS | |{WAIT_CNT};
	

	
	always @(negedge CLK_68KCLK)
	begin
		if (!nAS)
		begin

			if (WAIT_CNT) WAIT_CNT <= WAIT_CNT - 1'b1;
		end
		else
		begin
			if (!nROM_ZONE)
				WAIT_CNT <= ~nROMWAIT;
			else if (!nPORT_ZONE)
				WAIT_CNT <= ~{nPWAIT0, nPWAIT1};
			else if (!nCARD_ZONE)
				WAIT_CNT <= 2;
			else
				WAIT_CNT <= 0;
		end
	end
	
endmodule
module c1_wait(
	input CLK_68KCLK, nAS,
	input nROM_ZONE, nPORT_ZONE, nCARD_ZONE,
	input nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
	output nDTACK
);


	reg [1:0] WAIT_CNT;
	


	assign nDTACK = nAS | |{WAIT_CNT};
	

	
	always @(negedge CLK_68KCLK)
	begin
		if (!nAS)
		begin

			if (WAIT_CNT) WAIT_CNT <= WAIT_CNT - 1'b1;
		end
		else
		begin
			if (!nROM_ZONE)
				WAIT_CNT <= ~nROMWAIT;
			else if (!nPORT_ZONE)
				WAIT_CNT <= ~{nPWAIT0, nPWAIT1};
			else if (!nCARD_ZONE)
				WAIT_CNT <= 2;
			else
				WAIT_CNT <= 0;
		end
	end
	
endmodule