data/full_repos/permissive/157979234/Semester III/Digital Design and Computer Organization/Session 03/1bFA_TB.v
1: b'%Error: Cannot find file containing module: III/Digital\n        ... Looked in:\n             data/full_repos/permissive/157979234/Semester/III/Digital\n             data/full_repos/permissive/157979234/Semester/III/Digital.v\n             data/full_repos/permissive/157979234/Semester/III/Digital.sv\n             III/Digital\n             III/Digital.v\n             III/Digital.sv\n             obj_dir/III/Digital\n             obj_dir/III/Digital.v\n             obj_dir/III/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Organization/Session\n%Error: Cannot find file containing module: 03,data/full_repos/permissive/157979234\n%Error: Cannot find file containing module: data/full_repos/permissive/157979234/Semester\n%Error: Cannot find file containing module: 03/1bFA_TB.v\n%Error: Exiting due to 8 error(s)\n'
module FA_TB();

wire t_s, t_cout;
reg t_a, t_b, t_cin;

FA I1(.A(t_a), .B(t_b), .Cin(t_cin), .S(t_s), .Cout(t_cout));

initial
begin
$dumpfile("FA.vcd");
$dumpvars(0,FA_TB);
end

initial
begin
$monitor(t_a, t_b, t_cin, t_s, t_cout);

t_a=1'b0;
t_b=1'b0;
t_cin=1'b0;
#5
t_a=1'b0;
t_b=1'b0;
t_cin=1'b1;
#5
t_a=1'b0;
t_b=1'b1;
t_cin=1'b0;
#5
t_a=1'b0;
t_b=1'b1;
t_cin=1'b1;
#5
t_a=1'b1;
t_b=1'b0;
t_cin=1'b0;
#5
t_a=1'b1;
t_b=1'b0;
t_cin=1'b1;
#5
t_a=1'b1;
t_b=1'b1;
t_cin=1'b0;
#5
t_a=1'b1;
t_b=1'b1;
t_cin=1'b1;
#5
t_a=1'b0;
t_b=1'b0;
t_cin=1'b0;

end
endmodule
module FA_TB();


wire t_s, t_cout;
reg t_a, t_b, t_cin;

FA I1(.A(t_a), .B(t_b), .Cin(t_cin), .S(t_s), .Cout(t_cout));

initial
begin
$dumpfile("FA.vcd");
$dumpvars(0,FA_TB);
end

initial
begin
$monitor(t_a, t_b, t_cin, t_s, t_cout);

t_a=1'b0;
t_b=1'b0;
t_cin=1'b0;
#5
t_a=1'b0;
t_b=1'b0;
t_cin=1'b1;
#5
t_a=1'b0;
t_b=1'b1;
t_cin=1'b0;
#5
t_a=1'b0;
t_b=1'b1;
t_cin=1'b1;
#5
t_a=1'b1;
t_b=1'b0;
t_cin=1'b0;
#5
t_a=1'b1;
t_b=1'b0;
t_cin=1'b1;
#5
t_a=1'b1;
t_b=1'b1;
t_cin=1'b0;
#5
t_a=1'b1;
t_b=1'b1;
t_cin=1'b1;
#5
t_a=1'b0;
t_b=1'b0;
t_cin=1'b0;

end
endmodule