data/full_repos/permissive/143278/ivltests/pr809b.v
data/verilator_xmls/fc5b20ca-b8d4-4248-8cb6-553acc905038.xml
module target
   #(parameter WA = 4, parameter WB = 4)
    (input [WA-1:0] A, output [WB-1:0] B);

   assign B = A;

endmodule
module target
   #(parameter WA = 4, parameter WB = 4)
    (input [WA-1:0] A, output [WB-1:0] B);


   assign B = A;

endmodule