data/full_repos/permissive/159902111/PCPU_experiment/PC_Ctrl.v
data/verilator_xmls/aa8c14f3-4350-42d7-8350-a80d5c361416.xml
module PC_Ctrl(
  input        enable_i,
  input  [1:0] PCSource_i,
  output [1:0] Signal_o
  );
  reg [1:0] Signal;
  always@(*)
  begin
    if (PCSource_i == 2'b01 && !enable_i)
      Signal = 2'b0;
    else Signal = PCSource_i;
  end
  assign Signal_o = Signal;
endmodule
module PC_Ctrl(
  input        enable_i,
  input  [1:0] PCSource_i,
  output [1:0] Signal_o
  );

  reg [1:0] Signal;
  always@(*)
  begin
    if (PCSource_i == 2'b01 && !enable_i)
      Signal = 2'b0;
    else Signal = PCSource_i;
  end
  assign Signal_o = Signal;
endmodule