data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/io_reg/io_reg_tb.v
 line:18: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/io_reg/io_reg_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #0 in_gen = 1\'b1; clk_gen = 1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/io_reg/io_reg_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #100 in_gen = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/io_reg/io_reg_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk_gen = ~clk_gen;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/io_reg/io_reg_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #5000 $stop;\n        ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/io_reg/io_reg_tb.v:6: Cannot find file containing module: \'io_reg\'\n    io_reg inst(.clk(clk_gen), .in(in_gen), .out(out));\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/io_reg,data/full_repos/permissive/137416811/io_reg\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/io_reg,data/full_repos/permissive/137416811/io_reg.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/io_reg,data/full_repos/permissive/137416811/io_reg.sv\n             io_reg\n             io_reg.v\n             io_reg.sv\n             obj_dir/io_reg\n             obj_dir/io_reg.v\n             obj_dir/io_reg.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module io_reg_tb;
    
    reg clk_gen, in_gen;
    wire out;

    io_reg inst(.clk(clk_gen), .in(in_gen), .out(out));

    initial begin
        #0 in_gen = 1'b1; clk_gen = 1'b0;
        #100 in_gen = 1'b0;
    end

    always begin
        #10 clk_gen = ~clk_gen;
    end

    initial begin
        #5000 $stop;
    end

endmodule
module io_reg_tb;

    
    reg clk_gen, in_gen;
    wire out;

    io_reg inst(.clk(clk_gen), .in(in_gen), .out(out));

    initial begin
        #0 in_gen = 1'b1; clk_gen = 1'b0;
        #100 in_gen = 1'b0;
    end

    always begin
        #10 clk_gen = ~clk_gen;
    end

    initial begin
        #5000 $stop;
    end

endmodule