data/full_repos/permissive/155656868/src/memory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/155656868/src/memory.v:79: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'instruction_memory\'\nmodule instruction_memory #(parameter ADDRESS_BITS=32, MEMORY_DEPTH=1024, WORD_SIZE=32)\n       ^~~~~~~~~~~~~~~~~~\n                                                                       : ... Top module \'register_bank\'\nmodule register_bank #(parameter REGISTER_COUNT=32, REGISTER_WIDTH=32, ADDRESS_BITS=5)\n       ^~~~~~~~~~~~~\n                                                                       : ... Top module \'data_memory\'\nmodule data_memory #(parameter ADDRESS_BITS=32, MEMORY_DEPTH=64, WORD_SIZE=32)\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:89: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance register_bank\n    initial reg_file[REGISTER_COUNT-1] = 1\'d0;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:101: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[0]  = 8\'h00_00_00_02;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:102: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[1]  = 8\'h00_00_00_05;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:103: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[2]  = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:104: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[3]  = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:105: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[4]  = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:106: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[5]  = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:107: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[6]  = 8\'h00_00_00_ff;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:108: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[7]  = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:109: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[8]  = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:110: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[9]  = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:111: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[10] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:112: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[11] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:113: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[12] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:114: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[13] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:115: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[14] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:116: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[15] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:117: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[16] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:118: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[17] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:119: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[18] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:120: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[19] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:121: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[20] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:122: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[21] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:123: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[22] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:124: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[23] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:125: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[24] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:126: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[25] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:127: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[26] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:128: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[27] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:129: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[28] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:130: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[29] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:131: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[30] = 8\'h00_00_00_00;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/155656868/src/memory.v:132: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                     : ... In instance register_bank\n    initial reg_file[31] = 8\'h00_00_00_00;\n                         ^\n%Error: Exiting due to 34 warning(s)\n'
module data_memory #(parameter ADDRESS_BITS=32, MEMORY_DEPTH=64, WORD_SIZE=32)
                    (input  [ADDRESS_BITS-1:0] addr,
                     input  [WORD_SIZE-1:0]    d_in,
                     input                     wr,
                     output [WORD_SIZE-1:0]    d_out);


    reg [WORD_SIZE-1:0] data_memory [0:MEMORY_DEPTH-1];
    reg [WORD_SIZE-1:0] data_out;

    always @(addr or wr) begin
        if (wr) data_memory[addr] <= d_in;
        else data_out <= data_memory[addr];
    end

    assign d_out = data_out;
endmodule
module data_memory #(parameter ADDRESS_BITS=32, MEMORY_DEPTH=64, WORD_SIZE=32)
                    (input  [ADDRESS_BITS-1:0] addr,
                     input  [WORD_SIZE-1:0]    d_in,
                     input                     wr,
                     output [WORD_SIZE-1:0]    d_out);



    reg [WORD_SIZE-1:0] data_memory [0:MEMORY_DEPTH-1];
    reg [WORD_SIZE-1:0] data_out;

    always @(addr or wr) begin
        if (wr) data_memory[addr] <= d_in;
        else data_out <= data_memory[addr];
    end

    assign d_out = data_out;
endmodule