data/full_repos/permissive/172912857/project_alu_basys3/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #2 tb_clk = ~tb_clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:23: Unsupported or unknown PLI call: $monitor\n$monitor(tb_x, tb_y, tb_opcode, tb_clk);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Error: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:67: Unsupported or unknown PLI call: $monitor\n  $monitor(tb_number, tb_thousands, tb_hundreds, tb_tens, tb_ones);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:69: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/172912857/project_alu_basys3/testbench.v:71: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module data_tb;
wire [15:0] tb_x, tb_y;
wire [5:0] tb_opcode;
reg [15:0] tb_data;
reg tb_clk;
reg [2:0] tb_load;

data my_data(
    .data(tb_data),

    .load(tb_load),
    .x(tb_x), .y(tb_y),
    .opcode(tb_opcode)
    );

always
    begin
    #2 tb_clk = ~tb_clk;
    end
    
initial
begin
$monitor(tb_x, tb_y, tb_opcode, tb_clk);

tb_clk = 0;
#5

tb_data = 16'b0;
tb_load = 3'b0;

#5
tb_load = 3'b001;

#5
tb_data = 16'b1010101010101010;

#5
tb_load = 3'b010;

#5
tb_data = 16'b1111111100110011;

#5
tb_load = 3'b100;

end
endmodule
module data_tb;

wire [15:0] tb_x, tb_y;
wire [5:0] tb_opcode;
reg [15:0] tb_data;
reg tb_clk;
reg [2:0] tb_load;

data my_data(
    .data(tb_data),

    .load(tb_load),
    .x(tb_x), .y(tb_y),
    .opcode(tb_opcode)
    );

always
    begin
    #2 tb_clk = ~tb_clk;
    end
    
initial
begin
$monitor(tb_x, tb_y, tb_opcode, tb_clk);

tb_clk = 0;
#5

tb_data = 16'b0;
tb_load = 3'b0;

#5
tb_load = 3'b001;

#5
tb_data = 16'b1010101010101010;

#5
tb_load = 3'b010;

#5
tb_data = 16'b1111111100110011;

#5
tb_load = 3'b100;

end
endmodule