data/full_repos/permissive/124846744/src/pool/pool_unit.v
data/verilator_xmls/74bd287e-df6f-47ac-a105-c3bcc9f887cc.xml
module pool_unit(

			d_out,

			clk,
			rst_n,
			d_in,
			pool_clr);
	input  	clk;
	input  	rst_n;

	input 	pool_clr;
	input 	[15:0]	d_in;
	output 	[15:0]	d_out;




wire [15:0] temp;
assign temp = (temp_r >d_in )? temp_r:d_in;


reg [15:0] temp_r;
always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin

		temp_r <= 0;
	end
	else if (pool_clr) begin
		temp_r <= d_in;
	end
	else begin
		temp_r <= temp;
	end	
end






assign d_out = temp_r;


endmodule
module pool_unit(

			d_out,

			clk,
			rst_n,
			d_in,
			pool_clr);

	input  	clk;
	input  	rst_n;

	input 	pool_clr;
	input 	[15:0]	d_in;
	output 	[15:0]	d_out;




wire [15:0] temp;
assign temp = (temp_r >d_in )? temp_r:d_in;


reg [15:0] temp_r;
always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin

		temp_r <= 0;
	end
	else if (pool_clr) begin
		temp_r <= d_in;
	end
	else begin
		temp_r <= temp;
	end	
end






assign d_out = temp_r;


endmodule