data/full_repos/permissive/109936328/pipeline/fe.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/pipeline/fe.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:20: Define or directive not defined: \'`ADDR_W\'\n  input [`ADDR_W - 1:0] i_branch_addr;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:22: Define or directive not defined: \'`ADDR_W\'\n  output [`ADDR_W -1:0] o_pc;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:25: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] r_pc;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:32: Define or directive not defined: \'`INSTR_W\'\n        r_pc <= i_branch_addr + `INSTR_W / 8;\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:32: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n        r_pc <= i_branch_addr + `INSTR_W / 8;\n                                         ^\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:34: Define or directive not defined: \'`INSTR_W\'\n        r_pc <= r_pc + `INSTR_W / 8;\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/fe.v:34: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n        r_pc <= r_pc + `INSTR_W / 8;\n                                ^\n%Error: Exiting due to 8 error(s)\n'
module fe(
  clk,
  clr,
  stall,

  i_branch,
  i_branch_addr,

  o_pc,
  o_instr_req
);

  input clk;
  input clr;
  input stall;

  input i_branch;
  input [`ADDR_W - 1:0] i_branch_addr;

  output [`ADDR_W -1:0] o_pc;
  output o_instr_req;

  reg [`ADDR_W - 1:0] r_pc;

  always@(posedge clk) begin
    if(clr == 1) begin
      r_pc <= 0;
    end else if(stall == 0) begin
      if (i_branch == 1) begin
        r_pc <= i_branch_addr + `INSTR_W / 8;
      end else begin
        r_pc <= r_pc + `INSTR_W / 8;
      end
    end
  end

  assign o_pc = i_branch ? i_branch_addr : r_pc;
  assign o_instr_req = ~clr;

endmodule
module fe(
  clk,
  clr,
  stall,

  i_branch,
  i_branch_addr,

  o_pc,
  o_instr_req
);


  input clk;
  input clr;
  input stall;

  input i_branch;
  input [`ADDR_W - 1:0] i_branch_addr;

  output [`ADDR_W -1:0] o_pc;
  output o_instr_req;

  reg [`ADDR_W - 1:0] r_pc;

  always@(posedge clk) begin
    if(clr == 1) begin
      r_pc <= 0;
    end else if(stall == 0) begin
      if (i_branch == 1) begin
        r_pc <= i_branch_addr + `INSTR_W / 8;
      end else begin
        r_pc <= r_pc + `INSTR_W / 8;
      end
    end
  end

  assign o_pc = i_branch ? i_branch_addr : r_pc;
  assign o_instr_req = ~clr;

endmodule