data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/ripple_adder_testbench.v
 line:37: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/ripple_adder_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish; \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/ripple_adder_testbench.v:30: Cannot find file containing module: \'ripple_adder\'\nripple_adder a1(co,sum,a,b,ci);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new,data/full_repos/permissive/169574047/ripple_adder\n             data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new,data/full_repos/permissive/169574047/ripple_adder.v\n             data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new,data/full_repos/permissive/169574047/ripple_adder.sv\n             ripple_adder\n             ripple_adder.v\n             ripple_adder.sv\n             obj_dir/ripple_adder\n             obj_dir/ripple_adder.v\n             obj_dir/ripple_adder.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ripple_adder_testbench;

reg [3:0] a,b;
reg ci;
wire [3:0] sum;
wire co;

ripple_adder a1(co,sum,a,b,ci);

initial
begin
    ci= 0;
    a = 4'b1101;
    b = 4'b1110;
    #10 $finish; 
end
endmodule
module ripple_adder_testbench;


reg [3:0] a,b;
reg ci;
wire [3:0] sum;
wire co;

ripple_adder a1(co,sum,a,b,ci);

initial
begin
    ci= 0;
    a = 4'b1101;
    b = 4'b1110;
    #10 $finish; 
end
endmodule