data/full_repos/permissive/205055389/vlib/74xxGateLevel.v
 line:125: before: "11"
1: b"%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:197: syntax error, unexpected (-for-strength, expecting '('\n  not (highz1, strong0) #40 g1(Y1, A1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:236: syntax error, unexpected (-for-strength, expecting '('\n  nor (highz1,strong0) #35 g1(Y1, A1, B1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:255: syntax error, unexpected (-for-strength, expecting '('\n  nand (highz1, strong0) #35 g1(Y1, A1, B1, C1, D1);\n        ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:367: syntax error, unexpected (-for-strength, expecting '('\n  nand (highz1, strong0) #35 g1(Y1, A1, B1, C1);\n        ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:385: syntax error, unexpected (-for-strength, expecting '('\n  and (highz1, strong0) #21 g1(Y1, A1, B1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:421: syntax error, unexpected (-for-strength, expecting '('\n  and (highz1, strong0) #40 g1(Y1, A1, B1, C1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:457: syntax error, unexpected (-for-strength, expecting '('\n  nand (highz1,strong0) #35 g1(Y1, A1, B1);\n        ^~~~~~\n%Error: Exiting due to 7 error(s)\n"
module SN74118 (_S1, _S2, _S3, _S4, _S5, _S6, _R, Q1, Q2, Q3, Q4, Q5, Q6);

  input _S1,_S2,_S3,_S4,_S5,_S6,_R;
  output Q1, Q2, Q3, Q4, Q5, Q6;
  wire  _Q1,_Q2,_Q3,_Q4,_Q5,_Q6;

  nand #11 g1( Q1,_S1,_Q1);
  nand #11 g2(_Q1, Q1,_R);
  
  nand #11 g3( Q2,_S2,_Q2);
  nand #11 g4(_Q2, Q2,_R);
  
  nand #11 g5( Q3,_S3,_Q3);
  nand #11 g6(_Q3, Q3,_R);
  
  nand #11 g7( Q4,_S4,_Q4);
  nand #11 g8(_Q4, Q4,_R);
  
  nand #11 g9( Q5,_S5,_Q5);
  nand #11 g10(_Q5, Q5,_R);
  
  nand #11 g11( Q6,_S6,_Q6);
  nand #11 g12(_Q6, Q6,_R);

endmodule
module SN74118 (_S1, _S2, _S3, _S4, _S5, _S6, _R, Q1, Q2, Q3, Q4, Q5, Q6);


  input _S1,_S2,_S3,_S4,_S5,_S6,_R;
  output Q1, Q2, Q3, Q4, Q5, Q6;
  wire  _Q1,_Q2,_Q3,_Q4,_Q5,_Q6;

  nand #11 g1( Q1,_S1,_Q1);
  nand #11 g2(_Q1, Q1,_R);
  
  nand #11 g3( Q2,_S2,_Q2);
  nand #11 g4(_Q2, Q2,_R);
  
  nand #11 g5( Q3,_S3,_Q3);
  nand #11 g6(_Q3, Q3,_R);
  
  nand #11 g7( Q4,_S4,_Q4);
  nand #11 g8(_Q4, Q4,_R);
  
  nand #11 g9( Q5,_S5,_Q5);
  nand #11 g10(_Q5, Q5,_R);
  
  nand #11 g11( Q6,_S6,_Q6);
  nand #11 g12(_Q6, Q6,_R);

endmodule