data/full_repos/permissive/119715647/sim/AccessControl/AccessControl_tb.v
 line:29: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl_tb.v:21: Unsupported or unknown PLI call: $monitor\n  $monitor("time:[%0t],Data:[%h],State:[%d],AddressWire:[%h],Access_grant:[%b]",\n  ^~~~~~~~\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl_tb.v:29: syntax error, unexpected \'@\'\n  #10 @(posedge clk) Data_In_Load = 1; Data_In = 16\'h1476;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10 @(posedge clk) Data_In_Load = 1; Data_In = 16\'h1476;\n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl_tb.v:30: syntax error, unexpected \'@\'\n  #30 @(posedge clk) Data_In_Load = 0; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #30 @(posedge clk) Data_In_Load = 0; \n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl_tb.v:31: syntax error, unexpected \'@\'\n  #10 @(posedge clk) Data_In_Load = 1; Data_In = 16\'h2456;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #10 @(posedge clk) Data_In_Load = 1; Data_In = 16\'h2456;\n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl_tb.v:32: syntax error, unexpected \'@\'\n  #30 @(posedge clk) Data_In_Load = 0; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControl_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #30 @(posedge clk) Data_In_Load = 0; \n  ^\n%Error: Exiting due to 5 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module AccessControl_tb();
	
	reg [0:0] clk, rst, Data_In_Load;
	reg [17:0] Data_In; 
	wire [0:0] Access_grant; 
	AccessControl AC(
		.clk(clk), 
		.rst(rst),  
		._Data_In(Data_In), 
		._Data_In_Load(Data_In_Load), 
		._Access_grant(Access_grant)
		); 

	always begin
		#10 clk = ~clk; 
	end

	initial begin
		$monitor("time:[%0t],Data:[%h],State:[%d],AddressWire:[%h],Access_grant:[%b]",
		$time,
		Data_In, 
		AC.FSM.State,
		AC.Address_Wire,
		Access_grant);  

		clk = 1; rst = 1;  
		#10 @(posedge clk) Data_In_Load = 1; Data_In = 16'h1476;
		#30 @(posedge clk) Data_In_Load = 0; 
		#10 @(posedge clk) Data_In_Load = 1; Data_In = 16'h2456;
		#30 @(posedge clk) Data_In_Load = 0; 






		

	end

endmodule
module AccessControl_tb();

	
	reg [0:0] clk, rst, Data_In_Load;
	reg [17:0] Data_In; 
	wire [0:0] Access_grant; 
	AccessControl AC(
		.clk(clk), 
		.rst(rst),  
		._Data_In(Data_In), 
		._Data_In_Load(Data_In_Load), 
		._Access_grant(Access_grant)
		); 

	always begin
		#10 clk = ~clk; 
	end

	initial begin
		$monitor("time:[%0t],Data:[%h],State:[%d],AddressWire:[%h],Access_grant:[%b]",
		$time,
		Data_In, 
		AC.FSM.State,
		AC.Address_Wire,
		Access_grant);  

		clk = 1; rst = 1;  
		#10 @(posedge clk) Data_In_Load = 1; Data_In = 16'h1476;
		#30 @(posedge clk) Data_In_Load = 0; 
		#10 @(posedge clk) Data_In_Load = 1; Data_In = 16'h2456;
		#30 @(posedge clk) Data_In_Load = 0; 






		

	end

endmodule