data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/PipeTest.v
1: b"%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/PipeTest.v:48: Cannot find file containing module: 'pipe_in_check'\npipe_in_check pic0 (.clk           (ti_clk),\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog,data/full_repos/permissive/120539939/pipe_in_check\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog,data/full_repos/permissive/120539939/pipe_in_check.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog,data/full_repos/permissive/120539939/pipe_in_check.sv\n             pipe_in_check\n             pipe_in_check.v\n             pipe_in_check.sv\n             obj_dir/pipe_in_check\n             obj_dir/pipe_in_check.v\n             obj_dir/pipe_in_check.sv\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/PipeTest.v:63: Cannot find file containing module: 'pipe_out_check'\npipe_out_check poc0 (.clk            (ti_clk),\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/PipeTest.v:75: Cannot find file containing module: 'okHost'\nokHost okHI(\n^~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/PipeTest.v:80: Cannot find file containing module: 'okWireOR'\nokWireOR # (.N(3)) wireOR (ok2, ok2x);\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/PipeTest.v:81: Cannot find file containing module: 'okWireIn'\nokWireIn     wi00 (.ok1(ok1),                           .ep_addr(8'h00), .ep_dataout(ep00wire));\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/PipeTest.v:82: Cannot find file containing module: 'okWireIn'\nokWireIn     wi01 (.ok1(ok1),                           .ep_addr(8'h01), .ep_dataout(throttle_out));\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/PipeTest.v:83: Cannot find file containing module: 'okWireIn'\nokWireIn     wi02 (.ok1(ok1),                           .ep_addr(8'h02), .ep_dataout(throttle_in));\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/PipeTest.v:84: Cannot find file containing module: 'okWireOut'\nokWireOut    wo21 (.ok1(ok1), .ok2(ok2x[ 0*17 +: 17 ]), .ep_addr(8'h21), .ep_datain(rcv_errors));\n^~~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/PipeTest.v:85: Cannot find file containing module: 'okBTPipeIn'\nokBTPipeIn   ep80 (.ok1(ok1), .ok2(ok2x[ 1*17 +: 17 ]), .ep_addr(8'h80), .ep_write(pipe_in_write), .ep_blockstrobe(), .ep_dataout(pipe_in_data), .ep_ready(pipe_in_ready));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/PipeTest.v:86: Cannot find file containing module: 'okBTPipeOut'\nokBTPipeOut  epA0 (.ok1(ok1), .ok2(ok2x[ 2*17 +: 17 ]), .ep_addr(8'ha0), .ep_read(pipe_out_read),  .ep_blockstrobe(), .ep_datain(pipe_out_data), .ep_ready(pipe_out_ready));\n^~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module PipeTest(
	input  wire [7:0]  hi_in,
	output wire [1:0]  hi_out,
	inout  wire [15:0] hi_inout,
	inout  wire        hi_aa,

	output wire        i2c_sda,
	output wire        i2c_scl,
	output wire        hi_muxsel,

	input  wire        clk1,
	output wire [7:0]  led
	);


wire         ti_clk;
wire [30:0]  ok1;
wire [16:0]  ok2;

assign i2c_sda = 1'bz;
assign i2c_scl = 1'bz;
assign hi_muxsel = 1'b0;


wire [15:0]  ep00wire, throttle_in, throttle_out;
wire [15:0]  rcv_errors;

assign led = ~(rcv_errors[7:0]);


wire        pipe_in_write;
wire        pipe_in_ready;
wire [15:0] pipe_in_data;
pipe_in_check pic0 (.clk           (ti_clk),
                    .reset         (ep00wire[2]),
                    .pipe_in_write (pipe_in_write),
                    .pipe_in_data  (pipe_in_data),
                    .pipe_in_ready (pipe_in_ready),
                    .throttle_set  (ep00wire[5]),
                    .throttle_val  ({throttle_in, throttle_in}),
                    .mode          (ep00wire[4]),
                    .error_count   (rcv_errors)
                    );


wire        pipe_out_read;
wire        pipe_out_ready;
wire [15:0] pipe_out_data;
pipe_out_check poc0 (.clk            (ti_clk),
                     .reset          (ep00wire[2]),
                     .pipe_out_read  (pipe_out_read),
                     .pipe_out_data  (pipe_out_data),
                     .pipe_out_ready (pipe_out_ready),
                     .throttle_set   (ep00wire[5]),
                     .throttle_val   ({throttle_out, throttle_out}),
                     .mode           (ep00wire[4])
                     );
                                          


okHost okHI(
	.hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout), .hi_aa(hi_aa), .ti_clk(ti_clk),
	.ok1(ok1), .ok2(ok2));

wire [17*3-1:0]  ok2x;
okWireOR # (.N(3)) wireOR (ok2, ok2x);
okWireIn     wi00 (.ok1(ok1),                           .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireIn     wi01 (.ok1(ok1),                           .ep_addr(8'h01), .ep_dataout(throttle_out));
okWireIn     wi02 (.ok1(ok1),                           .ep_addr(8'h02), .ep_dataout(throttle_in));
okWireOut    wo21 (.ok1(ok1), .ok2(ok2x[ 0*17 +: 17 ]), .ep_addr(8'h21), .ep_datain(rcv_errors));
okBTPipeIn   ep80 (.ok1(ok1), .ok2(ok2x[ 1*17 +: 17 ]), .ep_addr(8'h80), .ep_write(pipe_in_write), .ep_blockstrobe(), .ep_dataout(pipe_in_data), .ep_ready(pipe_in_ready));
okBTPipeOut  epA0 (.ok1(ok1), .ok2(ok2x[ 2*17 +: 17 ]), .ep_addr(8'ha0), .ep_read(pipe_out_read),  .ep_blockstrobe(), .ep_datain(pipe_out_data), .ep_ready(pipe_out_ready));

endmodule
module PipeTest(
	input  wire [7:0]  hi_in,
	output wire [1:0]  hi_out,
	inout  wire [15:0] hi_inout,
	inout  wire        hi_aa,

	output wire        i2c_sda,
	output wire        i2c_scl,
	output wire        hi_muxsel,

	input  wire        clk1,
	output wire [7:0]  led
	);



wire         ti_clk;
wire [30:0]  ok1;
wire [16:0]  ok2;

assign i2c_sda = 1'bz;
assign i2c_scl = 1'bz;
assign hi_muxsel = 1'b0;


wire [15:0]  ep00wire, throttle_in, throttle_out;
wire [15:0]  rcv_errors;

assign led = ~(rcv_errors[7:0]);


wire        pipe_in_write;
wire        pipe_in_ready;
wire [15:0] pipe_in_data;
pipe_in_check pic0 (.clk           (ti_clk),
                    .reset         (ep00wire[2]),
                    .pipe_in_write (pipe_in_write),
                    .pipe_in_data  (pipe_in_data),
                    .pipe_in_ready (pipe_in_ready),
                    .throttle_set  (ep00wire[5]),
                    .throttle_val  ({throttle_in, throttle_in}),
                    .mode          (ep00wire[4]),
                    .error_count   (rcv_errors)
                    );


wire        pipe_out_read;
wire        pipe_out_ready;
wire [15:0] pipe_out_data;
pipe_out_check poc0 (.clk            (ti_clk),
                     .reset          (ep00wire[2]),
                     .pipe_out_read  (pipe_out_read),
                     .pipe_out_data  (pipe_out_data),
                     .pipe_out_ready (pipe_out_ready),
                     .throttle_set   (ep00wire[5]),
                     .throttle_val   ({throttle_out, throttle_out}),
                     .mode           (ep00wire[4])
                     );
                                          


okHost okHI(
	.hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout), .hi_aa(hi_aa), .ti_clk(ti_clk),
	.ok1(ok1), .ok2(ok2));

wire [17*3-1:0]  ok2x;
okWireOR # (.N(3)) wireOR (ok2, ok2x);
okWireIn     wi00 (.ok1(ok1),                           .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireIn     wi01 (.ok1(ok1),                           .ep_addr(8'h01), .ep_dataout(throttle_out));
okWireIn     wi02 (.ok1(ok1),                           .ep_addr(8'h02), .ep_dataout(throttle_in));
okWireOut    wo21 (.ok1(ok1), .ok2(ok2x[ 0*17 +: 17 ]), .ep_addr(8'h21), .ep_datain(rcv_errors));
okBTPipeIn   ep80 (.ok1(ok1), .ok2(ok2x[ 1*17 +: 17 ]), .ep_addr(8'h80), .ep_write(pipe_in_write), .ep_blockstrobe(), .ep_dataout(pipe_in_data), .ep_ready(pipe_in_ready));
okBTPipeOut  epA0 (.ok1(ok1), .ok2(ok2x[ 2*17 +: 17 ]), .ep_addr(8'ha0), .ep_read(pipe_out_read),  .ep_blockstrobe(), .ep_datain(pipe_out_data), .ep_ready(pipe_out_ready));

endmodule