data/full_repos/permissive/198223683/rtl/video/videosync.v
1: b"%Error: data/full_repos/permissive/198223683/rtl/video/videosync.v:146: Cannot find file containing module: 'FDM'\n FDM H272(RASTERC[2], MATCH_PAL, H272_Q);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/198223683/rtl/video,data/full_repos/permissive/198223683/FDM\n             data/full_repos/permissive/198223683/rtl/video,data/full_repos/permissive/198223683/FDM.v\n             data/full_repos/permissive/198223683/rtl/video,data/full_repos/permissive/198223683/FDM.sv\n             FDM\n             FDM.v\n             FDM.sv\n             obj_dir/FDM\n             obj_dir/FDM.v\n             obj_dir/FDM.sv\n%Error: data/full_repos/permissive/198223683/rtl/video/videosync.v:147: Cannot find file containing module: 'FDM'\n FDM I238(FLIP, H272_Q, BLANK_PAL);\n ^~~\n%Error: data/full_repos/permissive/198223683/rtl/video/videosync.v:153: Cannot find file containing module: 'FD4'\n FD4 J251(~RASTERC[4], MATCH_NTSC, 1'b1, nRESETP, BLANK_NTSC);\n ^~~\n%Error: Exiting due to 3 error(s)\n"
module videosync(
	input CLK_24MB,
	input LSPC_3M,
	input LSPC_1_5M,
	input Q53_CO,
	input nRESETP,
	input VMODE,
	output [8:0] PIXELC,
	output [8:0] RASTERC,
	output HSYNC,
	output VSYNC,
	output BNK,
	output BNKB,
	output CHBL,
	output R15_QD,
	output reg FLIP,
	output nFLIP,
	output reg P50_CO
);
	



	
	assign R15_QD = R15_REG[3];
	assign nFLIP = ~FLIP;
	
	
	always @(posedge CLK_24MB or negedge nRESETP)
	begin
		if (!nRESETP)
			FLIP <= 0;
		else
		begin
			if (({P15_Q[2:0], P50_Q} == 7'b0111111) & Q53_CO)
				FLIP <= ~FLIP;
		end
	end

	
	

	
	reg [3:0] P50_Q;
	reg [3:0] P15_Q;
	
	assign PIXELC = {P15_Q[2:0], P50_Q, LSPC_1_5M, LSPC_3M};
	
	always @(posedge CLK_24MB)
	begin

		if (!nRESETP)
		begin
			P50_Q <= 4'b1110;
			P50_CO <= 1'b0;
		end
		else
		begin
			if (Q53_CO)
			begin
				P50_Q <= P50_Q + 1'd1;
				P50_CO <= (P50_Q == 4'd14);
			end
		end
		



		if (~nRESETP | ((P15_Q == 4'd15) & (P50_Q == 4'd15) & Q53_CO))
			P15_Q <= {3'b101, ~nRESETP};
		else
		begin
			if (Q53_CO & P50_CO)
				P15_Q <= P15_Q + 1'd1;
		end
	end



	
	
	

	
	assign RASTERC = {J268_J269_Q, FLIP};
	
	reg [7:0] J268_J269_Q;
	always @(posedge CLK_24MB or negedge nRESETP)
	begin
		if (!nRESETP)
		begin
			J268_J269_Q <= 8'd0;
		end
		else
		begin
			if (({P15_Q[2:0], P50_Q} == 7'b0111111) & Q53_CO & FLIP)
			begin


				if (J268_J269_Q == 8'hFF)
					J268_J269_Q <= {3'b011, ~VMODE, ~VMODE, 3'b100};
				else
					J268_J269_Q <= J268_J269_Q + 1'd1;
			end
		end
	end
	



	

	wire MATCH_PAL = ~&{RASTERC[4:3]} | RASTERC[5] | RASTERC[8];
	
	wire H272_Q, BLANK_PAL;
	FDM H272(RASTERC[2], MATCH_PAL, H272_Q);
	FDM I238(FLIP, H272_Q, BLANK_PAL);
	

	wire MATCH_NTSC = ~&{RASTERC[7:5]};
	

	FD4 J251(~RASTERC[4], MATCH_NTSC, 1'b1, nRESETP, BLANK_NTSC);
	

	wire BLANK_NTSC;
	assign VSYNC = VMODE ? BLANK_PAL : RASTERC[8];
	assign BNK = ~(VMODE ? RASTERC[8] : BLANK_NTSC);
	

	assign BNKB = ~BNK;
	

	

	wire #1 nPIXEL_H256 = ~PIXELC[8];
	wire P13A_OUT = PIXELC[6] & nPIXEL_H256;
	
	reg [3:0] R15_REG;
	reg [3:0] T116_REG;
	reg [3:0] S122_REG;
	reg S116_Q;
	always @(posedge LSPC_1_5M)
	begin

		R15_REG <= {R15_REG[2:0], ~P13A_OUT};

		T116_REG <= {T116_REG[2:0], R15_REG[3]};

		S122_REG <= {S122_REG[2:0], T116_REG[3]};

		S116_Q <= S122_REG[3];
	end

	

	assign HSYNC = ~&{S116_Q, ~T116_REG[1]};
	


	

	assign CHBL = ~R15_REG[3];

endmodule
module videosync(
	input CLK_24MB,
	input LSPC_3M,
	input LSPC_1_5M,
	input Q53_CO,
	input nRESETP,
	input VMODE,
	output [8:0] PIXELC,
	output [8:0] RASTERC,
	output HSYNC,
	output VSYNC,
	output BNK,
	output BNKB,
	output CHBL,
	output R15_QD,
	output reg FLIP,
	output nFLIP,
	output reg P50_CO
);

	



	
	assign R15_QD = R15_REG[3];
	assign nFLIP = ~FLIP;
	
	
	always @(posedge CLK_24MB or negedge nRESETP)
	begin
		if (!nRESETP)
			FLIP <= 0;
		else
		begin
			if (({P15_Q[2:0], P50_Q} == 7'b0111111) & Q53_CO)
				FLIP <= ~FLIP;
		end
	end

	
	

	
	reg [3:0] P50_Q;
	reg [3:0] P15_Q;
	
	assign PIXELC = {P15_Q[2:0], P50_Q, LSPC_1_5M, LSPC_3M};
	
	always @(posedge CLK_24MB)
	begin

		if (!nRESETP)
		begin
			P50_Q <= 4'b1110;
			P50_CO <= 1'b0;
		end
		else
		begin
			if (Q53_CO)
			begin
				P50_Q <= P50_Q + 1'd1;
				P50_CO <= (P50_Q == 4'd14);
			end
		end
		



		if (~nRESETP | ((P15_Q == 4'd15) & (P50_Q == 4'd15) & Q53_CO))
			P15_Q <= {3'b101, ~nRESETP};
		else
		begin
			if (Q53_CO & P50_CO)
				P15_Q <= P15_Q + 1'd1;
		end
	end



	
	
	

	
	assign RASTERC = {J268_J269_Q, FLIP};
	
	reg [7:0] J268_J269_Q;
	always @(posedge CLK_24MB or negedge nRESETP)
	begin
		if (!nRESETP)
		begin
			J268_J269_Q <= 8'd0;
		end
		else
		begin
			if (({P15_Q[2:0], P50_Q} == 7'b0111111) & Q53_CO & FLIP)
			begin


				if (J268_J269_Q == 8'hFF)
					J268_J269_Q <= {3'b011, ~VMODE, ~VMODE, 3'b100};
				else
					J268_J269_Q <= J268_J269_Q + 1'd1;
			end
		end
	end
	



	

	wire MATCH_PAL = ~&{RASTERC[4:3]} | RASTERC[5] | RASTERC[8];
	
	wire H272_Q, BLANK_PAL;
	FDM H272(RASTERC[2], MATCH_PAL, H272_Q);
	FDM I238(FLIP, H272_Q, BLANK_PAL);
	

	wire MATCH_NTSC = ~&{RASTERC[7:5]};
	

	FD4 J251(~RASTERC[4], MATCH_NTSC, 1'b1, nRESETP, BLANK_NTSC);
	

	wire BLANK_NTSC;
	assign VSYNC = VMODE ? BLANK_PAL : RASTERC[8];
	assign BNK = ~(VMODE ? RASTERC[8] : BLANK_NTSC);
	

	assign BNKB = ~BNK;
	

	

	wire #1 nPIXEL_H256 = ~PIXELC[8];
	wire P13A_OUT = PIXELC[6] & nPIXEL_H256;
	
	reg [3:0] R15_REG;
	reg [3:0] T116_REG;
	reg [3:0] S122_REG;
	reg S116_Q;
	always @(posedge LSPC_1_5M)
	begin

		R15_REG <= {R15_REG[2:0], ~P13A_OUT};

		T116_REG <= {T116_REG[2:0], R15_REG[3]};

		S122_REG <= {S122_REG[2:0], T116_REG[3]};

		S116_Q <= S122_REG[3];
	end

	

	assign HSYNC = ~&{S116_Q, ~T116_REG[1]};
	


	

	assign CHBL = ~R15_REG[3];

endmodule