data/full_repos/permissive/174323821/hdl/ram/jtframe_obj_buffer.v
1: b"%Error: data/full_repos/permissive/174323821/hdl/ram/jtframe_obj_buffer.v:86: Cannot find file containing module: 'jtframe_dual_ram'\njtframe_dual_ram #(.aw(AW+1),.dw(DW)) u_line(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174323821/hdl/ram,data/full_repos/permissive/174323821/jtframe_dual_ram\n             data/full_repos/permissive/174323821/hdl/ram,data/full_repos/permissive/174323821/jtframe_dual_ram.v\n             data/full_repos/permissive/174323821/hdl/ram,data/full_repos/permissive/174323821/jtframe_dual_ram.sv\n             jtframe_dual_ram\n             jtframe_dual_ram.v\n             jtframe_dual_ram.sv\n             obj_dir/jtframe_dual_ram\n             obj_dir/jtframe_dual_ram.v\n             obj_dir/jtframe_dual_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module jtframe_obj_buffer #(parameter
    DW=8,
    AW=9,
    ALPHAW=4,
    ALPHA=32'HF,
    BLANK=ALPHA,
    BLANK_DLY=2,
    FLIP_OFFSET=0
)(
    input   clk,
    input   LHBL,
    input   flip,

    input   [DW-1:0] wr_data,
    input   [AW-1:0] wr_addr,
    input   we,

    input   [AW-1:0] rd_addr,
    input   rd,
    output reg [DW-1:0] rd_data
);

reg     line, last_LHBL;
wire    new_we = wr_data[ALPHAW-1:0] != ALPHA[ALPHAW-1:0] && we;

reg [BLANK_DLY-1:0] dly;
wire                delete_we = dly[0];
wire [DW-1:0]       blank_data = BLANK[DW-1:0];
wire [DW-1:0]       dump_data;

`ifdef SIMULATION
initial begin
    line = 0;
end
`endif

always @(posedge clk) begin
    last_LHBL <= LHBL;
    if( !LHBL && last_LHBL )
        line <= ~line;
end

always @(posedge clk) begin
    if( rd ) begin
        dly       <= { 1'b1, {BLANK_DLY-1{1'b0}}  };
    end else begin
        dly       <= dly>>1;
    end
    if( delete_we ) rd_data <= dump_data;
end

wire [AW-1:0] wr_af = flip ? ~wr_addr + FLIP_OFFSET[AW-1:0] : wr_addr;

jtframe_dual_ram #(.aw(AW+1),.dw(DW)) u_line(
    .clk0   ( clk           ),
    .clk1   ( clk           ),

    .data0  ( wr_data       ),
    .addr0  ( {line,wr_af}  ),
    .we0    ( new_we        ),
    .q0     (               ),

    .data1  ( blank_data    ),
    .addr1  ({~line,rd_addr}),
    .we1    ( delete_we     ),
    .q1     ( dump_data     )
);

endmodule
module jtframe_obj_buffer #(parameter
    DW=8,
    AW=9,
    ALPHAW=4,
    ALPHA=32'HF,
    BLANK=ALPHA,
    BLANK_DLY=2,
    FLIP_OFFSET=0
)(
    input   clk,
    input   LHBL,
    input   flip,

    input   [DW-1:0] wr_data,
    input   [AW-1:0] wr_addr,
    input   we,

    input   [AW-1:0] rd_addr,
    input   rd,
    output reg [DW-1:0] rd_data
);


reg     line, last_LHBL;
wire    new_we = wr_data[ALPHAW-1:0] != ALPHA[ALPHAW-1:0] && we;

reg [BLANK_DLY-1:0] dly;
wire                delete_we = dly[0];
wire [DW-1:0]       blank_data = BLANK[DW-1:0];
wire [DW-1:0]       dump_data;

`ifdef SIMULATION
initial begin
    line = 0;
end
`endif

always @(posedge clk) begin
    last_LHBL <= LHBL;
    if( !LHBL && last_LHBL )
        line <= ~line;
end

always @(posedge clk) begin
    if( rd ) begin
        dly       <= { 1'b1, {BLANK_DLY-1{1'b0}}  };
    end else begin
        dly       <= dly>>1;
    end
    if( delete_we ) rd_data <= dump_data;
end

wire [AW-1:0] wr_af = flip ? ~wr_addr + FLIP_OFFSET[AW-1:0] : wr_addr;

jtframe_dual_ram #(.aw(AW+1),.dw(DW)) u_line(
    .clk0   ( clk           ),
    .clk1   ( clk           ),

    .data0  ( wr_data       ),
    .addr0  ( {line,wr_af}  ),
    .we0    ( new_we        ),
    .q0     (               ),

    .data1  ( blank_data    ),
    .addr1  ({~line,rd_addr}),
    .we1    ( delete_we     ),
    .q1     ( dump_data     )
);

endmodule