data/full_repos/permissive/157979234/Semester III/Digital Design and Computer Organization/Session 07/mproc.v
1: b'%Error: Cannot find file containing module: III/Digital\n        ... Looked in:\n             data/full_repos/permissive/157979234/Semester/III/Digital\n             data/full_repos/permissive/157979234/Semester/III/Digital.v\n             data/full_repos/permissive/157979234/Semester/III/Digital.sv\n             III/Digital\n             III/Digital.v\n             III/Digital.sv\n             obj_dir/III/Digital\n             obj_dir/III/Digital.v\n             obj_dir/III/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Organization/Session\n%Error: Cannot find file containing module: 07,data/full_repos/permissive/157979234\n%Error: Cannot find file containing module: data/full_repos/permissive/157979234/Semester\n%Error: Cannot find file containing module: 07/mproc.v\n%Error: Exiting due to 8 error(s)\n'
module control_logic (input wire clk, reset, input wire [15:0] cur_ins, output wire [2:0] rd_addr_a, rd_addr_b, wr_addr, output wire [1:0] op, output wire pc_inc, load_ir, wr_reg);



  wire noro;
  wire dfro;

  nor5 p(cur_ins[15], cur_ins[14], cur_ins[13], cur_ins[12], cur_ins[11], noro);
  dfs d(clk,reset, dfro, pc_inc);
  dfr d1(clk,reset, pc_inc, load_ir);
  dfr d2(clk,reset,load_ir, dfro);
  and2 a(noro, dfro, wr_reg);

  assign rd_addr_a = cur_ins[2:0];
  assign rd_addr_b = cur_ins[5:3];
  assign wr_addr = cur_ins[8:6];
  assign op = cur_ins[10:9];

endmodule
module control_logic (input wire clk, reset, input wire [15:0] cur_ins, output wire [2:0] rd_addr_a, rd_addr_b, wr_addr, output wire [1:0] op, output wire pc_inc, load_ir, wr_reg);




  wire noro;
  wire dfro;

  nor5 p(cur_ins[15], cur_ins[14], cur_ins[13], cur_ins[12], cur_ins[11], noro);
  dfs d(clk,reset, dfro, pc_inc);
  dfr d1(clk,reset, pc_inc, load_ir);
  dfr d2(clk,reset,load_ir, dfro);
  and2 a(noro, dfro, wr_reg);

  assign rd_addr_a = cur_ins[2:0];
  assign rd_addr_b = cur_ins[5:3];
  assign wr_addr = cur_ins[8:6];
  assign op = cur_ins[10:9];

endmodule