data/full_repos/permissive/123366832/fpga/cpu_clockgen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/123366832/fpga/cpu_clockgen.v:13: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                           : ... In instance cpu_clockgen\n            if(clkDivCtr == 3\'h4) begin\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module cpu_clockgen(
    input CLK10MHZ,
    input rst_n,
    output reg CLK1MHZ
    );
    
    reg[3:0] clkDivCtr;
    always@(posedge CLK10MHZ or negedge rst_n) begin
        if(~rst_n) begin
            clkDivCtr <= 0;
            CLK1MHZ <= 0;
        end else begin
            if(clkDivCtr == 3'h4) begin
                CLK1MHZ <= ~CLK1MHZ;
                clkDivCtr <= 0;
            end else begin
                clkDivCtr <= clkDivCtr + 1;
            end
        end
    end

endmodule
module cpu_clockgen(
    input CLK10MHZ,
    input rst_n,
    output reg CLK1MHZ
    );

    
    reg[3:0] clkDivCtr;
    always@(posedge CLK10MHZ or negedge rst_n) begin
        if(~rst_n) begin
            clkDivCtr <= 0;
            CLK1MHZ <= 0;
        end else begin
            if(clkDivCtr == 3'h4) begin
                CLK1MHZ <= ~CLK1MHZ;
                clkDivCtr <= 0;
            end else begin
                clkDivCtr <= clkDivCtr + 1;
            end
        end
    end

endmodule