data/full_repos/permissive/174369527/ST7735S/st7735s.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/174369527/ST7735S/st7735s.v:78: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'r_bit_counter\' generates 3 bits.\n                                                                         : ... In instance st7735s\n                if (r_bit_counter == 8-1 & r_low_freq_counter == c_CLOCK_PER_SPI_HALF_BIT*2-1)\n                                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module st7735s 
#(
    parameter c_CLOCK_PER_SPI_HALF_BIT = 100
)
(
    input wire i_nrst,
    input wire i_clk,

    input wire i_ncommand,
    input wire [7:0] i_data,
    input wire i_data_rdy,

    output wire o_waiting,

    output reg o_spi_clk = 0,
    output wire o_spi_mosi,
    output reg o_spi_dc = 0,
    output wire o_spi_ss
);

parameter c_COUNTER_SIZE = $clog2(c_CLOCK_PER_SPI_HALF_BIT*2);

reg [c_COUNTER_SIZE-1:0] r_low_freq_counter = 0;

reg [3-1:0] r_bit_counter = 0;

reg [7:0] r_buffer = 0;

reg r_tx_en = 1'b0;



    always @(posedge i_clk or negedge i_nrst)
    begin
        if (~i_nrst)
            r_low_freq_counter <= 0;
        else
        begin
            if (r_tx_en)
                r_low_freq_counter <= r_low_freq_counter + 1;
            else
                r_low_freq_counter <= 0;
        end
    end


    always @(posedge i_clk or negedge i_nrst)
    begin
        if (~i_nrst)
            r_bit_counter <= 0;
        else
        begin
            if (r_tx_en)
                if (r_low_freq_counter == c_CLOCK_PER_SPI_HALF_BIT*2-1)
                    r_bit_counter <= r_bit_counter + 1;
                else
                    r_bit_counter <= r_bit_counter;
            else
                r_bit_counter <= 0;
        end
    end


    always @(posedge i_clk or negedge i_nrst)
    begin
        if (~i_nrst)
            r_tx_en <= 0;
        else
        begin
            if (~r_tx_en)
                if (i_data_rdy)
                    r_tx_en <= 1;
                else
                    r_tx_en <= 0;
            else
                if (r_bit_counter == 8-1 & r_low_freq_counter == c_CLOCK_PER_SPI_HALF_BIT*2-1)
                    r_tx_en <= 0;
                else
                    r_tx_en <= 1;
        end
    end
    assign o_waiting = ~r_tx_en;
    assign o_spi_ss = ~r_tx_en;


    always @(posedge i_clk)
    begin
        if (i_data_rdy)
            r_buffer <= i_data;
        else
            if (r_low_freq_counter == c_CLOCK_PER_SPI_HALF_BIT*2-1)
                r_buffer <= {r_buffer[6:0], 1'b0};
            else
                r_buffer <= r_buffer;
    end
    assign o_spi_mosi = r_buffer[7];


    always @(posedge i_clk)
    begin
        if (i_data_rdy)
            o_spi_dc <= i_ncommand;
        else
            o_spi_dc <= o_spi_dc;
    end


    always @(posedge i_clk or negedge i_nrst)
    begin
        if (~i_nrst)
            o_spi_clk <= 0;
        else
        begin
            if (r_low_freq_counter == c_CLOCK_PER_SPI_HALF_BIT | r_low_freq_counter == c_CLOCK_PER_SPI_HALF_BIT*2-1)
                o_spi_clk <= ~o_spi_clk;
            else
                o_spi_clk <= o_spi_clk;
        end
    end

endmodule
module st7735s 
#(
    parameter c_CLOCK_PER_SPI_HALF_BIT = 100
)
(
    input wire i_nrst,
    input wire i_clk,

    input wire i_ncommand,
    input wire [7:0] i_data,
    input wire i_data_rdy,

    output wire o_waiting,

    output reg o_spi_clk = 0,
    output wire o_spi_mosi,
    output reg o_spi_dc = 0,
    output wire o_spi_ss
);


parameter c_COUNTER_SIZE = $clog2(c_CLOCK_PER_SPI_HALF_BIT*2);

reg [c_COUNTER_SIZE-1:0] r_low_freq_counter = 0;

reg [3-1:0] r_bit_counter = 0;

reg [7:0] r_buffer = 0;

reg r_tx_en = 1'b0;



    always @(posedge i_clk or negedge i_nrst)
    begin
        if (~i_nrst)
            r_low_freq_counter <= 0;
        else
        begin
            if (r_tx_en)
                r_low_freq_counter <= r_low_freq_counter + 1;
            else
                r_low_freq_counter <= 0;
        end
    end


    always @(posedge i_clk or negedge i_nrst)
    begin
        if (~i_nrst)
            r_bit_counter <= 0;
        else
        begin
            if (r_tx_en)
                if (r_low_freq_counter == c_CLOCK_PER_SPI_HALF_BIT*2-1)
                    r_bit_counter <= r_bit_counter + 1;
                else
                    r_bit_counter <= r_bit_counter;
            else
                r_bit_counter <= 0;
        end
    end


    always @(posedge i_clk or negedge i_nrst)
    begin
        if (~i_nrst)
            r_tx_en <= 0;
        else
        begin
            if (~r_tx_en)
                if (i_data_rdy)
                    r_tx_en <= 1;
                else
                    r_tx_en <= 0;
            else
                if (r_bit_counter == 8-1 & r_low_freq_counter == c_CLOCK_PER_SPI_HALF_BIT*2-1)
                    r_tx_en <= 0;
                else
                    r_tx_en <= 1;
        end
    end
    assign o_waiting = ~r_tx_en;
    assign o_spi_ss = ~r_tx_en;


    always @(posedge i_clk)
    begin
        if (i_data_rdy)
            r_buffer <= i_data;
        else
            if (r_low_freq_counter == c_CLOCK_PER_SPI_HALF_BIT*2-1)
                r_buffer <= {r_buffer[6:0], 1'b0};
            else
                r_buffer <= r_buffer;
    end
    assign o_spi_mosi = r_buffer[7];


    always @(posedge i_clk)
    begin
        if (i_data_rdy)
            o_spi_dc <= i_ncommand;
        else
            o_spi_dc <= o_spi_dc;
    end


    always @(posedge i_clk or negedge i_nrst)
    begin
        if (~i_nrst)
            o_spi_clk <= 0;
        else
        begin
            if (r_low_freq_counter == c_CLOCK_PER_SPI_HALF_BIT | r_low_freq_counter == c_CLOCK_PER_SPI_HALF_BIT*2-1)
                o_spi_clk <= ~o_spi_clk;
            else
                o_spi_clk <= o_spi_clk;
        end
    end

endmodule