data/full_repos/permissive/205931224/source/src/writeback.v
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data/verilator_xmls/cc98d64a-6895-4396-b183-5bceb268e8b4.xml
module writeback(
input wire [1:0]        ctr_wb,
input wire [31:0]       mem_out,
input wire [31:0]       ALU_out,
output wire [31:0]      write_data,
output wire             regwrite_flag
    );
    
    wire memtoReg_flag;
    assign memtoReg_flag = ctr_wb[0];
    assign regwrite_flag = ctr_wb[1];
    
    assign write_data = (memtoReg_flag) ? mem_out : ALU_out;
  
endmodule
module writeback(
input wire [1:0]        ctr_wb,
input wire [31:0]       mem_out,
input wire [31:0]       ALU_out,
output wire [31:0]      write_data,
output wire             regwrite_flag
    );

    
    wire memtoReg_flag;
    assign memtoReg_flag = ctr_wb[0];
    assign regwrite_flag = ctr_wb[1];
    
    assign write_data = (memtoReg_flag) ? mem_out : ALU_out;
  
endmodule