data/full_repos/permissive/17622333/t_sha1.v
 line:35: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/17622333/t_sha1.v:38: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/17622333/t_sha1.v:53: Unsupported: Ignoring delay on this delayed statement.\n         #20 start <= 1\'b0;\n         ^\n%Error: data/full_repos/permissive/17622333/t_sha1.v:13: Cannot find file containing module: \'sha1\'\n   sha1 uut(\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/17622333,data/full_repos/permissive/17622333/sha1\n             data/full_repos/permissive/17622333,data/full_repos/permissive/17622333/sha1.v\n             data/full_repos/permissive/17622333,data/full_repos/permissive/17622333/sha1.sv\n             sha1\n             sha1.v\n             sha1.sv\n             obj_dir/sha1\n             obj_dir/sha1.v\n             obj_dir/sha1.sv\n%Warning-WIDTH: data/full_repos/permissive/17622333/t_sha1.v:34: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'bytes_returned\' generates 32 bits.\n                                                               : ... In instance t_sha1\n      msg_length = msg_length + bytes_returned;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/17622333/t_sha1.v:44: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'bytes_returned\' generates 32 bits.\n                                                               : ... In instance t_sha1\n         msg_length = msg_length + bytes_returned;\n                                 ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_sha1();
   reg           clk;
   reg           start;
   reg           eof;
   reg  [511:0]  data_block;
   reg  [ 63:0]  msg_length;
   wire [159:0]  hash;
   wire          next_block;
   wire          done;
   
   integer fpr, bytes_returned;

   sha1 uut(
      .clk(clk),
      .start(start),
      .eof(eof),
      .data_block(data_block),
      .msg_length(msg_length),
      .hash(hash),
      .next_block(next_block),
      .done(done)
   );
   
   initial begin
      clk = 1'b0;
      start = 1'b0;
      eof   = 1'b0;
      data_block = 512'd0;
      msg_length = 64'd0;
      
      fpr = $fopen("testvector3.tv", "rb");
      bytes_returned = $fread(data_block, fpr);
      if (bytes_returned == 0) eof = 1'b1;
      msg_length = msg_length + bytes_returned;
      pulse_start();
   end
   
   always #10 clk = ~clk;

   always @ (posedge clk) begin
      if (next_block) begin
         bytes_returned = $fread(data_block, fpr);
         if (bytes_returned == 0) eof = 1'b1;
         msg_length = msg_length + bytes_returned;
      end
      else if (done) end_simulation();
   end

   task pulse_start;
      begin

         start     <= 1'b1;
         #20 start <= 1'b0;
      end
   endtask
   
   task end_simulation;
      begin
         $display("Hexdigest: %h", hash);
         $fclose(fpr);
         $stop;
      end
   endtask
   
endmodule
module t_sha1();

   reg           clk;
   reg           start;
   reg           eof;
   reg  [511:0]  data_block;
   reg  [ 63:0]  msg_length;
   wire [159:0]  hash;
   wire          next_block;
   wire          done;
   
   integer fpr, bytes_returned;

   sha1 uut(
      .clk(clk),
      .start(start),
      .eof(eof),
      .data_block(data_block),
      .msg_length(msg_length),
      .hash(hash),
      .next_block(next_block),
      .done(done)
   );
   
   initial begin
      clk = 1'b0;
      start = 1'b0;
      eof   = 1'b0;
      data_block = 512'd0;
      msg_length = 64'd0;
      
      fpr = $fopen("testvector3.tv", "rb");
      bytes_returned = $fread(data_block, fpr);
      if (bytes_returned == 0) eof = 1'b1;
      msg_length = msg_length + bytes_returned;
      pulse_start();
   end
   
   always #10 clk = ~clk;

   always @ (posedge clk) begin
      if (next_block) begin
         bytes_returned = $fread(data_block, fpr);
         if (bytes_returned == 0) eof = 1'b1;
         msg_length = msg_length + bytes_returned;
      end
      else if (done) end_simulation();
   end

   task pulse_start;
      begin

         start     <= 1'b1;
         #20 start <= 1'b0;
      end
   endtask
   
   task end_simulation;
      begin
         $display("Hexdigest: %h", hash);
         $fclose(fpr);
         $stop;
      end
   endtask
   
endmodule