data/full_repos/permissive/143278/ivltests/analog1.v
 line:1: before: "nature"
1: b'%Error: data/full_repos/permissive/143278/ivltests/analog1.v:1: syntax error, unexpected IDENTIFIER\nnature Voltage;\n^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/analog1.v:24: syntax error, unexpected \'<\', expecting \',\' or \';\'\n   analog V(out) <+ abs(value);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/analog1.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (V(out) != abs(value)) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/analog1.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (V(out) != abs(value)) begin\n      ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module main;

   real value;
   voltage out;
   analog V(out) <+ abs(value);

   initial begin
      value = 1.0;
      #1 if (V(out) != abs(value)) begin
	 $display("FAILED -- value=%g, res=%g", value, V(out));
	 $finish;
      end

      value = -1.0;
      #1 if (V(out) != abs(value)) begin
	 $display("FAILED -- value=%g, res=%f", value, V(out));
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   real value;
   voltage out;
   analog V(out) <+ abs(value);

   initial begin
      value = 1.0;
      #1 if (V(out) != abs(value)) begin
	 $display("FAILED -- value=%g, res=%g", value, V(out));
	 $finish;
      end

      value = -1.0;
      #1 if (V(out) != abs(value)) begin
	 $display("FAILED -- value=%g, res=%f", value, V(out));
	 $finish;
      end

      $display("PASSED");
   end

endmodule