data/full_repos/permissive/174242803/src/top_tb.v
 line:28: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/174242803/src/top_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n         #(4*CLKPERIOD) reset <= 0;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174242803/src/top_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n         #FINISHTIME \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/src/top_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n   always #CLKPERIOD clk <= ~clk; \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/src/top_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #(4*CLKPERIOD)\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/src/top_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #(4*CLKPERIOD)\n        ^\n%Error: data/full_repos/permissive/174242803/src/top_tb.v:61: Unsupported or unknown PLI call: $shm_open\n  $shm_open("top_tb.db");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/174242803/src/top_tb.v:62: Unsupported or unknown PLI call: $shm_probe\n  $shm_probe(top_tb,"AS");\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb #(parameter WIDTH = 8, REGBITS = 3)();

   parameter FINISHTIME = 20000;
   parameter CLKPERIOD  = 2.225;


   reg clk = 0;
   reg reset = 1;


   mips_mem #(WIDTH,REGBITS) dut(.clk(clk),
                                 .reset(reset));


   initial
      begin
         reset <= 1; 
         #(4*CLKPERIOD) reset <= 0;
         #FINISHTIME 
	 $display("Finishing Simulation due to simulation constraint.");
	$finish; 
      end


   always #CLKPERIOD clk <= ~clk; 



   always@(negedge clk) begin
      if(dut.memwrite) begin
         if(dut.adr == 8'hff & dut.writedata == 8'h0D) begin
            $display("Fibonacci Simulation was successful!!!");
		      #(4*CLKPERIOD)
	         $display("Ending Simulation.");
            $finish;
		   end
         else begin 
            $display("Fibonacci Simulation has failed...");
            $display("Data at address FF should be 0D");
		      #(4*CLKPERIOD)
	         $display("Ending Simulation.");
            $finish;
         end
      end
   end

	initial	
	begin




		$shm_open("top_tb.db");
		$shm_probe(top_tb,"AS");

	end

endmodule
module top_tb #(parameter WIDTH = 8, REGBITS = 3)();


   parameter FINISHTIME = 20000;
   parameter CLKPERIOD  = 2.225;


   reg clk = 0;
   reg reset = 1;


   mips_mem #(WIDTH,REGBITS) dut(.clk(clk),
                                 .reset(reset));


   initial
      begin
         reset <= 1; 
         #(4*CLKPERIOD) reset <= 0;
         #FINISHTIME 
	 $display("Finishing Simulation due to simulation constraint.");
	$finish; 
      end


   always #CLKPERIOD clk <= ~clk; 



   always@(negedge clk) begin
      if(dut.memwrite) begin
         if(dut.adr == 8'hff & dut.writedata == 8'h0D) begin
            $display("Fibonacci Simulation was successful!!!");
		      #(4*CLKPERIOD)
	         $display("Ending Simulation.");
            $finish;
		   end
         else begin 
            $display("Fibonacci Simulation has failed...");
            $display("Data at address FF should be 0D");
		      #(4*CLKPERIOD)
	         $display("Ending Simulation.");
            $finish;
         end
      end
   end

	initial	
	begin




		$shm_open("top_tb.db");
		$shm_probe(top_tb,"AS");

	end

endmodule