data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/ddr2_test.v
1: b'%Warning-WIDTH: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/ddr2_test.v:72: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                                            : ... In instance ddr2_test\n  burst_cnt       <= 3\'b000;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/ddr2_test.v:114: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                                             : ... In instance ddr2_test\n    if (burst_cnt == 3\'d0) begin\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/ddr2_test.v:160: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                                             : ... In instance ddr2_test\n    if (burst_cnt == 3\'d0) begin\n                  ^~\n%Error: Exiting due to 3 warning(s)\n'
module ddr2_test
	(
	input  wire          clk,
	input  wire          reset,
	input  wire          writes_en,
	input  wire          reads_en,
	input  wire          calib_done, 

	output reg           ib_re,
	input  wire [63:0]   ib_data,
	input  wire [8:0]    ib_count,
	input  wire          ib_valid,
	input  wire          ib_empty,

	output reg           ob_we,
	output reg  [63:0]   ob_data,
	input  wire [8:0]    ob_count,
	
	output reg           p0_rd_en_o, 
	input  wire          p0_rd_empty,
	input  wire [31:0]   p0_rd_data,
	
	input  wire          p0_cmd_full,
	output reg           p0_cmd_en,
	output reg  [2:0]    p0_cmd_instr,
	output reg  [29:0]   p0_cmd_byte_addr,
	output wire [5:0]    p0_cmd_bl_o, 
	input  wire          p0_wr_full,
	output reg           p0_wr_en,
	output reg  [31:0]   p0_wr_data,
	output wire [3:0]    p0_wr_mask
	);

localparam BURST_LEN      = 32;


wire        rd_fifo_afull;
reg  [29:0] cmd_byte_addr_wr, cmd_byte_addr_rd;
reg  [5:0]  burst_cnt;

reg         write_mode;
reg         read_mode;
reg         reset_d;


assign p0_cmd_bl_o = BURST_LEN - 1;
assign p0_wr_mask = 4'b0000;

always @(posedge clk) write_mode <= writes_en;
always @(posedge clk) read_mode <= reads_en;
always @(posedge clk) reset_d <= reset;


integer state;
localparam s_idle  = 0,
           s_write1 = 10,
           s_write2 = 11,
           s_write3 = 12,
           s_write4 = 13,
           s_read1 = 20,
           s_read2 = 21,
           s_read3 = 22,
           s_read4 = 23,
           s_read5 = 24;
always @(posedge clk) begin
	if (reset_d) begin
		state           <= s_idle;
		burst_cnt       <= 3'b000;
		cmd_byte_addr_wr  <= 0;
		cmd_byte_addr_rd  <= 0;
		p0_cmd_instr <= 3'b0;
		p0_cmd_byte_addr <= 30'b0;
	end else begin
		p0_cmd_en  <= 1'b0;
		p0_wr_en <= 1'b0;
		ib_re <= 1'b0;
		p0_rd_en_o   <= 1'b0;
		ob_we <= 1'b0;


		case (state)
			s_idle: begin
				burst_cnt <= BURST_LEN;


				if (calib_done==1 && write_mode==1 && (ib_count >= BURST_LEN/2)) begin
					state <= s_write1;
				end else if (calib_done==1 && read_mode==1 && (ob_count<511-BURST_LEN/2) ) begin
					state <= s_read1;
				end
			end

			s_write1: begin
				state <= s_write2;
				ib_re <= 1'b1;
			end

			s_write2: begin
				if(ib_valid==1) begin
					p0_wr_data <= ib_data[31:0];
					p0_wr_en   <= 1'b1;
					burst_cnt <= burst_cnt - 2;
					state <= s_write3;
				end
			end
			
			s_write3: begin
				p0_wr_data <= ib_data[63:32];
				p0_wr_en   <= 1'b1;
				if (burst_cnt == 3'd0) begin
					state <= s_write4;
				end else begin
					state <= s_write1;
				end
			end
			
			s_write4: begin
				p0_cmd_en    <= 1'b1;
				p0_cmd_byte_addr    <= cmd_byte_addr_wr;
				cmd_byte_addr_wr <= cmd_byte_addr_wr + 4*BURST_LEN;
				p0_cmd_instr     <= 3'b000;
				state <= s_idle;
			end

			s_read1: begin
				p0_cmd_byte_addr    <= cmd_byte_addr_rd;
				cmd_byte_addr_rd <= cmd_byte_addr_rd + 4*BURST_LEN;
				p0_cmd_instr     <= 3'b001;
				p0_cmd_en    <= 1'b1;
				state <= s_read2;
			end
			
			s_read2: begin
				if(p0_rd_empty==0) begin
					p0_rd_en_o   <= 1'b1;
					state <= s_read3;
				end
			end
			
			s_read3: begin
				ob_data[31:0] <= p0_rd_data;
				if(p0_rd_empty==0) begin
					p0_rd_en_o <= 1'b1;
					state <= s_read4;
				end			
			end
			
			s_read4: begin
				ob_data[63:32] <= p0_rd_data;
				ob_we <= 1'b1;
				burst_cnt <= burst_cnt - 2;
				state <= s_read5;
			end
			
			s_read5: begin
				if (burst_cnt == 3'd0) begin
					state <= s_idle;
				end else begin
					state <= s_read2;
				end
			end
			
				
		endcase
	end
end


endmodule
module ddr2_test
	(
	input  wire          clk,
	input  wire          reset,
	input  wire          writes_en,
	input  wire          reads_en,
	input  wire          calib_done, 

	output reg           ib_re,
	input  wire [63:0]   ib_data,
	input  wire [8:0]    ib_count,
	input  wire          ib_valid,
	input  wire          ib_empty,

	output reg           ob_we,
	output reg  [63:0]   ob_data,
	input  wire [8:0]    ob_count,
	
	output reg           p0_rd_en_o, 
	input  wire          p0_rd_empty,
	input  wire [31:0]   p0_rd_data,
	
	input  wire          p0_cmd_full,
	output reg           p0_cmd_en,
	output reg  [2:0]    p0_cmd_instr,
	output reg  [29:0]   p0_cmd_byte_addr,
	output wire [5:0]    p0_cmd_bl_o, 
	input  wire          p0_wr_full,
	output reg           p0_wr_en,
	output reg  [31:0]   p0_wr_data,
	output wire [3:0]    p0_wr_mask
	);


localparam BURST_LEN      = 32;


wire        rd_fifo_afull;
reg  [29:0] cmd_byte_addr_wr, cmd_byte_addr_rd;
reg  [5:0]  burst_cnt;

reg         write_mode;
reg         read_mode;
reg         reset_d;


assign p0_cmd_bl_o = BURST_LEN - 1;
assign p0_wr_mask = 4'b0000;

always @(posedge clk) write_mode <= writes_en;
always @(posedge clk) read_mode <= reads_en;
always @(posedge clk) reset_d <= reset;


integer state;
localparam s_idle  = 0,
           s_write1 = 10,
           s_write2 = 11,
           s_write3 = 12,
           s_write4 = 13,
           s_read1 = 20,
           s_read2 = 21,
           s_read3 = 22,
           s_read4 = 23,
           s_read5 = 24;
always @(posedge clk) begin
	if (reset_d) begin
		state           <= s_idle;
		burst_cnt       <= 3'b000;
		cmd_byte_addr_wr  <= 0;
		cmd_byte_addr_rd  <= 0;
		p0_cmd_instr <= 3'b0;
		p0_cmd_byte_addr <= 30'b0;
	end else begin
		p0_cmd_en  <= 1'b0;
		p0_wr_en <= 1'b0;
		ib_re <= 1'b0;
		p0_rd_en_o   <= 1'b0;
		ob_we <= 1'b0;


		case (state)
			s_idle: begin
				burst_cnt <= BURST_LEN;


				if (calib_done==1 && write_mode==1 && (ib_count >= BURST_LEN/2)) begin
					state <= s_write1;
				end else if (calib_done==1 && read_mode==1 && (ob_count<511-BURST_LEN/2) ) begin
					state <= s_read1;
				end
			end

			s_write1: begin
				state <= s_write2;
				ib_re <= 1'b1;
			end

			s_write2: begin
				if(ib_valid==1) begin
					p0_wr_data <= ib_data[31:0];
					p0_wr_en   <= 1'b1;
					burst_cnt <= burst_cnt - 2;
					state <= s_write3;
				end
			end
			
			s_write3: begin
				p0_wr_data <= ib_data[63:32];
				p0_wr_en   <= 1'b1;
				if (burst_cnt == 3'd0) begin
					state <= s_write4;
				end else begin
					state <= s_write1;
				end
			end
			
			s_write4: begin
				p0_cmd_en    <= 1'b1;
				p0_cmd_byte_addr    <= cmd_byte_addr_wr;
				cmd_byte_addr_wr <= cmd_byte_addr_wr + 4*BURST_LEN;
				p0_cmd_instr     <= 3'b000;
				state <= s_idle;
			end

			s_read1: begin
				p0_cmd_byte_addr    <= cmd_byte_addr_rd;
				cmd_byte_addr_rd <= cmd_byte_addr_rd + 4*BURST_LEN;
				p0_cmd_instr     <= 3'b001;
				p0_cmd_en    <= 1'b1;
				state <= s_read2;
			end
			
			s_read2: begin
				if(p0_rd_empty==0) begin
					p0_rd_en_o   <= 1'b1;
					state <= s_read3;
				end
			end
			
			s_read3: begin
				ob_data[31:0] <= p0_rd_data;
				if(p0_rd_empty==0) begin
					p0_rd_en_o <= 1'b1;
					state <= s_read4;
				end			
			end
			
			s_read4: begin
				ob_data[63:32] <= p0_rd_data;
				ob_we <= 1'b1;
				burst_cnt <= burst_cnt - 2;
				state <= s_read5;
			end
			
			s_read5: begin
				if (burst_cnt == 3'd0) begin
					state <= s_idle;
				end else begin
					state <= s_read2;
				end
			end
			
				
		endcase
	end
end


endmodule