data/full_repos/permissive/18426314/verilog/xilinx/pmi_fifo.v
1: b"%Error: data/full_repos/permissive/18426314/verilog/xilinx/pmi_fifo.v:27: Cannot find file containing module: 'fifo_uart'\nfifo_uart fifo_uart_inst(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18426314/verilog/xilinx,data/full_repos/permissive/18426314/fifo_uart\n             data/full_repos/permissive/18426314/verilog/xilinx,data/full_repos/permissive/18426314/fifo_uart.v\n             data/full_repos/permissive/18426314/verilog/xilinx,data/full_repos/permissive/18426314/fifo_uart.sv\n             fifo_uart\n             fifo_uart.v\n             fifo_uart.sv\n             obj_dir/fifo_uart\n             obj_dir/fifo_uart.v\n             obj_dir/fifo_uart.sv\n%Error: Exiting due to 1 error(s)\n"
module pmi_fifo #(
	parameter pmi_data_width = 8,
	parameter pmi_data_depth = 16,
	parameter pmi_full_flag = 16,
	parameter pmi_empty_flag = 0,
	parameter pmi_almost_full_flag = 1,
	parameter pmi_almost_empty_flag = 0,
	parameter pmi_regmode = "noreg",
	parameter pmi_family = 0,
	parameter module_type = "pmi_fifo",
	parameter pmi_implementation = "LUT"
)(
	input wire [pmi_data_width - 1 : 0] Data,
	input wire Clock,
	input wire WrEn,
	input wire RdEn,
	input wire Reset,
	output wire [pmi_data_width - 1 : 0] Q,
	output wire Empty,
	output wire Full,
	output wire AlmostEmpty,
	output wire AlmostFull
);   

fifo_uart fifo_uart_inst(
	.clk(Clock),
	.srst(Reset),
	.din(Data),
	.wr_en(WrEn),
	.rd_en(RdEn),
	.dout(Q),
	.full(Full),
	.almost_full(AlmostFull),
	.empty(Empty),
	.almost_empty(AlmostEmpty)
);

endmodule
module pmi_fifo #(
	parameter pmi_data_width = 8,
	parameter pmi_data_depth = 16,
	parameter pmi_full_flag = 16,
	parameter pmi_empty_flag = 0,
	parameter pmi_almost_full_flag = 1,
	parameter pmi_almost_empty_flag = 0,
	parameter pmi_regmode = "noreg",
	parameter pmi_family = 0,
	parameter module_type = "pmi_fifo",
	parameter pmi_implementation = "LUT"
)(
	input wire [pmi_data_width - 1 : 0] Data,
	input wire Clock,
	input wire WrEn,
	input wire RdEn,
	input wire Reset,
	output wire [pmi_data_width - 1 : 0] Q,
	output wire Empty,
	output wire Full,
	output wire AlmostEmpty,
	output wire AlmostFull
);
   

fifo_uart fifo_uart_inst(
	.clk(Clock),
	.srst(Reset),
	.din(Data),
	.wr_en(WrEn),
	.rd_en(RdEn),
	.dout(Q),
	.full(Full),
	.almost_full(AlmostFull),
	.empty(Empty),
	.almost_empty(AlmostEmpty)
);

endmodule