data/full_repos/permissive/211316121/lab5_1/FlipFlop.v
data/verilator_xmls/d8ef6967-f9c6-4ff4-9a6d-83398a96c8b5.xml
module Top_FF(
    input [9:0] sw,
    input clkstd,
    output [5:0] led
);

wire clk;

CLKDIV top_div(clkstd,clk);

DFF top_dff(sw[2],clk,sw[1],sw[0],led[1],led[0]);
JKFF top_jkff(sw[6],sw[5],clk,sw[4],sw[3],led[3],led[2]);
TFF top_tff(sw[9],clk,sw[8],sw[7],led[5],led[4]);


endmodule
module Top_FF(
    input [9:0] sw,
    input clkstd,
    output [5:0] led
);


wire clk;

CLKDIV top_div(clkstd,clk);

DFF top_dff(sw[2],clk,sw[1],sw[0],led[1],led[0]);
JKFF top_jkff(sw[6],sw[5],clk,sw[4],sw[3],led[3],led[2]);
TFF top_tff(sw[9],clk,sw[8],sw[7],led[5],led[4]);


endmodule