data/full_repos/permissive/162874044/HDL Files/DE.v
 line:24: before: "("
1: b'%Error: Cannot find file containing module: Files,data/full_repos/permissive/162874044\n        ... Looked in:\n             data/full_repos/permissive/162874044/HDL/Files,data/full_repos/permissive/162874044\n             data/full_repos/permissive/162874044/HDL/Files,data/full_repos/permissive/162874044.v\n             data/full_repos/permissive/162874044/HDL/Files,data/full_repos/permissive/162874044.sv\n             Files,data/full_repos/permissive/162874044\n             Files,data/full_repos/permissive/162874044.v\n             Files,data/full_repos/permissive/162874044.sv\n             obj_dir/Files,data/full_repos/permissive/162874044\n             obj_dir/Files,data/full_repos/permissive/162874044.v\n             obj_dir/Files,data/full_repos/permissive/162874044.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/162874044/HDL\n%Error: Cannot find file containing module: Files/DE.v\n%Error: Exiting due to 3 error(s)\n'
module DE #( 
	parameter busWidth = 11,
	parameter [ ( busWidth - 1 ) : 0 ] resHorizontal 	= 1920,
	parameter [ ( busWidth - 1 ) : 0 ] resVertical		= 1080
)
(
	input 							hSync,



	input [ (busWidth - 1) : 0]		vCount,
	output 							deOut
);


	reg deReg = 1'b0;
	reg [ ( busWidth - 1 ) : 0 ] counter = 1'b0;


	assign deOut = deReg;

	always @( posedge( hSync ) )
		begin



			if( counter == resHorizontal )
				begin
					deReg 	= 1'b0;
					counter	= 1'b0;
				end

			else
				begin
					deReg 	= 1'b1;
					counter = counter + 1'b1;
				end


		end
endmodule
module DE #( 
	parameter busWidth = 11,
	parameter [ ( busWidth - 1 ) : 0 ] resHorizontal 	= 1920,
	parameter [ ( busWidth - 1 ) : 0 ] resVertical		= 1080
)
(
	input 							hSync,



	input [ (busWidth - 1) : 0]		vCount,
	output 							deOut
);



	reg deReg = 1'b0;
	reg [ ( busWidth - 1 ) : 0 ] counter = 1'b0;


	assign deOut = deReg;

	always @( posedge( hSync ) )
		begin



			if( counter == resHorizontal )
				begin
					deReg 	= 1'b0;
					counter	= 1'b0;
				end

			else
				begin
					deReg 	= 1'b1;
					counter = counter + 1'b1;
				end


		end
endmodule