data/full_repos/permissive/154352170/IF_ID.v
data/verilator_xmls/51e88c33-4065-4a63-bb60-f6454a0248f0.xml
module IF_ID(
    input clk,
    input reset,
    input IF_ID_En,
	 input [31:0] IR_In, 
	 input [31:0] PC_Out_In,
	 output [31:0] IR_Out,
	 output [31:0] PC_Out_Out
    );
	 
	 reg [31:0] IF_ID_IR;
	 reg [31:0] IF_ID_PC;
	 
	 assign IR_Out = IF_ID_IR;
	 assign PC_Out_Out = IF_ID_PC;
	 
	 initial begin
       IF_ID_IR = 0;
		 IF_ID_PC = 0;
	 end
	 
	 always @ (posedge clk) begin
	    
		 if (reset) begin
		    IF_ID_IR <= 0;
			 IF_ID_PC <= 0;
		 end
		 
		 else if (IF_ID_En == 1) begin
		    IF_ID_IR <= IR_In;
			 IF_ID_PC <= PC_Out_In;
		 end
		 
	 end
	 
endmodule
module IF_ID(
    input clk,
    input reset,
    input IF_ID_En,
	 input [31:0] IR_In, 
	 input [31:0] PC_Out_In,
	 output [31:0] IR_Out,
	 output [31:0] PC_Out_Out
    );

	 
	 reg [31:0] IF_ID_IR;
	 reg [31:0] IF_ID_PC;
	 
	 assign IR_Out = IF_ID_IR;
	 assign PC_Out_Out = IF_ID_PC;
	 
	 initial begin
       IF_ID_IR = 0;
		 IF_ID_PC = 0;
	 end
	 
	 always @ (posedge clk) begin
	    
		 if (reset) begin
		    IF_ID_IR <= 0;
			 IF_ID_PC <= 0;
		 end
		 
		 else if (IF_ID_En == 1) begin
		    IF_ID_IR <= IR_In;
			 IF_ID_PC <= PC_Out_In;
		 end
		 
	 end
	 
endmodule