data/full_repos/permissive/202237519/verilog/digitalsystem5/line_decoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/line_decoder.v:19: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n                                                                                             : ... In instance line_decoder\n    default : S <= {dummy};\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module line_decoder(A,S);

input [3:0] A;
output reg[3:0] S;
reg dummy;

always@(A)
    case(A)
    4'b0000 : S <= 4'b0000;
    4'b0001 : S <= 4'b0001;
    4'b0010 : S <= 4'b0010;
    4'b0011 : S <= 4'b0011;
    4'b0100 : S <= 4'b0100;
    4'b0101 : S <= 4'b1000;
    4'b0110 : S <= 4'b1001;
    4'b0111 : S <= 4'b1010;
    4'b1000 : S <= 4'b1011;
    4'b1001 : S <= 4'b1100;
    default : S <= {dummy};
    endcase
endmodule
module line_decoder(A,S);


input [3:0] A;
output reg[3:0] S;
reg dummy;

always@(A)
    case(A)
    4'b0000 : S <= 4'b0000;
    4'b0001 : S <= 4'b0001;
    4'b0010 : S <= 4'b0010;
    4'b0011 : S <= 4'b0011;
    4'b0100 : S <= 4'b0100;
    4'b0101 : S <= 4'b1000;
    4'b0110 : S <= 4'b1001;
    4'b0111 : S <= 4'b1010;
    4'b1000 : S <= 4'b1011;
    4'b1001 : S <= 4'b1100;
    default : S <= {dummy};
    endcase
endmodule