data/full_repos/permissive/204937464/lib/verilog/passthrough.v
None: at end of input
data/verilator_xmls/7afa0f50-56f2-481b-99bc-59741cd13399.xml
module passthrough(
  clk,
  rst,
  op_din_en,
  op_din_eop,
  op_din,
  op_dout
);

parameter Q = 8;
parameter RELU = 0;

input clk;
input rst;
input op_din_en;
input op_din_eop;
input [15:0] op_din;
output [15:0] op_dout;

assign op_dout = op_din;

endmodule
module passthrough(
  clk,
  rst,
  op_din_en,
  op_din_eop,
  op_din,
  op_dout
);


parameter Q = 8;
parameter RELU = 0;

input clk;
input rst;
input op_din_en;
input op_din_eop;
input [15:0] op_din;
output [15:0] op_dout;

assign op_dout = op_din;

endmodule