data/full_repos/permissive/127241521/blinker/clock.v
data/verilator_xmls/1600ea30-5288-47d8-891f-07823afbca1a.xml
module clock(input clk, input rst, output tc); 
 
reg [25:0] clk_div;

always @(posedge clk)
    if(rst)
	     clk_div <= 0;
    else
	     if(tc)
		      clk_div <= 0;
		  else
	         clk_div <= clk_div + 1; 
 
assign tc = (clk_div == 49999999); 


endmodule
module clock(input clk, input rst, output tc);
 
 
reg [25:0] clk_div;

always @(posedge clk)
    if(rst)
	     clk_div <= 0;
    else
	     if(tc)
		      clk_div <= 0;
		  else
	         clk_div <= clk_div + 1; 
 
assign tc = (clk_div == 49999999); 


endmodule