data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Division/fp_Divide_tb.v
 line:56: before: "integer"
1: b'%Error: Cannot find file containing module: Project/SourceCode/Division,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Division,data/full_repos/permissive/119107706\n             Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Division/fp_Divide_tb.v\n%Error: Exiting due to 3 error(s)\n'
module fp_Divide_tb;

	parameter 
				WI1 = 12,
				WF1 = 12,
				WI2 = 12,
				WF2 = 12,
				WL1 = WI1 + WF1,	 
				WL2 = WI2 + WF2,
				WIO = 12,
				WFO = 12,
				WLO = WIO + WFO,
				LUT_bits = 24,
				LUT_addWidth = 12;


	reg CLK;
	reg nRST;
	reg CE;
	reg [WL1-1:0] OP1;
	reg [WL2-1:0] OP2;


	wire [WLO-1:0] dout;


	real real_OP1, real_OP2;
	real real_dout;


	function integer log2;
		input integer n;
		begin
			log2 = 0;
			while (2**log2<n) begin
				log2 = log2 + 1;
			end
		end
	endfunction


	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction
	

	function real fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF-1; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		fixedToFloat = retVal - (in[WI+WF-1] * (2.0**(WI-1)));
		end
	endfunction

	



	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;



	fp_Divide 
	#
	(
		.WI1(WI1),
		.WF1(WF1),
		.WI2(WI2),
		.WF2(WF2),
		.WIO(WIO),
		.WFO(WFO),
		.LUT_addWidth(LUT_addWidth),
		.LUT_bits(LUT_bits)
	)
	Fang_Divider 
	(
		.CLK(CLK), 
		.nRST(nRST), 
		.CE(CE), 
		.OP1(OP1), 
		.OP2(OP2), 
		.dout(dout)
	);

	initial begin

		$readmemb("LUT_rec_Hung_prar_24bit.txt", fp_Divide_tb.Fang_Divider.Fang_fp_sRec.Fang_Reciprocal_Hung.LUT); 
		

		nRST = 0; CE = 0;
		@(posedge CLK); CE = 1; 
		nRST = 1;

		OP1 = 24'b000000000001_100000000000; OP2 = 24'b000000001001_100000000000; @(posedge CLK);
		OP1 = 24'b000001011001_100000000000; OP2 = 24'b000000001111_100110000000; @(posedge CLK);
		OP1 = 24'b000000000000_001110000000; OP2 = 24'b000000000000_001011000000; @(posedge CLK);


		$finish;
        


	end


	always @ OP1 real_OP1 = fixedToFloat(OP1, WI1, WF1);
	always @ OP2 real_OP2 = fixedToFloat(OP2, WI2, WF2);


	always @ dout real_dout = fixedToFloat(dout, WIO, WFO);

endmodule
module fp_Divide_tb;


	parameter 
				WI1 = 12,
				WF1 = 12,
				WI2 = 12,
				WF2 = 12,
				WL1 = WI1 + WF1,	 
				WL2 = WI2 + WF2,
				WIO = 12,
				WFO = 12,
				WLO = WIO + WFO,
				LUT_bits = 24,
				LUT_addWidth = 12;


	reg CLK;
	reg nRST;
	reg CE;
	reg [WL1-1:0] OP1;
	reg [WL2-1:0] OP2;


	wire [WLO-1:0] dout;


	real real_OP1, real_OP2;
	real real_dout;


	function integer log2;
		input integer n;
		begin
			log2 = 0;
			while (2**log2<n) begin
				log2 = log2 + 1;
			end
		end
	endfunction


	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction
	

	function real fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF-1; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		fixedToFloat = retVal - (in[WI+WF-1] * (2.0**(WI-1)));
		end
	endfunction

	



	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;



	fp_Divide 
	#
	(
		.WI1(WI1),
		.WF1(WF1),
		.WI2(WI2),
		.WF2(WF2),
		.WIO(WIO),
		.WFO(WFO),
		.LUT_addWidth(LUT_addWidth),
		.LUT_bits(LUT_bits)
	)
	Fang_Divider 
	(
		.CLK(CLK), 
		.nRST(nRST), 
		.CE(CE), 
		.OP1(OP1), 
		.OP2(OP2), 
		.dout(dout)
	);

	initial begin

		$readmemb("LUT_rec_Hung_prar_24bit.txt", fp_Divide_tb.Fang_Divider.Fang_fp_sRec.Fang_Reciprocal_Hung.LUT); 
		

		nRST = 0; CE = 0;
		@(posedge CLK); CE = 1; 
		nRST = 1;

		OP1 = 24'b000000000001_100000000000; OP2 = 24'b000000001001_100000000000; @(posedge CLK);
		OP1 = 24'b000001011001_100000000000; OP2 = 24'b000000001111_100110000000; @(posedge CLK);
		OP1 = 24'b000000000000_001110000000; OP2 = 24'b000000000000_001011000000; @(posedge CLK);


		$finish;
        


	end


	always @ OP1 real_OP1 = fixedToFloat(OP1, WI1, WF1);
	always @ OP2 real_OP2 = fixedToFloat(OP2, WI2, WF2);


	always @ dout real_dout = fixedToFloat(dout, WIO, WFO);

endmodule