data/full_repos/permissive/128659832/verilog/RAND.v
 line:26 column:19: Illegal character "'"
data/verilator_xmls/5a7cd2db-978e-45b5-be07-0bcb69fe935c.xml
module RAND (
        input  wire       clk,
        input  wire [7:0] addr,
        input  wire       write_en,
        input  wire       rst,
        input  wire [7:0] din,
        output wire [7:0] dout
    );

    localparam

        SEED  = {7'h01, 8'h77},
        RULE  = 8'd 30,
        WIDTH = 15;

    reg ini = 0;
    always @(posedge(clk))
        ini <= 1;

    wire [WIDTH-1:0] in; 
    wire [WIDTH-1:0] out;

    genvar i;
    generate
        for (i=0; i<WIDTH; i=i+1)
        begin : automaton_cell
            CA_cell ca_cell( { in[ (i==0) ? WIDTH-1 : (i-1) ], in[i], in[ ( i == (WIDTH-1) ) ? 0 : i+1 ] }, RULE, out[i] );
        end 
    endgenerate

    reg [WIDTH-1:0] q = 0;

    always @(posedge(clk))
        if( ini == 0 ) q <= SEED;
        else if( write_en ) q <= {7'h01,din};
        else q <= out;

    assign in = q;



    reg [7:0] z = 0;

    always @(posedge(clk))
        if( ini == 0 ) z <= 8'h77;
        else z <= { z[6:0], out[7]};

    assign dout = z;

endmodule
module RAND (
        input  wire       clk,
        input  wire [7:0] addr,
        input  wire       write_en,
        input  wire       rst,
        input  wire [7:0] din,
        output wire [7:0] dout
    );


    localparam

        SEED  = {7'h01, 8'h77},
        RULE  = 8'd 30,
        WIDTH = 15;

    reg ini = 0;
    always @(posedge(clk))
        ini <= 1;

    wire [WIDTH-1:0] in; 
    wire [WIDTH-1:0] out;

    genvar i;
    generate
        for (i=0; i<WIDTH; i=i+1)
        begin : automaton_cell
            CA_cell ca_cell( { in[ (i==0) ? WIDTH-1 : (i-1) ], in[i], in[ ( i == (WIDTH-1) ) ? 0 : i+1 ] }, RULE, out[i] );
        end 
    endgenerate

    reg [WIDTH-1:0] q = 0;

    always @(posedge(clk))
        if( ini == 0 ) q <= SEED;
        else if( write_en ) q <= {7'h01,din};
        else q <= out;

    assign in = q;



    reg [7:0] z = 0;

    always @(posedge(clk))
        if( ini == 0 ) z <= 8'h77;
        else z <= { z[6:0], out[7]};

    assign dout = z;

endmodule