data/full_repos/permissive/188434311/verilog/register_slice/synchronizer/synchronizer_n.v
data/verilator_xmls/638da9e5-300e-495e-8554-564970fa6e50.xml
module synchonizer_n(
    input  wire  clki,
    input  wire  rstn,
    input  wire  data_i,
    output wire  data_o
);

`ifdef __FOR_SIM__

reg  data_reg;

assign data_o = data_reg;

always @( posedge clki or posedge rstn )
  if( ~ rstn )
    data_reg <= 1'b0;
  else
    data_reg <= data_i;

`else

`ifdef  __FOR_ASIC__

`endif

`endif


endmodule
module synchonizer_n(
    input  wire  clki,
    input  wire  rstn,
    input  wire  data_i,
    output wire  data_o
);


`ifdef __FOR_SIM__

reg  data_reg;

assign data_o = data_reg;

always @( posedge clki or posedge rstn )
  if( ~ rstn )
    data_reg <= 1'b0;
  else
    data_reg <= data_i;

`else

`ifdef  __FOR_ASIC__

`endif

`endif


endmodule