data/full_repos/permissive/158845296/decoder.v
1: b'%Error: data/full_repos/permissive/158845296/decoder.v:20: Cannot find include file: parameters.v\n    `include "parameters.v" \n             ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158845296,data/full_repos/permissive/158845296/parameters.v\n             data/full_repos/permissive/158845296,data/full_repos/permissive/158845296/parameters.v.v\n             data/full_repos/permissive/158845296,data/full_repos/permissive/158845296/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: data/full_repos/permissive/158845296/decoder.v:55: Define or directive not defined: \'`OP_ADD\'\n            `OP_ADD : mem_access <= 5\'b00010;\n            ^~~~~~~\n%Error: data/full_repos/permissive/158845296/decoder.v:55: syntax error, unexpected \':\', expecting endcase\n            `OP_ADD : mem_access <= 5\'b00010;\n                    ^\n%Error: data/full_repos/permissive/158845296/decoder.v:56: Define or directive not defined: \'`OP_SUB\'\n            `OP_SUB : mem_access <= 5\'b00010;\n            ^~~~~~~\n%Error: data/full_repos/permissive/158845296/decoder.v:57: Define or directive not defined: \'`OP_MUL\'\n            `OP_MUL : mem_access <= 5\'b00010;\n            ^~~~~~~\n%Error: data/full_repos/permissive/158845296/decoder.v:58: Define or directive not defined: \'`OP_LDB\'\n            `OP_LDB : mem_access <= 5\'b10101;\n            ^~~~~~~\n%Error: data/full_repos/permissive/158845296/decoder.v:59: Define or directive not defined: \'`OP_LDW\'\n            `OP_LDW : mem_access <= 5\'b10001;\n            ^~~~~~~\n%Error: data/full_repos/permissive/158845296/decoder.v:60: Define or directive not defined: \'`OP_STB\'\n            `OP_STB : mem_access <= 5\'b01100;\n            ^~~~~~~\n%Error: data/full_repos/permissive/158845296/decoder.v:61: Define or directive not defined: \'`OP_STW\'\n            `OP_STW : mem_access <= 5\'b01000;\n            ^~~~~~~\n%Error: Cannot continue\n'
module decoder
(
    input  [31:0] instruction,
    output [6:0]  opcode,
    output [4:0]  dst_reg,
    output [4:0]  src_reg_1,
    output [4:0]  src_reg_2,
    output [31:0] mem_offset,
    output [31:0] brn_offset,
    output [19:0] jmp_offset,
    
    output alu_imm_src,
    output mem_read,
    output mem_write,
    output mem_byte,
    output reg_write,
    output mem_to_reg
);

    `include "parameters.v"

    reg   [4:0] mem_access;
    wire [14:0] short_mem_offset;
    wire [14:0] short_brn_offset;
    wire [29:0] long_brn_offset;


    assign opcode     = instruction[31:25];
    assign dst_reg    = instruction[24:20];
    assign src_reg_1  = instruction[19:15];
    assign src_reg_2  = instruction[14:10];
    assign jmp_offset = {instruction[24:20], instruction[14:0]};
    

    assign short_mem_offset = instruction[14:0];
    assign mem_offset       = (short_mem_offset[14]) ? {17'h1FFFF, short_mem_offset} : {17'h0000, short_mem_offset};


    assign short_brn_offset = {instruction[24:20], instruction[9:0]};
    assign long_brn_offset  = (short_brn_offset[14]) ? {15'h7FFF, short_brn_offset} : {15'h0000, short_brn_offset};
    assign brn_offset       = {long_brn_offset, 2'b00};


    assign mem_read   = mem_access[4];
    assign mem_write  = mem_access[3];
    assign mem_byte   = mem_access[2];
    assign reg_write  = mem_access[1];
    assign mem_to_reg = mem_access[0];
    

    assign alu_imm_src = mem_read || mem_write;

    always @(*) begin
        case (opcode)
            `OP_ADD : mem_access <= 5'b00010;
            `OP_SUB : mem_access <= 5'b00010;
            `OP_MUL : mem_access <= 5'b00010;
            `OP_LDB : mem_access <= 5'b10101;
            `OP_LDW : mem_access <= 5'b10001;
            `OP_STB : mem_access <= 5'b01100;
            `OP_STW : mem_access <= 5'b01000;
            default : mem_access <= 5'b00000;
        endcase
    end

endmodule
module decoder
(
    input  [31:0] instruction,
    output [6:0]  opcode,
    output [4:0]  dst_reg,
    output [4:0]  src_reg_1,
    output [4:0]  src_reg_2,
    output [31:0] mem_offset,
    output [31:0] brn_offset,
    output [19:0] jmp_offset,
    
    output alu_imm_src,
    output mem_read,
    output mem_write,
    output mem_byte,
    output reg_write,
    output mem_to_reg
);


    `include "parameters.v"

    reg   [4:0] mem_access;
    wire [14:0] short_mem_offset;
    wire [14:0] short_brn_offset;
    wire [29:0] long_brn_offset;


    assign opcode     = instruction[31:25];
    assign dst_reg    = instruction[24:20];
    assign src_reg_1  = instruction[19:15];
    assign src_reg_2  = instruction[14:10];
    assign jmp_offset = {instruction[24:20], instruction[14:0]};
    

    assign short_mem_offset = instruction[14:0];
    assign mem_offset       = (short_mem_offset[14]) ? {17'h1FFFF, short_mem_offset} : {17'h0000, short_mem_offset};


    assign short_brn_offset = {instruction[24:20], instruction[9:0]};
    assign long_brn_offset  = (short_brn_offset[14]) ? {15'h7FFF, short_brn_offset} : {15'h0000, short_brn_offset};
    assign brn_offset       = {long_brn_offset, 2'b00};


    assign mem_read   = mem_access[4];
    assign mem_write  = mem_access[3];
    assign mem_byte   = mem_access[2];
    assign reg_write  = mem_access[1];
    assign mem_to_reg = mem_access[0];
    

    assign alu_imm_src = mem_read || mem_write;

    always @(*) begin
        case (opcode)
            `OP_ADD : mem_access <= 5'b00010;
            `OP_SUB : mem_access <= 5'b00010;
            `OP_MUL : mem_access <= 5'b00010;
            `OP_LDB : mem_access <= 5'b10101;
            `OP_LDW : mem_access <= 5'b10001;
            `OP_STB : mem_access <= 5'b01100;
            `OP_STW : mem_access <= 5'b01000;
            default : mem_access <= 5'b00000;
        endcase
    end

endmodule