data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:1: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Mips/Type/Word.v\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Mips/Type/Word.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Mips/Type/Word.v.sv\n             Mips/Type/Word.v\n             Mips/Type/Word.v.v\n             Mips/Type/Word.v.sv\n             obj_dir/Mips/Type/Word.v\n             obj_dir/Mips/Type/Word.v.v\n             obj_dir/Mips/Type/Word.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:2: Cannot find include file: Mips/Type/RegPorts.v\n`include "Mips/Type/RegPorts.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:4: Cannot find include file: Mips/Pipeline/Fwd/Ex.v\n`include "Mips/Pipeline/Fwd/Ex.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:5: Cannot find include file: Mips/Pipeline/Ex/Fwd.v\n`include "Mips/Pipeline/Ex/Fwd.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:6: Cannot find include file: Mips/Pipeline/Reg/Fwd.v\n`include "Mips/Pipeline/Reg/Fwd.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:7: Cannot find include file: Mips/Pipeline/Mem/Fwd.v\n`include "Mips/Pipeline/Mem/Fwd.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:9: Cannot find include file: Mips/Forward/Ex/forward.v\n`include "Mips/Forward/Ex/forward.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:14: Define or directive not defined: \'`Mips_Pipeline_FwdEx_T\'\n ( `Mips_Pipeline_FwdEx_T (output) pipeFwdEx\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:14: syntax error, unexpected \'(\', expecting \'[\'\n ( `Mips_Pipeline_FwdEx_T (output) pipeFwdEx\n                           ^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:15: Define or directive not defined: \'`Mips_Pipeline_ExFwd_T\'\n , `Mips_Pipeline_ExFwd_T (input) pipeExFwd\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:16: Define or directive not defined: \'`Mips_Pipeline_RegFwd_T\'\n , `Mips_Pipeline_RegFwd_T (input) pipeRegFwd\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:17: Define or directive not defined: \'`Mips_Pipeline_MemFwd_T\'\n , `Mips_Pipeline_MemFwd_T (input) pipeMemFwd\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:20: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipeEx_RegPort1;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:21: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipeEx_RegPort2;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:22: Define or directive not defined: \'`Mips_Type_RegPorts_T\'\n`Mips_Type_RegPorts_T (wire) pipeEx_RegPorts;\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:30: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipeMem_PcAddr;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:31: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipeMem_AluResult;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:32: Define or directive not defined: \'`Mips_Type_RegPorts_T\'\n`Mips_Type_RegPorts_T (wire) pipeMem_RegPorts;\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:40: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipeReg_WriteData;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:41: Define or directive not defined: \'`Mips_Type_RegPorts_T\'\n`Mips_Type_RegPorts_T (wire) pipeReg_RegPorts;\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:48: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) regPort1;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/fwd.v:49: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) regPort2;\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module Mips_Stage_fwd #
	( parameter DIRECT = 1
	)
	( `Mips_Pipeline_FwdEx_T (output) pipeFwdEx
	, `Mips_Pipeline_ExFwd_T (input) pipeExFwd
	, `Mips_Pipeline_RegFwd_T (input) pipeRegFwd
	, `Mips_Pipeline_MemFwd_T (input) pipeMemFwd
	);

`Mips_Type_Word_T (wire) pipeEx_RegPort1;
`Mips_Type_Word_T (wire) pipeEx_RegPort2;
`Mips_Type_RegPorts_T (wire) pipeEx_RegPorts;
Mips_Pipeline_ExFwd_unpack EXFWD
	( .in (pipeExFwd)
	, .regPort1 (pipeEx_RegPort1)
	, .regPort2 (pipeEx_RegPort2)
	, .regPorts (pipeEx_RegPorts)
	);

`Mips_Type_Word_T (wire) pipeMem_PcAddr;
`Mips_Type_Word_T (wire) pipeMem_AluResult;
`Mips_Type_RegPorts_T (wire) pipeMem_RegPorts;
Mips_Pipeline_MemFwd_unpack MEMFWD
	( .in (pipeMemFwd)
	, .pcAddr    (pipeMem_PcAddr)
	, .aluResult (pipeMem_AluResult)
	, .regPorts  (pipeMem_RegPorts)
	);

`Mips_Type_Word_T (wire) pipeReg_WriteData;
`Mips_Type_RegPorts_T (wire) pipeReg_RegPorts;
Mips_Pipeline_RegFwd_unpack REGFWD
	( .in (pipeRegFwd)
	, .writeData (pipeReg_WriteData)
	, .regPorts  (pipeReg_RegPorts)
	);

`Mips_Type_Word_T (wire) regPort1;
`Mips_Type_Word_T (wire) regPort2;
Mips_Forward_Ex_forward #
	( .DIRECT (DIRECT)
	) EX
	( .regPort1 (regPort1)
	, .regPort2 (regPort2)
	, .pipeEx_RegPort1   (pipeEx_RegPort1)
	, .pipeEx_RegPort2   (pipeEx_RegPort2)
	, .pipeEx_RegPorts   (pipeEx_RegPorts)
	, .pipeMem_RegPorts  (pipeMem_RegPorts)
	, .pipeReg_RegPorts  (pipeReg_RegPorts)
	, .pipeMem_AluResult (pipeMem_AluResult)
	, .pipeMem_PcAddr    (pipeMem_PcAddr)
	, .pipeReg_WriteData (pipeReg_WriteData)
	);

Mips_Pipeline_FwdEx_pack FWDEX
	( .out (pipeFwdEx)
	, .regPort1 (regPort1)
	, .regPort2 (regPort2)
	);

endmodule
module Mips_Stage_fwd #
	( parameter DIRECT = 1
	)
	( `Mips_Pipeline_FwdEx_T (output) pipeFwdEx
	, `Mips_Pipeline_ExFwd_T (input) pipeExFwd
	, `Mips_Pipeline_RegFwd_T (input) pipeRegFwd
	, `Mips_Pipeline_MemFwd_T (input) pipeMemFwd
	);


`Mips_Type_Word_T (wire) pipeEx_RegPort1;
`Mips_Type_Word_T (wire) pipeEx_RegPort2;
`Mips_Type_RegPorts_T (wire) pipeEx_RegPorts;
Mips_Pipeline_ExFwd_unpack EXFWD
	( .in (pipeExFwd)
	, .regPort1 (pipeEx_RegPort1)
	, .regPort2 (pipeEx_RegPort2)
	, .regPorts (pipeEx_RegPorts)
	);

`Mips_Type_Word_T (wire) pipeMem_PcAddr;
`Mips_Type_Word_T (wire) pipeMem_AluResult;
`Mips_Type_RegPorts_T (wire) pipeMem_RegPorts;
Mips_Pipeline_MemFwd_unpack MEMFWD
	( .in (pipeMemFwd)
	, .pcAddr    (pipeMem_PcAddr)
	, .aluResult (pipeMem_AluResult)
	, .regPorts  (pipeMem_RegPorts)
	);

`Mips_Type_Word_T (wire) pipeReg_WriteData;
`Mips_Type_RegPorts_T (wire) pipeReg_RegPorts;
Mips_Pipeline_RegFwd_unpack REGFWD
	( .in (pipeRegFwd)
	, .writeData (pipeReg_WriteData)
	, .regPorts  (pipeReg_RegPorts)
	);

`Mips_Type_Word_T (wire) regPort1;
`Mips_Type_Word_T (wire) regPort2;
Mips_Forward_Ex_forward #
	( .DIRECT (DIRECT)
	) EX
	( .regPort1 (regPort1)
	, .regPort2 (regPort2)
	, .pipeEx_RegPort1   (pipeEx_RegPort1)
	, .pipeEx_RegPort2   (pipeEx_RegPort2)
	, .pipeEx_RegPorts   (pipeEx_RegPorts)
	, .pipeMem_RegPorts  (pipeMem_RegPorts)
	, .pipeReg_RegPorts  (pipeReg_RegPorts)
	, .pipeMem_AluResult (pipeMem_AluResult)
	, .pipeMem_PcAddr    (pipeMem_PcAddr)
	, .pipeReg_WriteData (pipeReg_WriteData)
	);

Mips_Pipeline_FwdEx_pack FWDEX
	( .out (pipeFwdEx)
	, .regPort1 (regPort1)
	, .regPort2 (regPort2)
	);

endmodule