data/full_repos/permissive/18426314/verilog/xilinx/pmi_addsub.v
1: b'%Warning-WIDTH: data/full_repos/permissive/18426314/verilog/xilinx/pmi_addsub.v:19: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'Cin\' generates 1 bits.\n                                                                                  : ... In instance pmi_addsub\nwire [pmi_data_width : 0] tmp_addResult = DataA + DataB + Cin;\n                                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/18426314/verilog/xilinx/pmi_addsub.v:20: Operator SUB expects 33 bits on the RHS, but RHS\'s LOGNOT generates 1 bits.\n                                                                                  : ... In instance pmi_addsub\nwire [pmi_data_width : 0] tmp_subResult = DataA - DataB - !Cin;   \n                                                        ^\n%Error: Exiting due to 2 warning(s)\n'
module pmi_addsub #(
	parameter pmi_data_width    = 32,
	parameter pmi_result_width  = 32,
	parameter pmi_sign   = "off",
	parameter pmi_family = 0,
	parameter module_type= "pmi_addsub"
	)(
	input wire [pmi_data_width - 1 : 0] DataA,
	input wire [pmi_data_width - 1 : 0] DataB,
	input wire Cin,
	input wire Add_Sub,
	output wire [pmi_result_width - 1 : 0]Result,
	output wire Cout,
	output wire Overflow
);

wire [pmi_data_width : 0] tmp_addResult = DataA + DataB + Cin;
wire [pmi_data_width : 0] tmp_subResult = DataA - DataB - !Cin;   

assign Result = (Add_Sub == 1) ? tmp_addResult[pmi_result_width - 1 : 0] : tmp_subResult[pmi_result_width - 1 : 0];
assign Cout = (Add_Sub == 1) ? tmp_addResult[pmi_data_width] : !tmp_subResult[pmi_data_width];
assign Overflow = Cout;

endmodule
module pmi_addsub #(
	parameter pmi_data_width    = 32,
	parameter pmi_result_width  = 32,
	parameter pmi_sign   = "off",
	parameter pmi_family = 0,
	parameter module_type= "pmi_addsub"
	)(
	input wire [pmi_data_width - 1 : 0] DataA,
	input wire [pmi_data_width - 1 : 0] DataB,
	input wire Cin,
	input wire Add_Sub,
	output wire [pmi_result_width - 1 : 0]Result,
	output wire Cout,
	output wire Overflow
);


wire [pmi_data_width : 0] tmp_addResult = DataA + DataB + Cin;
wire [pmi_data_width : 0] tmp_subResult = DataA - DataB - !Cin;   

assign Result = (Add_Sub == 1) ? tmp_addResult[pmi_result_width - 1 : 0] : tmp_subResult[pmi_result_width - 1 : 0];
assign Cout = (Add_Sub == 1) ? tmp_addResult[pmi_data_width] : !tmp_subResult[pmi_data_width];
assign Overflow = Cout;

endmodule