data/full_repos/permissive/116704972/riscv_test.v
None: at end of input
1: b'%Error: data/full_repos/permissive/116704972/riscv_test.v:18: Cannot find include file: test_defines.v\n`include "test_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/116704972,data/full_repos/permissive/116704972/test_defines.v\n             data/full_repos/permissive/116704972,data/full_repos/permissive/116704972/test_defines.v.v\n             data/full_repos/permissive/116704972,data/full_repos/permissive/116704972/test_defines.v.sv\n             test_defines.v\n             test_defines.v.v\n             test_defines.v.sv\n             obj_dir/test_defines.v\n             obj_dir/test_defines.v.v\n             obj_dir/test_defines.v.sv\n%Error: data/full_repos/permissive/116704972/riscv_test.v:19: Cannot find include file: top.v\n`include "top.v" \n         ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/116704972/riscv_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n  always #2 clk = !clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116704972/riscv_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n  always #8 uart_clk = !uart_clk;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/116704972/riscv_test.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #9999 $display("Test timeout!\\n");\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/116704972/riscv_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10000 $finish;\n    ^\n%Error: data/full_repos/permissive/116704972/riscv_test.v:62: Define or directive not defined: \'`TEST_NAME\'\n        $display("%s\\ttest pass\\n", `TEST_NAME);\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/116704972/riscv_test.v:62: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        $display("%s\\ttest pass\\n", `TEST_NAME);\n                                              ^\n%Error: data/full_repos/permissive/116704972/riscv_test.v:65: Define or directive not defined: \'`TEST_NAME\'\n        $display("%s\\ttest failed!\\n", `TEST_NAME);\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/116704972/riscv_test.v:65: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        $display("%s\\ttest failed!\\n", `TEST_NAME);\n                                                 ^\n%Error: Exiting due to 6 error(s), 4 warning(s)\n'
module top_test;

  localparam WIDTH = 8;
  localparam UART_WIDTH = $clog2(WIDTH);
  localparam OUTPUT_CNT = 12;

  reg clk = 1;
  reg uart_clk = 0;
  reg receiving = 0;
  reg display = 0;
  reg [UART_WIDTH-1 : 0] serial_cnt = 0;
  reg [WIDTH-1 : 0] serial_data;
  reg [WIDTH-1 : 0] expected_output = 80;
  wire uart_tx;

  always #2 clk = !clk;
  always #8 uart_clk = !uart_clk;

  top t(
    .clk(clk),
    .uart_tx_line(uart_tx));

  initial begin
    #9999 $display("Test timeout!\n");
    #10000 $finish;
  end

  always @ (posedge uart_clk) begin
    if (receiving) begin

      if (serial_cnt == WIDTH - 1 ) begin
        receiving <= 0;
        display <= 1;
      end

      serial_data[serial_cnt] <= uart_tx;
      serial_cnt <= serial_cnt + 1;

    end else if (display) begin

      if (serial_data == expected_output) begin
        $display("%s\ttest pass\n", `TEST_NAME);
        $finish;
      end else begin
        $display("%s\ttest failed!\n", `TEST_NAME);
        $finish;
      end

      display <= 0;

    end else begin

      if (uart_tx == 0) begin
        receiving <= 1;
      end

    end
  end

endmodule
module top_test;


  localparam WIDTH = 8;
  localparam UART_WIDTH = $clog2(WIDTH);
  localparam OUTPUT_CNT = 12;

  reg clk = 1;
  reg uart_clk = 0;
  reg receiving = 0;
  reg display = 0;
  reg [UART_WIDTH-1 : 0] serial_cnt = 0;
  reg [WIDTH-1 : 0] serial_data;
  reg [WIDTH-1 : 0] expected_output = 80;
  wire uart_tx;

  always #2 clk = !clk;
  always #8 uart_clk = !uart_clk;

  top t(
    .clk(clk),
    .uart_tx_line(uart_tx));

  initial begin
    #9999 $display("Test timeout!\n");
    #10000 $finish;
  end

  always @ (posedge uart_clk) begin
    if (receiving) begin

      if (serial_cnt == WIDTH - 1 ) begin
        receiving <= 0;
        display <= 1;
      end

      serial_data[serial_cnt] <= uart_tx;
      serial_cnt <= serial_cnt + 1;

    end else if (display) begin

      if (serial_data == expected_output) begin
        $display("%s\ttest pass\n", `TEST_NAME);
        $finish;
      end else begin
        $display("%s\ttest failed!\n", `TEST_NAME);
        $finish;
      end

      display <= 0;

    end else begin

      if (uart_tx == 0) begin
        receiving <= 1;
      end

    end
  end

endmodule