data/full_repos/permissive/175808891/verilog/mul16.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/175808891/verilog/mul16.v:83: Signal definition not found, creating implicitly: \'temp2\'\n                                                                          : ... Suggested alternative: \'temp1\'\n    assign temp2 ={4\'b0,q2[7:0]};\n           ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/175808891/verilog/mul16.v:84: Signal definition not found, creating implicitly: \'temp3\'\n                                                                          : ... Suggested alternative: \'temp1\'\n    assign temp3 ={q3[7:0],4\'b0};\n           ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/mul16.v:76: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                       : ... In instance mul16.z4\n    array4 z1(a[3:0],b[3:0],q0[15:0]);\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/mul16.v:77: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                       : ... In instance mul16.z4\n    array4 z2(a[7:4],b[3:0],q1[15:0]);\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/mul16.v:78: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                       : ... In instance mul16.z4\n    array4 z3(a[3:0],b[7:4],q2[15:0]);\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/mul16.v:79: Output port connection \'c\' expects 8 bits on the pin connection, but pin connection\'s SEL generates 16 bits.\n                                                                       : ... In instance mul16.z4\n    array4 z4(a[7:4],b[7:4],q3[15:0]);\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/mul16.v:83: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                       : ... In instance mul16.z4\n    assign temp2 ={4\'b0,q2[7:0]};\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/mul16.v:84: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                       : ... In instance mul16.z4\n    assign temp3 ={q3[7:0],4\'b0};\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/mul16.v:85: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'temp2\' generates 1 bits.\n                                                                       : ... In instance mul16.z4\n    assign q5 = temp2+temp3;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/mul16.v:85: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'temp3\' generates 1 bits.\n                                                                       : ... In instance mul16.z4\n    assign q5 = temp2+temp3;\n                     ^\n%Error: Exiting due to 10 warning(s)\n'
module array4(a,b,c);
    input [3:0]a, b;
    output [7:0]c;
     
    wire [3:0]q0,q1,q2,q3,q4,temp1;
     
    wire [7:0]c;
    wire [5:0]q5,q6,temp2,temp3,temp4;
     
    array2 z1(a[1:0],b[1:0],q0[3:0]);
    array2 z2(a[3:2],b[1:0],q1[3:0]);
    array2 z3(a[1:0],b[3:2],q2[3:0]);
    array2 z4(a[3:2],b[3:2],q3[3:0]);
     
    assign temp1 ={2'b0,q0[3:2]};
    assign q4 = q1[3:0]+temp1;
    assign temp2 ={2'b0,q2[3:0]};
    assign temp3 ={q3[3:0],2'b0};
    assign q5 = temp2+temp3;
    assign temp4={2'b0,q4[3:0]};
    assign q6 = temp4+q5;
     
    assign c[1:0]=q0[1:0];
    assign c[7:2]=q6[5:0];
endmodule
module array4(a,b,c);

    input [3:0]a, b;
    output [7:0]c;
     
    wire [3:0]q0,q1,q2,q3,q4,temp1;
     
    wire [7:0]c;
    wire [5:0]q5,q6,temp2,temp3,temp4;
     
    array2 z1(a[1:0],b[1:0],q0[3:0]);
    array2 z2(a[3:2],b[1:0],q1[3:0]);
    array2 z3(a[1:0],b[3:2],q2[3:0]);
    array2 z4(a[3:2],b[3:2],q3[3:0]);
     
    assign temp1 ={2'b0,q0[3:2]};
    assign q4 = q1[3:0]+temp1;
    assign temp2 ={2'b0,q2[3:0]};
    assign temp3 ={q3[3:0],2'b0};
    assign q5 = temp2+temp3;
    assign temp4={2'b0,q4[3:0]};
    assign q6 = temp4+q5;
     
    assign c[1:0]=q0[1:0];
    assign c[7:2]=q6[5:0];
endmodule