data/full_repos/permissive/144785545/register.v
data/verilator_xmls/2664dfa4-bef9-42ac-b5bc-4bb95f1a4da1.xml
module REGISTER(
		input CLK, 
		input LD,
		input 	  [3:0]	IN,
		output reg [3:0]	OUT
);

always @( posedge CLK ) begin
		if( LD == 1'b0 )
			OUT <= IN;			
end


endmodule
module REGISTER(
		input CLK, 
		input LD,
		input 	  [3:0]	IN,
		output reg [3:0]	OUT
);


always @( posedge CLK ) begin
		if( LD == 1'b0 )
			OUT <= IN;			
end


endmodule