data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v
1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:10: Cannot find include file: sm_cpu.vh\n `include "sm_cpu.vh" \n          ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_cpu.vh\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_cpu.vh.v\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n             sm_cpu.vh\n             sm_cpu.vh.v\n             sm_cpu.vh.sv\n             obj_dir/sm_cpu.vh\n             obj_dir/sm_cpu.vh.v\n             obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:11: Cannot find include file: sm_pcpu.vh\n `include "sm_pcpu.vh" \n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:181: Define or directive not defined: \'`HZ_FW_WE\'\n    wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:181: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n                                                         ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:182: Define or directive not defined: \'`HZ_FW_ME\'\n                            ( hz_forwardA_E == `HZ_FW_ME ) ? aluResult_M : regData1_E );\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:185: Define or directive not defined: \'`HZ_FW_WE\'\n    wire [31:0] writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:185: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire [31:0] writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n                                                           ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:186: Define or directive not defined: \'`HZ_FW_ME\'\n                              ( hz_forwardB_E == `HZ_FW_ME ) ? aluResult_M : regData2_E );\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:325: Define or directive not defined: \'`HZ_FW_NONE\'\n    assign hz_forwardA_E =  ( instrRs_E == 5\'b0                        ) ? `HZ_FW_NONE : (\n                                                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:325: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign hz_forwardA_E =  ( instrRs_E == 5\'b0                        ) ? `HZ_FW_NONE : (\n                                                                                       ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:326: Define or directive not defined: \'`HZ_FW_ME\'\n                            ( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (\n                                                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:327: Define or directive not defined: \'`HZ_FW_WE\'\n                            ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));\n                                                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:327: Define or directive not defined: \'`HZ_FW_NONE\'\n                            ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));\n                                                                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:329: Define or directive not defined: \'`HZ_FW_NONE\'\n    assign hz_forwardB_E =  ( instrRt_E == 5\'b0                        ) ? `HZ_FW_NONE : (\n                                                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:329: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign hz_forwardB_E =  ( instrRt_E == 5\'b0                        ) ? `HZ_FW_NONE : (\n                                                                                       ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:330: Define or directive not defined: \'`HZ_FW_ME\'\n                            ( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (\n                                                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:331: Define or directive not defined: \'`HZ_FW_WE\'\n                            ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));\n                                                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:331: Define or directive not defined: \'`HZ_FW_NONE\'\n                            ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));\n                                                                                         ^~~~~~~~~~~\n%Error: Exiting due to 18 error(s)\n'
module sm_hazard_unit
(
    input   [ 4:0]  instrRs_E,
    input   [ 4:0]  instrRt_E,
    input   [ 4:0]  writeReg_M,
    input   [ 4:0]  writeReg_W,
    input           cw_regWrite_M,
    input           cw_regWrite_W,
    output  [ 1:0]  hz_forwardA_E,
    output  [ 1:0]  hz_forwardB_E,

    input   [ 4:0]  instrRs_D,
    input   [ 4:0]  instrRt_D,
    input   [ 4:0]  writeReg_E,
    input           cw_memToReg_E,
    output          hz_stall_n_F,
    output          hz_stall_n_D,
    output          hz_flush_n_E,

    input           cw_branch_D,
    input           cw_regWrite_E,
    input           cw_memToReg_M,
    output          hz_forwardA_D,
    output          hz_forwardB_D,

    input           cw_pcSrc_D,
    output          hz_flush_n_D
);

    assign hz_forwardA_E =  ( instrRs_E == 5'b0                        ) ? `HZ_FW_NONE : (
                            ( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (
                            ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));

    assign hz_forwardB_E =  ( instrRt_E == 5'b0                        ) ? `HZ_FW_NONE : (
                            ( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (
                            ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));


    wire hz_mem_stall = cw_memToReg_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E );


    assign hz_forwardA_D = ( instrRs_D != 5'b0 && instrRs_D == writeReg_M && cw_regWrite_M );
    assign hz_forwardB_D = ( instrRt_D != 5'b0 && instrRt_D == writeReg_M && cw_regWrite_M );

    wire hz_branch_stall =  cw_branch_D && (
                             ( cw_regWrite_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E ))
                          || ( cw_memToReg_M && ( instrRs_D == writeReg_M || instrRt_D == writeReg_M ))
                            );

    wire hz_stall = hz_mem_stall || hz_branch_stall;


    assign hz_flush_n_D = ~cw_pcSrc_D;


    assign hz_stall_n_F = ~hz_stall;
    assign hz_stall_n_D = ~hz_stall;
    assign hz_flush_n_E = ~hz_stall;

endmodule
module sm_hazard_unit
(
    input   [ 4:0]  instrRs_E,
    input   [ 4:0]  instrRt_E,
    input   [ 4:0]  writeReg_M,
    input   [ 4:0]  writeReg_W,
    input           cw_regWrite_M,
    input           cw_regWrite_W,
    output  [ 1:0]  hz_forwardA_E,
    output  [ 1:0]  hz_forwardB_E,

    input   [ 4:0]  instrRs_D,
    input   [ 4:0]  instrRt_D,
    input   [ 4:0]  writeReg_E,
    input           cw_memToReg_E,
    output          hz_stall_n_F,
    output          hz_stall_n_D,
    output          hz_flush_n_E,

    input           cw_branch_D,
    input           cw_regWrite_E,
    input           cw_memToReg_M,
    output          hz_forwardA_D,
    output          hz_forwardB_D,

    input           cw_pcSrc_D,
    output          hz_flush_n_D
);


    assign hz_forwardA_E =  ( instrRs_E == 5'b0                        ) ? `HZ_FW_NONE : (
                            ( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (
                            ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));

    assign hz_forwardB_E =  ( instrRt_E == 5'b0                        ) ? `HZ_FW_NONE : (
                            ( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (
                            ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));


    wire hz_mem_stall = cw_memToReg_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E );


    assign hz_forwardA_D = ( instrRs_D != 5'b0 && instrRs_D == writeReg_M && cw_regWrite_M );
    assign hz_forwardB_D = ( instrRt_D != 5'b0 && instrRt_D == writeReg_M && cw_regWrite_M );

    wire hz_branch_stall =  cw_branch_D && (
                             ( cw_regWrite_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E ))
                          || ( cw_memToReg_M && ( instrRs_D == writeReg_M || instrRt_D == writeReg_M ))
                            );

    wire hz_stall = hz_mem_stall || hz_branch_stall;


    assign hz_flush_n_D = ~cw_pcSrc_D;


    assign hz_stall_n_F = ~hz_stall;
    assign hz_stall_n_D = ~hz_stall;
    assign hz_flush_n_E = ~hz_stall;

endmodule