data/full_repos/permissive/204164783/procControl.sv
data/verilator_xmls/0ca8d16d-e3bd-429e-aede-332da5e3c7b0.xml
module procControl(
	input clock,
	input reset,
	
	input [23:0] confin_i,
	input confvalid_i,
	output [23:0] confout_o
);

















	
	reg enable;
	reg pinput;
	reg poutput;
    reg incache;
	reg [3:0] weightlen;
    reg [7:0] cachelen;
	reg [7:0] id;
	
	assign confout_o = {
		enable,
		pinput,
		poutput,
        incache,
		weightlen,
        cachelen,
		id
	};
	
	always@(posedge clock or posedge reset) begin
		if(reset) begin
			enable <= 0;
			pinput <= 0;
			poutput <= 0;
            incache <= 0;
			weightlen <= 0;
            cachelen <= 0;
			id <= 0;
		end
		else begin
			if(confvalid_i) begin
				{
					enable,
		            pinput,
		            poutput,
                    incache,
		            weightlen,
                    cachelen,
		            id
				} <= confin_i;
			end
		end
	end

endmodule
module procControl(
	input clock,
	input reset,
	
	input [23:0] confin_i,
	input confvalid_i,
	output [23:0] confout_o
);


















	
	reg enable;
	reg pinput;
	reg poutput;
    reg incache;
	reg [3:0] weightlen;
    reg [7:0] cachelen;
	reg [7:0] id;
	
	assign confout_o = {
		enable,
		pinput,
		poutput,
        incache,
		weightlen,
        cachelen,
		id
	};
	
	always@(posedge clock or posedge reset) begin
		if(reset) begin
			enable <= 0;
			pinput <= 0;
			poutput <= 0;
            incache <= 0;
			weightlen <= 0;
            cachelen <= 0;
			id <= 0;
		end
		else begin
			if(confvalid_i) begin
				{
					enable,
		            pinput,
		            poutput,
                    incache,
		            weightlen,
                    cachelen,
		            id
				} <= confin_i;
			end
		end
	end

endmodule