data/full_repos/permissive/202237519/verilog/digitalsystem4/full_adder_tb.v
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/full_adder_tb.v:1: Cannot find include file: full_adder.v\n`include "full_adder.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/full_adder.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/full_adder.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/full_adder.v.sv\n             full_adder.v\n             full_adder.v.v\n             full_adder.v.sv\n             obj_dir/full_adder.v\n             obj_dir/full_adder.v.v\n             obj_dir/full_adder.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/full_adder_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("full_adder_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/full_adder_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,full_adder_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/full_adder_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 A<=1\'b0; B<= 1\'b0; cin <= 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/full_adder_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #10 A<=1\'b0; B<= 1\'b1; cin <= 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/full_adder_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10 A<=1\'b0; B<= 1\'b1; cin <= 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/full_adder_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10 A<=1\'b1; B<= 1\'b0; cin <= 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/full_adder_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 A<=1\'b1; B<= 1\'b0; cin <= 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/full_adder_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10 A<=1\'b1; B<= 1\'b1; cin <= 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/full_adder_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #10 A<=1\'b1; B<= 1\'b1; cin <= 1\'b1;\n    ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n'
module full_adder_tb;

reg A,B;
reg cin;
wire sum,cout;

full_adder fa0 (A,B,cin,sum,cout);

initial begin
    $dumpfile("full_adder_tb.vcd");
    $dumpvars(0,full_adder_tb);
        A<=1'b0; B<= 1'b0; cin <= 1'b0;
    #10 A<=1'b0; B<= 1'b0; cin <= 1'b1;
    #10 A<=1'b0; B<= 1'b1; cin <= 1'b0;
    #10 A<=1'b0; B<= 1'b1; cin <= 1'b1;
    #10 A<=1'b1; B<= 1'b0; cin <= 1'b0;
    #10 A<=1'b1; B<= 1'b0; cin <= 1'b1;
    #10 A<=1'b1; B<= 1'b1; cin <= 1'b0;
    #10 A<=1'b1; B<= 1'b1; cin <= 1'b1;
    $finish;

end

endmodule
module full_adder_tb;


reg A,B;
reg cin;
wire sum,cout;

full_adder fa0 (A,B,cin,sum,cout);

initial begin
    $dumpfile("full_adder_tb.vcd");
    $dumpvars(0,full_adder_tb);
        A<=1'b0; B<= 1'b0; cin <= 1'b0;
    #10 A<=1'b0; B<= 1'b0; cin <= 1'b1;
    #10 A<=1'b0; B<= 1'b1; cin <= 1'b0;
    #10 A<=1'b0; B<= 1'b1; cin <= 1'b1;
    #10 A<=1'b1; B<= 1'b0; cin <= 1'b0;
    #10 A<=1'b1; B<= 1'b0; cin <= 1'b1;
    #10 A<=1'b1; B<= 1'b1; cin <= 1'b0;
    #10 A<=1'b1; B<= 1'b1; cin <= 1'b1;
    $finish;

end

endmodule