data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:310: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                    : ... Top module \'ARM_CPU\'\nmodule ARM_CPU\n       ^~~~~~~\n                                                                                    : ... Top module \'IC\'\nmodule IC\n       ^~\n                                                                                    : ... Top module \'Data_Memory\'\nmodule Data_Memory\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:563: Operator ASSIGN expects 38 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                                 : ... In instance ARM_CPU.unit4\n      outImmediate[63:26] = {64{outImmediate[25]}};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:566: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s SEL generates 19 bits.\n                                                                                 : ... In instance ARM_CPU.unit4\n      outImmediate[19:0] = inputInstruction[23:5];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:567: Operator ASSIGN expects 44 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                                 : ... In instance ARM_CPU.unit4\n      outImmediate[63:20] = {64{outImmediate[19]}};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:570: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 9 bits.\n                                                                                 : ... In instance ARM_CPU.unit4\n      outImmediate[9:0] = inputInstruction[20:12];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:571: Operator ASSIGN expects 54 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                                 : ... In instance ARM_CPU.unit4\n      outImmediate[63:10] = {64{outImmediate[9]}};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:515: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                 : ... In instance ARM_CPU.unit2\n            reg_out <= 1\'bx;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:287: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'initCount\' generates 32 bits.\n                                                                                 : ... In instance ARM_CPU.unit3\n      Data[initCount] = initCount;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:406: Bit extraction of array[31:0] requires 5 bit index, not 64 bits.\n                                                                                 : ... In instance Data_Memory\n        Data[inputAddress] = inputData;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:408: Bit extraction of array[31:0] requires 5 bit index, not 64 bits.\n                                                                                 : ... In instance Data_Memory\n        outputData = Data[inputAddress];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:336: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hf8\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[0] = 8\'hf8;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:337: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h40\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[1] = 8\'h40;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:338: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h11\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[2] = 8\'h11;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:339: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h22\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[3] = 8\'h22;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:342: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h8b\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[4] = 8\'h8b;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:343: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[5] = 8\'h05;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:344: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[6] = 8\'h01;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:345: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h43\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[7] = 8\'h43;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:348: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hcb\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[8] = 8\'hcb;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:349: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[9] = 8\'h05;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:350: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[10] = 8\'h01;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:351: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[11] = 8\'h44;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:354: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'haa\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[12] = 8\'haa;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:355: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'ha\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[13] = 8\'h0a;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:356: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[14] = 8\'h03;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:357: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hc5\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[15] = 8\'hc5;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:360: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h8a\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[16] = 8\'h8a;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:361: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'ha\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[17] = 8\'h0a;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:362: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[18] = 8\'h03;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:363: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hc6\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[19] = 8\'hc6;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:366: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hf8\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[20] = 8\'hf8;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:367: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[21] = 8\'h00;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:368: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[22] = 8\'h03;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:369: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'he2\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[23] = 8\'he2;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:374: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                 : ... In instance IC\n    instruction_out[8:0] = Data[PC_in + 3];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:375: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                 : ... In instance IC\n    instruction_out[16:8] = Data[PC_in + 2];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:376: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                 : ... In instance IC\n    instruction_out[24:16] = Data[PC_in + 1];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:377: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                 : ... In instance IC\n    instruction_out[31:24] = Data[PC_in];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:377: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                 : ... In instance IC\n    instruction_out[31:24] = Data[PC_in];\n                           ^\n%Error: Exiting due to 39 warning(s)\n'
module Registers
(
  input CLOCK,
  input [4:0] read1,
  input [4:0] read2,
  input [4:0] writeReg,
  input [63:0] writeData,
  input CONTROL_REGWRITE,
  output reg [63:0] data1,
  output reg [63:0] data2
);

  reg [63:0] Data[31:0];

  integer initCount;

  initial begin
    for (initCount = 0; initCount < 31; initCount = initCount + 1) begin
      Data[initCount] = initCount;
    end

    Data[31] = 64'h00000000;
  end

  always @(posedge CLOCK) begin

    data1 = Data[read1];
    data2 = Data[read2];

    if (CONTROL_REGWRITE == 1'b1) begin
      Data[writeReg] = writeData;
    end


    for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
      $display("REGISTER[%0d] = %0d", initCount, Data[initCount]);
    end
  end
endmodule
module Registers
(
  input CLOCK,
  input [4:0] read1,
  input [4:0] read2,
  input [4:0] writeReg,
  input [63:0] writeData,
  input CONTROL_REGWRITE,
  output reg [63:0] data1,
  output reg [63:0] data2
);


  reg [63:0] Data[31:0];

  integer initCount;

  initial begin
    for (initCount = 0; initCount < 31; initCount = initCount + 1) begin
      Data[initCount] = initCount;
    end

    Data[31] = 64'h00000000;
  end

  always @(posedge CLOCK) begin

    data1 = Data[read1];
    data2 = Data[read2];

    if (CONTROL_REGWRITE == 1'b1) begin
      Data[writeReg] = writeData;
    end


    for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
      $display("REGISTER[%0d] = %0d", initCount, Data[initCount]);
    end
  end
endmodule