data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:3: Cannot find include file: tb.v\n`include "tb.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/test/cache,data/full_repos/permissive/201275379/tb.v\n             data/full_repos/permissive/201275379/test/cache,data/full_repos/permissive/201275379/tb.v.v\n             data/full_repos/permissive/201275379/test/cache,data/full_repos/permissive/201275379/tb.v.sv\n             tb.v\n             tb.v.v\n             tb.v.sv\n             obj_dir/tb.v\n             obj_dir/tb.v.v\n             obj_dir/tb.v.sv\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:4: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:5: Cannot find include file: cache.v\n`include "cache.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:12: Define or directive not defined: \'`GEN_TICK\'\n  `GEN_TICK(clk, rst);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:12: syntax error, unexpected \'(\'\n  `GEN_TICK(clk, rst);\n            ^~~\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:21: Define or directive not defined: \'`DATA_BUS\'\n  reg[`DATA_BUS]  data_in;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`DATA_BUS]  data_in;\n               ^\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:27: Define or directive not defined: \'`DATA_BUS\'\n  wire[`DATA_BUS] data_out;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`DATA_BUS] data_out;\n                ^\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:56: Define or directive not defined: \'`TICK\'\n      case (`TICK)\n            ^~~~~\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:56: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      case (`TICK)\n                 ^\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:66: syntax error, unexpected \':\'\n        1: begin\n         ^\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:75: syntax error, unexpected INTEGER NUMBER\n        2: begin\n        ^\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:87: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("valid_out", valid_out);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:88: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("dirty_out", dirty_out);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:89: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("tag_out  ", tag_out);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:90: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("data_out ", data_out);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/cache/CacheLine_tb.v:92: Define or directive not defined: \'`END_AT_TICK\'\n    `END_AT_TICK(3);\n    ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module CacheLine_tb(
  input clk,
  input rst
);

  `GEN_TICK(clk, rst);


  reg             write_en;
  reg             valid_in;
  reg             dirty_in;
  reg[19:0]       tag_in;
  reg[3:0]        offset_in;
  reg[3:0]        data_byte_en;
  reg[`DATA_BUS]  data_in;


  wire            valid_out;
  wire            dirty_out;
  wire[19:0]      tag_out;
  wire[`DATA_BUS] data_out;

  CacheLine cacheline (
    .clk          (clk),
    .rst          (rst),
    .write_en     (write_en),
    .valid_in     (valid_in),
    .dirty_in     (dirty_in),
    .tag_in       (tag_in),
    .offset_in    (offset_in),
    .data_byte_en (data_byte_en),
    .data_in      (data_in),
    .valid_out    (valid_out),
    .dirty_out    (dirty_out),
    .tag_out      (tag_out),
    .data_out     (data_out)
  );

  always @(posedge clk) begin
    if (!rst) begin
      write_en <= 0;
      valid_in <= 0;
      dirty_in <= 0;
      tag_in <= 0;
      offset_in <= 0;
      data_byte_en <= 0;
      data_in <= 0;
    end
    else begin
      case (`TICK)
        0: begin
          write_en <= 1'b1;
          valid_in <= 1'b1;
          dirty_in <= 1'b1;
          tag_in <= 20'h2;
          offset_in <= 4'h3;
          data_byte_en <= 4'b0011;
          data_in <= 32'hFFFF_FFFF;
        end
        1: begin
          write_en <= 1'b1;
          valid_in <= 1'b0;
          dirty_in <= 1'b1;
          tag_in <= 20'h2;
          offset_in <= 4'h3;
          data_byte_en <= 4'b0001;
          data_in <= 32'hFFFF_FFFF;
        end
        2: begin
          write_en <= 1'b0;
          valid_in <= 1'b0;
          dirty_in <= 1'b0;
          tag_in <= 20'h2;
          offset_in <= 4'h3;
          data_byte_en <= 4'b1111;
          data_in <= 32'hFFFF_FFFF;
        end
      endcase
    end

    `DISPLAY("valid_out", valid_out);
    `DISPLAY("dirty_out", dirty_out);
    `DISPLAY("tag_out  ", tag_out);
    `DISPLAY("data_out ", data_out);
    $display("");
    `END_AT_TICK(3);
  end

endmodule
module CacheLine_tb(
  input clk,
  input rst
);


  `GEN_TICK(clk, rst);


  reg             write_en;
  reg             valid_in;
  reg             dirty_in;
  reg[19:0]       tag_in;
  reg[3:0]        offset_in;
  reg[3:0]        data_byte_en;
  reg[`DATA_BUS]  data_in;


  wire            valid_out;
  wire            dirty_out;
  wire[19:0]      tag_out;
  wire[`DATA_BUS] data_out;

  CacheLine cacheline (
    .clk          (clk),
    .rst          (rst),
    .write_en     (write_en),
    .valid_in     (valid_in),
    .dirty_in     (dirty_in),
    .tag_in       (tag_in),
    .offset_in    (offset_in),
    .data_byte_en (data_byte_en),
    .data_in      (data_in),
    .valid_out    (valid_out),
    .dirty_out    (dirty_out),
    .tag_out      (tag_out),
    .data_out     (data_out)
  );

  always @(posedge clk) begin
    if (!rst) begin
      write_en <= 0;
      valid_in <= 0;
      dirty_in <= 0;
      tag_in <= 0;
      offset_in <= 0;
      data_byte_en <= 0;
      data_in <= 0;
    end
    else begin
      case (`TICK)
        0: begin
          write_en <= 1'b1;
          valid_in <= 1'b1;
          dirty_in <= 1'b1;
          tag_in <= 20'h2;
          offset_in <= 4'h3;
          data_byte_en <= 4'b0011;
          data_in <= 32'hFFFF_FFFF;
        end
        1: begin
          write_en <= 1'b1;
          valid_in <= 1'b0;
          dirty_in <= 1'b1;
          tag_in <= 20'h2;
          offset_in <= 4'h3;
          data_byte_en <= 4'b0001;
          data_in <= 32'hFFFF_FFFF;
        end
        2: begin
          write_en <= 1'b0;
          valid_in <= 1'b0;
          dirty_in <= 1'b0;
          tag_in <= 20'h2;
          offset_in <= 4'h3;
          data_byte_en <= 4'b1111;
          data_in <= 32'hFFFF_FFFF;
        end
      endcase
    end

    `DISPLAY("valid_out", valid_out);
    `DISPLAY("dirty_out", dirty_out);
    `DISPLAY("tag_out  ", tag_out);
    `DISPLAY("data_out ", data_out);
    $display("");
    `END_AT_TICK(3);
  end

endmodule