data/full_repos/permissive/136584400/digital_logic_labs/lab03/1-b/sources/t_trigger.v
data/verilator_xmls/4b87ad71-071e-429f-805e-68c145281cb3.xml
module t_trigger(clk, x, q, notq);
  input clk, x;
  output reg q;
  output notq;
initial
begin
  q = 0;
end
  assign notq = ~q;
always @(negedge clk)
begin
  if (x == 1)
  	q <= ~q;
end
endmodule
module t_trigger(clk, x, q, notq);

  input clk, x;
  output reg q;
  output notq;
initial
begin
  q = 0;
end
  assign notq = ~q;
always @(negedge clk)
begin
  if (x == 1)
  	q <= ~q;
end
endmodule