data/full_repos/permissive/149070951/examples/user-test/debouncer.v
1: b"%Error: data/full_repos/permissive/149070951/examples/user-test/debouncer.v:84: Cannot find file containing module: 'prescaler'\nprescaler #(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149070951/examples/user-test,data/full_repos/permissive/149070951/prescaler\n             data/full_repos/permissive/149070951/examples/user-test,data/full_repos/permissive/149070951/prescaler.v\n             data/full_repos/permissive/149070951/examples/user-test,data/full_repos/permissive/149070951/prescaler.sv\n             prescaler\n             prescaler.v\n             prescaler.sv\n             obj_dir/prescaler\n             obj_dir/prescaler.v\n             obj_dir/prescaler.sv\n%Error: Exiting due to 1 error(s)\n"
module debounce_pulse(input wire clk,
                input wire sw_in,
                output wire sw_out);







localparam IDLE  = 0;
localparam WAIT_1  = 1;
localparam PULSE = 2;
localparam WAIT_0 = 3;


reg [1:0] state = IDLE;
reg [1:0] next_state;


reg out = 0;
reg timer_ena = 0;

assign sw_out = out;


always @(posedge clk)
  state <= next_state;


always @(*) begin


  next_state = state;
  timer_ena = 0;
  out = 0;

  case (state)



    IDLE: begin
      timer_ena = 0;
      out = 0;
      if (sw_in)
        next_state = WAIT_1;
    end


    WAIT_1: begin
      timer_ena = 1;
      out = 0;
      if (timer_trig)
        next_state = PULSE;
    end

    PULSE: begin
      timer_ena = 0;
      out = 1;
      next_state = WAIT_0;
    end

    WAIT_0: begin
      timer_ena = 1;
      out = 0;
      if (timer_trig && sw_in==0)
        next_state = IDLE;
    end

    default: begin

    end
  endcase
end

assign sw_out = out;



wire timer_trig;


prescaler #(
  .N(16)
) pres0 (
  .clk_in(clk),
  .ena(timer_ena),
  .clk_out(timer_trig)
);

endmodule
module debounce_pulse(input wire clk,
                input wire sw_in,
                output wire sw_out);








localparam IDLE  = 0;
localparam WAIT_1  = 1;
localparam PULSE = 2;
localparam WAIT_0 = 3;


reg [1:0] state = IDLE;
reg [1:0] next_state;


reg out = 0;
reg timer_ena = 0;

assign sw_out = out;


always @(posedge clk)
  state <= next_state;


always @(*) begin


  next_state = state;
  timer_ena = 0;
  out = 0;

  case (state)



    IDLE: begin
      timer_ena = 0;
      out = 0;
      if (sw_in)
        next_state = WAIT_1;
    end


    WAIT_1: begin
      timer_ena = 1;
      out = 0;
      if (timer_trig)
        next_state = PULSE;
    end

    PULSE: begin
      timer_ena = 0;
      out = 1;
      next_state = WAIT_0;
    end

    WAIT_0: begin
      timer_ena = 1;
      out = 0;
      if (timer_trig && sw_in==0)
        next_state = IDLE;
    end

    default: begin

    end
  endcase
end

assign sw_out = out;



wire timer_trig;


prescaler #(
  .N(16)
) pres0 (
  .clk_in(clk),
  .ena(timer_ena),
  .clk_out(timer_trig)
);

endmodule