data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v
 line:25: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v:25: syntax error, unexpected \'@\'\n  #10 @(posedge clk) Address = Address + 1\'h1;  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #10 @(posedge clk) Address = Address + 1\'h1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk; \n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v:49: Unsupported or unknown PLI call: $monitor\n  $monitor("time:[%0t], Address:[%h], Data_In:[%h]",\n  ^~~~~~~~\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v:56: syntax error, unexpected \'@\'\n  #40 @(posedge clk) Address = 16\'h1476; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #40 @(posedge clk) Address = 16\'h1476; \n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v:57: syntax error, unexpected \'@\'\n  #40 @(posedge clk) Address = 16\'h6435;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #40 @(posedge clk) Address = 16\'h6435;\n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v:58: syntax error, unexpected \'@\'\n  #40 @(posedge clk) Address = 16\'h5095;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/ROM_RAM_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #40 @(posedge clk) Address = 16\'h5095;\n  ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TEST_password_for_USID();
	reg [15:0] Address; 
	reg clk; 
	wire [15:0] Data_ROM_2;  

	ROMPassword ROM(
	._Address(Address),
	.clk(clk), 
	._Data(Data_ROM_2)); 

	always begin 
		#10 clk = ~clk; 
	end

	initial begin 
		$monitor("time:[%0t], Address:[%h], Data_In:[%h]",
			$time,
			ROM._Address, 
			ROM._Data);  

		clk  = 1; 
		Address = 0; 
		#40 @(posedge clk) Address = 16'h1476; 
		#40 @(posedge clk) Address = 16'h6435;
		#40 @(posedge clk) Address = 16'h5095;

	end
endmodule
module TEST_password_for_USID();

	reg [15:0] Address; 
	reg clk; 
	wire [15:0] Data_ROM_2;  

	ROMPassword ROM(
	._Address(Address),
	.clk(clk), 
	._Data(Data_ROM_2)); 

	always begin 
		#10 clk = ~clk; 
	end

	initial begin 
		$monitor("time:[%0t], Address:[%h], Data_In:[%h]",
			$time,
			ROM._Address, 
			ROM._Data);  

		clk  = 1; 
		Address = 0; 
		#40 @(posedge clk) Address = 16'h1476; 
		#40 @(posedge clk) Address = 16'h6435;
		#40 @(posedge clk) Address = 16'h5095;

	end
endmodule