data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v
None: at end of input
1: b'%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:1: Cannot find include file: cypress.v\n`include "cypress.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out,data/full_repos/permissive/193054270/cypress.v\n             data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out,data/full_repos/permissive/193054270/cypress.v.v\n             data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out,data/full_repos/permissive/193054270/cypress.v.sv\n             cypress.v\n             cypress.v.v\n             cypress.v.sv\n             obj_dir/cypress.v\n             obj_dir/cypress.v.v\n             obj_dir/cypress.v.sv\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:50: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:50: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                   ^\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:50: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:50: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:51: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:51: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:51: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:52: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:52: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:52: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:53: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:54: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:54: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:54: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:55: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:55: Define or directive not defined: \'`CS_A0_SRC___F0\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:55: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:56: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:56: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:56: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:57: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:58: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:58: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:58: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:59: Define or directive not defined: \'`CS_SHFT_OP___SL\'\n    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:59: Define or directive not defined: \'`CS_A0_SRC__ALU\'\n    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:59: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:60: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:60: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:60: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:61: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:62: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:62: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:62: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:63: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:63: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:63: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:64: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:64: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:64: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:65: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:66: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:66: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:66: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:67: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:67: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:67: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:68: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/shift_reg_out/shift_reg_out.cydsn/sreg_out/sreg_out.v:68: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module sreg_out (
	output  isr,
    output  data,
	input   clock
);

localparam PG_IDLE    = 3'b000;
localparam PG_COPY_F0 = 3'b001;
localparam PG_SHIFTOUT = 3'b010;

reg [2:0] pg_state;
reg [3:0] so_32;
reg [4:0] out_count;
reg f0_empty;
reg f0_not_empty;

always @(posedge clock)
begin
    case(pg_state)
    PG_IDLE:
    begin
        if(f0_not_empty)
        begin
            pg_state = PG_COPY_F0;
        end
    end
    PG_COPY_F0:
    begin
        out_count = 5'd0;
        pg_state = PG_SHIFTOUT;
    end
    PG_SHIFTOUT:
    begin
        out_count = out_count + 5'd1;
        if(out_count == 5'd0)
        begin
            pg_state = PG_IDLE;
        end
    end
    endcase
end

assign isr = f0_empty;
assign data = so_32[3];

cy_psoc3_dp32 #(
.cy_dpconfig_a({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_DEFSI,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_b({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_c({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_d({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}))dp(
.clk(clock),
.cs_addr(pg_state),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.f0_bus_stat(f0_not_empty),
.f0_blk_stat(f0_empty),
.f1_bus_stat(),
.f1_blk_stat(),
.so(so_32)
);

endmodule
module sreg_out (
	output  isr,
    output  data,
	input   clock
);


localparam PG_IDLE    = 3'b000;
localparam PG_COPY_F0 = 3'b001;
localparam PG_SHIFTOUT = 3'b010;

reg [2:0] pg_state;
reg [3:0] so_32;
reg [4:0] out_count;
reg f0_empty;
reg f0_not_empty;

always @(posedge clock)
begin
    case(pg_state)
    PG_IDLE:
    begin
        if(f0_not_empty)
        begin
            pg_state = PG_COPY_F0;
        end
    end
    PG_COPY_F0:
    begin
        out_count = 5'd0;
        pg_state = PG_SHIFTOUT;
    end
    PG_SHIFTOUT:
    begin
        out_count = out_count + 5'd1;
        if(out_count == 5'd0)
        begin
            pg_state = PG_IDLE;
        end
    end
    endcase
end

assign isr = f0_empty;
assign data = so_32[3];

cy_psoc3_dp32 #(
.cy_dpconfig_a({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_DEFSI,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_b({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_c({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}),
.cy_dpconfig_d({
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
        8'hFF, 8'h00,
        8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
    `SC_SI_A_CHAIN,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_CHNED, `SC_CMP1_CHNED,
    `SC_CMP0_CHNED,
        10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}))dp(
.clk(clock),
.cs_addr(pg_state),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.f0_bus_stat(f0_not_empty),
.f0_blk_stat(f0_empty),
.f1_bus_stat(),
.f1_blk_stat(),
.so(so_32)
);

endmodule