data/full_repos/permissive/170402453/SMPS_ZVS/PWMR.v
data/verilator_xmls/a4f726ad-0cf3-4347-bd08-de743ddcd711.xml
module PWMR(
    input CLK,
	 input reset,
    input [7:0] DUTY_CYCLE,
    output PWM_OUT
    );
	 

	 
	 reg [7:0] cycle;
	 
	 reg pwm;
	 assign PWM_OUT = pwm;
	 initial begin
		cycle = 0;
		pwm = 0;
	 end
	 
	 parameter CYCLE_SIZE = 255;
	 

	 always @(posedge CLK) begin

		cycle <= (cycle >= CYCLE_SIZE) ? 0 : cycle+1;
		


		pwm <= (cycle < DUTY_CYCLE) ? 1 : 0;

		
		if(reset) begin
			cycle=0;
			pwm=0;
		end
	 end
endmodule
module PWMR(
    input CLK,
	 input reset,
    input [7:0] DUTY_CYCLE,
    output PWM_OUT
    );

	 

	 
	 reg [7:0] cycle;
	 
	 reg pwm;
	 assign PWM_OUT = pwm;
	 initial begin
		cycle = 0;
		pwm = 0;
	 end
	 
	 parameter CYCLE_SIZE = 255;
	 

	 always @(posedge CLK) begin

		cycle <= (cycle >= CYCLE_SIZE) ? 0 : cycle+1;
		


		pwm <= (cycle < DUTY_CYCLE) ? 1 : 0;

		
		if(reset) begin
			cycle=0;
			pwm=0;
		end
	 end
endmodule