data/full_repos/permissive/107735152/src/framemaker/framecontroller_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/framecontroller_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset_tb = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/framecontroller_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n   #10 CAN_RX_tb = messageTest[75];\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/107735152/src/framemaker/framecontroller_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #5 sp_tb = !sp_tb;\n  ^\n%Error: data/full_repos/permissive/107735152/src/framemaker/framecontroller_tb.v:13: Cannot find file containing module: \'framecontroller\'\n framecontroller dut(sp_tb, CAN_RX_tb, reset_tb, isStuff_tb, errorFlag_tb,BSonoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, RTR_SRR_tb, IDE_tb, EDL_tb, BRS_tb, RTR_r1_tb, frameReady_tb );\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/framecontroller\n             data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/framecontroller.v\n             data/full_repos/permissive/107735152/src/framemaker,data/full_repos/permissive/107735152/framecontroller.sv\n             framecontroller\n             framecontroller.v\n             framecontroller.sv\n             obj_dir/framecontroller\n             obj_dir/framecontroller.v\n             obj_dir/framecontroller.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module framecontroller_tb
(
	
);



	reg [75:0] messageTest;
	reg	sp_tb, CAN_RX_tb, reset_tb,isStuff_tb,  errorFlag_tb;
	wire BSonoff_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, RTR_SRR_tb, IDE_tb, EDL_tb, BRS_tb, RTR_r1_tb, frameReady_tb;
	wire [1:0] CRCtype_tb;

	framecontroller dut(sp_tb, CAN_RX_tb, reset_tb, isStuff_tb, errorFlag_tb,BSonoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, RTR_SRR_tb, IDE_tb, EDL_tb, BRS_tb, RTR_r1_tb, frameReady_tb );
	



	
	initial
	begin
		$stop;
		CAN_RX_tb = 1'b0;
		sp_tb = 1'b0;
		reset_tb = 1'b1;


		messageTest = 76'b1100100100111010101010101010101010110001101010100101010101010101011111111111;
		isStuff_tb = 1'b0;
		errorFlag_tb = 1'b0;
		#10 reset_tb = 1'b0;
	end
	 
	always @(posedge sp_tb)
	begin
		if(messageTest != 0)
		begin


			#10 CAN_RX_tb = messageTest[75];
			messageTest <= messageTest << 1;

		end
		else
		begin
			$stop;
		end
	
	end
	
	always
		#5 sp_tb = !sp_tb;
		
endmodule
module framecontroller_tb
(
	
);




	reg [75:0] messageTest;
	reg	sp_tb, CAN_RX_tb, reset_tb,isStuff_tb,  errorFlag_tb;
	wire BSonoff_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, RTR_SRR_tb, IDE_tb, EDL_tb, BRS_tb, RTR_r1_tb, frameReady_tb;
	wire [1:0] CRCtype_tb;

	framecontroller dut(sp_tb, CAN_RX_tb, reset_tb, isStuff_tb, errorFlag_tb,BSonoff_tb, CRCtype_tb, BRS_Stop_tb, invalidBit_tb, CRCcalc_on_tb, CRCtime_tb, ackValue_tb, RTR_SRR_tb, IDE_tb, EDL_tb, BRS_tb, RTR_r1_tb, frameReady_tb );
	



	
	initial
	begin
		$stop;
		CAN_RX_tb = 1'b0;
		sp_tb = 1'b0;
		reset_tb = 1'b1;


		messageTest = 76'b1100100100111010101010101010101010110001101010100101010101010101011111111111;
		isStuff_tb = 1'b0;
		errorFlag_tb = 1'b0;
		#10 reset_tb = 1'b0;
	end
	 
	always @(posedge sp_tb)
	begin
		if(messageTest != 0)
		begin


			#10 CAN_RX_tb = messageTest[75];
			messageTest <= messageTest << 1;

		end
		else
		begin
			$stop;
		end
	
	end
	
	always
		#5 sp_tb = !sp_tb;
		
endmodule