data/full_repos/permissive/174783592/FloatAdd/Adder/kpgGenTB.v
 line:39: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/174783592/FloatAdd/Adder/kpgGenTB.v:35: Unsupported: Ignoring delay on this delayed statement.\n #2 a = ~a;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174783592/FloatAdd/Adder/kpgGenTB.v:36: Unsupported: Ignoring delay on this delayed statement.\n   #2 b = ~b;\n   ^\n%Error: data/full_repos/permissive/174783592/FloatAdd/Adder/kpgGenTB.v:38: Unsupported or unknown PLI call: $monitor\n initial $monitor ($time,"a=%b,b=%b,out=%b",a,b,out);\n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174783592/FloatAdd/Adder/kpgGenTB.v:39: Unsupported: Ignoring delay on this delayed statement.\n initial #16 $finish;\n         ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module kgpGenTB();
	reg a , b ;
	wire [1:0]out;
	
	 kpgGen h1(a, b, out);
	
	initial
	begin
		a = 0;
		b = 0;	
	end
	always 
	begin
	#2 a = ~a;
   #2 b = ~b;
	end
	initial $monitor ($time,"a=%b,b=%b,out=%b",a,b,out);
	initial #16 $finish;
endmodule
module kgpGenTB();

	reg a , b ;
	wire [1:0]out;
	
	 kpgGen h1(a, b, out);
	
	initial
	begin
		a = 0;
		b = 0;	
	end
	always 
	begin
	#2 a = ~a;
   #2 b = ~b;
	end
	initial $monitor ($time,"a=%b,b=%b,out=%b",a,b,out);
	initial #16 $finish;
endmodule