data/full_repos/permissive/172201645/src/debug/seven_segment_driver.v
data/verilator_xmls/0a216c04-962a-42c1-986d-4fe279b6a7b5.xml
module seven_segment_driver(
    input  wire clk,
    input  wire [11:0] value,
    output reg  [7:0] segments,
    output reg  [2:0] segment_enable
    );
    
reg [39:0] counter;
reg [2:0] next_enable;
reg [3:0] to_decode;
    
always @(posedge clk) begin


   case (to_decode)
     4'b0000: segments <= 8'b00000011;
     4'b0001: segments <= 8'b10011111;
     4'b0010: segments <= 8'b00100101;
     4'b0011: segments <= 8'b00001101;
     4'b0100: segments <= 8'b10011001;
     4'b0101: segments <= 8'b01001001;
     4'b0110: segments <= 8'b01000001;
     4'b0111: segments <= 8'b00011111;
     4'b1000: segments <= 8'b00000001;
     4'b1001: segments <= 8'b00001001;
     4'b1010: segments <= 8'b00010001;
     4'b1011: segments <= 8'b11000001;
     4'b1100: segments <= 8'b01100011;
     4'b1101: segments <= 8'b10000101;
     4'b1110: segments <= 8'b01100001;
     default: segments <= 8'b01110001;
   endcase;
    
   segment_enable <= next_enable;

   case (counter[19:18]) 
     2'b00:   begin 
                next_enable <= 3'b110;
                to_decode   <= value[3:0];
              end

     2'b01:   begin
                next_enable <= 3'b101;
                to_decode   <= value[7:4];
              end

     2'b10:   begin
                next_enable <= 3'b011;
                to_decode   <= value[11:8];
              end

     default: begin 
                next_enable <= 3'b111;
                to_decode   <= 4'b0000;
              end
   endcase;          

   counter  <= counter + 1;
end

endmodule
module seven_segment_driver(
    input  wire clk,
    input  wire [11:0] value,
    output reg  [7:0] segments,
    output reg  [2:0] segment_enable
    );

    
reg [39:0] counter;
reg [2:0] next_enable;
reg [3:0] to_decode;
    
always @(posedge clk) begin


   case (to_decode)
     4'b0000: segments <= 8'b00000011;
     4'b0001: segments <= 8'b10011111;
     4'b0010: segments <= 8'b00100101;
     4'b0011: segments <= 8'b00001101;
     4'b0100: segments <= 8'b10011001;
     4'b0101: segments <= 8'b01001001;
     4'b0110: segments <= 8'b01000001;
     4'b0111: segments <= 8'b00011111;
     4'b1000: segments <= 8'b00000001;
     4'b1001: segments <= 8'b00001001;
     4'b1010: segments <= 8'b00010001;
     4'b1011: segments <= 8'b11000001;
     4'b1100: segments <= 8'b01100011;
     4'b1101: segments <= 8'b10000101;
     4'b1110: segments <= 8'b01100001;
     default: segments <= 8'b01110001;
   endcase;
    
   segment_enable <= next_enable;

   case (counter[19:18]) 
     2'b00:   begin 
                next_enable <= 3'b110;
                to_decode   <= value[3:0];
              end

     2'b01:   begin
                next_enable <= 3'b101;
                to_decode   <= value[7:4];
              end

     2'b10:   begin
                next_enable <= 3'b011;
                to_decode   <= value[11:8];
              end

     default: begin 
                next_enable <= 3'b111;
                to_decode   <= 4'b0000;
              end
   endcase;          

   counter  <= counter + 1;
end

endmodule