data/full_repos/permissive/136056083/src/DataCache.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136056083/src/DataCache.v:20: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 29 bits.\n                                                                       : ... In instance DataCache\n wire [3:0] setID = blockAddress % 16;  \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136056083/src/DataCache.v:21: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 29 bits.\n                                                                       : ... In instance DataCache\n    assign setID = blockAddress % 16;\n                 ^\n%Error: Exiting due to 2 warning(s)\n'
module DataCache( memWrite,  memRead, memToReg, address,  writeData,  readData, clock);

    input clock;
    input memWrite;
    input memRead;
    input memToReg;
    input [31:0] address;
    input [31:0] writeData;

    output reg[31:0] readData;
 
	reg [28:0]setAddress[0:15];
   	reg [31:0]setData[0:15]; 
	reg [6:0]i;
    wire [28:0]blockAddress = address[31:3];

	wire [3:0] setID = blockAddress % 16;
    assign setID = blockAddress % 16;


    reg [3:0] syncData;
    initial begin syncData = 0; end
 

	always @(posedge clock) begin : search
        syncData = syncData + 1;
        if (syncData == 4) begin
        

            if (memToReg==0) begin
                readData = address;
            end
            
            if(blockAddress == setAddress[setID]) begin

                if(memRead) begin
                    readData = setData[setID];
                end

                else if(memWrite) begin
                    setData[setID] = writeData;
                    readData = setData[setID];
                end

            end

            else begin
                if(memRead) begin
                    setAddress[setID] = blockAddress;


                    setData[setID] = 32'hDEAD_BEEF;
                    readData = 32'hDEAD_BEEF;
                end
                else if (memWrite) begin
                    setAddress[setID] = blockAddress;
                    setData[setID] = writeData;
                    readData = setData[setID];
                end
            
            end
            


            if (memToReg==0) begin
                readData = address;
            end
        end
        else begin
            readData =32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
        end
        if (syncData == 5) begin
            syncData = 0;
        end
       

    end

	initial begin



		setAddress[0] = 29'h000000A0; setData[0] = 32'b00000001000000010000000100000001;
		setAddress[1] = 29'h000000A1; setData[1] = 32'b00000010000000100000001000000010;
        setAddress[2] = 29'h000000A2; setData[2] = 32'b00000011000000110000001100000011;
        setAddress[3] = 29'h000000A3; setData[3] = 32'b00000100000001000000010000000100;
        setAddress[4] = 29'h000000A4; setData[4] = 32'b00000101000001010000010100000101;
        setAddress[5] = 29'h000000A5; setData[5] = 32'b00000110000001100000011000000110;
        setAddress[6] = 29'h000000A6; setData[6] = 32'b00000111000001110000011100000111;
        setAddress[7] = 29'h000000A7; setData[7] = 32'b00001000000010000000100000001000;
        setAddress[8] = 29'h000000A8; setData[8] = 32'b00001001000010010000100100001001;
        setAddress[9] = 29'h000000A9; setData[9] = 32'h00000000;
        setAddress[10] = 29'h000000AA; setData[10] = 32'h00000000;
        setAddress[11] = 29'h000000AB; setData[11] = 32'h00000000;
        setAddress[12] = 29'h000000AC; setData[12] = 32'h00000000;
        setAddress[13] = 29'h000000AD; setData[13] = 32'h00000000;
        setAddress[14] = 29'h000000AE; setData[14] = 32'h00000000;
        setAddress[15] = 29'h000000AF; setData[15] = 32'h00000000;
        
        
        
        
	end

  
  
  
endmodule
module DataCache( memWrite,  memRead, memToReg, address,  writeData,  readData, clock);


    input clock;
    input memWrite;
    input memRead;
    input memToReg;
    input [31:0] address;
    input [31:0] writeData;

    output reg[31:0] readData;
 
	reg [28:0]setAddress[0:15];
   	reg [31:0]setData[0:15]; 
	reg [6:0]i;
    wire [28:0]blockAddress = address[31:3];

	wire [3:0] setID = blockAddress % 16;
    assign setID = blockAddress % 16;


    reg [3:0] syncData;
    initial begin syncData = 0; end
 

	always @(posedge clock) begin : search
        syncData = syncData + 1;
        if (syncData == 4) begin
        

            if (memToReg==0) begin
                readData = address;
            end
            
            if(blockAddress == setAddress[setID]) begin

                if(memRead) begin
                    readData = setData[setID];
                end

                else if(memWrite) begin
                    setData[setID] = writeData;
                    readData = setData[setID];
                end

            end

            else begin
                if(memRead) begin
                    setAddress[setID] = blockAddress;


                    setData[setID] = 32'hDEAD_BEEF;
                    readData = 32'hDEAD_BEEF;
                end
                else if (memWrite) begin
                    setAddress[setID] = blockAddress;
                    setData[setID] = writeData;
                    readData = setData[setID];
                end
            
            end
            


            if (memToReg==0) begin
                readData = address;
            end
        end
        else begin
            readData =32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
        end
        if (syncData == 5) begin
            syncData = 0;
        end
       

    end

	initial begin



		setAddress[0] = 29'h000000A0; setData[0] = 32'b00000001000000010000000100000001;
		setAddress[1] = 29'h000000A1; setData[1] = 32'b00000010000000100000001000000010;
        setAddress[2] = 29'h000000A2; setData[2] = 32'b00000011000000110000001100000011;
        setAddress[3] = 29'h000000A3; setData[3] = 32'b00000100000001000000010000000100;
        setAddress[4] = 29'h000000A4; setData[4] = 32'b00000101000001010000010100000101;
        setAddress[5] = 29'h000000A5; setData[5] = 32'b00000110000001100000011000000110;
        setAddress[6] = 29'h000000A6; setData[6] = 32'b00000111000001110000011100000111;
        setAddress[7] = 29'h000000A7; setData[7] = 32'b00001000000010000000100000001000;
        setAddress[8] = 29'h000000A8; setData[8] = 32'b00001001000010010000100100001001;
        setAddress[9] = 29'h000000A9; setData[9] = 32'h00000000;
        setAddress[10] = 29'h000000AA; setData[10] = 32'h00000000;
        setAddress[11] = 29'h000000AB; setData[11] = 32'h00000000;
        setAddress[12] = 29'h000000AC; setData[12] = 32'h00000000;
        setAddress[13] = 29'h000000AD; setData[13] = 32'h00000000;
        setAddress[14] = 29'h000000AE; setData[14] = 32'h00000000;
        setAddress[15] = 29'h000000AF; setData[15] = 32'h00000000;
        
        
        
        
	end

  
  
  
endmodule