data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axi_to_strobed.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axi_to_strobed.v:44: Cannot find file containing module: 'axi_fifo'\n  axi_fifo #(.WIDTH(WIDTH+1), .SIZE(FIFO_SIZE)) axi_fifo (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi,data/full_repos/permissive/214858095/axi_fifo\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi,data/full_repos/permissive/214858095/axi_fifo.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi,data/full_repos/permissive/214858095/axi_fifo.sv\n             axi_fifo\n             axi_fifo.v\n             axi_fifo.sv\n             obj_dir/axi_fifo\n             obj_dir/axi_fifo.v\n             obj_dir/axi_fifo.sv\n%Error: Exiting due to 1 error(s)\n"
module axi_to_strobed #(
  parameter WIDTH = 32,
  parameter FIFO_SIZE = 1,
  parameter MIN_RATE = 256
)(
  input clk, input reset, input clear,
  input [$clog2(MIN_RATE):0] out_rate,
  input ready,
  output error,
  input [WIDTH-1:0] i_tdata, input i_tvalid, input i_tlast, output i_tready,
  output out_stb, output out_last, output [WIDTH-1:0] out_data
);

  reg strobe;
  wire valid;
  reg [$clog2(MIN_RATE):0] counter = 1;
  always @(posedge clk) begin
    if (reset | clear) begin
      strobe    <= 1'b0;
      counter   <= 1;
    end else if (ready) begin
      if (counter >= out_rate) begin
        strobe  <= 1'b1;
        counter <= 1;
      end else begin
        strobe  <= 1'b0;
        counter <= counter + 1'b1;
      end
    end else begin
      strobe <= 1'b0;
    end
  end

  axi_fifo #(.WIDTH(WIDTH+1), .SIZE(FIFO_SIZE)) axi_fifo (
    .clk(clk), .reset(reset), .clear(clear),
    .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
    .o_tdata({out_last,out_data}), .o_tvalid(valid), .o_tready(strobe),
    .space(), .occupied());

  assign out_stb = valid & strobe;
  assign error = ~valid & strobe;
endmodule
module axi_to_strobed #(
  parameter WIDTH = 32,
  parameter FIFO_SIZE = 1,
  parameter MIN_RATE = 256
)(
  input clk, input reset, input clear,
  input [$clog2(MIN_RATE):0] out_rate,
  input ready,
  output error,
  input [WIDTH-1:0] i_tdata, input i_tvalid, input i_tlast, output i_tready,
  output out_stb, output out_last, output [WIDTH-1:0] out_data
);


  reg strobe;
  wire valid;
  reg [$clog2(MIN_RATE):0] counter = 1;
  always @(posedge clk) begin
    if (reset | clear) begin
      strobe    <= 1'b0;
      counter   <= 1;
    end else if (ready) begin
      if (counter >= out_rate) begin
        strobe  <= 1'b1;
        counter <= 1;
      end else begin
        strobe  <= 1'b0;
        counter <= counter + 1'b1;
      end
    end else begin
      strobe <= 1'b0;
    end
  end

  axi_fifo #(.WIDTH(WIDTH+1), .SIZE(FIFO_SIZE)) axi_fifo (
    .clk(clk), .reset(reset), .clear(clear),
    .i_tdata({i_tlast,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
    .o_tdata({out_last,out_data}), .o_tvalid(valid), .o_tready(strobe),
    .space(), .occupied());

  assign out_stb = valid & strobe;
  assign error = ~valid & strobe;
endmodule