data/full_repos/permissive/205055389/test/verga/sum3.v
 line:26: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/sum3.v:26: Unsupported: Ignoring delay on this delayed statement.\n     #1 $display("sum: %3b = %2b + %2b + %2b       (%d=%d+%d+%d)",{c[2],s},a,b,c[0],{c[2],s},a,b,c[0]);\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205055389/test/verga/sum3.v:21: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'8\'h1\' generates 8 bits.\n                                                                         : ... In instance top\n     a[0] = (i & 8\'h1) != 0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/205055389/test/verga/sum3.v:22: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                         : ... In instance top\n     a[1] = (i & 8\'h2) != 0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/205055389/test/verga/sum3.v:23: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'8\'h4\' generates 8 bits.\n                                                                         : ... In instance top\n     b[0] = (i & 8\'h4) != 0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/205055389/test/verga/sum3.v:24: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'8\'h8\' generates 8 bits.\n                                                                         : ... In instance top\n     b[1] = (i & 8\'h8) != 0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/205055389/test/verga/sum3.v:25: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'8\'h10\' generates 8 bits.\n                                                                         : ... In instance top\n     c[0] = (i & 8\'h10) != 0;\n               ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  parameter n = 2;

  reg [n-1:0] a, b;
  reg ci;
  reg [n-1:0] s;
  reg [n:0] c;
  integer i,j;

  always @(*) 
	begin
	  c[n:1] <= a & b | a & c[n-1:0] | b & c[n-1:0];
	  s <= a ^ b ^ c[n-1:0];
	end

  initial
    begin
	$display("Starting SUM test");
        for (i = 0;i < 32;i = i + 1)
	  begin
	    a[0] = (i & 8'h1) != 0;
	    a[1] = (i & 8'h2) != 0;
	    b[0] = (i & 8'h4) != 0;
	    b[1] = (i & 8'h8) != 0;
	    c[0] = (i & 8'h10) != 0;
	    #1 $display("sum: %3b = %2b + %2b + %2b       (%d=%d+%d+%d)",{c[2],s},a,b,c[0],{c[2],s},a,b,c[0]);
	  end
    end
endmodule
module top;

  parameter n = 2;

  reg [n-1:0] a, b;
  reg ci;
  reg [n-1:0] s;
  reg [n:0] c;
  integer i,j;

  always @(*) 
	begin
	  c[n:1] <= a & b | a & c[n-1:0] | b & c[n-1:0];
	  s <= a ^ b ^ c[n-1:0];
	end

  initial
    begin
	$display("Starting SUM test");
        for (i = 0;i < 32;i = i + 1)
	  begin
	    a[0] = (i & 8'h1) != 0;
	    a[1] = (i & 8'h2) != 0;
	    b[0] = (i & 8'h4) != 0;
	    b[1] = (i & 8'h8) != 0;
	    c[0] = (i & 8'h10) != 0;
	    #1 $display("sum: %3b = %2b + %2b + %2b       (%d=%d+%d+%d)",{c[2],s},a,b,c[0],{c[2],s},a,b,c[0]);
	  end
    end
endmodule