data/full_repos/permissive/143278/ivltests/shift_pad.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/shift_pad.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (out !== 2\'b10) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/shift_pad.v:27: Operator SHIFTL expects 2 bits on the LHS, but LHS\'s VARREF \'in\' generates 1 bits.\n                                                                         : ... In instance main\n      out = in << 1;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/shift_pad.v:33: Operator SHIFTL expects 2 bits on the LHS, but LHS\'s VARREF \'in\' generates 1 bits.\n                                                                         : ... In instance main\n      out <= in << 1;\n                ^~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [1:0] out;
   reg	     in;

   initial begin
      in = 1;
      out = in << 1;
      if (out !== 2'b10) begin
	 $display("FAILED (1) -- out == %b", out);
	 $finish;
      end

      out <= in << 1;

      #1 if (out !== 2'b10) begin
	 $display("FAILED (2) -- out == %b", out);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;


   reg [1:0] out;
   reg	     in;

   initial begin
      in = 1;
      out = in << 1;
      if (out !== 2'b10) begin
	 $display("FAILED (1) -- out == %b", out);
	 $finish;
      end

      out <= in << 1;

      #1 if (out !== 2'b10) begin
	 $display("FAILED (2) -- out == %b", out);
	 $finish;
      end

      $display("PASSED");
   end
endmodule