data/full_repos/permissive/19340845/test/MUXTest.v
 line:18: before: "$"
1: b'%Error: data/full_repos/permissive/19340845/test/MUXTest.v:10: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("muxTest.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19340845/test/MUXTest.v:11: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, MUXTEST);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19340845/test/MUXTest.v:12: Unsupported or unknown PLI call: $monitor\n      $monitor ("%t: a = %b, b = %b, Sw = %b, out = %b", $time, a, b, Sw, out);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MUXTest.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 4\'b1100; b =4\'b0101;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MUXTest.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #10 Sw = 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/MUXTest.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #10 $finish;\n      ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MUXTEST;
   reg [3:0] a,b;
   reg 	      Sw;
   wire [3:0] out;
   
   Multiplexer #(4) mux (a, b, Sw, out);


   initial begin
      $dumpfile("muxTest.vcd");
      $dumpvars(0, MUXTEST);
      $monitor ("%t: a = %b, b = %b, Sw = %b, out = %b", $time, a, b, Sw, out);
      

      Sw = 1'b0; a = 4'b0011; b = 4'b1010;
      #10 a = 4'b1100; b =4'b0101;
      #10 Sw = 1'b1;
      #10 $finish;
   end
endmodule
module MUXTEST;

   reg [3:0] a,b;
   reg 	      Sw;
   wire [3:0] out;
   
   Multiplexer #(4) mux (a, b, Sw, out);


   initial begin
      $dumpfile("muxTest.vcd");
      $dumpvars(0, MUXTEST);
      $monitor ("%t: a = %b, b = %b, Sw = %b, out = %b", $time, a, b, Sw, out);
      

      Sw = 1'b0; a = 4'b0011; b = 4'b1010;
      #10 a = 4'b1100; b =4'b0101;
      #10 Sw = 1'b1;
      #10 $finish;
   end
endmodule