data/full_repos/permissive/208741034/key_control_beep/rtl/uart_tx.v
 line:9: before: ";"
1: b"%Error: data/full_repos/permissive/208741034/key_control_beep/rtl/uart_tx.v:9: syntax error, unexpected ';', expecting ')' or ','\n    output reg     uart_tx_data;\n                               ^\n%Error: data/full_repos/permissive/208741034/key_control_beep/rtl/uart_tx.v:19: syntax error, unexpected reg, expecting IDENTIFIER or '=' or do or final\nreg uart_tx_d0;\n^~~\n%Error: data/full_repos/permissive/208741034/key_control_beep/rtl/uart_tx.v:21: syntax error, unexpected assign\nassign uart_tx_flag = uart_tx_d0 & (~uart_tx_d1);\n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module uart_tx(
    input  clk,
    input  rst_n,

    input          uart_tx_flag,
    input  [7 : 0] uart_data,
    output reg     uart_tx_data;
);

parameter  CLK_CNT  = 50_000_000 ;
parameter  UART_BSP = 115200;
localparam BSP_CNT = CLK_CNT / UART_BSP;

reg [15 : 0] clk_cnt;
reg [3  : 0] tx_cnt ;
reg          
reg uart_tx_d0;
reg uart_tx_d1;
assign uart_tx_flag = uart_tx_d0 & (~uart_tx_d1);


always @(posedge clk or negedge rst_n) begin
   if(!rst_n)begin
   uart_tx_d0 <= 1'd0;
   uart_tx_d1 <= 1'd0;
   end
   else begin
       uart_tx_d0 <= uart_tx_flag;
       uart_tx_d1 <= uart_tx_d0;
   end
end


always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin

    end
    
end

endmodule
module uart_tx(
    input  clk,
    input  rst_n,

    input          uart_tx_flag,
    input  [7 : 0] uart_data,
    output reg     uart_tx_data;

);

parameter  CLK_CNT  = 50_000_000 ;
parameter  UART_BSP = 115200;
localparam BSP_CNT = CLK_CNT / UART_BSP;

reg [15 : 0] clk_cnt;
reg [3  : 0] tx_cnt ;
reg          
reg uart_tx_d0;
reg uart_tx_d1;
assign uart_tx_flag = uart_tx_d0 & (~uart_tx_d1);


always @(posedge clk or negedge rst_n) begin
   if(!rst_n)begin
   uart_tx_d0 <= 1'd0;
   uart_tx_d1 <= 1'd0;
   end
   else begin
       uart_tx_d0 <= uart_tx_flag;
       uart_tx_d1 <= uart_tx_d0;
   end
end


always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin

    end
    
end

endmodule