data/full_repos/permissive/115852809/tb/mcs4eval_tb.v
 line:31: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/115852809/tb/mcs4eval_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #(96) clk <= !clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115852809/tb/mcs4eval_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("mcs4eval_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/115852809/tb/mcs4eval_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, mcs4eval_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115852809/tb/mcs4eval_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #8000000\n  ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mcs4eval_tb();
	reg clk = 1'b0;
	wire phi1;
	wire phi2;
	wire sync;
	wire cm_rom;

	wire [3:0] data_bus;

	always
		#(96) clk <= !clk;

	i4001 #(.ROM_FILENAME("build/roms/mcs4eval.mem")) rom(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom));
	
	i4002 ram_0(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom),.P0_i(1'b0));
	i4002 ram_1(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom),.P0_i(1'b1));
	
	i4004 cpu(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_o(sync),.D_io(data_bus),.CM_ROM_o(cm_rom),.TEST_i(1'b1));

	mcs4_clk_gen generator(.clk_i(clk),.PHI1_o(phi1),.PHI2_o(phi2));

	initial
	begin
		$dumpfile("mcs4eval_tb.vcd");
		$dumpvars(0, mcs4eval_tb);
		#8000000
		$finish;
	end
endmodule
module mcs4eval_tb();

	reg clk = 1'b0;
	wire phi1;
	wire phi2;
	wire sync;
	wire cm_rom;

	wire [3:0] data_bus;

	always
		#(96) clk <= !clk;

	i4001 #(.ROM_FILENAME("build/roms/mcs4eval.mem")) rom(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom));
	
	i4002 ram_0(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom),.P0_i(1'b0));
	i4002 ram_1(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_i(sync),.D_io(data_bus),.CM_i(cm_rom),.P0_i(1'b1));
	
	i4004 cpu(.clk_i(clk),.PHI1_i(phi1),.PHI2_i(phi2),.SYNC_o(sync),.D_io(data_bus),.CM_ROM_o(cm_rom),.TEST_i(1'b1));

	mcs4_clk_gen generator(.clk_i(clk),.PHI1_o(phi1),.PHI2_o(phi2));

	initial
	begin
		$dumpfile("mcs4eval_tb.vcd");
		$dumpvars(0, mcs4eval_tb);
		#8000000
		$finish;
	end
endmodule