data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v
 line:174: before: "/"
1: b'%Warning-MULTITOP: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:168: Multiple top level modules\n                                                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                   : ... Top module \'seg7decimal\'\nmodule seg7decimal(\n       ^~~~~~~~~~~\n                                                                                                                   : ... Top module \'Disp_minus\'\nmodule Disp_minus (input clk,\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:36: Operator DIV expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'clkdiv\' generates 20 bits.\n                                                                                                               : ... In instance seg7decimal\n    wire [3:0] ss = clkdiv / 10000000;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:36: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 24 bits.\n                                                                                                               : ... In instance seg7decimal\n    wire [3:0] ss = clkdiv / 10000000;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:46: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h31968146\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                0: num =    32\'h31968146;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:47: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h56000000\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                1: num =    32\'h56000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:48: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h66600000\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                2: num =    32\'h66600000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:49: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h6660000\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                3: num =    32\'h06660000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:50: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h666000\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                4: num =    32\'h00666000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:51: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h66600\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                5: num =    32\'h00066600;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:52: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h6660\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                6: num =    32\'h00006660;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:53: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h666\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                7: num =    32\'h00000666;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:54: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h67\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                8: num =    32\'h00000067;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:55: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1a\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                9: num =    32\'h0000001A;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:56: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h111\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                10: num =   32\'h00000111;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:57: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1110\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                11: num =   32\'h00001110;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:58: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h11100\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                12: num =   32\'h00011100;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:59: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h111000\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                13: num =   32\'h00111000;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:60: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1110000\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                14: num =   32\'h01110000;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:61: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h11100000\' generates 32 bits.\n                                                                                                               : ... In instance seg7decimal\n                15: num =   32\'h11100000;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:65: Operator MODDIV expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[3:0] = eightnum[7:0] % 4\'d10;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:65: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 8 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[3:0] = eightnum[7:0] % 4\'d10;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:66: Operator DIV expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[7:4] = eightnum[7:0] / 4\'d10;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:66: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 8 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[7:4] = eightnum[7:0] / 4\'d10;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:64: Operator GTE expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                               : ... In instance seg7decimal\n            if (eightnum[7:0] >= 4\'d10) begin  \n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:72: Operator MODDIV expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[11:8] = eightnum[15:8] % 4\'d10;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:72: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 8 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[11:8] = eightnum[15:8] % 4\'d10;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:73: Operator DIV expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[15:12] = eightnum[15:8] / 4\'d10;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:73: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 8 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[15:12] = eightnum[15:8] / 4\'d10;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:71: Operator GTE expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                               : ... In instance seg7decimal\n            if (eightnum[15:8] >= 4\'d10) begin  \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:79: Operator MODDIV expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[19:16] = eightnum[23:16] % 4\'d10;\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:79: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 8 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[19:16] = eightnum[23:16] % 4\'d10;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:80: Operator DIV expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[23:20] = eightnum[23:16] / 4\'d10;\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:80: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 8 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[23:20] = eightnum[23:16] / 4\'d10;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:78: Operator GTE expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                               : ... In instance seg7decimal\n            if (eightnum[23:16] >= 4\'d10 && eightnum[23:16] != 8\'hEE) begin  \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:86: Operator MODDIV expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[27:24] = eightnum[31:24] % 4\'d10;\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:86: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 8 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[27:24] = eightnum[31:24] % 4\'d10;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:87: Operator DIV expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[31:28] = eightnum[31:24] / 4\'d10;\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Seg_7_Display.v:87: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 8 bits.\n                                                                                                               : ... In instance seg7decimal\n                num[31:28] = eightnum[31:24] / 4\'d10;\n                           ^\n%Error: Exiting due to 38 warning(s)\n'
module seg7decimal(
    input [31:0] eightnum,
    input [3:0] stat,
    input clk,
    output reg [6:0] seg,
    output reg [7:0] an,
    output wire dp);
    
    wire [2:0] s;
    reg [3:0] digit;
    wire [7:0] aen;
    reg [19:0] clkdiv = 0;
    reg [32:0] num;
    
    assign dp  = 1;
    wire [3:0] ss = clkdiv / 10000000;
    assign s   = clkdiv[19:17];
    assign aen = 8'b11111111;
    

    integer i;
    always @(posedge clk) begin
        if (stat == 4'h3)

            case (0)
                0: num =    32'h31968146;
                1: num =    32'h56000000;
                2: num =    32'h66600000;
                3: num =    32'h06660000;
                4: num =    32'h00666000;
                5: num =    32'h00066600;
                6: num =    32'h00006660;
                7: num =    32'h00000666;
                8: num =    32'h00000067;
                9: num =    32'h0000001A;
                10: num =   32'h00000111;
                11: num =   32'h00001110;
                12: num =   32'h00011100;
                13: num =   32'h00111000;
                14: num =   32'h01110000;
                15: num =   32'h11100000;
            endcase
        else begin
            if (eightnum[7:0] >= 4'd10) begin
                num[3:0] = eightnum[7:0] % 4'd10;
                num[7:4] = eightnum[7:0] / 4'd10;
                end
            else
                num[7:0] = eightnum[7:0];
                
            if (eightnum[15:8] >= 4'd10) begin
                num[11:8] = eightnum[15:8] % 4'd10;
                num[15:12] = eightnum[15:8] / 4'd10;
                end
            else
                num[15:8] = eightnum[15:8];

            if (eightnum[23:16] >= 4'd10 && eightnum[23:16] != 8'hEE) begin
                num[19:16] = eightnum[23:16] % 4'd10;
                num[23:20] = eightnum[23:16] / 4'd10;
                end
            else
                num[23:16] = eightnum[23:16];

            if (eightnum[31:24] >= 8'd10 && eightnum[31:24] != 8'hEE) begin
                num[27:24] = eightnum[31:24] % 4'd10;
                num[31:28] = eightnum[31:24] / 4'd10;
                end
            else
                num[31:24] = eightnum[31:24];
        end
        case(s)
            0:digit = num[3:0];
            1:digit = num[7:4];
            2:digit = num[11:8];
            3:digit = num[15:12];
            4:digit = num[19:16];
            5:digit = num[23:20];
            6:digit = num[27:24];
            7:digit = num[31:28];
            default:digit = num[3:0];
        endcase
    end
    

    always @(*)
        if (stat == 4'h3)
            case(digit)



                0:seg   = 7'b1111111;
                1:seg   = 7'b1111110;
                2:seg   = 7'b1011110;
                3:seg   = 7'b1001110;
                4:seg   = 7'b1000111;
                5:seg   = 7'b1100111;
                6:seg   = 7'b1110111;
                7:seg   = 7'b1110011;
                8:seg   = 7'b1110001;
                9:seg   = 7'b1111000;
                'hA:seg = 7'b1111100;
                'hB:seg = 7'b0100011;
                'hC:seg = 7'b0101111;
                'hD:seg = 7'b0101111;
                'hE:seg = 7'b0000110;
                'hF:seg = 7'b0001110;
                default: seg = 7'b0000000;
            endcase
        else
            case(digit)



                0:seg   = 7'b1000000;
                1:seg   = 7'b1111001;
                2:seg   = 7'b0100100;
                3:seg   = 7'b0110000;
                4:seg   = 7'b0011001;
                5:seg   = 7'b0010010;
                6:seg   = 7'b0000010;
                7:seg   = 7'b1111000;
                8:seg   = 7'b0000000;
                9:seg   = 7'b0010000;
                'hA:seg = 7'b0001000;
                'hB:seg = 7'b0000011;
                'hC:seg = 7'b1000110;
                'hD:seg = 7'b0100001;
                'hE:seg = 7'b0111111;
                'hF:seg = 7'b0001110;
                default: seg = 7'b0000000;
            endcase
    
    always @(*) begin
        an = 8'b11111111;
        if (aen[s] == 1)
            an[s] = 0;
    end
        

        
	always @(posedge clk) begin
		clkdiv = clkdiv+1;
	end
           
endmodule
module seg7decimal(
    input [31:0] eightnum,
    input [3:0] stat,
    input clk,
    output reg [6:0] seg,
    output reg [7:0] an,
    output wire dp);

    
    wire [2:0] s;
    reg [3:0] digit;
    wire [7:0] aen;
    reg [19:0] clkdiv = 0;
    reg [32:0] num;
    
    assign dp  = 1;
    wire [3:0] ss = clkdiv / 10000000;
    assign s   = clkdiv[19:17];
    assign aen = 8'b11111111;
    

    integer i;
    always @(posedge clk) begin
        if (stat == 4'h3)

            case (0)
                0: num =    32'h31968146;
                1: num =    32'h56000000;
                2: num =    32'h66600000;
                3: num =    32'h06660000;
                4: num =    32'h00666000;
                5: num =    32'h00066600;
                6: num =    32'h00006660;
                7: num =    32'h00000666;
                8: num =    32'h00000067;
                9: num =    32'h0000001A;
                10: num =   32'h00000111;
                11: num =   32'h00001110;
                12: num =   32'h00011100;
                13: num =   32'h00111000;
                14: num =   32'h01110000;
                15: num =   32'h11100000;
            endcase
        else begin
            if (eightnum[7:0] >= 4'd10) begin
                num[3:0] = eightnum[7:0] % 4'd10;
                num[7:4] = eightnum[7:0] / 4'd10;
                end
            else
                num[7:0] = eightnum[7:0];
                
            if (eightnum[15:8] >= 4'd10) begin
                num[11:8] = eightnum[15:8] % 4'd10;
                num[15:12] = eightnum[15:8] / 4'd10;
                end
            else
                num[15:8] = eightnum[15:8];

            if (eightnum[23:16] >= 4'd10 && eightnum[23:16] != 8'hEE) begin
                num[19:16] = eightnum[23:16] % 4'd10;
                num[23:20] = eightnum[23:16] / 4'd10;
                end
            else
                num[23:16] = eightnum[23:16];

            if (eightnum[31:24] >= 8'd10 && eightnum[31:24] != 8'hEE) begin
                num[27:24] = eightnum[31:24] % 4'd10;
                num[31:28] = eightnum[31:24] / 4'd10;
                end
            else
                num[31:24] = eightnum[31:24];
        end
        case(s)
            0:digit = num[3:0];
            1:digit = num[7:4];
            2:digit = num[11:8];
            3:digit = num[15:12];
            4:digit = num[19:16];
            5:digit = num[23:20];
            6:digit = num[27:24];
            7:digit = num[31:28];
            default:digit = num[3:0];
        endcase
    end
    

    always @(*)
        if (stat == 4'h3)
            case(digit)



                0:seg   = 7'b1111111;
                1:seg   = 7'b1111110;
                2:seg   = 7'b1011110;
                3:seg   = 7'b1001110;
                4:seg   = 7'b1000111;
                5:seg   = 7'b1100111;
                6:seg   = 7'b1110111;
                7:seg   = 7'b1110011;
                8:seg   = 7'b1110001;
                9:seg   = 7'b1111000;
                'hA:seg = 7'b1111100;
                'hB:seg = 7'b0100011;
                'hC:seg = 7'b0101111;
                'hD:seg = 7'b0101111;
                'hE:seg = 7'b0000110;
                'hF:seg = 7'b0001110;
                default: seg = 7'b0000000;
            endcase
        else
            case(digit)



                0:seg   = 7'b1000000;
                1:seg   = 7'b1111001;
                2:seg   = 7'b0100100;
                3:seg   = 7'b0110000;
                4:seg   = 7'b0011001;
                5:seg   = 7'b0010010;
                6:seg   = 7'b0000010;
                7:seg   = 7'b1111000;
                8:seg   = 7'b0000000;
                9:seg   = 7'b0010000;
                'hA:seg = 7'b0001000;
                'hB:seg = 7'b0000011;
                'hC:seg = 7'b1000110;
                'hD:seg = 7'b0100001;
                'hE:seg = 7'b0111111;
                'hF:seg = 7'b0001110;
                default: seg = 7'b0000000;
            endcase
    
    always @(*) begin
        an = 8'b11111111;
        if (aen[s] == 1)
            an[s] = 0;
    end
        

        
	always @(posedge clk) begin
		clkdiv = clkdiv+1;
	end
           
endmodule