data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:117: Cannot find file containing module: \'small_fifo\'\n      small_fifo\n      ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path,data/full_repos/permissive/121277233/small_fifo\n             data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path,data/full_repos/permissive/121277233/small_fifo.v\n             data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path,data/full_repos/permissive/121277233/small_fifo.sv\n             small_fifo\n             small_fifo.v\n             small_fifo.sv\n             obj_dir/small_fifo\n             obj_dir/small_fifo.v\n             obj_dir/small_fifo.sv\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:204: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n                                                                                                                                                                     : ... In instance queue_aggr\n         else if(empty[4]==0)   cur_queue_next=4;\n                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-SELRANGE: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:204: Selection index out of range: 4:4 outside 3:0\n                                                                                                                                                                        : ... In instance queue_aggr\n         else if(empty[4]==0)   cur_queue_next=4;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:212: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n                                                                                                                                                                     : ... In instance queue_aggr\n            else if(empty[4]==0)   cur_queue_next=4;\n                                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:212: Selection index out of range: 4:4 outside 3:0\n                                                                                                                                                                        : ... In instance queue_aggr\n            else if(empty[4]==0)   cur_queue_next=4;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:220: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n                                                                                                                                                                     : ... In instance queue_aggr\n                else if(empty[4]==0)   cur_queue_next=4;\n                                                     ^\n%Warning-SELRANGE: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:220: Selection index out of range: 4:4 outside 3:0\n                                                                                                                                                                        : ... In instance queue_aggr\n                else if(empty[4]==0)   cur_queue_next=4;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:228: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n                                                                                                                                                                     : ... In instance queue_aggr\n             if     (empty[4]==0)   cur_queue_next=4;\n                                                  ^\n%Warning-SELRANGE: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:228: Selection index out of range: 4:4 outside 3:0\n                                                                                                                                                                        : ... In instance queue_aggr\n             if     (empty[4]==0)   cur_queue_next=4;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:241: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n                                                                                                                                                                     : ... In instance queue_aggr\n            else if(empty[4]==0)   cur_queue_next=4;\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:242: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n                                                                                                                                                                     : ... In instance queue_aggr\n            else                   cur_queue_next=4;\n                                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:241: Selection index out of range: 4:4 outside 3:0\n                                                                                                                                                                        : ... In instance queue_aggr\n            else if(empty[4]==0)   cur_queue_next=4;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:198: Operator CASE expects 32 or 3 bits on the Case expression, but Case expression\'s VARREF \'cur_queue\' generates 2 bits.\n                                                                                                                                                                     : ... In instance queue_aggr\n   else case(cur_queue)\n        ^~~~\n%Warning-SELRANGE: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:286: Selection index out of range: 4 outside 3:0\n                                                                                                                                                                        : ... In instance queue_aggr\n   assign in_data[4]         = in_data_4;\n                 ^\n%Warning-SELRANGE: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:287: Selection index out of range: 4 outside 3:0\n                                                                                                                                                                        : ... In instance queue_aggr\n   assign in_ctrl[4]         = in_ctrl_4;\n                 ^\n%Warning-SELRANGE: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:288: Selection index out of range: 4:4 outside 3:0\n                                                                                                                                                                        : ... In instance queue_aggr\n   assign in_wr[4]           = in_wr_4;\n               ^\n%Warning-SELRANGE: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v:289: Selection index out of range: 4:4 outside 3:0\n                                                                                                                                                                        : ... In instance queue_aggr\n   assign in_rdy_4           = !nearly_full[4];\n                                           ^\n%Error: Exiting due to 1 error(s), 16 warning(s)\n'
module queue_aggr
    #(parameter DATA_WIDTH = 64,
      parameter CTRL_WIDTH=DATA_WIDTH/8,
      parameter UDP_REG_SRC_WIDTH = 2,
      parameter STAGE_NUMBER = 2,
      parameter NUM_QUEUES = 4,
      parameter MAX_NUM_QUEUES = 8
      )

   (
    output reg [DATA_WIDTH-1:0]        out_data,
    output reg [CTRL_WIDTH-1:0]        out_ctrl,
    output reg                         out_wr,
    input                              out_rdy,


    input  [DATA_WIDTH-1:0]            in_data_0,
    input  [CTRL_WIDTH-1:0]            in_ctrl_0,
    input                              in_wr_0,
    output                             in_rdy_0,

    input  [DATA_WIDTH-1:0]            in_data_1,
    input  [CTRL_WIDTH-1:0]            in_ctrl_1,
    input                              in_wr_1,
    output                             in_rdy_1,

    input  [DATA_WIDTH-1:0]            in_data_2,
    input  [CTRL_WIDTH-1:0]            in_ctrl_2,
    input                              in_wr_2,
    output                             in_rdy_2,

    input  [DATA_WIDTH-1:0]            in_data_3,
    input  [CTRL_WIDTH-1:0]            in_ctrl_3,
    input                              in_wr_3,
    output                             in_rdy_3,

    input  [DATA_WIDTH-1:0]            in_data_4,
    input  [CTRL_WIDTH-1:0]            in_ctrl_4,
    input                              in_wr_4,
    output                             in_rdy_4,




    input                              reset,
    input                              clk
   );


   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction


   localparam NUM_QUEUES_WIDTH = log2(NUM_QUEUES);



   wire [NUM_QUEUES-1:0]           nearly_full;
   wire [NUM_QUEUES-1:0]           empty;
   wire [DATA_WIDTH-1:0]               in_data      [NUM_QUEUES-1:0];
   wire [CTRL_WIDTH-1:0]               in_ctrl      [NUM_QUEUES-1:0];
   wire [NUM_QUEUES-1:0]           in_wr;
   wire [CTRL_WIDTH-1:0]               fifo_out_ctrl[NUM_QUEUES-1:0];
   wire [DATA_WIDTH-1:0]               fifo_out_data[NUM_QUEUES-1:0];
   reg [NUM_QUEUES-1:0]            rd_en;
   reg [NUM_QUEUES-1:0]            rd_fifo;

   wire [NUM_QUEUES_WIDTH-1:0]         cur_queue_plus1;
   reg [NUM_QUEUES_WIDTH-1:0]          cur_queue;
   reg [NUM_QUEUES_WIDTH-1:0]          cur_queue_next;
   reg [CTRL_WIDTH-1:0]                fifo_out_ctrl_prev;
   reg [CTRL_WIDTH-1:0]                fifo_out_ctrl_prev_next;

   wire [CTRL_WIDTH-1:0]               fifo_out_ctrl_sel;
   wire [DATA_WIDTH-1:0]               fifo_out_data_sel;

   reg [DATA_WIDTH-1:0]                out_data_next;
   reg [CTRL_WIDTH-1:0]                out_ctrl_next;
   reg                                 out_wr_next;

   reg                                 eop;



   generate
   genvar i;
   for(i=0; i<NUM_QUEUES; i=i+1) begin: in_arb_queues
      small_fifo
        #( .WIDTH(DATA_WIDTH+CTRL_WIDTH),
           .MAX_DEPTH_BITS(5))
      in_arb_fifo
        (
         .dout                           ({fifo_out_ctrl[i], fifo_out_data[i]}),
         .full                           (),
         .nearly_full                    (nearly_full[i]),
         .prog_full                      (),
         .empty                          (empty[i]),

         .din                            ({in_ctrl[i], in_data[i]}),
         .wr_en                          (in_wr[i]),
         .rd_en                          (rd_fifo[i]),
         .reset                          (reset),
         .clk                            (clk));
   end
   endgenerate
    

    
    reg [3:0]cur_st,nxt_st;
    localparam IDLE=0;
    localparam READ=1;
    localparam READ_HEAD=2;
    localparam WAIT_EOP=3;
    localparam ADD_QUEUE=4;
    
    always@(posedge clk)
        if(reset)   cur_st<=0;
        else        cur_st<=nxt_st;
        
    always@(*)
        begin
            nxt_st=0;
            case(cur_st)
                IDLE:
                    if(!empty[cur_queue]) nxt_st=READ;
                    else nxt_st=ADD_QUEUE;
                READ:
                    if(out_rdy) nxt_st=READ_HEAD;
                    else nxt_st=READ;
                READ_HEAD:
                    if(fifo_out_ctrl[cur_queue]==0) nxt_st=WAIT_EOP;
                    else nxt_st=READ_HEAD;
                WAIT_EOP:
                    if(fifo_out_ctrl[cur_queue]!=0) nxt_st=ADD_QUEUE;
                    else nxt_st=WAIT_EOP;
                ADD_QUEUE:nxt_st=IDLE;
                default:nxt_st=IDLE;
            endcase
        end
           
    always@(*)
        begin
            rd_en=0;
            if(cur_st==READ | cur_st==READ_HEAD) rd_en[cur_queue]=!empty[cur_queue];
            else if(cur_st==WAIT_EOP && fifo_out_ctrl[cur_queue]!=0) rd_en[cur_queue]=0;
            else if(cur_st==WAIT_EOP ) rd_en[cur_queue]=!empty[cur_queue];
        end
    
    always@(*)
        if(reset)   rd_fifo=0;
        else begin
            rd_fifo=0;
            rd_fifo[cur_queue]=rd_en[cur_queue] & out_rdy;
        end
        
    always@(posedge clk)
        if(reset)   out_wr<=0;
        else out_wr<= |rd_fifo;

    always@(posedge clk)
        if(reset)   cur_queue<=0;
        else if(cur_st==ADD_QUEUE)
         cur_queue<=cur_queue_next;


   always@(*)
   if(reset) 
      cur_queue_next=0;
   else case(cur_queue)
   0:
      begin
         if     (empty[1]==0)   cur_queue_next=1;
         else if(empty[2]==0)   cur_queue_next=2;
         else if(empty[3]==0)   cur_queue_next=3;
         else if(empty[4]==0)   cur_queue_next=4;
         else if(empty[0]==0)   cur_queue_next=0;
         else                   cur_queue_next=0;
      end
   1:
         begin
            if     (empty[2]==0)   cur_queue_next=2;
            else if(empty[3]==0)   cur_queue_next=3;
            else if(empty[4]==0)   cur_queue_next=4;
            else if(empty[0]==0)   cur_queue_next=0;
            else if(empty[1]==0)   cur_queue_next=1;
            else                   cur_queue_next=1;
         end
    2:
          begin
                if     (empty[3]==0)   cur_queue_next=3;
                else if(empty[4]==0)   cur_queue_next=4;
                else if(empty[0]==0)   cur_queue_next=0;
                else if(empty[1]==0)   cur_queue_next=1;
                else if(empty[2]==0)   cur_queue_next=2;
                else                   cur_queue_next=2;
             end
    3:
          begin
             if     (empty[4]==0)   cur_queue_next=4;
             else if(empty[0]==0)   cur_queue_next=0;
             else if(empty[1]==0)   cur_queue_next=1;
             else if(empty[2]==0)   cur_queue_next=2;
             else if(empty[3]==0)   cur_queue_next=3;
             else                   cur_queue_next=3;
         end
   4:
         begin
            if     (empty[0]==0)   cur_queue_next=0;
            else if(empty[1]==0)   cur_queue_next=1;
            else if(empty[2]==0)   cur_queue_next=2;
            else if(empty[3]==0)   cur_queue_next=3;
            else if(empty[4]==0)   cur_queue_next=4;
            else                   cur_queue_next=4;
         end
     default:cur_queue_next=0;
   endcase

    always@(*)
        if(reset)   
            begin 
                out_data=0;
                out_ctrl=0;
            end
        else if(cur_st==READ_HEAD | cur_st==WAIT_EOP)   
            begin 
                out_data=fifo_out_data[cur_queue];
                out_ctrl=fifo_out_ctrl[cur_queue];
            end
        else
            begin
                out_data=0;
                out_ctrl=0;
            end



   assign in_data[0]         = in_data_0;
   assign in_ctrl[0]         = in_ctrl_0;
   assign in_wr[0]           = in_wr_0;
   assign in_rdy_0           = !nearly_full[0];

   assign in_data[1]         = in_data_1;
   assign in_ctrl[1]         = in_ctrl_1;
   assign in_wr[1]           = in_wr_1;
   assign in_rdy_1           = !nearly_full[1];

   assign in_data[2]         = in_data_2;
   assign in_ctrl[2]         = in_ctrl_2;
   assign in_wr[2]           = in_wr_2;
   assign in_rdy_2           = !nearly_full[2];

   assign in_data[3]         = in_data_3;
   assign in_ctrl[3]         = in_ctrl_3;
   assign in_wr[3]           = in_wr_3;
   assign in_rdy_3           = !nearly_full[3];

   assign in_data[4]         = in_data_4;
   assign in_ctrl[4]         = in_ctrl_4;
   assign in_wr[4]           = in_wr_4;
   assign in_rdy_4           = !nearly_full[4];


   


endmodule
module queue_aggr
    #(parameter DATA_WIDTH = 64,
      parameter CTRL_WIDTH=DATA_WIDTH/8,
      parameter UDP_REG_SRC_WIDTH = 2,
      parameter STAGE_NUMBER = 2,
      parameter NUM_QUEUES = 4,
      parameter MAX_NUM_QUEUES = 8
      )

   (
    output reg [DATA_WIDTH-1:0]        out_data,
    output reg [CTRL_WIDTH-1:0]        out_ctrl,
    output reg                         out_wr,
    input                              out_rdy,


    input  [DATA_WIDTH-1:0]            in_data_0,
    input  [CTRL_WIDTH-1:0]            in_ctrl_0,
    input                              in_wr_0,
    output                             in_rdy_0,

    input  [DATA_WIDTH-1:0]            in_data_1,
    input  [CTRL_WIDTH-1:0]            in_ctrl_1,
    input                              in_wr_1,
    output                             in_rdy_1,

    input  [DATA_WIDTH-1:0]            in_data_2,
    input  [CTRL_WIDTH-1:0]            in_ctrl_2,
    input                              in_wr_2,
    output                             in_rdy_2,

    input  [DATA_WIDTH-1:0]            in_data_3,
    input  [CTRL_WIDTH-1:0]            in_ctrl_3,
    input                              in_wr_3,
    output                             in_rdy_3,

    input  [DATA_WIDTH-1:0]            in_data_4,
    input  [CTRL_WIDTH-1:0]            in_ctrl_4,
    input                              in_wr_4,
    output                             in_rdy_4,




    input                              reset,
    input                              clk
   );



   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction


   localparam NUM_QUEUES_WIDTH = log2(NUM_QUEUES);



   wire [NUM_QUEUES-1:0]           nearly_full;
   wire [NUM_QUEUES-1:0]           empty;
   wire [DATA_WIDTH-1:0]               in_data      [NUM_QUEUES-1:0];
   wire [CTRL_WIDTH-1:0]               in_ctrl      [NUM_QUEUES-1:0];
   wire [NUM_QUEUES-1:0]           in_wr;
   wire [CTRL_WIDTH-1:0]               fifo_out_ctrl[NUM_QUEUES-1:0];
   wire [DATA_WIDTH-1:0]               fifo_out_data[NUM_QUEUES-1:0];
   reg [NUM_QUEUES-1:0]            rd_en;
   reg [NUM_QUEUES-1:0]            rd_fifo;

   wire [NUM_QUEUES_WIDTH-1:0]         cur_queue_plus1;
   reg [NUM_QUEUES_WIDTH-1:0]          cur_queue;
   reg [NUM_QUEUES_WIDTH-1:0]          cur_queue_next;
   reg [CTRL_WIDTH-1:0]                fifo_out_ctrl_prev;
   reg [CTRL_WIDTH-1:0]                fifo_out_ctrl_prev_next;

   wire [CTRL_WIDTH-1:0]               fifo_out_ctrl_sel;
   wire [DATA_WIDTH-1:0]               fifo_out_data_sel;

   reg [DATA_WIDTH-1:0]                out_data_next;
   reg [CTRL_WIDTH-1:0]                out_ctrl_next;
   reg                                 out_wr_next;

   reg                                 eop;



   generate
   genvar i;
   for(i=0; i<NUM_QUEUES; i=i+1) begin: in_arb_queues
      small_fifo
        #( .WIDTH(DATA_WIDTH+CTRL_WIDTH),
           .MAX_DEPTH_BITS(5))
      in_arb_fifo
        (
         .dout                           ({fifo_out_ctrl[i], fifo_out_data[i]}),
         .full                           (),
         .nearly_full                    (nearly_full[i]),
         .prog_full                      (),
         .empty                          (empty[i]),

         .din                            ({in_ctrl[i], in_data[i]}),
         .wr_en                          (in_wr[i]),
         .rd_en                          (rd_fifo[i]),
         .reset                          (reset),
         .clk                            (clk));
   end
   endgenerate
    

    
    reg [3:0]cur_st,nxt_st;
    localparam IDLE=0;
    localparam READ=1;
    localparam READ_HEAD=2;
    localparam WAIT_EOP=3;
    localparam ADD_QUEUE=4;
    
    always@(posedge clk)
        if(reset)   cur_st<=0;
        else        cur_st<=nxt_st;
        
    always@(*)
        begin
            nxt_st=0;
            case(cur_st)
                IDLE:
                    if(!empty[cur_queue]) nxt_st=READ;
                    else nxt_st=ADD_QUEUE;
                READ:
                    if(out_rdy) nxt_st=READ_HEAD;
                    else nxt_st=READ;
                READ_HEAD:
                    if(fifo_out_ctrl[cur_queue]==0) nxt_st=WAIT_EOP;
                    else nxt_st=READ_HEAD;
                WAIT_EOP:
                    if(fifo_out_ctrl[cur_queue]!=0) nxt_st=ADD_QUEUE;
                    else nxt_st=WAIT_EOP;
                ADD_QUEUE:nxt_st=IDLE;
                default:nxt_st=IDLE;
            endcase
        end
           
    always@(*)
        begin
            rd_en=0;
            if(cur_st==READ | cur_st==READ_HEAD) rd_en[cur_queue]=!empty[cur_queue];
            else if(cur_st==WAIT_EOP && fifo_out_ctrl[cur_queue]!=0) rd_en[cur_queue]=0;
            else if(cur_st==WAIT_EOP ) rd_en[cur_queue]=!empty[cur_queue];
        end
    
    always@(*)
        if(reset)   rd_fifo=0;
        else begin
            rd_fifo=0;
            rd_fifo[cur_queue]=rd_en[cur_queue] & out_rdy;
        end
        
    always@(posedge clk)
        if(reset)   out_wr<=0;
        else out_wr<= |rd_fifo;

    always@(posedge clk)
        if(reset)   cur_queue<=0;
        else if(cur_st==ADD_QUEUE)
         cur_queue<=cur_queue_next;


   always@(*)
   if(reset) 
      cur_queue_next=0;
   else case(cur_queue)
   0:
      begin
         if     (empty[1]==0)   cur_queue_next=1;
         else if(empty[2]==0)   cur_queue_next=2;
         else if(empty[3]==0)   cur_queue_next=3;
         else if(empty[4]==0)   cur_queue_next=4;
         else if(empty[0]==0)   cur_queue_next=0;
         else                   cur_queue_next=0;
      end
   1:
         begin
            if     (empty[2]==0)   cur_queue_next=2;
            else if(empty[3]==0)   cur_queue_next=3;
            else if(empty[4]==0)   cur_queue_next=4;
            else if(empty[0]==0)   cur_queue_next=0;
            else if(empty[1]==0)   cur_queue_next=1;
            else                   cur_queue_next=1;
         end
    2:
          begin
                if     (empty[3]==0)   cur_queue_next=3;
                else if(empty[4]==0)   cur_queue_next=4;
                else if(empty[0]==0)   cur_queue_next=0;
                else if(empty[1]==0)   cur_queue_next=1;
                else if(empty[2]==0)   cur_queue_next=2;
                else                   cur_queue_next=2;
             end
    3:
          begin
             if     (empty[4]==0)   cur_queue_next=4;
             else if(empty[0]==0)   cur_queue_next=0;
             else if(empty[1]==0)   cur_queue_next=1;
             else if(empty[2]==0)   cur_queue_next=2;
             else if(empty[3]==0)   cur_queue_next=3;
             else                   cur_queue_next=3;
         end
   4:
         begin
            if     (empty[0]==0)   cur_queue_next=0;
            else if(empty[1]==0)   cur_queue_next=1;
            else if(empty[2]==0)   cur_queue_next=2;
            else if(empty[3]==0)   cur_queue_next=3;
            else if(empty[4]==0)   cur_queue_next=4;
            else                   cur_queue_next=4;
         end
     default:cur_queue_next=0;
   endcase

    always@(*)
        if(reset)   
            begin 
                out_data=0;
                out_ctrl=0;
            end
        else if(cur_st==READ_HEAD | cur_st==WAIT_EOP)   
            begin 
                out_data=fifo_out_data[cur_queue];
                out_ctrl=fifo_out_ctrl[cur_queue];
            end
        else
            begin
                out_data=0;
                out_ctrl=0;
            end



   assign in_data[0]         = in_data_0;
   assign in_ctrl[0]         = in_ctrl_0;
   assign in_wr[0]           = in_wr_0;
   assign in_rdy_0           = !nearly_full[0];

   assign in_data[1]         = in_data_1;
   assign in_ctrl[1]         = in_ctrl_1;
   assign in_wr[1]           = in_wr_1;
   assign in_rdy_1           = !nearly_full[1];

   assign in_data[2]         = in_data_2;
   assign in_ctrl[2]         = in_ctrl_2;
   assign in_wr[2]           = in_wr_2;
   assign in_rdy_2           = !nearly_full[2];

   assign in_data[3]         = in_data_3;
   assign in_ctrl[3]         = in_ctrl_3;
   assign in_wr[3]           = in_wr_3;
   assign in_rdy_3           = !nearly_full[3];

   assign in_data[4]         = in_data_4;
   assign in_ctrl[4]         = in_ctrl_4;
   assign in_wr[4]           = in_wr_4;
   assign in_rdy_4           = !nearly_full[4];


   


endmodule