data/full_repos/permissive/124979458/FIFO_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/124979458/FIFO_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/124979458/FIFO_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #100 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/124979458/FIFO_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #10 wr_clk = ~wr_clk;\n        ^\n%Error: data/full_repos/permissive/124979458/FIFO_tb.v:37: Cannot find file containing module: \'fifo_generator_0\'\nfifo_generator_0 KeyHash_FIFO(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/124979458,data/full_repos/permissive/124979458/fifo_generator_0\n             data/full_repos/permissive/124979458,data/full_repos/permissive/124979458/fifo_generator_0.v\n             data/full_repos/permissive/124979458,data/full_repos/permissive/124979458/fifo_generator_0.sv\n             fifo_generator_0\n             fifo_generator_0.v\n             fifo_generator_0.sv\n             obj_dir/fifo_generator_0\n             obj_dir/fifo_generator_0.v\n             obj_dir/fifo_generator_0.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FIFO_tb;


reg rst;
reg rd_clk;
reg wr_clk;
reg rd_en;
reg wr_en;
reg [127:0] din;

wire [127:0] dout;
wire full;
wire empty;

fifo_generator_0 KeyHash_FIFO(
	.rst(rst),
	
	.wr_clk(wr_clk),
	
	.rd_clk(rd_clk),
	
	.din(din),
	
	.wr_en(wr_en),
	
	.rd_en(rd_en),
	.dout(dout),
	.full(full),
	.empty(empty)
    );


initial begin
    rst = 0;
    wr_clk = 0;
    rd_clk = 0;
    #5 rst = 1;
    #100 rst = 0;
    forever begin
        #10 wr_clk = ~wr_clk;
            rd_clk = ~rd_clk;
    end   
end






reg [127:0]	mem [0:9];
reg [1:0]state_w;
reg [3:0]i;

initial $readmemh("D:\\memKey.txt", mem);

always @(posedge wr_clk, posedge rst)begin
	if(rst)begin
		wr_en <= 1'b0;
		din <= 128'd0;
		i <= 0;
		state_w <= 0;
	end
	else if(!full)begin
		case(state_w)
		2'd0:begin
			wr_en <= 1;
			din <= mem[i];
			i <= i+1;
			state_w <= state_w+1;
		end
		2'd1:begin
			if(i == 4'd10)begin
				wr_en <= 1'b0;
				state_w = state_w+1;
			end
			else begin
				din <= mem[i];
				i <= i+1;
			end
		end
		default:begin		
			
		end
		endcase
	end

end


reg [127:0]			mem_o [0:9];
reg [2:0]			state_r;
reg [3:0]			o;
always @(posedge rd_clk , posedge rst)begin
	if(rst)begin
		rd_en <= 0;
		o <= 0;
		state_r <= 0;
	end
	else if(!empty)begin
		case(state_r)
		3'd0:begin
			rd_en <= 0;
			state_r <= state_r+1;


		end
		3'd1:if(wr_en == 0)begin
			rd_en <= 1'b1;
			state_r = state_r+1;
		end
		3'd2:begin
			if(o == 4'd10)begin
				rd_en <= 1'b0;
				state_r = state_r+1;
			end
			else begin
				mem_o[o] <= dout;
				o <= o+1;
			end
		end
		default:begin
			rd_en <= 1'b0;
			state_r = 0;
		end
		endcase
	end
end


endmodule
module FIFO_tb;



reg rst;
reg rd_clk;
reg wr_clk;
reg rd_en;
reg wr_en;
reg [127:0] din;

wire [127:0] dout;
wire full;
wire empty;

fifo_generator_0 KeyHash_FIFO(
	.rst(rst),
	
	.wr_clk(wr_clk),
	
	.rd_clk(rd_clk),
	
	.din(din),
	
	.wr_en(wr_en),
	
	.rd_en(rd_en),
	.dout(dout),
	.full(full),
	.empty(empty)
    );


initial begin
    rst = 0;
    wr_clk = 0;
    rd_clk = 0;
    #5 rst = 1;
    #100 rst = 0;
    forever begin
        #10 wr_clk = ~wr_clk;
            rd_clk = ~rd_clk;
    end   
end






reg [127:0]	mem [0:9];
reg [1:0]state_w;
reg [3:0]i;

initial $readmemh("D:\\memKey.txt", mem);

always @(posedge wr_clk, posedge rst)begin
	if(rst)begin
		wr_en <= 1'b0;
		din <= 128'd0;
		i <= 0;
		state_w <= 0;
	end
	else if(!full)begin
		case(state_w)
		2'd0:begin
			wr_en <= 1;
			din <= mem[i];
			i <= i+1;
			state_w <= state_w+1;
		end
		2'd1:begin
			if(i == 4'd10)begin
				wr_en <= 1'b0;
				state_w = state_w+1;
			end
			else begin
				din <= mem[i];
				i <= i+1;
			end
		end
		default:begin		
			
		end
		endcase
	end

end


reg [127:0]			mem_o [0:9];
reg [2:0]			state_r;
reg [3:0]			o;
always @(posedge rd_clk , posedge rst)begin
	if(rst)begin
		rd_en <= 0;
		o <= 0;
		state_r <= 0;
	end
	else if(!empty)begin
		case(state_r)
		3'd0:begin
			rd_en <= 0;
			state_r <= state_r+1;


		end
		3'd1:if(wr_en == 0)begin
			rd_en <= 1'b1;
			state_r = state_r+1;
		end
		3'd2:begin
			if(o == 4'd10)begin
				rd_en <= 1'b0;
				state_r = state_r+1;
			end
			else begin
				mem_o[o] <= dout;
				o <= o+1;
			end
		end
		default:begin
			rd_en <= 1'b0;
			state_r = 0;
		end
		endcase
	end
end


endmodule