data/full_repos/permissive/182333580/software/DE10_Standard_FB.v
 line:430: before: "."
1: b'%Warning-WIDTH: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:237: Operator ASSIGNW expects 28 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 23 bits.\n                                                                                    : ... In instance DE10_Standard_FB\nassign stm_hw_events = {{4{1\'b0}}, SW, fpga_led_internal[8:0]};\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:266: Cannot find file containing module: \'soc_system\'\nsoc_system u0 (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/182333580/software,data/full_repos/permissive/182333580/soc_system\n             data/full_repos/permissive/182333580/software,data/full_repos/permissive/182333580/soc_system.v\n             data/full_repos/permissive/182333580/software,data/full_repos/permissive/182333580/soc_system.sv\n             soc_system\n             soc_system.v\n             soc_system.sv\n             obj_dir/soc_system\n             obj_dir/soc_system.v\n             obj_dir/soc_system.sv\n%Error: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:380: Cannot find file containing module: \'DE10_Standard_DCC_TOP\'\nDE10_Standard_DCC_TOP DCC_TOP_ins(\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:419: Cannot find file containing module: \'hps_reset\'\nhps_reset hps_reset_inst (\n^~~~~~~~~\n%Error: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:424: Cannot find file containing module: \'altera_edge_detector\'\naltera_edge_detector pulse_cold_reset (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:434: Cannot find file containing module: \'altera_edge_detector\'\naltera_edge_detector pulse_warm_reset (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:444: Cannot find file containing module: \'altera_edge_detector\'\naltera_edge_detector pulse_debug_reset (\n^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:526: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'ADA_D\' generates 14 bits.\n                                                                                    : ... In instance DE10_Standard_FB\n  a_post_window[post_window_count] = ADA_D;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:527: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'ADB_D\' generates 14 bits.\n                                                                                    : ... In instance DE10_Standard_FB\n  b_post_window[post_window_count] = ADB_D;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:544: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'ADA_D\' generates 14 bits.\n                                                                                    : ... In instance DE10_Standard_FB\n  a_pre_window[3] = ADA_D;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:551: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'ADB_D\' generates 14 bits.\n                                                                                    : ... In instance DE10_Standard_FB\n  b_pre_window[3] = ADB_D;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:575: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'counter\' generates 26 bits.\n                                                                                    : ... In instance DE10_Standard_FB\n  times[data_count] = counter;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/182333580/software/DE10_Standard_FB.v:558: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'store_flag\' generates 32 bits.\n                                                                                    : ... In instance DE10_Standard_FB\n if (store_flag)\n ^~\n%Error: Exiting due to 6 error(s), 7 warning(s)\n'
module DE10_Standard_FB(


    input              CLOCK2_50,
    input              CLOCK3_50,
    input              CLOCK4_50,
    input              CLOCK_50,


    input    [ 9: 0]   SW,


    output   [ 9: 0]   LEDR,


    output             DRAM_CLK,
    output             DRAM_CKE,
    output   [12: 0]   DRAM_ADDR,
    output   [ 1: 0]   DRAM_BA,
    inout    [15: 0]   DRAM_DQ,
    output             DRAM_LDQM,
    output             DRAM_UDQM,
    output             DRAM_CS_N,
    output             DRAM_WE_N,
    output             DRAM_CAS_N,
    output             DRAM_RAS_N,


    input    [ 3: 0]   KEY,


`ifdef ENABLE_HSMC

	input 		          		ADA_DCO,
	input 		    [13:0]		ADA_D,
	output		          		ADA_OE,
	input 		          		ADA_OR,
	output		          		ADA_SPI_CS,
	input 		          		ADB_DCO,
	input 		    [13:0]		ADB_D,
	output		          		ADB_OE,
	input 		          		ADB_OR,
	output		          		ADB_SPI_CS,
	inout 		          		AD_SCLK,
	inout 		          		AD_SDIO,
	inout 		          		AIC_BCLK,
	output		          		AIC_DIN,
	input 		          		AIC_DOUT,
	inout 		          		AIC_LRCIN,
	inout 		          		AIC_LRCOUT,
	output		          		AIC_SPI_CS,
	output		          		AIC_XCLK,
	input 		          		CLKIN1,
	output		          		CLKOUT0,
	output		    [13:0]		DA,
	output		    [13:0]		DB,
	inout 		          		FPGA_CLK_A_N,
	inout 		          		FPGA_CLK_A_P,
	inout 		          		FPGA_CLK_B_N,
	inout 		          		FPGA_CLK_B_P,
	inout 		          		J1_152,
	output		          		SCL,
	inout 		          		SDA,
	input 		          		XT_IN_N,
	input 		          		XT_IN_P,
`endif


`ifdef ENABLE_HPS

    inout              HPS_CONV_USB_N,
    output   [14: 0]   HPS_DDR3_ADDR,
    output   [ 2: 0]   HPS_DDR3_BA,
    output             HPS_DDR3_CAS_N,
    output             HPS_DDR3_CKE,
    output             HPS_DDR3_CK_N,
    output             HPS_DDR3_CK_P,
    output             HPS_DDR3_CS_N,
    output   [ 3: 0]   HPS_DDR3_DM,
    inout    [31: 0]   HPS_DDR3_DQ,
    inout    [ 3: 0]   HPS_DDR3_DQS_N,
    inout    [ 3: 0]   HPS_DDR3_DQS_P,
    output             HPS_DDR3_ODT,
    output             HPS_DDR3_RAS_N,
    output             HPS_DDR3_RESET_N,
    input              HPS_DDR3_RZQ,
    output             HPS_DDR3_WE_N,
    output             HPS_ENET_GTX_CLK,
    inout              HPS_ENET_INT_N,
    output             HPS_ENET_MDC,
    inout              HPS_ENET_MDIO,
    input              HPS_ENET_RX_CLK,
    input    [ 3: 0]   HPS_ENET_RX_DATA,
    input              HPS_ENET_RX_DV,
    output   [ 3: 0]   HPS_ENET_TX_DATA,
    output             HPS_ENET_TX_EN,
    inout    [ 3: 0]   HPS_FLASH_DATA,
    output             HPS_FLASH_DCLK,
    output             HPS_FLASH_NCSO,
    inout              HPS_GSENSOR_INT,
    inout              HPS_I2C1_SCLK,
    inout              HPS_I2C1_SDAT,
    inout              HPS_I2C2_SCLK,
    inout              HPS_I2C2_SDAT,
    inout              HPS_I2C_CONTROL,
    inout              HPS_KEY,
    inout              HPS_LCM_BK,
    inout              HPS_LCM_D_C,
    inout              HPS_LCM_RST_N,
    output             HPS_LCM_SPIM_CLK,
    output             HPS_LCM_SPIM_MOSI,
    input              HPS_LCM_SPIM_MISO,
    output             HPS_LCM_SPIM_SS,
    inout              HPS_LED,
    inout              HPS_LTC_GPIO,
    output             HPS_SD_CLK,
    inout              HPS_SD_CMD,
    inout    [ 3: 0]   HPS_SD_DATA,
    output             HPS_SPIM_CLK,
    input              HPS_SPIM_MISO,
    output             HPS_SPIM_MOSI,
    output             HPS_SPIM_SS,
    input              HPS_UART_RX,
    output             HPS_UART_TX,
    input              HPS_USB_CLKOUT,
    inout    [ 7: 0]   HPS_USB_DATA,
    input              HPS_USB_DIR,
    input              HPS_USB_NXT,
    output             HPS_USB_STP,
`endif


`ifdef ENABLE_OTHER

    input              TD_CLK27,
    input              TD_HS,
    input              TD_VS,
    input    [ 7: 0]   TD_DATA,
    output             TD_RESET_N,


    inout              AUD_BCLK,
    output             AUD_XCK,
    inout              AUD_ADCLRCK,
    input              AUD_ADCDAT,
    inout              AUD_DACLRCK,
    output             AUD_DACDAT,


    inout              PS2_CLK,
    inout              PS2_CLK2,
    inout              PS2_DAT,
    inout              PS2_DAT2,


    output             ADC_SCLK,
    input              ADC_DOUT,
    output             ADC_DIN,
    output             ADC_CONVST,


    output             FPGA_I2C_SCLK,
    inout              FPGA_I2C_SDAT,


    output   [ 6: 0]   HEX0,
    output   [ 6: 0]   HEX1,
    output   [ 6: 0]   HEX2,
    output   [ 6: 0]   HEX3,
    output   [ 6: 0]   HEX4,
    output   [ 6: 0]   HEX5,



    output             IRDA_TXD,
    input              IRDA_RXD,



    output             VGA_CLK,
    output             VGA_HS,
    output             VGA_VS,
    output   [ 7: 0]   VGA_R,
    output   [ 7: 0]   VGA_G,
    output   [ 7: 0]   VGA_B,
    output             VGA_BLANK_N,
    output             VGA_SYNC_N,
`endif





    inout    [35: 0]   GPIO

);


wire               clk_65, clk_vip;
wire [7:0]         vid_r,vid_g,vid_b;
wire               vid_v_sync;
wire               vid_h_sync;
wire               vid_datavalid;






wire        hps_read;
wire [31:0] data_peak_out;
wire [31:0] data_tail_out;
wire [25:0] data_time_out;

wire        hps_fpga_reset_n;
wire [9:0]  fpga_led_internal;
wire [2:0]  hps_reset_req;
wire        hps_cold_reset;
wire        hps_warm_reset;
wire        hps_debug_reset;
wire [27:0] stm_hw_events;
wire        fpga_clk_50;


assign stm_hw_events = {{4{1'b0}}, SW, fpga_led_internal[8:0]};
assign fpga_clk_50 = CLOCK_50;

wire hps_0_f2h_dma_req0_dma_req;
wire hps_0_f2h_dma_req0_dma_single;
wire hps_0_f2h_dma_req0_dma_ack;
wire hps_0_f2h_dma_req1_dma_req;
wire hps_0_f2h_dma_req1_dma_single;
wire hps_0_f2h_dma_req1_dma_ack;
wire hps_0_f2h_dma_req2_dma_req;
wire hps_0_f2h_dma_req2_dma_single;
wire hps_0_f2h_dma_req2_dma_ack;
wire hps_0_f2h_dma_req3_dma_req;
wire hps_0_f2h_dma_req3_dma_single;
wire hps_0_f2h_dma_req3_dma_ack;














soc_system u0 (
        .clk_clk                               (CLOCK_50),
        .reset_reset_n                         (1'b1),

        .memory_mem_a                          (HPS_DDR3_ADDR),
        .memory_mem_ba                         (HPS_DDR3_BA),
        .memory_mem_ck                         (HPS_DDR3_CK_P),
        .memory_mem_ck_n                       (HPS_DDR3_CK_N),
        .memory_mem_cke                        (HPS_DDR3_CKE),
        .memory_mem_cs_n                       (HPS_DDR3_CS_N),
        .memory_mem_ras_n                      (HPS_DDR3_RAS_N),
        .memory_mem_cas_n                      (HPS_DDR3_CAS_N),
        .memory_mem_we_n                       (HPS_DDR3_WE_N),
        .memory_mem_reset_n                    (HPS_DDR3_RESET_N),
        .memory_mem_dq                         (HPS_DDR3_DQ),
        .memory_mem_dqs                        (HPS_DDR3_DQS_P),
        .memory_mem_dqs_n                      (HPS_DDR3_DQS_N),
        .memory_mem_odt                        (HPS_DDR3_ODT),
        .memory_mem_dm                         (HPS_DDR3_DM),
        .memory_oct_rzqin                      (HPS_DDR3_RZQ),

        .hps_0_hps_io_hps_io_emac1_inst_TX_CLK (HPS_ENET_GTX_CLK),
        .hps_0_hps_io_hps_io_emac1_inst_TXD0   (HPS_ENET_TX_DATA[0]),
        .hps_0_hps_io_hps_io_emac1_inst_TXD1   (HPS_ENET_TX_DATA[1]),
        .hps_0_hps_io_hps_io_emac1_inst_TXD2   (HPS_ENET_TX_DATA[2]),
        .hps_0_hps_io_hps_io_emac1_inst_TXD3   (HPS_ENET_TX_DATA[3]),
        .hps_0_hps_io_hps_io_emac1_inst_RXD0   (HPS_ENET_RX_DATA[0]),
        .hps_0_hps_io_hps_io_emac1_inst_MDIO   (HPS_ENET_MDIO),
        .hps_0_hps_io_hps_io_emac1_inst_MDC    (HPS_ENET_MDC),
        .hps_0_hps_io_hps_io_emac1_inst_RX_CTL (HPS_ENET_RX_DV),
        .hps_0_hps_io_hps_io_emac1_inst_TX_CTL (HPS_ENET_TX_EN),
        .hps_0_hps_io_hps_io_emac1_inst_RX_CLK (HPS_ENET_RX_CLK),
        .hps_0_hps_io_hps_io_emac1_inst_RXD1   (HPS_ENET_RX_DATA[1]),
        .hps_0_hps_io_hps_io_emac1_inst_RXD2   (HPS_ENET_RX_DATA[2]),
        .hps_0_hps_io_hps_io_emac1_inst_RXD3   (HPS_ENET_RX_DATA[3]),

        .hps_0_hps_io_hps_io_qspi_inst_IO0     (HPS_FLASH_DATA[0]),
        .hps_0_hps_io_hps_io_qspi_inst_IO1     (HPS_FLASH_DATA[1]),
        .hps_0_hps_io_hps_io_qspi_inst_IO2     (HPS_FLASH_DATA[2]),
        .hps_0_hps_io_hps_io_qspi_inst_IO3     (HPS_FLASH_DATA[3]),
        .hps_0_hps_io_hps_io_qspi_inst_SS0     (HPS_FLASH_NCSO),
        .hps_0_hps_io_hps_io_qspi_inst_CLK     (HPS_FLASH_DCLK),

        .hps_0_hps_io_hps_io_sdio_inst_CMD     (HPS_SD_CMD),
        .hps_0_hps_io_hps_io_sdio_inst_D0      (HPS_SD_DATA[0]),
        .hps_0_hps_io_hps_io_sdio_inst_D1      (HPS_SD_DATA[1]),
        .hps_0_hps_io_hps_io_sdio_inst_CLK     (HPS_SD_CLK),
        .hps_0_hps_io_hps_io_sdio_inst_D2      (HPS_SD_DATA[2]),
        .hps_0_hps_io_hps_io_sdio_inst_D3      (HPS_SD_DATA[3]),

        .hps_0_hps_io_hps_io_usb1_inst_D0      (HPS_USB_DATA[0]),
        .hps_0_hps_io_hps_io_usb1_inst_D1      (HPS_USB_DATA[1]),
        .hps_0_hps_io_hps_io_usb1_inst_D2      (HPS_USB_DATA[2]),
        .hps_0_hps_io_hps_io_usb1_inst_D3      (HPS_USB_DATA[3]),
        .hps_0_hps_io_hps_io_usb1_inst_D4      (HPS_USB_DATA[4]),
        .hps_0_hps_io_hps_io_usb1_inst_D5      (HPS_USB_DATA[5]),
        .hps_0_hps_io_hps_io_usb1_inst_D6      (HPS_USB_DATA[6]),
        .hps_0_hps_io_hps_io_usb1_inst_D7      (HPS_USB_DATA[7]),
        .hps_0_hps_io_hps_io_usb1_inst_CLK     (HPS_USB_CLKOUT),
        .hps_0_hps_io_hps_io_usb1_inst_STP     (HPS_USB_STP),
        .hps_0_hps_io_hps_io_usb1_inst_DIR     (HPS_USB_DIR),
        .hps_0_hps_io_hps_io_usb1_inst_NXT     (HPS_USB_NXT),

        .hps_0_hps_io_hps_io_spim0_inst_CLK    (HPS_LCM_SPIM_CLK),
        .hps_0_hps_io_hps_io_spim0_inst_MOSI   (HPS_LCM_SPIM_MOSI),
        .hps_0_hps_io_hps_io_spim0_inst_MISO   (HPS_LCM_SPIM_MISO),
        .hps_0_hps_io_hps_io_spim0_inst_SS0    (HPS_LCM_SPIM_SS),

        .hps_0_hps_io_hps_io_spim1_inst_CLK    (HPS_SPIM_CLK),
        .hps_0_hps_io_hps_io_spim1_inst_MOSI   (HPS_SPIM_MOSI),
        .hps_0_hps_io_hps_io_spim1_inst_MISO   (HPS_SPIM_MISO),
        .hps_0_hps_io_hps_io_spim1_inst_SS0    (HPS_SPIM_SS),

        .hps_0_hps_io_hps_io_uart0_inst_RX     (HPS_UART_RX),
        .hps_0_hps_io_hps_io_uart0_inst_TX     (HPS_UART_TX),

        .hps_0_hps_io_hps_io_i2c0_inst_SDA     (HPS_I2C1_SDAT),
        .hps_0_hps_io_hps_io_i2c0_inst_SCL     (HPS_I2C1_SCLK),

        .hps_0_hps_io_hps_io_i2c1_inst_SDA     (HPS_I2C2_SDAT),
        .hps_0_hps_io_hps_io_i2c1_inst_SCL     (HPS_I2C2_SCLK),

        .hps_0_hps_io_hps_io_gpio_inst_GPIO09  (HPS_CONV_USB_N),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO35  (HPS_ENET_INT_N),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO37  (HPS_LCM_BK),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO40  (HPS_LTC_GPIO),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO41  (HPS_LCM_D_C),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO44  (HPS_LCM_RST_N),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO48  (HPS_I2C_CONTROL),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO53  (HPS_LED),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO54  (HPS_KEY),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO61  (HPS_GSENSOR_INT),

        .hps_0_h2f_reset_reset_n               (hps_fpga_reset_n),
        .hps_0_f2h_cold_reset_req_reset_n      (~hps_cold_reset),
        .hps_0_f2h_debug_reset_req_reset_n     (~hps_debug_reset),
        .hps_0_f2h_stm_hw_events_stm_hwevents  (stm_hw_events),
        .hps_0_f2h_warm_reset_req_reset_n      (~hps_warm_reset),




        .ledr_external_connection_export            (fpga_led_internal),
        .sw_external_connection_export              (SW),


        .ddc_peak_out_external_connection_export	 (data_peak_out),
        .ddc_tail_out_external_connection_export	 (data_tail_out),
        .ddc_time_out_external_connection_export	 (data_time_out),
        .hps_read_bit_external_connection_export    (hps_read)

);


DE10_Standard_DCC_TOP DCC_TOP_ins(
    .CLK(CLOCK_50),
    .KEY(KEY),
    .SW(SW),
    .LED(LEDR),
    .AD_SCLK(AD_SCLK),
    .AD_SDIO(AD_SDIO),
    .ADA_D(ADA_D),
    .ADA_DCO(ADA_DCO),
    .ADA_OE(ADA_OE),
    .ADA_OR(ADA_OR),
    .ADA_SPI_CS(ADA_SPI_CS),
    .ADB_D(ADB_D),
    .ADB_DCO(ADB_DCO),
    .ADB_OE(ADB_OE),
    .ADB_OR(ADB_OR),
    .ADB_SPI_CS(ADB_SPI_CS),
    .AIC_BCLK(AIC_BCLK),
    .AIC_DIN(AIC_DIN),
    .AIC_DOUT(AIC_DOUT),
    .AIC_LRCIN(AIC_LRCIN),
    .AIC_LRCOUT(AIC_LRCOUT),
    .AIC_SPI_CS(AIC_SPI_CS),
    .AIC_XCLK(AIC_XCLK),
    .CLKIN1(CLKIN1),
    .CLKOUT0(CLKOUT0),
    .DA(DA),
    .DB(DB),
    .FPGA_CLK_A_N(FPGA_CLK_A_N),
    .FPGA_CLK_A_P(FPGA_CLK_A_P),
    .FPGA_CLK_B_N(FPGA_CLK_B_N),
    .FPGA_CLK_B_P(FPGA_CLK_B_P),
    .J1_152(J1_152),
    .XT_IN_N(XT_IN_N),
    .XT_IN_P(XT_IN_P)
	);



hps_reset hps_reset_inst (
        .source_clk (fpga_clk_50),
        .source     (hps_reset_req)
);

altera_edge_detector pulse_cold_reset (
        .clk       (fpga_clk_50),
        .rst_n     (hps_fpga_reset_n),
        .signal_in (hps_reset_req[0]),
        .pulse_out (hps_cold_reset)
);
defparam pulse_cold_reset.PULSE_EXT = 6;
defparam pulse_cold_reset.EDGE_TYPE = 1;
defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1;

altera_edge_detector pulse_warm_reset (
        .clk       (fpga_clk_50),
        .rst_n     (hps_fpga_reset_n),
        .signal_in (hps_reset_req[1]),
        .pulse_out (hps_warm_reset)
);
defparam pulse_warm_reset.PULSE_EXT = 2;
defparam pulse_warm_reset.EDGE_TYPE = 1;
defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1;

altera_edge_detector pulse_debug_reset (
        .clk       (fpga_clk_50),
        .rst_n     (hps_fpga_reset_n),
        .signal_in (hps_reset_req[2]),
        .pulse_out (hps_debug_reset)
);
defparam pulse_debug_reset.PULSE_EXT = 32;
defparam pulse_debug_reset.EDGE_TYPE = 1;
defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1;


reg [25:0] counter;
reg  led_level;
always @(posedge fpga_clk_50 or negedge hps_fpga_reset_n)
begin
    if(~hps_fpga_reset_n)
    begin
        counter<=0;
        led_level<=0;
    end

    else if(counter==49999999)
    begin
        counter<=0;
        led_level<=~led_level;
    end
	 else
        counter<=counter+1'b1;

end

assign LEDR[9]=led_level;
















parameter WINDOW_SIZE = 20;

integer post_window_count, store_flag, data_count, time_index, a_index, b_index, pre_index, post_index;
reg			[31:0]			ddc_time;


reg			[15:0]			a_data;
reg			[15:0]			b_data;

reg		 	[15:0]			a_pre_window[3:0];
reg		 	[15:0]			b_pre_window[3:0];

reg		 	[15:0]			a_post_window[27:0];
reg		 	[15:0]			b_post_window[27:0];


reg								triggered;


reg         [31:0]          full_data[319:0];

reg         [31:0]          times[9:0];


always @(posedge ADA_DCO)
begin	
	if(ADA_D <= -2170)
	begin
		triggered = 1;
		post_window_count = 0;
	end
	
	if(triggered)
	begin
		a_post_window[post_window_count] = ADA_D;
		b_post_window[post_window_count] = ADB_D;
		post_window_count=post_window_count+1;
		
		if(post_window_count>27)
		begin
			triggered = 0;
			store_flag = 1;
		end
	end
	else
	begin
	

		for(a_index=1;a_index<3;a_index=a_index+1)
		begin
			a_pre_window[a_index] = a_pre_window[a_index+1];
		end
		a_pre_window[3] = ADA_D;
		

		for(b_index=1;b_index<3;b_index=b_index+1)
		begin
			b_pre_window[b_index] = b_pre_window[b_index+1];
		end
		b_pre_window[3] = ADB_D;
	end
	
end

always @(negedge ADA_DCO)
begin
	if (store_flag)
	begin

		

		for(pre_index=0;pre_index<4;pre_index=pre_index+1)
		begin
			full_data[data_count*32+pre_index] = {a_pre_window[pre_index], b_pre_window[pre_index]};
		end
		

		for(post_index=0;post_index<28;post_index=post_index+1)
		begin
			full_data[data_count*32+post_index+4] = {a_post_window[post_index], b_post_window[post_index]};
		end
		

		times[data_count] = counter;
		
		data_count = data_count + 1;
		store_flag = 0;
	end
end



































endmodule
module DE10_Standard_FB(


    input              CLOCK2_50,
    input              CLOCK3_50,
    input              CLOCK4_50,
    input              CLOCK_50,


    input    [ 9: 0]   SW,


    output   [ 9: 0]   LEDR,


    output             DRAM_CLK,
    output             DRAM_CKE,
    output   [12: 0]   DRAM_ADDR,
    output   [ 1: 0]   DRAM_BA,
    inout    [15: 0]   DRAM_DQ,
    output             DRAM_LDQM,
    output             DRAM_UDQM,
    output             DRAM_CS_N,
    output             DRAM_WE_N,
    output             DRAM_CAS_N,
    output             DRAM_RAS_N,


    input    [ 3: 0]   KEY,


`ifdef ENABLE_HSMC

	input 		          		ADA_DCO,
	input 		    [13:0]		ADA_D,
	output		          		ADA_OE,
	input 		          		ADA_OR,
	output		          		ADA_SPI_CS,
	input 		          		ADB_DCO,
	input 		    [13:0]		ADB_D,
	output		          		ADB_OE,
	input 		          		ADB_OR,
	output		          		ADB_SPI_CS,
	inout 		          		AD_SCLK,
	inout 		          		AD_SDIO,
	inout 		          		AIC_BCLK,
	output		          		AIC_DIN,
	input 		          		AIC_DOUT,
	inout 		          		AIC_LRCIN,
	inout 		          		AIC_LRCOUT,
	output		          		AIC_SPI_CS,
	output		          		AIC_XCLK,
	input 		          		CLKIN1,
	output		          		CLKOUT0,
	output		    [13:0]		DA,
	output		    [13:0]		DB,
	inout 		          		FPGA_CLK_A_N,
	inout 		          		FPGA_CLK_A_P,
	inout 		          		FPGA_CLK_B_N,
	inout 		          		FPGA_CLK_B_P,
	inout 		          		J1_152,
	output		          		SCL,
	inout 		          		SDA,
	input 		          		XT_IN_N,
	input 		          		XT_IN_P,
`endif


`ifdef ENABLE_HPS

    inout              HPS_CONV_USB_N,
    output   [14: 0]   HPS_DDR3_ADDR,
    output   [ 2: 0]   HPS_DDR3_BA,
    output             HPS_DDR3_CAS_N,
    output             HPS_DDR3_CKE,
    output             HPS_DDR3_CK_N,
    output             HPS_DDR3_CK_P,
    output             HPS_DDR3_CS_N,
    output   [ 3: 0]   HPS_DDR3_DM,
    inout    [31: 0]   HPS_DDR3_DQ,
    inout    [ 3: 0]   HPS_DDR3_DQS_N,
    inout    [ 3: 0]   HPS_DDR3_DQS_P,
    output             HPS_DDR3_ODT,
    output             HPS_DDR3_RAS_N,
    output             HPS_DDR3_RESET_N,
    input              HPS_DDR3_RZQ,
    output             HPS_DDR3_WE_N,
    output             HPS_ENET_GTX_CLK,
    inout              HPS_ENET_INT_N,
    output             HPS_ENET_MDC,
    inout              HPS_ENET_MDIO,
    input              HPS_ENET_RX_CLK,
    input    [ 3: 0]   HPS_ENET_RX_DATA,
    input              HPS_ENET_RX_DV,
    output   [ 3: 0]   HPS_ENET_TX_DATA,
    output             HPS_ENET_TX_EN,
    inout    [ 3: 0]   HPS_FLASH_DATA,
    output             HPS_FLASH_DCLK,
    output             HPS_FLASH_NCSO,
    inout              HPS_GSENSOR_INT,
    inout              HPS_I2C1_SCLK,
    inout              HPS_I2C1_SDAT,
    inout              HPS_I2C2_SCLK,
    inout              HPS_I2C2_SDAT,
    inout              HPS_I2C_CONTROL,
    inout              HPS_KEY,
    inout              HPS_LCM_BK,
    inout              HPS_LCM_D_C,
    inout              HPS_LCM_RST_N,
    output             HPS_LCM_SPIM_CLK,
    output             HPS_LCM_SPIM_MOSI,
    input              HPS_LCM_SPIM_MISO,
    output             HPS_LCM_SPIM_SS,
    inout              HPS_LED,
    inout              HPS_LTC_GPIO,
    output             HPS_SD_CLK,
    inout              HPS_SD_CMD,
    inout    [ 3: 0]   HPS_SD_DATA,
    output             HPS_SPIM_CLK,
    input              HPS_SPIM_MISO,
    output             HPS_SPIM_MOSI,
    output             HPS_SPIM_SS,
    input              HPS_UART_RX,
    output             HPS_UART_TX,
    input              HPS_USB_CLKOUT,
    inout    [ 7: 0]   HPS_USB_DATA,
    input              HPS_USB_DIR,
    input              HPS_USB_NXT,
    output             HPS_USB_STP,
`endif


`ifdef ENABLE_OTHER

    input              TD_CLK27,
    input              TD_HS,
    input              TD_VS,
    input    [ 7: 0]   TD_DATA,
    output             TD_RESET_N,


    inout              AUD_BCLK,
    output             AUD_XCK,
    inout              AUD_ADCLRCK,
    input              AUD_ADCDAT,
    inout              AUD_DACLRCK,
    output             AUD_DACDAT,


    inout              PS2_CLK,
    inout              PS2_CLK2,
    inout              PS2_DAT,
    inout              PS2_DAT2,


    output             ADC_SCLK,
    input              ADC_DOUT,
    output             ADC_DIN,
    output             ADC_CONVST,


    output             FPGA_I2C_SCLK,
    inout              FPGA_I2C_SDAT,


    output   [ 6: 0]   HEX0,
    output   [ 6: 0]   HEX1,
    output   [ 6: 0]   HEX2,
    output   [ 6: 0]   HEX3,
    output   [ 6: 0]   HEX4,
    output   [ 6: 0]   HEX5,



    output             IRDA_TXD,
    input              IRDA_RXD,



    output             VGA_CLK,
    output             VGA_HS,
    output             VGA_VS,
    output   [ 7: 0]   VGA_R,
    output   [ 7: 0]   VGA_G,
    output   [ 7: 0]   VGA_B,
    output             VGA_BLANK_N,
    output             VGA_SYNC_N,
`endif





    inout    [35: 0]   GPIO

);



wire               clk_65, clk_vip;
wire [7:0]         vid_r,vid_g,vid_b;
wire               vid_v_sync;
wire               vid_h_sync;
wire               vid_datavalid;






wire        hps_read;
wire [31:0] data_peak_out;
wire [31:0] data_tail_out;
wire [25:0] data_time_out;

wire        hps_fpga_reset_n;
wire [9:0]  fpga_led_internal;
wire [2:0]  hps_reset_req;
wire        hps_cold_reset;
wire        hps_warm_reset;
wire        hps_debug_reset;
wire [27:0] stm_hw_events;
wire        fpga_clk_50;


assign stm_hw_events = {{4{1'b0}}, SW, fpga_led_internal[8:0]};
assign fpga_clk_50 = CLOCK_50;

wire hps_0_f2h_dma_req0_dma_req;
wire hps_0_f2h_dma_req0_dma_single;
wire hps_0_f2h_dma_req0_dma_ack;
wire hps_0_f2h_dma_req1_dma_req;
wire hps_0_f2h_dma_req1_dma_single;
wire hps_0_f2h_dma_req1_dma_ack;
wire hps_0_f2h_dma_req2_dma_req;
wire hps_0_f2h_dma_req2_dma_single;
wire hps_0_f2h_dma_req2_dma_ack;
wire hps_0_f2h_dma_req3_dma_req;
wire hps_0_f2h_dma_req3_dma_single;
wire hps_0_f2h_dma_req3_dma_ack;














soc_system u0 (
        .clk_clk                               (CLOCK_50),
        .reset_reset_n                         (1'b1),

        .memory_mem_a                          (HPS_DDR3_ADDR),
        .memory_mem_ba                         (HPS_DDR3_BA),
        .memory_mem_ck                         (HPS_DDR3_CK_P),
        .memory_mem_ck_n                       (HPS_DDR3_CK_N),
        .memory_mem_cke                        (HPS_DDR3_CKE),
        .memory_mem_cs_n                       (HPS_DDR3_CS_N),
        .memory_mem_ras_n                      (HPS_DDR3_RAS_N),
        .memory_mem_cas_n                      (HPS_DDR3_CAS_N),
        .memory_mem_we_n                       (HPS_DDR3_WE_N),
        .memory_mem_reset_n                    (HPS_DDR3_RESET_N),
        .memory_mem_dq                         (HPS_DDR3_DQ),
        .memory_mem_dqs                        (HPS_DDR3_DQS_P),
        .memory_mem_dqs_n                      (HPS_DDR3_DQS_N),
        .memory_mem_odt                        (HPS_DDR3_ODT),
        .memory_mem_dm                         (HPS_DDR3_DM),
        .memory_oct_rzqin                      (HPS_DDR3_RZQ),

        .hps_0_hps_io_hps_io_emac1_inst_TX_CLK (HPS_ENET_GTX_CLK),
        .hps_0_hps_io_hps_io_emac1_inst_TXD0   (HPS_ENET_TX_DATA[0]),
        .hps_0_hps_io_hps_io_emac1_inst_TXD1   (HPS_ENET_TX_DATA[1]),
        .hps_0_hps_io_hps_io_emac1_inst_TXD2   (HPS_ENET_TX_DATA[2]),
        .hps_0_hps_io_hps_io_emac1_inst_TXD3   (HPS_ENET_TX_DATA[3]),
        .hps_0_hps_io_hps_io_emac1_inst_RXD0   (HPS_ENET_RX_DATA[0]),
        .hps_0_hps_io_hps_io_emac1_inst_MDIO   (HPS_ENET_MDIO),
        .hps_0_hps_io_hps_io_emac1_inst_MDC    (HPS_ENET_MDC),
        .hps_0_hps_io_hps_io_emac1_inst_RX_CTL (HPS_ENET_RX_DV),
        .hps_0_hps_io_hps_io_emac1_inst_TX_CTL (HPS_ENET_TX_EN),
        .hps_0_hps_io_hps_io_emac1_inst_RX_CLK (HPS_ENET_RX_CLK),
        .hps_0_hps_io_hps_io_emac1_inst_RXD1   (HPS_ENET_RX_DATA[1]),
        .hps_0_hps_io_hps_io_emac1_inst_RXD2   (HPS_ENET_RX_DATA[2]),
        .hps_0_hps_io_hps_io_emac1_inst_RXD3   (HPS_ENET_RX_DATA[3]),

        .hps_0_hps_io_hps_io_qspi_inst_IO0     (HPS_FLASH_DATA[0]),
        .hps_0_hps_io_hps_io_qspi_inst_IO1     (HPS_FLASH_DATA[1]),
        .hps_0_hps_io_hps_io_qspi_inst_IO2     (HPS_FLASH_DATA[2]),
        .hps_0_hps_io_hps_io_qspi_inst_IO3     (HPS_FLASH_DATA[3]),
        .hps_0_hps_io_hps_io_qspi_inst_SS0     (HPS_FLASH_NCSO),
        .hps_0_hps_io_hps_io_qspi_inst_CLK     (HPS_FLASH_DCLK),

        .hps_0_hps_io_hps_io_sdio_inst_CMD     (HPS_SD_CMD),
        .hps_0_hps_io_hps_io_sdio_inst_D0      (HPS_SD_DATA[0]),
        .hps_0_hps_io_hps_io_sdio_inst_D1      (HPS_SD_DATA[1]),
        .hps_0_hps_io_hps_io_sdio_inst_CLK     (HPS_SD_CLK),
        .hps_0_hps_io_hps_io_sdio_inst_D2      (HPS_SD_DATA[2]),
        .hps_0_hps_io_hps_io_sdio_inst_D3      (HPS_SD_DATA[3]),

        .hps_0_hps_io_hps_io_usb1_inst_D0      (HPS_USB_DATA[0]),
        .hps_0_hps_io_hps_io_usb1_inst_D1      (HPS_USB_DATA[1]),
        .hps_0_hps_io_hps_io_usb1_inst_D2      (HPS_USB_DATA[2]),
        .hps_0_hps_io_hps_io_usb1_inst_D3      (HPS_USB_DATA[3]),
        .hps_0_hps_io_hps_io_usb1_inst_D4      (HPS_USB_DATA[4]),
        .hps_0_hps_io_hps_io_usb1_inst_D5      (HPS_USB_DATA[5]),
        .hps_0_hps_io_hps_io_usb1_inst_D6      (HPS_USB_DATA[6]),
        .hps_0_hps_io_hps_io_usb1_inst_D7      (HPS_USB_DATA[7]),
        .hps_0_hps_io_hps_io_usb1_inst_CLK     (HPS_USB_CLKOUT),
        .hps_0_hps_io_hps_io_usb1_inst_STP     (HPS_USB_STP),
        .hps_0_hps_io_hps_io_usb1_inst_DIR     (HPS_USB_DIR),
        .hps_0_hps_io_hps_io_usb1_inst_NXT     (HPS_USB_NXT),

        .hps_0_hps_io_hps_io_spim0_inst_CLK    (HPS_LCM_SPIM_CLK),
        .hps_0_hps_io_hps_io_spim0_inst_MOSI   (HPS_LCM_SPIM_MOSI),
        .hps_0_hps_io_hps_io_spim0_inst_MISO   (HPS_LCM_SPIM_MISO),
        .hps_0_hps_io_hps_io_spim0_inst_SS0    (HPS_LCM_SPIM_SS),

        .hps_0_hps_io_hps_io_spim1_inst_CLK    (HPS_SPIM_CLK),
        .hps_0_hps_io_hps_io_spim1_inst_MOSI   (HPS_SPIM_MOSI),
        .hps_0_hps_io_hps_io_spim1_inst_MISO   (HPS_SPIM_MISO),
        .hps_0_hps_io_hps_io_spim1_inst_SS0    (HPS_SPIM_SS),

        .hps_0_hps_io_hps_io_uart0_inst_RX     (HPS_UART_RX),
        .hps_0_hps_io_hps_io_uart0_inst_TX     (HPS_UART_TX),

        .hps_0_hps_io_hps_io_i2c0_inst_SDA     (HPS_I2C1_SDAT),
        .hps_0_hps_io_hps_io_i2c0_inst_SCL     (HPS_I2C1_SCLK),

        .hps_0_hps_io_hps_io_i2c1_inst_SDA     (HPS_I2C2_SDAT),
        .hps_0_hps_io_hps_io_i2c1_inst_SCL     (HPS_I2C2_SCLK),

        .hps_0_hps_io_hps_io_gpio_inst_GPIO09  (HPS_CONV_USB_N),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO35  (HPS_ENET_INT_N),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO37  (HPS_LCM_BK),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO40  (HPS_LTC_GPIO),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO41  (HPS_LCM_D_C),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO44  (HPS_LCM_RST_N),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO48  (HPS_I2C_CONTROL),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO53  (HPS_LED),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO54  (HPS_KEY),
        .hps_0_hps_io_hps_io_gpio_inst_GPIO61  (HPS_GSENSOR_INT),

        .hps_0_h2f_reset_reset_n               (hps_fpga_reset_n),
        .hps_0_f2h_cold_reset_req_reset_n      (~hps_cold_reset),
        .hps_0_f2h_debug_reset_req_reset_n     (~hps_debug_reset),
        .hps_0_f2h_stm_hw_events_stm_hwevents  (stm_hw_events),
        .hps_0_f2h_warm_reset_req_reset_n      (~hps_warm_reset),




        .ledr_external_connection_export            (fpga_led_internal),
        .sw_external_connection_export              (SW),


        .ddc_peak_out_external_connection_export	 (data_peak_out),
        .ddc_tail_out_external_connection_export	 (data_tail_out),
        .ddc_time_out_external_connection_export	 (data_time_out),
        .hps_read_bit_external_connection_export    (hps_read)

);


DE10_Standard_DCC_TOP DCC_TOP_ins(
    .CLK(CLOCK_50),
    .KEY(KEY),
    .SW(SW),
    .LED(LEDR),
    .AD_SCLK(AD_SCLK),
    .AD_SDIO(AD_SDIO),
    .ADA_D(ADA_D),
    .ADA_DCO(ADA_DCO),
    .ADA_OE(ADA_OE),
    .ADA_OR(ADA_OR),
    .ADA_SPI_CS(ADA_SPI_CS),
    .ADB_D(ADB_D),
    .ADB_DCO(ADB_DCO),
    .ADB_OE(ADB_OE),
    .ADB_OR(ADB_OR),
    .ADB_SPI_CS(ADB_SPI_CS),
    .AIC_BCLK(AIC_BCLK),
    .AIC_DIN(AIC_DIN),
    .AIC_DOUT(AIC_DOUT),
    .AIC_LRCIN(AIC_LRCIN),
    .AIC_LRCOUT(AIC_LRCOUT),
    .AIC_SPI_CS(AIC_SPI_CS),
    .AIC_XCLK(AIC_XCLK),
    .CLKIN1(CLKIN1),
    .CLKOUT0(CLKOUT0),
    .DA(DA),
    .DB(DB),
    .FPGA_CLK_A_N(FPGA_CLK_A_N),
    .FPGA_CLK_A_P(FPGA_CLK_A_P),
    .FPGA_CLK_B_N(FPGA_CLK_B_N),
    .FPGA_CLK_B_P(FPGA_CLK_B_P),
    .J1_152(J1_152),
    .XT_IN_N(XT_IN_N),
    .XT_IN_P(XT_IN_P)
	);



hps_reset hps_reset_inst (
        .source_clk (fpga_clk_50),
        .source     (hps_reset_req)
);

altera_edge_detector pulse_cold_reset (
        .clk       (fpga_clk_50),
        .rst_n     (hps_fpga_reset_n),
        .signal_in (hps_reset_req[0]),
        .pulse_out (hps_cold_reset)
);
defparam pulse_cold_reset.PULSE_EXT = 6;
defparam pulse_cold_reset.EDGE_TYPE = 1;
defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1;

altera_edge_detector pulse_warm_reset (
        .clk       (fpga_clk_50),
        .rst_n     (hps_fpga_reset_n),
        .signal_in (hps_reset_req[1]),
        .pulse_out (hps_warm_reset)
);
defparam pulse_warm_reset.PULSE_EXT = 2;
defparam pulse_warm_reset.EDGE_TYPE = 1;
defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1;

altera_edge_detector pulse_debug_reset (
        .clk       (fpga_clk_50),
        .rst_n     (hps_fpga_reset_n),
        .signal_in (hps_reset_req[2]),
        .pulse_out (hps_debug_reset)
);
defparam pulse_debug_reset.PULSE_EXT = 32;
defparam pulse_debug_reset.EDGE_TYPE = 1;
defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1;


reg [25:0] counter;
reg  led_level;
always @(posedge fpga_clk_50 or negedge hps_fpga_reset_n)
begin
    if(~hps_fpga_reset_n)
    begin
        counter<=0;
        led_level<=0;
    end

    else if(counter==49999999)
    begin
        counter<=0;
        led_level<=~led_level;
    end
	 else
        counter<=counter+1'b1;

end

assign LEDR[9]=led_level;
















parameter WINDOW_SIZE = 20;

integer post_window_count, store_flag, data_count, time_index, a_index, b_index, pre_index, post_index;
reg			[31:0]			ddc_time;


reg			[15:0]			a_data;
reg			[15:0]			b_data;

reg		 	[15:0]			a_pre_window[3:0];
reg		 	[15:0]			b_pre_window[3:0];

reg		 	[15:0]			a_post_window[27:0];
reg		 	[15:0]			b_post_window[27:0];


reg								triggered;


reg         [31:0]          full_data[319:0];

reg         [31:0]          times[9:0];


always @(posedge ADA_DCO)
begin	
	if(ADA_D <= -2170)
	begin
		triggered = 1;
		post_window_count = 0;
	end
	
	if(triggered)
	begin
		a_post_window[post_window_count] = ADA_D;
		b_post_window[post_window_count] = ADB_D;
		post_window_count=post_window_count+1;
		
		if(post_window_count>27)
		begin
			triggered = 0;
			store_flag = 1;
		end
	end
	else
	begin
	

		for(a_index=1;a_index<3;a_index=a_index+1)
		begin
			a_pre_window[a_index] = a_pre_window[a_index+1];
		end
		a_pre_window[3] = ADA_D;
		

		for(b_index=1;b_index<3;b_index=b_index+1)
		begin
			b_pre_window[b_index] = b_pre_window[b_index+1];
		end
		b_pre_window[3] = ADB_D;
	end
	
end

always @(negedge ADA_DCO)
begin
	if (store_flag)
	begin

		

		for(pre_index=0;pre_index<4;pre_index=pre_index+1)
		begin
			full_data[data_count*32+pre_index] = {a_pre_window[pre_index], b_pre_window[pre_index]};
		end
		

		for(post_index=0;post_index<28;post_index=post_index+1)
		begin
			full_data[data_count*32+post_index+4] = {a_post_window[post_index], b_post_window[post_index]};
		end
		

		times[data_count] = counter;
		
		data_count = data_count + 1;
		store_flag = 0;
	end
end



































endmodule