data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv
 line:63: before: "unsigned"
1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:23: Cannot find file containing module: 'shift_out_reg_right'\nshift_out_reg_right #(8) sr(CLK, EN & ready, bit_inc, DATA, sr_q);\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right.v\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right.sv\n             shift_out_reg_right\n             shift_out_reg_right.v\n             shift_out_reg_right.sv\n             obj_dir/shift_out_reg_right\n             obj_dir/shift_out_reg_right.v\n             obj_dir/shift_out_reg_right.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:25: Cannot find file containing module: 'counter'\ncounter #(16) bit_counter (CLK, ready | bit_done, 1'b1, bit_cnt  );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:27: Cannot find file containing module: 'counter'\ncounter #(3)  byte_counter(CLK, ready,         bit_inc, byte_cnt );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:31: Cannot find file containing module: 'ffd'\nffd #(1) parity_fd(CLK, RESET, (EN & ready) | bit_inc, par_fd_in, par_fd_q);\n^~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:32: Cannot find file containing module: 'ffd'\nffd #(1) output_fd(CLK, RESET, 1'b1, tx_logic, TX );\n^~~\n%Error: Exiting due to 5 error(s)\n"
module uart_tx_fsm( input  CLK,
                    input  RESET,
                    input  EN,
                    input  BIT_DONE,
                    input  BYTE_DONE,
                    input  PARITY_EN,
                    output READY,
                    output PAR_OVR,
                    output FSM_OVR,
                    output FSM_VAL );

enum int unsigned { ST_READY      = 0, 
                    ST_START_BIT  = 1, 
                    ST_DATA_BIT   = 2,
                    ST_PARITY_BIT = 3, 
                    ST_STOP_BIT   = 4 } state, next;

always_ff@(posedge CLK)
  if(RESET) state <= ST_READY;
  else      state <= next;

always_comb begin
  next = ST_READY;
  case(state)
  ST_READY:      if(EN)                next = ST_START_BIT;
                 else                  next = state;
                
  ST_START_BIT:  if(BIT_DONE)          next = ST_DATA_BIT;
                 else                  next = state;
                
  ST_DATA_BIT:   if(BIT_DONE & 
                    BYTE_DONE)
                    begin
                     if(PARITY_EN)     next = ST_PARITY_BIT;
                     else              next = ST_STOP_BIT;
                    end       
                 else                  next = state;

  ST_PARITY_BIT: if(BIT_DONE)          next = ST_STOP_BIT;
                 else                  next = state;
                
  ST_STOP_BIT:   if(BIT_DONE)          next = ST_READY;
                 else                  next = state;
  
  default:                             next = ST_READY;
  endcase
end

assign READY   = (state == ST_READY );

assign PAR_OVR = (state == ST_PARITY_BIT);

assign FSM_OVR = (state != ST_DATA_BIT);

assign FSM_VAL = ((state == ST_READY)  | 
                  (state == ST_STOP_BIT));

endmodule
module uart_tx_fsm( input  CLK,
                    input  RESET,
                    input  EN,
                    input  BIT_DONE,
                    input  BYTE_DONE,
                    input  PARITY_EN,
                    output READY,
                    output PAR_OVR,
                    output FSM_OVR,
                    output FSM_VAL );


enum int unsigned { ST_READY      = 0, 
                    ST_START_BIT  = 1, 
                    ST_DATA_BIT   = 2,
                    ST_PARITY_BIT = 3, 
                    ST_STOP_BIT   = 4 } state, next;

always_ff@(posedge CLK)
  if(RESET) state <= ST_READY;
  else      state <= next;

always_comb begin
  next = ST_READY;
  case(state)
  ST_READY:      if(EN)                next = ST_START_BIT;
                 else                  next = state;
                
  ST_START_BIT:  if(BIT_DONE)          next = ST_DATA_BIT;
                 else                  next = state;
                
  ST_DATA_BIT:   if(BIT_DONE & 
                    BYTE_DONE)
                    begin
                     if(PARITY_EN)     next = ST_PARITY_BIT;
                     else              next = ST_STOP_BIT;
                    end       
                 else                  next = state;

  ST_PARITY_BIT: if(BIT_DONE)          next = ST_STOP_BIT;
                 else                  next = state;
                
  ST_STOP_BIT:   if(BIT_DONE)          next = ST_READY;
                 else                  next = state;
  
  default:                             next = ST_READY;
  endcase
end

assign READY   = (state == ST_READY );

assign PAR_OVR = (state == ST_PARITY_BIT);

assign FSM_OVR = (state != ST_DATA_BIT);

assign FSM_VAL = ((state == ST_READY)  | 
                  (state == ST_STOP_BIT));

endmodule