data/full_repos/permissive/158922207/Verilog Design/modules/Memory.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/Memory.v\n%Error: Exiting due to 3 error(s)\n'
module Memory(R_data, W_data, Addr, W_en,R_en, clock, reset);
parameter width = 32;
parameter addr_width = 32;
parameter number = 63;

output wire [width-1:0] R_data;
input [width-1:0] W_data;
input W_en,R_en, clock, reset;
input [addr_width-1:0]  Addr;

reg [width-1:0] memory [number-1:0];

reg[addr_width-1:0] i;
initial begin
 for (i = 0; i < number; i = i+1)
 	memory[i] <= 0;
end

always @(posedge clock or posedge reset) begin
if (reset)
for (i = 0; i < number; i = i+1)
  memory[i] <= 0;
else begin
if (W_en)
    memory[Addr] <= W_data;
end
end

assign R_data = (R_en) ? memory[Addr]: 32'd0;
endmodule
module Memory(R_data, W_data, Addr, W_en,R_en, clock, reset);

parameter width = 32;
parameter addr_width = 32;
parameter number = 63;

output wire [width-1:0] R_data;
input [width-1:0] W_data;
input W_en,R_en, clock, reset;
input [addr_width-1:0]  Addr;

reg [width-1:0] memory [number-1:0];

reg[addr_width-1:0] i;
initial begin
 for (i = 0; i < number; i = i+1)
 	memory[i] <= 0;
end

always @(posedge clock or posedge reset) begin
if (reset)
for (i = 0; i < number; i = i+1)
  memory[i] <= 0;
else begin
if (W_en)
    memory[Addr] <= W_data;
end
end

assign R_data = (R_en) ? memory[Addr]: 32'd0;
endmodule