data/full_repos/permissive/179980995/Lab2/main.v
data/verilator_xmls/ffe682a8-a3d9-41a3-a9f9-e88c87fa4fb3.xml
module alu_4b(
input [3:0] a,
input [3:0] b,
input cin,
input m,
input [1:0] s,
output [3:0] f,
output cout
);
wire c1, c2, c3;
alu alu1(a[0], b[0], cin, m, s, f[0], c1);
alu alu2(a[1], b[1], c1, m, s, f[1], c2);
alu alu3(a[2], b[2], c2, m, s, f[2], c3);
alu alu4(a[3], b[3], c3, m, s, f[3], cout);
endmodule
module alu_4b(
input [3:0] a,
input [3:0] b,
input cin,
input m,
input [1:0] s,
output [3:0] f,
output cout
);

wire c1, c2, c3;
alu alu1(a[0], b[0], cin, m, s, f[0], c1);
alu alu2(a[1], b[1], c1, m, s, f[1], c2);
alu alu3(a[2], b[2], c2, m, s, f[2], c3);
alu alu4(a[3], b[3], c3, m, s, f[3], cout);
endmodule