data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/IPx2Sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/IPx2Sim.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #(10) reset =1\'b1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/IPx2Sim.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #(10) reset =1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/IPx2Sim.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk=~clk;\n  ^\n%Error: data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/IPx2Sim.v:36: Cannot find file containing module: \'IP\'\nIP #(DATA_WIDTH, 4\'b1111, FREQ) IP1 (.DataOutIP(Data1), .Outr(Line1),.Outw(Line2),.DataInIP(Data2),\n^~\n        ... Looked in:\n             data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim,data/full_repos/permissive/163602545/IP\n             data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim,data/full_repos/permissive/163602545/IP.v\n             data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim,data/full_repos/permissive/163602545/IP.sv\n             IP\n             IP.v\n             IP.sv\n             obj_dir/IP\n             obj_dir/IP.v\n             obj_dir/IP.sv\n%Error: data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/IPx2Sim.v:38: Cannot find file containing module: \'IP\'\nIP #(DATA_WIDTH, 4\'b0000, FREQ) IP2 (.DataOutIP(Data2), .Outr(Line3),.Outw(Line4),.DataInIP(Data1),\n^~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module IPx2Sim
   #(  parameter DATA_WIDTH = 37,
       parameter FREQ = 4 
   
)
();

reg clk;
reg reset;

initial 
begin 
  $display("Start simulation at %t",$time); 
  clk=0;
  reset=0;
  #(10) reset =1'b1;
  #(10) reset =1'b0;
end
always
begin
  #1 clk=~clk;
end



wire [DATA_WIDTH-1:0] Data1, Data2;
wire Line1,Line2,Line3,Line4;
IP #(DATA_WIDTH, 4'b1111, FREQ) IP1 (.DataOutIP(Data1), .Outr(Line1),.Outw(Line2),.DataInIP(Data2),
                                     .Inr(Line3),.Inw(Line4),.clk(clk),.reset(reset));
IP #(DATA_WIDTH, 4'b0000, FREQ) IP2 (.DataOutIP(Data2), .Outr(Line3),.Outw(Line4),.DataInIP(Data1),
                                     .Inr(Line1),.Inw(Line2),.clk(clk),.reset(reset));

endmodule
module IPx2Sim
   #(  parameter DATA_WIDTH = 37,
       parameter FREQ = 4 
   
)
();


reg clk;
reg reset;

initial 
begin 
  $display("Start simulation at %t",$time); 
  clk=0;
  reset=0;
  #(10) reset =1'b1;
  #(10) reset =1'b0;
end
always
begin
  #1 clk=~clk;
end



wire [DATA_WIDTH-1:0] Data1, Data2;
wire Line1,Line2,Line3,Line4;
IP #(DATA_WIDTH, 4'b1111, FREQ) IP1 (.DataOutIP(Data1), .Outr(Line1),.Outw(Line2),.DataInIP(Data2),
                                     .Inr(Line3),.Inw(Line4),.clk(clk),.reset(reset));
IP #(DATA_WIDTH, 4'b0000, FREQ) IP2 (.DataOutIP(Data2), .Outr(Line3),.Outw(Line4),.DataInIP(Data1),
                                     .Inr(Line1),.Inw(Line2),.clk(clk),.reset(reset));

endmodule