data/full_repos/permissive/147086086/Lab4/hw/dec_7seg_demo_1/dec_7seg_demo_tb.v
 line:27: before: "i_rst_n"
1: b'%Warning-STMTDLY: data/full_repos/permissive/147086086/Lab4/hw/dec_7seg_demo_1/dec_7seg_demo_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    forever #(PERIOD/2) i_clk = ~i_clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147086086/Lab4/hw/dec_7seg_demo_1/dec_7seg_demo_tb.v:27: syntax error, unexpected \'@\'\n    @(negedge i_clk) i_rst_n = 1\'b1;\n    ^\n%Error: data/full_repos/permissive/147086086/Lab4/hw/dec_7seg_demo_1/dec_7seg_demo_tb.v:29: syntax error, unexpected \'@\'\n    repeat (DELAY_CYCLES) @(negedge i_clk);\n                          ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dec_7seg_demo_tb;

parameter PERIOD = 20;
parameter DELAY_CYCLES = 16*50_000_000;

reg         i_clk;
reg         i_rst_n;

wire [6:0]  o_seg;

dec_7seg_demo dec_7seg_demo_inst(.MAX10_CLK1_50 (i_clk), 
                                 .KEY ({i_rst_n, 1'b0}), 
                                 .HEX0 (o_seg)
                                );

initial begin
    i_clk = 0;
    forever #(PERIOD/2) i_clk = ~i_clk;
end

initial begin

    i_rst_n = 1'b0;

    @(negedge i_clk) i_rst_n = 1'b1;

    repeat (DELAY_CYCLES) @(negedge i_clk);

    $finish;

end

endmodule
module dec_7seg_demo_tb;


parameter PERIOD = 20;
parameter DELAY_CYCLES = 16*50_000_000;

reg         i_clk;
reg         i_rst_n;

wire [6:0]  o_seg;

dec_7seg_demo dec_7seg_demo_inst(.MAX10_CLK1_50 (i_clk), 
                                 .KEY ({i_rst_n, 1'b0}), 
                                 .HEX0 (o_seg)
                                );

initial begin
    i_clk = 0;
    forever #(PERIOD/2) i_clk = ~i_clk;
end

initial begin

    i_rst_n = 1'b0;

    @(negedge i_clk) i_rst_n = 1'b1;

    repeat (DELAY_CYCLES) @(negedge i_clk);

    $finish;

end

endmodule