data/full_repos/permissive/143278/ivltests/vhdl_struct_array.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_struct_array.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (in !== out[15:0]) begin\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_struct_array.v:6: Cannot find file containing module: \'foo_entity\'\n   foo_entity dut (.o_high1(out[15:12]), .o_low1(out[11:8]),\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/foo_entity\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/foo_entity.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/foo_entity.sv\n             foo_entity\n             foo_entity.v\n             foo_entity.sv\n             obj_dir/foo_entity\n             obj_dir/foo_entity.v\n             obj_dir/foo_entity.sv\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_struct_array.v:14: Operator NEQCASE expects 17 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                 : ... In instance main\n  #1 if (in !== out[15:0]) begin\n            ^~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [16:0] in;
   wire [15:0] out;

   foo_entity dut (.o_high1(out[15:12]), .o_low1(out[11:8]),
		   .o_high0(out[7:4]),   .o_low0(out[3:0]),

		   .i_high1(in[15:12]), .i_low1(in[11:8]),
		   .i_high0(in[7:4]),   .i_low0(in[3:0]));

   initial begin
      for (in = 0 ; in < 256 ; in = in+1) begin
	 #1 if (in !== out[15:0]) begin
	    $display("FAILED -- out=%h, in=%h", out, in);
	    $finish;
	 end
      end
      $display("PASSED");
   end

endmodule
module main;


   reg [16:0] in;
   wire [15:0] out;

   foo_entity dut (.o_high1(out[15:12]), .o_low1(out[11:8]),
		   .o_high0(out[7:4]),   .o_low0(out[3:0]),

		   .i_high1(in[15:12]), .i_low1(in[11:8]),
		   .i_high0(in[7:4]),   .i_low0(in[3:0]));

   initial begin
      for (in = 0 ; in < 256 ; in = in+1) begin
	 #1 if (in !== out[15:0]) begin
	    $display("FAILED -- out=%h, in=%h", out, in);
	    $finish;
	 end
      end
      $display("PASSED");
   end

endmodule