data/full_repos/permissive/148201731/rtl/decode/signal_extend.v
data/verilator_xmls/44297f3b-17f4-4e4a-bb7b-58287076b811.xml
module signal_extend
#(
   parameter OUT_DATA_WIDTH = 32,
   parameter IN_DATA_WIDTH = 16
)(
   input [IN_DATA_WIDTH-1:0] signal_in,
   output [OUT_DATA_WIDTH-1:0] signal_out
);


assign signal_out = {{(OUT_DATA_WIDTH-IN_DATA_WIDTH){signal_in[IN_DATA_WIDTH-1]}},signal_in};

endmodule
module signal_extend
#(
   parameter OUT_DATA_WIDTH = 32,
   parameter IN_DATA_WIDTH = 16
)(
   input [IN_DATA_WIDTH-1:0] signal_in,
   output [OUT_DATA_WIDTH-1:0] signal_out
);



assign signal_out = {{(OUT_DATA_WIDTH-IN_DATA_WIDTH){signal_in[IN_DATA_WIDTH-1]}},signal_in};

endmodule