data/full_repos/permissive/143278/ivltests/pr2136787.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2136787.v:18: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s SIGNED generates 4 bits.\n                                                                         : ... In instance signed_mux_bug\n    z = s ? $signed(a) : $signed(b);\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2136787.v:18: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s SIGNED generates 4 bits.\n                                                                         : ... In instance signed_mux_bug\n    z = s ? $signed(a) : $signed(b);\n          ^\n%Error: Exiting due to 2 warning(s)\n'
module signed_mux_bug();

reg       s;
reg [3:0] a, b;
reg [7:0] y, z;

initial begin

    s = 1'b1;
    a = 4'b1010;
    b = 4'b0000;


    y = s ? {{4{a[3]}}, a} : {{4{b[3]}}, b};



    z = s ? $signed(a) : $signed(b);


    $display("a = %b", a);
    $display("b = %b", b);
    $display("y = %b", y);
    $display("z = %b", z);


    $finish(0);
end

endmodule
module signed_mux_bug();


reg       s;
reg [3:0] a, b;
reg [7:0] y, z;

initial begin

    s = 1'b1;
    a = 4'b1010;
    b = 4'b0000;


    y = s ? {{4{a[3]}}, a} : {{4{b[3]}}, b};



    z = s ? $signed(a) : $signed(b);


    $display("a = %b", a);
    $display("b = %b", b);
    $display("y = %b", y);
    $display("z = %b", z);


    $finish(0);
end

endmodule