data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Multiplexers/mux256to1v.v
data/verilator_xmls/3e4eda9b-68d0-4909-98a6-4d1ef8b4a410.xml
module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    reg [7:0]index;
    assign     out[3:0] = in[4*sel+:4];
endmodule
module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );

    reg [7:0]index;
    assign     out[3:0] = in[4*sel+:4];
endmodule