data/full_repos/permissive/170402453/Average128.v
 line:38: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/170402453/Average128.v:53: Operator ADD expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                    : ... In instance Average8\n          Adder = Adder+Average[AvgTIndex];\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/170402453/Average128.v:58: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'Adder\' generates 32 bits.\n                                                                    : ... In instance Average8\n  AverageOUT_ = Adder;\n              ^\n%Error: Exiting due to 2 warning(s)\n'
module Average8(
    input CLK,
    input [7:0] SampleIN,
    output [7:0] AverageOUT
    );


	 reg [7:0] Average [127:0];
	 reg [7:0] AverageOUT_;
	 reg [6:0] AvgIndex;
	 reg [6:0] AvgTIndex;
	 integer Adder;


	 initial begin
		Adder = 0;
		AvgIndex = 0;
		repeat(128) begin
			Average[AvgIndex] = 0;
			AvgIndex = AvgIndex+1;
		end
		AvgIndex = 0;
	 end

	 assign AverageOUT = AverageOUT_;

	 always @ (posedge CLK) begin

		Average[AvgIndex] = SampleIN;
		AvgIndex = AvgIndex+1;
		
		repeat(128) begin
		        Adder = Adder+Average[AvgTIndex];
		        AvgTIndex = AvgTIndex+1;		
	        end
	        AvgTIndex = 0;
		Adder = Adder>>7;
		AverageOUT_ = Adder;
	 end

endmodule
module Average8(
    input CLK,
    input [7:0] SampleIN,
    output [7:0] AverageOUT
    );



	 reg [7:0] Average [127:0];
	 reg [7:0] AverageOUT_;
	 reg [6:0] AvgIndex;
	 reg [6:0] AvgTIndex;
	 integer Adder;


	 initial begin
		Adder = 0;
		AvgIndex = 0;
		repeat(128) begin
			Average[AvgIndex] = 0;
			AvgIndex = AvgIndex+1;
		end
		AvgIndex = 0;
	 end

	 assign AverageOUT = AverageOUT_;

	 always @ (posedge CLK) begin

		Average[AvgIndex] = SampleIN;
		AvgIndex = AvgIndex+1;
		
		repeat(128) begin
		        Adder = Adder+Average[AvgTIndex];
		        AvgTIndex = AvgTIndex+1;		
	        end
	        AvgTIndex = 0;
		Adder = Adder>>7;
		AverageOUT_ = Adder;
	 end

endmodule