data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register-tb.v
 line:47: before: "for"
1: b'%Error: data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register-tb.v:23: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("left-shift-register-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register-tb.v:24: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, left_shift_register_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register-tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #15\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Error: data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register-tb.v:48: syntax error, unexpected \'@\'\n        @ (posedge CLK) begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Error: data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register-tb.v:54: syntax error, unexpected \'#\'\n    #20\n    ^\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module left_shift_register_tb;


reg        CLK, RST;
reg        D;
wire [3:0] OUT;
integer    i;
integer    seed=1;


left_shift_register uut(
    .clk(CLK), .rst(RST),
    .d(D),
    .out(OUT)
);


initial begin
    $dumpfile("left-shift-register-tb.vcd");
    $dumpvars(0, left_shift_register_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    RST = 0;
    D = 0;


    #15
    RST = 1;
    #20
    RST = 0;
    #20


    for (i = 0; i < 30; i = i + 1) begin
        @ (posedge CLK) begin
            D <= $random(seed);
        end
    end
    

    #20

    $display("test complete");
    $finish;
end

endmodule
module left_shift_register_tb;



reg        CLK, RST;
reg        D;
wire [3:0] OUT;
integer    i;
integer    seed=1;


left_shift_register uut(
    .clk(CLK), .rst(RST),
    .d(D),
    .out(OUT)
);


initial begin
    $dumpfile("left-shift-register-tb.vcd");
    $dumpvars(0, left_shift_register_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    RST = 0;
    D = 0;


    #15
    RST = 1;
    #20
    RST = 0;
    #20


    for (i = 0; i < 30; i = i + 1) begin
        @ (posedge CLK) begin
            D <= $random(seed);
        end
    end
    

    #20

    $display("test complete");
    $finish;
end

endmodule