data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:6: Cannot find include file: ../../../basic-code/sequential-logic/d-flip-flop/d-flip-flop.v\n`include "../../../basic-code/sequential-logic/d-flip-flop/d-flip-flop.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register,data/full_repos/permissive/174155074/../../../basic-code/sequential-logic/d-flip-flop/d-flip-flop.v\n             data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register,data/full_repos/permissive/174155074/../../../basic-code/sequential-logic/d-flip-flop/d-flip-flop.v.v\n             data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register,data/full_repos/permissive/174155074/../../../basic-code/sequential-logic/d-flip-flop/d-flip-flop.v.sv\n             ../../../basic-code/sequential-logic/d-flip-flop/d-flip-flop.v\n             ../../../basic-code/sequential-logic/d-flip-flop/d-flip-flop.v.v\n             ../../../basic-code/sequential-logic/d-flip-flop/d-flip-flop.v.sv\n             obj_dir/../../../basic-code/sequential-logic/d-flip-flop/d-flip-flop.v\n             obj_dir/../../../basic-code/sequential-logic/d-flip-flop/d-flip-flop.v.v\n             obj_dir/../../../basic-code/sequential-logic/d-flip-flop/d-flip-flop.v.sv\n%Error: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:28: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("simple-8-bit-register-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:29: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, simple_8_bit_register_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #15 CLR_BAR = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #20 CLR_BAR = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #20; DATA_IN = 8\'hF0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #40\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #20 LD_BAR = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #20 LD_BAR = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #20 CLR_BAR = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #40\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #20 CLR_BAR = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register-tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #40\n    ^\n%Error: Exiting due to 3 error(s), 11 warning(s)\n'
module simple_8_bit_register_tb;


reg  [7:0] DATA_IN;
reg        CLK;
reg        LD_BAR;
reg        CLR_BAR;
wire [7:0] DATA_OUT;


simple_8_bit_register uut(
    .data_in (DATA_IN),
    .clk(CLK),
    .ld_bar(LD_BAR),
    .clr_bar(CLR_BAR),
    .data_out(DATA_OUT)
);


initial begin
    $dumpfile("simple-8-bit-register-tb.vcd");
    $dumpvars(0, simple_8_bit_register_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    LD_BAR = 1;
    CLR_BAR = 1;
    DATA_IN = 8'h00;


    #15 CLR_BAR = 0;
    #20 CLR_BAR = 1;
    #40


    #20; DATA_IN = 8'hF0;
    #20 LD_BAR = 0;
    #20 LD_BAR = 1;
    #40


    #20 CLR_BAR = 0;
    #20 CLR_BAR = 1;
    #40

    $display("test complete");
    $finish;
end

endmodule
module simple_8_bit_register_tb;



reg  [7:0] DATA_IN;
reg        CLK;
reg        LD_BAR;
reg        CLR_BAR;
wire [7:0] DATA_OUT;


simple_8_bit_register uut(
    .data_in (DATA_IN),
    .clk(CLK),
    .ld_bar(LD_BAR),
    .clr_bar(CLR_BAR),
    .data_out(DATA_OUT)
);


initial begin
    $dumpfile("simple-8-bit-register-tb.vcd");
    $dumpvars(0, simple_8_bit_register_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    LD_BAR = 1;
    CLR_BAR = 1;
    DATA_IN = 8'h00;


    #15 CLR_BAR = 0;
    #20 CLR_BAR = 1;
    #40


    #20; DATA_IN = 8'hF0;
    #20 LD_BAR = 0;
    #20 LD_BAR = 1;
    #40


    #20 CLR_BAR = 0;
    #20 CLR_BAR = 1;
    #40

    $display("test complete");
    $finish;
end

endmodule