data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:106: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'dsi_byte_reverse\'\nmodule dsi_byte_reverse\n       ^~~~~~~~~~~~~~~~\n                                                                                         : ... Top module \'dsi_packer\'\nmodule dsi_packer\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:100: Operator SHIFTL expects 80 bits on the LHS, but LHS\'s VARREF \'d_i\' generates 24 bits.\n                                                                                      : ... In instance dsi_packer.U_Shifter\n        assign gen_array[i] = d_i << (i * 8);\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:103: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                      : ... In instance dsi_packer.U_Shifter\n   assign shifted_o = gen_array[shift_i];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:75: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s ARRAYSEL generates 24 bits.\n                                                                                     : ... In instance dsi_packer.U_RevIn\n   assign q_o = (size_i) <= g_num_bytes ? swapped[size_i] : \'hx;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:75: Operator ASSIGNW expects 24 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                     : ... In instance dsi_packer.U_RevIn\n   assign q_o = (size_i) <= g_num_bytes ? swapped[size_i] : \'hx;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:160: Operator GTE expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n   assign shift_out = (count >= q_size_i && q_req_i);\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:161: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n   assign in_shift = (shift_out ? count - q_size_i : count);\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:164: Input port connection \'size_i\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'d_size_i\' generates 4 bits.\n                                                                                      : ... In instance dsi_packer\n   dsi_byte_swapper #(g_input_bytes) U_RevIn ( d_i, d_size_i, d_in );\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:182: Input port connection \'shift_i\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'in_shift\' generates 5 bits.\n                                                                                      : ... In instance dsi_packer\n      .shift_i(in_shift),\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:183: Output port connection \'shifted_o\' expects 80 bits on the pin connection, but pin connection\'s VARREF \'in_shifted\' generates 64 bits.\n                                                                                      : ... In instance dsi_packer\n      .shifted_o(in_shifted)\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:198: Operator GT expects 32 bits on the LHS, but LHS\'s VARREF \'count\' generates 5 bits.\n                                                                                      : ... In instance dsi_packer\n            q_valid_o[i] <= count > i;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:221: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n             count <= count - q_size_i + d_size_i;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:227: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n             count <= count - q_size_i;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:238: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n       avail_next <= avail + q_size_i - d_size_i;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:242: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n       avail_next <= avail + q_size_i;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:249: Operator SUB expects 32 or 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n   assign d_req_int = (avail_next >= g_input_bytes) || (shift_out && avail_next >= (g_input_bytes - q_size_i));\n                                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:251: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'count\' generates 5 bits.\n                                                                                      : ... In instance dsi_packer\n   assign d_empty_o = !count;\n                      ^\n%Error: Exiting due to 17 warning(s)\n'
module dsi_packer
  (
   clk_i,
   rst_n_i,

   
  
   d_i,
   d_size_i,
   d_req_o,
   d_valid_i,
   d_empty_o,

   q_size_i,
   q_o,
   q_req_i,
   q_flush_i,
   q_valid_o  
   );

   
   parameter g_input_bytes = 3;
   parameter g_output_bytes = 3;

   
   localparam c_shiftreg_bytes = 2 * (g_input_bytes > g_output_bytes ? g_input_bytes : g_output_bytes) + 2;
   
   
   input clk_i, rst_n_i;
   input [g_input_bytes * 8 - 1 : 0] d_i;
   input [3 : 0]                     d_size_i;
   output                            d_req_o;
   input                             d_valid_i, q_flush_i;

   output reg [g_output_bytes * 8 -1 :0] q_o;
   output reg [g_output_bytes-1:0]   q_valid_o;
   output                            d_empty_o;
   
   input                             q_req_i;

   input [2:0]                       q_size_i;
   
   wire [g_input_bytes * 8 - 1 : 0]  d_in;
   reg [g_output_bytes * 8 - 1 : 0]  q_out;
   
   reg [4:0]                         count, avail, avail_next;
   reg [c_shiftreg_bytes * 8 -1 :0]  shreg, shreg_shifted;
   wire [c_shiftreg_bytes * 8 -1 :0] in_shifted;
   wire                              shift_out;
   wire [4:0]                        in_shift;

   wire                              d_req_int;
   
   
   assign shift_out = (count >= q_size_i && q_req_i);
   assign in_shift = (shift_out ? count - q_size_i : count);
   

   dsi_byte_swapper #(g_input_bytes) U_RevIn ( d_i, d_size_i, d_in );


   wire [8*g_output_bytes-1:0]         q_out_reversed[0:7];
   
   
   
   always@* 
     q_o <= q_out;
  
   dsi_byte_shifter
     #(
       .g_data_bytes(g_input_bytes),
       .g_max_shift(c_shiftreg_bytes - 1)
       ) 
   U_Shifter 
     (
      .d_i(d_in),
      .shift_i(in_shift),
      .shifted_o(in_shifted)
      );
   
   
   always@(posedge clk_i)
     if(!rst_n_i) begin
        q_valid_o <= 0;
        q_out <= 0;
     end else if(shift_out || q_flush_i)
       begin : drive_output
          integer i;
          
          q_out <= shreg[g_output_bytes * 8 - 1 : 0];

          for(i=0;i<g_output_bytes;i=i+1)
            q_valid_o[i] <= count > i;
       end else
         q_valid_o <= 0;
   

   always@*
     begin
        case (q_size_i)
          3: shreg_shifted <= shreg >> 24;
          default: shreg_shifted <= shreg >> 32;
        endcase
     end
   
   always@(posedge clk_i)
     if (!rst_n_i)
       begin
          count <= 0;
          avail <= c_shiftreg_bytes;
          shreg <= 0;
          
       end else begin
          if(d_valid_i && shift_out) begin
             shreg <= shreg_shifted | in_shifted;
             count <= count - q_size_i + d_size_i;
          end else if(d_valid_i) begin
             shreg <= shreg | in_shifted;
             count <= count + d_size_i;
          end else if(shift_out) begin
             shreg <= shreg_shifted;
             count <= count - q_size_i;
          end else if (q_flush_i) begin
             count <= 0;
             shreg <= 0;
          end
          avail <= avail_next;
       end

   
   always@*
     if(d_valid_i && shift_out) 
       avail_next <= avail + q_size_i - d_size_i;
     else if(d_valid_i) 
       avail_next <= avail - d_size_i;
     else if(shift_out) 
       avail_next <= avail + q_size_i;
     else if(q_flush_i)
       avail_next <= c_shiftreg_bytes;
     else
       avail_next <= avail;
   
   
   assign d_req_int = (avail_next >= g_input_bytes) || (shift_out && avail_next >= (g_input_bytes - q_size_i));
   assign d_req_o = d_req_int;
   assign d_empty_o = !count;
   
   
endmodule
module dsi_packer
  (
   clk_i,
   rst_n_i,

   
  
   d_i,
   d_size_i,
   d_req_o,
   d_valid_i,
   d_empty_o,

   q_size_i,
   q_o,
   q_req_i,
   q_flush_i,
   q_valid_o  
   );


   
   parameter g_input_bytes = 3;
   parameter g_output_bytes = 3;

   
   localparam c_shiftreg_bytes = 2 * (g_input_bytes > g_output_bytes ? g_input_bytes : g_output_bytes) + 2;
   
   
   input clk_i, rst_n_i;
   input [g_input_bytes * 8 - 1 : 0] d_i;
   input [3 : 0]                     d_size_i;
   output                            d_req_o;
   input                             d_valid_i, q_flush_i;

   output reg [g_output_bytes * 8 -1 :0] q_o;
   output reg [g_output_bytes-1:0]   q_valid_o;
   output                            d_empty_o;
   
   input                             q_req_i;

   input [2:0]                       q_size_i;
   
   wire [g_input_bytes * 8 - 1 : 0]  d_in;
   reg [g_output_bytes * 8 - 1 : 0]  q_out;
   
   reg [4:0]                         count, avail, avail_next;
   reg [c_shiftreg_bytes * 8 -1 :0]  shreg, shreg_shifted;
   wire [c_shiftreg_bytes * 8 -1 :0] in_shifted;
   wire                              shift_out;
   wire [4:0]                        in_shift;

   wire                              d_req_int;
   
   
   assign shift_out = (count >= q_size_i && q_req_i);
   assign in_shift = (shift_out ? count - q_size_i : count);
   

   dsi_byte_swapper #(g_input_bytes) U_RevIn ( d_i, d_size_i, d_in );


   wire [8*g_output_bytes-1:0]         q_out_reversed[0:7];
   
   
   
   always@* 
     q_o <= q_out;
  
   dsi_byte_shifter
     #(
       .g_data_bytes(g_input_bytes),
       .g_max_shift(c_shiftreg_bytes - 1)
       ) 
   U_Shifter 
     (
      .d_i(d_in),
      .shift_i(in_shift),
      .shifted_o(in_shifted)
      );
   
   
   always@(posedge clk_i)
     if(!rst_n_i) begin
        q_valid_o <= 0;
        q_out <= 0;
     end else if(shift_out || q_flush_i)
       begin : drive_output
          integer i;
          
          q_out <= shreg[g_output_bytes * 8 - 1 : 0];

          for(i=0;i<g_output_bytes;i=i+1)
            q_valid_o[i] <= count > i;
       end else
         q_valid_o <= 0;
   

   always@*
     begin
        case (q_size_i)
          3: shreg_shifted <= shreg >> 24;
          default: shreg_shifted <= shreg >> 32;
        endcase
     end
   
   always@(posedge clk_i)
     if (!rst_n_i)
       begin
          count <= 0;
          avail <= c_shiftreg_bytes;
          shreg <= 0;
          
       end else begin
          if(d_valid_i && shift_out) begin
             shreg <= shreg_shifted | in_shifted;
             count <= count - q_size_i + d_size_i;
          end else if(d_valid_i) begin
             shreg <= shreg | in_shifted;
             count <= count + d_size_i;
          end else if(shift_out) begin
             shreg <= shreg_shifted;
             count <= count - q_size_i;
          end else if (q_flush_i) begin
             count <= 0;
             shreg <= 0;
          end
          avail <= avail_next;
       end

   
   always@*
     if(d_valid_i && shift_out) 
       avail_next <= avail + q_size_i - d_size_i;
     else if(d_valid_i) 
       avail_next <= avail - d_size_i;
     else if(shift_out) 
       avail_next <= avail + q_size_i;
     else if(q_flush_i)
       avail_next <= c_shiftreg_bytes;
     else
       avail_next <= avail;
   
   
   assign d_req_int = (avail_next >= g_input_bytes) || (shift_out && avail_next >= (g_input_bytes - q_size_i));
   assign d_req_o = d_req_int;
   assign d_empty_o = !count;
   
   
endmodule