data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/单周期CPU代码/ROM.v
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data/verilator_xmls/bdd563ab-d486-4986-b4c9-505047e7124d.xml
module ROM ( 
	rd, 
	addr, 
	dataOut
);

	input rd;
	input [31:0] addr;
	output reg [31:0] dataOut;
	reg [7:0] rom [127:0];

	initial begin
		$readmemb ("E:/Xlinx/VivadoProject/ROM/rom_data.txt", rom);
	end
	always @( rd or addr ) begin
		if (rd==0) begin
			dataOut[31:24] = rom[addr];
			dataOut[23:16] = rom[addr+1];
			dataOut[15:8] = rom[addr+2];
			dataOut[7:0] = rom[addr+3];
		end
	end
endmodule
module ROM ( 
	rd, 
	addr, 
	dataOut
);


	input rd;
	input [31:0] addr;
	output reg [31:0] dataOut;
	reg [7:0] rom [127:0];

	initial begin
		$readmemb ("E:/Xlinx/VivadoProject/ROM/rom_data.txt", rom);
	end
	always @( rd or addr ) begin
		if (rd==0) begin
			dataOut[31:24] = rom[addr];
			dataOut[23:16] = rom[addr+1];
			dataOut[15:8] = rom[addr+2];
			dataOut[7:0] = rom[addr+3];
		end
	end
endmodule