data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/func_constant_signed.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/func_constant_signed.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #5 v1=5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/func_constant_signed.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #5 v1=-5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/func_constant_signed.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module func_constant_signed;

parameter RAM_DEPTH = 256;
reg [clogb2(RAM_DEPTH)-1:0] addr_bus;


function integer clogb2(input integer depth);
begin
    for(clogb2=0;depth>1;clogb2=clogb2+1)
        depth = depth >> 1;
end
endfunction



function signed [63:0] compute_signed(input [63:0] vector);
    compute_signed = vector;
endfunction

reg [63:0] v1;
always @(v1)
begin
    if(compute_signed(v1) < -3)
        $display($time," compute_signed(vector) < -3");
    else
        $display($time," compute_signed(vector) >= -3");
end

initial
begin
    #5 v1=5;
    #5 v1=-5;
    
    #5 $finish;
end

endmodule
module func_constant_signed;


parameter RAM_DEPTH = 256;
reg [clogb2(RAM_DEPTH)-1:0] addr_bus;


function integer clogb2(input integer depth);
begin
    for(clogb2=0;depth>1;clogb2=clogb2+1)
        depth = depth >> 1;
end
endfunction



function signed [63:0] compute_signed(input [63:0] vector);
    compute_signed = vector;
endfunction

reg [63:0] v1;
always @(v1)
begin
    if(compute_signed(v1) < -3)
        $display($time," compute_signed(vector) < -3");
    else
        $display($time," compute_signed(vector) >= -3");
end

initial
begin
    #5 v1=5;
    #5 v1=-5;
    
    #5 $finish;
end

endmodule