data/full_repos/permissive/115141190/LCD_controller.v
1: b"%Error: data/full_repos/permissive/115141190/LCD_controller.v:51: Cannot find file containing module: 'Initialize_FSM'\nInitialize_FSM Initialize_FSM (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/Initialize_FSM\n             data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/Initialize_FSM.v\n             data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/Initialize_FSM.sv\n             Initialize_FSM\n             Initialize_FSM.v\n             Initialize_FSM.sv\n             obj_dir/Initialize_FSM\n             obj_dir/Initialize_FSM.v\n             obj_dir/Initialize_FSM.sv\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:60: Cannot find file containing module: 'Init_counter_generator'\nInit_counter_generator Init_counter_generator (\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:69: Cannot find file containing module: 'Configure_FSM'\nConfigure_FSM Configure_FSM (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:82: Cannot find file containing module: 'ClockCounterGenerator_w1_64ms'\nClockCounterGenerator_w1_64ms ClockCounterGenerator_w1_64ms (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:89: Cannot find file containing module: 'ClockCounterGenerator_w1s'\nClockCounterGenerator_w1s ClockCounterGenerator_w1s(\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:99: Cannot find file containing module: 'Instruction_FSM'\nInstruction_FSM Instruction_FSM (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115141190/LCD_controller.v:113: Cannot find file containing module: 'Instruction_ClockCounterGenerator'\nInstruction_ClockCounterGenerator Instruction_ClockCounterGenerator (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module LCD_controller (clk, reset, LCD_E, SF_D11, SF_D10, SF_D9, SF_D8, LCD_RS, LCD_RW);
input wire clk, reset;
output reg LCD_E;
output wire LCD_RS, LCD_RW;
output reg SF_D11, SF_D10, SF_D9, SF_D8;

wire [11:0]init_sfd;
wire [11:0]instr_sfd;
wire init_lcd_e, instr_lcd_e;
wire enable, done, next_instruction, enable_w1s, enable_w1_64ms, enable_instr_cnt;
wire [19:0]init_clk_cnt;
wire [11:0]instruction_clk_cnt;
wire [25:0]cnt_1s;
wire [16:0]cnt_1_64ms;
wire [9:0]db;






always @ (posedge clk or posedge reset) begin
    if(reset) begin
        SF_D11  <= 1'b0;
        SF_D10  <= 1'b0;
        SF_D9   <= 1'b0;
        SF_D8   <= 1'b0;
        LCD_E   <= 1'b1;
    end
    else begin
        if (enable == 1'b1) begin
            SF_D11  <= instr_sfd[11];
            SF_D10  <= instr_sfd[10];
            SF_D9   <= instr_sfd[9];
            SF_D8   <= instr_sfd[8];
            LCD_E <= instr_lcd_e;
        end
        else begin
            SF_D11  <= init_sfd[11];
            SF_D10  <= init_sfd[10];
            SF_D9   <= init_sfd[9];
            SF_D8   <= init_sfd[8];
            LCD_E <= init_lcd_e;
        end
    end
end




Initialize_FSM Initialize_FSM (
    .clk      (clk),
    .reset    (reset),
    .clk_cnt  (init_clk_cnt),
    .enable   (enable),
    .SF_D     (init_sfd),
    .LCD_E    (init_lcd_e)
);

Init_counter_generator Init_counter_generator (
    .clk      (clk),
    .reset    (reset),
    .clk_cnt  (init_clk_cnt)
);




Configure_FSM Configure_FSM (
    .clk              (clk),
    .reset            (reset),
    .enable           (enable),
    .done             (done),
    .cnt_1s           (cnt_1s),
    .cnt_1_64ms       (cnt_1_64ms),
    .next_instruction (next_instruction),
    .db               (db),
    .enable_w1s       (enable_w1s),
    .enable_w1_64ms   (enable_w1_64ms)
);

ClockCounterGenerator_w1_64ms ClockCounterGenerator_w1_64ms (
    .clk      (clk),
    .reset    (reset),
    .enable   (enable_w1_64ms),
    .clk_cnt  (cnt_1_64ms)
);

ClockCounterGenerator_w1s ClockCounterGenerator_w1s(
    .clk      (clk),
    .reset    (reset),
    .enable   (enable_w1s),
    .clk_cnt  (cnt_1s)
);




Instruction_FSM Instruction_FSM (
    .clk              (clk),
    .reset            (reset),
    .next_instruction (next_instruction),
    .clk_cnt          (instruction_clk_cnt),
    .db               (db),
    .LCD_RS           (LCD_RS),
    .SF_D             (instr_sfd),
    .LCD_RW           (LCD_RW),
    .LCD_E            (instr_lcd_e),
    .done             (done),
    .enable           (enable_instr_cnt)
);

Instruction_ClockCounterGenerator Instruction_ClockCounterGenerator (
    .clk        (clk),
    .reset      (reset),
    .clk_cnt    (instruction_clk_cnt),
    .enable     (enable_instr_cnt)
);


endmodule
module LCD_controller (clk, reset, LCD_E, SF_D11, SF_D10, SF_D9, SF_D8, LCD_RS, LCD_RW);

input wire clk, reset;
output reg LCD_E;
output wire LCD_RS, LCD_RW;
output reg SF_D11, SF_D10, SF_D9, SF_D8;

wire [11:0]init_sfd;
wire [11:0]instr_sfd;
wire init_lcd_e, instr_lcd_e;
wire enable, done, next_instruction, enable_w1s, enable_w1_64ms, enable_instr_cnt;
wire [19:0]init_clk_cnt;
wire [11:0]instruction_clk_cnt;
wire [25:0]cnt_1s;
wire [16:0]cnt_1_64ms;
wire [9:0]db;






always @ (posedge clk or posedge reset) begin
    if(reset) begin
        SF_D11  <= 1'b0;
        SF_D10  <= 1'b0;
        SF_D9   <= 1'b0;
        SF_D8   <= 1'b0;
        LCD_E   <= 1'b1;
    end
    else begin
        if (enable == 1'b1) begin
            SF_D11  <= instr_sfd[11];
            SF_D10  <= instr_sfd[10];
            SF_D9   <= instr_sfd[9];
            SF_D8   <= instr_sfd[8];
            LCD_E <= instr_lcd_e;
        end
        else begin
            SF_D11  <= init_sfd[11];
            SF_D10  <= init_sfd[10];
            SF_D9   <= init_sfd[9];
            SF_D8   <= init_sfd[8];
            LCD_E <= init_lcd_e;
        end
    end
end




Initialize_FSM Initialize_FSM (
    .clk      (clk),
    .reset    (reset),
    .clk_cnt  (init_clk_cnt),
    .enable   (enable),
    .SF_D     (init_sfd),
    .LCD_E    (init_lcd_e)
);

Init_counter_generator Init_counter_generator (
    .clk      (clk),
    .reset    (reset),
    .clk_cnt  (init_clk_cnt)
);




Configure_FSM Configure_FSM (
    .clk              (clk),
    .reset            (reset),
    .enable           (enable),
    .done             (done),
    .cnt_1s           (cnt_1s),
    .cnt_1_64ms       (cnt_1_64ms),
    .next_instruction (next_instruction),
    .db               (db),
    .enable_w1s       (enable_w1s),
    .enable_w1_64ms   (enable_w1_64ms)
);

ClockCounterGenerator_w1_64ms ClockCounterGenerator_w1_64ms (
    .clk      (clk),
    .reset    (reset),
    .enable   (enable_w1_64ms),
    .clk_cnt  (cnt_1_64ms)
);

ClockCounterGenerator_w1s ClockCounterGenerator_w1s(
    .clk      (clk),
    .reset    (reset),
    .enable   (enable_w1s),
    .clk_cnt  (cnt_1s)
);




Instruction_FSM Instruction_FSM (
    .clk              (clk),
    .reset            (reset),
    .next_instruction (next_instruction),
    .clk_cnt          (instruction_clk_cnt),
    .db               (db),
    .LCD_RS           (LCD_RS),
    .SF_D             (instr_sfd),
    .LCD_RW           (LCD_RW),
    .LCD_E            (instr_lcd_e),
    .done             (done),
    .enable           (enable_instr_cnt)
);

Instruction_ClockCounterGenerator Instruction_ClockCounterGenerator (
    .clk        (clk),
    .reset      (reset),
    .clk_cnt    (instruction_clk_cnt),
    .enable     (enable_instr_cnt)
);


endmodule