data/full_repos/permissive/128100618/SV/FPU.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/128100618/SV/FPU.v:388: Cell has missing pin: \'oSum\'\n FPadd init_newton(reduced_input_x_2, T1, x0) ;\n       ^~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/128100618/SV/FPU.v:392: Cell has missing pin: \'oSum\'\n FPadd newton12(T2, input_x_x0, two_minus_input_x_x0);\n       ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/128100618/SV/FPU.v:397: Cell has missing pin: \'oSum\'\n FPadd newton22(T2, input_x_x1, two_minus_input_x_x1);\n       ^~~~~~~~\n%Warning-MULTITOP: data/full_repos/permissive/128100618/SV/FPU.v:311: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                    : ... Top module \'FPinv\'\nmodule FPinv (\n       ^~~~~\n                                                                    : ... Top module \'fp2int\'\nmodule fp2int(\n       ^~~~~~\n                                                                    : ... Top module \'FPinv_prof\'\nmodule FPinv_prof (f1, fout);\n       ^~~~~~~~~~\n                                                                    : ... Top module \'fpadd\'\nmodule fpadd (fout, f1, f2);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:209: Operator GT expects 9 bits on the LHS, but LHS\'s VARREF \'exp_diff_A\' generates 8 bits.\n                                                                 : ... In instance FPinv_prof.newton22\n                         (exp_diff_A > 9\'d35) ? 47\'b0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:212: Operator GT expects 9 bits on the LHS, but LHS\'s VARREF \'exp_diff_B\' generates 8 bits.\n                                                                 : ... In instance FPinv_prof.newton22\n                         (exp_diff_B > 9\'d35) ? 47\'b0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:122: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 9 bits.\n                                                                 : ... In instance FPinv_prof.newton23\n    assign oProd_e = pre_prod_frac[45] ? (pre_prod_exp-9\'d126) : (pre_prod_exp - 9\'d127);\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:388: Input port connection \'iCLK\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'reduced_input_x_2\' generates 32 bits.\n                                                                 : ... In instance FPinv_prof\n FPadd init_newton(reduced_input_x_2, T1, x0) ;\n                   ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:392: Input port connection \'iCLK\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'T2\' generates 32 bits.\n                                                                 : ... In instance FPinv_prof\n FPadd newton12(T2, input_x_x0, two_minus_input_x_x0);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:397: Input port connection \'iCLK\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'T2\' generates 32 bits.\n                                                                 : ... In instance FPinv_prof\n FPadd newton22(T2, input_x_x1, two_minus_input_x_x1);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:330: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'m_in\' generates 24 bits.\n                                                                 : ... In instance fp2int\n assign abs_int = (e_in>8\'h80)? (m_in >> (8\'d150 - e_in)) : 32\'d0;\n                                      ^~\n%Error: Exiting due to 11 warning(s)\n'
module FPinv (
	
	input iCLK,
	input [31:0] in,
	output [31:0] out

);

	wire [31:0] Out_invsqrt;

	FPinvsqrt fpinvsqrt (

		.iCLK(iCLK),
		.iA(in),
		.oInvsqrt(Out_invsqrt)
		
	);

	FPmult fpmult (

		.iA(Out_invsqrt),
		.iB(Out_invsqrt),
		.oProd(out)
		
	);

endmodule
module FPinv (
	
	input iCLK,
	input [31:0] in,
	output [31:0] out

);


	wire [31:0] Out_invsqrt;

	FPinvsqrt fpinvsqrt (

		.iCLK(iCLK),
		.iA(in),
		.oInvsqrt(Out_invsqrt)
		
	);

	FPmult fpmult (

		.iA(Out_invsqrt),
		.iB(Out_invsqrt),
		.oProd(out)
		
	);

endmodule