data/full_repos/permissive/138208056/Dual_CSI-2_Camera_to_HDMI_Bridge_Demo/Crosslink_DualCSI2toRaw10/source/rx_global_ctrl_bb.v
data/verilator_xmls/a3a2ee2c-e698-406f-943c-d2e4f4353c4d.xml
module rx_global_ctrl #(
    parameter NUM_RX_LANE = 4,
    parameter RX_GEAR = 8,
    parameter RX_FIFO = "OFF",
    parameter RX_CLK_MODE = "HS_ONLY"
)
(
    input  wire	              reset_n_i,
    input  wire	              reset_lp_n_i,
    input  wire	              reset_byte_fr_n_i,
    input  wire               clk_lp_ctrl_i,
    input  wire	              clk_byte_hs_i,
    input  wire	              clk_byte_i,
    input  wire	              clk_byte_fr_i,
    input  wire	              pll_lock_i,

    input wire [RX_GEAR-1:0]  bd0_i,
    input wire [RX_GEAR-1:0]  bd1_i,
    input wire [RX_GEAR-1:0]  bd2_i,
    input wire [RX_GEAR-1:0]  bd3_i,
    input wire                lp_clk_p_i,
    input wire                lp_clk_n_i,
    input wire                lp_d0_p_i,
    input wire                lp_d0_n_i,
    input wire                lp_d1_p_i,
    input wire                lp_d1_n_i,
    input wire                lp_d2_p_i,
    input wire                lp_d2_n_i,
    input wire                lp_d3_p_i,
    input wire                lp_d3_n_i,
    input wire                hs_sync_i,
    output wire [RX_GEAR-1:0] bd0_o,
    output wire [RX_GEAR-1:0] bd1_o,
    output wire [RX_GEAR-1:0] bd2_o,
    output wire [RX_GEAR-1:0] bd3_o,
    output wire               term_clk_en_o,
    output wire               term_d0_en_o,
    output wire               hs_d0_en_o,
    output wire               term_d1_en_o,
    output wire               hs_d1_en_o,
    output wire               term_d2_en_o,
    output wire               hs_d2_en_o,
    output wire               term_d3_en_o,
    output wire               hs_d3_en_o,
    output wire               hs_sync_o,
    output wire [1:0]         lp_hs_state_clk_o,
    output wire [1:0]         lp_hs_state_d_o
);



endmodule
module rx_global_ctrl #(
    parameter NUM_RX_LANE = 4,
    parameter RX_GEAR = 8,
    parameter RX_FIFO = "OFF",
    parameter RX_CLK_MODE = "HS_ONLY"
)
(
    input  wire	              reset_n_i,
    input  wire	              reset_lp_n_i,
    input  wire	              reset_byte_fr_n_i,
    input  wire               clk_lp_ctrl_i,
    input  wire	              clk_byte_hs_i,
    input  wire	              clk_byte_i,
    input  wire	              clk_byte_fr_i,
    input  wire	              pll_lock_i,

    input wire [RX_GEAR-1:0]  bd0_i,
    input wire [RX_GEAR-1:0]  bd1_i,
    input wire [RX_GEAR-1:0]  bd2_i,
    input wire [RX_GEAR-1:0]  bd3_i,
    input wire                lp_clk_p_i,
    input wire                lp_clk_n_i,
    input wire                lp_d0_p_i,
    input wire                lp_d0_n_i,
    input wire                lp_d1_p_i,
    input wire                lp_d1_n_i,
    input wire                lp_d2_p_i,
    input wire                lp_d2_n_i,
    input wire                lp_d3_p_i,
    input wire                lp_d3_n_i,
    input wire                hs_sync_i,
    output wire [RX_GEAR-1:0] bd0_o,
    output wire [RX_GEAR-1:0] bd1_o,
    output wire [RX_GEAR-1:0] bd2_o,
    output wire [RX_GEAR-1:0] bd3_o,
    output wire               term_clk_en_o,
    output wire               term_d0_en_o,
    output wire               hs_d0_en_o,
    output wire               term_d1_en_o,
    output wire               hs_d1_en_o,
    output wire               term_d2_en_o,
    output wire               hs_d2_en_o,
    output wire               term_d3_en_o,
    output wire               hs_d3_en_o,
    output wire               hs_sync_o,
    output wire [1:0]         lp_hs_state_clk_o,
    output wire [1:0]         lp_hs_state_d_o
);




endmodule