data/full_repos/permissive/177233467/cpu.v
 line:58: before: "."
1: b'%Error: data/full_repos/permissive/177233467/cpu.v:46: Cannot find file containing module: \'reg_file\'\nreg_file regf(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/177233467,data/full_repos/permissive/177233467/reg_file\n             data/full_repos/permissive/177233467,data/full_repos/permissive/177233467/reg_file.v\n             data/full_repos/permissive/177233467,data/full_repos/permissive/177233467/reg_file.sv\n             reg_file\n             reg_file.v\n             reg_file.sv\n             obj_dir/reg_file\n             obj_dir/reg_file.v\n             obj_dir/reg_file.sv\n%Error: data/full_repos/permissive/177233467/cpu.v:85: Cannot find file containing module: \'memory\'\nmemory mem(\n^~~~~~\n%Error: data/full_repos/permissive/177233467/cpu.v:104: Cannot find file containing module: \'instruction_fetch\'\ninstruction_fetch ifetch(\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177233467/cpu.v:129: Cannot find file containing module: \'instruction_decode\'\ninstruction_decode idecode(\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177233467/cpu.v:198: Cannot find file containing module: \'alu\'\nalu alu_m(\n^~~\n%Error: data/full_repos/permissive/177233467/cpu.v:271: Cannot find file containing module: \'hazard_detect\'\nhazard_detect res(\n^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/177233467/cpu.v:315: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                              : ... In instance cpu\nassign debug_port5 = {vf_wb, vf_mem,  VF & (~mf_ex[6] | mf_ex[7]) & (~mf_mem[4])};      \n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/177233467/cpu.v:316: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'fwd_flags\' generates 6 bits.\n                                                              : ... In instance cpu\nassign debug_port6 = fwd_flags;  \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/177233467/cpu.v:317: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s CONST \'8\'hfc\' generates 8 bits.\n                                                              : ... In instance cpu\nassign debug_port7 = rf_we ? rf_wd : 8\'hfc;    \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/177233467/cpu.v:317: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                              : ... In instance cpu\nassign debug_port7 = rf_we ? rf_wd : 8\'hfc;    \n                   ^\n%Error: Exiting due to 6 error(s), 4 warning(s)\n'
module cpu(
  input wire clk,
  input wire resetn,
  output wire led,
  output wire [7:0] debug_port1,
  output wire [7:0] debug_port2,
  output wire [7:0] debug_port3,
  output wire [7:0] debug_port4,
  output wire [7:0] debug_port5,
  output wire [7:0] debug_port6,
  output wire [7:0] debug_port7
  );


 


localparam nreg = 16;
localparam reg_width = 32;
localparam reg_addr_width = $clog2(nreg);

  reg [reg_width - 1:0] rf_d1, rf_d2;
  reg [reg_addr_width - 1:0] rf_rs1, rf_rs2;
  reg [reg_addr_width - 1:0] rf_ws;
  reg [reg_width - 1:0] rf_wd;
  reg rf_we;

always @(*) begin
  rf_rs1 = rf_Rn;
  rf_rs2 = rf_Rm;

  rf_ws = rf_wb[11:8];
  rf_wd = mf_wb[2] ? data_mem_rd : alu_wb;
  rf_we = vf_wb & mf_wb[0];
end






reg_file regf(
  clk, resetn,


  rf_rs1, rf_rs2,
  rf_wd, rf_ws, rf_we,

  pc,


  rf_d1, rf_d2
);
defparam regf.nreg = nreg;
defparam regf.reg_width = reg_width;
defparam regf.reg_addr_width = reg_addr_width;


localparam data_width = 32;
localparam data_width_l2b = $clog2(data_width / 8);
localparam data_words = 512;
localparam data_words_l2 = $clog2(data_words);
localparam data_addr_width = data_words_l2;

  reg [data_width - 1:0]  data_mem_rd;
  reg [data_width - 1:0]  data_mem_wd;
  reg [data_addr_width - 1:0] data_addr;
  reg data_mem_we;

always @(*) begin

  data_addr = fwd_flags[4] ? rf_wd[data_addr_width - 1:0] : alu_mem[data_addr_width - 1:0]; 
  data_mem_wd = fwd_flags[5] ? rf_wd : wd_mem;   
  data_mem_we = vf_mem & mf_mem[3];
end

memory mem(
    clk,

    data_mem_we, data_addr, data_mem_wd,
    data_mem_rd
);
defparam mem.data_width = data_width;
defparam mem.data_words = data_words;
defparam mem.data_addr_width = data_addr_width;


localparam code_width = 32;
localparam code_width_l2b = $clog2(data_width / 8);
localparam code_words = 512;
localparam code_words_l2 = $clog2(data_words);
localparam code_addr_width = code_words_l2;

  wire [code_width - 1:0]  code_mem_rd;

instruction_fetch ifetch(
  clk, resetn,
  pc,
  code_mem_rd
);
defparam ifetch.code_width = code_width;
defparam ifetch.code_words = code_words;
defparam ifetch.code_addr_width = code_addr_width;


  reg [3:0] cond_code;
  reg [7:0] opcode, muxflags;
  reg [3:0] rf_Rn, rf_Rm, rf_Rd;
  reg [2:0] rf_Rw;
  reg [31:0] imm32;

  reg [7:0] debug_id;








instruction_decode idecode(
  clk, resetn,

  inst_in,

  pc,
  cond_code, opcode, 
  muxflags,
  rf_Rn, rf_Rm, rf_Rd, 
  rf_Rw,
  imm32,


  debug_id
);

  reg [code_width - 1:0] prev_inst;
always @(posedge clk) begin
  prev_inst <= code_mem_rd;
end
  
  reg [code_width - 1: 0] inst_in;
always @(*) begin



  inst_in = mf_mem[4] ? prev_inst : code_mem_rd;
end

defparam idecode.code_width = code_width;
defparam idecode.code_words = code_words;
defparam idecode.reg_width = reg_width;
defparam idecode.reg_addr_width = reg_addr_width;
defparam idecode.data_width = data_width;
defparam idecode.data_addr_width = data_addr_width;





  reg [31:0] cpsr_prev, cpsr_next;
  reg [31:0] A, B;
  reg [31:0] ALU_out;
  reg [7:0] op;
  reg [3:0] cc;
  reg VF;

always @(posedge clk)
  if(!resetn)
    cpsr_prev <= 32'd0;
  else
    cpsr_prev <= cpsr_next;

always @(*) begin
  op = opcode;
  cc = cond_code;


  A = (rf_ex[7:4] == 4'hF) ? pc_prev: rf_d1; 
  A = fwd_flags[3] ? rf_wd : A;
  A = fwd_flags[1] ? alu_mem: A;



  B = mf_ex[1] ? imm32 : (rf_ex[3:0] == 4'hF) ? pc_prev : rf_d2;
  B = fwd_flags[2] ? rf_wd : B;
  B = fwd_flags[0] ? alu_mem: B;
end
  wire [7:0] debug_ex;
alu alu_m(
    clk, resetn,

    cc, op,
    A, B,
    cpsr_prev,
    cpsr_next,


    VF,
    ALU_out,

    debug_ex
);











  reg [31:0] alu_mem, alu_wb;
  reg [(3*reg_addr_width+3)-1:0] rf_ex, rf_mem, rf_wb;
  reg [7:0] mf_ex, mf_mem, mf_wb;
  reg [reg_width-1:0] wd_mem;
  reg vf_mem, vf_wb;

always @(posedge clk) begin
  if(mf_ex[7])
    alu_mem <= pc - 32'd4;
  else
    alu_mem <= ALU_out;
  alu_wb <= alu_mem;

  rf_ex <= {rf_Rw, rf_Rd, rf_Rn, rf_Rm};
  rf_mem <= rf_ex;
  rf_wb <= rf_mem;

  mf_ex <= muxflags;
  mf_mem <= mf_ex;
  mf_wb <= mf_mem;

  wd_mem <= rf_d2;



  vf_mem <= VF & (~mf_ex[6] | mf_ex[7]) & (~mf_mem[4] );
  vf_wb <= vf_mem;
end

  reg [5:0] fwd_flags;
  reg [nreg-1:0] rf_use_ex, rf_use_mem;
  reg [nreg-1:0] rf_def_mem, rf_def_wb; 
hazard_detect res(

  mf_ex, mf_mem, mf_wb,
  rf_ex, rf_mem, rf_wb,
  vf_mem, vf_wb,
  fwd_flags,
  rf_use_ex, rf_use_mem,
  rf_def_mem, rf_def_wb
);
defparam res.nreg = nreg;
defparam res.reg_addr_width = reg_addr_width;


  reg [31:0] pc, pc_next, pc_prev;
  

  always @(*) begin

    if (!resetn | pc >= (code_words << 2)) 
      pc_next = 0;
    else if(mf_ex[4])
      pc_next = pc;
    else if(~mf_mem[4] & mf_ex[6] & VF)
      pc_next = ALU_out;
    else
      pc_next = pc + 4;
  end

  always @(posedge clk) begin
    pc <= pc_next;
    pc_prev <= pc;
  end


assign led = pc[2];





assign debug_port1 = pc[9:2];
assign debug_port2 = opcode; 
assign debug_port3 = ALU_out[7:0];         
assign debug_port4 = data_addr[7:0];    
assign debug_port5 = {vf_wb, vf_mem,  VF & (~mf_ex[6] | mf_ex[7]) & (~mf_mem[4])};      
assign debug_port6 = fwd_flags;
assign debug_port7 = rf_we ? rf_wd : 8'hfc;

endmodule
module cpu(
  input wire clk,
  input wire resetn,
  output wire led,
  output wire [7:0] debug_port1,
  output wire [7:0] debug_port2,
  output wire [7:0] debug_port3,
  output wire [7:0] debug_port4,
  output wire [7:0] debug_port5,
  output wire [7:0] debug_port6,
  output wire [7:0] debug_port7
  );



 


localparam nreg = 16;
localparam reg_width = 32;
localparam reg_addr_width = $clog2(nreg);

  reg [reg_width - 1:0] rf_d1, rf_d2;
  reg [reg_addr_width - 1:0] rf_rs1, rf_rs2;
  reg [reg_addr_width - 1:0] rf_ws;
  reg [reg_width - 1:0] rf_wd;
  reg rf_we;

always @(*) begin
  rf_rs1 = rf_Rn;
  rf_rs2 = rf_Rm;

  rf_ws = rf_wb[11:8];
  rf_wd = mf_wb[2] ? data_mem_rd : alu_wb;
  rf_we = vf_wb & mf_wb[0];
end






reg_file regf(
  clk, resetn,


  rf_rs1, rf_rs2,
  rf_wd, rf_ws, rf_we,

  pc,


  rf_d1, rf_d2
);
defparam regf.nreg = nreg;
defparam regf.reg_width = reg_width;
defparam regf.reg_addr_width = reg_addr_width;


localparam data_width = 32;
localparam data_width_l2b = $clog2(data_width / 8);
localparam data_words = 512;
localparam data_words_l2 = $clog2(data_words);
localparam data_addr_width = data_words_l2;

  reg [data_width - 1:0]  data_mem_rd;
  reg [data_width - 1:0]  data_mem_wd;
  reg [data_addr_width - 1:0] data_addr;
  reg data_mem_we;

always @(*) begin

  data_addr = fwd_flags[4] ? rf_wd[data_addr_width - 1:0] : alu_mem[data_addr_width - 1:0]; 
  data_mem_wd = fwd_flags[5] ? rf_wd : wd_mem;   
  data_mem_we = vf_mem & mf_mem[3];
end

memory mem(
    clk,

    data_mem_we, data_addr, data_mem_wd,
    data_mem_rd
);
defparam mem.data_width = data_width;
defparam mem.data_words = data_words;
defparam mem.data_addr_width = data_addr_width;


localparam code_width = 32;
localparam code_width_l2b = $clog2(data_width / 8);
localparam code_words = 512;
localparam code_words_l2 = $clog2(data_words);
localparam code_addr_width = code_words_l2;

  wire [code_width - 1:0]  code_mem_rd;

instruction_fetch ifetch(
  clk, resetn,
  pc,
  code_mem_rd
);
defparam ifetch.code_width = code_width;
defparam ifetch.code_words = code_words;
defparam ifetch.code_addr_width = code_addr_width;


  reg [3:0] cond_code;
  reg [7:0] opcode, muxflags;
  reg [3:0] rf_Rn, rf_Rm, rf_Rd;
  reg [2:0] rf_Rw;
  reg [31:0] imm32;

  reg [7:0] debug_id;








instruction_decode idecode(
  clk, resetn,

  inst_in,

  pc,
  cond_code, opcode, 
  muxflags,
  rf_Rn, rf_Rm, rf_Rd, 
  rf_Rw,
  imm32,


  debug_id
);

  reg [code_width - 1:0] prev_inst;
always @(posedge clk) begin
  prev_inst <= code_mem_rd;
end
  
  reg [code_width - 1: 0] inst_in;
always @(*) begin



  inst_in = mf_mem[4] ? prev_inst : code_mem_rd;
end

defparam idecode.code_width = code_width;
defparam idecode.code_words = code_words;
defparam idecode.reg_width = reg_width;
defparam idecode.reg_addr_width = reg_addr_width;
defparam idecode.data_width = data_width;
defparam idecode.data_addr_width = data_addr_width;





  reg [31:0] cpsr_prev, cpsr_next;
  reg [31:0] A, B;
  reg [31:0] ALU_out;
  reg [7:0] op;
  reg [3:0] cc;
  reg VF;

always @(posedge clk)
  if(!resetn)
    cpsr_prev <= 32'd0;
  else
    cpsr_prev <= cpsr_next;

always @(*) begin
  op = opcode;
  cc = cond_code;


  A = (rf_ex[7:4] == 4'hF) ? pc_prev: rf_d1; 
  A = fwd_flags[3] ? rf_wd : A;
  A = fwd_flags[1] ? alu_mem: A;



  B = mf_ex[1] ? imm32 : (rf_ex[3:0] == 4'hF) ? pc_prev : rf_d2;
  B = fwd_flags[2] ? rf_wd : B;
  B = fwd_flags[0] ? alu_mem: B;
end
  wire [7:0] debug_ex;
alu alu_m(
    clk, resetn,

    cc, op,
    A, B,
    cpsr_prev,
    cpsr_next,


    VF,
    ALU_out,

    debug_ex
);











  reg [31:0] alu_mem, alu_wb;
  reg [(3*reg_addr_width+3)-1:0] rf_ex, rf_mem, rf_wb;
  reg [7:0] mf_ex, mf_mem, mf_wb;
  reg [reg_width-1:0] wd_mem;
  reg vf_mem, vf_wb;

always @(posedge clk) begin
  if(mf_ex[7])
    alu_mem <= pc - 32'd4;
  else
    alu_mem <= ALU_out;
  alu_wb <= alu_mem;

  rf_ex <= {rf_Rw, rf_Rd, rf_Rn, rf_Rm};
  rf_mem <= rf_ex;
  rf_wb <= rf_mem;

  mf_ex <= muxflags;
  mf_mem <= mf_ex;
  mf_wb <= mf_mem;

  wd_mem <= rf_d2;



  vf_mem <= VF & (~mf_ex[6] | mf_ex[7]) & (~mf_mem[4] );
  vf_wb <= vf_mem;
end

  reg [5:0] fwd_flags;
  reg [nreg-1:0] rf_use_ex, rf_use_mem;
  reg [nreg-1:0] rf_def_mem, rf_def_wb; 
hazard_detect res(

  mf_ex, mf_mem, mf_wb,
  rf_ex, rf_mem, rf_wb,
  vf_mem, vf_wb,
  fwd_flags,
  rf_use_ex, rf_use_mem,
  rf_def_mem, rf_def_wb
);
defparam res.nreg = nreg;
defparam res.reg_addr_width = reg_addr_width;


  reg [31:0] pc, pc_next, pc_prev;
  

  always @(*) begin

    if (!resetn | pc >= (code_words << 2)) 
      pc_next = 0;
    else if(mf_ex[4])
      pc_next = pc;
    else if(~mf_mem[4] & mf_ex[6] & VF)
      pc_next = ALU_out;
    else
      pc_next = pc + 4;
  end

  always @(posedge clk) begin
    pc <= pc_next;
    pc_prev <= pc;
  end


assign led = pc[2];





assign debug_port1 = pc[9:2];
assign debug_port2 = opcode; 
assign debug_port3 = ALU_out[7:0];         
assign debug_port4 = data_addr[7:0];    
assign debug_port5 = {vf_wb, vf_mem,  VF & (~mf_ex[6] | mf_ex[7]) & (~mf_mem[4])};      
assign debug_port6 = fwd_flags;
assign debug_port7 = rf_we ? rf_wd : 8'hfc;

endmodule