data/full_repos/permissive/205673649/UART/Simulacion/tb_tx.v
 line:54: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_tx.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #0\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_tx.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_tx.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #160 data = 8\'b00000110;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_tx.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #160 tx_start = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_tx.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #10 tx_start = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_tx.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #500000000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_tx.v:56: Unsupported: Ignoring delay on this delayed statement.\n    always #2.5 clk=~clk;   \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_tx.v:57: Unsupported: Ignoring delay on this delayed statement.\n    always #5 rate=~rate;        \n           ^\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_tx.v:59: Cannot find file containing module: \'tx\'\ntx #(.NB_DATA(NB_DBIT_01), .SB_TICK(NB_TICK_01))\n^~\n        ... Looked in:\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/tx\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/tx.v\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/tx.sv\n             tx\n             tx.v\n             tx.sv\n             obj_dir/tx\n             obj_dir/tx.v\n             obj_dir/tx.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_tx();

localparam  NB_DBIT_01    =  8;
localparam NB_TICK_01 = 16;

reg  clk;
reg  rst;
reg  tx_start;
reg rate;
reg [NB_DBIT_01-1:0] data;
wire done_tx;
wire tx_o;



initial	
begin
    #0
    clk = 1'b0;
    rate = 1'b0;
    rst = 1'b0;
    data = 8'b0;
    tx_start = 0;
    #10 rst = 1'b1;

    #160 data = 8'b00000110;
    
    #160 tx_start = 1'b1;
    #10 tx_start = 1'b0;
            
            
    
    #500000000 $finish;
end
    always #2.5 clk=~clk;
    always #5 rate=~rate;

tx #(.NB_DATA(NB_DBIT_01), .SB_TICK(NB_TICK_01))
u_b
(
    .i_clk(clk),
    .i_rst(rst),
    .i_tx_start(tx_start),   
    .i_data(data),               
    .i_tick(rate),
    .o_done_tx(done_tx),  
    .o_tx(tx_o)      
);

endmodule
module tb_tx();


localparam  NB_DBIT_01    =  8;
localparam NB_TICK_01 = 16;

reg  clk;
reg  rst;
reg  tx_start;
reg rate;
reg [NB_DBIT_01-1:0] data;
wire done_tx;
wire tx_o;



initial	
begin
    #0
    clk = 1'b0;
    rate = 1'b0;
    rst = 1'b0;
    data = 8'b0;
    tx_start = 0;
    #10 rst = 1'b1;

    #160 data = 8'b00000110;
    
    #160 tx_start = 1'b1;
    #10 tx_start = 1'b0;
            
            
    
    #500000000 $finish;
end
    always #2.5 clk=~clk;
    always #5 rate=~rate;

tx #(.NB_DATA(NB_DBIT_01), .SB_TICK(NB_TICK_01))
u_b
(
    .i_clk(clk),
    .i_rst(rst),
    .i_tx_start(tx_start),   
    .i_data(data),               
    .i_tick(rate),
    .o_done_tx(done_tx),  
    .o_tx(tx_o)      
);

endmodule