data/full_repos/permissive/219219909/Radix-3/src/buf20.v
data/verilator_xmls/12d67d1b-490f-444b-91f2-c12e450a81a0.xml
module buf20(
    input [31:0] a1_re,
    input [31:0] b1_re,
	 input [31:0] b2_re,
    input [31:0] a1_img,
    input [31:0] b1_img,
	 input [31:0] b2_img,
    output reg [31:0] a2_re,
    output reg [31:0] b3_re,
	 output reg [31:0] b4_re,
    output reg [31:0] a2_img,
    output reg [31:0] b3_img,
	 output reg [31:0] b4_img,
    input clk
    );
always @(posedge clk) begin
a2_re<=a1_re;
a2_img<=a1_img;
b3_re<=b1_re;
b3_img<=b1_img;
b4_re<=b2_re;
b4_img<=b2_img;
end

endmodule
module buf20(
    input [31:0] a1_re,
    input [31:0] b1_re,
	 input [31:0] b2_re,
    input [31:0] a1_img,
    input [31:0] b1_img,
	 input [31:0] b2_img,
    output reg [31:0] a2_re,
    output reg [31:0] b3_re,
	 output reg [31:0] b4_re,
    output reg [31:0] a2_img,
    output reg [31:0] b3_img,
	 output reg [31:0] b4_img,
    input clk
    );

always @(posedge clk) begin
a2_re<=a1_re;
a2_img<=a1_img;
b3_re<=b1_re;
b3_img<=b1_img;
b4_re<=b2_re;
b4_img<=b2_img;
end

endmodule