data/full_repos/permissive/105772342/hdl/conv_8to16.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/c6213eb2-def5-4465-96bc-0f46e973e722.xml
module CONV_8TO16(

input wire clk_in,
input wire reset_in,

input wire [7:0] data8_in,
input wire valid8_in,
output reg ready8_out,

output reg [15:0] data16_out,
output reg valid16_out,
input wire ready16_in
);

parameter [0:0]
  S_WAIT_MSB = 0,
  S_WAIT_LSB = 1;

reg state = S_WAIT_MSB;
reg state_next;
reg [7:0] msb = 0;
reg [7:0] msb_next;


  always @(posedge clk_in) begin
    if((reset_in == 1'b 1)) begin
      state <= S_WAIT_MSB;
      msb <= 8'b00;
    end
    else begin
      state <= state_next;
      msb <= msb_next;
    end
  end



  always @(state or msb or data8_in or valid8_in or ready16_in) begin
    state_next <= state;
    msb_next <= msb;
    valid16_out <= 1'b 0;
    case(state)

    S_WAIT_LSB : begin
      ready8_out <= ready16_in;

      data16_out <= {msb,data8_in};
      if((valid8_in == 1'b 1 && ready16_in == 1'b 1)) begin
        valid16_out <= 1'b 1;
        state_next <= S_WAIT_MSB;
      end

    end
    default : begin
      ready8_out <= 1'b 1;

      data16_out <= {16{1'bX}};
      if((valid8_in == 1'b 1)) begin
        msb_next <= data8_in;
        state_next <= S_WAIT_LSB;
      end
    end
    endcase
  end


endmodule
module CONV_8TO16(

input wire clk_in,
input wire reset_in,

input wire [7:0] data8_in,
input wire valid8_in,
output reg ready8_out,

output reg [15:0] data16_out,
output reg valid16_out,
input wire ready16_in
);


parameter [0:0]
  S_WAIT_MSB = 0,
  S_WAIT_LSB = 1;

reg state = S_WAIT_MSB;
reg state_next;
reg [7:0] msb = 0;
reg [7:0] msb_next;


  always @(posedge clk_in) begin
    if((reset_in == 1'b 1)) begin
      state <= S_WAIT_MSB;
      msb <= 8'b00;
    end
    else begin
      state <= state_next;
      msb <= msb_next;
    end
  end



  always @(state or msb or data8_in or valid8_in or ready16_in) begin
    state_next <= state;
    msb_next <= msb;
    valid16_out <= 1'b 0;
    case(state)

    S_WAIT_LSB : begin
      ready8_out <= ready16_in;

      data16_out <= {msb,data8_in};
      if((valid8_in == 1'b 1 && ready16_in == 1'b 1)) begin
        valid16_out <= 1'b 1;
        state_next <= S_WAIT_MSB;
      end

    end
    default : begin
      ready8_out <= 1'b 1;

      data16_out <= {16{1'bX}};
      if((valid8_in == 1'b 1)) begin
        msb_next <= data8_in;
        state_next <= S_WAIT_LSB;
      end
    end
    endcase
  end


endmodule