data/full_repos/permissive/132176809/adc.v
data/verilator_xmls/97fc6a12-a3e2-46fb-966b-daf415a26eff.xml
module adc (
	input wire clk,
    input wire reset,
    output wire adc_clk,
    output wire adc_cs,
    output reg ready,
    input wire adc_sd,
    output reg [11:0] data,
    output reg [11:0] max
);

    initial begin
        ready = 0;
        data = 0;
        max = 0;
    end


    assign adc_clk = clk;
    assign adc_cs = (cnt == 0 && reset == 0) ? 1 : 0; 

    reg [11:0] serial_data = 0;
    reg [3:0] cnt = 0;
    reg capture = 0;

    always @(posedge clk) begin

        if(reset) begin

            max <= 0;
            serial_data <= 12'b0;
            cnt <= 0;
            data <= 12'b0;
            ready <= 0;

        end else begin

            cnt<=cnt+1;

            if(cnt == 0) begin
                ready <= 0;
            end

            if(cnt > 1 && cnt <= 13)
                serial_data <= { serial_data[10:0], adc_sd };
            if(cnt == 0)
                serial_data <= 0;

            if(cnt == 14) begin
                data <= serial_data;
                ready <= 1;
                if(serial_data > max)
                    max <= serial_data;
            end


            if(cnt == 15) 
                ready <= 0;
        end
    end

endmodule
module adc (
	input wire clk,
    input wire reset,
    output wire adc_clk,
    output wire adc_cs,
    output reg ready,
    input wire adc_sd,
    output reg [11:0] data,
    output reg [11:0] max
);


    initial begin
        ready = 0;
        data = 0;
        max = 0;
    end


    assign adc_clk = clk;
    assign adc_cs = (cnt == 0 && reset == 0) ? 1 : 0; 

    reg [11:0] serial_data = 0;
    reg [3:0] cnt = 0;
    reg capture = 0;

    always @(posedge clk) begin

        if(reset) begin

            max <= 0;
            serial_data <= 12'b0;
            cnt <= 0;
            data <= 12'b0;
            ready <= 0;

        end else begin

            cnt<=cnt+1;

            if(cnt == 0) begin
                ready <= 0;
            end

            if(cnt > 1 && cnt <= 13)
                serial_data <= { serial_data[10:0], adc_sd };
            if(cnt == 0)
                serial_data <= 0;

            if(cnt == 14) begin
                data <= serial_data;
                ready <= 1;
                if(serial_data > max)
                    max <= serial_data;
            end


            if(cnt == 15) 
                ready <= 0;
        end
    end

endmodule