data/full_repos/permissive/216615048/src/simulation/reg_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/reg_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\nalways begin #10 clk=~clk; end\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/reg_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/reg_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/reg_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/reg_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Error: data/full_repos/permissive/216615048/src/simulation/reg_tb.v:29: Cannot find file containing module: \'register\'\nregister tb(clk,in,rst,load,out);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/register\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/register.v\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/register.sv\n             register\n             register.v\n             register.sv\n             obj_dir/register\n             obj_dir/register.v\n             obj_dir/register.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module muxer_tb();

reg rst,clk,load;
reg [31:0]in;
wire [31:0]out;

register tb(clk,in,rst,load,out);

always begin #10 clk=~clk; end

initial begin
rst = 1;
load = 0;
#10
rst = 1;
clk = 0;

load = 1;
rst = 0;
in = 32'h00000000;
#100


load = 1;
rst = 1;
in = 32'hFFFFFFFF;
#100


load = 1;
rst = 0;
in = 32'hFFFFFFFF;
#100


load = 0;
rst = 0;
in = 32'h00001111;



end
endmodule
module muxer_tb();


reg rst,clk,load;
reg [31:0]in;
wire [31:0]out;

register tb(clk,in,rst,load,out);

always begin #10 clk=~clk; end

initial begin
rst = 1;
load = 0;
#10
rst = 1;
clk = 0;

load = 1;
rst = 0;
in = 32'h00000000;
#100


load = 1;
rst = 1;
in = 32'hFFFFFFFF;
#100


load = 1;
rst = 0;
in = 32'hFFFFFFFF;
#100


load = 0;
rst = 0;
in = 32'h00001111;



end
endmodule