data/full_repos/permissive/140927679/Quartus/USB Amplifier/Remote/RemoteDecoder.v
 line:45: before: "+"
1: b'%Error: Cannot find file containing module: Amplifier/Remote,data/full_repos/permissive/140927679\n        ... Looked in:\n             data/full_repos/permissive/140927679/Quartus/USB/Amplifier/Remote,data/full_repos/permissive/140927679\n             data/full_repos/permissive/140927679/Quartus/USB/Amplifier/Remote,data/full_repos/permissive/140927679.v\n             data/full_repos/permissive/140927679/Quartus/USB/Amplifier/Remote,data/full_repos/permissive/140927679.sv\n             Amplifier/Remote,data/full_repos/permissive/140927679\n             Amplifier/Remote,data/full_repos/permissive/140927679.v\n             Amplifier/Remote,data/full_repos/permissive/140927679.sv\n             obj_dir/Amplifier/Remote,data/full_repos/permissive/140927679\n             obj_dir/Amplifier/Remote,data/full_repos/permissive/140927679.v\n             obj_dir/Amplifier/Remote,data/full_repos/permissive/140927679.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/140927679/Quartus/USB\n%Error: Cannot find file containing module: Amplifier/Remote/RemoteDecoder.v\n%Error: Exiting due to 3 error(s)\n'
module RemoteDecoder(
 input Clk,
 input Reset,
 
 input Input,

 output reg [3:0]Buttons,
 output reg [7:0]Knob
);


reg [24:0]Timeout;
reg [15:0]Count;
reg      tInput;

reg [35:0]Stream;
reg [15:0]Decoded;
reg [15:0]ValidEdges;


integer j;
always @(*) begin
 for(j = 0; j < 16; j++) begin
  Decoded   [j] = Stream[2*j  ] ^ Stream[2*j+1];
  ValidEdges[j] = Stream[2*j+1] ^ Stream[2*j+2];
 end
end


reg tReset;
always @(posedge Clk) begin
 tReset  <= Reset;
 tInput  <= Input;


 if(tReset) begin
  Timeout <= 0;
  Count   <= 0;
  Stream  <= 0;

  Buttons <= 0;
  Knob    <= 0;


 end else if(tInput ^ Input) begin
  if(Count[15]) begin
   if(&Count[14:0]) begin
    Stream <= 0;

   end else begin
    Stream <= {Stream[33:0], tInput, tInput};
   end
  end else begin
    Stream <= {Stream[34:0], tInput};
  end

  Count   <= 0;
  Timeout <= 0;


 end else if(~&Count) begin
  if(
   (~|Count        ) &&
   (~|Stream[35:32]) &&
   ( &ValidEdges   ) &&
   (~|Decoded[3: 1]) &&
   ( ^Decoded      )
  ) begin
   Buttons <= Decoded[15:12];
   Knob    <= Decoded[11: 4];
  end

  Count   <= Count   + 1'b1;
  Timeout <= Timeout + 1'b1;


 end else begin
  if(&Timeout) Buttons <= 0;
  else         Timeout <= Timeout + 1'b1;
 end
end


endmodule
module RemoteDecoder(
 input Clk,
 input Reset,
 
 input Input,

 output reg [3:0]Buttons,
 output reg [7:0]Knob
);



reg [24:0]Timeout;
reg [15:0]Count;
reg      tInput;

reg [35:0]Stream;
reg [15:0]Decoded;
reg [15:0]ValidEdges;


integer j;
always @(*) begin
 for(j = 0; j < 16; j++) begin
  Decoded   [j] = Stream[2*j  ] ^ Stream[2*j+1];
  ValidEdges[j] = Stream[2*j+1] ^ Stream[2*j+2];
 end
end


reg tReset;
always @(posedge Clk) begin
 tReset  <= Reset;
 tInput  <= Input;


 if(tReset) begin
  Timeout <= 0;
  Count   <= 0;
  Stream  <= 0;

  Buttons <= 0;
  Knob    <= 0;


 end else if(tInput ^ Input) begin
  if(Count[15]) begin
   if(&Count[14:0]) begin
    Stream <= 0;

   end else begin
    Stream <= {Stream[33:0], tInput, tInput};
   end
  end else begin
    Stream <= {Stream[34:0], tInput};
  end

  Count   <= 0;
  Timeout <= 0;


 end else if(~&Count) begin
  if(
   (~|Count        ) &&
   (~|Stream[35:32]) &&
   ( &ValidEdges   ) &&
   (~|Decoded[3: 1]) &&
   ( ^Decoded      )
  ) begin
   Buttons <= Decoded[15:12];
   Knob    <= Decoded[11: 4];
  end

  Count   <= Count   + 1'b1;
  Timeout <= Timeout + 1'b1;


 end else begin
  if(&Timeout) Buttons <= 0;
  else         Timeout <= Timeout + 1'b1;
 end
end


endmodule