data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/Mux.v
data/verilator_xmls/91abc275-678b-412a-9166-fed38ff4f9c0.xml
module Mux_2to1 (A,B,Sel,Out,Carry);

input [4:0] A,B;
input Sel;
output reg Carry;
output reg [3:0] Out;

always @ * begin
    case(Sel)
    1'b0 : begin
            Out[3:0] <= A[3:0];
            Carry <= A[4];
           end
    1'b1 : begin 
            Out[3:0] <= B[3:0];
            Carry <= B[4];
           end
    endcase
end

endmodule
module Mux_2to1 (A,B,Sel,Out,Carry);


input [4:0] A,B;
input Sel;
output reg Carry;
output reg [3:0] Out;

always @ * begin
    case(Sel)
    1'b0 : begin
            Out[3:0] <= A[3:0];
            Carry <= A[4];
           end
    1'b1 : begin 
            Out[3:0] <= B[3:0];
            Carry <= B[4];
           end
    endcase
end

endmodule