data/full_repos/permissive/18477150/lib/shared/sonic_common_fifo_usedw_calculator.sv
 line:190: before: "WIDTH"
1: b'%Error: data/full_repos/permissive/18477150/lib/shared/sonic_common_fifo_usedw_calculator.sv:5: Cannot find include file: sonic_constants.sv\n`include "sonic_constants.sv" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18477150/lib/shared,data/full_repos/permissive/18477150/sonic_constants.sv\n             data/full_repos/permissive/18477150/lib/shared,data/full_repos/permissive/18477150/sonic_constants.sv.v\n             data/full_repos/permissive/18477150/lib/shared,data/full_repos/permissive/18477150/sonic_constants.sv.sv\n             sonic_constants.sv\n             sonic_constants.sv.v\n             sonic_constants.sv.sv\n             obj_dir/sonic_constants.sv\n             obj_dir/sonic_constants.sv.v\n             obj_dir/sonic_constants.sv.sv\n%Error: data/full_repos/permissive/18477150/lib/shared/sonic_common_fifo_usedw_calculator.sv:43: Define or directive not defined: \'`USED_QWORDS_WIDTH\'\n       output logic [`USED_QWORDS_WIDTH-1:0] wrusedqwords,\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/sonic_common_fifo_usedw_calculator.sv:48: Define or directive not defined: \'`USED_QWORDS_WIDTH\'\n       output logic [`USED_QWORDS_WIDTH-1:0] rdusedqwords,\n                     ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module sonic_common_fifo_usedw_calculator 
  #(
    parameter int WIDTH = 8,
    parameter int QWORD_DEPTH = 9,
    parameter int UPSTREAM = 0, 
    parameter int READ_TO_WRITE_DELAY = 3,
    parameter int WRITE_TO_READ_DELAY = 3
    ) (

       input logic rdclock,
       input logic rdena,
       input logic wrclock,
       input logic wrena,
       input logic reset,


       input logic wrreq,
       input logic rdreq,


       output logic [`USED_QWORDS_WIDTH-1:0] wrusedqwords,
       output logic full,
       output logic almost_full,


       output logic [`USED_QWORDS_WIDTH-1:0] rdusedqwords,
       output logic [WIDTH-1:0] clock_crossed_wptr,
       output logic [WIDTH-1:0] clock_crossed_rptr,
       output logic empty,
       output logic almost_empty
       );



   localparam WR_INCREMENT = (UPSTREAM==1)?1:2;
   localparam RD_INCREMENT = (UPSTREAM==1)?2:1;

   logic [WIDTH-1:0] rdusedqwords_reg;
   logic [WIDTH-1:0] wrusedqwords_reg;
   logic 	     full_reg;
   logic 	     almost_full_reg;
   logic 	     empty_reg;
   logic 	     almost_empty_reg;








   logic [WIDTH-1:0] wrcounter, rdcounter;
   


   logic [WIDTH-1:0] clock_crossed_wrcounter, clock_crossed_rdcounter;	
   

   logic [WIDTH-1:0] clock_crossed_wrcounter_prev, clock_crossed_rdcounter_prev;
   logic [WIDTH-1:0] writes_this_read_cycle, reads_this_write_cycle;


   logic [WIDTH-1:0] writes_this_read_cycle_delay, reads_this_write_cycle_delay;


   always @ (posedge rdclock or posedge reset) begin
      if (reset == 1'b1) begin
	 rdcounter <= 0;
      end
      else if ((rdena == 1'b1) && (rdreq == 1'b1)) begin
	 rdcounter <= rdcounter + RD_INCREMENT;
      end
   end
   

   always @ (posedge wrclock or posedge reset) begin
      if (reset == 1'b1) begin
	 wrcounter <= 0;
      end
      else if ((wrena == 1'b1) && (wrreq == 1'b1)) begin

	 wrcounter <= wrcounter + WR_INCREMENT;
      end
   end



   sonic_common_gray_clock_crosser wrcounter_to_rdclock(
							.inclock(wrclock),
							.outclock(rdclock),
							.inena(wrena),
							.outena(1'b1),
							.reset(reset),
							.data(wrcounter),
							.q(clock_crossed_wrcounter)
							);
   defparam wrcounter_to_rdclock.WIDTH = WIDTH;


   always @(posedge reset or posedge rdclock) begin
      if (reset == 1'b1) 
	clock_crossed_wrcounter_prev <= 0;
      else
	clock_crossed_wrcounter_prev <= clock_crossed_wrcounter;
   end



   assign writes_this_read_cycle = clock_crossed_wrcounter - clock_crossed_wrcounter_prev;

   sonic_common_gray_clock_crosser rdcounter_to_wrclock(
							.inclock(rdclock),
							.outclock(wrclock),
							.inena(rdena),
							.outena(1'b1),
							.reset(reset),
							.data(rdcounter),
							.q(clock_crossed_rdcounter)
							);
   defparam rdcounter_to_wrclock.WIDTH = WIDTH;


   always @(posedge reset or posedge wrclock) begin
      if (reset == 1'b1)
	clock_crossed_rdcounter_prev <= 0;
      else
	clock_crossed_rdcounter_prev <= clock_crossed_rdcounter;
   end

   assign	reads_this_write_cycle = clock_crossed_rdcounter - clock_crossed_rdcounter_prev;


   sonic_common_logic_vector_delay writes_this_read_cycle_delayer(
								  .clock(rdclock),
								  .ena(1'b1),
								  .reset(reset),
								  .data(writes_this_read_cycle),
								  .q(writes_this_read_cycle_delay)
								  );
   defparam writes_this_read_cycle_delayer.WIDTH = WIDTH,
     writes_this_read_cycle_delayer.DELAY = WRITE_TO_READ_DELAY;

   sonic_common_logic_vector_delay reads_this_write_cycle_delayer(
								  .clock(wrclock),
								  .ena(1'b1),
								  .reset(reset),
								  .data(reads_this_write_cycle),
								  .q(reads_this_write_cycle_delay)
								  );
   defparam reads_this_write_cycle_delayer.WIDTH = WIDTH,
     reads_this_write_cycle_delayer.DELAY = READ_TO_WRITE_DELAY;


   always @(posedge reset or posedge wrclock) begin
      if (reset == 1'b1) begin

	 full_reg <= 0;
	 almost_full_reg <= 0;
	 wrusedqwords_reg <= 0;
      end
      else begin


	 if ((wrreq == 1'b1) && (wrena == 1'b1)) begin

	    if ((wrusedqwords_reg + WR_INCREMENT - reads_this_write_cycle_delay) > (wrusedqwords_reg + WR_INCREMENT))
	      wrusedqwords_reg <= 0;

	    else if ((wrusedqwords_reg + WR_INCREMENT - reads_this_write_cycle_delay) > QWORD_DEPTH)
              wrusedqwords_reg <= QWORD_DEPTH;
            else
	      wrusedqwords_reg <= wrusedqwords_reg + WR_INCREMENT - reads_this_write_cycle_delay;
	 end
	 else begin

            if ((wrusedqwords_reg - reads_this_write_cycle_delay) > wrusedqwords_reg)
              wrusedqwords_reg <= 0;
            else if ((wrusedqwords_reg - reads_this_write_cycle_delay) > QWORD_DEPTH)
              wrusedqwords_reg <= QWORD_DEPTH;
            else
	      wrusedqwords_reg <= wrusedqwords_reg - reads_this_write_cycle_delay;
	 end

	 if (wrusedqwords_reg >= QWORD_DEPTH)
	   full_reg <= 1'b1;
	 else
	   full_reg <= 1'b0;
	 
	 if (wrusedqwords_reg >= QWORD_DEPTH - 10)
	   almost_full_reg <= 1'b1;
	 else
	   almost_full_reg <= 1'b0;
      end
   end
   

   assign wrusedqwords = wrusedqwords_reg;
   assign full = full_reg;
   assign almost_full = (QWORD_DEPTH > 1)? almost_full_reg : 1'b1;


   always @ (posedge reset or posedge rdclock) begin
      if (reset == 1'b1) begin

	 empty_reg <= 1'b1;
	 almost_empty_reg <= 1'b1;
	 rdusedqwords_reg <= 0;
      end
      else begin
	 if ((rdreq == 1'b1) && (rdena == 1'b1))
	   begin

	      if ((rdusedqwords_reg - RD_INCREMENT + writes_this_read_cycle_delay) > rdusedqwords_reg + writes_this_read_cycle_delay) 
		rdusedqwords_reg <= 0;

              else if ((rdusedqwords_reg - RD_INCREMENT + writes_this_read_cycle_delay) > QWORD_DEPTH)
                rdusedqwords_reg <= QWORD_DEPTH;
	      else
		rdusedqwords_reg <= rdusedqwords_reg - RD_INCREMENT + writes_this_read_cycle_delay;
	   end
	 else begin
	    rdusedqwords_reg <= rdusedqwords_reg + writes_this_read_cycle_delay;
	 end


	 if (rdusedqwords_reg == 0)
	   empty_reg <= 1'b1;
	 else
	   empty_reg <= 1'b0;

	 if (rdusedqwords_reg <= 10) 
	   almost_empty_reg <= 1'b1;
	 else
	   almost_empty_reg <= 1'b0;
      end
   end


   assign rdusedqwords = rdusedqwords_reg;
   assign clock_crossed_wptr = clock_crossed_wrcounter;
   assign clock_crossed_rptr = clock_crossed_rdcounter;
   assign empty = empty_reg;
   assign almost_empty = (QWORD_DEPTH > 1) ? almost_empty_reg : 1'b1;

endmodule
module sonic_common_fifo_usedw_calculator 
  #(
    parameter int WIDTH = 8,
    parameter int QWORD_DEPTH = 9,
    parameter int UPSTREAM = 0, 
    parameter int READ_TO_WRITE_DELAY = 3,
    parameter int WRITE_TO_READ_DELAY = 3
    ) (

       input logic rdclock,
       input logic rdena,
       input logic wrclock,
       input logic wrena,
       input logic reset,


       input logic wrreq,
       input logic rdreq,


       output logic [`USED_QWORDS_WIDTH-1:0] wrusedqwords,
       output logic full,
       output logic almost_full,


       output logic [`USED_QWORDS_WIDTH-1:0] rdusedqwords,
       output logic [WIDTH-1:0] clock_crossed_wptr,
       output logic [WIDTH-1:0] clock_crossed_rptr,
       output logic empty,
       output logic almost_empty
       );




   localparam WR_INCREMENT = (UPSTREAM==1)?1:2;
   localparam RD_INCREMENT = (UPSTREAM==1)?2:1;

   logic [WIDTH-1:0] rdusedqwords_reg;
   logic [WIDTH-1:0] wrusedqwords_reg;
   logic 	     full_reg;
   logic 	     almost_full_reg;
   logic 	     empty_reg;
   logic 	     almost_empty_reg;








   logic [WIDTH-1:0] wrcounter, rdcounter;
   


   logic [WIDTH-1:0] clock_crossed_wrcounter, clock_crossed_rdcounter;	
   

   logic [WIDTH-1:0] clock_crossed_wrcounter_prev, clock_crossed_rdcounter_prev;
   logic [WIDTH-1:0] writes_this_read_cycle, reads_this_write_cycle;


   logic [WIDTH-1:0] writes_this_read_cycle_delay, reads_this_write_cycle_delay;


   always @ (posedge rdclock or posedge reset) begin
      if (reset == 1'b1) begin
	 rdcounter <= 0;
      end
      else if ((rdena == 1'b1) && (rdreq == 1'b1)) begin
	 rdcounter <= rdcounter + RD_INCREMENT;
      end
   end
   

   always @ (posedge wrclock or posedge reset) begin
      if (reset == 1'b1) begin
	 wrcounter <= 0;
      end
      else if ((wrena == 1'b1) && (wrreq == 1'b1)) begin

	 wrcounter <= wrcounter + WR_INCREMENT;
      end
   end



   sonic_common_gray_clock_crosser wrcounter_to_rdclock(
							.inclock(wrclock),
							.outclock(rdclock),
							.inena(wrena),
							.outena(1'b1),
							.reset(reset),
							.data(wrcounter),
							.q(clock_crossed_wrcounter)
							);
   defparam wrcounter_to_rdclock.WIDTH = WIDTH;


   always @(posedge reset or posedge rdclock) begin
      if (reset == 1'b1) 
	clock_crossed_wrcounter_prev <= 0;
      else
	clock_crossed_wrcounter_prev <= clock_crossed_wrcounter;
   end



   assign writes_this_read_cycle = clock_crossed_wrcounter - clock_crossed_wrcounter_prev;

   sonic_common_gray_clock_crosser rdcounter_to_wrclock(
							.inclock(rdclock),
							.outclock(wrclock),
							.inena(rdena),
							.outena(1'b1),
							.reset(reset),
							.data(rdcounter),
							.q(clock_crossed_rdcounter)
							);
   defparam rdcounter_to_wrclock.WIDTH = WIDTH;


   always @(posedge reset or posedge wrclock) begin
      if (reset == 1'b1)
	clock_crossed_rdcounter_prev <= 0;
      else
	clock_crossed_rdcounter_prev <= clock_crossed_rdcounter;
   end

   assign	reads_this_write_cycle = clock_crossed_rdcounter - clock_crossed_rdcounter_prev;


   sonic_common_logic_vector_delay writes_this_read_cycle_delayer(
								  .clock(rdclock),
								  .ena(1'b1),
								  .reset(reset),
								  .data(writes_this_read_cycle),
								  .q(writes_this_read_cycle_delay)
								  );
   defparam writes_this_read_cycle_delayer.WIDTH = WIDTH,
     writes_this_read_cycle_delayer.DELAY = WRITE_TO_READ_DELAY;

   sonic_common_logic_vector_delay reads_this_write_cycle_delayer(
								  .clock(wrclock),
								  .ena(1'b1),
								  .reset(reset),
								  .data(reads_this_write_cycle),
								  .q(reads_this_write_cycle_delay)
								  );
   defparam reads_this_write_cycle_delayer.WIDTH = WIDTH,
     reads_this_write_cycle_delayer.DELAY = READ_TO_WRITE_DELAY;


   always @(posedge reset or posedge wrclock) begin
      if (reset == 1'b1) begin

	 full_reg <= 0;
	 almost_full_reg <= 0;
	 wrusedqwords_reg <= 0;
      end
      else begin


	 if ((wrreq == 1'b1) && (wrena == 1'b1)) begin

	    if ((wrusedqwords_reg + WR_INCREMENT - reads_this_write_cycle_delay) > (wrusedqwords_reg + WR_INCREMENT))
	      wrusedqwords_reg <= 0;

	    else if ((wrusedqwords_reg + WR_INCREMENT - reads_this_write_cycle_delay) > QWORD_DEPTH)
              wrusedqwords_reg <= QWORD_DEPTH;
            else
	      wrusedqwords_reg <= wrusedqwords_reg + WR_INCREMENT - reads_this_write_cycle_delay;
	 end
	 else begin

            if ((wrusedqwords_reg - reads_this_write_cycle_delay) > wrusedqwords_reg)
              wrusedqwords_reg <= 0;
            else if ((wrusedqwords_reg - reads_this_write_cycle_delay) > QWORD_DEPTH)
              wrusedqwords_reg <= QWORD_DEPTH;
            else
	      wrusedqwords_reg <= wrusedqwords_reg - reads_this_write_cycle_delay;
	 end

	 if (wrusedqwords_reg >= QWORD_DEPTH)
	   full_reg <= 1'b1;
	 else
	   full_reg <= 1'b0;
	 
	 if (wrusedqwords_reg >= QWORD_DEPTH - 10)
	   almost_full_reg <= 1'b1;
	 else
	   almost_full_reg <= 1'b0;
      end
   end
   

   assign wrusedqwords = wrusedqwords_reg;
   assign full = full_reg;
   assign almost_full = (QWORD_DEPTH > 1)? almost_full_reg : 1'b1;


   always @ (posedge reset or posedge rdclock) begin
      if (reset == 1'b1) begin

	 empty_reg <= 1'b1;
	 almost_empty_reg <= 1'b1;
	 rdusedqwords_reg <= 0;
      end
      else begin
	 if ((rdreq == 1'b1) && (rdena == 1'b1))
	   begin

	      if ((rdusedqwords_reg - RD_INCREMENT + writes_this_read_cycle_delay) > rdusedqwords_reg + writes_this_read_cycle_delay) 
		rdusedqwords_reg <= 0;

              else if ((rdusedqwords_reg - RD_INCREMENT + writes_this_read_cycle_delay) > QWORD_DEPTH)
                rdusedqwords_reg <= QWORD_DEPTH;
	      else
		rdusedqwords_reg <= rdusedqwords_reg - RD_INCREMENT + writes_this_read_cycle_delay;
	   end
	 else begin
	    rdusedqwords_reg <= rdusedqwords_reg + writes_this_read_cycle_delay;
	 end


	 if (rdusedqwords_reg == 0)
	   empty_reg <= 1'b1;
	 else
	   empty_reg <= 1'b0;

	 if (rdusedqwords_reg <= 10) 
	   almost_empty_reg <= 1'b1;
	 else
	   almost_empty_reg <= 1'b0;
      end
   end


   assign rdusedqwords = rdusedqwords_reg;
   assign clock_crossed_wptr = clock_crossed_wrcounter;
   assign clock_crossed_rptr = clock_crossed_rdcounter;
   assign empty = empty_reg;
   assign almost_empty = (QWORD_DEPTH > 1) ? almost_empty_reg : 1'b1;

endmodule