data/full_repos/permissive/143278/ivltests/tri0b.v
 line:29: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri0b.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (t0 !== 1\'b0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri0b.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (t0 !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri0b.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (t0 !== 1\'b1) begin\n      ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg enable, val;
   tri0 t0 = (~enable) ? 1'bz : val;

   initial begin
      enable = 0;
      val = 0;

      #1 if (t0 !== 1'b0) begin
	 $display("FAILED -- undriven t0 == %b", t0);
	 $finish;
      end

      enable = 1;

      #1 if (t0 !== 1'b0) begin
	 $display("FAILED -- driven-0 t0 == %b", t0);
	 $finish;
      end

      val = 1;

      #1 if (t0 !== 1'b1) begin
	 $display("FAILED -- driven-1 t0 == %b", t0);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;


   reg enable, val;
   tri0 t0 = (~enable) ? 1'bz : val;

   initial begin
      enable = 0;
      val = 0;

      #1 if (t0 !== 1'b0) begin
	 $display("FAILED -- undriven t0 == %b", t0);
	 $finish;
      end

      enable = 1;

      #1 if (t0 !== 1'b0) begin
	 $display("FAILED -- driven-0 t0 == %b", t0);
	 $finish;
      end

      val = 1;

      #1 if (t0 !== 1'b1) begin
	 $display("FAILED -- driven-1 t0 == %b", t0);
	 $finish;
      end

      $display("PASSED");
   end
endmodule