data/full_repos/permissive/174242803/src/mips.v
1: b"%Error: data/full_repos/permissive/174242803/src/mips.v:25: Cannot find file containing module: 'controller'\n    controller cont(.clk(clk),\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174242803/src,data/full_repos/permissive/174242803/controller\n             data/full_repos/permissive/174242803/src,data/full_repos/permissive/174242803/controller.v\n             data/full_repos/permissive/174242803/src,data/full_repos/permissive/174242803/controller.sv\n             controller\n             controller.v\n             controller.sv\n             obj_dir/controller\n             obj_dir/controller.v\n             obj_dir/controller.sv\n%Error: data/full_repos/permissive/174242803/src/mips.v:42: Cannot find file containing module: 'alucontrol'\n    alucontrol ac(.aluop(aluop),\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/174242803/src/mips.v:46: Cannot find file containing module: 'datapath'\n    datapath dp(.clk(clk),\n    ^~~~~~~~\n%Error: data/full_repos/permissive/174242803/src/mips.v:66: Cannot find file containing module: 'pc_controller'\n    pc_controller pc(.zero(zero),\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module mips
    ( clk, rst, memdata, memread, memwrite, writedata, adr, const_gnd);

    parameter WIDTH = 8;
    parameter REGBITS = 3;

    input clk;
    input rst;
    input [WIDTH - 1:0] memdata;
    input const_gnd;
    output memread;
    output memwrite;
    output [WIDTH - 1:0] writedata;
    output [WIDTH - 1:0] adr;

    wire [31:0] instr;
    wire        zero, alusrca, memtoreg, iord, pcen, regwrite, regdst;
    wire [1:0]  aluop, pcsource, alusrcb;
    wire [3:0]  irwrite;
    wire [2:0]  alucont;
    wire pcwrite, branch;

    controller cont(.clk(clk),
                    .rst(rst),
                    .op(instr[31:26]),
                    .memread(memread),
                    .memwrite(memwrite),
                    .alusrca(alusrca),
                    .memtoreg(memtoreg),
                    .iord(iord),
                    .regwrite(regwrite),
                    .regdst(regdst),
                    .pcsource(pcsource),
                    .alusrcb(alusrcb),
                    .aluop(aluop),
                    .irwrite(irwrite),
                    .pcwrite(pcwrite),
                    .branch(branch));

    alucontrol ac(.aluop(aluop),
                  .funct(instr[5:0]),
                  .alucont(alucont));

    datapath dp(.clk(clk),
                .reset(rst),
                .memdata(memdata),
                .adr(adr),
                .writedata(writedata),
                .alusrca(alusrca),
                .alusrcb(alusrcb),
                .iord(iord),
                .pcen(pcen),
                .zero(zero),
                .irwrite(irwrite),
                .memtoreg(memtoreg),
                .pcsource(pcsource),
                .regwrite(regwrite),
                .regdst(regdst),
                .instr(instr),
                .alucontrol(alucont),
                .const_gnd(const_gnd)
                );

    pc_controller pc(.zero(zero),
                     .pcen(pcen),
                     .pcwrite(pcwrite),
                     .branch(branch));

endmodule
module mips
    ( clk, rst, memdata, memread, memwrite, writedata, adr, const_gnd);


    parameter WIDTH = 8;
    parameter REGBITS = 3;

    input clk;
    input rst;
    input [WIDTH - 1:0] memdata;
    input const_gnd;
    output memread;
    output memwrite;
    output [WIDTH - 1:0] writedata;
    output [WIDTH - 1:0] adr;

    wire [31:0] instr;
    wire        zero, alusrca, memtoreg, iord, pcen, regwrite, regdst;
    wire [1:0]  aluop, pcsource, alusrcb;
    wire [3:0]  irwrite;
    wire [2:0]  alucont;
    wire pcwrite, branch;

    controller cont(.clk(clk),
                    .rst(rst),
                    .op(instr[31:26]),
                    .memread(memread),
                    .memwrite(memwrite),
                    .alusrca(alusrca),
                    .memtoreg(memtoreg),
                    .iord(iord),
                    .regwrite(regwrite),
                    .regdst(regdst),
                    .pcsource(pcsource),
                    .alusrcb(alusrcb),
                    .aluop(aluop),
                    .irwrite(irwrite),
                    .pcwrite(pcwrite),
                    .branch(branch));

    alucontrol ac(.aluop(aluop),
                  .funct(instr[5:0]),
                  .alucont(alucont));

    datapath dp(.clk(clk),
                .reset(rst),
                .memdata(memdata),
                .adr(adr),
                .writedata(writedata),
                .alusrca(alusrca),
                .alusrcb(alusrcb),
                .iord(iord),
                .pcen(pcen),
                .zero(zero),
                .irwrite(irwrite),
                .memtoreg(memtoreg),
                .pcsource(pcsource),
                .regwrite(regwrite),
                .regdst(regdst),
                .instr(instr),
                .alucontrol(alucont),
                .const_gnd(const_gnd)
                );

    pc_controller pc(.zero(zero),
                     .pcen(pcen),
                     .pcwrite(pcwrite),
                     .branch(branch));

endmodule