data/full_repos/permissive/147690299/lab/31_fsm_basic/rtl/fsm_mealy.v
data/verilator_xmls/1e32434a-bcdc-46a1-a545-447919eb0bbf.xml
module fsm_mealy
(
    input  clk,
    input  rst_n,
    input  en,
    input  idata,
    output smile
);

    parameter S0 = 0,
              S1 = 1;

    reg  state;
    wire next_state;


    always @ (posedge clk or negedge rst_n)
        if (! rst_n)
            state <= S0;
        else if (en)
            state <= next_state;


    assign next_state = idata ? S0 : S1;


    assign smile = (idata & state == S1);

endmodule
module fsm_mealy
(
    input  clk,
    input  rst_n,
    input  en,
    input  idata,
    output smile
);


    parameter S0 = 0,
              S1 = 1;

    reg  state;
    wire next_state;


    always @ (posedge clk or negedge rst_n)
        if (! rst_n)
            state <= S0;
        else if (en)
            state <= next_state;


    assign next_state = idata ? S0 : S1;


    assign smile = (idata & state == S1);

endmodule