data/full_repos/permissive/162338081/separa.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/162338081/separa.v:9: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n                                                               : ... In instance separa\n        numero3 = numero/1000;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/162338081/separa.v:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n                                                                : ... In instance separa\n        numero2 = aux/100;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/162338081/separa.v:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n                                                                : ... In instance separa\n        numero1 = aux/10;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/162338081/separa.v:15: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'aux\' generates 14 bits.\n                                                                : ... In instance separa\n        numero0 = aux;\n                ^\n%Error: Exiting due to 4 warning(s)\n'
module separa( numero , numero0 , numero1 , numero2 , numero3);
    input [13:0]numero;      
    output reg [3:0]numero0;
    output reg [3:0]numero1;
    output reg [3:0]numero2;
    output reg [3:0]numero3;
    reg [13:0]aux;
    always@(numero)begin
        numero3 = numero/1000;
        aux = numero%1000;
        numero2 = aux/100;
        aux = aux%100;
        numero1 = aux/10;
        aux= aux%10;
        numero0 = aux;
    end

endmodule
module separa( numero , numero0 , numero1 , numero2 , numero3);

    input [13:0]numero;      
    output reg [3:0]numero0;
    output reg [3:0]numero1;
    output reg [3:0]numero2;
    output reg [3:0]numero3;
    reg [13:0]aux;
    always@(numero)begin
        numero3 = numero/1000;
        aux = numero%1000;
        numero2 = aux/100;
        aux = aux%100;
        numero1 = aux/10;
        aux= aux%10;
        numero0 = aux;
    end

endmodule