data/full_repos/permissive/143278/ivltests/pr1960545.v
data/verilator_xmls/2dedaab9-bc20-4bfe-8cac-092ce78038fa.xml
module test;
   initial
     begin: A1
	while(1 != 0)
	  begin: A2
	     reg B;
	     B = 1;
	     $display("B is %d", B);
	     disable A1;
	  end
     end
endmodule
module test;

   initial
     begin: A1
	while(1 != 0)
	  begin: A2
	     reg B;
	     B = 1;
	     $display("B is %d", B);
	     disable A1;
	  end
     end
endmodule