data/full_repos/permissive/211878730/atlys/practice/register4.v
data/verilator_xmls/e3be7389-c359-471d-a609-8126cf6f2906.xml
module register4(
	input  wire clk,
	input  wire [3:0] data,
	output reg [3:0] q
    );
	 
	always @(posedge clk) begin
		q <= data;
	end
endmodule
module register4(
	input  wire clk,
	input  wire [3:0] data,
	output reg [3:0] q
    );

	 
	always @(posedge clk) begin
		q <= data;
	end
endmodule