data/full_repos/permissive/148324174/HDLBits/Circuits/EdgeDetect.v
1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/EdgeDetect.v:15: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/EdgeDetect.v:2: ... Location of original declaration\nmodule top_module (\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/EdgeDetect.v:28: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/EdgeDetect.v:2: ... Location of original declaration\nmodule top_module (\n       ^~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0] in_reg1;
    always @(posedge clk)begin
        in_reg1 <= in;
        anyedge <= in^in_reg1;
    end
endmodule
module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);

    reg [7:0] in_reg1;
    always @(posedge clk)begin
        in_reg1 <= in;
        anyedge <= in^in_reg1;
    end
endmodule