data/full_repos/permissive/163484550/maze.v
 line:609: before: "["
1: b"%Error: data/full_repos/permissive/163484550/maze.v:609: Duplicate declaration of port: 'key'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                ^~~\n        data/full_repos/permissive/163484550/maze.v:615: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163484550/maze.v:609: Duplicate declaration of port: 'key'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                       ^~~\n        data/full_repos/permissive/163484550/maze.v:615: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163484550/maze.v:609: Duplicate declaration of port: 'key'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                              ^~~\n        data/full_repos/permissive/163484550/maze.v:615: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163484550/maze.v:609: Duplicate declaration of port: 'key_pulse'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                  ^~~~~~~~~\n        data/full_repos/permissive/163484550/maze.v:616: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/163484550/maze.v:609: Duplicate declaration of port: 'key_pulse'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                               ^~~~~~~~~\n        data/full_repos/permissive/163484550/maze.v:616: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/163484550/maze.v:609: Duplicate declaration of port: 'key_pulse'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                                            ^~~~~~~~~\n        data/full_repos/permissive/163484550/maze.v:616: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/163484550/maze.v:153: Duplicate pin connection: '__pinNumber4'\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                                 ^~~~~~~~~~\n        data/full_repos/permissive/163484550/maze.v:153: ... Location of original pin connection\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/163484550/maze.v:153: Duplicate pin connection: '__pinNumber5'\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                                            ^~~~~~~~~~\n        data/full_repos/permissive/163484550/maze.v:153: ... Location of original pin connection\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/163484550/maze.v:153: Duplicate pin connection: '__pinNumber6'\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                                                       ^~~~~~~~~~\n        data/full_repos/permissive/163484550/maze.v:153: ... Location of original pin connection\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/163484550/maze.v:153: Duplicate pin connection: '__pinNumber8'\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                                                                                  ^~~~~~~~~~~~~~~\n        data/full_repos/permissive/163484550/maze.v:153: ... Location of original pin connection\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                                                                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/163484550/maze.v:153: Duplicate pin connection: '__pinNumber9'\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                                                                                                  ^~~~~~~~~~~~~~~\n        data/full_repos/permissive/163484550/maze.v:153: ... Location of original pin connection\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                                                                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/163484550/maze.v:153: Duplicate pin connection: '__pinNumber10'\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                                                                                                                  ^~~~~~~~~~~~~~~\n        data/full_repos/permissive/163484550/maze.v:153: ... Location of original pin connection\n debounce c1(clk,~rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\n                                                                  ^~~~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n"
module digit_tube(clk,start,change_map,time_sign,step_cnt,digit_con,digit_seg0);
	input clk;
	input start;
	input change_map;
	input [4:0] time_sign;
	input [6:0] step_cnt;

	output reg [7:0] digit_con;
	output reg [7:0] digit_seg0;

	wire [3:0] ten;
	wire [3:0] one;
	reg [3:0] ten_step;
	reg [3:0] one_step;

	two_ten t1(.clk(clk),.num(time_sign),.ten(ten),.one(one));
	

	integer i;
	
			always @(posedge clk)
			begin
				ten_step=4'd0;
				one_step=4'd0;
		
				for(i=6;i>=0;i=i-1)
				begin
					if(ten_step>4)
						ten_step=ten_step+4'd3;
					if(one_step>4)
						one_step=one_step+4'd3;
					ten_step=ten_step<<1;
					ten_step[0]=one_step[3];
					one_step=one_step<<1;
					one_step[0]=step_cnt[i];
				end
			end

	reg [31:0] count=32'd0;
	reg clk_1kHz;

	always @(posedge clk) begin
		if(count==50000) begin
			count<=32'd0;
			clk_1kHz<=~clk_1kHz;
		end
		else begin
			count<=count+1;
		end
	end

	reg [3:0] row_num=4'b0000; 
	


	always @(posedge clk_1kHz) begin
	if(row_num!=4'b0111) begin
		row_num<=row_num+1;
	end
	else row_num<=4'b0000;
	end

	always @(posedge clk_1kHz) begin
	case(row_num)
	4'h0: begin
		digit_con<=8'b1111_1110;
	end
	4'h1: begin
		digit_con<=8'b1111_1101;
	end
	4'h2: begin
		digit_con<=8'b1111_1011;
	end
	4'h3: begin
		digit_con<=8'b1111_0111;
	end
	4'h4: begin
		digit_con<=8'b1110_1111;
	end
	4'h5: begin
		digit_con<=8'b1101_1111;
	end
	4'h6: begin
		digit_con<=8'b1011_1111;
	end
	4'h7: begin
		digit_con<=8'b0111_1111;
	end
	endcase
end

	always @(posedge clk_1kHz) begin
		
	end

	wire [2:0] maze_con;
	reg start_con=1'b0;
	reg map_con=1'b0;
	reg mode_con=1'b0;

	assign maze_con = {mode_con,map_con,start_con};

	wire start_lock;
	wire change_map_lock;


	sw b1(.clk(clk),.key_in(start),.key_out(start_lock));
	sw b2(.clk(clk),.key_in(change_map),.key_out(change_map_lock));

	always @(posedge start_lock) begin
		if(start_lock==1) begin
			start_con<=1'b1;
		end
	end

	always @(change_map_lock) begin
		if(change_map_lock==0) begin
			map_con<=1'b0;
		end
		else begin
			map_con<=1'b1;
		end
	end

	always @(posedge clk_1kHz) begin
		if(start_con==0) begin
			digit_seg0<=8'b0000_0000;
		end
		if(start_con==1) begin
		if(row_num==1) begin
			case(ten)
			4'd0:digit_seg0<=8'b11111100;
			4'd1:digit_seg0<=8'b01100000;
			4'd2:digit_seg0<=8'b11011010;	
			4'd3:digit_seg0<=8'b11110010;
			4'd4:digit_seg0<=8'b01100110;
			4'd5:digit_seg0<=8'b10110110;
			4'd6:digit_seg0<=8'b10111110;
			4'd7:digit_seg0<=8'b11100000;
			4'd8:digit_seg0<=8'b11111110;
			4'd9:digit_seg0<=8'b11110110;
		endcase
		end
		if(row_num==0) begin
		case(one)
			4'd0:digit_seg0<=8'b11111100;
			4'd1:digit_seg0<=8'b01100000;
			4'd2:digit_seg0<=8'b11011010;	
			4'd3:digit_seg0<=8'b11110010;
			4'd4:digit_seg0<=8'b01100110;
			4'd5:digit_seg0<=8'b10110110;
			4'd6:digit_seg0<=8'b10111110;
			4'd7:digit_seg0<=8'b11100000;
			4'd8:digit_seg0<=8'b11111110;
			4'd9:digit_seg0<=8'b11110110;
		endcase
		end
		if(row_num==2||row_num==3||row_num==4||row_num==5) begin
			digit_seg0<=8'b0000_0000;
		end
		if(row_num==6) begin
		case(one_step)
			4'd0:digit_seg0<=8'b11111100;
			4'd1:digit_seg0<=8'b01100000;
			4'd2:digit_seg0<=8'b11011010;	
			4'd3:digit_seg0<=8'b11110010;
			4'd4:digit_seg0<=8'b01100110;
			4'd5:digit_seg0<=8'b10110110;
			4'd6:digit_seg0<=8'b10111110;
			4'd7:digit_seg0<=8'b11100000;
			4'd8:digit_seg0<=8'b11111110;
			4'd9:digit_seg0<=8'b11110110;
		endcase
		end
		if(row_num==7) begin
			case(ten_step)
			4'd0:digit_seg0<=8'b11111100;
			4'd1:digit_seg0<=8'b01100000;
			4'd2:digit_seg0<=8'b11011010;	
			4'd3:digit_seg0<=8'b11110010;
			4'd4:digit_seg0<=8'b01100110;
			4'd5:digit_seg0<=8'b10110110;
			4'd6:digit_seg0<=8'b10111110;
			4'd7:digit_seg0<=8'b11100000;
			4'd8:digit_seg0<=8'b11111110;
			4'd9:digit_seg0<=8'b11110110;
		endcase
		end
		end
	end

endmodule
module digit_tube(clk,start,change_map,time_sign,step_cnt,digit_con,digit_seg0);

	input clk;
	input start;
	input change_map;
	input [4:0] time_sign;
	input [6:0] step_cnt;

	output reg [7:0] digit_con;
	output reg [7:0] digit_seg0;

	wire [3:0] ten;
	wire [3:0] one;
	reg [3:0] ten_step;
	reg [3:0] one_step;

	two_ten t1(.clk(clk),.num(time_sign),.ten(ten),.one(one));
	

	integer i;
	
			always @(posedge clk)
			begin
				ten_step=4'd0;
				one_step=4'd0;
		
				for(i=6;i>=0;i=i-1)
				begin
					if(ten_step>4)
						ten_step=ten_step+4'd3;
					if(one_step>4)
						one_step=one_step+4'd3;
					ten_step=ten_step<<1;
					ten_step[0]=one_step[3];
					one_step=one_step<<1;
					one_step[0]=step_cnt[i];
				end
			end

	reg [31:0] count=32'd0;
	reg clk_1kHz;

	always @(posedge clk) begin
		if(count==50000) begin
			count<=32'd0;
			clk_1kHz<=~clk_1kHz;
		end
		else begin
			count<=count+1;
		end
	end

	reg [3:0] row_num=4'b0000; 
	


	always @(posedge clk_1kHz) begin
	if(row_num!=4'b0111) begin
		row_num<=row_num+1;
	end
	else row_num<=4'b0000;
	end

	always @(posedge clk_1kHz) begin
	case(row_num)
	4'h0: begin
		digit_con<=8'b1111_1110;
	end
	4'h1: begin
		digit_con<=8'b1111_1101;
	end
	4'h2: begin
		digit_con<=8'b1111_1011;
	end
	4'h3: begin
		digit_con<=8'b1111_0111;
	end
	4'h4: begin
		digit_con<=8'b1110_1111;
	end
	4'h5: begin
		digit_con<=8'b1101_1111;
	end
	4'h6: begin
		digit_con<=8'b1011_1111;
	end
	4'h7: begin
		digit_con<=8'b0111_1111;
	end
	endcase
end

	always @(posedge clk_1kHz) begin
		
	end

	wire [2:0] maze_con;
	reg start_con=1'b0;
	reg map_con=1'b0;
	reg mode_con=1'b0;

	assign maze_con = {mode_con,map_con,start_con};

	wire start_lock;
	wire change_map_lock;


	sw b1(.clk(clk),.key_in(start),.key_out(start_lock));
	sw b2(.clk(clk),.key_in(change_map),.key_out(change_map_lock));

	always @(posedge start_lock) begin
		if(start_lock==1) begin
			start_con<=1'b1;
		end
	end

	always @(change_map_lock) begin
		if(change_map_lock==0) begin
			map_con<=1'b0;
		end
		else begin
			map_con<=1'b1;
		end
	end

	always @(posedge clk_1kHz) begin
		if(start_con==0) begin
			digit_seg0<=8'b0000_0000;
		end
		if(start_con==1) begin
		if(row_num==1) begin
			case(ten)
			4'd0:digit_seg0<=8'b11111100;
			4'd1:digit_seg0<=8'b01100000;
			4'd2:digit_seg0<=8'b11011010;	
			4'd3:digit_seg0<=8'b11110010;
			4'd4:digit_seg0<=8'b01100110;
			4'd5:digit_seg0<=8'b10110110;
			4'd6:digit_seg0<=8'b10111110;
			4'd7:digit_seg0<=8'b11100000;
			4'd8:digit_seg0<=8'b11111110;
			4'd9:digit_seg0<=8'b11110110;
		endcase
		end
		if(row_num==0) begin
		case(one)
			4'd0:digit_seg0<=8'b11111100;
			4'd1:digit_seg0<=8'b01100000;
			4'd2:digit_seg0<=8'b11011010;	
			4'd3:digit_seg0<=8'b11110010;
			4'd4:digit_seg0<=8'b01100110;
			4'd5:digit_seg0<=8'b10110110;
			4'd6:digit_seg0<=8'b10111110;
			4'd7:digit_seg0<=8'b11100000;
			4'd8:digit_seg0<=8'b11111110;
			4'd9:digit_seg0<=8'b11110110;
		endcase
		end
		if(row_num==2||row_num==3||row_num==4||row_num==5) begin
			digit_seg0<=8'b0000_0000;
		end
		if(row_num==6) begin
		case(one_step)
			4'd0:digit_seg0<=8'b11111100;
			4'd1:digit_seg0<=8'b01100000;
			4'd2:digit_seg0<=8'b11011010;	
			4'd3:digit_seg0<=8'b11110010;
			4'd4:digit_seg0<=8'b01100110;
			4'd5:digit_seg0<=8'b10110110;
			4'd6:digit_seg0<=8'b10111110;
			4'd7:digit_seg0<=8'b11100000;
			4'd8:digit_seg0<=8'b11111110;
			4'd9:digit_seg0<=8'b11110110;
		endcase
		end
		if(row_num==7) begin
			case(ten_step)
			4'd0:digit_seg0<=8'b11111100;
			4'd1:digit_seg0<=8'b01100000;
			4'd2:digit_seg0<=8'b11011010;	
			4'd3:digit_seg0<=8'b11110010;
			4'd4:digit_seg0<=8'b01100110;
			4'd5:digit_seg0<=8'b10110110;
			4'd6:digit_seg0<=8'b10111110;
			4'd7:digit_seg0<=8'b11100000;
			4'd8:digit_seg0<=8'b11111110;
			4'd9:digit_seg0<=8'b11110110;
		endcase
		end
		end
	end

endmodule