data/full_repos/permissive/133571498/count/top_tb.v
 line:8: before: "*"
1: b'%Error: data/full_repos/permissive/133571498/count/top_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("project.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/133571498/count/top_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/133571498/count/top_tb.v:21: Unsupported: fork statements\n fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/133571498/count/top_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  forever #(PERIOD/2) clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133571498/count/top_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133571498/count/top_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD en  = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133571498/count/top_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #ENDTIME $finish;\n  ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_tb;

	reg clk, rst, en;
	wire [4:0] out;

	top top (.*);

	parameter PERIOD  = 20;
	parameter ENDTIME = PERIOD * 10;

	initial	begin
		$dumpfile("project.vcd");
		$dumpvars;
		main;
	end


	task main;
	fork
		init;
		clk_gen;
		rst_gen;
		operation;
		end_sim;
	join
	endtask


	task init;
	begin
		clk = 0;
		en = 'b0;
		rst = 'b1;
	end
	endtask


	task clk_gen;
	begin
		forever #(PERIOD/2) clk = ~clk;
	end
	endtask


	task rst_gen;
	begin
		#PERIOD rst = 0;
		#PERIOD en  = 1;
	end
	endtask


	task operation;
	begin

	end
	endtask


	task end_sim;
	begin
		#ENDTIME $finish;
	end
	endtask

endmodule
module main_tb;


	reg clk, rst, en;
	wire [4:0] out;

	top top (.*);

	parameter PERIOD  = 20;
	parameter ENDTIME = PERIOD * 10;

	initial	begin
		$dumpfile("project.vcd");
		$dumpvars;
		main;
	end


	task main;
	fork
		init;
		clk_gen;
		rst_gen;
		operation;
		end_sim;
	join
	endtask


	task init;
	begin
		clk = 0;
		en = 'b0;
		rst = 'b1;
	end
	endtask


	task clk_gen;
	begin
		forever #(PERIOD/2) clk = ~clk;
	end
	endtask


	task rst_gen;
	begin
		#PERIOD rst = 0;
		#PERIOD en  = 1;
	end
	endtask


	task operation;
	begin

	end
	endtask


	task end_sim;
	begin
		#ENDTIME $finish;
	end
	endtask

endmodule