data/full_repos/permissive/119758565/seg7.v
data/verilator_xmls/1b23968b-c084-4e74-9404-5b993e878f20.xml
module seg7(
     input [3:0] bcd,
     output reg [6:0] seg
    );
	 
    always @(bcd)
    begin
        case (bcd)
            0 : seg = 7'b0111111;
            1 : seg = 7'b0001001;
            2 : seg = 7'b1011110;
            3 : seg = 7'b1011011;
            4 : seg = 7'b1101001;
            5 : seg = 7'b1110011;
            6 : seg = 7'b1110111;
            7 : seg = 7'b0011001;
            8 : seg = 7'b1111111;
            9 : seg = 7'b1111001;
            default : seg = 7'b1000000; 
        endcase
    end
    
endmodule
module seg7(
     input [3:0] bcd,
     output reg [6:0] seg
    );

	 
    always @(bcd)
    begin
        case (bcd)
            0 : seg = 7'b0111111;
            1 : seg = 7'b0001001;
            2 : seg = 7'b1011110;
            3 : seg = 7'b1011011;
            4 : seg = 7'b1101001;
            5 : seg = 7'b1110011;
            6 : seg = 7'b1110111;
            7 : seg = 7'b0011001;
            8 : seg = 7'b1111111;
            9 : seg = 7'b1111001;
            default : seg = 7'b1000000; 
        endcase
    end
    
endmodule