data/full_repos/permissive/175958895/control_unit_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/175958895/control_unit_testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/175958895/control_unit_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/175958895/control_unit_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/175958895/control_unit_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/175958895/control_unit_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/175958895/control_unit_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/175958895/control_unit_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/175958895/control_unit_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/175958895/control_unit_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/175958895/control_unit_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/175958895/control_unit_testbench.v:36: Unsupported or unknown PLI call: $monitor\n$monitor("time = %2d, function_code = %6b, select_bits_ALU = %3b", $time, function_code, select_bits_ALU); \n^~~~~~~~\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_unit_testbench(); 

reg [5:0] function_code;
wire [2:0] select_bits_ALU;


control_unit cu(select_bits_ALU, function_code);

initial begin
function_code = 6'b100000; 
#`DELAY;
function_code = 6'b100001; 
#`DELAY;
function_code = 6'b100100; 
#`DELAY;
function_code = 6'b100111; 
#`DELAY;
function_code = 6'b100101; 
#`DELAY;
function_code = 6'b101011; 
#`DELAY;
function_code = 6'b000000; 
#`DELAY;
function_code = 6'b000010; 
#`DELAY;
function_code = 6'b100010; 
#`DELAY;
function_code = 6'b100011; 
#`DELAY;
end

 
initial
begin
$monitor("time = %2d, function_code = %6b, select_bits_ALU = %3b", $time, function_code, select_bits_ALU); 
end
	
endmodule
module control_unit_testbench();
 

reg [5:0] function_code;
wire [2:0] select_bits_ALU;


control_unit cu(select_bits_ALU, function_code);

initial begin
function_code = 6'b100000; 
#`DELAY;
function_code = 6'b100001; 
#`DELAY;
function_code = 6'b100100; 
#`DELAY;
function_code = 6'b100111; 
#`DELAY;
function_code = 6'b100101; 
#`DELAY;
function_code = 6'b101011; 
#`DELAY;
function_code = 6'b000000; 
#`DELAY;
function_code = 6'b000010; 
#`DELAY;
function_code = 6'b100010; 
#`DELAY;
function_code = 6'b100011; 
#`DELAY;
end

 
initial
begin
$monitor("time = %2d, function_code = %6b, select_bits_ALU = %3b", $time, function_code, select_bits_ALU); 
end
	
endmodule