data/full_repos/permissive/181738725/wavetrace/verilog/lib/debug/stream_stats.v
1: b'%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/debug/stream_stats.v:57: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'cfg_paddr\' generates 5 bits.\n                                                                                                  : ... In instance stream_stats\n    addr_i = cfg_paddr >> 2;  \n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/debug/stream_stats.v:88: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                                  : ... In instance stream_stats\n          StatusAddr:    cfg_prdata <= {din_ready, din_valid};\n                                    ^~\n%Error: Exiting due to 2 warning(s)\n'
module stream_stats #(
  parameter DataBits = 8)
(
  input                 clk,
  input                 rst,

  input [4:0]           cfg_paddr,
  input                 cfg_psel,
  input                 cfg_penable,
  input                 cfg_pwrite,
  input [31:0]          cfg_pwdata,
  output                cfg_pready,
  output reg [31:0]     cfg_prdata,
  output                cfg_pslverr,

  input                 din_ready,
  input                 din_valid,
  input [DataBits-1:0]  din_data,
  input                 din_eof
);




  localparam StatusAddr    = 0,
             VldCntAddr    = 1,
             FrameCntAddr  = 2,
             RdyLowCntAddr = 3;

  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;

  reg [31:0] valid_count, frame_count, rdy_low_count;

  always @(posedge clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;




    if (din_valid & din_ready) begin
      valid_count <= valid_count + 1;
    end

    if (din_valid & din_ready & din_eof) begin
      frame_count <= frame_count + 1;
    end

    if (~din_ready) begin
      rdy_low_count <= rdy_low_count + 1;
    end




    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        case (addr_i)
          VldCntAddr:    valid_count   <= cfg_pwdata;
          FrameCntAddr:  frame_count   <= cfg_pwdata;
          RdyLowCntAddr: rdy_low_count <= cfg_pwdata;
        endcase

      end else begin
        case (addr_i)
          StatusAddr:    cfg_prdata <= {din_ready, din_valid};
          VldCntAddr:    cfg_prdata <= valid_count;
          FrameCntAddr:  cfg_prdata <= frame_count;
          RdyLowCntAddr: cfg_prdata <= rdy_low_count;
        endcase
      end
    end

    if (rst) begin
      valid_count   <= 0;
      frame_count   <= 0;
      rdy_low_count <= 0;
    end

  end

endmodule
module stream_stats #(
  parameter DataBits = 8)
(
  input                 clk,
  input                 rst,

  input [4:0]           cfg_paddr,
  input                 cfg_psel,
  input                 cfg_penable,
  input                 cfg_pwrite,
  input [31:0]          cfg_pwdata,
  output                cfg_pready,
  output reg [31:0]     cfg_prdata,
  output                cfg_pslverr,

  input                 din_ready,
  input                 din_valid,
  input [DataBits-1:0]  din_data,
  input                 din_eof
);





  localparam StatusAddr    = 0,
             VldCntAddr    = 1,
             FrameCntAddr  = 2,
             RdyLowCntAddr = 3;

  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;

  reg [31:0] valid_count, frame_count, rdy_low_count;

  always @(posedge clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;




    if (din_valid & din_ready) begin
      valid_count <= valid_count + 1;
    end

    if (din_valid & din_ready & din_eof) begin
      frame_count <= frame_count + 1;
    end

    if (~din_ready) begin
      rdy_low_count <= rdy_low_count + 1;
    end




    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        case (addr_i)
          VldCntAddr:    valid_count   <= cfg_pwdata;
          FrameCntAddr:  frame_count   <= cfg_pwdata;
          RdyLowCntAddr: rdy_low_count <= cfg_pwdata;
        endcase

      end else begin
        case (addr_i)
          StatusAddr:    cfg_prdata <= {din_ready, din_valid};
          VldCntAddr:    cfg_prdata <= valid_count;
          FrameCntAddr:  cfg_prdata <= frame_count;
          RdyLowCntAddr: cfg_prdata <= rdy_low_count;
        endcase
      end
    end

    if (rst) begin
      valid_count   <= 0;
      frame_count   <= 0;
      rdy_low_count <= 0;
    end

  end

endmodule