data/full_repos/permissive/183345139/common/hba_or_slaves.v
data/verilator_xmls/d68b8df0-d8df-49f3-9b62-ea4e47f7e426.xml
module hba_or_slaves #
(
    parameter integer DBUS_WIDTH = 8
)
(
    input wire [15:0] hba_xferack_slave,

    input wire [DBUS_WIDTH-1:0] hba_dbus_slave0,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave1,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave2,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave3,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave4,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave5,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave6,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave7,

    input wire [DBUS_WIDTH-1:0] hba_dbus_slave8,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave9,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave10,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave11,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave12,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave13,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave14,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave15,

    output wire hba_xferack,
    output wire [DBUS_WIDTH-1:0] hba_dbus_slave
);



assign hba_xferack = | hba_xferack_slave;


assign hba_dbus_slave = (hba_dbus_slave0 | hba_dbus_slave1 | hba_dbus_slave2 | hba_dbus_slave3) |
        (hba_dbus_slave4 | hba_dbus_slave5 | hba_dbus_slave6 | hba_dbus_slave7) |
        (hba_dbus_slave8 | hba_dbus_slave9 | hba_dbus_slave10 | hba_dbus_slave11) |
        (hba_dbus_slave12 | hba_dbus_slave13 | hba_dbus_slave14 | hba_dbus_slave15);

endmodule
module hba_or_slaves #
(
    parameter integer DBUS_WIDTH = 8
)
(
    input wire [15:0] hba_xferack_slave,

    input wire [DBUS_WIDTH-1:0] hba_dbus_slave0,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave1,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave2,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave3,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave4,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave5,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave6,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave7,

    input wire [DBUS_WIDTH-1:0] hba_dbus_slave8,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave9,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave10,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave11,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave12,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave13,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave14,
    input wire [DBUS_WIDTH-1:0] hba_dbus_slave15,

    output wire hba_xferack,
    output wire [DBUS_WIDTH-1:0] hba_dbus_slave
);




assign hba_xferack = | hba_xferack_slave;


assign hba_dbus_slave = (hba_dbus_slave0 | hba_dbus_slave1 | hba_dbus_slave2 | hba_dbus_slave3) |
        (hba_dbus_slave4 | hba_dbus_slave5 | hba_dbus_slave6 | hba_dbus_slave7) |
        (hba_dbus_slave8 | hba_dbus_slave9 | hba_dbus_slave10 | hba_dbus_slave11) |
        (hba_dbus_slave12 | hba_dbus_slave13 | hba_dbus_slave14 | hba_dbus_slave15);

endmodule