data/full_repos/permissive/140493787/src/hdl/pixelMemory.v
1: b"%Error: data/full_repos/permissive/140493787/src/hdl/pixelMemory.v:31: Cannot find file containing module: 'blk_mem_gen_0'\n    blk_mem_gen_0 mem (\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/140493787/src/hdl,data/full_repos/permissive/140493787/blk_mem_gen_0\n             data/full_repos/permissive/140493787/src/hdl,data/full_repos/permissive/140493787/blk_mem_gen_0.v\n             data/full_repos/permissive/140493787/src/hdl,data/full_repos/permissive/140493787/blk_mem_gen_0.sv\n             blk_mem_gen_0\n             blk_mem_gen_0.v\n             blk_mem_gen_0.sv\n             obj_dir/blk_mem_gen_0\n             obj_dir/blk_mem_gen_0.v\n             obj_dir/blk_mem_gen_0.sv\n%Error: Exiting due to 1 error(s)\n"
module pixelMemory (
    input  wire       read_clk,
    input  wire [9:0] read_x,
    input  wire [9:0] read_y,
    output wire       read_color,
    
    input  wire       write_clk,
    input  wire [8:0] write_x,
    input  wire [8:0] write_y,
    input  wire       wr_enable,
    
    input wire reset,
    output wire reset_done
);
    reg [17:0] reset_addr = 0;
    reg _reset_done = 1;
    assign reset_done = ~reset & _reset_done;
    
    always@(posedge write_clk)
        if (_reset_done == 1) begin
            if (reset == 1) begin
                _reset_done <= 0;
                reset_addr <= 0;
            end
        end else if (&reset_addr == 1)
            _reset_done <= 1;
        else
            reset_addr <= reset_addr + 1;
            
    wire dout;
    blk_mem_gen_0 mem (

        .clka(write_clk),
        .addra( (reset_done) ? {write_y, write_x} : (reset_addr) ),
        .dina( (reset_done) ? {1'b1} : (1'b0) ),
        .douta(),
        .wea( wr_enable | ~reset_done ),

        .clkb(read_clk),
        .addrb( {read_y[8:0], read_x[8:0]} ),
        .dinb(1'b0),
        .doutb(dout),
        .web(1'b0)
    );
    assign read_color = (reset_done) ? (dout) : (0);
endmodule
module pixelMemory (
    input  wire       read_clk,
    input  wire [9:0] read_x,
    input  wire [9:0] read_y,
    output wire       read_color,
    
    input  wire       write_clk,
    input  wire [8:0] write_x,
    input  wire [8:0] write_y,
    input  wire       wr_enable,
    
    input wire reset,
    output wire reset_done
);

    reg [17:0] reset_addr = 0;
    reg _reset_done = 1;
    assign reset_done = ~reset & _reset_done;
    
    always@(posedge write_clk)
        if (_reset_done == 1) begin
            if (reset == 1) begin
                _reset_done <= 0;
                reset_addr <= 0;
            end
        end else if (&reset_addr == 1)
            _reset_done <= 1;
        else
            reset_addr <= reset_addr + 1;
            
    wire dout;
    blk_mem_gen_0 mem (

        .clka(write_clk),
        .addra( (reset_done) ? {write_y, write_x} : (reset_addr) ),
        .dina( (reset_done) ? {1'b1} : (1'b0) ),
        .douta(),
        .wea( wr_enable | ~reset_done ),

        .clkb(read_clk),
        .addrb( {read_y[8:0], read_x[8:0]} ),
        .dinb(1'b0),
        .doutb(dout),
        .web(1'b0)
    );
    assign read_color = (reset_done) ? (dout) : (0);
endmodule