data/full_repos/permissive/211316121/lab7_2/TrafficFarm.v
data/verilator_xmls/25bc4578-aa7e-43e4-a633-38d4d2910e9c.xml
module count(
input clk,
input ST,
output TS,
output TL
);
    parameter TStime=5,TLtime=20;
    
    reg [4:0] value;
    always@(posedge clk,posedge ST)
        if(ST) value<=0;
        else if(value<TLtime) value<=value+1;
             else              value<=TLtime;
             
    assign TS = (value>=TStime-1);
    assign TL = (value>=TLtime-1); 
endmodule
module count(
input clk,
input ST,
output TS,
output TL
);

    parameter TStime=5,TLtime=20;
    
    reg [4:0] value;
    always@(posedge clk,posedge ST)
        if(ST) value<=0;
        else if(value<TLtime) value<=value+1;
             else              value<=TLtime;
             
    assign TS = (value>=TStime-1);
    assign TL = (value>=TLtime-1); 
endmodule