data/full_repos/permissive/164484080/testbench/soc_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/soc_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10 soc_clk_i = ~soc_clk_i;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/soc_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/soc_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/164484080/testbench/soc_tb.v:32: Cannot find file containing module: \'soc\'\n soc uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/164484080/testbench,data/full_repos/permissive/164484080/soc\n             data/full_repos/permissive/164484080/testbench,data/full_repos/permissive/164484080/soc.v\n             data/full_repos/permissive/164484080/testbench,data/full_repos/permissive/164484080/soc.sv\n             soc\n             soc.v\n             soc.sv\n             obj_dir/soc\n             obj_dir/soc.v\n             obj_dir/soc.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module soc_tb;


	reg soc_rst_i;
	reg soc_clk_i;


	soc uut (
		.soc_rst_i(soc_rst_i),
		.soc_clk_i(soc_clk_i)
	);

	always begin
		#10 soc_clk_i = ~soc_clk_i;
	end

	initial begin

		soc_rst_i = 0;
		soc_clk_i = 0;


		#100;


		#1000;
	end

endmodule
module soc_tb;



	reg soc_rst_i;
	reg soc_clk_i;


	soc uut (
		.soc_rst_i(soc_rst_i),
		.soc_clk_i(soc_clk_i)
	);

	always begin
		#10 soc_clk_i = ~soc_clk_i;
	end

	initial begin

		soc_rst_i = 0;
		soc_clk_i = 0;


		#100;


		#1000;
	end

endmodule