data/full_repos/permissive/133863909/Analysis of a Sequential Circuit/testbench.v
 line:31: before: "#"
1: b'%Error: Cannot find file containing module: of\n        ... Looked in:\n             data/full_repos/permissive/133863909/Analysis/of\n             data/full_repos/permissive/133863909/Analysis/of.v\n             data/full_repos/permissive/133863909/Analysis/of.sv\n             of\n             of.v\n             of.sv\n             obj_dir/of\n             obj_dir/of.v\n             obj_dir/of.sv\n%Error: Cannot find file containing module: a\n%Error: Cannot find file containing module: Sequential\n%Error: Cannot find file containing module: Circuit,data/full_repos/permissive/133863909\n%Error: Cannot find file containing module: data/full_repos/permissive/133863909/Analysis\n%Error: Cannot find file containing module: Circuit/testbench.v\n%Error: Exiting due to 6 error(s)\n'
module Testbench();

reg input_a, input_b, clock, reset;
wire [1:0] output_y;


always begin
	clock <= 0;
	#10;
	clock <= 1;
	#10;
end

analysis analysis1(output_y, input_a, input_b, clock, reset);

initial begin
    $dumpfile("TimingDiagram.vcd");
	$dumpvars(0, output_y, input_a, input_b, clock, reset);
	
	reset = 1;
	
	input_a = 0;
	input_b = 0;
	
	#20
	reset = 0;
	
	#5 
	#20 input_b = 1;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_a = 1;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_a = 1;
	#20 input_b = 1;
	#20 input_b = 0;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_a = 0;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_a = 1;
	#20 input_b = 1;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_a = 0;
	#20 input_a = 1;
	#20 input_b = 1;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_b = 1;
	#5
	
	reset = 1;
	#20;
	
    $finish;
end

endmodule
module Testbench();


reg input_a, input_b, clock, reset;
wire [1:0] output_y;


always begin
	clock <= 0;
	#10;
	clock <= 1;
	#10;
end

analysis analysis1(output_y, input_a, input_b, clock, reset);

initial begin
    $dumpfile("TimingDiagram.vcd");
	$dumpvars(0, output_y, input_a, input_b, clock, reset);
	
	reset = 1;
	
	input_a = 0;
	input_b = 0;
	
	#20
	reset = 0;
	
	#5 
	#20 input_b = 1;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_a = 1;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_a = 1;
	#20 input_b = 1;
	#20 input_b = 0;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_a = 0;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_a = 1;
	#20 input_b = 1;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_a = 0;
	#20 input_a = 1;
	#20 input_b = 1;
	#20 input_a = 1;
	#20 input_b = 0;
	#20 input_b = 1;
	#5
	
	reset = 1;
	#20;
	
    $finish;
end

endmodule