data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/imports/lab030201/lab030201.srcs/sources_1/new/ctr.v
data/verilator_xmls/86367e37-7321-4f05-aafa-77126f411634.xml
module ALUctr(
    input [5:0] Funct,
    input [1:0] ALUOp,
    output reg [3:0] ALUCtrOut
    );    
    
    always @ (ALUOp or Funct)
    begin 
        casex ( {ALUOp, Funct} )
            8'b00xxxxxx:
            ALUCtrOut=4'b0010;
            
            8'b00xxxxxx:
            ALUCtrOut=4'b0010;
            
            8'b01xxxxxx:
            ALUCtrOut=4'b0110;
            
            8'b10100000:
            ALUCtrOut=4'b0010;
            
            8'b10100010:
            ALUCtrOut=4'b0110;
            
            8'b10100100:
            ALUCtrOut=4'b0000;
            
            8'b10100101:
            ALUCtrOut=4'b0001;
            
            8'b10101010:
            ALUCtrOut=4'b0111;
            
        endcase
    end
    
endmodule
module ALUctr(
    input [5:0] Funct,
    input [1:0] ALUOp,
    output reg [3:0] ALUCtrOut
    );
    
    
    always @ (ALUOp or Funct)
    begin 
        casex ( {ALUOp, Funct} )
            8'b00xxxxxx:
            ALUCtrOut=4'b0010;
            
            8'b00xxxxxx:
            ALUCtrOut=4'b0010;
            
            8'b01xxxxxx:
            ALUCtrOut=4'b0110;
            
            8'b10100000:
            ALUCtrOut=4'b0010;
            
            8'b10100010:
            ALUCtrOut=4'b0110;
            
            8'b10100100:
            ALUCtrOut=4'b0000;
            
            8'b10100101:
            ALUCtrOut=4'b0001;
            
            8'b10101010:
            ALUCtrOut=4'b0111;
            
        endcase
    end
    
endmodule