data/full_repos/permissive/205673649/MIPS/Source/pc.v
data/verilator_xmls/97cd37b9-3a7d-42bb-bceb-0ef95f4f33f5.xml
module pc
    #(
        parameter LEN = 32
    )
    (
        input i_clk,
        input i_rst,
        input [LEN-1:0] i_mux,
        input i_enable,
        output reg [LEN-1:0] o_pc
    );
    
always @(negedge i_clk)
begin
    if(!i_rst)
        o_pc <= 32'h0;
    else
    begin
        if(!i_enable)
            o_pc <= i_mux;
        else
            o_pc <= o_pc;
    end
end
endmodule
module pc
    #(
        parameter LEN = 32
    )
    (
        input i_clk,
        input i_rst,
        input [LEN-1:0] i_mux,
        input i_enable,
        output reg [LEN-1:0] o_pc
    );

    
always @(negedge i_clk)
begin
    if(!i_rst)
        o_pc <= 32'h0;
    else
    begin
        if(!i_enable)
            o_pc <= i_mux;
        else
            o_pc <= o_pc;
    end
end
endmodule