data/full_repos/permissive/136510272/projects/version.1.zx80/icarus.v
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1: b'%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/icarus.v:81: Cannot find include file: icarus_memory.v\n    `include "icarus_memory.v"     \n             ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/projects/version.1.zx80,data/full_repos/permissive/136510272/icarus_memory.v\n             data/full_repos/permissive/136510272/projects/version.1.zx80,data/full_repos/permissive/136510272/icarus_memory.v.v\n             data/full_repos/permissive/136510272/projects/version.1.zx80,data/full_repos/permissive/136510272/icarus_memory.v.sv\n             icarus_memory.v\n             icarus_memory.v.v\n             icarus_memory.v.sv\n             obj_dir/icarus_memory.v\n             obj_dir/icarus_memory.v.v\n             obj_dir/icarus_memory.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/version.1.zx80/icarus.v:26: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/version.1.zx80/icarus.v:27: Unsupported: Ignoring delay on this delayed statement.\nalways #4 cpu = ~cpu;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/version.1.zx80/icarus.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #2000 $finish;  \n  ^\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/icarus.v:39: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("output.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/icarus.v:40: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, CPU);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/icarus.v:41: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, PORT);\n  ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module main;

reg clk;
reg cpu;

wire [3:0]  led;
reg  [7:0]  data8_in;
wire [7:0]  data8_out;
wire [15:0] address;
wire        wren;


wire [15:0] port_addr;
wire [7:0]  port_data;
wire [7:0]  port_out;
wire        port_clock;


wire [2:0]  vga_border;


processor CPU(cpu, address, data8_in, data8_out, wren, port_addr, port_data, port_out, port_clock);
port PORT(port_clock, port_addr, port_data, port_out, vga_border);


always #1 clk = ~clk;
always #4 cpu = ~cpu;


initial begin
  clk = 0;
  cpu = 0;
  #2000 $finish;
end 


initial
begin
  $dumpfile("output.vcd");
  $dumpvars(0, CPU);
  $dumpvars(0, PORT);
end


reg [7:0]  sdram[1048576];
reg [8:0]  b8;
reg        wren_already;


always @(posedge clk) begin
   

    data8_in <= sdram[ address ];
    
    if (wren) begin
    

        if (!cpu && !wren_already) begin
        
            sdram[ address ] <= data8_out[7:0];   
            wren_already     <= 1'b1;
            
        end

        else if (cpu) begin
        
            wren_already <= 1'b0;
    
        end

    end

end

initial begin

    b8       = 1'b0;
    data8_in = 1'b0;


    `include "icarus_memory.v"    

end

endmodule
module main;


reg clk;
reg cpu;

wire [3:0]  led;
reg  [7:0]  data8_in;
wire [7:0]  data8_out;
wire [15:0] address;
wire        wren;


wire [15:0] port_addr;
wire [7:0]  port_data;
wire [7:0]  port_out;
wire        port_clock;


wire [2:0]  vga_border;


processor CPU(cpu, address, data8_in, data8_out, wren, port_addr, port_data, port_out, port_clock);
port PORT(port_clock, port_addr, port_data, port_out, vga_border);


always #1 clk = ~clk;
always #4 cpu = ~cpu;


initial begin
  clk = 0;
  cpu = 0;
  #2000 $finish;
end 


initial
begin
  $dumpfile("output.vcd");
  $dumpvars(0, CPU);
  $dumpvars(0, PORT);
end


reg [7:0]  sdram[1048576];
reg [8:0]  b8;
reg        wren_already;


always @(posedge clk) begin
   

    data8_in <= sdram[ address ];
    
    if (wren) begin
    

        if (!cpu && !wren_already) begin
        
            sdram[ address ] <= data8_out[7:0];   
            wren_already     <= 1'b1;
            
        end

        else if (cpu) begin
        
            wren_already <= 1'b0;
    
        end

    end

end

initial begin

    b8       = 1'b0;
    data8_in = 1'b0;


    `include "icarus_memory.v"    

end

endmodule