data/full_repos/permissive/19572582/Lab4/lab4_part1.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:160: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'lab4_part1\'\nmodule lab4_part1 (SW, LEDG, HEX3, HEX2, HEX1, HEX0, KEY);\n       ^~~~~~~~~~\n                                                                            : ... Top module \'b2d_ssd\'\nmodule b2d_ssd (X, SSD);\n       ^~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:181: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output reg [0:6] SSD;\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:48: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX3, HEX2, HEX1, HEX0;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:55: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H0 (Q[3:0], HEX0);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:56: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H1 (Q[7:4], HEX1);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:57: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H2 (Q[11:8], HEX2);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:58: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H3 (Q[15:12], HEX3);\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:162: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output reg [0:6] SSD;\n             ^\n%Error: Exiting due to 8 warning(s)\n'
module counter_16bit (En, Clk, Clr, Q);
	
	wire [15:0] T, Qs;
	input En, Clk, Clr;
	output [15:0] Q;
		
	t_flipflop T0 (En, Clk, Clr, Qs[0]);
   assign T[0] = En & Qs[0];

  t_flipflop T1 (T[0], Clk, Clr, Qs[1]);
  assign T[1] = T[0] & Qs[1];

  t_flipflop T2 (T[1], Clk, Clr, Qs[2]);
  assign T[2] = T[1] & Qs[2];

  t_flipflop T3 (T[2], Clk, Clr, Qs[3]);
  assign T[3] = T[2] & Qs[3];

  t_flipflop T4 (T[3], Clk, Clr, Qs[4]);
  assign T[4] = T[3] & Qs[4];

  t_flipflop T5 (T[4], Clk, Clr, Qs[5]);
  assign T[5] = T[4] & Qs[5];

  t_flipflop T6 (T[5], Clk, Clr, Qs[6]);
  assign T[6] = T[5] & Qs[6];

  t_flipflop T7 (T[6], Clk, Clr, Qs[7]);
  assign T[7] = T[6] & Qs[7];

  t_flipflop T8 (T[7], Clk, Clr, Qs[8]);
  assign T[8] = T[7] & Qs[8];

  t_flipflop T9 (T[7], Clk, Clr, Qs[9]);
  assign T[9] = T[7] & Qs[9];

  t_flipflop T10 (T[9], Clk, Clr, Qs[10]);
  assign T[10] = T[9] & Qs[10];

  t_flipflop T11 (T[10], Clk, Clr, Qs[11]);
  assign T[11] = T[10] & Qs[11];
	
	t_flipflop T12 (T[11], Clk, Clr, Qs[12]);
	assign T[12] = T[11] & Qs[12];
	
	t_flipflop T13 (T[12], Clk, Clr, Qs[13]);
	assign T[13] = T[12] & Qs[13];
	
	t_flipflop T14 (T[13], Clk, Clr, Qs[14]);
	assign T[14] = T[13] & Qs[14];
	
	t_flipflop T15 (T[14], Clk, Clr, Qs[15]);

	
	assign Q = Qs;

  endmodule
module counter_16bit (En, Clk, Clr, Q);

	
	wire [15:0] T, Qs;
	input En, Clk, Clr;
	output [15:0] Q;
		
	t_flipflop T0 (En, Clk, Clr, Qs[0]);
   assign T[0] = En & Qs[0];

  t_flipflop T1 (T[0], Clk, Clr, Qs[1]);
  assign T[1] = T[0] & Qs[1];

  t_flipflop T2 (T[1], Clk, Clr, Qs[2]);
  assign T[2] = T[1] & Qs[2];

  t_flipflop T3 (T[2], Clk, Clr, Qs[3]);
  assign T[3] = T[2] & Qs[3];

  t_flipflop T4 (T[3], Clk, Clr, Qs[4]);
  assign T[4] = T[3] & Qs[4];

  t_flipflop T5 (T[4], Clk, Clr, Qs[5]);
  assign T[5] = T[4] & Qs[5];

  t_flipflop T6 (T[5], Clk, Clr, Qs[6]);
  assign T[6] = T[5] & Qs[6];

  t_flipflop T7 (T[6], Clk, Clr, Qs[7]);
  assign T[7] = T[6] & Qs[7];

  t_flipflop T8 (T[7], Clk, Clr, Qs[8]);
  assign T[8] = T[7] & Qs[8];

  t_flipflop T9 (T[7], Clk, Clr, Qs[9]);
  assign T[9] = T[7] & Qs[9];

  t_flipflop T10 (T[9], Clk, Clr, Qs[10]);
  assign T[10] = T[9] & Qs[10];

  t_flipflop T11 (T[10], Clk, Clr, Qs[11]);
  assign T[11] = T[10] & Qs[11];
	
	t_flipflop T12 (T[11], Clk, Clr, Qs[12]);
	assign T[12] = T[11] & Qs[12];
	
	t_flipflop T13 (T[12], Clk, Clr, Qs[13]);
	assign T[13] = T[12] & Qs[13];
	
	t_flipflop T14 (T[13], Clk, Clr, Qs[14]);
	assign T[14] = T[13] & Qs[14];
	
	t_flipflop T15 (T[14], Clk, Clr, Qs[15]);

	
	assign Q = Qs;

  endmodule