data/full_repos/permissive/130234582/demo_003/test_top.v
 line:50: before: "clk"
1: b'%Error: data/full_repos/permissive/130234582/demo_003/test_top.v:48: Unsupported: fork statements\n    fork\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/130234582/demo_003/test_top.v:50: Unsupported: Ignoring delay on this delayed statement.\n            #5ns clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/130234582/demo_003/test_top.v:53: Unsupported: Ignoring delay on this delayed statement.\n            #21 rst_n = 1;\n            ^\n%Error: data/full_repos/permissive/130234582/demo_003/test_top.v:56: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/130234582/demo_003/test_top.v:57: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("demo_03.vcd");\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/130234582/demo_003/test_top.v:58: Unsupported: Ignoring delay on this delayed statement.\n            #10000ns\n            ^\n%Error: data/full_repos/permissive/130234582/demo_003/test_top.v:67: Unsupported: wait statements\n    wait(rst_n == 0);\n    ^~~~\n%Error: data/full_repos/permissive/130234582/demo_003/test_top.v:80: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/130234582/demo_003/test_top.v:90: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/130234582/demo_003/test_top.v:92: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to 7 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_top;

reg [7:0] p_cnt;
reg [7:0] d_cnt;

reg       clk;
reg       rst_n;

reg       st_clk;
reg       sin;
wire      sout;
wire [15:0] dout;

s2p_w_oe U_S2P_0
(
    .clk        (clk),
    .rst_n      (rst_n),
    .oe_n       (1'b0),
    .st_clk     (st_clk),
    .sin        (sin),
    .sout       (sout),
    .dout       (dout[7:0])
);

s2p_w_oe U_S2P_1
(
    .clk        (clk),
    .rst_n      (rst_n),
    .oe_n       (1'b0),
    .st_clk     (st_clk),
    .sin        (sout),
    .dout       (dout[15:8])
);

pwm_gen U_PWM_GEN
(
    .clk        (clk),
    .rst_n      (rst_n),
    .period     (dout[7:0]),
    .duty_cycle (dout[15:8]),
    .pwm_out    (p_out)
);

initial begin
    clk   = 0;
    rst_n = 0;
    fork
        forever begin
            #5ns clk = ~clk;
        end
        begin
            #21 rst_n = 1;
        end
        begin
            $dumpvars(0);
            $dumpfile("demo_03.vcd");
            #10000ns
            $finish;
        end
    join
end

initial begin
    sin = 0;
    st_clk = 0;
    wait(rst_n == 0);
    drive_pwm(30,32);
end

task drive_pwm;
    input [7:0] duty_cycle;
    input [7:0] period;
    integer i;
    begin
        for(i=0;i<8;i=i+1)
            s2p_drive(duty_cycle[7-i]); 
        for(i=0;i<8;i=i+1)
            s2p_drive(period[7-i]);
        @(posedge clk)
        st_clk = 1;
        @(negedge clk)
        st_clk = 0;
    end
endtask

task s2p_drive;
    input val;
    begin
	@(negedge clk);
        sin = val;
        @(posedge clk);
    end
endtask

endmodule
module test_top;


reg [7:0] p_cnt;
reg [7:0] d_cnt;

reg       clk;
reg       rst_n;

reg       st_clk;
reg       sin;
wire      sout;
wire [15:0] dout;

s2p_w_oe U_S2P_0
(
    .clk        (clk),
    .rst_n      (rst_n),
    .oe_n       (1'b0),
    .st_clk     (st_clk),
    .sin        (sin),
    .sout       (sout),
    .dout       (dout[7:0])
);

s2p_w_oe U_S2P_1
(
    .clk        (clk),
    .rst_n      (rst_n),
    .oe_n       (1'b0),
    .st_clk     (st_clk),
    .sin        (sout),
    .dout       (dout[15:8])
);

pwm_gen U_PWM_GEN
(
    .clk        (clk),
    .rst_n      (rst_n),
    .period     (dout[7:0]),
    .duty_cycle (dout[15:8]),
    .pwm_out    (p_out)
);

initial begin
    clk   = 0;
    rst_n = 0;
    fork
        forever begin
            #5ns clk = ~clk;
        end
        begin
            #21 rst_n = 1;
        end
        begin
            $dumpvars(0);
            $dumpfile("demo_03.vcd");
            #10000ns
            $finish;
        end
    join
end

initial begin
    sin = 0;
    st_clk = 0;
    wait(rst_n == 0);
    drive_pwm(30,32);
end

task drive_pwm;
    input [7:0] duty_cycle;
    input [7:0] period;
    integer i;
    begin
        for(i=0;i<8;i=i+1)
            s2p_drive(duty_cycle[7-i]); 
        for(i=0;i<8;i=i+1)
            s2p_drive(period[7-i]);
        @(posedge clk)
        st_clk = 1;
        @(negedge clk)
        st_clk = 0;
    end
endtask

task s2p_drive;
    input val;
    begin
	@(negedge clk);
        sin = val;
        @(posedge clk);
    end
endtask

endmodule