data/full_repos/permissive/188270170/verilog/genram.v
data/verilator_xmls/2106bb1a-75d9-45fd-832b-733414477c47.xml
module genram #(
         parameter AW = 9,
         parameter DW = 12)

       (
         input clk,
         input cs,
         input wire [AW-1: 0] addr,
         input wire rw,
         input wire [DW-1: 0] data_in,
         output reg [DW-1: 0] data_out);


parameter ROMFILE = "prog.list";


localparam NPOS = 2 ** AW;


  reg [DW-1: 0] ram [0: NPOS-1];



  always @(posedge clk) begin
    if (cs & rw == 1)
        data_out <= ram[addr];
  end



  always @(posedge clk) begin
    if (cs & rw == 0)
        ram[addr] <= data_in;
  end



initial begin
  $readmemh(ROMFILE, ram);
end


endmodule
module genram #(
         parameter AW = 9,
         parameter DW = 12)

       (
         input clk,
         input cs,
         input wire [AW-1: 0] addr,
         input wire rw,
         input wire [DW-1: 0] data_in,
         output reg [DW-1: 0] data_out);



parameter ROMFILE = "prog.list";


localparam NPOS = 2 ** AW;


  reg [DW-1: 0] ram [0: NPOS-1];



  always @(posedge clk) begin
    if (cs & rw == 1)
        data_out <= ram[addr];
  end



  always @(posedge clk) begin
    if (cs & rw == 0)
        ram[addr] <= data_in;
  end



initial begin
  $readmemh(ROMFILE, ram);
end


endmodule