data/full_repos/permissive/169266176/flashtest.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/169266176/flashtest.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169266176/flashtest.v:83: Unsupported: Ignoring delay on this delayed statement.\n#17.675 clk<=~clk;\n^\n%Error: data/full_repos/permissive/169266176/flashtest.v:45: Cannot find file containing module: \'spiflash\'\n spiflash uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169266176,data/full_repos/permissive/169266176/spiflash\n             data/full_repos/permissive/169266176,data/full_repos/permissive/169266176/spiflash.v\n             data/full_repos/permissive/169266176,data/full_repos/permissive/169266176/spiflash.sv\n             spiflash\n             spiflash.v\n             spiflash.sv\n             obj_dir/spiflash\n             obj_dir/spiflash.v\n             obj_dir/spiflash.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module flashtest;


	reg clk;
	reg [7:0] din;
	reg [23:0] Addr;
	reg [7:0] cmd;
	reg active;
	reg ack;
	reg reset;
	wire flash_so;


	wire [7:0] dout;
	wire busy;
	wire flash_ck;
	wire flash_cs;
	wire flash_si;


	spiflash uut (
		.clk(clk), 
		.din(din), 
		.dout(dout), 
		.Addr(Addr), 
		.cmd(cmd), 
		.active(active), 
		.ack(ack), 
		.reset(reset), 
		.busy(busy), 
		.flash_ck(flash_ck), 
		.flash_cs(flash_cs), 
		.flash_si(flash_si), 
		.flash_so(flash_so)
	);
	initial begin

		clk = 0;
		din = 0;
		Addr = 24'h000000;
		cmd = 8'h00;
		active = 0;
		ack = 0;
		reset = 0;
		

		#100;

		Addr = 24'h3fe512;
		cmd=8'h03;
		active=1;
		file=$fopen("fakerom.bin","rb");
		
	end


always
		begin
#17.675	clk<=~clk;
		end


reg [2:0] bytecount=0;
reg [2:0] bitcount=7;
reg [2:0] cbitcount=0;
reg [7:0] flashreg=8'h00;
integer file;
reg command=1;

always @(negedge flash_ck) begin
	if (~flash_cs) begin
		if (~command) begin
			bitcount<=bitcount+1;
			if(bitcount==7)
				flashreg<=$fgetc(file);
			else flashreg[7:0]<={flashreg[6:0],1'b0};		
		end

	end
end

always @(posedge flash_ck) begin
	if(command) begin
		cbitcount<=cbitcount+1;
		if(cbitcount==7)
			if(bytecount==3)
				command<=0;
			else	bytecount=bytecount+1;
	end
end

assign flash_so=flashreg[7];	
		
always @(negedge active) begin
	$fclose(file);
end
		
      
endmodule
module flashtest;



	reg clk;
	reg [7:0] din;
	reg [23:0] Addr;
	reg [7:0] cmd;
	reg active;
	reg ack;
	reg reset;
	wire flash_so;


	wire [7:0] dout;
	wire busy;
	wire flash_ck;
	wire flash_cs;
	wire flash_si;


	spiflash uut (
		.clk(clk), 
		.din(din), 
		.dout(dout), 
		.Addr(Addr), 
		.cmd(cmd), 
		.active(active), 
		.ack(ack), 
		.reset(reset), 
		.busy(busy), 
		.flash_ck(flash_ck), 
		.flash_cs(flash_cs), 
		.flash_si(flash_si), 
		.flash_so(flash_so)
	);
	initial begin

		clk = 0;
		din = 0;
		Addr = 24'h000000;
		cmd = 8'h00;
		active = 0;
		ack = 0;
		reset = 0;
		

		#100;

		Addr = 24'h3fe512;
		cmd=8'h03;
		active=1;
		file=$fopen("fakerom.bin","rb");
		
	end


always
		begin
#17.675	clk<=~clk;
		end


reg [2:0] bytecount=0;
reg [2:0] bitcount=7;
reg [2:0] cbitcount=0;
reg [7:0] flashreg=8'h00;
integer file;
reg command=1;

always @(negedge flash_ck) begin
	if (~flash_cs) begin
		if (~command) begin
			bitcount<=bitcount+1;
			if(bitcount==7)
				flashreg<=$fgetc(file);
			else flashreg[7:0]<={flashreg[6:0],1'b0};		
		end

	end
end

always @(posedge flash_ck) begin
	if(command) begin
		cbitcount<=cbitcount+1;
		if(cbitcount==7)
			if(bytecount==3)
				command<=0;
			else	bytecount=bytecount+1;
	end
end

assign flash_so=flashreg[7];	
		
always @(negedge active) begin
	$fclose(file);
end
		
      
endmodule