data/full_repos/permissive/125742950/SSG.v
1: b'%Error: data/full_repos/permissive/125742950/SSG.v:37: Cannot find file containing module: \'ControlUnit\'\n    ControlUnit C0( .CLK(CLK), .RST(RST), .CE(CE), .BusControl(BusControl), .Data(Data), .BUSY(BUSY), .BR(BR),\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125742950,data/full_repos/permissive/125742950/ControlUnit\n             data/full_repos/permissive/125742950,data/full_repos/permissive/125742950/ControlUnit.v\n             data/full_repos/permissive/125742950,data/full_repos/permissive/125742950/ControlUnit.sv\n             ControlUnit\n             ControlUnit.v\n             ControlUnit.sv\n             obj_dir/ControlUnit\n             obj_dir/ControlUnit.v\n             obj_dir/ControlUnit.sv\n%Error: data/full_repos/permissive/125742950/SSG.v:41: Cannot find file containing module: \'RegisterUnit\'\n    RegisterUnit R0(    .CLK(CLK), .RST(RST), .ToneValue(ToneValue), .ToneWE(ToneWE), .Status(Status), .StatusWE(StatusWE),\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125742950/SSG.v:44: Cannot find file containing module: \'WavetableRAM\'\n    WavetableRAM W0(    .CLK(CLK), .WE(WavetableWE), .Address(WavetableAddress), .Data(WavetableSample), .Indices(WavetableIndices),\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125742950/SSG.v:47: Cannot find file containing module: \'NoiseGenerator\'\n    NoiseGenerator N0(  .CLK(CLK), .RST(RST), .Output(Noise));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125742950/SSG.v:49: Cannot find file containing module: \'OutputMultiplexer\'\n    OutputMultiplexer O0(   .Waveforms(Waveforms), .Noise(Noise), .Status(ChannelStatus),\n    ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/125742950/SSG.v:52: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'Channel0\' generates 6 bits.\n                                                             : ... In instance SSG\n    assign WaveOut = Channel0 + Channel1 + Channel2 + Channel3;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/125742950/SSG.v:52: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'Channel1\' generates 6 bits.\n                                                             : ... In instance SSG\n    assign WaveOut = Channel0 + Channel1 + Channel2 + Channel3;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/125742950/SSG.v:52: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'Channel2\' generates 6 bits.\n                                                             : ... In instance SSG\n    assign WaveOut = Channel0 + Channel1 + Channel2 + Channel3;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/125742950/SSG.v:52: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'Channel3\' generates 6 bits.\n                                                             : ... In instance SSG\n    assign WaveOut = Channel0 + Channel1 + Channel2 + Channel3;\n                                                    ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module SSG(CLK, RST, CE, BusControl, Data, BUSY, BR, WaveOut);
    input CLK, RST;
    input CE;
    input[1:0] BusControl;
    input[7:0] Data;
    output BUSY, BR;
    output[7:0] WaveOut;
    
    wire[5:0] WavetableSample;
    wire[7:0] WavetableAddress;
    wire WavetableWE;
    wire[11:0] ToneValue;
    wire[3:0] ToneWE;
    wire[7:0] Status;
    wire[7:0] StatusWE;
    
    wire[23:0] WavetableIndices;
    wire[23:0] Waveforms;
    
    wire[7:0] ChannelStatus;
    
    wire[5:0] Noise;
    
    wire[5:0] Channel0;
    wire[5:0] Channel1;
    wire[5:0] Channel2;
    wire[5:0] Channel3;
    
    
    ControlUnit C0( .CLK(CLK), .RST(RST), .CE(CE), .BusControl(BusControl), .Data(Data), .BUSY(BUSY), .BR(BR),
                    .WavetableSample(WavetableSample), .WavetableAddress(WavetableAddress), .WavetableWE(WavetableWE),
                    .ToneValue(ToneValue), .ToneWE(ToneWE), .Status(Status), .StatusWE(StatusWE));
                    
    RegisterUnit R0(    .CLK(CLK), .RST(RST), .ToneValue(ToneValue), .ToneWE(ToneWE), .Status(Status), .StatusWE(StatusWE),
                        .ChannelStatus(ChannelStatus), .WavetableIndices(WavetableIndices));
    
    WavetableRAM W0(    .CLK(CLK), .WE(WavetableWE), .Address(WavetableAddress), .Data(WavetableSample), .Indices(WavetableIndices),
                        .Waveforms(Waveforms));
                        
    NoiseGenerator N0(  .CLK(CLK), .RST(RST), .Output(Noise));
    
    OutputMultiplexer O0(   .Waveforms(Waveforms), .Noise(Noise), .Status(ChannelStatus),
                            .Channel0(Channel0), .Channel1(Channel1), .Channel2(Channel2), .Channel3(Channel3));
                            
    assign WaveOut = Channel0 + Channel1 + Channel2 + Channel3;
    
endmodule
module SSG(CLK, RST, CE, BusControl, Data, BUSY, BR, WaveOut);

    input CLK, RST;
    input CE;
    input[1:0] BusControl;
    input[7:0] Data;
    output BUSY, BR;
    output[7:0] WaveOut;
    
    wire[5:0] WavetableSample;
    wire[7:0] WavetableAddress;
    wire WavetableWE;
    wire[11:0] ToneValue;
    wire[3:0] ToneWE;
    wire[7:0] Status;
    wire[7:0] StatusWE;
    
    wire[23:0] WavetableIndices;
    wire[23:0] Waveforms;
    
    wire[7:0] ChannelStatus;
    
    wire[5:0] Noise;
    
    wire[5:0] Channel0;
    wire[5:0] Channel1;
    wire[5:0] Channel2;
    wire[5:0] Channel3;
    
    
    ControlUnit C0( .CLK(CLK), .RST(RST), .CE(CE), .BusControl(BusControl), .Data(Data), .BUSY(BUSY), .BR(BR),
                    .WavetableSample(WavetableSample), .WavetableAddress(WavetableAddress), .WavetableWE(WavetableWE),
                    .ToneValue(ToneValue), .ToneWE(ToneWE), .Status(Status), .StatusWE(StatusWE));
                    
    RegisterUnit R0(    .CLK(CLK), .RST(RST), .ToneValue(ToneValue), .ToneWE(ToneWE), .Status(Status), .StatusWE(StatusWE),
                        .ChannelStatus(ChannelStatus), .WavetableIndices(WavetableIndices));
    
    WavetableRAM W0(    .CLK(CLK), .WE(WavetableWE), .Address(WavetableAddress), .Data(WavetableSample), .Indices(WavetableIndices),
                        .Waveforms(Waveforms));
                        
    NoiseGenerator N0(  .CLK(CLK), .RST(RST), .Output(Noise));
    
    OutputMultiplexer O0(   .Waveforms(Waveforms), .Noise(Noise), .Status(ChannelStatus),
                            .Channel0(Channel0), .Channel1(Channel1), .Channel2(Channel2), .Channel3(Channel3));
                            
    assign WaveOut = Channel0 + Channel1 + Channel2 + Channel3;
    
endmodule