data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_sync.v
data/verilator_xmls/f46ef781-cedd-4577-ab1e-094952382f05.xml
module spio_spinnaker_link_sync #
(
  parameter SIZE = 1
)
(
  input                   CLK_IN,
  input      [SIZE - 1:0] IN,
  output reg [SIZE - 1:0] OUT
);




  (* IOB = "TRUE" *)
  reg  [SIZE - 1:0] sync;

   




  always @ (posedge CLK_IN)
    begin
       sync <= IN;
       OUT  <= sync;
    end


endmodule
module spio_spinnaker_link_sync #
(
  parameter SIZE = 1
)
(
  input                   CLK_IN,
  input      [SIZE - 1:0] IN,
  output reg [SIZE - 1:0] OUT
);





  (* IOB = "TRUE" *)
  reg  [SIZE - 1:0] sync;

   




  always @ (posedge CLK_IN)
    begin
       sync <= IN;
       OUT  <= sync;
    end


endmodule