data/full_repos/permissive/133571498/dance/pc.v
data/verilator_xmls/e972e957-43ce-4992-80d6-39ccaec769d1.xml
module pc (
    input clock, reset,
    output reg [3:0] count
);

    always @(posedge clock, posedge reset) begin
        if (reset) begin
            count <= 0;
        end
        else begin
            count <= (count < 8) ? count + 1 : 0;
        end
    end

endmodule
module pc (
    input clock, reset,
    output reg [3:0] count
);


    always @(posedge clock, posedge reset) begin
        if (reset) begin
            count <= 0;
        end
        else begin
            count <= (count < 8) ? count + 1 : 0;
        end
    end

endmodule