data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_2_lg_credit_to_token_decimation_p_4/top.v
 line:40: before: "t"
1: b'%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_2_lg_credit_to_token_decimation_p_4/top.v:61: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                          : ... In instance top.wrapper.bapg.ptr_sync.sync_p_z_blss\n                      (N1)? iclk_data_i : 1\'b0;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_2_lg_credit_to_token_decimation_p_4/top.v:154: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                           : ... In instance top.wrapper.bapg\n                        (N1)? w_ptr_gray_r_o : 1\'b0;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_2_lg_credit_to_token_decimation_p_4/top.v:214: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'r_dec_credit_i\' generates 1 bits.\n                                                                                                                                                                           : ... In instance top.wrapper\n  assign { N8, N7, N6, N5, N4, N3 } = r_counter_r + r_dec_credit_i;\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_2_lg_credit_to_token_decimation_p_4/top.v:216: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                           : ... In instance top.wrapper\n                                           (N1)? { N8, N7, N6, N5, N4, N3 } : 1\'b0;\n                                               ^\n%Error: Exiting due to 4 warning(s)\n'
module bsg_async_ptr_gray_lg_size_p2_use_negedge_for_launch_p0_use_async_reset_p0
(
  w_clk_i,
  w_reset_i,
  w_inc_i,
  r_clk_i,
  w_ptr_binary_r_o,
  w_ptr_gray_r_o,
  w_ptr_gray_r_rsync_o
);

  output [1:0] w_ptr_binary_r_o;
  output [1:0] w_ptr_gray_r_o;
  output [1:0] w_ptr_gray_r_rsync_o;
  input w_clk_i;
  input w_reset_i;
  input w_inc_i;
  input r_clk_i;
  wire [1:0] w_ptr_gray_r_o,w_ptr_gray_r_rsync_o,w_ptr_p2,w_ptr_gray_n;
  wire N0,N1,N2,N3;
  reg [1:0] w_ptr_p1_r,w_ptr_binary_r_o;

  bsg_launch_sync_sync_width_p2_use_negedge_for_launch_p0_use_async_reset_p0
  ptr_sync
  (
    .iclk_i(w_clk_i),
    .iclk_reset_i(w_reset_i),
    .oclk_i(r_clk_i),
    .iclk_data_i(w_ptr_gray_n),
    .iclk_data_o(w_ptr_gray_r_o),
    .oclk_data_o(w_ptr_gray_r_rsync_o)
  );

  assign w_ptr_p2 = w_ptr_p1_r + 1'b1;
  assign w_ptr_gray_n = (N0)? { w_ptr_p1_r[1:1], N3 } : 
                        (N1)? w_ptr_gray_r_o : 1'b0;
  assign N0 = w_inc_i;
  assign N1 = N2;
  assign N2 = ~w_inc_i;
  assign N3 = w_ptr_p1_r[1] ^ w_ptr_p1_r[0];

  always @(posedge w_clk_i) begin
    if(w_reset_i) begin
      { w_ptr_p1_r[1:0] } <= { 1'b0, 1'b1 };
      { w_ptr_binary_r_o[1:0] } <= { 1'b0, 1'b0 };
    end else if(w_inc_i) begin
      { w_ptr_p1_r[1:0] } <= { w_ptr_p2[1:0] };
      { w_ptr_binary_r_o[1:0] } <= { w_ptr_p1_r[1:0] };
    end 
  end


endmodule
module bsg_async_ptr_gray_lg_size_p2_use_negedge_for_launch_p0_use_async_reset_p0
(
  w_clk_i,
  w_reset_i,
  w_inc_i,
  r_clk_i,
  w_ptr_binary_r_o,
  w_ptr_gray_r_o,
  w_ptr_gray_r_rsync_o
);


  output [1:0] w_ptr_binary_r_o;
  output [1:0] w_ptr_gray_r_o;
  output [1:0] w_ptr_gray_r_rsync_o;
  input w_clk_i;
  input w_reset_i;
  input w_inc_i;
  input r_clk_i;
  wire [1:0] w_ptr_gray_r_o,w_ptr_gray_r_rsync_o,w_ptr_p2,w_ptr_gray_n;
  wire N0,N1,N2,N3;
  reg [1:0] w_ptr_p1_r,w_ptr_binary_r_o;

  bsg_launch_sync_sync_width_p2_use_negedge_for_launch_p0_use_async_reset_p0
  ptr_sync
  (
    .iclk_i(w_clk_i),
    .iclk_reset_i(w_reset_i),
    .oclk_i(r_clk_i),
    .iclk_data_i(w_ptr_gray_n),
    .iclk_data_o(w_ptr_gray_r_o),
    .oclk_data_o(w_ptr_gray_r_rsync_o)
  );

  assign w_ptr_p2 = w_ptr_p1_r + 1'b1;
  assign w_ptr_gray_n = (N0)? { w_ptr_p1_r[1:1], N3 } : 
                        (N1)? w_ptr_gray_r_o : 1'b0;
  assign N0 = w_inc_i;
  assign N1 = N2;
  assign N2 = ~w_inc_i;
  assign N3 = w_ptr_p1_r[1] ^ w_ptr_p1_r[0];

  always @(posedge w_clk_i) begin
    if(w_reset_i) begin
      { w_ptr_p1_r[1:0] } <= { 1'b0, 1'b1 };
      { w_ptr_binary_r_o[1:0] } <= { 1'b0, 1'b0 };
    end else if(w_inc_i) begin
      { w_ptr_p1_r[1:0] } <= { w_ptr_p2[1:0] };
      { w_ptr_binary_r_o[1:0] } <= { w_ptr_p1_r[1:0] };
    end 
  end


endmodule