data/full_repos/permissive/146246005/RISC-y Processor/RISCY_CPU.sv
 line:3: before: "package"
1: b'%Error: Cannot find file containing module: Processor,data/full_repos/permissive/146246005\n        ... Looked in:\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.v\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.sv\n             Processor,data/full_repos/permissive/146246005\n             Processor,data/full_repos/permissive/146246005.v\n             Processor,data/full_repos/permissive/146246005.sv\n             obj_dir/Processor,data/full_repos/permissive/146246005\n             obj_dir/Processor,data/full_repos/permissive/146246005.v\n             obj_dir/Processor,data/full_repos/permissive/146246005.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/RISC-y\n%Error: Cannot find file containing module: Processor/RISCY_CPU.sv\n%Error: Exiting due to 3 error(s)\n'
module ROM(DATA, ADDR, OE, CS);
  output reg [31:0] DATA;
  input wire [4:0] ADDR; 
  input OE, CS;
  reg [31:0] memory [0:31];
  

  always@* DATA = (OE && !CS) ? memory[ADDR] : 32'bz;

endmodule
module ROM(DATA, ADDR, OE, CS);

  output reg [31:0] DATA;
  input wire [4:0] ADDR; 
  input OE, CS;
  reg [31:0] memory [0:31];
  

  always@* DATA = (OE && !CS) ? memory[ADDR] : 32'bz;

endmodule