data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6.v
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data/verilator_xmls/8da96748-135e-4ee3-b6b2-309749f85b24.xml
module Top (
input [3:0] i1,
input [3:0] i2,
input [3:0] i3,
input [3:0] i4,
input [3:0] i5,
input [3:0] i6,
output [5:0] answer
);
wire [5:0] cout_S1;
wire [5:0] sum_S1;
wire [5:0] cout_S2;
wire [5:0] sum_S2;
wire [5:0] sum_S3;
wire [5:0] cout_S3;

stage1_3is2 S1 ( {i1[3],i1[3],i1[3:0]} , {i2[3],i2[3],i2[3:0]} , {i3[3],i3[3],i3[3:0]} , cout_S1[5:0] , sum_S1[5:0]);
stage2_3is2 S2 ( {i4[3],i4[3],i4[3:0]} , {i5[3],i5[3],i5[3:0]} , {i6[3],i6[3],i6[3:0]} , cout_S2[5:0] , sum_S2[5:0]);
stage3_4is2 S3 (sum_S1[5:0],({cout_S1[4:0],1'b0}),sum_S2[5:0],({cout_S2[4:0],1'b0}),sum_S3[5:0],cout_S3[5:0]);
assign answer [5:0] = (sum_S3[5:0]) + ({cout_S3[4:0],1'b0}); 
endmodule
module Top (
input [3:0] i1,
input [3:0] i2,
input [3:0] i3,
input [3:0] i4,
input [3:0] i5,
input [3:0] i6,
output [5:0] answer
);

wire [5:0] cout_S1;
wire [5:0] sum_S1;
wire [5:0] cout_S2;
wire [5:0] sum_S2;
wire [5:0] sum_S3;
wire [5:0] cout_S3;

stage1_3is2 S1 ( {i1[3],i1[3],i1[3:0]} , {i2[3],i2[3],i2[3:0]} , {i3[3],i3[3],i3[3:0]} , cout_S1[5:0] , sum_S1[5:0]);
stage2_3is2 S2 ( {i4[3],i4[3],i4[3:0]} , {i5[3],i5[3],i5[3:0]} , {i6[3],i6[3],i6[3:0]} , cout_S2[5:0] , sum_S2[5:0]);
stage3_4is2 S3 (sum_S1[5:0],({cout_S1[4:0],1'b0}),sum_S2[5:0],({cout_S2[4:0],1'b0}),sum_S3[5:0],cout_S3[5:0]);
assign answer [5:0] = (sum_S3[5:0]) + ({cout_S3[4:0],1'b0}); 
endmodule