data/full_repos/permissive/112823543/Avalon_LedPanel _Client_Server/StandardAnimation.v
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1: b'%Error: Cannot find file containing module: _Client_Server,data/full_repos/permissive/112823543\n        ... Looked in:\n             data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543\n             data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.v\n             data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.sv\n             _Client_Server,data/full_repos/permissive/112823543\n             _Client_Server,data/full_repos/permissive/112823543.v\n             _Client_Server,data/full_repos/permissive/112823543.sv\n             obj_dir/_Client_Server,data/full_repos/permissive/112823543\n             obj_dir/_Client_Server,data/full_repos/permissive/112823543.v\n             obj_dir/_Client_Server,data/full_repos/permissive/112823543.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/112823543/Avalon_LedPanel\n%Error: Cannot find file containing module: _Client_Server/StandardAnimation.v\n%Error: Exiting due to 3 error(s)\n'
module StandardAnimation #(
        parameter   NUM_REGIONS = 5,
		parameter	DISPLAY_ROWS_LINES = 4,
		parameter	DISPLAY_COLS_LINES = 6,
		parameter	COLOR_BITS		   = 8
    ) (
    input wire              clock_clk,
    input wire              v_sync,
    input wire              reset_rst,


    input wire [2:0]        s0_address,
    input wire              s0_read,
    output reg [31:0]       s0_readdata,
    input wire              s0_write,
    input wire [31:0]       s0_writedata,


    input wire [NUM_REGIONS-1:0]    event_trigger,

    input wire [DISPLAY_COLS_LINES-1:0]             col1,
    input wire [DISPLAY_ROWS_LINES-1:0]             row1,
    input wire [3:0]                                bitplane1,
    output reg                                      red1,
    output reg                                      green1,
    output reg                                      blue1,

    input wire [DISPLAY_COLS_LINES-1:0]             col2,
    input wire [DISPLAY_ROWS_LINES-1:0]             row2,
    input wire [3:0]                                bitplane2,
    output reg                                      red2,
    output reg                                      green2,
    output reg                                      blue2

);











    reg [7:0]           RegStartColumn, RegEndColumn, RegStartRow, RegEndRow;
    reg [7:0]           RegLightColorR, RegLightColorG, RegLightColorB;
    reg [7:0]           RegAnimationType;
    reg [31:0]          RegParameterSlope;
    reg [31:0]          RegParameterFrequency;
    reg [31:0]          RegParameterDirection;
    reg [31:0]          RegParameterSpeed;



    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                RegStartColumn  <= 8'b0;
                RegEndColumn    <= 8'b0;
                RegStartRow     <= 8'b0;
                RegEndRow       <= 8'b0;
                RegLightColorB  <= 8'b0;
                RegLightColorG  <= 8'b0;
                RegLightColorR  <= 8'b0;
                RegAnimationType<= 8'b0;
                RegParameterSlope <= 32'b0;
                RegParameterFrequency <= 32'b0;
                RegParameterSpeed <= 32'b0;
                RegParameterDirection <= 32'b0;
            end else begin
                if (s0_write) begin
                    case (s0_address)
                        3'd0:   
                            begin
                                RegStartColumn      <= s0_writedata[31:24]; 
                                RegEndColumn        <= s0_writedata[23:16]; 
                                RegStartRow         <= s0_writedata[15:8]; 
                                RegEndRow           <= s0_writedata[7:0];
                            end
                        3'd1:
                            begin
                                RegLightColorR      <= s0_writedata[7:0];
                                RegLightColorG      <= s0_writedata[15:8];
                                RegLightColorB      <= s0_writedata[23:16];
                            end
                        3'd2:
                            begin
                                RegAnimationType    <= s0_writedata[7:0];
                            end
                        3'd3:
                            begin
                                RegParameterSlope   <= s0_writedata;
                            end
                        3'd4:
                            begin
                                RegParameterFrequency <= s0_writedata;
                            end
                        3'd5:
                            begin
                                RegParameterDirection <= s0_writedata;
                            end
                        3'd6:
                            begin
                                RegParameterSpeed   <= s0_writedata;                              
                            end
                    endcase
                end
            end
        end

    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                s0_readdata <= 32'b0;
            end else begin
                s0_readdata <= 32'b0;
                if (s0_read) begin
                    case (s0_address)
                        3'd0:   s0_readdata <= {RegStartColumn, RegEndColumn, RegStartRow, RegEndRow};
                        3'd1:   s0_readdata <= {8'b0, RegLightColorB, RegLightColorG, RegLightColorR};
                        3'd2:   s0_readdata <= {24'b0, RegAnimationType};
                        3'd3:   s0_readdata <= RegParameterSlope;
                        3'd4:   s0_readdata <= RegParameterFrequency;
                        3'd5:   s0_readdata <= RegParameterDirection;
                        3'd6:   s0_readdata <= RegParameterSpeed;
                        default:    s0_readdata <= 32'b0;
                    endcase
                end
            end
      
        end






    reg [7:0]           RegStartColumn_q, RegEndColumn_q, RegStartRow_q, RegEndRow_q;
    reg [7:0]           RegLightColorR_q, RegLightColorG_q, RegLightColorB_q;
    reg [7:0]           FrameCount_d, FrameCount_q;
    reg [1:0]           v_sync_edge_detect_d,v_sync_edge_detect_q;

    wire                cs_col1, cs_row1;
    assign              cs_col1 = (col1 >= RegStartColumn_q) && (col1 <= RegEndColumn_q);
    assign              cs_row1 = (row1 >= RegStartRow_q   ) && (row1 <= RegEndRow_q);
    wire                cs1 = cs_col1 && cs_row1;
    wire                cs_col2, cs_row2;
    assign              cs_col2 = (col2 >= RegStartColumn_q) && (col2 <= RegEndColumn_q);
    assign              cs_row2 = (row2 >= RegStartRow_q   ) && (row2 <= RegEndRow_q);
    wire                cs2 = cs_col2 && cs_row2;


    always @(*)
        begin
            if (reset_rst) begin
                v_sync_edge_detect_d <= 2'b0;
            end else begin
                v_sync_edge_detect_d <= {v_sync_edge_detect_q[0], v_sync};
            end
        end

    always @(posedge clock_clk)
        begin
            if (reset_rst) begin
                v_sync_edge_detect_q <= 2'b0;
            end else begin
                v_sync_edge_detect_q <= v_sync_edge_detect_d;
            end
        end



    always @(*)
        begin
            if (reset_rst) begin
                FrameCount_d <= 0;
            end else begin
                FrameCount_d <= FrameCount_q;
                if (v_sync_edge_detect_q == 2'b01) begin
                    if (event_trigger[0]) begin
                            FrameCount_d <= FrameCount_q + 1;
                    end else begin
                        if (FrameCount_q !=0) 
                            FrameCount_d <= FrameCount_q - 1;
                    end
                end
            end
        end

    always @(posedge clock_clk)
        begin
            if (reset_rst) begin
                FrameCount_q <= 0;
            end else begin
                FrameCount_q <= FrameCount_d;
            end
        end

    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
            end else begin
                if (v_sync) begin
                    RegStartColumn_q    <= RegStartColumn;
                    RegEndColumn_q      <= RegEndColumn;
                    RegStartRow_q       <= RegStartRow;
                    RegEndRow_q         <= RegEndRow;
                    RegLightColorB_q    <= RegLightColorB;
                    RegLightColorG_q    <= RegLightColorG;
                    RegLightColorR_q    <= RegLightColorR;
                end else begin
                end 
            end
        end

`ifdef (0)

    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                red1 <= 0;
                green1 <= 0;
                blue1 <= 0; 
            end else begin
                red1 <= 0;
                green1 <= 0;
                blue1 <= 0;
                if (cs1) begin
                    if (event_trigger[0]) begin
                        red1 <= RegLightColorR_q[bitplane1];
                        green1 <= RegLightColorG_q[bitplane1];
                        blue1 <= RegLightColorB_q[bitplane1];
                    end 
                end 
            end
        end

    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                red2 <= 0;
                green2 <= 0;
                blue2 <= 0;
            end else begin
                red2 <= 0;
                green2 <= 0;
                blue2 <= 0;
                if (cs2) begin
                    if (event_trigger[0]) begin
                        red2 <= RegLightColorR_q[bitplane2];
                        green2 <= RegLightColorG_q[bitplane2];
                        blue2 <= RegLightColorB_q[bitplane2];
                    end
                end
            end
        end
`endif


    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                red1 <= 0;
                green1 <= 0;
                blue1 <= 0; 
            end else begin
                red1 <= 0;
                green1 <= 0;
                blue1 <= 0;
                if (cs1) begin
                    if (event_trigger[0]) begin
                        red1 <= RegLightColorR_q[bitplane1];
                        green1 <= RegLightColorG_q[bitplane1];
                        blue1 <= RegLightColorB_q[bitplane1];
                    end 
                end 
            end
        end

    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                red2 <= 0;
                green2 <= 0;
                blue2 <= 0;
            end else begin
                red2 <= 0;
                green2 <= 0;
                blue2 <= 0;
                if (cs2) begin
                    if (event_trigger[0]) begin
                        red2 <= RegLightColorR_q[bitplane2];
                        green2 <= RegLightColorG_q[bitplane2];
                        blue2 <= RegLightColorB_q[bitplane2];
                    end
                end
            end
        end
endmodule
module StandardAnimation #(
        parameter   NUM_REGIONS = 5,
		parameter	DISPLAY_ROWS_LINES = 4,
		parameter	DISPLAY_COLS_LINES = 6,
		parameter	COLOR_BITS		   = 8
    ) (
    input wire              clock_clk,
    input wire              v_sync,
    input wire              reset_rst,


    input wire [2:0]        s0_address,
    input wire              s0_read,
    output reg [31:0]       s0_readdata,
    input wire              s0_write,
    input wire [31:0]       s0_writedata,


    input wire [NUM_REGIONS-1:0]    event_trigger,

    input wire [DISPLAY_COLS_LINES-1:0]             col1,
    input wire [DISPLAY_ROWS_LINES-1:0]             row1,
    input wire [3:0]                                bitplane1,
    output reg                                      red1,
    output reg                                      green1,
    output reg                                      blue1,

    input wire [DISPLAY_COLS_LINES-1:0]             col2,
    input wire [DISPLAY_ROWS_LINES-1:0]             row2,
    input wire [3:0]                                bitplane2,
    output reg                                      red2,
    output reg                                      green2,
    output reg                                      blue2

);












    reg [7:0]           RegStartColumn, RegEndColumn, RegStartRow, RegEndRow;
    reg [7:0]           RegLightColorR, RegLightColorG, RegLightColorB;
    reg [7:0]           RegAnimationType;
    reg [31:0]          RegParameterSlope;
    reg [31:0]          RegParameterFrequency;
    reg [31:0]          RegParameterDirection;
    reg [31:0]          RegParameterSpeed;



    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                RegStartColumn  <= 8'b0;
                RegEndColumn    <= 8'b0;
                RegStartRow     <= 8'b0;
                RegEndRow       <= 8'b0;
                RegLightColorB  <= 8'b0;
                RegLightColorG  <= 8'b0;
                RegLightColorR  <= 8'b0;
                RegAnimationType<= 8'b0;
                RegParameterSlope <= 32'b0;
                RegParameterFrequency <= 32'b0;
                RegParameterSpeed <= 32'b0;
                RegParameterDirection <= 32'b0;
            end else begin
                if (s0_write) begin
                    case (s0_address)
                        3'd0:   
                            begin
                                RegStartColumn      <= s0_writedata[31:24]; 
                                RegEndColumn        <= s0_writedata[23:16]; 
                                RegStartRow         <= s0_writedata[15:8]; 
                                RegEndRow           <= s0_writedata[7:0];
                            end
                        3'd1:
                            begin
                                RegLightColorR      <= s0_writedata[7:0];
                                RegLightColorG      <= s0_writedata[15:8];
                                RegLightColorB      <= s0_writedata[23:16];
                            end
                        3'd2:
                            begin
                                RegAnimationType    <= s0_writedata[7:0];
                            end
                        3'd3:
                            begin
                                RegParameterSlope   <= s0_writedata;
                            end
                        3'd4:
                            begin
                                RegParameterFrequency <= s0_writedata;
                            end
                        3'd5:
                            begin
                                RegParameterDirection <= s0_writedata;
                            end
                        3'd6:
                            begin
                                RegParameterSpeed   <= s0_writedata;                              
                            end
                    endcase
                end
            end
        end

    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                s0_readdata <= 32'b0;
            end else begin
                s0_readdata <= 32'b0;
                if (s0_read) begin
                    case (s0_address)
                        3'd0:   s0_readdata <= {RegStartColumn, RegEndColumn, RegStartRow, RegEndRow};
                        3'd1:   s0_readdata <= {8'b0, RegLightColorB, RegLightColorG, RegLightColorR};
                        3'd2:   s0_readdata <= {24'b0, RegAnimationType};
                        3'd3:   s0_readdata <= RegParameterSlope;
                        3'd4:   s0_readdata <= RegParameterFrequency;
                        3'd5:   s0_readdata <= RegParameterDirection;
                        3'd6:   s0_readdata <= RegParameterSpeed;
                        default:    s0_readdata <= 32'b0;
                    endcase
                end
            end
      
        end






    reg [7:0]           RegStartColumn_q, RegEndColumn_q, RegStartRow_q, RegEndRow_q;
    reg [7:0]           RegLightColorR_q, RegLightColorG_q, RegLightColorB_q;
    reg [7:0]           FrameCount_d, FrameCount_q;
    reg [1:0]           v_sync_edge_detect_d,v_sync_edge_detect_q;

    wire                cs_col1, cs_row1;
    assign              cs_col1 = (col1 >= RegStartColumn_q) && (col1 <= RegEndColumn_q);
    assign              cs_row1 = (row1 >= RegStartRow_q   ) && (row1 <= RegEndRow_q);
    wire                cs1 = cs_col1 && cs_row1;
    wire                cs_col2, cs_row2;
    assign              cs_col2 = (col2 >= RegStartColumn_q) && (col2 <= RegEndColumn_q);
    assign              cs_row2 = (row2 >= RegStartRow_q   ) && (row2 <= RegEndRow_q);
    wire                cs2 = cs_col2 && cs_row2;


    always @(*)
        begin
            if (reset_rst) begin
                v_sync_edge_detect_d <= 2'b0;
            end else begin
                v_sync_edge_detect_d <= {v_sync_edge_detect_q[0], v_sync};
            end
        end

    always @(posedge clock_clk)
        begin
            if (reset_rst) begin
                v_sync_edge_detect_q <= 2'b0;
            end else begin
                v_sync_edge_detect_q <= v_sync_edge_detect_d;
            end
        end



    always @(*)
        begin
            if (reset_rst) begin
                FrameCount_d <= 0;
            end else begin
                FrameCount_d <= FrameCount_q;
                if (v_sync_edge_detect_q == 2'b01) begin
                    if (event_trigger[0]) begin
                            FrameCount_d <= FrameCount_q + 1;
                    end else begin
                        if (FrameCount_q !=0) 
                            FrameCount_d <= FrameCount_q - 1;
                    end
                end
            end
        end

    always @(posedge clock_clk)
        begin
            if (reset_rst) begin
                FrameCount_q <= 0;
            end else begin
                FrameCount_q <= FrameCount_d;
            end
        end

    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
            end else begin
                if (v_sync) begin
                    RegStartColumn_q    <= RegStartColumn;
                    RegEndColumn_q      <= RegEndColumn;
                    RegStartRow_q       <= RegStartRow;
                    RegEndRow_q         <= RegEndRow;
                    RegLightColorB_q    <= RegLightColorB;
                    RegLightColorG_q    <= RegLightColorG;
                    RegLightColorR_q    <= RegLightColorR;
                end else begin
                end 
            end
        end

`ifdef (0)

    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                red1 <= 0;
                green1 <= 0;
                blue1 <= 0; 
            end else begin
                red1 <= 0;
                green1 <= 0;
                blue1 <= 0;
                if (cs1) begin
                    if (event_trigger[0]) begin
                        red1 <= RegLightColorR_q[bitplane1];
                        green1 <= RegLightColorG_q[bitplane1];
                        blue1 <= RegLightColorB_q[bitplane1];
                    end 
                end 
            end
        end

    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                red2 <= 0;
                green2 <= 0;
                blue2 <= 0;
            end else begin
                red2 <= 0;
                green2 <= 0;
                blue2 <= 0;
                if (cs2) begin
                    if (event_trigger[0]) begin
                        red2 <= RegLightColorR_q[bitplane2];
                        green2 <= RegLightColorG_q[bitplane2];
                        blue2 <= RegLightColorB_q[bitplane2];
                    end
                end
            end
        end
`endif


    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                red1 <= 0;
                green1 <= 0;
                blue1 <= 0; 
            end else begin
                red1 <= 0;
                green1 <= 0;
                blue1 <= 0;
                if (cs1) begin
                    if (event_trigger[0]) begin
                        red1 <= RegLightColorR_q[bitplane1];
                        green1 <= RegLightColorG_q[bitplane1];
                        blue1 <= RegLightColorB_q[bitplane1];
                    end 
                end 
            end
        end

    always @(posedge clock_clk) 
        begin
            if (reset_rst) begin
                red2 <= 0;
                green2 <= 0;
                blue2 <= 0;
            end else begin
                red2 <= 0;
                green2 <= 0;
                blue2 <= 0;
                if (cs2) begin
                    if (event_trigger[0]) begin
                        red2 <= RegLightColorR_q[bitplane2];
                        green2 <= RegLightColorG_q[bitplane2];
                        blue2 <= RegLightColorB_q[bitplane2];
                    end
                end
            end
        end
endmodule