data/full_repos/permissive/206783267/SPI/CNTLR/ADS8688_manchn_tb.v
 line:25: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206783267/SPI/CNTLR/ADS8688_manchn_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n forever #(CLK_CYCLE/2) clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/206783267/SPI/CNTLR/ADS8688_manchn_tb.v:24: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: data/full_repos/permissive/206783267/SPI/CNTLR/ADS8688_manchn_tb.v:32: syntax error, unexpected \'@\'\n @(posedge arstn)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/SPI/CNTLR/ADS8688_manchn_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE) manchn_start <= 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/SPI/CNTLR/ADS8688_manchn_tb.v:42: syntax error, unexpected \'@\'\n @(posedge manchn_start)\n ^\n%Error: data/full_repos/permissive/206783267/SPI/CNTLR/ADS8688_manchn_tb.v:56: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ADS8688_manchn_tb();

parameter CLK_CYCLE = 20;

reg	clk, arstn;
reg	manchn_start;
reg	[15:0]	chsel;
wire	sclk, csn, mosi;
reg		miso;
wire	manchn_done;
wire	[15:0]	ch_data;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	@(posedge clk)
		#(CLK_CYCLE)	arstn = 1'b1;
end


task gen_manchn_start;
begin
	manchn_start = 1'b0;
	@(posedge arstn)
		#(CLK_CYCLE*15)	manchn_start <= 1'b1;
		#(CLK_CYCLE)	manchn_start <= 1'b0;
end
endtask


task gen_chsel;
begin
	chsel = 'd0;
	@(posedge manchn_start)
		#(CLK_CYCLE)	chsel = 16'hc400;
	@(negedge manchn_done)
		#(CLK_CYCLE*15)	$finish;
end
endtask

initial begin
	miso = 1'b0;
end
always@(posedge sclk) begin
	miso = $random;
end

initial fork
	gen_manchn_start;
	gen_chsel;
join

ADS8688_manchn DUT(
	.clk(clk),
	.arstn(arstn),
	.manchn_start(manchn_start),
	.chsel(chsel),
	.sclk(sclk),
	.csn(csn),
	.mosi(mosi),
	.miso(miso),
	.manchn_done(manchn_done),
	.ch_data(ch_data)
	);

endmodule
module ADS8688_manchn_tb();


parameter CLK_CYCLE = 20;

reg	clk, arstn;
reg	manchn_start;
reg	[15:0]	chsel;
wire	sclk, csn, mosi;
reg		miso;
wire	manchn_done;
wire	[15:0]	ch_data;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	@(posedge clk)
		#(CLK_CYCLE)	arstn = 1'b1;
end


task gen_manchn_start;
begin
	manchn_start = 1'b0;
	@(posedge arstn)
		#(CLK_CYCLE*15)	manchn_start <= 1'b1;
		#(CLK_CYCLE)	manchn_start <= 1'b0;
end
endtask


task gen_chsel;
begin
	chsel = 'd0;
	@(posedge manchn_start)
		#(CLK_CYCLE)	chsel = 16'hc400;
	@(negedge manchn_done)
		#(CLK_CYCLE*15)	$finish;
end
endtask

initial begin
	miso = 1'b0;
end
always@(posedge sclk) begin
	miso = $random;
end

initial fork
	gen_manchn_start;
	gen_chsel;
join

ADS8688_manchn DUT(
	.clk(clk),
	.arstn(arstn),
	.manchn_start(manchn_start),
	.chsel(chsel),
	.sclk(sclk),
	.csn(csn),
	.mosi(mosi),
	.miso(miso),
	.manchn_done(manchn_done),
	.ch_data(ch_data)
	);

endmodule