data/full_repos/permissive/118082957/main/proj1.v
 line:18: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:10: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20 rst=1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:17: Unsupported: Ignoring delay on this delayed statement.\n#435\n^\n%Warning-IMPLICIT: data/full_repos/permissive/118082957/main/proj1.v:648: Signal definition not found, creating implicitly: \'Zflag_reg\'\n   MAR_next, Zflag_reg, zflag_next);\n             ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/118082957/main/proj1.v:648: Signal definition not found, creating implicitly: \'zflag_next\'\n   MAR_next, Zflag_reg, zflag_next);\n                        ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/118082957/main/proj1.v:696: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'ACC_reg\' generates 16 bits.\n                                                                     : ... In instance tb_proj1.dut.datapath\n zflag = (!ACC_reg)? 1:0;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/118082957/main/proj1.v:19: Bit extraction of array[255:0] requires 8 bit index, not 16 bits.\n                                                                    : ... In instance tb_proj1\n$display("0x00d %d\\n",tb_proj1.dut.ram_ins.mem256x16[16\'h000d]);\n                                                    ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module proj1(
 clk,
 rst,
 MemRW_IO,
 MemAddr_IO,
 MemD_IO
 );
 input clk;
 input rst;
 output MemRW_IO;
 output [7:0] MemAddr_IO;
 output [15:0]MemD_IO;
 wire    [15:0]MemD; 

 wire [7:0] MemAddr;
 wire [15:0] MemQ;
 wire zflag;
 wire [7:0] opcode;
 wire muxPC, muxMAR, muxACC, loadMAR, loadPC,
     loadACC, loadMDR, loadIR, MemRW; 
 wire [1:0] opALU;


	ram ram_ins(MemRW, MemD, MemQ, MemAddr);



	ctr ctr_main(clk, rst, zflag, opcode,
		      	muxPC, muxMAR, muxACC, loadMAR, loadPC, 
				loadACC, loadMDR, loadIR, opALU, MemRW);


	datapath datapath(clk, rst, muxPC, muxMAR, muxACC, loadMAR,
 				loadPC, loadACC, loadMDR, loadIR, opALU,
 				zflag, opcode, MemAddr, MemD, MemQ);


endmodule
module proj1(
 clk,
 rst,
 MemRW_IO,
 MemAddr_IO,
 MemD_IO
 );

 input clk;
 input rst;
 output MemRW_IO;
 output [7:0] MemAddr_IO;
 output [15:0]MemD_IO;
 wire    [15:0]MemD; 

 wire [7:0] MemAddr;
 wire [15:0] MemQ;
 wire zflag;
 wire [7:0] opcode;
 wire muxPC, muxMAR, muxACC, loadMAR, loadPC,
     loadACC, loadMDR, loadIR, MemRW; 
 wire [1:0] opALU;


	ram ram_ins(MemRW, MemD, MemQ, MemAddr);



	ctr ctr_main(clk, rst, zflag, opcode,
		      	muxPC, muxMAR, muxACC, loadMAR, loadPC, 
				loadACC, loadMDR, loadIR, opALU, MemRW);


	datapath datapath(clk, rst, muxPC, muxMAR, muxACC, loadMAR,
 				loadPC, loadACC, loadMDR, loadIR, opALU,
 				zflag, opcode, MemAddr, MemD, MemQ);


endmodule