data/full_repos/permissive/16552133/src/verilog/alu_with_acc.v
 line:38: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/16552133/src/verilog/alu_with_acc.v:43: Operator NOT expects 32 or 17 bits on the LHS, but LHS\'s VARREF \'in\' generates 16 bits.\n                                                                                 : ... In instance alu_with_acc\n   3\'b001 : {v,accumulator} <= accumulator - ((~in) + 1);  \n                                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module alu_with_acc(clk,in,out,select,enable);
	parameter n = 16;
	parameter m = 3;
	
	input clk, enable;
	input [n-1:0] in;
	input [m-1:0] select;
	output [n-1:0] out;
	reg [n-1:0] accumulator;
	reg v;
	
	initial begin
		accumulator <= 16'h00;
		v = 0;
	end
	
	always @(posedge(clk))
	begin
		if (enable == 1) begin
			case (select)
			3'b000 : {v,accumulator} <= accumulator + in;
			3'b001 : {v,accumulator} <= accumulator - ((~in) + 1);
			3'b010 : {v,accumulator} <= accumulator + 1'b1;
			3'b011 : {v,accumulator} <= accumulator - 1'b1;


			3'b110 : accumulator <= in;
			3'b111 : accumulator <= accumulator;
			endcase
		end
	end
	

	assign out = select[2] ? accumulator : 16'hZZ;
	
endmodule
module alu_with_acc(clk,in,out,select,enable);

	parameter n = 16;
	parameter m = 3;
	
	input clk, enable;
	input [n-1:0] in;
	input [m-1:0] select;
	output [n-1:0] out;
	reg [n-1:0] accumulator;
	reg v;
	
	initial begin
		accumulator <= 16'h00;
		v = 0;
	end
	
	always @(posedge(clk))
	begin
		if (enable == 1) begin
			case (select)
			3'b000 : {v,accumulator} <= accumulator + in;
			3'b001 : {v,accumulator} <= accumulator - ((~in) + 1);
			3'b010 : {v,accumulator} <= accumulator + 1'b1;
			3'b011 : {v,accumulator} <= accumulator - 1'b1;


			3'b110 : accumulator <= in;
			3'b111 : accumulator <= accumulator;
			endcase
		end
	end
	

	assign out = select[2] ? accumulator : 16'hZZ;
	
endmodule