data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:34: Little bit endian vector: MSB < LSB of bit range: 0:9\ninput [0:9] chany_bottom_in;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:36: Little bit endian vector: MSB < LSB of bit range: 0:9\ninput [0:9] chany_top_in;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:40: Little bit endian vector: MSB < LSB of bit range: 0:9\noutput [0:9] chany_bottom_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:42: Little bit endian vector: MSB < LSB of bit range: 0:9\noutput [0:9] chany_top_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:68: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_0_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:69: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_0_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:70: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_1_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:71: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_1_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:72: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_2_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:73: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_2_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:74: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_3_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:75: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_3_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:76: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_4_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:77: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_4_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:78: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_5_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:79: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_5_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:80: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_6_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:81: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_6_sram_inv;\n     ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:174: Cannot find file containing module: \'mux_2level_tapbuf_size4\'\n mux_2level_tapbuf_size4 mux_left_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing,data/full_repos/permissive/137416811/mux_2level_tapbuf_size4\n             data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing,data/full_repos/permissive/137416811/mux_2level_tapbuf_size4.v\n             data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing,data/full_repos/permissive/137416811/mux_2level_tapbuf_size4.sv\n             mux_2level_tapbuf_size4\n             mux_2level_tapbuf_size4.v\n             mux_2level_tapbuf_size4.sv\n             obj_dir/mux_2level_tapbuf_size4\n             obj_dir/mux_2level_tapbuf_size4.v\n             obj_dir/mux_2level_tapbuf_size4.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:180: Cannot find file containing module: \'mux_2level_tapbuf_size4\'\n mux_2level_tapbuf_size4 mux_right_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:186: Cannot find file containing module: \'mux_2level_tapbuf_size4\'\n mux_2level_tapbuf_size4 mux_right_ipin_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:192: Cannot find file containing module: \'mux_2level_tapbuf_size4\'\n mux_2level_tapbuf_size4 mux_right_ipin_2 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:198: Cannot find file containing module: \'mux_2level_tapbuf_size4\'\n mux_2level_tapbuf_size4 mux_right_ipin_3 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:204: Cannot find file containing module: \'mux_2level_tapbuf_size4\'\n mux_2level_tapbuf_size4 mux_right_ipin_4 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:210: Cannot find file containing module: \'mux_2level_tapbuf_size4\'\n mux_2level_tapbuf_size4 mux_right_ipin_5 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:216: Cannot find file containing module: \'mux_2level_tapbuf_size4_mem\'\n mux_2level_tapbuf_size4_mem mem_left_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:224: Cannot find file containing module: \'mux_2level_tapbuf_size4_mem\'\n mux_2level_tapbuf_size4_mem mem_right_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:232: Cannot find file containing module: \'mux_2level_tapbuf_size4_mem\'\n mux_2level_tapbuf_size4_mem mem_right_ipin_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:240: Cannot find file containing module: \'mux_2level_tapbuf_size4_mem\'\n mux_2level_tapbuf_size4_mem mem_right_ipin_2 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:248: Cannot find file containing module: \'mux_2level_tapbuf_size4_mem\'\n mux_2level_tapbuf_size4_mem mem_right_ipin_3 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:256: Cannot find file containing module: \'mux_2level_tapbuf_size4_mem\'\n mux_2level_tapbuf_size4_mem mem_right_ipin_4 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v:264: Cannot find file containing module: \'mux_2level_tapbuf_size4_mem\'\n mux_2level_tapbuf_size4_mem mem_right_ipin_5 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s), 18 warning(s)\n'
module cby_1__1_(pReset,
                 prog_clk,
                 chany_bottom_in,
                 chany_top_in,
                 ccff_head,
                 chany_bottom_out,
                 chany_top_out,
                 right_grid_left_width_0_height_0_subtile_0__pin_clk_0_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_0_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_1_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_2_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_3_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_4_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_5_,
                 ccff_tail);

input [0:0] pReset;

input [0:0] prog_clk;

input [0:9] chany_bottom_in;

input [0:9] chany_top_in;

input [0:0] ccff_head;

output [0:9] chany_bottom_out;

output [0:9] chany_top_out;

output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_clk_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_1_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_2_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_3_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_4_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_5_;

output [0:0] ccff_tail;









wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_2_sram;
wire [0:5] mux_2level_tapbuf_size4_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_3_sram;
wire [0:5] mux_2level_tapbuf_size4_3_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_4_sram;
wire [0:5] mux_2level_tapbuf_size4_4_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_5_sram;
wire [0:5] mux_2level_tapbuf_size4_5_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_6_sram;
wire [0:5] mux_2level_tapbuf_size4_6_sram_inv;
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail;





	assign chany_top_out[0] = chany_bottom_in[0];



	assign chany_top_out[1] = chany_bottom_in[1];



	assign chany_top_out[2] = chany_bottom_in[2];



	assign chany_top_out[3] = chany_bottom_in[3];



	assign chany_top_out[4] = chany_bottom_in[4];



	assign chany_top_out[5] = chany_bottom_in[5];



	assign chany_top_out[6] = chany_bottom_in[6];



	assign chany_top_out[7] = chany_bottom_in[7];



	assign chany_top_out[8] = chany_bottom_in[8];



	assign chany_top_out[9] = chany_bottom_in[9];



	assign chany_bottom_out[0] = chany_top_in[0];



	assign chany_bottom_out[1] = chany_top_in[1];



	assign chany_bottom_out[2] = chany_top_in[2];



	assign chany_bottom_out[3] = chany_top_in[3];



	assign chany_bottom_out[4] = chany_top_in[4];



	assign chany_bottom_out[5] = chany_top_in[5];



	assign chany_bottom_out[6] = chany_top_in[6];



	assign chany_bottom_out[7] = chany_top_in[7];



	assign chany_bottom_out[8] = chany_top_in[8];



	assign chany_bottom_out[9] = chany_top_in[9];




	mux_2level_tapbuf_size4 mux_left_ipin_0 (
		.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
		.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
		.out(right_grid_left_width_0_height_0_subtile_0__pin_clk_0_));

	mux_2level_tapbuf_size4 mux_right_ipin_0 (
		.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
		.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_0_));

	mux_2level_tapbuf_size4 mux_right_ipin_1 (
		.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
		.sram(mux_2level_tapbuf_size4_2_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_2_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_1_));

	mux_2level_tapbuf_size4 mux_right_ipin_2 (
		.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
		.sram(mux_2level_tapbuf_size4_3_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_3_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_2_));

	mux_2level_tapbuf_size4 mux_right_ipin_3 (
		.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[9], chany_top_in[9]}),
		.sram(mux_2level_tapbuf_size4_4_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_4_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_3_));

	mux_2level_tapbuf_size4 mux_right_ipin_4 (
		.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
		.sram(mux_2level_tapbuf_size4_5_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_5_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_4_));

	mux_2level_tapbuf_size4 mux_right_ipin_5 (
		.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
		.sram(mux_2level_tapbuf_size4_6_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_6_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_5_));

	mux_2level_tapbuf_size4_mem mem_left_ipin_0 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(ccff_head),
		.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_0 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail),
		.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_1 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail),
		.ccff_tail(mux_2level_tapbuf_size4_mem_2_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_2_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_2_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_2 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_2_ccff_tail),
		.ccff_tail(mux_2level_tapbuf_size4_mem_3_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_3_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_3_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_3 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_3_ccff_tail),
		.ccff_tail(mux_2level_tapbuf_size4_mem_4_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_4_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_4_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_4 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_4_ccff_tail),
		.ccff_tail(mux_2level_tapbuf_size4_mem_5_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_5_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_5_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_5 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_5_ccff_tail),
		.ccff_tail(ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_6_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_6_sram_inv[0:5]));

endmodule
module cby_1__1_(pReset,
                 prog_clk,
                 chany_bottom_in,
                 chany_top_in,
                 ccff_head,
                 chany_bottom_out,
                 chany_top_out,
                 right_grid_left_width_0_height_0_subtile_0__pin_clk_0_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_0_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_1_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_2_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_3_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_4_,
                 left_grid_right_width_0_height_0_subtile_0__pin_I_5_,
                 ccff_tail);


input [0:0] pReset;

input [0:0] prog_clk;

input [0:9] chany_bottom_in;

input [0:9] chany_top_in;

input [0:0] ccff_head;

output [0:9] chany_bottom_out;

output [0:9] chany_top_out;

output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_clk_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_0_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_1_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_2_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_3_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_4_;

output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_5_;

output [0:0] ccff_tail;









wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_2_sram;
wire [0:5] mux_2level_tapbuf_size4_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_3_sram;
wire [0:5] mux_2level_tapbuf_size4_3_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_4_sram;
wire [0:5] mux_2level_tapbuf_size4_4_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_5_sram;
wire [0:5] mux_2level_tapbuf_size4_5_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_6_sram;
wire [0:5] mux_2level_tapbuf_size4_6_sram_inv;
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail;





	assign chany_top_out[0] = chany_bottom_in[0];



	assign chany_top_out[1] = chany_bottom_in[1];



	assign chany_top_out[2] = chany_bottom_in[2];



	assign chany_top_out[3] = chany_bottom_in[3];



	assign chany_top_out[4] = chany_bottom_in[4];



	assign chany_top_out[5] = chany_bottom_in[5];



	assign chany_top_out[6] = chany_bottom_in[6];



	assign chany_top_out[7] = chany_bottom_in[7];



	assign chany_top_out[8] = chany_bottom_in[8];



	assign chany_top_out[9] = chany_bottom_in[9];



	assign chany_bottom_out[0] = chany_top_in[0];



	assign chany_bottom_out[1] = chany_top_in[1];



	assign chany_bottom_out[2] = chany_top_in[2];



	assign chany_bottom_out[3] = chany_top_in[3];



	assign chany_bottom_out[4] = chany_top_in[4];



	assign chany_bottom_out[5] = chany_top_in[5];



	assign chany_bottom_out[6] = chany_top_in[6];



	assign chany_bottom_out[7] = chany_top_in[7];



	assign chany_bottom_out[8] = chany_top_in[8];



	assign chany_bottom_out[9] = chany_top_in[9];




	mux_2level_tapbuf_size4 mux_left_ipin_0 (
		.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
		.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
		.out(right_grid_left_width_0_height_0_subtile_0__pin_clk_0_));

	mux_2level_tapbuf_size4 mux_right_ipin_0 (
		.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
		.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_0_));

	mux_2level_tapbuf_size4 mux_right_ipin_1 (
		.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
		.sram(mux_2level_tapbuf_size4_2_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_2_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_1_));

	mux_2level_tapbuf_size4 mux_right_ipin_2 (
		.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
		.sram(mux_2level_tapbuf_size4_3_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_3_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_2_));

	mux_2level_tapbuf_size4 mux_right_ipin_3 (
		.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[9], chany_top_in[9]}),
		.sram(mux_2level_tapbuf_size4_4_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_4_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_3_));

	mux_2level_tapbuf_size4 mux_right_ipin_4 (
		.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
		.sram(mux_2level_tapbuf_size4_5_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_5_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_4_));

	mux_2level_tapbuf_size4 mux_right_ipin_5 (
		.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
		.sram(mux_2level_tapbuf_size4_6_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_6_sram_inv[0:5]),
		.out(left_grid_right_width_0_height_0_subtile_0__pin_I_5_));

	mux_2level_tapbuf_size4_mem mem_left_ipin_0 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(ccff_head),
		.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_0 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail),
		.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_1 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail),
		.ccff_tail(mux_2level_tapbuf_size4_mem_2_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_2_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_2_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_2 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_2_ccff_tail),
		.ccff_tail(mux_2level_tapbuf_size4_mem_3_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_3_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_3_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_3 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_3_ccff_tail),
		.ccff_tail(mux_2level_tapbuf_size4_mem_4_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_4_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_4_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_4 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_4_ccff_tail),
		.ccff_tail(mux_2level_tapbuf_size4_mem_5_ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_5_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_5_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_right_ipin_5 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.ccff_head(mux_2level_tapbuf_size4_mem_5_ccff_tail),
		.ccff_tail(ccff_tail),
		.mem_out(mux_2level_tapbuf_size4_6_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_6_sram_inv[0:5]));

endmodule