data/full_repos/permissive/123339956/Homework_Assignment_2/multiplier_8bit.v
 line:19: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/123339956/Homework_Assignment_2/multiplier_8bit.v:12: Unsupported: Ignoring delay on this delayed statement.\n always #10 clock = ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Homework_Assignment_2/multiplier_8bit.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #00 clock = 1\'b0; reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Homework_Assignment_2/multiplier_8bit.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #00 A = 8\'b0000_1111 ; B = 8\'b0000_1111 ; reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Homework_Assignment_2/multiplier_8bit.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #120 $stop ; \n  ^\n%Error: data/full_repos/permissive/123339956/Homework_Assignment_2/multiplier_8bit.v:22: Unsupported or unknown PLI call: $monitor\n initial $monitor("t=%3d, A=%b,B=%b,reset=%b,clock=%b,prod=%b eop=%b",$time,A,B,reset,clock, prod, eop); \n         ^~~~~~~~\n%Error: data/full_repos/permissive/123339956/Homework_Assignment_2/multiplier_8bit.v:26: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("multiplier_8bit.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/123339956/Homework_Assignment_2/multiplier_8bit.v:27: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multiplier_8bit(prod, eop, A, B, clock, reset);

	
	input [7:0] A,B;
	input clock, reset;
	output reg [15:0] prod;
	output reg eop;
	reg [3:0] count;
	reg [7:0] partprod;
	

	always @ (negedge clock or posedge reset)
	begin
		if(reset)
		begin
			prod = 16'b0000_0000_0000_0000;
			count = 0;
			eop = 0;
		end
		else
		begin
			if (count < 4)
			begin
				eop = 0;
				begin
					if (B[count] == 1)
						partprod = A;
					else 
						partprod = 8'b00000000;
				end
				prod = {prod[14:0],1'b0};
				prod = prod + partprod;
				count = count+1;
			end
			else
			begin
				eop = 1;
				count = 0;
			end
		end
	end

endmodule
module multiplier_8bit(prod, eop, A, B, clock, reset);


	
	input [7:0] A,B;
	input clock, reset;
	output reg [15:0] prod;
	output reg eop;
	reg [3:0] count;
	reg [7:0] partprod;
	

	always @ (negedge clock or posedge reset)
	begin
		if(reset)
		begin
			prod = 16'b0000_0000_0000_0000;
			count = 0;
			eop = 0;
		end
		else
		begin
			if (count < 4)
			begin
				eop = 0;
				begin
					if (B[count] == 1)
						partprod = A;
					else 
						partprod = 8'b00000000;
				end
				prod = {prod[14:0],1'b0};
				prod = prod + partprod;
				count = count+1;
			end
			else
			begin
				eop = 1;
				count = 0;
			end
		end
	end

endmodule