data/full_repos/permissive/143278/blif/blif02k_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/blif/blif02k_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #1 ;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/blif/blif02k_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #1 ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/blif/blif02k_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #1 ;\n      ^\n%Error: data/full_repos/permissive/143278/blif/blif02k_tb.v:8: Cannot find file containing module: \'test_mux\'\n   test_mux DUT(.\\S[1] (sel[1]), .\\S[0] (sel[0]),\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/blif,data/full_repos/permissive/143278/test_mux\n             data/full_repos/permissive/143278/blif,data/full_repos/permissive/143278/test_mux.v\n             data/full_repos/permissive/143278/blif,data/full_repos/permissive/143278/test_mux.sv\n             test_mux\n             test_mux.v\n             test_mux.sv\n             obj_dir/test_mux\n             obj_dir/test_mux.v\n             obj_dir/test_mux.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [1:0] D0, D1;
   reg [1:0] sel;
   wire [1:0] Q, R;

   test_mux DUT(.\S[1] (sel[1]), .\S[0] (sel[0]),
		.\D0[1] (D0[1]), .\D0[0] (D0[0]),
		.\D1[1] (D1[1]), .\D1[0] (D1[0]),
		.\Q[1] (Q[1]), .\Q[0] (Q[0]),
		.\R[1] (R[1]), .\R[0] (R[0]));

   initial begin
      D0 = 'b01;
      D1 = 'b10;
      sel = 0;
      #1 ;
      if (Q !== D0) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q);
	 $finish;
      end
      if (R !== D0) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, R=%b", D0, D1, sel, R);
	 $finish;
      end

      sel = 1;
      #1 ;
      if (Q !== D1) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q);
	 $finish;
      end
      if (R !== D1) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, R=%b", D0, D1, sel, R);
	 $finish;
      end

      sel = 2;
      #1 ;
      if (Q !== 'b00) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q);
	 $finish;
      end
      if (R !== 'b00) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, R=%b", D0, D1, sel, R);
	 $finish;
      end
      $display("PASSED");
   end

endmodule
module main;


   reg [1:0] D0, D1;
   reg [1:0] sel;
   wire [1:0] Q, R;

   test_mux DUT(.\S[1] (sel[1]), .\S[0] (sel[0]),
		.\D0[1] (D0[1]), .\D0[0] (D0[0]),
		.\D1[1] (D1[1]), .\D1[0] (D1[0]),
		.\Q[1] (Q[1]), .\Q[0] (Q[0]),
		.\R[1] (R[1]), .\R[0] (R[0]));

   initial begin
      D0 = 'b01;
      D1 = 'b10;
      sel = 0;
      #1 ;
      if (Q !== D0) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q);
	 $finish;
      end
      if (R !== D0) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, R=%b", D0, D1, sel, R);
	 $finish;
      end

      sel = 1;
      #1 ;
      if (Q !== D1) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q);
	 $finish;
      end
      if (R !== D1) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, R=%b", D0, D1, sel, R);
	 $finish;
      end

      sel = 2;
      #1 ;
      if (Q !== 'b00) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q);
	 $finish;
      end
      if (R !== 'b00) begin
	 $display("FAILED -- D0=%b, D1=%b, S=%b, R=%b", D0, D1, sel, R);
	 $finish;
      end
      $display("PASSED");
   end

endmodule