data/full_repos/permissive/219917900/rx_rtl_files/asyncFIFO_glay.v
1: b'%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/asyncFIFO_glay.v:38: Operator AND expects 6 bits on the LHS, but LHS\'s VARREF \'wr_en\' generates 1 bits.\n                                                                                     : ... In instance asyncFIFO_glay\nassign next_wadr = wadr_reg + (wr_en & ~full);      \n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/asyncFIFO_glay.v:38: Operator NOT expects 6 bits on the LHS, but LHS\'s VARREF \'full\' generates 1 bits.\n                                                                                     : ... In instance asyncFIFO_glay\nassign next_wadr = wadr_reg + (wr_en & ~full);      \n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/asyncFIFO_glay.v:70: Operator AND expects 6 bits on the LHS, but LHS\'s VARREF \'rd_en\' generates 1 bits.\n                                                                                     : ... In instance asyncFIFO_glay\nassign next_radr = radr_reg + (rd_en & ~empty);     \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/asyncFIFO_glay.v:70: Operator NOT expects 6 bits on the LHS, but LHS\'s VARREF \'empty\' generates 1 bits.\n                                                                                     : ... In instance asyncFIFO_glay\nassign next_radr = radr_reg + (rd_en & ~empty);     \n                                       ^\n%Error: Exiting due to 4 warning(s)\n'
module asyncFIFO_glay #(parameter WA=5,WD=256)
    (input  rst
    ,input  wr_clk
    ,input  wr_en
    ,input[WD-1:0] din
    ,output reg full
    ,input  rd_clk
    ,input  rd_en
    ,output reg[WD-1:0] dout
    ,output reg empty
    );
reg[WA:0] wadr_reg;
reg[WA:0] radr_reg;
reg[WA:0] wptr_reg,wptr0_reg,wptr1_reg;
reg[WA:0] rptr_reg,rptr0_reg,rptr1_reg;
wire[WA:0] next_wadr,next_wptr;
wire[WA:0] next_radr,next_rptr;
reg[WD-1:0] ram[0:2**WA-1];

always @(posedge wr_clk)
    if(wr_en) ram[wadr_reg[WA-1:0]] <= din;
always @(posedge rd_clk)
    if(rd_en) dout <= ram[radr_reg[WA-1:0]];


always @(posedge wr_clk or posedge rst)
    begin
    if(rst)
        {wadr_reg,wptr_reg} <= {{(WA+1){1'b0}},{(WA+1){1'b0}}};
    else if(wr_en)
        {wadr_reg,wptr_reg} <= {next_wadr, next_wptr};
    end
assign next_wadr = wadr_reg + (wr_en & ~full);
assign next_wptr = next_wadr ^ (next_wadr>>1'b1);

always @(posedge wr_clk or posedge rst)
    begin
    if(rst)
        {rptr1_reg, rptr0_reg} <= {{(WA+1){1'b0}},{(WA+1){1'b0}}};
    else
        {rptr1_reg, rptr0_reg} <= {rptr0_reg, rptr_reg};
    end


always @(posedge wr_clk or posedge rst)
    begin
    if(rst)
        full <= 1'b0;
    else if(next_wptr=={~rptr1_reg[WA:WA-1], rptr1_reg[WA-2:0]})
        full <= 1'b1;
    else
        full <= 1'b0;
    end


always @(posedge rd_clk or posedge rst)
    begin
    if(rst)
        {radr_reg,rptr_reg} <= {{(WA+1){1'b0}},{(WA+1){1'b0}}};
    else if(rd_en)
        {radr_reg,rptr_reg} <= {next_radr, next_rptr};
    end
assign next_radr = radr_reg + (rd_en & ~empty);
assign next_rptr = next_radr ^ (next_radr >> 1);

always @(posedge rd_clk or posedge rst)
    begin
    if(rst)
        {wptr1_reg, wptr0_reg} <= {{(WA+1){1'b0}},{(WA+1){1'b0}}};
    else
        {wptr1_reg, wptr0_reg} <= {wptr0_reg, wptr_reg};
    end


always @(posedge rd_clk or posedge rst)
    begin
    if(rst)
        empty <= 1'b1;
    else if(next_rptr==wptr1_reg)
        empty <= 1'b1;
    else
        empty <= 1'b0;
    end
endmodule
module asyncFIFO_glay #(parameter WA=5,WD=256)
    (input  rst
    ,input  wr_clk
    ,input  wr_en
    ,input[WD-1:0] din
    ,output reg full
    ,input  rd_clk
    ,input  rd_en
    ,output reg[WD-1:0] dout
    ,output reg empty
    );

reg[WA:0] wadr_reg;
reg[WA:0] radr_reg;
reg[WA:0] wptr_reg,wptr0_reg,wptr1_reg;
reg[WA:0] rptr_reg,rptr0_reg,rptr1_reg;
wire[WA:0] next_wadr,next_wptr;
wire[WA:0] next_radr,next_rptr;
reg[WD-1:0] ram[0:2**WA-1];

always @(posedge wr_clk)
    if(wr_en) ram[wadr_reg[WA-1:0]] <= din;
always @(posedge rd_clk)
    if(rd_en) dout <= ram[radr_reg[WA-1:0]];


always @(posedge wr_clk or posedge rst)
    begin
    if(rst)
        {wadr_reg,wptr_reg} <= {{(WA+1){1'b0}},{(WA+1){1'b0}}};
    else if(wr_en)
        {wadr_reg,wptr_reg} <= {next_wadr, next_wptr};
    end
assign next_wadr = wadr_reg + (wr_en & ~full);
assign next_wptr = next_wadr ^ (next_wadr>>1'b1);

always @(posedge wr_clk or posedge rst)
    begin
    if(rst)
        {rptr1_reg, rptr0_reg} <= {{(WA+1){1'b0}},{(WA+1){1'b0}}};
    else
        {rptr1_reg, rptr0_reg} <= {rptr0_reg, rptr_reg};
    end


always @(posedge wr_clk or posedge rst)
    begin
    if(rst)
        full <= 1'b0;
    else if(next_wptr=={~rptr1_reg[WA:WA-1], rptr1_reg[WA-2:0]})
        full <= 1'b1;
    else
        full <= 1'b0;
    end


always @(posedge rd_clk or posedge rst)
    begin
    if(rst)
        {radr_reg,rptr_reg} <= {{(WA+1){1'b0}},{(WA+1){1'b0}}};
    else if(rd_en)
        {radr_reg,rptr_reg} <= {next_radr, next_rptr};
    end
assign next_radr = radr_reg + (rd_en & ~empty);
assign next_rptr = next_radr ^ (next_radr >> 1);

always @(posedge rd_clk or posedge rst)
    begin
    if(rst)
        {wptr1_reg, wptr0_reg} <= {{(WA+1){1'b0}},{(WA+1){1'b0}}};
    else
        {wptr1_reg, wptr0_reg} <= {wptr0_reg, wptr_reg};
    end


always @(posedge rd_clk or posedge rst)
    begin
    if(rst)
        empty <= 1'b1;
    else if(next_rptr==wptr1_reg)
        empty <= 1'b1;
    else
        empty <= 1'b0;
    end
endmodule