data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v
 line:62: before: "="
1: b'%Error: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:31: Cannot find file containing module: \'reset_conditioner_1\'\n  reset_conditioner_1 reset_cond (\n  ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113756623/Max7219YouTube/work/verilog,data/full_repos/permissive/113756623/reset_conditioner_1\n             data/full_repos/permissive/113756623/Max7219YouTube/work/verilog,data/full_repos/permissive/113756623/reset_conditioner_1.v\n             data/full_repos/permissive/113756623/Max7219YouTube/work/verilog,data/full_repos/permissive/113756623/reset_conditioner_1.sv\n             reset_conditioner_1\n             reset_conditioner_1.v\n             reset_conditioner_1.sv\n             obj_dir/reset_conditioner_1\n             obj_dir/reset_conditioner_1.v\n             obj_dir/reset_conditioner_1.sv\n%Error: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:43: Cannot find file containing module: \'max7219_2\'\n  max7219_2 max (\n  ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:63: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance mojo_top_0\n  reg [63:0] M_segments_d, M_segments_q = 1\'h0;\n                                          ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:64: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance mojo_top_0\n  reg [2:0] M_segment_index_d, M_segment_index_q = 1\'h0;\n                                                   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:135: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance mojo_top_0\n        M_segment_index_d = 1\'h0;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:157: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance mojo_top_0\n        max_data = 1\'h0;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:173: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'M_segment_index_q\' generates 3 bits.\n                                                                                                 : ... In instance mojo_top_0\n          max_addr = M_segment_index_q + 1\'h1;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:179: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance mojo_top_0\n          M_segment_index_d = 1\'h0;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:171: Operator LT expects 4 bits on the LHS, but LHS\'s VARREF \'M_segment_index_q\' generates 3 bits.\n                                                                                                 : ... In instance mojo_top_0\n        if (M_segment_index_q < 4\'h8) begin\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:197: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance mojo_top_0\n      M_segments_q <= 1\'h0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:198: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance mojo_top_0\n      M_segment_index_q <= 1\'h0;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219YouTube/work/verilog/mojo_top_0.v:199: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance mojo_top_0\n      M_state_q <= 1\'h0;\n                ^~\n%Error: Exiting due to 2 error(s), 10 warning(s)\n'
module mojo_top_0 (
    input clk,
    input rst_n,
    output reg [7:0] led,
    input cclk,
    output reg spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,
    output reg [3:0] spi_channel,
    input avr_tx,
    output reg avr_rx,
    input avr_rx_busy,
    output reg max7219_load,
    output reg max7219_data,
    output reg max7219_clock
  );
  
  
  
  reg rst;
  
  wire [1-1:0] M_reset_cond_out;
  reg [1-1:0] M_reset_cond_in;
  reset_conditioner_1 reset_cond (
    .clk(clk),
    .in(M_reset_cond_in),
    .out(M_reset_cond_out)
  );
  wire [1-1:0] M_max_cs;
  wire [1-1:0] M_max_dout;
  wire [1-1:0] M_max_sck;
  wire [1-1:0] M_max_busy;
  reg [8-1:0] M_max_addr_in;
  reg [8-1:0] M_max_din;
  reg [1-1:0] M_max_start;
  max7219_2 max (
    .clk(clk),
    .rst(rst),
    .addr_in(M_max_addr_in),
    .din(M_max_din),
    .start(M_max_start),
    .cs(M_max_cs),
    .dout(M_max_dout),
    .sck(M_max_sck),
    .busy(M_max_busy)
  );
  localparam IDLE_state = 3'd0;
  localparam SEND_SHUTDOWN_state = 3'd1;
  localparam SEND_RESET_state = 3'd2;
  localparam SEND_NO_DECODE_state = 3'd3;
  localparam SEND_ALL_DIGITS_state = 3'd4;
  localparam SEND_WORD_state = 3'd5;
  localparam HALT_state = 3'd6;
  
  reg [2:0] M_state_d, M_state_q = IDLE_state;
  reg [63:0] M_segments_d, M_segments_q = 1'h0;
  reg [2:0] M_segment_index_d, M_segment_index_q = 1'h0;
  
  reg [7:0] max_addr;
  
  reg [7:0] max_data;
  
  localparam C0 = 8'h7e;
  
  localparam C1 = 8'h30;
  
  localparam C2 = 8'h6d;
  
  localparam C3 = 8'h79;
  
  localparam C4 = 8'h33;
  
  localparam C5 = 8'h5b;
  
  localparam C6 = 8'h5f;
  
  localparam C7 = 8'h70;
  
  localparam C8 = 8'h7f;
  
  localparam C9 = 8'h7b;
  
  localparam A = 8'h77;
  
  localparam B = 8'h1f;
  
  localparam C = 8'h4e;
  
  localparam D = 8'h3d;
  
  localparam E = 8'h4f;
  
  localparam F = 8'h47;
  
  localparam O = 8'h1d;
  
  localparam R = 8'h05;
  
  localparam MINUS = 8'h40;
  
  localparam BLANK = 8'h00;
  
  always @* begin
    M_state_d = M_state_q;
    M_segments_d = M_segments_q;
    M_segment_index_d = M_segment_index_q;
    
    M_segments_d[56+7-:8] = 8'h3d;
    M_segments_d[48+7-:8] = 8'h4f;
    M_segments_d[40+7-:8] = 8'h77;
    M_segments_d[32+7-:8] = 8'h3d;
    M_segments_d[24+7-:8] = 8'h1f;
    M_segments_d[16+7-:8] = 8'h4f;
    M_segments_d[8+7-:8] = 8'h4f;
    M_segments_d[0+7-:8] = 8'h47;
    M_reset_cond_in = ~rst_n;
    rst = M_reset_cond_out;
    led = 8'h00;
    spi_miso = 1'bz;
    spi_channel = 4'bzzzz;
    avr_rx = 1'bz;
    max_addr = 8'h00;
    max_data = 8'h00;
    M_max_start = 1'h0;
    
    case (M_state_q)
      IDLE_state: begin
        M_segment_index_d = 1'h0;
        M_state_d = SEND_SHUTDOWN_state;
      end
      SEND_SHUTDOWN_state: begin
        M_max_start = 1'h1;
        max_addr = 8'h0c;
        max_data = 8'h00;
        if (M_max_busy != 1'h1) begin
          M_state_d = SEND_RESET_state;
        end
      end
      SEND_RESET_state: begin
        M_max_start = 1'h1;
        max_addr = 8'h0c;
        max_data = 8'h01;
        if (M_max_busy != 1'h1) begin
          M_state_d = SEND_NO_DECODE_state;
        end
      end
      SEND_NO_DECODE_state: begin
        M_max_start = 1'h1;
        max_addr = 8'h09;
        max_data = 1'h0;
        if (M_max_busy != 1'h1) begin
          M_state_d = SEND_ALL_DIGITS_state;
        end
      end
      SEND_ALL_DIGITS_state: begin
        M_max_start = 1'h1;
        max_addr = 8'h0b;
        max_data = 8'h07;
        if (M_max_busy != 1'h1) begin
          M_state_d = SEND_WORD_state;
        end
      end
      SEND_WORD_state: begin
        if (M_segment_index_q < 4'h8) begin
          M_max_start = 1'h1;
          max_addr = M_segment_index_q + 1'h1;
          max_data = M_segments_q[(M_segment_index_q)*8+7-:8];
          if (M_max_busy != 1'h1) begin
            M_segment_index_d = M_segment_index_q + 1'h1;
          end
        end else begin
          M_segment_index_d = 1'h0;
          M_state_d = HALT_state;
        end
      end
      HALT_state: begin
        max_addr = 8'h00;
        max_data = 8'h00;
      end
    endcase
    M_max_addr_in = max_addr;
    M_max_din = max_data;
    max7219_clock = M_max_sck;
    max7219_data = M_max_dout;
    max7219_load = M_max_cs;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_segments_q <= 1'h0;
      M_segment_index_q <= 1'h0;
      M_state_q <= 1'h0;
    end else begin
      M_segments_q <= M_segments_d;
      M_segment_index_q <= M_segment_index_d;
      M_state_q <= M_state_d;
    end
  end
  
endmodule
module mojo_top_0 (
    input clk,
    input rst_n,
    output reg [7:0] led,
    input cclk,
    output reg spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,
    output reg [3:0] spi_channel,
    input avr_tx,
    output reg avr_rx,
    input avr_rx_busy,
    output reg max7219_load,
    output reg max7219_data,
    output reg max7219_clock
  );

  
  
  
  reg rst;
  
  wire [1-1:0] M_reset_cond_out;
  reg [1-1:0] M_reset_cond_in;
  reset_conditioner_1 reset_cond (
    .clk(clk),
    .in(M_reset_cond_in),
    .out(M_reset_cond_out)
  );
  wire [1-1:0] M_max_cs;
  wire [1-1:0] M_max_dout;
  wire [1-1:0] M_max_sck;
  wire [1-1:0] M_max_busy;
  reg [8-1:0] M_max_addr_in;
  reg [8-1:0] M_max_din;
  reg [1-1:0] M_max_start;
  max7219_2 max (
    .clk(clk),
    .rst(rst),
    .addr_in(M_max_addr_in),
    .din(M_max_din),
    .start(M_max_start),
    .cs(M_max_cs),
    .dout(M_max_dout),
    .sck(M_max_sck),
    .busy(M_max_busy)
  );
  localparam IDLE_state = 3'd0;
  localparam SEND_SHUTDOWN_state = 3'd1;
  localparam SEND_RESET_state = 3'd2;
  localparam SEND_NO_DECODE_state = 3'd3;
  localparam SEND_ALL_DIGITS_state = 3'd4;
  localparam SEND_WORD_state = 3'd5;
  localparam HALT_state = 3'd6;
  
  reg [2:0] M_state_d, M_state_q = IDLE_state;
  reg [63:0] M_segments_d, M_segments_q = 1'h0;
  reg [2:0] M_segment_index_d, M_segment_index_q = 1'h0;
  
  reg [7:0] max_addr;
  
  reg [7:0] max_data;
  
  localparam C0 = 8'h7e;
  
  localparam C1 = 8'h30;
  
  localparam C2 = 8'h6d;
  
  localparam C3 = 8'h79;
  
  localparam C4 = 8'h33;
  
  localparam C5 = 8'h5b;
  
  localparam C6 = 8'h5f;
  
  localparam C7 = 8'h70;
  
  localparam C8 = 8'h7f;
  
  localparam C9 = 8'h7b;
  
  localparam A = 8'h77;
  
  localparam B = 8'h1f;
  
  localparam C = 8'h4e;
  
  localparam D = 8'h3d;
  
  localparam E = 8'h4f;
  
  localparam F = 8'h47;
  
  localparam O = 8'h1d;
  
  localparam R = 8'h05;
  
  localparam MINUS = 8'h40;
  
  localparam BLANK = 8'h00;
  
  always @* begin
    M_state_d = M_state_q;
    M_segments_d = M_segments_q;
    M_segment_index_d = M_segment_index_q;
    
    M_segments_d[56+7-:8] = 8'h3d;
    M_segments_d[48+7-:8] = 8'h4f;
    M_segments_d[40+7-:8] = 8'h77;
    M_segments_d[32+7-:8] = 8'h3d;
    M_segments_d[24+7-:8] = 8'h1f;
    M_segments_d[16+7-:8] = 8'h4f;
    M_segments_d[8+7-:8] = 8'h4f;
    M_segments_d[0+7-:8] = 8'h47;
    M_reset_cond_in = ~rst_n;
    rst = M_reset_cond_out;
    led = 8'h00;
    spi_miso = 1'bz;
    spi_channel = 4'bzzzz;
    avr_rx = 1'bz;
    max_addr = 8'h00;
    max_data = 8'h00;
    M_max_start = 1'h0;
    
    case (M_state_q)
      IDLE_state: begin
        M_segment_index_d = 1'h0;
        M_state_d = SEND_SHUTDOWN_state;
      end
      SEND_SHUTDOWN_state: begin
        M_max_start = 1'h1;
        max_addr = 8'h0c;
        max_data = 8'h00;
        if (M_max_busy != 1'h1) begin
          M_state_d = SEND_RESET_state;
        end
      end
      SEND_RESET_state: begin
        M_max_start = 1'h1;
        max_addr = 8'h0c;
        max_data = 8'h01;
        if (M_max_busy != 1'h1) begin
          M_state_d = SEND_NO_DECODE_state;
        end
      end
      SEND_NO_DECODE_state: begin
        M_max_start = 1'h1;
        max_addr = 8'h09;
        max_data = 1'h0;
        if (M_max_busy != 1'h1) begin
          M_state_d = SEND_ALL_DIGITS_state;
        end
      end
      SEND_ALL_DIGITS_state: begin
        M_max_start = 1'h1;
        max_addr = 8'h0b;
        max_data = 8'h07;
        if (M_max_busy != 1'h1) begin
          M_state_d = SEND_WORD_state;
        end
      end
      SEND_WORD_state: begin
        if (M_segment_index_q < 4'h8) begin
          M_max_start = 1'h1;
          max_addr = M_segment_index_q + 1'h1;
          max_data = M_segments_q[(M_segment_index_q)*8+7-:8];
          if (M_max_busy != 1'h1) begin
            M_segment_index_d = M_segment_index_q + 1'h1;
          end
        end else begin
          M_segment_index_d = 1'h0;
          M_state_d = HALT_state;
        end
      end
      HALT_state: begin
        max_addr = 8'h00;
        max_data = 8'h00;
      end
    endcase
    M_max_addr_in = max_addr;
    M_max_din = max_data;
    max7219_clock = M_max_sck;
    max7219_data = M_max_dout;
    max7219_load = M_max_cs;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_segments_q <= 1'h0;
      M_segment_index_q <= 1'h0;
      M_state_q <= 1'h0;
    end else begin
      M_segments_q <= M_segments_d;
      M_segment_index_q <= M_segment_index_d;
      M_state_q <= M_state_d;
    end
  end
  
endmodule