data/full_repos/permissive/106408053/verilog/trigger_adv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n              ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trigsum (term_hits, clock, wrenb, din, hit);
input [31:0] term_hits;
input clock,wrenb,din;
output hit;
wire [7:0] pair_sum;
trigterm_32bit pair (term_hits, clock, wrenb, din, dout_pair, pair_sum);
trigterm_4bit mid0 (pair_sum[3:0], clock, wrenb, dout_pair, dout_mid0, mid0_sum);
trigterm_4bit mid1 (pair_sum[7:4], clock, wrenb, dout_mid0, dout_mid1, mid1_sum);
trigterm_4bit final ({2'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);
endmodule
module trigsum (term_hits, clock, wrenb, din, hit);

input [31:0] term_hits;
input clock,wrenb,din;
output hit;
wire [7:0] pair_sum;
trigterm_32bit pair (term_hits, clock, wrenb, din, dout_pair, pair_sum);
trigterm_4bit mid0 (pair_sum[3:0], clock, wrenb, dout_pair, dout_mid0, mid0_sum);
trigterm_4bit mid1 (pair_sum[7:4], clock, wrenb, dout_mid0, dout_mid1, mid1_sum);
trigterm_4bit final ({2'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);
endmodule