data/full_repos/permissive/189567834/DD_FIR/DD_FIR.srcs/sources_1/imports/vivado_demo/code/multiplier16.v
1: b'%Warning-WIDTH: data/full_repos/permissive/189567834/DD_FIR/DD_FIR.srcs/sources_1/imports/vivado_demo/code/multiplier16.v:37: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 11 bits.\n                                                                                                                            : ... In instance multiplier16\n        out_mantissa=product[20:10];\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module multiplier16(in_a,in_b,out);
    input[15:0] in_a,in_b;
    output[15:0] out;

    reg a_sign,b_sign,out_sign;
    reg[4:0] a_exp,b_exp,out_exp;
    reg[10:0] a_mantissa,b_mantissa;
    reg[9:0] out_mantissa;
    reg[21:0] product;

    assign out[15] = out_sign;
	assign out[14:10] = out_exp;
	assign out[9:0] = out_mantissa[9:0];

    always @(*) begin
        a_sign=in_a[15];
        a_exp=in_a[14:10];
        a_mantissa={1'b1,in_a[9:0]};

        b_sign=in_b[15];
        b_exp=in_b[14:10];
        b_mantissa={1'b1,in_b[9:0]};


        out_sign = a_sign ^ b_sign;
        out_exp = a_exp + b_exp - 15;
        product = a_mantissa * b_mantissa;

    

        if(product[21]==1) begin
            out_exp=out_exp+1;
            product = product >> 1;
        end


        out_mantissa=product[20:10];
        if(product[9]==1) begin
            out_mantissa=out_mantissa+1;
        end
    end
    
endmodule
module multiplier16(in_a,in_b,out);

    input[15:0] in_a,in_b;
    output[15:0] out;

    reg a_sign,b_sign,out_sign;
    reg[4:0] a_exp,b_exp,out_exp;
    reg[10:0] a_mantissa,b_mantissa;
    reg[9:0] out_mantissa;
    reg[21:0] product;

    assign out[15] = out_sign;
	assign out[14:10] = out_exp;
	assign out[9:0] = out_mantissa[9:0];

    always @(*) begin
        a_sign=in_a[15];
        a_exp=in_a[14:10];
        a_mantissa={1'b1,in_a[9:0]};

        b_sign=in_b[15];
        b_exp=in_b[14:10];
        b_mantissa={1'b1,in_b[9:0]};


        out_sign = a_sign ^ b_sign;
        out_exp = a_exp + b_exp - 15;
        product = a_mantissa * b_mantissa;

    

        if(product[21]==1) begin
            out_exp=out_exp+1;
            product = product >> 1;
        end


        out_mantissa=product[20:10];
        if(product[9]==1) begin
            out_mantissa=out_mantissa+1;
        end
    end
    
endmodule