data/full_repos/permissive/134057391/2020_sap/sap-1/rtl/controller.v
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data/verilator_xmls/628415cc-cde8-4027-abaa-dadad9bf6ace.xml
module controller(
    input            clk,
    input            clr,
    input [3:0]      inst,
    output reg [6:1] t,
    output           mar_sel,
    output           lm,
    output           cp,
    output           li,
    output           a_sel,
    output           la,
    output           lb,
    output           su,
    output           lo
    );


    wire         lda, add, sub, out, halt;





    always @(negedge clk)
        if (clr)
            t <= 6'b000000;
        else begin
            if (t == 0)
                t <= 6'b000001;
            else begin
                t[6:2] <= t[5:1];
                t[1] <= t[6];
            end
        end








    assign lm = t[1] ||
                (t[4] && (lda || add || sub));


    assign la = (t[5] && lda) ||
                (t[6] && (add || sub));


    assign a_sel = t[6] && (add || sub);


    assign lb = t[5] && (add || sub);


    assign lo = t[4] && out;










    assign lda = (inst == 4'b0000);
    assign add = (inst == 4'b0001);
    assign sub = (inst == 4'b0010);
    assign out = (inst == 4'b1110);
    assign halt = (inst == 4'b1111);


    assign cp = t[2];
    assign li = t[3];
    assign mar_sel = t[4];


    assign su = sub;

endmodule
module controller(
    input            clk,
    input            clr,
    input [3:0]      inst,
    output reg [6:1] t,
    output           mar_sel,
    output           lm,
    output           cp,
    output           li,
    output           a_sel,
    output           la,
    output           lb,
    output           su,
    output           lo
    );



    wire         lda, add, sub, out, halt;





    always @(negedge clk)
        if (clr)
            t <= 6'b000000;
        else begin
            if (t == 0)
                t <= 6'b000001;
            else begin
                t[6:2] <= t[5:1];
                t[1] <= t[6];
            end
        end








    assign lm = t[1] ||
                (t[4] && (lda || add || sub));


    assign la = (t[5] && lda) ||
                (t[6] && (add || sub));


    assign a_sel = t[6] && (add || sub);


    assign lb = t[5] && (add || sub);


    assign lo = t[4] && out;










    assign lda = (inst == 4'b0000);
    assign add = (inst == 4'b0001);
    assign sub = (inst == 4'b0010);
    assign out = (inst == 4'b1110);
    assign halt = (inst == 4'b1111);


    assign cp = t[2];
    assign li = t[3];
    assign mar_sel = t[4];


    assign su = sub;

endmodule