data/full_repos/permissive/169526487/verilog-codes/array-multiplication.v
data/verilator_xmls/ad8e1edd-5799-49ba-8456-da96c37ad30f.xml
module and1(input x, input y,
output wire w);

assign w=x*y;
endmodule
module and1(input x, input y,
output wire w);


assign w=x*y;
endmodule