data/full_repos/permissive/202905213/src_v/ftdi_sync.v
data/verilator_xmls/b8c21618-206f-459e-aaaf-0c0cbe94e227.xml
module ftdi_sync
(

     input           clk_i
    ,input           rst_i
    ,input           ftdi_rxf_i
    ,input           ftdi_txe_i
    ,input  [  7:0]  ftdi_data_in_i
    ,input           inport_valid_i
    ,input  [  7:0]  inport_data_i
    ,input           outport_accept_i


    ,output          ftdi_siwua_o
    ,output          ftdi_wrn_o
    ,output          ftdi_rdn_o
    ,output          ftdi_oen_o
    ,output [  7:0]  ftdi_data_out_o
    ,output          inport_accept_o
    ,output          outport_valid_o
    ,output [  7:0]  outport_data_o
);







wire [7:0] tx_data_w;
wire       tx_valid_w;
wire       tx_accept_w;
wire [6:0] tx_level_w;

ftdi_fifo
#(
    .WIDTH(8),
    .DEPTH(64),
    .ADDR_W(6),
    .COUNT_W(7)
)
u_fifo_out
(
    .clk_i(clk_i),
    .rst_i(rst_i),

    .push_i(inport_valid_i),
    .data_in_i(inport_data_i),
    .accept_o(inport_accept_o),

    .valid_o(tx_valid_w),
    .data_out_o(tx_data_w),
    .pop_i(tx_accept_w),
    .level_o(tx_level_w)
);

wire tx_empty_next_w = (tx_level_w <= 7'd1);




wire [7:0] rx_data_w  = ftdi_data_in_i;
wire       rx_valid_w = !ftdi_rdn_o && !ftdi_rxf_i;
wire       rx_accept_w;
wire [6:0] rx_level_w;

ftdi_fifo
#(
    .WIDTH(8),
    .DEPTH(64),
    .ADDR_W(6),
    .COUNT_W(7)
)
u_fifo_in
(
    .clk_i(clk_i),
    .rst_i(rst_i),

    .push_i(rx_valid_w),
    .data_in_i(rx_data_w),
    .accept_o(rx_accept_w),

    .valid_o(outport_valid_o),
    .data_out_o(outport_data_o),
    .pop_i(outport_accept_i),
    .level_o(rx_level_w)
);

wire rx_full_next_w = (rx_level_w >= 7'd63);




localparam STATE_W           = 2;
localparam STATE_IDLE        = 2'd0;
localparam STATE_TX          = 2'd1;
localparam STATE_RX          = 2'd2;
reg [STATE_W-1:0] state_q;

wire rx_space_w = rx_accept_w;
wire rx_ready_w = !ftdi_rxf_i;
wire tx_space_w = !ftdi_txe_i;

reg  tx_valid_q;
assign tx_accept_w = !tx_valid_q || (state_q == STATE_TX && tx_space_w);

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    tx_valid_q   <= 1'b0;
else if (tx_accept_w)
    tx_valid_q   <= tx_valid_w;




reg [STATE_W-1:0] next_state_r;
always @ *
begin
    next_state_r = state_q;

    case (state_q)



    STATE_IDLE :
    begin
        if (rx_ready_w && rx_space_w)
            next_state_r    = STATE_RX;
        else if (tx_space_w && (tx_valid_w || tx_valid_q))
            next_state_r    = STATE_TX;
    end



    STATE_RX :
    begin
        if (!rx_ready_w || rx_full_next_w)
            next_state_r  = STATE_IDLE;
    end



    STATE_TX :
    begin
        if (!tx_space_w || tx_empty_next_w)
            next_state_r  = STATE_IDLE;
    end    
    default:
        ;
   endcase
end


always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    state_q   <= STATE_IDLE;
else
    state_q   <= next_state_r;










reg       rdn_q;
reg       wrn_q;
reg       oen_q;
reg [7:0] data_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    oen_q   <= 1'b1;
else if (state_q == STATE_IDLE && next_state_r == STATE_RX)
    oen_q   <= 1'b0;
else if (state_q == STATE_RX && next_state_r == STATE_IDLE)
    oen_q   <= 1'b1;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    rdn_q   <= 1'b1;
else if (state_q == STATE_IDLE && next_state_r == STATE_RX)
    rdn_q   <= 1'b0;
else if (state_q == STATE_RX && next_state_r == STATE_IDLE)
    rdn_q   <= 1'b1;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    wrn_q   <= 1'b1;
else if (state_q == STATE_IDLE && next_state_r == STATE_TX)
    wrn_q   <= 1'b0;
else if (state_q == STATE_TX && next_state_r == STATE_IDLE)
    wrn_q   <= 1'b1;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    data_q  <= 8'b0;
else if (tx_accept_w)
    data_q  <= tx_data_w;

assign ftdi_wrn_o      = wrn_q;
assign ftdi_rdn_o      = rdn_q;
assign ftdi_oen_o      = oen_q;
assign ftdi_data_out_o = data_q;
assign ftdi_siwua_o    = 1'b1;

endmodule
module ftdi_sync
(

     input           clk_i
    ,input           rst_i
    ,input           ftdi_rxf_i
    ,input           ftdi_txe_i
    ,input  [  7:0]  ftdi_data_in_i
    ,input           inport_valid_i
    ,input  [  7:0]  inport_data_i
    ,input           outport_accept_i


    ,output          ftdi_siwua_o
    ,output          ftdi_wrn_o
    ,output          ftdi_rdn_o
    ,output          ftdi_oen_o
    ,output [  7:0]  ftdi_data_out_o
    ,output          inport_accept_o
    ,output          outport_valid_o
    ,output [  7:0]  outport_data_o
);








wire [7:0] tx_data_w;
wire       tx_valid_w;
wire       tx_accept_w;
wire [6:0] tx_level_w;

ftdi_fifo
#(
    .WIDTH(8),
    .DEPTH(64),
    .ADDR_W(6),
    .COUNT_W(7)
)
u_fifo_out
(
    .clk_i(clk_i),
    .rst_i(rst_i),

    .push_i(inport_valid_i),
    .data_in_i(inport_data_i),
    .accept_o(inport_accept_o),

    .valid_o(tx_valid_w),
    .data_out_o(tx_data_w),
    .pop_i(tx_accept_w),
    .level_o(tx_level_w)
);

wire tx_empty_next_w = (tx_level_w <= 7'd1);




wire [7:0] rx_data_w  = ftdi_data_in_i;
wire       rx_valid_w = !ftdi_rdn_o && !ftdi_rxf_i;
wire       rx_accept_w;
wire [6:0] rx_level_w;

ftdi_fifo
#(
    .WIDTH(8),
    .DEPTH(64),
    .ADDR_W(6),
    .COUNT_W(7)
)
u_fifo_in
(
    .clk_i(clk_i),
    .rst_i(rst_i),

    .push_i(rx_valid_w),
    .data_in_i(rx_data_w),
    .accept_o(rx_accept_w),

    .valid_o(outport_valid_o),
    .data_out_o(outport_data_o),
    .pop_i(outport_accept_i),
    .level_o(rx_level_w)
);

wire rx_full_next_w = (rx_level_w >= 7'd63);




localparam STATE_W           = 2;
localparam STATE_IDLE        = 2'd0;
localparam STATE_TX          = 2'd1;
localparam STATE_RX          = 2'd2;
reg [STATE_W-1:0] state_q;

wire rx_space_w = rx_accept_w;
wire rx_ready_w = !ftdi_rxf_i;
wire tx_space_w = !ftdi_txe_i;

reg  tx_valid_q;
assign tx_accept_w = !tx_valid_q || (state_q == STATE_TX && tx_space_w);

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    tx_valid_q   <= 1'b0;
else if (tx_accept_w)
    tx_valid_q   <= tx_valid_w;




reg [STATE_W-1:0] next_state_r;
always @ *
begin
    next_state_r = state_q;

    case (state_q)



    STATE_IDLE :
    begin
        if (rx_ready_w && rx_space_w)
            next_state_r    = STATE_RX;
        else if (tx_space_w && (tx_valid_w || tx_valid_q))
            next_state_r    = STATE_TX;
    end



    STATE_RX :
    begin
        if (!rx_ready_w || rx_full_next_w)
            next_state_r  = STATE_IDLE;
    end



    STATE_TX :
    begin
        if (!tx_space_w || tx_empty_next_w)
            next_state_r  = STATE_IDLE;
    end    
    default:
        ;
   endcase
end


always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    state_q   <= STATE_IDLE;
else
    state_q   <= next_state_r;










reg       rdn_q;
reg       wrn_q;
reg       oen_q;
reg [7:0] data_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    oen_q   <= 1'b1;
else if (state_q == STATE_IDLE && next_state_r == STATE_RX)
    oen_q   <= 1'b0;
else if (state_q == STATE_RX && next_state_r == STATE_IDLE)
    oen_q   <= 1'b1;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    rdn_q   <= 1'b1;
else if (state_q == STATE_IDLE && next_state_r == STATE_RX)
    rdn_q   <= 1'b0;
else if (state_q == STATE_RX && next_state_r == STATE_IDLE)
    rdn_q   <= 1'b1;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    wrn_q   <= 1'b1;
else if (state_q == STATE_IDLE && next_state_r == STATE_TX)
    wrn_q   <= 1'b0;
else if (state_q == STATE_TX && next_state_r == STATE_IDLE)
    wrn_q   <= 1'b1;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    data_q  <= 8'b0;
else if (tx_accept_w)
    data_q  <= tx_data_w;

assign ftdi_wrn_o      = wrn_q;
assign ftdi_rdn_o      = rdn_q;
assign ftdi_oen_o      = oen_q;
assign ftdi_data_out_o = data_q;
assign ftdi_siwua_o    = 1'b1;

endmodule