data/full_repos/permissive/123690745/IM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/123690745/IM.v:35: Operator SUB expects 32 bits on the LHS, but LHS\'s SEL generates 11 bits.\n                                                            : ... In instance IM\n assign AddrTrans = Address[12:2]-(32\'h00000c00);\n                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/123690745/IM.v:35: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                            : ... In instance IM\n assign AddrTrans = Address[12:2]-(32\'h00000c00);\n                  ^\n%Error: Exiting due to 2 warning(s)\n'
module IM(
    input [31:0] Address,
    output [31:0] Instruction
    );
	 reg [31:0] Memory[2047:0];
	 wire [10:0] AddrTrans;
	 integer i;
	initial begin
		for (i = 0; i<= 2047; i = i+1) begin
			Memory[i] = 0;
		end
		$readmemh("code/1code.txt", Memory);
		$readmemh("1codeExc.txt", Memory, 32'h00000460, 32'h000007ff);
	end
	assign AddrTrans = Address[12:2]-(32'h00000c00);
	assign Instruction = Memory[AddrTrans];
endmodule
module IM(
    input [31:0] Address,
    output [31:0] Instruction
    );

	 reg [31:0] Memory[2047:0];
	 wire [10:0] AddrTrans;
	 integer i;
	initial begin
		for (i = 0; i<= 2047; i = i+1) begin
			Memory[i] = 0;
		end
		$readmemh("code/1code.txt", Memory);
		$readmemh("1codeExc.txt", Memory, 32'h00000460, 32'h000007ff);
	end
	assign AddrTrans = Address[12:2]-(32'h00000c00);
	assign Instruction = Memory[AddrTrans];
endmodule