data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v
1: b'%Error: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:14: Unsupported or unknown PLI call: $monitor\n$monitor ($time, "inp1 = %b \\t inp2 = %b \\t inp3 = %b \\t inp4 = %b \\t inp5 = %b \\t inp6 = %b \\t answerp = %b \\t",inp1[3:0],inp2[3:0],inp3[3:0],inp4[3:0],inp5[3:0],inp6[3:0],answerp[5:0]);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:204: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:218: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:225: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6_tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: Exiting due to 1 error(s), 32 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Top_tb;
reg [3:0] inp1;
reg [3:0] inp2;
reg [3:0] inp3;
reg [3:0] inp4;
reg [3:0] inp5;
reg [3:0] inp6;
wire [5:0] answerp;
Top Toptestbench (inp1 [3:0],inp2 [3:0],inp3 [3:0],inp4 [3:0],inp5 [3:0],inp6 [3:0],answerp [5:0]);

initial 
begin
$monitor ($time, "inp1 = %b \t inp2 = %b \t inp3 = %b \t inp4 = %b \t inp5 = %b \t inp6 = %b \t answerp = %b \t",inp1[3:0],inp2[3:0],inp3[3:0],inp4[3:0],inp5[3:0],inp6[3:0],answerp[5:0]);
#5;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0001;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0001;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0001;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0001;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0001;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0001;
#50;
inp1[3:0] = 4'b1111;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b1111;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b1111;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b1111;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b1111;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b1111;
#50;
inp1[3:0] = 4'b0111;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0111;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0111;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0111;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0111;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0111;
#50;
inp1[3:0] = 4'b1000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b1000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b1000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b1000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b1000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b1000;
#50;
inp1[3:0] = 4'b0001;
inp2[3:0] = 4'b0001;
inp3[3:0] = 4'b0001;
inp4[3:0] = 4'b0001;
inp5[3:0] = 4'b0001;
inp6[3:0] = 4'b0001;
#50;
inp1[3:0] = 4'b1111;
inp2[3:0] = 4'b1111;
inp3[3:0] = 4'b1111;
inp4[3:0] = 4'b1111;
inp5[3:0] = 4'b1111;
inp6[3:0] = 4'b1111;
#50;
inp1[3:0] = 4'b0001;
inp2[3:0] = 4'b0010;
inp3[3:0] = 4'b0011;
inp4[3:0] = 4'b0100;
inp5[3:0] = 4'b0101;
inp6[3:0] = 4'b0110;
#50;
inp1[3:0] = 4'b0110;
inp2[3:0] = 4'b0101;
inp3[3:0] = 4'b0101;
inp4[3:0] = 4'b0101;
inp5[3:0] = 4'b0101;
inp6[3:0] = 4'b0101;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b1001;
inp2[3:0] = 4'b1011;
inp3[3:0] = 4'b1011;
inp4[3:0] = 4'b1011;
inp5[3:0] = 4'b1011;
inp6[3:0] = 4'b1011;
#100;
end
endmodule
module Top_tb;

reg [3:0] inp1;
reg [3:0] inp2;
reg [3:0] inp3;
reg [3:0] inp4;
reg [3:0] inp5;
reg [3:0] inp6;
wire [5:0] answerp;
Top Toptestbench (inp1 [3:0],inp2 [3:0],inp3 [3:0],inp4 [3:0],inp5 [3:0],inp6 [3:0],answerp [5:0]);

initial 
begin
$monitor ($time, "inp1 = %b \t inp2 = %b \t inp3 = %b \t inp4 = %b \t inp5 = %b \t inp6 = %b \t answerp = %b \t",inp1[3:0],inp2[3:0],inp3[3:0],inp4[3:0],inp5[3:0],inp6[3:0],answerp[5:0]);
#5;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0001;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0001;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0001;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0001;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0001;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0001;
#50;
inp1[3:0] = 4'b1111;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b1111;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b1111;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b1111;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b1111;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b1111;
#50;
inp1[3:0] = 4'b0111;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0111;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0111;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0111;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0111;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0111;
#50;
inp1[3:0] = 4'b1000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b1000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b1000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b1000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b1000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b1000;
#50;
inp1[3:0] = 4'b0001;
inp2[3:0] = 4'b0001;
inp3[3:0] = 4'b0001;
inp4[3:0] = 4'b0001;
inp5[3:0] = 4'b0001;
inp6[3:0] = 4'b0001;
#50;
inp1[3:0] = 4'b1111;
inp2[3:0] = 4'b1111;
inp3[3:0] = 4'b1111;
inp4[3:0] = 4'b1111;
inp5[3:0] = 4'b1111;
inp6[3:0] = 4'b1111;
#50;
inp1[3:0] = 4'b0001;
inp2[3:0] = 4'b0010;
inp3[3:0] = 4'b0011;
inp4[3:0] = 4'b0100;
inp5[3:0] = 4'b0101;
inp6[3:0] = 4'b0110;
#50;
inp1[3:0] = 4'b0110;
inp2[3:0] = 4'b0101;
inp3[3:0] = 4'b0101;
inp4[3:0] = 4'b0101;
inp5[3:0] = 4'b0101;
inp6[3:0] = 4'b0101;
#50;
inp1[3:0] = 4'b0000;
inp2[3:0] = 4'b0000;
inp3[3:0] = 4'b0000;
inp4[3:0] = 4'b0000;
inp5[3:0] = 4'b0000;
inp6[3:0] = 4'b0000;
#50;
inp1[3:0] = 4'b1001;
inp2[3:0] = 4'b1011;
inp3[3:0] = 4'b1011;
inp4[3:0] = 4'b1011;
inp5[3:0] = 4'b1011;
inp6[3:0] = 4'b1011;
#100;
end
endmodule