data/full_repos/permissive/175063152/ip/securePUF_1.0/src/rtl/mapping.v
1: b"%Error: data/full_repos/permissive/175063152/ip/securePUF_1.0/src/rtl/mapping.v:49: Cannot find file containing module: 'pufInputNetwork'\n pufInputNetwork #(.Width(CHALLENGE_WIDTH))\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175063152/ip/securePUF_1.0/src/rtl,data/full_repos/permissive/175063152/pufInputNetwork\n             data/full_repos/permissive/175063152/ip/securePUF_1.0/src/rtl,data/full_repos/permissive/175063152/pufInputNetwork.v\n             data/full_repos/permissive/175063152/ip/securePUF_1.0/src/rtl,data/full_repos/permissive/175063152/pufInputNetwork.sv\n             pufInputNetwork\n             pufInputNetwork.v\n             pufInputNetwork.sv\n             obj_dir/pufInputNetwork\n             obj_dir/pufInputNetwork.v\n             obj_dir/pufInputNetwork.sv\n%Error: data/full_repos/permissive/175063152/ip/securePUF_1.0/src/rtl/mapping.v:58: Cannot find file containing module: 'pufInterconNetwork'\n pufInterconNetwork picn (\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175063152/ip/securePUF_1.0/src/rtl/mapping.v:68: Cannot find file containing module: 'pufOutputNetwork'\n pufOutputNetwork pon (\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module mapping #(
	parameter CHALLENGE_WIDTH = 32,
	parameter PDL_CONFIG_WIDTH = 128,
	parameter RESPONSE_WIDTH = 6
)(
	input wire clk,
	input wire reset,
	input wire trigger,
	input wire [CHALLENGE_WIDTH-1:0] challenge,
	input wire [PDL_CONFIG_WIDTH-1:0] pdl_config,
	output reg done,
	output wire [RESPONSE_WIDTH-1:0] raw_response,
	output wire xor_response
	);


	localparam IDLE = 0;
	localparam COMPUTE = 1;
	

	reg mp_state;
	

	wire [CHALLENGE_WIDTH-1:0] actual_challenge;

	

	
	(* KEEP_HIERARCHY="TRUE" *)
	pufInputNetwork #(.Width(CHALLENGE_WIDTH))
					pin(
						.dataIn(challenge[CHALLENGE_WIDTH-1:0]),
						.dataOut(actual_challenge[CHALLENGE_WIDTH-1:0])
					);
					
					

	(* KEEP_HIERARCHY="TRUE" *)
	pufInterconNetwork picn (
						.CHALLENGE(actual_challenge[CHALLENGE_WIDTH-1:0]),
						.PDL_CONFIG(pdl_config[PDL_CONFIG_WIDTH-1:0]),
						.RESPONSE(raw_response),
						.trigger(trigger),
						.reset(reset)
						);
						

	(* KEEP_HIERARCHY="TRUE" *)
	pufOutputNetwork pon (
						.response(raw_response),
						.xor_response(xor_response)
						);

endmodule
module mapping #(
	parameter CHALLENGE_WIDTH = 32,
	parameter PDL_CONFIG_WIDTH = 128,
	parameter RESPONSE_WIDTH = 6
)(
	input wire clk,
	input wire reset,
	input wire trigger,
	input wire [CHALLENGE_WIDTH-1:0] challenge,
	input wire [PDL_CONFIG_WIDTH-1:0] pdl_config,
	output reg done,
	output wire [RESPONSE_WIDTH-1:0] raw_response,
	output wire xor_response
	);



	localparam IDLE = 0;
	localparam COMPUTE = 1;
	

	reg mp_state;
	

	wire [CHALLENGE_WIDTH-1:0] actual_challenge;

	

	
	(* KEEP_HIERARCHY="TRUE" *)
	pufInputNetwork #(.Width(CHALLENGE_WIDTH))
					pin(
						.dataIn(challenge[CHALLENGE_WIDTH-1:0]),
						.dataOut(actual_challenge[CHALLENGE_WIDTH-1:0])
					);
					
					

	(* KEEP_HIERARCHY="TRUE" *)
	pufInterconNetwork picn (
						.CHALLENGE(actual_challenge[CHALLENGE_WIDTH-1:0]),
						.PDL_CONFIG(pdl_config[PDL_CONFIG_WIDTH-1:0]),
						.RESPONSE(raw_response),
						.trigger(trigger),
						.reset(reset)
						);
						

	(* KEEP_HIERARCHY="TRUE" *)
	pufOutputNetwork pon (
						.response(raw_response),
						.xor_response(xor_response)
						);

endmodule