data/full_repos/permissive/143278/blif/blif02i.v
data/verilator_xmls/442c4b30-2066-43db-8b60-4c3aff79b366.xml
module cmpN
  #(parameter WID = 4)
   (input wire [WID-1:0] A,
    input wire [WID-1:0] B,
    output reg QE, QN, QGT, QGE
);

   always @(A, B)
     if (A > B)
       QGT = 1;
     else
       QGT = 0;

   always @(A, B)
     if (A >= B)
       QGE = 1;
     else
       QGE = 0;

   always @(A, B)
     if (A == B)
       QE = 1;
     else
       QE = 0;

   always @(A, B)
     if (A != B)
       QN = 1;
     else
       QN = 0;



endmodule
module cmpN
  #(parameter WID = 4)
   (input wire [WID-1:0] A,
    input wire [WID-1:0] B,
    output reg QE, QN, QGT, QGE
);


   always @(A, B)
     if (A > B)
       QGT = 1;
     else
       QGT = 0;

   always @(A, B)
     if (A >= B)
       QGE = 1;
     else
       QGE = 0;

   always @(A, B)
     if (A == B)
       QE = 1;
     else
       QE = 0;

   always @(A, B)
     if (A != B)
       QN = 1;
     else
       QN = 0;



endmodule