data/full_repos/permissive/134057391/2018_cpu/code/testbench/avr_core_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/avr_core_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n     #(1.01*PERIOD) reset = 1\'b0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/avr_core_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2) clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/avr_core_tb.v:55: Cannot find file containing module: \'avr_core\'\n    avr_core DUT (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/avr_core\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/avr_core.v\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/avr_core.sv\n             avr_core\n             avr_core.v\n             avr_core.sv\n             obj_dir/avr_core\n             obj_dir/avr_core.v\n             obj_dir/avr_core.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module avr_core_tb;

    parameter PERIOD = 10;
    parameter PC_WIDTH = 4;

    reg                 clk;
    reg                 reset;
    wire [PC_WIDTH-1:0] pc;
    wire [15:0]         instruction;
    wire  [5:0]         opcode;
    wire  [4:0]         rf1;
    wire  [4:0]         rf2;
    wire  [7:0]         a;
    wire  [7:0]         b;
    wire  [7:0]         sum;
    
	initial begin
        clk = 1'b1;
	    reset = 1'b1;
	    #(1.01*PERIOD) reset = 1'b0;
	end
			
    always begin
        #(PERIOD/2) clk = ~clk;
    end

    avr_core DUT (
        .clk(clk),
        .reset(reset),
        .pc(pc),
        .instruction(instruction),
        .opcode(opcode),
        .rf1(rf1),
        .rf2(rf2),
        .a(a),
        .b(b),
        .sum(sum)
    );

endmodule
module avr_core_tb;


    parameter PERIOD = 10;
    parameter PC_WIDTH = 4;

    reg                 clk;
    reg                 reset;
    wire [PC_WIDTH-1:0] pc;
    wire [15:0]         instruction;
    wire  [5:0]         opcode;
    wire  [4:0]         rf1;
    wire  [4:0]         rf2;
    wire  [7:0]         a;
    wire  [7:0]         b;
    wire  [7:0]         sum;
    
	initial begin
        clk = 1'b1;
	    reset = 1'b1;
	    #(1.01*PERIOD) reset = 1'b0;
	end
			
    always begin
        #(PERIOD/2) clk = ~clk;
    end

    avr_core DUT (
        .clk(clk),
        .reset(reset),
        .pc(pc),
        .instruction(instruction),
        .opcode(opcode),
        .rf1(rf1),
        .rf2(rf2),
        .a(a),
        .b(b),
        .sum(sum)
    );

endmodule