data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v
 line:93: before: "instruction_word"
1: b'%Warning-MULTITOP: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:361: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                           : ... Top module \'SS_ARM\'\nmodule SS_ARM(\n       ^~~~~~\n                                                                                           : ... Top module \'Instruction_Memory\'\nmodule Instruction_Memory(\n       ^~~~~~~~~~~~~~~~~~\n                                                                                           : ... Top module \'Registers\'\nmodule Registers(\n       ^~~~~~~~~\n                                                                                           : ... Top module \'Data_Memory\'\nmodule Data_Memory(\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:288: Operator ASSIGN expects 38 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                                        : ... In instance SS_ARM.mod1\n            immediate_out[63:26] = {64{immediate_out[25]}};\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:291: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s SEL generates 19 bits.\n                                                                                        : ... In instance SS_ARM.mod1\n            immediate_out[19:0] = instruction_in[23:5];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:292: Operator ASSIGN expects 44 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                                        : ... In instance SS_ARM.mod1\n            immediate_out[63:20] = {64{immediate_out[19]}};\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:295: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 9 bits.\n                                                                                        : ... In instance SS_ARM.mod1\n            immediate_out[9:0] = instruction_in[20:12];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:296: Operator ASSIGN expects 54 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                                        : ... In instance SS_ARM.mod1\n            immediate_out[63:10] = {64{immediate_out[9]}};\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:515: Bit extraction of array[31:0] requires 5 bit index, not 64 bits.\n                                                                                        : ... In instance Data_Memory\n            Data[address_in] = data_in;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:519: Bit extraction of array[31:0] requires 5 bit index, not 64 bits.\n                                                                                        : ... In instance Data_Memory\n            Data_out = Data[address_in];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:475: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'initCount\' generates 32 bits.\n                                                                                        : ... In instance Registers\n            Data[initCount] = initCount;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:371: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hf8\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[0] = 8\'hF8;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:372: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h40\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[1] = 8\'h40;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:373: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[2] = 8\'h01;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:374: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h42\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[3] = 8\'h42;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:377: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hf8\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[4] = 8\'hF8;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:378: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h40\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[5] = 8\'h40;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:379: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h11\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[6] = 8\'h11;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:380: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h43\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[7] = 8\'h43;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:383: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hcb\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[8] = 8\'hCB;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:384: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[9] = 8\'h02;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:385: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[10] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:386: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h64\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[11] = 8\'h64;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:389: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h8b\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[12] = 8\'h8B;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:390: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[13] = 8\'h02;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:391: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[14] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:392: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h65\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[15] = 8\'h65;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:395: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hb4\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[16] = 8\'hB4;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:396: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[17] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:397: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[18] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:398: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h41\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[19] = 8\'h41;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:401: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hb4\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[20] = 8\'hB4;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:402: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[21] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:403: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[22] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:404: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h40\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[23] = 8\'h40;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:407: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hf8\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[24] = 8\'hF8;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:408: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h40\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[25] = 8\'h40;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:409: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[26] = 8\'h01;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:410: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h42\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[27] = 8\'h42;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:413: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'haa\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[28] = 8\'hAA;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:414: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[29] = 8\'h03;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:415: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[30] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:416: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h46\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[31] = 8\'h46;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:419: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h8a\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[32] = 8\'h8A;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:420: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[33] = 8\'h03;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:421: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[34] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:422: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h47\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[35] = 8\'h47;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:425: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hf8\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[36] = 8\'hF8;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:426: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[37] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:427: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h10\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[38] = 8\'h10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:428: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'he4\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[39] = 8\'hE4;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:431: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h14\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[40] = 8\'h14;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:432: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[41] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:433: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[42] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:434: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[43] = 8\'h03;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:437: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hf8\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[44] = 8\'hF8;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:438: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h40\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[45] = 8\'h40;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:439: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h11\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[46] = 8\'h11;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:440: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h43\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[47] = 8\'h43;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:443: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h8b\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[48] = 8\'h8B;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:444: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[49] = 8\'h01;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:445: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[50] = 8\'h00;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:446: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h8\' generates 8 bits.\n                                                                                        : ... In instance Instruction_Memory\n        Data[51] = 8\'h08;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:450: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                        : ... In instance Instruction_Memory\n        CPU_Instruction[8:0] = Data[PC+3];\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:451: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                        : ... In instance Instruction_Memory\n        CPU_Instruction[16:8] = Data[PC+2];\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:452: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                        : ... In instance Instruction_Memory\n        CPU_Instruction[24:16] = Data[PC+1];\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:453: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                        : ... In instance Instruction_Memory\n        CPU_Instruction[31:24] = Data[PC];\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/208519918/Single-Cycle-Processor/SS_ARM.v:453: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                        : ... In instance Instruction_Memory\n        CPU_Instruction[31:24] = Data[PC];\n                               ^\n%Error: Exiting due to 66 warning(s)\n'
module Data_Memory(
    input [63:0] address_in,
    input [63:0] data_in,
    input MemRead_control,
    input MemWrite_control,
    output reg [63:0] Data_out
    );
    
    reg [63:0] Data[31:0];
  
    integer initCount;
  
    initial begin
        for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
            Data[initCount] = initCount * 100;
        end
  
        Data[10] = 1540;
        Data[11] = 2117;
    end
  
    always @(address_in, data_in, MemRead_control, MemWrite_control) begin
        if (MemWrite_control == 1) begin
            Data[address_in] = data_in;
        end
  
        if (MemRead_control == 1) begin
            Data_out = Data[address_in];
        end
    end
endmodule
module Data_Memory(
    input [63:0] address_in,
    input [63:0] data_in,
    input MemRead_control,
    input MemWrite_control,
    output reg [63:0] Data_out
    );

    
    reg [63:0] Data[31:0];
  
    integer initCount;
  
    initial begin
        for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
            Data[initCount] = initCount * 100;
        end
  
        Data[10] = 1540;
        Data[11] = 2117;
    end
  
    always @(address_in, data_in, MemRead_control, MemWrite_control) begin
        if (MemWrite_control == 1) begin
            Data[address_in] = data_in;
        end
  
        if (MemRead_control == 1) begin
            Data_out = Data[address_in];
        end
    end
endmodule