data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX V1.00/UART_TX/process.v
1: b'%Error: Cannot find file containing module: V1.00/UART_TX,data/full_repos/permissive/216654561\n        ... Looked in:\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n             V1.00/UART_TX,data/full_repos/permissive/216654561\n             V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX\n%Error: Cannot find file containing module: V1.00/UART_TX/process.v\n%Error: Exiting due to 3 error(s)\n'
module Process(
    input LCR0,
    input LCR1,
    input LCR2,
    input LCR3,
    input LCR4,
    input LCR5,
    input [7:0] data_in,  
    input fifo_empty,
    input clk,
    input reset,
    input tx_ready,
    output reg  fifo_read,
    output reg [8:0] data_out,  
    output reg  [3:0] data_length,
    output reg [1:0] num_stop_bit,
    output reg data_out_active
    );
    
 
 reg  XOR_OUT_parity;
 wire XOR_OUT ;   
 reg  [3:0] data_in_length ;    
 reg [7:0] data;   
 reg [2:0] state;
 reg [2:0] next_state;  
 reg [8:0] data_parity;    
 reg  [3:0] data_parity_length ;
 
 assign XOR_OUT = ^data ; 
 
 parameter  IDLE = 1'b0;     
 parameter  data_processing = 1'b1; 

 
 
always @(posedge clk) 
begin
  if (reset==0)  state<= IDLE;
  else           state<= next_state;
          
end 
   
always @ ( state or data_parity or data_parity_length or fifo_empty or data_in or tx_ready or data_in_length or data or LCR0 or LCR1 or  LCR2 or  LCR3 or  LCR4 or  LCR5 or XOR_OUT)
 begin
   case (state)

   IDLE: 
     begin 
          data_out_active <=  0;
          data_out <=0;
          num_stop_bit <=0;
          data_length <=0;
          fifo_read <= 0;
          data_parity <= 0;
          data_parity_length <=0;
          data <= 0;
          data_in_length <= 0;
          
    if ( fifo_empty == 0 && tx_ready)
       begin
      fifo_read <= 1;
     next_state <= data_processing ;
       end    	
	else   begin 
	  fifo_read <= 0; 
	  next_state<= IDLE;
     end
 end       

data_processing: 
    begin
    data_length<= 0;
	fifo_read <= 0;
	data<= data_in;	
	data_out <= data_parity ;
	data_length <= data_parity_length; 
    data_out_active<=1;

 case({LCR0,LCR1})
      2'b00:
        begin
         data_in_length <=5;
        end
      2'b01:
       begin
        data_in_length<=6;
       end
       2'b10:
        begin
         data_in_length<=7;
        end
       
     default: 
     begin
            data_in_length<=8;
      end
 endcase

     if (LCR3==1)
 begin
     case({LCR4,LCR5, XOR_OUT})
        3'b000:
         begin
          data_parity_length <= data_in_length+ 1 ; 
          data_parity<= {1'b0,data} ;                 
         end
        3'b001 :
         begin
          data_parity_length<=  data_in_length+ 1;
          data_parity<= {1'b1,data} ;            
         end       
        3'b010:   
         begin
          data_parity_length <= data_in_length+ 1 ; 
          data_parity<= {1'b1,data} ;             
         end
        3'b011: 
         begin
          data_parity_length<=  data_in_length+ 1;
          data_parity<= {1'b0,data} ;              
         end
        3'b100:
        begin
          data_parity_length <= data_in_length+ 1 ; 
          data_parity<= {1'b0,data} ;  
        end 
       3'b101: 
        begin
          data_parity_length <= data_in_length+ 1 ; 
          data_parity<= {1'b1,data} ;  
        end    
       3'b110: 
        begin
          data_parity_length <= data_in_length+ 1 ; 
          data_parity<= {1'b1,data} ;  
        end 
      default: 
       begin
         data_parity_length <= data_in_length+ 1 ; 
         data_parity<= {1'b0,data} ;  
         end            
      endcase
     end     
 else  
      begin
      data_parity_length<=  data_in_length;  
      data_parity<= data;
      end 
  

 case (LCR2)
 1'b0: 
     begin
        num_stop_bit<=2'b01;
      end
  
 1'b1:
      begin
        case({LCR0,LCR1})
        2'b00:
          begin
           num_stop_bit<=2'b10 ;
          end
         default:
           begin
            num_stop_bit<= 2'b11 ;
          end
          
      endcase  
     end  
endcase
      
    if(!tx_ready)                     
       next_state<=  IDLE;  
    else
       next_state<=  data_processing ;   
    end


 default: begin
    data_out_active <=  0;
    data_out<=0;
    num_stop_bit<=0;
    data_length<=0;
    fifo_read<= 0;
    next_state <= IDLE;
    data_parity<= 0;
    data_parity_length <= 0;
    data <= 0;
    data_in_length <= 0;
 end
endcase 

 end 
 
endmodule
module Process(
    input LCR0,
    input LCR1,
    input LCR2,
    input LCR3,
    input LCR4,
    input LCR5,
    input [7:0] data_in,  
    input fifo_empty,
    input clk,
    input reset,
    input tx_ready,
    output reg  fifo_read,
    output reg [8:0] data_out,  
    output reg  [3:0] data_length,
    output reg [1:0] num_stop_bit,
    output reg data_out_active
    );

    
 
 reg  XOR_OUT_parity;
 wire XOR_OUT ;   
 reg  [3:0] data_in_length ;    
 reg [7:0] data;   
 reg [2:0] state;
 reg [2:0] next_state;  
 reg [8:0] data_parity;    
 reg  [3:0] data_parity_length ;
 
 assign XOR_OUT = ^data ; 
 
 parameter  IDLE = 1'b0;     
 parameter  data_processing = 1'b1; 

 
 
always @(posedge clk) 
begin
  if (reset==0)  state<= IDLE;
  else           state<= next_state;
          
end 
   
always @ ( state or data_parity or data_parity_length or fifo_empty or data_in or tx_ready or data_in_length or data or LCR0 or LCR1 or  LCR2 or  LCR3 or  LCR4 or  LCR5 or XOR_OUT)
 begin
   case (state)

   IDLE: 
     begin 
          data_out_active <=  0;
          data_out <=0;
          num_stop_bit <=0;
          data_length <=0;
          fifo_read <= 0;
          data_parity <= 0;
          data_parity_length <=0;
          data <= 0;
          data_in_length <= 0;
          
    if ( fifo_empty == 0 && tx_ready)
       begin
      fifo_read <= 1;
     next_state <= data_processing ;
       end    	
	else   begin 
	  fifo_read <= 0; 
	  next_state<= IDLE;
     end
 end       

data_processing: 
    begin
    data_length<= 0;
	fifo_read <= 0;
	data<= data_in;	
	data_out <= data_parity ;
	data_length <= data_parity_length; 
    data_out_active<=1;

 case({LCR0,LCR1})
      2'b00:
        begin
         data_in_length <=5;
        end
      2'b01:
       begin
        data_in_length<=6;
       end
       2'b10:
        begin
         data_in_length<=7;
        end
       
     default: 
     begin
            data_in_length<=8;
      end
 endcase

     if (LCR3==1)
 begin
     case({LCR4,LCR5, XOR_OUT})
        3'b000:
         begin
          data_parity_length <= data_in_length+ 1 ; 
          data_parity<= {1'b0,data} ;                 
         end
        3'b001 :
         begin
          data_parity_length<=  data_in_length+ 1;
          data_parity<= {1'b1,data} ;            
         end       
        3'b010:   
         begin
          data_parity_length <= data_in_length+ 1 ; 
          data_parity<= {1'b1,data} ;             
         end
        3'b011: 
         begin
          data_parity_length<=  data_in_length+ 1;
          data_parity<= {1'b0,data} ;              
         end
        3'b100:
        begin
          data_parity_length <= data_in_length+ 1 ; 
          data_parity<= {1'b0,data} ;  
        end 
       3'b101: 
        begin
          data_parity_length <= data_in_length+ 1 ; 
          data_parity<= {1'b1,data} ;  
        end    
       3'b110: 
        begin
          data_parity_length <= data_in_length+ 1 ; 
          data_parity<= {1'b1,data} ;  
        end 
      default: 
       begin
         data_parity_length <= data_in_length+ 1 ; 
         data_parity<= {1'b0,data} ;  
         end            
      endcase
     end     
 else  
      begin
      data_parity_length<=  data_in_length;  
      data_parity<= data;
      end 
  

 case (LCR2)
 1'b0: 
     begin
        num_stop_bit<=2'b01;
      end
  
 1'b1:
      begin
        case({LCR0,LCR1})
        2'b00:
          begin
           num_stop_bit<=2'b10 ;
          end
         default:
           begin
            num_stop_bit<= 2'b11 ;
          end
          
      endcase  
     end  
endcase
      
    if(!tx_ready)                     
       next_state<=  IDLE;  
    else
       next_state<=  data_processing ;   
    end


 default: begin
    data_out_active <=  0;
    data_out<=0;
    num_stop_bit<=0;
    data_length<=0;
    fifo_read<= 0;
    next_state <= IDLE;
    data_parity<= 0;
    data_parity_length <= 0;
    data <= 0;
    data_in_length <= 0;
 end
endcase 

 end 
 
endmodule