data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_clgen.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_clgen.v:41: Cannot find include file: spi_defines.v\n`include "spi_defines.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup,data/full_repos/permissive/19905110/spi_defines.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup,data/full_repos/permissive/19905110/spi_defines.v.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup,data/full_repos/permissive/19905110/spi_defines.v.sv\n             spi_defines.v\n             spi_defines.v.v\n             spi_defines.v.sv\n             obj_dir/spi_defines.v\n             obj_dir/spi_defines.v.v\n             obj_dir/spi_defines.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_startup/spi_clgen.v:42: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module spi_flash_clgen (clk_in, rst, go, enable, last_clk, clk_out, pos_edge, neg_edge); 
   
   parameter divider_len = 2;
   parameter divider = 1;
   
   parameter Tp = 1;
   
   input                            clk_in;
   input                            rst;
   input                            enable;
   input                            go;
   input                            last_clk;

   output                           clk_out;
   output                           pos_edge;
   output                           neg_edge;
   
   reg                              clk_out;
   reg                              pos_edge;
   reg                              neg_edge;
   
   reg [divider_len-1:0] 	    cnt;
   wire                             cnt_zero;
   wire                             cnt_one;
   
   
   assign cnt_zero = cnt == {divider_len{1'b0}};
   assign cnt_one  = cnt == {{divider_len-1{1'b0}}, 1'b1};
   

   always @(posedge clk_in or posedge rst)
     begin
	if(rst)
	  cnt <= #Tp {divider_len{1'b1}};
	else
	  begin
             if(!enable || cnt_zero)
               cnt <= #Tp divider;
             else
               cnt <= #Tp cnt - {{divider_len-1{1'b0}}, 1'b1};
	  end
     end
   

   always @(posedge clk_in or posedge rst)
     begin
	if(rst)
	  clk_out <= #Tp 1'b0;
	else
	  clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
     end
   

   always @(posedge clk_in or posedge rst)
     begin
	if(rst)
	  begin
             pos_edge  <= #Tp 1'b0;
             neg_edge  <= #Tp 1'b0;
	  end
	else
	  begin
             pos_edge  <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
             neg_edge  <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
	  end
     end
endmodule
module spi_flash_clgen (clk_in, rst, go, enable, last_clk, clk_out, pos_edge, neg_edge);
 
   
   parameter divider_len = 2;
   parameter divider = 1;
   
   parameter Tp = 1;
   
   input                            clk_in;
   input                            rst;
   input                            enable;
   input                            go;
   input                            last_clk;

   output                           clk_out;
   output                           pos_edge;
   output                           neg_edge;
   
   reg                              clk_out;
   reg                              pos_edge;
   reg                              neg_edge;
   
   reg [divider_len-1:0] 	    cnt;
   wire                             cnt_zero;
   wire                             cnt_one;
   
   
   assign cnt_zero = cnt == {divider_len{1'b0}};
   assign cnt_one  = cnt == {{divider_len-1{1'b0}}, 1'b1};
   

   always @(posedge clk_in or posedge rst)
     begin
	if(rst)
	  cnt <= #Tp {divider_len{1'b1}};
	else
	  begin
             if(!enable || cnt_zero)
               cnt <= #Tp divider;
             else
               cnt <= #Tp cnt - {{divider_len-1{1'b0}}, 1'b1};
	  end
     end
   

   always @(posedge clk_in or posedge rst)
     begin
	if(rst)
	  clk_out <= #Tp 1'b0;
	else
	  clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
     end
   

   always @(posedge clk_in or posedge rst)
     begin
	if(rst)
	  begin
             pos_edge  <= #Tp 1'b0;
             neg_edge  <= #Tp 1'b0;
	  end
	else
	  begin
             pos_edge  <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
             neg_edge  <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
	  end
     end
endmodule