data/full_repos/permissive/114421971/clbconfigs/top.v
 line:53: before: ","
1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n                                      ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n        ^~\n%Error: Exiting due to 2 error(s)\n"
module clb_m (input clk, input [15:0] din, output [15:0] dout);
	assign dout = 0;
endmodule
module clb_m (input clk, input [15:0] din, output [15:0] dout);

	assign dout = 0;
endmodule