data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v
None: at end of input
1: b'%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:22: Cannot find include file: common.h\n`include "common.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.v\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.sv\n             common.h\n             common.h.v\n             common.h.sv\n             obj_dir/common.h\n             obj_dir/common.h.v\n             obj_dir/common.h.sv\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:51: Define or directive not defined: \'`BW_DATA_IN\'\nparameter BW_DATA_IN = `BW_DATA_IN;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:51: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DATA_IN = `BW_DATA_IN;\n                                  ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:80: Define or directive not defined: \'`BW_TYPE_CODE\'\nwire [`BW_TYPE_CODE-1:0] type_code;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:122: Define or directive not defined: \'`RANGE_TYPE_CODE\'\nassign type_code = data_fifo_in[`RANGE_TYPE_CODE];\n                                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:122: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign type_code = data_fifo_in[`RANGE_TYPE_CODE];\n                                                ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:161: Define or directive not defined: \'`TYPE_CODE_SET_LR_L2\'\n    if((type_code!=`TYPE_CODE_SET_LR_L2)&&(type_code!=`TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(type_code!=`TYPE_CODE_RST_MEMN2N)&&(type_code!=`TYPE_CODE_DUMMY)&&(type_code!=`TYPE_CODE_SET_MODE_ON)&&(type_code!=`TYPE_CODE_SET_MODE_OFF)&&(set_mode==1\'b0))\n                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:161: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if((type_code!=`TYPE_CODE_SET_LR_L2)&&(type_code!=`TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(type_code!=`TYPE_CODE_RST_MEMN2N)&&(type_code!=`TYPE_CODE_DUMMY)&&(type_code!=`TYPE_CODE_SET_MODE_ON)&&(type_code!=`TYPE_CODE_SET_MODE_OFF)&&(set_mode==1\'b0))\n                                       ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:161: Define or directive not defined: \'`TYPE_CODE_DIN_EXP_SHIFT_BIT\'\n    if((type_code!=`TYPE_CODE_SET_LR_L2)&&(type_code!=`TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(type_code!=`TYPE_CODE_RST_MEMN2N)&&(type_code!=`TYPE_CODE_DUMMY)&&(type_code!=`TYPE_CODE_SET_MODE_ON)&&(type_code!=`TYPE_CODE_SET_MODE_OFF)&&(set_mode==1\'b0))\n                                                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:161: Define or directive not defined: \'`TYPE_CODE_RST_MEMN2N\'\n    if((type_code!=`TYPE_CODE_SET_LR_L2)&&(type_code!=`TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(type_code!=`TYPE_CODE_RST_MEMN2N)&&(type_code!=`TYPE_CODE_DUMMY)&&(type_code!=`TYPE_CODE_SET_MODE_ON)&&(type_code!=`TYPE_CODE_SET_MODE_OFF)&&(set_mode==1\'b0))\n                                                                                                 ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:161: Define or directive not defined: \'`TYPE_CODE_DUMMY\'\n    if((type_code!=`TYPE_CODE_SET_LR_L2)&&(type_code!=`TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(type_code!=`TYPE_CODE_RST_MEMN2N)&&(type_code!=`TYPE_CODE_DUMMY)&&(type_code!=`TYPE_CODE_SET_MODE_ON)&&(type_code!=`TYPE_CODE_SET_MODE_OFF)&&(set_mode==1\'b0))\n                                                                                                                                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:161: Define or directive not defined: \'`TYPE_CODE_SET_MODE_ON\'\n    if((type_code!=`TYPE_CODE_SET_LR_L2)&&(type_code!=`TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(type_code!=`TYPE_CODE_RST_MEMN2N)&&(type_code!=`TYPE_CODE_DUMMY)&&(type_code!=`TYPE_CODE_SET_MODE_ON)&&(type_code!=`TYPE_CODE_SET_MODE_OFF)&&(set_mode==1\'b0))\n                                                                                                                                                                    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:161: Define or directive not defined: \'`TYPE_CODE_SET_MODE_OFF\'\n    if((type_code!=`TYPE_CODE_SET_LR_L2)&&(type_code!=`TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(type_code!=`TYPE_CODE_RST_MEMN2N)&&(type_code!=`TYPE_CODE_DUMMY)&&(type_code!=`TYPE_CODE_SET_MODE_ON)&&(type_code!=`TYPE_CODE_SET_MODE_OFF)&&(set_mode==1\'b0))\n                                                                                                                                                                                                         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:196: Define or directive not defined: \'`TYPE_CODE_SET_LR_L2\'\n        if((type_code == `TYPE_CODE_SET_LR_L2)&&(set_mode_on_0==1\'b0)&&(set_mode==1\'b0))\n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:207: Define or directive not defined: \'`TYPE_CODE_DIN_EXP_SHIFT_BIT\'\n        if((type_code == `TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(set_mode_on_0==1\'b0)&&(set_mode==1\'b0))\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:222: Define or directive not defined: \'`TYPE_CODE_SET_MODE_ON\'\n            if(type_code == `TYPE_CODE_SET_MODE_ON)\n                            ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:234: Define or directive not defined: \'`TYPE_CODE_SET_MODE_ON_1\'\n            if((set_mode_on_0==1\'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_ON_1))\n                                                     ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:246: Define or directive not defined: \'`TYPE_CODE_SET_MODE_ON_2\'\n            if((set_mode_on_1==1\'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_ON_2))\n                                                     ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:272: Define or directive not defined: \'`TYPE_CODE_SET_MODE_OFF\'\n            if(type_code == `TYPE_CODE_SET_MODE_OFF)\n                            ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:272: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(type_code == `TYPE_CODE_SET_MODE_OFF)\n                                                   ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:284: Define or directive not defined: \'`TYPE_CODE_SET_MODE_OFF_1\'\n            if((set_mode_off_0==1\'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_OFF_1))\n                                                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:284: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if((set_mode_off_0==1\'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_OFF_1))\n                                                                               ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:296: Define or directive not defined: \'`TYPE_CODE_SET_MODE_OFF_2\'\n            if((set_mode_off_1==1\'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_OFF_2))\n                                                      ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:296: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if((set_mode_off_1==1\'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_OFF_2))\n                                                                               ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:322: Define or directive not defined: \'`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA\'\n        if((set_mode==1\'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA)&&(valid_fifo_in==1\'b1))\n                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:322: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if((set_mode==1\'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA)&&(valid_fifo_in==1\'b1))\n                                                                              ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:351: Define or directive not defined: \'`TYPE_CODE_RST_MEMN2N\'\n            if(type_code != `TYPE_CODE_RST_MEMN2N)\n                            ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:351: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(type_code != `TYPE_CODE_RST_MEMN2N)\n                                                 ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:359: Define or directive not defined: \'`TYPE_CODE_RST_MEMN2N\'\n    if((type_code == `TYPE_CODE_RST_MEMN2N)&&(done_rst_n_memn2n_cmd==1\'b0)&&(set_mode==1\'b0))\n                     ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:359: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if((type_code == `TYPE_CODE_RST_MEMN2N)&&(done_rst_n_memn2n_cmd==1\'b0)&&(set_mode==1\'b0))\n                                          ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:367: Define or directive not defined: \'`TYPE_CODE_RST_MEMN2N\'\n    if((type_code!=`TYPE_CODE_RST_MEMN2N)||(rst_n==1\'b0)||(set_mode==1\'b1))\n                   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/memory_network_controller.v:367: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if((type_code!=`TYPE_CODE_RST_MEMN2N)||(rst_n==1\'b0)||(set_mode==1\'b1))\n                                        ^\n%Error: Exiting due to 32 error(s)\n'
module memory_network_controller
(

    clk,

    rst_n,

    rb_n_memory_network,
    valid_fifo_in,
    done_init_memn2n,
    data_fifo_in,
    data_out,

    en_memory_network,
    done_init,
    data_in,
    data_in_fifo_out,
    lr_l2,
    din_exp_shift_bit,
    rst_n_memn2n_cmd,
    set_mode,
    en_w_load_to_fpga
);




parameter BW_DATA_IN = `BW_DATA_IN;





input wire clk;

input wire rst_n;

input wire rb_n_memory_network;
input wire valid_fifo_in;
input wire done_init_memn2n;
input wire [BW_DATA_IN-1:0] data_fifo_in;
input wire [BW_DATA_IN-1:0] data_out;

output reg en_memory_network;
output reg done_init;
output reg [BW_DATA_IN-1:0] data_in;
output reg [BW_DATA_IN-1:0] data_in_fifo_out;
output reg [7:0] lr_l2;
output reg [7:0] din_exp_shift_bit;
output reg rst_n_memn2n_cmd;
output reg set_mode;
output reg en_w_load_to_fpga;




wire [`BW_TYPE_CODE-1:0] type_code;
wire [BW_DATA_IN-1:0] type_code_16;

wire [BW_DATA_IN-1:0] _data_in;
wire [BW_DATA_IN-1:0] _data_in_fifo_out;


reg en_rst_n_memn2n_cmd;
reg rst_n_count_rst_n_memn2n;
wire en_count_rst_n_memn2n;
reg done_rst_n_memn2n_cmd;
wire done_count_rst_n_memn2n_cmd;

wire _set_mode_on;
reg set_mode_on_0;
reg set_mode_on_1;
reg set_mode_on_2;

reg set_mode_off;
wire _set_mode_off;
reg set_mode_off_0;
reg set_mode_off_1;
reg set_mode_off_2;

reg _en_memory_network;











assign type_code = data_fifo_in[`RANGE_TYPE_CODE];
assign type_code_16 = data_fifo_in;

assign _data_in = data_fifo_in;
assign _data_in_fifo_out = data_out;





always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_memory_network <= 1'b0;
    else 
        en_memory_network <= valid_fifo_in && rb_n_memory_network && _en_memory_network;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        done_init <= 1'b0;
    else
        if(done_init==1'b0)
            done_init <= done_init_memn2n;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        data_in <= {BW_DATA_IN{1'b0}};
    else
        if(_en_memory_network==1'b1)
            data_in <= _data_in;
end

always@(*)
begin

    if((type_code!=`TYPE_CODE_SET_LR_L2)&&(type_code!=`TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(type_code!=`TYPE_CODE_RST_MEMN2N)&&(type_code!=`TYPE_CODE_DUMMY)&&(type_code!=`TYPE_CODE_SET_MODE_ON)&&(type_code!=`TYPE_CODE_SET_MODE_OFF)&&(set_mode==1'b0))
    begin
        _en_memory_network = 1'b1;
    end
    else
    begin
        _en_memory_network = 1'b0;
    end
end





always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        data_in_fifo_out <= {BW_DATA_IN{1'b0}};
    else
        data_in_fifo_out <= _data_in_fifo_out;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        lr_l2 <= 8'b0;
    else
        if((type_code == `TYPE_CODE_SET_LR_L2)&&(set_mode_on_0==1'b0)&&(set_mode==1'b0))
        begin
            lr_l2 <= _data_in[7:0];
        end
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        din_exp_shift_bit <= 8'b0;
    else
        if((type_code == `TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(set_mode_on_0==1'b0)&&(set_mode==1'b0))
        begin
            din_exp_shift_bit <= _data_in[7:0];
        end
end


always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_on_0 <= 1'b0;
    else
        if(set_mode==1'b1)
            set_mode_on_0 <= 1'b0;
        else
            if(type_code == `TYPE_CODE_SET_MODE_ON)
                set_mode_on_0 <= 1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_on_1 <= 1'b0;
    else
        if(set_mode==1'b1)
            set_mode_on_1 <= 1'b0;
        else 
            if((set_mode_on_0==1'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_ON_1))
                set_mode_on_1 <= 1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_on_2 <= 1'b0;
    else
        if(set_mode==1'b1)
            set_mode_on_2 <= 1'b0;
        else
            if((set_mode_on_1==1'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_ON_2))
                set_mode_on_2 <= 1'b1;
end

assign _set_mode_on = set_mode_on_0&&set_mode_on_1&&set_mode_on_2;

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode <= 1'b0;
    else
        if(set_mode_off==1'b1)
            set_mode <= 1'b0;
        else
            if(set_mode==1'b0)
                set_mode <= _set_mode_on;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_off_0 <= 1'b0;
    else
        if(set_mode_off==1'b1)
            set_mode_off_0 <= 1'b0;
        else
            if(type_code == `TYPE_CODE_SET_MODE_OFF)
                set_mode_off_0 <= 1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_off_1 <= 1'b0;
    else
        if(set_mode_off==1'b1)
            set_mode_off_1 <= 1'b0;
        else 
            if((set_mode_off_0==1'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_OFF_1))
                set_mode_off_1 <= 1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_off_2 <= 1'b0;
    else
        if(set_mode_off==1'b1)
            set_mode_off_2 <= 1'b0;
        else
            if((set_mode_off_1==1'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_OFF_2))
                set_mode_off_2 <= 1'b1;
end

assign _set_mode_off = set_mode_off_0&&set_mode_off_1&&set_mode_off_2;

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_off <= 1'b0;
    else
        if(set_mode_off==1'b1)
            set_mode_off <= 1'b0;
        else
            set_mode_off <= _set_mode_off;
end


always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_w_load_to_fpga <= 1'b0;
    else



        if((set_mode==1'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA)&&(valid_fifo_in==1'b1))
            en_w_load_to_fpga <= 1'b1;
        else
            en_w_load_to_fpga <= 1'b0;

end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        rst_n_memn2n_cmd <= 1'b1;
    else
        if(done_rst_n_memn2n_cmd==1'b1)
            rst_n_memn2n_cmd <= 1'b1;
        else
            if(en_rst_n_memn2n_cmd==1'b1)
                rst_n_memn2n_cmd <= 1'b0;
            else
                rst_n_memn2n_cmd <= 1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        done_rst_n_memn2n_cmd <= 1'b0;
    else
        if(done_rst_n_memn2n_cmd==1'b0)
            done_rst_n_memn2n_cmd <= done_count_rst_n_memn2n;
        else
            if(type_code != `TYPE_CODE_RST_MEMN2N)
                done_rst_n_memn2n_cmd <= 1'b0;
end

assign en_count_rst_n_memn2n = en_rst_n_memn2n_cmd;

always@(*)
begin
    if((type_code == `TYPE_CODE_RST_MEMN2N)&&(done_rst_n_memn2n_cmd==1'b0)&&(set_mode==1'b0))
        en_rst_n_memn2n_cmd = 1'b1;
    else
        en_rst_n_memn2n_cmd = 1'b0;
end

always@(*)
begin
    if((type_code!=`TYPE_CODE_RST_MEMN2N)||(rst_n==1'b0)||(set_mode==1'b1))
        rst_n_count_rst_n_memn2n = 1'b0;
    else
        rst_n_count_rst_n_memn2n = 1'b1;
end

counter
#(
    .BW(9),
    .COUNT_VALUE(128)
)
count_rst_n_memn2n
(

    .clk(clk),

    .rst_n(rst_n_count_rst_n_memn2n),

    .en(en_count_rst_n_memn2n),
    .en_hold_max(1'b0),

    .count(),
    .done(done_count_rst_n_memn2n)
);


`ifdef DEBUG
`ifdef DEBUG_ILA

ila
ila_memn2n_controller
(
    .clk(clk),


    .probe0(rb_n_memory_network),
    .probe1(valid_fifo_in),
    .probe2(done_init_memn2n),
    .probe3(en_memory_network),
    .probe4(done_init),
    .probe5(rst_n_memn2n_cmd),
    .probe6(set_mode),
    .probe7(en_w_load_to_fpga),


    .probe8(en_rst_n_memn2n_cmd),
    .probe9(rst_n_count_rst_n_memn2n),
    .probe10(en_count_rst_n_memn2n),
    .probe11(done_rst_n_memn2n_cmd),
    .probe12(_set_mode_on),
    .probe13(_en_memory_network),
    .probe14(),
    .probe15(),


    .probe16(data_fifo_in),
    .probe17(data_out),
    .probe18(data_in),
    .probe19(data_in_fifo_out),
    .probe20(_data_in),
    .probe21(_data_in_fifo_out),
    .probe22(lr_l2),
    .probe23(din_exp_shift_bit),


    .probe24(),
    .probe25(data_out),
    .probe26(type_code),
    .probe27(type_code_16),
    .probe28(),
    .probe29(),
    .probe30(),
    .probe31(),


    .probe32(set_mode_on_0),
    .probe33(set_mode_on_1),
    .probe34(set_mode_on_2),
    .probe35(set_mode_off),
    .probe36(_set_mode_off),
    .probe37(set_mode_off_0),
    .probe38(set_mode_off_1),
    .probe39(set_mode_off_2),


    .probe40(),
    .probe41(),
    .probe42(),
    .probe43(),
    .probe44(),
    .probe45(),
    .probe46(),
    .probe47(),


    .probe48(),
    .probe49(),
    .probe50(),
    .probe51(),
    .probe52(),
    .probe53(),
    .probe54(),
    .probe55(),


    .probe56(),
    .probe57(),
    .probe58(),
    .probe59(),
    .probe60(),
    .probe61(),
    .probe62(),
    .probe63()
);
`endif
`endif

endmodule
module memory_network_controller
(

    clk,

    rst_n,

    rb_n_memory_network,
    valid_fifo_in,
    done_init_memn2n,
    data_fifo_in,
    data_out,

    en_memory_network,
    done_init,
    data_in,
    data_in_fifo_out,
    lr_l2,
    din_exp_shift_bit,
    rst_n_memn2n_cmd,
    set_mode,
    en_w_load_to_fpga
);





parameter BW_DATA_IN = `BW_DATA_IN;





input wire clk;

input wire rst_n;

input wire rb_n_memory_network;
input wire valid_fifo_in;
input wire done_init_memn2n;
input wire [BW_DATA_IN-1:0] data_fifo_in;
input wire [BW_DATA_IN-1:0] data_out;

output reg en_memory_network;
output reg done_init;
output reg [BW_DATA_IN-1:0] data_in;
output reg [BW_DATA_IN-1:0] data_in_fifo_out;
output reg [7:0] lr_l2;
output reg [7:0] din_exp_shift_bit;
output reg rst_n_memn2n_cmd;
output reg set_mode;
output reg en_w_load_to_fpga;




wire [`BW_TYPE_CODE-1:0] type_code;
wire [BW_DATA_IN-1:0] type_code_16;

wire [BW_DATA_IN-1:0] _data_in;
wire [BW_DATA_IN-1:0] _data_in_fifo_out;


reg en_rst_n_memn2n_cmd;
reg rst_n_count_rst_n_memn2n;
wire en_count_rst_n_memn2n;
reg done_rst_n_memn2n_cmd;
wire done_count_rst_n_memn2n_cmd;

wire _set_mode_on;
reg set_mode_on_0;
reg set_mode_on_1;
reg set_mode_on_2;

reg set_mode_off;
wire _set_mode_off;
reg set_mode_off_0;
reg set_mode_off_1;
reg set_mode_off_2;

reg _en_memory_network;











assign type_code = data_fifo_in[`RANGE_TYPE_CODE];
assign type_code_16 = data_fifo_in;

assign _data_in = data_fifo_in;
assign _data_in_fifo_out = data_out;





always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_memory_network <= 1'b0;
    else 
        en_memory_network <= valid_fifo_in && rb_n_memory_network && _en_memory_network;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        done_init <= 1'b0;
    else
        if(done_init==1'b0)
            done_init <= done_init_memn2n;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        data_in <= {BW_DATA_IN{1'b0}};
    else
        if(_en_memory_network==1'b1)
            data_in <= _data_in;
end

always@(*)
begin

    if((type_code!=`TYPE_CODE_SET_LR_L2)&&(type_code!=`TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(type_code!=`TYPE_CODE_RST_MEMN2N)&&(type_code!=`TYPE_CODE_DUMMY)&&(type_code!=`TYPE_CODE_SET_MODE_ON)&&(type_code!=`TYPE_CODE_SET_MODE_OFF)&&(set_mode==1'b0))
    begin
        _en_memory_network = 1'b1;
    end
    else
    begin
        _en_memory_network = 1'b0;
    end
end





always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        data_in_fifo_out <= {BW_DATA_IN{1'b0}};
    else
        data_in_fifo_out <= _data_in_fifo_out;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        lr_l2 <= 8'b0;
    else
        if((type_code == `TYPE_CODE_SET_LR_L2)&&(set_mode_on_0==1'b0)&&(set_mode==1'b0))
        begin
            lr_l2 <= _data_in[7:0];
        end
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        din_exp_shift_bit <= 8'b0;
    else
        if((type_code == `TYPE_CODE_DIN_EXP_SHIFT_BIT)&&(set_mode_on_0==1'b0)&&(set_mode==1'b0))
        begin
            din_exp_shift_bit <= _data_in[7:0];
        end
end


always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_on_0 <= 1'b0;
    else
        if(set_mode==1'b1)
            set_mode_on_0 <= 1'b0;
        else
            if(type_code == `TYPE_CODE_SET_MODE_ON)
                set_mode_on_0 <= 1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_on_1 <= 1'b0;
    else
        if(set_mode==1'b1)
            set_mode_on_1 <= 1'b0;
        else 
            if((set_mode_on_0==1'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_ON_1))
                set_mode_on_1 <= 1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_on_2 <= 1'b0;
    else
        if(set_mode==1'b1)
            set_mode_on_2 <= 1'b0;
        else
            if((set_mode_on_1==1'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_ON_2))
                set_mode_on_2 <= 1'b1;
end

assign _set_mode_on = set_mode_on_0&&set_mode_on_1&&set_mode_on_2;

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode <= 1'b0;
    else
        if(set_mode_off==1'b1)
            set_mode <= 1'b0;
        else
            if(set_mode==1'b0)
                set_mode <= _set_mode_on;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_off_0 <= 1'b0;
    else
        if(set_mode_off==1'b1)
            set_mode_off_0 <= 1'b0;
        else
            if(type_code == `TYPE_CODE_SET_MODE_OFF)
                set_mode_off_0 <= 1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_off_1 <= 1'b0;
    else
        if(set_mode_off==1'b1)
            set_mode_off_1 <= 1'b0;
        else 
            if((set_mode_off_0==1'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_OFF_1))
                set_mode_off_1 <= 1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_off_2 <= 1'b0;
    else
        if(set_mode_off==1'b1)
            set_mode_off_2 <= 1'b0;
        else
            if((set_mode_off_1==1'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_OFF_2))
                set_mode_off_2 <= 1'b1;
end

assign _set_mode_off = set_mode_off_0&&set_mode_off_1&&set_mode_off_2;

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        set_mode_off <= 1'b0;
    else
        if(set_mode_off==1'b1)
            set_mode_off <= 1'b0;
        else
            set_mode_off <= _set_mode_off;
end


always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_w_load_to_fpga <= 1'b0;
    else



        if((set_mode==1'b1)&&(type_code_16==`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA)&&(valid_fifo_in==1'b1))
            en_w_load_to_fpga <= 1'b1;
        else
            en_w_load_to_fpga <= 1'b0;

end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        rst_n_memn2n_cmd <= 1'b1;
    else
        if(done_rst_n_memn2n_cmd==1'b1)
            rst_n_memn2n_cmd <= 1'b1;
        else
            if(en_rst_n_memn2n_cmd==1'b1)
                rst_n_memn2n_cmd <= 1'b0;
            else
                rst_n_memn2n_cmd <= 1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        done_rst_n_memn2n_cmd <= 1'b0;
    else
        if(done_rst_n_memn2n_cmd==1'b0)
            done_rst_n_memn2n_cmd <= done_count_rst_n_memn2n;
        else
            if(type_code != `TYPE_CODE_RST_MEMN2N)
                done_rst_n_memn2n_cmd <= 1'b0;
end

assign en_count_rst_n_memn2n = en_rst_n_memn2n_cmd;

always@(*)
begin
    if((type_code == `TYPE_CODE_RST_MEMN2N)&&(done_rst_n_memn2n_cmd==1'b0)&&(set_mode==1'b0))
        en_rst_n_memn2n_cmd = 1'b1;
    else
        en_rst_n_memn2n_cmd = 1'b0;
end

always@(*)
begin
    if((type_code!=`TYPE_CODE_RST_MEMN2N)||(rst_n==1'b0)||(set_mode==1'b1))
        rst_n_count_rst_n_memn2n = 1'b0;
    else
        rst_n_count_rst_n_memn2n = 1'b1;
end

counter
#(
    .BW(9),
    .COUNT_VALUE(128)
)
count_rst_n_memn2n
(

    .clk(clk),

    .rst_n(rst_n_count_rst_n_memn2n),

    .en(en_count_rst_n_memn2n),
    .en_hold_max(1'b0),

    .count(),
    .done(done_count_rst_n_memn2n)
);


`ifdef DEBUG
`ifdef DEBUG_ILA

ila
ila_memn2n_controller
(
    .clk(clk),


    .probe0(rb_n_memory_network),
    .probe1(valid_fifo_in),
    .probe2(done_init_memn2n),
    .probe3(en_memory_network),
    .probe4(done_init),
    .probe5(rst_n_memn2n_cmd),
    .probe6(set_mode),
    .probe7(en_w_load_to_fpga),


    .probe8(en_rst_n_memn2n_cmd),
    .probe9(rst_n_count_rst_n_memn2n),
    .probe10(en_count_rst_n_memn2n),
    .probe11(done_rst_n_memn2n_cmd),
    .probe12(_set_mode_on),
    .probe13(_en_memory_network),
    .probe14(),
    .probe15(),


    .probe16(data_fifo_in),
    .probe17(data_out),
    .probe18(data_in),
    .probe19(data_in_fifo_out),
    .probe20(_data_in),
    .probe21(_data_in_fifo_out),
    .probe22(lr_l2),
    .probe23(din_exp_shift_bit),


    .probe24(),
    .probe25(data_out),
    .probe26(type_code),
    .probe27(type_code_16),
    .probe28(),
    .probe29(),
    .probe30(),
    .probe31(),


    .probe32(set_mode_on_0),
    .probe33(set_mode_on_1),
    .probe34(set_mode_on_2),
    .probe35(set_mode_off),
    .probe36(_set_mode_off),
    .probe37(set_mode_off_0),
    .probe38(set_mode_off_1),
    .probe39(set_mode_off_2),


    .probe40(),
    .probe41(),
    .probe42(),
    .probe43(),
    .probe44(),
    .probe45(),
    .probe46(),
    .probe47(),


    .probe48(),
    .probe49(),
    .probe50(),
    .probe51(),
    .probe52(),
    .probe53(),
    .probe54(),
    .probe55(),


    .probe56(),
    .probe57(),
    .probe58(),
    .probe59(),
    .probe60(),
    .probe61(),
    .probe62(),
    .probe63()
);
`endif
`endif

endmodule