data/full_repos/permissive/169574047/counter/counter.srcs/sim_1/new/testbench.v
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1: b'%Error: data/full_repos/permissive/169574047/counter/counter.srcs/sim_1/new/testbench.v:30: Unsupported or unknown PLI call: $monitor\n    $monitor($time," Count Q = %b, Clear = %b", Q[3:0], CLEAR);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169574047/counter/counter.srcs/sim_1/new/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #34 CLEAR = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/counter/counter.srcs/sim_1/new/testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #200 CLEAR = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/counter/counter.srcs/sim_1/new/testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #50 CLEAR = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/counter/counter.srcs/sim_1/new/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n    forever #10 CLOCK = ~CLOCK;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/counter/counter.srcs/sim_1/new/testbench.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #400 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;


reg CLOCK, CLEAR;
wire [3:0] Q;

initial
    $monitor($time," Count Q = %b, Clear = %b", Q[3:0], CLEAR);


counter c1(Q, CLOCK, CLEAR);


initial
begin
    CLEAR = 1'b1;
    #34 CLEAR = 1'b0;
    #200 CLEAR = 1'b1;
    #50 CLEAR = 1'b0;
end


initial
begin
    CLOCK = 1'b0;
    forever #10 CLOCK = ~CLOCK;
end




initial
begin
    #400 $finish;
end

endmodule
module testbench;



reg CLOCK, CLEAR;
wire [3:0] Q;

initial
    $monitor($time," Count Q = %b, Clear = %b", Q[3:0], CLEAR);


counter c1(Q, CLOCK, CLEAR);


initial
begin
    CLEAR = 1'b1;
    #34 CLEAR = 1'b0;
    #200 CLEAR = 1'b1;
    #50 CLEAR = 1'b0;
end


initial
begin
    CLOCK = 1'b0;
    forever #10 CLOCK = ~CLOCK;
end




initial
begin
    #400 $finish;
end

endmodule