data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/two_bit_collector/two_bit_collector.sv
data/verilator_xmls/fb3f28c7-b69e-4915-9cba-380c7481326f.xml
module two_bit_collector
(
	input  wire       clk,
	input  wire       reset,
	
	input  wire       snk_data,
	input  wire       snk_valid,
	
	output reg  [1:0] src_data,
	output reg        src_valid
);

reg [1:0] state;

always @ (posedge clk or posedge reset) begin
	if(reset) begin
		state <= 2'b00;
		src_data <= 2'b00;
		src_valid <= 1'b0;
	end else begin
		src_valid <= 1'b0;
		if(snk_valid) begin
			if(^state) begin
				src_valid <= 1'b1;
			end
			src_data[0] <= snk_data;
			src_data[1] <= src_data[0];
			
			state[0] <= ~state[1];
			state[1] <= state[0];
		end
	end
end

endmodule
module two_bit_collector
(
	input  wire       clk,
	input  wire       reset,
	
	input  wire       snk_data,
	input  wire       snk_valid,
	
	output reg  [1:0] src_data,
	output reg        src_valid
);


reg [1:0] state;

always @ (posedge clk or posedge reset) begin
	if(reset) begin
		state <= 2'b00;
		src_data <= 2'b00;
		src_valid <= 1'b0;
	end else begin
		src_valid <= 1'b0;
		if(snk_valid) begin
			if(^state) begin
				src_valid <= 1'b1;
			end
			src_data[0] <= snk_data;
			src_data[1] <= src_data[0];
			
			state[0] <= ~state[1];
			state[1] <= state[0];
		end
	end
end

endmodule