data/full_repos/permissive/143278/ivltests/pr3077640.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr3077640.v:10: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                         : ... In instance top\n    val = $unsigned(-4);\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr3077640.v:16: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 4 bits.\n                                                                         : ... In instance top\n    val = $unsigned(-4\'sd4);\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr3077640.v:22: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 4 bits.\n                                                                         : ... In instance top\n    sval = $signed(4\'hc);\n         ^\n%Error: Exiting due to 3 warning(s)\n'
module top;
  reg pass;
  reg [7:0] val;
  reg signed [7:0] sval;

  initial begin
    pass = 1'b1;


    val = $unsigned(-4);
    if (val !== 8'hfc) begin
      $display("Failed unsigned, expected 8'hfc, got %h", val);
      pass = 1'b0;
    end

    val = $unsigned(-4'sd4);
    if (val !== 8'h0c) begin
      $display("Failed sized unsigned, expected 8'h0c, got %h", val);
      pass = 1'b0;
    end

    sval = $signed(4'hc);
    if (sval !== -4) begin
      $display("Failed signed, expected -4, got %d", sval);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  reg [7:0] val;
  reg signed [7:0] sval;

  initial begin
    pass = 1'b1;


    val = $unsigned(-4);
    if (val !== 8'hfc) begin
      $display("Failed unsigned, expected 8'hfc, got %h", val);
      pass = 1'b0;
    end

    val = $unsigned(-4'sd4);
    if (val !== 8'h0c) begin
      $display("Failed sized unsigned, expected 8'h0c, got %h", val);
      pass = 1'b0;
    end

    sval = $signed(4'hc);
    if (sval !== -4) begin
      $display("Failed signed, expected -4, got %d", sval);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule