data/full_repos/permissive/11649754/p2/test.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/11649754/p2/test.v:21: Unsupported: Ignoring delay on this delayed statement.\n   #CLKH clk = 0;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11649754/p2/test.v:22: Unsupported: Ignoring delay on this delayed statement.\n   #CLKL clk = 1;\n   ^\n%Error: data/full_repos/permissive/11649754/p2/test.v:28: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("test.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/11649754/p2/test.v:29: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0,test.c);\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/11649754/p2/test.v:38: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/11649754/p2/test.v:41: Unsupported or unknown PLI call: $dumpall\n   $dumpall;\n   ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/11649754/p2/test.v:47: Unsupported: Ignoring delay on this delayed statement.\n   #1 reset = 1;\n   ^\n%Error: data/full_repos/permissive/11649754/p2/test.v:48: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   reg clk;
   reg reset;

   wire isEnd;
   wire [31:0] sum;
   

   core c(reset, clk, isEnd, sum);

   parameter CLKP = 5000;
   parameter CLKH = CLKP/2;
   parameter CLKL = CLKP-CLKH;
   

   always begin
	  #CLKH clk = 0;
	  #CLKL clk = 1;
   end


`ifdef GTK
   initial begin
	  $dumpfile("test.vcd");
	  $dumpvars(0,test.c);
   end
`endif

   initial begin : test
	  $display("*** Simulation Started. ***");
	  sys_reset;
	  $display("*** Simulation Initialized. ***");
	  while (~isEnd)
		@(posedge clk);
	  $display("*** Simulation Complete! ***");
	  $display("RESULT: %d", sum);
	  $dumpall;
	  $finish;
   end

   task sys_reset;
	  begin
		 #1 reset = 1;
		 @(posedge clk);
		 reset = 0;
	  end
   endtask
   

endmodule
module test;


   reg clk;
   reg reset;

   wire isEnd;
   wire [31:0] sum;
   

   core c(reset, clk, isEnd, sum);

   parameter CLKP = 5000;
   parameter CLKH = CLKP/2;
   parameter CLKL = CLKP-CLKH;
   

   always begin
	  #CLKH clk = 0;
	  #CLKL clk = 1;
   end


`ifdef GTK
   initial begin
	  $dumpfile("test.vcd");
	  $dumpvars(0,test.c);
   end
`endif

   initial begin : test
	  $display("*** Simulation Started. ***");
	  sys_reset;
	  $display("*** Simulation Initialized. ***");
	  while (~isEnd)
		@(posedge clk);
	  $display("*** Simulation Complete! ***");
	  $display("RESULT: %d", sum);
	  $dumpall;
	  $finish;
   end

   task sys_reset;
	  begin
		 #1 reset = 1;
		 @(posedge clk);
		 reset = 0;
	  end
   endtask
   

endmodule