data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v
1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n             char_def.vh\n             char_def.vh.v\n             char_def.vh.sv\n             obj_dir/char_def.vh\n             obj_dir/char_def.vh.v\n             obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:39: Define or directive not defined: \'`Delay_done\'\n    assign delay_fin = (current_state == `Delay_done && delay_en == 1) ? 1 : 0;\n                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:39: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n    assign delay_fin = (current_state == `Delay_done && delay_en == 1) ? 1 : 0;\n                                                     ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:43: Define or directive not defined: \'`Delay_idle\'\n            current_state <= `Delay_idle;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            current_state <= `Delay_idle;\n                                        ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:46: Define or directive not defined: \'`Delay_idle\'\n                `Delay_idle: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:46: syntax error, unexpected \':\', expecting endcase\n                `Delay_idle: begin\n                           ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:48: Define or directive not defined: \'`Delay_hold\'\n                        current_state <= `Delay_hold;\n                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:51: Define or directive not defined: \'`Delay_hold\'\n                `Delay_hold: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:51: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `Delay_hold: begin\n                             ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:53: Define or directive not defined: \'`Delay_done\'\n                        current_state <= `Delay_done;\n                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:56: Define or directive not defined: \'`Delay_done\'\n                `Delay_done: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:58: Define or directive not defined: \'`Delay_idle\'\n                        current_state <= `Delay_idle;\n                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:62: Define or directive not defined: \'`Delay_idle\'\n                    current_state <= `Delay_idle;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/delay_gen.v:73: Define or directive not defined: \'`Delay_hold\'\n            if(current_state == `Delay_hold) begin\n                                ^~~~~~~~~~~\n%Error: Cannot continue\n'
module delay_gen(
    clk,
    rst,
    delay_ms,
    delay_en,
    delay_fin
    );
    input clk, rst, delay_en;
    input [11:0] delay_ms;
    output delay_fin;

    reg [16:0] clk_counter;
    reg [11:0] ms_counter;
    reg [1:0]  current_state;

    assign delay_fin = (current_state == `Delay_done && delay_en == 1) ? 1 : 0;

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            current_state <= `Delay_idle;
        end else begin
            case(current_state)
                `Delay_idle: begin
                    if(delay_en) begin
                        current_state <= `Delay_hold;
                    end
                end
                `Delay_hold: begin
                    if(ms_counter == delay_ms) begin
                        current_state <= `Delay_done;
                    end
                end
                `Delay_done: begin
                    if(!delay_en) begin
                        current_state <= `Delay_idle;
                    end
                end
                default: begin
                    current_state <= `Delay_idle;
                end
            endcase
        end
    end

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            clk_counter <= 17'b0;
            ms_counter  <= 12'b0;
        end else begin
            if(current_state == `Delay_hold) begin
                if(clk_counter == 17'b11000011010100000) begin

                    clk_counter <= 17'b0;
                    ms_counter <= ms_counter + 1;
                end else begin
                    clk_counter <= clk_counter + 1;
                end
            end else begin
                clk_counter <= 17'b0;
                ms_counter <= 12'b0;
            end
        end
    end

endmodule
module delay_gen(
    clk,
    rst,
    delay_ms,
    delay_en,
    delay_fin
    );

    input clk, rst, delay_en;
    input [11:0] delay_ms;
    output delay_fin;

    reg [16:0] clk_counter;
    reg [11:0] ms_counter;
    reg [1:0]  current_state;

    assign delay_fin = (current_state == `Delay_done && delay_en == 1) ? 1 : 0;

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            current_state <= `Delay_idle;
        end else begin
            case(current_state)
                `Delay_idle: begin
                    if(delay_en) begin
                        current_state <= `Delay_hold;
                    end
                end
                `Delay_hold: begin
                    if(ms_counter == delay_ms) begin
                        current_state <= `Delay_done;
                    end
                end
                `Delay_done: begin
                    if(!delay_en) begin
                        current_state <= `Delay_idle;
                    end
                end
                default: begin
                    current_state <= `Delay_idle;
                end
            endcase
        end
    end

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            clk_counter <= 17'b0;
            ms_counter  <= 12'b0;
        end else begin
            if(current_state == `Delay_hold) begin
                if(clk_counter == 17'b11000011010100000) begin

                    clk_counter <= 17'b0;
                    ms_counter <= ms_counter + 1;
                end else begin
                    clk_counter <= clk_counter + 1;
                end
            end else begin
                clk_counter <= 17'b0;
                ms_counter <= 12'b0;
            end
        end
    end

endmodule