data/full_repos/permissive/170402453/PhaseDetector.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170402453/PhaseDetector.v:57: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'PhaseO\' generates 12 bits.\n                                                                       : ... In instance PhaseDetector\n  assign PhaseOUT = PhaseO;  \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module PhaseDetector(
    input CLK,
    input Phase1,
    input Phase2,
    output [15:0] PhaseOUT,
	 output LeftFirst,
	 output SignalDetect
    );
	 



	 


	 
	 reg SetPhase, Left, LeftO, Detect, P1, P2, PSet1, PSet2; 
	 reg [11:0] Counter, PhaseO;
	 reg [26:0] SignalCounter;
	 
	 wire P1O, P2O;
	 
	 initial begin
		SetPhase = 0;
		Left = 0;
		LeftO = 0;
		Counter = 0;
		PhaseO = 0;
		SignalCounter = 0;
		P1 = 0;
		P2 = 0;
		PSet1 = 0;
		PSet2 = 0;
	 end
	 
	 assign LeftFirst = LeftO;
	 assign PhaseOUT = PhaseO;
	 assign SignalDetect = Detect;
	 
	 xor(P1O, P1, PSet1);
	 xor(P2O, P2, PSet2);
	 
	 always @(posedge Phase1) begin
		P1 = ~P1;
	 end
	 
	 always @(posedge Phase2) begin
		P2 = ~P2;
	 end
	 
	 always @(posedge CLK) begin

		if(Phase1 | Phase2) begin
			SignalCounter <= 0;
			Detect <= 1;
		end else begin
			if(SignalCounter > 100_000_000) begin
				Detect <= 0;
			end else begin
				SignalCounter <= SignalCounter+1;
			end
		end
	  end
	  

	  always @ (negedge CLK) begin
		if(SetPhase) begin

			if(Left) begin
				if(P2O) begin
					PSet2 <= ~PSet2;
					PhaseO <= Counter;
					LeftO <= 1;
					SetPhase <= 0;
				end
			end else begin
				if(P1O) begin
					PSet1 <= ~PSet1;
					PhaseO <= Counter;
					LeftO <= 0;
					SetPhase <= 0;
				end
			end
			Counter <= Counter+1;
		end else begin
			if(P1O) begin
				PSet1 <= ~PSet1;
				Left <= 1;
				SetPhase <= 1;
			end else if(P2O) begin
				PSet2 <= ~PSet2;
				Left <= 0;
				SetPhase <= 1;
			end else begin
				
				Counter <= 0;
			end
		end
	 end
endmodule
module PhaseDetector(
    input CLK,
    input Phase1,
    input Phase2,
    output [15:0] PhaseOUT,
	 output LeftFirst,
	 output SignalDetect
    );

	 



	 


	 
	 reg SetPhase, Left, LeftO, Detect, P1, P2, PSet1, PSet2; 
	 reg [11:0] Counter, PhaseO;
	 reg [26:0] SignalCounter;
	 
	 wire P1O, P2O;
	 
	 initial begin
		SetPhase = 0;
		Left = 0;
		LeftO = 0;
		Counter = 0;
		PhaseO = 0;
		SignalCounter = 0;
		P1 = 0;
		P2 = 0;
		PSet1 = 0;
		PSet2 = 0;
	 end
	 
	 assign LeftFirst = LeftO;
	 assign PhaseOUT = PhaseO;
	 assign SignalDetect = Detect;
	 
	 xor(P1O, P1, PSet1);
	 xor(P2O, P2, PSet2);
	 
	 always @(posedge Phase1) begin
		P1 = ~P1;
	 end
	 
	 always @(posedge Phase2) begin
		P2 = ~P2;
	 end
	 
	 always @(posedge CLK) begin

		if(Phase1 | Phase2) begin
			SignalCounter <= 0;
			Detect <= 1;
		end else begin
			if(SignalCounter > 100_000_000) begin
				Detect <= 0;
			end else begin
				SignalCounter <= SignalCounter+1;
			end
		end
	  end
	  

	  always @ (negedge CLK) begin
		if(SetPhase) begin

			if(Left) begin
				if(P2O) begin
					PSet2 <= ~PSet2;
					PhaseO <= Counter;
					LeftO <= 1;
					SetPhase <= 0;
				end
			end else begin
				if(P1O) begin
					PSet1 <= ~PSet1;
					PhaseO <= Counter;
					LeftO <= 0;
					SetPhase <= 0;
				end
			end
			Counter <= Counter+1;
		end else begin
			if(P1O) begin
				PSet1 <= ~PSet1;
				Left <= 1;
				SetPhase <= 1;
			end else if(P2O) begin
				PSet2 <= ~PSet2;
				Left <= 0;
				SetPhase <= 1;
			end else begin
				
				Counter <= 0;
			end
		end
	 end
endmodule