data/full_repos/permissive/143278/ivltests/vhdl_subprogram.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_subprogram.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1;    \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_subprogram.v:28: Can\'t find definition of \'negated\' in dotted variable: \'dut.negated\'\n    if(dut.negated !== \'b00111000) begin\n           ^~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_subprogram.v:33: Can\'t find definition of \'reversed\' in dotted variable: \'dut.reversed\'\n    if(dut.reversed != \'b11100001) begin\n           ^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module subprogram_test;
  subprogram dut();

  initial begin
    #1;

    if(dut.negated !== 'b00111000) begin
      $display("FAILED 1");
      $finish;
    end

    if(dut.reversed != 'b11100001) begin
      $display("FAILED 2");
      $finish;
    end

    $display("PASSED");
  end
endmodule
module subprogram_test;

  subprogram dut();

  initial begin
    #1;

    if(dut.negated !== 'b00111000) begin
      $display("FAILED 1");
      $finish;
    end

    if(dut.reversed != 'b11100001) begin
      $display("FAILED 2");
      $finish;
    end

    $display("PASSED");
  end
endmodule