data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n always #0.5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:37: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile(`VCD_OUTPUT".vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:37: Define or directive not defined: \'`VCD_OUTPUT\'\n  $dumpfile(`VCD_OUTPUT".vcd");\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:38: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, buspirate_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #0 rst <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #1 rst <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #1 mc_ce <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #1 mc_oe <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #5 mc_ce <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #1 mc_ce <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #5 mc_ce <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #1 mc_ce <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #1 mc_oe <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #5 mc_ce <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/mcutest/buspirate_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #(DURATION) $display("End of simulation");\n  ^\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module buspirate_tb();

  parameter DURATION = 50;

  localparam MC_DATA_WIDTH = 16;
  localparam MC_ADD_WIDTH = 6;

  reg clk=0, rst;

  reg mc_oe, mc_ce, mc_we;
  reg [MC_ADD_WIDTH-1:0] mc_add;
  wire [MC_DATA_WIDTH-1:0] mc_data;
  reg [MC_DATA_WIDTH-1:0] mc_data_reg;

  assign mc_data=(mc_oe)?mc_data_reg:16'hzzzz;

  top buspirate(
    .clock(clk),
    .reset(rst),
    .mc_oe(mc_oe),
    .mc_ce(mc_ce),
    .mc_we(mc_we),
    .mc_add(mc_add),
    .mc_data(mc_data)
    );


	always #0.5 clk = ~clk;



	initial begin

		$dumpfile(`DUMPSTR(`VCD_OUTPUT));
		$dumpvars(0, buspirate_tb);

		#0	rst <= 1;
			mc_oe <= 1;
			mc_we <= 1;
			mc_ce <= 1;
		#1	rst <= 0;
			mc_add <= 6'h00;


		#1	mc_ce <= 0;
		#1	mc_oe <= 0;
		#5	mc_ce <= 1;
			mc_oe <= 1;


		#1	mc_ce <= 0;
			mc_we <= 0;
			mc_data_reg <= 16'hAA55;
		#5	mc_ce <= 1;
			mc_we <= 1;


		#1	mc_ce <= 0;
		#1	mc_oe <= 0;
		#5	mc_ce <= 1;
			mc_oe <= 1;

		#(DURATION) $display("End of simulation");
	$finish;
end

endmodule
module buspirate_tb();


  parameter DURATION = 50;

  localparam MC_DATA_WIDTH = 16;
  localparam MC_ADD_WIDTH = 6;

  reg clk=0, rst;

  reg mc_oe, mc_ce, mc_we;
  reg [MC_ADD_WIDTH-1:0] mc_add;
  wire [MC_DATA_WIDTH-1:0] mc_data;
  reg [MC_DATA_WIDTH-1:0] mc_data_reg;

  assign mc_data=(mc_oe)?mc_data_reg:16'hzzzz;

  top buspirate(
    .clock(clk),
    .reset(rst),
    .mc_oe(mc_oe),
    .mc_ce(mc_ce),
    .mc_we(mc_we),
    .mc_add(mc_add),
    .mc_data(mc_data)
    );


	always #0.5 clk = ~clk;



	initial begin

		$dumpfile(`DUMPSTR(`VCD_OUTPUT));
		$dumpvars(0, buspirate_tb);

		#0	rst <= 1;
			mc_oe <= 1;
			mc_we <= 1;
			mc_ce <= 1;
		#1	rst <= 0;
			mc_add <= 6'h00;


		#1	mc_ce <= 0;
		#1	mc_oe <= 0;
		#5	mc_ce <= 1;
			mc_oe <= 1;


		#1	mc_ce <= 0;
			mc_we <= 0;
			mc_data_reg <= 16'hAA55;
		#5	mc_ce <= 1;
			mc_we <= 1;


		#1	mc_ce <= 0;
		#1	mc_oe <= 0;
		#5	mc_ce <= 1;
			mc_oe <= 1;

		#(DURATION) $display("End of simulation");
	$finish;
end

endmodule