data/full_repos/permissive/114324064/src/ex.v
1: b'%Error: data/full_repos/permissive/114324064/src/ex.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.v\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/114324064/src/ex.v:8: Define or directive not defined: \'`AluOpBus\'\n    input wire[`AluOpBus]         aluop_i,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`AluOpBus]         aluop_i,\n                        ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:9: Define or directive not defined: \'`AluSelBus\'\n    input wire[`AluSelBus]        alusel_i,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:10: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus]           reg1_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:11: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus]           reg2_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:12: Define or directive not defined: \'`RegAddrBus\'\n    input wire[`RegAddrBus]       wd_i,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`RegBus]           link_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:15: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus]           link_addr_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:16: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus]           offset_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:19: Define or directive not defined: \'`RegAddrBus\'\n    output reg[`RegAddrBus]       wd_o,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:21: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[`RegBus]           wdata_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:21: Define or directive not defined: \'`RegBus\'\n    output reg[`RegBus]           wdata_o,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:23: Define or directive not defined: \'`AluOpBus\'\n    output wire[`AluOpBus]         aluop_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:24: Define or directive not defined: \'`RegBus\'\n    output wire[`RegBus]           mem_addr_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:25: Define or directive not defined: \'`RegBus\'\n    output wire[`RegBus]           reg2_o\n                ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:28: Define or directive not defined: \'`RegBus\'\n    reg[`RegBus] logicout;\n        ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`RegBus] logicout;\n               ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:29: Define or directive not defined: \'`RegBus\'\n    reg[`RegBus] shiftres;\n        ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`RegBus] shiftres;\n               ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:30: Define or directive not defined: \'`RegBus\'\n    reg[`RegBus] arithmeticres;\n        ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`RegBus] arithmeticres;\n               ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:34: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] reg2_i_mux;\n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] reg2_i_mux;\n                ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:35: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] reg1_i_not;\n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] reg1_i_not;\n                ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:36: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] result_sum;  \n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] result_sum;  \n                ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:39: Define or directive not defined: \'`NoStop\'\n    assign stallreq = `NoStop;\n                      ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:40: Define or directive not defined: \'`EXE_SUB_OP\'\n    assign reg2_i_mux = ((aluop_i == `EXE_SUB_OP) ||\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:41: Define or directive not defined: \'`EXE_SLT_OP\'\n                         (aluop_i == `EXE_SLT_OP)) ?\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:44: Define or directive not defined: \'`EXE_SLT_OP\'\n    assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP) ?\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:57: Define or directive not defined: \'`RstEnable\'\n        if(rst == `RstEnable) begin\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:58: Define or directive not defined: \'`ZeroWord\'\n            logicout <= `ZeroWord;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:61: Define or directive not defined: \'`EXE_OR_OP\'\n                `EXE_OR_OP: begin\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:64: Define or directive not defined: \'`EXE_AND_OP\'\n                `EXE_AND_OP: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:67: Define or directive not defined: \'`EXE_XOR_OP\'\n                `EXE_XOR_OP: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:70: Define or directive not defined: \'`EXE_LUI_OP\'\n                `EXE_LUI_OP: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:74: Define or directive not defined: \'`ZeroWord\'\n                    logicout <= `ZeroWord;\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:81: Define or directive not defined: \'`RstEnable\'\n        if(rst == `RstEnable) begin\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:82: Define or directive not defined: \'`ZeroWord\'\n            shiftres <= `ZeroWord;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:85: Define or directive not defined: \'`EXE_SLL_OP\'\n                `EXE_SLL_OP: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:88: Define or directive not defined: \'`EXE_SRL_OP\'\n                `EXE_SRL_OP: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:91: Define or directive not defined: \'`EXE_SRA_OP\'\n                `EXE_SRA_OP: begin  \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:96: Define or directive not defined: \'`ZeroWord\'\n                    shiftres <= `ZeroWord;\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:103: Define or directive not defined: \'`RstEnable\'\n        if(rst == `RstEnable) begin\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:104: Define or directive not defined: \'`ZeroWord\'\n            arithmeticres <= `ZeroWord;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:107: Define or directive not defined: \'`EXE_SLT_OP\'\n                `EXE_SLT_OP, `EXE_SLTU_OP: begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:107: Define or directive not defined: \'`EXE_SLTU_OP\'\n                `EXE_SLT_OP, `EXE_SLTU_OP: begin\n                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:110: Define or directive not defined: \'`EXE_ADD_OP\'\n                `EXE_ADD_OP, `EXE_ADDI_OP: begin\n                ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ex(

    input wire                    rst,


    input wire[`AluOpBus]         aluop_i,
    input wire[`AluSelBus]        alusel_i,
    input wire[`RegBus]           reg1_i,
    input wire[`RegBus]           reg2_i,
    input wire[`RegAddrBus]       wd_i,
    input wire                    wreg_i,

    input wire[`RegBus]           link_addr_i,
    input wire[`RegBus]           offset_i,


    output reg[`RegAddrBus]       wd_o,
    output reg                    wreg_o,
    output reg[`RegBus]           wdata_o,

    output wire[`AluOpBus]         aluop_o,
    output wire[`RegBus]           mem_addr_o,
    output wire[`RegBus]           reg2_o
);

    reg[`RegBus] logicout;
    reg[`RegBus] shiftres;
    reg[`RegBus] arithmeticres;

    wire reg1_eq_reg2;
    wire reg1_lt_reg2;
    wire[`RegBus] reg2_i_mux;
    wire[`RegBus] reg1_i_not;
    wire[`RegBus] result_sum;


    assign stallreq = `NoStop;
    assign reg2_i_mux = ((aluop_i == `EXE_SUB_OP) ||
                         (aluop_i == `EXE_SLT_OP)) ?
                         (~reg2_i) + 1 : reg2_i;
    assign result_sum = reg1_i + reg2_i_mux;
    assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP) ?
                          ((reg1_i[31] && !reg2_i[31]) ||
                           (!reg1_i[31] && !reg2_i[31] && result_sum[31]) ||
                           (reg1_i[31] && reg1_i[31] && result_sum[31])) :
                          (reg1_i < reg2_i);
    assign reg1_i_not = ~reg1_i;
    assign aluop_o = aluop_i;
    assign mem_addr_o = reg1_i + offset_i;
    assign reg2_o = reg2_i;



    always @ (*) begin
        if(rst == `RstEnable) begin
            logicout <= `ZeroWord;
        end else begin
            case (aluop_i)
                `EXE_OR_OP: begin
                    logicout <= reg1_i | reg2_i;
                end
                `EXE_AND_OP: begin
                    logicout <= reg1_i & reg2_i;
                end
                `EXE_XOR_OP: begin
                    logicout <= reg1_i ^ reg2_i;
                end
                `EXE_LUI_OP: begin
                    
                end
                default: begin
                    logicout <= `ZeroWord;
                end
            endcase
        end
    end

    always @ (*) begin
        if(rst == `RstEnable) begin
            shiftres <= `ZeroWord;
        end else begin
            case (aluop_i)
                `EXE_SLL_OP: begin
                    shiftres <= reg1_i << reg2_i[4:0];
                end
                `EXE_SRL_OP: begin
                    shiftres <= reg1_i >> reg2_i[4:0];
                end
                `EXE_SRA_OP: begin
                    shiftres <= ({32{reg1_i[31]}} << (6'd32 - {1'b0,reg2_i[4:0]})) |
                                (reg1_i >> reg2_i[4:0]);
                end
                default: begin
                    shiftres <= `ZeroWord;
                end
            endcase
        end
    end

    always @ (*) begin
        if(rst == `RstEnable) begin
            arithmeticres <= `ZeroWord;
        end else begin
            case (aluop_i)
                `EXE_SLT_OP, `EXE_SLTU_OP: begin
                    arithmeticres <= reg1_lt_reg2;
                end
                `EXE_ADD_OP, `EXE_ADDI_OP: begin
                    arithmeticres <= result_sum;
                end
                `EXE_SUB_OP: begin
                    arithmeticres <= result_sum;
                end
                default: begin
                    arithmeticres <= `ZeroWord;
                end
            endcase
        end
    end


    always @ ( * ) begin
        wd_o <= wd_i;
        wreg_o <= wreg_i;
        case (alusel_i)
            `EXE_RES_LOGIC: begin
                wdata_o <= logicout;
            end
            `EXE_RES_SHIFT: begin
                wdata_o <= shiftres;
            end
            `EXE_RES_ARITHMETIC: begin
                wdata_o <= arithmeticres;
            end
            `EXE_RES_JUMP_BRANCH: begin
                wdata_o <= link_addr_i;
            end
            default: begin
                wdata_o <= `ZeroWord;
            end
        endcase
    end

endmodule
module ex(

    input wire                    rst,


    input wire[`AluOpBus]         aluop_i,
    input wire[`AluSelBus]        alusel_i,
    input wire[`RegBus]           reg1_i,
    input wire[`RegBus]           reg2_i,
    input wire[`RegAddrBus]       wd_i,
    input wire                    wreg_i,

    input wire[`RegBus]           link_addr_i,
    input wire[`RegBus]           offset_i,


    output reg[`RegAddrBus]       wd_o,
    output reg                    wreg_o,
    output reg[`RegBus]           wdata_o,

    output wire[`AluOpBus]         aluop_o,
    output wire[`RegBus]           mem_addr_o,
    output wire[`RegBus]           reg2_o
);


    reg[`RegBus] logicout;
    reg[`RegBus] shiftres;
    reg[`RegBus] arithmeticres;

    wire reg1_eq_reg2;
    wire reg1_lt_reg2;
    wire[`RegBus] reg2_i_mux;
    wire[`RegBus] reg1_i_not;
    wire[`RegBus] result_sum;


    assign stallreq = `NoStop;
    assign reg2_i_mux = ((aluop_i == `EXE_SUB_OP) ||
                         (aluop_i == `EXE_SLT_OP)) ?
                         (~reg2_i) + 1 : reg2_i;
    assign result_sum = reg1_i + reg2_i_mux;
    assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP) ?
                          ((reg1_i[31] && !reg2_i[31]) ||
                           (!reg1_i[31] && !reg2_i[31] && result_sum[31]) ||
                           (reg1_i[31] && reg1_i[31] && result_sum[31])) :
                          (reg1_i < reg2_i);
    assign reg1_i_not = ~reg1_i;
    assign aluop_o = aluop_i;
    assign mem_addr_o = reg1_i + offset_i;
    assign reg2_o = reg2_i;



    always @ (*) begin
        if(rst == `RstEnable) begin
            logicout <= `ZeroWord;
        end else begin
            case (aluop_i)
                `EXE_OR_OP: begin
                    logicout <= reg1_i | reg2_i;
                end
                `EXE_AND_OP: begin
                    logicout <= reg1_i & reg2_i;
                end
                `EXE_XOR_OP: begin
                    logicout <= reg1_i ^ reg2_i;
                end
                `EXE_LUI_OP: begin
                    
                end
                default: begin
                    logicout <= `ZeroWord;
                end
            endcase
        end
    end

    always @ (*) begin
        if(rst == `RstEnable) begin
            shiftres <= `ZeroWord;
        end else begin
            case (aluop_i)
                `EXE_SLL_OP: begin
                    shiftres <= reg1_i << reg2_i[4:0];
                end
                `EXE_SRL_OP: begin
                    shiftres <= reg1_i >> reg2_i[4:0];
                end
                `EXE_SRA_OP: begin
                    shiftres <= ({32{reg1_i[31]}} << (6'd32 - {1'b0,reg2_i[4:0]})) |
                                (reg1_i >> reg2_i[4:0]);
                end
                default: begin
                    shiftres <= `ZeroWord;
                end
            endcase
        end
    end

    always @ (*) begin
        if(rst == `RstEnable) begin
            arithmeticres <= `ZeroWord;
        end else begin
            case (aluop_i)
                `EXE_SLT_OP, `EXE_SLTU_OP: begin
                    arithmeticres <= reg1_lt_reg2;
                end
                `EXE_ADD_OP, `EXE_ADDI_OP: begin
                    arithmeticres <= result_sum;
                end
                `EXE_SUB_OP: begin
                    arithmeticres <= result_sum;
                end
                default: begin
                    arithmeticres <= `ZeroWord;
                end
            endcase
        end
    end


    always @ ( * ) begin
        wd_o <= wd_i;
        wreg_o <= wreg_i;
        case (alusel_i)
            `EXE_RES_LOGIC: begin
                wdata_o <= logicout;
            end
            `EXE_RES_SHIFT: begin
                wdata_o <= shiftres;
            end
            `EXE_RES_ARITHMETIC: begin
                wdata_o <= arithmeticres;
            end
            `EXE_RES_JUMP_BRANCH: begin
                wdata_o <= link_addr_i;
            end
            default: begin
                wdata_o <= `ZeroWord;
            end
        endcase
    end

endmodule