data/full_repos/permissive/143278/ivltests/pr1444055.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1444055.v:21: Unsupported: Ignoring delay on this delayed statement.\n   aa=2\'b00; #100;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1444055.v:26: Unsupported: Ignoring delay on this delayed statement.\n   aa=2\'b11; #100;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1444055.v:31: Unsupported: Ignoring delay on this delayed statement.\n   aa=2\'b00; #100;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1444055.v:36: Unsupported: Ignoring delay on this delayed statement.\n   aa=2\'b11; #100;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1444055.v:43: Unsupported: Ignoring delay on this delayed statement.\n   aa=2\'b00; #100;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1444055.v:48: Unsupported: Ignoring delay on this delayed statement.\n   aa=2\'b11; #100;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1444055.v:53: Unsupported: Ignoring delay on this delayed statement.\n   aa=2\'b00; #100;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1444055.v:58: Unsupported: Ignoring delay on this delayed statement.\n   aa=2\'b11; #100;\n             ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();
   reg [1:0] aa;
   wire [1:0] zz;
   reg [1:0]  ee;

   bts sub1 (.z(zz[1]), .a(aa[1]), .e(ee[1]));
   bts sub0 (.z(zz[0]), .a(aa[0]), .e(ee[0]));


  initial begin

   ee=2'b00;
   aa=2'b00; #100;
   if (zz !== 2'bzz) begin
      $display("FAILED -- (1) All disabled, expected HiZ, got %b", zz);
      $finish;
   end
   aa=2'b11; #100;
   if (zz !== 2'bzz) begin
      $display("FAILED -- (2) All disabled, expected HiZ, got %b", zz);
      $finish;
   end
   aa=2'b00; #100;
   if (zz !== 2'bzz) begin
      $display("FAILED -- (3) All disabled, expected HiZ, got %b", zz);
      $finish;
   end
   aa=2'b11; #100;
   if (zz !== 2'bzz) begin
      $display("FAILED -- (4) All disabled, expected HiZ, got %b", zz);
      $finish;
   end

   ee=2'b11;
   aa=2'b00; #100;
   if (zz !== 2'b00) begin
      $display("FAILED -- (5) All enabled, expected 00, got %b", zz);
      $finish;
   end
   aa=2'b11; #100;
   if (zz !== 2'b11) begin
      $display("FAILED -- (6) All enabled, expected 11, got %b", zz);
      $finish;
   end
   aa=2'b00; #100;
   if (zz !== 2'b00) begin
      $display("FAILED -- (7) All enabled, expected 00, got %b", zz);
      $finish;
   end
   aa=2'b11; #100;
   if (zz !== 2'b11) begin
      $display("FAILED -- (8) All enabled, expected 11, got %b", zz);
      $finish;
   end

   $display("PASSED");
  end
endmodule
module test();

   reg [1:0] aa;
   wire [1:0] zz;
   reg [1:0]  ee;

   bts sub1 (.z(zz[1]), .a(aa[1]), .e(ee[1]));
   bts sub0 (.z(zz[0]), .a(aa[0]), .e(ee[0]));


  initial begin

   ee=2'b00;
   aa=2'b00; #100;
   if (zz !== 2'bzz) begin
      $display("FAILED -- (1) All disabled, expected HiZ, got %b", zz);
      $finish;
   end
   aa=2'b11; #100;
   if (zz !== 2'bzz) begin
      $display("FAILED -- (2) All disabled, expected HiZ, got %b", zz);
      $finish;
   end
   aa=2'b00; #100;
   if (zz !== 2'bzz) begin
      $display("FAILED -- (3) All disabled, expected HiZ, got %b", zz);
      $finish;
   end
   aa=2'b11; #100;
   if (zz !== 2'bzz) begin
      $display("FAILED -- (4) All disabled, expected HiZ, got %b", zz);
      $finish;
   end

   ee=2'b11;
   aa=2'b00; #100;
   if (zz !== 2'b00) begin
      $display("FAILED -- (5) All enabled, expected 00, got %b", zz);
      $finish;
   end
   aa=2'b11; #100;
   if (zz !== 2'b11) begin
      $display("FAILED -- (6) All enabled, expected 11, got %b", zz);
      $finish;
   end
   aa=2'b00; #100;
   if (zz !== 2'b00) begin
      $display("FAILED -- (7) All enabled, expected 00, got %b", zz);
      $finish;
   end
   aa=2'b11; #100;
   if (zz !== 2'b11) begin
      $display("FAILED -- (8) All enabled, expected 11, got %b", zz);
      $finish;
   end

   $display("PASSED");
  end
endmodule