data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v:1: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: Exiting due to 1 error(s)\n'
module s2p_synth(IN_CLK_s2p, IN_LANE_s2p, IN_MODO_s2p, IN_DIR_s2p, IN_ENB_s2p, OUT_LANE3_s2p, OUT_LANE2_s2p, OUT_LANE1_s2p, OUT_LANE0_s2p);
  input [1:0] IN_CLK_s2p;
  input IN_DIR_s2p;
  input IN_ENB_s2p;
  input [3:0] IN_LANE_s2p;
  input [1:0] IN_MODO_s2p;
  output [7:0] OUT_LANE0_s2p;
  output [7:0] OUT_LANE1_s2p;
  output [7:0] OUT_LANE2_s2p;
  output [7:0] OUT_LANE3_s2p;
  wire [7:0] P0_synth_s2p;
  wire [7:0] P1_synth_s2p;
  wire [7:0] P2_synth_s2p;
  wire [7:0] P3_synth_s2p;
  ffd_s2p_synth \ffd_lane0[0]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[0]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[0])
  );
  ffd_s2p_synth \ffd_lane0[1]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[1]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[1])
  );
  ffd_s2p_synth \ffd_lane0[2]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[2]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[2])
  );
  ffd_s2p_synth \ffd_lane0[3]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[3]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[3])
  );
  ffd_s2p_synth \ffd_lane0[4]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[4]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[4])
  );
  ffd_s2p_synth \ffd_lane0[5]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[5]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[5])
  );
  ffd_s2p_synth \ffd_lane0[6]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[6]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[6])
  );
  ffd_s2p_synth \ffd_lane0[7]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[7]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[7])
  );
  ffd_s2p_synth \ffd_lane1[0]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[0]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[0])
  );
  ffd_s2p_synth \ffd_lane1[1]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[1]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[1])
  );
  ffd_s2p_synth \ffd_lane1[2]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[2]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[2])
  );
  ffd_s2p_synth \ffd_lane1[3]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[3]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[3])
  );
  ffd_s2p_synth \ffd_lane1[4]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[4]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[4])
  );
  ffd_s2p_synth \ffd_lane1[5]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[5]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[5])
  );
  ffd_s2p_synth \ffd_lane1[6]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[6]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[6])
  );
  ffd_s2p_synth \ffd_lane1[7]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[7]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[7])
  );
  ffd_s2p_synth \ffd_lane2[0]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[0]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[0])
  );
  ffd_s2p_synth \ffd_lane2[1]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[1]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[1])
  );
  ffd_s2p_synth \ffd_lane2[2]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[2]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[2])
  );
  ffd_s2p_synth \ffd_lane2[3]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[3]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[3])
  );
  ffd_s2p_synth \ffd_lane2[4]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[4]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[4])
  );
  ffd_s2p_synth \ffd_lane2[5]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[5]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[5])
  );
  ffd_s2p_synth \ffd_lane2[6]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[6]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[6])
  );
  ffd_s2p_synth \ffd_lane2[7]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[7]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[7])
  );
  ffd_s2p_synth \ffd_lane3[0]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[0]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[0])
  );
  ffd_s2p_synth \ffd_lane3[1]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[1]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[1])
  );
  ffd_s2p_synth \ffd_lane3[2]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[2]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[2])
  );
  ffd_s2p_synth \ffd_lane3[3]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[3]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[3])
  );
  ffd_s2p_synth \ffd_lane3[4]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[4]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[4])
  );
  ffd_s2p_synth \ffd_lane3[5]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[5]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[5])
  );
  ffd_s2p_synth \ffd_lane3[6]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[6]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[6])
  );
  ffd_s2p_synth \ffd_lane3[7]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[7]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[7])
  );
  s2p_reg_synth reg_lane0 (
    .CLK(IN_CLK_s2p[0]),
    .DIR(IN_DIR_s2p),
    .ENB(IN_ENB_s2p),
    .MODO(IN_MODO_s2p),
    .Q(P0_synth_s2p),
    .S_IN(IN_LANE_s2p[0])
  );
  s2p_reg_synth reg_lane1 (
    .CLK(IN_CLK_s2p[0]),
    .DIR(IN_DIR_s2p),
    .ENB(IN_ENB_s2p),
    .MODO(IN_MODO_s2p),
    .Q(P1_synth_s2p),
    .S_IN(IN_LANE_s2p[1])
  );
  s2p_reg_synth reg_lane2 (
    .CLK(IN_CLK_s2p[0]),
    .DIR(IN_DIR_s2p),
    .ENB(IN_ENB_s2p),
    .MODO(IN_MODO_s2p),
    .Q(P2_synth_s2p),
    .S_IN(IN_LANE_s2p[2])
  );
  s2p_reg_synth reg_lane3 (
    .CLK(IN_CLK_s2p[0]),
    .DIR(IN_DIR_s2p),
    .ENB(IN_ENB_s2p),
    .MODO(IN_MODO_s2p),
    .Q(P3_synth_s2p),
    .S_IN(IN_LANE_s2p[3])
  );
endmodule
module s2p_synth(IN_CLK_s2p, IN_LANE_s2p, IN_MODO_s2p, IN_DIR_s2p, IN_ENB_s2p, OUT_LANE3_s2p, OUT_LANE2_s2p, OUT_LANE1_s2p, OUT_LANE0_s2p);

  input [1:0] IN_CLK_s2p;
  input IN_DIR_s2p;
  input IN_ENB_s2p;
  input [3:0] IN_LANE_s2p;
  input [1:0] IN_MODO_s2p;
  output [7:0] OUT_LANE0_s2p;
  output [7:0] OUT_LANE1_s2p;
  output [7:0] OUT_LANE2_s2p;
  output [7:0] OUT_LANE3_s2p;
  wire [7:0] P0_synth_s2p;
  wire [7:0] P1_synth_s2p;
  wire [7:0] P2_synth_s2p;
  wire [7:0] P3_synth_s2p;
  ffd_s2p_synth \ffd_lane0[0]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[0]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[0])
  );
  ffd_s2p_synth \ffd_lane0[1]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[1]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[1])
  );
  ffd_s2p_synth \ffd_lane0[2]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[2]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[2])
  );
  ffd_s2p_synth \ffd_lane0[3]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[3]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[3])
  );
  ffd_s2p_synth \ffd_lane0[4]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[4]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[4])
  );
  ffd_s2p_synth \ffd_lane0[5]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[5]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[5])
  );
  ffd_s2p_synth \ffd_lane0[6]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[6]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[6])
  );
  ffd_s2p_synth \ffd_lane0[7]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P0_synth_s2p[7]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE0_s2p[7])
  );
  ffd_s2p_synth \ffd_lane1[0]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[0]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[0])
  );
  ffd_s2p_synth \ffd_lane1[1]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[1]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[1])
  );
  ffd_s2p_synth \ffd_lane1[2]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[2]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[2])
  );
  ffd_s2p_synth \ffd_lane1[3]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[3]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[3])
  );
  ffd_s2p_synth \ffd_lane1[4]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[4]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[4])
  );
  ffd_s2p_synth \ffd_lane1[5]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[5]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[5])
  );
  ffd_s2p_synth \ffd_lane1[6]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[6]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[6])
  );
  ffd_s2p_synth \ffd_lane1[7]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P1_synth_s2p[7]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE1_s2p[7])
  );
  ffd_s2p_synth \ffd_lane2[0]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[0]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[0])
  );
  ffd_s2p_synth \ffd_lane2[1]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[1]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[1])
  );
  ffd_s2p_synth \ffd_lane2[2]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[2]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[2])
  );
  ffd_s2p_synth \ffd_lane2[3]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[3]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[3])
  );
  ffd_s2p_synth \ffd_lane2[4]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[4]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[4])
  );
  ffd_s2p_synth \ffd_lane2[5]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[5]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[5])
  );
  ffd_s2p_synth \ffd_lane2[6]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[6]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[6])
  );
  ffd_s2p_synth \ffd_lane2[7]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P2_synth_s2p[7]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE2_s2p[7])
  );
  ffd_s2p_synth \ffd_lane3[0]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[0]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[0])
  );
  ffd_s2p_synth \ffd_lane3[1]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[1]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[1])
  );
  ffd_s2p_synth \ffd_lane3[2]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[2]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[2])
  );
  ffd_s2p_synth \ffd_lane3[3]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[3]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[3])
  );
  ffd_s2p_synth \ffd_lane3[4]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[4]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[4])
  );
  ffd_s2p_synth \ffd_lane3[5]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[5]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[5])
  );
  ffd_s2p_synth \ffd_lane3[6]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[6]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[6])
  );
  ffd_s2p_synth \ffd_lane3[7]  (
    .CLK(IN_CLK_s2p[1]),
    .D(P3_synth_s2p[7]),
    .ENB(IN_ENB_s2p),
    .Q(OUT_LANE3_s2p[7])
  );
  s2p_reg_synth reg_lane0 (
    .CLK(IN_CLK_s2p[0]),
    .DIR(IN_DIR_s2p),
    .ENB(IN_ENB_s2p),
    .MODO(IN_MODO_s2p),
    .Q(P0_synth_s2p),
    .S_IN(IN_LANE_s2p[0])
  );
  s2p_reg_synth reg_lane1 (
    .CLK(IN_CLK_s2p[0]),
    .DIR(IN_DIR_s2p),
    .ENB(IN_ENB_s2p),
    .MODO(IN_MODO_s2p),
    .Q(P1_synth_s2p),
    .S_IN(IN_LANE_s2p[1])
  );
  s2p_reg_synth reg_lane2 (
    .CLK(IN_CLK_s2p[0]),
    .DIR(IN_DIR_s2p),
    .ENB(IN_ENB_s2p),
    .MODO(IN_MODO_s2p),
    .Q(P2_synth_s2p),
    .S_IN(IN_LANE_s2p[2])
  );
  s2p_reg_synth reg_lane3 (
    .CLK(IN_CLK_s2p[0]),
    .DIR(IN_DIR_s2p),
    .ENB(IN_ENB_s2p),
    .MODO(IN_MODO_s2p),
    .Q(P3_synth_s2p),
    .S_IN(IN_LANE_s2p[3])
  );
endmodule