data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPRfunct.sv
 line:12: before: "S9"
1: b'%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPRfunct.sv:52: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPRfunct.sv:52: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPRfunct.sv:57: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                                             : ... In instance testbenchPPRfunct\n       currentvec = vectors[vectornum];\n                           ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FTCfunct(Cin, I1, I2, I3, I4, C, Cout, S);
  input Cin;
  input I1;
  input I2;
  input I3;
  input I4;
  output C;
  output Cout;
  output S;

 assign S = Cin ^ I1 ^ I2 ^ I3 ^ I4;
 assign C = ((I1 ^ I2 ^ I3) & I4) | ((I1 ^ I2 ^ I3) & Cin) | (I4 & Cin);
 assign Cout = (I1 & I2) | (I1 & I3) | (I2 & I3);
 
endmodule
module FTCfunct(Cin, I1, I2, I3, I4, C, Cout, S);

  input Cin;
  input I1;
  input I2;
  input I3;
  input I4;
  output C;
  output Cout;
  output S;

 assign S = Cin ^ I1 ^ I2 ^ I3 ^ I4;
 assign C = ((I1 ^ I2 ^ I3) & I4) | ((I1 ^ I2 ^ I3) & Cin) | (I4 & Cin);
 assign Cout = (I1 & I2) | (I1 & I3) | (I2 & I3);
 
endmodule