data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_top.v
 line:38: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_top.v:38: Unsupported: Ignoring delay on this delayed statement.\n    always #5 begin\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_top.v:48: syntax error, unexpected \'@\'\n                @(posedge clk)\n                ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_top.v:60: syntax error, unexpected \'@\'\n  @(posedge led[7])\n  ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_top();
	reg clk;
	reg rst;
	reg [7:0] sw;
	wire [7:0] led;

	top_module tm(
		.sysclk(clk), .cpu_resetn(~rst),
		.sw(sw), .led(led));

    initial begin
		clk <= 0;
		rst <= 0;
    end

    always #5 begin
        clk <= ~clk;
    end

    task wait_posedge_clk;
        input   n;
        integer n;

        begin
            for(n=n; n>0; n=n-1) begin
                @(posedge clk)
                    ;
            end
        end
    endtask

	initial begin
		wait_posedge_clk(1);
		rst <= 1;
		wait_posedge_clk(1);
		rst <= 0;
		sw[0] = 1;
		@(posedge led[7])
			;
		wait_posedge_clk(10);
		$finish;
	end

endmodule
module test_top();

	reg clk;
	reg rst;
	reg [7:0] sw;
	wire [7:0] led;

	top_module tm(
		.sysclk(clk), .cpu_resetn(~rst),
		.sw(sw), .led(led));

    initial begin
		clk <= 0;
		rst <= 0;
    end

    always #5 begin
        clk <= ~clk;
    end

    task wait_posedge_clk;
        input   n;
        integer n;

        begin
            for(n=n; n>0; n=n-1) begin
                @(posedge clk)
                    ;
            end
        end
    endtask

	initial begin
		wait_posedge_clk(1);
		rst <= 1;
		wait_posedge_clk(1);
		rst <= 0;
		sw[0] = 1;
		@(posedge led[7])
			;
		wait_posedge_clk(10);
		$finish;
	end

endmodule