data/full_repos/permissive/142505464/modules/wb_bfm_mod/bench/wb_bfm_mod_tb.v
 line:94: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/142505464/modules/wb_bfm_mod/bench/wb_bfm_mod_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n   always #5 wb_clk <= ~wb_clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/142505464/modules/wb_bfm_mod/bench/wb_bfm_mod_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n   initial  #100 wb_rst <= 0;\n            ^\n%Error: data/full_repos/permissive/142505464/modules/wb_bfm_mod/bench/wb_bfm_mod_tb.v:94: Can\'t find definition of \'set_transactions\' in dotted task/function: \'master.set_transactions\'\n master.set_transactions(TRANSACTIONS);\n        ^~~~~~~~~~~~~~~~\n        ... Known scopes under \'set_transactions\': <no cells found>\n%Error: data/full_repos/permissive/142505464/modules/wb_bfm_mod/bench/wb_bfm_mod_tb.v:96: Can\'t find definition of \'set_subtransactions\' in dotted task/function: \'master.set_subtransactions\'\n master.set_subtransactions(SUBTRANSACTIONS);\n        ^~~~~~~~~~~~~~~~~~~\n        ... Known scopes under \'set_subtransactions\': <no cells found>\n%Error: data/full_repos/permissive/142505464/modules/wb_bfm_mod/bench/wb_bfm_mod_tb.v:98: Can\'t find definition of \'SEED\' in dotted variable: \'master.SEED\'\n master.SEED = SEED;\n        ^~~~\n%Error: data/full_repos/permissive/142505464/modules/wb_bfm_mod/bench/wb_bfm_mod_tb.v:100: Can\'t find definition of \'display_settings\' in dotted task/function: \'master.display_settings\'\n      master.display_settings;\n             ^~~~~~~~~~~~~~~~\n        ... Known scopes under \'display_settings\': <no cells found>\n%Error: data/full_repos/permissive/142505464/modules/wb_bfm_mod/bench/wb_bfm_mod_tb.v:101: Can\'t find definition of \'run\' in dotted task/function: \'master.run\'\n      master.run;\n             ^~~\n        ... Known scopes under \'run\': <no cells found>\n%Error: data/full_repos/permissive/142505464/modules/wb_bfm_mod/bench/wb_bfm_mod_tb.v:102: Can\'t find definition of \'display_stats\' in dotted task/function: \'master.display_stats\'\n      master.display_stats;\n             ^~~~~~~~~~~~~\n        ... Known scopes under \'display_stats\': <no cells found>\n%Error: data/full_repos/permissive/142505464/modules/wb_bfm_mod/bench/wb_bfm_mod_tb.v:106: Can\'t find definition of \'ok\' in dotted task/function: \'vtg.ok\'\n      vtg.ok("All tests complete");\n          ^~\n        ... Known scopes under \'ok\': <no cells found>\n%Error: Exiting due to 7 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module wb_bfm_mod_tb;

   vlog_tb_utils vlog_tb_utils0();
   vlog_tap_generator #("wb_bfm_mod.tap", 1) vtg();

   localparam aw = 32;
   localparam dw = 32;

   reg	   wb_clk = 1'b1;
   reg	   wb_rst = 1'b1;

   always #5 wb_clk <= ~wb_clk;
   initial  #100 wb_rst <= 0;

   wire    done;

   wire [aw-1:0] wb_m2s_adr;
   wire [dw-1:0] wb_m2s_dat;
   wire [3:0] 	 wb_m2s_sel;
   wire 	 wb_m2s_we ;
   wire 	 wb_m2s_cyc;
   wire 	 wb_m2s_stb;
   wire [2:0] 	 wb_m2s_cti;
   wire [1:0] 	 wb_m2s_bte;
   wire [dw-1:0] wb_s2m_dat;
   wire 	 wb_s2m_ack;
   wire 	 wb_s2m_err;
   wire 	 wb_s2m_rty;

   wb_bfm_mod_transactor
     #(.MEM_HIGH (32'h00007fff),
       .AUTORUN (0),
       .VERBOSE (0))
   master
     (.wb_clk_i (wb_clk),
      .wb_rst_i (wb_rst),
      .wb_adr_o (wb_m2s_adr),
      .wb_dat_o (wb_m2s_dat),
      .wb_sel_o (wb_m2s_sel),
      .wb_we_o  (wb_m2s_we ),
      .wb_cyc_o (wb_m2s_cyc),
      .wb_stb_o (wb_m2s_stb),
      .wb_cti_o (wb_m2s_cti),
      .wb_bte_o (wb_m2s_bte),
      .wb_dat_i (wb_s2m_dat),
      .wb_ack_i (wb_s2m_ack),
      .wb_err_i (wb_s2m_err),
      .wb_rty_i (wb_s2m_rty),
      .done     (done));

   wb_bfm_mod_memory #(.DEBUG (0))
   wb_mem_model0
     (.wb_clk_i (wb_clk),
      .wb_rst_i (wb_rst),
      .wb_adr_i (wb_m2s_adr),
      .wb_dat_i (wb_m2s_dat),
      .wb_sel_i (wb_m2s_sel),
      .wb_we_i  (wb_m2s_we ),
      .wb_cyc_i (wb_m2s_cyc),
      .wb_stb_i (wb_m2s_stb),
      .wb_cti_i (wb_m2s_cti),
      .wb_bte_i (wb_m2s_bte),
      .wb_dat_o (wb_s2m_dat),
      .wb_ack_o (wb_s2m_ack),
      .wb_err_o (wb_s2m_err),
      .wb_rty_o (wb_s2m_rty));

   integer 	 TRANSACTIONS;
   integer 	 SUBTRANSACTIONS;
   integer 	 SEED;

   initial begin

      if($value$plusargs("transactions=%d", TRANSACTIONS))
	master.set_transactions(TRANSACTIONS);
      if($value$plusargs("subtransactions=%d", SUBTRANSACTIONS))
	master.set_subtransactions(SUBTRANSACTIONS);
      if($value$plusargs("seed=%d", SEED))
	master.SEED = SEED;

      master.display_settings;
      master.run;
      master.display_stats;
   end

   always @(posedge done) begin
      vtg.ok("All tests complete");
      $display("All tests complete");
      $finish;
   end

endmodule
module wb_bfm_mod_tb;


   vlog_tb_utils vlog_tb_utils0();
   vlog_tap_generator #("wb_bfm_mod.tap", 1) vtg();

   localparam aw = 32;
   localparam dw = 32;

   reg	   wb_clk = 1'b1;
   reg	   wb_rst = 1'b1;

   always #5 wb_clk <= ~wb_clk;
   initial  #100 wb_rst <= 0;

   wire    done;

   wire [aw-1:0] wb_m2s_adr;
   wire [dw-1:0] wb_m2s_dat;
   wire [3:0] 	 wb_m2s_sel;
   wire 	 wb_m2s_we ;
   wire 	 wb_m2s_cyc;
   wire 	 wb_m2s_stb;
   wire [2:0] 	 wb_m2s_cti;
   wire [1:0] 	 wb_m2s_bte;
   wire [dw-1:0] wb_s2m_dat;
   wire 	 wb_s2m_ack;
   wire 	 wb_s2m_err;
   wire 	 wb_s2m_rty;

   wb_bfm_mod_transactor
     #(.MEM_HIGH (32'h00007fff),
       .AUTORUN (0),
       .VERBOSE (0))
   master
     (.wb_clk_i (wb_clk),
      .wb_rst_i (wb_rst),
      .wb_adr_o (wb_m2s_adr),
      .wb_dat_o (wb_m2s_dat),
      .wb_sel_o (wb_m2s_sel),
      .wb_we_o  (wb_m2s_we ),
      .wb_cyc_o (wb_m2s_cyc),
      .wb_stb_o (wb_m2s_stb),
      .wb_cti_o (wb_m2s_cti),
      .wb_bte_o (wb_m2s_bte),
      .wb_dat_i (wb_s2m_dat),
      .wb_ack_i (wb_s2m_ack),
      .wb_err_i (wb_s2m_err),
      .wb_rty_i (wb_s2m_rty),
      .done     (done));

   wb_bfm_mod_memory #(.DEBUG (0))
   wb_mem_model0
     (.wb_clk_i (wb_clk),
      .wb_rst_i (wb_rst),
      .wb_adr_i (wb_m2s_adr),
      .wb_dat_i (wb_m2s_dat),
      .wb_sel_i (wb_m2s_sel),
      .wb_we_i  (wb_m2s_we ),
      .wb_cyc_i (wb_m2s_cyc),
      .wb_stb_i (wb_m2s_stb),
      .wb_cti_i (wb_m2s_cti),
      .wb_bte_i (wb_m2s_bte),
      .wb_dat_o (wb_s2m_dat),
      .wb_ack_o (wb_s2m_ack),
      .wb_err_o (wb_s2m_err),
      .wb_rty_o (wb_s2m_rty));

   integer 	 TRANSACTIONS;
   integer 	 SUBTRANSACTIONS;
   integer 	 SEED;

   initial begin

      if($value$plusargs("transactions=%d", TRANSACTIONS))
	master.set_transactions(TRANSACTIONS);
      if($value$plusargs("subtransactions=%d", SUBTRANSACTIONS))
	master.set_subtransactions(SUBTRANSACTIONS);
      if($value$plusargs("seed=%d", SEED))
	master.SEED = SEED;

      master.display_settings;
      master.run;
      master.display_stats;
   end

   always @(posedge done) begin
      vtg.ok("All tests complete");
      $display("All tests complete");
      $finish;
   end

endmodule