data/full_repos/permissive/114652687/dut1/ip.v
None: at end of input
data/verilator_xmls/3f9da683-1457-41f0-9df0-abc8d2530654.xml
module ip(
            tdi,
            shift,
            update,
            capture,
            tck,

            reset_n,

            tdo
         );

  input tdi;
  input shift;
  input update;
  input capture;
  input tck;

  input reset_n;

  output tdo;

  reg [48:0] dr;

  wire write_en;
  wire write;
  wire read;
  wire [15:0] address;
  wire [31:0] data;
  wire busy, fail, error;

  assign tdo = dr[0];
  assign address[15:0] = dr[47:32];
  assign data[31:0] = dr[31:0];
  assign write_en = dr[48];
  assign write = write_en && update;
  assign read = !write_en && capture;



  always @ (posedge tck or negedge reset_n) begin
    if (reset_n == 0)
      dr[48:0] <= 49'b0;
    else if (shift == 1)
      begin
        dr[48] <= tdi;
        dr[47:0] <= dr[48:1];
      end
    else
      dr[48:0] <= dr[48:0];
  end


  reg [31:0] cmd;
  reg [31:0] status;
  reg [31:0] data_reg;

  always @ (negedge tck or negedge reset_n) begin
    if (reset_n == 0)
      cmd[31:0] <= 32'b0;
    else if (write && address == 16'h0) begin
      if (busy)
        status[2] <= 1'b1;
      else
        cmd[31:0] <= data[31:0];
      end
    else if (read && address == 16'h0)
      dr[31:0] <= cmd[31:0];
  end

  assign busy = status[0];
  assign fail = status[1];
  assign error = status[2];
  
  always @ (negedge tck or negedge reset_n) begin
    if (reset_n == 0)
      status[31:0] <= 32'b1;
    else if (write && address == 16'h4) begin
      if (busy)
        status[2] <= 1'b1;
      else
        begin
          if (data[1] == 1'b1)
            status[1] <= 1'b0;
          if (data[2] == 1'b1)
            status[2] <= 1'b0;
        end
      end
    else if (read && address == 16'h4)
      dr[31:0] <= status[31:0];
  end

  always @ (posedge reset_n) begin
    status[31:0] <= 32'b0;
  end

  always @ (negedge tck or negedge reset_n) begin
    if (reset_n == 0)
      data_reg[31:0] <= 32'b0;
    else if (write && address == 16'h8)
      data_reg[31:0] <= data[31:0];
    else if (read && address == 16'h8)
      dr[31:0] <= data_reg[31:0];
  end



  reg [31:0] i;

  always @ (negedge tck) begin
    if (cmd >= 32'd1 && cmd <= 32'd1000)
      begin
        if (busy == 0)
          begin
            i[31:0] <= 1000 * cmd;
            status[0] <= 1'b1;
          end
        else
          begin
            if (i == 1)
              begin
                cmd[31:0] <= 32'h0;
                i <= 0;
                status[0] <= 1'b0;
              end
            else
              i <= i - 1;
          end
      end

    else if (cmd != 32'h0)
      status[2] <= 1'b1;
  end

endmodule
module ip(
            tdi,
            shift,
            update,
            capture,
            tck,

            reset_n,

            tdo
         );


  input tdi;
  input shift;
  input update;
  input capture;
  input tck;

  input reset_n;

  output tdo;

  reg [48:0] dr;

  wire write_en;
  wire write;
  wire read;
  wire [15:0] address;
  wire [31:0] data;
  wire busy, fail, error;

  assign tdo = dr[0];
  assign address[15:0] = dr[47:32];
  assign data[31:0] = dr[31:0];
  assign write_en = dr[48];
  assign write = write_en && update;
  assign read = !write_en && capture;



  always @ (posedge tck or negedge reset_n) begin
    if (reset_n == 0)
      dr[48:0] <= 49'b0;
    else if (shift == 1)
      begin
        dr[48] <= tdi;
        dr[47:0] <= dr[48:1];
      end
    else
      dr[48:0] <= dr[48:0];
  end


  reg [31:0] cmd;
  reg [31:0] status;
  reg [31:0] data_reg;

  always @ (negedge tck or negedge reset_n) begin
    if (reset_n == 0)
      cmd[31:0] <= 32'b0;
    else if (write && address == 16'h0) begin
      if (busy)
        status[2] <= 1'b1;
      else
        cmd[31:0] <= data[31:0];
      end
    else if (read && address == 16'h0)
      dr[31:0] <= cmd[31:0];
  end

  assign busy = status[0];
  assign fail = status[1];
  assign error = status[2];
  
  always @ (negedge tck or negedge reset_n) begin
    if (reset_n == 0)
      status[31:0] <= 32'b1;
    else if (write && address == 16'h4) begin
      if (busy)
        status[2] <= 1'b1;
      else
        begin
          if (data[1] == 1'b1)
            status[1] <= 1'b0;
          if (data[2] == 1'b1)
            status[2] <= 1'b0;
        end
      end
    else if (read && address == 16'h4)
      dr[31:0] <= status[31:0];
  end

  always @ (posedge reset_n) begin
    status[31:0] <= 32'b0;
  end

  always @ (negedge tck or negedge reset_n) begin
    if (reset_n == 0)
      data_reg[31:0] <= 32'b0;
    else if (write && address == 16'h8)
      data_reg[31:0] <= data[31:0];
    else if (read && address == 16'h8)
      dr[31:0] <= data_reg[31:0];
  end



  reg [31:0] i;

  always @ (negedge tck) begin
    if (cmd >= 32'd1 && cmd <= 32'd1000)
      begin
        if (busy == 0)
          begin
            i[31:0] <= 1000 * cmd;
            status[0] <= 1'b1;
          end
        else
          begin
            if (i == 1)
              begin
                cmd[31:0] <= 32'h0;
                i <= 0;
                status[0] <= 1'b0;
              end
            else
              i <= i - 1;
          end
      end

    else if (cmd != 32'h0)
      status[2] <= 1'b1;
  end

endmodule