data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/Selector31_5bits.v
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data/verilator_xmls/1acc9c60-e462-4066-a3f6-63ac742811d3.xml
module Selector31_5bits(
    rt, rd, RegDst, WriteReg
);
    input [4:0] rt;
    input [4:0] rd;
    input [1:0] RegDst;
    output reg[4:0] WriteReg;
    
    always @(rt or rd or RegDst)begin
        case(RegDst)
                   2'b00: WriteReg = 5'b11111;
                   2'b01: WriteReg = rt;
                   2'b10: WriteReg = rd;
                   default: WriteReg = WriteReg;
        endcase       
    end
endmodule
module Selector31_5bits(
    rt, rd, RegDst, WriteReg
);

    input [4:0] rt;
    input [4:0] rd;
    input [1:0] RegDst;
    output reg[4:0] WriteReg;
    
    always @(rt or rd or RegDst)begin
        case(RegDst)
                   2'b00: WriteReg = 5'b11111;
                   2'b01: WriteReg = rt;
                   2'b10: WriteReg = rd;
                   default: WriteReg = WriteReg;
        endcase       
    end
endmodule