data/full_repos/permissive/150214807/lab5.v
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1: b'%Error: data/full_repos/permissive/150214807/lab5.v:100: Unsupported or unknown PLI call: $monitor\n$monitor(,$time,"r1=%b r2=%b reset=%b, w=%b, d=%h, rd1=%h, rd2=%h rw=%b",rr1,rr2,rst,w,wd,rd1,rd2,rw);\n^~~~~~~~\n%Error: data/full_repos/permissive/150214807/lab5.v:100: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n$monitor(,$time,"r1=%b r2=%b reset=%b, w=%b, d=%h, rd1=%h, rd2=%h rw=%b",rr1,rr2,rst,w,wd,rd1,rd2,rw);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:102: Unsupported: Ignoring delay on this delayed statement.\n#30 rst = 1\'b1; wd=32\'hAFAFAFAF; w=2\'b10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:103: Unsupported: Ignoring delay on this delayed statement.\n#10 rw=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:104: Unsupported: Ignoring delay on this delayed statement.\n#15 w=2\'b01;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:105: Unsupported: Ignoring delay on this delayed statement.\n#20 wd=32\'hFAFAFAFA;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:106: Unsupported: Ignoring delay on this delayed statement.\n#10 rst=1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:107: Unsupported: Ignoring delay on this delayed statement.\n#200 $finish;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:111: Unsupported: Ignoring delay on this delayed statement.\n#7 clk = ~clk;\n^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegFile(clk,reset,ReadReg1,ReadReg2,WriteReg,WriteData,RegWrite,ReadData1,ReadData2);
	output [31:0] ReadData1,ReadData2;
	input clk,reset,RegWrite;
	input [31:0] WriteData;
	input [1:0] ReadReg1,ReadReg2,WriteReg;
	wire [3:0] regclk,decreg;
	wire [3:0] [31:0] q;
	genvar j;
	decoder2_4 d(decreg,WriteReg);
	generate for (j=0;j<4;j=j+1) begin: regbuild
		and aj(regclk[j],decreg[j],RegWrite,clk);
		reg_32bit rj(q[j],WriteData,regclk[j],reset);
	end
	endgenerate
	mux4_1 m1(ReadData1,q[0],q[1],q[2],q[3],ReadReg1);
	mux4_1 m2(ReadData2,q[0],q[1],q[2],q[3],ReadReg2);
endmodule
module RegFile(clk,reset,ReadReg1,ReadReg2,WriteReg,WriteData,RegWrite,ReadData1,ReadData2);

	output [31:0] ReadData1,ReadData2;
	input clk,reset,RegWrite;
	input [31:0] WriteData;
	input [1:0] ReadReg1,ReadReg2,WriteReg;
	wire [3:0] regclk,decreg;
	wire [3:0] [31:0] q;
	genvar j;
	decoder2_4 d(decreg,WriteReg);
	generate for (j=0;j<4;j=j+1) begin: regbuild
		and aj(regclk[j],decreg[j],RegWrite,clk);
		reg_32bit rj(q[j],WriteData,regclk[j],reset);
	end
	endgenerate
	mux4_1 m1(ReadData1,q[0],q[1],q[2],q[3],ReadReg1);
	mux4_1 m2(ReadData2,q[0],q[1],q[2],q[3],ReadReg2);
endmodule