data/full_repos/permissive/152883307/Project/PWM.v
data/verilator_xmls/578a399a-901c-45d7-8d27-df25f32c53cb.xml
module PWM(
	clock_in,
	reset_n,
   Duty_data,
	Dead_time,
	PWM_out1,
	PWM_out2
);
input 					clock_in; 	
input						reset_n;
input 		[9:0] 	Duty_data;
output reg		 		PWM_out1,PWM_out2;
input			[8:0]		Dead_time;

reg [9:0] 	Counter = 0;

parameter Dead_time80	=10'd82;

always@(negedge clock_in or negedge reset_n) begin
	if(!reset_n) Counter <= 10'd0;
	else 			
		begin
			if ( Counter < Duty_data-Dead_time)
				begin
				PWM_out1 <= 1;
				PWM_out2 <= 0;
				end
			else if ((Counter > Duty_data-Dead_time)&&(Counter < Duty_data))
				begin
				PWM_out1 <= 0;
				PWM_out2 <= 0;
				end
			else if ((Counter > Duty_data)&&(Counter < Duty_data*2-Dead_time))
				begin
				PWM_out1 <= 0;
				PWM_out2 <= 1;
				end
			else if (Counter > Duty_data*2-Dead_time)
				begin
				PWM_out1 <= 0;
				PWM_out2 <= 0;
				end
			Counter <= Counter+1;
		end
end

endmodule
module PWM(
	clock_in,
	reset_n,
   Duty_data,
	Dead_time,
	PWM_out1,
	PWM_out2
);

input 					clock_in; 	
input						reset_n;
input 		[9:0] 	Duty_data;
output reg		 		PWM_out1,PWM_out2;
input			[8:0]		Dead_time;

reg [9:0] 	Counter = 0;

parameter Dead_time80	=10'd82;

always@(negedge clock_in or negedge reset_n) begin
	if(!reset_n) Counter <= 10'd0;
	else 			
		begin
			if ( Counter < Duty_data-Dead_time)
				begin
				PWM_out1 <= 1;
				PWM_out2 <= 0;
				end
			else if ((Counter > Duty_data-Dead_time)&&(Counter < Duty_data))
				begin
				PWM_out1 <= 0;
				PWM_out2 <= 0;
				end
			else if ((Counter > Duty_data)&&(Counter < Duty_data*2-Dead_time))
				begin
				PWM_out1 <= 0;
				PWM_out2 <= 1;
				end
			else if (Counter > Duty_data*2-Dead_time)
				begin
				PWM_out1 <= 0;
				PWM_out2 <= 0;
				end
			Counter <= Counter+1;
		end
end

endmodule