data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v
 line:135: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n always #5 clock <= ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:20: Unsupported or unknown PLI call: $monitor\n  $monitor("%5t %b %b %b %b %b %b %b %h %h", $time, clock, reset,\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #2\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo32_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Error: Exiting due to 1 error(s), 38 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifo16_tb;
	
	reg		clock		= 1;
	reg		reset		= 0;
	reg		read		= 0;
	reg		write		= 0;
	
	reg		[17:0]	wr_data	= 0;
	wire	[17:0]	rd_data;
	
	wire	almost_full;
	wire	almost_empty;
	wire	not_empty;
	
	always	#5	clock	<= ~clock;
	
	
	initial begin : Sim
		$display("Time CLK RST RD WR A_FULL A_EMPTY EMPTY# R_DATA W_DATA");
		$monitor("%5t %b %b %b %b %b %b %b %h %h", $time, clock, reset,
			read, write, almost_full, almost_empty, not_empty, rd_data, wr_data);
		
		#2
		reset	= 1;
		
		#10
		reset	= 0;
		
		#10
		write	= 1;
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		write = 0;
		
		#10
		read = 1;
		wr_data	= 18'h0A0A;
		
		#10
		read	= 0;
		write	= 0;
		
		#30
		$finish;
	end
	
	

	fifo32 #('d18) FIFO0(
		.read_clock_i(clock),
		.write_clock_i(clock),
		.reset_i(reset),
		.read_i(read),
		.write_i(write),
		.data_i(wr_data),
		.data_o(rd_data),
		.almost_full_o(almost_full),
		.almost_empty_o(almost_empty),
		.not_empty_o(not_empty)
	);
	
	
endmodule
module fifo16_tb;

	
	reg		clock		= 1;
	reg		reset		= 0;
	reg		read		= 0;
	reg		write		= 0;
	
	reg		[17:0]	wr_data	= 0;
	wire	[17:0]	rd_data;
	
	wire	almost_full;
	wire	almost_empty;
	wire	not_empty;
	
	always	#5	clock	<= ~clock;
	
	
	initial begin : Sim
		$display("Time CLK RST RD WR A_FULL A_EMPTY EMPTY# R_DATA W_DATA");
		$monitor("%5t %b %b %b %b %b %b %b %h %h", $time, clock, reset,
			read, write, almost_full, almost_empty, not_empty, rd_data, wr_data);
		
		#2
		reset	= 1;
		
		#10
		reset	= 0;
		
		#10
		write	= 1;
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= 18'h30F0;
		
		#10
		write = 0;
		
		#10
		read = 1;
		wr_data	= 18'h0A0A;
		
		#10
		read	= 0;
		write	= 0;
		
		#30
		$finish;
	end
	
	

	fifo32 #('d18) FIFO0(
		.read_clock_i(clock),
		.write_clock_i(clock),
		.reset_i(reset),
		.read_i(read),
		.write_i(write),
		.data_i(wr_data),
		.data_o(rd_data),
		.almost_full_o(almost_full),
		.almost_empty_o(almost_empty),
		.not_empty_o(not_empty)
	);
	
	
endmodule