data/full_repos/permissive/106966316/memoria_datos.v
1: b"%Error: data/full_repos/permissive/106966316/memoria_datos.v:43: Cannot find file containing module: 'sram'\nsram sram1(.clk(clk),\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram.v\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram.sv\n             sram\n             sram.v\n             sram.sv\n             obj_dir/sram\n             obj_dir/sram.v\n             obj_dir/sram.sv\n%Error: data/full_repos/permissive/106966316/memoria_datos.v:51: Cannot find file containing module: 'sram'\nsram sram2(.clk(clk),\n^~~~\n%Error: data/full_repos/permissive/106966316/memoria_datos.v:60: Cannot find file containing module: 'sram'\nsram ROM(\n^~~~\n%Error: Exiting due to 3 error(s)\n"
module memoria_datos(clk,EscrMem,Direc,Datain,LeerMem,Dataout);
    input clk;
    input EscrMem;
    input [31:0] Direc;
    input [31:0] Datain;
    input LeerMem;
    output reg [31:0] Dataout;
    


wire CSram1;
wire CSram2;

wire [2:0] CS;

wire [31:0] Dataout1;
wire [31:0] Dataout2;
wire [31:0] Dataout3;
wire CSrom;
 
sram sram1(.clk(clk),
           .CSram(CSram1),
           .Direc(Direc[7:0]),
           .Datain(Datain),
           .LeerMem(LeerMem),
           .Dataout(Dataout1),
           .EscrMem(EscrMem)
           );
sram sram2(.clk(clk),
           .CSram(CSram2),
           .Direc(Direc[7:0]),
           .Datain(Datain),
           .LeerMem(LeerMem),
           .Dataout(Dataout2),
           .EscrMem(EscrMem)
           );

sram ROM(
           .clk(clk),
           .CSram(CSrom),
           .Direc(Direc[7:0]),
           .Datain(Datain),
           .LeerMem(LeerMem),
           .Dataout(Dataout3),
           .EscrMem(EscrMem)
           );




assign CSrom  = (Direc[31:8]==24'b0000_0000_0000_0000_0000_0100) ? 1 : 0 ; 
assign CSram1 = ((Direc[31:8]==24'b0000_0000_0000_0000_0000_0000)|(Direc[31:8]==24'b0000_0000_0000_0000_0000_0001)) ? 1 : 0 ;
assign CSram2 = ((Direc[31:8]==24'b0000_0000_0000_0000_0000_0010)|(Direc[31:8]==24'b0000_0000_0000_0000_0000_0011)) ? 1 : 0 ;
assign CS = {CSrom,CSram1,CSram2};
always @ (*)

begin
    

    case(CS)
        3'b100:Dataout = Dataout3;
        3'b010:Dataout = Dataout1;
        3'b001:Dataout = Dataout2;
    endcase
        
end



endmodule
module memoria_datos(clk,EscrMem,Direc,Datain,LeerMem,Dataout);

    input clk;
    input EscrMem;
    input [31:0] Direc;
    input [31:0] Datain;
    input LeerMem;
    output reg [31:0] Dataout;
    


wire CSram1;
wire CSram2;

wire [2:0] CS;

wire [31:0] Dataout1;
wire [31:0] Dataout2;
wire [31:0] Dataout3;
wire CSrom;
 
sram sram1(.clk(clk),
           .CSram(CSram1),
           .Direc(Direc[7:0]),
           .Datain(Datain),
           .LeerMem(LeerMem),
           .Dataout(Dataout1),
           .EscrMem(EscrMem)
           );
sram sram2(.clk(clk),
           .CSram(CSram2),
           .Direc(Direc[7:0]),
           .Datain(Datain),
           .LeerMem(LeerMem),
           .Dataout(Dataout2),
           .EscrMem(EscrMem)
           );

sram ROM(
           .clk(clk),
           .CSram(CSrom),
           .Direc(Direc[7:0]),
           .Datain(Datain),
           .LeerMem(LeerMem),
           .Dataout(Dataout3),
           .EscrMem(EscrMem)
           );




assign CSrom  = (Direc[31:8]==24'b0000_0000_0000_0000_0000_0100) ? 1 : 0 ; 
assign CSram1 = ((Direc[31:8]==24'b0000_0000_0000_0000_0000_0000)|(Direc[31:8]==24'b0000_0000_0000_0000_0000_0001)) ? 1 : 0 ;
assign CSram2 = ((Direc[31:8]==24'b0000_0000_0000_0000_0000_0010)|(Direc[31:8]==24'b0000_0000_0000_0000_0000_0011)) ? 1 : 0 ;
assign CS = {CSrom,CSram1,CSram2};
always @ (*)

begin
    

    case(CS)
        3'b100:Dataout = Dataout3;
        3'b010:Dataout = Dataout1;
        3'b001:Dataout = Dataout2;
    endcase
        
end



endmodule