data/full_repos/permissive/115837888/source-7400/74162-tb.v
 line:5: before: "tbassert"
1: b'%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:6: Define or directive not defined: \'`TBASSERT_2_METHOD\'\n`TBASSERT_2_METHOD(tbassert2)\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:7: Define or directive not defined: \'`CASE_TBASSERT_2_METHOD\'\n`CASE_TBASSERT_2_METHOD(case_tbassert2, tbassert2)\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:8: Define or directive not defined: \'`TBCLK_WAIT_TICK_METHOD\'\n`TBCLK_WAIT_TICK_METHOD(wait_tick)\n^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:38: Unsupported: Ignoring delay on this delayed statement.\nalways #50 Clk = ~Clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:43: syntax error, unexpected \'@\'\n  repeat (2) @(posedge Clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:54: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("74162-tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74162-tb.v:55: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#225\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n#110\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n#110\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n#105\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n#95\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n#22\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:198: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:202: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:216: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:218: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n#97\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:223: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n#97\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:229: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:239: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:241: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:244: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:251: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:257: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:260: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:267: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:270: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:273: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:276: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:279: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:281: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:284: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:287: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:290: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:293: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:296: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:298: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:301: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:304: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:307: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:313: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:310: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:316: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:318: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:321: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:324: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:327: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:330: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:332: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:335: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:338: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:341: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:344: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:347: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:349: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:352: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:355: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:358: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:363: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:367: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:370: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:373: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:376: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:380: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:383: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:387: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:390: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:393: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:396: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:400: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:404: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:407: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:410: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:413: Unsupported: Ignoring delay on this delayed statement.\n#200\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:416: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:419: Unsupported: Ignoring delay on this delayed statement.\n#85\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:422: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:425: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:429: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:432: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:435: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:438: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:441: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:444: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:447: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:450: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:453: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:457: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:460: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:464: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:467: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:469: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:472: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:485: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:488: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:475: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:496: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:506: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:509: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:516: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:522: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:524: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:526: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:529: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:531: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:533: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74162-tb.v:535: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: Exiting due to 8 error(s), 131 warning(s)\n'
module test;

`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
`CASE_TBASSERT_2_METHOD(case_tbassert2, tbassert2)
`TBCLK_WAIT_TICK_METHOD(wait_tick)

localparam WIDTH = 4;


reg Clear_bar;
reg Load_bar;
reg ENT;
reg ENP;
reg [WIDTH-1:0] D;
reg Clk;


wire RCO;
wire [WIDTH-1:0] Q;


ttl_74162 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .Clear_bar(Clear_bar),
  .Load_bar(Load_bar),
  .ENT(ENT),
  .ENP(ENP),
  .D(D),
  .Clk(Clk),
  .RCO(RCO),
  .Q(Q)
);

initial Clk = 1'b0;

always #50 Clk = ~Clk;

task parallel_load_and_tick(input [WIDTH-1:0] D_next);
  Load_bar = 1'b0;
  D = D_next;
  repeat (2) @(posedge Clk);
#7
  Load_bar = 1'b1;
endtask

initial
begin
  reg [WIDTH-1:0] D_next;
  reg [WIDTH-1:0] Q_expected;
  integer i;

  $dumpfile("74162-tb.vcd");
  $dumpvars;



#225

  tbassert(Q === 4'bxxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#0

  Load_bar = 1'b0;
  D = 4'b0000;
#25
  tbassert(Q === 4'bxxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#2

  tbassert(Q === 4'bxxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#2

  tbassert(Q == 4'b0000, "Test 1");
  tbassert(RCO == 1'b0, "Test 1");
#140

  Load_bar = 1'b1;
#175
  tbassert(Q == 4'b0000, "Test 2");
  tbassert(RCO == 1'b0, "Test 2");
#0

  Load_bar = 1'b0;
  ENT = 1'b1;
  D = 4'b1111;
#125
  Load_bar = 1'b1;
#110
  tbassert(Q == 4'b1111, "Test 3");
  tbassert(RCO == 1'b0, "Test 3");
#0

  Load_bar = 1'b0;

  D = 4'b1001;
#90
  Load_bar = 1'b1;
#110
  tbassert(Q == 4'b1001, "Test 4");
  tbassert(RCO == 1'b1, "Test 4");
#0



  D_next = 4'b1001;

  for (i = 1; i <= 6; i++)
  begin
    Q_expected = D_next;
    D_next = (Q_expected + 1) ^ 5;

    case (i)
      1:
      begin
        ENT = 1'b0;
      end
      2:
      begin
        ENT = 1'b0;
        ENP = 1'b0;
      end
      3:
      begin
        ENT = 1'b1;
        ENP = 1'b0;
      end
      4:
      begin
        ENT = 1'b0;
        ENP = 1'b1;
      end
      5:
      begin
        Clear_bar = 1'b1;
        ENT = 1'b0;
        ENP = 1'b1;
      end
      6:
      begin
        Clear_bar = 1'b1;
        ENT = 1'b1;
        ENP = 1'b0;
      end
    endcase
#75
    tbassert2(Q == Q_expected, "Test", i, "5");
    tbassert2(RCO == 1'b0, "Test", i, "5");
#0

    Load_bar = 1'b0;
    D = D_next;
#100
    tbassert2(Q == D_next, "Test", i, "5");
    tbassert2(RCO == 1'b0, "Test", i, "5");
#0

    Load_bar = 1'b1;
#105
    tbassert2(Q == D_next, "Test", i, "5");
    tbassert2(RCO == 1'b0, "Test", i, "5");

  end



  tbassert2(Q == 4'b1101, "Test", 6, "5");
#175



  wait_tick();
#7

  Clear_bar = 1'b0;
#95

  tbassert(Q == 4'b1101, "Test 6");
  tbassert(RCO == 1'b0, "Test 6");
#2

  tbassert(Q == 4'b0000, "Test 6");
  tbassert(RCO == 1'b0, "Test 6");
#150
  Clear_bar = 1'b1;
#50
  ENT = 1'b1;
  parallel_load_and_tick(4'b1001);
#70

  Clear_bar = 1'b0;
#22

  tbassert(Q == 4'b1001, "Test 7");
  tbassert(RCO == 1'b1, "Test 7");
#5

  tbassert(Q == 4'b0000, "Test 7");
  tbassert(RCO == 1'b0, "Test 7");
#10

  Clear_bar = 1'b1;
#120
  tbassert(Q == 4'b0000, "Test 8");
  tbassert(RCO == 1'b0, "Test 8");
#50



  Clear_bar = 1'bx;
  Load_bar = 1'bx;
  ENT = 1'bx;
  ENP = 1'bx;
#15
  parallel_load_and_tick(4'bxxxx);
#0
  Load_bar = 1'bx;
#97
  tbassert(Q === 4'bxxxx, "Test 9");
  tbassert(RCO === 1'bx, "Test 9");
#0

  Clear_bar = 1'b0;
#97
  tbassert(Q === 4'bxxxx, "Test 9");
  tbassert(RCO === 1'bx, "Test 9");
#2

  tbassert(Q == 4'b0000, "Test 9");
  tbassert(RCO == 1'b0, "Test 9");
#15

  Clear_bar = 1'b1;
#120
  tbassert(Q == 4'b0000, "Test 10");
  tbassert(RCO == 1'b0, "Test 10");
#0
  Load_bar = 1'b1;
#80
  tbassert(Q == 4'b0000, "Test 10");
  tbassert(RCO == 1'b0, "Test 10");
#0




  ENT = 1'b0;
  ENP = 1'b1;
#7
  tbassert(Q == 4'b0000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#50
  tbassert(Q == 4'b0000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#100
  tbassert(Q == 4'b0000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#15

  ENT = 1'b1;
  ENP = 1'b0;
#7
  tbassert(Q == 4'b0000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#50
  tbassert(Q == 4'b0000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#100
  tbassert(Q == 4'b0000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#0

  wait_tick();
#15
  Load_bar = 1'b0;
  D = 4'b1110;
#15
  Load_bar = 1'b1;
#7
  tbassert(Q == 4'b0000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#50
  tbassert(Q == 4'b0000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#100
  tbassert(Q == 4'b0000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#0

  wait_tick();
#20
  ENT = 1'b1;
  ENP = 1'b1;
#15
  ENT = 1'b0;
#15
  tbassert(Q == 4'b0000, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#50
  tbassert(Q == 4'b0000, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#100
  tbassert(Q == 4'b0000, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#20

  parallel_load_and_tick(4'b1001);
#50


#175
  tbassert(Q == 4'b1001, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#0
  ENP = 1'b0;
#50
  tbassert(Q == 4'b1001, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#100
  tbassert(Q == 4'b1001, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#0

  wait_tick();
#25
  Load_bar = 1'b0;
  D = 4'b0010;
#15
  Load_bar = 1'b1;
#7
  tbassert(Q == 4'b1001, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#50
  tbassert(Q == 4'b1001, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#100
  tbassert(Q == 4'b1001, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#0

  wait_tick();
#15
  ENT = 1'b1;
  ENP = 1'b1;
#15
  ENT = 1'b0;
#7
  tbassert(Q == 4'b1001, "Test 17");
  tbassert(RCO == 1'b0, "Test 17");
#50
  tbassert(Q == 4'b1001, "Test 17");
  tbassert(RCO == 1'b0, "Test 17");
#100
  tbassert(Q == 4'b1001, "Test 17");
  tbassert(RCO == 1'b0, "Test 17");
#0



  wait_tick();
#10

  ENT = 1'b1;
  ENP = 1'b1;
#40
  tbassert(Q == 4'b1001, "Test 18");
  tbassert(RCO == 1'b1, "Test 18");
#50
  tbassert(Q == 4'b1001, "Test 18");
  tbassert(RCO == 1'b1, "Test 18");
#7
  tbassert(Q == 4'b0000, "Test 18");
  tbassert(RCO == 1'b0, "Test 18");
#90

  tbassert(Q == 4'b0000, "Test 19");
  tbassert(RCO == 1'b0, "Test 19");
#10
  tbassert(Q == 4'b0001, "Test 19");
  tbassert(RCO == 1'b0, "Test 19");
#90

  tbassert(Q == 4'b0001, "Test 20");
  tbassert(RCO == 1'b0, "Test 20");
#10
  tbassert(Q == 4'b0010, "Test 20");
  tbassert(RCO == 1'b0, "Test 20");
#7

  parallel_load_and_tick(4'b0111);
#0
  tbassert(Q == 4'b0111, "Test 21");
  tbassert(RCO == 1'b0, "Test 21");
#100

  tbassert(Q == 4'b1000, "Test 22");
  tbassert(RCO == 1'b0, "Test 22");
#100

  tbassert(Q == 4'b1001, "Test 23");
  tbassert(RCO == 1'b1, "Test 23");
#0

  ENP = 1'b0;
#50
  tbassert(Q == 4'b1001, "Test 24");
  tbassert(RCO == 1'b1, "Test 24");
#50
  tbassert(Q == 4'b1001, "Test 24");
  tbassert(RCO == 1'b1, "Test 24");
#200
  tbassert(Q == 4'b1001, "Test 24");
  tbassert(RCO == 1'b1, "Test 24");
#0

  ENP = 1'b1;
#85
  tbassert(Q == 4'b1001, "Test 25");
  tbassert(RCO == 1'b1, "Test 25");
#15
  tbassert(Q == 4'b0000, "Test 25");
  tbassert(RCO == 1'b0, "Test 25");
#100

  tbassert(Q == 4'b0001, "Test 26");
  tbassert(RCO == 1'b0, "Test 26");
#0

  Clear_bar = 1'b0;
#90
  tbassert(Q == 4'b0001, "Test 27");
  tbassert(RCO == 1'b0, "Test 27");
#10
  tbassert(Q == 4'b0000, "Test 27");
  tbassert(RCO == 1'b0, "Test 27");
#0

  Clear_bar = 1'b1;
#90
  tbassert(Q == 4'b0000, "Test 28");
  tbassert(RCO == 1'b0, "Test 28");
#10
  tbassert(Q == 4'b0001, "Test 28");
  tbassert(RCO == 1'b0, "Test 28");
#50

  Clear_bar = 1'b0;
#50
  Clear_bar = 1'b1;
  parallel_load_and_tick(4'b0101);
#90

  tbassert(Q == 4'b0101, "Test 29");
  tbassert(RCO == 1'b0, "Test 29");
#10
  tbassert(Q == 4'b0110, "Test 29");
  tbassert(RCO == 1'b0, "Test 29");
#20


  ENP = 1'b0;
#50
  tbassert(Q == 4'b0110, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#0
  ENP = 1'b1;
#2
  tbassert(Q == 4'b0110, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#50
  tbassert(Q == 4'b0111, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#0






  for (i = 10; i <= 15; i++)
  begin
    parallel_load_and_tick(i);
#20
    tbassert2(Q > 4'b1001, "Test", (i - 9), "31");
    tbassert2(RCO == 1'b0, "Test", (i - 9), "31");
#80
    tbassert2(Q >= 0 && Q <= 4'b1001, "Test", (i - 9), "31");
    case_tbassert2(Q < 4'b1001, RCO == 1'b0, "Test", (i - 9), "31");
    case_tbassert2(Q == 4'b1001, RCO == 1'b1, "Test", (i - 9), "31");

  end


#0



  ENT = 1'b1;
  ENP = 1'b0;

  for (i = 10; i <= 15; i++)
  begin
    parallel_load_and_tick(i);
#20
    tbassert2(Q > 4'b1001, "Test", (i - 9), "32");
    tbassert2(RCO == 1'b0, "Test", (i - 9), "32");
#120
    tbassert2(Q > 4'b1001, "Test", (i - 9), "32");
    tbassert2(RCO == 1'b0, "Test", (i - 9), "32");

  end


#0


  ENT = 1'b0;
  ENP = 1'b1;
  parallel_load_and_tick(4'b1001);
#100
  tbassert(RCO == 1'b0, "Test 33");
#10
  ENT = 1'b1;
#15
  tbassert(Q == 4'b1001, "Test 33");
  tbassert(RCO == 1'b1, "Test 33");
#0
  ENT = 1'b0;
#15
  tbassert(RCO == 1'b0, "Test 33");
#0
  wait_tick();
#50
  $finish;
end

endmodule
module test;


`TBASSERT_METHOD(tbassert)
`TBASSERT_2_METHOD(tbassert2)
`CASE_TBASSERT_2_METHOD(case_tbassert2, tbassert2)
`TBCLK_WAIT_TICK_METHOD(wait_tick)

localparam WIDTH = 4;


reg Clear_bar;
reg Load_bar;
reg ENT;
reg ENP;
reg [WIDTH-1:0] D;
reg Clk;


wire RCO;
wire [WIDTH-1:0] Q;


ttl_74162 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .Clear_bar(Clear_bar),
  .Load_bar(Load_bar),
  .ENT(ENT),
  .ENP(ENP),
  .D(D),
  .Clk(Clk),
  .RCO(RCO),
  .Q(Q)
);

initial Clk = 1'b0;

always #50 Clk = ~Clk;

task parallel_load_and_tick(input [WIDTH-1:0] D_next);
  Load_bar = 1'b0;
  D = D_next;
  repeat (2) @(posedge Clk);
#7
  Load_bar = 1'b1;
endtask

initial
begin
  reg [WIDTH-1:0] D_next;
  reg [WIDTH-1:0] Q_expected;
  integer i;

  $dumpfile("74162-tb.vcd");
  $dumpvars;



#225

  tbassert(Q === 4'bxxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#0

  Load_bar = 1'b0;
  D = 4'b0000;
#25
  tbassert(Q === 4'bxxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#2

  tbassert(Q === 4'bxxxx, "Test 1");
  tbassert(RCO === 1'bx, "Test 1");
#2

  tbassert(Q == 4'b0000, "Test 1");
  tbassert(RCO == 1'b0, "Test 1");
#140

  Load_bar = 1'b1;
#175
  tbassert(Q == 4'b0000, "Test 2");
  tbassert(RCO == 1'b0, "Test 2");
#0

  Load_bar = 1'b0;
  ENT = 1'b1;
  D = 4'b1111;
#125
  Load_bar = 1'b1;
#110
  tbassert(Q == 4'b1111, "Test 3");
  tbassert(RCO == 1'b0, "Test 3");
#0

  Load_bar = 1'b0;

  D = 4'b1001;
#90
  Load_bar = 1'b1;
#110
  tbassert(Q == 4'b1001, "Test 4");
  tbassert(RCO == 1'b1, "Test 4");
#0



  D_next = 4'b1001;

  for (i = 1; i <= 6; i++)
  begin
    Q_expected = D_next;
    D_next = (Q_expected + 1) ^ 5;

    case (i)
      1:
      begin
        ENT = 1'b0;
      end
      2:
      begin
        ENT = 1'b0;
        ENP = 1'b0;
      end
      3:
      begin
        ENT = 1'b1;
        ENP = 1'b0;
      end
      4:
      begin
        ENT = 1'b0;
        ENP = 1'b1;
      end
      5:
      begin
        Clear_bar = 1'b1;
        ENT = 1'b0;
        ENP = 1'b1;
      end
      6:
      begin
        Clear_bar = 1'b1;
        ENT = 1'b1;
        ENP = 1'b0;
      end
    endcase
#75
    tbassert2(Q == Q_expected, "Test", i, "5");
    tbassert2(RCO == 1'b0, "Test", i, "5");
#0

    Load_bar = 1'b0;
    D = D_next;
#100
    tbassert2(Q == D_next, "Test", i, "5");
    tbassert2(RCO == 1'b0, "Test", i, "5");
#0

    Load_bar = 1'b1;
#105
    tbassert2(Q == D_next, "Test", i, "5");
    tbassert2(RCO == 1'b0, "Test", i, "5");

  end



  tbassert2(Q == 4'b1101, "Test", 6, "5");
#175



  wait_tick();
#7

  Clear_bar = 1'b0;
#95

  tbassert(Q == 4'b1101, "Test 6");
  tbassert(RCO == 1'b0, "Test 6");
#2

  tbassert(Q == 4'b0000, "Test 6");
  tbassert(RCO == 1'b0, "Test 6");
#150
  Clear_bar = 1'b1;
#50
  ENT = 1'b1;
  parallel_load_and_tick(4'b1001);
#70

  Clear_bar = 1'b0;
#22

  tbassert(Q == 4'b1001, "Test 7");
  tbassert(RCO == 1'b1, "Test 7");
#5

  tbassert(Q == 4'b0000, "Test 7");
  tbassert(RCO == 1'b0, "Test 7");
#10

  Clear_bar = 1'b1;
#120
  tbassert(Q == 4'b0000, "Test 8");
  tbassert(RCO == 1'b0, "Test 8");
#50



  Clear_bar = 1'bx;
  Load_bar = 1'bx;
  ENT = 1'bx;
  ENP = 1'bx;
#15
  parallel_load_and_tick(4'bxxxx);
#0
  Load_bar = 1'bx;
#97
  tbassert(Q === 4'bxxxx, "Test 9");
  tbassert(RCO === 1'bx, "Test 9");
#0

  Clear_bar = 1'b0;
#97
  tbassert(Q === 4'bxxxx, "Test 9");
  tbassert(RCO === 1'bx, "Test 9");
#2

  tbassert(Q == 4'b0000, "Test 9");
  tbassert(RCO == 1'b0, "Test 9");
#15

  Clear_bar = 1'b1;
#120
  tbassert(Q == 4'b0000, "Test 10");
  tbassert(RCO == 1'b0, "Test 10");
#0
  Load_bar = 1'b1;
#80
  tbassert(Q == 4'b0000, "Test 10");
  tbassert(RCO == 1'b0, "Test 10");
#0




  ENT = 1'b0;
  ENP = 1'b1;
#7
  tbassert(Q == 4'b0000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#50
  tbassert(Q == 4'b0000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#100
  tbassert(Q == 4'b0000, "Test 11");
  tbassert(RCO == 1'b0, "Test 11");
#15

  ENT = 1'b1;
  ENP = 1'b0;
#7
  tbassert(Q == 4'b0000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#50
  tbassert(Q == 4'b0000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#100
  tbassert(Q == 4'b0000, "Test 12");
  tbassert(RCO == 1'b0, "Test 12");
#0

  wait_tick();
#15
  Load_bar = 1'b0;
  D = 4'b1110;
#15
  Load_bar = 1'b1;
#7
  tbassert(Q == 4'b0000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#50
  tbassert(Q == 4'b0000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#100
  tbassert(Q == 4'b0000, "Test 13");
  tbassert(RCO == 1'b0, "Test 13");
#0

  wait_tick();
#20
  ENT = 1'b1;
  ENP = 1'b1;
#15
  ENT = 1'b0;
#15
  tbassert(Q == 4'b0000, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#50
  tbassert(Q == 4'b0000, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#100
  tbassert(Q == 4'b0000, "Test 14");
  tbassert(RCO == 1'b0, "Test 14");
#20

  parallel_load_and_tick(4'b1001);
#50


#175
  tbassert(Q == 4'b1001, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#0
  ENP = 1'b0;
#50
  tbassert(Q == 4'b1001, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#100
  tbassert(Q == 4'b1001, "Test 15");
  tbassert(RCO == 1'b0, "Test 15");
#0

  wait_tick();
#25
  Load_bar = 1'b0;
  D = 4'b0010;
#15
  Load_bar = 1'b1;
#7
  tbassert(Q == 4'b1001, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#50
  tbassert(Q == 4'b1001, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#100
  tbassert(Q == 4'b1001, "Test 16");
  tbassert(RCO == 1'b0, "Test 16");
#0

  wait_tick();
#15
  ENT = 1'b1;
  ENP = 1'b1;
#15
  ENT = 1'b0;
#7
  tbassert(Q == 4'b1001, "Test 17");
  tbassert(RCO == 1'b0, "Test 17");
#50
  tbassert(Q == 4'b1001, "Test 17");
  tbassert(RCO == 1'b0, "Test 17");
#100
  tbassert(Q == 4'b1001, "Test 17");
  tbassert(RCO == 1'b0, "Test 17");
#0



  wait_tick();
#10

  ENT = 1'b1;
  ENP = 1'b1;
#40
  tbassert(Q == 4'b1001, "Test 18");
  tbassert(RCO == 1'b1, "Test 18");
#50
  tbassert(Q == 4'b1001, "Test 18");
  tbassert(RCO == 1'b1, "Test 18");
#7
  tbassert(Q == 4'b0000, "Test 18");
  tbassert(RCO == 1'b0, "Test 18");
#90

  tbassert(Q == 4'b0000, "Test 19");
  tbassert(RCO == 1'b0, "Test 19");
#10
  tbassert(Q == 4'b0001, "Test 19");
  tbassert(RCO == 1'b0, "Test 19");
#90

  tbassert(Q == 4'b0001, "Test 20");
  tbassert(RCO == 1'b0, "Test 20");
#10
  tbassert(Q == 4'b0010, "Test 20");
  tbassert(RCO == 1'b0, "Test 20");
#7

  parallel_load_and_tick(4'b0111);
#0
  tbassert(Q == 4'b0111, "Test 21");
  tbassert(RCO == 1'b0, "Test 21");
#100

  tbassert(Q == 4'b1000, "Test 22");
  tbassert(RCO == 1'b0, "Test 22");
#100

  tbassert(Q == 4'b1001, "Test 23");
  tbassert(RCO == 1'b1, "Test 23");
#0

  ENP = 1'b0;
#50
  tbassert(Q == 4'b1001, "Test 24");
  tbassert(RCO == 1'b1, "Test 24");
#50
  tbassert(Q == 4'b1001, "Test 24");
  tbassert(RCO == 1'b1, "Test 24");
#200
  tbassert(Q == 4'b1001, "Test 24");
  tbassert(RCO == 1'b1, "Test 24");
#0

  ENP = 1'b1;
#85
  tbassert(Q == 4'b1001, "Test 25");
  tbassert(RCO == 1'b1, "Test 25");
#15
  tbassert(Q == 4'b0000, "Test 25");
  tbassert(RCO == 1'b0, "Test 25");
#100

  tbassert(Q == 4'b0001, "Test 26");
  tbassert(RCO == 1'b0, "Test 26");
#0

  Clear_bar = 1'b0;
#90
  tbassert(Q == 4'b0001, "Test 27");
  tbassert(RCO == 1'b0, "Test 27");
#10
  tbassert(Q == 4'b0000, "Test 27");
  tbassert(RCO == 1'b0, "Test 27");
#0

  Clear_bar = 1'b1;
#90
  tbassert(Q == 4'b0000, "Test 28");
  tbassert(RCO == 1'b0, "Test 28");
#10
  tbassert(Q == 4'b0001, "Test 28");
  tbassert(RCO == 1'b0, "Test 28");
#50

  Clear_bar = 1'b0;
#50
  Clear_bar = 1'b1;
  parallel_load_and_tick(4'b0101);
#90

  tbassert(Q == 4'b0101, "Test 29");
  tbassert(RCO == 1'b0, "Test 29");
#10
  tbassert(Q == 4'b0110, "Test 29");
  tbassert(RCO == 1'b0, "Test 29");
#20


  ENP = 1'b0;
#50
  tbassert(Q == 4'b0110, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#0
  ENP = 1'b1;
#2
  tbassert(Q == 4'b0110, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#50
  tbassert(Q == 4'b0111, "Test 30");
  tbassert(RCO == 1'b0, "Test 30");
#0






  for (i = 10; i <= 15; i++)
  begin
    parallel_load_and_tick(i);
#20
    tbassert2(Q > 4'b1001, "Test", (i - 9), "31");
    tbassert2(RCO == 1'b0, "Test", (i - 9), "31");
#80
    tbassert2(Q >= 0 && Q <= 4'b1001, "Test", (i - 9), "31");
    case_tbassert2(Q < 4'b1001, RCO == 1'b0, "Test", (i - 9), "31");
    case_tbassert2(Q == 4'b1001, RCO == 1'b1, "Test", (i - 9), "31");

  end


#0



  ENT = 1'b1;
  ENP = 1'b0;

  for (i = 10; i <= 15; i++)
  begin
    parallel_load_and_tick(i);
#20
    tbassert2(Q > 4'b1001, "Test", (i - 9), "32");
    tbassert2(RCO == 1'b0, "Test", (i - 9), "32");
#120
    tbassert2(Q > 4'b1001, "Test", (i - 9), "32");
    tbassert2(RCO == 1'b0, "Test", (i - 9), "32");

  end


#0


  ENT = 1'b0;
  ENP = 1'b1;
  parallel_load_and_tick(4'b1001);
#100
  tbassert(RCO == 1'b0, "Test 33");
#10
  ENT = 1'b1;
#15
  tbassert(Q == 4'b1001, "Test 33");
  tbassert(RCO == 1'b1, "Test 33");
#0
  ENT = 1'b0;
#15
  tbassert(RCO == 1'b0, "Test 33");
#0
  wait_tick();
#50
  $finish;
end

endmodule