data/full_repos/permissive/126366342/verilog modules/MMU.v
1: b'%Error: Cannot find file containing module: modules,data/full_repos/permissive/126366342\n        ... Looked in:\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342.v\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342.sv\n             modules,data/full_repos/permissive/126366342\n             modules,data/full_repos/permissive/126366342.v\n             modules,data/full_repos/permissive/126366342.sv\n             obj_dir/modules,data/full_repos/permissive/126366342\n             obj_dir/modules,data/full_repos/permissive/126366342.v\n             obj_dir/modules,data/full_repos/permissive/126366342.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/126366342/verilog\n%Error: Cannot find file containing module: modules/MMU.v\n%Error: Exiting due to 3 error(s)\n'
module data_read_mux(
    input [31:0] A, B, C, D,E,
    input [4:0] Sel,
    output reg [31:0] Y
);
    always @(Sel or A or B or C or D or E) begin
        case(Sel)
            1: Y <= A;
            2: Y <= B;
            4: Y <= C;
				8: Y <= D;
				16: Y <= E; 
            default: Y <= 32'h0000_0000;
        endcase
    end

endmodule
module data_read_mux(
    input [31:0] A, B, C, D,E,
    input [4:0] Sel,
    output reg [31:0] Y
);

    always @(Sel or A or B or C or D or E) begin
        case(Sel)
            1: Y <= A;
            2: Y <= B;
            4: Y <= C;
				8: Y <= D;
				16: Y <= E; 
            default: Y <= 32'h0000_0000;
        endcase
    end

endmodule