data/full_repos/permissive/167856740/cpu/tb/mux3_tb.v
 line:30: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/mux3_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #10 sel = 2\'b01;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/mux3_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10 sel = 2\'b10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/mux3_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #10 sel = 2\'b11;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/mux3_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/mux3_tb.v:14: Cannot find file containing module: \'mux3\'\n mux3 mux3(.I_sel(sel), .I_data1(source_1), .I_data2(source_2), .I_data3(source_3), .O_data(destination));\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/mux3\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/mux3.v\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/mux3.sv\n             mux3\n             mux3.v\n             mux3.sv\n             obj_dir/mux3\n             obj_dir/mux3.v\n             obj_dir/mux3.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux3_tb;
	

	reg [1:0] sel;	
	reg [31:0] source_1;
	reg [31:0] source_2;
	reg [31:0] source_3;
	wire [31:0] destination;


	mux3 mux3(.I_sel(sel), .I_data1(source_1), .I_data2(source_2), .I_data3(source_3), .O_data(destination));

	initial begin

		sel = 2'b00; source_1 = 32'h00000001; source_2 = 32'h00000002; source_3 = 32'h00000003;
	

		#10 sel = 2'b01;
		

        #10 sel = 2'b10;
        

        #10 sel = 2'b11;
		

		#10 $finish;
	end
	
endmodule
module mux3_tb;

	

	reg [1:0] sel;	
	reg [31:0] source_1;
	reg [31:0] source_2;
	reg [31:0] source_3;
	wire [31:0] destination;


	mux3 mux3(.I_sel(sel), .I_data1(source_1), .I_data2(source_2), .I_data3(source_3), .O_data(destination));

	initial begin

		sel = 2'b00; source_1 = 32'h00000001; source_2 = 32'h00000002; source_3 = 32'h00000003;
	

		#10 sel = 2'b01;
		

        #10 sel = 2'b10;
        

        #10 sel = 2'b11;
		

		#10 $finish;
	end
	
endmodule