data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new/ALU.v
None: at end of input
data/verilator_xmls/2fe43e17-67d2-4af0-943e-0381398c9e4b.xml
module ALU(
    input rst,
    input[3:0] alu_ct,
    input[31:0] alu_src1,alu_src2,
    output alu_zero,
    output reg [31:0] alu_res
    );
    assign alu_zero = (alu_res==0)?1:0;
    always@(*)
        if(!rst) begin
            alu_res = 32'bz;
        end else begin
            case(alu_ct)
            4'b0010: alu_res = alu_src1 + alu_src2;
            4'b0110: alu_res = alu_src1 - alu_src2;
            4'b0111: alu_res = (alu_src1 << alu_src2);
            4'b1000: alu_res = (alu_src2 << 16);
            4'b1001: alu_res = (alu_src2 | alu_src1);
            4'b1010: alu_res = (alu_src2 * alu_src1);
            4'b1011: alu_res = (alu_src2 / alu_src1);
            4'b1100: alu_res = (alu_src2 & alu_src1);
            4'b1101: alu_res = (alu_src2 ^ alu_src1);
            4'b1110: alu_res = ~(alu_src2 | alu_src1);
            4'b1111: alu_res = (alu_src2 < alu_src1)?1:0;
            default: begin
            end
            endcase
        end
endmodule
module ALU(
    input rst,
    input[3:0] alu_ct,
    input[31:0] alu_src1,alu_src2,
    output alu_zero,
    output reg [31:0] alu_res
    );

    assign alu_zero = (alu_res==0)?1:0;
    always@(*)
        if(!rst) begin
            alu_res = 32'bz;
        end else begin
            case(alu_ct)
            4'b0010: alu_res = alu_src1 + alu_src2;
            4'b0110: alu_res = alu_src1 - alu_src2;
            4'b0111: alu_res = (alu_src1 << alu_src2);
            4'b1000: alu_res = (alu_src2 << 16);
            4'b1001: alu_res = (alu_src2 | alu_src1);
            4'b1010: alu_res = (alu_src2 * alu_src1);
            4'b1011: alu_res = (alu_src2 / alu_src1);
            4'b1100: alu_res = (alu_src2 & alu_src1);
            4'b1101: alu_res = (alu_src2 ^ alu_src1);
            4'b1110: alu_res = ~(alu_src2 | alu_src1);
            4'b1111: alu_res = (alu_src2 < alu_src1)?1:0;
            default: begin
            end
            endcase
        end
endmodule