data/full_repos/permissive/210844779/lab6/6.3/tb.v
 line:11: before: "forever"
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab6/6.3/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #9\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab6/6.3/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #9;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab6/6.3/tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #25\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab6/6.3/tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab6/6.3/tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #25 d=$random;\n    ^\n%Error: data/full_repos/permissive/210844779/lab6/6.3/tb.v:5: Cannot find file containing module: \'top\'\n  top u0(d,clk,rst,q);\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab6/6.3,data/full_repos/permissive/210844779/top\n             data/full_repos/permissive/210844779/lab6/6.3,data/full_repos/permissive/210844779/top.v\n             data/full_repos/permissive/210844779/lab6/6.3,data/full_repos/permissive/210844779/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab6/6.3/tb.v:25: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n    #25 d=$random;\n         ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  reg d,clk,rst;
  wire q;
  
  top u0(d,clk,rst,q);
  
  initial
  begin
    clk=0;
    #25
    forever
    begin
      clk=0;
      #9
      clk=1;
      #9;
    end
  end
  
  initial
  begin
    rst=1;d=0;
    #10 rst=0;
    forever
    #25 d=$random;
  end
  
endmodule
module tb();

  reg d,clk,rst;
  wire q;
  
  top u0(d,clk,rst,q);
  
  initial
  begin
    clk=0;
    #25
    forever
    begin
      clk=0;
      #9
      clk=1;
      #9;
    end
  end
  
  initial
  begin
    rst=1;d=0;
    #10 rst=0;
    forever
    #25 d=$random;
  end
  
endmodule