data/full_repos/permissive/161029703/src/uart/uart_tx.v
1: b'%Error: data/full_repos/permissive/161029703/src/uart/uart_tx.v:45: Cannot find file containing module: \'clk_ctrl\'\nclk_ctrl rst(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161029703/src/uart,data/full_repos/permissive/161029703/clk_ctrl\n             data/full_repos/permissive/161029703/src/uart,data/full_repos/permissive/161029703/clk_ctrl.v\n             data/full_repos/permissive/161029703/src/uart,data/full_repos/permissive/161029703/clk_ctrl.sv\n             clk_ctrl\n             clk_ctrl.v\n             clk_ctrl.sv\n             obj_dir/clk_ctrl\n             obj_dir/clk_ctrl.v\n             obj_dir/clk_ctrl.sv\n%Error: data/full_repos/permissive/161029703/src/uart/uart_tx.v:51: Cannot find file containing module: \'flag_sync\'\nflag_sync sync_tx_req( \n^~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/uart/uart_tx.v:59: Cannot find file containing module: \'flag_sync\'\nflag_sync sync_tx_done( \n^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161029703/src/uart/uart_tx.v:106: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'COUNTER_PERIOD\' generates 32 or 24 bits.\n                                                                           : ... In instance uart_tx\n                baud_cnt <= COUNTER_PERIOD;\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161029703/src/uart/uart_tx.v:111: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                           : ... In instance uart_tx\n                tx_done <= 4\'b1;\n                        ^~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module uart_tx(

            idle,
            txd,

            clk_bus,
            clk_uart,
            rst_n,
            tx_request,
            data);

parameter ignore_for_sim = 1'b0;

parameter BAUD = 115200;
parameter UART_CLK = 11059200;
parameter COUNTER_PERIOD = UART_CLK/BAUD-1;

`define START_BIT 1'b0
`define STOP_BIT  1'b1

input wire clk_bus;
input wire clk_uart;
input wire rst_n;

input wire tx_request;
input wire[7:0] data;
output reg idle;

output reg txd;

reg tx_request_reg;
reg[7:0] data_reg;
wire tx_done_sync;

reg tx_done;
wire tx_request_sync;
reg[7:0] data_sync[0:1];
reg[9:0] send_buf;
reg[3:0] state;
reg[3:0] remain_bit;
reg[14:0] baud_cnt;

wire clk_uart_rst_n;

clk_ctrl rst(
    .clk      (clk_uart),
    .rst_in_n (rst_n),
    .rst_out_n(clk_uart_rst_n)
);

flag_sync sync_tx_req(
         .FlagOut_clkB(tx_request_sync),
         .a_rst_n(rst_n),
         .clkA(clk_bus),
         .FlagIn_clkA(tx_request_reg),
         .b_rst_n(clk_uart_rst_n),
         .clkB(clk_uart));

flag_sync sync_tx_done(
         .FlagOut_clkB(tx_done_sync),
         .a_rst_n(rst_n),
         .clkA(clk_uart),
         .FlagIn_clkA(tx_done),
         .b_rst_n(clk_uart_rst_n),
         .clkB(clk_bus));

always @(posedge clk_bus or negedge rst_n) begin
    if (!rst_n) begin
        idle <= 1'b1;
        tx_request_reg <= 1'b0;
    end else begin
        tx_request_reg <= 1'b0;
        if(idle && tx_request && ignore_for_sim) begin
            $write("%c",data);
        end
        if(idle && tx_request && !ignore_for_sim) begin
            tx_request_reg <= 1'b1;
            data_reg <= data;
            idle <= 1'b0;
        end else if(tx_done_sync) begin
            idle <= 1'b1;
        end
    end
end

always @(posedge clk_uart or negedge clk_uart_rst_n) begin
    if (!clk_uart_rst_n) begin
        state <= 4'h0;
        txd <= 1'b1;
        tx_done <= 1'b0;
    end
    else begin
        data_sync[0] <= data_reg;
        data_sync[1] <= data_sync[0];
        tx_done <= 1'b0;
        case(state)
        4'h0: begin
            if(tx_request_sync) begin
                state <= 4'h1;
                remain_bit <= 4'd10;
                send_buf <= {`STOP_BIT,data_sync[1],`START_BIT};
            end
        end
        4'h1: begin
            if(remain_bit!=4'd0) begin
                baud_cnt <= COUNTER_PERIOD;
                txd <= send_buf[0];
                send_buf <= send_buf>>1;
                state <= 4'h2;
            end else begin
                tx_done <= 4'b1;
                txd <= 1'b1;
                state <= 4'h0;
            end
        end
        4'h2: begin
            if(baud_cnt == 0)begin
                state <= 4'h1;
                remain_bit <= remain_bit-1'b1;
            end else begin
                baud_cnt <= baud_cnt - 1'b1;
            end
        end
        endcase
    end
end
endmodule
module uart_tx(

            idle,
            txd,

            clk_bus,
            clk_uart,
            rst_n,
            tx_request,
            data);


parameter ignore_for_sim = 1'b0;

parameter BAUD = 115200;
parameter UART_CLK = 11059200;
parameter COUNTER_PERIOD = UART_CLK/BAUD-1;

`define START_BIT 1'b0
`define STOP_BIT  1'b1

input wire clk_bus;
input wire clk_uart;
input wire rst_n;

input wire tx_request;
input wire[7:0] data;
output reg idle;

output reg txd;

reg tx_request_reg;
reg[7:0] data_reg;
wire tx_done_sync;

reg tx_done;
wire tx_request_sync;
reg[7:0] data_sync[0:1];
reg[9:0] send_buf;
reg[3:0] state;
reg[3:0] remain_bit;
reg[14:0] baud_cnt;

wire clk_uart_rst_n;

clk_ctrl rst(
    .clk      (clk_uart),
    .rst_in_n (rst_n),
    .rst_out_n(clk_uart_rst_n)
);

flag_sync sync_tx_req(
         .FlagOut_clkB(tx_request_sync),
         .a_rst_n(rst_n),
         .clkA(clk_bus),
         .FlagIn_clkA(tx_request_reg),
         .b_rst_n(clk_uart_rst_n),
         .clkB(clk_uart));

flag_sync sync_tx_done(
         .FlagOut_clkB(tx_done_sync),
         .a_rst_n(rst_n),
         .clkA(clk_uart),
         .FlagIn_clkA(tx_done),
         .b_rst_n(clk_uart_rst_n),
         .clkB(clk_bus));

always @(posedge clk_bus or negedge rst_n) begin
    if (!rst_n) begin
        idle <= 1'b1;
        tx_request_reg <= 1'b0;
    end else begin
        tx_request_reg <= 1'b0;
        if(idle && tx_request && ignore_for_sim) begin
            $write("%c",data);
        end
        if(idle && tx_request && !ignore_for_sim) begin
            tx_request_reg <= 1'b1;
            data_reg <= data;
            idle <= 1'b0;
        end else if(tx_done_sync) begin
            idle <= 1'b1;
        end
    end
end

always @(posedge clk_uart or negedge clk_uart_rst_n) begin
    if (!clk_uart_rst_n) begin
        state <= 4'h0;
        txd <= 1'b1;
        tx_done <= 1'b0;
    end
    else begin
        data_sync[0] <= data_reg;
        data_sync[1] <= data_sync[0];
        tx_done <= 1'b0;
        case(state)
        4'h0: begin
            if(tx_request_sync) begin
                state <= 4'h1;
                remain_bit <= 4'd10;
                send_buf <= {`STOP_BIT,data_sync[1],`START_BIT};
            end
        end
        4'h1: begin
            if(remain_bit!=4'd0) begin
                baud_cnt <= COUNTER_PERIOD;
                txd <= send_buf[0];
                send_buf <= send_buf>>1;
                state <= 4'h2;
            end else begin
                tx_done <= 4'b1;
                txd <= 1'b1;
                state <= 4'h0;
            end
        end
        4'h2: begin
            if(baud_cnt == 0)begin
                state <= 4'h1;
                remain_bit <= remain_bit-1'b1;
            end else begin
                baud_cnt <= baud_cnt - 1'b1;
            end
        end
        endcase
    end
end
endmodule