data/full_repos/permissive/102515926/Modules/COMP.v
data/verilator_xmls/4e8197ed-b720-48f1-85d1-70f9e63aeeb2.xml
module COMP(a, b, gt, lt, eq);

    parameter DATAWIDTH = 64;

    input [DATAWIDTH - 1:0] a, b;
    output reg gt, lt, eq;
    
    initial begin
        gt <= 0; lt <= 0; eq <= 0;
    end
    
    always @(*) begin
        gt <= 0; lt <= 0; eq <= 0;
    
        if($signed(a) > $signed(b))
            gt <= 1;
        else if($signed(a) < $signed(b))
            lt <= 1;
        else
            eq <= 1;
    
    end
    
endmodule
module COMP(a, b, gt, lt, eq);


    parameter DATAWIDTH = 64;

    input [DATAWIDTH - 1:0] a, b;
    output reg gt, lt, eq;
    
    initial begin
        gt <= 0; lt <= 0; eq <= 0;
    end
    
    always @(*) begin
        gt <= 0; lt <= 0; eq <= 0;
    
        if($signed(a) > $signed(b))
            gt <= 1;
        else if($signed(a) < $signed(b))
            lt <= 1;
        else
            eq <= 1;
    
    end
    
endmodule