data/full_repos/permissive/161526648/Hazard_Detection.v
data/verilator_xmls/fac1ae31-50ba-4e6a-9326-917c24033185.xml
module Hazard_Detection(rt_ex,rs,rt,MemRead_ex,IDFlush,PCWrite,IFIDWrite);
	input[4:0] rt_ex,rs,rt;
	input MemRead_ex;
	output reg IDFlush,PCWrite,IFIDWrite;
	
	initial begin
	   IFIDWrite <= 1'b0;
	   PCWrite <= 1'b0;
		IDFlush <= 1'b0;
	end
	
	always @(rt_ex or rs or rt or MemRead_ex) 
	begin
	if ((MemRead_ex==1) && ((rt_ex==rs) || (rt_ex==rt))) 
	   begin
		IFIDWrite <= 1'b1;
		PCWrite <= 1'b1;
		IDFlush <= 1'b1;
		end
	else
	   begin
			IFIDWrite <= 1'b0;
			PCWrite <= 1'b0;
			IDFlush <= 1'b0;
		end
	end
endmodule
module Hazard_Detection(rt_ex,rs,rt,MemRead_ex,IDFlush,PCWrite,IFIDWrite);

	input[4:0] rt_ex,rs,rt;
	input MemRead_ex;
	output reg IDFlush,PCWrite,IFIDWrite;
	
	initial begin
	   IFIDWrite <= 1'b0;
	   PCWrite <= 1'b0;
		IDFlush <= 1'b0;
	end
	
	always @(rt_ex or rs or rt or MemRead_ex) 
	begin
	if ((MemRead_ex==1) && ((rt_ex==rs) || (rt_ex==rt))) 
	   begin
		IFIDWrite <= 1'b1;
		PCWrite <= 1'b1;
		IDFlush <= 1'b1;
		end
	else
	   begin
			IFIDWrite <= 1'b0;
			PCWrite <= 1'b0;
			IDFlush <= 1'b0;
		end
	end
endmodule