data/full_repos/permissive/133651929/late_1_TB.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #30;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #15 rst     = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #15 rst     = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10 enable  = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10 rd_en   = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #20 rx_data = 8\'b10101010;    \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #70 enable  = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #70 rd_en   = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10 enable  = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10 rd_en   = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #20 rx_data = 8\'b00011000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #70 enable  = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #70 rd_en   = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_TB.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #500 $finish;         \n  ^\n%Error: data/full_repos/permissive/133651929/late_1_TB.v:16: Cannot find file containing module: \'late_1\'\n late_1 uut (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133651929,data/full_repos/permissive/133651929/late_1\n             data/full_repos/permissive/133651929,data/full_repos/permissive/133651929/late_1.v\n             data/full_repos/permissive/133651929,data/full_repos/permissive/133651929/late_1.sv\n             late_1\n             late_1.v\n             late_1.sv\n             obj_dir/late_1\n             obj_dir/late_1.v\n             obj_dir/late_1.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module late_1_TB;


	reg clk;
	reg rst;
	reg enable;
	reg rd_en;
	reg [7:0] rx_data;


	wire tx;


	late_1 uut (
		.clk(clk), 
		.rst(rst), 
		.enable(enable), 
		.rd_en(rd_en), 
		.tx(tx), 
		.rx_data(rx_data)
	);
	
	initial 
		begin
			clk = 0;
			forever 
				begin
					clk = #5 !clk;
				end
		end
	initial 
	begin

		clk = 0;
		rst = 0;
		enable = 0;
		rd_en = 0;
		rx_data = 0;


		#30;
        
		
		#15 rst     = 1'b1;
		#15 rst     = 1'b0;
		#10 enable  = 1'b1;
		#10 rd_en   = 1'b1;
		#20 rx_data = 8'b10101010;				
		#70 enable  = 1'b0;
		#70 rd_en   = 1'b0;
		#10 enable  = 1'b1;
		#10 rd_en   = 1'b1;
		#20 rx_data = 8'b00011000;
		#70 enable  = 1'b0;
		#70 rd_en   = 1'b0;
		

		
		#500 $finish;

	end
      
endmodule
module late_1_TB;



	reg clk;
	reg rst;
	reg enable;
	reg rd_en;
	reg [7:0] rx_data;


	wire tx;


	late_1 uut (
		.clk(clk), 
		.rst(rst), 
		.enable(enable), 
		.rd_en(rd_en), 
		.tx(tx), 
		.rx_data(rx_data)
	);
	
	initial 
		begin
			clk = 0;
			forever 
				begin
					clk = #5 !clk;
				end
		end
	initial 
	begin

		clk = 0;
		rst = 0;
		enable = 0;
		rd_en = 0;
		rx_data = 0;


		#30;
        
		
		#15 rst     = 1'b1;
		#15 rst     = 1'b0;
		#10 enable  = 1'b1;
		#10 rd_en   = 1'b1;
		#20 rx_data = 8'b10101010;				
		#70 enable  = 1'b0;
		#70 rd_en   = 1'b0;
		#10 enable  = 1'b1;
		#10 rd_en   = 1'b1;
		#20 rx_data = 8'b00011000;
		#70 enable  = 1'b0;
		#70 rd_en   = 1'b0;
		

		
		#500 $finish;

	end
      
endmodule