data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:10: Define or directive not defined: \'`MemAddrWidth\'\n        input wire[`MemAddrWidth-1:0] if_pc,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:11: Define or directive not defined: \'`InstWidth\'\n        input wire[`InstWidth-1:0] if_inst,\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:18: Define or directive not defined: \'`MemAddrWidth\'\n        output reg[`MemAddrWidth-1:0] id_pc,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:19: Define or directive not defined: \'`InstWidth\'\n        output reg[`InstWidth-1:0] id_inst\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:24: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable)\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (rst == `RstEnable)\n                             ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:26: Define or directive not defined: \'`ZeroWord\'\n            id_pc <= `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:27: Define or directive not defined: \'`ZeroWord\'\n            id_inst <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            id_inst <= `ZeroWord;\n                                ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:29: Define or directive not defined: \'`JumpUncdt\'\n   if (idex_jump_type == `JumpUncdt \n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:30: Define or directive not defined: \'`JumpBranch\'\n    || (idex_jump_type == `JumpBranch && ex_jump)) begin\n                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:31: Define or directive not defined: \'`ZeroWord\'\n    id_pc <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:32: Define or directive not defined: \'`NopInst\'\n    id_inst <= `NopInst;\n               ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:48: Define or directive not defined: \'`AluOpWidth\'\n  input wire[`AluOpWidth-1:0]  id_aluop,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:49: Define or directive not defined: \'`AluSelWidth\'\n  input wire[`AluSelWidth-1:0] id_alusel,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:50: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] id_reg1,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:51: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] id_reg2,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:52: Define or directive not defined: \'`RegAddrWidth\'\n  input wire[`RegAddrWidth-1:0] id_wd,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:54: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] id_addr_base,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:55: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] id_addr_off,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:61: Define or directive not defined: \'`AluOpWidth\'\n  output reg[`AluOpWidth-1:0]  ex_aluop,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:62: Define or directive not defined: \'`AluSelWidth\'\n  output reg[`AluSelWidth-1:0] ex_alusel,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:63: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] ex_reg1,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:64: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] ex_reg2,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:65: Define or directive not defined: \'`RegAddrWidth\'\n  output reg[`RegAddrWidth-1:0] ex_wd,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:67: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] ex_addr_base,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:68: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] ex_addr_off,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:77: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if(rst == `RstEnable) begin\n                      ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:78: Define or directive not defined: \'`EXE_NOP_OP\'\n   ex_aluop <= `EXE_NOP_OP;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:79: Define or directive not defined: \'`EXE_NOP_RES\'\n   ex_alusel <= `EXE_NOP_RES;\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_alusel <= `EXE_NOP_RES;\n                            ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:80: Define or directive not defined: \'`ZeroWord\'\n   ex_reg1  <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_reg1  <= `ZeroWord;\n                        ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:81: Define or directive not defined: \'`ZeroWord\'\n   ex_reg2  <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_reg2  <= `ZeroWord;\n                        ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:82: Define or directive not defined: \'`ZeroRegAddr\'\n   ex_wd  <= `ZeroRegAddr;\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:82: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_wd  <= `ZeroRegAddr;\n                         ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:83: Define or directive not defined: \'`WriteDisable\'\n   ex_wreg  <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_wreg  <= `WriteDisable;\n                            ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:84: Define or directive not defined: \'`ZeroWord\'\n   ex_addr_base <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_addr_base <= `ZeroWord;\n                            ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:85: Define or directive not defined: \'`ZeroWord\'\n   ex_addr_off <= `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:85: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_addr_off <= `ZeroWord;\n                           ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:86: Define or directive not defined: \'`NoJump\'\n   jump_type_o <= `NoJump;\n                  ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   jump_type_o <= `NoJump;\n                         ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:87: Define or directive not defined: \'`MEM_NOP\'\n   memop_o  <= `MEM_NOP;\n               ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:87: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   memop_o  <= `MEM_NOP;\n                       ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:89: syntax error, unexpected else\n  end else if(!stall[2]) begin\n      ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ex_mem(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,
        

        input wire[`RegDataWidth-1:0] ex_wdata,
        input wire[`RegAddrWidth-1:0] ex_wd,
        input wire ex_wreg,
		input wire[`MemAddrWidth-1:0] ex_addr,
		input wire[1:0] memop_i,
		input wire[2:0] memfunct_i,
        

        output reg[`RegDataWidth-1:0] mem_wdata,            
        output reg[`RegAddrWidth-1:0] mem_wd,               
        output reg mem_wreg,
		output reg[`MemAddrWidth-1:0] mem_addr,
		output reg[1:0] memop_o,
		output reg[2:0] memfunct_o
    );
    
    always @ (posedge clk) 
    begin
        if (rst == `RstEnable) begin
            mem_wdata <= `ZeroWord;
            mem_wd <= `ZeroRegAddr;
            mem_wreg <= `WriteDisable;
			mem_addr <= `ZeroWord;
			memop_o <= 0;
			memfunct_o <= 0;
        end else if (!stall[3]) begin
            mem_wdata <= ex_wdata;
            mem_wd <= ex_wd;
            mem_wreg <= ex_wreg;
			mem_addr <= ex_addr;
			memop_o <= memop_i;
			memfunct_o <= memfunct_i;
        end
    end
endmodule
module ex_mem(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,
        

        input wire[`RegDataWidth-1:0] ex_wdata,
        input wire[`RegAddrWidth-1:0] ex_wd,
        input wire ex_wreg,
		input wire[`MemAddrWidth-1:0] ex_addr,
		input wire[1:0] memop_i,
		input wire[2:0] memfunct_i,
        

        output reg[`RegDataWidth-1:0] mem_wdata,            
        output reg[`RegAddrWidth-1:0] mem_wd,               
        output reg mem_wreg,
		output reg[`MemAddrWidth-1:0] mem_addr,
		output reg[1:0] memop_o,
		output reg[2:0] memfunct_o
    );

    
    always @ (posedge clk) 
    begin
        if (rst == `RstEnable) begin
            mem_wdata <= `ZeroWord;
            mem_wd <= `ZeroRegAddr;
            mem_wreg <= `WriteDisable;
			mem_addr <= `ZeroWord;
			memop_o <= 0;
			memfunct_o <= 0;
        end else if (!stall[3]) begin
            mem_wdata <= ex_wdata;
            mem_wd <= ex_wd;
            mem_wreg <= ex_wreg;
			mem_addr <= ex_addr;
			memop_o <= memop_i;
			memfunct_o <= memfunct_i;
        end
    end
endmodule