data/full_repos/permissive/149912776/verilog_modules/data_storage/ff_d_sr.v
1: b"%Error: data/full_repos/permissive/149912776/verilog_modules/data_storage/ff_d_sr.v:5: Can't find definition of variable: 'clk'\nalways @ (posedge clk)\n                  ^~~\n%Error: Exiting due to 1 error(s)\n"
module ff_d_sr (Q, D, CLK, RST);
input D, CLK, RST;
output Q;
reg Q;
always @ (posedge clk)
begin
    if (~RST)
    Q <= D;
    else
    Q <= 0'b0;
end
endmodule
module ff_d_sr (Q, D, CLK, RST);

input D, CLK, RST;
output Q;
reg Q;
always @ (posedge clk)
begin
    if (~RST)
    Q <= D;
    else
    Q <= 0'b0;
end
endmodule