data/full_repos/permissive/214823094/lab_6/project_2/project_2.srcs/sources_1/new/traffic_lights_2.v
data/verilator_xmls/4e60f4d5-05cb-41f5-84ae-4a8cd8665f26.xml
module traffic_lights_2(
    input C,
    input clk,
    input reset,
    output reg [2:0] H,
    output reg [2:0] F
    );
    
    wire TS,TL;
    wire myclk;
    reg ST;
    wire ST1;
    wire [2:0] H1;
    wire [2:0] F1;
    clkdiv c1(clk,myclk);
    counter cnt1(myclk,ST1,TS,TL);
    always@(ST1)
        ST<=ST1;
    FSM f1(TS,TL,C,ST1,H1[2:0],F1[2:0]);
    always@(TS,TL,reset,C)
    begin
        if(reset)
        begin
        H<=3'b001;
        F<=3'b100;
        ST<=1;
        end
        else
        begin
        H<=H1;
        F<=F1;
        end
        
    end
    
endmodule
module traffic_lights_2(
    input C,
    input clk,
    input reset,
    output reg [2:0] H,
    output reg [2:0] F
    );

    
    wire TS,TL;
    wire myclk;
    reg ST;
    wire ST1;
    wire [2:0] H1;
    wire [2:0] F1;
    clkdiv c1(clk,myclk);
    counter cnt1(myclk,ST1,TS,TL);
    always@(ST1)
        ST<=ST1;
    FSM f1(TS,TL,C,ST1,H1[2:0],F1[2:0]);
    always@(TS,TL,reset,C)
    begin
        if(reset)
        begin
        H<=3'b001;
        F<=3'b100;
        ST<=1;
        end
        else
        begin
        H<=H1;
        F<=F1;
        end
        
    end
    
endmodule