data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Divider.v
data/verilator_xmls/3c84deba-42bb-4d3f-b058-02cce90d1df1.xml
module Divider #(
        parameter N = 100_000_000
    )(
        input clk,
        output reg clk_N
    );

    reg [31: 0] counter = 0;

    initial begin
        counter = 0;
        clk_N = 0;
    end

    always @(posedge clk) begin
        counter <= counter + 1;
        if(counter == N / 2) begin
            clk_N <= ~clk_N;
            counter <= 0;
        end
    end
endmodule
module Divider #(
        parameter N = 100_000_000
    )(
        input clk,
        output reg clk_N
    );


    reg [31: 0] counter = 0;

    initial begin
        counter = 0;
        clk_N = 0;
    end

    always @(posedge clk) begin
        counter <= counter + 1;
        if(counter == N / 2) begin
            clk_N <= ~clk_N;
            counter <= 0;
        end
    end
endmodule