data/full_repos/permissive/178052224/Tarea6/demux_valid/src/probador.v
1: b'%Error: data/full_repos/permissive/178052224/Tarea6/demux_valid/src/probador.v:12: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("demux_1x2.vcd");                \n      ^~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea6/demux_valid/src/probador.v:13: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;                                 \n      ^~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea6/demux_valid/src/probador.v:17: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/178052224/Tarea6/demux_valid/src/probador.v:22: syntax error, unexpected \'@\'\n             @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/178052224/Tarea6/demux_valid/src/probador.v:27: syntax error, unexpected \'@\'\n             @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/178052224/Tarea6/demux_valid/src/probador.v:35: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea6/demux_valid/src/probador.v:40: Unsupported: Ignoring delay on this delayed statement.\n    always  #2 clk  <= ~clk;                     \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea6/demux_valid/src/probador.v:41: Unsupported: Ignoring delay on this delayed statement.\n    always  #10 data_in <= $random % 16;\n            ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador(
                    input [3:0]	data_out0, data_out1, data_tran,
                    output reg clk,
                    output reg reset_L,
                    output reg valid_in,
                    output reg [3:0] data_in,
                    input valid_out0, valid_out1
                    );
 
   initial
     begin
      $dumpfile("demux_1x2.vcd");
      $dumpvars;
         
         valid_in<= 0;                      
         reset_L <= 'b0;
         @(posedge clk);
            reset_L <= 1;
            valid_in <= 1;
         
         repeat(10)begin
             @(posedge clk);
                valid_in <= 0;  
         end

         repeat(20)begin
             @(posedge clk);
                valid_in <= 1;  
         end

         repeat(5)begin
          reset_L <= 0;
         end
         
         @(posedge clk);
         reset_L <='b0;
         $finish;
     end
    
    always  #2 clk  <= ~clk;
    always  #10 data_in <= $random % 16;
    initial clk <= 0;
    initial data_in <= 'b0;


endmodule
module probador(
                    input [3:0]	data_out0, data_out1, data_tran,
                    output reg clk,
                    output reg reset_L,
                    output reg valid_in,
                    output reg [3:0] data_in,
                    input valid_out0, valid_out1
                    );

 
   initial
     begin
      $dumpfile("demux_1x2.vcd");
      $dumpvars;
         
         valid_in<= 0;                      
         reset_L <= 'b0;
         @(posedge clk);
            reset_L <= 1;
            valid_in <= 1;
         
         repeat(10)begin
             @(posedge clk);
                valid_in <= 0;  
         end

         repeat(20)begin
             @(posedge clk);
                valid_in <= 1;  
         end

         repeat(5)begin
          reset_L <= 0;
         end
         
         @(posedge clk);
         reset_L <='b0;
         $finish;
     end
    
    always  #2 clk  <= ~clk;
    always  #10 data_in <= $random % 16;
    initial clk <= 0;
    initial data_in <= 'b0;


endmodule