data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v
 line:1: before: "function"
1: b'%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:4: syntax error, unexpected ::, expecting \'(\' or \';\'\nfunction void UNI_cell::post_randomize();\n                      ^~\n                                                                   : ... Perhaps \'UNI_cell\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:13: Unsupported: virtual classes\nvirtual class BaseTr;\n^~~~~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:13: Unsupported: classes\nvirtual class BaseTr;\n        ^~~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:14: Unsupported: new constructor\n  function new();\n           ^~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:15: syntax error, unexpected ++, expecting \';\'\n    id = count++;\n              ^~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:18: Unsupported: pure virtual class method\n  pure virtual function bit compare(input BaseTr to);\n  ^~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:19: Unsupported: pure virtual class method\n  pure virtual function BaseTr copy(input BaseTr to=null);\n  ^~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:20: Unsupported: pure virtual class method\n  pure virtual function void display(input string prefix="");\n  ^~~~\n%Error: data/full_repos/permissive/20985349/maze/maze-sv2009/m2.v:26: syntax error, unexpected "\'", expecting TYPE-IDENTIFIER\ninteger threes[4] = \' { 3, 6, 9, 12 };\n                    ^\n%Error: Exiting due to 9 error(s)\n'
module spc2wbm (




    input sys_clock_i,
    input sys_reset_i,
    input[5:0] sys_interrupt_source_i,


    input[4:0] spc_req_i,
    input spc_atom_i,
    input[(   124  -1):0] spc_packetout_i,


    input wbm_ack_i,
    input[( 64-1):0] wbm_data_i,




    output reg[4:0] spc_grant_o,
    output reg spc_ready_o,
    output reg[   145  -1:0] spc_packetin_o,
    output reg spc_stall_o,
    output reg spc_resume_o,


    output reg wbm_cycle_o,
    output reg wbm_strobe_o,
    output reg wbm_we_o,
    output reg[ 64-1:0] wbm_addr_o,
    output reg[ 64-1:0] wbm_data_o,
    output reg[ 64/8-1:0] wbm_sel_o

  );





  reg[3:0] state;
  reg[4:0] spc2wbm_region;
  reg spc2wbm_atomic;
  reg[(   124  -1):0] spc2wbm_packet;


  reg wbm2spc_valid;
  reg[(       143  -       140):0] wbm2spc_type;
  reg wbm2spc_miss;
  reg[(      139  -      137-1):0] wbm2spc_error;
  reg wbm2spc_nc;
  reg[(       135  -       134):0] wbm2spc_thread;
  reg wbm2spc_way_valid;
  reg[(       132  -       131):0] wbm2spc_way;
  reg wbm2spc_boot_fetch;
  reg wbm2spc_atomic;
  reg wbm2spc_pfl;
  reg[(       127  -         0):0] wbm2spc_data;
  reg[6:0] wbm2spc_interrupt_source;
  reg wbm2spc_interrupt_new;




  wire spc2wbm_req;
  wire spc2wbm_valid;
  wire[(       122  -       118):0] spc2wbm_type;
  wire spc2wbm_nc;
  wire[(       116  -       114):0] spc2wbm_cpu_id;
  wire[(       113  -       112):0] spc2wbm_thread;
  wire spc2wbm_invalidate;
  wire[(       108  -       107):0] spc2wbm_way;
  wire[(       106  -       104):0] spc2wbm_size;
  wire[(       103  -        64):0] spc2wbm_addr;
  wire[(        63  -         0):0] spc2wbm_data;


  wire[   145  -1:0] wbm2spc_packet;




  assign spc2wbm_req = ( spc_req_i[4] | spc_req_i[3] | spc_req_i[2] | spc_req_i[1] | spc_req_i[0] );
  assign spc2wbm_valid = spc2wbm_packet[         123  ];
  assign spc2wbm_type = spc2wbm_packet[       122  :       118];
  assign spc2wbm_nc = spc2wbm_packet[          117  ];
  assign spc2wbm_cpu_id = spc2wbm_packet[       116  :       114];
  assign spc2wbm_thread = spc2wbm_packet[       113  :       112];
  assign spc2wbm_invalidate = spc2wbm_packet[      111];
  assign spc2wbm_way = spc2wbm_packet[       108  :       107];
  assign spc2wbm_size = spc2wbm_packet[       106  :       104];
  assign spc2wbm_addr = spc2wbm_packet[       103  :        64];
  assign spc2wbm_data = spc2wbm_packet[        63  :         0];


  assign wbm2spc_packet = { wbm2spc_valid, wbm2spc_type, wbm2spc_miss, wbm2spc_error, wbm2spc_nc, wbm2spc_thread,
    wbm2spc_way_valid, wbm2spc_way, wbm2spc_boot_fetch, wbm2spc_atomic, wbm2spc_pfl, wbm2spc_data };



  always @(posedge sys_clock_i) begin


    if(sys_reset_i==1) begin


      spc_grant_o <= 5'b00000;
      spc_ready_o <= 0;
      spc_packetin_o <= 0;
      spc_stall_o <= 0;
      spc_resume_o <= 0;


      wbm_cycle_o <= 0;
      wbm_strobe_o <= 0;
      wbm_we_o <= 0;
      wbm_addr_o <= 64'b0;
      wbm_data_o <= 64'b0;
      wbm_sel_o <= 8'b0;



      wbm2spc_valid <= 1;
      wbm2spc_type <=          4'b0111;
      wbm2spc_miss <= 0;
      wbm2spc_error <= 0;
      wbm2spc_nc <= 0;
      wbm2spc_thread <= 0;
      wbm2spc_way_valid <= 0;
      wbm2spc_way <= 0;
      wbm2spc_boot_fetch <= 0;
      wbm2spc_atomic <= 0;
      wbm2spc_pfl <= 0;
      wbm2spc_data <= 64'h10001;
      wbm2spc_interrupt_source <= 7'h0;
      wbm2spc_interrupt_new <= 1'b0;


      state <=           4'b0000;

    end else begin



      if(state==          4'b0000) begin


        spc_ready_o <= 1;
        spc_packetin_o <= wbm2spc_packet;



            
        $display("INFO: SPC2WBM: SPARC Core to Wishbone Master bridge starting...");
        $display("INFO: SPC2WBM: Wakeup packet sent to SPARC Core");
      



        state <=             4'b0001;




      end else if(state==            4'b0001) begin


        if(spc2wbm_req==1) begin


          spc_ready_o <= 0;
          spc_packetin_o <= 0;


          spc_stall_o <= 1;


          spc2wbm_region <= spc_req_i;
          spc2wbm_atomic <= spc_atom_i;


          state <=  4'b0010;


        end else if(sys_interrupt_source_i!=wbm2spc_interrupt_source) begin


          wbm2spc_interrupt_new <= 1;


          wbm2spc_valid <= 1;
          wbm2spc_type <=          4'b0111;
          wbm2spc_miss <= 0;
          wbm2spc_error <= 0;
          wbm2spc_nc <= 0;
          wbm2spc_thread <= 0;
          wbm2spc_way_valid <= 0;
          wbm2spc_way <= 0;
          wbm2spc_boot_fetch <= 0;
          wbm2spc_atomic <= 0;
          wbm2spc_pfl <= 0;


        end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_interrupt_new) begin


          wbm2spc_interrupt_new <= 0;


          spc_ready_o <= 1;
          spc_packetin_o <= wbm2spc_packet;


          state <=             4'b0001;


        end else begin


          spc_ready_o <= 0;
          spc_packetin_o <= 0;


          spc_stall_o <= 0;
      spc_resume_o <= 0;


          state <=             4'b0001;

        end





      end else if(state== 4'b0010) begin


        spc2wbm_packet <= spc_packetout_i;


        spc_grant_o <= spc2wbm_region;


        spc_stall_o <= 0;



            
        $display("INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE ***");
        if(spc2wbm_region[0]==1) $display("INFO: SPC2WBM: Request to RAM Bank 0");
        else if(spc2wbm_region[1]==1) $display("INFO: SPC2WBM: Request to RAM Bank 1");
        else if(spc2wbm_region[2]==1) $display("INFO: SPC2WBM: Request to RAM Bank 2");
        else if(spc2wbm_region[3]==1) $display("INFO: SPC2WBM: Request to RAM Bank 3");
        else if(spc2wbm_region[4]==1) $display("INFO: SPC2WBM: Request targeted to I/O Block");
        else $display("INFO: SPC2WBM: Request to target region unknown");
        if(spc2wbm_atomic==1) $display("INFO: SPC2WBM: Request is ATOMIC");
        else $display("INFO: SPC2WBM: Request is not atomic");
      



        state <=   4'b0011;





      end else if(state==  4'b0011) begin


        spc_grant_o <= 5'b0;


        wbm_cycle_o <= 1;
        wbm_strobe_o <= 1;
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[       103  -        64:3], 3'b000 };
        wbm_data_o <= spc2wbm_data;


        if(spc2wbm_type==    5'b10000) begin


          wbm_we_o <= 0;
          if(spc2wbm_region==5'b10000)

            wbm_sel_o <= (4'b1111<<(spc2wbm_addr[2]<<2));
          else

            wbm_sel_o <= 8'b11111111;

        end else if(spc2wbm_type==     5'b00000) begin


          wbm_we_o <= 0;
          case(spc2wbm_size)
                3'b000  : wbm_sel_o <= (1'b1<<spc2wbm_addr[2:0]);
                3'b001  : wbm_sel_o <= (2'b11<<(spc2wbm_addr[2:1]<<1));
                3'b010  : wbm_sel_o <= (4'b1111<<(spc2wbm_addr[2]<<2));
                3'b011  : wbm_sel_o <= 8'b11111111;
               3'b111  : wbm_sel_o <= 8'b11111111;
            default: wbm_sel_o <= 8'b00000000;
          endcase

        end else if(spc2wbm_type==    5'b00001) begin


          wbm_we_o <= 1;
          case(spc2wbm_size)
                3'b000  : wbm_sel_o <= (1'b1<<spc2wbm_addr[2:0]);
                3'b001  : wbm_sel_o <= (2'b11<<(spc2wbm_addr[2:1]<<1));
                3'b010  : wbm_sel_o <= (4'b1111<<(spc2wbm_addr[2]<<2));
                3'b011  : wbm_sel_o <= 8'b11111111;
               3'b111  : wbm_sel_o <= 8'b11111111;
            default: wbm_sel_o <= 8'b00000000;
          endcase

        end else begin

          wbm_we_o <= 1;
          wbm_sel_o <= 8'b00000000;

        end



            
        $display("INFO: SPC2WBM: Valid bit is %X", spc2wbm_valid);
        case(spc2wbm_type)
               5'b00000: $display("INFO: SPC2WBM: Request of Type LOAD_RQ");
              5'b10000: $display("INFO: SPC2WBM: Request of Type IMISS_RQ");
              5'b00001: $display("INFO: SPC2WBM: Request of Type STORE_RQ");
               5'b00010: $display("INFO: SPC2WBM: Request of Type CAS1_RQ");
               5'b00011: $display("INFO: SPC2WBM: Request of Type CAS2_RQ");
               5'b00110: $display("INFO: SPC2WBM: Request of Type SWAP_RQ");
            5'b00100: $display("INFO: SPC2WBM: Request of Type STRLOAD_RQ");
              5'b00101: $display("INFO: SPC2WBM: Request of Type STRST_RQ");
                    5'b00111: $display("INFO: SPC2WBM: Request of Type STQ_RQ");
                    5'b01001: $display("INFO: SPC2WBM: Request of Type INT_RQ");
                    5'b01101: $display("INFO: SPC2WBM: Request of Type FWD_RQ");
                   5'b01110: $display("INFO: SPC2WBM: Request of Type FWD_RPY");
                   5'b11111: $display("INFO: SPC2WBM: Request of Type RSVD_RQ");
          default: $display("INFO: SPC2WBM: Request of Type Unknown");
    endcase
        $display("INFO: SPC2WBM: Non-Cacheable bit is %X", spc2wbm_nc);
        $display("INFO: SPC2WBM: CPU-ID is %X", spc2wbm_cpu_id);
        $display("INFO: SPC2WBM: Thread is %X", spc2wbm_thread);
        $display("INFO: SPC2WBM: Invalidate All is %X", spc2wbm_invalidate);
        $display("INFO: SPC2WBM: Replaced L1 Way is %X", spc2wbm_way);
        case(spc2wbm_size)
              3'b000  : $display("INFO: SPC2WBM: Request size is 1 Byte");
              3'b001  : $display("INFO: SPC2WBM: Request size is 2 Bytes");
              3'b010  : $display("INFO: SPC2WBM: Request size is 4 Bytes");
              3'b011  : $display("INFO: SPC2WBM: Request size is 8 Bytes");
             3'b111  : $display("INFO: SPC2WBM: Request size is 16 Bytes");
          default: $display("INFO: SPC2WBM: Request size is Unknown");
        endcase
        $display("INFO: SPC2WBM: Address is %X", spc2wbm_addr);
        $display("INFO: SPC2WBM: Data is %X", spc2wbm_data);
      



        state <=  4'b0100;



      end else if(state== 4'b0100) begin


        if(wbm_ack_i==1) begin


          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
          wbm_strobe_o <= 0;
          wbm_we_o <= 0;
          wbm_addr_o <= 64'b0;
          wbm_data_o <= 64'b0;
          wbm_sel_o <= 8'b0;


          wbm2spc_valid <= 1;
          case(spc2wbm_type)
                5'b10000: begin
              wbm2spc_type <=        4'b0001;
              wbm2spc_atomic <= 0;
            end
                 5'b00000: begin
              wbm2spc_type <=         4'b0000;
              wbm2spc_atomic <= spc2wbm_atomic;
            end
                5'b00001: begin
              wbm2spc_type <=           4'b0100;
              wbm2spc_atomic <= spc2wbm_atomic;
            end
          endcase
          wbm2spc_miss <= 0;
          wbm2spc_error <= 0;
          wbm2spc_nc <= spc2wbm_nc;
          wbm2spc_thread <= spc2wbm_thread;
          wbm2spc_way_valid <= 0;
          wbm2spc_way <= 0;
      if(spc2wbm_region==5'b10000) wbm2spc_boot_fetch <= 1;
      else wbm2spc_boot_fetch <= 0;
          wbm2spc_pfl <= 0;
          if(spc2wbm_addr[3]==0) wbm2spc_data <= { wbm_data_i, 64'b0 };
          else wbm2spc_data <= { 64'b0, wbm_data_i };


          if(

              ( (spc2wbm_type==    5'b10000)&&(spc2wbm_region!=5'b10000) ) ||

              ( (spc2wbm_type==     5'b00000)&&(spc2wbm_size==   3'b111  ) )
            )
            state <=    4'b0101;
          else
            state <=     4'b1011;

        end else state <=  4'b0100;



      end else if(state==   4'b0101) begin


        wbm_cycle_o <= 1;
        wbm_strobe_o <= 1;
        wbm_we_o <= 0;
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[       103  -        64:4], 4'b1000 };
        wbm_data_o <= 64'b0;
        wbm_sel_o <= 8'b11111111;


        state <=      4'b0110;



      end else if(state==     4'b0110) begin


        if(wbm_ack_i==1) begin


          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
          wbm_strobe_o <= 0;
          wbm_we_o <= 0;
          wbm_addr_o <= 64'b0;
          wbm_data_o <= 64'b0;
          wbm_sel_o <= 8'b0;


          wbm2spc_data[63:0] <= wbm_data_i;


          if(spc2wbm_type==    5'b10000 && spc2wbm_region==5'b10000)
            state <=     4'b1011;
          else
            state <=    4'b0111;

        end else state <=      4'b0110;




      end else if(state==   4'b0111) begin


        spc_ready_o <= 1;
        spc_packetin_o <= wbm2spc_packet;


        wbm_cycle_o <= 1;
        wbm_strobe_o <= 1;
        wbm_we_o <= 0;
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[       103  -        64:5], 5'b10000 };
        wbm_data_o <= 64'b0;
        wbm_sel_o <= 8'b11111111;



            
        $display("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***");
        $display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
        case(wbm2spc_type)
                 4'b0001: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
                  4'b0000: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
                    4'b0100: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
          default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
        endcase
        $display("INFO: WBM2SPC: L2 Miss is %X", wbm2spc_miss);
        $display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
        $display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
        $display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
        $display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
        $display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
        $display("INFO: WBM2SPC: Fetch for Boot is %X", wbm2spc_boot_fetch);
        $display("INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is %X", wbm2spc_atomic);
        $display("INFO: WBM2SPC: PFL is %X", wbm2spc_pfl);
        $display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
      



        state <=      4'b1000;



      end else if(state==     4'b1000) begin


        spc_ready_o <= 0;


        if(wbm_ack_i==1) begin


          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
          wbm_strobe_o <= 0;
          wbm_we_o <= 0;
          wbm_addr_o <= 64'b0;
          wbm_data_o <= 64'b0;
          wbm_sel_o <= 8'b0;


          wbm2spc_data <= { wbm_data_i, 64'b0 };


          state <=    4'b1001;

        end else state <=      4'b1000;



      end else if(state==   4'b1001) begin


        wbm_cycle_o <= 1;
        wbm_strobe_o <= 1;
        wbm_we_o <= 0;
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[       103  -        64:5], 5'b11000 };
        wbm_data_o <= 64'b0;
        wbm_sel_o <= 8'b11111111;


        state <=      4'b1010;



      end else if(state==     4'b1010) begin


        if(wbm_ack_i==1) begin


          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
          wbm_strobe_o <= 0;
          wbm_we_o <= 0;
          wbm_addr_o <= 64'b0;
          wbm_data_o <= 64'b0;
          wbm_sel_o <= 8'b0;


          wbm2spc_atomic <= 1;
          wbm2spc_data[63:0] <= wbm_data_i;


          state <=     4'b1011;

        end else state <=      4'b1010;



      end else if(state==    4'b1011) begin


        spc_ready_o <= 1;
        spc_packetin_o <= wbm2spc_packet;


        spc_resume_o <= 1;


        state <=             4'b0001;



            
        $display("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***");
        $display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
        case(wbm2spc_type)
                 4'b0001: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
                  4'b0000: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
                    4'b0100: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
          default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
        endcase
        $display("INFO: WBM2SPC: L2 Miss is %X", wbm2spc_miss);
        $display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
        $display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
        $display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
        $display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
        $display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
        $display("INFO: WBM2SPC: Fetch for Boot is %X", wbm2spc_boot_fetch);
        $display("INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is %X", wbm2spc_atomic);
        $display("INFO: WBM2SPC: PFL is %X", wbm2spc_pfl);
        $display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
      


      end
    end
  end

endmodule
module spc2wbm (




    input sys_clock_i,
    input sys_reset_i,
    input[5:0] sys_interrupt_source_i,


    input[4:0] spc_req_i,
    input spc_atom_i,
    input[(   124  -1):0] spc_packetout_i,


    input wbm_ack_i,
    input[( 64-1):0] wbm_data_i,




    output reg[4:0] spc_grant_o,
    output reg spc_ready_o,
    output reg[   145  -1:0] spc_packetin_o,
    output reg spc_stall_o,
    output reg spc_resume_o,


    output reg wbm_cycle_o,
    output reg wbm_strobe_o,
    output reg wbm_we_o,
    output reg[ 64-1:0] wbm_addr_o,
    output reg[ 64-1:0] wbm_data_o,
    output reg[ 64/8-1:0] wbm_sel_o

  );






  reg[3:0] state;
  reg[4:0] spc2wbm_region;
  reg spc2wbm_atomic;
  reg[(   124  -1):0] spc2wbm_packet;


  reg wbm2spc_valid;
  reg[(       143  -       140):0] wbm2spc_type;
  reg wbm2spc_miss;
  reg[(      139  -      137-1):0] wbm2spc_error;
  reg wbm2spc_nc;
  reg[(       135  -       134):0] wbm2spc_thread;
  reg wbm2spc_way_valid;
  reg[(       132  -       131):0] wbm2spc_way;
  reg wbm2spc_boot_fetch;
  reg wbm2spc_atomic;
  reg wbm2spc_pfl;
  reg[(       127  -         0):0] wbm2spc_data;
  reg[6:0] wbm2spc_interrupt_source;
  reg wbm2spc_interrupt_new;




  wire spc2wbm_req;
  wire spc2wbm_valid;
  wire[(       122  -       118):0] spc2wbm_type;
  wire spc2wbm_nc;
  wire[(       116  -       114):0] spc2wbm_cpu_id;
  wire[(       113  -       112):0] spc2wbm_thread;
  wire spc2wbm_invalidate;
  wire[(       108  -       107):0] spc2wbm_way;
  wire[(       106  -       104):0] spc2wbm_size;
  wire[(       103  -        64):0] spc2wbm_addr;
  wire[(        63  -         0):0] spc2wbm_data;


  wire[   145  -1:0] wbm2spc_packet;




  assign spc2wbm_req = ( spc_req_i[4] | spc_req_i[3] | spc_req_i[2] | spc_req_i[1] | spc_req_i[0] );
  assign spc2wbm_valid = spc2wbm_packet[         123  ];
  assign spc2wbm_type = spc2wbm_packet[       122  :       118];
  assign spc2wbm_nc = spc2wbm_packet[          117  ];
  assign spc2wbm_cpu_id = spc2wbm_packet[       116  :       114];
  assign spc2wbm_thread = spc2wbm_packet[       113  :       112];
  assign spc2wbm_invalidate = spc2wbm_packet[      111];
  assign spc2wbm_way = spc2wbm_packet[       108  :       107];
  assign spc2wbm_size = spc2wbm_packet[       106  :       104];
  assign spc2wbm_addr = spc2wbm_packet[       103  :        64];
  assign spc2wbm_data = spc2wbm_packet[        63  :         0];


  assign wbm2spc_packet = { wbm2spc_valid, wbm2spc_type, wbm2spc_miss, wbm2spc_error, wbm2spc_nc, wbm2spc_thread,
    wbm2spc_way_valid, wbm2spc_way, wbm2spc_boot_fetch, wbm2spc_atomic, wbm2spc_pfl, wbm2spc_data };



  always @(posedge sys_clock_i) begin


    if(sys_reset_i==1) begin


      spc_grant_o <= 5'b00000;
      spc_ready_o <= 0;
      spc_packetin_o <= 0;
      spc_stall_o <= 0;
      spc_resume_o <= 0;


      wbm_cycle_o <= 0;
      wbm_strobe_o <= 0;
      wbm_we_o <= 0;
      wbm_addr_o <= 64'b0;
      wbm_data_o <= 64'b0;
      wbm_sel_o <= 8'b0;



      wbm2spc_valid <= 1;
      wbm2spc_type <=          4'b0111;
      wbm2spc_miss <= 0;
      wbm2spc_error <= 0;
      wbm2spc_nc <= 0;
      wbm2spc_thread <= 0;
      wbm2spc_way_valid <= 0;
      wbm2spc_way <= 0;
      wbm2spc_boot_fetch <= 0;
      wbm2spc_atomic <= 0;
      wbm2spc_pfl <= 0;
      wbm2spc_data <= 64'h10001;
      wbm2spc_interrupt_source <= 7'h0;
      wbm2spc_interrupt_new <= 1'b0;


      state <=           4'b0000;

    end else begin



      if(state==          4'b0000) begin


        spc_ready_o <= 1;
        spc_packetin_o <= wbm2spc_packet;



            
        $display("INFO: SPC2WBM: SPARC Core to Wishbone Master bridge starting...");
        $display("INFO: SPC2WBM: Wakeup packet sent to SPARC Core");
      



        state <=             4'b0001;




      end else if(state==            4'b0001) begin


        if(spc2wbm_req==1) begin


          spc_ready_o <= 0;
          spc_packetin_o <= 0;


          spc_stall_o <= 1;


          spc2wbm_region <= spc_req_i;
          spc2wbm_atomic <= spc_atom_i;


          state <=  4'b0010;


        end else if(sys_interrupt_source_i!=wbm2spc_interrupt_source) begin


          wbm2spc_interrupt_new <= 1;


          wbm2spc_valid <= 1;
          wbm2spc_type <=          4'b0111;
          wbm2spc_miss <= 0;
          wbm2spc_error <= 0;
          wbm2spc_nc <= 0;
          wbm2spc_thread <= 0;
          wbm2spc_way_valid <= 0;
          wbm2spc_way <= 0;
          wbm2spc_boot_fetch <= 0;
          wbm2spc_atomic <= 0;
          wbm2spc_pfl <= 0;


        end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_interrupt_new) begin


          wbm2spc_interrupt_new <= 0;


          spc_ready_o <= 1;
          spc_packetin_o <= wbm2spc_packet;


          state <=             4'b0001;


        end else begin


          spc_ready_o <= 0;
          spc_packetin_o <= 0;


          spc_stall_o <= 0;
      spc_resume_o <= 0;


          state <=             4'b0001;

        end





      end else if(state== 4'b0010) begin


        spc2wbm_packet <= spc_packetout_i;


        spc_grant_o <= spc2wbm_region;


        spc_stall_o <= 0;



            
        $display("INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE ***");
        if(spc2wbm_region[0]==1) $display("INFO: SPC2WBM: Request to RAM Bank 0");
        else if(spc2wbm_region[1]==1) $display("INFO: SPC2WBM: Request to RAM Bank 1");
        else if(spc2wbm_region[2]==1) $display("INFO: SPC2WBM: Request to RAM Bank 2");
        else if(spc2wbm_region[3]==1) $display("INFO: SPC2WBM: Request to RAM Bank 3");
        else if(spc2wbm_region[4]==1) $display("INFO: SPC2WBM: Request targeted to I/O Block");
        else $display("INFO: SPC2WBM: Request to target region unknown");
        if(spc2wbm_atomic==1) $display("INFO: SPC2WBM: Request is ATOMIC");
        else $display("INFO: SPC2WBM: Request is not atomic");
      



        state <=   4'b0011;





      end else if(state==  4'b0011) begin


        spc_grant_o <= 5'b0;


        wbm_cycle_o <= 1;
        wbm_strobe_o <= 1;
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[       103  -        64:3], 3'b000 };
        wbm_data_o <= spc2wbm_data;


        if(spc2wbm_type==    5'b10000) begin


          wbm_we_o <= 0;
          if(spc2wbm_region==5'b10000)

            wbm_sel_o <= (4'b1111<<(spc2wbm_addr[2]<<2));
          else

            wbm_sel_o <= 8'b11111111;

        end else if(spc2wbm_type==     5'b00000) begin


          wbm_we_o <= 0;
          case(spc2wbm_size)
                3'b000  : wbm_sel_o <= (1'b1<<spc2wbm_addr[2:0]);
                3'b001  : wbm_sel_o <= (2'b11<<(spc2wbm_addr[2:1]<<1));
                3'b010  : wbm_sel_o <= (4'b1111<<(spc2wbm_addr[2]<<2));
                3'b011  : wbm_sel_o <= 8'b11111111;
               3'b111  : wbm_sel_o <= 8'b11111111;
            default: wbm_sel_o <= 8'b00000000;
          endcase

        end else if(spc2wbm_type==    5'b00001) begin


          wbm_we_o <= 1;
          case(spc2wbm_size)
                3'b000  : wbm_sel_o <= (1'b1<<spc2wbm_addr[2:0]);
                3'b001  : wbm_sel_o <= (2'b11<<(spc2wbm_addr[2:1]<<1));
                3'b010  : wbm_sel_o <= (4'b1111<<(spc2wbm_addr[2]<<2));
                3'b011  : wbm_sel_o <= 8'b11111111;
               3'b111  : wbm_sel_o <= 8'b11111111;
            default: wbm_sel_o <= 8'b00000000;
          endcase

        end else begin

          wbm_we_o <= 1;
          wbm_sel_o <= 8'b00000000;

        end



            
        $display("INFO: SPC2WBM: Valid bit is %X", spc2wbm_valid);
        case(spc2wbm_type)
               5'b00000: $display("INFO: SPC2WBM: Request of Type LOAD_RQ");
              5'b10000: $display("INFO: SPC2WBM: Request of Type IMISS_RQ");
              5'b00001: $display("INFO: SPC2WBM: Request of Type STORE_RQ");
               5'b00010: $display("INFO: SPC2WBM: Request of Type CAS1_RQ");
               5'b00011: $display("INFO: SPC2WBM: Request of Type CAS2_RQ");
               5'b00110: $display("INFO: SPC2WBM: Request of Type SWAP_RQ");
            5'b00100: $display("INFO: SPC2WBM: Request of Type STRLOAD_RQ");
              5'b00101: $display("INFO: SPC2WBM: Request of Type STRST_RQ");
                    5'b00111: $display("INFO: SPC2WBM: Request of Type STQ_RQ");
                    5'b01001: $display("INFO: SPC2WBM: Request of Type INT_RQ");
                    5'b01101: $display("INFO: SPC2WBM: Request of Type FWD_RQ");
                   5'b01110: $display("INFO: SPC2WBM: Request of Type FWD_RPY");
                   5'b11111: $display("INFO: SPC2WBM: Request of Type RSVD_RQ");
          default: $display("INFO: SPC2WBM: Request of Type Unknown");
    endcase
        $display("INFO: SPC2WBM: Non-Cacheable bit is %X", spc2wbm_nc);
        $display("INFO: SPC2WBM: CPU-ID is %X", spc2wbm_cpu_id);
        $display("INFO: SPC2WBM: Thread is %X", spc2wbm_thread);
        $display("INFO: SPC2WBM: Invalidate All is %X", spc2wbm_invalidate);
        $display("INFO: SPC2WBM: Replaced L1 Way is %X", spc2wbm_way);
        case(spc2wbm_size)
              3'b000  : $display("INFO: SPC2WBM: Request size is 1 Byte");
              3'b001  : $display("INFO: SPC2WBM: Request size is 2 Bytes");
              3'b010  : $display("INFO: SPC2WBM: Request size is 4 Bytes");
              3'b011  : $display("INFO: SPC2WBM: Request size is 8 Bytes");
             3'b111  : $display("INFO: SPC2WBM: Request size is 16 Bytes");
          default: $display("INFO: SPC2WBM: Request size is Unknown");
        endcase
        $display("INFO: SPC2WBM: Address is %X", spc2wbm_addr);
        $display("INFO: SPC2WBM: Data is %X", spc2wbm_data);
      



        state <=  4'b0100;



      end else if(state== 4'b0100) begin


        if(wbm_ack_i==1) begin


          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
          wbm_strobe_o <= 0;
          wbm_we_o <= 0;
          wbm_addr_o <= 64'b0;
          wbm_data_o <= 64'b0;
          wbm_sel_o <= 8'b0;


          wbm2spc_valid <= 1;
          case(spc2wbm_type)
                5'b10000: begin
              wbm2spc_type <=        4'b0001;
              wbm2spc_atomic <= 0;
            end
                 5'b00000: begin
              wbm2spc_type <=         4'b0000;
              wbm2spc_atomic <= spc2wbm_atomic;
            end
                5'b00001: begin
              wbm2spc_type <=           4'b0100;
              wbm2spc_atomic <= spc2wbm_atomic;
            end
          endcase
          wbm2spc_miss <= 0;
          wbm2spc_error <= 0;
          wbm2spc_nc <= spc2wbm_nc;
          wbm2spc_thread <= spc2wbm_thread;
          wbm2spc_way_valid <= 0;
          wbm2spc_way <= 0;
      if(spc2wbm_region==5'b10000) wbm2spc_boot_fetch <= 1;
      else wbm2spc_boot_fetch <= 0;
          wbm2spc_pfl <= 0;
          if(spc2wbm_addr[3]==0) wbm2spc_data <= { wbm_data_i, 64'b0 };
          else wbm2spc_data <= { 64'b0, wbm_data_i };


          if(

              ( (spc2wbm_type==    5'b10000)&&(spc2wbm_region!=5'b10000) ) ||

              ( (spc2wbm_type==     5'b00000)&&(spc2wbm_size==   3'b111  ) )
            )
            state <=    4'b0101;
          else
            state <=     4'b1011;

        end else state <=  4'b0100;



      end else if(state==   4'b0101) begin


        wbm_cycle_o <= 1;
        wbm_strobe_o <= 1;
        wbm_we_o <= 0;
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[       103  -        64:4], 4'b1000 };
        wbm_data_o <= 64'b0;
        wbm_sel_o <= 8'b11111111;


        state <=      4'b0110;



      end else if(state==     4'b0110) begin


        if(wbm_ack_i==1) begin


          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
          wbm_strobe_o <= 0;
          wbm_we_o <= 0;
          wbm_addr_o <= 64'b0;
          wbm_data_o <= 64'b0;
          wbm_sel_o <= 8'b0;


          wbm2spc_data[63:0] <= wbm_data_i;


          if(spc2wbm_type==    5'b10000 && spc2wbm_region==5'b10000)
            state <=     4'b1011;
          else
            state <=    4'b0111;

        end else state <=      4'b0110;




      end else if(state==   4'b0111) begin


        spc_ready_o <= 1;
        spc_packetin_o <= wbm2spc_packet;


        wbm_cycle_o <= 1;
        wbm_strobe_o <= 1;
        wbm_we_o <= 0;
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[       103  -        64:5], 5'b10000 };
        wbm_data_o <= 64'b0;
        wbm_sel_o <= 8'b11111111;



            
        $display("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***");
        $display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
        case(wbm2spc_type)
                 4'b0001: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
                  4'b0000: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
                    4'b0100: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
          default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
        endcase
        $display("INFO: WBM2SPC: L2 Miss is %X", wbm2spc_miss);
        $display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
        $display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
        $display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
        $display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
        $display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
        $display("INFO: WBM2SPC: Fetch for Boot is %X", wbm2spc_boot_fetch);
        $display("INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is %X", wbm2spc_atomic);
        $display("INFO: WBM2SPC: PFL is %X", wbm2spc_pfl);
        $display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
      



        state <=      4'b1000;



      end else if(state==     4'b1000) begin


        spc_ready_o <= 0;


        if(wbm_ack_i==1) begin


          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
          wbm_strobe_o <= 0;
          wbm_we_o <= 0;
          wbm_addr_o <= 64'b0;
          wbm_data_o <= 64'b0;
          wbm_sel_o <= 8'b0;


          wbm2spc_data <= { wbm_data_i, 64'b0 };


          state <=    4'b1001;

        end else state <=      4'b1000;



      end else if(state==   4'b1001) begin


        wbm_cycle_o <= 1;
        wbm_strobe_o <= 1;
        wbm_we_o <= 0;
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[       103  -        64:5], 5'b11000 };
        wbm_data_o <= 64'b0;
        wbm_sel_o <= 8'b11111111;


        state <=      4'b1010;



      end else if(state==     4'b1010) begin


        if(wbm_ack_i==1) begin


          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
          wbm_strobe_o <= 0;
          wbm_we_o <= 0;
          wbm_addr_o <= 64'b0;
          wbm_data_o <= 64'b0;
          wbm_sel_o <= 8'b0;


          wbm2spc_atomic <= 1;
          wbm2spc_data[63:0] <= wbm_data_i;


          state <=     4'b1011;

        end else state <=      4'b1010;



      end else if(state==    4'b1011) begin


        spc_ready_o <= 1;
        spc_packetin_o <= wbm2spc_packet;


        spc_resume_o <= 1;


        state <=             4'b0001;



            
        $display("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***");
        $display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
        case(wbm2spc_type)
                 4'b0001: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
                  4'b0000: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
                    4'b0100: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
          default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
        endcase
        $display("INFO: WBM2SPC: L2 Miss is %X", wbm2spc_miss);
        $display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
        $display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
        $display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
        $display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
        $display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
        $display("INFO: WBM2SPC: Fetch for Boot is %X", wbm2spc_boot_fetch);
        $display("INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is %X", wbm2spc_atomic);
        $display("INFO: WBM2SPC: PFL is %X", wbm2spc_pfl);
        $display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
      


      end
    end
  end

endmodule