data/full_repos/permissive/109936328/pipeline/id.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/pipeline/id.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:2: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:70: Define or directive not defined: \'`ADDR_W\'\n  input [`ADDR_W - 1:0] i_pc;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:71: Define or directive not defined: \'`INSTR_W\'\n  input [`INSTR_W - 1:0] i_instr;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:73: Define or directive not defined: \'`INSTR_W\'\n  wire [`INSTR_W - 1:0] s_instr;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:75: Define or directive not defined: \'`REG_IDX_W\'\n  input [`REG_IDX_W - 1:0] i_ex_dest_reg;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:76: Define or directive not defined: \'`DEST_SRC_W\'\n  input [`DEST_SRC_W - 1:0] i_ex_dest_src;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:77: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_ex_alu_eval;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:79: Define or directive not defined: \'`REG_IDX_W\'\n  input [`REG_IDX_W - 1:0] i_me_dest_reg;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:80: Define or directive not defined: \'`DEST_SRC_W\'\n  input [`DEST_SRC_W - 1:0] i_me_dest_src;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:81: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_me_dest_data;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:85: Define or directive not defined: \'`REG_IDX_W\'\n  input [`REG_IDX_W - 1:0] i_wb_dest_reg;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:86: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_wb_dest_data;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:89: Define or directive not defined: \'`ADDR_W\'\n  output [`ADDR_W - 1:0] o_pc;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:90: Define or directive not defined: \'`INSTR_W\'\n  output [`INSTR_W - 1:0] o_instr;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:93: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] r_pc;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:94: Define or directive not defined: \'`INSTR_W\'\n  reg [`INSTR_W - 1:0] r_instr;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:97: Define or directive not defined: \'`ALU_OP_W\'\n  output [`ALU_OP_W - 1:0] o_alu_op;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:100: Define or directive not defined: \'`WORD_W\'\n  output reg[`WORD_W - 1:0] o_alu_data_a;\n             ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:101: Define or directive not defined: \'`WORD_W\'\n  output reg[`WORD_W - 1:0] o_alu_data_b;\n             ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:103: Define or directive not defined: \'`WORD_W\'\n  output [`WORD_W - 1:0] o_imm;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:105: Define or directive not defined: \'`MEM_OP_W\'\n  output [`MEM_OP_W - 1:0] o_mem_op;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:110: Define or directive not defined: \'`DEST_SRC_W\'\n  output [`DEST_SRC_W - 1:0] o_dest_src;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:111: Define or directive not defined: \'`REG_IDX_W\'\n  output [`REG_IDX_W - 1:0] o_dest_reg;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:112: Define or directive not defined: \'`INSTR_XPR_DEST\'\n  assign o_dest_reg = `INSTR_XPR_DEST(s_instr);\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:117: Define or directive not defined: \'`ALU_SRC_A_W\'\n  wire [`ALU_SRC_A_W - 1:0] s_alu_src_a;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:118: Define or directive not defined: \'`ALU_SRC_B_W\'\n  wire [`ALU_SRC_B_W - 1:0] s_alu_src_b;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:120: Define or directive not defined: \'`MEM_OP_W\'\n  wire [`MEM_OP_W - 1:0] s_mem_op;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:121: Define or directive not defined: \'`DEST_SRC_W\'\n  wire [`DEST_SRC_W - 1:0] s_dest_src;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:125: Define or directive not defined: \'`REG_IDX_W\'\n  wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:125: Define or directive not defined: \'`INSTR_XPR_A\'\n  wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);\n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:126: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] s_reg_data_a;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:127: Define or directive not defined: \'`REG_IDX_W\'\n  wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:127: Define or directive not defined: \'`INSTR_XPR_B\'\n  wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);\n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:128: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] s_reg_data_b;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:133: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] r_temp_pc;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:134: Define or directive not defined: \'`INSTR_W\'\n  reg [`INSTR_W - 1:0] r_temp_instr;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:166: Define or directive not defined: \'`MEM_OP_NOP\'\n  assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:166: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;\n                                        ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:167: Define or directive not defined: \'`DEST_SRC_NONE\'\n  assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;\n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:167: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;\n                                             ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:212: Define or directive not defined: \'`WORD_W\'\n  function [`WORD_W - 1:0] fwd_alu_data;\n            ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:213: Define or directive not defined: \'`REG_IDX_W\'\n    input [`REG_IDX_W - 1:0] reg_num;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:214: Define or directive not defined: \'`WORD_W\'\n    input [`WORD_W - 1:0] reg_data;\n           ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:217: Define or directive not defined: \'`DEST_SRC_ALU\'\n      i_ex_dest_src == `DEST_SRC_ALU) begin\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:217: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      i_ex_dest_src == `DEST_SRC_ALU) begin\n                                    ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:221: Define or directive not defined: \'`DEST_SRC_NONE\'\n      i_me_dest_src != `DEST_SRC_NONE) begin\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:236: Define or directive not defined: \'`REG_IDX_W\'\n    input [`REG_IDX_W - 1:0] reg_num;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:239: Define or directive not defined: \'`DEST_SRC_MEM\'\n      i_ex_dest_src == `DEST_SRC_MEM) begin\n                       ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
function [`WORD_W - 1:0] fwd_alu_data;
    input [`REG_IDX_W - 1:0] reg_num;
    input [`WORD_W - 1:0] reg_data;
  begin
    if(reg_num != 0 && reg_num == i_ex_dest_reg &&
      i_ex_dest_src == `DEST_SRC_ALU) begin

      fwd_alu_data = i_ex_alu_eval;
    end else if(reg_num != 0 && reg_num == i_me_dest_reg &&
      i_me_dest_src != `DEST_SRC_NONE) begin

      fwd_alu_data = i_me_dest_data;
    end else if(reg_num != 0 && reg_num == i_wb_dest_reg &&
      i_wb_dest_en == 1) begin

      fwd_alu_data = i_wb_dest_data;
    end else begin
      fwd_alu_data = reg_data;
    end
  end
  endfunction
function [`WORD_W - 1:0] fwd_alu_data;

    input [`REG_IDX_W - 1:0] reg_num;
    input [`WORD_W - 1:0] reg_data;
  begin
    if(reg_num != 0 && reg_num == i_ex_dest_reg &&
      i_ex_dest_src == `DEST_SRC_ALU) begin

      fwd_alu_data = i_ex_alu_eval;
    end else if(reg_num != 0 && reg_num == i_me_dest_reg &&
      i_me_dest_src != `DEST_SRC_NONE) begin

      fwd_alu_data = i_me_dest_data;
    end else if(reg_num != 0 && reg_num == i_wb_dest_reg &&
      i_wb_dest_en == 1) begin

      fwd_alu_data = i_wb_dest_data;
    end else begin
      fwd_alu_data = reg_data;
    end
  end
  endfunction