data/full_repos/permissive/123528630/test/test_clk_div.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123528630/test/test_clk_div.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #4 reset<=1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123528630/test/test_clk_div.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #7 reset<=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123528630/test/test_clk_div.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #200 div=4\'b1001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123528630/test/test_clk_div.v:48: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk=!clk;\n           ^\n%Error: data/full_repos/permissive/123528630/test/test_clk_div.v:28: Cannot find file containing module: \'clock_divider\'\n    clock_divider uut0\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123528630/test,data/full_repos/permissive/123528630/clock_divider\n             data/full_repos/permissive/123528630/test,data/full_repos/permissive/123528630/clock_divider.v\n             data/full_repos/permissive/123528630/test,data/full_repos/permissive/123528630/clock_divider.sv\n             clock_divider\n             clock_divider.v\n             clock_divider.sv\n             obj_dir/clock_divider\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_clk_div;
    reg clk;
    reg reset;
    reg [3:0]div;
    wire o_clk;
    clock_divider uut0
    (
        .clk_i (clk),
        .clk_o (o_clk),
        .div (div),
        .rst (reset)
    );
    initial 
    begin
        clk=0;
        reset=0;
        div=4'b0011;
        #4 reset<=1'b1;
        #7 reset<=1'b0;
        
        #200 div=4'b1001;
    end

    
    
    always #5 clk=!clk;
    
endmodule
module test_clk_div;

    reg clk;
    reg reset;
    reg [3:0]div;
    wire o_clk;
    clock_divider uut0
    (
        .clk_i (clk),
        .clk_o (o_clk),
        .div (div),
        .rst (reset)
    );
    initial 
    begin
        clk=0;
        reset=0;
        div=4'b0011;
        #4 reset<=1'b1;
        #7 reset<=1'b0;
        
        #200 div=4'b1001;
    end

    
    
    always #5 clk=!clk;
    
endmodule