data/full_repos/permissive/196412397/register_rd_wr_tb.v
1: b'%Error: data/full_repos/permissive/196412397/register_rd_wr_tb.v:11: Cannot find include file: clock_enable_param.v\n`include "clock_enable_param.v"  \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/clock_enable_param.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/clock_enable_param.v.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/clock_enable_param.v.sv\n             clock_enable_param.v\n             clock_enable_param.v.v\n             clock_enable_param.v.sv\n             obj_dir/clock_enable_param.v\n             obj_dir/clock_enable_param.v.v\n             obj_dir/clock_enable_param.v.sv\n%Error: data/full_repos/permissive/196412397/register_rd_wr_tb.v:13: Cannot find include file: default_reg_writer.v\n`include "default_reg_writer.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/196412397/register_rd_wr_tb.v:14: Cannot find include file: blockram.v\n`include "blockram.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/196412397/register_rd_wr_tb.v:15: Cannot find include file: reg_reader.v\n`include "reg_reader.v" \n         ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/196412397/register_rd_wr_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/196412397/register_rd_wr_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n    #0_500; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/register_rd_wr_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #0_020;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/register_rd_wr_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n    #3_500; \n    ^\n%Error: data/full_repos/permissive/196412397/register_rd_wr_tb.v:121: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/196412397/register_rd_wr_tb.v:122: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0);\n    ^~~~~~~~~\n%Error: Exiting due to 6 error(s), 4 warning(s)\n'
module register_rd_wr_tb #(parameter
    CAM_LINE        = 9,
    CAM_PIXEL       = 10,
    DEPTH =  88,
    ADDR_WIDTH = 7, 
    DATA_WIDTH = 25 
  )();



reg clk = 1'b0;
wire w_enable;
reg reset = 0;

wire [24:0]             w_data_reg;
wire [6:0]              w_addr_rd_reg;
wire                    w_config_default ;
wire [6:0]              w_addr_default ;
wire [24:0]             w_data_default ;
wire                    w_we_default ;



always #0.5 clk <= ~clk;


default_reg_writer #(
    .CAM_LINE(CAM_LINE),
    .CAM_PIXEL(CAM_PIXEL)
) default_reg_writer1(
    .clk(clk),
    .i_enable(w_enable),
    .i_reset(reset),
    .o_configured(w_config_default),
    .o_addr(w_addr_default),
    .o_data(w_data_default) ,
    .o_we(w_we_default) 
);

reg_reader #(
    .CAM_LINE(CAM_LINE),
    .CAM_PIXEL(CAM_PIXEL)
) reg_reader1 (
    .clk(clk),
    .i_enable(w_enable),
    .i_cam0_mode(2'b00),
    .i_cam1_mode(2'b00),
    .i_data(w_data_reg),
    .o_addr_rd(w_addr_rd_reg)
);

rams_tdp_rf_rf #( 
    .DEPTH(DEPTH),             
    .ADDR_WIDTH(ADDR_WIDTH),         
    .DATA_WIDTH(DATA_WIDTH)
    ) 
bram_reg(

    .clka(  clk),
    .ena(1'b1),
    .wea(  ),
    .addra(w_addr_rd_reg),
    .dia(  ),
    .doa(w_data_reg),


    .clkb(  clk),
    .addrb( w_config_default ? w_addr_default : w_addr_default ),
    .enb(   w_enable),
    .web(   w_config_default ? w_we_default : w_we_default),
    .dib(   w_config_default ? w_data_default : w_data_default),
    .dob()
    );


clock_enable_param #(


  ) clock_enable1 (
    .clk(clk),
    .enable(w_enable)
);

initial 
  begin 
    #0_500; 
    $display("*");
    reset = 1;
    #0_020;
    reset = 0;
    #3_500; 

    $display(" ");
    $display("Use this command to open timing diagram:");
    $display("gtkwave -f wave.vcd");
    $display("----------------------------------------------");
    $finish();
end

initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
end

endmodule
module register_rd_wr_tb #(parameter
    CAM_LINE        = 9,
    CAM_PIXEL       = 10,
    DEPTH =  88,
    ADDR_WIDTH = 7, 
    DATA_WIDTH = 25 
  )();




reg clk = 1'b0;
wire w_enable;
reg reset = 0;

wire [24:0]             w_data_reg;
wire [6:0]              w_addr_rd_reg;
wire                    w_config_default ;
wire [6:0]              w_addr_default ;
wire [24:0]             w_data_default ;
wire                    w_we_default ;



always #0.5 clk <= ~clk;


default_reg_writer #(
    .CAM_LINE(CAM_LINE),
    .CAM_PIXEL(CAM_PIXEL)
) default_reg_writer1(
    .clk(clk),
    .i_enable(w_enable),
    .i_reset(reset),
    .o_configured(w_config_default),
    .o_addr(w_addr_default),
    .o_data(w_data_default) ,
    .o_we(w_we_default) 
);

reg_reader #(
    .CAM_LINE(CAM_LINE),
    .CAM_PIXEL(CAM_PIXEL)
) reg_reader1 (
    .clk(clk),
    .i_enable(w_enable),
    .i_cam0_mode(2'b00),
    .i_cam1_mode(2'b00),
    .i_data(w_data_reg),
    .o_addr_rd(w_addr_rd_reg)
);

rams_tdp_rf_rf #( 
    .DEPTH(DEPTH),             
    .ADDR_WIDTH(ADDR_WIDTH),         
    .DATA_WIDTH(DATA_WIDTH)
    ) 
bram_reg(

    .clka(  clk),
    .ena(1'b1),
    .wea(  ),
    .addra(w_addr_rd_reg),
    .dia(  ),
    .doa(w_data_reg),


    .clkb(  clk),
    .addrb( w_config_default ? w_addr_default : w_addr_default ),
    .enb(   w_enable),
    .web(   w_config_default ? w_we_default : w_we_default),
    .dib(   w_config_default ? w_data_default : w_data_default),
    .dob()
    );


clock_enable_param #(


  ) clock_enable1 (
    .clk(clk),
    .enable(w_enable)
);

initial 
  begin 
    #0_500; 
    $display("*");
    reset = 1;
    #0_020;
    reset = 0;
    #3_500; 

    $display(" ");
    $display("Use this command to open timing diagram:");
    $display("gtkwave -f wave.vcd");
    $display("----------------------------------------------");
    $finish();
end

initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
end

endmodule