data/full_repos/permissive/119715647/sim/BlockRandomizer/blockRandomizer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/119715647/sim/BlockRandomizer/blockRandomizer.v:14: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                                             : ... In instance blockRandomizer\n      outputBlock = {outputBlock[7:0], feedback};\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module blockRandomizer (clk, rst, outputBlock);
  output reg [7:0] outputBlock;
  input clk, rst;

  wire feedback;

  assign feedback = ~(outputBlock[7] ^ outputBlock[3]);

  always @ (posedge clk) begin
    if (rst == 0) begin
      outputBlock = 8'b0;
    end
    else begin
      outputBlock = {outputBlock[7:0], feedback};
    end
  end
endmodule
module blockRandomizer (clk, rst, outputBlock);

  output reg [7:0] outputBlock;
  input clk, rst;

  wire feedback;

  assign feedback = ~(outputBlock[7] ^ outputBlock[3]);

  always @ (posedge clk) begin
    if (rst == 0) begin
      outputBlock = 8'b0;
    end
    else begin
      outputBlock = {outputBlock[7:0], feedback};
    end
  end
endmodule