data/full_repos/permissive/126366342/verilog modules/round.v
1: b'%Error: Cannot find file containing module: modules,data/full_repos/permissive/126366342\n        ... Looked in:\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342.v\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342.sv\n             modules,data/full_repos/permissive/126366342\n             modules,data/full_repos/permissive/126366342.v\n             modules,data/full_repos/permissive/126366342.sv\n             obj_dir/modules,data/full_repos/permissive/126366342\n             obj_dir/modules,data/full_repos/permissive/126366342.v\n             obj_dir/modules,data/full_repos/permissive/126366342.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/126366342/verilog\n%Error: Cannot find file containing module: modules/round.v\n%Error: Exiting due to 3 error(s)\n'
module round(input [1:32] leftHalf, input [1:32] rightHalf, input [1:48] round_key,output [1:32]new_left,output [1:32] new_right
    );

wire [1:32] f_block1;

F_block f1(.key(round_key),.half_block(rightHalf),.f_block_output(f_block1));

assign new_left = leftHalf ^ f_block1;
assign new_right = rightHalf;
	 

endmodule
module round(input [1:32] leftHalf, input [1:32] rightHalf, input [1:48] round_key,output [1:32]new_left,output [1:32] new_right
    );


wire [1:32] f_block1;

F_block f1(.key(round_key),.half_block(rightHalf),.f_block_output(f_block1));

assign new_left = leftHalf ^ f_block1;
assign new_right = rightHalf;
	 

endmodule