data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/flopenrc.v
data/verilator_xmls/7f9a7875-c92f-4455-9aea-ab126bb1b3f6.xml
module flopenrc #(parameter WIDTH=8)
    (
    input clk,reset,en,clear,
    input [WIDTH-1:0] d,
    output reg [WIDTH-1:0] q
    );
    
    always@(posedge clk,posedge reset)
    if(reset)
        q<= #1 0;
    else
        if(~en)
            q<= #1 q;
        else
            if(clear)
                q<= #1 0;
            else
                q<= #1 d;
    
endmodule
module flopenrc #(parameter WIDTH=8)
    (
    input clk,reset,en,clear,
    input [WIDTH-1:0] d,
    output reg [WIDTH-1:0] q
    );

    
    always@(posedge clk,posedge reset)
    if(reset)
        q<= #1 0;
    else
        if(~en)
            q<= #1 q;
        else
            if(clear)
                q<= #1 0;
            else
                q<= #1 d;
    
endmodule