data/full_repos/permissive/172705897/simulation/instruction_mem.v
data/verilator_xmls/abe94056-dd2e-485d-84bd-75fc7eaf4aa4.xml
module instruction_memory(addr, out);
	input[31:0]	addr;
	output reg[31:0] out;

	reg[31:0] instruction_memory[0:2**9-1];

	initial begin

		$readmemh("simulation/program.hex",instruction_memory);
	end

	assign out = instruction_memory[addr >> 2];

endmodule
module instruction_memory(addr, out);

	input[31:0]	addr;
	output reg[31:0] out;

	reg[31:0] instruction_memory[0:2**9-1];

	initial begin

		$readmemh("simulation/program.hex",instruction_memory);
	end

	assign out = instruction_memory[addr >> 2];

endmodule