data/full_repos/permissive/205957121/mango1.v
 line:426 column:26: Illegal character "'"
1: b'%Error: data/full_repos/permissive/205957121/mango1.v:2: Cannot find include file: hvsync_generator.v\n`include "hvsync_generator.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205957121,data/full_repos/permissive/205957121/hvsync_generator.v\n             data/full_repos/permissive/205957121,data/full_repos/permissive/205957121/hvsync_generator.v.v\n             data/full_repos/permissive/205957121,data/full_repos/permissive/205957121/hvsync_generator.v.sv\n             hvsync_generator.v\n             hvsync_generator.v.v\n             hvsync_generator.v.sv\n             obj_dir/hvsync_generator.v\n             obj_dir/hvsync_generator.v.v\n             obj_dir/hvsync_generator.v.sv\n%Error: data/full_repos/permissive/205957121/mango1.v:3: Cannot find include file: cpu6502.v\n`include "cpu6502.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/205957121/mango1.v:4: Cannot find include file: font_cp437_8x8.v\n`include "font_cp437_8x8.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module apple1_top(clk, reset, hsync, vsync, rgb, keycode, keystrobe);

  input clk, reset;
  input [7:0] keycode;
  output reg keystrobe;
  output hsync, vsync;
  output [2:0] rgb;
  wire display_on;
  wire [8:0] hpos;
  wire [8:0] vpos;

  wire [15:0] AB;
  wire [7:0] DI;
  wire [7:0] DO;
  wire WE;
  wire IRQ=0;
  wire NMI=0;
  wire RDY=1;

  cpu6502 cpu( clk, reset, AB, DI, DO, WE, IRQ, NMI, RDY );

  always @(posedge clk)
    begin
      casez (AB)
        16'h0zzz: DI <= ram[AB[11:0]];
        16'hd010: begin
          if (keycode >= 97+128 && keycode <= 122+128)
            DI <= keycode - 32;
          else
            DI <= keycode;
          keystrobe <= (keycode & 8'h80) != 0;
        end
        16'hd011: begin
          DI <= keycode & 8'h80;
          keystrobe <= 0;
        end
        16'hd012: begin
          DI <= {!tready, 7'b0};
        end
        16'hffzz: DI <= monitor_rom[AB[7:0]];
      endcase
    end

  always @(posedge clk)
    if (WE) begin
      casez (AB)
        16'hd010: begin end
        16'hd011: begin end
        16'hd012: begin end
        16'hd013: begin end
        16'h0zzz: ram[AB[11:0]] <= DO;
      endcase
    end

  reg [7:0] ram[4096];
  reg [7:0] monitor_rom[256];

  initial begin
    $readmemh("mango1.hex", monitor_rom);
  end
  
  hvsync_generator hvsync_gen(
    .clk(clk),
    .reset(reset),
    .hsync(hsync),
    .vsync(vsync),
    .display_on(display_on),
    .hpos(hpos),
    .vpos(vpos)
  );

  wire tready;
  wire dot;
  wire te = WE && AB == 16'hd012;
  signetics_term terminal(clk, reset, hpos, vpos,
                          tready, dot,
                          te, .ti(DO & 8'h7f));
  
  wire r = display_on && 0;
  wire g = display_on && dot;
  wire b = display_on && 0;
  assign rgb = {b,g,r};

endmodule
module apple1_top(clk, reset, hsync, vsync, rgb, keycode, keystrobe);


  input clk, reset;
  input [7:0] keycode;
  output reg keystrobe;
  output hsync, vsync;
  output [2:0] rgb;
  wire display_on;
  wire [8:0] hpos;
  wire [8:0] vpos;

  wire [15:0] AB;
  wire [7:0] DI;
  wire [7:0] DO;
  wire WE;
  wire IRQ=0;
  wire NMI=0;
  wire RDY=1;

  cpu6502 cpu( clk, reset, AB, DI, DO, WE, IRQ, NMI, RDY );

  always @(posedge clk)
    begin
      casez (AB)
        16'h0zzz: DI <= ram[AB[11:0]];
        16'hd010: begin
          if (keycode >= 97+128 && keycode <= 122+128)
            DI <= keycode - 32;
          else
            DI <= keycode;
          keystrobe <= (keycode & 8'h80) != 0;
        end
        16'hd011: begin
          DI <= keycode & 8'h80;
          keystrobe <= 0;
        end
        16'hd012: begin
          DI <= {!tready, 7'b0};
        end
        16'hffzz: DI <= monitor_rom[AB[7:0]];
      endcase
    end

  always @(posedge clk)
    if (WE) begin
      casez (AB)
        16'hd010: begin end
        16'hd011: begin end
        16'hd012: begin end
        16'hd013: begin end
        16'h0zzz: ram[AB[11:0]] <= DO;
      endcase
    end

  reg [7:0] ram[4096];
  reg [7:0] monitor_rom[256];

  initial begin
    $readmemh("mango1.hex", monitor_rom);
  end
  
  hvsync_generator hvsync_gen(
    .clk(clk),
    .reset(reset),
    .hsync(hsync),
    .vsync(vsync),
    .display_on(display_on),
    .hpos(hpos),
    .vpos(vpos)
  );

  wire tready;
  wire dot;
  wire te = WE && AB == 16'hd012;
  signetics_term terminal(clk, reset, hpos, vpos,
                          tready, dot,
                          te, .ti(DO & 8'h7f));
  
  wire r = display_on && 0;
  wire g = display_on && dot;
  wire b = display_on && 0;
  assign rgb = {b,g,r};

endmodule