data/full_repos/permissive/120024308/src/cpu/bubbler.v
 line:159: before: ":"
1: b"%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:159: Define or directive not defined: '`NOP'\n   `NOP:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:159: syntax error, unexpected ':', expecting endcase\n   `NOP:\n       ^\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:164: Define or directive not defined: '`ADDI'\n   `ADDI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:165: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:170: Define or directive not defined: '`ADD'\n   `ADD:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:171: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:176: Define or directive not defined: '`SUB'\n   `SUB:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:177: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:182: Define or directive not defined: '`SUBI'\n   `SUBI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:183: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:188: Define or directive not defined: '`AND'\n   `AND:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:189: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:194: Define or directive not defined: '`OR'\n   `OR:\n   ^~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:195: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:200: Define or directive not defined: '`XOR'\n   `XOR:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:201: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:206: Define or directive not defined: '`NOR'\n   `NOR:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:207: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:212: Define or directive not defined: '`SLT'\n   `SLT:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:213: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:218: Define or directive not defined: '`SLTI'\n   `SLTI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:219: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:224: Define or directive not defined: '`ANDI'\n   `ANDI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:225: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:230: Define or directive not defined: '`ORI'\n   `ORI:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:231: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:236: Define or directive not defined: '`XORI'\n   `XORI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:237: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:242: Define or directive not defined: '`SLL'\n   `SLL:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:243: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:248: Define or directive not defined: '`SRL'\n   `SRL:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:249: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:254: Define or directive not defined: '`MULT'\n   `MULT:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:255: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:260: Define or directive not defined: '`MFHI'\n   `MFHI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:261: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:265: Define or directive not defined: '`MTHI'\n   `MTHI:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:266: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:270: Define or directive not defined: '`MFLO'\n   `MFLO:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:271: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:275: Define or directive not defined: '`MTLO'\n   `MTLO:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:276: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:280: Define or directive not defined: '`DIV'\n   `DIV:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:281: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:286: Define or directive not defined: '`J'\n   `J:\n   ^~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:287: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:291: Define or directive not defined: '`JR'\n   `JR:\n   ^~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:292: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:297: Define or directive not defined: '`JALR'\n   `JALR:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/bubbler.v:298: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module Bubbler #(parameter R_ADDR_SIZE=5, parameter OP_SIZE=6, parameter INSTRUCTION_SIZE = 32, parameter INMEDIATE_SIZE = 16, parameter ZERO_PAD = 11)
   (
    input wire 			    Clock,
    input wire 			    Reset,
    input wire [31:0] 		    current_address,
    input wire 			    global_branch_taken,
    input wire [OP_SIZE-1:0] 	    operation,
    input wire [INMEDIATE_SIZE-1:0] inmediate,
    input wire [R_ADDR_SIZE-1:0]    destination,
    input wire [R_ADDR_SIZE-1:0]    read0,
    input wire [R_ADDR_SIZE-1:0]    read1,
    input wire [R_ADDR_SIZE-1:0]    read2,
    input wire 			    branch_taken,
    input wire 			    link,
    input wire 			    from_register,
    input wire 			    ram_enable_write,
    input wire 			    ram_enable_read,


    input wire [OP_SIZE-1:0] 	    past_operation0,
    input wire [OP_SIZE-1:0] 	    past_operation1,
    input wire [OP_SIZE-1:0] 	    past_operation2,
    input wire [R_ADDR_SIZE-1:0]    past_destination0,
    input wire [R_ADDR_SIZE-1:0]    past_destination1,
    input wire [R_ADDR_SIZE-1:0]    past_destination2,

    output reg 			    stall,
    output reg [31:0] 		    overwrite_address,
    output reg [OP_SIZE-1:0] 	    out_operation,
    output reg [INMEDIATE_SIZE-1:0] out_inmediate,
    output reg [R_ADDR_SIZE-1:0]    out_destination,
    output reg [R_ADDR_SIZE-1:0]    out_read0,
    output reg [R_ADDR_SIZE-1:0]    out_read1,
    output reg [R_ADDR_SIZE-1:0]    out_read2,
    output reg 			    out_branch_taken,
    output reg 			    out_link,
    output reg 			    out_from_register,
    output reg 			    out_ram_enable_write,
    output reg 			    out_ram_enable_read
                                    );


   wire 			    not_null_destination;   
   wire 			    condition_for_I;
   wire 			    condition_for_R;
   wire 			    condition_for_branch;
   
   
   

    always @ (posedge Clock)
      begin
	 overwrite_address <= current_address;
	 

    if(Reset)
      begin
	 overwrite_address <= 0;
         out_inmediate <= 0;
         out_destination <= 0;
         out_read0 <= 0;
         out_read1 <= 0;
         out_read2 <= 0;
         out_branch_taken <= 0;
         out_link <= 0;
         out_from_register <= 0;
         out_ram_enable_write <= 0;
         out_ram_enable_read <= 0;
      end
    else
      begin         
         if(stall)
           begin
	      overwrite_address <= overwrite_address;	      
              out_operation <= 0;
              out_inmediate <= 0;
              out_destination <= 0;
              out_read0 <= 0;
              out_read1 <= 0;
              out_read2 <= 0;
              out_branch_taken <= 0;
              out_link <= 0;
              out_from_register <= 0;
              out_ram_enable_write <= 0;
              out_ram_enable_read <= 0;
           end
	 else
	   begin
	      out_operation <= operation;
              out_inmediate <= inmediate;
              out_destination <= destination;
              out_read0 <= read0;
              out_read1 <= read1;
              out_read2 <= read2;
              out_branch_taken <= branch_taken;
              out_link <= link;
              out_from_register <= from_register;
              out_ram_enable_write <= ram_enable_write;
              out_ram_enable_read <= ram_enable_read;
	   end
      end
    end

   assign condition_for_I = ((read1 == past_destination0 && past_destination0 !=0) || 
			     (read1 == past_destination1 && past_destination1 !=0) || 
			     (read1 == past_destination2 && past_destination2 !=0));
   
   assign condition_for_R = ((read1 == past_destination0 && past_destination0 !=0) || 
			     (read1 == past_destination1 && past_destination1 !=0) || 
			     (read1 == past_destination2 && past_destination2 !=0) ||
			     (read0 == past_destination0 && past_destination0 !=0) || 
			     (read0 == past_destination1 && past_destination1 !=0) || 
			     (read0 == past_destination2 && past_destination2 !=0));
   
   assign condition_for_branch = ((read1 == past_destination0 && past_destination0 !=0) || 
				  (read1 == past_destination1 && past_destination1 !=0) || 
				  (read1 == past_destination2 && past_destination2 !=0) ||
				  (read2 == past_destination0 && past_destination0 !=0) || 
				  (read2 == past_destination1 && past_destination1 !=0) || 
				  (read2 == past_destination2 && past_destination2 !=0));

   
   
   

   always @(*)
     begin
        stall = 0;
        case(operation)

	  `NOP:
            begin
               stall = 0;
            end

	  `ADDI:
	    begin
	       if (condition_for_I)
		  stall = 1;
	    end

	  `ADD:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `SUB:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `SUBI:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `AND:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `OR:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `XOR:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `NOR:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `SLT:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `SLTI:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `ANDI:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `ORI:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `XORI:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `SLL:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `SRL:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `MULT:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `MFHI:
	    begin
	       stall = 0;
	    end

	  `MTHI:
	    begin
	       stall = 0;
	    end

	  `MFLO:
	    begin
	       stall = 0;
	    end

	  `MTLO:
	    begin
	       stall = 0;
	    end

	  `DIV:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `J:
	    begin
	       stall = 0;
	    end

	  `JR:
	    begin
	       if (read0 == past_destination0 || read0 == past_destination1 || read0 == past_destination2)
		 stall = 1;
	    end

	  `JALR:
	    begin
	       if (read0 == past_destination0 || read0 == past_destination1 || read0 == past_destination2)
		 stall = 1;
	    end

	  `BLTZ:
	    begin
	       if (condition_for_branch)
		 stall =1;
	    end

	  `JAL:
	    begin
	       stall = 0;
	    end

	  `BEQ:
	    begin
	       if(condition_for_branch)
		 stall = 1;
	    end

	  `BNE:
	    begin
	       if(condition_for_branch)
		 stall = 1;
	    end

	  `BGTZ:
	    begin
	       if(condition_for_branch)
		 stall = 1;
	    end

	  `LW:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `SW:
	    begin

	       if (condition_for_branch)
		 stall = 1;
	    end

          `LEDI:
            begin
               stall = 0;
            end

          `LED:
            begin
               if(condition_for_I)
                 stall = 1;
            end

          default:

            begin
               stall = 1;               
            end
        endcase
     end
endmodule
module Bubbler #(parameter R_ADDR_SIZE=5, parameter OP_SIZE=6, parameter INSTRUCTION_SIZE = 32, parameter INMEDIATE_SIZE = 16, parameter ZERO_PAD = 11)
   (
    input wire 			    Clock,
    input wire 			    Reset,
    input wire [31:0] 		    current_address,
    input wire 			    global_branch_taken,
    input wire [OP_SIZE-1:0] 	    operation,
    input wire [INMEDIATE_SIZE-1:0] inmediate,
    input wire [R_ADDR_SIZE-1:0]    destination,
    input wire [R_ADDR_SIZE-1:0]    read0,
    input wire [R_ADDR_SIZE-1:0]    read1,
    input wire [R_ADDR_SIZE-1:0]    read2,
    input wire 			    branch_taken,
    input wire 			    link,
    input wire 			    from_register,
    input wire 			    ram_enable_write,
    input wire 			    ram_enable_read,


    input wire [OP_SIZE-1:0] 	    past_operation0,
    input wire [OP_SIZE-1:0] 	    past_operation1,
    input wire [OP_SIZE-1:0] 	    past_operation2,
    input wire [R_ADDR_SIZE-1:0]    past_destination0,
    input wire [R_ADDR_SIZE-1:0]    past_destination1,
    input wire [R_ADDR_SIZE-1:0]    past_destination2,

    output reg 			    stall,
    output reg [31:0] 		    overwrite_address,
    output reg [OP_SIZE-1:0] 	    out_operation,
    output reg [INMEDIATE_SIZE-1:0] out_inmediate,
    output reg [R_ADDR_SIZE-1:0]    out_destination,
    output reg [R_ADDR_SIZE-1:0]    out_read0,
    output reg [R_ADDR_SIZE-1:0]    out_read1,
    output reg [R_ADDR_SIZE-1:0]    out_read2,
    output reg 			    out_branch_taken,
    output reg 			    out_link,
    output reg 			    out_from_register,
    output reg 			    out_ram_enable_write,
    output reg 			    out_ram_enable_read
                                    );



   wire 			    not_null_destination;   
   wire 			    condition_for_I;
   wire 			    condition_for_R;
   wire 			    condition_for_branch;
   
   
   

    always @ (posedge Clock)
      begin
	 overwrite_address <= current_address;
	 

    if(Reset)
      begin
	 overwrite_address <= 0;
         out_inmediate <= 0;
         out_destination <= 0;
         out_read0 <= 0;
         out_read1 <= 0;
         out_read2 <= 0;
         out_branch_taken <= 0;
         out_link <= 0;
         out_from_register <= 0;
         out_ram_enable_write <= 0;
         out_ram_enable_read <= 0;
      end
    else
      begin         
         if(stall)
           begin
	      overwrite_address <= overwrite_address;	      
              out_operation <= 0;
              out_inmediate <= 0;
              out_destination <= 0;
              out_read0 <= 0;
              out_read1 <= 0;
              out_read2 <= 0;
              out_branch_taken <= 0;
              out_link <= 0;
              out_from_register <= 0;
              out_ram_enable_write <= 0;
              out_ram_enable_read <= 0;
           end
	 else
	   begin
	      out_operation <= operation;
              out_inmediate <= inmediate;
              out_destination <= destination;
              out_read0 <= read0;
              out_read1 <= read1;
              out_read2 <= read2;
              out_branch_taken <= branch_taken;
              out_link <= link;
              out_from_register <= from_register;
              out_ram_enable_write <= ram_enable_write;
              out_ram_enable_read <= ram_enable_read;
	   end
      end
    end

   assign condition_for_I = ((read1 == past_destination0 && past_destination0 !=0) || 
			     (read1 == past_destination1 && past_destination1 !=0) || 
			     (read1 == past_destination2 && past_destination2 !=0));
   
   assign condition_for_R = ((read1 == past_destination0 && past_destination0 !=0) || 
			     (read1 == past_destination1 && past_destination1 !=0) || 
			     (read1 == past_destination2 && past_destination2 !=0) ||
			     (read0 == past_destination0 && past_destination0 !=0) || 
			     (read0 == past_destination1 && past_destination1 !=0) || 
			     (read0 == past_destination2 && past_destination2 !=0));
   
   assign condition_for_branch = ((read1 == past_destination0 && past_destination0 !=0) || 
				  (read1 == past_destination1 && past_destination1 !=0) || 
				  (read1 == past_destination2 && past_destination2 !=0) ||
				  (read2 == past_destination0 && past_destination0 !=0) || 
				  (read2 == past_destination1 && past_destination1 !=0) || 
				  (read2 == past_destination2 && past_destination2 !=0));

   
   
   

   always @(*)
     begin
        stall = 0;
        case(operation)

	  `NOP:
            begin
               stall = 0;
            end

	  `ADDI:
	    begin
	       if (condition_for_I)
		  stall = 1;
	    end

	  `ADD:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `SUB:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `SUBI:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `AND:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `OR:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `XOR:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `NOR:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `SLT:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `SLTI:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `ANDI:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `ORI:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `XORI:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `SLL:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `SRL:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `MULT:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `MFHI:
	    begin
	       stall = 0;
	    end

	  `MTHI:
	    begin
	       stall = 0;
	    end

	  `MFLO:
	    begin
	       stall = 0;
	    end

	  `MTLO:
	    begin
	       stall = 0;
	    end

	  `DIV:
	    begin
	       if (condition_for_R)
		 stall = 1;
	    end

	  `J:
	    begin
	       stall = 0;
	    end

	  `JR:
	    begin
	       if (read0 == past_destination0 || read0 == past_destination1 || read0 == past_destination2)
		 stall = 1;
	    end

	  `JALR:
	    begin
	       if (read0 == past_destination0 || read0 == past_destination1 || read0 == past_destination2)
		 stall = 1;
	    end

	  `BLTZ:
	    begin
	       if (condition_for_branch)
		 stall =1;
	    end

	  `JAL:
	    begin
	       stall = 0;
	    end

	  `BEQ:
	    begin
	       if(condition_for_branch)
		 stall = 1;
	    end

	  `BNE:
	    begin
	       if(condition_for_branch)
		 stall = 1;
	    end

	  `BGTZ:
	    begin
	       if(condition_for_branch)
		 stall = 1;
	    end

	  `LW:
	    begin
	       if (condition_for_I)
		 stall = 1;
	    end

	  `SW:
	    begin

	       if (condition_for_branch)
		 stall = 1;
	    end

          `LEDI:
            begin
               stall = 0;
            end

          `LED:
            begin
               if(condition_for_I)
                 stall = 1;
            end

          default:

            begin
               stall = 1;               
            end
        endcase
     end
endmodule