data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_decoder2to4.v
 line:370: before: "."
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_decoder2to4.v:22: Unsupported: Ignoring delay on this delayed statement.\n        repeat(4)#1\n                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_decoder2to4.v:15: Cannot find file containing module: \'decoder2to4\'\n    decoder2to4 utt(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches,data/full_repos/permissive/212763527/decoder2to4\n             data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches,data/full_repos/permissive/212763527/decoder2to4.v\n             data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches,data/full_repos/permissive/212763527/decoder2to4.sv\n             decoder2to4\n             decoder2to4.v\n             decoder2to4.sv\n             obj_dir/decoder2to4\n             obj_dir/decoder2to4.v\n             obj_dir/decoder2to4.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_decoder2to4;


    reg[1:0] x;


    wire[3:0] y;

    initial begin
        x=0;
    end
    
    decoder2to4 utt(
        x,
        y
    );

    initial begin

        repeat(4)#1
            x = x+1;
        $finish;
    end

endmodule
module tb_decoder2to4;



    reg[1:0] x;


    wire[3:0] y;

    initial begin
        x=0;
    end
    
    decoder2to4 utt(
        x,
        y
    );

    initial begin

        repeat(4)#1
            x = x+1;
        $finish;
    end

endmodule