data/full_repos/permissive/201275379/src/cpu/core/utility/PipelineDeliverAsyn.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/201275379/src/cpu/core/utility/PipelineDeliverAsyn.v:28: Duplicate declaration of signal: 'out'\n                                                                                          : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  reg[WIDTH - 1:0] out;\n                   ^~~\n        data/full_repos/permissive/201275379/src/cpu/core/utility/PipelineDeliverAsyn.v:10: ... Location of original declaration\n  output  [WIDTH - 1:0] out\n                        ^~~\n%Error: Exiting due to 1 error(s)\n"
module PipelineDeliverAsyn #(parameter WIDTH = 1) (
  input                 clk,
  input                 rst,
  input                 flush_in,
  input                 stall_current_stage_in,
  input                 stall_next_stage_in,
  input   [WIDTH - 1:0] in,
  output  [WIDTH - 1:0] out
);

  reg flush_delay, stall_current, stall_next;
  wire flush, stall_current_stage, stall_next_stage;


  assign flush = flush_in | flush_delay;
  assign stall_current_stage = stall_current_stage_in | stall_current;
  assign stall_next_stage = stall_next_stage_in | stall_next;


  always @(posedge clk) begin
    flush_delay <= flush_in;
    stall_current <= stall_current_stage_in;
    stall_next <= stall_next_stage_in;
  end

  reg[WIDTH - 1:0] out;

  always @(*) begin
    if (!rst) begin
      out <= 0;
    end
    else if (flush) begin
      out <= 0;
    end
    else if (stall_current_stage && !stall_next_stage) begin
      out <= 0;
    end
    else if (!stall_current_stage) begin
      out <= in;
    end
  end

endmodule
module PipelineDeliverAsyn #(parameter WIDTH = 1) (
  input                 clk,
  input                 rst,
  input                 flush_in,
  input                 stall_current_stage_in,
  input                 stall_next_stage_in,
  input   [WIDTH - 1:0] in,
  output  [WIDTH - 1:0] out
);


  reg flush_delay, stall_current, stall_next;
  wire flush, stall_current_stage, stall_next_stage;


  assign flush = flush_in | flush_delay;
  assign stall_current_stage = stall_current_stage_in | stall_current;
  assign stall_next_stage = stall_next_stage_in | stall_next;


  always @(posedge clk) begin
    flush_delay <= flush_in;
    stall_current <= stall_current_stage_in;
    stall_next <= stall_next_stage_in;
  end

  reg[WIDTH - 1:0] out;

  always @(*) begin
    if (!rst) begin
      out <= 0;
    end
    else if (flush) begin
      out <= 0;
    end
    else if (stall_current_stage && !stall_next_stage) begin
      out <= 0;
    end
    else if (!stall_current_stage) begin
      out <= in;
    end
  end

endmodule