data/full_repos/permissive/135701568/BrVerify.v
data/verilator_xmls/dbdfeb8b-2cf4-4b42-b0bd-b45ca398a11e.xml
module BrVerify (opCode, Cin, Zin, BrTaken);
  input [4:0] opCode;
  input Cin, Zin;
  output reg BrTaken;
  always @ ( opCode, Cin, Zin ) begin
    BrTaken=0;
    case(opCode)
    5'b10100 : begin if(Zin)begin BrTaken=1; end  end
    5'b10101 : begin if(~Zin)begin BrTaken=1; end end
    5'b10110 : begin if(Cin)begin BrTaken=1; end  end
    5'b10111 : begin if(~Cin)begin BrTaken=1; end end
    default: BrTaken=0;
    endcase
  end
endmodule
module BrVerify (opCode, Cin, Zin, BrTaken);

  input [4:0] opCode;
  input Cin, Zin;
  output reg BrTaken;
  always @ ( opCode, Cin, Zin ) begin
    BrTaken=0;
    case(opCode)
    5'b10100 : begin if(Zin)begin BrTaken=1; end  end
    5'b10101 : begin if(~Zin)begin BrTaken=1; end end
    5'b10110 : begin if(Cin)begin BrTaken=1; end  end
    5'b10111 : begin if(~Cin)begin BrTaken=1; end end
    default: BrTaken=0;
    endcase
  end
endmodule