data/full_repos/permissive/201275379/test/storage/RegFile_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:3: Cannot find include file: tb.v\n`include "tb.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/test/storage,data/full_repos/permissive/201275379/tb.v\n             data/full_repos/permissive/201275379/test/storage,data/full_repos/permissive/201275379/tb.v.v\n             data/full_repos/permissive/201275379/test/storage,data/full_repos/permissive/201275379/tb.v.sv\n             tb.v\n             tb.v.v\n             tb.v.sv\n             obj_dir/tb.v\n             obj_dir/tb.v.v\n             obj_dir/tb.v.sv\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:4: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:5: Cannot find include file: rob.v\n`include "rob.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:12: Define or directive not defined: \'`GEN_TICK\'\n  `GEN_TICK(clk, rst);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:12: syntax error, unexpected \'(\'\n  `GEN_TICK(clk, rst);\n            ^~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:16: Define or directive not defined: \'`REG_ADDR_BUS\'\n  reg[`REG_ADDR_BUS]  write_addr;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:16: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`REG_ADDR_BUS]  write_addr;\n                   ^\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:17: Define or directive not defined: \'`ROB_ADDR_BUS\'\n  reg[`ROB_ADDR_BUS]  write_ref_id;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`ROB_ADDR_BUS]  write_ref_id;\n                   ^\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:20: Define or directive not defined: \'`REG_ADDR_BUS\'\n  reg[`REG_ADDR_BUS]  commit_addr;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`REG_ADDR_BUS]  commit_addr;\n                   ^\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:21: Define or directive not defined: \'`DATA_BUS\'\n  reg[`DATA_BUS]      commit_data;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`DATA_BUS]      commit_data;\n               ^\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:24: Define or directive not defined: \'`REG_ADDR_BUS\'\n  reg[`REG_ADDR_BUS]  read_addr_1;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`REG_ADDR_BUS]  read_addr_1;\n                   ^\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:25: Define or directive not defined: \'`REG_ADDR_BUS\'\n  reg[`REG_ADDR_BUS]  read_addr_2;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`REG_ADDR_BUS]  read_addr_2;\n                   ^\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:30: Define or directive not defined: \'`DATA_BUS\'\n  wire[`DATA_BUS]     read_data_1;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`DATA_BUS]     read_data_1;\n                ^\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:31: Define or directive not defined: \'`DATA_BUS\'\n  wire[`DATA_BUS]     read_data_2;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`DATA_BUS]     read_data_2;\n                ^\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:73: Define or directive not defined: \'`TICK\'\n      case (`TICK)\n            ^~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:73: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      case (`TICK)\n                 ^\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:84: syntax error, unexpected \':\'\n        1: begin\n         ^\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:88: Define or directive not defined: \'`ROB_ADDR_WIDTH\'\n          write_ref_id <= `ROB_ADDR_WIDTH\'h0a;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:94: syntax error, unexpected INTEGER NUMBER\n        2: begin\n        ^\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:98: Define or directive not defined: \'`ROB_ADDR_WIDTH\'\n          write_ref_id <= `ROB_ADDR_WIDTH\'h0f;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:117: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("read_is_ref_1 ", read_is_ref_1);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:118: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("read_is_ref_2 ", read_is_ref_2);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:119: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("read_data_1   ", read_data_1);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:120: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("read_data_2   ", read_data_2);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/storage/RegFile_tb.v:122: Define or directive not defined: \'`END_AT_TICK\'\n    `END_AT_TICK(4);\n    ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module RegFile_tb(
  input clk,
  input rst
);

  `GEN_TICK(clk, rst);


  reg                 write_en;
  reg[`REG_ADDR_BUS]  write_addr;
  reg[`ROB_ADDR_BUS]  write_ref_id;
  reg                 commit_en;
  reg                 commit_restore;
  reg[`REG_ADDR_BUS]  commit_addr;
  reg[`DATA_BUS]      commit_data;
  reg                 read_en_1;
  reg                 read_en_2;
  reg[`REG_ADDR_BUS]  read_addr_1;
  reg[`REG_ADDR_BUS]  read_addr_2;


  wire                read_is_ref_1;
  wire                read_is_ref_2;
  wire[`DATA_BUS]     read_data_1;
  wire[`DATA_BUS]     read_data_2;

  RegFile regfile(
    .clk            (clk),
    .rst            (rst),
    .write_en       (write_en),
    .write_addr     (write_addr),
    .write_ref_id   (write_ref_id),
    .commit_en      (commit_en),
    .commit_restore (commit_restore),
    .commit_addr    (commit_addr),
    .commit_data    (commit_data),
    .read_en_1      (read_en_1),
    .read_en_2      (read_en_2),
    .read_addr_1    (read_addr_1),
    .read_addr_2    (read_addr_2),
    .read_is_ref_1  (read_is_ref_1),
    .read_is_ref_2  (read_is_ref_2),
    .read_data_1    (read_data_1),
    .read_data_2    (read_data_2)
  );

  always @(posedge clk) begin
    if (!rst) begin
      write_en <= 0;
      write_addr <= 0;
      write_ref_id <= 0;
      commit_en <= 0;
      commit_restore <= 0;
      commit_addr <= 0;
      commit_data <= 0;
      read_en_1 <= 0;
      read_en_2 <= 0;
      read_addr_1 <= 0;
      read_addr_2 <= 0;
    end
    else begin
      read_en_1 <= 1;
      read_en_2 <= 1;
      read_addr_1 <= 1;
      read_addr_2 <= 2;

      case (`TICK)
        0: begin
          $display("commit value");
          write_en <= 0;
          write_addr <= 0;
          write_ref_id <= 0;
          commit_en <= 1;
          commit_restore <= 0;
          commit_addr <= 1;
          commit_data <= 32'h12345678;
        end
        1: begin
          $display("write ref id");
          write_en <= 1;
          write_addr <= 1;
          write_ref_id <= `ROB_ADDR_WIDTH'h0a;
          commit_en <= 0;
          commit_restore <= 0;
          commit_addr <= 0;
          commit_data <= 0;
        end
        2: begin
          $display("write and commit at same time");
          write_en <= 1;
          write_addr <= 2;
          write_ref_id <= `ROB_ADDR_WIDTH'h0f;
          commit_en <= 1;
          commit_restore <= 0;
          commit_addr <= 2;
          commit_data <= 32'habcdef00;
        end
        3: begin
          $display("restore value");
          write_en <= 0;
          write_addr <= 0;
          write_ref_id <= 0;
          commit_en <= 0;
          commit_restore <= 1;
          commit_addr <= 0;
          commit_data <= 0;
        end
      endcase
    end

    `DISPLAY("read_is_ref_1 ", read_is_ref_1);
    `DISPLAY("read_is_ref_2 ", read_is_ref_2);
    `DISPLAY("read_data_1   ", read_data_1);
    `DISPLAY("read_data_2   ", read_data_2);
    $display("");
    `END_AT_TICK(4);
  end

endmodule
module RegFile_tb(
  input clk,
  input rst
);


  `GEN_TICK(clk, rst);


  reg                 write_en;
  reg[`REG_ADDR_BUS]  write_addr;
  reg[`ROB_ADDR_BUS]  write_ref_id;
  reg                 commit_en;
  reg                 commit_restore;
  reg[`REG_ADDR_BUS]  commit_addr;
  reg[`DATA_BUS]      commit_data;
  reg                 read_en_1;
  reg                 read_en_2;
  reg[`REG_ADDR_BUS]  read_addr_1;
  reg[`REG_ADDR_BUS]  read_addr_2;


  wire                read_is_ref_1;
  wire                read_is_ref_2;
  wire[`DATA_BUS]     read_data_1;
  wire[`DATA_BUS]     read_data_2;

  RegFile regfile(
    .clk            (clk),
    .rst            (rst),
    .write_en       (write_en),
    .write_addr     (write_addr),
    .write_ref_id   (write_ref_id),
    .commit_en      (commit_en),
    .commit_restore (commit_restore),
    .commit_addr    (commit_addr),
    .commit_data    (commit_data),
    .read_en_1      (read_en_1),
    .read_en_2      (read_en_2),
    .read_addr_1    (read_addr_1),
    .read_addr_2    (read_addr_2),
    .read_is_ref_1  (read_is_ref_1),
    .read_is_ref_2  (read_is_ref_2),
    .read_data_1    (read_data_1),
    .read_data_2    (read_data_2)
  );

  always @(posedge clk) begin
    if (!rst) begin
      write_en <= 0;
      write_addr <= 0;
      write_ref_id <= 0;
      commit_en <= 0;
      commit_restore <= 0;
      commit_addr <= 0;
      commit_data <= 0;
      read_en_1 <= 0;
      read_en_2 <= 0;
      read_addr_1 <= 0;
      read_addr_2 <= 0;
    end
    else begin
      read_en_1 <= 1;
      read_en_2 <= 1;
      read_addr_1 <= 1;
      read_addr_2 <= 2;

      case (`TICK)
        0: begin
          $display("commit value");
          write_en <= 0;
          write_addr <= 0;
          write_ref_id <= 0;
          commit_en <= 1;
          commit_restore <= 0;
          commit_addr <= 1;
          commit_data <= 32'h12345678;
        end
        1: begin
          $display("write ref id");
          write_en <= 1;
          write_addr <= 1;
          write_ref_id <= `ROB_ADDR_WIDTH'h0a;
          commit_en <= 0;
          commit_restore <= 0;
          commit_addr <= 0;
          commit_data <= 0;
        end
        2: begin
          $display("write and commit at same time");
          write_en <= 1;
          write_addr <= 2;
          write_ref_id <= `ROB_ADDR_WIDTH'h0f;
          commit_en <= 1;
          commit_restore <= 0;
          commit_addr <= 2;
          commit_data <= 32'habcdef00;
        end
        3: begin
          $display("restore value");
          write_en <= 0;
          write_addr <= 0;
          write_ref_id <= 0;
          commit_en <= 0;
          commit_restore <= 1;
          commit_addr <= 0;
          commit_data <= 0;
        end
      endcase
    end

    `DISPLAY("read_is_ref_1 ", read_is_ref_1);
    `DISPLAY("read_is_ref_2 ", read_is_ref_2);
    `DISPLAY("read_data_1   ", read_data_1);
    `DISPLAY("read_data_2   ", read_data_2);
    $display("");
    `END_AT_TICK(4);
  end

endmodule