data/full_repos/permissive/178052224/Tarea2/demux/demux.v
data/verilator_xmls/5caa1b79-563d-437c-baee-31b8678a0d72.xml
module demux(
                    input clk, reset_L,
                    output reg [3:0] data_out0, data_out1,
                    input [3:0] data_in );


    reg s = 'b0;


    initial data_out0 = 'b0;
    initial data_out1 = 'b0;
    

    always@(posedge clk) begin
        s <= ~s; 
        if (reset_L == 0)
        begin
            data_out0 <= 0;
            data_out1 <= 0;
        end
       
        else
        begin

            if (s==0) 
            begin
            data_out0 <= data_in;
            data_out1 <= 0;
            end


        else
        begin
            data_out0 <= 0;
            data_out1 <= data_in;
        end
      end
    end


endmodule
module demux(
                    input clk, reset_L,
                    output reg [3:0] data_out0, data_out1,
                    input [3:0] data_in );



    reg s = 'b0;


    initial data_out0 = 'b0;
    initial data_out1 = 'b0;
    

    always@(posedge clk) begin
        s <= ~s; 
        if (reset_L == 0)
        begin
            data_out0 <= 0;
            data_out1 <= 0;
        end
       
        else
        begin

            if (s==0) 
            begin
            data_out0 <= data_in;
            data_out1 <= 0;
            end


        else
        begin
            data_out0 <= 0;
            data_out1 <= data_in;
        end
      end
    end


endmodule