data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/lfsr15_shift.v
data/verilator_xmls/0b89549d-74cf-419b-8764-03c972139b29.xml
module lfsr15_shift #(
  parameter DataBits = 32,
  parameter LfsrSeed = 15'h5555)
(
  input                 clk,
  input                 rst,

  input [14:0]          seed,
  input                 init,
  input                 shift,
  output [DataBits-1:0] lfsr_data);


  localparam LfsrBits = 15;

  reg  [LfsrBits-1:0]            lfsr_reg;
  wire [LfsrBits + DataBits-1:0] lfsr_next;


  assign lfsr_next[LfsrBits-1:0] = lfsr_reg;
  genvar i;
  generate
    for (i=LfsrBits; i < LfsrBits + DataBits; i=i+1) begin: lfsr_bits
      assign lfsr_next[i] = lfsr_next[i-15] ^ lfsr_next[i-14];
    end
  endgenerate


  always @(posedge clk) begin
    if (init) begin
      lfsr_reg <= seed;
    end else if (shift) begin
      lfsr_reg <= lfsr_next[DataBits + LfsrBits - 1 : DataBits];
    end
    if (rst) begin
      lfsr_reg <= LfsrSeed;
    end
  end

  assign lfsr_data = lfsr_next[DataBits-1:0];

endmodule
module lfsr15_shift #(
  parameter DataBits = 32,
  parameter LfsrSeed = 15'h5555)
(
  input                 clk,
  input                 rst,

  input [14:0]          seed,
  input                 init,
  input                 shift,
  output [DataBits-1:0] lfsr_data);



  localparam LfsrBits = 15;

  reg  [LfsrBits-1:0]            lfsr_reg;
  wire [LfsrBits + DataBits-1:0] lfsr_next;


  assign lfsr_next[LfsrBits-1:0] = lfsr_reg;
  genvar i;
  generate
    for (i=LfsrBits; i < LfsrBits + DataBits; i=i+1) begin: lfsr_bits
      assign lfsr_next[i] = lfsr_next[i-15] ^ lfsr_next[i-14];
    end
  endgenerate


  always @(posedge clk) begin
    if (init) begin
      lfsr_reg <= seed;
    end else if (shift) begin
      lfsr_reg <= lfsr_next[DataBits + LfsrBits - 1 : DataBits];
    end
    if (rst) begin
      lfsr_reg <= LfsrSeed;
    end
  end

  assign lfsr_data = lfsr_next[DataBits-1:0];

endmodule