data/full_repos/permissive/156417892/hdl/WriteBack/DataBranch/DataBranch.v
data/verilator_xmls/bbf0a625-52ca-4225-bc3d-167980cc2219.xml
module DataBranch(MemRead,
                  Addr,
                  SigMemToReg,
                  Write2Reg);
   input SigMemToReg;
   input [31:0] MemRead, Addr;
   output [31:0] Write2Reg;
   
   assign Write2Reg = (SigMemToReg) ? MemRead : Addr; 
endmodule
module DataBranch(MemRead,
                  Addr,
                  SigMemToReg,
                  Write2Reg);

   input SigMemToReg;
   input [31:0] MemRead, Addr;
   output [31:0] Write2Reg;
   
   assign Write2Reg = (SigMemToReg) ? MemRead : Addr; 
endmodule