data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/tart_control.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/tart_control.v:70: Cannot find include file: tartcfg.v\n`include "tartcfg.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Error: Exiting due to 1 error(s)\n'
module tart_control
  #(
    parameter WIDTH = 8,
    parameter MSB   = WIDTH-1,
    parameter COUNT = 24,
    parameter CSB   = COUNT-1,
    parameter RTIME = 4,


    parameter PIPED = 1,
    parameter CHECK = 1,


    parameter DELAY = 3)
   (input          clk_i,
    input          rst_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [1:0]    adr_i,
    input [MSB:0]  dat_i,
    output [MSB:0] dat_o,

    input [MSB:0]  status_i,
    input [MSB:0]  extra_i,
    input          reset_ni,
    output         reset_o
    );

   reg [MSB:0]     dat;
   reg             ack = 1'b0;
   wire            stb_w, ack_w, r_stb;




   assign ack_o = ack;
   assign wat_o = 1'b0;
   assign rty_o = 1'b0;
   assign err_o = 1'b0;
   assign dat_o = dat;




   assign stb_w = CHECK ? cyc_i && stb_i : stb_i;
   assign ack_w = PIPED ? stb_w : stb_w && !ack;


   assign r_stb = stb_w && adr_i == 2'b11;





   always @(posedge clk_i)
     if (rst_i)
       ack <= #DELAY 1'b0;
     else
       ack <= #DELAY ack_w;


   always @(posedge clk_i)
     if (cyc_i && stb_i && !we_i)
       case (adr_i)
         2'b00:   dat <= #DELAY status_i;
         2'b01:   dat <= #DELAY extra_i;
         default: dat <= #DELAY 8'bx;
       endcase





   wb_reset #( .WIDTH(WIDTH), .RTIME(RTIME) ) WB_RESET0
     ( .clk_i(clk_i),
       .rst_i(rst_i),
       .cyc_i(cyc_i),
       .stb_i(r_stb),
       .we_i (we_i),
       .ack_o(),
       .dat_i(dat_i),
       .dat_o(),

       .reset_ni(reset_ni),
       .reset_o (reset_o)
       );


endmodule
module tart_control
  #(
    parameter WIDTH = 8,
    parameter MSB   = WIDTH-1,
    parameter COUNT = 24,
    parameter CSB   = COUNT-1,
    parameter RTIME = 4,


    parameter PIPED = 1,
    parameter CHECK = 1,


    parameter DELAY = 3)
   (input          clk_i,
    input          rst_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [1:0]    adr_i,
    input [MSB:0]  dat_i,
    output [MSB:0] dat_o,

    input [MSB:0]  status_i,
    input [MSB:0]  extra_i,
    input          reset_ni,
    output         reset_o
    );


   reg [MSB:0]     dat;
   reg             ack = 1'b0;
   wire            stb_w, ack_w, r_stb;




   assign ack_o = ack;
   assign wat_o = 1'b0;
   assign rty_o = 1'b0;
   assign err_o = 1'b0;
   assign dat_o = dat;




   assign stb_w = CHECK ? cyc_i && stb_i : stb_i;
   assign ack_w = PIPED ? stb_w : stb_w && !ack;


   assign r_stb = stb_w && adr_i == 2'b11;





   always @(posedge clk_i)
     if (rst_i)
       ack <= #DELAY 1'b0;
     else
       ack <= #DELAY ack_w;


   always @(posedge clk_i)
     if (cyc_i && stb_i && !we_i)
       case (adr_i)
         2'b00:   dat <= #DELAY status_i;
         2'b01:   dat <= #DELAY extra_i;
         default: dat <= #DELAY 8'bx;
       endcase





   wb_reset #( .WIDTH(WIDTH), .RTIME(RTIME) ) WB_RESET0
     ( .clk_i(clk_i),
       .rst_i(rst_i),
       .cyc_i(cyc_i),
       .stb_i(r_stb),
       .we_i (we_i),
       .ack_o(),
       .dat_i(dat_i),
       .dat_o(),

       .reset_ni(reset_ni),
       .reset_o (reset_o)
       );


endmodule