data/full_repos/permissive/135851130/TopSim.v
 line:51: before: "1"
1: b'%Warning-STMTDLY: data/full_repos/permissive/135851130/TopSim.v:36: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135851130/TopSim.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/135851130/TopSim.v:32: Cannot find file containing module: \'Toplevel\'\n Toplevel uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135851130,data/full_repos/permissive/135851130/Toplevel\n             data/full_repos/permissive/135851130,data/full_repos/permissive/135851130/Toplevel.v\n             data/full_repos/permissive/135851130,data/full_repos/permissive/135851130/Toplevel.sv\n             Toplevel\n             Toplevel.v\n             Toplevel.sv\n             obj_dir/Toplevel\n             obj_dir/Toplevel.v\n             obj_dir/Toplevel.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TopSim;


	reg clk;
	reg reset;


	Toplevel uut (
		.clk(clk), 
		.reset(reset)
	);
	always #10 clk=~clk;
	initial begin

		clk = 0;
		reset = 1;


		#100;
      reset = 0;


	end
      
endmodule
module TopSim;



	reg clk;
	reg reset;


	Toplevel uut (
		.clk(clk), 
		.reset(reset)
	);
	always #10 clk=~clk;
	initial begin

		clk = 0;
		reset = 1;


		#100;
      reset = 0;


	end
      
endmodule