data/full_repos/permissive/167489907/Memory/ROM/ROM_64bit_testbench.v
 line:13: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/ROM/ROM_64bit_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #640 $stop;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/ROM/ROM_64bit_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #5 clock <= ~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/ROM/ROM_64bit_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= address + 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/ROM/ROM_64bit_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #160 size <= size + 1\'b1;\n  ^\n%Error: data/full_repos/permissive/167489907/Memory/ROM/ROM_64bit_testbench.v:7: Cannot find file containing module: \'ROM_64bit\'\n ROM_64bit dut (data, address, clock, size);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167489907/Memory/ROM,data/full_repos/permissive/167489907/ROM_64bit\n             data/full_repos/permissive/167489907/Memory/ROM,data/full_repos/permissive/167489907/ROM_64bit.v\n             data/full_repos/permissive/167489907/Memory/ROM,data/full_repos/permissive/167489907/ROM_64bit.sv\n             ROM_64bit\n             ROM_64bit.v\n             ROM_64bit.sv\n             obj_dir/ROM_64bit\n             obj_dir/ROM_64bit.v\n             obj_dir/ROM_64bit.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ROM_64bit_testbench();
	wire [63:0] data;
	reg [7:0] address;
	reg [1:0] size;
	reg clock;
	
	ROM_64bit dut (data, address, clock, size);
	
	initial begin
		clock <= 1'b0;
		address <= 8'b0;
		size <= 2'b00;
		#640 $stop;
	end
	
	always
		#5 clock <= ~clock;
	
	always
		#10 address <= address + 1'b1;

	always 
		#160 size <= size + 1'b1;
	
endmodule
module ROM_64bit_testbench();

	wire [63:0] data;
	reg [7:0] address;
	reg [1:0] size;
	reg clock;
	
	ROM_64bit dut (data, address, clock, size);
	
	initial begin
		clock <= 1'b0;
		address <= 8'b0;
		size <= 2'b00;
		#640 $stop;
	end
	
	always
		#5 clock <= ~clock;
	
	always
		#10 address <= address + 1'b1;

	always 
		#160 size <= size + 1'b1;
	
endmodule