data/full_repos/permissive/131249673/MIPS_L_PipeLine/Reg_MEM_WB.v
1: b'%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Reg_MEM_WB.v:1: Cannot find include file: flopr.v\n`include "flopr.v"; \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/flopr.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/flopr.v.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/flopr.v.sv\n             flopr.v\n             flopr.v.v\n             flopr.v.sv\n             obj_dir/flopr.v\n             obj_dir/flopr.v.v\n             obj_dir/flopr.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Reg_MEM_WB ( clk, rst,
	MEM_instr, MEM_WB_instr,
	DataMem, DataMem_MEM_WB_r,
	ALUOut, ALUOut_MEM_WB_r,
	WriteDst, WriteDst_MEM_WB_r,
	EX_MEM_PC_r, MEM_WB_PC_r
	);

	input	clk, rst;
	input	[31:0]	MEM_instr;
	input	[31:0]	DataMem;
	input	[31:0]	ALUOut;
	input	[4:0]	WriteDst;
	input	[29:0]	EX_MEM_PC_r;

	output	[31:0]	MEM_WB_instr;
	output	[31:0]	DataMem_MEM_WB_r;
	output	[31:0]	ALUOut_MEM_WB_r;
	output	[4:0]	WriteDst_MEM_WB_r;
	output	[29:0]	MEM_WB_PC_r;


	
	flopr #(.WIDTH(32)) instr_r(
		.clk(clk), .rst(rst), .d(MEM_instr), .q(MEM_WB_instr)
	);
	
	flopr #(.WIDTH(32))	DataMem_r(
		.clk(clk), .rst(rst), .d(DataMem), .q(DataMem_MEM_WB_r)
	);

	flopr #(.WIDTH(32))	ALUOut_r(
		.clk(clk), .rst(rst), .d(ALUOut), .q(ALUOut_MEM_WB_r)
	);

	flopr #(.WIDTH(5))	WriteDst_r(
		.clk(clk), .rst(rst), .d(WriteDst), .q(WriteDst_MEM_WB_r)
	);

	flopr #(.WIDTH(30)) PC_r (
		.clk(clk), .rst(rst), .d(EX_MEM_PC_r), .q(MEM_WB_PC_r)
	);

	endmodule
module Reg_MEM_WB ( clk, rst,
	MEM_instr, MEM_WB_instr,
	DataMem, DataMem_MEM_WB_r,
	ALUOut, ALUOut_MEM_WB_r,
	WriteDst, WriteDst_MEM_WB_r,
	EX_MEM_PC_r, MEM_WB_PC_r
	);


	input	clk, rst;
	input	[31:0]	MEM_instr;
	input	[31:0]	DataMem;
	input	[31:0]	ALUOut;
	input	[4:0]	WriteDst;
	input	[29:0]	EX_MEM_PC_r;

	output	[31:0]	MEM_WB_instr;
	output	[31:0]	DataMem_MEM_WB_r;
	output	[31:0]	ALUOut_MEM_WB_r;
	output	[4:0]	WriteDst_MEM_WB_r;
	output	[29:0]	MEM_WB_PC_r;


	
	flopr #(.WIDTH(32)) instr_r(
		.clk(clk), .rst(rst), .d(MEM_instr), .q(MEM_WB_instr)
	);
	
	flopr #(.WIDTH(32))	DataMem_r(
		.clk(clk), .rst(rst), .d(DataMem), .q(DataMem_MEM_WB_r)
	);

	flopr #(.WIDTH(32))	ALUOut_r(
		.clk(clk), .rst(rst), .d(ALUOut), .q(ALUOut_MEM_WB_r)
	);

	flopr #(.WIDTH(5))	WriteDst_r(
		.clk(clk), .rst(rst), .d(WriteDst), .q(WriteDst_MEM_WB_r)
	);

	flopr #(.WIDTH(30)) PC_r (
		.clk(clk), .rst(rst), .d(EX_MEM_PC_r), .q(MEM_WB_PC_r)
	);

	endmodule