data/full_repos/permissive/174369527/SISD/alu.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/174369527/SISD/alu.v:5: Cannot find include file: alu_uadd-CLA2.v\n`include "alu_uadd-CLA2.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174369527/SISD,data/full_repos/permissive/174369527/alu_uadd-CLA2.v\n             data/full_repos/permissive/174369527/SISD,data/full_repos/permissive/174369527/alu_uadd-CLA2.v.v\n             data/full_repos/permissive/174369527/SISD,data/full_repos/permissive/174369527/alu_uadd-CLA2.v.sv\n             alu_uadd-CLA2.v\n             alu_uadd-CLA2.v.v\n             alu_uadd-CLA2.v.sv\n             obj_dir/alu_uadd-CLA2.v\n             obj_dir/alu_uadd-CLA2.v.v\n             obj_dir/alu_uadd-CLA2.v.sv\n%Error: data/full_repos/permissive/174369527/SISD/alu.v:16: syntax error, unexpected \'=\', expecting \')\' or \',\'\n output [0:0] o_zero = 1\'b0,\n                     ^\n%Error: data/full_repos/permissive/174369527/SISD/alu.v:19: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: Exiting due to 3 error(s)\n'
module alu
	#(parameter SLOW = 1'b0)
	(
	input wire [7:0] i_s1,
	input wire [7:0] i_s2,
	input wire [0:0] i_en,
	input wire [2:0] i_func,
	output wire [7:0] o_result,
	output [0:0] o_zero = 1'b0,
	output [0:0] o_negative = 1'b0,
	output  wire [0:0] o_overflow
	);
	
	alu_uadd #(.SIZE(8)) inst_uadd (
		.i_s1(i_s1),
		.i_s2(i_s2),
		.o_result(o_result),
		.o_carry(o_overflow)
		);


endmodule
module alu
	#(parameter SLOW = 1'b0)
	(
	input wire [7:0] i_s1,
	input wire [7:0] i_s2,
	input wire [0:0] i_en,
	input wire [2:0] i_func,
	output wire [7:0] o_result,
	output [0:0] o_zero = 1'b0,
	output [0:0] o_negative = 1'b0,
	output  wire [0:0] o_overflow
	);

	
	alu_uadd #(.SIZE(8)) inst_uadd (
		.i_s1(i_s1),
		.i_s2(i_s2),
		.o_result(o_result),
		.o_carry(o_overflow)
		);


endmodule