data/full_repos/permissive/170402453/AngularEncoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170402453/AngularEncoder.v:40: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'Rate_\' generates 32 bits.\n                                                                        : ... In instance SpeedController\n  assign Rate = Rate_;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/170402453/AngularEncoder.v:77: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'Duty_In\' generates 8 bits.\n                                                                        : ... In instance SpeedController\n   Rate_ <= Duty_In;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/170402453/AngularEncoder.v:87: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Duty_In\' generates 8 bits.\n                                                                        : ... In instance SpeedController\n  Rate_ <= ((Rate_ <= 10 && Duty_In > 10) || SetCounted == 0) ? \n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/AngularEncoder.v:89: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'Duty_Offset\' generates 9 bits.\n                                                                        : ... In instance SpeedController\n      (Duty_Offset > 255) ? 255 : Duty_Offset;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/AngularEncoder.v:97: Operator GT expects 32 or 11 bits on the LHS, but LHS\'s VARREF \'Count60Hz\' generates 10 bits.\n                                                                        : ... In instance SpeedController\n  if(Count60Hz > 1707) begin  \n               ^\n%Error: data/full_repos/permissive/170402453/AngularEncoder.v:104: Cannot find file containing module: \'PWM\'\n  PWM pwm1 ( \n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/PWM\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/PWM.v\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/PWM.sv\n             PWM\n             PWM.v\n             PWM.sv\n             obj_dir/PWM\n             obj_dir/PWM.v\n             obj_dir/PWM.sv\n%Error: data/full_repos/permissive/170402453/AngularEncoder.v:110: Cannot find file containing module: \'Average8\'\n  Average8 averager (  \n  ^~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n'
module SpeedController(
    input AE_CLK,
	 input PWM_CLK,
    input [7:0] Duty_In,
    input AngularEncoder,
    output PWM_Out,
	 output [7:0] Rate
	 );
	 
	 reg [7:0] Counter;
	 reg [9:0] Wait_Count;
	 reg [8:0] Duty_Offset;
	 reg [9:0] Count60Hz;
	 integer Rate_;
	 reg First;
	 
	 wire [7:0] SetCounted;
	 
	 assign Rate = Rate_;
	 
	 reg Average_CLK;
	 
	 initial begin
		First = 1;
		Counter = 0;
		Rate_ = 0;
		Wait_Count=0;
		Count60Hz = 0;

	 end
	 


	 
	 always @ (posedge AE_CLK) begin

		if(First) begin
			if(AngularEncoder) begin
				Wait_Count <= 0;
				Counter <= Counter+1;
			end else begin
				First <= 0;






			end
		end else if(AngularEncoder) begin
			First <= 1;
			Counter <= 1;
		end else if(Wait_Count > 1000) begin

			Wait_Count <= 0;
			Rate_ <= Duty_In;
		end else begin
			Wait_Count <= Wait_Count+1;
			Counter <= 0;
		end
		


		Duty_Offset <= 2*Duty_In-(Duty_In+SetCounted)/2;

		Rate_ <= ((Rate_ <= 10 && Duty_In > 10) || SetCounted == 0) ? 
						Duty_In : 
						(Duty_Offset > 255) ? 255 : Duty_Offset;
	 end
	 
	 
	 always @ (negedge AE_CLK) begin

		Count60Hz <= Count60Hz+1;
		Average_CLK <= 0;
		if(Count60Hz > 1707) begin
			Count60Hz <= 0;
			Average_CLK <= 1;
		end
	 end
	 
	 
	 PWM pwm1 ( 
		 .CLK(PWM_CLK), 
		 .DUTY_CYCLE(Rate_), 
		 .PWM_OUT(PWM_Out)
    );
	 
	 Average8 averager (
		.CLK(Average_CLK), 
		.SampleIN(Counter), 
		.AverageOUT(SetCounted)
    );
endmodule
module SpeedController(
    input AE_CLK,
	 input PWM_CLK,
    input [7:0] Duty_In,
    input AngularEncoder,
    output PWM_Out,
	 output [7:0] Rate
	 );

	 
	 reg [7:0] Counter;
	 reg [9:0] Wait_Count;
	 reg [8:0] Duty_Offset;
	 reg [9:0] Count60Hz;
	 integer Rate_;
	 reg First;
	 
	 wire [7:0] SetCounted;
	 
	 assign Rate = Rate_;
	 
	 reg Average_CLK;
	 
	 initial begin
		First = 1;
		Counter = 0;
		Rate_ = 0;
		Wait_Count=0;
		Count60Hz = 0;

	 end
	 


	 
	 always @ (posedge AE_CLK) begin

		if(First) begin
			if(AngularEncoder) begin
				Wait_Count <= 0;
				Counter <= Counter+1;
			end else begin
				First <= 0;






			end
		end else if(AngularEncoder) begin
			First <= 1;
			Counter <= 1;
		end else if(Wait_Count > 1000) begin

			Wait_Count <= 0;
			Rate_ <= Duty_In;
		end else begin
			Wait_Count <= Wait_Count+1;
			Counter <= 0;
		end
		


		Duty_Offset <= 2*Duty_In-(Duty_In+SetCounted)/2;

		Rate_ <= ((Rate_ <= 10 && Duty_In > 10) || SetCounted == 0) ? 
						Duty_In : 
						(Duty_Offset > 255) ? 255 : Duty_Offset;
	 end
	 
	 
	 always @ (negedge AE_CLK) begin

		Count60Hz <= Count60Hz+1;
		Average_CLK <= 0;
		if(Count60Hz > 1707) begin
			Count60Hz <= 0;
			Average_CLK <= 1;
		end
	 end
	 
	 
	 PWM pwm1 ( 
		 .CLK(PWM_CLK), 
		 .DUTY_CYCLE(Rate_), 
		 .PWM_OUT(PWM_Out)
    );
	 
	 Average8 averager (
		.CLK(Average_CLK), 
		.SampleIN(Counter), 
		.AverageOUT(SetCounted)
    );
endmodule