data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:358: Cannot find file containing module: 'NOR3A'\n    NOR3A \\SM_8S_1_i_0_a3[3]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .C(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A.sv\n             NOR3A\n             NOR3A.v\n             NOR3A.sv\n             obj_dir/NOR3A\n             obj_dir/NOR3A.v\n             obj_dir/NOR3A.sv\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:360: Cannot find file containing module: 'NOR2A'\n    NOR2A \\SM_8S_1_i_0_1[3]  (.A(SM_8S_1_i_0_a3_0_0), .B(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:362: Cannot find file containing module: 'NOR2B'\n    NOR2B \\SM_8S_1_i_0_o2[1]  (.A(Disp_dat[3]), .B(Disp_dat[1]), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:364: Cannot find file containing module: 'NOR3B'\n    NOR3B \\SM_8S_1_i_i_a2[6]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:366: Cannot find file containing module: 'AX1C'\n    AX1C \\SM_8S_1_i_i_x2[6]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:368: Cannot find file containing module: 'GND'\n    GND GND_i_0 (.Y(GND_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:369: Cannot find file containing module: 'NOR2'\n    NOR2 \\SM_8S_1_0_0_o2[5]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:371: Cannot find file containing module: 'OR2B'\n    OR2B \\SM_8S_1_i_0_a3_0[1]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:373: Cannot find file containing module: 'AO1C'\n    AO1C \\SM_8S_1_0_0[5]  (.A(N_17), .B(Disp_dat[0]), .C(N_15_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:375: Cannot find file containing module: 'VCC'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:376: Cannot find file containing module: 'OR3C'\n    OR3C \\SM_8S_1_0_i_a3_0[2]  (.A(Disp_dat[3]), .B(Disp_dat[0]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:378: Cannot find file containing module: 'AO1A'\n    AO1A \\SM_8S_1_i_i_a3[6]  (.A(Disp_dat[0]), .B(Disp_dat[2]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:380: Cannot find file containing module: 'AOI1B'\n    AOI1B \\SM_8S_1_i_i_a3_0[4]  (.A(Disp_dat[2]), .B(Disp_dat[1]), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:382: Cannot find file containing module: 'GND'\n    GND GND_i (.Y(GND));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:383: Cannot find file containing module: 'XOR2'\n    XOR2 \\SM_8S_1_i_0_x2[0]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:385: Cannot find file containing module: 'OA1B'\n    OA1B \\SM_8S_1_i_0[1]  (.A(N_19), .B(\\SM_8S_1_i_0_a3_0[1]_net_1 ), \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:387: Cannot find file containing module: 'VCC'\n    VCC VCC_i_0 (.Y(VCC_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:388: Cannot find file containing module: 'OR2B'\n    OR2B \\SM_8S_1_i_i_1[6]  (.A(N_70), .B(N_15_i), .Y(Seg_c[6]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:389: Cannot find file containing module: 'OR2A'\n    OR2A \\SM_8S_1_i_0_a3_0[0]  (.A(N_19), .B(N_14_i_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:683: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_3[2]  (.A(Q_NS_e2_0_a2_1_0), .B(N_30), .Y(N_40));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:684: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_2[2]  (.A(Q_NS[2]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:686: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[1]  (.A(N_34), .B(Q_NS_e1_0_0), .C(N_39_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:688: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_0[4]  (.A(Q_NS[4]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:690: Cannot find file containing module: 'OR2B'\n    OR2B Q_NS_e1_0_a2_4 (.A(N_30), .B(one_seond_clk_0_Cout), .Y(N_62));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:691: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_1[7]  (.A(Q_NS[7]), .B(Q_NSlde_i_o2tt_m1_0_a2), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:693: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[7]  (.A(N_56), .B(N_58), .C(N_57), .Y(Q_NS_e7));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:694: Cannot find file containing module: 'OR3'\n    OR3 \\Q_NS_RNO_2[3]  (.A(N_19), .B(Q_NS[3]), .C(N_62), .Y(N_44));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:695: Cannot find file containing module: 'OA1'\n    OA1 \\Q_NS_RNO_2[6]  (.A(N_22), .B(Q_NS[5]), .C(Q_NS[6]), .Y(\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:697: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_0[3]  (.A(Q_NS_e3_0_a2_0), .B(N_30), .Y(N_43));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:698: Cannot find file containing module: 'NOR2B'\n    NOR2B \\Q_NS_RNO_3[3]  (.A(Q_NS[3]), .B(N_19), .Y(Q_NS_e3_0_a2_0));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:699: Cannot find file containing module: 'VCC'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:700: Cannot find file containing module: 'NOR2B'\n    NOR2B \\Q_NS_RNO_3[5]  (.A(Q_NS[5]), .B(N_22), .Y(Q_NS_e5_0_a2_0_0));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:701: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNO_0[7]  (.A(N_30), .B(Q_NS[7]), .C(N_26), .Y(N_56));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:702: Cannot find file containing module: 'NOR3'\n    NOR3 \\Q_NS_RNISBRL[6]  (.A(N_22), .B(Q_NS[5]), .C(Q_NS[6]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:704: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[0]  (.D(Q_NS_e0), .CLK(Clk_c), .Q(Q_NS[0]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:705: Cannot find file containing module: 'AO1C'\n    AO1C \\Q_NS_RNO[2]  (.A(N_19), .B(N_24), .C(Q_NS_e2_0_2), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:707: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNIF75S[7]  (.A(one_seond_clk_0_Cout), .B(N_26), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:709: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNO_1[2]  (.A(Green2_c), .B(N_16), .C(N_30), .Y(N_41));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:710: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[7]  (.D(Q_NS_e7), .CLK(Clk_c), .Q(Q_NS[7]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:711: Cannot find file containing module: 'NOR2A'\n    NOR2A Q_NS_e2_0_a2_4_1 (.A(current_state[0]), .B(Red1_c), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:713: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[5]  (.D(Q_NS_e5), .CLK(Clk_c), .Q(Q_NS[5]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:714: Cannot find file containing module: 'NOR3C'\n    NOR3C \\Q_NS_RNO_0[2]  (.A(N_41), .B(Q_NS_e2_0_0), .C(N_39_i), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:716: Cannot find file containing module: 'NOR2'\n    NOR2 un1_Reset_1_i_i_a2 (.A(Ld_i), .B(Reset_c), .Y(N_30));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:717: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[3]  (.A(N_43), .B(N_45), .C(N_44), .Y(Q_NS_e3));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:718: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_0[6]  (.A(Q_NS[6]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:720: Cannot find file containing module: 'OR3A'\n    OR3A \\Q_NS_RNO_2[7]  (.A(N_26), .B(N_62), .C(Q_NS[7]), .Y(N_57));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:721: Cannot find file containing module: 'OA1'\n    OA1 \\Q_NS_RNO_4[2]  (.A(Q_NS[0]), .B(Q_NS[1]), .C(Q_NS[2]), .Y(\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:723: Cannot find file containing module: 'OR3A'\n    OR3A \\Q_NS_RNO_1[5]  (.A(N_24), .B(N_22), .C(Q_NS[5]), .Y(N_51));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:724: Cannot find file containing module: 'AO1C'\n    AO1C \\Q_NS_RNO[6]  (.A(N_62), .B(N_26), .C(Q_NS_e6_0_0), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:726: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_1[6]  (.A(Q_NS_e6_0_a2_0), .B(N_30), .Y(N_54));\n    ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module BIN_to_BCD_BIN_to_BCD_0(
       un1_BIN_to_BCD_0,
       un1_BIN_to_BCD_0_1,
       Q_NS_0
    );
output [3:1] un1_BIN_to_BCD_0;
output [3:0] un1_BIN_to_BCD_0_1;
input  [7:1] Q_NS_0;

    wire \temp_22[7]_net_1 , N_19_i, N_25_i, temp86lto2, CO1, 
        \temp_11_i[0] , \temp_15[1]_net_1 , CO1_0, \temp_7_i[0] , CO2, 
        \temp_7[1]_net_1 , \temp_7[2]_net_1 , \temp_11[1]_net_1 , 
        \temp_11[2]_net_1 , \temp_22[5]_net_1 , \temp_15[2]_net_1 , 
        CO1_1, \temp_15_i[0] , \temp_19[1]_net_1 , N_31, CO2_0, CO1_2, 
        \temp_22[6]_net_1 , \un1_BIN_to_BCD_0_2[0] , CO1_3, 
        \temp_19_i[0] , \temp_19_i[2] , GND, VCC, GND_0, VCC_0;
    
    OR2B un32_temp_1_CO2 (.A(CO1_0), .B(\temp_7[1]_net_1 ), .Y(CO2));
    AX1D \temp_15[1]  (.A(Q_NS_0[3]), .B(N_25_i), .C(\temp_11_i[0] ), 
        .Y(\temp_15[1]_net_1 ));
    XOR2 \temp_15[0]  (.A(Q_NS_0[3]), .B(N_25_i), .Y(\temp_15_i[0] ));
    NOR2A \temp_22[6]  (.A(temp86lto2), .B(N_19_i), .Y(
        \temp_22[6]_net_1 ));
    XOR2 \temp_7[0]  (.A(Q_NS_0[5]), .B(temp86lto2), .Y(\temp_7_i[0] ));
    VCC VCC_i (.Y(VCC));
    XNOR2 un32_temp_1_SUM3_0 (.A(CO2), .B(\temp_7[2]_net_1 ), .Y(
        N_19_i));
    AX1 \temp[5]  (.A(N_31), .B(\un1_BIN_to_BCD_0_2[0] ), .C(
        \temp_22[5]_net_1 ), .Y(un1_BIN_to_BCD_0_1[2]));
    AX1D \temp_11[1]  (.A(Q_NS_0[4]), .B(N_19_i), .C(\temp_7_i[0] ), 
        .Y(\temp_11[1]_net_1 ));
    AX1E un64_temp_1_SUM3_0 (.A(\temp_15[1]_net_1 ), .B(CO1_1), .C(
        \temp_15[2]_net_1 ), .Y(N_31));
    OR2 un104_temp_1_CO1 (.A(\temp_22[5]_net_1 ), .B(N_31), .Y(CO1_2));
    OR2B un104_temp_1_CO2 (.A(CO1_2), .B(\temp_22[6]_net_1 ), .Y(CO2_0)
        );
    AX1A \temp[1]  (.A(Q_NS_0[1]), .B(un1_BIN_to_BCD_0_1[0]), .C(
        \temp_19_i[0] ), .Y(un1_BIN_to_BCD_0[2]));
    OR2A un92_temp_1_CO1 (.A(\temp_19_i[0] ), .B(Q_NS_0[1]), .Y(CO1_3));
    AXOI4 \temp_22[5]  (.A(N_19_i), .B(N_25_i), .C(temp86lto2), .Y(
        \temp_22[5]_net_1 ));
    AX1A \temp_19[1]  (.A(Q_NS_0[2]), .B(N_31), .C(\temp_15_i[0] ), .Y(
        \temp_19[1]_net_1 ));
    MX2B \temp[2]  (.A(\temp_19[1]_net_1 ), .B(\temp_19_i[2] ), .S(
        CO1_3), .Y(un1_BIN_to_BCD_0[3]));
    OR2A un64_temp_1_CO1 (.A(\temp_15_i[0] ), .B(Q_NS_0[2]), .Y(CO1_1));
    XNOR2 un104_temp_1_SUM3_0 (.A(CO2_0), .B(\temp_22[7]_net_1 ), .Y(
        \un1_BIN_to_BCD_0_2[0] ));
    GND GND_i (.Y(GND));
    OA1A \temp_7[1]  (.A(Q_NS_0[7]), .B(Q_NS_0[5]), .C(Q_NS_0[6]), .Y(
        \temp_7[1]_net_1 ));
    AX1E un92_temp_1_SUM3_0 (.A(\temp_19[1]_net_1 ), .B(CO1_3), .C(
        \temp_19_i[2] ), .Y(un1_BIN_to_BCD_0_1[0]));
    MX2 \temp[6]  (.A(\temp_22[6]_net_1 ), .B(\temp_22[7]_net_1 ), .S(
        CO1_2), .Y(un1_BIN_to_BCD_0_1[3]));
    XOR2 \temp[0]  (.A(Q_NS_0[1]), .B(un1_BIN_to_BCD_0_1[0]), .Y(
        un1_BIN_to_BCD_0[1]));
    XOR2 \temp[4]  (.A(\un1_BIN_to_BCD_0_2[0] ), .B(N_31), .Y(
        un1_BIN_to_BCD_0_1[1]));
    MX2A \temp_19[2]  (.A(\temp_15[1]_net_1 ), .B(\temp_15[2]_net_1 ), 
        .S(CO1_1), .Y(\temp_19_i[2] ));
    OAI1 un15_temp_1_CO2 (.A(Q_NS_0[5]), .B(Q_NS_0[6]), .C(Q_NS_0[7]), 
        .Y(temp86lto2));
    OR2A un32_temp_1_CO1 (.A(\temp_7_i[0] ), .B(Q_NS_0[4]), .Y(CO1_0));
    NOR3B \temp_22[7]  (.A(N_19_i), .B(N_25_i), .C(temp86lto2), .Y(
        \temp_22[7]_net_1 ));
    MX2A \temp_11[2]  (.A(\temp_7[1]_net_1 ), .B(\temp_7[2]_net_1 ), 
        .S(CO1_0), .Y(\temp_11[2]_net_1 ));
    AX1C un48_temp_1_SUM3_0 (.A(\temp_11[1]_net_1 ), .B(CO1), .C(
        \temp_11[2]_net_1 ), .Y(N_25_i));
    OR2A un48_temp_1_CO1 (.A(\temp_11_i[0] ), .B(Q_NS_0[3]), .Y(CO1));
    OR2B \temp_7[2]  (.A(Q_NS_0[7]), .B(temp86lto2), .Y(
        \temp_7[2]_net_1 ));
    XOR2 \temp_11[0]  (.A(Q_NS_0[4]), .B(N_19_i), .Y(\temp_11_i[0] ));
    XNOR2 \temp_19[0]  (.A(Q_NS_0[2]), .B(N_31), .Y(\temp_19_i[0] ));
    MX2A \temp_15[2]  (.A(\temp_11[1]_net_1 ), .B(\temp_11[2]_net_1 ), 
        .S(CO1), .Y(\temp_15[2]_net_1 ));
    VCC VCC_i_0 (.Y(VCC_0));
    GND GND_i_0 (.Y(GND_0));
    
endmodule
module BIN_to_BCD_BIN_to_BCD_0(
       un1_BIN_to_BCD_0,
       un1_BIN_to_BCD_0_1,
       Q_NS_0
    );

output [3:1] un1_BIN_to_BCD_0;
output [3:0] un1_BIN_to_BCD_0_1;
input  [7:1] Q_NS_0;

    wire \temp_22[7]_net_1 , N_19_i, N_25_i, temp86lto2, CO1, 
        \temp_11_i[0] , \temp_15[1]_net_1 , CO1_0, \temp_7_i[0] , CO2, 
        \temp_7[1]_net_1 , \temp_7[2]_net_1 , \temp_11[1]_net_1 , 
        \temp_11[2]_net_1 , \temp_22[5]_net_1 , \temp_15[2]_net_1 , 
        CO1_1, \temp_15_i[0] , \temp_19[1]_net_1 , N_31, CO2_0, CO1_2, 
        \temp_22[6]_net_1 , \un1_BIN_to_BCD_0_2[0] , CO1_3, 
        \temp_19_i[0] , \temp_19_i[2] , GND, VCC, GND_0, VCC_0;
    
    OR2B un32_temp_1_CO2 (.A(CO1_0), .B(\temp_7[1]_net_1 ), .Y(CO2));
    AX1D \temp_15[1]  (.A(Q_NS_0[3]), .B(N_25_i), .C(\temp_11_i[0] ), 
        .Y(\temp_15[1]_net_1 ));
    XOR2 \temp_15[0]  (.A(Q_NS_0[3]), .B(N_25_i), .Y(\temp_15_i[0] ));
    NOR2A \temp_22[6]  (.A(temp86lto2), .B(N_19_i), .Y(
        \temp_22[6]_net_1 ));
    XOR2 \temp_7[0]  (.A(Q_NS_0[5]), .B(temp86lto2), .Y(\temp_7_i[0] ));
    VCC VCC_i (.Y(VCC));
    XNOR2 un32_temp_1_SUM3_0 (.A(CO2), .B(\temp_7[2]_net_1 ), .Y(
        N_19_i));
    AX1 \temp[5]  (.A(N_31), .B(\un1_BIN_to_BCD_0_2[0] ), .C(
        \temp_22[5]_net_1 ), .Y(un1_BIN_to_BCD_0_1[2]));
    AX1D \temp_11[1]  (.A(Q_NS_0[4]), .B(N_19_i), .C(\temp_7_i[0] ), 
        .Y(\temp_11[1]_net_1 ));
    AX1E un64_temp_1_SUM3_0 (.A(\temp_15[1]_net_1 ), .B(CO1_1), .C(
        \temp_15[2]_net_1 ), .Y(N_31));
    OR2 un104_temp_1_CO1 (.A(\temp_22[5]_net_1 ), .B(N_31), .Y(CO1_2));
    OR2B un104_temp_1_CO2 (.A(CO1_2), .B(\temp_22[6]_net_1 ), .Y(CO2_0)
        );
    AX1A \temp[1]  (.A(Q_NS_0[1]), .B(un1_BIN_to_BCD_0_1[0]), .C(
        \temp_19_i[0] ), .Y(un1_BIN_to_BCD_0[2]));
    OR2A un92_temp_1_CO1 (.A(\temp_19_i[0] ), .B(Q_NS_0[1]), .Y(CO1_3));
    AXOI4 \temp_22[5]  (.A(N_19_i), .B(N_25_i), .C(temp86lto2), .Y(
        \temp_22[5]_net_1 ));
    AX1A \temp_19[1]  (.A(Q_NS_0[2]), .B(N_31), .C(\temp_15_i[0] ), .Y(
        \temp_19[1]_net_1 ));
    MX2B \temp[2]  (.A(\temp_19[1]_net_1 ), .B(\temp_19_i[2] ), .S(
        CO1_3), .Y(un1_BIN_to_BCD_0[3]));
    OR2A un64_temp_1_CO1 (.A(\temp_15_i[0] ), .B(Q_NS_0[2]), .Y(CO1_1));
    XNOR2 un104_temp_1_SUM3_0 (.A(CO2_0), .B(\temp_22[7]_net_1 ), .Y(
        \un1_BIN_to_BCD_0_2[0] ));
    GND GND_i (.Y(GND));
    OA1A \temp_7[1]  (.A(Q_NS_0[7]), .B(Q_NS_0[5]), .C(Q_NS_0[6]), .Y(
        \temp_7[1]_net_1 ));
    AX1E un92_temp_1_SUM3_0 (.A(\temp_19[1]_net_1 ), .B(CO1_3), .C(
        \temp_19_i[2] ), .Y(un1_BIN_to_BCD_0_1[0]));
    MX2 \temp[6]  (.A(\temp_22[6]_net_1 ), .B(\temp_22[7]_net_1 ), .S(
        CO1_2), .Y(un1_BIN_to_BCD_0_1[3]));
    XOR2 \temp[0]  (.A(Q_NS_0[1]), .B(un1_BIN_to_BCD_0_1[0]), .Y(
        un1_BIN_to_BCD_0[1]));
    XOR2 \temp[4]  (.A(\un1_BIN_to_BCD_0_2[0] ), .B(N_31), .Y(
        un1_BIN_to_BCD_0_1[1]));
    MX2A \temp_19[2]  (.A(\temp_15[1]_net_1 ), .B(\temp_15[2]_net_1 ), 
        .S(CO1_1), .Y(\temp_19_i[2] ));
    OAI1 un15_temp_1_CO2 (.A(Q_NS_0[5]), .B(Q_NS_0[6]), .C(Q_NS_0[7]), 
        .Y(temp86lto2));
    OR2A un32_temp_1_CO1 (.A(\temp_7_i[0] ), .B(Q_NS_0[4]), .Y(CO1_0));
    NOR3B \temp_22[7]  (.A(N_19_i), .B(N_25_i), .C(temp86lto2), .Y(
        \temp_22[7]_net_1 ));
    MX2A \temp_11[2]  (.A(\temp_7[1]_net_1 ), .B(\temp_7[2]_net_1 ), 
        .S(CO1_0), .Y(\temp_11[2]_net_1 ));
    AX1C un48_temp_1_SUM3_0 (.A(\temp_11[1]_net_1 ), .B(CO1), .C(
        \temp_11[2]_net_1 ), .Y(N_25_i));
    OR2A un48_temp_1_CO1 (.A(\temp_11_i[0] ), .B(Q_NS_0[3]), .Y(CO1));
    OR2B \temp_7[2]  (.A(Q_NS_0[7]), .B(temp86lto2), .Y(
        \temp_7[2]_net_1 ));
    XOR2 \temp_11[0]  (.A(Q_NS_0[4]), .B(N_19_i), .Y(\temp_11_i[0] ));
    XNOR2 \temp_19[0]  (.A(Q_NS_0[2]), .B(N_31), .Y(\temp_19_i[0] ));
    MX2A \temp_15[2]  (.A(\temp_11[1]_net_1 ), .B(\temp_11[2]_net_1 ), 
        .S(CO1), .Y(\temp_15[2]_net_1 ));
    VCC VCC_i_0 (.Y(VCC_0));
    GND GND_i_0 (.Y(GND_0));
    
endmodule