data/full_repos/permissive/217768747/divide_testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/217768747/divide_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/217768747/divide_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/217768747/divide_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n#40\n^\n%Warning-STMTDLY: data/full_repos/permissive/217768747/divide_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/217768747/divide_testbench.v:8: Cannot find file containing module: \'divison\'\ndivison DUT(.page_rank(page_rank),.out_deg(out_deg),.clk(clk),.reset(reset),.quotient(quotient),.done(done));\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/divison\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/divison.v\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/divison.sv\n             divison\n             divison.v\n             divison.sv\n             obj_dir/divison\n             obj_dir/divison.v\n             obj_dir/divison.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module divide_tb;
reg [31:0] page_rank;
reg [31:0] out_deg;
wire [31:0] quotient;
reg clk=0;
reg reset;
wire done;
divison DUT(.page_rank(page_rank),.out_deg(out_deg),.clk(clk),.reset(reset),.quotient(quotient),.done(done));
initial begin
page_rank=32'b0100;
out_deg=32'b0010;
reset=1;
#40
$display(quotient);
$display("done", done);
page_rank=32'b0100;
out_deg=32'b0001;
reset=1;
#40
$display(quotient);
$display("done", done);
page_rank=32'b0110;
out_deg=32'b0100;
reset=1;
#40
$display(quotient);
$display("done", done);
$finish;
end
always #1 clk=~clk;
endmodule
module divide_tb;

reg [31:0] page_rank;
reg [31:0] out_deg;
wire [31:0] quotient;
reg clk=0;
reg reset;
wire done;
divison DUT(.page_rank(page_rank),.out_deg(out_deg),.clk(clk),.reset(reset),.quotient(quotient),.done(done));
initial begin
page_rank=32'b0100;
out_deg=32'b0010;
reset=1;
#40
$display(quotient);
$display("done", done);
page_rank=32'b0100;
out_deg=32'b0001;
reset=1;
#40
$display(quotient);
$display("done", done);
page_rank=32'b0110;
out_deg=32'b0100;
reset=1;
#40
$display(quotient);
$display("done", done);
$finish;
end
always #1 clk=~clk;
endmodule