data/full_repos/permissive/124999927/mem/fifo_sync.v
data/verilator_xmls/713f788a-cf90-4572-a9e6-6dde8f6a8853.xml
module fifo_sync(
  clk,
  aresetn,


  data_wr,
  wr_en,


  data_rd,
  rd_en,


  data_count,
  full,
  overflow,
  empty,
  underflow
);
  parameter DATA_W = 8;
  parameter SIZE = 32;

  localparam SIZE_W = $clog2(SIZE) + 1;
  localparam POINTER_W = $clog2(SIZE);

  input clk;
  input aresetn;

  input [DATA_W - 1:0] data_wr;
  input wr_en;

  output reg [DATA_W - 1:0] data_rd;
  input rd_en;

  output reg [SIZE_W - 1:0] data_count;
  output full;
  output reg overflow;
  output empty;
  output reg underflow;

  reg [DATA_W - 1:0] data [0:SIZE - 1];
  reg [POINTER_W - 1:0] head;
  reg [POINTER_W - 1:0] tail;


  assign full = data_count == SIZE;
  assign empty = data_count == 0;

  integer i;
  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin
      for(i = 0 ; i < SIZE; i = i + 1) begin
        data[i] <= 0;
      end

      data_rd <= 0;
      data_count <= 0;
      overflow <= 0;
      underflow <= 0;

      head <= 0;
      tail <= 0;
    end else begin

      overflow <= 0;
      underflow <= 0;


      if(rd_en == 1) begin

        if(empty == 1) begin
          underflow <= 1;
        end else begin
          data_rd <= data[tail];
          data_count <= data_count - 1;
          tail <= tail + 1;
        end
      end


      if(wr_en == 1) begin

        if(full == 1) begin
          overflow <= 1;

          tail <= tail + 1;
        end else begin
          data_count <= data_count + 1;
        end


        data[head] <= data_wr;
        head <= head + 1;
      end

      if(rd_en == 1 && wr_en == 1) begin
        data_count <= data_count;
      end
    end
  end
endmodule
module fifo_sync(
  clk,
  aresetn,


  data_wr,
  wr_en,


  data_rd,
  rd_en,


  data_count,
  full,
  overflow,
  empty,
  underflow
);

  parameter DATA_W = 8;
  parameter SIZE = 32;

  localparam SIZE_W = $clog2(SIZE) + 1;
  localparam POINTER_W = $clog2(SIZE);

  input clk;
  input aresetn;

  input [DATA_W - 1:0] data_wr;
  input wr_en;

  output reg [DATA_W - 1:0] data_rd;
  input rd_en;

  output reg [SIZE_W - 1:0] data_count;
  output full;
  output reg overflow;
  output empty;
  output reg underflow;

  reg [DATA_W - 1:0] data [0:SIZE - 1];
  reg [POINTER_W - 1:0] head;
  reg [POINTER_W - 1:0] tail;


  assign full = data_count == SIZE;
  assign empty = data_count == 0;

  integer i;
  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin
      for(i = 0 ; i < SIZE; i = i + 1) begin
        data[i] <= 0;
      end

      data_rd <= 0;
      data_count <= 0;
      overflow <= 0;
      underflow <= 0;

      head <= 0;
      tail <= 0;
    end else begin

      overflow <= 0;
      underflow <= 0;


      if(rd_en == 1) begin

        if(empty == 1) begin
          underflow <= 1;
        end else begin
          data_rd <= data[tail];
          data_count <= data_count - 1;
          tail <= tail + 1;
        end
      end


      if(wr_en == 1) begin

        if(full == 1) begin
          overflow <= 1;

          tail <= tail + 1;
        end else begin
          data_count <= data_count + 1;
        end


        data[head] <= data_wr;
        head <= head + 1;
      end

      if(rd_en == 1 && wr_en == 1) begin
        data_count <= data_count;
      end
    end
  end
endmodule