data/full_repos/permissive/143278/ivltests/credence20041209.v
 line:78: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/credence20041209.v:78: Unsupported: Ignoring delay on this delayed statement.\n   #10000 $display("This test doesn\'t check itself.");\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:26: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          start_edge = ( v_value[0] * 1.95)\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:27: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          + ( v_value[1] * 3.9 )\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:28: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          + ( v_value[2] * 7.8 )\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:29: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          + ( v_value[3] * 15.6 )\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:30: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          + ( v_value[4] * 31.2 )\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:31: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          + ( v_value[5] * 62.5 )\n                     ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vtest;

wire vout0, vout1, vout2, vout3, vout4, vout5, vout6, vout7, vout8, vout9;
wire vout10, vout11, vout12, vout13, vout14, vout15, vout16, vout17,
vout18, vout19;

reg  clk, bit0;

verr v0     (clk, vout0);
verr v1     (clk, vout1);
verr v2     (clk, vout2);
verr v3     (clk, vout3);
verr v4     (clk, vout4);
verr v5     (clk, vout5);
verr v6     (clk, vout6);
verr v7     (clk, vout7);
verr v8     (clk, vout8);
verr v9     (clk, vout9);
verr v10     (clk, vout10);
verr v11     (clk, vout11);
verr v12     (clk, vout12);
verr v13     (clk, vout13);
verr v14     (clk, vout14);
verr v15     (clk, vout15);
verr v16     (clk, vout16);
verr v17     (clk, vout17);
verr v18     (clk, vout18);
verr v19     (clk, vout19);

initial begin
   #10000 $display("This test doesn't check itself.");
   $display("PASSED");
end

endmodule
module vtest;


wire vout0, vout1, vout2, vout3, vout4, vout5, vout6, vout7, vout8, vout9;
wire vout10, vout11, vout12, vout13, vout14, vout15, vout16, vout17,
vout18, vout19;

reg  clk, bit0;

verr v0     (clk, vout0);
verr v1     (clk, vout1);
verr v2     (clk, vout2);
verr v3     (clk, vout3);
verr v4     (clk, vout4);
verr v5     (clk, vout5);
verr v6     (clk, vout6);
verr v7     (clk, vout7);
verr v8     (clk, vout8);
verr v9     (clk, vout9);
verr v10     (clk, vout10);
verr v11     (clk, vout11);
verr v12     (clk, vout12);
verr v13     (clk, vout13);
verr v14     (clk, vout14);
verr v15     (clk, vout15);
verr v16     (clk, vout16);
verr v17     (clk, vout17);
verr v18     (clk, vout18);
verr v19     (clk, vout19);

initial begin
   #10000 $display("This test doesn't check itself.");
   $display("PASSED");
end

endmodule