data/full_repos/permissive/118800618/mulit_ctrl.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/f7625cd9-a9e3-4255-8a19-0fcad433f1f7.xml
module ctrl(input  clk,
				input  reset,
				input  [31:0] Inst_in,
				input  zero,
				input  overflow,
				input  MIO_ready,
				output reg MemRead,
				output reg MemWrite,
				output reg[2:0]ALU_operation,
				output [4:0]state_out,
				
				output reg CPU_MIO,
				output reg IorD,
				output reg IRWrite,
				output reg [1:0]RegDst,
				output reg RegWrite,
				output reg [1:0]MemtoReg,
				output reg ALUSrcA,
				output reg [1:0]ALUSrcB,
				output reg [1:0]PCSource,
				output reg PCWrite,
				output reg PCWriteCond,
				output reg Branch
				);
				
				

	reg [4:0] state;
	reg [1:0] ALUop;
	
			



			

	`define Datapath_signals {PCWrite, PCWriteCond, IorD, MemRead, MemWrite, IRWrite, MemtoReg, PCSource, ALUSrcB, ALUSrcA, RegWrite, RegDst, CPU_MIO, ALUop}

	parameter 	AND = 3'b000, OR = 3'b001, ADD = 3'b010, SUB = 3'b110,
					NOR = 3'b100,SLT = 3'b111, XOR = 3'b011, SRL = 3'b101;
	
	assign state_out = state;
	
	

	always @(posedge clk or posedge reset) begin
			if(reset == 1) state <= 0;
			else
				case(state)
					0:	if(MIO_ready) state <= 1;
							else state <= 0;
					1:	case(Inst_in[31:26])
								6'b000000: if
												(Inst_in[5:0] == 6'b001000) state <= 14;
											  else 
												state <= 6;
								6'b100011: state <= 3;
								6'b101011: state <= 3;
								6'b000100: state <= 3;
								6'b000101: state <= 3;
								6'b000010: state <= 9;
								6'b001000: state <= 10;
								6'b001100: state <= 10;
								6'b001101: state <= 10;
								6'b001110: state <= 10;
								6'b001010: state <= 10;
								6'b001111: state <= 12;
								6'b000011: state <= 15;
								default: state <= 16;
							endcase
					6: 	state <= 7;
					3:
							case(Inst_in[31:26])
								6'b100011: state <= 5;
								6'b101011: state <= 5;
								default: state <= 16;
							endcase
							
							
					5: 	state <= 4;
					10:	state <= 11;
					

					4: 	state <= 0;
					5: 	state <= 0;
					7:		state <= 0;
					8:		state <= 0;
					9:		state <= 0;
					
					11:	state <= 0;
					12:	state <= 0;
					13:	state <= 0;
					14:	state <= 0;
					15:	state <= 0;
					16: 	state <= 16;
					default: state <= 16;
				endcase
	end
	

	
	always @* begin
		case(state)
			0:		begin `Datapath_signals <= 19'b10010_10000_0100_001_00;
								Branch = 0;
								ALU_operation <= ADD; end
			1:		begin `Datapath_signals <= 19'b00000_00000_1100_000_00;
								ALU_operation <= ADD; end
			2:	begin `Datapath_signals <= 19'b00000_00000_1010_000_00;
								ALU_operation <= ADD; end
			3:	begin `Datapath_signals <= 19'b00110_00000_0000_001_00;
								ALU_operation <= ADD; end
			4:	begin `Datapath_signals <= 19'b00000_00100_0001_000_00;
								ALU_operation <= ADD; end
			5:	begin `Datapath_signals <= 19'b00101_00000_0000_001_00;
								ALU_operation <= ADD; end
			6:	begin `Datapath_signals <= 19'b00000_00000_0010_000_10;
								case(Inst_in[5:0])
									6'b100000: ALU_operation <= ADD;
									6'b100010: ALU_operation <= SUB;
									6'b100100: ALU_operation <= AND;
									6'b100101: ALU_operation <= OR;
									6'b100110: ALU_operation <= XOR;
									6'b100111: ALU_operation <= NOR;
									6'b101010: ALU_operation <= SLT;
									6'b000010: ALU_operation <= SRL;
									default:   ALU_operation <= ADD;
								endcase
						end
			7:		begin `Datapath_signals <= 19'b00000_00000_0011_010_00;
								ALU_operation <= ADD; end
			8:	begin `Datapath_signals <= 19'b01000_00001_0010_000_01;
								Branch = 1;
								ALU_operation <= SUB; end
			9:	begin `Datapath_signals <= 19'b10000_00010_0000_000_00;
								ALU_operation <= ADD; end
			10:	begin `Datapath_signals <= 19'b00000_00000_1010_000_11;
								case(Inst_in[31:26])
									6'b001000: ALU_operation <= ADD;
									6'b001100: ALU_operation <= AND;
									6'b001101: ALU_operation <= OR;
									6'b001110: ALU_operation <= XOR;
									6'b001010: ALU_operation <= SLT;
									default:   ALU_operation <= ADD;
								endcase
						end
			11:		begin `Datapath_signals <= 19'b00000_00000_1011_000_00;
								ALU_operation <= ADD; end
			12:	begin `Datapath_signals <= 19'b00000_01000_0001_000_00;
								ALU_operation <= ADD; end
			13:	begin `Datapath_signals <= 19'b01000_00001_0010_000_01;
								Branch = 0;
								ALU_operation <= SUB; end
			14:	begin `Datapath_signals <= 19'b10000_00011_0010_000_00;
								ALU_operation <= ADD; end
			15:	begin `Datapath_signals <= 19'b10000_01110_0111_100_00;
								ALU_operation <= ADD; end
			default:	begin `Datapath_signals <= 19'b10010_10000_0100_001_00;
								ALU_operation <= ADD; end
		endcase
	end
	
	
endmodule
module ctrl(input  clk,
				input  reset,
				input  [31:0] Inst_in,
				input  zero,
				input  overflow,
				input  MIO_ready,
				output reg MemRead,
				output reg MemWrite,
				output reg[2:0]ALU_operation,
				output [4:0]state_out,
				
				output reg CPU_MIO,
				output reg IorD,
				output reg IRWrite,
				output reg [1:0]RegDst,
				output reg RegWrite,
				output reg [1:0]MemtoReg,
				output reg ALUSrcA,
				output reg [1:0]ALUSrcB,
				output reg [1:0]PCSource,
				output reg PCWrite,
				output reg PCWriteCond,
				output reg Branch
				);

				
				

	reg [4:0] state;
	reg [1:0] ALUop;
	
			



			

	`define Datapath_signals {PCWrite, PCWriteCond, IorD, MemRead, MemWrite, IRWrite, MemtoReg, PCSource, ALUSrcB, ALUSrcA, RegWrite, RegDst, CPU_MIO, ALUop}

	parameter 	AND = 3'b000, OR = 3'b001, ADD = 3'b010, SUB = 3'b110,
					NOR = 3'b100,SLT = 3'b111, XOR = 3'b011, SRL = 3'b101;
	
	assign state_out = state;
	
	

	always @(posedge clk or posedge reset) begin
			if(reset == 1) state <= 0;
			else
				case(state)
					0:	if(MIO_ready) state <= 1;
							else state <= 0;
					1:	case(Inst_in[31:26])
								6'b000000: if
												(Inst_in[5:0] == 6'b001000) state <= 14;
											  else 
												state <= 6;
								6'b100011: state <= 3;
								6'b101011: state <= 3;
								6'b000100: state <= 3;
								6'b000101: state <= 3;
								6'b000010: state <= 9;
								6'b001000: state <= 10;
								6'b001100: state <= 10;
								6'b001101: state <= 10;
								6'b001110: state <= 10;
								6'b001010: state <= 10;
								6'b001111: state <= 12;
								6'b000011: state <= 15;
								default: state <= 16;
							endcase
					6: 	state <= 7;
					3:
							case(Inst_in[31:26])
								6'b100011: state <= 5;
								6'b101011: state <= 5;
								default: state <= 16;
							endcase
							
							
					5: 	state <= 4;
					10:	state <= 11;
					

					4: 	state <= 0;
					5: 	state <= 0;
					7:		state <= 0;
					8:		state <= 0;
					9:		state <= 0;
					
					11:	state <= 0;
					12:	state <= 0;
					13:	state <= 0;
					14:	state <= 0;
					15:	state <= 0;
					16: 	state <= 16;
					default: state <= 16;
				endcase
	end
	

	
	always @* begin
		case(state)
			0:		begin `Datapath_signals <= 19'b10010_10000_0100_001_00;
								Branch = 0;
								ALU_operation <= ADD; end
			1:		begin `Datapath_signals <= 19'b00000_00000_1100_000_00;
								ALU_operation <= ADD; end
			2:	begin `Datapath_signals <= 19'b00000_00000_1010_000_00;
								ALU_operation <= ADD; end
			3:	begin `Datapath_signals <= 19'b00110_00000_0000_001_00;
								ALU_operation <= ADD; end
			4:	begin `Datapath_signals <= 19'b00000_00100_0001_000_00;
								ALU_operation <= ADD; end
			5:	begin `Datapath_signals <= 19'b00101_00000_0000_001_00;
								ALU_operation <= ADD; end
			6:	begin `Datapath_signals <= 19'b00000_00000_0010_000_10;
								case(Inst_in[5:0])
									6'b100000: ALU_operation <= ADD;
									6'b100010: ALU_operation <= SUB;
									6'b100100: ALU_operation <= AND;
									6'b100101: ALU_operation <= OR;
									6'b100110: ALU_operation <= XOR;
									6'b100111: ALU_operation <= NOR;
									6'b101010: ALU_operation <= SLT;
									6'b000010: ALU_operation <= SRL;
									default:   ALU_operation <= ADD;
								endcase
						end
			7:		begin `Datapath_signals <= 19'b00000_00000_0011_010_00;
								ALU_operation <= ADD; end
			8:	begin `Datapath_signals <= 19'b01000_00001_0010_000_01;
								Branch = 1;
								ALU_operation <= SUB; end
			9:	begin `Datapath_signals <= 19'b10000_00010_0000_000_00;
								ALU_operation <= ADD; end
			10:	begin `Datapath_signals <= 19'b00000_00000_1010_000_11;
								case(Inst_in[31:26])
									6'b001000: ALU_operation <= ADD;
									6'b001100: ALU_operation <= AND;
									6'b001101: ALU_operation <= OR;
									6'b001110: ALU_operation <= XOR;
									6'b001010: ALU_operation <= SLT;
									default:   ALU_operation <= ADD;
								endcase
						end
			11:		begin `Datapath_signals <= 19'b00000_00000_1011_000_00;
								ALU_operation <= ADD; end
			12:	begin `Datapath_signals <= 19'b00000_01000_0001_000_00;
								ALU_operation <= ADD; end
			13:	begin `Datapath_signals <= 19'b01000_00001_0010_000_01;
								Branch = 0;
								ALU_operation <= SUB; end
			14:	begin `Datapath_signals <= 19'b10000_00011_0010_000_00;
								ALU_operation <= ADD; end
			15:	begin `Datapath_signals <= 19'b10000_01110_0111_100_00;
								ALU_operation <= ADD; end
			default:	begin `Datapath_signals <= 19'b10010_10000_0100_001_00;
								ALU_operation <= ADD; end
		endcase
	end
	
	
endmodule