data/full_repos/permissive/188595972/src/lib.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/188595972/src/lib.v:31: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'InputToASCII\'\nmodule InputToASCII(keyboard,ascii,e);\n       ^~~~~~~~~~~~\n                                                                    : ... Top module \'EightSegDisplayment\'\nmodule EightSegDisplayment(segmentSelect,bitSelect_m,data,clk,rst_n);\n       ^~~~~~~~~~~~~~~~~~~\n                                                                    : ... Top module \'KeyboardScaner\'\nmodule KeyboardScaner(Yin,clk,rst_n,Xout,data);\n       ^~~~~~~~~~~~~~\n                                                                    : ... Top module \'SerialClockModule\'\nmodule SerialClockModule(e,clk,rst_n,out,half);\n       ^~~~~~~~~~~~~~~~~\n                                                                    : ... Top module \'AShiftReg\'\nmodule AShiftReg(Di,D,e,set,clk,rst_n,Q);\n       ^~~~~~~~~\n                                                                    : ... Top module \'NegedgeDetector\'\nmodule NegedgeDetector(i,clk,rst_n,neg);\n       ^~~~~~~~~~~~~~~\n                                                                    : ... Top module \'JK_FF\'\nmodule JK_FF(J,K,clk,rst_n,Q);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/188595972/src/lib.v:182: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                  : ... In instance NegedgeDetector\n        if(!rst_n) negCache<=2\'d0;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/188595972/src/lib.v:187: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                  : ... In instance NegedgeDetector\n        Y={negCache[0],|antiVibrationQ};\n         ^\n%Warning-WIDTH: data/full_repos/permissive/188595972/src/lib.v:47: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'num\' generates 2 bits.\n                                                                 : ... In instance EightSegDisplayment\n        case(num)\n        ^~~~\n%Error: Exiting due to 4 warning(s)\n'
module EightSegDisplayment(segmentSelect,bitSelect_m,data,clk,rst_n);
    input clk,rst_n;
    input [15:0]data;
    output [6:0]segmentSelect;
    output [3:0]bitSelect_m;
    
    reg [3:0]numSelected;
    wire [6:0]segmentSelect_n;
    wire [1:0]num;
    wire [3:0]coverCode;
    wire [3:0]bitSelect;
    assign segmentSelect=~segmentSelect_n;
    assign coverCode=~{|data[15:12],|data[15:8],|data[15:4],1'b1};
    assign bitSelect_m=coverCode|bitSelect;
    always@(num or data)
      begin
        case(num)
          4'b00:numSelected=data[15:12];
          4'b01:numSelected=data[11:8];
          4'b10:numSelected=data[7:4];
          4'b11:numSelected=data[3:0];
        endcase
      end
    SequenceSingalGenerator ssg(clk,rst_n,num,bitSelect);
    ToDisplay bcdtd(numSelected,segmentSelect_n);
    endmodule
module EightSegDisplayment(segmentSelect,bitSelect_m,data,clk,rst_n);

    input clk,rst_n;
    input [15:0]data;
    output [6:0]segmentSelect;
    output [3:0]bitSelect_m;
    
    reg [3:0]numSelected;
    wire [6:0]segmentSelect_n;
    wire [1:0]num;
    wire [3:0]coverCode;
    wire [3:0]bitSelect;
    assign segmentSelect=~segmentSelect_n;
    assign coverCode=~{|data[15:12],|data[15:8],|data[15:4],1'b1};
    assign bitSelect_m=coverCode|bitSelect;
    always@(num or data)
      begin
        case(num)
          4'b00:numSelected=data[15:12];
          4'b01:numSelected=data[11:8];
          4'b10:numSelected=data[7:4];
          4'b11:numSelected=data[3:0];
        endcase
      end
    SequenceSingalGenerator ssg(clk,rst_n,num,bitSelect);
    ToDisplay bcdtd(numSelected,segmentSelect_n);
    endmodule