data/full_repos/permissive/156463370/MAC.v
data/verilator_xmls/00692fc4-64ee-4ac5-b391-dd53cc446e7d.xml
module MAC (
    input logic Clock_50,
    input logic Resetn,
    input logic clear,
    input logic [31:0] operand1,
    input logic [31:0] operand2,
    output logic [63:0] accumulate,
    output logic [63:0] multOut
);

assign multOut = operand1 *operand2;

always_ff @ (posedge Clock_50 or negedge Resetn) begin
	if ((Resetn == 1'b0) | (clear == 1'b0)) begin
		accumulate <= 64'd0;
	end else begin
        accumulate <= accumulate + multOut;
    end
end

endmodule
module MAC (
    input logic Clock_50,
    input logic Resetn,
    input logic clear,
    input logic [31:0] operand1,
    input logic [31:0] operand2,
    output logic [63:0] accumulate,
    output logic [63:0] multOut
);


assign multOut = operand1 *operand2;

always_ff @ (posedge Clock_50 or negedge Resetn) begin
	if ((Resetn == 1'b0) | (clear == 1'b0)) begin
		accumulate <= 64'd0;
	end else begin
        accumulate <= accumulate + multOut;
    end
end

endmodule