data/full_repos/permissive/179980995/FPU/fpu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/179980995/FPU/fpu_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100 clock = ~clock;  \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/179980995/FPU/fpu_tb.v:35: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fpu_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/179980995/FPU/fpu_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,clock, a, b, op, out);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/179980995/FPU/fpu_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#400  \n^\n%Warning-STMTDLY: data/full_repos/permissive/179980995/FPU/fpu_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#400  \n^\n%Warning-STMTDLY: data/full_repos/permissive/179980995/FPU/fpu_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#400  \n^\n%Warning-STMTDLY: data/full_repos/permissive/179980995/FPU/fpu_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n#400  \n^\n%Warning-STMTDLY: data/full_repos/permissive/179980995/FPU/fpu_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n#400  \n^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fpu_tb ();


 reg clock;
 reg [31:0] a, b;
 reg [1:0] op;
 reg [31:0] correct;


 wire [31:0] out;
 wire [49:0] pro;



 fpu U1 (
          .clk(clock),
          .A(a),
          .B(b),
          .opcode(op),
          .O(out)
        );


 always
 #100 clock = ~clock;


 initial
 begin
 $dumpfile("fpu_tb.vcd");
 $dumpvars(0,clock, a, b, op, out);
 clock = 0;op = 2'b00;
a = 32'b01110001111000111010000101011001;
b = 32'b11110010010011001010101111101111;
correct = 32'b11110001101101011011011010000101;
#400
if ((correct - out > 2) && (out - correct > 2)) begin
$display ("A      : %b %b %b %h", a[31], a[30:23], a[22:0], a);
$display ("B      : %b %b %b %h", b[31], b[30:23], b[22:0], b);
$display ("Output : %b %b %b %h", out[31], out[30:23], out[22:0], out);
$display ("Correct: %b %b %b %h",correct[31], correct[30:23], correct[22:0], correct); $display();end
a = 32'b11000010001101000010111001000001;
b = 32'b00101110001111001000111101011100;
correct = 32'b11000010001101000010111001000001;
#400
if ((correct - out > 2) && (out - correct > 2)) begin
$display ("A      : %b %b %b %h", a[31], a[30:23], a[22:0], a);
$display ("B      : %b %b %b %h", b[31], b[30:23], b[22:0], b);
$display ("Output : %b %b %b %h", out[31], out[30:23], out[22:0], out);
$display ("Correct: %b %b %b %h",correct[31], correct[30:23], correct[22:0], correct); $display();end
a = 32'b00110110011100110010100111101100;
b = 32'b01010001101010111010000101111110;
correct = 32'b01010001101010111010000101111110;
#400
if ((correct - out > 2) && (out - correct > 2)) begin
$display ("A      : %b %b %b %h", a[31], a[30:23], a[22:0], a);
$display ("B      : %b %b %b %h", b[31], b[30:23], b[22:0], b);
$display ("Output : %b %b %b %h", out[31], out[30:23], out[22:0], out);
$display ("Correct: %b %b %b %h",correct[31], correct[30:23], correct[22:0], correct); $display();end
a = 32'b00010111110010111110101100010001;
b = 32'b00111000010010111101000111010111;
correct = 32'b00111000010010111101000111010111;
#400
if ((correct - out > 2) && (out - correct > 2)) begin
$display ("A      : %b %b %b %h", a[31], a[30:23], a[22:0], a);
$display ("B      : %b %b %b %h", b[31], b[30:23], b[22:0], b);
$display ("Output : %b %b %b %h", out[31], out[30:23], out[22:0], out);
$display ("Correct: %b %b %b %h",correct[31], correct[30:23], correct[22:0], correct); $display();end
a = 32'b10110111011111010001101100111110;
b = 32'b01000101110111101100101001001110;
correct = 32'b01000101110111101100101001001110;
#400
if ((correct - out > 2) && (out - correct > 2)) begin
$display ("A      : %b %b %b %h", a[31], a[30:23], a[22:0], a);
$display ("B      : %b %b %b %h", b[31], b[30:23], b[22:0], b);
$display ("Output : %b %b %b %h", out[31], out[30:23], out[22:0], out);
$display ("Correct: %b %b %b %h",correct[31], correct[30:23], correct[22:0], correct); $display();end
$display ("Done.");
$stop;

 end

endmodule
module fpu_tb ();



 reg clock;
 reg [31:0] a, b;
 reg [1:0] op;
 reg [31:0] correct;


 wire [31:0] out;
 wire [49:0] pro;



 fpu U1 (
          .clk(clock),
          .A(a),
          .B(b),
          .opcode(op),
          .O(out)
        );


 always
 #100 clock = ~clock;


 initial
 begin
 $dumpfile("fpu_tb.vcd");
 $dumpvars(0,clock, a, b, op, out);
 clock = 0;op = 2'b00;
a = 32'b01110001111000111010000101011001;
b = 32'b11110010010011001010101111101111;
correct = 32'b11110001101101011011011010000101;
#400
if ((correct - out > 2) && (out - correct > 2)) begin
$display ("A      : %b %b %b %h", a[31], a[30:23], a[22:0], a);
$display ("B      : %b %b %b %h", b[31], b[30:23], b[22:0], b);
$display ("Output : %b %b %b %h", out[31], out[30:23], out[22:0], out);
$display ("Correct: %b %b %b %h",correct[31], correct[30:23], correct[22:0], correct); $display();end
a = 32'b11000010001101000010111001000001;
b = 32'b00101110001111001000111101011100;
correct = 32'b11000010001101000010111001000001;
#400
if ((correct - out > 2) && (out - correct > 2)) begin
$display ("A      : %b %b %b %h", a[31], a[30:23], a[22:0], a);
$display ("B      : %b %b %b %h", b[31], b[30:23], b[22:0], b);
$display ("Output : %b %b %b %h", out[31], out[30:23], out[22:0], out);
$display ("Correct: %b %b %b %h",correct[31], correct[30:23], correct[22:0], correct); $display();end
a = 32'b00110110011100110010100111101100;
b = 32'b01010001101010111010000101111110;
correct = 32'b01010001101010111010000101111110;
#400
if ((correct - out > 2) && (out - correct > 2)) begin
$display ("A      : %b %b %b %h", a[31], a[30:23], a[22:0], a);
$display ("B      : %b %b %b %h", b[31], b[30:23], b[22:0], b);
$display ("Output : %b %b %b %h", out[31], out[30:23], out[22:0], out);
$display ("Correct: %b %b %b %h",correct[31], correct[30:23], correct[22:0], correct); $display();end
a = 32'b00010111110010111110101100010001;
b = 32'b00111000010010111101000111010111;
correct = 32'b00111000010010111101000111010111;
#400
if ((correct - out > 2) && (out - correct > 2)) begin
$display ("A      : %b %b %b %h", a[31], a[30:23], a[22:0], a);
$display ("B      : %b %b %b %h", b[31], b[30:23], b[22:0], b);
$display ("Output : %b %b %b %h", out[31], out[30:23], out[22:0], out);
$display ("Correct: %b %b %b %h",correct[31], correct[30:23], correct[22:0], correct); $display();end
a = 32'b10110111011111010001101100111110;
b = 32'b01000101110111101100101001001110;
correct = 32'b01000101110111101100101001001110;
#400
if ((correct - out > 2) && (out - correct > 2)) begin
$display ("A      : %b %b %b %h", a[31], a[30:23], a[22:0], a);
$display ("B      : %b %b %b %h", b[31], b[30:23], b[22:0], b);
$display ("Output : %b %b %b %h", out[31], out[30:23], out[22:0], out);
$display ("Correct: %b %b %b %h",correct[31], correct[30:23], correct[22:0], correct); $display();end
$display ("Done.");
$stop;

 end

endmodule