data/full_repos/permissive/174008594/src/tst_6502.v
1: b"%Error: data/full_repos/permissive/174008594/src/tst_6502.v:20: Duplicate declaration of signal: 'CPU_IRQ'\n                                                              : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire CPU_WE, CPU_IRQ;\n                 ^~~~~~~\n        data/full_repos/permissive/174008594/src/tst_6502.v:14: ... Location of original declaration\n    output CPU_IRQ           \n           ^~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module tst_6502(
    input clk,
    input reset,
    
	output reg [7:0] gpio_o,
	input [7:0] gpio_i,
	
	input RX,
	output TX,
    
    output CPU_IRQ
);

    wire [15:0] CPU_AB;
    reg [7:0] CPU_DI;
    wire [7:0] CPU_DO;
    wire CPU_WE, CPU_IRQ;
    cpu ucpu(
        .clk(clk),
        .reset(reset),
        .AB(CPU_AB),
        .DI(CPU_DI),
        .DO(CPU_DO),
        .WE(CPU_WE),
        .IRQ(CPU_IRQ),
        .NMI(1'b0),
        .RDY(1'b1)
    );
    

	wire ram_sel = (CPU_AB[15] == 1'b0) ? 1 : 0;
	wire gpio_sel = (CPU_AB[15:12] == 4'hd) ? 1 : 0;
	wire acia_sel = (CPU_AB[15:12] == 4'he) ? 1 : 0;
	wire rom_sel = (CPU_AB[15:12] == 4'hf) ? 1 : 0;
	

    wire [7:0] ram_do;
    RAM_32kB uram(
        .clk(clk),
        .sel(ram_sel),
        .we(CPU_WE),
        .addr(CPU_AB[14:0]),
        .din(CPU_DO),
        .dout(ram_do)
    );
    

	reg [7:0] gpio_do;
	always @(posedge clk)
		if((CPU_WE == 1'b1) && (gpio_sel == 1'b1))
			gpio_o <= CPU_DO;
	always @(posedge clk)
		gpio_do <= gpio_i;
	

	wire [7:0] acia_do;
	acia uacia(
		.clk(clk),
		.rst(reset),
		.cs(acia_sel),
		.we(CPU_WE),
		.rs(CPU_AB[0]),
		.rx(RX),
		.din(CPU_DO),
		.dout(acia_do),
		.tx(TX),
		.irq(CPU_IRQ)
	);
	

    reg [7:0] rom_mem[4095:0];
	reg [7:0] rom_do;
	initial
        $readmemh("rom.hex",rom_mem);
	always @(posedge clk)
		rom_do <= rom_mem[CPU_AB[11:0]];


	reg [3:0] mux_sel;
	always @(posedge clk)
		mux_sel <= {rom_sel,acia_sel,gpio_sel,ram_sel};
	always @(*)
		casez(mux_sel)
			4'b0001: CPU_DI = ram_do;
			4'b001z: CPU_DI = gpio_do;
			4'b01zz: CPU_DI = acia_do;
			4'b1zzz: CPU_DI = rom_do;
			default: CPU_DI = rom_do;
		endcase
endmodule
module tst_6502(
    input clk,
    input reset,
    
	output reg [7:0] gpio_o,
	input [7:0] gpio_i,
	
	input RX,
	output TX,
    
    output CPU_IRQ
);


    wire [15:0] CPU_AB;
    reg [7:0] CPU_DI;
    wire [7:0] CPU_DO;
    wire CPU_WE, CPU_IRQ;
    cpu ucpu(
        .clk(clk),
        .reset(reset),
        .AB(CPU_AB),
        .DI(CPU_DI),
        .DO(CPU_DO),
        .WE(CPU_WE),
        .IRQ(CPU_IRQ),
        .NMI(1'b0),
        .RDY(1'b1)
    );
    

	wire ram_sel = (CPU_AB[15] == 1'b0) ? 1 : 0;
	wire gpio_sel = (CPU_AB[15:12] == 4'hd) ? 1 : 0;
	wire acia_sel = (CPU_AB[15:12] == 4'he) ? 1 : 0;
	wire rom_sel = (CPU_AB[15:12] == 4'hf) ? 1 : 0;
	

    wire [7:0] ram_do;
    RAM_32kB uram(
        .clk(clk),
        .sel(ram_sel),
        .we(CPU_WE),
        .addr(CPU_AB[14:0]),
        .din(CPU_DO),
        .dout(ram_do)
    );
    

	reg [7:0] gpio_do;
	always @(posedge clk)
		if((CPU_WE == 1'b1) && (gpio_sel == 1'b1))
			gpio_o <= CPU_DO;
	always @(posedge clk)
		gpio_do <= gpio_i;
	

	wire [7:0] acia_do;
	acia uacia(
		.clk(clk),
		.rst(reset),
		.cs(acia_sel),
		.we(CPU_WE),
		.rs(CPU_AB[0]),
		.rx(RX),
		.din(CPU_DO),
		.dout(acia_do),
		.tx(TX),
		.irq(CPU_IRQ)
	);
	

    reg [7:0] rom_mem[4095:0];
	reg [7:0] rom_do;
	initial
        $readmemh("rom.hex",rom_mem);
	always @(posedge clk)
		rom_do <= rom_mem[CPU_AB[11:0]];


	reg [3:0] mux_sel;
	always @(posedge clk)
		mux_sel <= {rom_sel,acia_sel,gpio_sel,ram_sel};
	always @(*)
		casez(mux_sel)
			4'b0001: CPU_DI = ram_do;
			4'b001z: CPU_DI = gpio_do;
			4'b01zz: CPU_DI = acia_do;
			4'b1zzz: CPU_DI = rom_do;
			default: CPU_DI = rom_do;
		endcase
endmodule