data/full_repos/permissive/184916587/ALU_RECV.v
data/verilator_xmls/11c131a4-5f02-45c9-b967-521eab3318de.xml
module slt_32(
	input[31:0] slt_rs1,
	input[31:0] slt_rs2,
	output reg[31:0] slt_rd
);

	always @(*)
	begin
		if(slt_rs1<slt_rs2)
			slt_rd=32'b11111111111111111111111111111111;
		else begin
			slt_rd=32'b00000000000000000000000000000000;
		end
	end
endmodule
module slt_32(
	input[31:0] slt_rs1,
	input[31:0] slt_rs2,
	output reg[31:0] slt_rd
);


	always @(*)
	begin
		if(slt_rs1<slt_rs2)
			slt_rd=32'b11111111111111111111111111111111;
		else begin
			slt_rd=32'b00000000000000000000000000000000;
		end
	end
endmodule