data/full_repos/permissive/143278/ivltests/nblkpush.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nblkpush.v:43: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nblkpush.v:52: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   reg a, b, c, d;

   wire ab = a & b;
   wire abc = ab | c;
   wire abcd = abc & d;

   initial
     begin
	a = 0;
	b = 1;
	c = 0;
	d = 1;
	#1;
	a = 1;
	if (abcd === 1)
	  begin
	     $display("PASSED");
	     $finish;
	  end

	$display("FAILED ab=%b, abc=%b, abcd=%b", ab, abc, abcd);
	#1;
	if (abcd === 1)
	  $display("abcd value changed late");
	else
	  $display("abcd value still wrong");
     end

endmodule
module test;


   reg a, b, c, d;

   wire ab = a & b;
   wire abc = ab | c;
   wire abcd = abc & d;

   initial
     begin
	a = 0;
	b = 1;
	c = 0;
	d = 1;
	#1;
	a = 1;
	if (abcd === 1)
	  begin
	     $display("PASSED");
	     $finish;
	  end

	$display("FAILED ab=%b, abc=%b, abcd=%b", ab, abc, abcd);
	#1;
	if (abcd === 1)
	  $display("abcd value changed late");
	else
	  $display("abcd value still wrong");
     end

endmodule