data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v
1: b'%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:96: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:114: Define or directive not defined: \'`E203_PC_SIZE\'\n input  [`E203_PC_SIZE-1:0] pc_rtvec,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:120: Define or directive not defined: \'`E203_PC_SIZE\'\n output  [`E203_PC_SIZE-1:0] cmt_dpc,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:137: Define or directive not defined: \'`E203_PC_SIZE\'\n input  [`E203_PC_SIZE-1:0] dpc_r     ,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:148: Define or directive not defined: \'`E203_HART_ID_W\'\n input [`E203_HART_ID_W-1:0] core_mhartid,  \n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:156: Define or directive not defined: \'`E203_ADDR_SIZE\'\n input [`E203_ADDR_SIZE-1:0]    clint_region_indic,\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:161: Define or directive not defined: \'`E203_ADDR_SIZE\'\n output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:163: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:164: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:164: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,\n                   ^\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:174: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:176: Define or directive not defined: \'`E203_ADDR_SIZE\'\n input [`E203_ADDR_SIZE-1:0]    plic_region_indic,\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:181: Define or directive not defined: \'`E203_ADDR_SIZE\'\n output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:183: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:184: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:194: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:232: syntax error, unexpected IDENTIFIER\ne203_reset_ctrl #(.MASTER(MASTER)) u_e203_reset_ctrl (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:272: syntax error, unexpected IDENTIFIER\ne203_irq_sync  #(.MASTER(MASTER)) u_e203_irq_sync(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:340: Define or directive not defined: \'`E203_LIRQ_NUM\'\n .lcl_irq_r               (`E203_LIRQ_NUM\'b0), \n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu.v:344: Define or directive not defined: \'`E203_EVT_NUM\'\n .evt_r                   (`E203_EVT_NUM\'b0), \n                           ^~~~~~~~~~~~~\n%Error: Exiting due to 20 error(s)\n'
module e203_cpu #(
	parameter MASTER = 1
)
(
	output inspect_dbg_irq,
	output inspect_core_clk,
	output core_csr_clk,






	output  core_wfi,
	output  tm_stop,
	
	input  [`E203_PC_SIZE-1:0] pc_rtvec,





	output  [`E203_PC_SIZE-1:0] cmt_dpc,
	output  cmt_dpc_ena,

	output  [3-1:0] cmt_dcause,
	output  cmt_dcause_ena,




	output  wr_dcsr_ena    ,
	output  wr_dpc_ena     ,
	output  wr_dscratch_ena,


	output  [32-1:0] wr_csr_nxt    ,

	input  [32-1:0] dcsr_r    ,
	input  [`E203_PC_SIZE-1:0] dpc_r     ,
	input  [32-1:0] dscratch_r,









	input [`E203_HART_ID_W-1:0] core_mhartid,  


	input  ext_irq_a,
	input  sft_irq_a,
	input  tmr_irq_a,

	
	input [`E203_ADDR_SIZE-1:0]    clint_region_indic,
	input                          clint_icb_enable,

	output                         clint_icb_cmd_valid,
	input                          clint_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, 
	output                         clint_icb_cmd_read, 
	output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,
	output                         clint_icb_cmd_lock,
	output                         clint_icb_cmd_excl,
	output [1:0]                   clint_icb_cmd_size,


	input                          clint_icb_rsp_valid,
	output                         clint_icb_rsp_ready,
	input                          clint_icb_rsp_err  ,
	input                          clint_icb_rsp_excl_ok  ,
	input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,

	input [`E203_ADDR_SIZE-1:0]    plic_region_indic,
	input                          plic_icb_enable,

	output                         plic_icb_cmd_valid,
	input                          plic_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, 
	output                         plic_icb_cmd_read, 
	output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,
	output                         plic_icb_cmd_lock,
	output                         plic_icb_cmd_excl,
	output [1:0]                   plic_icb_cmd_size,


	input                          plic_icb_rsp_valid,
	output                         plic_icb_rsp_ready,
	input                          plic_icb_rsp_err  ,
	input                          plic_icb_rsp_excl_ok  ,
	input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,

	input  clk,
	input  rst_n
	);

	wire core_cgstop;

	

	wire core_exu_active;
	wire core_lsu_active;
	wire core_biu_active;
	

	wire rst_core;
	wire clk_core_ifu;
	wire clk_core_exu;
	wire clk_core_lsu;
	wire clk_core_biu;
	







	wire rst_aon;





	wire rst_itcm;



e203_reset_ctrl #(.MASTER(MASTER)) u_e203_reset_ctrl (
	.clk        (clk  ),
	.rst_n      (rst_n    ),

	.rst_sync_n   (rst_sync_n)


);



e203_clk_ctrl u_e203_clk_ctrl(
	.clk          (clk          ),
	.rst_n        (rst_sync_n),
	.test_mode    (1'b0    ),
															
	.core_cgstop   (core_cgstop),
		
	.clk_core_ifu (clk_core_ifu      ),
	.clk_core_exu (clk_core_exu      ),
	.clk_core_lsu (clk_core_lsu      ),
	.clk_core_biu (clk_core_biu      ),







	.core_ifu_active(1'b1),
	.core_exu_active(core_exu_active),
	.core_lsu_active(core_lsu_active),
	.core_biu_active(core_biu_active),
	.core_wfi     (core_wfi ) 
);

	wire ext_irq_r;
	wire sft_irq_r;
	wire tmr_irq_r;

e203_irq_sync  #(.MASTER(MASTER)) u_e203_irq_sync(
	.clk       (clk),
	.rst_n     (rst_sync_n),
											 




	.ext_irq_a   (ext_irq_a),
	.sft_irq_a   (sft_irq_a),
	.tmr_irq_a   (tmr_irq_a),
	.ext_irq_r   (ext_irq_r),
	.sft_irq_r   (sft_irq_r),
	.tmr_irq_r   (tmr_irq_r) 
);



































 
(* DONT_TOUCH = "TRUE" *)
e203_core u_e203_core(


	.core_cgstop             (core_cgstop),
	.tm_stop                 (tm_stop),

	.pc_rtvec                (pc_rtvec),


	.exu_active              (core_exu_active),
	.lsu_active              (core_lsu_active),
	.biu_active              (core_biu_active),
	.core_wfi                (core_wfi),

	.core_mhartid            (core_mhartid),  

	.lcl_irq_r               (`E203_LIRQ_NUM'b0),
	.ext_irq_r               (ext_irq_r),
	.sft_irq_r               (sft_irq_r),
	.tmr_irq_r               (tmr_irq_r),
	.evt_r                   (`E203_EVT_NUM'b0),

	.cmt_dpc                 (cmt_dpc        ),
	.cmt_dpc_ena             (cmt_dpc_ena    ),
	.cmt_dcause              (cmt_dcause     ),
	.cmt_dcause_ena          (cmt_dcause_ena ),

	.wr_dcsr_ena     (wr_dcsr_ena    ),
	.wr_dpc_ena      (wr_dpc_ena     ),
	.wr_dscratch_ena (wr_dscratch_ena),
																	 
	.wr_csr_nxt      (wr_csr_nxt    ),
																	 
	.dcsr_r          (dcsr_r         ),
	.dpc_r           (dpc_r          ),
	.dscratch_r      (dscratch_r     ),
																					 























	








	.plic_icb_enable        (plic_icb_enable),
	.plic_region_indic      (plic_region_indic ),
	.plic_icb_cmd_valid     (plic_icb_cmd_valid),
	.plic_icb_cmd_ready     (plic_icb_cmd_ready),
	.plic_icb_cmd_addr      (plic_icb_cmd_addr ),
	.plic_icb_cmd_read      (plic_icb_cmd_read ),
	.plic_icb_cmd_wdata     (plic_icb_cmd_wdata),
	.plic_icb_cmd_wmask     (plic_icb_cmd_wmask),
	.plic_icb_cmd_lock      (plic_icb_cmd_lock ),
	.plic_icb_cmd_excl      (plic_icb_cmd_excl ),
	.plic_icb_cmd_size      (plic_icb_cmd_size ),
	
	.plic_icb_rsp_valid     (plic_icb_rsp_valid),
	.plic_icb_rsp_ready     (plic_icb_rsp_ready),
	.plic_icb_rsp_err       (plic_icb_rsp_err  ),
	.plic_icb_rsp_excl_ok   (plic_icb_rsp_excl_ok),
	.plic_icb_rsp_rdata     (plic_icb_rsp_rdata),

	.clint_icb_enable        (clint_icb_enable),
	.clint_region_indic      (clint_region_indic ),
	.clint_icb_cmd_valid     (clint_icb_cmd_valid),
	.clint_icb_cmd_ready     (clint_icb_cmd_ready),
	.clint_icb_cmd_addr      (clint_icb_cmd_addr ),
	.clint_icb_cmd_read      (clint_icb_cmd_read ),
	.clint_icb_cmd_wdata     (clint_icb_cmd_wdata),
	.clint_icb_cmd_wmask     (clint_icb_cmd_wmask),
	.clint_icb_cmd_lock      (clint_icb_cmd_lock ),
	.clint_icb_cmd_excl      (clint_icb_cmd_excl ),
	.clint_icb_cmd_size      (clint_icb_cmd_size ),
	
	.clint_icb_rsp_valid     (clint_icb_rsp_valid),
	.clint_icb_rsp_ready     (clint_icb_rsp_ready),
	.clint_icb_rsp_err       (clint_icb_rsp_err  ),
	.clint_icb_rsp_excl_ok   (clint_icb_rsp_excl_ok),
	.clint_icb_rsp_rdata     (clint_icb_rsp_rdata),

	.clk               (clk),
	.clk_core_ifu      (clk_core_ifu      ),
	.clk_core_exu      (clk_core_exu      ),
	.clk_core_lsu      (clk_core_lsu      ),
	.clk_core_biu      (clk_core_biu      ),

	.rst_n             (rst_sync_n) 
);








	assign inspect_dbg_irq = dbg_irq_a;
	assign inspect_core_clk = clk;

endmodule
module e203_cpu #(
	parameter MASTER = 1
)
(
	output inspect_dbg_irq,
	output inspect_core_clk,
	output core_csr_clk,






	output  core_wfi,
	output  tm_stop,
	
	input  [`E203_PC_SIZE-1:0] pc_rtvec,





	output  [`E203_PC_SIZE-1:0] cmt_dpc,
	output  cmt_dpc_ena,

	output  [3-1:0] cmt_dcause,
	output  cmt_dcause_ena,




	output  wr_dcsr_ena    ,
	output  wr_dpc_ena     ,
	output  wr_dscratch_ena,


	output  [32-1:0] wr_csr_nxt    ,

	input  [32-1:0] dcsr_r    ,
	input  [`E203_PC_SIZE-1:0] dpc_r     ,
	input  [32-1:0] dscratch_r,









	input [`E203_HART_ID_W-1:0] core_mhartid,  


	input  ext_irq_a,
	input  sft_irq_a,
	input  tmr_irq_a,

	
	input [`E203_ADDR_SIZE-1:0]    clint_region_indic,
	input                          clint_icb_enable,

	output                         clint_icb_cmd_valid,
	input                          clint_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, 
	output                         clint_icb_cmd_read, 
	output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,
	output                         clint_icb_cmd_lock,
	output                         clint_icb_cmd_excl,
	output [1:0]                   clint_icb_cmd_size,


	input                          clint_icb_rsp_valid,
	output                         clint_icb_rsp_ready,
	input                          clint_icb_rsp_err  ,
	input                          clint_icb_rsp_excl_ok  ,
	input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,

	input [`E203_ADDR_SIZE-1:0]    plic_region_indic,
	input                          plic_icb_enable,

	output                         plic_icb_cmd_valid,
	input                          plic_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, 
	output                         plic_icb_cmd_read, 
	output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,
	output                         plic_icb_cmd_lock,
	output                         plic_icb_cmd_excl,
	output [1:0]                   plic_icb_cmd_size,


	input                          plic_icb_rsp_valid,
	output                         plic_icb_rsp_ready,
	input                          plic_icb_rsp_err  ,
	input                          plic_icb_rsp_excl_ok  ,
	input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,

	input  clk,
	input  rst_n
	);


	wire core_cgstop;

	

	wire core_exu_active;
	wire core_lsu_active;
	wire core_biu_active;
	

	wire rst_core;
	wire clk_core_ifu;
	wire clk_core_exu;
	wire clk_core_lsu;
	wire clk_core_biu;
	







	wire rst_aon;





	wire rst_itcm;



e203_reset_ctrl #(.MASTER(MASTER)) u_e203_reset_ctrl (
	.clk        (clk  ),
	.rst_n      (rst_n    ),

	.rst_sync_n   (rst_sync_n)


);



e203_clk_ctrl u_e203_clk_ctrl(
	.clk          (clk          ),
	.rst_n        (rst_sync_n),
	.test_mode    (1'b0    ),
															
	.core_cgstop   (core_cgstop),
		
	.clk_core_ifu (clk_core_ifu      ),
	.clk_core_exu (clk_core_exu      ),
	.clk_core_lsu (clk_core_lsu      ),
	.clk_core_biu (clk_core_biu      ),







	.core_ifu_active(1'b1),
	.core_exu_active(core_exu_active),
	.core_lsu_active(core_lsu_active),
	.core_biu_active(core_biu_active),
	.core_wfi     (core_wfi ) 
);

	wire ext_irq_r;
	wire sft_irq_r;
	wire tmr_irq_r;

e203_irq_sync  #(.MASTER(MASTER)) u_e203_irq_sync(
	.clk       (clk),
	.rst_n     (rst_sync_n),
											 




	.ext_irq_a   (ext_irq_a),
	.sft_irq_a   (sft_irq_a),
	.tmr_irq_a   (tmr_irq_a),
	.ext_irq_r   (ext_irq_r),
	.sft_irq_r   (sft_irq_r),
	.tmr_irq_r   (tmr_irq_r) 
);



































 
(* DONT_TOUCH = "TRUE" *)
e203_core u_e203_core(


	.core_cgstop             (core_cgstop),
	.tm_stop                 (tm_stop),

	.pc_rtvec                (pc_rtvec),


	.exu_active              (core_exu_active),
	.lsu_active              (core_lsu_active),
	.biu_active              (core_biu_active),
	.core_wfi                (core_wfi),

	.core_mhartid            (core_mhartid),  

	.lcl_irq_r               (`E203_LIRQ_NUM'b0),
	.ext_irq_r               (ext_irq_r),
	.sft_irq_r               (sft_irq_r),
	.tmr_irq_r               (tmr_irq_r),
	.evt_r                   (`E203_EVT_NUM'b0),

	.cmt_dpc                 (cmt_dpc        ),
	.cmt_dpc_ena             (cmt_dpc_ena    ),
	.cmt_dcause              (cmt_dcause     ),
	.cmt_dcause_ena          (cmt_dcause_ena ),

	.wr_dcsr_ena     (wr_dcsr_ena    ),
	.wr_dpc_ena      (wr_dpc_ena     ),
	.wr_dscratch_ena (wr_dscratch_ena),
																	 
	.wr_csr_nxt      (wr_csr_nxt    ),
																	 
	.dcsr_r          (dcsr_r         ),
	.dpc_r           (dpc_r          ),
	.dscratch_r      (dscratch_r     ),
																					 























	








	.plic_icb_enable        (plic_icb_enable),
	.plic_region_indic      (plic_region_indic ),
	.plic_icb_cmd_valid     (plic_icb_cmd_valid),
	.plic_icb_cmd_ready     (plic_icb_cmd_ready),
	.plic_icb_cmd_addr      (plic_icb_cmd_addr ),
	.plic_icb_cmd_read      (plic_icb_cmd_read ),
	.plic_icb_cmd_wdata     (plic_icb_cmd_wdata),
	.plic_icb_cmd_wmask     (plic_icb_cmd_wmask),
	.plic_icb_cmd_lock      (plic_icb_cmd_lock ),
	.plic_icb_cmd_excl      (plic_icb_cmd_excl ),
	.plic_icb_cmd_size      (plic_icb_cmd_size ),
	
	.plic_icb_rsp_valid     (plic_icb_rsp_valid),
	.plic_icb_rsp_ready     (plic_icb_rsp_ready),
	.plic_icb_rsp_err       (plic_icb_rsp_err  ),
	.plic_icb_rsp_excl_ok   (plic_icb_rsp_excl_ok),
	.plic_icb_rsp_rdata     (plic_icb_rsp_rdata),

	.clint_icb_enable        (clint_icb_enable),
	.clint_region_indic      (clint_region_indic ),
	.clint_icb_cmd_valid     (clint_icb_cmd_valid),
	.clint_icb_cmd_ready     (clint_icb_cmd_ready),
	.clint_icb_cmd_addr      (clint_icb_cmd_addr ),
	.clint_icb_cmd_read      (clint_icb_cmd_read ),
	.clint_icb_cmd_wdata     (clint_icb_cmd_wdata),
	.clint_icb_cmd_wmask     (clint_icb_cmd_wmask),
	.clint_icb_cmd_lock      (clint_icb_cmd_lock ),
	.clint_icb_cmd_excl      (clint_icb_cmd_excl ),
	.clint_icb_cmd_size      (clint_icb_cmd_size ),
	
	.clint_icb_rsp_valid     (clint_icb_rsp_valid),
	.clint_icb_rsp_ready     (clint_icb_rsp_ready),
	.clint_icb_rsp_err       (clint_icb_rsp_err  ),
	.clint_icb_rsp_excl_ok   (clint_icb_rsp_excl_ok),
	.clint_icb_rsp_rdata     (clint_icb_rsp_rdata),

	.clk               (clk),
	.clk_core_ifu      (clk_core_ifu      ),
	.clk_core_exu      (clk_core_exu      ),
	.clk_core_lsu      (clk_core_lsu      ),
	.clk_core_biu      (clk_core_biu      ),

	.rst_n             (rst_sync_n) 
);








	assign inspect_dbg_irq = dbg_irq_a;
	assign inspect_core_clk = clk;

endmodule