data/full_repos/permissive/146618947/pipeline_tarea9/testbench.v
 line:30: before: "$"
1: b'%Error: data/full_repos/permissive/146618947/pipeline_tarea9/testbench.v:2: Cannot find include file: tester.v\n`include "tester.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146618947/pipeline_tarea9,data/full_repos/permissive/146618947/tester.v\n             data/full_repos/permissive/146618947/pipeline_tarea9,data/full_repos/permissive/146618947/tester.v.v\n             data/full_repos/permissive/146618947/pipeline_tarea9,data/full_repos/permissive/146618947/tester.v.sv\n             tester.v\n             tester.v.v\n             tester.v.sv\n             obj_dir/tester.v\n             obj_dir/tester.v.v\n             obj_dir/tester.v.sv\n%Error: data/full_repos/permissive/146618947/pipeline_tarea9/testbench.v:3: Cannot find include file: sumador_cond.v\n`include "sumador_cond.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/146618947/pipeline_tarea9/testbench.v:4: Cannot find include file: sumador_est.v\n`include "sumador_est.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/146618947/pipeline_tarea9/testbench.v:5: Cannot find include file: sum_pipe_cond.v\n`include "sum_pipe_cond.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/146618947/pipeline_tarea9/testbench.v:6: Cannot find include file: mycells.v\n`include "mycells.v" \n         ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module testbench;

   wire clk, reset_L;
   wire [3:0] idx_dd_cond, sum30_dd_cond;
   wire [3:0] idx_dd_est, sum30_dd_est;
   wire [3:0] idx, dataA, dataB;

   tester tester_ (
                   .clk (clk),
                   .idx_dd_cond (idx_dd_cond),
                   .idx_dd_est (idx_dd_est),
                   .reset_L (reset_L),
                   .idx (idx),
                   .dataA (dataA),
                   .dataB (dataB),
                   .sum30_dd_cond (sum30_dd_cond),
                   .sum30_dd_est (sum30_dd_est)
                   );

   sumador_cond sc (
                    .clk (clk),
                    .idx_dd (idx_dd_cond),
                    .reset_L (reset_L),
                    .idx (idx),
                    .dataA (dataA),
                    .dataB (dataB),
                    .sum30_dd (sum30_dd_cond)
                    );

   sumador_est se (
                   .clk (clk),
                   .idx_dd (idx_dd_est),
                   .reset_L (reset_L),
                   .idx (idx),
                   .dataA (dataA),
                   .dataB (dataB),
                   .sum30_dd (sum30_dd_est)
                   );

endmodule
module testbench;


   wire clk, reset_L;
   wire [3:0] idx_dd_cond, sum30_dd_cond;
   wire [3:0] idx_dd_est, sum30_dd_est;
   wire [3:0] idx, dataA, dataB;

   tester tester_ (
                   .clk (clk),
                   .idx_dd_cond (idx_dd_cond),
                   .idx_dd_est (idx_dd_est),
                   .reset_L (reset_L),
                   .idx (idx),
                   .dataA (dataA),
                   .dataB (dataB),
                   .sum30_dd_cond (sum30_dd_cond),
                   .sum30_dd_est (sum30_dd_est)
                   );

   sumador_cond sc (
                    .clk (clk),
                    .idx_dd (idx_dd_cond),
                    .reset_L (reset_L),
                    .idx (idx),
                    .dataA (dataA),
                    .dataB (dataB),
                    .sum30_dd (sum30_dd_cond)
                    );

   sumador_est se (
                   .clk (clk),
                   .idx_dd (idx_dd_est),
                   .reset_L (reset_L),
                   .idx (idx),
                   .dataA (dataA),
                   .dataB (dataB),
                   .sum30_dd (sum30_dd_est)
                   );

endmodule