data/full_repos/permissive/129973551/work2/fifo.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/129973551/work2/fifo.sv:40: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                     : ... In instance fifo\ndata_out <= fifo_memo[rd_ptr];\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/129973551/work2/fifo.sv:56: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                     : ... In instance fifo\n data_out <= fifo_memo[wr_ptr];\n                      ^\n%Error: Exiting due to 2 warning(s)\n'
module fifo ( 
       input            wr_clk,
       input            rd_clk,
	   input            rd_sync_cntrl,
	   input			wr_sync_cntrl,
       input            reset_n,
       input            wr,
       input            rd,
       input      [7:0] data_in,
       output reg [7:0] data_out,
       output           empty,
       output           full,
	   output logic [63:0] fifo_counter
       );

	   
	   reg [63:0] rd_ptr, wr_ptr;
	   reg [7:0] fifo_memo[63:0];

assign empty = (fifo_counter == 0); 
assign full = (fifo_counter == 64) ;	   



always_ff@(posedge rd_clk, negedge reset_n)

if(~reset_n)
begin 
fifo_counter <= 0;
data_out <= 0;
end
else if((!full && wr) && (!empty && rd))
fifo_counter <= fifo_counter;
else if (!empty && rd)
begin 
data_out <= fifo_memo[rd_ptr];
fifo_counter <= fifo_counter - 1;
end

always_ff@(posedge wr_clk, negedge reset_n)

if(~reset_n)
begin
fifo_counter <= 0;
data_out <= 0;
end 

else if((!full && wr) && (!empty && rd))
fifo_counter <= fifo_counter;
else if (!full && wr)
begin
 data_out <= fifo_memo[wr_ptr];
 fifo_counter <= fifo_counter + 1;
 end

 
always_ff@(posedge wr_clk, negedge reset_n)

if(~reset_n)
	wr_ptr <= 0;
		


else if(!full && wr)
	
		wr_ptr = wr_ptr + 1;

always_ff@(posedge rd_clk, negedge reset_n)	
if(~reset_n)
			rd_ptr <= 0;	
else if (!empty && rd)
	
		rd_ptr = rd_ptr +1;
		
		
endmodule
module fifo ( 
       input            wr_clk,
       input            rd_clk,
	   input            rd_sync_cntrl,
	   input			wr_sync_cntrl,
       input            reset_n,
       input            wr,
       input            rd,
       input      [7:0] data_in,
       output reg [7:0] data_out,
       output           empty,
       output           full,
	   output logic [63:0] fifo_counter
       );


	   
	   reg [63:0] rd_ptr, wr_ptr;
	   reg [7:0] fifo_memo[63:0];

assign empty = (fifo_counter == 0); 
assign full = (fifo_counter == 64) ;	   



always_ff@(posedge rd_clk, negedge reset_n)

if(~reset_n)
begin 
fifo_counter <= 0;
data_out <= 0;
end
else if((!full && wr) && (!empty && rd))
fifo_counter <= fifo_counter;
else if (!empty && rd)
begin 
data_out <= fifo_memo[rd_ptr];
fifo_counter <= fifo_counter - 1;
end

always_ff@(posedge wr_clk, negedge reset_n)

if(~reset_n)
begin
fifo_counter <= 0;
data_out <= 0;
end 

else if((!full && wr) && (!empty && rd))
fifo_counter <= fifo_counter;
else if (!full && wr)
begin
 data_out <= fifo_memo[wr_ptr];
 fifo_counter <= fifo_counter + 1;
 end

 
always_ff@(posedge wr_clk, negedge reset_n)

if(~reset_n)
	wr_ptr <= 0;
		


else if(!full && wr)
	
		wr_ptr = wr_ptr + 1;

always_ff@(posedge rd_clk, negedge reset_n)	
if(~reset_n)
			rd_ptr <= 0;	
else if (!empty && rd)
	
		rd_ptr = rd_ptr +1;
		
		
endmodule