data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:5: Cannot find include file: sim_exec_report.vh\n`include "sim_exec_report.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate,data/full_repos/permissive/214858095/sim_exec_report.vh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate,data/full_repos/permissive/214858095/sim_exec_report.vh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate,data/full_repos/permissive/214858095/sim_exec_report.vh.sv\n             sim_exec_report.vh\n             sim_exec_report.vh.v\n             sim_exec_report.vh.sv\n             obj_dir/sim_exec_report.vh\n             obj_dir/sim_exec_report.vh.v\n             obj_dir/sim_exec_report.vh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:6: Cannot find include file: sim_clks_rsts.vh\n`include "sim_clks_rsts.vh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:7: Cannot find include file: sim_axis_lib.svh\n`include "sim_axis_lib.svh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:10: Define or directive not defined: \'`TEST_BENCH_INIT\'\n  `TEST_BENCH_INIT("axi_packet_gate_tb", 7, 1);\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:10: syntax error, unexpected \'(\'\n  `TEST_BENCH_INIT("axi_packet_gate_tb", 7, 1);\n                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:12: Define or directive not defined: \'`DEFINE_CLK\'\n  `DEFINE_CLK(clk, CLK_PERIOD, 50);\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:12: syntax error, unexpected \'(\'\n  `DEFINE_CLK(clk, CLK_PERIOD, 50);\n              ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:13: Define or directive not defined: \'`DEFINE_RESET\'\n  `DEFINE_RESET(reset, 0, 100);\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:50: syntax error, unexpected \'@\'\n          @(posedge clk);\n          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:65: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                            : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for Reset");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:65: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for Reset");\n                                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:68: syntax error, unexpected \'@\'\n    while (reset) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:69: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(~reset);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:69: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(~reset);\n                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:74: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                            : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Fill and empty FIFO");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:74: syntax error, unexpected \';\'\n    `TEST_CASE_START("Fill and empty FIFO");\n                                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:81: Define or directive not defined: \'`ASSERT_FATAL\'\n      `ASSERT_FATAL(m_axis.axis.tready, s);\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:81: syntax error, unexpected \',\'\n      `ASSERT_FATAL(m_axis.axis.tready, s);\n                                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:97: syntax error, unexpected \'@\'\n    repeat(MAX_PKT_SIZE) @(posedge clk);\n                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:101: Define or directive not defined: \'`ASSERT_FATAL\'\n      `ASSERT_FATAL(s_axis.axis.tvalid, s);\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:101: syntax error, unexpected \',\'\n      `ASSERT_FATAL(s_axis.axis.tvalid, s);\n                                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:104: Define or directive not defined: \'`ASSERT_FATAL\'\n      `ASSERT_FATAL(check == i, s);\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:104: syntax error, unexpected \',\'\n      `ASSERT_FATAL(check == i, s);\n                              ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:106: Define or directive not defined: \'`ASSERT_FATAL\'\n        `ASSERT_FATAL(last, "tlast not asserted on final word!");\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:106: syntax error, unexpected \',\'\n        `ASSERT_FATAL(last, "tlast not asserted on final word!");\n                          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:108: Define or directive not defined: \'`ASSERT_FATAL\'\n        `ASSERT_FATAL(~last, "tlast asserted prematurely!");\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:108: syntax error, unexpected \',\'\n        `ASSERT_FATAL(~last, "tlast asserted prematurely!");\n                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:111: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:111: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:116: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                             : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Check gating");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:116: syntax error, unexpected \';\'\n    `TEST_CASE_START("Check gating");\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:127: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:128: Define or directive not defined: \'`ASSERT_FATAL\'\n    `ASSERT_FATAL(~s_axis.axis.tvalid, "Saw output before a full packet input");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:128: syntax error, unexpected \',\'\n    `ASSERT_FATAL(~s_axis.axis.tvalid, "Saw output before a full packet input");\n                                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:133: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:134: Define or directive not defined: \'`ASSERT_FATAL\'\n    `ASSERT_FATAL(s_axis.axis.tvalid, "Did not see output even after full packet input");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:134: syntax error, unexpected \',\'\n    `ASSERT_FATAL(s_axis.axis.tvalid, "Did not see output even after full packet input");\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:138: Define or directive not defined: \'`ASSERT_FATAL\'\n      `ASSERT_FATAL(s_axis.axis.tvalid, s);\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:138: syntax error, unexpected \',\'\n      `ASSERT_FATAL(s_axis.axis.tvalid, s);\n                                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:141: Define or directive not defined: \'`ASSERT_FATAL\'\n      `ASSERT_FATAL(check == i, s);\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:141: syntax error, unexpected \',\'\n      `ASSERT_FATAL(check == i, s);\n                              ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:143: Define or directive not defined: \'`ASSERT_FATAL\'\n        `ASSERT_FATAL(last, "tlast not asserted on final word!");\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:143: syntax error, unexpected \',\'\n        `ASSERT_FATAL(last, "tlast not asserted on final word!");\n                          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:145: Define or directive not defined: \'`ASSERT_FATAL\'\n        `ASSERT_FATAL(~last, "tlast asserted prematurely!");\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:145: syntax error, unexpected \',\'\n        `ASSERT_FATAL(~last, "tlast asserted prematurely!");\n                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:148: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:148: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:153: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                             : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Ensure no bleed");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:153: syntax error, unexpected \';\'\n    `TEST_CASE_START("Ensure no bleed");\n                                       ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/axi_packet_gate/axi_packet_gate_tb.sv:169: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module axi_packet_gate_tb();
  `TEST_BENCH_INIT("axi_packet_gate_tb", `NUM_TEST_CASES, `NS_PER_TICK);
  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
  `DEFINE_CLK(clk, CLK_PERIOD, 50);
  `DEFINE_RESET(reset, 0, 100);

  localparam MAX_PKT_SIZE = 64;


  axis_master #(.DWIDTH(32+1)) m_axis (.clk(clk));
  axis_slave #(.DWIDTH(32)) s_axis (.clk(clk));

  axi_packet_gate #(
    .WIDTH(32),
    .SIZE($clog2(MAX_PKT_SIZE)),
    .USE_AS_BUFF(1)
  ) dut (
    .clk(clk), .reset(reset), .clear(1'b0),
    .i_tdata(m_axis.axis.tdata[31:0]),
    .i_tvalid(m_axis.axis.tvalid),
    .i_tlast(m_axis.axis.tlast),
    .i_terror(m_axis.axis.tdata[32]),
    .i_tready(m_axis.axis.tready),
    .o_tdata(s_axis.axis.tdata),
    .o_tvalid(s_axis.axis.tvalid),
    .o_tlast(s_axis.axis.tlast),
    .o_tready(s_axis.axis.tready)
  );


  task random_wait(int unsigned min_cycles, int unsigned max_cycles);
    begin
      int unsigned num_cycles;
      do begin
        num_cycles = $random() & (2**($clog2(max_cycles))-1);
      end while ((num_cycles < min_cycles) || (num_cycles > max_cycles));

      if (num_cycles != 0) begin
        for (int unsigned i = 0; i < num_cycles; i++) begin
          @(posedge clk);
        end
        @(negedge clk);
      end
    end
  endtask

  initial begin : tb_main
    string s;
    logic error, last;
    int cnt, check;


    `TEST_CASE_START("Wait for Reset");
    m_axis.reset();
    s_axis.reset();
    while (reset) @(posedge clk);
    `TEST_CASE_DONE(~reset);


    `TEST_CASE_START("Fill and empty FIFO");
    error = 0;
    last = 0;
    cnt = 0;
    $display("Write %0d words to FIFO", MAX_PKT_SIZE);
    for (int i = 0; i < MAX_PKT_SIZE; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE-1);
      cnt++;
    end
    $display("Done writing to FIFO");
    if (m_axis.axis.tready) begin
      $display("FIFO not full, fill remaining space");

      while (m_axis.axis.tready) begin
        m_axis.push_word({error,cnt}, 0);
        cnt++;
      end
      $display("Done filling remaining space");
      $display("Expected FIFO size: %0d, Actual: %0d",MAX_PKT_SIZE,cnt);
    end

    repeat(MAX_PKT_SIZE) @(posedge clk);
    $display("Empty FIFO and check output");
    for (int i = 0; i < cnt; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == i, s);
      if (i == cnt-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    `TEST_CASE_DONE(1);


    `TEST_CASE_START("Check gating");
    error = 0;
    last = 0;
    cnt = 0;

    $display("Write %0d words to FIFO and check out valid", MAX_PKT_SIZE);
    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
      m_axis.push_word({error,cnt}, 0);
      cnt++;
    end

    repeat(10) @(posedge clk);
    `ASSERT_FATAL(~s_axis.axis.tvalid, "Saw output before a full packet input");
    for (int i = MAX_PKT_SIZE/2; i < MAX_PKT_SIZE; i++) begin
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE-1);
      cnt++;
    end
    repeat(10) @(posedge clk);
    `ASSERT_FATAL(s_axis.axis.tvalid, "Did not see output even after full packet input");
    $display("Empty FIFO and check output");
    for (int i = 0; i < cnt; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == i, s);
      if (i == cnt-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    `TEST_CASE_DONE(1);


    `TEST_CASE_START("Ensure no bleed");
    error = 0;
    last = 0;
    cnt = 0;

    $display("Write %0d words to FIFO (full packet)", MAX_PKT_SIZE/2);
    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
      m_axis.push_word({error,cnt}, i == (MAX_PKT_SIZE/2)-1);
      cnt++;
    end
    $display("Write %0d words to FIFO (partial packet)", MAX_PKT_SIZE/4);
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      m_axis.push_word({error,cnt}, 0);
      cnt++;
    end

    repeat(10) @(posedge clk);
    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == i, s);
      if (i == (MAX_PKT_SIZE/2)-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    repeat(10) @(posedge clk);
    `ASSERT_FATAL(~s_axis.axis.tvalid, "Partial packet bled through with full packet");
    for (int i = MAX_PKT_SIZE/4; i < MAX_PKT_SIZE/2; i++) begin
      m_axis.push_word({error,cnt}, i == (MAX_PKT_SIZE/2)-1);
      cnt++;
    end
    repeat(10) @(posedge clk);
    `ASSERT_FATAL(s_axis.axis.tvalid, "Did not see output even after full packet input");
    $display("Empty FIFO and check output");
    for (int i = MAX_PKT_SIZE/2; i < cnt; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == i, s);
      if (i == cnt-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    `TEST_CASE_DONE(1);


    `TEST_CASE_START("Back to back small packets");
    error = 0;
    last = 0;
    cnt = 0;
    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/2-1);
      cnt++;
    end
    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/2-1);
      cnt++;
    end
    fork
    begin
      for (int k = 0; k < 8; k++) begin
        for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
          m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/2-1);
          cnt++;
        end
      end
    end
    begin
      @(posedge clk);
      @(posedge clk);
      @(posedge clk);
      for (int k = 0; k < 10; k++) begin
        for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
          `ASSERT_FATAL(s_axis.axis.tvalid, "tvalid not asserted!");
          s_axis.pull_word(check, last);
          $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
          `ASSERT_FATAL(check == (i+k*MAX_PKT_SIZE/2), s);
          if (i == MAX_PKT_SIZE/2-1) begin
            `ASSERT_FATAL(last, "tlast not asserted on final word!");
          end else begin
            `ASSERT_FATAL(~last, "tlast asserted prematurely!");
          end
        end
      end
    end
    join
    `TEST_CASE_DONE(1);

    #2000;


    `TEST_CASE_START("Drop error packet");
    cnt = 0;
    $display("Write packet with %0d words to FIFO", MAX_PKT_SIZE/4);
    error = 0;
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/4-1);
      cnt++;
    end
    $display("Write error packet with %0d words to FIFO", MAX_PKT_SIZE/4);
    error = 1;
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/4-1);
      cnt++;
    end
    $display("Write packet with %0d words to FIFO", MAX_PKT_SIZE/4);
    error = 0;
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/4-1);
      cnt++;
    end
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == i, s);
      if (i == MAX_PKT_SIZE/4-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == (i+MAX_PKT_SIZE/2), s);
      if (i == MAX_PKT_SIZE/4-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    `TEST_CASE_DONE(1);

    #2000;


    `TEST_CASE_START("Random read / writes");
    error = 0;
    last = 0;
    cnt = 0;
    fork
    begin
      for (int k = 1; k <= 5000*MAX_PKT_SIZE; k++) begin
        m_axis.push_word({error,k}, (k % 16) == 0);
        random_wait(0,16);
      end
    end
    begin
      for (int k = 1; k <= 5000*MAX_PKT_SIZE; k++) begin
        random_wait(0,16);
        s_axis.pull_word(check, last);
        $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", k, check);
        `ASSERT_FATAL(check == k, s);
        if ((k % 16) == 0) begin
          `ASSERT_FATAL(last, "tlast not asserted!");
        end else begin
          `ASSERT_FATAL(~last, "tlast asserted prematurely!");
        end
      end
    end
    join
    `TEST_CASE_DONE(1);

    `TEST_BENCH_DONE;

  end
endmodule
module axi_packet_gate_tb();

  `TEST_BENCH_INIT("axi_packet_gate_tb", `NUM_TEST_CASES, `NS_PER_TICK);
  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
  `DEFINE_CLK(clk, CLK_PERIOD, 50);
  `DEFINE_RESET(reset, 0, 100);

  localparam MAX_PKT_SIZE = 64;


  axis_master #(.DWIDTH(32+1)) m_axis (.clk(clk));
  axis_slave #(.DWIDTH(32)) s_axis (.clk(clk));

  axi_packet_gate #(
    .WIDTH(32),
    .SIZE($clog2(MAX_PKT_SIZE)),
    .USE_AS_BUFF(1)
  ) dut (
    .clk(clk), .reset(reset), .clear(1'b0),
    .i_tdata(m_axis.axis.tdata[31:0]),
    .i_tvalid(m_axis.axis.tvalid),
    .i_tlast(m_axis.axis.tlast),
    .i_terror(m_axis.axis.tdata[32]),
    .i_tready(m_axis.axis.tready),
    .o_tdata(s_axis.axis.tdata),
    .o_tvalid(s_axis.axis.tvalid),
    .o_tlast(s_axis.axis.tlast),
    .o_tready(s_axis.axis.tready)
  );


  task random_wait(int unsigned min_cycles, int unsigned max_cycles);
    begin
      int unsigned num_cycles;
      do begin
        num_cycles = $random() & (2**($clog2(max_cycles))-1);
      end while ((num_cycles < min_cycles) || (num_cycles > max_cycles));

      if (num_cycles != 0) begin
        for (int unsigned i = 0; i < num_cycles; i++) begin
          @(posedge clk);
        end
        @(negedge clk);
      end
    end
  endtask

  initial begin : tb_main
    string s;
    logic error, last;
    int cnt, check;


    `TEST_CASE_START("Wait for Reset");
    m_axis.reset();
    s_axis.reset();
    while (reset) @(posedge clk);
    `TEST_CASE_DONE(~reset);


    `TEST_CASE_START("Fill and empty FIFO");
    error = 0;
    last = 0;
    cnt = 0;
    $display("Write %0d words to FIFO", MAX_PKT_SIZE);
    for (int i = 0; i < MAX_PKT_SIZE; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE-1);
      cnt++;
    end
    $display("Done writing to FIFO");
    if (m_axis.axis.tready) begin
      $display("FIFO not full, fill remaining space");

      while (m_axis.axis.tready) begin
        m_axis.push_word({error,cnt}, 0);
        cnt++;
      end
      $display("Done filling remaining space");
      $display("Expected FIFO size: %0d, Actual: %0d",MAX_PKT_SIZE,cnt);
    end

    repeat(MAX_PKT_SIZE) @(posedge clk);
    $display("Empty FIFO and check output");
    for (int i = 0; i < cnt; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == i, s);
      if (i == cnt-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    `TEST_CASE_DONE(1);


    `TEST_CASE_START("Check gating");
    error = 0;
    last = 0;
    cnt = 0;

    $display("Write %0d words to FIFO and check out valid", MAX_PKT_SIZE);
    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
      m_axis.push_word({error,cnt}, 0);
      cnt++;
    end

    repeat(10) @(posedge clk);
    `ASSERT_FATAL(~s_axis.axis.tvalid, "Saw output before a full packet input");
    for (int i = MAX_PKT_SIZE/2; i < MAX_PKT_SIZE; i++) begin
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE-1);
      cnt++;
    end
    repeat(10) @(posedge clk);
    `ASSERT_FATAL(s_axis.axis.tvalid, "Did not see output even after full packet input");
    $display("Empty FIFO and check output");
    for (int i = 0; i < cnt; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == i, s);
      if (i == cnt-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    `TEST_CASE_DONE(1);


    `TEST_CASE_START("Ensure no bleed");
    error = 0;
    last = 0;
    cnt = 0;

    $display("Write %0d words to FIFO (full packet)", MAX_PKT_SIZE/2);
    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
      m_axis.push_word({error,cnt}, i == (MAX_PKT_SIZE/2)-1);
      cnt++;
    end
    $display("Write %0d words to FIFO (partial packet)", MAX_PKT_SIZE/4);
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      m_axis.push_word({error,cnt}, 0);
      cnt++;
    end

    repeat(10) @(posedge clk);
    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == i, s);
      if (i == (MAX_PKT_SIZE/2)-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    repeat(10) @(posedge clk);
    `ASSERT_FATAL(~s_axis.axis.tvalid, "Partial packet bled through with full packet");
    for (int i = MAX_PKT_SIZE/4; i < MAX_PKT_SIZE/2; i++) begin
      m_axis.push_word({error,cnt}, i == (MAX_PKT_SIZE/2)-1);
      cnt++;
    end
    repeat(10) @(posedge clk);
    `ASSERT_FATAL(s_axis.axis.tvalid, "Did not see output even after full packet input");
    $display("Empty FIFO and check output");
    for (int i = MAX_PKT_SIZE/2; i < cnt; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == i, s);
      if (i == cnt-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    `TEST_CASE_DONE(1);


    `TEST_CASE_START("Back to back small packets");
    error = 0;
    last = 0;
    cnt = 0;
    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/2-1);
      cnt++;
    end
    for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/2-1);
      cnt++;
    end
    fork
    begin
      for (int k = 0; k < 8; k++) begin
        for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
          m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/2-1);
          cnt++;
        end
      end
    end
    begin
      @(posedge clk);
      @(posedge clk);
      @(posedge clk);
      for (int k = 0; k < 10; k++) begin
        for (int i = 0; i < MAX_PKT_SIZE/2; i++) begin
          `ASSERT_FATAL(s_axis.axis.tvalid, "tvalid not asserted!");
          s_axis.pull_word(check, last);
          $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
          `ASSERT_FATAL(check == (i+k*MAX_PKT_SIZE/2), s);
          if (i == MAX_PKT_SIZE/2-1) begin
            `ASSERT_FATAL(last, "tlast not asserted on final word!");
          end else begin
            `ASSERT_FATAL(~last, "tlast asserted prematurely!");
          end
        end
      end
    end
    join
    `TEST_CASE_DONE(1);

    #2000;


    `TEST_CASE_START("Drop error packet");
    cnt = 0;
    $display("Write packet with %0d words to FIFO", MAX_PKT_SIZE/4);
    error = 0;
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/4-1);
      cnt++;
    end
    $display("Write error packet with %0d words to FIFO", MAX_PKT_SIZE/4);
    error = 1;
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/4-1);
      cnt++;
    end
    $display("Write packet with %0d words to FIFO", MAX_PKT_SIZE/4);
    error = 0;
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      $sformat(s, "FIFO prematurely full at %0d (tready not asserted!)", i);
      `ASSERT_FATAL(m_axis.axis.tready, s);
      m_axis.push_word({error,cnt}, i == MAX_PKT_SIZE/4-1);
      cnt++;
    end
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == i, s);
      if (i == MAX_PKT_SIZE/4-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    for (int i = 0; i < MAX_PKT_SIZE/4; i++) begin
      $sformat(s, "FIFO prematurely empty at %0d (tvalid not asserted!)", i);
      `ASSERT_FATAL(s_axis.axis.tvalid, s);
      s_axis.pull_word(check, last);
      $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", i, check);
      `ASSERT_FATAL(check == (i+MAX_PKT_SIZE/2), s);
      if (i == MAX_PKT_SIZE/4-1) begin
        `ASSERT_FATAL(last, "tlast not asserted on final word!");
      end else begin
        `ASSERT_FATAL(~last, "tlast asserted prematurely!");
      end
    end
    `TEST_CASE_DONE(1);

    #2000;


    `TEST_CASE_START("Random read / writes");
    error = 0;
    last = 0;
    cnt = 0;
    fork
    begin
      for (int k = 1; k <= 5000*MAX_PKT_SIZE; k++) begin
        m_axis.push_word({error,k}, (k % 16) == 0);
        random_wait(0,16);
      end
    end
    begin
      for (int k = 1; k <= 5000*MAX_PKT_SIZE; k++) begin
        random_wait(0,16);
        s_axis.pull_word(check, last);
        $sformat(s, "FIFO output incorrect! Expected: %0d, Actual: %0d", k, check);
        `ASSERT_FATAL(check == k, s);
        if ((k % 16) == 0) begin
          `ASSERT_FATAL(last, "tlast not asserted!");
        end else begin
          `ASSERT_FATAL(~last, "tlast asserted prematurely!");
        end
      end
    end
    join
    `TEST_CASE_DONE(1);

    `TEST_BENCH_DONE;

  end
endmodule