data/full_repos/permissive/187464337/single_cycle_computer/freq_divider.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/187464337/single_cycle_computer/freq_divider.v:16: Multiple top level modules\n                                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                               : ... Top module \'freq_divider\'\nmodule freq_divider(input clk_50m, output reg out_clk);\n       ^~~~~~~~~~~~\n                                                                                               : ... Top module \'divide_by_two\'\nmodule divide_by_two(input in_clk, output reg out_clk);\n       ^~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module freq_divider(input clk_50m, output reg out_clk);
   parameter delay = 12_499_999;
   reg [24:0] counter = 0;

   initial out_clk <= 0;

   always @(posedge clk_50m)
      if (counter < delay)
         counter <= counter + 1'b1;
      else begin
         counter <= 0;
         out_clk <= ~out_clk;
      end
endmodule
module freq_divider(input clk_50m, output reg out_clk);

   parameter delay = 12_499_999;
   reg [24:0] counter = 0;

   initial out_clk <= 0;

   always @(posedge clk_50m)
      if (counter < delay)
         counter <= counter + 1'b1;
      else begin
         counter <= 0;
         out_clk <= ~out_clk;
      end
endmodule