data/full_repos/permissive/217518118/rtl/roms.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/217518118/rtl/roms.v:49: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'NJFGROM\'\nmodule NJFGROM\n       ^~~~~~~\n                                                                     : ... Top module \'NJBGROM\'\nmodule NJBGROM\n       ^~~~~~~\n                                                                     : ... Top module \'NJC0ROM\'\nmodule NJC0ROM\n       ^~~~~~~\n                                                                     : ... Top module \'NJC1ROM\'\nmodule NJC1ROM\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/roms.v:104: Input port connection \'AD1\' expects 15 bits on the pin connection, but pin connection\'s VARREF \'ROMAD\' generates 17 bits.\n                                                                   : ... In instance NJC1ROM\nDLROM #(15,8) r(CL,AD,DT,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2\'b11));\n                               ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/roms.v:87: Input port connection \'AD1\' expects 15 bits on the pin connection, but pin connection\'s VARREF \'ROMAD\' generates 17 bits.\n                                                                  : ... In instance NJC0ROM\nDLROM #(15,8) r(CL,AD,DT,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2\'b10));\n                               ^~~~~\n%Error: Exiting due to 3 warning(s)\n'
module NJC1ROM
(
	input				CL,
	input  [14:0]	AD,
	output  [7:0]	DT,
	
	input				ROMCL,
	input  [16:0]	ROMAD,
	input	  [7:0]	ROMDT,
	input				ROMEN
);

DLROM #(15,8) r(CL,AD,DT,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b11));

endmodule
module NJC1ROM
(
	input				CL,
	input  [14:0]	AD,
	output  [7:0]	DT,
	
	input				ROMCL,
	input  [16:0]	ROMAD,
	input	  [7:0]	ROMDT,
	input				ROMEN
);


DLROM #(15,8) r(CL,AD,DT,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b11));

endmodule