data/full_repos/permissive/124352446/synth/MyDesign.v
None: at end of input
1: b'%Error: data/full_repos/permissive/124352446/synth/MyDesign.v:4: Cannot find include file: /afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mac.v\n`include "/afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mac.v"  // link to designware Multiplier module   --> "/afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mult.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/124352446/synth,data/full_repos/permissive/124352446//afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mac.v\n             data/full_repos/permissive/124352446/synth,data/full_repos/permissive/124352446//afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mac.v.v\n             data/full_repos/permissive/124352446/synth,data/full_repos/permissive/124352446//afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mac.v.sv\n             /afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mac.v\n             /afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mac.v.v\n             /afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mac.v.sv\n             obj_dir//afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mac.v\n             obj_dir//afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mac.v.v\n             obj_dir//afs/eos.ncsu.edu/dist/synopsys2013/syn/dw/sim_ver/DW02_mac.v.sv\n%Error: Exiting due to 1 error(s)\n'
module inputQuadrant(
  input wire        clock, 
  input wire        rst,      
  input wire [9:0] clockCounter,
  input wire        flag,        
  input wire        aEnable,
  input wire        bEnable,
  input wire [15:0] bvm__dut__data,  
  input wire [15:0] dim__dut__data,  
  output reg [15:0] z0,
  output reg [15:0] z1,
  output reg [15:0] z2,
  output reg [15:0] z3,
  output reg [15:0] z4,         
  output reg [15:0] z5,          
  output reg [15:0] z6,          
  output reg [15:0] z7,          
  output reg [15:0] z8,         
  output reg [15:0] z9,          
  output reg [15:0] z10,         
  output reg [15:0] z11,         
  output reg [15:0] z12,         
  output reg [15:0] z13,         
  output reg [15:0] z14,         
  output reg [15:0] z15         
);


reg  [15:0] aReg [35:0];
reg  [15:0] bReg [35:0];
wire [31:0] cReg0, cReg1, cReg2, cReg3;
reg  [15:0] aTemp;
reg  [15:0] bTemp[3:0];
reg  [31:0] cTemp[3:0];
reg  [5:0]  clkCount1;

always@(posedge clock)
begin
  if(rst)
  begin
    clkCount1 <= 6'hA0;

  end
  else 
  begin
    clkCount1 <= clkCount1 + 1'h1;

  end




  if((clockCounter > 10'h000) && (clockCounter < 10'h025) && (aEnable))
    begin   
      aReg[clockCounter-1] <= dim__dut__data;    

    end
  else if(clockCounter == 10'h025)
    begin
      clkCount1 <= 6'h00;                                               
    end
  else if((clockCounter > 10'h050) && (clockCounter < 10'h075) && (aEnable))
    begin   
      aReg[clockCounter-8'h51] <= dim__dut__data;    
    end
  else if(clockCounter == 10'h075)
    begin
      clkCount1 <= 6'h00;                                               
    end
  if((clockCounter > 10'h0A0) && (clockCounter < 10'h0C5) && (aEnable))
    begin   
      aReg[clockCounter-8'hA1] <= dim__dut__data;    
    end
  else if(clockCounter == 10'h0C5)
    begin
      clkCount1 <= 6'h00;                                           
    end
  if((clockCounter > 10'h0F0) && (clockCounter < 10'h115) && (aEnable))
    begin   
      aReg[clockCounter-8'hF1] <= dim__dut__data;    
    end
  else if(clockCounter == 10'h115)
    begin
      clkCount1 <= 6'h00;

    end
     





  if((clockCounter > 10'h000) && (clockCounter < 10'h025) && (bEnable))  
    begin
      bReg[clockCounter-1] <= bvm__dut__data;
    end   
  else 
    begin
    end







  if(clkCount1 == 6'h00 && flag)
  begin
    cTemp[0] <= 32'h0;
    cTemp[1] <= 32'h0;
    cTemp[2] <= 32'h0;
    cTemp[3] <= 32'h0;

    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1];
    bTemp[1] <= bReg[clkCount1 + 8'h09];
    bTemp[2] <= bReg[clkCount1 + 8'h12];
    bTemp[3] <= bReg[clkCount1 + 8'h1B];    
  end
  else if((clkCount1 > 6'h00) && (clkCount1 < 6'h09) && flag)
  begin
    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1];
    bTemp[1] <= bReg[clkCount1 + 8'h09];
    bTemp[2] <= bReg[clkCount1 + 8'h12];
    bTemp[3] <= bReg[clkCount1 + 8'h1B]; 

    cTemp[0] <= cReg0;
    cTemp[1] <= cReg1;
    cTemp[2] <= cReg2;
    cTemp[3] <= cReg3;
  end
  else if(clkCount1 == 6'h09 && flag)
  begin
    cTemp[0] <= 32'h0;
    cTemp[1] <= 32'h0;
    cTemp[2] <= 32'h0;
    cTemp[3] <= 32'h0;

    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 6'h09];
    bTemp[1] <= bReg[clkCount1];
    bTemp[2] <= bReg[clkCount1 + 6'h09];
    bTemp[3] <= bReg[clkCount1 + 6'h12]; 
   
    if(cReg0[31]==1'h0) z0 <= cReg0 [31:16];
    else                z0 <= 16'h0000;
    if(cReg1[31]==1'h0) z1 <= cReg1 [31:16];
    else                z1 <= 16'h0000;
    if(cReg2[31]==1'h0) z2 <= cReg2 [31:16];
    else                z2 <= 16'h0000;
    if(cReg3[31]==1'h0) z3 <= cReg3 [31:16];
    else                z3 <= 16'h0000;
  end

  else if((clkCount1 > 6'h09) && (clkCount1 < 6'h12) && flag)
  begin
    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 8'h09];
    bTemp[1] <= bReg[clkCount1];
    bTemp[2] <= bReg[clkCount1 + 8'h09];
    bTemp[3] <= bReg[clkCount1 + 8'h12]; 
 
    cTemp[0] <= cReg0;
    cTemp[1] <= cReg1;
    cTemp[2] <= cReg2;
    cTemp[3] <= cReg3;
  end
  else if(clkCount1 == 6'h12 && flag)
  begin
    cTemp[0] <= 32'h0;
    cTemp[1] <= 32'h0;
    cTemp[2] <= 32'h0;
    cTemp[3] <= 32'h0;

    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 8'h12];
    bTemp[1] <= bReg[clkCount1 - 8'h09];
    bTemp[2] <= bReg[clkCount1];
    bTemp[3] <= bReg[clkCount1 + 8'h09]; 

    if(cReg0[31]==1'h0) z4 <= cReg0 [31:16];
    else                z4 <= 16'h0000;
    if(cReg1[31]==1'h0) z5 <= cReg1 [31:16];
    else                z5 <= 16'h0000;
    if(cReg2[31]==1'h0) z6 <= cReg2 [31:16];
    else                z6 <= 16'h0000;
    if(cReg3[31]==1'h0) z7 <= cReg3 [31:16];
    else                z7 <= 16'h0000;
  end
  else if((clkCount1 > 6'h12) && (clkCount1 < 6'h1B) && flag)
  begin
    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 8'h12];
    bTemp[1] <= bReg[clkCount1 - 8'h09];
    bTemp[2] <= bReg[clkCount1];
    bTemp[3] <= bReg[clkCount1 + 8'h09]; 

    cTemp[0] <= cReg0;
    cTemp[1] <= cReg1;
    cTemp[2] <= cReg2;
    cTemp[3] <= cReg3;
  end
  else if(clkCount1 == 6'h1B && flag)
  begin
    cTemp[0] <= 32'h0;
    cTemp[1] <= 32'h0;
    cTemp[2] <= 32'h0;
    cTemp[3] <= 32'h0;

    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 8'h1B];
    bTemp[1] <= bReg[clkCount1 - 8'h12];
    bTemp[2] <= bReg[clkCount1 - 8'h09];
    bTemp[3] <= bReg[clkCount1]; 

    if(cReg0[31]==1'h0) z8 <= cReg0 [31:16];
    else                z8 <= 16'h0000;
    if(cReg1[31]==1'h0) z9 <= cReg1 [31:16];
    else                z9 <= 16'h0000;
    if(cReg2[31]==1'h0) z10<= cReg2 [31:16];
    else                z10<= 16'h0000;
    if(cReg3[31]==1'h0) z11<= cReg3 [31:16];
    else                z11<= 16'h0000;
  end
  else if((clkCount1 > 6'h1B) && (clkCount1 < 6'h24) && flag)
  begin
    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 8'h1B];
    bTemp[1] <= bReg[clkCount1 - 8'h12];
    bTemp[2] <= bReg[clkCount1 - 8'h09];
    bTemp[3] <= bReg[clkCount1]; 

    cTemp[0] <= cReg0;
    cTemp[1] <= cReg1;
    cTemp[2] <= cReg2;
    cTemp[3] <= cReg3;
  end
  else if(clkCount1 == 6'h24 && flag)
  begin
    if(cReg0[31]==1'h0) z12<= cReg0 [31:16];
    else                z12<= 16'h0000;
    if(cReg1[31]==1'h0) z13<= cReg1 [31:16];
    else                z13<= 16'h0000;
    if(cReg2[31]==1'h0) z14<= cReg2 [31:16];
    else                z14<= 16'h0000;
    if(cReg3[31]==1'h0) z15<= cReg3 [31:16];
    else                z15<= 16'h0000;
  end

end
 
    

DW02_mac #(16,16)  U0 ( .A(aTemp), .B(bTemp[0]), .C(cTemp[0]), .TC(1'b1), .MAC(cReg0) );
DW02_mac #(16,16)  U1 ( .A(aTemp), .B(bTemp[1]), .C(cTemp[1]), .TC(1'b1), .MAC(cReg1) );
DW02_mac #(16,16)  U2 ( .A(aTemp), .B(bTemp[2]), .C(cTemp[2]), .TC(1'b1), .MAC(cReg2) );
DW02_mac #(16,16)  U3 ( .A(aTemp), .B(bTemp[3]), .C(cTemp[3]), .TC(1'b1), .MAC(cReg3) );

endmodule
module inputQuadrant(
  input wire        clock, 
  input wire        rst,      
  input wire [9:0] clockCounter,
  input wire        flag,        
  input wire        aEnable,
  input wire        bEnable,
  input wire [15:0] bvm__dut__data,  
  input wire [15:0] dim__dut__data,  
  output reg [15:0] z0,
  output reg [15:0] z1,
  output reg [15:0] z2,
  output reg [15:0] z3,
  output reg [15:0] z4,         
  output reg [15:0] z5,          
  output reg [15:0] z6,          
  output reg [15:0] z7,          
  output reg [15:0] z8,         
  output reg [15:0] z9,          
  output reg [15:0] z10,         
  output reg [15:0] z11,         
  output reg [15:0] z12,         
  output reg [15:0] z13,         
  output reg [15:0] z14,         
  output reg [15:0] z15         
);



reg  [15:0] aReg [35:0];
reg  [15:0] bReg [35:0];
wire [31:0] cReg0, cReg1, cReg2, cReg3;
reg  [15:0] aTemp;
reg  [15:0] bTemp[3:0];
reg  [31:0] cTemp[3:0];
reg  [5:0]  clkCount1;

always@(posedge clock)
begin
  if(rst)
  begin
    clkCount1 <= 6'hA0;

  end
  else 
  begin
    clkCount1 <= clkCount1 + 1'h1;

  end




  if((clockCounter > 10'h000) && (clockCounter < 10'h025) && (aEnable))
    begin   
      aReg[clockCounter-1] <= dim__dut__data;    

    end
  else if(clockCounter == 10'h025)
    begin
      clkCount1 <= 6'h00;                                               
    end
  else if((clockCounter > 10'h050) && (clockCounter < 10'h075) && (aEnable))
    begin   
      aReg[clockCounter-8'h51] <= dim__dut__data;    
    end
  else if(clockCounter == 10'h075)
    begin
      clkCount1 <= 6'h00;                                               
    end
  if((clockCounter > 10'h0A0) && (clockCounter < 10'h0C5) && (aEnable))
    begin   
      aReg[clockCounter-8'hA1] <= dim__dut__data;    
    end
  else if(clockCounter == 10'h0C5)
    begin
      clkCount1 <= 6'h00;                                           
    end
  if((clockCounter > 10'h0F0) && (clockCounter < 10'h115) && (aEnable))
    begin   
      aReg[clockCounter-8'hF1] <= dim__dut__data;    
    end
  else if(clockCounter == 10'h115)
    begin
      clkCount1 <= 6'h00;

    end
     





  if((clockCounter > 10'h000) && (clockCounter < 10'h025) && (bEnable))  
    begin
      bReg[clockCounter-1] <= bvm__dut__data;
    end   
  else 
    begin
    end







  if(clkCount1 == 6'h00 && flag)
  begin
    cTemp[0] <= 32'h0;
    cTemp[1] <= 32'h0;
    cTemp[2] <= 32'h0;
    cTemp[3] <= 32'h0;

    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1];
    bTemp[1] <= bReg[clkCount1 + 8'h09];
    bTemp[2] <= bReg[clkCount1 + 8'h12];
    bTemp[3] <= bReg[clkCount1 + 8'h1B];    
  end
  else if((clkCount1 > 6'h00) && (clkCount1 < 6'h09) && flag)
  begin
    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1];
    bTemp[1] <= bReg[clkCount1 + 8'h09];
    bTemp[2] <= bReg[clkCount1 + 8'h12];
    bTemp[3] <= bReg[clkCount1 + 8'h1B]; 

    cTemp[0] <= cReg0;
    cTemp[1] <= cReg1;
    cTemp[2] <= cReg2;
    cTemp[3] <= cReg3;
  end
  else if(clkCount1 == 6'h09 && flag)
  begin
    cTemp[0] <= 32'h0;
    cTemp[1] <= 32'h0;
    cTemp[2] <= 32'h0;
    cTemp[3] <= 32'h0;

    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 6'h09];
    bTemp[1] <= bReg[clkCount1];
    bTemp[2] <= bReg[clkCount1 + 6'h09];
    bTemp[3] <= bReg[clkCount1 + 6'h12]; 
   
    if(cReg0[31]==1'h0) z0 <= cReg0 [31:16];
    else                z0 <= 16'h0000;
    if(cReg1[31]==1'h0) z1 <= cReg1 [31:16];
    else                z1 <= 16'h0000;
    if(cReg2[31]==1'h0) z2 <= cReg2 [31:16];
    else                z2 <= 16'h0000;
    if(cReg3[31]==1'h0) z3 <= cReg3 [31:16];
    else                z3 <= 16'h0000;
  end

  else if((clkCount1 > 6'h09) && (clkCount1 < 6'h12) && flag)
  begin
    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 8'h09];
    bTemp[1] <= bReg[clkCount1];
    bTemp[2] <= bReg[clkCount1 + 8'h09];
    bTemp[3] <= bReg[clkCount1 + 8'h12]; 
 
    cTemp[0] <= cReg0;
    cTemp[1] <= cReg1;
    cTemp[2] <= cReg2;
    cTemp[3] <= cReg3;
  end
  else if(clkCount1 == 6'h12 && flag)
  begin
    cTemp[0] <= 32'h0;
    cTemp[1] <= 32'h0;
    cTemp[2] <= 32'h0;
    cTemp[3] <= 32'h0;

    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 8'h12];
    bTemp[1] <= bReg[clkCount1 - 8'h09];
    bTemp[2] <= bReg[clkCount1];
    bTemp[3] <= bReg[clkCount1 + 8'h09]; 

    if(cReg0[31]==1'h0) z4 <= cReg0 [31:16];
    else                z4 <= 16'h0000;
    if(cReg1[31]==1'h0) z5 <= cReg1 [31:16];
    else                z5 <= 16'h0000;
    if(cReg2[31]==1'h0) z6 <= cReg2 [31:16];
    else                z6 <= 16'h0000;
    if(cReg3[31]==1'h0) z7 <= cReg3 [31:16];
    else                z7 <= 16'h0000;
  end
  else if((clkCount1 > 6'h12) && (clkCount1 < 6'h1B) && flag)
  begin
    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 8'h12];
    bTemp[1] <= bReg[clkCount1 - 8'h09];
    bTemp[2] <= bReg[clkCount1];
    bTemp[3] <= bReg[clkCount1 + 8'h09]; 

    cTemp[0] <= cReg0;
    cTemp[1] <= cReg1;
    cTemp[2] <= cReg2;
    cTemp[3] <= cReg3;
  end
  else if(clkCount1 == 6'h1B && flag)
  begin
    cTemp[0] <= 32'h0;
    cTemp[1] <= 32'h0;
    cTemp[2] <= 32'h0;
    cTemp[3] <= 32'h0;

    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 8'h1B];
    bTemp[1] <= bReg[clkCount1 - 8'h12];
    bTemp[2] <= bReg[clkCount1 - 8'h09];
    bTemp[3] <= bReg[clkCount1]; 

    if(cReg0[31]==1'h0) z8 <= cReg0 [31:16];
    else                z8 <= 16'h0000;
    if(cReg1[31]==1'h0) z9 <= cReg1 [31:16];
    else                z9 <= 16'h0000;
    if(cReg2[31]==1'h0) z10<= cReg2 [31:16];
    else                z10<= 16'h0000;
    if(cReg3[31]==1'h0) z11<= cReg3 [31:16];
    else                z11<= 16'h0000;
  end
  else if((clkCount1 > 6'h1B) && (clkCount1 < 6'h24) && flag)
  begin
    aTemp    <= aReg[clkCount1];

    bTemp[0] <= bReg[clkCount1 - 8'h1B];
    bTemp[1] <= bReg[clkCount1 - 8'h12];
    bTemp[2] <= bReg[clkCount1 - 8'h09];
    bTemp[3] <= bReg[clkCount1]; 

    cTemp[0] <= cReg0;
    cTemp[1] <= cReg1;
    cTemp[2] <= cReg2;
    cTemp[3] <= cReg3;
  end
  else if(clkCount1 == 6'h24 && flag)
  begin
    if(cReg0[31]==1'h0) z12<= cReg0 [31:16];
    else                z12<= 16'h0000;
    if(cReg1[31]==1'h0) z13<= cReg1 [31:16];
    else                z13<= 16'h0000;
    if(cReg2[31]==1'h0) z14<= cReg2 [31:16];
    else                z14<= 16'h0000;
    if(cReg3[31]==1'h0) z15<= cReg3 [31:16];
    else                z15<= 16'h0000;
  end

end
 
    

DW02_mac #(16,16)  U0 ( .A(aTemp), .B(bTemp[0]), .C(cTemp[0]), .TC(1'b1), .MAC(cReg0) );
DW02_mac #(16,16)  U1 ( .A(aTemp), .B(bTemp[1]), .C(cTemp[1]), .TC(1'b1), .MAC(cReg1) );
DW02_mac #(16,16)  U2 ( .A(aTemp), .B(bTemp[2]), .C(cTemp[2]), .TC(1'b1), .MAC(cReg2) );
DW02_mac #(16,16)  U3 ( .A(aTemp), .B(bTemp[3]), .C(cTemp[3]), .TC(1'b1), .MAC(cReg3) );

endmodule