data/full_repos/permissive/159596577/src/dff32.v
data/verilator_xmls/658018c6-848b-42dd-9c90-10fe077f5f3f.xml
module dff32(
    d,
    clk,
    rst,
    q
);
    input [31:0]d;
    input clk,rst;
    output [31:0]q;
    reg [31:0]q;
    always @(posedge clk, posedge rst) begin
        if(rst == 0) q<=0;
        else q<=d;
    end
endmodule
module dff32(
    d,
    clk,
    rst,
    q
);

    input [31:0]d;
    input clk,rst;
    output [31:0]q;
    reg [31:0]q;
    always @(posedge clk, posedge rst) begin
        if(rst == 0) q<=0;
        else q<=d;
    end
endmodule