data/full_repos/permissive/126085346/src/fuji_iie.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/126085346/src/fuji_iie.v:115: Assigning to input/const variable: 'diagnostics_rom_d'\n    assign diagnostics_rom_d = md;\n           ^~~~~~~~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/126085346/src/fuji_iie.v:120: Assigning to input/const variable: 'monitor_rom_d'\n    assign monitor_rom_d = md;\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module FujiIIe(
    input clk_core,
    input clk_14M,
    input reset,


    output diagnostics_rom_ce_n,
    output diagnostics_rom_oe_n,
    output [12:0] diagnostics_rom_a,
    input [7:0] diagnostics_rom_d,


    output monitor_rom_ce_n,
    output monitor_rom_oe_n,
    output [12:0] monitor_rom_a,
    input [7:0] monitor_rom_d,


    output [7:0] main_ram_ra,
    output main_ram_ras_n,
    output main_ram_cas_n,
    output main_ram_rw_n,
    inout [7:0] main_ram_d
    );

    wire clk_7M;
    wire clk_q3;
    wire clk_phi_0;
    wire clk_phi_1;
    wire clk_phi_2;


    wire [15:0] a;
    wire [7:0] md;
    wire rdwr_n;

    wire romen1_n;
    wire romen2_n;


    wire ramen_n;
    wire pras_n;
    wire pcas_n;
    wire [7:0] ra;

    MCL65 cpu(
        .CORE_CLK(clk_core),
        .CLK0(clk_phi_0),
        .CLK1(clk_phi_1),
        .CLK2(clk_phi_2),
        .RESET_n(~reset),
        .NMI_n(),
        .IRQ_n(),
        .SO(),
        .SYNC(),
        .RDWR_n(rdwr_n),
        .READY(),
        .A(a),
        .D(md),
        .DIR0(),
        .DIR1()
    );

    AppleIIePAL pal(
        .clk_14M(clk_14M),

        .clk_7M(clk_7M),
        .clk_q3(clk_q3),
        .clk_phi_0(clk_phi_0),

        .clk_phi_1(clk_phi_1),
        .ramen_n(ramen_n),
        .pras_n(pras_n),
        .pcas_n(pcas_n)
    );

    AppleIIeMemoryManagementUnit mmu(
        .clk_phi_0(clk_phi_0),
        .clk_q3(clk_q3),

        .a(a),
        .md7(md[7]),
        .rw_n(rdwr_n),

        .inh_n(1'b1),

        .ramen_n(ramen_n),
        .pras_n(pras_n),
        .ra(ra),

        .romen1_n(romen1_n),
        .romen2_n(romen2_n)
    );

    assign diagnostics_rom_ce_n = 1'b0;
    assign diagnostics_rom_oe_n = romen1_n;
    assign diagnostics_rom_a = a[12:0];
    assign diagnostics_rom_d = md;

    assign monitor_rom_ce_n = 1'b0;
    assign monitor_rom_oe_n = romen2_n;
    assign monitor_rom_a = a[12:0];
    assign monitor_rom_d = md;

    assign main_ram_ra = ra;
    assign main_ram_ras_n = pras_n;
    assign main_ram_cas_n = pcas_n;
    assign main_ram_d = md;
endmodule
module FujiIIe(
    input clk_core,
    input clk_14M,
    input reset,


    output diagnostics_rom_ce_n,
    output diagnostics_rom_oe_n,
    output [12:0] diagnostics_rom_a,
    input [7:0] diagnostics_rom_d,


    output monitor_rom_ce_n,
    output monitor_rom_oe_n,
    output [12:0] monitor_rom_a,
    input [7:0] monitor_rom_d,


    output [7:0] main_ram_ra,
    output main_ram_ras_n,
    output main_ram_cas_n,
    output main_ram_rw_n,
    inout [7:0] main_ram_d
    );


    wire clk_7M;
    wire clk_q3;
    wire clk_phi_0;
    wire clk_phi_1;
    wire clk_phi_2;


    wire [15:0] a;
    wire [7:0] md;
    wire rdwr_n;

    wire romen1_n;
    wire romen2_n;


    wire ramen_n;
    wire pras_n;
    wire pcas_n;
    wire [7:0] ra;

    MCL65 cpu(
        .CORE_CLK(clk_core),
        .CLK0(clk_phi_0),
        .CLK1(clk_phi_1),
        .CLK2(clk_phi_2),
        .RESET_n(~reset),
        .NMI_n(),
        .IRQ_n(),
        .SO(),
        .SYNC(),
        .RDWR_n(rdwr_n),
        .READY(),
        .A(a),
        .D(md),
        .DIR0(),
        .DIR1()
    );

    AppleIIePAL pal(
        .clk_14M(clk_14M),

        .clk_7M(clk_7M),
        .clk_q3(clk_q3),
        .clk_phi_0(clk_phi_0),

        .clk_phi_1(clk_phi_1),
        .ramen_n(ramen_n),
        .pras_n(pras_n),
        .pcas_n(pcas_n)
    );

    AppleIIeMemoryManagementUnit mmu(
        .clk_phi_0(clk_phi_0),
        .clk_q3(clk_q3),

        .a(a),
        .md7(md[7]),
        .rw_n(rdwr_n),

        .inh_n(1'b1),

        .ramen_n(ramen_n),
        .pras_n(pras_n),
        .ra(ra),

        .romen1_n(romen1_n),
        .romen2_n(romen2_n)
    );

    assign diagnostics_rom_ce_n = 1'b0;
    assign diagnostics_rom_oe_n = romen1_n;
    assign diagnostics_rom_a = a[12:0];
    assign diagnostics_rom_d = md;

    assign monitor_rom_ce_n = 1'b0;
    assign monitor_rom_oe_n = romen2_n;
    assign monitor_rom_a = a[12:0];
    assign monitor_rom_d = md;

    assign main_ram_ra = ra;
    assign main_ram_ras_n = pras_n;
    assign main_ram_cas_n = pcas_n;
    assign main_ram_d = md;
endmodule