data/full_repos/permissive/143278/ivltests/pr3296466b.v
 line:24: before: "$"
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr3296466b.v:3: Unsupported: Verilog 1995 gate primitive: tran\ntran(c[0], c[1]);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3296466b.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b", a);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3296466b.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b", a);\n  ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top();

tri [3:0] a;

reg dir;

connect connect1(a[1:0]);
connect connect2(a[2:1]);
connect connect3(a[3:2]);

assign a[0] = dir ? 1'bz : 1'b0;
assign a[3] = dir ? 1'b1 : 1'bz;

reg pass = 1;

initial begin
  dir = 1'b0;
  #1 $display("%b", a);
  if (a !== 4'b0000) pass = 0;
  dir = 1'b1;
  #1 $display("%b", a);
  if (a !== 4'b1111) pass = 0;

  if (pass)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module top();


tri [3:0] a;

reg dir;

connect connect1(a[1:0]);
connect connect2(a[2:1]);
connect connect3(a[3:2]);

assign a[0] = dir ? 1'bz : 1'b0;
assign a[3] = dir ? 1'b1 : 1'bz;

reg pass = 1;

initial begin
  dir = 1'b0;
  #1 $display("%b", a);
  if (a !== 4'b0000) pass = 0;
  dir = 1'b1;
  #1 $display("%b", a);
  if (a !== 4'b1111) pass = 0;

  if (pass)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule