data/full_repos/permissive/198139336/DD_lab11/Lab11_example_Zedboard/DD_FIR/DD_FIR.srcs/sources_1/imports/vivado_demo/code/dbuf.v
data/verilator_xmls/67d877bd-6e21-47ed-8645-d967911455eb.xml
module dbuf(
	input wire clk, 
	input wire [15:0] din,
	input wire [5:0] didx,
	input wire RW,
	output reg [15:0] di
);
	reg [15:0] mem [0:63];


	always @(posedge clk) begin 
		if(RW) 
			mem[didx] <= din; 
		
		di <= RW ? din:mem[didx];
	end

endmodule
module dbuf(
	input wire clk, 
	input wire [15:0] din,
	input wire [5:0] didx,
	input wire RW,
	output reg [15:0] di
);

	reg [15:0] mem [0:63];


	always @(posedge clk) begin 
		if(RW) 
			mem[didx] <= din; 
		
		di <= RW ? din:mem[didx];
	end

endmodule