data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v
'utf-8' codec can't decode byte 0xbe in position 25: invalid start byte
1: b'%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:2: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.v\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:9: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus]   addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`DataAddrBus]   addr,\n                        ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`DataBus]      data_i,\n ^~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:11: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus]      data_i,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:12: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus]     data_o\n            ^~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:19: Define or directive not defined: \'`DataMemNum\'\n reg[7 : 0] data_mem[0: `DataMemNum - 1];\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:21: syntax error, unexpected always\n always @ (posedge clk) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:22: Define or directive not defined: \'`ChipDisable\'\n  if (ce == `ChipDisable) begin\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:24: Define or directive not defined: \'`WriteEnable\'\n  end else if(we == `WriteEnable) begin\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:49: Define or directive not defined: \'`ChipDisable\'\n  if (ce == `ChipDisable) begin\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:50: Define or directive not defined: \'`ZeroWord\'\n   data_o <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:51: Define or directive not defined: \'`WriteDisable\'\n   end else if(we == `WriteDisable) begin\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/data_ram.v:61: Define or directive not defined: \'`ZeroWord\'\n    data_o <= `ZeroWord;\n              ^~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module data_ram(

	input	wire										clk,
	input wire										ce,
	input wire										we,
	input wire[`DataAddrBus]			addr,
	input wire[3:0]								sel,
	input wire[`DataBus]						data_i,
	output reg[`DataBus]					data_o

);




	reg[7 : 0] data_mem[0: `DataMemNum - 1];

	always @ (posedge clk) begin
		if (ce == `ChipDisable) begin

		end else if(we == `WriteEnable) begin
			  if (sel == 4'b0100) begin




			  {data_mem[addr + 3],
			  data_mem[addr + 2],
			  data_mem[addr + 1],
			  data_mem[addr]} <= data_i[31:0];
			end
			  else if (sel == 4'b0010) begin


			  {data_mem[addr + 1],
			  data_mem[addr]} <= data_i[15:0];
			end
		  	  else if (sel == 4'b0001) begin

			  {data_mem[addr]} <= data_i[7:0];
			end
		end
	end

	always @ (*) begin
		if (ce == `ChipDisable) begin
			data_o <= `ZeroWord;
	  end else if(we == `WriteDisable) begin




			 data_o <=  {data_mem[addr + 3],
 		              	 data_mem[addr + 2],
 		                 data_mem[addr + 1],
 		                 data_mem[addr]};
		end else begin
				data_o <= `ZeroWord;
		end
	end

endmodule
module data_ram(

	input	wire										clk,
	input wire										ce,
	input wire										we,
	input wire[`DataAddrBus]			addr,
	input wire[3:0]								sel,
	input wire[`DataBus]						data_i,
	output reg[`DataBus]					data_o

);





	reg[7 : 0] data_mem[0: `DataMemNum - 1];

	always @ (posedge clk) begin
		if (ce == `ChipDisable) begin

		end else if(we == `WriteEnable) begin
			  if (sel == 4'b0100) begin




			  {data_mem[addr + 3],
			  data_mem[addr + 2],
			  data_mem[addr + 1],
			  data_mem[addr]} <= data_i[31:0];
			end
			  else if (sel == 4'b0010) begin


			  {data_mem[addr + 1],
			  data_mem[addr]} <= data_i[15:0];
			end
		  	  else if (sel == 4'b0001) begin

			  {data_mem[addr]} <= data_i[7:0];
			end
		end
	end

	always @ (*) begin
		if (ce == `ChipDisable) begin
			data_o <= `ZeroWord;
	  end else if(we == `WriteDisable) begin




			 data_o <=  {data_mem[addr + 3],
 		              	 data_mem[addr + 2],
 		                 data_mem[addr + 1],
 		                 data_mem[addr]};
		end else begin
				data_o <= `ZeroWord;
		end
	end

endmodule