data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:15: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb,data/full_repos/permissive/214858095/test_exec.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb,data/full_repos/permissive/214858095/test_exec.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb,data/full_repos/permissive/214858095/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:16: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgTestExec::*;\n         ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:88: Unsupported: Ignoring delay on this delayed statement.\n  always #(CLK200_PERIOD) clk200 = ~clk200;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:91: Unsupported: Ignoring delay on this delayed statement.\n  always #(CLK_PERIOD) clk = ~clk;\n         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:110: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:113: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:116: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:119: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:124: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:127: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:130: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:133: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:147: syntax error, unexpected \'@\'\n    repeat (len) @(posedge clk);\n                 ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:153: syntax error, unexpected \'@\'\n    repeat(num_cycles) @(negedge rx_clk);\n                       ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:155: syntax error, unexpected \'@\'\n    repeat(2) @(negedge rx_clk);\n              ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:221: syntax error, unexpected \'@\'\n      @(negedge rx_clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:223: syntax error, unexpected \'@\'\n      @(negedge rx_clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:228: syntax error, unexpected \'@\'\n      @(negedge rx_clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:230: syntax error, unexpected \'@\'\n      @(negedge rx_clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:235: syntax error, unexpected \'@\'\n      @(negedge rx_clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:237: syntax error, unexpected \'@\'\n      @(negedge rx_clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:242: syntax error, unexpected \'@\'\n      @(negedge rx_clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:244: syntax error, unexpected \'@\'\n      @(negedge rx_clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:558: syntax error, unexpected \'@\'\n      @(posedge tx_clk_n);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:561: syntax error, unexpected \'@\'\n      @(posedge tx_clk_p);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:564: syntax error, unexpected \'@\'\n      @(posedge tx_clk_n);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:569: syntax error, unexpected \'@\'\n      @(posedge tx_clk_p);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:572: syntax error, unexpected \'@\'\n      @(posedge tx_clk_n);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:575: syntax error, unexpected \'@\'\n      @(posedge tx_clk_p);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:578: syntax error, unexpected \'@\'\n      @(posedge tx_clk_n);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/io_cap_gen/cat_io_lvds_dual_mode_tb/cat_io_lvds_dual_mode_tb.sv:582: Unsupported: Ignoring delay on this delayed statement.\n      #1    \n      ^\n%Error: Exiting due to 28 error(s), 3 warning(s)\n'
module cat_io_lvds_dual_mode_tb();

  `include "test_exec.svh"
  import PkgTestExec::*;

  localparam CLK_PERIOD    = 10;
  localparam CLK200_PERIOD = 2.5;

  localparam USE_CLOCK_IDELAY   = 1;
  localparam USE_DATA_IDELAY    = 1;
  localparam DATA_IDELAY_MODE   = "FIXED";
  localparam CLOCK_IDELAY_MODE  = "FIXED";
  localparam INPUT_CLOCK_DELAY  = 16;
  localparam INPUT_DATA_DELAY   = 0;
  localparam USE_CLOCK_ODELAY   = 1;
  localparam USE_DATA_ODELAY    = 1;
  localparam DATA_ODELAY_MODE   = "FIXED";
  localparam CLOCK_ODELAY_MODE  = "FIXED";
  localparam OUTPUT_CLOCK_DELAY = 31;
  localparam OUTPUT_DATA_DELAY  = 0;

  reg       check_enabled;

  reg       clk    = 0;
  reg       rx_clk = 0;
  reg       clk200 = 0;

  reg       reset;
  reg       mimo;
  reg       tx_ch;
  reg [5:0] rx_d;
  reg       rx_frame;
  reg [7:0] rx_count = 0;



  wire [11:0] i0 = { 4'hA, rx_count };
  wire [11:0] q0 = { 4'hB, rx_count };
  wire [11:0] i1 = { 4'hC, rx_count };
  wire [11:0] q1 = { 4'hD, rx_count };

  wire radio_clk;

  reg [11:0] tx_i0;
  reg [11:0] tx_q0;
  reg [11:0] tx_i1;
  reg [11:0] tx_q1;

  wire [11:0] rx_i0;
  wire [11:0] rx_q0;
  wire [11:0] rx_i1;
  wire [11:0] rx_q1;

  wire rx_aligned;

  wire        tx_clk_p, tx_clk_n;
  wire        tx_frame_p, tx_frame_n;
  wire [5:0]  tx_d_p, tx_d_n;

  reg [4:0]  ctrl_in_data_delay;
  reg [4:0]  ctrl_in_clk_delay;
  reg        ctrl_ld_in_data_delay;
  reg        ctrl_ld_in_clk_delay;

  reg [4:0]  ctrl_out_data_delay;
  reg [4:0]  ctrl_out_clk_delay;
  reg        ctrl_ld_out_data_delay;
  reg        ctrl_ld_out_clk_delay;







  always #(CLK200_PERIOD) clk200 = ~clk200;


  always #(CLK_PERIOD) clk = ~clk;


  always @(negedge clk) rx_clk <= ~rx_clk;









  task Burst(int len, logic do_mimo);
    repeat(len)
      begin
        mimo <= do_mimo;


        @(posedge clk);
        rx_d <= i0[11:6];
        rx_frame <= 1;
        @(posedge clk);
        rx_d <= q0[11:6];
        rx_frame <= 1;
        @(posedge clk);
        rx_d <= i0[5:0];
        rx_frame <= do_mimo;
        @(posedge clk);
        rx_d <= q0[5:0];
        rx_frame <= do_mimo;


        @(posedge clk);
        rx_d <= i1[11:6];
        rx_frame <= ~do_mimo;
        @(posedge clk);
        rx_d <= q1[11:6];
        rx_frame <= ~do_mimo;
        @(posedge clk);
        rx_d <= i1[5:0];
        rx_frame <= 0;
        @(posedge clk);
        rx_d <= q1[5:0];
        rx_frame <= 0;

        rx_count <= rx_count + 1;
      end
  endtask : Burst




  task Idle(int len = 100);
    rx_d     <= 0;
    rx_frame <= 0;
    repeat (len) @(posedge clk);
  endtask : Idle


  task Reset(int num_cycles = 20);
    reset <= 1;
    repeat(num_cycles) @(negedge rx_clk);
    reset <= 0;
    repeat(2) @(negedge rx_clk);
  endtask : Reset







  task TestBurst;
    input [31:0] len;
    input        do_mimo;
    begin
      if (len <= 2) begin
        $fatal(1, "ERROR @%0t in %m: In TestBurst, len must be > 2", $time);
      end



      Burst(1, do_mimo);


      check_enabled <= 1'b1;


      Burst(len-2, do_mimo);


      check_enabled <= 1'b0;


      Burst(1, do_mimo);
    end
  endtask






  initial begin : main

    test.start_tb("cat_io_lvds_dual_mode_tb");


    check_enabled <= 1'b0;
    reset = 1;
    mimo  = 1;
    ctrl_in_clk_delay      = INPUT_CLOCK_DELAY;
    ctrl_in_data_delay     = INPUT_DATA_DELAY;
    ctrl_ld_in_data_delay  = 1'b0;
    ctrl_ld_in_clk_delay   = 1'b0;
    ctrl_out_clk_delay     = OUTPUT_CLOCK_DELAY;
    ctrl_out_data_delay    = OUTPUT_DATA_DELAY;
    ctrl_ld_out_data_delay = 1'b0;
    ctrl_ld_out_clk_delay  = 1'b0;

    Reset();




    test.start_test("Load IO delays");

    if (CLOCK_IDELAY_MODE == "VAR_LOAD") begin
      ctrl_ld_in_clk_delay  = 1'b1;
      @(negedge rx_clk);
      ctrl_ld_in_clk_delay  = 1'b0;
      @(negedge rx_clk);
    end

    if (DATA_IDELAY_MODE == "VAR_LOAD") begin
      ctrl_ld_in_data_delay = 1'b1;
      @(negedge rx_clk);
      ctrl_ld_in_data_delay = 1'b0;
      @(negedge rx_clk);
    end

    if (CLOCK_ODELAY_MODE == "VAR_LOAD") begin
      ctrl_ld_out_clk_delay  = 1'b1;
      @(negedge rx_clk);
      ctrl_ld_out_clk_delay  = 1'b0;
      @(negedge rx_clk);
    end

    if (DATA_ODELAY_MODE == "VAR_LOAD") begin
      ctrl_ld_out_data_delay = 1'b1;
      @(negedge rx_clk);
      ctrl_ld_out_data_delay = 1'b0;
      @(negedge rx_clk);
    end

    test.end_test();




    test.start_test("Load IO delays");


    Burst(2,1);

    test.end_test();





    test.start_test("Test MIMO");


    $display("Wait align 1");
    while (!rx_aligned) begin
      Burst(1,1);
    end


    $display("Burst 1 (MIMO)");
    TestBurst(30, 1);


    $display("Reset 2");
    Reset();


    $display("Wait align 2");
    while (!rx_aligned) begin
      Burst(1,1);
    end


    $display("Burst 2 (MIMO)");
    TestBurst(23, 1);

    test.end_test();




    test.start_test("Test SISO (transmit channel 0)");

    tx_ch <= 1'b0;


    $display("Reset 3");
    Reset();


    $display("Wait align 3");
    while (!rx_aligned) Burst(1,0);


    $display("Burst 3 (SISO, Ch 0)");
    TestBurst(25, 0);


    $display("Reset 4");
    Reset();


    $display("Wait align 4");
    while (!rx_aligned) Burst(1,0);


    $display("Burst 4 (SISO, Ch 0)");
    TestBurst(27, 0);

    test.end_test();




    test.start_test("Test SISO (transmit channel 1)");

    tx_ch <= 1'b1;


    $display("Reset 5");
    Reset();


    $display("Wait align 5");
    while (!rx_aligned) Burst(1,0);


    $display("Burst 5 (SISO, Ch 1)");
    TestBurst(25, 0);


    $display("Reset 6");
    Reset();


    $display("Wait align 6");
    while (!rx_aligned) Burst(1,0);


    $display("Burst 6 (SISO, Ch 1)");
    TestBurst(27, 0);

    test.end_test();




    test.start_test("Test Idle then SISO");

    tx_ch <= 1'b1;

    $display("Wait idle flush 6");
    while (rx_aligned) Idle(1);
    $display("Wait align 6");
    while (!rx_aligned) Burst(1,0);


    $display("Burst 6 (SISO, Ch 1)");
    TestBurst(25, 0);

    test.end_test();




    test.start_test("Test Idle then MIMO");

    tx_ch <= 1'b1;

    $display("Wait idle flush 7");
    while (rx_aligned) Idle(1);
    $display("Wait align 7");
    while (!rx_aligned) begin
      Burst(1,1);
    end


    $display("Burst 7 (SISO, Ch 1)");
    TestBurst(25, 1);

    test.end_test();




    test.end_tb();
  end : main






















  reg first_rx_check = 1'b1;
  reg [11:0] rx_i0_del1, rx_i0_del2;
  reg [11:0] rx_q0_del1, rx_q0_del2;
  reg [11:0] rx_i1_del1, rx_i1_del2;
  reg [11:0] rx_q1_del1, rx_q1_del2;

  always @(posedge radio_clk)
  begin
    if (check_enabled) begin
      if (!first_rx_check) begin

        if (mimo) begin


          if (rx_i0[11:8] != 4'hA || rx_q0[11:8] != 4'hB) begin
            $fatal(1, "ERROR in %m: Rx channel 0 didn't have expected A/B prefix in MIMO mode");
          end


          if (rx_i1[11:8] != 4'hC || rx_q1[11:8] != 4'hD) begin
            $fatal(1, "ERROR in %m: Rx channel 1 didn't have expected C/D in MIMO mode");
          end


          if (! (rx_i0[7:0] == rx_q0[7:0] &&
                 rx_i0[7:0] == rx_i1[7:0] &&
                 rx_i0[7:0] == rx_q1[7:0]) ) begin
            $fatal(1, "ERROR in %m: Rx data counts didn't match on all outputs in MIMO mode");
          end


          if (rx_i0[7:0] != rx_i0_del1[7:0] + 8'd1 || rx_q0[7:0] != rx_q0_del1[7:0] + 8'd1 ||
              rx_i1[7:0] != rx_i1_del1[7:0] + 8'd1 || rx_q1[7:0] != rx_q1_del1[7:0] + 8'd1) begin
            $fatal(1, "ERROR in %m: Rx data count didn't increment as expected");
          end

        end else begin


          if (rx_i0 != rx_i1 || rx_q0 != rx_q1) begin
            $fatal(1, "ERROR in %m: Rx channel 0 and 1 don't match in SISO mode");
          end



          if (!((rx_i0[11:8] == 4'hA && rx_q0[11:8] == 4'hB) ||
                (rx_i0[11:8] == 4'hC && rx_q0[11:8] == 4'hD))) begin
            $fatal(1, "ERROR in %m: Rx data didn't have expected A/B or C/D prefix in SISO mode");
          end



          if (!((rx_i0[11:8] == 4'hA && rx_i0_del1[11:8] == 4'hC) ||
                (rx_i0[11:8] == 4'hC && rx_i0_del1[11:8] == 4'hA) ||
                (rx_q0[11:8] == 4'hB && rx_q0_del1[11:8] == 4'hD) ||
                (rx_q0[11:8] == 4'hD && rx_q0_del1[11:8] == 4'hB))) begin
            $fatal(1, "ERROR in %m: Rx data not toggling between channel data in SISO mode");
          end



          if (rx_i0[7:0] != rx_q0[7:0]) begin
            $fatal(1, "ERROR in %m: Rx data counts didn't match on all outputs in SISO mode");
          end



          if (!(
              rx_i0[7:0] != rx_i0_del2[7:0] + 8'd1 && (rx_i0[7:0] == rx_i0_del1[7:0] || rx_i0[7:0] == rx_i0_del1[7:0] + 8'd1) &&
              rx_q0[7:0] != rx_q0_del2[7:0] + 8'd1 && (rx_q0[7:0] == rx_q0_del1[7:0] || rx_q0[7:0] == rx_q0_del1[7:0] + 8'd1)
            )) begin
            $fatal(1, "ERROR in %m: Rx data count didn't increment as expected");
          end

        end
      end



      first_rx_check <= 1'b0;

    end else begin
      first_rx_check <= 1'b1;
    end


    rx_i0_del1 <= rx_i0;
    rx_q0_del1 <= rx_q0;
    rx_i1_del1 <= rx_i1;
    rx_q1_del1 <= rx_q1;
    rx_i0_del2 <= rx_i0_del2;
    rx_q0_del2 <= rx_q0_del2;
    rx_i1_del2 <= rx_i1_del2;
    rx_q1_del2 <= rx_q1_del2;
  end











  reg first_tx_check;
  reg [11:0] tx_i0_del1;
  reg [11:0] tx_q0_del1;
  reg [11:0] tx_i1_del1;
  reg [11:0] tx_q1_del1;
  reg        tx_frame_del1;

  reg [11:0] tx_i0_check;
  reg [11:0] tx_q0_check;
  reg [11:0] tx_i1_check;
  reg [11:0] tx_q1_check;
  reg [7:0]  tx_frame_check;


  always @(posedge tx_clk_p)
  begin
    tx_frame_del1 <= tx_frame_p;
  end


  always @(posedge tx_clk_p)
  begin
    if (tx_frame_p && !tx_frame_del1) begin





      tx_i0_check[11:6] <= tx_d_p;
      tx_frame_check[7] <= tx_frame_p;
      @(posedge tx_clk_n);
      tx_q0_check[11:6] <= tx_d_p;
      tx_frame_check[6] <= tx_frame_p;
      @(posedge tx_clk_p);
      tx_i0_check[5:0] <= tx_d_p;
      tx_frame_check[5] <= tx_frame_p;
      @(posedge tx_clk_n);
      tx_q0_check[5:0] <= tx_d_p;
      tx_frame_check[4] <= tx_frame_p;


      @(posedge tx_clk_p);
      tx_i1_check[11:6] <= tx_d_p;
      tx_frame_check[3] <= tx_frame_p;
      @(posedge tx_clk_n);
      tx_q1_check[11:6] <= tx_d_p;
      tx_frame_check[2] <= tx_frame_p;
      @(posedge tx_clk_p);
      tx_i1_check[5:0] <= tx_d_p;
      tx_frame_check[1] <= tx_frame_p;
      @(posedge tx_clk_n);
      tx_q1_check[5:0] <= tx_d_p;
      tx_frame_check[0] <= tx_frame_p;

      #1

      if (check_enabled) begin
        if (!first_tx_check) begin

          if (mimo) begin





            if (tx_frame_check != 8'b11110000) begin
              $fatal(1, "ERROR @%0t in %m: Tx frame was not correct in MIMO mode", $time);
            end


            if (tx_i0_check[11:8] != 4'hA || tx_q0_check[11:8] != 4'hB) begin
              $fatal(1, "ERROR @%0t in %m: Tx channel 0 didn't have expected A/B prefix in MIMO mode", $time);
            end


            if (tx_i1_check[11:8] != 4'hC || tx_q1_check[11:8] != 4'hD) begin
              $fatal(1, "ERROR @%0t in %m: Tx channel 1 didn't have expected C/D in MIMO mode", $time);
            end


            if (! (tx_i0_check[7:0] == tx_q0_check[7:0] &&
                   tx_i0_check[7:0] == tx_i1_check[7:0] &&
                   tx_i0_check[7:0] == tx_q1_check[7:0]) ) begin
              $fatal(1, "ERROR @%0t in %m: Rx data counts didn't match on all outputs in MIMO mode", $time);
            end


            if (tx_i0_check[7:0] != tx_i0_del1[7:0] + 8'd1 || tx_q0_check[7:0] != tx_q0_del1[7:0] + 8'd1 ||
                tx_i1_check[7:0] != tx_i1_del1[7:0] + 8'd1 || tx_q1_check[7:0] != tx_q1_del1[7:0] + 8'd1) begin
              $fatal(1, "ERROR @%0t in %m: Rx data count didn't increment as expected", $time);
            end

          end else begin





            if (tx_frame_check != 8'b11001100) begin
              $fatal(1, "ERROR @%0t in %m: Tx frame was not correct in SISO mode", $time);
            end























            if (!(

              ((tx_ch == 0 &&
                tx_i0_check[11:8] == 4'hA &&
                tx_q0_check[11:8] == 4'hB) ||
               (tx_ch == 1 &&
                tx_i0_check[11:8] == 4'hC &&
                tx_q0_check[11:8] == 4'hD)) &&

              (tx_i0_check[11:8] == tx_i1_check[11:8]  &&
               tx_q0_check[11:8] == tx_q1_check[11:8])
              )) begin
              $fatal(1, "ERROR @%0t in %m: Tx channel didn't have expected prefixes in SISO mode", $time);
            end


            if (!(
              tx_i0_check[7:0] == tx_q0_check[7:0] &&
              tx_i1_check[7:0] == tx_q1_check[7:0] &&
              tx_i0_check[7:0] == tx_i1_check[7:0] - 8'd1
              )) begin
              $fatal(1, "ERROR @%0t in %m: Tx channel data counts didn't correlate in SISO mode", $time);
            end


            if (tx_i0_check[7:0] != tx_i0_del1[7:0] + 8'd2 ||
                tx_q0_check[7:0] != tx_q0_del1[7:0] + 8'd2 ||
                tx_i1_check[7:0] != tx_i1_del1[7:0] + 8'd2 ||
                tx_q1_check[7:0] != tx_q1_del1[7:0] + 8'd2) begin
              $fatal(1, "ERROR @%0t in %m: Tx data count didn't increment as expected", $time);
            end

          end

        end else begin


          first_tx_check <= 1'b0;
        end


        tx_i0_del1 <= tx_i0_check;
        tx_q0_del1 <= tx_q0_check;
        tx_i1_del1 <= tx_i1_check;
        tx_q1_del1 <= tx_q1_check;

      end else begin
        first_tx_check <= 1'b1;

      end

    end

  end















  reg [7:0] tx_count = 0;


  always @(posedge radio_clk) begin
    tx_i0 <= { 4'hA, tx_count };
    tx_q0 <= { 4'hB, tx_count };
    tx_i1 <= { 4'hC, tx_count };
    tx_q1 <= { 4'hD, tx_count };
    tx_count <= tx_count + 7'd1;
  end






  cat_io_lvds_dual_mode #(
    .INVERT_FRAME_RX    (0),
    .INVERT_DATA_RX     (6'b00_0000),
    .INVERT_FRAME_TX    (0),
    .INVERT_DATA_TX     (6'b00_0000),
    .USE_CLOCK_IDELAY   (USE_CLOCK_IDELAY),
    .USE_DATA_IDELAY    (USE_DATA_IDELAY),
    .DATA_IDELAY_MODE   (DATA_IDELAY_MODE),
    .CLOCK_IDELAY_MODE  (CLOCK_IDELAY_MODE),
    .INPUT_CLOCK_DELAY  (INPUT_CLOCK_DELAY),
    .INPUT_DATA_DELAY   (INPUT_DATA_DELAY),
    .USE_CLOCK_ODELAY   (USE_CLOCK_ODELAY),
    .USE_DATA_ODELAY    (USE_DATA_ODELAY),
    .DATA_ODELAY_MODE   (DATA_ODELAY_MODE),
    .CLOCK_ODELAY_MODE  (CLOCK_ODELAY_MODE),
    .OUTPUT_CLOCK_DELAY (OUTPUT_CLOCK_DELAY),
    .OUTPUT_DATA_DELAY  (OUTPUT_DATA_DELAY)
  ) cat_io_lvds_dual_mode_dut (
    .clk200 (clk200),


    .a_mimo  (mimo),
    .a_tx_ch (tx_ch),


    .ctrl_clk               (rx_clk),

    .ctrl_in_data_delay     (ctrl_in_data_delay),
    .ctrl_in_clk_delay      (ctrl_in_clk_delay),
    .ctrl_ld_in_data_delay  (ctrl_ld_in_data_delay),
    .ctrl_ld_in_clk_delay   (ctrl_ld_in_clk_delay),

    .ctrl_out_data_delay    (ctrl_out_data_delay),
    .ctrl_out_clk_delay     (ctrl_out_clk_delay),
    .ctrl_ld_out_data_delay (ctrl_ld_out_data_delay),
    .ctrl_ld_out_clk_delay  (ctrl_ld_out_clk_delay),


    .radio_rst  (reset),
    .radio_clk  (radio_clk),
    .rx_aligned (rx_aligned),

    .rx_i0      (rx_i0),
    .rx_q0      (rx_q0),
    .rx_i1      (rx_i1),
    .rx_q1      (rx_q1),

    .tx_i0      (tx_i0),
    .tx_q0      (tx_q0),
    .tx_i1      (tx_i1),
    .tx_q1      (tx_q1),


    .rx_clk_p   (rx_clk),
    .rx_clk_n   (~rx_clk),
    .rx_frame_p (rx_frame),
    .rx_frame_n (~rx_frame),
    .rx_d_p     (rx_d),
    .rx_d_n     (~rx_d),

    .tx_clk_p   (tx_clk_p),
    .tx_clk_n   (tx_clk_n),
    .tx_frame_p (tx_frame_p),
    .tx_frame_n (tx_frame_n),
    .tx_d_p     (tx_d_p),
    .tx_d_n     (tx_d_n)
  );

endmodule
module cat_io_lvds_dual_mode_tb();


  `include "test_exec.svh"
  import PkgTestExec::*;

  localparam CLK_PERIOD    = 10;
  localparam CLK200_PERIOD = 2.5;

  localparam USE_CLOCK_IDELAY   = 1;
  localparam USE_DATA_IDELAY    = 1;
  localparam DATA_IDELAY_MODE   = "FIXED";
  localparam CLOCK_IDELAY_MODE  = "FIXED";
  localparam INPUT_CLOCK_DELAY  = 16;
  localparam INPUT_DATA_DELAY   = 0;
  localparam USE_CLOCK_ODELAY   = 1;
  localparam USE_DATA_ODELAY    = 1;
  localparam DATA_ODELAY_MODE   = "FIXED";
  localparam CLOCK_ODELAY_MODE  = "FIXED";
  localparam OUTPUT_CLOCK_DELAY = 31;
  localparam OUTPUT_DATA_DELAY  = 0;

  reg       check_enabled;

  reg       clk    = 0;
  reg       rx_clk = 0;
  reg       clk200 = 0;

  reg       reset;
  reg       mimo;
  reg       tx_ch;
  reg [5:0] rx_d;
  reg       rx_frame;
  reg [7:0] rx_count = 0;



  wire [11:0] i0 = { 4'hA, rx_count };
  wire [11:0] q0 = { 4'hB, rx_count };
  wire [11:0] i1 = { 4'hC, rx_count };
  wire [11:0] q1 = { 4'hD, rx_count };

  wire radio_clk;

  reg [11:0] tx_i0;
  reg [11:0] tx_q0;
  reg [11:0] tx_i1;
  reg [11:0] tx_q1;

  wire [11:0] rx_i0;
  wire [11:0] rx_q0;
  wire [11:0] rx_i1;
  wire [11:0] rx_q1;

  wire rx_aligned;

  wire        tx_clk_p, tx_clk_n;
  wire        tx_frame_p, tx_frame_n;
  wire [5:0]  tx_d_p, tx_d_n;

  reg [4:0]  ctrl_in_data_delay;
  reg [4:0]  ctrl_in_clk_delay;
  reg        ctrl_ld_in_data_delay;
  reg        ctrl_ld_in_clk_delay;

  reg [4:0]  ctrl_out_data_delay;
  reg [4:0]  ctrl_out_clk_delay;
  reg        ctrl_ld_out_data_delay;
  reg        ctrl_ld_out_clk_delay;







  always #(CLK200_PERIOD) clk200 = ~clk200;


  always #(CLK_PERIOD) clk = ~clk;


  always @(negedge clk) rx_clk <= ~rx_clk;









  task Burst(int len, logic do_mimo);
    repeat(len)
      begin
        mimo <= do_mimo;


        @(posedge clk);
        rx_d <= i0[11:6];
        rx_frame <= 1;
        @(posedge clk);
        rx_d <= q0[11:6];
        rx_frame <= 1;
        @(posedge clk);
        rx_d <= i0[5:0];
        rx_frame <= do_mimo;
        @(posedge clk);
        rx_d <= q0[5:0];
        rx_frame <= do_mimo;


        @(posedge clk);
        rx_d <= i1[11:6];
        rx_frame <= ~do_mimo;
        @(posedge clk);
        rx_d <= q1[11:6];
        rx_frame <= ~do_mimo;
        @(posedge clk);
        rx_d <= i1[5:0];
        rx_frame <= 0;
        @(posedge clk);
        rx_d <= q1[5:0];
        rx_frame <= 0;

        rx_count <= rx_count + 1;
      end
  endtask : Burst




  task Idle(int len = 100);
    rx_d     <= 0;
    rx_frame <= 0;
    repeat (len) @(posedge clk);
  endtask : Idle


  task Reset(int num_cycles = 20);
    reset <= 1;
    repeat(num_cycles) @(negedge rx_clk);
    reset <= 0;
    repeat(2) @(negedge rx_clk);
  endtask : Reset







  task TestBurst;
    input [31:0] len;
    input        do_mimo;
    begin
      if (len <= 2) begin
        $fatal(1, "ERROR @%0t in %m: In TestBurst, len must be > 2", $time);
      end



      Burst(1, do_mimo);


      check_enabled <= 1'b1;


      Burst(len-2, do_mimo);


      check_enabled <= 1'b0;


      Burst(1, do_mimo);
    end
  endtask






  initial begin : main

    test.start_tb("cat_io_lvds_dual_mode_tb");


    check_enabled <= 1'b0;
    reset = 1;
    mimo  = 1;
    ctrl_in_clk_delay      = INPUT_CLOCK_DELAY;
    ctrl_in_data_delay     = INPUT_DATA_DELAY;
    ctrl_ld_in_data_delay  = 1'b0;
    ctrl_ld_in_clk_delay   = 1'b0;
    ctrl_out_clk_delay     = OUTPUT_CLOCK_DELAY;
    ctrl_out_data_delay    = OUTPUT_DATA_DELAY;
    ctrl_ld_out_data_delay = 1'b0;
    ctrl_ld_out_clk_delay  = 1'b0;

    Reset();




    test.start_test("Load IO delays");

    if (CLOCK_IDELAY_MODE == "VAR_LOAD") begin
      ctrl_ld_in_clk_delay  = 1'b1;
      @(negedge rx_clk);
      ctrl_ld_in_clk_delay  = 1'b0;
      @(negedge rx_clk);
    end

    if (DATA_IDELAY_MODE == "VAR_LOAD") begin
      ctrl_ld_in_data_delay = 1'b1;
      @(negedge rx_clk);
      ctrl_ld_in_data_delay = 1'b0;
      @(negedge rx_clk);
    end

    if (CLOCK_ODELAY_MODE == "VAR_LOAD") begin
      ctrl_ld_out_clk_delay  = 1'b1;
      @(negedge rx_clk);
      ctrl_ld_out_clk_delay  = 1'b0;
      @(negedge rx_clk);
    end

    if (DATA_ODELAY_MODE == "VAR_LOAD") begin
      ctrl_ld_out_data_delay = 1'b1;
      @(negedge rx_clk);
      ctrl_ld_out_data_delay = 1'b0;
      @(negedge rx_clk);
    end

    test.end_test();




    test.start_test("Load IO delays");


    Burst(2,1);

    test.end_test();





    test.start_test("Test MIMO");


    $display("Wait align 1");
    while (!rx_aligned) begin
      Burst(1,1);
    end


    $display("Burst 1 (MIMO)");
    TestBurst(30, 1);


    $display("Reset 2");
    Reset();


    $display("Wait align 2");
    while (!rx_aligned) begin
      Burst(1,1);
    end


    $display("Burst 2 (MIMO)");
    TestBurst(23, 1);

    test.end_test();




    test.start_test("Test SISO (transmit channel 0)");

    tx_ch <= 1'b0;


    $display("Reset 3");
    Reset();


    $display("Wait align 3");
    while (!rx_aligned) Burst(1,0);


    $display("Burst 3 (SISO, Ch 0)");
    TestBurst(25, 0);


    $display("Reset 4");
    Reset();


    $display("Wait align 4");
    while (!rx_aligned) Burst(1,0);


    $display("Burst 4 (SISO, Ch 0)");
    TestBurst(27, 0);

    test.end_test();




    test.start_test("Test SISO (transmit channel 1)");

    tx_ch <= 1'b1;


    $display("Reset 5");
    Reset();


    $display("Wait align 5");
    while (!rx_aligned) Burst(1,0);


    $display("Burst 5 (SISO, Ch 1)");
    TestBurst(25, 0);


    $display("Reset 6");
    Reset();


    $display("Wait align 6");
    while (!rx_aligned) Burst(1,0);


    $display("Burst 6 (SISO, Ch 1)");
    TestBurst(27, 0);

    test.end_test();




    test.start_test("Test Idle then SISO");

    tx_ch <= 1'b1;

    $display("Wait idle flush 6");
    while (rx_aligned) Idle(1);
    $display("Wait align 6");
    while (!rx_aligned) Burst(1,0);


    $display("Burst 6 (SISO, Ch 1)");
    TestBurst(25, 0);

    test.end_test();




    test.start_test("Test Idle then MIMO");

    tx_ch <= 1'b1;

    $display("Wait idle flush 7");
    while (rx_aligned) Idle(1);
    $display("Wait align 7");
    while (!rx_aligned) begin
      Burst(1,1);
    end


    $display("Burst 7 (SISO, Ch 1)");
    TestBurst(25, 1);

    test.end_test();




    test.end_tb();
  end : main






















  reg first_rx_check = 1'b1;
  reg [11:0] rx_i0_del1, rx_i0_del2;
  reg [11:0] rx_q0_del1, rx_q0_del2;
  reg [11:0] rx_i1_del1, rx_i1_del2;
  reg [11:0] rx_q1_del1, rx_q1_del2;

  always @(posedge radio_clk)
  begin
    if (check_enabled) begin
      if (!first_rx_check) begin

        if (mimo) begin


          if (rx_i0[11:8] != 4'hA || rx_q0[11:8] != 4'hB) begin
            $fatal(1, "ERROR in %m: Rx channel 0 didn't have expected A/B prefix in MIMO mode");
          end


          if (rx_i1[11:8] != 4'hC || rx_q1[11:8] != 4'hD) begin
            $fatal(1, "ERROR in %m: Rx channel 1 didn't have expected C/D in MIMO mode");
          end


          if (! (rx_i0[7:0] == rx_q0[7:0] &&
                 rx_i0[7:0] == rx_i1[7:0] &&
                 rx_i0[7:0] == rx_q1[7:0]) ) begin
            $fatal(1, "ERROR in %m: Rx data counts didn't match on all outputs in MIMO mode");
          end


          if (rx_i0[7:0] != rx_i0_del1[7:0] + 8'd1 || rx_q0[7:0] != rx_q0_del1[7:0] + 8'd1 ||
              rx_i1[7:0] != rx_i1_del1[7:0] + 8'd1 || rx_q1[7:0] != rx_q1_del1[7:0] + 8'd1) begin
            $fatal(1, "ERROR in %m: Rx data count didn't increment as expected");
          end

        end else begin


          if (rx_i0 != rx_i1 || rx_q0 != rx_q1) begin
            $fatal(1, "ERROR in %m: Rx channel 0 and 1 don't match in SISO mode");
          end



          if (!((rx_i0[11:8] == 4'hA && rx_q0[11:8] == 4'hB) ||
                (rx_i0[11:8] == 4'hC && rx_q0[11:8] == 4'hD))) begin
            $fatal(1, "ERROR in %m: Rx data didn't have expected A/B or C/D prefix in SISO mode");
          end



          if (!((rx_i0[11:8] == 4'hA && rx_i0_del1[11:8] == 4'hC) ||
                (rx_i0[11:8] == 4'hC && rx_i0_del1[11:8] == 4'hA) ||
                (rx_q0[11:8] == 4'hB && rx_q0_del1[11:8] == 4'hD) ||
                (rx_q0[11:8] == 4'hD && rx_q0_del1[11:8] == 4'hB))) begin
            $fatal(1, "ERROR in %m: Rx data not toggling between channel data in SISO mode");
          end



          if (rx_i0[7:0] != rx_q0[7:0]) begin
            $fatal(1, "ERROR in %m: Rx data counts didn't match on all outputs in SISO mode");
          end



          if (!(
              rx_i0[7:0] != rx_i0_del2[7:0] + 8'd1 && (rx_i0[7:0] == rx_i0_del1[7:0] || rx_i0[7:0] == rx_i0_del1[7:0] + 8'd1) &&
              rx_q0[7:0] != rx_q0_del2[7:0] + 8'd1 && (rx_q0[7:0] == rx_q0_del1[7:0] || rx_q0[7:0] == rx_q0_del1[7:0] + 8'd1)
            )) begin
            $fatal(1, "ERROR in %m: Rx data count didn't increment as expected");
          end

        end
      end



      first_rx_check <= 1'b0;

    end else begin
      first_rx_check <= 1'b1;
    end


    rx_i0_del1 <= rx_i0;
    rx_q0_del1 <= rx_q0;
    rx_i1_del1 <= rx_i1;
    rx_q1_del1 <= rx_q1;
    rx_i0_del2 <= rx_i0_del2;
    rx_q0_del2 <= rx_q0_del2;
    rx_i1_del2 <= rx_i1_del2;
    rx_q1_del2 <= rx_q1_del2;
  end











  reg first_tx_check;
  reg [11:0] tx_i0_del1;
  reg [11:0] tx_q0_del1;
  reg [11:0] tx_i1_del1;
  reg [11:0] tx_q1_del1;
  reg        tx_frame_del1;

  reg [11:0] tx_i0_check;
  reg [11:0] tx_q0_check;
  reg [11:0] tx_i1_check;
  reg [11:0] tx_q1_check;
  reg [7:0]  tx_frame_check;


  always @(posedge tx_clk_p)
  begin
    tx_frame_del1 <= tx_frame_p;
  end


  always @(posedge tx_clk_p)
  begin
    if (tx_frame_p && !tx_frame_del1) begin





      tx_i0_check[11:6] <= tx_d_p;
      tx_frame_check[7] <= tx_frame_p;
      @(posedge tx_clk_n);
      tx_q0_check[11:6] <= tx_d_p;
      tx_frame_check[6] <= tx_frame_p;
      @(posedge tx_clk_p);
      tx_i0_check[5:0] <= tx_d_p;
      tx_frame_check[5] <= tx_frame_p;
      @(posedge tx_clk_n);
      tx_q0_check[5:0] <= tx_d_p;
      tx_frame_check[4] <= tx_frame_p;


      @(posedge tx_clk_p);
      tx_i1_check[11:6] <= tx_d_p;
      tx_frame_check[3] <= tx_frame_p;
      @(posedge tx_clk_n);
      tx_q1_check[11:6] <= tx_d_p;
      tx_frame_check[2] <= tx_frame_p;
      @(posedge tx_clk_p);
      tx_i1_check[5:0] <= tx_d_p;
      tx_frame_check[1] <= tx_frame_p;
      @(posedge tx_clk_n);
      tx_q1_check[5:0] <= tx_d_p;
      tx_frame_check[0] <= tx_frame_p;

      #1

      if (check_enabled) begin
        if (!first_tx_check) begin

          if (mimo) begin





            if (tx_frame_check != 8'b11110000) begin
              $fatal(1, "ERROR @%0t in %m: Tx frame was not correct in MIMO mode", $time);
            end


            if (tx_i0_check[11:8] != 4'hA || tx_q0_check[11:8] != 4'hB) begin
              $fatal(1, "ERROR @%0t in %m: Tx channel 0 didn't have expected A/B prefix in MIMO mode", $time);
            end


            if (tx_i1_check[11:8] != 4'hC || tx_q1_check[11:8] != 4'hD) begin
              $fatal(1, "ERROR @%0t in %m: Tx channel 1 didn't have expected C/D in MIMO mode", $time);
            end


            if (! (tx_i0_check[7:0] == tx_q0_check[7:0] &&
                   tx_i0_check[7:0] == tx_i1_check[7:0] &&
                   tx_i0_check[7:0] == tx_q1_check[7:0]) ) begin
              $fatal(1, "ERROR @%0t in %m: Rx data counts didn't match on all outputs in MIMO mode", $time);
            end


            if (tx_i0_check[7:0] != tx_i0_del1[7:0] + 8'd1 || tx_q0_check[7:0] != tx_q0_del1[7:0] + 8'd1 ||
                tx_i1_check[7:0] != tx_i1_del1[7:0] + 8'd1 || tx_q1_check[7:0] != tx_q1_del1[7:0] + 8'd1) begin
              $fatal(1, "ERROR @%0t in %m: Rx data count didn't increment as expected", $time);
            end

          end else begin





            if (tx_frame_check != 8'b11001100) begin
              $fatal(1, "ERROR @%0t in %m: Tx frame was not correct in SISO mode", $time);
            end























            if (!(

              ((tx_ch == 0 &&
                tx_i0_check[11:8] == 4'hA &&
                tx_q0_check[11:8] == 4'hB) ||
               (tx_ch == 1 &&
                tx_i0_check[11:8] == 4'hC &&
                tx_q0_check[11:8] == 4'hD)) &&

              (tx_i0_check[11:8] == tx_i1_check[11:8]  &&
               tx_q0_check[11:8] == tx_q1_check[11:8])
              )) begin
              $fatal(1, "ERROR @%0t in %m: Tx channel didn't have expected prefixes in SISO mode", $time);
            end


            if (!(
              tx_i0_check[7:0] == tx_q0_check[7:0] &&
              tx_i1_check[7:0] == tx_q1_check[7:0] &&
              tx_i0_check[7:0] == tx_i1_check[7:0] - 8'd1
              )) begin
              $fatal(1, "ERROR @%0t in %m: Tx channel data counts didn't correlate in SISO mode", $time);
            end


            if (tx_i0_check[7:0] != tx_i0_del1[7:0] + 8'd2 ||
                tx_q0_check[7:0] != tx_q0_del1[7:0] + 8'd2 ||
                tx_i1_check[7:0] != tx_i1_del1[7:0] + 8'd2 ||
                tx_q1_check[7:0] != tx_q1_del1[7:0] + 8'd2) begin
              $fatal(1, "ERROR @%0t in %m: Tx data count didn't increment as expected", $time);
            end

          end

        end else begin


          first_tx_check <= 1'b0;
        end


        tx_i0_del1 <= tx_i0_check;
        tx_q0_del1 <= tx_q0_check;
        tx_i1_del1 <= tx_i1_check;
        tx_q1_del1 <= tx_q1_check;

      end else begin
        first_tx_check <= 1'b1;

      end

    end

  end















  reg [7:0] tx_count = 0;


  always @(posedge radio_clk) begin
    tx_i0 <= { 4'hA, tx_count };
    tx_q0 <= { 4'hB, tx_count };
    tx_i1 <= { 4'hC, tx_count };
    tx_q1 <= { 4'hD, tx_count };
    tx_count <= tx_count + 7'd1;
  end






  cat_io_lvds_dual_mode #(
    .INVERT_FRAME_RX    (0),
    .INVERT_DATA_RX     (6'b00_0000),
    .INVERT_FRAME_TX    (0),
    .INVERT_DATA_TX     (6'b00_0000),
    .USE_CLOCK_IDELAY   (USE_CLOCK_IDELAY),
    .USE_DATA_IDELAY    (USE_DATA_IDELAY),
    .DATA_IDELAY_MODE   (DATA_IDELAY_MODE),
    .CLOCK_IDELAY_MODE  (CLOCK_IDELAY_MODE),
    .INPUT_CLOCK_DELAY  (INPUT_CLOCK_DELAY),
    .INPUT_DATA_DELAY   (INPUT_DATA_DELAY),
    .USE_CLOCK_ODELAY   (USE_CLOCK_ODELAY),
    .USE_DATA_ODELAY    (USE_DATA_ODELAY),
    .DATA_ODELAY_MODE   (DATA_ODELAY_MODE),
    .CLOCK_ODELAY_MODE  (CLOCK_ODELAY_MODE),
    .OUTPUT_CLOCK_DELAY (OUTPUT_CLOCK_DELAY),
    .OUTPUT_DATA_DELAY  (OUTPUT_DATA_DELAY)
  ) cat_io_lvds_dual_mode_dut (
    .clk200 (clk200),


    .a_mimo  (mimo),
    .a_tx_ch (tx_ch),


    .ctrl_clk               (rx_clk),

    .ctrl_in_data_delay     (ctrl_in_data_delay),
    .ctrl_in_clk_delay      (ctrl_in_clk_delay),
    .ctrl_ld_in_data_delay  (ctrl_ld_in_data_delay),
    .ctrl_ld_in_clk_delay   (ctrl_ld_in_clk_delay),

    .ctrl_out_data_delay    (ctrl_out_data_delay),
    .ctrl_out_clk_delay     (ctrl_out_clk_delay),
    .ctrl_ld_out_data_delay (ctrl_ld_out_data_delay),
    .ctrl_ld_out_clk_delay  (ctrl_ld_out_clk_delay),


    .radio_rst  (reset),
    .radio_clk  (radio_clk),
    .rx_aligned (rx_aligned),

    .rx_i0      (rx_i0),
    .rx_q0      (rx_q0),
    .rx_i1      (rx_i1),
    .rx_q1      (rx_q1),

    .tx_i0      (tx_i0),
    .tx_q0      (tx_q0),
    .tx_i1      (tx_i1),
    .tx_q1      (tx_q1),


    .rx_clk_p   (rx_clk),
    .rx_clk_n   (~rx_clk),
    .rx_frame_p (rx_frame),
    .rx_frame_n (~rx_frame),
    .rx_d_p     (rx_d),
    .rx_d_n     (~rx_d),

    .tx_clk_p   (tx_clk_p),
    .tx_clk_n   (tx_clk_n),
    .tx_frame_p (tx_frame_p),
    .tx_frame_n (tx_frame_n),
    .tx_d_p     (tx_d_p),
    .tx_d_n     (tx_d_n)
  );

endmodule