data/full_repos/permissive/159555381/counter.v
 line:34: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/159555381/counter.v:25: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159555381/counter.v:30: Unsupported: Ignoring delay on this delayed statement.\n   #15 clr = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/counter.v:31: Unsupported: Ignoring delay on this delayed statement.\n   #30 clr = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/counter.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #35 clr = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/counter.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #100 clr = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/counter.v:34: Unsupported: Ignoring delay on this delayed statement.\n   #10 $finish;\n   ^\n%Error: data/full_repos/permissive/159555381/counter.v:38: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("counter.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/159555381/counter.v:39: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0, wb);\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/159555381/counter.v:40: Unsupported or unknown PLI call: $monitor\n   $monitor($time,,,"Count : %d\\n", out);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/159555381/counter.v:40: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   $monitor($time,,,"Count : %d\\n", out);\n                  ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module count (
	output reg [7:0] count,
	input clr, clk) ;
	always @(*)
		if(clr)
		count <= 0;
	always @(negedge clk) 
		count <= count + 1;
endmodule
module count (
	output reg [7:0] count,
	input clr, clk) ;

	always @(*)
		if(clr)
		count <= 0;
	always @(negedge clk) 
		count <= count + 1;
endmodule