data/full_repos/permissive/19016904/rtl/ram.v
 line:27: before: "pclk"
1: b'%Warning-WIDTH: data/full_repos/permissive/19016904/rtl/ram.v:18: Bit extraction of array[255:0] requires 8 bit index, not 12 bits.\n                                                                : ... In instance ram\n            rom[addr] <= data_in;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/19016904/rtl/ram.v:19: Bit extraction of array[255:0] requires 8 bit index, not 12 bits.\n                                                                : ... In instance ram\n        data_out <= rom[addr];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/19016904/rtl/ram.v:20: Bit extraction of array[255:0] requires 8 bit index, not 12 bits.\n                                                                : ... In instance ram\n        rom_out <= rom[rom_addr];\n                      ^\n%Error: Exiting due to 3 warning(s)\n'
module ram (clk, addr, data_in, write_en, data_out, rom_addr, rom_out);
    parameter ADDR_SIZE = 12;
    parameter WORD_SIZE = 16;
    parameter ROM_SIZE = 256;  
    
    input wire clk, write_en;
    input wire [ADDR_SIZE-1:0] addr;
    input wire [ADDR_SIZE-1:0] rom_addr;
    input wire [WORD_SIZE-1:0] data_in;
    output reg [WORD_SIZE-1:0] data_out;
    output reg [WORD_SIZE-1:0] rom_out;
    
    
    reg [WORD_SIZE-1:0] rom [ROM_SIZE-1:0];
    
    always @(negedge clk) begin
        if(write_en)
            rom[addr] <= data_in;
        data_out <= rom[addr];
        rom_out <= rom[rom_addr];
    end
        
    initial
        $readmemh("data/ram.txt",rom);
        
endmodule
module ram (clk, addr, data_in, write_en, data_out, rom_addr, rom_out);

    parameter ADDR_SIZE = 12;
    parameter WORD_SIZE = 16;
    parameter ROM_SIZE = 256;  
    
    input wire clk, write_en;
    input wire [ADDR_SIZE-1:0] addr;
    input wire [ADDR_SIZE-1:0] rom_addr;
    input wire [WORD_SIZE-1:0] data_in;
    output reg [WORD_SIZE-1:0] data_out;
    output reg [WORD_SIZE-1:0] rom_out;
    
    
    reg [WORD_SIZE-1:0] rom [ROM_SIZE-1:0];
    
    always @(negedge clk) begin
        if(write_en)
            rom[addr] <= data_in;
        data_out <= rom[addr];
        rom_out <= rom[rom_addr];
    end
        
    initial
        $readmemh("data/ram.txt",rom);
        
endmodule