data/full_repos/permissive/169266176/basic_rom.v
data/verilator_xmls/edcc2068-ba2b-4b03-844c-bcf423ced6ef.xml
module basic_rom(
    input wire clk,
    input wire [13:0] address_in,
    output wire [7:0] data_out,
    input wire cs
    );

(* ROM_STYLE="BLOCK" *)
reg [7:0] basic [0:16383];
reg [7:0] data;
reg cs_prev=1'b1;
wire enable;

always@(posedge clk)
	if(enable)
		data<=basic[address_in];

always@(posedge clk)
	cs_prev<=cs;

assign enable=~cs&cs_prev;
assign data_out=(~cs)?data:8'hff;

initial begin
$readmemh("basic.hex",basic);
end

endmodule
module basic_rom(
    input wire clk,
    input wire [13:0] address_in,
    output wire [7:0] data_out,
    input wire cs
    );


(* ROM_STYLE="BLOCK" *)
reg [7:0] basic [0:16383];
reg [7:0] data;
reg cs_prev=1'b1;
wire enable;

always@(posedge clk)
	if(enable)
		data<=basic[address_in];

always@(posedge clk)
	cs_prev<=cs;

assign enable=~cs&cs_prev;
assign data_out=(~cs)?data:8'hff;

initial begin
$readmemh("basic.hex",basic);
end

endmodule