data/full_repos/permissive/20203077/right_shift_register_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/20203077/right_shift_register_test.v:61: Unsupported: Ignoring delay on this delayed statement.\n            clk <= 1; # 5; clk <= 0; # 5;\n                      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20203077/right_shift_register_test.v:61: Unsupported: Ignoring delay on this delayed statement.\n            clk <= 1; # 5; clk <= 0; # 5;\n                                     ^\n%Error: data/full_repos/permissive/20203077/right_shift_register_test.v:37: Cannot find file containing module: \'right_shift_register\'\n right_shift_register uut (\n ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20203077,data/full_repos/permissive/20203077/right_shift_register\n             data/full_repos/permissive/20203077,data/full_repos/permissive/20203077/right_shift_register.v\n             data/full_repos/permissive/20203077,data/full_repos/permissive/20203077/right_shift_register.sv\n             right_shift_register\n             right_shift_register.v\n             right_shift_register.sv\n             obj_dir/right_shift_register\n             obj_dir/right_shift_register.v\n             obj_dir/right_shift_register.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module right_shift_register_test;


	reg clk;
	reg enable;
	reg [15:0] in;
	reg mode;


	wire [15:0] out;


	right_shift_register uut (
		.clk(clk), 
		.enable(enable), 
		.in(in), 
		.mode(mode), 
		.out(out)
	);

	initial begin

		clk = 0;
		enable = 0;
		in = 0;
		mode = 0;
        

		enable = 0;
		mode = 1;
		in = 16'b1001011010010110;
	end
    

    always
        begin
            clk <= 1; # 5; clk <= 0; # 5;
        end
      
endmodule
module right_shift_register_test;



	reg clk;
	reg enable;
	reg [15:0] in;
	reg mode;


	wire [15:0] out;


	right_shift_register uut (
		.clk(clk), 
		.enable(enable), 
		.in(in), 
		.mode(mode), 
		.out(out)
	);

	initial begin

		clk = 0;
		enable = 0;
		in = 0;
		mode = 0;
        

		enable = 0;
		mode = 1;
		in = 16'b1001011010010110;
	end
    

    always
        begin
            clk <= 1; # 5; clk <= 0; # 5;
        end
      
endmodule