data/full_repos/permissive/165110048/code/vga_sync.v
data/verilator_xmls/b297b2f0-88af-4af5-bbc3-f358b8befe29.xml
module vga_sync(
    input vga_clk,
    input reset,
    output reg hsync,
    output reg vsync,
    output video_on,
    output reg [9:0] pixel_x,
    output reg [9:0] pixel_y
    );
	

	reg [9:0] h_count;
	reg [9:0] v_count;
	wire [9:0] row;
	wire [9:0] col;

	wire v_sync, h_sync;

	wire h_end, v_end, pixel_tick;
	
	always @(posedge vga_clk) begin
		if (reset) h_count <= 10'h0;
		else if(h_count == 10'd799)
			h_count <= 10'h0;
		else h_count <= h_count + 10'h1;

		pixel_x = col;
		pixel_y = row;
		hsync = h_sync;
		vsync = v_sync;
	end
	
	always @(posedge vga_clk or posedge reset) begin
		if(reset) v_count <= 10'h0;
		else if (h_count == 10'd799) begin
			if(v_count == 10'd524) v_count <= 10'h0;
			else v_count <= v_count + 10'h1;
		end
	end


	assign row = v_count - 10'd35;
	assign col = h_count - 10'd143;
	assign h_sync = (h_count > 10'd95);
	assign v_sync = (v_count > 10'd1);
	assign video_on = (
		h_count > 10'd142 &&
		h_count < 10'd783 &&
		v_count > 10'd34 &&
		v_count < 10'd515);
endmodule
module vga_sync(
    input vga_clk,
    input reset,
    output reg hsync,
    output reg vsync,
    output video_on,
    output reg [9:0] pixel_x,
    output reg [9:0] pixel_y
    );

	

	reg [9:0] h_count;
	reg [9:0] v_count;
	wire [9:0] row;
	wire [9:0] col;

	wire v_sync, h_sync;

	wire h_end, v_end, pixel_tick;
	
	always @(posedge vga_clk) begin
		if (reset) h_count <= 10'h0;
		else if(h_count == 10'd799)
			h_count <= 10'h0;
		else h_count <= h_count + 10'h1;

		pixel_x = col;
		pixel_y = row;
		hsync = h_sync;
		vsync = v_sync;
	end
	
	always @(posedge vga_clk or posedge reset) begin
		if(reset) v_count <= 10'h0;
		else if (h_count == 10'd799) begin
			if(v_count == 10'd524) v_count <= 10'h0;
			else v_count <= v_count + 10'h1;
		end
	end


	assign row = v_count - 10'd35;
	assign col = h_count - 10'd143;
	assign h_sync = (h_count > 10'd95);
	assign v_sync = (v_count > 10'd1);
	assign video_on = (
		h_count > 10'd142 &&
		h_count < 10'd783 &&
		v_count > 10'd34 &&
		v_count < 10'd515);
endmodule