data/full_repos/permissive/20270692/labs/lab8/t/t_flipflop_tb.v
 line:77: before: "$"
1: b'%Error: data/full_repos/permissive/20270692/labs/lab8/t/t_flipflop_tb.v:7: Cannot find include file: t_flipflop.v\n`include "t_flipflop.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab8/t,data/full_repos/permissive/20270692/t_flipflop.v\n             data/full_repos/permissive/20270692/labs/lab8/t,data/full_repos/permissive/20270692/t_flipflop.v.v\n             data/full_repos/permissive/20270692/labs/lab8/t,data/full_repos/permissive/20270692/t_flipflop.v.sv\n             t_flipflop.v\n             t_flipflop.v.v\n             t_flipflop.v.sv\n             obj_dir/t_flipflop.v\n             obj_dir/t_flipflop.v.v\n             obj_dir/t_flipflop.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab8/t/t_flipflop_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  initial #1000 $finish;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab8/t/t_flipflop_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    forever #5 t_clock=~t_clock;\n            ^\n%Error: data/full_repos/permissive/20270692/labs/lab8/t/t_flipflop_tb.v:49: Unsupported or unknown PLI call: $monitor\n    $monitor("time=%0d", $time,, "T=%b REset=%b q=%b", T, REset, q);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab8/t/t_flipflop_tb.v:49: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    $monitor("time=%0d", $time,, "T=%b REset=%b q=%b", T, REset, q);\n                               ^\n%Error: data/full_repos/permissive/20270692/labs/lab8/t/t_flipflop_tb.v:50: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("t_flipflop.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab8/t/t_flipflop_tb.v:51: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module t_ff_tb (T, REset);

  output T, REset;
  reg T, REset;

  wire q;

  reg t_T [5000:0];
  reg t_REset [5000:0];
  reg t_clock;
  reg [31:0] vectornum;

  t_ff I0 (q, T, t_clock, REset);

  initial #1000 $finish;

  initial
  begin
    t_clock=0;
    forever #5 t_clock=~t_clock;
  end

  initial
  begin
    $readmemb("./bit_str_a_0.txt",t_T);
    $readmemb("./bit_str_a_1.txt",t_REset);
    vectornum=0;
  end

  always @(negedge t_clock)
  begin
    T<=t_T[vectornum];
    REset<=t_REset[vectornum];
    vectornum<=vectornum+1;
  end

  initial
  begin
    $monitor("time=%0d", $time,, "T=%b REset=%b q=%b", T, REset, q);
    $dumpfile("t_flipflop.vcd");
    $dumpvars;
  end

endmodule
module t_ff_tb (T, REset);


  output T, REset;
  reg T, REset;

  wire q;

  reg t_T [5000:0];
  reg t_REset [5000:0];
  reg t_clock;
  reg [31:0] vectornum;

  t_ff I0 (q, T, t_clock, REset);

  initial #1000 $finish;

  initial
  begin
    t_clock=0;
    forever #5 t_clock=~t_clock;
  end

  initial
  begin
    $readmemb("./bit_str_a_0.txt",t_T);
    $readmemb("./bit_str_a_1.txt",t_REset);
    vectornum=0;
  end

  always @(negedge t_clock)
  begin
    T<=t_T[vectornum];
    REset<=t_REset[vectornum];
    vectornum<=vectornum+1;
  end

  initial
  begin
    $monitor("time=%0d", $time,, "T=%b REset=%b q=%b", T, REset, q);
    $dumpfile("t_flipflop.vcd");
    $dumpvars;
  end

endmodule