data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n             MBScore_const.v\n             MBScore_const.v.v\n             MBScore_const.v.sv\n             obj_dir/MBScore_const.v\n             obj_dir/MBScore_const.v.v\n             obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:6: Define or directive not defined: \'`INT_SEL_WIDTH\'\n    input [`INT_SEL_WIDTH-1:0]      int_vec,\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:10: Define or directive not defined: \'`ADDR_WIDTH\'\n    output reg [`ADDR_WIDTH-1:0]    int_addr,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:30: Define or directive not defined: \'`INT_KEYBOARD\'\n        if(int_vec_r == `INT_KEYBOARD)\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:30: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if(int_vec_r == `INT_KEYBOARD)\n                                     ^\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:31: Define or directive not defined: \'`INT_KEYBOARD_ADDR\'\n            int_addr = `INT_KEYBOARD_ADDR;\n                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:33: Define or directive not defined: \'`INT_MOUSE\'\n        if(int_vec_r == `INT_MOUSE)\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:34: Define or directive not defined: \'`INT_MOUSE_ADDR\'\n            int_addr = `INT_MOUSE_ADDR;\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:36: Define or directive not defined: \'`INT_UART\'\n        if(int_vec_r == `INT_UART)\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:37: Define or directive not defined: \'`INT_UART_ADDR\'\n            int_addr = `INT_UART_ADDR;\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:39: Define or directive not defined: \'`INT_STORAGE\'\n        if(int_vec_r == `INT_STORAGE)\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:40: Define or directive not defined: \'`INT_STORAGE_ADDR\'\n            int_addr = `INT_STORAGE_ADDR;\n                       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:42: Define or directive not defined: \'`INT_ETHERNET\'\n        if(int_vec_r == `INT_ETHERNET)\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:43: Define or directive not defined: \'`INT_ETHERNET_ADDR\'\n            int_addr = `INT_ETHERNET_ADDR;\n                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:51: Define or directive not defined: \'`ADDR_WIDTH\'\n        int_addr     = `ADDR_WIDTH\'d0;\n                       ^~~~~~~~~~~\n%Error: Exiting due to 15 error(s)\n'
module MBScore_interrupt_ctrl(
    input                           clk,
    input                           rst_n,
    input [`INT_SEL_WIDTH-1:0]      int_vec,
    input                           int_en_n,
    output reg                      stop,
    output reg                      setINTR,
    output reg [`ADDR_WIDTH-1:0]    int_addr,
    output reg                      int_jump
);

    reg                             int_vec_r;

    always @(int_vec)
    if(int_vec && !int_en_n)
    begin
        int_vec_r   = int_vec;
        stop        = 1'b1;
    end 
    else
    stop = 1'b0;

    always @(posedge clk)
    if(stop)
    begin
        setINTR      = 1'b1;

        if(int_vec_r == `INT_KEYBOARD)
            int_addr = `INT_KEYBOARD_ADDR;
        else
        if(int_vec_r == `INT_MOUSE)
            int_addr = `INT_MOUSE_ADDR;
        else
        if(int_vec_r == `INT_UART)
            int_addr = `INT_UART_ADDR;
        else
        if(int_vec_r == `INT_STORAGE)
            int_addr = `INT_STORAGE_ADDR;
        else
        if(int_vec_r == `INT_ETHERNET)
            int_addr = `INT_ETHERNET_ADDR;

        int_jump     = 1'b1;
    end
    else
    begin
        setINTR      = 1'b0;
        int_jump     = 1'b0;
        int_addr     = `ADDR_WIDTH'd0;
    end

endmodule
module MBScore_interrupt_ctrl(
    input                           clk,
    input                           rst_n,
    input [`INT_SEL_WIDTH-1:0]      int_vec,
    input                           int_en_n,
    output reg                      stop,
    output reg                      setINTR,
    output reg [`ADDR_WIDTH-1:0]    int_addr,
    output reg                      int_jump
);


    reg                             int_vec_r;

    always @(int_vec)
    if(int_vec && !int_en_n)
    begin
        int_vec_r   = int_vec;
        stop        = 1'b1;
    end 
    else
    stop = 1'b0;

    always @(posedge clk)
    if(stop)
    begin
        setINTR      = 1'b1;

        if(int_vec_r == `INT_KEYBOARD)
            int_addr = `INT_KEYBOARD_ADDR;
        else
        if(int_vec_r == `INT_MOUSE)
            int_addr = `INT_MOUSE_ADDR;
        else
        if(int_vec_r == `INT_UART)
            int_addr = `INT_UART_ADDR;
        else
        if(int_vec_r == `INT_STORAGE)
            int_addr = `INT_STORAGE_ADDR;
        else
        if(int_vec_r == `INT_ETHERNET)
            int_addr = `INT_ETHERNET_ADDR;

        int_jump     = 1'b1;
    end
    else
    begin
        setINTR      = 1'b0;
        int_jump     = 1'b0;
        int_addr     = `ADDR_WIDTH'd0;
    end

endmodule