data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:140: Multiple top level modules\n                                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                      : ... Top module \'draw_gold\'\nmodule draw_gold(\n       ^~~~~~~~~\n                                                                                                      : ... Top module \'draw_stone\'\nmodule draw_stone(\n       ^~~~~~~~~~\n                                                                                                      : ... Top module \'draw_background\'\nmodule draw_background(\n       ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:307: Operator ADD expects 17 bits on the RHS, but RHS\'s REPLICATE generates 14 bits.\n                                                                                                   : ... In instance draw_background\n wire [16:0] background_mem_address = ({ background_cout[16:9], 8\'d0} + { background_cout[16:9], 6\'d0} + { background_cout[8:0]});\n                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:307: Operator ADD expects 17 bits on the RHS, but RHS\'s REPLICATE generates 9 bits.\n                                                                                                   : ... In instance draw_background\n wire [16:0] background_mem_address = ({ background_cout[16:9], 8\'d0} + { background_cout[16:9], 6\'d0} + { background_cout[8:0]});\n                                                                                                       ^\n%Error: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:311: Cannot find file containing module: \'background\'\n background b0(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/186443491/view,data/full_repos/permissive/186443491/background\n             data/full_repos/permissive/186443491/view,data/full_repos/permissive/186443491/background.v\n             data/full_repos/permissive/186443491/view,data/full_repos/permissive/186443491/background.sv\n             background\n             background.v\n             background.sv\n             obj_dir/background\n             obj_dir/background.v\n             obj_dir/background.sv\n%Warning-WIDTH: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:338: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                   : ... In instance draw_background\n    Y_out_background <= background_cout[16:9];\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:346: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n                                                                                                   : ... In instance draw_background\n  if(resetn == 0 |!resetn_gold_stone_diamond) background_cout <= 17\'b0;\n                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:195: Operator ADD expects 8 bits on the RHS, but RHS\'s REPLICATE generates 4 bits.\n                                                                                                   : ... In instance draw_stone\n wire [7:0] stone_mem_address = ({stone_pixel_cout[7:4], 4\'d0} + {stone_pixel_cout[3:0]-1\'b1}+1\'b1);\n                                                               ^\n%Error: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:204: Cannot find file containing module: \'stone\'\n stone s0(\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:243: Operator ADD expects 9 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                   : ... In instance draw_stone\n    X_out_stone <= x + stone_pixel_cout[3:0];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:252: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                   : ... In instance draw_stone\n    Y_out_stone <= y + stone_pixel_cout[7:4];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:60: Operator ADD expects 8 bits on the RHS, but RHS\'s REPLICATE generates 4 bits.\n                                                                                                  : ... In instance draw_gold\n wire [7:0] gold_mem_address = ({gold_pixel_cout[7:4], 4\'d0} + {gold_pixel_cout[3:0]+1\'b1});\n                                                             ^\n%Error: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:69: Cannot find file containing module: \'gold\'\n gold g0(\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:106: Operator ADD expects 9 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                   : ... In instance draw_gold\n    X_out_gold <= x + gold_pixel_cout[3:0];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/186443491/view/draw_gold_stone_background_datapath.v:115: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                                   : ... In instance draw_gold\n    Y_out_gold <= y + gold_pixel_cout[7:4];\n                    ^\n%Error: Exiting due to 3 error(s), 11 warning(s)\n'
module draw_gold(
		clk, 
		resetn,
		x_init,
		y_init,
		

		resetn_c_gold, 
		enable_c_gold, 
		load_x_gold,
		load_y_gold,

		enable_x_adder_gold, 
		enable_y_adder_gold,
		enable_gold_count,

		resetn_gold_stone,

		
		X_out_gold, 
		Y_out_gold, 
		Color_out_gold,


		gold_count,
		gold_pixel_cout

	
	);
	
	input clk, resetn;
	input [8:0]x_init;
	input [7:0]y_init;
	
	
	input resetn_c_gold, 
			enable_c_gold, 
			load_x_gold,
			load_y_gold,

			enable_x_adder_gold, 
			enable_y_adder_gold;
	
	input enable_gold_count;
	input resetn_gold_stone;
			
	output reg [8:0]X_out_gold;
	output reg [7:0]Y_out_gold;
	output reg [11:0]Color_out_gold;
	
	
	output reg [7:0]gold_count;
	output reg [8:0]gold_pixel_cout;
	
	
	wire [7:0] gold_mem_address = ({gold_pixel_cout[7:4], 4'd0} + {gold_pixel_cout[3:0]+1'b1});
	

	reg [8:0] x;
	reg [7:0] y;
	
	wire [11:0] gold_color;
	

	gold g0(
	.address(gold_mem_address),
	.clock(clk),
	.q(gold_color));
	

	always@(posedge clk)begin
		if(!resetn)	Color_out_gold = 12'b0;
		else Color_out_gold <= gold_color;
	end
	
	

	always@(posedge clk)begin
		if(resetn == 0) x <= 9'b0;
		else
			if(load_x_gold) begin
			x[8:0] <= x_init;
			end
	end
	

	always@(posedge clk)begin
		if(resetn == 0) y <= 8'b0;
		else
			if(load_y_gold) begin
			y[7:0] <= y_init;
			
			end
	end
	


	always@(posedge clk)begin
		if(resetn == 0) X_out_gold <= 9'b0;
		else
			if(enable_x_adder_gold) begin
				X_out_gold <= x + gold_pixel_cout[3:0];
				end
	end
	

	always@(posedge clk)begin
		if(resetn == 0) Y_out_gold <= 8'b0;
		else
			if(enable_y_adder_gold)begin
				Y_out_gold <= y + gold_pixel_cout[7:4];
				end
	end
	

	

	always@(posedge clk)begin
		if((resetn == 0) | (resetn_c_gold == 0)) gold_pixel_cout <= 9'b0;
		else
			if(enable_c_gold)
			gold_pixel_cout <= gold_pixel_cout + 1'b1;
	end
	

	always@(posedge clk)begin
		if(!resetn | (!resetn_gold_stone)) gold_count <= 8'b0;
		else if(enable_gold_count)
			gold_count <= gold_count + 1'b1;
	end
	
endmodule
module draw_gold(
		clk, 
		resetn,
		x_init,
		y_init,
		

		resetn_c_gold, 
		enable_c_gold, 
		load_x_gold,
		load_y_gold,

		enable_x_adder_gold, 
		enable_y_adder_gold,
		enable_gold_count,

		resetn_gold_stone,

		
		X_out_gold, 
		Y_out_gold, 
		Color_out_gold,


		gold_count,
		gold_pixel_cout

	
	);

	
	input clk, resetn;
	input [8:0]x_init;
	input [7:0]y_init;
	
	
	input resetn_c_gold, 
			enable_c_gold, 
			load_x_gold,
			load_y_gold,

			enable_x_adder_gold, 
			enable_y_adder_gold;
	
	input enable_gold_count;
	input resetn_gold_stone;
			
	output reg [8:0]X_out_gold;
	output reg [7:0]Y_out_gold;
	output reg [11:0]Color_out_gold;
	
	
	output reg [7:0]gold_count;
	output reg [8:0]gold_pixel_cout;
	
	
	wire [7:0] gold_mem_address = ({gold_pixel_cout[7:4], 4'd0} + {gold_pixel_cout[3:0]+1'b1});
	

	reg [8:0] x;
	reg [7:0] y;
	
	wire [11:0] gold_color;
	

	gold g0(
	.address(gold_mem_address),
	.clock(clk),
	.q(gold_color));
	

	always@(posedge clk)begin
		if(!resetn)	Color_out_gold = 12'b0;
		else Color_out_gold <= gold_color;
	end
	
	

	always@(posedge clk)begin
		if(resetn == 0) x <= 9'b0;
		else
			if(load_x_gold) begin
			x[8:0] <= x_init;
			end
	end
	

	always@(posedge clk)begin
		if(resetn == 0) y <= 8'b0;
		else
			if(load_y_gold) begin
			y[7:0] <= y_init;
			
			end
	end
	


	always@(posedge clk)begin
		if(resetn == 0) X_out_gold <= 9'b0;
		else
			if(enable_x_adder_gold) begin
				X_out_gold <= x + gold_pixel_cout[3:0];
				end
	end
	

	always@(posedge clk)begin
		if(resetn == 0) Y_out_gold <= 8'b0;
		else
			if(enable_y_adder_gold)begin
				Y_out_gold <= y + gold_pixel_cout[7:4];
				end
	end
	

	

	always@(posedge clk)begin
		if((resetn == 0) | (resetn_c_gold == 0)) gold_pixel_cout <= 9'b0;
		else
			if(enable_c_gold)
			gold_pixel_cout <= gold_pixel_cout + 1'b1;
	end
	

	always@(posedge clk)begin
		if(!resetn | (!resetn_gold_stone)) gold_count <= 8'b0;
		else if(enable_gold_count)
			gold_count <= gold_count + 1'b1;
	end
	
endmodule