data/full_repos/permissive/200314387/verilog/74139/hct74139.v
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data/verilator_xmls/ecf5967d-4f3a-4aef-9e2a-36ddb0b1b012.xml
module hct74139(
input _Ea, 
input _Eb, 
input [1:0] Aa,
input [1:0] Ab,
output logic [3:0] _Ya,
output logic [3:0] _Yb
); 

    parameter LOG = 0;

    parameter AY_PD = 13;
    parameter EY_PD = 13;

    function [3:0] f74139(input [1:0] A, input _E); 

        logic [3:0] f74139;


        if (_E == 0) begin 
            case (A) 

                0: f74139 = 4'b1110;
                1: f74139 = 4'b1101;
                2: f74139 = 4'b1011; 
                3: f74139 = 4'b0111; 
            endcase
        end 
        else
        if (_E == 1) begin 
            f74139 = 4'b1111;
        end

    endfunction


    logic _Ea_d;
    logic _Eb_d;
    logic [1:0] Aa_d;
    logic [1:0] Ab_d;

    always @*
         Aa_d = #(AY_PD) Aa;
    always @*
         Ab_d = #(AY_PD) Ab;
    always @*
         _Ea_d = #(EY_PD) _Ea;
    always @*
         _Eb_d = #(EY_PD) _Eb;

    always @*
         _Ya = f74139(Aa_d,_Ea_d);

    always @*
        _Yb = f74139(Ab_d,_Eb_d);

   if (LOG) always @*
        $display("%9t ", $time, " DEMUX   _Ea=%1b", _Ea, " Aa=%2b", Aa, " _Ya=%4b", _Ya, "  /  _Eb=%1b", _Eb, " Ab=%2b", Ab, " _Yb=%4b", _Yb);

endmodule
module hct74139(
input _Ea, 
input _Eb, 
input [1:0] Aa,
input [1:0] Ab,
output logic [3:0] _Ya,
output logic [3:0] _Yb
);
 

    parameter LOG = 0;

    parameter AY_PD = 13;
    parameter EY_PD = 13;

    function [3:0] f74139(input [1:0] A, input _E); 

        logic [3:0] f74139;


        if (_E == 0) begin 
            case (A) 

                0: f74139 = 4'b1110;
                1: f74139 = 4'b1101;
                2: f74139 = 4'b1011; 
                3: f74139 = 4'b0111; 
            endcase
        end 
        else
        if (_E == 1) begin 
            f74139 = 4'b1111;
        end

    endfunction


    logic _Ea_d;
    logic _Eb_d;
    logic [1:0] Aa_d;
    logic [1:0] Ab_d;

    always @*
         Aa_d = #(AY_PD) Aa;
    always @*
         Ab_d = #(AY_PD) Ab;
    always @*
         _Ea_d = #(EY_PD) _Ea;
    always @*
         _Eb_d = #(EY_PD) _Eb;

    always @*
         _Ya = f74139(Aa_d,_Ea_d);

    always @*
        _Yb = f74139(Ab_d,_Eb_d);

   if (LOG) always @*
        $display("%9t ", $time, " DEMUX   _Ea=%1b", _Ea, " Aa=%2b", Aa, " _Ya=%4b", _Ya, "  /  _Eb=%1b", _Eb, " Ab=%2b", Ab, " _Yb=%4b", _Yb);

endmodule