data/full_repos/permissive/170402453/RISC/ALu_tb.v
 line:39: before: "."
1: b'%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/ALu_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/ALu_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Error: data/full_repos/permissive/170402453/RISC/ALu_tb.v:40: Cannot find file containing module: \'ALU\'\n ALU uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/ALU\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/ALU.v\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALu_tb.v:63: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                     : ... In instance ALU_tb\n   A = j;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALu_tb.v:65: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'k\' generates 32 bits.\n                                                                     : ... In instance ALU_tb\n    B = k;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALu_tb.v:67: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                     : ... In instance ALU_tb\n     {Sel,Cin} = i;\n               ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_tb;


	reg Cin;
	reg [2:0] Sel;
	reg [3:0] A;
	reg [3:0] B;
	integer i,j,k;


	wire [3:0] Out;
	wire Cout, statV;


	defparam uut.BITS=4;
	ALU uut (
		.Cin(Cin), 
		.Sel(Sel), 
		.A(A), 
		.B(B), 
		.Out(Out), 
		.Cout(Cout),
		.statV(statV)
	);

	initial begin

		Cin = 0;
		Sel = 0;
		A = 0;
		B = 0;


		#100;
		
		

		for(j=0;j<16;j=j+1) begin
			A = j;
			for(k=0;k<16;k=k+1) begin
				B = k;
				for(i=0;i<16;i=i+1) begin
					{Sel,Cin} = i;
					#1;
				end
			end
		end
	end
      
endmodule
module ALU_tb;



	reg Cin;
	reg [2:0] Sel;
	reg [3:0] A;
	reg [3:0] B;
	integer i,j,k;


	wire [3:0] Out;
	wire Cout, statV;


	defparam uut.BITS=4;
	ALU uut (
		.Cin(Cin), 
		.Sel(Sel), 
		.A(A), 
		.B(B), 
		.Out(Out), 
		.Cout(Cout),
		.statV(statV)
	);

	initial begin

		Cin = 0;
		Sel = 0;
		A = 0;
		B = 0;


		#100;
		
		

		for(j=0;j<16;j=j+1) begin
			A = j;
			for(k=0;k<16;k=k+1) begin
				B = k;
				for(i=0;i<16;i=i+1) begin
					{Sel,Cin} = i;
					#1;
				end
			end
		end
	end
      
endmodule