data/full_repos/permissive/110151336/lab_05/src/16_prefix_adder/common/prefix_adder.v
 line:43: before: "THER"
1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/16_prefix_adder/common/prefix_adder.v:17: Cannot find file containing module: 'prefix_carry_generator'\n    prefix_carry_generator\n    ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/lab_05/src/16_prefix_adder/common,data/full_repos/permissive/110151336/prefix_carry_generator\n             data/full_repos/permissive/110151336/lab_05/src/16_prefix_adder/common,data/full_repos/permissive/110151336/prefix_carry_generator.v\n             data/full_repos/permissive/110151336/lab_05/src/16_prefix_adder/common,data/full_repos/permissive/110151336/prefix_carry_generator.sv\n             prefix_carry_generator\n             prefix_carry_generator.v\n             prefix_carry_generator.sv\n             obj_dir/prefix_carry_generator\n             obj_dir/prefix_carry_generator.v\n             obj_dir/prefix_carry_generator.sv\n%Error: Exiting due to 1 error(s)\n"
module prefix_adder
# (
    parameter LEVELS = 3,
    parameter WIDTH = 2 ** LEVELS
)
(
    input                      carry_in,
    input    [ WIDTH - 1 : 0 ] x,
    input    [ WIDTH - 1 : 0 ] y,
    output   [ WIDTH - 1 : 0 ] z,
    output                     carry_out
);
    wire [ WIDTH - 1 : 0 ] carry;
    
    wire [ WIDTH - 1 : 0 ] generate_wire, propagate_wire; 
    
    prefix_carry_generator
    # ( .LEVELS(LEVELS), .WIDTH(WIDTH) )
    i_PCG
    (
        .carry_in    ( carry_in       ),
        .generate_in ( generate_wire  ),
        .propagate_in( propagate_wire ),
        .carry       ( carry          ),
        .carry_out   ( carry_out      )
    );
    
    generate
        
        genvar i;
        
        for (i = 0; i <= WIDTH - 1; i = i + 1)
        begin : stage

            assign generate_wire [ i ] = x[ i ] & y[ i ];
            assign propagate_wire[ i ] = x[ i ] ^ y[ i ];

            assign z[ i ] = carry[ i ] ^ propagate_wire[ i ];
        end
    endgenerate
    
endmodule
module prefix_adder
# (
    parameter LEVELS = 3,
    parameter WIDTH = 2 ** LEVELS
)
(
    input                      carry_in,
    input    [ WIDTH - 1 : 0 ] x,
    input    [ WIDTH - 1 : 0 ] y,
    output   [ WIDTH - 1 : 0 ] z,
    output                     carry_out
);

    wire [ WIDTH - 1 : 0 ] carry;
    
    wire [ WIDTH - 1 : 0 ] generate_wire, propagate_wire; 
    
    prefix_carry_generator
    # ( .LEVELS(LEVELS), .WIDTH(WIDTH) )
    i_PCG
    (
        .carry_in    ( carry_in       ),
        .generate_in ( generate_wire  ),
        .propagate_in( propagate_wire ),
        .carry       ( carry          ),
        .carry_out   ( carry_out      )
    );
    
    generate
        
        genvar i;
        
        for (i = 0; i <= WIDTH - 1; i = i + 1)
        begin : stage

            assign generate_wire [ i ] = x[ i ] & y[ i ];
            assign propagate_wire[ i ] = x[ i ] ^ y[ i ];

            assign z[ i ] = carry[ i ] ^ propagate_wire[ i ];
        end
    endgenerate
    
endmodule