data/full_repos/permissive/181665138/verilog/capitolo_ii/NOT.v
data/verilator_xmls/fdb308b4-12b1-42ce-a205-a9e7eaf232ca.xml
module NOT(x, z);
    input x;
    output z;

    assign z = (x == 0)?1:0;
    


endmodule
module NOT(x, z);

    input x;
    output z;

    assign z = (x == 0)?1:0;
    


endmodule