data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:90: Signal definition not found, creating implicitly: \'ALUSrc1\'\n  .Operand1( (ALUSrc1) ? PC : RF_RD1),     \n              ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:91: Signal definition not found, creating implicitly: \'ALUSrc2\'\n                                                                                                : ... Suggested alternative: \'ALUSrc1\'\n  .Operand2( (ALUSrc2) ? offset : RF_RD2 ), \n              ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:93: Signal definition not found, creating implicitly: \'Zero\'\n  .Zero(Zero),     \n        ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:102: Signal definition not found, creating implicitly: \'Branch\'\n assign Branch_Taken = Branch & Zero;\n                       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:103: Signal definition not found, creating implicitly: \'Jump\'\n assign NXT_PC = (~RSTn)? 0 : (Jump)? ( (JALorJALR)? JALR_Address : JAL_Address ) : ((Branch_Taken)? Branch_Target : PC+4 );\n                               ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:103: Signal definition not found, creating implicitly: \'JALorJALR\'\n assign NXT_PC = (~RSTn)? 0 : (Jump)? ( (JALorJALR)? JALR_Address : JAL_Address ) : ((Branch_Taken)? Branch_Target : PC+4 );\n                                         ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:119: Signal definition not found, creating implicitly: \'MemWrite\'\n assign D_MEM_WEN = ~MemWrite;\n                     ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:123: Signal definition not found, creating implicitly: \'RegWrite\'\n                                                                                                 : ... Suggested alternative: \'MemWrite\'\n assign RF_WE = RegWrite;\n                ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:126: Signal definition not found, creating implicitly: \'RegDst\'\n assign RF_WA1 = (RegDst) ? I_MEM_DI[11:7] : I_MEM_DI[24:20];\n                  ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:127: Signal definition not found, creating implicitly: \'MemtoReg\'\n assign RF_WD = (Jump) ? PC+4 : (MemtoReg) ? D_MEM_DI : ALU_Result;\n                                 ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:266: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (Operand1 == Operand2); \n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:270: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s NEQ generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (Operand1 != Operand2); \n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:277: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (signed_Operand1 < signed_Operand2);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:284: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s GTES generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (signed_Operand1 >= signed_Operand2);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:288: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (Operand1 < Operand2);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:292: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s GTE generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (Operand1 >= Operand2);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:299: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (signed_Operand1 < signed_Operand2);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:303: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (Operand1 < Operand2);\n               ^\n%Error: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:46: Cannot find file containing module: \'Control\'\n Control control(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab,data/full_repos/permissive/149079484/Control\n             data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab,data/full_repos/permissive/149079484/Control.v\n             data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab,data/full_repos/permissive/149079484/Control.sv\n             Control\n             Control.v\n             Control.sv\n             obj_dir/Control\n             obj_dir/Control.v\n             obj_dir/Control.sv\n%Error: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:65: Cannot find file containing module: \'ALUControl\'\n ALUControl alucontrol(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:133: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Branch_Taken\' generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP\n assign OUTPUT_PORT = (Branch) ? Branch_Taken : (MemWrite)? ALU_Result : RF_WD;\n                               ^\n%Error: Exiting due to 2 error(s), 19 warning(s)\n'
module RISCV_TOP (

	input wire CLK,
	input wire RSTn,


	output wire I_MEM_CSN,
	input wire [31:0] I_MEM_DI,
	output reg [11:0] I_MEM_ADDR,


	output wire D_MEM_CSN,
	input wire [31:0] D_MEM_DI,
	output wire [31:0] D_MEM_DOUT,
	output wire [11:0] D_MEM_ADDR,
	output wire D_MEM_WEN,
	output wire [3:0] D_MEM_BE,


	output wire RF_WE,
	output wire [4:0] RF_RA1,
	output wire [4:0] RF_RA2,
	output wire [4:0] RF_WA1,
	input wire [31:0] RF_RD1,
	input wire [31:0] RF_RD2,
	output wire [31:0] RF_WD,
	output wire HALT,
	output reg [31:0] NUM_INST,
	output wire [31:0] OUTPUT_PORT
	);


	initial begin
		NUM_INST <= 0;
	end


	always @ (negedge CLK) begin
		if (RSTn) NUM_INST <= NUM_INST + 1;
	end


	wire [6:0] ALUOp;
	wire [2:0] Concat_control;
	wire [3:0] BE;
	Control control(
		.opcode(I_MEM_DI[6:0]),
		.funct3(I_MEM_DI[14:12]),
   		.RegDst(RegDst),
   		.Jump(Jump),
		.Branch(Branch),
   		.MemRead(MemRead),
   		.MemtoReg(MemtoReg),
   		.ALUOp(ALUOp),
   		.MemWrite(MemWrite),
   		.ALUSrc1(ALUSrc1),
		.ALUSrc2(ALUSrc2),
   		.RegWrite(RegWrite),
		.JALorJALR(JALorJALR),
		.BE(BE),
		.Concat_control(Concat_control)
   		);

	wire [4:0] ALU_operation;
	ALUControl alucontrol(
		.ALUOp(ALUOp),
 		.funct3(I_MEM_DI[14:12]),
		.funct7(I_MEM_DI[31:25]),
		.ALU_operation(ALU_operation)
   		);
	
	wire [31:0] offset;
	Immediate_Concatenator Im_con(
		.Instr(I_MEM_DI),
		.Concat_control(Concat_control), 
		.offset(offset)
		);


	wire [31:0] JAL_Address;
	wire [31:0] JALR_Address;
	wire [31:0] Branch_Target;
	reg [31:0] PC;
	wire [31:0] NXT_PC;
	wire Branch_Taken;
	

	wire [31:0] ALU_Result;
	ALU alu(
		.Operand1( (ALUSrc1) ? PC : RF_RD1),
		.Operand2( (ALUSrc2) ? offset : RF_RD2 ), 
		.ALU_operation(ALU_operation), 
		.Zero(Zero),
		.ALU_Result(ALU_Result)  
		);



	assign JAL_Address = ALU_Result;
	assign JALR_Address = ALU_Result & (32'hfffffffe);
	assign Branch_Target = offset + PC;
	assign Branch_Taken = Branch & Zero;
	assign NXT_PC = (~RSTn)? 0 : (Jump)? ( (JALorJALR)? JALR_Address : JAL_Address ) : ((Branch_Taken)? Branch_Target : PC+4 );
	always @(posedge CLK) begin
		PC <= NXT_PC;
		I_MEM_ADDR <= NXT_PC[11:0];
	end
	assign I_MEM_CSN = (~RSTn)? 1'b1 : 1'b0;





	wire [31:0] temp_ALU_Result = ALU_Result;

	assign D_MEM_CSN = (~RSTn)? 1'b1 : 1'b0;
	assign D_MEM_DOUT = RF_RD2;
	assign D_MEM_ADDR = temp_ALU_Result[13:2]; 
	assign D_MEM_WEN = ~MemWrite;
	assign D_MEM_BE = BE;


	assign RF_WE = RegWrite;
	assign RF_RA1 = I_MEM_DI[19:15];
	assign RF_RA2 = I_MEM_DI[24:20];
	assign RF_WA1 = (RegDst) ? I_MEM_DI[11:7] : I_MEM_DI[24:20];
	assign RF_WD = (Jump) ? PC+4 : (MemtoReg) ? D_MEM_DI : ALU_Result;



	assign HALT = (RF_RD1 == 32'h0000000c) && (I_MEM_DI == 32'h00008067);	
	
	assign OUTPUT_PORT = (Branch) ? Branch_Taken : (MemWrite)? ALU_Result : RF_WD;

endmodule
module RISCV_TOP (

	input wire CLK,
	input wire RSTn,


	output wire I_MEM_CSN,
	input wire [31:0] I_MEM_DI,
	output reg [11:0] I_MEM_ADDR,


	output wire D_MEM_CSN,
	input wire [31:0] D_MEM_DI,
	output wire [31:0] D_MEM_DOUT,
	output wire [11:0] D_MEM_ADDR,
	output wire D_MEM_WEN,
	output wire [3:0] D_MEM_BE,


	output wire RF_WE,
	output wire [4:0] RF_RA1,
	output wire [4:0] RF_RA2,
	output wire [4:0] RF_WA1,
	input wire [31:0] RF_RD1,
	input wire [31:0] RF_RD2,
	output wire [31:0] RF_WD,
	output wire HALT,
	output reg [31:0] NUM_INST,
	output wire [31:0] OUTPUT_PORT
	);



	initial begin
		NUM_INST <= 0;
	end


	always @ (negedge CLK) begin
		if (RSTn) NUM_INST <= NUM_INST + 1;
	end


	wire [6:0] ALUOp;
	wire [2:0] Concat_control;
	wire [3:0] BE;
	Control control(
		.opcode(I_MEM_DI[6:0]),
		.funct3(I_MEM_DI[14:12]),
   		.RegDst(RegDst),
   		.Jump(Jump),
		.Branch(Branch),
   		.MemRead(MemRead),
   		.MemtoReg(MemtoReg),
   		.ALUOp(ALUOp),
   		.MemWrite(MemWrite),
   		.ALUSrc1(ALUSrc1),
		.ALUSrc2(ALUSrc2),
   		.RegWrite(RegWrite),
		.JALorJALR(JALorJALR),
		.BE(BE),
		.Concat_control(Concat_control)
   		);

	wire [4:0] ALU_operation;
	ALUControl alucontrol(
		.ALUOp(ALUOp),
 		.funct3(I_MEM_DI[14:12]),
		.funct7(I_MEM_DI[31:25]),
		.ALU_operation(ALU_operation)
   		);
	
	wire [31:0] offset;
	Immediate_Concatenator Im_con(
		.Instr(I_MEM_DI),
		.Concat_control(Concat_control), 
		.offset(offset)
		);


	wire [31:0] JAL_Address;
	wire [31:0] JALR_Address;
	wire [31:0] Branch_Target;
	reg [31:0] PC;
	wire [31:0] NXT_PC;
	wire Branch_Taken;
	

	wire [31:0] ALU_Result;
	ALU alu(
		.Operand1( (ALUSrc1) ? PC : RF_RD1),
		.Operand2( (ALUSrc2) ? offset : RF_RD2 ), 
		.ALU_operation(ALU_operation), 
		.Zero(Zero),
		.ALU_Result(ALU_Result)  
		);



	assign JAL_Address = ALU_Result;
	assign JALR_Address = ALU_Result & (32'hfffffffe);
	assign Branch_Target = offset + PC;
	assign Branch_Taken = Branch & Zero;
	assign NXT_PC = (~RSTn)? 0 : (Jump)? ( (JALorJALR)? JALR_Address : JAL_Address ) : ((Branch_Taken)? Branch_Target : PC+4 );
	always @(posedge CLK) begin
		PC <= NXT_PC;
		I_MEM_ADDR <= NXT_PC[11:0];
	end
	assign I_MEM_CSN = (~RSTn)? 1'b1 : 1'b0;





	wire [31:0] temp_ALU_Result = ALU_Result;

	assign D_MEM_CSN = (~RSTn)? 1'b1 : 1'b0;
	assign D_MEM_DOUT = RF_RD2;
	assign D_MEM_ADDR = temp_ALU_Result[13:2]; 
	assign D_MEM_WEN = ~MemWrite;
	assign D_MEM_BE = BE;


	assign RF_WE = RegWrite;
	assign RF_RA1 = I_MEM_DI[19:15];
	assign RF_RA2 = I_MEM_DI[24:20];
	assign RF_WA1 = (RegDst) ? I_MEM_DI[11:7] : I_MEM_DI[24:20];
	assign RF_WD = (Jump) ? PC+4 : (MemtoReg) ? D_MEM_DI : ALU_Result;



	assign HALT = (RF_RD1 == 32'h0000000c) && (I_MEM_DI == 32'h00008067);	
	
	assign OUTPUT_PORT = (Branch) ? Branch_Taken : (MemWrite)? ALU_Result : RF_WD;

endmodule