data/full_repos/permissive/167489907/Examples/Adder-Subtractor/addsub_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/Adder-Subtractor/addsub_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/Adder-Subtractor/addsub_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10; $stop;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/Adder-Subtractor/addsub_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n#5 clk = ~clk;\n^\n%Error: data/full_repos/permissive/167489907/Examples/Adder-Subtractor/addsub_tb.v:7: Cannot find file containing module: \'addsub\'\naddsub uut(.dataa(dataa), .datab(datab), .add_sub(add_sub), .clk(clk), .result(result));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167489907/Examples/Adder-Subtractor,data/full_repos/permissive/167489907/addsub\n             data/full_repos/permissive/167489907/Examples/Adder-Subtractor,data/full_repos/permissive/167489907/addsub.v\n             data/full_repos/permissive/167489907/Examples/Adder-Subtractor,data/full_repos/permissive/167489907/addsub.sv\n             addsub\n             addsub.v\n             addsub.sv\n             obj_dir/addsub\n             obj_dir/addsub.v\n             obj_dir/addsub.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module addsub_tb;

reg [7:0] dataa, datab;
reg add_sub, clk;
wire [8:0] result;

addsub uut(.dataa(dataa), .datab(datab), .add_sub(add_sub), .clk(clk), .result(result));

initial
begin
	clk = 0;
	add_sub = 1'b1;
	dataa = 8'b11000011;
	datab = 8'b00001101;
	#10;
	add_sub = 1'b0;
	#10; $stop;
end

always
#5 clk = ~clk;
endmodule
module addsub_tb;


reg [7:0] dataa, datab;
reg add_sub, clk;
wire [8:0] result;

addsub uut(.dataa(dataa), .datab(datab), .add_sub(add_sub), .clk(clk), .result(result));

initial
begin
	clk = 0;
	add_sub = 1'b1;
	dataa = 8'b11000011;
	datab = 8'b00001101;
	#10;
	add_sub = 1'b0;
	#10; $stop;
end

always
#5 clk = ~clk;
endmodule