data/full_repos/permissive/188434311/verilog/register_slice/forward_register_slice.v
data/verilator_xmls/b0c262ac-bf16-44ee-a476-08a3f8ce1ac7.xml
module forward_register_slice #(parameter BITWIDTH = 8)
(
input  wire                         clki,
input  wire                         rst_n,

input  wire                         RxVld,
input  wire  [ BITWIDTH - 1 : 0 ]   RxData,
output wire                         RxRdy,

output reg                          TxVld,
output reg   [ BITWIDTH - 1 : 0 ]   TxData,
input  wire                         TxRdy

);

wire TxData_en ;

assign TxData_en = RxVld & RxRdy ;
assign RxRdy = ( ~ TxVld | TxRdy );

always @( posedge clki or negedge rst_n )
  if( ! rst_n )
    TxVld <= #0.001 ( 1'b0 ) ;
  else  TxVld <= #0.001 ( ( RxVld | ~ TxRdy & TxVld ) ) ;

always @( posedge clki )
  if( TxData_en )
    TxData <= #0.001 ( RxData ) ;
  
endmodule
module forward_register_slice #(parameter BITWIDTH = 8)
(
input  wire                         clki,
input  wire                         rst_n,

input  wire                         RxVld,
input  wire  [ BITWIDTH - 1 : 0 ]   RxData,
output wire                         RxRdy,

output reg                          TxVld,
output reg   [ BITWIDTH - 1 : 0 ]   TxData,
input  wire                         TxRdy

);


wire TxData_en ;

assign TxData_en = RxVld & RxRdy ;
assign RxRdy = ( ~ TxVld | TxRdy );

always @( posedge clki or negedge rst_n )
  if( ! rst_n )
    TxVld <= #0.001 ( 1'b0 ) ;
  else  TxVld <= #0.001 ( ( RxVld | ~ TxRdy & TxVld ) ) ;

always @( posedge clki )
  if( TxData_en )
    TxData <= #0.001 ( RxData ) ;
  
endmodule