data/full_repos/permissive/210918583/rtl/arb.v
data/verilator_xmls/25f6ae0f-a9e6-4a2f-8db1-88cec6e10377.xml
module arb(

           input CLK7M,
           input CLKCPU,

           input AS20,
           input AS_INT,

           input BGACK,
           input BG20,

           output reg BG_INT,
           output reg BGACK_INT

       );

always @(posedge CLK7M) begin

    BGACK_INT <= BGACK;

end





always @(posedge CLKCPU or posedge BG20) begin

    if (BG20 == 1'b1) begin

        BG_INT <= 1'b1;

    end else begin

        if (AS20 == AS_INT) begin

            BG_INT <= BG20;

        end

    end

end

endmodule
module arb(

           input CLK7M,
           input CLKCPU,

           input AS20,
           input AS_INT,

           input BGACK,
           input BG20,

           output reg BG_INT,
           output reg BGACK_INT

       );


always @(posedge CLK7M) begin

    BGACK_INT <= BGACK;

end





always @(posedge CLKCPU or posedge BG20) begin

    if (BG20 == 1'b1) begin

        BG_INT <= 1'b1;

    end else begin

        if (AS20 == AS_INT) begin

            BG_INT <= BG20;

        end

    end

end

endmodule