data/full_repos/permissive/144334019/vga_dc_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n always begin clk = ~clk;    #50; end\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/vga_dc_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n always begin ptick = ~ptick;    #50; end\n                                 ^\n%Error: data/full_repos/permissive/144334019/vga_dc_tb.v:19: Cannot find file containing module: \'vga_data_controller\'\n vga_data_controller uut (\n ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/144334019,data/full_repos/permissive/144334019/vga_data_controller\n             data/full_repos/permissive/144334019,data/full_repos/permissive/144334019/vga_data_controller.v\n             data/full_repos/permissive/144334019,data/full_repos/permissive/144334019/vga_data_controller.sv\n             vga_data_controller\n             vga_data_controller.v\n             vga_data_controller.sv\n             obj_dir/vga_data_controller\n             obj_dir/vga_data_controller.v\n             obj_dir/vga_data_controller.sv\n%Warning-WIDTH: data/full_repos/permissive/144334019/vga_dc_tb.v:71: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh64\' generates 32 or 7 bits.\n                                                                   : ... In instance vga_dc_TB\n  x_div = 100; \n        ^\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vga_dc_TB;


	reg ptick;
	reg clk;
	reg rst;
	reg [7:0] pico_addr;
	reg [7:0] pico_data_in;
	reg [5:0] x_div;
	reg [5:0] y_div;


	wire [7:0] pico_data_out;
	wire [7:0] vga_out;


	vga_data_controller uut (
		.ptick(ptick), 
		.clk(clk), 
		.rst(rst), 
		.pico_addr(pico_addr), 
		.pico_data_in(pico_data_in), 
		.x_div(x_div), 
		.y_div(y_div), 
		.pico_data_out(pico_data_out), 
		.vga_out(vga_out)
	);

	initial begin

		ptick = 0;
		clk = 0;
		rst = 0;
		pico_addr = 0;
		pico_data_in = 0;
		x_div = 0;
		y_div = 0;


		#100;
      rst = 1; 

		#50
		rst = 0;
		x_div = 20; 
		y_div = 15;
		#50
		x_div = 18; 
		y_div = 16;
		#50
		x_div = 19; 
		y_div = 15;
		#50
		x_div = 20; 
		y_div = 19;
		#50
		x_div = 21; 
		y_div = 15;
		#50
		x_div = 22; 
		y_div = 15;
		#50
		x_div = 23; 
		y_div = 21;
		#50
		x_div = 24; 
		y_div = 15;
		#50
		x_div = 100; 
		y_div = 17;
		#50
		x_div = 0; 
		y_div = 0;
		
		
	end
   
	always begin clk = ~clk; 	  #50; end
	always begin ptick = ~ptick; 	  #50; end

	
	
endmodule
module vga_dc_TB;



	reg ptick;
	reg clk;
	reg rst;
	reg [7:0] pico_addr;
	reg [7:0] pico_data_in;
	reg [5:0] x_div;
	reg [5:0] y_div;


	wire [7:0] pico_data_out;
	wire [7:0] vga_out;


	vga_data_controller uut (
		.ptick(ptick), 
		.clk(clk), 
		.rst(rst), 
		.pico_addr(pico_addr), 
		.pico_data_in(pico_data_in), 
		.x_div(x_div), 
		.y_div(y_div), 
		.pico_data_out(pico_data_out), 
		.vga_out(vga_out)
	);

	initial begin

		ptick = 0;
		clk = 0;
		rst = 0;
		pico_addr = 0;
		pico_data_in = 0;
		x_div = 0;
		y_div = 0;


		#100;
      rst = 1; 

		#50
		rst = 0;
		x_div = 20; 
		y_div = 15;
		#50
		x_div = 18; 
		y_div = 16;
		#50
		x_div = 19; 
		y_div = 15;
		#50
		x_div = 20; 
		y_div = 19;
		#50
		x_div = 21; 
		y_div = 15;
		#50
		x_div = 22; 
		y_div = 15;
		#50
		x_div = 23; 
		y_div = 21;
		#50
		x_div = 24; 
		y_div = 15;
		#50
		x_div = 100; 
		y_div = 17;
		#50
		x_div = 0; 
		y_div = 0;
		
		
	end
   
	always begin clk = ~clk; 	  #50; end
	always begin ptick = ~ptick; 	  #50; end

	
	
endmodule