data/full_repos/permissive/158845296/memory_to_writeback.v
data/verilator_xmls/7c938260-956e-4628-b6cc-0dce01fdd810.xml
module memory_to_writeback
(
    input clock,
    input reset,


    input  [4:0] m_dst_reg,
    input        m_reg_write,
    input        m_mem_to_reg,
    input [31:0] m_alu_result,
    input [31:0] m_mem_data,
    input        m_stall,
    

    input             w_stall,
    output reg  [4:0] w_dst_reg,
    output reg        w_reg_write,
    output reg        w_mem_to_reg,
    output reg [31:0] w_alu_result,
    output reg [31:0] w_mem_data
);

    always @(posedge clock) begin
        w_dst_reg    <= (reset) ?  5'b0 : (w_stall ? w_dst_reg                      : m_dst_reg);
        w_reg_write  <= (reset) ?  1'b0 : (w_stall ? w_reg_write  : (m_stall ? 1'b0 : m_reg_write));
        w_mem_to_reg <= (reset) ?  1'b0 : (w_stall ? w_mem_to_reg                   : m_mem_to_reg);
        w_alu_result <= (reset) ? 32'b0 : (w_stall ? w_alu_result                   : m_alu_result);
        w_mem_data   <= (reset) ? 32'b0 : (w_stall ? w_mem_data                     : m_mem_data);
    end

endmodule
module memory_to_writeback
(
    input clock,
    input reset,


    input  [4:0] m_dst_reg,
    input        m_reg_write,
    input        m_mem_to_reg,
    input [31:0] m_alu_result,
    input [31:0] m_mem_data,
    input        m_stall,
    

    input             w_stall,
    output reg  [4:0] w_dst_reg,
    output reg        w_reg_write,
    output reg        w_mem_to_reg,
    output reg [31:0] w_alu_result,
    output reg [31:0] w_mem_data
);


    always @(posedge clock) begin
        w_dst_reg    <= (reset) ?  5'b0 : (w_stall ? w_dst_reg                      : m_dst_reg);
        w_reg_write  <= (reset) ?  1'b0 : (w_stall ? w_reg_write  : (m_stall ? 1'b0 : m_reg_write));
        w_mem_to_reg <= (reset) ?  1'b0 : (w_stall ? w_mem_to_reg                   : m_mem_to_reg);
        w_alu_result <= (reset) ? 32'b0 : (w_stall ? w_alu_result                   : m_alu_result);
        w_mem_data   <= (reset) ? 32'b0 : (w_stall ? w_mem_data                     : m_mem_data);
    end

endmodule