data/full_repos/permissive/203526788/iVerilog/Template/top.v
data/verilator_xmls/651345ed-d6ab-4609-89ee-8389f01b24c8.xml
module top (input wire a,
            input wire clk,
            output reg b);

    always @(posedge clk)
    begin
		b <= a;
    end

endmodule
module top (input wire a,
            input wire clk,
            output reg b);


    always @(posedge clk)
    begin
		b <= a;
    end

endmodule