data/full_repos/permissive/159555381/Lab_Exam/mul.v
 line:102: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:57: Unsupported: Ignoring delay on this delayed statement.\n   s3: #2 if(eqz) state <= s4;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:66: Unsupported: Ignoring delay on this delayed statement.\n   s0: begin #1 lda =0; ldb = 0; ldp = 0; clrp =0; decb =0; done = 0; end\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:67: Unsupported: Ignoring delay on this delayed statement.\n   s1: begin #1 lda =1;end\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:68: Unsupported: Ignoring delay on this delayed statement.\n   s2: begin #1 lda =0; ldb = 1; clrp = 1; end\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:69: Unsupported: Ignoring delay on this delayed statement.\n   s3: begin #1 ldb=0; ldp =1; clrp= 0; decb=1; end\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:70: Unsupported: Ignoring delay on this delayed statement.\n   s4: begin #1 done =1; ldb =0; ldp = 0; decb =0; end\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:71: Unsupported: Ignoring delay on this delayed statement.\n   default: begin #1 lda = 0; ldb = 0; ldp = 0; clrp = 0; decb = 0; end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #3 start = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #500 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:104: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #14 data_in = 17; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/Lab_Exam/mul.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #13 data_in = 5;\n  ^\n%Error: data/full_repos/permissive/159555381/Lab_Exam/mul.v:114: Unsupported or unknown PLI call: $monitor\n  $monitor ($time,"  x: %b  , y: %d   , z: %d Status: %b ",dp.x, dp.y, dp.z, done);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/159555381/Lab_Exam/mul.v:115: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("mul.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/159555381/Lab_Exam/mul.v:116: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,mul_test);\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mul_data(eqz, lda, ldb, ldp, clrp, decb, data_in, clk);
	input lda, ldb, ldp, clrp, decb, clk;
	input [15:0] data_in;
	output eqz;
	wire [15:0] x, y, z, bout, bus;
	assign bus = data_in;


	PIP01 A(x, bus, lda, clk);
	PIP02 P(y, z, ldp, clrp, clk);
	CNTR B(bout, bus, ldb, decb, clk);
	ADD AD(z, x, y);
	EQZ COMP(eqz, bout);
endmodule
module mul_data(eqz, lda, ldb, ldp, clrp, decb, data_in, clk);

	input lda, ldb, ldp, clrp, decb, clk;
	input [15:0] data_in;
	output eqz;
	wire [15:0] x, y, z, bout, bus;
	assign bus = data_in;


	PIP01 A(x, bus, lda, clk);
	PIP02 P(y, z, ldp, clrp, clk);
	CNTR B(bout, bus, ldb, decb, clk);
	ADD AD(z, x, y);
	EQZ COMP(eqz, bout);
endmodule