data/full_repos/permissive/108410192/src/LSFR.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/108410192/src/LSFR.v:29: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'LFSR\'\nmodule LFSR (output reg [0:7] q,\n       ^~~~\n                                                                     : ... Top module \'LFSR2\'\nmodule LFSR2 (output reg [1:8] q,\n       ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:29: Little bit endian vector: MSB < LSB of bit range: 1:8\nmodule LFSR2 (output reg [1:8] q,\n                         ^\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:31: Little bit endian vector: MSB < LSB of bit range: 1:8\n              input [1:8] din);\n                    ^\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:3: Little bit endian vector: MSB < LSB of bit range: 0:7\nmodule LFSR (output reg [0:7] q,\n                        ^\n%Warning-LITENDIAN: data/full_repos/permissive/108410192/src/LSFR.v:5: Little bit endian vector: MSB < LSB of bit range: 0:7\n             input [0:7] din);\n                   ^\n%Error: Exiting due to 5 warning(s)\n'
module LFSR2 (output reg [1:8] q,
              input clk, rst_n, load,
              input [1:8] din);
    
    always @(posedge clk) begin
        if (~rst_n) 
            q <= 8'b0;
        else begin
            if (load)
                q <= (|din) ? din : 8'b0000_0001;
            else begin
                if (q == 8'b0) q <= 8'b0000_0001;
                else begin
                    q[8] <= q[7];
                    q[7] <= q[6] ^ q[8];
                    q[6] <= q[5] ^ q[8];
                    {q[5], q[4], q[3]} <= {q[4], q[3], q[2]};
                    q[2] <= q[1] ^ q[8];
                    q[1] <= q[8];
                end
            end
        end
    end
    
endmodule
module LFSR2 (output reg [1:8] q,
              input clk, rst_n, load,
              input [1:8] din);

    
    always @(posedge clk) begin
        if (~rst_n) 
            q <= 8'b0;
        else begin
            if (load)
                q <= (|din) ? din : 8'b0000_0001;
            else begin
                if (q == 8'b0) q <= 8'b0000_0001;
                else begin
                    q[8] <= q[7];
                    q[7] <= q[6] ^ q[8];
                    q[6] <= q[5] ^ q[8];
                    {q[5], q[4], q[3]} <= {q[4], q[3], q[2]};
                    q[2] <= q[1] ^ q[8];
                    q[1] <= q[8];
                end
            end
        end
    end
    
endmodule