data/full_repos/permissive/146246005/Multiplexer/MUX2_1.v
data/verilator_xmls/b5bca2f2-0439-4b76-94bc-d48c1870a213.xml
module MUX2_1(OUT, A, B, SEL);

    input A, B, SEL;
    output OUT;


    wire A1, B1, SEL_N;


    not (SEL_N, SEL);
    and (A1, A, SEL_N);
    and (B1, B, SEL);
    or (OUT, A1, B1);
endmodule
module MUX2_1(OUT, A, B, SEL);


    input A, B, SEL;
    output OUT;


    wire A1, B1, SEL_N;


    not (SEL_N, SEL);
    and (A1, A, SEL_N);
    and (B1, B, SEL);
    or (OUT, A1, B1);
endmodule