data/full_repos/permissive/20726090/hw/vlog/ethmac/eth_spram_256x32.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/20726090/hw/vlog/ethmac/eth_spram_256x32.v:40: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20726090/hw/vlog/ethmac,data/full_repos/permissive/20726090/timescale.v\n             data/full_repos/permissive/20726090/hw/vlog/ethmac,data/full_repos/permissive/20726090/timescale.v.v\n             data/full_repos/permissive/20726090/hw/vlog/ethmac,data/full_repos/permissive/20726090/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/20726090/hw/vlog/ethmac/eth_spram_256x32.v:53: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n output [31:0]   do     \n                 ^~\n%Error: data/full_repos/permissive/20726090/hw/vlog/ethmac/eth_spram_256x32.v:81: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n    .o_read_data    ( do            )\n                      ^~\n%Error: Exiting due to 3 error(s)\n'
module eth_spram_256x32(



	input           clk,
	input           rst,
	input           ce,
	input  [3:0]    we,
	input           oe,
	input  [7:0]    addr,
	input  [31:0]   di,
	output [31:0]   do

);

wire write_enable;
assign write_enable = ce & (|we);

`ifdef XILINX_SPARTAN6_FPGA
    xs6_sram_256x32_byte_en 
`endif

`ifdef XILINX_VIRTEX6_FPGA
    xv6_sram_256x32_byte_en 
`endif

`ifndef XILINX_FPGA
    generic_sram_byte_en
`endif

    #(
    .DATA_WIDTH     ( 32            ) ,
    .ADDRESS_WIDTH  ( 8             )
) u_ram (
    .i_clk          ( clk           ),
    .i_write_data   ( di            ),
    .i_write_enable ( write_enable  ),
    .i_address      ( addr          ),
    .i_byte_enable  ( we            ),
    .o_read_data    ( do            )
);


endmodule
module eth_spram_256x32(



	input           clk,
	input           rst,
	input           ce,
	input  [3:0]    we,
	input           oe,
	input  [7:0]    addr,
	input  [31:0]   di,
	output [31:0]   do

);


wire write_enable;
assign write_enable = ce & (|we);

`ifdef XILINX_SPARTAN6_FPGA
    xs6_sram_256x32_byte_en 
`endif

`ifdef XILINX_VIRTEX6_FPGA
    xv6_sram_256x32_byte_en 
`endif

`ifndef XILINX_FPGA
    generic_sram_byte_en
`endif

    #(
    .DATA_WIDTH     ( 32            ) ,
    .ADDRESS_WIDTH  ( 8             )
) u_ram (
    .i_clk          ( clk           ),
    .i_write_data   ( di            ),
    .i_write_enable ( write_enable  ),
    .i_address      ( addr          ),
    .i_byte_enable  ( we            ),
    .o_read_data    ( do            )
);


endmodule