data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/sign_extension_testbench.v
 line:19: before: "$"
1: b'%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/sign_extension_testbench.v:12: Unsupported or unknown PLI call: $monitor\n    $monitor(in, ext);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/sign_extension_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/sign_extension_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sign_extension_testbench;

reg [15:0]in;
wire [31:0]ext;

sign_extension uut(.in(in), .ext(ext));

initial begin

    $monitor(in, ext);
    

    in=16'b1000_0000_0000_0000;
    #5
    in=16'b0100_0000_0000_0000;
    #5
    $finish;
    
end
endmodule
module sign_extension_testbench;


reg [15:0]in;
wire [31:0]ext;

sign_extension uut(.in(in), .ext(ext));

initial begin

    $monitor(in, ext);
    

    in=16'b1000_0000_0000_0000;
    #5
    in=16'b0100_0000_0000_0000;
    #5
    $finish;
    
end
endmodule