data/full_repos/permissive/173362503/cpu_top.v
1: b"%Error: data/full_repos/permissive/173362503/cpu_top.v:36: Cannot find file containing module: 'bram_dpstrobe'\nbram_dpstrobe RAM0\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173362503,data/full_repos/permissive/173362503/bram_dpstrobe\n             data/full_repos/permissive/173362503,data/full_repos/permissive/173362503/bram_dpstrobe.v\n             data/full_repos/permissive/173362503,data/full_repos/permissive/173362503/bram_dpstrobe.sv\n             bram_dpstrobe\n             bram_dpstrobe.v\n             bram_dpstrobe.sv\n             obj_dir/bram_dpstrobe\n             obj_dir/bram_dpstrobe.v\n             obj_dir/bram_dpstrobe.sv\n%Error: data/full_repos/permissive/173362503/cpu_top.v:45: Cannot find file containing module: 'core_top'\ncore_top CT0 \n^~~~~~~~\n%Error: data/full_repos/permissive/173362503/cpu_top.v:56: Cannot find file containing module: 'io_port'\nio_port IO0\n^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module cpu_top
(
	input wire clk,
	input wire resetb,
	inout wire [7:0] gpio0
);

wire [7:0] io_addr;
wire       io_en, io_we;
wire [31:0] io_data_read;
wire [31:0] io_data_write;
wire        irq_mtimecmp;


wire [31:2] ram_iaddr;
wire [31:0] ram_irdata;
wire [31:2] ram_addr;
wire [3:0] ram_wstrb;
wire [31:0] ram_rdata;
wire [31:0] ram_wdata;


wire [7:0] input0, output0, dir0;

generate
	genvar i;
	for (i=0; i<8; i=i+1) begin
		assign gpio0[i] = dir0[i] ? output0[i] : 1'bZ;
		assign input0[i] = gpio0[i];
	end
endgenerate

bram_dpstrobe RAM0
(
	.clk(clk), 
	.addra(ram_iaddr[15:2]), .addrb(ram_addr[15:2]),
	.dina(32'bX), .dinb(ram_wdata),
	.wea(4'b0), .web(ram_wstrb),
	.douta(ram_irdata), .doutb(ram_rdata)
);

core_top CT0 
(
	.clk(clk), .resetb(resetb),
	.ram_iaddr(ram_iaddr), .ram_irdata(ram_irdata), 
	.ram_addr(ram_addr), .ram_wstrb(ram_wstrb), 
	.ram_rdata(ram_rdata), .ram_wdata(ram_wdata),
	.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
	.io_data_read(io_data_read), .io_data_write(io_data_write),
	.irq_mtimecmp(irq_mtimecmp)
);

io_port IO0
(
	.clk(clk), .resetb(resetb),
	.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
	.io_data_read(io_data_read), .io_data_write(io_data_write),
	.irq_mtimecmp(irq_mtimecmp),
	.output0(output0), .input0(input0), .dir0(dir0)
);


endmodule
module cpu_top
(
	input wire clk,
	input wire resetb,
	inout wire [7:0] gpio0
);


wire [7:0] io_addr;
wire       io_en, io_we;
wire [31:0] io_data_read;
wire [31:0] io_data_write;
wire        irq_mtimecmp;


wire [31:2] ram_iaddr;
wire [31:0] ram_irdata;
wire [31:2] ram_addr;
wire [3:0] ram_wstrb;
wire [31:0] ram_rdata;
wire [31:0] ram_wdata;


wire [7:0] input0, output0, dir0;

generate
	genvar i;
	for (i=0; i<8; i=i+1) begin
		assign gpio0[i] = dir0[i] ? output0[i] : 1'bZ;
		assign input0[i] = gpio0[i];
	end
endgenerate

bram_dpstrobe RAM0
(
	.clk(clk), 
	.addra(ram_iaddr[15:2]), .addrb(ram_addr[15:2]),
	.dina(32'bX), .dinb(ram_wdata),
	.wea(4'b0), .web(ram_wstrb),
	.douta(ram_irdata), .doutb(ram_rdata)
);

core_top CT0 
(
	.clk(clk), .resetb(resetb),
	.ram_iaddr(ram_iaddr), .ram_irdata(ram_irdata), 
	.ram_addr(ram_addr), .ram_wstrb(ram_wstrb), 
	.ram_rdata(ram_rdata), .ram_wdata(ram_wdata),
	.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
	.io_data_read(io_data_read), .io_data_write(io_data_write),
	.irq_mtimecmp(irq_mtimecmp)
);

io_port IO0
(
	.clk(clk), .resetb(resetb),
	.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
	.io_data_read(io_data_read), .io_data_write(io_data_write),
	.irq_mtimecmp(irq_mtimecmp),
	.output0(output0), .input0(input0), .dir0(dir0)
);


endmodule