data/full_repos/permissive/159479522/Select_module.v
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data/verilator_xmls/70385dbe-7414-4a9e-b118-9f4a3eb69abd.xml
module Select_module(reset,power_led,start_pause,module_select,if_finish,model_now );
input wire reset,power_led,start_pause,module_select,if_finish;
output reg [2:0] model_now;
initial begin
model_now=0;
end
always @(posedge module_select or posedge if_finish) begin
   if(if_finish==1)begin
       model_now=0;
       end       
   else if(power_led && ~start_pause)
       begin
       model_now=model_now+1;
       if(model_now>=6)
       model_now=0;
       end
    end
endmodule
module Select_module(reset,power_led,start_pause,module_select,if_finish,model_now );

input wire reset,power_led,start_pause,module_select,if_finish;
output reg [2:0] model_now;
initial begin
model_now=0;
end
always @(posedge module_select or posedge if_finish) begin
   if(if_finish==1)begin
       model_now=0;
       end       
   else if(power_led && ~start_pause)
       begin
       model_now=model_now+1;
       if(model_now>=6)
       model_now=0;
       end
    end
endmodule