data/full_repos/permissive/150266237/parte2.v
1: b'%Error: data/full_repos/permissive/150266237/parte2.v:119: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile ("out.vcd"); \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte2.v:120: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars; \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte2.v:125: Unsupported or unknown PLI call: $monitor\n     $monitor($time," c %b res %b a %b s %d smem %d sporta %d",c,res,a,saida,saida1,saida2);\n     ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:126: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=0; a=0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:127: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:128: Unsupported: Ignoring delay on this delayed statement.\n      #8 a=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:129: Unsupported: Ignoring delay on this delayed statement.\n      #16 a=0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:130: Unsupported: Ignoring delay on this delayed statement.\n      #12 a=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:131: Unsupported: Ignoring delay on this delayed statement.\n      #4;\n      ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module statePorta(input clk, input res, input a, output [2:0] s);
wire [2:0] e;
wire [2:0] p;
assign s[0] = e[0] | e[2]&~e[1] ;
assign s[1] = e[2];
assign s[2] = ~e[1] & ~e[2];
assign p[0]  =  ~e[1]&~e[2]&a;
assign p[1]  =  e[0] | ~e[1]&~a;
assign p[2] =   e[0]| a&~e[2] | e[1]&~e[0]&~e[2] | ~a&e[1];



ff  e0(p[0],clk,res,e[0]);
ff  e1(p[1],clk,res,e[1]);
ff  e2(p[2],clk,res,e[2]);

endmodule
module statePorta(input clk, input res, input a, output [2:0] s);

wire [2:0] e;
wire [2:0] p;
assign s[0] = e[0] | e[2]&~e[1] ;
assign s[1] = e[2];
assign s[2] = ~e[1] & ~e[2];
assign p[0]  =  ~e[1]&~e[2]&a;
assign p[1]  =  e[0] | ~e[1]&~a;
assign p[2] =   e[0]| a&~e[2] | e[1]&~e[0]&~e[2] | ~a&e[1];



ff  e0(p[0],clk,res,e[0]);
ff  e1(p[1],clk,res,e[1]);
ff  e2(p[2],clk,res,e[2]);

endmodule