data/full_repos/permissive/167161024/ad9958_core.v
1: b'%Error: data/full_repos/permissive/167161024/ad9958_core.v:6: Cannot find include file: ad9958_registers.vh\n`include "ad9958_registers.vh" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167161024,data/full_repos/permissive/167161024/ad9958_registers.vh\n             data/full_repos/permissive/167161024,data/full_repos/permissive/167161024/ad9958_registers.vh.v\n             data/full_repos/permissive/167161024,data/full_repos/permissive/167161024/ad9958_registers.vh.sv\n             ad9958_registers.vh\n             ad9958_registers.vh.v\n             ad9958_registers.vh.sv\n             obj_dir/ad9958_registers.vh\n             obj_dir/ad9958_registers.vh.v\n             obj_dir/ad9958_registers.vh.sv\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:7: Cannot find include file: ad9958_vars.vh\n`include "ad9958_vars.vh" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:49: Define or directive not defined: \'`IOMODE_4_BIT\'\n  IO_MODE = `IOMODE_4_BIT;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  IO_MODE = `IOMODE_4_BIT;\n                         ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:117: Define or directive not defined: \'`ADDR_CSR\'\n     reg_address <= `ADDR_CSR;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:117: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     reg_address <= `ADDR_CSR;\n                             ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:141: Define or directive not defined: \'`INSTRUCTION_WRITE\'\n     data_input <= reg_address | `INSTRUCTION_WRITE;\n                                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:141: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     data_input <= reg_address | `INSTRUCTION_WRITE;\n                                                   ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:142: Define or directive not defined: \'`SIZE_INST\'\n     bits_to_send <= `SIZE_INST;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:142: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     bits_to_send <= `SIZE_INST;\n                               ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:151: Define or directive not defined: \'`ADDR_CSR\'\n    `ADDR_CSR : begin\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:151: syntax error, unexpected \':\', expecting endcase\n    `ADDR_CSR : begin\n              ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:154: Define or directive not defined: \'`ADDR_FR1\'\n    `ADDR_FR1 : begin\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:154: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ADDR_FR1 : begin\n                ^~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:157: Define or directive not defined: \'`ADDR_FR2\'\n    `ADDR_FR2 : begin\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:157: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ADDR_FR2 : begin\n                ^~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:160: Define or directive not defined: \'`ADDR_CFR\'\n    `ADDR_CFR : begin\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:160: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ADDR_CFR : begin\n                ^~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:163: Define or directive not defined: \'`ADDR_CFTW0\'\n    `ADDR_CFTW0 : begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:163: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ADDR_CFTW0 : begin\n                  ^~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:166: Define or directive not defined: \'`ADDR_ACR\'\n    `ADDR_ACR : begin\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:166: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    `ADDR_ACR : begin\n                ^~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:180: Define or directive not defined: \'`SIZE_CSR\'\n     bits_to_send <= `SIZE_CSR;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:180: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     bits_to_send <= `SIZE_CSR;\n                              ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:189: Define or directive not defined: \'`ADDR_CFTW0\'\n      reg_address <= `ADDR_CFTW0;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:189: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      reg_address <= `ADDR_CFTW0;\n                                ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:192: Define or directive not defined: \'`ADDR_ACR\'\n      reg_address <= `ADDR_ACR;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:192: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      reg_address <= `ADDR_ACR;\n                              ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:202: Define or directive not defined: \'`ADDR_CFTW0\'\n      reg_address <= `ADDR_CFTW0;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:202: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      reg_address <= `ADDR_CFTW0;\n                                ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:205: Define or directive not defined: \'`ADDR_ACR\'\n      reg_address <= `ADDR_ACR;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:205: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      reg_address <= `ADDR_ACR;\n                              ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:215: Define or directive not defined: \'`ADDR_FR1\'\n       reg_address <= `ADDR_FR1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:215: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       reg_address <= `ADDR_FR1;\n                               ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:220: Define or directive not defined: \'`ADDR_FR1\'\n       reg_address <= `ADDR_FR1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:220: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       reg_address <= `ADDR_FR1;\n                               ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:228: Define or directive not defined: \'`ADDR_CFR\'\n     reg_address <= `ADDR_CFR;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:228: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     reg_address <= `ADDR_CFR;\n                             ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:231: Define or directive not defined: \'`SIZE_FR1\'\n     bits_to_send <= `SIZE_FR1;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:231: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     bits_to_send <= `SIZE_FR1;\n                              ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:240: Define or directive not defined: \'`ADDR_CSR\'\n     reg_address <= `ADDR_CSR;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:240: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     reg_address <= `ADDR_CSR;\n                             ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:250: Define or directive not defined: \'`SIZE_CFR\'\n     bits_to_send <= `SIZE_CFR;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:250: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     bits_to_send <= `SIZE_CFR;\n                              ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:253: Define or directive not defined: \'`ADDR_CSR\'\n     reg_address <= `ADDR_CSR;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:253: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     reg_address <= `ADDR_CSR;\n                             ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:261: Define or directive not defined: \'`SIZE_CFTW0\'\n     bits_to_send <= `SIZE_CFTW0;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:261: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     bits_to_send <= `SIZE_CFTW0;\n                                ^\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:283: Define or directive not defined: \'`ADDR_CSR\'\n     reg_address <= `ADDR_CSR;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_core.v:283: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     reg_address <= `ADDR_CSR;\n                             ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ad9958_core(
				   input 			 clock,
				   input 			 reset_n,

				   input [32-1:0] 	 ftw_ch0,
				   input [32-1:0] 	 ftw_ch1,
				   input [10-1:0] 	 asf_ch0,
				   input [10-1:0] 	 asf_ch1,


				   input 			 vco_gain,
				   input [4:0] 		 clock_multiplier,

				   input [1:0] 		 dac_fscale_ch0,
				   input [1:0] 		 dac_fscale_ch1,

				   input 			 busy,

				   output reg 		 trigger,
				   output reg 		 four_bit,
				   output reg [5:0]  bits_to_send,
				   output reg [63:0] data_input,

				   output reg 		 master_reset,
				   output reg 		 io_update
				   );


   parameter
	 MSB_FIRST = 0,
	 LSB_FIRST = 1;

   parameter
	 ASF_EN = 13'b1000000000000;

   parameter
	 CH0_ENABLE = 8'b01000000,
	 CH1_ENABLE = 8'b10000000;

   parameter
	 IO_MODE = `IOMODE_4_BIT;

   


   parameter
	 STATE_MASTER_RESET = 0,
	 STATE_IO_UPDATE = 1,
	 STATE_INSTRUCTION_WRITE = 2,
	 STATE_CSR_CONFIG = 3,
	 STATE_FR1_CONFIG = 4,
	 STATE_FR2_CONFIG = 5,
	 STATE_CFR_CONFIG = 6,
	 STATE_FTW_CONFIG = 7,
	 STATE_ASF_CONFIG = 8,
	 STATE_WAIT = 9;
   
   parameter
	 NONE_SELECTED = 0,
	 CH0_SELECTED = 1,
	 CH1_SELECTED = 2,
	 BOTH_SELECTED = 3;

   parameter
	 TUNE_FREQ = 0,
	 TUNE_AMPL = 1;
   
   reg 								 init_done;
   reg [1:0] 						 channel_select;
   reg 								 io_mode_set;

   reg [3:0] 						 state;
   reg [3:0] 						 next_state;
   
   reg [7:0] 						 reg_address;

   reg [1:0] 						 tune_target;
   
   reg [32-1:0] 					 ftw_ch0_buf;
   reg [32-1:0] 					 ftw_ch1_buf;
   reg [32-1:0] 					 asf_ch0_buf;
   reg [32-1:0] 					 asf_ch1_buf;


   always @(posedge io_update) begin
	  ftw_ch0_buf <= ftw_ch0;
	  ftw_ch1_buf <= ftw_ch1;

	  asf_ch0_buf <= asf_ch0;
	  asf_ch1_buf <= asf_ch1;
   end

   always @(posedge clock) begin
	  if(~reset_n) begin
		 init_done <= 0;
		 master_reset <= 0;
		 state <= STATE_MASTER_RESET;
		 io_mode_set <= 0;
	  end else begin
		 case(state)
		   STATE_MASTER_RESET : begin
			  four_bit <= 0;
			  master_reset <= 0;
			  state <= STATE_INSTRUCTION_WRITE;
			  next_state <= STATE_CSR_CONFIG;
			  channel_select <= BOTH_SELECTED;
			  reg_address <= `ADDR_CSR;
			  tune_target <= TUNE_FREQ;

		   end

		   STATE_IO_UPDATE : begin
			  io_update <= 1;
			  state <= STATE_WAIT;
			  next_state <= STATE_INSTRUCTION_WRITE;
			  channel_select <= CH0_SELECTED;
			  

		   end

		   STATE_INSTRUCTION_WRITE : begin
			  state <= STATE_WAIT;
			  master_reset <= 0;

			  trigger <= 1;
			  data_input <= reg_address | `INSTRUCTION_WRITE;
			  bits_to_send <= `SIZE_INST;

			  if(io_mode_set) begin
				 four_bit <= 1;
			  end else begin
				 four_bit <= 0;
			  end
			  
			  case(reg_address)
				`ADDR_CSR : begin
				   next_state <= STATE_CSR_CONFIG;
				end
				`ADDR_FR1 : begin
				   next_state <= STATE_FR1_CONFIG;
				end
				`ADDR_FR2 : begin
				   next_state <= STATE_FR2_CONFIG;
				end
				`ADDR_CFR : begin
				   next_state <= STATE_CFR_CONFIG;
				end
				`ADDR_CFTW0 : begin
				   next_state <= STATE_FTW_CONFIG;
				end
				`ADDR_ACR : begin
				   next_state <= STATE_ASF_CONFIG;
				end
				default : begin
				   next_state <= STATE_INSTRUCTION_WRITE;
				end
			  endcase
			  
		   end

		   STATE_CSR_CONFIG : begin
			  state <= STATE_WAIT;
			  trigger <= 1;

			  bits_to_send <= `SIZE_CSR;
			  
			  case (channel_select)
				CH0_SELECTED : begin

					next_state <= STATE_INSTRUCTION_WRITE;
				   data_input <= CH0_ENABLE | MSB_FIRST | IO_MODE;
				   case(tune_target)
					 TUNE_FREQ : begin
						reg_address <= `ADDR_CFTW0;
					 end
					 TUNE_AMPL :begin
						reg_address <= `ADDR_ACR;
					 end
				   endcase
				end

				CH1_SELECTED : begin
					next_state <= STATE_INSTRUCTION_WRITE;
				   data_input <= CH1_ENABLE | MSB_FIRST | IO_MODE;
				   case(tune_target)
					 TUNE_FREQ : begin
						reg_address <= `ADDR_CFTW0;
					 end
					 TUNE_AMPL :begin
						reg_address <= `ADDR_ACR;
					 end
				   endcase
				end

				BOTH_SELECTED : begin

					next_state <= STATE_IO_UPDATE;
				   io_mode_set <= 1;
					data_input <= CH0_ENABLE | CH1_ENABLE | MSB_FIRST | IO_MODE;
				   reg_address <= `ADDR_FR1;
				end
				
				default : begin
				   data_input <= MSB_FIRST | IO_MODE;
				   reg_address <= `ADDR_FR1;
				end
			  endcase
		   end

		   STATE_FR1_CONFIG : begin
			  state <= STATE_WAIT;
			  next_state <= STATE_IO_UPDATE;
			  reg_address <= `ADDR_CFR;

			  trigger <= 1;
			  bits_to_send <= `SIZE_FR1;
			  data_input <= (vco_gain << 23) | (clock_multiplier << 18);
			  
		   end


		   STATE_FR2_CONFIG : begin
			  state <= STATE_WAIT;
			  next_state <= STATE_IO_UPDATE;
			  reg_address <= `ADDR_CSR;
		   end

		   STATE_CFR_CONFIG : begin
			  state <= STATE_WAIT;
			  next_state <= STATE_IO_UPDATE;
			  init_done <= 1;

			  trigger <= 1;

			  bits_to_send <= `SIZE_CFR;
			  data_input <= (dac_fscale_ch0 << 8);
			  
			  reg_address <= `ADDR_CSR;
		   end

		   STATE_FTW_CONFIG : begin
			  state <= STATE_WAIT;
			  next_state <= STATE_INSTRUCTION_WRITE;

			  trigger <= 1;
			  bits_to_send <= `SIZE_CFTW0;
			  
			  case(channel_select)
				CH0_SELECTED : begin
				   channel_select <= CH1_SELECTED;
				   data_input <= ftw_ch0_buf;
				   next_state <= STATE_INSTRUCTION_WRITE;
				   tune_target <= TUNE_FREQ;

				end
				CH1_SELECTED : begin
				   channel_select <= CH0_SELECTED;
				   data_input <= ftw_ch1_buf;
				   next_state <= STATE_IO_UPDATE;
				   tune_target <= TUNE_AMPL;

				end
				default : begin

				end
			  endcase

			  reg_address <= `ADDR_CSR;

		   end

		   STATE_ASF_CONFIG : begin
			  state <= STATE_WAIT;

			  trigger <= 1;
			  bits_to_send <= `SIZE_ACR;
			  
			  case (channel_select)
				CH0_SELECTED : begin
				   channel_select <= CH1_SELECTED;

				   next_state <= STATE_INSTRUCTION_WRITE;
				   data_input <= ASF_EN | asf_ch0_buf;
				   tune_target <= TUNE_AMPL;

				end

				CH1_SELECTED : begin
				   channel_select <= CH0_SELECTED;

				   next_state <= STATE_IO_UPDATE;
				   data_input <= ASF_EN | asf_ch1_buf;
				   tune_target <= TUNE_FREQ;
				end
				default : begin
				   channel_select <= CH0_SELECTED;
				end
			  endcase
			  
			  reg_address <= `ADDR_CSR;
		   end

		   STATE_WAIT : begin
			  master_reset <= 0;
			  io_update <= 0;
			  trigger <= 0;

			  if(~ (busy | trigger)) begin
				 state <= next_state;
			  end
		   end
		   default : begin
		   end
		 endcase
	  end
   end
endmodule
module ad9958_core(
				   input 			 clock,
				   input 			 reset_n,

				   input [32-1:0] 	 ftw_ch0,
				   input [32-1:0] 	 ftw_ch1,
				   input [10-1:0] 	 asf_ch0,
				   input [10-1:0] 	 asf_ch1,


				   input 			 vco_gain,
				   input [4:0] 		 clock_multiplier,

				   input [1:0] 		 dac_fscale_ch0,
				   input [1:0] 		 dac_fscale_ch1,

				   input 			 busy,

				   output reg 		 trigger,
				   output reg 		 four_bit,
				   output reg [5:0]  bits_to_send,
				   output reg [63:0] data_input,

				   output reg 		 master_reset,
				   output reg 		 io_update
				   );



   parameter
	 MSB_FIRST = 0,
	 LSB_FIRST = 1;

   parameter
	 ASF_EN = 13'b1000000000000;

   parameter
	 CH0_ENABLE = 8'b01000000,
	 CH1_ENABLE = 8'b10000000;

   parameter
	 IO_MODE = `IOMODE_4_BIT;

   


   parameter
	 STATE_MASTER_RESET = 0,
	 STATE_IO_UPDATE = 1,
	 STATE_INSTRUCTION_WRITE = 2,
	 STATE_CSR_CONFIG = 3,
	 STATE_FR1_CONFIG = 4,
	 STATE_FR2_CONFIG = 5,
	 STATE_CFR_CONFIG = 6,
	 STATE_FTW_CONFIG = 7,
	 STATE_ASF_CONFIG = 8,
	 STATE_WAIT = 9;
   
   parameter
	 NONE_SELECTED = 0,
	 CH0_SELECTED = 1,
	 CH1_SELECTED = 2,
	 BOTH_SELECTED = 3;

   parameter
	 TUNE_FREQ = 0,
	 TUNE_AMPL = 1;
   
   reg 								 init_done;
   reg [1:0] 						 channel_select;
   reg 								 io_mode_set;

   reg [3:0] 						 state;
   reg [3:0] 						 next_state;
   
   reg [7:0] 						 reg_address;

   reg [1:0] 						 tune_target;
   
   reg [32-1:0] 					 ftw_ch0_buf;
   reg [32-1:0] 					 ftw_ch1_buf;
   reg [32-1:0] 					 asf_ch0_buf;
   reg [32-1:0] 					 asf_ch1_buf;


   always @(posedge io_update) begin
	  ftw_ch0_buf <= ftw_ch0;
	  ftw_ch1_buf <= ftw_ch1;

	  asf_ch0_buf <= asf_ch0;
	  asf_ch1_buf <= asf_ch1;
   end

   always @(posedge clock) begin
	  if(~reset_n) begin
		 init_done <= 0;
		 master_reset <= 0;
		 state <= STATE_MASTER_RESET;
		 io_mode_set <= 0;
	  end else begin
		 case(state)
		   STATE_MASTER_RESET : begin
			  four_bit <= 0;
			  master_reset <= 0;
			  state <= STATE_INSTRUCTION_WRITE;
			  next_state <= STATE_CSR_CONFIG;
			  channel_select <= BOTH_SELECTED;
			  reg_address <= `ADDR_CSR;
			  tune_target <= TUNE_FREQ;

		   end

		   STATE_IO_UPDATE : begin
			  io_update <= 1;
			  state <= STATE_WAIT;
			  next_state <= STATE_INSTRUCTION_WRITE;
			  channel_select <= CH0_SELECTED;
			  

		   end

		   STATE_INSTRUCTION_WRITE : begin
			  state <= STATE_WAIT;
			  master_reset <= 0;

			  trigger <= 1;
			  data_input <= reg_address | `INSTRUCTION_WRITE;
			  bits_to_send <= `SIZE_INST;

			  if(io_mode_set) begin
				 four_bit <= 1;
			  end else begin
				 four_bit <= 0;
			  end
			  
			  case(reg_address)
				`ADDR_CSR : begin
				   next_state <= STATE_CSR_CONFIG;
				end
				`ADDR_FR1 : begin
				   next_state <= STATE_FR1_CONFIG;
				end
				`ADDR_FR2 : begin
				   next_state <= STATE_FR2_CONFIG;
				end
				`ADDR_CFR : begin
				   next_state <= STATE_CFR_CONFIG;
				end
				`ADDR_CFTW0 : begin
				   next_state <= STATE_FTW_CONFIG;
				end
				`ADDR_ACR : begin
				   next_state <= STATE_ASF_CONFIG;
				end
				default : begin
				   next_state <= STATE_INSTRUCTION_WRITE;
				end
			  endcase
			  
		   end

		   STATE_CSR_CONFIG : begin
			  state <= STATE_WAIT;
			  trigger <= 1;

			  bits_to_send <= `SIZE_CSR;
			  
			  case (channel_select)
				CH0_SELECTED : begin

					next_state <= STATE_INSTRUCTION_WRITE;
				   data_input <= CH0_ENABLE | MSB_FIRST | IO_MODE;
				   case(tune_target)
					 TUNE_FREQ : begin
						reg_address <= `ADDR_CFTW0;
					 end
					 TUNE_AMPL :begin
						reg_address <= `ADDR_ACR;
					 end
				   endcase
				end

				CH1_SELECTED : begin
					next_state <= STATE_INSTRUCTION_WRITE;
				   data_input <= CH1_ENABLE | MSB_FIRST | IO_MODE;
				   case(tune_target)
					 TUNE_FREQ : begin
						reg_address <= `ADDR_CFTW0;
					 end
					 TUNE_AMPL :begin
						reg_address <= `ADDR_ACR;
					 end
				   endcase
				end

				BOTH_SELECTED : begin

					next_state <= STATE_IO_UPDATE;
				   io_mode_set <= 1;
					data_input <= CH0_ENABLE | CH1_ENABLE | MSB_FIRST | IO_MODE;
				   reg_address <= `ADDR_FR1;
				end
				
				default : begin
				   data_input <= MSB_FIRST | IO_MODE;
				   reg_address <= `ADDR_FR1;
				end
			  endcase
		   end

		   STATE_FR1_CONFIG : begin
			  state <= STATE_WAIT;
			  next_state <= STATE_IO_UPDATE;
			  reg_address <= `ADDR_CFR;

			  trigger <= 1;
			  bits_to_send <= `SIZE_FR1;
			  data_input <= (vco_gain << 23) | (clock_multiplier << 18);
			  
		   end


		   STATE_FR2_CONFIG : begin
			  state <= STATE_WAIT;
			  next_state <= STATE_IO_UPDATE;
			  reg_address <= `ADDR_CSR;
		   end

		   STATE_CFR_CONFIG : begin
			  state <= STATE_WAIT;
			  next_state <= STATE_IO_UPDATE;
			  init_done <= 1;

			  trigger <= 1;

			  bits_to_send <= `SIZE_CFR;
			  data_input <= (dac_fscale_ch0 << 8);
			  
			  reg_address <= `ADDR_CSR;
		   end

		   STATE_FTW_CONFIG : begin
			  state <= STATE_WAIT;
			  next_state <= STATE_INSTRUCTION_WRITE;

			  trigger <= 1;
			  bits_to_send <= `SIZE_CFTW0;
			  
			  case(channel_select)
				CH0_SELECTED : begin
				   channel_select <= CH1_SELECTED;
				   data_input <= ftw_ch0_buf;
				   next_state <= STATE_INSTRUCTION_WRITE;
				   tune_target <= TUNE_FREQ;

				end
				CH1_SELECTED : begin
				   channel_select <= CH0_SELECTED;
				   data_input <= ftw_ch1_buf;
				   next_state <= STATE_IO_UPDATE;
				   tune_target <= TUNE_AMPL;

				end
				default : begin

				end
			  endcase

			  reg_address <= `ADDR_CSR;

		   end

		   STATE_ASF_CONFIG : begin
			  state <= STATE_WAIT;

			  trigger <= 1;
			  bits_to_send <= `SIZE_ACR;
			  
			  case (channel_select)
				CH0_SELECTED : begin
				   channel_select <= CH1_SELECTED;

				   next_state <= STATE_INSTRUCTION_WRITE;
				   data_input <= ASF_EN | asf_ch0_buf;
				   tune_target <= TUNE_AMPL;

				end

				CH1_SELECTED : begin
				   channel_select <= CH0_SELECTED;

				   next_state <= STATE_IO_UPDATE;
				   data_input <= ASF_EN | asf_ch1_buf;
				   tune_target <= TUNE_FREQ;
				end
				default : begin
				   channel_select <= CH0_SELECTED;
				end
			  endcase
			  
			  reg_address <= `ADDR_CSR;
		   end

		   STATE_WAIT : begin
			  master_reset <= 0;
			  io_update <= 0;
			  trigger <= 0;

			  if(~ (busy | trigger)) begin
				 state <= next_state;
			  end
		   end
		   default : begin
		   end
		 endcase
	  end
   end
endmodule