data/full_repos/permissive/143278/ivltests/fileline2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/fileline2.v:9: Unsupported: Ignoring delay on this delayed statement.\ninitial begin #0\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module aaa;
reg pass;

`define printfl(x) $display("%0d -> %s:%0d", x, `__FILE__, `__LINE__)
initial begin #0
    pass = 1;

`line 1000 "./ivltests/fileline2.v" 0
    if(`__LINE__ !== 1000) begin
        $display("FAIL"); pass = 0;
    end
    `printfl(1);

`line 2000 "imaginary-include-file" 1
    if(`__LINE__ !== 2000) begin
        $display("FAIL"); pass = 0;
    end
    `printfl(2);

`line 3000 "./ivltests/fileline2.v" 2
    if(`__LINE__ !== 3000) begin
        $display("FAIL"); pass = 0;
    end
    `printfl(3);


    if(pass) $display("PASSED");
end
endmodule
module aaa;

reg pass;

`define printfl(x) $display("%0d -> %s:%0d", x, `__FILE__, `__LINE__)
initial begin #0
    pass = 1;

`line 1000 "./ivltests/fileline2.v" 0
    if(`__LINE__ !== 1000) begin
        $display("FAIL"); pass = 0;
    end
    `printfl(1);

`line 2000 "imaginary-include-file" 1
    if(`__LINE__ !== 2000) begin
        $display("FAIL"); pass = 0;
    end
    `printfl(2);

`line 3000 "./ivltests/fileline2.v" 2
    if(`__LINE__ !== 3000) begin
        $display("FAIL"); pass = 0;
    end
    `printfl(3);


    if(pass) $display("PASSED");
end
endmodule