data/full_repos/permissive/219917900/txrx_rtl_files/rx_rtl_files/five2one_v2.v
 line:16: before: ","
1: b'%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/rx_rtl_files/five2one_v2.v:41: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                 : ... In instance five2one_v2\n   rx_id <= rxd[3:0];\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/219917900/txrx_rtl_files/rx_rtl_files/five2one_v2.v:77: Cannot find file containing module: \'comparator\'\ncomparator comp0(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219917900/txrx_rtl_files/rx_rtl_files,data/full_repos/permissive/219917900/comparator\n             data/full_repos/permissive/219917900/txrx_rtl_files/rx_rtl_files,data/full_repos/permissive/219917900/comparator.v\n             data/full_repos/permissive/219917900/txrx_rtl_files/rx_rtl_files,data/full_repos/permissive/219917900/comparator.sv\n             comparator\n             comparator.v\n             comparator.sv\n             obj_dir/comparator\n             obj_dir/comparator.v\n             obj_dir/comparator.sv\n%Error: data/full_repos/permissive/219917900/txrx_rtl_files/rx_rtl_files/five2one_v2.v:86: Cannot find file containing module: \'comparator\'\ncomparator comp1(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/219917900/txrx_rtl_files/rx_rtl_files/five2one_v2.v:94: Cannot find file containing module: \'comparator\'\ncomparator comp2(\n^~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
function check;
input [11:0] results_all;
begin
	casex(results_all)
		12'bxxx_xxx_xxx_x11: check = 1;
		12'bxxx_xxx_x1x_xx1: check = 1;
		12'bxxx_xxx_1xx_xx1: check = 1;

		12'bxxx_xx1_xxx_x1x: check = 1;
		12'bxxx_x1x_xxx_x1x: check = 1;
		12'bxx1_xxx_xxx_1xx: check = 1;
		
		


		default: check = 0;
	endcase
end
endfunction
function check;

input [11:0] results_all;
begin
	casex(results_all)
		12'bxxx_xxx_xxx_x11: check = 1;
		12'bxxx_xxx_x1x_xx1: check = 1;
		12'bxxx_xxx_1xx_xx1: check = 1;

		12'bxxx_xx1_xxx_x1x: check = 1;
		12'bxxx_x1x_xxx_x1x: check = 1;
		12'bxx1_xxx_xxx_1xx: check = 1;
		
		


		default: check = 0;
	endcase
end
endfunction