data/full_repos/permissive/113471686/baseline/freq/freq.v
1: b"%Error: data/full_repos/permissive/113471686/baseline/freq/freq.v:43: Cannot find file containing module: 'MERGE_SORTER_TREE'\n  MERGE_SORTER_TREE #(9, 64, 32)\n  ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113471686/baseline/freq,data/full_repos/permissive/113471686/MERGE_SORTER_TREE\n             data/full_repos/permissive/113471686/baseline/freq,data/full_repos/permissive/113471686/MERGE_SORTER_TREE.v\n             data/full_repos/permissive/113471686/baseline/freq,data/full_repos/permissive/113471686/MERGE_SORTER_TREE.sv\n             MERGE_SORTER_TREE\n             MERGE_SORTER_TREE.v\n             MERGE_SORTER_TREE.sv\n             obj_dir/MERGE_SORTER_TREE\n             obj_dir/MERGE_SORTER_TREE.v\n             obj_dir/MERGE_SORTER_TREE.sv\n%Error: Exiting due to 1 error(s)\n"
module freq(input  wire CLK,
            input  wire RST_IN,
            output wire OUT);

  reg RST; always @(posedge CLK) RST <= RST_IN;
     
  wire [(`DATW<<`W_LOG)-1:0] merge_sorter_tree_din;
  wire [(1<<`W_LOG)-1:0]     merge_sorter_tree_dinen;
  wire [(1<<`W_LOG)-1:0]     merge_sorter_tree_ful;
  wire [`DATW-1:0]           merge_sorter_tree_dot;
  wire                       merge_sorter_tree_doten;
  
  assign merge_sorter_tree_dinen = ~merge_sorter_tree_ful;
  
  genvar i;
  generate
    for (i=0; i<(1<<`W_LOG); i=i+1) begin: loop
      wire [`KEYW-1:0] init_key = (1<<`W_LOG) - i;
      reg  [`DATW-1:0] init_record;
      always @(posedge CLK) begin
        if      (RST)                        init_record <= {{(`DATW-`KEYW){1'b1}}, init_key};
        else if (merge_sorter_tree_dinen[i]) init_record <= init_record + (1<<`W_LOG);
      end
      assign merge_sorter_tree_din[`DATW*(i+1)-1:`DATW*i] = init_record;
    end
  endgenerate

  MERGE_SORTER_TREE #(`W_LOG, `DATW, `KEYW)
  merge_sorter_tree(CLK, RST, 1'b0, merge_sorter_tree_din, merge_sorter_tree_dinen, 
                    merge_sorter_tree_ful, merge_sorter_tree_dot, merge_sorter_tree_doten);

  reg [`DATW-1:0] dot_buf; 
  always @(posedge CLK) begin
    if (merge_sorter_tree_doten) dot_buf <= merge_sorter_tree_dot;
  end

  assign OUT = ^dot_buf;
  
endmodule
module freq(input  wire CLK,
            input  wire RST_IN,
            output wire OUT);


  reg RST; always @(posedge CLK) RST <= RST_IN;
     
  wire [(`DATW<<`W_LOG)-1:0] merge_sorter_tree_din;
  wire [(1<<`W_LOG)-1:0]     merge_sorter_tree_dinen;
  wire [(1<<`W_LOG)-1:0]     merge_sorter_tree_ful;
  wire [`DATW-1:0]           merge_sorter_tree_dot;
  wire                       merge_sorter_tree_doten;
  
  assign merge_sorter_tree_dinen = ~merge_sorter_tree_ful;
  
  genvar i;
  generate
    for (i=0; i<(1<<`W_LOG); i=i+1) begin: loop
      wire [`KEYW-1:0] init_key = (1<<`W_LOG) - i;
      reg  [`DATW-1:0] init_record;
      always @(posedge CLK) begin
        if      (RST)                        init_record <= {{(`DATW-`KEYW){1'b1}}, init_key};
        else if (merge_sorter_tree_dinen[i]) init_record <= init_record + (1<<`W_LOG);
      end
      assign merge_sorter_tree_din[`DATW*(i+1)-1:`DATW*i] = init_record;
    end
  endgenerate

  MERGE_SORTER_TREE #(`W_LOG, `DATW, `KEYW)
  merge_sorter_tree(CLK, RST, 1'b0, merge_sorter_tree_din, merge_sorter_tree_dinen, 
                    merge_sorter_tree_ful, merge_sorter_tree_dot, merge_sorter_tree_doten);

  reg [`DATW-1:0] dot_buf; 
  always @(posedge CLK) begin
    if (merge_sorter_tree_doten) dot_buf <= merge_sorter_tree_dot;
  end

  assign OUT = ^dot_buf;
  
endmodule