data/full_repos/permissive/143278/vhdl_tests/mux2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/mux2.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/mux2.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/mux2.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
  wire o;
  reg  i0, i1, sel;

  mux2 uut(o, i0, i1, sel);

  initial begin
    i0 <= 1;
    i1 <= 0;
    sel <= 0;
    #1;
    sel <= 1;
    #1;
    i1 <= 1;
    #1;
  end

  always @(o)
    $display(o);

endmodule
module testbench;

  wire o;
  reg  i0, i1, sel;

  mux2 uut(o, i0, i1, sel);

  initial begin
    i0 <= 1;
    i1 <= 0;
    sel <= 0;
    #1;
    sel <= 1;
    #1;
    i1 <= 1;
    #1;
  end

  always @(o)
    $display(o);

endmodule