data/full_repos/permissive/152129793/comun/modulos.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:576: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.los_interruptores\n  wire [7:0] posx = hc - XINIT;   \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:577: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.los_interruptores\n  wire [7:0] posy = vc - YINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:503: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_leds\n  wire [7:0] pos = hc - XINIT;   \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:399: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n    posicion_caracter_en_pantalla = (hc - XINIT + 1)>>4;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:403: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n  wire [7:0] posx = hc - XINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:404: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n  wire [7:0] posy = vc - YINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:436: Bit extraction of array[127:0] requires 7 bit index, not 8 bits.\n                                                                        : ... In instance display.display_digitos\n        scan_actual <= chars[charaddr];\n                            ^\n%Warning-UNSIGNED: data/full_repos/permissive/152129793/comun/modulos.v:216: Comparison is constant due to unsigned arithmetic\n                                                                           : ... In instance display.sincronismos\n    if (hcont>=0 && hcont<HACTIVE && vcont>=0 && vcont<VACTIVE)\n             ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152129793/comun/modulos.v:216: Comparison is constant due to unsigned arithmetic\n                                                                           : ... In instance display.sincronismos\n    if (hcont>=0 && hcont<HACTIVE && vcont>=0 && vcont<VACTIVE)\n                                          ^~\n%Error: Exiting due to 9 warning(s)\n'
module display (
  input wire clk,


  input wire [3:0] d0,
  input wire [3:0] d1,
  input wire [3:0] d2,
  input wire [3:0] d3,

  input wire [3:0] d4,
  input wire [3:0] d5,
  input wire [3:0] d6,
  input wire [3:0] d7,

  input wire [3:0] d8,
  input wire [3:0] d9,
  input wire [3:0] d10,
  input wire [3:0] d11,


  input wire [7:0] led,
  

  output wire [7:0] switch,
  

  output wire evento_teclado,
  output wire [7:0] scancode,
  output wire soltada,
  output wire extendida,
  

  input wire [5:0] ri,
  input wire [5:0] gi,
  input wire [5:0] bi,
  output wire [10:0] posx,
  output wire [10:0] posy,
  output wire display_activo,  
    

  input wire clkps2,
  input wire dataps2,
  

  output wire [5:0] r,
  output wire [5:0] g,
  output wire [5:0] b,
  output wire hs,
  output wire vs
  );
  
  parameter YINIT = 392;
  parameter FONTFILE = "fuente_hexadecimal_ibm.hex";
  
  wire [10:0] hc, vc;
  wire den;
  
  wire [5:0] rdigits, gdigits, bdigits;
  wire [5:0] rleds, gleds, bleds;
  wire [5:0] rswitch, gswitch, bswitch;
  
  ps2_port el_teclado (
    .clk(clk),
    .enable_rcv(1'b1),
    .kb_or_mouse(1'b0),
    .ps2clk_ext(clkps2),
    .ps2data_ext(dataps2),
    .kb_interrupt(evento_teclado),
    .scancode(scancode),
    .released(soltada),
    .extended(extendida)
  );  
  
  videosyncs sincronismos (
    .clk(clk),
    .hs(hs),
    .vs(vs),
 	  .hc(hc),
	  .vc(vc),
    .display_enable(den)
    );
    
  switches #(.YINIT(YINIT)) los_interruptores (
    .clk(clk),
    .evento_teclado(evento_teclado),
    .scancode(scancode),
    .extended(extendida),
    .released(soltada),
    .switch(switch),
    .hc(hc),
    .vc(vc),
    .r(rswitch),
    .g(gswitch),
    .b(bswitch)
    );

  leds #(.YINIT(YINIT+32)) display_leds (
    .led(led),
    .hc(hc),
    .vc(vc),
    .r(rleds),
    .g(gleds),
    .b(bleds)
    );
    
  digits #(.YINIT(YINIT+56), .FONTFILE(FONTFILE)) display_digitos (
    .clk(clk),
    .d0(d0),
    .d1(d1),
    .d2(d2),
    .d3(d3),
    .d4(d4),
    .d5(d5),
    .d6(d6),
    .d7(d7),
    .d8(d8),
    .d9(d9),
    .d10(d10),
    .d11(d11),
    .hc(hc),
    .vc(vc),
    .r(rdigits),
    .g(gdigits),
    .b(bdigits)
    );


  wire [5:0] ro = rdigits | rleds | rswitch;
  wire [5:0] go = gdigits | gleds | gswitch;
  wire [5:0] bo = bdigits | bleds | bswitch;
  
  wire es_negro = ({ro,go,bo} == 18'h00000);
  


  assign r = (den == 1'b1)? ((es_negro)? ri : ro) : 6'h00;
  assign g = (den == 1'b1)? ((es_negro)? gi : go) : 6'h00;
  assign b = (den == 1'b1)? ((es_negro)? bi : bo) : 6'h00;

  assign posx = hc;
  assign posy = vc;
  assign display_activo = den;

endmodule
module display (
  input wire clk,


  input wire [3:0] d0,
  input wire [3:0] d1,
  input wire [3:0] d2,
  input wire [3:0] d3,

  input wire [3:0] d4,
  input wire [3:0] d5,
  input wire [3:0] d6,
  input wire [3:0] d7,

  input wire [3:0] d8,
  input wire [3:0] d9,
  input wire [3:0] d10,
  input wire [3:0] d11,


  input wire [7:0] led,
  

  output wire [7:0] switch,
  

  output wire evento_teclado,
  output wire [7:0] scancode,
  output wire soltada,
  output wire extendida,
  

  input wire [5:0] ri,
  input wire [5:0] gi,
  input wire [5:0] bi,
  output wire [10:0] posx,
  output wire [10:0] posy,
  output wire display_activo,  
    

  input wire clkps2,
  input wire dataps2,
  

  output wire [5:0] r,
  output wire [5:0] g,
  output wire [5:0] b,
  output wire hs,
  output wire vs
  );

  
  parameter YINIT = 392;
  parameter FONTFILE = "fuente_hexadecimal_ibm.hex";
  
  wire [10:0] hc, vc;
  wire den;
  
  wire [5:0] rdigits, gdigits, bdigits;
  wire [5:0] rleds, gleds, bleds;
  wire [5:0] rswitch, gswitch, bswitch;
  
  ps2_port el_teclado (
    .clk(clk),
    .enable_rcv(1'b1),
    .kb_or_mouse(1'b0),
    .ps2clk_ext(clkps2),
    .ps2data_ext(dataps2),
    .kb_interrupt(evento_teclado),
    .scancode(scancode),
    .released(soltada),
    .extended(extendida)
  );  
  
  videosyncs sincronismos (
    .clk(clk),
    .hs(hs),
    .vs(vs),
 	  .hc(hc),
	  .vc(vc),
    .display_enable(den)
    );
    
  switches #(.YINIT(YINIT)) los_interruptores (
    .clk(clk),
    .evento_teclado(evento_teclado),
    .scancode(scancode),
    .extended(extendida),
    .released(soltada),
    .switch(switch),
    .hc(hc),
    .vc(vc),
    .r(rswitch),
    .g(gswitch),
    .b(bswitch)
    );

  leds #(.YINIT(YINIT+32)) display_leds (
    .led(led),
    .hc(hc),
    .vc(vc),
    .r(rleds),
    .g(gleds),
    .b(bleds)
    );
    
  digits #(.YINIT(YINIT+56), .FONTFILE(FONTFILE)) display_digitos (
    .clk(clk),
    .d0(d0),
    .d1(d1),
    .d2(d2),
    .d3(d3),
    .d4(d4),
    .d5(d5),
    .d6(d6),
    .d7(d7),
    .d8(d8),
    .d9(d9),
    .d10(d10),
    .d11(d11),
    .hc(hc),
    .vc(vc),
    .r(rdigits),
    .g(gdigits),
    .b(bdigits)
    );


  wire [5:0] ro = rdigits | rleds | rswitch;
  wire [5:0] go = gdigits | gleds | gswitch;
  wire [5:0] bo = bdigits | bleds | bswitch;
  
  wire es_negro = ({ro,go,bo} == 18'h00000);
  


  assign r = (den == 1'b1)? ((es_negro)? ri : ro) : 6'h00;
  assign g = (den == 1'b1)? ((es_negro)? gi : go) : 6'h00;
  assign b = (den == 1'b1)? ((es_negro)? bi : bo) : 6'h00;

  assign posx = hc;
  assign posy = vc;
  assign display_activo = den;

endmodule