data/full_repos/permissive/143278/ivltests/ga_mod2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #10 C <= 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #10 if (out !== 2\'b00) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #10 C <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #10 if (out !== 2\'b10) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:48: Unsupported: Ignoring delay on this delayed statement.\n      #10 C <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod2.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #10 if (out !== 2\'b01) begin\n      ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg C;
   reg [1:0] in;
   wire [1:0] out;

   DFF u [1:0] (out, in, C);

   initial begin
      C <= 0;
      in <= 2'b00;

      #10 C <= 1;
      #10 if (out !== 2'b00) begin
	 $display("FAILED -- out=%b, in=%b", out, in);
	 $finish;
      end

      C <= 0;
      in <= 2'b10;
      #10 C <= 1;
      #10 if (out !== 2'b10) begin
	 $display("FAILED -- out=%b, in=%b", out, in);
	 $finish;
      end

      C <= 0;
      in <= 2'b01;
      #10 C <= 1;
      #10 if (out !== 2'b01) begin
	 $display("FAILED -- out=%b, in=%b", out, in);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg C;
   reg [1:0] in;
   wire [1:0] out;

   DFF u [1:0] (out, in, C);

   initial begin
      C <= 0;
      in <= 2'b00;

      #10 C <= 1;
      #10 if (out !== 2'b00) begin
	 $display("FAILED -- out=%b, in=%b", out, in);
	 $finish;
      end

      C <= 0;
      in <= 2'b10;
      #10 C <= 1;
      #10 if (out !== 2'b10) begin
	 $display("FAILED -- out=%b, in=%b", out, in);
	 $finish;
      end

      C <= 0;
      in <= 2'b01;
      #10 C <= 1;
      #10 if (out !== 2'b01) begin
	 $display("FAILED -- out=%b, in=%b", out, in);
	 $finish;
      end

      $display("PASSED");
   end

endmodule