data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sim/sim1.v
 line:41: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sim/sim1.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #10 cp <= ~cp;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sim/sim1.v:15: Cannot find file containing module: \'counter_mod8\'\n  counter_mod8 test(.cp(cp), .qcc(qcc), .Q(Q));\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sim,data/full_repos/permissive/136584400/counter_mod8\n             data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sim,data/full_repos/permissive/136584400/counter_mod8.v\n             data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sim,data/full_repos/permissive/136584400/counter_mod8.sv\n             counter_mod8\n             counter_mod8.v\n             counter_mod8.sv\n             obj_dir/counter_mod8\n             obj_dir/counter_mod8.v\n             obj_dir/counter_mod8.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_module;
  wire [3:0] Q;
  reg cp;
  wire qcc;

  counter_mod8 test(.cp(cp), .qcc(qcc), .Q(Q));

initial begin
  cp <= 0;
end

always begin
  #10 cp <= ~cp;
end

endmodule
module test_module;

  wire [3:0] Q;
  reg cp;
  wire qcc;

  counter_mod8 test(.cp(cp), .qcc(qcc), .Q(Q));

initial begin
  cp <= 0;
end

always begin
  #10 cp <= ~cp;
end

endmodule