data/full_repos/permissive/143278/ivltests/pr2722339b.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2722339b.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:8: Operator MODDIV expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                         : ... In instance top\n  assign ruu = a % b;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:8: Operator MODDIV expects 16 bits on the RHS, but RHS\'s VARREF \'b\' generates 8 bits.\n                                                                         : ... In instance top\n  assign ruu = a % b;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:9: Operator MODDIV expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                         : ... In instance top\n  assign rsu = $signed(a) % b;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:9: Operator MODDIV expects 16 bits on the RHS, but RHS\'s VARREF \'b\' generates 8 bits.\n                                                                         : ... In instance top\n  assign rsu = $signed(a) % b;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:10: Operator MODDIV expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                          : ... In instance top\n  assign rus = a % $signed(b);\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:10: Operator MODDIV expects 16 bits on the RHS, but RHS\'s SIGNED generates 8 bits.\n                                                                          : ... In instance top\n  assign rus = a % $signed(b);\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:11: Operator MODDIVS expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                          : ... In instance top\n  assign rss = $signed(a) % $signed(b);\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:11: Operator MODDIVS expects 16 bits on the RHS, but RHS\'s SIGNED generates 8 bits.\n                                                                          : ... In instance top\n  assign rss = $signed(a) % $signed(b);\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:19: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                          : ... In instance top\n      a = $random;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:20: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                          : ... In instance top\n      b = $random;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:24: Operator MODDIV expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                          : ... In instance top\n      if (ruu !== a%b) begin\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:24: Operator MODDIV expects 16 bits on the RHS, but RHS\'s VARREF \'b\' generates 8 bits.\n                                                                          : ... In instance top\n      if (ruu !== a%b) begin\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:29: Operator MODDIV expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                          : ... In instance top\n      if (rsu !== a%b) begin\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:29: Operator MODDIV expects 16 bits on the RHS, but RHS\'s VARREF \'b\' generates 8 bits.\n                                                                          : ... In instance top\n      if (rsu !== a%b) begin\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:34: Operator MODDIV expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                          : ... In instance top\n      if (rus !== a%b) begin\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:34: Operator MODDIV expects 16 bits on the RHS, but RHS\'s VARREF \'b\' generates 8 bits.\n                                                                          : ... In instance top\n      if (rus !== a%b) begin\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:39: Operator MODDIVS expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                          : ... In instance top\n      res = $signed(a)%$signed(b);\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2722339b.v:39: Operator MODDIVS expects 16 bits on the RHS, but RHS\'s SIGNED generates 8 bits.\n                                                                          : ... In instance top\n      res = $signed(a)%$signed(b);\n                      ^\n%Error: Exiting due to 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass;
  reg   [7:0] a, b;
  wire [15:0] ruu, rsu, rus, rss;
  reg signed [15:0] res;
  integer i;

  assign ruu = a % b;
  assign rsu = $signed(a) % b;
  assign rus = a % $signed(b);
  assign rss = $signed(a) % $signed(b);

  initial begin
    pass = 1'b1;


    for (i = 0; i < 1000; i = i + 1) begin

      a = $random;
      b = $random;
      #1;


      if (ruu !== a%b) begin
        $display("FAILED: u%%u (%b%%%b) gave %b, expected %b", a, b, ruu, a%b);
        pass = 1'b0;
      end

      if (rsu !== a%b) begin
        $display("FAILED: s%%u (%b%%%b) gave %b, expected %b", a, b, rsu, a%b);
        pass = 1'b0;
      end

      if (rus !== a%b) begin
        $display("FAILED: u%%s (%b%%%b) gave %b, expected %b", a, b, rus, a%b);
        pass = 1'b0;
      end

      res = $signed(a)%$signed(b);
      if (rss !== res) begin
        $display("FAILED: s%%s (%b%%%b) gave %b, expected %b", a, b, rss, res);
        pass = 1'b0;
      end
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  reg   [7:0] a, b;
  wire [15:0] ruu, rsu, rus, rss;
  reg signed [15:0] res;
  integer i;

  assign ruu = a % b;
  assign rsu = $signed(a) % b;
  assign rus = a % $signed(b);
  assign rss = $signed(a) % $signed(b);

  initial begin
    pass = 1'b1;


    for (i = 0; i < 1000; i = i + 1) begin

      a = $random;
      b = $random;
      #1;


      if (ruu !== a%b) begin
        $display("FAILED: u%%u (%b%%%b) gave %b, expected %b", a, b, ruu, a%b);
        pass = 1'b0;
      end

      if (rsu !== a%b) begin
        $display("FAILED: s%%u (%b%%%b) gave %b, expected %b", a, b, rsu, a%b);
        pass = 1'b0;
      end

      if (rus !== a%b) begin
        $display("FAILED: u%%s (%b%%%b) gave %b, expected %b", a, b, rus, a%b);
        pass = 1'b0;
      end

      res = $signed(a)%$signed(b);
      if (rss !== res) begin
        $display("FAILED: s%%s (%b%%%b) gave %b, expected %b", a, b, rss, res);
        pass = 1'b0;
      end
    end

    if (pass) $display("PASSED");
  end
endmodule