data/full_repos/permissive/179227721/final/logic_design_tb.v
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1: b'%Error: data/full_repos/permissive/179227721/final/logic_design_tb.v:15: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("logic_design_wave.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/179227721/final/logic_design_tb.v:16: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, ld);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/179227721/final/logic_design_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/179227721/final/logic_design_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/179227721/final/logic_design_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/179227721/final/logic_design_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n           #100;\n           ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module logic_design_tb;
   integer i;

   reg [4:0] sw;
   reg       clock;
   wire [6:0] HEX0, HEX1, HEX3;

   logic_design ld(.SW(sw),
                   .CLOCK_50(clock),
                   .HEX0(HEX0),
                   .HEX1(HEX1),
                   .HEX3(HEX3));

   initial begin
      $dumpfile("logic_design_wave.vcd");
      $dumpvars(0, ld);

      clock <= 0;
      sw <= 0;

      #10;
      sw[4] <= 1;
      #10;
      sw <= 0;
      #10;

      for(i = 0; i < 512; i++)
        begin
           clock <= ~clock;

           if(i % 4 == 0)
             begin
                sw <= sw + 1;
             end
           #100;
        end
   end

endmodule
module logic_design_tb;

   integer i;

   reg [4:0] sw;
   reg       clock;
   wire [6:0] HEX0, HEX1, HEX3;

   logic_design ld(.SW(sw),
                   .CLOCK_50(clock),
                   .HEX0(HEX0),
                   .HEX1(HEX1),
                   .HEX3(HEX3));

   initial begin
      $dumpfile("logic_design_wave.vcd");
      $dumpvars(0, ld);

      clock <= 0;
      sw <= 0;

      #10;
      sw[4] <= 1;
      #10;
      sw <= 0;
      #10;

      for(i = 0; i < 512; i++)
        begin
           clock <= ~clock;

           if(i % 4 == 0)
             begin
                sw <= sw + 1;
             end
           #100;
        end
   end

endmodule