data/full_repos/permissive/119453325/import/tv80/rtl/core/tv80_core.v
1: b'%Error: data/full_repos/permissive/119453325/import/tv80/rtl/core/tv80_core.v:215: Cannot find file containing module: \'tv80_mcode\'\n  tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119453325/import/tv80/rtl/core,data/full_repos/permissive/119453325/tv80_mcode\n             data/full_repos/permissive/119453325/import/tv80/rtl/core,data/full_repos/permissive/119453325/tv80_mcode.v\n             data/full_repos/permissive/119453325/import/tv80/rtl/core,data/full_repos/permissive/119453325/tv80_mcode.sv\n             tv80_mcode\n             tv80_mcode.v\n             tv80_mcode.sv\n             obj_dir/tv80_mcode\n             obj_dir/tv80_mcode.v\n             obj_dir/tv80_mcode.sv\n%Error: data/full_repos/permissive/119453325/import/tv80/rtl/core/tv80_core.v:271: Cannot find file containing module: \'tv80_alu\'\n  tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu\n  ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/119453325/import/tv80/rtl/core/tv80_core.v:944: Operator NEQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                                         : ... In instance tv80_core\n      if (IncDec_16[2] == 1\'b1 && ((tstate[2] && wait_n == 1\'b1 && mcycle != 3\'b001) || (tstate[3] && mcycle[0])) ) \n                                                                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/119453325/import/tv80/rtl/core/tv80_core.v:973: Operator NEQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                                         : ... In instance tv80_core\n      else if (IncDec_16[2] == 1\'b1 && ((tstate[2] && mcycle != 3\'b001) || (tstate[3] && mcycle[0])) ) \n                                                             ^~\n%Error: data/full_repos/permissive/119453325/import/tv80/rtl/core/tv80_core.v:980: Cannot find file containing module: \'tv80_reg\'\n  tv80_reg i_reg\n  ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/119453325/import/tv80/rtl/core/tv80_core.v:1242: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'mcycle\' generates 7 bits.\n                                                                                          : ... In instance tv80_core\n                              Pre_XY_F_M <= #1 mcycle;\n                                         ^~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
function [6:0] number_to_bitvec;
    input [2:0] num;
    begin
      case (num)
        1 : number_to_bitvec = 7'b0000001;
        2 : number_to_bitvec = 7'b0000010;
        3 : number_to_bitvec = 7'b0000100;
        4 : number_to_bitvec = 7'b0001000;
        5 : number_to_bitvec = 7'b0010000;
        6 : number_to_bitvec = 7'b0100000;
        7 : number_to_bitvec = 7'b1000000;
        default : number_to_bitvec = 7'bx;
      endcase
    end
  endfunction
function [6:0] number_to_bitvec;

    input [2:0] num;
    begin
      case (num)
        1 : number_to_bitvec = 7'b0000001;
        2 : number_to_bitvec = 7'b0000010;
        3 : number_to_bitvec = 7'b0000100;
        4 : number_to_bitvec = 7'b0001000;
        5 : number_to_bitvec = 7'b0010000;
        6 : number_to_bitvec = 7'b0100000;
        7 : number_to_bitvec = 7'b1000000;
        default : number_to_bitvec = 7'bx;
      endcase
    end
  endfunction