data/full_repos/permissive/161029703/xilinx/NaiveMIPS/ip_repo/confreg/confreg_1.0/hdl/confreg_v1_0.v
1: b"%Error: data/full_repos/permissive/161029703/xilinx/NaiveMIPS/ip_repo/confreg/confreg_1.0/hdl/confreg_v1_0.v:52: Cannot find file containing module: 'confreg_v1_0_S00_AXI'\n confreg_v1_0_S00_AXI # ( \n ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161029703/xilinx/NaiveMIPS/ip_repo/confreg/confreg_1.0/hdl,data/full_repos/permissive/161029703/confreg_v1_0_S00_AXI\n             data/full_repos/permissive/161029703/xilinx/NaiveMIPS/ip_repo/confreg/confreg_1.0/hdl,data/full_repos/permissive/161029703/confreg_v1_0_S00_AXI.v\n             data/full_repos/permissive/161029703/xilinx/NaiveMIPS/ip_repo/confreg/confreg_1.0/hdl,data/full_repos/permissive/161029703/confreg_v1_0_S00_AXI.sv\n             confreg_v1_0_S00_AXI\n             confreg_v1_0_S00_AXI.v\n             confreg_v1_0_S00_AXI.sv\n             obj_dir/confreg_v1_0_S00_AXI\n             obj_dir/confreg_v1_0_S00_AXI.v\n             obj_dir/confreg_v1_0_S00_AXI.sv\n%Error: Exiting due to 1 error(s)\n"
module confreg_v1_0 #
	(







		parameter integer C_S00_AXI_DATA_WIDTH	= 32,
		parameter integer C_S00_AXI_ADDR_WIDTH	= 13
	)
	(

		output wire    [31:0] num_data,
		output wire    [15:0] led,
		output wire    [1 :0] led_rg0,
		output wire    [1 :0] led_rg1,
		input  wire    [31:0] SW,
        output wire    [31:0] vidstream_ctl,





		input wire  s00_axi_aclk,
		input wire  s00_axi_aresetn,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
		input wire [2 : 0] s00_axi_awprot,
		input wire  s00_axi_awvalid,
		output wire  s00_axi_awready,
		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
		input wire  s00_axi_wvalid,
		output wire  s00_axi_wready,
		output wire [1 : 0] s00_axi_bresp,
		output wire  s00_axi_bvalid,
		input wire  s00_axi_bready,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
		input wire [2 : 0] s00_axi_arprot,
		input wire  s00_axi_arvalid,
		output wire  s00_axi_arready,
		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
		output wire [1 : 0] s00_axi_rresp,
		output wire  s00_axi_rvalid,
		input wire  s00_axi_rready
	);

	confreg_v1_0_S00_AXI # ( 
		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
	) confreg_v1_0_S00_AXI_inst (
		.num_data(num_data),
		.led(led),
		.led_rg1(led_rg1),
		.led_rg0(led_rg0),
		.SW(SW),
		.vidstream_ctl(vidstream_ctl),
		.S_AXI_ACLK(s00_axi_aclk),
		.S_AXI_ARESETN(s00_axi_aresetn),
		.S_AXI_AWADDR(s00_axi_awaddr),
		.S_AXI_AWPROT(s00_axi_awprot),
		.S_AXI_AWVALID(s00_axi_awvalid),
		.S_AXI_AWREADY(s00_axi_awready),
		.S_AXI_WDATA(s00_axi_wdata),
		.S_AXI_WSTRB(s00_axi_wstrb),
		.S_AXI_WVALID(s00_axi_wvalid),
		.S_AXI_WREADY(s00_axi_wready),
		.S_AXI_BRESP(s00_axi_bresp),
		.S_AXI_BVALID(s00_axi_bvalid),
		.S_AXI_BREADY(s00_axi_bready),
		.S_AXI_ARADDR(s00_axi_araddr),
		.S_AXI_ARPROT(s00_axi_arprot),
		.S_AXI_ARVALID(s00_axi_arvalid),
		.S_AXI_ARREADY(s00_axi_arready),
		.S_AXI_RDATA(s00_axi_rdata),
		.S_AXI_RRESP(s00_axi_rresp),
		.S_AXI_RVALID(s00_axi_rvalid),
		.S_AXI_RREADY(s00_axi_rready)
	);





	endmodule
module confreg_v1_0 #
	(







		parameter integer C_S00_AXI_DATA_WIDTH	= 32,
		parameter integer C_S00_AXI_ADDR_WIDTH	= 13
	)
	(

		output wire    [31:0] num_data,
		output wire    [15:0] led,
		output wire    [1 :0] led_rg0,
		output wire    [1 :0] led_rg1,
		input  wire    [31:0] SW,
        output wire    [31:0] vidstream_ctl,





		input wire  s00_axi_aclk,
		input wire  s00_axi_aresetn,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
		input wire [2 : 0] s00_axi_awprot,
		input wire  s00_axi_awvalid,
		output wire  s00_axi_awready,
		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
		input wire  s00_axi_wvalid,
		output wire  s00_axi_wready,
		output wire [1 : 0] s00_axi_bresp,
		output wire  s00_axi_bvalid,
		input wire  s00_axi_bready,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
		input wire [2 : 0] s00_axi_arprot,
		input wire  s00_axi_arvalid,
		output wire  s00_axi_arready,
		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
		output wire [1 : 0] s00_axi_rresp,
		output wire  s00_axi_rvalid,
		input wire  s00_axi_rready
	);


	confreg_v1_0_S00_AXI # ( 
		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
	) confreg_v1_0_S00_AXI_inst (
		.num_data(num_data),
		.led(led),
		.led_rg1(led_rg1),
		.led_rg0(led_rg0),
		.SW(SW),
		.vidstream_ctl(vidstream_ctl),
		.S_AXI_ACLK(s00_axi_aclk),
		.S_AXI_ARESETN(s00_axi_aresetn),
		.S_AXI_AWADDR(s00_axi_awaddr),
		.S_AXI_AWPROT(s00_axi_awprot),
		.S_AXI_AWVALID(s00_axi_awvalid),
		.S_AXI_AWREADY(s00_axi_awready),
		.S_AXI_WDATA(s00_axi_wdata),
		.S_AXI_WSTRB(s00_axi_wstrb),
		.S_AXI_WVALID(s00_axi_wvalid),
		.S_AXI_WREADY(s00_axi_wready),
		.S_AXI_BRESP(s00_axi_bresp),
		.S_AXI_BVALID(s00_axi_bvalid),
		.S_AXI_BREADY(s00_axi_bready),
		.S_AXI_ARADDR(s00_axi_araddr),
		.S_AXI_ARPROT(s00_axi_arprot),
		.S_AXI_ARVALID(s00_axi_arvalid),
		.S_AXI_ARREADY(s00_axi_arready),
		.S_AXI_RDATA(s00_axi_rdata),
		.S_AXI_RRESP(s00_axi_rresp),
		.S_AXI_RVALID(s00_axi_rvalid),
		.S_AXI_RREADY(s00_axi_rready)
	);





	endmodule