data/full_repos/permissive/133819542/src/mem_wb.v
1: b'%Error: data/full_repos/permissive/133819542/src/mem_wb.v:9: Cannot find include file: const.v\n`include "const.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.sv\n             const.v\n             const.v.v\n             const.v.sv\n             obj_dir/const.v\n             obj_dir/const.v.v\n             obj_dir/const.v.sv\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:17: Define or directive not defined: \'`RegAddrBus\'\n    input  wire  [`RegAddrBus]      mem_waddr       ,\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input  wire  [`RegAddrBus]      mem_waddr       ,\n                             ^\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:18: Define or directive not defined: \'`RegBus\'\n    input  wire  [`RegBus    ]      mem_wdata       ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [`RegBus    ]      mem_hi          ,\n    ^~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:20: Define or directive not defined: \'`RegBus\'\n    input  wire  [`RegBus    ]      mem_hi          ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:21: Define or directive not defined: \'`RegBus\'\n    input  wire  [`RegBus    ]      mem_lo          ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                     mem_LLbit_value ,\n    ^~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [`StallBus  ]      stall           ,\n    ^~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:26: Define or directive not defined: \'`StallBus\'\n    input  wire  [`StallBus  ]      stall           ,\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:30: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg  [`RegAddrBus]      wb_waddr        ,\n    ^~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:30: Define or directive not defined: \'`RegAddrBus\'\n    output  reg  [`RegAddrBus]      wb_waddr        ,\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:31: Define or directive not defined: \'`RegBus\'\n    output  reg  [`RegBus    ]      wb_wdata        ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg  [`RegBus    ]      wb_hi           ,\n    ^~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:33: Define or directive not defined: \'`RegBus\'\n    output  reg  [`RegBus    ]      wb_hi           ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:34: Define or directive not defined: \'`RegBus\'\n    output  reg  [`RegBus    ]      wb_lo           ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:36: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg                     wb_LLbit_value   \n    ^~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:40: Define or directive not defined: \'`RESET_ENABLE\'\n        if(rst == `RESET_ENABLE || (stall[4] == `STOP && stall[5] == `NOSTOP)) begin \n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:40: Define or directive not defined: \'`STOP\'\n        if(rst == `RESET_ENABLE || (stall[4] == `STOP && stall[5] == `NOSTOP)) begin \n                                                ^~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:40: Define or directive not defined: \'`NOSTOP\'\n        if(rst == `RESET_ENABLE || (stall[4] == `STOP && stall[5] == `NOSTOP)) begin \n                                                                     ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:41: Define or directive not defined: \'`NOPRegAddr\'\n            wb_waddr       <=  `NOPRegAddr;\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:42: Define or directive not defined: \'`WRITE_DISABLE\'\n            wb_we          <=  `WRITE_DISABLE;\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:43: Define or directive not defined: \'`ZERO_WORD\'\n            wb_wdata       <=  `ZERO_WORD;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:44: Define or directive not defined: \'`WRITE_DISABLE\'\n            wb_whilo       <=  `WRITE_DISABLE;\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:45: Define or directive not defined: \'`ZERO_WORD\'\n            wb_hi          <=  `ZERO_WORD;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:46: Define or directive not defined: \'`ZERO_WORD\'\n            wb_lo          <=  `ZERO_WORD;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/mem_wb.v:49: Define or directive not defined: \'`NOSTOP\'\n        end else if (stall[4] == `NOSTOP) begin \n                                 ^~~~~~~\n%Error: Exiting due to 27 error(s)\n'
module mem_wb (
    input  wire                     clk        ,
    input  wire                     rst        ,


    input  wire                     mem_we          ,
    input  wire  [`RegAddrBus]      mem_waddr       ,
    input  wire  [`RegBus    ]      mem_wdata       ,
    input  wire                     mem_whilo       ,
    input  wire  [`RegBus    ]      mem_hi          ,
    input  wire  [`RegBus    ]      mem_lo          ,
    input  wire                     mem_LLbit_we    ,
    input  wire                     mem_LLbit_value ,


    input  wire  [`StallBus  ]      stall           ,


    output  reg                     wb_we           ,
    output  reg  [`RegAddrBus]      wb_waddr        ,
    output  reg  [`RegBus    ]      wb_wdata        ,
    output  reg                     wb_whilo        ,
    output  reg  [`RegBus    ]      wb_hi           ,
    output  reg  [`RegBus    ]      wb_lo           ,
    output  reg                     wb_LLbit_we     ,
    output  reg                     wb_LLbit_value   
);

    always @(posedge clk) begin 
        if(rst == `RESET_ENABLE || (stall[4] == `STOP && stall[5] == `NOSTOP)) begin 
            wb_waddr       <=  `NOPRegAddr;
            wb_we          <=  `WRITE_DISABLE;
            wb_wdata       <=  `ZERO_WORD;
            wb_whilo       <=  `WRITE_DISABLE;
            wb_hi          <=  `ZERO_WORD;
            wb_lo          <=  `ZERO_WORD;
            wb_LLbit_we    <=  1'b0;
            wb_LLbit_value <=  1'b0;
        end else if (stall[4] == `NOSTOP) begin 
            wb_waddr       <=  mem_waddr;
            wb_we          <=  mem_we;
            wb_wdata       <=  mem_wdata;
            wb_whilo       <=  mem_whilo;
            wb_hi          <=  mem_hi;
            wb_lo          <=  mem_lo;
            wb_LLbit_we    <=  mem_LLbit_we;
            wb_LLbit_value <=  mem_LLbit_value;
        end
    end

endmodule
module mem_wb (
    input  wire                     clk        ,
    input  wire                     rst        ,


    input  wire                     mem_we          ,
    input  wire  [`RegAddrBus]      mem_waddr       ,
    input  wire  [`RegBus    ]      mem_wdata       ,
    input  wire                     mem_whilo       ,
    input  wire  [`RegBus    ]      mem_hi          ,
    input  wire  [`RegBus    ]      mem_lo          ,
    input  wire                     mem_LLbit_we    ,
    input  wire                     mem_LLbit_value ,


    input  wire  [`StallBus  ]      stall           ,


    output  reg                     wb_we           ,
    output  reg  [`RegAddrBus]      wb_waddr        ,
    output  reg  [`RegBus    ]      wb_wdata        ,
    output  reg                     wb_whilo        ,
    output  reg  [`RegBus    ]      wb_hi           ,
    output  reg  [`RegBus    ]      wb_lo           ,
    output  reg                     wb_LLbit_we     ,
    output  reg                     wb_LLbit_value   
);


    always @(posedge clk) begin 
        if(rst == `RESET_ENABLE || (stall[4] == `STOP && stall[5] == `NOSTOP)) begin 
            wb_waddr       <=  `NOPRegAddr;
            wb_we          <=  `WRITE_DISABLE;
            wb_wdata       <=  `ZERO_WORD;
            wb_whilo       <=  `WRITE_DISABLE;
            wb_hi          <=  `ZERO_WORD;
            wb_lo          <=  `ZERO_WORD;
            wb_LLbit_we    <=  1'b0;
            wb_LLbit_value <=  1'b0;
        end else if (stall[4] == `NOSTOP) begin 
            wb_waddr       <=  mem_waddr;
            wb_we          <=  mem_we;
            wb_wdata       <=  mem_wdata;
            wb_whilo       <=  mem_whilo;
            wb_hi          <=  mem_hi;
            wb_lo          <=  mem_lo;
            wb_LLbit_we    <=  mem_LLbit_we;
            wb_LLbit_value <=  mem_LLbit_value;
        end
    end

endmodule