data/full_repos/permissive/21918193/group_size_is_151_bits/testbench/test_fsm.v
 line:63: before: "forever"
1: b'%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_151_bits/testbench/test_fsm.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_151_bits/testbench/test_fsm.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2); reset = 1; #(20); reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_151_bits/testbench/test_fsm.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2); reset = 1; #(20); reset = 0;\n                            ^\n%Error: data/full_repos/permissive/21918193/group_size_is_151_bits/testbench/test_fsm.v:59: syntax error, unexpected \'@\'\n        @(posedge done);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_151_bits/testbench/test_fsm.v:63: Unsupported: Ignoring delay on this delayed statement.\n    initial #100 forever #(20/2) clk = ~clk;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_151_bits/testbench/test_fsm.v:63: Unsupported: Ignoring delay on this delayed statement.\n    initial #100 forever #(20/2) clk = ~clk;\n            ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_fsm;


	reg clk;
	reg reset;
	reg [25:0] rom_q;


	wire [8:0] rom_addr;
	wire [5:0] ram_a_addr;
	wire [5:0] ram_b_addr;
	wire ram_b_w;
	wire [10:0] pe;
	wire done;


	FSM uut (
		.clk(clk), 
		.reset(reset), 
		.rom_addr(rom_addr), 
		.rom_q(rom_q), 
		.ram_a_addr(ram_a_addr), 
		.ram_b_addr(ram_b_addr), 
		.ram_b_w(ram_b_w), 
		.pe(pe), 
		.done(done)
	);

	initial begin

		clk = 0;
		reset = 0;


		#100;
        

        #(`P/2); reset = 1; #(`P); reset = 0;
        
        @(posedge done);
        $finish;
	end
    
    initial #100 forever #(`P/2) clk = ~clk;
    

    parameter ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;

    always @ (posedge clk)
        case(rom_addr)
        0: rom_q <= {6'd10, 6'd11, ADD, 6'd1, 6'd12};
        1: rom_q <= {6'd20, 6'd21, SUB, 6'd1, 6'd22};
        2: rom_q <= {6'd30, 6'd31, CUBIC, 6'd5, 6'd32};
        3: rom_q <= {6'd40, 6'd41, MULT, 6'd33, 6'd42};
        default: rom_q <= 0;
        endcase
endmodule
module test_fsm;



	reg clk;
	reg reset;
	reg [25:0] rom_q;


	wire [8:0] rom_addr;
	wire [5:0] ram_a_addr;
	wire [5:0] ram_b_addr;
	wire ram_b_w;
	wire [10:0] pe;
	wire done;


	FSM uut (
		.clk(clk), 
		.reset(reset), 
		.rom_addr(rom_addr), 
		.rom_q(rom_q), 
		.ram_a_addr(ram_a_addr), 
		.ram_b_addr(ram_b_addr), 
		.ram_b_w(ram_b_w), 
		.pe(pe), 
		.done(done)
	);

	initial begin

		clk = 0;
		reset = 0;


		#100;
        

        #(`P/2); reset = 1; #(`P); reset = 0;
        
        @(posedge done);
        $finish;
	end
    
    initial #100 forever #(`P/2) clk = ~clk;
    

    parameter ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;

    always @ (posedge clk)
        case(rom_addr)
        0: rom_q <= {6'd10, 6'd11, ADD, 6'd1, 6'd12};
        1: rom_q <= {6'd20, 6'd21, SUB, 6'd1, 6'd22};
        2: rom_q <= {6'd30, 6'd31, CUBIC, 6'd5, 6'd32};
        3: rom_q <= {6'd40, 6'd41, MULT, 6'd33, 6'd42};
        default: rom_q <= 0;
        endcase
endmodule