data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new/UIM_pipeline_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new/UIM_pipeline_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n                        count = count + 1; #5\n                                           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new/UIM_pipeline_tb.v:35: Cannot find file containing module: \'unsigned_integer_multiplier_inferred\'\nunsigned_integer_multiplier_inferred DUTCONTROL (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new,data/full_repos/permissive/124604849/unsigned_integer_multiplier_inferred\n             data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new,data/full_repos/permissive/124604849/unsigned_integer_multiplier_inferred.v\n             data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new,data/full_repos/permissive/124604849/unsigned_integer_multiplier_inferred.sv\n             unsigned_integer_multiplier_inferred\n             unsigned_integer_multiplier_inferred.v\n             unsigned_integer_multiplier_inferred.sv\n             obj_dir/unsigned_integer_multiplier_inferred\n             obj_dir/unsigned_integer_multiplier_inferred.v\n             obj_dir/unsigned_integer_multiplier_inferred.sv\n%Error: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new/UIM_pipeline_tb.v:41: Cannot find file containing module: \'pipeline_unsigned_integer_multiplier\'\npipeline_unsigned_integer_multiplier DUT (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new/UIM_pipeline_tb.v:60: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                                             : ... In instance UIM_pipeline_tb\n                in_A_tb = i;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new/UIM_pipeline_tb.v:63: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                                                                             : ... In instance UIM_pipeline_tb\n                    in_B_tb = j;                 \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/124604849/parallel_unsigned_integer_multiplier.srcs/sim_1/new/UIM_pipeline_tb.v:69: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                                                             : ... In instance UIM_pipeline_tb\n                        clk = clk_ % 2;\n                            ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UIM_pipeline_tb;
parameter A_width = 4, B_width = 4, P_width = 8;

reg  [A_width - 1:0] in_A_tb;
reg  [B_width - 1:0] in_B_tb;

wire [P_width - 1:0] P_Inferred_tb;

wire [P_width - 1:0] P_Pipeline_tb;
reg clk;


unsigned_integer_multiplier_inferred DUTCONTROL (
.A(in_A_tb[A_width-1:0]), 
.B(in_B_tb[B_width-1:0]),  
.P(P_Inferred_tb) 
);

pipeline_unsigned_integer_multiplier DUT (
.A(in_A_tb[A_width-1:0]), 
.B(in_B_tb[B_width-1:0]),
.clk(clk),  
.P(P_Pipeline_tb) 
);

integer i = 0;
integer j = 0;
integer clk_ = 0;
integer count = 0;
integer clock_counter = 1;
integer result_counter = 0;
reg  ctrl_results [255:0][7:0];
    initial
    begin
        $display("Pipeline UIM Test Begin");
            for(i = 0; i < 16; i = i + 1)
            begin
                in_A_tb = i;
                for(j = 0; j < 16; j = j + 1)
                begin
                    in_B_tb = j;                 
                    
                    for(clk_ = 0; clk_ < 4; clk_ = clk_ + 1)
                    begin
                        count = count + 1; #5
                        clock_counter = clock_counter + 1;
                        clk = clk_ % 2;
                        
                        if((clock_counter % 2) == 0)
                        begin

                        end
                        
                        if((clock_counter % 2) == 1)
                        begin
                        
                        end 
                        
                        $display("A=%b=%d",in_A_tb[A_width -1:0],in_A_tb[A_width -1:0]);
                        $display("B=%b=%d",in_B_tb[B_width-1:0],in_B_tb[B_width-1:0]);
                        $display("P = %b = %d", P_Pipeline_tb[P_width - 1:0],P_Pipeline_tb[P_width - 1:0]);
                        $display("clk = %b",clk); 
                        $display("Inferred Sum=%b=%d",P_Inferred_tb[P_width - 1:0],P_Inferred_tb[P_width - 1:0]);
                        







                    end
                end
            end
            $display("Test Successful. %d Trials. Time=%dns.",count, $time);
            $finish;
     end
endmodule
module UIM_pipeline_tb;

parameter A_width = 4, B_width = 4, P_width = 8;

reg  [A_width - 1:0] in_A_tb;
reg  [B_width - 1:0] in_B_tb;

wire [P_width - 1:0] P_Inferred_tb;

wire [P_width - 1:0] P_Pipeline_tb;
reg clk;


unsigned_integer_multiplier_inferred DUTCONTROL (
.A(in_A_tb[A_width-1:0]), 
.B(in_B_tb[B_width-1:0]),  
.P(P_Inferred_tb) 
);

pipeline_unsigned_integer_multiplier DUT (
.A(in_A_tb[A_width-1:0]), 
.B(in_B_tb[B_width-1:0]),
.clk(clk),  
.P(P_Pipeline_tb) 
);

integer i = 0;
integer j = 0;
integer clk_ = 0;
integer count = 0;
integer clock_counter = 1;
integer result_counter = 0;
reg  ctrl_results [255:0][7:0];
    initial
    begin
        $display("Pipeline UIM Test Begin");
            for(i = 0; i < 16; i = i + 1)
            begin
                in_A_tb = i;
                for(j = 0; j < 16; j = j + 1)
                begin
                    in_B_tb = j;                 
                    
                    for(clk_ = 0; clk_ < 4; clk_ = clk_ + 1)
                    begin
                        count = count + 1; #5
                        clock_counter = clock_counter + 1;
                        clk = clk_ % 2;
                        
                        if((clock_counter % 2) == 0)
                        begin

                        end
                        
                        if((clock_counter % 2) == 1)
                        begin
                        
                        end 
                        
                        $display("A=%b=%d",in_A_tb[A_width -1:0],in_A_tb[A_width -1:0]);
                        $display("B=%b=%d",in_B_tb[B_width-1:0],in_B_tb[B_width-1:0]);
                        $display("P = %b = %d", P_Pipeline_tb[P_width - 1:0],P_Pipeline_tb[P_width - 1:0]);
                        $display("clk = %b",clk); 
                        $display("Inferred Sum=%b=%d",P_Inferred_tb[P_width - 1:0],P_Inferred_tb[P_width - 1:0]);
                        







                    end
                end
            end
            $display("Test Successful. %d Trials. Time=%dns.",count, $time);
            $finish;
     end
endmodule