data/full_repos/permissive/176378198/src/ram.v
 line:45: before: "."
1: b"%Error: data/full_repos/permissive/176378198/src/ram.v:7: Expecting include filename. Found: TEXT\n`include `GRVM_PATH(interfacing/register.v) \n                   ^\n%Error: data/full_repos/permissive/176378198/src/ram.v:8: Expecting include filename. Found: TEXT\n`include `GRVM_PATH(interfacing/tri_state_buffer.v) \n                   ^\n%Error: data/full_repos/permissive/176378198/src/ram.v:7: Define or directive not defined: '`GRVM_PATHinterfacing'\n `GRVM_PATHinterfacing/register.v)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/176378198/src/ram.v:7: syntax error, unexpected '/'\n `GRVM_PATHinterfacing/register.v)\n                      ^\n%Error: data/full_repos/permissive/176378198/src/ram.v:8: Define or directive not defined: '`GRVM_PATHinterfacing'\n `GRVM_PATHinterfacing/tri_state_buffer.v)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module ram (
    inout [7 : 0] bus,
    input clk,
    input rst,

    input MI,
    input RO,
    input RI
    );

    reg [3 : 0] mar;
    always @(posedge clk) begin
        mar = bus[3 : 0];
    end

    wire [7 : 0] ram_out;
    SB_RAM512x8 ram512x8_inst (
        .RADDR({5'h0, mar}),
        .RCLK(~clk),
        .RCLKE(1'b1),
        .RDATA(ram_out),
        .RE(1'b1),
        .WDATA(bus),
        .WADDR({5'h0, mar}),
        .WCLK(clk),
        .WCLKE(1'b1),
        .WE(RI)
    );

    tri_state_buffer output_buf [7 : 0] (
        .in(ram_out),
        .out(bus),
        .enable(RO)
    );

    defparam ram512x8_inst.INIT_0 = 256'h000000000000000000000000000000000100010000000000604F1E4D2F4EE01D;

endmodule
module ram (
    inout [7 : 0] bus,
    input clk,
    input rst,

    input MI,
    input RO,
    input RI
    );


    reg [3 : 0] mar;
    always @(posedge clk) begin
        mar = bus[3 : 0];
    end

    wire [7 : 0] ram_out;
    SB_RAM512x8 ram512x8_inst (
        .RADDR({5'h0, mar}),
        .RCLK(~clk),
        .RCLKE(1'b1),
        .RDATA(ram_out),
        .RE(1'b1),
        .WDATA(bus),
        .WADDR({5'h0, mar}),
        .WCLK(clk),
        .WCLKE(1'b1),
        .WE(RI)
    );

    tri_state_buffer output_buf [7 : 0] (
        .in(ram_out),
        .out(bus),
        .enable(RO)
    );

    defparam ram512x8_inst.INIT_0 = 256'h000000000000000000000000000000000100010000000000604F1E4D2F4EE01D;

endmodule