data/full_repos/permissive/143278/ivltests/pr3306516.v
 line:37: before: "ta"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3306516.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (y !== 1\'bx && y !== 1\'bz) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3306516.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (y !== 1\'b0) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3306516.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (y !== 1\'b0) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3306516.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (y !== 1\'b1) begin\n    ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg passed;
  reg a, b;
  wire y;

  initial begin
    passed = 1'b1;
    a = 0;
    b = 1;
    #2 if (y !== 1'bx && y !== 1'bz) begin
      $display("Failed: Initial value, expected 1'bx, got %b", y);
      passed = 1'b0;
    end
    #2 if (y !== 1'b0) begin
      $display("Failed: Initial value propagation, expected 1'b0, got %b", y);
      passed = 1'b0;
    end
    a = 1;
    #2 if (y !== 1'b0) begin
      $display("Failed: to hold initial value, expected 1'b0, got %b", y);
      passed = 1'b0;
    end
    #2 if (y !== 1'b1) begin
      $display("Failed: Final value propagation, expected 1'b1, got %b", y);
      passed = 1'b0;
    end

    if (passed) $display("PASSED");
  end

  my_and dut(y, a, b);
endmodule
module top;

  reg passed;
  reg a, b;
  wire y;

  initial begin
    passed = 1'b1;
    a = 0;
    b = 1;
    #2 if (y !== 1'bx && y !== 1'bz) begin
      $display("Failed: Initial value, expected 1'bx, got %b", y);
      passed = 1'b0;
    end
    #2 if (y !== 1'b0) begin
      $display("Failed: Initial value propagation, expected 1'b0, got %b", y);
      passed = 1'b0;
    end
    a = 1;
    #2 if (y !== 1'b0) begin
      $display("Failed: to hold initial value, expected 1'b0, got %b", y);
      passed = 1'b0;
    end
    #2 if (y !== 1'b1) begin
      $display("Failed: Final value propagation, expected 1'b1, got %b", y);
      passed = 1'b0;
    end

    if (passed) $display("PASSED");
  end

  my_and dut(y, a, b);
endmodule