data/full_repos/permissive/143278/ivltests/pr1022.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1022.v:8: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (fred[0] !== 1) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/143278/ivltests/pr1022.v:4: Little bit endian vector: MSB < LSB of bit range: -1:0\n   wire [-1:0] fred;\n        ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module foo;
   wire [-1:0] fred;
   assign      fred = 1;

   initial begin
      #1 if (fred[0] !== 1) begin
	 $display("FAILED -- fred[0] = %b", fred[0]);
	 $finish;
      end

      if (fred[-1] !== 0) begin
	 $display("FAILED -- fred[-1] = %b", fred[-1]);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module foo;

   wire [-1:0] fred;
   assign      fred = 1;

   initial begin
      #1 if (fred[0] !== 1) begin
	 $display("FAILED -- fred[0] = %b", fred[0]);
	 $finish;
      end

      if (fred[-1] !== 0) begin
	 $display("FAILED -- fred[-1] = %b", fred[-1]);
	 $finish;
      end

      $display("PASSED");
   end

endmodule