data/full_repos/permissive/161033574/rawlcd.v
1: b'%Error: data/full_repos/permissive/161033574/rawlcd.v:11: Cannot find include file: lcd_params.vh\n`include "lcd_params.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161033574,data/full_repos/permissive/161033574/lcd_params.vh\n             data/full_repos/permissive/161033574,data/full_repos/permissive/161033574/lcd_params.vh.v\n             data/full_repos/permissive/161033574,data/full_repos/permissive/161033574/lcd_params.vh.sv\n             lcd_params.vh\n             lcd_params.vh.v\n             lcd_params.vh.sv\n             obj_dir/lcd_params.vh\n             obj_dir/lcd_params.vh.v\n             obj_dir/lcd_params.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module lcd(input        clk,
           input        rst_n,
           output       fb_clk,
           input [7:0]  fb_data,
           input [31:0] fb_addr,
           output [3:0] data,
           output       flm,
           output       lp,
           output       dclk,
           output       m);
`include "lcd_params.vh"

   reg [3:0]            data;
   reg                  flm;
   reg                  lp;
   reg                  dclk;
   reg                  m;

   reg [7:0]            state;
   reg [15:0]           row;
   reg [15:0]           coloff;
   reg                  tmp;

   wire [7:0]           fb_bitswap;
   wire [7:0]           fb_data;
   wire [31:0]          fb_addr;

   genvar               i;

   generate
      for (i = 0; i < 8; i = i + 1)
        begin
           assign fb_bitswap[i] = fb_data[7 - i];
        end
   endgenerate

   assign fb_clk = clk;
   assign fb_addr = row * (res_x / 8) + coloff[15:1];

   always @ (negedge clk, negedge rst_n)
     begin
        if (!rst_n)
          begin
             data <= 0;
             flm <= 0;
             lp <= 0;
             dclk <= 0;
             m <= 0;
             state <= 0;
             row <= 0;
             coloff <= 0;
             tmp <= 0;
          end
        else
          begin
             case(state)
               8'h00:
                 begin
                    if (row == 0)
                      begin
                         flm <= 1;
                         m <= ~m;
                      end
                    else
                      begin
                         flm <= 0;
                      end

                    lp <= 1;
                    state <= state + 1;
                 end
               8'h01:
                 begin
                    lp <= 0;
                    if (coloff >= 8'd80)
                      begin
                         coloff <= 0;
                         state <= state + 1;
                         dclk <= 0;
                      end
                    else
                      begin
                         tmp <= ~tmp;
                         if (!tmp)
                           begin
                              data <= coloff[0] ? fb_bitswap[3:0] : fb_bitswap[7:4];
                              dclk <= 1;
                           end
                         else
                           begin
                              dclk <= 0;
                              coloff <= coloff + 1;
                           end
                      end
                 end
               8'h02:
                 begin
                    if (row >= res_y - 1)
                      begin
                         row <= 0;
                      end
                    else
                      begin
                         row <= row + 1;
                      end
                    state <= 0;
                 end
             endcase
          end
     end
endmodule
module lcd(input        clk,
           input        rst_n,
           output       fb_clk,
           input [7:0]  fb_data,
           input [31:0] fb_addr,
           output [3:0] data,
           output       flm,
           output       lp,
           output       dclk,
           output       m);

`include "lcd_params.vh"

   reg [3:0]            data;
   reg                  flm;
   reg                  lp;
   reg                  dclk;
   reg                  m;

   reg [7:0]            state;
   reg [15:0]           row;
   reg [15:0]           coloff;
   reg                  tmp;

   wire [7:0]           fb_bitswap;
   wire [7:0]           fb_data;
   wire [31:0]          fb_addr;

   genvar               i;

   generate
      for (i = 0; i < 8; i = i + 1)
        begin
           assign fb_bitswap[i] = fb_data[7 - i];
        end
   endgenerate

   assign fb_clk = clk;
   assign fb_addr = row * (res_x / 8) + coloff[15:1];

   always @ (negedge clk, negedge rst_n)
     begin
        if (!rst_n)
          begin
             data <= 0;
             flm <= 0;
             lp <= 0;
             dclk <= 0;
             m <= 0;
             state <= 0;
             row <= 0;
             coloff <= 0;
             tmp <= 0;
          end
        else
          begin
             case(state)
               8'h00:
                 begin
                    if (row == 0)
                      begin
                         flm <= 1;
                         m <= ~m;
                      end
                    else
                      begin
                         flm <= 0;
                      end

                    lp <= 1;
                    state <= state + 1;
                 end
               8'h01:
                 begin
                    lp <= 0;
                    if (coloff >= 8'd80)
                      begin
                         coloff <= 0;
                         state <= state + 1;
                         dclk <= 0;
                      end
                    else
                      begin
                         tmp <= ~tmp;
                         if (!tmp)
                           begin
                              data <= coloff[0] ? fb_bitswap[3:0] : fb_bitswap[7:4];
                              dclk <= 1;
                           end
                         else
                           begin
                              dclk <= 0;
                              coloff <= coloff + 1;
                           end
                      end
                 end
               8'h02:
                 begin
                    if (row >= res_y - 1)
                      begin
                         row <= 0;
                      end
                    else
                      begin
                         row <= row + 1;
                      end
                    state <= 0;
                 end
             endcase
          end
     end
endmodule