data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/spi_debug_ifc.v
 line:145: before: ","
data/verilator_xmls/e014abe6-5406-487e-be6b-fbf6d7365077.xml
module sync_oneway(
	input txclk,
	input txdat,
	input rxclk,
	output rxdat
	);

reg a = 0;


reg b = 0, c = 0;

always @(posedge txclk)
	a <= txdat;

always @(posedge rxclk) begin
	b <= a;
	c <= b;
end

assign rxdat = c;

endmodule
module sync_oneway(
	input txclk,
	input txdat,
	input rxclk,
	output rxdat
	);


reg a = 0;


reg b = 0, c = 0;

always @(posedge txclk)
	a <= txdat;

always @(posedge rxclk) begin
	b <= a;
	c <= b;
end

assign rxdat = c;

endmodule