data/full_repos/permissive/103842408/bin/fsm-template.v
None: at end of input
1: b'%Error: data/full_repos/permissive/103842408/bin/fsm-template.v:11: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/103842408/bin,data/full_repos/permissive/103842408/rvm_constants.v\n             data/full_repos/permissive/103842408/bin,data/full_repos/permissive/103842408/rvm_constants.v.v\n             data/full_repos/permissive/103842408/bin,data/full_repos/permissive/103842408/rvm_constants.v.sv\n             rvm_constants.v\n             rvm_constants.v.v\n             rvm_constants.v.sv\n             obj_dir/rvm_constants.v\n             obj_dir/rvm_constants.v.v\n             obj_dir/rvm_constants.v.sv\n%Error: data/full_repos/permissive/103842408/bin/fsm-template.v:16: syntax error, unexpected \'{\', expecting \'[\'\n{% for interface_name in interfaces|sort %}\n^\n%Error: data/full_repos/permissive/103842408/bin/fsm-template.v:39: syntax error, unexpected \'{\', expecting IDENTIFIER or \'=\' or do or final\nreg [{{state_var_w}}:0] {{state_var}};\n                        ^\n%Error: data/full_repos/permissive/103842408/bin/fsm-template.v:40: syntax error, unexpected \'{\', expecting \',\' or \';\'\nreg [{{state_var_w}}:0] n_{{state_var}};\n                          ^\n%Error: Exiting due to 4 error(s)\n'
module rvm_control(
input  wire         clk        ,
input  wire         resetn     ,
{% for interface_name in interfaces|sort %}
{% set interface = interfaces[interface_name]  %}

    {% for signal_name  in interface.signals|sort -%}
    {% set signal = interface.signals[signal_name] -%}
{{signal.direction()}} [{{signal.get_range()}}] {{signal.verilog_name()}}
    {%- if not loop.last -%},{% endif %}
    {% endfor -%}
{%- if not loop.last -%},{%- endif -%}
{% endfor %}

);





{% for state in states|sort %}
localparam {{states[state].verilog_name()}} = {{states[state].get_encoding()}};
{%- endfor %}



reg [{{state_var_w}}:0] {{state_var}};
reg [{{state_var_w}}:0] n_{{state_var}};



{% for interface_name in interfaces|sort %}
{%- set interface = interfaces[interface_name]  %}





    {% for signal_name in interface.signals|sort -%}
    {%- set signal = interface.signals[signal_name] -%}
    {%- if signal.writable %}

assign {{signal_name}} =  
    {%- if signal.values|length == 0 -%} 0; {%-endif-%}
    {% for assignment in signal.values|sort(attribute="value") -%}
        ({ {{signal|length}} { {{state_var-}} 
            == 
        {{-assignment.state.verilog_name()-}} } } & {{assignment.value}})
        {%- if(loop.last) -%}
            ;
        {%- else %} |
        {%- endif %}
    {% endfor %}
    {%- endif -%}
    
    {%- endfor -%}
{% endfor %}









always @(*) begin : p_ctrl_next_state
case ({{state_var}})

{%- for state_name in states|sort %}
{% set state = states[state_name] %}
    {{state.verilog_name()}}: begin
        {% if state.single_next_state -%}
            n_{{state_var}} = {{state.next_state.verilog_name()}};

        {%- else -%}
            n_{{state_var}} = {{default_next_state}};
            {% for ass in state.next_state|sort(attribute="value") %}
            if ({{ass.condition}}) n_{{state_var}} = {{ass.value}};
            {% endfor -%}
        {%- endif %}
    end
{%- endfor %}

    default:
        n_{{state_var}} = {{default_next_state}};

endcase end







always @(posedge clk, negedge resetn) begin : p_ctrl_progress_state
    if(!resetn) begin
        {{state_var}} <= {{default_next_state}};
    end else begin
        {{state_var}} <= n_{{state_var}};
    end
end

endmodule
module rvm_control(
input  wire         clk        ,
input  wire         resetn     ,
{% for interface_name in interfaces|sort %}
{% set interface = interfaces[interface_name]  %}

    {% for signal_name  in interface.signals|sort -%}
    {% set signal = interface.signals[signal_name] -%}
{{signal.direction()}} [{{signal.get_range()}}] {{signal.verilog_name()}}
    {%- if not loop.last -%},{% endif %}
    {% endfor -%}
{%- if not loop.last -%},{%- endif -%}
{% endfor %}

);






{% for state in states|sort %}
localparam {{states[state].verilog_name()}} = {{states[state].get_encoding()}};
{%- endfor %}



reg [{{state_var_w}}:0] {{state_var}};
reg [{{state_var_w}}:0] n_{{state_var}};



{% for interface_name in interfaces|sort %}
{%- set interface = interfaces[interface_name]  %}





    {% for signal_name in interface.signals|sort -%}
    {%- set signal = interface.signals[signal_name] -%}
    {%- if signal.writable %}

assign {{signal_name}} =  
    {%- if signal.values|length == 0 -%} 0; {%-endif-%}
    {% for assignment in signal.values|sort(attribute="value") -%}
        ({ {{signal|length}} { {{state_var-}} 
            == 
        {{-assignment.state.verilog_name()-}} } } & {{assignment.value}})
        {%- if(loop.last) -%}
            ;
        {%- else %} |
        {%- endif %}
    {% endfor %}
    {%- endif -%}
    
    {%- endfor -%}
{% endfor %}









always @(*) begin : p_ctrl_next_state
case ({{state_var}})

{%- for state_name in states|sort %}
{% set state = states[state_name] %}
    {{state.verilog_name()}}: begin
        {% if state.single_next_state -%}
            n_{{state_var}} = {{state.next_state.verilog_name()}};

        {%- else -%}
            n_{{state_var}} = {{default_next_state}};
            {% for ass in state.next_state|sort(attribute="value") %}
            if ({{ass.condition}}) n_{{state_var}} = {{ass.value}};
            {% endfor -%}
        {%- endif %}
    end
{%- endfor %}

    default:
        n_{{state_var}} = {{default_next_state}};

endcase end







always @(posedge clk, negedge resetn) begin : p_ctrl_progress_state
    if(!resetn) begin
        {{state_var}} <= {{default_next_state}};
    end else begin
        {{state_var}} <= n_{{state_var}};
    end
end

endmodule