data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v
'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte
1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n             const_defination.v\n             const_defination.v.v\n             const_defination.v.sv\n             obj_dir/const_defination.v\n             obj_dir/const_defination.v.v\n             obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:25: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] d_rvalA,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`digitsBus] d_rvalA,\n                         ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:26: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] d_rvalB,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:27: Define or directive not defined: \'`icodeBus\'\n    input wire[`icodeBus] icode,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:28: Define or directive not defined: \'`regBus\'\n    input wire[`regBus] e_dstE,M_dstE,M_dstM,W_dstM,W_dstE,    \n               ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:29: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] e_valE,m_valM,M_valE,W_valM,W_valE,  \n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:30: Define or directive not defined: \'`regBus\'\n    input wire[`regBus] srcA,srcB,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:31: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] valP,  \n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:32: Define or directive not defined: \'`digitsBus\'\n    output reg[`digitsBus] valA,valB\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:39: Define or directive not defined: \'`call\'\n            `call:\n            ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/decode.v:43: Define or directive not defined: \'`jmp\'\n   `jmp:\n   ^~~~\n%Error: Exiting due to 12 error(s)\n'
module decode(
    input wire[`digitsBus] d_rvalA,
    input wire[`digitsBus] d_rvalB,
    input wire[`icodeBus] icode,
    input wire[`regBus] e_dstE,M_dstE,M_dstM,W_dstM,W_dstE,
    input wire[`digitsBus] e_valE,m_valM,M_valE,W_valM,W_valE,
    input wire[`regBus] srcA,srcB,
    input wire[`digitsBus] valP,
    output reg[`digitsBus] valA,valB
    );
    

    always@(*)
    begin
        case({icode,4'h0})
            `call:
                begin
                    valA=valP;
                end
			`jmp:
                begin
                    valA=valP;
                end
			default:
			begin
				if(srcA==e_dstE)
				begin
					valA=e_valE;
				end
				else if(srcA==M_dstM)
				begin
					valA=m_valM;
				end
				else if(srcA==M_dstE)
				begin
					valA=M_valE;
				end
				else if(srcA==W_dstM)
				begin
					valA=W_valM;
				end
				else if(srcA==W_dstE)
				begin
					valA=W_valE;
				end
				else
				begin
					valA=d_rvalA;
				end
			end
        endcase
    end
    

    always@(*)
        begin
            if(srcB==e_dstE)
            begin
                valB=e_valE;
            end
            else if(srcB==M_dstM)
            begin
                valB=m_valM;
            end
            else if(srcB==M_dstE)
            begin
                valB=M_valE;
            end
            else if(srcB==W_dstM)
            begin
                valB=W_valM;
            end
            else if(srcB==W_dstE)
            begin
                valB=W_valE;
            end
            else
            begin
                valB=d_rvalB;
            end
        end
    
endmodule
module decode(
    input wire[`digitsBus] d_rvalA,
    input wire[`digitsBus] d_rvalB,
    input wire[`icodeBus] icode,
    input wire[`regBus] e_dstE,M_dstE,M_dstM,W_dstM,W_dstE,
    input wire[`digitsBus] e_valE,m_valM,M_valE,W_valM,W_valE,
    input wire[`regBus] srcA,srcB,
    input wire[`digitsBus] valP,
    output reg[`digitsBus] valA,valB
    );

    

    always@(*)
    begin
        case({icode,4'h0})
            `call:
                begin
                    valA=valP;
                end
			`jmp:
                begin
                    valA=valP;
                end
			default:
			begin
				if(srcA==e_dstE)
				begin
					valA=e_valE;
				end
				else if(srcA==M_dstM)
				begin
					valA=m_valM;
				end
				else if(srcA==M_dstE)
				begin
					valA=M_valE;
				end
				else if(srcA==W_dstM)
				begin
					valA=W_valM;
				end
				else if(srcA==W_dstE)
				begin
					valA=W_valE;
				end
				else
				begin
					valA=d_rvalA;
				end
			end
        endcase
    end
    

    always@(*)
        begin
            if(srcB==e_dstE)
            begin
                valB=e_valE;
            end
            else if(srcB==M_dstM)
            begin
                valB=m_valM;
            end
            else if(srcB==M_dstE)
            begin
                valB=M_valE;
            end
            else if(srcB==W_dstM)
            begin
                valB=W_valM;
            end
            else if(srcB==W_dstE)
            begin
                valB=W_valE;
            end
            else
            begin
                valB=d_rvalB;
            end
        end
    
endmodule