data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:52: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:54: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:114: Define or directive not defined: \'`OR1200_DCTAG_W\'\n   input [`OR1200_DCTAG_W-2:0]   tag;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:128: Define or directive not defined: \'`OR1200_DCLS\'\n   reg [`OR1200_DCLS-1:0]   cnt;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:153: Define or directive not defined: \'`OR1200_DCLS\'\n   wire [(`OR1200_DCLS-1)-2:0]  next_addr_word;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:273: Define or directive not defined: \'`OR1200_DCLS\'\n   assign next_addr_word =  addr_r[`OR1200_DCLS-1:2] + 1;\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:289: Define or directive not defined: \'`OR1200_DCLS\'\n      {addr_r[31:`OR1200_DCLS], next_addr_word, 2\'b00} : addr_r;\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:289: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      {addr_r[31:`OR1200_DCLS], next_addr_word, 2\'b00} : addr_r;\n                             ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:347: Define or directive not defined: \'`OR1200_DCLS\'\n       (cnt==((1 << `OR1200_DCLS) - 4)) & biudata_valid & \n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:347: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n       (cnt==((1 << `OR1200_DCLS) - 4)) & biudata_valid & \n                                ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:364: Define or directive not defined: \'`OR1200_RST_EVENT\'\n   always @(posedge clk or `OR1200_RST_EVENT rst) begin\n                           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:365: Define or directive not defined: \'`OR1200_RST_VALUE\'\n      if (rst == `OR1200_RST_VALUE) begin\n                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:365: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (rst == `OR1200_RST_VALUE) begin\n                                  ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:371: Define or directive not defined: \'`OR1200_DCLS\'\n  cnt <=  `OR1200_DCLS\'d0;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:379: syntax error, unexpected else\n      else\n      ^~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:405: syntax error, unexpected <=, expecting IDENTIFIER\n                cache_inhibit <=  dcqmem_ci_i;  \n                              ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:420: syntax error, unexpected <=, expecting IDENTIFIER\n       addr_r <=  {tag, lsu_addr[`OR1200_DCINDXH:2],2\'d0};\n              ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:420: Define or directive not defined: \'`OR1200_DCINDXH\'\n       addr_r <=  {tag, lsu_addr[`OR1200_DCINDXH:2],2\'d0};\n                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:429: syntax error, unexpected <=, expecting IDENTIFIER\n       addr_r <=  lsu_addr;\n              ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:433: syntax error, unexpected <=, expecting IDENTIFIER\n    state <= 3\'d2;    \n          ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:435: Define or directive not defined: \'`OR1200_DCLS\'\n    cnt <=  ((1 << `OR1200_DCLS) - 4);\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:445: syntax error, unexpected <=, expecting IDENTIFIER\n                state <=  3\'d0;\n                      ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:458: Define or directive not defined: \'`OR1200_DCLS\'\n  cnt <= `OR1200_DCLS\'d0;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:462: Define or directive not defined: \'`OR1200_DCLS\'\n                addr_r[`OR1200_DCLS-1:2] <=  addr_r[`OR1200_DCLS-1:2] + 1;\n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:462: Define or directive not defined: \'`OR1200_DCLS\'\n                addr_r[`OR1200_DCLS-1:2] <=  addr_r[`OR1200_DCLS-1:2] + 1;\n                                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:483: Define or directive not defined: \'`OR1200_DCLS\'\n  cnt <=  ((1 << `OR1200_DCLS) - 4);\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:511: syntax error, unexpected <=, expecting IDENTIFIER\n    cache_spr_block_flush <= 1\'b0;\n                          ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:523: syntax error, unexpected <=, expecting IDENTIFIER\n       addr_r <=  {tag, addr_r[`OR1200_DCINDXH:2],2\'d0};\n              ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:523: Define or directive not defined: \'`OR1200_DCINDXH\'\n       addr_r <=  {tag, addr_r[`OR1200_DCINDXH:2],2\'d0};\n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:531: Define or directive not defined: \'`OR1200_DCLS\'\n       cnt <=  ((1 << `OR1200_DCLS) - 4);\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:536: syntax error, unexpected <=, expecting IDENTIFIER\n         state <=  3\'d6;\n               ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:541: syntax error, unexpected <=, expecting IDENTIFIER\n         cache_spr_block_writeback <= 1\'b0;\n                                   ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:545: syntax error, unexpected end\n   end\n   ^~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_dc_fsm.v:550: syntax error, unexpected <=, expecting IDENTIFIER\n        state <=  3\'d0;\n              ^~\n%Error: Cannot continue\n'
module or1200_dc_fsm
  (

   clk, rst,
   

   dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
   tagcomp_miss, biudata_valid, biudata_error, lsu_addr,
   dcram_we, biu_read, biu_write, biu_do_sel, dcram_di_sel, first_hit_ack, 
   first_miss_ack, first_miss_err, burst, tag_we, tag_valid, dc_addr, 
   dc_no_writethrough, tag_dirty, dirty, tag, tag_v, dc_block_flush, 
   dc_block_writeback, spr_dat_i, mtspr_dc_done, spr_cswe
   );




   input				clk;
   input				rst;
   input				dc_en;
   input				dcqmem_cycstb_i;
   input				dcqmem_ci_i;
   input				dcqmem_we_i;
   input [3:0] 				dcqmem_sel_i;
   input				tagcomp_miss;
   input				biudata_valid;
   input				biudata_error;
   input [31:0] 			lsu_addr;
   output [3:0] 			dcram_we;
   output				biu_read;
   output				biu_write;
   output 				dcram_di_sel;
   output 				biu_do_sel;
   output				first_hit_ack;
   output				first_miss_ack;
   output				first_miss_err;
   output				burst;
   output				tag_we;
   output 				tag_valid;
   output [31:0] 			dc_addr;
   input 				dc_no_writethrough;
   output 				tag_dirty;
   input 				dirty;
   input [`OR1200_DCTAG_W-2:0] 		tag;
   input 				tag_v;   
   input 				dc_block_flush;
   input 				dc_block_writeback;
   input [31:0] 			spr_dat_i;
   output 				mtspr_dc_done;
   input 				spr_cswe;
   
   



   reg [31:0] 				addr_r;
   reg [2:0] 				state;
   reg [`OR1200_DCLS-1:0] 		cnt;
   reg 					hitmiss_eval;
   reg 					store;
   reg 					load;
   reg 					cache_inhibit;
   reg 					cache_miss;
   reg 					cache_dirty_needs_writeback;
   reg                                  did_early_load_ack;
   reg 					cache_spr_block_flush;
   reg 					cache_spr_block_writeback;
   reg 					cache_wb;   
   wire 				load_hit_ack;
   wire 				load_miss_ack;
   wire 				load_inhibit_ack;   
   wire 				store_hit_ack;
   wire 				store_hit_writethrough_ack;   
   wire 				store_miss_writethrough_ack;   
   wire 				store_inhibit_ack;
   wire 				store_miss_ack;
   wire 				dcram_we_after_line_load;
   wire 				dcram_we_during_line_load;
   wire 				tagram_we_end_of_loadstore_loop;
   wire 				tagram_dirty_bit_set;   
   wire 				writethrough;
   wire 				cache_inhibit_with_eval;
   wire [(`OR1200_DCLS-1)-2:0]		next_addr_word;




   

   assign cache_inhibit_with_eval = (hitmiss_eval & dcqmem_ci_i) |
				    (!hitmiss_eval & cache_inhibit);
   





   assign dcram_we_after_line_load = (state == `OR1200_DCFSM_LOOP3) &
				    dcqmem_we_i & !cache_dirty_needs_writeback &
				     !did_early_load_ack;


   assign dcram_we_during_line_load = (state == `OR1200_DCFSM_LOOP2) & load & 
				      biudata_valid;   
   
   assign dcram_we =(


		     ({4{store_hit_ack | store_hit_writethrough_ack}} |

		     {4{dcram_we_after_line_load}}) & 
		     dcqmem_sel_i		 ) |

		    {4{dcram_we_during_line_load}};




   

   assign tagram_we_end_of_loadstore_loop = ((state==`OR1200_DCFSM_LOOP2) & 
					     biudata_valid & !(|cnt));
   
`ifndef OR1200_DC_WRITETHROUGH

   assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;


   assign mtspr_dc_done =
			  !dc_en | !spr_cswe |

			  ((state==`OR1200_DCFSM_FLUSH5) & 
			   (!tag_v | (cache_spr_block_writeback & !dirty))) |

			  ((state==`OR1200_DCFSM_LOOP3) & 
			   (cache_spr_block_flush | cache_spr_block_writeback))|

			  ((state==`OR1200_DCFSM_INV6) & cache_spr_block_flush);
   
   
`else
 `ifdef OR1200_DC_NOSTACKWRITETHROUGH   

   assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
 `else

   assign tagram_dirty_bit_set = 0;
 `endif
   
   assign mtspr_dc_done = 1'b1;
   
`endif

   assign tag_dirty = tagram_dirty_bit_set;
   

   assign tag_we = tagram_we_end_of_loadstore_loop |		    
                    tagram_dirty_bit_set | (state == `OR1200_DCFSM_INV6);
   



   assign tag_valid = ( tagram_we_end_of_loadstore_loop & 
			(load | (store & cache_spr_block_writeback)) ) |
		      tagram_dirty_bit_set;


   




   assign biu_read =

		     ((state == `OR1200_DCFSM_CLOADSTORE) &
		      (((hitmiss_eval & tagcomp_miss & !dirty & 
			 !(store & writethrough)) | 
			(load & cache_inhibit_with_eval)) & dcqmem_cycstb_i)) |

		     ((state == `OR1200_DCFSM_LOOP2) & load);
   

   assign biu_write =

		      ((state == `OR1200_DCFSM_CLOADSTORE) & 
		       (((hitmiss_eval & tagcomp_miss & dirty) | 
			 (store & writethrough)) | 
			(store & cache_inhibit_with_eval)) & dcqmem_cycstb_i) |

		      ((state == `OR1200_DCFSM_LOOP2) & store);
   




   assign dcram_di_sel = load;


   assign biu_do_sel = (state == `OR1200_DCFSM_LOOP2) & store;



   assign next_addr_word =  addr_r[`OR1200_DCLS-1:2] + 1;
   

   assign dc_addr =

		   ((dc_block_flush & !cache_spr_block_flush) | 
		   (dc_block_writeback & !cache_spr_block_writeback)) ? 
		   spr_dat_i :
		   (state==`OR1200_DCFSM_FLUSH5) ? addr_r:

		    (state==`OR1200_DCFSM_IDLE | hitmiss_eval) ? lsu_addr :




		    (state==`OR1200_DCFSM_LOOP2 & biudata_valid & store ) ? 
		    {addr_r[31:`OR1200_DCLS], next_addr_word, 2'b00} : addr_r;
   
`ifdef OR1200_DC_WRITETHROUGH
 `ifdef OR1200_DC_NOSTACKWRITETHROUGH   
   assign writethrough = !dc_no_writethrough;
 `else
   assign writethrough = 1;
 `endif
`else
   assign writethrough = 0;
`endif
   



   

   assign first_hit_ack = load_hit_ack | store_hit_ack | 
			  store_hit_writethrough_ack | 
			  store_miss_writethrough_ack |
			  store_inhibit_ack | store_miss_ack ;






   assign first_miss_ack = ~first_hit_ack & (load_miss_ack | load_inhibit_ack);
   

   assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) & 
			 hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i & load;
   

   assign store_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) & 
			  hitmiss_eval  & !tagcomp_miss & !dcqmem_ci_i &
			  store & !writethrough;
   

   assign store_hit_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) & 
				       !cache_miss & !cache_inhibit &
				       store & writethrough & biudata_valid;
   

   assign store_miss_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) & 
					cache_miss & !cache_inhibit &
					store & writethrough & biudata_valid;
      

   assign store_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
			      store & cache_inhibit & biudata_valid;
   
   




   assign load_miss_ack =  ((state== `OR1200_DCFSM_LOOP2) & load &
			    (cnt==((1 << `OR1200_DCLS) - 4)) & biudata_valid & 
			    !(dcqmem_we_i & !writethrough));
   
   assign load_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
			     load & cache_inhibit & biudata_valid;   
   

   assign store_miss_ack = dcram_we_after_line_load;
            
   assign first_miss_err = biudata_error & dcqmem_cycstb_i;


   assign burst = (state == `OR1200_DCFSM_LOOP2);




   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if (rst == `OR1200_RST_VALUE) begin
	 state <=  `OR1200_DCFSM_IDLE;
	 addr_r <=  32'd0;
	 hitmiss_eval <=  1'b0;
	 store <=  1'b0;
	 load <=  1'b0;
	 cnt <=  `OR1200_DCLS'd0;
         cache_miss <=  1'b0;
	 cache_dirty_needs_writeback <= 1'b0;
	 cache_inhibit <=  1'b0;
	 did_early_load_ack <= 1'b0;
	 cache_spr_block_flush <= 1'b0;
	 cache_spr_block_writeback <= 1'b0;
      end
      else
	case (state)
	  
          `OR1200_DCFSM_IDLE : begin
	     if (dc_en & (dc_block_flush | dc_block_writeback))
	       begin
		  cache_spr_block_flush <= dc_block_flush;
		  cache_spr_block_writeback <= dc_block_writeback;
		  hitmiss_eval <= 1'b1;
		  state <= `OR1200_DCFSM_FLUSH5;
		  addr_r <=  spr_dat_i;
	       end
	     else if (dc_en & dcqmem_cycstb_i)
	       begin
		  state <= `OR1200_DCFSM_CLOADSTORE;
		  hitmiss_eval <=  1'b1;
		  store <=  dcqmem_we_i;
		  load <=  !dcqmem_we_i;
	       end
	     
	     
          end
	  
          `OR1200_DCFSM_CLOADSTORE: begin
	     hitmiss_eval <=  1'b0;
	     if (hitmiss_eval) begin
                cache_inhibit <=  dcqmem_ci_i;
                cache_miss <=  tagcomp_miss;
		cache_dirty_needs_writeback <= dirty;
		addr_r <=  lsu_addr;
             end



	     if (hitmiss_eval & tagcomp_miss & !(store & writethrough) &
		 !dcqmem_ci_i)
	       begin


		  if (dirty) begin

		     addr_r <=  {tag, lsu_addr[`OR1200_DCINDXH:2],2'd0};
		     load <= 1'b0;
		     store <= 1'b1;
`ifdef OR1200_VERBOSE		     
		     $display("%t: dcache miss and dirty", $time);
`endif
		  end

		  else begin
		     addr_r <=  lsu_addr;
		     load <= 1'b1;
		     store <= 1'b0;
		  end
		  state <= `OR1200_DCFSM_LOOP2;		  

		  cnt <=  ((1 << `OR1200_DCLS) - 4);
	       end
             else if (
		      !dcqmem_cycstb_i |

		      (!hitmiss_eval & (biudata_valid | biudata_error)) |

		      (hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &

		      !(store & writethrough))) begin
                state <=  `OR1200_DCFSM_IDLE;
                load <=  1'b0;
		store <= 1'b0;
		cache_inhibit <= 1'b0;
		cache_dirty_needs_writeback <= 1'b0;
             end	     
          end
	  
          `OR1200_DCFSM_LOOP2 : begin
             if (!dc_en| biudata_error) begin
                state <=  `OR1200_DCFSM_IDLE;
                load <=  1'b0;
		store <= 1'b0;
		cnt <= `OR1200_DCLS'd0;
             end
             if (biudata_valid & (|cnt)) begin
                cnt <=  cnt - 4;
                addr_r[`OR1200_DCLS-1:2] <=  addr_r[`OR1200_DCLS-1:2] + 1;
             end
	     else if (biudata_valid & !(|cnt)) begin
		state <= `OR1200_DCFSM_LOOP3;
		addr_r <=  lsu_addr;
		load <= 1'b0;
		store <= 1'b0;
	     end


	     if (load_miss_ack)
	       did_early_load_ack <= 1'b1;
	     

          end
	  
	  `OR1200_DCFSM_LOOP3: begin
	     if (cache_dirty_needs_writeback) begin

		load <= 1'b1;

		cnt <=  ((1 << `OR1200_DCLS) - 4);

		addr_r <=  lsu_addr;
		cache_dirty_needs_writeback <= 1'b0;
		state <= `OR1200_DCFSM_LOOP2;
	     end
	     else if (cache_spr_block_flush | cache_spr_block_writeback) begin

		cache_spr_block_flush <= 1'b0;
		cache_spr_block_writeback <= 1'b0;
		state <= `OR1200_DCFSM_WAITSPRCS7;
	     end
	     else begin

		did_early_load_ack <= 1'b0;
		state <= `OR1200_DCFSM_LOOP4;
	     end
	  end

	  `OR1200_DCFSM_LOOP4: begin
	     state <=  `OR1200_DCFSM_IDLE;
	  end

	  `OR1200_DCFSM_FLUSH5: begin
	     hitmiss_eval <= 1'b0;
	     if (hitmiss_eval & !tag_v)
	       begin

		  cache_spr_block_flush <= 1'b0;
		  cache_spr_block_writeback <= 1'b0;
		  state <=  `OR1200_DCFSM_WAITSPRCS7;
	       end
	     else if (hitmiss_eval & tag_v)
	       begin

		  if ((cache_spr_block_flush | cache_spr_block_writeback) & 
		      dirty) begin



		     addr_r <=  {tag, addr_r[`OR1200_DCINDXH:2],2'd0};
		     load <= 1'b0;
		     store <= 1'b1;
`ifdef OR1200_VERBOSE		     
		     $display("%t: block flush: dirty block", $time);
`endif
		     state <= `OR1200_DCFSM_LOOP2;		  

		     cnt <=  ((1 << `OR1200_DCLS) - 4);
		  end
		  else if (cache_spr_block_flush & !dirty)
		    begin

		       state <=  `OR1200_DCFSM_INV6;
		    end
		  else if (cache_spr_block_writeback & !dirty)
		    begin

		       cache_spr_block_writeback <= 1'b0;
		       state <=  `OR1200_DCFSM_WAITSPRCS7;
		    end
	  end
	  end
	  `OR1200_DCFSM_INV6: begin
	     cache_spr_block_flush <= 1'b0;

	     if (!spr_cswe)
	       state <=  `OR1200_DCFSM_IDLE;
	  end
	  `OR1200_DCFSM_WAITSPRCS7: begin

	     if (!spr_cswe)
	       state <=  `OR1200_DCFSM_IDLE;
	  end

	endcase
      
   end
   

endmodule
module or1200_dc_fsm
  (

   clk, rst,
   

   dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
   tagcomp_miss, biudata_valid, biudata_error, lsu_addr,
   dcram_we, biu_read, biu_write, biu_do_sel, dcram_di_sel, first_hit_ack, 
   first_miss_ack, first_miss_err, burst, tag_we, tag_valid, dc_addr, 
   dc_no_writethrough, tag_dirty, dirty, tag, tag_v, dc_block_flush, 
   dc_block_writeback, spr_dat_i, mtspr_dc_done, spr_cswe
   );





   input				clk;
   input				rst;
   input				dc_en;
   input				dcqmem_cycstb_i;
   input				dcqmem_ci_i;
   input				dcqmem_we_i;
   input [3:0] 				dcqmem_sel_i;
   input				tagcomp_miss;
   input				biudata_valid;
   input				biudata_error;
   input [31:0] 			lsu_addr;
   output [3:0] 			dcram_we;
   output				biu_read;
   output				biu_write;
   output 				dcram_di_sel;
   output 				biu_do_sel;
   output				first_hit_ack;
   output				first_miss_ack;
   output				first_miss_err;
   output				burst;
   output				tag_we;
   output 				tag_valid;
   output [31:0] 			dc_addr;
   input 				dc_no_writethrough;
   output 				tag_dirty;
   input 				dirty;
   input [`OR1200_DCTAG_W-2:0] 		tag;
   input 				tag_v;   
   input 				dc_block_flush;
   input 				dc_block_writeback;
   input [31:0] 			spr_dat_i;
   output 				mtspr_dc_done;
   input 				spr_cswe;
   
   



   reg [31:0] 				addr_r;
   reg [2:0] 				state;
   reg [`OR1200_DCLS-1:0] 		cnt;
   reg 					hitmiss_eval;
   reg 					store;
   reg 					load;
   reg 					cache_inhibit;
   reg 					cache_miss;
   reg 					cache_dirty_needs_writeback;
   reg                                  did_early_load_ack;
   reg 					cache_spr_block_flush;
   reg 					cache_spr_block_writeback;
   reg 					cache_wb;   
   wire 				load_hit_ack;
   wire 				load_miss_ack;
   wire 				load_inhibit_ack;   
   wire 				store_hit_ack;
   wire 				store_hit_writethrough_ack;   
   wire 				store_miss_writethrough_ack;   
   wire 				store_inhibit_ack;
   wire 				store_miss_ack;
   wire 				dcram_we_after_line_load;
   wire 				dcram_we_during_line_load;
   wire 				tagram_we_end_of_loadstore_loop;
   wire 				tagram_dirty_bit_set;   
   wire 				writethrough;
   wire 				cache_inhibit_with_eval;
   wire [(`OR1200_DCLS-1)-2:0]		next_addr_word;




   

   assign cache_inhibit_with_eval = (hitmiss_eval & dcqmem_ci_i) |
				    (!hitmiss_eval & cache_inhibit);
   





   assign dcram_we_after_line_load = (state == `OR1200_DCFSM_LOOP3) &
				    dcqmem_we_i & !cache_dirty_needs_writeback &
				     !did_early_load_ack;


   assign dcram_we_during_line_load = (state == `OR1200_DCFSM_LOOP2) & load & 
				      biudata_valid;   
   
   assign dcram_we =(


		     ({4{store_hit_ack | store_hit_writethrough_ack}} |

		     {4{dcram_we_after_line_load}}) & 
		     dcqmem_sel_i		 ) |

		    {4{dcram_we_during_line_load}};




   

   assign tagram_we_end_of_loadstore_loop = ((state==`OR1200_DCFSM_LOOP2) & 
					     biudata_valid & !(|cnt));
   
`ifndef OR1200_DC_WRITETHROUGH

   assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;


   assign mtspr_dc_done =
			  !dc_en | !spr_cswe |

			  ((state==`OR1200_DCFSM_FLUSH5) & 
			   (!tag_v | (cache_spr_block_writeback & !dirty))) |

			  ((state==`OR1200_DCFSM_LOOP3) & 
			   (cache_spr_block_flush | cache_spr_block_writeback))|

			  ((state==`OR1200_DCFSM_INV6) & cache_spr_block_flush);
   
   
`else
 `ifdef OR1200_DC_NOSTACKWRITETHROUGH   

   assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
 `else

   assign tagram_dirty_bit_set = 0;
 `endif
   
   assign mtspr_dc_done = 1'b1;
   
`endif

   assign tag_dirty = tagram_dirty_bit_set;
   

   assign tag_we = tagram_we_end_of_loadstore_loop |		    
                    tagram_dirty_bit_set | (state == `OR1200_DCFSM_INV6);
   



   assign tag_valid = ( tagram_we_end_of_loadstore_loop & 
			(load | (store & cache_spr_block_writeback)) ) |
		      tagram_dirty_bit_set;


   




   assign biu_read =

		     ((state == `OR1200_DCFSM_CLOADSTORE) &
		      (((hitmiss_eval & tagcomp_miss & !dirty & 
			 !(store & writethrough)) | 
			(load & cache_inhibit_with_eval)) & dcqmem_cycstb_i)) |

		     ((state == `OR1200_DCFSM_LOOP2) & load);
   

   assign biu_write =

		      ((state == `OR1200_DCFSM_CLOADSTORE) & 
		       (((hitmiss_eval & tagcomp_miss & dirty) | 
			 (store & writethrough)) | 
			(store & cache_inhibit_with_eval)) & dcqmem_cycstb_i) |

		      ((state == `OR1200_DCFSM_LOOP2) & store);
   




   assign dcram_di_sel = load;


   assign biu_do_sel = (state == `OR1200_DCFSM_LOOP2) & store;



   assign next_addr_word =  addr_r[`OR1200_DCLS-1:2] + 1;
   

   assign dc_addr =

		   ((dc_block_flush & !cache_spr_block_flush) | 
		   (dc_block_writeback & !cache_spr_block_writeback)) ? 
		   spr_dat_i :
		   (state==`OR1200_DCFSM_FLUSH5) ? addr_r:

		    (state==`OR1200_DCFSM_IDLE | hitmiss_eval) ? lsu_addr :




		    (state==`OR1200_DCFSM_LOOP2 & biudata_valid & store ) ? 
		    {addr_r[31:`OR1200_DCLS], next_addr_word, 2'b00} : addr_r;
   
`ifdef OR1200_DC_WRITETHROUGH
 `ifdef OR1200_DC_NOSTACKWRITETHROUGH   
   assign writethrough = !dc_no_writethrough;
 `else
   assign writethrough = 1;
 `endif
`else
   assign writethrough = 0;
`endif
   



   

   assign first_hit_ack = load_hit_ack | store_hit_ack | 
			  store_hit_writethrough_ack | 
			  store_miss_writethrough_ack |
			  store_inhibit_ack | store_miss_ack ;






   assign first_miss_ack = ~first_hit_ack & (load_miss_ack | load_inhibit_ack);
   

   assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) & 
			 hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i & load;
   

   assign store_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) & 
			  hitmiss_eval  & !tagcomp_miss & !dcqmem_ci_i &
			  store & !writethrough;
   

   assign store_hit_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) & 
				       !cache_miss & !cache_inhibit &
				       store & writethrough & biudata_valid;
   

   assign store_miss_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) & 
					cache_miss & !cache_inhibit &
					store & writethrough & biudata_valid;
      

   assign store_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
			      store & cache_inhibit & biudata_valid;
   
   




   assign load_miss_ack =  ((state== `OR1200_DCFSM_LOOP2) & load &
			    (cnt==((1 << `OR1200_DCLS) - 4)) & biudata_valid & 
			    !(dcqmem_we_i & !writethrough));
   
   assign load_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
			     load & cache_inhibit & biudata_valid;   
   

   assign store_miss_ack = dcram_we_after_line_load;
            
   assign first_miss_err = biudata_error & dcqmem_cycstb_i;


   assign burst = (state == `OR1200_DCFSM_LOOP2);




   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if (rst == `OR1200_RST_VALUE) begin
	 state <=  `OR1200_DCFSM_IDLE;
	 addr_r <=  32'd0;
	 hitmiss_eval <=  1'b0;
	 store <=  1'b0;
	 load <=  1'b0;
	 cnt <=  `OR1200_DCLS'd0;
         cache_miss <=  1'b0;
	 cache_dirty_needs_writeback <= 1'b0;
	 cache_inhibit <=  1'b0;
	 did_early_load_ack <= 1'b0;
	 cache_spr_block_flush <= 1'b0;
	 cache_spr_block_writeback <= 1'b0;
      end
      else
	case (state)
	  
          `OR1200_DCFSM_IDLE : begin
	     if (dc_en & (dc_block_flush | dc_block_writeback))
	       begin
		  cache_spr_block_flush <= dc_block_flush;
		  cache_spr_block_writeback <= dc_block_writeback;
		  hitmiss_eval <= 1'b1;
		  state <= `OR1200_DCFSM_FLUSH5;
		  addr_r <=  spr_dat_i;
	       end
	     else if (dc_en & dcqmem_cycstb_i)
	       begin
		  state <= `OR1200_DCFSM_CLOADSTORE;
		  hitmiss_eval <=  1'b1;
		  store <=  dcqmem_we_i;
		  load <=  !dcqmem_we_i;
	       end
	     
	     
          end
	  
          `OR1200_DCFSM_CLOADSTORE: begin
	     hitmiss_eval <=  1'b0;
	     if (hitmiss_eval) begin
                cache_inhibit <=  dcqmem_ci_i;
                cache_miss <=  tagcomp_miss;
		cache_dirty_needs_writeback <= dirty;
		addr_r <=  lsu_addr;
             end



	     if (hitmiss_eval & tagcomp_miss & !(store & writethrough) &
		 !dcqmem_ci_i)
	       begin


		  if (dirty) begin

		     addr_r <=  {tag, lsu_addr[`OR1200_DCINDXH:2],2'd0};
		     load <= 1'b0;
		     store <= 1'b1;
`ifdef OR1200_VERBOSE		     
		     $display("%t: dcache miss and dirty", $time);
`endif
		  end

		  else begin
		     addr_r <=  lsu_addr;
		     load <= 1'b1;
		     store <= 1'b0;
		  end
		  state <= `OR1200_DCFSM_LOOP2;		  

		  cnt <=  ((1 << `OR1200_DCLS) - 4);
	       end
             else if (
		      !dcqmem_cycstb_i |

		      (!hitmiss_eval & (biudata_valid | biudata_error)) |

		      (hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &

		      !(store & writethrough))) begin
                state <=  `OR1200_DCFSM_IDLE;
                load <=  1'b0;
		store <= 1'b0;
		cache_inhibit <= 1'b0;
		cache_dirty_needs_writeback <= 1'b0;
             end	     
          end
	  
          `OR1200_DCFSM_LOOP2 : begin
             if (!dc_en| biudata_error) begin
                state <=  `OR1200_DCFSM_IDLE;
                load <=  1'b0;
		store <= 1'b0;
		cnt <= `OR1200_DCLS'd0;
             end
             if (biudata_valid & (|cnt)) begin
                cnt <=  cnt - 4;
                addr_r[`OR1200_DCLS-1:2] <=  addr_r[`OR1200_DCLS-1:2] + 1;
             end
	     else if (biudata_valid & !(|cnt)) begin
		state <= `OR1200_DCFSM_LOOP3;
		addr_r <=  lsu_addr;
		load <= 1'b0;
		store <= 1'b0;
	     end


	     if (load_miss_ack)
	       did_early_load_ack <= 1'b1;
	     

          end
	  
	  `OR1200_DCFSM_LOOP3: begin
	     if (cache_dirty_needs_writeback) begin

		load <= 1'b1;

		cnt <=  ((1 << `OR1200_DCLS) - 4);

		addr_r <=  lsu_addr;
		cache_dirty_needs_writeback <= 1'b0;
		state <= `OR1200_DCFSM_LOOP2;
	     end
	     else if (cache_spr_block_flush | cache_spr_block_writeback) begin

		cache_spr_block_flush <= 1'b0;
		cache_spr_block_writeback <= 1'b0;
		state <= `OR1200_DCFSM_WAITSPRCS7;
	     end
	     else begin

		did_early_load_ack <= 1'b0;
		state <= `OR1200_DCFSM_LOOP4;
	     end
	  end

	  `OR1200_DCFSM_LOOP4: begin
	     state <=  `OR1200_DCFSM_IDLE;
	  end

	  `OR1200_DCFSM_FLUSH5: begin
	     hitmiss_eval <= 1'b0;
	     if (hitmiss_eval & !tag_v)
	       begin

		  cache_spr_block_flush <= 1'b0;
		  cache_spr_block_writeback <= 1'b0;
		  state <=  `OR1200_DCFSM_WAITSPRCS7;
	       end
	     else if (hitmiss_eval & tag_v)
	       begin

		  if ((cache_spr_block_flush | cache_spr_block_writeback) & 
		      dirty) begin



		     addr_r <=  {tag, addr_r[`OR1200_DCINDXH:2],2'd0};
		     load <= 1'b0;
		     store <= 1'b1;
`ifdef OR1200_VERBOSE		     
		     $display("%t: block flush: dirty block", $time);
`endif
		     state <= `OR1200_DCFSM_LOOP2;		  

		     cnt <=  ((1 << `OR1200_DCLS) - 4);
		  end
		  else if (cache_spr_block_flush & !dirty)
		    begin

		       state <=  `OR1200_DCFSM_INV6;
		    end
		  else if (cache_spr_block_writeback & !dirty)
		    begin

		       cache_spr_block_writeback <= 1'b0;
		       state <=  `OR1200_DCFSM_WAITSPRCS7;
		    end
	  end
	  end
	  `OR1200_DCFSM_INV6: begin
	     cache_spr_block_flush <= 1'b0;

	     if (!spr_cswe)
	       state <=  `OR1200_DCFSM_IDLE;
	  end
	  `OR1200_DCFSM_WAITSPRCS7: begin

	     if (!spr_cswe)
	       state <=  `OR1200_DCFSM_IDLE;
	  end

	endcase
      
   end
   

endmodule