data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_ic.v
 line:45: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_ic.v:45: Unsupported: Ignoring delay on this delayed statement.\n    always #5 begin\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test_ic.v:55: syntax error, unexpected \'@\'\n                @(posedge clk)\n                ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_ic();
    reg clk, rst;

	reg set_enabled;
	reg next_enabled;
	reg [31:0] set_addr;
	wire [31:0] pc_addr;

	instruction_counter ic(
		.clk(clk), .rst(rst),
		.set_enabled(set_enabled), .next_enabled(next_enabled),
		.set_addr(set_addr), .pc_addr(pc_addr)
		);

    initial begin
		clk <= 0;
		rst <= 0;
		set_enabled <= 0;
		next_enabled <= 0;
		set_addr <= 0;
    end

    always #5 begin
        clk <= ~clk;
    end

    task wait_posedge_clk;
        input   n;
        integer n;

        begin
            for(n=n; n>0; n=n-1) begin
                @(posedge clk)
                    ;
            end
        end
    endtask

	initial begin
		wait_posedge_clk(1);
		rst <= 1;
		wait_posedge_clk(1);
		rst <= 0;
		wait_posedge_clk(1);
		next_enabled <= 1;
		wait_posedge_clk(4);
		next_enabled <= 0;
		wait_posedge_clk(4);
		set_enabled <= 1;
		set_addr <= 'hffff0080;
		wait_posedge_clk(1);
		set_enabled <= 0;
		wait_posedge_clk(1);
		next_enabled <= 1;
		wait_posedge_clk(16);

		$finish;
	end

endmodule
module test_ic();

    reg clk, rst;

	reg set_enabled;
	reg next_enabled;
	reg [31:0] set_addr;
	wire [31:0] pc_addr;

	instruction_counter ic(
		.clk(clk), .rst(rst),
		.set_enabled(set_enabled), .next_enabled(next_enabled),
		.set_addr(set_addr), .pc_addr(pc_addr)
		);

    initial begin
		clk <= 0;
		rst <= 0;
		set_enabled <= 0;
		next_enabled <= 0;
		set_addr <= 0;
    end

    always #5 begin
        clk <= ~clk;
    end

    task wait_posedge_clk;
        input   n;
        integer n;

        begin
            for(n=n; n>0; n=n-1) begin
                @(posedge clk)
                    ;
            end
        end
    endtask

	initial begin
		wait_posedge_clk(1);
		rst <= 1;
		wait_posedge_clk(1);
		rst <= 0;
		wait_posedge_clk(1);
		next_enabled <= 1;
		wait_posedge_clk(4);
		next_enabled <= 0;
		wait_posedge_clk(4);
		set_enabled <= 1;
		set_addr <= 'hffff0080;
		wait_posedge_clk(1);
		set_enabled <= 0;
		wait_posedge_clk(1);
		next_enabled <= 1;
		wait_posedge_clk(16);

		$finish;
	end

endmodule