data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Reciprocal/Recirpocal_multicycle.v
1: b'%Error: Cannot find file containing module: Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Reciprocal/Recirpocal_multicycle.v\n%Error: Exiting due to 3 error(s)\n'
module Reciprocal_NR_multicycle






		#(parameter 	
						WL = 24,
						LUT_bits = 10,
						LUT_addWidth = 6,
						dWL = 26,
						ITERATION = 1





		 ) 		

		(
			input CLK,
			input nRST,
			input CE,
			
			input [WL-1:0] din,

			output reg [WL-1:0] dout
		);


		reg  [LUT_bits-1 : 0]     LUT [2**LUT_addWidth-1 : 0];
		reg  [LUT_bits-1 : 0]	  ini;
		reg  [WL-1		 :  0]    ini2;
		wire [WL-1		 : 0]  	  iniValue;
		reg  [LUT_addWidth-1:0]   reg_cmp;
		wire [dWL-1 :0]   		  mul1_net;
		reg  [dWL-1 :0]   		  mul_1_r;
		wire [dWL*2-1:0]	  	  mul2_net;
		wire [WL-1:0]			  tmp_result_1;
		reg  [WL-1:0]			  tmp_result_2;
		reg  					  Sel;







integer pointer;

		always @ (posedge CLK) begin
			if(~nRST) begin
					Sel <= 1'b0;
					pointer <= 0;
			end
			else begin
				if (CE) begin
					tmp_result_2 <= tmp_result_1;
					if (pointer == ITERATION) begin
						dout <= tmp_result_1;
						pointer <= 0;
						Sel <= 1'b0;
					end else begin
						pointer <= pointer + 1;
						Sel <= 1'b1;
					end
				end
			end
		end

	always @ * begin
			if(~nRST) begin
					reg_cmp <= 0;
					ini <= 0;
					ini2 <= 0;
					mul_1_r <= 0;		
			end else begin
				if (CE) begin
					reg_cmp  <= din[WL-2 : WL-1-LUT_addWidth];
					ini <= LUT[reg_cmp];
					ini2[WL-1:WL-LUT_bits] <= ini;
					mul_1_r <= ~mul1_net;
				end
			end
	end

multiplexer #(.N(WL)) mux (.a(ini2),.b(tmp_result_2),.Sel(Sel),.out(iniValue));
		
mult_unsigned #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(WL-1), .WIO(1), .WFO(dWL-1)) multiplier_1 
				   (.CLK(CLK), .RST(nRST), .in1(din), .in2(iniValue), .out(mul1_net));
				   
mult_unsigned #(.WI1(1), .WF1(dWL-1), .WI2(1), .WF2(WL-1), .WIO(1), .WFO(dWL*2-1)) multiplier_2 
				   (.CLK(CLK), .RST(nRST), .in1(mul_1_r), .in2(iniValue), .out(mul2_net));


		ux_round2nearest
			#(									
				.WordLength(dWL*2),
				.RoundLength(dWL*2-WL)
			 )
		round_0 
			(
				.CLK(CLK),
				.RESET(nRST),
				.CE(CE),
				.x(mul2_net),
				.y(tmp_result_1)
			 );
			 
endmodule
module Reciprocal_NR_multicycle






		#(parameter 	
						WL = 24,
						LUT_bits = 10,
						LUT_addWidth = 6,
						dWL = 26,
						ITERATION = 1





		 ) 		

		(
			input CLK,
			input nRST,
			input CE,
			
			input [WL-1:0] din,

			output reg [WL-1:0] dout
		);



		reg  [LUT_bits-1 : 0]     LUT [2**LUT_addWidth-1 : 0];
		reg  [LUT_bits-1 : 0]	  ini;
		reg  [WL-1		 :  0]    ini2;
		wire [WL-1		 : 0]  	  iniValue;
		reg  [LUT_addWidth-1:0]   reg_cmp;
		wire [dWL-1 :0]   		  mul1_net;
		reg  [dWL-1 :0]   		  mul_1_r;
		wire [dWL*2-1:0]	  	  mul2_net;
		wire [WL-1:0]			  tmp_result_1;
		reg  [WL-1:0]			  tmp_result_2;
		reg  					  Sel;







integer pointer;

		always @ (posedge CLK) begin
			if(~nRST) begin
					Sel <= 1'b0;
					pointer <= 0;
			end
			else begin
				if (CE) begin
					tmp_result_2 <= tmp_result_1;
					if (pointer == ITERATION) begin
						dout <= tmp_result_1;
						pointer <= 0;
						Sel <= 1'b0;
					end else begin
						pointer <= pointer + 1;
						Sel <= 1'b1;
					end
				end
			end
		end

	always @ * begin
			if(~nRST) begin
					reg_cmp <= 0;
					ini <= 0;
					ini2 <= 0;
					mul_1_r <= 0;		
			end else begin
				if (CE) begin
					reg_cmp  <= din[WL-2 : WL-1-LUT_addWidth];
					ini <= LUT[reg_cmp];
					ini2[WL-1:WL-LUT_bits] <= ini;
					mul_1_r <= ~mul1_net;
				end
			end
	end

multiplexer #(.N(WL)) mux (.a(ini2),.b(tmp_result_2),.Sel(Sel),.out(iniValue));
		
mult_unsigned #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(WL-1), .WIO(1), .WFO(dWL-1)) multiplier_1 
				   (.CLK(CLK), .RST(nRST), .in1(din), .in2(iniValue), .out(mul1_net));
				   
mult_unsigned #(.WI1(1), .WF1(dWL-1), .WI2(1), .WF2(WL-1), .WIO(1), .WFO(dWL*2-1)) multiplier_2 
				   (.CLK(CLK), .RST(nRST), .in1(mul_1_r), .in2(iniValue), .out(mul2_net));


		ux_round2nearest
			#(									
				.WordLength(dWL*2),
				.RoundLength(dWL*2-WL)
			 )
		round_0 
			(
				.CLK(CLK),
				.RESET(nRST),
				.CE(CE),
				.x(mul2_net),
				.y(tmp_result_1)
			 );
			 
endmodule