data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:1: Cannot find include file: Altera/Mf.v\n`include "Altera/Mf.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Data/Memory,data/full_repos/permissive/131921633/Altera/Mf.v\n             data/full_repos/permissive/131921633/tv/Data/Memory,data/full_repos/permissive/131921633/Altera/Mf.v.v\n             data/full_repos/permissive/131921633/tv/Data/Memory,data/full_repos/permissive/131921633/Altera/Mf.v.sv\n             Altera/Mf.v\n             Altera/Mf.v.v\n             Altera/Mf.v.sv\n             obj_dir/Altera/Mf.v\n             obj_dir/Altera/Mf.v.v\n             obj_dir/Altera/Mf.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:2: Cannot find include file: Util/Math.v\n`include "Util/Math.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:3: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:5: Cannot find include file: Data/Memory/bam.v\n`include "Data/Memory/bam.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:9: Define or directive not defined: \'`Data_Control_Control_T\'\n`Data_Control_Control_T(logic) ctrl;\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:9: syntax error, unexpected \'(\'\n`Data_Control_Control_T(logic) ctrl;\n                        ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:29: Define or directive not defined: \'`Data_Control_Control_Clock\'\ninitial `Data_Control_Control_Clock(ctrl) = 1\'b0;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:29: syntax error, unexpected \'=\'\ninitial `Data_Control_Control_Clock(ctrl) = 1\'b0;\n                                          ^\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:30: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:30: syntax error, unexpected \'=\'\nalways #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n                                            ^\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:30: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n                                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:30: Unsupported: Ignoring delay on this delayed statement.\nalways #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:33: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:34: Define or directive not defined: \'`Data_Control_Control_Reset\'\n `Data_Control_Control_Reset(ctrl) = 1\'b1;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:34: syntax error, unexpected \'=\'\n `Data_Control_Control_Reset(ctrl) = 1\'b1;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:36: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:37: Define or directive not defined: \'`Data_Control_Control_Reset\'\n `Data_Control_Control_Reset(ctrl) = 1\'b0;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:37: syntax error, unexpected \'=\'\n `Data_Control_Control_Reset(ctrl) = 1\'b0;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:43: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:49: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:53: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:57: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Memory/bam.sv:62: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 15 error(s), 8 warning(s)\n'
module Data_Memory_bam_tb;

`Data_Control_Control_T(logic) ctrl;
logic [3:0] addr;
logic [31:0] data;
logic [3:0] bytes;
logic [31:0] out;
logic wren;

Data_Memory_bam #
	( .DATA_W (32)
	, .BYTE_W (8)
	, .ADDR_WORD_L (4)
	) DUT
	( .ctrl (ctrl)
	, .addr (addr)
	, .data (data)
	, .bytes (bytes)
	, .out (out)
	, .wren (wren)
	);

initial `Data_Control_Control_Clock(ctrl) = 1'b0;
always #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);

initial begin
	#0;
	`Data_Control_Control_Reset(ctrl) = 1'b1;

	#10;
	`Data_Control_Control_Reset(ctrl) = 1'b0;
	addr = 4'h4;
	data = 32'h01234567;
	bytes = 4'b1111;
	wren = 1'b1;

	#10;
	addr = 4'h0;
	data = 32'h89abcdef;
	bytes = 4'b1111;
	wren = 1'b1;

	#10;
	bytes = 4'b1111;
	wren = 1'b0;

	#10;
	bytes = 4'b1001;
	wren = 1'b0;

	#10;
	addr = 4'h2;
	bytes = 4'b0011;
	wren = 1'b0;

	#10;
	addr = 4'h1;
	data = 32'h76543210;
	bytes = 4'b1001;
	wren = 1'b1;
end

endmodule
module Data_Memory_bam_tb;


`Data_Control_Control_T(logic) ctrl;
logic [3:0] addr;
logic [31:0] data;
logic [3:0] bytes;
logic [31:0] out;
logic wren;

Data_Memory_bam #
	( .DATA_W (32)
	, .BYTE_W (8)
	, .ADDR_WORD_L (4)
	) DUT
	( .ctrl (ctrl)
	, .addr (addr)
	, .data (data)
	, .bytes (bytes)
	, .out (out)
	, .wren (wren)
	);

initial `Data_Control_Control_Clock(ctrl) = 1'b0;
always #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);

initial begin
	#0;
	`Data_Control_Control_Reset(ctrl) = 1'b1;

	#10;
	`Data_Control_Control_Reset(ctrl) = 1'b0;
	addr = 4'h4;
	data = 32'h01234567;
	bytes = 4'b1111;
	wren = 1'b1;

	#10;
	addr = 4'h0;
	data = 32'h89abcdef;
	bytes = 4'b1111;
	wren = 1'b1;

	#10;
	bytes = 4'b1111;
	wren = 1'b0;

	#10;
	bytes = 4'b1001;
	wren = 1'b0;

	#10;
	addr = 4'h2;
	bytes = 4'b0011;
	wren = 1'b0;

	#10;
	addr = 4'h1;
	data = 32'h76543210;
	bytes = 4'b1001;
	wren = 1'b1;
end

endmodule