data/full_repos/permissive/211878730/atlys/practice/audio.v
data/verilator_xmls/ba76d70d-4625-471c-a357-e850a4f39e66.xml
module audio(
    input  wire clk,
    input  wire btn,
    output wire spkr
    );

    reg [31:0] cnt;

    always @(posedge clk) begin
        if (cnt == 32'd113636)
            cnt <= 32'd0;
        else
            cnt <= cnt + 32'd1;
    end

    assign spkr = btn && (cnt < 56818);

endmodule
module audio(
    input  wire clk,
    input  wire btn,
    output wire spkr
    );


    reg [31:0] cnt;

    always @(posedge clk) begin
        if (cnt == 32'd113636)
            cnt <= 32'd0;
        else
            cnt <= cnt + 32'd1;
    end

    assign spkr = btn && (cnt < 56818);

endmodule