data/full_repos/permissive/113582216/Experiment/FPGA1/checkOddEven/checkOddEven.v
data/verilator_xmls/4f8891d5-321f-450a-b809-f6b8dd9d3629.xml
module checkOddEven(
	input [7:0] in,
	output odd,
	output even
	);
	
	assign odd = in[0] ^ in[1] ^ in[2] ^ in[3]
					^ in[4] ^ in[5] ^ in[6] ^ in[7];
	assign even = ~odd;
	
endmodule
module checkOddEven(
	input [7:0] in,
	output odd,
	output even
	);

	
	assign odd = in[0] ^ in[1] ^ in[2] ^ in[3]
					^ in[4] ^ in[5] ^ in[6] ^ in[7];
	assign even = ~odd;
	
endmodule