data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v
data/verilator_xmls/70595310-3040-4210-acd1-1699f82b3e25.xml
module mac_18(a, b, c, out);
parameter DATA_WIDTH = 18;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule
module mac_18(a, b, c, out);

parameter DATA_WIDTH = 18;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule