data/full_repos/permissive/143278/ivltests/br_gh18.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh18.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #0 $display("%b", y);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug();

wire [3:0] y = 4'b0 * 4'bx;

initial begin
  #0 $display("%b", y);
  if (y === 4'bxxxx)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module bug();


wire [3:0] y = 4'b0 * 4'bx;

initial begin
  #0 $display("%b", y);
  if (y === 4'bxxxx)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule