data/full_repos/permissive/147790758/tb2_b2bd.v
 line:19: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b2bd.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b2bd.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/147790758/tb2_b2bd.v:11: Cannot find file containing module: \'b2bd\'\nb2bd DUT (.sw(datain), .led(dataout));\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b2bd\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b2bd.v\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b2bd.sv\n             b2bd\n             b2bd.v\n             b2bd.sv\n             obj_dir/b2bd\n             obj_dir/b2bd.v\n             obj_dir/b2bd.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb2_b2bd();
	
	reg [3:0]datain;
	reg [7:0]expected;
	wire [7:0]dataout;
	reg [3:0]tetrad;
	integer i;
	
b2bd DUT (.sw(datain), .led(dataout));
 
initial begin: make_data
	$display("**UNIT TEST STARTED**");
	datain = 4'b0000;
	for (i= 0; i<=9; i=i+1) begin
		expected = {4'b0000,datain};
		#10;
		check_data(dataout, expected);
		datain = datain + 1'b1;
	end
	

	tetrad = 4'b0000;
	for (i= 0; i<=5; i=i+1) begin
		expected = {4'b0001,tetrad};
		#10;
		check_data(dataout, expected);
		tetrad = tetrad + 1'b1;
		datain = datain + 1'b1;
	end
	$display("**ALL TESTS PASSED**");
	$stop;
end	

task check_data;
		input [7:0]dataout;
		input [7:0]expected;
begin
	$display("Now testing with inputs: %b, Expected result: %b Actual result: %b", datain, expected, dataout);	
	if (dataout != expected) begin
			$display("ERROR: Expected %b, but got %b. Inputs were: %b", expected, dataout, datain);
			$display("**ERROR: UNIT DOES NOT WORK PROPERLY**");
			$stop;
	end
end
endtask
endmodule
module tb2_b2bd();

	
	reg [3:0]datain;
	reg [7:0]expected;
	wire [7:0]dataout;
	reg [3:0]tetrad;
	integer i;
	
b2bd DUT (.sw(datain), .led(dataout));
 
initial begin: make_data
	$display("**UNIT TEST STARTED**");
	datain = 4'b0000;
	for (i= 0; i<=9; i=i+1) begin
		expected = {4'b0000,datain};
		#10;
		check_data(dataout, expected);
		datain = datain + 1'b1;
	end
	

	tetrad = 4'b0000;
	for (i= 0; i<=5; i=i+1) begin
		expected = {4'b0001,tetrad};
		#10;
		check_data(dataout, expected);
		tetrad = tetrad + 1'b1;
		datain = datain + 1'b1;
	end
	$display("**ALL TESTS PASSED**");
	$stop;
end	

task check_data;
		input [7:0]dataout;
		input [7:0]expected;
begin
	$display("Now testing with inputs: %b, Expected result: %b Actual result: %b", datain, expected, dataout);	
	if (dataout != expected) begin
			$display("ERROR: Expected %b, but got %b. Inputs were: %b", expected, dataout, datain);
			$display("**ERROR: UNIT DOES NOT WORK PROPERLY**");
			$stop;
	end
end
endtask
endmodule