data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) RxD = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) RxD = 1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) RxD = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) RxD = 1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) RxD = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) RxD = 1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) RxD = 1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) RxD = 1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) RxD = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) RxD = 1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #500  buttons[0] = 1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #2000 buttons[0] = 0;\n  ^\n%Error: data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1/serial_tb.v:70: Cannot find file containing module: \'serial_top\'\n serial_top sptop(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1,data/full_repos/permissive/172396252/serial_top\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1,data/full_repos/permissive/172396252/serial_top.v\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sim_1,data/full_repos/permissive/172396252/serial_top.sv\n             serial_top\n             serial_top.v\n             serial_top.sv\n             obj_dir/serial_top\n             obj_dir/serial_top.v\n             obj_dir/serial_top.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module serial_tb();

	reg clk = 0;
	reg [15:0] sw = 16'h0000;
	wire [15:0] led;
	reg [4:0] buttons = 1;
	wire [7:0] seg;
	wire [3:0] an;
	reg RxD = 1;
	wire TxD;



	parameter delay = 26042;  

	always #5 clk = ~clk;
	always begin	











		#(delay) RxD = 0;
		#(delay) RxD = 1;
		#(delay) RxD = 0;
		#(delay) RxD = 1;
		#(delay) RxD = 0;
		#(delay) RxD = 1;
		#(delay) RxD = 1;
		#(delay) RxD = 1;
		#(delay) RxD = 0;
		#(delay) RxD = 1;

	end

	initial begin
		#500  buttons[0] = 1;
		#2000 buttons[0] = 0;
	end

	serial_top sptop(
		clk,
		sw,
		led,
		buttons,
		seg,
		an,
		TxD,
		RxD,
		Tx2,
		Rx2
	); 
		
		
		
	endmodule
module serial_tb();


	reg clk = 0;
	reg [15:0] sw = 16'h0000;
	wire [15:0] led;
	reg [4:0] buttons = 1;
	wire [7:0] seg;
	wire [3:0] an;
	reg RxD = 1;
	wire TxD;



	parameter delay = 26042;  

	always #5 clk = ~clk;
	always begin	











		#(delay) RxD = 0;
		#(delay) RxD = 1;
		#(delay) RxD = 0;
		#(delay) RxD = 1;
		#(delay) RxD = 0;
		#(delay) RxD = 1;
		#(delay) RxD = 1;
		#(delay) RxD = 1;
		#(delay) RxD = 0;
		#(delay) RxD = 1;

	end

	initial begin
		#500  buttons[0] = 1;
		#2000 buttons[0] = 0;
	end

	serial_top sptop(
		clk,
		sw,
		led,
		buttons,
		seg,
		an,
		TxD,
		RxD,
		Tx2,
		Rx2
	); 
		
		
		
	endmodule