data/full_repos/permissive/128426084/vivado/uec2_DeathRace.srcs/sources_1/new/vga.v
None: at end of input
1: b'%Error: data/full_repos/permissive/128426084/vivado/uec2_DeathRace.srcs/sources_1/new/vga.v:14: Cannot find include file: verilog_macro_bus.vh\n`include "verilog_macro_bus.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128426084/vivado/uec2_DeathRace.srcs/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh\n             data/full_repos/permissive/128426084/vivado/uec2_DeathRace.srcs/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.v\n             data/full_repos/permissive/128426084/vivado/uec2_DeathRace.srcs/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.sv\n             verilog_macro_bus.vh\n             verilog_macro_bus.vh.v\n             verilog_macro_bus.vh.sv\n             obj_dir/verilog_macro_bus.vh\n             obj_dir/verilog_macro_bus.vh.v\n             obj_dir/verilog_macro_bus.vh.sv\n%Error: data/full_repos/permissive/128426084/vivado/uec2_DeathRace.srcs/sources_1/new/vga.v:30: Define or directive not defined: \'`VGA_BUS_SIZE\'\nwire [`VGA_BUS_SIZE - 1 : 0] vga_bus [3:-1];\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/vivado/uec2_DeathRace.srcs/sources_1/new/vga.v:31: Define or directive not defined: \'`MOUSE_BUS_SIZE\'\nwire [`MOUSE_BUS_SIZE - 1 : 0] mouse_bus [1:0] ;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/vivado/uec2_DeathRace.srcs/sources_1/new/vga.v:81: Define or directive not defined: \'`VGA_SPLIT_INPUT\'\n `VGA_SPLIT_INPUT(vga_bus[2])\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/vivado/uec2_DeathRace.srcs/sources_1/new/vga.v:81: syntax error, unexpected \'(\'\n `VGA_SPLIT_INPUT(vga_bus[2])\n                  ^~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module vga (
  inout wire ps2_data,
  inout wire ps2_clk,
  input wire clk,
  input wire [15:0] sw,
  output reg vs,
  output reg hs,
  output reg [3:0] r,
  output reg [3:0] g,
  output reg [3:0] b,
  output wire pclk_mirror,
  input wire rst
    );

wire [`VGA_BUS_SIZE - 1 : 0] vga_bus [3:-1];
wire [`MOUSE_BUS_SIZE - 1 : 0] mouse_bus [1:0] ;






  wire clk_in;
  wire locked;
  wire clk_fb;
  wire clk_ss;
  wire clk_out;
  wire pclk;
  wire pclk100;
  (* KEEP = "TRUE" *) 
  (* ASYNC_REG = "TRUE" *)
  reg [7:0] safe_start = 0;


clk_wiz_0 myClk(
    .clk_out1(pclk100),
    .clk_in1(clk),
    .locked(locked),
    .clk_out2(pclk),
    .reset(rst)
);


  ODDR pclk_oddr (
    .Q(pclk_mirror),
    .C(pclk),
    .CE(1'b1),
    .D1(1'b1),
    .D2(1'b0),
    .R(1'b0),
    .S(1'b0)
  );

wire [21:0] address;
wire [11:0] rgb;

wire TimeOut;  
  

  vga_timing my_timing (
    .vga_out(vga_bus[-1]),
    .pclk(pclk),
    .rst(!rst)
  );
  
 `VGA_SPLIT_INPUT(vga_bus[2])
  wire Title_Sel,Wait_for_Game,Time_out,GameOn,Highscore,dual,single;
  
  
Car_display #(.Color(3'b110),.X(500),.Y(500)) MyCar(
    .clk(pclk),
    .direction(sw[3:0]),
    .enable(TimeOut),
    .go(sw[5]),
    .vga_in(vga_bus[-1]),
    .vga_out(vga_bus[0]),
    .rst(!rst)
);
Car_display #(.X(300),.Y(500),.Color(3'b100)) MyCar2(
    
    .clk(pclk),
    .direction(sw[9:6]),
    .enable(!TimeOut),
    .go(sw[11]),
    .vga_in(vga_bus[0]),
    .vga_out(vga_bus[1]),
    .rst(!rst)
);

     
game_bg Game_bg(
    .clk(pclk),
    .Player1Score(8'hf),
    .Player2Score({4'b0,sw[15:12]}),
    .vga_in(vga_bus[1]),
    .vga_out(vga_bus[2]),
    .rst(!rst),
    .TimeOut(TimeOut)
);  

  
  always @(posedge pclk)
  begin
    vs <= vsync_in;
    hs <= hsync_in;
    
    {r,g,b} <= ((vblnk_in == 0) && (hblnk_in == 0))?rgb_in:12'h000;
  end

endmodule
module vga (
  inout wire ps2_data,
  inout wire ps2_clk,
  input wire clk,
  input wire [15:0] sw,
  output reg vs,
  output reg hs,
  output reg [3:0] r,
  output reg [3:0] g,
  output reg [3:0] b,
  output wire pclk_mirror,
  input wire rst
    );


wire [`VGA_BUS_SIZE - 1 : 0] vga_bus [3:-1];
wire [`MOUSE_BUS_SIZE - 1 : 0] mouse_bus [1:0] ;






  wire clk_in;
  wire locked;
  wire clk_fb;
  wire clk_ss;
  wire clk_out;
  wire pclk;
  wire pclk100;
  (* KEEP = "TRUE" *) 
  (* ASYNC_REG = "TRUE" *)
  reg [7:0] safe_start = 0;


clk_wiz_0 myClk(
    .clk_out1(pclk100),
    .clk_in1(clk),
    .locked(locked),
    .clk_out2(pclk),
    .reset(rst)
);


  ODDR pclk_oddr (
    .Q(pclk_mirror),
    .C(pclk),
    .CE(1'b1),
    .D1(1'b1),
    .D2(1'b0),
    .R(1'b0),
    .S(1'b0)
  );

wire [21:0] address;
wire [11:0] rgb;

wire TimeOut;  
  

  vga_timing my_timing (
    .vga_out(vga_bus[-1]),
    .pclk(pclk),
    .rst(!rst)
  );
  
 `VGA_SPLIT_INPUT(vga_bus[2])
  wire Title_Sel,Wait_for_Game,Time_out,GameOn,Highscore,dual,single;
  
  
Car_display #(.Color(3'b110),.X(500),.Y(500)) MyCar(
    .clk(pclk),
    .direction(sw[3:0]),
    .enable(TimeOut),
    .go(sw[5]),
    .vga_in(vga_bus[-1]),
    .vga_out(vga_bus[0]),
    .rst(!rst)
);
Car_display #(.X(300),.Y(500),.Color(3'b100)) MyCar2(
    
    .clk(pclk),
    .direction(sw[9:6]),
    .enable(!TimeOut),
    .go(sw[11]),
    .vga_in(vga_bus[0]),
    .vga_out(vga_bus[1]),
    .rst(!rst)
);

     
game_bg Game_bg(
    .clk(pclk),
    .Player1Score(8'hf),
    .Player2Score({4'b0,sw[15:12]}),
    .vga_in(vga_bus[1]),
    .vga_out(vga_bus[2]),
    .rst(!rst),
    .TimeOut(TimeOut)
);  

  
  always @(posedge pclk)
  begin
    vs <= vsync_in;
    hs <= hsync_in;
    
    {r,g,b} <= ((vblnk_in == 0) && (hblnk_in == 0))?rgb_in:12'h000;
  end

endmodule