data/full_repos/permissive/21051978/final/src/pipe2tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/pipe2tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk=0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/pipe2tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/pipe2tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/pipe2tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/pipe2tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/final/src/pipe2tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:9: Little bit endian vector: MSB < LSB of bit range: 0:4\n reg [0:4] aluop_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:10: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg [0:2] ppp_in; \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:11: Little bit endian vector: MSB < LSB of bit range: 0:1\n reg [0:1] ww_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:12: Little bit endian vector: MSB < LSB of bit range: 0:1\n reg [0:1] memop_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:13: Little bit endian vector: MSB < LSB of bit range: 0:20\n reg [0:20] memAddr_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:14: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] wbyteen_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:16: Little bit endian vector: MSB < LSB of bit range: 0:4\n reg [0:4] rwraddrd_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:18: Little bit endian vector: MSB < LSB of bit range: 0:127\n reg [0:127] rd1data_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:19: Little bit endian vector: MSB < LSB of bit range: 0:127\n reg [0:127] rd2data_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:23: Little bit endian vector: MSB < LSB of bit range: 0:4\n wire [0:4] aluop_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:24: Little bit endian vector: MSB < LSB of bit range: 0:2\n wire [0:2] ppp_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:25: Little bit endian vector: MSB < LSB of bit range: 0:1\n wire [0:1] ww_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:28: Little bit endian vector: MSB < LSB of bit range: 0:20\n wire [0:20] memAddr_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:29: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] wbyteen_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:31: Little bit endian vector: MSB < LSB of bit range: 0:4\n wire [0:4] rwraddrd_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:33: Little bit endian vector: MSB < LSB of bit range: 0:127\n wire [0:127] rd1data_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/final/src/pipe2tb.v:34: Little bit endian vector: MSB < LSB of bit range: 0:127\n wire [0:127] rd2data_out;\n      ^\n%Error: data/full_repos/permissive/21051978/final/src/pipe2tb.v:37: Cannot find file containing module: \'pipe2\'\n pipe2 pipe2_1(aluop_in, aluop_out, ppp_in, ppp_out, ww_in, ww_out, \n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/final/src,data/full_repos/permissive/21051978/pipe2\n             data/full_repos/permissive/21051978/final/src,data/full_repos/permissive/21051978/pipe2.v\n             data/full_repos/permissive/21051978/final/src,data/full_repos/permissive/21051978/pipe2.sv\n             pipe2\n             pipe2.v\n             pipe2.sv\n             obj_dir/pipe2\n             obj_dir/pipe2.v\n             obj_dir/pipe2.sv\n%Error: Exiting due to 1 error(s), 23 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pipe2tb;
	

	reg [0:4] aluop_in;
	reg [0:2] ppp_in; 
	reg [0:1] ww_in;
	reg [0:1] memop_in;
	reg [0:20] memAddr_in;
	reg [0:15] wbyteen_in;
	reg regwren_in;
	reg [0:4] rwraddrd_in;
	reg reginmuxop_in;
	reg [0:127] rd1data_in;
	reg [0:127] rd2data_in;
	reg clk, reset;
	

	wire [0:4] aluop_out;
	wire [0:2] ppp_out;
	wire [0:1] ww_out;
	wire memWrEn_out;
	wire memEn_out;
	wire [0:20] memAddr_out;
	wire [0:15] wbyteen_out;
	wire regwren_out;
	wire [0:4] rwraddrd_out;
	wire reginmuxop_out;
	wire [0:127] rd1data_out;
	wire [0:127] rd2data_out;
	

	pipe2 pipe2_1(aluop_in, aluop_out, ppp_in, ppp_out, ww_in, ww_out, 
		 memop_in, memWrEn_out, memEn_out, memAddr_in, memAddr_out,
		 wbyteen_in, wbyteen_out, regwren_in, regwren_out, rwraddrd_in,
		 rwraddrd_out, reginmuxop_in, reginmuxop_out,
		 rd1data_in, rd1data_out, rd2data_in, rd2data_out, clk, reset);
	
	always
		begin
		#5 clk=0;
		#5 clk=1;
		end
		
	initial
		begin
		#5;
		reset=1'b1;
		#10;
		reset=1'b0;
		#10;
			aluop_in<=5'b1;
			ppp_in<=3'b1; 
			ww_in<=2'b1;
			memop_in<=2'b11;
			memAddr_in<=21'b1;
			wbyteen_in<=16'b1;
			regwren_in<=1'b1;
			rwraddrd_in<=5'b1;
			reginmuxop_in<=1'b1;
			rd1data_in<=128'b1;
			rd2data_in<=128'b1;
		#10;
		$finish;
		end
endmodule
module pipe2tb;

	

	reg [0:4] aluop_in;
	reg [0:2] ppp_in; 
	reg [0:1] ww_in;
	reg [0:1] memop_in;
	reg [0:20] memAddr_in;
	reg [0:15] wbyteen_in;
	reg regwren_in;
	reg [0:4] rwraddrd_in;
	reg reginmuxop_in;
	reg [0:127] rd1data_in;
	reg [0:127] rd2data_in;
	reg clk, reset;
	

	wire [0:4] aluop_out;
	wire [0:2] ppp_out;
	wire [0:1] ww_out;
	wire memWrEn_out;
	wire memEn_out;
	wire [0:20] memAddr_out;
	wire [0:15] wbyteen_out;
	wire regwren_out;
	wire [0:4] rwraddrd_out;
	wire reginmuxop_out;
	wire [0:127] rd1data_out;
	wire [0:127] rd2data_out;
	

	pipe2 pipe2_1(aluop_in, aluop_out, ppp_in, ppp_out, ww_in, ww_out, 
		 memop_in, memWrEn_out, memEn_out, memAddr_in, memAddr_out,
		 wbyteen_in, wbyteen_out, regwren_in, regwren_out, rwraddrd_in,
		 rwraddrd_out, reginmuxop_in, reginmuxop_out,
		 rd1data_in, rd1data_out, rd2data_in, rd2data_out, clk, reset);
	
	always
		begin
		#5 clk=0;
		#5 clk=1;
		end
		
	initial
		begin
		#5;
		reset=1'b1;
		#10;
		reset=1'b0;
		#10;
			aluop_in<=5'b1;
			ppp_in<=3'b1; 
			ww_in<=2'b1;
			memop_in<=2'b11;
			memAddr_in<=21'b1;
			wbyteen_in<=16'b1;
			regwren_in<=1'b1;
			rwraddrd_in<=5'b1;
			reginmuxop_in<=1'b1;
			rd1data_in<=128'b1;
			rd2data_in<=128'b1;
		#10;
		$finish;
		end
endmodule