data/full_repos/permissive/18921956/HardwareLab/Upload/101062124_戴宏穎_Lab8/Mole.v
data/verilator_xmls/dcff58f7-f68d-4215-a9aa-dba63d71e592.xml
module Mole(
			output reg [15:0] mole16bit,
			input [3:0]random_value,
			input isFinished,
			input clk, 
			input rst_n
    );
	reg [15:0] next_mole;
	always@ (posedge clk or negedge rst_n) begin
		if (!rst_n) begin
			mole16bit <= 16'd0;
		end else begin
			mole16bit <= next_mole;
		end
	end
	always@ (*) begin
		if (isFinished) begin
			next_mole = mole16bit;
		end else begin
			next_mole = (16'b1 << random_value);
		end
	end
endmodule
module Mole(
			output reg [15:0] mole16bit,
			input [3:0]random_value,
			input isFinished,
			input clk, 
			input rst_n
    );

	reg [15:0] next_mole;
	always@ (posedge clk or negedge rst_n) begin
		if (!rst_n) begin
			mole16bit <= 16'd0;
		end else begin
			mole16bit <= next_mole;
		end
	end
	always@ (*) begin
		if (isFinished) begin
			next_mole = mole16bit;
		end else begin
			next_mole = (16'b1 << random_value);
		end
	end
endmodule