data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v
1: b'%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:6: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:75: Define or directive not defined: \'`SERIAL_WCNT\'\n      end else if( waitnum >= `SERIAL_WCNT ) begin\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:75: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      end else if( waitnum >= `SERIAL_WCNT ) begin\n                                           ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:81: syntax error, unexpected else\n      end else begin\n          ^~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:192: Define or directive not defined: \'`SERIAL_WCNT\'\n   assign waitcnt = `SERIAL_WCNT;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:192: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   assign waitcnt = `SERIAL_WCNT;\n                                ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:283: Define or directive not defined: \'`APP_SIZE\'\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:283: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                               ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:287: Define or directive not defined: \'`APP_SIZE\'\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:287: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                               ^\n%Error: Exiting due to 10 error(s)\n'
module SingleUartTx(CLK, RST_X, TXD, ERR, DT01, WE01);
   input  wire       CLK, RST_X;
   input  wire [7:0] DT01;
   input  wire 	     WE01;
   output wire 	     TXD, ERR;
   
   wire 	     RE01;
   wire [7:0] 	     data01;
   wire 	     en01;
   wire 	     RDY01;
   wire 	     ERR01;
   wire 	     TxRdy;

   assign ERR = ERR01;
   assign RE01 = (RDY01 & TxRdy);

   TX_FIFO fifo_01(CLK, RST_X, DT01, WE01, RE01, data01, en01, RDY01, ERR01); 
   UartTx send(CLK, RST_X, data01, en01, TXD, TxRdy);
endmodule
module SingleUartTx(CLK, RST_X, TXD, ERR, DT01, WE01);

   input  wire       CLK, RST_X;
   input  wire [7:0] DT01;
   input  wire 	     WE01;
   output wire 	     TXD, ERR;
   
   wire 	     RE01;
   wire [7:0] 	     data01;
   wire 	     en01;
   wire 	     RDY01;
   wire 	     ERR01;
   wire 	     TxRdy;

   assign ERR = ERR01;
   assign RE01 = (RDY01 & TxRdy);

   TX_FIFO fifo_01(CLK, RST_X, DT01, WE01, RE01, data01, en01, RDY01, ERR01); 
   UartTx send(CLK, RST_X, data01, en01, TXD, TxRdy);
endmodule