data/full_repos/permissive/152883307/Project/PID.v
 line:1 column:1: Illegal character '\ufeff'
1: b'%Warning-WIDTH: data/full_repos/permissive/152883307/Project/PID.v:75: Operator ADD expects 32 or 15 bits on the LHS, but LHS\'s VARREF \'u_prev\' generates 13 bits.\n                                                                     : ... In instance PID\n    u_temp <= u_prev + (k1*e_in) - (k2*e_prev1) + (k3*e_prev2); \n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module PID #(parameter W=12)
(	u_out,
	e_in,
	clk,
	reset_n,
	u_prev
	);
output signed	 [W: 0] u_out;
input signed	 [W: 0] e_in;
input clk;
input reset_n;

parameter 	Kp = 1;	   				
parameter 	Ki = 20;							
parameter 	Kd = 1;	

parameter	T  = 0.05;
parameter	Ti = Kp/Ki;
parameter	Td = Kd/Kp;
















parameter k1 = Kp*(1+(1)+(Td*20));
parameter k2 = Kp*(1+(2*Td*20));
parameter k3 = Kp*(Td*20);
output reg signed	[W: 0] 	u_prev;
reg 	signed 		[W: 0] 	e_prev2;
reg 	signed 		[W: 0] 	e_prev1;
reg 	signed  		[W+2: 0]	u_temp;
reg								seq;



assign u_out= 	(~u_temp[W+2] &  u_temp[W+1]) ? 13'b0_1111_1111_1111 :
					( u_temp[W+2] & ~u_temp[W+1]) ? 13'b1_0000_0000_0000 :
					(~u_temp[W+1] &  u_temp[W]) 	? 13'b0_1111_1111_1111 :
               ( u_temp[W+1] & ~u_temp[W]) 	? 13'b1_0000_0000_0000 :
               u_temp[W:0];
					
always @ (posedge clk)
begin
if (!reset_n) begin
		u_prev <= 0;
		e_prev1 <= 0;
		e_prev2 <= 0;
		u_temp <=  0;
		seq <= 0;
	end
	else begin
		case (seq)
			0: begin
				e_prev2 <= e_prev1;
				e_prev1 <= e_in;
				u_prev <= u_out;
				seq <= 1;
				end
			1: begin
				u_temp <= u_prev + (k1*e_in) - (k2*e_prev1) + (k3*e_prev2);
				seq <= 0;
				end
		endcase
	end
end

endmodule
module PID #(parameter W=12)
(	u_out,
	e_in,
	clk,
	reset_n,
	u_prev
	);

output signed	 [W: 0] u_out;
input signed	 [W: 0] e_in;
input clk;
input reset_n;

parameter 	Kp = 1;	   				
parameter 	Ki = 20;							
parameter 	Kd = 1;	

parameter	T  = 0.05;
parameter	Ti = Kp/Ki;
parameter	Td = Kd/Kp;
















parameter k1 = Kp*(1+(1)+(Td*20));
parameter k2 = Kp*(1+(2*Td*20));
parameter k3 = Kp*(Td*20);
output reg signed	[W: 0] 	u_prev;
reg 	signed 		[W: 0] 	e_prev2;
reg 	signed 		[W: 0] 	e_prev1;
reg 	signed  		[W+2: 0]	u_temp;
reg								seq;



assign u_out= 	(~u_temp[W+2] &  u_temp[W+1]) ? 13'b0_1111_1111_1111 :
					( u_temp[W+2] & ~u_temp[W+1]) ? 13'b1_0000_0000_0000 :
					(~u_temp[W+1] &  u_temp[W]) 	? 13'b0_1111_1111_1111 :
               ( u_temp[W+1] & ~u_temp[W]) 	? 13'b1_0000_0000_0000 :
               u_temp[W:0];
					
always @ (posedge clk)
begin
if (!reset_n) begin
		u_prev <= 0;
		e_prev1 <= 0;
		e_prev2 <= 0;
		u_temp <=  0;
		seq <= 0;
	end
	else begin
		case (seq)
			0: begin
				e_prev2 <= e_prev1;
				e_prev1 <= e_in;
				u_prev <= u_out;
				seq <= 1;
				end
			1: begin
				u_temp <= u_prev + (k1*e_in) - (k2*e_prev1) + (k3*e_prev2);
				seq <= 0;
				end
		endcase
	end
end

endmodule