data/full_repos/permissive/197356760/FIFO/fifo_top.v
 line:31: before: "reset"
1: b"%Error: data/full_repos/permissive/197356760/FIFO/fifo_top.v:19: Cannot find file containing module: 'mem_module'\n  mem_module  m1 (clk, rst, wr_en, read_ptr, wrt_ptr, din, dout);\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197356760/FIFO,data/full_repos/permissive/197356760/mem_module\n             data/full_repos/permissive/197356760/FIFO,data/full_repos/permissive/197356760/mem_module.v\n             data/full_repos/permissive/197356760/FIFO,data/full_repos/permissive/197356760/mem_module.sv\n             mem_module\n             mem_module.v\n             mem_module.sv\n             obj_dir/mem_module\n             obj_dir/mem_module.v\n             obj_dir/mem_module.sv\n%Error: data/full_repos/permissive/197356760/FIFO/fifo_top.v:21: Cannot find file containing module: 'read_ptr_module'\n  read_ptr_module m2 (clk, rst, rd_en, read_ptr);\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/FIFO/fifo_top.v:23: Cannot find file containing module: 'write_ptr_module'\n  write_ptr_module m3 (clk, rst, wr_en, wrt_ptr);\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/FIFO/fifo_top.v:25: Cannot find file containing module: 'sts_module'\n  sts_module m4(clk, rst, rd_en, wr_en, f_empty, f_full);\n  ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module fifo_design # (parameter width = 8, depth = 8)
  					(input clk, rst, f_rd, f_wr,
 					input [width-1:0] din,
					output f_empty, f_full,
 					output [width-1:0] dout);
  
  
  wire rd_en, wr_en;
  wire [2:0] read_ptr, wrt_ptr;
  	
  mem_module  m1 (clk, rst, wr_en, read_ptr, wrt_ptr, din, dout);
  
  read_ptr_module m2 (clk, rst, rd_en, read_ptr);
  
  write_ptr_module m3 (clk, rst, wr_en, wrt_ptr);
  
  sts_module m4(clk, rst, rd_en, wr_en, f_empty, f_full);
  
  assign rd_en = !f_empty & f_rd;  
  assign wr_en = !f_full & f_wr;
  
endmodule
module fifo_design # (parameter width = 8, depth = 8)
  					(input clk, rst, f_rd, f_wr,
 					input [width-1:0] din,
					output f_empty, f_full,
 					output [width-1:0] dout);

  
  
  wire rd_en, wr_en;
  wire [2:0] read_ptr, wrt_ptr;
  	
  mem_module  m1 (clk, rst, wr_en, read_ptr, wrt_ptr, din, dout);
  
  read_ptr_module m2 (clk, rst, rd_en, read_ptr);
  
  write_ptr_module m3 (clk, rst, wr_en, wrt_ptr);
  
  sts_module m4(clk, rst, rd_en, wr_en, f_empty, f_full);
  
  assign rd_en = !f_empty & f_rd;  
  assign wr_en = !f_full & f_wr;
  
endmodule