data/full_repos/permissive/174155074/systems/pipelines/simple-pipeline/simple-pipeline-tb.v
 line:45: before: "$"
1: b'%Error: data/full_repos/permissive/174155074/systems/pipelines/simple-pipeline/simple-pipeline-tb.v:24: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("simple-pipeline-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/systems/pipelines/simple-pipeline/simple-pipeline-tb.v:25: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, simple_pipeline_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/systems/pipelines/simple-pipeline/simple-pipeline-tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/systems/pipelines/simple-pipeline/simple-pipeline-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #15 A = 8\'h01; B = 8\'h02; C = 8\'h05; D = 8\'h04;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/systems/pipelines/simple-pipeline/simple-pipeline-tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #20 A = 8\'h16; B = 8\'h16; C = 8\'h62; D = 8\'h01;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/systems/pipelines/simple-pipeline/simple-pipeline-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #20 A = 8\'h03; B = 8\'h03; C = 8\'h09; D = 8\'h08;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/systems/pipelines/simple-pipeline/simple-pipeline-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simple_pipeline_tb;


reg  [7:0]    A, B, C, D;
reg           CLK;
wire [7:0]    F;


simple_pipeline uut(
    .clk(CLK),
    .a (A),
    .b (B),
    .c (C),
    .d (D),
    .f (F)
);


initial begin
    $dumpfile("simple-pipeline-tb.vcd");
    $dumpvars(0, simple_pipeline_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    A = 8'h00; B = 8'h00; C = 8'h00; D = 8'h00; 


    #15 A = 8'h01; B = 8'h02; C = 8'h05; D = 8'h04;
    #20 A = 8'h16; B = 8'h16; C = 8'h62; D = 8'h01;
    #20 A = 8'h03; B = 8'h03; C = 8'h09; D = 8'h08;
    #100

    $display("test complete");
    $finish;
end

endmodule
module simple_pipeline_tb;



reg  [7:0]    A, B, C, D;
reg           CLK;
wire [7:0]    F;


simple_pipeline uut(
    .clk(CLK),
    .a (A),
    .b (B),
    .c (C),
    .d (D),
    .f (F)
);


initial begin
    $dumpfile("simple-pipeline-tb.vcd");
    $dumpvars(0, simple_pipeline_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    A = 8'h00; B = 8'h00; C = 8'h00; D = 8'h00; 


    #15 A = 8'h01; B = 8'h02; C = 8'h05; D = 8'h04;
    #20 A = 8'h16; B = 8'h16; C = 8'h62; D = 8'h01;
    #20 A = 8'h03; B = 8'h03; C = 8'h09; D = 8'h08;
    #100

    $display("test complete");
    $finish;
end

endmodule