data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/pipe_in_check.v
1: b'%Warning-WIDTH: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/pipe_in_check.v:43: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                                                               : ... In instance pipe_in_check\n  level <= 16\'d0;\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/pipe_in_check.v:51: Operator LT expects 17 bits on the RHS, but RHS\'s CONST \'16\'hfc00\' generates 16 bits.\n                                                                                                                               : ... In instance pipe_in_check\n  if (level < 16\'d64512) begin\n            ^\n%Warning-WIDTH: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/pipe_in_check.v:64: Operator GT expects 17 bits on the RHS, but RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                                                               : ... In instance pipe_in_check\n    if (level > 16\'d0) begin\n              ^\n%Warning-WIDTH: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/PipeTest/XEM6010-Verilog/pipe_in_check.v:71: Operator LT expects 17 bits on the RHS, but RHS\'s CONST \'16\'hffff\' generates 16 bits.\n                                                                                                                               : ... In instance pipe_in_check\n    if (level < 16\'d65535) begin\n              ^\n%Error: Exiting due to 4 warning(s)\n'
module pipe_in_check(
	input  wire            clk,
	input  wire            reset,
	input  wire            pipe_in_write,
	input  wire [15:0]     pipe_in_data,
	output reg             pipe_in_ready,
	input  wire            throttle_set,
	input  wire [31:0]     throttle_val,
	input  wire            mode,
	output reg  [31:0]     error_count
	);

reg  [63:0]  lfsr;
reg  [31:0]  throttle;
reg  [16:0]  level;








always @(posedge clk) begin
	if (reset == 1'b1) begin
		error_count <= 0;
		throttle <= throttle_val;
		level <= 16'd0;
		
		if (mode == 1'b1) begin
			lfsr  <= 64'h0D0C0B0A04030201;
		end else begin
			lfsr  <= 64'h0000000100000001;
		end
	end else begin
		if (level < 16'd64512) begin
			pipe_in_ready <= 1'b1;
		end else begin
			pipe_in_ready <= 1'b0;
		end
	

		case ({pipe_in_write, throttle[0]})
			2'b00: begin
			end
			

			2'b01: begin
				if (level > 16'd0) begin
					level <= level - 1'b1;
				end
			end
			

			2'b10: begin
				if (level < 16'd65535) begin
					level <= level + 1'b1;
				end
			end
			

			2'b11: begin
			end
		endcase
	





		if (throttle_set == 1'b1) begin
			throttle <= throttle_val;
		end else begin
			throttle <= {throttle[0], throttle[31:1]};
		end
		
		

		if (pipe_in_write == 1'b1) begin
			if (pipe_in_data[15:0] != lfsr[15:0]) begin
				error_count <= error_count + 1'b1;
			end
		end


		if (pipe_in_write == 1'b1) begin
			if (mode == 1'b1) begin
				lfsr[31:0]  <= {lfsr[30:0],  lfsr[31] ^ lfsr[21] ^ lfsr[1] };
				lfsr[63:32] <= {lfsr[62:32], lfsr[63] ^ lfsr[53] ^ lfsr[33]};
			end else begin
				lfsr[31:0]  <= lfsr[31:0]  + 1'b1;
				lfsr[63:32] <= lfsr[63:32] + 1'b1;
			end
		end
	end
end

endmodule
module pipe_in_check(
	input  wire            clk,
	input  wire            reset,
	input  wire            pipe_in_write,
	input  wire [15:0]     pipe_in_data,
	output reg             pipe_in_ready,
	input  wire            throttle_set,
	input  wire [31:0]     throttle_val,
	input  wire            mode,
	output reg  [31:0]     error_count
	);


reg  [63:0]  lfsr;
reg  [31:0]  throttle;
reg  [16:0]  level;








always @(posedge clk) begin
	if (reset == 1'b1) begin
		error_count <= 0;
		throttle <= throttle_val;
		level <= 16'd0;
		
		if (mode == 1'b1) begin
			lfsr  <= 64'h0D0C0B0A04030201;
		end else begin
			lfsr  <= 64'h0000000100000001;
		end
	end else begin
		if (level < 16'd64512) begin
			pipe_in_ready <= 1'b1;
		end else begin
			pipe_in_ready <= 1'b0;
		end
	

		case ({pipe_in_write, throttle[0]})
			2'b00: begin
			end
			

			2'b01: begin
				if (level > 16'd0) begin
					level <= level - 1'b1;
				end
			end
			

			2'b10: begin
				if (level < 16'd65535) begin
					level <= level + 1'b1;
				end
			end
			

			2'b11: begin
			end
		endcase
	





		if (throttle_set == 1'b1) begin
			throttle <= throttle_val;
		end else begin
			throttle <= {throttle[0], throttle[31:1]};
		end
		
		

		if (pipe_in_write == 1'b1) begin
			if (pipe_in_data[15:0] != lfsr[15:0]) begin
				error_count <= error_count + 1'b1;
			end
		end


		if (pipe_in_write == 1'b1) begin
			if (mode == 1'b1) begin
				lfsr[31:0]  <= {lfsr[30:0],  lfsr[31] ^ lfsr[21] ^ lfsr[1] };
				lfsr[63:32] <= {lfsr[62:32], lfsr[63] ^ lfsr[53] ^ lfsr[33]};
			end else begin
				lfsr[31:0]  <= lfsr[31:0]  + 1'b1;
				lfsr[63:32] <= lfsr[63:32] + 1'b1;
			end
		end
	end
end

endmodule