data/full_repos/permissive/143286506/execute.v
 line:45: before: "case"
1: b"%Error: data/full_repos/permissive/143286506/execute.v:97: syntax error, unexpected INTEGER NUMBER\n      5'b01_001: assign reg2 = {8'd0,r2[7:0],r2[15:8].8'd0};\n                                                      ^~~~\n%Error: data/full_repos/permissive/143286506/execute.v:118: syntax error, unexpected ',', expecting '}'\n      5'b00_000: assign res = {24{dm_r_data [7]},dm_r_data [7:0]};\n                                                ^\n%Error: data/full_repos/permissive/143286506/execute.v:119: syntax error, unexpected ',', expecting '}'\n      5'b01_000: assign res = {24{dm_r_data [15]},dm_r_data [15:8]};\n                                                 ^\n%Error: data/full_repos/permissive/143286506/execute.v:120: syntax error, unexpected ',', expecting '}'\n      5'b10_000: assign res = {24{dm_r_data [23]},dm_r_data [23:16]};\n                                                 ^\n%Error: data/full_repos/permissive/143286506/execute.v:121: syntax error, unexpected ',', expecting '}'\n      5'b11_000: assign res = {24{dm_r_data [31]},dm_r_data [31:24]};\n                                                 ^\n%Error: data/full_repos/permissive/143286506/execute.v:126: syntax error, unexpected ',', expecting '}'\n      5'b00_001: assign res = {16{dm_r_data [7]},dm_r_data [7:0],dm_r_data [15:8]};\n                                                ^\n%Error: data/full_repos/permissive/143286506/execute.v:127: syntax error, unexpected ',', expecting '}'\n      5'b01_001: assign res = {16{dm_r_data [15]},dm_r_data [15:8],dm_r_data [23:16]};\n                                                 ^\n%Error: data/full_repos/permissive/143286506/execute.v:128: syntax error, unexpected ',', expecting '}'\n      5'b10_001: assign res = {16{dm_r_data [23]},dm_r_data [23:16],dm_r_data [31:24]};\n                                                 ^\n%Error: data/full_repos/permissive/143286506/execute.v:143: syntax error, unexpected '(', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule (alures,memres,CSRres,lastres,selectop);\n        ^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module mem_access(clk,r1,r2,immi,imms,res,mainop,subop);
    input clk;
    input [31:0]r1;
    input [31:0]r2;
    input [31:0]immi;
    input [31:0]imms;

    input [2:0]mainop;
    input subop;

    output [31:0]res;
    wire [31:0]mem_address;
    wire [31:0]reg2;
    wire [31:0]dm_r_data;
    wire [4:0]selector;
    wire [3:0]dren;
    wire [3:0]storedren;
    assign mem_address = subop ? r1 + immi: r1 + imms;
    assign selector = {mem_address[1:0],mainop};
    case (selector)
      5'b00_000: assign reg2 = {24'd0,r2[7:0]};
      5'b01_000: assign reg2 = {16'd0,r2[7:0],8'd0};
      5'b10_000: assign reg2 = {8'd0,r2[7:0],16'd0};
      5'b11_000: assign reg2 = {r2[7:0],24'd0};
      5'b00_001: assign reg2 = {16'd0,r2[7:0],r2[15:8]};
      5'b01_001: assign reg2 = {8'd0,r2[7:0],r2[15:8].8'd0};
      5'b10_001: assign reg2 = {r2[7:0],r2[15:8],16'd0};
      default: assign reg2 = {r2[7:0],r2[15:8],r2[23:16],r2[31:24]};
    endcase
    case (selector)
      5'b00_000: assign storedren = 4'b1110;
      5'b01_000: assign storedren = 4'b1101;
      5'b10_000: assign storedren = 4'b1011;
      5'b11_000: assign storedren = 4'b0111;
      5'b00_001: assign storedren = 4'b1100;
      5'b01_001: assign storedren = 4'b1001;
      5'b10_001: assign storedren = 4'b0011;
      5'b00_010: assign storedren = 4'b0000;
      default: assign storedren = 4'b1111;
    endcase
    assign dren = subop?storecode:4'b1111;
    data_mem data_mem_body0(mem_address[31:2], clk, reg2[7:0], dren[0], dm_r_data [7:0]);
    data_mem data_mem_body1(mem_address[31:2], clk, reg2[15:8], dren[1], dm_r_data[15:8]);
    data_mem data_mem_body2(mem_address[31:2], clk, reg2[23:16], dren[2], dm_r_data[23:16]);
    data_mem data_mem_body3(mem_address[31:2], clk, reg2[31:24], dren[3], dm_r_data[31:24]);
    case (selector)
      5'b00_000: assign res = {24{dm_r_data [7]},dm_r_data [7:0]};
      5'b01_000: assign res = {24{dm_r_data [15]},dm_r_data [15:8]};
      5'b10_000: assign res = {24{dm_r_data [23]},dm_r_data [23:16]};
      5'b11_000: assign res = {24{dm_r_data [31]},dm_r_data [31:24]};
      5'b00_100: assign res = {24'd0,dm_r_data [7:0]};
      5'b01_100: assign res = {24'd0,dm_r_data [15:8]};
      5'b10_100: assign res = {24'd0,dm_r_data [23:16]};
      5'b11_100: assign res = {24'd0,dm_r_data [31:24]};
      5'b00_001: assign res = {16{dm_r_data [7]},dm_r_data [7:0],dm_r_data [15:8]};
      5'b01_001: assign res = {16{dm_r_data [15]},dm_r_data [15:8],dm_r_data [23:16]};
      5'b10_001: assign res = {16{dm_r_data [23]},dm_r_data [23:16],dm_r_data [31:24]};
      5'b00_101: assign res = {16'd0,dm_r_data [7:0],dm_r_data [15:8]};
      5'b01_101: assign res = {16'd0,dm_r_data [15:8],dm_r_data [23:16]};
      5'b10_101: assign res = {16'd0,dm_r_data [23:16],dm_r_data [31:24]};
      5'b00_010: assign res = {dm_r_data [7:0],dm_r_data [15:8],dm_r_data [23:16],dm_r_data [31:24]};
      default: assign res = 32'd0;
    endcase
endmodule
module mem_access(clk,r1,r2,immi,imms,res,mainop,subop);

    input clk;
    input [31:0]r1;
    input [31:0]r2;
    input [31:0]immi;
    input [31:0]imms;

    input [2:0]mainop;
    input subop;

    output [31:0]res;
    wire [31:0]mem_address;
    wire [31:0]reg2;
    wire [31:0]dm_r_data;
    wire [4:0]selector;
    wire [3:0]dren;
    wire [3:0]storedren;
    assign mem_address = subop ? r1 + immi: r1 + imms;
    assign selector = {mem_address[1:0],mainop};
    case (selector)
      5'b00_000: assign reg2 = {24'd0,r2[7:0]};
      5'b01_000: assign reg2 = {16'd0,r2[7:0],8'd0};
      5'b10_000: assign reg2 = {8'd0,r2[7:0],16'd0};
      5'b11_000: assign reg2 = {r2[7:0],24'd0};
      5'b00_001: assign reg2 = {16'd0,r2[7:0],r2[15:8]};
      5'b01_001: assign reg2 = {8'd0,r2[7:0],r2[15:8].8'd0};
      5'b10_001: assign reg2 = {r2[7:0],r2[15:8],16'd0};
      default: assign reg2 = {r2[7:0],r2[15:8],r2[23:16],r2[31:24]};
    endcase
    case (selector)
      5'b00_000: assign storedren = 4'b1110;
      5'b01_000: assign storedren = 4'b1101;
      5'b10_000: assign storedren = 4'b1011;
      5'b11_000: assign storedren = 4'b0111;
      5'b00_001: assign storedren = 4'b1100;
      5'b01_001: assign storedren = 4'b1001;
      5'b10_001: assign storedren = 4'b0011;
      5'b00_010: assign storedren = 4'b0000;
      default: assign storedren = 4'b1111;
    endcase
    assign dren = subop?storecode:4'b1111;
    data_mem data_mem_body0(mem_address[31:2], clk, reg2[7:0], dren[0], dm_r_data [7:0]);
    data_mem data_mem_body1(mem_address[31:2], clk, reg2[15:8], dren[1], dm_r_data[15:8]);
    data_mem data_mem_body2(mem_address[31:2], clk, reg2[23:16], dren[2], dm_r_data[23:16]);
    data_mem data_mem_body3(mem_address[31:2], clk, reg2[31:24], dren[3], dm_r_data[31:24]);
    case (selector)
      5'b00_000: assign res = {24{dm_r_data [7]},dm_r_data [7:0]};
      5'b01_000: assign res = {24{dm_r_data [15]},dm_r_data [15:8]};
      5'b10_000: assign res = {24{dm_r_data [23]},dm_r_data [23:16]};
      5'b11_000: assign res = {24{dm_r_data [31]},dm_r_data [31:24]};
      5'b00_100: assign res = {24'd0,dm_r_data [7:0]};
      5'b01_100: assign res = {24'd0,dm_r_data [15:8]};
      5'b10_100: assign res = {24'd0,dm_r_data [23:16]};
      5'b11_100: assign res = {24'd0,dm_r_data [31:24]};
      5'b00_001: assign res = {16{dm_r_data [7]},dm_r_data [7:0],dm_r_data [15:8]};
      5'b01_001: assign res = {16{dm_r_data [15]},dm_r_data [15:8],dm_r_data [23:16]};
      5'b10_001: assign res = {16{dm_r_data [23]},dm_r_data [23:16],dm_r_data [31:24]};
      5'b00_101: assign res = {16'd0,dm_r_data [7:0],dm_r_data [15:8]};
      5'b01_101: assign res = {16'd0,dm_r_data [15:8],dm_r_data [23:16]};
      5'b10_101: assign res = {16'd0,dm_r_data [23:16],dm_r_data [31:24]};
      5'b00_010: assign res = {dm_r_data [7:0],dm_r_data [15:8],dm_r_data [23:16],dm_r_data [31:24]};
      default: assign res = 32'd0;
    endcase
endmodule