data/full_repos/permissive/177039499/main.v
1: b'%Error: data/full_repos/permissive/177039499/main.v:11: Cannot find include file: pipeline-regs/IF-ID.v\n`include "pipeline-regs/IF-ID.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/177039499,data/full_repos/permissive/177039499/pipeline-regs/IF-ID.v\n             data/full_repos/permissive/177039499,data/full_repos/permissive/177039499/pipeline-regs/IF-ID.v.v\n             data/full_repos/permissive/177039499,data/full_repos/permissive/177039499/pipeline-regs/IF-ID.v.sv\n             pipeline-regs/IF-ID.v\n             pipeline-regs/IF-ID.v.v\n             pipeline-regs/IF-ID.v.sv\n             obj_dir/pipeline-regs/IF-ID.v\n             obj_dir/pipeline-regs/IF-ID.v.v\n             obj_dir/pipeline-regs/IF-ID.v.sv\n%Error: data/full_repos/permissive/177039499/main.v:12: Cannot find include file: pipeline-regs/ID-EX.v\n`include "pipeline-regs/ID-EX.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177039499/main.v:13: Cannot find include file: pipeline-regs/EX-MEM.v\n`include "pipeline-regs/EX-MEM.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177039499/main.v:14: Cannot find include file: pipeline-regs/MEM-WB.v\n`include "pipeline-regs/MEM-WB.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177039499/main.v:18: Cannot find include file: instruction-fetch/stage.v\n`include "instruction-fetch/stage.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177039499/main.v:19: Cannot find include file: instruction-decode/stage.v\n`include "instruction-decode/stage.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177039499/main.v:20: Cannot find include file: execution/stage.v\n`include "execution/stage.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177039499/main.v:21: Cannot find include file: memory/stage.v\n`include "memory/stage.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177039499/main.v:22: Cannot find include file: write-back/stage.v\n`include "write-back/stage.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177039499/main.v:26: Cannot find include file: hazard-unit.v\n`include "hazard-unit.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177039499/main.v:27: Cannot find include file: forward-unit.v\n`include "forward-unit.v" \n         ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n'
module datapath(
	input wire clk,
	input wire reset
);




	wire [31:0] IF_PC;
	wire [31:0] IF_inst;

	wire [31:0] IFID_PC;
	wire [31:0] IFID_inst;

	wire        ID_RegWrite;
    wire        ID_MemRead, ID_MemWrite;
    wire  [3:0] ID_ALUOp;
    wire        ID_NotEqual, ID_IsBranch;
    wire [31:0] ID_ALUVal1, ID_ALUVal2;
    wire [31:0] ID_regRead2;
    wire [31:0] ID_immediate;
    wire  [4:0] ID_rs, ID_rtOR0, ID_rdORrt;
	wire  [1:0] ID_PCSrc;
	wire [31:0] ID_jumpAddress;
	wire [31:0] ID_jumpReg;

	wire        IDEX_RegWrite;
    wire        IDEX_MemRead, IDEX_MemWrite;
    wire  [3:0] IDEX_ALUOp;
    wire        IDEX_NotEqual, IDEX_IsBranch;
	wire [31:0] IDEX_ALUVal1, IDEX_ALUVal2;
    wire [31:0] IDEX_regRead2;
    wire [31:0] IDEX_branchAddr;
    wire  [4:0] IDEX_src1, IDEX_src2, IDEX_dest;

	wire [31:0] EX_ALUResult;
	wire [31:0] EX_storeVal;
	wire        EX_BranchTaken;

	wire        EXMEM_RegWrite;
	wire        EXMEM_MemRead, EXMEM_MemWrite;
	wire [31:0] EXMEM_ALUResult;
	wire [31:0] EXMEM_storeVal;
	wire  [4:0] EXMEM_regWriteAddress;

	wire [31:0] MEM_readData;

	wire        MEMWB_RegWrite, MEMWB_MemRead;
	wire [31:0] MEMWB_ALUResult;
	wire [31:0] MEMWB_memReadData;
	wire  [4:0] MEMWB_regWriteAddress;

    wire [31:0] WB_writeData;

	wire        hazard;

    wire  [1:0] forwardA, forwardB, forwardC;



	stageIF stage_IF(clk, reset, hazard, ID_PCSrc, ID_jumpAddress, ID_jumpReg, EX_BranchTaken, IDEX_branchAddr,
		IF_PC, IF_inst);



	rIFID reg_IFID(clk, reset, EX_BranchTaken, hazard, IF_PC, IF_inst,
		IFID_PC, IFID_inst);



	stageID stage_ID(clk, reset, hazard, IFID_PC, IFID_inst, MEMWB_RegWrite, MEMWB_regWriteAddress, WB_writeData, 
		ID_RegWrite, ID_MemRead, ID_MemWrite, ID_ALUOp, ID_NotEqual, ID_IsBranch, ID_ALUVal1, ID_ALUVal2,
		ID_regRead2, ID_immediate, ID_rs, ID_rtOR0, ID_rdORrt, ID_PCSrc, ID_jumpAddress, ID_jumpReg);



	rIDEX reg_IDEX(clk, reset, ID_RegWrite, ID_MemRead, ID_MemWrite, ID_ALUOp, ID_NotEqual, ID_IsBranch,
		ID_ALUVal1, ID_ALUVal2, ID_regRead2, ID_immediate, ID_rs, ID_rtOR0, ID_rdORrt,
		IDEX_RegWrite, IDEX_MemRead, IDEX_MemWrite, IDEX_ALUOp, IDEX_NotEqual, IDEX_IsBranch,
		IDEX_ALUVal1, IDEX_ALUVal2, IDEX_regRead2, IDEX_branchAddr, IDEX_src1, IDEX_src2, IDEX_dest);



	stageEX stage_EX(IDEX_ALUOp, IDEX_NotEqual, IDEX_IsBranch, IDEX_ALUVal1, IDEX_ALUVal2, IDEX_regRead2,
		EXMEM_ALUResult, WB_writeData, forwardA, forwardB, forwardC,
		EX_ALUResult, EX_storeVal, EX_BranchTaken);



	rEXMEM reg_EXMEM(clk, reset, IDEX_RegWrite, IDEX_MemRead, IDEX_MemWrite, EX_ALUResult, EX_storeVal, IDEX_dest,
		EXMEM_RegWrite, EXMEM_MemRead, EXMEM_MemWrite, EXMEM_ALUResult, EXMEM_storeVal, EXMEM_regWriteAddress);



	stageMEM stage_MEM(clk, reset, EXMEM_MemWrite, EXMEM_ALUResult, EXMEM_storeVal,
		MEM_readData);



	rMEMWB reg_MEMWB(clk, reset, EXMEM_RegWrite, EXMEM_MemRead, EXMEM_ALUResult, MEM_readData, EXMEM_regWriteAddress,
		MEMWB_RegWrite, MEMWB_MemRead, MEMWB_ALUResult, MEMWB_memReadData, MEMWB_regWriteAddress);



	stageWB stage_WB(MEMWB_MemRead, MEMWB_ALUResult, MEMWB_memReadData,
		WB_writeData);



	hazardUnit hazardDet(IDEX_MemRead, IFID_inst[25:21], IFID_inst[20:16], IDEX_dest,
		hazard);



	forwardingUnit forward(IDEX_src1, IDEX_src2, IDEX_dest, EXMEM_RegWrite, EXMEM_regWriteAddress,
		MEMWB_RegWrite, MEMWB_regWriteAddress,
		forwardA, forwardB, forwardC);

endmodule
module datapath(
	input wire clk,
	input wire reset
);





	wire [31:0] IF_PC;
	wire [31:0] IF_inst;

	wire [31:0] IFID_PC;
	wire [31:0] IFID_inst;

	wire        ID_RegWrite;
    wire        ID_MemRead, ID_MemWrite;
    wire  [3:0] ID_ALUOp;
    wire        ID_NotEqual, ID_IsBranch;
    wire [31:0] ID_ALUVal1, ID_ALUVal2;
    wire [31:0] ID_regRead2;
    wire [31:0] ID_immediate;
    wire  [4:0] ID_rs, ID_rtOR0, ID_rdORrt;
	wire  [1:0] ID_PCSrc;
	wire [31:0] ID_jumpAddress;
	wire [31:0] ID_jumpReg;

	wire        IDEX_RegWrite;
    wire        IDEX_MemRead, IDEX_MemWrite;
    wire  [3:0] IDEX_ALUOp;
    wire        IDEX_NotEqual, IDEX_IsBranch;
	wire [31:0] IDEX_ALUVal1, IDEX_ALUVal2;
    wire [31:0] IDEX_regRead2;
    wire [31:0] IDEX_branchAddr;
    wire  [4:0] IDEX_src1, IDEX_src2, IDEX_dest;

	wire [31:0] EX_ALUResult;
	wire [31:0] EX_storeVal;
	wire        EX_BranchTaken;

	wire        EXMEM_RegWrite;
	wire        EXMEM_MemRead, EXMEM_MemWrite;
	wire [31:0] EXMEM_ALUResult;
	wire [31:0] EXMEM_storeVal;
	wire  [4:0] EXMEM_regWriteAddress;

	wire [31:0] MEM_readData;

	wire        MEMWB_RegWrite, MEMWB_MemRead;
	wire [31:0] MEMWB_ALUResult;
	wire [31:0] MEMWB_memReadData;
	wire  [4:0] MEMWB_regWriteAddress;

    wire [31:0] WB_writeData;

	wire        hazard;

    wire  [1:0] forwardA, forwardB, forwardC;



	stageIF stage_IF(clk, reset, hazard, ID_PCSrc, ID_jumpAddress, ID_jumpReg, EX_BranchTaken, IDEX_branchAddr,
		IF_PC, IF_inst);



	rIFID reg_IFID(clk, reset, EX_BranchTaken, hazard, IF_PC, IF_inst,
		IFID_PC, IFID_inst);



	stageID stage_ID(clk, reset, hazard, IFID_PC, IFID_inst, MEMWB_RegWrite, MEMWB_regWriteAddress, WB_writeData, 
		ID_RegWrite, ID_MemRead, ID_MemWrite, ID_ALUOp, ID_NotEqual, ID_IsBranch, ID_ALUVal1, ID_ALUVal2,
		ID_regRead2, ID_immediate, ID_rs, ID_rtOR0, ID_rdORrt, ID_PCSrc, ID_jumpAddress, ID_jumpReg);



	rIDEX reg_IDEX(clk, reset, ID_RegWrite, ID_MemRead, ID_MemWrite, ID_ALUOp, ID_NotEqual, ID_IsBranch,
		ID_ALUVal1, ID_ALUVal2, ID_regRead2, ID_immediate, ID_rs, ID_rtOR0, ID_rdORrt,
		IDEX_RegWrite, IDEX_MemRead, IDEX_MemWrite, IDEX_ALUOp, IDEX_NotEqual, IDEX_IsBranch,
		IDEX_ALUVal1, IDEX_ALUVal2, IDEX_regRead2, IDEX_branchAddr, IDEX_src1, IDEX_src2, IDEX_dest);



	stageEX stage_EX(IDEX_ALUOp, IDEX_NotEqual, IDEX_IsBranch, IDEX_ALUVal1, IDEX_ALUVal2, IDEX_regRead2,
		EXMEM_ALUResult, WB_writeData, forwardA, forwardB, forwardC,
		EX_ALUResult, EX_storeVal, EX_BranchTaken);



	rEXMEM reg_EXMEM(clk, reset, IDEX_RegWrite, IDEX_MemRead, IDEX_MemWrite, EX_ALUResult, EX_storeVal, IDEX_dest,
		EXMEM_RegWrite, EXMEM_MemRead, EXMEM_MemWrite, EXMEM_ALUResult, EXMEM_storeVal, EXMEM_regWriteAddress);



	stageMEM stage_MEM(clk, reset, EXMEM_MemWrite, EXMEM_ALUResult, EXMEM_storeVal,
		MEM_readData);



	rMEMWB reg_MEMWB(clk, reset, EXMEM_RegWrite, EXMEM_MemRead, EXMEM_ALUResult, MEM_readData, EXMEM_regWriteAddress,
		MEMWB_RegWrite, MEMWB_MemRead, MEMWB_ALUResult, MEMWB_memReadData, MEMWB_regWriteAddress);



	stageWB stage_WB(MEMWB_MemRead, MEMWB_ALUResult, MEMWB_memReadData,
		WB_writeData);



	hazardUnit hazardDet(IDEX_MemRead, IFID_inst[25:21], IFID_inst[20:16], IDEX_dest,
		hazard);



	forwardingUnit forward(IDEX_src1, IDEX_src2, IDEX_dest, EXMEM_RegWrite, EXMEM_regWriteAddress,
		MEMWB_RegWrite, MEMWB_regWriteAddress,
		forwardA, forwardB, forwardC);

endmodule