data/full_repos/permissive/143278/ivltests/dffsynth7.v
1: b'%Error: data/full_repos/permissive/143278/ivltests/dffsynth7.v:20: Unsupported or unknown PLI call: $monitor\n  $monitor("%b %b %b %b", rst, clk, d, q);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth7.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth7.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth7.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth7.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth7.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth7.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth7.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth7.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth7.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth7.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dff();

reg clk;
reg rst;
reg ce;
reg [3:0] d;
reg [3:0] q;

always @(negedge clk or posedge rst) begin
  if (rst)
    q <= 4'b1001;
  else if (ce)
    q <= d;
end

(* ivl_synthesis_off *)
reg failed = 0;

initial begin
  $monitor("%b %b %b %b", rst, clk, d, q);
  clk = 1'b0;
  ce  = 1'b0;
  rst = 1'b0;
  d = 4'b0110;
  #1;
  if (q !== 4'bxxxx) failed = 1;
  rst = 1'b1;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b1;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b0;
  #1;
  if (q !== 4'b1001) failed = 1;
  rst = 1'b0;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b1;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b0;
  #1;
  if (q !== 4'b1001) failed = 1;
  ce  = 1'b1;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b1;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b0;
  #1;
  if (q !== 4'b0110) failed = 1;
  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module dff();


reg clk;
reg rst;
reg ce;
reg [3:0] d;
reg [3:0] q;

always @(negedge clk or posedge rst) begin
  if (rst)
    q <= 4'b1001;
  else if (ce)
    q <= d;
end

(* ivl_synthesis_off *)
reg failed = 0;

initial begin
  $monitor("%b %b %b %b", rst, clk, d, q);
  clk = 1'b0;
  ce  = 1'b0;
  rst = 1'b0;
  d = 4'b0110;
  #1;
  if (q !== 4'bxxxx) failed = 1;
  rst = 1'b1;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b1;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b0;
  #1;
  if (q !== 4'b1001) failed = 1;
  rst = 1'b0;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b1;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b0;
  #1;
  if (q !== 4'b1001) failed = 1;
  ce  = 1'b1;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b1;
  #1;
  if (q !== 4'b1001) failed = 1;
  clk = 1'b0;
  #1;
  if (q !== 4'b0110) failed = 1;
  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule