data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/18b7845a-9e76-429b-a6aa-f3fe68a91cb6.xml
module counter(clk_counter, q_counter, rst_counter);

    input clk_counter;
    input rst_counter;
    output [7:0] q_counter;
    reg [7:0] q_counter;

    initial begin
      q_counter <= 0;
    end

    always @ (posedge clk_counter)
    begin
        if(rst_counter)
		q_counter <= 8'b00000000;
	else
		q_counter <= q_counter + 1;
    end

endmodule
module counter(clk_counter, q_counter, rst_counter);


    input clk_counter;
    input rst_counter;
    output [7:0] q_counter;
    reg [7:0] q_counter;

    initial begin
      q_counter <= 0;
    end

    always @ (posedge clk_counter)
    begin
        if(rst_counter)
		q_counter <= 8'b00000000;
	else
		q_counter <= q_counter + 1;
    end

endmodule