data/full_repos/permissive/139767240/IntelReferenceDesign/moore_mac.v
data/verilator_xmls/0a33f794-7cae-4758-b10a-4190400c13bc.xml
module moore_mac
(
	input	clk, data_in, reset,
	output reg [1:0] data_out
);
	

	reg		[1:0]state;
	

	parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
	

	always @ (state) begin
		case (state)
			S0:
				data_out = 2'b01;
			S1:
				data_out = 2'b10;
			S2:
				data_out = 2'b11;
			S3:
				data_out = 2'b00;
			default:
				data_out = 2'b00;
		endcase
	end
	

	always @ (posedge clk or posedge reset) begin
		if (reset)
			state <= S0;
		else
			case (state)
				S0:
					state <= S1;
				S1:
					if (data_in)
						state <= S2;
					else
						state <= S1;
				S2:
					if (data_in)
						state <= S3;
					else
						state <= S1;
				S3:
					if (data_in)
						state <= S2;
					else
						state <= S3;
			endcase
	end
	
endmodule
module moore_mac
(
	input	clk, data_in, reset,
	output reg [1:0] data_out
);

	

	reg		[1:0]state;
	

	parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
	

	always @ (state) begin
		case (state)
			S0:
				data_out = 2'b01;
			S1:
				data_out = 2'b10;
			S2:
				data_out = 2'b11;
			S3:
				data_out = 2'b00;
			default:
				data_out = 2'b00;
		endcase
	end
	

	always @ (posedge clk or posedge reset) begin
		if (reset)
			state <= S0;
		else
			case (state)
				S0:
					state <= S1;
				S1:
					if (data_in)
						state <= S2;
					else
						state <= S1;
				S2:
					if (data_in)
						state <= S3;
					else
						state <= S1;
				S3:
					if (data_in)
						state <= S2;
					else
						state <= S3;
			endcase
	end
	
endmodule