data/full_repos/permissive/212394344/ExecutionBlock_TB.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:138: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:198: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:204: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:210: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:216: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:222: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:228: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:234: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:236: Unsupported: Ignoring delay on this delayed statement.\n  #600;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:244: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:246: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Error: data/full_repos/permissive/212394344/ExecutionBlock_TB.v:42: Cannot find file containing module: \'ExecutionBlock\'\n ExecutionBlock uut (\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/ExecutionBlock\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/ExecutionBlock.v\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/ExecutionBlock.sv\n             ExecutionBlock\n             ExecutionBlock.v\n             ExecutionBlock.sv\n             obj_dir/ExecutionBlock\n             obj_dir/ExecutionBlock.v\n             obj_dir/ExecutionBlock.sv\n%Error: Exiting due to 1 error(s), 33 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ExecutionBlock_TB;


	reg [7:0] A;
	reg [7:0] B;
	reg [7:0] data_in;
	reg [4:0] op_dec;
	reg clk;
	reg reset;


	wire [7:0] ans_ex;
	wire [7:0] DM_data;
	wire [7:0] data_out;
	wire [3:0] flag_ex;


	ExecutionBlock uut (
		.ans_ex(ans_ex), 
		.DM_data(DM_data), 
		.data_out(data_out), 
		.flag_ex(flag_ex), 
		.A(A), 
		.B(B), 
		.data_in(data_in), 
		.op_dec(op_dec), 
		.clk(clk), 
		.reset(reset)
	);

	initial begin
		
		
		
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00010;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01010;
		#1000;
	
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b11000;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11001;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11010;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11011;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11100;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11101;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11110;
		#1000;
        
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11111;
		#1000;
		
	end
	
	initial begin
		reset=1;
		#200;
		reset=0;
		#600;
		reset=1;
	end
	
	always
	begin
		
		clk = 1'b0;
		#1000;
		clk = 1'b1;
		#1000;
	end
      
endmodule
module ExecutionBlock_TB;



	reg [7:0] A;
	reg [7:0] B;
	reg [7:0] data_in;
	reg [4:0] op_dec;
	reg clk;
	reg reset;


	wire [7:0] ans_ex;
	wire [7:0] DM_data;
	wire [7:0] data_out;
	wire [3:0] flag_ex;


	ExecutionBlock uut (
		.ans_ex(ans_ex), 
		.DM_data(DM_data), 
		.data_out(data_out), 
		.flag_ex(flag_ex), 
		.A(A), 
		.B(B), 
		.data_in(data_in), 
		.op_dec(op_dec), 
		.clk(clk), 
		.reset(reset)
	);

	initial begin
		
		
		
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00010;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b00111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01010;
		#1000;
	
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b01111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10000;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10001;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10100;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10101;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10110;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b10111;
		#1000;
		
		A = 64;
		B = 192;
		data_in = 8;
		op_dec = 5'b11000;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11001;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11010;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11011;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11100;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11101;
		#1000;
		
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11110;
		#1000;
        
		A = 192;
		B = 1;
		data_in = 8;
		op_dec = 5'b11111;
		#1000;
		
	end
	
	initial begin
		reset=1;
		#200;
		reset=0;
		#600;
		reset=1;
	end
	
	always
	begin
		
		clk = 1'b0;
		#1000;
		clk = 1'b1;
		#1000;
	end
      
endmodule