data/full_repos/permissive/211316121/lab7_1_nexys4/Traffic.v
data/verilator_xmls/ca577149-9261-4fa3-876c-03fa47d393ac.xml
module Traffic_Top(
    input CLK100MHZ,
    input [1:0] SW,
    output [5:0] LED
    );
    wire clr=SW[0];
    wire resetDIV;
    wire resetTRA=SW[1];
    wire oneSec,sec5,sec10;
    
    oneSecond top_1s(CLK100MHZ,clr,oneSec);
    
    clkdiv top_15_45(oneSec,resetDIV,sec5,sec10);
    
    Traffic top_tra(sec5,sec10,oneSec,resetTRA,LED,resetDIV);
    
endmodule
module Traffic_Top(
    input CLK100MHZ,
    input [1:0] SW,
    output [5:0] LED
    );

    wire clr=SW[0];
    wire resetDIV;
    wire resetTRA=SW[1];
    wire oneSec,sec5,sec10;
    
    oneSecond top_1s(CLK100MHZ,clr,oneSec);
    
    clkdiv top_15_45(oneSec,resetDIV,sec5,sec10);
    
    Traffic top_tra(sec5,sec10,oneSec,resetTRA,LED,resetDIV);
    
endmodule