data/full_repos/permissive/168846058/01_Test/Display_Test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/168846058/01_Test/Display_Test.v:16: Unsupported: Ignoring delay on this delayed statement.\n    always #0.01 clk = ~clk;  \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/168846058/01_Test/Display_Test.v:18: Unsupported: Ignoring delay on this delayed statement.\n        data = 32\'hfedc_ba98; #500;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/168846058/01_Test/Display_Test.v:19: Unsupported: Ignoring delay on this delayed statement.\n        data = 32\'h7654_3210; #500;\n                              ^\n%Error: data/full_repos/permissive/168846058/01_Test/Display_Test.v:12: Cannot find file containing module: \'Display\'\n    Display Display_Instance(.clk(clk), .data(data),\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/168846058/01_Test,data/full_repos/permissive/168846058/Display\n             data/full_repos/permissive/168846058/01_Test,data/full_repos/permissive/168846058/Display.v\n             data/full_repos/permissive/168846058/01_Test,data/full_repos/permissive/168846058/Display.sv\n             Display\n             Display.v\n             Display.sv\n             obj_dir/Display\n             obj_dir/Display.v\n             obj_dir/Display.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Display_Test();
    reg clk = 0;
    reg [32:1] data;
    wire [2:0] which;
    wire [7:0] seg;
    wire [10:0] count;
    wire [3:0] digit;


    Display Display_Instance(.clk(clk), .data(data),
        .which(which), .seg(seg),
        .count(count), .digit(digit));

    always #0.01 clk = ~clk;
    initial begin
        data = 32'hfedc_ba98; #500;
        data = 32'h7654_3210; #500;
    end

endmodule
module Display_Test();

    reg clk = 0;
    reg [32:1] data;
    wire [2:0] which;
    wire [7:0] seg;
    wire [10:0] count;
    wire [3:0] digit;


    Display Display_Instance(.clk(clk), .data(data),
        .which(which), .seg(seg),
        .count(count), .digit(digit));

    always #0.01 clk = ~clk;
    initial begin
        data = 32'hfedc_ba98; #500;
        data = 32'h7654_3210; #500;
    end

endmodule