data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:97: Cannot find include file: pci_constants.v\n`include "pci_constants.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v.sv\n             pci_constants.v\n             pci_constants.v.v\n             pci_constants.v.sv\n             obj_dir/pci_constants.v\n             obj_dir/pci_constants.v.v\n             obj_dir/pci_constants.v.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:100: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:255: Define or directive not defined: \'`WBW_DEPTH\'\nparameter WBW_DEPTH = `WBW_DEPTH ;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:255: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter WBW_DEPTH = `WBW_DEPTH ;\n                                 ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:256: Define or directive not defined: \'`WBW_ADDR_LENGTH\'\nparameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;\n                            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:256: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;\n                                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:257: Define or directive not defined: \'`WBR_DEPTH\'\nparameter WBR_DEPTH = `WBR_DEPTH ;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:257: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter WBR_DEPTH = `WBR_DEPTH ;\n                                 ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:258: Define or directive not defined: \'`WBR_ADDR_LENGTH\'\nparameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;\n                            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:258: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;\n                                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:299: Define or directive not defined: \'`LAST_CTRL_BIT\'\nwire wbw_last_in  = wbw_control_in[`LAST_CTRL_BIT]  ;\n                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:299: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire wbw_last_in  = wbw_control_in[`LAST_CTRL_BIT]  ;\n                                                 ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:300: Define or directive not defined: \'`LAST_CTRL_BIT\'\nwire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:300: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;\n                                                  ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:435: Define or directive not defined: \'`WB_FIFO_RAM_ADDR_LENGTH\'\n    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1\'b0}} ;\n           ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:435: Define or directive not defined: \'`WB_FIFO_RAM_ADDR_LENGTH\'\n    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1\'b0}} ;\n                                                                                   ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:436: Define or directive not defined: \'`WB_FIFO_RAM_ADDR_LENGTH\'\n    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1\'b1}} ;\n           ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:436: Define or directive not defined: \'`WB_FIFO_RAM_ADDR_LENGTH\'\n    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1\'b1}} ;\n                                                                                   ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:444: Define or directive not defined: \'`WB_FIFO_RAM_ADDR_LENGTH\'\n    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;\n           ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:450: Define or directive not defined: \'`WB_FIFO_RAM_ADDR_LENGTH\'\n    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr  = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;\n           ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:457: Define or directive not defined: \'`WB_FIFO_RAM_ADDR_LENGTH\'\n    pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage\n                   ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:559: Define or directive not defined: \'`FF_DELAY\'\n        pci_clk_inGreyCount <= #`FF_DELAY 0 ;\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:559: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        pci_clk_inGreyCount <= #`FF_DELAY 0 ;\n                                            ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:561: Define or directive not defined: \'`FF_DELAY\'\n        pci_clk_inGreyCount <= # `FF_DELAY pci_clk_sync_inGreyCount ;\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:561: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        pci_clk_inGreyCount <= # `FF_DELAY pci_clk_sync_inGreyCount ;\n                                                                    ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:569: Define or directive not defined: \'`FF_DELAY\'\n        outGreyCount <= #`FF_DELAY 0 ;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:569: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        outGreyCount <= #`FF_DELAY 0 ;\n                                     ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:573: Define or directive not defined: \'`FF_DELAY\'\n        outGreyCount <= #`FF_DELAY outNextGreyCount ;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:573: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        outGreyCount <= #`FF_DELAY outNextGreyCount ;\n                                                    ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:580: Define or directive not defined: \'`FF_DELAY\'\n        wbw_inTransactionCount <= #`FF_DELAY 1 ;\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:580: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        wbw_inTransactionCount <= #`FF_DELAY 1 ;\n                                               ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:583: Define or directive not defined: \'`FF_DELAY\'\n        wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1\'b1 ;\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wbw_wbr_fifos.v:593: Define or directive not defined: \'`FF_DELAY\'\n        wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1\'b1 ;\n                                    ^~~~~~~~~\n%Error: Exiting due to 33 error(s)\n'
module pci_wbw_wbr_fifos
(
    wb_clock_in,
    pci_clock_in,
    reset_in,
    wbw_wenable_in,
    wbw_addr_data_in,
    wbw_cbe_in,
    wbw_control_in,
    wbw_renable_in,
    wbw_addr_data_out,
    wbw_cbe_out,
    wbw_control_out,

    wbw_almost_full_out,
    wbw_full_out,
    wbw_empty_out,
    wbw_transaction_ready_out,
    wbr_wenable_in,
    wbr_data_in,
    wbr_be_in,
    wbr_control_in,
    wbr_renable_in,
    wbr_data_out,
    wbr_be_out,
    wbr_control_out,
    wbr_flush_in,
    wbr_empty_out

`ifdef PCI_BIST
    ,

    mbist_si_i,
    mbist_so_o,
    mbist_ctrl_i
`endif                        
) ;


input wb_clock_in, pci_clock_in, reset_in ;



input        wbw_wenable_in ;
input [31:0] wbw_addr_data_in ;
input [3:0]  wbw_cbe_in ;
input [3:0]  wbw_control_in ;


input         wbw_renable_in ;
output [31:0] wbw_addr_data_out ;
output [3:0]  wbw_cbe_out ;
output [3:0]  wbw_control_out ;





output wbw_almost_full_out ;
output wbw_full_out ;
output wbw_empty_out ;
output wbw_transaction_ready_out ;



input        wbr_wenable_in ;
input [31:0] wbr_data_in ;
input [3:0]  wbr_be_in ;
input [3:0]  wbr_control_in ;


input         wbr_renable_in ;
output [31:0] wbr_data_out ;
output [3:0]  wbr_be_out ;
output [3:0]  wbr_control_out ;


input wbr_flush_in ;

output wbr_empty_out ;

`ifdef PCI_BIST

input   mbist_si_i;
output  mbist_so_o;
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
`endif


parameter WBW_DEPTH = `WBW_DEPTH ;
parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
parameter WBR_DEPTH = `WBR_DEPTH ;
parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;


wire wbw_wallow ;
wire wbw_rallow ;


wire wbr_wallow ;
wire wbr_rallow ;


wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;


wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;


reg [(WBW_ADDR_LENGTH - 2):0] wbw_inTransactionCount ;
reg [(WBW_ADDR_LENGTH - 2):0] wbw_outTransactionCount ;


wire wbw_last_in  = wbw_control_in[`LAST_CTRL_BIT]  ;
wire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;

wire wbw_empty ;
wire wbr_empty ;

assign wbw_empty_out = wbw_empty ;
assign wbr_empty_out = wbr_empty ;


wire wbw_clear = reset_in;
wire wbr_clear = reset_in;


wire [39:0] dpram_portA_output ;
wire [39:0] dpram_portB_output ;

wire [39:0] dpram_portA_input = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
wire [39:0] dpram_portB_input = {wbr_control_in, wbr_be_in, wbr_data_in} ;


assign wbw_control_out = dpram_portB_output[39:36] ;
assign wbr_control_out = dpram_portA_output[39:36] ;

assign wbw_cbe_out     = dpram_portB_output[35:32] ;
assign wbr_be_out      = dpram_portA_output[35:32] ;

assign wbw_addr_data_out = dpram_portB_output[31:0] ;
assign wbr_data_out      = dpram_portA_output[31:0] ;

`ifdef WB_RAM_DONT_SHARE







    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_waddr = wbw_waddr ;
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_raddr = wbw_raddr ;

    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_waddr = wbr_waddr ;
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;

    wire wbw_read_enable = 1'b1 ;
    wire wbr_read_enable = 1'b1 ;

    `ifdef PCI_BIST
    wire mbist_so_o_internal ;
    wire mbist_si_i_internal = mbist_so_o_internal ;
    `endif


    pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
    (

        .clk_a(wb_clock_in),
        .rst_a(reset_in),
        .ce_a(1'b1),
        .we_a(wbw_wallow),
        .oe_a(1'b1),
        .addr_a(wbw_whole_waddr),
        .di_a(dpram_portA_input),
        .do_a(),

        .clk_b(pci_clock_in),
        .rst_b(reset_in),
        .ce_b(wbw_read_enable),
        .we_b(1'b0),
        .oe_b(1'b1),
        .addr_b(wbw_whole_raddr),
        .di_b(40'h00_0000_0000),
        .do_b(dpram_portB_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o_internal),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

    pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
    (

        .clk_a(pci_clock_in),
        .rst_a(reset_in),
        .ce_a(1'b1),
        .we_a(wbr_wallow),
        .oe_a(1'b1),
        .addr_a(wbr_whole_waddr),
        .di_a(dpram_portB_input),
        .do_a(),

        .clk_b(wb_clock_in),
        .rst_b(reset_in),
        .ce_b(wbr_read_enable),
        .we_b(1'b0),
        .oe_b(1'b1),
        .addr_b(wbr_whole_raddr),
        .di_b(40'h00_0000_0000),
        .do_b(dpram_portA_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i_internal),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

`else



    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b1}} ;


    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;


    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr  = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;

    wire portA_enable      = 1'b1 ;

    wire portB_enable      = 1'b1 ;


    pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage
    (

        .clk_a(wb_clock_in),
        .rst_a(reset_in),
        .ce_a(portA_enable),
        .we_a(wbw_wallow),
        .oe_a(1'b1),
        .addr_a(portA_addr),
        .di_a(dpram_portA_input),
        .do_a(dpram_portA_output),
        .clk_b(pci_clock_in),
        .rst_b(reset_in),
        .ce_b(portB_enable),
        .we_b(wbr_wallow),
        .oe_b(1'b1),
        .addr_b(portB_addr),
        .di_b(dpram_portB_input),
        .do_b(dpram_portB_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

`endif


pci_wbw_fifo_control #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
(
    .rclock_in(pci_clock_in),
    .wclock_in(wb_clock_in),
    .renable_in(wbw_renable_in),
    .wenable_in(wbw_wenable_in),
    .reset_in(reset_in),

    .almost_full_out(wbw_almost_full_out),
    .full_out(wbw_full_out),
    .empty_out(wbw_empty),
    .waddr_out(wbw_waddr),
    .raddr_out(wbw_raddr),
    .rallow_out(wbw_rallow),
    .wallow_out(wbw_wallow)
);

pci_wbr_fifo_control #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
(   .rclock_in(wb_clock_in),
    .wclock_in(pci_clock_in),
    .renable_in(wbr_renable_in),
    .wenable_in(wbr_wenable_in),
    .reset_in(reset_in),
    .flush_in(wbr_flush_in),
    .empty_out(wbr_empty),
    .waddr_out(wbr_waddr),
    .raddr_out(wbr_raddr),
    .rallow_out(wbr_rallow),
    .wallow_out(wbr_wallow)
);



reg  [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
reg  [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;


wire in_count_en  = wbw_wallow && wbw_last_in ;


wire out_count_en = wbw_renable_in && wbw_last_out ;


always@(posedge wb_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
    begin
        inGreyCount <= #3 0 ;
    end
    else
    if (in_count_en)
        inGreyCount <= #3 inNextGreyCount ;
end

wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
reg  [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ;
pci_synchronizer_flop #((WBW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
(
    .data_in        (inGreyCount),
    .clk_out        (pci_clock_in),
    .sync_data_out  (pci_clk_sync_inGreyCount),
    .async_reset    (wbw_clear)
) ;

always@(posedge pci_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
        pci_clk_inGreyCount <= #`FF_DELAY 0 ;
    else
        pci_clk_inGreyCount <= # `FF_DELAY pci_clk_sync_inGreyCount ;
end


always@(posedge pci_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
    begin
        outGreyCount <= #`FF_DELAY 0 ;
    end
    else
    if (out_count_en)
        outGreyCount <= #`FF_DELAY outNextGreyCount ;
end


always@(posedge wb_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
        wbw_inTransactionCount <= #`FF_DELAY 1 ;
    else
    if (in_count_en)
        wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
end


always@(posedge pci_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
        wbw_outTransactionCount <= 1 ;
    else
    if (out_count_en)
        wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
end

assign wbw_transaction_ready_out = pci_clk_inGreyCount != outGreyCount ;

endmodule
module pci_wbw_wbr_fifos
(
    wb_clock_in,
    pci_clock_in,
    reset_in,
    wbw_wenable_in,
    wbw_addr_data_in,
    wbw_cbe_in,
    wbw_control_in,
    wbw_renable_in,
    wbw_addr_data_out,
    wbw_cbe_out,
    wbw_control_out,

    wbw_almost_full_out,
    wbw_full_out,
    wbw_empty_out,
    wbw_transaction_ready_out,
    wbr_wenable_in,
    wbr_data_in,
    wbr_be_in,
    wbr_control_in,
    wbr_renable_in,
    wbr_data_out,
    wbr_be_out,
    wbr_control_out,
    wbr_flush_in,
    wbr_empty_out

`ifdef PCI_BIST
    ,

    mbist_si_i,
    mbist_so_o,
    mbist_ctrl_i
`endif                        
) ;



input wb_clock_in, pci_clock_in, reset_in ;



input        wbw_wenable_in ;
input [31:0] wbw_addr_data_in ;
input [3:0]  wbw_cbe_in ;
input [3:0]  wbw_control_in ;


input         wbw_renable_in ;
output [31:0] wbw_addr_data_out ;
output [3:0]  wbw_cbe_out ;
output [3:0]  wbw_control_out ;





output wbw_almost_full_out ;
output wbw_full_out ;
output wbw_empty_out ;
output wbw_transaction_ready_out ;



input        wbr_wenable_in ;
input [31:0] wbr_data_in ;
input [3:0]  wbr_be_in ;
input [3:0]  wbr_control_in ;


input         wbr_renable_in ;
output [31:0] wbr_data_out ;
output [3:0]  wbr_be_out ;
output [3:0]  wbr_control_out ;


input wbr_flush_in ;

output wbr_empty_out ;

`ifdef PCI_BIST

input   mbist_si_i;
output  mbist_so_o;
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
`endif


parameter WBW_DEPTH = `WBW_DEPTH ;
parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
parameter WBR_DEPTH = `WBR_DEPTH ;
parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;


wire wbw_wallow ;
wire wbw_rallow ;


wire wbr_wallow ;
wire wbr_rallow ;


wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;


wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;


reg [(WBW_ADDR_LENGTH - 2):0] wbw_inTransactionCount ;
reg [(WBW_ADDR_LENGTH - 2):0] wbw_outTransactionCount ;


wire wbw_last_in  = wbw_control_in[`LAST_CTRL_BIT]  ;
wire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;

wire wbw_empty ;
wire wbr_empty ;

assign wbw_empty_out = wbw_empty ;
assign wbr_empty_out = wbr_empty ;


wire wbw_clear = reset_in;
wire wbr_clear = reset_in;


wire [39:0] dpram_portA_output ;
wire [39:0] dpram_portB_output ;

wire [39:0] dpram_portA_input = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
wire [39:0] dpram_portB_input = {wbr_control_in, wbr_be_in, wbr_data_in} ;


assign wbw_control_out = dpram_portB_output[39:36] ;
assign wbr_control_out = dpram_portA_output[39:36] ;

assign wbw_cbe_out     = dpram_portB_output[35:32] ;
assign wbr_be_out      = dpram_portA_output[35:32] ;

assign wbw_addr_data_out = dpram_portB_output[31:0] ;
assign wbr_data_out      = dpram_portA_output[31:0] ;

`ifdef WB_RAM_DONT_SHARE







    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_waddr = wbw_waddr ;
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_raddr = wbw_raddr ;

    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_waddr = wbr_waddr ;
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;

    wire wbw_read_enable = 1'b1 ;
    wire wbr_read_enable = 1'b1 ;

    `ifdef PCI_BIST
    wire mbist_so_o_internal ;
    wire mbist_si_i_internal = mbist_so_o_internal ;
    `endif


    pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
    (

        .clk_a(wb_clock_in),
        .rst_a(reset_in),
        .ce_a(1'b1),
        .we_a(wbw_wallow),
        .oe_a(1'b1),
        .addr_a(wbw_whole_waddr),
        .di_a(dpram_portA_input),
        .do_a(),

        .clk_b(pci_clock_in),
        .rst_b(reset_in),
        .ce_b(wbw_read_enable),
        .we_b(1'b0),
        .oe_b(1'b1),
        .addr_b(wbw_whole_raddr),
        .di_b(40'h00_0000_0000),
        .do_b(dpram_portB_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o_internal),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

    pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
    (

        .clk_a(pci_clock_in),
        .rst_a(reset_in),
        .ce_a(1'b1),
        .we_a(wbr_wallow),
        .oe_a(1'b1),
        .addr_a(wbr_whole_waddr),
        .di_a(dpram_portB_input),
        .do_a(),

        .clk_b(wb_clock_in),
        .rst_b(reset_in),
        .ce_b(wbr_read_enable),
        .we_b(1'b0),
        .oe_b(1'b1),
        .addr_b(wbr_whole_raddr),
        .di_b(40'h00_0000_0000),
        .do_b(dpram_portA_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i_internal),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

`else



    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b1}} ;


    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;


    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr  = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;

    wire portA_enable      = 1'b1 ;

    wire portB_enable      = 1'b1 ;


    pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage
    (

        .clk_a(wb_clock_in),
        .rst_a(reset_in),
        .ce_a(portA_enable),
        .we_a(wbw_wallow),
        .oe_a(1'b1),
        .addr_a(portA_addr),
        .di_a(dpram_portA_input),
        .do_a(dpram_portA_output),
        .clk_b(pci_clock_in),
        .rst_b(reset_in),
        .ce_b(portB_enable),
        .we_b(wbr_wallow),
        .oe_b(1'b1),
        .addr_b(portB_addr),
        .di_b(dpram_portB_input),
        .do_b(dpram_portB_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

`endif


pci_wbw_fifo_control #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
(
    .rclock_in(pci_clock_in),
    .wclock_in(wb_clock_in),
    .renable_in(wbw_renable_in),
    .wenable_in(wbw_wenable_in),
    .reset_in(reset_in),

    .almost_full_out(wbw_almost_full_out),
    .full_out(wbw_full_out),
    .empty_out(wbw_empty),
    .waddr_out(wbw_waddr),
    .raddr_out(wbw_raddr),
    .rallow_out(wbw_rallow),
    .wallow_out(wbw_wallow)
);

pci_wbr_fifo_control #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
(   .rclock_in(wb_clock_in),
    .wclock_in(pci_clock_in),
    .renable_in(wbr_renable_in),
    .wenable_in(wbr_wenable_in),
    .reset_in(reset_in),
    .flush_in(wbr_flush_in),
    .empty_out(wbr_empty),
    .waddr_out(wbr_waddr),
    .raddr_out(wbr_raddr),
    .rallow_out(wbr_rallow),
    .wallow_out(wbr_wallow)
);



reg  [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
reg  [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;


wire in_count_en  = wbw_wallow && wbw_last_in ;


wire out_count_en = wbw_renable_in && wbw_last_out ;


always@(posedge wb_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
    begin
        inGreyCount <= #3 0 ;
    end
    else
    if (in_count_en)
        inGreyCount <= #3 inNextGreyCount ;
end

wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
reg  [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ;
pci_synchronizer_flop #((WBW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
(
    .data_in        (inGreyCount),
    .clk_out        (pci_clock_in),
    .sync_data_out  (pci_clk_sync_inGreyCount),
    .async_reset    (wbw_clear)
) ;

always@(posedge pci_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
        pci_clk_inGreyCount <= #`FF_DELAY 0 ;
    else
        pci_clk_inGreyCount <= # `FF_DELAY pci_clk_sync_inGreyCount ;
end


always@(posedge pci_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
    begin
        outGreyCount <= #`FF_DELAY 0 ;
    end
    else
    if (out_count_en)
        outGreyCount <= #`FF_DELAY outNextGreyCount ;
end


always@(posedge wb_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
        wbw_inTransactionCount <= #`FF_DELAY 1 ;
    else
    if (in_count_en)
        wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
end


always@(posedge pci_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
        wbw_outTransactionCount <= 1 ;
    else
    if (out_count_en)
        wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
end

assign wbw_transaction_ready_out = pci_clk_inGreyCount != outGreyCount ;

endmodule