data/full_repos/permissive/188434311/verilog/csr/ctrl_state_reg.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/188434311/verilog/csr/ctrl_state_reg.v:62: Signal definition not found, creating implicitly: \'EMPTY_STATE_ADDR\'\nassign EMPTY_STATE_ADDR = { 30\'h0 , 2\'b0 };\n       ^~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/188434311/verilog/csr/ctrl_state_reg.v:63: Signal definition not found, creating implicitly: \'CFG_THRESHOLD_ADDR\'\nassign CFG_THRESHOLD_ADDR = { 30\'h1 , 2\'b0 };\n       ^~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/188434311/verilog/csr/ctrl_state_reg.v:71: Signal definition not found, creating implicitly: \'EMPTY_STATE_SEL\'\n                                                                                       : ... Suggested alternative: \'EMPTY_STATE_ADDR\'\nassign EMPTY_STATE_SEL = APB_WRITE & ( paddr ==EMPTY_STATE_ADDR ) ;\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/188434311/verilog/csr/ctrl_state_reg.v:93: Can\'t find definition of variable: \'empty_state_reg\'\n                                                                            : ... Suggested alternative: \'empty_state_sel\'\n    EMPTY_STATE_ADDR : prdata_i <= empty_state_reg ;\n                                   ^~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module ctrl_state_reg(

  input wire pclk,
  input wire preset_n,

  input  wire            psel,
  input  wire            penable,
  input  wire [ 31 : 0 ] paddr,
  input  wire            pwrite,


  input  wire [ 31 : 0 ] pwdata,
  output reg  [ 31 : 0 ] prdata,
  output reg             pready,
  output reg             pslverr,

  input  wire [ 15 : 0 ] empty_state ,
  output reg  [ 15 : 0 ] cfg_threshold

  );


localparam APB_WRITE = psel & pwrite ;
localparam APB_READ  = psel & ( ~ pwrite ) ;
localparam APB_OK    = 1'b0 ;
localparam APB_ERROR = 1'b1 ;


wire empty_state_sel ;
wire cfg_threshold_sel ;


reg [ 31 : 0 ] prdata_i; 
reg [ 31 : 0 ] cfg_threshold_reg ;

assign EMPTY_STATE_ADDR = { 30'h0 , 2'b0 };
assign CFG_THRESHOLD_ADDR = { 30'h1 , 2'b0 };



assign EMPTY_STATE_SEL = APB_WRITE & ( paddr ==EMPTY_STATE_ADDR ) ;
assign cfg_threshold_sel = APB_WRITE & ( paddr == CFG_THRESHOLD_ADDR ) ;





always @( * ) begin
  pready  <= 1'b1;
  pslverr <= APB_OK;
end

always @( posedge pclk or negedge preset_n )
  if( ~ preset_n ) begin
     cfg_threshold_reg <= 32'h0 ;
  end
  else begin
         cfg_threshold_reg <= cfg_threshold_sel ? { 16'h0 , pwdata[15:0] } : cfg_threshold_reg ;
end

always @( * )
  case( paddr )
    EMPTY_STATE_ADDR : prdata_i <= empty_state_reg ;
    CFG_THRESHOLD_ADDR : prdata_i <=  cfg_threshold_reg ;
    default : prdata_i <= 32'h0 ;
  endcase

always @( posedge pclk or negedge preset_n )
  if( ~ preset_n )
    prdata <= 32'h0 ;
  else if( APB_READ )
         prdata <= prdata_i ;



endmodule
module ctrl_state_reg(

  input wire pclk,
  input wire preset_n,

  input  wire            psel,
  input  wire            penable,
  input  wire [ 31 : 0 ] paddr,
  input  wire            pwrite,


  input  wire [ 31 : 0 ] pwdata,
  output reg  [ 31 : 0 ] prdata,
  output reg             pready,
  output reg             pslverr,

  input  wire [ 15 : 0 ] empty_state ,
  output reg  [ 15 : 0 ] cfg_threshold

  );



localparam APB_WRITE = psel & pwrite ;
localparam APB_READ  = psel & ( ~ pwrite ) ;
localparam APB_OK    = 1'b0 ;
localparam APB_ERROR = 1'b1 ;


wire empty_state_sel ;
wire cfg_threshold_sel ;


reg [ 31 : 0 ] prdata_i; 
reg [ 31 : 0 ] cfg_threshold_reg ;

assign EMPTY_STATE_ADDR = { 30'h0 , 2'b0 };
assign CFG_THRESHOLD_ADDR = { 30'h1 , 2'b0 };



assign EMPTY_STATE_SEL = APB_WRITE & ( paddr ==EMPTY_STATE_ADDR ) ;
assign cfg_threshold_sel = APB_WRITE & ( paddr == CFG_THRESHOLD_ADDR ) ;





always @( * ) begin
  pready  <= 1'b1;
  pslverr <= APB_OK;
end

always @( posedge pclk or negedge preset_n )
  if( ~ preset_n ) begin
     cfg_threshold_reg <= 32'h0 ;
  end
  else begin
         cfg_threshold_reg <= cfg_threshold_sel ? { 16'h0 , pwdata[15:0] } : cfg_threshold_reg ;
end

always @( * )
  case( paddr )
    EMPTY_STATE_ADDR : prdata_i <= empty_state_reg ;
    CFG_THRESHOLD_ADDR : prdata_i <=  cfg_threshold_reg ;
    default : prdata_i <= 32'h0 ;
  endcase

always @( posedge pclk or negedge preset_n )
  if( ~ preset_n )
    prdata <= 32'h0 ;
  else if( APB_READ )
         prdata <= prdata_i ;



endmodule