data/full_repos/permissive/123796236/reg32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123796236/reg32.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #100 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testreg32();

reg clk, reset;
reg	[31:0]	d_in;
wire [31:0] d_out;
reg32 r(clk, reset, d_in, d_out);

initial begin
		clk = 0;
		reset = 0;
		d_in = 32'hffffffff;
	end
always
	begin	
		#100 clk = ~clk;
	end
	

endmodule
module testreg32();


reg clk, reset;
reg	[31:0]	d_in;
wire [31:0] d_out;
reg32 r(clk, reset, d_in, d_out);

initial begin
		clk = 0;
		reset = 0;
		d_in = 32'hffffffff;
	end
always
	begin	
		#100 clk = ~clk;
	end
	

endmodule