data/full_repos/permissive/133245813/axi_shift_register/shift_register.v
data/verilator_xmls/18dc94f4-410a-4e8c-9ce3-fd9d6b708446.xml
module shift_register
    (
        input  wire       clk, rst_n,
        input  wire       dir, din, en,
        output wire [3:0] q
    );
    
    reg [3:0] sreg_cv, sreg_nv;
    
    always @(posedge clk)
    begin
        if (!rst_n)
            sreg_cv <= 0;
        else
            sreg_cv <= sreg_nv;
    end
    
    always @*
    begin
        sreg_nv = sreg_cv;
        if (en)
            if (!dir)
                sreg_nv = {sreg_cv[2:0], din}; 
            else
                sreg_nv = {din, sreg_cv[3:1]};
    end
    
    assign q = sreg_cv;
    
endmodule
module shift_register
    (
        input  wire       clk, rst_n,
        input  wire       dir, din, en,
        output wire [3:0] q
    );

    
    reg [3:0] sreg_cv, sreg_nv;
    
    always @(posedge clk)
    begin
        if (!rst_n)
            sreg_cv <= 0;
        else
            sreg_cv <= sreg_nv;
    end
    
    always @*
    begin
        sreg_nv = sreg_cv;
        if (en)
            if (!dir)
                sreg_nv = {sreg_cv[2:0], din}; 
            else
                sreg_nv = {din, sreg_cv[3:1]};
    end
    
    assign q = sreg_cv;
    
endmodule