data/full_repos/permissive/19572582/Lab2/lab2_part6.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part6.v:64: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] SSD;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part6.v:21: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part6.v:38: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 5 bits.\n                                                                        : ... In instance lab2_part6\n    S0 = T0 - Z0;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part6.v:40: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'c1\' generates 1 bits.\n                                                                        : ... In instance lab2_part6\n    T1 = SW[7:4] + SW[15:12] + c1;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part6.v:48: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 5 bits.\n                                                                        : ... In instance lab2_part6\n    S1 = T1 - Z1;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part6.v:49: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'c2\' generates 1 bits.\n                                                                        : ... In instance lab2_part6\n    S2 = c2;\n       ^\n%Error: Exiting due to 6 warning(s)\n'
module b2d_7seg (X, SSD);
  input [3:0] X;
  output [0:6] SSD;

  assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] & ~X[1] & ~X[0]));
  assign SSD[1] = ((~X[3] &  X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] &  X[1] & ~X[0]));
  assign SSD[2] =  (~X[3] & ~X[2] &  X[1] & ~X[0]);
  assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] & ~X[1] & ~X[0]) | (~X[3] &  X[2] & X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]));
  assign SSD[4] = ~((~X[2] & ~X[0]) | (X[1] & ~X[0]));
  assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] & ~X[2] &  X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
  assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] &  X[2] & X[1] & X[0]));
endmodule
module b2d_7seg (X, SSD);

  input [3:0] X;
  output [0:6] SSD;

  assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] & ~X[1] & ~X[0]));
  assign SSD[1] = ((~X[3] &  X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] &  X[1] & ~X[0]));
  assign SSD[2] =  (~X[3] & ~X[2] &  X[1] & ~X[0]);
  assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] &  X[2] & ~X[1] & ~X[0]) | (~X[3] &  X[2] & X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]));
  assign SSD[4] = ~((~X[2] & ~X[0]) | (X[1] & ~X[0]));
  assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] & ~X[2] &  X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
  assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] &  X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] &  X[2] & X[1] & X[0]));
endmodule