data/full_repos/permissive/193790231/B_memoryFlops.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/193790231/B_memoryFlops.v:30: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                          : ... Top module \'B_latchRSe\'\nmodule B_latchRSe(\n       ^~~~~~~~~~\n                                                                          : ... Top module \'B_latchRSg\'\nmodule B_latchRSg(\n       ^~~~~~~~~~\n                                                                          : ... Top module \'B_flipflopDmse\'\nmodule B_flipflopDmse(\n       ^~~~~~~~~~~~~~\n                                                                          : ... Top module \'mem_DLatch\'\nmodule mem_DLatch(\n       ^~~~~~~~~~\n                                                                          : ... Top module \'mem_Dflipneg\'\nmodule mem_Dflipneg(\n       ^~~~~~~~~~~~\n                                                                          : ... Top module \'lab04part01_TFlipAnd\'\nmodule lab04part01_TFlipAnd(\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                          : ... Top module \'registerNx\'\nmodule registerNx #(parameter regWidth=8)(\n       ^~~~~~~~~~\n                                                                          : ... Top module \'shiftRegisterNx\'\nmodule shiftRegisterNx #(parameter regWidth=4) (\n       ^~~~~~~~~~~~~~~\n                                                                          : ... Top module \'genericRAM\'\nmodule genericRAM #(parameter dataW = 8, parameter addrW = 5) (\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module mem_Tflippos(
	output reg Q,
	input T, clk, reset
);
	wire d;
	xor(d, Q, T);
	
	always@(posedge clk)
	begin
		if(~reset)
			Q <= 1'b0;


		else
			Q <= d;
	end
endmodule
module mem_Tflippos(
	output reg Q,
	input T, clk, reset
);

	wire d;
	xor(d, Q, T);
	
	always@(posedge clk)
	begin
		if(~reset)
			Q <= 1'b0;


		else
			Q <= d;
	end
endmodule