data/full_repos/permissive/122693972/hdlsrc/testbench.v
 line:19: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/122693972/hdlsrc/testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n# TIME_RUN  $stop();\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/122693972/hdlsrc/testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\n  # 100 O_RST   = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122693972/hdlsrc/testbench.v:67: Unsupported: Ignoring delay on this delayed statement.\n  # 200 O_RST   = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122693972/hdlsrc/testbench.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #CLK_PERIOD_HALF O_CLK = ~O_CLK;\n  ^\n%Error: data/full_repos/permissive/122693972/hdlsrc/testbench.v:32: Cannot find file containing module: \'u_add_1\'\nu_add_1 U_add(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122693972/hdlsrc,data/full_repos/permissive/122693972/u_add_1\n             data/full_repos/permissive/122693972/hdlsrc,data/full_repos/permissive/122693972/u_add_1.v\n             data/full_repos/permissive/122693972/hdlsrc,data/full_repos/permissive/122693972/u_add_1.sv\n             u_add_1\n             u_add_1.v\n             u_add_1.sv\n             obj_dir/u_add_1\n             obj_dir/u_add_1.v\n             obj_dir/u_add_1.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gen_clk_rst(
  O_CLK   ,
  O_RST   );

parameter CLK_PERIOD_HALF = 1; 

output O_CLK;
output O_RST;
reg O_CLK;
reg O_RST;

initial begin
  O_CLK         = 0;
  O_RST         = 1;
  # 100 O_RST   = 1'b1;
  # 200 O_RST   = 1'b0;
end

always begin
  #CLK_PERIOD_HALF O_CLK = ~O_CLK;
end

endmodule
module gen_clk_rst(
  O_CLK   ,
  O_RST   );


parameter CLK_PERIOD_HALF = 1; 

output O_CLK;
output O_RST;
reg O_CLK;
reg O_RST;

initial begin
  O_CLK         = 0;
  O_RST         = 1;
  # 100 O_RST   = 1'b1;
  # 200 O_RST   = 1'b0;
end

always begin
  #CLK_PERIOD_HALF O_CLK = ~O_CLK;
end

endmodule