data/full_repos/permissive/205931224/source/src/fetch.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/205931224/source/src/fetch.v:21: Cannot find include file: macros.v\n`include "macros.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205931224/source/src,data/full_repos/permissive/205931224/macros.v\n             data/full_repos/permissive/205931224/source/src,data/full_repos/permissive/205931224/macros.v.v\n             data/full_repos/permissive/205931224/source/src,data/full_repos/permissive/205931224/macros.v.sv\n             macros.v\n             macros.v.v\n             macros.v.sv\n             obj_dir/macros.v\n             obj_dir/macros.v.v\n             obj_dir/macros.v.sv\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:53: Define or directive not defined: \'`OPCODE_J_JUMP\'\n assign jump_j_flag = (instruction[31:26] == `OPCODE_J_JUMP) ? 1\'b1 : 1\'b0;\n                                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:53: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign jump_j_flag = (instruction[31:26] == `OPCODE_J_JUMP) ? 1\'b1 : 1\'b0;\n                                                           ^\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:54: Define or directive not defined: \'`OPCODE_JAL_JUMP\'\n assign jump_jal_flag = (instruction[31:26] == `OPCODE_JAL_JUMP) ? 1\'b1 : 1\'b0;\n                                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:54: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign jump_jal_flag = (instruction[31:26] == `OPCODE_JAL_JUMP) ? 1\'b1 : 1\'b0;\n                                                               ^\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:55: Define or directive not defined: \'`OPCODE_R\'\n assign jump_jr_flag = (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) ? 1\'b1 : 1\'b0;\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:55: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n assign jump_jr_flag = (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) ? 1\'b1 : 1\'b0;\n                                                        ^~\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:55: Define or directive not defined: \'`R_FUNC_JR\'\n assign jump_jr_flag = (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) ? 1\'b1 : 1\'b0;\n                                                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:59: Define or directive not defined: \'`OPCODE_I_BEQ\'\n    assign if_branch_flag = (instruction[31:26] == `OPCODE_I_BEQ) | (instruction[31:26] == `OPCODE_I_BNE) | pre_jump_flag;\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:59: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign if_branch_flag = (instruction[31:26] == `OPCODE_I_BEQ) | (instruction[31:26] == `OPCODE_I_BNE) | pre_jump_flag;\n                                                                ^\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:59: Define or directive not defined: \'`OPCODE_I_BNE\'\n    assign if_branch_flag = (instruction[31:26] == `OPCODE_I_BEQ) | (instruction[31:26] == `OPCODE_I_BNE) | pre_jump_flag;\n                                                                                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:122: Define or directive not defined: \'`NOP\'\n                    reg_instruction <= `NOP;\n                                       ^~~~\n%Error: data/full_repos/permissive/205931224/source/src/fetch.v:122: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    reg_instruction <= `NOP;\n                                           ^\n%Error: Exiting due to 13 error(s)\n'
module fetch(
input wire							clk,
input wire							rst,
input wire [31:0]                   instruction,
input wire [31:0]                   pc_branch,
input wire [31:0]                   pc_jump,
input wire [31:0]                   pc_next,
input wire                          real_token,
input wire                          jump_token,
input wire                          isHazard,
input wire                          isFlush,
input wire                          isCacheStall,
output reg [31:0]                   reg_pc,
output reg [31:0]                   reg_instruction,

output reg [1:0]                    reg_bht_token,
input wire [9:0]                    bht_write_addr,
input wire                          bht_we,
input wire [33:0]                   bht_din
    );

	wire [31:0]                pc_inc;
	wire [31:0]                pc;
	wire                       pre_jump_flag;
	wire                       jump_j_flag;
	wire                       jump_jal_flag;
	wire                       jump_jr_flag;

    wire                        if_branch_flag;
		

	assign jump_j_flag = (instruction[31:26] == `OPCODE_J_JUMP) ? 1'b1 : 1'b0;
	assign jump_jal_flag = (instruction[31:26] == `OPCODE_JAL_JUMP) ? 1'b1 : 1'b0;
	assign jump_jr_flag = (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) ? 1'b1 : 1'b0;

    assign pre_jump_flag = (jump_j_flag | jump_jal_flag) | jump_jr_flag;

    assign if_branch_flag = (instruction[31:26] == `OPCODE_I_BEQ) | (instruction[31:26] == `OPCODE_I_BNE) | pre_jump_flag;
	

	assign pc_inc = reg_pc + 3'd4;
	assign pc = BRANCH_RES(isFlush, jump_token, real_token, pc_branch, pc_jump, pc_next, pc_inc);
	function [31:0] BRANCH_RES;
		input         isFlush;
		input         jump_token;
		input         real_token;
		input [31:0]  pc_branch;
		input [31:0]  pc_jump;
		input [31:0]  pc_next;
		input [31:0]  pc_inc;
		begin
		  if( isFlush )
		  begin
		      if( real_token )
		          BRANCH_RES = pc_branch;
		      else if( jump_token )
		          BRANCH_RES = pc_jump;
		      else
		          BRANCH_RES = pc_next;
		  end
		  else
		      BRANCH_RES = pc_inc;
		end
	endfunction
	
	
	wire [9:0]     bht_read_addr;
	wire [33:0]    bht_dout;
	wire [1:0]     bht_predict_isBranch;
	wire [31:0]    bht_predict_pc;
	

	assign bht_read_addr = reg_pc[11:2];
	assign bht_predict_isBranch = bht_dout[33:32];
	assign bht_predict_pc = bht_dout[31:0];

	bht bht_inst(
	   .a( bht_write_addr ),
	   .d( bht_din ),
	   .dpra( bht_read_addr ),
	   .clk( clk ),
	   .we( bht_we ),
	   .dpo( bht_dout )
	);
	

	always@(posedge clk)
	begin
		if( rst )
		  begin
			reg_pc <= 0;
			reg_instruction <= 0;
			reg_bht_token <= 0;
		  end
		else
			begin

                if( isFlush )
                 begin
                    reg_pc <= pc;
                    reg_instruction <= `NOP;
                    reg_bht_token <= 0;
                 end

			    else if( isHazard || isCacheStall )
			     begin
			        reg_pc <= reg_pc;
                    reg_instruction <= reg_instruction;
                    reg_bht_token <= reg_bht_token;
				 end

				 else if( if_branch_flag && bht_predict_isBranch[1] )
				 begin
				    reg_pc <= bht_predict_pc;
				    reg_instruction <= instruction;
				    reg_bht_token <= bht_predict_isBranch;
				 end
				else
				 begin
				    reg_pc <= pc;
				    reg_instruction <= instruction;
				    reg_bht_token <= bht_predict_isBranch;;
				 end   
			end
	end

endmodule
module fetch(
input wire							clk,
input wire							rst,
input wire [31:0]                   instruction,
input wire [31:0]                   pc_branch,
input wire [31:0]                   pc_jump,
input wire [31:0]                   pc_next,
input wire                          real_token,
input wire                          jump_token,
input wire                          isHazard,
input wire                          isFlush,
input wire                          isCacheStall,
output reg [31:0]                   reg_pc,
output reg [31:0]                   reg_instruction,

output reg [1:0]                    reg_bht_token,
input wire [9:0]                    bht_write_addr,
input wire                          bht_we,
input wire [33:0]                   bht_din
    );


	wire [31:0]                pc_inc;
	wire [31:0]                pc;
	wire                       pre_jump_flag;
	wire                       jump_j_flag;
	wire                       jump_jal_flag;
	wire                       jump_jr_flag;

    wire                        if_branch_flag;
		

	assign jump_j_flag = (instruction[31:26] == `OPCODE_J_JUMP) ? 1'b1 : 1'b0;
	assign jump_jal_flag = (instruction[31:26] == `OPCODE_JAL_JUMP) ? 1'b1 : 1'b0;
	assign jump_jr_flag = (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) ? 1'b1 : 1'b0;

    assign pre_jump_flag = (jump_j_flag | jump_jal_flag) | jump_jr_flag;

    assign if_branch_flag = (instruction[31:26] == `OPCODE_I_BEQ) | (instruction[31:26] == `OPCODE_I_BNE) | pre_jump_flag;
	

	assign pc_inc = reg_pc + 3'd4;
	assign pc = BRANCH_RES(isFlush, jump_token, real_token, pc_branch, pc_jump, pc_next, pc_inc);
	function [31:0] BRANCH_RES;
		input         isFlush;
		input         jump_token;
		input         real_token;
		input [31:0]  pc_branch;
		input [31:0]  pc_jump;
		input [31:0]  pc_next;
		input [31:0]  pc_inc;
		begin
		  if( isFlush )
		  begin
		      if( real_token )
		          BRANCH_RES = pc_branch;
		      else if( jump_token )
		          BRANCH_RES = pc_jump;
		      else
		          BRANCH_RES = pc_next;
		  end
		  else
		      BRANCH_RES = pc_inc;
		end
	endfunction
	
	
	wire [9:0]     bht_read_addr;
	wire [33:0]    bht_dout;
	wire [1:0]     bht_predict_isBranch;
	wire [31:0]    bht_predict_pc;
	

	assign bht_read_addr = reg_pc[11:2];
	assign bht_predict_isBranch = bht_dout[33:32];
	assign bht_predict_pc = bht_dout[31:0];

	bht bht_inst(
	   .a( bht_write_addr ),
	   .d( bht_din ),
	   .dpra( bht_read_addr ),
	   .clk( clk ),
	   .we( bht_we ),
	   .dpo( bht_dout )
	);
	

	always@(posedge clk)
	begin
		if( rst )
		  begin
			reg_pc <= 0;
			reg_instruction <= 0;
			reg_bht_token <= 0;
		  end
		else
			begin

                if( isFlush )
                 begin
                    reg_pc <= pc;
                    reg_instruction <= `NOP;
                    reg_bht_token <= 0;
                 end

			    else if( isHazard || isCacheStall )
			     begin
			        reg_pc <= reg_pc;
                    reg_instruction <= reg_instruction;
                    reg_bht_token <= reg_bht_token;
				 end

				 else if( if_branch_flag && bht_predict_isBranch[1] )
				 begin
				    reg_pc <= bht_predict_pc;
				    reg_instruction <= instruction;
				    reg_bht_token <= bht_predict_isBranch;
				 end
				else
				 begin
				    reg_pc <= pc;
				    reg_instruction <= instruction;
				    reg_bht_token <= bht_predict_isBranch;;
				 end   
			end
	end

endmodule