data/full_repos/permissive/20289584/mux4.v
 line:33: before: "begin"
1: b'%Error: data/full_repos/permissive/20289584/mux4.v:35: Unsupported or unknown PLI call: $monitor\n  $monitor("%4dns monitor: s=%d d=%d q=%d", $stime, s, d, q);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/20289584/mux4.v:36: Unsupported or unknown PLI call: $monitor\n    $monitor("%4dns monitor: s=%d d=%d q=%d", $stime, s, d1, q1);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20289584/mux4.v:33: Unsupported: Ignoring delay on this delayed statement.\nalways #50 begin\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20289584/mux4.v:39: Unsupported: Ignoring delay on this delayed statement.\ninitial #1000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux4(input[1:0]  select, input[3:0] d, input[3:0] d1, output reg q,output reg q1 );
always @( select or d or d1)
begin
   case( select )
       0 : q = d[0];
       1 : q = d[1];
       2 : q = d[2];
       3 : q = d[3]; 
   endcase
	 case( select )
       0 : q1 = d1[0];
       1 : q1 = d1[1];
       2 : q1 = d1[2];
       3 : q1 = d1[3]; 
   endcase
end
endmodule
module mux4(input[1:0]  select, input[3:0] d, input[3:0] d1, output reg q,output reg q1 );

always @( select or d or d1)
begin
   case( select )
       0 : q = d[0];
       1 : q = d[1];
       2 : q = d[2];
       3 : q = d[3]; 
   endcase
	 case( select )
       0 : q1 = d1[0];
       1 : q1 = d1[1];
       2 : q1 = d1[2];
       3 : q1 = d1[3]; 
   endcase
end
endmodule