data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v
Syntax Error
1: b'%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v:47: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 or 7 bits.\n                                                                           : ... In instance LZD_N.l1\n    else if (N & (N-1))\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Adder/LZD_N.v:47: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 bits.\n                                                                           : ... In instance LZD_N.l1.genblk2.genblk2.h\n    else if (N & (N-1))\n         ^~\n%Error: Exiting due to 2 warning(s)\n'
function [31:0] log2;
    input reg [31:0] value;
    begin
      value = value-1;
      for (log2=0; value>0; log2=log2+1)
	value = value>>1;
    end
  endfunction
function [31:0] log2;

    input reg [31:0] value;
    begin
      value = value-1;
      for (log2=0; value>0; log2=log2+1)
	value = value>>1;
    end
  endfunction