data/full_repos/permissive/117439411/Pacman_ACL_v1/ssdctrl.v
1: b"%Error: data/full_repos/permissive/117439411/Pacman_ACL_v1/ssdctrl.v:40: Cannot find file containing module: 'Format_Data'\n  Format_Data XFDATA(\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117439411/Pacman_ACL_v1,data/full_repos/permissive/117439411/Format_Data\n             data/full_repos/permissive/117439411/Pacman_ACL_v1,data/full_repos/permissive/117439411/Format_Data.v\n             data/full_repos/permissive/117439411/Pacman_ACL_v1,data/full_repos/permissive/117439411/Format_Data.sv\n             Format_Data\n             Format_Data.v\n             Format_Data.sv\n             obj_dir/Format_Data\n             obj_dir/Format_Data.v\n             obj_dir/Format_Data.sv\n%Error: data/full_repos/permissive/117439411/Pacman_ACL_v1/ssdctrl.v:50: Cannot find file containing module: 'Format_Data'\n  Format_Data YFDATA(\n  ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ssdCtrl(
		CLK,
		RST,
		x_DIN,
		y_DIN,
		x_bcdData,
		y_bcdData
);




   input            CLK;
   input            RST;
   input [9:0]      x_DIN;
   input [9:0]      y_DIN;
	output [15:0]	  x_bcdData;
 	output [15:0]	  y_bcdData;   




   parameter [15:0] cntEndVal = 16'hC350;
   reg [15:0]       clkCount;
   reg              DCLK;




		assign x_bcdData[15:12] = (x_DIN[9] == 1'b0) ? (4'h0) : (4'hF);
		assign y_bcdData[15:12] = (y_DIN[9] == 1'b0) ? (4'h0) : (4'hF);
		



		Format_Data XFDATA(
				.CLK(CLK),
				.DCLK(DCLK),
				.RST(RST),
				.DIN(x_DIN[8:0]),
				.BCDOUT(x_bcdData[11:0])
		);



		Format_Data YFDATA(
				.CLK(CLK),
				.DCLK(DCLK),
				.RST(RST),
				.DIN(y_DIN[8:0]),
				.BCDOUT(y_bcdData[11:0])
		);
		





		always @(posedge CLK) begin
				if (clkCount == cntEndVal) begin
					DCLK <= 1'b1;
					clkCount <= 16'h0000;
				end
				else begin
					DCLK <= 1'b0;
					clkCount <= clkCount + 1'b1;
				end
		end
endmodule
module ssdCtrl(
		CLK,
		RST,
		x_DIN,
		y_DIN,
		x_bcdData,
		y_bcdData
);





   input            CLK;
   input            RST;
   input [9:0]      x_DIN;
   input [9:0]      y_DIN;
	output [15:0]	  x_bcdData;
 	output [15:0]	  y_bcdData;   




   parameter [15:0] cntEndVal = 16'hC350;
   reg [15:0]       clkCount;
   reg              DCLK;




		assign x_bcdData[15:12] = (x_DIN[9] == 1'b0) ? (4'h0) : (4'hF);
		assign y_bcdData[15:12] = (y_DIN[9] == 1'b0) ? (4'h0) : (4'hF);
		



		Format_Data XFDATA(
				.CLK(CLK),
				.DCLK(DCLK),
				.RST(RST),
				.DIN(x_DIN[8:0]),
				.BCDOUT(x_bcdData[11:0])
		);



		Format_Data YFDATA(
				.CLK(CLK),
				.DCLK(DCLK),
				.RST(RST),
				.DIN(y_DIN[8:0]),
				.BCDOUT(y_bcdData[11:0])
		);
		





		always @(posedge CLK) begin
				if (clkCount == cntEndVal) begin
					DCLK <= 1'b1;
					clkCount <= 16'h0000;
				end
				else begin
					DCLK <= 1'b0;
					clkCount <= clkCount + 1'b1;
				end
		end
endmodule