data/full_repos/permissive/121803953/Lab2/lab2.v
data/verilator_xmls/d30f6656-4afb-4621-883b-a3d78d745bea.xml
module lab2(a, b, c, d, X, Y, P);
    input a, b, c, d;
    output X, Y, P;
    part1 mod1(a, b, c, d, X);
    part2 mod2(a, b, c, d, Y);
    part3 mod3({d, c, b, a}, P);    
endmodule
module lab2(a, b, c, d, X, Y, P);

    input a, b, c, d;
    output X, Y, P;
    part1 mod1(a, b, c, d, X);
    part2 mod2(a, b, c, d, Y);
    part3 mod3({d, c, b, a}, P);    
endmodule