data/full_repos/permissive/193753641/AddRoundKey.v
data/verilator_xmls/fd4b7bed-13cc-4f28-ae00-416a87c48bbe.xml
module AddRoundKey(in,key,out);

	input [127:0] in,key;
	output [127:0] out;

	assign out=in^key;

endmodule
module AddRoundKey(in,key,out);


	input [127:0] in,key;
	output [127:0] out;

	assign out=in^key;

endmodule