data/full_repos/permissive/157135695/shifter.v
 line:49: before: "module"
data/verilator_xmls/57eeb26f-2e8c-436a-b856-3a442e1670d2.xml
module shifter(A, LA, LR, Y, C);


input [7:0] A; 
input LA; 
input LR; 
  

output [7:0] Y; 
output  C; 



  

  assign Y = LR ? (LA ? ({A[7],A[7:1]}) : ({1'b0,A[7:1]})) : ({A[6:0],1'b0});
  assign C = LR ? A[0] : A[7];
 

endmodule
module shifter(A, LA, LR, Y, C);



input [7:0] A; 
input LA; 
input LR; 
  

output [7:0] Y; 
output  C; 



  

  assign Y = LR ? (LA ? ({A[7],A[7:1]}) : ({1'b0,A[7:1]})) : ({A[6:0],1'b0});
  assign C = LR ? A[0] : A[7];
 

endmodule