data/full_repos/permissive/137416864/benchmarks/techmapping/tigfet/sclib_tigfet10_hpnw4_tt_0p70v_25c.v
None: at end of input
data/verilator_xmls/66fbbc70-176b-43e7-9514-2e141670a68b.xml
module XOR2_HPNW4 (Y, A, B);
	output Y;
	input A, B;


	buf (Y, 1'b0);


	specify
		(posedge A => (Y:A)) = 0;
		(negedge A => (Y:A)) = 0;
		(posedge B => (Y:B)) = 0;
		(negedge B => (Y:B)) = 0;
	endspecify
endmodule
module XOR2_HPNW4 (Y, A, B);

	output Y;
	input A, B;


	buf (Y, 1'b0);


	specify
		(posedge A => (Y:A)) = 0;
		(negedge A => (Y:A)) = 0;
		(posedge B => (Y:B)) = 0;
		(negedge B => (Y:B)) = 0;
	endspecify
endmodule