data/full_repos/permissive/114459345/srcCache/mem_wb.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:9: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] mem_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus] mem_wd,\n                       ^\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] mem_wdata,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:11: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:14: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wb_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:16: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] wb_wdata\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:16: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wb_wdata\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:21: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:22: Define or directive not defined: \'`NopRegAddr\'\n   wb_wd <= `NopRegAddr;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:23: Define or directive not defined: \'`WriteDisable\'\n   wb_wreg <= `WriteDisable;\n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:24: Define or directive not defined: \'`ZeroWord\'\n   wb_wdata <= `ZeroWord;\n               ^~~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module mem_wb(
	input wire clk,
	input wire rst,
	

	input wire[`RegAddrBus] mem_wd,
	input wire mem_wreg,
	input wire[`RegBus] mem_wdata,
	

	output reg[`RegAddrBus] wb_wd,
	output reg wb_wreg,
	output reg[`RegBus] wb_wdata

);

	always @ (posedge clk) begin
		if(rst == `RstEnable) begin
			wb_wd <= `NopRegAddr;
			wb_wreg <= `WriteDisable;
			wb_wdata <= `ZeroWord;
		end
		else begin
			wb_wd <= mem_wd;
			wb_wreg <= mem_wreg;
			wb_wdata <= mem_wdata;
		end
	end

endmodule
module mem_wb(
	input wire clk,
	input wire rst,
	

	input wire[`RegAddrBus] mem_wd,
	input wire mem_wreg,
	input wire[`RegBus] mem_wdata,
	

	output reg[`RegAddrBus] wb_wd,
	output reg wb_wreg,
	output reg[`RegBus] wb_wdata

);


	always @ (posedge clk) begin
		if(rst == `RstEnable) begin
			wb_wd <= `NopRegAddr;
			wb_wreg <= `WriteDisable;
			wb_wdata <= `ZeroWord;
		end
		else begin
			wb_wd <= mem_wd;
			wb_wreg <= mem_wreg;
			wb_wdata <= mem_wdata;
		end
	end

endmodule