data/full_repos/permissive/135795492/project/top.v
1: b'%Error: data/full_repos/permissive/135795492/project/top.v:43: Duplicate declaration of signal: \'clk\'\n                                                             : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire CLK_OUT1,CLK_OUT2,clk;\n                       ^~~\n        data/full_repos/permissive/135795492/project/top.v:22: ... Location of original declaration\n    input clk,\n          ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/135795492/project/top.v:220: Signal definition not found, creating implicitly: \'videoon\'\nif(videoon)begin\n   ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module top(
    input clk,
    input rx,
	 input ch,


	 output full,
	
	 

	 input [5:0] sw,
	 output reg [5:0] rgb,
	 output hsync,
	 output vsync

    );

wire [7:0]  data;
wire 	[7:0] data_rx;
reg tx_data_ready;
wire clk_wr, clk_rd;
wire [7:0]dout_fifo;
wire CLK_OUT1,CLK_OUT2,clk;
wire [10:0]pixel_x, pixel_y;
wire [10:0]douta;
wire RxD_data_ready;
reg rd_en=0;

 
async_receiver # (.Baud(115200)) uart_rec (
    .clk(clk), 
    .RxD(rx), 
    .RxD_data_ready(RxD_data_ready), 
    .RxD_data(data_rx), 
    .RxD_idle(), 
    .RxD_endofpacket()
    );
wire [10:0] rd_data_count;  


fifo our_fifo(
  .clk(clk),
  .din(data_rx),
  .wr_en(RxD_data_ready),
  .rd_en(rd_en),
  .dout(dout_fifo),
  .full(full),
  .empty(empty),
  .data_count(rd_data_count)
);
	
 

reg done_fft;
reg [9:0]norm2;
reg [8 : 0] addr_in_ram;
wire [8 : 0] xn_index;
wire [7 : 0] xk_re;
wire [7 : 0] xk_im;
wire [7 : 0] xn_re;
wire [8 : 0] xk_index;
wire [7 : 0] doutb1;
wire [7 : 0] doutb2;
reg [7 : 0] doutb;
reg [9:0] cnt_fifo = 0; 

reg start =0;
reg forconfig = 1;
reg fwd_inv_we=0;
reg ce=0;
reg scale_sch_we=0;


always @(posedge clk)
	begin
		if(forconfig)
			begin
				fwd_inv_we <= 1;
				scale_sch_we <= 1;
				forconfig <= 1'b0;
				start <= 1;

			end
		else  
			begin
				fwd_inv_we <= 0;
				scale_sch_we <= 0;
			end
	end

always @(posedge clk)
	begin
		if(rd_data_count == 511)
			begin
				rd_en <= 1'b1;
				ce <= 1'b1;
				cnt_fifo <= 0;
			end
		if(rd_en)
			begin
				cnt_fifo <= cnt_fifo + 1'b1;
			end
		if (cnt_fifo == 511)
			begin
				rd_en <= 0;
				cnt_fifo <= 0;
			end
		if(xk_index == 511)
			begin
				ce <= 0;
			end
	end



	
reg unload=1'b1;	
reg [17:0] scale_sch=18;	

fft our_fft (
  .clk(clk),
  .ce(ce),
  .start(start),
  .unload(unload),
  .xn_re(dout_fifo),
  .xn_im(0),
  .fwd_inv(1),
  .fwd_inv_we(fwd_inv_we),
  .scale_sch(scale_sch),
  .scale_sch_we(scale_sch_we),
  .rfd(rfd),
  .xn_index(xn_index),
  .busy(busy),
  .edone(edone),
  .done(done),
  .dv(dv),
  .xk_index(xk_index),
  .xk_re(xk_re),
  .xk_im(xk_im)
);
wire [16:0] data_fft;
assign data_fft = (xk_re * xk_re) + (xk_im * xk_im);




reg [9:0]add_ram=0;

ram our_ram (
  .clka(clk),
  .wea(dv),
  .addra(xk_index),
  .dina(data_fft),
  .douta(),
  .clkb(clk),
  .web(1'b0),
  .addrb(add_ram),
  .dinb(),
  .doutb(doutb1)
);

ram main_sig(
  .clka(clk),
  .wea(rd_en),
  .addra(cnt_fifo),
  .dina(dout_fifo),
  .douta(),
  .clkb(clk),
  .web(1'b0),
  .addrb(add_ram),
  .dinb(),
  .doutb(doutb2)
);

always @(posedge clk)
	begin
		if(ch == 1)
			doutb <= doutb1;
		else
			doutb <= doutb2;
	end


	
VGA my_vga(
    .clk(clk), 
    .pixel_x(pixel_x), 
    .pixel_y(pixel_y), 
    .videoon(videoon), 
    .h_synq(hsync), 
    .v_synq(vsync)
    );	
	 
	 


		
always@(posedge clk)
begin
if(videoon)begin
		if(pixel_x > 64 && pixel_x < 576)
			if(pixel_y > 430)
				begin
						add_ram <= pixel_x - 64;
						if(pixel_y > 480-doutb)
							rgb <= sw;
						else 
							rgb <= ~sw;
					
				end
			else
				begin 
						add_ram <= pixel_x - 64;
						if(pixel_y > 480-doutb)
							rgb <= ~sw;
						else 
							rgb <= sw;
				end

			else
				begin
					add_ram <= 0;
					rgb <= sw;
				end
end
else 
	rgb <= 6'b0;
end  

	
endmodule
module top(
    input clk,
    input rx,
	 input ch,


	 output full,
	
	 

	 input [5:0] sw,
	 output reg [5:0] rgb,
	 output hsync,
	 output vsync

    );


wire [7:0]  data;
wire 	[7:0] data_rx;
reg tx_data_ready;
wire clk_wr, clk_rd;
wire [7:0]dout_fifo;
wire CLK_OUT1,CLK_OUT2,clk;
wire [10:0]pixel_x, pixel_y;
wire [10:0]douta;
wire RxD_data_ready;
reg rd_en=0;

 
async_receiver # (.Baud(115200)) uart_rec (
    .clk(clk), 
    .RxD(rx), 
    .RxD_data_ready(RxD_data_ready), 
    .RxD_data(data_rx), 
    .RxD_idle(), 
    .RxD_endofpacket()
    );
wire [10:0] rd_data_count;  


fifo our_fifo(
  .clk(clk),
  .din(data_rx),
  .wr_en(RxD_data_ready),
  .rd_en(rd_en),
  .dout(dout_fifo),
  .full(full),
  .empty(empty),
  .data_count(rd_data_count)
);
	
 

reg done_fft;
reg [9:0]norm2;
reg [8 : 0] addr_in_ram;
wire [8 : 0] xn_index;
wire [7 : 0] xk_re;
wire [7 : 0] xk_im;
wire [7 : 0] xn_re;
wire [8 : 0] xk_index;
wire [7 : 0] doutb1;
wire [7 : 0] doutb2;
reg [7 : 0] doutb;
reg [9:0] cnt_fifo = 0; 

reg start =0;
reg forconfig = 1;
reg fwd_inv_we=0;
reg ce=0;
reg scale_sch_we=0;


always @(posedge clk)
	begin
		if(forconfig)
			begin
				fwd_inv_we <= 1;
				scale_sch_we <= 1;
				forconfig <= 1'b0;
				start <= 1;

			end
		else  
			begin
				fwd_inv_we <= 0;
				scale_sch_we <= 0;
			end
	end

always @(posedge clk)
	begin
		if(rd_data_count == 511)
			begin
				rd_en <= 1'b1;
				ce <= 1'b1;
				cnt_fifo <= 0;
			end
		if(rd_en)
			begin
				cnt_fifo <= cnt_fifo + 1'b1;
			end
		if (cnt_fifo == 511)
			begin
				rd_en <= 0;
				cnt_fifo <= 0;
			end
		if(xk_index == 511)
			begin
				ce <= 0;
			end
	end



	
reg unload=1'b1;	
reg [17:0] scale_sch=18;	

fft our_fft (
  .clk(clk),
  .ce(ce),
  .start(start),
  .unload(unload),
  .xn_re(dout_fifo),
  .xn_im(0),
  .fwd_inv(1),
  .fwd_inv_we(fwd_inv_we),
  .scale_sch(scale_sch),
  .scale_sch_we(scale_sch_we),
  .rfd(rfd),
  .xn_index(xn_index),
  .busy(busy),
  .edone(edone),
  .done(done),
  .dv(dv),
  .xk_index(xk_index),
  .xk_re(xk_re),
  .xk_im(xk_im)
);
wire [16:0] data_fft;
assign data_fft = (xk_re * xk_re) + (xk_im * xk_im);




reg [9:0]add_ram=0;

ram our_ram (
  .clka(clk),
  .wea(dv),
  .addra(xk_index),
  .dina(data_fft),
  .douta(),
  .clkb(clk),
  .web(1'b0),
  .addrb(add_ram),
  .dinb(),
  .doutb(doutb1)
);

ram main_sig(
  .clka(clk),
  .wea(rd_en),
  .addra(cnt_fifo),
  .dina(dout_fifo),
  .douta(),
  .clkb(clk),
  .web(1'b0),
  .addrb(add_ram),
  .dinb(),
  .doutb(doutb2)
);

always @(posedge clk)
	begin
		if(ch == 1)
			doutb <= doutb1;
		else
			doutb <= doutb2;
	end


	
VGA my_vga(
    .clk(clk), 
    .pixel_x(pixel_x), 
    .pixel_y(pixel_y), 
    .videoon(videoon), 
    .h_synq(hsync), 
    .v_synq(vsync)
    );	
	 
	 


		
always@(posedge clk)
begin
if(videoon)begin
		if(pixel_x > 64 && pixel_x < 576)
			if(pixel_y > 430)
				begin
						add_ram <= pixel_x - 64;
						if(pixel_y > 480-doutb)
							rgb <= sw;
						else 
							rgb <= ~sw;
					
				end
			else
				begin 
						add_ram <= pixel_x - 64;
						if(pixel_y > 480-doutb)
							rgb <= ~sw;
						else 
							rgb <= sw;
				end

			else
				begin
					add_ram <= 0;
					rgb <= sw;
				end
end
else 
	rgb <= 6'b0;
end  

	
endmodule