data/full_repos/permissive/143278/ivltests/casesynth9.v
 line:38: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth9.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #1 $display("%d : %b", sel, out);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/casesynth9.v:40: Operator NEQCASE expects 3 bits on the RHS, but RHS\'s VARREF \'sel\' generates 2 bits.\n                                                                          : ... In instance test\n    if (out !== sel) failed = 1;\n            ^~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

reg  [1:0] sel;
wire [2:0] out;

mux mux(sel, 3'd0, 3'd1, 3'd2, 3'd3, 3'd4, out);

reg failed;

(* ivl_synthesis_off *)
initial begin
  failed = 0;
  sel = 0;
  repeat (4) begin
    #1 $display("%d : %b", sel, out);
    if (out !== sel) failed = 1;
    sel = sel + 1;
  end
  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module test();


reg  [1:0] sel;
wire [2:0] out;

mux mux(sel, 3'd0, 3'd1, 3'd2, 3'd3, 3'd4, out);

reg failed;

(* ivl_synthesis_off *)
initial begin
  failed = 0;
  sel = 0;
  repeat (4) begin
    #1 $display("%d : %b", sel, out);
    if (out !== sel) failed = 1;
    sel = sel + 1;
  end
  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule