data/full_repos/permissive/143278/ivltests/pr1963240.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1963240.v:5: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'hf7\' generates 32 bits.\n                                                                        : ... In instance test\n      i8 = 32\'hf7;\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1963240.v:6: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3\' generates 32 bits.\n                                                                        : ... In instance test\n      j8 = 32\'h3;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1963240.v:7: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n                                                                        : ... In instance test\n      i32 = $signed(i8 / j8);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1963240.v:9: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'hf7\' generates 32 bits.\n                                                                        : ... In instance test\n      i8 = 32\'hf7;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1963240.v:10: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                         : ... In instance test\n      j8 = 32\'h1;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1963240.v:11: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n                                                                         : ... In instance test\n      i32 = $signed(i8 / j8);\n          ^\n%Error: Exiting due to 6 warning(s)\n'
module test;
   reg [7:0] i8, j8;
   reg [31:0] i32;
   initial begin
      i8 = 32'hf7;
      j8 = 32'h3;
      i32 = $signed(i8 / j8);
      $write("expected %0h; got %0h\n", 8'h52, i32);
      i8 = 32'hf7;
      j8 = 32'h1;
      i32 = $signed(i8 / j8);
      $write("expected %0h; got %0h\n", 32'hffffff_f7, i32);
   end
endmodule
module test;

   reg [7:0] i8, j8;
   reg [31:0] i32;
   initial begin
      i8 = 32'hf7;
      j8 = 32'h3;
      i32 = $signed(i8 / j8);
      $write("expected %0h; got %0h\n", 8'h52, i32);
      i8 = 32'hf7;
      j8 = 32'h1;
      i32 = $signed(i8 / j8);
      $write("expected %0h; got %0h\n", 32'hffffff_f7, i32);
   end
endmodule