data/full_repos/permissive/185287750/openmsp430/msp_core/driver_7segment.v
1: b'%Warning-WIDTH: data/full_repos/permissive/185287750/openmsp430/msp_core/driver_7segment.v:203: Operator AND expects 16 bits on the LHS, but LHS\'s VARREF \'digit0\' generates 8 bits.\n                                                                                              : ... In instance driver_7segment\nwire [15:0] digit0_rd   = (digit0  & {8{reg_rd[DIGIT0]}})  << (8 & {4{DIGIT0[0]}});\n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/185287750/openmsp430/msp_core/driver_7segment.v:203: Operator AND expects 16 bits on the RHS, but RHS\'s REPLICATE generates 8 bits.\n                                                                                              : ... In instance driver_7segment\nwire [15:0] digit0_rd   = (digit0  & {8{reg_rd[DIGIT0]}})  << (8 & {4{DIGIT0[0]}});\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/185287750/openmsp430/msp_core/driver_7segment.v:204: Operator AND expects 16 bits on the LHS, but LHS\'s VARREF \'digit1\' generates 8 bits.\n                                                                                              : ... In instance driver_7segment\nwire [15:0] digit1_rd   = (digit1  & {8{reg_rd[DIGIT1]}})  << (8 & {4{DIGIT1[0]}});\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/185287750/openmsp430/msp_core/driver_7segment.v:204: Operator AND expects 16 bits on the RHS, but RHS\'s REPLICATE generates 8 bits.\n                                                                                              : ... In instance driver_7segment\nwire [15:0] digit1_rd   = (digit1  & {8{reg_rd[DIGIT1]}})  << (8 & {4{DIGIT1[0]}});\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/185287750/openmsp430/msp_core/driver_7segment.v:205: Operator AND expects 16 bits on the LHS, but LHS\'s VARREF \'digit2\' generates 8 bits.\n                                                                                              : ... In instance driver_7segment\nwire [15:0] digit2_rd   = (digit2  & {8{reg_rd[DIGIT2]}})  << (8 & {4{DIGIT2[0]}});\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/185287750/openmsp430/msp_core/driver_7segment.v:205: Operator AND expects 16 bits on the RHS, but RHS\'s REPLICATE generates 8 bits.\n                                                                                              : ... In instance driver_7segment\nwire [15:0] digit2_rd   = (digit2  & {8{reg_rd[DIGIT2]}})  << (8 & {4{DIGIT2[0]}});\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/185287750/openmsp430/msp_core/driver_7segment.v:206: Operator AND expects 16 bits on the LHS, but LHS\'s VARREF \'digit3\' generates 8 bits.\n                                                                                              : ... In instance driver_7segment\nwire [15:0] digit3_rd   = (digit3  & {8{reg_rd[DIGIT3]}})  << (8 & {4{DIGIT3[0]}});\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/185287750/openmsp430/msp_core/driver_7segment.v:206: Operator AND expects 16 bits on the RHS, but RHS\'s REPLICATE generates 8 bits.\n                                                                                              : ... In instance driver_7segment\nwire [15:0] digit3_rd   = (digit3  & {8{reg_rd[DIGIT3]}})  << (8 & {4{DIGIT3[0]}});\n                                   ^\n%Error: Exiting due to 8 warning(s)\n'
module  driver_7segment (


    per_dout,
    seg_a,
    seg_b,
    seg_c,
    seg_d,
    seg_e,
    seg_f,
    seg_g,
    seg_dp,
    seg_an0,
    seg_an1,
    seg_an2,
    seg_an3,


    mclk,
    per_addr,
    per_din,
    per_en,
    per_we,
    puc_rst
);



output      [15:0] per_dout;
output             seg_a;
output             seg_b;
output             seg_c;
output             seg_d;
output             seg_e;
output             seg_f;
output             seg_g;
output             seg_dp;
output             seg_an0;
output             seg_an1;
output             seg_an2;
output             seg_an3;



input              mclk;
input       [13:0] per_addr;
input       [15:0] per_din;
input              per_en;
input        [1:0] per_we;
input              puc_rst;







parameter       [14:0] BASE_ADDR   = 15'h0090;


parameter              DEC_WD      =  2;


parameter [DEC_WD-1:0] DIGIT0      =  'h0,
                       DIGIT1      =  'h1,
                       DIGIT2      =  'h2,
                       DIGIT3      =  'h3;

   

parameter              DEC_SZ      =  2**DEC_WD;
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};


parameter [DEC_SZ-1:0] DIGIT0_D  = (BASE_REG << DIGIT0),
                       DIGIT1_D  = (BASE_REG << DIGIT1), 
                       DIGIT2_D  = (BASE_REG << DIGIT2), 
                       DIGIT3_D  = (BASE_REG << DIGIT3); 







wire              reg_sel      =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);


wire [DEC_WD-1:0] reg_addr     =  {1'b0, per_addr[DEC_WD-2:0]};


wire [DEC_SZ-1:0] reg_dec      = (DIGIT0_D  &  {DEC_SZ{(reg_addr==(DIGIT0 >>1))}}) |
                                 (DIGIT1_D  &  {DEC_SZ{(reg_addr==(DIGIT1 >>1))}}) |
                                 (DIGIT2_D  &  {DEC_SZ{(reg_addr==(DIGIT2 >>1))}}) |
                                 (DIGIT3_D  &  {DEC_SZ{(reg_addr==(DIGIT3 >>1))}});


wire              reg_lo_write =  per_we[0] & reg_sel;
wire              reg_hi_write =  per_we[1] & reg_sel;
wire              reg_read     = ~|per_we   & reg_sel;


wire [DEC_SZ-1:0] reg_hi_wr    = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr    = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd       = reg_dec & {DEC_SZ{reg_read}};








reg  [7:0] digit0;

wire       digit0_wr  = DIGIT0[0] ? reg_hi_wr[DIGIT0] : reg_lo_wr[DIGIT0];
wire [7:0] digit0_nxt = DIGIT0[0] ? per_din[15:8]     : per_din[7:0];

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)        digit0 <=  8'b01111010;
  else if (digit0_wr) digit0 <=  digit0_nxt;

   


reg  [7:0] digit1;

wire       digit1_wr  = DIGIT1[0] ? reg_hi_wr[DIGIT1] : reg_lo_wr[DIGIT1];
wire [7:0] digit1_nxt = DIGIT1[0] ? per_din[15:8]     : per_din[7:0];

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)        digit1 <=  8'b10110110; 
  else if (digit1_wr) digit1 <=  digit1_nxt;

   


reg  [7:0] digit2;

wire       digit2_wr  = DIGIT2[0] ? reg_hi_wr[DIGIT2] : reg_lo_wr[DIGIT2];
wire [7:0] digit2_nxt = DIGIT2[0] ? per_din[15:8]     : per_din[7:0];

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)        digit2 <=  8'b00001010;
  else if (digit2_wr) digit2 <=  digit2_nxt;

   


reg  [7:0] digit3;

wire       digit3_wr  = DIGIT3[0] ? reg_hi_wr[DIGIT3] : reg_lo_wr[DIGIT3];
wire [7:0] digit3_nxt = DIGIT3[0] ? per_din[15:8]     : per_din[7:0];

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)        digit3 <=  8'b01001110; 
  else if (digit3_wr) digit3 <=  digit3_nxt;







wire [15:0] digit0_rd   = (digit0  & {8{reg_rd[DIGIT0]}})  << (8 & {4{DIGIT0[0]}});
wire [15:0] digit1_rd   = (digit1  & {8{reg_rd[DIGIT1]}})  << (8 & {4{DIGIT1[0]}});
wire [15:0] digit2_rd   = (digit2  & {8{reg_rd[DIGIT2]}})  << (8 & {4{DIGIT2[0]}});
wire [15:0] digit3_rd   = (digit3  & {8{reg_rd[DIGIT3]}})  << (8 & {4{DIGIT3[0]}});

wire [15:0] per_dout  =  digit0_rd  |
                         digit1_rd  |
                         digit2_rd  |
                         digit3_rd;

   








reg [23:0] anode_cnt;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) anode_cnt <=  24'h00_0000;
else         anode_cnt <=  anode_cnt+24'h00_0001;


wire [3:0] seg_an  = (4'h1 << anode_cnt[17:16]);
wire       seg_an0 = ~seg_an[0];
wire       seg_an1 = ~seg_an[1];
wire       seg_an2 = ~seg_an[2];
wire       seg_an3 = ~seg_an[3];





wire [7:0] digit  = seg_an[0] ? digit0 :
	            seg_an[1] ? digit1 : 
                    seg_an[2] ? digit2 :
                                digit3;

wire       seg_a  = ~digit[7];
wire       seg_b  = ~digit[6];
wire       seg_c  = ~digit[5];
wire       seg_d  = ~digit[4];
wire       seg_e  = ~digit[3];
wire       seg_f  = ~digit[2];
wire       seg_g  = ~digit[1];
wire       seg_dp = ~digit[0];

	   
endmodule
module  driver_7segment (


    per_dout,
    seg_a,
    seg_b,
    seg_c,
    seg_d,
    seg_e,
    seg_f,
    seg_g,
    seg_dp,
    seg_an0,
    seg_an1,
    seg_an2,
    seg_an3,


    mclk,
    per_addr,
    per_din,
    per_en,
    per_we,
    puc_rst
);




output      [15:0] per_dout;
output             seg_a;
output             seg_b;
output             seg_c;
output             seg_d;
output             seg_e;
output             seg_f;
output             seg_g;
output             seg_dp;
output             seg_an0;
output             seg_an1;
output             seg_an2;
output             seg_an3;



input              mclk;
input       [13:0] per_addr;
input       [15:0] per_din;
input              per_en;
input        [1:0] per_we;
input              puc_rst;







parameter       [14:0] BASE_ADDR   = 15'h0090;


parameter              DEC_WD      =  2;


parameter [DEC_WD-1:0] DIGIT0      =  'h0,
                       DIGIT1      =  'h1,
                       DIGIT2      =  'h2,
                       DIGIT3      =  'h3;

   

parameter              DEC_SZ      =  2**DEC_WD;
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};


parameter [DEC_SZ-1:0] DIGIT0_D  = (BASE_REG << DIGIT0),
                       DIGIT1_D  = (BASE_REG << DIGIT1), 
                       DIGIT2_D  = (BASE_REG << DIGIT2), 
                       DIGIT3_D  = (BASE_REG << DIGIT3); 







wire              reg_sel      =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);


wire [DEC_WD-1:0] reg_addr     =  {1'b0, per_addr[DEC_WD-2:0]};


wire [DEC_SZ-1:0] reg_dec      = (DIGIT0_D  &  {DEC_SZ{(reg_addr==(DIGIT0 >>1))}}) |
                                 (DIGIT1_D  &  {DEC_SZ{(reg_addr==(DIGIT1 >>1))}}) |
                                 (DIGIT2_D  &  {DEC_SZ{(reg_addr==(DIGIT2 >>1))}}) |
                                 (DIGIT3_D  &  {DEC_SZ{(reg_addr==(DIGIT3 >>1))}});


wire              reg_lo_write =  per_we[0] & reg_sel;
wire              reg_hi_write =  per_we[1] & reg_sel;
wire              reg_read     = ~|per_we   & reg_sel;


wire [DEC_SZ-1:0] reg_hi_wr    = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr    = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd       = reg_dec & {DEC_SZ{reg_read}};








reg  [7:0] digit0;

wire       digit0_wr  = DIGIT0[0] ? reg_hi_wr[DIGIT0] : reg_lo_wr[DIGIT0];
wire [7:0] digit0_nxt = DIGIT0[0] ? per_din[15:8]     : per_din[7:0];

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)        digit0 <=  8'b01111010;
  else if (digit0_wr) digit0 <=  digit0_nxt;

   


reg  [7:0] digit1;

wire       digit1_wr  = DIGIT1[0] ? reg_hi_wr[DIGIT1] : reg_lo_wr[DIGIT1];
wire [7:0] digit1_nxt = DIGIT1[0] ? per_din[15:8]     : per_din[7:0];

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)        digit1 <=  8'b10110110; 
  else if (digit1_wr) digit1 <=  digit1_nxt;

   


reg  [7:0] digit2;

wire       digit2_wr  = DIGIT2[0] ? reg_hi_wr[DIGIT2] : reg_lo_wr[DIGIT2];
wire [7:0] digit2_nxt = DIGIT2[0] ? per_din[15:8]     : per_din[7:0];

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)        digit2 <=  8'b00001010;
  else if (digit2_wr) digit2 <=  digit2_nxt;

   


reg  [7:0] digit3;

wire       digit3_wr  = DIGIT3[0] ? reg_hi_wr[DIGIT3] : reg_lo_wr[DIGIT3];
wire [7:0] digit3_nxt = DIGIT3[0] ? per_din[15:8]     : per_din[7:0];

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)        digit3 <=  8'b01001110; 
  else if (digit3_wr) digit3 <=  digit3_nxt;







wire [15:0] digit0_rd   = (digit0  & {8{reg_rd[DIGIT0]}})  << (8 & {4{DIGIT0[0]}});
wire [15:0] digit1_rd   = (digit1  & {8{reg_rd[DIGIT1]}})  << (8 & {4{DIGIT1[0]}});
wire [15:0] digit2_rd   = (digit2  & {8{reg_rd[DIGIT2]}})  << (8 & {4{DIGIT2[0]}});
wire [15:0] digit3_rd   = (digit3  & {8{reg_rd[DIGIT3]}})  << (8 & {4{DIGIT3[0]}});

wire [15:0] per_dout  =  digit0_rd  |
                         digit1_rd  |
                         digit2_rd  |
                         digit3_rd;

   








reg [23:0] anode_cnt;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) anode_cnt <=  24'h00_0000;
else         anode_cnt <=  anode_cnt+24'h00_0001;


wire [3:0] seg_an  = (4'h1 << anode_cnt[17:16]);
wire       seg_an0 = ~seg_an[0];
wire       seg_an1 = ~seg_an[1];
wire       seg_an2 = ~seg_an[2];
wire       seg_an3 = ~seg_an[3];





wire [7:0] digit  = seg_an[0] ? digit0 :
	            seg_an[1] ? digit1 : 
                    seg_an[2] ? digit2 :
                                digit3;

wire       seg_a  = ~digit[7];
wire       seg_b  = ~digit[6];
wire       seg_c  = ~digit[5];
wire       seg_d  = ~digit[4];
wire       seg_e  = ~digit[3];
wire       seg_f  = ~digit[2];
wire       seg_g  = ~digit[1];
wire       seg_dp = ~digit[0];

	   
endmodule