data/full_repos/permissive/103842408/rtl/main/rvm_core_axi4.v
1: b'%Error: data/full_repos/permissive/103842408/rtl/main/rvm_core_axi4.v:11: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.v\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.sv\n             rvm_constants.v\n             rvm_constants.v.v\n             rvm_constants.v.sv\n             obj_dir/rvm_constants.v\n             obj_dir/rvm_constants.v.v\n             obj_dir/rvm_constants.v.sv\n%Error: Exiting due to 1 error(s)\n'
module rvm_core_axi4(


input         ACLK     ,
input         ARESETn  ,

output     [31:0] M_AXI_ARADDR,
input             M_AXI_ARREADY,
output     [ 2:0] M_AXI_ARSIZE,
output            M_AXI_ARVALID,

output     [31:0] M_AXI_AWADDR,
input             M_AXI_AWREADY,
output     [ 2:0] M_AXI_AWSIZE,
output            M_AXI_AWVALID,

output            M_AXI_BREADY,
input      [ 1:0] M_AXI_BRESP,
input             M_AXI_BVALID,

input      [31:0] M_AXI_RDATA,
output            M_AXI_RREADY,
input      [ 1:0] M_AXI_RRESP,
input             M_AXI_RVALID,

output     [31:0] M_AXI_WDATA,
input             M_AXI_WREADY,
output     [ 3:0] M_AXI_WSTRB,
output            M_AXI_WVALID

);

wire [31:0]  mem_addr;
wire [31:0]  mem_rdata;
wire [31:0]  mem_wdata;
wire         mem_c_en;
wire         mem_w_en;
wire [ 3:0]  mem_b_en;
wire         mem_error;
wire         mem_stall;

reg          aw_ready;
reg          wd_ready;
reg          ar_ready;

reg          rd_out;
wire         n_rd_out;

reg          wr_out;
wire         n_wr_out;



assign n_rd_out = rd_out && !M_AXI_RVALID || (mem_c_en && !mem_w_en) ;
assign n_wr_out = wr_out && !M_AXI_BVALID || (mem_c_en &&  mem_w_en) ;

always @(posedge ACLK, negedge ARESETn) begin
    if(!ARESETn) begin
        rd_out <= 1'b0;
    end else begin
        rd_out <= n_rd_out;
    end
end

always @(posedge ACLK, negedge ARESETn) begin
    if(!ARESETn) begin
        wr_out <= 1'b0;
    end else begin
        wr_out <= n_wr_out;
    end
end




always @(posedge ACLK, negedge ARESETn) begin
    if(!ARESETn) begin
        ar_ready <= 1'b0;
    end else begin
        ar_ready <= (ar_ready || M_AXI_ARREADY) && !M_AXI_RVALID;
    end
end




always @(posedge ACLK, negedge ARESETn) begin
    if(!ARESETn) begin
        aw_ready <= 1'b0;
    end else begin
        aw_ready <= (aw_ready || M_AXI_AWREADY) && !M_AXI_BVALID;
    end
end




always @(posedge ACLK, negedge ARESETn) begin
    if(!ARESETn) begin
        wd_ready <= 1'b0;
    end else begin
        wd_ready <= (wd_ready || M_AXI_WREADY) && !M_AXI_BVALID;
    end
end



assign mem_stall        = (wr_out && !M_AXI_BVALID) ||
                          (rd_out && !M_AXI_RVALID) ;

assign mem_error        = M_AXI_BVALID && M_AXI_BRESP != 2'b0 ||
                          M_AXI_RVALID && M_AXI_RRESP != 2'b0  ;



assign M_AXI_BREADY     = 1'b1;
assign M_AXI_RREADY     = 1'b1;


assign M_AXI_ARADDR     = mem_addr;
assign M_AXI_ARSIZE     = 3'b010;
assign M_AXI_ARVALID    = n_rd_out;

assign mem_rdata        = M_AXI_RDATA;


assign M_AXI_AWADDR     = mem_addr;
assign M_AXI_AWSIZE     = 3'b010;
assign M_AXI_AWVALID    = n_wr_out && !aw_ready;

assign M_AXI_WSTRB      = mem_b_en;
assign M_AXI_WDATA      = mem_wdata;
assign M_AXI_WVALID     = n_wr_out && !wd_ready;








rvm_core i_rvm_core(
.clk         (ACLK     ),
.resetn      (ARESETn  ),
.mem_addr    (mem_addr ),
.mem_rdata   (mem_rdata),
.mem_wdata   (mem_wdata),
.mem_c_en    (mem_c_en ),
.mem_w_en    (mem_w_en ),
.mem_b_en    (mem_b_en ),
.mem_error   (mem_error),
.mem_stall   (mem_stall)
);

endmodule
module rvm_core_axi4(


input         ACLK     ,
input         ARESETn  ,

output     [31:0] M_AXI_ARADDR,
input             M_AXI_ARREADY,
output     [ 2:0] M_AXI_ARSIZE,
output            M_AXI_ARVALID,

output     [31:0] M_AXI_AWADDR,
input             M_AXI_AWREADY,
output     [ 2:0] M_AXI_AWSIZE,
output            M_AXI_AWVALID,

output            M_AXI_BREADY,
input      [ 1:0] M_AXI_BRESP,
input             M_AXI_BVALID,

input      [31:0] M_AXI_RDATA,
output            M_AXI_RREADY,
input      [ 1:0] M_AXI_RRESP,
input             M_AXI_RVALID,

output     [31:0] M_AXI_WDATA,
input             M_AXI_WREADY,
output     [ 3:0] M_AXI_WSTRB,
output            M_AXI_WVALID

);


wire [31:0]  mem_addr;
wire [31:0]  mem_rdata;
wire [31:0]  mem_wdata;
wire         mem_c_en;
wire         mem_w_en;
wire [ 3:0]  mem_b_en;
wire         mem_error;
wire         mem_stall;

reg          aw_ready;
reg          wd_ready;
reg          ar_ready;

reg          rd_out;
wire         n_rd_out;

reg          wr_out;
wire         n_wr_out;



assign n_rd_out = rd_out && !M_AXI_RVALID || (mem_c_en && !mem_w_en) ;
assign n_wr_out = wr_out && !M_AXI_BVALID || (mem_c_en &&  mem_w_en) ;

always @(posedge ACLK, negedge ARESETn) begin
    if(!ARESETn) begin
        rd_out <= 1'b0;
    end else begin
        rd_out <= n_rd_out;
    end
end

always @(posedge ACLK, negedge ARESETn) begin
    if(!ARESETn) begin
        wr_out <= 1'b0;
    end else begin
        wr_out <= n_wr_out;
    end
end




always @(posedge ACLK, negedge ARESETn) begin
    if(!ARESETn) begin
        ar_ready <= 1'b0;
    end else begin
        ar_ready <= (ar_ready || M_AXI_ARREADY) && !M_AXI_RVALID;
    end
end




always @(posedge ACLK, negedge ARESETn) begin
    if(!ARESETn) begin
        aw_ready <= 1'b0;
    end else begin
        aw_ready <= (aw_ready || M_AXI_AWREADY) && !M_AXI_BVALID;
    end
end




always @(posedge ACLK, negedge ARESETn) begin
    if(!ARESETn) begin
        wd_ready <= 1'b0;
    end else begin
        wd_ready <= (wd_ready || M_AXI_WREADY) && !M_AXI_BVALID;
    end
end



assign mem_stall        = (wr_out && !M_AXI_BVALID) ||
                          (rd_out && !M_AXI_RVALID) ;

assign mem_error        = M_AXI_BVALID && M_AXI_BRESP != 2'b0 ||
                          M_AXI_RVALID && M_AXI_RRESP != 2'b0  ;



assign M_AXI_BREADY     = 1'b1;
assign M_AXI_RREADY     = 1'b1;


assign M_AXI_ARADDR     = mem_addr;
assign M_AXI_ARSIZE     = 3'b010;
assign M_AXI_ARVALID    = n_rd_out;

assign mem_rdata        = M_AXI_RDATA;


assign M_AXI_AWADDR     = mem_addr;
assign M_AXI_AWSIZE     = 3'b010;
assign M_AXI_AWVALID    = n_wr_out && !aw_ready;

assign M_AXI_WSTRB      = mem_b_en;
assign M_AXI_WDATA      = mem_wdata;
assign M_AXI_WVALID     = n_wr_out && !wd_ready;








rvm_core i_rvm_core(
.clk         (ACLK     ),
.resetn      (ARESETn  ),
.mem_addr    (mem_addr ),
.mem_rdata   (mem_rdata),
.mem_wdata   (mem_wdata),
.mem_c_en    (mem_c_en ),
.mem_w_en    (mem_w_en ),
.mem_b_en    (mem_b_en ),
.mem_error   (mem_error),
.mem_stall   (mem_stall)
);

endmodule