data/full_repos/permissive/167274925/Mux32Bit2To1_tb.v
 line:27: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167274925/Mux32Bit2To1_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #100 inA <= 32\'h00000001; inB <= 32\'h00000002; sel <= 1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167274925/Mux32Bit2To1_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #20 $display("sel=%h, out=%h", sel, out);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/Mux32Bit2To1_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #100 inA <= 32\'h00000001; inB <= 32\'h00000002; sel <= 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/Mux32Bit2To1_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #20 $display("sel=%h, out=%h", sel, out);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/Mux32Bit2To1_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #100 inA <= 32\'hF0000001; inB <= 32\'hF0000002; sel <= 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/Mux32Bit2To1_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #20 $display("sel=%h, out=%h", sel, out);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/Mux32Bit2To1_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #100 inA <= 32\'hF0000001; inB <= 32\'hF0000002; sel <= 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/Mux32Bit2To1_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #20 $display("sel=%h, out=%h", sel, out);\n        ^\n%Error: data/full_repos/permissive/167274925/Mux32Bit2To1_tb.v:16: Cannot find file containing module: \'Mux32Bit2To1\'\n Mux32Bit2To1 u0(\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/Mux32Bit2To1\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/Mux32Bit2To1.v\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/Mux32Bit2To1.sv\n             Mux32Bit2To1\n             Mux32Bit2To1.v\n             Mux32Bit2To1.sv\n             obj_dir/Mux32Bit2To1\n             obj_dir/Mux32Bit2To1.v\n             obj_dir/Mux32Bit2To1.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Mux32Bit2To1_tb();

	reg	[31:0] inA;
	reg	[31:0] inB;
	reg	sel;
    
	wire [31:0]	out;

	Mux32Bit2To1 u0(
        .out(out), 
        .inA(inA), 
        .inB(inB), 
        .sel(sel)
    );
        
	initial begin


        #100 inA <= 32'h00000001; inB <= 32'h00000002; sel <= 1'b0;
        #20 $display("sel=%h, out=%h", sel, out);

        #100 inA <= 32'h00000001; inB <= 32'h00000002; sel <= 1'b1;
        #20 $display("sel=%h, out=%h", sel, out);
        
        #100 inA <= 32'hF0000001; inB <= 32'hF0000002; sel <= 1'b0;
        #20 $display("sel=%h, out=%h", sel, out);

        #100 inA <= 32'hF0000001; inB <= 32'hF0000002; sel <= 1'b1;
        #20 $display("sel=%h, out=%h", sel, out);
       
	end

endmodule
module Mux32Bit2To1_tb();


	reg	[31:0] inA;
	reg	[31:0] inB;
	reg	sel;
    
	wire [31:0]	out;

	Mux32Bit2To1 u0(
        .out(out), 
        .inA(inA), 
        .inB(inB), 
        .sel(sel)
    );
        
	initial begin


        #100 inA <= 32'h00000001; inB <= 32'h00000002; sel <= 1'b0;
        #20 $display("sel=%h, out=%h", sel, out);

        #100 inA <= 32'h00000001; inB <= 32'h00000002; sel <= 1'b1;
        #20 $display("sel=%h, out=%h", sel, out);
        
        #100 inA <= 32'hF0000001; inB <= 32'hF0000002; sel <= 1'b0;
        #20 $display("sel=%h, out=%h", sel, out);

        #100 inA <= 32'hF0000001; inB <= 32'hF0000002; sel <= 1'b1;
        #20 $display("sel=%h, out=%h", sel, out);
       
	end

endmodule