data/full_repos/permissive/117026779/src/MIPS.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/117026779/src/MIPS.v:898: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'MIPS\'\nmodule MIPS(\n       ^~~~\n                                                                      : ... Top module \'MULT\'\nmodule MULT #(parameter WIDTH = 32)(\n       ^~~~\n                                                                      : ... Top module \'DIV\'\nmodule DIV #(parameter WIDTH = 32)(\n       ^~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:754: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n                                                                   : ... In instance MIPS.regfile\nassign read_data_1 = (read_address_1 != 0) ? register_file[read_address_1] : 0;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:755: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n                                                                   : ... In instance MIPS.regfile\nassign read_data_2 = (read_address_2 != 0) ? register_file[read_address_2] : 0;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:774: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n                                                                   : ... In instance MIPS.regfile\n        register_file[write_address] <= write_data;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegWriteDst <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegInSelect <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            PCSrc       <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            MemWrite    <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:587: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            ALUOp       <= 1\'bx;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegWriteDst <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegInSelect <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            PCSrc       <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            MemWrite    <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:614: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            ALUOp       <= 1\'bx;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegWriteDst <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            RegInSelect <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            PCSrc       <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            MemWrite    <= 1\'bx; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:674: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance MIPS.decoder\n            ALUOp       <= 1\'bx;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:194: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'write_address\' generates 5 bits.\n                                                                   : ... In instance MIPS\nassign RegWriteAddress              = write_address;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:241: Operator AND expects 32 bits on the RHS, but RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                   : ... In instance MIPS\nwire [32-1:0] DataBusByte = DataBusByteShifted & 8\'hFF;\n                                               ^\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:266: Cannot find file containing module: \'REGISTER\'\nREGISTER #(.WIDTH(32)) pc_register (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/REGISTER\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/REGISTER.v\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/REGISTER.sv\n             REGISTER\n             REGISTER.v\n             REGISTER.sv\n             obj_dir/REGISTER\n             obj_dir/REGISTER.v\n             obj_dir/REGISTER.sv\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:280: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/MIPS.v:325: Input port connection \'a\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'branch_pc_offset\' generates 32 bits.\n                                                                   : ... In instance MIPS\n .a(branch_pc_offset),\n  ^\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:335: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:344: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:366: Cannot find file containing module: \'OR\'\nOR #(.WIDTH(4)\n^~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:372: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:385: Cannot find file containing module: \'TRIBUFFER\'\nTRIBUFFER #(.WIDTH(32)\n^~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/MIPS.v:403: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: Exiting due to 8 error(s), 22 warning(s)\n'
module PROCESSOR_DECODER(
    input wire [`OP_CODE_WIDTH-1:0]  opcode,
    input wire [`FUNCTION_WIDTH-1:0] funct,
    input wire [`REGISTER_WIDTH-1:0] alu_result,
    input wire                      zero,
    input wire                      less_than_eq,
    input wire                      greater_than,
    output wire                     BusCycle,
    output reg [1:0]                RegWriteDst,
    output reg [1:0]                RegInSelect,
    output reg [1:0]                PCSrc,
    output reg                      ALUSrc,
    output reg                      SignExtImm,
    output reg                      RegWrite,
    output reg [3:0]                MemWrite,
    output reg                      MemRead,
    output reg [`ALU_OP_CODE_WIDTH-1:0]  ALUOp
);







assign BusCycle = (MemRead | (|MemWrite));

`define ALUSRC_FOR_RTYPE            0
`define ALUSRC_FOR_ITYPE            1

`define REGWRITEDST_FROM_RTYPE      0
`define REGWRITEDST_FROM_ITYPE      1
`define REGWRITEDST_RETURN_ADDR     2

`define PCSRC_NEXT_PC               0
`define PCSRC_BRANCH_PC             1
`define PCSRC_JUMP_PC_IMMEDIATE     2
`define PCSRC_JUMP_PC_REGISTER      3

`define REGIN_ALU_RESULT            0
`define REGIN_DATABUS               1
`define REGIN_STORE_NEXT_PC         2
`define REGIN_DATABUS_BYTE_ACCESS   3

`define ALU_NULL_OPCODE             `ALU_OP_CODE_WIDTH'b0

`define UNSUPPORTED_OPERATIONS   \
            RegWrite    <= 1'bx; \
            SignExtImm  <= 1'bx; \
            RegWriteDst <= 1'bx; \
            ALUSrc      <= 1'bx; \
            RegInSelect <= 1'bx; \
            PCSrc       <= 1'bx; \
            MemWrite    <= 1'bx; \
            MemRead     <= 1'bx; \
            ALUOp       <= 1'bx

wire [`ALU_OP_CODE_WIDTH-1:0] immediate_funct;

IMMEDIATE_TO_ALU_CONVERTER imm_to_alu (
    .opcode(opcode),
    .instruction_function(funct),
    .alu_funct(immediate_funct)
);

always @(*)
begin
    case(opcode)
        `OP_TYPE_R: begin
            RegWrite    <= 1;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_RTYPE;
            ALUSrc      <= `ALUSRC_FOR_RTYPE;
            RegInSelect <= `REGIN_ALU_RESULT;
            case(funct)
                `FUNCTION_OP_JR,
                `FUNCTION_OP_JALR: begin
                    PCSrc       <= `PCSRC_JUMP_PC_REGISTER;
                end
                default: begin
                    PCSrc       <= 0;
                end
            endcase
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= funct;
        end
        `OP_ADDI,
        `OP_ADDIU,
        `OP_SLTI,
        `OP_SLTIU,
        `OP_LUI: begin
            RegWrite    <= 1;
            SignExtImm  <= 1;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= `REGIN_ALU_RESULT;
            PCSrc       <= 0;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= immediate_funct;
        end
        `OP_ANDI,
        `OP_ORI,
        `OP_XORI: begin
            RegWrite    <= 1;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= `REGIN_ALU_RESULT;
            PCSrc       <= 0;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= immediate_funct;
        end
        `OP_BEQ: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= 0;
            ALUSrc      <= 0;
            RegInSelect <= 0;
            PCSrc       <= (zero) ? `PCSRC_BRANCH_PC : `PCSRC_NEXT_PC;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_SUB;
        end
        `OP_BNE: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= 0;
            ALUSrc      <= 0;
            RegInSelect <= 0;
            PCSrc       <= (!zero) ? `PCSRC_BRANCH_PC : `PCSRC_NEXT_PC;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_SUB;
        end
        `OP_BGTZ: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= 0;
            ALUSrc      <= 0;
            RegInSelect <= 0;
            PCSrc       <= (greater_than) ? `PCSRC_BRANCH_PC : `PCSRC_NEXT_PC;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_SUB;
        end
        `OP_BLEZ: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= 0;
            ALUSrc      <= 0;
            RegInSelect <= 0;
            PCSrc       <= (less_than_eq) ? `PCSRC_BRANCH_PC : `PCSRC_NEXT_PC;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_SUB;
        end
        `OP_BGEZAL,
        `OP_BLTZAL: begin
            `UNSUPPORTED_OPERATIONS;
        end
        `OP_J: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= 0;
            ALUSrc      <= 0;
            RegInSelect <= 0;
            PCSrc       <= `PCSRC_JUMP_PC_IMMEDIATE;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `ALU_NULL_OPCODE;
        end
        `OP_JAL: begin
            RegWrite    <= 1;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_RETURN_ADDR;
            ALUSrc      <= 0;
            RegInSelect <= `REGIN_STORE_NEXT_PC;
            PCSrc       <= `PCSRC_JUMP_PC_IMMEDIATE;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `ALU_NULL_OPCODE;
        end
        `OP_LH,
        `OP_LHU,
        `OP_LL:begin
            `UNSUPPORTED_OPERATIONS;
        end

        `OP_LBU,
        `OP_LB: begin
            RegWrite    <= 1;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= `REGIN_DATABUS_BYTE_ACCESS;
            PCSrc       <= 0;
            MemWrite    <= 0;
            MemRead     <= 1;
            ALUOp       <= `FUNCTION_OP_ADD;
        end
        `OP_LW: begin
            RegWrite    <= 1;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= `REGIN_DATABUS;
            PCSrc       <= 0;
            MemWrite    <= 0;
            MemRead     <= 1;
            ALUOp       <= `FUNCTION_OP_ADD;
        end
        `OP_SB: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= 0;
            PCSrc       <= 0;
            MemWrite    <= 4'b0001 << alu_result[1:0];
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_ADD;
        end
        `OP_SH: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= 0;
            PCSrc       <= 0;
            MemWrite    <= 4'b0011 << (alu_result[1] << 1);
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_ADD;
        end
        `OP_SW: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= 0;
            PCSrc       <= 0;
            MemWrite    <= 4'b1111;
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_ADD;
        end
        default: begin
            `UNSUPPORTED_OPERATIONS;
        end
    endcase
end
endmodule
module PROCESSOR_DECODER(
    input wire [`OP_CODE_WIDTH-1:0]  opcode,
    input wire [`FUNCTION_WIDTH-1:0] funct,
    input wire [`REGISTER_WIDTH-1:0] alu_result,
    input wire                      zero,
    input wire                      less_than_eq,
    input wire                      greater_than,
    output wire                     BusCycle,
    output reg [1:0]                RegWriteDst,
    output reg [1:0]                RegInSelect,
    output reg [1:0]                PCSrc,
    output reg                      ALUSrc,
    output reg                      SignExtImm,
    output reg                      RegWrite,
    output reg [3:0]                MemWrite,
    output reg                      MemRead,
    output reg [`ALU_OP_CODE_WIDTH-1:0]  ALUOp
);








assign BusCycle = (MemRead | (|MemWrite));

`define ALUSRC_FOR_RTYPE            0
`define ALUSRC_FOR_ITYPE            1

`define REGWRITEDST_FROM_RTYPE      0
`define REGWRITEDST_FROM_ITYPE      1
`define REGWRITEDST_RETURN_ADDR     2

`define PCSRC_NEXT_PC               0
`define PCSRC_BRANCH_PC             1
`define PCSRC_JUMP_PC_IMMEDIATE     2
`define PCSRC_JUMP_PC_REGISTER      3

`define REGIN_ALU_RESULT            0
`define REGIN_DATABUS               1
`define REGIN_STORE_NEXT_PC         2
`define REGIN_DATABUS_BYTE_ACCESS   3

`define ALU_NULL_OPCODE             `ALU_OP_CODE_WIDTH'b0

`define UNSUPPORTED_OPERATIONS   \
            RegWrite    <= 1'bx; \
            SignExtImm  <= 1'bx; \
            RegWriteDst <= 1'bx; \
            ALUSrc      <= 1'bx; \
            RegInSelect <= 1'bx; \
            PCSrc       <= 1'bx; \
            MemWrite    <= 1'bx; \
            MemRead     <= 1'bx; \
            ALUOp       <= 1'bx

wire [`ALU_OP_CODE_WIDTH-1:0] immediate_funct;

IMMEDIATE_TO_ALU_CONVERTER imm_to_alu (
    .opcode(opcode),
    .instruction_function(funct),
    .alu_funct(immediate_funct)
);

always @(*)
begin
    case(opcode)
        `OP_TYPE_R: begin
            RegWrite    <= 1;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_RTYPE;
            ALUSrc      <= `ALUSRC_FOR_RTYPE;
            RegInSelect <= `REGIN_ALU_RESULT;
            case(funct)
                `FUNCTION_OP_JR,
                `FUNCTION_OP_JALR: begin
                    PCSrc       <= `PCSRC_JUMP_PC_REGISTER;
                end
                default: begin
                    PCSrc       <= 0;
                end
            endcase
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= funct;
        end
        `OP_ADDI,
        `OP_ADDIU,
        `OP_SLTI,
        `OP_SLTIU,
        `OP_LUI: begin
            RegWrite    <= 1;
            SignExtImm  <= 1;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= `REGIN_ALU_RESULT;
            PCSrc       <= 0;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= immediate_funct;
        end
        `OP_ANDI,
        `OP_ORI,
        `OP_XORI: begin
            RegWrite    <= 1;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= `REGIN_ALU_RESULT;
            PCSrc       <= 0;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= immediate_funct;
        end
        `OP_BEQ: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= 0;
            ALUSrc      <= 0;
            RegInSelect <= 0;
            PCSrc       <= (zero) ? `PCSRC_BRANCH_PC : `PCSRC_NEXT_PC;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_SUB;
        end
        `OP_BNE: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= 0;
            ALUSrc      <= 0;
            RegInSelect <= 0;
            PCSrc       <= (!zero) ? `PCSRC_BRANCH_PC : `PCSRC_NEXT_PC;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_SUB;
        end
        `OP_BGTZ: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= 0;
            ALUSrc      <= 0;
            RegInSelect <= 0;
            PCSrc       <= (greater_than) ? `PCSRC_BRANCH_PC : `PCSRC_NEXT_PC;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_SUB;
        end
        `OP_BLEZ: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= 0;
            ALUSrc      <= 0;
            RegInSelect <= 0;
            PCSrc       <= (less_than_eq) ? `PCSRC_BRANCH_PC : `PCSRC_NEXT_PC;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_SUB;
        end
        `OP_BGEZAL,
        `OP_BLTZAL: begin
            `UNSUPPORTED_OPERATIONS;
        end
        `OP_J: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= 0;
            ALUSrc      <= 0;
            RegInSelect <= 0;
            PCSrc       <= `PCSRC_JUMP_PC_IMMEDIATE;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `ALU_NULL_OPCODE;
        end
        `OP_JAL: begin
            RegWrite    <= 1;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_RETURN_ADDR;
            ALUSrc      <= 0;
            RegInSelect <= `REGIN_STORE_NEXT_PC;
            PCSrc       <= `PCSRC_JUMP_PC_IMMEDIATE;
            MemWrite    <= 0;
            MemRead     <= 0;
            ALUOp       <= `ALU_NULL_OPCODE;
        end
        `OP_LH,
        `OP_LHU,
        `OP_LL:begin
            `UNSUPPORTED_OPERATIONS;
        end

        `OP_LBU,
        `OP_LB: begin
            RegWrite    <= 1;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= `REGIN_DATABUS_BYTE_ACCESS;
            PCSrc       <= 0;
            MemWrite    <= 0;
            MemRead     <= 1;
            ALUOp       <= `FUNCTION_OP_ADD;
        end
        `OP_LW: begin
            RegWrite    <= 1;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= `REGIN_DATABUS;
            PCSrc       <= 0;
            MemWrite    <= 0;
            MemRead     <= 1;
            ALUOp       <= `FUNCTION_OP_ADD;
        end
        `OP_SB: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= 0;
            PCSrc       <= 0;
            MemWrite    <= 4'b0001 << alu_result[1:0];
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_ADD;
        end
        `OP_SH: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= 0;
            PCSrc       <= 0;
            MemWrite    <= 4'b0011 << (alu_result[1] << 1);
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_ADD;
        end
        `OP_SW: begin
            RegWrite    <= 0;
            SignExtImm  <= 0;
            RegWriteDst <= `REGWRITEDST_FROM_ITYPE;
            ALUSrc      <= `ALUSRC_FOR_ITYPE;
            RegInSelect <= 0;
            PCSrc       <= 0;
            MemWrite    <= 4'b1111;
            MemRead     <= 0;
            ALUOp       <= `FUNCTION_OP_ADD;
        end
        default: begin
            `UNSUPPORTED_OPERATIONS;
        end
    endcase
end
endmodule