data/full_repos/permissive/139213403/FPGA/sseg_array.v
1: b"%Error: data/full_repos/permissive/139213403/FPGA/sseg_array.v:32: Cannot find file containing module: 'pwm'\n pwm #(.N(PWM_BITS), .M(SSEG_N + SSEG_LEDS_N)) pwm1(.clk(clk), .reset(reset), .in({ cur_oe, cur_sseg }), .w(brightness), .out({ oe, o_sseg })); \n ^~~\n        ... Looked in:\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/pwm\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/pwm.v\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/pwm.sv\n             pwm\n             pwm.v\n             pwm.sv\n             obj_dir/pwm\n             obj_dir/pwm.v\n             obj_dir/pwm.sv\n%Error: data/full_repos/permissive/139213403/FPGA/sseg_array.v:33: Cannot find file containing module: 'sseg'\n sseg encoder(.num(val), .en(en), .sign(sign), .dp(dp), .hex(val_enc));\n ^~~~\n%Error: data/full_repos/permissive/139213403/FPGA/sseg_array.v:34: Cannot find file containing module: 'mod_m_counter'\n mod_m_counter #(.M_BITS(LED_PERIOD_BITS)) tick_counter(.clk(clk), .reset(reset), .m(led_period), .max_tick(led_tick), .q());\n ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module sseg_array
#(
	parameter SSEG_BITS=2,
	          SSEG_N=3,
				 

				 PWM_BITS=12,
				 LED_PERIOD_BITS=24
)
(
	input wire clk, reset,
	input wire wr,
	input wire [PWM_BITS-1:0] brightness,
	input wire [SSEG_BITS-1:0] sel,
	input wire [LED_PERIOD_BITS-1:0] led_period,
	input wire en, sign, dp,
	input wire [3:0] val,
	output wire [7:0] o_sseg,
	output wire [SSEG_N-1:0] oe,
	output reg done_tick
);
	localparam SSEG_LEDS_N = 8;

	reg [SSEG_LEDS_N-1:0] sseg_arr_reg [SSEG_N-1:0];
	reg [SSEG_BITS-1:0] oe_i_reg, oe_i_next;
	reg done_reg;
	wire [SSEG_LEDS_N-1:0] val_enc;
	wire [SSEG_LEDS_N-1:0] cur_sseg;
	wire [SSEG_N-1:0] cur_oe;
	wire led_tick;
	
	pwm #(.N(PWM_BITS), .M(SSEG_N + SSEG_LEDS_N)) pwm1(.clk(clk), .reset(reset), .in({ cur_oe, cur_sseg }), .w(brightness), .out({ oe, o_sseg })); 
	sseg encoder(.num(val), .en(en), .sign(sign), .dp(dp), .hex(val_enc));
	mod_m_counter #(.M_BITS(LED_PERIOD_BITS)) tick_counter(.clk(clk), .reset(reset), .m(led_period), .max_tick(led_tick), .q());
		

	always @(posedge clk)
		if (wr)
			begin
				$display("val: val=%b sel=%b -> %b", {en, sign, dp, val }, sel, val_enc);
				sseg_arr_reg[sel] <= val_enc;
			end
			

	always @(posedge clk, posedge reset)
		if (reset)
			oe_i_reg <= 0;
		else
			oe_i_reg <= oe_i_next;
				

	always @*
		begin
			oe_i_next = oe_i_reg;
			done_tick = 0;
			if (led_tick)
				begin
					oe_i_next = oe_i_reg + 1'b1;
					if (oe_i_next == SSEG_N)
						begin
							oe_i_next = 0;
							done_tick = 1'b1;
						end
				end
		end
		
	assign cur_sseg = sseg_arr_reg[oe_i_reg];
	assign cur_oe = (sseg_arr_reg[oe_i_reg] > 0) ? (1 << oe_i_reg) : 0;

endmodule
module sseg_array
#(
	parameter SSEG_BITS=2,
	          SSEG_N=3,
				 

				 PWM_BITS=12,
				 LED_PERIOD_BITS=24
)
(
	input wire clk, reset,
	input wire wr,
	input wire [PWM_BITS-1:0] brightness,
	input wire [SSEG_BITS-1:0] sel,
	input wire [LED_PERIOD_BITS-1:0] led_period,
	input wire en, sign, dp,
	input wire [3:0] val,
	output wire [7:0] o_sseg,
	output wire [SSEG_N-1:0] oe,
	output reg done_tick
);

	localparam SSEG_LEDS_N = 8;

	reg [SSEG_LEDS_N-1:0] sseg_arr_reg [SSEG_N-1:0];
	reg [SSEG_BITS-1:0] oe_i_reg, oe_i_next;
	reg done_reg;
	wire [SSEG_LEDS_N-1:0] val_enc;
	wire [SSEG_LEDS_N-1:0] cur_sseg;
	wire [SSEG_N-1:0] cur_oe;
	wire led_tick;
	
	pwm #(.N(PWM_BITS), .M(SSEG_N + SSEG_LEDS_N)) pwm1(.clk(clk), .reset(reset), .in({ cur_oe, cur_sseg }), .w(brightness), .out({ oe, o_sseg })); 
	sseg encoder(.num(val), .en(en), .sign(sign), .dp(dp), .hex(val_enc));
	mod_m_counter #(.M_BITS(LED_PERIOD_BITS)) tick_counter(.clk(clk), .reset(reset), .m(led_period), .max_tick(led_tick), .q());
		

	always @(posedge clk)
		if (wr)
			begin
				$display("val: val=%b sel=%b -> %b", {en, sign, dp, val }, sel, val_enc);
				sseg_arr_reg[sel] <= val_enc;
			end
			

	always @(posedge clk, posedge reset)
		if (reset)
			oe_i_reg <= 0;
		else
			oe_i_reg <= oe_i_next;
				

	always @*
		begin
			oe_i_next = oe_i_reg;
			done_tick = 0;
			if (led_tick)
				begin
					oe_i_next = oe_i_reg + 1'b1;
					if (oe_i_next == SSEG_N)
						begin
							oe_i_next = 0;
							done_tick = 1'b1;
						end
				end
		end
		
	assign cur_sseg = sseg_arr_reg[oe_i_reg];
	assign cur_oe = (sseg_arr_reg[oe_i_reg] > 0) ? (1 << oe_i_reg) : 0;

endmodule