data/full_repos/permissive/106583614/Lab3/VGAVsync.v
 line:67: before: "/"
1: b"%Error: data/full_repos/permissive/106583614/Lab3/VGAVsync.v:34: Cannot find file containing module: 'VGAHsync'\n VGAHsync vga_hsync_0(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAHsync\n             data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAHsync.v\n             data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAHsync.sv\n             VGAHsync\n             VGAHsync.v\n             VGAHsync.sv\n             obj_dir/VGAHsync\n             obj_dir/VGAHsync.v\n             obj_dir/VGAHsync.sv\n%Error: Exiting due to 1 error(s)\n"
module VGAVsync(
	clk,
	reset,
	vga_red_0,
	vga_red_1,
	vga_red_2,
	vga_green_0,
	vga_green_1,
	vga_green_2,
	vga_blue_1,
	vga_blue_2,
	h_sync,
	v_sync
);

	input clk, reset;

	output vga_red_0, vga_red_1, vga_red_2;
	output vga_green_0, vga_green_1, vga_green_2;
	output vga_blue_1, vga_blue_2;
	output wire v_sync; 
	output wire h_sync;


	reg [19:0] master_vsync_count;
	wire h_sync_en;


	VGAHsync vga_hsync_0(
		.clk(clk) ,
		.reset(reset) ,
		.h_sync(h_sync) ,
		.vga_red_0( vga_red_0),
		.vga_red_1( vga_red_1) ,
		.vga_red_2( vga_red_2) ,
		.vga_green_0 (vga_green_0),
		.vga_green_1 (vga_green_1),
		.vga_green_2 (vga_green_2),
		.vga_blue_1	(vga_blue_1),
		.vga_blue_2	(vga_blue_2),
		.h_sync_en(h_sync_en)
	);


	always @(posedge clk or posedge reset) begin
		if (reset) begin
			master_vsync_count <= 0;
		end else begin
			master_vsync_count <= master_vsync_count + 1;
			if (master_vsync_count == 833599) begin
				master_vsync_count <= 0;
			end
		end
	end


	assign v_sync = ( (master_vsync_count >= 20'd0) && (master_vsync_count <= 20'd3199) ) ? 0 : 1;


	assign h_sync_en = ( (master_vsync_count > 20'd49599) && (master_vsync_count <= 20'd817599) ) ? 1 : 0;

endmodule
module VGAVsync(
	clk,
	reset,
	vga_red_0,
	vga_red_1,
	vga_red_2,
	vga_green_0,
	vga_green_1,
	vga_green_2,
	vga_blue_1,
	vga_blue_2,
	h_sync,
	v_sync
);


	input clk, reset;

	output vga_red_0, vga_red_1, vga_red_2;
	output vga_green_0, vga_green_1, vga_green_2;
	output vga_blue_1, vga_blue_2;
	output wire v_sync; 
	output wire h_sync;


	reg [19:0] master_vsync_count;
	wire h_sync_en;


	VGAHsync vga_hsync_0(
		.clk(clk) ,
		.reset(reset) ,
		.h_sync(h_sync) ,
		.vga_red_0( vga_red_0),
		.vga_red_1( vga_red_1) ,
		.vga_red_2( vga_red_2) ,
		.vga_green_0 (vga_green_0),
		.vga_green_1 (vga_green_1),
		.vga_green_2 (vga_green_2),
		.vga_blue_1	(vga_blue_1),
		.vga_blue_2	(vga_blue_2),
		.h_sync_en(h_sync_en)
	);


	always @(posedge clk or posedge reset) begin
		if (reset) begin
			master_vsync_count <= 0;
		end else begin
			master_vsync_count <= master_vsync_count + 1;
			if (master_vsync_count == 833599) begin
				master_vsync_count <= 0;
			end
		end
	end


	assign v_sync = ( (master_vsync_count >= 20'd0) && (master_vsync_count <= 20'd3199) ) ? 0 : 1;


	assign h_sync_en = ( (master_vsync_count > 20'd49599) && (master_vsync_count <= 20'd817599) ) ? 1 : 0;

endmodule