data/full_repos/permissive/143278/ivltests/pr979.v
None: at end of input
data/verilator_xmls/2106dc64-b164-45f6-b1c9-c281d31cb0a8.xml
module test();
real r;

initial
begin
r=0.25;
$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));
r=0.5;
$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));

$display("neg reals don't work");
r=-0.25;
$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));
r=-0.5;
$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));

end
endmodule
module test();

real r;

initial
begin
r=0.25;
$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));
r=0.5;
$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));

$display("neg reals don't work");
r=-0.25;
$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));
r=-0.5;
$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));

end
endmodule