data/full_repos/permissive/143278/ivltests/pr1755593.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1755593.v:14: Unsupported: Ignoring delay on this delayed statement.\n     #1 if (out !== data[sel]) begin\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire out;
   reg [4:0] data;
   reg [2:0] sel;

   test U1(out, data[0], data[1], data[2], data[3], sel[0], sel[1]);

   initial begin
      for (sel=0 ; sel<4 ; sel=sel+1)
	 for (data=0 ; data<16 ; data=data+1) begin
	    #1 if (out !== data[sel]) begin
	       $display("FAILED -- data=%b, sel=%d", data, sel);
	       $finish;
	    end
	 end

      $display("PASSED");
   end

endmodule
module main;


   wire out;
   reg [4:0] data;
   reg [2:0] sel;

   test U1(out, data[0], data[1], data[2], data[3], sel[0], sel[1]);

   initial begin
      for (sel=0 ; sel<4 ; sel=sel+1)
	 for (data=0 ; data<16 ; data=data+1) begin
	    #1 if (out !== data[sel]) begin
	       $display("FAILED -- data=%b, sel=%d", data, sel);
	       $finish;
	    end
	 end

      $display("PASSED");
   end

endmodule