data/full_repos/permissive/123528630/Sources/clock_divider.v
data/verilator_xmls/b2f6bb85-7c36-40c0-84cf-81a1c9f51856.xml
module clock_divider(
    input clk_i,
    input [3:0] div,
    input rst,
    output [0:0] clk_o
    );
reg [3:0] p_div;
reg [3:0] n_div;
assign clk_o= !(p_div[1] & n_div[1]);
always @ (posedge clk_i)
begin
    if (rst == 1) 
    begin
        p_div<=4'b0001;
    end
    else
    begin
        if (p_div==div)
        begin
            p_div<=4'b0001;
        end
        else
        begin
            p_div<=p_div+4'b0001;
        end
    end   
end

always @ (negedge clk_i)
begin
    if (rst == 1) 
    begin
        n_div<=4'b0001;
    end
    else
    begin
        if (n_div==div)
        begin
            n_div<=4'b0001;
        end
        else
        begin
            n_div<=n_div+4'b0001;
        end
    end   
end


endmodule
module clock_divider(
    input clk_i,
    input [3:0] div,
    input rst,
    output [0:0] clk_o
    );

reg [3:0] p_div;
reg [3:0] n_div;
assign clk_o= !(p_div[1] & n_div[1]);
always @ (posedge clk_i)
begin
    if (rst == 1) 
    begin
        p_div<=4'b0001;
    end
    else
    begin
        if (p_div==div)
        begin
            p_div<=4'b0001;
        end
        else
        begin
            p_div<=p_div+4'b0001;
        end
    end   
end

always @ (negedge clk_i)
begin
    if (rst == 1) 
    begin
        n_div<=4'b0001;
    end
    else
    begin
        if (n_div==div)
        begin
            n_div<=4'b0001;
        end
        else
        begin
            n_div<=n_div+4'b0001;
        end
    end   
end


endmodule