data/full_repos/permissive/116266634/mip_data_mem_testnebch.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/116266634/mip_data_mem_testnebch.v:14: Unsupported: Ignoring delay on this delayed statement.\nmem_write = 1\'b1; #50;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116266634/mip_data_mem_testnebch.v:19: Unsupported: Ignoring delay on this delayed statement.\nmem_write = 1\'b0; #50;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/116266634/mip_data_mem_testnebch.v:24: Unsupported: Ignoring delay on this delayed statement.\nmem_write = 1\'b1; #50\n                  ^\n%Error: data/full_repos/permissive/116266634/mip_data_mem_testnebch.v:35: Unsupported or unknown PLI call: $monitor\n$monitor("MEMADRESS: %32b----WRITEDATA: %32b\\nMEMREAD: %1b--MEMWRITE: %1b------READDATA: %32b\\n\\n",mem_address,write_data,mem_read,mem_write,read_data);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mip_data_mem_testnebch();

wire [31:0] read_data;
reg [31:0] mem_address, write_data;
reg mem_read, mem_write;

mips_data_mem test(read_data, mem_address, write_data, mem_read, mem_write);


initial begin
mem_address = 32'b00000000000000000000000000010101;
write_data  = 32'b11111101111111111111111111111111;
mem_read = 1'b0;
mem_write = 1'b1; #50;

mem_address = 32'b00000000000000000000000000010101;
write_data  = 32'b11111101111111111111111111111111;
mem_read = 1'b1;
mem_write = 1'b0; #50;

mem_address = 32'b00000000000000000000000000010101;
write_data  = 32'b11111101111111111111111111111111;
mem_read = 1'b1;
mem_write = 1'b1; #50

mem_address = 32'b00000000000000000000000000010101;
write_data  = 32'b11111101111111111111111111111111;
mem_read = 1'b0;
mem_write = 1'b0; 
 
end

initial begin 

$monitor("MEMADRESS: %32b----WRITEDATA: %32b\nMEMREAD: %1b--MEMWRITE: %1b------READDATA: %32b\n\n",mem_address,write_data,mem_read,mem_write,read_data);

end

endmodule
module mip_data_mem_testnebch();


wire [31:0] read_data;
reg [31:0] mem_address, write_data;
reg mem_read, mem_write;

mips_data_mem test(read_data, mem_address, write_data, mem_read, mem_write);


initial begin
mem_address = 32'b00000000000000000000000000010101;
write_data  = 32'b11111101111111111111111111111111;
mem_read = 1'b0;
mem_write = 1'b1; #50;

mem_address = 32'b00000000000000000000000000010101;
write_data  = 32'b11111101111111111111111111111111;
mem_read = 1'b1;
mem_write = 1'b0; #50;

mem_address = 32'b00000000000000000000000000010101;
write_data  = 32'b11111101111111111111111111111111;
mem_read = 1'b1;
mem_write = 1'b1; #50

mem_address = 32'b00000000000000000000000000010101;
write_data  = 32'b11111101111111111111111111111111;
mem_read = 1'b0;
mem_write = 1'b0; 
 
end

initial begin 

$monitor("MEMADRESS: %32b----WRITEDATA: %32b\nMEMREAD: %1b--MEMWRITE: %1b------READDATA: %32b\n\n",mem_address,write_data,mem_read,mem_write,read_data);

end

endmodule