data/full_repos/permissive/175122930/uart_tx_tb.v
 line:27: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/175122930/uart_tx_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #2 clock = ~clock;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/175122930/uart_tx_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #5000 $finish;\n  ^\n%Error: data/full_repos/permissive/175122930/uart_tx_tb.v:31: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("uart_tx_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/175122930/uart_tx_tb.v:32: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars (0, uart_tx_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/175122930/uart_tx_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/uart_tx_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #2\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/uart_tx_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #20 reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/uart_tx_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/uart_tx_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/uart_tx_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/uart_tx_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/uart_tx_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Error: data/full_repos/permissive/175122930/uart_tx_tb.v:56: syntax error, unexpected \'@\'\n  @(negedge ready);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/uart_tx_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Error: Exiting due to 3 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_tx_tb ();
	reg clock;
	reg [7:0] read_data;
	reg read_clock_enable;
	reg reset;
	wire ready;
	wire tx;
	wire uart_clock;

	uart_tx #(.CLOCK_FREQ(2_400), .BAUD_RATE(1_200))
		UART (
			.reset(reset),
			.clock(clock),
			.read_data(read_data),
			.read_clock_enable(read_clock_enable),
			.tx(tx),
			.ready(ready),
			.uart_clock(uart_clock));

	always
		#2 clock = ~clock;

	initial begin
		#5000 $finish;
	end

	initial begin
		$dumpfile ("uart_tx_tb.vcd");
		$dumpvars (0, uart_tx_tb);
		clock = 0;
		reset = 0;
		read_data = 8'hb7;
		read_clock_enable = 1;
		#10
		if (ready == 'b1) begin
			$display("ready in reset is high. Expected: low");
			$stop;
		end
		#2
		read_clock_enable = 0;
		#20 reset = 1;
		#2;
		#2;
		#2;
		reset = 1;
		#500;
		if (ready == 'b0) begin
			$display("ready after reset is low. Expected: high");
			$stop;
		end
		#2;
		read_clock_enable = 1;
		@(negedge ready);
		read_clock_enable = 0;
		#2000;

		$finish;
	end
endmodule
module uart_tx_tb ();

	reg clock;
	reg [7:0] read_data;
	reg read_clock_enable;
	reg reset;
	wire ready;
	wire tx;
	wire uart_clock;

	uart_tx #(.CLOCK_FREQ(2_400), .BAUD_RATE(1_200))
		UART (
			.reset(reset),
			.clock(clock),
			.read_data(read_data),
			.read_clock_enable(read_clock_enable),
			.tx(tx),
			.ready(ready),
			.uart_clock(uart_clock));

	always
		#2 clock = ~clock;

	initial begin
		#5000 $finish;
	end

	initial begin
		$dumpfile ("uart_tx_tb.vcd");
		$dumpvars (0, uart_tx_tb);
		clock = 0;
		reset = 0;
		read_data = 8'hb7;
		read_clock_enable = 1;
		#10
		if (ready == 'b1) begin
			$display("ready in reset is high. Expected: low");
			$stop;
		end
		#2
		read_clock_enable = 0;
		#20 reset = 1;
		#2;
		#2;
		#2;
		reset = 1;
		#500;
		if (ready == 'b0) begin
			$display("ready after reset is low. Expected: high");
			$stop;
		end
		#2;
		read_clock_enable = 1;
		@(negedge ready);
		read_clock_enable = 0;
		#2000;

		$finish;
	end
endmodule