data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:15: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:29: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:43: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:60: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:77: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:93: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MULTITOP: data/full_repos/permissive/148324174/HDLBits/Circuits/Counter.v:106: Multiple top level modules\n                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                      : ... Top module \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'decade\'\nmodule decade(\n       ^~~~~~\n%Error: Exiting due to 7 warning(s)\n'
module top_module (
    input clk,
    input reset,
    output [3:1] ena,
    output [15:0] q);
    decade U1(clk, reset, 1'b1, q[3:0]);
    decade U2(clk, reset, ena[1], q[7:4]);
    decade U3(clk, reset, ena[2], q[11:8]);
    decade U4(clk, reset, ena[3], q[15:12]);
    assign ena[1] = (q[3:0] == 4'h9);
    assign ena[2] = (q[7:0] == 8'h99);
    assign ena[3] = (q[11:0] == 12'h999);
endmodule
module top_module (
    input clk,
    input reset,
    output [3:1] ena,
    output [15:0] q);

    decade U1(clk, reset, 1'b1, q[3:0]);
    decade U2(clk, reset, ena[1], q[7:4]);
    decade U3(clk, reset, ena[2], q[11:8]);
    decade U4(clk, reset, ena[3], q[15:12]);
    assign ena[1] = (q[3:0] == 4'h9);
    assign ena[2] = (q[7:0] == 8'h99);
    assign ena[3] = (q[11:0] == 12'h999);
endmodule