data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog/seg_write_back.v
data/verilator_xmls/08231a16-efcd-418b-85cf-8571c266cbb3.xml
module seg_write_back
    #(  parameter   LEN             = 32,
        parameter   NB_ADDR         = 5,
        parameter   NB_CTRL_WB      = 2
    )
    (

        input wire [LEN-1 : 0]      i_read_data,
        input wire [LEN-1 : 0]      i_ALU_result,
        input wire [NB_ADDR-1:0]    i_write_register,

        input wire [NB_CTRL_WB-1:0] i_ctrl_wb_bus,
        

        output wire                 o_RegWrite,
        output wire [LEN -1 : 0]    o_write_data,
        output wire [NB_ADDR-1:0]   o_write_register
    );
    

    wire   MemtoReg;


    assign o_RegWrite       = i_ctrl_wb_bus[1];
    assign MemtoReg         = i_ctrl_wb_bus[0];

    assign o_write_register = i_write_register;

    assign o_write_data     = (MemtoReg) ? i_read_data : i_ALU_result;

endmodule
module seg_write_back
    #(  parameter   LEN             = 32,
        parameter   NB_ADDR         = 5,
        parameter   NB_CTRL_WB      = 2
    )
    (

        input wire [LEN-1 : 0]      i_read_data,
        input wire [LEN-1 : 0]      i_ALU_result,
        input wire [NB_ADDR-1:0]    i_write_register,

        input wire [NB_CTRL_WB-1:0] i_ctrl_wb_bus,
        

        output wire                 o_RegWrite,
        output wire [LEN -1 : 0]    o_write_data,
        output wire [NB_ADDR-1:0]   o_write_register
    );

    

    wire   MemtoReg;


    assign o_RegWrite       = i_ctrl_wb_bus[1];
    assign MemtoReg         = i_ctrl_wb_bus[0];

    assign o_write_register = i_write_register;

    assign o_write_data     = (MemtoReg) ? i_read_data : i_ALU_result;

endmodule