data/full_repos/permissive/177136805/main.v
1: b"%Error: data/full_repos/permissive/177136805/main.v:15: Cannot find file containing module: 'displayA'\ndisplayA disA(.x(x[5:0]),.y(a[5:0]));    \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/177136805,data/full_repos/permissive/177136805/displayA\n             data/full_repos/permissive/177136805,data/full_repos/permissive/177136805/displayA.v\n             data/full_repos/permissive/177136805,data/full_repos/permissive/177136805/displayA.sv\n             displayA\n             displayA.v\n             displayA.sv\n             obj_dir/displayA\n             obj_dir/displayA.v\n             obj_dir/displayA.sv\n%Error: data/full_repos/permissive/177136805/main.v:16: Cannot find file containing module: 'displayB'\ndisplayB disB(.x(y[5:0]),.y(b[5:0]));    \n^~~~~~~~\n%Error: data/full_repos/permissive/177136805/main.v:17: Cannot find file containing module: 'displayNA'\ndisplayNA disNA(.x(x[5:0]),.y(c[5:0]));  \n^~~~~~~~~\n%Error: data/full_repos/permissive/177136805/main.v:18: Cannot find file containing module: 'displayNB'\ndisplayNB disNB(.x(y[5:0]),.y(d[5:0]));  \n^~~~~~~~~\n%Error: data/full_repos/permissive/177136805/main.v:19: Cannot find file containing module: 'displayXOR'\ndisplayXOR disXOR(.x(x[5:0]),.y(y[5:0]),.out(e[5:0]));   \n^~~~~~~~~~\n%Error: data/full_repos/permissive/177136805/main.v:20: Cannot find file containing module: 'sixbitgtoreq'\nsixbitgtoreq gtoreq(.x(x[5:0]),.y(y[5:0]),.agteqb(f));   \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/177136805/main.v:21: Cannot find file containing module: 'bit_ripple_adder'\nbit_ripple_adder adder(.x(x[5:0]),.y(y[5:0]),.sel(0),.overflow(i),.c_out(j),.sum(g[5:0]));   \n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/177136805/main.v:22: Cannot find file containing module: 'bit_ripple_adder'\nbit_ripple_adder subtractor(.x(x[5:0]),.y(y[5:0]),.sel(1),.overflow(k),.c_out(l),.sum(h[5:0])); \n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module main
(
    input [5:0]x,
    input [5:0]y,
    input [2:0]fxn,
    output reg[5:0]out,
    output reg carry,
    output reg over,
    output reg agteqb
);
wire[5:0] a,b,c,d,e,g,h;
wire f,i,j,k,l,m,n;


displayA disA(.x(x[5:0]),.y(a[5:0]));
displayB disB(.x(y[5:0]),.y(b[5:0]));
displayNA disNA(.x(x[5:0]),.y(c[5:0]));
displayNB disNB(.x(y[5:0]),.y(d[5:0]));
displayXOR disXOR(.x(x[5:0]),.y(y[5:0]),.out(e[5:0]));
sixbitgtoreq gtoreq(.x(x[5:0]),.y(y[5:0]),.agteqb(f));
bit_ripple_adder adder(.x(x[5:0]),.y(y[5:0]),.sel(0),.overflow(i),.c_out(j),.sum(g[5:0]));
bit_ripple_adder subtractor(.x(x[5:0]),.y(y[5:0]),.sel(1),.overflow(k),.c_out(l),.sum(h[5:0])); 






always@*    
begin
    case(fxn)
        3'b000:
            begin   
                agteqb=0;
                carry=0;
                over=0;
                out=a[5:0];
             end
        3'b001:
            begin
                agteqb=0;
                carry=0;
                over=0;
                out=b[5:0];
             end
        3'b010:
            begin
                agteqb=0;
                carry=0;
                over=0;
                out=c[5:0];
             end
        3'b011:
            begin
                agteqb=0;
                carry=0;
                over=0;
                out=d[5:0];
             end
        3'b100:
            begin
                carry=0;
                over=0;
                out=0;
                agteqb=f;
             end
        3'b101:
            begin
                agteqb=0;
                carry=0;
                over=0;
                out=e[5:0];
             end
        3'b110:
            begin
                agteqb=0;
                over=i;
                carry=j;
                out=g[5:0];
            end
        3'b111:
            begin
                agteqb=0;   
                over=k;
                carry=l;
                out=h[5:0];
            end
    endcase
end    
endmodule
module main
(
    input [5:0]x,
    input [5:0]y,
    input [2:0]fxn,
    output reg[5:0]out,
    output reg carry,
    output reg over,
    output reg agteqb
);

wire[5:0] a,b,c,d,e,g,h;
wire f,i,j,k,l,m,n;


displayA disA(.x(x[5:0]),.y(a[5:0]));
displayB disB(.x(y[5:0]),.y(b[5:0]));
displayNA disNA(.x(x[5:0]),.y(c[5:0]));
displayNB disNB(.x(y[5:0]),.y(d[5:0]));
displayXOR disXOR(.x(x[5:0]),.y(y[5:0]),.out(e[5:0]));
sixbitgtoreq gtoreq(.x(x[5:0]),.y(y[5:0]),.agteqb(f));
bit_ripple_adder adder(.x(x[5:0]),.y(y[5:0]),.sel(0),.overflow(i),.c_out(j),.sum(g[5:0]));
bit_ripple_adder subtractor(.x(x[5:0]),.y(y[5:0]),.sel(1),.overflow(k),.c_out(l),.sum(h[5:0])); 






always@*    
begin
    case(fxn)
        3'b000:
            begin   
                agteqb=0;
                carry=0;
                over=0;
                out=a[5:0];
             end
        3'b001:
            begin
                agteqb=0;
                carry=0;
                over=0;
                out=b[5:0];
             end
        3'b010:
            begin
                agteqb=0;
                carry=0;
                over=0;
                out=c[5:0];
             end
        3'b011:
            begin
                agteqb=0;
                carry=0;
                over=0;
                out=d[5:0];
             end
        3'b100:
            begin
                carry=0;
                over=0;
                out=0;
                agteqb=f;
             end
        3'b101:
            begin
                agteqb=0;
                carry=0;
                over=0;
                out=e[5:0];
             end
        3'b110:
            begin
                agteqb=0;
                over=i;
                carry=j;
                out=g[5:0];
            end
        3'b111:
            begin
                agteqb=0;   
                over=k;
                carry=l;
                out=h[5:0];
            end
    endcase
end    
endmodule