data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k.v
 line:57: before: "="
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k.v:79: Cannot find file containing module: \'mfsr10\'\nmfsr10 MFSR0 (\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync,data/full_repos/permissive/20430511/mfsr10\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync,data/full_repos/permissive/20430511/mfsr10.v\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync,data/full_repos/permissive/20430511/mfsr10.sv\n             mfsr10\n             mfsr10.v\n             mfsr10.sv\n             obj_dir/mfsr10\n             obj_dir/mfsr10.v\n             obj_dir/mfsr10.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k.v:84: Cannot find file containing module: \'mfsr10\'\nmfsr10 MFSR1 (\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k.v:101: Bit extraction of array[2047:0] requires 11 bit index, not 10 bits.\n                                                                                         : ... In instance sfifo2k\n data_o <= #2 fmem[rd_ptr [PSB:0]];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k.v:123: Bit extraction of array[2047:0] requires 11 bit index, not 10 bits.\n                                                                                         : ... In instance sfifo2k\n  fmem [wr_ptr [PSB:0]] <= #2 data_i;\n       ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module sfifo2k #(
`ifdef __use_mfsrs
	parameter	INIT	= 1,
`else
	parameter	INIT	= 0,
`endif
	parameter	WIDTH	= 32,
	parameter	SIZE	= 2048,
	parameter	PWIDTH	= 10,
	parameter	MSB	= WIDTH - 1,
	parameter	PSB	= PWIDTH - 1
) (
	input		clock_i,
	input		reset_ni,

	input		read_i,
	input		write_i,
	input	[MSB:0]	data_i,
`ifdef __sim_only
	output	[MSB:0]	data_o,
`else
	output	reg	[MSB:0]	data_o,
`endif
	output	reg	full_o	= 0,
	output	reg	empty_o	= 1,
	output		rack_ao,
	output		wack_ao,
	output		full_ao,
	output		empty_ao
);

reg	[MSB:0]	fmem [SIZE-1:0];

reg	[PWIDTH:0]	rd_ptr	= INIT;
reg	[PWIDTH:0]	wr_ptr	= INIT;

wire	[PWIDTH:0]	next_rd_ptr, next_wr_ptr;

wire	empty_w	= (wr_ptr == rd_ptr) || (next_rd_ptr == wr_ptr && read_i);
wire	full_w	= (wr_ptr [PSB:0] == rd_ptr [PSB:0]) && (wr_ptr [PWIDTH] != rd_ptr [PWIDTH]);

assign	#2 full_ao	= full_w;
assign	#2 empty_ao	= empty_w;

`ifdef __use_mfsrs
mfsr10 MFSR0 (
	.count_i	(rd_ptr),
	.count_o	(next_rd_ptr)
);

mfsr10 MFSR1 (
	.count_i	(wr_ptr),
	.count_o	(next_wr_ptr)
);
`else
assign	#2 next_rd_ptr	= rd_ptr + 1;
assign	#2 next_wr_ptr	= wr_ptr + 1;
`endif

assign	#2 rack_ao	= (rd_ptr != wr_ptr) && read_i;
assign	#2 wack_ao	= !full_w && write_i;


`ifdef __sim_only
assign	#2 data_o	= fmem[rd_ptr [PSB:0]];
`else
always @(posedge clock_i)
	data_o	<= #2 fmem[rd_ptr [PSB:0]];
`endif




always @(posedge clock_i)
	if (!reset_ni)
		rd_ptr	<= #2 INIT;
	else if (rack_ao)
		rd_ptr	<= #2 next_rd_ptr;

always @(posedge clock_i)
	if (!reset_ni)
		wr_ptr	<= #2 INIT;
	else if (wack_ao)
		wr_ptr	<= #2 next_wr_ptr;



always @(posedge clock_i)
	if (write_i && !full_w)
		fmem [wr_ptr [PSB:0]]	<= #2 data_i;



always @(posedge clock_i)
	if (!reset_ni)
		full_o	<= #2 0;
	else
		full_o	<= #2 full_w;

always @(posedge clock_i)
	if (!reset_ni)
		empty_o	<= #2 1;
	else
		empty_o	<= #2 empty_w;


endmodule
module sfifo2k #(
`ifdef __use_mfsrs
	parameter	INIT	= 1,
`else
	parameter	INIT	= 0,
`endif
	parameter	WIDTH	= 32,
	parameter	SIZE	= 2048,
	parameter	PWIDTH	= 10,
	parameter	MSB	= WIDTH - 1,
	parameter	PSB	= PWIDTH - 1
) (
	input		clock_i,
	input		reset_ni,

	input		read_i,
	input		write_i,
	input	[MSB:0]	data_i,
`ifdef __sim_only
	output	[MSB:0]	data_o,
`else
	output	reg	[MSB:0]	data_o,
`endif
	output	reg	full_o	= 0,
	output	reg	empty_o	= 1,
	output		rack_ao,
	output		wack_ao,
	output		full_ao,
	output		empty_ao
);


reg	[MSB:0]	fmem [SIZE-1:0];

reg	[PWIDTH:0]	rd_ptr	= INIT;
reg	[PWIDTH:0]	wr_ptr	= INIT;

wire	[PWIDTH:0]	next_rd_ptr, next_wr_ptr;

wire	empty_w	= (wr_ptr == rd_ptr) || (next_rd_ptr == wr_ptr && read_i);
wire	full_w	= (wr_ptr [PSB:0] == rd_ptr [PSB:0]) && (wr_ptr [PWIDTH] != rd_ptr [PWIDTH]);

assign	#2 full_ao	= full_w;
assign	#2 empty_ao	= empty_w;

`ifdef __use_mfsrs
mfsr10 MFSR0 (
	.count_i	(rd_ptr),
	.count_o	(next_rd_ptr)
);

mfsr10 MFSR1 (
	.count_i	(wr_ptr),
	.count_o	(next_wr_ptr)
);
`else
assign	#2 next_rd_ptr	= rd_ptr + 1;
assign	#2 next_wr_ptr	= wr_ptr + 1;
`endif

assign	#2 rack_ao	= (rd_ptr != wr_ptr) && read_i;
assign	#2 wack_ao	= !full_w && write_i;


`ifdef __sim_only
assign	#2 data_o	= fmem[rd_ptr [PSB:0]];
`else
always @(posedge clock_i)
	data_o	<= #2 fmem[rd_ptr [PSB:0]];
`endif




always @(posedge clock_i)
	if (!reset_ni)
		rd_ptr	<= #2 INIT;
	else if (rack_ao)
		rd_ptr	<= #2 next_rd_ptr;

always @(posedge clock_i)
	if (!reset_ni)
		wr_ptr	<= #2 INIT;
	else if (wack_ao)
		wr_ptr	<= #2 next_wr_ptr;



always @(posedge clock_i)
	if (write_i && !full_w)
		fmem [wr_ptr [PSB:0]]	<= #2 data_i;



always @(posedge clock_i)
	if (!reset_ni)
		full_o	<= #2 0;
	else
		full_o	<= #2 full_w;

always @(posedge clock_i)
	if (!reset_ni)
		empty_o	<= #2 1;
	else
		empty_o	<= #2 empty_w;


endmodule