data/full_repos/permissive/212981921/rtl/ls10.v
data/verilator_xmls/6e75e4c4-176e-42f3-b6f6-8815e48ba49e.xml
module ls10
(
    input wire  a, b, c,
    output wire y
);

nand(y, a, b, c);

endmodule
module ls10
(
    input wire  a, b, c,
    output wire y
);


nand(y, a, b, c);

endmodule