data/full_repos/permissive/166614783/counter.v
data/verilator_xmls/b6c7854e-300b-4c43-97f3-858f134d605f.xml
module counter(pc_addr, clock, rst, en);
input clock, rst, en;
output reg [7:0] pc_addr;

always @(posedge clock or negedge rst) begin
	if(!rst) begin
		pc_addr <= 8'd0;
	end
	else begin
		if(en) pc_addr <= pc_addr+1;
		else pc_addr <= pc_addr;
	end
end

endmodule
module counter(pc_addr, clock, rst, en);

input clock, rst, en;
output reg [7:0] pc_addr;

always @(posedge clock or negedge rst) begin
	if(!rst) begin
		pc_addr <= 8'd0;
	end
	else begin
		if(en) pc_addr <= pc_addr+1;
		else pc_addr <= pc_addr;
	end
end

endmodule