data/full_repos/permissive/190755935/src/comms/rtl/uart_out.v
 line:467: before: "("
1: b'%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_out.v:52: Cannot find include file: ../../pipe/rtl/pipe_defs.v\n`include "../../pipe/rtl/pipe_defs.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v.v\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v.sv\n             ../../pipe/rtl/pipe_defs.v\n             ../../pipe/rtl/pipe_defs.v.v\n             ../../pipe/rtl/pipe_defs.v.sv\n             obj_dir/../../pipe/rtl/pipe_defs.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.sv\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_out.v:54: Define or directive not defined: \'`PS_DATA\'\nmodule uart_out  #( parameter PipeSpec = `PS_DATA( 8 ), parameter ClockFrequency = 12000000, parameter BaudRate = 9600 ) (\n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_out.v:58: Define or directive not defined: \'`P_w\'\n        inout [`P_w(PipeSpec)-1:0] pipe_in,\n               ^~~~\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_out.v:63: Define or directive not defined: \'`P_Data_w\'\n    wire [`P_Data_w(PipeSpec)-1:0] in_data;\n          ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module uart_out  #( parameter PipeSpec = `PS_DATA( 8 ), parameter ClockFrequency = 12000000, parameter BaudRate = 9600 ) (
        input clock,
        input reset,

        inout [`P_w(PipeSpec)-1:0] pipe_in,

        output pin_tx
    );

    wire [`P_Data_w(PipeSpec)-1:0] in_data;
    wire                     in_valid;
    wire                     in_ready;

    p_unpack_data        #( .PipeSpec( PipeSpec ) ) in_unpack_d ( pipe_in, in_data);
    p_unpack_valid_ready #( .PipeSpec( PipeSpec ) ) in_unpack_vr( pipe_in, in_valid, in_ready );


    uart_out_np #( .ClockFrequency( ClockFrequency ), .BaudRate( BaudRate ) )  u_o_np (
            clock, reset,

            in_data, in_valid, in_ready,

            pin_tx
        );

endmodule
module uart_out  #( parameter PipeSpec = `PS_DATA( 8 ), parameter ClockFrequency = 12000000, parameter BaudRate = 9600 ) (
        input clock,
        input reset,

        inout [`P_w(PipeSpec)-1:0] pipe_in,

        output pin_tx
    );


    wire [`P_Data_w(PipeSpec)-1:0] in_data;
    wire                     in_valid;
    wire                     in_ready;

    p_unpack_data        #( .PipeSpec( PipeSpec ) ) in_unpack_d ( pipe_in, in_data);
    p_unpack_valid_ready #( .PipeSpec( PipeSpec ) ) in_unpack_vr( pipe_in, in_valid, in_ready );


    uart_out_np #( .ClockFrequency( ClockFrequency ), .BaudRate( BaudRate ) )  u_o_np (
            clock, reset,

            in_data, in_valid, in_ready,

            pin_tx
        );

endmodule