data/full_repos/permissive/192346182/ALU.v
data/verilator_xmls/2e2b3569-0ce0-4eae-b39b-ec6d71955b90.xml
module ALU
(
	output reg True,
	output reg signed [31:0] Result,
	input Fast_Clock,
	input signed [31:0] Input_1,
	input signed [31:0] Input_2,
	input [4:0] ALU_Op
);

always @ (negedge Fast_Clock)
begin
	case (ALU_Op)

		0:
		begin
			Result = Input_1 + Input_2;
			True = 0;
		end

		1:
		begin
			Result = Input_1 - Input_2;
			True = 0;
		end

		2:
		begin
			Result = Input_1 * Input_2;
			True = 0;
		end

		3:
		begin
			Result = Input_1 / Input_2;
			True = 0;
		end

		4:
		begin
			Result = Input_1 % Input_2;
			True = 0;
		end

		5:
		begin
			Result = Input_1 & Input_2;
			True = 0;
		end

		6:
		begin
			Result = Input_1 | Input_2;
			True = 0;
		end

		7:
		begin
			Result = Input_1 ^ Input_2;
			True = 0;
		end

		8:
		begin
			Result = ~Input_1;
			True = 0;
		end

		9:
		begin
			Result = Input_1 << $unsigned(Input_2);
			True = 0;
		end

		10:
		begin
			Result = Input_1 >> $unsigned(Input_2);
			True = 0;
		end

		11:
		begin
			if (Input_1 == Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		12:
		begin
			if (Input_1 != Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		13:
		begin
			if (Input_1 >= Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		14:
		begin
			if (Input_1 > Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		15:
		begin
			if (Input_1 <= Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		16:
		begin
			if (Input_1 < Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		17:
		begin
			Result = 0;
			True = 0;
		end

		18:
		begin
			Result = Input_2;
			True = 0;
		end

		default:
		begin
			Result = 0;
			True = 0;
		end

	endcase

end

endmodule
module ALU
(
	output reg True,
	output reg signed [31:0] Result,
	input Fast_Clock,
	input signed [31:0] Input_1,
	input signed [31:0] Input_2,
	input [4:0] ALU_Op
);


always @ (negedge Fast_Clock)
begin
	case (ALU_Op)

		0:
		begin
			Result = Input_1 + Input_2;
			True = 0;
		end

		1:
		begin
			Result = Input_1 - Input_2;
			True = 0;
		end

		2:
		begin
			Result = Input_1 * Input_2;
			True = 0;
		end

		3:
		begin
			Result = Input_1 / Input_2;
			True = 0;
		end

		4:
		begin
			Result = Input_1 % Input_2;
			True = 0;
		end

		5:
		begin
			Result = Input_1 & Input_2;
			True = 0;
		end

		6:
		begin
			Result = Input_1 | Input_2;
			True = 0;
		end

		7:
		begin
			Result = Input_1 ^ Input_2;
			True = 0;
		end

		8:
		begin
			Result = ~Input_1;
			True = 0;
		end

		9:
		begin
			Result = Input_1 << $unsigned(Input_2);
			True = 0;
		end

		10:
		begin
			Result = Input_1 >> $unsigned(Input_2);
			True = 0;
		end

		11:
		begin
			if (Input_1 == Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		12:
		begin
			if (Input_1 != Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		13:
		begin
			if (Input_1 >= Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		14:
		begin
			if (Input_1 > Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		15:
		begin
			if (Input_1 <= Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		16:
		begin
			if (Input_1 < Input_2)
			begin
				Result = 1;
				True = 1;
			end
			else
			begin
				Result = 0;
				True = 0;
			end
		end

		17:
		begin
			Result = 0;
			True = 0;
		end

		18:
		begin
			Result = Input_2;
			True = 0;
		end

		default:
		begin
			Result = 0;
			True = 0;
		end

	endcase

end

endmodule