data/full_repos/permissive/104504209/PGM8755/src/buffer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/104504209/PGM8755/src/buffer.v:22: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3f0\' generates 10 bits.\n                                                                            : ... In instance buffer\n  if(rst) address_i <= 10\'hFF0;\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module buffer(input rst, clk, dir, input[7:0] data_in, input[10:0] address, output reg[7:0] data_out);
	
	reg[7:0] blockram [2047:0];
	reg[10:0] address_i;
	

	always@(posedge clk) begin
		if(rst) address_i <= 10'hFF0;
		if(dir) data_out <= blockram[address];
		else begin
			blockram[address_i] <= data_in;
			address_i <= address_i - 1'b1;
		end
	end
	
endmodule
module buffer(input rst, clk, dir, input[7:0] data_in, input[10:0] address, output reg[7:0] data_out);

	
	reg[7:0] blockram [2047:0];
	reg[10:0] address_i;
	

	always@(posedge clk) begin
		if(rst) address_i <= 10'hFF0;
		if(dir) data_out <= blockram[address];
		else begin
			blockram[address_i] <= data_in;
			address_i <= address_i - 1'b1;
		end
	end
	
endmodule