data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v
 line:55: before: "#"
1: b'%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:52: syntax error, unexpected \'@\'\n @(negedge reset_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:58: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:61: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:65: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:68: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:71: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:75: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:78: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:81: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:85: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:88: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:91: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:95: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:98: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:101: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Error: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:105: syntax error, unexpected \'@\'\n #100 @(posedge clk_i)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge clk_i)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk_i = ~clk_i;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19591557/modules/rr_arbiter/spio_rr_arbiter_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Error: Exiting due to 16 error(s), 17 warning(s)\n'
module spio_rr_arbiter_tb;

localparam PKT_BITS = 72;

genvar i;

reg clk_i;
reg reset_i;


reg [PKT_BITS-1:0] in_data_i [1:0];
reg                in_vld_i [1:0];
wire               in_rdy_i [1:0];


wire [PKT_BITS-1:0] out_data_i;
wire                out_vld_i;
reg                 out_rdy_i;






spio_rr_arbiter #( .PKT_BITS(PKT_BITS) )
spio_rr_arbiter_i( .CLK_IN   (clk_i)
                 , .RESET_IN (reset_i)
                 , .DATA0_IN (in_data_i[0])
                 , .VLD0_IN  (in_vld_i[0])
                 , .RDY0_OUT (in_rdy_i[0])
                 , .DATA1_IN (in_data_i[1])
                 , .VLD1_IN  (in_vld_i[1])
                 , .RDY1_OUT (in_rdy_i[1])
                 , .DATA_OUT (out_data_i)
                 , .VLD_OUT  (out_vld_i)
                 , .RDY_IN   (out_rdy_i)
                 );






initial
	begin
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;
	@(negedge reset_i)
	

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b0;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;
	

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b1;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b0;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b1;
	

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b1;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b0;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b1;
	

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b0;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;
	

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b0;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;
	

	#100 @(posedge clk_i)
	$finish;
	end

generate for (i = 0; i < 2; i = i + 1)
	begin: input_stimulus
		reg [PKT_BITS-4-1:0] packets_sent_i;
		
		always @ (posedge clk_i, posedge reset_i)
			if (reset_i)
				begin
					in_data_i[i]   <= {0, i==0 ? 4'hA : 4'hB};
					packets_sent_i <= 1;
				end
			else
				begin
					if (in_vld_i[i] && in_rdy_i[i])
						begin
							in_data_i[i]   <= {packets_sent_i, i==0 ? 4'hA : 4'hB};
							packets_sent_i <= packets_sent_i + 1;
						end
				end
	end
endgenerate

reg [PKT_BITS-4-1:0] next_arrival_i [1:0];

initial
	begin
		next_arrival_i[0] = 0;
		next_arrival_i[0] = 0;
	end


always @ (posedge clk_i)
	if (out_vld_i && out_rdy_i)
		begin
			if (out_data_i[3:0] == 4'hA)
				begin
					$display("Tick=%8d; %018x", $time/10, out_data_i);
					
					if (out_data_i[PKT_BITS-1:4] != next_arrival_i[0])
						$display("Tick=%8d; %018x Missing!", $time/10, next_arrival_i[0]);
					next_arrival_i[0] = next_arrival_i[0]+1;
				end
			else
				begin
					$display("Tick=%8d;                                           %018x", $time/10, out_data_i);
					
					if (out_data_i[PKT_BITS-1:4] != next_arrival_i[1])
						$display("Tick=%8d;                                           %018x Missing", $time/10, next_arrival_i[1]);
					next_arrival_i[1] = next_arrival_i[1]+1;
				end
		end
	else
		$display("Tick=%8d; Output Idle.", $time/10);







initial
	begin
	clk_i = 1'b0;
	forever
		#5 clk_i = ~clk_i;
	end



initial
	begin
		reset_i <= 1'b1;
		#100
		reset_i <= 1'b0;
	end


endmodule
module spio_rr_arbiter_tb;


localparam PKT_BITS = 72;

genvar i;

reg clk_i;
reg reset_i;


reg [PKT_BITS-1:0] in_data_i [1:0];
reg                in_vld_i [1:0];
wire               in_rdy_i [1:0];


wire [PKT_BITS-1:0] out_data_i;
wire                out_vld_i;
reg                 out_rdy_i;






spio_rr_arbiter #( .PKT_BITS(PKT_BITS) )
spio_rr_arbiter_i( .CLK_IN   (clk_i)
                 , .RESET_IN (reset_i)
                 , .DATA0_IN (in_data_i[0])
                 , .VLD0_IN  (in_vld_i[0])
                 , .RDY0_OUT (in_rdy_i[0])
                 , .DATA1_IN (in_data_i[1])
                 , .VLD1_IN  (in_vld_i[1])
                 , .RDY1_OUT (in_rdy_i[1])
                 , .DATA_OUT (out_data_i)
                 , .VLD_OUT  (out_vld_i)
                 , .RDY_IN   (out_rdy_i)
                 );






initial
	begin
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;
	@(negedge reset_i)
	

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b0;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;
	

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b1;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b0;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b1;
	

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b1;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b0;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b0;   out_rdy_i <= 1'b1;
	

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b0;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b1;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;
	

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b0;

	#100 @(posedge clk_i)
	in_vld_i[0] <= 1'b0;   in_vld_i[1] <= 1'b1;   out_rdy_i <= 1'b1;
	

	#100 @(posedge clk_i)
	$finish;
	end

generate for (i = 0; i < 2; i = i + 1)
	begin: input_stimulus
		reg [PKT_BITS-4-1:0] packets_sent_i;
		
		always @ (posedge clk_i, posedge reset_i)
			if (reset_i)
				begin
					in_data_i[i]   <= {0, i==0 ? 4'hA : 4'hB};
					packets_sent_i <= 1;
				end
			else
				begin
					if (in_vld_i[i] && in_rdy_i[i])
						begin
							in_data_i[i]   <= {packets_sent_i, i==0 ? 4'hA : 4'hB};
							packets_sent_i <= packets_sent_i + 1;
						end
				end
	end
endgenerate

reg [PKT_BITS-4-1:0] next_arrival_i [1:0];

initial
	begin
		next_arrival_i[0] = 0;
		next_arrival_i[0] = 0;
	end


always @ (posedge clk_i)
	if (out_vld_i && out_rdy_i)
		begin
			if (out_data_i[3:0] == 4'hA)
				begin
					$display("Tick=%8d; %018x", $time/10, out_data_i);
					
					if (out_data_i[PKT_BITS-1:4] != next_arrival_i[0])
						$display("Tick=%8d; %018x Missing!", $time/10, next_arrival_i[0]);
					next_arrival_i[0] = next_arrival_i[0]+1;
				end
			else
				begin
					$display("Tick=%8d;                                           %018x", $time/10, out_data_i);
					
					if (out_data_i[PKT_BITS-1:4] != next_arrival_i[1])
						$display("Tick=%8d;                                           %018x Missing", $time/10, next_arrival_i[1]);
					next_arrival_i[1] = next_arrival_i[1]+1;
				end
		end
	else
		$display("Tick=%8d; Output Idle.", $time/10);







initial
	begin
	clk_i = 1'b0;
	forever
		#5 clk_i = ~clk_i;
	end



initial
	begin
		reset_i <= 1'b1;
		#100
		reset_i <= 1'b0;
	end


endmodule