data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/thirty_two_bit_adder.v
1: b"%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/thirty_two_bit_adder.v:20: Cannot find file containing module: 'sixteen_bit_adder'\nsixteen_bit_adder add1(.x(x[15:0]), .y(y[15:0]), .c_in(c_in), .sum(sum[15:0]), .c_out(carry));\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/sixteen_bit_adder\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/sixteen_bit_adder.v\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/sixteen_bit_adder.sv\n             sixteen_bit_adder\n             sixteen_bit_adder.v\n             sixteen_bit_adder.sv\n             obj_dir/sixteen_bit_adder\n             obj_dir/sixteen_bit_adder.v\n             obj_dir/sixteen_bit_adder.sv\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/thirty_two_bit_adder.v:21: Cannot find file containing module: 'sixteen_bit_adder'\nsixteen_bit_adder add2(.x(x[31:16]), .y(y[31:16]), .c_in(carry), .sum(sum[31:16]), .c_out(c_out));\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module thirty_two_bit_adder(input wire [31:0] x, input wire [31:0] y,output wire [31:0] sum);







wire carry;
wire c_out;
reg c_in;

parameter zero=0;
initial begin
    c_in=zero;
end

sixteen_bit_adder add1(.x(x[15:0]), .y(y[15:0]), .c_in(c_in), .sum(sum[15:0]), .c_out(carry));
sixteen_bit_adder add2(.x(x[31:16]), .y(y[31:16]), .c_in(carry), .sum(sum[31:16]), .c_out(c_out));

endmodule
module thirty_two_bit_adder(input wire [31:0] x, input wire [31:0] y,output wire [31:0] sum);








wire carry;
wire c_out;
reg c_in;

parameter zero=0;
initial begin
    c_in=zero;
end

sixteen_bit_adder add1(.x(x[15:0]), .y(y[15:0]), .c_in(c_in), .sum(sum[15:0]), .c_out(carry));
sixteen_bit_adder add2(.x(x[31:16]), .y(y[31:16]), .c_in(carry), .sum(sum[31:16]), .c_out(c_out));

endmodule