data/full_repos/permissive/144334019/LSFR3.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-IMPLICIT: data/full_repos/permissive/144334019/LSFR3.v:34: Signal definition not found, creating implicitly: \'feedback\'\n assign feedback =   \n        ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module LFSR3 #(parameter polinom = 9'b1_0111_0001)(clk, rst, ctextIn, zOut,seed);

	input [7:0]		seed;
	input				clk;
	input				rst;
	input				ctextIn;
	output [7:0]		zOut;

	(*KEEP="TRUE"*)reg 	[7:0] 	ffs;
	(*KEEP="TRUE"*)reg	[7:0]		ctext_reg;
						reg	[3:0]		counter;
	assign zOut = ffs;
	
	assign feedback =
								(polinom[1] && ffs[0]) ^ 
								(polinom[2] && ffs[1]) ^ 
								(polinom[3] && ffs[2]) ^ 
								(polinom[4] && ffs[3]) ^ 
								(polinom[5] && ffs[4]) ^ 
								(polinom[6] && ffs[5]) ^ 
								(polinom[7] && ffs[6]) ^ 
								(polinom[8] && ffs[7]) | 

								!(	ffs[0] | ffs[1] | 
									ffs[2] | ffs[3] | 
									ffs[4] | ffs[5] | 
									ffs[6] | ffs[7]
								);						
								

	always@(posedge clk or posedge rst)
	begin
		if(rst)
		begin
			ffs 			<= seed;
			ctext_reg 	<= 8'h00;
			counter		<= 4'h0;
		end
		else
		begin
			counter <= counter + 1;
			if(counter == 4'h8)

			begin
				ffs <= ctext_reg;
			end
			else
			begin
				ffs <= {ffs[6:0],feedback};				
			end
			ctext_reg <= {ctext_reg[6:0],ctextIn};
		end
	end
endmodule
module LFSR3 #(parameter polinom = 9'b1_0111_0001)(clk, rst, ctextIn, zOut,seed);


	input [7:0]		seed;
	input				clk;
	input				rst;
	input				ctextIn;
	output [7:0]		zOut;

	(*KEEP="TRUE"*)reg 	[7:0] 	ffs;
	(*KEEP="TRUE"*)reg	[7:0]		ctext_reg;
						reg	[3:0]		counter;
	assign zOut = ffs;
	
	assign feedback =
								(polinom[1] && ffs[0]) ^ 
								(polinom[2] && ffs[1]) ^ 
								(polinom[3] && ffs[2]) ^ 
								(polinom[4] && ffs[3]) ^ 
								(polinom[5] && ffs[4]) ^ 
								(polinom[6] && ffs[5]) ^ 
								(polinom[7] && ffs[6]) ^ 
								(polinom[8] && ffs[7]) | 

								!(	ffs[0] | ffs[1] | 
									ffs[2] | ffs[3] | 
									ffs[4] | ffs[5] | 
									ffs[6] | ffs[7]
								);						
								

	always@(posedge clk or posedge rst)
	begin
		if(rst)
		begin
			ffs 			<= seed;
			ctext_reg 	<= 8'h00;
			counter		<= 4'h0;
		end
		else
		begin
			counter <= counter + 1;
			if(counter == 4'h8)

			begin
				ffs <= ctext_reg;
			end
			else
			begin
				ffs <= {ffs[6:0],feedback};				
			end
			ctext_reg <= {ctext_reg[6:0],ctextIn};
		end
	end
endmodule