data/full_repos/permissive/201488448/2_circuits/1_combinational/09_eq2.v
data/verilator_xmls/e552e312-1666-42cf-86b5-a1251ab7baa0.xml
module top_module ( input [1:0] A, input [1:0] B, output z ); 

    assign	z = (A==B);
    
endmodule
module top_module ( input [1:0] A, input [1:0] B, output z );
 

    assign	z = (A==B);
    
endmodule