data/full_repos/permissive/148324174/FIFO/sync_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/148324174/FIFO/sync_fifo.v:59: Bit extraction of array[8:0] requires 4 bit index, not 2 bits.\n                                                                        : ... In instance sync_fifo\n      {src_out,dst_out,data_out} <= fifomem[tail];\n                                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/148324174/FIFO/sync_fifo.v:67: Bit extraction of array[8:0] requires 4 bit index, not 2 bits.\n                                                                        : ... In instance sync_fifo\n      fifomem[head] <= {src_in,dst_in,data_in};\n             ^\n%Error: Exiting due to 2 warning(s)\n'
module sync_fifo (clk, rstp, src_in, dst_in, data_in, writep, readp, 
	src_out, dst_out, data_out, emptyp, fullp);
input		clk;
input		rstp;
input [7:0]	src_in;
input [7:0]	dst_in;
input [31:0]	data_in;
input		readp;
input		writep;
output [7:0]	src_out;
output [7:0]	dst_out;
output [31:0]	data_out;
output		emptyp;
output		fullp;



parameter	DEPTH = 2,	
		FULL = (1<<3),
		EMPTY = (1<<3);

reg 		emptyp;
reg		fullp;


reg [7:0]	src_out;
reg [7:0]	dst_out;
reg [31:0]	data_out;



reg [(DEPTH-1):0]	tail;
reg [(DEPTH-1):0]	head;




reg [DEPTH:0]	count;




reg [47:0] fifomem[0:FULL];



integer i;
always @(posedge clk or posedge rstp) begin
   if (rstp == 1) begin
      src_out <= 8'b0;
      dst_out <= 8'b0;
      data_out <= 32'b0;
   end
   else begin
      {src_out,dst_out,data_out} <= fifomem[tail];
   end
end 
     

always @(posedge clk)
   if (rstp == 1'b0) begin
     if (writep == 1'b1 && fullp == 1'b0)
      fifomem[head] <= {src_in,dst_in,data_in};
   end



always @(posedge clk) begin
   if (rstp == 1'b1) begin
     head <= 0;
   end
   else begin
      if (writep == 1'b1 && fullp == 1'b0) begin

         head <= head + 1;
      end
   end
end



always @(posedge clk) begin
   if (rstp == 1'b1) begin
      tail <= 0;
   end
   else begin
      if (readp == 1'b1 && emptyp == 1'b0) begin

         tail <= tail + 1;
      end
   end
end



always @(posedge clk) begin
   if (rstp == 1'b1) begin
      count <= 0;
   end
   else begin
      case ({readp, writep})
         2'b00: count <= count;
         2'b01: 

            if (!fullp) 
               count <= count + 1;
         2'b10: 

            if (!emptyp)
               count <= count - 1;
         2'b11:

            count <= count - 1;
      endcase
   end
end

         



always @(count) begin
   if (count == EMPTY)
     emptyp = 1'b1;
   else
     emptyp = 1'b0;
end



always @(count) begin
   if (count < FULL)
      fullp = 1'b0;
   else
      fullp = 1'b1;
end

endmodule
module sync_fifo (clk, rstp, src_in, dst_in, data_in, writep, readp, 
	src_out, dst_out, data_out, emptyp, fullp);

input		clk;
input		rstp;
input [7:0]	src_in;
input [7:0]	dst_in;
input [31:0]	data_in;
input		readp;
input		writep;
output [7:0]	src_out;
output [7:0]	dst_out;
output [31:0]	data_out;
output		emptyp;
output		fullp;



parameter	DEPTH = 2,	
		FULL = (1<<3),
		EMPTY = (1<<3);

reg 		emptyp;
reg		fullp;


reg [7:0]	src_out;
reg [7:0]	dst_out;
reg [31:0]	data_out;



reg [(DEPTH-1):0]	tail;
reg [(DEPTH-1):0]	head;




reg [DEPTH:0]	count;




reg [47:0] fifomem[0:FULL];



integer i;
always @(posedge clk or posedge rstp) begin
   if (rstp == 1) begin
      src_out <= 8'b0;
      dst_out <= 8'b0;
      data_out <= 32'b0;
   end
   else begin
      {src_out,dst_out,data_out} <= fifomem[tail];
   end
end 
     

always @(posedge clk)
   if (rstp == 1'b0) begin
     if (writep == 1'b1 && fullp == 1'b0)
      fifomem[head] <= {src_in,dst_in,data_in};
   end



always @(posedge clk) begin
   if (rstp == 1'b1) begin
     head <= 0;
   end
   else begin
      if (writep == 1'b1 && fullp == 1'b0) begin

         head <= head + 1;
      end
   end
end



always @(posedge clk) begin
   if (rstp == 1'b1) begin
      tail <= 0;
   end
   else begin
      if (readp == 1'b1 && emptyp == 1'b0) begin

         tail <= tail + 1;
      end
   end
end



always @(posedge clk) begin
   if (rstp == 1'b1) begin
      count <= 0;
   end
   else begin
      case ({readp, writep})
         2'b00: count <= count;
         2'b01: 

            if (!fullp) 
               count <= count + 1;
         2'b10: 

            if (!emptyp)
               count <= count - 1;
         2'b11:

            count <= count - 1;
      endcase
   end
end

         



always @(count) begin
   if (count == EMPTY)
     emptyp = 1'b1;
   else
     emptyp = 1'b0;
end



always @(count) begin
   if (count < FULL)
      fullp = 1'b0;
   else
      fullp = 1'b1;
end

endmodule