data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl/clk_gen_tb.v
 line:18: before: "."
1: b'%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl/clk_gen_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n     forever #5 clk_source = !clk_source;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl/clk_gen_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n     forever #5 clk = !clk;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl/clk_gen_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl/clk_gen_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl/clk_gen_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n     #5\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl/clk_gen_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n     #5\n     ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl/clk_gen_tb.v:17: Cannot find file containing module: \'clk_gen\'\n clk_gen tb(clk_source,clk_out,clk,reset_n,chipselect,address,read,write,readdata,writedata);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl,data/full_repos/permissive/117851934/clk_gen\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl,data/full_repos/permissive/117851934/clk_gen.v\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl,data/full_repos/permissive/117851934/clk_gen.sv\n             clk_gen\n             clk_gen.v\n             clk_gen.sv\n             obj_dir/clk_gen\n             obj_dir/clk_gen.v\n             obj_dir/clk_gen.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clk_gen_tb;
 parameter clk_num=4;
 	reg clk_source,clk,reset_n,chipselect,read,write;
 	reg [31:0] writedata;
 	reg [4:0] address;
 	wire	[clk_num-1:0] clk_out;
 	wire [31:0] readdata;					
 clk_gen tb(clk_source,clk_out,clk,reset_n,chipselect,address,read,write,readdata,writedata);
  defparam tb.clk_num=clk_num;

 initial                         
   begin
     clk_source = 0;
     forever #`delay clk_source = !clk_source;
   end
 initial                         
   begin
     clk=0;
     forever #`delay clk = !clk;
   end
task  avalon_write;
  input [4:0] addr;
  input [31:0] data;
  begin
  #`delay;
	address=addr;
	writedata=data;
	chipselect=1;
	write=1;
	#`delay;
	chipselect=0;
	write=0;
	end
endtask
   
 initial                         
   begin
     reset_n = 1;
     #`delay
     reset_n = 0;
     #`delay
     reset_n = 1;
     
     avalon_write(5'h0,32'h2);
     avalon_write(5'h1,32'h3); 
     avalon_write(5'h2,32'h4); 
     avalon_write(5'h3,32'h1); 
     
   end


 endmodule
module clk_gen_tb;

 parameter clk_num=4;
 	reg clk_source,clk,reset_n,chipselect,read,write;
 	reg [31:0] writedata;
 	reg [4:0] address;
 	wire	[clk_num-1:0] clk_out;
 	wire [31:0] readdata;					
 clk_gen tb(clk_source,clk_out,clk,reset_n,chipselect,address,read,write,readdata,writedata);
  defparam tb.clk_num=clk_num;

 initial                         
   begin
     clk_source = 0;
     forever #`delay clk_source = !clk_source;
   end
 initial                         
   begin
     clk=0;
     forever #`delay clk = !clk;
   end
task  avalon_write;
  input [4:0] addr;
  input [31:0] data;
  begin
  #`delay;
	address=addr;
	writedata=data;
	chipselect=1;
	write=1;
	#`delay;
	chipselect=0;
	write=0;
	end
endtask
   
 initial                         
   begin
     reset_n = 1;
     #`delay
     reset_n = 0;
     #`delay
     reset_n = 1;
     
     avalon_write(5'h0,32'h2);
     avalon_write(5'h1,32'h3); 
     avalon_write(5'h2,32'h4); 
     avalon_write(5'h3,32'h1); 
     
   end


 endmodule