data/full_repos/permissive/138961980/powlib_std.v
 line:24: before: "if"
1: b'%Error: data/full_repos/permissive/138961980/powlib_std.v:195: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh.v\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh.sv\n             powlib_std.vh\n             powlib_std.vh.v\n             powlib_std.vh.sv\n             obj_dir/powlib_std.vh\n             obj_dir/powlib_std.vh.v\n             obj_dir/powlib_std.vh.sv\n%Error: data/full_repos/permissive/138961980/powlib_std.v:221: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:252: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:207: Define or directive not defined: \'`POWLIB_DW\'\n            wire [`POWLIB_DW-1:0] d0 = powlib_grayencode(d); \n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:233: Define or directive not defined: \'`POWLIB_DW\'\n            wire [`POWLIB_DW-1:0] d0 = powlib_graydecode(d); \n                  ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module powlib_cntr(cntr,nval,adv,ld,dx,clr,clk,rst);


  
  parameter              W     = 32;
  parameter      [W-1:0] X     = 1;
  parameter      [W-1:0] INIT  = 0;
  parameter              ELD   = 1;
  parameter              EDX   = 0;
  parameter              EAR   = 0;
  output    wire [W-1:0] cntr;
  input     wire [W-1:0] nval;
  input     wire         adv;
  input     wire         ld;
  input     wire [W-1:0] dx;
  input     wire         clr;
  input     wire         clk;
  input     wire         rst;
   
            wire         ld0   = ld && (ELD!=0);
            wire [W-1:0] x0    = (EDX!=0) ? dx : X;        
  
  powlib_flipflop #(.W(W),.INIT(INIT),.EAR(EAR),.EVLD(1)) cntr_inst (
    .d((clr) ? INIT    : 
       (ld0) ? nval    :
       (adv) ? cntr+x0 : {W{1'bz}}),
    .q(cntr),
    .clk(clk),
    .rst(rst),
    .vld(clr||ld0||adv));
  
endmodule
module powlib_cntr(cntr,nval,adv,ld,dx,clr,clk,rst);



  
  parameter              W     = 32;
  parameter      [W-1:0] X     = 1;
  parameter      [W-1:0] INIT  = 0;
  parameter              ELD   = 1;
  parameter              EDX   = 0;
  parameter              EAR   = 0;
  output    wire [W-1:0] cntr;
  input     wire [W-1:0] nval;
  input     wire         adv;
  input     wire         ld;
  input     wire [W-1:0] dx;
  input     wire         clr;
  input     wire         clk;
  input     wire         rst;
   
            wire         ld0   = ld && (ELD!=0);
            wire [W-1:0] x0    = (EDX!=0) ? dx : X;        
  
  powlib_flipflop #(.W(W),.INIT(INIT),.EAR(EAR),.EVLD(1)) cntr_inst (
    .d((clr) ? INIT    : 
       (ld0) ? nval    :
       (adv) ? cntr+x0 : {W{1'bz}}),
    .q(cntr),
    .clk(clk),
    .rst(rst),
    .vld(clr||ld0||adv));
  
endmodule