data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v:193: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'populate_candidates\'\nmodule populate_candidates (\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'find_best_iso\'\nmodule find_best_iso (\n       ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v:235: Signal definition not found, creating implicitly: \'fi_done\'\n                                                                                              : ... Suggested alternative: \'fi_en\'\n .complete ( fi_done )\n             ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v:35: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                          : ... In instance populate_candidates.hd\n distance = bit_diff[0] + bit_diff[1] + bit_diff[2] + bit_diff[3]\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v:35: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                          : ... In instance populate_candidates.hd\n distance = bit_diff[0] + bit_diff[1] + bit_diff[2] + bit_diff[3]\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v:35: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                          : ... In instance populate_candidates.hd\n distance = bit_diff[0] + bit_diff[1] + bit_diff[2] + bit_diff[3]\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v:35: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                          : ... In instance populate_candidates.hd\n distance = bit_diff[0] + bit_diff[1] + bit_diff[2] + bit_diff[3]\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v:36: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                          : ... In instance populate_candidates.hd\n    + bit_diff[4] + bit_diff[5] + bit_diff[6] + bit_diff[7];\n    ^\n%Warning-WIDTH: data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v:36: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                          : ... In instance populate_candidates.hd\n    + bit_diff[4] + bit_diff[5] + bit_diff[6] + bit_diff[7];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v:36: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                          : ... In instance populate_candidates.hd\n    + bit_diff[4] + bit_diff[5] + bit_diff[6] + bit_diff[7];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v:36: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                          : ... In instance populate_candidates.hd\n    + bit_diff[4] + bit_diff[5] + bit_diff[6] + bit_diff[7];\n                                              ^\n%Error: data/full_repos/permissive/12930831/code-search/verilog/icblbc/icblbc.v:222: Cannot find file containing module: \'icblbc_ram\'\nicblbc_ram codes (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/12930831/code-search/verilog/icblbc,data/full_repos/permissive/12930831/icblbc_ram\n             data/full_repos/permissive/12930831/code-search/verilog/icblbc,data/full_repos/permissive/12930831/icblbc_ram.v\n             data/full_repos/permissive/12930831/code-search/verilog/icblbc,data/full_repos/permissive/12930831/icblbc_ram.sv\n             icblbc_ram\n             icblbc_ram.v\n             icblbc_ram.sv\n             obj_dir/icblbc_ram\n             obj_dir/icblbc_ram.v\n             obj_dir/icblbc_ram.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n'
module hamming_distance (
input wire clock,
input wire [7:0] val_a, val_b,
output reg [3:0] distance
);

wire [7:0] bit_diff;
assign bit_diff = val_a ^ val_b;

always @(posedge clock) begin

	distance = bit_diff[0] + bit_diff[1] + bit_diff[2] + bit_diff[3]
			 + bit_diff[4] + bit_diff[5] + bit_diff[6] + bit_diff[7];
end
endmodule
module hamming_distance (
input wire clock,
input wire [7:0] val_a, val_b,
output reg [3:0] distance
);


wire [7:0] bit_diff;
assign bit_diff = val_a ^ val_b;

always @(posedge clock) begin

	distance = bit_diff[0] + bit_diff[1] + bit_diff[2] + bit_diff[3]
			 + bit_diff[4] + bit_diff[5] + bit_diff[6] + bit_diff[7];
end
endmodule