data/full_repos/permissive/169294490/FPGA/src/misc/counter.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/169294490/FPGA/src/misc/counter.v:15: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h0\' generates 31 bits.\n                                                                               : ... In instance counter\n        out <= 31\'b0 ;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module counter (
    out,
    enable,
    clk,
    reset
);

output [31:0] out;
input enable, clk, reset;

reg [31:0] out;

always @(posedge clk)
    if (reset) begin
        out <= 31'b0 ;
    end else if (enable) begin
        out <= out + 1;
    end
endmodule
module counter (
    out,
    enable,
    clk,
    reset
);


output [31:0] out;
input enable, clk, reset;

reg [31:0] out;

always @(posedge clk)
    if (reset) begin
        out <= 31'b0 ;
    end else if (enable) begin
        out <= out + 1;
    end
endmodule