data/full_repos/permissive/125927162/4017/4017_tb.v
 line:42: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/4017/4017_tb.v:32: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("4017.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/4017/4017_tb.v:33: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, ln4017_tb);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/4017/4017_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #15\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/4017/4017_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #1000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/4017/4017_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #1000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/4017/4017_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n   always #5 cp0 = ~cp0;\n          ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ln4017_tb ();
   reg cp0;
   reg cp1;
   reg mr;
   wire [9:0] out;
   wire	     q59_n;

   ln4017 DUT(
	      .cp0(cp0),
	      .cp1(cp1),
	      .mr(mr),
	      .out_q(out),
	      .q59_n(q59_n)
	      );

   initial begin
      $dumpfile("4017.vcd");
      $dumpvars(0, ln4017_tb);
      mr = 1;
      cp0 = 0;
      cp1 = 0;
      #15
	mr = 0;
      #1000
	cp1 = 1;
      #1000
	$finish;
   end

   always #5 cp0 = ~cp0;

endmodule
module ln4017_tb ();

   reg cp0;
   reg cp1;
   reg mr;
   wire [9:0] out;
   wire	     q59_n;

   ln4017 DUT(
	      .cp0(cp0),
	      .cp1(cp1),
	      .mr(mr),
	      .out_q(out),
	      .q59_n(q59_n)
	      );

   initial begin
      $dumpfile("4017.vcd");
      $dumpvars(0, ln4017_tb);
      mr = 1;
      cp0 = 0;
      cp1 = 0;
      #15
	mr = 0;
      #1000
	cp1 = 1;
      #1000
	$finish;
   end

   always #5 cp0 = ~cp0;

endmodule