data/full_repos/permissive/113582216/Experiment/FPGA1/vFullAdd/vFullAdd.v
data/verilator_xmls/c010f426-f35d-4c40-905a-4265d3039199.xml
module vFullAdd(
	input a,
	input b,
	input c0,
	output s,
	output c
	);
	
	assign {c,s} = a + b + c0;
	
endmodule
module vFullAdd(
	input a,
	input b,
	input c0,
	output s,
	output c
	);

	
	assign {c,s} = a + b + c0;
	
endmodule