data/full_repos/permissive/21051978/processor/spare/build3/umult8tb.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/spare/build3/umult8tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/processor/spare/build3/umult8tb.v:14: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] result;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/processor/spare/build3/umult8tb.v:16: Little bit endian vector: MSB < LSB of bit range: 0:7\n reg [0:7] reg_A, reg_B;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/21051978/processor/spare/build3/umult8tb.v:18: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] e_result;\n     ^\n%Error: data/full_repos/permissive/21051978/processor/spare/build3/umult8tb.v:22: Cannot find file containing module: \'umult8\'\n umult8 umult8_1 (reg_A,reg_B,result);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor/spare/build3,data/full_repos/permissive/21051978/umult8\n             data/full_repos/permissive/21051978/processor/spare/build3,data/full_repos/permissive/21051978/umult8.v\n             data/full_repos/permissive/21051978/processor/spare/build3,data/full_repos/permissive/21051978/umult8.sv\n             umult8\n             umult8.v\n             umult8.sv\n             obj_dir/umult8\n             obj_dir/umult8.v\n             obj_dir/umult8.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module umult8tb();
	
	wire [0:15] result;
	
	reg [0:7] reg_A, reg_B;
	
	reg [0:15] e_result;
	
	
	
	umult8 umult8_1 (reg_A,reg_B,result);
	
	
	initial
	begin

		$display($time, " << Starting the simulation >>");	
		
		reg_B=8'h02;
		reg_A=8'h03;
		e_result=16'h06;
		#10;
		
		
		

		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule
module umult8tb();

	
	wire [0:15] result;
	
	reg [0:7] reg_A, reg_B;
	
	reg [0:15] e_result;
	
	
	
	umult8 umult8_1 (reg_A,reg_B,result);
	
	
	initial
	begin

		$display($time, " << Starting the simulation >>");	
		
		reg_B=8'h02;
		reg_A=8'h03;
		e_result=16'h06;
		#10;
		
		
		

		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule