data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv
 line:94 column:14: Illegal character "'"
1: b'%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:100: Unsupported: Ignoring delay on this delayed statement.\n      #1 vsync = \'0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:102: syntax error, unexpected \'@\'\n      repeat(VERT_BLANK) @(posedge clk);\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:103: Unsupported: Ignoring delay on this delayed statement.\n      #1 vsync = \'1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:109: Unsupported: Ignoring delay on this delayed statement.\n      #1 vsync = \'1;\n      ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:111: syntax error, unexpected \'@\'\n      repeat(VERT_BLANK) @(posedge clk);\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:112: Unsupported: Ignoring delay on this delayed statement.\n      #1 vsync = \'0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:118: Unsupported: Ignoring delay on this delayed statement.\n        #1 vsync = \'1;\n        ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:121: syntax error, unexpected \'@\'\n        repeat(HOR_BLANK) @(posedge clk);\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:130: Unsupported: Ignoring delay on this delayed statement.\n        #1 pixel = pxl;\n        ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:131: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:140: Unsupported: Ignoring delay on this delayed statement.\n        #1 pixel = \'0;\n        ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:142: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/camera_model.sv:144: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to 6 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module camera_model #(
  parameter FOUR_BITS  = "FALSE",
  parameter WIDTH      = 8  ,
  parameter MAX_COLS   = 1000,
  parameter MAX_ROWS   = 1000,
  parameter HOR_BLANK  = 4   ,
  parameter VERT_BLANK = 6
) (
  input                    clk  ,
  output logic [WIDTH-1:0] pixel,
  output logic             vsync,
  output logic             hsync
);

  initial begin
    vsync = 1'b0;
    hsync = 1'b0;
    pixel = '0;
  end


  task vert_blank_start;
    begin
      #1 vsync = '0;
      hsync = '0;
      repeat(VERT_BLANK) @(posedge clk);
      #1 vsync = '1;
    end
  endtask

  task vert_blank_end;
    begin
      #1 vsync = '1;
      hsync = '0;
      repeat(VERT_BLANK) @(posedge clk);
      #1 vsync = '0;
    end
  endtask

task hor_blank;
    begin
        #1 vsync = '1;
        hsync = '0;
        pixel = '0;
        repeat(HOR_BLANK) @(posedge clk);
    end
endtask

task write_pixel;
    input [WIDTH-1:0] pxl;
    begin
        vsync = '1;
        hsync = '1;
        #1 pixel = pxl;
        @(posedge clk);
    end
endtask

task write_pixel_4bits;
    input [WIDTH-1:0] pxl;
    begin
        vsync = '1;
        hsync = '1;
        #1 pixel = '0;
           pixel[WIDTH/2-1:0] = pxl[WIDTH-1:WIDTH/2];
        @(posedge clk);
           pixel[WIDTH/2-1:0] = pxl[WIDTH/2-1:0];
        @(posedge clk);
    end
endtask

task write_frame;
    input integer num_cols;
    input integer num_rows;
    input logic [WIDTH-1:0] data_i [0:MAX_COLS*MAX_ROWS-1];
    begin
        integer row_cnt;
        row_cnt = 0;


        vert_blank_start();

        for (int r=0; r<num_rows; r++) begin
            hor_blank();


            for (int c=0; c<num_cols; c++) begin
                if (FOUR_BITS == "FALSE")
                    write_pixel(data_i[r*num_cols+c]);
                else
                    write_pixel_4bits(data_i[r*num_cols+c]);
            end


            hor_blank();
            vert_blank_end();


        end
    end
endtask

endmodule
module camera_model #(
  parameter FOUR_BITS  = "FALSE",
  parameter WIDTH      = 8  ,
  parameter MAX_COLS   = 1000,
  parameter MAX_ROWS   = 1000,
  parameter HOR_BLANK  = 4   ,
  parameter VERT_BLANK = 6
) (
  input                    clk  ,
  output logic [WIDTH-1:0] pixel,
  output logic             vsync,
  output logic             hsync
);


  initial begin
    vsync = 1'b0;
    hsync = 1'b0;
    pixel = '0;
  end


  task vert_blank_start;
    begin
      #1 vsync = '0;
      hsync = '0;
      repeat(VERT_BLANK) @(posedge clk);
      #1 vsync = '1;
    end
  endtask

  task vert_blank_end;
    begin
      #1 vsync = '1;
      hsync = '0;
      repeat(VERT_BLANK) @(posedge clk);
      #1 vsync = '0;
    end
  endtask

task hor_blank;
    begin
        #1 vsync = '1;
        hsync = '0;
        pixel = '0;
        repeat(HOR_BLANK) @(posedge clk);
    end
endtask

task write_pixel;
    input [WIDTH-1:0] pxl;
    begin
        vsync = '1;
        hsync = '1;
        #1 pixel = pxl;
        @(posedge clk);
    end
endtask

task write_pixel_4bits;
    input [WIDTH-1:0] pxl;
    begin
        vsync = '1;
        hsync = '1;
        #1 pixel = '0;
           pixel[WIDTH/2-1:0] = pxl[WIDTH-1:WIDTH/2];
        @(posedge clk);
           pixel[WIDTH/2-1:0] = pxl[WIDTH/2-1:0];
        @(posedge clk);
    end
endtask

task write_frame;
    input integer num_cols;
    input integer num_rows;
    input logic [WIDTH-1:0] data_i [0:MAX_COLS*MAX_ROWS-1];
    begin
        integer row_cnt;
        row_cnt = 0;


        vert_blank_start();

        for (int r=0; r<num_rows; r++) begin
            hor_blank();


            for (int c=0; c<num_cols; c++) begin
                if (FOUR_BITS == "FALSE")
                    write_pixel(data_i[r*num_cols+c]);
                else
                    write_pixel_4bits(data_i[r*num_cols+c]);
            end


            hor_blank();
            vert_blank_end();


        end
    end
endtask

endmodule