data/full_repos/permissive/185914332/solution_attempts/washing_machine_1.v
 line:1: before: ")"
1: b"%Error: data/full_repos/permissive/185914332/solution_attempts/washing_machine_1.v:1: syntax error, unexpected ')', expecting '['\nmodule counter(clk, reset, cycles,  );\n                                    ^\n%Error: data/full_repos/permissive/185914332/solution_attempts/washing_machine_1.v:7: syntax error, unexpected always\nalways @ (posedge clk or posedge reset)\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module counter(clk, reset, cycles,);
input clk, reset, cycles;


reg [7:0]count;

always @ (posedge clk or posedge reset)
	begin: timer_implementation
		while(count <= cycles && cycles!=0) begin
			if (reset) count <= 0;
			else	count <= count + 1;
		end

	end
endmodule
module counter(clk, reset, cycles,);

input clk, reset, cycles;


reg [7:0]count;

always @ (posedge clk or posedge reset)
	begin: timer_implementation
		while(count <= cycles && cycles!=0) begin
			if (reset) count <= 0;
			else	count <= count + 1;
		end

	end
endmodule