data/full_repos/permissive/100975158/MIPS32_Full/Processor/DataMemoryInterface.v
1: b'%Warning-WIDTH: data/full_repos/permissive/100975158/MIPS32_Full/Processor/DataMemoryInterface.v:30: Bit extraction of array[255:0] requires 8 bit index, not 7 bits.\n                                                                                                   : ... In instance DataMemoryInterface\n                memory[address[8:2]] <= data_write;  \n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100975158/MIPS32_Full/Processor/DataMemoryInterface.v:36: Bit extraction of array[255:0] requires 8 bit index, not 7 bits.\n                                                                                                   : ... In instance DataMemoryInterface\n    assign read_data = (mem_read) ? memory[address[8:2]] : 32\'hxxxxxxxx;\n                                          ^\n%Error: Exiting due to 2 warning(s)\n'
module DataMemoryInterface (
    input           clock,
    input           reset,
    input [31:0]    address,
    input           mem_write,
    input [31:0]    data_write,
    input           mem_read,
    output [31:0]   read_data
);

    reg [31:0] memory [0:255];

    integer i;
    initial begin
        for (i = 0; i < 256; i = i + 1) begin
            memory[i] = 0;
        end
    end

    always @ (posedge clock) begin
        if (reset) begin
            for (i = 0; i < 256; i = i + 1) begin
                memory[i] = 0;
            end
        end
        else begin
            if (mem_write) begin
                memory[address[8:2]] <= data_write;
            end
        end
    end


    assign read_data = (mem_read) ? memory[address[8:2]] : 32'hxxxxxxxx;

endmodule
module DataMemoryInterface (
    input           clock,
    input           reset,
    input [31:0]    address,
    input           mem_write,
    input [31:0]    data_write,
    input           mem_read,
    output [31:0]   read_data
);


    reg [31:0] memory [0:255];

    integer i;
    initial begin
        for (i = 0; i < 256; i = i + 1) begin
            memory[i] = 0;
        end
    end

    always @ (posedge clock) begin
        if (reset) begin
            for (i = 0; i < 256; i = i + 1) begin
                memory[i] = 0;
            end
        end
        else begin
            if (mem_write) begin
                memory[address[8:2]] <= data_write;
            end
        end
    end


    assign read_data = (mem_read) ? memory[address[8:2]] : 32'hxxxxxxxx;

endmodule