data/full_repos/permissive/146618947/pipeline_tarea9/sumador_cond.v
1: b"%Error: data/full_repos/permissive/146618947/pipeline_tarea9/sumador_cond.v:13: Cannot find file containing module: 'sum_pipe_cond'\n   sum_pipe_cond spc (\n   ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146618947/pipeline_tarea9,data/full_repos/permissive/146618947/sum_pipe_cond\n             data/full_repos/permissive/146618947/pipeline_tarea9,data/full_repos/permissive/146618947/sum_pipe_cond.v\n             data/full_repos/permissive/146618947/pipeline_tarea9,data/full_repos/permissive/146618947/sum_pipe_cond.sv\n             sum_pipe_cond\n             sum_pipe_cond.v\n             sum_pipe_cond.sv\n             obj_dir/sum_pipe_cond\n             obj_dir/sum_pipe_cond.v\n             obj_dir/sum_pipe_cond.sv\n%Error: Exiting due to 1 error(s)\n"
module sumador_cond (
                     input        clk,
                     input        reset_L,
                     input [3:0]  idx,
                     input [3:0]  dataA,
                     input [3:0]  dataB,
                     output reg [3:0] idx_dd,
                     output [3:0] sum30_dd
                     );

   reg [3:0]                      idx_d;

   sum_pipe_cond spc (
                      .clk (clk),
                      .reset_L (reset_L),
                      .dataA (dataA),
                      .dataB (dataB),
                      .sum30_dd (sum30_dd)
                      );

   always @ (posedge clk) begin
      if (!reset_L) begin
         idx_d <= 0;
         idx_dd <= 0;
      end else begin
         idx_d <= idx + 1;
         idx_dd <= idx_d + 1;
      end
   end

endmodule
module sumador_cond (
                     input        clk,
                     input        reset_L,
                     input [3:0]  idx,
                     input [3:0]  dataA,
                     input [3:0]  dataB,
                     output reg [3:0] idx_dd,
                     output [3:0] sum30_dd
                     );


   reg [3:0]                      idx_d;

   sum_pipe_cond spc (
                      .clk (clk),
                      .reset_L (reset_L),
                      .dataA (dataA),
                      .dataB (dataB),
                      .sum30_dd (sum30_dd)
                      );

   always @ (posedge clk) begin
      if (!reset_L) begin
         idx_d <= 0;
         idx_dd <= 0;
      end else begin
         idx_d <= idx + 1;
         idx_dd <= idx_d + 1;
      end
   end

endmodule