data/full_repos/permissive/196070799/src/UserInputHandler.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/ebab95e3-b24e-494b-bd4e-5b01e4620070.xml
module UserInputHandler
(
  IN_CLOCK                                                                                              ,
  IN_RESET_N                                                                                            ,
  IN_BUTTONS                                                                                            ,
  IN_COMP                                                                                               ,
  IN_CHECK                                                                                              ,
  OUT_SUCCESS                                                                                           ,
  OUT_FAILED                                            
);

input                           IN_CLOCK                                                                ;
input                           IN_RESET_N                                                              ;
input           [3:0]           IN_BUTTONS                                                              ;
input           [3:0]           IN_COMP                                                                 ;
input                           IN_CHECK                                                                ;
output reg                      OUT_SUCCESS                                                             ;
output reg                      OUT_FAILED                                                              ;


reg                             succ_r                                                                  ;
reg                             succ_r_d0                                                               ;
reg                             fail_r                                                                  ;
reg                             fail_r_d0                                                               ;


always @ (posedge IN_CLOCK) begin
  if (!IN_RESET_N) begin
    succ_r                                          <= 1'b0                                             ;
    fail_r                                          <= 1'b0                                             ;
    succ_r_d0                                       <= 1'b0                                             ;
    fail_r_d0                                       <= 1'b0                                             ;
  end
  else begin
    if (IN_CHECK == 1'b1) begin
      if (IN_BUTTONS != 4'b0000) begin
        if (IN_BUTTONS == IN_COMP) begin
          succ_r                                    <= 1'b1                                             ;
          fail_r                                    <= 1'b0                                             ;
          succ_r_d0                                 <= succ_r                                           ;
          fail_r_d0                                 <= fail_r                                           ;
        end
        else begin
          succ_r                                    <= 1'b0                                             ;
          fail_r                                    <= 1'b1                                             ;
          succ_r_d0                                 <= succ_r                                           ;
          fail_r_d0                                 <= fail_r                                           ;
        end
      end
      else begin
        succ_r                                      <= 1'b0                                             ;
        fail_r                                      <= 1'b0                                             ;
        succ_r_d0                                   <= 1'b0                                             ;
        fail_r_d0                                   <= 1'b0                                             ;
      end
    end
    else begin
      succ_r                                        <= 1'b0                                             ;
      fail_r                                        <= 1'b0                                             ;
      succ_r_d0                                     <= 1'b0                                             ;
      fail_r_d0                                     <= 1'b0                                             ;
    end
  end
end


always @ (posedge IN_CLOCK) begin
  if (!IN_RESET_N) begin
    OUT_SUCCESS                                     <= 1'b0                                             ;
    OUT_FAILED                                      <= 1'b0                                             ;
  end
  else begin
    OUT_SUCCESS                                     <= ((succ_r == 1'b1) & (succ_r_d0 == 1'b0))         ;
    OUT_FAILED                                      <= ((fail_r == 1'b1) & (fail_r_d0 == 1'b0))         ;
  end
end

endmodule
module UserInputHandler
(
  IN_CLOCK                                                                                              ,
  IN_RESET_N                                                                                            ,
  IN_BUTTONS                                                                                            ,
  IN_COMP                                                                                               ,
  IN_CHECK                                                                                              ,
  OUT_SUCCESS                                                                                           ,
  OUT_FAILED                                            
);


input                           IN_CLOCK                                                                ;
input                           IN_RESET_N                                                              ;
input           [3:0]           IN_BUTTONS                                                              ;
input           [3:0]           IN_COMP                                                                 ;
input                           IN_CHECK                                                                ;
output reg                      OUT_SUCCESS                                                             ;
output reg                      OUT_FAILED                                                              ;


reg                             succ_r                                                                  ;
reg                             succ_r_d0                                                               ;
reg                             fail_r                                                                  ;
reg                             fail_r_d0                                                               ;


always @ (posedge IN_CLOCK) begin
  if (!IN_RESET_N) begin
    succ_r                                          <= 1'b0                                             ;
    fail_r                                          <= 1'b0                                             ;
    succ_r_d0                                       <= 1'b0                                             ;
    fail_r_d0                                       <= 1'b0                                             ;
  end
  else begin
    if (IN_CHECK == 1'b1) begin
      if (IN_BUTTONS != 4'b0000) begin
        if (IN_BUTTONS == IN_COMP) begin
          succ_r                                    <= 1'b1                                             ;
          fail_r                                    <= 1'b0                                             ;
          succ_r_d0                                 <= succ_r                                           ;
          fail_r_d0                                 <= fail_r                                           ;
        end
        else begin
          succ_r                                    <= 1'b0                                             ;
          fail_r                                    <= 1'b1                                             ;
          succ_r_d0                                 <= succ_r                                           ;
          fail_r_d0                                 <= fail_r                                           ;
        end
      end
      else begin
        succ_r                                      <= 1'b0                                             ;
        fail_r                                      <= 1'b0                                             ;
        succ_r_d0                                   <= 1'b0                                             ;
        fail_r_d0                                   <= 1'b0                                             ;
      end
    end
    else begin
      succ_r                                        <= 1'b0                                             ;
      fail_r                                        <= 1'b0                                             ;
      succ_r_d0                                     <= 1'b0                                             ;
      fail_r_d0                                     <= 1'b0                                             ;
    end
  end
end


always @ (posedge IN_CLOCK) begin
  if (!IN_RESET_N) begin
    OUT_SUCCESS                                     <= 1'b0                                             ;
    OUT_FAILED                                      <= 1'b0                                             ;
  end
  else begin
    OUT_SUCCESS                                     <= ((succ_r == 1'b1) & (succ_r_d0 == 1'b0))         ;
    OUT_FAILED                                      <= ((fail_r == 1'b1) & (fail_r_d0 == 1'b0))         ;
  end
end

endmodule