data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp
 line:10: before: "("
1: b"%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:10: Define or directive not defined: '`mname'\nmodule  `mname()`;\n        ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:10: syntax error, unexpected '(', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule  `mname()`;\n               ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:56: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:135: syntax error, unexpected assign\nassign mad_full = (next_op_a_in*next_op_b_in) + next_op_c_in;\n^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:143: Unsupported or unknown PLI call: $urandom_range\n        pre_nextOP               <= pe_oper'($urandom_range(17,0));  \n                                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:144: Unsupported or unknown PLI call: $urandom_range\n        is_signed_pre_next <= $urandom_range(1,0);\n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:149: syntax error, unexpected assign\nassign full_sum = next_op_a_in + next_op_b_in + next_op_c_in + next_op_d_p_in;\n^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:191: Unsupported or unknown PLI call: $urandom_range\n        next_op_a_msb_in <= $urandom_range(2**DataWidth - 1,0);\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:192: Unsupported or unknown PLI call: $urandom_range\n        next_op_b_msb_in <= $urandom_range(2**DataWidth - 1,0);\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:194: Unsupported or unknown PLI call: $urandom_range\n        next_op_a_in <= $urandom_range(2**DataWidth - 1,0);\n                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:195: Unsupported or unknown PLI call: $urandom_range\n        next_op_b_in <= {2{16'($urandom_range(31,0))}}; \n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:196: Unsupported or unknown PLI call: $urandom_range\n        next_op_c_in <= $urandom_range(2**DataWidth - 1,0);\n                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:198: Unsupported or unknown PLI call: $urandom_range\n        next_op_d_p_in <= $urandom_range(1,0);\n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:275: Unsupported or unknown PLI call: $urandom_range\n                next_op_b_in <= {2{16'($urandom_range(16,0))}}; \n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:282: Unsupported or unknown PLI call: $urandom_range\n                next_op_b_in <= {2{16'($urandom_range(16,0))}}; \n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:289: Unsupported or unknown PLI call: $urandom_range\n                next_op_b_in <= {2{16'($urandom_range(16,0))}}; \n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:369: Unsupported or unknown PLI call: $dut\n`$dut->instantiate()` (\n ^~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/pe/verif/test_pe/test_pe_comp_tb.svp:397: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Exiting due to 18 error(s)\n"
module  `mname()`;

localparam DataWidth = 16;
localparam DataMSB   = DataWidth-1;


logic                clk;
logic                rst_n;

logic [DataMSB:0] next_op_a_msb_in;
logic [DataMSB:0] next_op_b_msb_in;


logic [DataMSB:0] next_op_a_in;
logic [DataMSB:0] next_op_b_in;
logic [DataMSB:0] next_op_c_in;

logic                           next_op_d_p_in;

logic [DataMSB:0] op_a_msb_in;
logic [DataMSB:0] op_b_msb_in;

logic [DataMSB:0] op_a_in;
logic [DataMSB:0] op_b_in;
logic [DataMSB:0] op_c_in;

logic                           op_d_p_in;

logic [DataMSB:0] res;
logic                           res_p;

logic [15:0]    op_code;

bit [31:0] count;

bit [4*DataWidth-1:0] exp_mult32_res;
bit [DataMSB:0] exp_res;
bit                         exp_res_p;

bit                         ignore_res;
bit                         ignore_res_p;


bit fail_res, fail_res_p, fail, fail_latch;


initial begin
    #1000000 $display("Time = %d clk = %b", $time, clk);


    if(fail_latch)
        $display("\nAt least one test has FAILED!\n");
    else
        $display("\nAll tests Passed\n");

     $finish;
end

initial begin
    #1 clk = 1;
    forever begin
        #5 clk = ~clk;
    end
end

initial begin
    rst_n = 0;
    repeat(10) @(posedge clk);
    rst_n = 1;
end

always_ff @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        fail_latch <= 0;
    else if(fail)
        fail_latch <= 1;
end

assign fail_res     = ~ignore_res & (exp_res !== res);
assign fail_res_p = ~ignore_res_p & (exp_res_p !== res_p);
assign fail             = fail_res | fail_res_p;


typedef enum {
Add_Op, Sub_Op, Abs_Op, GteMax_Op, LteMin_Op, Eq_Op,
Sel_Op, Rshft_Op, RshftS_Op, Lshft_Op, Mult0_Op, Mult1_Op, Mult2_Op, Or_Op,
And_Op, Xor_Op, Inv_Op, Cntr_Op, Div_Op, InvalidOp
} pe_oper;

pe_oper pre_nextOP;
pe_oper nextOP;
pe_oper currentOP;

localparam PE_ADD_OP         = 6'h0;
localparam PE_SUB_OP         = 6'h1;

localparam PE_ABS_OP         = 6'h3;

localparam PE_GTE_MAX_OP = 6'h4;
localparam PE_LTE_MIN_OP = 6'h5;
localparam PE_EQ_OP          = 6'h6;

localparam PE_SEL_OP         = 6'h8;

localparam PE_RSHFT_OP   = 6'hF;
localparam PE_RSHFT_S_OP = 6'h10;
localparam PE_LSHFT_OP   = 6'h11;

localparam PE_MULT_0_OP  = 6'hB;
localparam PE_MULT_1_OP  = 6'hC;
localparam PE_MULT_2_OP  = 6'hD;

localparam PE_OR_OP          = 6'h12;
localparam PE_AND_OP         = 6'h13;
localparam PE_XOR_OP         = 6'h14;
localparam PE_INV_OP         = 6'h15;

localparam PE_CNTR_OP        = 6'h18;

localparam PE_DIV_OP        = 6'h19;

logic is_signed_next;
logic is_signed_pre_next;

logic [2*DataWidth-1:0] mad_full;
assign mad_full = (next_op_a_in*next_op_b_in) + next_op_c_in;

always_ff @(posedge clk) begin
    if (~rst_n) begin
        pre_nextOP               <= Add_Op;
        is_signed_pre_next <= 1'b0;
    end
    else begin
        pre_nextOP               <= pe_oper'($urandom_range(17,0));
        is_signed_pre_next <= $urandom_range(1,0);
    end
end

logic [DataWidth + 1: 0] full_sum;
assign full_sum = next_op_a_in + next_op_b_in + next_op_c_in + next_op_d_p_in;

always_ff @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        count                <= 'h0;

        next_op_a_in <= 'h0;
        next_op_b_in <= 'h0;
        next_op_c_in <= 'h0;

        next_op_d_p_in <= 'h0;

        op_a_in <= 'h0;
        op_b_in <= 'h0;
        op_c_in <= 'h0;

        op_d_p_in <= 'h0;

        op_code <= 'h0;

        exp_mult32_res <= 'h0;

        exp_res     <= 'h0;
        exp_res_p <= 'h0;

        ignore_res   <= 'h0;
        ignore_res_p <= 'h0;

        nextOP      <= Add_Op;
        currentOP <= Add_Op;

        is_signed_next <= 1'b0;

    end
    else begin
        count <= count + 1;
                

        nextOP               <= pre_nextOP;
        is_signed_next <= is_signed_pre_next;
        currentOP            <= nextOP;

        next_op_a_msb_in <= $urandom_range(2**DataWidth - 1,0);
        next_op_b_msb_in <= $urandom_range(2**DataWidth - 1,0);

        next_op_a_in <= $urandom_range(2**DataWidth - 1,0);
        next_op_b_in <= {2{16'($urandom_range(31,0))}};
        next_op_c_in <= $urandom_range(2**DataWidth - 1,0);

        next_op_d_p_in <= $urandom_range(1,0);

        op_a_msb_in <= next_op_a_msb_in;
        op_b_msb_in <= next_op_b_msb_in;

        op_a_in <= next_op_a_in;
        op_b_in <= next_op_b_in;
        op_c_in <= next_op_c_in;

        op_d_p_in <= next_op_d_p_in;

        ignore_res   <= 1'b0;
        ignore_res_p <= 1'b0;

        op_code[15:6] <= 'h0;
        op_code[6]      <= is_signed_pre_next;

        op_code[8]      <= 1'b1;


        case(pre_nextOP)
            Add_Op : begin
                op_code[5:0] <= PE_ADD_OP;
                exp_res          <= full_sum[DataWidth-1:0];
                exp_res_p        <= |full_sum[DataWidth+1:DataWidth];
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b0;
            end
            Sub_Op : begin
                op_code[5:0] <= PE_SUB_OP;
                exp_res          <= (next_op_a_in - next_op_b_in) + next_op_c_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Abs_Op : begin
                op_code[5:0] <= PE_ABS_OP;
                exp_res          <= abs(next_op_a_in - next_op_b_in) + next_op_c_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            GteMax_Op : begin
                op_code[5:0] <= PE_GTE_MAX_OP;
                if (is_signed_pre_next) begin
                    exp_res          <= ($signed(next_op_a_in) >= $signed(next_op_b_in)) ? next_op_a_in : next_op_b_in;
                    exp_res_p        <= ($signed(next_op_a_in) >= $signed(next_op_b_in));
                end else begin
                    exp_res          <= (next_op_a_in >= next_op_b_in) ? next_op_a_in : next_op_b_in;
                    exp_res_p        <= (next_op_a_in >= next_op_b_in);
                end
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b0;
            end
            LteMin_Op : begin
                op_code[5:0] <= PE_LTE_MIN_OP;
                if (is_signed_pre_next) begin
                    exp_res          <= ($signed(next_op_a_in) <= $signed(next_op_b_in)) ? next_op_a_in : next_op_b_in;
                    exp_res_p        <= ($signed(next_op_a_in) <= $signed(next_op_b_in));
                end else begin
                    exp_res          <= (next_op_a_in <= next_op_b_in) ? next_op_a_in : next_op_b_in;
                    exp_res_p        <= (next_op_a_in <= next_op_b_in);
                end
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b0;
            end
            Eq_Op : begin
                op_code[5:0] <= PE_EQ_OP;
                exp_res_p        <= (next_op_a_in === next_op_b_in);
                ignore_res   <= 1'b1;
                ignore_res_p <= 1'b0;
            end
            Sel_Op : begin
                op_code[5:0] <= PE_SEL_OP;
                exp_res          <= next_op_d_p_in ? next_op_a_in : next_op_b_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Lshft_Op : begin
                next_op_b_in <= {2{16'($urandom_range(16,0))}};
                op_code[5:0] <= PE_LSHFT_OP;
                exp_res          <= next_op_a_in << next_op_b_in[3:0];
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            RshftS_Op : begin
                next_op_b_in <= {2{16'($urandom_range(16,0))}};
                op_code[5:0] <= PE_RSHFT_S_OP;
                exp_res          <= $signed(next_op_a_in) >>> next_op_b_in[3:0];
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Rshft_Op : begin
                next_op_b_in <= {2{16'($urandom_range(16,0))}};
                op_code[5:0] <= PE_RSHFT_OP;
                exp_res          <= next_op_a_in >> next_op_b_in[3:0];
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Or_Op : begin
                op_code[5:0] <= PE_OR_OP;
                exp_res          <= next_op_a_in | next_op_b_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            And_Op : begin
                op_code[5:0] <= PE_AND_OP;
                exp_res          <= next_op_a_in & next_op_b_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Xor_Op : begin
                op_code[5:0] <= PE_XOR_OP;
                exp_res          <= next_op_a_in ^ next_op_b_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Inv_Op : begin
                op_code[5:0] <= PE_INV_OP;
                exp_res          <= ~next_op_a_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Mult0_Op : begin
                op_code[5:0] <= PE_MULT_0_OP;
                exp_res          <= (next_op_a_in*next_op_b_in) + next_op_c_in ;
                exp_mult32_res <= {next_op_a_msb_in, next_op_a_in} * {next_op_b_msb_in, next_op_b_in};
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Mult1_Op : begin
                op_code[5:0] <= PE_MULT_1_OP;
                exp_res          <= (mad_full >> (DataWidth/2));
                exp_mult32_res <= {next_op_a_msb_in, next_op_a_in} * {next_op_b_msb_in, next_op_b_in};
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Mult2_Op : begin
                op_code[5:0] <= PE_MULT_2_OP;
                exp_res          <= (mad_full >> DataWidth);
                exp_mult32_res <= {next_op_a_msb_in, next_op_a_in} * {next_op_b_msb_in, next_op_b_in};
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Cntr_Op : begin
                op_code[5:0] <= PE_CNTR_OP;
                exp_res          <= 'hX;
                ignore_res   <= 1'b1;
                ignore_res_p <= 1'b1;
                next_op_a_in <= 'h1;
                next_op_b_in <= 'h0;
                next_op_c_in <= 'h9;
            end

            Div_Op : begin
                op_code[5:0] <= PE_DIV_OP;
                exp_res          <= 'hX;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
                next_op_a_in <= 'h1234;
                next_op_b_in <= 'h56;
                next_op_c_in <= 'h0;
            end

            default: begin
                $display("Error: unexpected instruction op code: %x!\n", nextOP);
            end
        endcase
    end
end



`$dut->instantiate()` (
    .op_code (op_code[8:0]),

    .op_a (op_a_in[15:0]),
    .op_b (op_b_in[15:0]),
    .op_c (op_c_in[15:0]),

    .op_d_p (op_d_p_in),


    .cntr_en     (),


    .div_ci (),
    .div_co (),

    .res     (res[15:0]),
    .res_p (res_p)
);



function [DataWidth-1:0] abs(
    input [DataWidth-1:0] a
);
    abs = ($signed(a) < 0) ? -a : a;
endfunction

endmodule
module  `mname()`;


localparam DataWidth = 16;
localparam DataMSB   = DataWidth-1;


logic                clk;
logic                rst_n;

logic [DataMSB:0] next_op_a_msb_in;
logic [DataMSB:0] next_op_b_msb_in;


logic [DataMSB:0] next_op_a_in;
logic [DataMSB:0] next_op_b_in;
logic [DataMSB:0] next_op_c_in;

logic                           next_op_d_p_in;

logic [DataMSB:0] op_a_msb_in;
logic [DataMSB:0] op_b_msb_in;

logic [DataMSB:0] op_a_in;
logic [DataMSB:0] op_b_in;
logic [DataMSB:0] op_c_in;

logic                           op_d_p_in;

logic [DataMSB:0] res;
logic                           res_p;

logic [15:0]    op_code;

bit [31:0] count;

bit [4*DataWidth-1:0] exp_mult32_res;
bit [DataMSB:0] exp_res;
bit                         exp_res_p;

bit                         ignore_res;
bit                         ignore_res_p;


bit fail_res, fail_res_p, fail, fail_latch;


initial begin
    #1000000 $display("Time = %d clk = %b", $time, clk);


    if(fail_latch)
        $display("\nAt least one test has FAILED!\n");
    else
        $display("\nAll tests Passed\n");

     $finish;
end

initial begin
    #1 clk = 1;
    forever begin
        #5 clk = ~clk;
    end
end

initial begin
    rst_n = 0;
    repeat(10) @(posedge clk);
    rst_n = 1;
end

always_ff @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        fail_latch <= 0;
    else if(fail)
        fail_latch <= 1;
end

assign fail_res     = ~ignore_res & (exp_res !== res);
assign fail_res_p = ~ignore_res_p & (exp_res_p !== res_p);
assign fail             = fail_res | fail_res_p;


typedef enum {
Add_Op, Sub_Op, Abs_Op, GteMax_Op, LteMin_Op, Eq_Op,
Sel_Op, Rshft_Op, RshftS_Op, Lshft_Op, Mult0_Op, Mult1_Op, Mult2_Op, Or_Op,
And_Op, Xor_Op, Inv_Op, Cntr_Op, Div_Op, InvalidOp
} pe_oper;

pe_oper pre_nextOP;
pe_oper nextOP;
pe_oper currentOP;

localparam PE_ADD_OP         = 6'h0;
localparam PE_SUB_OP         = 6'h1;

localparam PE_ABS_OP         = 6'h3;

localparam PE_GTE_MAX_OP = 6'h4;
localparam PE_LTE_MIN_OP = 6'h5;
localparam PE_EQ_OP          = 6'h6;

localparam PE_SEL_OP         = 6'h8;

localparam PE_RSHFT_OP   = 6'hF;
localparam PE_RSHFT_S_OP = 6'h10;
localparam PE_LSHFT_OP   = 6'h11;

localparam PE_MULT_0_OP  = 6'hB;
localparam PE_MULT_1_OP  = 6'hC;
localparam PE_MULT_2_OP  = 6'hD;

localparam PE_OR_OP          = 6'h12;
localparam PE_AND_OP         = 6'h13;
localparam PE_XOR_OP         = 6'h14;
localparam PE_INV_OP         = 6'h15;

localparam PE_CNTR_OP        = 6'h18;

localparam PE_DIV_OP        = 6'h19;

logic is_signed_next;
logic is_signed_pre_next;

logic [2*DataWidth-1:0] mad_full;
assign mad_full = (next_op_a_in*next_op_b_in) + next_op_c_in;

always_ff @(posedge clk) begin
    if (~rst_n) begin
        pre_nextOP               <= Add_Op;
        is_signed_pre_next <= 1'b0;
    end
    else begin
        pre_nextOP               <= pe_oper'($urandom_range(17,0));
        is_signed_pre_next <= $urandom_range(1,0);
    end
end

logic [DataWidth + 1: 0] full_sum;
assign full_sum = next_op_a_in + next_op_b_in + next_op_c_in + next_op_d_p_in;

always_ff @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        count                <= 'h0;

        next_op_a_in <= 'h0;
        next_op_b_in <= 'h0;
        next_op_c_in <= 'h0;

        next_op_d_p_in <= 'h0;

        op_a_in <= 'h0;
        op_b_in <= 'h0;
        op_c_in <= 'h0;

        op_d_p_in <= 'h0;

        op_code <= 'h0;

        exp_mult32_res <= 'h0;

        exp_res     <= 'h0;
        exp_res_p <= 'h0;

        ignore_res   <= 'h0;
        ignore_res_p <= 'h0;

        nextOP      <= Add_Op;
        currentOP <= Add_Op;

        is_signed_next <= 1'b0;

    end
    else begin
        count <= count + 1;
                

        nextOP               <= pre_nextOP;
        is_signed_next <= is_signed_pre_next;
        currentOP            <= nextOP;

        next_op_a_msb_in <= $urandom_range(2**DataWidth - 1,0);
        next_op_b_msb_in <= $urandom_range(2**DataWidth - 1,0);

        next_op_a_in <= $urandom_range(2**DataWidth - 1,0);
        next_op_b_in <= {2{16'($urandom_range(31,0))}};
        next_op_c_in <= $urandom_range(2**DataWidth - 1,0);

        next_op_d_p_in <= $urandom_range(1,0);

        op_a_msb_in <= next_op_a_msb_in;
        op_b_msb_in <= next_op_b_msb_in;

        op_a_in <= next_op_a_in;
        op_b_in <= next_op_b_in;
        op_c_in <= next_op_c_in;

        op_d_p_in <= next_op_d_p_in;

        ignore_res   <= 1'b0;
        ignore_res_p <= 1'b0;

        op_code[15:6] <= 'h0;
        op_code[6]      <= is_signed_pre_next;

        op_code[8]      <= 1'b1;


        case(pre_nextOP)
            Add_Op : begin
                op_code[5:0] <= PE_ADD_OP;
                exp_res          <= full_sum[DataWidth-1:0];
                exp_res_p        <= |full_sum[DataWidth+1:DataWidth];
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b0;
            end
            Sub_Op : begin
                op_code[5:0] <= PE_SUB_OP;
                exp_res          <= (next_op_a_in - next_op_b_in) + next_op_c_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Abs_Op : begin
                op_code[5:0] <= PE_ABS_OP;
                exp_res          <= abs(next_op_a_in - next_op_b_in) + next_op_c_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            GteMax_Op : begin
                op_code[5:0] <= PE_GTE_MAX_OP;
                if (is_signed_pre_next) begin
                    exp_res          <= ($signed(next_op_a_in) >= $signed(next_op_b_in)) ? next_op_a_in : next_op_b_in;
                    exp_res_p        <= ($signed(next_op_a_in) >= $signed(next_op_b_in));
                end else begin
                    exp_res          <= (next_op_a_in >= next_op_b_in) ? next_op_a_in : next_op_b_in;
                    exp_res_p        <= (next_op_a_in >= next_op_b_in);
                end
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b0;
            end
            LteMin_Op : begin
                op_code[5:0] <= PE_LTE_MIN_OP;
                if (is_signed_pre_next) begin
                    exp_res          <= ($signed(next_op_a_in) <= $signed(next_op_b_in)) ? next_op_a_in : next_op_b_in;
                    exp_res_p        <= ($signed(next_op_a_in) <= $signed(next_op_b_in));
                end else begin
                    exp_res          <= (next_op_a_in <= next_op_b_in) ? next_op_a_in : next_op_b_in;
                    exp_res_p        <= (next_op_a_in <= next_op_b_in);
                end
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b0;
            end
            Eq_Op : begin
                op_code[5:0] <= PE_EQ_OP;
                exp_res_p        <= (next_op_a_in === next_op_b_in);
                ignore_res   <= 1'b1;
                ignore_res_p <= 1'b0;
            end
            Sel_Op : begin
                op_code[5:0] <= PE_SEL_OP;
                exp_res          <= next_op_d_p_in ? next_op_a_in : next_op_b_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Lshft_Op : begin
                next_op_b_in <= {2{16'($urandom_range(16,0))}};
                op_code[5:0] <= PE_LSHFT_OP;
                exp_res          <= next_op_a_in << next_op_b_in[3:0];
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            RshftS_Op : begin
                next_op_b_in <= {2{16'($urandom_range(16,0))}};
                op_code[5:0] <= PE_RSHFT_S_OP;
                exp_res          <= $signed(next_op_a_in) >>> next_op_b_in[3:0];
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Rshft_Op : begin
                next_op_b_in <= {2{16'($urandom_range(16,0))}};
                op_code[5:0] <= PE_RSHFT_OP;
                exp_res          <= next_op_a_in >> next_op_b_in[3:0];
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Or_Op : begin
                op_code[5:0] <= PE_OR_OP;
                exp_res          <= next_op_a_in | next_op_b_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            And_Op : begin
                op_code[5:0] <= PE_AND_OP;
                exp_res          <= next_op_a_in & next_op_b_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Xor_Op : begin
                op_code[5:0] <= PE_XOR_OP;
                exp_res          <= next_op_a_in ^ next_op_b_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Inv_Op : begin
                op_code[5:0] <= PE_INV_OP;
                exp_res          <= ~next_op_a_in;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Mult0_Op : begin
                op_code[5:0] <= PE_MULT_0_OP;
                exp_res          <= (next_op_a_in*next_op_b_in) + next_op_c_in ;
                exp_mult32_res <= {next_op_a_msb_in, next_op_a_in} * {next_op_b_msb_in, next_op_b_in};
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Mult1_Op : begin
                op_code[5:0] <= PE_MULT_1_OP;
                exp_res          <= (mad_full >> (DataWidth/2));
                exp_mult32_res <= {next_op_a_msb_in, next_op_a_in} * {next_op_b_msb_in, next_op_b_in};
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Mult2_Op : begin
                op_code[5:0] <= PE_MULT_2_OP;
                exp_res          <= (mad_full >> DataWidth);
                exp_mult32_res <= {next_op_a_msb_in, next_op_a_in} * {next_op_b_msb_in, next_op_b_in};
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
            end
            Cntr_Op : begin
                op_code[5:0] <= PE_CNTR_OP;
                exp_res          <= 'hX;
                ignore_res   <= 1'b1;
                ignore_res_p <= 1'b1;
                next_op_a_in <= 'h1;
                next_op_b_in <= 'h0;
                next_op_c_in <= 'h9;
            end

            Div_Op : begin
                op_code[5:0] <= PE_DIV_OP;
                exp_res          <= 'hX;
                ignore_res   <= 1'b0;
                ignore_res_p <= 1'b1;
                next_op_a_in <= 'h1234;
                next_op_b_in <= 'h56;
                next_op_c_in <= 'h0;
            end

            default: begin
                $display("Error: unexpected instruction op code: %x!\n", nextOP);
            end
        endcase
    end
end



`$dut->instantiate()` (
    .op_code (op_code[8:0]),

    .op_a (op_a_in[15:0]),
    .op_b (op_b_in[15:0]),
    .op_c (op_c_in[15:0]),

    .op_d_p (op_d_p_in),


    .cntr_en     (),


    .div_ci (),
    .div_co (),

    .res     (res[15:0]),
    .res_p (res_p)
);



function [DataWidth-1:0] abs(
    input [DataWidth-1:0] a
);
    abs = ($signed(a) < 0) ? -a : a;
endfunction

endmodule