data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v:1: Cannot find include file: doremi.v\n`include "doremi.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem9,data/full_repos/permissive/202237519/doremi.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem9,data/full_repos/permissive/202237519/doremi.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem9,data/full_repos/permissive/202237519/doremi.v.sv\n             doremi.v\n             doremi.v.v\n             doremi.v.sv\n             obj_dir/doremi.v\n             obj_dir/doremi.v.v\n             obj_dir/doremi.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v:9: syntax error, unexpected do, expecting IDENTIFIER\ndoremi do(reset, clk, key, piezo);\n       ^~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk <= ~clk; \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("doremi_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,doremi_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    reset = 1; clk = 0; #15;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    reset = 0; #5;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    key = 8\'b00000001; #10000;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    key = 8\'b00000100; #10000;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    key = 8\'b00010000; #10000;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    key = 8\'b01000000; #10000;\n                       ^\n%Error: Exiting due to 4 error(s), 7 warning(s)\n'
module doremi_tb;

reg [7:0]key;
reg reset,clk;
wire piezo;

doremi do(reset, clk, key, piezo);

always begin 
    #10 clk <= ~clk; 
    end

initial begin
    $dumpfile("doremi_tb.vcd");
    $dumpvars(0,doremi_tb);

    reset = 1; clk = 0; #15;
    reset = 0; #5;

    key = 8'b00000001; #10000;
    key = 8'b00000100; #10000;
    key = 8'b00010000; #10000;
    key = 8'b01000000; #10000;


    $finish;

end


endmodule
module doremi_tb;


reg [7:0]key;
reg reset,clk;
wire piezo;

doremi do(reset, clk, key, piezo);

always begin 
    #10 clk <= ~clk; 
    end

initial begin
    $dumpfile("doremi_tb.vcd");
    $dumpvars(0,doremi_tb);

    reset = 1; clk = 0; #15;
    reset = 0; #5;

    key = 8'b00000001; #10000;
    key = 8'b00000100; #10000;
    key = 8'b00010000; #10000;
    key = 8'b01000000; #10000;


    $finish;

end


endmodule