data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_reader_eof.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_reader_eof.sv:67: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module dma_reader_eof #(
  parameter DataBits      = 64,
  parameter AddrBits      = 32,
  parameter LengthBits    = 16,
  parameter BurstSize     = 16,
  parameter FifoDepth     = 128)

(
  input                       clk,
  input                       rst,

  input                       cfg_valid,
  output                      cfg_ready,
  input [AddrBits-1:0]        cfg_addr,
  input [LengthBits-1:0]      cfg_len,

  output                      dout_valid,
  input                       dout_ready,
  output [DataBits-1:0]       dout_data,
  output                      dout_eof,

  output logic                mst_arvalid,
  input                       mst_arready,
  output logic [AddrBits-1:0] mst_araddr,
  output logic [3:0]          mst_arlen,
  output [3:0]                mst_arid,
  output [2:0]                mst_arsize,
  output [1:0]                mst_arburst,
  output [1:0]                mst_arlock,

  input                       mst_rvalid,
  output                      mst_rready,
  input [3:0]                 mst_rid,
  input [DataBits-1:0]        mst_rdata,
  input [1:0]                 mst_rresp,
  input                       mst_rlast,

  output logic                done,
  output logic [1:0]          error);

`include "util.vh"

  localparam BytesPerWord = DataBits / 8;
  localparam BurstBits = $clog2(BurstSize + 1);
  localparam FifoUsedBits = $clog2(FifoDepth + 1);




  enum {Idle, PrepBurst1, PrepBurst2, PrepBurst3,
       IssueBurst, WaitPending} state;

  logic [BurstBits-1:0]    burst_cand, next_burst;
  logic [LengthBits-1:0]   remain, pending;
  logic [9:0]              until_4k;
  logic [AddrBits-1:0]     next_addr;
  logic [FifoUsedBits-1:0] fifo_used, fifo_free, fifo_required;

  always_ff @(posedge clk) begin:transacs
    reg [LengthBits-1:0] pending_next;


    pending_next = pending;


    if (mst_arready) begin
      mst_arvalid <= 0;
    end

    case (state)

      Idle:
        if (cfg_valid & cfg_len >= 1) begin
          remain    <= cfg_len;
          next_addr <= cfg_addr;
          state     <= PrepBurst1;
        end

      PrepBurst1:
        begin
          if (remain > 0) begin
            burst_cand <= min(remain, BurstSize);
            until_4k   <= (13'h1000 - next_addr[11:0]) / BytesPerWord;
            state      <= PrepBurst2;
          end else begin
            state <= WaitPending;
          end
        end

      PrepBurst2:
        begin

          next_burst <= min(burst_cand, until_4k);
          state      <= PrepBurst3;
        end

      PrepBurst3:
        begin
          fifo_required <= pending + next_burst;
          state         <= IssueBurst;
        end

      IssueBurst:
        begin
          if (fifo_free >= fifo_required) begin
            if (!mst_arvalid || mst_arready) begin
              mst_arvalid <= 1;
              mst_araddr  <= next_addr;
              mst_arlen   <= next_burst - 1;
              pending_next = pending + next_burst;
              remain      <= remain - next_burst;
              next_addr   <= next_addr + (next_burst * BytesPerWord);
              state       <= PrepBurst1;
            end
          end else begin
            fifo_required <= pending + next_burst;
          end
        end

      WaitPending:
        if (pending == 0) begin
          state    <= Idle;
        end
    endcase


    if (mst_rvalid & mst_rready) begin
      if (pending_next > 0) begin
        pending_next = pending_next - 1;
      end
      error <= mst_rresp;
    end

    pending <= pending_next;

    if (rst) begin
      state       <= Idle;
      error       <= '0;
      pending     <= '0;
      mst_arvalid <= '0;
    end

  end

  wire eof = (remain == 0 && pending == 1);

  assign done = mst_rvalid & mst_rdata & eof;
  assign cfg_ready = (state == Idle);






  stream_fifo_1clk #(
    .Width      (DataBits + 1),
    .Depth      (FifoDepth))
  fifo(
    .rst        (rst),
    .clk        (clk),

    .din_valid  (mst_rvalid),
    .din_ready  (mst_rready),
    .din_data   ({eof, mst_rdata}),

    .dout_valid (dout_valid),
    .dout_ready (dout_ready),
    .dout_data  ({dout_eof, dout_data}),
    .used       (fifo_used));

  assign fifo_free = FifoDepth - fifo_used;


  assign mst_arid    = 4'b0;
  assign mst_arsize  = clog2(DataBits/8);
  assign mst_arlock  = 2'b00;
  assign mst_arburst = 2'b01;

endmodule
module dma_reader_eof #(
  parameter DataBits      = 64,
  parameter AddrBits      = 32,
  parameter LengthBits    = 16,
  parameter BurstSize     = 16,
  parameter FifoDepth     = 128)

(
  input                       clk,
  input                       rst,

  input                       cfg_valid,
  output                      cfg_ready,
  input [AddrBits-1:0]        cfg_addr,
  input [LengthBits-1:0]      cfg_len,

  output                      dout_valid,
  input                       dout_ready,
  output [DataBits-1:0]       dout_data,
  output                      dout_eof,

  output logic                mst_arvalid,
  input                       mst_arready,
  output logic [AddrBits-1:0] mst_araddr,
  output logic [3:0]          mst_arlen,
  output [3:0]                mst_arid,
  output [2:0]                mst_arsize,
  output [1:0]                mst_arburst,
  output [1:0]                mst_arlock,

  input                       mst_rvalid,
  output                      mst_rready,
  input [3:0]                 mst_rid,
  input [DataBits-1:0]        mst_rdata,
  input [1:0]                 mst_rresp,
  input                       mst_rlast,

  output logic                done,
  output logic [1:0]          error);


`include "util.vh"

  localparam BytesPerWord = DataBits / 8;
  localparam BurstBits = $clog2(BurstSize + 1);
  localparam FifoUsedBits = $clog2(FifoDepth + 1);




  enum {Idle, PrepBurst1, PrepBurst2, PrepBurst3,
       IssueBurst, WaitPending} state;

  logic [BurstBits-1:0]    burst_cand, next_burst;
  logic [LengthBits-1:0]   remain, pending;
  logic [9:0]              until_4k;
  logic [AddrBits-1:0]     next_addr;
  logic [FifoUsedBits-1:0] fifo_used, fifo_free, fifo_required;

  always_ff @(posedge clk) begin:transacs
    reg [LengthBits-1:0] pending_next;


    pending_next = pending;


    if (mst_arready) begin
      mst_arvalid <= 0;
    end

    case (state)

      Idle:
        if (cfg_valid & cfg_len >= 1) begin
          remain    <= cfg_len;
          next_addr <= cfg_addr;
          state     <= PrepBurst1;
        end

      PrepBurst1:
        begin
          if (remain > 0) begin
            burst_cand <= min(remain, BurstSize);
            until_4k   <= (13'h1000 - next_addr[11:0]) / BytesPerWord;
            state      <= PrepBurst2;
          end else begin
            state <= WaitPending;
          end
        end

      PrepBurst2:
        begin

          next_burst <= min(burst_cand, until_4k);
          state      <= PrepBurst3;
        end

      PrepBurst3:
        begin
          fifo_required <= pending + next_burst;
          state         <= IssueBurst;
        end

      IssueBurst:
        begin
          if (fifo_free >= fifo_required) begin
            if (!mst_arvalid || mst_arready) begin
              mst_arvalid <= 1;
              mst_araddr  <= next_addr;
              mst_arlen   <= next_burst - 1;
              pending_next = pending + next_burst;
              remain      <= remain - next_burst;
              next_addr   <= next_addr + (next_burst * BytesPerWord);
              state       <= PrepBurst1;
            end
          end else begin
            fifo_required <= pending + next_burst;
          end
        end

      WaitPending:
        if (pending == 0) begin
          state    <= Idle;
        end
    endcase


    if (mst_rvalid & mst_rready) begin
      if (pending_next > 0) begin
        pending_next = pending_next - 1;
      end
      error <= mst_rresp;
    end

    pending <= pending_next;

    if (rst) begin
      state       <= Idle;
      error       <= '0;
      pending     <= '0;
      mst_arvalid <= '0;
    end

  end

  wire eof = (remain == 0 && pending == 1);

  assign done = mst_rvalid & mst_rdata & eof;
  assign cfg_ready = (state == Idle);






  stream_fifo_1clk #(
    .Width      (DataBits + 1),
    .Depth      (FifoDepth))
  fifo(
    .rst        (rst),
    .clk        (clk),

    .din_valid  (mst_rvalid),
    .din_ready  (mst_rready),
    .din_data   ({eof, mst_rdata}),

    .dout_valid (dout_valid),
    .dout_ready (dout_ready),
    .dout_data  ({dout_eof, dout_data}),
    .used       (fifo_used));

  assign fifo_free = FifoDepth - fifo_used;


  assign mst_arid    = 4'b0;
  assign mst_arsize  = clog2(DataBits/8);
  assign mst_arlock  = 2'b00;
  assign mst_arburst = 2'b01;

endmodule