data/full_repos/permissive/138243369/f1_keyproc.v
data/verilator_xmls/43bd26ed-0ba1-4584-b744-b07f9aac83aa.xml
module f1_keyproc(
input wire [3:0] func1_keys,
input wire sysclk,
output reg [2:0] color,
output reg write);

always @(posedge sysclk) begin
	if (func1_keys[0]) begin
		write <= 1'b1;

		color <= func1_keys[3:1];
	end
	else
		write <= 1'b0;
end

endmodule
module f1_keyproc(
input wire [3:0] func1_keys,
input wire sysclk,
output reg [2:0] color,
output reg write);


always @(posedge sysclk) begin
	if (func1_keys[0]) begin
		write <= 1'b1;

		color <= func1_keys[3:1];
	end
	else
		write <= 1'b0;
end

endmodule