data/full_repos/permissive/132220215/d_ff_asyn_clr.v
 line:12: before: "clr"
1: b"%Error: data/full_repos/permissive/132220215/d_ff_asyn_clr.v:10: Duplicate declaration of signal: 'Q'\n                                                               : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg Q;\n     ^\n        data/full_repos/permissive/132220215/d_ff_asyn_clr.v:8: ... Location of original declaration\n output Q);\n        ^\n%Error: Exiting due to 1 error(s)\n"
module D_FF(
	input D,
	input clk,
	input clr,
	output Q);

 reg Q;

 always @(posedge clk or clr)
	  begin
		  if(clr)
			  Q <= 1'b0;

		  else
			  Q <= D;
	  end
	  
endmodule
module D_FF(
	input D,
	input clk,
	input clr,
	output Q);


 reg Q;

 always @(posedge clk or clr)
	  begin
		  if(clr)
			  Q <= 1'b0;

		  else
			  Q <= D;
	  end
	  
endmodule