data/full_repos/permissive/165160692/04.FPGA/5932_74HC02/hdl/5932_74HC02.v
'utf-8' codec can't decode byte 0xbb in position 93: invalid start byte
data/verilator_xmls/bcc70c5b-b530-4901-b4f9-cf093a616e40.xml
module HC02(A,B,Y);
input [4:1]A,B;
output [4:1]Y;
assign Y=~(A|B);
endmodule
module HC02(A,B,Y);

input [4:1]A,B;
output [4:1]Y;
assign Y=~(A|B);
endmodule