data/full_repos/permissive/162696624/Traffic Light.v
 line:32: before: "["
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/162696624/Traffic\n        ... Looked in:\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.sv\n             data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624/Traffic.sv\n             obj_dir/data/full_repos/permissive/162696624/Traffic\n             obj_dir/data/full_repos/permissive/162696624/Traffic.v\n             obj_dir/data/full_repos/permissive/162696624/Traffic.sv\n%Error: Cannot find file containing module: Light.v\n%Error: Exiting due to 2 error(s)\n'
module test_traffic;
  reg A,B,R,AT,BT,CLK;
  wire AL,BL,finished1,finished2;
  wire[3:0] ATH;
  wire [3:0] ATL;
  traffic_light tl(A,B,R,AT,BT,CLK,ATH,ATL,AL,BL,finished1,finished2);
  initial 
  begin
    R=1;
    CLK=0;
    #15 R=0;
    repeat(4000)
    #5 CLK=~CLK;
  end
  
  initial
  begin
    A=0; B=0; AT=0; BT=0;
    #2000 AT=1; 
    #200 AT=0;
    #500 B=1;
    #200 B=0;
    #2000 BT=1;
    #1000 A=1;
    #200  A=0;
    #1000 R=1;
    #200  R=0;
    #2500 BT=0;
    #4000 AT=1;
     
    
       
  end
endmodule
module test_traffic;

  reg A,B,R,AT,BT,CLK;
  wire AL,BL,finished1,finished2;
  wire[3:0] ATH;
  wire [3:0] ATL;
  traffic_light tl(A,B,R,AT,BT,CLK,ATH,ATL,AL,BL,finished1,finished2);
  initial 
  begin
    R=1;
    CLK=0;
    #15 R=0;
    repeat(4000)
    #5 CLK=~CLK;
  end
  
  initial
  begin
    A=0; B=0; AT=0; BT=0;
    #2000 AT=1; 
    #200 AT=0;
    #500 B=1;
    #200 B=0;
    #2000 BT=1;
    #1000 A=1;
    #200  A=0;
    #1000 R=1;
    #200  R=0;
    #2500 BT=0;
    #4000 AT=1;
     
    
       
  end
endmodule