data/full_repos/permissive/193530477/source codes/F_CODE_tb.v
 line:43: before: "state"
1: b'%Error: Cannot find file containing module: codes,data/full_repos/permissive/193530477\n        ... Looked in:\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.v\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.sv\n             codes,data/full_repos/permissive/193530477\n             codes,data/full_repos/permissive/193530477.v\n             codes,data/full_repos/permissive/193530477.sv\n             obj_dir/codes,data/full_repos/permissive/193530477\n             obj_dir/codes,data/full_repos/permissive/193530477.v\n             obj_dir/codes,data/full_repos/permissive/193530477.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/193530477/source\n%Error: Cannot find file containing module: codes/F_CODE_tb.v\n%Error: Exiting due to 3 error(s)\n'
module F_CODE_tb;

reg[3:0] inx;
reg[3:0] keyvalue;
reg[3:0] state;
wire[3:0] code;
wire[10:0] tn;

wire high;
reg clk1;
reg clk2;
 
F_CODE U1(
	.INX ( inx ),
	.KEYVALUE(keyvalue),
	.STATE(state),
	.CODE ( code ),
	.H ( high ),
	.TO ( tn )
	);

initial begin
	inx = 4'b0000;
	clk1 = 1'b0;
	clk2 = 1'b0;
	state = 4'b0001;
	keyvalue = 4'b0000;
	end

always 
	#10 clk1 = ~ clk1;
always 
	#20 clk2 = ~ clk2;
	
always @ (posedge clk1)
	if (inx <= 4'b1111)  inx <= inx + 1'b1;
	else inx = 4'd0000;
	
always 
	#400 	state = 4'b0011;

always @ (posedge clk2 or state)
	if (state == 4'b0011 && keyvalue <= 4'b1111)  keyvalue <= keyvalue + 1'b1;
	else keyvalue = 4'd0000;
	
endmodule
module F_CODE_tb;


reg[3:0] inx;
reg[3:0] keyvalue;
reg[3:0] state;
wire[3:0] code;
wire[10:0] tn;

wire high;
reg clk1;
reg clk2;
 
F_CODE U1(
	.INX ( inx ),
	.KEYVALUE(keyvalue),
	.STATE(state),
	.CODE ( code ),
	.H ( high ),
	.TO ( tn )
	);

initial begin
	inx = 4'b0000;
	clk1 = 1'b0;
	clk2 = 1'b0;
	state = 4'b0001;
	keyvalue = 4'b0000;
	end

always 
	#10 clk1 = ~ clk1;
always 
	#20 clk2 = ~ clk2;
	
always @ (posedge clk1)
	if (inx <= 4'b1111)  inx <= inx + 1'b1;
	else inx = 4'd0000;
	
always 
	#400 	state = 4'b0011;

always @ (posedge clk2 or state)
	if (state == 4'b0011 && keyvalue <= 4'b1111)  keyvalue <= keyvalue + 1'b1;
	else keyvalue = 4'd0000;
	
endmodule