data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v
None: at end of input
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:10: Define or directive not defined: \'`RegDataWidth\'\n        input wire[`RegDataWidth-1:0] ex_wdata,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:11: Define or directive not defined: \'`RegAddrWidth\'\n        input wire[`RegAddrWidth-1:0] ex_wd,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:15: Define or directive not defined: \'`RegDataWidth\'\n        output reg[`RegDataWidth-1:0] mem_wdata,            \n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:16: Define or directive not defined: \'`RegAddrWidth\'\n        output reg[`RegAddrWidth-1:0] mem_wd,               \n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:22: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:22: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (rst == `RstEnable) begin\n                             ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:23: Define or directive not defined: \'`ZeroWord\'\n            mem_wdata <= `ZeroWord;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:24: Define or directive not defined: \'`ZeroRegAddr\'\n            mem_wd <= `ZeroRegAddr;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            mem_wd <= `ZeroRegAddr;\n                                  ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:25: Define or directive not defined: \'`WriteDisable\'\n            mem_wreg <= `WriteDisable;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:25: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            mem_wreg <= `WriteDisable;\n                                     ^\n%Error: Cannot continue\n'
module ex_mem(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,
        

        input wire[`RegDataWidth-1:0] ex_wdata,
        input wire[`RegAddrWidth-1:0] ex_wd,
        input wire ex_wreg,
        

        output reg[`RegDataWidth-1:0] mem_wdata,            
        output reg[`RegAddrWidth-1:0] mem_wd,               
        output reg mem_wreg                   
    );
    
    always @ (posedge clk) 
    begin
        if (rst == `RstEnable) begin
            mem_wdata <= `ZeroWord;
            mem_wd <= `ZeroRegAddr;
            mem_wreg <= `WriteDisable;
        end else if (!stall[3]) begin
            mem_wdata <= ex_wdata;
            mem_wd <= ex_wd;
            mem_wreg <= ex_wreg;
        end
    end
endmodule
module ex_mem(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,
        

        input wire[`RegDataWidth-1:0] ex_wdata,
        input wire[`RegAddrWidth-1:0] ex_wd,
        input wire ex_wreg,
        

        output reg[`RegDataWidth-1:0] mem_wdata,            
        output reg[`RegAddrWidth-1:0] mem_wd,               
        output reg mem_wreg                   
    );

    
    always @ (posedge clk) 
    begin
        if (rst == `RstEnable) begin
            mem_wdata <= `ZeroWord;
            mem_wd <= `ZeroRegAddr;
            mem_wreg <= `WriteDisable;
        end else if (!stall[3]) begin
            mem_wdata <= ex_wdata;
            mem_wd <= ex_wd;
            mem_wreg <= ex_wreg;
        end
    end
endmodule