data/full_repos/permissive/143278/ivltests/br994.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br994.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br994.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br994.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br994.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br994.v:12: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'b\' generates 7 bits.\n                                                                     : ... In instance test\n    q <= b;\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br994.v:14: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 8 bits.\n                                                                     : ... In instance test\n    q <= a;\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br994.v:22: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hbb\' generates 32 or 8 bits.\n                                                                     : ... In instance test\n  b = \'hbb;\n    ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

reg       clk;
reg       sel;
reg [7:0] a;
reg [6:0] b;
reg [5:0] q;

(* ivl_synthesis_on *)
always @(posedge clk) begin
  if (sel)
    q <= b;
  else
    q <= a;
end
(* ivl_synthesis_off *)

reg failed;

initial begin
  a = 'haa;
  b = 'hbb;
  clk = 0;
  sel = 0;
  #1 clk = 1;
  #1 clk = 0;
  $display("%h", q);
  if (q !== 6'h2a) failed = 1;
  sel = 1;
  #1 clk = 1;
  #1 clk = 0;
  $display("%h", q);
  if (q !== 6'h3b) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module test();


reg       clk;
reg       sel;
reg [7:0] a;
reg [6:0] b;
reg [5:0] q;

(* ivl_synthesis_on *)
always @(posedge clk) begin
  if (sel)
    q <= b;
  else
    q <= a;
end
(* ivl_synthesis_off *)

reg failed;

initial begin
  a = 'haa;
  b = 'hbb;
  clk = 0;
  sel = 0;
  #1 clk = 1;
  #1 clk = 0;
  $display("%h", q);
  if (q !== 6'h2a) failed = 1;
  sel = 1;
  #1 clk = 1;
  #1 clk = 0;
  $display("%h", q);
  if (q !== 6'h3b) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule