data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv
 line:52 column:28: Illegal character "'"
1: b'%Error: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:4: Cannot find include file: wb_spi_slave.sv\n`include "wb_spi_slave.sv" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/204736068/SoM/RTL/spi,data/full_repos/permissive/204736068/wb_spi_slave.sv\n             data/full_repos/permissive/204736068/SoM/RTL/spi,data/full_repos/permissive/204736068/wb_spi_slave.sv.v\n             data/full_repos/permissive/204736068/SoM/RTL/spi,data/full_repos/permissive/204736068/wb_spi_slave.sv.sv\n             wb_spi_slave.sv\n             wb_spi_slave.sv.v\n             wb_spi_slave.sv.sv\n             obj_dir/wb_spi_slave.sv\n             obj_dir/wb_spi_slave.sv.v\n             obj_dir/wb_spi_slave.sv.sv\n%Error: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:34: Cannot find include file: tb_spi_helpers.sv\n    `include "tb_spi_helpers.sv" \n             ^~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:74: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:80: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_wb_spi_slave.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:81: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:91: Unsupported: Ignoring delay on this delayed statement.\n        #100 rst = \'1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:92: Unsupported: Ignoring delay on this delayed statement.\n        #100 rst = \'0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:93: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:96: Unsupported: Ignoring delay on this delayed statement.\n        # 1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:103: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:114: Unsupported: Ignoring delay on this delayed statement.\n        #5000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:126: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/spi/tb_wb_spi_slave.sv:185: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: Exiting due to 4 error(s), 9 warning(s)\n'
module tb;
    parameter logic debug = 0; 
  
    logic                 clk = 1'b0;
    logic               rst, rst_dut;
    
    logic               i_wb_ack;
    logic [31:0]         i_wb_dat;
    logic [23:0]        o_wb_adr;
    logic               o_wb_cyc;
    logic [31:0]         o_wb_dat;
    logic               o_wb_stb;
    logic               o_wb_we;
    
    logic               spi_mosi;
    logic               spi_miso;
    logic               spi_clk;
    logic               spi_ss;

    logic tx_overrun;
    logic spi_busy;
    logic [7:0] spi_id, spi_status;
    logic spi_start;
    logic reset_out;

    logic [31:0]        recvWord;
    int                 i;

    `include "tb_spi_helpers.sv"
    
    assign #100 rst_dut = reset_out | rst;
    
    wb_spi_slave
        dut
        (
            .rst( rst_dut ),
            .sck                               (spi_clk),
            .ssn                               (spi_ss),
            .mosi                              (spi_mosi),
            .miso                              (spi_miso),
            .*
        );

    logic [31:0]         mem[10000:0];
    logic i_ack;
    assign i_wb_ack = i_ack & o_wb_stb;
    
    always @(posedge clk) begin
        i_ack <= o_wb_stb & o_wb_cyc;

        if (o_wb_cyc & o_wb_stb) begin
            if (o_wb_we) begin
                mem[o_wb_adr] <= o_wb_dat;
                if (i_wb_ack)
                    $display("%t:: WB Write: addr: 0x%x, data: 0x%x", $time, o_wb_adr, o_wb_dat);
            end else begin
                i_wb_dat <= mem[o_wb_adr];
                if (i_wb_ack)
                    $display("%t:: WB Read: addr: 0x%x, data: 0x%x", $time, o_wb_adr, mem[o_wb_adr]);
            end
        end
        
    end

    always @(posedge reset_out)
        $display("%t::: Got a reset!", $time);
        

    always #10 clk = ~clk;
    logic [23:0] exp_addr;
    logic [31:0] temp, temp1, temp2;

    initial begin
        $display("Starting simulation");
        $dumpfile("tb_wb_spi_slave.vcd");
        $dumpvars;


        
        spi_ss = '1;
        spi_mosi = '0;
        spi_clk = '0;
        spi_id = 'hde;
        spi_status = 'had;
        
        #100 rst = '1;
        #100 rst = '0;
        #100;
        
        spiWriteReg('hdeadbabe, 'hfeedf00d);
        # 1000;

        spiWriteStart('hff);
        for (int i=0; i<10; i++)
            spiWriteWord('hdeadbeef+i);
        spiWriteEnd();

        #1000;
    

        spiWriteReg('h7fe, 'hfeedf00d);
        spiReadReg('h7fe, temp);
        $display("Read back: 0x%x", temp);

                

        for (int i=0; i<4; i++)
            spiWriteReg('h100+i, 'h12345678+4*i);
        #5000;
        for (int i=0; i<4; i++) begin
            spiReadReg('h100+i, temp);
            $display("Read back: 0x%x", temp);
        end
        

        spiWriteStart('hfe);
        for (int i=0; i<10; i++)
            spiWriteWord('h12345678+i);
        spiWriteEnd();
        
        #1000;
        spiReadStart('hfe);
        for (int i=0; i<4; i++) begin
            spiReadWord(temp);
            $display("Read back: 0x%x", temp);
        end
        spiReadEnd();


        for (int i=0; i<10; i++) begin
            spiGetStatus(temp);
            $display("Status: 0x%x", temp);
            spi_id = spi_id + 'd1;
            spi_status = spi_status - 'd1;
        end
        

        $display("Expect a reset now");
        spiSendReset();
        

        
        #10000;
        $display("Finishing simulation");
        $finish;
        
    end
    
    
endmodule
module tb;

    parameter logic debug = 0; 
  
    logic                 clk = 1'b0;
    logic               rst, rst_dut;
    
    logic               i_wb_ack;
    logic [31:0]         i_wb_dat;
    logic [23:0]        o_wb_adr;
    logic               o_wb_cyc;
    logic [31:0]         o_wb_dat;
    logic               o_wb_stb;
    logic               o_wb_we;
    
    logic               spi_mosi;
    logic               spi_miso;
    logic               spi_clk;
    logic               spi_ss;

    logic tx_overrun;
    logic spi_busy;
    logic [7:0] spi_id, spi_status;
    logic spi_start;
    logic reset_out;

    logic [31:0]        recvWord;
    int                 i;

    `include "tb_spi_helpers.sv"
    
    assign #100 rst_dut = reset_out | rst;
    
    wb_spi_slave
        dut
        (
            .rst( rst_dut ),
            .sck                               (spi_clk),
            .ssn                               (spi_ss),
            .mosi                              (spi_mosi),
            .miso                              (spi_miso),
            .*
        );

    logic [31:0]         mem[10000:0];
    logic i_ack;
    assign i_wb_ack = i_ack & o_wb_stb;
    
    always @(posedge clk) begin
        i_ack <= o_wb_stb & o_wb_cyc;

        if (o_wb_cyc & o_wb_stb) begin
            if (o_wb_we) begin
                mem[o_wb_adr] <= o_wb_dat;
                if (i_wb_ack)
                    $display("%t:: WB Write: addr: 0x%x, data: 0x%x", $time, o_wb_adr, o_wb_dat);
            end else begin
                i_wb_dat <= mem[o_wb_adr];
                if (i_wb_ack)
                    $display("%t:: WB Read: addr: 0x%x, data: 0x%x", $time, o_wb_adr, mem[o_wb_adr]);
            end
        end
        
    end

    always @(posedge reset_out)
        $display("%t::: Got a reset!", $time);
        

    always #10 clk = ~clk;
    logic [23:0] exp_addr;
    logic [31:0] temp, temp1, temp2;

    initial begin
        $display("Starting simulation");
        $dumpfile("tb_wb_spi_slave.vcd");
        $dumpvars;


        
        spi_ss = '1;
        spi_mosi = '0;
        spi_clk = '0;
        spi_id = 'hde;
        spi_status = 'had;
        
        #100 rst = '1;
        #100 rst = '0;
        #100;
        
        spiWriteReg('hdeadbabe, 'hfeedf00d);
        # 1000;

        spiWriteStart('hff);
        for (int i=0; i<10; i++)
            spiWriteWord('hdeadbeef+i);
        spiWriteEnd();

        #1000;
    

        spiWriteReg('h7fe, 'hfeedf00d);
        spiReadReg('h7fe, temp);
        $display("Read back: 0x%x", temp);

                

        for (int i=0; i<4; i++)
            spiWriteReg('h100+i, 'h12345678+4*i);
        #5000;
        for (int i=0; i<4; i++) begin
            spiReadReg('h100+i, temp);
            $display("Read back: 0x%x", temp);
        end
        

        spiWriteStart('hfe);
        for (int i=0; i<10; i++)
            spiWriteWord('h12345678+i);
        spiWriteEnd();
        
        #1000;
        spiReadStart('hfe);
        for (int i=0; i<4; i++) begin
            spiReadWord(temp);
            $display("Read back: 0x%x", temp);
        end
        spiReadEnd();


        for (int i=0; i<10; i++) begin
            spiGetStatus(temp);
            $display("Status: 0x%x", temp);
            spi_id = spi_id + 'd1;
            spi_status = spi_status - 'd1;
        end
        

        $display("Expect a reset now");
        spiSendReset();
        

        
        #10000;
        $display("Finishing simulation");
        $finish;
        
    end
    
    
endmodule