data/full_repos/permissive/213361049/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/213361049/alu.v:17: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                             : ... In instance alu\n   4\'b0111 : begin op = a && b;end\n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/213361049/alu.v:17: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'b\' generates 8 bits.\n                                                             : ... In instance alu\n   4\'b0111 : begin op = a && b;end\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/213361049/alu.v:17: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s LOGAND generates 1 bits.\n                                                             : ... In instance alu\n   4\'b0111 : begin op = a && b;end\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/213361049/alu.v:18: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                             : ... In instance alu\n   4\'b1000 : begin op = a || b;end\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/213361049/alu.v:18: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s VARREF \'b\' generates 8 bits.\n                                                             : ... In instance alu\n   4\'b1000 : begin op = a || b;end\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/213361049/alu.v:18: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s LOGOR generates 1 bits.\n                                                             : ... In instance alu\n   4\'b1000 : begin op = a || b;end\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/213361049/alu.v:21: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                             : ... In instance alu\n   4\'b1011 : begin op = ! a;   end\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/213361049/alu.v:21: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s LOGNOT generates 1 bits.\n                                                             : ... In instance alu\n   4\'b1011 : begin op = ! a;   end\n                      ^\n%Error: Exiting due to 8 warning(s)\n'
module alu (a,b,op,opcode);

  output reg [7:0] op;     
   input [7:0]     a,b;    
   input [3:0] opcode;    
   
always @(*)
begin
 case (opcode)
   4'b0000 : begin op = a + b; end
   4'b0001 : begin op = a - b; end
   4'b0010 : begin op = a * b; end
   4'b0011 : begin op = a / b; end
   4'b0100 : begin op = a % b; end
   4'b0101 : begin op = a & b; end
   4'b0110 : begin op = a | b; end
   4'b0111 : begin op = a && b;end
   4'b1000 : begin op = a || b;end
   4'b1001 : begin op = a ^ b; end
   4'b1010 : begin op = ~ a;   end
   4'b1011 : begin op = ! a;   end
   4'b1100 : begin op = a >> 1;end
   4'b1101 : begin op = a << 1;end
   4'b1110 : begin op = a + 1; end
   4'b1111 : begin op = a - 1; end
   default:op = 8'bXXXXXXXX;
 endcase
end

endmodule
module alu (a,b,op,opcode);


  output reg [7:0] op;     
   input [7:0]     a,b;    
   input [3:0] opcode;    
   
always @(*)
begin
 case (opcode)
   4'b0000 : begin op = a + b; end
   4'b0001 : begin op = a - b; end
   4'b0010 : begin op = a * b; end
   4'b0011 : begin op = a / b; end
   4'b0100 : begin op = a % b; end
   4'b0101 : begin op = a & b; end
   4'b0110 : begin op = a | b; end
   4'b0111 : begin op = a && b;end
   4'b1000 : begin op = a || b;end
   4'b1001 : begin op = a ^ b; end
   4'b1010 : begin op = ~ a;   end
   4'b1011 : begin op = ! a;   end
   4'b1100 : begin op = a >> 1;end
   4'b1101 : begin op = a << 1;end
   4'b1110 : begin op = a + 1; end
   4'b1111 : begin op = a - 1; end
   default:op = 8'bXXXXXXXX;
 endcase
end

endmodule