data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v
'utf-8' codec can't decode byte 0xb5 in position 19: invalid start byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:17: Unsupported: Ignoring delay on this delayed statement.\n #20 \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:20: Unsupported: Ignoring delay on this delayed statement.\n #20 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:23: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:27: Unsupported: Ignoring delay on this delayed statement.\n #20 IAGB=0;IASB=0;IAEB=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:28: Unsupported: Ignoring delay on this delayed statement.\n #20 IAGB=1;IASB=0;IAEB=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:29: Unsupported: Ignoring delay on this delayed statement.\n #20 IAGB=1;IASB=0;IAEB=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:31: Unsupported: Ignoring delay on this delayed statement.\n #20 IAGB=0;IASB=1;IAEB=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20 IAGB=0;IASB=1;IAEB=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:33: Unsupported: Ignoring delay on this delayed statement.\n #20 IAGB=1;IASB=1;IAEB=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:34: Unsupported: Ignoring delay on this delayed statement.\n #20 IAGB=1;IASB=1;IAEB=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:37: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:40: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus/testbench85.v:12: Cannot find file containing module: \'HC85\'\nHC85 u1(A,B,QAGB,QASB,QAEB,IAGB,IASB,IAEB);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus,data/full_repos/permissive/165160692/HC85\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus,data/full_repos/permissive/165160692/HC85.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC85/stimulus,data/full_repos/permissive/165160692/HC85.sv\n             HC85\n             HC85.v\n             HC85.sv\n             obj_dir/HC85\n             obj_dir/HC85.v\n             obj_dir/HC85.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
reg[3:0]A,B;
reg IAGB,IASB,IAEB;
wire QAGB,QASB,QAEB;


HC85 u1(A,B,QAGB,QASB,QAEB,IAGB,IASB,IAEB);
initial
 begin
 A=0;B=0;
 IAGB=1;IASB=1;IAEB=1;
 #20 
  A=3;B=1;
 
 #20 
  A=1;B=2;

 #20
  A=0;B=0;
  IAGB=0;IASB=0;IAEB=0;
 
 #20 IAGB=0;IASB=0;IAEB=1;
 #20 IAGB=1;IASB=0;IAEB=0;
 #20 IAGB=1;IASB=0;IAEB=1;
 
 #20 IAGB=0;IASB=1;IAEB=0;
 #20 IAGB=0;IASB=1;IAEB=1;
 #20 IAGB=1;IASB=1;IAEB=0;
 #20 IAGB=1;IASB=1;IAEB=1;


 #20
  A=5;B=9;
 
 #20
  A=3;B=2;
 
 end
endmodule
module testbench();

reg[3:0]A,B;
reg IAGB,IASB,IAEB;
wire QAGB,QASB,QAEB;


HC85 u1(A,B,QAGB,QASB,QAEB,IAGB,IASB,IAEB);
initial
 begin
 A=0;B=0;
 IAGB=1;IASB=1;IAEB=1;
 #20 
  A=3;B=1;
 
 #20 
  A=1;B=2;

 #20
  A=0;B=0;
  IAGB=0;IASB=0;IAEB=0;
 
 #20 IAGB=0;IASB=0;IAEB=1;
 #20 IAGB=1;IASB=0;IAEB=0;
 #20 IAGB=1;IASB=0;IAEB=1;
 
 #20 IAGB=0;IASB=1;IAEB=0;
 #20 IAGB=0;IASB=1;IAEB=1;
 #20 IAGB=1;IASB=1;IAEB=0;
 #20 IAGB=1;IASB=1;IAEB=1;


 #20
  A=5;B=9;
 
 #20
  A=3;B=2;
 
 end
endmodule