data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:89: Define or directive not defined: '`OPENFLOW_NEXT_TABLE_ID_WIDTH'\n   reg [`OPENFLOW_NEXT_TABLE_ID_WIDTH-1:0]    pkt_dst_table_id;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:100: Define or directive not defined: '`OPENFLOW_ENTRY_SRC_PORT_POS'\n           flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS +: `OPENFLOW_ENTRY_SRC_PORT_WIDTH];\n                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:100: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n           flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS +: `OPENFLOW_ENTRY_SRC_PORT_WIDTH];\n                                                                          ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:100: Define or directive not defined: '`OPENFLOW_ENTRY_SRC_PORT_WIDTH'\n           flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS +: `OPENFLOW_ENTRY_SRC_PORT_WIDTH];\n                                                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:101: Define or directive not defined: '`OPENFLOW_ENTRY_ETH_DST_POS'\n           flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_DST_POS +:`OPENFLOW_ENTRY_ETH_DST_WIDTH];\n                                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:101: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n           flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_DST_POS +:`OPENFLOW_ENTRY_ETH_DST_WIDTH];\n                                                                          ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:101: Define or directive not defined: '`OPENFLOW_ENTRY_ETH_DST_WIDTH'\n           flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_DST_POS +:`OPENFLOW_ENTRY_ETH_DST_WIDTH];\n                                                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:104: Define or directive not defined: '`OPENFLOW_ENTRY_TRANSP_SRC_POS'\n           flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS +:`OPENFLOW_ENTRY_TRANSP_SRC_WIDTH];\n                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:104: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n           flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS +:`OPENFLOW_ENTRY_TRANSP_SRC_WIDTH];\n                                                                            ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:104: Define or directive not defined: '`OPENFLOW_ENTRY_TRANSP_SRC_WIDTH'\n           flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS +:`OPENFLOW_ENTRY_TRANSP_SRC_WIDTH];\n                                                                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:105: Define or directive not defined: '`OPENFLOW_ENTRY_TRANSP_DST_POS'\n           flow_entry[31:16] = flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS +:`OPENFLOW_ENTRY_TRANSP_DST_WIDTH];         \n                                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:105: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n           flow_entry[31:16] = flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS +:`OPENFLOW_ENTRY_TRANSP_DST_WIDTH];         \n                                                                             ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:105: Define or directive not defined: '`OPENFLOW_ENTRY_TRANSP_DST_WIDTH'\n           flow_entry[31:16] = flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS +:`OPENFLOW_ENTRY_TRANSP_DST_WIDTH];         \n                                                                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:106: Define or directive not defined: '`OPENFLOW_ENTRY_IP_DST_POS'\n           flow_entry[63:32] = flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS +:`OPENFLOW_ENTRY_IP_DST_WIDTH];\n                                              ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:106: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n           flow_entry[63:32] = flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS +:`OPENFLOW_ENTRY_IP_DST_WIDTH];\n                                                                         ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:106: Define or directive not defined: '`OPENFLOW_ENTRY_IP_DST_WIDTH'\n           flow_entry[63:32] = flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS +:`OPENFLOW_ENTRY_IP_DST_WIDTH];\n                                                                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:109: Define or directive not defined: '`OPENFLOW_ENTRY_ETH_TYPE_POS'\n           flow_entry[15:0]= flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS+:`OPENFLOW_ENTRY_ETH_TYPE_WIDTH];      \n                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:109: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n           flow_entry[15:0]= flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS+:`OPENFLOW_ENTRY_ETH_TYPE_WIDTH];      \n                                                                        ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:109: Define or directive not defined: '`OPENFLOW_ENTRY_ETH_TYPE_WIDTH'\n           flow_entry[15:0]= flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS+:`OPENFLOW_ENTRY_ETH_TYPE_WIDTH];      \n                                                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:110: Define or directive not defined: '`OPENFLOW_ENTRY_ETH_SRC_POS'\n           flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS+:`OPENFLOW_ENTRY_ETH_SRC_WIDTH];\n                                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:110: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n           flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS+:`OPENFLOW_ENTRY_ETH_SRC_WIDTH];\n                                                                         ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:110: Define or directive not defined: '`OPENFLOW_ENTRY_ETH_SRC_WIDTH'\n           flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS+:`OPENFLOW_ENTRY_ETH_SRC_WIDTH];\n                                                                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:113: Define or directive not defined: '`OPENFLOW_ENTRY_VLAN_ID_POS'\n          flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_VLAN_ID_POS +: `OPENFLOW_ENTRY_VLAN_ID_WIDTH];\n                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:113: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n          flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_VLAN_ID_POS +: `OPENFLOW_ENTRY_VLAN_ID_WIDTH];\n                                                                        ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:113: Define or directive not defined: '`OPENFLOW_ENTRY_VLAN_ID_WIDTH'\n          flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_VLAN_ID_POS +: `OPENFLOW_ENTRY_VLAN_ID_WIDTH];\n                                                                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:114: Define or directive not defined: '`OPENFLOW_ENTRY_ETH_SRC_POS'\n          flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS +:`OPENFLOW_ENTRY_ETH_SRC_WIDTH];\n                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:114: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n          flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS +:`OPENFLOW_ENTRY_ETH_SRC_WIDTH];\n                                                                         ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:114: Define or directive not defined: '`OPENFLOW_ENTRY_ETH_SRC_WIDTH'\n          flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS +:`OPENFLOW_ENTRY_ETH_SRC_WIDTH];\n                                                                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:117: Define or directive not defined: '`OPENFLOW_ENTRY_IP_PROTO_POS'\n         flow_entry[7:0]   = flow_entry_all[`OPENFLOW_ENTRY_IP_PROTO_POS +: `OPENFLOW_ENTRY_IP_PROTO_WIDTH];\n                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:117: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n         flow_entry[7:0]   = flow_entry_all[`OPENFLOW_ENTRY_IP_PROTO_POS +: `OPENFLOW_ENTRY_IP_PROTO_WIDTH];\n                                                                         ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:117: Define or directive not defined: '`OPENFLOW_ENTRY_IP_PROTO_WIDTH'\n         flow_entry[7:0]   = flow_entry_all[`OPENFLOW_ENTRY_IP_PROTO_POS +: `OPENFLOW_ENTRY_IP_PROTO_WIDTH];\n                                                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:118: Define or directive not defined: '`OPENFLOW_ENTRY_IP_TOS_POS'\n         flow_entry[15:8]  = flow_entry_all[`OPENFLOW_ENTRY_IP_TOS_POS +: `OPENFLOW_ENTRY_IP_TOS_WIDTH];\n                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:118: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n         flow_entry[15:8]  = flow_entry_all[`OPENFLOW_ENTRY_IP_TOS_POS +: `OPENFLOW_ENTRY_IP_TOS_WIDTH];\n                                                                       ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:118: Define or directive not defined: '`OPENFLOW_ENTRY_IP_TOS_WIDTH'\n         flow_entry[15:8]  = flow_entry_all[`OPENFLOW_ENTRY_IP_TOS_POS +: `OPENFLOW_ENTRY_IP_TOS_WIDTH];\n                                                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:119: Define or directive not defined: '`OPENFLOW_ENTRY_ETH_TYPE_POS'\n         flow_entry[31:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS+:`OPENFLOW_ENTRY_ETH_TYPE_WIDTH];\n                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:119: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n         flow_entry[31:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS+:`OPENFLOW_ENTRY_ETH_TYPE_WIDTH];\n                                                                        ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:119: Define or directive not defined: '`OPENFLOW_ENTRY_ETH_TYPE_WIDTH'\n         flow_entry[31:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS+:`OPENFLOW_ENTRY_ETH_TYPE_WIDTH];\n                                                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:120: Define or directive not defined: '`OPENFLOW_ENTRY_IP_SRC_POS'\n         flow_entry[63:32] = flow_entry_all[`OPENFLOW_ENTRY_IP_SRC_POS +:`OPENFLOW_ENTRY_IP_SRC_WIDTH];        \n                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:120: syntax error, unexpected +:, expecting TYPE-IDENTIFIER\n         flow_entry[63:32] = flow_entry_all[`OPENFLOW_ENTRY_IP_SRC_POS +:`OPENFLOW_ENTRY_IP_SRC_WIDTH];        \n                                                                       ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:120: Define or directive not defined: '`OPENFLOW_ENTRY_IP_SRC_WIDTH'\n         flow_entry[63:32] = flow_entry_all[`OPENFLOW_ENTRY_IP_SRC_POS +:`OPENFLOW_ENTRY_IP_SRC_WIDTH];        \n                                                                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:128: Define or directive not defined: '`LOG2_FUNC'\n   `LOG2_FUNC\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:195: Define or directive not defined: '`VLAN_CTRL_WORD'\n                     is_vlan <= (in_ctrl==`VLAN_CTRL_WORD);\n                                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:195: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n                     is_vlan <= (in_ctrl==`VLAN_CTRL_WORD);\n                                                         ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:197: Define or directive not defined: '`METEDATA_NUM'\n                  else if(in_ctrl==`METEDATA_NUM)\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:197: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n                  else if(in_ctrl==`METEDATA_NUM)\n                                                ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:200: Define or directive not defined: '`IO_QUEUE_STAGE_NUM'\n                  else if(in_ctrl==`IO_QUEUE_STAGE_NUM) begin\n                                   ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:201: Define or directive not defined: '`OPENFLOW_ENTRY_SRC_PORT_POS'\n                     flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1 : `OPENFLOW_ENTRY_SRC_PORT_POS]\n                                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:201: Define or directive not defined: '`OPENFLOW_ENTRY_SRC_PORT_WIDTH'\n                     flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1 : `OPENFLOW_ENTRY_SRC_PORT_POS]\n                                                                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:201: Define or directive not defined: '`OPENFLOW_ENTRY_SRC_PORT_POS'\n                     flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1 : `OPENFLOW_ENTRY_SRC_PORT_POS]\n                                                                                                        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v:202: Define or directive not defined: '`IOQ_SRC_PORT_POS'\n                                                          <= in_data[`IOQ_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1 : `IOQ_SRC_PORT_POS];\n                                                                     ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module header_parser
    #(parameter DATA_WIDTH = 64,
      parameter CTRL_WIDTH = DATA_WIDTH/8,
      parameter PKT_SIZE_WIDTH = 12,
      parameter ADDITIONAL_WORD_SIZE = 16,
      parameter ADDITIONAL_WORD_BITMASK = 16'h0fff,
      parameter ADDITIONAL_WORD_POS  = 224,
      parameter ADDITIONAL_WORD_CTRL = 8'h40,
      parameter ADDITIONAL_WORD_DEFAULT = 16'hffff,
      parameter FLOW_ENTRY_SIZE_ALL = 240,
      parameter OPENFLOW_ENTRY_WIDTH = 64,
      parameter CURRENT_TABLE_ID = 0
      )
   (
    input  [DATA_WIDTH-1:0]                in_data,
    input  [CTRL_WIDTH-1:0]                in_ctrl,
    input                                  in_wr,


    output reg[OPENFLOW_ENTRY_WIDTH-1:0]           flow_entry,

    output reg [PKT_SIZE_WIDTH-1:0]        pkt_size,
    output reg                             flow_entry_vld,
    
    input[7:0]                             head_combine,
    
    output                                  skip_lookup,


    input                                  reset,
    input                                  clk
   );
   reg [`OPENFLOW_NEXT_TABLE_ID_WIDTH-1:0]    pkt_dst_table_id;
   assign skip_lookup=(pkt_dst_table_id>CURRENT_TABLE_ID)?1:0;


   reg [FLOW_ENTRY_SIZE_ALL-1:0]           flow_entry_all;
      reg[7:0]                             metadata;
    
   always@(*)
    begin
        flow_entry[95:64]={24'h0,metadata};
        if(head_combine == 0)begin
           flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS +: `OPENFLOW_ENTRY_SRC_PORT_WIDTH];
           flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_DST_POS +:`OPENFLOW_ENTRY_ETH_DST_WIDTH];
        end
        else if(head_combine == 1)begin
           flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS +:`OPENFLOW_ENTRY_TRANSP_SRC_WIDTH];
           flow_entry[31:16] = flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS +:`OPENFLOW_ENTRY_TRANSP_DST_WIDTH];         
           flow_entry[63:32] = flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS +:`OPENFLOW_ENTRY_IP_DST_WIDTH];
        end
        else if(head_combine == 2)begin
           flow_entry[15:0]= flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS+:`OPENFLOW_ENTRY_ETH_TYPE_WIDTH];      
           flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS+:`OPENFLOW_ENTRY_ETH_SRC_WIDTH];
        end     
      else if(head_combine == 3)begin
          flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_VLAN_ID_POS +: `OPENFLOW_ENTRY_VLAN_ID_WIDTH];
          flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS +:`OPENFLOW_ENTRY_ETH_SRC_WIDTH];
      end  
      else if(head_combine == 4)begin
         flow_entry[7:0]   = flow_entry_all[`OPENFLOW_ENTRY_IP_PROTO_POS +: `OPENFLOW_ENTRY_IP_PROTO_WIDTH];
         flow_entry[15:8]  = flow_entry_all[`OPENFLOW_ENTRY_IP_TOS_POS +: `OPENFLOW_ENTRY_IP_TOS_WIDTH];
         flow_entry[31:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS+:`OPENFLOW_ENTRY_ETH_TYPE_WIDTH];
         flow_entry[63:32] = flow_entry_all[`OPENFLOW_ENTRY_IP_SRC_POS +:`OPENFLOW_ENTRY_IP_SRC_WIDTH];        
      end
      else begin
          flow_entry[15:0] =  0  ;
          flow_entry[63:16] = 0  ;
      end
    end

   `LOG2_FUNC


   localparam MODULE_HDRS                   = 0;
   localparam PKT_WORDS                     = 1;
   localparam WAIT_EOP                      = 2;
   localparam RESET_FLOW_ENTRY              = 3;

   localparam MAC_SRC_LO_ETHERTYPE_WORD     = 1,
              IP_PROT_WORD                  = 2,
              IP_SRC_DST_HI_WORD            = 3,
              IP_DST_LO_TRANSP_PORTS_WORD   = 4,
              ARP_DST_HI_WORD               = 5,
              ARP_DST_LO_WORD               = 6;


   reg [1:0]                            state;
   reg [2:0]                            counter;

   reg                                  is_ip;
   reg                                  is_tcp_udp;
   reg                                  is_icmp;
   reg                                  is_vlan;
   reg                                  is_arp;


   reg [3:0]                            ip_hdr_len;

   wire [FLOW_ENTRY_SIZE_ALL-1:0]       flow_entry_default;
   


   generate
      if(FLOW_ENTRY_SIZE_ALL > ADDITIONAL_WORD_POS+ADDITIONAL_WORD_SIZE) begin:gen_flow_msb
         assign flow_entry_default[FLOW_ENTRY_SIZE_ALL-1:ADDITIONAL_WORD_POS+ADDITIONAL_WORD_SIZE]     = 0;
      end
   endgenerate
   assign flow_entry_default[ADDITIONAL_WORD_POS+ADDITIONAL_WORD_SIZE-1:ADDITIONAL_WORD_POS] = ADDITIONAL_WORD_DEFAULT;
   assign flow_entry_default[ADDITIONAL_WORD_POS-1:0]                                        = 0;


   always @(posedge clk) begin
      if(reset) begin
         counter           <= 0;
         flow_entry_vld    <= 0;
         flow_entry_all        <= flow_entry_default;
         pkt_size          <= 0;
         state             <= MODULE_HDRS;
         is_ip             <= 0;
         is_tcp_udp        <= 0;
         is_icmp           <= 0;
         is_vlan           <= 0;
         ip_hdr_len        <= 0;
         metadata          <= 0;
      end

      else begin
         flow_entry_vld    <= 0;
         case (state)
            RESET_FLOW_ENTRY: begin
               flow_entry_all    <= flow_entry_default;
               state         <= MODULE_HDRS;
               if(in_wr) begin

                  if(in_ctrl==ADDITIONAL_WORD_CTRL) begin
                     flow_entry_all[ADDITIONAL_WORD_POS + ADDITIONAL_WORD_SIZE - 1 : ADDITIONAL_WORD_POS]
                                                      <= in_data[ADDITIONAL_WORD_SIZE-1 : 0] & ADDITIONAL_WORD_BITMASK;
                     is_vlan <= (in_ctrl==`VLAN_CTRL_WORD);
                  end
                  else if(in_ctrl==`METEDATA_NUM)
                    metadata=in_data[7:0];

                  else if(in_ctrl==`IO_QUEUE_STAGE_NUM) begin
                     flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1 : `OPENFLOW_ENTRY_SRC_PORT_POS]
                                                          <= in_data[`IOQ_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1 : `IOQ_SRC_PORT_POS];
                     pkt_dst_table_id=in_data[`IOQ_DST_TABLE_ID_POS +: `IOQ_DST_TABLE_ID_LEN];                                     
                     if(is_vlan) begin
                        pkt_size <= (in_data[`IOQ_BYTE_LEN_POS + PKT_SIZE_WIDTH - 1:`IOQ_BYTE_LEN_POS] + 4);
                     end
                     else begin
                        pkt_size <= in_data[`IOQ_BYTE_LEN_POS + PKT_SIZE_WIDTH - 1:`IOQ_BYTE_LEN_POS];
                     end
                     is_vlan <= 0;
                  end


                  else if(in_ctrl==0) begin
                     $display("%t %m ERROR: found ctrl=0 as first word of pkt.", $time);
                     $stop;
                  end

               end
            end

            MODULE_HDRS: begin
               if(in_wr) begin

                  if(in_ctrl==ADDITIONAL_WORD_CTRL) begin
                     flow_entry_all[ADDITIONAL_WORD_POS + ADDITIONAL_WORD_SIZE - 1 : ADDITIONAL_WORD_POS]
                                                      <= in_data[ADDITIONAL_WORD_SIZE-1 : 0] & ADDITIONAL_WORD_BITMASK;
                            
                     is_vlan <= (in_ctrl==`VLAN_CTRL_WORD);
                  end

                  else if(in_ctrl==`VLAN_CTRL_WORD)
                     flow_entry_all[`OPENFLOW_SET_VLAN_VID_POS+`OPENFLOW_SET_VLAN_VID_WIDTH-1:`OPENFLOW_SET_VLAN_VID_POS] <= in_data [15:0];                  
                  else if(in_ctrl==`METEDATA_NUM)
                    metadata=in_data[7:0];
                  else if(in_ctrl==`IO_QUEUE_STAGE_NUM) begin
                     flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1:`OPENFLOW_ENTRY_SRC_PORT_POS]
                                                          <= in_data[`IOQ_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1:`IOQ_SRC_PORT_POS];
                     pkt_dst_table_id=in_data[`IOQ_DST_TABLE_ID_POS +: `IOQ_DST_TABLE_ID_LEN];                                      
                     if(is_vlan) begin
                        pkt_size <= (in_data[`IOQ_BYTE_LEN_POS + PKT_SIZE_WIDTH - 1:`IOQ_BYTE_LEN_POS] + 4);
                     end
                     else begin
                        pkt_size <= in_data[`IOQ_BYTE_LEN_POS + PKT_SIZE_WIDTH - 1:`IOQ_BYTE_LEN_POS];
                     end
                     is_vlan <= 0;
                  end

                  else if(in_ctrl==0) begin
                     flow_entry_all[`OPENFLOW_ENTRY_ETH_DST_POS + 47 : `OPENFLOW_ENTRY_ETH_DST_POS]
                                        <= in_data[63:16];

                     flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS + 47 : `OPENFLOW_ENTRY_ETH_SRC_POS + 32]
                                        <= in_data[15:0];
                     state    <= PKT_WORDS;
                  end
                  counter <= 1;
               end
            end

            PKT_WORDS: begin
               if(in_wr) begin
                  if(in_ctrl!=0)
                  begin
                     flow_entry_vld    <= 1'b1;
                     state             <= MODULE_HDRS;
                     flow_entry_all        <= flow_entry_default;
                     pkt_size          <= 0;
                  end
                  else begin
                  counter <= counter + 1;

                  case(counter)
                     MAC_SRC_LO_ETHERTYPE_WORD: begin
                        flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS + 31 : `OPENFLOW_ENTRY_ETH_SRC_POS] <= in_data[63:32];
                        flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS + 15 : `OPENFLOW_ENTRY_ETH_TYPE_POS] <= in_data[31:16];
                        if (in_data[31:16] == `ETH_TYPE_IP) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_TOS_POS + 7 : `OPENFLOW_ENTRY_IP_TOS_POS ]<= in_data[7:2];
                        end
                        is_ip      <= in_data[31:16] == `ETH_TYPE_IP;
                        is_arp     <= in_data[31:16] == `ETH_TYPE_ARP;
                        ip_hdr_len <= in_data[11:8];
                     end

                     IP_PROT_WORD: begin
                        if(is_ip) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_PROTO_POS + 7 : `OPENFLOW_ENTRY_IP_PROTO_POS] <= in_data[7:0];

                           if(ip_hdr_len < 5) begin
                              flow_entry_all        <= flow_entry_default;
                              flow_entry_vld    <= 1'b1;
                              state             <= WAIT_EOP;
                           end
                        end
                        else if(is_arp) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_PROTO_POS + 7 : `OPENFLOW_ENTRY_IP_PROTO_POS] <= in_data[23:16];
                        end
                        is_tcp_udp <= is_ip && ((in_data[7:0] == `IP_PROTO_TCP)
                                                || (in_data[7:0] == `IP_PROTO_UDP));
                        is_icmp    <= is_ip && (in_data[7:0] == `IP_PROTO_ICMP);
                     end

                     IP_SRC_DST_HI_WORD: begin
                        if(is_ip) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_SRC_POS + 31:`OPENFLOW_ENTRY_IP_SRC_POS]<= in_data[47:16];
                           flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS + 31: `OPENFLOW_ENTRY_IP_DST_POS + 16]<= in_data[15:0];
                        end
                        else if(is_arp) begin
                           counter <= counter + 2;
                           flow_entry_all[`OPENFLOW_ENTRY_IP_SRC_POS + 31:`OPENFLOW_ENTRY_IP_SRC_POS]<= in_data[31:0];
                        end
                     end

                     IP_DST_LO_TRANSP_PORTS_WORD: begin
                        counter       <= counter;
                        ip_hdr_len    <= ip_hdr_len - 2'h2;

                        if(is_ip) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS + 15:`OPENFLOW_ENTRY_IP_DST_POS] <= in_data[63:48];
                           is_ip    <= 0;
                        end
                        else if(is_arp) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS + 31:`OPENFLOW_ENTRY_IP_DST_POS+15] <= in_data[15:0];
                        end

                        if(is_tcp_udp) begin
                           if(ip_hdr_len == 5) begin
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS + 15:`OPENFLOW_ENTRY_TRANSP_SRC_POS]    <= in_data[47:32];
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS + 15:`OPENFLOW_ENTRY_TRANSP_DST_POS]    <= in_data[31:16];
                           end
                           else if(ip_hdr_len == 6) begin
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS + 15:`OPENFLOW_ENTRY_TRANSP_SRC_POS]    <= in_data[15:0];
                           end
                           else if(ip_hdr_len == 4) begin
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS + 15:`OPENFLOW_ENTRY_TRANSP_DST_POS]    <= in_data[63:48];
                           end
                        end
                        else if (is_icmp) begin
                           if(ip_hdr_len == 5) begin
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS + 15:`OPENFLOW_ENTRY_TRANSP_SRC_POS + 8] <= 8'h0;
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS +  7:`OPENFLOW_ENTRY_TRANSP_SRC_POS]     <= in_data[47:40];
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS + 15:`OPENFLOW_ENTRY_TRANSP_DST_POS + 8] <= 8'h0;
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS +  7:`OPENFLOW_ENTRY_TRANSP_DST_POS]     <= in_data[39:32];
                           end
                           else if(ip_hdr_len == 6) begin
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS + 15:`OPENFLOW_ENTRY_TRANSP_SRC_POS + 8] <= 8'h0;
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS +  7:`OPENFLOW_ENTRY_TRANSP_SRC_POS]     <= in_data[15:8];
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS + 15:`OPENFLOW_ENTRY_TRANSP_DST_POS + 8] <= 8'h0;
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS +  7:`OPENFLOW_ENTRY_TRANSP_DST_POS]     <= in_data[7:0];
                           end
                        end
                        if(!(is_tcp_udp || is_icmp)
                           || ((is_tcp_udp || is_icmp)
                               && (ip_hdr_len == 5
                                   || ip_hdr_len == 4))) begin
                           flow_entry_vld    <= 1'b1;

                           if(in_ctrl != 0) begin
                              state    <= RESET_FLOW_ENTRY;
                           end
                           else begin
                              state    <= WAIT_EOP;
                           end
                        end
                     end

                     ARP_DST_HI_WORD: begin
                        flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS + 31:`OPENFLOW_ENTRY_IP_DST_POS + 16]
                           <= in_data[15:0];
                     end

                     default: begin
                        flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS + 15:`OPENFLOW_ENTRY_IP_DST_POS]
                           <= in_data[63:48];
                        is_arp            <= 0;
                        flow_entry_vld    <= 1'b1;

                        if(in_ctrl != 0) begin
                           state    <= RESET_FLOW_ENTRY;
                        end
                        else begin
                           state    <= WAIT_EOP;
                        end
                     end

                  endcase
               end
               end
            end

            WAIT_EOP: begin
               flow_entry_vld    <= 1'b0;
               if(in_ctrl!=0 & in_wr) begin
                  state             <= MODULE_HDRS;
                  flow_entry_all        <= flow_entry_default;
                  pkt_size          <= 0;
               end
            end

         endcase
      end
   end

endmodule
module header_parser
    #(parameter DATA_WIDTH = 64,
      parameter CTRL_WIDTH = DATA_WIDTH/8,
      parameter PKT_SIZE_WIDTH = 12,
      parameter ADDITIONAL_WORD_SIZE = 16,
      parameter ADDITIONAL_WORD_BITMASK = 16'h0fff,
      parameter ADDITIONAL_WORD_POS  = 224,
      parameter ADDITIONAL_WORD_CTRL = 8'h40,
      parameter ADDITIONAL_WORD_DEFAULT = 16'hffff,
      parameter FLOW_ENTRY_SIZE_ALL = 240,
      parameter OPENFLOW_ENTRY_WIDTH = 64,
      parameter CURRENT_TABLE_ID = 0
      )
   (
    input  [DATA_WIDTH-1:0]                in_data,
    input  [CTRL_WIDTH-1:0]                in_ctrl,
    input                                  in_wr,


    output reg[OPENFLOW_ENTRY_WIDTH-1:0]           flow_entry,

    output reg [PKT_SIZE_WIDTH-1:0]        pkt_size,
    output reg                             flow_entry_vld,
    
    input[7:0]                             head_combine,
    
    output                                  skip_lookup,


    input                                  reset,
    input                                  clk
   );

   reg [`OPENFLOW_NEXT_TABLE_ID_WIDTH-1:0]    pkt_dst_table_id;
   assign skip_lookup=(pkt_dst_table_id>CURRENT_TABLE_ID)?1:0;


   reg [FLOW_ENTRY_SIZE_ALL-1:0]           flow_entry_all;
      reg[7:0]                             metadata;
    
   always@(*)
    begin
        flow_entry[95:64]={24'h0,metadata};
        if(head_combine == 0)begin
           flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS +: `OPENFLOW_ENTRY_SRC_PORT_WIDTH];
           flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_DST_POS +:`OPENFLOW_ENTRY_ETH_DST_WIDTH];
        end
        else if(head_combine == 1)begin
           flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS +:`OPENFLOW_ENTRY_TRANSP_SRC_WIDTH];
           flow_entry[31:16] = flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS +:`OPENFLOW_ENTRY_TRANSP_DST_WIDTH];         
           flow_entry[63:32] = flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS +:`OPENFLOW_ENTRY_IP_DST_WIDTH];
        end
        else if(head_combine == 2)begin
           flow_entry[15:0]= flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS+:`OPENFLOW_ENTRY_ETH_TYPE_WIDTH];      
           flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS+:`OPENFLOW_ENTRY_ETH_SRC_WIDTH];
        end     
      else if(head_combine == 3)begin
          flow_entry[15:0] = flow_entry_all[`OPENFLOW_ENTRY_VLAN_ID_POS +: `OPENFLOW_ENTRY_VLAN_ID_WIDTH];
          flow_entry[63:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS +:`OPENFLOW_ENTRY_ETH_SRC_WIDTH];
      end  
      else if(head_combine == 4)begin
         flow_entry[7:0]   = flow_entry_all[`OPENFLOW_ENTRY_IP_PROTO_POS +: `OPENFLOW_ENTRY_IP_PROTO_WIDTH];
         flow_entry[15:8]  = flow_entry_all[`OPENFLOW_ENTRY_IP_TOS_POS +: `OPENFLOW_ENTRY_IP_TOS_WIDTH];
         flow_entry[31:16] = flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS+:`OPENFLOW_ENTRY_ETH_TYPE_WIDTH];
         flow_entry[63:32] = flow_entry_all[`OPENFLOW_ENTRY_IP_SRC_POS +:`OPENFLOW_ENTRY_IP_SRC_WIDTH];        
      end
      else begin
          flow_entry[15:0] =  0  ;
          flow_entry[63:16] = 0  ;
      end
    end

   `LOG2_FUNC


   localparam MODULE_HDRS                   = 0;
   localparam PKT_WORDS                     = 1;
   localparam WAIT_EOP                      = 2;
   localparam RESET_FLOW_ENTRY              = 3;

   localparam MAC_SRC_LO_ETHERTYPE_WORD     = 1,
              IP_PROT_WORD                  = 2,
              IP_SRC_DST_HI_WORD            = 3,
              IP_DST_LO_TRANSP_PORTS_WORD   = 4,
              ARP_DST_HI_WORD               = 5,
              ARP_DST_LO_WORD               = 6;


   reg [1:0]                            state;
   reg [2:0]                            counter;

   reg                                  is_ip;
   reg                                  is_tcp_udp;
   reg                                  is_icmp;
   reg                                  is_vlan;
   reg                                  is_arp;


   reg [3:0]                            ip_hdr_len;

   wire [FLOW_ENTRY_SIZE_ALL-1:0]       flow_entry_default;
   


   generate
      if(FLOW_ENTRY_SIZE_ALL > ADDITIONAL_WORD_POS+ADDITIONAL_WORD_SIZE) begin:gen_flow_msb
         assign flow_entry_default[FLOW_ENTRY_SIZE_ALL-1:ADDITIONAL_WORD_POS+ADDITIONAL_WORD_SIZE]     = 0;
      end
   endgenerate
   assign flow_entry_default[ADDITIONAL_WORD_POS+ADDITIONAL_WORD_SIZE-1:ADDITIONAL_WORD_POS] = ADDITIONAL_WORD_DEFAULT;
   assign flow_entry_default[ADDITIONAL_WORD_POS-1:0]                                        = 0;


   always @(posedge clk) begin
      if(reset) begin
         counter           <= 0;
         flow_entry_vld    <= 0;
         flow_entry_all        <= flow_entry_default;
         pkt_size          <= 0;
         state             <= MODULE_HDRS;
         is_ip             <= 0;
         is_tcp_udp        <= 0;
         is_icmp           <= 0;
         is_vlan           <= 0;
         ip_hdr_len        <= 0;
         metadata          <= 0;
      end

      else begin
         flow_entry_vld    <= 0;
         case (state)
            RESET_FLOW_ENTRY: begin
               flow_entry_all    <= flow_entry_default;
               state         <= MODULE_HDRS;
               if(in_wr) begin

                  if(in_ctrl==ADDITIONAL_WORD_CTRL) begin
                     flow_entry_all[ADDITIONAL_WORD_POS + ADDITIONAL_WORD_SIZE - 1 : ADDITIONAL_WORD_POS]
                                                      <= in_data[ADDITIONAL_WORD_SIZE-1 : 0] & ADDITIONAL_WORD_BITMASK;
                     is_vlan <= (in_ctrl==`VLAN_CTRL_WORD);
                  end
                  else if(in_ctrl==`METEDATA_NUM)
                    metadata=in_data[7:0];

                  else if(in_ctrl==`IO_QUEUE_STAGE_NUM) begin
                     flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1 : `OPENFLOW_ENTRY_SRC_PORT_POS]
                                                          <= in_data[`IOQ_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1 : `IOQ_SRC_PORT_POS];
                     pkt_dst_table_id=in_data[`IOQ_DST_TABLE_ID_POS +: `IOQ_DST_TABLE_ID_LEN];                                     
                     if(is_vlan) begin
                        pkt_size <= (in_data[`IOQ_BYTE_LEN_POS + PKT_SIZE_WIDTH - 1:`IOQ_BYTE_LEN_POS] + 4);
                     end
                     else begin
                        pkt_size <= in_data[`IOQ_BYTE_LEN_POS + PKT_SIZE_WIDTH - 1:`IOQ_BYTE_LEN_POS];
                     end
                     is_vlan <= 0;
                  end


                  else if(in_ctrl==0) begin
                     $display("%t %m ERROR: found ctrl=0 as first word of pkt.", $time);
                     $stop;
                  end

               end
            end

            MODULE_HDRS: begin
               if(in_wr) begin

                  if(in_ctrl==ADDITIONAL_WORD_CTRL) begin
                     flow_entry_all[ADDITIONAL_WORD_POS + ADDITIONAL_WORD_SIZE - 1 : ADDITIONAL_WORD_POS]
                                                      <= in_data[ADDITIONAL_WORD_SIZE-1 : 0] & ADDITIONAL_WORD_BITMASK;
                            
                     is_vlan <= (in_ctrl==`VLAN_CTRL_WORD);
                  end

                  else if(in_ctrl==`VLAN_CTRL_WORD)
                     flow_entry_all[`OPENFLOW_SET_VLAN_VID_POS+`OPENFLOW_SET_VLAN_VID_WIDTH-1:`OPENFLOW_SET_VLAN_VID_POS] <= in_data [15:0];                  
                  else if(in_ctrl==`METEDATA_NUM)
                    metadata=in_data[7:0];
                  else if(in_ctrl==`IO_QUEUE_STAGE_NUM) begin
                     flow_entry_all[`OPENFLOW_ENTRY_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1:`OPENFLOW_ENTRY_SRC_PORT_POS]
                                                          <= in_data[`IOQ_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1:`IOQ_SRC_PORT_POS];
                     pkt_dst_table_id=in_data[`IOQ_DST_TABLE_ID_POS +: `IOQ_DST_TABLE_ID_LEN];                                      
                     if(is_vlan) begin
                        pkt_size <= (in_data[`IOQ_BYTE_LEN_POS + PKT_SIZE_WIDTH - 1:`IOQ_BYTE_LEN_POS] + 4);
                     end
                     else begin
                        pkt_size <= in_data[`IOQ_BYTE_LEN_POS + PKT_SIZE_WIDTH - 1:`IOQ_BYTE_LEN_POS];
                     end
                     is_vlan <= 0;
                  end

                  else if(in_ctrl==0) begin
                     flow_entry_all[`OPENFLOW_ENTRY_ETH_DST_POS + 47 : `OPENFLOW_ENTRY_ETH_DST_POS]
                                        <= in_data[63:16];

                     flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS + 47 : `OPENFLOW_ENTRY_ETH_SRC_POS + 32]
                                        <= in_data[15:0];
                     state    <= PKT_WORDS;
                  end
                  counter <= 1;
               end
            end

            PKT_WORDS: begin
               if(in_wr) begin
                  if(in_ctrl!=0)
                  begin
                     flow_entry_vld    <= 1'b1;
                     state             <= MODULE_HDRS;
                     flow_entry_all        <= flow_entry_default;
                     pkt_size          <= 0;
                  end
                  else begin
                  counter <= counter + 1;

                  case(counter)
                     MAC_SRC_LO_ETHERTYPE_WORD: begin
                        flow_entry_all[`OPENFLOW_ENTRY_ETH_SRC_POS + 31 : `OPENFLOW_ENTRY_ETH_SRC_POS] <= in_data[63:32];
                        flow_entry_all[`OPENFLOW_ENTRY_ETH_TYPE_POS + 15 : `OPENFLOW_ENTRY_ETH_TYPE_POS] <= in_data[31:16];
                        if (in_data[31:16] == `ETH_TYPE_IP) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_TOS_POS + 7 : `OPENFLOW_ENTRY_IP_TOS_POS ]<= in_data[7:2];
                        end
                        is_ip      <= in_data[31:16] == `ETH_TYPE_IP;
                        is_arp     <= in_data[31:16] == `ETH_TYPE_ARP;
                        ip_hdr_len <= in_data[11:8];
                     end

                     IP_PROT_WORD: begin
                        if(is_ip) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_PROTO_POS + 7 : `OPENFLOW_ENTRY_IP_PROTO_POS] <= in_data[7:0];

                           if(ip_hdr_len < 5) begin
                              flow_entry_all        <= flow_entry_default;
                              flow_entry_vld    <= 1'b1;
                              state             <= WAIT_EOP;
                           end
                        end
                        else if(is_arp) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_PROTO_POS + 7 : `OPENFLOW_ENTRY_IP_PROTO_POS] <= in_data[23:16];
                        end
                        is_tcp_udp <= is_ip && ((in_data[7:0] == `IP_PROTO_TCP)
                                                || (in_data[7:0] == `IP_PROTO_UDP));
                        is_icmp    <= is_ip && (in_data[7:0] == `IP_PROTO_ICMP);
                     end

                     IP_SRC_DST_HI_WORD: begin
                        if(is_ip) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_SRC_POS + 31:`OPENFLOW_ENTRY_IP_SRC_POS]<= in_data[47:16];
                           flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS + 31: `OPENFLOW_ENTRY_IP_DST_POS + 16]<= in_data[15:0];
                        end
                        else if(is_arp) begin
                           counter <= counter + 2;
                           flow_entry_all[`OPENFLOW_ENTRY_IP_SRC_POS + 31:`OPENFLOW_ENTRY_IP_SRC_POS]<= in_data[31:0];
                        end
                     end

                     IP_DST_LO_TRANSP_PORTS_WORD: begin
                        counter       <= counter;
                        ip_hdr_len    <= ip_hdr_len - 2'h2;

                        if(is_ip) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS + 15:`OPENFLOW_ENTRY_IP_DST_POS] <= in_data[63:48];
                           is_ip    <= 0;
                        end
                        else if(is_arp) begin
                           flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS + 31:`OPENFLOW_ENTRY_IP_DST_POS+15] <= in_data[15:0];
                        end

                        if(is_tcp_udp) begin
                           if(ip_hdr_len == 5) begin
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS + 15:`OPENFLOW_ENTRY_TRANSP_SRC_POS]    <= in_data[47:32];
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS + 15:`OPENFLOW_ENTRY_TRANSP_DST_POS]    <= in_data[31:16];
                           end
                           else if(ip_hdr_len == 6) begin
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS + 15:`OPENFLOW_ENTRY_TRANSP_SRC_POS]    <= in_data[15:0];
                           end
                           else if(ip_hdr_len == 4) begin
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS + 15:`OPENFLOW_ENTRY_TRANSP_DST_POS]    <= in_data[63:48];
                           end
                        end
                        else if (is_icmp) begin
                           if(ip_hdr_len == 5) begin
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS + 15:`OPENFLOW_ENTRY_TRANSP_SRC_POS + 8] <= 8'h0;
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS +  7:`OPENFLOW_ENTRY_TRANSP_SRC_POS]     <= in_data[47:40];
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS + 15:`OPENFLOW_ENTRY_TRANSP_DST_POS + 8] <= 8'h0;
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS +  7:`OPENFLOW_ENTRY_TRANSP_DST_POS]     <= in_data[39:32];
                           end
                           else if(ip_hdr_len == 6) begin
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS + 15:`OPENFLOW_ENTRY_TRANSP_SRC_POS + 8] <= 8'h0;
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_SRC_POS +  7:`OPENFLOW_ENTRY_TRANSP_SRC_POS]     <= in_data[15:8];
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS + 15:`OPENFLOW_ENTRY_TRANSP_DST_POS + 8] <= 8'h0;
                              flow_entry_all[`OPENFLOW_ENTRY_TRANSP_DST_POS +  7:`OPENFLOW_ENTRY_TRANSP_DST_POS]     <= in_data[7:0];
                           end
                        end
                        if(!(is_tcp_udp || is_icmp)
                           || ((is_tcp_udp || is_icmp)
                               && (ip_hdr_len == 5
                                   || ip_hdr_len == 4))) begin
                           flow_entry_vld    <= 1'b1;

                           if(in_ctrl != 0) begin
                              state    <= RESET_FLOW_ENTRY;
                           end
                           else begin
                              state    <= WAIT_EOP;
                           end
                        end
                     end

                     ARP_DST_HI_WORD: begin
                        flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS + 31:`OPENFLOW_ENTRY_IP_DST_POS + 16]
                           <= in_data[15:0];
                     end

                     default: begin
                        flow_entry_all[`OPENFLOW_ENTRY_IP_DST_POS + 15:`OPENFLOW_ENTRY_IP_DST_POS]
                           <= in_data[63:48];
                        is_arp            <= 0;
                        flow_entry_vld    <= 1'b1;

                        if(in_ctrl != 0) begin
                           state    <= RESET_FLOW_ENTRY;
                        end
                        else begin
                           state    <= WAIT_EOP;
                        end
                     end

                  endcase
               end
               end
            end

            WAIT_EOP: begin
               flow_entry_vld    <= 1'b0;
               if(in_ctrl!=0 & in_wr) begin
                  state             <= MODULE_HDRS;
                  flow_entry_all        <= flow_entry_default;
                  pkt_size          <= 0;
               end
            end

         endcase
      end
   end

endmodule