data/full_repos/permissive/159891569/timers.t.v
 line:3: before: ";"
1: b'%Error: data/full_repos/permissive/159891569/timers.t.v:1: Cannot find include file: timers.v\n`include "timers.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/timers.v\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/timers.v.v\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/timers.v.sv\n             timers.v\n             timers.v.v\n             timers.v.sv\n             obj_dir/timers.v\n             obj_dir/timers.v.v\n             obj_dir/timers.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:12: Unsupported: Ignoring delay on this delayed statement.\n  clk = 0; #10;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/159891569/timers.t.v:14: Unsupported or unknown PLI call: $monitor\n  $monitor("clk=%b, clkOut=%b, i=", clk, clkOut, tmr.i);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:16: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:16: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:17: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:17: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:18: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:18: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:19: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:19: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:20: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:20: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:21: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:21: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:22: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:22: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:23: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:23: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:24: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:24: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:25: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:25: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:26: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:26: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:27: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/timers.t.v:27: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Error: Exiting due to 2 error(s), 25 warning(s)\n'
module testTimer();

	reg clk;
	wire clkOut;


	varTimer #(3) tmr(clk, 3'd5, clkOut);

	initial begin
		clk = 0; #10;
		
		$monitor("clk=%b, clkOut=%b, i=", clk, clkOut, tmr.i);

		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;

		$finish;
	end
endmodule
module testTimer();


	reg clk;
	wire clkOut;


	varTimer #(3) tmr(clk, 3'd5, clkOut);

	initial begin
		clk = 0; #10;
		
		$monitor("clk=%b, clkOut=%b, i=", clk, clkOut, tmr.i);

		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;

		$finish;
	end
endmodule