data/full_repos/permissive/160073872/fpga/hdl/soc.srcs/sources_1/new/rst_spike.v
data/verilator_xmls/c53d288b-a59c-4619-9e19-c2940b642b8d.xml
module rst_spike(
    input wire clk,
    input wire rst_in,
    input wire spi_clk,
    output reg rst_out
);

reg[31:0] wdt = 0;

reg spi_clk_prev = 0;

always @(posedge clk) begin
  spi_clk_prev <= spi_clk;

  if (spi_clk != spi_clk_prev || rst_in) begin
    wdt <= 0;
  end else if (wdt < `WDT_PERIOD) begin
    wdt <= wdt + 1;
  end else begin
    wdt <= 0;
  end

  rst_out <= (wdt > `WDT_WAIT) || rst_in;
end

endmodule
module rst_spike(
    input wire clk,
    input wire rst_in,
    input wire spi_clk,
    output reg rst_out
);


reg[31:0] wdt = 0;

reg spi_clk_prev = 0;

always @(posedge clk) begin
  spi_clk_prev <= spi_clk;

  if (spi_clk != spi_clk_prev || rst_in) begin
    wdt <= 0;
  end else if (wdt < `WDT_PERIOD) begin
    wdt <= wdt + 1;
  end else begin
    wdt <= 0;
  end

  rst_out <= (wdt > `WDT_WAIT) || rst_in;
end

endmodule