data/full_repos/permissive/20759093/CPU_TOP.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/20759093/CPU_TOP.v:241: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'Single_Cycle_CPU\'\nmodule Single_Cycle_CPU(\n       ^~~~~~~~~~~~~~~~\n                                                                    : ... Top module \'mux_2_to_1_5\'\nmodule mux_2_to_1_5(\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/20759093/CPU_TOP.v:496: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                 : ... In instance Single_Cycle_CPU.M4\n            4\'b1001 : result <= (A < B);\n                             ^~\n%Error: data/full_repos/permissive/20759093/CPU_TOP.v:104: Cannot find file containing module: \'RAM_A\'\n    RAM_A M8(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A.v\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A.sv\n             RAM_A\n             RAM_A.v\n             RAM_A.sv\n             obj_dir/RAM_A\n             obj_dir/RAM_A.v\n             obj_dir/RAM_A.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module control(
    input [5:0]op,
    input [5:0]funct,
    output reg [1:0]RegDst,
    output reg RegWrite,
    output reg ALUSrc,
    output reg MemRead,
    output reg MemWrite,
    output reg MemtoReg,
    output reg [1:0]Jump,
    output reg Branch,
    output reg Equal,
    output reg JumpLink,
    output reg [3:0]ALUCtrl
);








    always @* begin
     case(op)
        6'h08 : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b0001;
            end
        6'h0C : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b0011;
            end
        6'h0D : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b0100;
            end
        6'h0E : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b0101;
            end
        6'h0F : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b1000;
            end
        6'h23 : begin
            `CONTROL_SIGNAL <= 12'b0011101000X0;
            ALUCtrl <= 4'b0001;
            end
        6'h2B : begin
            `CONTROL_SIGNAL <= 12'bXX01011000X0;
            ALUCtrl <= 4'b0001;
            end
        6'h04 : begin
            `CONTROL_SIGNAL <= 12'b000000000100;
            ALUCtrl <= 4'b0010;
            end
        6'h05 : begin
            `CONTROL_SIGNAL <= 12'b000000000110;
            ALUCtrl <= 4'b0010;
            end
        6'h0A : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b1001;
            end
        6'h02 : begin
            `CONTROL_SIGNAL <= 12'bXX0X000010X0;
            ALUCtrl <= 4'b0000; 
            end
        6'h03 : begin
            `CONTROL_SIGNAL <= 12'b101X000010X1;
            ALUCtrl <= 4'b0000; 
            end
        6'h00 :
            case(funct) 
                6'd32 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0001;
                    end
                6'd34 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0010;
                    end
                6'd36 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0011;
                    end
                6'd37 : begin
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0100;
                    end
                6'd38 : begin
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0101;
                    end
                6'd39 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0110;
                    end
                6'd42 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b1001;
                    end
                6'd02 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0111;
                    end
                6'd08 : begin
                    `CONTROL_SIGNAL <= 12'b000000010XX0;
                    ALUCtrl <= 4'b0000; 
                    end
                6'd09 : begin
                    `CONTROL_SIGNAL <= 12'b011000010XX1;
                    ALUCtrl <= 4'b0000; 
                    end
                default : begin
                    `CONTROL_SIGNAL <= 12'b0;
                    ALUCtrl <= 4'b0;
                    end
            endcase
        default : begin
            `CONTROL_SIGNAL <= 12'b0;
            ALUCtrl <= 4'b0;
            end
    endcase
 end

endmodule
module control(
    input [5:0]op,
    input [5:0]funct,
    output reg [1:0]RegDst,
    output reg RegWrite,
    output reg ALUSrc,
    output reg MemRead,
    output reg MemWrite,
    output reg MemtoReg,
    output reg [1:0]Jump,
    output reg Branch,
    output reg Equal,
    output reg JumpLink,
    output reg [3:0]ALUCtrl
);









    always @* begin
     case(op)
        6'h08 : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b0001;
            end
        6'h0C : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b0011;
            end
        6'h0D : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b0100;
            end
        6'h0E : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b0101;
            end
        6'h0F : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b1000;
            end
        6'h23 : begin
            `CONTROL_SIGNAL <= 12'b0011101000X0;
            ALUCtrl <= 4'b0001;
            end
        6'h2B : begin
            `CONTROL_SIGNAL <= 12'bXX01011000X0;
            ALUCtrl <= 4'b0001;
            end
        6'h04 : begin
            `CONTROL_SIGNAL <= 12'b000000000100;
            ALUCtrl <= 4'b0010;
            end
        6'h05 : begin
            `CONTROL_SIGNAL <= 12'b000000000110;
            ALUCtrl <= 4'b0010;
            end
        6'h0A : begin
            `CONTROL_SIGNAL <= 12'b0011000000X0;
            ALUCtrl <= 4'b1001;
            end
        6'h02 : begin
            `CONTROL_SIGNAL <= 12'bXX0X000010X0;
            ALUCtrl <= 4'b0000; 
            end
        6'h03 : begin
            `CONTROL_SIGNAL <= 12'b101X000010X1;
            ALUCtrl <= 4'b0000; 
            end
        6'h00 :
            case(funct) 
                6'd32 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0001;
                    end
                6'd34 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0010;
                    end
                6'd36 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0011;
                    end
                6'd37 : begin
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0100;
                    end
                6'd38 : begin
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0101;
                    end
                6'd39 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0110;
                    end
                6'd42 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b1001;
                    end
                6'd02 : begin 
                    `CONTROL_SIGNAL <= 12'b0110000000X0;
                    ALUCtrl <= 4'b0111;
                    end
                6'd08 : begin
                    `CONTROL_SIGNAL <= 12'b000000010XX0;
                    ALUCtrl <= 4'b0000; 
                    end
                6'd09 : begin
                    `CONTROL_SIGNAL <= 12'b011000010XX1;
                    ALUCtrl <= 4'b0000; 
                    end
                default : begin
                    `CONTROL_SIGNAL <= 12'b0;
                    ALUCtrl <= 4'b0;
                    end
            endcase
        default : begin
            `CONTROL_SIGNAL <= 12'b0;
            ALUCtrl <= 4'b0;
            end
    endcase
 end

endmodule