data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v
 line:64: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:110: Unsupported: Ignoring delay on this delayed statement.\n    #2 Enable = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:114: Unsupported: Ignoring delay on this delayed statement.\n    #3 Enable = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:64: Unsupported: Ignoring delay on this delayed statement.\ninitial #200 begin\n        ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:134: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    Mem[Address] = DataIn[7:0];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:138: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    Mem[Address] = DataIn[15:8];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:145: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    Mem[Address] = DataIn[31:24];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:155: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        Mem[Address] = DataIn[31:24];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:179: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        DataOut[7:0] = Mem[Address];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:189: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        DataOut[7:0] = Mem[Address];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:174: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    if(Mem[Address][7] == 1\'b1)\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:200: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        DataOut[15:8] = Mem[Address];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:209: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        DataOut[15:8] = Mem[Address];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:196: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    if(Mem[Address][7] == 1\'b1)\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:218: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    DataOut[31:24] = Mem[Address];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:228: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    DataOut[7:0] = Mem[Address];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:234: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                    DataOut[15:8] = Mem[Address];\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:243: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                         : ... In instance Ram_access.ram1\n                        DataOut[31:24] = Mem[Address];\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:17: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                        : ... In instance Ram_access\n        ram1.Mem[Address] = data;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:17: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'data\' generates 32 bits.\n                                                                                        : ... In instance Ram_access\n        ram1.Mem[Address] = data;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/150028698/PF1_Henriquez_Paulino_Juan_ram.v:40: Bit extraction of array[512:0] requires 10 bit index, not 9 bits.\n                                                                                        : ... In instance Ram_access\n    $display("data in ram: address %h, data is %b", Address, ram1.Mem[Address]);\n                                                                     ^\n%Error: Exiting due to 36 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram512x8(output reg [31:0] DataOut, input Enable, input [8:0] Address, input [31:0] DataIn,
                    input [5:0] opcode, output reg almostdone = 1'b0, output reg done );

reg [7:0] Mem[0:512];
reg [7:0] zero = 8'b00000000;
reg [7:0] one = 8'b11111111;
always @ (Enable) begin
    done = 1'b0;
    if(Enable)
        begin

            case(opcode)
                6'b101000:
                begin  
                    Mem[Address] = DataIn[7:0];
                end
                6'b101001:
                begin
                    Mem[Address] = DataIn[15:8];
                    Mem[Address+1] = DataIn[7:0];


                end
                6'b101011:
                begin
                    Mem[Address] = DataIn[31:24];
                    Mem[Address+1] = DataIn[23:16];
                    Mem[Address+2] = DataIn[15:8];
                    Mem[Address+3] = DataIn[7:0];
                end

                6'b111101:
                begin
                    if(!almostdone)
                    begin
                        Mem[Address] = DataIn[31:24];
                        Mem[Address+1] = DataIn[23:16];
                        Mem[Address+2] = DataIn[15:8];
                        Mem[Address+3] = DataIn[7:0];
                        almostdone = 1'b1;
                    end
                     else 
                    begin
                        Mem[Address+4] = DataIn[31:24];
                        Mem[Address+5] = DataIn[23:16];
                        Mem[Address+6] = DataIn[15:8];
                        Mem[Address+7] = DataIn[7:0];
                        almostdone = 1'b0;
                    end
                end

                6'b100000:
                begin 

                    if(Mem[Address][7] == 1'b1)
                    begin
                        DataOut[31:24] = one;
                        DataOut[23:16] = one;
                        DataOut[15:8] = one;
                        DataOut[7:0] = Mem[Address];


                    end
                    else  
                    begin

                        DataOut[31:24] = zero;
                        DataOut[23:16] = zero;
                        DataOut[15:8] = zero;
                        DataOut[7:0] = Mem[Address];
                    end
                    
                end
                6'b100001:
                begin

                    if(Mem[Address][7] == 1'b1)
                    begin
                        DataOut[31:24] = one;
                        DataOut[23:16] = one;
                        DataOut[15:8] = Mem[Address];
                        DataOut[7:0] = Mem[Address+1];


                    end
                    else 
                    begin
                        DataOut[31:24] = zero;
                        DataOut[23:16] = zero;
                        DataOut[15:8] = Mem[Address];
                        DataOut[7:0] = Mem[Address+1];
                    end
                    
                end
                6'b100011:
                begin


                    DataOut[31:24] = Mem[Address];
                    DataOut[23:16] = Mem[Address+1];
                    DataOut[15:8] = Mem[Address+2];
                    DataOut[7:0] = Mem[Address+3];
                end
                6'b100100:
                begin
                    DataOut[31:24] = zero;
                    DataOut[23:16] = zero;
                    DataOut[15:8] = zero;
                    DataOut[7:0] = Mem[Address];
                end
                6'b100101:
                begin
                    DataOut[31:24] = zero;
                    DataOut[23:16] = zero;
                    DataOut[15:8] = Mem[Address];
                    DataOut[7:0] = Mem[Address+1];
                end

                6'b110101:
                begin
                    if(!almostdone)

                    begin
                        DataOut[31:24] = Mem[Address];
                        DataOut[23:16] = Mem[Address+1];
                        DataOut[15:8] = Mem[Address+2];
                        DataOut[7:0] = Mem[Address+3];
                        almostdone = 1'b1;
                    end
                    else
                    begin 
                        DataOut[31:24] = Mem[Address+4];
                        DataOut[23:16] = Mem[Address+5];
                        DataOut[15:8] = Mem[Address+6];
                        DataOut[7:0] = Mem[Address+7];
                        almostdone = 1'b0;
                    end
                end
            endcase
            done = 1'b1;
    end
end
endmodule
module ram512x8(output reg [31:0] DataOut, input Enable, input [8:0] Address, input [31:0] DataIn,
                    input [5:0] opcode, output reg almostdone = 1'b0, output reg done );


reg [7:0] Mem[0:512];
reg [7:0] zero = 8'b00000000;
reg [7:0] one = 8'b11111111;
always @ (Enable) begin
    done = 1'b0;
    if(Enable)
        begin

            case(opcode)
                6'b101000:
                begin  
                    Mem[Address] = DataIn[7:0];
                end
                6'b101001:
                begin
                    Mem[Address] = DataIn[15:8];
                    Mem[Address+1] = DataIn[7:0];


                end
                6'b101011:
                begin
                    Mem[Address] = DataIn[31:24];
                    Mem[Address+1] = DataIn[23:16];
                    Mem[Address+2] = DataIn[15:8];
                    Mem[Address+3] = DataIn[7:0];
                end

                6'b111101:
                begin
                    if(!almostdone)
                    begin
                        Mem[Address] = DataIn[31:24];
                        Mem[Address+1] = DataIn[23:16];
                        Mem[Address+2] = DataIn[15:8];
                        Mem[Address+3] = DataIn[7:0];
                        almostdone = 1'b1;
                    end
                     else 
                    begin
                        Mem[Address+4] = DataIn[31:24];
                        Mem[Address+5] = DataIn[23:16];
                        Mem[Address+6] = DataIn[15:8];
                        Mem[Address+7] = DataIn[7:0];
                        almostdone = 1'b0;
                    end
                end

                6'b100000:
                begin 

                    if(Mem[Address][7] == 1'b1)
                    begin
                        DataOut[31:24] = one;
                        DataOut[23:16] = one;
                        DataOut[15:8] = one;
                        DataOut[7:0] = Mem[Address];


                    end
                    else  
                    begin

                        DataOut[31:24] = zero;
                        DataOut[23:16] = zero;
                        DataOut[15:8] = zero;
                        DataOut[7:0] = Mem[Address];
                    end
                    
                end
                6'b100001:
                begin

                    if(Mem[Address][7] == 1'b1)
                    begin
                        DataOut[31:24] = one;
                        DataOut[23:16] = one;
                        DataOut[15:8] = Mem[Address];
                        DataOut[7:0] = Mem[Address+1];


                    end
                    else 
                    begin
                        DataOut[31:24] = zero;
                        DataOut[23:16] = zero;
                        DataOut[15:8] = Mem[Address];
                        DataOut[7:0] = Mem[Address+1];
                    end
                    
                end
                6'b100011:
                begin


                    DataOut[31:24] = Mem[Address];
                    DataOut[23:16] = Mem[Address+1];
                    DataOut[15:8] = Mem[Address+2];
                    DataOut[7:0] = Mem[Address+3];
                end
                6'b100100:
                begin
                    DataOut[31:24] = zero;
                    DataOut[23:16] = zero;
                    DataOut[15:8] = zero;
                    DataOut[7:0] = Mem[Address];
                end
                6'b100101:
                begin
                    DataOut[31:24] = zero;
                    DataOut[23:16] = zero;
                    DataOut[15:8] = Mem[Address];
                    DataOut[7:0] = Mem[Address+1];
                end

                6'b110101:
                begin
                    if(!almostdone)

                    begin
                        DataOut[31:24] = Mem[Address];
                        DataOut[23:16] = Mem[Address+1];
                        DataOut[15:8] = Mem[Address+2];
                        DataOut[7:0] = Mem[Address+3];
                        almostdone = 1'b1;
                    end
                    else
                    begin 
                        DataOut[31:24] = Mem[Address+4];
                        DataOut[23:16] = Mem[Address+5];
                        DataOut[15:8] = Mem[Address+6];
                        DataOut[7:0] = Mem[Address+7];
                        almostdone = 1'b0;
                    end
                end
            endcase
            done = 1'b1;
    end
end
endmodule