data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_port_arbiter.v
1: b'%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_port_arbiter.v:113: Cannot find file containing module: \'wb_port\'\n  wb_port #(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog,data/full_repos/permissive/19905110/wb_port\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog,data/full_repos/permissive/19905110/wb_port.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog,data/full_repos/permissive/19905110/wb_port.sv\n             wb_port\n             wb_port.v\n             wb_port.sv\n             obj_dir/wb_port\n             obj_dir/wb_port.v\n             obj_dir/wb_port.sv\n%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_port_arbiter.v:154: Bit extraction of array[2:0] requires 2 bit index, not 3 bits.\n                                                                                                                                      : ... In instance wb_port_arbiter\n assign adr_o = p_adr_o[port_enc];\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_port_arbiter.v:155: Bit extraction of array[2:0] requires 2 bit index, not 3 bits.\n                                                                                                                                      : ... In instance wb_port_arbiter\n assign dat_o = p_dat_o[port_enc];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_port_arbiter.v:156: Bit extraction of var[2:0] requires 2 bit index, not 3 bits.\n                                                                                                                                      : ... In instance wb_port_arbiter\n assign acc_o = p_acc_o[port_enc];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_port_arbiter.v:157: Bit extraction of array[2:0] requires 2 bit index, not 3 bits.\n                                                                                                                                      : ... In instance wb_port_arbiter\n assign sel_o = p_sel_o[port_enc];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_port_arbiter.v:158: Bit extraction of array[2:0] requires 2 bit index, not 3 bits.\n                                                                                                                                      : ... In instance wb_port_arbiter\n assign we_o  = p_we_o[port_enc];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_port_arbiter.v:159: Bit extraction of array[2:0] requires 2 bit index, not 3 bits.\n                                                                                                                                      : ... In instance wb_port_arbiter\n assign buf_width_o = p_buf_width_o[port_enc];\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_port_arbiter.v:161: Bit extraction of var[2:0] requires 2 bit index, not 3 bits.\n                                                                                                                                      : ... In instance wb_port_arbiter\n assign safe_to_switch = sdram_idle_i & !p_acc_o[port_enc];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/wb_port_arbiter.v:192: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                                                      : ... In instance wb_port_arbiter\n    if (in[i]) ff1 = i;\n                   ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n'
function [WB_PORTS-1:0] ff1;
		input [WB_PORTS-1:0] in;
		integer i;
		begin
			ff1 = 0;
			for (i = WB_PORTS-1; i >= 0; i=i-1)
				if (in[i]) ff1 = i;
		end
	endfunction
function [WB_PORTS-1:0] ff1;

		input [WB_PORTS-1:0] in;
		integer i;
		begin
			ff1 = 0;
			for (i = WB_PORTS-1; i >= 0; i=i-1)
				if (in[i]) ff1 = i;
		end
	endfunction