data/full_repos/permissive/131069375/nano-risc/verilog/strobe.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/131069375/nano-risc/verilog/strobe.v:21: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'sel\' generates 2 bits.\n                                                                                  : ... In instance strobe\n     case (sel)\n     ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module strobe
(
 input 	      reset,clock,
 input [27:0] digits,
 output reg [6:0] seg,
 output reg [3:0] an
 );
 
   wire [1:0] sel;
   reg [19:0] clkdiv;
   
   always @(posedge clock)
     if (reset)
       clkdiv <= 0;
     else
       clkdiv = clkdiv + 1;
       
   assign sel = clkdiv[19:18];
   
   always @(sel)
     case (sel)
       4'b00: an = 4'b1110;
       4'b01: an = 4'b1101;
       4'b10: an = 4'b1011;
       4'b11: an = 4'b0111;
     endcase
     
   always @(digits or an)
     case (an)
       4'b0111: seg = digits[27:21];
       4'b1011: seg = digits[20:14];
       4'b1101: seg = digits[13:7];
       4'b1110: seg = digits[6:0];
       default: seg = 7'bxxxxxxx;
     endcase
endmodule
module strobe
(
 input 	      reset,clock,
 input [27:0] digits,
 output reg [6:0] seg,
 output reg [3:0] an
 );

 
   wire [1:0] sel;
   reg [19:0] clkdiv;
   
   always @(posedge clock)
     if (reset)
       clkdiv <= 0;
     else
       clkdiv = clkdiv + 1;
       
   assign sel = clkdiv[19:18];
   
   always @(sel)
     case (sel)
       4'b00: an = 4'b1110;
       4'b01: an = 4'b1101;
       4'b10: an = 4'b1011;
       4'b11: an = 4'b0111;
     endcase
     
   always @(digits or an)
     case (an)
       4'b0111: seg = digits[27:21];
       4'b1011: seg = digits[20:14];
       4'b1101: seg = digits[13:7];
       4'b1110: seg = digits[6:0];
       default: seg = 7'bxxxxxxx;
     endcase
endmodule