data/full_repos/permissive/100331186/tarea3/modulos/notGate.v
 line:50: before: ":"
1: b"%Error: data/full_repos/permissive/100331186/tarea3/modulos/notGate.v:44: Duplicate declaration of signal: 'a'\n                                                                        : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire a, y;\n       ^\n        data/full_repos/permissive/100331186/tarea3/modulos/notGate.v:32: ... Location of original declaration\n  input a,   \n        ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/notGate.v:44: Duplicate declaration of signal: 'y'\n  wire a, y;\n          ^\n        data/full_repos/permissive/100331186/tarea3/modulos/notGate.v:33: ... Location of original declaration\n  output y   \n         ^\n%Error: Exiting due to 2 error(s)\n"
module notGate (
  input a,
  output y
);


  parameter tpdmin = 5;
  parameter tpdmax = 7.1;

  parameter Vcc = 3.3;
  parameter Cl = 0.0015;


  wire a, y;


  integer c;
  initial c = 0;

  assign #(tpdmin:tpdmax:tpdmax) y = ~a;

  always @ (y) begin
    c=c+1;

  end
endmodule
module notGate (
  input a,
  output y
);



  parameter tpdmin = 5;
  parameter tpdmax = 7.1;

  parameter Vcc = 3.3;
  parameter Cl = 0.0015;


  wire a, y;


  integer c;
  initial c = 0;

  assign #(tpdmin:tpdmax:tpdmax) y = ~a;

  always @ (y) begin
    c=c+1;

  end
endmodule