data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display1_top.v
1: b"%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display1_top.v:13: Cannot find file containing module: 'SevenSegOneDig'\nSevenSegOneDig sSeg(number,sevenSeg);\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display1,data/full_repos/permissive/214278225/SevenSegOneDig\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display1,data/full_repos/permissive/214278225/SevenSegOneDig.v\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display1,data/full_repos/permissive/214278225/SevenSegOneDig.sv\n             SevenSegOneDig\n             SevenSegOneDig.v\n             SevenSegOneDig.sv\n             obj_dir/SevenSegOneDig\n             obj_dir/SevenSegOneDig.v\n             obj_dir/SevenSegOneDig.sv\n%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/display1/display1_top.v:14: Cannot find file containing module: 'decoder2_4'\ndecoder2_4 dec(count[SCWIDTH:SCWIDTH-1],anode,rst);\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module display1(clk, rst, dataIn, sevenSeg, anode);
input clk,rst;
input [7:0] dataIn;
output [3:0] anode;
output [7:0] sevenSeg;

parameter SCWIDTH = 15;

reg [15:0] count,countNext;
reg [3:0] number;

SevenSegOneDig sSeg(number,sevenSeg);
decoder2_4 dec(count[SCWIDTH:SCWIDTH-1],anode,rst);

 
always@(posedge clk) begin
	count <= countNext;
end

always @ (*)begin
	if(rst) begin
		countNext = 0;

		number    = 0;
	end 
	else begin
		countNext = count +1;
		case(count[SCWIDTH:SCWIDTH-1])
			2'b00: begin 
					number = {2'b00,dataIn[1:0]};
				end
			2'b01: begin 
					number = {2'b00,dataIn[3:2]};
				end
			2'b10: begin 
					number = {2'b00,dataIn[5:4]};
				end
			2'b11: begin 
					number = {2'b00,dataIn[7:6]};
				end
		endcase
	end
end
endmodule
module display1(clk, rst, dataIn, sevenSeg, anode);

input clk,rst;
input [7:0] dataIn;
output [3:0] anode;
output [7:0] sevenSeg;

parameter SCWIDTH = 15;

reg [15:0] count,countNext;
reg [3:0] number;

SevenSegOneDig sSeg(number,sevenSeg);
decoder2_4 dec(count[SCWIDTH:SCWIDTH-1],anode,rst);

 
always@(posedge clk) begin
	count <= countNext;
end

always @ (*)begin
	if(rst) begin
		countNext = 0;

		number    = 0;
	end 
	else begin
		countNext = count +1;
		case(count[SCWIDTH:SCWIDTH-1])
			2'b00: begin 
					number = {2'b00,dataIn[1:0]};
				end
			2'b01: begin 
					number = {2'b00,dataIn[3:2]};
				end
			2'b10: begin 
					number = {2'b00,dataIn[5:4]};
				end
			2'b11: begin 
					number = {2'b00,dataIn[7:6]};
				end
		endcase
	end
end
endmodule