data/full_repos/permissive/14593708/data/register-file/register-file.v
1: b"%Error: data/full_repos/permissive/14593708/data/register-file/register-file.v:16: Cannot find file containing module: 'decoder_2x4'\n    decoder_2x4 dec_write_register(write_register, decoder_out);\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14593708/data/register-file,data/full_repos/permissive/14593708/decoder_2x4\n             data/full_repos/permissive/14593708/data/register-file,data/full_repos/permissive/14593708/decoder_2x4.v\n             data/full_repos/permissive/14593708/data/register-file,data/full_repos/permissive/14593708/decoder_2x4.sv\n             decoder_2x4\n             decoder_2x4.v\n             decoder_2x4.sv\n             obj_dir/decoder_2x4\n             obj_dir/decoder_2x4.v\n             obj_dir/decoder_2x4.sv\n%Error: data/full_repos/permissive/14593708/data/register-file/register-file.v:22: Cannot find file containing module: 'register'\n    register r0(write_data, write_enabled_register[0], mux_in0);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/14593708/data/register-file/register-file.v:23: Cannot find file containing module: 'register'\n    register r1(write_data, write_enabled_register[1], mux_in1);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/14593708/data/register-file/register-file.v:24: Cannot find file containing module: 'register'\n    register r2(write_data, write_enabled_register[2], mux_in2);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/14593708/data/register-file/register-file.v:25: Cannot find file containing module: 'register'\n    register r3(write_data, write_enabled_register[3], mux_in3);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/14593708/data/register-file/register-file.v:27: Cannot find file containing module: 'multiplexor_4x1'\n    multiplexor_4x1 mux_data_port_0(read_register_port_0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/14593708/data/register-file/register-file.v:31: Cannot find file containing module: 'multiplexor_4x1'\n    multiplexor_4x1 mux_data_port_1(read_register_port_1,\n    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module register_file(input[1:0]   read_register_port_0,
                     input[1:0]   read_register_port_1,
                     input[1:0]   write_register,
                     input[31:0]  write_data,
                     input        write_enable,
                     output[31:0] read_data_port_0,
                     output[31:0] read_data_port_1);

    wire[31:0] mux_in0;
    wire[31:0] mux_in1;
    wire[31:0] mux_in2;
    wire[31:0] mux_in3;
    wire[3:0]  decoder_out;
    wire[3:0]  write_enabled_register;

    decoder_2x4 dec_write_register(write_register, decoder_out);
    and (write_enabled_register[0], write_enable, decoder_out[0]);
    and (write_enabled_register[1], write_enable, decoder_out[1]);
    and (write_enabled_register[2], write_enable, decoder_out[2]);
    and (write_enabled_register[3], write_enable, decoder_out[3]);

    register r0(write_data, write_enabled_register[0], mux_in0);
    register r1(write_data, write_enabled_register[1], mux_in1);
    register r2(write_data, write_enabled_register[2], mux_in2);
    register r3(write_data, write_enabled_register[3], mux_in3);

    multiplexor_4x1 mux_data_port_0(read_register_port_0,
                                    mux_in0, mux_in1, mux_in2, mux_in3,
                                    read_data_port_0);

    multiplexor_4x1 mux_data_port_1(read_register_port_1,
                                    mux_in0, mux_in1, mux_in2, mux_in3,
                                    read_data_port_1);
endmodule
module register_file(input[1:0]   read_register_port_0,
                     input[1:0]   read_register_port_1,
                     input[1:0]   write_register,
                     input[31:0]  write_data,
                     input        write_enable,
                     output[31:0] read_data_port_0,
                     output[31:0] read_data_port_1);


    wire[31:0] mux_in0;
    wire[31:0] mux_in1;
    wire[31:0] mux_in2;
    wire[31:0] mux_in3;
    wire[3:0]  decoder_out;
    wire[3:0]  write_enabled_register;

    decoder_2x4 dec_write_register(write_register, decoder_out);
    and (write_enabled_register[0], write_enable, decoder_out[0]);
    and (write_enabled_register[1], write_enable, decoder_out[1]);
    and (write_enabled_register[2], write_enable, decoder_out[2]);
    and (write_enabled_register[3], write_enable, decoder_out[3]);

    register r0(write_data, write_enabled_register[0], mux_in0);
    register r1(write_data, write_enabled_register[1], mux_in1);
    register r2(write_data, write_enabled_register[2], mux_in2);
    register r3(write_data, write_enabled_register[3], mux_in3);

    multiplexor_4x1 mux_data_port_0(read_register_port_0,
                                    mux_in0, mux_in1, mux_in2, mux_in3,
                                    read_data_port_0);

    multiplexor_4x1 mux_data_port_1(read_register_port_1,
                                    mux_in0, mux_in1, mux_in2, mux_in3,
                                    read_data_port_1);
endmodule