data/full_repos/permissive/135109538/top.v
1: b'%Error: data/full_repos/permissive/135109538/top.v:2: Cannot find include file: srlatch.v\n`include "srlatch.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135109538,data/full_repos/permissive/135109538/srlatch.v\n             data/full_repos/permissive/135109538,data/full_repos/permissive/135109538/srlatch.v.v\n             data/full_repos/permissive/135109538,data/full_repos/permissive/135109538/srlatch.v.sv\n             srlatch.v\n             srlatch.v.v\n             srlatch.v.sv\n             obj_dir/srlatch.v\n             obj_dir/srlatch.v.v\n             obj_dir/srlatch.v.sv\n%Error: data/full_repos/permissive/135109538/top.v:3: Cannot find include file: addrselect.v\n`include "addrselect.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135109538/top.v:4: Cannot find include file: tristate8port.v\n`include "tristate8port.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module top(
  input  [15:0] in,
  input  [2:0]  addr,
  input  [2:0]  aBus,
  output [7:0]  out
);
  wire [7:0] srout;
  wire       enable;


  srlatch srl0(
    .R(in[0]),
    .S(in[1]),
    .Qn(srout[0])
  );
  
  srlatch srl1(
    .R(in[2]),
    .S(in[3]),
    .Qn(srout[1])
  );

  srlatch srl2(
    .R(in[4]),
    .S(in[5]),
    .Qn(srout[2])
  );

  srlatch srl3(
    .R(in[6]),
    .S(in[7]),
    .Qn(srout[3])
  );

  srlatch srl4(
    .R(in[8]),
    .S(in[9]),
    .Qn(srout[4])
  );

  srlatch srl5(
    .R(in[10]),
    .S(in[11]),
    .Qn(srout[5])
  );

  srlatch srl6(
    .R(in[12]),
    .S(in[13]),
    .Qn(srout[6])
  );

  srlatch srl7(
    .R(in[14]),
    .S(in[15]),
    .Qn(srout[7])
  );
  

  addrselect as(
    .addr(addr),
    .aBus(aBus),
    .enable(enable)
  );
  

  tristate8port ts8(
    .enable(enable),
    .in(srout),
    .out(out)
  );
  
endmodule
module top(
  input  [15:0] in,
  input  [2:0]  addr,
  input  [2:0]  aBus,
  output [7:0]  out
);

  wire [7:0] srout;
  wire       enable;


  srlatch srl0(
    .R(in[0]),
    .S(in[1]),
    .Qn(srout[0])
  );
  
  srlatch srl1(
    .R(in[2]),
    .S(in[3]),
    .Qn(srout[1])
  );

  srlatch srl2(
    .R(in[4]),
    .S(in[5]),
    .Qn(srout[2])
  );

  srlatch srl3(
    .R(in[6]),
    .S(in[7]),
    .Qn(srout[3])
  );

  srlatch srl4(
    .R(in[8]),
    .S(in[9]),
    .Qn(srout[4])
  );

  srlatch srl5(
    .R(in[10]),
    .S(in[11]),
    .Qn(srout[5])
  );

  srlatch srl6(
    .R(in[12]),
    .S(in[13]),
    .Qn(srout[6])
  );

  srlatch srl7(
    .R(in[14]),
    .S(in[15]),
    .Qn(srout[7])
  );
  

  addrselect as(
    .addr(addr),
    .aBus(aBus),
    .enable(enable)
  );
  

  tristate8port ts8(
    .enable(enable),
    .in(srout),
    .out(out)
  );
  
endmodule