data/full_repos/permissive/193530477/source codes/STATE_CONTROL_tb.v
1: b'%Error: Cannot find file containing module: codes,data/full_repos/permissive/193530477\n        ... Looked in:\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.v\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.sv\n             codes,data/full_repos/permissive/193530477\n             codes,data/full_repos/permissive/193530477.v\n             codes,data/full_repos/permissive/193530477.sv\n             obj_dir/codes,data/full_repos/permissive/193530477\n             obj_dir/codes,data/full_repos/permissive/193530477.v\n             obj_dir/codes,data/full_repos/permissive/193530477.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/193530477/source\n%Error: Cannot find file containing module: codes/STATE_CONTROL_tb.v\n%Error: Exiting due to 3 error(s)\n'
module STATE_CONTROL_tb;

	reg clk;
	reg rst_n;
	reg [3:0] switch;
	wire[3:0] cstate;
	wire[9:0] end_addr;
	wire[9:0] start_addr;
	
	STATE_CONTROL U1(
	.clk(clk),
	.rst_n(rst_n),
	.switch(switch),
	.cstate(cstate),
	.end_addr( end_addr ),
	.start_addr( start_addr )
);
	initial begin
		clk = 1'b0;
		switch = 4'b0000;	
		rst_n = 1'b0;
		#10 rst_n = 1'b1;
	end 
	
	always 
		#10 clk = ~clk;
		
	always @ (posedge clk) begin
		if (switch <= 4'b1111)  switch <= switch + 1'b1;
		else switch = 4'd0000;
	end
endmodule
module STATE_CONTROL_tb;


	reg clk;
	reg rst_n;
	reg [3:0] switch;
	wire[3:0] cstate;
	wire[9:0] end_addr;
	wire[9:0] start_addr;
	
	STATE_CONTROL U1(
	.clk(clk),
	.rst_n(rst_n),
	.switch(switch),
	.cstate(cstate),
	.end_addr( end_addr ),
	.start_addr( start_addr )
);
	initial begin
		clk = 1'b0;
		switch = 4'b0000;	
		rst_n = 1'b0;
		#10 rst_n = 1'b1;
	end 
	
	always 
		#10 clk = ~clk;
		
	always @ (posedge clk) begin
		if (switch <= 4'b1111)  switch <= switch + 1'b1;
		else switch = 4'd0000;
	end
endmodule