data/full_repos/permissive/156129873/verilog/mem.v
1: b'%Error: data/full_repos/permissive/156129873/verilog/mem.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/156129873/verilog/mem.v:43: Define or directive not defined: \'`MEM_READ_OP\'\n      `MEM_READ_OP: begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/mem.v:43: syntax error, unexpected \':\', expecting endcase\n      `MEM_READ_OP: begin\n                  ^\n%Error: data/full_repos/permissive/156129873/verilog/mem.v:46: syntax error, unexpected \':\', expecting clocking\n      default: begin\n             ^\n%Error: Cannot continue\n'
module mem (


    input wire[1:0] memOp_i,
    input wire[15:0] data_i,
    input wire[15:0] memAddr_i,

    input wire[3:0] regAddr_wb_i,
    input wire we_i,


    input wire[15:0] data_MMU_i,



    output reg[15:0] data_wb_o,
    output reg[3:0] regAddr_wb_o,
    output reg we_o,


    output reg[1:0] memOp_o,
    output wire[15:0] ramData_o,
    output wire[15:0] ramAddr_o
);


assign ramData_o = data_i;
assign ramAddr_o = memAddr_i;


always @(*) begin
    regAddr_wb_o = regAddr_wb_i;
    we_o = we_i;
end


always @(*) begin
    memOp_o = memOp_i;
	 data_wb_o = data_i;
    case (memOp_i)
      `MEM_READ_OP: begin
          data_wb_o = data_MMU_i;
      end
      default: begin
      	
      end
    endcase
end

endmodule
module mem (


    input wire[1:0] memOp_i,
    input wire[15:0] data_i,
    input wire[15:0] memAddr_i,

    input wire[3:0] regAddr_wb_i,
    input wire we_i,


    input wire[15:0] data_MMU_i,



    output reg[15:0] data_wb_o,
    output reg[3:0] regAddr_wb_o,
    output reg we_o,


    output reg[1:0] memOp_o,
    output wire[15:0] ramData_o,
    output wire[15:0] ramAddr_o
);



assign ramData_o = data_i;
assign ramAddr_o = memAddr_i;


always @(*) begin
    regAddr_wb_o = regAddr_wb_i;
    we_o = we_i;
end


always @(*) begin
    memOp_o = memOp_i;
	 data_wb_o = data_i;
    case (memOp_i)
      `MEM_READ_OP: begin
          data_wb_o = data_MMU_i;
      end
      default: begin
      	
      end
    endcase
end

endmodule