data/full_repos/permissive/174263347/crtv10/hdl/crt_pix.v
data/verilator_xmls/20f61c47-c743-4741-87bd-d9ec44299d19.xml
module crt_pix ( clk, reset, pxclk, video_data_in, video_data_latch, black, pixel_data_out );

    input           clk, reset;
	input			pxclk;
    input   [7:0]   video_data_in;
    input           video_data_latch;
    input           black;
    
    output  [3:0]   pixel_data_out;        

    reg     [7:0]   pixel_reg;

    assign pixel_data_out =  pixel_reg[3:0];

    always @ (posedge reset or posedge clk)
        if (reset)
            pixel_reg <= 8'b0000_0000;
        else if (pxclk)
            if (video_data_latch)
                if (black)
                    pixel_reg <= 8'b0000_0000;
                else
                    pixel_reg <= video_data_in;
            else 
                if (black)
                    pixel_reg <= 8'b0000_0000;
                else
                    pixel_reg[3:0] <= pixel_reg[7:4];
endmodule
module crt_pix ( clk, reset, pxclk, video_data_in, video_data_latch, black, pixel_data_out );


    input           clk, reset;
	input			pxclk;
    input   [7:0]   video_data_in;
    input           video_data_latch;
    input           black;
    
    output  [3:0]   pixel_data_out;        

    reg     [7:0]   pixel_reg;

    assign pixel_data_out =  pixel_reg[3:0];

    always @ (posedge reset or posedge clk)
        if (reset)
            pixel_reg <= 8'b0000_0000;
        else if (pxclk)
            if (video_data_latch)
                if (black)
                    pixel_reg <= 8'b0000_0000;
                else
                    pixel_reg <= video_data_in;
            else 
                if (black)
                    pixel_reg <= 8'b0000_0000;
                else
                    pixel_reg[3:0] <= pixel_reg[7:4];
endmodule