data/full_repos/permissive/144902498/source/rtl/mux_alu_op_b.v
None: at end of input
1: b'%Error: data/full_repos/permissive/144902498/source/rtl/mux_alu_op_b.v:3: Cannot find include file: buswidth.vh\n`include "buswidth.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/144902498/source/rtl,data/full_repos/permissive/144902498/buswidth.vh\n             data/full_repos/permissive/144902498/source/rtl,data/full_repos/permissive/144902498/buswidth.vh.v\n             data/full_repos/permissive/144902498/source/rtl,data/full_repos/permissive/144902498/buswidth.vh.sv\n             buswidth.vh\n             buswidth.vh.v\n             buswidth.vh.sv\n             obj_dir/buswidth.vh\n             obj_dir/buswidth.vh.v\n             obj_dir/buswidth.vh.sv\n%Error: data/full_repos/permissive/144902498/source/rtl/mux_alu_op_b.v:6: Define or directive not defined: \'`MUX_ALU_OP_B_SEL_WIDTH\'\n    input [`MUX_ALU_OP_B_SEL_WIDTH-1:0] data_select,\n           ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module mux_alu_op_b (
    input [`MUX_ALU_OP_B_SEL_WIDTH-1:0] data_select,
    input [7:0] regfile_out_8bit_b,
    input [15:0] regfile_out_16bit_b,
    input [7:0] reg_mem_din_hi,
    input [7:0] reg_mem_din_lo,
    output reg [15:0] data_out
);

localparam MUX_ALU_OP_B_IDX_REGFILE_OUT_16BIT_B    = 0;
localparam MUX_ALU_OP_B_IDX_REG_MEM_DIN            = 1;
localparam MUX_ALU_OP_B_IDX_REG_MEM_DIN_LO_SGN_EXT = 2;
localparam MUX_ALU_OP_B_IDX_CONST2                 = 3;

always @* begin
    data_out = { 8'h00, regfile_out_8bit_b };

    if (data_select[MUX_ALU_OP_B_IDX_REGFILE_OUT_16BIT_B])
        data_out = regfile_out_16bit_b;
    if (data_select[MUX_ALU_OP_B_IDX_REG_MEM_DIN])
        data_out = { reg_mem_din_hi, reg_mem_din_lo };
    if (data_select[MUX_ALU_OP_B_IDX_REG_MEM_DIN_LO_SGN_EXT])
        data_out = { {8{reg_mem_din_lo[7]}}, reg_mem_din_lo };
    if (data_select[MUX_ALU_OP_B_IDX_CONST2])
        data_out = 16'h0002;
end

endmodule
module mux_alu_op_b (
    input [`MUX_ALU_OP_B_SEL_WIDTH-1:0] data_select,
    input [7:0] regfile_out_8bit_b,
    input [15:0] regfile_out_16bit_b,
    input [7:0] reg_mem_din_hi,
    input [7:0] reg_mem_din_lo,
    output reg [15:0] data_out
);


localparam MUX_ALU_OP_B_IDX_REGFILE_OUT_16BIT_B    = 0;
localparam MUX_ALU_OP_B_IDX_REG_MEM_DIN            = 1;
localparam MUX_ALU_OP_B_IDX_REG_MEM_DIN_LO_SGN_EXT = 2;
localparam MUX_ALU_OP_B_IDX_CONST2                 = 3;

always @* begin
    data_out = { 8'h00, regfile_out_8bit_b };

    if (data_select[MUX_ALU_OP_B_IDX_REGFILE_OUT_16BIT_B])
        data_out = regfile_out_16bit_b;
    if (data_select[MUX_ALU_OP_B_IDX_REG_MEM_DIN])
        data_out = { reg_mem_din_hi, reg_mem_din_lo };
    if (data_select[MUX_ALU_OP_B_IDX_REG_MEM_DIN_LO_SGN_EXT])
        data_out = { {8{reg_mem_din_lo[7]}}, reg_mem_din_lo };
    if (data_select[MUX_ALU_OP_B_IDX_CONST2])
        data_out = 16'h0002;
end

endmodule