data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v
'utf-8' codec can't decode byte 0xbd in position 1844: invalid start byte
1: b'%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:36: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v.v\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:44: Define or directive not defined: \'`ExceptionTypeBus\'\n input wire[`ExceptionTypeBus] if_excepttype,\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`ExceptionTypeBus] if_excepttype,\n                             ^\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:47: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] if_pc,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:49: Define or directive not defined: \'`InstBus\'\n input wire[`InstBus] if_inst,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:55: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[`RegBus] id_pc,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:55: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] id_pc,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:58: Define or directive not defined: \'`InstBus\'\n output reg[`InstBus] id_inst,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:61: Define or directive not defined: \'`ExceptionTypeBus\'\n output reg[`ExceptionTypeBus] id_excepttype,\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:66: Define or directive not defined: \'`RstEnable\'\n  if (rst_n == `RstEnable)\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:68: Define or directive not defined: \'`ZeroWord\'\n   id_pc <= `ZeroWord;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:69: Define or directive not defined: \'`ZeroWord\'\n   id_inst <= `ZeroWord;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:70: Define or directive not defined: \'`False_v\'\n   id_not_stall <= `False_v;\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:74: Define or directive not defined: \'`ChipDisable\'\n  else if(if_inst_ce == `ChipDisable)\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:76: Define or directive not defined: \'`ZeroWord\'\n   id_pc <= `ZeroWord;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:77: Define or directive not defined: \'`ZeroWord\'\n   id_inst <= `ZeroWord;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:78: Define or directive not defined: \'`False_v\'\n   id_not_stall <= `False_v;\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:82: Define or directive not defined: \'`Flush\'\n  else if(flush == `Flush)\n                   ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:84: Define or directive not defined: \'`ZeroWord\'\n   id_pc <= `ZeroWord;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:85: Define or directive not defined: \'`ZeroWord\'\n   id_inst <= `ZeroWord;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:86: Define or directive not defined: \'`False_v\'\n   id_not_stall <= `False_v;\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:90: Define or directive not defined: \'`Stop\'\n  else if(stall[1] == `Stop && stall[2] == `NoStop)\n                      ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:90: Define or directive not defined: \'`NoStop\'\n  else if(stall[1] == `Stop && stall[2] == `NoStop)\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:95: Define or directive not defined: \'`ZeroWord\'\n   id_pc <= `ZeroWord;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:96: Define or directive not defined: \'`ZeroWord\'\n   id_inst <= `ZeroWord;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:97: Define or directive not defined: \'`False_v\'\n   id_not_stall <= `False_v;\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:101: Define or directive not defined: \'`NoStop\'\n  else if(stall[1] == `NoStop)\n                      ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/if_id.v:105: Define or directive not defined: \'`True_v\'\n   id_not_stall <= `True_v;\n                   ^~~~~~~\n%Error: Exiting due to 28 error(s)\n'
module if_id(

	input wire clk,
	input wire rst_n,
	input wire[5:0] stall,	
	input wire flush,
	input wire[`ExceptionTypeBus] if_excepttype,


	input wire[`RegBus] if_pc,

	input wire[`InstBus] if_inst,

	input wire if_inst_ce,
	
	

	output reg[`RegBus] id_pc,
	

	output reg[`InstBus] id_inst,


	output reg[`ExceptionTypeBus] id_excepttype,

	output reg id_not_stall
);
	always @ (posedge clk or negedge rst_n) begin
		if (rst_n == `RstEnable)
		begin
			id_pc <= `ZeroWord;
			id_inst <= `ZeroWord;
			id_not_stall <= `False_v;

			id_excepttype <= 32'b0;
		end
		else if(if_inst_ce == `ChipDisable)
		begin
			id_pc <= `ZeroWord;
			id_inst <= `ZeroWord;
			id_not_stall <= `False_v;

			id_excepttype <= 32'b0;
		end
		else if(flush == `Flush)
		begin
			id_pc <= `ZeroWord;
			id_inst <= `ZeroWord;
			id_not_stall <= `False_v;

			id_excepttype <= 32'b0;
		end
		else if(stall[1] == `Stop && stall[2] == `NoStop)
		begin
			$display("should never arrive here");
			$stop;

			id_pc <= `ZeroWord;
			id_inst <= `ZeroWord;
			id_not_stall <= `False_v;

			id_excepttype <= 32'b0;
		end
		else if(stall[1] == `NoStop)
		begin
			id_pc <= if_pc;
			id_inst <= if_inst;
			id_not_stall <= `True_v;

			id_excepttype <= if_excepttype;
		end
	end

endmodule
module if_id(

	input wire clk,
	input wire rst_n,
	input wire[5:0] stall,	
	input wire flush,
	input wire[`ExceptionTypeBus] if_excepttype,


	input wire[`RegBus] if_pc,

	input wire[`InstBus] if_inst,

	input wire if_inst_ce,
	
	

	output reg[`RegBus] id_pc,
	

	output reg[`InstBus] id_inst,


	output reg[`ExceptionTypeBus] id_excepttype,

	output reg id_not_stall
);

	always @ (posedge clk or negedge rst_n) begin
		if (rst_n == `RstEnable)
		begin
			id_pc <= `ZeroWord;
			id_inst <= `ZeroWord;
			id_not_stall <= `False_v;

			id_excepttype <= 32'b0;
		end
		else if(if_inst_ce == `ChipDisable)
		begin
			id_pc <= `ZeroWord;
			id_inst <= `ZeroWord;
			id_not_stall <= `False_v;

			id_excepttype <= 32'b0;
		end
		else if(flush == `Flush)
		begin
			id_pc <= `ZeroWord;
			id_inst <= `ZeroWord;
			id_not_stall <= `False_v;

			id_excepttype <= 32'b0;
		end
		else if(stall[1] == `Stop && stall[2] == `NoStop)
		begin
			$display("should never arrive here");
			$stop;

			id_pc <= `ZeroWord;
			id_inst <= `ZeroWord;
			id_not_stall <= `False_v;

			id_excepttype <= 32'b0;
		end
		else if(stall[1] == `NoStop)
		begin
			id_pc <= if_pc;
			id_inst <= if_inst;
			id_not_stall <= `True_v;

			id_excepttype <= if_excepttype;
		end
	end

endmodule