data/full_repos/permissive/168753118/rtl/modules/LSU.v
data/verilator_xmls/80fd6959-c828-4cd5-97c9-1b93596671c8.xml
module LSU
  #(parameter XLEN=32) (
  input lsu_enable_in,
  input [3:0] lsu_uop_in,
  input [XLEN-1:0] lsu_a_data_in,
  input [XLEN-1:0] lsu_b_data_in,
  input [XLEN-1:0] lsu_c_data_in,
  input [XLEN-1:0] lsu_mem_data_in,
  output reg [3:0] lsu_mem_op_out,
  output reg [XLEN-1:0] lsu_result_out,
  output reg [XLEN-1:0] lsu_mem_data_out,
  output reg [XLEN-1:0] lsu_mem_addr_out
);




reg [XLEN-1:0] lsu_effective_addr_reg;



always @ ( * ) begin

  if (lsu_enable_in == 1'b1) begin


    lsu_effective_addr_reg = lsu_b_data_in + lsu_c_data_in;


    if (lsu_uop_in[3] == 1'b0) begin


      lsu_mem_addr_out = lsu_effective_addr_reg;
      lsu_mem_op_out = lsu_uop_in;


      if(lsu_uop_in[1:0] == 2'b01)


        if(lsu_uop_in[2] == 1'b0)
          lsu_result_out = {{24{lsu_mem_data_in[7]}}, lsu_mem_data_in[7:0]};


        else
          lsu_result_out = {{24{1'b0}}, lsu_mem_data_in[7:0]};


      else if(lsu_uop_in[1:0] == 2'b10)


        if(lsu_uop_in[2] == 1'b0)
          lsu_result_out = {{16{lsu_mem_data_in[15]}}, lsu_mem_data_in[15:0]};


        else
          lsu_result_out = {{16{1'b0}}, lsu_mem_data_in[15:0]};


      else
        lsu_result_out = lsu_mem_data_in;


    end else begin


      lsu_mem_addr_out = lsu_effective_addr_reg;
      lsu_mem_op_out = lsu_uop_in;


      lsu_mem_data_out = lsu_a_data_in;

    end
  end
end

endmodule
module LSU
  #(parameter XLEN=32) (
  input lsu_enable_in,
  input [3:0] lsu_uop_in,
  input [XLEN-1:0] lsu_a_data_in,
  input [XLEN-1:0] lsu_b_data_in,
  input [XLEN-1:0] lsu_c_data_in,
  input [XLEN-1:0] lsu_mem_data_in,
  output reg [3:0] lsu_mem_op_out,
  output reg [XLEN-1:0] lsu_result_out,
  output reg [XLEN-1:0] lsu_mem_data_out,
  output reg [XLEN-1:0] lsu_mem_addr_out
);





reg [XLEN-1:0] lsu_effective_addr_reg;



always @ ( * ) begin

  if (lsu_enable_in == 1'b1) begin


    lsu_effective_addr_reg = lsu_b_data_in + lsu_c_data_in;


    if (lsu_uop_in[3] == 1'b0) begin


      lsu_mem_addr_out = lsu_effective_addr_reg;
      lsu_mem_op_out = lsu_uop_in;


      if(lsu_uop_in[1:0] == 2'b01)


        if(lsu_uop_in[2] == 1'b0)
          lsu_result_out = {{24{lsu_mem_data_in[7]}}, lsu_mem_data_in[7:0]};


        else
          lsu_result_out = {{24{1'b0}}, lsu_mem_data_in[7:0]};


      else if(lsu_uop_in[1:0] == 2'b10)


        if(lsu_uop_in[2] == 1'b0)
          lsu_result_out = {{16{lsu_mem_data_in[15]}}, lsu_mem_data_in[15:0]};


        else
          lsu_result_out = {{16{1'b0}}, lsu_mem_data_in[15:0]};


      else
        lsu_result_out = lsu_mem_data_in;


    end else begin


      lsu_mem_addr_out = lsu_effective_addr_reg;
      lsu_mem_op_out = lsu_uop_in;


      lsu_mem_data_out = lsu_a_data_in;

    end
  end
end

endmodule