data/full_repos/permissive/214823094/lab_6/project_2/project_2.srcs/sources_1/new/traffic_lights_2.v
data/verilator_xmls/4e60f4d5-05cb-41f5-84ae-4a8cd8665f26.xml
module FSM(
    input TS,
    input TL,
    input C,
    output reg ST,
    output reg [2:0] H,
    output reg [2:0] F
    );
    
    always@(posedge TS,posedge TL,posedge C)
    begin
        if(~(TL&C))
        begin
        H<=3'b001;
        F<=3'b100;
        ST<=ST;
        end
        else
            if(TL&C)
            begin
            ST<=0;
            H<=3'b010;
            F<=3'b100;
            end
            else
            if(~TS)
            begin
            H<=H;
            F<=F;
            end
            else
        if(~(TL|~C))
        begin
        H<=3'b100;
        F<=3'b001;
        end
        else
        if(TS)
        begin
            if(H==3'b010)
            begin
            H<=3'b100;
            F<=3'b001;
            ST<=ST;
            end
            else
            if(F==3'b010)
            begin
            H<=3'b001;
            F<=3'b100;
            ST<=ST;
            end
        end
        else
            if(~(TL|(~C)))
            begin
            F<=F;
            H<=H;
            end
    end
    
endmodule
module FSM(
    input TS,
    input TL,
    input C,
    output reg ST,
    output reg [2:0] H,
    output reg [2:0] F
    );

    
    always@(posedge TS,posedge TL,posedge C)
    begin
        if(~(TL&C))
        begin
        H<=3'b001;
        F<=3'b100;
        ST<=ST;
        end
        else
            if(TL&C)
            begin
            ST<=0;
            H<=3'b010;
            F<=3'b100;
            end
            else
            if(~TS)
            begin
            H<=H;
            F<=F;
            end
            else
        if(~(TL|~C))
        begin
        H<=3'b100;
        F<=3'b001;
        end
        else
        if(TS)
        begin
            if(H==3'b010)
            begin
            H<=3'b100;
            F<=3'b001;
            ST<=ST;
            end
            else
            if(F==3'b010)
            begin
            H<=3'b001;
            F<=3'b100;
            ST<=ST;
            end
        end
        else
            if(~(TL|(~C)))
            begin
            F<=F;
            H<=H;
            end
    end
    
endmodule