data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/stimulus/textbench.v
 line:15: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/stimulus/textbench.v:9: Unsupported: Ignoring delay on this delayed statement.\nalways#(DELY/2)clk=~clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/stimulus/textbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #(DELY*2) reset=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/stimulus/textbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #DELY reset=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/stimulus/textbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #(DELY*500000) $finish;\n  ^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/stimulus/textbench.v:8: Cannot find file containing module: \'XYF\'\nXYF u1(.Red1(red1),.Red2(red2),.Reset(reset),.Clk(clk),.Green1(green1),.Green2(green2),.Yellow1(yellow1),.Yellow2(yellow2),.Seg(seg),.Sl(sl));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/stimulus,data/full_repos/permissive/165160692/XYF\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/stimulus,data/full_repos/permissive/165160692/XYF.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/stimulus,data/full_repos/permissive/165160692/XYF.sv\n             XYF\n             XYF.v\n             XYF.sv\n             obj_dir/XYF\n             obj_dir/XYF.v\n             obj_dir/XYF.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
reg clk,reset;
wire[7:0]seg;
wire[3:0]sl;
wire red1,green1,yellow1,red2,green2,yellow2;
parameter DELY=20;
XYF u1(.Red1(red1),.Red2(red2),.Reset(reset),.Clk(clk),.Green1(green1),.Green2(green2),.Yellow1(yellow1),.Yellow2(yellow2),.Seg(seg),.Sl(sl));
always#(DELY/2)clk=~clk;
initial
 begin
  clk=0;reset=0;
  #(DELY*2) reset=1;
  #DELY reset=0;
  #(DELY*500000) $finish;
 end
endmodule
module testbench;

reg clk,reset;
wire[7:0]seg;
wire[3:0]sl;
wire red1,green1,yellow1,red2,green2,yellow2;
parameter DELY=20;
XYF u1(.Red1(red1),.Red2(red2),.Reset(reset),.Clk(clk),.Green1(green1),.Green2(green2),.Yellow1(yellow1),.Yellow2(yellow2),.Seg(seg),.Sl(sl));
always#(DELY/2)clk=~clk;
initial
 begin
  clk=0;reset=0;
  #(DELY*2) reset=1;
  #DELY reset=0;
  #(DELY*500000) $finish;
 end
endmodule