data/full_repos/permissive/197356760/SerialAdder/filip-flop.v
data/verilator_xmls/6008f72b-b796-4dad-b53e-0405afd964a4.xml
module filipflop(data_in,data_out,clk);

	input  data_in,clk;  
	output reg  data_out; 

	always @ (posedge clk) 
		data_out=data_in;
	

endmodule
module filipflop(data_in,data_out,clk);


	input  data_in,clk;  
	output reg  data_out; 

	always @ (posedge clk) 
		data_out=data_in;
	

endmodule