data/full_repos/permissive/206169433/single cycle/im.v
1: b'%Error: Cannot find file containing module: cycle,data/full_repos/permissive/206169433\n        ... Looked in:\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433.v\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433.sv\n             cycle,data/full_repos/permissive/206169433\n             cycle,data/full_repos/permissive/206169433.v\n             cycle,data/full_repos/permissive/206169433.sv\n             obj_dir/cycle,data/full_repos/permissive/206169433\n             obj_dir/cycle,data/full_repos/permissive/206169433.v\n             obj_dir/cycle,data/full_repos/permissive/206169433.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/206169433/single\n%Error: Cannot find file containing module: cycle/im.v\n%Error: Exiting due to 3 error(s)\n'
module im(
    PC, instruction    
    );
    parameter       size = 100;
    input            [31:0]PC;
    output           [31:0]instruction;
    reg              [31:0]memory[size-1:0];
    reg              [31:0]instruction;

    initial 
    begin
    memory[0] = 32'b00100000000010000000000000100000;
            memory[1] = 32'b00100000000010010000000000110111;
            memory[2] = 32'b00000001000010011000000000100100;
            memory[3] = 32'b00000001000010011000000000100101;
            memory[4] = 32'b10101100000100000000000000000100;
            memory[5] = 32'b10101100000010000000000000001000;
            memory[6] = 32'b00000001000010011000100000100000;
            memory[7] = 32'b00000001000010011001000000100010;
            memory[8] = 32'b00010010001100100000000000001001;
            memory[9] = 32'b10001100000100010000000000000100;
            memory[10]= 32'b00110010001100100000000001001000;
            memory[11] =32'b00010010001100100000000000001001;
            memory[12] =32'b10001100000100110000000000001000;
            memory[13] =32'b00010010000100110000000000001010;
            memory[14] =32'b00000010010100011010000000101010;
            memory[15] =32'b00010010100000000000000000001111;
            memory[16] =32'b00000010001000001001000000100000;
            memory[17] =32'b00001000000000000000000000001110;
            memory[18] =32'b00100000000010000000000000000000;
            memory[19] =32'b00100000000010010000000000000000;
            memory[20] =32'b00001000000000000000000000011111;
            memory[21] =32'b00100000000010000000000000000001;
            memory[22] =32'b00100000000010010000000000000001;
            memory[23] =32'b00001000000000000000000000011111;
            memory[24] =32'b00100000000010000000000000000010;
            memory[25] =32'b00100000000010010000000000000010;
            memory[26] =32'b00001000000000000000000000011111;
            memory[27] =32'b00100000000010000000000000000011;
            memory[28] =32'b00100000000010010000000000000011;
            memory[29] =32'b00001000000000000000000000011111;


    end
always @(PC)
      instruction = memory[PC>>2];
endmodule
module im(
    PC, instruction    
    );

    parameter       size = 100;
    input            [31:0]PC;
    output           [31:0]instruction;
    reg              [31:0]memory[size-1:0];
    reg              [31:0]instruction;

    initial 
    begin
    memory[0] = 32'b00100000000010000000000000100000;
            memory[1] = 32'b00100000000010010000000000110111;
            memory[2] = 32'b00000001000010011000000000100100;
            memory[3] = 32'b00000001000010011000000000100101;
            memory[4] = 32'b10101100000100000000000000000100;
            memory[5] = 32'b10101100000010000000000000001000;
            memory[6] = 32'b00000001000010011000100000100000;
            memory[7] = 32'b00000001000010011001000000100010;
            memory[8] = 32'b00010010001100100000000000001001;
            memory[9] = 32'b10001100000100010000000000000100;
            memory[10]= 32'b00110010001100100000000001001000;
            memory[11] =32'b00010010001100100000000000001001;
            memory[12] =32'b10001100000100110000000000001000;
            memory[13] =32'b00010010000100110000000000001010;
            memory[14] =32'b00000010010100011010000000101010;
            memory[15] =32'b00010010100000000000000000001111;
            memory[16] =32'b00000010001000001001000000100000;
            memory[17] =32'b00001000000000000000000000001110;
            memory[18] =32'b00100000000010000000000000000000;
            memory[19] =32'b00100000000010010000000000000000;
            memory[20] =32'b00001000000000000000000000011111;
            memory[21] =32'b00100000000010000000000000000001;
            memory[22] =32'b00100000000010010000000000000001;
            memory[23] =32'b00001000000000000000000000011111;
            memory[24] =32'b00100000000010000000000000000010;
            memory[25] =32'b00100000000010010000000000000010;
            memory[26] =32'b00001000000000000000000000011111;
            memory[27] =32'b00100000000010000000000000000011;
            memory[28] =32'b00100000000010010000000000000011;
            memory[29] =32'b00001000000000000000000000011111;


    end
always @(PC)
      instruction = memory[PC>>2];
endmodule