data/full_repos/permissive/108561032/control2.v
None: at end of input
data/verilator_xmls/9e4e4389-12dd-489a-9dc8-dc42b43729ce.xml
module control2(reset,Control,clk,SaltoCond,EscrMem,Controls2,LeerMem);

    input wire [9:0] Control;
    input clk;
    output reg [9:0] Controls2;
    input reset;
 

    output reg SaltoCond;
    output reg LeerMem;


    output reg EscrMem;



   
   wire SaltoConda;
	

assign SaltoConda = 1'b0;


always   @(posedge clk)
begin

    if (Control[2] == 1'b1)
        begin
        SaltoCond = 1'b1;

        end
     else
        SaltoCond=SaltoConda;
end

always   @(posedge clk)
begin
Controls2 = Control;






EscrMem      = Control[3];


LeerMem      = Control[4];
end     
endmodule
module control2(reset,Control,clk,SaltoCond,EscrMem,Controls2,LeerMem);


    input wire [9:0] Control;
    input clk;
    output reg [9:0] Controls2;
    input reset;
 

    output reg SaltoCond;
    output reg LeerMem;


    output reg EscrMem;



   
   wire SaltoConda;
	

assign SaltoConda = 1'b0;


always   @(posedge clk)
begin

    if (Control[2] == 1'b1)
        begin
        SaltoCond = 1'b1;

        end
     else
        SaltoCond=SaltoConda;
end

always   @(posedge clk)
begin
Controls2 = Control;






EscrMem      = Control[3];


LeerMem      = Control[4];
end     
endmodule