data/full_repos/permissive/209997548/testbench/TB_PRIME_ROM.sv
 line:61: before: "/"
1: b'%Warning-STMTDLY: data/full_repos/permissive/209997548/testbench/TB_PRIME_ROM.sv:40: Unsupported: Ignoring delay on this delayed statement.\n    #(ClkCyc);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/209997548/testbench/TB_PRIME_ROM.sv:42: Unsupported: Ignoring delay on this delayed statement.\n    #(ClkCyc);\n    ^\n%Error: data/full_repos/permissive/209997548/testbench/TB_PRIME_ROM.sv:55: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_PRIME_ROM ;


logic           CLK;


logic [10:0]    ADDRESS;
logic [15:0]    DATA;


parameter ClkCyc = 20;


PRIME_ROM U_PRIME_ROM (
    CLK,
    ADDRESS,
    DATA
);


always begin
    CLK <= 1'b0;
    #(ClkCyc);
    CLK <= 1'b1;
    #(ClkCyc);
end


initial begin
    ADDRESS <= 16'd0;


    while (ADDRESS !== 1227) begin
        @(posedge CLK);
        ADDRESS <= ADDRESS + 16'd1;
    end
    $finish;
end

endmodule
module TB_PRIME_ROM ;



logic           CLK;


logic [10:0]    ADDRESS;
logic [15:0]    DATA;


parameter ClkCyc = 20;


PRIME_ROM U_PRIME_ROM (
    CLK,
    ADDRESS,
    DATA
);


always begin
    CLK <= 1'b0;
    #(ClkCyc);
    CLK <= 1'b1;
    #(ClkCyc);
end


initial begin
    ADDRESS <= 16'd0;


    while (ADDRESS !== 1227) begin
        @(posedge CLK);
        ADDRESS <= ADDRESS + 16'd1;
    end
    $finish;
end

endmodule