data/full_repos/permissive/167489907/Memory/ROM/ROM_64bit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/167489907/Memory/ROM/ROM_64bit.v:26: Operator ADD expects 5 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                              : ... In instance ROM_64bit\n assign word_address1 = address[ADDR_WIDTH-1:3] + 3\'d1;\n                                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/167489907/Memory/ROM/ROM_64bit.v:45: Operator AND expects 128 bits on the RHS, but RHS\'s VARREF \'mask\' generates 64 bits.\n                                                                              : ... In instance ROM_64bit\n assign data = ({data1, data0} >> {address[2:0], 3\'b000}) & mask;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/167489907/Memory/ROM/ROM_64bit.v:45: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s AND generates 128 bits.\n                                                                              : ... In instance ROM_64bit\n assign data = ({data1, data0} >> {address[2:0], 3\'b000}) & mask;\n             ^\n%Error: Exiting due to 3 warning(s)\n'
module ROM_64bit(data, address, clock, size);
	parameter ADDR_WIDTH = 8;
	parameter WORD_DEPTH = 1 << (ADDR_WIDTH-3);
	output [63:0] data; 
	input [ADDR_WIDTH-1:0] address;
	input clock;
	input [1:0] size;
	

	reg [63:0] rom_array [0:WORD_DEPTH-1];
	
	initial begin






		$readmemh("D:/Dropbox/RowanTeaching/CompArch/Quartus/LEGv8/test_memory_hex_file.mem", rom_array);
	end
	

	wire [ADDR_WIDTH-4:0] word_address0, word_address1;
	reg [63:0] data0, data1;
	assign word_address0 = address[ADDR_WIDTH-1:3];
	assign word_address1 = address[ADDR_WIDTH-1:3] + 3'd1;
	
	always @(posedge clock) begin
		data0 <= rom_array[word_address0];
		data1 <= rom_array[word_address1];
	end


	reg [63:0] mask;
	always @(*) begin
		case(size)
			2'b00: mask <= 64'h00000000000000FF;
			2'b01: mask <= 64'h000000000000FFFF;
			2'b10: mask <= 64'h00000000FFFFFFFF;
			2'b11: mask <= 64'hFFFFFFFFFFFFFFFF;
		endcase
	end
		

	assign data = ({data1, data0} >> {address[2:0], 3'b000}) & mask;
endmodule
module ROM_64bit(data, address, clock, size);

	parameter ADDR_WIDTH = 8;
	parameter WORD_DEPTH = 1 << (ADDR_WIDTH-3);
	output [63:0] data; 
	input [ADDR_WIDTH-1:0] address;
	input clock;
	input [1:0] size;
	

	reg [63:0] rom_array [0:WORD_DEPTH-1];
	
	initial begin






		$readmemh("D:/Dropbox/RowanTeaching/CompArch/Quartus/LEGv8/test_memory_hex_file.mem", rom_array);
	end
	

	wire [ADDR_WIDTH-4:0] word_address0, word_address1;
	reg [63:0] data0, data1;
	assign word_address0 = address[ADDR_WIDTH-1:3];
	assign word_address1 = address[ADDR_WIDTH-1:3] + 3'd1;
	
	always @(posedge clock) begin
		data0 <= rom_array[word_address0];
		data1 <= rom_array[word_address1];
	end


	reg [63:0] mask;
	always @(*) begin
		case(size)
			2'b00: mask <= 64'h00000000000000FF;
			2'b01: mask <= 64'h000000000000FFFF;
			2'b10: mask <= 64'h00000000FFFFFFFF;
			2'b11: mask <= 64'hFFFFFFFFFFFFFFFF;
		endcase
	end
		

	assign data = ({data1, data0} >> {address[2:0], 3'b000}) & mask;
endmodule