data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v
1: b'%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:2: Cannot find include file: ../../utils/test.v\n`include "../../utils/test.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165846232/components/UpDownCounter,data/full_repos/permissive/165846232/../../utils/test.v\n             data/full_repos/permissive/165846232/components/UpDownCounter,data/full_repos/permissive/165846232/../../utils/test.v.v\n             data/full_repos/permissive/165846232/components/UpDownCounter,data/full_repos/permissive/165846232/../../utils/test.v.sv\n             ../../utils/test.v\n             ../../utils/test.v.v\n             ../../utils/test.v.sv\n             obj_dir/../../utils/test.v\n             obj_dir/../../utils/test.v.v\n             obj_dir/../../utils/test.v.sv\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:3: Cannot find include file: ./UpDownCounter.v\n`include "./UpDownCounter.v"        \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:29: Define or directive not defined: \'`defClock\'\n    `defClock(Clk, 2);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:29: syntax error, unexpected \'(\'\n    `defClock(Clk, 2);\n              ^~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:52: Define or directive not defined: \'`startTest\'\n `startTest("UpDownCounter")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:52: syntax error, unexpected \'(\'\n `startTest("UpDownCounter")\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:59: Define or directive not defined: \'`describe\'\n        `describe("Test basic up counting");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:62: Define or directive not defined: \'`assert\'\n            #10; `assert(Output, 5);\n                 ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:64: Define or directive not defined: \'`describe\'\n        `describe("Test basic down counting");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:66: Define or directive not defined: \'`assert\'\n            #6; `assert(Output, 2);\n                ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:68: Define or directive not defined: \'`assert\'\n            #20; `assert(Output, 0);\n                 ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:70: Define or directive not defined: \'`describe\'\n        `describe("Test overflow prevention");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:72: Define or directive not defined: \'`assert\'\n            #254; `assert(Output, 128);\n                  ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:74: Define or directive not defined: \'`assert\'\n            #(2 ** 9); `assert(Output, 2 ** 8 - 1);\n                       ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:76: Define or directive not defined: \'`describe\'\n        `describe("Test counter reset");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:79: Define or directive not defined: \'`assert\'\n            `assert(Output, 0);\n            ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/UpDownCounter/TestUpDownCounter.v:81: Define or directive not defined: \'`endTest\'\n    `endTest    \n    ^~~~~~~~\n%Error: Exiting due to 17 error(s)\n'
module TestUpDownCounter
#(
    parameter INPUT_BIT_WIDTH = 8
);


    `defClock(Clk, 2);
    reg Reset;
    reg UpDownMode;
    

    wire [INPUT_BIT_WIDTH-1:0] Output;
    wire LimitReachedFlag;


	UpDownCounter #(
        .INPUT_BIT_WIDTH(INPUT_BIT_WIDTH)
    ) uut(
		.Clk(Clk),
        .ClkEnable(1'b1),
        .Reset(Reset),
        .Stop(1'b0),
        .UpDownMode(UpDownMode),
        .Output(Output),
        .LimitReachedFlag(LimitReachedFlag)
	);
    
    integer i;
    
	`startTest("UpDownCounter")

        Reset      = 1;
        Clk        = 0;
        UpDownMode = 1;
        #100;
        
        `describe("Test basic up counting");
            `countUp;
            `runReset;
            #10; `assert(Output, 5);
        
        `describe("Test basic down counting");
            `countDown;
            #6; `assert(Output, 2);
        
            #20; `assert(Output, 0);
            
        `describe("Test overflow prevention");
            `countUp;
            #254; `assert(Output, 128);
            
            #(2 ** 9); `assert(Output, 2 ** 8 - 1);
        
        `describe("Test counter reset");
            Reset = 1;
            #2;
            `assert(Output, 0);
    
    `endTest    
    
      
endmodule
module TestUpDownCounter
#(
    parameter INPUT_BIT_WIDTH = 8
);



    `defClock(Clk, 2);
    reg Reset;
    reg UpDownMode;
    

    wire [INPUT_BIT_WIDTH-1:0] Output;
    wire LimitReachedFlag;


	UpDownCounter #(
        .INPUT_BIT_WIDTH(INPUT_BIT_WIDTH)
    ) uut(
		.Clk(Clk),
        .ClkEnable(1'b1),
        .Reset(Reset),
        .Stop(1'b0),
        .UpDownMode(UpDownMode),
        .Output(Output),
        .LimitReachedFlag(LimitReachedFlag)
	);
    
    integer i;
    
	`startTest("UpDownCounter")

        Reset      = 1;
        Clk        = 0;
        UpDownMode = 1;
        #100;
        
        `describe("Test basic up counting");
            `countUp;
            `runReset;
            #10; `assert(Output, 5);
        
        `describe("Test basic down counting");
            `countDown;
            #6; `assert(Output, 2);
        
            #20; `assert(Output, 0);
            
        `describe("Test overflow prevention");
            `countUp;
            #254; `assert(Output, 128);
            
            #(2 ** 9); `assert(Output, 2 ** 8 - 1);
        
        `describe("Test counter reset");
            Reset = 1;
            #2;
            `assert(Output, 0);
    
    `endTest    
    
      
endmodule