data/full_repos/permissive/139213403/FPGA/mod_m_counter_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/mod_m_counter_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/mod_m_counter_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/mod_m_counter_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/mod_m_counter_testbench.v:35: syntax error, unexpected \'@\'\n  @(negedge reset);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/mod_m_counter_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/mod_m_counter_testbench.v:40: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/mod_m_counter_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Error: data/full_repos/permissive/139213403/FPGA/mod_m_counter_testbench.v:44: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/mod_m_counter_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #2000;  \n  ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mod_m_counter_testbench;

localparam T = 20,
           M_BITS = 8;

reg clk, reset;
reg [M_BITS-1:0] m;
wire max_tick;
wire [M_BITS-1:0] q;

mod_m_counter #(.M_BITS(M_BITS)) uut(.clk(clk), .reset(reset), .m(m), .max_tick(max_tick), .q(q));


always
	begin
		clk = 1'b1;
		#(T / 2);
		clk = 1'b0;
		#(T / 2);
	end


initial
	begin
		reset = 1'b1;
		#(T / 2);
		reset = 1'b0;
	end
	

initial
	begin
		@(negedge reset);
		@(negedge clk);
		
		m = 16;
		#2000;
		@(negedge clk);
		
		m = 163;
		#2000;
		@(negedge clk);
		
		#2000;		
		$stop;
	end
	
endmodule
module mod_m_counter_testbench;


localparam T = 20,
           M_BITS = 8;

reg clk, reset;
reg [M_BITS-1:0] m;
wire max_tick;
wire [M_BITS-1:0] q;

mod_m_counter #(.M_BITS(M_BITS)) uut(.clk(clk), .reset(reset), .m(m), .max_tick(max_tick), .q(q));


always
	begin
		clk = 1'b1;
		#(T / 2);
		clk = 1'b0;
		#(T / 2);
	end


initial
	begin
		reset = 1'b1;
		#(T / 2);
		reset = 1'b0;
	end
	

initial
	begin
		@(negedge reset);
		@(negedge clk);
		
		m = 16;
		#2000;
		@(negedge clk);
		
		m = 163;
		#2000;
		@(negedge clk);
		
		#2000;		
		$stop;
	end
	
endmodule