data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'block_ram_sp\'\nmodule  block_ram_sp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'block_ram_dp\'\nmodule  block_ram_dp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'dist_ram_dp\'\nmodule  dist_ram_dp(\n        ^~~~~~~~~~~\n                                                                                             : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n                                                                                          : ... In instance per_dp2_0_r\n  counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n                                             ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module mem_stage_dp2_r(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,                        
out_start,                       
clk,                             
counter_in,                             
rst                              
);                               
  parameter DATA_WIDTH = 8;                                
  input in_start, clk, rst;                   
  input [5-1:0] counter_in;        
  input [DATA_WIDTH-1:0] inData_0,
      inData_1;
  output reg [DATA_WIDTH-1:0] outData_0,
      outData_1;
  output reg out_start; 
  
  wire [DATA_WIDTH-1:0] wire_in [1:0];              
  wire [DATA_WIDTH-1:0] wire_out [1:0];              
  
  wire wen_wire;              
  wire out_start_wire;              
  assign wire_in[0] = inData_0;    
  assign wire_in[1] = inData_1;    
  
  wire [4:0] addr_wire_0;        

  wire [4:0] addr_wire_1;        

  mem_addr_ctrl_dp2_per0 addr_gen_inst(.in_start(in_start), .counter_in(counter_in), .wen_out(wen_wire), .out_start(out_start_wire), .mem_addr_out_0(addr_wire_0), .mem_addr_out_1(addr_wire_1), .clk(clk), .rst(rst));

  dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(5)) 
         ram_inst_0(.wen(wen_wire), .addr(addr_wire_0), .din(wire_in[0]), .dout(wire_out[0]), .clk(clk) );

  dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(5)) 
         ram_inst_1(.wen(wen_wire), .addr(addr_wire_1), .din(wire_in[1]), .dout(wire_out[1]), .clk(clk) );

  
  always@(posedge clk)             
  begin                            
    if(rst) begin                    
      outData_0 <= 0;    
      outData_1 <= 0;    
      out_start <= 1'b0;              
      end
    else begin                        
      outData_0 <= wire_out[0];    
      outData_1 <= wire_out[1];    
      out_start <= out_start_wire;    
      end
  end                              

endmodule
module mem_stage_dp2_r(
inData_0,
inData_1,
outData_0,
outData_1,
in_start,                        
out_start,                       
clk,                             
counter_in,                             
rst                              
);
                               
  parameter DATA_WIDTH = 8;                                
  input in_start, clk, rst;                   
  input [5-1:0] counter_in;        
  input [DATA_WIDTH-1:0] inData_0,
      inData_1;
  output reg [DATA_WIDTH-1:0] outData_0,
      outData_1;
  output reg out_start; 
  
  wire [DATA_WIDTH-1:0] wire_in [1:0];              
  wire [DATA_WIDTH-1:0] wire_out [1:0];              
  
  wire wen_wire;              
  wire out_start_wire;              
  assign wire_in[0] = inData_0;    
  assign wire_in[1] = inData_1;    
  
  wire [4:0] addr_wire_0;        

  wire [4:0] addr_wire_1;        

  mem_addr_ctrl_dp2_per0 addr_gen_inst(.in_start(in_start), .counter_in(counter_in), .wen_out(wen_wire), .out_start(out_start_wire), .mem_addr_out_0(addr_wire_0), .mem_addr_out_1(addr_wire_1), .clk(clk), .rst(rst));

  dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(5)) 
         ram_inst_0(.wen(wen_wire), .addr(addr_wire_0), .din(wire_in[0]), .dout(wire_out[0]), .clk(clk) );

  dist_ram_sp #(.DATA_WIDTH(8), .ADDR_WIDTH(5)) 
         ram_inst_1(.wen(wen_wire), .addr(addr_wire_1), .din(wire_in[1]), .dout(wire_out[1]), .clk(clk) );

  
  always@(posedge clk)             
  begin                            
    if(rst) begin                    
      outData_0 <= 0;    
      outData_1 <= 0;    
      out_start <= 1'b0;              
      end
    else begin                        
      outData_0 <= wire_out[0];    
      outData_1 <= wire_out[1];    
      out_start <= out_start_wire;    
      end
  end                              

endmodule