data/full_repos/permissive/210737016/wam_dis.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/210737016/wam_dis.v:41: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'wam_led\'\nmodule wam_led (             \n       ^~~~~~~\n                                                                    : ... Top module \'wam_lst\'\nmodule wam_lst (             \n       ^~~~~~~\n                                                                    : ... Top module \'wam_dis\'\nmodule wam_dis(              \n       ^~~~~~~\n%Error: data/full_repos/permissive/210737016/wam_dis.v:54: Cannot find file containing module: \'wam_tch\'\n    wam_tch tchc( .clk_19(clk_19), .btn(cout0), .tch(cout0s));\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_tch\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_tch.v\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_tch.sv\n             wam_tch\n             wam_tch.v\n             wam_tch.sv\n             obj_dir/wam_tch\n             obj_dir/wam_tch.v\n             obj_dir/wam_tch.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module wam_dis(
    input clk_16,
    input wire  [3:0]  hrdn,
    input wire  [11:0] score,
    input wire  lstn,
    output reg  [3:0]  an,
    output wire [6:0]  a2g
    );

    reg [1:0] clk_16_cnt;
    reg [3:0] dnum;

    always @ (posedge clk_16) begin
        clk_16_cnt <= clk_16_cnt + 1;
    end

    always @(*) begin
        case(clk_16_cnt)
            2'b00: begin
                dnum = score[3:0];
                an = 4'b1110;
            end
            2'b01: begin
                dnum = score[7:4];
                an = 4'b1101;
            end
            2'b10: begin
                dnum = score[11:8];
                an = 4'b1011;
            end
            2'b11: begin
                dnum = hrdn;
                if (lstn)
                    an = 4'b0111;
                else
                    an = 4'b1111;
            end
        endcase
    end
    wam_obd obd( .num(dnum), .a2g(a2g) );
endmodule
module wam_dis(
    input clk_16,
    input wire  [3:0]  hrdn,
    input wire  [11:0] score,
    input wire  lstn,
    output reg  [3:0]  an,
    output wire [6:0]  a2g
    );


    reg [1:0] clk_16_cnt;
    reg [3:0] dnum;

    always @ (posedge clk_16) begin
        clk_16_cnt <= clk_16_cnt + 1;
    end

    always @(*) begin
        case(clk_16_cnt)
            2'b00: begin
                dnum = score[3:0];
                an = 4'b1110;
            end
            2'b01: begin
                dnum = score[7:4];
                an = 4'b1101;
            end
            2'b10: begin
                dnum = score[11:8];
                an = 4'b1011;
            end
            2'b11: begin
                dnum = hrdn;
                if (lstn)
                    an = 4'b0111;
                else
                    an = 4'b1111;
            end
        endcase
    end
    wam_obd obd( .num(dnum), .a2g(a2g) );
endmodule