data/full_repos/permissive/143278/ivltests/vhdl_test8.v
 line:30: before: "i"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test8.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (o_vhdl !== o_verilog) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test8.v:33: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test8.v:42: Unsupported: Ignoring delay on this delayed statement.\n            #4;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test8.v:47: Unsupported: Ignoring delay on this delayed statement.\n       #100 $display("PASSED");\n       ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_test8.v:54: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                          : ... In instance main.stim\n            temp = $random % 16;\n                 ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_test8.v:66: Cannot find file containing module: \'match_bits\'\n    match_bits match_vhdl(a,b,o_vhdl);\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/match_bits\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/match_bits.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/match_bits.sv\n             match_bits\n             match_bits.v\n             match_bits.sv\n             obj_dir/match_bits\n             obj_dir/match_bits.v\n             obj_dir/match_bits.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stimulus (output reg [7:0] a,b);
    parameter S = 20000;
    int unsigned i,j,k,l;
    initial begin
        for (i=0; i<S; i=i+1) begin
            #5;
            for(k=0; k<8; k=k+1) begin
                a[k] <= inject();
            end
        end
    end

    initial begin
        for (i=0; i<S; i=i+1) begin
            #4;
            for(l=0; l<8; l=l+1) begin
                b[l] <= inject();
            end
        end
       #100 $display("PASSED");
       $finish;
    end

    function inject();
        reg [3:0] temp;
        begin
            temp = $random % 16;
            if(temp >= 10)
                inject = 1'b1;
            else
                inject = 1'b0;
        end
    endfunction
endmodule
module stimulus (output reg [7:0] a,b);

    parameter S = 20000;
    int unsigned i,j,k,l;
    initial begin
        for (i=0; i<S; i=i+1) begin
            #5;
            for(k=0; k<8; k=k+1) begin
                a[k] <= inject();
            end
        end
    end

    initial begin
        for (i=0; i<S; i=i+1) begin
            #4;
            for(l=0; l<8; l=l+1) begin
                b[l] <= inject();
            end
        end
       #100 $display("PASSED");
       $finish;
    end

    function inject();
        reg [3:0] temp;
        begin
            temp = $random % 16;
            if(temp >= 10)
                inject = 1'b1;
            else
                inject = 1'b0;
        end
    endfunction
endmodule