data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_fifo_merge.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_fifo_merge.v:81: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 11 bits.\n                                                                                                                    : ... In instance nt_recv_capture_fifo_merge\n      data_word_cnt_sig = meta_len_capture >> 3;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_fifo_merge.v:84: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 11 bits.\n                                                                                                                    : ... In instance nt_recv_capture_fifo_merge\n      data_word_cnt_sig = (meta_len_capture >> 3) + 11\'b1;\n                        ^\n%Error: Exiting due to 2 warning(s)\n'
module nt_recv_capture_fifo_merge
(

  input wire          clk,
  input wire          rstn,
  input wire          rst_sw,


  input wire [74:0]   fifo_meta_dout_i,
  input wire          fifo_meta_empty_i,
  output wire         fifo_meta_rd_en_o,


  input wire [63:0]   fifo_data_dout_i,
  input wire          fifo_data_empty_i,
  output wire         fifo_data_rd_en_o,


  output wire [63:0]  fifo_din_o,
  output wire         fifo_wr_en_o,
  input wire          fifo_full_i
);


  wire [10:0] meta_len_capture;
  assign meta_len_capture = fifo_meta_dout_i[74:64];


  reg [7:0] data_word_cnt_sig;



  always @(*) begin
    if ((meta_len_capture & 11'h7) == 0) begin

      data_word_cnt_sig = meta_len_capture >> 3;
    end else begin

      data_word_cnt_sig = (meta_len_capture >> 3) + 11'b1;
    end
  end


  parameter META = 1'b0,
            DATA = 1'b1;

  reg           state, nxt_state;
  reg [7:0]     data_word_cnt, nxt_data_word_cnt;
  reg [7:0]     data_word_cntr, nxt_data_word_cntr;


  always @(posedge clk) begin
    if (~rstn | rst_sw) begin
      state <= META;
    end else begin
      state <= nxt_state;
    end

    data_word_cnt <= nxt_data_word_cnt;
    data_word_cntr <= nxt_data_word_cntr;
  end


  always @(*) begin
    nxt_state = state;
    nxt_data_word_cnt = data_word_cnt;
    nxt_data_word_cntr = data_word_cntr;

    case (state)
      META: begin
        if (~fifo_full_i & ~fifo_meta_empty_i) begin



          nxt_data_word_cnt = data_word_cnt_sig;
          nxt_data_word_cntr = 8'b0;

          if (data_word_cnt_sig > 0) begin

            nxt_state = DATA;
          end
        end
      end

      DATA: begin
        if (~fifo_full_i & ~fifo_data_empty_i) begin




          nxt_data_word_cntr = data_word_cntr + 1;

          if ((data_word_cntr + 1) == data_word_cnt) begin

            nxt_state = META;
          end
        end
      end

    endcase
  end



  assign fifo_din_o = (state == META) ? fifo_meta_dout_i[63:0] :
                        fifo_data_dout_i;
  assign fifo_wr_en_o = ~fifo_full_i &
                          (((state == META) & ~fifo_meta_empty_i) ||
                           ((state == DATA) & ~fifo_data_empty_i));


  assign fifo_meta_rd_en_o
    = ~fifo_full_i & (state == META) & ~fifo_meta_empty_i;
  assign fifo_data_rd_en_o
    = ~fifo_full_i & (state == DATA) & ~fifo_data_empty_i;

endmodule
module nt_recv_capture_fifo_merge
(

  input wire          clk,
  input wire          rstn,
  input wire          rst_sw,


  input wire [74:0]   fifo_meta_dout_i,
  input wire          fifo_meta_empty_i,
  output wire         fifo_meta_rd_en_o,


  input wire [63:0]   fifo_data_dout_i,
  input wire          fifo_data_empty_i,
  output wire         fifo_data_rd_en_o,


  output wire [63:0]  fifo_din_o,
  output wire         fifo_wr_en_o,
  input wire          fifo_full_i
);



  wire [10:0] meta_len_capture;
  assign meta_len_capture = fifo_meta_dout_i[74:64];


  reg [7:0] data_word_cnt_sig;



  always @(*) begin
    if ((meta_len_capture & 11'h7) == 0) begin

      data_word_cnt_sig = meta_len_capture >> 3;
    end else begin

      data_word_cnt_sig = (meta_len_capture >> 3) + 11'b1;
    end
  end


  parameter META = 1'b0,
            DATA = 1'b1;

  reg           state, nxt_state;
  reg [7:0]     data_word_cnt, nxt_data_word_cnt;
  reg [7:0]     data_word_cntr, nxt_data_word_cntr;


  always @(posedge clk) begin
    if (~rstn | rst_sw) begin
      state <= META;
    end else begin
      state <= nxt_state;
    end

    data_word_cnt <= nxt_data_word_cnt;
    data_word_cntr <= nxt_data_word_cntr;
  end


  always @(*) begin
    nxt_state = state;
    nxt_data_word_cnt = data_word_cnt;
    nxt_data_word_cntr = data_word_cntr;

    case (state)
      META: begin
        if (~fifo_full_i & ~fifo_meta_empty_i) begin



          nxt_data_word_cnt = data_word_cnt_sig;
          nxt_data_word_cntr = 8'b0;

          if (data_word_cnt_sig > 0) begin

            nxt_state = DATA;
          end
        end
      end

      DATA: begin
        if (~fifo_full_i & ~fifo_data_empty_i) begin




          nxt_data_word_cntr = data_word_cntr + 1;

          if ((data_word_cntr + 1) == data_word_cnt) begin

            nxt_state = META;
          end
        end
      end

    endcase
  end



  assign fifo_din_o = (state == META) ? fifo_meta_dout_i[63:0] :
                        fifo_data_dout_i;
  assign fifo_wr_en_o = ~fifo_full_i &
                          (((state == META) & ~fifo_meta_empty_i) ||
                           ((state == DATA) & ~fifo_data_empty_i));


  assign fifo_meta_rd_en_o
    = ~fifo_full_i & (state == META) & ~fifo_meta_empty_i;
  assign fifo_data_rd_en_o
    = ~fifo_full_i & (state == DATA) & ~fifo_data_empty_i;

endmodule