data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:9: Cannot find include file: aeses_defines.vh\n`include "aeses_defines.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207610706/src/key_scheduler,data/full_repos/permissive/207610706/aeses_defines.vh\n             data/full_repos/permissive/207610706/src/key_scheduler,data/full_repos/permissive/207610706/aeses_defines.vh.v\n             data/full_repos/permissive/207610706/src/key_scheduler,data/full_repos/permissive/207610706/aeses_defines.vh.sv\n             aeses_defines.vh\n             aeses_defines.vh.v\n             aeses_defines.vh.sv\n             obj_dir/aeses_defines.vh\n             obj_dir/aeses_defines.vh.v\n             obj_dir/aeses_defines.vh.sv\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:83: Define or directive not defined: \'`KEY_128\'\n        key_length <= `KEY_128;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        key_length <= `KEY_128;\n                              ^\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:104: Define or directive not defined: \'`KEY_256\'\n    if(input_key_length == `KEY_256)\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:104: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if(input_key_length == `KEY_256)\n                                   ^\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:106: Define or directive not defined: \'`KEY_192\'\n    else if(input_key_length == `KEY_192)\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:114: Define or directive not defined: \'`KEY_INVALID\'\n            if(input_key_length != `KEY_INVALID)\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:114: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(input_key_length != `KEY_INVALID)\n                                               ^\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:119: syntax error, unexpected end, expecting endcase\n            end\n            ^~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:129: Define or directive not defined: \'`KEY_192\'\n                next_phase_count = key_length == `KEY_192 & phase_count == 2\'d2 ? 2\'d0 : phase_count + 1;\n                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:131: syntax error, unexpected end\n            end\n            ^~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:196: Define or directive not defined: \'`KEY_192\'\n        `KEY_192:\n        ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:196: syntax error, unexpected \':\', expecting endcase\n        `KEY_192:\n                ^\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:198: Define or directive not defined: \'`KEY_256\'\n        `KEY_256:\n        ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:208: Define or directive not defined: \'`KEY_192\'\n    alternate_buffer_we = (key_length == `KEY_192);  \n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:213: Define or directive not defined: \'`KEY_128\'\n        (key_length == `KEY_128 |\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:214: Define or directive not defined: \'`KEY_192\'\n        key_length == `KEY_192 & phase_count != 2\'d1 |\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:215: Define or directive not defined: \'`KEY_256\'\n        key_length == `KEY_256 & ~phase_count[0]));\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:223: Define or directive not defined: \'`KEY_128\'\n        (key_length == `KEY_128 |\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:224: Define or directive not defined: \'`KEY_192\'\n        key_length == `KEY_192 & phase_count != 2\'d1 |\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:225: Define or directive not defined: \'`KEY_256\'\n        key_length == `KEY_256 & ~phase_count[0]);\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:228: Define or directive not defined: \'`KEY_192\'\n        (key_length == `KEY_192 & phase_count != 2\'d1 |\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:229: Define or directive not defined: \'`KEY_256\'\n        key_length == `KEY_256 & phase_count[0]);\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:232: Define or directive not defined: \'`KEY_256\'\n        (key_length == `KEY_256 & phase_count[0]);\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:235: Define or directive not defined: \'`KEY_192\'\n        ~(key_length == `KEY_192 & phase_count == 2\'d1);\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:254: Define or directive not defined: \'`KEY_256\'\n    key_word_register[4] ^ (key_length == `KEY_256 ?\n                                          ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:254: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n    key_word_register[4] ^ (key_length == `KEY_256 ?\n                                                   ^\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:271: Define or directive not defined: \'`KEY_192\'\n    output_key_selector[1] = (key_length == `KEY_192) & (phase_count != 2\'d0);\n                                            ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:271: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    output_key_selector[1] = (key_length == `KEY_192) & (phase_count != 2\'d0);\n                                                    ^\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:272: Define or directive not defined: \'`KEY_128\'\n    output_key_selector[0] = (key_length != `KEY_128) & phase_count[0];\n                                            ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/hp_key_sched.sv:272: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    output_key_selector[0] = (key_length != `KEY_128) & phase_count[0];\n                                                    ^\n%Error: Exiting due to 31 error(s)\n'
module hp_key_sched(
        clk, rst,
        new_key_schedule, input_key_length,
        aes_key_input,
        valid_key_out, round_key_material);

input clk, rst;

input new_key_schedule;
input [1:0] input_key_length;
input [0:255] aes_key_input;

output valid_key_out;
output [0:127] round_key_material;


localparam IDLE = 1'b0;
localparam SCHED = 1'b1;


reg state;
reg [1:0] key_length;
reg [3:0] round_key_count;
reg [1:0] phase_count;


reg next_state;
reg [1:0] next_key_length;
reg [3:0] next_round_key_count;
reg [1:0] next_phase_count;


reg [31:0] key_word_register[0:7];
reg [31:0] alternate_buffer[0:1];
reg [31:0] g_feed_in;
reg [7:0] rc;


wire [31:0] sbox_mapping;
wire [31:0] twisted_sbox_mapping;
wire [31:0] next_key_word_register[7:0];



wire [31:0] input_key_words[0:7];

genvar i;
generate
    for(i = 0; i < 8; i++)
    begin: split_input_key
        assign input_key_words[i] = aes_key_input[i*32:32*(i+1)-1];
    end
endgenerate


always@(posedge clk)
begin
    if(rst)
    begin
        state <= IDLE;
        key_length <= `KEY_128;
        round_key_count <= 4'd0;
        phase_count <= 2'd0;
    end
    else begin
        state <= next_state;
        key_length <= next_key_length;
        round_key_count <= next_round_key_count;
        phase_count <= next_phase_count;
    end
end


always@(*)
begin
    next_state = state;
    next_key_length = key_length;
    next_phase_count = 2'd0;
    
    if(input_key_length == `KEY_256)
        next_round_key_count = 4'd0;
    else if(input_key_length == `KEY_192)
        next_round_key_count = 4'd2;
    else
        next_round_key_count = 4'd4;
    
    case(state)
        IDLE:
            begin
            if(input_key_length != `KEY_INVALID)
                begin
                next_key_length = input_key_length;
                next_state = new_key_schedule;
                end
            end
        SCHED:
            begin


            if(round_key_count == 4'd14)
                next_state = IDLE;
            else
                begin
                next_round_key_count = round_key_count + 1;
                next_phase_count = key_length == `KEY_192 & phase_count == 2'd2 ? 2'd0 : phase_count + 1;
                end
            end
    endcase
end







reg [1:0] g_feed_in_casez_selector;
reg [31:0] next_g_feed_in;
reg g_feed_in_we;
reg alternate_buffer_we;
wire [7:0] rc_times_2;
reg [7:0] next_rc;
reg next_rc_we;

reg new_input_we;
reg key_reg_128_we, key_reg_192_we, key_reg_256_we;


aes_const_mult_02 next_rc_calculator(rc, rc_times_2);

always@(posedge clk)
begin
    if(key_reg_128_we)
        begin
        key_word_register[0] <= next_key_word_register[0];
        key_word_register[1] <= next_key_word_register[1];
        key_word_register[2] <= next_key_word_register[2];
        key_word_register[3] <= next_key_word_register[3];
        end
    if(key_reg_192_we)
        begin
        key_word_register[4] <= next_key_word_register[4];
        key_word_register[5] <= next_key_word_register[5];
        end
    if(key_reg_256_we)
        begin
        key_word_register[6] <= next_key_word_register[6];
        key_word_register[7] <= next_key_word_register[7];
        end
    
    if(g_feed_in_we)
        g_feed_in <= next_g_feed_in;
    
    if(next_rc_we)
        rc <= next_rc;
    
    if(alternate_buffer_we)
        begin
        alternate_buffer[0] <= key_word_register[4];
        alternate_buffer[1] <= key_word_register[5];
        end
end

always@(*)
begin

    g_feed_in_casez_selector = state == IDLE ? input_key_length : key_length;
    
    case(g_feed_in_casez_selector)
        `KEY_192:
            next_g_feed_in = next_key_word_register[5];
        `KEY_256:
            next_g_feed_in = state == IDLE | phase_count[0] ? next_key_word_register[7] : next_key_word_register[3];
        default:
            next_g_feed_in = next_key_word_register[3];
    endcase
    




    alternate_buffer_we = (key_length == `KEY_192);



    next_rc_we = (state == IDLE) | (state == SCHED &
        (key_length == `KEY_128 |
        key_length == `KEY_192 & phase_count != 2'd1 |
        key_length == `KEY_256 & ~phase_count[0]));
    next_rc = state == IDLE ? 8'h01 : rc_times_2;
    


    new_input_we = (state == IDLE) & new_key_schedule;
    
    key_reg_128_we = new_input_we | state == SCHED &
        (key_length == `KEY_128 |
        key_length == `KEY_192 & phase_count != 2'd1 |
        key_length == `KEY_256 & ~phase_count[0]);

    key_reg_192_we = new_input_we | state == SCHED &
        (key_length == `KEY_192 & phase_count != 2'd1 |
        key_length == `KEY_256 & phase_count[0]);

    key_reg_256_we = new_input_we | state == SCHED &
        (key_length == `KEY_256 & phase_count[0]);
    
    g_feed_in_we = new_input_we | state == SCHED &
        ~(key_length == `KEY_192 & phase_count == 2'd1);
        
end



hardwired_sbox sbox(g_feed_in, sbox_mapping);
assign twisted_sbox_mapping = {sbox_mapping[23:16] ^ rc, sbox_mapping[15:0], sbox_mapping[31:24]};


assign next_key_word_register[0] = state == IDLE ? input_key_words[0] : twisted_sbox_mapping ^ key_word_register[0];
assign next_key_word_register[1] = state == IDLE ? input_key_words[1] : next_key_word_register[0] ^ key_word_register[1];
assign next_key_word_register[2] = state == IDLE ? input_key_words[2] : next_key_word_register[1] ^ key_word_register[2];
assign next_key_word_register[3] = state == IDLE ? input_key_words[3] : next_key_word_register[2] ^ key_word_register[3];


assign next_key_word_register[4] = state == IDLE ? input_key_words[4] :
    key_word_register[4] ^ (key_length == `KEY_256 ?
    sbox_mapping :
    next_key_word_register[3]);

assign next_key_word_register[5] = state == IDLE ? input_key_words[5] : next_key_word_register[4] ^ key_word_register[5];
assign next_key_word_register[6] = state == IDLE ? input_key_words[6] : next_key_word_register[5] ^ key_word_register[6];
assign next_key_word_register[7] = state == IDLE ? input_key_words[7] : next_key_word_register[6] ^ key_word_register[7];


reg [1:0] output_key_selector;
reg [31:0] next_key_material[0:3];
wire [0:127] pack_next_key;

always@(*)
begin
    output_key_selector[1] = (key_length == `KEY_192) & (phase_count != 2'd0);
    output_key_selector[0] = (key_length != `KEY_128) & phase_count[0];
    
    case(output_key_selector)



        2'b00:
            begin
            next_key_material[0] = key_word_register[0];
            next_key_material[1] = key_word_register[1];
            next_key_material[2] = key_word_register[2];
            next_key_material[3] = key_word_register[3];
            end

        2'b01:
            begin
            next_key_material[0] = key_word_register[4];
            next_key_material[1] = key_word_register[5];
            next_key_material[2] = key_word_register[6];
            next_key_material[3] = key_word_register[7];
            end


        2'b11:
            begin
            next_key_material[0] = alternate_buffer[0];
            next_key_material[1] = alternate_buffer[1];
            next_key_material[2] = key_word_register[0];
            next_key_material[3] = key_word_register[1];
            end


        2'b10:
            begin
            next_key_material[0] = key_word_register[2];
            next_key_material[1] = key_word_register[3];
            next_key_material[2] = key_word_register[4];
            next_key_material[3] = key_word_register[5];
            end
    endcase
end

assign pack_next_key = {next_key_material[0], next_key_material[1], next_key_material[2], next_key_material[3]};
assign round_key_material = state == IDLE ? 128'd0 : pack_next_key;

assign valid_key_out = state;

endmodule
module hp_key_sched(
        clk, rst,
        new_key_schedule, input_key_length,
        aes_key_input,
        valid_key_out, round_key_material);


input clk, rst;

input new_key_schedule;
input [1:0] input_key_length;
input [0:255] aes_key_input;

output valid_key_out;
output [0:127] round_key_material;


localparam IDLE = 1'b0;
localparam SCHED = 1'b1;


reg state;
reg [1:0] key_length;
reg [3:0] round_key_count;
reg [1:0] phase_count;


reg next_state;
reg [1:0] next_key_length;
reg [3:0] next_round_key_count;
reg [1:0] next_phase_count;


reg [31:0] key_word_register[0:7];
reg [31:0] alternate_buffer[0:1];
reg [31:0] g_feed_in;
reg [7:0] rc;


wire [31:0] sbox_mapping;
wire [31:0] twisted_sbox_mapping;
wire [31:0] next_key_word_register[7:0];



wire [31:0] input_key_words[0:7];

genvar i;
generate
    for(i = 0; i < 8; i++)
    begin: split_input_key
        assign input_key_words[i] = aes_key_input[i*32:32*(i+1)-1];
    end
endgenerate


always@(posedge clk)
begin
    if(rst)
    begin
        state <= IDLE;
        key_length <= `KEY_128;
        round_key_count <= 4'd0;
        phase_count <= 2'd0;
    end
    else begin
        state <= next_state;
        key_length <= next_key_length;
        round_key_count <= next_round_key_count;
        phase_count <= next_phase_count;
    end
end


always@(*)
begin
    next_state = state;
    next_key_length = key_length;
    next_phase_count = 2'd0;
    
    if(input_key_length == `KEY_256)
        next_round_key_count = 4'd0;
    else if(input_key_length == `KEY_192)
        next_round_key_count = 4'd2;
    else
        next_round_key_count = 4'd4;
    
    case(state)
        IDLE:
            begin
            if(input_key_length != `KEY_INVALID)
                begin
                next_key_length = input_key_length;
                next_state = new_key_schedule;
                end
            end
        SCHED:
            begin


            if(round_key_count == 4'd14)
                next_state = IDLE;
            else
                begin
                next_round_key_count = round_key_count + 1;
                next_phase_count = key_length == `KEY_192 & phase_count == 2'd2 ? 2'd0 : phase_count + 1;
                end
            end
    endcase
end







reg [1:0] g_feed_in_casez_selector;
reg [31:0] next_g_feed_in;
reg g_feed_in_we;
reg alternate_buffer_we;
wire [7:0] rc_times_2;
reg [7:0] next_rc;
reg next_rc_we;

reg new_input_we;
reg key_reg_128_we, key_reg_192_we, key_reg_256_we;


aes_const_mult_02 next_rc_calculator(rc, rc_times_2);

always@(posedge clk)
begin
    if(key_reg_128_we)
        begin
        key_word_register[0] <= next_key_word_register[0];
        key_word_register[1] <= next_key_word_register[1];
        key_word_register[2] <= next_key_word_register[2];
        key_word_register[3] <= next_key_word_register[3];
        end
    if(key_reg_192_we)
        begin
        key_word_register[4] <= next_key_word_register[4];
        key_word_register[5] <= next_key_word_register[5];
        end
    if(key_reg_256_we)
        begin
        key_word_register[6] <= next_key_word_register[6];
        key_word_register[7] <= next_key_word_register[7];
        end
    
    if(g_feed_in_we)
        g_feed_in <= next_g_feed_in;
    
    if(next_rc_we)
        rc <= next_rc;
    
    if(alternate_buffer_we)
        begin
        alternate_buffer[0] <= key_word_register[4];
        alternate_buffer[1] <= key_word_register[5];
        end
end

always@(*)
begin

    g_feed_in_casez_selector = state == IDLE ? input_key_length : key_length;
    
    case(g_feed_in_casez_selector)
        `KEY_192:
            next_g_feed_in = next_key_word_register[5];
        `KEY_256:
            next_g_feed_in = state == IDLE | phase_count[0] ? next_key_word_register[7] : next_key_word_register[3];
        default:
            next_g_feed_in = next_key_word_register[3];
    endcase
    




    alternate_buffer_we = (key_length == `KEY_192);



    next_rc_we = (state == IDLE) | (state == SCHED &
        (key_length == `KEY_128 |
        key_length == `KEY_192 & phase_count != 2'd1 |
        key_length == `KEY_256 & ~phase_count[0]));
    next_rc = state == IDLE ? 8'h01 : rc_times_2;
    


    new_input_we = (state == IDLE) & new_key_schedule;
    
    key_reg_128_we = new_input_we | state == SCHED &
        (key_length == `KEY_128 |
        key_length == `KEY_192 & phase_count != 2'd1 |
        key_length == `KEY_256 & ~phase_count[0]);

    key_reg_192_we = new_input_we | state == SCHED &
        (key_length == `KEY_192 & phase_count != 2'd1 |
        key_length == `KEY_256 & phase_count[0]);

    key_reg_256_we = new_input_we | state == SCHED &
        (key_length == `KEY_256 & phase_count[0]);
    
    g_feed_in_we = new_input_we | state == SCHED &
        ~(key_length == `KEY_192 & phase_count == 2'd1);
        
end



hardwired_sbox sbox(g_feed_in, sbox_mapping);
assign twisted_sbox_mapping = {sbox_mapping[23:16] ^ rc, sbox_mapping[15:0], sbox_mapping[31:24]};


assign next_key_word_register[0] = state == IDLE ? input_key_words[0] : twisted_sbox_mapping ^ key_word_register[0];
assign next_key_word_register[1] = state == IDLE ? input_key_words[1] : next_key_word_register[0] ^ key_word_register[1];
assign next_key_word_register[2] = state == IDLE ? input_key_words[2] : next_key_word_register[1] ^ key_word_register[2];
assign next_key_word_register[3] = state == IDLE ? input_key_words[3] : next_key_word_register[2] ^ key_word_register[3];


assign next_key_word_register[4] = state == IDLE ? input_key_words[4] :
    key_word_register[4] ^ (key_length == `KEY_256 ?
    sbox_mapping :
    next_key_word_register[3]);

assign next_key_word_register[5] = state == IDLE ? input_key_words[5] : next_key_word_register[4] ^ key_word_register[5];
assign next_key_word_register[6] = state == IDLE ? input_key_words[6] : next_key_word_register[5] ^ key_word_register[6];
assign next_key_word_register[7] = state == IDLE ? input_key_words[7] : next_key_word_register[6] ^ key_word_register[7];


reg [1:0] output_key_selector;
reg [31:0] next_key_material[0:3];
wire [0:127] pack_next_key;

always@(*)
begin
    output_key_selector[1] = (key_length == `KEY_192) & (phase_count != 2'd0);
    output_key_selector[0] = (key_length != `KEY_128) & phase_count[0];
    
    case(output_key_selector)



        2'b00:
            begin
            next_key_material[0] = key_word_register[0];
            next_key_material[1] = key_word_register[1];
            next_key_material[2] = key_word_register[2];
            next_key_material[3] = key_word_register[3];
            end

        2'b01:
            begin
            next_key_material[0] = key_word_register[4];
            next_key_material[1] = key_word_register[5];
            next_key_material[2] = key_word_register[6];
            next_key_material[3] = key_word_register[7];
            end


        2'b11:
            begin
            next_key_material[0] = alternate_buffer[0];
            next_key_material[1] = alternate_buffer[1];
            next_key_material[2] = key_word_register[0];
            next_key_material[3] = key_word_register[1];
            end


        2'b10:
            begin
            next_key_material[0] = key_word_register[2];
            next_key_material[1] = key_word_register[3];
            next_key_material[2] = key_word_register[4];
            next_key_material[3] = key_word_register[5];
            end
    endcase
end

assign pack_next_key = {next_key_material[0], next_key_material[1], next_key_material[2], next_key_material[3]};
assign round_key_material = state == IDLE ? 128'd0 : pack_next_key;

assign valid_key_out = state;

endmodule