data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX V1.00/UART_TX/fifo.v
 line:291: before: "("
1: b'%Error: Cannot find file containing module: V1.00/UART_TX,data/full_repos/permissive/216654561\n        ... Looked in:\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n             V1.00/UART_TX,data/full_repos/permissive/216654561\n             V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX\n%Error: Cannot find file containing module: V1.00/UART_TX/fifo.v\n%Error: Exiting due to 3 error(s)\n'
module fifo
(
 input we,
 input re,
 input clk,
 input rst,
 input [7:0] data_in,
 output full,
 output reg [7:0] data_o,
 output  empty

 

);
integer i;
reg [4:0] pr,pw;
reg [7:0] mem [31:0];
assign empty = ((pw-pr)==0)? 1'b1:1'b0;
assign full  = (pr>pw)? (((pr-pw)==1)? 1'b1:1'b0):1'b0;




 always@(posedge clk )
begin

 if(!rst)
  begin
   pr<=5'd1;
   pw<=5'd1; 
   for(i=0;i<=31;i=i+1)
    begin
      mem[i]<=8'b0;
	end
  end
else
begin
  if(re&&!empty)
   begin
     data_o=mem[pr]; 
     pr=pr+5'd1;
   end
  else begin data_o<=data_o; end
  if(we&&!full )
   begin
     mem[pw]=data_in;
     pw=pw+5'd1;
   end
     
end
end
 
endmodule
module fifo
(
 input we,
 input re,
 input clk,
 input rst,
 input [7:0] data_in,
 output full,
 output reg [7:0] data_o,
 output  empty

 

);

integer i;
reg [4:0] pr,pw;
reg [7:0] mem [31:0];
assign empty = ((pw-pr)==0)? 1'b1:1'b0;
assign full  = (pr>pw)? (((pr-pw)==1)? 1'b1:1'b0):1'b0;




 always@(posedge clk )
begin

 if(!rst)
  begin
   pr<=5'd1;
   pw<=5'd1; 
   for(i=0;i<=31;i=i+1)
    begin
      mem[i]<=8'b0;
	end
  end
else
begin
  if(re&&!empty)
   begin
     data_o=mem[pr]; 
     pr=pr+5'd1;
   end
  else begin data_o<=data_o; end
  if(we&&!full )
   begin
     mem[pw]=data_in;
     pw=pw+5'd1;
   end
     
end
end
 
endmodule