data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v
 line:67: before: "module"
1: b'%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:2: Cannot find include file: definitions.vh\n`include "definitions.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh.v\n             data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new,data/full_repos/permissive/206059435/definitions.vh.sv\n             definitions.vh\n             definitions.vh.v\n             definitions.vh.sv\n             obj_dir/definitions.vh\n             obj_dir/definitions.vh.v\n             obj_dir/definitions.vh.sv\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:15: Define or directive not defined: \'`ALU_OP_LENGTH\'\n           input  wire[`ALU_OP_LENGTH  - 1:0]  cu_alu_op,\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:25: Define or directive not defined: \'`OVERFLOW_TRUE\'\nassign overflow = (alu_temp_result[32] != alu_temp_result[31]) ? `OVERFLOW_TRUE : `OVERFLOW_FALSE;\n                                                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:25: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nassign overflow = (alu_temp_result[32] != alu_temp_result[31]) ? `OVERFLOW_TRUE : `OVERFLOW_FALSE;\n                                                                                ^\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:25: Define or directive not defined: \'`OVERFLOW_FALSE\'\nassign overflow = (alu_temp_result[32] != alu_temp_result[31]) ? `OVERFLOW_TRUE : `OVERFLOW_FALSE;\n                                                                                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:30: Define or directive not defined: \'`ALU_OP_SLL\'\n       (cu_alu_op == `ALU_OP_SLL ||\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:30: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n       (cu_alu_op == `ALU_OP_SLL ||\n                                 ^~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:31: Define or directive not defined: \'`ALU_OP_SRL\'\n        cu_alu_op == `ALU_OP_SRL ||\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:32: Define or directive not defined: \'`ALU_OP_SRA\'\n        cu_alu_op == `ALU_OP_SRA) ? sa : alu_input_1[4:0];\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:41: Define or directive not defined: \'`ALU_OP_ADD\'\n        `ALU_OP_ADD:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:41: syntax error, unexpected \':\', expecting endcase\n        `ALU_OP_ADD:\n                   ^\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:43: Define or directive not defined: \'`ALU_OP_SUB\'\n        `ALU_OP_SUB:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:46: Define or directive not defined: \'`ALU_OP_SLT\'\n        `ALU_OP_SLT:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:50: Define or directive not defined: \'`ALU_OP_AND\'\n        `ALU_OP_AND:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:52: Define or directive not defined: \'`ALU_OP_OR\'\n        `ALU_OP_OR :\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:54: Define or directive not defined: \'`ALU_OP_NOR\'\n        `ALU_OP_NOR:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:57: Define or directive not defined: \'`ALU_OP_XOR\'\n        `ALU_OP_XOR:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:61: Define or directive not defined: \'`ALU_OP_SLL\'\n        `ALU_OP_SLL:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:63: Define or directive not defined: \'`ALU_OP_SLLV\'\n        `ALU_OP_SLLV:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:67: Define or directive not defined: \'`ALU_OP_SRL\'\n        `ALU_OP_SRL:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:69: Define or directive not defined: \'`ALU_OP_SRLV\'\n        `ALU_OP_SRLV:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:73: Define or directive not defined: \'`ALU_OP_SRA\'\n        `ALU_OP_SRA:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:75: Define or directive not defined: \'`ALU_OP_SRAV\'\n        `ALU_OP_SRAV:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/206059435/pipelined-zanpu.srcs/sources_1/new/alu.v:78: Define or directive not defined: \'`ALU_OP_DEFAULT\'\n        `ALU_OP_DEFAULT:\n        ^~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module alu(
           input  wire[31:0]                   alu_input_1,
           input  wire[31:0]                   alu_input_2,
           input  wire[4:0]                    sa,
           input  wire[`ALU_OP_LENGTH  - 1:0]  cu_alu_op,

           output wire[31:0]                   alu_result,
           output wire                         overflow
       );

reg[32:0] alu_temp_result;
assign alu_result = alu_temp_result[31:0];


assign overflow = (alu_temp_result[32] != alu_temp_result[31]) ? `OVERFLOW_TRUE : `OVERFLOW_FALSE;


wire[4:0] displacement;
assign displacement =
       (cu_alu_op == `ALU_OP_SLL ||
        cu_alu_op == `ALU_OP_SRL ||
        cu_alu_op == `ALU_OP_SRA) ? sa : alu_input_1[4:0];


wire[31:0] diff;
assign diff = (alu_input_1 < alu_input_2) ? 32'h00000001 : 32'h00000000;

always @ (*) begin
    case (cu_alu_op)

        `ALU_OP_ADD:
            alu_temp_result <= {alu_input_1[31], alu_input_1} + {alu_input_2[31], alu_input_2};
        `ALU_OP_SUB:
            alu_temp_result <= {alu_input_1[31], alu_input_1} - {alu_input_2[31], alu_input_2};

        `ALU_OP_SLT:
            alu_temp_result <= diff;


        `ALU_OP_AND:
            alu_temp_result <= {alu_input_1[31], alu_input_1} & {alu_input_2[31], alu_input_2};
        `ALU_OP_OR :
            alu_temp_result <= {alu_input_1[31], alu_input_1} | {alu_input_2[31], alu_input_2};
        `ALU_OP_NOR:
            alu_temp_result <= (({alu_input_1[31], alu_input_1} & ~{alu_input_2[31], alu_input_2}) |
                                (~{alu_input_1[31], alu_input_1} & {alu_input_2[31], alu_input_2}));
        `ALU_OP_XOR:
            alu_temp_result <= {alu_input_1[31], alu_input_1} ^ {alu_input_2[31], alu_input_2};


        `ALU_OP_SLL:
            alu_temp_result <= {alu_input_2[31], alu_input_2} << displacement;
        `ALU_OP_SLLV:
            alu_temp_result <= {alu_input_2[31], alu_input_2} << displacement;


        `ALU_OP_SRL:
            alu_temp_result <= {alu_input_2[31], alu_input_2} >> displacement;
        `ALU_OP_SRLV:
            alu_temp_result <= {alu_input_2[31], alu_input_2} >> displacement;


        `ALU_OP_SRA:
            alu_temp_result <= ({{31{alu_input_2[31]}}, 1'b0} << (~displacement)) | (alu_input_2 >> displacement);
        `ALU_OP_SRAV:
            alu_temp_result <= ({{31{alu_input_2[31]}}, 1'b0} << (~displacement)) | (alu_input_2 >> displacement);

        `ALU_OP_DEFAULT:
            alu_temp_result <= {alu_input_2[31], alu_input_2};
    endcase
end
endmodule
module alu(
           input  wire[31:0]                   alu_input_1,
           input  wire[31:0]                   alu_input_2,
           input  wire[4:0]                    sa,
           input  wire[`ALU_OP_LENGTH  - 1:0]  cu_alu_op,

           output wire[31:0]                   alu_result,
           output wire                         overflow
       );


reg[32:0] alu_temp_result;
assign alu_result = alu_temp_result[31:0];


assign overflow = (alu_temp_result[32] != alu_temp_result[31]) ? `OVERFLOW_TRUE : `OVERFLOW_FALSE;


wire[4:0] displacement;
assign displacement =
       (cu_alu_op == `ALU_OP_SLL ||
        cu_alu_op == `ALU_OP_SRL ||
        cu_alu_op == `ALU_OP_SRA) ? sa : alu_input_1[4:0];


wire[31:0] diff;
assign diff = (alu_input_1 < alu_input_2) ? 32'h00000001 : 32'h00000000;

always @ (*) begin
    case (cu_alu_op)

        `ALU_OP_ADD:
            alu_temp_result <= {alu_input_1[31], alu_input_1} + {alu_input_2[31], alu_input_2};
        `ALU_OP_SUB:
            alu_temp_result <= {alu_input_1[31], alu_input_1} - {alu_input_2[31], alu_input_2};

        `ALU_OP_SLT:
            alu_temp_result <= diff;


        `ALU_OP_AND:
            alu_temp_result <= {alu_input_1[31], alu_input_1} & {alu_input_2[31], alu_input_2};
        `ALU_OP_OR :
            alu_temp_result <= {alu_input_1[31], alu_input_1} | {alu_input_2[31], alu_input_2};
        `ALU_OP_NOR:
            alu_temp_result <= (({alu_input_1[31], alu_input_1} & ~{alu_input_2[31], alu_input_2}) |
                                (~{alu_input_1[31], alu_input_1} & {alu_input_2[31], alu_input_2}));
        `ALU_OP_XOR:
            alu_temp_result <= {alu_input_1[31], alu_input_1} ^ {alu_input_2[31], alu_input_2};


        `ALU_OP_SLL:
            alu_temp_result <= {alu_input_2[31], alu_input_2} << displacement;
        `ALU_OP_SLLV:
            alu_temp_result <= {alu_input_2[31], alu_input_2} << displacement;


        `ALU_OP_SRL:
            alu_temp_result <= {alu_input_2[31], alu_input_2} >> displacement;
        `ALU_OP_SRLV:
            alu_temp_result <= {alu_input_2[31], alu_input_2} >> displacement;


        `ALU_OP_SRA:
            alu_temp_result <= ({{31{alu_input_2[31]}}, 1'b0} << (~displacement)) | (alu_input_2 >> displacement);
        `ALU_OP_SRAV:
            alu_temp_result <= ({{31{alu_input_2[31]}}, 1'b0} << (~displacement)) | (alu_input_2 >> displacement);

        `ALU_OP_DEFAULT:
            alu_temp_result <= {alu_input_2[31], alu_input_2};
    endcase
end
endmodule