data/full_repos/permissive/143278/ivltests/case3.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ;
reg [1:0] sel;
reg a,b,c,d;
wire q;

switch u_switch (q,a,b,c,d,sel);

initial
  begin
    a = 0;
    b = 0;
    c = 0;
    d = 0;
    sel = 2'b00;

    #1;
    if(q !== 1'b0)
      begin
        $display("FAILED");
        $finish;
      end
    a = 1;
    #1;
    if(q !== 1'b1)
      begin
        $display("FAILED");
        $finish;
      end
    $display("PASSED");
  end
endmodule
module test ;

reg [1:0] sel;
reg a,b,c,d;
wire q;

switch u_switch (q,a,b,c,d,sel);

initial
  begin
    a = 0;
    b = 0;
    c = 0;
    d = 0;
    sel = 2'b00;

    #1;
    if(q !== 1'b0)
      begin
        $display("FAILED");
        $finish;
      end
    a = 1;
    #1;
    if(q !== 1'b1)
      begin
        $display("FAILED");
        $finish;
      end
    $display("PASSED");
  end
endmodule