data/full_repos/permissive/121410129/Step6/debouncer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/121410129/Step6/debouncer.v:14: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h0\' generates 20 bits.\n                                                                         : ... In instance debounce\n  count  <= 20\'d0;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/121410129/Step6/debouncer.v:22: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h0\' generates 20 bits.\n                                                                         : ... In instance debounce\n    count  <= 20\'d0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/121410129/Step6/debouncer.v:34: Operator ADD expects 28 bits on the RHS, but RHS\'s CONST \'20\'h1\' generates 20 bits.\n                                                                         : ... In instance debounce\n    count <= count + 20\'d1;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/121410129/Step6/debouncer.v:39: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h0\' generates 20 bits.\n                                                                         : ... In instance debounce\n   count  <= 20\'d0;\n          ^~\n%Error: Exiting due to 4 warning(s)\n'
module debounce (clk, reset, noisy, clean);
parameter DEBOUNCE = 1000000;
parameter DELAY = 100000000;
input wire clk, reset, noisy;
output reg clean;

reg [27:0] count;
reg [27:0]delay;
reg [2:0]step;

always @ (posedge clk or posedge reset) begin
	if(reset == 1) begin
		clean 		<= 1'b0;
		count		<= 20'd0;
		delay		<= DEBOUNCE;
		step		<= 3'b0;
	end
	else begin
		if (noisy == 1'b1) begin
			if (count == delay) begin
				clean		<= 1'b1;
				count		<= 20'd0;
				if (step == 0) begin
					delay <= DELAY;
					step <= step + 3'b1;
				end
				else if (step < 4) begin
					delay <= delay >> 1;
					step <= step + 3'b1;
				end
			end
			else begin
				clean <= 1'b0;
				count <= count + 20'd1;
			end
		end
		else begin
			clean 		<= 1'b0;
			count		<= 20'd0;
			delay		<= DEBOUNCE;
			step		<= 3'b0;
		end
	end
end
endmodule
module debounce (clk, reset, noisy, clean);

parameter DEBOUNCE = 1000000;
parameter DELAY = 100000000;
input wire clk, reset, noisy;
output reg clean;

reg [27:0] count;
reg [27:0]delay;
reg [2:0]step;

always @ (posedge clk or posedge reset) begin
	if(reset == 1) begin
		clean 		<= 1'b0;
		count		<= 20'd0;
		delay		<= DEBOUNCE;
		step		<= 3'b0;
	end
	else begin
		if (noisy == 1'b1) begin
			if (count == delay) begin
				clean		<= 1'b1;
				count		<= 20'd0;
				if (step == 0) begin
					delay <= DELAY;
					step <= step + 3'b1;
				end
				else if (step < 4) begin
					delay <= delay >> 1;
					step <= step + 3'b1;
				end
			end
			else begin
				clean <= 1'b0;
				count <= count + 20'd1;
			end
		end
		else begin
			clean 		<= 1'b0;
			count		<= 20'd0;
			delay		<= DEBOUNCE;
			step		<= 3'b0;
		end
	end
end
endmodule