data/full_repos/permissive/14593708/tests/register-file-testbench.v
1: b'%Error: data/full_repos/permissive/14593708/tests/register-file-testbench.v:17: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("register-file-test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/14593708/tests/register-file-testbench.v:18: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, register_file_testbench);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/14593708/tests/register-file-testbench.v:19: Unsupported or unknown PLI call: $monitor\n        $monitor("read_register_port_0=%d write_register=%d write_data=%d write_enable=%d read_data_port_0=%d",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #0  write_enable = \'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #0  write_data = \'d21;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #0  write_register = \'b00;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1  write_enable = \'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1  write_enable = \'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #0  write_register = \'b01;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #0  write_data = \'d42;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1  write_enable = \'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #1  write_enable = \'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #0  write_register = \'b10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #0  write_data = \'d84;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1  write_enable = \'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1  write_enable = \'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #0  write_register = \'b11;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #0  write_data = \'d168;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #1  write_enable = \'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #1  write_enable = \'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1  read_register_port_0 = \'b00;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #1  read_register_port_0 = \'b01;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #1  read_register_port_0 = \'b10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-file-testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #1  read_register_port_0 = \'b11;\n    ^\n%Error: Exiting due to 3 error(s), 21 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_file_testbench;

    reg[1:0]   read_register_port_0;
    reg[1:0]   read_register_port_1;
    reg[1:0]   write_register;
    reg[31:0]  write_data;
    reg        write_enable;
    wire[31:0] read_data_port_0;
    wire[31:0] read_data_port_1;

    register_file rf(read_register_port_0, read_register_port_1,
                     write_register, write_data, write_enable,
                     read_data_port_0, read_data_port_1);

    initial
    begin
        $dumpfile("register-file-test.vcd");
        $dumpvars(0, register_file_testbench);
        $monitor("read_register_port_0=%d write_register=%d write_data=%d write_enable=%d read_data_port_0=%d",
                 read_register_port_0, write_register, write_data,
                 write_enable, read_data_port_0);

    #0  write_enable = 'b0;
    #0  write_data = 'd21;
    #0  write_register = 'b00;
    #1  write_enable = 'b1;
    #1  write_enable = 'b0;
    
    #0  write_register = 'b01;
    #0  write_data = 'd42;
    #1  write_enable = 'b1;
    #1  write_enable = 'b0;

    #0  write_register = 'b10;
    #0  write_data = 'd84;
    #1  write_enable = 'b1;
    #1  write_enable = 'b0;
    
    #0  write_register = 'b11;
    #0  write_data = 'd168;
    #1  write_enable = 'b1;
    #1  write_enable = 'b0;

    #1  read_register_port_0 = 'b00;
    #1  read_register_port_0 = 'b01;
    #1  read_register_port_0 = 'b10;
    #1  read_register_port_0 = 'b11;
    end

endmodule
module register_file_testbench;


    reg[1:0]   read_register_port_0;
    reg[1:0]   read_register_port_1;
    reg[1:0]   write_register;
    reg[31:0]  write_data;
    reg        write_enable;
    wire[31:0] read_data_port_0;
    wire[31:0] read_data_port_1;

    register_file rf(read_register_port_0, read_register_port_1,
                     write_register, write_data, write_enable,
                     read_data_port_0, read_data_port_1);

    initial
    begin
        $dumpfile("register-file-test.vcd");
        $dumpvars(0, register_file_testbench);
        $monitor("read_register_port_0=%d write_register=%d write_data=%d write_enable=%d read_data_port_0=%d",
                 read_register_port_0, write_register, write_data,
                 write_enable, read_data_port_0);

    #0  write_enable = 'b0;
    #0  write_data = 'd21;
    #0  write_register = 'b00;
    #1  write_enable = 'b1;
    #1  write_enable = 'b0;
    
    #0  write_register = 'b01;
    #0  write_data = 'd42;
    #1  write_enable = 'b1;
    #1  write_enable = 'b0;

    #0  write_register = 'b10;
    #0  write_data = 'd84;
    #1  write_enable = 'b1;
    #1  write_enable = 'b0;
    
    #0  write_register = 'b11;
    #0  write_data = 'd168;
    #1  write_enable = 'b1;
    #1  write_enable = 'b0;

    #1  read_register_port_0 = 'b00;
    #1  read_register_port_0 = 'b01;
    #1  read_register_port_0 = 'b10;
    #1  read_register_port_0 = 'b11;
    end

endmodule