data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_splitter.v
 line:46: before: "="
data/verilator_xmls/ea4cb33b-5c3d-46ee-8c8d-2dc2b855e949.xml
module ctrlport_splitter #(
  parameter NUM_SLAVES = 2
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,
  input  wire [ 3:0] s_ctrlport_req_byte_en,
  input  wire        s_ctrlport_req_has_time,
  input  wire [63:0] s_ctrlport_req_time,
  output reg         s_ctrlport_resp_ack = 1'b0,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  output wire [   NUM_SLAVES-1:0] m_ctrlport_req_wr,
  output wire [   NUM_SLAVES-1:0] m_ctrlport_req_rd,
  output wire [20*NUM_SLAVES-1:0] m_ctrlport_req_addr,
  output wire [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
  output wire [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
  output wire [   NUM_SLAVES-1:0] m_ctrlport_req_has_time,
  output wire [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
  input  wire [   NUM_SLAVES-1:0] m_ctrlport_resp_ack,
  input  wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
  input  wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
);

  generate
    if (NUM_SLAVES == 1) begin : gen_no_split

      assign m_ctrlport_req_wr       = s_ctrlport_req_wr;
      assign m_ctrlport_req_rd       = s_ctrlport_req_rd;
      assign m_ctrlport_req_addr     = s_ctrlport_req_addr;
      assign m_ctrlport_req_data     = s_ctrlport_req_data;
      assign m_ctrlport_req_byte_en  = s_ctrlport_req_byte_en;
      assign m_ctrlport_req_has_time = s_ctrlport_req_has_time;
      assign m_ctrlport_req_time     = s_ctrlport_req_time;
      always @(*) begin
        s_ctrlport_resp_ack     = m_ctrlport_resp_ack;
        s_ctrlport_resp_status  = m_ctrlport_resp_status;
        s_ctrlport_resp_data    = m_ctrlport_resp_data;
      end

    end else begin : gen_splitter




      genvar i;
      for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split


        assign m_ctrlport_req_wr[i]           = s_ctrlport_req_wr;
        assign m_ctrlport_req_rd[i]           = s_ctrlport_req_rd;
        assign m_ctrlport_req_addr[20*i+:20]  = s_ctrlport_req_addr;
        assign m_ctrlport_req_data[32*i+:32]  = s_ctrlport_req_data;
        assign m_ctrlport_req_byte_en[4*i+:4] = s_ctrlport_req_byte_en;
        assign m_ctrlport_req_has_time[i]     = s_ctrlport_req_has_time;
        assign m_ctrlport_req_time[64*i+:64]  = s_ctrlport_req_time;
      end





      reg [31:0] data;
      reg [ 1:0] status;
      reg        ack = 0;


      always @(*) begin : comb_decode
        integer s;
        data   = 0;
        status = 0;
        ack    = 0;
        for (s = 0; s < NUM_SLAVES; s = s+1) begin
          data   = data   | (m_ctrlport_resp_data  [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
          status = status | (m_ctrlport_resp_status[s* 2 +:  2] & { 2{m_ctrlport_resp_ack[s]}});
          ack    = ack    | m_ctrlport_resp_ack[s];
        end
      end


      always @(posedge ctrlport_clk) begin : response_reg
        if (ctrlport_rst) begin
          s_ctrlport_resp_ack  <= 0;
        end else begin
          s_ctrlport_resp_data   <= data;
          s_ctrlport_resp_status <= status;
          s_ctrlport_resp_ack    <= ack;
        end
      end
    end
  endgenerate
endmodule
module ctrlport_splitter #(
  parameter NUM_SLAVES = 2
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,
  input  wire [ 3:0] s_ctrlport_req_byte_en,
  input  wire        s_ctrlport_req_has_time,
  input  wire [63:0] s_ctrlport_req_time,
  output reg         s_ctrlport_resp_ack = 1'b0,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  output wire [   NUM_SLAVES-1:0] m_ctrlport_req_wr,
  output wire [   NUM_SLAVES-1:0] m_ctrlport_req_rd,
  output wire [20*NUM_SLAVES-1:0] m_ctrlport_req_addr,
  output wire [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
  output wire [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
  output wire [   NUM_SLAVES-1:0] m_ctrlport_req_has_time,
  output wire [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
  input  wire [   NUM_SLAVES-1:0] m_ctrlport_resp_ack,
  input  wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
  input  wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
);


  generate
    if (NUM_SLAVES == 1) begin : gen_no_split

      assign m_ctrlport_req_wr       = s_ctrlport_req_wr;
      assign m_ctrlport_req_rd       = s_ctrlport_req_rd;
      assign m_ctrlport_req_addr     = s_ctrlport_req_addr;
      assign m_ctrlport_req_data     = s_ctrlport_req_data;
      assign m_ctrlport_req_byte_en  = s_ctrlport_req_byte_en;
      assign m_ctrlport_req_has_time = s_ctrlport_req_has_time;
      assign m_ctrlport_req_time     = s_ctrlport_req_time;
      always @(*) begin
        s_ctrlport_resp_ack     = m_ctrlport_resp_ack;
        s_ctrlport_resp_status  = m_ctrlport_resp_status;
        s_ctrlport_resp_data    = m_ctrlport_resp_data;
      end

    end else begin : gen_splitter




      genvar i;
      for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split


        assign m_ctrlport_req_wr[i]           = s_ctrlport_req_wr;
        assign m_ctrlport_req_rd[i]           = s_ctrlport_req_rd;
        assign m_ctrlport_req_addr[20*i+:20]  = s_ctrlport_req_addr;
        assign m_ctrlport_req_data[32*i+:32]  = s_ctrlport_req_data;
        assign m_ctrlport_req_byte_en[4*i+:4] = s_ctrlport_req_byte_en;
        assign m_ctrlport_req_has_time[i]     = s_ctrlport_req_has_time;
        assign m_ctrlport_req_time[64*i+:64]  = s_ctrlport_req_time;
      end





      reg [31:0] data;
      reg [ 1:0] status;
      reg        ack = 0;


      always @(*) begin : comb_decode
        integer s;
        data   = 0;
        status = 0;
        ack    = 0;
        for (s = 0; s < NUM_SLAVES; s = s+1) begin
          data   = data   | (m_ctrlport_resp_data  [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
          status = status | (m_ctrlport_resp_status[s* 2 +:  2] & { 2{m_ctrlport_resp_ack[s]}});
          ack    = ack    | m_ctrlport_resp_ack[s];
        end
      end


      always @(posedge ctrlport_clk) begin : response_reg
        if (ctrlport_rst) begin
          s_ctrlport_resp_ack  <= 0;
        end else begin
          s_ctrlport_resp_data   <= data;
          s_ctrlport_resp_status <= status;
          s_ctrlport_resp_ack    <= ack;
        end
      end
    end
  endgenerate
endmodule