data/full_repos/permissive/116563702/tristateBuffer/tristateBuffer.v
data/verilator_xmls/3df8747e-b58e-4420-b35a-9d0c1052af02.xml
module tristate(input [3:0] data,
		input 	     s,
		output [3:0] bus);

   assign bus = s ? data : 4'bz;
endmodule
module tristate(input [3:0] data,
		input 	     s,
		output [3:0] bus);


   assign bus = s ? data : 4'bz;
endmodule