data/full_repos/permissive/14636651/Accumulator.v
data/verilator_xmls/c56a5957-688b-4a33-898f-e1c5682f62c5.xml
module Accumulator(input clk, load, input [15:0] din, output reg [15:0] dout);
	always@(posedge clk)
	begin
		if(load)
		begin
			dout <= din;
		end
	end
endmodule
module Accumulator(input clk, load, input [15:0] din, output reg [15:0] dout);

	always@(posedge clk)
	begin
		if(load)
		begin
			dout <= din;
		end
	end
endmodule