data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_rx_fifo_p1_adapter.v
data/verilator_xmls/0fb7a9b2-44ea-41b3-8930-f2a781c438ab.xml
module sonic_vc_rx_fifo_p1_adapter (
    

      input              clk,

      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [127: 0] in_data,
      input              in_startofpacket,
      input              in_endofpacket,
      input      [ 1: 0] in_empty,

      input              out_ready,
      output reg         out_valid,
      output reg [127: 0] out_data,
      output reg         out_startofpacket,
      output reg         out_endofpacket,
      output reg [ 1: 0] out_empty
);








   reg  [131: 0] in_payload;
   reg  [131: 0] out_payload;
   reg  [ 1: 0] ready;





   always @* begin
     in_payload = {in_data,in_startofpacket,in_endofpacket,in_empty};
     {out_data,out_startofpacket,out_endofpacket,out_empty} = out_payload;
   end




   always @* begin
     ready[1] = out_ready;
     out_valid = in_valid && ready[0];
     out_payload = in_payload;
     in_ready = ready[0];
   end


   always @(posedge clk or negedge reset_n) begin
      if (!reset_n) begin
        ready[1-1:0] <= 0;
      end else begin
        ready[1-1:0] <= ready[1:1];
      end 
   end


endmodule
module sonic_vc_rx_fifo_p1_adapter (
    

      input              clk,

      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [127: 0] in_data,
      input              in_startofpacket,
      input              in_endofpacket,
      input      [ 1: 0] in_empty,

      input              out_ready,
      output reg         out_valid,
      output reg [127: 0] out_data,
      output reg         out_startofpacket,
      output reg         out_endofpacket,
      output reg [ 1: 0] out_empty
);









   reg  [131: 0] in_payload;
   reg  [131: 0] out_payload;
   reg  [ 1: 0] ready;





   always @* begin
     in_payload = {in_data,in_startofpacket,in_endofpacket,in_empty};
     {out_data,out_startofpacket,out_endofpacket,out_empty} = out_payload;
   end




   always @* begin
     ready[1] = out_ready;
     out_valid = in_valid && ready[0];
     out_payload = in_payload;
     in_ready = ready[0];
   end


   always @(posedge clk or negedge reset_n) begin
      if (!reset_n) begin
        ready[1-1:0] <= 0;
      end else begin
        ready[1-1:0] <= ready[1:1];
      end 
   end


endmodule