data/full_repos/permissive/156129873/verilog/id.v
1: b'%Error: data/full_repos/permissive/156129873/verilog/id.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/156129873/verilog/id.v:72: Define or directive not defined: \'`Enable\'\n        if (re1_o == `Enable && ex_writeReg_i == `Enable && reg1Addr_o == ex_writeRegAddr_i) begin\n                     ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:72: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n        if (re1_o == `Enable && ex_writeReg_i == `Enable && reg1Addr_o == ex_writeRegAddr_i) begin\n                             ^~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:72: Define or directive not defined: \'`Enable\'\n        if (re1_o == `Enable && ex_writeReg_i == `Enable && reg1Addr_o == ex_writeRegAddr_i) begin\n                                                 ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:74: Define or directive not defined: \'`Enable\'\n        end else if (re1_o == `Enable && mem_writeReg_i == `Enable && reg1Addr_o == mem_writeRegAddr_i) begin\n                              ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:74: Define or directive not defined: \'`Enable\'\n        end else if (re1_o == `Enable && mem_writeReg_i == `Enable && reg1Addr_o == mem_writeRegAddr_i) begin\n                                                           ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:83: Define or directive not defined: \'`Enable\'\n        if (re2_o == `Enable && ex_writeReg_i == `Enable && reg2Addr_o == ex_writeRegAddr_i) begin\n                     ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:83: Define or directive not defined: \'`Enable\'\n        if (re2_o == `Enable && ex_writeReg_i == `Enable && reg2Addr_o == ex_writeRegAddr_i) begin\n                                                 ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:85: Define or directive not defined: \'`Enable\'\n        end else if (re2_o == `Enable && mem_writeReg_i == `Enable && reg2Addr_o == mem_writeRegAddr_i) begin\n                              ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:85: Define or directive not defined: \'`Enable\'\n        end else if (re2_o == `Enable && mem_writeReg_i == `Enable && reg2Addr_o == mem_writeRegAddr_i) begin\n                                                           ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:94: Define or directive not defined: \'`MEM_READ_OP\'\n        if (lastMemOp_i == `MEM_READ_OP && \n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:95: Define or directive not defined: \'`Enable\'\n            ((lastRegAddr_i == reg1Addr_o && re1_o == `Enable) || \n                                                      ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:96: Define or directive not defined: \'`Enable\'\n    (lastRegAddr_i == reg2Addr_o && re2_o == `Enable))) begin\n                                             ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:97: Define or directive not defined: \'`Enable\'\n            pc_pause_o = `Enable;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:98: Define or directive not defined: \'`Enable\'\n            id_pause_o = `Enable;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:99: Define or directive not defined: \'`Enable\'\n            ex_pause_o = `Enable;  \n                         ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:101: Define or directive not defined: \'`Disable\'\n            pc_pause_o = `Disable;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:102: Define or directive not defined: \'`Disable\'\n            id_pause_o = `Disable;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:103: Define or directive not defined: \'`Disable\'\n            ex_pause_o = `Disable;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:110: Define or directive not defined: \'`ZERO\'\n            reg1Addr_o = `ZERO;\n                         ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:111: Define or directive not defined: \'`ZERO\'\n            reg2Addr_o = `ZERO;\n                         ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:112: Define or directive not defined: \'`Disable\'\n            re1_o = `Disable;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:113: Define or directive not defined: \'`Disable\'\n            re2_o = `Disable;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:116: Define or directive not defined: \'`ZERO\'\n            operand1_o = `ZERO;\n                         ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:117: Define or directive not defined: \'`ZERO\'\n            operand2_o = `ZERO;\n                         ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:118: Define or directive not defined: \'`ALU_NOP_OP\'\n            aluOp_o = `ALU_NOP_OP;\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:121: Define or directive not defined: \'`MEM_NOP_OP\'\n            memOp_o = `MEM_NOP_OP;\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:124: Define or directive not defined: \'`Disable\'\n            wreg_o = `Disable;\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:128: Define or directive not defined: \'`ZERO\'\n            branchPC_o = `ZERO;\n                         ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:129: Define or directive not defined: \'`Disable\'\n            branchFlag_o = `Disable;\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:133: Define or directive not defined: \'`EXE_SLL_SRA\'\n            `EXE_SLL_SRA: begin\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:133: syntax error, unexpected \':\', expecting endcase\n            `EXE_SLL_SRA: begin\n                        ^\n%Error: data/full_repos/permissive/156129873/verilog/id.v:138: Define or directive not defined: \'`Enable\'\n                        re1_o = `Enable;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:143: Define or directive not defined: \'`ALU_SLL_OP\'\n                        aluOp_o = `ALU_SLL_OP;\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:145: Define or directive not defined: \'`Enable\'\n                        wreg_o = `Enable;\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:151: Define or directive not defined: \'`Enable\'\n                        re1_o = `Enable;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:156: Define or directive not defined: \'`ALU_SRA_OP\'\n                        aluOp_o = `ALU_SRA_OP;\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:158: Define or directive not defined: \'`Enable\'\n                        wreg_o = `Enable;\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:168: Define or directive not defined: \'`EXE_ADDU_SUBU\'\n            `EXE_ADDU_SUBU: begin\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:173: Define or directive not defined: \'`Enable\'\n                        re1_o = `Enable;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:175: Define or directive not defined: \'`Enable\'\n                        re2_o = `Enable;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:180: Define or directive not defined: \'`ALU_ADDU_OP\'\n                        aluOp_o = `ALU_ADDU_OP;\n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:182: Define or directive not defined: \'`Enable\'\n                        wreg_o = `Enable;\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:188: Define or directive not defined: \'`Enable\'\n                        re1_o = `Enable;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:190: Define or directive not defined: \'`Enable\'\n                        re2_o = `Enable;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:195: Define or directive not defined: \'`ALU_SUBU_OP\'\n                        aluOp_o = `ALU_SUBU_OP;\n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:197: Define or directive not defined: \'`Enable\'\n                        wreg_o = `Enable;\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:207: Define or directive not defined: \'`EXE_AND_OR_CMP_SLTU_MFPC_JR_JRRA_JALR\'\n            `EXE_AND_OR_CMP_SLTU_MFPC_JR_JRRA_JALR: begin\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:212: Define or directive not defined: \'`Enable\'\n                        re1_o = `Enable;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/id.v:214: Define or directive not defined: \'`Enable\'\n                        re2_o = `Enable;\n                                ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module id(


    input wire[15:0] pc_i,
    input wire[15:0] ins_i,
    

    input wire[15:0] reg1Data_i,
    input wire[15:0] reg2Data_i,
    


    input wire ex_writeReg_i,
    input wire[3:0] ex_writeRegAddr_i,
    input wire[15:0] ex_writeData_i,



    input wire mem_writeReg_i,
    input wire[3:0] mem_writeRegAddr_i,
    input wire[15:0] mem_writeData_i,


    input wire[1:0] lastMemOp_i,
    input wire[3:0] lastRegAddr_i,



    output reg[15:0] branchPC_o,
    output reg branchFlag_o,


    output reg pc_pause_o,


    output reg[3:0] reg1Addr_o,
    output reg[3:0] reg2Addr_o,
    output reg re1_o,
    output reg re2_o,


    output reg id_pause_o,


    output reg[15:0] operand1_o,
    output reg[15:0] operand2_o,
    output reg[4:0] aluOp_o,
    output reg ex_pause_o,


    output reg[1:0] memOp_o,


    output reg wreg_o,
    output reg[3:0] wd_o
    );


    wire[4:0] op = ins_i[15:11];
    wire[2:0] sec1 = ins_i[10:8];
    wire[2:0] sec2 = ins_i[7:5];
    wire[2:0] sec3 = ins_i[4:2];
    wire[1:0] sec4 = ins_i[1:0];

    reg[15:0] regData1;
    reg[15:0] regData2;
    

    always @(*) begin
        if (re1_o == `Enable && ex_writeReg_i == `Enable && reg1Addr_o == ex_writeRegAddr_i) begin
            regData1 = ex_writeData_i;
        end else if (re1_o == `Enable && mem_writeReg_i == `Enable && reg1Addr_o == mem_writeRegAddr_i) begin
            regData1 = mem_writeData_i;
        end else begin
            regData1 = reg1Data_i;
        end
    end


    always @(*) begin
        if (re2_o == `Enable && ex_writeReg_i == `Enable && reg2Addr_o == ex_writeRegAddr_i) begin
            regData2 = ex_writeData_i;
        end else if (re2_o == `Enable && mem_writeReg_i == `Enable && reg2Addr_o == mem_writeRegAddr_i) begin
            regData2 = mem_writeData_i;
        end else begin
            regData2 = reg2Data_i;
        end
    end


    always @(*) begin
        if (lastMemOp_i == `MEM_READ_OP && 
            ((lastRegAddr_i == reg1Addr_o && re1_o == `Enable) || 
				(lastRegAddr_i == reg2Addr_o && re2_o == `Enable))) begin
            pc_pause_o = `Enable;
            id_pause_o = `Enable;
            ex_pause_o = `Enable;  
        end else begin
            pc_pause_o = `Disable;
            id_pause_o = `Disable;
            ex_pause_o = `Disable;
        end
    end


    always @(*) begin

            reg1Addr_o = `ZERO;
            reg2Addr_o = `ZERO;
            re1_o = `Disable;
            re2_o = `Disable;
        

            operand1_o = `ZERO;
            operand2_o = `ZERO;
            aluOp_o = `ALU_NOP_OP;


            memOp_o = `MEM_NOP_OP;


            wreg_o = `Disable;
            wd_o = 4'h0;


            branchPC_o = `ZERO;
            branchFlag_o = `Disable;

        case (op)

            `EXE_SLL_SRA: begin
                case(sec4)

                    2'b00: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = {13'b0, sec3};
                        aluOp_o = `ALU_SLL_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec1};
                    end

                    2'b11: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = {13'b0, sec3};
                        aluOp_o = `ALU_SRA_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec1};
                    end
                    default: begin
                    	
                    end
                endcase
            end


            `EXE_ADDU_SUBU: begin
                case(sec4)

                    2'b01: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_ADDU_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec3};
                    end

                    2'b11: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_SUBU_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec3};
                    end
                    default: begin
                    	
                    end
                endcase
            end


            `EXE_AND_OR_CMP_SLTU_MFPC_JR_JRRA_JALR: begin
                case({sec3,sec4})

                    5'b01100: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_AND_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec1};
                    end

                    5'b01101: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_OR_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec1};
                    end

                    5'b01010: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_CMP_OP;

                        wreg_o = `Enable;
                        wd_o = `REG_T;
                    end

                    5'b00011: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_SLTU_OP;

                        wreg_o = `Enable;
                        wd_o = `REG_T;
                    end

                    5'b00000: begin
                        case(sec2)

                        	3'b010: begin

                            	operand1_o = pc_i + 1;
                            	operand2_o = 16'b0;
                            	aluOp_o = `ALU_MFPC_OP;

                            	wreg_o = `Enable;
                            	wd_o = {1'b0,sec1};
                        	end

                        	3'b000: begin

                        		re1_o = `Enable;
                        		reg1Addr_o = {1'b0,sec1};

                        		operand1_o = 16'b0;
                        		operand2_o = 16'b0;
                        		aluOp_o = `ALU_JR_OP;

                        		branchPC_o = regData1;
                        		branchFlag_o = `Enable;
                        	end

                        	3'b001: begin

                        		re1_o = `Enable;
                        		reg1Addr_o = `REG_RA;

                        		operand1_o = 16'b0;
                        		operand2_o = 16'b0;
                        		aluOp_o = `ALU_JRRA_OP;

                        		branchPC_o = regData1;
                        		branchFlag_o = `Enable;
                        	end

                        	3'b110: begin

                        		re1_o = `Enable;
                        		reg1Addr_o = {1'b0,sec1};
                        		re2_o = `Enable;
                        		reg2Addr_o = `REG_RA;

                        		operand1_o = pc_i + 2;
                        		operand2_o = 16'b0;
                        		aluOp_o = `ALU_JALR_OP;

                        		branchPC_o = regData1;
                        		branchFlag_o = `Enable;

                        		wreg_o = `Enable;
                            	wd_o = `REG_RA;
                        	end
                        	default: begin
                    	
                    		end
                        endcase
                    end
                    default: begin
                    	
                    end
                endcase
            end


            `EXE_MTSP_ADDSP_SWRS_BTEQZ_BTNEZ: begin
                case(sec1)

                    3'b100: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = 16'b0;
                        aluOp_o = `ALU_MTSP_OP;

                        wreg_o = `Enable;
                        wd_o = `REG_SP;
                    end

                    3'b011: begin

                        re1_o = `Enable;
                        reg1Addr_o = `REG_SP;

                        operand1_o = regData1;
                        operand2_o = {{8{sec2[2]}},sec2,sec3,sec4};
                        aluOp_o = `ALU_ADDSP_OP;

                        wreg_o = `Enable;
                        wd_o = `REG_SP;
                    end

                    3'b010: begin

                        re1_o = `Enable;
                        reg1Addr_o = `REG_SP;
                        re2_o = `Enable;
                        reg2Addr_o = `REG_RA;

                        operand1_o = regData1 + {{8{sec2[2]}},sec2,sec3,sec4};
                        operand2_o = regData2;
                        aluOp_o = `ALU_SWRS_OP;

                		memOp_o = `MEM_WRITE_OP;
                    end

                    3'b000: begin

                		re1_o = `Enable;
                		reg1Addr_o = `REG_T;

                		aluOp_o = `ALU_BTEQZ_OP;

                		if(regData1 == 16'b0) begin
                			branchPC_o = pc_i + 1 + {{8{sec2[2]}},sec2,sec3,sec4};
                			branchFlag_o = `Enable;
                		end else begin
                			
                		end
                    end

                    3'b001: begin

                		re1_o = `Enable;
                		reg1Addr_o = `REG_T;

                		aluOp_o = `ALU_BTNEZ_OP;

                		if(regData1 == 16'b0) begin
                			
                		end else begin
                			branchPC_o = pc_i + 1 + {{8{sec2[2]}},sec2,sec3,sec4};
                			branchFlag_o = `Enable;
                		end
                    end
                    default: begin
                    	
                    end
                endcase
            end


            `EXE_MFIH_MTIH: begin
            	case(sec4)

            		2'b00: begin

                        re1_o = `Enable;
                        reg1Addr_o = `REG_IH;

                        operand1_o = regData1;
                        operand2_o = 16'b0;
                        aluOp_o = `ALU_MFIH_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec1};
            		end

            		2'b01: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};

                        operand1_o = regData1;
                        operand2_o = 16'b0;
                        aluOp_o = `ALU_MTIH_OP;

                        wreg_o = `Enable;
                        wd_o = `REG_IH;
            		end
            		default: begin
                    	
                    end
            	endcase
            end


            `EXE_ADDIU: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};

                operand1_o = regData1;
                operand2_o = {{8{sec2[2]}},sec2,sec3,sec4};
                aluOp_o = `ALU_ADDIU_OP;

                wreg_o = `Enable;
                wd_o = {1'b0,sec1};
            end


            `EXE_ADDIU3: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};

                operand1_o = regData1;
                operand2_o = {{12{sec3[1]}},sec3[1:0],sec4};
                aluOp_o = `ALU_ADDIU3_OP;

                wreg_o = `Enable;
                wd_o = {1'b0,sec2};
            end


            `EXE_LI: begin

                operand1_o = {{8{sec2[2]}},sec2,sec3,sec4};
                operand2_o = 16'b0;
                aluOp_o = `ALU_LI_OP;

                wreg_o = `Enable;
                wd_o = {1'b0,sec1};
            end


            `EXE_LW: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};

                operand1_o = regData1;
                operand2_o = {{11{sec3[2]}},sec3,sec4};
                aluOp_o = `ALU_LW_OP;

                wreg_o = `Enable;
                wd_o = {1'b0,sec2};

                memOp_o = `MEM_READ_OP;
            end


            `EXE_LWSP: begin

                re1_o = `Enable;
                reg1Addr_o = `REG_SP;

                operand1_o = regData1;
                operand2_o = {{8{sec2[2]}},sec2,sec3,sec4};
                aluOp_o = `ALU_LWSP_OP;

                wreg_o = `Enable;
                wd_o = {1'b0,sec1};

                memOp_o = `MEM_READ_OP;
            end


            `EXE_SW: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};
                re2_o = `Enable;
                reg2Addr_o = {1'b0,sec2};

                operand1_o = regData1 + {{11{sec3[2]}},sec3,sec4};
                operand2_o = regData2;
                aluOp_o = `ALU_SW_OP;

                memOp_o = `MEM_WRITE_OP;
            end


            `EXE_SWSP: begin

                re1_o = `Enable;
                reg1Addr_o = `REG_SP;
                re2_o = `Enable;
                reg2Addr_o = {1'b0,sec1};

                operand1_o = regData1 + {{8{sec2[2]}},sec2,sec3,sec4};
                operand2_o = regData2;
                aluOp_o = `ALU_SWSP_OP;

                memOp_o = `MEM_WRITE_OP;
            end


            `EXE_B: begin

                aluOp_o = `ALU_B_OP;

                branchPC_o = pc_i + 1 + {{5{sec1[2]}},sec1,sec2,sec3,sec4};
                branchFlag_o = `Enable;

            end


            `EXE_BEQZ: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};

                aluOp_o = `ALU_BEQZ_OP;

                if(regData1 == 16'b0) begin
                	branchPC_o = pc_i + 1 + {{8{sec2[2]}},sec2,sec3,sec4};
                	branchFlag_o = `Enable;
                end else begin
                	
                end
            end


            `EXE_BNEZ: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};

                aluOp_o = `ALU_BNEZ_OP;

                if(regData1 == 16'b0) begin
                	
                end else begin
                	branchPC_o = pc_i + 1 + {{8{sec2[2]}},sec2,sec3,sec4};
                	branchFlag_o = `Enable;
                end
            end


            `EXE_NOP: begin

                    operand1_o = 16'b0;
                    operand2_o = 16'b0;
                    aluOp_o = `ALU_NOP_OP;
            end

            default: begin

			end
		endcase
    end

endmodule
module id(


    input wire[15:0] pc_i,
    input wire[15:0] ins_i,
    

    input wire[15:0] reg1Data_i,
    input wire[15:0] reg2Data_i,
    


    input wire ex_writeReg_i,
    input wire[3:0] ex_writeRegAddr_i,
    input wire[15:0] ex_writeData_i,



    input wire mem_writeReg_i,
    input wire[3:0] mem_writeRegAddr_i,
    input wire[15:0] mem_writeData_i,


    input wire[1:0] lastMemOp_i,
    input wire[3:0] lastRegAddr_i,



    output reg[15:0] branchPC_o,
    output reg branchFlag_o,


    output reg pc_pause_o,


    output reg[3:0] reg1Addr_o,
    output reg[3:0] reg2Addr_o,
    output reg re1_o,
    output reg re2_o,


    output reg id_pause_o,


    output reg[15:0] operand1_o,
    output reg[15:0] operand2_o,
    output reg[4:0] aluOp_o,
    output reg ex_pause_o,


    output reg[1:0] memOp_o,


    output reg wreg_o,
    output reg[3:0] wd_o
    );



    wire[4:0] op = ins_i[15:11];
    wire[2:0] sec1 = ins_i[10:8];
    wire[2:0] sec2 = ins_i[7:5];
    wire[2:0] sec3 = ins_i[4:2];
    wire[1:0] sec4 = ins_i[1:0];

    reg[15:0] regData1;
    reg[15:0] regData2;
    

    always @(*) begin
        if (re1_o == `Enable && ex_writeReg_i == `Enable && reg1Addr_o == ex_writeRegAddr_i) begin
            regData1 = ex_writeData_i;
        end else if (re1_o == `Enable && mem_writeReg_i == `Enable && reg1Addr_o == mem_writeRegAddr_i) begin
            regData1 = mem_writeData_i;
        end else begin
            regData1 = reg1Data_i;
        end
    end


    always @(*) begin
        if (re2_o == `Enable && ex_writeReg_i == `Enable && reg2Addr_o == ex_writeRegAddr_i) begin
            regData2 = ex_writeData_i;
        end else if (re2_o == `Enable && mem_writeReg_i == `Enable && reg2Addr_o == mem_writeRegAddr_i) begin
            regData2 = mem_writeData_i;
        end else begin
            regData2 = reg2Data_i;
        end
    end


    always @(*) begin
        if (lastMemOp_i == `MEM_READ_OP && 
            ((lastRegAddr_i == reg1Addr_o && re1_o == `Enable) || 
				(lastRegAddr_i == reg2Addr_o && re2_o == `Enable))) begin
            pc_pause_o = `Enable;
            id_pause_o = `Enable;
            ex_pause_o = `Enable;  
        end else begin
            pc_pause_o = `Disable;
            id_pause_o = `Disable;
            ex_pause_o = `Disable;
        end
    end


    always @(*) begin

            reg1Addr_o = `ZERO;
            reg2Addr_o = `ZERO;
            re1_o = `Disable;
            re2_o = `Disable;
        

            operand1_o = `ZERO;
            operand2_o = `ZERO;
            aluOp_o = `ALU_NOP_OP;


            memOp_o = `MEM_NOP_OP;


            wreg_o = `Disable;
            wd_o = 4'h0;


            branchPC_o = `ZERO;
            branchFlag_o = `Disable;

        case (op)

            `EXE_SLL_SRA: begin
                case(sec4)

                    2'b00: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = {13'b0, sec3};
                        aluOp_o = `ALU_SLL_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec1};
                    end

                    2'b11: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = {13'b0, sec3};
                        aluOp_o = `ALU_SRA_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec1};
                    end
                    default: begin
                    	
                    end
                endcase
            end


            `EXE_ADDU_SUBU: begin
                case(sec4)

                    2'b01: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_ADDU_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec3};
                    end

                    2'b11: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_SUBU_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec3};
                    end
                    default: begin
                    	
                    end
                endcase
            end


            `EXE_AND_OR_CMP_SLTU_MFPC_JR_JRRA_JALR: begin
                case({sec3,sec4})

                    5'b01100: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_AND_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec1};
                    end

                    5'b01101: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_OR_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec1};
                    end

                    5'b01010: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_CMP_OP;

                        wreg_o = `Enable;
                        wd_o = `REG_T;
                    end

                    5'b00011: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};
                        re2_o = `Enable;
                        reg2Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = regData2;
                        aluOp_o = `ALU_SLTU_OP;

                        wreg_o = `Enable;
                        wd_o = `REG_T;
                    end

                    5'b00000: begin
                        case(sec2)

                        	3'b010: begin

                            	operand1_o = pc_i + 1;
                            	operand2_o = 16'b0;
                            	aluOp_o = `ALU_MFPC_OP;

                            	wreg_o = `Enable;
                            	wd_o = {1'b0,sec1};
                        	end

                        	3'b000: begin

                        		re1_o = `Enable;
                        		reg1Addr_o = {1'b0,sec1};

                        		operand1_o = 16'b0;
                        		operand2_o = 16'b0;
                        		aluOp_o = `ALU_JR_OP;

                        		branchPC_o = regData1;
                        		branchFlag_o = `Enable;
                        	end

                        	3'b001: begin

                        		re1_o = `Enable;
                        		reg1Addr_o = `REG_RA;

                        		operand1_o = 16'b0;
                        		operand2_o = 16'b0;
                        		aluOp_o = `ALU_JRRA_OP;

                        		branchPC_o = regData1;
                        		branchFlag_o = `Enable;
                        	end

                        	3'b110: begin

                        		re1_o = `Enable;
                        		reg1Addr_o = {1'b0,sec1};
                        		re2_o = `Enable;
                        		reg2Addr_o = `REG_RA;

                        		operand1_o = pc_i + 2;
                        		operand2_o = 16'b0;
                        		aluOp_o = `ALU_JALR_OP;

                        		branchPC_o = regData1;
                        		branchFlag_o = `Enable;

                        		wreg_o = `Enable;
                            	wd_o = `REG_RA;
                        	end
                        	default: begin
                    	
                    		end
                        endcase
                    end
                    default: begin
                    	
                    end
                endcase
            end


            `EXE_MTSP_ADDSP_SWRS_BTEQZ_BTNEZ: begin
                case(sec1)

                    3'b100: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec2};

                        operand1_o = regData1;
                        operand2_o = 16'b0;
                        aluOp_o = `ALU_MTSP_OP;

                        wreg_o = `Enable;
                        wd_o = `REG_SP;
                    end

                    3'b011: begin

                        re1_o = `Enable;
                        reg1Addr_o = `REG_SP;

                        operand1_o = regData1;
                        operand2_o = {{8{sec2[2]}},sec2,sec3,sec4};
                        aluOp_o = `ALU_ADDSP_OP;

                        wreg_o = `Enable;
                        wd_o = `REG_SP;
                    end

                    3'b010: begin

                        re1_o = `Enable;
                        reg1Addr_o = `REG_SP;
                        re2_o = `Enable;
                        reg2Addr_o = `REG_RA;

                        operand1_o = regData1 + {{8{sec2[2]}},sec2,sec3,sec4};
                        operand2_o = regData2;
                        aluOp_o = `ALU_SWRS_OP;

                		memOp_o = `MEM_WRITE_OP;
                    end

                    3'b000: begin

                		re1_o = `Enable;
                		reg1Addr_o = `REG_T;

                		aluOp_o = `ALU_BTEQZ_OP;

                		if(regData1 == 16'b0) begin
                			branchPC_o = pc_i + 1 + {{8{sec2[2]}},sec2,sec3,sec4};
                			branchFlag_o = `Enable;
                		end else begin
                			
                		end
                    end

                    3'b001: begin

                		re1_o = `Enable;
                		reg1Addr_o = `REG_T;

                		aluOp_o = `ALU_BTNEZ_OP;

                		if(regData1 == 16'b0) begin
                			
                		end else begin
                			branchPC_o = pc_i + 1 + {{8{sec2[2]}},sec2,sec3,sec4};
                			branchFlag_o = `Enable;
                		end
                    end
                    default: begin
                    	
                    end
                endcase
            end


            `EXE_MFIH_MTIH: begin
            	case(sec4)

            		2'b00: begin

                        re1_o = `Enable;
                        reg1Addr_o = `REG_IH;

                        operand1_o = regData1;
                        operand2_o = 16'b0;
                        aluOp_o = `ALU_MFIH_OP;

                        wreg_o = `Enable;
                        wd_o = {1'b0,sec1};
            		end

            		2'b01: begin

                        re1_o = `Enable;
                        reg1Addr_o = {1'b0,sec1};

                        operand1_o = regData1;
                        operand2_o = 16'b0;
                        aluOp_o = `ALU_MTIH_OP;

                        wreg_o = `Enable;
                        wd_o = `REG_IH;
            		end
            		default: begin
                    	
                    end
            	endcase
            end


            `EXE_ADDIU: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};

                operand1_o = regData1;
                operand2_o = {{8{sec2[2]}},sec2,sec3,sec4};
                aluOp_o = `ALU_ADDIU_OP;

                wreg_o = `Enable;
                wd_o = {1'b0,sec1};
            end


            `EXE_ADDIU3: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};

                operand1_o = regData1;
                operand2_o = {{12{sec3[1]}},sec3[1:0],sec4};
                aluOp_o = `ALU_ADDIU3_OP;

                wreg_o = `Enable;
                wd_o = {1'b0,sec2};
            end


            `EXE_LI: begin

                operand1_o = {{8{sec2[2]}},sec2,sec3,sec4};
                operand2_o = 16'b0;
                aluOp_o = `ALU_LI_OP;

                wreg_o = `Enable;
                wd_o = {1'b0,sec1};
            end


            `EXE_LW: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};

                operand1_o = regData1;
                operand2_o = {{11{sec3[2]}},sec3,sec4};
                aluOp_o = `ALU_LW_OP;

                wreg_o = `Enable;
                wd_o = {1'b0,sec2};

                memOp_o = `MEM_READ_OP;
            end


            `EXE_LWSP: begin

                re1_o = `Enable;
                reg1Addr_o = `REG_SP;

                operand1_o = regData1;
                operand2_o = {{8{sec2[2]}},sec2,sec3,sec4};
                aluOp_o = `ALU_LWSP_OP;

                wreg_o = `Enable;
                wd_o = {1'b0,sec1};

                memOp_o = `MEM_READ_OP;
            end


            `EXE_SW: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};
                re2_o = `Enable;
                reg2Addr_o = {1'b0,sec2};

                operand1_o = regData1 + {{11{sec3[2]}},sec3,sec4};
                operand2_o = regData2;
                aluOp_o = `ALU_SW_OP;

                memOp_o = `MEM_WRITE_OP;
            end


            `EXE_SWSP: begin

                re1_o = `Enable;
                reg1Addr_o = `REG_SP;
                re2_o = `Enable;
                reg2Addr_o = {1'b0,sec1};

                operand1_o = regData1 + {{8{sec2[2]}},sec2,sec3,sec4};
                operand2_o = regData2;
                aluOp_o = `ALU_SWSP_OP;

                memOp_o = `MEM_WRITE_OP;
            end


            `EXE_B: begin

                aluOp_o = `ALU_B_OP;

                branchPC_o = pc_i + 1 + {{5{sec1[2]}},sec1,sec2,sec3,sec4};
                branchFlag_o = `Enable;

            end


            `EXE_BEQZ: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};

                aluOp_o = `ALU_BEQZ_OP;

                if(regData1 == 16'b0) begin
                	branchPC_o = pc_i + 1 + {{8{sec2[2]}},sec2,sec3,sec4};
                	branchFlag_o = `Enable;
                end else begin
                	
                end
            end


            `EXE_BNEZ: begin

                re1_o = `Enable;
                reg1Addr_o = {1'b0,sec1};

                aluOp_o = `ALU_BNEZ_OP;

                if(regData1 == 16'b0) begin
                	
                end else begin
                	branchPC_o = pc_i + 1 + {{8{sec2[2]}},sec2,sec3,sec4};
                	branchFlag_o = `Enable;
                end
            end


            `EXE_NOP: begin

                    operand1_o = 16'b0;
                    operand2_o = 16'b0;
                    aluOp_o = `ALU_NOP_OP;
            end

            default: begin

			end
		endcase
    end

endmodule