data/full_repos/permissive/173099254/lab6/cod.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173099254/lab6/cod.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #5 clock = ~clock; load =0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab6/cod.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #5 clock = ~clock;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab6/cod.v:105: Unsupported: Ignoring delay on this delayed statement.\n       #5 reset =0;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab6/cod.v:110: Unsupported: Ignoring delay on this delayed statement.\n       #5 load =0;\n       ^\n%Warning-MULTITOP: data/full_repos/permissive/173099254/lab6/cod.v:77: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                     : ... Top module \'numarator_test\'\nmodule numarator_test();\n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'desc_numarator_test\'\nmodule desc_numarator_test();\n       ^~~~~~~~~~~~~~~~~~~\n%Warning-INFINITELOOP: data/full_repos/permissive/173099254/lab6/cod.v:69: Infinite loop (condition always true)\n                                                                         : ... In instance numarator_test\n  forever\n  ^~~~~~~\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module desc_numarator_test();

reg [3:0] data;
reg up_down;
reg enable;
reg load;
reg clock;
reg reset;
wire [3:0] result;
wire terminal_count;
integer i;


initial begin
  reset =0;
  clock = 0;
  enable = 1;
  data =10;
  up_down =0;
  load =0;
  clock =0;
  
  for(i = 0; i < 20; i = i+1)
    begin
    #5 clock = ~clock;
    if(i == 10)
      begin
       reset = 1;
       #5 reset =0;
     end
    if(i == 2)
    begin
       load = 1;
       #5 load =0;
    end
  end
end
numarator4 num4_test(data, up_down, enable, load, clock, reset, result, terminal_count);
endmodule
module desc_numarator_test();


reg [3:0] data;
reg up_down;
reg enable;
reg load;
reg clock;
reg reset;
wire [3:0] result;
wire terminal_count;
integer i;


initial begin
  reset =0;
  clock = 0;
  enable = 1;
  data =10;
  up_down =0;
  load =0;
  clock =0;
  
  for(i = 0; i < 20; i = i+1)
    begin
    #5 clock = ~clock;
    if(i == 10)
      begin
       reset = 1;
       #5 reset =0;
     end
    if(i == 2)
    begin
       load = 1;
       #5 load =0;
    end
  end
end
numarator4 num4_test(data, up_down, enable, load, clock, reset, result, terminal_count);
endmodule