data/full_repos/permissive/21438680/DAQ_Firmware/modelsim/control_unit_testbench.v
 line:77: before: "reset"
1: b'%Warning-STMTDLY: data/full_repos/permissive/21438680/DAQ_Firmware/modelsim/control_unit_testbench.v:65: Unsupported: Ignoring delay on this delayed statement.\nalways #( CLK_PERIOD/2.0 )\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/modelsim/control_unit_testbench.v:96: Unsupported or unknown PLI call: $writememb\n    $writememb("memory_binary.txt", memory);\n    ^~~~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_unit_testbench
  (

  );


reg sys_clk;
reg reset;

integer i;

parameter CLK_PERIOD = 10;
parameter MEM_WORDS = 128;

wire        read_req;
wire        write_req;
wire [16:0] addr;
wire [31:0] data_o;
reg  [31:0] data_i;
reg         busy;


reg [31:0] mem[0:MEM_WORDS-1];

control_unit control_unit_inst (
  .clk ( sys_clk ),
  .reset ( reset ),

  .memory_read_req ( read_req ),
  .memory_write_req ( write_req ),
  .memory_addr ( addr ),
  .memory_data_o ( data_o ),
  .memory_data_i ( data_i ),
  .memory_busy ( busy )
);
initial i = 0;

initial sys_clk = 1'b0;
always #( CLK_PERIOD/2.0 )
  sys_clk = ~sys_clk;

initial reset = 1'b1;
always @( posedge sys_clk ) begin
  i = i + 1;
  if ( i == 2 )
    reset <= 1'b0;
end

initial $readmemh("instructions.txt", mem);

always @(posedge sys_clk or reset) begin
  if ( ~reset ) begin
    busy <= 0;
    if ( read_req ) begin
      data_i <= mem[addr>>2];
    end
    if ( write_req ) begin
      mem[addr>>2] <= data_o;
    end
  end
end

integer j;
reg [7:0] memory [0:15];

initial begin
    for (j=0; j<16; j=j+1) begin
        memory[j] = j;
    end
    $writememb("memory_binary.txt", memory);
    $writememh("memory_hex.txt", memory);
end
endmodule
module control_unit_testbench
  (

  );



reg sys_clk;
reg reset;

integer i;

parameter CLK_PERIOD = 10;
parameter MEM_WORDS = 128;

wire        read_req;
wire        write_req;
wire [16:0] addr;
wire [31:0] data_o;
reg  [31:0] data_i;
reg         busy;


reg [31:0] mem[0:MEM_WORDS-1];

control_unit control_unit_inst (
  .clk ( sys_clk ),
  .reset ( reset ),

  .memory_read_req ( read_req ),
  .memory_write_req ( write_req ),
  .memory_addr ( addr ),
  .memory_data_o ( data_o ),
  .memory_data_i ( data_i ),
  .memory_busy ( busy )
);
initial i = 0;

initial sys_clk = 1'b0;
always #( CLK_PERIOD/2.0 )
  sys_clk = ~sys_clk;

initial reset = 1'b1;
always @( posedge sys_clk ) begin
  i = i + 1;
  if ( i == 2 )
    reset <= 1'b0;
end

initial $readmemh("instructions.txt", mem);

always @(posedge sys_clk or reset) begin
  if ( ~reset ) begin
    busy <= 0;
    if ( read_req ) begin
      data_i <= mem[addr>>2];
    end
    if ( write_req ) begin
      mem[addr>>2] <= data_o;
    end
  end
end

integer j;
reg [7:0] memory [0:15];

initial begin
    for (j=0; j<16; j=j+1) begin
        memory[j] = j;
    end
    $writememb("memory_binary.txt", memory);
    $writememh("memory_hex.txt", memory);
end
endmodule