data/full_repos/permissive/143278/ivltests/specify4.v
 line:10: before: "$"
1: b'%Error: data/full_repos/permissive/143278/ivltests/specify4.v:10: Unsupported or unknown PLI call: $monitor\n      #10 $monitor($time,,"q=%b, d=%b, c=%b", q, d, c);\n          ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/specify4.v:10: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      #10 $monitor($time,,"q=%b, d=%b, c=%b", q, d, c);\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/specify4.v:10: Unsupported: Ignoring delay on this delayed statement.\n      #10 $monitor($time,,"q=%b, d=%b, c=%b", q, d, c);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/specify4.v:11: Unsupported: Ignoring delay on this delayed statement.\n      #5 c = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/specify4.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #5 c = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/specify4.v:13: Unsupported: Ignoring delay on this delayed statement.\n      #5 c = 0; d = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/specify4.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #5 c = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/specify4.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #5 c = 0; d = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/specify4.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #5 c = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/specify4.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #10 $finish(0);\n      ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
   reg d, c;
   wire q;

   initial begin
      d = 0;
      c = 1;
      #10 $monitor($time,,"q=%b, d=%b, c=%b", q, d, c);
      #5 c = 0;
      #5 c = 1;
      #5 c = 0; d = 1;
      #5 c = 1;
      #5 c = 0; d = 0;
      #5 c = 1;
      #10 $finish(0);
   end

   mydff g1 (q, d, c);

endmodule
module top;

   reg d, c;
   wire q;

   initial begin
      d = 0;
      c = 1;
      #10 $monitor($time,,"q=%b, d=%b, c=%b", q, d, c);
      #5 c = 0;
      #5 c = 1;
      #5 c = 0; d = 1;
      #5 c = 1;
      #5 c = 0; d = 0;
      #5 c = 1;
      #10 $finish(0);
   end

   mydff g1 (q, d, c);

endmodule