data/full_repos/permissive/160794640/example/forstmt.v
 line:6: before: "logic"
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/160794640/example/forstmt.v:6: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'cnt'\n                                                                            : ... In instance forstmt\n     for (logic [7:0] i = 0; i < 10; i=i+1) cnt <= cnt + 1;\n                                            ^~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module forstmt(
               input        clk,
               output [7:0] cnt);

   always @(posedge clk)
     for (logic [7:0] i = 0; i < 10; i=i+1) cnt <= cnt + 1;

endmodule
module forstmt(
               input        clk,
               output [7:0] cnt);


   always @(posedge clk)
     for (logic [7:0] i = 0; i < 10; i=i+1) cnt <= cnt + 1;

endmodule