data/full_repos/permissive/164482394/Verilog/MIDI_baudrate_generator.v
data/verilator_xmls/12b680ef-1af3-4afa-ab5c-588947f5c4fe.xml
module MIDI_BaudRate_generator(
    Clk                   ,
    Rst_n                 ,
    Tick                  ,
    BaudRate
    );

input           Clk                 ;
input           Rst_n               ;
input [15:0]    BaudRate            ;
output  reg        Tick                ;
reg [15:0]      baudRateReg         ;


always @(posedge Clk or negedge Rst_n)
begin
    if (!Rst_n) baudRateReg <= 16'b0;
	 else begin
		 if (baudRateReg <= BaudRate) baudRateReg <= baudRateReg + 1'b1;
		 else
		 begin
			baudRateReg <= 16'b0;
			Tick <= ~Tick;
		 end
	 end
end
endmodule
module MIDI_BaudRate_generator(
    Clk                   ,
    Rst_n                 ,
    Tick                  ,
    BaudRate
    );


input           Clk                 ;
input           Rst_n               ;
input [15:0]    BaudRate            ;
output  reg        Tick                ;
reg [15:0]      baudRateReg         ;


always @(posedge Clk or negedge Rst_n)
begin
    if (!Rst_n) baudRateReg <= 16'b0;
	 else begin
		 if (baudRateReg <= BaudRate) baudRateReg <= baudRateReg + 1'b1;
		 else
		 begin
			baudRateReg <= 16'b0;
			Tick <= ~Tick;
		 end
	 end
end
endmodule