data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v
'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte
1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n             const_defination.v\n             const_defination.v.v\n             const_defination.v.sv\n             obj_dir/const_defination.v\n             obj_dir/const_defination.v.v\n             obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:25: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] pc,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`digitsBus] pc,\n                         ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:26: Define or directive not defined: \'`MaxIntroduction\'\n    output reg[`MaxIntroduction] intd,\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:30: Define or directive not defined: \'`introduction_memory_size\'\n    reg[7:0] intds[`introduction_memory_size];    \n                   ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:31: syntax error, unexpected initial\n    initial $readmemh ( "E:/vivado project/myY-86/test.txt",intds );  \n    ^~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:35: Define or directive not defined: \'`introduction_memory_length\'\n        if(pc<`introduction_memory_length)\n              ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/introduction_memory.v:40: Define or directive not defined: \'`introduction_memory_length\'\n        else if(pc>`introduction_memory_length)\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module introduction_memory(
    input wire[`digitsBus] pc,
    output reg[`MaxIntroduction] intd,
	output reg imem_error
    );
    
    reg[7:0] intds[`introduction_memory_size];
    initial $readmemh ( "E:/vivado project/myY-86/test.txt",intds );  
    
    always@(*)
    begin
        if(pc<`introduction_memory_length)
        begin
            intd={intds[pc][7:0],intds[pc+1][7:0],intds[pc+2][7:0],intds[pc+3][7:0],intds[pc+4][7:0],intds[pc+5][7:0],intds[pc+6][7:0],intds[pc+7][7:0],intds[pc+8][7:0],intds[pc+9][7:0]};
			imem_error=0;
		end
        else if(pc>`introduction_memory_length)
		begin
			imem_error=1;
		end
		else
        begin
            intd=80'h10000000000000000000;
			imem_error=0;
        end
    end
    
endmodule
module introduction_memory(
    input wire[`digitsBus] pc,
    output reg[`MaxIntroduction] intd,
	output reg imem_error
    );

    
    reg[7:0] intds[`introduction_memory_size];
    initial $readmemh ( "E:/vivado project/myY-86/test.txt",intds );  
    
    always@(*)
    begin
        if(pc<`introduction_memory_length)
        begin
            intd={intds[pc][7:0],intds[pc+1][7:0],intds[pc+2][7:0],intds[pc+3][7:0],intds[pc+4][7:0],intds[pc+5][7:0],intds[pc+6][7:0],intds[pc+7][7:0],intds[pc+8][7:0],intds[pc+9][7:0]};
			imem_error=0;
		end
        else if(pc>`introduction_memory_length)
		begin
			imem_error=1;
		end
		else
        begin
            intd=80'h10000000000000000000;
			imem_error=0;
        end
    end
    
endmodule