data/full_repos/permissive/143278/ivltests/udp_real_delay.v
 line:3: before: "primitive"
1: b'%Error: data/full_repos/permissive/143278/ivltests/udp_real_delay.v:32: Unsupported or unknown PLI call: $monitor\n  $monitor($realtime,,a,,b,,y);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/udp_real_delay.v:32: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  $monitor($realtime,,a,,b,,y);\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_real_delay.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #0.6 if (y !== 1\'b0) failed = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_real_delay.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #0.4 if (y !== 1\'b0) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_real_delay.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #0.2 if (y !== 1\'b1) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_real_delay.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #0.4 if (y !== 1\'b1) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_real_delay.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #0.2 if (y !== 1\'b0) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_real_delay.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #0.4 if (y !== 1\'b0) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_real_delay.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #0.2 if (y !== 1\'b1) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_real_delay.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #0.4 if (y !== 1\'b1) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_real_delay.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #0.2 if (y !== 1\'b0) failed = 1;\n  ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

reg         a;
reg         b;
wire        y;

udp_and #0.5 gate(y, a, b);

reg failed = 0;

initial begin
  $monitor($realtime,,a,,b,,y);
  a = 0; b = 0;
  #0.6 if (y !== 1'b0) failed = 1;
  a = 1; b = 1;
  #0.4 if (y !== 1'b0) failed = 1;
  #0.2 if (y !== 1'b1) failed = 1;
  a = 0; b = 1;
  #0.4 if (y !== 1'b1) failed = 1;
  #0.2 if (y !== 1'b0) failed = 1;
  a = 1; b = 1;
  #0.4 if (y !== 1'b0) failed = 1;
  #0.2 if (y !== 1'b1) failed = 1;
  a = 1; b = 0;
  #0.4 if (y !== 1'b1) failed = 1;
  #0.2 if (y !== 1'b0) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module test();


reg         a;
reg         b;
wire        y;

udp_and #0.5 gate(y, a, b);

reg failed = 0;

initial begin
  $monitor($realtime,,a,,b,,y);
  a = 0; b = 0;
  #0.6 if (y !== 1'b0) failed = 1;
  a = 1; b = 1;
  #0.4 if (y !== 1'b0) failed = 1;
  #0.2 if (y !== 1'b1) failed = 1;
  a = 0; b = 1;
  #0.4 if (y !== 1'b1) failed = 1;
  #0.2 if (y !== 1'b0) failed = 1;
  a = 1; b = 1;
  #0.4 if (y !== 1'b0) failed = 1;
  #0.2 if (y !== 1'b1) failed = 1;
  a = 1; b = 0;
  #0.4 if (y !== 1'b1) failed = 1;
  #0.2 if (y !== 1'b0) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule