data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/lib/SN74LS27.v
data/verilator_xmls/bb53fd00-444c-4f1c-b53e-58538d1ac947.xml
module SN74LS27
(
    input wire a1,
    input wire b1, 
    input wire c1,
    output wire y1,
    
    input wire a2,
    input wire b2, 
    input wire c2,
    output wire y2,
    
    input wire a3,
    input wire b3, 
    input wire c3,
    output wire y3
);

assign y1 = ~a1 & ~b1 & ~c1;
assign y2 = ~a2 & ~b2 & ~c2;
assign y3 = ~a3 & ~b3 & ~c3;

endmodule
module SN74LS27
(
    input wire a1,
    input wire b1, 
    input wire c1,
    output wire y1,
    
    input wire a2,
    input wire b2, 
    input wire c2,
    output wire y2,
    
    input wire a3,
    input wire b3, 
    input wire c3,
    output wire y3
);


assign y1 = ~a1 & ~b1 & ~c1;
assign y2 = ~a2 & ~b2 & ~c2;
assign y3 = ~a3 & ~b3 & ~c3;

endmodule