data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/JK_flip_flop/jk_flip_flop.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/JK_flip_flop/jk_flip_flop.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #100 clk=1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/JK_flip_flop/jk_flip_flop.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #100 clk=0;J=0;K=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/JK_flip_flop/jk_flip_flop.v:24: Unsupported: Ignoring delay on this delayed statement.\n                #100 J=1;K=1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/JK_flip_flop/jk_flip_flop.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #100 clk=1;J=1;K=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/JK_flip_flop/jk_flip_flop.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #100 clk=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/JK_flip_flop/jk_flip_flop.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #100 J=1;K=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/JK_flip_flop/jk_flip_flop.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #100 clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/JK_flip_flop/jk_flip_flop.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #100 clk=1;J=0;K=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/JK_flip_flop/jk_flip_flop.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #100 clk=1;J=1;K=1;\n  ^\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_JK_flip_flop();
	wire Q,Q_b;
	reg J,K,clk;
	JK_flip_flop G(Q,Q_b,J,K,clk);
	initial
		begin
		J=0;K=1;clk=0;
		#100 clk=1;
		#100 clk=0;J=0;K=0;
       	        #100 J=1;K=1;
		#100 clk=1;J=1;K=0;
		#100 clk=0;
		#100 J=1;K=1;
		#100 clk=1;
		#100 clk=1;J=0;K=1;
		#100 clk=1;J=1;K=1;
	end
endmodule
module test_JK_flip_flop();

	wire Q,Q_b;
	reg J,K,clk;
	JK_flip_flop G(Q,Q_b,J,K,clk);
	initial
		begin
		J=0;K=1;clk=0;
		#100 clk=1;
		#100 clk=0;J=0;K=0;
       	        #100 J=1;K=1;
		#100 clk=1;J=1;K=0;
		#100 clk=0;
		#100 J=1;K=1;
		#100 clk=1;
		#100 clk=1;J=0;K=1;
		#100 clk=1;J=1;K=1;
	end
endmodule