data/full_repos/permissive/197042892/hardware/17.srcs/trigger_in.v
data/verilator_xmls/56d555c3-f4fc-40af-ac72-34f3c67be75f.xml
module trigger_in(
	input wire trigger_in_pc,
	input wire trigger_in_external,
	input wire trig_source,
	input wire clock,
	input wire reset,
	input wire resetflag,
	input wire channel_disable,
	input wire channel_is_disable,
	
	output reg flag,
	output reg new_trig,
	output reg no_trig
    );
	
	wire trigger_in;
	wire present_stage;
    reg previous_stage;
	wire next_flag;
	reg prev_trig;
	reg prev_flag;
	reg [31:0] counter;
	wire next_no_trig;
	
	assign trigger_in = channel_is_disable ? 1'b0 
					  : (trig_source == 1'b1) ? trigger_in_external 
					  : trigger_in_pc;
	assign next_flag = flag;
	assign next_no_trig = no_trig;

	always @ (negedge clock) begin
		if (trigger_in) begin
			prev_trig <= 1'b1;
		end else begin
			prev_trig <= 1'b0;
		end
	end
	
	always @ (negedge clock) begin
		if (reset | resetflag | channel_disable | channel_is_disable) begin
			prev_flag <= 1'b0;
		end else begin
			prev_flag <= flag;
		end
		
		if (reset | resetflag| channel_disable | channel_is_disable) begin
			flag <= 1'b0;
		end else if (trigger_in && ~prev_trig) begin
			flag <= 1'b1;
		end else begin
			flag <= next_flag;			
		end
	end
	
	always @ (negedge clock) begin
		if (reset | resetflag | channel_disable | channel_is_disable) new_trig <= 1'b0;
		else if (trigger_in && ~prev_trig && prev_flag) new_trig <= 1'b1;
		else new_trig <= 1'b0;
	end
	
	always @ (negedge clock) begin
		if (reset | flag | channel_disable | channel_is_disable) begin
			counter <= 0;
		end else begin
			counter <= counter + 1;
		end
	end
	
	always @ (negedge clock) begin
		if (reset | flag | channel_disable | channel_is_disable) no_trig <= 1'b0;
		else if (~flag && counter >= 32'h8E56E58) begin
			no_trig <= 1'b1;
		end else begin
			no_trig <= next_no_trig;
		end
	end
	
endmodule
module trigger_in(
	input wire trigger_in_pc,
	input wire trigger_in_external,
	input wire trig_source,
	input wire clock,
	input wire reset,
	input wire resetflag,
	input wire channel_disable,
	input wire channel_is_disable,
	
	output reg flag,
	output reg new_trig,
	output reg no_trig
    );

	
	wire trigger_in;
	wire present_stage;
    reg previous_stage;
	wire next_flag;
	reg prev_trig;
	reg prev_flag;
	reg [31:0] counter;
	wire next_no_trig;
	
	assign trigger_in = channel_is_disable ? 1'b0 
					  : (trig_source == 1'b1) ? trigger_in_external 
					  : trigger_in_pc;
	assign next_flag = flag;
	assign next_no_trig = no_trig;

	always @ (negedge clock) begin
		if (trigger_in) begin
			prev_trig <= 1'b1;
		end else begin
			prev_trig <= 1'b0;
		end
	end
	
	always @ (negedge clock) begin
		if (reset | resetflag | channel_disable | channel_is_disable) begin
			prev_flag <= 1'b0;
		end else begin
			prev_flag <= flag;
		end
		
		if (reset | resetflag| channel_disable | channel_is_disable) begin
			flag <= 1'b0;
		end else if (trigger_in && ~prev_trig) begin
			flag <= 1'b1;
		end else begin
			flag <= next_flag;			
		end
	end
	
	always @ (negedge clock) begin
		if (reset | resetflag | channel_disable | channel_is_disable) new_trig <= 1'b0;
		else if (trigger_in && ~prev_trig && prev_flag) new_trig <= 1'b1;
		else new_trig <= 1'b0;
	end
	
	always @ (negedge clock) begin
		if (reset | flag | channel_disable | channel_is_disable) begin
			counter <= 0;
		end else begin
			counter <= counter + 1;
		end
	end
	
	always @ (negedge clock) begin
		if (reset | flag | channel_disable | channel_is_disable) no_trig <= 1'b0;
		else if (~flag && counter >= 32'h8E56E58) begin
			no_trig <= 1'b1;
		end else begin
			no_trig <= next_no_trig;
		end
	end
	
endmodule