data/full_repos/permissive/143278/ivltests/pr1002a.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1002a.v:14: Unsupported: Ignoring delay on this delayed statement.\n     #1 datain = 14\'h0FFF;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1002a.v:15: Unsupported: Ignoring delay on this delayed statement.\n     #1 datain = 14\'h0000;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1002a.v:16: Unsupported: Ignoring delay on this delayed statement.\n     #1 datain = 14\'h1FFF;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1002a.v:17: Unsupported: Ignoring delay on this delayed statement.\n     #1 datain = 14\'h1000;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1002a.v:18: Unsupported: Ignoring delay on this delayed statement.\n     #1 datain = 14\'h2FFF;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1002a.v:19: Unsupported: Ignoring delay on this delayed statement.\n     #1 datain = 14\'h2000;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1002a.v:20: Unsupported: Ignoring delay on this delayed statement.\n     #1 datain = 14\'h3FFF;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1002a.v:21: Unsupported: Ignoring delay on this delayed statement.\n     #1 datain = 14\'h3000;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1002a.v:22: Unsupported: Ignoring delay on this delayed statement.\n     #2;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1002a.v:7: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'datain\' generates 14 bits.\n                                                                      : ... In instance top\nassign dataout = datain <<< 2;\n                        ^~~\n%Error: Exiting due to 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top (
	    );

reg signed [13:0] datain;
wire signed [15:0] dataout;

assign dataout = datain <<< 2;

reg test_failed;

initial
  begin
     test_failed = 0;
     #1 datain = 14'h0FFF;
     #1 datain = 14'h0000;
     #1 datain = 14'h1FFF;
     #1 datain = 14'h1000;
     #1 datain = 14'h2FFF;
     #1 datain = 14'h2000;
     #1 datain = 14'h3FFF;
     #1 datain = 14'h3000;
     #2;
     if (test_failed)
       $display("TEST FAILED :-(");
     else
       $display("TEST PASSED :-)");
  end

wire signed [15:0] expected_dataout;

assign expected_dataout = $signed({datain[13:0], 2'b0});

always @(dataout)
  if (expected_dataout != dataout)
    begin
       $display("datain = %d dataout = %d expected = %d ... CHECK FAILED", datain, dataout, expected_dataout);
       test_failed = 1;
    end
  else
    $display("datain = %d dataout = %d expected = %d ... CHECK PASSED", datain, dataout, expected_dataout);

endmodule
module top (
	    );


reg signed [13:0] datain;
wire signed [15:0] dataout;

assign dataout = datain <<< 2;

reg test_failed;

initial
  begin
     test_failed = 0;
     #1 datain = 14'h0FFF;
     #1 datain = 14'h0000;
     #1 datain = 14'h1FFF;
     #1 datain = 14'h1000;
     #1 datain = 14'h2FFF;
     #1 datain = 14'h2000;
     #1 datain = 14'h3FFF;
     #1 datain = 14'h3000;
     #2;
     if (test_failed)
       $display("TEST FAILED :-(");
     else
       $display("TEST PASSED :-)");
  end

wire signed [15:0] expected_dataout;

assign expected_dataout = $signed({datain[13:0], 2'b0});

always @(dataout)
  if (expected_dataout != dataout)
    begin
       $display("datain = %d dataout = %d expected = %d ... CHECK FAILED", datain, dataout, expected_dataout);
       test_failed = 1;
    end
  else
    $display("datain = %d dataout = %d expected = %d ... CHECK PASSED", datain, dataout, expected_dataout);

endmodule