data/full_repos/permissive/123649059/PwmGenor.v
1: b'%Warning-WIDTH: data/full_repos/permissive/123649059/PwmGenor.v:35: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                  : ... In instance PwmGenor\n  cnt <= 1\'b0;\n      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/123649059/PwmGenor.v:43: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                  : ... In instance PwmGenor\n   cnt <= 1\'b0;\n       ^~\n%Error: Exiting due to 2 warning(s)\n'
module PwmGenor(
	clk,
	rst_n,
	col_n,
	cycle,
	duty,
	out
);

parameter OUT0        = 1'b0;
parameter CYCLE_WIDTH = 8;
parameter DUTY_WIDTH  = CYCLE_WIDTH;

input                  clk;
input                  rst_n;
input                  col_n;
input[CYCLE_WIDTH-1:0] cycle;
input[DUTY_WIDTH -1:0] duty;
output                 out;

reg                   out;
wire                  out0;
reg [CYCLE_WIDTH-1:0] cnt;
wire[CYCLE_WIDTH-1:0] r_cycle;
wire[DUTY_WIDTH -1:0] r_duty;

assign r_cycle = cycle - 1'b1;
assign r_duty  = duty  - 1'b1;
assign out0    = col_n ? OUT0 : (~OUT0);

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt <= 1'b0;
		out <= out0;
	end else begin
		cnt <= cnt + 1'b1;
		if(cnt == r_duty) begin
			out <= ~out0;
		end else if(cnt == r_cycle) begin
			out <= out0;
			cnt <= 1'b0;
		end
	end
end

endmodule
module PwmGenor(
	clk,
	rst_n,
	col_n,
	cycle,
	duty,
	out
);


parameter OUT0        = 1'b0;
parameter CYCLE_WIDTH = 8;
parameter DUTY_WIDTH  = CYCLE_WIDTH;

input                  clk;
input                  rst_n;
input                  col_n;
input[CYCLE_WIDTH-1:0] cycle;
input[DUTY_WIDTH -1:0] duty;
output                 out;

reg                   out;
wire                  out0;
reg [CYCLE_WIDTH-1:0] cnt;
wire[CYCLE_WIDTH-1:0] r_cycle;
wire[DUTY_WIDTH -1:0] r_duty;

assign r_cycle = cycle - 1'b1;
assign r_duty  = duty  - 1'b1;
assign out0    = col_n ? OUT0 : (~OUT0);

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt <= 1'b0;
		out <= out0;
	end else begin
		cnt <= cnt + 1'b1;
		if(cnt == r_duty) begin
			out <= ~out0;
		end else if(cnt == r_cycle) begin
			out <= out0;
			cnt <= 1'b0;
		end
	end
end

endmodule