data/full_repos/permissive/143278/ivltests/pr3368642.v
 line:14: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3368642.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b %b %b", r1, w1, w2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr3368642.v:16: Unsupported: Verilog 1995 force\n  force w1 = 4\'bz;\n  ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3368642.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b %b %b", r1, w1, w2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3368642.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b %b %b", r1, w1, w2);\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/pr3368642.v:22: Unsupported: Verilog 1995 release\n  release w1;\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3368642.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b %b %b", r1, w1, w2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3368642.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b %b %b", r1, w1, w2);\n  ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug;

reg  [3:0] r1;
wire [3:0] w1;
wire [3:0] w2;

assign w1 = r1;
assign w2 = w1;

reg fail = 0;

initial begin
  r1 = 0;
  #1 $display("%b %b %b", r1, w1, w2);
  if ((r1 !== 4'b0000) || (w1 !== 4'b0000) || (w2 !== 4'b0000)) fail = 1;
  force w1 = 4'bz;
  #1 $display("%b %b %b", r1, w1, w2);
  if ((r1 !== 4'b0000) || (w1 !== 4'bzzzz) || (w2 !== 4'bzzzz)) fail = 1;
  r1 = 1;
  #1 $display("%b %b %b", r1, w1, w2);
  if ((r1 !== 4'b0001) || (w1 !== 4'bzzzz) || (w2 !== 4'bzzzz)) fail = 1;
  release w1;
  #1 $display("%b %b %b", r1, w1, w2);
  if ((r1 !== 4'b0001) || (w1 !== 4'b0001) || (w2 !== 4'b0001)) fail = 1;
  r1 = 2;
  #1 $display("%b %b %b", r1, w1, w2);
  if ((r1 !== 4'b0010) || (w1 !== 4'b0010) || (w2 !== 4'b0010)) fail = 1;

  if (fail)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module bug;


reg  [3:0] r1;
wire [3:0] w1;
wire [3:0] w2;

assign w1 = r1;
assign w2 = w1;

reg fail = 0;

initial begin
  r1 = 0;
  #1 $display("%b %b %b", r1, w1, w2);
  if ((r1 !== 4'b0000) || (w1 !== 4'b0000) || (w2 !== 4'b0000)) fail = 1;
  force w1 = 4'bz;
  #1 $display("%b %b %b", r1, w1, w2);
  if ((r1 !== 4'b0000) || (w1 !== 4'bzzzz) || (w2 !== 4'bzzzz)) fail = 1;
  r1 = 1;
  #1 $display("%b %b %b", r1, w1, w2);
  if ((r1 !== 4'b0001) || (w1 !== 4'bzzzz) || (w2 !== 4'bzzzz)) fail = 1;
  release w1;
  #1 $display("%b %b %b", r1, w1, w2);
  if ((r1 !== 4'b0001) || (w1 !== 4'b0001) || (w2 !== 4'b0001)) fail = 1;
  r1 = 2;
  #1 $display("%b %b %b", r1, w1, w2);
  if ((r1 !== 4'b0010) || (w1 !== 4'b0010) || (w2 !== 4'b0010)) fail = 1;

  if (fail)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule