data/full_repos/permissive/169225814/modules/gpio/rtl/gpio.v
data/verilator_xmls/704f2da8-b21e-4efe-a710-9975069cc1b1.xml
module gpio (

	input hclk,
	input hresetn,

	input [31:0] 	  haddr,
	input         	  hsel,
	input [31:0]  	  hwdata,
	input         	  hwrite,
	output reg [31:0] hrdata,
	output reg   	  hready,
	output 		      hresp,



	output wire 	  intc,




	output wire [3:0] gpio_out,
	input  wire [3:0]   gpio_in
	);
	




	wire       valid_write;
	wire       valid_read;
	reg[31:0]  write_addr;
	reg[31:0]  read_addr;
	reg        valid_write_lat;
	reg[31:0]  read_data;

	reg	   err_dec_rd_d1;
	reg	   err_dec_rd_d2;

	reg        err_dec_rd;
	wire       err_dec_wr;

	reg 	   gpio0_sync1;
	reg 	   gpio1_sync1;
	reg 	   gpio2_sync1;
	reg 	   gpio3_sync1;

	reg 	   gpio0_sync2;
	reg 	   gpio1_sync2;
	reg 	   gpio2_sync2;
	reg 	   gpio3_sync2;

	reg 	   gpio0_in;
	reg 	   gpio1_in;
	reg 	   gpio2_in;
	reg 	   gpio3_in;


	reg        gpio0_ctl_wr_en;
	reg	   gpio0_out_wr_en;
	reg 	   gpio1_ctl_wr_en;
	reg 	   gpio1_out_wr_en;
	reg 	   gpio2_ctl_wr_en;
	reg 	   gpio2_out_wr_en;
	reg	   gpio3_ctl_wr_en;
	reg	   gpio3_out_wr_en;




        wire[31:0]  gpio0_in_data;
	wire[31:0]  gpio1_in_data;
	wire[31:0]  gpio2_in_data;
	wire[31:0]  gpio3_in_data;




	reg[31:0]  gpio0_ctl_data;
	reg[31:0]  gpio0_out_data;
	reg[31:0]  gpio1_ctl_data;
	reg[31:0]  gpio1_out_data;
	reg[31:0]  gpio2_ctl_data;
	reg[31:0]  gpio2_out_data;
	reg[31:0]  gpio3_ctl_data;
	reg[31:0]  gpio3_out_data;

	reg[3:0]  intc_loc;



	
    localparam GPIO0_CTL_ADDR = 16'h0000;
    localparam GPIO0_OUT_ADDR = 16'h0004;
    localparam GPIO0_IN_ADDR  = 16'h0008;
 	localparam GPIO1_CTL_ADDR = 16'h000C;
 	localparam GPIO1_OUT_ADDR = 16'h0010;
 	localparam GPIO1_IN_ADDR  = 16'h0014;
 	localparam GPIO2_CTL_ADDR = 16'h0018;
 	localparam GPIO2_OUT_ADDR = 16'h001C;
 	localparam GPIO2_IN_ADDR  = 16'h0020;
 	localparam GPIO3_CTL_ADDR = 16'h0024;
 	localparam GPIO3_OUT_ADDR = 16'h0028;
 	localparam GPIO3_IN_ADDR  = 16'h002C;




assign valid_write = hsel & hwrite;
assign valid_read  = hsel & ~hwrite;





always @(posedge hclk or negedge hresetn) begin
  if (hresetn == 1'b0) begin
    write_addr       <= 32'b0;
    valid_write_lat  <= 1'b0;
  end
  else if (valid_write) begin
    write_addr       <= haddr;
    valid_write_lat  <= valid_write;
  end
  else begin
    write_addr       <= 32'b0;
    valid_write_lat  <= 1'b0;
  end 
end



































 always @ (write_addr, valid_write_lat) begin
   gpio0_ctl_wr_en = 1'b0;
   gpio0_out_wr_en = 1'b0;
   gpio1_ctl_wr_en = 1'b0;
   gpio1_out_wr_en = 1'b0;
   gpio2_ctl_wr_en = 1'b0;
   gpio2_out_wr_en = 1'b0;
   gpio3_ctl_wr_en = 1'b0;
   gpio3_out_wr_en = 1'b0;
   case(write_addr[15:0])
     GPIO0_CTL_ADDR : begin
       gpio0_ctl_wr_en = valid_write_lat;
     end
     GPIO0_OUT_ADDR : begin
	gpio0_out_wr_en = valid_write_lat;
     end
     GPIO1_CTL_ADDR : begin
	gpio1_ctl_wr_en = valid_write_lat;
     end
     GPIO1_OUT_ADDR : begin
	gpio1_out_wr_en = valid_write_lat;
     end
     GPIO2_CTL_ADDR : begin
	gpio2_ctl_wr_en = valid_write_lat;
     end
     GPIO2_OUT_ADDR : begin
	gpio2_out_wr_en = valid_write_lat;
     end
     GPIO3_CTL_ADDR : begin
	gpio3_ctl_wr_en = valid_write_lat;
     end
     GPIO3_OUT_ADDR : begin
	gpio3_out_wr_en = valid_write_lat;
     end
     default : begin
       gpio0_ctl_wr_en = 1'b0;
       gpio0_out_wr_en = 1'b0;
       gpio1_ctl_wr_en = 1'b0;
       gpio1_out_wr_en = 1'b0;
       gpio2_ctl_wr_en = 1'b0;
       gpio2_out_wr_en = 1'b0;
       gpio3_ctl_wr_en = 1'b0;
       gpio3_out_wr_en = 1'b0;
     end
   endcase  
 end










always @* begin
  if (gpio0_ctl_data[0] == 1'b1) begin
     if (gpio0_sync2 & ~gpio0_in & gpio0_ctl_data[1]) begin
	intc_loc[0] = 1'b1;
      end
      else if (~gpio0_sync2 & gpio0_in & ~gpio0_ctl_data[1]) begin
    	intc_loc[0] = 1'b1;
      end
      else begin
 	intc_loc[0] = 1'b0; 
      end
  end
  else begin
 	  intc_loc[0] = 1'b0; 
  end
end

always @* begin
  if (gpio1_ctl_data[0] == 1'b1) begin     
      if (gpio1_sync2 &  ~gpio1_in & gpio1_ctl_data[1]) begin 
        intc_loc[1] = 1'b1;
      end
      else if (~gpio1_sync2 & gpio1_in & ~gpio1_ctl_data[1]) begin 
        intc_loc[1] = 1'b1;
      end
      else begin
        intc_loc[1] = 1'b0;
      end
  end
  else begin
          intc_loc[1] = 1'b0;
  end
end


always @* begin
  if (gpio2_ctl_data[0] == 1'b1) begin
      if (gpio2_sync2 & ~gpio2_in & gpio2_ctl_data[1]) begin
        intc_loc[2] = 1'b1;
      end
      else if (~gpio2_sync2 & gpio2_in & ~gpio2_ctl_data[1]) begin
        intc_loc[2] = 1'b1;
      end
      else begin
        intc_loc[2] = 1'b0;
      end
  end
  else begin
          intc_loc[2] = 1'b0;
  end
end


always @* begin
  if (gpio3_ctl_data[0] == 1'b1) begin
      if (gpio3_sync2 & ~gpio3_in & gpio3_ctl_data[1]) begin
        intc_loc[3] = 1'b1;
      end
      else if (~gpio2_sync2 & gpio2_in & ~gpio3_ctl_data[1]) begin
        intc_loc[3] = 1'b1;
      end
      else begin
        intc_loc[3] = 1'b0;
      end
  end
  else begin
          intc_loc[3] = 1'b0;
  end
end


assign intc = intc_loc[0] | intc_loc[1] | intc_loc[2] | intc_loc[3];












always @*  begin
 err_dec_rd = 1'b0;
 if (valid_read == 1) begin
   case(haddr[15:0])
     GPIO0_CTL_ADDR  : begin
	   read_data = gpio0_ctl_data;
     end
     GPIO0_OUT_ADDR  : begin
	   read_data = gpio0_out_data;
     end
     GPIO0_IN_ADDR  : begin
	   read_data = gpio0_in_data;
     end
     GPIO1_CTL_ADDR : begin
       read_data = gpio1_ctl_data;
     end
     GPIO1_OUT_ADDR  : begin
	   read_data = gpio1_out_data;
     end
     GPIO1_IN_ADDR  : begin
	   read_data = gpio1_in_data;
     end
     GPIO2_CTL_ADDR  : begin
       read_data = gpio2_ctl_data;     
     end
     GPIO2_OUT_ADDR  : begin
       read_data = gpio2_out_data;
     end
     GPIO2_IN_ADDR  : begin
       read_data = gpio2_in_data;
     end
     GPIO3_CTL_ADDR  : begin
       read_data = gpio3_ctl_data;
     end
     GPIO3_OUT_ADDR  : begin
       read_data = gpio3_out_data;
     end
     GPIO3_IN_ADDR  : begin
       read_data = gpio3_in_data;
     end
     default : begin
       read_data = 32'h0;
       err_dec_rd = 1'b1;
     end
  endcase
 end
 else begin
   read_data = 32'h0;
 end
end
















  
 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     gpio0_ctl_data <= 32'h0;
     gpio0_out_data <= 32'h0;
     gpio1_ctl_data <= 32'h0;
     gpio1_out_data <= 32'h0;
     gpio2_ctl_data <= 32'h0;
     gpio2_out_data <= 32'h0;
     gpio3_ctl_data <= 32'h0;
     gpio3_out_data <= 32'h0;
   end
   else begin
     if (gpio0_ctl_wr_en == 1'b1) begin
       gpio0_ctl_data <= hwdata;
     end
     if (gpio0_out_wr_en == 1'b1) begin
       gpio0_out_data <= hwdata;
     end
     if (gpio1_ctl_wr_en == 1'b1) begin
	gpio1_ctl_data <= hwdata;
     end
     if (gpio1_out_wr_en == 1'b1) begin
	gpio1_out_data <= hwdata;
     end
     if (gpio2_ctl_wr_en == 1'b1) begin
	gpio2_ctl_data <= hwdata;
     end
     if (gpio2_out_wr_en == 1'b1) begin
	gpio2_out_data <= hwdata;
     end
     if (gpio3_ctl_wr_en == 1'b1) begin
	gpio3_ctl_data <= hwdata;
     end
     if (gpio3_out_wr_en == 1'b1) begin
	 gpio3_out_data <= hwdata;
     end
   end
 end
	




assign gpio_out[0] = gpio0_out_data[0];
assign gpio_out[1] = gpio1_out_data[0];
assign gpio_out[2] = gpio2_out_data[0];
assign gpio_out[3] = gpio3_out_data[0];








 always @ (posedge hclk or negedge hresetn) begin       
   if (hresetn == 1'b0) begin
	gpio0_sync1 <= 1'b0;
	gpio1_sync1 <= 1'b0;
	gpio2_sync1 <= 1'b0;
	gpio3_sync1 <= 1'b0;
	gpio0_sync2 <= 1'b0;
	gpio1_sync2 <= 1'b0;
	gpio2_sync2 <= 1'b0;
	gpio3_sync2 <= 1'b0;
	gpio0_in    <= 1'b0;
	gpio1_in    <= 1'b0;
	gpio2_in    <= 1'b0;
	gpio3_in    <= 1'b0;
   end
   else begin
    gpio0_sync1 <= gpio_in[0];
	gpio1_sync1 <= gpio_in[1];
	gpio2_sync1 <= gpio_in[2];
	gpio3_sync1 <= gpio_in[3];      
    gpio0_sync2 <= gpio0_sync1;
	gpio1_sync2 <= gpio1_sync1;
	gpio2_sync2 <= gpio2_sync1;
	gpio3_sync2 <= gpio3_sync1;      
    gpio0_in    <= gpio0_sync2;
	gpio1_in    <= gpio1_sync2;
	gpio2_in    <= gpio2_sync2;
	gpio3_in    <= gpio3_sync2;      
   end
 end

 assign gpio0_in_data = {31'b0, gpio0_in};
 assign gpio1_in_data = {31'b0, gpio1_in};
 assign gpio2_in_data = {31'b0, gpio2_in};
 assign gpio3_in_data = {31'b0, gpio3_in};









 always @ (posedge hclk or negedge hresetn) begin       
   if (hresetn == 1'b0) begin
	 hrdata <= 32'h0;
   end
   else begin
     hrdata    <= read_data;      
   end
 end














always @(posedge hclk or negedge hresetn) begin         
  if (hresetn == 1'b0) begin
    err_dec_rd_d1  <= 1'b0;
    err_dec_rd_d2  <= 1'b0;
  end
  else begin
    err_dec_rd_d1  <= err_dec_rd;
    err_dec_rd_d2  <= err_dec_rd_d1;
  end
end

assign hresp = err_dec_rd_d1 | err_dec_rd_d2;


always @(posedge hclk or negedge hresetn) begin         
  if (hresetn == 1'b0) begin
    hready  <= 1'b1;
  end
  else if (err_dec_rd) begin
    hready  <= 1'b0;
  end
  else begin
    hready  <= 1'b1;
  end
end



endmodule
module gpio (

	input hclk,
	input hresetn,

	input [31:0] 	  haddr,
	input         	  hsel,
	input [31:0]  	  hwdata,
	input         	  hwrite,
	output reg [31:0] hrdata,
	output reg   	  hready,
	output 		      hresp,



	output wire 	  intc,




	output wire [3:0] gpio_out,
	input  wire [3:0]   gpio_in
	);

	




	wire       valid_write;
	wire       valid_read;
	reg[31:0]  write_addr;
	reg[31:0]  read_addr;
	reg        valid_write_lat;
	reg[31:0]  read_data;

	reg	   err_dec_rd_d1;
	reg	   err_dec_rd_d2;

	reg        err_dec_rd;
	wire       err_dec_wr;

	reg 	   gpio0_sync1;
	reg 	   gpio1_sync1;
	reg 	   gpio2_sync1;
	reg 	   gpio3_sync1;

	reg 	   gpio0_sync2;
	reg 	   gpio1_sync2;
	reg 	   gpio2_sync2;
	reg 	   gpio3_sync2;

	reg 	   gpio0_in;
	reg 	   gpio1_in;
	reg 	   gpio2_in;
	reg 	   gpio3_in;


	reg        gpio0_ctl_wr_en;
	reg	   gpio0_out_wr_en;
	reg 	   gpio1_ctl_wr_en;
	reg 	   gpio1_out_wr_en;
	reg 	   gpio2_ctl_wr_en;
	reg 	   gpio2_out_wr_en;
	reg	   gpio3_ctl_wr_en;
	reg	   gpio3_out_wr_en;




        wire[31:0]  gpio0_in_data;
	wire[31:0]  gpio1_in_data;
	wire[31:0]  gpio2_in_data;
	wire[31:0]  gpio3_in_data;




	reg[31:0]  gpio0_ctl_data;
	reg[31:0]  gpio0_out_data;
	reg[31:0]  gpio1_ctl_data;
	reg[31:0]  gpio1_out_data;
	reg[31:0]  gpio2_ctl_data;
	reg[31:0]  gpio2_out_data;
	reg[31:0]  gpio3_ctl_data;
	reg[31:0]  gpio3_out_data;

	reg[3:0]  intc_loc;



	
    localparam GPIO0_CTL_ADDR = 16'h0000;
    localparam GPIO0_OUT_ADDR = 16'h0004;
    localparam GPIO0_IN_ADDR  = 16'h0008;
 	localparam GPIO1_CTL_ADDR = 16'h000C;
 	localparam GPIO1_OUT_ADDR = 16'h0010;
 	localparam GPIO1_IN_ADDR  = 16'h0014;
 	localparam GPIO2_CTL_ADDR = 16'h0018;
 	localparam GPIO2_OUT_ADDR = 16'h001C;
 	localparam GPIO2_IN_ADDR  = 16'h0020;
 	localparam GPIO3_CTL_ADDR = 16'h0024;
 	localparam GPIO3_OUT_ADDR = 16'h0028;
 	localparam GPIO3_IN_ADDR  = 16'h002C;




assign valid_write = hsel & hwrite;
assign valid_read  = hsel & ~hwrite;





always @(posedge hclk or negedge hresetn) begin
  if (hresetn == 1'b0) begin
    write_addr       <= 32'b0;
    valid_write_lat  <= 1'b0;
  end
  else if (valid_write) begin
    write_addr       <= haddr;
    valid_write_lat  <= valid_write;
  end
  else begin
    write_addr       <= 32'b0;
    valid_write_lat  <= 1'b0;
  end 
end



































 always @ (write_addr, valid_write_lat) begin
   gpio0_ctl_wr_en = 1'b0;
   gpio0_out_wr_en = 1'b0;
   gpio1_ctl_wr_en = 1'b0;
   gpio1_out_wr_en = 1'b0;
   gpio2_ctl_wr_en = 1'b0;
   gpio2_out_wr_en = 1'b0;
   gpio3_ctl_wr_en = 1'b0;
   gpio3_out_wr_en = 1'b0;
   case(write_addr[15:0])
     GPIO0_CTL_ADDR : begin
       gpio0_ctl_wr_en = valid_write_lat;
     end
     GPIO0_OUT_ADDR : begin
	gpio0_out_wr_en = valid_write_lat;
     end
     GPIO1_CTL_ADDR : begin
	gpio1_ctl_wr_en = valid_write_lat;
     end
     GPIO1_OUT_ADDR : begin
	gpio1_out_wr_en = valid_write_lat;
     end
     GPIO2_CTL_ADDR : begin
	gpio2_ctl_wr_en = valid_write_lat;
     end
     GPIO2_OUT_ADDR : begin
	gpio2_out_wr_en = valid_write_lat;
     end
     GPIO3_CTL_ADDR : begin
	gpio3_ctl_wr_en = valid_write_lat;
     end
     GPIO3_OUT_ADDR : begin
	gpio3_out_wr_en = valid_write_lat;
     end
     default : begin
       gpio0_ctl_wr_en = 1'b0;
       gpio0_out_wr_en = 1'b0;
       gpio1_ctl_wr_en = 1'b0;
       gpio1_out_wr_en = 1'b0;
       gpio2_ctl_wr_en = 1'b0;
       gpio2_out_wr_en = 1'b0;
       gpio3_ctl_wr_en = 1'b0;
       gpio3_out_wr_en = 1'b0;
     end
   endcase  
 end










always @* begin
  if (gpio0_ctl_data[0] == 1'b1) begin
     if (gpio0_sync2 & ~gpio0_in & gpio0_ctl_data[1]) begin
	intc_loc[0] = 1'b1;
      end
      else if (~gpio0_sync2 & gpio0_in & ~gpio0_ctl_data[1]) begin
    	intc_loc[0] = 1'b1;
      end
      else begin
 	intc_loc[0] = 1'b0; 
      end
  end
  else begin
 	  intc_loc[0] = 1'b0; 
  end
end

always @* begin
  if (gpio1_ctl_data[0] == 1'b1) begin     
      if (gpio1_sync2 &  ~gpio1_in & gpio1_ctl_data[1]) begin 
        intc_loc[1] = 1'b1;
      end
      else if (~gpio1_sync2 & gpio1_in & ~gpio1_ctl_data[1]) begin 
        intc_loc[1] = 1'b1;
      end
      else begin
        intc_loc[1] = 1'b0;
      end
  end
  else begin
          intc_loc[1] = 1'b0;
  end
end


always @* begin
  if (gpio2_ctl_data[0] == 1'b1) begin
      if (gpio2_sync2 & ~gpio2_in & gpio2_ctl_data[1]) begin
        intc_loc[2] = 1'b1;
      end
      else if (~gpio2_sync2 & gpio2_in & ~gpio2_ctl_data[1]) begin
        intc_loc[2] = 1'b1;
      end
      else begin
        intc_loc[2] = 1'b0;
      end
  end
  else begin
          intc_loc[2] = 1'b0;
  end
end


always @* begin
  if (gpio3_ctl_data[0] == 1'b1) begin
      if (gpio3_sync2 & ~gpio3_in & gpio3_ctl_data[1]) begin
        intc_loc[3] = 1'b1;
      end
      else if (~gpio2_sync2 & gpio2_in & ~gpio3_ctl_data[1]) begin
        intc_loc[3] = 1'b1;
      end
      else begin
        intc_loc[3] = 1'b0;
      end
  end
  else begin
          intc_loc[3] = 1'b0;
  end
end


assign intc = intc_loc[0] | intc_loc[1] | intc_loc[2] | intc_loc[3];












always @*  begin
 err_dec_rd = 1'b0;
 if (valid_read == 1) begin
   case(haddr[15:0])
     GPIO0_CTL_ADDR  : begin
	   read_data = gpio0_ctl_data;
     end
     GPIO0_OUT_ADDR  : begin
	   read_data = gpio0_out_data;
     end
     GPIO0_IN_ADDR  : begin
	   read_data = gpio0_in_data;
     end
     GPIO1_CTL_ADDR : begin
       read_data = gpio1_ctl_data;
     end
     GPIO1_OUT_ADDR  : begin
	   read_data = gpio1_out_data;
     end
     GPIO1_IN_ADDR  : begin
	   read_data = gpio1_in_data;
     end
     GPIO2_CTL_ADDR  : begin
       read_data = gpio2_ctl_data;     
     end
     GPIO2_OUT_ADDR  : begin
       read_data = gpio2_out_data;
     end
     GPIO2_IN_ADDR  : begin
       read_data = gpio2_in_data;
     end
     GPIO3_CTL_ADDR  : begin
       read_data = gpio3_ctl_data;
     end
     GPIO3_OUT_ADDR  : begin
       read_data = gpio3_out_data;
     end
     GPIO3_IN_ADDR  : begin
       read_data = gpio3_in_data;
     end
     default : begin
       read_data = 32'h0;
       err_dec_rd = 1'b1;
     end
  endcase
 end
 else begin
   read_data = 32'h0;
 end
end
















  
 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     gpio0_ctl_data <= 32'h0;
     gpio0_out_data <= 32'h0;
     gpio1_ctl_data <= 32'h0;
     gpio1_out_data <= 32'h0;
     gpio2_ctl_data <= 32'h0;
     gpio2_out_data <= 32'h0;
     gpio3_ctl_data <= 32'h0;
     gpio3_out_data <= 32'h0;
   end
   else begin
     if (gpio0_ctl_wr_en == 1'b1) begin
       gpio0_ctl_data <= hwdata;
     end
     if (gpio0_out_wr_en == 1'b1) begin
       gpio0_out_data <= hwdata;
     end
     if (gpio1_ctl_wr_en == 1'b1) begin
	gpio1_ctl_data <= hwdata;
     end
     if (gpio1_out_wr_en == 1'b1) begin
	gpio1_out_data <= hwdata;
     end
     if (gpio2_ctl_wr_en == 1'b1) begin
	gpio2_ctl_data <= hwdata;
     end
     if (gpio2_out_wr_en == 1'b1) begin
	gpio2_out_data <= hwdata;
     end
     if (gpio3_ctl_wr_en == 1'b1) begin
	gpio3_ctl_data <= hwdata;
     end
     if (gpio3_out_wr_en == 1'b1) begin
	 gpio3_out_data <= hwdata;
     end
   end
 end
	




assign gpio_out[0] = gpio0_out_data[0];
assign gpio_out[1] = gpio1_out_data[0];
assign gpio_out[2] = gpio2_out_data[0];
assign gpio_out[3] = gpio3_out_data[0];








 always @ (posedge hclk or negedge hresetn) begin       
   if (hresetn == 1'b0) begin
	gpio0_sync1 <= 1'b0;
	gpio1_sync1 <= 1'b0;
	gpio2_sync1 <= 1'b0;
	gpio3_sync1 <= 1'b0;
	gpio0_sync2 <= 1'b0;
	gpio1_sync2 <= 1'b0;
	gpio2_sync2 <= 1'b0;
	gpio3_sync2 <= 1'b0;
	gpio0_in    <= 1'b0;
	gpio1_in    <= 1'b0;
	gpio2_in    <= 1'b0;
	gpio3_in    <= 1'b0;
   end
   else begin
    gpio0_sync1 <= gpio_in[0];
	gpio1_sync1 <= gpio_in[1];
	gpio2_sync1 <= gpio_in[2];
	gpio3_sync1 <= gpio_in[3];      
    gpio0_sync2 <= gpio0_sync1;
	gpio1_sync2 <= gpio1_sync1;
	gpio2_sync2 <= gpio2_sync1;
	gpio3_sync2 <= gpio3_sync1;      
    gpio0_in    <= gpio0_sync2;
	gpio1_in    <= gpio1_sync2;
	gpio2_in    <= gpio2_sync2;
	gpio3_in    <= gpio3_sync2;      
   end
 end

 assign gpio0_in_data = {31'b0, gpio0_in};
 assign gpio1_in_data = {31'b0, gpio1_in};
 assign gpio2_in_data = {31'b0, gpio2_in};
 assign gpio3_in_data = {31'b0, gpio3_in};









 always @ (posedge hclk or negedge hresetn) begin       
   if (hresetn == 1'b0) begin
	 hrdata <= 32'h0;
   end
   else begin
     hrdata    <= read_data;      
   end
 end














always @(posedge hclk or negedge hresetn) begin         
  if (hresetn == 1'b0) begin
    err_dec_rd_d1  <= 1'b0;
    err_dec_rd_d2  <= 1'b0;
  end
  else begin
    err_dec_rd_d1  <= err_dec_rd;
    err_dec_rd_d2  <= err_dec_rd_d1;
  end
end

assign hresp = err_dec_rd_d1 | err_dec_rd_d2;


always @(posedge hclk or negedge hresetn) begin         
  if (hresetn == 1'b0) begin
    hready  <= 1'b1;
  end
  else if (err_dec_rd) begin
    hready  <= 1'b0;
  end
  else begin
    hready  <= 1'b1;
  end
end



endmodule