data/full_repos/permissive/14432793/rfid-verilog/tag/epc.v
data/verilator_xmls/0f93018b-ae9a-40f3-a49f-e02154166858.xml
module epc(reset, epcclk, epcbitout, epcdone);
input reset, epcclk;
output epcbitout, epcdone;

wire [111:0] epc;
assign epc = 112'h3000aabbccddeeff012345678910;

reg [6:0] bitoutcounter;
assign epcbitout = epc[bitoutcounter];
assign epcdone = (bitoutcounter == 0);
reg    initialized;

always @ (posedge epcclk or posedge reset) begin
  if (reset) begin
    bitoutcounter <= 0;
    initialized   <= 0;
  end else if (!initialized) begin
    bitoutcounter <= 111;
    initialized <= 1;
  end else if (!epcdone) begin
    bitoutcounter <= bitoutcounter - 7'd1;
  end else begin
  end
end

endmodule
module epc(reset, epcclk, epcbitout, epcdone);

input reset, epcclk;
output epcbitout, epcdone;

wire [111:0] epc;
assign epc = 112'h3000aabbccddeeff012345678910;

reg [6:0] bitoutcounter;
assign epcbitout = epc[bitoutcounter];
assign epcdone = (bitoutcounter == 0);
reg    initialized;

always @ (posedge epcclk or posedge reset) begin
  if (reset) begin
    bitoutcounter <= 0;
    initialized   <= 0;
  end else if (!initialized) begin
    bitoutcounter <= 111;
    initialized <= 1;
  end else if (!epcdone) begin
    bitoutcounter <= bitoutcounter - 7'd1;
  end else begin
  end
end

endmodule