data/full_repos/permissive/160911965/top_module.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160911965/top_module.v:59: Operator CASE expects 8 bits on the Case expression, but Case expression\'s VARREF \'char_count\' generates 3 bits.\n                                                                    : ... In instance top_module\n        case (char_count)\n        ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/160911965/top_module.v:96: Cannot find file containing module: \'uart\'\n    uart UART(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/160911965,data/full_repos/permissive/160911965/uart\n             data/full_repos/permissive/160911965,data/full_repos/permissive/160911965/uart.v\n             data/full_repos/permissive/160911965,data/full_repos/permissive/160911965/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module top_module(
    input clk,
    input nrst,
    output tx,
    input rx,
    output reg [3:0] led
    );
    

       reg transmit_signal = 0;
       wire recieved_signal;
       wire is_receiving;
       wire is_transmitting;
       

       reg[7:0] tx_data=0;
       wire[7:0] rx_data;
     


       reg [2:0] char_count =0;
       reg cena =0;
          
     always @(posedge clk)begin
        if (!nrst)
           char_count <= 0;
        else begin 
            if (transmit_signal_reg)
            char_count <= char_count + 1;
        end
     end
         

          
      reg[7:0] data =0;
      always @(posedge clk)begin
        case (char_count)
          8'd0: data <= "H";
          8'd1: data <= "e";
          8'd2: data <= "l";
          8'd3: data <= "l";
          8'd4: data <= "o";
          8'd5: data <= "!";
          8'd6: data <= ".";
          8'd7: data <= ".";
          default: data <= ".";
        endcase
      end
      
      reg transmit_signal_reg = 0;

    always@(posedge clk) begin
        if(!nrst) begin
            tx_data <= 0;

        end
        else begin
            tx_data <=  data;
            transmit_signal <= 1'b1;
            if(is_transmitting) begin
                 transmit_signal <= 1'b0;
                 transmit_signal_reg <= transmit_signal;
                 led <= ~led;
            end
        end
    end
    




       

    uart UART(
        .clk(clk),
        .rst(~nrst),
        .rx(rx),
        .tx(tx),
        .transmit(transmit_signal),
        .tx_byte(tx_data),
        .received(recieved_signal),
        .rx_byte(rx_data),
        .is_receiving(is_receiving),
        .is_transmitting(is_transmitting),
        .recv_error()
        );
endmodule
module top_module(
    input clk,
    input nrst,
    output tx,
    input rx,
    output reg [3:0] led
    );

    

       reg transmit_signal = 0;
       wire recieved_signal;
       wire is_receiving;
       wire is_transmitting;
       

       reg[7:0] tx_data=0;
       wire[7:0] rx_data;
     


       reg [2:0] char_count =0;
       reg cena =0;
          
     always @(posedge clk)begin
        if (!nrst)
           char_count <= 0;
        else begin 
            if (transmit_signal_reg)
            char_count <= char_count + 1;
        end
     end
         

          
      reg[7:0] data =0;
      always @(posedge clk)begin
        case (char_count)
          8'd0: data <= "H";
          8'd1: data <= "e";
          8'd2: data <= "l";
          8'd3: data <= "l";
          8'd4: data <= "o";
          8'd5: data <= "!";
          8'd6: data <= ".";
          8'd7: data <= ".";
          default: data <= ".";
        endcase
      end
      
      reg transmit_signal_reg = 0;

    always@(posedge clk) begin
        if(!nrst) begin
            tx_data <= 0;

        end
        else begin
            tx_data <=  data;
            transmit_signal <= 1'b1;
            if(is_transmitting) begin
                 transmit_signal <= 1'b0;
                 transmit_signal_reg <= transmit_signal;
                 led <= ~led;
            end
        end
    end
    




       

    uart UART(
        .clk(clk),
        .rst(~nrst),
        .rx(rx),
        .tx(tx),
        .transmit(transmit_signal),
        .tx_byte(tx_data),
        .received(recieved_signal),
        .rx_byte(rx_data),
        .is_receiving(is_receiving),
        .is_transmitting(is_transmitting),
        .recv_error()
        );
endmodule