data/full_repos/permissive/203650831/hd44780_nybsen_tb.v
 line:120: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_nybsen_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = (clk === 1\'b0);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/203650831/hd44780_nybsen_tb.v:49: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("hd44780_nybsen_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_nybsen_tb.v:50: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, hd44780_nybsen_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_nybsen_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #90 nybbin = 4\'b1011;            \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_nybsen_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #10 ststrobe = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_nybsen_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #10 ststrobe = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_nybsen_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #700 nybbin = 4\'b0100;            \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_nybsen_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #10 ststrobe = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_nybsen_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #500 ststrobe = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_nybsen_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #2500 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hd44780_nybsen_tb;











    reg clk = 1;


    always #5 clk = (clk === 1'b0);


    wire wb_reset;
    wire wb_clk;
    hd44780_syscon syscon(
        .i_clk(clk),
        .RST_O(wb_reset),
        .CLK_O(wb_clk)
        );



    initial begin
        $dumpfile("hd44780_nybsen_tb.vcd");
        $dumpvars(0, hd44780_nybsen_tb);
    end
















    reg ststrobe = 0;
    wire busy;
    reg rs_reg = 0;
    reg [3:0] nybbin = 4'b0000;


    wire pin_busy;
    wire [3:0] pins_data;
    wire pin_rs;
    wire pin_e;

    hd44780_nybble_sender nybsen(
        .RST_I(wb_reset),
        .CLK_I(wb_clk),
        .STB_I(ststrobe),
        .i_rs(rs_reg),
        .i_nybble(nybbin),
        .o_busy(pin_busy),
        .o_lcd_data(pins_data),
        .o_rs(pin_rs),
        .o_e(pin_e)
    );

    initial begin



        #90 nybbin = 4'b1011;
        rs_reg = 1;
        #10 ststrobe = 1;
        #10 ststrobe = 0;



        /

endmodule
module hd44780_nybsen_tb;












    reg clk = 1;


    always #5 clk = (clk === 1'b0);


    wire wb_reset;
    wire wb_clk;
    hd44780_syscon syscon(
        .i_clk(clk),
        .RST_O(wb_reset),
        .CLK_O(wb_clk)
        );



    initial begin
        $dumpfile("hd44780_nybsen_tb.vcd");
        $dumpvars(0, hd44780_nybsen_tb);
    end
















    reg ststrobe = 0;
    wire busy;
    reg rs_reg = 0;
    reg [3:0] nybbin = 4'b0000;


    wire pin_busy;
    wire [3:0] pins_data;
    wire pin_rs;
    wire pin_e;

    hd44780_nybble_sender nybsen(
        .RST_I(wb_reset),
        .CLK_I(wb_clk),
        .STB_I(ststrobe),
        .i_rs(rs_reg),
        .i_nybble(nybbin),
        .o_busy(pin_busy),
        .o_lcd_data(pins_data),
        .o_rs(pin_rs),
        .o_e(pin_e)
    );

    initial begin



        #90 nybbin = 4'b1011;
        rs_reg = 1;
        #10 ststrobe = 1;
        #10 ststrobe = 0;



        /

endmodule