data/full_repos/permissive/18770871/addPC.v
None: at end of input
data/verilator_xmls/a251e291-871c-473e-91a4-8c24bf5d00ab.xml
module addPC(in, out, stall);
    input[15:0] in;
    input stall;
    output[15:0] out;
    
    assign out = (stall!==1'b1)? in + 16'b0000000000000001 : in;
    
endmodule
module addPC(in, out, stall);

    input[15:0] in;
    input stall;
    output[15:0] out;
    
    assign out = (stall!==1'b1)? in + 16'b0000000000000001 : in;
    
endmodule