data/full_repos/permissive/175197601/hdl/jtpopeye_timing.v
'utf-8' codec can't decode byte 0x8c in position 2560: invalid start byte
1: b'%Warning-WIDTH: data/full_repos/permissive/175197601/hdl/jtpopeye_timing.v:63: Operator XOR expects 5 bits on the RHS, but RHS\'s VARREF \'RV\' generates 1 bits.\n                                                                             : ... In instance jtpopeye_timing\n    H[7:3] = Hcnt[7:3] ^ RV;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/175197601/hdl/jtpopeye_timing.v:98: Operator XOR expects 8 bits on the RHS, but RHS\'s VARREF \'RV\' generates 1 bits.\n                                                                             : ... In instance jtpopeye_timing\n            if( !HB ) V[7:0] <= Vcnt[8:1] ^ RV; \n                                          ^\n%Error: data/full_repos/permissive/175197601/hdl/jtpopeye_timing.v:169: Cannot find file containing module: \'jtframe_prom\'\njtframe_prom #(.aw(8),.dw(4),.simfile("../../rom/tpp2-v.7j")) u_prom_7j(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175197601/hdl,data/full_repos/permissive/175197601/jtframe_prom\n             data/full_repos/permissive/175197601/hdl,data/full_repos/permissive/175197601/jtframe_prom.v\n             data/full_repos/permissive/175197601/hdl,data/full_repos/permissive/175197601/jtframe_prom.sv\n             jtframe_prom\n             jtframe_prom.v\n             jtframe_prom.sv\n             obj_dir/jtframe_prom\n             obj_dir/jtframe_prom.v\n             obj_dir/jtframe_prom.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module jtpopeye_timing(
    input               clk,
    input               pxl2_cen,
    input               pxl_cen,

    input               RV_n,

    output  reg [7:0]   V = 8'd0,
    output  reg [7:0]   H,
    output  reg         H2O,

    output reg          HB = 1'b0,
    output              HBD_n,
    output reg          pre_HBDn = 1'b1,
    output reg          VB,
    output reg          INITEO = 1'b0,
    output reg          SY_n,

    output reg          HS,
    output reg          VS,

    input   [7:0]       prog_addr,
    input               prom_7j_we,
    input   [3:0]       prom_din
);


wire RV = ~RV_n;
wire [3:0] prom_data;

reg [7:0] Hcnt = 8'd0;
reg [9:0] Vcnt = 10'd0;

`ifdef SIMULATION
initial begin
    Vcnt = 'd0;
    VB   = 'd0;
end
`endif

always @(*) begin
    H[2:0] = Hcnt[2:0];
    H[7:3] = Hcnt[7:3] ^ RV;
    H2O    = Hcnt[2] ^ RV;
end

reg preEO = 1'b0;
reg VBl   = 1'b0;


















always @(posedge clk )
    if(pxl_cen) begin
        if( Hcnt!= 8'hFF)
            Hcnt <= Hcnt+8'h1;
        else begin
            HB <= ~HB;
            Hcnt <= HB ? 8'h0 : 8'hc0;




            if( !HB ) V[7:0] <= Vcnt[8:1] ^ RV; 
        end
    end


always @(posedge clk) begin
        VBl <= VB;
        if( VB && !VBl ) begin
            preEO    <= ~HB;
        end
        INITEO  <= ~(preEO ^ RV);
    end




reg HB3 = 1'b0;

assign HBD_n = ~( HB3 & HB );

always @(posedge clk) if(pxl_cen) begin
    if( Hcnt[2:0]==3'b111 ) HB3 <= HB;
    if( Hcnt[2:0]==3'b110 ) pre_HBDn <= ~HB;
end


wire Vup = prom_data[1];
reg  Vupl;
wire Vup_edge = Vup && !Vupl;

always @(posedge clk ) begin
    Vupl <= Vup;
    if( Vup_edge ) begin
        Vcnt[0]   <= ~Vcnt[9] & ~Vcnt[0];
        Vcnt[8:1] <= Vcnt[9] ? 8'd0 : Vcnt[8:1] + {7'd0,Vcnt[0]};
        Vcnt[9]   <= &Vcnt[8:0];
        if( &Vcnt[4:0] ) VB <= &Vcnt[8:6];
    end
end


reg pre_SY_n;
reg VB_sampled;

always @(*) begin : csync
    reg nand_7b_6, nand_5b_11, nand_7b_8, nand_5b_8;
    nand_7b_6  = ~( ~Vcnt[3] & Vcnt[4] & Vcnt[5] & VB );
    nand_5b_11 = ~( ~nand_7b_6 & prom_data[0] );
    nand_7b_8  = ~( nand_7b_6 & VB_sampled & prom_data[1] );
    nand_5b_8  = ~( ~VB_sampled & prom_data[2] );
    pre_SY_n = ~(~nand_5b_11 | ~nand_7b_8 | ~nand_5b_8);
end

always @(posedge clk) begin : latching
    reg last_vcnt3;
    SY_n <= pre_SY_n;
    last_vcnt3 <= Vcnt[3];
    if ( Vcnt[3] && ! last_vcnt3 ) VB_sampled <= VB & (&Vcnt[8:6]);
    if( VB ) begin
        if( Vcnt[5:4]==2'b11 ) VS <= ~Vcnt[3];
    end else VS <= 1'b0;
    if( HB ) begin
        if( Hcnt[5:0]==6'b010_110 ) HS <= 1'b1;
        if( Hcnt[5:0]==6'b100_110 ) HS <= 1'b0;
    end else HS <= 1'b0;
end



wire [7:0] prom_addr = { HB, Hcnt[7:1] };

jtframe_prom #(.aw(8),.dw(4),.simfile("../../rom/tpp2-v.7j")) u_prom_7j(
    .clk    ( clk               ),
    .cen    ( 1'b1              ),
    .data   ( prom_din          ),
    .rd_addr( prom_addr         ),
    .wr_addr( prog_addr         ),
    .we     ( prom_7j_we        ),
    .q      ( prom_data         )
);

endmodule
module jtpopeye_timing(
    input               clk,
    input               pxl2_cen,
    input               pxl_cen,

    input               RV_n,

    output  reg [7:0]   V = 8'd0,
    output  reg [7:0]   H,
    output  reg         H2O,

    output reg          HB = 1'b0,
    output              HBD_n,
    output reg          pre_HBDn = 1'b1,
    output reg          VB,
    output reg          INITEO = 1'b0,
    output reg          SY_n,

    output reg          HS,
    output reg          VS,

    input   [7:0]       prog_addr,
    input               prom_7j_we,
    input   [3:0]       prom_din
);



wire RV = ~RV_n;
wire [3:0] prom_data;

reg [7:0] Hcnt = 8'd0;
reg [9:0] Vcnt = 10'd0;

`ifdef SIMULATION
initial begin
    Vcnt = 'd0;
    VB   = 'd0;
end
`endif

always @(*) begin
    H[2:0] = Hcnt[2:0];
    H[7:3] = Hcnt[7:3] ^ RV;
    H2O    = Hcnt[2] ^ RV;
end

reg preEO = 1'b0;
reg VBl   = 1'b0;


















always @(posedge clk )
    if(pxl_cen) begin
        if( Hcnt!= 8'hFF)
            Hcnt <= Hcnt+8'h1;
        else begin
            HB <= ~HB;
            Hcnt <= HB ? 8'h0 : 8'hc0;




            if( !HB ) V[7:0] <= Vcnt[8:1] ^ RV; 
        end
    end


always @(posedge clk) begin
        VBl <= VB;
        if( VB && !VBl ) begin
            preEO    <= ~HB;
        end
        INITEO  <= ~(preEO ^ RV);
    end




reg HB3 = 1'b0;

assign HBD_n = ~( HB3 & HB );

always @(posedge clk) if(pxl_cen) begin
    if( Hcnt[2:0]==3'b111 ) HB3 <= HB;
    if( Hcnt[2:0]==3'b110 ) pre_HBDn <= ~HB;
end


wire Vup = prom_data[1];
reg  Vupl;
wire Vup_edge = Vup && !Vupl;

always @(posedge clk ) begin
    Vupl <= Vup;
    if( Vup_edge ) begin
        Vcnt[0]   <= ~Vcnt[9] & ~Vcnt[0];
        Vcnt[8:1] <= Vcnt[9] ? 8'd0 : Vcnt[8:1] + {7'd0,Vcnt[0]};
        Vcnt[9]   <= &Vcnt[8:0];
        if( &Vcnt[4:0] ) VB <= &Vcnt[8:6];
    end
end


reg pre_SY_n;
reg VB_sampled;

always @(*) begin : csync
    reg nand_7b_6, nand_5b_11, nand_7b_8, nand_5b_8;
    nand_7b_6  = ~( ~Vcnt[3] & Vcnt[4] & Vcnt[5] & VB );
    nand_5b_11 = ~( ~nand_7b_6 & prom_data[0] );
    nand_7b_8  = ~( nand_7b_6 & VB_sampled & prom_data[1] );
    nand_5b_8  = ~( ~VB_sampled & prom_data[2] );
    pre_SY_n = ~(~nand_5b_11 | ~nand_7b_8 | ~nand_5b_8);
end

always @(posedge clk) begin : latching
    reg last_vcnt3;
    SY_n <= pre_SY_n;
    last_vcnt3 <= Vcnt[3];
    if ( Vcnt[3] && ! last_vcnt3 ) VB_sampled <= VB & (&Vcnt[8:6]);
    if( VB ) begin
        if( Vcnt[5:4]==2'b11 ) VS <= ~Vcnt[3];
    end else VS <= 1'b0;
    if( HB ) begin
        if( Hcnt[5:0]==6'b010_110 ) HS <= 1'b1;
        if( Hcnt[5:0]==6'b100_110 ) HS <= 1'b0;
    end else HS <= 1'b0;
end



wire [7:0] prom_addr = { HB, Hcnt[7:1] };

jtframe_prom #(.aw(8),.dw(4),.simfile("../../rom/tpp2-v.7j")) u_prom_7j(
    .clk    ( clk               ),
    .cen    ( 1'b1              ),
    .data   ( prom_din          ),
    .rd_addr( prom_addr         ),
    .wr_addr( prog_addr         ),
    .we     ( prom_7j_we        ),
    .q      ( prom_data         )
);

endmodule