data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_terminator.v
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_terminator.v:29: Cannot find include file: ../core/ctrlport.vh\n`include "../core/ctrlport.vh" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/../core/ctrlport.vh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/../core/ctrlport.vh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/../core/ctrlport.vh.sv\n             ../core/ctrlport.vh\n             ../core/ctrlport.vh.v\n             ../core/ctrlport.vh.sv\n             obj_dir/../core/ctrlport.vh\n             obj_dir/../core/ctrlport.vh.v\n             obj_dir/../core/ctrlport.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module ctrlport_terminator #(
  parameter START_ADDRESS = 0,
  parameter LAST_ADDRESS = 32
)(



  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,
  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output  reg        s_ctrlport_resp_ack,
  output wire [ 1:0] s_ctrlport_resp_status,
  output wire [31:0] s_ctrlport_resp_data
);

`include "../core/ctrlport.vh"




always @(posedge ctrlport_clk) begin
  if (ctrlport_clk) begin
    if (ctrlport_rst) begin
      s_ctrlport_resp_ack <= 1'b0;
    end else if ((s_ctrlport_req_addr >= START_ADDRESS) && (s_ctrlport_req_addr <= LAST_ADDRESS)) begin
      s_ctrlport_resp_ack <= s_ctrlport_req_wr | s_ctrlport_req_rd;
    end else begin
      s_ctrlport_resp_ack <= 1'b0;
    end
  end
end


assign s_ctrlport_resp_status = CTRL_STS_CMDERR;
assign s_ctrlport_resp_data = { CTRLPORT_DATA_W {1'b0}};

endmodule
module ctrlport_terminator #(
  parameter START_ADDRESS = 0,
  parameter LAST_ADDRESS = 32
)(



  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,
  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output  reg        s_ctrlport_resp_ack,
  output wire [ 1:0] s_ctrlport_resp_status,
  output wire [31:0] s_ctrlport_resp_data
);


`include "../core/ctrlport.vh"




always @(posedge ctrlport_clk) begin
  if (ctrlport_clk) begin
    if (ctrlport_rst) begin
      s_ctrlport_resp_ack <= 1'b0;
    end else if ((s_ctrlport_req_addr >= START_ADDRESS) && (s_ctrlport_req_addr <= LAST_ADDRESS)) begin
      s_ctrlport_resp_ack <= s_ctrlport_req_wr | s_ctrlport_req_rd;
    end else begin
      s_ctrlport_resp_ack <= 1'b0;
    end
  end
end


assign s_ctrlport_resp_status = CTRL_STS_CMDERR;
assign s_ctrlport_resp_data = { CTRLPORT_DATA_W {1'b0}};

endmodule