data/full_repos/permissive/201196900/Tutorial/02_andgate.v
data/verilator_xmls/373ddcca-cf33-4dab-92b3-b7f38608c894.xml
module andgate(input a, input b, output q);

assign q=a & b;

endmodule
module andgate(input a, input b, output q);


assign q=a & b;

endmodule