data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/IMG_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/IMG_TB.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/IMG_TB.v:45: Unsupported: Ignoring delay on this delayed statement.\nalways #500 clk = ~clk;      \n       ^\n%Error: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/IMG_TB.v:31: Cannot find file containing module: \'DCT\'\n DCT uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/DCT\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/DCT.v\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/DCT.sv\n             DCT\n             DCT.v\n             DCT.sv\n             obj_dir/DCT\n             obj_dir/DCT.v\n             obj_dir/DCT.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module IMG_TB;


	reg clk;


	DCT uut (
		.clk(clk)
	);

	initial begin

		clk = 0;


		#100;
        


	end
always #500 clk = ~clk;      
endmodule
module IMG_TB;



	reg clk;


	DCT uut (
		.clk(clk)
	);

	initial begin

		clk = 0;


		#100;
        


	end
always #500 clk = ~clk;      
endmodule