data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:254: Unsupported: Ignoring delay on this delayed statement.\n        forever #50 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:45: Cannot find file containing module: \'instMemory\'\n    instMemory #(32, 4) myIMEM(.inst(instr32), .pcVal(PC16[3:0]), .sysCLK(mainCLOCK));    \n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191834901/VerilogHDL,data/full_repos/permissive/191834901/instMemory\n             data/full_repos/permissive/191834901/VerilogHDL,data/full_repos/permissive/191834901/instMemory.v\n             data/full_repos/permissive/191834901/VerilogHDL,data/full_repos/permissive/191834901/instMemory.sv\n             instMemory\n             instMemory.v\n             instMemory.sv\n             obj_dir/instMemory\n             obj_dir/instMemory.v\n             obj_dir/instMemory.sv\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:50: Cannot find file containing module: \'controlPathDriver\'\n    controlPathDriver #(16, 16) myCP(\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:72: Cannot find file containing module: \'registerFile\'\n    registerFile #(32, 5) riscRegisters(\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:86: Cannot find file containing module: \'mainALU\'\n    mainALU #(32) testALU(\n    ^~~~~~~\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:99: Cannot find file containing module: \'dataMemory\'\n    dataMemory #(32, 16) myDMEM(\n    ^~~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mainProcessor(
        output [31:0] instr32,
        output [31:0] PC32,
        output [31:0] immidiate32b,
        output [31:0] dataRS1, dataRS2, aluOut, ALUinA, ALUinB,
        output reg [31:0] writeBackData,
        output [4:0]  rs1addr, rs2addr, rdaddr,
        output PCSel,
        output [2:0] ImmSel,
        output BrUn, ASel, BSel,
        output [3:0] ALUSel,
        output MemRW, RegWEn,
        output [1:0] WBSel,
        input  [3:2]  KEY
);

        wire mainCLOCK;
        assign mainCLOCK = ~KEY[3];




    wire [15:0] PC16, PC16Next;
    assign PC32= {16'b0, PC16};










    wire BrLt, BrEq;





    programCounter #(16) myPC(
        .PC(PC16), .PCNext(PC16Next), .ALUout(aluOut), .PCSel(PCSel), .sysCLK(mainCLOCK), .pRST(~KEY[2])
    );

    instMemory #(32, 4) myIMEM(.inst(instr32), .pcVal(PC16[3:0]), .sysCLK(mainCLOCK));    




    controlPathDriver #(16, 16) myCP(
        PCSel, ImmSel, BrUn, ASel, BSel, ALUSel, MemRW, RegWEn, WBSel, instr32, BrEq, BrLt, mainCLOCK
    );





    wire [6:0] instOPCODE;

    wire [2:0] funct3;
    wire [6:0] funct7;
    splitInstruction getCodes(instOPCODE, rdaddr, rs1addr, rs2addr, funct3, funct7, instr32);



    immideateGen #(32) immInst(.imm32(immidiate32b), .instr(instr32), .immSelect(ImmSel));





    registerFile #(32, 5) riscRegisters(
        .regDataA(dataRS1), .regDataB(dataRS2), .regDataD(writeBackData), .addrA(rs1addr),
        .addrB(rs2addr), .addrD(rdaddr), .regWEn(RegWEn), .sysCLK(mainCLOCK)
    );





    mux2x1 #(32) aluinputMUX1(.M(ALUinA), .X(dataRS1), .Y(PC32), .Sel(ASel));
    mux2x1 #(32) aluinputMUX2(.M(ALUinB), .X(dataRS2), .Y(immidiate32b), .Sel(BSel));



    mainALU #(32) testALU(
        .outALU(aluOut), .inALUa(ALUinA), .inALUb(ALUinB), .ALUSel(ALUSel)
    );


    comparatorNx #(32) compAB(
        .BrLt(BrLt), .BrEq(BrEq), .A(dataRS1), .B(dataRS2)
    );




    wire [31:0] dataRead;
    dataMemory #(32, 16) myDMEM(
        .memDataR(dataRead), .memDataW(dataRS2), .addrD(aluOut[15:0]), .memRW(MemRW), .sysCLK(mainCLOCK)
    );




    always@(*) begin
        case(WBSel)
            2'b00: writeBackData = aluOut;
            2'b01: writeBackData = dataRead;
            2'b10: writeBackData = {16'b0, PC16Next};
            default: writeBackData = 32'h0;
        endcase
    end


endmodule
module mainProcessor(
        output [31:0] instr32,
        output [31:0] PC32,
        output [31:0] immidiate32b,
        output [31:0] dataRS1, dataRS2, aluOut, ALUinA, ALUinB,
        output reg [31:0] writeBackData,
        output [4:0]  rs1addr, rs2addr, rdaddr,
        output PCSel,
        output [2:0] ImmSel,
        output BrUn, ASel, BSel,
        output [3:0] ALUSel,
        output MemRW, RegWEn,
        output [1:0] WBSel,
        input  [3:2]  KEY
);


        wire mainCLOCK;
        assign mainCLOCK = ~KEY[3];




    wire [15:0] PC16, PC16Next;
    assign PC32= {16'b0, PC16};










    wire BrLt, BrEq;





    programCounter #(16) myPC(
        .PC(PC16), .PCNext(PC16Next), .ALUout(aluOut), .PCSel(PCSel), .sysCLK(mainCLOCK), .pRST(~KEY[2])
    );

    instMemory #(32, 4) myIMEM(.inst(instr32), .pcVal(PC16[3:0]), .sysCLK(mainCLOCK));    




    controlPathDriver #(16, 16) myCP(
        PCSel, ImmSel, BrUn, ASel, BSel, ALUSel, MemRW, RegWEn, WBSel, instr32, BrEq, BrLt, mainCLOCK
    );





    wire [6:0] instOPCODE;

    wire [2:0] funct3;
    wire [6:0] funct7;
    splitInstruction getCodes(instOPCODE, rdaddr, rs1addr, rs2addr, funct3, funct7, instr32);



    immideateGen #(32) immInst(.imm32(immidiate32b), .instr(instr32), .immSelect(ImmSel));





    registerFile #(32, 5) riscRegisters(
        .regDataA(dataRS1), .regDataB(dataRS2), .regDataD(writeBackData), .addrA(rs1addr),
        .addrB(rs2addr), .addrD(rdaddr), .regWEn(RegWEn), .sysCLK(mainCLOCK)
    );





    mux2x1 #(32) aluinputMUX1(.M(ALUinA), .X(dataRS1), .Y(PC32), .Sel(ASel));
    mux2x1 #(32) aluinputMUX2(.M(ALUinB), .X(dataRS2), .Y(immidiate32b), .Sel(BSel));



    mainALU #(32) testALU(
        .outALU(aluOut), .inALUa(ALUinA), .inALUb(ALUinB), .ALUSel(ALUSel)
    );


    comparatorNx #(32) compAB(
        .BrLt(BrLt), .BrEq(BrEq), .A(dataRS1), .B(dataRS2)
    );




    wire [31:0] dataRead;
    dataMemory #(32, 16) myDMEM(
        .memDataR(dataRead), .memDataW(dataRS2), .addrD(aluOut[15:0]), .memRW(MemRW), .sysCLK(mainCLOCK)
    );




    always@(*) begin
        case(WBSel)
            2'b00: writeBackData = aluOut;
            2'b01: writeBackData = dataRead;
            2'b10: writeBackData = {16'b0, PC16Next};
            default: writeBackData = 32'h0;
        endcase
    end


endmodule