data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/mem/ddr3_parameters.vh
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/1a968e26-cf8d-4e89-93ef-8047b9533cb1.xml
function [3:0] min_cwl;
    input period;
    real period;
    min_cwl = (period >= 2500.0) ? 5:
              (period >= 1875.0) ? 6:
              (period >= 1500.0) ? 7:
              (period >= 1250.0) ? 8:
              (period >= 1070.0) ? 9:
              10;
endfunction
function [3:0] min_cwl;

    input period;
    real period;
    min_cwl = (period >= 2500.0) ? 5:
              (period >= 1875.0) ? 6:
              (period >= 1500.0) ? 7:
              (period >= 1250.0) ? 8:
              (period >= 1070.0) ? 9:
              10;
endfunction