data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v
 line:20: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:12: Unsupported: Ignoring delay on this delayed statement.\n#00  op=3\'d0; a=4\'d7; b=4\'d3;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:13: Unsupported: Ignoring delay on this delayed statement.\n#20  op=3\'d1; a=4\'d7; b=4\'d3;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:14: Unsupported: Ignoring delay on this delayed statement.\n#20  op=3\'d2; a=4\'d7; b=4\'d3;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:15: Unsupported: Ignoring delay on this delayed statement.\n#20  op=3\'d3; a=4\'d7; b=4\'d3;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20  op=3\'d4; a=4\'d7; b=4\'d3;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:17: Unsupported: Ignoring delay on this delayed statement.\n#20  op=3\'d5; a=4\'d7; b=4\'d3;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:18: Unsupported: Ignoring delay on this delayed statement.\n#20  op=3\'d6; a=4\'d7; b=4\'d3;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:19: Unsupported: Ignoring delay on this delayed statement.\n#20  op=3\'d7; a=4\'d7; b=4\'d3;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:20: Unsupported: Ignoring delay on this delayed statement.\n#20  $stop;\n^\n%Error: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:25: Unsupported or unknown PLI call: $monitor\n$monitor("time=%3d, a=%4d, b=%4d, op=%3d, out=%7d",$time,a,b,op,out);\n^~~~~~~~\n%Error: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:30: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("alu_4bit.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/123339956/Lab2_Behavorial_Modelling/alu_4bit.v:31: Unsupported or unknown PLI call: $dumpvars\n$dumpvars;\n^~~~~~~~~\n%Error: Exiting due to 3 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_4bit(out,a,b,op);
	
output reg [3:0] out;
input [3:0] a,b;
input [2:0] op;

parameter sub 	= 3'b000 ;
parameter add 	= 3'b001 ;
parameter exor 	= 3'b010 ;
parameter andab = 3'b011 ;
parameter orab 	= 3'b100 ;
parameter shr 	= 3'b101 ;
parameter shl 	= 3'b110 ;
parameter sar 	= 3'b111 ;

always @(*)
begin 
case(op)
sub		: out <= a-b ; 
add 	: out <= a+b ; 
exor	: out <= a^b ; 
andab 	: out <= a&b ;
orab	: out <= a|b ; 
shr		: out <= a >> 1'b1 ;
shl		: out <= a << 1'b1 ; 
sar		: out <= {a[3],a[3:1]} ; 
default: out <= 4'bzzzz ; 
endcase
end

endmodule
module alu_4bit(out,a,b,op);

	
output reg [3:0] out;
input [3:0] a,b;
input [2:0] op;

parameter sub 	= 3'b000 ;
parameter add 	= 3'b001 ;
parameter exor 	= 3'b010 ;
parameter andab = 3'b011 ;
parameter orab 	= 3'b100 ;
parameter shr 	= 3'b101 ;
parameter shl 	= 3'b110 ;
parameter sar 	= 3'b111 ;

always @(*)
begin 
case(op)
sub		: out <= a-b ; 
add 	: out <= a+b ; 
exor	: out <= a^b ; 
andab 	: out <= a&b ;
orab	: out <= a|b ; 
shr		: out <= a >> 1'b1 ;
shl		: out <= a << 1'b1 ; 
sar		: out <= {a[3],a[3:1]} ; 
default: out <= 4'bzzzz ; 
endcase
end

endmodule