data/full_repos/permissive/174369527/verilator_test/01-Wire/thruwire.v
None: at end of input
data/verilator_xmls/d10737fb-79f2-4489-b8f6-7cf8df1b02f0.xml
module thruwire(i_sw, o_led);
	input wire i_sw;
	output wire o_led;
	assign o_led = i_sw;
endmodule
module thruwire(i_sw, o_led);

	input wire i_sw;
	output wire o_led;
	assign o_led = i_sw;
endmodule