data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:28: Define or directive not defined: \'`WORD_W\'\n  localparam integer ADDR_COUNT = WORD_COUNT * `WORD_W / 8;\n                                               ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:28: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n  localparam integer ADDR_COUNT = WORD_COUNT * `WORD_W / 8;\n                                                       ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:31: Define or directive not defined: \'`ADDR_W\'\n  localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:31: Define or directive not defined: \'`ADDR_W\'\n  localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];\n                                                         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:32: Define or directive not defined: \'`ADDR_W\'\n  localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:32: Define or directive not defined: \'`ADDR_W\'\n  localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];\n                                                     ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:41: Define or directive not defined: \'`WORD_W\'\n  input [WORD_COUNT * `WORD_W - 1:0] i_registers;\n                      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:43: Define or directive not defined: \'`ADDR_W\'\n  input [`ADDR_W - 1:0] i_req_addr;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:44: Define or directive not defined: \'`MEM_COUNT_W\'\n  input [`MEM_COUNT_W - 1:0] i_req_count;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:50: Define or directive not defined: \'`WORD_W\'\n  output reg [`WORD_W - 1:0] o_res_rd_data;\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:51: Define or directive not defined: \'`MEM_CODE_W\'\n  output reg [`MEM_CODE_W - 1:0] o_res_code;\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:57: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] mem [ADDR_START:ADDR_END];\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:59: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 2 - 1:0] s_addr_aligned;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:60: Define or directive not defined: \'`ADDR_W\'\n  assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:68: Define or directive not defined: \'`WORD_W\'\n      assign mem[i + ADDR_START] = i_registers[(i + 1) * `WORD_W - 1:i * `WORD_W];\n                                                         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:68: Define or directive not defined: \'`WORD_W\'\n      assign mem[i + ADDR_START] = i_registers[(i + 1) * `WORD_W - 1:i * `WORD_W];\n                                                                         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:68: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      assign mem[i + ADDR_START] = i_registers[(i + 1) * `WORD_W - 1:i * `WORD_W];\n                                                                                ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:75: Define or directive not defined: \'`MEM_CODE_INVALID\'\n      o_res_code <= `MEM_CODE_INVALID;\n                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      o_res_code <= `MEM_CODE_INVALID;\n                                     ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:77: Define or directive not defined: \'`MEM_COUNT_NONE\'\n      if(i_req_count != `MEM_COUNT_NONE) begin\n                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if(i_req_count != `MEM_COUNT_NONE) begin\n                                       ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:79: Define or directive not defined: \'`MEM_COUNT_HALF\'\n        if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||\n                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:80: Define or directive not defined: \'`MEM_COUNT_WORD\'\n          (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:83: Define or directive not defined: \'`MEM_CODE_MISALIGNED\'\n          o_res_code <= `MEM_CODE_MISALIGNED;\n                        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n          o_res_code <= `MEM_CODE_MISALIGNED;\n                                            ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:88: Define or directive not defined: \'`MEM_CODE_MISALIGNED\'\n          o_res_code <= `MEM_CODE_MISALIGNED;\n                        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n          o_res_code <= `MEM_CODE_MISALIGNED;\n                                            ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:93: Define or directive not defined: \'`MEM_CODE_READ\'\n          o_res_code <= `MEM_CODE_READ;\n                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:96: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n            `MEM_COUNT_BYTE: begin\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:96: syntax error, unexpected \':\', expecting endcase\n            `MEM_COUNT_BYTE: begin\n                           ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:99: syntax error, unexpected \'[\', expecting IDENTIFIER\n                0: o_res_rd_data[7:0] <= mem[s_addr_aligned][7:0];\n                                ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:100: syntax error, unexpected \'[\', expecting IDENTIFIER\n                1: o_res_rd_data[7:0] <= mem[s_addr_aligned][15:8];\n                                ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:101: syntax error, unexpected \'[\', expecting IDENTIFIER\n                2: o_res_rd_data[7:0] <= mem[s_addr_aligned][23:16];\n                                ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:102: syntax error, unexpected \'[\', expecting IDENTIFIER\n                3: o_res_rd_data[7:0] <= mem[s_addr_aligned][31:24];\n                                ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n                default: o_res_rd_data[7:0] <= 0;\n                                      ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:107: Define or directive not defined: \'`MEM_COUNT_HALF\'\n            `MEM_COUNT_HALF: begin\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:110: syntax error, unexpected \'[\', expecting IDENTIFIER\n                0: o_res_rd_data[15:0] <= mem[s_addr_aligned][15:0];\n                                ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:111: syntax error, unexpected \'[\', expecting IDENTIFIER\n                1: o_res_rd_data[15:0] <= mem[s_addr_aligned][31:16];\n                                ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:112: syntax error, unexpected \'[\', expecting IDENTIFIER\n                default: o_res_rd_data[15:0] <= 0;\n                                      ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:116: Define or directive not defined: \'`MEM_COUNT_WORD\'\n            `MEM_COUNT_WORD: o_res_rd_data <= mem[s_addr_aligned];\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readonly_registers.v:120: Define or directive not defined: \'`MEM_CODE_INVALID\'\n             o_res_code <= `MEM_CODE_INVALID;\n                           ^~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module readonly_registers(
  clk,
  aresetn,

  i_registers,

  i_req_addr,
  i_req_count,

  o_res_rd_data,
  o_res_code
);



  parameter WORD_COUNT = 1;
  parameter ADDR_START = 0;




  localparam integer ADDR_COUNT = WORD_COUNT * `WORD_W / 8;
  localparam ADDR_END = ADDR_COUNT + ADDR_START - 1;

  localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];
  localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];





  input clk;
  input aresetn;

  input [WORD_COUNT * `WORD_W - 1:0] i_registers;

  input [`ADDR_W - 1:0] i_req_addr;
  input [`MEM_COUNT_W - 1:0] i_req_count;





  output reg [`WORD_W - 1:0] o_res_rd_data;
  output reg [`MEM_CODE_W - 1:0] o_res_code;





  wire [`WORD_W - 1:0] mem [ADDR_START:ADDR_END];

  wire [`ADDR_W - 2 - 1:0] s_addr_aligned;
  assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];

  wire [1:0] s_offset;
  assign s_offset = i_req_addr[1:0];

  genvar i;
  generate
    for(i = 0; i < WORD_COUNT; i = i + 1) begin: memory_remap
      assign mem[i + ADDR_START] = i_registers[(i + 1) * `WORD_W - 1:i * `WORD_W];
    end
  endgenerate

  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin
      o_res_rd_data <= 0;
      o_res_code <= `MEM_CODE_INVALID;
    end else begin
      if(i_req_count != `MEM_COUNT_NONE) begin
        
        if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
          (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin

          o_res_rd_data <= 0;
          o_res_code <= `MEM_CODE_MISALIGNED;

        end else if(s_addr_aligned > ADDR_END) begin
          
          o_res_rd_data <= 0;
          o_res_code <= `MEM_CODE_MISALIGNED;

        end else begin
          
          o_res_rd_data <= 0;
          o_res_code <= `MEM_CODE_READ;

          case(i_req_count)
            `MEM_COUNT_BYTE: begin
              o_res_rd_data[31:8] <= 0;
              case(s_offset)
                0: o_res_rd_data[7:0] <= mem[s_addr_aligned][7:0];
                1: o_res_rd_data[7:0] <= mem[s_addr_aligned][15:8];
                2: o_res_rd_data[7:0] <= mem[s_addr_aligned][23:16];
                3: o_res_rd_data[7:0] <= mem[s_addr_aligned][31:24];
                default: o_res_rd_data[7:0] <= 0;
              endcase
            end
          
            `MEM_COUNT_HALF: begin
              o_res_rd_data[31:15] <= 0;
              case(s_offset[1])
                0: o_res_rd_data[15:0] <= mem[s_addr_aligned][15:0];
                1: o_res_rd_data[15:0] <= mem[s_addr_aligned][31:16];
                default: o_res_rd_data[15:0] <= 0;
              endcase
            end

            `MEM_COUNT_WORD: o_res_rd_data <= mem[s_addr_aligned];

            default: begin 
             o_res_rd_data <= 0;
             o_res_code <= `MEM_CODE_INVALID;
            end
          endcase
        end
      end
    end
  end
endmodule
module readonly_registers(
  clk,
  aresetn,

  i_registers,

  i_req_addr,
  i_req_count,

  o_res_rd_data,
  o_res_code
);




  parameter WORD_COUNT = 1;
  parameter ADDR_START = 0;




  localparam integer ADDR_COUNT = WORD_COUNT * `WORD_W / 8;
  localparam ADDR_END = ADDR_COUNT + ADDR_START - 1;

  localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];
  localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];





  input clk;
  input aresetn;

  input [WORD_COUNT * `WORD_W - 1:0] i_registers;

  input [`ADDR_W - 1:0] i_req_addr;
  input [`MEM_COUNT_W - 1:0] i_req_count;





  output reg [`WORD_W - 1:0] o_res_rd_data;
  output reg [`MEM_CODE_W - 1:0] o_res_code;





  wire [`WORD_W - 1:0] mem [ADDR_START:ADDR_END];

  wire [`ADDR_W - 2 - 1:0] s_addr_aligned;
  assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];

  wire [1:0] s_offset;
  assign s_offset = i_req_addr[1:0];

  genvar i;
  generate
    for(i = 0; i < WORD_COUNT; i = i + 1) begin: memory_remap
      assign mem[i + ADDR_START] = i_registers[(i + 1) * `WORD_W - 1:i * `WORD_W];
    end
  endgenerate

  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin
      o_res_rd_data <= 0;
      o_res_code <= `MEM_CODE_INVALID;
    end else begin
      if(i_req_count != `MEM_COUNT_NONE) begin
        
        if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
          (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin

          o_res_rd_data <= 0;
          o_res_code <= `MEM_CODE_MISALIGNED;

        end else if(s_addr_aligned > ADDR_END) begin
          
          o_res_rd_data <= 0;
          o_res_code <= `MEM_CODE_MISALIGNED;

        end else begin
          
          o_res_rd_data <= 0;
          o_res_code <= `MEM_CODE_READ;

          case(i_req_count)
            `MEM_COUNT_BYTE: begin
              o_res_rd_data[31:8] <= 0;
              case(s_offset)
                0: o_res_rd_data[7:0] <= mem[s_addr_aligned][7:0];
                1: o_res_rd_data[7:0] <= mem[s_addr_aligned][15:8];
                2: o_res_rd_data[7:0] <= mem[s_addr_aligned][23:16];
                3: o_res_rd_data[7:0] <= mem[s_addr_aligned][31:24];
                default: o_res_rd_data[7:0] <= 0;
              endcase
            end
          
            `MEM_COUNT_HALF: begin
              o_res_rd_data[31:15] <= 0;
              case(s_offset[1])
                0: o_res_rd_data[15:0] <= mem[s_addr_aligned][15:0];
                1: o_res_rd_data[15:0] <= mem[s_addr_aligned][31:16];
                default: o_res_rd_data[15:0] <= 0;
              endcase
            end

            `MEM_COUNT_WORD: o_res_rd_data <= mem[s_addr_aligned];

            default: begin 
             o_res_rd_data <= 0;
             o_res_code <= `MEM_CODE_INVALID;
            end
          endcase
        end
      end
    end
  end
endmodule