data/full_repos/permissive/203526788/iVerilog/Template/tb.v
 line:78: before: "$"
1: b'%Error: data/full_repos/permissive/203526788/iVerilog/Template/tb.v:22: Cannot find include file: top.v\n`include "top.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203526788/iVerilog/Template,data/full_repos/permissive/203526788/top.v\n             data/full_repos/permissive/203526788/iVerilog/Template,data/full_repos/permissive/203526788/top.v.v\n             data/full_repos/permissive/203526788/iVerilog/Template,data/full_repos/permissive/203526788/top.v.sv\n             top.v\n             top.v.v\n             top.v.sv\n             obj_dir/top.v\n             obj_dir/top.v.v\n             obj_dir/top.v.sv\n%Error: data/full_repos/permissive/203526788/iVerilog/Template/tb.v:34: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/203526788/iVerilog/Template/tb.v:35: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/203526788/iVerilog/Template/tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/203526788/iVerilog/Template/tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/203526788/iVerilog/Template/tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/203526788/iVerilog/Template/tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/203526788/iVerilog/Template/tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #20 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/203526788/iVerilog/Template/tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk= ~clk;\n           ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n'
module tb;
            
    reg a; 
    reg clk;
    wire b;
            
                    
    initial 
    begin
    
    $dumpfile("tb.vcd");
	$dumpvars(0, tb);

    clk = 0;
    #1
    a=0;
    #5
    a=1;
    #5
    a=0;
    #1
    a=1;
    
    #20 $finish;
    end
    
    always #1 clk= ~clk;

    top myInstance (a,clk,b);

endmodule
module tb;

            
    reg a; 
    reg clk;
    wire b;
            
                    
    initial 
    begin
    
    $dumpfile("tb.vcd");
	$dumpvars(0, tb);

    clk = 0;
    #1
    a=0;
    #5
    a=1;
    #5
    a=0;
    #1
    a=1;
    
    #20 $finish;
    end
    
    always #1 clk= ~clk;

    top myInstance (a,clk,b);

endmodule