data/full_repos/permissive/167518838/sources/MBIST_BRAM_TOP.v
1: b"%Error: data/full_repos/permissive/167518838/sources/MBIST_BRAM_TOP.v:68: Cannot find file containing module: 'MBIST_BRAM_SHELL'\n   MBIST_BRAM_SHELL #(\n   ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167518838/sources,data/full_repos/permissive/167518838/MBIST_BRAM_SHELL\n             data/full_repos/permissive/167518838/sources,data/full_repos/permissive/167518838/MBIST_BRAM_SHELL.v\n             data/full_repos/permissive/167518838/sources,data/full_repos/permissive/167518838/MBIST_BRAM_SHELL.sv\n             MBIST_BRAM_SHELL\n             MBIST_BRAM_SHELL.v\n             MBIST_BRAM_SHELL.sv\n             obj_dir/MBIST_BRAM_SHELL\n             obj_dir/MBIST_BRAM_SHELL.v\n             obj_dir/MBIST_BRAM_SHELL.sv\n%Error: Exiting due to 1 error(s)\n"
module MBIST_BRAM_TOP (RESET_L, TEST_H, TCLK, ALG_SEL, FAIL, DONE);

	parameter SHN = 4;
	parameter ASNET = 3;
	parameter UUTN = 10;
	parameter ADA = 8;
	parameter ADB = 8;
	parameter DAA = 35;
	parameter DAB = 35;
	
	input RESET_L;
	input TEST_H;
	input TCLK;
	input [ASNET:0] ALG_SEL;
	output FAIL;
	output DONE;

	wire [SHN:1] top_fail;
	wire [SHN:1] top_done;
	
	assign FAIL = |top_fail;
	assign DONE = &top_done;
	
	genvar k;
	generate
		
		for (k=1;k<=SHN;k=k+1) begin: SHELL
			MBIST_BRAM_SHELL #(
				.ASNET(ASNET),
				.UUTN(UUTN),
				.ADA(ADA),
				.ADB(ADB),
				.DAA(DAA),
				.DAB(DAB))
			MBLOCK (
				.RESET_L(RESET_L),
				.TEST_H(TEST_H),
				.TCLK(TCLK),
				.ALG_SEL(ALG_SEL),
				.FAIL(top_fail[k]),
				.DONE(top_done[k])
			);
		end	
		
	endgenerate	
	
endmodule
module MBIST_BRAM_TOP (RESET_L, TEST_H, TCLK, ALG_SEL, FAIL, DONE);


	parameter SHN = 4;
	parameter ASNET = 3;
	parameter UUTN = 10;
	parameter ADA = 8;
	parameter ADB = 8;
	parameter DAA = 35;
	parameter DAB = 35;
	
	input RESET_L;
	input TEST_H;
	input TCLK;
	input [ASNET:0] ALG_SEL;
	output FAIL;
	output DONE;

	wire [SHN:1] top_fail;
	wire [SHN:1] top_done;
	
	assign FAIL = |top_fail;
	assign DONE = &top_done;
	
	genvar k;
	generate
		
		for (k=1;k<=SHN;k=k+1) begin: SHELL
			MBIST_BRAM_SHELL #(
				.ASNET(ASNET),
				.UUTN(UUTN),
				.ADA(ADA),
				.ADB(ADB),
				.DAA(DAA),
				.DAB(DAB))
			MBLOCK (
				.RESET_L(RESET_L),
				.TEST_H(TEST_H),
				.TCLK(TCLK),
				.ALG_SEL(ALG_SEL),
				.FAIL(top_fail[k]),
				.DONE(top_done[k])
			);
		end	
		
	endgenerate	
	
endmodule