data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Arithmetic_Circuits/m2014_q4j.v
data/verilator_xmls/3edffbf7-217f-49cf-8e47-cac0914e841e.xml
module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);
    FourBitAdder ins(x,y,sum);
endmodule
module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);

    FourBitAdder ins(x,y,sum);
endmodule