data/full_repos/permissive/21702465/source/sirc_files/system.v
1: b"%Error: data/full_repos/permissive/21702465/source/sirc_files/system.v:92: Cannot find file containing module: 'IBUF'\n IBUF reset_ibuf (.I(RESET), .O(hard_reset_low));\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/21702465/source/sirc_files,data/full_repos/permissive/21702465/IBUF\n             data/full_repos/permissive/21702465/source/sirc_files,data/full_repos/permissive/21702465/IBUF.v\n             data/full_repos/permissive/21702465/source/sirc_files,data/full_repos/permissive/21702465/IBUF.sv\n             IBUF\n             IBUF.v\n             IBUF.sv\n             obj_dir/IBUF\n             obj_dir/IBUF.v\n             obj_dir/IBUF.sv\n%Error: data/full_repos/permissive/21702465/source/sirc_files/system.v:109: Cannot find file containing module: 'PLL_BASE'\n PLL_BASE #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/21702465/source/sirc_files/system.v:146: Cannot find file containing module: 'BUFG'\n BUFG bufCLK_200 (.O(clk_200), .I(clk_200_i));\n ^~~~\n%Error: data/full_repos/permissive/21702465/source/sirc_files/system.v:147: Cannot find file containing module: 'BUFG'\n BUFG bufCLK_125 (.O(clk_125_eth), .I(clk_125_eth_i));\n ^~~~\n%Error: data/full_repos/permissive/21702465/source/sirc_files/system.v:148: Cannot find file containing module: 'BUFG'\n BUFG bufCLK_user (.O(clk_user_interface), .I(clk_user_interface_i));\n ^~~~\n%Error: data/full_repos/permissive/21702465/source/sirc_files/system.v:184: Cannot find file containing module: 'ethernet2BlockMem'\n ethernet2BlockMem #(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/21702465/source/sirc_files/system.v:254: Cannot find file containing module: 'SircHandler'\n SircHandler #(\n ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module system #(







	parameter INMEM_USER_BYTE_WIDTH = 1,
	parameter OUTMEM_USER_BYTE_WIDTH = 1,




	parameter INMEM_USER_ADDRESS_WIDTH = 17,
	parameter OUTMEM_USER_ADDRESS_WIDTH = 13,





	parameter INMEM_USER_REGISTER = 1,


	parameter MAC_ADDRESS = 48'hAAAAAAAAAAAA
)(	
	input		wire 			CLK_100,
	input		wire 			RESET,






	output	wire [7:0]	GMII_TXD_0,
	output	wire 			GMII_TX_EN_0,
	output	wire 			GMII_TX_ER_0,
	output	wire 			GMII_GTX_CLK_0,
	input    wire [7:0]	GMII_RXD_0,
	input		wire 			GMII_RX_DV_0,
	input		wire 			GMII_RX_ER_0,
	input		wire 			GMII_RX_CLK_0,
	output	wire 			GMII_RESET_B,


	input		wire 			sysACE_CLK,
	output 	wire [6:0]	sysACE_MPADD,
	inout 	wire [15:0]	sysACE_MPDATA,
	output	wire 			sysACE_MPCE,
	output	wire 			sysACE_MPWE,
	output	wire 			sysACE_MPOE,



	output	wire [7:0]	LED,

	input wire RST,
	
	input wire start,
	input wire sw

);




	wire hard_reset_low;



	IBUF reset_ibuf (.I(RESET), .O(hard_reset_low));






	wire clk_200_i;
	wire clk_200;
	wire clk_125_eth_i;
	wire clk_125_eth;
	wire pllFB;
	wire pllLock;


	wire clk_user_interface_i;
	wire clk_user_interface;
	PLL_BASE #(
		.COMPENSATION("SYSTEM_SYNCHRONOUS"),
		.BANDWIDTH("OPTIMIZED"),

		.CLKFBOUT_MULT(10),
		.DIVCLK_DIVIDE(1),
		.CLKFBOUT_PHASE(0.0),
		.REF_JITTER(0.100),
		.CLKIN_PERIOD(10.0),

		.CLKOUT0_DIVIDE(5),
		.CLKOUT0_PHASE(0.0),
		.CLKOUT0_DUTY_CYCLE(0.5),
		.CLKOUT1_DIVIDE(8),
		.CLKOUT1_PHASE(0.0),
		.CLKOUT1_DUTY_CYCLE(0.5),




		.CLKOUT2_DIVIDE(6),
		.CLKOUT2_PHASE(0.0),
		.CLKOUT2_DUTY_CYCLE(0.5)
	) clkBPLL (
		.CLKOUT0(clk_200_i),
		.CLKOUT1(clk_125_eth_i),


		.CLKOUT2(clk_user_interface_i),
		.CLKFBOUT(pllFB),
		.CLKIN(CLK_100),
		.CLKFBIN(pllFB),
		.LOCKED(pllLock),
		.RST(~hard_reset_low)
	);


	BUFG bufCLK_200 (.O(clk_200), .I(clk_200_i));
	BUFG bufCLK_125 (.O(clk_125_eth), .I(clk_125_eth_i));
	BUFG bufCLK_user (.O(clk_user_interface), .I(clk_user_interface_i));
	





	wire userLogicReset;
	

	wire userRunValue;
	wire userRunClear;
	

	wire register32CmdReq;
	wire register32CmdAck;
	wire [31:0] register32WriteData;
	wire [7:0] register32Address;
	wire register32WriteEn;
	wire register32ReadDataValid;
	wire [31:0] register32ReadData;
									

	wire inputMemoryReadReq;
	wire inputMemoryReadAck;
	wire [(INMEM_USER_ADDRESS_WIDTH - 1):0] 		inputMemoryReadAdd;
	wire inputMemoryReadDataValid;
	wire [((INMEM_USER_BYTE_WIDTH * 8) - 1):0] 	inputMemoryReadData;


	wire outputMemoryWriteReq;
	wire outputMemoryWriteAck;
	wire [(OUTMEM_USER_ADDRESS_WIDTH - 1):0] 		outputMemoryWriteAdd;
	wire [((OUTMEM_USER_BYTE_WIDTH * 8) - 1):0]	outputMemoryWriteData;
	wire [(OUTMEM_USER_BYTE_WIDTH - 1):0]			outputMemoryWriteByteMask;

	ethernet2BlockMem #(

		.INMEM_USER_BYTE_WIDTH(INMEM_USER_BYTE_WIDTH),
		.OUTMEM_USER_BYTE_WIDTH(OUTMEM_USER_BYTE_WIDTH),
		.INMEM_USER_ADDRESS_WIDTH(INMEM_USER_ADDRESS_WIDTH),
		.OUTMEM_USER_ADDRESS_WIDTH(OUTMEM_USER_ADDRESS_WIDTH),
		.INMEM_USER_REGISTER(INMEM_USER_REGISTER),
		.MAC_ADDRESS(MAC_ADDRESS)
	) E2M(
		.refClock(clk_200),
		.clockLock(pllLock),
		.hardResetLow(hard_reset_low),
		.ethClock(clk_125_eth),
		

		.GMII_TXD(GMII_TXD_0),
		.GMII_TX_EN(GMII_TX_EN_0),
		.GMII_TX_ER(GMII_TX_ER_0),
		.GMII_GTX_CLK(GMII_GTX_CLK_0),
		.GMII_RXD(GMII_RXD_0),
		.GMII_RX_DV(GMII_RX_DV_0),
		.GMII_RX_ER(GMII_RX_ER_0),
		.GMII_RX_CLK(GMII_RX_CLK_0),
		.GMII_RESET_B(GMII_RESET_B),


		.sysACE_CLK(sysACE_CLK),
		.sysACE_MPADD(sysACE_MPADD),
		.sysACE_MPDATA(sysACE_MPDATA),
		.sysACE_MPCE(sysACE_MPCE),
		.sysACE_MPWE(sysACE_MPWE),
		.sysACE_MPOE(sysACE_MPOE),




		.userInterfaceClk(clk_user_interface),
		.userLogicReset(userLogicReset),


		.userRunValue(userRunValue),
		.userRunClear(userRunClear),
		

		.register32CmdReq(register32CmdReq),
		.register32CmdAck(register32CmdAck),
		.register32WriteData(register32WriteData),
		.register32Address(register32Address),
		.register32WriteEn(register32WriteEn),
		.register32ReadDataValid(register32ReadDataValid),
		.register32ReadData(register32ReadData),
		

		.inputMemoryReadReq(inputMemoryReadReq),
		.inputMemoryReadAck(inputMemoryReadAck),
		.inputMemoryReadAdd(inputMemoryReadAdd),
		.inputMemoryReadDataValid(inputMemoryReadDataValid),
		.inputMemoryReadData(inputMemoryReadData),
		

		.outputMemoryWriteReq(outputMemoryWriteReq),
		.outputMemoryWriteAck(outputMemoryWriteAck),
		.outputMemoryWriteAdd(outputMemoryWriteAdd),
		.outputMemoryWriteData(outputMemoryWriteData),
		.outputMemoryWriteByteMask(outputMemoryWriteByteMask)
	);




	SircHandler #(

		.INMEM_BYTE_WIDTH(INMEM_USER_BYTE_WIDTH),
		.OUTMEM_BYTE_WIDTH(OUTMEM_USER_BYTE_WIDTH),
		.INMEM_ADDRESS_WIDTH(INMEM_USER_ADDRESS_WIDTH),
		.OUTMEM_ADDRESS_WIDTH(OUTMEM_USER_ADDRESS_WIDTH)
	) sh(										
      .clk(clk_user_interface),

      .reset(userLogicReset),
		
		.userRunValue(userRunValue),
		.userRunClear(userRunClear),

		

		.register32CmdReq(register32CmdReq),
		.register32CmdAck(register32CmdAck),
		.register32WriteData(register32WriteData),
		.register32Address(register32Address),
		.register32WriteEn(register32WriteEn),
		.register32ReadDataValid(register32ReadDataValid),
		.register32ReadData(register32ReadData),
		

		.inputMemoryReadReq(inputMemoryReadReq),
		.inputMemoryReadAck(inputMemoryReadAck),
		.inputMemoryReadAdd(inputMemoryReadAdd),
		.inputMemoryReadDataValid(inputMemoryReadDataValid),
		.inputMemoryReadData(inputMemoryReadData),
		

		.outputMemoryWriteReq(outputMemoryWriteReq),
		.outputMemoryWriteAck(outputMemoryWriteAck),
		.outputMemoryWriteAdd(outputMemoryWriteAdd),
		.outputMemoryWriteData(outputMemoryWriteData),
		.outputMemoryWriteByteMask(outputMemoryWriteByteMask),
		

		.LED(LED),
		.RST(RST),
		.start(start),
		.sw(sw)
		 );
endmodule
module system #(







	parameter INMEM_USER_BYTE_WIDTH = 1,
	parameter OUTMEM_USER_BYTE_WIDTH = 1,




	parameter INMEM_USER_ADDRESS_WIDTH = 17,
	parameter OUTMEM_USER_ADDRESS_WIDTH = 13,





	parameter INMEM_USER_REGISTER = 1,


	parameter MAC_ADDRESS = 48'hAAAAAAAAAAAA
)(	
	input		wire 			CLK_100,
	input		wire 			RESET,






	output	wire [7:0]	GMII_TXD_0,
	output	wire 			GMII_TX_EN_0,
	output	wire 			GMII_TX_ER_0,
	output	wire 			GMII_GTX_CLK_0,
	input    wire [7:0]	GMII_RXD_0,
	input		wire 			GMII_RX_DV_0,
	input		wire 			GMII_RX_ER_0,
	input		wire 			GMII_RX_CLK_0,
	output	wire 			GMII_RESET_B,


	input		wire 			sysACE_CLK,
	output 	wire [6:0]	sysACE_MPADD,
	inout 	wire [15:0]	sysACE_MPDATA,
	output	wire 			sysACE_MPCE,
	output	wire 			sysACE_MPWE,
	output	wire 			sysACE_MPOE,



	output	wire [7:0]	LED,

	input wire RST,
	
	input wire start,
	input wire sw

);





	wire hard_reset_low;



	IBUF reset_ibuf (.I(RESET), .O(hard_reset_low));






	wire clk_200_i;
	wire clk_200;
	wire clk_125_eth_i;
	wire clk_125_eth;
	wire pllFB;
	wire pllLock;


	wire clk_user_interface_i;
	wire clk_user_interface;
	PLL_BASE #(
		.COMPENSATION("SYSTEM_SYNCHRONOUS"),
		.BANDWIDTH("OPTIMIZED"),

		.CLKFBOUT_MULT(10),
		.DIVCLK_DIVIDE(1),
		.CLKFBOUT_PHASE(0.0),
		.REF_JITTER(0.100),
		.CLKIN_PERIOD(10.0),

		.CLKOUT0_DIVIDE(5),
		.CLKOUT0_PHASE(0.0),
		.CLKOUT0_DUTY_CYCLE(0.5),
		.CLKOUT1_DIVIDE(8),
		.CLKOUT1_PHASE(0.0),
		.CLKOUT1_DUTY_CYCLE(0.5),




		.CLKOUT2_DIVIDE(6),
		.CLKOUT2_PHASE(0.0),
		.CLKOUT2_DUTY_CYCLE(0.5)
	) clkBPLL (
		.CLKOUT0(clk_200_i),
		.CLKOUT1(clk_125_eth_i),


		.CLKOUT2(clk_user_interface_i),
		.CLKFBOUT(pllFB),
		.CLKIN(CLK_100),
		.CLKFBIN(pllFB),
		.LOCKED(pllLock),
		.RST(~hard_reset_low)
	);


	BUFG bufCLK_200 (.O(clk_200), .I(clk_200_i));
	BUFG bufCLK_125 (.O(clk_125_eth), .I(clk_125_eth_i));
	BUFG bufCLK_user (.O(clk_user_interface), .I(clk_user_interface_i));
	





	wire userLogicReset;
	

	wire userRunValue;
	wire userRunClear;
	

	wire register32CmdReq;
	wire register32CmdAck;
	wire [31:0] register32WriteData;
	wire [7:0] register32Address;
	wire register32WriteEn;
	wire register32ReadDataValid;
	wire [31:0] register32ReadData;
									

	wire inputMemoryReadReq;
	wire inputMemoryReadAck;
	wire [(INMEM_USER_ADDRESS_WIDTH - 1):0] 		inputMemoryReadAdd;
	wire inputMemoryReadDataValid;
	wire [((INMEM_USER_BYTE_WIDTH * 8) - 1):0] 	inputMemoryReadData;


	wire outputMemoryWriteReq;
	wire outputMemoryWriteAck;
	wire [(OUTMEM_USER_ADDRESS_WIDTH - 1):0] 		outputMemoryWriteAdd;
	wire [((OUTMEM_USER_BYTE_WIDTH * 8) - 1):0]	outputMemoryWriteData;
	wire [(OUTMEM_USER_BYTE_WIDTH - 1):0]			outputMemoryWriteByteMask;

	ethernet2BlockMem #(

		.INMEM_USER_BYTE_WIDTH(INMEM_USER_BYTE_WIDTH),
		.OUTMEM_USER_BYTE_WIDTH(OUTMEM_USER_BYTE_WIDTH),
		.INMEM_USER_ADDRESS_WIDTH(INMEM_USER_ADDRESS_WIDTH),
		.OUTMEM_USER_ADDRESS_WIDTH(OUTMEM_USER_ADDRESS_WIDTH),
		.INMEM_USER_REGISTER(INMEM_USER_REGISTER),
		.MAC_ADDRESS(MAC_ADDRESS)
	) E2M(
		.refClock(clk_200),
		.clockLock(pllLock),
		.hardResetLow(hard_reset_low),
		.ethClock(clk_125_eth),
		

		.GMII_TXD(GMII_TXD_0),
		.GMII_TX_EN(GMII_TX_EN_0),
		.GMII_TX_ER(GMII_TX_ER_0),
		.GMII_GTX_CLK(GMII_GTX_CLK_0),
		.GMII_RXD(GMII_RXD_0),
		.GMII_RX_DV(GMII_RX_DV_0),
		.GMII_RX_ER(GMII_RX_ER_0),
		.GMII_RX_CLK(GMII_RX_CLK_0),
		.GMII_RESET_B(GMII_RESET_B),


		.sysACE_CLK(sysACE_CLK),
		.sysACE_MPADD(sysACE_MPADD),
		.sysACE_MPDATA(sysACE_MPDATA),
		.sysACE_MPCE(sysACE_MPCE),
		.sysACE_MPWE(sysACE_MPWE),
		.sysACE_MPOE(sysACE_MPOE),




		.userInterfaceClk(clk_user_interface),
		.userLogicReset(userLogicReset),


		.userRunValue(userRunValue),
		.userRunClear(userRunClear),
		

		.register32CmdReq(register32CmdReq),
		.register32CmdAck(register32CmdAck),
		.register32WriteData(register32WriteData),
		.register32Address(register32Address),
		.register32WriteEn(register32WriteEn),
		.register32ReadDataValid(register32ReadDataValid),
		.register32ReadData(register32ReadData),
		

		.inputMemoryReadReq(inputMemoryReadReq),
		.inputMemoryReadAck(inputMemoryReadAck),
		.inputMemoryReadAdd(inputMemoryReadAdd),
		.inputMemoryReadDataValid(inputMemoryReadDataValid),
		.inputMemoryReadData(inputMemoryReadData),
		

		.outputMemoryWriteReq(outputMemoryWriteReq),
		.outputMemoryWriteAck(outputMemoryWriteAck),
		.outputMemoryWriteAdd(outputMemoryWriteAdd),
		.outputMemoryWriteData(outputMemoryWriteData),
		.outputMemoryWriteByteMask(outputMemoryWriteByteMask)
	);




	SircHandler #(

		.INMEM_BYTE_WIDTH(INMEM_USER_BYTE_WIDTH),
		.OUTMEM_BYTE_WIDTH(OUTMEM_USER_BYTE_WIDTH),
		.INMEM_ADDRESS_WIDTH(INMEM_USER_ADDRESS_WIDTH),
		.OUTMEM_ADDRESS_WIDTH(OUTMEM_USER_ADDRESS_WIDTH)
	) sh(										
      .clk(clk_user_interface),

      .reset(userLogicReset),
		
		.userRunValue(userRunValue),
		.userRunClear(userRunClear),

		

		.register32CmdReq(register32CmdReq),
		.register32CmdAck(register32CmdAck),
		.register32WriteData(register32WriteData),
		.register32Address(register32Address),
		.register32WriteEn(register32WriteEn),
		.register32ReadDataValid(register32ReadDataValid),
		.register32ReadData(register32ReadData),
		

		.inputMemoryReadReq(inputMemoryReadReq),
		.inputMemoryReadAck(inputMemoryReadAck),
		.inputMemoryReadAdd(inputMemoryReadAdd),
		.inputMemoryReadDataValid(inputMemoryReadDataValid),
		.inputMemoryReadData(inputMemoryReadData),
		

		.outputMemoryWriteReq(outputMemoryWriteReq),
		.outputMemoryWriteAck(outputMemoryWriteAck),
		.outputMemoryWriteAdd(outputMemoryWriteAdd),
		.outputMemoryWriteData(outputMemoryWriteData),
		.outputMemoryWriteByteMask(outputMemoryWriteByteMask),
		

		.LED(LED),
		.RST(RST),
		.start(start),
		.sw(sw)
		 );
endmodule