data/full_repos/permissive/129527056/cores/sectionz/ver/timer/test.v
 line:18: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/129527056/cores/sectionz/ver/timer/test.v:9: Unsupported: Ignoring delay on this delayed statement.\n    forever #83.334 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/129527056/cores/sectionz/ver/timer/test.v:18: Define or directive not defined: \'`HOFFSET\'\nassign hoffset = `HOFFSET;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/sectionz/ver/timer/test.v:18: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign hoffset = `HOFFSET;\n                         ^\n%Error: data/full_repos/permissive/129527056/cores/sectionz/ver/timer/test.v:19: Define or directive not defined: \'`VOFFSET\'\nassign voffset = `VOFFSET;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/sectionz/ver/timer/test.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign voffset = `VOFFSET;\n                         ^\n%Error: data/full_repos/permissive/129527056/cores/sectionz/ver/timer/test.v:35: Define or directive not defined: \'`LAYOUT\'\njtgng_timer #(.LAYOUT(`LAYOUT)) UUT(\n                      ^~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/sectionz/ver/timer/test.v:72: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test.lxt");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/sectionz/ver/timer/test.v:73: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,test);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/sectionz/ver/timer/test.v:74: Unsupported or unknown PLI call: $dumpon\n    $dumpon;\n    ^~~~~~~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

reg clk;

initial begin
    clk = 0;
    forever #83.334 clk = ~clk;
end

wire [8:0] V,H;
wire       Hinit, Vinit, LHBL, LHBL_obj, LVBL, LVBL_obj, HS, VS;
wire       hs_out, vs_out;

wire [3:0] hoffset, voffset;

assign hoffset = `HOFFSET;
assign voffset = `VOFFSET;

jtframe_resync u_resync(
    .clk      (  clk         ),
    .pxl_cen  (  1'b1        ),
    .hs_in    (  HS          ),
    .vs_in    (  VS          ),
    .LVBL     (  LVBL        ),
    .LHBL     (  LHBL        ),
    .hoffset  (  hoffset     ),
    .voffset  (  voffset     ),
    .hs_out   (  hs_out      ),
    .vs_out   (  vs_out      )    
);


jtgng_timer #(.LAYOUT(`LAYOUT)) UUT(
    .clk       ( clk      ),
    .cen6      ( 1'b1     ),
    .V         ( V        ),
    .H         ( H        ),
    .Hinit     ( Hinit    ),
    .Vinit     ( Vinit    ),
    .LHBL      ( LHBL     ),
    .LHBL_obj  ( LHBL_obj ),
    .LVBL      ( LVBL     ),
    .LVBL_obj  ( LVBL_obj ),
    .HS        ( HS       ),
    .VS        ( VS       )
);

old_timer old(
    .clk       ( clk      ),
    .cen6      ( 1'b1     )
);

reg VS_last, HS_last;

wire new_HS = HS && !HS_last;
wire new_VS = VS && !VS_last;

integer framecnt=0;

always @(posedge clk) begin
    VS_last <= VS;
    HS_last <= HS;
    if( new_VS ) begin
        framecnt <= framecnt+1;
        if( framecnt==2 ) $finish;
    end
end

initial begin
    $dumpfile("test.lxt");
    $dumpvars(0,test);
    $dumpon;
end

endmodule
module test;


reg clk;

initial begin
    clk = 0;
    forever #83.334 clk = ~clk;
end

wire [8:0] V,H;
wire       Hinit, Vinit, LHBL, LHBL_obj, LVBL, LVBL_obj, HS, VS;
wire       hs_out, vs_out;

wire [3:0] hoffset, voffset;

assign hoffset = `HOFFSET;
assign voffset = `VOFFSET;

jtframe_resync u_resync(
    .clk      (  clk         ),
    .pxl_cen  (  1'b1        ),
    .hs_in    (  HS          ),
    .vs_in    (  VS          ),
    .LVBL     (  LVBL        ),
    .LHBL     (  LHBL        ),
    .hoffset  (  hoffset     ),
    .voffset  (  voffset     ),
    .hs_out   (  hs_out      ),
    .vs_out   (  vs_out      )    
);


jtgng_timer #(.LAYOUT(`LAYOUT)) UUT(
    .clk       ( clk      ),
    .cen6      ( 1'b1     ),
    .V         ( V        ),
    .H         ( H        ),
    .Hinit     ( Hinit    ),
    .Vinit     ( Vinit    ),
    .LHBL      ( LHBL     ),
    .LHBL_obj  ( LHBL_obj ),
    .LVBL      ( LVBL     ),
    .LVBL_obj  ( LVBL_obj ),
    .HS        ( HS       ),
    .VS        ( VS       )
);

old_timer old(
    .clk       ( clk      ),
    .cen6      ( 1'b1     )
);

reg VS_last, HS_last;

wire new_HS = HS && !HS_last;
wire new_VS = VS && !VS_last;

integer framecnt=0;

always @(posedge clk) begin
    VS_last <= VS;
    HS_last <= HS;
    if( new_VS ) begin
        framecnt <= framecnt+1;
        if( framecnt==2 ) $finish;
    end
end

initial begin
    $dumpfile("test.lxt");
    $dumpvars(0,test);
    $dumpon;
end

endmodule