data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:231: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h21\' generates 8 bits.\n                                                                                                : ... In instance processor\n    i2c_addr=8\'h21;  \n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:334: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 8 bits.\n                                                                                                : ... In instance processor\n     else getadcadr<=(readdata-110); \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:345: Operator ADD expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     nsamp=256*extradata[0]+extradata[1];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:356: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     triggerpoint=256*extradata[0]+extradata[1];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:368: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     nsmp=256*extradata[0]+extradata[1];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:379: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     sendincrement=extradata[0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:390: Operator SUB expects 32 bits on the LHS, but LHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     clockbitstowaitlockin = extradata[0]-2;  \n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:400: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     clockbitstowait=extradata[0];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:428: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     triggertype=extradata[0];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:438: Operator ADD expects 32 or 13 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     triggertot=256*extradata[0]+extradata[1];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:501: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h20\' generates 8 bits.\n                                                                                                : ... In instance processor\n     i2c_addr=8\'h20;  \n             ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:519: Operator ADD expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     serialdelaytimerwait=50*(256*extradata[0]+extradata[1]);  \n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:532: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     i2c_datacounttosend=extradata[0]; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:533: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     i2c_addr=extradata[1];  \n             ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:557: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     lockinnumtoshift = 256*extradata[0]+extradata[1];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:589: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h20\' generates 8 bits.\n                                                                                                : ... In instance processor\n     i2c_addr=8\'h20;  \n             ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:640: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     blockstosend = extradata[0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:650: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                                : ... In instance processor\n     i2c_addr=extradata[0];  \n             ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:723: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'ram_output3\' generates 8 bits.\n                                                                                                : ... In instance processor\n     chan2mean = chan2mean + ram_output3;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:724: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'ram_output4\' generates 8 bits.\n                                                                                                : ... In instance processor\n     chan3mean = chan3mean + ram_output4;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:735: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output3\' generates 8 bits.\n                                                                                                : ... In instance processor\n      lockinresult2 = lockinresult2 + (ram_output3-chan2mean)*(ram_output4-chan3mean);  \n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:735: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output4\' generates 8 bits.\n                                                                                                : ... In instance processor\n      lockinresult2 = lockinresult2 + (ram_output3-chan2mean)*(ram_output4-chan3mean);  \n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:734: Operator GT expects 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                                : ... In instance processor\n     if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:734: Operator LT expects 32 or 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                                : ... In instance processor\n     if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:741: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output3\' generates 8 bits.\n                                                                                                : ... In instance processor\n      lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean);  \n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:741: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ram_output4\' generates 8 bits.\n                                                                                                : ... In instance processor\n      lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean);  \n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:740: Operator GT expects 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                                : ... In instance processor\n     if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:740: Operator LT expects 32 or 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                                : ... In instance processor\n     if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:750: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'rdaddress\' generates 12 bits.\n                                                                                                : ... In instance processor\n   if (SendCount[ram_width+1:ram_width]==1) rdaddress2=rdaddress-lockinnumtoshift;\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:750: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s SUB generates 16 bits.\n                                                                                                : ... In instance processor\n   if (SendCount[ram_width+1:ram_width]==1) rdaddress2=rdaddress-lockinnumtoshift;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:795: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'numlockinbytes\' generates 8 bits.\n                                                                                                : ... In instance processor\n        if (ioCount < numlockinbytes-1) begin\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:853: Operator EQ expects 8 bits on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                                : ... In instance processor\n       if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]); \n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:883: Operator GT expects 32 bits on the LHS, but LHS\'s VARREF \'usb2counter\' generates 8 bits.\n                                                                                                : ... In instance processor\n   if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]!=thecounterbit)) begin  \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:917: Operator EQ expects 8 bits on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                                : ... In instance processor\n      if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]); \n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:903: Operator GT expects 32 bits on the LHS, but LHS\'s VARREF \'usb2counter\' generates 8 bits.\n                                                                                                : ... In instance processor\n   if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]==thecounterbit) ) begin  \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:945: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'writesamp\' generates 12 bits.\n                                                                                                : ... In instance processor\n    if (writesamp>=(nsamp-1)) begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:961: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                : ... In instance processor\n    if (writebyte) txData=adcramdata[11:8];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:971: Operator GT expects 32 bits on the LHS, but LHS\'s VARREF \'writesamp\' generates 12 bits.\n                                                                                                : ... In instance processor\n   if (writesamp>(nsamp-1)) state=READ;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1043: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                                 : ... In instance processor\n    i2c_datawr = i2cdata[i2c_datacount];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1081: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                                                 : ... In instance processor\n    if (columndata[2:0]>b) screendata[b]=1; \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1081: Operator GT expects 4 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                                                 : ... In instance processor\n    if (columndata[2:0]>b) screendata[b]=1; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1077: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'row\' generates 3 bits.\n                                                                                                 : ... In instance processor\n  if (columndata>=8*(row+1)) screendata = 8\'hff;  \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1092: Operator GTE expects 8 bits on the RHS, but RHS\'s SEL generates 6 bits.\n                                                                                                 : ... In instance processor\n   if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8\'hfa;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:1095: Operator GTE expects 8 bits on the RHS, but RHS\'s SEL generates 6 bits.\n                                                                                                 : ... In instance processor\n   if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8\'hfa;\n           ^~\n%Warning-UNSIGNED: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:852: Comparison is constant due to unsigned arithmetic\n                                                                                                   : ... In instance processor\n      if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin  \n                                                 ^~\n%Warning-UNSIGNED: data/full_repos/permissive/112978342/max10_adc_firmware_v8/serialprocessor.v:916: Comparison is constant due to unsigned arithmetic\n                                                                                                   : ... In instance processor\n     if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin  \n                                                ^~\n%Error: Exiting due to 46 warning(s)\n'
module processor(clk, rxReady, rxData, txBusy, txStart, txData, readdata, get_ext_data, ext_data_ready, wraddress_triggerpoint, rden, rdaddress, ram_output1, ram_output2, ram_output3, ram_output4,
newcomdata,comdata,spare1,spare2,spare3,serial_passthrough,master_clock, imthelast,imthefirst,rollingtrigger,trigDebug, 
adcdata,adcready,getadcdata,getadcadr,adcvalid,adcreset,adcramdata,writesamp,writeadc,adctestout,
triggerpoint,downsample, screendata,screenwren,screenaddr,screenreset,trigthresh,trigchannels,triggertype,triggertot,
SPIsend,SPIsenddata,delaycounter,carrycounter,usb_siwu,SPIstate,offset,gainsw,do_usb,
i2c_ena,i2c_addr,i2c_rw,i2c_datawr,i2c_datard,i2c_busy,i2c_ackerror,   usb_clk60,usb_dataio,usb_txe_busy,usb_wr,
rdaddress2,trigthresh2, debug1,debug2,chip_id, highres,  use_ext_trig,  digital_buffer1, nsmp);
   input clk;
	input[7:0] rxData;
   input rxReady;
   input txBusy;
   output reg txStart;
   output reg[7:0] txData;
   output reg[7:0] readdata;
   output reg spare1,spare2,spare3;
	reg led1,led2,led3,led4,led5,led6,led7,led8;
  	output reg get_ext_data;
	input ext_data_ready;
	parameter ram_width=12;
	input wire[ram_width-1:0] wraddress_triggerpoint;
	output reg [ram_width-1:0] rdaddress;
	output reg [ram_width-1:0] rdaddress2;
	output reg [ram_width-1:0] triggerpoint;
	output reg rden;
	input wire [7:0] ram_output1;
	input wire [7:0] ram_output2;
	input wire [7:0] ram_output3;
	input wire [7:0] ram_output4;
	input wire [7:0] digital_buffer1;
	output reg serial_passthrough;
	output reg [1:0] master_clock;
	output reg[7:0] comdata;
	output reg newcomdata;
	output reg imthelast;
	output wire imthefirst;
	output reg rollingtrigger;
	input trigDebug;
	input [11:0] adcdata;
	input adcready;
	input adcvalid;
	output reg getadcdata;
	output reg [4:0] getadcadr;
	output reg adcreset;
	output reg [11:0] writesamp;
	output reg writeadc;
	output reg [11:0] adctestout;
	output reg [7:0] downsample;
	output reg [7:0] screendata;
	output reg screenwren=0;
	output reg [9:0] screenaddr = 10'd0;
	output reg screenreset=0;
	output reg [7:0] trigthresh = 8'h80, trigthresh2=8'hff;
	output reg [3:0] trigchannels = 4'b1111;
	output reg [3:0] triggertype = 4'b0001;
   output reg [ram_width:0] triggertot;
	output reg [15:0] SPIsenddata;
	output reg SPIsend;
	input [7:0] delaycounter;
	input [7:0] carrycounter;
	input [3:0] SPIstate;
	output wire[3:0] offset;
	output reg[3:0] gainsw;
	reg[3:0] oversamp;
	output reg debug1,debug2;
	input [63:0] chip_id;
	output reg highres=0;
	output reg use_ext_trig=0;
	
	output reg i2c_ena;
	output reg [6:0] i2c_addr;
	output reg i2c_rw;
	output reg [7:0] i2c_datawr;
	input [7:0] i2c_datard;
	input i2c_busy;
	input i2c_ackerror;
	reg [7:0] i2cdata[8];
	reg [3:0] i2c_datacounttosend,i2c_datacount;
	reg i2cgo=0;
	reg i2cdoread=0;

  localparam READ=0, SOLVING=1, WAITING=2, WRITE_EXT1=3, WRITE_EXT2=4, WAIT_ADC1=5, WAIT_ADC2=6, WRITE_BYTE1=7, WRITE_BYTE2=8, READMORE=9, 
	WRITE1=10, WRITE2=11,SPIWAIT=12,I2CWAIT=13,I2CSEND1=14,I2CSEND2=15,
	LOCKIN1=18,LOCKIN2=19,LOCKIN3=20,LOCKINWRITE1=21,LOCKINWRITE2=22,
	WRITE_USB_EXT1=33, WRITE_USB_EXT2=34, WRITE_USB_EXT3=35, WRITE_USB_EXT4=36, WRITE_USB_EXT5=37;
  integer state,i2cstate;

  reg [7:0] myid;
  assign imthefirst = (myid==0);
  reg [7:0] extradata[10];
  reg [ram_width+2:0] SendCount=0;
  reg [2:0] blockstosend=4;
  integer nsamp = 6;
  input [11:0] adcramdata;
  reg writebyte;
  integer bytesread, byteswanted;
  reg thecounterbit, thecounterbitlockin;
  integer clockbitstowait=5, clockbitstowaitlockin=3;
  reg [3:0] sendincrement = 0;
  output reg [ram_width-1:0] nsmp = 0;
  reg [7:0] chanforscreen=0;
  reg autorearm=0;
  integer thecounter=0, timeoutcounter=0, serialdelaytimer=0,serialdelaytimerwait=0;
  
  reg [7:0] usb2counter;
  output reg do_usb=0;
  input usb_clk60;
  output reg [7:0] usb_dataio;
  input usb_txe_busy;
  output reg usb_wr, usb_siwu;
  reg usb_txe_not_busy;
  

  reg [5:0] screencolumndata [128];
  

  integer ioCount, ioCountToSend;
  reg[7:0] data[0:15];
  

  reg [7:0] numlockinbytes=16;
  integer lockinresult1;
  integer lockinresult2;
  reg [15:0] lockinnumtoshift = 0;
  integer chan2mean, chan3mean;
  reg calcmeans;
  
  initial begin
    state<=READ;
	 i2cstate<=READ;
	 myid<=200;
	 master_clock<=2'b00;
	 imthelast<=0;
	 rollingtrigger<=1;
	 triggerpoint<=(2**(ram_width-2));
	 downsample<=1;
	 serial_passthrough<=0;
	 usb_siwu<=1;
	 gainsw<=4'b0000;
	 oversamp<=4'b0011;
  	 debug1<=0; debug2<=0;
	 spare1<=0;
	 spare2<=0;
	 spare3<=0;
	 led4<=1;
	 led5<=0;
	 led6<=0;
	 led7<=0;
	 led8<=0;
  end
  

  always @(posedge clk) begin
	thecounter<=thecounter+1;
	usb_txe_not_busy <= ~usb_txe_busy;
	debug1 <= usb_txe_not_busy;
   if ( imthelast & thecounter[26]==1'b1 ) begin
		led1<=0;		led2<=0;		led3<=0;
	end




	else if (myid==0) begin	   
		led1<=1;		led2<=1;		led3<=1;
	end
	else if (myid==1) begin	   
		led1<=0;		led2<=1;		led3<=1;
	end
	else if (myid==2) begin	   
		led1<=1;		led2<=0;		led3<=1;
	end
	else if (myid==3) begin	   
		led1<=0;		led2<=0;		led3<=1;
	end
	else if (myid==4) begin	   
		led1<=1;		led2<=1;		led3<=0;
	end
	else begin		
		led1<=0;		led2<=0;		led3<=0;
	end
  end
  reg oldled1,oldled2,oldled3,oldled4,oldled5,oldled6,oldled7,oldled8;
  




















  
  always @(posedge clk) begin
    case (state)
	 
      READ: begin
		  get_ext_data<=0;
		  adcreset<=1;
		  txStart<=0;
		  getadcdata<=0;
		  bytesread<=0;
		  byteswanted<=0;
		  newcomdata<=0;
		  SPIsend<=0;
		  i2cgo=0;
		  usb_wr<=1;
        ioCount = 0;
        if (rxReady) begin
			 readdata = rxData;
          state = SOLVING;
        end
		  if (oldled1!=led1 || oldled2!=led2 || oldled3!=led3 || oldled4!=led4 || oldled5!=led5 || oldled6!=led6 || oldled7!=led7 || oldled8!=led8) begin
			 oldled1=led1; oldled2=led2; oldled3=led3; oldled4=led4;
			 oldled5=led5; oldled6=led6; oldled7=led7; oldled8=led8;

			 i2c_datacounttosend=2;
			 i2c_addr=8'h21;
			 i2cdata[0]=8'h12;
			 i2cdata[1][0]=led1; i2cdata[1][1]=led2; i2cdata[1][2]=led3; i2cdata[1][3]=led4;
			 i2cdata[1][4]=led5; i2cdata[1][5]=led6; i2cdata[1][6]=led7; i2cdata[1][7]=led8;
			 i2cdata[2]=0;
			 if (i2cstate==READ) begin
			   i2cdoread = 0;
				i2cgo=1;
			 end
		  end
      end
		
		READMORE: begin
			newcomdata=0;
			if (rxReady) begin
				extradata[bytesread] = rxData;
				comdata=rxData;
				newcomdata=1;
				bytesread = bytesread+1;
				if (bytesread>=byteswanted) state=SOLVING;
			end
		end

      SOLVING: begin
			if (readdata < 10) begin
				myid=readdata;
				if (readdata==0) begin
					master_clock=2'b00;
				end
				else master_clock=2'b01;
				comdata=(readdata+1);
				newcomdata=1;
				state=READ;
			end
			else if (readdata > 9 && readdata < 20) begin
				if (myid==(readdata-10)) begin

					serial_passthrough=0;
					timeoutcounter=0;
					state=WAITING;
				end
				else begin

					serial_passthrough=1;
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
			end
			else if (readdata > 19 && readdata < 30) begin
				if (myid==(readdata-20)) imthelast=1;
				else imthelast=0;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata > 29 && readdata < 40) begin
				if (myid==(readdata-30)) begin

					serial_passthrough=0;
				end
				else begin

					serial_passthrough=1;
					comdata=readdata;
					newcomdata=1;
				end
				state=READ;
			end
			
			else if (100==readdata) begin

				get_ext_data=1;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			
			else if (101==readdata) begin

				led5=1;
				rollingtrigger=1;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (102==readdata) begin

				led5=0;
				rollingtrigger=0;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			
			else if (readdata>109 && readdata<120) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					if (readdata==119) getadcadr<=17;
					else getadcadr<=(readdata-110);
					writesamp<=0;
					state=WAIT_ADC1;
				end
			end
			else if (readdata==120) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					nsamp=256*extradata[0]+extradata[1];
					if (nsamp>4095) nsamp=4095;
					state=READ;
				end
			end
			else if (readdata==121) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggerpoint=256*extradata[0]+extradata[1];
					if (triggerpoint>(2**ram_width)-16) triggerpoint=(2**ram_width)-16;
					else if (triggerpoint<4) triggerpoint=4;
					state=READ;
				end
			end
			else if (readdata==122) begin
				byteswanted=2;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					nsmp=256*extradata[0]+extradata[1];
					if (triggerpoint>(nsmp-5)) triggerpoint=nsmp/2;
					state=READ;
				end
			end
			else if (readdata==123) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					sendincrement=extradata[0];
					state=READ;
				end
			end
			else if (readdata==124) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]>30) extradata[0]=30;
					downsample=extradata[0];
					clockbitstowaitlockin = extradata[0]-2;
					state=READ;
				end
			end
			else if (readdata==125) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]>30) extradata[0]=30;
					clockbitstowait=extradata[0];
					state=READ;
				end
			end
			else if (readdata==126) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					chanforscreen=extradata[0];
					state=READ;
				end
			end
			
			else if (readdata==127) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					trigthresh=extradata[0];
					state=READ;
				end
			end
			else if (readdata==128) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggertype=extradata[0];
					state=READ;
				end
			end
			else if (readdata==129) begin
				byteswanted=2;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggertot=256*extradata[0]+extradata[1];
					state=READ;
				end
			end
			else if (readdata==130) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						trigchannels[extradata[0]%4]=~trigchannels[extradata[0]%4];
					end
					state=READ;
				end
			end
			else if (readdata==131) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					SPIsenddata[15:8]=extradata[0];
					SPIsenddata[7:0]=extradata[1];
					SPIsenddata[15]=1'b0;
					SPIsend=1;
					state=SPIWAIT;
				end
			end
			else if (readdata==132) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=delaycounter;
					state=WRITE1;
				end
			end
			else if (readdata==133) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=carrycounter;
					state=WRITE1;
				end
			end
			else if (readdata==134) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						gainsw[extradata[0]%4]=~gainsw[extradata[0]%4];
					end

					i2c_datacounttosend=2;
					i2c_addr=8'h20;
					i2cdata[0]=8'h12;
					i2cdata[1][3:0]=gainsw;
					i2cdata[1][7:4]=oversamp;
					i2cdata[2]=0;
					if (i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end
			else if (readdata==135) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					serialdelaytimerwait=50*(256*extradata[0]+extradata[1]);
					state=READ;
				end
			end
			else if (readdata==136) begin
				byteswanted=6;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin



					i2c_datacounttosend=extradata[0];
					i2c_addr=extradata[1];
					i2cdata[0]=extradata[2];
					i2cdata[1]=extradata[3];
					i2cdata[2]=extradata[4];
					if ((extradata[5]==myid || extradata[5]==200) && i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end
			else if (137==readdata) begin

				do_usb=~do_usb;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==138) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					lockinnumtoshift = 256*extradata[0]+extradata[1];
					state=READ;
				end
			end
			else if (139==readdata) begin

				autorearm=~autorearm;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==140) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					trigthresh2 = extradata[0];
					state=READ;
				end
			end
			else if (readdata==141) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						oversamp[extradata[0]%4]=~oversamp[extradata[0]%4];
					end

					i2c_datacounttosend=2;
					i2c_addr=8'h20;
					i2cdata[0]=8'h12;
					i2cdata[1][3:0]=gainsw;
					i2cdata[1][7:4]=oversamp;
					i2cdata[2]=0;
					if (i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end			
			else if (readdata==142) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					data[0]=chip_id[7+8*0:8*0];
					data[1]=chip_id[7+8*1:8*1];
					data[2]=chip_id[7+8*2:8*2];
					data[3]=chip_id[7+8*3:8*3];
					data[4]=chip_id[7+8*4:8*4];
					data[5]=chip_id[7+8*5:8*5];
					data[6]=chip_id[7+8*6:8*6];
					data[7]=chip_id[7+8*7:8*7];
					ioCountToSend = 8;
					state=WRITE1;
				end
			end
			else if (143==readdata) begin

				highres=~highres;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (144==readdata) begin

				use_ext_trig=~use_ext_trig;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==145) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					blockstosend = extradata[0];
					state=READ;
				end
			end
			else if (readdata==146) begin
				byteswanted=3;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					i2c_addr=extradata[0];
					i2c_datacounttosend=2;
					i2cdata[0]=extradata[1];
					i2cdata[1]=0;
					if ((extradata[2]==myid || extradata[2]==200) && i2cstate==READ) begin
						i2cdoread = 1;
						i2cgo=1;

						ioCountToSend = 1;
						data[0] = i2c_datard;
						state=WRITE1;
					end
					else state=READ;
				end
			end
			else if (readdata==147) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=5;
					state=WRITE1;
				end
			end
			
			else state=READ;
      end
		
		SPIWAIT: begin
			newcomdata<=0;

			if (SPIstate==3) begin 
				state=READ;
			end
		end
		
		WAITING: begin
			timeoutcounter=timeoutcounter+1;
			if (ext_data_ready) begin
				SendCount= 0;
				rdaddress = wraddress_triggerpoint - triggerpoint;
				rdaddress2 = rdaddress;
				thecounterbit=thecounter[clockbitstowait];
				thecounterbitlockin=thecounter[clockbitstowaitlockin];
				if (lockinnumtoshift>0) begin
					lockinresult1=0;
					lockinresult2=0;
					chan2mean=0;
					chan3mean=0;
					calcmeans=1;
					state=LOCKIN1;
				end
				else begin
					if (do_usb) state=WRITE_USB_EXT1;
					else state=WRITE_EXT1;
				end
			end
			if ( timeoutcounter > 100000000 ) begin
				state=READ;



			end
		end
		LOCKIN1: begin
			rden = 1;
			if ( (thecounter[clockbitstowaitlockin]!=thecounterbitlockin) ) begin
			case(SendCount[ram_width+1:ram_width])
				0: begin

					chan2mean = chan2mean + ram_output3;
					chan3mean = chan3mean + ram_output4;
				end
				1: begin
					if (calcmeans) begin
						calcmeans=0;
						chan2mean = chan2mean/4096;
						chan3mean = chan3mean/4096;
					end


					if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
						lockinresult2 = lockinresult2 + (ram_output3-chan2mean)*(ram_output4-chan3mean);
					end
				end
				2: begin

					if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
						lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean);
					end
				end
				3: begin
						
				end
			endcase			
			SendCount = SendCount + 1;
			rdaddress = rdaddress + 1;
			if (SendCount[ram_width+1:ram_width]==1) rdaddress2=rdaddress-lockinnumtoshift;
			else rdaddress2=rdaddress;
			state=LOCKIN2;
			end
		end
		LOCKIN2: begin	
			state=LOCKIN3;
		end
		LOCKIN3: begin
			if ( (thecounter[clockbitstowaitlockin]==thecounterbitlockin) ) begin
			if(SendCount[ram_width+1:0]==0) begin
				ioCount = 0;
				SendCount = 0;
				state=LOCKINWRITE1;
			end
			else begin
				state=LOCKIN1;
			end
			end
		end
		LOCKINWRITE1: begin
       if (!txBusy) begin
          if (ioCount==0) txData = lockinresult1[7+8*0:0+8*0];
          else if (ioCount==1) txData = lockinresult1[7+8*1:0+8*1];
          else if (ioCount==2) txData = lockinresult1[7+8*2:0+8*2];
          else if (ioCount==3) txData = lockinresult1[7+8*3:0+8*3];
          else if (ioCount==4) txData = lockinresult2[7+8*0:0+8*0];
          else if (ioCount==5) txData = lockinresult2[7+8*1:0+8*1];
          else if (ioCount==6) txData = lockinresult2[7+8*2:0+8*2];
          else if (ioCount==7) txData = lockinresult2[7+8*3:0+8*3];			 
			 else if (ioCount==8) txData = chan2mean[7+8*0:0+8*0];
          else if (ioCount==9) txData = chan2mean[7+8*1:0+8*1];
          else if (ioCount==10) txData = chan2mean[7+8*2:0+8*2];
          else if (ioCount==11) txData = chan2mean[7+8*3:0+8*3];
			 else if (ioCount==12) txData = chan3mean[7+8*0:0+8*0];
          else if (ioCount==13) txData = chan3mean[7+8*1:0+8*1];
          else if (ioCount==14) txData = chan3mean[7+8*2:0+8*2];
          else if (ioCount==15) txData = chan3mean[7+8*3:0+8*3];
			 else txData = 0;
          txStart = 1;
          state = LOCKINWRITE2;
        end
      end
      LOCKINWRITE2: begin
        txStart = 0;
        if (ioCount < numlockinbytes-1) begin
          ioCount = ioCount + 1;
          state = LOCKINWRITE1;
        end
		  else begin
				rdaddress = wraddress_triggerpoint - triggerpoint;
				rdaddress2 = rdaddress;
				thecounterbit=thecounter[clockbitstowait];
				if (do_usb) state=WRITE_USB_EXT1;
				else state=WRITE_EXT1;
        end
      end
		WRITE_EXT1: begin
			timeoutcounter=timeoutcounter+1;
			rden = 1;

			case(SendCount[ram_width+2:ram_width])
			0: txData<=ram_output1;
			1: txData<=ram_output2;
			2: txData<=ram_output3;
			3: txData<=ram_output4;
			4: txData<=digital_buffer1;
			endcase
			if( (!txBusy) && (thecounter[clockbitstowait]!=thecounterbit)) begin
				txStart<= 1;				
				SendCount = SendCount + (2**sendincrement);
				rdaddress = rdaddress + (2**sendincrement);
				rdaddress2 = rdaddress;
				if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
					SendCount[ram_width-1:0]=0;
					SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
					rdaddress = wraddress_triggerpoint - triggerpoint;
					rdaddress2 = rdaddress;
				end
				state=WRITE_EXT2;
			end
			if ( timeoutcounter > 100000000 ) begin
				rden = 0;
				state=READ;
			end
		end
		WRITE_EXT2: begin
			if( thecounter[clockbitstowait]==thecounterbit ) begin
				txStart<= 0;			
				if(SendCount[ram_width+2:ram_width]==blockstosend) begin
					rden = 0;
					if (autorearm) begin

						get_ext_data=1;
					end
					state=READ;
				end
				else begin					
					if(SendCount[4:0]==0 && serialdelaytimer<serialdelaytimerwait) begin
						serialdelaytimer=serialdelaytimer+1;
					end
					else begin
						if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin
							if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]);
							screenwren = 1;
						end
						serialdelaytimer=0;
						state=WRITE_EXT1;
					end
				end
			end
		end
		
		WRITE_USB_EXT1: begin
			if (usb_txe_not_busy) begin
				thecounterbit=thecounter[clockbitstowait];
				usb2counter<=0;
				state=WRITE_USB_EXT2;
			end
			debug2<=1;
			rden = 1;
		end
		WRITE_USB_EXT2: begin
			debug2<=0;
			usb2counter<=usb2counter+1;

			case(SendCount[ram_width+2:ram_width])
				0: usb_dataio<=ram_output1;
				1: usb_dataio<=ram_output2;
				2: usb_dataio<=ram_output3;
				3: usb_dataio<=ram_output4;
				4: usb_dataio<=digital_buffer1;
			endcase
			if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]!=thecounterbit)) begin
				SendCount = SendCount + (2**sendincrement);
				rdaddress = rdaddress + (2**sendincrement);
				rdaddress2 = rdaddress;
				if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
					SendCount[ram_width-1:0]=0;
					SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
					rdaddress = wraddress_triggerpoint - triggerpoint;
					rdaddress2 = rdaddress;
				end
				state=WRITE_USB_EXT3;
			end
		end
		WRITE_USB_EXT3: begin
			usb_wr<= 0;
			usb2counter<=0;
			state=WRITE_USB_EXT4;
		end
		WRITE_USB_EXT4: begin
			usb2counter=usb2counter+1;
			if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]==thecounterbit) ) begin
				usb_wr<= 1;	
				if(SendCount[ram_width+2:ram_width]==blockstosend) begin
					rden = 0;
					if (autorearm) begin

						get_ext_data=1;
					end
					state=WRITE_USB_EXT5;
				end
				else begin
					usb2counter=0;
					state=WRITE_USB_EXT1;
					if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin
						if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]);
						screenwren = 1;
					end
				end
			end
		end
		WRITE_USB_EXT5: begin
			usb_siwu=0;
			usb2counter<=usb2counter+1;
			if( (usb2counter>8) ) begin
				state=READ;
				usb_siwu=1;
			end
		end

		WAIT_ADC1: begin
			newcomdata<=0;
			writeadc<=0;
			getadcdata<=1;

				state=WAIT_ADC2;

		end
		WAIT_ADC2: begin
			if (adcvalid) begin
				adctestout<=adcdata;
				writeadc<=1;
				getadcdata<=0;
				if (writesamp>=(nsamp-1)) begin
					writesamp<=0;
					writebyte<=0;
					thecounterbit=thecounter[clockbitstowait];
					state<=WRITE_BYTE1;
				end
				else begin
					writesamp=writesamp+1;
					state=WAIT_ADC1;
				end
			end
		end
		WRITE_BYTE1: begin
			newcomdata<=0;
			writeadc<=0;
			if(!txBusy && (thecounter[clockbitstowait]!=thecounterbit)) begin
				if (writebyte) txData=adcramdata[11:8];
				else txData=adcramdata[7:0];
				txStart=1;
				state=WRITE_BYTE2;
			end
		end
		WRITE_BYTE2: begin
			txStart=0;
			if (writebyte) writesamp=writesamp+1;
			writebyte = ~writebyte;
			if (writesamp>(nsamp-1)) state=READ;
			else state=WRITE_BYTE1;
		end
		

		WRITE1: begin
       newcomdata<=0;
       if (!txBusy) begin
          txData = data[ioCount];
          txStart = 1;
          state = WRITE2;
        end
      end
      WRITE2: begin
        txStart = 0;
        if (ioCount < ioCountToSend-1) begin
          ioCount = ioCount + 1;
          state = WRITE1;
        end else begin
          state = READ;
        end
      end
		



















		
    endcase
	 
  end  
  

  always @(posedge clk) begin
   case (i2cstate)
		READ: begin
			i2c_ena<=0;
			if (i2cgo) begin
				i2cstate=I2CWAIT;
			end
		end
		I2CWAIT: begin
			if (~i2c_busy) begin

				i2c_rw=0;

				i2c_datawr = i2cdata[0];
				i2c_datacount=1;
				i2cstate=I2CSEND1;
			end
		end
		I2CSEND1: begin
			i2c_ena = 1;
			if (i2c_datacount >= i2c_datacounttosend) begin
				i2cstate=READ;
			end
			else if (i2c_busy) begin
				i2c_datawr = i2cdata[i2c_datacount];
				if (i2cdoread) begin
					i2c_rw=1;
				end
				i2cstate=I2CSEND2;
			end
		end
		I2CSEND2: begin
			if (~i2c_busy) begin

				i2c_datacount = i2c_datacount+1;
				i2cstate=I2CSEND1;
			end
		end
	endcase
	end
  

	reg [5:0] columndata;
	reg [2:0] row;
	reg [6:0] column;
	reg [3:0] b;
	always @(posedge clk) begin
		if (screenaddr>1000) screenreset<=1;
		screenaddr = screenaddr + 1;
		row=7-screenaddr[9:7];
		column=screenaddr[6:0];
		


		
		columndata = screencolumndata[column];
		

		if (columndata>=8*(row+1)) screendata = 8'hff;
		else if (columndata>=8*row) begin
			screendata=8'h00; b=0;
			while (b<8) begin
				if (columndata[2:0]>b) screendata[b]=1;
				b=b+1;
			end
		end
		else screendata = 8'h00;
		


		

		if (row==7 & trigDebug) begin
			if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
		end
		if (row==6 & !trigDebug) begin
			if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
		end	
	end
	
endmodule
module processor(clk, rxReady, rxData, txBusy, txStart, txData, readdata, get_ext_data, ext_data_ready, wraddress_triggerpoint, rden, rdaddress, ram_output1, ram_output2, ram_output3, ram_output4,
newcomdata,comdata,spare1,spare2,spare3,serial_passthrough,master_clock, imthelast,imthefirst,rollingtrigger,trigDebug, 
adcdata,adcready,getadcdata,getadcadr,adcvalid,adcreset,adcramdata,writesamp,writeadc,adctestout,
triggerpoint,downsample, screendata,screenwren,screenaddr,screenreset,trigthresh,trigchannels,triggertype,triggertot,
SPIsend,SPIsenddata,delaycounter,carrycounter,usb_siwu,SPIstate,offset,gainsw,do_usb,
i2c_ena,i2c_addr,i2c_rw,i2c_datawr,i2c_datard,i2c_busy,i2c_ackerror,   usb_clk60,usb_dataio,usb_txe_busy,usb_wr,
rdaddress2,trigthresh2, debug1,debug2,chip_id, highres,  use_ext_trig,  digital_buffer1, nsmp);

   input clk;
	input[7:0] rxData;
   input rxReady;
   input txBusy;
   output reg txStart;
   output reg[7:0] txData;
   output reg[7:0] readdata;
   output reg spare1,spare2,spare3;
	reg led1,led2,led3,led4,led5,led6,led7,led8;
  	output reg get_ext_data;
	input ext_data_ready;
	parameter ram_width=12;
	input wire[ram_width-1:0] wraddress_triggerpoint;
	output reg [ram_width-1:0] rdaddress;
	output reg [ram_width-1:0] rdaddress2;
	output reg [ram_width-1:0] triggerpoint;
	output reg rden;
	input wire [7:0] ram_output1;
	input wire [7:0] ram_output2;
	input wire [7:0] ram_output3;
	input wire [7:0] ram_output4;
	input wire [7:0] digital_buffer1;
	output reg serial_passthrough;
	output reg [1:0] master_clock;
	output reg[7:0] comdata;
	output reg newcomdata;
	output reg imthelast;
	output wire imthefirst;
	output reg rollingtrigger;
	input trigDebug;
	input [11:0] adcdata;
	input adcready;
	input adcvalid;
	output reg getadcdata;
	output reg [4:0] getadcadr;
	output reg adcreset;
	output reg [11:0] writesamp;
	output reg writeadc;
	output reg [11:0] adctestout;
	output reg [7:0] downsample;
	output reg [7:0] screendata;
	output reg screenwren=0;
	output reg [9:0] screenaddr = 10'd0;
	output reg screenreset=0;
	output reg [7:0] trigthresh = 8'h80, trigthresh2=8'hff;
	output reg [3:0] trigchannels = 4'b1111;
	output reg [3:0] triggertype = 4'b0001;
   output reg [ram_width:0] triggertot;
	output reg [15:0] SPIsenddata;
	output reg SPIsend;
	input [7:0] delaycounter;
	input [7:0] carrycounter;
	input [3:0] SPIstate;
	output wire[3:0] offset;
	output reg[3:0] gainsw;
	reg[3:0] oversamp;
	output reg debug1,debug2;
	input [63:0] chip_id;
	output reg highres=0;
	output reg use_ext_trig=0;
	
	output reg i2c_ena;
	output reg [6:0] i2c_addr;
	output reg i2c_rw;
	output reg [7:0] i2c_datawr;
	input [7:0] i2c_datard;
	input i2c_busy;
	input i2c_ackerror;
	reg [7:0] i2cdata[8];
	reg [3:0] i2c_datacounttosend,i2c_datacount;
	reg i2cgo=0;
	reg i2cdoread=0;

  localparam READ=0, SOLVING=1, WAITING=2, WRITE_EXT1=3, WRITE_EXT2=4, WAIT_ADC1=5, WAIT_ADC2=6, WRITE_BYTE1=7, WRITE_BYTE2=8, READMORE=9, 
	WRITE1=10, WRITE2=11,SPIWAIT=12,I2CWAIT=13,I2CSEND1=14,I2CSEND2=15,
	LOCKIN1=18,LOCKIN2=19,LOCKIN3=20,LOCKINWRITE1=21,LOCKINWRITE2=22,
	WRITE_USB_EXT1=33, WRITE_USB_EXT2=34, WRITE_USB_EXT3=35, WRITE_USB_EXT4=36, WRITE_USB_EXT5=37;
  integer state,i2cstate;

  reg [7:0] myid;
  assign imthefirst = (myid==0);
  reg [7:0] extradata[10];
  reg [ram_width+2:0] SendCount=0;
  reg [2:0] blockstosend=4;
  integer nsamp = 6;
  input [11:0] adcramdata;
  reg writebyte;
  integer bytesread, byteswanted;
  reg thecounterbit, thecounterbitlockin;
  integer clockbitstowait=5, clockbitstowaitlockin=3;
  reg [3:0] sendincrement = 0;
  output reg [ram_width-1:0] nsmp = 0;
  reg [7:0] chanforscreen=0;
  reg autorearm=0;
  integer thecounter=0, timeoutcounter=0, serialdelaytimer=0,serialdelaytimerwait=0;
  
  reg [7:0] usb2counter;
  output reg do_usb=0;
  input usb_clk60;
  output reg [7:0] usb_dataio;
  input usb_txe_busy;
  output reg usb_wr, usb_siwu;
  reg usb_txe_not_busy;
  

  reg [5:0] screencolumndata [128];
  

  integer ioCount, ioCountToSend;
  reg[7:0] data[0:15];
  

  reg [7:0] numlockinbytes=16;
  integer lockinresult1;
  integer lockinresult2;
  reg [15:0] lockinnumtoshift = 0;
  integer chan2mean, chan3mean;
  reg calcmeans;
  
  initial begin
    state<=READ;
	 i2cstate<=READ;
	 myid<=200;
	 master_clock<=2'b00;
	 imthelast<=0;
	 rollingtrigger<=1;
	 triggerpoint<=(2**(ram_width-2));
	 downsample<=1;
	 serial_passthrough<=0;
	 usb_siwu<=1;
	 gainsw<=4'b0000;
	 oversamp<=4'b0011;
  	 debug1<=0; debug2<=0;
	 spare1<=0;
	 spare2<=0;
	 spare3<=0;
	 led4<=1;
	 led5<=0;
	 led6<=0;
	 led7<=0;
	 led8<=0;
  end
  

  always @(posedge clk) begin
	thecounter<=thecounter+1;
	usb_txe_not_busy <= ~usb_txe_busy;
	debug1 <= usb_txe_not_busy;
   if ( imthelast & thecounter[26]==1'b1 ) begin
		led1<=0;		led2<=0;		led3<=0;
	end




	else if (myid==0) begin	   
		led1<=1;		led2<=1;		led3<=1;
	end
	else if (myid==1) begin	   
		led1<=0;		led2<=1;		led3<=1;
	end
	else if (myid==2) begin	   
		led1<=1;		led2<=0;		led3<=1;
	end
	else if (myid==3) begin	   
		led1<=0;		led2<=0;		led3<=1;
	end
	else if (myid==4) begin	   
		led1<=1;		led2<=1;		led3<=0;
	end
	else begin		
		led1<=0;		led2<=0;		led3<=0;
	end
  end
  reg oldled1,oldled2,oldled3,oldled4,oldled5,oldled6,oldled7,oldled8;
  




















  
  always @(posedge clk) begin
    case (state)
	 
      READ: begin
		  get_ext_data<=0;
		  adcreset<=1;
		  txStart<=0;
		  getadcdata<=0;
		  bytesread<=0;
		  byteswanted<=0;
		  newcomdata<=0;
		  SPIsend<=0;
		  i2cgo=0;
		  usb_wr<=1;
        ioCount = 0;
        if (rxReady) begin
			 readdata = rxData;
          state = SOLVING;
        end
		  if (oldled1!=led1 || oldled2!=led2 || oldled3!=led3 || oldled4!=led4 || oldled5!=led5 || oldled6!=led6 || oldled7!=led7 || oldled8!=led8) begin
			 oldled1=led1; oldled2=led2; oldled3=led3; oldled4=led4;
			 oldled5=led5; oldled6=led6; oldled7=led7; oldled8=led8;

			 i2c_datacounttosend=2;
			 i2c_addr=8'h21;
			 i2cdata[0]=8'h12;
			 i2cdata[1][0]=led1; i2cdata[1][1]=led2; i2cdata[1][2]=led3; i2cdata[1][3]=led4;
			 i2cdata[1][4]=led5; i2cdata[1][5]=led6; i2cdata[1][6]=led7; i2cdata[1][7]=led8;
			 i2cdata[2]=0;
			 if (i2cstate==READ) begin
			   i2cdoread = 0;
				i2cgo=1;
			 end
		  end
      end
		
		READMORE: begin
			newcomdata=0;
			if (rxReady) begin
				extradata[bytesread] = rxData;
				comdata=rxData;
				newcomdata=1;
				bytesread = bytesread+1;
				if (bytesread>=byteswanted) state=SOLVING;
			end
		end

      SOLVING: begin
			if (readdata < 10) begin
				myid=readdata;
				if (readdata==0) begin
					master_clock=2'b00;
				end
				else master_clock=2'b01;
				comdata=(readdata+1);
				newcomdata=1;
				state=READ;
			end
			else if (readdata > 9 && readdata < 20) begin
				if (myid==(readdata-10)) begin

					serial_passthrough=0;
					timeoutcounter=0;
					state=WAITING;
				end
				else begin

					serial_passthrough=1;
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
			end
			else if (readdata > 19 && readdata < 30) begin
				if (myid==(readdata-20)) imthelast=1;
				else imthelast=0;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata > 29 && readdata < 40) begin
				if (myid==(readdata-30)) begin

					serial_passthrough=0;
				end
				else begin

					serial_passthrough=1;
					comdata=readdata;
					newcomdata=1;
				end
				state=READ;
			end
			
			else if (100==readdata) begin

				get_ext_data=1;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			
			else if (101==readdata) begin

				led5=1;
				rollingtrigger=1;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (102==readdata) begin

				led5=0;
				rollingtrigger=0;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			
			else if (readdata>109 && readdata<120) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					if (readdata==119) getadcadr<=17;
					else getadcadr<=(readdata-110);
					writesamp<=0;
					state=WAIT_ADC1;
				end
			end
			else if (readdata==120) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					nsamp=256*extradata[0]+extradata[1];
					if (nsamp>4095) nsamp=4095;
					state=READ;
				end
			end
			else if (readdata==121) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggerpoint=256*extradata[0]+extradata[1];
					if (triggerpoint>(2**ram_width)-16) triggerpoint=(2**ram_width)-16;
					else if (triggerpoint<4) triggerpoint=4;
					state=READ;
				end
			end
			else if (readdata==122) begin
				byteswanted=2;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					nsmp=256*extradata[0]+extradata[1];
					if (triggerpoint>(nsmp-5)) triggerpoint=nsmp/2;
					state=READ;
				end
			end
			else if (readdata==123) begin
				byteswanted=1;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					sendincrement=extradata[0];
					state=READ;
				end
			end
			else if (readdata==124) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]>30) extradata[0]=30;
					downsample=extradata[0];
					clockbitstowaitlockin = extradata[0]-2;
					state=READ;
				end
			end
			else if (readdata==125) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]>30) extradata[0]=30;
					clockbitstowait=extradata[0];
					state=READ;
				end
			end
			else if (readdata==126) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					chanforscreen=extradata[0];
					state=READ;
				end
			end
			
			else if (readdata==127) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					trigthresh=extradata[0];
					state=READ;
				end
			end
			else if (readdata==128) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggertype=extradata[0];
					state=READ;
				end
			end
			else if (readdata==129) begin
				byteswanted=2;
				comdata=readdata;	
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					triggertot=256*extradata[0]+extradata[1];
					state=READ;
				end
			end
			else if (readdata==130) begin
				comdata=readdata;	newcomdata=1;
				byteswanted=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						trigchannels[extradata[0]%4]=~trigchannels[extradata[0]%4];
					end
					state=READ;
				end
			end
			else if (readdata==131) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					SPIsenddata[15:8]=extradata[0];
					SPIsenddata[7:0]=extradata[1];
					SPIsenddata[15]=1'b0;
					SPIsend=1;
					state=SPIWAIT;
				end
			end
			else if (readdata==132) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=delaycounter;
					state=WRITE1;
				end
			end
			else if (readdata==133) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=carrycounter;
					state=WRITE1;
				end
			end
			else if (readdata==134) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						gainsw[extradata[0]%4]=~gainsw[extradata[0]%4];
					end

					i2c_datacounttosend=2;
					i2c_addr=8'h20;
					i2cdata[0]=8'h12;
					i2cdata[1][3:0]=gainsw;
					i2cdata[1][7:4]=oversamp;
					i2cdata[2]=0;
					if (i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end
			else if (readdata==135) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					serialdelaytimerwait=50*(256*extradata[0]+extradata[1]);
					state=READ;
				end
			end
			else if (readdata==136) begin
				byteswanted=6;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin



					i2c_datacounttosend=extradata[0];
					i2c_addr=extradata[1];
					i2cdata[0]=extradata[2];
					i2cdata[1]=extradata[3];
					i2cdata[2]=extradata[4];
					if ((extradata[5]==myid || extradata[5]==200) && i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end
			else if (137==readdata) begin

				do_usb=~do_usb;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==138) begin
				byteswanted=2;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					lockinnumtoshift = 256*extradata[0]+extradata[1];
					state=READ;
				end
			end
			else if (139==readdata) begin

				autorearm=~autorearm;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==140) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					trigthresh2 = extradata[0];
					state=READ;
				end
			end
			else if (readdata==141) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					if (extradata[0]/4 ==myid) begin
						oversamp[extradata[0]%4]=~oversamp[extradata[0]%4];
					end

					i2c_datacounttosend=2;
					i2c_addr=8'h20;
					i2cdata[0]=8'h12;
					i2cdata[1][3:0]=gainsw;
					i2cdata[1][7:4]=oversamp;
					i2cdata[2]=0;
					if (i2cstate==READ) begin
						i2cdoread = 0;
						i2cgo=1;
					end
					state=READ;
				end
			end			
			else if (readdata==142) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					data[0]=chip_id[7+8*0:8*0];
					data[1]=chip_id[7+8*1:8*1];
					data[2]=chip_id[7+8*2:8*2];
					data[3]=chip_id[7+8*3:8*3];
					data[4]=chip_id[7+8*4:8*4];
					data[5]=chip_id[7+8*5:8*5];
					data[6]=chip_id[7+8*6:8*6];
					data[7]=chip_id[7+8*7:8*7];
					ioCountToSend = 8;
					state=WRITE1;
				end
			end
			else if (143==readdata) begin

				highres=~highres;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (144==readdata) begin

				use_ext_trig=~use_ext_trig;
				comdata=readdata;
				newcomdata=1;
				state=READ;
			end
			else if (readdata==145) begin
				byteswanted=1;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					blockstosend = extradata[0];
					state=READ;
				end
			end
			else if (readdata==146) begin
				byteswanted=3;
				comdata=readdata;
				newcomdata=1;
				if (bytesread<byteswanted) state=READMORE;
				else begin
					i2c_addr=extradata[0];
					i2c_datacounttosend=2;
					i2cdata[0]=extradata[1];
					i2cdata[1]=0;
					if ((extradata[2]==myid || extradata[2]==200) && i2cstate==READ) begin
						i2cdoread = 1;
						i2cgo=1;

						ioCountToSend = 1;
						data[0] = i2c_datard;
						state=WRITE1;
					end
					else state=READ;
				end
			end
			else if (readdata==147) begin
				if (serial_passthrough) begin
					comdata=readdata;
					newcomdata=1;
					state=READ;
				end
				else begin
					ioCountToSend = 1;
					data[0]=5;
					state=WRITE1;
				end
			end
			
			else state=READ;
      end
		
		SPIWAIT: begin
			newcomdata<=0;

			if (SPIstate==3) begin 
				state=READ;
			end
		end
		
		WAITING: begin
			timeoutcounter=timeoutcounter+1;
			if (ext_data_ready) begin
				SendCount= 0;
				rdaddress = wraddress_triggerpoint - triggerpoint;
				rdaddress2 = rdaddress;
				thecounterbit=thecounter[clockbitstowait];
				thecounterbitlockin=thecounter[clockbitstowaitlockin];
				if (lockinnumtoshift>0) begin
					lockinresult1=0;
					lockinresult2=0;
					chan2mean=0;
					chan3mean=0;
					calcmeans=1;
					state=LOCKIN1;
				end
				else begin
					if (do_usb) state=WRITE_USB_EXT1;
					else state=WRITE_EXT1;
				end
			end
			if ( timeoutcounter > 100000000 ) begin
				state=READ;



			end
		end
		LOCKIN1: begin
			rden = 1;
			if ( (thecounter[clockbitstowaitlockin]!=thecounterbitlockin) ) begin
			case(SendCount[ram_width+1:ram_width])
				0: begin

					chan2mean = chan2mean + ram_output3;
					chan3mean = chan3mean + ram_output4;
				end
				1: begin
					if (calcmeans) begin
						calcmeans=0;
						chan2mean = chan2mean/4096;
						chan3mean = chan3mean/4096;
					end


					if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
						lockinresult2 = lockinresult2 + (ram_output3-chan2mean)*(ram_output4-chan3mean);
					end
				end
				2: begin

					if (SendCount[ram_width-1:0]>lockinnumtoshift && SendCount[ram_width-1:0]<(4096-lockinnumtoshift)) begin
						lockinresult1 = lockinresult1 + (ram_output3-chan2mean)*(ram_output4-chan3mean);
					end
				end
				3: begin
						
				end
			endcase			
			SendCount = SendCount + 1;
			rdaddress = rdaddress + 1;
			if (SendCount[ram_width+1:ram_width]==1) rdaddress2=rdaddress-lockinnumtoshift;
			else rdaddress2=rdaddress;
			state=LOCKIN2;
			end
		end
		LOCKIN2: begin	
			state=LOCKIN3;
		end
		LOCKIN3: begin
			if ( (thecounter[clockbitstowaitlockin]==thecounterbitlockin) ) begin
			if(SendCount[ram_width+1:0]==0) begin
				ioCount = 0;
				SendCount = 0;
				state=LOCKINWRITE1;
			end
			else begin
				state=LOCKIN1;
			end
			end
		end
		LOCKINWRITE1: begin
       if (!txBusy) begin
          if (ioCount==0) txData = lockinresult1[7+8*0:0+8*0];
          else if (ioCount==1) txData = lockinresult1[7+8*1:0+8*1];
          else if (ioCount==2) txData = lockinresult1[7+8*2:0+8*2];
          else if (ioCount==3) txData = lockinresult1[7+8*3:0+8*3];
          else if (ioCount==4) txData = lockinresult2[7+8*0:0+8*0];
          else if (ioCount==5) txData = lockinresult2[7+8*1:0+8*1];
          else if (ioCount==6) txData = lockinresult2[7+8*2:0+8*2];
          else if (ioCount==7) txData = lockinresult2[7+8*3:0+8*3];			 
			 else if (ioCount==8) txData = chan2mean[7+8*0:0+8*0];
          else if (ioCount==9) txData = chan2mean[7+8*1:0+8*1];
          else if (ioCount==10) txData = chan2mean[7+8*2:0+8*2];
          else if (ioCount==11) txData = chan2mean[7+8*3:0+8*3];
			 else if (ioCount==12) txData = chan3mean[7+8*0:0+8*0];
          else if (ioCount==13) txData = chan3mean[7+8*1:0+8*1];
          else if (ioCount==14) txData = chan3mean[7+8*2:0+8*2];
          else if (ioCount==15) txData = chan3mean[7+8*3:0+8*3];
			 else txData = 0;
          txStart = 1;
          state = LOCKINWRITE2;
        end
      end
      LOCKINWRITE2: begin
        txStart = 0;
        if (ioCount < numlockinbytes-1) begin
          ioCount = ioCount + 1;
          state = LOCKINWRITE1;
        end
		  else begin
				rdaddress = wraddress_triggerpoint - triggerpoint;
				rdaddress2 = rdaddress;
				thecounterbit=thecounter[clockbitstowait];
				if (do_usb) state=WRITE_USB_EXT1;
				else state=WRITE_EXT1;
        end
      end
		WRITE_EXT1: begin
			timeoutcounter=timeoutcounter+1;
			rden = 1;

			case(SendCount[ram_width+2:ram_width])
			0: txData<=ram_output1;
			1: txData<=ram_output2;
			2: txData<=ram_output3;
			3: txData<=ram_output4;
			4: txData<=digital_buffer1;
			endcase
			if( (!txBusy) && (thecounter[clockbitstowait]!=thecounterbit)) begin
				txStart<= 1;				
				SendCount = SendCount + (2**sendincrement);
				rdaddress = rdaddress + (2**sendincrement);
				rdaddress2 = rdaddress;
				if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
					SendCount[ram_width-1:0]=0;
					SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
					rdaddress = wraddress_triggerpoint - triggerpoint;
					rdaddress2 = rdaddress;
				end
				state=WRITE_EXT2;
			end
			if ( timeoutcounter > 100000000 ) begin
				rden = 0;
				state=READ;
			end
		end
		WRITE_EXT2: begin
			if( thecounter[clockbitstowait]==thecounterbit ) begin
				txStart<= 0;			
				if(SendCount[ram_width+2:ram_width]==blockstosend) begin
					rden = 0;
					if (autorearm) begin

						get_ext_data=1;
					end
					state=READ;
				end
				else begin					
					if(SendCount[4:0]==0 && serialdelaytimer<serialdelaytimerwait) begin
						serialdelaytimer=serialdelaytimer+1;
					end
					else begin
						if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin
							if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]);
							screenwren = 1;
						end
						serialdelaytimer=0;
						state=WRITE_EXT1;
					end
				end
			end
		end
		
		WRITE_USB_EXT1: begin
			if (usb_txe_not_busy) begin
				thecounterbit=thecounter[clockbitstowait];
				usb2counter<=0;
				state=WRITE_USB_EXT2;
			end
			debug2<=1;
			rden = 1;
		end
		WRITE_USB_EXT2: begin
			debug2<=0;
			usb2counter<=usb2counter+1;

			case(SendCount[ram_width+2:ram_width])
				0: usb_dataio<=ram_output1;
				1: usb_dataio<=ram_output2;
				2: usb_dataio<=ram_output3;
				3: usb_dataio<=ram_output4;
				4: usb_dataio<=digital_buffer1;
			endcase
			if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]!=thecounterbit)) begin
				SendCount = SendCount + (2**sendincrement);
				rdaddress = rdaddress + (2**sendincrement);
				rdaddress2 = rdaddress;
				if (nsmp>0 && SendCount[ram_width-1:0]>=nsmp) begin
					SendCount[ram_width-1:0]=0;
					SendCount[ram_width+2:ram_width] = (SendCount[ram_width+2:ram_width] + 1);
					rdaddress = wraddress_triggerpoint - triggerpoint;
					rdaddress2 = rdaddress;
				end
				state=WRITE_USB_EXT3;
			end
		end
		WRITE_USB_EXT3: begin
			usb_wr<= 0;
			usb2counter<=0;
			state=WRITE_USB_EXT4;
		end
		WRITE_USB_EXT4: begin
			usb2counter=usb2counter+1;
			if( (usb2counter>clockbitstowait) && (thecounter[clockbitstowait]==thecounterbit) ) begin
				usb_wr<= 1;	
				if(SendCount[ram_width+2:ram_width]==blockstosend) begin
					rden = 0;
					if (autorearm) begin

						get_ext_data=1;
					end
					state=WRITE_USB_EXT5;
				end
				else begin
					usb2counter=0;
					state=WRITE_USB_EXT1;
					if ( (rdaddress- wraddress_triggerpoint-64)>=0 && (rdaddress-wraddress_triggerpoint+64)<128 && (!SendCount[ram_width+2]) ) begin
						if (SendCount[ram_width+1:ram_width]==chanforscreen) screencolumndata[rdaddress - wraddress_triggerpoint - 64]=(63-txData[7:2]);
						screenwren = 1;
					end
				end
			end
		end
		WRITE_USB_EXT5: begin
			usb_siwu=0;
			usb2counter<=usb2counter+1;
			if( (usb2counter>8) ) begin
				state=READ;
				usb_siwu=1;
			end
		end

		WAIT_ADC1: begin
			newcomdata<=0;
			writeadc<=0;
			getadcdata<=1;

				state=WAIT_ADC2;

		end
		WAIT_ADC2: begin
			if (adcvalid) begin
				adctestout<=adcdata;
				writeadc<=1;
				getadcdata<=0;
				if (writesamp>=(nsamp-1)) begin
					writesamp<=0;
					writebyte<=0;
					thecounterbit=thecounter[clockbitstowait];
					state<=WRITE_BYTE1;
				end
				else begin
					writesamp=writesamp+1;
					state=WAIT_ADC1;
				end
			end
		end
		WRITE_BYTE1: begin
			newcomdata<=0;
			writeadc<=0;
			if(!txBusy && (thecounter[clockbitstowait]!=thecounterbit)) begin
				if (writebyte) txData=adcramdata[11:8];
				else txData=adcramdata[7:0];
				txStart=1;
				state=WRITE_BYTE2;
			end
		end
		WRITE_BYTE2: begin
			txStart=0;
			if (writebyte) writesamp=writesamp+1;
			writebyte = ~writebyte;
			if (writesamp>(nsamp-1)) state=READ;
			else state=WRITE_BYTE1;
		end
		

		WRITE1: begin
       newcomdata<=0;
       if (!txBusy) begin
          txData = data[ioCount];
          txStart = 1;
          state = WRITE2;
        end
      end
      WRITE2: begin
        txStart = 0;
        if (ioCount < ioCountToSend-1) begin
          ioCount = ioCount + 1;
          state = WRITE1;
        end else begin
          state = READ;
        end
      end
		



















		
    endcase
	 
  end  
  

  always @(posedge clk) begin
   case (i2cstate)
		READ: begin
			i2c_ena<=0;
			if (i2cgo) begin
				i2cstate=I2CWAIT;
			end
		end
		I2CWAIT: begin
			if (~i2c_busy) begin

				i2c_rw=0;

				i2c_datawr = i2cdata[0];
				i2c_datacount=1;
				i2cstate=I2CSEND1;
			end
		end
		I2CSEND1: begin
			i2c_ena = 1;
			if (i2c_datacount >= i2c_datacounttosend) begin
				i2cstate=READ;
			end
			else if (i2c_busy) begin
				i2c_datawr = i2cdata[i2c_datacount];
				if (i2cdoread) begin
					i2c_rw=1;
				end
				i2cstate=I2CSEND2;
			end
		end
		I2CSEND2: begin
			if (~i2c_busy) begin

				i2c_datacount = i2c_datacount+1;
				i2cstate=I2CSEND1;
			end
		end
	endcase
	end
  

	reg [5:0] columndata;
	reg [2:0] row;
	reg [6:0] column;
	reg [3:0] b;
	always @(posedge clk) begin
		if (screenaddr>1000) screenreset<=1;
		screenaddr = screenaddr + 1;
		row=7-screenaddr[9:7];
		column=screenaddr[6:0];
		


		
		columndata = screencolumndata[column];
		

		if (columndata>=8*(row+1)) screendata = 8'hff;
		else if (columndata>=8*row) begin
			screendata=8'h00; b=0;
			while (b<8) begin
				if (columndata[2:0]>b) screendata[b]=1;
				b=b+1;
			end
		end
		else screendata = 8'h00;
		


		

		if (row==7 & trigDebug) begin
			if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
		end
		if (row==6 & !trigDebug) begin
			if (myid>=screenaddr[6:1] && !screenaddr[0]) screendata = 8'hfa;
		end	
	end
	
endmodule