data/full_repos/permissive/108561032/memoriaintrucciones.v
data/verilator_xmls/2b76c1ce-e075-47f3-b952-661027d1f7da.xml
module memoriaintrucciones(direinstru,instru,clk,reset);

input [31:0] direinstru;
input clk;
input reset;

output wire [31:0] instru;


reg [31:0] registro_rom [31:0];


assign instru = registro_rom[direinstru];
 
always @ (*)
begin

if (reset == 1)
begin   
        registro_rom[0] = 32'b1010_1100_0010_0011__0000_0000_0000_0000;
        registro_rom[1] = 32'b1000_1100_0011_1111__0000_0000_0000_0000;
        registro_rom[2] = 32'b1111_1000_0000_0000__0000_0000_0000_0010;

        registro_rom[3] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
        registro_rom[4] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
        registro_rom[5] = 32'b1000_1100_0011_1111__0000_0000_0000_0000;
        registro_rom[6] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
        registro_rom[7] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
        registro_rom[8] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
        registro_rom[9] = 32'b1111_1000_0000_0000__0000_0000_0000_0010;
        

end
else
        begin
































end     
end 
 
endmodule
module memoriaintrucciones(direinstru,instru,clk,reset);


input [31:0] direinstru;
input clk;
input reset;

output wire [31:0] instru;


reg [31:0] registro_rom [31:0];


assign instru = registro_rom[direinstru];
 
always @ (*)
begin

if (reset == 1)
begin   
        registro_rom[0] = 32'b1010_1100_0010_0011__0000_0000_0000_0000;
        registro_rom[1] = 32'b1000_1100_0011_1111__0000_0000_0000_0000;
        registro_rom[2] = 32'b1111_1000_0000_0000__0000_0000_0000_0010;

        registro_rom[3] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
        registro_rom[4] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
        registro_rom[5] = 32'b1000_1100_0011_1111__0000_0000_0000_0000;
        registro_rom[6] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
        registro_rom[7] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
        registro_rom[8] = 32'b1111_1100_0000_0000__0000_0000_0000_0000;
        registro_rom[9] = 32'b1111_1000_0000_0000__0000_0000_0000_0010;
        

end
else
        begin
































end     
end 
 
endmodule