data/full_repos/permissive/169574047/generate/generate.srcs/sources_1/new/counter.v
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data/verilator_xmls/e96fb9a2-1429-4ccf-8715-e4df82481d53.xml
module counter(Q, clock, clear);


output [3:0] Q;
input clock, clear;

reg[3:0] Q;

always @(posedge clear or negedge clock)
begin
    if(clear)
        Q <= 4'd0;
    else
        Q <= Q + 1;
end

endmodule
module counter(Q, clock, clear);



output [3:0] Q;
input clock, clear;

reg[3:0] Q;

always @(posedge clear or negedge clock)
begin
    if(clear)
        Q <= 4'd0;
    else
        Q <= Q + 1;
end

endmodule