data/full_repos/permissive/105772342/hdl/conv_8to24.v
 line:86: before: "<="
data/verilator_xmls/da76061a-322b-4ef2-b584-b94bc8fdfa5f.xml
module CONV_8TO24(
input wire clk_in,
input wire reset_in,
input wire [7:0] data8_in,
input wire valid8_in,
output reg ready8_out,
output reg [23:0] data24_out,
output reg valid24_out,
input wire ready24_in
);







parameter [1:0]
  S_WAIT_MSB = 0,
  S_WAIT_MID = 1,
  S_WAIT_LSB = 2;

reg [1:0] state = S_WAIT_MSB;
reg [1:0] state_next;
reg [7:0] msb = 0;
reg [7:0] msb_next;
reg [7:0] mid = 0;
reg [7:0] mid_next;


  always @(posedge clk_in) begin
    if((reset_in == 1'b 1)) begin
      state <= S_WAIT_MSB;
      msb <= {8{1'b0}};
      mid <= {8{1'b0}};
    end
    else begin
      state <= state_next;
      msb <= msb_next;
      mid <= mid_next;
    end
  end


  always @(state or msb or mid or data8_in or valid8_in or ready24_in) begin
    state_next <= state;
    msb_next <= msb;
    mid_next <= mid;
    valid24_out <= 1'b 0;
    case(state)

    S_WAIT_LSB : begin
      ready8_out <= ready24_in;

      data24_out <= {msb,mid,data8_in};
      if((valid8_in == 1'b 1 && ready24_in == 1'b 1)) begin
        valid24_out <= 1'b 1;
        state_next <= S_WAIT_MSB;
      end

    end
    S_WAIT_MID : begin
      ready8_out <= 1'b 1;

      data24_out <= {24{1'bX}};
      if((valid8_in == 1'b 1)) begin
        mid_next <= data8_in;
        state_next <= S_WAIT_LSB;
      end

    end
    default : begin
      ready8_out <= 1'b 1;

      data24_out <= {24{1'bX}};
      if((valid8_in == 1'b 1)) begin
        msb_next <= data8_in;
        state_next <= S_WAIT_MID;
      end
    end
    endcase
  end


endmodule
module CONV_8TO24(
input wire clk_in,
input wire reset_in,
input wire [7:0] data8_in,
input wire valid8_in,
output reg ready8_out,
output reg [23:0] data24_out,
output reg valid24_out,
input wire ready24_in
);








parameter [1:0]
  S_WAIT_MSB = 0,
  S_WAIT_MID = 1,
  S_WAIT_LSB = 2;

reg [1:0] state = S_WAIT_MSB;
reg [1:0] state_next;
reg [7:0] msb = 0;
reg [7:0] msb_next;
reg [7:0] mid = 0;
reg [7:0] mid_next;


  always @(posedge clk_in) begin
    if((reset_in == 1'b 1)) begin
      state <= S_WAIT_MSB;
      msb <= {8{1'b0}};
      mid <= {8{1'b0}};
    end
    else begin
      state <= state_next;
      msb <= msb_next;
      mid <= mid_next;
    end
  end


  always @(state or msb or mid or data8_in or valid8_in or ready24_in) begin
    state_next <= state;
    msb_next <= msb;
    mid_next <= mid;
    valid24_out <= 1'b 0;
    case(state)

    S_WAIT_LSB : begin
      ready8_out <= ready24_in;

      data24_out <= {msb,mid,data8_in};
      if((valid8_in == 1'b 1 && ready24_in == 1'b 1)) begin
        valid24_out <= 1'b 1;
        state_next <= S_WAIT_MSB;
      end

    end
    S_WAIT_MID : begin
      ready8_out <= 1'b 1;

      data24_out <= {24{1'bX}};
      if((valid8_in == 1'b 1)) begin
        mid_next <= data8_in;
        state_next <= S_WAIT_LSB;
      end

    end
    default : begin
      ready8_out <= 1'b 1;

      data24_out <= {24{1'bX}};
      if((valid8_in == 1'b 1)) begin
        msb_next <= data8_in;
        state_next <= S_WAIT_MID;
      end
    end
    endcase
  end


endmodule