data/full_repos/permissive/177039499/pipeline-regs/EX-MEM.v
data/verilator_xmls/da21c789-3747-4a79-8bdf-f21320e7d3a4.xml
module rEXMEM(
	input wire        clk,
	input wire        reset,

	input wire        RegWriteIn,
    input wire        MemReadIn, MemWriteIn,
    input wire [31:0] ALUResultIn,
    input wire [31:0] storeValIn,
    input wire  [4:0] regWriteAddressIn,

    output reg        RegWrite,
    output reg        MemRead, MemWrite,
    output reg [31:0] ALUResult,
    output reg [31:0] storeVal,
    output reg  [4:0] regWriteAddress
);

	always @(posedge clk) begin
        if (reset) begin
            { RegWrite, MemRead, MemWrite, ALUResult, storeVal, regWriteAddress } <= 0;
        end else begin
            RegWrite 		<= RegWriteIn;
            MemRead 		<= MemReadIn;
            MemWrite 		<= MemWriteIn;
            ALUResult 		<= ALUResultIn;
            storeVal 		<= storeValIn;
            regWriteAddress <= regWriteAddressIn;
        end
    end

endmodule
module rEXMEM(
	input wire        clk,
	input wire        reset,

	input wire        RegWriteIn,
    input wire        MemReadIn, MemWriteIn,
    input wire [31:0] ALUResultIn,
    input wire [31:0] storeValIn,
    input wire  [4:0] regWriteAddressIn,

    output reg        RegWrite,
    output reg        MemRead, MemWrite,
    output reg [31:0] ALUResult,
    output reg [31:0] storeVal,
    output reg  [4:0] regWriteAddress
);


	always @(posedge clk) begin
        if (reset) begin
            { RegWrite, MemRead, MemWrite, ALUResult, storeVal, regWriteAddress } <= 0;
        end else begin
            RegWrite 		<= RegWriteIn;
            MemRead 		<= MemReadIn;
            MemWrite 		<= MemWriteIn;
            ALUResult 		<= ALUResultIn;
            storeVal 		<= storeValIn;
            regWriteAddress <= regWriteAddressIn;
        end
    end

endmodule