data/full_repos/permissive/193909872/Sim/testbench.v
 line:16: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/193909872/Sim/testbench.v:10: Unsupported: Ignoring delay on this delayed statement.\n   #5 clk = ~clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/193909872/Sim/testbench.v:16: syntax error, unexpected \'@\'\n  repeat (10) @(posedge clk);\n              ^\n%Error: data/full_repos/permissive/193909872/Sim/testbench.v:18: syntax error, unexpected \'@\'\n  repeat (600) @(posedge clk);\n               ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module blram(clk, rst, i_we, i_addr, i_ram_data_in, o_ram_data_out);

parameter SIZE = 10, DEPTH = 1024;

input clk;
input rst;
input i_we;
input [SIZE-1:0] i_addr;
input [31:0] i_ram_data_in;
output reg [31:0] o_ram_data_out;

reg [31:0] memory[0:DEPTH-1];

always @(posedge clk) begin
  o_ram_data_out <= #1 memory[i_addr[SIZE-1:0]];
  if (i_we)
		memory[i_addr[SIZE-1:0]] <= #1 i_ram_data_in;
end 

initial begin




end

endmodule
module blram(clk, rst, i_we, i_addr, i_ram_data_in, o_ram_data_out);


parameter SIZE = 10, DEPTH = 1024;

input clk;
input rst;
input i_we;
input [SIZE-1:0] i_addr;
input [31:0] i_ram_data_in;
output reg [31:0] o_ram_data_out;

reg [31:0] memory[0:DEPTH-1];

always @(posedge clk) begin
  o_ram_data_out <= #1 memory[i_addr[SIZE-1:0]];
  if (i_we)
		memory[i_addr[SIZE-1:0]] <= #1 i_ram_data_in;
end 

initial begin




end

endmodule