data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/vga.v
None: at end of input
1: b'%Warning-LITENDIAN: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/vga.v:21: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output reg [WIDTH - 1:0] hdata,\n               ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/vga.v:22: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output reg [WIDTH - 1:0] vdata,\n               ^\n%Warning-UNSIGNED: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/vga.v:54: Comparison is constant due to unsigned arithmetic\n                                                                                               : ... In instance vga\nassign hsync = ((hdata >= HFP) && (hdata < HSP)) ? HSPP : !HSPP;\n                       ^~\n%Warning-UNSIGNED: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/vga.v:54: Comparison is constant due to unsigned arithmetic\n                                                                                               : ... In instance vga\nassign hsync = ((hdata >= HFP) && (hdata < HSP)) ? HSPP : !HSPP;\n                                         ^\n%Warning-UNSIGNED: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/vga.v:55: Comparison is constant due to unsigned arithmetic\n                                                                                               : ... In instance vga\nassign vsync = ((vdata >= VFP) && (vdata < VSP)) ? VSPP : !VSPP;\n                       ^~\n%Warning-UNSIGNED: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/vga.v:55: Comparison is constant due to unsigned arithmetic\n                                                                                               : ... In instance vga\nassign vsync = ((vdata >= VFP) && (vdata < VSP)) ? VSPP : !VSPP;\n                                         ^\n%Warning-UNSIGNED: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/vga.v:56: Comparison is constant due to unsigned arithmetic\n                                                                                               : ... In instance vga\nassign data_enable = ((hdata < HSIZE) & (vdata < VSIZE));\n                             ^\n%Warning-UNSIGNED: data/full_repos/permissive/155070420/thinpad_top.srcs/sources_1/new/vga.v:56: Comparison is constant due to unsigned arithmetic\n                                                                                               : ... In instance vga\nassign data_enable = ((hdata < HSIZE) & (vdata < VSIZE));\n                                               ^\n%Error: Exiting due to 8 warning(s)\n'
module vga
#(parameter WIDTH = 0, HSIZE = 0, HFP = 0, HSP = 0, HMAX = 0, VSIZE = 0, VFP = 0, VSP = 0, VMAX = 0, HSPP = 0, VSPP = 0)
(
    input wire clk,
    output wire hsync,
    output wire vsync,
    output reg [WIDTH - 1:0] hdata,
    output reg [WIDTH - 1:0] vdata,
    output wire data_enable
);


initial begin
    hdata <= 0;
    vdata <= 0;
end


always @ (posedge clk)
begin
    if (hdata == (HMAX - 1))
        hdata <= 0;
    else
        hdata <= hdata + 1;
end


always @ (posedge clk)
begin
    if (hdata == (HMAX - 1)) 
    begin
        if (vdata == (VMAX - 1))
            vdata <= 0;
        else
            vdata <= vdata + 1;
    end
end


assign hsync = ((hdata >= HFP) && (hdata < HSP)) ? HSPP : !HSPP;
assign vsync = ((vdata >= VFP) && (vdata < VSP)) ? VSPP : !VSPP;
assign data_enable = ((hdata < HSIZE) & (vdata < VSIZE));

endmodule
module vga
#(parameter WIDTH = 0, HSIZE = 0, HFP = 0, HSP = 0, HMAX = 0, VSIZE = 0, VFP = 0, VSP = 0, VMAX = 0, HSPP = 0, VSPP = 0)
(
    input wire clk,
    output wire hsync,
    output wire vsync,
    output reg [WIDTH - 1:0] hdata,
    output reg [WIDTH - 1:0] vdata,
    output wire data_enable
);



initial begin
    hdata <= 0;
    vdata <= 0;
end


always @ (posedge clk)
begin
    if (hdata == (HMAX - 1))
        hdata <= 0;
    else
        hdata <= hdata + 1;
end


always @ (posedge clk)
begin
    if (hdata == (HMAX - 1)) 
    begin
        if (vdata == (VMAX - 1))
            vdata <= 0;
        else
            vdata <= vdata + 1;
    end
end


assign hsync = ((hdata >= HFP) && (hdata < HSP)) ? HSPP : !HSPP;
assign vsync = ((vdata >= VFP) && (vdata < VSP)) ? VSPP : !VSPP;
assign data_enable = ((hdata < HSIZE) & (vdata < VSIZE));

endmodule