data/full_repos/permissive/106408053/verilog/sync.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/sync.v:71: Unsupported: Ignoring delay on this delayed statement.\nalways @* begin #1; next_testcount = testcount+1\'b1; end\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/sync.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-IMPLICIT: data/full_repos/permissive/106408053/verilog/sync.v:91: Signal definition not found, creating implicitly: \'sampled_intTestMode\'\nwire [31:0] itm_indata = (sampled_intTestMode) ? itm_count : sync_indata;\n                          ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/106408053/verilog/sync.v:115: Signal definition not found, creating implicitly: \'sampled_numberScheme\'\nwire [31:0] demux_indata = (sampled_numberScheme) ? {demuxH_indata[15:0],demuxH_indata[31:16]} : demuxL_indata;\n                            ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:52: Cannot find file containing module: \'dly_signal\'\ndly_signal sampled_intTestMode_reg (clock, intTestMode, sampled_intTestMode);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/dly_signal\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/dly_signal.v\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/dly_signal.sv\n             dly_signal\n             dly_signal.v\n             dly_signal.sv\n             obj_dir/dly_signal\n             obj_dir/dly_signal.v\n             obj_dir/dly_signal.sv\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:53: Cannot find file containing module: \'dly_signal\'\ndly_signal sampled_numberScheme_reg (clock, numberScheme, sampled_numberScheme);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:60: Cannot find file containing module: \'ddr_inbuf\'\nddr_inbuf inbuf (clock, indata, sync_indata, sync_indata180);\n^~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:87: Cannot find file containing module: \'dly_signal\'\ndly_signal #(32) sampled_testcount_reg (clock, {testcount3,testcount2,testcount1,testcount}, itm_count);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:102: Cannot find file containing module: \'demux\'\ndemux demuxL (\n^~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:109: Cannot find file containing module: \'demux\'\ndemux demuxH (\n^~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sync.v:122: Cannot find file containing module: \'filter\'\nfilter filter (\n^~~~~~\n%Error: Exiting due to 7 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sync (clock, indata, intTestMode, numberScheme, filter_mode, demux_mode, falling_edge, outdata);

input clock;
input [31:0] indata;
input intTestMode;
input numberScheme;
input filter_mode;
input demux_mode;
input falling_edge;
output [31:0] outdata;





dly_signal sampled_intTestMode_reg (clock, intTestMode, sampled_intTestMode);
dly_signal sampled_numberScheme_reg (clock, numberScheme, sampled_numberScheme);





wire [31:0] sync_indata, sync_indata180;
ddr_inbuf inbuf (clock, indata, sync_indata, sync_indata180);
 






reg [7:0] testcount, next_testcount;
initial testcount=0;
always @ (posedge clock) testcount = next_testcount;
always @* begin #1; next_testcount = testcount+1'b1; end

wire [7:0] testcount1 = {
  testcount[0],testcount[1],testcount[2],testcount[3],
  testcount[4],testcount[5],testcount[6],testcount[7]};

wire [7:0] testcount2 = {
  testcount[3],testcount[2],testcount[1],testcount[0],
  testcount[4],testcount[5],testcount[6],testcount[7]};

wire [7:0] testcount3 = {
  testcount[3],testcount[2],testcount[1],testcount[0],
  testcount[7],testcount[6],testcount[5],testcount[4]};

wire [31:0] itm_count;
(* equivalent_register_removal = "no" *)
dly_signal #(32) sampled_testcount_reg (clock, {testcount3,testcount2,testcount1,testcount}, itm_count);



wire [31:0] itm_indata = (sampled_intTestMode) ? itm_count : sync_indata;
wire [31:0] itm_indata180 = (sampled_intTestMode) ? ~itm_count : sync_indata180;








wire [31:0] demuxL_indata; 
demux demuxL (
  .clock(clock),
  .indata(itm_indata[15:0]), 
  .indata180(itm_indata180[15:0]), 
  .outdata(demuxL_indata));

wire [31:0] demuxH_indata; 
demux demuxH (
  .clock(clock),
  .indata(itm_indata[31:16]), 
  .indata180(itm_indata180[31:16]), 
  .outdata(demuxH_indata));

wire [31:0] demux_indata = (sampled_numberScheme) ? {demuxH_indata[15:0],demuxH_indata[31:16]} : demuxL_indata;





wire [31:0] filtered_indata; 
filter filter (
  .clock(clock), 
  .indata(itm_indata),
  .indata180(itm_indata180),
  .outdata(filtered_indata));





reg [1:0] select, next_select;
reg [31:0] selectdata, next_selectdata;
reg [31:0] outdata;

always @(posedge clock) 
begin
  select = next_select;
  selectdata = next_selectdata;
end

always @*
begin
  #1;
  if (demux_mode)
    next_select = 2'b10;
  else if (filter_mode)
    next_select = 2'b11;
  else next_select = {1'b0,falling_edge};


  case (select) 
    2'b00 : next_selectdata = itm_indata;
    2'b01 : next_selectdata = itm_indata180;
    2'b10 : next_selectdata = demux_indata;
    2'b11 : next_selectdata = filtered_indata;
  endcase




  outdata = (sampled_numberScheme) ? {selectdata[15:0],selectdata[31:16]} : selectdata;
end
endmodule
module sync (clock, indata, intTestMode, numberScheme, filter_mode, demux_mode, falling_edge, outdata);


input clock;
input [31:0] indata;
input intTestMode;
input numberScheme;
input filter_mode;
input demux_mode;
input falling_edge;
output [31:0] outdata;





dly_signal sampled_intTestMode_reg (clock, intTestMode, sampled_intTestMode);
dly_signal sampled_numberScheme_reg (clock, numberScheme, sampled_numberScheme);





wire [31:0] sync_indata, sync_indata180;
ddr_inbuf inbuf (clock, indata, sync_indata, sync_indata180);
 






reg [7:0] testcount, next_testcount;
initial testcount=0;
always @ (posedge clock) testcount = next_testcount;
always @* begin #1; next_testcount = testcount+1'b1; end

wire [7:0] testcount1 = {
  testcount[0],testcount[1],testcount[2],testcount[3],
  testcount[4],testcount[5],testcount[6],testcount[7]};

wire [7:0] testcount2 = {
  testcount[3],testcount[2],testcount[1],testcount[0],
  testcount[4],testcount[5],testcount[6],testcount[7]};

wire [7:0] testcount3 = {
  testcount[3],testcount[2],testcount[1],testcount[0],
  testcount[7],testcount[6],testcount[5],testcount[4]};

wire [31:0] itm_count;
(* equivalent_register_removal = "no" *)
dly_signal #(32) sampled_testcount_reg (clock, {testcount3,testcount2,testcount1,testcount}, itm_count);



wire [31:0] itm_indata = (sampled_intTestMode) ? itm_count : sync_indata;
wire [31:0] itm_indata180 = (sampled_intTestMode) ? ~itm_count : sync_indata180;








wire [31:0] demuxL_indata; 
demux demuxL (
  .clock(clock),
  .indata(itm_indata[15:0]), 
  .indata180(itm_indata180[15:0]), 
  .outdata(demuxL_indata));

wire [31:0] demuxH_indata; 
demux demuxH (
  .clock(clock),
  .indata(itm_indata[31:16]), 
  .indata180(itm_indata180[31:16]), 
  .outdata(demuxH_indata));

wire [31:0] demux_indata = (sampled_numberScheme) ? {demuxH_indata[15:0],demuxH_indata[31:16]} : demuxL_indata;





wire [31:0] filtered_indata; 
filter filter (
  .clock(clock), 
  .indata(itm_indata),
  .indata180(itm_indata180),
  .outdata(filtered_indata));





reg [1:0] select, next_select;
reg [31:0] selectdata, next_selectdata;
reg [31:0] outdata;

always @(posedge clock) 
begin
  select = next_select;
  selectdata = next_selectdata;
end

always @*
begin
  #1;
  if (demux_mode)
    next_select = 2'b10;
  else if (filter_mode)
    next_select = 2'b11;
  else next_select = {1'b0,falling_edge};


  case (select) 
    2'b00 : next_selectdata = itm_indata;
    2'b01 : next_selectdata = itm_indata180;
    2'b10 : next_selectdata = demux_indata;
    2'b11 : next_selectdata = filtered_indata;
  endcase




  outdata = (sampled_numberScheme) ? {selectdata[15:0],selectdata[31:16]} : selectdata;
end
endmodule