data/full_repos/permissive/138580357/ex/index.v
1: b'%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:59: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'year\' generates 8 bits.\n                                                                  : ... In instance index\n          if ((2100+year)%4==0&&(2100+year)%100!=0||(2100+year)%400==0)  \n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:59: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'year\' generates 8 bits.\n                                                                  : ... In instance index\n          if ((2100+year)%4==0&&(2100+year)%100!=0||(2100+year)%400==0)  \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:59: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s VARREF \'year\' generates 8 bits.\n                                                                  : ... In instance index\n          if ((2100+year)%4==0&&(2100+year)%100!=0||(2100+year)%400==0)  \n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:151: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q1 = day%10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:152: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q2 = day/10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:153: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q3 = month%10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:154: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q4 = month/10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:155: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q5 = year%10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:156: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q6 = year/10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:160: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q1 = second%10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:161: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q2 = second/10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:162: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q3 = minutes%10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:163: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q4 = minutes/10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:164: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q5 = hour%10;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/138580357/ex/index.v:165: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                   : ... In instance index\n              q6 = hour/10;\n                 ^\n%Error: Exiting due to 15 warning(s)\n'
module index(clk,sw0,sw1,key0,key1,key2,key3,hex0,hex1,hex2,hex3,hex4,hex5,clock);
input clk,sw0,sw1,key0,key1,key2,key3;
output hex0,hex1,hex2,hex3,hex4,hex5;
wire [3:0] hex0,hex1,hex2,hex3,hex4,hex5;
output  reg clock;
reg [7:0] year,month,day,hour,minutes,second;
reg [3:0] q1,q2,q3,q4,q5,q6;



always @(posedge clk or negedge key0 )
begin 
  if (~key0)
	  begin
		if(sw1)
			begin
				year = 16;
				month = 1;
				day = 1 ;
		   end
		else
			begin
		
					hour = 0;
					minutes = 0;
					second = 0;
			end
		  
	  end
  else
    begin

      if (sw0)
         begin
          second = second + 1;
        end

      if(second == 60)
        begin
          second = 0;
          minutes = minutes+1;
        end

      if (minutes==60)
        begin
          minutes = 0;
          hour = hour+1;
        end

      if (hour==24)
        begin
          hour = 0;
          day = day+1;
          clock = 1;
        end

      if (month==2) 
        begin
          if ((2100+year)%4==0&&(2100+year)%100!=0||(2100+year)%400==0)
		        begin
                if (day==30) 
			            begin
                    month = 3;
                    day = 1;
                  end
            end

          else
       
            begin
                if (day==29) 
			            begin
                    month = 3;
                    day = 1;
                  end
            end
    
        end

      if(month==1||month==3||month==5||month == 7||month==8||month==10||month==12)
          begin
            if (day==32)
		          begin
                month = month+1;
                day = 1;
              end
          end

      if (month == 4||month==6||month==9||month ==11)
          begin
            if (day==31)
		          begin
                month=month+1;
                day = 1;
              end
          end
      if (month==13)
          begin
            month=1;
            year = year +1;
          end
    
      if (second!=0) 
          begin
            clock = 0;
          end
      if(!key1)
          begin
            if (sw1&&sw0==0) 
              begin
                day = day +  1;
              end
            else if (sw1==0&&sw0==0) 
              begin
                
					 second = second + 1;
              end
          end

      if(!key2)
          begin 
            
              if (sw1&&sw0==0) 
              begin
               month = month +1;
              end
            else if (sw1==0&&sw0==0) 
              begin
                
					 minutes = minutes + 1;
              end
             
          end
      if(!key3)
          begin
            if (sw1&&sw0==0)
              begin
					 year = year + 1;
              end
            else if(sw1==0&&sw0==0)
              begin
                 hour = hour + 1;

              end
          end

      
      if (sw1) 
          begin

              q1 = day%10;
              q2 = day/10;
              q3 = month%10;
              q4 = month/10;
              q5 = year%10;
              q6 = year/10;
          end 
      else 
          begin
              q1 = second%10;
              q2 = second/10;
              q3 = minutes%10;
              q4 = minutes/10;
              q5 = hour%10;
              q6 = hour/10;
          end 

    end

end

assign hex0 = q1;
assign hex1 = q2;
assign hex2 = q3;
assign hex3 = q4;
assign hex4 = q5;
assign hex5 = q6;

endmodule
module index(clk,sw0,sw1,key0,key1,key2,key3,hex0,hex1,hex2,hex3,hex4,hex5,clock);

input clk,sw0,sw1,key0,key1,key2,key3;
output hex0,hex1,hex2,hex3,hex4,hex5;
wire [3:0] hex0,hex1,hex2,hex3,hex4,hex5;
output  reg clock;
reg [7:0] year,month,day,hour,minutes,second;
reg [3:0] q1,q2,q3,q4,q5,q6;



always @(posedge clk or negedge key0 )
begin 
  if (~key0)
	  begin
		if(sw1)
			begin
				year = 16;
				month = 1;
				day = 1 ;
		   end
		else
			begin
		
					hour = 0;
					minutes = 0;
					second = 0;
			end
		  
	  end
  else
    begin

      if (sw0)
         begin
          second = second + 1;
        end

      if(second == 60)
        begin
          second = 0;
          minutes = minutes+1;
        end

      if (minutes==60)
        begin
          minutes = 0;
          hour = hour+1;
        end

      if (hour==24)
        begin
          hour = 0;
          day = day+1;
          clock = 1;
        end

      if (month==2) 
        begin
          if ((2100+year)%4==0&&(2100+year)%100!=0||(2100+year)%400==0)
		        begin
                if (day==30) 
			            begin
                    month = 3;
                    day = 1;
                  end
            end

          else
       
            begin
                if (day==29) 
			            begin
                    month = 3;
                    day = 1;
                  end
            end
    
        end

      if(month==1||month==3||month==5||month == 7||month==8||month==10||month==12)
          begin
            if (day==32)
		          begin
                month = month+1;
                day = 1;
              end
          end

      if (month == 4||month==6||month==9||month ==11)
          begin
            if (day==31)
		          begin
                month=month+1;
                day = 1;
              end
          end
      if (month==13)
          begin
            month=1;
            year = year +1;
          end
    
      if (second!=0) 
          begin
            clock = 0;
          end
      if(!key1)
          begin
            if (sw1&&sw0==0) 
              begin
                day = day +  1;
              end
            else if (sw1==0&&sw0==0) 
              begin
                
					 second = second + 1;
              end
          end

      if(!key2)
          begin 
            
              if (sw1&&sw0==0) 
              begin
               month = month +1;
              end
            else if (sw1==0&&sw0==0) 
              begin
                
					 minutes = minutes + 1;
              end
             
          end
      if(!key3)
          begin
            if (sw1&&sw0==0)
              begin
					 year = year + 1;
              end
            else if(sw1==0&&sw0==0)
              begin
                 hour = hour + 1;

              end
          end

      
      if (sw1) 
          begin

              q1 = day%10;
              q2 = day/10;
              q3 = month%10;
              q4 = month/10;
              q5 = year%10;
              q6 = year/10;
          end 
      else 
          begin
              q1 = second%10;
              q2 = second/10;
              q3 = minutes%10;
              q4 = minutes/10;
              q5 = hour%10;
              q6 = hour/10;
          end 

    end

end

assign hex0 = q1;
assign hex1 = q2;
assign hex2 = q3;
assign hex3 = q4;
assign hex4 = q5;
assign hex5 = q6;

endmodule