data/full_repos/permissive/143278/ivltests/pr2834340.v
 line:6: before: "pd1"
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr2834340.v:6: syntax error, unexpected (-for-strength, expecting \'(\'\npulldown (weak0) pd1 (r1a,r1c,r1o);\n          ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2834340.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2834340.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/pr2834340.v:46: Unsupported: Verilog 1995 gate primitive: tranif1\ntranif1 t1 (ARM,NC,coil_off);\n        ^~\n%Error: data/full_repos/permissive/143278/ivltests/pr2834340.v:47: Unsupported: Verilog 1995 gate primitive: tranif1\ntranif1 t2 (ARM,NO,coil_on);\n        ^~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module SPDT_RELAY (COIL1, COIL2, ARM, NC, NO);
inout COIL1, COIL2, ARM, NC, NO;
wire coil = ((COIL1===1'b1) && (COIL2===1'b0)) || ((COIL1===1'b0) && (COIL2===1'b1));

wire #1 dly_coil = coil;
wire coil_on = coil & dly_coil;
wire coil_off = !coil & !dly_coil;




tranif1 t1 (ARM,NC,coil_off);
tranif1 t2 (ARM,NO,coil_on);
endmodule
module SPDT_RELAY (COIL1, COIL2, ARM, NC, NO);

inout COIL1, COIL2, ARM, NC, NO;
wire coil = ((COIL1===1'b1) && (COIL2===1'b0)) || ((COIL1===1'b0) && (COIL2===1'b1));

wire #1 dly_coil = coil;
wire coil_on = coil & dly_coil;
wire coil_off = !coil & !dly_coil;




tranif1 t1 (ARM,NC,coil_off);
tranif1 t2 (ARM,NO,coil_on);
endmodule