data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/TmpImage_Test_bench.v
 line:51: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/TmpImage_Test_bench.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/TmpImage_Test_bench.v:48: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/TmpImage_Test_bench.v:50: Unsupported: Ignoring delay on this delayed statement.\n     #1000\n     ^\n%Error: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/TmpImage_Test_bench.v:32: Cannot find file containing module: \'TempImgCreator\'\n    TempImgCreator uut(.CLK(clk),\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new,data/full_repos/permissive/123043192/TempImgCreator\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new,data/full_repos/permissive/123043192/TempImgCreator.v\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new,data/full_repos/permissive/123043192/TempImgCreator.sv\n             TempImgCreator\n             TempImgCreator.v\n             TempImgCreator.sv\n             obj_dir/TempImgCreator\n             obj_dir/TempImgCreator.v\n             obj_dir/TempImgCreator.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TmpImage_Test_bench(

    );
    
    reg clk;
    wire clkout;
    wire[7:0] scaler;
    reg rst;
    
    TempImgCreator uut(.CLK(clk),
                         .CLKOUT(clkout),
                         .dataOut(scaler),
                         .reset(rst));
                         
                         
     initial begin
        clk = 0;
        forever begin
        #1 clk = ~clk;
        end
     end
     
     initial begin
     $display("Testing data creator");
     rst = 1;
     #10;
     rst = 0;
     #1000
     $finish;
     end
    
endmodule
module TmpImage_Test_bench(

    );

    
    reg clk;
    wire clkout;
    wire[7:0] scaler;
    reg rst;
    
    TempImgCreator uut(.CLK(clk),
                         .CLKOUT(clkout),
                         .dataOut(scaler),
                         .reset(rst));
                         
                         
     initial begin
        clk = 0;
        forever begin
        #1 clk = ~clk;
        end
     end
     
     initial begin
     $display("Testing data creator");
     rst = 1;
     #10;
     rst = 0;
     #1000
     $finish;
     end
    
endmodule