data/full_repos/permissive/201488448/1_verilog/22_shift8.v
1: b"%Error: data/full_repos/permissive/201488448/1_verilog/22_shift8.v:11: Cannot find file containing module: 'my_dff8'\n my_dff8 d1 ( clk, d, o1 );\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/my_dff8\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/my_dff8.v\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/my_dff8.sv\n             my_dff8\n             my_dff8.v\n             my_dff8.sv\n             obj_dir/my_dff8\n             obj_dir/my_dff8.v\n             obj_dir/my_dff8.sv\n%Error: data/full_repos/permissive/201488448/1_verilog/22_shift8.v:12: Cannot find file containing module: 'my_dff8'\n my_dff8 d2 ( clk, o1, o2 );\n ^~~~~~~\n%Error: data/full_repos/permissive/201488448/1_verilog/22_shift8.v:13: Cannot find file containing module: 'my_dff8'\n my_dff8 d3 ( clk, o2, o3 );\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module (
	input clk,
	input [7:0] d,
	input [1:0] sel,
	output reg [7:0] q
);

	wire [7:0] o1, o2, o3;
	

	my_dff8 d1 ( clk, d, o1 );
	my_dff8 d2 ( clk, o1, o2 );
	my_dff8 d3 ( clk, o2, o3 );


	always @(*)
		case(sel)
			2'h0: q = d;
			2'h1: q = o1;
			2'h2: q = o2;
			2'h3: q = o3;
		endcase

endmodule
module top_module (
	input clk,
	input [7:0] d,
	input [1:0] sel,
	output reg [7:0] q
);


	wire [7:0] o1, o2, o3;
	

	my_dff8 d1 ( clk, d, o1 );
	my_dff8 d2 ( clk, o1, o2 );
	my_dff8 d3 ( clk, o2, o3 );


	always @(*)
		case(sel)
			2'h0: q = d;
			2'h1: q = o1;
			2'h2: q = o2;
			2'h3: q = o3;
		endcase

endmodule