data/full_repos/permissive/213361049/instructions_tb.v
1: b'%Error: data/full_repos/permissive/213361049/instructions_tb.v:16: Unsupported or unknown PLI call: $monitor\n$monitor("i:%b class:%b CS:%b s0:%d s1:%d s2:%d ML:%d Aluout:%d",i,class3,cs,os0,os1,os2,ml,aluout);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/213361049/instructions_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/213361049/instructions_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/instructions_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/instructions_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module p2_tb();
wire [1:0]class3;
wire [4:0]cs;
wire [31:0]os0;
wire [31:0]os1;
wire [31:0]os2;
wire [31:0]ml;
wire [31:0]aluout;
reg [31:0]i;
reg [31:0]s0;
reg [31:0]s1;
reg [31:0]s2;
instructions my_gate(i,s0,s1,s2,class3,cs,os0,os1,os2,ml,aluout);
initial
begin
$monitor("i:%b class:%b CS:%b s0:%d s1:%d s2:%d ML:%d Aluout:%d",i,class3,cs,os0,os1,os2,ml,aluout);

i = 32'b00000010001100101000000000100000;
s0 = 32'b00000000000000000000000000000100;
s1 = 32'b00000000000000000000000000001010;
s2 = 32'b00000000000000000000000000010100;
#5
i = 32'b10001110001100000000000000100000;
s0 = 32'b00000000000000000000000000000100;
s1 = 32'b00000000000000000000000000001010;
s2 = 32'b00000000000000000000000000010100;
#5
i = 32'b10101110001100000000000000100000;
s0 = 32'b00000000000000000000000000000100;
s1 = 32'b00000000000000000000000000001010;
s2 = 32'b00000000000000000000000000010100;
#5
i = 32'b00010010000100010000000011001000;
s0 = 32'b00000000000000000000000000000100;
s1 = 32'b00000000000000000000000000001010;
s2 = 32'b00000000000000000000000000010100;
#5
i = 32'b00001000000000000000001111101000;
s0 = 32'b00000000000000000000000000000100;
s1 = 32'b00000000000000000000000000001010;
s2 = 32'b00000000000000000000000000010100;
end
endmodule
module p2_tb();

wire [1:0]class3;
wire [4:0]cs;
wire [31:0]os0;
wire [31:0]os1;
wire [31:0]os2;
wire [31:0]ml;
wire [31:0]aluout;
reg [31:0]i;
reg [31:0]s0;
reg [31:0]s1;
reg [31:0]s2;
instructions my_gate(i,s0,s1,s2,class3,cs,os0,os1,os2,ml,aluout);
initial
begin
$monitor("i:%b class:%b CS:%b s0:%d s1:%d s2:%d ML:%d Aluout:%d",i,class3,cs,os0,os1,os2,ml,aluout);

i = 32'b00000010001100101000000000100000;
s0 = 32'b00000000000000000000000000000100;
s1 = 32'b00000000000000000000000000001010;
s2 = 32'b00000000000000000000000000010100;
#5
i = 32'b10001110001100000000000000100000;
s0 = 32'b00000000000000000000000000000100;
s1 = 32'b00000000000000000000000000001010;
s2 = 32'b00000000000000000000000000010100;
#5
i = 32'b10101110001100000000000000100000;
s0 = 32'b00000000000000000000000000000100;
s1 = 32'b00000000000000000000000000001010;
s2 = 32'b00000000000000000000000000010100;
#5
i = 32'b00010010000100010000000011001000;
s0 = 32'b00000000000000000000000000000100;
s1 = 32'b00000000000000000000000000001010;
s2 = 32'b00000000000000000000000000010100;
#5
i = 32'b00001000000000000000001111101000;
s0 = 32'b00000000000000000000000000000100;
s1 = 32'b00000000000000000000000000001010;
s2 = 32'b00000000000000000000000000010100;
end
endmodule