data/full_repos/permissive/121770408/Multi-Slave/Master.v
 line:23: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/121770408/Multi-Slave/Master.v:14: Unsupported: Ignoring delay on this delayed statement.\n#10 ss1 = 0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121770408/Multi-Slave/Master.v:17: Unsupported: Ignoring delay on this delayed statement.\n#100 ss2 = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/121770408/Multi-Slave/Master.v:30: Unsupported: Ignoring delay on this delayed statement.\n#2 scl = !scl;\n^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Master(qw,scl,mosi,miso,ss1,ss2,sel);
input qw;
output reg scl;
input miso;
output reg [0:0]mosi;
output reg ss1;
output reg ss2;
output reg [1:0] sel;
reg [16:0]xx;
initial begin
scl = 0;
ss1 = 1;
ss2 = 1;
#10 ss1 = 0;
sel = 0;
xx = 17'b011101001_00011001;
#100 ss2 = 0;
xx = 17'b010101011_00011001;
ss1 = 1;
sel = 1;
end
always @(negedge ss1 or negedge ss2)
slock ;
always @(posedge scl)begin
mosi = xx[16];
xx = xx<<1;
end
task slock;
repeat (38)
#2 scl = !scl;
endtask: slock;
endmodule
module Master(qw,scl,mosi,miso,ss1,ss2,sel);

input qw;
output reg scl;
input miso;
output reg [0:0]mosi;
output reg ss1;
output reg ss2;
output reg [1:0] sel;
reg [16:0]xx;
initial begin
scl = 0;
ss1 = 1;
ss2 = 1;
#10 ss1 = 0;
sel = 0;
xx = 17'b011101001_00011001;
#100 ss2 = 0;
xx = 17'b010101011_00011001;
ss1 = 1;
sel = 1;
end
always @(negedge ss1 or negedge ss2)
slock ;
always @(posedge scl)begin
mosi = xx[16];
xx = xx<<1;
end
task slock;
repeat (38)
#2 scl = !scl;
endtask: slock;
endmodule