data/full_repos/permissive/199399537/datagene.v
data/verilator_xmls/41dbef0b-f976-4f29-9f71-ee0d7f9d9d5b.xml
module datagene(
				clk_20m,
				clk_100m,
				rst_n,
				wrf_din,
				wrf_wrreq,
				moni_addr,
				syswr_done,
				sdram_rd_ack,
				datain,
				write,
				index
			);

input clk_20m;
input clk_100m;
input rst_n;
input [15:0] datain;
output			[15:0] wrf_din;
output 			wrf_wrreq;	
output         write;
output         [4:0] index;

output			[21:0] moni_addr;
output 			syswr_done;

input 				sdram_rd_ack;



reg 				sdr_rdackr1;
reg					sdr_rdackr2;
reg					[15:0] delay;
reg 				wr_done;
reg					[18:0] 	addr;
reg 				wrf_wrreqr;
reg					[15:0] wrf_dinr;
reg             arwrite;
reg             [4:0] indexx;

wire 				neg_rdack 		= ~sdr_rdackr1 & sdr_rdackr2;
wire 				delay_done 	= (delay == 16'd50000);	


parameter 	[18:0] 	addr_end=19'h00003;


assign        index =indexx;
assign        write = arwrite;
assign 			wrf_wrreq 		= wrf_wrreqr;
assign 			wrf_din 			= wrf_dinr;
assign 			syswr_done 	= wr_done;
assign 			moni_addr 		= {addr,3'b0};


always @(posedge clk_100m or negedge rst_n)		
		if(!rst_n) 
			begin
				sdr_rdackr1 <= 1'b0;
				sdr_rdackr2 <= 1'b0;
			end
			
		else 
			begin
				sdr_rdackr1 <= sdram_rd_ack;
				sdr_rdackr2 <= sdr_rdackr1;				
			end



always @(posedge clk_100m or negedge rst_n)
	if(!rst_n) 
			delay <= 16'd0;
	else if(delay < 16'd50000) 
			delay <= delay+1'b1;


always @(posedge clk_100m or negedge rst_n)
	if(!rst_n) 
			begin
					wr_done	<=1'b0;
					addr 			<= 19'd0;
			end
	else if(addr == addr_end)
			begin
					wr_done 	<= 1'b1;
					addr			<=	19'd0;
			end
	else if(!wr_done && cntwr == 6'h3f)
			addr 	<= addr+1'b1;
					
	else if(neg_rdack) 
			addr	<=	addr+1'b1;



		

reg[5:0] cntwr;

always @(posedge clk_100m or negedge rst_n)
	if(!rst_n) 
			cntwr <= 6'd0;
	else if(delay_done) 
			cntwr <= cntwr+1'b1;



always @(posedge clk_100m or negedge rst_n)
	if(!rst_n) begin
			wrf_wrreqr <= 1'b0;
			indexx <= 5'b0;
	      arwrite <= 1'b0;
			end 
	else if(!wr_done) 
			begin	
					if((cntwr >= 6'h05) && (cntwr < 6'h0d))  begin 
							wrf_wrreqr <= 1'b1;
							indexx <= indexx + 1;
	                  arwrite <= 1'b1;
							end 
					else if(cntwr == 6'h0d) begin  
							wrf_wrreqr <= 1'b0;
		
							end 
			end

	
always @(posedge clk_100m or negedge rst_n)
	if(!rst_n) begin 
			wrf_dinr <= 16'h6211;

			end 
	else if(!wr_done && ((cntwr > 6'h05) && (cntwr <= 6'h0d))) 
			begin	
			wrf_dinr <= datain;	
				
			end
	
endmodule
module datagene(
				clk_20m,
				clk_100m,
				rst_n,
				wrf_din,
				wrf_wrreq,
				moni_addr,
				syswr_done,
				sdram_rd_ack,
				datain,
				write,
				index
			);


input clk_20m;
input clk_100m;
input rst_n;
input [15:0] datain;
output			[15:0] wrf_din;
output 			wrf_wrreq;	
output         write;
output         [4:0] index;

output			[21:0] moni_addr;
output 			syswr_done;

input 				sdram_rd_ack;



reg 				sdr_rdackr1;
reg					sdr_rdackr2;
reg					[15:0] delay;
reg 				wr_done;
reg					[18:0] 	addr;
reg 				wrf_wrreqr;
reg					[15:0] wrf_dinr;
reg             arwrite;
reg             [4:0] indexx;

wire 				neg_rdack 		= ~sdr_rdackr1 & sdr_rdackr2;
wire 				delay_done 	= (delay == 16'd50000);	


parameter 	[18:0] 	addr_end=19'h00003;


assign        index =indexx;
assign        write = arwrite;
assign 			wrf_wrreq 		= wrf_wrreqr;
assign 			wrf_din 			= wrf_dinr;
assign 			syswr_done 	= wr_done;
assign 			moni_addr 		= {addr,3'b0};


always @(posedge clk_100m or negedge rst_n)		
		if(!rst_n) 
			begin
				sdr_rdackr1 <= 1'b0;
				sdr_rdackr2 <= 1'b0;
			end
			
		else 
			begin
				sdr_rdackr1 <= sdram_rd_ack;
				sdr_rdackr2 <= sdr_rdackr1;				
			end



always @(posedge clk_100m or negedge rst_n)
	if(!rst_n) 
			delay <= 16'd0;
	else if(delay < 16'd50000) 
			delay <= delay+1'b1;


always @(posedge clk_100m or negedge rst_n)
	if(!rst_n) 
			begin
					wr_done	<=1'b0;
					addr 			<= 19'd0;
			end
	else if(addr == addr_end)
			begin
					wr_done 	<= 1'b1;
					addr			<=	19'd0;
			end
	else if(!wr_done && cntwr == 6'h3f)
			addr 	<= addr+1'b1;
					
	else if(neg_rdack) 
			addr	<=	addr+1'b1;



		

reg[5:0] cntwr;

always @(posedge clk_100m or negedge rst_n)
	if(!rst_n) 
			cntwr <= 6'd0;
	else if(delay_done) 
			cntwr <= cntwr+1'b1;



always @(posedge clk_100m or negedge rst_n)
	if(!rst_n) begin
			wrf_wrreqr <= 1'b0;
			indexx <= 5'b0;
	      arwrite <= 1'b0;
			end 
	else if(!wr_done) 
			begin	
					if((cntwr >= 6'h05) && (cntwr < 6'h0d))  begin 
							wrf_wrreqr <= 1'b1;
							indexx <= indexx + 1;
	                  arwrite <= 1'b1;
							end 
					else if(cntwr == 6'h0d) begin  
							wrf_wrreqr <= 1'b0;
		
							end 
			end

	
always @(posedge clk_100m or negedge rst_n)
	if(!rst_n) begin 
			wrf_dinr <= 16'h6211;

			end 
	else if(!wr_done && ((cntwr > 6'h05) && (cntwr <= 6'h0d))) 
			begin	
			wrf_dinr <= datain;	
				
			end
	
endmodule