data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v
 line:80: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #4 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_rst = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #30\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_PC_branch = 10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_PCSrc = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:83: Unsupported: Ignoring delay on this delayed statement.\n    always #1 i_clk = ~i_clk;\n           ^\n%Error: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_fetch.v:85: Cannot find file containing module: \'seg_instruction_fetch\'\n    seg_instruction_fetch \n    ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_instruction_fetch\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_instruction_fetch.v\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_instruction_fetch.sv\n             seg_instruction_fetch\n             seg_instruction_fetch.v\n             seg_instruction_fetch.sv\n             obj_dir/seg_instruction_fetch\n             obj_dir/seg_instruction_fetch.v\n             obj_dir/seg_instruction_fetch.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_seg_instruction_fetch();

	parameter LEN                     = 32;

    parameter RAM_WIDTH_PROGRAM       = 32;
    parameter RAM_DEPTH_PROGRAM       = 32;
    parameter RAM_PERFORMANCE_PROGRAM = "LOW_LATENCY";

    parameter INIT_FILE_PROGRAM       = "";
    

    reg                 i_clk;
    reg                 i_rst;
    reg [LEN - 1 : 0]   i_PC_branch;
    reg [LEN - 1 : 0]   i_PC_dir_jump;
    reg                 i_PCSrc;
    reg                 i_jump;
    reg                 i_stall_flag;
    reg                 i_preload_flag;
    reg [LEN - 1 : 0]   i_preload_address;
    reg [LEN - 1 : 0]   i_preload_instruction;

    wire [LEN - 1 : 0]  o_instruction;
    wire [LEN - 1 : 0]  o_PC;

    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;
        i_PC_branch = {LEN{1'b0}};
        i_PC_dir_jump = {LEN{1'b0}};
        i_PCSrc = 1'b0;
        i_jump = 1'b0;
        i_stall_flag = 1'b0;
        i_preload_flag = 1'b0;
        i_preload_address = {LEN{1'b0}};
        i_preload_instruction = {LEN{1'b0}};


        #4
        i_preload_flag = 1;
        i_preload_address = 0;
        i_preload_instruction = 32'hAB8B0000;
        #4
        i_preload_address = 1;
        i_preload_instruction = 32'hAB8B0001;
        #4
        i_preload_address = 2;
        i_preload_instruction = 32'hAB8B0002;
        #4
        i_preload_address = 3;
        i_preload_instruction = 32'hAB8B0003;
        #4
        i_preload_address = 6;
        i_preload_instruction = 32'hAB8B0006;

        #4 
        i_preload_flag = 0;
        i_rst = 1'b1;


        
        #10 i_rst = 1'b1;

        #30
        i_PCSrc = 1'b1;
        i_PC_branch = 3;

        #10
        i_PCSrc = 1'b0;
        i_PC_branch = 2;

        #10 i_PC_branch = 10;
        #10
        i_PC_branch = 0;
        i_PCSrc = 1'b1;
        #2 i_PCSrc = 1'b0;
        
        #10 $finish;
    end

    always #1 i_clk = ~i_clk;

    seg_instruction_fetch 
    #(
        .LEN                     (LEN                     ),
        .RAM_WIDTH_PROGRAM       (RAM_WIDTH_PROGRAM       ),
        .RAM_DEPTH_PROGRAM       (RAM_DEPTH_PROGRAM       ),
        .RAM_PERFORMANCE_PROGRAM (RAM_PERFORMANCE_PROGRAM ),
        .INIT_FILE_PROGRAM       (INIT_FILE_PROGRAM       )
    )
    u_seg_instruction_fetch(
    	.i_clk                 (i_clk                 ),
        .i_rst                 (i_rst                 ),
        .i_PC_branch           (i_PC_branch           ),
        .i_PC_dir_jump         (i_PC_dir_jump         ),
        .i_PCSrc               (i_PCSrc               ),
        .i_jump                (i_jump                ),
        .i_stall_flag          (i_stall_flag          ),
        .i_preload_flag        (i_preload_flag        ),
        .i_preload_address     (i_preload_address     ),
        .i_preload_instruction (i_preload_instruction ),
        .o_instruction         (o_instruction         ),
        .o_PC                  (o_PC                  )
    );
    

endmodule
module tb_seg_instruction_fetch();


	parameter LEN                     = 32;

    parameter RAM_WIDTH_PROGRAM       = 32;
    parameter RAM_DEPTH_PROGRAM       = 32;
    parameter RAM_PERFORMANCE_PROGRAM = "LOW_LATENCY";

    parameter INIT_FILE_PROGRAM       = "";
    

    reg                 i_clk;
    reg                 i_rst;
    reg [LEN - 1 : 0]   i_PC_branch;
    reg [LEN - 1 : 0]   i_PC_dir_jump;
    reg                 i_PCSrc;
    reg                 i_jump;
    reg                 i_stall_flag;
    reg                 i_preload_flag;
    reg [LEN - 1 : 0]   i_preload_address;
    reg [LEN - 1 : 0]   i_preload_instruction;

    wire [LEN - 1 : 0]  o_instruction;
    wire [LEN - 1 : 0]  o_PC;

    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;
        i_PC_branch = {LEN{1'b0}};
        i_PC_dir_jump = {LEN{1'b0}};
        i_PCSrc = 1'b0;
        i_jump = 1'b0;
        i_stall_flag = 1'b0;
        i_preload_flag = 1'b0;
        i_preload_address = {LEN{1'b0}};
        i_preload_instruction = {LEN{1'b0}};


        #4
        i_preload_flag = 1;
        i_preload_address = 0;
        i_preload_instruction = 32'hAB8B0000;
        #4
        i_preload_address = 1;
        i_preload_instruction = 32'hAB8B0001;
        #4
        i_preload_address = 2;
        i_preload_instruction = 32'hAB8B0002;
        #4
        i_preload_address = 3;
        i_preload_instruction = 32'hAB8B0003;
        #4
        i_preload_address = 6;
        i_preload_instruction = 32'hAB8B0006;

        #4 
        i_preload_flag = 0;
        i_rst = 1'b1;


        
        #10 i_rst = 1'b1;

        #30
        i_PCSrc = 1'b1;
        i_PC_branch = 3;

        #10
        i_PCSrc = 1'b0;
        i_PC_branch = 2;

        #10 i_PC_branch = 10;
        #10
        i_PC_branch = 0;
        i_PCSrc = 1'b1;
        #2 i_PCSrc = 1'b0;
        
        #10 $finish;
    end

    always #1 i_clk = ~i_clk;

    seg_instruction_fetch 
    #(
        .LEN                     (LEN                     ),
        .RAM_WIDTH_PROGRAM       (RAM_WIDTH_PROGRAM       ),
        .RAM_DEPTH_PROGRAM       (RAM_DEPTH_PROGRAM       ),
        .RAM_PERFORMANCE_PROGRAM (RAM_PERFORMANCE_PROGRAM ),
        .INIT_FILE_PROGRAM       (INIT_FILE_PROGRAM       )
    )
    u_seg_instruction_fetch(
    	.i_clk                 (i_clk                 ),
        .i_rst                 (i_rst                 ),
        .i_PC_branch           (i_PC_branch           ),
        .i_PC_dir_jump         (i_PC_dir_jump         ),
        .i_PCSrc               (i_PCSrc               ),
        .i_jump                (i_jump                ),
        .i_stall_flag          (i_stall_flag          ),
        .i_preload_flag        (i_preload_flag        ),
        .i_preload_address     (i_preload_address     ),
        .i_preload_instruction (i_preload_instruction ),
        .o_instruction         (o_instruction         ),
        .o_PC                  (o_PC                  )
    );
    

endmodule