data/full_repos/permissive/203526788/GoBoard/Debouncer/Debouncer.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/203526788/GoBoard/Debouncer/Debouncer.v:35: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'state'\n                                                                                         : ... In instance Debouncer\n   state= ~state;\n   ^~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module Debouncer (
	input CLK,
	input in,
	output reg out
	);

wire state = out;
reg prev, curr;

always @(posedge CLK)
begin
	prev= in;
	curr= prev;
end

reg [16:0] count;
wire idle = (state == curr);
wire finish = &count;


always @(posedge CLK)
begin
	if (idle)
	begin
		count <= 0;
	end
	else
	begin
		count <= count + 1;
		if (finish)
		begin
			state= ~state;
		end
	end
end

endmodule
module Debouncer (
	input CLK,
	input in,
	output reg out
	);


wire state = out;
reg prev, curr;

always @(posedge CLK)
begin
	prev= in;
	curr= prev;
end

reg [16:0] count;
wire idle = (state == curr);
wire finish = &count;


always @(posedge CLK)
begin
	if (idle)
	begin
		count <= 0;
	end
	else
	begin
		count <= count + 1;
		if (finish)
		begin
			state= ~state;
		end
	end
end

endmodule