data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:102: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:103: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:106: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:107: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:108: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:110: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:114: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:115: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:116: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:117: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:118: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:121: Cannot find file containing module: \'ovl_always_on_edge_wrapped\'\n  ovl_always_on_edge_wrapped oaoew(\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_always_on_edge_wrapped\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_always_on_edge_wrapped.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_always_on_edge_wrapped.sv\n             ovl_always_on_edge_wrapped\n             ovl_always_on_edge_wrapped.v\n             ovl_always_on_edge_wrapped.sv\n             obj_dir/ovl_always_on_edge_wrapped\n             obj_dir/ovl_always_on_edge_wrapped.v\n             obj_dir/ovl_always_on_edge_wrapped.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestOVL.v:130: Cannot find file containing module: \'ovl_always_wrapped\'\n  ovl_always_wrapped oaw(\n  ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 36 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module unitTestOVL();
  reg clk;
  wire rst;
  reg a;
  reg b;
  wire inv;
  wire assert_edge, assert_always;
  
  initial begin
    clk = 1'b0;
    a = 1'b0;
    b = 1'b0;
  end
   
  assign rst = 1'b0;
  assign inv = 1'b0;
  




  
  always begin
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    b = 1'b1;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    b = 1'b0;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    a = 1;
    b = 1;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    b = 0;
    #10 clk = ~clk;
    #10 clk = ~clk;
    a = 0;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    a = 1;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    a = 0;
    b = 1;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
  end
  
  ovl_always_on_edge_wrapped oaoew(
    .clk(clk),
    .rst(rst),
    .sampling_event(a),
    .test_expr(b),
    .prevConfigInvalid(inv),
    .out(assert_edge)
  );
  
  ovl_always_wrapped oaw(
    .clk(clk),
    .rst(rst),
    .test_expr(b),
    .prevConfigInvalid(inv),
    .out(assert_always)
  );
endmodule
module unitTestOVL();

  reg clk;
  wire rst;
  reg a;
  reg b;
  wire inv;
  wire assert_edge, assert_always;
  
  initial begin
    clk = 1'b0;
    a = 1'b0;
    b = 1'b0;
  end
   
  assign rst = 1'b0;
  assign inv = 1'b0;
  




  
  always begin
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    b = 1'b1;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    b = 1'b0;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    a = 1;
    b = 1;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    b = 0;
    #10 clk = ~clk;
    #10 clk = ~clk;
    a = 0;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    a = 1;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    a = 0;
    b = 1;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
  end
  
  ovl_always_on_edge_wrapped oaoew(
    .clk(clk),
    .rst(rst),
    .sampling_event(a),
    .test_expr(b),
    .prevConfigInvalid(inv),
    .out(assert_edge)
  );
  
  ovl_always_wrapped oaw(
    .clk(clk),
    .rst(rst),
    .test_expr(b),
    .prevConfigInvalid(inv),
    .out(assert_always)
  );
endmodule