data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v
1: b'%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:97: Cannot find file containing module: \'butterfly0\'\n butterfly0 butt0_layer1(.ai(in0),\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/butterfly0\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/butterfly0.v\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/butterfly0.sv\n             butterfly0\n             butterfly0.v\n             butterfly0.sv\n             obj_dir/butterfly0\n             obj_dir/butterfly0.v\n             obj_dir/butterfly0.sv\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:102: Cannot find file containing module: \'butterfly1\'\n butterfly1 butt1_layer1(.ai(in1),\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:107: Cannot find file containing module: \'butterfly2r\'\n butterfly2r butt2_layer1(.ai(in2),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:112: Cannot find file containing module: \'butterfly3r\'\n butterfly3r butt3_layer1(.ai(in3),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:119: Cannot find file containing module: \'butterfly0\'\n butterfly0 butt0a_layer2(.ai(out0_layer1), \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:124: Cannot find file containing module: \'butterfly0\'\n butterfly0 butt0b_layer2(.ai(out4_layer1), \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:129: Cannot find file containing module: \'butterfly2\'\n butterfly2 butt2_layer2(.ai(out1_layer1), \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:134: Cannot find file containing module: \'butterfly2r\'\n butterfly2r butt3_layer2(.ai(out5_layer1), \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:141: Cannot find file containing module: \'butterfly0\'\n butterfly0 butt0a_layer3(.ai(out0_layer2), \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:146: Cannot find file containing module: \'butterfly0\'\n butterfly0 butt0b_layer3(.ai(out2_layer2), \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:151: Cannot find file containing module: \'butterfly0\'\n butterfly0 butt0c_layer3(.ai(out4_layer2), \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:156: Cannot find file containing module: \'butterfly0\'\n butterfly0 butt0d_layer3(.ai(out6_layer2), \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:163: Cannot find file containing module: \'do_reduce_full\'\n do_reduce_full do_reduce_full1(.ai(out0_layer3), \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:166: Cannot find file containing module: \'do_reduce_full\'\n do_reduce_full do_reduce_full2(.ai(out1_layer3), \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:169: Cannot find file containing module: \'do_reduce_full\'\n do_reduce_full do_reduce_full3(.ai(out2_layer3), \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:172: Cannot find file containing module: \'do_reduce_full\'\n do_reduce_full do_reduce_full4(.ai(out3_layer3), \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:175: Cannot find file containing module: \'do_reduce_full\'\n do_reduce_full do_reduce_full5(.ai(out4_layer3), \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:178: Cannot find file containing module: \'do_reduce_full\'\n do_reduce_full do_reduce_full6(.ai(out5_layer3), \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:181: Cannot find file containing module: \'do_reduce_full\'\n do_reduce_full do_reduce_full7(.ai(out6_layer3), \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:184: Cannot find file containing module: \'do_reduce_full\'\n do_reduce_full do_reduce_full8(.ai(out7_layer3), \n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:189: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'i0\' generates 10 bits.\n                                                                              : ... In instance FFT_8\n assign in0 = i0;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:190: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'i1\' generates 10 bits.\n                                                                              : ... In instance FFT_8\n assign in1 = i1;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:191: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'i2\' generates 10 bits.\n                                                                              : ... In instance FFT_8\n assign in2 = i2;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:192: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'i3\' generates 10 bits.\n                                                                              : ... In instance FFT_8\n assign in3 = i3;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:193: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'i4\' generates 10 bits.\n                                                                              : ... In instance FFT_8\n assign in4 = i4;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:194: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'i5\' generates 10 bits.\n                                                                              : ... In instance FFT_8\n assign in5 = i5;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:195: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'i6\' generates 10 bits.\n                                                                              : ... In instance FFT_8\n assign in6 = i6;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_8.v:196: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'i7\' generates 10 bits.\n                                                                              : ... In instance FFT_8\n assign in7 = i7;\n            ^\n%Error: Exiting due to 20 error(s), 8 warning(s)\n'
module FFT_8(i0,
			 i1,
			 i2,
			 i3,
			 i4,
			 i5,
			 i6,
			 i7,
			 o0,
			 o1,
			 o2,
			 o3,
			 o4,
			 o5,
			 o6,
			 o7
			 );


	input signed [9:0] i0;
	input signed [9:0] i1;
	input signed [9:0] i2;
	input signed [9:0] i3;
	input signed [9:0] i4;
	input signed [9:0] i5;
	input signed [9:0] i6;
	input signed [9:0] i7;
	

	output signed [8:0] o0;
	output signed [8:0] o1;
	output signed [8:0] o2;
	output signed [8:0] o3;
	output signed [8:0] o4;
	output signed [8:0] o5;
	output signed [8:0] o6;
	output signed [8:0] o7;
	

	wire signed [14:0] in0;
	wire signed [14:0] in1;
	wire signed [14:0] in2;
	wire signed [14:0] in3;
	wire signed [14:0] in4;
	wire signed [14:0] in5;
	wire signed [14:0] in6;
	wire signed [14:0] in7;


	wire signed [14:0] out0_layer1;
	wire signed [14:0] out1_layer1;
	wire signed [14:0] out2_layer1;
	wire signed [14:0] out3_layer1;
	wire signed [14:0] out4_layer1;
	wire signed [14:0] out5_layer1;
	wire signed [14:0] out6_layer1;
	wire signed [14:0] out7_layer1;
	

	wire signed [14:0] out0_layer2;
	wire signed [14:0] out1_layer2;
	wire signed [14:0] out2_layer2;
	wire signed [14:0] out3_layer2;
	wire signed [14:0] out4_layer2;
	wire signed [14:0] out5_layer2;
	wire signed [14:0] out6_layer2;
	wire signed [14:0] out7_layer2;
	

	wire signed [14:0] out0_layer3;
	wire signed [14:0] out1_layer3;
	wire signed [14:0] out2_layer3;
	wire signed [14:0] out3_layer3;
	wire signed [14:0] out4_layer3;
	wire signed [14:0] out5_layer3;
	wire signed [14:0] out6_layer3;
	wire signed [14:0] out7_layer3;


	butterfly0 butt0_layer1(.ai(in0),
							.bi(in4),
							.ao(out0_layer1),
							.bo(out4_layer1)
							);
	butterfly1 butt1_layer1(.ai(in1),
							.bi(in5),
							.ao(out1_layer1),
							.bo(out5_layer1)
							);
	butterfly2r butt2_layer1(.ai(in2),
							 .bi(in6),
							 .ao(out2_layer1),
							 .bo(out6_layer1)
							 );
	butterfly3r butt3_layer1(.ai(in3),
							 .bi(in7),
							 .ao(out3_layer1),
							 .bo(out7_layer1)
							 );
	

	butterfly0 butt0a_layer2(.ai(out0_layer1), 
							 .bi(out2_layer1), 
							 .ao(out0_layer2), 
							 .bo(out2_layer2)
							 );
	butterfly0 butt0b_layer2(.ai(out4_layer1), 
							 .bi(out6_layer1), 
							 .ao(out4_layer2), 
							 .bo(out6_layer2)
							 );
	butterfly2 butt2_layer2(.ai(out1_layer1), 
							.bi(out3_layer1), 
							.ao(out1_layer2), 
							.bo(out3_layer2)
							);
	butterfly2r butt3_layer2(.ai(out5_layer1), 
							 .bi(out7_layer1), 
							 .ao(out5_layer2), 
							 .bo(out7_layer2)
							 );	
	

	butterfly0 butt0a_layer3(.ai(out0_layer2), 
							 .bi(out1_layer2), 
							 .ao(out0_layer3), 
							 .bo(out1_layer3)
							 );
	butterfly0 butt0b_layer3(.ai(out2_layer2), 
							 .bi(out3_layer2), 
							 .ao(out2_layer3), 
							 .bo(out3_layer3)
							 );
	butterfly0 butt0c_layer3(.ai(out4_layer2), 
							 .bi(out5_layer2), 
							 .ao(out4_layer3), 
							 .bo(out5_layer3)
							 );
	butterfly0 butt0d_layer3(.ai(out6_layer2), 
							 .bi(out7_layer2), 
							 .ao(out6_layer3), 
							 .bo(out7_layer3)
							 );
	

	do_reduce_full do_reduce_full1(.ai(out0_layer3), 
								   .ao(o0)
								   );
	do_reduce_full do_reduce_full2(.ai(out1_layer3), 
								   .ao(o1)
								   );
	do_reduce_full do_reduce_full3(.ai(out2_layer3), 
								   .ao(o2)
								   );
	do_reduce_full do_reduce_full4(.ai(out3_layer3), 
								   .ao(o3)
								   );
	do_reduce_full do_reduce_full5(.ai(out4_layer3), 
								   .ao(o4)
								   );
	do_reduce_full do_reduce_full6(.ai(out5_layer3), 
								   .ao(o5)
								   );
	do_reduce_full do_reduce_full7(.ai(out6_layer3), 
								   .ao(o6)
								   );
	do_reduce_full do_reduce_full8(.ai(out7_layer3), 
								   .ao(o7)
								   );
	

	assign in0 = i0;
	assign in1 = i1;
	assign in2 = i2;
	assign in3 = i3;
	assign in4 = i4;
	assign in5 = i5;
	assign in6 = i6;
	assign in7 = i7;
	
	
endmodule
module FFT_8(i0,
			 i1,
			 i2,
			 i3,
			 i4,
			 i5,
			 i6,
			 i7,
			 o0,
			 o1,
			 o2,
			 o3,
			 o4,
			 o5,
			 o6,
			 o7
			 );



	input signed [9:0] i0;
	input signed [9:0] i1;
	input signed [9:0] i2;
	input signed [9:0] i3;
	input signed [9:0] i4;
	input signed [9:0] i5;
	input signed [9:0] i6;
	input signed [9:0] i7;
	

	output signed [8:0] o0;
	output signed [8:0] o1;
	output signed [8:0] o2;
	output signed [8:0] o3;
	output signed [8:0] o4;
	output signed [8:0] o5;
	output signed [8:0] o6;
	output signed [8:0] o7;
	

	wire signed [14:0] in0;
	wire signed [14:0] in1;
	wire signed [14:0] in2;
	wire signed [14:0] in3;
	wire signed [14:0] in4;
	wire signed [14:0] in5;
	wire signed [14:0] in6;
	wire signed [14:0] in7;


	wire signed [14:0] out0_layer1;
	wire signed [14:0] out1_layer1;
	wire signed [14:0] out2_layer1;
	wire signed [14:0] out3_layer1;
	wire signed [14:0] out4_layer1;
	wire signed [14:0] out5_layer1;
	wire signed [14:0] out6_layer1;
	wire signed [14:0] out7_layer1;
	

	wire signed [14:0] out0_layer2;
	wire signed [14:0] out1_layer2;
	wire signed [14:0] out2_layer2;
	wire signed [14:0] out3_layer2;
	wire signed [14:0] out4_layer2;
	wire signed [14:0] out5_layer2;
	wire signed [14:0] out6_layer2;
	wire signed [14:0] out7_layer2;
	

	wire signed [14:0] out0_layer3;
	wire signed [14:0] out1_layer3;
	wire signed [14:0] out2_layer3;
	wire signed [14:0] out3_layer3;
	wire signed [14:0] out4_layer3;
	wire signed [14:0] out5_layer3;
	wire signed [14:0] out6_layer3;
	wire signed [14:0] out7_layer3;


	butterfly0 butt0_layer1(.ai(in0),
							.bi(in4),
							.ao(out0_layer1),
							.bo(out4_layer1)
							);
	butterfly1 butt1_layer1(.ai(in1),
							.bi(in5),
							.ao(out1_layer1),
							.bo(out5_layer1)
							);
	butterfly2r butt2_layer1(.ai(in2),
							 .bi(in6),
							 .ao(out2_layer1),
							 .bo(out6_layer1)
							 );
	butterfly3r butt3_layer1(.ai(in3),
							 .bi(in7),
							 .ao(out3_layer1),
							 .bo(out7_layer1)
							 );
	

	butterfly0 butt0a_layer2(.ai(out0_layer1), 
							 .bi(out2_layer1), 
							 .ao(out0_layer2), 
							 .bo(out2_layer2)
							 );
	butterfly0 butt0b_layer2(.ai(out4_layer1), 
							 .bi(out6_layer1), 
							 .ao(out4_layer2), 
							 .bo(out6_layer2)
							 );
	butterfly2 butt2_layer2(.ai(out1_layer1), 
							.bi(out3_layer1), 
							.ao(out1_layer2), 
							.bo(out3_layer2)
							);
	butterfly2r butt3_layer2(.ai(out5_layer1), 
							 .bi(out7_layer1), 
							 .ao(out5_layer2), 
							 .bo(out7_layer2)
							 );	
	

	butterfly0 butt0a_layer3(.ai(out0_layer2), 
							 .bi(out1_layer2), 
							 .ao(out0_layer3), 
							 .bo(out1_layer3)
							 );
	butterfly0 butt0b_layer3(.ai(out2_layer2), 
							 .bi(out3_layer2), 
							 .ao(out2_layer3), 
							 .bo(out3_layer3)
							 );
	butterfly0 butt0c_layer3(.ai(out4_layer2), 
							 .bi(out5_layer2), 
							 .ao(out4_layer3), 
							 .bo(out5_layer3)
							 );
	butterfly0 butt0d_layer3(.ai(out6_layer2), 
							 .bi(out7_layer2), 
							 .ao(out6_layer3), 
							 .bo(out7_layer3)
							 );
	

	do_reduce_full do_reduce_full1(.ai(out0_layer3), 
								   .ao(o0)
								   );
	do_reduce_full do_reduce_full2(.ai(out1_layer3), 
								   .ao(o1)
								   );
	do_reduce_full do_reduce_full3(.ai(out2_layer3), 
								   .ao(o2)
								   );
	do_reduce_full do_reduce_full4(.ai(out3_layer3), 
								   .ao(o3)
								   );
	do_reduce_full do_reduce_full5(.ai(out4_layer3), 
								   .ao(o4)
								   );
	do_reduce_full do_reduce_full6(.ai(out5_layer3), 
								   .ao(o5)
								   );
	do_reduce_full do_reduce_full7(.ai(out6_layer3), 
								   .ao(o6)
								   );
	do_reduce_full do_reduce_full8(.ai(out7_layer3), 
								   .ao(o7)
								   );
	

	assign in0 = i0;
	assign in1 = i1;
	assign in2 = i2;
	assign in3 = i3;
	assign in4 = i4;
	assign in5 = i5;
	assign in6 = i6;
	assign in7 = i7;
	
	
endmodule