data/full_repos/permissive/115035459/verilog/src/example002.v
 line:23: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #41.7 CLK = ~CLK;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115035459/verilog/src/example002.v:23: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("work/example002.vcd");\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #0\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/example002.v:24: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #100000 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
	reg [31:0] counter = 0;
	wire [5:1] LED;
	reg CLK = 0;
	always
		#41.7 CLK = ~CLK;
	always @(posedge CLK) begin
		counter <= counter + 1;
	end
	initial begin
		#0
		$dumpfile("work/example002.vcd");
		$dumpvars(0, testbench);
		#100000 $finish;
	end
	top #(.LOG2DELAY(1)) my_top_instance (.CLK(CLK), .LED1(LED[1]), .LED2(LED[2]), .LED3(LED[3]), .LED4(LED[4]), .LED5(LED[5]));
endmodule
module testbench;

	reg [31:0] counter = 0;
	wire [5:1] LED;
	reg CLK = 0;
	always
		#41.7 CLK = ~CLK;
	always @(posedge CLK) begin
		counter <= counter + 1;
	end
	initial begin
		#0
		$dumpfile("work/example002.vcd");
		$dumpvars(0, testbench);
		#100000 $finish;
	end
	top #(.LOG2DELAY(1)) my_top_instance (.CLK(CLK), .LED1(LED[1]), .LED2(LED[2]), .LED3(LED[3]), .LED4(LED[4]), .LED5(LED[5]));
endmodule