data/full_repos/permissive/154371523/Code/rtl/xbooth.v
1: b'%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xbooth.v:20: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'bit_index\' generates 5 bits.\n                                                                         : ... In instance booth_mult\n    wire          ready = !bit_index;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xbooth.v:41: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'multiplicand\' generates 12 bits.\n                                                                         : ... In instance booth_mult\n    3\'b011: product[24:12] = product[24:12] + (multiplicand << 1);  \n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xbooth.v:42: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'multiplicand\' generates 12 bits.\n                                                                         : ... In instance booth_mult\n    3\'b100: product[24:12] = product[24:12] - (multiplicand << 1);  \n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xbooth.v:35: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'bit_index\' generates 5 bits.\n                                                                         : ... In instance booth_mult\n  else if( bit_index ) begin\n       ^~\n%Error: Exiting due to 4 warning(s)\n'
module booth_mult(prod,ready,multiplicand,multiplier,start,clk);

	input [11:0]  multiplicand, multiplier;
    input         start, clk;
    output [23:0] prod;
    output        ready;

    reg [24:0]    product = 0;
    
    assign prod = product[23:0];

    reg [4:0]     bit_index = 0; 
    wire          ready = !bit_index;
    reg           lostbit = 0;
   

    wire [12:0]   multsx = {multiplicand[11],multiplicand};

	always @( posedge clk )

		if( ready && start ) begin

        bit_index = 6;
        product = { 13'b0, multiplier };
        lostbit = 0;
        
		end 
		else if( bit_index ) begin

			case ( {product[1:0],lostbit} )

				3'b001: product[24:12] = product[24:12] + multsx;
				3'b010: product[24:12] = product[24:12] + multsx;
				3'b011: product[24:12] = product[24:12] + (multiplicand << 1);
				3'b100: product[24:12] = product[24:12] - (multiplicand << 1);
				3'b101: product[24:12] = product[24:12] - multsx;
				3'b110: product[24:12] = product[24:12] - multsx;

			endcase

			  lostbit = product[1];
			  product = { product[24], product[24], product[24:2] };
			  bit_index = bit_index - 1;

     end

endmodule
module booth_mult(prod,ready,multiplicand,multiplier,start,clk);


	input [11:0]  multiplicand, multiplier;
    input         start, clk;
    output [23:0] prod;
    output        ready;

    reg [24:0]    product = 0;
    
    assign prod = product[23:0];

    reg [4:0]     bit_index = 0; 
    wire          ready = !bit_index;
    reg           lostbit = 0;
   

    wire [12:0]   multsx = {multiplicand[11],multiplicand};

	always @( posedge clk )

		if( ready && start ) begin

        bit_index = 6;
        product = { 13'b0, multiplier };
        lostbit = 0;
        
		end 
		else if( bit_index ) begin

			case ( {product[1:0],lostbit} )

				3'b001: product[24:12] = product[24:12] + multsx;
				3'b010: product[24:12] = product[24:12] + multsx;
				3'b011: product[24:12] = product[24:12] + (multiplicand << 1);
				3'b100: product[24:12] = product[24:12] - (multiplicand << 1);
				3'b101: product[24:12] = product[24:12] - multsx;
				3'b110: product[24:12] = product[24:12] - multsx;

			endcase

			  lostbit = product[1];
			  product = { product[24], product[24], product[24:2] };
			  bit_index = bit_index - 1;

     end

endmodule