data/full_repos/permissive/18921956/HardwareLab/Lab5/Lab5.v
1: b"%Error: data/full_repos/permissive/18921956/HardwareLab/Lab5/Lab5.v:21: Cannot find file containing module: 'clock_divisor'\nclock_divisor CD(clk24, clk22, clk15, clk);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18921956/HardwareLab/Lab5,data/full_repos/permissive/18921956/clock_divisor\n             data/full_repos/permissive/18921956/HardwareLab/Lab5,data/full_repos/permissive/18921956/clock_divisor.v\n             data/full_repos/permissive/18921956/HardwareLab/Lab5,data/full_repos/permissive/18921956/clock_divisor.sv\n             clock_divisor\n             clock_divisor.v\n             clock_divisor.sv\n             obj_dir/clock_divisor\n             obj_dir/clock_divisor.v\n             obj_dir/clock_divisor.sv\n%Error: data/full_repos/permissive/18921956/HardwareLab/Lab5/Lab5.v:22: Cannot find file containing module: 'debounce'\ndebounce resDB(DB_rst, reset, clk15);\n^~~~~~~~\n%Error: data/full_repos/permissive/18921956/HardwareLab/Lab5/Lab5.v:23: Cannot find file containing module: 'KeyBoard_ctrl'\nKeyBoard_ctrl kbSeg(clk, DB_rst, row, column, KB1, KB0);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18921956/HardwareLab/Lab5/Lab5.v:24: Cannot find file containing module: 'pingpong_counter'\npingpong_counter PC(max, min, BCD1, BCD0, KB1, KB0, clk_selected, DB_rst );\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18921956/HardwareLab/Lab5/Lab5.v:25: Cannot find file containing module: 'LED7SEG'\nLED7SEG SevenSeg(DIGIT, DISPLAY, BCD0, BCD1, KB0, KB1, clk15);\n^~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module lab5(DIGIT, DISPLAY, max, min, clk, reset, speed, row, column);
input clk;
input reset;
input speed;

input [3:0] column;
output [3:0] row;
output [3:0] DIGIT;
output [7:0] DISPLAY;
output max;
output min;

wire clk24, clk22, clk15, clk_selected;
wire DB_rst;
wire [3:0] BCD1, BCD0;
wire [3:0] KB1, KB0;


clock_divisor CD(clk24, clk22, clk15, clk);
debounce resDB(DB_rst, reset, clk15);
KeyBoard_ctrl kbSeg(clk, DB_rst, row, column, KB1, KB0);
pingpong_counter PC(max, min, BCD1, BCD0, KB1, KB0, clk_selected, DB_rst );
LED7SEG SevenSeg(DIGIT, DISPLAY, BCD0, BCD1, KB0, KB1, clk15);

assign clk_selected = (speed==0) ? clk24 : clk22 ;

endmodule
module lab5(DIGIT, DISPLAY, max, min, clk, reset, speed, row, column);

input clk;
input reset;
input speed;

input [3:0] column;
output [3:0] row;
output [3:0] DIGIT;
output [7:0] DISPLAY;
output max;
output min;

wire clk24, clk22, clk15, clk_selected;
wire DB_rst;
wire [3:0] BCD1, BCD0;
wire [3:0] KB1, KB0;


clock_divisor CD(clk24, clk22, clk15, clk);
debounce resDB(DB_rst, reset, clk15);
KeyBoard_ctrl kbSeg(clk, DB_rst, row, column, KB1, KB0);
pingpong_counter PC(max, min, BCD1, BCD0, KB1, KB0, clk_selected, DB_rst );
LED7SEG SevenSeg(DIGIT, DISPLAY, BCD0, BCD1, KB0, KB1, clk15);

assign clk_selected = (speed==0) ? clk24 : clk22 ;

endmodule