data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v:25: Operator ADD expects 17 bits on the RHS, but RHS\'s REPLICATE generates 15 bits.\n                                                                                            : ... In instance vga_address_translator\n wire [16:0] res_320x240 = ({1\'b0, y, 8\'d0} + {1\'b0, y, 6\'d0} + {1\'b0, x});\n                                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v:25: Operator ADD expects 17 bits on the RHS, but RHS\'s REPLICATE generates 10 bits.\n                                                                                            : ... In instance vga_address_translator\n wire [16:0] res_320x240 = ({1\'b0, y, 8\'d0} + {1\'b0, y, 6\'d0} + {1\'b0, x});\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v:26: Operator ADD expects 16 bits on the RHS, but RHS\'s REPLICATE generates 14 bits.\n                                                                                            : ... In instance vga_address_translator\n wire [15:0] res_160x120 = ({1\'b0, y, 7\'d0} + {1\'b0, y, 5\'d0} + {1\'b0, x});\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v:26: Operator ADD expects 16 bits on the RHS, but RHS\'s REPLICATE generates 10 bits.\n                                                                                            : ... In instance vga_address_translator\n wire [15:0] res_160x120 = ({1\'b0, y, 7\'d0} + {1\'b0, y, 5\'d0} + {1\'b0, x});\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/104147155/vga_adapter/vga_address_translator.v:33: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s SEL generates 15 bits.\n                                                                                            : ... In instance vga_address_translator\n   mem_address = res_160x120[14:0];\n               ^\n%Error: Exiting due to 5 warning(s)\n'
module vga_address_translator(x, y, mem_address);

	parameter RESOLUTION = "320x240";


	input [((RESOLUTION == "320x240") ? (8) : (7)):0] x; 
	input [((RESOLUTION == "320x240") ? (7) : (6)):0] y;	
	output reg [((RESOLUTION == "320x240") ? (16) : (14)):0] mem_address;
	

	wire [16:0] res_320x240 = ({1'b0, y, 8'd0} + {1'b0, y, 6'd0} + {1'b0, x});
	wire [15:0] res_160x120 = ({1'b0, y, 7'd0} + {1'b0, y, 5'd0} + {1'b0, x});
	
	always @(*)
	begin
		if (RESOLUTION == "320x240")
			mem_address = res_320x240;
		else
			mem_address = res_160x120[14:0];
	end
endmodule
module vga_address_translator(x, y, mem_address);


	parameter RESOLUTION = "320x240";


	input [((RESOLUTION == "320x240") ? (8) : (7)):0] x; 
	input [((RESOLUTION == "320x240") ? (7) : (6)):0] y;	
	output reg [((RESOLUTION == "320x240") ? (16) : (14)):0] mem_address;
	

	wire [16:0] res_320x240 = ({1'b0, y, 8'd0} + {1'b0, y, 6'd0} + {1'b0, x});
	wire [15:0] res_160x120 = ({1'b0, y, 7'd0} + {1'b0, y, 5'd0} + {1'b0, x});
	
	always @(*)
	begin
		if (RESOLUTION == "320x240")
			mem_address = res_320x240;
		else
			mem_address = res_160x120[14:0];
	end
endmodule