data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:18: Cannot find include file: raggedstone_spinn_aer_if_top.h\n`include "raggedstone_spinn_aer_if_top.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if,data/full_repos/permissive/19591557/raggedstone_spinn_aer_if_top.h\n             data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if,data/full_repos/permissive/19591557/raggedstone_spinn_aer_if_top.h.v\n             data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if,data/full_repos/permissive/19591557/raggedstone_spinn_aer_if_top.h.sv\n             raggedstone_spinn_aer_if_top.h\n             raggedstone_spinn_aer_if_top.h.v\n             raggedstone_spinn_aer_if_top.h.sv\n             obj_dir/raggedstone_spinn_aer_if_top.h\n             obj_dir/raggedstone_spinn_aer_if_top.h.v\n             obj_dir/raggedstone_spinn_aer_if_top.h.sv\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:19: Cannot find include file: ../../modules/spinnaker_link/spio_spinnaker_link.h\n`include "../../modules/spinnaker_link/spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:29: Define or directive not defined: \'`PKT_BITS\'\n  input  wire [`PKT_BITS - 1:0] cpkt_data,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:34: Define or directive not defined: \'`MODE_BITS\'\n  input  wire [`MODE_BITS - 1:0] msel,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:35: Define or directive not defined: \'`VKS_BITS\'\n  input  wire  [`VKS_BITS - 1:0] vksel,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:36: Define or directive not defined: \'`MODE_BITS\'\n  output reg  [`MODE_BITS - 1:0] vmode,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:37: Define or directive not defined: \'`VKEY_BITS\'\n  output reg  [`VKEY_BITS - 1:0] vkey,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:62: Define or directive not defined: \'`VKS_ALT\'\n      `VKS_ALT: vkey = `VIRTUAL_KEY_ALT;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:62: syntax error, unexpected \':\', expecting endcase\n      `VKS_ALT: vkey = `VIRTUAL_KEY_ALT;\n              ^\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:62: Define or directive not defined: \'`VIRTUAL_KEY_ALT\'\n      `VKS_ALT: vkey = `VIRTUAL_KEY_ALT;\n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:63: Define or directive not defined: \'`VIRTUAL_KEY_DEF\'\n      default:  vkey = `VIRTUAL_KEY_DEF;\n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_control.v:73: Define or directive not defined: \'`INIT_GO\'\n      go <= `INIT_GO;\n            ^~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module raggedstone_spinn_aer_if_control
(
  input  wire                   rst,
  input  wire                   clk,


  input  wire [`PKT_BITS - 1:0] cpkt_data,
  input  wire                   cpkt_vld,
  output reg                    cpkt_rdy,


  input  wire [`MODE_BITS - 1:0] msel,
  input  wire  [`VKS_BITS - 1:0] vksel,
  output reg  [`MODE_BITS - 1:0] vmode,
  output reg  [`VKEY_BITS - 1:0] vkey,
  output reg                    go
);




  always @(*)
    cpkt_rdy <= 1'b1;






  always @(*)
    vmode = msel;






  always @(*)
    case (vksel)
      `VKS_ALT: vkey = `VIRTUAL_KEY_ALT;
      default:  vkey = `VIRTUAL_KEY_DEF;
    endcase






  always @(posedge clk or posedge rst)
    if (rst)
      go <= `INIT_GO;
    else
      if (cpkt_vld)
        go <= cpkt_data[8];
endmodule
module raggedstone_spinn_aer_if_control
(
  input  wire                   rst,
  input  wire                   clk,


  input  wire [`PKT_BITS - 1:0] cpkt_data,
  input  wire                   cpkt_vld,
  output reg                    cpkt_rdy,


  input  wire [`MODE_BITS - 1:0] msel,
  input  wire  [`VKS_BITS - 1:0] vksel,
  output reg  [`MODE_BITS - 1:0] vmode,
  output reg  [`VKEY_BITS - 1:0] vkey,
  output reg                    go
);





  always @(*)
    cpkt_rdy <= 1'b1;






  always @(*)
    vmode = msel;






  always @(*)
    case (vksel)
      `VKS_ALT: vkey = `VIRTUAL_KEY_ALT;
      default:  vkey = `VIRTUAL_KEY_DEF;
    endcase






  always @(posedge clk or posedge rst)
    if (rst)
      go <= `INIT_GO;
    else
      if (cpkt_vld)
        go <= cpkt_data[8];
endmodule