data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:50: Signal definition not found, creating implicitly: \'CS\'\n                                                                              : ... Suggested alternative: \'BS\'\n  assign MbConstIM = CS ? (IR_DOF[14] ? ~IR_DOF[14:0]+1 : IR_DOF[14:0]) : IR_DOF[14:0];\n                     ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:69: Signal definition not found, creating implicitly: \'MA\'\n                                                                              : ... Suggested alternative: \'HA\'\n  assign HA = CompAA_EX && ~MA && RW_EX;\n                            ^~\n%Warning-IMPLICIT: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:70: Signal definition not found, creating implicitly: \'MB\'\n                                                                              : ... Suggested alternative: \'HB\'\n  assign HB = CompBA_EX && ~MB && RW_EX;\n                            ^~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:27: Cannot find file containing module: \'MUX4\'\n MUX4 mC(PCSelect, PC_DOF, BrA, RAA_EX, BrA, PC);  \n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/170402453/RISC_DIVIDER,data/full_repos/permissive/170402453/MUX4\n             data/full_repos/permissive/170402453/RISC_DIVIDER,data/full_repos/permissive/170402453/MUX4.v\n             data/full_repos/permissive/170402453/RISC_DIVIDER,data/full_repos/permissive/170402453/MUX4.sv\n             MUX4\n             MUX4.v\n             MUX4.sv\n             obj_dir/MUX4\n             obj_dir/MUX4.v\n             obj_dir/MUX4.sv\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:32: Cannot find file containing module: \'NegEdgeBuffer32\'\n  NegEdgeBuffer32 pcif(clk, PC, PC_IF);\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:34: Cannot find file containing module: \'Instruction32BitMemory\'\n  Instruction32BitMemory InstMem(clk, PC_IF, IR);\n  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:42: Cannot find file containing module: \'NegEdgeBuffer32\'\n  NegEdgeBuffer32 pcdof(clk, PC_IF+1, PC_DOF);\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:43: Cannot find file containing module: \'NegEdgeBuffer32\'\n  NegEdgeBuffer32 irdof(clk, IR, IR_DOF);\n  ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:50: Operator NOT expects 32 bits on the LHS, but LHS\'s SEL generates 15 bits.\n                                                                           : ... In instance RISC\n  assign MbConstIM = CS ? (IR_DOF[14] ? ~IR_DOF[14:0]+1 : IR_DOF[14:0]) : IR_DOF[14:0];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:50: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 15 bits.\n                                                                           : ... In instance RISC\n  assign MbConstIM = CS ? (IR_DOF[14] ? ~IR_DOF[14:0]+1 : IR_DOF[14:0]) : IR_DOF[14:0];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:50: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 15 bits.\n                                                                           : ... In instance RISC\n  assign MbConstIM = CS ? (IR_DOF[14] ? ~IR_DOF[14:0]+1 : IR_DOF[14:0]) : IR_DOF[14:0];\n                        ^\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:51: Cannot find file containing module: \'InstructionDecoder\'\n  InstructionDecoder id1(IR_DOF, RW, MD, BS, PS, MW, FS, MA, MB, CS);\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:52: Cannot find file containing module: \'RegisterFile_32Bit\'\n  RegisterFile_32Bit RegFile(clk, RW_WB, RegA, RegB, DA_WB, MDOut, DecBusA, DecBusB);\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:54: Cannot find file containing module: \'MUX4\'\n  MUX4 mA({{HA},{MA}}, DecBusA, PC_DOF, MDOut2, 0, RAA);  \n  ^~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:55: Cannot find file containing module: \'MUX4\'\n  MUX4 mB({{HB},{MB}}, DecBusB, MbConstIM, MDOut2, 0, MBd);  \n  ^~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:72: Cannot find file containing module: \'MUX4\'\n  MUX4 mD2(MD_EX, FuncOut, MemDataOut, {{31\'b0000000000000000000000000000000},{N^V}}, 0, MDOut2);  \n  ^~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:77: Cannot find file containing module: \'NegEdgeBuffer32\'\n  NegEdgeBuffer32 pcex(clk, PC_DOF, PC_EX);\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:78: Cannot find file containing module: \'NegEdgeBuffer1\'\n  NegEdgeBuffer1  rwex(clk, RW, RW_EX);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:79: Cannot find file containing module: \'NegEdgeBuffer5\'\n  NegEdgeBuffer5  daex(clk, RegD, DA_EX);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:80: Cannot find file containing module: \'NegEdgeBuffer2\'\n  NegEdgeBuffer2  mdex(clk, MD, MD_EX);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:81: Cannot find file containing module: \'NegEdgeBuffer2\'\n  NegEdgeBuffer2  bsex(clk, BS, BS_EX);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:82: Cannot find file containing module: \'NegEdgeBuffer1\'\n  NegEdgeBuffer1  psex(clk, PS, PS_EX);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:83: Cannot find file containing module: \'NegEdgeBuffer1\'\n  NegEdgeBuffer1  mwex(clk, MW, MW_EX);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:84: Cannot find file containing module: \'NegEdgeBuffer5\'\n  NegEdgeBuffer5  fsex(clk, FS, FS_EX);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:85: Cannot find file containing module: \'NegEdgeBuffer5\'\n  NegEdgeBuffer5  shex(clk, SH, SH_EX);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:86: Cannot find file containing module: \'NegEdgeBuffer32\'\n  NegEdgeBuffer32 busaex(clk, RAA, RAA_EX);\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:87: Cannot find file containing module: \'NegEdgeBuffer32\'\n  NegEdgeBuffer32 busbex(clk, MBd, MBd_EX);\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:89: Cannot find file containing module: \'DataMemory32Bit\'\n  DataMemory32Bit DataMem(clk, MW_EX, RAA_EX, RAA_EX, MBd_EX, MemDataOut);\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:90: Cannot find file containing module: \'FunctionUnit\'\n  FunctionUnit fu1(RAA_EX, MBd_EX, FS_EX, SH_EX, C, N, V, Z, FuncOut);\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:91: Cannot find file containing module: \'Adder\'\n  Adder add1(PC_EX, MBd_EX, BrA);\n  ^~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:99: Cannot find file containing module: \'NegEdgeBuffer1\'\n  NegEdgeBuffer1  rwWB(clk, RW_EX, RW_WB);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:100: Cannot find file containing module: \'NegEdgeBuffer5\'\n  NegEdgeBuffer5  daWB(clk, DA_EX, DA_WB);  \n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:101: Cannot find file containing module: \'NegEdgeBuffer1\'\n  NegEdgeBuffer1  NVWB(clk, (N^V), NV_WB);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:102: Cannot find file containing module: \'NegEdgeBuffer32\'\n  NegEdgeBuffer32 FOWB(clk, FuncOut, FO_WB);\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:103: Cannot find file containing module: \'NegEdgeBuffer32\'\n  NegEdgeBuffer32 memWB(clk, MemDataOut, MEM_WB);\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:104: Cannot find file containing module: \'NegEdgeBuffer2\'\n  NegEdgeBuffer2  mdwb(clk, MD_EX, MD_WB);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC.v:106: Cannot find file containing module: \'MUX4\'\n  MUX4 mD(MD_WB, FO_WB, MEM_WB, {{31\'b0000000000000000000000000000000},{NV_WB}}, 0, MDOut);  \n  ^~~~\n%Error: Exiting due to 31 error(s), 6 warning(s)\n'
module RISC(input clk);


	wire [31:0] PC;
	wire [1:0] PCSelect;
	assign PCSelect = {{BS[0] & (BS[1] | (PS_EX^Z))}, {BS[1]}};
	MUX4 mC(PCSelect, PC_DOF, BrA, RAA_EX, BrA, PC);



	 wire [31:0] PC_IF, IR;
	 NegEdgeBuffer32 pcif(clk, PC, PC_IF);
	 
	 Instruction32BitMemory InstMem(clk, PC_IF, IR);
	 

	 wire [31:0] IR_DOF, PC_DOF, DecBusA, DecBusB, RAA, MBd, MbConstIM;
	 wire [4:0] RegA, RegB, RegD;
	 wire RW, PS, MW;
	 wire [1:0] BS, MD;
	 wire [4:0] FS, SH;
	 NegEdgeBuffer32 pcdof(clk, PC_IF+1, PC_DOF);
	 NegEdgeBuffer32 irdof(clk, IR, IR_DOF);
	 
	 assign RegA = IR_DOF[19:15];
	 assign RegB = IR_DOF[14:10];
	 assign RegD = IR_DOF[24:20];
	 
	 assign SH = IR[4:0];
	 assign MbConstIM = CS ? (IR_DOF[14] ? ~IR_DOF[14:0]+1 : IR_DOF[14:0]) : IR_DOF[14:0];
	 InstructionDecoder id1(IR_DOF, RW, MD, BS, PS, MW, FS, MA, MB, CS);
	 RegisterFile_32Bit RegFile(clk, RW_WB, RegA, RegB, DA_WB, MDOut, DecBusA, DecBusB);
	 
	 MUX4 mA({{HA},{MA}}, DecBusA, PC_DOF, MDOut2, 0, RAA);
	 MUX4 mB({{HB},{MB}}, DecBusB, MbConstIM, MDOut2, 0, MBd);
	 

	 wire [31:0] PC_EX, RAA_EX, MBd_EX, BrA;
	 wire [4:0] FS_EX, SH_EX, DA_EX;
	 wire [1:0] MD_EX, BS_EX;
	 wire RW_EX, MW_EX, PS_EX, Z, C, N, V;
	 wire [31:0] MemDataOut, FuncOut;
	 

	 wire CompBA_EX, CompAA_EX, HA, HB;
	 wire [31:0] MDOut2;
	 assign CompAA_EX = (RegA == DA_EX);
	 assign CompBA_EX = (RegB == DA_EX);
	 assign HA = CompAA_EX && ~MA && RW_EX;
	 assign HB = CompBA_EX && ~MB && RW_EX;
	 
	 MUX4 mD2(MD_EX, FuncOut, MemDataOut, {{31'b0000000000000000000000000000000},{N^V}}, 0, MDOut2);
	 
	 
	 

	 NegEdgeBuffer32 pcex(clk, PC_DOF, PC_EX);
	 NegEdgeBuffer1  rwex(clk, RW, RW_EX);
	 NegEdgeBuffer5  daex(clk, RegD, DA_EX);
	 NegEdgeBuffer2  mdex(clk, MD, MD_EX);
	 NegEdgeBuffer2  bsex(clk, BS, BS_EX);
	 NegEdgeBuffer1  psex(clk, PS, PS_EX);
	 NegEdgeBuffer1  mwex(clk, MW, MW_EX);
	 NegEdgeBuffer5  fsex(clk, FS, FS_EX);
	 NegEdgeBuffer5  shex(clk, SH, SH_EX);
	 NegEdgeBuffer32 busaex(clk, RAA, RAA_EX);
	 NegEdgeBuffer32 busbex(clk, MBd, MBd_EX);
	 
	 DataMemory32Bit DataMem(clk, MW_EX, RAA_EX, RAA_EX, MBd_EX, MemDataOut);
	 FunctionUnit fu1(RAA_EX, MBd_EX, FS_EX, SH_EX, C, N, V, Z, FuncOut);
	 Adder add1(PC_EX, MBd_EX, BrA);
	 

	 wire [31:0] FO_WB, MEM_WB;
	 wire [4:0] DA_WB;
	 wire [1:0] MD_WB;
	 wire RW_WB, NV_WB;
	 wire [31:0] MDOut;
	 NegEdgeBuffer1  rwWB(clk, RW_EX, RW_WB);
	 NegEdgeBuffer5  daWB(clk, DA_EX, DA_WB);
	 NegEdgeBuffer1  NVWB(clk, (N^V), NV_WB);
	 NegEdgeBuffer32 FOWB(clk, FuncOut, FO_WB);
	 NegEdgeBuffer32 memWB(clk, MemDataOut, MEM_WB);
	 NegEdgeBuffer2  mdwb(clk, MD_EX, MD_WB);
	 
	 MUX4 mD(MD_WB, FO_WB, MEM_WB, {{31'b0000000000000000000000000000000},{NV_WB}}, 0, MDOut);
	 
	 
	 
	 
	 
	 function [1:0] OneTo4;
		input ins;
		begin
			OneTo4 = {{1'b0},{ins}};
		end
	 endfunction
endmodule
module RISC(input clk);



	wire [31:0] PC;
	wire [1:0] PCSelect;
	assign PCSelect = {{BS[0] & (BS[1] | (PS_EX^Z))}, {BS[1]}};
	MUX4 mC(PCSelect, PC_DOF, BrA, RAA_EX, BrA, PC);



	 wire [31:0] PC_IF, IR;
	 NegEdgeBuffer32 pcif(clk, PC, PC_IF);
	 
	 Instruction32BitMemory InstMem(clk, PC_IF, IR);
	 

	 wire [31:0] IR_DOF, PC_DOF, DecBusA, DecBusB, RAA, MBd, MbConstIM;
	 wire [4:0] RegA, RegB, RegD;
	 wire RW, PS, MW;
	 wire [1:0] BS, MD;
	 wire [4:0] FS, SH;
	 NegEdgeBuffer32 pcdof(clk, PC_IF+1, PC_DOF);
	 NegEdgeBuffer32 irdof(clk, IR, IR_DOF);
	 
	 assign RegA = IR_DOF[19:15];
	 assign RegB = IR_DOF[14:10];
	 assign RegD = IR_DOF[24:20];
	 
	 assign SH = IR[4:0];
	 assign MbConstIM = CS ? (IR_DOF[14] ? ~IR_DOF[14:0]+1 : IR_DOF[14:0]) : IR_DOF[14:0];
	 InstructionDecoder id1(IR_DOF, RW, MD, BS, PS, MW, FS, MA, MB, CS);
	 RegisterFile_32Bit RegFile(clk, RW_WB, RegA, RegB, DA_WB, MDOut, DecBusA, DecBusB);
	 
	 MUX4 mA({{HA},{MA}}, DecBusA, PC_DOF, MDOut2, 0, RAA);
	 MUX4 mB({{HB},{MB}}, DecBusB, MbConstIM, MDOut2, 0, MBd);
	 

	 wire [31:0] PC_EX, RAA_EX, MBd_EX, BrA;
	 wire [4:0] FS_EX, SH_EX, DA_EX;
	 wire [1:0] MD_EX, BS_EX;
	 wire RW_EX, MW_EX, PS_EX, Z, C, N, V;
	 wire [31:0] MemDataOut, FuncOut;
	 

	 wire CompBA_EX, CompAA_EX, HA, HB;
	 wire [31:0] MDOut2;
	 assign CompAA_EX = (RegA == DA_EX);
	 assign CompBA_EX = (RegB == DA_EX);
	 assign HA = CompAA_EX && ~MA && RW_EX;
	 assign HB = CompBA_EX && ~MB && RW_EX;
	 
	 MUX4 mD2(MD_EX, FuncOut, MemDataOut, {{31'b0000000000000000000000000000000},{N^V}}, 0, MDOut2);
	 
	 
	 

	 NegEdgeBuffer32 pcex(clk, PC_DOF, PC_EX);
	 NegEdgeBuffer1  rwex(clk, RW, RW_EX);
	 NegEdgeBuffer5  daex(clk, RegD, DA_EX);
	 NegEdgeBuffer2  mdex(clk, MD, MD_EX);
	 NegEdgeBuffer2  bsex(clk, BS, BS_EX);
	 NegEdgeBuffer1  psex(clk, PS, PS_EX);
	 NegEdgeBuffer1  mwex(clk, MW, MW_EX);
	 NegEdgeBuffer5  fsex(clk, FS, FS_EX);
	 NegEdgeBuffer5  shex(clk, SH, SH_EX);
	 NegEdgeBuffer32 busaex(clk, RAA, RAA_EX);
	 NegEdgeBuffer32 busbex(clk, MBd, MBd_EX);
	 
	 DataMemory32Bit DataMem(clk, MW_EX, RAA_EX, RAA_EX, MBd_EX, MemDataOut);
	 FunctionUnit fu1(RAA_EX, MBd_EX, FS_EX, SH_EX, C, N, V, Z, FuncOut);
	 Adder add1(PC_EX, MBd_EX, BrA);
	 

	 wire [31:0] FO_WB, MEM_WB;
	 wire [4:0] DA_WB;
	 wire [1:0] MD_WB;
	 wire RW_WB, NV_WB;
	 wire [31:0] MDOut;
	 NegEdgeBuffer1  rwWB(clk, RW_EX, RW_WB);
	 NegEdgeBuffer5  daWB(clk, DA_EX, DA_WB);
	 NegEdgeBuffer1  NVWB(clk, (N^V), NV_WB);
	 NegEdgeBuffer32 FOWB(clk, FuncOut, FO_WB);
	 NegEdgeBuffer32 memWB(clk, MemDataOut, MEM_WB);
	 NegEdgeBuffer2  mdwb(clk, MD_EX, MD_WB);
	 
	 MUX4 mD(MD_WB, FO_WB, MEM_WB, {{31'b0000000000000000000000000000000},{NV_WB}}, 0, MDOut);
	 
	 
	 
	 
	 
	 function [1:0] OneTo4;
		input ins;
		begin
			OneTo4 = {{1'b0},{ins}};
		end
	 endfunction
endmodule