data/full_repos/permissive/144902498/source/rtl/mux_mem_dout.v
None: at end of input
1: b'%Error: data/full_repos/permissive/144902498/source/rtl/mux_mem_dout.v:3: Cannot find include file: buswidth.vh\n`include "buswidth.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/144902498/source/rtl,data/full_repos/permissive/144902498/buswidth.vh\n             data/full_repos/permissive/144902498/source/rtl,data/full_repos/permissive/144902498/buswidth.vh.v\n             data/full_repos/permissive/144902498/source/rtl,data/full_repos/permissive/144902498/buswidth.vh.sv\n             buswidth.vh\n             buswidth.vh.v\n             buswidth.vh.sv\n             obj_dir/buswidth.vh\n             obj_dir/buswidth.vh.v\n             obj_dir/buswidth.vh.sv\n%Error: data/full_repos/permissive/144902498/source/rtl/mux_mem_dout.v:6: Define or directive not defined: \'`MUX_MEM_DOUT_SEL_WIDTH\'\n    input [`MUX_MEM_DOUT_SEL_WIDTH-1:0] data_select,\n           ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module mux_mem_dout (
    input [`MUX_MEM_DOUT_SEL_WIDTH-1:0] data_select,
    input [15:0] reg_mem_dout,
    input [7:0] reg_mem_din_lo,
    input [15:0] reg_pc,
    input [7:0] regfile_out_8bit_a,
    input [15:0] regfile_out_16bit_a,
    output reg [7:0] data_out
);

localparam MUX_MEM_DOUT_IDX_REG_MEM_DOUT_HI        = 0;
localparam MUX_MEM_DOUT_IDX_REG_MEM_DIN_LO         = 1;
localparam MUX_MEM_DOUT_IDX_REG_PC_LO              = 2;
localparam MUX_MEM_DOUT_IDX_REG_PC_HI              = 3;
localparam MUX_MEM_DOUT_IDX_REGFILE_OUT_8BIT_A     = 4;
localparam MUX_MEM_DOUT_IDX_REGFILE_OUT_16BIT_A_LO = 5;

always @* begin
    data_out = reg_mem_dout[7:0];

    if (data_select[MUX_MEM_DOUT_IDX_REG_MEM_DOUT_HI])
        data_out = reg_mem_dout[15:8];
    if (data_select[MUX_MEM_DOUT_IDX_REG_MEM_DIN_LO])
        data_out = reg_mem_din_lo;
    if (data_select[MUX_MEM_DOUT_IDX_REG_PC_LO])
        data_out = reg_pc[7:0];
    if (data_select[MUX_MEM_DOUT_IDX_REG_PC_HI])
        data_out = reg_pc[15:8];
    if (data_select[MUX_MEM_DOUT_IDX_REGFILE_OUT_8BIT_A])
        data_out = regfile_out_8bit_a;
    if (data_select[MUX_MEM_DOUT_IDX_REGFILE_OUT_16BIT_A_LO])
        data_out = regfile_out_16bit_a[7:0];
end

endmodule
module mux_mem_dout (
    input [`MUX_MEM_DOUT_SEL_WIDTH-1:0] data_select,
    input [15:0] reg_mem_dout,
    input [7:0] reg_mem_din_lo,
    input [15:0] reg_pc,
    input [7:0] regfile_out_8bit_a,
    input [15:0] regfile_out_16bit_a,
    output reg [7:0] data_out
);


localparam MUX_MEM_DOUT_IDX_REG_MEM_DOUT_HI        = 0;
localparam MUX_MEM_DOUT_IDX_REG_MEM_DIN_LO         = 1;
localparam MUX_MEM_DOUT_IDX_REG_PC_LO              = 2;
localparam MUX_MEM_DOUT_IDX_REG_PC_HI              = 3;
localparam MUX_MEM_DOUT_IDX_REGFILE_OUT_8BIT_A     = 4;
localparam MUX_MEM_DOUT_IDX_REGFILE_OUT_16BIT_A_LO = 5;

always @* begin
    data_out = reg_mem_dout[7:0];

    if (data_select[MUX_MEM_DOUT_IDX_REG_MEM_DOUT_HI])
        data_out = reg_mem_dout[15:8];
    if (data_select[MUX_MEM_DOUT_IDX_REG_MEM_DIN_LO])
        data_out = reg_mem_din_lo;
    if (data_select[MUX_MEM_DOUT_IDX_REG_PC_LO])
        data_out = reg_pc[7:0];
    if (data_select[MUX_MEM_DOUT_IDX_REG_PC_HI])
        data_out = reg_pc[15:8];
    if (data_select[MUX_MEM_DOUT_IDX_REGFILE_OUT_8BIT_A])
        data_out = regfile_out_8bit_a;
    if (data_select[MUX_MEM_DOUT_IDX_REGFILE_OUT_16BIT_A_LO])
        data_out = regfile_out_16bit_a[7:0];
end

endmodule