data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/new/PC.v
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data/verilator_xmls/066b49eb-1495-4d8a-98f2-2ffd1392f177.xml
module PC(
	 clk,
	 reset,
	 input_pc,
	 output_pc,
	 PCWre
);
	 input wire[31:0] input_pc;
	 output reg[31:0] output_pc;
	 input clk, reset, PCWre;


	always@(posedge clk)begin
		if(reset == 0)begin
			output_pc = 0;
		end
		else if(!PCWre)begin
			output_pc = output_pc;
		end
		else if(PCWre)begin
			output_pc = input_pc;
		end
	end

endmodule
module PC(
	 clk,
	 reset,
	 input_pc,
	 output_pc,
	 PCWre
);

	 input wire[31:0] input_pc;
	 output reg[31:0] output_pc;
	 input clk, reset, PCWre;


	always@(posedge clk)begin
		if(reset == 0)begin
			output_pc = 0;
		end
		else if(!PCWre)begin
			output_pc = output_pc;
		end
		else if(PCWre)begin
			output_pc = input_pc;
		end
	end

endmodule