data/full_repos/permissive/182333580/software/ip/TERASIC_SEG7/TERASIC_SEG7.v
 line:118: before: "integer"
1: b'%Warning-WIDTH: data/full_repos/permissive/182333580/software/ip/TERASIC_SEG7/TERASIC_SEG7.v:128: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_address\' generates 3 bits.\n                                                                                                : ... In instance TERASIC_SEG7\n  base_index = s_address;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/182333580/software/ip/TERASIC_SEG7/TERASIC_SEG7.v:132: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'base_index\' generates 8 bits.\n                                                                                                : ... In instance TERASIC_SEG7\n   reg_file[base_index+j] = write_data[j];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/182333580/software/ip/TERASIC_SEG7/TERASIC_SEG7.v:138: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_address\' generates 3 bits.\n                                                                                                : ... In instance TERASIC_SEG7\n  base_index = s_address;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/182333580/software/ip/TERASIC_SEG7/TERASIC_SEG7.v:142: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'base_index\' generates 8 bits.\n                                                                                                : ... In instance TERASIC_SEG7\n   read_data[k] = reg_file[base_index+k];\n                                     ^\n%Error: Exiting due to 4 warning(s)\n'
module TERASIC_SEG7(	


					s_clk,
					s_address,
					s_read,
					s_readdata,
					s_write,
					s_writedata,
					s_reset,




					SEG7
				 );
				

parameter	SEG7_NUM		=   8;
parameter	ADDR_WIDTH		=	3;		
parameter	DEFAULT_ACTIVE  =   1;
parameter	LOW_ACTIVE  	=   1;











reg		[7:0]				base_index;
reg		[7:0]				write_data;
reg		[7:0]				read_data;
reg		[(SEG7_NUM*8-1):0]  reg_file;





input						s_clk;
input	[(ADDR_WIDTH-1):0]	s_address;
input						s_read;
output	[7:0]				s_readdata;
input						s_write;
input	[7:0]				s_writedata;
input						s_reset;




output	[(SEG7_NUM*8-1):0]  SEG7;





 
always @ (negedge s_clk)
begin
	
	if (s_reset)
	begin
		integer i;
		for(i=0;i<SEG7_NUM*8;i=i+1)
		begin
			reg_file[i] = (DEFAULT_ACTIVE)?1'b1:1'b0;
		end
	end
	else if (s_write)
	begin
		integer j;
		write_data = s_writedata;
		base_index = s_address;
		base_index = base_index << 3;
		for(j=0;j<8;j=j+1)
		begin
			reg_file[base_index+j] = write_data[j];
		end
	end
	else if (s_read)
	begin
		integer k;
		base_index = s_address;
		base_index = base_index << 3;
		for(k=0;k<8;k=k+1)
		begin
			read_data[k] = reg_file[base_index+k];
		end
	end	
end
 



assign SEG7 = (LOW_ACTIVE)?~reg_file:reg_file;
assign s_readdata = read_data;


endmodule
module TERASIC_SEG7(	


					s_clk,
					s_address,
					s_read,
					s_readdata,
					s_write,
					s_writedata,
					s_reset,




					SEG7
				 );

				

parameter	SEG7_NUM		=   8;
parameter	ADDR_WIDTH		=	3;		
parameter	DEFAULT_ACTIVE  =   1;
parameter	LOW_ACTIVE  	=   1;











reg		[7:0]				base_index;
reg		[7:0]				write_data;
reg		[7:0]				read_data;
reg		[(SEG7_NUM*8-1):0]  reg_file;





input						s_clk;
input	[(ADDR_WIDTH-1):0]	s_address;
input						s_read;
output	[7:0]				s_readdata;
input						s_write;
input	[7:0]				s_writedata;
input						s_reset;




output	[(SEG7_NUM*8-1):0]  SEG7;





 
always @ (negedge s_clk)
begin
	
	if (s_reset)
	begin
		integer i;
		for(i=0;i<SEG7_NUM*8;i=i+1)
		begin
			reg_file[i] = (DEFAULT_ACTIVE)?1'b1:1'b0;
		end
	end
	else if (s_write)
	begin
		integer j;
		write_data = s_writedata;
		base_index = s_address;
		base_index = base_index << 3;
		for(j=0;j<8;j=j+1)
		begin
			reg_file[base_index+j] = write_data[j];
		end
	end
	else if (s_read)
	begin
		integer k;
		base_index = s_address;
		base_index = base_index << 3;
		for(k=0;k<8;k=k+1)
		begin
			read_data[k] = reg_file[base_index+k];
		end
	end	
end
 



assign SEG7 = (LOW_ACTIVE)?~reg_file:reg_file;
assign s_readdata = read_data;


endmodule