data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v
 line:62: before: "("
1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:1: Cannot find include file: def.vh\n`include "def.vh" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.v\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.sv\n             def.vh\n             def.vh.v\n             def.vh.sv\n             obj_dir/def.vh\n             obj_dir/def.vh.v\n             obj_dir/def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:5: Define or directive not defined: \'`ERRC_BITDEF\'\n output [`ERRC_BITDEF] errno,\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:5: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n output [`ERRC_BITDEF] errno,\n                     ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:12: Define or directive not defined: \'`ERRC_BITDEF\'\n reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;\n                  ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:19: Define or directive not defined: \'`ERRC_NOERR\'\n   Rerrno <= `ERRC_NOERR; result <= Aresult;\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   Rerrno <= `ERRC_NOERR; result <= Aresult;\n                        ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:23: syntax error, unexpected always\n always @ (posedge clk or posedge rst) begin\n ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:28: Define or directive not defined: \'`ALUC_ADD\'\n    `ALUC_ADD: Treturn(ra + rb);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:29: Define or directive not defined: \'`ALUC_SUB\'\n    `ALUC_SUB: Treturn(ra - rb);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:30: Define or directive not defined: \'`ALUC_AND\'\n    `ALUC_AND: Treturn(ra & rb);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:31: Define or directive not defined: \'`ALUC_OR\'\n    `ALUC_OR: Treturn(ra | rb);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:32: Define or directive not defined: \'`ALUC_XOR\'\n    `ALUC_XOR: Treturn(ra ^ rb);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:33: Define or directive not defined: \'`ALUC_NOR\'\n    `ALUC_NOR: Treturn(~(ra | rb));\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:34: Define or directive not defined: \'`ALUC_SLL\'\n    `ALUC_SLL: Treturn(ra << shift_width);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:35: Define or directive not defined: \'`ALUC_SRL\'\n    `ALUC_SRL: Treturn(ra >> shift_width);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:36: Define or directive not defined: \'`ALUC_SRA\'\n    `ALUC_SRA: Treturn(ra >>> shift_width);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:37: Define or directive not defined: \'`ERRC_NOERR\'\n    31:   Rerrno <= `ERRC_NOERR;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/alu.v:38: Define or directive not defined: \'`ERRC_ILLAUX\'\n    default: Rerrno <= `ERRC_ILLAUX;\n                       ^~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module alu(
	input clk, input rst,
	output [`ERRC_BITDEF] errno,
	input [10:0] aux,
	input [31:0] ra,
	input [31:0] rb,
	output [31:0] rout
	);

	reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;
	reg [31:0] result;
	wire [4:0] shift_width = aux[10:6];
	wire [5:0] aux_type = aux[5:0];

	task Treturn(input [31:0] Aresult);
		begin
			Rerrno <= `ERRC_NOERR; result <= Aresult;
		end
	endtask

	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			Rerrno <= 0; result <= 0;
		end else begin
			case (aux_type)
				`ALUC_ADD:	Treturn(ra + rb);
				`ALUC_SUB:	Treturn(ra - rb);
				`ALUC_AND:	Treturn(ra & rb);
				`ALUC_OR:	Treturn(ra | rb);
				`ALUC_XOR:	Treturn(ra ^ rb);
				`ALUC_NOR:	Treturn(~(ra | rb));
				`ALUC_SLL:	Treturn(ra << shift_width);
				`ALUC_SRL:	Treturn(ra >> shift_width);
				`ALUC_SRA:	Treturn(ra >>> shift_width);
				31:			Rerrno <= `ERRC_NOERR;
				default:	Rerrno <= `ERRC_ILLAUX;
			endcase
		end
	end

	assign rout = result;
endmodule
module alu(
	input clk, input rst,
	output [`ERRC_BITDEF] errno,
	input [10:0] aux,
	input [31:0] ra,
	input [31:0] rb,
	output [31:0] rout
	);


	reg [`ERRC_BITDEF] Rerrno; assign errno = Rerrno;
	reg [31:0] result;
	wire [4:0] shift_width = aux[10:6];
	wire [5:0] aux_type = aux[5:0];

	task Treturn(input [31:0] Aresult);
		begin
			Rerrno <= `ERRC_NOERR; result <= Aresult;
		end
	endtask

	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			Rerrno <= 0; result <= 0;
		end else begin
			case (aux_type)
				`ALUC_ADD:	Treturn(ra + rb);
				`ALUC_SUB:	Treturn(ra - rb);
				`ALUC_AND:	Treturn(ra & rb);
				`ALUC_OR:	Treturn(ra | rb);
				`ALUC_XOR:	Treturn(ra ^ rb);
				`ALUC_NOR:	Treturn(~(ra | rb));
				`ALUC_SLL:	Treturn(ra << shift_width);
				`ALUC_SRL:	Treturn(ra >> shift_width);
				`ALUC_SRA:	Treturn(ra >>> shift_width);
				31:			Rerrno <= `ERRC_NOERR;
				default:	Rerrno <= `ERRC_ILLAUX;
			endcase
		end
	end

	assign rout = result;
endmodule