data/full_repos/permissive/121451239/final.v
 line:36: before: ","
1: b"%Error: data/full_repos/permissive/121451239/final.v:18: Cannot find file containing module: 'mux2v'\n  mux2v #(13) start_mux(start_mux_to_reg, start_num, mul_div_mux_out, start);   \n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/121451239,data/full_repos/permissive/121451239/mux2v\n             data/full_repos/permissive/121451239,data/full_repos/permissive/121451239/mux2v.v\n             data/full_repos/permissive/121451239,data/full_repos/permissive/121451239/mux2v.sv\n             mux2v\n             mux2v.v\n             mux2v.sv\n             obj_dir/mux2v\n             obj_dir/mux2v.v\n             obj_dir/mux2v.sv\n%Error: data/full_repos/permissive/121451239/final.v:19: Cannot find file containing module: 'register'\n  register #(13) main_reg(reg_out, start_mux_to_reg, reg_clock, reg_enable, reset);   \n  ^~~~~~~~\n%Error: data/full_repos/permissive/121451239/final.v:20: Cannot find file containing module: 'mux2v'\n  mux2v #(13) BCDtoLED_mux(BCDtoLED_out, start_num, reg_out, start);   \n  ^~~~~\n%Error: data/full_repos/permissive/121451239/final.v:21: Cannot find file containing module: 'enable_bit_selector'\n  enable_bit_selector ebs(reg_enable, reg_out, pause);   \n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121451239/final.v:27: Cannot find file containing module: 'adder'\n  adder add1(add_out1, reg_out, reg_out);\n  ^~~~~\n%Error: data/full_repos/permissive/121451239/final.v:28: Cannot find file containing module: 'adder'\n  adder add2(add_out2, add_out1, reg_out);\n  ^~~~~\n%Error: data/full_repos/permissive/121451239/final.v:29: Cannot find file containing module: 'adder'\n  adder add3(add_out, add_out2, 13'b1);\n  ^~~~~\n%Error: data/full_repos/permissive/121451239/final.v:32: Cannot find file containing module: 'mux2v'\n  mux2v #(13) mul_div_mux(mul_div_mux_out, divide, add_out, reg_out[0]);\n  ^~~~~\n%Error: data/full_repos/permissive/121451239/final.v:36: Cannot find file containing module: 'DecimalDigitDecoder'\n  DecimalDigitDecoder ddd(binary, , thousands, hundreds, tens, ones);\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121451239/final.v:37: Cannot find file containing module: 'BCDToLED'\n  BCDToLED ones_BTL(ones, seg1);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/121451239/final.v:38: Cannot find file containing module: 'BCDToLED'\n  BCDToLED tens_BTL(tens, seg2);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/121451239/final.v:39: Cannot find file containing module: 'BCDToLED'\n  BCDToLED hundreds_BTL(hundreds, seg3);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/121451239/final.v:40: Cannot find file containing module: 'BCDToLED'\n  BCDToLED thousands_BTL(thousands, seg4);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/121451239/final.v:48: Cannot find file containing module: 'clk_wiz'\n  clk_wiz clock1(clk, clk_out);   \n  ^~~~~~~\n%Error: data/full_repos/permissive/121451239/final.v:49: Cannot find file containing module: 'clock_divider'\n  clock_divider clock2(clk_out, clock_out);   \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121451239/final.v:50: Cannot find file containing module: 'clock_divider'\n  clock_divider #(1) clock3(clock_out, sec_clock_out);   \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121451239/final.v:51: Cannot find file containing module: 'clock_divider'\n  clock_divider #(250) clock4(clock_out, reg_clock);  \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121451239/final.v:54: Cannot find file containing module: 'mux4v'\n  mux4v #(7) seg_mux(seg, seg1, seg2, seg3, seg4, select);\n  ^~~~~\n%Error: data/full_repos/permissive/121451239/final.v:55: Cannot find file containing module: 'mux4v'\n  mux4v #(4) an_mux(an, an1, an2, an3, an4, select);\n  ^~~~~\n%Error: Exiting due to 19 error(s)\n"
module collatz_conjecture(
  input [15:0] sw,
  input clk,
  output [6:0] seg,
  output [3:0] an
  );

  wire reg_enable, clk_out, clock_out, sec_clock_out, reg_clock;
  wire [12:0] reg_out, start_mux_to_reg, BCDtoLED_out, add_out1, add_out2, add_out, mul_div_mux_out;
  wire [6:0] seg1, seg2, seg3, seg4;
  wire [3:0] ones, tens, hundreds, thousands;

  wire start = sw[15];
  wire pause = sw[14];
  wire reset = sw[13];
  wire [12:0] start_num = sw[12:0];

  mux2v #(13) start_mux(start_mux_to_reg, start_num, mul_div_mux_out, start);
  register #(13) main_reg(reg_out, start_mux_to_reg, reg_clock, reg_enable, reset);
  mux2v #(13) BCDtoLED_mux(BCDtoLED_out, start_num, reg_out, start);
  enable_bit_selector ebs(reg_enable, reg_out, pause);


  wire [12:0] divide = {1'b0, reg_out[12:1]};


  adder add1(add_out1, reg_out, reg_out);
  adder add2(add_out2, add_out1, reg_out);
  adder add3(add_out, add_out2, 13'b1);


  mux2v #(13) mul_div_mux(mul_div_mux_out, divide, add_out, reg_out[0]);


  wire [15:0] binary = {3'b0, BCDtoLED_out};
  DecimalDigitDecoder ddd(binary, , thousands, hundreds, tens, ones);
  BCDToLED ones_BTL(ones, seg1);
  BCDToLED tens_BTL(tens, seg2);
  BCDToLED hundreds_BTL(hundreds, seg3);
  BCDToLED thousands_BTL(thousands, seg4);


  wire [3:0] an1 = 4'b1110;
  wire [3:0] an2 = 4'b1101;
  wire [3:0] an3 = 4'b1011;
  wire [3:0] an4 = 4'b0111;
  
  clk_wiz clock1(clk, clk_out);
  clock_divider clock2(clk_out, clock_out);
  clock_divider #(1) clock3(clock_out, sec_clock_out);
  clock_divider #(250) clock4(clock_out, reg_clock);
  
  wire [1:0] select = {clock_out, sec_clock_out};
  mux4v #(7) seg_mux(seg, seg1, seg2, seg3, seg4, select);
  mux4v #(4) an_mux(an, an1, an2, an3, an4, select);

endmodule
module collatz_conjecture(
  input [15:0] sw,
  input clk,
  output [6:0] seg,
  output [3:0] an
  );


  wire reg_enable, clk_out, clock_out, sec_clock_out, reg_clock;
  wire [12:0] reg_out, start_mux_to_reg, BCDtoLED_out, add_out1, add_out2, add_out, mul_div_mux_out;
  wire [6:0] seg1, seg2, seg3, seg4;
  wire [3:0] ones, tens, hundreds, thousands;

  wire start = sw[15];
  wire pause = sw[14];
  wire reset = sw[13];
  wire [12:0] start_num = sw[12:0];

  mux2v #(13) start_mux(start_mux_to_reg, start_num, mul_div_mux_out, start);
  register #(13) main_reg(reg_out, start_mux_to_reg, reg_clock, reg_enable, reset);
  mux2v #(13) BCDtoLED_mux(BCDtoLED_out, start_num, reg_out, start);
  enable_bit_selector ebs(reg_enable, reg_out, pause);


  wire [12:0] divide = {1'b0, reg_out[12:1]};


  adder add1(add_out1, reg_out, reg_out);
  adder add2(add_out2, add_out1, reg_out);
  adder add3(add_out, add_out2, 13'b1);


  mux2v #(13) mul_div_mux(mul_div_mux_out, divide, add_out, reg_out[0]);


  wire [15:0] binary = {3'b0, BCDtoLED_out};
  DecimalDigitDecoder ddd(binary, , thousands, hundreds, tens, ones);
  BCDToLED ones_BTL(ones, seg1);
  BCDToLED tens_BTL(tens, seg2);
  BCDToLED hundreds_BTL(hundreds, seg3);
  BCDToLED thousands_BTL(thousands, seg4);


  wire [3:0] an1 = 4'b1110;
  wire [3:0] an2 = 4'b1101;
  wire [3:0] an3 = 4'b1011;
  wire [3:0] an4 = 4'b0111;
  
  clk_wiz clock1(clk, clk_out);
  clock_divider clock2(clk_out, clock_out);
  clock_divider #(1) clock3(clock_out, sec_clock_out);
  clock_divider #(250) clock4(clock_out, reg_clock);
  
  wire [1:0] select = {clock_out, sec_clock_out};
  mux4v #(7) seg_mux(seg, seg1, seg2, seg3, seg4, select);
  mux4v #(4) an_mux(an, an1, an2, an3, an4, select);

endmodule