data/full_repos/permissive/203526788/IceStick/ADC/top.v
 line:72: before: "="
1: b'%Error: data/full_repos/permissive/203526788/IceStick/ADC/top.v:1: Cannot find include file: async.v\n`include "async.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203526788/IceStick/ADC,data/full_repos/permissive/203526788/async.v\n             data/full_repos/permissive/203526788/IceStick/ADC,data/full_repos/permissive/203526788/async.v.v\n             data/full_repos/permissive/203526788/IceStick/ADC,data/full_repos/permissive/203526788/async.v.sv\n             async.v\n             async.v.v\n             async.v.sv\n             obj_dir/async.v\n             obj_dir/async.v.v\n             obj_dir/async.v.sv\n%Error: Exiting due to 1 error(s)\n'
module top(input wire CLK_IN,
		   input wire [5:0] J3,
		   output wire CLK_2,
		   output wire [4:0] LED,
		   output wire TX);

	parameter ClkFrequency = 12000000;
	parameter Baud = 115200;


	CLK_GEN #(.FREQ(1000)) sampler (CLK_IN, CLK_2);
	assign LED= J3[4:0];

	wire ready;
	assign ready = J3[5];


	async_transmitter #(ClkFrequency, Baud) TXD(.clk(CLK_IN), .TxD(TX), .TxD_start(ready), .TxD_data({3'b000, J3[4:0]}));
	

endmodule
module top(input wire CLK_IN,
		   input wire [5:0] J3,
		   output wire CLK_2,
		   output wire [4:0] LED,
		   output wire TX);


	parameter ClkFrequency = 12000000;
	parameter Baud = 115200;


	CLK_GEN #(.FREQ(1000)) sampler (CLK_IN, CLK_2);
	assign LED= J3[4:0];

	wire ready;
	assign ready = J3[5];


	async_transmitter #(ClkFrequency, Baud) TXD(.clk(CLK_IN), .TxD(TX), .TxD_start(ready), .TxD_data({3'b000, J3[4:0]}));
	

endmodule