data/full_repos/permissive/163494071/count_num/example2/example2.v
data/verilator_xmls/146e4215-73e1-429a-a47a-b7d66c5c05bf.xml
module example2(clk,key,led);
	input clk;
	input key;
	output reg led;
	wire key_1;
	
	always @(posedge clk)
		begin
		if(key_1==1)
		led<=1'b1;
		else
		led<=1'b0;
	end
	key_fangdou u1(.clk(clk),.key_in(key),.key_out(key_1));
endmodule
module example2(clk,key,led);

	input clk;
	input key;
	output reg led;
	wire key_1;
	
	always @(posedge clk)
		begin
		if(key_1==1)
		led<=1'b1;
		else
		led<=1'b0;
	end
	key_fangdou u1(.clk(clk),.key_in(key),.key_out(key_1));
endmodule