data/full_repos/permissive/134057391/2018_cpu/code/rtl/ff_07.v
data/verilator_xmls/faf71a31-0f9e-46c3-a5c3-252df210689a.xml
module ff_07(
    input clk,
    input reset,
    input d,
    output reg qa,
    output reg qs
    );


            


endmodule
module ff_07(
    input clk,
    input reset,
    input d,
    output reg qa,
    output reg qs
    );



            


endmodule