data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv
 line:77: before: "unsigned"
1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:23: Cannot find file containing module: 'sync_edetect'\nsync_edetect sd(CLK, RX, rx_s, any_edge, neg_edge);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect.v\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/sync_edetect.sv\n             sync_edetect\n             sync_edetect.v\n             sync_edetect.sv\n             obj_dir/sync_edetect\n             obj_dir/sync_edetect.v\n             obj_dir/sync_edetect.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:33: Cannot find file containing module: 'counter'\ncounter #(16) bit_time_cnt(CLK, cnt_reset, count_en, bit_cnt_q );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:36: Cannot find file containing module: 'counter'\ncounter #(3) byte_cnt(CLK, resync, shift_bit, byte_cnt_q );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:38: Cannot find file containing module: 'shift_in_reg_right'\nshift_in_reg_right #(8) sr( CLK, resync, shift_bit, rx_s, DATA );\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_rx.sv:41: Cannot find file containing module: 'ffd'\nffd #(1) parity_fd(CLK, RESET, resync | shift_bit_p, par_fd_in, par_fd_q);\n^~~\n%Error: Exiting due to 5 error(s)\n"
module uart_rx ( input        CLK,
                 input        RESET,
                 
                 input [15:0] BIT_TIME,
                 input        PARITY_EN,
                 input        PARITY_ODD,                

                 output [7:0] DATA,
                 output       EN,
                 output       PARITY_ERR,
                 output       IDLE,
                
                 input        RX );

logic any_edge, neg_edge, count_en, half_period, full_period,
      byte_done, data_bit, dp_bit, start_bit, cnt_reset, resync,
      par_fd_in, par_fd_q, shift_bit, shift_bit_p, rx_s;

logic [15:0] bit_cnt_q;
logic  [2:0] byte_cnt_q;

sync_edetect sd(CLK, RX, rx_s, any_edge, neg_edge);

assign resync      = (half_period & start_bit);
assign shift_bit   = (full_period & data_bit);
assign shift_bit_p = (full_period & dp_bit);

assign half_period = (bit_cnt_q == {1'b0, BIT_TIME[15:1]});
assign full_period = (bit_cnt_q == BIT_TIME);
assign cnt_reset = ~count_en | resync | shift_bit_p;

counter #(16) bit_time_cnt(CLK, cnt_reset, count_en, bit_cnt_q );

assign byte_done = (byte_cnt_q == 3'd7);
counter #(3) byte_cnt(CLK, resync, shift_bit, byte_cnt_q );

shift_in_reg_right #(8) sr( CLK, resync, shift_bit, rx_s, DATA );

assign par_fd_in = resync ? PARITY_ODD : (par_fd_q ^ rx_s);
ffd #(1) parity_fd(CLK, RESET, resync | shift_bit_p, par_fd_in, par_fd_q);

uart_rx_fsm fsm( .CLK         ( CLK         ),
                 .RESET       ( RESET       ),
                 .NEG_EDGE    ( neg_edge    ),
                 .ANY_EDGE    ( any_edge    ),
                 .HALF_PERIOD ( half_period ),
                 .FULL_PERIOD ( full_period ),
                 .BYTE_DONE   ( byte_done   ),
                 .PARITY_EN   ( PARITY_EN   ),
                 .COUNT_EN    ( count_en    ),
                 .START_BIT   ( start_bit   ),
                 .DATA_BIT    ( data_bit    ),
                 .DP_BIT      ( dp_bit      ),
                 .DONE        ( EN          ),
                 .READY       ( IDLE        ) );

assign PARITY_ERR = par_fd_q & EN;

endmodule
module uart_rx ( input        CLK,
                 input        RESET,
                 
                 input [15:0] BIT_TIME,
                 input        PARITY_EN,
                 input        PARITY_ODD,                

                 output [7:0] DATA,
                 output       EN,
                 output       PARITY_ERR,
                 output       IDLE,
                
                 input        RX );


logic any_edge, neg_edge, count_en, half_period, full_period,
      byte_done, data_bit, dp_bit, start_bit, cnt_reset, resync,
      par_fd_in, par_fd_q, shift_bit, shift_bit_p, rx_s;

logic [15:0] bit_cnt_q;
logic  [2:0] byte_cnt_q;

sync_edetect sd(CLK, RX, rx_s, any_edge, neg_edge);

assign resync      = (half_period & start_bit);
assign shift_bit   = (full_period & data_bit);
assign shift_bit_p = (full_period & dp_bit);

assign half_period = (bit_cnt_q == {1'b0, BIT_TIME[15:1]});
assign full_period = (bit_cnt_q == BIT_TIME);
assign cnt_reset = ~count_en | resync | shift_bit_p;

counter #(16) bit_time_cnt(CLK, cnt_reset, count_en, bit_cnt_q );

assign byte_done = (byte_cnt_q == 3'd7);
counter #(3) byte_cnt(CLK, resync, shift_bit, byte_cnt_q );

shift_in_reg_right #(8) sr( CLK, resync, shift_bit, rx_s, DATA );

assign par_fd_in = resync ? PARITY_ODD : (par_fd_q ^ rx_s);
ffd #(1) parity_fd(CLK, RESET, resync | shift_bit_p, par_fd_in, par_fd_q);

uart_rx_fsm fsm( .CLK         ( CLK         ),
                 .RESET       ( RESET       ),
                 .NEG_EDGE    ( neg_edge    ),
                 .ANY_EDGE    ( any_edge    ),
                 .HALF_PERIOD ( half_period ),
                 .FULL_PERIOD ( full_period ),
                 .BYTE_DONE   ( byte_done   ),
                 .PARITY_EN   ( PARITY_EN   ),
                 .COUNT_EN    ( count_en    ),
                 .START_BIT   ( start_bit   ),
                 .DATA_BIT    ( data_bit    ),
                 .DP_BIT      ( dp_bit      ),
                 .DONE        ( EN          ),
                 .READY       ( IDLE        ) );

assign PARITY_ERR = par_fd_q & EN;

endmodule