data/full_repos/permissive/159479522/bin27seg.v
data/verilator_xmls/60a8ebd8-7a0b-46a8-8aa9-502a716f258b.xml
module bin27seg (data_in ,data_out );
input  wire [3:0] data_in ;
output reg  [7:0] data_out ;

always @(data_in)   
    begin
       case (data_in )
       0: data_out<= 8'b11000000;
       1: data_out<= 8'b11111001;
       2: data_out<= 8'b10100100;
       3: data_out<= 8'b10110000;
       4: data_out<= 8'b10011001;
       5: data_out<= 8'b10010010;
       6: data_out<= 8'b10000010;
       7: data_out<= 8'b11111000;
       8: data_out<= 8'b10000000;
       9: data_out<= 8'b10010000;
       default:data_out<= 8'b10111111; 
       endcase
  end
endmodule
module bin27seg (data_in ,data_out );

input  wire [3:0] data_in ;
output reg  [7:0] data_out ;

always @(data_in)   
    begin
       case (data_in )
       0: data_out<= 8'b11000000;
       1: data_out<= 8'b11111001;
       2: data_out<= 8'b10100100;
       3: data_out<= 8'b10110000;
       4: data_out<= 8'b10011001;
       5: data_out<= 8'b10010010;
       6: data_out<= 8'b10000010;
       7: data_out<= 8'b11111000;
       8: data_out<= 8'b10000000;
       9: data_out<= 8'b10010000;
       default:data_out<= 8'b10111111; 
       endcase
  end
endmodule