data/full_repos/permissive/143278/ivltests/contrib8.5.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/contrib8.5.v:31: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/contrib8.5.v:36: Unsupported: Ignoring delay on this delayed statement.\n          #1 ;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/contrib8.5.v:54: Unsupported: Ignoring delay on this delayed statement.\n          #1 ;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/contrib8.5.v:37: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'a\' generates 8 bits.\n                                                                          : ... In instance main\n          if(a)\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/contrib8.5.v:45: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                          : ... In instance main\n          if(!a)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/contrib8.5.v:55: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                          : ... In instance main\n          if(!a)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/contrib8.5.v:63: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'a\' generates 8 bits.\n                                                                          : ... In instance main\n          if(a)\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/contrib8.5.v:77: Operator XOR expects 8 bits on the RHS, but RHS\'s VARREF \'b\' generates 1 bits.\n                                                                          : ... In instance main\n   c <= a ^ b;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/contrib8.5.v:77: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s XOR generates 8 bits.\n                                                                          : ... In instance main\n   c <= a ^ b;\n     ^~\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
reg [7:0] a;
reg b;
reg c;
reg error;

initial
  begin
   #1;
    error = 0;
     for(a = 0; a <= 8'h1; a = a + 1)
       begin
          b = 0;
          #1 ;
          if(a)
            begin
              if(!c)
                begin
                  $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
                  error = 1;
                end
            end
          if(!a)
            begin
              if(c)
                begin
                  $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
                  error = 1;
                end
            end
          b = 1;
          #1 ;
          if(!a)
            begin
              if(!c)
                begin
                  $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
                  error = 1;
                end
            end
          if(a)
            begin
              if(c)
                begin
                  $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
                  error = 1;
                end
            end
       end
    if(!error)
       $display("PASSED");
  end

always @(a or b)
   c <= a ^ b;
endmodule
module main;

reg [7:0] a;
reg b;
reg c;
reg error;

initial
  begin
   #1;
    error = 0;
     for(a = 0; a <= 8'h1; a = a + 1)
       begin
          b = 0;
          #1 ;
          if(a)
            begin
              if(!c)
                begin
                  $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
                  error = 1;
                end
            end
          if(!a)
            begin
              if(c)
                begin
                  $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
                  error = 1;
                end
            end
          b = 1;
          #1 ;
          if(!a)
            begin
              if(!c)
                begin
                  $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
                  error = 1;
                end
            end
          if(a)
            begin
              if(c)
                begin
                  $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c);
                  error = 1;
                end
            end
       end
    if(!error)
       $display("PASSED");
  end

always @(a or b)
   c <= a ^ b;
endmodule