data/full_repos/permissive/146618947/mux_21/mux_tester.v
 line:29: before: "("
1: b'%Error: data/full_repos/permissive/146618947/mux_21/mux_tester.v:14: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("mux.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/mux_21/mux_tester.v:15: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/mux_21/mux_tester.v:25: syntax error, unexpected \'@\'\n      @ (posedge clk);\n      ^\n%Error: data/full_repos/permissive/146618947/mux_21/mux_tester.v:30: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/mux_21/mux_tester.v:44: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/146618947/mux_21/mux_tester.v:56: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/mux_21/mux_tester.v:66: Unsupported: Ignoring delay on this delayed statement.\n   always #2 clk <= ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 6 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_tester (
                   output reg clk,
                   output reg reset,
                   output reg selector,
                   output reg data_0,
                   output reg data_1,
                   input      data_out
                   );

   reg                        counter;

   initial begin
      $dumpfile("mux.vcd");
      $dumpvars;
      data_0 <= 1'b0;
      data_1 <= 1'b1;
      reset <= 1'b1;
      selector <= 1'b0;


      counter <= 'b0;


      @ (posedge clk);
      reset <= 1'b0;


      repeat (8) begin
         @(posedge clk);
         counter = ~counter;

         if (counter == 'b1) begin
            data_0 = ~data_0;
            data_1 = ~data_1;
            selector = ~selector;
         end
      end

      data_0 = ~data_0;


      repeat (8) begin
         @(posedge clk);
         counter = ~counter;

         if (counter == 'b1) begin
            data_0 = ~data_0;
            data_1 = ~data_1;
            selector = ~selector;
         end

      end


      @(posedge clk);
      data_0 = 'b0;
      data_1 = 'b0;

      $finish;

   end

   initial clk <= 0;

   always #2 clk <= ~clk;

endmodule
module mux_tester (
                   output reg clk,
                   output reg reset,
                   output reg selector,
                   output reg data_0,
                   output reg data_1,
                   input      data_out
                   );


   reg                        counter;

   initial begin
      $dumpfile("mux.vcd");
      $dumpvars;
      data_0 <= 1'b0;
      data_1 <= 1'b1;
      reset <= 1'b1;
      selector <= 1'b0;


      counter <= 'b0;


      @ (posedge clk);
      reset <= 1'b0;


      repeat (8) begin
         @(posedge clk);
         counter = ~counter;

         if (counter == 'b1) begin
            data_0 = ~data_0;
            data_1 = ~data_1;
            selector = ~selector;
         end
      end

      data_0 = ~data_0;


      repeat (8) begin
         @(posedge clk);
         counter = ~counter;

         if (counter == 'b1) begin
            data_0 = ~data_0;
            data_1 = ~data_1;
            selector = ~selector;
         end

      end


      @(posedge clk);
      data_0 = 'b0;
      data_1 = 'b0;

      $finish;

   end

   initial clk <= 0;

   always #2 clk <= ~clk;

endmodule