data/full_repos/permissive/102821975/Processor/DataMemory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/102821975/Processor/DataMemory.v:27: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'DataIn\' generates 32 bits.\n                                                                              : ... In instance DataMemory\n   Memory[MemoryAddress]=DataIn;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module DataMemory(clk,Reset,MemoryAddress,memWD,memRD,DataOut,DataIn);
	output reg [31:0] DataOut;
	input [31:0] MemoryAddress,DataIn;
   input memRD, memWD,Reset,clk;
	
	
	
	reg [6:0] Memory [0:60348];
	
	
	
	initial begin
		DataOut=32'd0;
		$readmemb("text.txt",Memory);

 	end
	
	
	always @ (posedge clk)begin
		if (memRD)begin
			DataOut[6:0]=Memory[MemoryAddress];
			DataOut[31:7]=25'd0;
		end
		else if (memWD)begin
			Memory[MemoryAddress]=DataIn;
			DataOut=32'd0;
		end
		else  DataOut=MemoryAddress;

	end
endmodule
module DataMemory(clk,Reset,MemoryAddress,memWD,memRD,DataOut,DataIn);

	output reg [31:0] DataOut;
	input [31:0] MemoryAddress,DataIn;
   input memRD, memWD,Reset,clk;
	
	
	
	reg [6:0] Memory [0:60348];
	
	
	
	initial begin
		DataOut=32'd0;
		$readmemb("text.txt",Memory);

 	end
	
	
	always @ (posedge clk)begin
		if (memRD)begin
			DataOut[6:0]=Memory[MemoryAddress];
			DataOut[31:7]=25'd0;
		end
		else if (memWD)begin
			Memory[MemoryAddress]=DataIn;
			DataOut=32'd0;
		end
		else  DataOut=MemoryAddress;

	end
endmodule