data/full_repos/permissive/143286506/Ver2/fetch.v
 line:9: before: "/"
data/verilator_xmls/780cb8e4-e21a-42e0-915a-c8e7de6b167c.xml
module fetch(
  pc,
  ins
);
input [31:0] pc;
output [31:0] ins;
reg [31:0] ins_mem [0:255];
assign ins = ins_mem[pc]; 
endmodule
module fetch(
  pc,
  ins
);

input [31:0] pc;
output [31:0] ins;
reg [31:0] ins_mem [0:255];
assign ins = ins_mem[pc]; 
endmodule