data/full_repos/permissive/135475029/lab_8/src/DataMemory.v
None: at end of input
data/verilator_xmls/9ab7f6a7-c9ac-4d2d-9854-be150dfc9b91.xml
module DataMemory(
  input         CLK,
  input   [5:0] A,
	input         WE,
  input  [31:0] WD,
	output [31:0] RD
);

  reg [31:0] DataArr [63:0];

  initial
    begin
      $readmemh("datamem_h.txt", DataArr);
    end

	assign RD = DataArr[A];

  always @(posedge CLK)
	  begin
	    if(WE)
		    DataArr[A] <= WD;
		  end

endmodule
module DataMemory(
  input         CLK,
  input   [5:0] A,
	input         WE,
  input  [31:0] WD,
	output [31:0] RD
);


  reg [31:0] DataArr [63:0];

  initial
    begin
      $readmemh("datamem_h.txt", DataArr);
    end

	assign RD = DataArr[A];

  always @(posedge CLK)
	  begin
	    if(WE)
		    DataArr[A] <= WD;
		  end

endmodule