data/full_repos/permissive/122497324/assignment_4/assignment_4.v
 line:593: before: "("
1: b'%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:238: Cell has missing pin: \'store_mux_stall\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b010)) FP_add_station\n                                                    ^~~~~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:238: Cell has missing pin: \'trigger_exes\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b010)) FP_add_station\n                                                    ^~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:238: Cell has missing pin: \'memory_offset_out\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b010)) FP_add_station\n                                                    ^~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:238: Cell has missing pin: \'valid_data\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b010)) FP_add_station\n                                                    ^~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:254: Cell has missing pin: \'store_mux_stall\'\n  reservation_station #(.BUS_LENGTH(1),.ID(3\'b001)) FP_mult_station\n                                                    ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:254: Cell has missing pin: \'trigger_exes\'\n  reservation_station #(.BUS_LENGTH(1),.ID(3\'b001)) FP_mult_station\n                                                    ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:254: Cell has missing pin: \'memory_offset_out\'\n  reservation_station #(.BUS_LENGTH(1),.ID(3\'b001)) FP_mult_station\n                                                    ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:254: Cell has missing pin: \'valid_data\'\n  reservation_station #(.BUS_LENGTH(1),.ID(3\'b001)) FP_mult_station\n                                                    ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:270: Cell has missing pin: \'trigger_exes\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b011)) store_station\n                                                    ^~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:286: Cell has missing pin: \'store_mux_stall\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b100)) load_station\n                                                    ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:315: Cell has missing pin: \'bbus_data_in\'\n  execution_unit #(.CYCLE_TIME(2),.ID(2\'b11)) load_store_unit\n                                              ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:315: Cell has missing pin: \'fake_clock\'\n  execution_unit #(.CYCLE_TIME(2),.ID(2\'b11)) load_store_unit\n                                              ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'offset_in\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'memory_in\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'store_dbus_data_in\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'fake_clock\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'memory_address\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'memory_out\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'op_code_out\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'offset_in\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'memory_in\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'store_dbus_data_in\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'memory_address\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'memory_out\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'op_code_out\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:962: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 31 bits.\n                                                                                    : ... In instance assignment_4.load_store_unit\n    memory_address = 31\'bz;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:1007: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'offset_in\' generates 3 bits.\n                                                                                     : ... In instance assignment_4.load_store_unit\n              memory_address = abus_data_in + offset_in;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:1014: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'offset_in\' generates 3 bits.\n                                                                                     : ... In instance assignment_4.load_store_unit\n              memory_address = abus_data_in + offset_in;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:583: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'bzzzzzzzz\' generates 8 bits.\n                                                                                    : ... In instance assignment_4.FP_add_station\n    d_select_out = 8\'bz;\n                 ^\n%Warning-UNSIGNED: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:463: Comparison is constant due to unsigned arithmetic\n                                                                                       : ... In instance assignment_4\n    if((memory_address >= 0) && (load_store > 3\'b000)) begin\n                       ^~\n%Error: Exiting due to 30 warning(s)\n'
module assignment_4(reset,clk,ibus,iaddrbus,databus,daddrbus);




  input reset;



  input [11:0] ibus;


  output [31:0] iaddrbus;

  inout  [31:0] databus;

  output [31:0] daddrbus;

  

  input clk;
  



  wire [2:0] opbus_opcode;
  wire [2:0] opbus_dest;
  wire [2:0] opbus_src_a;
  wire [2:0] opbus_src_b;
  


  wire [2:0] cdbus_dest;
  wire [7:0] cdbus_dest_shift;
  wire [31:0] cdbus_data;
  wire cdbus_valid_data;
  


  wire [31:0] abus_wire_ld_st;
  wire [31:0] abus_wire_add;
  wire [31:0] abus_wire_mult;
  wire [31:0] abus_wire_int;
  wire [31:0] bbus_wire_ld_st;
  wire [31:0] bbus_wire_add;
  wire [31:0] bbus_wire_mult;
  wire [31:0] bbus_wire_int;
  wire [7:0] a_select_wire_ld_st;
  wire [7:0] a_select_wire_add;
  wire [7:0] a_select_wire_mult;
  wire [7:0] a_select_wire_int;
  wire [7:0] b_select_wire_ld_st;
  wire [7:0] b_select_wire_add;
  wire [7:0] b_select_wire_mult;
  wire [7:0] b_select_wire_int;
  wire [7:0] busy_bus;
  


  wire [2:0] rs_ex_fp_op_code;
  wire [2:0] rs_ex_fp_d_select;
  wire [7:0] rs_ex_fp_d_select_shift;
  wire [31:0] rs_ex_fp_abus_data;
  wire [31:0] rs_ex_fp_bbus_data;
  wire rs_ex_fp_add_is_busy;

  wire [2:0] rs_ex_fp_mult_op_code;
  wire [2:0] rs_ex_fp_mult_d_select;
  wire [7:0] rs_ex_fp_mult_d_select_shift;
  wire [31:0] rs_ex_fp_mult_abus_data;
  wire [31:0] rs_ex_fp_mult_bbus_data;
  wire rs_ex_fp_mult_is_busy;

  wire [2:0] rs_ex_int_op_code;
  wire [2:0] rs_ex_int_d_select;
  wire [7:0] rs_ex_int_d_select_shift;
  wire [31:0] rs_ex_int_abus_data;
  wire [31:0] rs_ex_int_bbus_data;
  wire rs_ex_int_is_busy;

  wire [2:0] rs_ex_ld_op_code;
  wire [2:0] rs_ex_ld_d_select;
  wire [7:0] rs_ex_ld_d_select_shift;
  wire [31:0] rs_ex_ld_abus_data;
  wire [31:0] rs_ex_ld_bbus_data;

  wire [2:0] rs_ex_st_op_code;
  wire [2:0] rs_ex_st_d_select;
  wire [7:0] rs_ex_st_d_select_shift;
  wire [31:0] rs_ex_st_abus_data;
  wire [31:0] rs_ex_st_bbus_data;
  wire rs_ex_ld_st_is_busy;
  


  wire FP_add_mux_valid_data;
  wire [2:0] FP_add_mux_d_select;
  wire [7:0] FP_add_mux_d_select_shift;
  wire [31:0] FP_add_mux_data;
  wire FP_add_mux_stall;

  wire FP_mult_mux_valid_data;
  wire [2:0] FP_mult_mux_d_select;
  wire [7:0] FP_mult_mux_d_select_shift;
  wire [31:0] FP_mult_mux_data;
  wire FP_mult_mux_stall;

  wire int_mux_valid_data;
  wire [2:0] int_mux_d_select;
  wire [7:0] int_mux_d_select_shift;
  wire [31:0] int_mux_data;
  wire int_mux_stall;

  wire mem_mux_valid_data;
  wire [2:0] mem_mux_d_select;
  wire [7:0] mem_mux_d_select_shift;
  wire [31:0] mem_mux_data;
  wire mem_mux_stall;
  

  reg load_selected_flag;
  reg store_selected_flag;
  reg FP_add_selected_flag;
  reg FP_mult_selected_flag;
  reg int_selected_flag;
  

  wire load_full_flag;
  wire store_full_flag;
  wire FP_mult_full_flag;
  reg int_full_full_flag;
  wire FP_add_full_flag;
  

  wire RS_load_valid_data;
  wire RS_store_valid_data;
  


  wire [2:0] RS_load_mem_ofset;
  wire [2:0] RS_store_mem_ofset;
  wire [31:0] RS_load_address;
  wire [31:0] RS_store_address;

  wire RS_store_mux_stall;
  wire [31:0] RS_store_data;

  wire [2:0] RS_load_dest;
  wire [7:0] RS_load_dest_shift;
  

  wire [2:0] mem_ex_d_select;
  wire [7:0] mem_ex_d_select_shift;
  wire [2:0] mem_ex_b_offset;
  wire [31:0] mem_ex_dbus_data;
  wire [31:0] mem_ex_abus_address;
  wire [2:0] mem_ex_op_code;
  




  reg [11:0] instruction_queue [5:0];
  reg [11:0] current_instruction;
  

  wire [31:0] memory_address;
  reg [31:0] memory [3:0];
  wire [2:0] load_store;
  wire [31:0] store_data;
  reg [31:0] load_data;
  

  integer i;
  

  reg fake_rs_clock;
  wire fake_mux_clock;
  wire fake_mux_snoop_clock;
  wire fake_meme_RS_mux_clock;
  

  reg [7:0] busy_select_shift;


  regfile best_regfile_name_ever
  (

    .clk(clk), .AselectAdd(a_select_wire_add), .AselectInt(a_select_wire_int), .AselectMult(a_select_wire_mult),
    .AselectLdSt(a_select_wire_ld_st), .BselectAdd(b_select_wire_add), .BselectInt(b_select_wire_int), .BselectMult(b_select_wire_mult),
    .BselectLdSt(b_select_wire_ld_st), .busySelect(busy_select_shift), .Dselect(cdbus_dest_shift), .dbus(cdbus_data),
    .validData(cdbus_valid_data),

    .busyBus(busy_bus), .abusAdd(abus_wire_add), .abusMult(abus_wire_mult), .abusInt(abus_wire_int), .abusLdSt(abus_wire_ld_st),
    .bbusLdSt(bbus_wire_ld_st), .bbusMult(bbus_wire_mult), .bbusAdd(bbus_wire_add), .bbusInt(bbus_wire_int)
  );
  



  reservation_station #(.BUS_LENGTH(2),.ID(3'b010)) FP_add_station
  (

    .clk(clk), .fake_clock(fake_rs_clock), .fake_mux_clock(fake_mux_snoop_clock), .station_selected(FP_add_selected_flag),
    .opbus_op(opbus_opcode), .opbus_dest(opbus_dest), .opbus_src_a(opbus_src_a), .opbus_src_b(opbus_src_b), .abus_in(abus_wire_add),
    .bbus_in(bbus_wire_add), .busy_bus(busy_bus), .execution_unit_busy(rs_ex_fp_add_is_busy), .cdbus_dest(cdbus_dest),
    .cdbus_dest_shift(cdbus_dest_shift), .cdbus_dest_data(cdbus_data), .cdbus_valid(cdbus_valid_data),

    .a_select_out(a_select_wire_add), .b_select_out(b_select_wire_add), .station_full(FP_add_full_flag), .d_select_out(rs_ex_fp_d_select),
    .d_select_out_shift(rs_ex_fp_d_select_shift), .abus_out(rs_ex_fp_abus_data), .bbus_out(rs_ex_fp_bbus_data),
    .op_code_out(rs_ex_fp_op_code)
  );
  



  reservation_station #(.BUS_LENGTH(1),.ID(3'b001)) FP_mult_station
  (

    .clk(clk), .fake_clock(fake_rs_clock), .fake_mux_clock(fake_mux_snoop_clock), .station_selected(FP_mult_selected_flag),
    .opbus_op(opbus_opcode), .opbus_dest(opbus_dest), .opbus_src_a(opbus_src_a), .opbus_src_b(opbus_src_b), .abus_in(abus_wire_mult),
    .bbus_in(bbus_wire_mult), .busy_bus(busy_bus), .execution_unit_busy(rs_ex_fp_mult_is_busy), .cdbus_dest(cdbus_dest),
    .cdbus_dest_shift(cdbus_dest_shift), .cdbus_dest_data(cdbus_data), .cdbus_valid(cdbus_valid_data),

    .a_select_out(a_select_wire_mult), .b_select_out(b_select_wire_mult), .station_full(FP_mult_full_flag), .d_select_out(rs_ex_fp_mult_d_select),
    .d_select_out_shift(rs_ex_fp_mult_d_select_shift), .abus_out(rs_ex_fp_mult_abus_data), .bbus_out(rs_ex_fp_mult_bbus_data),
    .op_code_out(rs_ex_fp_mult_op_code)
  );
  



  reservation_station #(.BUS_LENGTH(2),.ID(3'b011)) store_station
  (

    .clk(clk), .fake_clock(fake_rs_clock), .fake_mux_clock(fake_mux_snoop_clock), .station_selected(store_selected_flag),
    .opbus_op(opbus_opcode), .opbus_dest(opbus_dest), .opbus_src_a(opbus_src_a), .opbus_src_b(opbus_src_b), .abus_in(abus_wire_ld_st),
    .bbus_in(bbus_wire_ld_st), .busy_bus(busy_bus), .execution_unit_busy(rs_ex_ld_st_is_busy), .cdbus_dest(cdbus_dest),
    .cdbus_dest_shift(cdbus_dest_shift), .cdbus_dest_data(cdbus_data), .cdbus_valid(cdbus_valid_data), .store_mux_stall(RS_store_mux_stall),

    .a_select_out(a_select_wire_ld_st), .b_select_out(b_select_wire_ld_st), .station_full(store_full_flag), .d_select_out(rs_ex_st_d_select),
    .d_select_out_shift(rs_ex_st_d_select_shift), .abus_out(RS_store_address), .bbus_out(RS_store_data),
    .op_code_out(rs_ex_st_op_code), .memory_offset_out(RS_store_mem_ofset), .valid_data(RS_store_valid_data)
  );
  



  reservation_station #(.BUS_LENGTH(2),.ID(3'b100)) load_station
  (

    .clk(clk), .fake_clock(fake_rs_clock), .fake_mux_clock(fake_mux_snoop_clock), .station_selected(load_selected_flag),
    .opbus_op(opbus_opcode), .opbus_dest(opbus_dest), .opbus_src_a(opbus_src_a), .opbus_src_b(opbus_src_b), .abus_in(abus_wire_ld_st),
    .bbus_in(bbus_wire_ld_st), .busy_bus(busy_bus), .execution_unit_busy(rs_ex_ld_st_is_busy), .cdbus_dest(cdbus_dest),
    .cdbus_dest_shift(cdbus_dest_shift), .cdbus_dest_data(cdbus_data), .cdbus_valid(cdbus_valid_data),

    .a_select_out(a_select_wire_ld_st), .b_select_out(b_select_wire_ld_st), .station_full(load_full_flag), .d_select_out(RS_load_dest),
    .d_select_out_shift(RS_load_dest_shift), .abus_out(RS_load_address), .bbus_out(rs_ex_ld_bbus_data),
    .op_code_out(rs_ex_ld_op_code), .trigger_exes(fake_meme_RS_mux_clock), .memory_offset_out(RS_load_mem_ofset),
    .valid_data(RS_load_valid_data)
  );
  

  partly_smart_mux psmux
(

  .fake_clock(fake_meme_RS_mux_clock), .load_d_select(RS_load_dest), .load_d_select_shift(RS_load_dest_shift),
  .load_address(RS_load_address), .load_offset(RS_load_mem_ofset), .store_dbus_data(RS_store_data), .store_address(RS_store_address),
  .store_offset(RS_store_mem_ofset), .valid_load_data(RS_load_valid_data), .valid_store_data(RS_store_valid_data),
  .load_op_code(rs_ex_ld_op_code), .store_op_code(rs_ex_st_op_code), .execution_unit_stall(rs_ex_ld_st_is_busy), .stall_by_mux(mem_mux_stall),

  .store_stall(RS_store_mux_stall), .exec_d_select(mem_ex_d_select), .exec_d_select_shift(mem_ex_d_select_shift),
  .exec_b_offset(mem_ex_b_offset), .exec_dbus_data(mem_ex_dbus_data), .exec_abus_address(mem_ex_abus_address), .exec_op_code(mem_ex_op_code)
);
  


  execution_unit #(.CYCLE_TIME(2),.ID(2'b11)) load_store_unit
  (

    .clk(clk), .op_code_in(mem_ex_op_code), .d_select_in(mem_ex_d_select), .d_select_shift_in(mem_ex_d_select_shift),
    .abus_data_in(mem_ex_abus_address), .stall_by_mux(mem_mux_stall), .offset_in(mem_ex_b_offset), .memory_in(load_data),
    .store_dbus_data_in(mem_ex_dbus_data),

    .is_busy(rs_ex_ld_st_is_busy), .valid_data(mem_mux_valid_data), .dbus_data_out(mem_mux_data),
    .d_select_out(mem_mux_d_select), .d_select_shift_out(mem_mux_d_select_shift), .memory_address(memory_address), .memory_out(store_data),
    .op_code_out(load_store)
  );
  


  execution_unit #(.CYCLE_TIME(3),.ID(2'b10)) FP_add_unit
  (

    .clk(clk), .op_code_in(rs_ex_fp_op_code), .d_select_in(rs_ex_fp_d_select), .d_select_shift_in(rs_ex_fp_d_select_shift),
    .abus_data_in(rs_ex_fp_abus_data), .bbus_data_in(rs_ex_fp_bbus_data), .stall_by_mux(FP_add_mux_stall),

    .is_busy(rs_ex_fp_add_is_busy), .valid_data(FP_add_mux_valid_data), .dbus_data_out(FP_add_mux_data),
    .d_select_out(FP_add_mux_d_select), .d_select_shift_out(FP_add_mux_d_select_shift)
  );
  


  execution_unit #(.CYCLE_TIME(5),.ID(2'b01)) FP_mult_unit
  (

    .clk(clk), .op_code_in(rs_ex_fp_mult_op_code), .d_select_in(rs_ex_fp_mult_d_select), .d_select_shift_in(rs_ex_fp_mult_d_select_shift),
    .abus_data_in(rs_ex_fp_mult_abus_data), .bbus_data_in(rs_ex_fp_mult_bbus_data), .stall_by_mux(FP_mult_mux_stall),

    .is_busy(rs_ex_fp_mult_is_busy), .valid_data(FP_mult_mux_valid_data), .dbus_data_out(FP_mult_mux_data),
    .d_select_out(FP_mult_mux_d_select), .d_select_shift_out(FP_mult_mux_d_select_shift), .fake_clock(fake_mux_clock)
  );
  

  smart_mux smux
  (

    .fake_clock(fake_mux_clock), .mem_valid(mem_mux_valid_data), .FP_mult_valid(FP_mult_mux_valid_data),
    .FP_add_valid(FP_add_mux_valid_data), .int_valid(int_mux_valid_data), .mem_d_select(mem_mux_d_select),
    .FP_mult_d_select(FP_mult_mux_d_select), .FP_add_d_select(FP_add_mux_d_select), .int_d_select(int_mux_d_select),
    .mem_d_select_shift(mem_mux_d_select_shift), .FP_mult_d_select_shift(FP_mult_mux_d_select_shift),
    .FP_add_d_select_shift(FP_add_mux_d_select_shift), .int_d_select_shift(int_mux_d_select_shift), .mem_data(mem_mux_data),
    .FP_mult_data(FP_mult_mux_data), .FP_add_data(FP_add_mux_data), .int_data(int_mux_data),

    .mem_stall(mem_mux_stall), .FP_mult_stall(FP_mult_mux_stall), .FP_add_stall(FP_add_mux_stall), .int_stall(int_mux_stall),
    .cdbus_d_select(cdbus_dest), .cdbus_d_select_shift(cdbus_dest_shift), .cdbus_data(cdbus_data), .cdbus_valid_data(cdbus_valid_data),
    .fake_mux_output_clock(fake_mux_snoop_clock)
  );
  
  initial begin

    store_selected_flag = 0;
    load_selected_flag = 0;
    FP_add_selected_flag = 0;
    FP_mult_selected_flag = 0;
    int_selected_flag = 0;
    int_full_full_flag = 0;

    fake_rs_clock = 0;
    busy_select_shift = 8'b0;

    current_instruction = 12'b0;
    load_data = 32'bz;


    instruction_queue[0] [11:0] = 12'b100_010_001_001;
    instruction_queue[1] [11:0] = 12'b011_011_010_001;
    instruction_queue[2] [11:0] = 12'b011_101_001_001;
    instruction_queue[3] [11:0] = 12'b000_000_000_000;
    instruction_queue[4] [11:0] = 12'b000_000_000_000;
    instruction_queue[5] [11:0] = 12'b000_000_000_000;
    

    memory[0] [31:0] = 32'hDEADBEEF;
    memory[1] [31:0] = 32'b0;
    memory[2] [31:0] = 32'b0;
    memory[3] [31:0] = 32'b0;
  end
  
  always @(posedge clk) begin


    store_selected_flag = 0;
    load_selected_flag = 0;
    FP_add_selected_flag = 0;
    FP_mult_selected_flag = 0;
    int_selected_flag = 0;

    busy_select_shift = 8'b0;

    current_instruction[11:0] = instruction_queue[0];
    case (current_instruction[11:9])
      3'b000: begin


      end
      3'b001: begin

        load_selected_flag = (load_full_flag)? 0 : 1;
      end
      3'b010: begin

        store_selected_flag = (store_full_flag)? 0 : 1;
      end
      3'b011: begin

        FP_add_selected_flag = (FP_add_full_flag)? 0 : 1;
      end
      3'b100: begin

        FP_mult_selected_flag = (FP_mult_full_flag)? 0 : 1;
      end
    endcase
    if(store_selected_flag||load_selected_flag||FP_add_selected_flag||FP_mult_selected_flag||int_selected_flag) begin



      if(!store_selected_flag) begin
        busy_select_shift = (current_instruction[8:6] == 3'b0)? 8'b0 : 8'b00000001 << current_instruction[8:6];
      end



      for(i = 0; i < 5; i=i+1) begin
        instruction_queue[i] = instruction_queue[i+1];
      end

      instruction_queue[5] = 12'b0;
    end


    fake_rs_clock = ~fake_rs_clock;
  end
  

  always @(memory_address) begin

    $display("request for memory started, memory_address=%d, load_store=%d", memory_address, load_store);
    if((memory_address >= 0) && (load_store > 3'b000)) begin
      load_data = 32'bz;
      case(load_store)
        3'b001: begin

          load_data = memory[memory_address];
        end
        3'b010: begin

          memory[memory_address] = store_data;
        end
      endcase
    end
  end

  assign opbus_opcode = (store_selected_flag||load_selected_flag||FP_add_selected_flag||FP_mult_selected_flag||int_selected_flag)? current_instruction[11:9] : 3'bz;
  assign opbus_dest = (store_selected_flag||load_selected_flag||FP_add_selected_flag||FP_mult_selected_flag||int_selected_flag)? current_instruction[8:6] : 3'bz;
  assign opbus_src_a = (store_selected_flag||load_selected_flag||FP_add_selected_flag||FP_mult_selected_flag||int_selected_flag)? current_instruction[5:3] : 3'bz;
  assign opbus_src_b = (store_selected_flag||load_selected_flag||FP_add_selected_flag||FP_mult_selected_flag||int_selected_flag)? current_instruction[2:0] : 3'bz;
endmodule
module assignment_4(reset,clk,ibus,iaddrbus,databus,daddrbus);





  input reset;



  input [11:0] ibus;


  output [31:0] iaddrbus;

  inout  [31:0] databus;

  output [31:0] daddrbus;

  

  input clk;
  



  wire [2:0] opbus_opcode;
  wire [2:0] opbus_dest;
  wire [2:0] opbus_src_a;
  wire [2:0] opbus_src_b;
  


  wire [2:0] cdbus_dest;
  wire [7:0] cdbus_dest_shift;
  wire [31:0] cdbus_data;
  wire cdbus_valid_data;
  


  wire [31:0] abus_wire_ld_st;
  wire [31:0] abus_wire_add;
  wire [31:0] abus_wire_mult;
  wire [31:0] abus_wire_int;
  wire [31:0] bbus_wire_ld_st;
  wire [31:0] bbus_wire_add;
  wire [31:0] bbus_wire_mult;
  wire [31:0] bbus_wire_int;
  wire [7:0] a_select_wire_ld_st;
  wire [7:0] a_select_wire_add;
  wire [7:0] a_select_wire_mult;
  wire [7:0] a_select_wire_int;
  wire [7:0] b_select_wire_ld_st;
  wire [7:0] b_select_wire_add;
  wire [7:0] b_select_wire_mult;
  wire [7:0] b_select_wire_int;
  wire [7:0] busy_bus;
  


  wire [2:0] rs_ex_fp_op_code;
  wire [2:0] rs_ex_fp_d_select;
  wire [7:0] rs_ex_fp_d_select_shift;
  wire [31:0] rs_ex_fp_abus_data;
  wire [31:0] rs_ex_fp_bbus_data;
  wire rs_ex_fp_add_is_busy;

  wire [2:0] rs_ex_fp_mult_op_code;
  wire [2:0] rs_ex_fp_mult_d_select;
  wire [7:0] rs_ex_fp_mult_d_select_shift;
  wire [31:0] rs_ex_fp_mult_abus_data;
  wire [31:0] rs_ex_fp_mult_bbus_data;
  wire rs_ex_fp_mult_is_busy;

  wire [2:0] rs_ex_int_op_code;
  wire [2:0] rs_ex_int_d_select;
  wire [7:0] rs_ex_int_d_select_shift;
  wire [31:0] rs_ex_int_abus_data;
  wire [31:0] rs_ex_int_bbus_data;
  wire rs_ex_int_is_busy;

  wire [2:0] rs_ex_ld_op_code;
  wire [2:0] rs_ex_ld_d_select;
  wire [7:0] rs_ex_ld_d_select_shift;
  wire [31:0] rs_ex_ld_abus_data;
  wire [31:0] rs_ex_ld_bbus_data;

  wire [2:0] rs_ex_st_op_code;
  wire [2:0] rs_ex_st_d_select;
  wire [7:0] rs_ex_st_d_select_shift;
  wire [31:0] rs_ex_st_abus_data;
  wire [31:0] rs_ex_st_bbus_data;
  wire rs_ex_ld_st_is_busy;
  


  wire FP_add_mux_valid_data;
  wire [2:0] FP_add_mux_d_select;
  wire [7:0] FP_add_mux_d_select_shift;
  wire [31:0] FP_add_mux_data;
  wire FP_add_mux_stall;

  wire FP_mult_mux_valid_data;
  wire [2:0] FP_mult_mux_d_select;
  wire [7:0] FP_mult_mux_d_select_shift;
  wire [31:0] FP_mult_mux_data;
  wire FP_mult_mux_stall;

  wire int_mux_valid_data;
  wire [2:0] int_mux_d_select;
  wire [7:0] int_mux_d_select_shift;
  wire [31:0] int_mux_data;
  wire int_mux_stall;

  wire mem_mux_valid_data;
  wire [2:0] mem_mux_d_select;
  wire [7:0] mem_mux_d_select_shift;
  wire [31:0] mem_mux_data;
  wire mem_mux_stall;
  

  reg load_selected_flag;
  reg store_selected_flag;
  reg FP_add_selected_flag;
  reg FP_mult_selected_flag;
  reg int_selected_flag;
  

  wire load_full_flag;
  wire store_full_flag;
  wire FP_mult_full_flag;
  reg int_full_full_flag;
  wire FP_add_full_flag;
  

  wire RS_load_valid_data;
  wire RS_store_valid_data;
  


  wire [2:0] RS_load_mem_ofset;
  wire [2:0] RS_store_mem_ofset;
  wire [31:0] RS_load_address;
  wire [31:0] RS_store_address;

  wire RS_store_mux_stall;
  wire [31:0] RS_store_data;

  wire [2:0] RS_load_dest;
  wire [7:0] RS_load_dest_shift;
  

  wire [2:0] mem_ex_d_select;
  wire [7:0] mem_ex_d_select_shift;
  wire [2:0] mem_ex_b_offset;
  wire [31:0] mem_ex_dbus_data;
  wire [31:0] mem_ex_abus_address;
  wire [2:0] mem_ex_op_code;
  




  reg [11:0] instruction_queue [5:0];
  reg [11:0] current_instruction;
  

  wire [31:0] memory_address;
  reg [31:0] memory [3:0];
  wire [2:0] load_store;
  wire [31:0] store_data;
  reg [31:0] load_data;
  

  integer i;
  

  reg fake_rs_clock;
  wire fake_mux_clock;
  wire fake_mux_snoop_clock;
  wire fake_meme_RS_mux_clock;
  

  reg [7:0] busy_select_shift;


  regfile best_regfile_name_ever
  (

    .clk(clk), .AselectAdd(a_select_wire_add), .AselectInt(a_select_wire_int), .AselectMult(a_select_wire_mult),
    .AselectLdSt(a_select_wire_ld_st), .BselectAdd(b_select_wire_add), .BselectInt(b_select_wire_int), .BselectMult(b_select_wire_mult),
    .BselectLdSt(b_select_wire_ld_st), .busySelect(busy_select_shift), .Dselect(cdbus_dest_shift), .dbus(cdbus_data),
    .validData(cdbus_valid_data),

    .busyBus(busy_bus), .abusAdd(abus_wire_add), .abusMult(abus_wire_mult), .abusInt(abus_wire_int), .abusLdSt(abus_wire_ld_st),
    .bbusLdSt(bbus_wire_ld_st), .bbusMult(bbus_wire_mult), .bbusAdd(bbus_wire_add), .bbusInt(bbus_wire_int)
  );
  



  reservation_station #(.BUS_LENGTH(2),.ID(3'b010)) FP_add_station
  (

    .clk(clk), .fake_clock(fake_rs_clock), .fake_mux_clock(fake_mux_snoop_clock), .station_selected(FP_add_selected_flag),
    .opbus_op(opbus_opcode), .opbus_dest(opbus_dest), .opbus_src_a(opbus_src_a), .opbus_src_b(opbus_src_b), .abus_in(abus_wire_add),
    .bbus_in(bbus_wire_add), .busy_bus(busy_bus), .execution_unit_busy(rs_ex_fp_add_is_busy), .cdbus_dest(cdbus_dest),
    .cdbus_dest_shift(cdbus_dest_shift), .cdbus_dest_data(cdbus_data), .cdbus_valid(cdbus_valid_data),

    .a_select_out(a_select_wire_add), .b_select_out(b_select_wire_add), .station_full(FP_add_full_flag), .d_select_out(rs_ex_fp_d_select),
    .d_select_out_shift(rs_ex_fp_d_select_shift), .abus_out(rs_ex_fp_abus_data), .bbus_out(rs_ex_fp_bbus_data),
    .op_code_out(rs_ex_fp_op_code)
  );
  



  reservation_station #(.BUS_LENGTH(1),.ID(3'b001)) FP_mult_station
  (

    .clk(clk), .fake_clock(fake_rs_clock), .fake_mux_clock(fake_mux_snoop_clock), .station_selected(FP_mult_selected_flag),
    .opbus_op(opbus_opcode), .opbus_dest(opbus_dest), .opbus_src_a(opbus_src_a), .opbus_src_b(opbus_src_b), .abus_in(abus_wire_mult),
    .bbus_in(bbus_wire_mult), .busy_bus(busy_bus), .execution_unit_busy(rs_ex_fp_mult_is_busy), .cdbus_dest(cdbus_dest),
    .cdbus_dest_shift(cdbus_dest_shift), .cdbus_dest_data(cdbus_data), .cdbus_valid(cdbus_valid_data),

    .a_select_out(a_select_wire_mult), .b_select_out(b_select_wire_mult), .station_full(FP_mult_full_flag), .d_select_out(rs_ex_fp_mult_d_select),
    .d_select_out_shift(rs_ex_fp_mult_d_select_shift), .abus_out(rs_ex_fp_mult_abus_data), .bbus_out(rs_ex_fp_mult_bbus_data),
    .op_code_out(rs_ex_fp_mult_op_code)
  );
  



  reservation_station #(.BUS_LENGTH(2),.ID(3'b011)) store_station
  (

    .clk(clk), .fake_clock(fake_rs_clock), .fake_mux_clock(fake_mux_snoop_clock), .station_selected(store_selected_flag),
    .opbus_op(opbus_opcode), .opbus_dest(opbus_dest), .opbus_src_a(opbus_src_a), .opbus_src_b(opbus_src_b), .abus_in(abus_wire_ld_st),
    .bbus_in(bbus_wire_ld_st), .busy_bus(busy_bus), .execution_unit_busy(rs_ex_ld_st_is_busy), .cdbus_dest(cdbus_dest),
    .cdbus_dest_shift(cdbus_dest_shift), .cdbus_dest_data(cdbus_data), .cdbus_valid(cdbus_valid_data), .store_mux_stall(RS_store_mux_stall),

    .a_select_out(a_select_wire_ld_st), .b_select_out(b_select_wire_ld_st), .station_full(store_full_flag), .d_select_out(rs_ex_st_d_select),
    .d_select_out_shift(rs_ex_st_d_select_shift), .abus_out(RS_store_address), .bbus_out(RS_store_data),
    .op_code_out(rs_ex_st_op_code), .memory_offset_out(RS_store_mem_ofset), .valid_data(RS_store_valid_data)
  );
  



  reservation_station #(.BUS_LENGTH(2),.ID(3'b100)) load_station
  (

    .clk(clk), .fake_clock(fake_rs_clock), .fake_mux_clock(fake_mux_snoop_clock), .station_selected(load_selected_flag),
    .opbus_op(opbus_opcode), .opbus_dest(opbus_dest), .opbus_src_a(opbus_src_a), .opbus_src_b(opbus_src_b), .abus_in(abus_wire_ld_st),
    .bbus_in(bbus_wire_ld_st), .busy_bus(busy_bus), .execution_unit_busy(rs_ex_ld_st_is_busy), .cdbus_dest(cdbus_dest),
    .cdbus_dest_shift(cdbus_dest_shift), .cdbus_dest_data(cdbus_data), .cdbus_valid(cdbus_valid_data),

    .a_select_out(a_select_wire_ld_st), .b_select_out(b_select_wire_ld_st), .station_full(load_full_flag), .d_select_out(RS_load_dest),
    .d_select_out_shift(RS_load_dest_shift), .abus_out(RS_load_address), .bbus_out(rs_ex_ld_bbus_data),
    .op_code_out(rs_ex_ld_op_code), .trigger_exes(fake_meme_RS_mux_clock), .memory_offset_out(RS_load_mem_ofset),
    .valid_data(RS_load_valid_data)
  );
  

  partly_smart_mux psmux
(

  .fake_clock(fake_meme_RS_mux_clock), .load_d_select(RS_load_dest), .load_d_select_shift(RS_load_dest_shift),
  .load_address(RS_load_address), .load_offset(RS_load_mem_ofset), .store_dbus_data(RS_store_data), .store_address(RS_store_address),
  .store_offset(RS_store_mem_ofset), .valid_load_data(RS_load_valid_data), .valid_store_data(RS_store_valid_data),
  .load_op_code(rs_ex_ld_op_code), .store_op_code(rs_ex_st_op_code), .execution_unit_stall(rs_ex_ld_st_is_busy), .stall_by_mux(mem_mux_stall),

  .store_stall(RS_store_mux_stall), .exec_d_select(mem_ex_d_select), .exec_d_select_shift(mem_ex_d_select_shift),
  .exec_b_offset(mem_ex_b_offset), .exec_dbus_data(mem_ex_dbus_data), .exec_abus_address(mem_ex_abus_address), .exec_op_code(mem_ex_op_code)
);
  


  execution_unit #(.CYCLE_TIME(2),.ID(2'b11)) load_store_unit
  (

    .clk(clk), .op_code_in(mem_ex_op_code), .d_select_in(mem_ex_d_select), .d_select_shift_in(mem_ex_d_select_shift),
    .abus_data_in(mem_ex_abus_address), .stall_by_mux(mem_mux_stall), .offset_in(mem_ex_b_offset), .memory_in(load_data),
    .store_dbus_data_in(mem_ex_dbus_data),

    .is_busy(rs_ex_ld_st_is_busy), .valid_data(mem_mux_valid_data), .dbus_data_out(mem_mux_data),
    .d_select_out(mem_mux_d_select), .d_select_shift_out(mem_mux_d_select_shift), .memory_address(memory_address), .memory_out(store_data),
    .op_code_out(load_store)
  );
  


  execution_unit #(.CYCLE_TIME(3),.ID(2'b10)) FP_add_unit
  (

    .clk(clk), .op_code_in(rs_ex_fp_op_code), .d_select_in(rs_ex_fp_d_select), .d_select_shift_in(rs_ex_fp_d_select_shift),
    .abus_data_in(rs_ex_fp_abus_data), .bbus_data_in(rs_ex_fp_bbus_data), .stall_by_mux(FP_add_mux_stall),

    .is_busy(rs_ex_fp_add_is_busy), .valid_data(FP_add_mux_valid_data), .dbus_data_out(FP_add_mux_data),
    .d_select_out(FP_add_mux_d_select), .d_select_shift_out(FP_add_mux_d_select_shift)
  );
  


  execution_unit #(.CYCLE_TIME(5),.ID(2'b01)) FP_mult_unit
  (

    .clk(clk), .op_code_in(rs_ex_fp_mult_op_code), .d_select_in(rs_ex_fp_mult_d_select), .d_select_shift_in(rs_ex_fp_mult_d_select_shift),
    .abus_data_in(rs_ex_fp_mult_abus_data), .bbus_data_in(rs_ex_fp_mult_bbus_data), .stall_by_mux(FP_mult_mux_stall),

    .is_busy(rs_ex_fp_mult_is_busy), .valid_data(FP_mult_mux_valid_data), .dbus_data_out(FP_mult_mux_data),
    .d_select_out(FP_mult_mux_d_select), .d_select_shift_out(FP_mult_mux_d_select_shift), .fake_clock(fake_mux_clock)
  );
  

  smart_mux smux
  (

    .fake_clock(fake_mux_clock), .mem_valid(mem_mux_valid_data), .FP_mult_valid(FP_mult_mux_valid_data),
    .FP_add_valid(FP_add_mux_valid_data), .int_valid(int_mux_valid_data), .mem_d_select(mem_mux_d_select),
    .FP_mult_d_select(FP_mult_mux_d_select), .FP_add_d_select(FP_add_mux_d_select), .int_d_select(int_mux_d_select),
    .mem_d_select_shift(mem_mux_d_select_shift), .FP_mult_d_select_shift(FP_mult_mux_d_select_shift),
    .FP_add_d_select_shift(FP_add_mux_d_select_shift), .int_d_select_shift(int_mux_d_select_shift), .mem_data(mem_mux_data),
    .FP_mult_data(FP_mult_mux_data), .FP_add_data(FP_add_mux_data), .int_data(int_mux_data),

    .mem_stall(mem_mux_stall), .FP_mult_stall(FP_mult_mux_stall), .FP_add_stall(FP_add_mux_stall), .int_stall(int_mux_stall),
    .cdbus_d_select(cdbus_dest), .cdbus_d_select_shift(cdbus_dest_shift), .cdbus_data(cdbus_data), .cdbus_valid_data(cdbus_valid_data),
    .fake_mux_output_clock(fake_mux_snoop_clock)
  );
  
  initial begin

    store_selected_flag = 0;
    load_selected_flag = 0;
    FP_add_selected_flag = 0;
    FP_mult_selected_flag = 0;
    int_selected_flag = 0;
    int_full_full_flag = 0;

    fake_rs_clock = 0;
    busy_select_shift = 8'b0;

    current_instruction = 12'b0;
    load_data = 32'bz;


    instruction_queue[0] [11:0] = 12'b100_010_001_001;
    instruction_queue[1] [11:0] = 12'b011_011_010_001;
    instruction_queue[2] [11:0] = 12'b011_101_001_001;
    instruction_queue[3] [11:0] = 12'b000_000_000_000;
    instruction_queue[4] [11:0] = 12'b000_000_000_000;
    instruction_queue[5] [11:0] = 12'b000_000_000_000;
    

    memory[0] [31:0] = 32'hDEADBEEF;
    memory[1] [31:0] = 32'b0;
    memory[2] [31:0] = 32'b0;
    memory[3] [31:0] = 32'b0;
  end
  
  always @(posedge clk) begin


    store_selected_flag = 0;
    load_selected_flag = 0;
    FP_add_selected_flag = 0;
    FP_mult_selected_flag = 0;
    int_selected_flag = 0;

    busy_select_shift = 8'b0;

    current_instruction[11:0] = instruction_queue[0];
    case (current_instruction[11:9])
      3'b000: begin


      end
      3'b001: begin

        load_selected_flag = (load_full_flag)? 0 : 1;
      end
      3'b010: begin

        store_selected_flag = (store_full_flag)? 0 : 1;
      end
      3'b011: begin

        FP_add_selected_flag = (FP_add_full_flag)? 0 : 1;
      end
      3'b100: begin

        FP_mult_selected_flag = (FP_mult_full_flag)? 0 : 1;
      end
    endcase
    if(store_selected_flag||load_selected_flag||FP_add_selected_flag||FP_mult_selected_flag||int_selected_flag) begin



      if(!store_selected_flag) begin
        busy_select_shift = (current_instruction[8:6] == 3'b0)? 8'b0 : 8'b00000001 << current_instruction[8:6];
      end



      for(i = 0; i < 5; i=i+1) begin
        instruction_queue[i] = instruction_queue[i+1];
      end

      instruction_queue[5] = 12'b0;
    end


    fake_rs_clock = ~fake_rs_clock;
  end
  

  always @(memory_address) begin

    $display("request for memory started, memory_address=%d, load_store=%d", memory_address, load_store);
    if((memory_address >= 0) && (load_store > 3'b000)) begin
      load_data = 32'bz;
      case(load_store)
        3'b001: begin

          load_data = memory[memory_address];
        end
        3'b010: begin

          memory[memory_address] = store_data;
        end
      endcase
    end
  end

  assign opbus_opcode = (store_selected_flag||load_selected_flag||FP_add_selected_flag||FP_mult_selected_flag||int_selected_flag)? current_instruction[11:9] : 3'bz;
  assign opbus_dest = (store_selected_flag||load_selected_flag||FP_add_selected_flag||FP_mult_selected_flag||int_selected_flag)? current_instruction[8:6] : 3'bz;
  assign opbus_src_a = (store_selected_flag||load_selected_flag||FP_add_selected_flag||FP_mult_selected_flag||int_selected_flag)? current_instruction[5:3] : 3'bz;
  assign opbus_src_b = (store_selected_flag||load_selected_flag||FP_add_selected_flag||FP_mult_selected_flag||int_selected_flag)? current_instruction[2:0] : 3'bz;
endmodule