data/full_repos/permissive/134057391/tutorials/03-SN74181/rtl/sn74181.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/fb6a3214-4709-42d6-9efc-c609e0c1353c.xml
module sn74181(
    input  [3:0] a,
    input  [3:0] b,
    input  [3:0] s,
    input        m,
    input        ci_n,
    output [3:0] f,
    output       aeqb,
    output       x,
    output       y,
    output       co_n
    );



    wire   [3:0] p_n;
    wire   [3:0] g_n;
    genvar       i;

    for (i = 0; i < 4; i = i + 1) begin
        assign g_n[i] = ! (( a[i] &&  s[3] &&  b[i]) || ( a[i] &&  s[2] && !b[i]));
        assign p_n[i] = ! ((!b[i] &&  s[1]) || ( b[i] &&  s[0]) || a[i]);
    end


    wire [3:0] f_int;
    wire       y_int;
    wire       z;

    assign y_int = (
                    !(
                        (p_n[3]) ||
                        (g_n[3] && p_n[2]) ||
                        (g_n[3] && g_n[2] && p_n[1]) ||
                        (g_n[3] && g_n[2] && g_n[1] && p_n[0])
                    )
                );

    assign z = !(ci_n && (&g_n));

    assign co_n = !(y_int && z);

    assign x = ! (&g_n);

    assign f_int[3] = (
                        (p_n[3] ^ g_n[3]) ^
                        !(
                            (!m &&  g_n[2] &&  g_n[1] &&  g_n[0] &&  ci_n) ||
                            (!m &&  p_n[0] &&  g_n[2] &&  g_n[1]) ||
                            (!m &&  p_n[1] &&  g_n[2]) ||
                            (!m &&  p_n[2])
                        )
                    );

    assign f_int[2] = (
                        (p_n[2] ^ g_n[2]) ^
                        !(
                            (!m &&  g_n[1] &&  g_n[0] &&  ci_n) ||
                            (!m &&  p_n[0] &&  g_n[1]) ||
                            (!m &&  p_n[1])
                        )
                    );

    assign f_int[1] = (
                        (p_n[1] ^ g_n[1]) ^
                        !(
                            (!m &&  g_n[0] &&  ci_n) ||
                            (!m &&  p_n[0])
                        )
                    );

    assign f_int[0] = (
                        (p_n[0] ^ g_n[0]) ^
                        !(!m && ci_n)
                    );

    assign y = y_int;
    assign f = f_int;
    assign aeqb = &f_int;

endmodule
module sn74181(
    input  [3:0] a,
    input  [3:0] b,
    input  [3:0] s,
    input        m,
    input        ci_n,
    output [3:0] f,
    output       aeqb,
    output       x,
    output       y,
    output       co_n
    );




    wire   [3:0] p_n;
    wire   [3:0] g_n;
    genvar       i;

    for (i = 0; i < 4; i = i + 1) begin
        assign g_n[i] = ! (( a[i] &&  s[3] &&  b[i]) || ( a[i] &&  s[2] && !b[i]));
        assign p_n[i] = ! ((!b[i] &&  s[1]) || ( b[i] &&  s[0]) || a[i]);
    end


    wire [3:0] f_int;
    wire       y_int;
    wire       z;

    assign y_int = (
                    !(
                        (p_n[3]) ||
                        (g_n[3] && p_n[2]) ||
                        (g_n[3] && g_n[2] && p_n[1]) ||
                        (g_n[3] && g_n[2] && g_n[1] && p_n[0])
                    )
                );

    assign z = !(ci_n && (&g_n));

    assign co_n = !(y_int && z);

    assign x = ! (&g_n);

    assign f_int[3] = (
                        (p_n[3] ^ g_n[3]) ^
                        !(
                            (!m &&  g_n[2] &&  g_n[1] &&  g_n[0] &&  ci_n) ||
                            (!m &&  p_n[0] &&  g_n[2] &&  g_n[1]) ||
                            (!m &&  p_n[1] &&  g_n[2]) ||
                            (!m &&  p_n[2])
                        )
                    );

    assign f_int[2] = (
                        (p_n[2] ^ g_n[2]) ^
                        !(
                            (!m &&  g_n[1] &&  g_n[0] &&  ci_n) ||
                            (!m &&  p_n[0] &&  g_n[1]) ||
                            (!m &&  p_n[1])
                        )
                    );

    assign f_int[1] = (
                        (p_n[1] ^ g_n[1]) ^
                        !(
                            (!m &&  g_n[0] &&  ci_n) ||
                            (!m &&  p_n[0])
                        )
                    );

    assign f_int[0] = (
                        (p_n[0] ^ g_n[0]) ^
                        !(!m && ci_n)
                    );

    assign y = y_int;
    assign f = f_int;
    assign aeqb = &f_int;

endmodule