data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v
 line:65: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #40 rst_n = 1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:48: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("apple1_top_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:49: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #180000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #400\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #400\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #400\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #800\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #1600\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #1000000 $display("Stopping...");\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/apple1_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #20 clk25 = !clk25;\n        ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module apple1_tb #(
    parameter BASIC_FILENAME      = "../roms/basic.hex",
    parameter FONT_ROM_FILENAME   = "../roms/vga_font_bitreversed.hex",
    parameter RAM_FILENAME        = "../roms/ram.hex",
    parameter VRAM_FILENAME       = "../roms/vga_vram.bin",
    parameter WOZMON_ROM_FILENAME = "../roms/wozmon.hex"
);

    reg clk25, uart_rx, rst_n;
    wire uart_tx, uart_cts;




    initial begin

        clk25 = 1'b0;
        uart_rx = 1'b1;
        rst_n = 1'b0;
        #40 rst_n = 1'b1;

        $display("Starting...");
        $dumpfile("apple1_top_tb.vcd");
        $dumpvars;

        #180000
        uart_rx = 1'b0;
        #400
        uart_rx = 1'b1;
        #400
        uart_rx = 1'b0;
        #400
        uart_rx = 1'b1;
        #800
        uart_rx = 1'b0;
        #1600
        uart_rx = 1'b1;
 

        #1000000 $display("Stopping...");
        $finish;
    end




    always
        #20 clk25 = !clk25;



    apple1 #(
        .BASIC_FILENAME (BASIC_FILENAME),
        .FONT_ROM_FILENAME (FONT_ROM_FILENAME),
        .RAM_FILENAME (RAM_FILENAME),
        .VRAM_FILENAME (VRAM_FILENAME),
        .WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
    ) core_top (
        .clk25(clk25),
        .rst_n(rst_n),
        .uart_rx(uart_rx),
        .uart_tx(uart_tx),
        .uart_cts(uart_cts)
    );

endmodule
module apple1_tb #(
    parameter BASIC_FILENAME      = "../roms/basic.hex",
    parameter FONT_ROM_FILENAME   = "../roms/vga_font_bitreversed.hex",
    parameter RAM_FILENAME        = "../roms/ram.hex",
    parameter VRAM_FILENAME       = "../roms/vga_vram.bin",
    parameter WOZMON_ROM_FILENAME = "../roms/wozmon.hex"
);


    reg clk25, uart_rx, rst_n;
    wire uart_tx, uart_cts;




    initial begin

        clk25 = 1'b0;
        uart_rx = 1'b1;
        rst_n = 1'b0;
        #40 rst_n = 1'b1;

        $display("Starting...");
        $dumpfile("apple1_top_tb.vcd");
        $dumpvars;

        #180000
        uart_rx = 1'b0;
        #400
        uart_rx = 1'b1;
        #400
        uart_rx = 1'b0;
        #400
        uart_rx = 1'b1;
        #800
        uart_rx = 1'b0;
        #1600
        uart_rx = 1'b1;
 

        #1000000 $display("Stopping...");
        $finish;
    end




    always
        #20 clk25 = !clk25;



    apple1 #(
        .BASIC_FILENAME (BASIC_FILENAME),
        .FONT_ROM_FILENAME (FONT_ROM_FILENAME),
        .RAM_FILENAME (RAM_FILENAME),
        .VRAM_FILENAME (VRAM_FILENAME),
        .WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
    ) core_top (
        .clk25(clk25),
        .rst_n(rst_n),
        .uart_rx(uart_rx),
        .uart_tx(uart_tx),
        .uart_cts(uart_cts)
    );

endmodule