data/full_repos/permissive/139767240/CodeSnippetsExamples/Mux-4to1-1.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/139767240/CodeSnippetsExamples/Mux-4to1-1.v:18: Little bit endian vector: MSB < LSB of bit range: 0:3\n    input [0:3]W;\n          ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mux4to1 (W, S, f);
    input [0:3]W;
    input [1:0] S;
    output reg f;

    always @(W, S)
        case (S)
            0: f = W[0];
            1: f = W[1];
            2: f = W[2];
            3: f = W[3];
        endcase

endmodule
module mux4to1 (W, S, f);

    input [0:3]W;
    input [1:0] S;
    output reg f;

    always @(W, S)
        case (S)
            0: f = W[0];
            1: f = W[1];
            2: f = W[2];
            3: f = W[3];
        endcase

endmodule