data/full_repos/permissive/113471686/baseline/test/tb_mtree.v
None: at end of input
1: b'%Error: data/full_repos/permissive/113471686/baseline/test/tb_mtree.v:7: Cannot find include file: mtree.v\n`include "mtree.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113471686/baseline/test,data/full_repos/permissive/113471686/mtree.v\n             data/full_repos/permissive/113471686/baseline/test,data/full_repos/permissive/113471686/mtree.v.v\n             data/full_repos/permissive/113471686/baseline/test,data/full_repos/permissive/113471686/mtree.v.sv\n             mtree.v\n             mtree.v.v\n             mtree.v.sv\n             obj_dir/mtree.v\n             obj_dir/mtree.v.v\n             obj_dir/mtree.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/113471686/baseline/test/tb_mtree.v:14: Unsupported: Ignoring delay on this delayed statement.\n  reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end\n                                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113471686/baseline/test/tb_mtree.v:15: Unsupported: Ignoring delay on this delayed statement.\n  reg RST; initial begin RST=1; #400 RST=0; end\n                                ^\n%Error: data/full_repos/permissive/113471686/baseline/test/tb_mtree.v:49: Unsupported: $fflush of all handles does not map to C++.\n      $fflush();\n      ^~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module tb_MERGE_SORTER_TREE();
  reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
  reg RST; initial begin RST=1; #400 RST=0; end
  
  wire [(`DATW<<`W_LOG)-1:0] merge_sorter_tree_din;
  wire [(1<<`W_LOG)-1:0]     merge_sorter_tree_dinen;
  wire [(1<<`W_LOG)-1:0]     merge_sorter_tree_ful;
  wire [`DATW-1:0]           merge_sorter_tree_dot;
  wire                       merge_sorter_tree_doten;

  reg [`DATW-1:0]            check_record;

  assign merge_sorter_tree_dinen = ~merge_sorter_tree_ful;
  
  genvar i;
  generate
    for (i=0; i<(1<<`W_LOG); i=i+1) begin: loop
      wire [`KEYW-1:0] init_key = (1<<`W_LOG) - i;
      reg  [`DATW-1:0] init_record;
      always @(posedge CLK) begin
        if      (RST)                        init_record <= {{(`DATW-`KEYW){1'b1}}, init_key};
        else if (merge_sorter_tree_dinen[i]) init_record <= init_record + (1<<`W_LOG);
      end
      assign merge_sorter_tree_din[`DATW*(i+1)-1:`DATW*i] = init_record;
    end
  endgenerate

  MERGE_SORTER_TREE #(`W_LOG, `DATW, `KEYW)
  merge_sorter_tree(CLK, RST, 1'b0, merge_sorter_tree_din, merge_sorter_tree_dinen, 
                    merge_sorter_tree_ful, merge_sorter_tree_dot, merge_sorter_tree_doten);


  always @(posedge CLK) begin
    if (merge_sorter_tree_doten) begin
      $write("%d", merge_sorter_tree_dot[`KEYW-1:0]);
      $write("\n");
      $fflush();
    end
  end


  always @(posedge CLK) begin
    if (RST) begin
      check_record <= {{(`DATW-`KEYW){1'b1}}, `KEYW'b1};
    end else begin
      if (merge_sorter_tree_doten) begin
        check_record <= check_record + 1;
        if (merge_sorter_tree_dot != check_record) begin
          $write("\nError!\n");
          $write("%d %d\n", merge_sorter_tree_dot, check_record);
          $finish();
        end
      end
    end
  end
  

  reg [31:0] cycle;
  always @(posedge CLK) begin
    if (RST) begin
      cycle <= 0;
    end else begin
      cycle <= cycle + 1;
      if (cycle >= 200) $finish();
    end
  end

endmodule
module tb_MERGE_SORTER_TREE();

  reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
  reg RST; initial begin RST=1; #400 RST=0; end
  
  wire [(`DATW<<`W_LOG)-1:0] merge_sorter_tree_din;
  wire [(1<<`W_LOG)-1:0]     merge_sorter_tree_dinen;
  wire [(1<<`W_LOG)-1:0]     merge_sorter_tree_ful;
  wire [`DATW-1:0]           merge_sorter_tree_dot;
  wire                       merge_sorter_tree_doten;

  reg [`DATW-1:0]            check_record;

  assign merge_sorter_tree_dinen = ~merge_sorter_tree_ful;
  
  genvar i;
  generate
    for (i=0; i<(1<<`W_LOG); i=i+1) begin: loop
      wire [`KEYW-1:0] init_key = (1<<`W_LOG) - i;
      reg  [`DATW-1:0] init_record;
      always @(posedge CLK) begin
        if      (RST)                        init_record <= {{(`DATW-`KEYW){1'b1}}, init_key};
        else if (merge_sorter_tree_dinen[i]) init_record <= init_record + (1<<`W_LOG);
      end
      assign merge_sorter_tree_din[`DATW*(i+1)-1:`DATW*i] = init_record;
    end
  endgenerate

  MERGE_SORTER_TREE #(`W_LOG, `DATW, `KEYW)
  merge_sorter_tree(CLK, RST, 1'b0, merge_sorter_tree_din, merge_sorter_tree_dinen, 
                    merge_sorter_tree_ful, merge_sorter_tree_dot, merge_sorter_tree_doten);


  always @(posedge CLK) begin
    if (merge_sorter_tree_doten) begin
      $write("%d", merge_sorter_tree_dot[`KEYW-1:0]);
      $write("\n");
      $fflush();
    end
  end


  always @(posedge CLK) begin
    if (RST) begin
      check_record <= {{(`DATW-`KEYW){1'b1}}, `KEYW'b1};
    end else begin
      if (merge_sorter_tree_doten) begin
        check_record <= check_record + 1;
        if (merge_sorter_tree_dot != check_record) begin
          $write("\nError!\n");
          $write("%d %d\n", merge_sorter_tree_dot, check_record);
          $finish();
        end
      end
    end
  end
  

  reg [31:0] cycle;
  always @(posedge CLK) begin
    if (RST) begin
      cycle <= 0;
    end else begin
      cycle <= cycle + 1;
      if (cycle >= 200) $finish();
    end
  end

endmodule