data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/reset_sync.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/reset_sync.v:21: Cannot find file containing module: 'synchronizer'\n  synchronizer #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/synchronizer\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/synchronizer.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/synchronizer.sv\n             synchronizer\n             synchronizer.v\n             synchronizer.sv\n             obj_dir/synchronizer\n             obj_dir/synchronizer.v\n             obj_dir/synchronizer.sv\n%Error: Exiting due to 1 error(s)\n"
module reset_sync (

  input  clk,

  input  reset_in,

  output reg reset_out);

  wire reset_c;

  synchronizer #(


    .FALSE_PATH_TO_IN(1),



    .INITIAL_VAL(1),
    .STAGES(10)
  ) reset_double_sync (
    .clk(clk), .rst(1'b0), .in(reset_in), .out(reset_c)
  );

  always @(posedge clk)
      reset_out <= reset_c;

endmodule
module reset_sync (

  input  clk,

  input  reset_in,

  output reg reset_out);


  wire reset_c;

  synchronizer #(


    .FALSE_PATH_TO_IN(1),



    .INITIAL_VAL(1),
    .STAGES(10)
  ) reset_double_sync (
    .clk(clk), .rst(1'b0), .in(reset_in), .out(reset_c)
  );

  always @(posedge clk)
      reset_out <= reset_c;

endmodule