data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/weight_buffer/weight_buffer.v
None: at end of input
1: b'%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/weight_buffer/weight_buffer.v:2: Cannot find include file: common.vh\n`include "common.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/weight_buffer,data/full_repos/permissive/150133337/common.vh\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/weight_buffer,data/full_repos/permissive/150133337/common.vh.v\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/weight_buffer,data/full_repos/permissive/150133337/common.vh.sv\n             common.vh\n             common.vh.v\n             common.vh.sv\n             obj_dir/common.vh\n             obj_dir/common.vh.v\n             obj_dir/common.vh.sv\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/weight_buffer/weight_buffer.v:28: Define or directive not defined: \'`C_LOG_2\'\n  localparam integer MUX_SEL_WIDTH  = `C_LOG_2(WR_WIDTH/RD_WIDTH);\n                                      ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module weight_buffer
#(
  parameter integer RD_WIDTH      = 16,
  parameter integer WR_WIDTH      = 64,
  parameter integer RD_ADDR_WIDTH = 7,
  parameter integer WR_ADDR_WIDTH = 5
)
(
  input  wire                           clk,
  input  wire                           reset,

  input  wire                           read_req,
  output reg  [ RD_WIDTH      -1 : 0 ]  read_data,
  input  wire [ RD_ADDR_WIDTH -1 : 0 ]  read_addr,

  input  wire                           write_req,
  input  wire [ WR_WIDTH      -1 : 0 ]  write_data,
  input  wire [ WR_ADDR_WIDTH -1 : 0 ]  write_addr
);




  localparam integer MEM_WIDTH      = WR_WIDTH;
  localparam integer MEM_ADDR_WIDTH = WR_ADDR_WIDTH;
  localparam integer MUX_SEL_WIDTH  = `C_LOG_2(WR_WIDTH/RD_WIDTH);





  reg  [ MEM_WIDTH      -1 : 0 ] mem [ 0 : (1<<WR_ADDR_WIDTH) - 1 ];
  reg  [ MEM_WIDTH      -1 : 0 ] mem_out;
  reg  [ MUX_SEL_WIDTH  -1 : 0 ] mux_sel, mux_sel_d;

  reg  [ WR_ADDR_WIDTH  -1 : 0 ] mem_addr;

  reg                            read_req_d, read_req_dd;

  wire [ 1024           -1 : 0 ] GND = 1024'd0;



  integer ii, jj;
  reg [WR_WIDTH-1:0] tmp;
  initial begin
    for (ii=0; ii<1<<WR_ADDR_WIDTH; ii=ii+1)
    begin
      tmp = 0;
      for (jj=1<<(RD_ADDR_WIDTH-WR_ADDR_WIDTH); jj > -1; jj=jj-1)
      begin
        tmp = (tmp << RD_WIDTH) + (ii*(1<<(RD_ADDR_WIDTH - WR_ADDR_WIDTH)) + jj);
        mem [ii] = tmp;
      end
    end
  end

  always @(posedge clk)
  begin: MEM_ADDR_GEN
    if (reset)
      {mem_addr, mux_sel} <= 'b0;
    else if (read_req)
      {mem_addr, mux_sel} <= read_addr;
  end

  always @(posedge clk)
    read_req_d <= read_req;
  always @(posedge clk)
    read_req_dd <= read_req_d;

  always @(posedge clk)
  begin: MEM_READ
    if (reset)
      mem_out <= GND[MEM_WIDTH-1:0];
    else if (read_req_d)
      mem_out <= mem[mem_addr];
  end

  always @(posedge clk)
    mux_sel_d <= mux_sel;

  always @(posedge clk)
  begin: MUX_READ
    read_data <= mem_out[mux_sel_d*RD_WIDTH+:RD_WIDTH];
  end

  always @(posedge clk)
  begin: WRITE
    if (write_req)
    begin
      mem[write_addr] <= write_data;
    end
  end

endmodule
module weight_buffer
#(
  parameter integer RD_WIDTH      = 16,
  parameter integer WR_WIDTH      = 64,
  parameter integer RD_ADDR_WIDTH = 7,
  parameter integer WR_ADDR_WIDTH = 5
)
(
  input  wire                           clk,
  input  wire                           reset,

  input  wire                           read_req,
  output reg  [ RD_WIDTH      -1 : 0 ]  read_data,
  input  wire [ RD_ADDR_WIDTH -1 : 0 ]  read_addr,

  input  wire                           write_req,
  input  wire [ WR_WIDTH      -1 : 0 ]  write_data,
  input  wire [ WR_ADDR_WIDTH -1 : 0 ]  write_addr
);





  localparam integer MEM_WIDTH      = WR_WIDTH;
  localparam integer MEM_ADDR_WIDTH = WR_ADDR_WIDTH;
  localparam integer MUX_SEL_WIDTH  = `C_LOG_2(WR_WIDTH/RD_WIDTH);





  reg  [ MEM_WIDTH      -1 : 0 ] mem [ 0 : (1<<WR_ADDR_WIDTH) - 1 ];
  reg  [ MEM_WIDTH      -1 : 0 ] mem_out;
  reg  [ MUX_SEL_WIDTH  -1 : 0 ] mux_sel, mux_sel_d;

  reg  [ WR_ADDR_WIDTH  -1 : 0 ] mem_addr;

  reg                            read_req_d, read_req_dd;

  wire [ 1024           -1 : 0 ] GND = 1024'd0;



  integer ii, jj;
  reg [WR_WIDTH-1:0] tmp;
  initial begin
    for (ii=0; ii<1<<WR_ADDR_WIDTH; ii=ii+1)
    begin
      tmp = 0;
      for (jj=1<<(RD_ADDR_WIDTH-WR_ADDR_WIDTH); jj > -1; jj=jj-1)
      begin
        tmp = (tmp << RD_WIDTH) + (ii*(1<<(RD_ADDR_WIDTH - WR_ADDR_WIDTH)) + jj);
        mem [ii] = tmp;
      end
    end
  end

  always @(posedge clk)
  begin: MEM_ADDR_GEN
    if (reset)
      {mem_addr, mux_sel} <= 'b0;
    else if (read_req)
      {mem_addr, mux_sel} <= read_addr;
  end

  always @(posedge clk)
    read_req_d <= read_req;
  always @(posedge clk)
    read_req_dd <= read_req_d;

  always @(posedge clk)
  begin: MEM_READ
    if (reset)
      mem_out <= GND[MEM_WIDTH-1:0];
    else if (read_req_d)
      mem_out <= mem[mem_addr];
  end

  always @(posedge clk)
    mux_sel_d <= mux_sel;

  always @(posedge clk)
  begin: MUX_READ
    read_data <= mem_out[mux_sel_d*RD_WIDTH+:RD_WIDTH];
  end

  always @(posedge clk)
  begin: WRITE
    if (write_req)
    begin
      mem[write_addr] <= write_data;
    end
  end

endmodule