data/full_repos/permissive/120845848/003-key_filter/tb/key_model.v
 line:13: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/120845848/003-key_filter/tb/key_model.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #get_rand key = !key;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120845848/003-key_filter/tb/key_model.v:18: Unsupported: Ignoring delay on this delayed statement.\n   #25_000_000;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/120845848/003-key_filter/tb/key_model.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #get_rand key = !key;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/120845848/003-key_filter/tb/key_model.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #25_000_000;\n   ^\n%Warning-WIDTH: data/full_repos/permissive/120845848/003-key_filter/tb/key_model.v:14: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                     : ... In instance key_model\n    get_rand = {$random}%65536;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/120845848/003-key_filter/tb/key_model.v:20: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                     : ... In instance key_model\n    get_rand = {$random}%65536;\n             ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module key_model(press,key);
	input press;
	output reg key;
	
	initial key = 1'b1;
	
	reg [15:0]get_rand;
	
	task press_key;
		begin
			repeat(50)begin
				get_rand = {$random}%65536;
				#get_rand key = !key;
			end
			key = 1'b0;
			#25_000_000;
			repeat(50)begin
				get_rand = {$random}%65536;
				#get_rand key = !key;
			end
			key = 1'b1;
			#25_000_000;
		end
	endtask
	
	always@(posedge press)
		press_key;

endmodule
module key_model(press,key);

	input press;
	output reg key;
	
	initial key = 1'b1;
	
	reg [15:0]get_rand;
	
	task press_key;
		begin
			repeat(50)begin
				get_rand = {$random}%65536;
				#get_rand key = !key;
			end
			key = 1'b0;
			#25_000_000;
			repeat(50)begin
				get_rand = {$random}%65536;
				#get_rand key = !key;
			end
			key = 1'b1;
			#25_000_000;
		end
	endtask
	
	always@(posedge press)
		press_key;

endmodule