data/full_repos/permissive/205055389/test/verga/always1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/always1.v:8: Unsupported: Ignoring delay on this delayed statement.\n #2 r = i;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/always1.v:16: Unsupported: Ignoring delay on this delayed statement.\n          #3 b = j;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/always1.v:18: Unsupported: Ignoring delay on this delayed statement.\n          #5 b = 2*j;\n          ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg[31:0] r,b;
  integer i,j;

  initial
    for (i = 0;i < 10;i = i + 1)
      begin
	#2 r = i;
	$display("r=%d in <%m>",r);
      end 

  initial
    for (j = 0;j < 10;j = j + 1)
      begin
        if (j < 7)
          #3 b = j;
        else
          #5 b = 2*j;
	$display("b=%d",b);
      end 

  always @(r or b)
    begin
      $display("@%d change in r=%d or b=%d",$time,r,b);
    end 

endmodule
module top;

  reg[31:0] r,b;
  integer i,j;

  initial
    for (i = 0;i < 10;i = i + 1)
      begin
	#2 r = i;
	$display("r=%d in <%m>",r);
      end 

  initial
    for (j = 0;j < 10;j = j + 1)
      begin
        if (j < 7)
          #3 b = j;
        else
          #5 b = 2*j;
	$display("b=%d",b);
      end 

  always @(r or b)
    begin
      $display("@%d change in r=%d or b=%d",$time,r,b);
    end 

endmodule