data/full_repos/permissive/179884651/examples/WF_audio_demo.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:55: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:57: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:63: Signal definition not found, creating implicitly: \'ten_ms\'\n                                                                                   : ... Suggested alternative: \'ten_us\'\n           .timer_pulse(ten_ms));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:69: Signal definition not found, creating implicitly: \'quarter_second\'\n           .timer_pulse(quarter_second));\n                        ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:78: Signal definition not found, creating implicitly: \'switch_pushed\'\n      .switch_pushed(switch_pushed),     \n                     ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:108: Signal definition not found, creating implicitly: \'sclk_fall\'\n  assign sclk_fall = sclk_d && ~SCK;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:48: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.v\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:214: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h1 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:216: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h3 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:219: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h6 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:220: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h7 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:222: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h9 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:223: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'ha : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:224: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'hb : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:244: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                 : ... In instance fpga_top\n    assign sinlut = sine[phase_acc[15:8]];\n                  ^\n%Error: Exiting due to 1 error(s), 14 warning(s)\n'
module WF_timer (
       input  wire clk,
       input  wire enable,
       output reg  timer_pulse
   );

   parameter [9:0] COUNT = 499;
   parameter       EVERY_CLK = 1'b0;

    reg [9:0] counter;

    always @ (posedge clk)
        if (enable)
          begin
            if (counter == COUNT)
              begin
                timer_pulse <= 1'b1;
                counter     <= 'b0;
              end
           else
             begin
              counter     <= counter + 'b1;
              if (EVERY_CLK)
               timer_pulse <= 1'b0;
             end

          end
        else
            timer_pulse <= 1'b0;

   endmodule
module WF_timer (
       input  wire clk,
       input  wire enable,
       output reg  timer_pulse
   );


   parameter [9:0] COUNT = 499;
   parameter       EVERY_CLK = 1'b0;

    reg [9:0] counter;

    always @ (posedge clk)
        if (enable)
          begin
            if (counter == COUNT)
              begin
                timer_pulse <= 1'b1;
                counter     <= 'b0;
              end
           else
             begin
              counter     <= counter + 'b1;
              if (EVERY_CLK)
               timer_pulse <= 1'b0;
             end

          end
        else
            timer_pulse <= 1'b0;

   endmodule