data/full_repos/permissive/143278/ivltests/delay_assign_nb2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/delay_assign_nb2.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (step !== 0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/delay_assign_nb2.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #2 if (step !== 1) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [7:0] delay = 0;
   reg	     step;

   initial begin
      delay = 2;
      step = 0;
      step <= #(delay) 1;

      #1 if (step !== 0) begin
	 $display("FAILED -- step=%b at time=1", step);
	 $finish;
      end

      #2 if (step !== 1) begin
	 $display("FAILED == step=%b at time=3", step);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg [7:0] delay = 0;
   reg	     step;

   initial begin
      delay = 2;
      step = 0;
      step <= #(delay) 1;

      #1 if (step !== 0) begin
	 $display("FAILED -- step=%b at time=1", step);
	 $finish;
      end

      #2 if (step !== 1) begin
	 $display("FAILED == step=%b at time=3", step);
	 $finish;
      end

      $display("PASSED");
   end

endmodule