data/full_repos/permissive/119187354/Counter_4bit.v
data/verilator_xmls/521530e0-cd2d-4b95-a61a-3be419544549.xml
module Counter_4bit(
	input CLK,
	input [3:0]IN,
	input LD,
	input RESET,
	output [3:0]OUT
);

	reg [3:0]Q;
	
	always @ (posedge CLK) begin
		if (RESET) begin
			Q <= 4'b0000;
		end else begin
			if (LD) begin
				Q <= IN;
			end else begin
				Q <= Q + 4'b0001;
			end
		end
	end
	
	assign OUT = Q;
	
endmodule
module Counter_4bit(
	input CLK,
	input [3:0]IN,
	input LD,
	input RESET,
	output [3:0]OUT
);


	reg [3:0]Q;
	
	always @ (posedge CLK) begin
		if (RESET) begin
			Q <= 4'b0000;
		end else begin
			if (LD) begin
				Q <= IN;
			end else begin
				Q <= Q + 4'b0001;
			end
		end
	end
	
	assign OUT = Q;
	
endmodule