data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb/lspuf_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb/lspuf_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb/lspuf_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n always #50 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb/lspuf_tb.v:38: Cannot find file containing module: \'lspuf\'\n lspuf uut (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb,data/full_repos/permissive/128781882/lspuf\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb,data/full_repos/permissive/128781882/lspuf.v\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb,data/full_repos/permissive/128781882/lspuf.sv\n             lspuf\n             lspuf.v\n             lspuf.sv\n             obj_dir/lspuf\n             obj_dir/lspuf.v\n             obj_dir/lspuf.sv\n%Warning-WIDTH: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/tb/lspuf_tb.v:51: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'hafbaafbaafbaafb\' generates 64 bits.\n                                                                                                  : ... In instance lspuf_tb\n  c = 64\'hafbaafbaafbaafb;\n    ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lspuf_tb;


	reg clk;
	reg tigSignal;
	reg [15:0] c;


	wire respReady;
	wire [9:0] respBitA;
	wire [8:0] respBits;


	lspuf uut (
		.clk(clk), 
		.tigSignal(tigSignal), 
		.c(c), 
		.respReady(respReady), 
		.respBitA(respBitA), 
		.respBits(respBits)
	);

	initial begin

		clk = 0;
		tigSignal = 0;
		c = 64'hafbaafbaafbaafb;


		#500;
		tigSignal = 1;
        


	end
   
	always #50 clk = ~clk;
	
endmodule
module lspuf_tb;



	reg clk;
	reg tigSignal;
	reg [15:0] c;


	wire respReady;
	wire [9:0] respBitA;
	wire [8:0] respBits;


	lspuf uut (
		.clk(clk), 
		.tigSignal(tigSignal), 
		.c(c), 
		.respReady(respReady), 
		.respBitA(respBitA), 
		.respBits(respBits)
	);

	initial begin

		clk = 0;
		tigSignal = 0;
		c = 64'hafbaafbaafbaafb;


		#500;
		tigSignal = 1;
        


	end
   
	always #50 clk = ~clk;
	
endmodule