data/full_repos/permissive/159596577/testbench/cla32_test/cla32_tb.v
 line:1: before: "@"
1: b'%Error: data/full_repos/permissive/159596577/testbench/cla32_test/cla32_tb.v:2: Cannot find include file: ../../src/cla32.v\n`include "../../src/cla32.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159596577/testbench/cla32_test,data/full_repos/permissive/159596577/../../src/cla32.v\n             data/full_repos/permissive/159596577/testbench/cla32_test,data/full_repos/permissive/159596577/../../src/cla32.v.v\n             data/full_repos/permissive/159596577/testbench/cla32_test,data/full_repos/permissive/159596577/../../src/cla32.v.sv\n             ../../src/cla32.v\n             ../../src/cla32.v.v\n             ../../src/cla32.v.sv\n             obj_dir/../../src/cla32.v\n             obj_dir/../../src/cla32.v.v\n             obj_dir/../../src/cla32.v.sv\n%Error: data/full_repos/permissive/159596577/testbench/cla32_test/cla32_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("cla32_test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/159596577/testbench/cla32_test/cla32_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159596577/testbench/cla32_test/cla32_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n       #0 A = 1;B = 1;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159596577/testbench/cla32_test/cla32_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n       #5 A = 2;B = 2;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/159596577/testbench/cla32_test/cla32_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n       #10 A = \'h4;B = \'h4;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/159596577/testbench/cla32_test/cla32_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n       #20 $finish;\n       ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module test_tb;

   reg [31:0]A,B;
   reg ci;
   wire co;
   wire [31:0]s;
   cla32 cla32(A, B,ci,s,co);

   initial begin
      $dumpfile("cla32_test.vcd");
      $dumpvars;
   end
   initial begin
       ci = 1'b0;
       #0 A = 1;B = 1;
       #5 A = 2;B = 2;
       #10 A = 'h4;B = 'h4;
       #20 $finish;
   end

endmodule
module test_tb;


   reg [31:0]A,B;
   reg ci;
   wire co;
   wire [31:0]s;
   cla32 cla32(A, B,ci,s,co);

   initial begin
      $dumpfile("cla32_test.vcd");
      $dumpvars;
   end
   initial begin
       ci = 1'b0;
       #0 A = 1;B = 1;
       #5 A = 2;B = 2;
       #10 A = 'h4;B = 'h4;
       #20 $finish;
   end

endmodule