data/full_repos/permissive/157135695/lab4_top.v
1: b"%Error: data/full_repos/permissive/157135695/lab4_top.v:31: Cannot find file containing module: 'lab4'\n  lab4 daCore(\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/157135695,data/full_repos/permissive/157135695/lab4\n             data/full_repos/permissive/157135695,data/full_repos/permissive/157135695/lab4.v\n             data/full_repos/permissive/157135695,data/full_repos/permissive/157135695/lab4.sv\n             lab4\n             lab4.v\n             lab4.sv\n             obj_dir/lab4\n             obj_dir/lab4.v\n             obj_dir/lab4.sv\n%Error: data/full_repos/permissive/157135695/lab4_top.v:44: Cannot find file containing module: 'var_clk'\n  var_clk clockGenerator(\n  ^~~~~~~\n%Error: data/full_repos/permissive/157135695/lab4_top.v:50: Cannot find file containing module: 'dual_reg_in'\n  dual_reg_in inputs(\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157135695/lab4_top.v:71: Cannot find file containing module: 'hex_to_seven_seg'\n  hex_to_seven_seg upperIOG(\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157135695/lab4_top.v:76: Cannot find file containing module: 'hex_to_seven_seg'\n  hex_to_seven_seg lowerIOG(\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157135695/lab4_top.v:81: Cannot find file containing module: 'hex_to_seven_seg'\n  hex_to_seven_seg upperIOF(\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157135695/lab4_top.v:86: Cannot find file containing module: 'hex_to_seven_seg'\n  hex_to_seven_seg lowerIOF(\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157135695/lab4_top.v:91: Cannot find file containing module: 'hex_to_seven_seg'\n  hex_to_seven_seg upperIOE(\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157135695/lab4_top.v:96: Cannot find file containing module: 'hex_to_seven_seg'\n  hex_to_seven_seg lowerIOE(\n  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module lab4_top(CLK50, SW, KEY, RESET_N, LEDR, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0);
  input         CLK50;
  input  [9:0]  SW;
  input  [3:0]  KEY;
  input			    RESET_N;
  
  output [9:0]  LEDR;
  output [6:0]  HEX5;
  output [6:0]  HEX4;
  output [6:0]  HEX3;
  output [6:0]  HEX2;
  output [6:0]  HEX1;
  output [6:0]  HEX0;
  
  wire			    CLK;
  wire 		      CLK_SEL;
  wire 		      RESET;
  wire			    EN_L;
  wire  [7:0]   IOA;
  wire	[7:0]	  IOB;
  wire	[7:0]	  IOC;
  wire	[7:0]	  IOD;
  wire	[7:0]	  IOE;
  wire	[7:0]	  IOF;
  wire	[7:0]	  IOG;
  
  assign RESET   = ~RESET_N;
  assign CLK_SEL = SW[9];
  assign EN_L    = KEY[2];
  
  lab4 daCore(
    .CLK(CLK),
    .RESET(RESET),
    .IOA(IOA),
    .IOB(IOB),
    .IOC(IOC),
    .EN_L(EN_L),
    .IOD(IOD),
    .IOE(IOE),
    .IOF(IOF),
    .IOG(IOG)
  );
  
  var_clk clockGenerator(
    .clock_50MHz(CLK50),
    .clock_sel({CLK_SEL, CLK_SEL, CLK_SEL}),
    .var_clock(CLK)
  );
  
  dual_reg_in inputs(
    .CLK(CLK),
    .IN(SW[7:0]),
    .SEL(SW[8]),
    .WEN_L(KEY[3]),
    .OUTA(IOA),
    .OUTB(IOB)
  );
  

  assign IOC[7:2]		= 6'b0;
  assign IOC[1]		= ~KEY[1];
  assign IOC[0]		= ~KEY[0];
  

  assign LEDR[9]     = CLK;
  assign LEDR[8]		= 1'b0;
  assign LEDR[7:0]   = IOD;
  

  
  hex_to_seven_seg upperIOG(
    .B(IOG[7:4]),
    .SSEG_L(HEX5)
  );
  
  hex_to_seven_seg lowerIOG(
    .B(IOG[3:0]),
    .SSEG_L(HEX4)
  );
  
  hex_to_seven_seg upperIOF(
    .B(IOF[7:4]),
    .SSEG_L(HEX3)
  );
  
  hex_to_seven_seg lowerIOF(
    .B(IOF[3:0]),
    .SSEG_L(HEX2)
  );
  
  hex_to_seven_seg upperIOE(
    .B(IOE[7:4]),
    .SSEG_L(HEX1)
  );
  
  hex_to_seven_seg lowerIOE(
    .B(IOE[3:0]),
    .SSEG_L(HEX0)
  );
  
endmodule
module lab4_top(CLK50, SW, KEY, RESET_N, LEDR, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0);

  input         CLK50;
  input  [9:0]  SW;
  input  [3:0]  KEY;
  input			    RESET_N;
  
  output [9:0]  LEDR;
  output [6:0]  HEX5;
  output [6:0]  HEX4;
  output [6:0]  HEX3;
  output [6:0]  HEX2;
  output [6:0]  HEX1;
  output [6:0]  HEX0;
  
  wire			    CLK;
  wire 		      CLK_SEL;
  wire 		      RESET;
  wire			    EN_L;
  wire  [7:0]   IOA;
  wire	[7:0]	  IOB;
  wire	[7:0]	  IOC;
  wire	[7:0]	  IOD;
  wire	[7:0]	  IOE;
  wire	[7:0]	  IOF;
  wire	[7:0]	  IOG;
  
  assign RESET   = ~RESET_N;
  assign CLK_SEL = SW[9];
  assign EN_L    = KEY[2];
  
  lab4 daCore(
    .CLK(CLK),
    .RESET(RESET),
    .IOA(IOA),
    .IOB(IOB),
    .IOC(IOC),
    .EN_L(EN_L),
    .IOD(IOD),
    .IOE(IOE),
    .IOF(IOF),
    .IOG(IOG)
  );
  
  var_clk clockGenerator(
    .clock_50MHz(CLK50),
    .clock_sel({CLK_SEL, CLK_SEL, CLK_SEL}),
    .var_clock(CLK)
  );
  
  dual_reg_in inputs(
    .CLK(CLK),
    .IN(SW[7:0]),
    .SEL(SW[8]),
    .WEN_L(KEY[3]),
    .OUTA(IOA),
    .OUTB(IOB)
  );
  

  assign IOC[7:2]		= 6'b0;
  assign IOC[1]		= ~KEY[1];
  assign IOC[0]		= ~KEY[0];
  

  assign LEDR[9]     = CLK;
  assign LEDR[8]		= 1'b0;
  assign LEDR[7:0]   = IOD;
  

  
  hex_to_seven_seg upperIOG(
    .B(IOG[7:4]),
    .SSEG_L(HEX5)
  );
  
  hex_to_seven_seg lowerIOG(
    .B(IOG[3:0]),
    .SSEG_L(HEX4)
  );
  
  hex_to_seven_seg upperIOF(
    .B(IOF[7:4]),
    .SSEG_L(HEX3)
  );
  
  hex_to_seven_seg lowerIOF(
    .B(IOF[3:0]),
    .SSEG_L(HEX2)
  );
  
  hex_to_seven_seg upperIOE(
    .B(IOE[7:4]),
    .SSEG_L(HEX1)
  );
  
  hex_to_seven_seg lowerIOE(
    .B(IOE[3:0]),
    .SSEG_L(HEX0)
  );
  
endmodule