data/full_repos/permissive/181082280/lab_7/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_7/tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_7/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_7/tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_7/tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_7/tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_7/tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_7/tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_7/tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/181082280/lab_7/tb.v:48: Unsupported or unknown PLI call: $monitor\n        $monitor ("d0=%2b d1=%2b d2=%2b sel=%2b y=%2b", d0, d1, d2, sel, y);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/181082280/lab_7/tb.v:52: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;   \n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;


    reg [1:0] d0;
    reg [1:0] d1;
    reg [1:0] d2;
    reg [1:0] sel;


    wire [1:0] y;


    mux dut
    (
        .d0  ( d0  ),
        .d1  ( d1  ),
        .d2  ( d2  ),
        .sel ( sel ),
        .y   ( y   )
    );

    initial begin
        d0  = 2'b00; d1  = 2'b01; d2  = 2'b10;
        #10;
        sel = 2'b00;
        #10;
        sel = 2'b01;
        #10;
        d0  = 2'b00; d1  = 2'b11; d2  = 2'b10;
        #10
        sel = 2'b10;
        #10;
        sel = 2'b11;
        #10;
        sel = 2'b00;
        #10;
        sel = 2'b11;
        #10;
    end



    initial
        $monitor ("d0=%2b d1=%2b d2=%2b sel=%2b y=%2b", d0, d1, d2, sel, y);


    initial 
        $dumpvars;

endmodule
module tb;



    reg [1:0] d0;
    reg [1:0] d1;
    reg [1:0] d2;
    reg [1:0] sel;


    wire [1:0] y;


    mux dut
    (
        .d0  ( d0  ),
        .d1  ( d1  ),
        .d2  ( d2  ),
        .sel ( sel ),
        .y   ( y   )
    );

    initial begin
        d0  = 2'b00; d1  = 2'b01; d2  = 2'b10;
        #10;
        sel = 2'b00;
        #10;
        sel = 2'b01;
        #10;
        d0  = 2'b00; d1  = 2'b11; d2  = 2'b10;
        #10
        sel = 2'b10;
        #10;
        sel = 2'b11;
        #10;
        sel = 2'b00;
        #10;
        sel = 2'b11;
        #10;
    end



    initial
        $monitor ("d0=%2b d1=%2b d2=%2b sel=%2b y=%2b", d0, d1, d2, sel, y);


    initial 
        $dumpvars;

endmodule