data/full_repos/permissive/143278/ivltests/pr1388974.v
 line:4: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1388974.v:4: Unsupported: Ignoring delay on this delayed statement.\n      # 32 $display("PASSED");\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr1388974.v:13: Too many digits for 32 bit number: 4294967312\n        ... As that number was unsized (\'d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n        ... Suggest adding a size to it.\n      # 4294967312 $display("FAILED -- time=%d", $time);\n        ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1388974.v:13: Unsupported: Ignoring delay on this delayed statement.\n      # 4294967312 $display("FAILED -- time=%d", $time);\n      ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   initial begin
      # 32 $display("PASSED");
      $finish;
   end





   initial begin
      # 4294967312 $display("FAILED -- time=%d", $time);
      $finish;
   end
endmodule
module main;


   initial begin
      # 32 $display("PASSED");
      $finish;
   end





   initial begin
      # 4294967312 $display("FAILED -- time=%d", $time);
      $finish;
   end
endmodule