data/full_repos/permissive/111433415/verilog/03_combinacionales/03-2_azar/azar.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/111433415/verilog/03_combinacionales/03-2_azar/azar.v:65: Multiple top level modules\n                                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                      : ... Top module \'hazard_f\'\nmodule hazard_f (\n       ^~~~~~~~\n                                                                                                      : ... Top module \'hazard_e\'\nmodule hazard_e #(\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module hazard_e #(


    parameter delay = 5
    )(
    input wire a,
    input wire b,
    output wire f
    );


    wire x, y, z;




    not #delay inv(x, a);
    and #delay and1(y, a, b);
    and #delay and2(z, x, b);
    or #delay or1(f, y, z);

endmodule
module hazard_e #(


    parameter delay = 5
    )(
    input wire a,
    input wire b,
    output wire f
    );



    wire x, y, z;




    not #delay inv(x, a);
    and #delay and1(y, a, b);
    and #delay and2(z, x, b);
    or #delay or1(f, y, z);

endmodule