data/full_repos/permissive/166661632/p7/p7/Exc_m.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:2: Cannot find include file: head.v\n`include"head.v" \n        ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166661632/p7/p7,data/full_repos/permissive/166661632/head.v\n             data/full_repos/permissive/166661632/p7/p7,data/full_repos/permissive/166661632/head.v.v\n             data/full_repos/permissive/166661632/p7/p7,data/full_repos/permissive/166661632/head.v.sv\n             head.v\n             head.v.v\n             head.v.sv\n             obj_dir/head.v\n             obj_dir/head.v.v\n             obj_dir/head.v.sv\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:22: Define or directive not defined: \'`lw\'\n  if(op==`lw)\n         ^~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:22: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if(op==`lw)\n            ^\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:25: Define or directive not defined: \'`exc_adel\'\n     exccode_m<=`exc_adel;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:27: Define or directive not defined: \'`exc_adel\'\n     exccode_m<=`exc_adel;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:31: Define or directive not defined: \'`sw\'\n  else if(op==`sw)\n              ^~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:34: Define or directive not defined: \'`exc_ades\'\n     exccode_m<=`exc_ades;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:36: Define or directive not defined: \'`exc_ades\'\n     exccode_m<=`exc_ades;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:40: Define or directive not defined: \'`lh\'\n  else if(op==`lh||op==`lhu)\n              ^~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:40: Define or directive not defined: \'`lhu\'\n  else if(op==`lh||op==`lhu)\n                       ^~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:43: Define or directive not defined: \'`exc_adel\'\n     exccode_m<=`exc_adel;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:45: Define or directive not defined: \'`exc_adel\'\n     exccode_m<=`exc_adel;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:49: Define or directive not defined: \'`sh\'\n  else if(op==`sh)\n              ^~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:52: Define or directive not defined: \'`exc_ades\'\n     exccode_m<=`exc_ades;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:54: Define or directive not defined: \'`exc_ades\'\n     exccode_m<=`exc_ades;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:58: Define or directive not defined: \'`lb\'\n  else if(op==`lb||op==`lbu)\n              ^~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:58: Define or directive not defined: \'`lbu\'\n  else if(op==`lb||op==`lbu)\n                       ^~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:61: Define or directive not defined: \'`exc_adel\'\n     exccode_m<=`exc_adel;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:65: Define or directive not defined: \'`sb\'\n  else if(op==`sb)\n              ^~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Exc_m.v:68: Define or directive not defined: \'`exc_ades\'\n     exccode_m<=`exc_ades;\n                ^~~~~~~~~\n%Error: Cannot continue\n'
module Exc_m(instr_m,ao_m,exccode_e,bd_e,exccode_m,bd_m);
input [31:0] instr_m,ao_m;
input [4:0] exccode_e;
input bd_e;
output reg [4:0] exccode_m;
output bd_m;

wire [5:0] op,funct;
assign funct=instr_m[5:0];
assign op=instr_m[31:26];

assign bd_m=bd_e;

initial begin
	exccode_m<=0;
end

always@(*)
	begin
		if(op==`lw)
			begin
				if(ao_m[1:0]!=0)
					exccode_m<=`exc_adel;
				else if(ao_m>32'h2fff&&!(ao_m>=32'h7f00&&ao_m<=32'h7f0b||ao_m>=32'h7f10&&ao_m<=32'h7f1b))
					exccode_m<=`exc_adel;
				else
					exccode_m<=exccode_e;
			end
		else if(op==`sw)
			begin
				if(ao_m[1:0]!=0)
					exccode_m<=`exc_ades;
				else if(ao_m>32'h2fff&&!(ao_m>=32'h7f00&&ao_m<=32'h7f07||ao_m>=32'h7f10&&ao_m<=32'h7f17))
					exccode_m<=`exc_ades;
				else
					exccode_m<=exccode_e;
			end
		else if(op==`lh||op==`lhu)
			begin
				if(ao_m[0]!=0)
					exccode_m<=`exc_adel;
				else if(ao_m>32'h2fff)
					exccode_m<=`exc_adel;
				else
					exccode_m<=exccode_e;
			end
		else if(op==`sh)
			begin
				if(ao_m[0]!=0)
					exccode_m<=`exc_ades;
				else if(ao_m>32'h2fff)
					exccode_m<=`exc_ades;
				else
					exccode_m<=exccode_e;
			end
		else if(op==`lb||op==`lbu)
			begin
				if(ao_m>32'h2fff)
					exccode_m<=`exc_adel;
				else
					exccode_m<=exccode_e;
			end
		else if(op==`sb)
			begin
				if(ao_m>32'h2fff)
					exccode_m<=`exc_ades;
				else
					exccode_m<=exccode_e;
			end
		else
			exccode_m<=exccode_e;
	end



endmodule
module Exc_m(instr_m,ao_m,exccode_e,bd_e,exccode_m,bd_m);

input [31:0] instr_m,ao_m;
input [4:0] exccode_e;
input bd_e;
output reg [4:0] exccode_m;
output bd_m;

wire [5:0] op,funct;
assign funct=instr_m[5:0];
assign op=instr_m[31:26];

assign bd_m=bd_e;

initial begin
	exccode_m<=0;
end

always@(*)
	begin
		if(op==`lw)
			begin
				if(ao_m[1:0]!=0)
					exccode_m<=`exc_adel;
				else if(ao_m>32'h2fff&&!(ao_m>=32'h7f00&&ao_m<=32'h7f0b||ao_m>=32'h7f10&&ao_m<=32'h7f1b))
					exccode_m<=`exc_adel;
				else
					exccode_m<=exccode_e;
			end
		else if(op==`sw)
			begin
				if(ao_m[1:0]!=0)
					exccode_m<=`exc_ades;
				else if(ao_m>32'h2fff&&!(ao_m>=32'h7f00&&ao_m<=32'h7f07||ao_m>=32'h7f10&&ao_m<=32'h7f17))
					exccode_m<=`exc_ades;
				else
					exccode_m<=exccode_e;
			end
		else if(op==`lh||op==`lhu)
			begin
				if(ao_m[0]!=0)
					exccode_m<=`exc_adel;
				else if(ao_m>32'h2fff)
					exccode_m<=`exc_adel;
				else
					exccode_m<=exccode_e;
			end
		else if(op==`sh)
			begin
				if(ao_m[0]!=0)
					exccode_m<=`exc_ades;
				else if(ao_m>32'h2fff)
					exccode_m<=`exc_ades;
				else
					exccode_m<=exccode_e;
			end
		else if(op==`lb||op==`lbu)
			begin
				if(ao_m>32'h2fff)
					exccode_m<=`exc_adel;
				else
					exccode_m<=exccode_e;
			end
		else if(op==`sb)
			begin
				if(ao_m>32'h2fff)
					exccode_m<=`exc_ades;
				else
					exccode_m<=exccode_e;
			end
		else
			exccode_m<=exccode_e;
	end



endmodule