data/full_repos/permissive/162533945/sra.v
data/verilator_xmls/69fdcba1-a746-4296-bdca-3144785d7d91.xml
module sra(in, amt, out);
	
	input [31:0] in;
	input [4:0] amt;
	output [31:0] out;
	
	wire [31:0] t0, t1, t2, t3, t4, t5, t6, t7, t8;
	
	shifter_right_16 sixteen(in, t0);
	genvar i0;
	generate
		for (i0=0;i0<32;i0=i0+1) begin: mux0
		 mux_2to1_1bit mux0(in[i0], t0[i0], amt[4], t1[i0]);
		end
	endgenerate
	
	

	
	shifter_right_8 eight(t1, t2);
	genvar i1;
	generate
		for (i1=0;i1<32;i1=i1+1) begin: mux1
		 mux_2to1_1bit mux1(t1[i1], t2[i1], amt[3], t3[i1]);
		end
	endgenerate

	
	shifter_right_4 four(t3, t4);
	genvar i2;
	generate
		for (i2=0;i2<32;i2=i2+1) begin: mux2
		 mux_2to1_1bit mux2(t3[i2], t4[i2], amt[2], t5[i2]);
		end
	endgenerate

	
	shifter_right_2 two(t5, t6);
	genvar i3;
	generate
		for (i3=0;i3<32;i3=i3+1) begin: mux3
		 mux_2to1_1bit mux3(t5[i3], t6[i3], amt[1], t7[i3]);
		end
	endgenerate

	
	shifter_right_1 one(t7, t8);
	genvar i4;
	generate
		for (i4=0;i4<32;i4=i4+1) begin: mux4
		 mux_2to1_1bit mux4(t7[i4], t8[i4], amt[0], out[i4]);
		end
	endgenerate

	
endmodule
module sra(in, amt, out);

	
	input [31:0] in;
	input [4:0] amt;
	output [31:0] out;
	
	wire [31:0] t0, t1, t2, t3, t4, t5, t6, t7, t8;
	
	shifter_right_16 sixteen(in, t0);
	genvar i0;
	generate
		for (i0=0;i0<32;i0=i0+1) begin: mux0
		 mux_2to1_1bit mux0(in[i0], t0[i0], amt[4], t1[i0]);
		end
	endgenerate
	
	

	
	shifter_right_8 eight(t1, t2);
	genvar i1;
	generate
		for (i1=0;i1<32;i1=i1+1) begin: mux1
		 mux_2to1_1bit mux1(t1[i1], t2[i1], amt[3], t3[i1]);
		end
	endgenerate

	
	shifter_right_4 four(t3, t4);
	genvar i2;
	generate
		for (i2=0;i2<32;i2=i2+1) begin: mux2
		 mux_2to1_1bit mux2(t3[i2], t4[i2], amt[2], t5[i2]);
		end
	endgenerate

	
	shifter_right_2 two(t5, t6);
	genvar i3;
	generate
		for (i3=0;i3<32;i3=i3+1) begin: mux3
		 mux_2to1_1bit mux3(t5[i3], t6[i3], amt[1], t7[i3]);
		end
	endgenerate

	
	shifter_right_1 one(t7, t8);
	genvar i4;
	generate
		for (i4=0;i4<32;i4=i4+1) begin: mux4
		 mux_2to1_1bit mux4(t7[i4], t8[i4], amt[0], out[i4]);
		end
	endgenerate

	
endmodule