data/full_repos/permissive/143278/ivltests/pr1478121.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1478121.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q !== 2\'bzz) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1478121.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q !== 2\'b01) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sub(inout [1:0]Q,
	   output[1:0]Di,
	   input [1:0]Do,
	   input dir);

   assign	 Di = Q;
   assign	 Q = dir? Do : 2'bzz;
endmodule
module sub(inout [1:0]Q,
	   output[1:0]Di,
	   input [1:0]Do,
	   input dir);


   assign	 Di = Q;
   assign	 Q = dir? Do : 2'bzz;
endmodule