data/full_repos/permissive/169220768/code/top.v
'utf-8' codec can't decode byte 0xba in position 5369: invalid start byte
1: b'%Error: data/full_repos/permissive/169220768/code/top.v:290: Cannot find file containing module: \'debounce\'\n debounce debounce(clk,btns,btns_d); \n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169220768/code,data/full_repos/permissive/169220768/debounce\n             data/full_repos/permissive/169220768/code,data/full_repos/permissive/169220768/debounce.v\n             data/full_repos/permissive/169220768/code,data/full_repos/permissive/169220768/debounce.sv\n             debounce\n             debounce.v\n             debounce.sv\n             obj_dir/debounce\n             obj_dir/debounce.v\n             obj_dir/debounce.sv\n%Warning-WIDTH: data/full_repos/permissive/169220768/code/top.v:297: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'sw\' generates 8 bits.\n                                                                   : ... In instance top\n assign addr_show = sw; \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/169220768/code/top.v:298: Cannot find file containing module: \'seg\'\n seg seg1(clk,1\'b1,out_show,an,seg7); \n ^~~\n%Error: data/full_repos/permissive/169220768/code/top.v:299: Cannot find file containing module: \'regfile_copy_DMem\'\n regfile_copy_DMem regfile_copy_DMem(clk,~rst,addr_show,out_show,DMemaddr_MEM >> 2,DMemin_MEM,DMemWrite_MEM);\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:311: Cannot find file containing module: \'mux4\'\n mux4 MUXPC(\n ^~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:319: Cannot find file containing module: \'dff\'\n dff DFFPC(\n ^~~\n%Error: data/full_repos/permissive/169220768/code/top.v:327: Cannot find file containing module: \'alu\'\n alu ALUPCPlus(PC,4,5\'d01,PCPlus_IF);\n ^~~\n%Error: data/full_repos/permissive/169220768/code/top.v:330: Cannot find file containing module: \'IMem\'\n IMem IMem(clk,1\'b0,IMemaddr,32\'b0,IMemout); \n ^~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:334: Cannot find file containing module: \'IFID\'\n IFID IFID(\n ^~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:354: Cannot find file containing module: \'control\'\n control control(\n ^~~~~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:383: Cannot find file containing module: \'mux\'\n mux #(5) MUXRegWtaddr(RegDst_ID,Rt,Rd,RegWtaddr_ID);\n ^~~\n%Error: data/full_repos/permissive/169220768/code/top.v:391: Cannot find file containing module: \'alu\'\n alu BranchALU(PCPlus_ID,IMMSignExtendedShiftLeft2,5\'d01,PCBranch_ID);\n ^~~\n%Error: data/full_repos/permissive/169220768/code/top.v:399: Cannot find file containing module: \'regfile\'\n regfile regfile(clk,~rst,RegRdaddr1_ID,RegRdout1_ID,RegRdaddr2_ID,RegRdout2_ID,RegWtaddr_WB,RegWtin_WB,RegWrite_WB);\n ^~~~~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:401: Cannot find file containing module: \'compare\'\n compare compare1(RegRdout1_ID,RegRdout2_ID,RsCMPRt); \n ^~~~~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:402: Cannot find file containing module: \'compare\'\n compare compare2(RegRdout1_ID,0,RsCMPZero); \n ^~~~~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:405: Cannot find file containing module: \'hazard\'\n hazard hazard(Rs,Rt,RegWtaddr_EX,DMemRead_EX,PCEn,IF_ID_En,ID_EX_Flush);\n ^~~~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:407: Cannot find file containing module: \'IDEX\'\n IDEX IDEX(\n ^~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:454: Cannot find file containing module: \'forward\'\n forward forward(Rs_EX,Rt_EX,RegWrite_MEM,RegWrite_WB,RegWtaddr_MEM,RegWtaddr_WB,RegRdout1Sel_Forward_EX,RegRdout2Sel_Forward_EX);\n ^~~~~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:455: Cannot find file containing module: \'mux4\'\n mux4 MUXRegRdout1FW(RegRdout1Sel_Forward_EX,RegRdout1_EX,RegWtin_WB,ALUResult_MEM,0,RegRdout1_Forward_EX); \n ^~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:456: Cannot find file containing module: \'mux4\'\n mux4 MUXRegRdout2FW(RegRdout2Sel_Forward_EX,RegRdout2_EX,RegWtin_WB,ALUResult_MEM,0,RegRdout2_Forward_EX); \n ^~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:457: Cannot find file containing module: \'mux\'\n mux MUXALUSrcA(ALUSrcASel_EX,RegRdout1_Forward_EX,ShamtZeroExtended_EX,ALUSrcA_EX);\n ^~~\n%Error: data/full_repos/permissive/169220768/code/top.v:458: Cannot find file containing module: \'mux4\'\n mux4 MUXALUSrcB(ALUSrcBSel_EX,RegRdout2_Forward_EX,IMMSignExtended_EX,IMMZeroExtended_EX,0,ALUSrcB_EX);\n ^~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:459: Cannot find file containing module: \'alu\'\n alu alu(ALUSrcA_EX,ALUSrcB_EX,ALUControl_EX,ALUResult_EX);\n ^~~\n%Error: data/full_repos/permissive/169220768/code/top.v:461: Cannot find file containing module: \'EXMEM\'\n EXMEM EXMEM(\n ^~~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:488: Cannot find file containing module: \'DMem\'\n DMem DMem(clk,DMemWrite_MEM,DMemaddr_MEM >> 2,DMemin_MEM,DMemout_MEM); \n ^~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:490: Cannot find file containing module: \'MEMWB\'\n MEMWB MEMWB(\n ^~~~~\n%Error: data/full_repos/permissive/169220768/code/top.v:513: Cannot find file containing module: \'mux\'\n mux MUXDMemtoReg(DMemtoReg_WB,ALUResult_WB,DMemout_WB,RegWtin_WB);\n ^~~\n%Error: Exiting due to 26 error(s), 1 warning(s)\n'
module top(
	input clk,



    input [7:0] sw,
    output [6:0] seg7,
    output [3:0] an,
	 output [0:0] Led,
	 input btnr,btnl,btns,btnd,btnu

	);
	

	

	
	wire ALUSrcASel_ID;
	wire ALUSrcASel_EX;
	wire [1:0] ALUSrcBSel_ID;
	wire [1:0] ALUSrcBSel_EX;
	wire [31:0] ALUSrcA_EX;
	wire [31:0] ALUSrcB_EX;
	wire [4:0] ALUControl_ID;
	wire [4:0] ALUControl_EX;
	wire [31:0] ALUResult_EX;
	wire [31:0] ALUResult_MEM;
	wire [31:0] ALUResult_WB;
	
	wire [1:0] RsCMPZero;
	wire [1:0] RsCMPRt;
	
	wire [31:0] IMMSignExtended_ID;
	wire [31:0] IMMSignExtended_EX;
	wire [31:0] IMMZeroExtended_ID;
	wire [31:0] IMMZeroExtended_EX;	
	wire [31:0] ShamtZeroExtended_ID;
	wire [31:0] ShamtZeroExtended_EX;	

	
	wire [1:0] RegRdout1Sel_Forward_EX;
	wire [1:0] RegRdout2Sel_Forward_EX;
	wire [31:0] RegRdout1_Forward_EX;
	wire [31:0] RegRdout2_Forward_EX;
	
	wire [4:0] RegRdaddr1_ID;
	wire [31:0] RegRdout1_ID;
	wire [31:0] RegRdout1_EX;
	wire [4:0] RegRdaddr2_ID;
	wire [31:0] RegRdout2_ID;
	wire [31:0] RegRdout2_EX;
	wire [4:0] RegWtaddr_ID;
	wire [4:0] RegWtaddr_EX;	
	wire [4:0] RegWtaddr_MEM;
	wire [4:0] RegWtaddr_WB;
	wire [31:0] RegWtin_WB;
	wire RegWrite_ID;
	wire RegWrite_EX;
	wire RegWrite_MEM;
	wire RegWrite_WB;
	wire RegDst_ID;


	wire [31:0] IMemaddr;
	wire [31:0] IMemout;
	
	wire [31:0] DMemaddr_MEM;
	wire [31:0] DMemin_MEM;
	wire DMemRead_MEM;
	wire [31:0] DMemout_MEM;
	wire [31:0] DMemout_WB;
	wire DMemWrite_MEM;
	wire DMemtoReg_EX;
	wire DMemtoReg_MEM;
	wire DMemtoReg_WB;
	
	
	wire [31:0] PC;
	wire [31:0] PCPlus_IF;
	wire [31:0] PCPlus_ID;
	wire [31:0] PCPlus_EX;
	wire [31:0] EPC;
	wire [31:0] nextPC;
	wire PCEn;
	wire [1:0] PCSrc_ID;

	wire IF_ID_En;
	wire IF_ID_Flush;
	wire ID_EX_Flush;
	
	
	wire [31:0] PCJump_ID;
	wire [31:0] PCJR_ID;
	wire [31:0] PCBranch_ID;
	
	wire [31:0] Instr;	
	wire [5:0] Funct;
	wire [4:0] Shamt;
	wire [15:0] IMM16;
	wire [4:0] Rd;
	wire [4:0] Rt;
	wire [4:0] Rs;
	wire [5:0] Op;
	wire [4:0] Rt_EX;
	wire [4:0] Rs_EX;

	wire [25:0] JumpIMM;
	wire [31:0] IMMSignExtendedShiftLeft2;
	



	wire btns_d;
	debounce	debounce(clk,btns,btns_d);
	reg rst;
	assign Led = rst;
	always @(posedge btns_d) rst=~rst;

	wire [4:0] addr_show;
	wire [31:0] out_show;
	assign addr_show = sw;
	seg seg1(clk,1'b1,out_show,an,seg7);
	regfile_copy_DMem regfile_copy_DMem(clk,~rst,addr_show,out_show,DMemaddr_MEM >> 2,DMemin_MEM,DMemWrite_MEM);







	

		

	mux4 MUXPC(
		.sel(PCSrc_ID),
		.d0(PCPlus_IF),
		.d1(PCBranch_ID),
		.d2(PCJump_ID),
		.d3(PCJR_ID),
		.out(nextPC)
	);
	dff DFFPC(
		.clk(~clk),
		.en(PCEn),
		.rst(rst),
		.datain(nextPC),
		.dataout(PC)
	);	
	
	alu ALUPCPlus(PC,4,5'd01,PCPlus_IF);
	
	assign IMemaddr = PC >> 2;
	IMem IMem(clk,1'b0,IMemaddr,32'b0,IMemout);
	
	

	IFID IFID(
		.clk(~clk),
		.en(IF_ID_En),
		.flush(IF_ID_Flush || rst),
		.PCPlus_in(PCPlus_IF),
		.IMemout_in(IMemout),
		.PCPlus_out(PCPlus_ID),
		.IMemout_out(Instr)
	);

	assign JumpIMM = Instr[25:0];
	assign Funct = Instr[5:0];
	assign Shamt = Instr[10:6];
	assign IMM16 = Instr[15:0];
	assign Rd = Instr[15:11];
	assign Rt = Instr[20:16];
	assign Rs = Instr[25:21];
	assign Op = Instr[31:26];
	

	control control(

		.clk(clk),
		.rst(rst),
		.Op(Op),
		.Rt(Rt),
		.Funct(Funct),
		.RsCMPRt(RsCMPRt),
		.RsCMPZero(RsCMPZero),

		.PCSrc(PCSrc_ID), 

		.RegDst(RegDst_ID),

		.ALUSrcASel(ALUSrcASel_ID),
		.ALUSrcBSel(ALUSrcBSel_ID), 
		.ALUControl(ALUControl_ID),

		.DMemRead(DMemRead_ID),
		.DMemWrite(DMemWrite_ID),

		.DMemtoReg(DMemtoReg_ID),
		.RegWrite(RegWrite_ID)
	);


	
	assign RegRdaddr1_ID = Rs;
	assign RegRdaddr2_ID = Rt;
	mux #(5) MUXRegWtaddr(RegDst_ID,Rt,Rd,RegWtaddr_ID);
	
	
	assign ShamtZeroExtended_ID = {{27{1'b0}},Shamt};
	assign IMMSignExtended_ID = {{16{IMM16[15]}},IMM16};
	assign IMMZeroExtended_ID = {{16{1'b0}},IMM16};
	
	assign IMMSignExtendedShiftLeft2 = IMMSignExtended_ID << 2;
	alu BranchALU(PCPlus_ID,IMMSignExtendedShiftLeft2,5'd01,PCBranch_ID);
	assign PCJump_ID = {{PCPlus_ID[31:28]},{{2'b00,JumpIMM}<<2}};
	assign PCJR_ID = RegRdout1_ID;
	

	
	assign IF_ID_Flush = (PCSrc_ID != 2'b00);
	
	regfile regfile(clk,~rst,RegRdaddr1_ID,RegRdout1_ID,RegRdaddr2_ID,RegRdout2_ID,RegWtaddr_WB,RegWtin_WB,RegWrite_WB);
	
	compare compare1(RegRdout1_ID,RegRdout2_ID,RsCMPRt);
	compare compare2(RegRdout1_ID,0,RsCMPZero);
	
	
	hazard hazard(Rs,Rt,RegWtaddr_EX,DMemRead_EX,PCEn,IF_ID_En,ID_EX_Flush);

	IDEX IDEX(
		.clk(~clk),
		.en(1'b1),	
		.flush(ID_EX_Flush || rst),


		.PCPlus_in(PCPlus_ID),
		.RegRdout1_in(RegRdout1_ID),
		.RegRdout2_in(RegRdout2_ID),
		.IMMSignExtended_in(IMMSignExtended_ID),
		.IMMZeroExtended_in(IMMZeroExtended_ID),
		.ShamtZeroExtended_in(ShamtZeroExtended_ID),
		.Rs_in(Rs),
		.Rt_in(Rt),
		.RegWtaddr_in(RegWtaddr_ID),

		.PCPlus_out(PCPlus_EX),
		.RegRdout1_out(RegRdout1_EX),
		.RegRdout2_out(RegRdout2_EX),
		.IMMSignExtended_out(IMMSignExtended_EX),
		.IMMZeroExtended_out(IMMZeroExtended_EX),
		.ShamtZeroExtended_out(ShamtZeroExtended_EX),
		.Rs_out(Rs_EX),
		.Rt_out(Rt_EX),
		.RegWtaddr_out(RegWtaddr_EX),
		


		.RegDst_in(RegDst_ID),
		.ALUSrcASel_in(ALUSrcASel_ID),
		.ALUSrcBSel_in(ALUSrcBSel_ID), 
		.ALUControl_in(ALUControl_ID),
		.DMemRead_in(DMemRead_ID),
		.DMemWrite_in(DMemWrite_ID),
		.DMemtoReg_in(DMemtoReg_ID),
		.RegWrite_in(RegWrite_ID),

		.RegDst_out(RegDst_EX),
		.ALUSrcASel_out(ALUSrcASel_EX),
		.ALUSrcBSel_out(ALUSrcBSel_EX), 
		.ALUControl_out(ALUControl_EX),
		.DMemRead_out(DMemRead_EX),
		.DMemWrite_out(DMemWrite_EX),
		.DMemtoReg_out(DMemtoReg_EX),
		.RegWrite_out(RegWrite_EX)
	);

	forward forward(Rs_EX,Rt_EX,RegWrite_MEM,RegWrite_WB,RegWtaddr_MEM,RegWtaddr_WB,RegRdout1Sel_Forward_EX,RegRdout2Sel_Forward_EX);
	mux4 MUXRegRdout1FW(RegRdout1Sel_Forward_EX,RegRdout1_EX,RegWtin_WB,ALUResult_MEM,0,RegRdout1_Forward_EX);
	mux4 MUXRegRdout2FW(RegRdout2Sel_Forward_EX,RegRdout2_EX,RegWtin_WB,ALUResult_MEM,0,RegRdout2_Forward_EX);
	mux MUXALUSrcA(ALUSrcASel_EX,RegRdout1_Forward_EX,ShamtZeroExtended_EX,ALUSrcA_EX);
	mux4 MUXALUSrcB(ALUSrcBSel_EX,RegRdout2_Forward_EX,IMMSignExtended_EX,IMMZeroExtended_EX,0,ALUSrcB_EX);
	alu alu(ALUSrcA_EX,ALUSrcB_EX,ALUControl_EX,ALUResult_EX);

	EXMEM EXMEM(
		.clk(~clk),
		.en(1'b1),
		.flush(rst),


		.ALUResult_in(ALUResult_EX),
		.DMemin_in(RegRdout2_Forward_EX),
		.RegWtaddr_in(RegWtaddr_EX),

		.ALUResult_out(ALUResult_MEM),
		.DMemin_out(DMemin_MEM),
		.RegWtaddr_out(RegWtaddr_MEM),


		.DMemRead_in(DMemRead_EX),
		.DMemWrite_in(DMemWrite_EX),
		.DMemtoReg_in(DMemtoReg_EX),
		.RegWrite_in(RegWrite_EX),

		.DMemRead_out(DMemRead_MEM),
		.DMemWrite_out(DMemWrite_MEM),
		.DMemtoReg_out(DMemtoReg_MEM),
		.RegWrite_out(RegWrite_MEM)
	);

	assign DMemaddr_MEM = ALUResult_MEM;
	DMem DMem(clk,DMemWrite_MEM,DMemaddr_MEM >> 2,DMemin_MEM,DMemout_MEM);	

	MEMWB MEMWB(
		.clk(~clk),
		.en(1'b1),
		.flush(rst),


		.ALUResult_in(ALUResult_MEM),
		.DMemout_in(DMemout_MEM),
		.RegWtaddr_in(RegWtaddr_MEM),

		.ALUResult_out(ALUResult_WB),
		.DMemout_out(DMemout_WB),
		.RegWtaddr_out(RegWtaddr_WB),


		.DMemtoReg_in(DMemtoReg_MEM),
		.RegWrite_in(RegWrite_MEM),

		.DMemtoReg_out(DMemtoReg_WB),
		.RegWrite_out(RegWrite_WB)
	);


	mux MUXDMemtoReg(DMemtoReg_WB,ALUResult_WB,DMemout_WB,RegWtin_WB);
	
	
	

	
	

	
	
	
endmodule
module top(
	input clk,



    input [7:0] sw,
    output [6:0] seg7,
    output [3:0] an,
	 output [0:0] Led,
	 input btnr,btnl,btns,btnd,btnu

	);

	

	

	
	wire ALUSrcASel_ID;
	wire ALUSrcASel_EX;
	wire [1:0] ALUSrcBSel_ID;
	wire [1:0] ALUSrcBSel_EX;
	wire [31:0] ALUSrcA_EX;
	wire [31:0] ALUSrcB_EX;
	wire [4:0] ALUControl_ID;
	wire [4:0] ALUControl_EX;
	wire [31:0] ALUResult_EX;
	wire [31:0] ALUResult_MEM;
	wire [31:0] ALUResult_WB;
	
	wire [1:0] RsCMPZero;
	wire [1:0] RsCMPRt;
	
	wire [31:0] IMMSignExtended_ID;
	wire [31:0] IMMSignExtended_EX;
	wire [31:0] IMMZeroExtended_ID;
	wire [31:0] IMMZeroExtended_EX;	
	wire [31:0] ShamtZeroExtended_ID;
	wire [31:0] ShamtZeroExtended_EX;	

	
	wire [1:0] RegRdout1Sel_Forward_EX;
	wire [1:0] RegRdout2Sel_Forward_EX;
	wire [31:0] RegRdout1_Forward_EX;
	wire [31:0] RegRdout2_Forward_EX;
	
	wire [4:0] RegRdaddr1_ID;
	wire [31:0] RegRdout1_ID;
	wire [31:0] RegRdout1_EX;
	wire [4:0] RegRdaddr2_ID;
	wire [31:0] RegRdout2_ID;
	wire [31:0] RegRdout2_EX;
	wire [4:0] RegWtaddr_ID;
	wire [4:0] RegWtaddr_EX;	
	wire [4:0] RegWtaddr_MEM;
	wire [4:0] RegWtaddr_WB;
	wire [31:0] RegWtin_WB;
	wire RegWrite_ID;
	wire RegWrite_EX;
	wire RegWrite_MEM;
	wire RegWrite_WB;
	wire RegDst_ID;


	wire [31:0] IMemaddr;
	wire [31:0] IMemout;
	
	wire [31:0] DMemaddr_MEM;
	wire [31:0] DMemin_MEM;
	wire DMemRead_MEM;
	wire [31:0] DMemout_MEM;
	wire [31:0] DMemout_WB;
	wire DMemWrite_MEM;
	wire DMemtoReg_EX;
	wire DMemtoReg_MEM;
	wire DMemtoReg_WB;
	
	
	wire [31:0] PC;
	wire [31:0] PCPlus_IF;
	wire [31:0] PCPlus_ID;
	wire [31:0] PCPlus_EX;
	wire [31:0] EPC;
	wire [31:0] nextPC;
	wire PCEn;
	wire [1:0] PCSrc_ID;

	wire IF_ID_En;
	wire IF_ID_Flush;
	wire ID_EX_Flush;
	
	
	wire [31:0] PCJump_ID;
	wire [31:0] PCJR_ID;
	wire [31:0] PCBranch_ID;
	
	wire [31:0] Instr;	
	wire [5:0] Funct;
	wire [4:0] Shamt;
	wire [15:0] IMM16;
	wire [4:0] Rd;
	wire [4:0] Rt;
	wire [4:0] Rs;
	wire [5:0] Op;
	wire [4:0] Rt_EX;
	wire [4:0] Rs_EX;

	wire [25:0] JumpIMM;
	wire [31:0] IMMSignExtendedShiftLeft2;
	



	wire btns_d;
	debounce	debounce(clk,btns,btns_d);
	reg rst;
	assign Led = rst;
	always @(posedge btns_d) rst=~rst;

	wire [4:0] addr_show;
	wire [31:0] out_show;
	assign addr_show = sw;
	seg seg1(clk,1'b1,out_show,an,seg7);
	regfile_copy_DMem regfile_copy_DMem(clk,~rst,addr_show,out_show,DMemaddr_MEM >> 2,DMemin_MEM,DMemWrite_MEM);







	

		

	mux4 MUXPC(
		.sel(PCSrc_ID),
		.d0(PCPlus_IF),
		.d1(PCBranch_ID),
		.d2(PCJump_ID),
		.d3(PCJR_ID),
		.out(nextPC)
	);
	dff DFFPC(
		.clk(~clk),
		.en(PCEn),
		.rst(rst),
		.datain(nextPC),
		.dataout(PC)
	);	
	
	alu ALUPCPlus(PC,4,5'd01,PCPlus_IF);
	
	assign IMemaddr = PC >> 2;
	IMem IMem(clk,1'b0,IMemaddr,32'b0,IMemout);
	
	

	IFID IFID(
		.clk(~clk),
		.en(IF_ID_En),
		.flush(IF_ID_Flush || rst),
		.PCPlus_in(PCPlus_IF),
		.IMemout_in(IMemout),
		.PCPlus_out(PCPlus_ID),
		.IMemout_out(Instr)
	);

	assign JumpIMM = Instr[25:0];
	assign Funct = Instr[5:0];
	assign Shamt = Instr[10:6];
	assign IMM16 = Instr[15:0];
	assign Rd = Instr[15:11];
	assign Rt = Instr[20:16];
	assign Rs = Instr[25:21];
	assign Op = Instr[31:26];
	

	control control(

		.clk(clk),
		.rst(rst),
		.Op(Op),
		.Rt(Rt),
		.Funct(Funct),
		.RsCMPRt(RsCMPRt),
		.RsCMPZero(RsCMPZero),

		.PCSrc(PCSrc_ID), 

		.RegDst(RegDst_ID),

		.ALUSrcASel(ALUSrcASel_ID),
		.ALUSrcBSel(ALUSrcBSel_ID), 
		.ALUControl(ALUControl_ID),

		.DMemRead(DMemRead_ID),
		.DMemWrite(DMemWrite_ID),

		.DMemtoReg(DMemtoReg_ID),
		.RegWrite(RegWrite_ID)
	);


	
	assign RegRdaddr1_ID = Rs;
	assign RegRdaddr2_ID = Rt;
	mux #(5) MUXRegWtaddr(RegDst_ID,Rt,Rd,RegWtaddr_ID);
	
	
	assign ShamtZeroExtended_ID = {{27{1'b0}},Shamt};
	assign IMMSignExtended_ID = {{16{IMM16[15]}},IMM16};
	assign IMMZeroExtended_ID = {{16{1'b0}},IMM16};
	
	assign IMMSignExtendedShiftLeft2 = IMMSignExtended_ID << 2;
	alu BranchALU(PCPlus_ID,IMMSignExtendedShiftLeft2,5'd01,PCBranch_ID);
	assign PCJump_ID = {{PCPlus_ID[31:28]},{{2'b00,JumpIMM}<<2}};
	assign PCJR_ID = RegRdout1_ID;
	

	
	assign IF_ID_Flush = (PCSrc_ID != 2'b00);
	
	regfile regfile(clk,~rst,RegRdaddr1_ID,RegRdout1_ID,RegRdaddr2_ID,RegRdout2_ID,RegWtaddr_WB,RegWtin_WB,RegWrite_WB);
	
	compare compare1(RegRdout1_ID,RegRdout2_ID,RsCMPRt);
	compare compare2(RegRdout1_ID,0,RsCMPZero);
	
	
	hazard hazard(Rs,Rt,RegWtaddr_EX,DMemRead_EX,PCEn,IF_ID_En,ID_EX_Flush);

	IDEX IDEX(
		.clk(~clk),
		.en(1'b1),	
		.flush(ID_EX_Flush || rst),


		.PCPlus_in(PCPlus_ID),
		.RegRdout1_in(RegRdout1_ID),
		.RegRdout2_in(RegRdout2_ID),
		.IMMSignExtended_in(IMMSignExtended_ID),
		.IMMZeroExtended_in(IMMZeroExtended_ID),
		.ShamtZeroExtended_in(ShamtZeroExtended_ID),
		.Rs_in(Rs),
		.Rt_in(Rt),
		.RegWtaddr_in(RegWtaddr_ID),

		.PCPlus_out(PCPlus_EX),
		.RegRdout1_out(RegRdout1_EX),
		.RegRdout2_out(RegRdout2_EX),
		.IMMSignExtended_out(IMMSignExtended_EX),
		.IMMZeroExtended_out(IMMZeroExtended_EX),
		.ShamtZeroExtended_out(ShamtZeroExtended_EX),
		.Rs_out(Rs_EX),
		.Rt_out(Rt_EX),
		.RegWtaddr_out(RegWtaddr_EX),
		


		.RegDst_in(RegDst_ID),
		.ALUSrcASel_in(ALUSrcASel_ID),
		.ALUSrcBSel_in(ALUSrcBSel_ID), 
		.ALUControl_in(ALUControl_ID),
		.DMemRead_in(DMemRead_ID),
		.DMemWrite_in(DMemWrite_ID),
		.DMemtoReg_in(DMemtoReg_ID),
		.RegWrite_in(RegWrite_ID),

		.RegDst_out(RegDst_EX),
		.ALUSrcASel_out(ALUSrcASel_EX),
		.ALUSrcBSel_out(ALUSrcBSel_EX), 
		.ALUControl_out(ALUControl_EX),
		.DMemRead_out(DMemRead_EX),
		.DMemWrite_out(DMemWrite_EX),
		.DMemtoReg_out(DMemtoReg_EX),
		.RegWrite_out(RegWrite_EX)
	);

	forward forward(Rs_EX,Rt_EX,RegWrite_MEM,RegWrite_WB,RegWtaddr_MEM,RegWtaddr_WB,RegRdout1Sel_Forward_EX,RegRdout2Sel_Forward_EX);
	mux4 MUXRegRdout1FW(RegRdout1Sel_Forward_EX,RegRdout1_EX,RegWtin_WB,ALUResult_MEM,0,RegRdout1_Forward_EX);
	mux4 MUXRegRdout2FW(RegRdout2Sel_Forward_EX,RegRdout2_EX,RegWtin_WB,ALUResult_MEM,0,RegRdout2_Forward_EX);
	mux MUXALUSrcA(ALUSrcASel_EX,RegRdout1_Forward_EX,ShamtZeroExtended_EX,ALUSrcA_EX);
	mux4 MUXALUSrcB(ALUSrcBSel_EX,RegRdout2_Forward_EX,IMMSignExtended_EX,IMMZeroExtended_EX,0,ALUSrcB_EX);
	alu alu(ALUSrcA_EX,ALUSrcB_EX,ALUControl_EX,ALUResult_EX);

	EXMEM EXMEM(
		.clk(~clk),
		.en(1'b1),
		.flush(rst),


		.ALUResult_in(ALUResult_EX),
		.DMemin_in(RegRdout2_Forward_EX),
		.RegWtaddr_in(RegWtaddr_EX),

		.ALUResult_out(ALUResult_MEM),
		.DMemin_out(DMemin_MEM),
		.RegWtaddr_out(RegWtaddr_MEM),


		.DMemRead_in(DMemRead_EX),
		.DMemWrite_in(DMemWrite_EX),
		.DMemtoReg_in(DMemtoReg_EX),
		.RegWrite_in(RegWrite_EX),

		.DMemRead_out(DMemRead_MEM),
		.DMemWrite_out(DMemWrite_MEM),
		.DMemtoReg_out(DMemtoReg_MEM),
		.RegWrite_out(RegWrite_MEM)
	);

	assign DMemaddr_MEM = ALUResult_MEM;
	DMem DMem(clk,DMemWrite_MEM,DMemaddr_MEM >> 2,DMemin_MEM,DMemout_MEM);	

	MEMWB MEMWB(
		.clk(~clk),
		.en(1'b1),
		.flush(rst),


		.ALUResult_in(ALUResult_MEM),
		.DMemout_in(DMemout_MEM),
		.RegWtaddr_in(RegWtaddr_MEM),

		.ALUResult_out(ALUResult_WB),
		.DMemout_out(DMemout_WB),
		.RegWtaddr_out(RegWtaddr_WB),


		.DMemtoReg_in(DMemtoReg_MEM),
		.RegWrite_in(RegWrite_MEM),

		.DMemtoReg_out(DMemtoReg_WB),
		.RegWrite_out(RegWrite_WB)
	);


	mux MUXDMemtoReg(DMemtoReg_WB,ALUResult_WB,DMemout_WB,RegWtin_WB);
	
	
	

	
	

	
	
	
endmodule