data/full_repos/permissive/163115503/ultrasonic_distance/top.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/163115503/ultrasonic_distance/top.v:38: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'PIN_10'\n                                                                                     : ... In instance top\n  if (uS_since_trig < 580) PIN_10 = 1;\n                           ^~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/163115503/ultrasonic_distance/top.v:39: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'PIN_10'\n                                                                                     : ... In instance top\n  else PIN_10 = 0;\n       ^~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top (
    input CLK,
	input PIN_23,
	output PIN_22,
	output PIN_10,
	output LED,
    output USBPU
);

    assign USBPU = 0;

	reg trig_status;
	reg [51:0] clk_cycles;
	reg [51:0] last_trig_clk;
	reg [51:0] uS_since_trig;
	reg [51:0] distance;


	assign PIN_22 = trig_status;


    always @(posedge CLK) begin
		clk_cycles <= clk_cycles + 1;
		
		if (clk_cycles % 16000000 == 0) begin
			trig_status <= 1;
		end

		if (clk_cycles % 16000000 == 160) begin
			trig_status <= 0;
			last_trig_clk <= clk_cycles;
		end
    end

	always @(posedge PIN_23) begin

		uS_since_trig <= (clk_cycles - last_trig_clk) / 16;
		if (uS_since_trig < 580) PIN_10 = 1;
		else PIN_10 = 0;
	end
    
endmodule
module top (
    input CLK,
	input PIN_23,
	output PIN_22,
	output PIN_10,
	output LED,
    output USBPU
);


    assign USBPU = 0;

	reg trig_status;
	reg [51:0] clk_cycles;
	reg [51:0] last_trig_clk;
	reg [51:0] uS_since_trig;
	reg [51:0] distance;


	assign PIN_22 = trig_status;


    always @(posedge CLK) begin
		clk_cycles <= clk_cycles + 1;
		
		if (clk_cycles % 16000000 == 0) begin
			trig_status <= 1;
		end

		if (clk_cycles % 16000000 == 160) begin
			trig_status <= 0;
			last_trig_clk <= clk_cycles;
		end
    end

	always @(posedge PIN_23) begin

		uS_since_trig <= (clk_cycles - last_trig_clk) / 16;
		if (uS_since_trig < 580) PIN_10 = 1;
		else PIN_10 = 0;
	end
    
endmodule