data/full_repos/permissive/115837888/source-7400/74377-tb.v
 line:5: before: "tbassert"
1: b'%Error: data/full_repos/permissive/115837888/source-7400/74377-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74377-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74377-tb.v:6: Define or directive not defined: \'`TBASSERT_2R_METHOD\'\n`TBASSERT_2R_METHOD(tbassert2R)\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74377-tb.v:32: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("74377-tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74377-tb.v:33: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n#65\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n#4\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n#35\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n#35\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:187: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:199: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:201: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:231: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:239: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:244: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:246: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:260: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:262: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:267: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74377-tb.v:275: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: Exiting due to 5 error(s), 85 warning(s)\n'
module test;

`TBASSERT_METHOD(tbassert)
`TBASSERT_2R_METHOD(tbassert2R)

localparam WIDTH = 3;


reg Enable_bar;
reg [WIDTH-1:0] D;
reg Clk;


wire [WIDTH-1:0] Q;


ttl_74377 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .Enable_bar(Enable_bar),
  .D(D),
  .Clk(Clk),
  .Q(Q)
);

initial
begin
  reg [WIDTH-1:0] D_next;
  reg [WIDTH-1:0] Q_expected;
  integer i;

  $dumpfile("74377-tb.vcd");
  $dumpvars;



#65

  tbassert(Q === 3'bxxx, "Test 1");
#0

  Clk = 1'b0;
#7
  tbassert(Q === 3'bxxx, "Test 1");
#0

  D = 3'b000;
#25
  tbassert(Q === 3'bxxx, "Test 1");
#0

  Clk = 1'b1;
#50
  Clk = 1'b0;
#50
  Clk = 1'b1;
#50
  tbassert(Q === 3'bxxx, "Test 1");
#0

  Enable_bar = 1'b1;
#50
  tbassert(Q === 3'bxxx, "Test 1");
#0

  Enable_bar = 1'b0;
  Clk = 1'b0;
#25
  tbassert(Q === 3'bxxx, "Test 1");
#0

  Clk = 1'b1;
#2
  tbassert(Q === 3'bxxx, "Test 1");
#2

  tbassert(Q == 3'b000, "Test 1");
#140

  Clk = 1'b0;
#175
  tbassert(Q == 3'b000, "Test 2");
#0

  D = 3'b111;
#125
  tbassert(Q == 3'b000, "Test 3");
#0

  Clk = 1'b1;
#4
  tbassert(Q == 3'b000, "Test 3");
#2

  tbassert(Q == 3'b111, "Test 3");
#50

  Clk = 1'b0;
#125
  tbassert(Q == 3'b111, "Test 4");
#0

  D = 3'b101;
#15

  Clk = 1'b1;
#7
  tbassert(Q == 3'b101, "Test 5");
#140

  Clk = 1'b0;
#50
  tbassert(Q == 3'b101, "Test 6");
#0




  Enable_bar = 1'b1;

#25
  tbassert(Q == 3'b101, "Test 7");
#0

  D = 3'b011;
#15

  Clk = 1'b1;
#50
  Clk = 1'b0;
#50
  tbassert(Q == 3'b101, "Test 7");
#50
  Clk = 1'b1;
#15
  tbassert(Q == 3'b101, "Test 7");
#0

  Enable_bar = 1'b0;
#50
  Clk = 1'b0;
#50
  tbassert(Q == 3'b101, "Test 8");
#50

  Clk = 1'b1;
#15
  tbassert(Q == 3'b011, "Test 8");
#75

  Enable_bar = 1'b1;

#25
  tbassert(Q == 3'b011, "Test 9");
#0

  D = 3'b100;
#25
  Clk = 1'b0;
#50

  Clk = 1'b1;
#15
  tbassert(Q == 3'b011, "Test 9");
#35
  Clk = 1'b0;
#50
  Clk = 1'b1;
#15
  tbassert(Q == 3'b011, "Test 9");
#35
  Clk = 1'b0;
#0

  Enable_bar = 1'b0;
#25

  Clk = 1'b1;
#2
  tbassert(Q == 3'b011, "Test 10");
#5

  tbassert(Q == 3'b100, "Test 10");
#75

  Clk = 1'b0;
#80
  tbassert(Q == 3'b100, "Test 11");
#0

  Clk = 1'b1;
#50
  Clk = 1'b0;
#50
  tbassert(Q == 3'b100, "Test 12");
#0

  Enable_bar = 1'b1;
#75
  tbassert(Q == 3'b100, "Test 13");
#0
  Enable_bar = 1'b0;
#0



  D_next = 3'b100;

  for (i = 1; i <= 3; i++)
  begin
    Q_expected = D_next;

    case (i)
      1:
      begin
        D_next = 3'b110;
      end
      2:
      begin
        D_next = 3'b001;
      end
      3:
      begin
        D_next = 3'b111;
      end
    endcase
#20


    D = Q_expected;
#7
    Clk = 1'b1;
#20
    tbassert2R(Q == Q_expected, "Test", "1", (13 + i));
#0
    Clk = 1'b0;
#50
    tbassert2R(Q == Q_expected, "Test", "1", (13 + i));
#0

    Clk = 1'b1;
#7
    D = D_next;
#75
    tbassert2R(Q == Q_expected, "Test", "2", (13 + i));
#0
    Clk = 1'b0;
#25

    Enable_bar = 1'b1;

#25
    Clk = 1'b1;
#75
    tbassert2R(Q == Q_expected, "Test", "3", (13 + i));
#0
    Clk = 1'b0;
#50
    Clk = 1'b1;
#50
    tbassert2R(Q == Q_expected, "Test", "3", (13 + i));
#0
    Clk = 1'b0;
#25
    Enable_bar = 1'b0;
    D = 3'bzzz;
#25
    tbassert2R(Q == Q_expected, "Test", "3", (13 + i));

  end



  tbassert2R(Q == 3'b001, "Test", "3", 16);
#50
  $finish;
end

endmodule
module test;


`TBASSERT_METHOD(tbassert)
`TBASSERT_2R_METHOD(tbassert2R)

localparam WIDTH = 3;


reg Enable_bar;
reg [WIDTH-1:0] D;
reg Clk;


wire [WIDTH-1:0] Q;


ttl_74377 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .Enable_bar(Enable_bar),
  .D(D),
  .Clk(Clk),
  .Q(Q)
);

initial
begin
  reg [WIDTH-1:0] D_next;
  reg [WIDTH-1:0] Q_expected;
  integer i;

  $dumpfile("74377-tb.vcd");
  $dumpvars;



#65

  tbassert(Q === 3'bxxx, "Test 1");
#0

  Clk = 1'b0;
#7
  tbassert(Q === 3'bxxx, "Test 1");
#0

  D = 3'b000;
#25
  tbassert(Q === 3'bxxx, "Test 1");
#0

  Clk = 1'b1;
#50
  Clk = 1'b0;
#50
  Clk = 1'b1;
#50
  tbassert(Q === 3'bxxx, "Test 1");
#0

  Enable_bar = 1'b1;
#50
  tbassert(Q === 3'bxxx, "Test 1");
#0

  Enable_bar = 1'b0;
  Clk = 1'b0;
#25
  tbassert(Q === 3'bxxx, "Test 1");
#0

  Clk = 1'b1;
#2
  tbassert(Q === 3'bxxx, "Test 1");
#2

  tbassert(Q == 3'b000, "Test 1");
#140

  Clk = 1'b0;
#175
  tbassert(Q == 3'b000, "Test 2");
#0

  D = 3'b111;
#125
  tbassert(Q == 3'b000, "Test 3");
#0

  Clk = 1'b1;
#4
  tbassert(Q == 3'b000, "Test 3");
#2

  tbassert(Q == 3'b111, "Test 3");
#50

  Clk = 1'b0;
#125
  tbassert(Q == 3'b111, "Test 4");
#0

  D = 3'b101;
#15

  Clk = 1'b1;
#7
  tbassert(Q == 3'b101, "Test 5");
#140

  Clk = 1'b0;
#50
  tbassert(Q == 3'b101, "Test 6");
#0




  Enable_bar = 1'b1;

#25
  tbassert(Q == 3'b101, "Test 7");
#0

  D = 3'b011;
#15

  Clk = 1'b1;
#50
  Clk = 1'b0;
#50
  tbassert(Q == 3'b101, "Test 7");
#50
  Clk = 1'b1;
#15
  tbassert(Q == 3'b101, "Test 7");
#0

  Enable_bar = 1'b0;
#50
  Clk = 1'b0;
#50
  tbassert(Q == 3'b101, "Test 8");
#50

  Clk = 1'b1;
#15
  tbassert(Q == 3'b011, "Test 8");
#75

  Enable_bar = 1'b1;

#25
  tbassert(Q == 3'b011, "Test 9");
#0

  D = 3'b100;
#25
  Clk = 1'b0;
#50

  Clk = 1'b1;
#15
  tbassert(Q == 3'b011, "Test 9");
#35
  Clk = 1'b0;
#50
  Clk = 1'b1;
#15
  tbassert(Q == 3'b011, "Test 9");
#35
  Clk = 1'b0;
#0

  Enable_bar = 1'b0;
#25

  Clk = 1'b1;
#2
  tbassert(Q == 3'b011, "Test 10");
#5

  tbassert(Q == 3'b100, "Test 10");
#75

  Clk = 1'b0;
#80
  tbassert(Q == 3'b100, "Test 11");
#0

  Clk = 1'b1;
#50
  Clk = 1'b0;
#50
  tbassert(Q == 3'b100, "Test 12");
#0

  Enable_bar = 1'b1;
#75
  tbassert(Q == 3'b100, "Test 13");
#0
  Enable_bar = 1'b0;
#0



  D_next = 3'b100;

  for (i = 1; i <= 3; i++)
  begin
    Q_expected = D_next;

    case (i)
      1:
      begin
        D_next = 3'b110;
      end
      2:
      begin
        D_next = 3'b001;
      end
      3:
      begin
        D_next = 3'b111;
      end
    endcase
#20


    D = Q_expected;
#7
    Clk = 1'b1;
#20
    tbassert2R(Q == Q_expected, "Test", "1", (13 + i));
#0
    Clk = 1'b0;
#50
    tbassert2R(Q == Q_expected, "Test", "1", (13 + i));
#0

    Clk = 1'b1;
#7
    D = D_next;
#75
    tbassert2R(Q == Q_expected, "Test", "2", (13 + i));
#0
    Clk = 1'b0;
#25

    Enable_bar = 1'b1;

#25
    Clk = 1'b1;
#75
    tbassert2R(Q == Q_expected, "Test", "3", (13 + i));
#0
    Clk = 1'b0;
#50
    Clk = 1'b1;
#50
    tbassert2R(Q == Q_expected, "Test", "3", (13 + i));
#0
    Clk = 1'b0;
#25
    Enable_bar = 1'b0;
    D = 3'bzzz;
#25
    tbassert2R(Q == Q_expected, "Test", "3", (13 + i));

  end



  tbassert2R(Q == 3'b001, "Test", "3", 16);
#50
  $finish;
end

endmodule