data/full_repos/permissive/158922207/Verilog Design/modules/ALUControl.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/ALUControl.v\n%Error: Exiting due to 3 error(s)\n'
module ALUControl(Control, ALUOp, FunctCode);
input [1:0] ALUOp;
input [5:0] FunctCode;
output reg[3:0] Control;
wire [7:0] alufunc;
assign alufunc = {ALUOp, FunctCode};
always @(alufunc) begin
    casez (alufunc) 
        8'b00??????: Control <= 2;
        8'b01??????: Control <= 6;
        8'b11??????: Control <= 0;
        8'b10100000: Control <= 2;
        8'b10100010: Control <= 6;
        8'b10100100: Control <= 0;
        8'b10100101: Control <= 1;
        8'b10101010: Control <= 7;
    endcase
end
endmodule
module ALUControl(Control, ALUOp, FunctCode);

input [1:0] ALUOp;
input [5:0] FunctCode;
output reg[3:0] Control;
wire [7:0] alufunc;
assign alufunc = {ALUOp, FunctCode};
always @(alufunc) begin
    casez (alufunc) 
        8'b00??????: Control <= 2;
        8'b01??????: Control <= 6;
        8'b11??????: Control <= 0;
        8'b10100000: Control <= 2;
        8'b10100010: Control <= 6;
        8'b10100100: Control <= 0;
        8'b10100101: Control <= 1;
        8'b10101010: Control <= 7;
    endcase
end
endmodule