data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog/control.v
1: b"%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog/control.v:49: Cannot find file containing module: 'instruction_decoder'\n    instruction_decoder #(\n    ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog,data/full_repos/permissive/206437232/instruction_decoder\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog,data/full_repos/permissive/206437232/instruction_decoder.v\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog,data/full_repos/permissive/206437232/instruction_decoder.sv\n             instruction_decoder\n             instruction_decoder.v\n             instruction_decoder.sv\n             obj_dir/instruction_decoder\n             obj_dir/instruction_decoder.v\n             obj_dir/instruction_decoder.sv\n%Error: Exiting due to 1 error(s)\n"
module control
    #( parameter    NB_INSTRUC      = 16,
                    NB_OPCODE       = 5,
                    NB_OPERAND      = 11,
                    NB_ADDR         = 11
    )
    (

        input wire                         i_clk,
        input wire                         i_rst,
        input wire [NB_INSTRUC - 1 : 0]    i_instruc,

        output wire [NB_OPERAND - 1 : 0]    o_operand,
        output wire [NB_ADDR -1 : 0]        o_addr,

        output wire [1 : 0]                 o_SelA,
        output wire                         o_SelB,
        output wire                         o_WrAcc,
        output wire                         o_op,
        output wire                         o_WrRam,
        output wire                         o_RdRam
    );

    wire [NB_OPCODE - 1 : 0] opcode;
    wire WrPC;

    reg [NB_ADDR - 1 : 0] pc;

    assign opcode = i_instruc[NB_INSTRUC - 1 -: NB_OPCODE];
    assign o_operand[NB_OPERAND - 1 : 0] = i_instruc[NB_OPERAND - 1 : 0];



    always @(posedge i_clk) begin
        if (!i_rst) begin
            pc <= {NB_ADDR{1'b0}};
        end
        else if (WrPC) begin
            pc <= pc + 1'b1;
        end
    end

    assign o_addr = pc;



    instruction_decoder #(
        .NB_OPCODE  (NB_OPCODE)
    )
    u_instruction_decoder (

        .i_rst      (i_rst),
        .i_opcode   (opcode),

        .o_WrPC     (WrPC),
        .o_SelA     (o_SelA),
        .o_SelB     (o_SelB),
        .o_WrAcc    (o_WrAcc),
        .o_op       (o_op),
        .o_WrRam    (o_WrRam),
        .o_RdRam    (o_RdRam)
    );

endmodule
module control
    #( parameter    NB_INSTRUC      = 16,
                    NB_OPCODE       = 5,
                    NB_OPERAND      = 11,
                    NB_ADDR         = 11
    )
    (

        input wire                         i_clk,
        input wire                         i_rst,
        input wire [NB_INSTRUC - 1 : 0]    i_instruc,

        output wire [NB_OPERAND - 1 : 0]    o_operand,
        output wire [NB_ADDR -1 : 0]        o_addr,

        output wire [1 : 0]                 o_SelA,
        output wire                         o_SelB,
        output wire                         o_WrAcc,
        output wire                         o_op,
        output wire                         o_WrRam,
        output wire                         o_RdRam
    );


    wire [NB_OPCODE - 1 : 0] opcode;
    wire WrPC;

    reg [NB_ADDR - 1 : 0] pc;

    assign opcode = i_instruc[NB_INSTRUC - 1 -: NB_OPCODE];
    assign o_operand[NB_OPERAND - 1 : 0] = i_instruc[NB_OPERAND - 1 : 0];



    always @(posedge i_clk) begin
        if (!i_rst) begin
            pc <= {NB_ADDR{1'b0}};
        end
        else if (WrPC) begin
            pc <= pc + 1'b1;
        end
    end

    assign o_addr = pc;



    instruction_decoder #(
        .NB_OPCODE  (NB_OPCODE)
    )
    u_instruction_decoder (

        .i_rst      (i_rst),
        .i_opcode   (opcode),

        .o_WrPC     (WrPC),
        .o_SelA     (o_SelA),
        .o_SelB     (o_SelB),
        .o_WrAcc    (o_WrAcc),
        .o_op       (o_op),
        .o_WrRam    (o_WrRam),
        .o_RdRam    (o_RdRam)
    );

endmodule