data/full_repos/permissive/135077285/signExtend.v
1: b'%Warning-WIDTH: data/full_repos/permissive/135077285/signExtend.v:9: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'entrada\' generates 16 bits.\n                                                                   : ... In instance signExtend\n      aux = 32\'b0 + entrada;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module signExtend (
  input wire [15:0] entrada,
  output wire [31:0] saida
);

  reg [31:0] aux;

  always @(*) begin
      aux = 32'b0 + entrada;
  end

  assign saida = aux;
endmodule
module signExtend (
  input wire [15:0] entrada,
  output wire [31:0] saida
);


  reg [31:0] aux;

  always @(*) begin
      aux = 32'b0 + entrada;
  end

  assign saida = aux;
endmodule