data/full_repos/permissive/174323821/hdl/ver/jtframe_romrq_rdy_check.v
1: b'%Warning-WIDTH: data/full_repos/permissive/174323821/hdl/ver/jtframe_romrq_rdy_check.v:42: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 4 bits.\n                                                                                         : ... In instance jtframe_romrq_rdy_check\n        if( ba_ack & ~busy ) begin\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/174323821/hdl/ver/jtframe_romrq_rdy_check.v:46: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 4 bits.\n                                                                                         : ... In instance jtframe_romrq_rdy_check\n        if( ba_rdy & ~ackd ) begin\n        ^~\n%Error: Exiting due to 2 warning(s)\n'
module jtframe_romrq_rdy_check(
    input       rst,
    input       clk,
    input [3:0] ba_rd,
    input [3:0] ba_wr,
    input [3:0] ba_ack,
    input [3:0] ba_rdy
);

reg  [3:0] busy, ackd, last_rq;
wire [3:0] rq = ba_rd | ba_wr;
wire [3:0] rq_edge = rq & ~last_rq;

always @(posedge clk, posedge rst) begin
    if( rst ) begin
        busy <= 0;
        ackd <= 0;
        last_rq <= 0;
    end else begin
        last_rq <= rq;
        busy <= (busy | rq_edge) & ~ba_ack;
        if( ba_ack & ~busy ) begin
            $display("Warning: ACK from SDRAM but there was no active request (busy=%4b, ack=%4b)", busy, ba_ack );
        end
        ackd <= (ackd & ~rq_edge & ~ba_rdy ) | ba_ack;
        if( ba_rdy & ~ackd ) begin
            $display("\nError: RDY from SDRAM but there was no acknowledgement (rdy=%4b, ackd=%4b)\n", ba_rdy, ackd );
            $finish;
        end
    end
end

endmodule
module jtframe_romrq_rdy_check(
    input       rst,
    input       clk,
    input [3:0] ba_rd,
    input [3:0] ba_wr,
    input [3:0] ba_ack,
    input [3:0] ba_rdy
);


reg  [3:0] busy, ackd, last_rq;
wire [3:0] rq = ba_rd | ba_wr;
wire [3:0] rq_edge = rq & ~last_rq;

always @(posedge clk, posedge rst) begin
    if( rst ) begin
        busy <= 0;
        ackd <= 0;
        last_rq <= 0;
    end else begin
        last_rq <= rq;
        busy <= (busy | rq_edge) & ~ba_ack;
        if( ba_ack & ~busy ) begin
            $display("Warning: ACK from SDRAM but there was no active request (busy=%4b, ack=%4b)", busy, ba_ack );
        end
        ackd <= (ackd & ~rq_edge & ~ba_rdy ) | ba_ack;
        if( ba_rdy & ~ackd ) begin
            $display("\nError: RDY from SDRAM but there was no acknowledgement (rdy=%4b, ackd=%4b)\n", ba_rdy, ackd );
            $finish;
        end
    end
end

endmodule