data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v
 line:40: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n      forever #2 clk = ~clk;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n         #13 rst_n  = 1\'b0;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n         #14 rst_n  = 1\'b1;\n         ^\n%Error: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars();\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:37: Unsupported or unknown PLI call: $monitor\n      $monitor("Time=%0t ns\\t LFSR=0x%h",$time,prg_out);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:45: syntax error, unexpected \'@\'\n        @(negedge clk)\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #20\n      ^\n%Error: data/full_repos/permissive/110151336/lab_06/src/07_lfsr/simulation/lfsr_tb.v:54: syntax error, unexpected end\n   end\n   ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module lfsr_tb;

   reg        clk;
   reg        rst_n;
   wire [7:0] prg_out;
   integer    seq_len;
   
   lfsr l_inst
   (

         .prg_out ( prg_out ),

         .clk     ( clk     ),
         .rst_n   ( rst_n   )
   );
   
   initial begin
      clk = 0;
      forever #2 clk = ~clk;
   end

   task async_rst;
      begin
         $display("---------- Start async_reset at %0t ns ----------\n",$time);
         #13 rst_n  = 1'b0;
         #14 rst_n  = 1'b1;
         $display("---------- Finish async_reset at %0t ns ----------\n",$time);
      end
   endtask
 
   initial begin
      $dumpvars();
      $monitor("Time=%0t ns\t LFSR=0x%h",$time,prg_out);
      rst_n    = 1'b1;
      seq_len  = 0;
      async_rst();
      #20

      forever 
      begin
        @(negedge clk)
          begin
             seq_len = seq_len+1;
             if(prg_out == 8'hfc)begin
                $display("---------- Sequence lenght =%0d ----------\n",seq_len);        
                $finish;
             end
          end
      end
   end
   
endmodule
module lfsr_tb;


   reg        clk;
   reg        rst_n;
   wire [7:0] prg_out;
   integer    seq_len;
   
   lfsr l_inst
   (

         .prg_out ( prg_out ),

         .clk     ( clk     ),
         .rst_n   ( rst_n   )
   );
   
   initial begin
      clk = 0;
      forever #2 clk = ~clk;
   end

   task async_rst;
      begin
         $display("---------- Start async_reset at %0t ns ----------\n",$time);
         #13 rst_n  = 1'b0;
         #14 rst_n  = 1'b1;
         $display("---------- Finish async_reset at %0t ns ----------\n",$time);
      end
   endtask
 
   initial begin
      $dumpvars();
      $monitor("Time=%0t ns\t LFSR=0x%h",$time,prg_out);
      rst_n    = 1'b1;
      seq_len  = 0;
      async_rst();
      #20

      forever 
      begin
        @(negedge clk)
          begin
             seq_len = seq_len+1;
             if(prg_out == 8'hfc)begin
                $display("---------- Sequence lenght =%0d ----------\n",seq_len);        
                $finish;
             end
          end
      end
   end
   
endmodule