data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/hdl/top_lib/top_data_test.v
1: b"%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/hdl/top_lib/top_data_test.v:67: Cannot find file containing module: 'par8_receiver'\npar8_receiver par8_receiver_inst\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/hdl/top_lib,data/full_repos/permissive/150947952/par8_receiver\n             data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/hdl/top_lib,data/full_repos/permissive/150947952/par8_receiver.v\n             data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/hdl/top_lib,data/full_repos/permissive/150947952/par8_receiver.sv\n             par8_receiver\n             par8_receiver.v\n             par8_receiver.sv\n             obj_dir/par8_receiver\n             obj_dir/par8_receiver.v\n             obj_dir/par8_receiver.sv\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/hdl/top_lib/top_data_test.v:82: Cannot find file containing module: 'par8_transmitter'\npar8_transmitter par8_transmitter_inst\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module top_data_test
(
    input wire clk_100mhz,
    input wire reset_n,


    input wire bus_clk,
    inout wire [7:0] bus_data,
    input wire bus_rnw,

    output reg [3:0] led_out,
    output wire led0_r,
    output reg led0_g,
    output reg led1_r
);




wire reset;


wire [7:0] bus_data_out;

wire [7:0] rxd_data;
wire rxd_data_ready;

reg [7:0] txd_data;
reg txd_valid;
wire trans_ready_next;

assign bus_data = (bus_rnw==1) ? bus_data_out : 8'bz;
assign reset = ~reset_n;
assign led0_r = reset;



par8_receiver par8_receiver_inst
(
    .clk(clk_100mhz),
    .reset(reset),


    .bus_clk(bus_clk),
    .bus_data(bus_data),
    .bus_rnw(bus_rnw),


    .rxd_data(rxd_data),
    .rxd_data_ready(rxd_data_ready)
);

par8_transmitter par8_transmitter_inst
(
    .clk(clk_100mhz),
    .reset(reset),


    .txd_data(txd_data),
    .valid(txd_valid),


    .bus_clk(bus_clk),
    .bus_rnw(bus_rnw),


    .bus_data(bus_data_out),
    .ready_next(trans_ready_next)
);





localparam IDLE             = 0;
localparam CHECK            = 1;
localparam RECV_DONE        = 2;
localparam SEND_CHECK       = 3;
localparam SEND_DONE        = 4;

reg [3:0] state;
reg [7:0] expected_val;
reg [3:0] led_val;
reg [7:0] send_count;

always @ (posedge clk_100mhz)
begin
    if (reset) begin
        state <= IDLE;
        expected_val <= 0;
        led_val <= 0;
        led_out <= 0;
        led0_g <= 0;
        led1_r <= 0;
        txd_data <= 0;
        txd_valid <= 0;
    end else begin
        case (state)
            IDLE : begin
                led_val <= 1;
                expected_val <= 0;
                state <= CHECK;
            end
            CHECK : begin
                if (rxd_data_ready) begin
                    led_out <= rxd_data[3:0];
                    if (rxd_data != expected_val) begin
                        led_val <= 0;
                        led1_r <= led1_r + 1;
                    end else begin

                        led0_g <= led0_g + 1;
                    end

                    if (expected_val == 255) begin
                        led_out[3:0] <= led_val[3:0];
                        state <= RECV_DONE;
                    end else begin
                        expected_val <= expected_val + 1;
                        state <= CHECK;
                    end
                end
            end
            RECV_DONE : begin
                send_count <= 0; 
                txd_valid <= 0;
                state <= SEND_CHECK;
            end
            SEND_CHECK : begin
                if (trans_ready_next) begin
                    txd_data <= send_count;
                    txd_valid <= 1;
                    send_count <= send_count + 1;
                    if (send_count == 255) begin
                        state <= SEND_DONE;
                    end
                end else begin
                    txd_valid <= 0;
                end
            end
            SEND_DONE : begin
                led_out[1] <= 1;
                state <= SEND_DONE;
            end
            default : begin
                state <= IDLE;
            end
        endcase
    end
end


endmodule
module top_data_test
(
    input wire clk_100mhz,
    input wire reset_n,


    input wire bus_clk,
    inout wire [7:0] bus_data,
    input wire bus_rnw,

    output reg [3:0] led_out,
    output wire led0_r,
    output reg led0_g,
    output reg led1_r
);





wire reset;


wire [7:0] bus_data_out;

wire [7:0] rxd_data;
wire rxd_data_ready;

reg [7:0] txd_data;
reg txd_valid;
wire trans_ready_next;

assign bus_data = (bus_rnw==1) ? bus_data_out : 8'bz;
assign reset = ~reset_n;
assign led0_r = reset;



par8_receiver par8_receiver_inst
(
    .clk(clk_100mhz),
    .reset(reset),


    .bus_clk(bus_clk),
    .bus_data(bus_data),
    .bus_rnw(bus_rnw),


    .rxd_data(rxd_data),
    .rxd_data_ready(rxd_data_ready)
);

par8_transmitter par8_transmitter_inst
(
    .clk(clk_100mhz),
    .reset(reset),


    .txd_data(txd_data),
    .valid(txd_valid),


    .bus_clk(bus_clk),
    .bus_rnw(bus_rnw),


    .bus_data(bus_data_out),
    .ready_next(trans_ready_next)
);





localparam IDLE             = 0;
localparam CHECK            = 1;
localparam RECV_DONE        = 2;
localparam SEND_CHECK       = 3;
localparam SEND_DONE        = 4;

reg [3:0] state;
reg [7:0] expected_val;
reg [3:0] led_val;
reg [7:0] send_count;

always @ (posedge clk_100mhz)
begin
    if (reset) begin
        state <= IDLE;
        expected_val <= 0;
        led_val <= 0;
        led_out <= 0;
        led0_g <= 0;
        led1_r <= 0;
        txd_data <= 0;
        txd_valid <= 0;
    end else begin
        case (state)
            IDLE : begin
                led_val <= 1;
                expected_val <= 0;
                state <= CHECK;
            end
            CHECK : begin
                if (rxd_data_ready) begin
                    led_out <= rxd_data[3:0];
                    if (rxd_data != expected_val) begin
                        led_val <= 0;
                        led1_r <= led1_r + 1;
                    end else begin

                        led0_g <= led0_g + 1;
                    end

                    if (expected_val == 255) begin
                        led_out[3:0] <= led_val[3:0];
                        state <= RECV_DONE;
                    end else begin
                        expected_val <= expected_val + 1;
                        state <= CHECK;
                    end
                end
            end
            RECV_DONE : begin
                send_count <= 0; 
                txd_valid <= 0;
                state <= SEND_CHECK;
            end
            SEND_CHECK : begin
                if (trans_ready_next) begin
                    txd_data <= send_count;
                    txd_valid <= 1;
                    send_count <= send_count + 1;
                    if (send_count == 255) begin
                        state <= SEND_DONE;
                    end
                end else begin
                    txd_valid <= 0;
                end
            end
            SEND_DONE : begin
                led_out[1] <= 1;
                state <= SEND_DONE;
            end
            default : begin
                state <= IDLE;
            end
        endcase
    end
end


endmodule