data/full_repos/permissive/135295301/common/ip/precision_counter_1.0/hdl/precision_counter_v1_0_S00_AXI.v
1: b'%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/precision_counter_1.0/hdl/precision_counter_v1_0_S00_AXI.v:304: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                                                             : ... In instance precision_counter_v1_0_S00_AXI\n       axi_araddr  <= 32\'b0;\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module precision_counter_v1_0_S00_AXI #
	(






		parameter integer C_S_AXI_DATA_WIDTH	= 32,

		parameter integer C_S_AXI_ADDR_WIDTH	= 8
	)
	(
	    output wire ap_done,



		input wire  S_AXI_ACLK,

		input wire  S_AXI_ARESETN,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



		input wire [2 : 0] S_AXI_AWPROT,


		input wire  S_AXI_AWVALID,


		output wire  S_AXI_AWREADY,

		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


		input wire  S_AXI_WVALID,


		output wire  S_AXI_WREADY,


		output wire [1 : 0] S_AXI_BRESP,


		output wire  S_AXI_BVALID,


		input wire  S_AXI_BREADY,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



		input wire [2 : 0] S_AXI_ARPROT,


		input wire  S_AXI_ARVALID,


		output wire  S_AXI_ARREADY,

		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


		output wire [1 : 0] S_AXI_RRESP,


		output wire  S_AXI_RVALID,


		input wire  S_AXI_RREADY
	);


	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;






	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 2;




	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg_ctl;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg_v;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg_t;

	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;


	wire is_running;
	wire is_finished;
	assign is_running = (slv_reg_ctl[0] == 1'b1) && (slv_reg_v != 0);
	assign ap_done = (slv_reg_ctl[0] == 1'b1) && (slv_reg_v == 0);
	assign is_finished = (ap_done == 1'b1) && (slv_reg_ctl[0] == 1'b1);
	
	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin




	          axi_awready <= 1'b1;
	        end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
	        begin




	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      slv_reg_ctl <= 0;
	      slv_reg_v   <= 0;
	    end 
	  else begin
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr )
	          'h00: begin slv_reg_ctl <= {{C_S_AXI_DATA_WIDTH - 1{1'b0}}, S_AXI_WDATA[0]}; slv_reg_t <= 0; end
	          'h0C: begin slv_reg_ctl <= 0; slv_reg_ctl <= 0; end
	          'h20: slv_reg_v   <= S_AXI_WDATA; 
	          default : begin
	                      slv_reg_v <= (is_running ? (slv_reg_v - 1) : slv_reg_v);
	                      slv_reg_ctl <= slv_reg_ctl;
	                    end
	        endcase
	      end
	    else begin
          slv_reg_v <= (is_running ? (slv_reg_v - 1) : slv_reg_v);
          slv_reg_t <= (is_finished ? (slv_reg_t + 1) : slv_reg_t);
	    end
	  end
	end    







	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    




	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

	      case ( axi_araddr )
	        'h00   : reg_data_out <= slv_reg_ctl;
	        'h04   : reg_data_out <= 'b1;
	        'h08   : reg_data_out <= 'b1;
	        'h0C   : reg_data_out <= {{C_S_AXI_DATA_WIDTH - 1{1'b0}}, ap_done};
	        'h10   : reg_data_out <= slv_reg_t;
	        'h20   : reg_data_out <= slv_reg_v;
	        default : reg_data_out <= 0;
	      endcase
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    



	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;
	        end   
	    end
	end    

	endmodule
module precision_counter_v1_0_S00_AXI #
	(






		parameter integer C_S_AXI_DATA_WIDTH	= 32,

		parameter integer C_S_AXI_ADDR_WIDTH	= 8
	)
	(
	    output wire ap_done,



		input wire  S_AXI_ACLK,

		input wire  S_AXI_ARESETN,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



		input wire [2 : 0] S_AXI_AWPROT,


		input wire  S_AXI_AWVALID,


		output wire  S_AXI_AWREADY,

		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


		input wire  S_AXI_WVALID,


		output wire  S_AXI_WREADY,


		output wire [1 : 0] S_AXI_BRESP,


		output wire  S_AXI_BVALID,


		input wire  S_AXI_BREADY,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



		input wire [2 : 0] S_AXI_ARPROT,


		input wire  S_AXI_ARVALID,


		output wire  S_AXI_ARREADY,

		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


		output wire [1 : 0] S_AXI_RRESP,


		output wire  S_AXI_RVALID,


		input wire  S_AXI_RREADY
	);



	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;






	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 2;




	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg_ctl;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg_v;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg_t;

	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;


	wire is_running;
	wire is_finished;
	assign is_running = (slv_reg_ctl[0] == 1'b1) && (slv_reg_v != 0);
	assign ap_done = (slv_reg_ctl[0] == 1'b1) && (slv_reg_v == 0);
	assign is_finished = (ap_done == 1'b1) && (slv_reg_ctl[0] == 1'b1);
	
	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin




	          axi_awready <= 1'b1;
	        end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
	        begin




	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      slv_reg_ctl <= 0;
	      slv_reg_v   <= 0;
	    end 
	  else begin
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr )
	          'h00: begin slv_reg_ctl <= {{C_S_AXI_DATA_WIDTH - 1{1'b0}}, S_AXI_WDATA[0]}; slv_reg_t <= 0; end
	          'h0C: begin slv_reg_ctl <= 0; slv_reg_ctl <= 0; end
	          'h20: slv_reg_v   <= S_AXI_WDATA; 
	          default : begin
	                      slv_reg_v <= (is_running ? (slv_reg_v - 1) : slv_reg_v);
	                      slv_reg_ctl <= slv_reg_ctl;
	                    end
	        endcase
	      end
	    else begin
          slv_reg_v <= (is_running ? (slv_reg_v - 1) : slv_reg_v);
          slv_reg_t <= (is_finished ? (slv_reg_t + 1) : slv_reg_t);
	    end
	  end
	end    







	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    




	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

	      case ( axi_araddr )
	        'h00   : reg_data_out <= slv_reg_ctl;
	        'h04   : reg_data_out <= 'b1;
	        'h08   : reg_data_out <= 'b1;
	        'h0C   : reg_data_out <= {{C_S_AXI_DATA_WIDTH - 1{1'b0}}, ap_done};
	        'h10   : reg_data_out <= slv_reg_t;
	        'h20   : reg_data_out <= slv_reg_v;
	        default : reg_data_out <= 0;
	      endcase
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    



	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;
	        end   
	    end
	end    

	endmodule