data/full_repos/permissive/204736068/SoM/RTL/misc/delay.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/204736068/SoM/RTL/misc/delay.v:70: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                               : ... Top module \'delay_bit\'\nmodule delay_bit #(\n       ^~~~~~~~~\n                                                                               : ... Top module \'delay_bus\'\nmodule delay_bus #(\n       ^~~~~~~~~\n                                                                               : ... Top module \'delay_toggle\'\nmodule delay_toggle #(\n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module delay_bus #(
	parameter integer DELAY = 1,
	parameter integer WIDTH = 1
)(
	input  wire [WIDTH-1:0] d,
	output wire [WIDTH-1:0] q,
	input  wire clk
);

	genvar i;
	reg [WIDTH-1:0] dl[0:DELAY-1];

	always @(posedge clk)
		dl[0] <= d;

	generate
		for (i=1; i<DELAY; i=i+1)
			always @(posedge clk)
				dl[i] <= dl[i-1];
	endgenerate

	assign q = dl[DELAY-1];

endmodule
module delay_bus #(
	parameter integer DELAY = 1,
	parameter integer WIDTH = 1
)(
	input  wire [WIDTH-1:0] d,
	output wire [WIDTH-1:0] q,
	input  wire clk
);


	genvar i;
	reg [WIDTH-1:0] dl[0:DELAY-1];

	always @(posedge clk)
		dl[0] <= d;

	generate
		for (i=1; i<DELAY; i=i+1)
			always @(posedge clk)
				dl[i] <= dl[i-1];
	endgenerate

	assign q = dl[DELAY-1];

endmodule