data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v
 line:40: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:29: Unsupported or unknown PLI call: $monitor\n  $monitor("time:[%0t ns], State:[%d], Fail_Count:[%d], PassUserReg:[%h], PassMemReg:[%h], wren:[%b], Data_Out:[%h]",\n  ^~~~~~~~\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:40: syntax error, unexpected \'@\'\n  #10 @(posedge clk) rst =1; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #10 @(posedge clk) rst =1; \n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:41: syntax error, unexpected \'@\'\n  #10 @(posedge clk) Data_In_Load = 1; Data_In = 17\'h01476;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10 @(posedge clk) Data_In_Load = 1; Data_In = 17\'h01476;\n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:42: syntax error, unexpected \'@\'\n  #10 @(posedge clk) Data_In_Load = 0; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #10 @(posedge clk) Data_In_Load = 0; \n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:43: syntax error, unexpected \'@\'\n  #40 @(posedge clk) Memory_Data_In = 16\'h2456;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #40 @(posedge clk) Memory_Data_In = 16\'h2456;\n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:44: syntax error, unexpected \'@\'\n  #10 @(posedge clk) Data_In = 16\'h2456;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #10 @(posedge clk) Data_In = 16\'h2456;\n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:45: syntax error, unexpected \'@\'\n  #10 @(posedge clk) Data_In_Load = 1; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10 @(posedge clk) Data_In_Load = 1; \n  ^\n%Error: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:46: syntax error, unexpected \'@\'\n  #10 @(posedge clk) Data_In_Load = 0; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/AccessControl/AccessControlFsm_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #10 @(posedge clk) Data_In_Load = 0; \n  ^\n%Error: Exiting due to 8 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module AccessControlFsm_tb(); 
	reg [0:0]  clk, rst, Data_In_Load; 
	reg [16:0] Data_In;
	reg [15:0] Memory_Data_In;


	wire [0:0]  _Access_Grant, _wren; 
	wire [15:0] _Address, _Data_Out; 

	AccessControlFsm fsm1(
		.clk(clk),
		.rst(rst), 
		._Data_In(Data_In), 
		._Data_In_Load(Data_In_Load), 
		._Memory_In(Memory_Data_In),  
		.Access_Grant(_Access_Grant),
		.Address(_Address), 
		.wren(_wren),
		.Data_Out(_Data_Out)); 

	always begin
		#10 clk = ~clk; 
	end

	initial begin
		$monitor("time:[%0t ns], State:[%d], Fail_Count:[%d], PassUserReg:[%h], PassMemReg:[%h], wren:[%b], Data_Out:[%h]",
			$time, 
			fsm1.State, 
			fsm1.Fail_Count, 
			fsm1.Password_User_Reg, 
			fsm1.Password_Memory_Reg, 
			_wren,
			_Data_Out);

		clk = 1; 
		rst = 0; 
		#10 @(posedge clk) rst =1; 
		#10 @(posedge clk) Data_In_Load = 1; Data_In = 17'h01476;
		#10 @(posedge clk) Data_In_Load = 0; 
		#40 @(posedge clk) Memory_Data_In = 16'h2456;
		#10 @(posedge clk) Data_In = 16'h2456;
		#10 @(posedge clk) Data_In_Load = 1; 
		#10 @(posedge clk) Data_In_Load = 0; 
	end
endmodule
module AccessControlFsm_tb();
 
	reg [0:0]  clk, rst, Data_In_Load; 
	reg [16:0] Data_In;
	reg [15:0] Memory_Data_In;


	wire [0:0]  _Access_Grant, _wren; 
	wire [15:0] _Address, _Data_Out; 

	AccessControlFsm fsm1(
		.clk(clk),
		.rst(rst), 
		._Data_In(Data_In), 
		._Data_In_Load(Data_In_Load), 
		._Memory_In(Memory_Data_In),  
		.Access_Grant(_Access_Grant),
		.Address(_Address), 
		.wren(_wren),
		.Data_Out(_Data_Out)); 

	always begin
		#10 clk = ~clk; 
	end

	initial begin
		$monitor("time:[%0t ns], State:[%d], Fail_Count:[%d], PassUserReg:[%h], PassMemReg:[%h], wren:[%b], Data_Out:[%h]",
			$time, 
			fsm1.State, 
			fsm1.Fail_Count, 
			fsm1.Password_User_Reg, 
			fsm1.Password_Memory_Reg, 
			_wren,
			_Data_Out);

		clk = 1; 
		rst = 0; 
		#10 @(posedge clk) rst =1; 
		#10 @(posedge clk) Data_In_Load = 1; Data_In = 17'h01476;
		#10 @(posedge clk) Data_In_Load = 0; 
		#40 @(posedge clk) Memory_Data_In = 16'h2456;
		#10 @(posedge clk) Data_In = 16'h2456;
		#10 @(posedge clk) Data_In_Load = 1; 
		#10 @(posedge clk) Data_In_Load = 0; 
	end
endmodule