data/full_repos/permissive/149070951/tests/03-test-rs232/rs232.v
data/verilator_xmls/a357db03-5e1c-4c0e-8f74-8bdf82caf9f6.xml
module leds(input wire RTS,
            input wire DTR,
            output wire LED0,
            output wire LED7);

assign {LED0, LED7} = {DTR, RTS};

endmodule
module leds(input wire RTS,
            input wire DTR,
            output wire LED0,
            output wire LED7);


assign {LED0, LED7} = {DTR, RTS};

endmodule