data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor/f15_rise_decay.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor/f15_rise_decay.v:66: Cannot find file containing module: 'delay_bit'\n delay_bit #(2) dl_ena (ena_0, ena_2, clk);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor,data/full_repos/permissive/214858095/delay_bit\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor,data/full_repos/permissive/214858095/delay_bit.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor,data/full_repos/permissive/214858095/delay_bit.sv\n             delay_bit\n             delay_bit.v\n             delay_bit.sv\n             obj_dir/delay_bit\n             obj_dir/delay_bit.v\n             obj_dir/delay_bit.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor/f15_rise_decay.v:70: Cannot find file containing module: 'delay_bus'\n delay_bus #(2, WIDTH) dl_in (in_0, in_2, clk);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor/f15_rise_decay.v:73: Cannot find file containing module: 'DSP48E1'\n DSP48E1 #(\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module f15_rise_decay #(
	parameter integer WIDTH = 9
)(
	input  wire [WIDTH-1:0] in_0,
	output reg  [WIDTH-1:0] out_5,
	input  wire [15:0] k_0,
	input  wire ena_0,
	input  wire mode_0,
	input  wire [15:0] rng,
	input  wire clk,
	input  wire rst
);


	reg mode_1;
	reg [4:0] inmode_1;

	wire [WIDTH-1:0] in_2;
	wire ena_2;
	wire [6:0] opmode_2;
	reg  [3:0] alumode_2;

	wire [47:0] pout_4;
	wire pmatch_4;








	always @(posedge clk)
	begin
		mode_1 <= mode_0;

		if (mode_0)
			inmode_1 <= 5'b00000;
		else
			inmode_1 <= 5'b01100;

		if (mode_1)
			alumode_2 <= 4'b0011;
		else
			alumode_2 <= 4'b0000;
	end


	delay_bit #(2) dl_ena (ena_0, ena_2, clk);
	assign opmode_2  = ena_2 ? 7'b0110101 : 7'b0110000;


	delay_bus #(2, WIDTH) dl_in (in_0, in_2, clk);


	DSP48E1 #(
		.A_INPUT("DIRECT"),
		.B_INPUT("DIRECT"),
		.USE_DPORT("TRUE"),
		.USE_MULT("MULTIPLY"),
		.AUTORESET_PATDET("NO_RESET"),
		.MASK({1'b1, {(31-WIDTH){1'b0}}, {(WIDTH+16){1'b1}}}),
		.PATTERN(48'h000000000000),
		.SEL_MASK("MASK"),
		.SEL_PATTERN("PATTERN"),
		.USE_PATTERN_DETECT("PATDET"),
		.ACASCREG(1),
		.ADREG(1),
		.ALUMODEREG(1),
		.AREG(1),
		.BCASCREG(2),
		.BREG(2),
		.CARRYINREG(1),
		.CARRYINSELREG(1),
		.CREG(1),
		.DREG(1),
		.INMODEREG(1),
		.MREG(1),
		.OPMODEREG(1),
		.PREG(1),
		.USE_SIMD("ONE48")
	)
	dsp_exp_I (
		.PATTERNDETECT(pmatch_4),
		.P(pout_4),
		.ACIN(30'h0),
		.BCIN(18'h0),
		.CARRYCASCIN(1'h0),
		.MULTSIGNIN(1'h0),
		.PCIN(48'h000000000000),
		.ALUMODE(alumode_2),
		.CARRYINSEL(3'h0),
		.CEINMODE(1'b1),
		.CLK(clk),
		.INMODE(inmode_1),
		.OPMODE(opmode_2),
		.RSTINMODE(rst),
		.A({{(30-WIDTH){1'b0}}, in_0}),
		.B({ 2'h0, k_0}),
		.C({{(32-WIDTH){1'b0}}, in_2, rng}),
		.CARRYIN(1'b0),
		.D({{(24-WIDTH){1'b0}}, 1'b1, {WIDTH{1'b0}}}),
		.CEA1(1'b0),
		.CEA2(1'b1),
		.CEAD(1'b1),
		.CEALUMODE(1'b1),
		.CEB1(1'b1),
		.CEB2(1'b1),
		.CEC(1'b1),
		.CECARRYIN(1'b1),
		.CECTRL(1'b1),
		.CED(1'b1),
		.CEM(1'b1),
		.CEP(1'b1),
		.RSTA(rst),
		.RSTALLCARRYIN(rst),
		.RSTALUMODE(rst),
		.RSTB(rst),
		.RSTC(rst),
		.RSTCTRL(rst),
		.RSTD(rst),
		.RSTM(rst),
		.RSTP(rst)
	);





	always @(posedge clk)
	begin
		if (rst == 1)
			out_5 <= 0;
		else
			if (pout_4[47] == 1)
				out_5 <= {WIDTH{1'b0}};
			else if (pmatch_4 == 0)
				out_5 <= {WIDTH{1'b1}};
			else
				out_5 <= pout_4[WIDTH+15:16];
	end

endmodule
module f15_rise_decay #(
	parameter integer WIDTH = 9
)(
	input  wire [WIDTH-1:0] in_0,
	output reg  [WIDTH-1:0] out_5,
	input  wire [15:0] k_0,
	input  wire ena_0,
	input  wire mode_0,
	input  wire [15:0] rng,
	input  wire clk,
	input  wire rst
);



	reg mode_1;
	reg [4:0] inmode_1;

	wire [WIDTH-1:0] in_2;
	wire ena_2;
	wire [6:0] opmode_2;
	reg  [3:0] alumode_2;

	wire [47:0] pout_4;
	wire pmatch_4;








	always @(posedge clk)
	begin
		mode_1 <= mode_0;

		if (mode_0)
			inmode_1 <= 5'b00000;
		else
			inmode_1 <= 5'b01100;

		if (mode_1)
			alumode_2 <= 4'b0011;
		else
			alumode_2 <= 4'b0000;
	end


	delay_bit #(2) dl_ena (ena_0, ena_2, clk);
	assign opmode_2  = ena_2 ? 7'b0110101 : 7'b0110000;


	delay_bus #(2, WIDTH) dl_in (in_0, in_2, clk);


	DSP48E1 #(
		.A_INPUT("DIRECT"),
		.B_INPUT("DIRECT"),
		.USE_DPORT("TRUE"),
		.USE_MULT("MULTIPLY"),
		.AUTORESET_PATDET("NO_RESET"),
		.MASK({1'b1, {(31-WIDTH){1'b0}}, {(WIDTH+16){1'b1}}}),
		.PATTERN(48'h000000000000),
		.SEL_MASK("MASK"),
		.SEL_PATTERN("PATTERN"),
		.USE_PATTERN_DETECT("PATDET"),
		.ACASCREG(1),
		.ADREG(1),
		.ALUMODEREG(1),
		.AREG(1),
		.BCASCREG(2),
		.BREG(2),
		.CARRYINREG(1),
		.CARRYINSELREG(1),
		.CREG(1),
		.DREG(1),
		.INMODEREG(1),
		.MREG(1),
		.OPMODEREG(1),
		.PREG(1),
		.USE_SIMD("ONE48")
	)
	dsp_exp_I (
		.PATTERNDETECT(pmatch_4),
		.P(pout_4),
		.ACIN(30'h0),
		.BCIN(18'h0),
		.CARRYCASCIN(1'h0),
		.MULTSIGNIN(1'h0),
		.PCIN(48'h000000000000),
		.ALUMODE(alumode_2),
		.CARRYINSEL(3'h0),
		.CEINMODE(1'b1),
		.CLK(clk),
		.INMODE(inmode_1),
		.OPMODE(opmode_2),
		.RSTINMODE(rst),
		.A({{(30-WIDTH){1'b0}}, in_0}),
		.B({ 2'h0, k_0}),
		.C({{(32-WIDTH){1'b0}}, in_2, rng}),
		.CARRYIN(1'b0),
		.D({{(24-WIDTH){1'b0}}, 1'b1, {WIDTH{1'b0}}}),
		.CEA1(1'b0),
		.CEA2(1'b1),
		.CEAD(1'b1),
		.CEALUMODE(1'b1),
		.CEB1(1'b1),
		.CEB2(1'b1),
		.CEC(1'b1),
		.CECARRYIN(1'b1),
		.CECTRL(1'b1),
		.CED(1'b1),
		.CEM(1'b1),
		.CEP(1'b1),
		.RSTA(rst),
		.RSTALLCARRYIN(rst),
		.RSTALUMODE(rst),
		.RSTB(rst),
		.RSTC(rst),
		.RSTCTRL(rst),
		.RSTD(rst),
		.RSTM(rst),
		.RSTP(rst)
	);





	always @(posedge clk)
	begin
		if (rst == 1)
			out_5 <= 0;
		else
			if (pout_4[47] == 1)
				out_5 <= {WIDTH{1'b0}};
			else if (pmatch_4 == 0)
				out_5 <= {WIDTH{1'b1}};
			else
				out_5 <= pout_4[WIDTH+15:16];
	end

endmodule