data/full_repos/permissive/143278/ivltests/real_invalid_ops.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/143278/ivltests/real_invalid_ops.v:31: Value too wide for 32-bits expected in this context 2\n  wire r_rep = {2.0{var1}};\n                ^~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_invalid_ops.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/real_invalid_ops.v:65: Value too wide for 32-bits expected in this context 2\n    bvar = {2.0{var1}};\n            ^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module top;
  real var1, var2;
  reg [7:0] bvar;
  reg result;

  wire r_a = &var1;
  wire r_o = |var1;
  wire r_x = ^var1;
  wire r_na = ~&var1;
  wire r_no = ~|var1;
  wire r_xn1 = ~^var1;
  wire r_xn2 = ^~var1;

  wire r_b_a = var1 & var2;
  wire r_b_o = var1 | var2;
  wire r_b_x = var1 ^ var2;
  wire r_b_na = var1 ~& var2;
  wire r_b_no = var1 ~| var2;
  wire r_b_xn1 = var1 ~^ var2;
  wire r_b_xn2 = var1 ^~ var2;

  wire r_eeq = var1 === var2;
  wire r_neeq = var1 !== var2;

  wire r_ls = var1 << var2;
  wire r_als = var1 <<< var2;
  wire r_rs = var1 >> var2;
  wire r_ars = var1 >>> var2;

  wire r_con = {var1};
  wire r_rep = {2.0{var1}};

  initial begin
    var1 = 1.0;
    var2 = 2.0;

    #1;


    result = &var1;
    result = |var1;
    result = ^var1;
    result = ~&var1;
    result = ~|var1;
    result = ~^var1;
    result = ^~var1;

    result = var1 & var2;
    result = var1 | var2;
    result = var1 ^ var2;
    result = var1 ~& var2;
    result = var1 ~| var2;
    result = var1 ~^ var2;
    result = var1 ^~ var2;

    result = var1 === var2;
    result = var1 !== var2;

    bvar = var1 << var2;
    bvar = var1 <<< var2;
    bvar = var1 >> var2;
    bvar = var1 >>> var2;

    bvar = {var1};
    bvar = {2.0{var1}};

    $display("Failed");
  end
endmodule
module top;

  real var1, var2;
  reg [7:0] bvar;
  reg result;

  wire r_a = &var1;
  wire r_o = |var1;
  wire r_x = ^var1;
  wire r_na = ~&var1;
  wire r_no = ~|var1;
  wire r_xn1 = ~^var1;
  wire r_xn2 = ^~var1;

  wire r_b_a = var1 & var2;
  wire r_b_o = var1 | var2;
  wire r_b_x = var1 ^ var2;
  wire r_b_na = var1 ~& var2;
  wire r_b_no = var1 ~| var2;
  wire r_b_xn1 = var1 ~^ var2;
  wire r_b_xn2 = var1 ^~ var2;

  wire r_eeq = var1 === var2;
  wire r_neeq = var1 !== var2;

  wire r_ls = var1 << var2;
  wire r_als = var1 <<< var2;
  wire r_rs = var1 >> var2;
  wire r_ars = var1 >>> var2;

  wire r_con = {var1};
  wire r_rep = {2.0{var1}};

  initial begin
    var1 = 1.0;
    var2 = 2.0;

    #1;


    result = &var1;
    result = |var1;
    result = ^var1;
    result = ~&var1;
    result = ~|var1;
    result = ~^var1;
    result = ^~var1;

    result = var1 & var2;
    result = var1 | var2;
    result = var1 ^ var2;
    result = var1 ~& var2;
    result = var1 ~| var2;
    result = var1 ~^ var2;
    result = var1 ^~ var2;

    result = var1 === var2;
    result = var1 !== var2;

    bvar = var1 << var2;
    bvar = var1 <<< var2;
    bvar = var1 >> var2;
    bvar = var1 >>> var2;

    bvar = {var1};
    bvar = {2.0{var1}};

    $display("Failed");
  end
endmodule