data/full_repos/permissive/181665138/verilog/capitolo_v/Registro_Multifunzionale.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Registro_Multifunzionale.v:34: syntax error, unexpected <=, expecting '='\n    assign z3_z0 <= OUTR;\n                 ^~\n%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Registro_Multifunzionale.v:36: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(reset_ == 0) #1 OUTR <= 'B0000;\n                    ^~\n%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Registro_Multifunzionale.v:42: syntax error, unexpected endcase\n        endcase\n        ^~~~~~~\n%Error: Cannot continue\n"
module Registro_Carica_Parallelo_TraslaSinistro(z3_z0, x3_x0, b0, clock, reset_);
    input clock, reset_;
    input [3:0] x3_x0;
    input b0;
    output [3:0] z3_z0;

    reg [3: 0] OUTR;
    assign z3_z0 <= OUTR;

    always @(reset_ == 0) #1 OUTR <= 'B0000;

    always @(posedge clock) if (reset_ == 1) #3
        casex(b0)
            'B0: OUTR<=x3_x0;
            'B1: OUTR<={OUTR[2:0], 1'B0}
        endcase
endmodule
module Registro_Carica_Parallelo_TraslaSinistro(z3_z0, x3_x0, b0, clock, reset_);

    input clock, reset_;
    input [3:0] x3_x0;
    input b0;
    output [3:0] z3_z0;

    reg [3: 0] OUTR;
    assign z3_z0 <= OUTR;

    always @(reset_ == 0) #1 OUTR <= 'B0000;

    always @(posedge clock) if (reset_ == 1) #3
        casex(b0)
            'B0: OUTR<=x3_x0;
            'B1: OUTR<={OUTR[2:0], 1'B0}
        endcase
endmodule