data/full_repos/permissive/139831595/hw/source/fifo_parser_lit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/139831595/hw/source/fifo_parser_lit.v:44: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                   : ... In instance fifo_parser_lit\n    ram[write_ptr]=din;\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/139831595/hw/source/fifo_parser_lit.v:50: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                   : ... In instance fifo_parser_lit\n    fifo_out=ram[read_ptr];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/139831595/hw/source/fifo_parser_lit.v:56: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                   : ... In instance fifo_parser_lit\n                ram[write_ptr]=din;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/139831595/hw/source/fifo_parser_lit.v:57: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                   : ... In instance fifo_parser_lit\n    fifo_out=ram[read_ptr];\n                ^\n%Error: Exiting due to 4 warning(s)\n'
module fifo_parser_lit
#(
    parameter WIDTH=85,
    parameter DEPTH=8
)
(
    input clk,
	input srst,
	

	output full,
	input[WIDTH-1:0] din,
	input wr_en,
	
	output empty,
	output[WIDTH-1:0] dout,
	input rd_en,
	
	output valid,
	output prog_full,
	output wr_rst_busy,
	output rd_rst_busy
);
reg [WIDTH-1:0]fifo_out;
reg [WIDTH-1:0]ram[7:0];
reg [3:0]read_ptr,write_ptr,counter;
wire fifo_half,fifo_full;

always@(posedge clk)
  if(srst)
    begin
    read_ptr<=0;
    write_ptr<=0;
    counter<=0;
    end
  else
    case({rd_en,wr_en})
      2'b00:
            counter=counter;     
      2'b01:                        
            begin
				ram[write_ptr]=din;
				counter=counter+1;
				write_ptr=(write_ptr==7)?0:write_ptr+1;
            end
      2'b10:                       
            begin
				fifo_out=ram[read_ptr];
				counter=counter-1;
				read_ptr=(read_ptr==7)?0:read_ptr+1;
            end
      2'b11:                  
            begin
                ram[write_ptr]=din;
				fifo_out=ram[read_ptr];
                write_ptr=(write_ptr==7)?0:write_ptr+1;
                read_ptr=(read_ptr==7)?0:read_ptr+1;
            end
        endcase

assign empty=(counter==0); 
assign fifo_half=(counter>=3);
assign fifo_full=(counter==8);
assign dout=fifo_out;
assign prog_full=fifo_half;
assign full=fifo_full;

endmodule
module fifo_parser_lit
#(
    parameter WIDTH=85,
    parameter DEPTH=8
)
(
    input clk,
	input srst,
	

	output full,
	input[WIDTH-1:0] din,
	input wr_en,
	
	output empty,
	output[WIDTH-1:0] dout,
	input rd_en,
	
	output valid,
	output prog_full,
	output wr_rst_busy,
	output rd_rst_busy
);

reg [WIDTH-1:0]fifo_out;
reg [WIDTH-1:0]ram[7:0];
reg [3:0]read_ptr,write_ptr,counter;
wire fifo_half,fifo_full;

always@(posedge clk)
  if(srst)
    begin
    read_ptr<=0;
    write_ptr<=0;
    counter<=0;
    end
  else
    case({rd_en,wr_en})
      2'b00:
            counter=counter;     
      2'b01:                        
            begin
				ram[write_ptr]=din;
				counter=counter+1;
				write_ptr=(write_ptr==7)?0:write_ptr+1;
            end
      2'b10:                       
            begin
				fifo_out=ram[read_ptr];
				counter=counter-1;
				read_ptr=(read_ptr==7)?0:read_ptr+1;
            end
      2'b11:                  
            begin
                ram[write_ptr]=din;
				fifo_out=ram[read_ptr];
                write_ptr=(write_ptr==7)?0:write_ptr+1;
                read_ptr=(read_ptr==7)?0:read_ptr+1;
            end
        endcase

assign empty=(counter==0); 
assign fifo_half=(counter>=3);
assign fifo_full=(counter==8);
assign dout=fifo_out;
assign prog_full=fifo_half;
assign full=fifo_full;

endmodule