data/full_repos/permissive/218103167/code/s5/si570_controller/initial_config.v
 line:53: before: ")"
1: b"%Error: data/full_repos/permissive/218103167/code/s5/si570_controller/initial_config.v:53: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/218103167/code/s5/si570_controller/initial_config.v:77: syntax error, unexpected always\nalways@(posedge iCLK or negedge iRST_n)\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module initial_config(

iCLK,
iRST_n,
oINITIAL_START,
iINITIAL_ENABLE,
);









input iCLK;
input iRST_n;
output oINITIAL_START;
input	iINITIAL_ENABLE;




wire oINITIAL_START;
reg [`REG_SIZE-1:0] cnt;




always@(posedge iCLK or negedge iRST_n)
	begin
		if (!iRST_n)
			begin 
				cnt <= 0;
			end
		else if (cnt == 21'h1fffff)

			begin
				cnt <=21'h1fffff;

			end
		else
			begin
				cnt <= cnt + 1;	
			end
	end
	
	
assign oINITIAL_START = ((cnt == 21'h1ffffe)&iINITIAL_ENABLE) ? 1'b1: 1'b0;


endmodule
module initial_config(

iCLK,
iRST_n,
oINITIAL_START,
iINITIAL_ENABLE,
);










input iCLK;
input iRST_n;
output oINITIAL_START;
input	iINITIAL_ENABLE;




wire oINITIAL_START;
reg [`REG_SIZE-1:0] cnt;




always@(posedge iCLK or negedge iRST_n)
	begin
		if (!iRST_n)
			begin 
				cnt <= 0;
			end
		else if (cnt == 21'h1fffff)

			begin
				cnt <=21'h1fffff;

			end
		else
			begin
				cnt <= cnt + 1;	
			end
	end
	
	
assign oINITIAL_START = ((cnt == 21'h1ffffe)&iINITIAL_ENABLE) ? 1'b1: 1'b0;


endmodule