data/full_repos/permissive/157101210/regfile.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/157101210/regfile.v:158: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'regfile\'\nmodule regfile\n       ^~~~~~~\n                                                                     : ... Top module \'mux32to1by1\'\nmodule mux32to1by1\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/157101210/regfile.v:127: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'enable\' generates 1 bits.\n                                                                  : ... In instance regfile.decoder\n    assign out = enable<<address; \n                       ^~\n%Error: Exiting due to 2 warning(s)\n'
module register32zero
(
output reg [31:0] q,
input      [31:0] d,
input       wrenable,
input       clk
);
integer i;
	always @(negedge clk) begin
		q[31:0] <= 32'h00000000;
	end
endmodule
module register32zero
(
output reg [31:0] q,
input      [31:0] d,
input       wrenable,
input       clk
);

integer i;
	always @(negedge clk) begin
		q[31:0] <= 32'h00000000;
	end
endmodule