data/full_repos/permissive/153414067/Top_module.v
'utf-8' codec can't decode byte 0xf3 in position 79: invalid continuation byte
1: b'%Warning-WIDTH: data/full_repos/permissive/153414067/Top_module.v:28: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                    : ... In instance Top_module\n  assign mem_addr = {5\'b0, ver_addr, hor_addr};  \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/153414067/Top_module.v:34: Cannot find file containing module: \'VGA\'\n  VGA VGA(\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/153414067,data/full_repos/permissive/153414067/VGA\n             data/full_repos/permissive/153414067,data/full_repos/permissive/153414067/VGA.v\n             data/full_repos/permissive/153414067,data/full_repos/permissive/153414067/VGA.sv\n             VGA\n             VGA.v\n             VGA.sv\n             obj_dir/VGA\n             obj_dir/VGA.v\n             obj_dir/VGA.sv\n%Error: data/full_repos/permissive/153414067/Top_module.v:75: Cannot find file containing module: \'SRAM_256kx16\'\n  SRAM_256kx16 SRAM_256kx16(\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/153414067/Top_module.v:107: Cannot find file containing module: \'Accelo\'\n  Accelo Accelo(\n  ^~~~~~\n%Error: data/full_repos/permissive/153414067/Top_module.v:119: Cannot find file containing module: \'ball_movement\'\n  ball_movement ball(\n  ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module Top_module(
	input clk,
	input rstbt,
	
	output [8:0] aio,
	
	output [2:0] bo,
	input bi,
	
	output [17:0] mem_addr,
	inout [5:0] mem_data,
	output mem_wen,
	output mem_lbn,
	output sram_csn,
	output sram_oen,
	output sdram_csn
    );
	 
	 assign sdram_csn = 1;
	 
	 wire [7:0] ver_addr;
	 wire [6:0] hor_addr;
	 wire read;
	 wire write;
	 
	 assign mem_addr = {5'b0, ver_addr, hor_addr};
	 assign mem_wen = ~write;
	 assign mem_lbn = ~(read || write);
	 assign sram_csn = ~(read || write);
	 assign sram_oen = ~(read || write);
	 
	 VGA VGA(
		.clk(clk),
		.rst(~rstbt),
		.data(mem_data),
		.io(aio),
		.hor_addr(hor_addr),
		.ver_addr(ver_addr),
		.read(read),
		.write(write)
		);
	 
	 wire [6:0] ball_hor;
	 wire [9:0] ball_ver;
	 
	 wire [7:0] platform0_ver;
	 wire [6:0] platform0_hor;
	 wire [5:0] platform0_width;
	 
	 wire [6:0] platform1_ver;
	 wire [6:0] platform1_hor;
	 wire [4:0] platform1_width;
	 
	 wire [5:0] platform2_ver;
	 wire [6:0] platform2_hor;
	 wire [4:0] platform2_width;
	 
	 wire [4:0] platform3_ver;
	 wire [6:0] platform3_hor;
	 wire [4:0] platform3_width;
	 
	 wire [7:0] out_platform_ver;
	 wire [6:0] out_platform_hor;
	 wire [5:0] out_platform_width;
	 
	 wire right;
	 wire left;
	 wire middle;
	 
	 wire over;

	 
	 SRAM_256kx16 SRAM_256kx16(
		.clk(clk),
		.rst(~rstbt),
		.write(write),
		.mem_data(mem_data),
		
		.ball_hor(ball_hor),
		.ball_ver(ball_ver),
		
		.platform0_ver(platform0_ver),
		.platform0_hor(platform0_hor),
		.platform0_width(platform0_width),
		
		.platform1_ver(platform1_ver),
		.platform1_hor(platform1_hor),
		.platform1_width(platform1_width),
		
		.platform2_ver(platform2_ver),
		.platform2_hor(platform2_hor),
		.platform2_width(platform2_width),
		
		.platform3_ver(platform3_ver),
		.platform3_hor(platform3_hor),
		.platform3_width(platform3_width),
		
		.out_platform_ver(out_platform_ver),
		.out_platform_hor(out_platform_hor),
		.out_platform_width(out_platform_width),
		
		.over(over)
		);
		
	 Accelo Accelo(
		.clk(clk),
		.rst(~rstbt),
		
		.bo(bo),
		.bi(bi),
		
		.right(right),
		.left(left),
		.middle(middle)
		);
		
	 ball_movement ball(
		.clk(clk),
		.rst(~rstbt),
		
		.right(right),
		.left(left),
		.middle(middle),
		
		.ball_ver(ball_ver),
		.ball_hor(ball_hor),
		
		.platform0_ver(platform0_ver),
		.platform0_hor(platform0_hor),
		.platform0_width(platform0_width),
		
		.platform1_ver(platform1_ver),
		.platform1_hor(platform1_hor),
		.platform1_width(platform1_width),
		
		.platform2_ver(platform2_ver),
		.platform2_hor(platform2_hor),
		.platform2_width(platform2_width),
		
		.platform3_ver(platform3_ver),
		.platform3_hor(platform3_hor),
		.platform3_width(platform3_width),
		
		.out_platform_ver(out_platform_ver),
		.out_platform_hor(out_platform_hor),
		.out_platform_width(out_platform_width),
		

		.over(over)
		);


endmodule
module Top_module(
	input clk,
	input rstbt,
	
	output [8:0] aio,
	
	output [2:0] bo,
	input bi,
	
	output [17:0] mem_addr,
	inout [5:0] mem_data,
	output mem_wen,
	output mem_lbn,
	output sram_csn,
	output sram_oen,
	output sdram_csn
    );

	 
	 assign sdram_csn = 1;
	 
	 wire [7:0] ver_addr;
	 wire [6:0] hor_addr;
	 wire read;
	 wire write;
	 
	 assign mem_addr = {5'b0, ver_addr, hor_addr};
	 assign mem_wen = ~write;
	 assign mem_lbn = ~(read || write);
	 assign sram_csn = ~(read || write);
	 assign sram_oen = ~(read || write);
	 
	 VGA VGA(
		.clk(clk),
		.rst(~rstbt),
		.data(mem_data),
		.io(aio),
		.hor_addr(hor_addr),
		.ver_addr(ver_addr),
		.read(read),
		.write(write)
		);
	 
	 wire [6:0] ball_hor;
	 wire [9:0] ball_ver;
	 
	 wire [7:0] platform0_ver;
	 wire [6:0] platform0_hor;
	 wire [5:0] platform0_width;
	 
	 wire [6:0] platform1_ver;
	 wire [6:0] platform1_hor;
	 wire [4:0] platform1_width;
	 
	 wire [5:0] platform2_ver;
	 wire [6:0] platform2_hor;
	 wire [4:0] platform2_width;
	 
	 wire [4:0] platform3_ver;
	 wire [6:0] platform3_hor;
	 wire [4:0] platform3_width;
	 
	 wire [7:0] out_platform_ver;
	 wire [6:0] out_platform_hor;
	 wire [5:0] out_platform_width;
	 
	 wire right;
	 wire left;
	 wire middle;
	 
	 wire over;

	 
	 SRAM_256kx16 SRAM_256kx16(
		.clk(clk),
		.rst(~rstbt),
		.write(write),
		.mem_data(mem_data),
		
		.ball_hor(ball_hor),
		.ball_ver(ball_ver),
		
		.platform0_ver(platform0_ver),
		.platform0_hor(platform0_hor),
		.platform0_width(platform0_width),
		
		.platform1_ver(platform1_ver),
		.platform1_hor(platform1_hor),
		.platform1_width(platform1_width),
		
		.platform2_ver(platform2_ver),
		.platform2_hor(platform2_hor),
		.platform2_width(platform2_width),
		
		.platform3_ver(platform3_ver),
		.platform3_hor(platform3_hor),
		.platform3_width(platform3_width),
		
		.out_platform_ver(out_platform_ver),
		.out_platform_hor(out_platform_hor),
		.out_platform_width(out_platform_width),
		
		.over(over)
		);
		
	 Accelo Accelo(
		.clk(clk),
		.rst(~rstbt),
		
		.bo(bo),
		.bi(bi),
		
		.right(right),
		.left(left),
		.middle(middle)
		);
		
	 ball_movement ball(
		.clk(clk),
		.rst(~rstbt),
		
		.right(right),
		.left(left),
		.middle(middle),
		
		.ball_ver(ball_ver),
		.ball_hor(ball_hor),
		
		.platform0_ver(platform0_ver),
		.platform0_hor(platform0_hor),
		.platform0_width(platform0_width),
		
		.platform1_ver(platform1_ver),
		.platform1_hor(platform1_hor),
		.platform1_width(platform1_width),
		
		.platform2_ver(platform2_ver),
		.platform2_hor(platform2_hor),
		.platform2_width(platform2_width),
		
		.platform3_ver(platform3_ver),
		.platform3_hor(platform3_hor),
		.platform3_width(platform3_width),
		
		.out_platform_ver(out_platform_ver),
		.out_platform_hor(out_platform_hor),
		.out_platform_width(out_platform_width),
		

		.over(over)
		);


endmodule