data/full_repos/permissive/120024308/src/cpu/decoder.v
 line:62: before: ":"
1: b"%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:62: Define or directive not defined: '`J'\n   `J:\n   ^~\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:62: syntax error, unexpected ':', expecting endcase\n   `J:\n     ^\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:66: Define or directive not defined: '`JR'\n   `JR:\n   ^~~\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:67: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:71: Define or directive not defined: '`JAL'\n   `JAL:\n   ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:72: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:76: Define or directive not defined: '`JALR'\n   `JALR:\n   ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:77: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:82: Define or directive not defined: '`SW'\n   `SW:\n   ^~~\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:83: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:86: Define or directive not defined: '`LW'\n   `LW:\n   ^~~\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:87: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/decoder.v:92: syntax error, unexpected ':', expecting clocking\n   default:\n          ^\n%Error: Cannot continue\n"
module Decoder #(parameter R_ADDR_SIZE=5, parameter OP_SIZE=6, parameter INSTRUCTION_SIZE = 32, parameter INMEDIATE_SIZE = 16, parameter ZERO_PAD = 11)
   (
    input wire [INSTRUCTION_SIZE-1:0] instruction,
    output wire [OP_SIZE-1:0] 	      operation,
    output wire [INMEDIATE_SIZE-1:0]  inmediate,
    output wire [R_ADDR_SIZE-1:0]     destination,
    output wire [R_ADDR_SIZE-1:0]     read0,
    output wire [R_ADDR_SIZE-1:0]     read1,
    output wire [R_ADDR_SIZE-1:0]     read2,
    output reg 			      branch_taken,
    output reg 			      link,
    output reg 			      from_register,
    output reg 			      ram_enable_write,
    output reg 			      ram_enable_read
    );

   assign operation = instruction[INSTRUCTION_SIZE-1:INSTRUCTION_SIZE-OP_SIZE];
   assign read0 = instruction[ZERO_PAD+R_ADDR_SIZE-1:ZERO_PAD];
   assign read1 = instruction[ZERO_PAD+2*R_ADDR_SIZE-1:ZERO_PAD+R_ADDR_SIZE];
   assign read2 = instruction[ZERO_PAD+3*R_ADDR_SIZE-1:ZERO_PAD+2*R_ADDR_SIZE];
   assign destination = read2;
   assign inmediate = instruction[INMEDIATE_SIZE-1:0];

   always @ ( * )
     begin
	branch_taken = 0;
	link = 0;
	from_register = 0;
        ram_enable_write = 0;
	ram_enable_read = 0;


	case (operation)
	  `J:
	    begin
	       branch_taken = 1;
	    end
	  `JR:
	    begin
	       branch_taken = 1;
	       from_register = 1;
	    end
	  `JAL:
	    begin
	       branch_taken = 1;
	       link = 1;
	    end
	  `JALR:
	    begin
	       branch_taken = 1;
	       link = 1;
	       from_register = 1;
	    end
	  `SW:
	    begin
	       ram_enable_write = 1;
	    end
	  `LW:
	    begin
	       ram_enable_read = 1;
	    end


	  default:
	    begin
	       branch_taken = 0;
	       link=0;
	       from_register = 0;
	       ram_enable_write = 0;
	       ram_enable_read = 0;
	    end

	endcase
     end
endmodule
module Decoder #(parameter R_ADDR_SIZE=5, parameter OP_SIZE=6, parameter INSTRUCTION_SIZE = 32, parameter INMEDIATE_SIZE = 16, parameter ZERO_PAD = 11)
   (
    input wire [INSTRUCTION_SIZE-1:0] instruction,
    output wire [OP_SIZE-1:0] 	      operation,
    output wire [INMEDIATE_SIZE-1:0]  inmediate,
    output wire [R_ADDR_SIZE-1:0]     destination,
    output wire [R_ADDR_SIZE-1:0]     read0,
    output wire [R_ADDR_SIZE-1:0]     read1,
    output wire [R_ADDR_SIZE-1:0]     read2,
    output reg 			      branch_taken,
    output reg 			      link,
    output reg 			      from_register,
    output reg 			      ram_enable_write,
    output reg 			      ram_enable_read
    );


   assign operation = instruction[INSTRUCTION_SIZE-1:INSTRUCTION_SIZE-OP_SIZE];
   assign read0 = instruction[ZERO_PAD+R_ADDR_SIZE-1:ZERO_PAD];
   assign read1 = instruction[ZERO_PAD+2*R_ADDR_SIZE-1:ZERO_PAD+R_ADDR_SIZE];
   assign read2 = instruction[ZERO_PAD+3*R_ADDR_SIZE-1:ZERO_PAD+2*R_ADDR_SIZE];
   assign destination = read2;
   assign inmediate = instruction[INMEDIATE_SIZE-1:0];

   always @ ( * )
     begin
	branch_taken = 0;
	link = 0;
	from_register = 0;
        ram_enable_write = 0;
	ram_enable_read = 0;


	case (operation)
	  `J:
	    begin
	       branch_taken = 1;
	    end
	  `JR:
	    begin
	       branch_taken = 1;
	       from_register = 1;
	    end
	  `JAL:
	    begin
	       branch_taken = 1;
	       link = 1;
	    end
	  `JALR:
	    begin
	       branch_taken = 1;
	       link = 1;
	       from_register = 1;
	    end
	  `SW:
	    begin
	       ram_enable_write = 1;
	    end
	  `LW:
	    begin
	       ram_enable_read = 1;
	    end


	  default:
	    begin
	       branch_taken = 0;
	       link=0;
	       from_register = 0;
	       ram_enable_write = 0;
	       ram_enable_read = 0;
	    end

	endcase
     end
endmodule