data/full_repos/permissive/143278/ivltests/module3.12A.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/module3.12A.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(out1 != 32\'h11223344)\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/module3.12A.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(out2 != 32\'h44332211)\n    ^\n%Warning-MULTITOP: data/full_repos/permissive/143278/ivltests/module3.12A.v:28: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                              : ... Top module \'mod1\'\nmodule mod1 ;\n       ^~~~\n                                                                              : ... Top module \'mod2\'\nmodule mod2 ();\n       ^~~~\n                                                                              : ... Top module \'mod3\'\nmodule mod3 (a,b);\n       ^~~~\n                                                                              : ... Top module \'main\'\nmodule main ();\n       ^~~~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ();

wire [31:0] out1,out2;
reg  [31:0] val1,val2;
reg error;

mod4 inst1 (val1,out1);
mod4 inst2 (.ident1(val2),.out1(out2));

initial
 begin
    error = 0;
    val1 = 32'h11223344;
    #1 if(out1 != 32'h11223344)
      begin
        $display("FAILED - module 3.12A - Ordered module port list failed");
        error = 1;
      end
    val2 = 32'h44332211;
    #1 if(out2 != 32'h44332211)
      begin
        $display("FAILED -module 3.12A -named module port list (.x(a)) failed");
        error = 1;
      end
    if(error == 0)
      $display("PASSED");
 end


endmodule
module main ();


wire [31:0] out1,out2;
reg  [31:0] val1,val2;
reg error;

mod4 inst1 (val1,out1);
mod4 inst2 (.ident1(val2),.out1(out2));

initial
 begin
    error = 0;
    val1 = 32'h11223344;
    #1 if(out1 != 32'h11223344)
      begin
        $display("FAILED - module 3.12A - Ordered module port list failed");
        error = 1;
      end
    val2 = 32'h44332211;
    #1 if(out2 != 32'h44332211)
      begin
        $display("FAILED -module 3.12A -named module port list (.x(a)) failed");
        error = 1;
      end
    if(error == 0)
      $display("PASSED");
 end


endmodule