data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v
None: at end of input
1: b'%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:5: Cannot find include file: HD63701_defs.i\n`include "HD63701_defs.i" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174323821/hdl/cpu/63701,data/full_repos/permissive/174323821/HD63701_defs.i\n             data/full_repos/permissive/174323821/hdl/cpu/63701,data/full_repos/permissive/174323821/HD63701_defs.i.v\n             data/full_repos/permissive/174323821/hdl/cpu/63701,data/full_repos/permissive/174323821/HD63701_defs.i.sv\n             HD63701_defs.i\n             HD63701_defs.i.v\n             HD63701_defs.i.sv\n             obj_dir/HD63701_defs.i\n             obj_dir/HD63701_defs.i.v\n             obj_dir/HD63701_defs.i.sv\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:40: Define or directive not defined: \'`mcCCB\'\nwire          mcnw = (mcop==`mcCCB)|(mcop==`mcSCB)|(mcop==`mcAPC)|\n                            ^~~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:40: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire          mcnw = (mcop==`mcCCB)|(mcop==`mcSCB)|(mcop==`mcAPC)|\n                                  ^\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:40: Define or directive not defined: \'`mcSCB\'\nwire          mcnw = (mcop==`mcCCB)|(mcop==`mcSCB)|(mcop==`mcAPC)|\n                                           ^~~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:40: Define or directive not defined: \'`mcAPC\'\nwire          mcnw = (mcop==`mcCCB)|(mcop==`mcSCB)|(mcop==`mcAPC)|\n                                                          ^~~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:41: Define or directive not defined: \'`mcLDV\'\n                        (mcop==`mcLDV)|(mcop==`mcINT);\n                               ^~~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:41: Define or directive not defined: \'`mcINT\'\n                        (mcop==`mcLDV)|(mcop==`mcINT);\n                                              ^~~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:58: Define or directive not defined: \'`mcCCB\'\nwire IsCCR   = (mcop==`mcCCB)|(mcop==`mcSCB);\n                      ^~~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:58: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire IsCCR   = (mcop==`mcCCB)|(mcop==`mcSCB);\n                            ^\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:58: Define or directive not defined: \'`mcSCB\'\nwire IsCCR   = (mcop==`mcCCB)|(mcop==`mcSCB);\n                                     ^~~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:66: Define or directive not defined: \'`mcrC\'\n    .f0((mcr0 == `mcrC)|IsCCR),.d0({10\'b00000000_11,rC}),\n                 ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:66: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    .f0((mcr0 == `mcrC)|IsCCR),.d0({10\'b00000000_11,rC}),\n                      ^\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:67: Define or directive not defined: \'`mcrA\'\n                                                                            : ... Suggested alternative: \'`rA\'\n    .f1(mcr0 == `mcrA), .d1({8\'h0,rD[15:8]}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:68: Define or directive not defined: \'`mcrB\'\n                                                                            : ... Suggested alternative: \'`rB\'\n    .f2(mcr0 == `mcrB), .d2({8\'h0,rD[7:0]}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:69: Define or directive not defined: \'`mcrD\'\n    .f3(mcr0 == `mcrD), .d3(rD),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:70: Define or directive not defined: \'`mcrX\'\n    .f4(mcr0 == `mcrX), .d4(rX),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:71: Define or directive not defined: \'`mcrS\'\n    .f5(mcr0 == `mcrS), .d5(rS),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:72: Define or directive not defined: \'`mcrP\'\n    .f6(mcr0 == `mcrP), .d6(rP),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:73: Define or directive not defined: \'`mcrU\'\n                                                                            : ... Suggested alternative: \'`rU\'\n    .f7(mcr0 == `mcrU), .d7({8\'h0,rT[15:8]}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:74: Define or directive not defined: \'`mcrV\'\n                                                                            : ... Suggested alternative: \'`rV\'\n    .f8(mcr0 == `mcrV), .d8({8\'h0,rT[7:0]}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:75: Define or directive not defined: \'`mcrN\'\n    .f9(mcr0 == `mcrN), .d9({DI,8\'h0}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:76: Define or directive not defined: \'`mcrM\'\n    .fA(mcr0 == `mcrM), .dA({8\'h0,DI}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:77: Define or directive not defined: \'`mcrT\'\n    .fB(mcr0 == `mcrT), .dB(rT),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:78: Define or directive not defined: \'`mcrE\'\n    .fC(mcr0 == `mcrE), .dC(rE)\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:83: Define or directive not defined: \'`mcrC\'\n    .f0((mcr1 == `mcrC)|IsCCR),.d0({10\'b00000000_11,rC}),\n                 ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:83: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    .f0((mcr1 == `mcrC)|IsCCR),.d0({10\'b00000000_11,rC}),\n                      ^\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:84: Define or directive not defined: \'`mcrA\'\n                                                                            : ... Suggested alternative: \'`rA\'\n    .f1(mcr1 == `mcrA), .d1({8\'h0,rD[15:8]}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:85: Define or directive not defined: \'`mcrB\'\n                                                                            : ... Suggested alternative: \'`rB\'\n    .f2(mcr1 == `mcrB), .d2({8\'h0,rD[7:0]}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:86: Define or directive not defined: \'`mcrD\'\n    .f3(mcr1 == `mcrD), .d3(rD),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:87: Define or directive not defined: \'`mcrX\'\n    .f4(mcr1 == `mcrX), .d4(rX),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:88: Define or directive not defined: \'`mcrS\'\n    .f5(mcr1 == `mcrS), .d5(rS),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:89: Define or directive not defined: \'`mcrP\'\n    .f6(mcr1 == `mcrP), .d6(rP),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:90: Define or directive not defined: \'`mcrU\'\n                                                                            : ... Suggested alternative: \'`rU\'\n    .f7(mcr1 == `mcrU), .d7({8\'h0,rT[15:8]}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:91: Define or directive not defined: \'`mcrV\'\n                                                                            : ... Suggested alternative: \'`rV\'\n    .f8(mcr1 == `mcrV), .d8({8\'h0,rT[7:0]}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:92: Define or directive not defined: \'`mcrN\'\n    .f9(mcr1 == `mcrN), .d9({DI,8\'h0}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:93: Define or directive not defined: \'`mcrM\'\n    .fA(mcr1 == `mcrM), .dA({8\'h0,DI}),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:94: Define or directive not defined: \'`mcrT\'\n    .fB(mcr1 == `mcrT), .dB(rT),\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:95: Define or directive not defined: \'`mcrE\'\n    .fC(mcr1 == `mcrE), .dC(rE)\n                ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:99: Define or directive not defined: \'`mcrn\'\n    .op(mcop),.cf(mccf),.bw((mcr2==`mcrn) ? mcr0[2] : mcr2[2]),\n                                   ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:99: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    .op(mcop),.cf(mccf),.bw((mcr2==`mcrn) ? mcr0[2] : mcr2[2]),\n                                        ^\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:108: Define or directive not defined: \'`amPC\'\n    .f0(mcam==`amPC), .d0(rP),\n              ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:108: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    .f0(mcam==`amPC), .d0(rP),\n                   ^\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:109: Define or directive not defined: \'`amP1\'\n    .f1(mcam==`amP1), .d1(rP+16\'h1),\n              ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:110: Define or directive not defined: \'`amSP\'\n    .f2(mcam==`amSP), .d2(rS),\n              ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:111: Define or directive not defined: \'`amS1\'\n    .f3(mcam==`amS1), .d3(rS+16\'h1),\n              ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:112: Define or directive not defined: \'`amX0\'\n    .f4(mcam==`amX0), .d4(rX),\n              ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:113: Define or directive not defined: \'`amXT\'\n    .f5(mcam==`amXT), .d5(rX+rT),\n              ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:114: Define or directive not defined: \'`amE0\'\n    .f6(mcam==`amE0), .d6(rE),\n              ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:115: Define or directive not defined: \'`amE1\'\n    .f7(mcam==`amE1), .d7(rE+16\'h1)\n              ^~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/63701/HD63701_EXEC.v:122: Define or directive not defined: \'`mcPSH\'\n          if (pmcop==`mcPSH) rS <= rSp-16\'h1;\n                     ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module HD63701_DSEL8 (
    output [15:0] o,

    input f0, input [15:0] d0,
    input f1, input [15:0] d1,
    input f2, input [15:0] d2,
    input f3, input [15:0] d3,
    input f4, input [15:0] d4,
    input f5, input [15:0] d5,
    input f6, input [15:0] d6,
    input f7, input [15:0] d7
);

assign o =
            f0 ? d0 :
            f1 ? d1 :
            f2 ? d2 :
            f3 ? d3 :
            f4 ? d4 :
            f5 ? d5 :
            f6 ? d6 :
            f7 ? d7 :
            16'h0 ;

endmodule
module HD63701_DSEL8 (
    output [15:0] o,

    input f0, input [15:0] d0,
    input f1, input [15:0] d1,
    input f2, input [15:0] d2,
    input f3, input [15:0] d3,
    input f4, input [15:0] d4,
    input f5, input [15:0] d5,
    input f6, input [15:0] d6,
    input f7, input [15:0] d7
);


assign o =
            f0 ? d0 :
            f1 ? d1 :
            f2 ? d2 :
            f3 ? d3 :
            f4 ? d4 :
            f5 ? d5 :
            f6 ? d6 :
            f7 ? d7 :
            16'h0 ;

endmodule