data/full_repos/permissive/212763527/school_project/8_mult_div/sources/divider.v
1: b'%Warning-WIDTH: data/full_repos/permissive/212763527/school_project/8_mult_div/sources/divider.v:42: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                                                                   : ... In instance divider\n                q <= {q[n-1:0], 1\'b1};\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212763527/school_project/8_mult_div/sources/divider.v:45: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                                                                   : ... In instance divider\n                q <= {q[n-1:0], 1\'b0};\n                  ^~\n%Error: Exiting due to 2 warning(s)\n'
module divider #(parameter n = 16)
                (input clk,
                 input e,
                 input read,
                 input [n-1:0] dataA,
                 input [n-1:0] dataB,
                 output reg [n-1:0] q,
                 output reg [n-1:0] r,
                 output reg done);






reg [n-1:0] a;

integer counter;
always @(posedge clk) begin
    if (read) begin

        a <= dataA;
        r <= {n{1'b0}};
        q <= {n{1'b0}};
        done <= 1'b0;
        counter <= 0;
    end else if (e) begin
        if (counter == n) begin

            done <= 1'b1;
            r <= r;
            q <= q;
        end else begin
            counter <= counter + 1;

            a <= {a[n-2:0], 1'b0};



            if ({r[n-2:0], a[n-1]} >= dataB) begin
                r <= {r[n-2:0], a[n-1]} - dataB;
                q <= {q[n-1:0], 1'b1};
            end else begin
                r <= {r[n-2:0], a[n-1]};
                q <= {q[n-1:0], 1'b0};
            end

        end
    end
end

endmodule
module divider #(parameter n = 16)
                (input clk,
                 input e,
                 input read,
                 input [n-1:0] dataA,
                 input [n-1:0] dataB,
                 output reg [n-1:0] q,
                 output reg [n-1:0] r,
                 output reg done);







reg [n-1:0] a;

integer counter;
always @(posedge clk) begin
    if (read) begin

        a <= dataA;
        r <= {n{1'b0}};
        q <= {n{1'b0}};
        done <= 1'b0;
        counter <= 0;
    end else if (e) begin
        if (counter == n) begin

            done <= 1'b1;
            r <= r;
            q <= q;
        end else begin
            counter <= counter + 1;

            a <= {a[n-2:0], 1'b0};



            if ({r[n-2:0], a[n-1]} >= dataB) begin
                r <= {r[n-2:0], a[n-1]} - dataB;
                q <= {q[n-1:0], 1'b1};
            end else begin
                r <= {r[n-2:0], a[n-1]};
                q <= {q[n-1:0], 1'b0};
            end

        end
    end
end

endmodule