data/full_repos/permissive/109846502/redtb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/redtb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10; rst = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/redtb.v:47: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/redtb.v:53: Unsupported: Ignoring delay on this delayed statement.\n forever #15 en = ~en;\n         ^\n%Error: data/full_repos/permissive/109846502/redtb.v:36: Cannot find file containing module: \'red\'\n red uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/red\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/red.v\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/red.sv\n             red\n             red.v\n             red.sv\n             obj_dir/red\n             obj_dir/red.v\n             obj_dir/red.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module redtb;


	reg clk;
	reg rst;
	reg en;


	wire out;


	red uut (
		.clk(clk), 
		.rst(rst), 
		.en(en), 
		.out(out)
	);

	initial begin
	clk = 1'b0;
	rst = 1'b1;
	#10; rst = 1'b0;
	forever #1 clk = ~clk;

	end
	
	initial begin
	en = 1'b0;
	forever #15 en = ~en;
	end
      
endmodule
module redtb;



	reg clk;
	reg rst;
	reg en;


	wire out;


	red uut (
		.clk(clk), 
		.rst(rst), 
		.en(en), 
		.out(out)
	);

	initial begin
	clk = 1'b0;
	rst = 1'b1;
	#10; rst = 1'b0;
	forever #1 clk = ~clk;

	end
	
	initial begin
	en = 1'b0;
	forever #15 en = ~en;
	end
      
endmodule