data/full_repos/permissive/136794488/source/pipeexe.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136794488/source/pipeexe.v:26: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'8\'h4\' generates 8 bits.\n                                                                        : ... In instance pipeexe\n assign  epc8 = epc4 + 8\'h4;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/136794488/source/pipeexe.v:34: Cannot find file containing module: \'mux2x32\'\n   mux2x32 mux_shift  (ea,sa,eshift,alu_ina);\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136794488/source,data/full_repos/permissive/136794488/mux2x32\n             data/full_repos/permissive/136794488/source,data/full_repos/permissive/136794488/mux2x32.v\n             data/full_repos/permissive/136794488/source,data/full_repos/permissive/136794488/mux2x32.sv\n             mux2x32\n             mux2x32.v\n             mux2x32.sv\n             obj_dir/mux2x32\n             obj_dir/mux2x32.v\n             obj_dir/mux2x32.sv\n%Error: data/full_repos/permissive/136794488/source/pipeexe.v:36: Cannot find file containing module: \'mux2x32\'\n   mux2x32 mux_aluimm (eb,eimm,ealuimm,alu_inb);\n   ^~~~~~~\n%Error: data/full_repos/permissive/136794488/source/pipeexe.v:38: Cannot find file containing module: \'alu\'\n   alu al_unit (alu_ina,alu_inb,ealuc,aluout,zero );\n   ^~~\n%Error: data/full_repos/permissive/136794488/source/pipeexe.v:40: Cannot find file containing module: \'mux2x32\'\n   mux2x32 mux_jal (aluout,epc8,ejal,ealu);\n   ^~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module pipeexe ( ewreg,em2reg,ewmem,ejal,ealuc,ealuimm,eshift,
						epc4,ea,eb,eimm,ern0,
                  ern,ealu);

	input          ewreg,em2reg,ewmem,ejal,ealuimm,eshift;
	input   [3:0]  ealuc;
	input  [31:0]  epc4,ea,eb,eimm;
	input   [4:0]  ern0;

	output  [4:0]  ern;
	output [31:0]  ealu;
	
	wire           ewreg,em2reg,ewmem,ejal,ealuimm,eshift;
	wire    [3:0]  ealuc;
	wire   [31:0]  epc4,ea,eb,eimm;
	wire    [4:0]  ern0;
	
	wire    [4:0]  ern;
	wire   [31:0]  ealu;

	wire   [31:0]  epc8,alu_ina,alu_inb,aluout;
	wire   [31:0]  sa;
	wire           zero;
	

	assign  epc8 = epc4 + 8'h4;
	
	assign  sa[31:0] = { 27'b0,eimm[10:6] };

	
   assign  ern[4:0] = ern0 | {5{ejal}};


   mux2x32 mux_shift  (ea,sa,eshift,alu_ina);

   mux2x32 mux_aluimm (eb,eimm,ealuimm,alu_inb);

   alu al_unit (alu_ina,alu_inb,ealuc,aluout,zero );

   mux2x32 mux_jal (aluout,epc8,ejal,ealu);
    
endmodule
module pipeexe ( ewreg,em2reg,ewmem,ejal,ealuc,ealuimm,eshift,
						epc4,ea,eb,eimm,ern0,
                  ern,ealu);


	input          ewreg,em2reg,ewmem,ejal,ealuimm,eshift;
	input   [3:0]  ealuc;
	input  [31:0]  epc4,ea,eb,eimm;
	input   [4:0]  ern0;

	output  [4:0]  ern;
	output [31:0]  ealu;
	
	wire           ewreg,em2reg,ewmem,ejal,ealuimm,eshift;
	wire    [3:0]  ealuc;
	wire   [31:0]  epc4,ea,eb,eimm;
	wire    [4:0]  ern0;
	
	wire    [4:0]  ern;
	wire   [31:0]  ealu;

	wire   [31:0]  epc8,alu_ina,alu_inb,aluout;
	wire   [31:0]  sa;
	wire           zero;
	

	assign  epc8 = epc4 + 8'h4;
	
	assign  sa[31:0] = { 27'b0,eimm[10:6] };

	
   assign  ern[4:0] = ern0 | {5{ejal}};


   mux2x32 mux_shift  (ea,sa,eshift,alu_ina);

   mux2x32 mux_aluimm (eb,eimm,ealuimm,alu_inb);

   alu al_unit (alu_ina,alu_inb,ealuc,aluout,zero );

   mux2x32 mux_jal (aluout,epc8,ejal,ealu);
    
endmodule