data/full_repos/permissive/162672365/Adder.v
data/verilator_xmls/fbe7f381-9c5d-417b-8dbc-a02327e27a4f.xml
module fourBitFullAdder(sum, carry, in1, in2, cin);
	input [3:0] in1, in2;
	input cin;
	output [3:0] sum;
	output carry;
	wire c0, c1, c2;
	
	oneBitFullAdder obfa1(sum[0], c0, in1[0], in2[0], cin);
	oneBitFullAdder obfa2(sum[1], c1, in1[1], in2[1], c0);
	oneBitFullAdder obfa3(sum[2], c2, in1[2], in2[2], c1);
	oneBitFullAdder obfa4(sum[3], carry, in1[3], in2[3], c2);
	
endmodule
module fourBitFullAdder(sum, carry, in1, in2, cin);

	input [3:0] in1, in2;
	input cin;
	output [3:0] sum;
	output carry;
	wire c0, c1, c2;
	
	oneBitFullAdder obfa1(sum[0], c0, in1[0], in2[0], cin);
	oneBitFullAdder obfa2(sum[1], c1, in1[1], in2[1], c0);
	oneBitFullAdder obfa3(sum[2], c2, in1[2], in2[2], c1);
	oneBitFullAdder obfa4(sum[3], carry, in1[3], in2[3], c2);
	
endmodule