data/full_repos/permissive/113036182/OtherUnits.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/OtherUnits.v:5: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'tristate_buffer\'\nmodule tristate_buffer(input x, enable, output z);\n       ^~~~~~~~~~~~~~~\n                                                                      : ... Top module \'reg_32bit\'\nmodule reg_32bit (input[31:0] d, input en,wr,clk, output[31:0] q);\n       ^~~~~~~~~\n                                                                      : ... Top module \'decoder_32bit\'\nmodule decoder_32bit (input [4:0]x, output [31:0]y);\n       ^~~~~~~~~~~~~\n                                                                      : ... Top module \'mux_2x5\'\nmodule mux_2x5 (input [4:0]O1,O2, input select, output [4:0]out1);\n       ^~~~~~~\n                                                                      : ... Top module \'mux_4x5\'\n   module mux_4x5 (input [4:0]O1,O2,O3,O4, input [1:0]select, output [4:0]out3);\n          ^~~~~~~\n                                                                      : ... Top module \'mux_2x32\'\nmodule mux_2x32 (input [31:0]O1,O2, input select, output [31:0]out1);\n       ^~~~~~~~\n                                                                      : ... Top module \'mux_4x32\'\n  module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);\n         ^~~~~~~~\n                                                                      : ... Top module \'Latch_32bit\'\nmodule Latch_32bit (input [31:0]D,input clk,output [31:0]Q);\n       ^~~~~~~~~~~\n                                                                      : ... Top module \'SignExtend16\'\nmodule SignExtend16 (input [15:0]x, output [31:0]y);\n       ^~~~~~~~~~~~\n                                                                      : ... Top module \'Latch_5bit\'\nmodule Latch_5bit (input [4:0]D,input clk,output [4:0]Q);\n       ^~~~~~~~~~\n                                                                      : ... Top module \'Latch_2bit\'\nmodule Latch_2bit (input [1:0]D,input clk,output [1:0]Q);\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:114: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n        ... Looked in:\n             data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux\n             data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.v\n             data/full_repos/permissive/113036182,data/full_repos/permissive/113036182/mux.sv\n             mux\n             mux.v\n             mux.sv\n             obj_dir/mux\n             obj_dir/mux.v\n             obj_dir/mux.sv\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:78: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:60: Cannot find file containing module: \'mux\'\nmux q1 (O1[0],O2[0],select[0],out1[0]),\n^~~\n%Error: data/full_repos/permissive/113036182/OtherUnits.v:51: Cannot find file containing module: \'mux\'\nmux m1 (O1[0],O2[0],select,out1[0]),\n^~~\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'x\' generates 1 bits.\n                                                                   : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/113036182/OtherUnits.v:2: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                   : ... In instance tristate_buffer\nassign z = enable? x : \'bz;\n         ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);
  wire [31:0]out1,out2;
mux m1 (O1[0],O2[0],select[0],out1[0]),
    m2 (O1[1],O2[1],select[0],out1[1]),
    m3 (O1[2],O2[2],select[0],out1[2]),
    m4 (O1[3],O2[3],select[0],out1[3]),
    m5 (O1[4],O2[4],select[0],out1[4]),
    m6 (O1[5],O2[5],select[0],out1[5]),
    m7 (O1[6],O2[6],select[0],out1[6]),
    m8 (O1[7],O2[7],select[0],out1[7]),
    m9 (O1[8],O2[8],select[0],out1[8]),
    m10 (O1[9],O2[9],select[0],out1[9]),
    m11 (O1[10],O2[10],select[0],out1[10]),
    m12 (O1[11],O2[11],select[0],out1[11]),
    m13 (O1[12],O2[12],select[0],out1[12]),
    m14 (O1[13],O2[13],select[0],out1[13]),
    m15 (O1[14],O2[14],select[0],out1[14]),
    m16 (O1[15],O2[15],select[0],out1[15]),
    m17 (O1[16],O2[16],select[0],out1[16]),
    m18 (O1[17],O2[17],select[0],out1[17]),
    m19 (O1[18],O2[18],select[0],out1[18]),
    m20 (O1[19],O2[19],select[0],out1[19]),
    m21 (O1[20],O2[20],select[0],out1[20]),
    m22 (O1[21],O2[21],select[0],out1[21]),
    m23 (O1[22],O2[22],select[0],out1[22]),
    m24 (O1[23],O2[23],select[0],out1[23]),
    m25 (O1[24],O2[24],select[0],out1[24]),
    m26 (O1[25],O2[25],select[0],out1[25]),
    m27 (O1[26],O2[26],select[0],out1[26]),
    m28 (O1[27],O2[27],select[0],out1[27]),
    m29 (O1[28],O2[28],select[0],out1[28]),
    m30 (O1[29],O2[29],select[0],out1[29]),
    m31 (O1[30],O2[30],select[0],out1[30]),
    m32 (O1[31],O2[31],select[0],out1[31]),
    n1 (O3[0],O4[0],select[0],out2[0]),
    n2 (O3[1],O4[1],select[0],out2[1]),
    n3 (O3[2],O4[2],select[0],out2[2]),
    n4 (O3[3],O4[3],select[0],out2[3]),
    n5 (O3[4],O4[4],select[0],out2[4]),
    n6 (O3[5],O4[5],select[0],out2[5]),
    n7 (O3[6],O4[6],select[0],out2[6]),
    n8 (O3[7],O4[7],select[0],out2[7]),
    n9 (O3[8],O4[8],select[0],out2[8]),
    n10 (O3[9],O4[9],select[0],out2[9]),
    n11 (O3[10],O4[10],select[0],out2[10]),
    n12 (O3[11],O4[11],select[0],out2[11]),
    n13 (O3[12],O4[12],select[0],out2[12]),
    n14 (O3[13],O4[13],select[0],out2[13]),
    n15 (O3[14],O4[14],select[0],out2[14]),
    n16 (O3[15],O4[15],select[0],out2[15]),
    n17 (O3[16],O4[16],select[0],out2[16]),
    n18 (O3[17],O4[17],select[0],out2[17]),
    n19 (O3[18],O4[18],select[0],out2[18]),
    n20 (O3[19],O4[19],select[0],out2[19]),
    n21 (O3[20],O4[20],select[0],out2[20]),
    n22 (O3[21],O4[21],select[0],out2[21]),
    n23 (O3[22],O4[22],select[0],out2[22]),
    n24 (O3[23],O4[23],select[0],out2[23]),
    n25 (O3[24],O4[24],select[0],out2[24]),
    n26 (O3[25],O4[25],select[0],out2[25]),
    n27 (O3[26],O4[26],select[0],out2[26]),
    n28 (O3[27],O4[27],select[0],out2[27]),
    n29 (O3[28],O4[28],select[0],out2[28]),
    n30 (O3[29],O4[29],select[0],out2[29]),
    n31 (O3[30],O4[30],select[0],out2[30]),
    n32 (O3[31],O4[31],select[0],out2[31]),
    p1 (out1[0],out2[0],select[1],out3[0]),
    p2 (out1[1],out2[1],select[1],out3[1]),
    p3 (out1[2],out2[2],select[1],out3[2]),
    p4 (out1[3],out2[3],select[1],out3[3]),
    p5 (out1[4],out2[4],select[1],out3[4]),
    p6 (out1[5],out2[5],select[1],out3[5]),
    p7 (out1[6],out2[6],select[1],out3[6]),
    p8 (out1[7],out2[7],select[1],out3[7]),
    p9 (out1[8],out2[8],select[1],out3[8]),
    p10 (out1[9],out2[9],select[1],out3[9]),
    p11 (out1[10],out2[10],select[1],out3[10]),
    p12 (out1[11],out2[11],select[1],out3[11]),
    p13 (out1[12],out2[12],select[1],out3[12]),
    p14 (out1[13],out2[13],select[1],out3[13]),
    p15 (out1[14],out2[14],select[1],out3[14]),
    p16 (out1[15],out2[15],select[1],out3[15]),
    p17 (out1[16],out2[16],select[1],out3[16]),
    p18 (out1[17],out2[17],select[1],out3[17]),
    p19 (out1[18],out2[18],select[1],out3[18]),
    p20 (out1[19],out2[19],select[1],out3[19]),
    p21 (out1[20],out2[20],select[1],out3[20]),
    p22 (out1[21],out2[21],select[1],out3[21]),
    p23 (out1[22],out2[22],select[1],out3[22]),
    p24 (out1[23],out2[23],select[1],out3[23]),
    p25 (out1[24],out2[24],select[1],out3[24]),
    p26 (out1[25],out2[25],select[1],out3[25]),
    p27 (out1[26],out2[26],select[1],out3[26]),
    p28 (out1[27],out2[27],select[1],out3[27]),
    p29 (out1[28],out2[28],select[1],out3[28]),
    p30 (out1[29],out2[29],select[1],out3[29]),
    p31 (out1[30],out2[30],select[1],out3[30]),
    p32 (out1[31],out2[31],select[1],out3[31]);
  endmodule
module mux_4x32 (input [31:0]O1,O2,O3,O4, input [1:0]select, output [31:0]out3);

  wire [31:0]out1,out2;
mux m1 (O1[0],O2[0],select[0],out1[0]),
    m2 (O1[1],O2[1],select[0],out1[1]),
    m3 (O1[2],O2[2],select[0],out1[2]),
    m4 (O1[3],O2[3],select[0],out1[3]),
    m5 (O1[4],O2[4],select[0],out1[4]),
    m6 (O1[5],O2[5],select[0],out1[5]),
    m7 (O1[6],O2[6],select[0],out1[6]),
    m8 (O1[7],O2[7],select[0],out1[7]),
    m9 (O1[8],O2[8],select[0],out1[8]),
    m10 (O1[9],O2[9],select[0],out1[9]),
    m11 (O1[10],O2[10],select[0],out1[10]),
    m12 (O1[11],O2[11],select[0],out1[11]),
    m13 (O1[12],O2[12],select[0],out1[12]),
    m14 (O1[13],O2[13],select[0],out1[13]),
    m15 (O1[14],O2[14],select[0],out1[14]),
    m16 (O1[15],O2[15],select[0],out1[15]),
    m17 (O1[16],O2[16],select[0],out1[16]),
    m18 (O1[17],O2[17],select[0],out1[17]),
    m19 (O1[18],O2[18],select[0],out1[18]),
    m20 (O1[19],O2[19],select[0],out1[19]),
    m21 (O1[20],O2[20],select[0],out1[20]),
    m22 (O1[21],O2[21],select[0],out1[21]),
    m23 (O1[22],O2[22],select[0],out1[22]),
    m24 (O1[23],O2[23],select[0],out1[23]),
    m25 (O1[24],O2[24],select[0],out1[24]),
    m26 (O1[25],O2[25],select[0],out1[25]),
    m27 (O1[26],O2[26],select[0],out1[26]),
    m28 (O1[27],O2[27],select[0],out1[27]),
    m29 (O1[28],O2[28],select[0],out1[28]),
    m30 (O1[29],O2[29],select[0],out1[29]),
    m31 (O1[30],O2[30],select[0],out1[30]),
    m32 (O1[31],O2[31],select[0],out1[31]),
    n1 (O3[0],O4[0],select[0],out2[0]),
    n2 (O3[1],O4[1],select[0],out2[1]),
    n3 (O3[2],O4[2],select[0],out2[2]),
    n4 (O3[3],O4[3],select[0],out2[3]),
    n5 (O3[4],O4[4],select[0],out2[4]),
    n6 (O3[5],O4[5],select[0],out2[5]),
    n7 (O3[6],O4[6],select[0],out2[6]),
    n8 (O3[7],O4[7],select[0],out2[7]),
    n9 (O3[8],O4[8],select[0],out2[8]),
    n10 (O3[9],O4[9],select[0],out2[9]),
    n11 (O3[10],O4[10],select[0],out2[10]),
    n12 (O3[11],O4[11],select[0],out2[11]),
    n13 (O3[12],O4[12],select[0],out2[12]),
    n14 (O3[13],O4[13],select[0],out2[13]),
    n15 (O3[14],O4[14],select[0],out2[14]),
    n16 (O3[15],O4[15],select[0],out2[15]),
    n17 (O3[16],O4[16],select[0],out2[16]),
    n18 (O3[17],O4[17],select[0],out2[17]),
    n19 (O3[18],O4[18],select[0],out2[18]),
    n20 (O3[19],O4[19],select[0],out2[19]),
    n21 (O3[20],O4[20],select[0],out2[20]),
    n22 (O3[21],O4[21],select[0],out2[21]),
    n23 (O3[22],O4[22],select[0],out2[22]),
    n24 (O3[23],O4[23],select[0],out2[23]),
    n25 (O3[24],O4[24],select[0],out2[24]),
    n26 (O3[25],O4[25],select[0],out2[25]),
    n27 (O3[26],O4[26],select[0],out2[26]),
    n28 (O3[27],O4[27],select[0],out2[27]),
    n29 (O3[28],O4[28],select[0],out2[28]),
    n30 (O3[29],O4[29],select[0],out2[29]),
    n31 (O3[30],O4[30],select[0],out2[30]),
    n32 (O3[31],O4[31],select[0],out2[31]),
    p1 (out1[0],out2[0],select[1],out3[0]),
    p2 (out1[1],out2[1],select[1],out3[1]),
    p3 (out1[2],out2[2],select[1],out3[2]),
    p4 (out1[3],out2[3],select[1],out3[3]),
    p5 (out1[4],out2[4],select[1],out3[4]),
    p6 (out1[5],out2[5],select[1],out3[5]),
    p7 (out1[6],out2[6],select[1],out3[6]),
    p8 (out1[7],out2[7],select[1],out3[7]),
    p9 (out1[8],out2[8],select[1],out3[8]),
    p10 (out1[9],out2[9],select[1],out3[9]),
    p11 (out1[10],out2[10],select[1],out3[10]),
    p12 (out1[11],out2[11],select[1],out3[11]),
    p13 (out1[12],out2[12],select[1],out3[12]),
    p14 (out1[13],out2[13],select[1],out3[13]),
    p15 (out1[14],out2[14],select[1],out3[14]),
    p16 (out1[15],out2[15],select[1],out3[15]),
    p17 (out1[16],out2[16],select[1],out3[16]),
    p18 (out1[17],out2[17],select[1],out3[17]),
    p19 (out1[18],out2[18],select[1],out3[18]),
    p20 (out1[19],out2[19],select[1],out3[19]),
    p21 (out1[20],out2[20],select[1],out3[20]),
    p22 (out1[21],out2[21],select[1],out3[21]),
    p23 (out1[22],out2[22],select[1],out3[22]),
    p24 (out1[23],out2[23],select[1],out3[23]),
    p25 (out1[24],out2[24],select[1],out3[24]),
    p26 (out1[25],out2[25],select[1],out3[25]),
    p27 (out1[26],out2[26],select[1],out3[26]),
    p28 (out1[27],out2[27],select[1],out3[27]),
    p29 (out1[28],out2[28],select[1],out3[28]),
    p30 (out1[29],out2[29],select[1],out3[29]),
    p31 (out1[30],out2[30],select[1],out3[30]),
    p32 (out1[31],out2[31],select[1],out3[31]);
  endmodule