data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src/ALU.v
None: at end of input
1: b'%Error: data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src/ALU.v:12: Cannot find include file: Parameters.v\n`include "Parameters.v"    \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v.v\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v.sv\n             Parameters.v\n             Parameters.v.v\n             Parameters.v.sv\n             obj_dir/Parameters.v\n             obj_dir/Parameters.v.v\n             obj_dir/Parameters.v.sv\n%Error: Exiting due to 1 error(s)\n'
module ALU(
    input wire [31:0] Operand1,
    input wire [31:0] Operand2,
    input wire [3:0] AluContrl,
    output reg [31:0] AluOut
    );
endmodule
module ALU(
    input wire [31:0] Operand1,
    input wire [31:0] Operand2,
    input wire [3:0] AluContrl,
    output reg [31:0] AluOut
    );

endmodule