data/full_repos/permissive/143278/ivltests/br971.v
 line:11: before: "assign"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br971.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #0 $display("%d", data);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

reg  [1:0] addr;
reg  [3:0] memory[3:0];
reg  [3:0] data;

initial begin
  assign data = memory[addr];
  addr = 1;
  memory[addr] = 2;
  #0 $display("%d", data);
  if (data === 2)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module test();


reg  [1:0] addr;
reg  [3:0] memory[3:0];
reg  [3:0] data;

initial begin
  assign data = memory[addr];
  addr = 1;
  memory[addr] = 2;
  #0 $display("%d", data);
  if (data === 2)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule