data/full_repos/permissive/102515926/Modules/SUB.v
data/verilator_xmls/5889adc2-dc47-46d8-a87a-1132e3e5638c.xml
module SUB(a, b, diff);

    parameter DATAWIDTH = 64;

    input [DATAWIDTH - 1:0] a, b;
    output reg [DATAWIDTH - 1:0] diff;
    
    always @(*) begin
    
        diff <= a - b;
    
    end
    
endmodule
module SUB(a, b, diff);


    parameter DATAWIDTH = 64;

    input [DATAWIDTH - 1:0] a, b;
    output reg [DATAWIDTH - 1:0] diff;
    
    always @(*) begin
    
        diff <= a - b;
    
    end
    
endmodule