data/full_repos/permissive/189013641/src/codec_t.v
'utf-8' codec can't decode byte 0xa3 in position 1081: invalid start byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/189013641/src/codec_t.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #dely;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/codec_t.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #dely;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/codec_t.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #(dely/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/codec_t.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #(dely/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/codec_t.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #dely;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/codec_t.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #7000000 $fclose(write_out_file);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/codec_t.v:101: Unsupported: Ignoring delay on this delayed statement.\nalways #(dely/2) clk=~clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/codec_t.v:102: Unsupported: Ignoring delay on this delayed statement.\nalways #(dely/2) clk_temp=~clk_temp;\n       ^\n%Error: data/full_repos/permissive/189013641/src/codec_t.v:41: Cannot find file containing module: \'codec\'\n codec uut (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/189013641/src,data/full_repos/permissive/189013641/codec\n             data/full_repos/permissive/189013641/src,data/full_repos/permissive/189013641/codec.v\n             data/full_repos/permissive/189013641/src,data/full_repos/permissive/189013641/codec.sv\n             codec\n             codec.v\n             codec.sv\n             obj_dir/codec\n             obj_dir/codec.v\n             obj_dir/codec.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module codec_t_v;


	reg clk;
	reg clk_temp;
	reg reset;
	reg en;
	reg [7:0] data_in;


	wire [31:0] codes;
	wire en_out;
	wire [31:0] cod_32;
	wire [5:0] len_32;


	codec uut (
		.clk(clk), 
		.reset(reset), 
		.en(en), 
		.data_in(data_in), 
		.codes(codes), 
		.en_out(en_out), 
		.cod_32(cod_32), 
		.len_32(len_32)
	);

  

 integer write_out_file;
 integer record_out_file;




        reg[7:0] mem[0:262143];
        
   parameter dely=25;
	initial $readmemh("test33.hex",mem);  
	initial write_out_file=$fopen("write_out_file.txt","w");
	initial record_out_file=$fopen("record_out_file.txt","w");
	 
  always@(posedge clk)
  if(en_out&en) begin
   $fwrite(write_out_file,"%h",codes);
	$fwrite(record_out_file,"%h:time %d, ",codes,$time);
	end
  
	
	initial begin

		clk = 0;
	   
		reset = 0;
		data_in = 0;
		en = 0;


	
		  
		#dely;
		#dely;
		#(dely/2);
		clk_temp=1;
		#(dely/2);
		#dely;
		 reset = 1;
		 
		 
		#7000000 $fclose(write_out_file);
		         $fclose(record_out_file);

		
	end
        

always #(dely/2) clk=~clk;
always #(dely/2) clk_temp=~clk_temp;

integer	i;
always@(negedge clk_temp or negedge reset)
begin  
	if (!reset)
		i <= 0;
	else if(i == 262152)
		i <= i;
	else
		i <= i + 1;
end
		


always@(negedge clk_temp or negedge reset)
begin  
	if (!reset)
		en<= 0;
	else
		if((i > 2) && (i<262146))
			en <= 1;
		else
			en <= 0;
end      

always@(negedge clk_temp or negedge reset)
begin  
	if (!reset)
		data_in <= 0;
	else
		if((i > 2) && (i<262146))
			data_in <= mem[i - 3];
		else
			data_in <= 0;
		
end
		 
endmodule
module codec_t_v;



	reg clk;
	reg clk_temp;
	reg reset;
	reg en;
	reg [7:0] data_in;


	wire [31:0] codes;
	wire en_out;
	wire [31:0] cod_32;
	wire [5:0] len_32;


	codec uut (
		.clk(clk), 
		.reset(reset), 
		.en(en), 
		.data_in(data_in), 
		.codes(codes), 
		.en_out(en_out), 
		.cod_32(cod_32), 
		.len_32(len_32)
	);

  

 integer write_out_file;
 integer record_out_file;




        reg[7:0] mem[0:262143];
        
   parameter dely=25;
	initial $readmemh("test33.hex",mem);  
	initial write_out_file=$fopen("write_out_file.txt","w");
	initial record_out_file=$fopen("record_out_file.txt","w");
	 
  always@(posedge clk)
  if(en_out&en) begin
   $fwrite(write_out_file,"%h",codes);
	$fwrite(record_out_file,"%h:time %d, ",codes,$time);
	end
  
	
	initial begin

		clk = 0;
	   
		reset = 0;
		data_in = 0;
		en = 0;


	
		  
		#dely;
		#dely;
		#(dely/2);
		clk_temp=1;
		#(dely/2);
		#dely;
		 reset = 1;
		 
		 
		#7000000 $fclose(write_out_file);
		         $fclose(record_out_file);

		
	end
        

always #(dely/2) clk=~clk;
always #(dely/2) clk_temp=~clk_temp;

integer	i;
always@(negedge clk_temp or negedge reset)
begin  
	if (!reset)
		i <= 0;
	else if(i == 262152)
		i <= i;
	else
		i <= i + 1;
end
		


always@(negedge clk_temp or negedge reset)
begin  
	if (!reset)
		en<= 0;
	else
		if((i > 2) && (i<262146))
			en <= 1;
		else
			en <= 0;
end      

always@(negedge clk_temp or negedge reset)
begin  
	if (!reset)
		data_in <= 0;
	else
		if((i > 2) && (i<262146))
			data_in <= mem[i - 3];
		else
			data_in <= 0;
		
end
		 
endmodule