data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v
 line:79: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:264: Unsupported: Ignoring delay on this delayed statement.\n   #((pmi_duty_cycle_reg / 100) * t_clkos)\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:87: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'pmi_freq_clki\' generates 40 bits.\n                                                                                                                                           : ... In instance pmi_pll_fp\npmi_freq_clki_reg1 = pmi_freq_clki;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:88: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'pmi_freq_clkfb\' generates 40 bits.\n                                                                                                                                           : ... In instance pmi_pll_fp\npmi_freq_clkfb_reg1 = pmi_freq_clkfb;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:89: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'pmi_freq_clkop\' generates 40 bits.\n                                                                                                                                           : ... In instance pmi_pll_fp\npmi_freq_clkop_reg1 = pmi_freq_clkop;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:90: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'pmi_freq_clkok\' generates 32 bits.\n                                                                                                                                           : ... In instance pmi_pll_fp\npmi_freq_clkok_reg1 = pmi_freq_clkok;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:91: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'pmi_phase_adj\' generates 24 bits.\n                                                                                                                                           : ... In instance pmi_pll_fp\npmi_phase_adj_reg1 = pmi_phase_adj;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:125: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'pmi_freq_clkos\' generates 40 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n      pmi_freq_clkos_reg1 = pmi_freq_clkos;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:131: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'pmi_freq_clkop\' generates 40 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n      pmi_freq_clkos_reg1 = pmi_freq_clkop;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:133: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'pmi_duty_cycle\' generates 32 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n      pmi_duty_cycle_reg1 = pmi_duty_cycle;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:122: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n   if (pmi_family == "SC" || pmi_family == "SCM" ||\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:123: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n       pmi_family == "XO2" || pmi_family == "ECP5U" || pmi_family == "ECP5UM")\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:123: Operator EQ expects 40 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n       pmi_family == "XO2" || pmi_family == "ECP5U" || pmi_family == "ECP5UM")\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:123: Operator EQ expects 48 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n       pmi_family == "XO2" || pmi_family == "ECP5U" || pmi_family == "ECP5UM")\n                                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:239: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n   if (pmi_family == "XP2" || pmi_family == "ECP3")\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:239: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n   if (pmi_family == "XP2" || pmi_family == "ECP3")\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:275: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:275: Operator EQ expects 40 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:288: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:288: Operator EQ expects 40 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:308: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n   else if (pmi_family == "SC" || pmi_family == "SCM" ||\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:309: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n            pmi_family == "XO2" || pmi_family == "ECP5U" || pmi_family == "ECP5UM")\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:309: Operator EQ expects 40 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n            pmi_family == "XO2" || pmi_family == "ECP5U" || pmi_family == "ECP5UM")\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:309: Operator EQ expects 48 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n            pmi_family == "XO2" || pmi_family == "ECP5U" || pmi_family == "ECP5UM")\n                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:301: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/138208056/VIP_DDR3_Demo/DDR3_project/ddr3_ip_inst/inst1/ddr_p_eval/models/ecp5um/pmi_pll_fp.v:301: Operator EQ expects 40 bits on the LHS, but LHS\'s VARREF \'pmi_family\' generates 16 bits.\n                                                                                                                                            : ... In instance pmi_pll_fp\n   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")\n                                           ^~\n%Error: Exiting due to 25 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pmi_pll_fp
 #(parameter pmi_freq_clki = "100.0",
   parameter pmi_freq_clkfb = "100.0",
   parameter pmi_freq_clkop = "100.0",
   parameter pmi_freq_clkos = "100.0",
   parameter pmi_freq_clkok = "50.0",
   parameter pmi_family = "EC",
   parameter pmi_phase_adj = "0.0",
   parameter pmi_duty_cycle = "50.0",
   parameter pmi_clkfb_source = "CLKOP",
   parameter pmi_fdel = "off",
   parameter pmi_fdel_val = 0,
   parameter module_type = "pmi_pll_fp")

  (input       CLKI,
   input       CLKFB,
   input       RESET,
   output      CLKOP,
   output      CLKOS,
   output      CLKOK,
   output      CLKOK2,
   output      LOCK);


real pmi_freq_clki_reg, pmi_freq_clkfb_reg;
reg [63:0] pmi_freq_clki_reg1, pmi_freq_clkfb_reg1;
real pmi_freq_clkop_reg, pmi_freq_clkos_reg;
reg [63:0] pmi_freq_clkop_reg1, pmi_freq_clkos_reg1;
real pmi_freq_clkok_reg, pmi_phase_adj_reg;
reg [63:0] pmi_freq_clkok_reg1, pmi_phase_adj_reg1;
real pmi_duty_cycle_reg, pmi_fdel_val_reg;
reg [63:0] pmi_duty_cycle_reg1;
realtime t_clki, t_clkop, t_clkos, t_clkok, t_clkok2;
reg int_clk, CLKOP_REG, CLKOS_REG, CLKOK_REG, CLKOK2_REG;
reg first_time1, first_time2, first_time3, first_time4, vir_sclk, final_sclk;
reg CLKOP_NEW, CLKOS_NEW, CLKOK_NEW;
integer retval;

initial 
begin
pmi_freq_clki_reg1 = pmi_freq_clki;
pmi_freq_clkfb_reg1 = pmi_freq_clkfb;
pmi_freq_clkop_reg1 = pmi_freq_clkop;
pmi_freq_clkok_reg1 = pmi_freq_clkok;
pmi_phase_adj_reg1 = pmi_phase_adj;
retval=$sscanf(pmi_freq_clki_reg1, "%f", pmi_freq_clki_reg);
retval=$sscanf(pmi_freq_clkfb_reg1, "%f", pmi_freq_clkfb_reg);
retval=$sscanf(pmi_freq_clkop_reg1, "%f", pmi_freq_clkop_reg);
retval=$sscanf(pmi_freq_clkok_reg1, "%f", pmi_freq_clkok_reg);
retval=$sscanf(pmi_phase_adj_reg1, "%f", pmi_phase_adj_reg);
pmi_fdel_val_reg = (0.13 * pmi_fdel_val);

int_clk = 1'b0;
CLKOP_REG = 1'b0;
CLKOS_REG = 1'b0;
CLKOK_REG = 1'b0;
CLKOK2_REG = 1'b0;
CLKOP_NEW = 1'b0;
CLKOS_NEW = 1'b0;
CLKOK_NEW = 1'b0;
first_time1 = 1'b1;
first_time2 = 1'b1;
first_time3 = 1'b1;
first_time4 = 1'b1;
vir_sclk = 1'b0;
final_sclk = 1'b0;

   t_clki = (1000 / pmi_freq_clki_reg);
   t_clkop = (1000 / pmi_freq_clkop_reg);
   t_clkok = (1000 / pmi_freq_clkok_reg);
   t_clkok2 = (t_clkop * 3);
end

initial
begin
   if (pmi_family == "SC" || pmi_family == "SCM" ||
       pmi_family == "XO2" || pmi_family == "ECP5U" || pmi_family == "ECP5UM")
   begin
      pmi_freq_clkos_reg1 = pmi_freq_clkos;
      retval=$sscanf(pmi_freq_clkos_reg1, "%f", pmi_freq_clkos_reg);
      pmi_duty_cycle_reg = 50.0;
   end
   else
   begin
      pmi_freq_clkos_reg1 = pmi_freq_clkop;
      retval=$sscanf(pmi_freq_clkos_reg1, "%f", pmi_freq_clkos_reg);
      pmi_duty_cycle_reg1 = pmi_duty_cycle;
      retval=$sscanf(pmi_duty_cycle_reg1, "%f", pmi_duty_cycle_reg);
   end

   t_clkos = (1000 / pmi_freq_clkos_reg);

end


























always @ (posedge RESET or posedge CLKI)
begin
   if (RESET == 1'b1)
      int_clk <= 1'b0;
   else if (int_clk == 1'b0)
      int_clk <= 1'b1;
end 

always @ (int_clk or CLKOP_REG)
begin
   if (int_clk == 1'b0)
   begin
      CLKOP_REG <= 1'b0;
      first_time1 <= 1'b1;
   end
   else 
   begin
      if (first_time1 == 1'b1)
      begin
         CLKOP_REG <= 1'b1;
         first_time1 <= 1'b0;
      end
      else
      begin
         CLKOP_REG <= #(t_clkop/2) ~CLKOP_REG;
      end
   end
end 
      
always @ (int_clk or CLKOS_REG)
begin
   if (int_clk == 1'b0)
   begin
      CLKOS_REG <= 1'b0;
      first_time2 <= 1'b1;
   end
   else
   begin
      if (first_time2 == 1'b1)
      begin
         CLKOS_REG <= 1'b1;
         first_time2 <= 1'b0;
      end
      else
      begin
         CLKOS_REG <= #(t_clkos/2) ~CLKOS_REG;
      end
   end
end

always @ (int_clk or CLKOK_REG)
begin
   if (int_clk == 1'b0)
   begin
      CLKOK_REG <= 1'b0;
      first_time3 <= 1'b1;
   end
   else
   begin
      if (first_time3 == 1'b1)
      begin
         CLKOK_REG <= 1'b1;
         first_time3 <= 1'b0;
      end
      else
      begin
         CLKOK_REG <= #(t_clkok/2) ~CLKOK_REG;
      end
   end
end

always @ (int_clk or CLKOK2_REG)
begin
   if (pmi_family == "XP2" || pmi_family == "ECP3")
   begin 
      if (int_clk == 1'b0)
      begin
         CLKOK2_REG <= 1'b0;
         first_time4 <= 1'b1;
      end
      else
      begin
         if (first_time4 == 1'b1)
         begin
            CLKOK2_REG <= 1'b1;
            first_time4 <= 1'b0;
         end
         else
         begin
            CLKOK2_REG <= #(t_clkok2/2) ~CLKOK2_REG;
         end
      end
   end
end

always @ (posedge CLKOS_REG)
begin
   vir_sclk <= 1'b1;
   #((pmi_duty_cycle_reg / 100) * t_clkos)
   vir_sclk <= 1'b0;
  end

  always @(vir_sclk)
  begin
     final_sclk <= #((pmi_phase_adj_reg / 360) * t_clkos) vir_sclk;
  end

always @ (CLKOP_REG)
begin
   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")
   begin
      if (pmi_fdel_val_reg >= 0)
         CLKOP_NEW <= #(pmi_fdel_val_reg) CLKOP_REG;
      else
         CLKOP_NEW <= #(t_clki + pmi_fdel_val_reg) CLKOP_REG;
   end
   else
      CLKOP_NEW <= CLKOP_REG; 
end

always @ (final_sclk)
begin
   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")
   begin
      if (pmi_fdel_val_reg >= 0)
         CLKOS_NEW <= #(pmi_fdel_val_reg) final_sclk;
      else
         CLKOS_NEW <= #(t_clki + pmi_fdel_val_reg) final_sclk;
   end
   else
      CLKOS_NEW <= final_sclk;
end

always @ (CLKOK_REG)
begin
   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")
   begin
      if (pmi_fdel_val_reg >= 0)
         CLKOK_NEW <= #(pmi_fdel_val_reg) CLKOK_REG;
      else
         CLKOK_NEW <= #(t_clki + pmi_fdel_val_reg) CLKOK_REG;
   end
   else if (pmi_family == "SC" || pmi_family == "SCM" ||
            pmi_family == "XO2" || pmi_family == "ECP5U" || pmi_family == "ECP5UM")
      CLKOK_NEW <= 1'b0;
   else
      CLKOK_NEW <= CLKOK_REG;
end

assign CLKOP = CLKOP_NEW;
assign CLKOS = CLKOS_NEW;
assign CLKOK = CLKOK_NEW;
assign CLKOK2 = CLKOK2_REG;
assign LOCK = int_clk;


endmodule
module pmi_pll_fp
 #(parameter pmi_freq_clki = "100.0",
   parameter pmi_freq_clkfb = "100.0",
   parameter pmi_freq_clkop = "100.0",
   parameter pmi_freq_clkos = "100.0",
   parameter pmi_freq_clkok = "50.0",
   parameter pmi_family = "EC",
   parameter pmi_phase_adj = "0.0",
   parameter pmi_duty_cycle = "50.0",
   parameter pmi_clkfb_source = "CLKOP",
   parameter pmi_fdel = "off",
   parameter pmi_fdel_val = 0,
   parameter module_type = "pmi_pll_fp")

  (input       CLKI,
   input       CLKFB,
   input       RESET,
   output      CLKOP,
   output      CLKOS,
   output      CLKOK,
   output      CLKOK2,
   output      LOCK);



real pmi_freq_clki_reg, pmi_freq_clkfb_reg;
reg [63:0] pmi_freq_clki_reg1, pmi_freq_clkfb_reg1;
real pmi_freq_clkop_reg, pmi_freq_clkos_reg;
reg [63:0] pmi_freq_clkop_reg1, pmi_freq_clkos_reg1;
real pmi_freq_clkok_reg, pmi_phase_adj_reg;
reg [63:0] pmi_freq_clkok_reg1, pmi_phase_adj_reg1;
real pmi_duty_cycle_reg, pmi_fdel_val_reg;
reg [63:0] pmi_duty_cycle_reg1;
realtime t_clki, t_clkop, t_clkos, t_clkok, t_clkok2;
reg int_clk, CLKOP_REG, CLKOS_REG, CLKOK_REG, CLKOK2_REG;
reg first_time1, first_time2, first_time3, first_time4, vir_sclk, final_sclk;
reg CLKOP_NEW, CLKOS_NEW, CLKOK_NEW;
integer retval;

initial 
begin
pmi_freq_clki_reg1 = pmi_freq_clki;
pmi_freq_clkfb_reg1 = pmi_freq_clkfb;
pmi_freq_clkop_reg1 = pmi_freq_clkop;
pmi_freq_clkok_reg1 = pmi_freq_clkok;
pmi_phase_adj_reg1 = pmi_phase_adj;
retval=$sscanf(pmi_freq_clki_reg1, "%f", pmi_freq_clki_reg);
retval=$sscanf(pmi_freq_clkfb_reg1, "%f", pmi_freq_clkfb_reg);
retval=$sscanf(pmi_freq_clkop_reg1, "%f", pmi_freq_clkop_reg);
retval=$sscanf(pmi_freq_clkok_reg1, "%f", pmi_freq_clkok_reg);
retval=$sscanf(pmi_phase_adj_reg1, "%f", pmi_phase_adj_reg);
pmi_fdel_val_reg = (0.13 * pmi_fdel_val);

int_clk = 1'b0;
CLKOP_REG = 1'b0;
CLKOS_REG = 1'b0;
CLKOK_REG = 1'b0;
CLKOK2_REG = 1'b0;
CLKOP_NEW = 1'b0;
CLKOS_NEW = 1'b0;
CLKOK_NEW = 1'b0;
first_time1 = 1'b1;
first_time2 = 1'b1;
first_time3 = 1'b1;
first_time4 = 1'b1;
vir_sclk = 1'b0;
final_sclk = 1'b0;

   t_clki = (1000 / pmi_freq_clki_reg);
   t_clkop = (1000 / pmi_freq_clkop_reg);
   t_clkok = (1000 / pmi_freq_clkok_reg);
   t_clkok2 = (t_clkop * 3);
end

initial
begin
   if (pmi_family == "SC" || pmi_family == "SCM" ||
       pmi_family == "XO2" || pmi_family == "ECP5U" || pmi_family == "ECP5UM")
   begin
      pmi_freq_clkos_reg1 = pmi_freq_clkos;
      retval=$sscanf(pmi_freq_clkos_reg1, "%f", pmi_freq_clkos_reg);
      pmi_duty_cycle_reg = 50.0;
   end
   else
   begin
      pmi_freq_clkos_reg1 = pmi_freq_clkop;
      retval=$sscanf(pmi_freq_clkos_reg1, "%f", pmi_freq_clkos_reg);
      pmi_duty_cycle_reg1 = pmi_duty_cycle;
      retval=$sscanf(pmi_duty_cycle_reg1, "%f", pmi_duty_cycle_reg);
   end

   t_clkos = (1000 / pmi_freq_clkos_reg);

end


























always @ (posedge RESET or posedge CLKI)
begin
   if (RESET == 1'b1)
      int_clk <= 1'b0;
   else if (int_clk == 1'b0)
      int_clk <= 1'b1;
end 

always @ (int_clk or CLKOP_REG)
begin
   if (int_clk == 1'b0)
   begin
      CLKOP_REG <= 1'b0;
      first_time1 <= 1'b1;
   end
   else 
   begin
      if (first_time1 == 1'b1)
      begin
         CLKOP_REG <= 1'b1;
         first_time1 <= 1'b0;
      end
      else
      begin
         CLKOP_REG <= #(t_clkop/2) ~CLKOP_REG;
      end
   end
end 
      
always @ (int_clk or CLKOS_REG)
begin
   if (int_clk == 1'b0)
   begin
      CLKOS_REG <= 1'b0;
      first_time2 <= 1'b1;
   end
   else
   begin
      if (first_time2 == 1'b1)
      begin
         CLKOS_REG <= 1'b1;
         first_time2 <= 1'b0;
      end
      else
      begin
         CLKOS_REG <= #(t_clkos/2) ~CLKOS_REG;
      end
   end
end

always @ (int_clk or CLKOK_REG)
begin
   if (int_clk == 1'b0)
   begin
      CLKOK_REG <= 1'b0;
      first_time3 <= 1'b1;
   end
   else
   begin
      if (first_time3 == 1'b1)
      begin
         CLKOK_REG <= 1'b1;
         first_time3 <= 1'b0;
      end
      else
      begin
         CLKOK_REG <= #(t_clkok/2) ~CLKOK_REG;
      end
   end
end

always @ (int_clk or CLKOK2_REG)
begin
   if (pmi_family == "XP2" || pmi_family == "ECP3")
   begin 
      if (int_clk == 1'b0)
      begin
         CLKOK2_REG <= 1'b0;
         first_time4 <= 1'b1;
      end
      else
      begin
         if (first_time4 == 1'b1)
         begin
            CLKOK2_REG <= 1'b1;
            first_time4 <= 1'b0;
         end
         else
         begin
            CLKOK2_REG <= #(t_clkok2/2) ~CLKOK2_REG;
         end
      end
   end
end

always @ (posedge CLKOS_REG)
begin
   vir_sclk <= 1'b1;
   #((pmi_duty_cycle_reg / 100) * t_clkos)
   vir_sclk <= 1'b0;
  end

  always @(vir_sclk)
  begin
     final_sclk <= #((pmi_phase_adj_reg / 360) * t_clkos) vir_sclk;
  end

always @ (CLKOP_REG)
begin
   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")
   begin
      if (pmi_fdel_val_reg >= 0)
         CLKOP_NEW <= #(pmi_fdel_val_reg) CLKOP_REG;
      else
         CLKOP_NEW <= #(t_clki + pmi_fdel_val_reg) CLKOP_REG;
   end
   else
      CLKOP_NEW <= CLKOP_REG; 
end

always @ (final_sclk)
begin
   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")
   begin
      if (pmi_fdel_val_reg >= 0)
         CLKOS_NEW <= #(pmi_fdel_val_reg) final_sclk;
      else
         CLKOS_NEW <= #(t_clki + pmi_fdel_val_reg) final_sclk;
   end
   else
      CLKOS_NEW <= final_sclk;
end

always @ (CLKOK_REG)
begin
   if ((pmi_family == "ECP2" || pmi_family == "ECP2M") && pmi_fdel == "on")
   begin
      if (pmi_fdel_val_reg >= 0)
         CLKOK_NEW <= #(pmi_fdel_val_reg) CLKOK_REG;
      else
         CLKOK_NEW <= #(t_clki + pmi_fdel_val_reg) CLKOK_REG;
   end
   else if (pmi_family == "SC" || pmi_family == "SCM" ||
            pmi_family == "XO2" || pmi_family == "ECP5U" || pmi_family == "ECP5UM")
      CLKOK_NEW <= 1'b0;
   else
      CLKOK_NEW <= CLKOK_REG;
end

assign CLKOP = CLKOP_NEW;
assign CLKOS = CLKOS_NEW;
assign CLKOK = CLKOK_NEW;
assign CLKOK2 = CLKOK2_REG;
assign LOCK = int_clk;


endmodule