data/full_repos/permissive/193790231/lab02/lab02part01.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00000000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00000001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00000010;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00000011;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00000100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00000101;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00000110;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00000111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00001000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00001001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00001010; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00010000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00100000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b00110000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b01000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b01010000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b01100000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b01110000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b10000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part01.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #100; sw = 8\'b10010000;\n  ^\n%Error: data/full_repos/permissive/193790231/lab02/lab02part01.v:8: Cannot find file containing module: \'B_7SegDec\'\n B_7SegDec num1(SW[7:4], HEX1[6:0]);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193790231/lab02,data/full_repos/permissive/193790231/B_7SegDec\n             data/full_repos/permissive/193790231/lab02,data/full_repos/permissive/193790231/B_7SegDec.v\n             data/full_repos/permissive/193790231/lab02,data/full_repos/permissive/193790231/B_7SegDec.sv\n             B_7SegDec\n             B_7SegDec.v\n             B_7SegDec.sv\n             obj_dir/B_7SegDec\n             obj_dir/B_7SegDec.v\n             obj_dir/B_7SegDec.sv\n%Error: data/full_repos/permissive/193790231/lab02/lab02part01.v:9: Cannot find file containing module: \'B_7SegDec\'\n B_7SegDec num2(SW[3:0], HEX0[6:0]);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testBenchL2P1;
	
	reg [7:0]sw;
	wire [6:0]h0, h1;
	lab02part01 siml1p1(sw, h1, h0);
	
	initial begin
		#100;	sw = 8'b00000000;
		#100;	sw = 8'b00000001;
		#100;	sw = 8'b00000010;
		#100;	sw = 8'b00000011;
		#100;	sw = 8'b00000100;
		#100;	sw = 8'b00000101;
		#100;	sw = 8'b00000110;
		#100;	sw = 8'b00000111;
		#100;	sw = 8'b00001000;
		#100;	sw = 8'b00001001;
		#100;	sw = 8'b00001010;	
		#100;	sw = 8'b00010000;
		#100;	sw = 8'b00100000;
		#100;	sw = 8'b00110000;
		#100;	sw = 8'b01000000;
		#100;	sw = 8'b01010000;
		#100;	sw = 8'b01100000;
		#100;	sw = 8'b01110000;
		#100;	sw = 8'b10000000;
		#100;	sw = 8'b10010000;
		
	end
	
endmodule
module testBenchL2P1;

	
	reg [7:0]sw;
	wire [6:0]h0, h1;
	lab02part01 siml1p1(sw, h1, h0);
	
	initial begin
		#100;	sw = 8'b00000000;
		#100;	sw = 8'b00000001;
		#100;	sw = 8'b00000010;
		#100;	sw = 8'b00000011;
		#100;	sw = 8'b00000100;
		#100;	sw = 8'b00000101;
		#100;	sw = 8'b00000110;
		#100;	sw = 8'b00000111;
		#100;	sw = 8'b00001000;
		#100;	sw = 8'b00001001;
		#100;	sw = 8'b00001010;	
		#100;	sw = 8'b00010000;
		#100;	sw = 8'b00100000;
		#100;	sw = 8'b00110000;
		#100;	sw = 8'b01000000;
		#100;	sw = 8'b01010000;
		#100;	sw = 8'b01100000;
		#100;	sw = 8'b01110000;
		#100;	sw = 8'b10000000;
		#100;	sw = 8'b10010000;
		
	end
	
endmodule