data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v
 line:434: before: ")"
1: b"%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:434: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:439: syntax error, unexpected input\ninput CLK, RST, EN, WE;\n^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:450: syntax error, unexpected assign\nassign DO = mem[addr_reg][dw-1:0];\n^~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:522: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:527: syntax error, unexpected input\ninput CLK, RST, EN, WE;\n^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:538: syntax error, unexpected assign\nassign DO = mem[addr_reg][dw-1:0];\n^~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:566: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:571: syntax error, unexpected input\ninput CLK, RST, EN, WE;\n^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:582: syntax error, unexpected assign\nassign DO = mem[addr_reg][dw-1:0];\n^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module RAMB4_S2 (
    CLK,
    RST,
    ADDR,
    DI,
    EN,
    WE,
    DO,
);

parameter dw = 2;
parameter aw = 11;

input CLK, RST, EN, WE;
input [dw-1:0] DI;
output [dw-1:0] DO;
input [aw-1:0] ADDR;

reg	[dw-1:0]	mem [(1<<aw)-1:0];
reg	[aw-1:0]	addr_reg;




assign DO = mem[addr_reg][dw-1:0];




always @(posedge CLK or posedge RST)
    if ( RST == 1'b1 )
        addr_reg <= #1 {aw{1'b0}};
    else if ( EN )
        addr_reg <= #1 ADDR;




always @(posedge CLK)
	if (EN && WE)
		mem[ADDR] <= #1 DI;

endmodule
module RAMB4_S2 (
    CLK,
    RST,
    ADDR,
    DI,
    EN,
    WE,
    DO,
);


parameter dw = 2;
parameter aw = 11;

input CLK, RST, EN, WE;
input [dw-1:0] DI;
output [dw-1:0] DO;
input [aw-1:0] ADDR;

reg	[dw-1:0]	mem [(1<<aw)-1:0];
reg	[aw-1:0]	addr_reg;




assign DO = mem[addr_reg][dw-1:0];




always @(posedge CLK or posedge RST)
    if ( RST == 1'b1 )
        addr_reg <= #1 {aw{1'b0}};
    else if ( EN )
        addr_reg <= #1 ADDR;




always @(posedge CLK)
	if (EN && WE)
		mem[ADDR] <= #1 DI;

endmodule