data/full_repos/permissive/193790231/lab04/lab04part03.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193790231/lab04/lab04part03.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/193790231/lab04/lab04part03.v:8: Cannot find file containing module: \'count1\'\n count1 lpmcount(KEY[1], SW[0], SW[1], LEDR[15:0]);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193790231/lab04,data/full_repos/permissive/193790231/count1\n             data/full_repos/permissive/193790231/lab04,data/full_repos/permissive/193790231/count1.v\n             data/full_repos/permissive/193790231/lab04,data/full_repos/permissive/193790231/count1.sv\n             count1\n             count1.v\n             count1.sv\n             obj_dir/count1\n             obj_dir/count1.v\n             obj_dir/count1.sv\n%Error: data/full_repos/permissive/193790231/lab04/lab04part03.v:9: Cannot find file containing module: \'hexDecoder7Seg\'\n hexDecoder7Seg h3(HEX3[6:0], LEDR[15:12]);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193790231/lab04/lab04part03.v:10: Cannot find file containing module: \'hexDecoder7Seg\'\n hexDecoder7Seg h2(HEX2[6:0], LEDR[11:8]);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193790231/lab04/lab04part03.v:11: Cannot find file containing module: \'hexDecoder7Seg\'\n hexDecoder7Seg h1(HEX1[6:0], LEDR[7:4]);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193790231/lab04/lab04part03.v:12: Cannot find file containing module: \'hexDecoder7Seg\'\n hexDecoder7Seg h0(HEX0[6:0], LEDR[3:0]);\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tbl4p3;
	reg  [2:0]sw;
	wire [15:0]lr;
	wire [6:0]h3, h2, h1, h0;
	integer i;
	lab04part03 testl4p3(lr, h3, h2, h1, h0, {sw[2], sw[0]}, sw[1]);
	initial begin
		sw[1]=1'b0;
		sw[0]=1'b1;
		for(i=0; i<100; i=i+1) begin
		#100;
			if(i==0)
				sw[2] = 1;
			if(i==2)
				sw[2] = 0;
			sw[1] = ~sw[1];
		end

	end
endmodule
module tbl4p3;

	reg  [2:0]sw;
	wire [15:0]lr;
	wire [6:0]h3, h2, h1, h0;
	integer i;
	lab04part03 testl4p3(lr, h3, h2, h1, h0, {sw[2], sw[0]}, sw[1]);
	initial begin
		sw[1]=1'b0;
		sw[0]=1'b1;
		for(i=0; i<100; i=i+1) begin
		#100;
			if(i==0)
				sw[2] = 1;
			if(i==2)
				sw[2] = 0;
			sw[1] = ~sw[1];
		end

	end
endmodule