data/full_repos/permissive/127511545/src/Decoder.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:56: Signal definition not found, creating implicitly: \'F1\'\n and #(50) a0(F1, A, B, C, D), a1(G, F1, E);\n              ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:67: Signal definition not found, creating implicitly: \'NotA\'\n not #(50) inv4(NotA, Address[4]);\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:68: Signal definition not found, creating implicitly: \'NotB\'\n                                                                        : ... Suggested alternative: \'NotA\'\n not #(50) inv3(NotB, Address[3]);\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:69: Signal definition not found, creating implicitly: \'NotC\'\n                                                                        : ... Suggested alternative: \'NotA\'\n not #(50) inv2(NotC, Address[2]);\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:70: Signal definition not found, creating implicitly: \'NotD\'\n                                                                        : ... Suggested alternative: \'NotA\'\n not #(50) inv1(NotD, Address[1]);\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:71: Signal definition not found, creating implicitly: \'NotE\'\n                                                                        : ... Suggested alternative: \'NotA\'\n not #(50) inv0(NotE, Address[0]);\n                ^~~~\n%Error: Exiting due to 6 warning(s)\n'
module Decoder(WriteEnable, RegisterWrite, WriteRegister);

	output[31:0] WriteEnable;
	input RegisterWrite;
	input[4:0] WriteRegister;
	wire[31:0] OutputEnable;

	Decoder5to32 d5t32(OutputEnable, WriteRegister);

	assign 
		WriteEnable[0] = 0;
		and  #(50) a0(WriteEnable[1], OutputEnable[1], RegisterWrite);
		and  #(50) a1(WriteEnable[2], OutputEnable[2], RegisterWrite);
		and  #(50) a2(WriteEnable[3], OutputEnable[3], RegisterWrite);
		and  #(50) a3(WriteEnable[4], OutputEnable[4], RegisterWrite);
		and  #(50) a4(WriteEnable[5], OutputEnable[5], RegisterWrite);
		and  #(50) a5(WriteEnable[6], OutputEnable[6], RegisterWrite);
		and  #(50) a6(WriteEnable[7], OutputEnable[7], RegisterWrite);
		and  #(50) a7(WriteEnable[8], OutputEnable[8], RegisterWrite);
		and  #(50) a8(WriteEnable[9], OutputEnable[9], RegisterWrite);
		and  #(50) a9(WriteEnable[10], OutputEnable[10], RegisterWrite);
		and  #(50) a10(WriteEnable[11], OutputEnable[11], RegisterWrite);
		and  #(50) a11(WriteEnable[12], OutputEnable[12], RegisterWrite);
		and  #(50) a12(WriteEnable[13], OutputEnable[13], RegisterWrite);
		and  #(50) a13(WriteEnable[14], OutputEnable[14], RegisterWrite);
		and  #(50) a14(WriteEnable[15], OutputEnable[15], RegisterWrite);
		and  #(50) a15(WriteEnable[16], OutputEnable[16], RegisterWrite);
		and  #(50) a16(WriteEnable[17], OutputEnable[17], RegisterWrite);
		and  #(50) a17(WriteEnable[18], OutputEnable[18], RegisterWrite);
		and  #(50) a18(WriteEnable[19], OutputEnable[19], RegisterWrite);
		and  #(50) a19(WriteEnable[20], OutputEnable[20], RegisterWrite);
		and  #(50) a20(WriteEnable[21], OutputEnable[21], RegisterWrite);
		and  #(50) a21(WriteEnable[22], OutputEnable[22], RegisterWrite);
		and  #(50) a22(WriteEnable[23], OutputEnable[23], RegisterWrite);
		and  #(50) a23(WriteEnable[24], OutputEnable[24], RegisterWrite);
		and  #(50) a24(WriteEnable[25], OutputEnable[25], RegisterWrite);
		and  #(50) a25(WriteEnable[26], OutputEnable[26], RegisterWrite);
		and  #(50) a26(WriteEnable[27], OutputEnable[27], RegisterWrite);
		and  #(50) a27(WriteEnable[28], OutputEnable[28], RegisterWrite);
		and  #(50) a28(WriteEnable[29], OutputEnable[29], RegisterWrite);
		and  #(50) a29(WriteEnable[30], OutputEnable[30], RegisterWrite);
		and  #(50) a30(WriteEnable[31], OutputEnable[31], RegisterWrite);

endmodule
module Decoder(WriteEnable, RegisterWrite, WriteRegister);


	output[31:0] WriteEnable;
	input RegisterWrite;
	input[4:0] WriteRegister;
	wire[31:0] OutputEnable;

	Decoder5to32 d5t32(OutputEnable, WriteRegister);

	assign 
		WriteEnable[0] = 0;
		and  #(50) a0(WriteEnable[1], OutputEnable[1], RegisterWrite);
		and  #(50) a1(WriteEnable[2], OutputEnable[2], RegisterWrite);
		and  #(50) a2(WriteEnable[3], OutputEnable[3], RegisterWrite);
		and  #(50) a3(WriteEnable[4], OutputEnable[4], RegisterWrite);
		and  #(50) a4(WriteEnable[5], OutputEnable[5], RegisterWrite);
		and  #(50) a5(WriteEnable[6], OutputEnable[6], RegisterWrite);
		and  #(50) a6(WriteEnable[7], OutputEnable[7], RegisterWrite);
		and  #(50) a7(WriteEnable[8], OutputEnable[8], RegisterWrite);
		and  #(50) a8(WriteEnable[9], OutputEnable[9], RegisterWrite);
		and  #(50) a9(WriteEnable[10], OutputEnable[10], RegisterWrite);
		and  #(50) a10(WriteEnable[11], OutputEnable[11], RegisterWrite);
		and  #(50) a11(WriteEnable[12], OutputEnable[12], RegisterWrite);
		and  #(50) a12(WriteEnable[13], OutputEnable[13], RegisterWrite);
		and  #(50) a13(WriteEnable[14], OutputEnable[14], RegisterWrite);
		and  #(50) a14(WriteEnable[15], OutputEnable[15], RegisterWrite);
		and  #(50) a15(WriteEnable[16], OutputEnable[16], RegisterWrite);
		and  #(50) a16(WriteEnable[17], OutputEnable[17], RegisterWrite);
		and  #(50) a17(WriteEnable[18], OutputEnable[18], RegisterWrite);
		and  #(50) a18(WriteEnable[19], OutputEnable[19], RegisterWrite);
		and  #(50) a19(WriteEnable[20], OutputEnable[20], RegisterWrite);
		and  #(50) a20(WriteEnable[21], OutputEnable[21], RegisterWrite);
		and  #(50) a21(WriteEnable[22], OutputEnable[22], RegisterWrite);
		and  #(50) a22(WriteEnable[23], OutputEnable[23], RegisterWrite);
		and  #(50) a23(WriteEnable[24], OutputEnable[24], RegisterWrite);
		and  #(50) a24(WriteEnable[25], OutputEnable[25], RegisterWrite);
		and  #(50) a25(WriteEnable[26], OutputEnable[26], RegisterWrite);
		and  #(50) a26(WriteEnable[27], OutputEnable[27], RegisterWrite);
		and  #(50) a27(WriteEnable[28], OutputEnable[28], RegisterWrite);
		and  #(50) a28(WriteEnable[29], OutputEnable[29], RegisterWrite);
		and  #(50) a29(WriteEnable[30], OutputEnable[30], RegisterWrite);
		and  #(50) a30(WriteEnable[31], OutputEnable[31], RegisterWrite);

endmodule