data/full_repos/permissive/181665138/verilog/capitolo_vi/Interfaccia_Parallela_di_Uscita.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/181665138/verilog/capitolo_vi/Interfaccia_Parallela_di_Uscita.v:29: Unsupported: Ignoring delay on this delayed statement.\n    always @(posedge e) #3 TBR<=d7_d0;\n                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Interfaccia_Parallela_di_Uscita(d7_d0, s_, iow_, byte_out);
    input           s_, iow_;
    input   [7:0]   d7_d0;
    output  [7:0]   byte_out;

    reg [7:0] TBR;
    assign byte_out = TBR;

    wire e;
    assign e = ({s_, iow_}=='B00)? 1 : 0;

    always @(posedge e) #3 TBR<=d7_d0;
endmodule
module Interfaccia_Parallela_di_Uscita(d7_d0, s_, iow_, byte_out);

    input           s_, iow_;
    input   [7:0]   d7_d0;
    output  [7:0]   byte_out;

    reg [7:0] TBR;
    assign byte_out = TBR;

    wire e;
    assign e = ({s_, iow_}=='B00)? 1 : 0;

    always @(posedge e) #3 TBR<=d7_d0;
endmodule