data/full_repos/permissive/134925232/src/dmx_tb.v
 line:18: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/134925232/src/dmx_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/134925232/src/dmx_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile(`VCD_OUTPUT".vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/134925232/src/dmx_tb.v:16: Define or directive not defined: \'`VCD_OUTPUT\'\n        $dumpfile(`VCD_OUTPUT".vcd");\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/134925232/src/dmx_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, dmx_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/134925232/src/dmx_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #(duration) $display("END of simulation");\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dmx_tb();
    parameter duration = 175000;
    reg clk = 0;
    always #1 clk = ~clk;
    wire dmx_signal;
    dmx d0(
        .dmxclk(clk),
        .signal(dmx_signal)
    );

    initial begin
        $dumpfile(`DUMPSTR(`VCD_OUTPUT));
        $dumpvars(0, dmx_tb);
        #(duration) $display("END of simulation");
        $finish;
    end
endmodule
module dmx_tb();

    parameter duration = 175000;
    reg clk = 0;
    always #1 clk = ~clk;
    wire dmx_signal;
    dmx d0(
        .dmxclk(clk),
        .signal(dmx_signal)
    );

    initial begin
        $dumpfile(`DUMPSTR(`VCD_OUTPUT));
        $dumpvars(0, dmx_tb);
        #(duration) $display("END of simulation");
        $finish;
    end
endmodule