data/full_repos/permissive/169574047/mux4_to_1/mux4_to_1.srcs/sim_1/new/testbench.v
'utf-8' codec can't decode byte 0xb1 in position 474: invalid start byte
1: b'%Error: data/full_repos/permissive/169574047/mux4_to_1/mux4_to_1.srcs/sim_1/new/testbench.v:43: Unsupported or unknown PLI call: $monitor\n    $monitor("s1 = %b, s0 = %b, out = %b.", s1, s0, out1);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169574047/mux4_to_1/mux4_to_1.srcs/sim_1/new/testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #0 s1=0; s0=0;       \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/mux4_to_1/mux4_to_1.srcs/sim_1/new/testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #1 s1=0; s0=1;       \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/mux4_to_1/mux4_to_1.srcs/sim_1/new/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #1 s1=1; s0=0;       \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/mux4_to_1/mux4_to_1.srcs/sim_1/new/testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #1 s1=1; s0=1;       \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/mux4_to_1/mux4_to_1.srcs/sim_1/new/testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #1 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;


reg in0,in1,in2,in3;
reg s1,s0;


wire out1,out2,out3;



mux4_to_1 mymux1(out1, in0,in1,in2,in3, s1,s0);
logic1_mux4_to_1 mymux2(out2, in0,in1,in2,in3, s1,s0);
logic1_mux4_to_1 mymux3(out3, in0,in1,in2,in3, s1,s0);




initial
begin
    $monitor("s1 = %b, s0 = %b, out = %b.", s1, s0, out1);
    
    in0=1; in1=0; in2=1; in3=0;
    #0 s1=0; s0=0;
    #1 s1=0; s0=1;
    #1 s1=1; s0=0;
    #1 s1=1; s0=1;
    #1 $finish;
    
end

endmodule
module testbench;



reg in0,in1,in2,in3;
reg s1,s0;


wire out1,out2,out3;



mux4_to_1 mymux1(out1, in0,in1,in2,in3, s1,s0);
logic1_mux4_to_1 mymux2(out2, in0,in1,in2,in3, s1,s0);
logic1_mux4_to_1 mymux3(out3, in0,in1,in2,in3, s1,s0);




initial
begin
    $monitor("s1 = %b, s0 = %b, out = %b.", s1, s0, out1);
    
    in0=1; in1=0; in2=1; in3=0;
    #0 s1=0; s0=0;
    #1 s1=0; s0=1;
    #1 s1=1; s0=0;
    #1 s1=1; s0=1;
    #1 $finish;
    
end

endmodule