data/full_repos/permissive/167274925/ALU32Bit_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167274925/ALU32Bit_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167274925/ALU32Bit_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/ALU32Bit_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/ALU32Bit_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/ALU32Bit_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/ALU32Bit_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: data/full_repos/permissive/167274925/ALU32Bit_tb.v:18: Cannot find file containing module: \'ALU32Bit\'\n    ALU32Bit u0(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/ALU32Bit\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/ALU32Bit.v\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/ALU32Bit.sv\n             ALU32Bit\n             ALU32Bit.v\n             ALU32Bit.sv\n             obj_dir/ALU32Bit\n             obj_dir/ALU32Bit.v\n             obj_dir/ALU32Bit.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU32Bit_tb(); 

	reg [3:0] ALUControl;
	reg [31:0] A, B;

	wire [31:0] ALUResult;
	wire Zero;

    ALU32Bit u0(
        .ALUControl(ALUControl), 
        .A(A), 
        .B(B), 
        .ALUResult(ALUResult), 
        .Zero(Zero)
    );

	initial begin
	ALUControl<=4'b0110;
    A<=32'd12;
    B<=32'd12;
	#10;
	ALUControl<=4'd7;
	A<=32'd11;
	B<=32'd56;
    #10;
    A<=32'd100;
    B<=32'd56;
    #10;
    ALUControl<=4'd12;
     A<=32'd100;
     B<=32'd56;
    #10;
    ALUControl<=4'd0;
    #10;
    ALUControl<=4'd1;
    #10;
    end 
endmodule
module ALU32Bit_tb();
 

	reg [3:0] ALUControl;
	reg [31:0] A, B;

	wire [31:0] ALUResult;
	wire Zero;

    ALU32Bit u0(
        .ALUControl(ALUControl), 
        .A(A), 
        .B(B), 
        .ALUResult(ALUResult), 
        .Zero(Zero)
    );

	initial begin
	ALUControl<=4'b0110;
    A<=32'd12;
    B<=32'd12;
	#10;
	ALUControl<=4'd7;
	A<=32'd11;
	B<=32'd56;
    #10;
    A<=32'd100;
    B<=32'd56;
    #10;
    ALUControl<=4'd12;
     A<=32'd100;
     B<=32'd56;
    #10;
    ALUControl<=4'd0;
    #10;
    ALUControl<=4'd1;
    #10;
    end 
endmodule