data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v
1: b'%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:1: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:7: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   rs1_1,  \n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:8: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   rs2_1,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:9: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   rs1_2,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:10: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   rs2_2,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:11: Define or directive not defined: \'`DATA_LEN\'\n   output wire [`DATA_LEN-1:0]   rs1_1data,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:12: Define or directive not defined: \'`DATA_LEN\'\n   output wire [`DATA_LEN-1:0]   rs2_1data,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:13: Define or directive not defined: \'`DATA_LEN\'\n   output wire [`DATA_LEN-1:0]   rs1_2data,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:14: Define or directive not defined: \'`DATA_LEN\'\n   output wire [`DATA_LEN-1:0]   rs2_2data,  \n                ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:15: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   wreg1,  \n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:16: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   wreg2,  \n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:17: Define or directive not defined: \'`DATA_LEN\'\n   input wire [`DATA_LEN-1:0]   wdata1,  \n               ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:18: Define or directive not defined: \'`DATA_LEN\'\n   input wire [`DATA_LEN-1:0]   wdata2,  \n               ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:21: Define or directive not defined: \'`RRF_SEL\'\n   input wire [`RRF_SEL-1:0]   wrrfent1,  \n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:22: Define or directive not defined: \'`RRF_SEL\'\n   input wire [`RRF_SEL-1:0]   wrrfent2,  \n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:23: Define or directive not defined: \'`RRF_SEL\'\n   output wire [`RRF_SEL-1:0]   rs1_1tag,  \n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:24: Define or directive not defined: \'`RRF_SEL\'\n   output wire [`RRF_SEL-1:0]   rs2_1tag,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:25: Define or directive not defined: \'`RRF_SEL\'\n   output wire [`RRF_SEL-1:0]   rs1_2tag,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:26: Define or directive not defined: \'`RRF_SEL\'\n   output wire [`RRF_SEL-1:0]   rs2_2tag,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:27: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   tagbusy1_addr,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:28: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   tagbusy2_addr,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:31: Define or directive not defined: \'`RRF_SEL\'\n   input wire [`RRF_SEL-1:0]   settag1,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:32: Define or directive not defined: \'`RRF_SEL\'\n   input wire [`RRF_SEL-1:0]   settag2,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:33: Define or directive not defined: \'`SPECTAG_LEN\'\n   input wire [`SPECTAG_LEN-1:0] tagbusy1_spectag,\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:34: Define or directive not defined: \'`SPECTAG_LEN\'\n   input wire [`SPECTAG_LEN-1:0] tagbusy2_spectag,\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:41: Define or directive not defined: \'`SPECTAG_LEN\'\n   input wire [`SPECTAG_LEN-1:0] prtag,\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:42: Define or directive not defined: \'`SPECTAG_LEN\'\n   input wire [`SPECTAG_LEN-1:0] mpft_valid1,\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:43: Define or directive not defined: \'`SPECTAG_LEN\'\n   input wire [`SPECTAG_LEN-1:0] mpft_valid2\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:48: Define or directive not defined: \'`RRF_SEL\'\n   wire [`RRF_SEL-1:0]    comreg1_tag;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:49: Define or directive not defined: \'`RRF_SEL\'\n   wire [`RRF_SEL-1:0]    comreg2_tag;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:54: Define or directive not defined: \'`REG_SEL\'\n     (wreg1 != `REG_SEL\'b0);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:57: Define or directive not defined: \'`REG_SEL\'\n     (wreg2 != `REG_SEL\'b0);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:66: Define or directive not defined: \'`REG_SEL\'\n     #(`REG_SEL, `DATA_LEN, `REG_NUM)\n       ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:66: Define or directive not defined: \'`DATA_LEN\'\n     #(`REG_SEL, `DATA_LEN, `REG_NUM)\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:66: Define or directive not defined: \'`REG_NUM\'\n     #(`REG_SEL, `DATA_LEN, `REG_NUM)\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:132: Define or directive not defined: \'`SPECTAG_LEN\'\n       input wire [`SPECTAG_LEN-1:0] spectag,\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:133: Define or directive not defined: \'`REG_NUM\'\n       input wire [`REG_NUM-1:0]     dat0,\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:134: Define or directive not defined: \'`REG_NUM\'\n       input wire [`REG_NUM-1:0]     dat1,\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:135: Define or directive not defined: \'`REG_NUM\'\n       input wire [`REG_NUM-1:0]     dat2,\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:136: Define or directive not defined: \'`REG_NUM\'\n       input wire [`REG_NUM-1:0]     dat3,\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:137: Define or directive not defined: \'`REG_NUM\'\n       input wire [`REG_NUM-1:0]     dat4,\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:138: Define or directive not defined: \'`REG_NUM\'\n       output reg [`REG_NUM-1:0]     out\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:158: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   rs1_1,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:159: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   rs2_1,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:160: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   rs1_2,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:161: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   rs2_2,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:162: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   comreg1,  \n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:163: Define or directive not defined: \'`REG_SEL\'\n   input wire [`REG_SEL-1:0]   comreg2,  \n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:166: Define or directive not defined: \'`RRF_SEL\'\n   input wire [`RRF_SEL-1:0]   wrrfent1,\n               ^~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/arf.v:167: Define or directive not defined: \'`RRF_SEL\'\n   input wire [`RRF_SEL-1:0]   wrrfent2, \n               ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module arf
  (
   input wire 			 clk,
   input wire 			 reset,
   input wire [`REG_SEL-1:0] 	 rs1_1,
   input wire [`REG_SEL-1:0] 	 rs2_1,
   input wire [`REG_SEL-1:0] 	 rs1_2,
   input wire [`REG_SEL-1:0] 	 rs2_2,
   output wire [`DATA_LEN-1:0] 	 rs1_1data,
   output wire [`DATA_LEN-1:0] 	 rs2_1data,
   output wire [`DATA_LEN-1:0] 	 rs1_2data,
   output wire [`DATA_LEN-1:0] 	 rs2_2data,
   input wire [`REG_SEL-1:0] 	 wreg1,
   input wire [`REG_SEL-1:0] 	 wreg2,
   input wire [`DATA_LEN-1:0] 	 wdata1,
   input wire [`DATA_LEN-1:0] 	 wdata2,
   input wire 			 we1,
   input wire 			 we2,
   input wire [`RRF_SEL-1:0] 	 wrrfent1,
   input wire [`RRF_SEL-1:0] 	 wrrfent2,
   output wire [`RRF_SEL-1:0] 	 rs1_1tag,
   output wire [`RRF_SEL-1:0] 	 rs2_1tag,
   output wire [`RRF_SEL-1:0] 	 rs1_2tag,
   output wire [`RRF_SEL-1:0] 	 rs2_2tag,
   input wire [`REG_SEL-1:0] 	 tagbusy1_addr,
   input wire [`REG_SEL-1:0] 	 tagbusy2_addr,
   input wire 			 tagbusy1_we,
   input wire 			 tagbusy2_we,
   input wire [`RRF_SEL-1:0] 	 settag1,
   input wire [`RRF_SEL-1:0] 	 settag2,
   input wire [`SPECTAG_LEN-1:0] tagbusy1_spectag,
   input wire [`SPECTAG_LEN-1:0] tagbusy2_spectag,
   output wire 			 rs1_1busy,
   output wire 			 rs2_1busy,
   output wire 			 rs1_2busy,
   output wire 			 rs2_2busy,
   input wire 			 prmiss,
   input wire 			 prsuccess,
   input wire [`SPECTAG_LEN-1:0] prtag,
   input wire [`SPECTAG_LEN-1:0] mpft_valid1,
   input wire [`SPECTAG_LEN-1:0] mpft_valid2
   );



   wire [`RRF_SEL-1:0] 		 comreg1_tag;
   wire [`RRF_SEL-1:0] 		 comreg2_tag;
   wire 			 clearbusy1 = we1;
   wire 			 clearbusy2 = we2;

   wire 			 we1_0reg = we1 && 
				 (wreg1 != `REG_SEL'b0);
   
   wire 			 we2_0reg = we2 && 
				 (wreg2 != `REG_SEL'b0);
   
   wire 			 we1_prior2 = ((wreg1 == wreg2) &&
					       we1_0reg && we2_0reg) ? 
				 1'b0 : we1_0reg;
   


   ram_sync_nolatch_4r2w
     #(`REG_SEL, `DATA_LEN, `REG_NUM)
   regfile(
	   .clk(clk),
	   .raddr1(rs1_1),
	   .raddr2(rs2_1),
	   .raddr3(rs1_2),
	   .raddr4(rs2_2),
	   .rdata1(rs1_1data),
	   .rdata2(rs2_1data),
	   .rdata3(rs1_2data),
	   .rdata4(rs2_2data),
	   .waddr1(wreg1),
	   .waddr2(wreg2),
	   .wdata1(wdata1),
	   .wdata2(wdata2),

	   .we1(we1_0reg),
	   .we2(we2_0reg)
	   );

   
   renaming_table rt(
		     .clk(clk),
		     .reset(reset),
		     .rs1_1(rs1_1),
		     .rs2_1(rs2_1),
		     .rs1_2(rs1_2),
		     .rs2_2(rs2_2),
		     .comreg1(wreg1),
		     .comreg2(wreg2),
		     .rs1_1tag(rs1_1tag),
		     .rs2_1tag(rs2_1tag),
		     .rs1_2tag(rs1_2tag),
		     .rs2_2tag(rs2_2tag),
		     .rs1_1busy(rs1_1busy),
		     .rs2_1busy(rs2_1busy),
		     .rs1_2busy(rs1_2busy),
		     .rs2_2busy(rs2_2busy),
		     .settagbusy1_addr(tagbusy1_addr),
		     .settagbusy2_addr(tagbusy2_addr),
		     .settagbusy1(tagbusy1_we),
		     .settagbusy2(tagbusy2_we),
		     .settag1(settag1),
		     .settag2(settag2),
		     .setbusy1_spectag(tagbusy1_spectag),
		     .setbusy2_spectag(tagbusy2_spectag),
		     .clearbusy1(clearbusy1),
		     .clearbusy2(clearbusy2),
		     .wrrfent1(wrrfent1),
		     .wrrfent2(wrrfent2),
		     .prmiss(prmiss),
		     .prsuccess(prsuccess),
		     .prtag(prtag),
		     .mpft_valid1(mpft_valid1),
		     .mpft_valid2(mpft_valid2)
		     );
   

endmodule
module arf
  (
   input wire 			 clk,
   input wire 			 reset,
   input wire [`REG_SEL-1:0] 	 rs1_1,
   input wire [`REG_SEL-1:0] 	 rs2_1,
   input wire [`REG_SEL-1:0] 	 rs1_2,
   input wire [`REG_SEL-1:0] 	 rs2_2,
   output wire [`DATA_LEN-1:0] 	 rs1_1data,
   output wire [`DATA_LEN-1:0] 	 rs2_1data,
   output wire [`DATA_LEN-1:0] 	 rs1_2data,
   output wire [`DATA_LEN-1:0] 	 rs2_2data,
   input wire [`REG_SEL-1:0] 	 wreg1,
   input wire [`REG_SEL-1:0] 	 wreg2,
   input wire [`DATA_LEN-1:0] 	 wdata1,
   input wire [`DATA_LEN-1:0] 	 wdata2,
   input wire 			 we1,
   input wire 			 we2,
   input wire [`RRF_SEL-1:0] 	 wrrfent1,
   input wire [`RRF_SEL-1:0] 	 wrrfent2,
   output wire [`RRF_SEL-1:0] 	 rs1_1tag,
   output wire [`RRF_SEL-1:0] 	 rs2_1tag,
   output wire [`RRF_SEL-1:0] 	 rs1_2tag,
   output wire [`RRF_SEL-1:0] 	 rs2_2tag,
   input wire [`REG_SEL-1:0] 	 tagbusy1_addr,
   input wire [`REG_SEL-1:0] 	 tagbusy2_addr,
   input wire 			 tagbusy1_we,
   input wire 			 tagbusy2_we,
   input wire [`RRF_SEL-1:0] 	 settag1,
   input wire [`RRF_SEL-1:0] 	 settag2,
   input wire [`SPECTAG_LEN-1:0] tagbusy1_spectag,
   input wire [`SPECTAG_LEN-1:0] tagbusy2_spectag,
   output wire 			 rs1_1busy,
   output wire 			 rs2_1busy,
   output wire 			 rs1_2busy,
   output wire 			 rs2_2busy,
   input wire 			 prmiss,
   input wire 			 prsuccess,
   input wire [`SPECTAG_LEN-1:0] prtag,
   input wire [`SPECTAG_LEN-1:0] mpft_valid1,
   input wire [`SPECTAG_LEN-1:0] mpft_valid2
   );




   wire [`RRF_SEL-1:0] 		 comreg1_tag;
   wire [`RRF_SEL-1:0] 		 comreg2_tag;
   wire 			 clearbusy1 = we1;
   wire 			 clearbusy2 = we2;

   wire 			 we1_0reg = we1 && 
				 (wreg1 != `REG_SEL'b0);
   
   wire 			 we2_0reg = we2 && 
				 (wreg2 != `REG_SEL'b0);
   
   wire 			 we1_prior2 = ((wreg1 == wreg2) &&
					       we1_0reg && we2_0reg) ? 
				 1'b0 : we1_0reg;
   


   ram_sync_nolatch_4r2w
     #(`REG_SEL, `DATA_LEN, `REG_NUM)
   regfile(
	   .clk(clk),
	   .raddr1(rs1_1),
	   .raddr2(rs2_1),
	   .raddr3(rs1_2),
	   .raddr4(rs2_2),
	   .rdata1(rs1_1data),
	   .rdata2(rs2_1data),
	   .rdata3(rs1_2data),
	   .rdata4(rs2_2data),
	   .waddr1(wreg1),
	   .waddr2(wreg2),
	   .wdata1(wdata1),
	   .wdata2(wdata2),

	   .we1(we1_0reg),
	   .we2(we2_0reg)
	   );

   
   renaming_table rt(
		     .clk(clk),
		     .reset(reset),
		     .rs1_1(rs1_1),
		     .rs2_1(rs2_1),
		     .rs1_2(rs1_2),
		     .rs2_2(rs2_2),
		     .comreg1(wreg1),
		     .comreg2(wreg2),
		     .rs1_1tag(rs1_1tag),
		     .rs2_1tag(rs2_1tag),
		     .rs1_2tag(rs1_2tag),
		     .rs2_2tag(rs2_2tag),
		     .rs1_1busy(rs1_1busy),
		     .rs2_1busy(rs2_1busy),
		     .rs1_2busy(rs1_2busy),
		     .rs2_2busy(rs2_2busy),
		     .settagbusy1_addr(tagbusy1_addr),
		     .settagbusy2_addr(tagbusy2_addr),
		     .settagbusy1(tagbusy1_we),
		     .settagbusy2(tagbusy2_we),
		     .settag1(settag1),
		     .settag2(settag2),
		     .setbusy1_spectag(tagbusy1_spectag),
		     .setbusy2_spectag(tagbusy2_spectag),
		     .clearbusy1(clearbusy1),
		     .clearbusy2(clearbusy2),
		     .wrrfent1(wrrfent1),
		     .wrrfent2(wrrfent2),
		     .prmiss(prmiss),
		     .prsuccess(prsuccess),
		     .prtag(prtag),
		     .mpft_valid1(mpft_valid1),
		     .mpft_valid2(mpft_valid2)
		     );
   

endmodule