data/full_repos/permissive/132439949/sim_1/new/test_A_delay.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/132439949/sim_1/new/test_A_delay.v:32: Cannot find file containing module: 'A_delay'\n     A_delay dut(data_in, clk_write, pitch_shift);\n     ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132439949/sim_1/new,data/full_repos/permissive/132439949/A_delay\n             data/full_repos/permissive/132439949/sim_1/new,data/full_repos/permissive/132439949/A_delay.v\n             data/full_repos/permissive/132439949/sim_1/new,data/full_repos/permissive/132439949/A_delay.sv\n             A_delay\n             A_delay.v\n             A_delay.sv\n             obj_dir/A_delay\n             obj_dir/A_delay.v\n             obj_dir/A_delay.sv\n%Error: Exiting due to 1 error(s)\n"
module test_A_delay(

    );
    
     reg [11:0] data_in;
     reg clk_write;
     
     wire pitch_shift;
     
     A_delay dut(data_in, clk_write, pitch_shift);
     
     always @(posedge clk_write) begin
        pitch_shift <= pitch_shift + 1;
    end
    
endmodule
module test_A_delay(

    );

    
     reg [11:0] data_in;
     reg clk_write;
     
     wire pitch_shift;
     
     A_delay dut(data_in, clk_write, pitch_shift);
     
     always @(posedge clk_write) begin
        pitch_shift <= pitch_shift + 1;
    end
    
endmodule