data/full_repos/permissive/156129873/verilog/if_id.v
1: b'%Error: data/full_repos/permissive/156129873/verilog/if_id.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/156129873/verilog/if_id.v:23: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/if_id.v:23: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (rst == `RstEnable) begin\n                             ^\n%Error: data/full_repos/permissive/156129873/verilog/if_id.v:24: Define or directive not defined: \'`ZERO\'\n            id_pc <= `ZERO;\n                     ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/if_id.v:29: syntax error, unexpected else\n  else if (pause == `Enable) begin\n  ^~~~\n%Error: data/full_repos/permissive/156129873/verilog/if_id.v:29: Define or directive not defined: \'`Enable\'\n  else if (pause == `Enable) begin\n                    ^~~~~~~\n%Error: Cannot continue\n'
module if_id(
    input wire clk,
    input wire rst,
    input wire pause,



    input wire[15:0] if_pc,
    input wire[15:0] if_ins,


    input wire vmem_pause_i,



    output reg[15:0] id_pc,
    output reg[15:0] id_ins
    );

    always @(posedge clk) begin
        if (rst == `RstEnable) begin
            id_pc <= `ZERO;
            id_ins <= 16'b0000100000000000;
        endelse if (pause == `Enable) begin

            id_pc <= id_pc;
            id_ins <= id_ins;
        end else begin
            id_pc <= if_pc;
            id_ins <= if_ins;
        end
    end

endmodule
module if_id(
    input wire clk,
    input wire rst,
    input wire pause,



    input wire[15:0] if_pc,
    input wire[15:0] if_ins,


    input wire vmem_pause_i,



    output reg[15:0] id_pc,
    output reg[15:0] id_ins
    );


    always @(posedge clk) begin
        if (rst == `RstEnable) begin
            id_pc <= `ZERO;
            id_ins <= 16'b0000100000000000;
        endelse if (pause == `Enable) begin

            id_pc <= id_pc;
            id_ins <= id_ins;
        end else begin
            id_pc <= if_pc;
            id_ins <= if_ins;
        end
    end

endmodule