data/full_repos/permissive/123786074/processor.v
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1: b"%Error: data/full_repos/permissive/123786074/processor.v:45: Cannot find file containing module: 'clock_divider'\n clock_divider clock_divider1(clock, enable, finish, clk);  \n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123786074,data/full_repos/permissive/123786074/clock_divider\n             data/full_repos/permissive/123786074,data/full_repos/permissive/123786074/clock_divider.v\n             data/full_repos/permissive/123786074,data/full_repos/permissive/123786074/clock_divider.sv\n             clock_divider\n             clock_divider.v\n             clock_divider.sv\n             obj_dir/clock_divider\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.sv\n%Error: data/full_repos/permissive/123786074/processor.v:46: Cannot find file containing module: 'state_machine'\n state_machine state_machine1(clk, z, IR, pcinc, r1inc, r2inc, r3inc, acinc, MUXSel, aluop, fetch, cflag, finish);  \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/123786074/processor.v:47: Cannot find file containing module: 'mux'\n mux mux1(MUXSel, ram_out, PC, R1, R2, R3, R, AC, iram_out, bus);  \n ^~~\n%Error: data/full_repos/permissive/123786074/processor.v:48: Cannot find file containing module: 'alu'\n alu alu16(AC, bus, aluop, C_bus, z);  \n ^~~\n%Error: data/full_repos/permissive/123786074/processor.v:50: Cannot find file containing module: 'regn'\n regn ar(clk, cflag[7], bus, dram_addr);  \n ^~~~\n%Error: data/full_repos/permissive/123786074/processor.v:51: Cannot find file containing module: 'regn'\n regn r(clk, cflag[2], bus, R);  \n ^~~~\n%Error: data/full_repos/permissive/123786074/processor.v:52: Cannot find file containing module: 'regn'\n regn ir(clk, fetch, bus[7:0], IR);   \n ^~~~\n%Error: data/full_repos/permissive/123786074/processor.v:54: Cannot find file containing module: 'regn_incr'\n regn_incr pc(clk, cflag[6], pcinc, bus, PC);  \n ^~~~~~~~~\n%Error: data/full_repos/permissive/123786074/processor.v:55: Cannot find file containing module: 'regn_incr'\n regn_incr r1(clk,cflag[5],r1inc,bus,R1);  \n ^~~~~~~~~\n%Error: data/full_repos/permissive/123786074/processor.v:56: Cannot find file containing module: 'regn_incr'\n regn_incr r2(clk,cflag[4],r2inc,bus,R2);  \n ^~~~~~~~~\n%Error: data/full_repos/permissive/123786074/processor.v:57: Cannot find file containing module: 'regn_incr'\n regn_incr r3(clk,cflag[3],r3inc,bus,R3);  \n ^~~~~~~~~\n%Error: data/full_repos/permissive/123786074/processor.v:58: Cannot find file containing module: 'regn_incr'\n regn_incr ac(clk,cflag[1],acinc,C_bus,AC);  \n ^~~~~~~~~\n%Error: Exiting due to 12 error(s)\n"
module processor (clock, enable, ram_out, iram_out, finish, clock_out, dram_wr_en, dram_addr, dram_din, iram_addr); 
 input								clock;
 input 								enable;
 input 			[7:0] 			ram_out;
 input 			[7:0] 			iram_out;
 output								finish;
 output 								clock_out;
 output								dram_wr_en;
 output 			[15:0] 			dram_addr;
 output 			[7:0] 			dram_din;
 output 			[7:0]				iram_addr;
  
 wire clk;
 wire z;
 wire pcinc;
 wire r1inc, r2inc, r3inc;
 wire acinc;
 wire fetch;
 wire [2:0] MUXSel;
 wire [2:0] aluop;
 wire [7:0] IR;
 wire [7:0] cflag;
 wire [15:0] bus;
 wire [15:0] PC, R1, R2, R3, R;
 wire [15:0] AC;
 wire [15:0] C_bus;
  
 assign 	clock_out = clk; 
 assign	dram_wr_en = cflag[0]; 
 assign 	dram_din = bus[7:0]; 
 assign	iram_addr = PC[7:0]; 
  

 clock_divider clock_divider1(clock, enable, finish, clk);
 state_machine state_machine1(clk, z, IR, pcinc, r1inc, r2inc, r3inc, acinc, MUXSel, aluop, fetch, cflag, finish);
 mux mux1(MUXSel, ram_out, PC, R1, R2, R3, R, AC, iram_out, bus);
 alu alu16(AC, bus, aluop, C_bus, z);
 
 regn ar(clk, cflag[7], bus, dram_addr);
 regn r(clk, cflag[2], bus, R);
 regn ir(clk, fetch, bus[7:0], IR);
 defparam ir.n = 8;
 regn_incr pc(clk, cflag[6], pcinc, bus, PC);
 regn_incr r1(clk,cflag[5],r1inc,bus,R1);
 regn_incr r2(clk,cflag[4],r2inc,bus,R2);
 regn_incr r3(clk,cflag[3],r3inc,bus,R3);
 regn_incr ac(clk,cflag[1],acinc,C_bus,AC);
  
endmodule
module processor (clock, enable, ram_out, iram_out, finish, clock_out, dram_wr_en, dram_addr, dram_din, iram_addr);
 
 input								clock;
 input 								enable;
 input 			[7:0] 			ram_out;
 input 			[7:0] 			iram_out;
 output								finish;
 output 								clock_out;
 output								dram_wr_en;
 output 			[15:0] 			dram_addr;
 output 			[7:0] 			dram_din;
 output 			[7:0]				iram_addr;
  
 wire clk;
 wire z;
 wire pcinc;
 wire r1inc, r2inc, r3inc;
 wire acinc;
 wire fetch;
 wire [2:0] MUXSel;
 wire [2:0] aluop;
 wire [7:0] IR;
 wire [7:0] cflag;
 wire [15:0] bus;
 wire [15:0] PC, R1, R2, R3, R;
 wire [15:0] AC;
 wire [15:0] C_bus;
  
 assign 	clock_out = clk; 
 assign	dram_wr_en = cflag[0]; 
 assign 	dram_din = bus[7:0]; 
 assign	iram_addr = PC[7:0]; 
  

 clock_divider clock_divider1(clock, enable, finish, clk);
 state_machine state_machine1(clk, z, IR, pcinc, r1inc, r2inc, r3inc, acinc, MUXSel, aluop, fetch, cflag, finish);
 mux mux1(MUXSel, ram_out, PC, R1, R2, R3, R, AC, iram_out, bus);
 alu alu16(AC, bus, aluop, C_bus, z);
 
 regn ar(clk, cflag[7], bus, dram_addr);
 regn r(clk, cflag[2], bus, R);
 regn ir(clk, fetch, bus[7:0], IR);
 defparam ir.n = 8;
 regn_incr pc(clk, cflag[6], pcinc, bus, PC);
 regn_incr r1(clk,cflag[5],r1inc,bus,R1);
 regn_incr r2(clk,cflag[4],r2inc,bus,R2);
 regn_incr r3(clk,cflag[3],r3inc,bus,R3);
 regn_incr ac(clk,cflag[1],acinc,C_bus,AC);
  
endmodule