data/full_repos/permissive/157608247/testbench/candy_load_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:1: Cannot find include file: candy_defines.v\n`include "candy_defines.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v.v\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v.sv\n             candy_defines.v\n             candy_defines.v.v\n             candy_defines.v.sv\n             obj_dir/candy_defines.v\n             obj_dir/candy_defines.v.v\n             obj_dir/candy_defines.v.sv\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:9: Define or directive not defined: \'`RegAddrBus\'\nreg  [`RegAddrBus] rd;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg  [`RegAddrBus] rd;\n                 ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:10: Define or directive not defined: \'`ImmWidth\'\nreg [`ImmWidth] imm;\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`ImmWidth] imm;\n              ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:12: Define or directive not defined: \'`RegAddrBus\'\nwire [`RegAddrBus] reg_waddr;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`RegAddrBus] reg_waddr;\n                 ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:13: Define or directive not defined: \'`RegBus\'\nwire [`RegBus] reg_wdata;\n      ^~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`RegBus] reg_wdata;\n             ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:29: Define or directive not defined: \'`RstEnable\'\n        rst <= `RstEnable;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:29: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst <= `RstEnable;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #0 begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:33: Define or directive not defined: \'`RstDisable\'\n        rst <= `RstDisable;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:33: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst <= `RstDisable;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #25 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #25 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_load_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: Exiting due to 13 error(s), 4 warning(s)\n'
module candy_load_tb;

reg clk;
reg rst;
reg ld_en;

reg  [`RegAddrBus] rd;
reg [`ImmWidth] imm;

wire [`RegAddrBus] reg_waddr;
wire [`RegBus] reg_wdata;

candy_load ld(
    .clk(clk),
    .rst(rst),
    .load_enable(ld_en),
    .rd(rd),
    .imm(imm),
    .reg_waddr(reg_waddr),
    .reg_wdata(reg_wdata)
);


initial begin
    #0 begin
        clk <= 1'b0;
        rst <= `RstEnable;
        ld_en <= 1'b1;
    end
    #25 begin
        rst <= `RstDisable;
        rd <= 4'd9;
        imm <= 16'd113;
    end
    #25 begin
        rd <= 4'd10;
        imm <= 16'd32345;
    end
end

always #5 clk <= ~clk;

endmodule
module candy_load_tb;


reg clk;
reg rst;
reg ld_en;

reg  [`RegAddrBus] rd;
reg [`ImmWidth] imm;

wire [`RegAddrBus] reg_waddr;
wire [`RegBus] reg_wdata;

candy_load ld(
    .clk(clk),
    .rst(rst),
    .load_enable(ld_en),
    .rd(rd),
    .imm(imm),
    .reg_waddr(reg_waddr),
    .reg_wdata(reg_wdata)
);


initial begin
    #0 begin
        clk <= 1'b0;
        rst <= `RstEnable;
        ld_en <= 1'b1;
    end
    #25 begin
        rst <= `RstDisable;
        rd <= 4'd9;
        imm <= 16'd113;
    end
    #25 begin
        rd <= 4'd10;
        imm <= 16'd32345;
    end
end

always #5 clk <= ~clk;

endmodule