data/full_repos/permissive/149848590/src/cpu/core/registers/HILO.v
1: b'%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILO.v:3: Cannot find include file: ../define/bus.v\n`include "../define/bus.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149848590/src/cpu/core/registers,data/full_repos/permissive/149848590/../define/bus.v\n             data/full_repos/permissive/149848590/src/cpu/core/registers,data/full_repos/permissive/149848590/../define/bus.v.v\n             data/full_repos/permissive/149848590/src/cpu/core/registers,data/full_repos/permissive/149848590/../define/bus.v.sv\n             ../define/bus.v\n             ../define/bus.v.v\n             ../define/bus.v.sv\n             obj_dir/../define/bus.v\n             obj_dir/../define/bus.v.v\n             obj_dir/../define/bus.v.sv\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILO.v:9: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] hi_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILO.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] hi_in,\n                    ^\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILO.v:10: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] lo_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILO.v:11: Define or directive not defined: \'`DATA_BUS\'\n    output reg[`DATA_BUS] hi,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILO.v:12: Define or directive not defined: \'`DATA_BUS\'\n    output reg[`DATA_BUS] lo\n               ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module HILO(
    input clk,
    input rst,
    input write_en,
    input [`DATA_BUS] hi_in,
    input [`DATA_BUS] lo_in,
    output reg[`DATA_BUS] hi,
    output reg[`DATA_BUS] lo
);

    always @(posedge clk) begin
        if (!rst) begin
            hi <= 0;
            lo <= 0;
        end
        else if (write_en) begin
            hi <= hi_in;
            lo <= lo_in;
        end
    end

endmodule
module HILO(
    input clk,
    input rst,
    input write_en,
    input [`DATA_BUS] hi_in,
    input [`DATA_BUS] lo_in,
    output reg[`DATA_BUS] hi,
    output reg[`DATA_BUS] lo
);


    always @(posedge clk) begin
        if (!rst) begin
            hi <= 0;
            lo <= 0;
        end
        else if (write_en) begin
            hi <= hi_in;
            lo <= lo_in;
        end
    end

endmodule