data/full_repos/permissive/148324174/SeqLogic/sync_h2lck.v
data/verilator_xmls/19baee0e-c54b-4973-aa30-3f133c4de878.xml
module sync_h2lck(
    input async_in, bclk, rst,
    output sync_out
    );

reg q1, q2, q3;
wire async_rst;

assign async_rst = !async_in && sync_out;

always @(posedge async_in or posedge async_rst) begin
    if (async_rst) begin
        q1 <= 1'b0;
    end
    else begin
        q1 <= 1'b1;
    end
end

always @(posedge bclk or posedge rst) begin
    if (rst) begin
        q2 <= 1'b0;
        q3 <= 1'b0;
    end
    else begin
        q2 <= q1;
        q3 <= q2;
    end
end

assign sync_out = q3;

endmodule
module sync_h2lck(
    input async_in, bclk, rst,
    output sync_out
    );


reg q1, q2, q3;
wire async_rst;

assign async_rst = !async_in && sync_out;

always @(posedge async_in or posedge async_rst) begin
    if (async_rst) begin
        q1 <= 1'b0;
    end
    else begin
        q1 <= 1'b1;
    end
end

always @(posedge bclk or posedge rst) begin
    if (rst) begin
        q2 <= 1'b0;
        q3 <= 1'b0;
    end
    else begin
        q2 <= q1;
        q3 <= q2;
    end
end

assign sync_out = q3;

endmodule