data/full_repos/permissive/175808891/verilog/cache_coherence.v
data/verilator_xmls/003b368d-0972-4827-8b40-9b64c0460f58.xml
module cache_coherence ( 

	new_state, 

	Cache_Sector_Fill, 

	Invalidate,  

	AdrRetry,

	RMS, 

	RME, 

	WM, 

	WH,  

	SHR, 

	SHW, 

	state, 

	READ_DONE, 

	clk, 

	reset, 

	send_abort, 

	write_back_done,

	AllInvDone);



input RMS, RME, WM, WH, SHR, SHW, READ_DONE, clk, 

      reset, send_abort, write_back_done, AllInvDone;



input [2:0] state;



output [2:0] new_state;

output Cache_Sector_Fill, Invalidate, AdrRetry;



reg Cache_Sector_Fill, Invalidate, AdrRetry ;

reg [2:0] new_state; 









parameter

	INVALID = 3'b000,

	SHARED_1 = 3'b001,

	EXCLUSIVE = 3'b010,

	MODIFIED = 3'b011,

	Cache_Fill = 3'b100,

	start_write_back = 3'b101,



	WaitUntilAllInv = 3'b110;





reg [2:0]present_state;

reg [2:0]next_state;







always @(present_state or RMS or RME or WM or WH or SHW or READ_DONE 

         or SHR or write_back_done or AllInvDone or send_abort or state or reset) 

begin

	Cache_Sector_Fill = 0;

	Invalidate = 0; 

	AdrRetry = 0; 

	next_state = present_state; 

	if (reset) next_state = state; else 

	begin

	case(present_state)

		INVALID: 



			if (RMS || RME || WM)  			 

			begin

				Cache_Sector_Fill = 1;

				next_state = Cache_Fill ;

			end

			else 

			begin 

				next_state = INVALID;

			end



		Cache_Fill:	



			if (send_abort) 

			begin 

				next_state = INVALID;

			end

			else if (READ_DONE) 

			begin

				if (RMS) 

				begin

					next_state = SHARED_1;

				end

				else if (RME) 

				begin 

					next_state = EXCLUSIVE;	

				end

				else if (WM)

				begin

					Invalidate = 1;

					next_state = WaitUntilAllInv;

				end 

				else 

				begin 

					next_state = Cache_Fill ;

				end

			end	

			else 

			begin 

				next_state = Cache_Fill ;

			end

			

		SHARED_1:	  

			if (SHW)

			begin 

				next_state = INVALID;		

			end

			else if (WH)

			begin

				Invalidate = 1;

				next_state = WaitUntilAllInv;

			end 

			else 

			begin

				next_state = SHARED_1; 		

			end



		WaitUntilAllInv:





			if (AllInvDone) 

			begin 

				next_state = MODIFIED;

			end

			else 

			begin 

				next_state = WaitUntilAllInv;

			end



		EXCLUSIVE: 

								

			if (SHR)

			begin

				AdrRetry = 0;

				next_state = SHARED_1;  

			end 					

			else if (SHW)

			begin

				next_state = INVALID;	

			end

			else if (WH)

			begin

				next_state = MODIFIED;	

			end

			else 

			begin

				next_state = EXCLUSIVE;		

			end



		MODIFIED:  	

			if (SHW)

			begin

				next_state = INVALID;		

			end

			else if (SHR)

			begin

				AdrRetry = 1;

				next_state = start_write_back;

			end

			else

			begin

				next_state = MODIFIED; 		

			end



		start_write_back: 



			if (write_back_done) 

			begin

				next_state = SHARED_1; 

			end

			else

			begin 

				next_state = start_write_back;

			end

			

	endcase

	end

	

end





always @(posedge clk) 

begin

	present_state = next_state;

	new_state = next_state;

end


endmodule
module cache_coherence ( 

	new_state, 

	Cache_Sector_Fill, 

	Invalidate,  

	AdrRetry,

	RMS, 

	RME, 

	WM, 

	WH,  

	SHR, 

	SHW, 

	state, 

	READ_DONE, 

	clk, 

	reset, 

	send_abort, 

	write_back_done,

	AllInvDone);




input RMS, RME, WM, WH, SHR, SHW, READ_DONE, clk, 

      reset, send_abort, write_back_done, AllInvDone;



input [2:0] state;



output [2:0] new_state;

output Cache_Sector_Fill, Invalidate, AdrRetry;



reg Cache_Sector_Fill, Invalidate, AdrRetry ;

reg [2:0] new_state; 









parameter

	INVALID = 3'b000,

	SHARED_1 = 3'b001,

	EXCLUSIVE = 3'b010,

	MODIFIED = 3'b011,

	Cache_Fill = 3'b100,

	start_write_back = 3'b101,



	WaitUntilAllInv = 3'b110;





reg [2:0]present_state;

reg [2:0]next_state;







always @(present_state or RMS or RME or WM or WH or SHW or READ_DONE 

         or SHR or write_back_done or AllInvDone or send_abort or state or reset) 

begin

	Cache_Sector_Fill = 0;

	Invalidate = 0; 

	AdrRetry = 0; 

	next_state = present_state; 

	if (reset) next_state = state; else 

	begin

	case(present_state)

		INVALID: 



			if (RMS || RME || WM)  			 

			begin

				Cache_Sector_Fill = 1;

				next_state = Cache_Fill ;

			end

			else 

			begin 

				next_state = INVALID;

			end



		Cache_Fill:	



			if (send_abort) 

			begin 

				next_state = INVALID;

			end

			else if (READ_DONE) 

			begin

				if (RMS) 

				begin

					next_state = SHARED_1;

				end

				else if (RME) 

				begin 

					next_state = EXCLUSIVE;	

				end

				else if (WM)

				begin

					Invalidate = 1;

					next_state = WaitUntilAllInv;

				end 

				else 

				begin 

					next_state = Cache_Fill ;

				end

			end	

			else 

			begin 

				next_state = Cache_Fill ;

			end

			

		SHARED_1:	  

			if (SHW)

			begin 

				next_state = INVALID;		

			end

			else if (WH)

			begin

				Invalidate = 1;

				next_state = WaitUntilAllInv;

			end 

			else 

			begin

				next_state = SHARED_1; 		

			end



		WaitUntilAllInv:





			if (AllInvDone) 

			begin 

				next_state = MODIFIED;

			end

			else 

			begin 

				next_state = WaitUntilAllInv;

			end



		EXCLUSIVE: 

								

			if (SHR)

			begin

				AdrRetry = 0;

				next_state = SHARED_1;  

			end 					

			else if (SHW)

			begin

				next_state = INVALID;	

			end

			else if (WH)

			begin

				next_state = MODIFIED;	

			end

			else 

			begin

				next_state = EXCLUSIVE;		

			end



		MODIFIED:  	

			if (SHW)

			begin

				next_state = INVALID;		

			end

			else if (SHR)

			begin

				AdrRetry = 1;

				next_state = start_write_back;

			end

			else

			begin

				next_state = MODIFIED; 		

			end



		start_write_back: 



			if (write_back_done) 

			begin

				next_state = SHARED_1; 

			end

			else

			begin 

				next_state = start_write_back;

			end

			

	endcase

	end

	

end





always @(posedge clk) 

begin

	present_state = next_state;

	new_state = next_state;

end


endmodule