data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_a6.v
1: b"%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_a6.v:62: Cannot find file containing module: 'jt74245'\njt74245 u10H(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74245\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74245.v\n             data/full_repos/permissive/129527056/model/gng/hdl,data/full_repos/permissive/129527056/jt74245.sv\n             jt74245\n             jt74245.v\n             jt74245.sv\n             obj_dir/jt74245\n             obj_dir/jt74245.v\n             obj_dir/jt74245.sv\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_a6.v:78: Cannot find file containing module: 'jt74273'\njt74273 u9H( .clk(keep_clk), .d(DC), .q(aux), .cl_b(1'b1) );\n^~~~~~~\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_a6.v:79: Cannot find file containing module: 'jt74273'\njt74273 u9F( .clk(G4H), .d(aux), .q(AC[7:0]), .cl_b(1'b1) );\n^~~~~~~\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_a6.v:81: Cannot find file containing module: 'jt74273'\njt74273 u8H( .clk(G4H), .d(DC), .q(aux2), .cl_b(1'b1) );\n^~~~~~~\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_a6.v:82: Cannot find file containing module: 'jt74174'\njt74174 u8F( .clk(OH), .d(aux2[5:0]), .q(aux3), .cl_b(1'b1) );\n^~~~~~~\n%Error: data/full_repos/permissive/129527056/model/gng/hdl/jt_gng_a6.v:85: Cannot find file containing module: 'jt_gng_genram'\njt_gng_genram #(.addrw(11),.id(3)) u_7H (\n^~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module jt_gng_a6(
	input	H2,
	input	H4,
	input	H8,
	input	H16,
	input	H32,
	input	H64,
	input	H128,
	input	H256,
	input	V8,
	input	V16,
	input	V32,
	input	V64,
	input	V128,
	input	G4H,
	input	FLIP,
	output	MRDY_b,
	input	MRDY2_b,
	input	CHARCS_b,
	input	OH,
	input	N4H,
	output [3:0] CC,
	output	CHHFLIP,
	output	CHHFLIPq,
	output	CHVFLIP,
	output	[9:0] AC,
	inout	[7:0] DB,
	input	RDB_b,
	inout	[10:0] AB
);

reg [10:0] ram_addr;
reg	ram_we_b;


assign MRDY_b = MRDY2_b & (CHARCS_b | (H2&H4));

wire sel = ~H4;
always @(*)

	if( !sel ) begin
		ram_addr = AB;
		ram_we_b = CHARCS_b | ~RDB_b;
	end else begin
		ram_we_b = 1'b1;
		ram_addr = { H2, {10{FLIP}}^{V128,V64,V32,V16,V8,H128,H64,H32,H16,H8}};
	end

wire [7:0] DC;

wire CPU_access_ok = ~H4 | CHARCS_b;
wire keep_clk = H2 & ~H4;

jt74245 u10H(
	.a		( DB 			),
	.b		( DC 			),
	.dir	( RDB_b 		),
	.en_b	( CPU_access_ok )
);

wire [7:0] aux, aux2;
wire [5:0] aux3;

assign AC[9:8] = aux2[7:6];
assign CHVFLIP = aux2[5];
assign CHHFLIP = aux2[4];
assign CHHFLIPq = aux3[4];
assign CC = aux3[3:0];

jt74273 u9H( .clk(keep_clk), .d(DC), .q(aux), .cl_b(1'b1) );
jt74273 u9F( .clk(G4H), .d(aux), .q(AC[7:0]), .cl_b(1'b1) );

jt74273 u8H( .clk(G4H), .d(DC), .q(aux2), .cl_b(1'b1) );
jt74174 u8F( .clk(OH), .d(aux2[5:0]), .q(aux3), .cl_b(1'b1) );


jt_gng_genram #(.addrw(11),.id(3)) u_7H (
	.A		(ram_addr	),
	.D		(DC			),
	.cs_b	(1'b0		),
	.rd_b	(1'b0		),
	.wr_b	(ram_we_b	)
);

endmodule
module jt_gng_a6(
	input	H2,
	input	H4,
	input	H8,
	input	H16,
	input	H32,
	input	H64,
	input	H128,
	input	H256,
	input	V8,
	input	V16,
	input	V32,
	input	V64,
	input	V128,
	input	G4H,
	input	FLIP,
	output	MRDY_b,
	input	MRDY2_b,
	input	CHARCS_b,
	input	OH,
	input	N4H,
	output [3:0] CC,
	output	CHHFLIP,
	output	CHHFLIPq,
	output	CHVFLIP,
	output	[9:0] AC,
	inout	[7:0] DB,
	input	RDB_b,
	inout	[10:0] AB
);


reg [10:0] ram_addr;
reg	ram_we_b;


assign MRDY_b = MRDY2_b & (CHARCS_b | (H2&H4));

wire sel = ~H4;
always @(*)

	if( !sel ) begin
		ram_addr = AB;
		ram_we_b = CHARCS_b | ~RDB_b;
	end else begin
		ram_we_b = 1'b1;
		ram_addr = { H2, {10{FLIP}}^{V128,V64,V32,V16,V8,H128,H64,H32,H16,H8}};
	end

wire [7:0] DC;

wire CPU_access_ok = ~H4 | CHARCS_b;
wire keep_clk = H2 & ~H4;

jt74245 u10H(
	.a		( DB 			),
	.b		( DC 			),
	.dir	( RDB_b 		),
	.en_b	( CPU_access_ok )
);

wire [7:0] aux, aux2;
wire [5:0] aux3;

assign AC[9:8] = aux2[7:6];
assign CHVFLIP = aux2[5];
assign CHHFLIP = aux2[4];
assign CHHFLIPq = aux3[4];
assign CC = aux3[3:0];

jt74273 u9H( .clk(keep_clk), .d(DC), .q(aux), .cl_b(1'b1) );
jt74273 u9F( .clk(G4H), .d(aux), .q(AC[7:0]), .cl_b(1'b1) );

jt74273 u8H( .clk(G4H), .d(DC), .q(aux2), .cl_b(1'b1) );
jt74174 u8F( .clk(OH), .d(aux2[5:0]), .q(aux3), .cl_b(1'b1) );


jt_gng_genram #(.addrw(11),.id(3)) u_7H (
	.A		(ram_addr	),
	.D		(DC			),
	.cs_b	(1'b0		),
	.rd_b	(1'b0		),
	.wr_b	(ram_we_b	)
);

endmodule