data/full_repos/permissive/211891954/Finite States Machine/Maquina de Moore/Exemplo 3/moore.v
 line:14: before: "in"
1: b'%Error: Cannot find file containing module: States\n        ... Looked in:\n             data/full_repos/permissive/211891954/Finite/States\n             data/full_repos/permissive/211891954/Finite/States.v\n             data/full_repos/permissive/211891954/Finite/States.sv\n             States\n             States.v\n             States.sv\n             obj_dir/States\n             obj_dir/States.v\n             obj_dir/States.sv\n%Error: Cannot find file containing module: Machine/Maquina\n%Error: Cannot find file containing module: de\n%Error: Cannot find file containing module: Moore/Exemplo\n%Error: Cannot find file containing module: 3,data/full_repos/permissive/211891954\n%Error: Cannot find file containing module: data/full_repos/permissive/211891954/Finite\n%Error: Cannot find file containing module: 3/moore.v\n%Error: Exiting due to 7 error(s)\n'
module counter_odd(clk,rst,in,out);
    input wire clk,rst,in;
    output reg out;

    reg[1:0] estados;
    reg[1:0] proximo_estado;
    reg count =0;

    parameter   In = 2'b00,
                S0 = 2'b01,
                S1 = 2'b10,
                S2 = 2'b11;

    always @(posedge clk or in or rst) begin
       if(rst)begin
           estados = In;
       end
       else begin
           case (estados)                       
               In:begin
                    proximo_estado = S0;          
               end
               S0:begin
                    if (in == 1'b1 && count % 3 == 0)begin
                        proximo_estado = S1;  
                        out = 1'b1;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b1 &&  count % 3 !=0)begin
                        proximo_estado = S1;
                        out = 1'b0;
                        count = count + 1'b1;
                    end
                        
                    else if(in == 1'b0 && count % 3 == 0)begin
                        out = 1'b1;
                        proximo_estado = S0;
                    end

                    else if(in == 1'b0 && count % 3 !=0)begin
                        out = 1'b0;
                        proximo_estado = S0;
                    end
               end

               S1:begin
                    if (in == 1'b1 && count % 3 == 0)begin
                        proximo_estado = S2;  
                        out = 1'b1;
                        count = count + 1'b1;
                    end
                    else if(in == 1'b1 &&  count % 3 !=0)begin
                        proximo_estado = S2;
                        out = 1'b0;
                        count = count + 1'b1;
                    end
                    else if(in == 1'b0 && count % 3 == 0)begin
                        out = 1'b1;
                        proximo_estado = S1;
                    end
                    else if(in == 1'b0 && count % 3 !=0)begin
                        out = 1'b0;
                        proximo_estado = S1;
                    end
                end

               S2:begin
                    if (in == 1'b1 && count % 3 == 0)begin
                        proximo_estado = S0;  
                        out = 1'b1;
                        count = count + 1'b1;
                    end
                    else if(in == 1'b1 &&  count % 3 !=0)begin
                        proximo_estado = S0;
                        out = 1'b0;
                        count = count + 1'b1;
                    end
                    else if(in == 1'b0 && count % 3 == 0)begin
                        out = 1'b1;
                        proximo_estado = S2;
                    end
                    else if(in == 1'b0 && count % 3 !=0)begin
                        out = 1'b0;
                        proximo_estado = S2;
                   end
               end

           endcase
       end 
    end
endmodule
module counter_odd(clk,rst,in,out);

    input wire clk,rst,in;
    output reg out;

    reg[1:0] estados;
    reg[1:0] proximo_estado;
    reg count =0;

    parameter   In = 2'b00,
                S0 = 2'b01,
                S1 = 2'b10,
                S2 = 2'b11;

    always @(posedge clk or in or rst) begin
       if(rst)begin
           estados = In;
       end
       else begin
           case (estados)                       
               In:begin
                    proximo_estado = S0;          
               end
               S0:begin
                    if (in == 1'b1 && count % 3 == 0)begin
                        proximo_estado = S1;  
                        out = 1'b1;
                        count = count + 1'b1;
                    end

                    else if(in == 1'b1 &&  count % 3 !=0)begin
                        proximo_estado = S1;
                        out = 1'b0;
                        count = count + 1'b1;
                    end
                        
                    else if(in == 1'b0 && count % 3 == 0)begin
                        out = 1'b1;
                        proximo_estado = S0;
                    end

                    else if(in == 1'b0 && count % 3 !=0)begin
                        out = 1'b0;
                        proximo_estado = S0;
                    end
               end

               S1:begin
                    if (in == 1'b1 && count % 3 == 0)begin
                        proximo_estado = S2;  
                        out = 1'b1;
                        count = count + 1'b1;
                    end
                    else if(in == 1'b1 &&  count % 3 !=0)begin
                        proximo_estado = S2;
                        out = 1'b0;
                        count = count + 1'b1;
                    end
                    else if(in == 1'b0 && count % 3 == 0)begin
                        out = 1'b1;
                        proximo_estado = S1;
                    end
                    else if(in == 1'b0 && count % 3 !=0)begin
                        out = 1'b0;
                        proximo_estado = S1;
                    end
                end

               S2:begin
                    if (in == 1'b1 && count % 3 == 0)begin
                        proximo_estado = S0;  
                        out = 1'b1;
                        count = count + 1'b1;
                    end
                    else if(in == 1'b1 &&  count % 3 !=0)begin
                        proximo_estado = S0;
                        out = 1'b0;
                        count = count + 1'b1;
                    end
                    else if(in == 1'b0 && count % 3 == 0)begin
                        out = 1'b1;
                        proximo_estado = S2;
                    end
                    else if(in == 1'b0 && count % 3 !=0)begin
                        out = 1'b0;
                        proximo_estado = S2;
                   end
               end

           endcase
       end 
    end
endmodule