data/full_repos/permissive/200478172/source/Z.v
data/verilator_xmls/0bd4c445-8523-4a25-8118-c26887ec9e2c.xml
module Z(
    input ctr,

    input [31:0] data_in,
    output [31:0] data_out
    );
    wire[31:0]temp;
    assign temp=(ctr)?data_in:temp;
    assign data_out=(ctr)?temp:data_out;
endmodule
module Z(
    input ctr,

    input [31:0] data_in,
    output [31:0] data_out
    );

    wire[31:0]temp;
    assign temp=(ctr)?data_in:temp;
    assign data_out=(ctr)?temp:data_out;
endmodule