data/full_repos/permissive/151548608/MHP2/work/planAhead/MHP2/MHP2.srcs/sources_1/imports/verilog/decoder_13.v
1: b'%Warning-WIDTH: data/full_repos/permissive/151548608/MHP2/work/planAhead/MHP2/MHP2.srcs/sources_1/imports/verilog/decoder_13.v:20: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                 : ... In instance decoder_13\n    out = 1\'h0;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module decoder_13 (
    input [1:0] in,
    output reg [3:0] out
  );
  
  localparam WIDTH = 2'h2;
  
  
  always @* begin
    out = 1'h0;
    out[(in)*1+0-:1] = 1'h1;
  end
endmodule
module decoder_13 (
    input [1:0] in,
    output reg [3:0] out
  );

  
  localparam WIDTH = 2'h2;
  
  
  always @* begin
    out = 1'h0;
    out[(in)*1+0-:1] = 1'h1;
  end
endmodule