data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v
 line:64: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #25\n  ^\n%Error: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:64: syntax error, unexpected \'@\'\n        @ (negedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #25\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        # 2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #170;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T1800/AES-T1800/src/TjIn/battery_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module battery_tb;


	reg clk;
	reg rst;
	reg [127:0] state;
	reg [127:0] key;


	wire [127:0] out;


	top uut (
		.clk(clk), 
		.rst(rst), 
		.state(state), 
		.key(key), 
		.out(out)
	);


	initial begin
		clk = 0;
		state = 0;
		key = 0;
		rst = 0;

		#50
		rst = 1;
		
		#25
		rst = 0;

		#25

        @ (negedge clk);
        # 2;
        state = 128'h3243f6a8_885a308d_313198a2_e0370734;
        key   = 128'h2b7e1516_28aed2a6_abf71588_09cf4f3c;
        #10;
        state = 128'h00112233_44556677_8899aabb_ccddeeff;
        key   = 128'h00010203_04050607_08090a0b_0c0d0e0f;
        #10;
        state = 128'h0;
        key   = 128'h0;
        #10;
        state = 128'h0;
        key   = 128'h1;
        #10;
        state = 128'h1;
        key   = 128'h0;
        #170;
        if (out !== 128'h3925841d02dc09fbdc118597196a0b32)
          begin $display("E"); $finish; end
        #10;
        if (out !== 128'h69_c4_e0_d8_6a_7b_04_30_d8_cd_b7_80_70_b4_c5_5a)
          begin $display("E"); $finish; end
        #10;
        if (out !== 128'h66_e9_4b_d4_ef_8a_2c_3b_88_4c_fa_59_ca_34_2b_2e)
          begin $display("E"); $finish; end
        #10;
        if (out !== 128'h05_45_aa_d5_6d_a2_a9_7c_36_63_d1_43_2a_3d_1c_84)
          begin $display("E"); $finish; end
        #10;
        if (out !== 128'h58_e2_fc_ce_fa_7e_30_61_36_7f_1d_57_a4_e7_45_5a)
          begin $display("E"); $finish; end
        $display("Good.");
        $finish;
	end
      
    always #5 clk = ~clk;

endmodule
module battery_tb;



	reg clk;
	reg rst;
	reg [127:0] state;
	reg [127:0] key;


	wire [127:0] out;


	top uut (
		.clk(clk), 
		.rst(rst), 
		.state(state), 
		.key(key), 
		.out(out)
	);


	initial begin
		clk = 0;
		state = 0;
		key = 0;
		rst = 0;

		#50
		rst = 1;
		
		#25
		rst = 0;

		#25

        @ (negedge clk);
        # 2;
        state = 128'h3243f6a8_885a308d_313198a2_e0370734;
        key   = 128'h2b7e1516_28aed2a6_abf71588_09cf4f3c;
        #10;
        state = 128'h00112233_44556677_8899aabb_ccddeeff;
        key   = 128'h00010203_04050607_08090a0b_0c0d0e0f;
        #10;
        state = 128'h0;
        key   = 128'h0;
        #10;
        state = 128'h0;
        key   = 128'h1;
        #10;
        state = 128'h1;
        key   = 128'h0;
        #170;
        if (out !== 128'h3925841d02dc09fbdc118597196a0b32)
          begin $display("E"); $finish; end
        #10;
        if (out !== 128'h69_c4_e0_d8_6a_7b_04_30_d8_cd_b7_80_70_b4_c5_5a)
          begin $display("E"); $finish; end
        #10;
        if (out !== 128'h66_e9_4b_d4_ef_8a_2c_3b_88_4c_fa_59_ca_34_2b_2e)
          begin $display("E"); $finish; end
        #10;
        if (out !== 128'h05_45_aa_d5_6d_a2_a9_7c_36_63_d1_43_2a_3d_1c_84)
          begin $display("E"); $finish; end
        #10;
        if (out !== 128'h58_e2_fc_ce_fa_7e_30_61_36_7f_1d_57_a4_e7_45_5a)
          begin $display("E"); $finish; end
        $display("Good.");
        $finish;
	end
      
    always #5 clk = ~clk;

endmodule