data/full_repos/permissive/15431697/src/ocp_master_fsm.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:108: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output reg [0 - 1:0]    MDataInfo,\n             ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:109: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output reg [0 - 1:0]      MReqInfo,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:110: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input wire [0 - 1:0]    SDataInfo,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:111: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input wire [0 - 1:0]     SRespInfo,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:129: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output reg [0 - 1:0]              MDataTagID,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:130: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output reg [0 - 1:0]              MTagID,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:132: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input wire [0 - 1:0]              STagID,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:136: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output reg [0 - 1:0]      MConnID,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:137: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output reg [0 - 1:0]           MDataThreadID,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:138: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output reg [0 - 1:0]           MThreadBusy,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:139: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output reg [0 - 1:0]           MThreadID,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:140: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input wire [0 - 1:0]           SDataThreadBusy,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:141: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input wire [0 - 1:0]           SThreadBusy,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:142: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input wire [0 - 1:0]           SThreadID\n             ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:251: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n      state <= 3\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:252: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n      state[IDLE] <= 1\'b1;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:269: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n  next <= 3\'b0;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:290: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'SData\' generates 8 bits.\n                                                                            : ... In instance ocp_master_fsm\n        s_axis_tdata <= SData;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:307: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'SData\' generates 8 bits.\n                                                                            : ... In instance ocp_master_fsm\n        s_axis_tdata <= SData;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:343: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n          next[RD] <= 1\'b1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:347: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n          next[WR] <= 1\'b1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:351: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n          next[IDLE] <= 1\'b1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:340: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n    state[IDLE]: begin\n         ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:359: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n        next[IDLE] <= 1\'b1;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:363: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n        next[WR] <= 1\'b1;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:357: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n    state[WR]: begin\n         ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:370: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n        next[IDLE] <= 1\'b1;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:374: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n        next[RD] <= 1\'b1;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:368: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n    state[RD]: begin\n         ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:379: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n      next[IDLE] <= 1\'b1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:413: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MDataInfo         <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:414: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MReqInfo          <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:417: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MAtomicLength     <= 1\'b1;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:418: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MBlockHeight      <= 1\'b1;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:419: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MBlockStride      <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:420: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MBurstLength      <= 1\'b1;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:430: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MDataTagID        <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:431: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MTagID            <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:435: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MConnID           <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:436: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MDataThreadID     <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:437: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MThreadBusy       <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:438: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n    MThreadID         <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:499: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataInfo         <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:500: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MReqInfo          <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:503: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MAtomicLength     <= 1\'b1;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:504: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MBlockHeight      <= 1\'b1;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:505: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MBlockStride      <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:516: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataTagID        <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:517: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MTagID            <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:521: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MConnID           <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:522: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataThreadID     <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:523: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MThreadBusy       <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:524: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MThreadID         <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:473: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n      next[IDLE]: begin\n          ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:617: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataInfo         <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:618: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MReqInfo          <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:621: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MAtomicLength     <= 1\'b1;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:622: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MBlockHeight      <= 1\'b1;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:624: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MBlockStride      <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:637: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataTagID        <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:638: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MTagID            <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:642: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MConnID           <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:643: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataThreadID     <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:644: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MThreadBusy       <= 1\'b0;   \n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:645: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MThreadID         <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:554: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n      next[WR]: begin\n          ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:738: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataInfo         <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:739: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MReqInfo          <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:742: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MAtomicLength     <= 1\'b1;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:743: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MBlockHeight      <= 1\'b1;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:745: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MBlockStride      <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:758: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataTagID        <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:759: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MTagID            <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:763: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MConnID           <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:764: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataThreadID     <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:765: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MThreadBusy       <= 1\'b0;   \n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:766: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MThreadID         <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:675: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                            : ... In instance ocp_master_fsm\n      next[RD]: begin\n          ^\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:819: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataInfo         <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:820: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MReqInfo          <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:823: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MAtomicLength     <= 1\'b1;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:824: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MBlockHeight      <= 1\'b1;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:825: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MBlockStride      <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:826: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MBurstLength      <= 1\'b1;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:836: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataTagID        <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:837: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MTagID            <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:841: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MConnID           <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:842: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MDataThreadID     <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:843: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MThreadBusy       <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/15431697/src/ocp_master_fsm.v:844: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance ocp_master_fsm\n        MThreadID         <= 1\'b0;\n                          ^~\n%Error: Exiting due to 90 warning(s)\n'
module ocp_master_fsm(

  input wire [`addr_wdth - 1:0]         address,
  input wire                            enable,
  input wire [2:0]                      burst_seq,
  input wire                            burst_single_req,
  input wire [`request_length - 1:0]    burst_length,
  input wire                            data_valid,
  input wire                            read_request,
  input wire                            reset,
  input wire                            sys_clk,
  input wire [`data_wdth - 1:0]         valid_bytes,
  input wire [`data_wdth - 1:0]         write_data,
  input wire                            write_request,
  input wire                            writeresp_enable,
  output wire                           ocp_ready,


  output reg s_aclk,
  output reg s_axis_tvalid,
  input wire s_axis_tready,
  output reg [`fifo_wdth - 1:0] s_axis_tdata,
  output reg [`data_wdth - 1:0] s_axis_tkeep,
  output reg s_axis_tlast,
  input wire axis_overflow,



  

  output wire                           Clk,
  inout wire                            EnableClk,
  output reg [`addr_wdth - 1:0]         MAddr,
  output reg [2:0]                      MCmd,
  output reg [`data_wdth - 1:0]         MData,
  output reg                            MDataValid,
  output reg                            MRespAccept,
  input wire                            SCmdAccept,
  input wire [`data_wdth - 1:0]         SData,
  input wire                            SDataAccept,
  input wire [1:0]                      SResp,


  output reg [`addrspace_wdth - 1:0]    MAddrSpace,
  output reg [`data_wdth - 1:0]         MByteEn,
  output reg [`data_wdth - 1:0]         MDataByteEn,
  output reg [`mdatainfo_wdth - 1:0]    MDataInfo,
  output reg [`reqinfo_wdth - 1:0]      MReqInfo,
  input wire [`sdatainfo_wdth - 1:0]    SDataInfo,
  input wire [`respinfo_wdth - 1:0]     SRespInfo,


  output reg [`atomiclength_wdth - 1:0] MAtomicLength,
  output reg [`blockheight_wdth - 1:0]  MBlockHeight,
  output reg [`blockstride_wdth - 1:0]  MBlockStride,
  output reg [`burstlength_wdth - 1:0]  MBurstLength,
  output reg                            MBurstPrecise,
  output reg [2:0]                      MBurstSeq,
  output reg                            MBurstSingleSeq,
  output reg                            MDataLast,
  output reg                            MDataRowLast,
  output reg                            MReqLast,
  output reg                            MReqRowLast,
  input wire                            SRespLast,
  input wire                            SRespRowLast,


  output reg [`tags - 1:0]              MDataTagID,
  output reg [`tags - 1:0]              MTagID,
  output reg                            MTagInOrder,
  input wire [`tags - 1:0]              STagID,
  input wire                            STagInOrder,
  

  output reg [`connid_width - 1:0]      MConnID,
  output reg [`threads - 1:0]           MDataThreadID,
  output reg [`threads - 1:0]           MThreadBusy,
  output reg [`threads - 1:0]           MThreadID,
  input wire [`threads - 1:0]           SDataThreadBusy,
  input wire [`threads - 1:0]           SThreadBusy,
  input wire [`threads - 1:0]           SThreadID
  


















  












);






localparam IDLE  = 3'b000;
localparam WR    = 3'b001;
localparam RD    = 3'b010;
localparam RDEX  = 3'b011;
localparam RDL   = 3'b100;
localparam WRNP  = 3'b101;
localparam WRC   = 3'b110;
localparam BCST  = 3'b111;


localparam NULL  = 2'b00;
localparam DVA   = 2'b01;
localparam FAIL  = 2'b10;
localparam ERR   = 2'b11;


localparam INCR  = 3'b000;
localparam DFLT1 = 3'b001;
localparam WRAP  = 3'b010;
localparam DFLT2 = 3'b011;
localparam XOR   = 3'b100;
localparam STRM  = 3'b101;
localparam UNKN  = 3'b110;
localparam BLCK  = 3'b111;
























reg [3:0]                     state;
reg [3:0]                     next;


reg [`request_length - 1:0]   burst_count;
reg [`addr_wdth - 1:0]        base_address;
reg [`request_length - 1:0]   set_burst_length;
reg [2:0]                     set_burst_seq;
reg                           set_burst_single_req;
reg [`data_wdth - 1:0]        set_valid_bytes;
reg                           set_writeresp_enable;

assign EnableClk = enable;
assign Clk = sys_clk & enable;
assign ocp_ready = SCmdAccept;



always @(posedge Clk) begin
  if (EnableClk) begin
    if (reset) begin
      state <= 3'b0;
      state[IDLE] <= 1'b1;
    end

    else begin
      state <= next;
    end
  end

  else begin
    state <= state;
  end
end




always @(*) begin
  next <= 3'b0;


  case (SResp)

    NULL: begin
      s_aclk <= Clk;
      s_axis_tvalid <= 1'b1;
      

      s_axis_tdata <= {`fifo_wdth{1'bx}};
      s_axis_tkeep <= {`data_wdth{1'b0}};
    end


    DVA: begin
      s_aclk <= Clk;
      s_axis_tvalid <= 1'b1;
      

      if (s_axis_tready) begin
        s_axis_tdata <= SData;
        s_axis_tkeep <= {`data_wdth{1'b1}};
      end

      else begin
        s_axis_tdata <= {`fifo_wdth{1'bx}};
        s_axis_tkeep <= {`data_wdth{1'b0}};
      end
    end


    FAIL: begin
      s_aclk <= Clk;
      s_axis_tvalid <= 1'b1;


      if (s_axis_tready) begin
        s_axis_tdata <= SData;
        s_axis_tkeep <= {`data_wdth{1'b1}};
      end

      else begin
        s_axis_tdata <= {`fifo_wdth{1'bx}};
        s_axis_tkeep <= {`data_wdth{1'b0}};
      end
    end


    ERR: begin
      s_aclk <= 1'b0;
      s_axis_tvalid <= 1'b0;


      s_axis_tdata <= {`fifo_wdth{1'bx}};
      s_axis_tkeep <= {`data_wdth{1'b0}};
    end

    default: begin
      s_aclk <= Clk;
      s_axis_tvalid <= 1'b1;


      s_axis_tdata <= {`fifo_wdth{1'bx}};
      s_axis_tkeep <= {`data_wdth{1'b1}};
    end
  endcase



  case (1'b1)
    state[IDLE]: begin
      case (1'b1)
        read_request: begin
          next[RD] <= 1'b1;
        end

        write_request: begin
          next[WR] <= 1'b1;
        end

        default: begin
          next[IDLE] <= 1'b1;
        end
      endcase
    end


    state[WR]: begin
      if (SCmdAccept & MReqLast) begin
        next[IDLE] <= 1'b1;
      end

      else begin
        next[WR] <= 1'b1;
      end
    end


    state[RD]: begin
      if (SCmdAccept & MReqLast) begin
        next[IDLE] <= 1'b1;
      end

      else begin
        next[RD] <= 1'b1;
      end
    end

    default: begin
      next[IDLE] <= 1'b1;
    end
  endcase

end



always @(posedge Clk) begin

  if (reset) begin
    burst_count <= `burstlength_wdth'b0;
    base_address <= {`addr_wdth{1'b0}};
    set_burst_length <= burst_length;
    set_burst_seq <= burst_seq;

    set_valid_bytes <= valid_bytes;
    set_writeresp_enable <= writeresp_enable;





    MAddr             <= {`addr_wdth{1'bx}};
    MCmd              <= IDLE;
    MData             <= {`data_wdth{1'bx}};
    MDataValid        <= 1'bx;

    MRespAccept       <= s_axis_tready;


    MAddrSpace        <= {`addrspace_wdth{1'b1}};
    MByteEn           <= {`data_wdth{1'b1}};
    MDataByteEn       <= {`data_wdth{1'b1}};
    MDataInfo         <= 1'b0;
    MReqInfo          <= 1'b0;


    MAtomicLength     <= 1'b1;
    MBlockHeight      <= 1'b1;
    MBlockStride      <= 1'b0;
    MBurstLength      <= 1'b1;
    MBurstPrecise     <= 1'b1;
    MBurstSeq         <= INCR;
    MBurstSingleSeq   <= 1'b0;
    MDataLast         <= 1'bx;
    MDataRowLast      <= 1'bx;
    MReqLast          <= 1'bx;
    MReqRowLast       <= 1'bx;


    MDataTagID        <= 1'b0;
    MTagID            <= 1'b0;
    MTagInOrder       <= 1'b0;


    MConnID           <= 1'b0;
    MDataThreadID     <= 1'b0;
    MThreadBusy       <= 1'b0;
    MThreadID         <= 1'b0;

























  end


  else begin
    MCmd <= IDLE;


    case (1'b1)

      next[IDLE]: begin
        burst_count <= `burstlength_wdth'b0;
        base_address <= address;


        set_burst_length <= burst_length;
        set_burst_seq <= burst_seq;

        set_valid_bytes <= valid_bytes;
        set_writeresp_enable <= writeresp_enable;





        MAddr             <= {`addr_wdth{1'b0}};
        MCmd              <= IDLE;
        MData             <= {`data_wdth{1'b0}};
        MDataValid        <= 1'bx;

        MRespAccept       <= s_axis_tready;


        MAddrSpace        <= {`addrspace_wdth{1'b0}};
        MByteEn           <= {`data_wdth{1'b1}};
        MDataByteEn       <= {`data_wdth{1'b1}};
        MDataInfo         <= 1'b0;
        MReqInfo          <= 1'b0;


        MAtomicLength     <= 1'b1;
        MBlockHeight      <= 1'b1;
        MBlockStride      <= 1'b0;
        MBurstLength      <= burst_length;
        MBurstPrecise     <= 1'b1;
        MBurstSeq         <= INCR;
        MBurstSingleSeq   <= 1'b0;
        MDataLast         <= 1'bx;
        MDataRowLast      <= 1'bx;
        MReqLast          <= 1'bx;
        MReqRowLast       <= 1'bx;


        MDataTagID        <= 1'b0;
        MTagID            <= 1'b0;
        MTagInOrder       <= 1'b0;


        MConnID           <= 1'b0;
        MDataThreadID     <= 1'b0;
        MThreadBusy       <= 1'b0;
        MThreadID         <= 1'b0;

























      end



      next[WR]: begin
        burst_count <= (SCmdAccept & (burst_count < burst_length)) ? burst_count + 1'b1 : burst_count;


        if (SCmdAccept) begin
          case (burst_seq)
            INCR: begin
              base_address <= base_address + (`incr_addr_offset);
            end

            DFLT1: begin

            end

            WRAP: begin

            end

            DFLT2: begin

            end

            XOR: begin

            end

            STRM: begin

            end

            UNKN: begin

            end

            BLCK: begin

            end

            default: begin
              base_address <= base_address;
            end
          endcase
        end

        else begin
          base_address <= base_address;
        end




        MAddr             <= base_address;
        MCmd              <= WR;
        MData             <= write_data;
        MDataValid        <= 1'bx;

        MRespAccept       <= s_axis_tready;


        MAddrSpace        <= {`addrspace_wdth{1'b0}};

        MByteEn           <= valid_bytes;
        MDataByteEn       <= {`data_wdth{1'b1}};
        MDataInfo         <= 1'b0;
        MReqInfo          <= 1'b0;


        MAtomicLength     <= 1'b1;
        MBlockHeight      <= 1'b1;

        MBlockStride      <= 1'b0;
        MBurstLength      <= set_burst_length;
        MBurstPrecise     <= 1'b1;
        MBurstSeq         <= set_burst_seq;

        MBurstSingleSeq   <= 1'b0;
        MDataLast         <= 1'bx;
        MDataRowLast      <= 1'bx;

        MReqLast          <= (burst_count == (set_burst_length - 1'b1)) | set_burst_single_req;
        MReqRowLast       <= 1'bx;


        MDataTagID        <= 1'b0;
        MTagID            <= 1'b0;
        MTagInOrder       <= 1'b0;


        MConnID           <= 1'b0;
        MDataThreadID     <= 1'b0;
        MThreadBusy       <= 1'b0;
        MThreadID         <= 1'b0;

























      end



      next[RD]: begin
        burst_count <= (SCmdAccept & (burst_count < burst_length)) ? burst_count + 1'b1 : burst_count;


        if (SCmdAccept) begin
          case (burst_seq)
            INCR: begin
              base_address <= base_address + (`incr_addr_offset);
            end

            DFLT1: begin

            end

            WRAP: begin

            end

            DFLT2: begin

            end

            XOR: begin

            end

            STRM: begin

            end

            UNKN: begin

            end

            BLCK: begin

            end

            default: begin
              base_address <= base_address;
            end
          endcase
        end

        else begin
          base_address <= base_address;
        end




        MAddr             <= base_address;
        MCmd              <= RD;
        MData             <= {`data_wdth{1'b0}};
        MDataValid        <= 1'bx;

        MRespAccept       <= s_axis_tready;


        MAddrSpace        <= {`addrspace_wdth{1'b0}};

        MByteEn           <= set_valid_bytes;
        MDataByteEn       <= write_request ? set_valid_bytes : {`data_wdth{1'b1}};
        MDataInfo         <= 1'b0;
        MReqInfo          <= 1'b0;


        MAtomicLength     <= 1'b1;
        MBlockHeight      <= 1'b1;

        MBlockStride      <= 1'b0;

        MBurstLength      <= set_burst_length;
        MBurstPrecise     <= 1'b1;
        MBurstSeq         <= set_burst_seq;

        MBurstSingleSeq   <= 1'b0;
        MDataLast         <= 1'bx;
        MDataRowLast      <= 1'bx;
        MReqLast          <= (burst_count == (set_burst_length - 1'b1)) | set_burst_single_req;
        MReqRowLast       <= 1'bx;


        MDataTagID        <= 1'b0;
        MTagID            <= 1'b0;
        MTagInOrder       <= 1'b0;


        MConnID           <= 1'b0;
        MDataThreadID     <= 1'b0;
        MThreadBusy       <= 1'b0;
        MThreadID         <= 1'b0;

























      end



      default: begin
        burst_count <= `burstlength_wdth'b0;
        base_address <= {`addr_wdth{1'bx}};
        set_burst_length <= burst_length;
        set_burst_seq <= burst_seq;

        set_valid_bytes <= valid_bytes;
        set_writeresp_enable <= writeresp_enable;




        MAddr             <= {`addr_wdth{1'b0}};
        MCmd              <= IDLE;
        MData             <= {`data_wdth{1'b0}};
        MDataValid        <= 1'bx;

        MRespAccept       <= s_axis_tready;


        MAddrSpace        <= {`addrspace_wdth{1'b0}};
        MByteEn           <= {`data_wdth{1'b1}};
        MDataByteEn       <= {`data_wdth{1'b1}};
        MDataInfo         <= 1'b0;
        MReqInfo          <= 1'b0;


        MAtomicLength     <= 1'b1;
        MBlockHeight      <= 1'b1;
        MBlockStride      <= 1'b0;
        MBurstLength      <= 1'b1;
        MBurstPrecise     <= 1'b1;
        MBurstSeq         <= INCR;
        MBurstSingleSeq   <= 1'b0;
        MDataLast         <= 1'bx;
        MDataRowLast      <= 1'bx;
        MReqLast          <= 1'bx;
        MReqRowLast       <= 1'bx;


        MDataTagID        <= 1'b0;
        MTagID            <= 1'b0;
        MTagInOrder       <= 1'b0;


        MConnID           <= 1'b0;
        MDataThreadID     <= 1'b0;
        MThreadBusy       <= 1'b0;
        MThreadID         <= 1'b0;

























      end

    endcase

  end
end

endmodule
module ocp_master_fsm(

  input wire [`addr_wdth - 1:0]         address,
  input wire                            enable,
  input wire [2:0]                      burst_seq,
  input wire                            burst_single_req,
  input wire [`request_length - 1:0]    burst_length,
  input wire                            data_valid,
  input wire                            read_request,
  input wire                            reset,
  input wire                            sys_clk,
  input wire [`data_wdth - 1:0]         valid_bytes,
  input wire [`data_wdth - 1:0]         write_data,
  input wire                            write_request,
  input wire                            writeresp_enable,
  output wire                           ocp_ready,


  output reg s_aclk,
  output reg s_axis_tvalid,
  input wire s_axis_tready,
  output reg [`fifo_wdth - 1:0] s_axis_tdata,
  output reg [`data_wdth - 1:0] s_axis_tkeep,
  output reg s_axis_tlast,
  input wire axis_overflow,



  

  output wire                           Clk,
  inout wire                            EnableClk,
  output reg [`addr_wdth - 1:0]         MAddr,
  output reg [2:0]                      MCmd,
  output reg [`data_wdth - 1:0]         MData,
  output reg                            MDataValid,
  output reg                            MRespAccept,
  input wire                            SCmdAccept,
  input wire [`data_wdth - 1:0]         SData,
  input wire                            SDataAccept,
  input wire [1:0]                      SResp,


  output reg [`addrspace_wdth - 1:0]    MAddrSpace,
  output reg [`data_wdth - 1:0]         MByteEn,
  output reg [`data_wdth - 1:0]         MDataByteEn,
  output reg [`mdatainfo_wdth - 1:0]    MDataInfo,
  output reg [`reqinfo_wdth - 1:0]      MReqInfo,
  input wire [`sdatainfo_wdth - 1:0]    SDataInfo,
  input wire [`respinfo_wdth - 1:0]     SRespInfo,


  output reg [`atomiclength_wdth - 1:0] MAtomicLength,
  output reg [`blockheight_wdth - 1:0]  MBlockHeight,
  output reg [`blockstride_wdth - 1:0]  MBlockStride,
  output reg [`burstlength_wdth - 1:0]  MBurstLength,
  output reg                            MBurstPrecise,
  output reg [2:0]                      MBurstSeq,
  output reg                            MBurstSingleSeq,
  output reg                            MDataLast,
  output reg                            MDataRowLast,
  output reg                            MReqLast,
  output reg                            MReqRowLast,
  input wire                            SRespLast,
  input wire                            SRespRowLast,


  output reg [`tags - 1:0]              MDataTagID,
  output reg [`tags - 1:0]              MTagID,
  output reg                            MTagInOrder,
  input wire [`tags - 1:0]              STagID,
  input wire                            STagInOrder,
  

  output reg [`connid_width - 1:0]      MConnID,
  output reg [`threads - 1:0]           MDataThreadID,
  output reg [`threads - 1:0]           MThreadBusy,
  output reg [`threads - 1:0]           MThreadID,
  input wire [`threads - 1:0]           SDataThreadBusy,
  input wire [`threads - 1:0]           SThreadBusy,
  input wire [`threads - 1:0]           SThreadID
  


















  












);







localparam IDLE  = 3'b000;
localparam WR    = 3'b001;
localparam RD    = 3'b010;
localparam RDEX  = 3'b011;
localparam RDL   = 3'b100;
localparam WRNP  = 3'b101;
localparam WRC   = 3'b110;
localparam BCST  = 3'b111;


localparam NULL  = 2'b00;
localparam DVA   = 2'b01;
localparam FAIL  = 2'b10;
localparam ERR   = 2'b11;


localparam INCR  = 3'b000;
localparam DFLT1 = 3'b001;
localparam WRAP  = 3'b010;
localparam DFLT2 = 3'b011;
localparam XOR   = 3'b100;
localparam STRM  = 3'b101;
localparam UNKN  = 3'b110;
localparam BLCK  = 3'b111;
























reg [3:0]                     state;
reg [3:0]                     next;


reg [`request_length - 1:0]   burst_count;
reg [`addr_wdth - 1:0]        base_address;
reg [`request_length - 1:0]   set_burst_length;
reg [2:0]                     set_burst_seq;
reg                           set_burst_single_req;
reg [`data_wdth - 1:0]        set_valid_bytes;
reg                           set_writeresp_enable;

assign EnableClk = enable;
assign Clk = sys_clk & enable;
assign ocp_ready = SCmdAccept;



always @(posedge Clk) begin
  if (EnableClk) begin
    if (reset) begin
      state <= 3'b0;
      state[IDLE] <= 1'b1;
    end

    else begin
      state <= next;
    end
  end

  else begin
    state <= state;
  end
end




always @(*) begin
  next <= 3'b0;


  case (SResp)

    NULL: begin
      s_aclk <= Clk;
      s_axis_tvalid <= 1'b1;
      

      s_axis_tdata <= {`fifo_wdth{1'bx}};
      s_axis_tkeep <= {`data_wdth{1'b0}};
    end


    DVA: begin
      s_aclk <= Clk;
      s_axis_tvalid <= 1'b1;
      

      if (s_axis_tready) begin
        s_axis_tdata <= SData;
        s_axis_tkeep <= {`data_wdth{1'b1}};
      end

      else begin
        s_axis_tdata <= {`fifo_wdth{1'bx}};
        s_axis_tkeep <= {`data_wdth{1'b0}};
      end
    end


    FAIL: begin
      s_aclk <= Clk;
      s_axis_tvalid <= 1'b1;


      if (s_axis_tready) begin
        s_axis_tdata <= SData;
        s_axis_tkeep <= {`data_wdth{1'b1}};
      end

      else begin
        s_axis_tdata <= {`fifo_wdth{1'bx}};
        s_axis_tkeep <= {`data_wdth{1'b0}};
      end
    end


    ERR: begin
      s_aclk <= 1'b0;
      s_axis_tvalid <= 1'b0;


      s_axis_tdata <= {`fifo_wdth{1'bx}};
      s_axis_tkeep <= {`data_wdth{1'b0}};
    end

    default: begin
      s_aclk <= Clk;
      s_axis_tvalid <= 1'b1;


      s_axis_tdata <= {`fifo_wdth{1'bx}};
      s_axis_tkeep <= {`data_wdth{1'b1}};
    end
  endcase



  case (1'b1)
    state[IDLE]: begin
      case (1'b1)
        read_request: begin
          next[RD] <= 1'b1;
        end

        write_request: begin
          next[WR] <= 1'b1;
        end

        default: begin
          next[IDLE] <= 1'b1;
        end
      endcase
    end


    state[WR]: begin
      if (SCmdAccept & MReqLast) begin
        next[IDLE] <= 1'b1;
      end

      else begin
        next[WR] <= 1'b1;
      end
    end


    state[RD]: begin
      if (SCmdAccept & MReqLast) begin
        next[IDLE] <= 1'b1;
      end

      else begin
        next[RD] <= 1'b1;
      end
    end

    default: begin
      next[IDLE] <= 1'b1;
    end
  endcase

end



always @(posedge Clk) begin

  if (reset) begin
    burst_count <= `burstlength_wdth'b0;
    base_address <= {`addr_wdth{1'b0}};
    set_burst_length <= burst_length;
    set_burst_seq <= burst_seq;

    set_valid_bytes <= valid_bytes;
    set_writeresp_enable <= writeresp_enable;





    MAddr             <= {`addr_wdth{1'bx}};
    MCmd              <= IDLE;
    MData             <= {`data_wdth{1'bx}};
    MDataValid        <= 1'bx;

    MRespAccept       <= s_axis_tready;


    MAddrSpace        <= {`addrspace_wdth{1'b1}};
    MByteEn           <= {`data_wdth{1'b1}};
    MDataByteEn       <= {`data_wdth{1'b1}};
    MDataInfo         <= 1'b0;
    MReqInfo          <= 1'b0;


    MAtomicLength     <= 1'b1;
    MBlockHeight      <= 1'b1;
    MBlockStride      <= 1'b0;
    MBurstLength      <= 1'b1;
    MBurstPrecise     <= 1'b1;
    MBurstSeq         <= INCR;
    MBurstSingleSeq   <= 1'b0;
    MDataLast         <= 1'bx;
    MDataRowLast      <= 1'bx;
    MReqLast          <= 1'bx;
    MReqRowLast       <= 1'bx;


    MDataTagID        <= 1'b0;
    MTagID            <= 1'b0;
    MTagInOrder       <= 1'b0;


    MConnID           <= 1'b0;
    MDataThreadID     <= 1'b0;
    MThreadBusy       <= 1'b0;
    MThreadID         <= 1'b0;

























  end


  else begin
    MCmd <= IDLE;


    case (1'b1)

      next[IDLE]: begin
        burst_count <= `burstlength_wdth'b0;
        base_address <= address;


        set_burst_length <= burst_length;
        set_burst_seq <= burst_seq;

        set_valid_bytes <= valid_bytes;
        set_writeresp_enable <= writeresp_enable;





        MAddr             <= {`addr_wdth{1'b0}};
        MCmd              <= IDLE;
        MData             <= {`data_wdth{1'b0}};
        MDataValid        <= 1'bx;

        MRespAccept       <= s_axis_tready;


        MAddrSpace        <= {`addrspace_wdth{1'b0}};
        MByteEn           <= {`data_wdth{1'b1}};
        MDataByteEn       <= {`data_wdth{1'b1}};
        MDataInfo         <= 1'b0;
        MReqInfo          <= 1'b0;


        MAtomicLength     <= 1'b1;
        MBlockHeight      <= 1'b1;
        MBlockStride      <= 1'b0;
        MBurstLength      <= burst_length;
        MBurstPrecise     <= 1'b1;
        MBurstSeq         <= INCR;
        MBurstSingleSeq   <= 1'b0;
        MDataLast         <= 1'bx;
        MDataRowLast      <= 1'bx;
        MReqLast          <= 1'bx;
        MReqRowLast       <= 1'bx;


        MDataTagID        <= 1'b0;
        MTagID            <= 1'b0;
        MTagInOrder       <= 1'b0;


        MConnID           <= 1'b0;
        MDataThreadID     <= 1'b0;
        MThreadBusy       <= 1'b0;
        MThreadID         <= 1'b0;

























      end



      next[WR]: begin
        burst_count <= (SCmdAccept & (burst_count < burst_length)) ? burst_count + 1'b1 : burst_count;


        if (SCmdAccept) begin
          case (burst_seq)
            INCR: begin
              base_address <= base_address + (`incr_addr_offset);
            end

            DFLT1: begin

            end

            WRAP: begin

            end

            DFLT2: begin

            end

            XOR: begin

            end

            STRM: begin

            end

            UNKN: begin

            end

            BLCK: begin

            end

            default: begin
              base_address <= base_address;
            end
          endcase
        end

        else begin
          base_address <= base_address;
        end




        MAddr             <= base_address;
        MCmd              <= WR;
        MData             <= write_data;
        MDataValid        <= 1'bx;

        MRespAccept       <= s_axis_tready;


        MAddrSpace        <= {`addrspace_wdth{1'b0}};

        MByteEn           <= valid_bytes;
        MDataByteEn       <= {`data_wdth{1'b1}};
        MDataInfo         <= 1'b0;
        MReqInfo          <= 1'b0;


        MAtomicLength     <= 1'b1;
        MBlockHeight      <= 1'b1;

        MBlockStride      <= 1'b0;
        MBurstLength      <= set_burst_length;
        MBurstPrecise     <= 1'b1;
        MBurstSeq         <= set_burst_seq;

        MBurstSingleSeq   <= 1'b0;
        MDataLast         <= 1'bx;
        MDataRowLast      <= 1'bx;

        MReqLast          <= (burst_count == (set_burst_length - 1'b1)) | set_burst_single_req;
        MReqRowLast       <= 1'bx;


        MDataTagID        <= 1'b0;
        MTagID            <= 1'b0;
        MTagInOrder       <= 1'b0;


        MConnID           <= 1'b0;
        MDataThreadID     <= 1'b0;
        MThreadBusy       <= 1'b0;
        MThreadID         <= 1'b0;

























      end



      next[RD]: begin
        burst_count <= (SCmdAccept & (burst_count < burst_length)) ? burst_count + 1'b1 : burst_count;


        if (SCmdAccept) begin
          case (burst_seq)
            INCR: begin
              base_address <= base_address + (`incr_addr_offset);
            end

            DFLT1: begin

            end

            WRAP: begin

            end

            DFLT2: begin

            end

            XOR: begin

            end

            STRM: begin

            end

            UNKN: begin

            end

            BLCK: begin

            end

            default: begin
              base_address <= base_address;
            end
          endcase
        end

        else begin
          base_address <= base_address;
        end




        MAddr             <= base_address;
        MCmd              <= RD;
        MData             <= {`data_wdth{1'b0}};
        MDataValid        <= 1'bx;

        MRespAccept       <= s_axis_tready;


        MAddrSpace        <= {`addrspace_wdth{1'b0}};

        MByteEn           <= set_valid_bytes;
        MDataByteEn       <= write_request ? set_valid_bytes : {`data_wdth{1'b1}};
        MDataInfo         <= 1'b0;
        MReqInfo          <= 1'b0;


        MAtomicLength     <= 1'b1;
        MBlockHeight      <= 1'b1;

        MBlockStride      <= 1'b0;

        MBurstLength      <= set_burst_length;
        MBurstPrecise     <= 1'b1;
        MBurstSeq         <= set_burst_seq;

        MBurstSingleSeq   <= 1'b0;
        MDataLast         <= 1'bx;
        MDataRowLast      <= 1'bx;
        MReqLast          <= (burst_count == (set_burst_length - 1'b1)) | set_burst_single_req;
        MReqRowLast       <= 1'bx;


        MDataTagID        <= 1'b0;
        MTagID            <= 1'b0;
        MTagInOrder       <= 1'b0;


        MConnID           <= 1'b0;
        MDataThreadID     <= 1'b0;
        MThreadBusy       <= 1'b0;
        MThreadID         <= 1'b0;

























      end



      default: begin
        burst_count <= `burstlength_wdth'b0;
        base_address <= {`addr_wdth{1'bx}};
        set_burst_length <= burst_length;
        set_burst_seq <= burst_seq;

        set_valid_bytes <= valid_bytes;
        set_writeresp_enable <= writeresp_enable;




        MAddr             <= {`addr_wdth{1'b0}};
        MCmd              <= IDLE;
        MData             <= {`data_wdth{1'b0}};
        MDataValid        <= 1'bx;

        MRespAccept       <= s_axis_tready;


        MAddrSpace        <= {`addrspace_wdth{1'b0}};
        MByteEn           <= {`data_wdth{1'b1}};
        MDataByteEn       <= {`data_wdth{1'b1}};
        MDataInfo         <= 1'b0;
        MReqInfo          <= 1'b0;


        MAtomicLength     <= 1'b1;
        MBlockHeight      <= 1'b1;
        MBlockStride      <= 1'b0;
        MBurstLength      <= 1'b1;
        MBurstPrecise     <= 1'b1;
        MBurstSeq         <= INCR;
        MBurstSingleSeq   <= 1'b0;
        MDataLast         <= 1'bx;
        MDataRowLast      <= 1'bx;
        MReqLast          <= 1'bx;
        MReqRowLast       <= 1'bx;


        MDataTagID        <= 1'b0;
        MTagID            <= 1'b0;
        MTagInOrder       <= 1'b0;


        MConnID           <= 1'b0;
        MDataThreadID     <= 1'b0;
        MThreadBusy       <= 1'b0;
        MThreadID         <= 1'b0;

























      end

    endcase

  end
end

endmodule