data/full_repos/permissive/115035459/verilog/src/example002.v
 line:23: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #41.7 CLK = ~CLK;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/115035459/verilog/src/example002.v:23: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("work/example002.vcd");\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #0\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/example002.v:24: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/example002.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #100000 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top #(parameter LOG2DELAY=20) (input CLK, output LED1, output LED2, output LED3, output LED4, output LED5);
	localparam BITS = 5;
	reg [BITS+LOG2DELAY-1:0] counter = 0;
	reg [BITS-1:0] outcnt = 0;
	always @(posedge CLK) begin
		counter <= counter + 1;
		outcnt <= counter >> LOG2DELAY;
	end
	assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
endmodule
module top #(parameter LOG2DELAY=20) (input CLK, output LED1, output LED2, output LED3, output LED4, output LED5);

	localparam BITS = 5;
	reg [BITS+LOG2DELAY-1:0] counter = 0;
	reg [BITS-1:0] outcnt = 0;
	always @(posedge CLK) begin
		counter <= counter + 1;
		outcnt <= counter >> LOG2DELAY;
	end
	assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
endmodule