data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v
None: at end of input
1: b'%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:2: Cannot find include file: modulos/ternarioDoble.v\n  `include "modulos/ternarioDoble.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v.v\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v.sv\n             modulos/ternarioDoble.v\n             modulos/ternarioDoble.v.v\n             modulos/ternarioDoble.v.sv\n             obj_dir/modulos/ternarioDoble.v\n             obj_dir/modulos/ternarioDoble.v.v\n             obj_dir/modulos/ternarioDoble.v.sv\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:5: Cannot find include file: ../tarea3/modulos/mux.v\n  `include "../tarea3/modulos/mux.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:8: Cannot find include file: ../tarea3/modulos/norGate.v\n  `include "../tarea3/modulos/norGate.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:11: Cannot find include file: modulos/salidaSerial.v\n  `include "modulos/salidaSerial.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:14: Cannot find include file: modulos/serialOcontiguo.v\n  `include "modulos/serialOcontiguo.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:151: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:157: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:163: Unsupported: Ignoring delay on this delayed statement.\n  #retardos\n  ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:175: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./tests/testsalidaSerial.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:176: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:181: Unsupported or unknown PLI call: $monitor\n    $monitor ("%t| %b | %b | %b | %b  | %f ns",\n    ^~~~~~~~\n%Error: Exiting due to 8 error(s), 21 warning(s)\n'
module testsalidaSerial ();

  reg s_der, s_izq, dir;
  reg [1:0] modo;
  wire outAnd;


  wire s_out;


  salidaSerial tester(
    .modo(modo),
    .s_der(s_der),
    .s_izq(s_izq),
    .dir(dir),
    .s_out(s_out)
  );

  parameter retardos = 25;


  initial begin


  #retardos
  modo = 2'b00;
  s_der = 0;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 0;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 0;
  s_izq = 0;
  dir = 1;

  #retardos
  modo = 2'b10;
  s_der = 0;
  s_izq = 0;
  dir = 1;

  #retardos
  modo = 2'b10;
  s_der = 0;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b10;
  s_der = 0;
  s_izq = 1;
  dir = 0;

  #retardos
  modo = 2'b01;
  s_der = 1;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b01;
  s_der = 0;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b10;
  s_der = 0;
  s_izq = 1;
  dir = 0;

  #retardos
  modo = 2'b10;
  s_der = 1;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 0;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 1;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 0;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 0;


  $finish;
  end

  initial begin

    $dumpfile("./tests/testsalidaSerial.vcd");
    $dumpvars;
    $display("------------------------------------");
    $display("-- Test -para modulo salidaSerial --");
    $display("------------------------------------");
    $display ("\t     tiempo | s_der | s_izq | dir | dir | s_out | tiempo");
    $monitor ("%t| %b | %b | %b | %b  | %f ns",
              $time, s_der, s_izq, dir, s_out, $realtime);

  

	end
endmodule
module testsalidaSerial ();


  reg s_der, s_izq, dir;
  reg [1:0] modo;
  wire outAnd;


  wire s_out;


  salidaSerial tester(
    .modo(modo),
    .s_der(s_der),
    .s_izq(s_izq),
    .dir(dir),
    .s_out(s_out)
  );

  parameter retardos = 25;


  initial begin


  #retardos
  modo = 2'b00;
  s_der = 0;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 0;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 0;
  s_izq = 0;
  dir = 1;

  #retardos
  modo = 2'b10;
  s_der = 0;
  s_izq = 0;
  dir = 1;

  #retardos
  modo = 2'b10;
  s_der = 0;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b10;
  s_der = 0;
  s_izq = 1;
  dir = 0;

  #retardos
  modo = 2'b01;
  s_der = 1;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b01;
  s_der = 0;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b10;
  s_der = 0;
  s_izq = 1;
  dir = 0;

  #retardos
  modo = 2'b10;
  s_der = 1;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 0;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 1;
  dir = 0;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 0;
  s_izq = 1;
  dir = 1;

  #retardos
  modo = 2'b00;
  s_der = 1;
  s_izq = 0;
  dir = 0;


  $finish;
  end

  initial begin

    $dumpfile("./tests/testsalidaSerial.vcd");
    $dumpvars;
    $display("------------------------------------");
    $display("-- Test -para modulo salidaSerial --");
    $display("------------------------------------");
    $display ("\t     tiempo | s_der | s_izq | dir | dir | s_out | tiempo");
    $monitor ("%t| %b | %b | %b | %b  | %f ns",
              $time, s_der, s_izq, dir, s_out, $realtime);

  

	end
endmodule