data/full_repos/permissive/2084115/rtl/rtos/jelly2_rtos_eventflag.sv
None: at end of input
data/verilator_xmls/3086e59f-e5be-435d-8a7f-a114d27b9a47.xml
module jelly2_rtos_eventflag
        #(
            parameter   int                                         TMAX_FLGID   = 1,
            parameter   int                                         FLGPTN_WIDTH = 32,
            parameter   bit     [TMAX_FLGID:1][FLGPTN_WIDTH-1:0]    INIT_FLGPTN  = '0
        )
        (
            input   wire                                        reset,
            input   wire                                        clk,
            input   wire                                        cke,

            output  reg     [TMAX_FLGID:1][FLGPTN_WIDTH-1:0]    flgptn,

            input   wire    [TMAX_FLGID:1][FLGPTN_WIDTH-1:0]    set_flg,
            input   wire    [TMAX_FLGID:1][FLGPTN_WIDTH-1:0]    clr_flg
        );

    always_ff @(posedge clk) begin
        if ( reset ) begin
            flgptn <= INIT_FLGPTN;
        end
        else if ( cke ) begin
            flgptn <= ((flgptn & clr_flg) | set_flg);
        end
    end
    
endmodule
module jelly2_rtos_eventflag
        #(
            parameter   int                                         TMAX_FLGID   = 1,
            parameter   int                                         FLGPTN_WIDTH = 32,
            parameter   bit     [TMAX_FLGID:1][FLGPTN_WIDTH-1:0]    INIT_FLGPTN  = '0
        )
        (
            input   wire                                        reset,
            input   wire                                        clk,
            input   wire                                        cke,

            output  reg     [TMAX_FLGID:1][FLGPTN_WIDTH-1:0]    flgptn,

            input   wire    [TMAX_FLGID:1][FLGPTN_WIDTH-1:0]    set_flg,
            input   wire    [TMAX_FLGID:1][FLGPTN_WIDTH-1:0]    clr_flg
        );


    always_ff @(posedge clk) begin
        if ( reset ) begin
            flgptn <= INIT_FLGPTN;
        end
        else if ( cke ) begin
            flgptn <= ((flgptn & clr_flg) | set_flg);
        end
    end
    
endmodule