data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:90: Signal definition not found, creating implicitly: \'ALUSrc1\'\n  .Operand1( (ALUSrc1) ? PC : RF_RD1),     \n              ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:91: Signal definition not found, creating implicitly: \'ALUSrc2\'\n                                                                                                : ... Suggested alternative: \'ALUSrc1\'\n  .Operand2( (ALUSrc2) ? offset : RF_RD2 ), \n              ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:93: Signal definition not found, creating implicitly: \'Zero\'\n  .Zero(Zero),     \n        ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:102: Signal definition not found, creating implicitly: \'Branch\'\n assign Branch_Taken = Branch & Zero;\n                       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:103: Signal definition not found, creating implicitly: \'Jump\'\n assign NXT_PC = (~RSTn)? 0 : (Jump)? ( (JALorJALR)? JALR_Address : JAL_Address ) : ((Branch_Taken)? Branch_Target : PC+4 );\n                               ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:103: Signal definition not found, creating implicitly: \'JALorJALR\'\n assign NXT_PC = (~RSTn)? 0 : (Jump)? ( (JALorJALR)? JALR_Address : JAL_Address ) : ((Branch_Taken)? Branch_Target : PC+4 );\n                                         ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:119: Signal definition not found, creating implicitly: \'MemWrite\'\n assign D_MEM_WEN = ~MemWrite;\n                     ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:123: Signal definition not found, creating implicitly: \'RegWrite\'\n                                                                                                 : ... Suggested alternative: \'MemWrite\'\n assign RF_WE = RegWrite;\n                ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:126: Signal definition not found, creating implicitly: \'RegDst\'\n assign RF_WA1 = (RegDst) ? I_MEM_DI[11:7] : I_MEM_DI[24:20];\n                  ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:127: Signal definition not found, creating implicitly: \'MemtoReg\'\n assign RF_WD = (Jump) ? PC+4 : (MemtoReg) ? D_MEM_DI : ALU_Result;\n                                 ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:266: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (Operand1 == Operand2); \n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:270: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s NEQ generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (Operand1 != Operand2); \n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:277: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (signed_Operand1 < signed_Operand2);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:284: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s GTES generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (signed_Operand1 >= signed_Operand2);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:288: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (Operand1 < Operand2);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:292: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s GTE generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (Operand1 >= Operand2);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:299: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (signed_Operand1 < signed_Operand2);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:303: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP.alu\n    ALU_Result = (Operand1 < Operand2);\n               ^\n%Error: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:46: Cannot find file containing module: \'Control\'\n Control control(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab,data/full_repos/permissive/149079484/Control\n             data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab,data/full_repos/permissive/149079484/Control.v\n             data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab,data/full_repos/permissive/149079484/Control.sv\n             Control\n             Control.v\n             Control.sv\n             obj_dir/Control\n             obj_dir/Control.v\n             obj_dir/Control.sv\n%Error: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:65: Cannot find file containing module: \'ALUControl\'\n ALUControl alucontrol(\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_SingleCycleCPU-lab/RISCV_TOP.v:133: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Branch_Taken\' generates 1 bits.\n                                                                                              : ... In instance RISCV_TOP\n assign OUTPUT_PORT = (Branch) ? Branch_Taken : (MemWrite)? ALU_Result : RF_WD;\n                               ^\n%Error: Exiting due to 2 error(s), 19 warning(s)\n'
module ALU(
	input wire [31:0] Operand1,
	input wire [31:0] Operand2,
	input wire [4:0] ALU_operation,
	output reg Zero,
	output reg [31:0] ALU_Result
	);
	
	reg signed [31:0] signed_Operand1;
	reg signed [31:0] signed_Operand2;
	always@(*) begin
		case(ALU_operation)
			5'b00000: begin
				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = signed_Operand1 + signed_Operand2; 
				Zero = 1'b0;
			end
			5'b00001: begin
				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = signed_Operand1 - signed_Operand2; 
				Zero = 1'b0;
			end
			5'b00010: begin
				ALU_Result = Operand1 & Operand2; 
				Zero = 1'b0;
			end
			5'b00011: begin
				ALU_Result = Operand1 | Operand2; 
				Zero = 1'b0;
			end
			5'b00100: begin
				ALU_Result = ~(Operand1 & Operand2); 
				Zero = 1'b0;
			end
			5'b00101: begin 
				ALU_Result = ~(Operand1 | Operand2); 
				Zero = 1'b0;
			end
			5'b00110: begin 
				ALU_Result = Operand1 ^ Operand2; 
				Zero = 1'b0;
			end
			5'b00111: begin
				ALU_Result = Operand1 ~^ Operand2; 
				Zero = 1'b0;
			end
			5'b01000: begin
				ALU_Result = Operand2; 
				Zero = 1'b0;
			end
			5'b01001: begin
				ALU_Result = ~Operand2; 
				Zero = 1'b0;
			end
			5'b01010: begin
				ALU_Result = Operand1>>Operand2; 
				Zero = 1'b0;
			end
			5'b01011: begin
				signed_Operand1 = Operand1; 
				ALU_Result = signed_Operand1>>>Operand2; 
				Zero = 1'b0;
			end

			5'b01100: begin
				ALU_Result = Operand1 + Operand2; 
				Zero = 1'b0;
			end

			5'b01101: begin
				ALU_Result = Operand1<<Operand2; 
				Zero = 1'b0;
			end
			5'b01110: begin 
				ALU_Result = Operand1<<<Operand2; 
				Zero = 1'b0;
			end
		
			5'b01111: begin
				ALU_Result = Operand1 - Operand2; 
				Zero = 1'b0;
			end

			5'b10000: begin
				ALU_Result = (Operand1 == Operand2); 
				Zero = (Operand1 == Operand2);
			end
			5'b10001: begin
				ALU_Result = (Operand1 != Operand2); 
				Zero = (Operand1 != Operand2);
			end
			5'b10010: begin

				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = (signed_Operand1 < signed_Operand2);
				Zero = (signed_Operand1 < signed_Operand2);
			end
			5'b10011: begin

				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = (signed_Operand1 >= signed_Operand2);
				Zero = (signed_Operand1 >= signed_Operand2);
			end
			5'b10100: begin
				ALU_Result = (Operand1 < Operand2);
				Zero = (Operand1 < Operand2);
			end
			5'b10101: begin
				ALU_Result = (Operand1 >= Operand2);
				Zero = (Operand1 >= Operand2);
			end

			5'b10110:begin
				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = (signed_Operand1 < signed_Operand2);
				Zero = 0; 
			end
			5'b10111: begin
				ALU_Result = (Operand1 < Operand2);
				Zero = 0;
			end
			default: begin
				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = signed_Operand1 + signed_Operand2; 
				Zero = 1'b0;
			end
		endcase

	end
	

endmodule
module ALU(
	input wire [31:0] Operand1,
	input wire [31:0] Operand2,
	input wire [4:0] ALU_operation,
	output reg Zero,
	output reg [31:0] ALU_Result
	);

	
	reg signed [31:0] signed_Operand1;
	reg signed [31:0] signed_Operand2;
	always@(*) begin
		case(ALU_operation)
			5'b00000: begin
				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = signed_Operand1 + signed_Operand2; 
				Zero = 1'b0;
			end
			5'b00001: begin
				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = signed_Operand1 - signed_Operand2; 
				Zero = 1'b0;
			end
			5'b00010: begin
				ALU_Result = Operand1 & Operand2; 
				Zero = 1'b0;
			end
			5'b00011: begin
				ALU_Result = Operand1 | Operand2; 
				Zero = 1'b0;
			end
			5'b00100: begin
				ALU_Result = ~(Operand1 & Operand2); 
				Zero = 1'b0;
			end
			5'b00101: begin 
				ALU_Result = ~(Operand1 | Operand2); 
				Zero = 1'b0;
			end
			5'b00110: begin 
				ALU_Result = Operand1 ^ Operand2; 
				Zero = 1'b0;
			end
			5'b00111: begin
				ALU_Result = Operand1 ~^ Operand2; 
				Zero = 1'b0;
			end
			5'b01000: begin
				ALU_Result = Operand2; 
				Zero = 1'b0;
			end
			5'b01001: begin
				ALU_Result = ~Operand2; 
				Zero = 1'b0;
			end
			5'b01010: begin
				ALU_Result = Operand1>>Operand2; 
				Zero = 1'b0;
			end
			5'b01011: begin
				signed_Operand1 = Operand1; 
				ALU_Result = signed_Operand1>>>Operand2; 
				Zero = 1'b0;
			end

			5'b01100: begin
				ALU_Result = Operand1 + Operand2; 
				Zero = 1'b0;
			end

			5'b01101: begin
				ALU_Result = Operand1<<Operand2; 
				Zero = 1'b0;
			end
			5'b01110: begin 
				ALU_Result = Operand1<<<Operand2; 
				Zero = 1'b0;
			end
		
			5'b01111: begin
				ALU_Result = Operand1 - Operand2; 
				Zero = 1'b0;
			end

			5'b10000: begin
				ALU_Result = (Operand1 == Operand2); 
				Zero = (Operand1 == Operand2);
			end
			5'b10001: begin
				ALU_Result = (Operand1 != Operand2); 
				Zero = (Operand1 != Operand2);
			end
			5'b10010: begin

				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = (signed_Operand1 < signed_Operand2);
				Zero = (signed_Operand1 < signed_Operand2);
			end
			5'b10011: begin

				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = (signed_Operand1 >= signed_Operand2);
				Zero = (signed_Operand1 >= signed_Operand2);
			end
			5'b10100: begin
				ALU_Result = (Operand1 < Operand2);
				Zero = (Operand1 < Operand2);
			end
			5'b10101: begin
				ALU_Result = (Operand1 >= Operand2);
				Zero = (Operand1 >= Operand2);
			end

			5'b10110:begin
				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = (signed_Operand1 < signed_Operand2);
				Zero = 0; 
			end
			5'b10111: begin
				ALU_Result = (Operand1 < Operand2);
				Zero = 0;
			end
			default: begin
				signed_Operand1 = Operand1; 
				signed_Operand2 = Operand2; 
				ALU_Result = signed_Operand1 + signed_Operand2; 
				Zero = 1'b0;
			end
		endcase

	end
	

endmodule