data/full_repos/permissive/143278/ivltests/udp_bx.v
 line:1: before: "primitive"
1: b'%Error: data/full_repos/permissive/143278/ivltests/udp_bx.v:28: Unsupported or unknown PLI call: $monitor\n $monitor ($time,, "CL = %b, D = %b, Q = %b", CL, D, Q);\n ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/udp_bx.v:28: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n $monitor ($time,, "CL = %b, D = %b, Q = %b", CL, D, Q);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_bx.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_bx.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_bx.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_bx.v:38: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/143278/ivltests/udp_bx.v:40: syntax error, unexpected \'@\'\n repeat (3) @(negedge CK);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_bx.v:43: Unsupported: Ignoring delay on this delayed statement.\n    always #10 CK = !CK;\n           ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
    reg CL, D, CK, foo;
    wire Q;

    initial begin
	$monitor ($time,, "CL = %b, D = %b, Q = %b", CL, D, Q);
	CL = 1'b0;
	D = 1'b1;
	CK = 1'b0;
	#10;
	CL = 1'bx;
	#10;
	CL = 1'b0;
	#10;
	CL = 1'bx;
	#10;
	CL = 1'b1;
	repeat (3) @(negedge CK);
	$finish(0);
    end
    always #10 CK = !CK;

    flop ff (Q, CK, D, CL);

endmodule
module test;

    reg CL, D, CK, foo;
    wire Q;

    initial begin
	$monitor ($time,, "CL = %b, D = %b, Q = %b", CL, D, Q);
	CL = 1'b0;
	D = 1'b1;
	CK = 1'b0;
	#10;
	CL = 1'bx;
	#10;
	CL = 1'b0;
	#10;
	CL = 1'bx;
	#10;
	CL = 1'b1;
	repeat (3) @(negedge CK);
	$finish(0);
    end
    always #10 CK = !CK;

    flop ff (Q, CK, D, CL);

endmodule