data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v
1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:23: Duplicate declaration of module: \'top_module\'\nmodule top_module ( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:2: ... Location of original declaration\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:59: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:2: ... Location of original declaration\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:84: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:2: ... Location of original declaration\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:134: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:2: ... Location of original declaration\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:167: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:2: ... Location of original declaration\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n%Warning-MULTITOP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:112: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                            : ... Top module \'top_module\'\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n                                                                                            : ... Top module \'my_add16\'\nmodule my_add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );\n       ^~~~~~~~\n%Error: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:4: Cannot find file containing module: \'my_dff\'\n    my_dff U1(\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/148324174/HDLBits/VerilogLanguage,data/full_repos/permissive/148324174/my_dff\n             data/full_repos/permissive/148324174/HDLBits/VerilogLanguage,data/full_repos/permissive/148324174/my_dff.v\n             data/full_repos/permissive/148324174/HDLBits/VerilogLanguage,data/full_repos/permissive/148324174/my_dff.sv\n             my_dff\n             my_dff.v\n             my_dff.sv\n             obj_dir/my_dff\n             obj_dir/my_dff.v\n             obj_dir/my_dff.sv\n%Error: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:9: Cannot find file containing module: \'my_dff\'\n    my_dff U2(\n    ^~~~~~\n%Error: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:14: Cannot find file containing module: \'my_dff\'\n    my_dff U3(\n    ^~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n'
module my_add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );
    wire [15:0] cout_temp;
    add1 U0 (a[0 ], b[0 ], cin,           sum[0 ], cout_temp[0 ]);
    add1 U1 (a[1 ], b[1 ], cout_temp[0 ], sum[1 ], cout_temp[1 ]);
    add1 U2 (a[2 ], b[2 ], cout_temp[1 ], sum[2 ], cout_temp[2 ]);
    add1 U3 (a[3 ], b[3 ], cout_temp[2 ], sum[3 ], cout_temp[3 ]);
    add1 U4 (a[4 ], b[4 ], cout_temp[3 ], sum[4 ], cout_temp[4 ]);
    add1 U5 (a[5 ], b[5 ], cout_temp[4 ], sum[5 ], cout_temp[5 ]);
    add1 U6 (a[6 ], b[6 ], cout_temp[5 ], sum[6 ], cout_temp[6 ]);
    add1 U7 (a[7 ], b[7 ], cout_temp[6 ], sum[7 ], cout_temp[7 ]);
    add1 U8 (a[8 ], b[8 ], cout_temp[7 ], sum[8 ], cout_temp[8 ]);
    add1 U9 (a[9 ], b[9 ], cout_temp[8 ], sum[9 ], cout_temp[9 ]);
    add1 U10(a[10], b[10], cout_temp[9 ], sum[10], cout_temp[10]);
    add1 U11(a[11], b[11], cout_temp[10], sum[11], cout_temp[11]);
    add1 U12(a[12], b[12], cout_temp[11], sum[12], cout_temp[12]);
    add1 U13(a[13], b[13], cout_temp[12], sum[13], cout_temp[13]);
    add1 U14(a[14], b[14], cout_temp[13], sum[14], cout_temp[14]);
    add1 U15(a[15], b[15], cout_temp[14], sum[15], cout_temp[15]);
    assign cout = cout_temp[15];
endmodule
module my_add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

    wire [15:0] cout_temp;
    add1 U0 (a[0 ], b[0 ], cin,           sum[0 ], cout_temp[0 ]);
    add1 U1 (a[1 ], b[1 ], cout_temp[0 ], sum[1 ], cout_temp[1 ]);
    add1 U2 (a[2 ], b[2 ], cout_temp[1 ], sum[2 ], cout_temp[2 ]);
    add1 U3 (a[3 ], b[3 ], cout_temp[2 ], sum[3 ], cout_temp[3 ]);
    add1 U4 (a[4 ], b[4 ], cout_temp[3 ], sum[4 ], cout_temp[4 ]);
    add1 U5 (a[5 ], b[5 ], cout_temp[4 ], sum[5 ], cout_temp[5 ]);
    add1 U6 (a[6 ], b[6 ], cout_temp[5 ], sum[6 ], cout_temp[6 ]);
    add1 U7 (a[7 ], b[7 ], cout_temp[6 ], sum[7 ], cout_temp[7 ]);
    add1 U8 (a[8 ], b[8 ], cout_temp[7 ], sum[8 ], cout_temp[8 ]);
    add1 U9 (a[9 ], b[9 ], cout_temp[8 ], sum[9 ], cout_temp[9 ]);
    add1 U10(a[10], b[10], cout_temp[9 ], sum[10], cout_temp[10]);
    add1 U11(a[11], b[11], cout_temp[10], sum[11], cout_temp[11]);
    add1 U12(a[12], b[12], cout_temp[11], sum[12], cout_temp[12]);
    add1 U13(a[13], b[13], cout_temp[12], sum[13], cout_temp[13]);
    add1 U14(a[14], b[14], cout_temp[13], sum[14], cout_temp[14]);
    add1 U15(a[15], b[15], cout_temp[14], sum[15], cout_temp[15]);
    assign cout = cout_temp[15];
endmodule