data/full_repos/permissive/143278/ivltests/pr2901556.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2901556.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #5 lp = -5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2901556.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1 lp = -6;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2901556.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #5 if ($signed(res) !== -7) $display("FAILED");\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2901556.v:9: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                        : ... In instance top\n  wire signed [5:0] #1 fix = base + in[5];\n                                  ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  integer lp;

  wire signed [5:0] in = lp[5:0];



  wire [5:0] #1 base = (in + (in >>> 2)) >>> 2;
  wire signed [5:0] #1 fix = base + in[5];




  wire [6:0] #1 res = in + fix;

  always @(*) $display("%0d: %d %d %d %d", $time, $signed(in), $signed(base),
                       $signed(fix), $signed(res));

  initial begin
    lp = -7;
    #5 lp = -5;
    #1 lp = -6;
    #5 if ($signed(res) !== -7) $display("FAILED");
    else $display("PASSED");
  end
endmodule
module top;

  integer lp;

  wire signed [5:0] in = lp[5:0];



  wire [5:0] #1 base = (in + (in >>> 2)) >>> 2;
  wire signed [5:0] #1 fix = base + in[5];




  wire [6:0] #1 res = in + fix;

  always @(*) $display("%0d: %d %d %d %d", $time, $signed(in), $signed(base),
                       $signed(fix), $signed(res));

  initial begin
    lp = -7;
    #5 lp = -5;
    #1 lp = -6;
    #5 if ($signed(res) !== -7) $display("FAILED");
    else $display("PASSED");
  end
endmodule