data/full_repos/permissive/131712122/rtl/verilog/vga_clkgen.v
data/verilator_xmls/36053b4e-b7ea-47d5-957e-3432729c3a34.xml
module vga_clkgen #(
  parameter HAS_DVI = 0
)
(

  input      pclk_i,
  input      rst_i,

  output reg pclk_o,

  output reg dvi_pclk_p_o,
  output reg dvi_pclk_n_o,

  output reg pclk_ena_o
);








  always @(posedge pclk_i)
    if (rst_i)
    begin
        dvi_pclk_p_o <= 1'b0;
        dvi_pclk_n_o <= 1'b0;
    end
    else
    begin
        dvi_pclk_p_o <= ~dvi_pclk_p_o;
        dvi_pclk_n_o <=  dvi_pclk_p_o;
    end

generate
  if (HAS_DVI == 1)
  begin



      always @(posedge pclk_i)
        if (rst_i) pclk_o <=  1'b0;
        else       pclk_o <= ~pclk_o;


      always @(posedge pclk_i)
        if (rst_i) pclk_ena_o <=  1'b1;
        else       pclk_ena_o <= ~pclk_ena_o;
  end
  else
  begin



      always @* pclk_o     = pclk_i;







      always @(posedge pclk_i) pclk_ena_o = 1'b1;
  end
endgenerate

endmodule
module vga_clkgen #(
  parameter HAS_DVI = 0
)
(

  input      pclk_i,
  input      rst_i,

  output reg pclk_o,

  output reg dvi_pclk_p_o,
  output reg dvi_pclk_n_o,

  output reg pclk_ena_o
);









  always @(posedge pclk_i)
    if (rst_i)
    begin
        dvi_pclk_p_o <= 1'b0;
        dvi_pclk_n_o <= 1'b0;
    end
    else
    begin
        dvi_pclk_p_o <= ~dvi_pclk_p_o;
        dvi_pclk_n_o <=  dvi_pclk_p_o;
    end

generate
  if (HAS_DVI == 1)
  begin



      always @(posedge pclk_i)
        if (rst_i) pclk_o <=  1'b0;
        else       pclk_o <= ~pclk_o;


      always @(posedge pclk_i)
        if (rst_i) pclk_ena_o <=  1'b1;
        else       pclk_ena_o <= ~pclk_ena_o;
  end
  else
  begin



      always @* pclk_o     = pclk_i;







      always @(posedge pclk_i) pclk_ena_o = 1'b1;
  end
endgenerate

endmodule