data/full_repos/permissive/157550807/src/idvr_bitlogic.v
data/verilator_xmls/31f57fba-93a5-459f-b5e6-ef742c5ea6c7.xml
module idvr_bitlogic #(
    parameter W=1
) (
    input  [W-1:0] I0,
    input  [W-1:0] I1,
    output [W-1:0] O,
    input  [1:0]   S
);


    reg [W-1:0] wO;
    always @(*) begin : switch
        case (S)
            2'b00 : wO = I0 ^ I1;
            2'b01 : wO = ~I0;
            2'b10 : wO = I0 | I1;
            2'b11 : wO = I0 & I1;
        endcase
    end
    assign O = wO;
    

endmodule
module idvr_bitlogic #(
    parameter W=1
) (
    input  [W-1:0] I0,
    input  [W-1:0] I1,
    output [W-1:0] O,
    input  [1:0]   S
);



    reg [W-1:0] wO;
    always @(*) begin : switch
        case (S)
            2'b00 : wO = I0 ^ I1;
            2'b01 : wO = ~I0;
            2'b10 : wO = I0 | I1;
            2'b11 : wO = I0 & I1;
        endcase
    end
    assign O = wO;
    

endmodule