data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/dff8ar.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/dff8ar.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                                        : ... In instance top_module\n            q <= 0;\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/dff8ar.v:12: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                                         : ... In instance top_module\n            q <= d;\n            ^\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input areset,
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk or posedge areset) begin
        if(areset == 1) begin
            q <= 0;
        end
        else begin
            q <= d;
        end
    end
endmodule
module top_module (
    input clk,
    input areset,
    input [7:0] d,
    output [7:0] q
);

    always @(posedge clk or posedge areset) begin
        if(areset == 1) begin
            q <= 0;
        end
        else begin
            q <= d;
        end
    end
endmodule