data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/xge/rtl/verilog/meta_sync.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/xge/rtl/verilog/meta_sync.v:61: Cannot find file containing module: 'meta_sync_single'\n        meta_sync_single #(.EDGE_DETECT (EDGE_DETECT))\n        ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/xge/rtl/verilog,data/full_repos/permissive/214858095/meta_sync_single\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/xge/rtl/verilog,data/full_repos/permissive/214858095/meta_sync_single.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/xge/rtl/verilog,data/full_repos/permissive/214858095/meta_sync_single.sv\n             meta_sync_single\n             meta_sync_single.v\n             meta_sync_single.sv\n             obj_dir/meta_sync_single\n             obj_dir/meta_sync_single.v\n             obj_dir/meta_sync_single.sv\n%Error: Exiting due to 1 error(s)\n"
module meta_sync(

  out,

  clk, reset_n, in
  );
 
parameter DWIDTH = 1;
parameter EDGE_DETECT = 0;
 
input                clk;
input                reset_n;
 
input  [DWIDTH-1:0]  in;
 
output [DWIDTH-1:0]  out;
 
generate
genvar               i;
 
    for (i = 0; i < DWIDTH; i = i + 1) begin : meta
 
        meta_sync_single #(.EDGE_DETECT (EDGE_DETECT))
          meta_sync_single0 (

                      .out              (out[i]),

                      .clk              (clk),
                      .reset_n          (reset_n),
                      .in               (in[i]));
 
    end
 
endgenerate
 
endmodule
module meta_sync(

  out,

  clk, reset_n, in
  );

 
parameter DWIDTH = 1;
parameter EDGE_DETECT = 0;
 
input                clk;
input                reset_n;
 
input  [DWIDTH-1:0]  in;
 
output [DWIDTH-1:0]  out;
 
generate
genvar               i;
 
    for (i = 0; i < DWIDTH; i = i + 1) begin : meta
 
        meta_sync_single #(.EDGE_DETECT (EDGE_DETECT))
          meta_sync_single0 (

                      .out              (out[i]),

                      .clk              (clk),
                      .reset_n          (reset_n),
                      .in               (in[i]));
 
    end
 
endgenerate
 
endmodule