data/full_repos/permissive/214620165/rtl/core/ram.sv
 line:103 column:9: Illegal character "'"
1: b'%Error: data/full_repos/permissive/214620165/rtl/core/ram.sv:17: Cannot find include file: ../../rtl/core/riscv_config.sv\n`include "../../rtl/core/riscv_config.sv" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214620165/rtl/core,data/full_repos/permissive/214620165/../../rtl/core/riscv_config.sv\n             data/full_repos/permissive/214620165/rtl/core,data/full_repos/permissive/214620165/../../rtl/core/riscv_config.sv.v\n             data/full_repos/permissive/214620165/rtl/core,data/full_repos/permissive/214620165/../../rtl/core/riscv_config.sv.sv\n             ../../rtl/core/riscv_config.sv\n             ../../rtl/core/riscv_config.sv.v\n             ../../rtl/core/riscv_config.sv.sv\n             obj_dir/../../rtl/core/riscv_config.sv\n             obj_dir/../../rtl/core/riscv_config.sv.v\n             obj_dir/../../rtl/core/riscv_config.sv.sv\n%Error: Exiting due to 1 error(s)\n'
module ram
    #(
    parameter ADDR_WIDTH = 34
  )(

    input  logic                   clk,

    input  logic                   instr_req_i,
    input  logic [ADDR_WIDTH-1:0]  instr_addr_i,
    output logic [31:0]           instr_rdata_o,
    output logic                   instr_rvalid_o,
    output logic                   instr_gnt_o,

    input  logic                   data_req_i,
    input  logic [ADDR_WIDTH-1:0]  data_addr_i,
    input  logic                   data_we_i,
    input  logic [3:0]             data_be_i,
    input  logic [31:0]            data_wdata_i,
    output logic [31:0]            data_rdata_o,
    output logic                   data_rvalid_o,
    output logic                   data_gnt_o
  );


`ifndef FPGA
   dp_ram
     #(
       .ADDR_WIDTH (ADDR_WIDTH)
       )
   dp_ram_i
     (
      .clk       ( clk           ),

      .en_a_i    ( instr_req_i   ),
      .addr_a_i  ( {11'd0,instr_addr_i[20:0]}  ),
      .wdata_a_i ( '0            ),
      .rdata_a_o ( instr_rdata_o ),
      .we_a_i    ( '0            ),
      .be_a_i    ( 4'b1111       ),

      .en_b_i    ( data_req_i    ),
      .addr_b_i  (  {11'd0,data_addr_i[20:0]}   ),
      .wdata_b_i ( data_wdata_i  ),
      .rdata_b_o ( data_rdata_o  ),
      .we_b_i    ( data_we_i     ),
      .be_b_i    ( data_be_i     )
      );
 `else
	blk_mem_gen_0 MEM (
		.clka(clk),
		.ena(instr_req_i),
		.wea('0),
		.addra(instr_addr_i[17:2]),
		.dina('0),
		.douta(instr_rdata_o),
		
		.clkb(clk),
		.enb(data_req_i),
		.web(data_be_i & {4{data_we_i}}),
		.addrb(data_addr_i[17:2]),
		.dinb(data_wdata_i),
		.doutb(data_rdata_o)
);  

		 











	











`endif		
   assign data_gnt_o  = data_req_i;
   assign instr_gnt_o = instr_req_i;

   always_ff @(posedge clk)
     begin
	data_rvalid_o  <= data_req_i;
	instr_rvalid_o <= instr_req_i;
     end

endmodule
module ram
    #(
    parameter ADDR_WIDTH = 34
  )(

    input  logic                   clk,

    input  logic                   instr_req_i,
    input  logic [ADDR_WIDTH-1:0]  instr_addr_i,
    output logic [31:0]           instr_rdata_o,
    output logic                   instr_rvalid_o,
    output logic                   instr_gnt_o,

    input  logic                   data_req_i,
    input  logic [ADDR_WIDTH-1:0]  data_addr_i,
    input  logic                   data_we_i,
    input  logic [3:0]             data_be_i,
    input  logic [31:0]            data_wdata_i,
    output logic [31:0]            data_rdata_o,
    output logic                   data_rvalid_o,
    output logic                   data_gnt_o
  );



`ifndef FPGA
   dp_ram
     #(
       .ADDR_WIDTH (ADDR_WIDTH)
       )
   dp_ram_i
     (
      .clk       ( clk           ),

      .en_a_i    ( instr_req_i   ),
      .addr_a_i  ( {11'd0,instr_addr_i[20:0]}  ),
      .wdata_a_i ( '0            ),
      .rdata_a_o ( instr_rdata_o ),
      .we_a_i    ( '0            ),
      .be_a_i    ( 4'b1111       ),

      .en_b_i    ( data_req_i    ),
      .addr_b_i  (  {11'd0,data_addr_i[20:0]}   ),
      .wdata_b_i ( data_wdata_i  ),
      .rdata_b_o ( data_rdata_o  ),
      .we_b_i    ( data_we_i     ),
      .be_b_i    ( data_be_i     )
      );
 `else
	blk_mem_gen_0 MEM (
		.clka(clk),
		.ena(instr_req_i),
		.wea('0),
		.addra(instr_addr_i[17:2]),
		.dina('0),
		.douta(instr_rdata_o),
		
		.clkb(clk),
		.enb(data_req_i),
		.web(data_be_i & {4{data_we_i}}),
		.addrb(data_addr_i[17:2]),
		.dinb(data_wdata_i),
		.doutb(data_rdata_o)
);  

		 











	











`endif		
   assign data_gnt_o  = data_req_i;
   assign instr_gnt_o = instr_req_i;

   always_ff @(posedge clk)
     begin
	data_rvalid_o  <= data_req_i;
	instr_rvalid_o <= instr_req_i;
     end

endmodule