data/full_repos/permissive/147466718/LC3_REG.v
data/verilator_xmls/0c0b38e9-ec4c-4df4-b005-fd18e3573742.xml
module LC3_REG(
    input [15:0] IN,
    input LD,
    input clk,
    output reg [15:0] OUT
    );

    always @(posedge clk) begin
        if (LD)
	    OUT <= IN;
    end
endmodule
module LC3_REG(
    input [15:0] IN,
    input LD,
    input clk,
    output reg [15:0] OUT
    );


    always @(posedge clk) begin
        if (LD)
	    OUT <= IN;
    end
endmodule