data/full_repos/permissive/20430511/hardware/FPGA/wishbone/rtl/wb_write.v
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/wishbone/rtl/wb_write.v:74: Cannot find file containing module: 'wb_cycle'\n   wb_cycle\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/wishbone/rtl,data/full_repos/permissive/20430511/wb_cycle\n             data/full_repos/permissive/20430511/hardware/FPGA/wishbone/rtl,data/full_repos/permissive/20430511/wb_cycle.v\n             data/full_repos/permissive/20430511/hardware/FPGA/wishbone/rtl,data/full_repos/permissive/20430511/wb_cycle.sv\n             wb_cycle\n             wb_cycle.v\n             wb_cycle.sv\n             obj_dir/wb_cycle\n             obj_dir/wb_cycle.v\n             obj_dir/wb_cycle.sv\n%Error: Exiting due to 1 error(s)\n"
module wb_write
  #(
    parameter ASYNC = 1,
    parameter PIPED = 1,
    parameter CHECK = 1,

    parameter DELAY = 3)
   (
    input  clk_i,
    input  rst_i,
    output cyc_o,
    output stb_o,
    output we_o,
    input  ack_i,
    input  wat_i,
    input  rty_i,
    input  err_i,

    input  write_i,
    output busy_o,
    output done_o,
    output fail_o
    );

   assign we_o = 1'b1;





   wb_cycle
     #( .ASYNC(ASYNC),
        .PIPED(PIPED),
        .CHECK(CHECK),
        .DELAY(DELAY)
        ) WRCYC
       (
        .clk_i  (clk_i),
        .rst_i  (rst_i),
        .cyc_o  (cyc_o),
        .stb_o  (stb_o),
        .ack_i  (ack_i),
        .wat_i  (wat_i),
        .rty_i  (rty_i),
        .err_i  (err_i),
        .start_i(write_i),
        .busy_o (busy_o),
        .done_o (done_o),
        .fail_o (fail_o)
        );


endmodule
module wb_write
  #(
    parameter ASYNC = 1,
    parameter PIPED = 1,
    parameter CHECK = 1,

    parameter DELAY = 3)
   (
    input  clk_i,
    input  rst_i,
    output cyc_o,
    output stb_o,
    output we_o,
    input  ack_i,
    input  wat_i,
    input  rty_i,
    input  err_i,

    input  write_i,
    output busy_o,
    output done_o,
    output fail_o
    );


   assign we_o = 1'b1;





   wb_cycle
     #( .ASYNC(ASYNC),
        .PIPED(PIPED),
        .CHECK(CHECK),
        .DELAY(DELAY)
        ) WRCYC
       (
        .clk_i  (clk_i),
        .rst_i  (rst_i),
        .cyc_o  (cyc_o),
        .stb_o  (stb_o),
        .ack_i  (ack_i),
        .wat_i  (wat_i),
        .rty_i  (rty_i),
        .err_i  (err_i),
        .start_i(write_i),
        .busy_o (busy_o),
        .done_o (done_o),
        .fail_o (fail_o)
        );


endmodule