data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/shiftReg.sv
 line:32: before: "DATA_WIDTH"
data/verilator_xmls/6ee18f44-ee44-4afa-9342-acd1b9c2d0b7.xml
module shiftReg # ( 
  DATA_WIDTH = 16,
  MAX_FANOUT = 256
) (
  clk,
  rst,
  ena,
  in_data,
  out_data
);



  input   wire                       clk;
  input   wire                       rst;
  input   wire                       ena;
  input   wire   [DATA_WIDTH-1:0]    in_data;
  output         [DATA_WIDTH-1:0]    out_data;



  reg [DATA_WIDTH-1:0] out_data;



  always @(posedge clk) begin
    if(rst) begin
      out_data <= 0;
    end else if(ena) begin
      out_data <= in_data;
    end 
  end

endmodule
module shiftReg # ( 
  DATA_WIDTH = 16,
  MAX_FANOUT = 256
) (
  clk,
  rst,
  ena,
  in_data,
  out_data
);




  input   wire                       clk;
  input   wire                       rst;
  input   wire                       ena;
  input   wire   [DATA_WIDTH-1:0]    in_data;
  output         [DATA_WIDTH-1:0]    out_data;



  reg [DATA_WIDTH-1:0] out_data;



  always @(posedge clk) begin
    if(rst) begin
      out_data <= 0;
    end else if(ena) begin
      out_data <= in_data;
    end 
  end

endmodule