data/full_repos/permissive/138243369/keyboard_proc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/138243369/keyboard_proc.v:46: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                       : ... In instance keyboard_proc\n   func2_instruction = 4\'d0;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/138243369/keyboard_proc.v:63: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                       : ... In instance keyboard_proc\n   func2_instruction = 4\'d0;\n                     ^\n%Error: Exiting due to 2 warning(s)\n'
module keyboard_proc(
input wire East,
input wire West,
input wire North,
input wire South,
input wire SW0,
input wire SW1,
input wire SW2,
input wire SW3,
input wire change,
input wire sysclk,
output reg [1:0] func_index,
output reg [3:0] func1_instruction,
output reg [4:0] func2_instruction,
output reg [4:0] func3_instruction,
output reg reset);

reg [1:0] current_function;

initial begin

	current_function = 0;
end

always @(posedge change) begin
	if (current_function == 2)
		current_function <= 0;
	else
		current_function <= current_function + 1;
end

always @(*) begin

	reset = SW0;

	func_index = current_function;

	case (current_function)
		2'd0: begin




			func1_instruction = {{{SW3, SW2}, SW1}, East};

			func2_instruction = 4'd0;

			func3_instruction = 5'd0;
		end
		2'd1: begin

			func1_instruction = 4'd0;


			func2_instruction = {SW3, {{{East, West}, North}, South}};

			func3_instruction = 5'd0;
		end
		2'd2: begin

			func1_instruction = 4'd0;

			func2_instruction = 4'd0;


			func3_instruction = {{{{East, West}, North}, South}, SW3};
		end
	endcase
end

endmodule
module keyboard_proc(
input wire East,
input wire West,
input wire North,
input wire South,
input wire SW0,
input wire SW1,
input wire SW2,
input wire SW3,
input wire change,
input wire sysclk,
output reg [1:0] func_index,
output reg [3:0] func1_instruction,
output reg [4:0] func2_instruction,
output reg [4:0] func3_instruction,
output reg reset);


reg [1:0] current_function;

initial begin

	current_function = 0;
end

always @(posedge change) begin
	if (current_function == 2)
		current_function <= 0;
	else
		current_function <= current_function + 1;
end

always @(*) begin

	reset = SW0;

	func_index = current_function;

	case (current_function)
		2'd0: begin




			func1_instruction = {{{SW3, SW2}, SW1}, East};

			func2_instruction = 4'd0;

			func3_instruction = 5'd0;
		end
		2'd1: begin

			func1_instruction = 4'd0;


			func2_instruction = {SW3, {{{East, West}, North}, South}};

			func3_instruction = 5'd0;
		end
		2'd2: begin

			func1_instruction = 4'd0;

			func2_instruction = 4'd0;


			func3_instruction = {{{{East, West}, North}, South}, SW3};
		end
	endcase
end

endmodule