data/full_repos/permissive/141525667/Source/hdl/testBenches/testBench_squareGenerator.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/141525667/Source/hdl/testBenches/testBench_squareGenerator.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/141525667/Source/hdl/testBenches/testBench_squareGenerator.v:23: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/141525667/Source/hdl/testBenches/testBench_squareGenerator.v:12: Cannot find file containing module: \'squareGenerator\'\n    squareGenerator dut(clk, rst, phase, frequency, dacLevel);\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141525667/Source/hdl/testBenches,data/full_repos/permissive/141525667/squareGenerator\n             data/full_repos/permissive/141525667/Source/hdl/testBenches,data/full_repos/permissive/141525667/squareGenerator.v\n             data/full_repos/permissive/141525667/Source/hdl/testBenches,data/full_repos/permissive/141525667/squareGenerator.sv\n             squareGenerator\n             squareGenerator.v\n             squareGenerator.sv\n             obj_dir/squareGenerator\n             obj_dir/squareGenerator.v\n             obj_dir/squareGenerator.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testBench_squareGenerator;

    reg clk;
    reg rst;
    reg[31:0] phase;
    reg[31:0] frequency;

    wire[7:0] dacLevel;

    squareGenerator dut(clk, rst, phase, frequency, dacLevel);

    initial
    begin
        clk <= 0;
        rst <= 1;
        phase <= 32'h00000000;
        frequency <= 32'd429496;
        #20
        rst <= 0;
    end
    always #10 clk = ~clk;
endmodule
module testBench_squareGenerator;


    reg clk;
    reg rst;
    reg[31:0] phase;
    reg[31:0] frequency;

    wire[7:0] dacLevel;

    squareGenerator dut(clk, rst, phase, frequency, dacLevel);

    initial
    begin
        clk <= 0;
        rst <= 1;
        phase <= 32'h00000000;
        frequency <= 32'd429496;
        #20
        rst <= 0;
    end
    always #10 clk = ~clk;
endmodule