data/full_repos/permissive/156129873/verilog/mem_wb.v
1: b'%Error: data/full_repos/permissive/156129873/verilog/mem_wb.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/156129873/verilog/mem_wb.v:23: Define or directive not defined: \'`RstEnable\'\n    if (rst == `RstEnable) begin\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/mem_wb.v:23: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if (rst == `RstEnable) begin\n                         ^\n%Error: data/full_repos/permissive/156129873/verilog/mem_wb.v:27: syntax error, unexpected else\n    end else begin\n        ^~~~\n%Error: Cannot continue\n'
module mem_wb (


    input wire clk,


    input wire rst,


    input wire re,
    input wire[15:0] data,
    input wire[3:0] regAddr,


    output reg reO,
    output reg[15:0] dataO,
    output reg[3:0] regAddrO
);

always @(posedge clk) begin
    if (rst == `RstEnable) begin
        reO <= 1'b0;
        dataO <= 16'b0;
        regAddrO <= 4'b0;
    end else begin
        reO <= re;
        dataO <= data;
        regAddrO <= regAddr;
    end
end

endmodule
module mem_wb (


    input wire clk,


    input wire rst,


    input wire re,
    input wire[15:0] data,
    input wire[3:0] regAddr,


    output reg reO,
    output reg[15:0] dataO,
    output reg[3:0] regAddrO
);


always @(posedge clk) begin
    if (rst == `RstEnable) begin
        reO <= 1'b0;
        dataO <= 16'b0;
        regAddrO <= 4'b0;
    end else begin
        reO <= re;
        dataO <= data;
        regAddrO <= regAddr;
    end
end

endmodule