data/full_repos/permissive/102388603/udp_rx.v
Syntax Error
1: b'%Error: data/full_repos/permissive/102388603/udp_rx.v:38: Cannot find file containing module: \'mem_2port\'\nmem_2port #(.N(8), .L(10), .do_clk_b(0))\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/mem_2port\n             data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/mem_2port.v\n             data/full_repos/permissive/102388603,data/full_repos/permissive/102388603/mem_2port.sv\n             mem_2port\n             mem_2port.v\n             mem_2port.sv\n             obj_dir/mem_2port\n             obj_dir/mem_2port.v\n             obj_dir/mem_2port.sv\n%Error: data/full_repos/permissive/102388603/udp_rx.v:48: Cannot find file containing module: \'rmii_rx_byte\'\nrmii_rx_byte rmiiRB(.clk(clk), .rst(rst), .rmii_clk(PhyClk50Mhz), .fast_eth(1), .rm_rx_data(PhyRxd),\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/102388603/udp_rx.v:178: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'rmiiRcvByte\' generates 8 bits.\n                                                                 : ... In instance udp_rx\n   33: crc16Ip[8:0] <= rmiiRcvByte;  \n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/102388603/udp_rx.v:263: Cannot find file containing module: \'crc_32_802_3\'\ncrc_32_802_3 crc_32(.data_in(rmiiRcvByte), .crc(crc32Eth), .new_crc(crc32Res));\n^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module udp_rx #(parameter packSizePow2 = 10)
(	input clk,
	input rst,
	output ready,
	reg [3:0]packStatus,
	input modeTransp,


	input [47:0]macLoc,
	output reg [47:0]macRem,
	output reg [31:0]ipLoc,
	output reg [31:0]ipRem,
	output reg [15:0]ipID,
	output reg [15:0]portLoc,
	output reg [15:0]portRem,
	output reg [15:0]lenUdp,

	input [1:0]PhyRxd,
	input PhyClk50Mhz,
	input PhyCRsDv,
	input PhyRstn
);
	


reg en_a, we_a, en_b, we_b;
reg [9:0] addr_a;
reg [7:0] w_data_a;
wire [7:0] r_data_a;


wire [7:0] r_data_b;

mem_2port #(.N(8), .L(10), .do_clk_b(0))
mem2pr(.clk(clk), .en_a(en_a), .we_a(we_a), .addr_a(addr_a), .w_data_a(w_data_a), .r_data_a(r_data_a),
						 .clk_b(clk), .en_b(0), .we_b(0), .addr_b(0), .w_data_b(0), .r_data_b(r_data_b));


						 

reg [7:0] rmiiRcvByte;
wire rmiiRcvRdy;
wire rmiiRcvBusy;
rmii_rx_byte rmiiRB(.clk(clk), .rst(rst), .rmii_clk(PhyClk50Mhz), .fast_eth(1), .rm_rx_data(PhyRxd),
				.rm_crs_dv(PhyCRsDv), .data(rmiiRcvByte), .rdy(rmiiRcvRdy), .busy(rmiiRcvBusy));

				






parameter lenAllEthHeader = 8 + 14+ 20;
parameter lenIpUdpHeaders = 20;

reg [15:0] lenEthPack;
reg [15:0] lenIpPack;


reg [15:0] countEthByteRcv;


reg [3:0] countHeaderByte;


reg [5:0]stateEth;
parameter idle 			= 0;
parameter recvHead		= 1;
parameter sendMAC 		= 2;
parameter sendIpHead	= 3;
parameter sendIpAddr 	= 4;
parameter sendUDPHead	= 5;
parameter reciveUDPData	= 6;
parameter sendEthCRC	= 7;








parameter packStOk			= 0;
parameter packStErrCRCEth	= 1;
parameter packStErrMACAddr	= 2;
parameter packStErrIpAddr	= 3;
parameter packStErrUDPPort	= 4;
parameter packStErrCRCIp	= 5;
parameter packStErrCRCType	= 6;
parameter packStErrVer		= 7;



reg getByteUDPEn;
wire getByte;


always @(posedge clk, posedge rst)
if(rst)
begin
	getByteUDPEn <= 0;
	lenIpPack <= 0;
	lenEthPack <= 0;

	stateEth <= idle;
	countEthByteRcv <= 0;
	countHeaderByte <= 0;
	
	en_a <= 0;
	we_a <= 0;
	addr_a <= 0;
	w_data_a <= 0;
end
else
begin

	
	case(stateEth)
	idle:
	begin
		if(PhyCRsDv)
		begin

			countEthByteRcv <= 1;


			packStatus <= (rmiiRcvByte == 8'h55) ? packStOk : packStErrCRCIp;

			stateEth <= recvHead;
		end
	end

	recvHead:
	begin
		if(PhyCRsDv)
		begin
			countEthByteRcv <= countEthByteRcv + 1;

			case(countEthByteRcv)

			0,1,2,3,4,5,6: packStatus <= (rmiiRcvByte == 8'h55) ? packStOk : packStErrCRCIp;
			7:	begin
				packStatus <= (rmiiRcvByte == 8'hD5) ? packStOk : packStErrCRCIp;
				crc32En <= 1;
				end

			8:	macRem[47:40]	<= rmiiRcvByte;
			9:	macRem[39:32]	<= rmiiRcvByte;
			10:	macRem[31:24]	<= rmiiRcvByte;
			11:	macRem[23:16]	<= rmiiRcvByte;
			12:	macRem[15:8]	<= rmiiRcvByte;
			13:	macRem[7:0]		<= rmiiRcvByte;
			14:	packStatus		<= (rmiiRcvByte == macLoc[47:40])	? packStOk : packStErrCRCIp;
			15:	packStatus		<= (rmiiRcvByte == macLoc[39:32])	? packStOk : packStErrCRCIp;
			16:	packStatus		<= (rmiiRcvByte == macLoc[31:24])	? packStOk : packStErrCRCIp;
			17:	packStatus		<= (rmiiRcvByte == macLoc[23:16])	? packStOk : packStErrCRCIp;
			18:	packStatus		<= (rmiiRcvByte == macLoc[15:8])	? packStOk : packStErrCRCIp;
			19: packStatus		<= (rmiiRcvByte == macLoc[7:0])		? packStOk : packStErrCRCIp;
			20: packStatus		<= (rmiiRcvByte == 8'h08)			? packStOk : packStErrCRCType;
			21:	packStatus		<= (rmiiRcvByte == 8'h00)			? packStOk : packStErrCRCType;

			22:	packStatus		<= (rmiiRcvByte == 8'h45)			? packStOk : packStErrVer;
			23: packStatus		<= (rmiiRcvByte == 8'h00)			? packStOk : packStErrVer;
			24:	lenIpPack[15:8]	<= rmiiRcvByte;
			25:	lenIpPack[7:0]	<= rmiiRcvByte;
			26:	ipID[15:8]		<= rmiiRcvByte;
			27:	ipID[7:0]		<= rmiiRcvByte;
			28:	rmiiRcvByte		<= 0;
			29:	rmiiRcvByte		<= 0;
			30:	rmiiRcvByte		<= 8'h80;
			31:	packStatus		<= (rmiiRcvByte == 8'h11) ? packStOk : packStErrVer;
			32:	crc16Ip[15:8]	<= rmiiRcvByte;
			33:	crc16Ip[8:0]	<= rmiiRcvByte;
			34:	ipLoc[31:24]	<= rmiiRcvByte;
			35:	ipLoc[23:16]	<= rmiiRcvByte;
			36:	ipLoc[15:8]		<= rmiiRcvByte;
			37:	ipLoc[7:0]		<= rmiiRcvByte;
			38:	ipRem[31:24]	<= rmiiRcvByte;
			39:	ipRem[23:16]	<= rmiiRcvByte;
			40:	ipRem[15:8]		<= rmiiRcvByte;
			41:	ipRem[7:0]		<= rmiiRcvByte;

			42:	portLoc[15:8]	<= rmiiRcvByte;
			43:	portLoc[7:0]	<= rmiiRcvByte;
			44:	portRem[15:8]	<= rmiiRcvByte;
			45:	portRem[7:0]	<= rmiiRcvByte;
			46:	lenUdp[15:8]	<= rmiiRcvByte;
			47:	lenUdp[7:0]		<= rmiiRcvByte;
			48:	;
			49:	begin
					;
					getByteUDPEn <= 1;
					en_a <= 1;
					stateEth <= reciveUDPData;
				end
			endcase
			
		end
	end
	
	reciveUDPData:
	begin
		if(rmiiRcvRdy)
		begin
			we_a <= 1;
			countEthByteRcv <= countEthByteRcv + 1;
			if(countEthByteRcv < lenEthPack - 4)
			begin
				w_data_a <= rmiiRcvByte;
				addr_a <= addr_a + 1;
			end
			else
			begin
				crc32En <= 0;
				rmiiRcvByte <= ~crc32Eth[31:24];
				crc32EthBuf <= ~crc32Eth << 8;
				getByteUDPEn <= 0;
				stateEth <= sendEthCRC;
			end
		end
		else
			we_a <= 0;
	end
	
	sendEthCRC:
	begin
		if(rmiiRcvRdy)
		begin
			countEthByteRcv <= countEthByteRcv + 1;
			rmiiRcvByte <= crc32EthBuf[31:24];
			crc32EthBuf <= crc32EthBuf << 8;
		end
		if(countEthByteRcv > lenEthPack)
			stateEth <= idle;
	end
	
	endcase
end

reg [15:0]countByteSend;


wire [15:0]crc16Ip;
wire [31:0]ip_crc_step0;
wire [31:0]ip_crc_step1;

assign ip_crc_step0 = 32'h4500 + 32'h002E + 32'hB3FE + 32'h8011 + {16'd0,ipLoc[31:16]} + {16'd0,ipLoc[15:0]} + {16'd0,ipRem[31:16]} + {16'd0,ipRem[15:0]};
assign ip_crc_step1 = {16'd0 ,ip_crc_step0[31:16]}+{16'd0,ip_crc_step0[15:0]};
assign crc16Ip = ~{ip_crc_step1[31:16]+ip_crc_step1[15:0]};




reg [31:0] crc32Eth;
reg [31:0] crc32EthBuf;
wire [31:0] crc32Res;
reg crc32En;
crc_32_802_3 crc_32(.data_in(rmiiRcvByte), .crc(crc32Eth), .new_crc(crc32Res));

always @(posedge clk, posedge rst)
if(rst)
begin
	crc32Eth <=  0;

end
else
begin
	if(countByteSend == 0)
		crc32Eth <= -1;
	else if((countEthByteRcv > 7) & rmiiRcvRdy)
		crc32Eth <= crc32Res;
	else
		crc32Eth <= crc32Eth;
end

endmodule
module udp_rx #(parameter packSizePow2 = 10)
(	input clk,
	input rst,
	output ready,
	reg [3:0]packStatus,
	input modeTransp,


	input [47:0]macLoc,
	output reg [47:0]macRem,
	output reg [31:0]ipLoc,
	output reg [31:0]ipRem,
	output reg [15:0]ipID,
	output reg [15:0]portLoc,
	output reg [15:0]portRem,
	output reg [15:0]lenUdp,

	input [1:0]PhyRxd,
	input PhyClk50Mhz,
	input PhyCRsDv,
	input PhyRstn
);

	


reg en_a, we_a, en_b, we_b;
reg [9:0] addr_a;
reg [7:0] w_data_a;
wire [7:0] r_data_a;


wire [7:0] r_data_b;

mem_2port #(.N(8), .L(10), .do_clk_b(0))
mem2pr(.clk(clk), .en_a(en_a), .we_a(we_a), .addr_a(addr_a), .w_data_a(w_data_a), .r_data_a(r_data_a),
						 .clk_b(clk), .en_b(0), .we_b(0), .addr_b(0), .w_data_b(0), .r_data_b(r_data_b));


						 

reg [7:0] rmiiRcvByte;
wire rmiiRcvRdy;
wire rmiiRcvBusy;
rmii_rx_byte rmiiRB(.clk(clk), .rst(rst), .rmii_clk(PhyClk50Mhz), .fast_eth(1), .rm_rx_data(PhyRxd),
				.rm_crs_dv(PhyCRsDv), .data(rmiiRcvByte), .rdy(rmiiRcvRdy), .busy(rmiiRcvBusy));

				






parameter lenAllEthHeader = 8 + 14+ 20;
parameter lenIpUdpHeaders = 20;

reg [15:0] lenEthPack;
reg [15:0] lenIpPack;


reg [15:0] countEthByteRcv;


reg [3:0] countHeaderByte;


reg [5:0]stateEth;
parameter idle 			= 0;
parameter recvHead		= 1;
parameter sendMAC 		= 2;
parameter sendIpHead	= 3;
parameter sendIpAddr 	= 4;
parameter sendUDPHead	= 5;
parameter reciveUDPData	= 6;
parameter sendEthCRC	= 7;








parameter packStOk			= 0;
parameter packStErrCRCEth	= 1;
parameter packStErrMACAddr	= 2;
parameter packStErrIpAddr	= 3;
parameter packStErrUDPPort	= 4;
parameter packStErrCRCIp	= 5;
parameter packStErrCRCType	= 6;
parameter packStErrVer		= 7;



reg getByteUDPEn;
wire getByte;


always @(posedge clk, posedge rst)
if(rst)
begin
	getByteUDPEn <= 0;
	lenIpPack <= 0;
	lenEthPack <= 0;

	stateEth <= idle;
	countEthByteRcv <= 0;
	countHeaderByte <= 0;
	
	en_a <= 0;
	we_a <= 0;
	addr_a <= 0;
	w_data_a <= 0;
end
else
begin

	
	case(stateEth)
	idle:
	begin
		if(PhyCRsDv)
		begin

			countEthByteRcv <= 1;


			packStatus <= (rmiiRcvByte == 8'h55) ? packStOk : packStErrCRCIp;

			stateEth <= recvHead;
		end
	end

	recvHead:
	begin
		if(PhyCRsDv)
		begin
			countEthByteRcv <= countEthByteRcv + 1;

			case(countEthByteRcv)

			0,1,2,3,4,5,6: packStatus <= (rmiiRcvByte == 8'h55) ? packStOk : packStErrCRCIp;
			7:	begin
				packStatus <= (rmiiRcvByte == 8'hD5) ? packStOk : packStErrCRCIp;
				crc32En <= 1;
				end

			8:	macRem[47:40]	<= rmiiRcvByte;
			9:	macRem[39:32]	<= rmiiRcvByte;
			10:	macRem[31:24]	<= rmiiRcvByte;
			11:	macRem[23:16]	<= rmiiRcvByte;
			12:	macRem[15:8]	<= rmiiRcvByte;
			13:	macRem[7:0]		<= rmiiRcvByte;
			14:	packStatus		<= (rmiiRcvByte == macLoc[47:40])	? packStOk : packStErrCRCIp;
			15:	packStatus		<= (rmiiRcvByte == macLoc[39:32])	? packStOk : packStErrCRCIp;
			16:	packStatus		<= (rmiiRcvByte == macLoc[31:24])	? packStOk : packStErrCRCIp;
			17:	packStatus		<= (rmiiRcvByte == macLoc[23:16])	? packStOk : packStErrCRCIp;
			18:	packStatus		<= (rmiiRcvByte == macLoc[15:8])	? packStOk : packStErrCRCIp;
			19: packStatus		<= (rmiiRcvByte == macLoc[7:0])		? packStOk : packStErrCRCIp;
			20: packStatus		<= (rmiiRcvByte == 8'h08)			? packStOk : packStErrCRCType;
			21:	packStatus		<= (rmiiRcvByte == 8'h00)			? packStOk : packStErrCRCType;

			22:	packStatus		<= (rmiiRcvByte == 8'h45)			? packStOk : packStErrVer;
			23: packStatus		<= (rmiiRcvByte == 8'h00)			? packStOk : packStErrVer;
			24:	lenIpPack[15:8]	<= rmiiRcvByte;
			25:	lenIpPack[7:0]	<= rmiiRcvByte;
			26:	ipID[15:8]		<= rmiiRcvByte;
			27:	ipID[7:0]		<= rmiiRcvByte;
			28:	rmiiRcvByte		<= 0;
			29:	rmiiRcvByte		<= 0;
			30:	rmiiRcvByte		<= 8'h80;
			31:	packStatus		<= (rmiiRcvByte == 8'h11) ? packStOk : packStErrVer;
			32:	crc16Ip[15:8]	<= rmiiRcvByte;
			33:	crc16Ip[8:0]	<= rmiiRcvByte;
			34:	ipLoc[31:24]	<= rmiiRcvByte;
			35:	ipLoc[23:16]	<= rmiiRcvByte;
			36:	ipLoc[15:8]		<= rmiiRcvByte;
			37:	ipLoc[7:0]		<= rmiiRcvByte;
			38:	ipRem[31:24]	<= rmiiRcvByte;
			39:	ipRem[23:16]	<= rmiiRcvByte;
			40:	ipRem[15:8]		<= rmiiRcvByte;
			41:	ipRem[7:0]		<= rmiiRcvByte;

			42:	portLoc[15:8]	<= rmiiRcvByte;
			43:	portLoc[7:0]	<= rmiiRcvByte;
			44:	portRem[15:8]	<= rmiiRcvByte;
			45:	portRem[7:0]	<= rmiiRcvByte;
			46:	lenUdp[15:8]	<= rmiiRcvByte;
			47:	lenUdp[7:0]		<= rmiiRcvByte;
			48:	;
			49:	begin
					;
					getByteUDPEn <= 1;
					en_a <= 1;
					stateEth <= reciveUDPData;
				end
			endcase
			
		end
	end
	
	reciveUDPData:
	begin
		if(rmiiRcvRdy)
		begin
			we_a <= 1;
			countEthByteRcv <= countEthByteRcv + 1;
			if(countEthByteRcv < lenEthPack - 4)
			begin
				w_data_a <= rmiiRcvByte;
				addr_a <= addr_a + 1;
			end
			else
			begin
				crc32En <= 0;
				rmiiRcvByte <= ~crc32Eth[31:24];
				crc32EthBuf <= ~crc32Eth << 8;
				getByteUDPEn <= 0;
				stateEth <= sendEthCRC;
			end
		end
		else
			we_a <= 0;
	end
	
	sendEthCRC:
	begin
		if(rmiiRcvRdy)
		begin
			countEthByteRcv <= countEthByteRcv + 1;
			rmiiRcvByte <= crc32EthBuf[31:24];
			crc32EthBuf <= crc32EthBuf << 8;
		end
		if(countEthByteRcv > lenEthPack)
			stateEth <= idle;
	end
	
	endcase
end

reg [15:0]countByteSend;


wire [15:0]crc16Ip;
wire [31:0]ip_crc_step0;
wire [31:0]ip_crc_step1;

assign ip_crc_step0 = 32'h4500 + 32'h002E + 32'hB3FE + 32'h8011 + {16'd0,ipLoc[31:16]} + {16'd0,ipLoc[15:0]} + {16'd0,ipRem[31:16]} + {16'd0,ipRem[15:0]};
assign ip_crc_step1 = {16'd0 ,ip_crc_step0[31:16]}+{16'd0,ip_crc_step0[15:0]};
assign crc16Ip = ~{ip_crc_step1[31:16]+ip_crc_step1[15:0]};




reg [31:0] crc32Eth;
reg [31:0] crc32EthBuf;
wire [31:0] crc32Res;
reg crc32En;
crc_32_802_3 crc_32(.data_in(rmiiRcvByte), .crc(crc32Eth), .new_crc(crc32Res));

always @(posedge clk, posedge rst)
if(rst)
begin
	crc32Eth <=  0;

end
else
begin
	if(countByteSend == 0)
		crc32Eth <= -1;
	else if((countEthByteRcv > 7) & rmiiRcvRdy)
		crc32Eth <= crc32Res;
	else
		crc32Eth <= crc32Eth;
end

endmodule