data/full_repos/permissive/159891569/lenCounter.t.v
 line:15: before: "-"
1: b'%Error: data/full_repos/permissive/159891569/lenCounter.t.v:1: Cannot find include file: lenCounter.v\n`include "lenCounter.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/lenCounter.v\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/lenCounter.v.v\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/lenCounter.v.sv\n             lenCounter.v\n             lenCounter.v.v\n             lenCounter.v.sv\n             obj_dir/lenCounter.v\n             obj_dir/lenCounter.v.v\n             obj_dir/lenCounter.v.sv\n%Error: data/full_repos/permissive/159891569/lenCounter.t.v:12: Unsupported or unknown PLI call: $monitor\n  $monitor("clk=%d  lenLoad=%d trigger=%b lenEnable=%b chanEnable=%b", clk, lenLoad, trigger, lenEnable, chanEnable);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:16: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:16: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:18: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:18: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:20: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:20: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:21: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:21: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:22: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:22: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:23: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/lenCounter.t.v:23: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1; #10; clk = 0; #10;\n                         ^\n%Error: Exiting due to 2 error(s), 13 warning(s)\n'
module testlenCounter();

	reg clk, trigger, lenEnable;
	reg [5:0] lenLoad;
	wire chanEnable;

	lenCounter dut(clk, lenLoad, trigger, lenEnable, chanEnable);

	initial begin
		$monitor("clk=%d  lenLoad=%d trigger=%b lenEnable=%b chanEnable=%b", clk, lenLoad, trigger, lenEnable, chanEnable);

		clk = 0; lenLoad = 6'd63; trigger = 0; lenEnable = 1;
		#10
		clk = 1; #10; clk = 0; #10;
		lenLoad = 6'd61; trigger = 1;
		clk = 1; #10; clk = 0; #10;
		trigger = 0;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;

		$finish;
	end
endmodule
module testlenCounter();


	reg clk, trigger, lenEnable;
	reg [5:0] lenLoad;
	wire chanEnable;

	lenCounter dut(clk, lenLoad, trigger, lenEnable, chanEnable);

	initial begin
		$monitor("clk=%d  lenLoad=%d trigger=%b lenEnable=%b chanEnable=%b", clk, lenLoad, trigger, lenEnable, chanEnable);

		clk = 0; lenLoad = 6'd63; trigger = 0; lenEnable = 1;
		#10
		clk = 1; #10; clk = 0; #10;
		lenLoad = 6'd61; trigger = 1;
		clk = 1; #10; clk = 0; #10;
		trigger = 0;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;
		clk = 1; #10; clk = 0; #10;

		$finish;
	end
endmodule