data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Hybrid/Hybrid_tb.v
 line:67: before: "real"
1: b'%Error: Cannot find file containing module: Project/SourceCode/Hybrid,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Hybrid,data/full_repos/permissive/119107706\n             Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Hybrid,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Hybrid/Hybrid_tb.v\n%Error: Exiting due to 3 error(s)\n'
module Hybrid_tb;


	parameter WL = 25;
	parameter LUT_bits = 27;
	parameter LUT_addWidth = 11;
	parameter dWL = 30;
	parameter p = 1;


	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;
	reg [1:0] FUNCTION;
	

	wire [WL-1:0] dout;



	reg [WL-1:0] Testdata_vec_NR [`Testdata_Depth-1:0];

	reg [dWL-1:0] Simu_Result_Matlab [`Testdata_Depth-1:0];


	real real_din, real_MATLAB_reuslt, real_Xilinx_result;
	real real_iniValue, real_input_mul1, real_xo;
	real real_dout;


	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;

	

	function real fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF-1; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		fixedToFloat = retVal - (in[WI+WF-1] * (2.0**(WI-1)));
		end
	endfunction	



	Hybrid
	#(
		.WL(WL),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.dWL(dWL),
		.p(p)
	)
	Fang_rec_interpolat (
		.CLK(CLK), 
		.nRST(nRST), 
		.CE(CE), 
		.din(din),
		.FUNCTION(FUNCTION),		
		.dout(dout)
	);


	integer count;
	real count_mismatched = 0;
	initial begin




		$readmemb("ini_input_binary_rec_interpolat_hybrid_p1.txt", Testdata_vec_NR);		
		FUNCTION = 2'b00;

		$readmemb("LUT_rec_Interpolat_hybrid_p1.txt", Hybrid_tb.Fang_rec_interpolat.LUT_rec);
		$readmemb("result_rec_interpolat_round_hybrid_p1.txt", Simu_Result_Matlab);





		nRST = 0; CE = 0;
		@(posedge CLK); CE = 1; 
		nRST = 1;

		
		if(p==1) begin
			for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
				din = Testdata_vec_NR[count];
				@(posedge CLK);
				$display("MATLAB: %f, Xilinx: %f", fixedToFloat(Simu_Result_Matlab[count-1], 2, WL-2), fixedToFloat(dout, 2, WL-2));
				if (fixedToFloat(Simu_Result_Matlab[count-1], 2, WL-2)==fixedToFloat(dout, 2, WL-2)) begin

					$display("MATCHED");

				end else begin
					count_mismatched = count_mismatched + 1;
					$display("MISMATCHED HERE <================= !!! ");
					$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-1], dout);
				end
				@(posedge CLK);
				if (count==`Testdata_Depth) begin
					$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
					$finish;
				end
			end
		end else if (p == 2) begin
			for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
				din = Testdata_vec_NR[count];
				@(posedge CLK);@(posedge CLK);
				$display("MATLAB: %f, Xilinx: %f", fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1), fixedToFloat(dout, 1, WL-1));
				if (fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1)==fixedToFloat(dout, 1, WL-1))

					$display("MATCHED");
				else begin
					count_mismatched = count_mismatched + 1;
					$display("MISMATCHED HERE <================= !!! ");
					$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-1], dout);
				end
				@(posedge CLK);
				if (count==`Testdata_Depth) begin
					$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
					$finish;
				end
			end
		end
	end



	always @ din real_din = fixedToFloat(din, 2, WL-2);


	always @ Hybrid_tb.Fang_rec_interpolat.iniValue real_iniValue = fixedToFloat(Hybrid_tb.Fang_rec_interpolat.iniValue, 2, LUT_bits-2);
	always @ Hybrid_tb.Fang_rec_interpolat.input_mul1 real_input_mul1 = fixedToFloat(Hybrid_tb.Fang_rec_interpolat.input_mul1, 2, dWL-2);
	always @ Hybrid_tb.Fang_rec_interpolat.xo real_xo = fixedToFloat(Hybrid_tb.Fang_rec_interpolat.xo, 2, WL-LUT_addWidth-2);


	always @ dout real_Xilinx_result = fixedToFloat(dout, 2, WL-2);
	always @ Simu_Result_Matlab[count] real_MATLAB_reuslt = fixedToFloat(Simu_Result_Matlab[count], 2, WL-2);	
endmodule
module Hybrid_tb;



	parameter WL = 25;
	parameter LUT_bits = 27;
	parameter LUT_addWidth = 11;
	parameter dWL = 30;
	parameter p = 1;


	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;
	reg [1:0] FUNCTION;
	

	wire [WL-1:0] dout;



	reg [WL-1:0] Testdata_vec_NR [`Testdata_Depth-1:0];

	reg [dWL-1:0] Simu_Result_Matlab [`Testdata_Depth-1:0];


	real real_din, real_MATLAB_reuslt, real_Xilinx_result;
	real real_iniValue, real_input_mul1, real_xo;
	real real_dout;


	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;

	

	function real fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF-1; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		fixedToFloat = retVal - (in[WI+WF-1] * (2.0**(WI-1)));
		end
	endfunction	



	Hybrid
	#(
		.WL(WL),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.dWL(dWL),
		.p(p)
	)
	Fang_rec_interpolat (
		.CLK(CLK), 
		.nRST(nRST), 
		.CE(CE), 
		.din(din),
		.FUNCTION(FUNCTION),		
		.dout(dout)
	);


	integer count;
	real count_mismatched = 0;
	initial begin




		$readmemb("ini_input_binary_rec_interpolat_hybrid_p1.txt", Testdata_vec_NR);		
		FUNCTION = 2'b00;

		$readmemb("LUT_rec_Interpolat_hybrid_p1.txt", Hybrid_tb.Fang_rec_interpolat.LUT_rec);
		$readmemb("result_rec_interpolat_round_hybrid_p1.txt", Simu_Result_Matlab);





		nRST = 0; CE = 0;
		@(posedge CLK); CE = 1; 
		nRST = 1;

		
		if(p==1) begin
			for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
				din = Testdata_vec_NR[count];
				@(posedge CLK);
				$display("MATLAB: %f, Xilinx: %f", fixedToFloat(Simu_Result_Matlab[count-1], 2, WL-2), fixedToFloat(dout, 2, WL-2));
				if (fixedToFloat(Simu_Result_Matlab[count-1], 2, WL-2)==fixedToFloat(dout, 2, WL-2)) begin

					$display("MATCHED");

				end else begin
					count_mismatched = count_mismatched + 1;
					$display("MISMATCHED HERE <================= !!! ");
					$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-1], dout);
				end
				@(posedge CLK);
				if (count==`Testdata_Depth) begin
					$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
					$finish;
				end
			end
		end else if (p == 2) begin
			for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
				din = Testdata_vec_NR[count];
				@(posedge CLK);@(posedge CLK);
				$display("MATLAB: %f, Xilinx: %f", fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1), fixedToFloat(dout, 1, WL-1));
				if (fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1)==fixedToFloat(dout, 1, WL-1))

					$display("MATCHED");
				else begin
					count_mismatched = count_mismatched + 1;
					$display("MISMATCHED HERE <================= !!! ");
					$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-1], dout);
				end
				@(posedge CLK);
				if (count==`Testdata_Depth) begin
					$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
					$finish;
				end
			end
		end
	end



	always @ din real_din = fixedToFloat(din, 2, WL-2);


	always @ Hybrid_tb.Fang_rec_interpolat.iniValue real_iniValue = fixedToFloat(Hybrid_tb.Fang_rec_interpolat.iniValue, 2, LUT_bits-2);
	always @ Hybrid_tb.Fang_rec_interpolat.input_mul1 real_input_mul1 = fixedToFloat(Hybrid_tb.Fang_rec_interpolat.input_mul1, 2, dWL-2);
	always @ Hybrid_tb.Fang_rec_interpolat.xo real_xo = fixedToFloat(Hybrid_tb.Fang_rec_interpolat.xo, 2, WL-LUT_addWidth-2);


	always @ dout real_Xilinx_result = fixedToFloat(dout, 2, WL-2);
	always @ Simu_Result_Matlab[count] real_MATLAB_reuslt = fixedToFloat(Simu_Result_Matlab[count], 2, WL-2);	
endmodule