data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v
None: at end of input
1: b'%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:30: Cannot find include file: cypress.v\n`include "cypress.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0,data/full_repos/permissive/105824869/cypress.v\n             data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0,data/full_repos/permissive/105824869/cypress.v.v\n             data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0,data/full_repos/permissive/105824869/cypress.v.sv\n             cypress.v\n             cypress.v.v\n             cypress.v.sv\n             obj_dir/cypress.v\n             obj_dir/cypress.v.v\n             obj_dir/cypress.v.sv\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:102: Define or directive not defined: \'`TRUE\'\n    cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync\n                                                ^~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:121: Define or directive not defined: \'`CS_ALU_OP__ADD\'\n    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:121: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,\n                   ^\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:121: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:121: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:122: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:122: Define or directive not defined: \'`CS_A0_SRC__ALU\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:122: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:123: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:123: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:123: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:124: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:125: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:125: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:125: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:126: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:126: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:126: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:127: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:127: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:127: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:128: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:129: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:129: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:129: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:130: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:130: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:130: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:131: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:131: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:131: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:132: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:133: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:133: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:133: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:134: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:134: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:134: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:135: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:135: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:135: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:136: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:137: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:137: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:137: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:138: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:138: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:138: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/105824869/DDS32_lib.cylib/DDS32_v0_0/DDS32_v0_0.v:139: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module DDS32_v0_0 (
	drq,
	outp,
	clk,
	res
);
	output  drq;
	output  outp;
	input   clk;
	input   res;
    parameter BusWidth = 8'd8;



    wire     nc1,nc2,nc3,nc4,nc5,nc6,nc7,nc8,nc9, nc10, nc11, nc12;

	
	localparam [7:0]    DDS_8_BIT    = 8'd8;
    localparam [7:0]    DDS_16_BIT   = 8'd16;
	localparam [7:0]    DDS_24_BIT   = 8'd24;
	localparam [7:0]    DDS_32_BIT   = 8'd32;    

	
							 
	wire co_msb;
	assign drq = co_msb;
	
	wire cmsb;
	assign outp = cmsb;
	

    wire op_clk;
    
    cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync
    (
.clock_in(clk),
.enable(1'b1),
.clock_out(op_clk)
    );  	
	
	localparam [2:0] ACC_CMD_SUM = 3'b0;
	wire [2:0] cs_addr;
	
	assign cs_addr = ACC_CMD_SUM;





    
    parameter dpconfig0 = 
{
    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    8'hFF, 8'h00,
    8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_DEFSI,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
};

    parameter dpconfig1 = 
{
    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    8'hFF, 8'h00,
    8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_DEFSI,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
};

	generate 
	if(BusWidth == DDS_8_BIT) begin : sD8
	cy_psoc3_dp8 #(.cy_dpconfig_a (dpconfig0))
    DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb(co_msb),
.cmsb(cmsb),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
	end
    else if(BusWidth <= DDS_16_BIT) begin : sD16
	cy_psoc3_dp16 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1))
    DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc1}),
.cmsb({cmsb,nc2}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
	end
    else if(BusWidth <= DDS_24_BIT) begin : sD24
    cy_psoc3_dp24 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1), 
                    .cy_dpconfig_c (dpconfig1))
    DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc3,nc4}),
.cmsb({cmsb,nc5,nc6}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
	end
    else if(BusWidth <= DDS_32_BIT) begin : sD32
    cy_psoc3_dp32 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1), 
                    .cy_dpconfig_c (dpconfig1), .cy_dpconfig_d (dpconfig1))
    DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc7,nc8,nc9}),
.cmsb({cmsb,nc10,nc11,nc12}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
	end
	endgenerate
endmodule
module DDS32_v0_0 (
	drq,
	outp,
	clk,
	res
);

	output  drq;
	output  outp;
	input   clk;
	input   res;
    parameter BusWidth = 8'd8;



    wire     nc1,nc2,nc3,nc4,nc5,nc6,nc7,nc8,nc9, nc10, nc11, nc12;

	
	localparam [7:0]    DDS_8_BIT    = 8'd8;
    localparam [7:0]    DDS_16_BIT   = 8'd16;
	localparam [7:0]    DDS_24_BIT   = 8'd24;
	localparam [7:0]    DDS_32_BIT   = 8'd32;    

	
							 
	wire co_msb;
	assign drq = co_msb;
	
	wire cmsb;
	assign outp = cmsb;
	

    wire op_clk;
    
    cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync
    (
.clock_in(clk),
.enable(1'b1),
.clock_out(op_clk)
    );  	
	
	localparam [2:0] ACC_CMD_SUM = 3'b0;
	wire [2:0] cs_addr;
	
	assign cs_addr = ACC_CMD_SUM;





    
    parameter dpconfig0 = 
{
    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    8'hFF, 8'h00,
    8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_DEFSI,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
};

    parameter dpconfig1 = 
{
    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    8'hFF, 8'h00,
    8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
    `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_DEFSI,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
};

	generate 
	if(BusWidth == DDS_8_BIT) begin : sD8
	cy_psoc3_dp8 #(.cy_dpconfig_a (dpconfig0))
    DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb(co_msb),
.cmsb(cmsb),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
	end
    else if(BusWidth <= DDS_16_BIT) begin : sD16
	cy_psoc3_dp16 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1))
    DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc1}),
.cmsb({cmsb,nc2}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
	end
    else if(BusWidth <= DDS_24_BIT) begin : sD24
    cy_psoc3_dp24 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1), 
                    .cy_dpconfig_c (dpconfig1))
    DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc3,nc4}),
.cmsb({cmsb,nc5,nc6}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
	end
    else if(BusWidth <= DDS_32_BIT) begin : sD32
    cy_psoc3_dp32 #(.cy_dpconfig_a (dpconfig0), .cy_dpconfig_b (dpconfig1), 
                    .cy_dpconfig_c (dpconfig1), .cy_dpconfig_d (dpconfig1))
    DDSdp(
.reset(res),
.clk(op_clk),
.cs_addr(cs_addr),
.route_si(1'b0),
.route_ci(1'b0),
.f0_load(1'b0),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.ce0(),
.cl0(),
.z0(),
.ff0(),
.ce1(),
.cl1(),
.z1(),
.ff1(),
.ov_msb(),
.co_msb({co_msb,nc7,nc8,nc9}),
.cmsb({cmsb,nc10,nc11,nc12}),
.so(),
.f0_bus_stat(),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
	end
	endgenerate
endmodule