data/full_repos/permissive/152129081/src/spram.v
data/verilator_xmls/ca9eaec9-d72d-446e-8015-13e24600b170.xml
module spram (
   clk,
   cs,
   we,
   din,
   addr,
   dout);

parameter ADDR_WIDTH = 5;
parameter DATA_WIDTH = 128;

input   clk;
input   cs;
input   we;
input   [DATA_WIDTH-1:0] din;
input   [ADDR_WIDTH-1:0] addr;
output  [DATA_WIDTH-1:0] dout;

reg     [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH) - 1 : 0];
reg     [DATA_WIDTH-1:0] q;

`ifdef ALTERA_SYNC_SRAM








`else
reg   [ADDR_WIDTH-1:0] addr_reg;
always @(posedge clk) begin
  if (we && cs)
    ram[addr] <= din;
  addr_reg <= addr;
end
`endif

assign dout = ram[addr_reg];

endmodule
module spram (
   clk,
   cs,
   we,
   din,
   addr,
   dout);


parameter ADDR_WIDTH = 5;
parameter DATA_WIDTH = 128;

input   clk;
input   cs;
input   we;
input   [DATA_WIDTH-1:0] din;
input   [ADDR_WIDTH-1:0] addr;
output  [DATA_WIDTH-1:0] dout;

reg     [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH) - 1 : 0];
reg     [DATA_WIDTH-1:0] q;

`ifdef ALTERA_SYNC_SRAM








`else
reg   [ADDR_WIDTH-1:0] addr_reg;
always @(posedge clk) begin
  if (we && cs)
    ram[addr] <= din;
  addr_reg <= addr;
end
`endif

assign dout = ram[addr_reg];

endmodule