data/full_repos/permissive/139831595/hw/source/select.v
data/verilator_xmls/f3f30060-7903-4118-9609-1e29ba4128c8.xml
module select
#(
	parameter NUM_SEL=16, 
	NUM_LOG=4, 
	NUM_WIDTH=64
)
(
    input[NUM_WIDTH*NUM_SEL-1:0] data_in,
    input[NUM_LOG-1:0] sel,
    output[NUM_WIDTH-1:0] data_out
);


reg[NUM_WIDTH-1:0] data_array[NUM_SEL-1:0];
generate
genvar i;
for(i=0;i<NUM_SEL;i=i+1)begin:gearay
    always@(*)begin
        data_array[i]<=data_in[NUM_WIDTH*i+NUM_WIDTH-1:NUM_WIDTH*i];
    end
end
endgenerate
assign data_out= data_array[sel];
endmodule
module select
#(
	parameter NUM_SEL=16, 
	NUM_LOG=4, 
	NUM_WIDTH=64
)
(
    input[NUM_WIDTH*NUM_SEL-1:0] data_in,
    input[NUM_LOG-1:0] sel,
    output[NUM_WIDTH-1:0] data_out
);



reg[NUM_WIDTH-1:0] data_array[NUM_SEL-1:0];
generate
genvar i;
for(i=0;i<NUM_SEL;i=i+1)begin:gearay
    always@(*)begin
        data_array[i]<=data_in[NUM_WIDTH*i+NUM_WIDTH-1:NUM_WIDTH*i];
    end
end
endgenerate
assign data_out= data_array[sel];
endmodule