data/full_repos/permissive/105847195/combine.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #10 assign consumer_iclk = ~consumer_iclk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #5 assign producer_iclk = ~producer_iclk;      \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1 assign clk = ~clk;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:30: Unsupported: Ignoring delay on this delayed statement.\n   #5000 $finish;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #5 producer_iclk = ~(producer_iclk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:137: Unsupported: Ignoring delay on this delayed statement.\n      #30for(j=0;j<10;j++)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:151: Unsupported: Ignoring delay on this delayed statement.\n      #0 last = last +1;      \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:167: Unsupported: Ignoring delay on this delayed statement.\n          #0 start = start +1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:200: Unsupported: Ignoring delay on this delayed statement.\n      #1 consumer_req = 0;\n      ^\n%Error: data/full_repos/permissive/105847195/combine.v:209: Unsupported or unknown PLI call: $monitor\n      $monitor("data consumed : %d at time = %t", consumer_data,$time);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105847195/combine.v:217: Unsupported: Ignoring delay on this delayed statement.\n      #10 consumer_iclk = ~consumer_iclk;\n      ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifo(consumer_data,producer_data, consumer_req);
  
  input consumer_req;
  input producer_data;
  output consumer_data;
    
  reg [3:0] consumer_data;
  reg [3:0] producer_data;
  reg consumer_req;
    
  int i;
  int j;
  int last;
  int start;
  int diff;
  int last_s;
  int start_s;
  
  reg [3:0] queue [9:0];
  
  
  initial
    begin
      assign last_s = last % 10;
      assign start_s = start % 10;
      assign diff = last - start;


      #30for(j=0;j<10;j++)
        begin

        end
      
    end
  

  always @ (producer_data)
    if((diff < 10))
      begin
    begin      
      queue[last_s] = producer_data;

      #0 last = last +1;      
    end
      end else begin
        $finish;
      end
  

  always @(consumer_req)
    begin
      if(consumer_req == 1)
        begin
          if(diff != 0)
            begin

              consumer_data = queue[start_s];

          #0 start = start +1;
            end
          
          

        end
    end
  

endmodule
module fifo(consumer_data,producer_data, consumer_req);

  
  input consumer_req;
  input producer_data;
  output consumer_data;
    
  reg [3:0] consumer_data;
  reg [3:0] producer_data;
  reg consumer_req;
    
  int i;
  int j;
  int last;
  int start;
  int diff;
  int last_s;
  int start_s;
  
  reg [3:0] queue [9:0];
  
  
  initial
    begin
      assign last_s = last % 10;
      assign start_s = start % 10;
      assign diff = last - start;


      #30for(j=0;j<10;j++)
        begin

        end
      
    end
  

  always @ (producer_data)
    if((diff < 10))
      begin
    begin      
      queue[last_s] = producer_data;

      #0 last = last +1;      
    end
      end else begin
        $finish;
      end
  

  always @(consumer_req)
    begin
      if(consumer_req == 1)
        begin
          if(diff != 0)
            begin

              consumer_data = queue[start_s];

          #0 start = start +1;
            end
          
          

        end
    end
  

endmodule