data/full_repos/permissive/203526788/iVerilog/SimpleTemplate/dff.v
data/verilator_xmls/c4e11981-cac0-41f1-b6bb-26961b19b9c6.xml
module dff (input wire clk,
            input wire d,
            output reg q
           );

    always @(posedge clk)
    begin
		  q <= d;
    end

endmodule
module dff (input wire clk,
            input wire d,
            output reg q
           );


    always @(posedge clk)
    begin
		  q <= d;
    end

endmodule