data/full_repos/permissive/143278/ivltests/casesynth6.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth6.v:61: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q !== 5\'d0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth6.v:71: Unsupported: Ignoring delay on this delayed statement.\n     #1 if (q !== idx[4:0]) begin\n     ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
   reg [31:0] sel;
   wire [4:0] q;

   test dut (.q(q), .sel(sel));

   integer    idx;
   integer    rept;
   reg [31:0] mask, setb;
   initial begin
      sel = 0;
      #1 if (q !== 5'd0) begin
	 $display("FAILED -- sel=%b, q=%b", sel, q);
	 $finish;
      end

      for (idx = 0 ; idx < 32 ; idx = idx+1) begin
	 mask = 32'h7fff_ffff >> idx;
	 setb = mask + 32'd1;
	 for (rept = 0 ; rept < 4 ; rept = rept+1) begin
	    sel = setb | (mask & $random);
	    #1 if (q !== idx[4:0]) begin
	       $display("FAILED -- sel=%b, q=%b, idx=%0d", sel, q, idx);
	       $finish;
	    end
	 end
      end

      $display("PASSED");
   end
endmodule
module main;

   reg [31:0] sel;
   wire [4:0] q;

   test dut (.q(q), .sel(sel));

   integer    idx;
   integer    rept;
   reg [31:0] mask, setb;
   initial begin
      sel = 0;
      #1 if (q !== 5'd0) begin
	 $display("FAILED -- sel=%b, q=%b", sel, q);
	 $finish;
      end

      for (idx = 0 ; idx < 32 ; idx = idx+1) begin
	 mask = 32'h7fff_ffff >> idx;
	 setb = mask + 32'd1;
	 for (rept = 0 ; rept < 4 ; rept = rept+1) begin
	    sel = setb | (mask & $random);
	    #1 if (q !== idx[4:0]) begin
	       $display("FAILED -- sel=%b, q=%b, idx=%0d", sel, q, idx);
	       $finish;
	    end
	 end
      end

      $display("PASSED");
   end
endmodule