data/full_repos/permissive/148324174/SeqLogic/Dlatch_tb.v
 line:36: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/Dlatch_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\nalways #1 ena = ~ena;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/Dlatch_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #0\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/Dlatch_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/Dlatch_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2.5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/Dlatch_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/Dlatch_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #7.5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/SeqLogic/Dlatch_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/148324174/SeqLogic/Dlatch_tb.v:8: Cannot find file containing module: \'DLatch\'\nDLatch Latch_U1(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/148324174/SeqLogic,data/full_repos/permissive/148324174/DLatch\n             data/full_repos/permissive/148324174/SeqLogic,data/full_repos/permissive/148324174/DLatch.v\n             data/full_repos/permissive/148324174/SeqLogic,data/full_repos/permissive/148324174/DLatch.sv\n             DLatch\n             DLatch.v\n             DLatch.sv\n             obj_dir/DLatch\n             obj_dir/DLatch.v\n             obj_dir/DLatch.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Dlatch_tb;

reg D, ena, rst, pst;
wire Qsimple, Qasyncrst, Qasyncpst;

DLatch Latch_U1(
	.D(D),
	.ena(ena),
	.rst(rst),
	.pst(pst),
	.Qsimple(Qsimple),
	.Qasyncrst(Qasyncrst),
	.Qasyncpst(Qasyncpst)
	);

always #1 ena = ~ena;

initial begin
	#0
		ena = 1'b1;
		D = 1'b0;
		rst = 1'b0;
		pst = 1'b0;
	#1
		rst = 1'b1;
		pst = 1'b1;
	#2.5
		D = 1'b1;
	#5
		rst = 1'b0;
	#7.5
		pst = 1'b0;
	#10
		$finish;
end

endmodule
module Dlatch_tb;


reg D, ena, rst, pst;
wire Qsimple, Qasyncrst, Qasyncpst;

DLatch Latch_U1(
	.D(D),
	.ena(ena),
	.rst(rst),
	.pst(pst),
	.Qsimple(Qsimple),
	.Qasyncrst(Qasyncrst),
	.Qasyncpst(Qasyncpst)
	);

always #1 ena = ~ena;

initial begin
	#0
		ena = 1'b1;
		D = 1'b0;
		rst = 1'b0;
		pst = 1'b0;
	#1
		rst = 1'b1;
		pst = 1'b1;
	#2.5
		D = 1'b1;
	#5
		rst = 1'b0;
	#7.5
		pst = 1'b0;
	#10
		$finish;
end

endmodule