data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:31: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D;  \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:39: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5)  Q <= 1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:41: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5)  Q <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:43: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5)  Q <= D;\n^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:9: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                              : ... Top module \'BUF\'\nmodule BUF(A, Y);\n       ^~~\n                                                                                              : ... Top module \'NOT\'\nmodule NOT(A, Y);\n       ^~~\n                                                                                              : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n       ^~~~\n                                                                                              : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n       ^~~\n                                                                                              : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n       ^~~\n                                                                                              : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R); \n       ^~~~~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module NOR(A, B, Y);
input A, B;
output Y;
 assign  #(1:5.1:7.5) Y = ~(A | B);
endmodule
module NOR(A, B, Y);

input A, B;
output Y;
 assign  #(1:5.1:7.5) Y = ~(A | B);
endmodule