data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/ControlUnit.v
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1: b'%Error: data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/ControlUnit.v:19: Cannot find include file: Parameters.v\n`include "Parameters.v"    \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog,data/full_repos/permissive/175780824/Parameters.v\n             data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog,data/full_repos/permissive/175780824/Parameters.v.v\n             data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog,data/full_repos/permissive/175780824/Parameters.v.sv\n             Parameters.v\n             Parameters.v.v\n             Parameters.v.sv\n             obj_dir/Parameters.v\n             obj_dir/Parameters.v.v\n             obj_dir/Parameters.v.sv\n%Error: Exiting due to 1 error(s)\n'
module ControlUnit(
    input wire [6:0] Op,
    input wire [2:0] Fn3,
    input wire [6:0] Fn7,
    output wire JalD,
    output wire JalrD,
    output reg [2:0] RegWriteD,
    output wire MemToRegD,
    output reg [3:0] MemWriteD,
    output wire LoadNpcD,
    output wire BranchD,
    output reg [4:0] AluContrlD,
    output wire [1:0] AluSrc2D,
    output wire AluSrc1D,
    output reg [2:0] ImmType        
    );

`include "Parameters.v"   

    assign LoadNpcD = JalD | JalrD;
    assign JalD = (Op==7'b1101111)?1'b1:1'b0;
    assign JalrD = (Op==7'b1100111)?1'b1:1'b0;
    assign BranchD = (Op==7'b1100011)?1'b1:1'b0;
    assign MemToRegD = (Op==7'b0000011)?1'b1:1'b0;
    assign AluSrc1D = (Op==7'b0010111)?1'b1:1'b0;

    assign AluSrc2D = ( (Op==7'b0010011)&&(Fn3[1:0]==2'b01) )?(2'b01):(((Op==7'b0110011)||(Op==7'b1100011))?2'b00:2'b10);

    always@(*)
    case(Op)
        7'b0010011:begin
            RegWriteD<=LW;
            MemWriteD<=4'b0000;
            ImmType<=ITYPE;
            case(Fn3)
                3'b000:AluContrlD<=ADD;
                3'b001:AluContrlD<=SLL;
                3'b010:AluContrlD<=SLT;
                3'b011:AluContrlD<=SLTU;
                3'b100:AluContrlD<=XOR;
                3'b101:
                    if(Fn7[5]==1)
                        AluContrlD<=SRA;
                    else
                        AluContrlD<=SRL;
                3'b110:AluContrlD<=OR;
                default:AluContrlD<=AND;
            endcase
        end
        7'b0110011:begin
            RegWriteD<=LW;
            MemWriteD<=4'b0000;
            ImmType<=ITYPE;
            case(Fn3)
                3'b000:begin
                    if(Fn7[5]==1)
                        AluContrlD<=SUB;
                    else
                        AluContrlD<=ADD;
                end
                3'b001:AluContrlD<=SLL;
                3'b010:AluContrlD<=SLT;
                3'b011:AluContrlD<=SLTU;
                3'b100:AluContrlD<=XOR;
                3'b101:begin
                    if(Fn7[5]==1)
                        AluContrlD<=SRA;
                    else
                        AluContrlD<=SRL;
                end  
                3'b110:AluContrlD<=OR;
                default:AluContrlD<=AND;
            endcase
        end
        7'b0000011:begin
            MemWriteD<=4'b0000;
            AluContrlD<=ADD;
            ImmType<=ITYPE;
            case(Fn3)
                3'b000:RegWriteD<=LB;
                3'b001:RegWriteD<=LH;
                3'b010:RegWriteD<=LW;
                3'b100:RegWriteD<=LBU;
                default:RegWriteD<=LHU;
            endcase
        end
        7'b0100011:begin
            RegWriteD<=NOREGWRITE;
            AluContrlD<=ADD;
            ImmType<=STYPE; 
            case(Fn3)
                3'b000:MemWriteD<=4'b0001;
                3'b001:MemWriteD<=4'b0011;
                default:MemWriteD<=4'b1111;
            endcase
        end
        7'b0110111:begin
        RegWriteD<=LW;
        MemWriteD<=4'b0000;
        AluContrlD<=LUI;
        ImmType<=UTYPE;     
        end 
        7'b0010111:begin
        RegWriteD<=3'd3;
        MemWriteD<=4'b0000;
        AluContrlD<=ADD;
        ImmType<=UTYPE;
        end
        7'b1101111:begin
        RegWriteD<=LW;
        MemWriteD<=4'b0000;
        AluContrlD<=ADD;
        ImmType<=JTYPE;       
        end
        7'b1100111:begin
        RegWriteD<=LW;
        MemWriteD<=4'b0000;
        AluContrlD<=ADD;
        ImmType<=ITYPE;         
        end
        7'b1100011:begin
            RegWriteD<=NOREGWRITE;
            MemWriteD<=4'b0000;
            ImmType<=BTYPE;
            case(Fn3)
                3'b000:AluContrlD<=BEQ;
                3'b001:AluContrlD<=BNE;
                3'b100:AluContrlD<=BLT;
                3'b101:AluContrlD<=BGE;
                3'b110:AluContrlD<=BLTU;
                default:AluContrlD<=BGEU;
            endcase
        end
        default:begin
        RegWriteD<=NOREGWRITE;
        MemWriteD<=4'b0000;
        AluContrlD<=ADD;
        ImmType<=ITYPE;
        end
    endcase
    
endmodule
module ControlUnit(
    input wire [6:0] Op,
    input wire [2:0] Fn3,
    input wire [6:0] Fn7,
    output wire JalD,
    output wire JalrD,
    output reg [2:0] RegWriteD,
    output wire MemToRegD,
    output reg [3:0] MemWriteD,
    output wire LoadNpcD,
    output wire BranchD,
    output reg [4:0] AluContrlD,
    output wire [1:0] AluSrc2D,
    output wire AluSrc1D,
    output reg [2:0] ImmType        
    );


`include "Parameters.v"   

    assign LoadNpcD = JalD | JalrD;
    assign JalD = (Op==7'b1101111)?1'b1:1'b0;
    assign JalrD = (Op==7'b1100111)?1'b1:1'b0;
    assign BranchD = (Op==7'b1100011)?1'b1:1'b0;
    assign MemToRegD = (Op==7'b0000011)?1'b1:1'b0;
    assign AluSrc1D = (Op==7'b0010111)?1'b1:1'b0;

    assign AluSrc2D = ( (Op==7'b0010011)&&(Fn3[1:0]==2'b01) )?(2'b01):(((Op==7'b0110011)||(Op==7'b1100011))?2'b00:2'b10);

    always@(*)
    case(Op)
        7'b0010011:begin
            RegWriteD<=LW;
            MemWriteD<=4'b0000;
            ImmType<=ITYPE;
            case(Fn3)
                3'b000:AluContrlD<=ADD;
                3'b001:AluContrlD<=SLL;
                3'b010:AluContrlD<=SLT;
                3'b011:AluContrlD<=SLTU;
                3'b100:AluContrlD<=XOR;
                3'b101:
                    if(Fn7[5]==1)
                        AluContrlD<=SRA;
                    else
                        AluContrlD<=SRL;
                3'b110:AluContrlD<=OR;
                default:AluContrlD<=AND;
            endcase
        end
        7'b0110011:begin
            RegWriteD<=LW;
            MemWriteD<=4'b0000;
            ImmType<=ITYPE;
            case(Fn3)
                3'b000:begin
                    if(Fn7[5]==1)
                        AluContrlD<=SUB;
                    else
                        AluContrlD<=ADD;
                end
                3'b001:AluContrlD<=SLL;
                3'b010:AluContrlD<=SLT;
                3'b011:AluContrlD<=SLTU;
                3'b100:AluContrlD<=XOR;
                3'b101:begin
                    if(Fn7[5]==1)
                        AluContrlD<=SRA;
                    else
                        AluContrlD<=SRL;
                end  
                3'b110:AluContrlD<=OR;
                default:AluContrlD<=AND;
            endcase
        end
        7'b0000011:begin
            MemWriteD<=4'b0000;
            AluContrlD<=ADD;
            ImmType<=ITYPE;
            case(Fn3)
                3'b000:RegWriteD<=LB;
                3'b001:RegWriteD<=LH;
                3'b010:RegWriteD<=LW;
                3'b100:RegWriteD<=LBU;
                default:RegWriteD<=LHU;
            endcase
        end
        7'b0100011:begin
            RegWriteD<=NOREGWRITE;
            AluContrlD<=ADD;
            ImmType<=STYPE; 
            case(Fn3)
                3'b000:MemWriteD<=4'b0001;
                3'b001:MemWriteD<=4'b0011;
                default:MemWriteD<=4'b1111;
            endcase
        end
        7'b0110111:begin
        RegWriteD<=LW;
        MemWriteD<=4'b0000;
        AluContrlD<=LUI;
        ImmType<=UTYPE;     
        end 
        7'b0010111:begin
        RegWriteD<=3'd3;
        MemWriteD<=4'b0000;
        AluContrlD<=ADD;
        ImmType<=UTYPE;
        end
        7'b1101111:begin
        RegWriteD<=LW;
        MemWriteD<=4'b0000;
        AluContrlD<=ADD;
        ImmType<=JTYPE;       
        end
        7'b1100111:begin
        RegWriteD<=LW;
        MemWriteD<=4'b0000;
        AluContrlD<=ADD;
        ImmType<=ITYPE;         
        end
        7'b1100011:begin
            RegWriteD<=NOREGWRITE;
            MemWriteD<=4'b0000;
            ImmType<=BTYPE;
            case(Fn3)
                3'b000:AluContrlD<=BEQ;
                3'b001:AluContrlD<=BNE;
                3'b100:AluContrlD<=BLT;
                3'b101:AluContrlD<=BGE;
                3'b110:AluContrlD<=BLTU;
                default:AluContrlD<=BGEU;
            endcase
        end
        default:begin
        RegWriteD<=NOREGWRITE;
        MemWriteD<=4'b0000;
        AluContrlD<=ADD;
        ImmType<=ITYPE;
        end
    endcase
    
endmodule