data/full_repos/permissive/128659832/verilog/hrmcpu.v
 line:29 column:21: Illegal character "'"
1: b"%Error: data/full_repos/permissive/128659832/verilog/hrmcpu.v:68: Cannot find file containing module: 'ControlUnit'\n    ControlUnit ControlUnit0 (\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128659832/verilog,data/full_repos/permissive/128659832/ControlUnit\n             data/full_repos/permissive/128659832/verilog,data/full_repos/permissive/128659832/ControlUnit.v\n             data/full_repos/permissive/128659832/verilog,data/full_repos/permissive/128659832/ControlUnit.sv\n             ControlUnit\n             ControlUnit.v\n             ControlUnit.sv\n             obj_dir/ControlUnit\n             obj_dir/ControlUnit.v\n             obj_dir/ControlUnit.sv\n%Error: data/full_repos/permissive/128659832/verilog/hrmcpu.v:119: Cannot find file containing module: 'PC'\n    PC PC0 (\n    ^~\n%Error: data/full_repos/permissive/128659832/verilog/hrmcpu.v:150: Cannot find file containing module: 'PROG'\n    PROG program0 (\n    ^~~~\n%Error: data/full_repos/permissive/128659832/verilog/hrmcpu.v:177: Cannot find file containing module: 'IR'\n    IR IR0 (\n    ^~\n%Error: data/full_repos/permissive/128659832/verilog/hrmcpu.v:206: Cannot find file containing module: 'REG'\n    REG register0 (\n    ^~~\n%Error: data/full_repos/permissive/128659832/verilog/hrmcpu.v:242: Cannot find file containing module: 'MEMORY'\n    MEMORY MEMORY0 (\n    ^~~~~~\n%Error: data/full_repos/permissive/128659832/verilog/hrmcpu.v:277: Cannot find file containing module: 'ALU'\n    ALU alu0 (\n    ^~~\n%Error: data/full_repos/permissive/128659832/verilog/hrmcpu.v:300: Cannot find file containing module: 'WAIT'\n    WAIT WAIT0 (\n    ^~~~\n%Error: data/full_repos/permissive/128659832/verilog/hrmcpu.v:329: Cannot find file containing module: 'ufifo'\n    ufifo #(.LGFLEN(4'd5)) INBOX (\n    ^~~~~\n%Error: data/full_repos/permissive/128659832/verilog/hrmcpu.v:374: Cannot find file containing module: 'ufifo'\n    ufifo #(.LGFLEN(4'd5)) OUTB (\n    ^~~~~\n%Error: Exiting due to 10 error(s)\n"
module hrmcpu (

    input  wire       cpu_debug,
    input  wire       cpu_hold,
    input  wire       cpu_nxtInstr,
    input  wire [7:0] cpu_in_data,
    input  wire       cpu_in_wr,
    input  wire       cpu_out_rd,
    input  wire [2:0] cpu_dmp_chip_select,
    input  wire [4:0] cpu_dmp_fifo_pos,


    output reg        cpu_in_full,
    output reg        cpu_out_empty,
    output reg  [7:0] cpu_out_data,
    output reg  [7:0] cpu_dmp_data,
    output reg        cpu_dmp_valid,
    output reg  [7:0] cpu_o_leds,


    input wire clk,
    input wire i_rst
);


    localparam
    m_INBOX     = 3'd 0,
    m_OUTBOX    = 3'd 1,
    m_PC        = 3'd 2,
    m_RAM       = 3'd 3,
    m_REG       = 3'd 4,
    m_INSTR     = 3'd 5,
    m_STATE     = 3'd 6;


    parameter PROGRAM = "dummy_prg.hex";
    parameter ROMFILE = "dummy_ram.hex";




    wire [7:0] cu_INSTR;
    wire       cu_inEmpty;
    wire       cu_outFull;
    wire       cu_debug;
    wire       cu_nxtInstr;
    wire       cu_timer_busy;

    wire       cu_wIR;
    wire [1:0] cu_muxR;
    wire       cu_wR;
    wire       cu_srcA;
    wire       cu_wM;
    wire       cu_wAR;
    wire [2:0] cu_aluCtl;
    wire       cu_wPC;
    wire       cu_rIn;
    wire       cu_wO;
    wire       cu_ijump;
    wire       cu_branch;
    wire       cu_rst;
    wire       cu_halt;
    wire       cu_enT;
    wire [4:0] cu_dmp_state;

    ControlUnit ControlUnit0 (

        .INSTR(cu_INSTR),
        .inEmpty(cu_inEmpty),
        .outFull(cu_outFull),
        .debug(cu_debug),
        .nxtInstr(cu_nxtInstr),
        .busy(cu_timer_busy),

        .wIR(cu_wIR),
        .muxR(cu_muxR),
        .wR(cu_wR),
        .srcA(cu_srcA),
        .wM(cu_wM),
        .wAR(cu_wAR),
        .aluCtl(cu_aluCtl),
        .wPC(cu_wPC),
        .rIn(cu_rIn),
        .wO(cu_wO),
        .ijump(cu_ijump),
        .branch(cu_branch),
        .rst(cu_rst),
        .halt(cu_halt),
        .enT(cu_enT),
        .dmp_state(cu_dmp_state),

        .clk(clk & ~cpu_hold),
        .i_rst(i_rst)
    );


    assign cu_INSTR = IR0_rIR;
    assign cu_inEmpty = ~ INBOX_empty_n;
    assign cu_outFull = OUTB_full;
    assign cu_debug = cpu_debug;
    assign cu_nxtInstr = cpu_nxtInstr;
    assign cu_timer_busy = timer_busy;





    wire       PC0_rst;
    wire       PC0_branch;
    wire       PC0_ijump;
    wire       PC0_aluFlag;
    wire       PC0_wPC;

    wire [7:0] PC0_jmpAddr;
    wire [7:0] PC0_PC;

    PC PC0 (

        .jmpAddr(PC0_jmpAddr),
        .branch(PC0_branch),
        .ijump(PC0_ijump),
        .aluFlag(PC0_aluFlag),
        .wPC(PC0_wPC),

        .PC(PC0_PC),

        .clk(clk),
        .rst(PC0_rst)
    );


    assign PC0_rst = cu_rst;
    assign PC0_branch = cu_branch;
    assign PC0_ijump = cu_ijump;
    assign PC0_jmpAddr = program0_Data;
    assign PC0_aluFlag = alu_flag;
    assign PC0_wPC = cu_wPC;





    wire [7:0] program0_Addr;
    wire [7:0] i_program0_din;
    wire       i_program0_write_en;
    wire [7:0] program0_Data;

    PROG program0 (

        .Addr    (program0_Addr    ),
        .din     (i_program0_din     ),
        .write_en(i_program0_write_en),
        .clk     (clk     ),

        .Data    (program0_Data    )
    );

    defparam program0.addr_width = 8;
    defparam program0.data_width = 8;
    defparam program0.PROGRAM = PROGRAM;

    assign program0_Addr     = PC0_PC ;
    assign i_program0_din      = 8'b 0 ;
    assign i_program0_write_en = 1'b 0 ;





    wire [7:0] IR0_nIR;
    wire       IR0_wIR;
    wire [7:0] IR0_rIR;
    wire       IR0_rst;

    IR IR0 (

        .wIR(IR0_wIR),
        .nIR(IR0_nIR),
        .rst(IR0_rst),

        .rIR(IR0_rIR),

        .clk(clk)
    );

    assign IR0_nIR = program0_Data;
    assign IR0_wIR = cu_wIR;
    assign IR0_rst = cu_rst;





    wire signed [7:0] R_iInbox;
    wire signed [7:0] R_iAlu;
    wire signed [7:0] R_iMem;
    wire signed [7:0] R_iData;
    wire        [1:0] R_muxR;
    wire              R_wR;
    wire              R_rst;

    wire signed [7:0] R_value;

    REG register0 (

        .iInbox(R_iInbox),
        .iAlu(R_iAlu),
        .iMem(R_iMem),
        .iData(R_iData),
        .muxR(R_muxR),
        .wR(R_wR),
        .rst(R_rst),

        .R(R_value),

        .clk(clk)
    );

    assign R_iInbox = INBOX_o_data;
    assign R_iAlu = alu_Out;
    assign R_iMem = mem_M;
    assign R_iData = program0_Data;
    assign R_muxR = cu_muxR;
    assign R_wR = cu_wR;
    assign R_rst = cu_rst;





    wire        [7:0] mem_ADDR;
    wire        [7:0] mem_R;
    wire              mem_srcA;
    wire              mem_wM;
    wire              mem_wAR;
    wire              mem_mmio;
    wire signed [7:0] mem_M;
    wire        [7:0] mem_o_leds;

    MEMORY MEMORY0 (

        .ADDR(mem_ADDR),
        .R(mem_R),
        .srcA(mem_srcA),
        .wM(mem_wM),
        .wAR(mem_wAR),
        .mmio(mem_mmio),

        .M(mem_M),
        .o_leds(mem_o_leds),

        .rst(cu_rst),
        .clk(clk)
    );
    defparam MEMORY0.ROMFILE = ROMFILE;


    assign mem_ADDR = program0_Data;
    assign mem_R = R_value;
    assign mem_srcA = cu_srcA;
    assign mem_wM = cu_wM;
    assign mem_wAR = cu_wAR;
    assign mem_mmio = IR0_rIR[0:0];





    wire        [2:0] alu_Ctl;
    wire signed [7:0] alu_inR;
    wire signed [7:0] alu_inM;
    wire signed [7:0] alu_Out;
    wire              alu_flag;

    ALU alu0 (

        .aluCtl( alu_Ctl ),
        .inR( alu_inR ),
        .inM( alu_inM ),

        .aluOut( alu_Out ),
        .flag( alu_flag )
    );

    assign alu_Ctl = cu_aluCtl;
    assign alu_inR = R_value;
    assign alu_inM = mem_M;





    wire [7:0] timer_din;
    wire timer_start;
    wire timer_busy;
    wire timer_rst;

    WAIT WAIT0 (
        .din(timer_din),
        .start(timer_start),
        .busy(timer_busy),
        .clk(clk),
        .rst(timer_rst)
    );

    assign timer_din = program0_Data;
    assign timer_start = cu_enT;
    assign timer_rst = cu_rst;





    wire              INBOX_i_wr;
    wire signed [7:0] INBOX_i_data;
    wire              INBOX_i_rd;
    wire signed [7:0] INBOX_o_data;
    wire              INBOX_empty_n;
    wire              INBOX_full;
    wire              INBOX_i_rst;

    wire        [4:0] INBOX_i_dmp_pos;
    wire        [7:0] INBOX_o_dmp_data;
    wire              INBOX_o_dmp_valid;


    ufifo #(.LGFLEN(4'd5)) INBOX (

        .i_wr(INBOX_i_wr),
        .i_data(INBOX_i_data),

        .i_rd(INBOX_i_rd),
        .o_data(INBOX_o_data),

        .o_empty_n( INBOX_empty_n ),
        .o_full( INBOX_full ),


        .i_dmp_pos(INBOX_i_dmp_pos),
        .o_dmp_data(INBOX_o_dmp_data),
        .o_dmp_valid(INBOX_o_dmp_valid),

        .i_rst(INBOX_i_rst),
        .i_clk(clk)
    );

    defparam INBOX.RXFIFO=1'b1;

    assign INBOX_i_data = cpu_in_data;
    assign INBOX_i_wr = cpu_in_wr;
    assign INBOX_i_rd = cu_rIn;
    assign INBOX_i_rst = cu_rst;
    assign INBOX_i_dmp_pos = cpu_dmp_fifo_pos;





    wire              OUTB_i_wr;
    wire signed [7:0] OUTB_i_data;
    wire              OUTB_i_rd;
    wire signed [7:0] OUTB_o_data;
    wire              OUTB_empty_n;
    wire              OUTB_full;
    wire              OUTB_i_rst;

    wire        [4:0] OUTB_i_dmp_pos;
    wire        [7:0] OUTB_o_dmp_data;
    wire              OUTB_o_dmp_valid;


    ufifo #(.LGFLEN(4'd5)) OUTB (

        .i_wr(OUTB_i_wr),
        .i_data(OUTB_i_data),

        .i_rd(OUTB_i_rd),
        .o_data(OUTB_o_data),

        .o_empty_n( OUTB_empty_n ),
        .o_full( OUTB_full ),


        .i_dmp_pos(OUTB_i_dmp_pos),
        .o_dmp_data(OUTB_o_dmp_data),
        .o_dmp_valid(OUTB_o_dmp_valid),
        .i_rst(OUTB_i_rst),
        .i_clk(clk)
    );

    defparam OUTB.RXFIFO=1'b1;

    assign OUTB_i_data = R_value;
    assign OUTB_i_wr = cu_wO;
    assign OUTB_i_rd = cpu_out_rd;
    assign OUTB_i_rst = cu_rst;
    assign OUTB_i_dmp_pos = cpu_dmp_fifo_pos;





    always @(*)
    begin
        cpu_out_data = OUTB_o_data;
        cpu_out_empty = ~ OUTB_empty_n;
        cpu_in_full = INBOX_full;
        cpu_o_leds = mem_o_leds;
    end




    always @*
    begin
        cpu_dmp_data  = 8'b x;
        cpu_dmp_valid = 1'b 1;

        case (cpu_dmp_chip_select)
            m_INBOX  : begin
                cpu_dmp_data  = INBOX_o_dmp_data;
                cpu_dmp_valid = INBOX_o_dmp_valid;
            end
            m_OUTBOX  : begin
                cpu_dmp_data  = OUTB_o_dmp_data;
                cpu_dmp_valid = OUTB_o_dmp_valid;
            end
            m_RAM  : begin
                cpu_dmp_data  = 8'b 00;
                cpu_dmp_valid = 1'b 0;
            end
            m_PC     : cpu_dmp_data  = PC0_PC;
            m_INSTR  : cpu_dmp_data  = IR0_rIR;
            m_REG    : cpu_dmp_data  = R_value;
            m_STATE  : cpu_dmp_data  = {3'b0, cu_dmp_state };
            default  : cpu_dmp_data  = PC0_PC;
        endcase
    end


endmodule
module hrmcpu (

    input  wire       cpu_debug,
    input  wire       cpu_hold,
    input  wire       cpu_nxtInstr,
    input  wire [7:0] cpu_in_data,
    input  wire       cpu_in_wr,
    input  wire       cpu_out_rd,
    input  wire [2:0] cpu_dmp_chip_select,
    input  wire [4:0] cpu_dmp_fifo_pos,


    output reg        cpu_in_full,
    output reg        cpu_out_empty,
    output reg  [7:0] cpu_out_data,
    output reg  [7:0] cpu_dmp_data,
    output reg        cpu_dmp_valid,
    output reg  [7:0] cpu_o_leds,


    input wire clk,
    input wire i_rst
);



    localparam
    m_INBOX     = 3'd 0,
    m_OUTBOX    = 3'd 1,
    m_PC        = 3'd 2,
    m_RAM       = 3'd 3,
    m_REG       = 3'd 4,
    m_INSTR     = 3'd 5,
    m_STATE     = 3'd 6;


    parameter PROGRAM = "dummy_prg.hex";
    parameter ROMFILE = "dummy_ram.hex";




    wire [7:0] cu_INSTR;
    wire       cu_inEmpty;
    wire       cu_outFull;
    wire       cu_debug;
    wire       cu_nxtInstr;
    wire       cu_timer_busy;

    wire       cu_wIR;
    wire [1:0] cu_muxR;
    wire       cu_wR;
    wire       cu_srcA;
    wire       cu_wM;
    wire       cu_wAR;
    wire [2:0] cu_aluCtl;
    wire       cu_wPC;
    wire       cu_rIn;
    wire       cu_wO;
    wire       cu_ijump;
    wire       cu_branch;
    wire       cu_rst;
    wire       cu_halt;
    wire       cu_enT;
    wire [4:0] cu_dmp_state;

    ControlUnit ControlUnit0 (

        .INSTR(cu_INSTR),
        .inEmpty(cu_inEmpty),
        .outFull(cu_outFull),
        .debug(cu_debug),
        .nxtInstr(cu_nxtInstr),
        .busy(cu_timer_busy),

        .wIR(cu_wIR),
        .muxR(cu_muxR),
        .wR(cu_wR),
        .srcA(cu_srcA),
        .wM(cu_wM),
        .wAR(cu_wAR),
        .aluCtl(cu_aluCtl),
        .wPC(cu_wPC),
        .rIn(cu_rIn),
        .wO(cu_wO),
        .ijump(cu_ijump),
        .branch(cu_branch),
        .rst(cu_rst),
        .halt(cu_halt),
        .enT(cu_enT),
        .dmp_state(cu_dmp_state),

        .clk(clk & ~cpu_hold),
        .i_rst(i_rst)
    );


    assign cu_INSTR = IR0_rIR;
    assign cu_inEmpty = ~ INBOX_empty_n;
    assign cu_outFull = OUTB_full;
    assign cu_debug = cpu_debug;
    assign cu_nxtInstr = cpu_nxtInstr;
    assign cu_timer_busy = timer_busy;





    wire       PC0_rst;
    wire       PC0_branch;
    wire       PC0_ijump;
    wire       PC0_aluFlag;
    wire       PC0_wPC;

    wire [7:0] PC0_jmpAddr;
    wire [7:0] PC0_PC;

    PC PC0 (

        .jmpAddr(PC0_jmpAddr),
        .branch(PC0_branch),
        .ijump(PC0_ijump),
        .aluFlag(PC0_aluFlag),
        .wPC(PC0_wPC),

        .PC(PC0_PC),

        .clk(clk),
        .rst(PC0_rst)
    );


    assign PC0_rst = cu_rst;
    assign PC0_branch = cu_branch;
    assign PC0_ijump = cu_ijump;
    assign PC0_jmpAddr = program0_Data;
    assign PC0_aluFlag = alu_flag;
    assign PC0_wPC = cu_wPC;





    wire [7:0] program0_Addr;
    wire [7:0] i_program0_din;
    wire       i_program0_write_en;
    wire [7:0] program0_Data;

    PROG program0 (

        .Addr    (program0_Addr    ),
        .din     (i_program0_din     ),
        .write_en(i_program0_write_en),
        .clk     (clk     ),

        .Data    (program0_Data    )
    );

    defparam program0.addr_width = 8;
    defparam program0.data_width = 8;
    defparam program0.PROGRAM = PROGRAM;

    assign program0_Addr     = PC0_PC ;
    assign i_program0_din      = 8'b 0 ;
    assign i_program0_write_en = 1'b 0 ;





    wire [7:0] IR0_nIR;
    wire       IR0_wIR;
    wire [7:0] IR0_rIR;
    wire       IR0_rst;

    IR IR0 (

        .wIR(IR0_wIR),
        .nIR(IR0_nIR),
        .rst(IR0_rst),

        .rIR(IR0_rIR),

        .clk(clk)
    );

    assign IR0_nIR = program0_Data;
    assign IR0_wIR = cu_wIR;
    assign IR0_rst = cu_rst;





    wire signed [7:0] R_iInbox;
    wire signed [7:0] R_iAlu;
    wire signed [7:0] R_iMem;
    wire signed [7:0] R_iData;
    wire        [1:0] R_muxR;
    wire              R_wR;
    wire              R_rst;

    wire signed [7:0] R_value;

    REG register0 (

        .iInbox(R_iInbox),
        .iAlu(R_iAlu),
        .iMem(R_iMem),
        .iData(R_iData),
        .muxR(R_muxR),
        .wR(R_wR),
        .rst(R_rst),

        .R(R_value),

        .clk(clk)
    );

    assign R_iInbox = INBOX_o_data;
    assign R_iAlu = alu_Out;
    assign R_iMem = mem_M;
    assign R_iData = program0_Data;
    assign R_muxR = cu_muxR;
    assign R_wR = cu_wR;
    assign R_rst = cu_rst;





    wire        [7:0] mem_ADDR;
    wire        [7:0] mem_R;
    wire              mem_srcA;
    wire              mem_wM;
    wire              mem_wAR;
    wire              mem_mmio;
    wire signed [7:0] mem_M;
    wire        [7:0] mem_o_leds;

    MEMORY MEMORY0 (

        .ADDR(mem_ADDR),
        .R(mem_R),
        .srcA(mem_srcA),
        .wM(mem_wM),
        .wAR(mem_wAR),
        .mmio(mem_mmio),

        .M(mem_M),
        .o_leds(mem_o_leds),

        .rst(cu_rst),
        .clk(clk)
    );
    defparam MEMORY0.ROMFILE = ROMFILE;


    assign mem_ADDR = program0_Data;
    assign mem_R = R_value;
    assign mem_srcA = cu_srcA;
    assign mem_wM = cu_wM;
    assign mem_wAR = cu_wAR;
    assign mem_mmio = IR0_rIR[0:0];





    wire        [2:0] alu_Ctl;
    wire signed [7:0] alu_inR;
    wire signed [7:0] alu_inM;
    wire signed [7:0] alu_Out;
    wire              alu_flag;

    ALU alu0 (

        .aluCtl( alu_Ctl ),
        .inR( alu_inR ),
        .inM( alu_inM ),

        .aluOut( alu_Out ),
        .flag( alu_flag )
    );

    assign alu_Ctl = cu_aluCtl;
    assign alu_inR = R_value;
    assign alu_inM = mem_M;





    wire [7:0] timer_din;
    wire timer_start;
    wire timer_busy;
    wire timer_rst;

    WAIT WAIT0 (
        .din(timer_din),
        .start(timer_start),
        .busy(timer_busy),
        .clk(clk),
        .rst(timer_rst)
    );

    assign timer_din = program0_Data;
    assign timer_start = cu_enT;
    assign timer_rst = cu_rst;





    wire              INBOX_i_wr;
    wire signed [7:0] INBOX_i_data;
    wire              INBOX_i_rd;
    wire signed [7:0] INBOX_o_data;
    wire              INBOX_empty_n;
    wire              INBOX_full;
    wire              INBOX_i_rst;

    wire        [4:0] INBOX_i_dmp_pos;
    wire        [7:0] INBOX_o_dmp_data;
    wire              INBOX_o_dmp_valid;


    ufifo #(.LGFLEN(4'd5)) INBOX (

        .i_wr(INBOX_i_wr),
        .i_data(INBOX_i_data),

        .i_rd(INBOX_i_rd),
        .o_data(INBOX_o_data),

        .o_empty_n( INBOX_empty_n ),
        .o_full( INBOX_full ),


        .i_dmp_pos(INBOX_i_dmp_pos),
        .o_dmp_data(INBOX_o_dmp_data),
        .o_dmp_valid(INBOX_o_dmp_valid),

        .i_rst(INBOX_i_rst),
        .i_clk(clk)
    );

    defparam INBOX.RXFIFO=1'b1;

    assign INBOX_i_data = cpu_in_data;
    assign INBOX_i_wr = cpu_in_wr;
    assign INBOX_i_rd = cu_rIn;
    assign INBOX_i_rst = cu_rst;
    assign INBOX_i_dmp_pos = cpu_dmp_fifo_pos;





    wire              OUTB_i_wr;
    wire signed [7:0] OUTB_i_data;
    wire              OUTB_i_rd;
    wire signed [7:0] OUTB_o_data;
    wire              OUTB_empty_n;
    wire              OUTB_full;
    wire              OUTB_i_rst;

    wire        [4:0] OUTB_i_dmp_pos;
    wire        [7:0] OUTB_o_dmp_data;
    wire              OUTB_o_dmp_valid;


    ufifo #(.LGFLEN(4'd5)) OUTB (

        .i_wr(OUTB_i_wr),
        .i_data(OUTB_i_data),

        .i_rd(OUTB_i_rd),
        .o_data(OUTB_o_data),

        .o_empty_n( OUTB_empty_n ),
        .o_full( OUTB_full ),


        .i_dmp_pos(OUTB_i_dmp_pos),
        .o_dmp_data(OUTB_o_dmp_data),
        .o_dmp_valid(OUTB_o_dmp_valid),
        .i_rst(OUTB_i_rst),
        .i_clk(clk)
    );

    defparam OUTB.RXFIFO=1'b1;

    assign OUTB_i_data = R_value;
    assign OUTB_i_wr = cu_wO;
    assign OUTB_i_rd = cpu_out_rd;
    assign OUTB_i_rst = cu_rst;
    assign OUTB_i_dmp_pos = cpu_dmp_fifo_pos;





    always @(*)
    begin
        cpu_out_data = OUTB_o_data;
        cpu_out_empty = ~ OUTB_empty_n;
        cpu_in_full = INBOX_full;
        cpu_o_leds = mem_o_leds;
    end




    always @*
    begin
        cpu_dmp_data  = 8'b x;
        cpu_dmp_valid = 1'b 1;

        case (cpu_dmp_chip_select)
            m_INBOX  : begin
                cpu_dmp_data  = INBOX_o_dmp_data;
                cpu_dmp_valid = INBOX_o_dmp_valid;
            end
            m_OUTBOX  : begin
                cpu_dmp_data  = OUTB_o_dmp_data;
                cpu_dmp_valid = OUTB_o_dmp_valid;
            end
            m_RAM  : begin
                cpu_dmp_data  = 8'b 00;
                cpu_dmp_valid = 1'b 0;
            end
            m_PC     : cpu_dmp_data  = PC0_PC;
            m_INSTR  : cpu_dmp_data  = IR0_rIR;
            m_REG    : cpu_dmp_data  = R_value;
            m_STATE  : cpu_dmp_data  = {3'b0, cu_dmp_state };
            default  : cpu_dmp_data  = PC0_PC;
        endcase
    end


endmodule