data/full_repos/permissive/174783592/IFU/inc16bit.sv
1: b'%Error: data/full_repos/permissive/174783592/IFU/inc16bit.sv:2: Cannot find include file: inc4bit.sv\n`include "inc4bit.sv" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174783592/IFU,data/full_repos/permissive/174783592/inc4bit.sv\n             data/full_repos/permissive/174783592/IFU,data/full_repos/permissive/174783592/inc4bit.sv.v\n             data/full_repos/permissive/174783592/IFU,data/full_repos/permissive/174783592/inc4bit.sv.sv\n             inc4bit.sv\n             inc4bit.sv.v\n             inc4bit.sv.sv\n             obj_dir/inc4bit.sv\n             obj_dir/inc4bit.sv.v\n             obj_dir/inc4bit.sv.sv\n%Error: Exiting due to 1 error(s)\n'
module inc16bit(pc,pcwire,clk);
	input [15:0]pc;
	input clk;
	output  [15:0] pcwire;
	

	wire [3:0] lwire [3:0];
	reg [3:0] outwire[3:0];
	wire [3:0] temp;
	wire [3:0] temp2;
	wire [15:0] temp3;
	wire [15:0] temp4;
	integer i;
	wire [2:0]j;
	assign lwire [0] = pc[3:0];
	assign lwire [1] = pc[7:4];
	assign lwire [2] = pc[11:8];
	assign lwire [3] = pc[15:12];	





	wire [3:0]incb;
	wire [3:0]inca;
	wire [2:0] zeropos;

	assign incb[0] = pc[3] & pc[2] & pc[1] & pc[0];
	assign incb[1] = pc[7] & pc[6] & pc[5] & pc[4];
	assign incb[2] = pc[11] & pc[10] & pc[9] & pc[8];
	assign incb[3]= pc[15] & pc[14] & pc[13] & pc[12];
	
	assign zeropos[0] =  (~incb[1]&incb[0]);
	assign zeropos[1] = ~incb[2] & incb[1] & incb[0]; 
	assign zeropos[2] = incb[2] & incb[1] & incb[0]; 
	
	inc4bit inc(lwire[zeropos],temp);

	assign j = zeropos;



	assign temp2 = 4'b1111 << j;

	
	assign temp4[15] = pc[15] & temp2[3];
	assign temp4[14] = pc[14] & temp2[3];
	assign temp4[13] = pc[13] & temp2[3];
	assign temp4[12] = pc[12] & temp2[3];

	assign temp4[11] = pc[11] & temp2[2];
	assign temp4[10] = pc[10] & temp2[2];
	assign temp4[9] = pc[9] & temp2[2];
	assign temp4[8] = pc[8] & temp2[2];

	assign temp4[7] = pc[7] & temp2[1];
	assign temp4[6] = pc[6] & temp2[1];
	assign temp4[5] = pc[5] & temp2[1];
	assign temp4[4] = pc[4] & temp2[1];

	assign temp4[3] = pc[3] & temp2[0];
	assign temp4[2] = pc[2] & temp2[0];
	assign temp4[1] = pc[1] & temp2[0];
	assign temp4[0] = pc[0] & temp2[0];






	assign temp3 = temp << (4*j);



	assign pcwire = temp4 | temp3;







		





	
















endmodule
module inc16bit(pc,pcwire,clk);

	input [15:0]pc;
	input clk;
	output  [15:0] pcwire;
	

	wire [3:0] lwire [3:0];
	reg [3:0] outwire[3:0];
	wire [3:0] temp;
	wire [3:0] temp2;
	wire [15:0] temp3;
	wire [15:0] temp4;
	integer i;
	wire [2:0]j;
	assign lwire [0] = pc[3:0];
	assign lwire [1] = pc[7:4];
	assign lwire [2] = pc[11:8];
	assign lwire [3] = pc[15:12];	





	wire [3:0]incb;
	wire [3:0]inca;
	wire [2:0] zeropos;

	assign incb[0] = pc[3] & pc[2] & pc[1] & pc[0];
	assign incb[1] = pc[7] & pc[6] & pc[5] & pc[4];
	assign incb[2] = pc[11] & pc[10] & pc[9] & pc[8];
	assign incb[3]= pc[15] & pc[14] & pc[13] & pc[12];
	
	assign zeropos[0] =  (~incb[1]&incb[0]);
	assign zeropos[1] = ~incb[2] & incb[1] & incb[0]; 
	assign zeropos[2] = incb[2] & incb[1] & incb[0]; 
	
	inc4bit inc(lwire[zeropos],temp);

	assign j = zeropos;



	assign temp2 = 4'b1111 << j;

	
	assign temp4[15] = pc[15] & temp2[3];
	assign temp4[14] = pc[14] & temp2[3];
	assign temp4[13] = pc[13] & temp2[3];
	assign temp4[12] = pc[12] & temp2[3];

	assign temp4[11] = pc[11] & temp2[2];
	assign temp4[10] = pc[10] & temp2[2];
	assign temp4[9] = pc[9] & temp2[2];
	assign temp4[8] = pc[8] & temp2[2];

	assign temp4[7] = pc[7] & temp2[1];
	assign temp4[6] = pc[6] & temp2[1];
	assign temp4[5] = pc[5] & temp2[1];
	assign temp4[4] = pc[4] & temp2[1];

	assign temp4[3] = pc[3] & temp2[0];
	assign temp4[2] = pc[2] & temp2[0];
	assign temp4[1] = pc[1] & temp2[0];
	assign temp4[0] = pc[0] & temp2[0];






	assign temp3 = temp << (4*j);



	assign pcwire = temp4 | temp3;







		





	
















endmodule