data/full_repos/permissive/143278/ivltests/pr2233192c.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2233192c.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg passed;

  reg signed[95:0] m_one, m_two, zero, one, two;


  reg signed[95:0] rem;
  wire signed[95:0] wrem = one % two;


  reg signed[95:0] rem1n;
  wire signed[95:0] wrem1n = m_one % two;


  reg signed[95:0] rem2n;
  wire signed[95:0] wrem2n = one % m_two;


  reg signed[95:0] rembn;
  wire signed[95:0] wrembn = m_one % m_two;


  reg signed[95:0] remd0;
  wire signed[95:0] wremd0 = one % zero;

  initial begin
    passed = 1'b1;
    m_one = 96'hffffffffffffffffffffffff;
    m_two = 96'hfffffffffffffffffffffffe;
    zero = 96'h000000000000000000000000;
    one = 96'h000000000000000000000001;
    two = 96'h000000000000000000000002;

    #1;

    if (wrem !== 96'h000000000000000000000001) begin
      $display("Failed: CA remainder, expected 96'h00...01, got %h",
                wrem);
      passed = 1'b0;
    end

    rem = one % two;
    if (rem !== 96'h000000000000000000000001) begin
      $display("Failed: remainder, expected 96'h00...01, got %h",
                rem);
      passed = 1'b0;
    end


    if (wrem1n !== 96'hffffffffffffffffffffffff) begin
      $display("Failed: CA remainder (1n), expected 96'hff...ff, got %h",
                wrem1n);
      passed = 1'b0;
    end

    rem1n = m_one % two;
    if (rem1n !== 96'hffffffffffffffffffffffff) begin
      $display("Failed: remainder (1n), expected 96'hff...ff, got %h",
                rem1n);
      passed = 1'b0;
    end


    if (wrem2n !== 96'h000000000000000000000001) begin
      $display("Failed: CA remainder (2n), expected 96'h00...01, got %h",
                wrem2n);
      passed = 1'b0;
    end

    rem2n = one % m_two;
    if (rem2n !== 96'h000000000000000000000001) begin
      $display("Failed: remainder (2n), expected 96'h00...01, got %h",
                rem2n);
      passed = 1'b0;
    end


    if (wrembn !== 96'hffffffffffffffffffffffff) begin
      $display("Failed: CA remainder (bn), expected 96'hff...ff, got %h",
                wrembn);
      passed = 1'b0;
    end

    rembn = m_one % m_two;
    if (rembn !== 96'hffffffffffffffffffffffff) begin
      $display("Failed: remainder (bn), expected 96'hff...ff, got %h",
                rembn);
      passed = 1'b0;
    end


    if (wremd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
      $display("Failed: CA remainder (d0), expected 96'hxx...xx, got %h",
                wremd0);
      passed = 1'b0;
    end

    remd0 = one % zero;
    if (remd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
      $display("Failed: remainder (d0), expected 96'hxx...xx, got %h",
                remd0);
      passed = 1'b0;
    end

    if (passed) $display("PASSED");
  end
endmodule
module top;

  reg passed;

  reg signed[95:0] m_one, m_two, zero, one, two;


  reg signed[95:0] rem;
  wire signed[95:0] wrem = one % two;


  reg signed[95:0] rem1n;
  wire signed[95:0] wrem1n = m_one % two;


  reg signed[95:0] rem2n;
  wire signed[95:0] wrem2n = one % m_two;


  reg signed[95:0] rembn;
  wire signed[95:0] wrembn = m_one % m_two;


  reg signed[95:0] remd0;
  wire signed[95:0] wremd0 = one % zero;

  initial begin
    passed = 1'b1;
    m_one = 96'hffffffffffffffffffffffff;
    m_two = 96'hfffffffffffffffffffffffe;
    zero = 96'h000000000000000000000000;
    one = 96'h000000000000000000000001;
    two = 96'h000000000000000000000002;

    #1;

    if (wrem !== 96'h000000000000000000000001) begin
      $display("Failed: CA remainder, expected 96'h00...01, got %h",
                wrem);
      passed = 1'b0;
    end

    rem = one % two;
    if (rem !== 96'h000000000000000000000001) begin
      $display("Failed: remainder, expected 96'h00...01, got %h",
                rem);
      passed = 1'b0;
    end


    if (wrem1n !== 96'hffffffffffffffffffffffff) begin
      $display("Failed: CA remainder (1n), expected 96'hff...ff, got %h",
                wrem1n);
      passed = 1'b0;
    end

    rem1n = m_one % two;
    if (rem1n !== 96'hffffffffffffffffffffffff) begin
      $display("Failed: remainder (1n), expected 96'hff...ff, got %h",
                rem1n);
      passed = 1'b0;
    end


    if (wrem2n !== 96'h000000000000000000000001) begin
      $display("Failed: CA remainder (2n), expected 96'h00...01, got %h",
                wrem2n);
      passed = 1'b0;
    end

    rem2n = one % m_two;
    if (rem2n !== 96'h000000000000000000000001) begin
      $display("Failed: remainder (2n), expected 96'h00...01, got %h",
                rem2n);
      passed = 1'b0;
    end


    if (wrembn !== 96'hffffffffffffffffffffffff) begin
      $display("Failed: CA remainder (bn), expected 96'hff...ff, got %h",
                wrembn);
      passed = 1'b0;
    end

    rembn = m_one % m_two;
    if (rembn !== 96'hffffffffffffffffffffffff) begin
      $display("Failed: remainder (bn), expected 96'hff...ff, got %h",
                rembn);
      passed = 1'b0;
    end


    if (wremd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
      $display("Failed: CA remainder (d0), expected 96'hxx...xx, got %h",
                wremd0);
      passed = 1'b0;
    end

    remd0 = one % zero;
    if (remd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
      $display("Failed: remainder (d0), expected 96'hxx...xx, got %h",
                remd0);
      passed = 1'b0;
    end

    if (passed) $display("PASSED");
  end
endmodule