data/full_repos/permissive/167274925/Two4DigitDisplay.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/167274925/Two4DigitDisplay.v:33: Cannot find file containing module: \'SevenSegment\'\n    SevenSegment m1(in4, out7);\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/SevenSegment\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/SevenSegment.v\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/SevenSegment.sv\n             SevenSegment\n             SevenSegment.v\n             SevenSegment.sv\n             obj_dir/SevenSegment\n             obj_dir/SevenSegment.v\n             obj_dir/SevenSegment.sv\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:46: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                          : ... In instance Two4DigitDisplay\n                    firstdigitA <= NumberA%10;\n                                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:47: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                          : ... In instance Two4DigitDisplay\n                    seconddigitA <= (NumberA/10)%10;\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:48: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                          : ... In instance Two4DigitDisplay\n                    thirddigitA <= (NumberA/100)%10;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:49: Operator DIV expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'NumberA\' generates 8 bits.\n                                                                          : ... In instance Two4DigitDisplay\n                    forthdigitA <= NumberA/1000;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:49: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 10 bits.\n                                                                          : ... In instance Two4DigitDisplay\n                    forthdigitA <= NumberA/1000;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:44: Operator LT expects 32 or 14 bits on the LHS, but LHS\'s VARREF \'NumberA\' generates 8 bits.\n                                                                          : ... In instance Two4DigitDisplay\n            if (NumberA < 10000)\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:63: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                          : ... In instance Two4DigitDisplay\n                    firstdigitB <= NumberB%10;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:64: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                          : ... In instance Two4DigitDisplay\n                    seconddigitB <= (NumberB/10)%10;\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:65: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                          : ... In instance Two4DigitDisplay\n                    thirddigitB <= (NumberB/100)%10;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:66: Operator DIV expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'NumberB\' generates 8 bits.\n                                                                          : ... In instance Two4DigitDisplay\n                    forthdigitB <= NumberB/1000;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:66: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 10 bits.\n                                                                          : ... In instance Two4DigitDisplay\n                    forthdigitB <= NumberB/1000;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/Two4DigitDisplay.v:61: Operator LT expects 32 or 14 bits on the LHS, but LHS\'s VARREF \'NumberB\' generates 8 bits.\n                                                                          : ... In instance Two4DigitDisplay\n            if (NumberB < 10000)\n                        ^\n%Error: Exiting due to 1 error(s), 12 warning(s)\n'
module Two4DigitDisplay(Clk, NumberA, NumberB, out7, en_out);

    parameter NUM_WIDTH = 8;

    input  Clk;
    input  [NUM_WIDTH - 1:0] NumberA, NumberB;
    output [6:0] out7;
    output reg [7:0] en_out;
             
    reg  [3:0] in4;        
    reg  [3:0] firstdigitA;
    reg  [3:0] seconddigitA;
    reg  [3:0] thirddigitA;
    reg  [3:0] forthdigitA;
    reg  [3:0] firstdigitB;
    reg  [3:0] seconddigitB;
    reg  [3:0] thirddigitB;
    reg  [3:0] forthdigitB;
    


    SevenSegment m1(in4, out7);

         

    reg  [19:0] cnt;
    always @(posedge Clk) begin
        cnt <= cnt + 1;
    end
    

    always @(NumberA) begin
            if (NumberA < 10000)
                begin
                    firstdigitA <= NumberA%10;
                    seconddigitA <= (NumberA/10)%10;
                    thirddigitA <= (NumberA/100)%10;
                    forthdigitA <= NumberA/1000;
                end 
             else
             begin
                    firstdigitA <= 4'b1111;
                    seconddigitA <= 4'b1111;
                    thirddigitA <= 4'b1111;
                    forthdigitA <= 4'b1111;
             end
    end
    
    always @(NumberB) begin
            if (NumberB < 10000)
                begin
                    firstdigitB <= NumberB%10;
                    seconddigitB <= (NumberB/10)%10;
                    thirddigitB <= (NumberB/100)%10;
                    forthdigitB <= NumberB/1000;
                end 
             else
             begin
                    firstdigitB <= 4'b1111;
                    seconddigitB <= 4'b1111;
                    thirddigitB <= 4'b1111;
                    forthdigitB <= 4'b1111;
             end
    end
    

    always @(cnt) begin
        case(cnt[19:17])
            3'b000: begin en_out <= 8'b11111110; in4 <= firstdigitA; end
            3'b001: begin en_out <= 8'b11111101; in4 <= seconddigitA; end
            3'b010: begin en_out <= 8'b11111011; in4 <= thirddigitA; end
            3'b011: begin en_out <= 8'b11110111; in4 <= forthdigitA; end
            3'b100: begin en_out <= 8'b11101111; in4 <= firstdigitB; end
            3'b101: begin en_out <= 8'b11011111; in4 <= seconddigitB; end
            3'b110: begin en_out <= 8'b10111111; in4 <= thirddigitB; end
            3'b111: begin en_out <= 8'b01111111; in4 <= forthdigitB; end
            default: begin en_out <= 8'b11111111; in4 <= 4'b1111; end 
        endcase
     end
     
     
    
endmodule
module Two4DigitDisplay(Clk, NumberA, NumberB, out7, en_out);


    parameter NUM_WIDTH = 8;

    input  Clk;
    input  [NUM_WIDTH - 1:0] NumberA, NumberB;
    output [6:0] out7;
    output reg [7:0] en_out;
             
    reg  [3:0] in4;        
    reg  [3:0] firstdigitA;
    reg  [3:0] seconddigitA;
    reg  [3:0] thirddigitA;
    reg  [3:0] forthdigitA;
    reg  [3:0] firstdigitB;
    reg  [3:0] seconddigitB;
    reg  [3:0] thirddigitB;
    reg  [3:0] forthdigitB;
    


    SevenSegment m1(in4, out7);

         

    reg  [19:0] cnt;
    always @(posedge Clk) begin
        cnt <= cnt + 1;
    end
    

    always @(NumberA) begin
            if (NumberA < 10000)
                begin
                    firstdigitA <= NumberA%10;
                    seconddigitA <= (NumberA/10)%10;
                    thirddigitA <= (NumberA/100)%10;
                    forthdigitA <= NumberA/1000;
                end 
             else
             begin
                    firstdigitA <= 4'b1111;
                    seconddigitA <= 4'b1111;
                    thirddigitA <= 4'b1111;
                    forthdigitA <= 4'b1111;
             end
    end
    
    always @(NumberB) begin
            if (NumberB < 10000)
                begin
                    firstdigitB <= NumberB%10;
                    seconddigitB <= (NumberB/10)%10;
                    thirddigitB <= (NumberB/100)%10;
                    forthdigitB <= NumberB/1000;
                end 
             else
             begin
                    firstdigitB <= 4'b1111;
                    seconddigitB <= 4'b1111;
                    thirddigitB <= 4'b1111;
                    forthdigitB <= 4'b1111;
             end
    end
    

    always @(cnt) begin
        case(cnt[19:17])
            3'b000: begin en_out <= 8'b11111110; in4 <= firstdigitA; end
            3'b001: begin en_out <= 8'b11111101; in4 <= seconddigitA; end
            3'b010: begin en_out <= 8'b11111011; in4 <= thirddigitA; end
            3'b011: begin en_out <= 8'b11110111; in4 <= forthdigitA; end
            3'b100: begin en_out <= 8'b11101111; in4 <= firstdigitB; end
            3'b101: begin en_out <= 8'b11011111; in4 <= seconddigitB; end
            3'b110: begin en_out <= 8'b10111111; in4 <= thirddigitB; end
            3'b111: begin en_out <= 8'b01111111; in4 <= forthdigitB; end
            default: begin en_out <= 8'b11111111; in4 <= 4'b1111; end 
        endcase
     end
     
     
    
endmodule