data/full_repos/permissive/137045072/bram_controller.v
 line:423: before: "="
1: b'%Error: data/full_repos/permissive/137045072/bram_controller.v:32: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/137045072/bram_controller.v:43: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] addr,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] addr,\n                    ^\n%Error: data/full_repos/permissive/137045072/bram_controller.v:50: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] data_write,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:53: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`DATA_BUS] data_read,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:53: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] data_read,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:56: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg finished,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:59: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg ena = 0,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:60: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg wea = 0,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:61: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`BRAM_ADDR_BUS] addra,\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:61: Define or directive not defined: \'`BRAM_ADDR_BUS\'\n    output reg [`BRAM_ADDR_BUS] addra,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:62: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] dina,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:63: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] douta\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:97: syntax error, unexpected always\n    always @(posedge clk, negedge rst_n)\n    ^~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:126: Define or directive not defined: \'`MEM_WRITE\'\n                        if (rw == `MEM_WRITE)\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:130: Define or directive not defined: \'`MEM_WRITE\'\n                            wea <= `MEM_WRITE;\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:131: Define or directive not defined: \'`BRAM_ADDR_RANGE\'\n                            addra <= addr[`BRAM_ADDR_RANGE];\n                                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:141: Define or directive not defined: \'`MEM_READ\'\n                        else if (rw == `MEM_READ)\n                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:145: Define or directive not defined: \'`MEM_READ\'\n                            wea <= `MEM_READ;\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:146: Define or directive not defined: \'`BRAM_ADDR_RANGE\'\n                            addra <= addr[`BRAM_ADDR_RANGE];\n                                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:149: Define or directive not defined: \'`TRUE\'\n                            wait_for(STATE_READ, 3, `TRUE);\n                                                    ^~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:167: Define or directive not defined: \'`FALSE\'\n                        wait_for(STATE_READY, 1, `FALSE);\n                                                 ^~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:171: Define or directive not defined: \'`FALSE\'\n                        wait_for(STATE_READ_FINISH, 1, `FALSE);\n                                                       ^~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:181: Define or directive not defined: \'`FALSE\'\n                    wait_for(STATE_READY, 1, `FALSE);\n                                             ^~~~~~\n%Error: data/full_repos/permissive/137045072/bram_controller.v:194: Define or directive not defined: \'`FALSE\'\n                        wait_for(STATE_READY, 1, `FALSE);\n                                                 ^~~~~~\n%Error: Exiting due to 25 error(s)\n'
module bram_controller#(
	parameter DATA_WIDTH = 32,
	parameter BRAM_ADDR_WIDTH = 16,

    parameter BLOCK_OFFSET_WIDTH = 5
)(
    input clk,
    input rst_n,
    
    input [`DATA_BUS] addr,
    input enable,
    input rw,
    
    input op_size,
    input finishes_op,
    
    input [`DATA_BUS] data_write,
    output reg data_write_req_input,

    output reg [`DATA_BUS] data_read,
    output reg data_read_valid,

    output reg finished,


    output reg ena = 0,
    output reg wea = 0,
    output reg [`BRAM_ADDR_BUS] addra,
    output reg [`DATA_BUS] dina,
    input [`DATA_BUS] douta
    );


    localparam BLOCK_SIZE = 1<<BLOCK_OFFSET_WIDTH;

    localparam STATE_READY = 0;
    localparam STATE_READ = 2;
    localparam STATE_READ_FINISH = 7;
    localparam STATE_WRITE = 9;
    localparam STATE_WAIT = 15;
    
    localparam OP_SIZE_BLOCK = 0;
    localparam OP_SIZE_USER = 1;


    reg [3:0] state, next_state;
    reg [BLOCK_OFFSET_WIDTH-1:0] cnt;
    reg [5:0] delay_cnt;
    reg increasing_addr_delay;

    task wait_for;
        input [2:0] _next_state;
        input [5:0] delay;
        input increasing_addr;

        begin
            state <= STATE_WAIT;
            next_state <= _next_state;
            delay_cnt <= delay - 1;
            increasing_addr_delay <= increasing_addr;
        end
    endtask

    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            ena <= 0;
            addra <= 0;
            wea <= 0;
            dina <= 0;

            data_read <= 0;
            data_write_req_input <= 0;
            data_read_valid <= 0;
            finished <= 0;
            cnt <= 0;
            
            delay_cnt <= 0;
            increasing_addr_delay <= 0;
            next_state <= STATE_READY;

            state <= STATE_READY;
        end
        else
        begin
            case (state)
                STATE_READY: begin
                    data_read_valid <= 0;
                    ena <= 0;
                    if (enable)
                    begin
                        if (rw == `MEM_WRITE)
                        begin
                            cnt <= 0;
                            ena <= 1;
                            wea <= `MEM_WRITE;
                            addra <= addr[`BRAM_ADDR_RANGE];


                            dina <= data_write;
                            data_write_req_input <= 1;
                            state <= STATE_WRITE;
`ifdef DEBUG_BRAM
                            $display("bram: write");
`endif
                        end
                        else if (rw == `MEM_READ)
                        begin
                            cnt <= 0;
                            ena <= 1;
                            wea <= `MEM_READ;
                            addra <= addr[`BRAM_ADDR_RANGE];
                            

                            wait_for(STATE_READ, 3, `TRUE);
`ifdef DEBUG_BRAM
                            $display("bram: read");
`endif
                        end
                    end
                end
                STATE_READ: begin
                    data_read_valid <= 1;
                    data_read <= douta;
                    addra <= addra + 1;
                    cnt <= cnt + 1;
                    if (op_size == OP_SIZE_USER && finishes_op)
                    begin


                        finished <= 1;

                        wait_for(STATE_READY, 1, `FALSE);
                    end
                    else if (cnt == BLOCK_SIZE - 1)
                    begin
                        wait_for(STATE_READ_FINISH, 1, `FALSE);
                    end
                    else

                        finished <= 0;
                end
                STATE_READ_FINISH: begin
                    data_read_valid <= 1;
                    data_read <= douta;
                    finished <= 1;
                    wait_for(STATE_READY, 1, `FALSE);
                end
                STATE_WRITE: begin
                    dina <= data_write;
                    addra <= addra + 1;
                    cnt <= cnt + 1;
                    if (cnt == BLOCK_SIZE - 1 || op_size == OP_SIZE_USER && finishes_op)
                    begin

                        finished <= 1;
                        data_write_req_input <= 0;


                        wait_for(STATE_READY, 1, `FALSE);
                    end
                    else
                        finished <= 0;
                end
                STATE_WAIT: begin
                    finished <= 0;
                    delay_cnt <= delay_cnt - 1;
                    data_read <= douta;
                    if (increasing_addr_delay)
                    begin
                        addra <= addra + 1;
                        cnt <= cnt + 1;
                    end
                    if (delay_cnt == 0)
                        state <= next_state;
                end
            endcase
        end
    end
endmodule
module bram_controller#(
	parameter DATA_WIDTH = 32,
	parameter BRAM_ADDR_WIDTH = 16,

    parameter BLOCK_OFFSET_WIDTH = 5
)(
    input clk,
    input rst_n,
    
    input [`DATA_BUS] addr,
    input enable,
    input rw,
    
    input op_size,
    input finishes_op,
    
    input [`DATA_BUS] data_write,
    output reg data_write_req_input,

    output reg [`DATA_BUS] data_read,
    output reg data_read_valid,

    output reg finished,


    output reg ena = 0,
    output reg wea = 0,
    output reg [`BRAM_ADDR_BUS] addra,
    output reg [`DATA_BUS] dina,
    input [`DATA_BUS] douta
    );



    localparam BLOCK_SIZE = 1<<BLOCK_OFFSET_WIDTH;

    localparam STATE_READY = 0;
    localparam STATE_READ = 2;
    localparam STATE_READ_FINISH = 7;
    localparam STATE_WRITE = 9;
    localparam STATE_WAIT = 15;
    
    localparam OP_SIZE_BLOCK = 0;
    localparam OP_SIZE_USER = 1;


    reg [3:0] state, next_state;
    reg [BLOCK_OFFSET_WIDTH-1:0] cnt;
    reg [5:0] delay_cnt;
    reg increasing_addr_delay;

    task wait_for;
        input [2:0] _next_state;
        input [5:0] delay;
        input increasing_addr;

        begin
            state <= STATE_WAIT;
            next_state <= _next_state;
            delay_cnt <= delay - 1;
            increasing_addr_delay <= increasing_addr;
        end
    endtask

    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            ena <= 0;
            addra <= 0;
            wea <= 0;
            dina <= 0;

            data_read <= 0;
            data_write_req_input <= 0;
            data_read_valid <= 0;
            finished <= 0;
            cnt <= 0;
            
            delay_cnt <= 0;
            increasing_addr_delay <= 0;
            next_state <= STATE_READY;

            state <= STATE_READY;
        end
        else
        begin
            case (state)
                STATE_READY: begin
                    data_read_valid <= 0;
                    ena <= 0;
                    if (enable)
                    begin
                        if (rw == `MEM_WRITE)
                        begin
                            cnt <= 0;
                            ena <= 1;
                            wea <= `MEM_WRITE;
                            addra <= addr[`BRAM_ADDR_RANGE];


                            dina <= data_write;
                            data_write_req_input <= 1;
                            state <= STATE_WRITE;
`ifdef DEBUG_BRAM
                            $display("bram: write");
`endif
                        end
                        else if (rw == `MEM_READ)
                        begin
                            cnt <= 0;
                            ena <= 1;
                            wea <= `MEM_READ;
                            addra <= addr[`BRAM_ADDR_RANGE];
                            

                            wait_for(STATE_READ, 3, `TRUE);
`ifdef DEBUG_BRAM
                            $display("bram: read");
`endif
                        end
                    end
                end
                STATE_READ: begin
                    data_read_valid <= 1;
                    data_read <= douta;
                    addra <= addra + 1;
                    cnt <= cnt + 1;
                    if (op_size == OP_SIZE_USER && finishes_op)
                    begin


                        finished <= 1;

                        wait_for(STATE_READY, 1, `FALSE);
                    end
                    else if (cnt == BLOCK_SIZE - 1)
                    begin
                        wait_for(STATE_READ_FINISH, 1, `FALSE);
                    end
                    else

                        finished <= 0;
                end
                STATE_READ_FINISH: begin
                    data_read_valid <= 1;
                    data_read <= douta;
                    finished <= 1;
                    wait_for(STATE_READY, 1, `FALSE);
                end
                STATE_WRITE: begin
                    dina <= data_write;
                    addra <= addra + 1;
                    cnt <= cnt + 1;
                    if (cnt == BLOCK_SIZE - 1 || op_size == OP_SIZE_USER && finishes_op)
                    begin

                        finished <= 1;
                        data_write_req_input <= 0;


                        wait_for(STATE_READY, 1, `FALSE);
                    end
                    else
                        finished <= 0;
                end
                STATE_WAIT: begin
                    finished <= 0;
                    delay_cnt <= delay_cnt - 1;
                    data_read <= douta;
                    if (increasing_addr_delay)
                    begin
                        addra <= addra + 1;
                        cnt <= cnt + 1;
                    end
                    if (delay_cnt == 0)
                        state <= next_state;
                end
            endcase
        end
    end
endmodule