data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_combo_wrapped_tb.v
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_combo_wrapped_tb.v:3: Cannot find include file: ovl_combo_wrapped.v\n`include "ovl_combo_wrapped.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_combo_wrapped.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_combo_wrapped.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_combo_wrapped.v.sv\n             ovl_combo_wrapped.v\n             ovl_combo_wrapped.v.v\n             ovl_combo_wrapped.v.sv\n             obj_dir/ovl_combo_wrapped.v\n             obj_dir/ovl_combo_wrapped.v.v\n             obj_dir/ovl_combo_wrapped.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_combo_wrapped_tb.v:4: Cannot find include file: ovl_ported/ovl_combo.v\n`include "ovl_ported/ovl_combo.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module main();


   reg clk;
   reg rst;
   reg enable;
   reg [2:0] num_cks;
   reg       start_event;
   reg       test_expr;
   reg [1:0] select;
   reg       prevConfigInvalid;


   wire      out;
   wire      out_delayed;
   wire      configInvalid;

   ovl_combo_wrapped ovl_cw_t(.clk(clk),
                              .rst(rst),
                              .enable(enable),
                              .num_cks(num_cks),
                              .start_event(start_event),
                              .test_expr(test_expr),
                              .select(select),
                              .prevConfigInvalid(prevConfigInvalid),
                              .out(out),
                              .out_delayed(out_delayed),
                              .configInvalid(configInvalid));

   initial begin
      clk = 0;
      rst = 1;
      enable = 0;
      num_cks = 0;
      start_event = 0;
      test_expr = 0;
      select = 0;
      prevConfigInvalid = 0;
   end

   always begin
      clk = #5 !clk;
   end

endmodule
module main();



   reg clk;
   reg rst;
   reg enable;
   reg [2:0] num_cks;
   reg       start_event;
   reg       test_expr;
   reg [1:0] select;
   reg       prevConfigInvalid;


   wire      out;
   wire      out_delayed;
   wire      configInvalid;

   ovl_combo_wrapped ovl_cw_t(.clk(clk),
                              .rst(rst),
                              .enable(enable),
                              .num_cks(num_cks),
                              .start_event(start_event),
                              .test_expr(test_expr),
                              .select(select),
                              .prevConfigInvalid(prevConfigInvalid),
                              .out(out),
                              .out_delayed(out_delayed),
                              .configInvalid(configInvalid));

   initial begin
      clk = 0;
      rst = 1;
      enable = 0;
      num_cks = 0;
      start_event = 0;
      test_expr = 0;
      select = 0;
      prevConfigInvalid = 0;
   end

   always begin
      clk = #5 !clk;
   end

endmodule