data/full_repos/permissive/157587577/Basics/verilog/Labs/SyncAutomates/example_automates/milley_automate/milley_automate.v
 line:29: before: "reg"
data/verilator_xmls/143ec5a5-2bea-4fa1-ad39-b364990ce316.xml
module milley_automate(
    input wire reset,
    input wire clk,
    input wire [1:0] a,
    output reg [1:0] b
);
    


    
    localparam reg [1:0] A1 = 2'b01;
    localparam reg [1:0] A2 = 2'b10;
    localparam reg [1:0] A3 = 2'b11;
    
    localparam reg [1:0] B1 = 2'b00;
    localparam reg [1:0] B2 = 2'b01;
    localparam reg [1:0] B3 = 2'b10;
    localparam reg [1:0] B4 = 2'b11;
    
    localparam reg [1:0] C1 = 2'b00;
    localparam reg [1:0] C2 = 2'b01;
    localparam reg [1:0] C3 = 2'b10;
    localparam reg [1:0] C4 = 2'b11;

    reg[1:0] c;
    
    always @(posedge clk)
    begin
        if (reset)
        begin
            c <= C1;
            b <= 0;
        end
        else
        begin
            case (c)
                C1: 
                begin
                    if (a == A2)
                    begin
                        c <= C2;
                        b <= B3;
                    end
                    else if (a == A3)
                    begin
                        c <= C3;
                        b <= B4;
                    end
                    else
                    begin
                        c <= C1;
                        b <= B2;
                    end
                end
                C2: 
                begin
                    if (a == A3)
                    begin
                        c <= C1;
                        b <= B1;
                    end
                    else
                    begin
                        c <= C2;

                    end
                end
                C3: 
                begin
                    if (a == A1)
                    begin
                        c <= C4;
                        b <= B1;
                    end
                    else if (a == A2)
                    begin
                        c <= C1;
                        b <= B3;
                    end
                    else if (a == A3)
                    begin
                        c <= C2;
                        b <= B4;
                    end
                    else
                    begin
                        c <= C3;
                    end
                end
                C4: 
                begin
                    if (a == A1)
                    begin
                        c <= C4;
                        b <= B2;
                    end
                    else if (a == A3)
                    begin
                        c <= C2;
                        b <= B2;
                    end
                    else 
                    begin
                        c <= C4;
                    end
                end
                default:
                begin
                    b <= B1;
                    c <= C1;
                end
            endcase
        end
    end

endmodule
module milley_automate(
    input wire reset,
    input wire clk,
    input wire [1:0] a,
    output reg [1:0] b
);

    


    
    localparam reg [1:0] A1 = 2'b01;
    localparam reg [1:0] A2 = 2'b10;
    localparam reg [1:0] A3 = 2'b11;
    
    localparam reg [1:0] B1 = 2'b00;
    localparam reg [1:0] B2 = 2'b01;
    localparam reg [1:0] B3 = 2'b10;
    localparam reg [1:0] B4 = 2'b11;
    
    localparam reg [1:0] C1 = 2'b00;
    localparam reg [1:0] C2 = 2'b01;
    localparam reg [1:0] C3 = 2'b10;
    localparam reg [1:0] C4 = 2'b11;

    reg[1:0] c;
    
    always @(posedge clk)
    begin
        if (reset)
        begin
            c <= C1;
            b <= 0;
        end
        else
        begin
            case (c)
                C1: 
                begin
                    if (a == A2)
                    begin
                        c <= C2;
                        b <= B3;
                    end
                    else if (a == A3)
                    begin
                        c <= C3;
                        b <= B4;
                    end
                    else
                    begin
                        c <= C1;
                        b <= B2;
                    end
                end
                C2: 
                begin
                    if (a == A3)
                    begin
                        c <= C1;
                        b <= B1;
                    end
                    else
                    begin
                        c <= C2;

                    end
                end
                C3: 
                begin
                    if (a == A1)
                    begin
                        c <= C4;
                        b <= B1;
                    end
                    else if (a == A2)
                    begin
                        c <= C1;
                        b <= B3;
                    end
                    else if (a == A3)
                    begin
                        c <= C2;
                        b <= B4;
                    end
                    else
                    begin
                        c <= C3;
                    end
                end
                C4: 
                begin
                    if (a == A1)
                    begin
                        c <= C4;
                        b <= B2;
                    end
                    else if (a == A3)
                    begin
                        c <= C2;
                        b <= B2;
                    end
                    else 
                    begin
                        c <= C4;
                    end
                end
                default:
                begin
                    b <= B1;
                    c <= C1;
                end
            endcase
        end
    end

endmodule