data/full_repos/permissive/168234415/A1_Factorial_Accelerator/CMPE140_Assignment1.srcs/sources_1/new/CNT.v
data/verilator_xmls/3938f7d3-4c5e-47cd-90e9-72d7d907634b.xml
module CNT #(parameter Data_Width = 4)(
    input [Data_Width - 1:0] D,
    input Load_Cnt, En, Clk,
    output reg [Data_Width - 1:0] Q 
);    
    
    
    always @ (posedge Clk)
    begin
        if (En)
        begin
            if (Load_Cnt)
                Q <= D;
            else
            begin
                Q <= Q - 1'b1;
            end
        end
    end
endmodule
module CNT #(parameter Data_Width = 4)(
    input [Data_Width - 1:0] D,
    input Load_Cnt, En, Clk,
    output reg [Data_Width - 1:0] Q 
);
    
    
    
    always @ (posedge Clk)
    begin
        if (En)
        begin
            if (Load_Cnt)
                Q <= D;
            else
            begin
                Q <= Q - 1'b1;
            end
        end
    end
endmodule