data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/drams_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/drams_map.v:38: Multiple top level modules\n                                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                             : ... Top module \'$__XILINX_RAM64X1D\'\nmodule \\$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                                             : ... Top module \'$__XILINX_RAM128X1D\'\nmodule \\$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);\n       ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/drams_map.v:50: Cannot find file containing module: \'RAM128X1D\'\n RAM128X1D #(\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx,data/full_repos/permissive/200142067/RAM128X1D\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx,data/full_repos/permissive/200142067/RAM128X1D.v\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx,data/full_repos/permissive/200142067/RAM128X1D.sv\n             RAM128X1D\n             RAM128X1D.v\n             RAM128X1D.sv\n             obj_dir/RAM128X1D\n             obj_dir/RAM128X1D.v\n             obj_dir/RAM128X1D.sv\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/xilinx/drams_map.v:14: Cannot find file containing module: \'RAM64X1D\'\n RAM64X1D #(\n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
	parameter [63:0] INIT = 64'bx;
	parameter CLKPOL2 = 1;
	input CLK1;

	input [5:0] A1ADDR;
	output A1DATA;

	input [5:0] B1ADDR;
	input B1DATA;
	input B1EN;

	RAM64X1D #(
		.INIT(INIT),
		.IS_WCLK_INVERTED(!CLKPOL2)
	) _TECHMAP_REPLACE_ (
		.DPRA0(A1ADDR[0]),
		.DPRA1(A1ADDR[1]),
		.DPRA2(A1ADDR[2]),
		.DPRA3(A1ADDR[3]),
		.DPRA4(A1ADDR[4]),
		.DPRA5(A1ADDR[5]),
		.DPO(A1DATA),

		.A0(B1ADDR[0]),
		.A1(B1ADDR[1]),
		.A2(B1ADDR[2]),
		.A3(B1ADDR[3]),
		.A4(B1ADDR[4]),
		.A5(B1ADDR[5]),
		.D(B1DATA),
		.WCLK(CLK1),
		.WE(B1EN)
	);
endmodule
module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);

	parameter [63:0] INIT = 64'bx;
	parameter CLKPOL2 = 1;
	input CLK1;

	input [5:0] A1ADDR;
	output A1DATA;

	input [5:0] B1ADDR;
	input B1DATA;
	input B1EN;

	RAM64X1D #(
		.INIT(INIT),
		.IS_WCLK_INVERTED(!CLKPOL2)
	) _TECHMAP_REPLACE_ (
		.DPRA0(A1ADDR[0]),
		.DPRA1(A1ADDR[1]),
		.DPRA2(A1ADDR[2]),
		.DPRA3(A1ADDR[3]),
		.DPRA4(A1ADDR[4]),
		.DPRA5(A1ADDR[5]),
		.DPO(A1DATA),

		.A0(B1ADDR[0]),
		.A1(B1ADDR[1]),
		.A2(B1ADDR[2]),
		.A3(B1ADDR[3]),
		.A4(B1ADDR[4]),
		.A5(B1ADDR[5]),
		.D(B1DATA),
		.WCLK(CLK1),
		.WE(B1EN)
	);
endmodule