data/full_repos/permissive/211316121/7seg/sources_1/new/x7seg.v
1: b"%Error: data/full_repos/permissive/211316121/7seg/sources_1/new/x7seg.v:61: Cannot find file containing module: 'Hex7Seg'\n    Hex7Seg s7(.SW(digit),.A2G(A2G));\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/7seg/sources_1/new,data/full_repos/permissive/211316121/Hex7Seg\n             data/full_repos/permissive/211316121/7seg/sources_1/new,data/full_repos/permissive/211316121/Hex7Seg.v\n             data/full_repos/permissive/211316121/7seg/sources_1/new,data/full_repos/permissive/211316121/Hex7Seg.sv\n             Hex7Seg\n             Hex7Seg.v\n             Hex7Seg.sv\n             obj_dir/Hex7Seg\n             obj_dir/Hex7Seg.v\n             obj_dir/Hex7Seg.sv\n%Error: Exiting due to 1 error(s)\n"
module x7seg(
    input [15:0] SW,
    input CLK,
    input CLR,
    output [6:0] A2G,
    output reg [3:0] AN,
    output DP
    );
    reg [19:0] clkdiv;
    reg [3:0] digit;
    wire [1:0] s;
    
    assign DP=1;
    assign s=clkdiv[19:18];
    
    always@(*)
        case(s)
            0:digit = SW[3:0];
            1:digit = SW[7:4];
            2:digit = SW[11:8];
            3:digit = SW[15:12];
            default:digit = SW[3:0];
        endcase
        
    always@(*)
        begin
            AN='b1111;
            AN[s]=0;
        end
    
    always@(posedge CLK or posedge CLR)
        begin
            if(CLR==1)
                clkdiv<=0;
            else
                clkdiv<=clkdiv+1;
        end
    
    Hex7Seg s7(.SW(digit),.A2G(A2G));
endmodule
module x7seg(
    input [15:0] SW,
    input CLK,
    input CLR,
    output [6:0] A2G,
    output reg [3:0] AN,
    output DP
    );

    reg [19:0] clkdiv;
    reg [3:0] digit;
    wire [1:0] s;
    
    assign DP=1;
    assign s=clkdiv[19:18];
    
    always@(*)
        case(s)
            0:digit = SW[3:0];
            1:digit = SW[7:4];
            2:digit = SW[11:8];
            3:digit = SW[15:12];
            default:digit = SW[3:0];
        endcase
        
    always@(*)
        begin
            AN='b1111;
            AN[s]=0;
        end
    
    always@(posedge CLK or posedge CLR)
        begin
            if(CLR==1)
                clkdiv<=0;
            else
                clkdiv<=clkdiv+1;
        end
    
    Hex7Seg s7(.SW(digit),.A2G(A2G));
endmodule