data/full_repos/permissive/140572461/target/de0-nano/hdl/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/140572461/target/de0-nano/hdl/top.v:14: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                 : ... In instance top\nreg [7:0] reset_count = 1\'b0;\n                        ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/140572461/target/de0-nano/hdl/top.v:16: Cannot find file containing module: \'clk_div\'\nclk_div #(.SYS_CLK(50000000), .CLK_OUT(1000000)) clk_div_1(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/140572461/target/de0-nano/hdl,data/full_repos/permissive/140572461/clk_div\n             data/full_repos/permissive/140572461/target/de0-nano/hdl,data/full_repos/permissive/140572461/clk_div.v\n             data/full_repos/permissive/140572461/target/de0-nano/hdl,data/full_repos/permissive/140572461/clk_div.sv\n             clk_div\n             clk_div.v\n             clk_div.sv\n             obj_dir/clk_div\n             obj_dir/clk_div.v\n             obj_dir/clk_div.sv\n%Error: data/full_repos/permissive/140572461/target/de0-nano/hdl/top.v:22: Cannot find file containing module: \'cpu_core\'\ncpu_core #(.ROM_FILE("../../../asm/ledblink.hex")) cpu_core(\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module top(
    input           CLOCK_50,
    output  [7:0]   LED,
    input   [1:0]   KEY,
    input   [3:0]   SW
);

wire clk;
wire enable = SW[0];
reg reset = 1'b1;
reg [7:0] reset_count = 1'b0;

clk_div #(.SYS_CLK(50000000), .CLK_OUT(1000000)) clk_div_1(
    .clk (CLOCK_50),
    .clk_out (clk),
    .enable (enable)
);

cpu_core #(.ROM_FILE("../../../asm/ledblink.hex")) cpu_core(
    .clk (clk),
    .reset (reset),
    .gpio1 (LED)
);

always @(posedge clk) begin
    if (reset == 1'b1) begin
        reset_count = reset_count + 1'b1;
        if (reset_count == 8'hff) begin
            reset <= 1'b0;
        end
    end
end

endmodule
module top(
    input           CLOCK_50,
    output  [7:0]   LED,
    input   [1:0]   KEY,
    input   [3:0]   SW
);


wire clk;
wire enable = SW[0];
reg reset = 1'b1;
reg [7:0] reset_count = 1'b0;

clk_div #(.SYS_CLK(50000000), .CLK_OUT(1000000)) clk_div_1(
    .clk (CLOCK_50),
    .clk_out (clk),
    .enable (enable)
);

cpu_core #(.ROM_FILE("../../../asm/ledblink.hex")) cpu_core(
    .clk (clk),
    .reset (reset),
    .gpio1 (LED)
);

always @(posedge clk) begin
    if (reset == 1'b1) begin
        reset_count = reset_count + 1'b1;
        if (reset_count == 8'hff) begin
            reset <= 1'b0;
        end
    end
end

endmodule