data/full_repos/permissive/122497324/assignment_4/assignment_4.v
 line:593: before: "("
1: b'%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:238: Cell has missing pin: \'store_mux_stall\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b010)) FP_add_station\n                                                    ^~~~~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:238: Cell has missing pin: \'trigger_exes\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b010)) FP_add_station\n                                                    ^~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:238: Cell has missing pin: \'memory_offset_out\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b010)) FP_add_station\n                                                    ^~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:238: Cell has missing pin: \'valid_data\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b010)) FP_add_station\n                                                    ^~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:254: Cell has missing pin: \'store_mux_stall\'\n  reservation_station #(.BUS_LENGTH(1),.ID(3\'b001)) FP_mult_station\n                                                    ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:254: Cell has missing pin: \'trigger_exes\'\n  reservation_station #(.BUS_LENGTH(1),.ID(3\'b001)) FP_mult_station\n                                                    ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:254: Cell has missing pin: \'memory_offset_out\'\n  reservation_station #(.BUS_LENGTH(1),.ID(3\'b001)) FP_mult_station\n                                                    ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:254: Cell has missing pin: \'valid_data\'\n  reservation_station #(.BUS_LENGTH(1),.ID(3\'b001)) FP_mult_station\n                                                    ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:270: Cell has missing pin: \'trigger_exes\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b011)) store_station\n                                                    ^~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:286: Cell has missing pin: \'store_mux_stall\'\n  reservation_station #(.BUS_LENGTH(2),.ID(3\'b100)) load_station\n                                                    ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:315: Cell has missing pin: \'bbus_data_in\'\n  execution_unit #(.CYCLE_TIME(2),.ID(2\'b11)) load_store_unit\n                                              ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:315: Cell has missing pin: \'fake_clock\'\n  execution_unit #(.CYCLE_TIME(2),.ID(2\'b11)) load_store_unit\n                                              ^~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'offset_in\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'memory_in\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'store_dbus_data_in\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'fake_clock\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'memory_address\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'memory_out\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:329: Cell has missing pin: \'op_code_out\'\n  execution_unit #(.CYCLE_TIME(3),.ID(2\'b10)) FP_add_unit\n                                              ^~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'offset_in\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'memory_in\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'store_dbus_data_in\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'memory_address\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'memory_out\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:341: Cell has missing pin: \'op_code_out\'\n  execution_unit #(.CYCLE_TIME(5),.ID(2\'b01)) FP_mult_unit\n                                              ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:962: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 31 bits.\n                                                                                    : ... In instance assignment_4.load_store_unit\n    memory_address = 31\'bz;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:1007: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'offset_in\' generates 3 bits.\n                                                                                     : ... In instance assignment_4.load_store_unit\n              memory_address = abus_data_in + offset_in;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:1014: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'offset_in\' generates 3 bits.\n                                                                                     : ... In instance assignment_4.load_store_unit\n              memory_address = abus_data_in + offset_in;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:583: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'bzzzzzzzz\' generates 8 bits.\n                                                                                    : ... In instance assignment_4.FP_add_station\n    d_select_out = 8\'bz;\n                 ^\n%Warning-UNSIGNED: data/full_repos/permissive/122497324/assignment_4/assignment_4.v:463: Comparison is constant due to unsigned arithmetic\n                                                                                       : ... In instance assignment_4\n    if((memory_address >= 0) && (load_store > 3\'b000)) begin\n                       ^~\n%Error: Exiting due to 30 warning(s)\n'
module execution_unit #(parameter CYCLE_TIME = 1, ID = 2'b00)
  (

    clk, op_code_in, d_select_in, d_select_shift_in, abus_data_in, bbus_data_in, stall_by_mux, offset_in, memory_in, store_dbus_data_in,

    is_busy, valid_data, dbus_data_out, d_select_out, d_select_shift_out, fake_clock, memory_address, memory_out, op_code_out
  );
  input clk;

  input [2:0] op_code_in;
  input [2:0] d_select_in;
  input [7:0] d_select_shift_in;
  input [31:0] abus_data_in;
  input [31:0] bbus_data_in;

  input stall_by_mux;

  input [2:0] offset_in;

  input [31:0] memory_in;

  input [31:0] store_dbus_data_in;

  output reg is_busy;

  output reg valid_data;

  output reg [31:0] dbus_data_out;
  output reg [2:0] d_select_out;
  output reg [7:0] d_select_shift_out;
  output reg fake_clock;


  output reg [31:0] memory_address;

  output reg [31:0] memory_out;
  output reg [2:0] op_code_out;

  reg [31:0] counter;
  reg [31:0] counter_backup;
  reg [2:0] saved_op_code;
  
  initial begin

    is_busy = 0;
    valid_data = 0;
    dbus_data_out = 0;
    d_select_out = 0;
    d_select_shift_out = 0;
    memory_address = 32'bz;
    memory_out = 32'bz;
    fake_clock = 0;
    counter = 0;
    counter_backup = 0;
    op_code_out = 3'bz;
    saved_op_code = 3'bz;
  end
  

  always @(posedge clk) begin
    valid_data = 0;
    memory_address = 31'bz;
    memory_out = 32'bz;
    op_code_out = 3'bz;
    if(is_busy) begin
      counter = counter + 1;
      $display("execution unit %d is busy, counter=%d",ID, counter);
    end
    if((!is_busy) && (op_code_in > 0)) begin
      $display("execution unit %d is not busy, accepts new instruction.",ID);

      is_busy = 1;

      d_select_out = d_select_in;
      d_select_shift_out = d_select_shift_in;
      case(ID)
        2'b00: begin


        end
        2'b01: begin

          case(op_code_in)
            3'b100: begin

              dbus_data_out = abus_data_in * bbus_data_in;
            end
          endcase
        end
        2'b10: begin

          case(op_code_in)
            3'b011: begin

              dbus_data_out = abus_data_in + bbus_data_in;
            end
          endcase
        end
        2'b11: begin

          case(op_code_in)
            3'b001: begin


              op_code_out = op_code_in;
              saved_op_code = op_code_in;
              memory_address = abus_data_in + offset_in;
            end
            3'b010: begin

              op_code_out = op_code_in;
              saved_op_code = op_code_in;
              memory_out = store_dbus_data_in;
              memory_address = abus_data_in + offset_in;
            end
          endcase
        end
      endcase
    end


    if(counter == CYCLE_TIME) begin
      $display("execution complete for execution unit %d, valid data is high",ID);
      if(saved_op_code == 3'b001) begin

        dbus_data_out = memory_in;
        saved_op_code = 3'bz;
      end
      else if(saved_op_code == 3'b010) begin

        dbus_data_out = 32'b0;
        d_select_out = 3'b0;
        d_select_shift_out = 8'b00000001;
        saved_op_code = 3'bz;
      end

      is_busy = 0;
      counter_backup = counter;
      counter = 0;


      valid_data = 1;
    end

    else if(counter > CYCLE_TIME) begin

      $display("(posedge clk) execution unit %d stalled by mux, setting valid back to true", ID);
      valid_data = 1;
    end
    fake_clock = ~fake_clock;
  end
  

  always @(posedge stall_by_mux) begin
    $display("(posedge stall_by_mux) stall_by_mux detected for execution unit %d",ID);
    is_busy = 1;
    counter = counter_backup;
  end
  


  always @(negedge stall_by_mux) begin
    if(counter > CYCLE_TIME) begin
      $display("(negedge stall_by_mux) stall_by_mux detected for execution unit %d with counter > CYCLE_TIME true",ID);

      is_busy = 0;
      counter = 0;
      counter_backup = 0;
    end
  end
endmodule
module execution_unit #(parameter CYCLE_TIME = 1, ID = 2'b00)
  (

    clk, op_code_in, d_select_in, d_select_shift_in, abus_data_in, bbus_data_in, stall_by_mux, offset_in, memory_in, store_dbus_data_in,

    is_busy, valid_data, dbus_data_out, d_select_out, d_select_shift_out, fake_clock, memory_address, memory_out, op_code_out
  );

  input clk;

  input [2:0] op_code_in;
  input [2:0] d_select_in;
  input [7:0] d_select_shift_in;
  input [31:0] abus_data_in;
  input [31:0] bbus_data_in;

  input stall_by_mux;

  input [2:0] offset_in;

  input [31:0] memory_in;

  input [31:0] store_dbus_data_in;

  output reg is_busy;

  output reg valid_data;

  output reg [31:0] dbus_data_out;
  output reg [2:0] d_select_out;
  output reg [7:0] d_select_shift_out;
  output reg fake_clock;


  output reg [31:0] memory_address;

  output reg [31:0] memory_out;
  output reg [2:0] op_code_out;

  reg [31:0] counter;
  reg [31:0] counter_backup;
  reg [2:0] saved_op_code;
  
  initial begin

    is_busy = 0;
    valid_data = 0;
    dbus_data_out = 0;
    d_select_out = 0;
    d_select_shift_out = 0;
    memory_address = 32'bz;
    memory_out = 32'bz;
    fake_clock = 0;
    counter = 0;
    counter_backup = 0;
    op_code_out = 3'bz;
    saved_op_code = 3'bz;
  end
  

  always @(posedge clk) begin
    valid_data = 0;
    memory_address = 31'bz;
    memory_out = 32'bz;
    op_code_out = 3'bz;
    if(is_busy) begin
      counter = counter + 1;
      $display("execution unit %d is busy, counter=%d",ID, counter);
    end
    if((!is_busy) && (op_code_in > 0)) begin
      $display("execution unit %d is not busy, accepts new instruction.",ID);

      is_busy = 1;

      d_select_out = d_select_in;
      d_select_shift_out = d_select_shift_in;
      case(ID)
        2'b00: begin


        end
        2'b01: begin

          case(op_code_in)
            3'b100: begin

              dbus_data_out = abus_data_in * bbus_data_in;
            end
          endcase
        end
        2'b10: begin

          case(op_code_in)
            3'b011: begin

              dbus_data_out = abus_data_in + bbus_data_in;
            end
          endcase
        end
        2'b11: begin

          case(op_code_in)
            3'b001: begin


              op_code_out = op_code_in;
              saved_op_code = op_code_in;
              memory_address = abus_data_in + offset_in;
            end
            3'b010: begin

              op_code_out = op_code_in;
              saved_op_code = op_code_in;
              memory_out = store_dbus_data_in;
              memory_address = abus_data_in + offset_in;
            end
          endcase
        end
      endcase
    end


    if(counter == CYCLE_TIME) begin
      $display("execution complete for execution unit %d, valid data is high",ID);
      if(saved_op_code == 3'b001) begin

        dbus_data_out = memory_in;
        saved_op_code = 3'bz;
      end
      else if(saved_op_code == 3'b010) begin

        dbus_data_out = 32'b0;
        d_select_out = 3'b0;
        d_select_shift_out = 8'b00000001;
        saved_op_code = 3'bz;
      end

      is_busy = 0;
      counter_backup = counter;
      counter = 0;


      valid_data = 1;
    end

    else if(counter > CYCLE_TIME) begin

      $display("(posedge clk) execution unit %d stalled by mux, setting valid back to true", ID);
      valid_data = 1;
    end
    fake_clock = ~fake_clock;
  end
  

  always @(posedge stall_by_mux) begin
    $display("(posedge stall_by_mux) stall_by_mux detected for execution unit %d",ID);
    is_busy = 1;
    counter = counter_backup;
  end
  


  always @(negedge stall_by_mux) begin
    if(counter > CYCLE_TIME) begin
      $display("(negedge stall_by_mux) stall_by_mux detected for execution unit %d with counter > CYCLE_TIME true",ID);

      is_busy = 0;
      counter = 0;
      counter_backup = 0;
    end
  end
endmodule