data/full_repos/permissive/122924576/DE2_TOP.v
 line:375: before: "."
1: b"%Error: data/full_repos/permissive/122924576/DE2_TOP.v:312: syntax error, unexpected '(', expecting IDENTIFIER\n  CLOCK_50,        \n  ^~~~~~~~\n%Error: data/full_repos/permissive/122924576/DE2_TOP.v:355: syntax error, unexpected '(', expecting IDENTIFIER\nserialArraySend(CLOCK_20, reset, data, count, tile_select_ready, txdBusy, txdWrite, txdData, serialArrayBusy);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/122924576/DE2_TOP.v:457: syntax error, unexpected '(', expecting IDENTIFIER\n  CLOCK_20,\n  ^~~~~~~~\n%Error: data/full_repos/permissive/122924576/DE2_TOP.v:508: syntax error, unexpected '(', expecting IDENTIFIER\n select_x,select_y,\n ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module DE2_TOP
	(

		CLOCK_27,
		CLOCK_50,
		EXT_CLOCK,

		KEY,

		SW,

		HEX0,
		HEX1,
		HEX2,
		HEX3,
		HEX4,
		HEX5,
		HEX6,
		HEX7,

		LEDG,
		LEDR,

		UART_TXD,
		UART_RXD,

		IRDA_TXD,
		IRDA_RXD,

		DRAM_DQ,
		DRAM_ADDR,
		DRAM_LDQM,
		DRAM_UDQM,
		DRAM_WE_N,
		DRAM_CAS_N,
		DRAM_RAS_N,
		DRAM_CS_N,
		DRAM_BA_0,
		DRAM_BA_1,
		DRAM_CLK,
		DRAM_CKE,

		FL_DQ,
		FL_ADDR,
		FL_WE_N,
		FL_RST_N,
		FL_OE_N,
		FL_CE_N,

		SRAM_DQ,
		SRAM_ADDR,
		SRAM_UB_N,
		SRAM_LB_N,
		SRAM_WE_N,
		SRAM_CE_N,
		SRAM_OE_N,

		OTG_DATA,
		OTG_ADDR,
		OTG_CS_N,
		OTG_RD_N,
		OTG_WR_N,
		OTG_RST_N,
		OTG_FSPEED,
		OTG_LSPEED,
		OTG_INT0,
		OTG_INT1,
		OTG_DREQ0,
		OTG_DREQ1,
		OTG_DACK0_N,
		OTG_DACK1_N,

		LCD_ON,
		LCD_BLON,
		LCD_RW,
		LCD_EN,
		LCD_RS,
		LCD_DATA,

		SD_DAT,
		SD_WP_N,
		SD_CMD,
		SD_CLK,

		TDI,
		TCK,
		TCS,
	   TDO,

		I2C_SDAT,
		I2C_SCLK,

		PS2_DAT,
		PS2_CLK,

		VGA_CLK,
		VGA_HS,
		VGA_VS,
		VGA_BLANK,
		VGA_SYNC,
		VGA_R,
		VGA_G,
		VGA_B,

		ENET_DATA,
		ENET_CMD,
		ENET_CS_N,
		ENET_WR_N,
		ENET_RD_N,
		ENET_RST_N,
		ENET_INT,
		ENET_CLK,

		AUD_ADCLRCK,
		AUD_ADCDAT,
		AUD_DACLRCK,
		AUD_DACDAT,
		AUD_BCLK,
		AUD_XCK,

		TD_DATA,
		TD_HS,
		TD_VS,
		TD_RESET,
		TD_CLK27,

		GPIO_0,
		GPIO_1
	);


input		   	CLOCK_27;
input		   	CLOCK_50;
input			   EXT_CLOCK;

input	   [3:0]	KEY;

input	  [17:0]	SW;

output	[6:0]	HEX0;
output	[6:0]	HEX1;
output	[6:0]	HEX2;
output	[6:0]	HEX3;
output	[6:0]	HEX4;
output	[6:0]	HEX5;
output	[6:0]	HEX6;
output	[6:0]	HEX7;

output	[8:0]	LEDG;
output  [17:0]	LEDR;

output			UART_TXD;
input			   UART_RXD;

output			IRDA_TXD;
input			   IRDA_RXD;

inout	  [15:0]	DRAM_DQ;
output  [11:0]	DRAM_ADDR;
output			DRAM_LDQM;
output			DRAM_UDQM;
output			DRAM_WE_N;
output			DRAM_CAS_N;
output			DRAM_RAS_N;
output			DRAM_CS_N;
output			DRAM_BA_0;
output			DRAM_BA_1;
output			DRAM_CLK;
output			DRAM_CKE;

inout	  [7:0]	FL_DQ;
output [21:0]	FL_ADDR;
output			FL_WE_N;
output			FL_RST_N;
output			FL_OE_N;
output			FL_CE_N;

inout	 [15:0]	SRAM_DQ;
output [17:0]	SRAM_ADDR;
output			SRAM_UB_N;
output			SRAM_LB_N;
output			SRAM_WE_N;
output			SRAM_CE_N;
output			SRAM_OE_N;

inout	 [15:0]	OTG_DATA;
output  [1:0]	OTG_ADDR;
output			OTG_CS_N;
output			OTG_RD_N;
output			OTG_WR_N;
output			OTG_RST_N;
output			OTG_FSPEED;
output			OTG_LSPEED;
input			   OTG_INT0;
input			   OTG_INT1;
input			   OTG_DREQ0;
input			   OTG_DREQ1;
output			OTG_DACK0_N;
output			OTG_DACK1_N;

inout	  [7:0]	LCD_DATA;
output			LCD_ON;
output			LCD_BLON;
output			LCD_RW;
output			LCD_EN;
output			LCD_RS;

inout	 [3:0]	SD_DAT;
input			   SD_WP_N;
inout			   SD_CMD;
output			SD_CLK;

inout			   I2C_SDAT;
output			I2C_SCLK;

input		 	   PS2_DAT;
input			   PS2_CLK;

input  			TDI;
input  			TCK;
input  			TCS;
output 			TDO;

output			VGA_CLK;
output			VGA_HS;
output			VGA_VS;
output			VGA_BLANK;
output			VGA_SYNC;
output	[9:0]	VGA_R;
output	[9:0]	VGA_G;
output	[9:0]	VGA_B;

inout	[15:0]	ENET_DATA;
output			ENET_CMD;
output			ENET_CS_N;
output			ENET_WR_N;
output			ENET_RD_N;
output			ENET_RST_N;
input			   ENET_INT;
output			ENET_CLK;

inout			   AUD_ADCLRCK;
input			   AUD_ADCDAT;
inout			   AUD_DACLRCK;
output			AUD_DACDAT;
inout			   AUD_BCLK;
output			AUD_XCK;

input	 [7:0]	TD_DATA;
input			   TD_HS;
input			   TD_VS;
output			TD_RESET;
input          TD_CLK27;

inout	[35:0]	GPIO_0;
inout	[35:0]	GPIO_1;





wire CLOCK_20;

pll_clock (
		CLOCK_50,
		1'b1,
		CLOCK_20
	);

parameter depth=17;

parameter x_width=9;
parameter y_width=x_width;








wire reset;
assign reset = SW[17];
assign LEDG[8] = isWhite;






wire reciveOrderEnd;
wire [5:0] count;

wire isWhite;


wire txdBusy;
wire serialArrayBusy;
wire txdWrite;
wire [7:0] txdData;
wire [8*10 - 1:0] data;
wire rxdReady;
wire [7:0] rxdData;
wire [x_width:0] rel_x_recive, rel_y_recive;
wire [7:0] rel_type_recive;
async_receiver RX(.clk(CLOCK_20), .RxD(UART_RXD), .RxD_data_ready(rxdReady), .RxD_data(rxdData));
async_transmitter TX(.clk(CLOCK_20), .TxD(UART_TXD), .TxD_start(txdWrite), .TxD_busy(txdBusy), .TxD_data(txdData));
serialArraySend(CLOCK_20, reset, data, count, tile_select_ready, txdBusy, txdWrite, txdData, serialArrayBusy);
recieveOrder(rxdData, rxdReady, isWhite, CLOCK_20, reset, rel_x_recive, rel_y_recive, rel_type_recive, reciveOrderEnd);
/
endmodule
module DE2_TOP
	(

		CLOCK_27,
		CLOCK_50,
		EXT_CLOCK,

		KEY,

		SW,

		HEX0,
		HEX1,
		HEX2,
		HEX3,
		HEX4,
		HEX5,
		HEX6,
		HEX7,

		LEDG,
		LEDR,

		UART_TXD,
		UART_RXD,

		IRDA_TXD,
		IRDA_RXD,

		DRAM_DQ,
		DRAM_ADDR,
		DRAM_LDQM,
		DRAM_UDQM,
		DRAM_WE_N,
		DRAM_CAS_N,
		DRAM_RAS_N,
		DRAM_CS_N,
		DRAM_BA_0,
		DRAM_BA_1,
		DRAM_CLK,
		DRAM_CKE,

		FL_DQ,
		FL_ADDR,
		FL_WE_N,
		FL_RST_N,
		FL_OE_N,
		FL_CE_N,

		SRAM_DQ,
		SRAM_ADDR,
		SRAM_UB_N,
		SRAM_LB_N,
		SRAM_WE_N,
		SRAM_CE_N,
		SRAM_OE_N,

		OTG_DATA,
		OTG_ADDR,
		OTG_CS_N,
		OTG_RD_N,
		OTG_WR_N,
		OTG_RST_N,
		OTG_FSPEED,
		OTG_LSPEED,
		OTG_INT0,
		OTG_INT1,
		OTG_DREQ0,
		OTG_DREQ1,
		OTG_DACK0_N,
		OTG_DACK1_N,

		LCD_ON,
		LCD_BLON,
		LCD_RW,
		LCD_EN,
		LCD_RS,
		LCD_DATA,

		SD_DAT,
		SD_WP_N,
		SD_CMD,
		SD_CLK,

		TDI,
		TCK,
		TCS,
	   TDO,

		I2C_SDAT,
		I2C_SCLK,

		PS2_DAT,
		PS2_CLK,

		VGA_CLK,
		VGA_HS,
		VGA_VS,
		VGA_BLANK,
		VGA_SYNC,
		VGA_R,
		VGA_G,
		VGA_B,

		ENET_DATA,
		ENET_CMD,
		ENET_CS_N,
		ENET_WR_N,
		ENET_RD_N,
		ENET_RST_N,
		ENET_INT,
		ENET_CLK,

		AUD_ADCLRCK,
		AUD_ADCDAT,
		AUD_DACLRCK,
		AUD_DACDAT,
		AUD_BCLK,
		AUD_XCK,

		TD_DATA,
		TD_HS,
		TD_VS,
		TD_RESET,
		TD_CLK27,

		GPIO_0,
		GPIO_1
	);



input		   	CLOCK_27;
input		   	CLOCK_50;
input			   EXT_CLOCK;

input	   [3:0]	KEY;

input	  [17:0]	SW;

output	[6:0]	HEX0;
output	[6:0]	HEX1;
output	[6:0]	HEX2;
output	[6:0]	HEX3;
output	[6:0]	HEX4;
output	[6:0]	HEX5;
output	[6:0]	HEX6;
output	[6:0]	HEX7;

output	[8:0]	LEDG;
output  [17:0]	LEDR;

output			UART_TXD;
input			   UART_RXD;

output			IRDA_TXD;
input			   IRDA_RXD;

inout	  [15:0]	DRAM_DQ;
output  [11:0]	DRAM_ADDR;
output			DRAM_LDQM;
output			DRAM_UDQM;
output			DRAM_WE_N;
output			DRAM_CAS_N;
output			DRAM_RAS_N;
output			DRAM_CS_N;
output			DRAM_BA_0;
output			DRAM_BA_1;
output			DRAM_CLK;
output			DRAM_CKE;

inout	  [7:0]	FL_DQ;
output [21:0]	FL_ADDR;
output			FL_WE_N;
output			FL_RST_N;
output			FL_OE_N;
output			FL_CE_N;

inout	 [15:0]	SRAM_DQ;
output [17:0]	SRAM_ADDR;
output			SRAM_UB_N;
output			SRAM_LB_N;
output			SRAM_WE_N;
output			SRAM_CE_N;
output			SRAM_OE_N;

inout	 [15:0]	OTG_DATA;
output  [1:0]	OTG_ADDR;
output			OTG_CS_N;
output			OTG_RD_N;
output			OTG_WR_N;
output			OTG_RST_N;
output			OTG_FSPEED;
output			OTG_LSPEED;
input			   OTG_INT0;
input			   OTG_INT1;
input			   OTG_DREQ0;
input			   OTG_DREQ1;
output			OTG_DACK0_N;
output			OTG_DACK1_N;

inout	  [7:0]	LCD_DATA;
output			LCD_ON;
output			LCD_BLON;
output			LCD_RW;
output			LCD_EN;
output			LCD_RS;

inout	 [3:0]	SD_DAT;
input			   SD_WP_N;
inout			   SD_CMD;
output			SD_CLK;

inout			   I2C_SDAT;
output			I2C_SCLK;

input		 	   PS2_DAT;
input			   PS2_CLK;

input  			TDI;
input  			TCK;
input  			TCS;
output 			TDO;

output			VGA_CLK;
output			VGA_HS;
output			VGA_VS;
output			VGA_BLANK;
output			VGA_SYNC;
output	[9:0]	VGA_R;
output	[9:0]	VGA_G;
output	[9:0]	VGA_B;

inout	[15:0]	ENET_DATA;
output			ENET_CMD;
output			ENET_CS_N;
output			ENET_WR_N;
output			ENET_RD_N;
output			ENET_RST_N;
input			   ENET_INT;
output			ENET_CLK;

inout			   AUD_ADCLRCK;
input			   AUD_ADCDAT;
inout			   AUD_DACLRCK;
output			AUD_DACDAT;
inout			   AUD_BCLK;
output			AUD_XCK;

input	 [7:0]	TD_DATA;
input			   TD_HS;
input			   TD_VS;
output			TD_RESET;
input          TD_CLK27;

inout	[35:0]	GPIO_0;
inout	[35:0]	GPIO_1;





wire CLOCK_20;

pll_clock (
		CLOCK_50,
		1'b1,
		CLOCK_20
	);

parameter depth=17;

parameter x_width=9;
parameter y_width=x_width;








wire reset;
assign reset = SW[17];
assign LEDG[8] = isWhite;






wire reciveOrderEnd;
wire [5:0] count;

wire isWhite;


wire txdBusy;
wire serialArrayBusy;
wire txdWrite;
wire [7:0] txdData;
wire [8*10 - 1:0] data;
wire rxdReady;
wire [7:0] rxdData;
wire [x_width:0] rel_x_recive, rel_y_recive;
wire [7:0] rel_type_recive;
async_receiver RX(.clk(CLOCK_20), .RxD(UART_RXD), .RxD_data_ready(rxdReady), .RxD_data(rxdData));
async_transmitter TX(.clk(CLOCK_20), .TxD(UART_TXD), .TxD_start(txdWrite), .TxD_busy(txdBusy), .TxD_data(txdData));
serialArraySend(CLOCK_20, reset, data, count, tile_select_ready, txdBusy, txdWrite, txdData, serialArrayBusy);
recieveOrder(rxdData, rxdReady, isWhite, CLOCK_20, reset, rel_x_recive, rel_y_recive, rel_type_recive, reciveOrderEnd);
/
endmodule