data/full_repos/permissive/113036182/ALU32bit.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/113036182/ALU32bit.v:560: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'div_8x4\'\nmodule div_8x4 (input[7:0]a,input [3:0]b,output [3:0]q,output[3:0]r,output cout, ovfl);\n       ^~~~~~~\n                                                                      : ... Top module \'ALU_32bitNEW\'\nmodule ALU_32bitNEW (input [4:0]select, input [31:0]a,b, output [31:0]c, output cout,ovfl);\n       ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:72: Signal definition not found, creating implicitly: \'o1\'\n  and(o1,a,~s);\n      ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:73: Signal definition not found, creating implicitly: \'o2\'\n                                                                     : ... Suggested alternative: \'o1\'\n  and(o2,b,s);\n      ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:2: Signal definition not found, creating implicitly: \'o1\'\nxor(o1,a,b);\n    ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:4: Signal definition not found, creating implicitly: \'o2\'\n                                                                    : ... Suggested alternative: \'o1\'\nand(o2,a,b);\n    ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:5: Signal definition not found, creating implicitly: \'o3\'\n                                                                    : ... Suggested alternative: \'o1\'\nand(o3,o1,cin);\n    ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:78: Signal definition not found, creating implicitly: \'c0\'\n  FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n                                 ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'o1\'\n          f2 (a[1],b[1],1\'b0,o1,c1),\n                             ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:79: Signal definition not found, creating implicitly: \'c1\'\n                                                                     : ... Suggested alternative: \'c0\'\n          f2 (a[1],b[1],1\'b0,o1,c1),\n                                ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'o2\'\n                                                                     : ... Suggested alternative: \'o1\'\n          f3 (a[1],b[1],1\'b1,o2,c2);\n                             ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:80: Signal definition not found, creating implicitly: \'c2\'\n                                                                     : ... Suggested alternative: \'c0\'\n          f3 (a[1],b[1],1\'b1,o2,c2);\n                                ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:87: Signal definition not found, creating implicitly: \'c0\'\n  CSA_2bit f1 (a[1:0],b[1:0],cin,s[1:0],c0),\n                                        ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:88: Signal definition not found, creating implicitly: \'c1\'\n                                                                     : ... Suggested alternative: \'c0\'\n           f2 (a[3:2],b[3:2],1\'b0,o1[1:0],c1),\n                                          ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:89: Signal definition not found, creating implicitly: \'c2\'\n                                                                     : ... Suggested alternative: \'c0\'\n           f3 (a[3:2],b[3:2],1\'b1,o2[1:0],c2);\n                                          ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:97: Signal definition not found, creating implicitly: \'c0\'\n  CSA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n                                        ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:98: Signal definition not found, creating implicitly: \'c1\'\n                                                                     : ... Suggested alternative: \'c0\'\n           f2 (a[7:4],b[7:4],1\'b0,o1[3:0],c1),\n                                          ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:99: Signal definition not found, creating implicitly: \'c2\'\n                                                                     : ... Suggested alternative: \'c0\'\n           f3 (a[7:4],b[7:4],1\'b1,o2[3:0],c2);\n                                          ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:163: Signal definition not found, creating implicitly: \'c1\'\n  assign c1=g[0]+(p[0]&cin);\n         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:164: Signal definition not found, creating implicitly: \'c2\'\n                                                                      : ... Suggested alternative: \'c1\'\n  assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:165: Signal definition not found, creating implicitly: \'c3\'\n                                                                      : ... Suggested alternative: \'c1\'\n  assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:109: Signal definition not found, creating implicitly: \'c0\'\n  CSA_8bit f1 (a[7:0],b[7:0],cin,s[7:0],c0),\n                                        ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:110: Signal definition not found, creating implicitly: \'c1\'\n                                                                      : ... Suggested alternative: \'c0\'\n           f2 (a[15:8],b[15:8],1\'b0,o1[7:0],c1),\n                                            ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:111: Signal definition not found, creating implicitly: \'c2\'\n                                                                      : ... Suggested alternative: \'c0\'\n           f3 (a[15:8],b[15:8],1\'b1,o2[7:0],c2);\n                                            ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:45: Signal definition not found, creating implicitly: \'c0\'\n  FA_1bit f1 (a[0],b[0],cin,s[0],c0),\n                                 ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:46: Signal definition not found, creating implicitly: \'c1\'\n                                                                     : ... Suggested alternative: \'c0\'\n          f2 (a[1],b[1],c0,s[1],c1),\n                                ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:47: Signal definition not found, creating implicitly: \'c2\'\n                                                                     : ... Suggested alternative: \'c0\'\n          f3 (a[2],b[2],c1,s[2],c2),\n                                ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:177: Signal definition not found, creating implicitly: \'c1\'\n  assign c1=g[0]+(p[0]&cin);\n         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:178: Signal definition not found, creating implicitly: \'c2\'\n                                                                      : ... Suggested alternative: \'c1\'\n  assign c2=g[1]+(g[0]&p[1])+(cin&p[0]&p[1]);\n         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:179: Signal definition not found, creating implicitly: \'c3\'\n                                                                      : ... Suggested alternative: \'c1\'\n  assign c3=g[2]+(g[1]&p[2])+(g[0]&p[1]&p[2])+(cin&p[0]&p[1]&p[2]);\n         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:183: Signal definition not found, creating implicitly: \'co0\'\n  CLA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],co0,p[0],g[0]),\n                                        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:184: Signal definition not found, creating implicitly: \'co1\'\n                                                                      : ... Suggested alternative: \'c1\'\n           f2 (a[7:4],b[7:4],c1,s[7:4],co1,p[1],g[1]),\n                                       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:185: Signal definition not found, creating implicitly: \'co2\'\n                                                                      : ... Suggested alternative: \'c2\'\n           f3 (a[11:8],b[11:8],c2,s[11:8],co2,p[2],g[2]),\n                                          ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:186: Signal definition not found, creating implicitly: \'co3\'\n                                                                      : ... Suggested alternative: \'c3\'\n           f4 (a[15:12],b[15:12],c3,s[15:12],co3,p[3],g[3]);\n                                             ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:127: Signal definition not found, creating implicitly: \'c0\'\n                                                                      : ... Suggested alternative: \'c\'\n  CSA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n                                           ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:128: Signal definition not found, creating implicitly: \'c1\'\n                                                                      : ... Suggested alternative: \'c\'\n           f2 (a[31:16],c[31:16],1\'b0,o1[15:0],c1),\n                                               ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:129: Signal definition not found, creating implicitly: \'c2\'\n                                                                      : ... Suggested alternative: \'c\'\n           f3 (a[31:16],c[31:16],1\'b1,o2[15:0],c2);\n                                               ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:52: Signal definition not found, creating implicitly: \'c0\'\n  RCA_4bit f1 (a[3:0],b[3:0],cin,s[3:0],c0),\n                                        ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:53: Signal definition not found, creating implicitly: \'c1\'\n                                                                     : ... Suggested alternative: \'c0\'\n           f2 (a[7:4],b[7:4],c0,s[7:4],c1),\n                                       ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:54: Signal definition not found, creating implicitly: \'c2\'\n                                                                     : ... Suggested alternative: \'c0\'\n           f3 (a[11:8],b[11:8],c1,s[11:8],c2),\n                                          ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:193: Signal definition not found, creating implicitly: \'c1\'\n                                                                      : ... Suggested alternative: \'c\'\n  assign c1=g[0]+(p[0]&en);\n         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:195: Signal definition not found, creating implicitly: \'co0\'\n  CLA_16bit f1 (a[15:0],c[15:0],en,s[15:0],co0,p[0],g[0]),\n                                           ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:196: Signal definition not found, creating implicitly: \'co1\'\n                                                                      : ... Suggested alternative: \'c1\'\n            f2 (a[31:16],c[31:16],c1,s[31:16],co1,p[1],g[1]);\n                                              ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/113036182/ALU32bit.v:61: Signal definition not found, creating implicitly: \'c0\'\n                                                                     : ... Suggested alternative: \'c\'\n  RCA_16bit f1 (a[15:0],c[15:0],en,s[15:0],c0),\n                                           ^~\n%Error: Exiting due to 43 warning(s)\n'
module multiplier_8x8 (input [7:0]a,b, output [31:0]s,output cout,ovfl);
wire [31:0]r0,r1,r2,r3,r4,r5,r6,r7,k1,k2,k3,k4,k5,k6,k7,l3,l7,m6,m5,m7,s1,s2,s3,s4,s5,s6,s7;
wire c1,c2,c3,c4,c5,c6,c7;
wire [25:8]o;
wire [19:8]c;
assign cout=1'b0;
assign ovfl=1'b0;
multiplier_8x1 n0 (a[7:0],b[0],r0[7:0]),
               n1 (a[7:0],b[1],k1[7:0]),
               n2 (a[7:0],b[2],k2[7:0]),
               n3 (a[7:0],b[3],k3[7:0]),
               n4 (a[7:0],b[4],k4[7:0]),
               n5 (a[7:0],b[5],k5[7:0]),
               n6 (a[7:0],b[6],k6[7:0]),
               n7 (a[7:0],b[7],k7[7:0]);
ShiftLLogical1 p1 (k1[31:0],r1[31:0],c[8],o[8]),
               p3 (l3[31:0],r3[31:0],c[9],o[9]),
               p5 (m5[31:0],r5[31:0],c[10],o[10]),
               p7 (l7[31:0],r7[31:0],c[11],o[11]);
ShiftLLogical2 t2 (k2[31:0],r2[31:0],c[12],o[12]),
               t3 (k3[31:0],l3[31:0],c[13],o[13]),
               t6 (m6[31:0],r6[31:0],c[14],o[14]),
               t7 (m7[31:0],l7[31:0],c[15],o[15]);
ShiftLLogical4 u4 (k4[31:0],r4[31:0],c[16],o[16]),
               u5 (k5[31:0],m5[31:0],c[17],o[17]),
               u6 (k6[31:0],m6[31:0],c[18],o[18]),
               u7 (k7[31:0],m7[31:0],c[19],o[19]);
CSA_32bit add0 (r0[31:0],r1[31:0],1'b0,s1[31:0],c1,o[20]),
          add1 (s1[31:0],r2[31:0],1'b0,s2[31:0],c2,o[21]),
          add2 (s2[31:0],r3[31:0],1'b0,s3[31:0],c3,o[22]),
          add3 (s3[31:0],r4[31:0],1'b0,s4[31:0],c4,o[23]),
          add4 (s4[31:0],r5[31:0],1'b0,s5[31:0],c5,o[24]),
          add5 (s5[31:0],r6[31:0],1'b0,s6[31:0],c6,o[25]),
          add6 (s6[31:0],r7[31:0],1'b0,s7[31:0],c7,o[25]);
assign r0[31:8]=24'b0;
assign r1[31:9]=23'b0;
assign r2[31:10]=22'b0;
assign r3[31:11]=21'b0;
assign r4[31:12]=20'b0;
assign r5[31:13]=19'b0;
assign r6[31:14]=18'b0;
assign r7[31:15]=17'b0;
assign s=s7;
endmodule
module multiplier_8x8 (input [7:0]a,b, output [31:0]s,output cout,ovfl);

wire [31:0]r0,r1,r2,r3,r4,r5,r6,r7,k1,k2,k3,k4,k5,k6,k7,l3,l7,m6,m5,m7,s1,s2,s3,s4,s5,s6,s7;
wire c1,c2,c3,c4,c5,c6,c7;
wire [25:8]o;
wire [19:8]c;
assign cout=1'b0;
assign ovfl=1'b0;
multiplier_8x1 n0 (a[7:0],b[0],r0[7:0]),
               n1 (a[7:0],b[1],k1[7:0]),
               n2 (a[7:0],b[2],k2[7:0]),
               n3 (a[7:0],b[3],k3[7:0]),
               n4 (a[7:0],b[4],k4[7:0]),
               n5 (a[7:0],b[5],k5[7:0]),
               n6 (a[7:0],b[6],k6[7:0]),
               n7 (a[7:0],b[7],k7[7:0]);
ShiftLLogical1 p1 (k1[31:0],r1[31:0],c[8],o[8]),
               p3 (l3[31:0],r3[31:0],c[9],o[9]),
               p5 (m5[31:0],r5[31:0],c[10],o[10]),
               p7 (l7[31:0],r7[31:0],c[11],o[11]);
ShiftLLogical2 t2 (k2[31:0],r2[31:0],c[12],o[12]),
               t3 (k3[31:0],l3[31:0],c[13],o[13]),
               t6 (m6[31:0],r6[31:0],c[14],o[14]),
               t7 (m7[31:0],l7[31:0],c[15],o[15]);
ShiftLLogical4 u4 (k4[31:0],r4[31:0],c[16],o[16]),
               u5 (k5[31:0],m5[31:0],c[17],o[17]),
               u6 (k6[31:0],m6[31:0],c[18],o[18]),
               u7 (k7[31:0],m7[31:0],c[19],o[19]);
CSA_32bit add0 (r0[31:0],r1[31:0],1'b0,s1[31:0],c1,o[20]),
          add1 (s1[31:0],r2[31:0],1'b0,s2[31:0],c2,o[21]),
          add2 (s2[31:0],r3[31:0],1'b0,s3[31:0],c3,o[22]),
          add3 (s3[31:0],r4[31:0],1'b0,s4[31:0],c4,o[23]),
          add4 (s4[31:0],r5[31:0],1'b0,s5[31:0],c5,o[24]),
          add5 (s5[31:0],r6[31:0],1'b0,s6[31:0],c6,o[25]),
          add6 (s6[31:0],r7[31:0],1'b0,s7[31:0],c7,o[25]);
assign r0[31:8]=24'b0;
assign r1[31:9]=23'b0;
assign r2[31:10]=22'b0;
assign r3[31:11]=21'b0;
assign r4[31:12]=20'b0;
assign r5[31:13]=19'b0;
assign r6[31:14]=18'b0;
assign r7[31:15]=17'b0;
assign s=s7;
endmodule