data/full_repos/permissive/204937464/lib/verilog/vector_max.v
data/verilator_xmls/2028cc2c-068d-4815-b5f7-f8eee084a43b.xml
module vector_max(
        clk,
        rst,
        op_din_en,
        op_din_eop,
        op_din,
        op_dout
);




parameter RELU = 0;
parameter DIN_W = 16;
parameter Q = 8;




input clk;
input rst;
input op_din_en;
input op_din_eop;
input signed [DIN_W-1:0] op_din;
output signed [DIN_W-1:0] op_dout; 
 



reg op_din_eop_d1;
always @ (posedge clk)
begin
  if(rst)
    op_din_eop_d1 <= 1'b0;
  else
    op_din_eop_d1 <= op_din_eop;
end



reg signed [DIN_W-1:0] op_dout_tmp; 
always @ (posedge clk)
begin
  if(rst)
    op_dout_tmp <= {DIN_W{1'b0}};
  else if ((op_din_eop_d1 == 1'b1) && (op_din_en == 1'b1))
    op_dout_tmp <= op_din;
  else if ((op_din_eop_d1 == 1'b1) && (op_din_en == 1'b0))
    op_dout_tmp <= {1'b1, {(DIN_W-1){1'b0}}};
  else if ((op_din_eop_d1 == 1'b0) && (op_din_en == 1'b1))
    op_dout_tmp <= op_dout_tmp > op_din ? op_dout_tmp : op_din;
  else  
    op_dout_tmp <= op_dout_tmp;	
end




assign op_dout = RELU ? (op_dout_tmp[DIN_W-1] ? 0 : op_dout_tmp) : op_dout_tmp;

endmodule
module vector_max(
        clk,
        rst,
        op_din_en,
        op_din_eop,
        op_din,
        op_dout
);





parameter RELU = 0;
parameter DIN_W = 16;
parameter Q = 8;




input clk;
input rst;
input op_din_en;
input op_din_eop;
input signed [DIN_W-1:0] op_din;
output signed [DIN_W-1:0] op_dout; 
 



reg op_din_eop_d1;
always @ (posedge clk)
begin
  if(rst)
    op_din_eop_d1 <= 1'b0;
  else
    op_din_eop_d1 <= op_din_eop;
end



reg signed [DIN_W-1:0] op_dout_tmp; 
always @ (posedge clk)
begin
  if(rst)
    op_dout_tmp <= {DIN_W{1'b0}};
  else if ((op_din_eop_d1 == 1'b1) && (op_din_en == 1'b1))
    op_dout_tmp <= op_din;
  else if ((op_din_eop_d1 == 1'b1) && (op_din_en == 1'b0))
    op_dout_tmp <= {1'b1, {(DIN_W-1){1'b0}}};
  else if ((op_din_eop_d1 == 1'b0) && (op_din_en == 1'b1))
    op_dout_tmp <= op_dout_tmp > op_din ? op_dout_tmp : op_din;
  else  
    op_dout_tmp <= op_dout_tmp;	
end




assign op_dout = RELU ? (op_dout_tmp[DIN_W-1] ? 0 : op_dout_tmp) : op_dout_tmp;

endmodule