data/full_repos/permissive/143278/ivltests/bitsel.v
data/verilator_xmls/08cccad9-87b2-41f0-b1ad-35bc8a3311fa.xml
module m;

  reg [15:8] r;
  integer i;

initial
  begin
    r = 8'b01101001;
    for (i = 8; i <= 15; i = i + 1)
      $display(r[i]);
  end

endmodule
module m;


  reg [15:8] r;
  integer i;

initial
  begin
    r = 8'b01101001;
    for (i = 8; i <= 15; i = i + 1)
      $display(r[i]);
  end

endmodule