data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v
1: b'%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:46: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                         : ... In instance start\n            grant[4:0] = prio[24:20];\n                             ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:46: Extracting 5 bits from only 1 bit number\n                                                                         : ... In instance start\n            grant[4:0] = prio[24:20];\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:46: Selection index out of range: 24:20 outside 4:0\n                                                                                    : ... In instance start\n            grant[4:0] = prio[24:20];\n                             ^\n                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:46: Selection index out of range: 8:4 outside 4:0\n                                                                                    : ... In instance start\n            grant[4:0] = prio[24:20];\n                             ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:49: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                         : ... In instance start\n            grant[4:0] = prio[19:15];\n                             ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:49: Extracting 5 bits from only 1 bit number\n                                                                         : ... In instance start\n            grant[4:0] = prio[19:15];\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:49: Selection index out of range: 19:15 outside 4:0\n                                                                                    : ... In instance start\n            grant[4:0] = prio[19:15];\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:49: Selection index out of range: 11:7 outside 4:0\n                                                                                    : ... In instance start\n            grant[4:0] = prio[19:15];\n                             ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:52: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                         : ... In instance start\n            grant[4:0] = prio[14:10];\n                             ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:52: Extracting 5 bits from only 1 bit number\n                                                                         : ... In instance start\n            grant[4:0] = prio[14:10];\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:52: Selection index out of range: 14:10 outside 4:0\n                                                                                    : ... In instance start\n            grant[4:0] = prio[14:10];\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:52: Selection index out of range: 6:2 outside 4:0\n                                                                                    : ... In instance start\n            grant[4:0] = prio[14:10];\n                             ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:55: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                         : ... In instance start\n            grant[4:0] = prio[9:5];\n                             ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:55: Extracting 5 bits from only 1 bit number\n                                                                         : ... In instance start\n            grant[4:0] = prio[9:5];\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:55: Selection index out of range: 9:5 outside 4:0\n                                                                                    : ... In instance start\n            grant[4:0] = prio[9:5];\n                             ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:58: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                         : ... In instance start\n            grant[4:0] = prio[4:0];\n                             ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:58: Extracting 5 bits from only 1 bit number\n                                                                         : ... In instance start\n            grant[4:0] = prio[4:0];\n                             ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:57: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                         : ... In instance start\n        else if(busreq_final & prio[4:0]) begin\n                                   ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:57: Extracting 5 bits from only 1 bit number\n                                                                         : ... In instance start\n        else if(busreq_final & prio[4:0]) begin\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:57: Operator AND expects 16 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                                 : ... In instance start\n        else if(busreq_final & prio[4:0]) begin\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:57: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 16 bits.\n                                                                                 : ... In instance start\n        else if(busreq_final & prio[4:0]) begin\n             ^~\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:54: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                         : ... In instance start\n        else if(busreq_final & prio[9:5]) begin\n                                   ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:54: Extracting 5 bits from only 1 bit number\n                                                                         : ... In instance start\n        else if(busreq_final & prio[9:5]) begin\n                                   ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:54: Selection index out of range: 9:5 outside 4:0\n                                                                                    : ... In instance start\n        else if(busreq_final & prio[9:5]) begin\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:54: Operator AND expects 16 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                                 : ... In instance start\n        else if(busreq_final & prio[9:5]) begin\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:54: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 16 bits.\n                                                                                 : ... In instance start\n        else if(busreq_final & prio[9:5]) begin\n             ^~\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:51: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                         : ... In instance start\n        else if(busreq_final & prio[14:10]) begin\n                                   ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:51: Extracting 5 bits from only 1 bit number\n                                                                         : ... In instance start\n        else if(busreq_final & prio[14:10]) begin\n                                   ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:51: Selection index out of range: 14:10 outside 4:0\n                                                                                    : ... In instance start\n        else if(busreq_final & prio[14:10]) begin\n                                   ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:51: Selection index out of range: 6:2 outside 4:0\n                                                                                    : ... In instance start\n        else if(busreq_final & prio[14:10]) begin\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:51: Operator AND expects 16 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                                 : ... In instance start\n        else if(busreq_final & prio[14:10]) begin\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:51: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 16 bits.\n                                                                                 : ... In instance start\n        else if(busreq_final & prio[14:10]) begin\n             ^~\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:48: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                         : ... In instance start\n        else if(busreq_final & prio[19:15]) begin\n                                   ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:48: Extracting 5 bits from only 1 bit number\n                                                                         : ... In instance start\n        else if(busreq_final & prio[19:15]) begin\n                                   ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:48: Selection index out of range: 19:15 outside 4:0\n                                                                                    : ... In instance start\n        else if(busreq_final & prio[19:15]) begin\n                                   ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:48: Selection index out of range: 11:7 outside 4:0\n                                                                                    : ... In instance start\n        else if(busreq_final & prio[19:15]) begin\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:48: Operator AND expects 16 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                                 : ... In instance start\n        else if(busreq_final & prio[19:15]) begin\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:48: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 16 bits.\n                                                                                 : ... In instance start\n        else if(busreq_final & prio[19:15]) begin\n             ^~\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:45: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                         : ... In instance start\n        if(busreq_final & prio[24:20]) begin\n                              ^\n%Error: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:45: Extracting 5 bits from only 1 bit number\n                                                                         : ... In instance start\n        if(busreq_final & prio[24:20]) begin\n                              ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:45: Selection index out of range: 24:20 outside 4:0\n                                                                                    : ... In instance start\n        if(busreq_final & prio[24:20]) begin\n                              ^\n%Warning-SELRANGE: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:45: Selection index out of range: 8:4 outside 4:0\n                                                                                    : ... In instance start\n        if(busreq_final & prio[24:20]) begin\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:45: Operator AND expects 16 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                                 : ... In instance start\n        if(busreq_final & prio[24:20]) begin\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/176449044/AHB/AHB_SV_TB/rtl/start.v:45: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 16 bits.\n                                                                                 : ... In instance start\n        if(busreq_final & prio[24:20]) begin\n        ^~\n%Error: Exiting due to 20 error(s), 24 warning(s)\n'
module start (
    input hclk,
    input hrst_n,

    input [15:0]  hbusreqx,
    input [15:0]  hlockx,
    input [15:0]  hsplitx,

    input [1:0]  hresp,
    input        prio,
    output reg [15:0] grant
);

parameter   OKAY = 2'b00;
parameter   ERROR = 2'b01;
parameter   RETRY = 2'b10;
parameter   SPLIT = 2'b11;

reg [15:0] busreq_q;
reg [15:0] split_q;
wire [15:0] busreq_shield;
wire [15:0] busreq_final;

always @(posedge hclk or negedge hrst_n) begin
    if(~hrst_n) begin

        busreq_q <= 'h0;
        split_q <= 'h0;
    end
    else begin
        busreq_q <= hbusreqx;
        split_q <= hsplitx;

    end
end

assign busreq_final = (split_q != 0)?split_q:busreq_q;



always @(hlockx or hresp or prio) begin
    if(hresp == OKAY && hlockx == 0) begin
        if(busreq_final & prio[24:20]) begin
            grant[4:0] = prio[24:20];
        end
        else if(busreq_final & prio[19:15]) begin
            grant[4:0] = prio[19:15];
        end
        else if(busreq_final & prio[14:10]) begin
            grant[4:0] = prio[14:10];
        end
        else if(busreq_final & prio[9:5]) begin
            grant[4:0] = prio[9:5];
        end
        else if(busreq_final & prio[4:0]) begin
            grant[4:0] = prio[4:0];
        end
    end
end

endmodule
module start (
    input hclk,
    input hrst_n,

    input [15:0]  hbusreqx,
    input [15:0]  hlockx,
    input [15:0]  hsplitx,

    input [1:0]  hresp,
    input        prio,
    output reg [15:0] grant
);


parameter   OKAY = 2'b00;
parameter   ERROR = 2'b01;
parameter   RETRY = 2'b10;
parameter   SPLIT = 2'b11;

reg [15:0] busreq_q;
reg [15:0] split_q;
wire [15:0] busreq_shield;
wire [15:0] busreq_final;

always @(posedge hclk or negedge hrst_n) begin
    if(~hrst_n) begin

        busreq_q <= 'h0;
        split_q <= 'h0;
    end
    else begin
        busreq_q <= hbusreqx;
        split_q <= hsplitx;

    end
end

assign busreq_final = (split_q != 0)?split_q:busreq_q;



always @(hlockx or hresp or prio) begin
    if(hresp == OKAY && hlockx == 0) begin
        if(busreq_final & prio[24:20]) begin
            grant[4:0] = prio[24:20];
        end
        else if(busreq_final & prio[19:15]) begin
            grant[4:0] = prio[19:15];
        end
        else if(busreq_final & prio[14:10]) begin
            grant[4:0] = prio[14:10];
        end
        else if(busreq_final & prio[9:5]) begin
            grant[4:0] = prio[9:5];
        end
        else if(busreq_final & prio[4:0]) begin
            grant[4:0] = prio[4:0];
        end
    end
end

endmodule