data/full_repos/permissive/191565347/vote7/vote7.v
1: b'%Warning-WIDTH: data/full_repos/permissive/191565347/vote7/vote7.v:8: Operator ADD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                    : ... In instance vote7\n  T=I[0]+I[1]+I[2]+I[3]+I[4]+I[5]+I[6];\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/191565347/vote7/vote7.v:8: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                    : ... In instance vote7\n  T=I[0]+I[1]+I[2]+I[3]+I[4]+I[5]+I[6];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/191565347/vote7/vote7.v:8: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                    : ... In instance vote7\n  T=I[0]+I[1]+I[2]+I[3]+I[4]+I[5]+I[6];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/191565347/vote7/vote7.v:8: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                    : ... In instance vote7\n  T=I[0]+I[1]+I[2]+I[3]+I[4]+I[5]+I[6];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/191565347/vote7/vote7.v:8: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                    : ... In instance vote7\n  T=I[0]+I[1]+I[2]+I[3]+I[4]+I[5]+I[6];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/191565347/vote7/vote7.v:8: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                    : ... In instance vote7\n  T=I[0]+I[1]+I[2]+I[3]+I[4]+I[5]+I[6];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/191565347/vote7/vote7.v:8: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                    : ... In instance vote7\n  T=I[0]+I[1]+I[2]+I[3]+I[4]+I[5]+I[6];\n                                 ^\n%Error: Exiting due to 7 warning(s)\n'
module vote7(O,I);
	output O;
	input[6:0] I;
	
	integer T;
	reg O;
	always@(I) begin
		T=I[0]+I[1]+I[2]+I[3]+I[4]+I[5]+I[6];
		if(T>3) O=1'b1;
		else O=1'b0;
	end
endmodule
module vote7(O,I);

	output O;
	input[6:0] I;
	
	integer T;
	reg O;
	always@(I) begin
		T=I[0]+I[1]+I[2]+I[3]+I[4]+I[5]+I[6];
		if(T>3) O=1'b1;
		else O=1'b0;
	end
endmodule