data/full_repos/permissive/160424330/bcd_tb.v
 line:72: before: "("
1: b'%Error: data/full_repos/permissive/160424330/bcd_tb.v:1: Cannot find include file: bcd.v\n`include "bcd.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160424330,data/full_repos/permissive/160424330/bcd.v\n             data/full_repos/permissive/160424330,data/full_repos/permissive/160424330/bcd.v.v\n             data/full_repos/permissive/160424330,data/full_repos/permissive/160424330/bcd.v.sv\n             bcd.v\n             bcd.v.v\n             bcd.v.sv\n             obj_dir/bcd.v\n             obj_dir/bcd.v.v\n             obj_dir/bcd.v.sv\n%Error: data/full_repos/permissive/160424330/bcd_tb.v:2: Cannot find include file: utils.v\n`include "utils.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/160424330/bcd_tb.v:12: Unsupported or unknown PLI call: $monitor\n    $monitor($time, " %d -> %d %d %d", abc, a, b, c);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/160424330/bcd_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile(`VCD_FILE);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/160424330/bcd_tb.v:13: Define or directive not defined: \'`VCD_FILE\'\n    $dumpfile(`VCD_FILE);\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/160424330/bcd_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/160424330/bcd_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160424330/bcd_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #1 $finish;\n    ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module top;
  reg [7:0] abc = 0;
  wire [1:0] a;
  wire [3:0] b, c;

  bcd bcd0(abc, a, b, c);

  initial begin
    $monitor($time, " %d -> %d %d %d", abc, a, b, c);
    $dumpfile(`VCD_FILE);
    $dumpvars;

    repeat (256) begin
      #1;
      utils.assert_equal(abc, a * 100 + b * 10 + c);
      utils.assert_true(a < 10 && b < 10 && c < 10);

      abc += 1;
    end
    #1 $finish;
  end
endmodule
module top;

  reg [7:0] abc = 0;
  wire [1:0] a;
  wire [3:0] b, c;

  bcd bcd0(abc, a, b, c);

  initial begin
    $monitor($time, " %d -> %d %d %d", abc, a, b, c);
    $dumpfile(`VCD_FILE);
    $dumpvars;

    repeat (256) begin
      #1;
      utils.assert_equal(abc, a * 100 + b * 10 + c);
      utils.assert_true(a < 10 && b < 10 && c < 10);

      abc += 1;
    end
    #1 $finish;
  end
endmodule