data/full_repos/permissive/21438680/DAQ_Firmware/modelsim/flash_interface_testbench.v
 line:162 column:2: Illegal character '\x00'
1: b'%Warning-STMTDLY: data/full_repos/permissive/21438680/DAQ_Firmware/modelsim/flash_interface_testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\nalways #( CLK_PERIOD/2.0 )\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/modelsim/flash_interface_testbench.v:139: Cannot find file containing module: \'flash_interface\'\nflash_interface flash_interface_inst(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21438680/DAQ_Firmware/modelsim,data/full_repos/permissive/21438680/flash_interface\n             data/full_repos/permissive/21438680/DAQ_Firmware/modelsim,data/full_repos/permissive/21438680/flash_interface.v\n             data/full_repos/permissive/21438680/DAQ_Firmware/modelsim,data/full_repos/permissive/21438680/flash_interface.sv\n             flash_interface\n             flash_interface.v\n             flash_interface.sv\n             obj_dir/flash_interface\n             obj_dir/flash_interface.v\n             obj_dir/flash_interface.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module flash_interface_testbench (

);

parameter CLK_PERIOD = 10;
integer i;

reg clk;
reg reset;

reg  [7:0] instruction;
reg        execute;
reg  [7:0] bytes_to_read;
reg  [7:0] write_buffer_data;
reg        write_buffer_write;
reg        read_buffer_read;

reg  [7:0] instruction_shifter;
reg  [7:0] data_shifter;
reg  [15:0] out_shifter;
reg        word_complete;

wire       busy;
wire [7:0] read_buffer_q;
wire       read_buffer_empty;

wire       flash_c;
wire       flash_sb;
wire [3:0] flash_dq;

wire sout;
reg sin;

assign sout = flash_dq[0];
assign flash_dq[1] = sin;


initial clk = 1'b0;
always #( CLK_PERIOD/2.0 )
  clk = ~clk;

initial i = 0;

initial reset = 1'b1;
always @( posedge clk ) begin
  i = i + 1;
  execute <= 0;
  write_buffer_write <= 0;
  bytes_to_read <= 0;
  bytes_to_read <= 0;
  if ( i == 2 )
    reset <= 1'b0;

  if ( i == 4 ) begin
    write_buffer_data <= 8'hFF;
    write_buffer_write <= 1;
  end

  if ( i == 5 ) begin
    write_buffer_data <= 8'h22;
    write_buffer_write <= 1;
  end

  if ( i == 6 ) begin
    instruction <= 8'hAA;
    execute <= 1;
    bytes_to_read <= 2;
  end
  if ( ~read_buffer_empty ) begin
    read_buffer_read <= 1;
  end
end

integer clk_cnt;
integer words_received;

always @(posedge flash_c or negedge flash_c) begin
  if ( flash_sb ) begin
    instruction_shifter <= 0;
    data_shifter <= 0;
    clk_cnt <= 0;
    word_complete <= 0;
    words_received <= 0;
    out_shifter <= 16'hBEEF;
  end
  else begin
    if ( flash_c ) begin
      clk_cnt <= clk_cnt + 1;
      if ( clk_cnt < 8 ) begin
        instruction_shifter <= {instruction_shifter[6:0], sout};
      end
      else begin
        data_shifter <= {data_shifter[6:0], sout};
        if ( ((clk_cnt+1) % 8) == 0 ) begin
          word_complete <= 1;
          words_received <= words_received + 1;
        end
        else begin
          word_complete <= 0;
        end
      end
    end
    else begin
      if ( words_received >= 2 ) begin
        sin <= out_shifter[15];
        out_shifter <= {out_shifter[14:0], out_shifter[15]};
      end
    end
  end
end

flash_interface flash_interface_inst(
  .clk ( clk ),
  .reset ( reset ),

  .instruction ( instruction ),
  .execute ( execute ),
  .bytes_to_read ( bytes_to_read ),
  .busy ( busy ),

  .write_buffer_data ( write_buffer_data ),
  .write_buffer_write ( write_buffer_write ),

  .read_buffer_q ( read_buffer_q ),
  .read_buffer_empty ( read_buffer_empty ),
  .read_buffer_read ( read_buffer_read ),

  .flash_c ( flash_c ),
  .flash_sb ( flash_sb ),
  .flash_dq ( flash_dq )
);


endmodule
module flash_interface_testbench (

);


parameter CLK_PERIOD = 10;
integer i;

reg clk;
reg reset;

reg  [7:0] instruction;
reg        execute;
reg  [7:0] bytes_to_read;
reg  [7:0] write_buffer_data;
reg        write_buffer_write;
reg        read_buffer_read;

reg  [7:0] instruction_shifter;
reg  [7:0] data_shifter;
reg  [15:0] out_shifter;
reg        word_complete;

wire       busy;
wire [7:0] read_buffer_q;
wire       read_buffer_empty;

wire       flash_c;
wire       flash_sb;
wire [3:0] flash_dq;

wire sout;
reg sin;

assign sout = flash_dq[0];
assign flash_dq[1] = sin;


initial clk = 1'b0;
always #( CLK_PERIOD/2.0 )
  clk = ~clk;

initial i = 0;

initial reset = 1'b1;
always @( posedge clk ) begin
  i = i + 1;
  execute <= 0;
  write_buffer_write <= 0;
  bytes_to_read <= 0;
  bytes_to_read <= 0;
  if ( i == 2 )
    reset <= 1'b0;

  if ( i == 4 ) begin
    write_buffer_data <= 8'hFF;
    write_buffer_write <= 1;
  end

  if ( i == 5 ) begin
    write_buffer_data <= 8'h22;
    write_buffer_write <= 1;
  end

  if ( i == 6 ) begin
    instruction <= 8'hAA;
    execute <= 1;
    bytes_to_read <= 2;
  end
  if ( ~read_buffer_empty ) begin
    read_buffer_read <= 1;
  end
end

integer clk_cnt;
integer words_received;

always @(posedge flash_c or negedge flash_c) begin
  if ( flash_sb ) begin
    instruction_shifter <= 0;
    data_shifter <= 0;
    clk_cnt <= 0;
    word_complete <= 0;
    words_received <= 0;
    out_shifter <= 16'hBEEF;
  end
  else begin
    if ( flash_c ) begin
      clk_cnt <= clk_cnt + 1;
      if ( clk_cnt < 8 ) begin
        instruction_shifter <= {instruction_shifter[6:0], sout};
      end
      else begin
        data_shifter <= {data_shifter[6:0], sout};
        if ( ((clk_cnt+1) % 8) == 0 ) begin
          word_complete <= 1;
          words_received <= words_received + 1;
        end
        else begin
          word_complete <= 0;
        end
      end
    end
    else begin
      if ( words_received >= 2 ) begin
        sin <= out_shifter[15];
        out_shifter <= {out_shifter[14:0], out_shifter[15]};
      end
    end
  end
end

flash_interface flash_interface_inst(
  .clk ( clk ),
  .reset ( reset ),

  .instruction ( instruction ),
  .execute ( execute ),
  .bytes_to_read ( bytes_to_read ),
  .busy ( busy ),

  .write_buffer_data ( write_buffer_data ),
  .write_buffer_write ( write_buffer_write ),

  .read_buffer_q ( read_buffer_q ),
  .read_buffer_empty ( read_buffer_empty ),
  .read_buffer_read ( read_buffer_read ),

  .flash_c ( flash_c ),
  .flash_sb ( flash_sb ),
  .flash_dq ( flash_dq )
);


endmodule