data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/UDC_tb.v
 line:30: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/UDC_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/UDC_tb.v:30: syntax error, unexpected \'@\'\n repeat(5) @(posedge clk);\n           ^\n%Error: data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/UDC_tb.v:32: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/UDC_tb.v:36: syntax error, unexpected \'@\'\n  repeat(datasize) @(dataOut) begin\n                   ^\n%Error: data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/UDC_tb.v:47: syntax error, unexpected \'=\', expecting IDENTIFIER\n upDown    = 0;\n           ^\n%Error: data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/UDC_tb.v:50: syntax error, unexpected \'=\', expecting IDENTIFIER\n   jj = 10;\n      ^\n%Error: data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/UDC_tb.v:53: syntax error, unexpected \'=\', expecting IDENTIFIER\n   jj = 11;\n      ^\n%Error: data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/UDC_tb.v:56: syntax error, unexpected \'=\', expecting IDENTIFIER\n  flag = 1;\n       ^\n%Error: data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/UDC_tb.v:61: syntax error, unexpected $display\n    $display("Output ERROR at time %d, expected %b, received %b", $time, data[jj], dataOut);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/UDC_tb.v:64: syntax error, unexpected $display\n    $display("Output CORRECT at time %d, expected %b, received %b", $time, data[jj], dataOut);\n    ^~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module UDC_tb;

reg clk, rst, upDown;
wire [7:0] dataOut;
wire [3:0] anodeOut;
reg [7:0] data [0:63];
reg [7:0] datasize;
reg [7:0] repeatNum;

integer errorFlag, ii, jj, flag;

initial $readmemb("patterns", data);


UDC DUT(.upDown(upDown), .clk(clk), .rst(rst), .sevenSegment(dataOut), .anode(anodeOut));

initial begin
	clk = 1;
	forever
		#5 clk = ~clk;
end

initial begin
	datasize  = data[0];
	errorFlag = 0;
	flag 		 = 0;
	rst       = 0;
	upDown    = 1;
	repeat(5) @(posedge clk);
	rst       <= #1 1;
	@(posedge clk);
	rst       <= #1 0;
	for(ii = 0; ii<5; ii = ii +1) begin
		jj = 0;
		repeat(datasize) @(dataOut) begin
			@(negedge clk);
			jj = jj + 1;
			if(dataOut !== data[jj]) begin
				$display("Output ERROR at time %d, expected %b, received %b", $time, data[jj], dataOut);
				errorFlag = errorFlag +1;
			end
			else
				$display("Output CORRECT at time %d, expected %b, received %b", $time, data[jj], dataOut);
		end
	end
	upDown    = 0;
	for(ii = 0; ii<5; ii = ii +1) begin
		if(flag==0) begin
			jj = 10;
			repeatNum = datasize-1;
		end else begin
			jj = 11;
			repeatNum = datasize;
		end
		flag = 1;
		repeat(repeatNum) @(dataOut) begin
			@(negedge clk);
			jj = jj - 1;
			if(dataOut !== data[jj]) begin
				$display("Output ERROR at time %d, expected %b, received %b", $time, data[jj], dataOut);
				errorFlag = errorFlag +1;
			end else
				$display("Output CORRECT at time %d, expected %b, received %b", $time, data[jj], dataOut);
		end
	end
	if(errorFlag == 0)
		$display("No ERRORs Found!");
	else
		$display("%d ERRORs Found!", errorFlag);
	$finish;
end
endmodule
module UDC_tb;


reg clk, rst, upDown;
wire [7:0] dataOut;
wire [3:0] anodeOut;
reg [7:0] data [0:63];
reg [7:0] datasize;
reg [7:0] repeatNum;

integer errorFlag, ii, jj, flag;

initial $readmemb("patterns", data);


UDC DUT(.upDown(upDown), .clk(clk), .rst(rst), .sevenSegment(dataOut), .anode(anodeOut));

initial begin
	clk = 1;
	forever
		#5 clk = ~clk;
end

initial begin
	datasize  = data[0];
	errorFlag = 0;
	flag 		 = 0;
	rst       = 0;
	upDown    = 1;
	repeat(5) @(posedge clk);
	rst       <= #1 1;
	@(posedge clk);
	rst       <= #1 0;
	for(ii = 0; ii<5; ii = ii +1) begin
		jj = 0;
		repeat(datasize) @(dataOut) begin
			@(negedge clk);
			jj = jj + 1;
			if(dataOut !== data[jj]) begin
				$display("Output ERROR at time %d, expected %b, received %b", $time, data[jj], dataOut);
				errorFlag = errorFlag +1;
			end
			else
				$display("Output CORRECT at time %d, expected %b, received %b", $time, data[jj], dataOut);
		end
	end
	upDown    = 0;
	for(ii = 0; ii<5; ii = ii +1) begin
		if(flag==0) begin
			jj = 10;
			repeatNum = datasize-1;
		end else begin
			jj = 11;
			repeatNum = datasize;
		end
		flag = 1;
		repeat(repeatNum) @(dataOut) begin
			@(negedge clk);
			jj = jj - 1;
			if(dataOut !== data[jj]) begin
				$display("Output ERROR at time %d, expected %b, received %b", $time, data[jj], dataOut);
				errorFlag = errorFlag +1;
			end else
				$display("Output CORRECT at time %d, expected %b, received %b", $time, data[jj], dataOut);
		end
	end
	if(errorFlag == 0)
		$display("No ERRORs Found!");
	else
		$display("%d ERRORs Found!", errorFlag);
	$finish;
end
endmodule