data/full_repos/permissive/12186543/rtl/fx3_bus_in_path.v
data/verilator_xmls/fc22368b-c2ea-4d1a-ad46-9b12cbbfda3e.xml
module fx3_bus_in_path (
input               clk,
input               rst,



input               i_read_flow_cntrl,

input       [23:0]  i_packet_size,




output              o_output_enable,
output              o_read_enable,


output              o_data_valid,
input               i_in_path_enable,
output              o_in_path_busy,
output              o_in_path_finished
);



localparam IDLE                   = 4'h0;
localparam READ                   = 4'h1;
localparam READ_OE_DELAY          = 4'h2;
localparam FINISHED               = 4'h3;


reg         [3:0]   state;
reg         [3:0]   next_state;

reg         [23:0]  r_read_count;
reg         [1:0]   r_pre_re_count;
reg         [1:0]   r_post_re_count;




wire                w_controller_read_request;



assign  o_read_enable       = (state == READ);
assign  o_output_enable     = ((state == READ) |
                               (state == READ_OE_DELAY));
assign  o_data_valid        = (r_pre_re_count == 0) &&
                              (r_post_re_count > 0);


assign  o_in_path_busy      = ((state != IDLE) && (state != FINISHED));
assign  o_in_path_finished  = (state == FINISHED);


always @ (*) begin
  next_state  = state;
  case (state)
    IDLE: begin
      if (i_in_path_enable && i_read_flow_cntrl) begin
        next_state  = READ;
      end
      else begin
        next_state  = IDLE;
      end
    end
    READ: begin
      if (r_read_count >= i_packet_size - 1) begin
        next_state  = READ_OE_DELAY;
      end
      else begin
        next_state  = READ;
      end
    end
    READ_OE_DELAY: begin
      if (r_post_re_count == 0) begin
        next_state  = FINISHED;
      end
      else begin
        next_state  = READ_OE_DELAY;
      end
    end
    FINISHED: begin

      if (!i_in_path_enable) begin
        next_state  = IDLE;
      end
      else begin
        next_state  = FINISHED;
      end
    end
  endcase
end














always @ (posedge clk) begin
  if (rst) begin
    r_pre_re_count      <=  `RD_ENABLE_DELAY;
  end
  else begin
    case (state)
      IDLE: begin
        r_pre_re_count    <=  `RD_ENABLE_DELAY;
      end
      READ: begin
        if (r_pre_re_count > 2'h0) begin
          r_pre_re_count  <=  r_pre_re_count - 1'b1;
        end
      end
      default: begin
        r_pre_re_count    <=  r_pre_re_count;
      end
    endcase
  end
end



always @ (posedge clk) begin
  if (rst) begin
    r_post_re_count         <=  `RD_ENABLE_DELAY;
  end
  else begin
    case (state)
      READ: begin
        r_post_re_count     <=  `RD_ENABLE_DELAY;
      end
      READ_OE_DELAY: begin
        if (r_post_re_count > 2'h0) begin
          r_post_re_count   <=  r_post_re_count - 1'b1;
        end
        else begin
          r_post_re_count   <=  r_post_re_count;
        end
      end
      default: begin
        r_post_re_count     <=  r_post_re_count;
      end
    endcase
  end
end


always @ (posedge clk) begin
  if (rst) begin
    r_read_count                  <=  0;
  end
  else begin
    if ((state == READ) | (state == READ_OE_DELAY)) begin
      if (r_read_count < i_packet_size) begin
        r_read_count              <=  r_read_count + 1;
      end
    end
    else begin
      r_read_count                <=  0;
    end
  end
end


always @ (posedge clk) begin
  if (rst) begin
    state <=  IDLE;
  end
  else begin
    state <=  next_state;
  end
end

endmodule
module fx3_bus_in_path (
input               clk,
input               rst,



input               i_read_flow_cntrl,

input       [23:0]  i_packet_size,




output              o_output_enable,
output              o_read_enable,


output              o_data_valid,
input               i_in_path_enable,
output              o_in_path_busy,
output              o_in_path_finished
);




localparam IDLE                   = 4'h0;
localparam READ                   = 4'h1;
localparam READ_OE_DELAY          = 4'h2;
localparam FINISHED               = 4'h3;


reg         [3:0]   state;
reg         [3:0]   next_state;

reg         [23:0]  r_read_count;
reg         [1:0]   r_pre_re_count;
reg         [1:0]   r_post_re_count;




wire                w_controller_read_request;



assign  o_read_enable       = (state == READ);
assign  o_output_enable     = ((state == READ) |
                               (state == READ_OE_DELAY));
assign  o_data_valid        = (r_pre_re_count == 0) &&
                              (r_post_re_count > 0);


assign  o_in_path_busy      = ((state != IDLE) && (state != FINISHED));
assign  o_in_path_finished  = (state == FINISHED);


always @ (*) begin
  next_state  = state;
  case (state)
    IDLE: begin
      if (i_in_path_enable && i_read_flow_cntrl) begin
        next_state  = READ;
      end
      else begin
        next_state  = IDLE;
      end
    end
    READ: begin
      if (r_read_count >= i_packet_size - 1) begin
        next_state  = READ_OE_DELAY;
      end
      else begin
        next_state  = READ;
      end
    end
    READ_OE_DELAY: begin
      if (r_post_re_count == 0) begin
        next_state  = FINISHED;
      end
      else begin
        next_state  = READ_OE_DELAY;
      end
    end
    FINISHED: begin

      if (!i_in_path_enable) begin
        next_state  = IDLE;
      end
      else begin
        next_state  = FINISHED;
      end
    end
  endcase
end














always @ (posedge clk) begin
  if (rst) begin
    r_pre_re_count      <=  `RD_ENABLE_DELAY;
  end
  else begin
    case (state)
      IDLE: begin
        r_pre_re_count    <=  `RD_ENABLE_DELAY;
      end
      READ: begin
        if (r_pre_re_count > 2'h0) begin
          r_pre_re_count  <=  r_pre_re_count - 1'b1;
        end
      end
      default: begin
        r_pre_re_count    <=  r_pre_re_count;
      end
    endcase
  end
end



always @ (posedge clk) begin
  if (rst) begin
    r_post_re_count         <=  `RD_ENABLE_DELAY;
  end
  else begin
    case (state)
      READ: begin
        r_post_re_count     <=  `RD_ENABLE_DELAY;
      end
      READ_OE_DELAY: begin
        if (r_post_re_count > 2'h0) begin
          r_post_re_count   <=  r_post_re_count - 1'b1;
        end
        else begin
          r_post_re_count   <=  r_post_re_count;
        end
      end
      default: begin
        r_post_re_count     <=  r_post_re_count;
      end
    endcase
  end
end


always @ (posedge clk) begin
  if (rst) begin
    r_read_count                  <=  0;
  end
  else begin
    if ((state == READ) | (state == READ_OE_DELAY)) begin
      if (r_read_count < i_packet_size) begin
        r_read_count              <=  r_read_count + 1;
      end
    end
    else begin
      r_read_count                <=  0;
    end
  end
end


always @ (posedge clk) begin
  if (rst) begin
    state <=  IDLE;
  end
  else begin
    state <=  next_state;
  end
end

endmodule