data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pipeline_fetch2dec.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pipeline_fetch2dec.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161049548/project_1.srcs/sources_1/new,data/full_repos/permissive/161049548/defines.v\n             data/full_repos/permissive/161049548/project_1.srcs/sources_1/new,data/full_repos/permissive/161049548/defines.v.v\n             data/full_repos/permissive/161049548/project_1.srcs/sources_1/new,data/full_repos/permissive/161049548/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pipeline_fetch2dec.v:32: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] pc_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pipeline_fetch2dec.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input      [`DATA_BUS] pc_in,\n                         ^\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pipeline_fetch2dec.v:33: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] pc_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pipeline_fetch2dec.v:34: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] inst_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161049548/project_1.srcs/sources_1/new/pipeline_fetch2dec.v:35: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] inst_out\n                ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module pipeline_fetch2dec #(
    parameter DATA_WIDTH = 32
)(
    input clk,
    input rst_n,
    input flush,
    input stall,

    input      [`DATA_BUS] pc_in,
    output reg [`DATA_BUS] pc_out,
    input      [`DATA_BUS] inst_in,
    output reg [`DATA_BUS] inst_out
    );

    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            pc_out <= 0;
            inst_out <= 0;
        end
        else
        begin
            if (flush)
            begin
                pc_out <= 0;
                inst_out <= 0;
            end
            else if (!stall)
            begin
                pc_out <= pc_in;
                inst_out <= inst_in;
            end
        end
    end
endmodule
module pipeline_fetch2dec #(
    parameter DATA_WIDTH = 32
)(
    input clk,
    input rst_n,
    input flush,
    input stall,

    input      [`DATA_BUS] pc_in,
    output reg [`DATA_BUS] pc_out,
    input      [`DATA_BUS] inst_in,
    output reg [`DATA_BUS] inst_out
    );


    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            pc_out <= 0;
            inst_out <= 0;
        end
        else
        begin
            if (flush)
            begin
                pc_out <= 0;
                inst_out <= 0;
            end
            else if (!stall)
            begin
                pc_out <= pc_in;
                inst_out <= inst_in;
            end
        end
    end
endmodule