data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v
data/verilator_xmls/fde372b2-2cea-4877-abb7-f387cfbc63b5.xml
module mac_20(a, b, c, out);
parameter DATA_WIDTH = 20;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule
module mac_20(a, b, c, out);

parameter DATA_WIDTH = 20;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule