data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v
1: b'%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:2: Cannot find include file: ../../utils/test.v\n`include "../../utils/test.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165846232/components/SimpleALU,data/full_repos/permissive/165846232/../../utils/test.v\n             data/full_repos/permissive/165846232/components/SimpleALU,data/full_repos/permissive/165846232/../../utils/test.v.v\n             data/full_repos/permissive/165846232/components/SimpleALU,data/full_repos/permissive/165846232/../../utils/test.v.sv\n             ../../utils/test.v\n             ../../utils/test.v.v\n             ../../utils/test.v.sv\n             obj_dir/../../utils/test.v\n             obj_dir/../../utils/test.v.v\n             obj_dir/../../utils/test.v.sv\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:3: Cannot find include file: ./SimpleALU.v\n`include "./SimpleALU.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:47: Define or directive not defined: \'`defClock\'\n    `defClock(Clk, 2);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:47: syntax error, unexpected \'(\'\n    `defClock(Clk, 2);\n              ^~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:70: Define or directive not defined: \'`startTest\'\n    `startTest("SimpleALU")\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:70: syntax error, unexpected \'(\'\n    `startTest("SimpleALU")\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:78: Define or directive not defined: \'`describe\'\n        `describe("Test add operation");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:79: Define or directive not defined: \'`assert\'\n        `assert(ResultA, 22);;\n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:81: Define or directive not defined: \'`describe\'\n        `describe("Test gth operation");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:82: Define or directive not defined: \'`assert\'\n        `assert(ResultA, 255);;\n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:84: Define or directive not defined: \'`describe\'\n       `describe("Test or operation");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:85: Define or directive not defined: \'`assert\'\n        `assert(ResultA, 15);;\n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:87: Define or directive not defined: \'`describe\'\n       `describe("Test sub operation");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:88: Define or directive not defined: \'`assert\'\n        `assert(ResultA, 8);;\n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:90: Define or directive not defined: \'`describe\'\n       `describe("Test shl operation");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:91: Define or directive not defined: \'`assert\'\n        `assert(ResultA, 30);;\n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:93: Define or directive not defined: \'`describe\'\n       `describe("Test add operation");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:94: Define or directive not defined: \'`assert\'\n        `assert(ResultA, 105);;\n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:96: Define or directive not defined: \'`describe\'\n       `describe("Test div operation");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:97: Define or directive not defined: \'`assert\'\n        `assert(ResultA, 2);;\n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SimpleALU/TestSimpleALU.v:99: Define or directive not defined: \'`endTest\'\n    `endTest\n    ^~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module TestSimpleALU
#(
    parameter INPUT_BIT_WIDTH  = 8,
    parameter INSTR_BIT_WIDTH  = 5,
    parameter FLAGS_COUNT      = 1,
    parameter CODE_INSTR_NOP   = 5'b00000,
    parameter CODE_INSTR_ADD   = 5'b00001,
    parameter CODE_INSTR_SUB   = 5'b00010,
    parameter CODE_INSTR_MUL   = 5'b00011,
    parameter CODE_INSTR_DIV   = 5'b00100,
    parameter CODE_INSTR_SHL   = 5'b00101,
    parameter CODE_INSTR_SHR   = 5'b00110,
    parameter CODE_INSTR_ROL   = 5'b00111,
    parameter CODE_INSTR_ROR   = 5'b01000,
    parameter CODE_INSTR_AND   = 5'b01001,
    parameter CODE_INSTR_XOR   = 5'b01011,
    parameter CODE_INSTR_OR   = 5'b01101,
    parameter CODE_INSTR_NAND = 5'b01110,
    parameter CODE_INSTR_XNOR = 5'b01111,
    parameter CODE_INSTR_GTH   = 5'b10000,
    parameter CODE_INSTR_EQU   = 5'b10001
);


    `defClock(Clk, 2);
    reg [INSTR_BIT_WIDTH-1:0] Instruction;
    reg [INPUT_BIT_WIDTH-1:0] InputA;
    reg [INPUT_BIT_WIDTH-1:0] InputB;


    wire [INPUT_BIT_WIDTH-1:0] ResultA;
    wire [INPUT_BIT_WIDTH-1:0] ResultB;
    wire [FLAGS_COUNT-1:0] Flags;
    wire Ready;


    SimpleALU uut (
        .Clk(Clk),
        .Instruction(Instruction),
        .InputA(InputA),
        .InputB(InputB),
        .ResultA(ResultA),
        .ResultB(ResultB),
        .Flags(Flags),
        .Ready(Ready)
    );

    `startTest("SimpleALU")

        Clk = 0;
        Instruction = CODE_INSTR_NOP;
        InputA = 0;
        InputB = 0;
        #100;
        
        `describe("Test add operation");
            `do_op(CODE_INSTR_ADD, 15, 7, 22);
          
        `describe("Test gth operation");
            `do_op(CODE_INSTR_GTH, 15, 7, 255);
       
       `describe("Test or operation");
            `do_op(CODE_INSTR_OR, 15, 7, 15);
       
       `describe("Test sub operation");
            `do_op(CODE_INSTR_SUB, 15, 7, 8);
       
       `describe("Test shl operation");
            `do_op(CODE_INSTR_SHL, 15, 7, 30);
       
       `describe("Test add operation");
            `do_op(CODE_INSTR_MUL, 15, 7, 105);
       
       `describe("Test div operation");
            `do_op(CODE_INSTR_DIV, 15, 7, 2);

    `endTest
   
      
endmodule
module TestSimpleALU
#(
    parameter INPUT_BIT_WIDTH  = 8,
    parameter INSTR_BIT_WIDTH  = 5,
    parameter FLAGS_COUNT      = 1,
    parameter CODE_INSTR_NOP   = 5'b00000,
    parameter CODE_INSTR_ADD   = 5'b00001,
    parameter CODE_INSTR_SUB   = 5'b00010,
    parameter CODE_INSTR_MUL   = 5'b00011,
    parameter CODE_INSTR_DIV   = 5'b00100,
    parameter CODE_INSTR_SHL   = 5'b00101,
    parameter CODE_INSTR_SHR   = 5'b00110,
    parameter CODE_INSTR_ROL   = 5'b00111,
    parameter CODE_INSTR_ROR   = 5'b01000,
    parameter CODE_INSTR_AND   = 5'b01001,
    parameter CODE_INSTR_XOR   = 5'b01011,
    parameter CODE_INSTR_OR   = 5'b01101,
    parameter CODE_INSTR_NAND = 5'b01110,
    parameter CODE_INSTR_XNOR = 5'b01111,
    parameter CODE_INSTR_GTH   = 5'b10000,
    parameter CODE_INSTR_EQU   = 5'b10001
);



    `defClock(Clk, 2);
    reg [INSTR_BIT_WIDTH-1:0] Instruction;
    reg [INPUT_BIT_WIDTH-1:0] InputA;
    reg [INPUT_BIT_WIDTH-1:0] InputB;


    wire [INPUT_BIT_WIDTH-1:0] ResultA;
    wire [INPUT_BIT_WIDTH-1:0] ResultB;
    wire [FLAGS_COUNT-1:0] Flags;
    wire Ready;


    SimpleALU uut (
        .Clk(Clk),
        .Instruction(Instruction),
        .InputA(InputA),
        .InputB(InputB),
        .ResultA(ResultA),
        .ResultB(ResultB),
        .Flags(Flags),
        .Ready(Ready)
    );

    `startTest("SimpleALU")

        Clk = 0;
        Instruction = CODE_INSTR_NOP;
        InputA = 0;
        InputB = 0;
        #100;
        
        `describe("Test add operation");
            `do_op(CODE_INSTR_ADD, 15, 7, 22);
          
        `describe("Test gth operation");
            `do_op(CODE_INSTR_GTH, 15, 7, 255);
       
       `describe("Test or operation");
            `do_op(CODE_INSTR_OR, 15, 7, 15);
       
       `describe("Test sub operation");
            `do_op(CODE_INSTR_SUB, 15, 7, 8);
       
       `describe("Test shl operation");
            `do_op(CODE_INSTR_SHL, 15, 7, 30);
       
       `describe("Test add operation");
            `do_op(CODE_INSTR_MUL, 15, 7, 105);
       
       `describe("Test div operation");
            `do_op(CODE_INSTR_DIV, 15, 7, 2);

    `endTest
   
      
endmodule