data/full_repos/permissive/205673649/UART/Sources/interfaz.v
1: b'%Warning-WIDTH: data/full_repos/permissive/205673649/UART/Sources/interfaz.v:233: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'i_data\' generates 8 bits.\n                                                                                : ... In instance interfaz_rx\n            op_next = i_data;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module interfaz_rx # ( parameter NB_DATA = 8, parameter NB_OPERADOR =6)
(
    input i_clk,
    input i_rst,
    input [NB_DATA-1:0] i_data,
    input i_done_data,
    output reg [NB_DATA-1:0] o_a,
    output reg [NB_DATA-1:0] o_b,
    output reg [NB_OPERADOR-1:0] o_op,
    output o_rx_alu_done
);

localparam [3-1:0] idle = 3'b000;
localparam [3-1:0] op1 = 3'b001;
localparam [3-1:0] op2 = 3'b010;
localparam [3-1:0] operacion = 3'b011;
localparam [3-1:0] alu = 3'b100;

reg [3-1:0] state_reg;
reg [3-1:0] state_next;
reg [NB_DATA-1:0] a_next;
reg [NB_DATA-1:0] b_next;
reg [NB_OPERADOR-1:0] op_next;

reg done_data_prev;


always @(posedge i_clk)
begin
    if(!i_rst)
    begin
        state_reg <= idle;
        done_data_prev <= 0;
        o_a <= 0;
        o_b <= 0;
        o_op <= 0;
    end
    else
    begin
        state_reg <= state_next;
        done_data_prev <= i_done_data;
        o_a <= a_next;
        o_b <= b_next;
        o_op <= op_next;
    end
end



























always @(*) begin
    case(state_reg)
        
        idle:
        begin
            a_next = o_a;
            b_next = o_b;
            op_next = o_op;
        end
        
        op1:
        begin
            a_next = i_data;
            b_next = o_b;
            op_next = o_op;
        end
        
        op2:
        begin
           a_next = o_a;
           b_next = i_data;
           op_next = o_op;
        end
        
        operacion:
        begin
            a_next = o_a;
            b_next = o_b;
            op_next = i_data;
        end
        alu:
        begin
            a_next = o_a;
            b_next = o_b;
            op_next = o_op;
        end
        
        default:
        begin
            a_next = o_a;
            b_next = o_b;
            op_next = o_op;
        end
    endcase
end


always @(*)
begin
    state_next = state_reg;
    case(state_reg)
        
        idle:
        begin
            if((i_done_data==1)&&(done_data_prev == 0))
                state_next = op1;
        end
        
        op1:
        begin
            if((i_done_data==1)&&(done_data_prev == 0))
                state_next = op2;
        end
        
        op2:
        begin
            if((i_done_data==1)&&(done_data_prev == 0))
                state_next = operacion;
        end
        
        operacion:
        begin

                state_next = alu;
        end
        alu:
        begin
                state_next = idle;
        end
        
        default:
            state_next=idle;
    endcase
end

assign o_rx_alu_done = (state_reg==alu) ? 1'b1 : 1'b0;

endmodule
module interfaz_rx # ( parameter NB_DATA = 8, parameter NB_OPERADOR =6)
(
    input i_clk,
    input i_rst,
    input [NB_DATA-1:0] i_data,
    input i_done_data,
    output reg [NB_DATA-1:0] o_a,
    output reg [NB_DATA-1:0] o_b,
    output reg [NB_OPERADOR-1:0] o_op,
    output o_rx_alu_done
);


localparam [3-1:0] idle = 3'b000;
localparam [3-1:0] op1 = 3'b001;
localparam [3-1:0] op2 = 3'b010;
localparam [3-1:0] operacion = 3'b011;
localparam [3-1:0] alu = 3'b100;

reg [3-1:0] state_reg;
reg [3-1:0] state_next;
reg [NB_DATA-1:0] a_next;
reg [NB_DATA-1:0] b_next;
reg [NB_OPERADOR-1:0] op_next;

reg done_data_prev;


always @(posedge i_clk)
begin
    if(!i_rst)
    begin
        state_reg <= idle;
        done_data_prev <= 0;
        o_a <= 0;
        o_b <= 0;
        o_op <= 0;
    end
    else
    begin
        state_reg <= state_next;
        done_data_prev <= i_done_data;
        o_a <= a_next;
        o_b <= b_next;
        o_op <= op_next;
    end
end



























always @(*) begin
    case(state_reg)
        
        idle:
        begin
            a_next = o_a;
            b_next = o_b;
            op_next = o_op;
        end
        
        op1:
        begin
            a_next = i_data;
            b_next = o_b;
            op_next = o_op;
        end
        
        op2:
        begin
           a_next = o_a;
           b_next = i_data;
           op_next = o_op;
        end
        
        operacion:
        begin
            a_next = o_a;
            b_next = o_b;
            op_next = i_data;
        end
        alu:
        begin
            a_next = o_a;
            b_next = o_b;
            op_next = o_op;
        end
        
        default:
        begin
            a_next = o_a;
            b_next = o_b;
            op_next = o_op;
        end
    endcase
end


always @(*)
begin
    state_next = state_reg;
    case(state_reg)
        
        idle:
        begin
            if((i_done_data==1)&&(done_data_prev == 0))
                state_next = op1;
        end
        
        op1:
        begin
            if((i_done_data==1)&&(done_data_prev == 0))
                state_next = op2;
        end
        
        op2:
        begin
            if((i_done_data==1)&&(done_data_prev == 0))
                state_next = operacion;
        end
        
        operacion:
        begin

                state_next = alu;
        end
        alu:
        begin
                state_next = idle;
        end
        
        default:
            state_next=idle;
    endcase
end

assign o_rx_alu_done = (state_reg==alu) ? 1'b1 : 1'b0;

endmodule