data/full_repos/permissive/202237519/verilog/digitalsystem project/counter_tb.v
 line:12: before: "00"
1: b'%Error: Cannot find file containing module: project,data/full_repos/permissive/202237519\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519.sv\n             project,data/full_repos/permissive/202237519\n             project,data/full_repos/permissive/202237519.v\n             project,data/full_repos/permissive/202237519.sv\n             obj_dir/project,data/full_repos/permissive/202237519\n             obj_dir/project,data/full_repos/permissive/202237519.v\n             obj_dir/project,data/full_repos/permissive/202237519.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/202237519/verilog/digitalsystem\n%Error: Cannot find file containing module: project/counter_tb.v\n%Error: Exiting due to 3 error(s)\n'
module counter_tb;

reg clk;
reg reset;
wire c_out;

always #5 clk <= ~clk;

counter_10bit counter(reset, clk, c_out);

initial begin
    $dumpfile("counter_tb.vcd");
    $dumpvars(0,counter_tb);
    reset <= 1; clk <= 1; #10;
    reset <= 0; #1000;
    $finish;
end

endmodule
module counter_tb;


reg clk;
reg reset;
wire c_out;

always #5 clk <= ~clk;

counter_10bit counter(reset, clk, c_out);

initial begin
    $dumpfile("counter_tb.vcd");
    $dumpvars(0,counter_tb);
    reset <= 1; clk <= 1; #10;
    reset <= 0; #1000;
    $finish;
end

endmodule