data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v
 line:27: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #8\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:33: Unsupported or unknown PLI call: $urandom_range\n            x = $urandom_range(0, 2 ** WIDTH - 1);\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:34: Unsupported or unknown PLI call: $urandom_range\n            y = $urandom_range(0, 2 ** WIDTH - 1);\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:36: Unsupported or unknown PLI call: $urandom_range\n            c_in = $urandom_range(0, 1);\n                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:42: Unsupported or unknown PLI call: $monitor\n        $monitor("Time:\\t%g, x: %b, y: %b, c_in: %b, z: %b, c_out: %b",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:54: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/01_adder/simulation/testbench.v:55: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1);   \n        ^~~~~~~~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    parameter WIDTH = 8;

    reg  c_in;
    reg  [WIDTH - 1:0] x, y;
    wire [WIDTH - 1:0] z;
    wire c_out;
 

    adder #(.WIDTH(WIDTH)) adder_dut(
        .carry_in (c_in ),
        .x        (x    ),
        .y        (y    ),
        .z        (z    ),
        .carry_out(c_out)
    );
        

    initial begin
        x    = 0;
        y    = 0;
        c_in = 0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            x = $urandom_range(0, 2 ** WIDTH - 1);
            y = $urandom_range(0, 2 ** WIDTH - 1);
            
            c_in = $urandom_range(0, 1);
        end
            


    initial 
        $monitor("Time:\t%g, x: %b, y: %b, c_in: %b, z: %b, c_out: %b",
                $time,
                x,
                y,
                c_in,
                z,
                c_out
            );
            


    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);
    end
    
endmodule
module testbench;

    parameter WIDTH = 8;

    reg  c_in;
    reg  [WIDTH - 1:0] x, y;
    wire [WIDTH - 1:0] z;
    wire c_out;
 

    adder #(.WIDTH(WIDTH)) adder_dut(
        .carry_in (c_in ),
        .x        (x    ),
        .y        (y    ),
        .z        (z    ),
        .carry_out(c_out)
    );
        

    initial begin
        x    = 0;
        y    = 0;
        c_in = 0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            x = $urandom_range(0, 2 ** WIDTH - 1);
            y = $urandom_range(0, 2 ** WIDTH - 1);
            
            c_in = $urandom_range(0, 1);
        end
            


    initial 
        $monitor("Time:\t%g, x: %b, y: %b, c_in: %b, z: %b, c_out: %b",
                $time,
                x,
                y,
                c_in,
                z,
                c_out
            );
            


    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);
    end
    
endmodule