data/full_repos/permissive/483776248/Vision/EEE2Rover_ah2719/DE10_LITE_D8M_VIP_16/db/ip/Qsys/submodules/Qsys_sw.v
1: b'%Warning-WIDTH: data/full_repos/permissive/483776248/Vision/EEE2Rover_ah2719/DE10_LITE_D8M_VIP_16/db/ip/Qsys/submodules/Qsys_sw.v:52: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'read_mux_out\' generates 10 bits.\n                                                                                                                                    : ... In instance Qsys_sw\n          readdata <= {32\'b0 | read_mux_out};\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Qsys_sw (

                  address,
                  clk,
                  in_port,
                  reset_n,


                  readdata
               )
;

  output  [ 31: 0] readdata;
  input   [  1: 0] address;
  input            clk;
  input   [  9: 0] in_port;
  input            reset_n;


wire             clk_en;
wire    [  9: 0] data_in;
wire    [  9: 0] read_mux_out;
reg     [ 31: 0] readdata;
  assign clk_en = 1;

  assign read_mux_out = {10 {(address == 0)}} & data_in;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          readdata <= 0;
      else if (clk_en)
          readdata <= {32'b0 | read_mux_out};
    end


  assign data_in = in_port;

endmodule
module Qsys_sw (

                  address,
                  clk,
                  in_port,
                  reset_n,


                  readdata
               )
;


  output  [ 31: 0] readdata;
  input   [  1: 0] address;
  input            clk;
  input   [  9: 0] in_port;
  input            reset_n;


wire             clk_en;
wire    [  9: 0] data_in;
wire    [  9: 0] read_mux_out;
reg     [ 31: 0] readdata;
  assign clk_en = 1;

  assign read_mux_out = {10 {(address == 0)}} & data_in;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          readdata <= 0;
      else if (clk_en)
          readdata <= {32'b0 | read_mux_out};
    end


  assign data_in = in_port;

endmodule