data/full_repos/permissive/104504209/PGM8755/src/programmer_top.v
1: b"%Error: data/full_repos/permissive/104504209/PGM8755/src/programmer_top.v:49: Cannot find file containing module: 'programmer'\n programmer pgm(.clk(clk), .rst(rst), .data_latch(vdd_25), .data_in(buff_out), .rdy(new_tx_data), \n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104504209/PGM8755/src,data/full_repos/permissive/104504209/programmer\n             data/full_repos/permissive/104504209/PGM8755/src,data/full_repos/permissive/104504209/programmer.v\n             data/full_repos/permissive/104504209/PGM8755/src,data/full_repos/permissive/104504209/programmer.sv\n             programmer\n             programmer.v\n             programmer.sv\n             obj_dir/programmer\n             obj_dir/programmer.v\n             obj_dir/programmer.sv\n%Error: data/full_repos/permissive/104504209/PGM8755/src/programmer_top.v:53: Cannot find file containing module: 'buffer'\n buffer buff(.rst(rst), .clk(clk), .dir(en), .data_in(rx_data), .address(address), .data_out(buff_out));\n ^~~~~~\n%Error: data/full_repos/permissive/104504209/PGM8755/src/programmer_top.v:55: Cannot find file containing module: 'uart'\n uart #(.CLK_RATE(50000000), .SERIAL_BAUD_RATE(115200)) host(.rst(rst), .rx(rx), .new_tx_data(new_tx_data), \n ^~~~\n%Error: Exiting due to 3 error(s)\n"
module programmer_top(input clk, rst_n, rx, mode, en, output tx, pce, rd, vdd_25, vdd_5, 
					  ale, output[1:0]led, inout[10:0] address);

	wire rst = ~rst_n;

	wire[7:0] rx_data, buff_out;

	wire new_rx_data, new_tx_data, busy, block;
	
	
	programmer pgm(.clk(clk), .rst(rst), .data_latch(vdd_25), .data_in(buff_out), .rdy(new_tx_data), 
				   .tx_busy(busy), .addr_dat(address), .ce(pce), .rd(rd), .tx_block(block), .mode(mode), 
				   .en(en), .ale(ale));
				
	buffer buff(.rst(rst), .clk(clk), .dir(en), .data_in(rx_data), .address(address), .data_out(buff_out));
												 
	uart #(.CLK_RATE(50000000), .SERIAL_BAUD_RATE(115200)) host(.rst(rst), .rx(rx), .new_tx_data(new_tx_data), 
		   .clk(clk), .tx_data(address[7:0]), .tx(tx), .new_rx_data(new_rx_data), .rx_data(rx_data), 
		   .block(block), .busy(busy));
		   
	assign led[0] = new_rx_data;
	assign led[1] = new_tx_data;
	assign vdd_5 = ~vdd_25;

endmodule
module programmer_top(input clk, rst_n, rx, mode, en, output tx, pce, rd, vdd_25, vdd_5, 
					  ale, output[1:0]led, inout[10:0] address);


	wire rst = ~rst_n;

	wire[7:0] rx_data, buff_out;

	wire new_rx_data, new_tx_data, busy, block;
	
	
	programmer pgm(.clk(clk), .rst(rst), .data_latch(vdd_25), .data_in(buff_out), .rdy(new_tx_data), 
				   .tx_busy(busy), .addr_dat(address), .ce(pce), .rd(rd), .tx_block(block), .mode(mode), 
				   .en(en), .ale(ale));
				
	buffer buff(.rst(rst), .clk(clk), .dir(en), .data_in(rx_data), .address(address), .data_out(buff_out));
												 
	uart #(.CLK_RATE(50000000), .SERIAL_BAUD_RATE(115200)) host(.rst(rst), .rx(rx), .new_tx_data(new_tx_data), 
		   .clk(clk), .tx_data(address[7:0]), .tx(tx), .new_rx_data(new_rx_data), .rx_data(rx_data), 
		   .block(block), .busy(busy));
		   
	assign led[0] = new_rx_data;
	assign led[1] = new_tx_data;
	assign vdd_5 = ~vdd_25;

endmodule