data/full_repos/permissive/151863926/src/pulse_cross_domain.v
 line:6: before: "="
data/verilator_xmls/fa855c7d-6346-4293-bfa4-a3d86ea7b417.xml
module pulse_cross_domain(
    input  in_clk,
    input  in_pulse,
    
    input  out_clk,
    output reg out_pulse = 0
);

    reg ff = 0;
    always @(posedge in_clk)
        if (in_pulse)
            ff <= ~ff;
    
    reg r1 = 0;
    reg r2 = 0;
    reg r3 = 0;
    always @(posedge out_clk) begin
        r1 <= ff;
        r2 <= r1;
        r3 <= r2;
    end
    
    always @(posedge out_clk)
        out_pulse <= r2 ^ r3;
    
endmodule
module pulse_cross_domain(
    input  in_clk,
    input  in_pulse,
    
    input  out_clk,
    output reg out_pulse = 0
);


    reg ff = 0;
    always @(posedge in_clk)
        if (in_pulse)
            ff <= ~ff;
    
    reg r1 = 0;
    reg r2 = 0;
    reg r3 = 0;
    always @(posedge out_clk) begin
        r1 <= ff;
        r2 <= r1;
        r3 <= r2;
    end
    
    always @(posedge out_clk)
        out_pulse <= r2 ^ r3;
    
endmodule