data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v
 line:26: before: "integer"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:230: Signal definition not found, creating implicitly: \'gn_match\'\n                                                                                                   : ... Suggested alternative: \'gn_match_1\'\n assign gn_match = gn_match_1;\n        ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:68: Cannot find file containing module: \'IBUFG\'\n IBUFG bufg_fxclk (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/11584509/experimental/Ztex-1-15y,data/full_repos/permissive/11584509/IBUFG\n             data/full_repos/permissive/11584509/experimental/Ztex-1-15y,data/full_repos/permissive/11584509/IBUFG.v\n             data/full_repos/permissive/11584509/experimental/Ztex-1-15y,data/full_repos/permissive/11584509/IBUFG.sv\n             IBUFG\n             IBUFG.v\n             IBUFG.sv\n             obj_dir/IBUFG\n             obj_dir/IBUFG.v\n             obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:79: Cannot find file containing module: \'BUFGCE\'\n BUFGCE bufg_clk (\n ^~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:86: Cannot find file containing module: \'DCM_CLKGEN\'\n  DCM_CLKGEN #(\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:191: Cannot find file containing module: \'pbkdfengine\'\n pbkdfengine #(.SBITS(SBITS)) P1\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:198: Cannot find file containing module: \'salsaengine\'\n salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/Ztex-1-15y/ztex_ufm1_15y1.v:255: Operator ASSIGNDLY expects 608 bits on the Assign RHS, but Assign RHS\'s VARREF \'inbuf_tmp\' generates 640 bits.\n                                                                                                : ... In instance ztex_ufm1_15y1\n  inbuf <= inbuf_tmp;   \n        ^~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
function integer clog2;
		input integer value;
		begin
		value = value-1;
		for (clog2=0; value>0; clog2=clog2+1)
		value = value>>1;
		end
	endfunction
function integer clog2;

		input integer value;
		begin
		value = value-1;
		for (clog2=0; value>0; clog2=clog2+1)
		value = value>>1;
		end
	endfunction