data/full_repos/permissive/170402453/Test_SignalRouter.v
 line:138: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/170402453/Test_SignalRouter.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/170402453/Test_SignalRouter.v:155: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/Test_SignalRouter.v:159: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/Test_SignalRouter.v:163: Unsupported: Ignoring delay on this delayed statement.\n    #1000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/Test_SignalRouter.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/Test_SignalRouter.v:177: Unsupported: Ignoring delay on this delayed statement.\n   #1000000;\n   ^\n%Error: data/full_repos/permissive/170402453/Test_SignalRouter.v:71: Cannot find file containing module: \'SignalRouter8_1\'\n SignalRouter8_1 uut (\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/SignalRouter8_1\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/SignalRouter8_1.v\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/SignalRouter8_1.sv\n             SignalRouter8_1\n             SignalRouter8_1.v\n             SignalRouter8_1.sv\n             obj_dir/SignalRouter8_1\n             obj_dir/SignalRouter8_1.v\n             obj_dir/SignalRouter8_1.sv\n%Warning-WIDTH: data/full_repos/permissive/170402453/Test_SignalRouter.v:139: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                            : ... In instance Test_SignalRouter\n   RLoc[3*i +:3] = i;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/Test_SignalRouter.v:162: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                            : ... In instance Test_SignalRouter\n    RSel[2*i +:2] = j;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/Test_SignalRouter.v:176: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                            : ... In instance Test_SignalRouter\n   RSel[2*6 +:2] = j;\n                 ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_SignalRouter;


	reg CLK;
	reg [7:0] IN1;
	reg [7:0] IN2;
	reg [7:0] IN3;
	reg [7:0] IN4;
	reg IN5;
	reg IN6;
	reg IN7;
	reg IN8;
	reg [7:0] C1;
	reg [7:0] C2;
	reg [7:0] C3;
	reg [7:0] C4;
	reg C5;
	reg C6;
	reg C7;
	reg C8;
	reg [7:0] ClkDiv5;
	reg [7:0] ClkDiv6;
	reg [7:0] ClkDiv7;
	reg [7:0] ClkDiv8;
	reg [7:0] PWMRate5;
	reg [7:0] PWMRate6;
	reg [7:0] PWMRate7;
	reg [7:0] PWMRate8;


	wire [7:0] OUT1;
	wire [7:0] OUT2;
	wire [7:0] OUT3;
	wire [7:0] OUT4;
	wire OUT5;
	wire OUT6;
	wire OUT7;
	wire OUT8;


	 reg [23:0] RLoc;
	 reg [15:0] RSel;
	
	integer i,j;


	SignalRouter8_1 uut (
		.CLK(CLK), 
		.IN1(IN1), 
		.IN2(IN2), 
		.IN3(IN3), 
		.IN4(IN4), 
		.IN5(IN5), 
		.IN6(IN6), 
		.IN7(IN7), 
		.IN8(IN8), 
		.C1(C1), 
		.C2(C2), 
		.C3(C3), 
		.C4(C4), 
		.C5(C5), 
		.C6(C6), 
		.C7(C7), 
		.C8(C8), 
		.ClkDiv5(ClkDiv5), 
		.ClkDiv6(ClkDiv6), 
		.ClkDiv7(ClkDiv7), 
		.ClkDiv8(ClkDiv8), 
		.PWMRate5(PWMRate5), 
		.PWMRate6(PWMRate6), 
		.PWMRate7(PWMRate7), 
		.PWMRate8(PWMRate8), 
		.OUT1(OUT1), 
		.OUT2(OUT2), 
		.OUT3(OUT3), 
		.OUT4(OUT4), 
		.OUT5(OUT5), 
		.OUT6(OUT6), 
		.OUT7(OUT7), 
		.OUT8(OUT8), 
		.RLoc(RLoc), 
		.RSel(RSel)
	);

	initial begin

		CLK = 0;
		IN1 = 10;
		IN2 = 20;
		IN3 = 30;
		IN4 = 40;
		IN5 = 1;
		IN6 = 0;
		IN7 = 1;
		IN8 = 0;
		C1 = 1;
		C2 = 2;
		C3 = 3;
		C4 = 4;
		C5 = 0;
		C6 = 1;
		C7 = 0;
		C8 = 1;
		ClkDiv5 = 2;
		ClkDiv6 = 2;
		ClkDiv7 = 2;
		ClkDiv8 = 2;
		PWMRate5 = 50;
		PWMRate6 = 100;
		PWMRate7 = 200;
		PWMRate8 = 255;
		
		i = 0;
		repeat(8) begin
			RLoc[3*i +:3] = i;
			i=i+1;
		end
		
		i = 0;
		repeat(8) begin
			RSel[2*i +:2] = 2'b11;
			i=i+1;
		end


		#100;
        

		for(i=0;i<4;i=i+1) begin
			RSel[2*i +:2] = 0;
			#10;
		end
		

		#100;
		for(i=4;i<8;i=i+1) begin
			for(j=0;j<4;j=j+1) begin
				RSel[2*i +:2] = j;
				#1000000;
			end
		end
		

		#100;
		RLoc[3*4 +:3] = 6;
		RLoc[3*5 +:3] = 6;

		RLoc[3*7 +:3] = 6;
		

		for(j=0;j<4;j=j+1) begin
			RSel[2*6 +:2] = j;
			#1000000;
		end
	end
      
endmodule
module Test_SignalRouter;



	reg CLK;
	reg [7:0] IN1;
	reg [7:0] IN2;
	reg [7:0] IN3;
	reg [7:0] IN4;
	reg IN5;
	reg IN6;
	reg IN7;
	reg IN8;
	reg [7:0] C1;
	reg [7:0] C2;
	reg [7:0] C3;
	reg [7:0] C4;
	reg C5;
	reg C6;
	reg C7;
	reg C8;
	reg [7:0] ClkDiv5;
	reg [7:0] ClkDiv6;
	reg [7:0] ClkDiv7;
	reg [7:0] ClkDiv8;
	reg [7:0] PWMRate5;
	reg [7:0] PWMRate6;
	reg [7:0] PWMRate7;
	reg [7:0] PWMRate8;


	wire [7:0] OUT1;
	wire [7:0] OUT2;
	wire [7:0] OUT3;
	wire [7:0] OUT4;
	wire OUT5;
	wire OUT6;
	wire OUT7;
	wire OUT8;


	 reg [23:0] RLoc;
	 reg [15:0] RSel;
	
	integer i,j;


	SignalRouter8_1 uut (
		.CLK(CLK), 
		.IN1(IN1), 
		.IN2(IN2), 
		.IN3(IN3), 
		.IN4(IN4), 
		.IN5(IN5), 
		.IN6(IN6), 
		.IN7(IN7), 
		.IN8(IN8), 
		.C1(C1), 
		.C2(C2), 
		.C3(C3), 
		.C4(C4), 
		.C5(C5), 
		.C6(C6), 
		.C7(C7), 
		.C8(C8), 
		.ClkDiv5(ClkDiv5), 
		.ClkDiv6(ClkDiv6), 
		.ClkDiv7(ClkDiv7), 
		.ClkDiv8(ClkDiv8), 
		.PWMRate5(PWMRate5), 
		.PWMRate6(PWMRate6), 
		.PWMRate7(PWMRate7), 
		.PWMRate8(PWMRate8), 
		.OUT1(OUT1), 
		.OUT2(OUT2), 
		.OUT3(OUT3), 
		.OUT4(OUT4), 
		.OUT5(OUT5), 
		.OUT6(OUT6), 
		.OUT7(OUT7), 
		.OUT8(OUT8), 
		.RLoc(RLoc), 
		.RSel(RSel)
	);

	initial begin

		CLK = 0;
		IN1 = 10;
		IN2 = 20;
		IN3 = 30;
		IN4 = 40;
		IN5 = 1;
		IN6 = 0;
		IN7 = 1;
		IN8 = 0;
		C1 = 1;
		C2 = 2;
		C3 = 3;
		C4 = 4;
		C5 = 0;
		C6 = 1;
		C7 = 0;
		C8 = 1;
		ClkDiv5 = 2;
		ClkDiv6 = 2;
		ClkDiv7 = 2;
		ClkDiv8 = 2;
		PWMRate5 = 50;
		PWMRate6 = 100;
		PWMRate7 = 200;
		PWMRate8 = 255;
		
		i = 0;
		repeat(8) begin
			RLoc[3*i +:3] = i;
			i=i+1;
		end
		
		i = 0;
		repeat(8) begin
			RSel[2*i +:2] = 2'b11;
			i=i+1;
		end


		#100;
        

		for(i=0;i<4;i=i+1) begin
			RSel[2*i +:2] = 0;
			#10;
		end
		

		#100;
		for(i=4;i<8;i=i+1) begin
			for(j=0;j<4;j=j+1) begin
				RSel[2*i +:2] = j;
				#1000000;
			end
		end
		

		#100;
		RLoc[3*4 +:3] = 6;
		RLoc[3*5 +:3] = 6;

		RLoc[3*7 +:3] = 6;
		

		for(j=0;j<4;j=j+1) begin
			RSel[2*6 +:2] = j;
			#1000000;
		end
	end
      
endmodule