data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction.v
1: b'%Warning-WIDTH: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction.v:125: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 32 or 8 bits.\n                                                                                                       : ... In instance FromCLBToChannelBusJunction\n   assign ch_up_n[i] = ((configReg[(DIMENSION*CH_UP_WIDTH)-1:0] >> ((c_dimension * CH_UP_WIDTH) + i)) & \'b1)? clb_out : ch_up_s[i];\n                                                                                                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction.v:128: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 32 or 8 bits.\n                                                                                                       : ... In instance FromCLBToChannelBusJunction\n   assign ch_dn_s[i] = ((configReg[(DIMENSION*(CH_UP_WIDTH+CH_DN_WIDTH))-1:(DIMENSION*CH_UP_WIDTH)] >> ((c_dimension * CH_DN_WIDTH) + i)) & \'b1)? clb_out : ch_dn_n[i];\n                                                                                                                                                ^\n%Error: Exiting due to 2 warning(s)\n'
module FromCLBToChannelBusJunction#( 

		parameter DIMENSION = 4,

		parameter CH_UP_WIDTH = 2,

		parameter CH_DN_WIDTH = 2,

		parameter DIMENSION_WIDTH = 2
	) (

		mode,
		c_clk,
		c_bus,
		c_dimension,


		ch_up_n,
		ch_up_s,
		ch_dn_n,
		ch_dn_s,
		clb_out
	);


	parameter CONFIG_WORD_WIDTH = DIMENSION*(CH_UP_WIDTH+CH_DN_WIDTH);


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	output [CH_UP_WIDTH-1:0] ch_up_n;
	input [CH_UP_WIDTH-1:0] ch_up_s;
	input [CH_DN_WIDTH-1:0] ch_dn_n;
	output [CH_DN_WIDTH-1:0] ch_dn_s;
	input clb_out;


	reg [CONFIG_WORD_WIDTH-1:0] configReg;


	always @(posedge c_clk) begin
		if(mode) begin
			`CONFIGREG_CLB_UP_JUNCTION = `C_BUS_CLB_UP_JUNCTION;
			`CONFIGREG_CLB_DN_JUNCTION = `C_BUS_CLB_DN_JUNCTION;
		end
	end


	genvar i;
	generate

		for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : ch_up_nGen
			assign ch_up_n[i] = ((`CONFIGREG_CLB_UP_JUNCTION >> ((c_dimension * CH_UP_WIDTH) + i)) & 'b1)? clb_out : ch_up_s[i];
		end
		for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : ch_dn_sGen
			assign ch_dn_s[i] = ((`CONFIGREG_CLB_DN_JUNCTION >> ((c_dimension * CH_DN_WIDTH) + i)) & 'b1)? clb_out : ch_dn_n[i];
		end
	endgenerate

endmodule
module FromCLBToChannelBusJunction#( 

		parameter DIMENSION = 4,

		parameter CH_UP_WIDTH = 2,

		parameter CH_DN_WIDTH = 2,

		parameter DIMENSION_WIDTH = 2
	) (

		mode,
		c_clk,
		c_bus,
		c_dimension,


		ch_up_n,
		ch_up_s,
		ch_dn_n,
		ch_dn_s,
		clb_out
	);



	parameter CONFIG_WORD_WIDTH = DIMENSION*(CH_UP_WIDTH+CH_DN_WIDTH);


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	output [CH_UP_WIDTH-1:0] ch_up_n;
	input [CH_UP_WIDTH-1:0] ch_up_s;
	input [CH_DN_WIDTH-1:0] ch_dn_n;
	output [CH_DN_WIDTH-1:0] ch_dn_s;
	input clb_out;


	reg [CONFIG_WORD_WIDTH-1:0] configReg;


	always @(posedge c_clk) begin
		if(mode) begin
			`CONFIGREG_CLB_UP_JUNCTION = `C_BUS_CLB_UP_JUNCTION;
			`CONFIGREG_CLB_DN_JUNCTION = `C_BUS_CLB_DN_JUNCTION;
		end
	end


	genvar i;
	generate

		for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : ch_up_nGen
			assign ch_up_n[i] = ((`CONFIGREG_CLB_UP_JUNCTION >> ((c_dimension * CH_UP_WIDTH) + i)) & 'b1)? clb_out : ch_up_s[i];
		end
		for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : ch_dn_sGen
			assign ch_dn_s[i] = ((`CONFIGREG_CLB_DN_JUNCTION >> ((c_dimension * CH_DN_WIDTH) + i)) & 'b1)? clb_out : ch_dn_n[i];
		end
	endgenerate

endmodule