data/full_repos/permissive/211316121/lab3_2/sim_1/new/sim_fourAdder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_2/sim_1/new/sim_fourAdder.v:33: Unsupported: Ignoring delay on this delayed statement.\n            #10  a=\'b0001;b=\'b0101;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_2/sim_1/new/sim_fourAdder.v:34: Unsupported: Ignoring delay on this delayed statement.\n            #10  a=\'b0010;b=\'b0111;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_2/sim_1/new/sim_fourAdder.v:35: Unsupported: Ignoring delay on this delayed statement.\n            #10  a=\'b1100;b=\'b0101;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_2/sim_1/new/sim_fourAdder.v:36: Unsupported: Ignoring delay on this delayed statement.\n            #10  a=\'b0110;b=\'b0101;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_2/sim_1/new/sim_fourAdder.v:37: Unsupported: Ignoring delay on this delayed statement.\n            #10  a=\'b0001;b=\'b1101;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_2/sim_1/new/sim_fourAdder.v:38: Unsupported: Ignoring delay on this delayed statement.\n            #10  a=\'b0010;b=\'b1101;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_2/sim_1/new/sim_fourAdder.v:39: Unsupported: Ignoring delay on this delayed statement.\n            #10  a=\'b1001;b=\'b0101;\n            ^\n%Error: data/full_repos/permissive/211316121/lab3_2/sim_1/new/sim_fourAdder.v:41: Cannot find file containing module: \'fourAdder\'\n    fourAdder sim(a,b,s,c4);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab3_2/sim_1/new,data/full_repos/permissive/211316121/fourAdder\n             data/full_repos/permissive/211316121/lab3_2/sim_1/new,data/full_repos/permissive/211316121/fourAdder.v\n             data/full_repos/permissive/211316121/lab3_2/sim_1/new,data/full_repos/permissive/211316121/fourAdder.sv\n             fourAdder\n             fourAdder.v\n             fourAdder.sv\n             obj_dir/fourAdder\n             obj_dir/fourAdder.v\n             obj_dir/fourAdder.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_fourAdder(

    );
    reg [3:0] a;
    reg [3:0] b;
    wire [3:0] s;
    wire c4;
    initial
        begin
                 a='b0000;b='b0000;
            #10  a='b0001;b='b0101;
            #10  a='b0010;b='b0111;
            #10  a='b1100;b='b0101;
            #10  a='b0110;b='b0101;
            #10  a='b0001;b='b1101;
            #10  a='b0010;b='b1101;
            #10  a='b1001;b='b0101;
        end
    fourAdder sim(a,b,s,c4);
endmodule
module sim_fourAdder(

    );

    reg [3:0] a;
    reg [3:0] b;
    wire [3:0] s;
    wire c4;
    initial
        begin
                 a='b0000;b='b0000;
            #10  a='b0001;b='b0101;
            #10  a='b0010;b='b0111;
            #10  a='b1100;b='b0101;
            #10  a='b0110;b='b0101;
            #10  a='b0001;b='b1101;
            #10  a='b0010;b='b1101;
            #10  a='b1001;b='b0101;
        end
    fourAdder sim(a,b,s,c4);
endmodule