data/full_repos/permissive/165160692/04.FPGA/5932_lights/stimulus/textbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_lights/stimulus/textbench.v:16: Unsupported: Ignoring delay on this delayed statement.\nalways#(clock_period/2)clk=~clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_lights/stimulus/textbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10 rst=0;\n ^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_lights/stimulus/textbench.v:31: Cannot find file containing module: \'XYF\'\nXYF u1(.rst(rst),.clk(clk),.sel_0(sel_0),.sel_1(sel_1),.sel_2(sel_2),.led_0(led_0),.led_1(led_1),.led_2(led_2));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_lights/stimulus,data/full_repos/permissive/165160692/XYF\n             data/full_repos/permissive/165160692/04.FPGA/5932_lights/stimulus,data/full_repos/permissive/165160692/XYF.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_lights/stimulus,data/full_repos/permissive/165160692/XYF.sv\n             XYF\n             XYF.v\n             XYF.sv\n             obj_dir/XYF\n             obj_dir/XYF.v\n             obj_dir/XYF.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

reg rst,clk;

reg[1:0]sel_0;
reg[1:0]sel_1;
reg[1:0]sel_2;

wire[7:0]led_0;
wire[7:0]led_1;
wire[7:0]led_2;

parameter clock_period=10;
always#(clock_period/2)clk=~clk;

initial
 begin
 rst=1;clk=0;
 #10 rst=0;
 end

initial
 begin
  sel_0=0;
  sel_1=1;
  sel_2=2;
 end

XYF u1(.rst(rst),.clk(clk),.sel_0(sel_0),.sel_1(sel_1),.sel_2(sel_2),.led_0(led_0),.led_1(led_1),.led_2(led_2));
endmodule
module testbench();


reg rst,clk;

reg[1:0]sel_0;
reg[1:0]sel_1;
reg[1:0]sel_2;

wire[7:0]led_0;
wire[7:0]led_1;
wire[7:0]led_2;

parameter clock_period=10;
always#(clock_period/2)clk=~clk;

initial
 begin
 rst=1;clk=0;
 #10 rst=0;
 end

initial
 begin
  sel_0=0;
  sel_1=1;
  sel_2=2;
 end

XYF u1(.rst(rst),.clk(clk),.sel_0(sel_0),.sel_1(sel_1),.sel_2(sel_2),.led_0(led_0),.led_1(led_1),.led_2(led_2));
endmodule