data/full_repos/permissive/173670949/dds-synth/tb.v
 line:28: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/173670949/dds-synth/tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n    always #42 clk <= !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/173670949/dds-synth/tb.v:28: syntax error, unexpected byte, expecting IDENTIFIER\n    task uart_signal (input [7:0] byte);\n                                  ^~~~\n%Error: data/full_repos/permissive/173670949/dds-synth/tb.v:30: syntax error, unexpected begin\n        begin\n        ^~~~~\n%Error: data/full_repos/permissive/173670949/dds-synth/tb.v:35: syntax error, unexpected \'=\', expecting IDENTIFIER\n                uart_rx = byte[i];\n                        ^\n%Error: data/full_repos/permissive/173670949/dds-synth/tb.v:39: syntax error, unexpected \'=\', expecting IDENTIFIER\n            uart_rx = 1;\n                    ^\n%Error: data/full_repos/permissive/173670949/dds-synth/tb.v:45: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/173670949/dds-synth/tb.v:46: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, top_inst);\n        ^~~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

    parameter BITPER = 104_000;

    reg clk = 0;
    always #42 clk <= !clk;

    reg  uart_rx = 1;
    wire uart_tx;
    wire j3_10;
    wire j3_9;
    wire j3_8;
    wire gled5;
    wire rled1;
    wire rled2;
    wire rled3;
    wire rled4;

    UART_Mirror top_inst (
        clk, uart_rx, uart_tx,
        j3_10, j3_9, j3_8,
        gled5, rled1, rled2, rled3, rled4
    );

    task uart_signal (input [7:0] byte);
        integer i;
        begin

            uart_rx = 0;
            #BITPER;
            for (i = 0; i < 8; i = i + 1) begin
                uart_rx = byte[i];
                #BITPER;
            end

            uart_rx = 1;
            #BITPER;
        end
    endtask

    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, top_inst);
        uart_rx = 1;
        #10_000;

        uart_signal(8'h01);
        uart_signal(8'h02);
        uart_signal(8'h03);
        uart_signal(8'h04);
        uart_signal(8'h05);
        uart_signal(8'h06);
        uart_signal("h");









































        #5_000_000;
        $finish;
    end

endmodule
module tb();


    parameter BITPER = 104_000;

    reg clk = 0;
    always #42 clk <= !clk;

    reg  uart_rx = 1;
    wire uart_tx;
    wire j3_10;
    wire j3_9;
    wire j3_8;
    wire gled5;
    wire rled1;
    wire rled2;
    wire rled3;
    wire rled4;

    UART_Mirror top_inst (
        clk, uart_rx, uart_tx,
        j3_10, j3_9, j3_8,
        gled5, rled1, rled2, rled3, rled4
    );

    task uart_signal (input [7:0] byte);
        integer i;
        begin

            uart_rx = 0;
            #BITPER;
            for (i = 0; i < 8; i = i + 1) begin
                uart_rx = byte[i];
                #BITPER;
            end

            uart_rx = 1;
            #BITPER;
        end
    endtask

    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, top_inst);
        uart_rx = 1;
        #10_000;

        uart_signal(8'h01);
        uart_signal(8'h02);
        uart_signal(8'h03);
        uart_signal(8'h04);
        uart_signal(8'h05);
        uart_signal(8'h06);
        uart_signal("h");









































        #5_000_000;
        $finish;
    end

endmodule