data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v
 line:76: before: "assign"
1: b'%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b0000;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b0001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b0010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b0011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b0100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b0101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b0110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b0111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b1000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b1001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b1010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b1011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b1100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b1101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b1110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #100 assign sec=4\'b1111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:95: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk=!clk;\n           ^\n%Error: data/full_repos/permissive/201196900/Tutorial/07_mux16x1_test_bench.v:36: Cannot find file containing module: \'top\'\ntop mux16giristest(.clk(clk), \n^~~\n        ... Looked in:\n             data/full_repos/permissive/201196900/Tutorial,data/full_repos/permissive/201196900/top\n             data/full_repos/permissive/201196900/Tutorial,data/full_repos/permissive/201196900/top.v\n             data/full_repos/permissive/201196900/Tutorial,data/full_repos/permissive/201196900/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb;
  
reg [7:0] giris0, giris1, giris2, giris3,
          giris4, giris5, giris6, giris7,
          giris8, giris9, giris10, giris11,
          giris12, giris13, giris14, giris15;
reg clk;

reg [3:0] sec;

wire [7:0] cikis;
    

top mux16giristest(.clk(clk), 
                    .in0(giris0), 
                    .in1(giris1), 
                    .in2(giris2), 
                    .in3(giris3), 
                    .in4(giris4),
                    .in5(giris5),
                    .in6(giris6),
                    .in7(giris7),
                    .in8(giris8),
                    .in9(giris9),
                    .in10(giris10),
                    .in11(giris11),
                    .in12(giris12),
                    .in13(giris13),
                    .in14(giris14),
                    .in15(giris15),
                    .select(sec), 
                    .out(cikis));
    
    initial 
    begin
        clk =0;
        giris0=5;
        giris1=10;
        giris2=20;
        giris3=30;
        giris4=40;
        giris5=50;
        giris6=60;
        giris7=70;
        giris8=80;
        giris9=90;
        giris10=100;
        giris11=110;
        giris12=120;
        giris13=130;
        giris14=140;
        giris15=150;
        sec=0;
        #100 assign sec=4'b0000;
        #100 assign sec=4'b0001;
        #100 assign sec=4'b0010;
        #100 assign sec=4'b0011;
        #100 assign sec=4'b0100;
        #100 assign sec=4'b0101;
        #100 assign sec=4'b0110;
        #100 assign sec=4'b0111;
        #100 assign sec=4'b1000;
        #100 assign sec=4'b1001;
        #100 assign sec=4'b1010;
        #100 assign sec=4'b1011;
        #100 assign sec=4'b1100;
        #100 assign sec=4'b1101;
        #100 assign sec=4'b1110;
        #100 assign sec=4'b1111;
        $finish;
    end

    always #10 clk=!clk;
endmodule
module top_tb;

  
reg [7:0] giris0, giris1, giris2, giris3,
          giris4, giris5, giris6, giris7,
          giris8, giris9, giris10, giris11,
          giris12, giris13, giris14, giris15;
reg clk;

reg [3:0] sec;

wire [7:0] cikis;
    

top mux16giristest(.clk(clk), 
                    .in0(giris0), 
                    .in1(giris1), 
                    .in2(giris2), 
                    .in3(giris3), 
                    .in4(giris4),
                    .in5(giris5),
                    .in6(giris6),
                    .in7(giris7),
                    .in8(giris8),
                    .in9(giris9),
                    .in10(giris10),
                    .in11(giris11),
                    .in12(giris12),
                    .in13(giris13),
                    .in14(giris14),
                    .in15(giris15),
                    .select(sec), 
                    .out(cikis));
    
    initial 
    begin
        clk =0;
        giris0=5;
        giris1=10;
        giris2=20;
        giris3=30;
        giris4=40;
        giris5=50;
        giris6=60;
        giris7=70;
        giris8=80;
        giris9=90;
        giris10=100;
        giris11=110;
        giris12=120;
        giris13=130;
        giris14=140;
        giris15=150;
        sec=0;
        #100 assign sec=4'b0000;
        #100 assign sec=4'b0001;
        #100 assign sec=4'b0010;
        #100 assign sec=4'b0011;
        #100 assign sec=4'b0100;
        #100 assign sec=4'b0101;
        #100 assign sec=4'b0110;
        #100 assign sec=4'b0111;
        #100 assign sec=4'b1000;
        #100 assign sec=4'b1001;
        #100 assign sec=4'b1010;
        #100 assign sec=4'b1011;
        #100 assign sec=4'b1100;
        #100 assign sec=4'b1101;
        #100 assign sec=4'b1110;
        #100 assign sec=4'b1111;
        $finish;
    end

    always #10 clk=!clk;
endmodule