data/full_repos/permissive/143278/ivltests/dffsynth6.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #1 rst <= 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #1 rst <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:48: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q0 !== d0 || q1 !== d1) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/dffsynth6.v:37: Operator NEQCASE expects 2 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance main\n      #1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin\n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/dffsynth6.v:43: Operator NEQCASE expects 2 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance main\n      #1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin\n                               ^~~\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire       q0;
   wire [1:0] q1;
   reg	      d0, clk, rst;
   reg [1:0]  d1;

   DFF dut (.Q0(q0), .Q1(q1), .D0(d0), .D1(d1), .CLK(clk), .RST(rst));

   initial begin
      clk <= 1;
      d0 <= 0;
      d1 <= 2;

      #1 rst <= 1;
      #1 if (q0 !== 1'b0 || q1 !== 1'b0) begin
	 $display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1);
	 $finish;
      end

      #1 rst <= 0;
      #1 if (q0 !== 1'b0 || q1 !== 1'b0) begin
	 $display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1);
	 $finish;
      end

      #1 clk <= 0;
      #1 clk <= 1;
      #1 if (q0 !== d0 || q1 !== d1) begin
	 $display("FAILED -- Q0=%b Q1=%b, D0=%b D1=%b", q0, q1, d0, d1);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   wire       q0;
   wire [1:0] q1;
   reg	      d0, clk, rst;
   reg [1:0]  d1;

   DFF dut (.Q0(q0), .Q1(q1), .D0(d0), .D1(d1), .CLK(clk), .RST(rst));

   initial begin
      clk <= 1;
      d0 <= 0;
      d1 <= 2;

      #1 rst <= 1;
      #1 if (q0 !== 1'b0 || q1 !== 1'b0) begin
	 $display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1);
	 $finish;
      end

      #1 rst <= 0;
      #1 if (q0 !== 1'b0 || q1 !== 1'b0) begin
	 $display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1);
	 $finish;
      end

      #1 clk <= 0;
      #1 clk <= 1;
      #1 if (q0 !== d0 || q1 !== d1) begin
	 $display("FAILED -- Q0=%b Q1=%b, D0=%b D1=%b", q0, q1, d0, d1);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule