data/full_repos/permissive/143278/ivltests/pr1623097.v
 line:17: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1623097.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #0;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr1623097.v:17: Unsupported or unknown PLI call: $monitor\n    $monitor($time,,"clk=%b, data=%b, clear=%b, state=%b",\n    ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1623097.v:17: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    $monitor($time,,"clk=%b, data=%b, clear=%b, state=%b",\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1623097.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 clear = 4\'b0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1623097.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1623097.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 0; clear = 4\'b0010;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1623097.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 clear = 4\'b0000; data = 4\'b1010;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1623097.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1623097.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 0;\n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

  reg [3:0] state;
  reg [3:0] data;
  reg [3:0] clear;
  reg clk;

  genvar i;

  initial begin
    #0;
    clk = 0; data = 4'b1111; clear = 4'b1111;
    $monitor($time,,"clk=%b, data=%b, clear=%b, state=%b",
	    clk, data, clear, state);

    #10 clear = 4'b0000;
    #10 clk = 1;
    #10 clk = 0; clear = 4'b0010;
    #10 clear = 4'b0000; data = 4'b1010;
    #10 clk = 1;
    #10 clk = 0;
  end



  generate for (i=0; i<4; i=i+1) begin:sm
    always @(posedge clk or posedge clear[i]) begin
      if (clear[i]) state[i] <= 1'b0;
      else begin
        state[i] <= #1 data[i];
      end
    end
  end endgenerate



























endmodule
module top;


  reg [3:0] state;
  reg [3:0] data;
  reg [3:0] clear;
  reg clk;

  genvar i;

  initial begin
    #0;
    clk = 0; data = 4'b1111; clear = 4'b1111;
    $monitor($time,,"clk=%b, data=%b, clear=%b, state=%b",
	    clk, data, clear, state);

    #10 clear = 4'b0000;
    #10 clk = 1;
    #10 clk = 0; clear = 4'b0010;
    #10 clear = 4'b0000; data = 4'b1010;
    #10 clk = 1;
    #10 clk = 0;
  end



  generate for (i=0; i<4; i=i+1) begin:sm
    always @(posedge clk or posedge clear[i]) begin
      if (clear[i]) state[i] <= 1'b0;
      else begin
        state[i] <= #1 data[i];
      end
    end
  end endgenerate



























endmodule