data/full_repos/permissive/171720620/hardware/SingleCycleCPU/src/sources/EnablePC.v
1: b"%Error: data/full_repos/permissive/171720620/hardware/SingleCycleCPU/src/sources/EnablePC.v:27: Cannot find file containing module: 'Reg'\n    Reg pc_enable_reg(.data_in(syscall), .enable(enable_in), .clk(clk), .rst(rst_in), .data_out(pc_enable_out));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/171720620/hardware/SingleCycleCPU/src/sources,data/full_repos/permissive/171720620/Reg\n             data/full_repos/permissive/171720620/hardware/SingleCycleCPU/src/sources,data/full_repos/permissive/171720620/Reg.v\n             data/full_repos/permissive/171720620/hardware/SingleCycleCPU/src/sources,data/full_repos/permissive/171720620/Reg.sv\n             Reg\n             Reg.v\n             Reg.sv\n             obj_dir/Reg\n             obj_dir/Reg.v\n             obj_dir/Reg.sv\n%Error: Exiting due to 1 error(s)\n"
module EnablePC (
        input syscall,
        input show, 
        input rst,
        input go,
        input clk,
        output pc_enable
    );
    wire enable_in;
    wire rst_in;
    wire pc_enable_out;

    Reg pc_enable_reg(.data_in(syscall), .enable(enable_in), .clk(clk), .rst(rst_in), .data_out(pc_enable_out));

    assign enable_in = syscall & ~show;

    assign rst_in = rst | go;

    assign pc_enable = ~pc_enable_out;

endmodule
module EnablePC (
        input syscall,
        input show, 
        input rst,
        input go,
        input clk,
        output pc_enable
    );

    wire enable_in;
    wire rst_in;
    wire pc_enable_out;

    Reg pc_enable_reg(.data_in(syscall), .enable(enable_in), .clk(clk), .rst(rst_in), .data_out(pc_enable_out));

    assign enable_in = syscall & ~show;

    assign rst_in = rst | go;

    assign pc_enable = ~pc_enable_out;

endmodule