data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/IC8216_testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/IC8216_testbench.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/IC8216_testbench.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #200;    \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/IC8216_testbench.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/IC8216_testbench.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/IC8216_testbench.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/IC8216_testbench.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/IC8216_testbench.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #100 counter <= counter + 1;\n        ^\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/IC8216_testbench.v:48: Cannot find file containing module: \'IC82x6\'\n    IC82x6 # (.INVERTED_OUTPUT(0))\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/IC82x6\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/IC82x6.v\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/IC82x6.sv\n             IC82x6\n             IC82x6.v\n             IC82x6.sv\n             obj_dir/IC82x6\n             obj_dir/IC82x6.v\n             obj_dir/IC82x6.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module IC8216_testbench;


    reg [3:0] d_in;
    reg cs_n;
    reg dce;


    wire [3:0] d_out;


    wire [3:0] d_bus;
    
    localparam [3:0] TEST_VALUE_1 = 4'b0101;
    localparam [3:0] TEST_VALUE_2 = 4'b0001;
    localparam [3:0] TEST_VALUE_3 = 4'b1001;
    
    reg [3:0] d_bus_reg;
    wire [3:0] d_bus_net;

    assign d_bus = dce == 1'b1 ? d_bus_reg : d_bus_net;


    IC82x6 # (.INVERTED_OUTPUT(0))
    uut (
        .d_in(d_in), 
        .d_out(d_out), 
        .d_bus(d_bus), 
        .cs_n(cs_n), 
        .dce(dce)
    );
    
    reg[7:0] counter;

    initial begin



        d_bus_reg = 4'b0000;
        d_in = TEST_VALUE_1;
        cs_n = 1;
        dce = 0;
        
        #200;


        cs_n = 0;    
        d_in = TEST_VALUE_1;
        counter = 0;

        #200;    

        dce = 1;
        
        d_bus_reg = 4'b1111;
      
        #200;


        d_in = TEST_VALUE_2;
        cs_n = 1;
        dce = 0;
        
        #200;


        cs_n = 0;
        d_in = TEST_VALUE_2;

        #200;

        dce = 1;
        d_bus_reg = 4'b1110;
        

        #200;

        cs_n = 1;
    end
    
    always
    begin
        #100 counter <= counter + 1;
        if (counter == 13)
            d_bus_reg <= 4'b0100;
        if (counter == 14)
        begin

            d_bus_reg <= 4'b1111;
            dce <= 1;
            cs_n <= 0;
        end
        if (counter == 16)
        begin
            cs_n <= 1;

        end
         
        if (counter == 18)
        begin
            d_in <= TEST_VALUE_3;
            dce <= 0;
            cs_n <= 0;

        end
         
        if (counter == 20)
        begin
            cs_n <= 1;
            counter <= 0;

        end
    end
      
endmodule
module IC8216_testbench;



    reg [3:0] d_in;
    reg cs_n;
    reg dce;


    wire [3:0] d_out;


    wire [3:0] d_bus;
    
    localparam [3:0] TEST_VALUE_1 = 4'b0101;
    localparam [3:0] TEST_VALUE_2 = 4'b0001;
    localparam [3:0] TEST_VALUE_3 = 4'b1001;
    
    reg [3:0] d_bus_reg;
    wire [3:0] d_bus_net;

    assign d_bus = dce == 1'b1 ? d_bus_reg : d_bus_net;


    IC82x6 # (.INVERTED_OUTPUT(0))
    uut (
        .d_in(d_in), 
        .d_out(d_out), 
        .d_bus(d_bus), 
        .cs_n(cs_n), 
        .dce(dce)
    );
    
    reg[7:0] counter;

    initial begin



        d_bus_reg = 4'b0000;
        d_in = TEST_VALUE_1;
        cs_n = 1;
        dce = 0;
        
        #200;


        cs_n = 0;    
        d_in = TEST_VALUE_1;
        counter = 0;

        #200;    

        dce = 1;
        
        d_bus_reg = 4'b1111;
      
        #200;


        d_in = TEST_VALUE_2;
        cs_n = 1;
        dce = 0;
        
        #200;


        cs_n = 0;
        d_in = TEST_VALUE_2;

        #200;

        dce = 1;
        d_bus_reg = 4'b1110;
        

        #200;

        cs_n = 1;
    end
    
    always
    begin
        #100 counter <= counter + 1;
        if (counter == 13)
            d_bus_reg <= 4'b0100;
        if (counter == 14)
        begin

            d_bus_reg <= 4'b1111;
            dce <= 1;
            cs_n <= 0;
        end
        if (counter == 16)
        begin
            cs_n <= 1;

        end
         
        if (counter == 18)
        begin
            d_in <= TEST_VALUE_3;
            dce <= 0;
            cs_n <= 0;

        end
         
        if (counter == 20)
        begin
            cs_n <= 1;
            counter <= 0;

        end
    end
      
endmodule