data/full_repos/permissive/108908995/ssd.sv
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:22: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sen'\n                                                                  : ... In instance ssd\n            sen = 4'b1110;\n            ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:23: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'hb'\n                                                                  : ... In instance ssd\n            hb = WORD[3:0];\n            ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:26: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sen'\n                                                                  : ... In instance ssd\n            sen = 4'b1101;\n            ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:27: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'hb'\n                                                                  : ... In instance ssd\n            hb = WORD[7:4];\n            ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:30: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sen'\n                                                                  : ... In instance ssd\n            sen = 4'b1011;\n            ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:31: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'hb'\n                                                                  : ... In instance ssd\n            hb = WORD[11:8];\n            ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:34: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'sen'\n                                                                  : ... In instance ssd\n            sen = 4'b0111;\n            ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:35: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'hb'\n                                                                  : ... In instance ssd\n            hb = WORD[15:12];\n            ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:44: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'h0: ssc = 7'b1111110;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:45: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'h1: ssc = 7'b0110000;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:46: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'h2: ssc = 7'b1101101;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:47: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'h3: ssc = 7'b1111001;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:48: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'h4: ssc = 7'b0110011;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:49: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'h5: ssc = 7'b1011011;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:50: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'h6: ssc = 7'b1011111;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:51: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'h7: ssc = 7'b1110000;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:52: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'h8: ssc = 7'b1111111;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:53: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'h9: ssc = 7'b1111011;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:54: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'ha: ssc = 7'b1110111;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:55: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'hb: ssc = 7'b0011111;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:56: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'hc: ssc = 7'b1001110;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:57: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'hd: ssc = 7'b0111101;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:58: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'he: ssc = 7'b1101111;\n              ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/108908995/ssd.sv:59: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'ssc'\n                                                                  : ... In instance ssd\n        4'hf: ssc = 7'b1000111;\n              ^~~\n%Error: Exiting due to 24 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module ssd
(
    input CLK,
    input [15:0]WORD,
    input EN,

    output SEN1, SEN2, SEN3, SEN4,
    output SSA, SSB, SSC, SSD, SSE, SSF, SSG    
);

reg [15:0]cnt = 16'b0;
always @(posedge CLK) begin
    cnt <= cnt + 16'b1;
end

wire [3:0]sen;
assign {SEN1, SEN2, SEN3, SEN4} = EN ? sen : 4'b1111;
wire [3:0]hb;
always_comb begin
    case (cnt[15:14])
        2'b00: begin
            sen = 4'b1110;
            hb = WORD[3:0];
        end
        2'b01: begin
            sen = 4'b1101;
            hb = WORD[7:4];
        end
        2'b10: begin
            sen = 4'b1011;
            hb = WORD[11:8];
        end
        2'b11: begin
            sen = 4'b0111;
            hb = WORD[15:12];
        end
    endcase 
end

wire [6:0]ssc;
assign {SSA, SSB, SSC, SSD, SSE, SSF, SSG} = ssc;
always_comb begin
    case (hb)
        4'h0: ssc = 7'b1111110;
        4'h1: ssc = 7'b0110000;
        4'h2: ssc = 7'b1101101;
        4'h3: ssc = 7'b1111001;
        4'h4: ssc = 7'b0110011;
        4'h5: ssc = 7'b1011011;
        4'h6: ssc = 7'b1011111;
        4'h7: ssc = 7'b1110000;
        4'h8: ssc = 7'b1111111;
        4'h9: ssc = 7'b1111011;
        4'ha: ssc = 7'b1110111;
        4'hb: ssc = 7'b0011111;
        4'hc: ssc = 7'b1001110;
        4'hd: ssc = 7'b0111101;
        4'he: ssc = 7'b1101111;
        4'hf: ssc = 7'b1000111;
    endcase
end

endmodule
module ssd
(
    input CLK,
    input [15:0]WORD,
    input EN,

    output SEN1, SEN2, SEN3, SEN4,
    output SSA, SSB, SSC, SSD, SSE, SSF, SSG    
);


reg [15:0]cnt = 16'b0;
always @(posedge CLK) begin
    cnt <= cnt + 16'b1;
end

wire [3:0]sen;
assign {SEN1, SEN2, SEN3, SEN4} = EN ? sen : 4'b1111;
wire [3:0]hb;
always_comb begin
    case (cnt[15:14])
        2'b00: begin
            sen = 4'b1110;
            hb = WORD[3:0];
        end
        2'b01: begin
            sen = 4'b1101;
            hb = WORD[7:4];
        end
        2'b10: begin
            sen = 4'b1011;
            hb = WORD[11:8];
        end
        2'b11: begin
            sen = 4'b0111;
            hb = WORD[15:12];
        end
    endcase 
end

wire [6:0]ssc;
assign {SSA, SSB, SSC, SSD, SSE, SSF, SSG} = ssc;
always_comb begin
    case (hb)
        4'h0: ssc = 7'b1111110;
        4'h1: ssc = 7'b0110000;
        4'h2: ssc = 7'b1101101;
        4'h3: ssc = 7'b1111001;
        4'h4: ssc = 7'b0110011;
        4'h5: ssc = 7'b1011011;
        4'h6: ssc = 7'b1011111;
        4'h7: ssc = 7'b1110000;
        4'h8: ssc = 7'b1111111;
        4'h9: ssc = 7'b1111011;
        4'ha: ssc = 7'b1110111;
        4'hb: ssc = 7'b0011111;
        4'hc: ssc = 7'b1001110;
        4'hd: ssc = 7'b0111101;
        4'he: ssc = 7'b1101111;
        4'hf: ssc = 7'b1000111;
    endcase
end

endmodule