data/full_repos/permissive/115351337/uart/transmitter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:40: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n                                                                          : ... In instance uart_tx\n    reg [1:0]  state = IDLE;\n                       ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:51: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'TRANSMIT\' generates 3 bits.\n                                                                          : ... In instance uart_tx\n                    state <= TRANSMIT;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:53: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                          : ... In instance uart_tx\n                    buffer <= data[7:0];\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:55: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n                                                                          : ... In instance uart_tx\n                    state <= IDLE;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:64: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'DONE\' generates 3 bits.\n                                                                          : ... In instance uart_tx\n                    state <= DONE;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:76: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n                                                                          : ... In instance uart_tx\n                state <= IDLE;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:80: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n                                                                          : ... In instance uart_tx\n                state <= IDLE;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/transmitter.v:46: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n                                                                          : ... In instance uart_tx\n        case (state)\n        ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:49: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'tx\'\n                                                                              : ... In instance uart_tx\n                    tx <= 1\'b0;\n                    ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:52: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'in_progress\'\n                                                                              : ... In instance uart_tx\n                    in_progress <= 1\'b1;\n                    ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:56: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'tx\'\n                                                                              : ... In instance uart_tx\n                    tx <= 1\'b1;\n                    ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:57: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'in_progress\'\n                                                                              : ... In instance uart_tx\n                    in_progress <= 1\'b0;\n                    ^~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:67: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'tx\'\n                                                                              : ... In instance uart_tx\n                    tx <= buffer[bit_transmitted];\n                    ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/115351337/uart/transmitter.v:70: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'tx\'\n                                                                              : ... In instance uart_tx\n                    tx <= tx;\n                    ^~\n%Error: Exiting due to 6 error(s), 8 warning(s)\n'
module uart_tx (
    input            clk,
    input [7:0]      data,
    input            start,
    output           in_progress,
    output           tx
);
    parameter LIMIT          = 104;
    parameter IDLE           = 3'b00;
    parameter TRANSMIT       = 3'b01;
    parameter DONE           = 3'b10;

    reg [1:0]  state = IDLE;
    reg [31:0] count = 0;
    reg [3:0]  bit_transmitted = 0;
    reg [8:0]  buffer;

    always @(posedge clk) begin
        case (state)
            IDLE: begin
                if (start == 1'b1) begin
                    tx <= 1'b0;
                    count <= 0;
                    state <= TRANSMIT;
                    in_progress <= 1'b1;
                    buffer <= data[7:0];
                end else begin
                    state <= IDLE;
                    tx <= 1'b1;
                    in_progress <= 1'b0;
                    bit_transmitted <= 0;
                end
            end

            TRANSMIT: begin
                if ( bit_transmitted == 9 ) begin
                    state <= DONE;
                end else if (count == LIMIT) begin
                    count <= 0;
                    tx <= buffer[bit_transmitted];
                    bit_transmitted <= bit_transmitted + 1;
                end else begin
                    tx <= tx;
                    count <= count + 1;
                end
            end

            DONE: begin
                state <= IDLE;
            end

            default: begin
                state <= IDLE;
            end
        endcase
    end
endmodule
module uart_tx (
    input            clk,
    input [7:0]      data,
    input            start,
    output           in_progress,
    output           tx
);

    parameter LIMIT          = 104;
    parameter IDLE           = 3'b00;
    parameter TRANSMIT       = 3'b01;
    parameter DONE           = 3'b10;

    reg [1:0]  state = IDLE;
    reg [31:0] count = 0;
    reg [3:0]  bit_transmitted = 0;
    reg [8:0]  buffer;

    always @(posedge clk) begin
        case (state)
            IDLE: begin
                if (start == 1'b1) begin
                    tx <= 1'b0;
                    count <= 0;
                    state <= TRANSMIT;
                    in_progress <= 1'b1;
                    buffer <= data[7:0];
                end else begin
                    state <= IDLE;
                    tx <= 1'b1;
                    in_progress <= 1'b0;
                    bit_transmitted <= 0;
                end
            end

            TRANSMIT: begin
                if ( bit_transmitted == 9 ) begin
                    state <= DONE;
                end else if (count == LIMIT) begin
                    count <= 0;
                    tx <= buffer[bit_transmitted];
                    bit_transmitted <= bit_transmitted + 1;
                end else begin
                    tx <= tx;
                    count <= count + 1;
                end
            end

            DONE: begin
                state <= IDLE;
            end

            default: begin
                state <= IDLE;
            end
        endcase
    end
endmodule