data/full_repos/permissive/139213403/FPGA/digital_readout_array.v
None: at end of input
1: b'%Error: data/full_repos/permissive/139213403/FPGA/digital_readout_array.v:45: Cannot find file containing module: \'bin2bcd\'\n bin2bcd #(.BCD_N(READOUT_W-1), .BIN_N(READOUT_BIN_N)) b2bcd(.clk(clk), .reset(reset), .start(start_reg), .bin(val), .ready(bcd_ready), .done_tick(bcd_done_tick), .bcd(bcd));\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/bin2bcd\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/bin2bcd.v\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/bin2bcd.sv\n             bin2bcd\n             bin2bcd.v\n             bin2bcd.sv\n             obj_dir/bin2bcd\n             obj_dir/bin2bcd.v\n             obj_dir/bin2bcd.sv\n%Error: data/full_repos/permissive/139213403/FPGA/digital_readout_array.v:46: Cannot find file containing module: \'sseg_array\'\n sseg_array #(.SSEG_BITS(READOUT_N_BITS + READOUT_W_BITS), .SSEG_N(READOUT_N*READOUT_W), .C_ON_DIV_SSEG_N(C_ON_DIV_SSEG_N), .C_OFF_DIV_SSEG_N(C_OFF_DIV_SSEG_N), .C_BITS(C_BITS))           \n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/digital_readout_array.v:108: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s MUL generates 32 or 3 bits.\n                                                                                     : ... In instance digital_readout_array\n        sel_next = sel * READOUT_W;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/digital_readout_array.v:130: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 12 bits.\n                                                                                     : ... In instance digital_readout_array\n        bcd_next = (bcd >> (4 * n_next));\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/digital_readout_array.v:121: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'n_next\' generates 2 bits.\n                                                                                     : ... In instance digital_readout_array\n      else if (n_next == READOUT_W - 1)\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/digital_readout_array.v:115: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'n_next\' generates 2 bits.\n                                                                                     : ... In instance digital_readout_array\n      if (n_next == READOUT_W)\n                 ^~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module digital_readout_array
#(
	parameter READOUT_N_BITS=2,
				 READOUT_W_BITS=2,
				 READOUT_N=4,
				 READOUT_W=4,
				 READOUT_BIN_N=10,
				 READOUT_DECM_N=2,
				 

				 C_ON_DIV_SSEG_N=2,
				 C_OFF_DIV_SSEG_N=3,
				 C_BITS=3
)
(
	input wire clk, reset,
	input wire en, wr,
	input wire [READOUT_N_BITS-1:0] sel,
	input wire [READOUT_BIN_N-1:0] val,
	input wire [READOUT_DECM_N-1:0] mantissa,
	input wire sign, blink,
	output wire [7:0] sseg,
	output reg ready, done_tick,
	output wire [READOUT_N*READOUT_W-1:0] oe
);

	localparam [2:0] idle    = 3'd0,
	                 encode  = 3'd1,
						  write   = 3'd2,
						  stop    = 3'd3;
	
	
	reg [2:0] state_reg, state_next;
	reg start_reg, start_next;
	reg sign_reg, sign_next;
	reg [READOUT_N_BITS-1:0] sel_reg, sel_next;
	reg en_reg, en_next;
	reg dp_reg, dp_next;
	reg wr_reg, wr_next;
	reg [3:0] bcd_reg, bcd_next;
	reg [READOUT_W_BITS-1:0] n_reg, n_next;
	wire bcd_ready, bcd_done_tick;
	wire [(READOUT_W-1)*4-1:0] bcd;
	
	bin2bcd #(.BCD_N(READOUT_W-1), .BIN_N(READOUT_BIN_N)) b2bcd(.clk(clk), .reset(reset), .start(start_reg), .bin(val), .ready(bcd_ready), .done_tick(bcd_done_tick), .bcd(bcd));
	sseg_array #(.SSEG_BITS(READOUT_N_BITS + READOUT_W_BITS), .SSEG_N(READOUT_N*READOUT_W), .C_ON_DIV_SSEG_N(C_ON_DIV_SSEG_N), .C_OFF_DIV_SSEG_N(C_OFF_DIV_SSEG_N), .C_BITS(C_BITS))           
	           ssegarr(.clk(clk), .reset(reset), .en(en), .wr(wr), .sel(n_reg), .val(bcd[bcd_reg]), .sign(sign_reg), .dp(dp_reg), .blink(blink), .sseg(sseg), .oe(oe));


	always @(posedge clk, posedge reset)
		if (reset)
			begin
				state_reg <= 0;
				start_reg <= 0;
				sel_reg <= 0;
				sign_reg <= 0;
				en_reg <= 0;
				dp_reg <= 0;
				wr_reg <= 0;
				bcd_reg <= 0;
				n_reg <= 0;
			end
		else
			begin
				state_reg <= state_next;
				start_reg <= start_next;
				sel_reg <= sel_next;
				sign_reg <= sign_next;
				en_reg <= en_next;
				wr_reg <= wr_next;
				dp_reg <= dp_next;
				bcd_reg <= bcd_next;
				n_reg <= n_next;
			end
			
	always @*
		begin
			state_next = state_reg;
			start_next = start_reg;
			sign_next = sign_reg;
			sel_next = sel_reg;
			en_next = en_reg;
			dp_next = dp_reg;
			wr_next = wr_reg;
			bcd_next = bcd_reg;
			n_next = n_reg;
			ready = 1'b0;
			done_tick = 1'b0;
			
			case (state_reg)
				idle: 
					begin
						ready = 1'b1;
						if (wr)
							begin
								start_next = 1'b1;
								state_next = encode;
							end
					end
				encode:
					begin
						if (bcd_done_tick)
							begin
								n_next = 0;
								sign_next = 0;
								en_next = 0;
								wr_next = 1'b1;
								sel_next = sel * READOUT_W;
								state_next = write;
							end
					end
				write:
					begin
						dp_next = 1'b0;
						if (n_next == READOUT_W)
							begin

								wr_next = 1'b0;
								state_next = stop;
							end
						else if (n_next == READOUT_W - 1)
							begin

								en_next = sign;
								sign_next = sign;
							end
						else
							begin

								bcd_next = (bcd >> (4 * n_next));
								en_next = (n_next == 0) || (bcd_next != 0);
								if (n_next == mantissa)
									dp_next = 1'b1;
							end
							
						sel_next = sel_next + 1'b1;
						n_next = n_next + 1'b1;
					end
				stop:
					begin
						done_tick = 1'b1;
						state_next = idle;
					end
			endcase
		end
				  
endmodule
module digital_readout_array
#(
	parameter READOUT_N_BITS=2,
				 READOUT_W_BITS=2,
				 READOUT_N=4,
				 READOUT_W=4,
				 READOUT_BIN_N=10,
				 READOUT_DECM_N=2,
				 

				 C_ON_DIV_SSEG_N=2,
				 C_OFF_DIV_SSEG_N=3,
				 C_BITS=3
)
(
	input wire clk, reset,
	input wire en, wr,
	input wire [READOUT_N_BITS-1:0] sel,
	input wire [READOUT_BIN_N-1:0] val,
	input wire [READOUT_DECM_N-1:0] mantissa,
	input wire sign, blink,
	output wire [7:0] sseg,
	output reg ready, done_tick,
	output wire [READOUT_N*READOUT_W-1:0] oe
);


	localparam [2:0] idle    = 3'd0,
	                 encode  = 3'd1,
						  write   = 3'd2,
						  stop    = 3'd3;
	
	
	reg [2:0] state_reg, state_next;
	reg start_reg, start_next;
	reg sign_reg, sign_next;
	reg [READOUT_N_BITS-1:0] sel_reg, sel_next;
	reg en_reg, en_next;
	reg dp_reg, dp_next;
	reg wr_reg, wr_next;
	reg [3:0] bcd_reg, bcd_next;
	reg [READOUT_W_BITS-1:0] n_reg, n_next;
	wire bcd_ready, bcd_done_tick;
	wire [(READOUT_W-1)*4-1:0] bcd;
	
	bin2bcd #(.BCD_N(READOUT_W-1), .BIN_N(READOUT_BIN_N)) b2bcd(.clk(clk), .reset(reset), .start(start_reg), .bin(val), .ready(bcd_ready), .done_tick(bcd_done_tick), .bcd(bcd));
	sseg_array #(.SSEG_BITS(READOUT_N_BITS + READOUT_W_BITS), .SSEG_N(READOUT_N*READOUT_W), .C_ON_DIV_SSEG_N(C_ON_DIV_SSEG_N), .C_OFF_DIV_SSEG_N(C_OFF_DIV_SSEG_N), .C_BITS(C_BITS))           
	           ssegarr(.clk(clk), .reset(reset), .en(en), .wr(wr), .sel(n_reg), .val(bcd[bcd_reg]), .sign(sign_reg), .dp(dp_reg), .blink(blink), .sseg(sseg), .oe(oe));


	always @(posedge clk, posedge reset)
		if (reset)
			begin
				state_reg <= 0;
				start_reg <= 0;
				sel_reg <= 0;
				sign_reg <= 0;
				en_reg <= 0;
				dp_reg <= 0;
				wr_reg <= 0;
				bcd_reg <= 0;
				n_reg <= 0;
			end
		else
			begin
				state_reg <= state_next;
				start_reg <= start_next;
				sel_reg <= sel_next;
				sign_reg <= sign_next;
				en_reg <= en_next;
				wr_reg <= wr_next;
				dp_reg <= dp_next;
				bcd_reg <= bcd_next;
				n_reg <= n_next;
			end
			
	always @*
		begin
			state_next = state_reg;
			start_next = start_reg;
			sign_next = sign_reg;
			sel_next = sel_reg;
			en_next = en_reg;
			dp_next = dp_reg;
			wr_next = wr_reg;
			bcd_next = bcd_reg;
			n_next = n_reg;
			ready = 1'b0;
			done_tick = 1'b0;
			
			case (state_reg)
				idle: 
					begin
						ready = 1'b1;
						if (wr)
							begin
								start_next = 1'b1;
								state_next = encode;
							end
					end
				encode:
					begin
						if (bcd_done_tick)
							begin
								n_next = 0;
								sign_next = 0;
								en_next = 0;
								wr_next = 1'b1;
								sel_next = sel * READOUT_W;
								state_next = write;
							end
					end
				write:
					begin
						dp_next = 1'b0;
						if (n_next == READOUT_W)
							begin

								wr_next = 1'b0;
								state_next = stop;
							end
						else if (n_next == READOUT_W - 1)
							begin

								en_next = sign;
								sign_next = sign;
							end
						else
							begin

								bcd_next = (bcd >> (4 * n_next));
								en_next = (n_next == 0) || (bcd_next != 0);
								if (n_next == mantissa)
									dp_next = 1'b1;
							end
							
						sel_next = sel_next + 1'b1;
						n_next = n_next + 1'b1;
					end
				stop:
					begin
						done_tick = 1'b1;
						state_next = idle;
					end
			endcase
		end
				  
endmodule