data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/hdl/5932_74HC74.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/hdl/5932_74HC74.v:3: Little bit endian vector: MSB < LSB of bit range: 1:2\ninput [1:2]D,Clk,SD,RD;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/hdl/5932_74HC74.v:4: Little bit endian vector: MSB < LSB of bit range: 1:2\noutput [1:2]Q,QN;\n       ^\n%Error: Exiting due to 2 warning(s)\n'
module HC74(D,Clk,Q,SD,RD,QN);
input [1:2]D,Clk,SD,RD;
output [1:2]Q,QN;
reg [1:2]Q;
assign QN=~Q;

always@(posedge Clk[1] or negedge RD[1] or negedge SD[1])
 case({RD[1],SD[1]})
  2'b00:Q[1]<=1;
  2'b01:Q[1]<=0;
  2'b10:Q[1]<=1;
  2'b11:Q[1]<=D[1];
 endcase

always@(posedge Clk[2] or negedge RD[2] or negedge SD[2])
 case({RD[2],SD[2]})
  2'b00:Q[2]<=1;
  2'b01:Q[2]<=0;
  2'b10:Q[2]<=1;
  2'b11:Q[2]<=D[2];
 endcase

endmodule
module HC74(D,Clk,Q,SD,RD,QN);

input [1:2]D,Clk,SD,RD;
output [1:2]Q,QN;
reg [1:2]Q;
assign QN=~Q;

always@(posedge Clk[1] or negedge RD[1] or negedge SD[1])
 case({RD[1],SD[1]})
  2'b00:Q[1]<=1;
  2'b01:Q[1]<=0;
  2'b10:Q[1]<=1;
  2'b11:Q[1]<=D[1];
 endcase

always@(posedge Clk[2] or negedge RD[2] or negedge SD[2])
 case({RD[2],SD[2]})
  2'b00:Q[2]<=1;
  2'b01:Q[2]<=0;
  2'b10:Q[2]<=1;
  2'b11:Q[2]<=D[2];
 endcase

endmodule