data/full_repos/permissive/201488448/2_circuits/1_combinational/04_gate.v
data/verilator_xmls/b27465be-036f-44b8-bad7-0c71cb3d034d.xml
module top_module (
    input in1,
    input in2,
    output out);

    assign	out = in1&(~in2);
    
endmodule
module top_module (
    input in1,
    input in2,
    output out);


    assign	out = in1&(~in2);
    
endmodule