data/full_repos/permissive/201224775/rtl/ic/ic_cpu_bus_mux.v
data/verilator_xmls/5828adf4-9dd2-44cf-816a-89e36f85a7ec.xml
module ic_cpu_bus_mux (

input  wire        g_clk          ,
input  wire        g_resetn       ,

input  wire        s0_mem_req     ,
input  wire        s0_mem_wen     ,
input  wire [ 3:0] s0_mem_strb    ,
input  wire [31:0] s0_mem_wdata   ,
input  wire [31:0] s0_mem_addr    ,
output wire        s0_mem_gnt     ,
output wire        s0_mem_recv    ,
input  wire        s0_mem_ack     ,
output wire        s0_mem_error   ,
output wire [31:0] s0_mem_rdata   ,

input  wire        s1_mem_req     ,
input  wire        s1_mem_wen     ,
input  wire [ 3:0] s1_mem_strb    ,
input  wire [31:0] s1_mem_wdata   ,
input  wire [31:0] s1_mem_addr    ,
output wire        s1_mem_gnt     ,
output wire        s1_mem_recv    ,
input  wire        s1_mem_ack     ,
output wire        s1_mem_error   ,
output wire [31:0] s1_mem_rdata   ,

output wire        m0_mem_req     ,
output wire        m0_mem_wen     ,
output wire [ 3:0] m0_mem_strb    ,
output wire [31:0] m0_mem_wdata   ,
output wire [31:0] m0_mem_addr    ,
input  wire        m0_mem_gnt     ,
input  wire        m0_mem_recv    ,
output wire        m0_mem_ack     ,
input  wire        m0_mem_error   ,
input  wire [31:0] m0_mem_rdata

);





assign s0_mem_error     = m0_mem_error;
assign s0_mem_rdata     = m0_mem_rdata;

assign s1_mem_error     = m0_mem_error;
assign s1_mem_rdata     = m0_mem_rdata;





reg  s0_delayed_req;
reg  s1_delayed_req;

wire n_s0_delayed_req = s0_mem_req && !s0_mem_gnt;
wire n_s1_delayed_req = s1_mem_req && !s1_mem_gnt;

always @(posedge g_clk) begin
    if(!g_resetn) begin
        s0_delayed_req <= 1'b0;
        s1_delayed_req <= 1'b0;
    end else begin
        s0_delayed_req <= n_s0_delayed_req;
        s1_delayed_req <= n_s1_delayed_req;
    end
end





reg    hold_s1_req;

always @(posedge g_clk) begin
    if(!g_resetn) begin
        hold_s1_req <= 1'b0;
    end else if(s1_mem_req && s1_mem_gnt) begin
        hold_s1_req <= 1'b0;
    end else begin
        hold_s1_req <= s1_mem_req && !s0_mem_req;
    end
end

wire   route_s0_req = s0_mem_req && !hold_s1_req;

assign m0_mem_req   = s0_mem_req || s1_mem_req;

assign m0_mem_wen   = route_s0_req ? s0_mem_wen   : s1_mem_wen    ;
assign m0_mem_addr  = route_s0_req ? s0_mem_addr  : s1_mem_addr   ;
assign m0_mem_strb  = route_s0_req ? s0_mem_strb  : s1_mem_strb   ;
assign m0_mem_wdata = route_s0_req ? s0_mem_wdata : s1_mem_wdata  ;






reg  s0_rsp_out;
reg  s1_rsp_out;
        
wire n_s0_rsp_out =  (s0_mem_req  && s0_mem_gnt || s0_rsp_out) &&
                    !(s0_mem_recv && s0_mem_ack);

wire n_s1_rsp_out =  (s1_mem_req  && s1_mem_gnt || s1_rsp_out) &&
                    !(s1_mem_recv && s1_mem_ack);

always @(posedge g_clk) begin
    if(!g_resetn) begin
        s0_rsp_out <= 1'b0;
        s1_rsp_out <= 1'b0;
    end else begin
        s0_rsp_out <= n_s0_rsp_out;
        s1_rsp_out <= n_s1_rsp_out;
    end
end





assign s0_mem_recv  = s0_rsp_out && m0_mem_recv;
assign s1_mem_recv  = s1_rsp_out && m0_mem_recv;

assign m0_mem_ack   = s0_rsp_out ? s0_mem_ack : s1_mem_ack;

endmodule
module ic_cpu_bus_mux (

input  wire        g_clk          ,
input  wire        g_resetn       ,

input  wire        s0_mem_req     ,
input  wire        s0_mem_wen     ,
input  wire [ 3:0] s0_mem_strb    ,
input  wire [31:0] s0_mem_wdata   ,
input  wire [31:0] s0_mem_addr    ,
output wire        s0_mem_gnt     ,
output wire        s0_mem_recv    ,
input  wire        s0_mem_ack     ,
output wire        s0_mem_error   ,
output wire [31:0] s0_mem_rdata   ,

input  wire        s1_mem_req     ,
input  wire        s1_mem_wen     ,
input  wire [ 3:0] s1_mem_strb    ,
input  wire [31:0] s1_mem_wdata   ,
input  wire [31:0] s1_mem_addr    ,
output wire        s1_mem_gnt     ,
output wire        s1_mem_recv    ,
input  wire        s1_mem_ack     ,
output wire        s1_mem_error   ,
output wire [31:0] s1_mem_rdata   ,

output wire        m0_mem_req     ,
output wire        m0_mem_wen     ,
output wire [ 3:0] m0_mem_strb    ,
output wire [31:0] m0_mem_wdata   ,
output wire [31:0] m0_mem_addr    ,
input  wire        m0_mem_gnt     ,
input  wire        m0_mem_recv    ,
output wire        m0_mem_ack     ,
input  wire        m0_mem_error   ,
input  wire [31:0] m0_mem_rdata

);






assign s0_mem_error     = m0_mem_error;
assign s0_mem_rdata     = m0_mem_rdata;

assign s1_mem_error     = m0_mem_error;
assign s1_mem_rdata     = m0_mem_rdata;





reg  s0_delayed_req;
reg  s1_delayed_req;

wire n_s0_delayed_req = s0_mem_req && !s0_mem_gnt;
wire n_s1_delayed_req = s1_mem_req && !s1_mem_gnt;

always @(posedge g_clk) begin
    if(!g_resetn) begin
        s0_delayed_req <= 1'b0;
        s1_delayed_req <= 1'b0;
    end else begin
        s0_delayed_req <= n_s0_delayed_req;
        s1_delayed_req <= n_s1_delayed_req;
    end
end





reg    hold_s1_req;

always @(posedge g_clk) begin
    if(!g_resetn) begin
        hold_s1_req <= 1'b0;
    end else if(s1_mem_req && s1_mem_gnt) begin
        hold_s1_req <= 1'b0;
    end else begin
        hold_s1_req <= s1_mem_req && !s0_mem_req;
    end
end

wire   route_s0_req = s0_mem_req && !hold_s1_req;

assign m0_mem_req   = s0_mem_req || s1_mem_req;

assign m0_mem_wen   = route_s0_req ? s0_mem_wen   : s1_mem_wen    ;
assign m0_mem_addr  = route_s0_req ? s0_mem_addr  : s1_mem_addr   ;
assign m0_mem_strb  = route_s0_req ? s0_mem_strb  : s1_mem_strb   ;
assign m0_mem_wdata = route_s0_req ? s0_mem_wdata : s1_mem_wdata  ;






reg  s0_rsp_out;
reg  s1_rsp_out;
        
wire n_s0_rsp_out =  (s0_mem_req  && s0_mem_gnt || s0_rsp_out) &&
                    !(s0_mem_recv && s0_mem_ack);

wire n_s1_rsp_out =  (s1_mem_req  && s1_mem_gnt || s1_rsp_out) &&
                    !(s1_mem_recv && s1_mem_ack);

always @(posedge g_clk) begin
    if(!g_resetn) begin
        s0_rsp_out <= 1'b0;
        s1_rsp_out <= 1'b0;
    end else begin
        s0_rsp_out <= n_s0_rsp_out;
        s1_rsp_out <= n_s1_rsp_out;
    end
end





assign s0_mem_recv  = s0_rsp_out && m0_mem_recv;
assign s1_mem_recv  = s1_rsp_out && m0_mem_recv;

assign m0_mem_ack   = s0_rsp_out ? s0_mem_ack : s1_mem_ack;

endmodule