data/full_repos/permissive/137045072/uart_receiver.v
1: b'%Error: data/full_repos/permissive/137045072/uart_receiver.v:49: syntax error, unexpected bit, expecting IDENTIFIER or \'=\' or do or final\n    reg [3:0] bit;  \n              ^~~\n%Error: data/full_repos/permissive/137045072/uart_receiver.v:63: syntax error, unexpected <=, expecting "\'{"\n            bit <= 0;\n                ^~\n%Error: data/full_repos/permissive/137045072/uart_receiver.v:82: syntax error, unexpected <=, expecting "\'{"\n                    bit <= 0;\n                        ^~\n%Error: data/full_repos/permissive/137045072/uart_receiver.v:84: syntax error, unexpected <=, expecting "\'{"\n                    bit <= bit + 1;\n                        ^~\n%Error: data/full_repos/permissive/137045072/uart_receiver.v:120: syntax error, unexpected ==, expecting "\'{"\n                    if (bit == TRAN_WIDTH - 1)\n                            ^~\n%Error: data/full_repos/permissive/137045072/uart_receiver.v:128: syntax error, unexpected else, expecting endcase\n                else\n                ^~~~\n%Error: Cannot continue\n'
module uart_receiver#(
    parameter CLK_FREQ = 100_000_000
)(
    input clk,
    input rst_n,
    input RxD,
    output [7:0] data,
    output reg data_last
    );


    localparam STATE_READY = 0;
    localparam STATE_RECEIVING = 1;

    localparam DATA_WIDTH = 8;
    localparam TRAN_WIDTH = DATA_WIDTH + 2;

    localparam BAUD_RATE = 9600;
    localparam div_sample = 4;
    localparam CNT_DIV = CLK_FREQ / (BAUD_RATE * div_sample);
    localparam mid_sample = (div_sample/2);

    

    reg shift;
    reg state, next_state;
    reg [3:0] bit;
    reg [1:0] sample;
    reg [13:0] counter;
    reg [TRAN_WIDTH-1:0] cached = 0;
    reg clear_bit, inc_bit, inc_sample, clear_sample;

    assign data = cached[8:1];


    always @(posedge clk, negedge rst_n)
    begin 
        if (!rst_n)
        begin
            state <= STATE_READY;
            bit <= 0;
            counter <= 0;
            sample <= 0;
            cached <= 0;
        end
        else
        begin
            counter <= counter + 1;
            if (counter >= CNT_DIV - 1)
            begin
                counter <= 0;
                state <= next_state;
                if (shift)
                    cached <= {RxD, cached[TRAN_WIDTH-1:1]};
                if (clear_sample)
                    sample <= 0;
                if (inc_sample)
                    sample <= sample + 1;
                if (clear_bit)
                    bit <= 0;
                if (inc_bit)
                    bit <= bit + 1;
            end
        end
    end
    

    always @(posedge clk)
    begin 
        shift <= 0;
        clear_sample <= 0;
        inc_sample <= 0;
        clear_bit <= 0;
        inc_bit <= 0;
        next_state <= STATE_READY;
        data_last <= 0;
        case (state)
            STATE_READY: begin
                if (RxD)
                begin

                    next_state <= STATE_READY;
                end
                else
                begin
                    next_state <= STATE_RECEIVING;
                    clear_bit <= 1;
                    clear_sample <= 1;
                end
            end
            STATE_RECEIVING: begin
                next_state <= STATE_RECEIVING;
                if (sample == mid_sample - 1)
                    shift <= 1;
                if (sample == div_sample - 1)
                begin

                    if (bit == TRAN_WIDTH - 1)
                    begin
                        data_last <= 1;
                        next_state <= STATE_READY;
                    end 
                    inc_bit <= 1;
                    clear_sample <= 1;
                end
                else
                    inc_sample <= 1;
            end
        endcase
    end         
endmodule
module uart_receiver#(
    parameter CLK_FREQ = 100_000_000
)(
    input clk,
    input rst_n,
    input RxD,
    output [7:0] data,
    output reg data_last
    );



    localparam STATE_READY = 0;
    localparam STATE_RECEIVING = 1;

    localparam DATA_WIDTH = 8;
    localparam TRAN_WIDTH = DATA_WIDTH + 2;

    localparam BAUD_RATE = 9600;
    localparam div_sample = 4;
    localparam CNT_DIV = CLK_FREQ / (BAUD_RATE * div_sample);
    localparam mid_sample = (div_sample/2);

    

    reg shift;
    reg state, next_state;
    reg [3:0] bit;
    reg [1:0] sample;
    reg [13:0] counter;
    reg [TRAN_WIDTH-1:0] cached = 0;
    reg clear_bit, inc_bit, inc_sample, clear_sample;

    assign data = cached[8:1];


    always @(posedge clk, negedge rst_n)
    begin 
        if (!rst_n)
        begin
            state <= STATE_READY;
            bit <= 0;
            counter <= 0;
            sample <= 0;
            cached <= 0;
        end
        else
        begin
            counter <= counter + 1;
            if (counter >= CNT_DIV - 1)
            begin
                counter <= 0;
                state <= next_state;
                if (shift)
                    cached <= {RxD, cached[TRAN_WIDTH-1:1]};
                if (clear_sample)
                    sample <= 0;
                if (inc_sample)
                    sample <= sample + 1;
                if (clear_bit)
                    bit <= 0;
                if (inc_bit)
                    bit <= bit + 1;
            end
        end
    end
    

    always @(posedge clk)
    begin 
        shift <= 0;
        clear_sample <= 0;
        inc_sample <= 0;
        clear_bit <= 0;
        inc_bit <= 0;
        next_state <= STATE_READY;
        data_last <= 0;
        case (state)
            STATE_READY: begin
                if (RxD)
                begin

                    next_state <= STATE_READY;
                end
                else
                begin
                    next_state <= STATE_RECEIVING;
                    clear_bit <= 1;
                    clear_sample <= 1;
                end
            end
            STATE_RECEIVING: begin
                next_state <= STATE_RECEIVING;
                if (sample == mid_sample - 1)
                    shift <= 1;
                if (sample == div_sample - 1)
                begin

                    if (bit == TRAN_WIDTH - 1)
                    begin
                        data_last <= 1;
                        next_state <= STATE_READY;
                    end 
                    inc_bit <= 1;
                    clear_sample <= 1;
                end
                else
                    inc_sample <= 1;
            end
        endcase
    end         
endmodule