data/full_repos/permissive/113654920/hdl/Reg38.v
data/verilator_xmls/87f0a72d-6eb7-43a5-8a87-6bdce528bdbf.xml
module Reg38(
	input UDMAC		,
	input PS2WrIDE	,
	input iIRQ		,
	input cDQ		,
	input iDQ		,
	input iDK		,
	input BufEmpty		,
	input PB_HvSpace	,
	input [3:0] BufSize	,
	output [7:0] DOut		
);



wire [7:0] R381;
wire [7:0] W381;
wire WCond1;
wire WCond2,WCond2A,WCond2B1,WCond2B2;
wire WCond3;


wire Activity;

assign Activity	= cDQ | iIRQ | iDQ | iDK | BufSize[3] | BufSize[2] | BufSize[1] | BufSize[0];



assign R381[7]	= 1'b0;
assign R381[6] = ~Activity;
assign R381[5:4] = 2'b10;
assign R381[3:0] = BufSize[3:0];

assign W381[7:0] =
	(BufSize[3:0] == 4'b1000) ? 8'h20 :
	(BufSize[3:0] == 4'b0111) ? 8'h21 :
	(BufSize[3:0] == 4'b0110) ? 8'h22 :
	(BufSize[3:0] == 4'b0000) ? 8'h24 :
										 8'h23;






assign WCond1	= PS2WrIDE & ~(PB_HvSpace);
assign WCond2	= PS2WrIDE & ~(iDK);
assign WCond2A	= WCond2 & BufEmpty;
assign WCond2B1	= WCond2 & ~(BufEmpty) & UDMAC;
assign WCond2B2	= WCond2 & ~(BufEmpty) & ~(UDMAC);
assign WCond3	= PS2WrIDE & iDK;




assign DOut	=



	(PS2WrIDE == 1'b0) ? R381 :

	(WCond1	== 1'b1) ? 8'hA0 :

	(WCond2A	== 1'b1) ? 8'h50 :
	(WCond2B1 == 1'b1) ? 8'h22 :
	(WCond2B2 == 1'b1) ? 8'h21 :

	(WCond3	== 1'b1) ? W381 :


	8'hFF;


endmodule
module Reg38(
	input UDMAC		,
	input PS2WrIDE	,
	input iIRQ		,
	input cDQ		,
	input iDQ		,
	input iDK		,
	input BufEmpty		,
	input PB_HvSpace	,
	input [3:0] BufSize	,
	output [7:0] DOut		
);




wire [7:0] R381;
wire [7:0] W381;
wire WCond1;
wire WCond2,WCond2A,WCond2B1,WCond2B2;
wire WCond3;


wire Activity;

assign Activity	= cDQ | iIRQ | iDQ | iDK | BufSize[3] | BufSize[2] | BufSize[1] | BufSize[0];



assign R381[7]	= 1'b0;
assign R381[6] = ~Activity;
assign R381[5:4] = 2'b10;
assign R381[3:0] = BufSize[3:0];

assign W381[7:0] =
	(BufSize[3:0] == 4'b1000) ? 8'h20 :
	(BufSize[3:0] == 4'b0111) ? 8'h21 :
	(BufSize[3:0] == 4'b0110) ? 8'h22 :
	(BufSize[3:0] == 4'b0000) ? 8'h24 :
										 8'h23;






assign WCond1	= PS2WrIDE & ~(PB_HvSpace);
assign WCond2	= PS2WrIDE & ~(iDK);
assign WCond2A	= WCond2 & BufEmpty;
assign WCond2B1	= WCond2 & ~(BufEmpty) & UDMAC;
assign WCond2B2	= WCond2 & ~(BufEmpty) & ~(UDMAC);
assign WCond3	= PS2WrIDE & iDK;




assign DOut	=



	(PS2WrIDE == 1'b0) ? R381 :

	(WCond1	== 1'b1) ? 8'hA0 :

	(WCond2A	== 1'b1) ? 8'h50 :
	(WCond2B1 == 1'b1) ? 8'h22 :
	(WCond2B2 == 1'b1) ? 8'h21 :

	(WCond3	== 1'b1) ? W381 :


	8'hFF;


endmodule