data/full_repos/permissive/191834901/VerilogHDL/mainMemory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/191834901/VerilogHDL/mainMemory.v:20: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'instMemory\'\nmodule instMemory #(parameter instructionW=32, parameter addrW=16) (\n       ^~~~~~~~~~\n                                                                                  : ... Top module \'dataMemory\'\nmodule dataMemory #(parameter dataW=32, parameter addrW=16) (\n       ^~~~~~~~~~\n                                                                                  : ... Top module \'controlPathDriver\'\nmodule controlPathDriver #(parameter controlWordWidth=16, parameter caddrW=16) (\n       ^~~~~~~~~~~~~~~~~\n                                                                                  : ... Top module \'registerFile\'\nmodule registerFile #(parameter dataWidth=32, parameter addrWidth=5) (\n       ^~~~~~~~~~~~\n                                                                                  : ... Top module \'registerNx\'\nmodule registerNx #(parameter regWidth=8)(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module registerFile #(parameter dataWidth=32, parameter addrWidth=5) (
	output reg [(dataWidth-1):0] regDataA, regDataB,
	input  [(dataWidth-1):0] regDataD,
	input  [(addrWidth-1):0] addrA, addrB, addrD,
	input  regWEn, sysCLK
);

	reg [(dataWidth-1):0]regFile[((2**addrWidth)-1):0];


	initial begin
		$readmemh("C:/mem_register_file.txt", regFile);
	end

	always@(posedge sysCLK) begin
		regDataA <= regFile[addrA];
		regDataB <= regFile[addrB];
		if(regWEn && addrD != 0) begin
			regFile[addrD] <= regDataD;
		end
	end

endmodule
module registerFile #(parameter dataWidth=32, parameter addrWidth=5) (
	output reg [(dataWidth-1):0] regDataA, regDataB,
	input  [(dataWidth-1):0] regDataD,
	input  [(addrWidth-1):0] addrA, addrB, addrD,
	input  regWEn, sysCLK
);


	reg [(dataWidth-1):0]regFile[((2**addrWidth)-1):0];


	initial begin
		$readmemh("C:/mem_register_file.txt", regFile);
	end

	always@(posedge sysCLK) begin
		regDataA <= regFile[addrA];
		regDataB <= regFile[addrB];
		if(regWEn && addrD != 0) begin
			regFile[addrD] <= regDataD;
		end
	end

endmodule