data/full_repos/permissive/192147978/alu_control.v
data/verilator_xmls/8216d1a2-214b-4e06-abed-fe8a2d023939.xml
module alu_control(
    clk,
    reset,
    alu_op,
    instruction_5_0,
    alu_out
	);
    

    input [1:0] alu_op;
    input [5:0] instruction_5_0;
    input clk;
    input reset;

    output [3:0] alu_out;

    wire clk;
    wire reset;
    wire [1:0] alu_op;
    wire [5:0] instruction_5_0;

    reg [3:0] alu_out;

always @(posedge clk)
begin: alu_control
    

    case(alu_op)
   	 2'b00:
   	 begin
   		 alu_out = 4'b0010;
   	 end
   	 2'b01:
   	 begin
   		 alu_out = 4'b0110;
   	 end
   	 2'b10:
   	 begin
   		 case (instruction_5_0)
   			 6'b100000:
   			 begin
   				 alu_out = 4'b0010;
   			 end
   			 6'b100010:
   			 begin
   				 alu_out = 4'b0110;
   			 end
   			 6'b100100:
   			 begin
   				 alu_out = 4'b0000;
   			 end
   			 6'b100101:
   			 begin
   				 alu_out = 4'b0001;
   			 end
   			 6'b100111:
   			 begin
   				 alu_out = 4'b1100;
   			 end
   			 6'b101010:
   			 begin
   				 alu_out = 4'b0111;
   			 end
   			 default:
   			 begin
   				 alu_out = 4'b0000;
   			 end
   		 endcase
   	 end
   	 default:
   	 begin
   		 alu_out = 4'bxxxx;
   	 end
    endcase
   	 
end

endmodule
module alu_control(
    clk,
    reset,
    alu_op,
    instruction_5_0,
    alu_out
	);

    

    input [1:0] alu_op;
    input [5:0] instruction_5_0;
    input clk;
    input reset;

    output [3:0] alu_out;

    wire clk;
    wire reset;
    wire [1:0] alu_op;
    wire [5:0] instruction_5_0;

    reg [3:0] alu_out;

always @(posedge clk)
begin: alu_control
    

    case(alu_op)
   	 2'b00:
   	 begin
   		 alu_out = 4'b0010;
   	 end
   	 2'b01:
   	 begin
   		 alu_out = 4'b0110;
   	 end
   	 2'b10:
   	 begin
   		 case (instruction_5_0)
   			 6'b100000:
   			 begin
   				 alu_out = 4'b0010;
   			 end
   			 6'b100010:
   			 begin
   				 alu_out = 4'b0110;
   			 end
   			 6'b100100:
   			 begin
   				 alu_out = 4'b0000;
   			 end
   			 6'b100101:
   			 begin
   				 alu_out = 4'b0001;
   			 end
   			 6'b100111:
   			 begin
   				 alu_out = 4'b1100;
   			 end
   			 6'b101010:
   			 begin
   				 alu_out = 4'b0111;
   			 end
   			 default:
   			 begin
   				 alu_out = 4'b0000;
   			 end
   		 endcase
   	 end
   	 default:
   	 begin
   		 alu_out = 4'bxxxx;
   	 end
    endcase
   	 
end

endmodule