data/full_repos/permissive/121203026/virtex6/bf16x16/matlab/verilog_files/DesignProcessingElement.v
1: b'%Warning-WIDTH: data/full_repos/permissive/121203026/virtex6/bf16x16/matlab/verilog_files/DesignProcessingElement.v:14: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'wT\' generates 8 bits.\n                                                                                                                      : ... In instance PE\n  wire [20:0] new_distance = (dS+wT); \n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module PE(input [31:0]S,T, output [31:0] T_dash);

  
  
  
  wire [2:0]  pS = S[31:29];
  wire [7:0]  wS = S[28:21];          
  wire [20:0] dS = S[20: 0];          
    
  wire [2:0]  pT = T[31:29];
  wire [7:0]  wT = T[28:21];
  wire [20:0] dT = T[20: 0];
  
  wire [20:0] new_distance = (dS+wT); 
  wire update_true = new_distance < dT;
  
  wire [2:0 ] muxO_pT = update_true?      pS     : pT ;
  wire [20:0] muxO_dT = update_true? new_distance: dT ;

  
  wire [2:0]  pT_dash = muxO_pT;
  wire [7:0]  wT_dash = wT;
  wire [20:0] dT_dash = muxO_dT;
  
  assign T_dash={pT_dash, wT_dash, dT_dash};
  
endmodule
module PE(input [31:0]S,T, output [31:0] T_dash);


  
  
  
  wire [2:0]  pS = S[31:29];
  wire [7:0]  wS = S[28:21];          
  wire [20:0] dS = S[20: 0];          
    
  wire [2:0]  pT = T[31:29];
  wire [7:0]  wT = T[28:21];
  wire [20:0] dT = T[20: 0];
  
  wire [20:0] new_distance = (dS+wT); 
  wire update_true = new_distance < dT;
  
  wire [2:0 ] muxO_pT = update_true?      pS     : pT ;
  wire [20:0] muxO_dT = update_true? new_distance: dT ;

  
  wire [2:0]  pT_dash = muxO_pT;
  wire [7:0]  wT_dash = wT;
  wire [20:0] dT_dash = muxO_dT;
  
  assign T_dash={pT_dash, wT_dash, dT_dash};
  
endmodule