data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v
 line:153: before: "begin"
1: b'%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:88: syntax error, unexpected \'@\'\n      while(rx !== 1\'b1) @(rx);\n                         ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:91: syntax error, unexpected \'@\'\n        while(rx != 1\'b0) @(rx);\n                          ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:92: syntax error, unexpected \'@\'\n        repeat(8) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:94: syntax error, unexpected \'@\'\n           repeat(16) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:97: syntax error, unexpected \'@\'\n        repeat(16) @(posedge clk);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:112: Unsupported: Ignoring delay on this delayed statement.\n   initial #100\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:169: Unsupported: Ignoring delay on this delayed statement.\n         #1000000;\n         ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:171: Unsupported: wait statements\n         wait(gpio);\n         ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:172: Unsupported: Ignoring delay on this delayed statement.\n         if (uart_number == 1) #200000;\n                               ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:213: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:215: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:217: syntax error, unexpected \'@\'\n      repeat (3) @(posedge clk);\n                 ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:219: syntax error, unexpected \'@\'\n        @uart_tx_state;\n        ^\n%Error: Exiting due to 10 error(s), 3 warning(s)\n'
module raminfr_v(clk, we, a, dpra, di, dpo); 

parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;

input clk;   
input we;   
input  [addr_width-1:0] a;   
input  [addr_width-1:0] dpra;   
input  [data_width-1:0] di;   
output [data_width-1:0] dpo;   
reg    [data_width-1:0] ram [depth-1:0]; 

wire   [data_width-1:0] di;   
wire   [addr_width-1:0] a;   
wire   [addr_width-1:0] dpra;   
 
always @(posedge clk) begin
    if (we)   
      ram[a] <= di;   
end   
reg    [data_width-1:0] dpo;

always @(posedge clk)
    dpo <= ram[dpra];

endmodule
module raminfr_v(clk, we, a, dpra, di, dpo);
 

parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;

input clk;   
input we;   
input  [addr_width-1:0] a;   
input  [addr_width-1:0] dpra;   
input  [data_width-1:0] di;   
output [data_width-1:0] dpo;   
reg    [data_width-1:0] ram [depth-1:0]; 

wire   [data_width-1:0] di;   
wire   [addr_width-1:0] a;   
wire   [addr_width-1:0] dpra;   
 
always @(posedge clk) begin
    if (we)   
      ram[a] <= di;   
end   
reg    [data_width-1:0] dpo;

always @(posedge clk)
    dpo <= ram[dpra];

endmodule