data/full_repos/permissive/117026779/src/Motherboard.v
1: b'%Error: data/full_repos/permissive/117026779/src/Motherboard.v:187: Cannot find file containing module: \'Syncronizer\'\n Syncronizer #(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/Syncronizer\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/Syncronizer.v\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/Syncronizer.sv\n             Syncronizer\n             Syncronizer.v\n             Syncronizer.sv\n             obj_dir/Syncronizer\n             obj_dir/Syncronizer.v\n             obj_dir/Syncronizer.sv\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:199: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:208: Cannot find file containing module: \'ROM\'\nROM #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:217: Cannot find file containing module: \'MIPS\'\nMIPS mips(\n^~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:234: Cannot find file containing module: \'RAM\'\nRAM #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:250: Cannot find file containing module: \'DECODER\'\nDECODER #(.INPUT_WIDTH(3)) address_decoder\n^~~~~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:257: Cannot find file containing module: \'AND\'\nAND #(.WIDTH(3)) key_cs_and (\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:262: Cannot find file containing module: \'AND\'\nAND #(.WIDTH(3)) key_ready_cs_and (\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:267: Cannot find file containing module: \'AND\'\nAND #(.WIDTH(4)) vga_fifo_cs_and (\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:279: Cannot find file containing module: \'ASCII_Keyboard\'\nASCII_Keyboard keyboard(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:293: Cannot find file containing module: \'TRIBUFFER\'\nTRIBUFFER #(.WIDTH(32))\n^~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:302: Cannot find file containing module: \'TRIBUFFER\'\nTRIBUFFER #(.WIDTH(32))\n^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Motherboard.v:312: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 35 bits.\n                                                                          : ... In instance Motherboard\nwire [31:0] ControlBus      = { {(32-12){1\'b0}}, 3\'b0, BusCycle, 3\'b0, MemRead, 3\'b0, MemWrite };\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Motherboard.v:313: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n                                                                          : ... In instance Motherboard\nwire [31:0] KeyboardSignals = { 20\'b0, keyboard_ascii, scan_code, 3\'b0, keyboard_ready};\n                            ^\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:315: Cannot find file containing module: \'FIFO\'\nFIFO #(\n^~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:332: Cannot find file containing module: \'FIFO\'\nFIFO #(\n^~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:349: Cannot find file containing module: \'OR\'\nOR #(.WIDTH(2)) fifo_to_vga_cs_and (\n^~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:354: Cannot find file containing module: \'VGA_Terminal\'\nVGA_Terminal vga_term(\n^~~~~~~~~~~~\n%Error: Exiting due to 16 error(s), 2 warning(s)\n'
module ONESHOT(
    input wire clk,
    input wire rst,
    input wire signal,
    output reg out
);

reg previously_high;

always @(posedge clk or posedge rst)
begin
    if(rst)
    begin
        out <= 0;
        previously_high <= 0;
    end
    else
    begin
        if(signal && !previously_high)
        begin
            out <= 1;
            previously_high <= 1;
        end
        else if(signal && previously_high)
        begin
            out <= 0;
            previously_high <= 1;
        end
        else
        begin
            out <= 0;
            previously_high <= 0;
        end
    end
end

endmodule
module ONESHOT(
    input wire clk,
    input wire rst,
    input wire signal,
    output reg out
);


reg previously_high;

always @(posedge clk or posedge rst)
begin
    if(rst)
    begin
        out <= 0;
        previously_high <= 0;
    end
    else
    begin
        if(signal && !previously_high)
        begin
            out <= 1;
            previously_high <= 1;
        end
        else if(signal && previously_high)
        begin
            out <= 0;
            previously_high <= 1;
        end
        else
        begin
            out <= 0;
            previously_high <= 0;
        end
    end
end

endmodule