data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:63: Cannot find include file: ./ccs0001_header.v\n`include "./ccs0001_header.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169225814/modules/crypto_lib/verif,data/full_repos/permissive/169225814/./ccs0001_header.v\n             data/full_repos/permissive/169225814/modules/crypto_lib/verif,data/full_repos/permissive/169225814/./ccs0001_header.v.v\n             data/full_repos/permissive/169225814/modules/crypto_lib/verif,data/full_repos/permissive/169225814/./ccs0001_header.v.sv\n             ./ccs0001_header.v\n             ./ccs0001_header.v.v\n             ./ccs0001_header.v.sv\n             obj_dir/./ccs0001_header.v\n             obj_dir/./ccs0001_header.v.v\n             obj_dir/./ccs0001_header.v.sv\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:66: Cannot find include file: ./ccs0001_tasks.v\n`include "./ccs0001_tasks.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:114: Cannot find include file: ./hex/test.hex\n`include "./hex/test.hex" \n         ^~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2) CLK = ~CLK; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #(UART_BAUD/2) UART_CLK = ~UART_CLK; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n#0 nPORESET  = 1\'b1;\n^\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:96: syntax error, unexpected \'@\'\n    @(posedge CLK);\n    ^\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:98: Unsupported: Verilog 1995 force\nforce ccs0001_tb.u_dut_inst.u_chip_core_inst.u_gpcfg_inst.gpcfg17_reg = 32\'h9;\n^~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:105: syntax error, unexpected \'@\'\n    @(posedge CLK);\n    ^\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:111: syntax error, unexpected \'@\'\n    @(posedge UART_CLK);\n    ^\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:118: syntax error, unexpected \'@\'\n    @(posedge UART_CLK);\n    ^\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:176: Unsupported: Verilog 1995 force\nforce ccs0001_tb.pad_ctl_3  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[3][0];\n^~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:177: Unsupported: Verilog 1995 force\nforce ccs0001_tb.pad_ctl_4  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[4][0];\n^~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:178: Unsupported: Verilog 1995 force\nforce ccs0001_tb.pad_ctl_5  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[5][0];\n^~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:179: Unsupported: Verilog 1995 force\nforce ccs0001_tb.pad_ctl_6  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[6][0];\n^~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:180: Unsupported: Verilog 1995 force\nforce ccs0001_tb.pad_ctl_7  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[7][0];\n^~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:181: Unsupported: Verilog 1995 force\nforce ccs0001_tb.pad_ctl_8  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[8][0];\n^~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:182: Unsupported: Verilog 1995 force\nforce ccs0001_tb.pad_ctl_9  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[9][0];\n^~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/verif/ccs0001_tb.v:183: Unsupported: Verilog 1995 force\nforce ccs0001_tb.pad_ctl_10 = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[10][0];\n^~~~~\n%Error: Exiting due to 16 error(s), 3 warning(s)\n'
module ccs0001_tb (
);





localparam  CLK_PERIOD   = 4.167;
localparam  UART_BAUD    = 41.67;

localparam  NUM_PADS     = 11;
localparam  PAD_CTL_W    = 4;

wire [NUM_PADS-1  :0] pad;
wire [NUM_PADS-1  :0] pad_in;
wire [NUM_PADS-1  :0] pad_out;
wire [PAD_CTL_W-1 :0] pad_ctl[NUM_PADS-1 :0];

reg     CLK; 
reg     nPORESET; 
reg     nRESET; 

reg       UART_CLK; 
reg [9:0] tx_reg = 10'h3FF; 
reg [7:0] rx_reg; 
wire uartm_rx_data;

integer no_of_clocks; 

reg [31:0] mem [0:16383];



`include "./ccs0001_header.v"


`include "./ccs0001_tasks.v"


`define ARM_UD_MODEL;







initial begin
  CLK      = 1'b0; 
  UART_CLK = 1'b0; 
end

always begin
  #(CLK_PERIOD/2) CLK = ~CLK; 
end

always begin
  #(UART_BAUD/2) UART_CLK = ~UART_CLK; 
end


initial begin

#0 nPORESET  = 1'b1;
   nRESET    = 1'b1;
  repeat (10) begin
    @(posedge CLK);
  end
force ccs0001_tb.u_dut_inst.u_chip_core_inst.u_gpcfg_inst.gpcfg17_reg = 32'h9;

   nPORESET  = 1'b0;
   nRESET    = 1'b0;


  repeat (20) begin
    @(posedge CLK);
  end

  nPORESET = 1'b1;

  repeat (25) begin
    @(posedge UART_CLK);
  end

`include "./hex/test.hex"

`ifdef RELEASE_M0_RESET
  repeat (10) begin
    @(posedge UART_CLK);
  end

  nRESET   = 1'b1;
`endif

end






ccs0001 u_dut_inst 
  (
  .pad  (pad),
  .VDD  (1'b1),
  .DVDD (1'b1),
  .VSS  (1'b0),
  .DVSS (1'b0)
  );

















assign pad_in[0]  = nPORESET;
assign pad_ctl[0] = 4'h3;

assign pad_in[1]  = nRESET;
assign pad_ctl[1] = 4'h3;

assign pad_in[2]  = CLK;
assign pad_ctl[2] = 4'h3;


wire pad_ctl_3;
wire pad_ctl_4;
wire pad_ctl_5;
wire pad_ctl_6;
wire pad_ctl_7;
wire pad_ctl_8;
wire pad_ctl_9;
wire pad_ctl_10;

initial begin
force ccs0001_tb.pad_ctl_3  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[3][0];
force ccs0001_tb.pad_ctl_4  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[4][0];
force ccs0001_tb.pad_ctl_5  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[5][0];
force ccs0001_tb.pad_ctl_6  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[6][0];
force ccs0001_tb.pad_ctl_7  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[7][0];
force ccs0001_tb.pad_ctl_8  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[8][0];
force ccs0001_tb.pad_ctl_9  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[9][0];
force ccs0001_tb.pad_ctl_10 = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[10][0];
end

assign pad_in[3]  = 1'b0;
assign pad_ctl[3] = {3'b001,pad_ctl_3};
assign uartm_rx_data = pad_out[3];

assign pad_in[4]  = tx_reg[0];
assign pad_ctl[4] = {3'b001,pad_ctl_4};

assign pad_in[5]  = 1'b0;
assign pad_ctl[5] = {3'b001,pad_ctl_5};

assign pad_in[6]  = 1'b1;
assign pad_ctl[6] = {3'b001,pad_ctl_6};

assign pad_in[7]  = 1'b0;
assign pad_ctl[7] = {3'b001,pad_ctl_7};

assign pad_in[8]  = 1'b0;
assign pad_ctl[8] = {3'b001,pad_ctl_8};

assign pad_in[9]  = 1'b0;
assign pad_ctl[9] = {3'b001,pad_ctl_9};

assign pad_in[10]  = 1'b0;
assign pad_ctl[10] = {3'b001,pad_ctl_10};

padring_tb #(
  .NUM_PADS  (NUM_PADS),
  .PAD_CTL_W (PAD_CTL_W) )
  u_padring_tb_inst (
  .pad       (pad),
  .pad_in    (pad_in),
  .pad_out   (pad_out),
  .pad_ctl   (pad_ctl)
);




initial begin
  no_of_clocks = 0; 
end
always@(posedge CLK)  begin
  no_of_clocks = no_of_clocks +1 ; 








end

endmodule
module ccs0001_tb (
);






localparam  CLK_PERIOD   = 4.167;
localparam  UART_BAUD    = 41.67;

localparam  NUM_PADS     = 11;
localparam  PAD_CTL_W    = 4;

wire [NUM_PADS-1  :0] pad;
wire [NUM_PADS-1  :0] pad_in;
wire [NUM_PADS-1  :0] pad_out;
wire [PAD_CTL_W-1 :0] pad_ctl[NUM_PADS-1 :0];

reg     CLK; 
reg     nPORESET; 
reg     nRESET; 

reg       UART_CLK; 
reg [9:0] tx_reg = 10'h3FF; 
reg [7:0] rx_reg; 
wire uartm_rx_data;

integer no_of_clocks; 

reg [31:0] mem [0:16383];



`include "./ccs0001_header.v"


`include "./ccs0001_tasks.v"


`define ARM_UD_MODEL;







initial begin
  CLK      = 1'b0; 
  UART_CLK = 1'b0; 
end

always begin
  #(CLK_PERIOD/2) CLK = ~CLK; 
end

always begin
  #(UART_BAUD/2) UART_CLK = ~UART_CLK; 
end


initial begin

#0 nPORESET  = 1'b1;
   nRESET    = 1'b1;
  repeat (10) begin
    @(posedge CLK);
  end
force ccs0001_tb.u_dut_inst.u_chip_core_inst.u_gpcfg_inst.gpcfg17_reg = 32'h9;

   nPORESET  = 1'b0;
   nRESET    = 1'b0;


  repeat (20) begin
    @(posedge CLK);
  end

  nPORESET = 1'b1;

  repeat (25) begin
    @(posedge UART_CLK);
  end

`include "./hex/test.hex"

`ifdef RELEASE_M0_RESET
  repeat (10) begin
    @(posedge UART_CLK);
  end

  nRESET   = 1'b1;
`endif

end






ccs0001 u_dut_inst 
  (
  .pad  (pad),
  .VDD  (1'b1),
  .DVDD (1'b1),
  .VSS  (1'b0),
  .DVSS (1'b0)
  );

















assign pad_in[0]  = nPORESET;
assign pad_ctl[0] = 4'h3;

assign pad_in[1]  = nRESET;
assign pad_ctl[1] = 4'h3;

assign pad_in[2]  = CLK;
assign pad_ctl[2] = 4'h3;


wire pad_ctl_3;
wire pad_ctl_4;
wire pad_ctl_5;
wire pad_ctl_6;
wire pad_ctl_7;
wire pad_ctl_8;
wire pad_ctl_9;
wire pad_ctl_10;

initial begin
force ccs0001_tb.pad_ctl_3  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[3][0];
force ccs0001_tb.pad_ctl_4  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[4][0];
force ccs0001_tb.pad_ctl_5  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[5][0];
force ccs0001_tb.pad_ctl_6  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[6][0];
force ccs0001_tb.pad_ctl_7  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[7][0];
force ccs0001_tb.pad_ctl_8  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[8][0];
force ccs0001_tb.pad_ctl_9  = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[9][0];
force ccs0001_tb.pad_ctl_10 = ccs0001_tb.u_dut_inst.u_padring_inst.pad_ctl[10][0];
end

assign pad_in[3]  = 1'b0;
assign pad_ctl[3] = {3'b001,pad_ctl_3};
assign uartm_rx_data = pad_out[3];

assign pad_in[4]  = tx_reg[0];
assign pad_ctl[4] = {3'b001,pad_ctl_4};

assign pad_in[5]  = 1'b0;
assign pad_ctl[5] = {3'b001,pad_ctl_5};

assign pad_in[6]  = 1'b1;
assign pad_ctl[6] = {3'b001,pad_ctl_6};

assign pad_in[7]  = 1'b0;
assign pad_ctl[7] = {3'b001,pad_ctl_7};

assign pad_in[8]  = 1'b0;
assign pad_ctl[8] = {3'b001,pad_ctl_8};

assign pad_in[9]  = 1'b0;
assign pad_ctl[9] = {3'b001,pad_ctl_9};

assign pad_in[10]  = 1'b0;
assign pad_ctl[10] = {3'b001,pad_ctl_10};

padring_tb #(
  .NUM_PADS  (NUM_PADS),
  .PAD_CTL_W (PAD_CTL_W) )
  u_padring_tb_inst (
  .pad       (pad),
  .pad_in    (pad_in),
  .pad_out   (pad_out),
  .pad_ctl   (pad_ctl)
);




initial begin
  no_of_clocks = 0; 
end
always@(posedge CLK)  begin
  no_of_clocks = no_of_clocks +1 ; 








end

endmodule