data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v
 line:34: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #8\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n            #4 c_in = c_in + 1;\n            ^\n%Error: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:57: Unsupported or unknown PLI call: $monitor\n        $monitor("Time:\\t%g, x: %b, y: %b, c_in %b, z_b: %b, z_s: %b, c_out_b: %b, c_out_s: %b",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:71: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/09_full_adder/simulation/testbench.v:72: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1);   \n        ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

   reg  c_in;
   reg  x, y;
   wire z_behavioral, z_structural;
   wire c_out_behavioral, c_out_structural;
 

    full_adder full_adder_behavioral_dut(
        .carry_in ( c_in             ),
        .x        ( x                ),
        .y        ( y                ),
        .z        ( z_behavioral     ),
        .carry_out( c_out_behavioral )
    );
    
    full_adder_structural full_adder_structural_dut(
        .carry_in ( c_in             ),
        .x        ( x                ),
        .y        ( y                ),
        .z        ( z_structural     ),
        .carry_out( c_out_structural )
    );
    

    initial begin
        x    = 1'b0;
        y    = 1'b0;
        c_in = 1'b0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            if( x == 1'b1 ) begin
                x = 1'b0;
                y = y + 1;
            end
            else begin
                x = x + 1;
            end
        end
        
    initial
        forever begin
            #4 c_in = c_in + 1;
        end
    


    initial 
        $monitor("Time:\t%g, x: %b, y: %b, c_in %b, z_b: %b, z_s: %b, c_out_b: %b, c_out_s: %b",
                $time,
                x,
                y,
                c_in,
                z_behavioral,
                z_structural,
                c_out_behavioral,
                c_out_structural
            );
            


    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);
    end
    
endmodule
module testbench;


   reg  c_in;
   reg  x, y;
   wire z_behavioral, z_structural;
   wire c_out_behavioral, c_out_structural;
 

    full_adder full_adder_behavioral_dut(
        .carry_in ( c_in             ),
        .x        ( x                ),
        .y        ( y                ),
        .z        ( z_behavioral     ),
        .carry_out( c_out_behavioral )
    );
    
    full_adder_structural full_adder_structural_dut(
        .carry_in ( c_in             ),
        .x        ( x                ),
        .y        ( y                ),
        .z        ( z_structural     ),
        .carry_out( c_out_structural )
    );
    

    initial begin
        x    = 1'b0;
        y    = 1'b0;
        c_in = 1'b0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            if( x == 1'b1 ) begin
                x = 1'b0;
                y = y + 1;
            end
            else begin
                x = x + 1;
            end
        end
        
    initial
        forever begin
            #4 c_in = c_in + 1;
        end
    


    initial 
        $monitor("Time:\t%g, x: %b, y: %b, c_in %b, z_b: %b, z_s: %b, c_out_b: %b, c_out_s: %b",
                $time,
                x,
                y,
                c_in,
                z_behavioral,
                z_structural,
                c_out_behavioral,
                c_out_structural
            );
            


    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);
    end
    
endmodule