data/full_repos/permissive/206302844/davis_240.v
data/verilator_xmls/90daf25d-b295-43d1-ac81-14e0122d52be.xml
module davis_240(
input wire clk,
input wire[8:0]AER_bus,
input wire REQ,
input wire SEL,
output wire ACK,
output reg [31:0]data_out,
output reg [31:0]data_out_time     
    );
/
    data_out[7:0] <= Y_addr;
    data_out[16:8] <= X_addr_p;
    data_out[31:17] <= 0;
    data_out_time[31:0] <= time_register;

end

endmodule
module davis_240(
input wire clk,
input wire[8:0]AER_bus,
input wire REQ,
input wire SEL,
output wire ACK,
output reg [31:0]data_out,
output reg [31:0]data_out_time     
    );

/
    data_out[7:0] <= Y_addr;
    data_out[16:8] <= X_addr_p;
    data_out[31:17] <= 0;
    data_out_time[31:0] <= time_register;

end

endmodule