data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/check_4.v
 line:63: before: "or"
1: b'%Error: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/check_4.v:24: Cannot find file containing module: \'alu_14\'\n  alu_14 alu (\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/alu_14\n             data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/alu_14.v\n             data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/alu_14.sv\n             alu_14\n             alu_14.v\n             alu_14.sv\n             obj_dir/alu_14\n             obj_dir/alu_14.v\n             obj_dir/alu_14.sv\n%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/check_4.v:48: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                : ... In instance check_4\n    for (i = 1\'h0; i < 5\'h10; i = i + 1) begin\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/check_4.v:49: Operator SUB expects 32 bits on the LHS, but LHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                                                                                                : ... In instance check_4\n      msb[(4\'hf - i)*1+0-:1] = cols[(i)*14+13+0-:1];\n                ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module check_4 (
    input clk,
    input rst,
    input [223:0] cols,
    input [31:0] rows,
    output reg [0:0] changescore
  );
  
  
  
  wire [16-1:0] M_alu_out;
  wire [1-1:0] M_alu_z;
  wire [1-1:0] M_alu_v;
  wire [1-1:0] M_alu_n;
  reg [16-1:0] M_alu_a;
  reg [16-1:0] M_alu_b;
  reg [6-1:0] M_alu_alufn;
  alu_14 alu (
    .a(M_alu_a),
    .b(M_alu_b),
    .alufn(M_alu_alufn),
    .out(M_alu_out),
    .z(M_alu_z),
    .v(M_alu_v),
    .n(M_alu_n)
  );
  
  localparam AND = 6'h18;
  
  localparam ADD = 6'h00;
  
  reg [15:0] msb;
  
  reg [15:0] tempcheck;
  
  reg z;
  
  integer i;
  
  always @* begin
    changescore = 1'h0;
    for (i = 1'h0; i < 5'h10; i = i + 1) begin
      msb[(4'hf - i)*1+0-:1] = cols[(i)*14+13+0-:1];
    end
    M_alu_a = msb;
    M_alu_b = rows[16+15-:16];
    M_alu_alufn = 6'h18;
    tempcheck = M_alu_out;
    z = tempcheck[0+0-:1] + tempcheck[1+0-:1] + tempcheck[2+0-:1] + tempcheck[3+0-:1] + tempcheck[4+0-:1] + tempcheck[5+0-:1] + tempcheck[6+0-:1] + tempcheck[7+0-:1] + tempcheck[8+0-:1] + tempcheck[9+0-:1] + tempcheck[10+0-:1] + tempcheck[11+0-:1] + tempcheck[12+0-:1] + tempcheck[13+0-:1] + tempcheck[14+0-:1] + tempcheck[15+0-:1];
    if (z > 1'h0) begin
      changescore = 1'h1;
    end else begin
      changescore = 1'h0;
    end
  end
endmodule
module check_4 (
    input clk,
    input rst,
    input [223:0] cols,
    input [31:0] rows,
    output reg [0:0] changescore
  );

  
  
  
  wire [16-1:0] M_alu_out;
  wire [1-1:0] M_alu_z;
  wire [1-1:0] M_alu_v;
  wire [1-1:0] M_alu_n;
  reg [16-1:0] M_alu_a;
  reg [16-1:0] M_alu_b;
  reg [6-1:0] M_alu_alufn;
  alu_14 alu (
    .a(M_alu_a),
    .b(M_alu_b),
    .alufn(M_alu_alufn),
    .out(M_alu_out),
    .z(M_alu_z),
    .v(M_alu_v),
    .n(M_alu_n)
  );
  
  localparam AND = 6'h18;
  
  localparam ADD = 6'h00;
  
  reg [15:0] msb;
  
  reg [15:0] tempcheck;
  
  reg z;
  
  integer i;
  
  always @* begin
    changescore = 1'h0;
    for (i = 1'h0; i < 5'h10; i = i + 1) begin
      msb[(4'hf - i)*1+0-:1] = cols[(i)*14+13+0-:1];
    end
    M_alu_a = msb;
    M_alu_b = rows[16+15-:16];
    M_alu_alufn = 6'h18;
    tempcheck = M_alu_out;
    z = tempcheck[0+0-:1] + tempcheck[1+0-:1] + tempcheck[2+0-:1] + tempcheck[3+0-:1] + tempcheck[4+0-:1] + tempcheck[5+0-:1] + tempcheck[6+0-:1] + tempcheck[7+0-:1] + tempcheck[8+0-:1] + tempcheck[9+0-:1] + tempcheck[10+0-:1] + tempcheck[11+0-:1] + tempcheck[12+0-:1] + tempcheck[13+0-:1] + tempcheck[14+0-:1] + tempcheck[15+0-:1];
    if (z > 1'h0) begin
      changescore = 1'h1;
    end else begin
      changescore = 1'h0;
    end
  end
endmodule