data/full_repos/permissive/144334019/Test_system.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/144334019/Test_system.v:48: Unsupported: Ignoring delay on this delayed statement.\n always begin #50 clk = ~clk; end\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/144334019/Test_system.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/Test_system.v:60: Unsupported: Ignoring delay on this delayed statement.\n  sw = 1; #550 sw = 2; #550 sw = 3; \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/144334019/Test_system.v:60: Unsupported: Ignoring delay on this delayed statement.\n  sw = 1; #550 sw = 2; #550 sw = 3; \n                       ^\n%Error: data/full_repos/permissive/144334019/Test_system.v:39: Cannot find file containing module: \'vga_test\'\n vga_test uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/144334019,data/full_repos/permissive/144334019/vga_test\n             data/full_repos/permissive/144334019,data/full_repos/permissive/144334019/vga_test.v\n             data/full_repos/permissive/144334019,data/full_repos/permissive/144334019/vga_test.sv\n             vga_test\n             vga_test.v\n             vga_test.sv\n             obj_dir/vga_test\n             obj_dir/vga_test.v\n             obj_dir/vga_test.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_system;


	reg clk;
	reg reset;
	reg [7:0] sw;


	wire hsync;
	wire vsync;
	wire [7:0] rgb;
	wire [7:0] led;


	vga_test uut (
		.clk(clk), 
		.reset(reset), 
		.sw(sw), 
		.hsync(hsync), 
		.vsync(vsync), 
		.rgb(rgb), 
		.led(led)
	);
	always begin #50 clk = ~clk; end
	initial begin

		clk = 0;
		reset = 1;
		sw = 1;


		#100;
		reset = 0;
        

		sw = 1; #550 sw = 2; #550 sw = 3; 
	end
      
endmodule
module Test_system;



	reg clk;
	reg reset;
	reg [7:0] sw;


	wire hsync;
	wire vsync;
	wire [7:0] rgb;
	wire [7:0] led;


	vga_test uut (
		.clk(clk), 
		.reset(reset), 
		.sw(sw), 
		.hsync(hsync), 
		.vsync(vsync), 
		.rgb(rgb), 
		.led(led)
	);
	always begin #50 clk = ~clk; end
	initial begin

		clk = 0;
		reset = 1;
		sw = 1;


		#100;
		reset = 0;
        

		sw = 1; #550 sw = 2; #550 sw = 3; 
	end
      
endmodule