data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/data_cache.v
1: b'%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/data_cache.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/data_cache.v:32: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] addr,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/data_cache.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] addr,  \n                    ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/data_cache.v:37: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] write,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/data_cache.v:38: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] read\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/data_cache.v:44: syntax error, unexpected always\n    always @*\n    ^~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/data_cache.v:68: Define or directive not defined: \'`MEM_WRITE\'\n                if (rw == `MEM_WRITE)\n                          ^~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module data_cache#(
    parameter DATA_WIDTH = 32,
    parameter DATA_PER_BYTE_WIDTH = 2
)(
    input clk,
    input rst_n,


    input [`DATA_BUS] addr,
    input enable,
    input rw,
    

    input [`DATA_BUS] write,
    output reg [`DATA_BUS] read
    );
    
    reg [7:0] dat[0:127];
    integer i;
    
    always @*
    begin
        if (enable)
        begin
            read[31:24] <= dat[addr    ];
            read[23:16] <= dat[addr + 1];
            read[15: 8] <= dat[addr + 2];
            read[ 7: 0] <= dat[addr + 3];
        end
        else
            read <= 'bZZZZZZZZ;
    end
    
    always @(negedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            for (i = 0; i < 128; i = i + 1)
                dat[i] <= 0;
        end
        else
        begin
            if (enable)
            begin
                if (rw == `MEM_WRITE)
                begin
                    dat[addr    ] <= write[31:24];
                    dat[addr + 1] <= write[23:16];
                    dat[addr + 2] <= write[15: 8];
                    dat[addr + 3] <= write[ 7: 0];
                end
            end
        end
    end
endmodule
module data_cache#(
    parameter DATA_WIDTH = 32,
    parameter DATA_PER_BYTE_WIDTH = 2
)(
    input clk,
    input rst_n,


    input [`DATA_BUS] addr,
    input enable,
    input rw,
    

    input [`DATA_BUS] write,
    output reg [`DATA_BUS] read
    );

    
    reg [7:0] dat[0:127];
    integer i;
    
    always @*
    begin
        if (enable)
        begin
            read[31:24] <= dat[addr    ];
            read[23:16] <= dat[addr + 1];
            read[15: 8] <= dat[addr + 2];
            read[ 7: 0] <= dat[addr + 3];
        end
        else
            read <= 'bZZZZZZZZ;
    end
    
    always @(negedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            for (i = 0; i < 128; i = i + 1)
                dat[i] <= 0;
        end
        else
        begin
            if (enable)
            begin
                if (rw == `MEM_WRITE)
                begin
                    dat[addr    ] <= write[31:24];
                    dat[addr + 1] <= write[23:16];
                    dat[addr + 2] <= write[15: 8];
                    dat[addr + 3] <= write[ 7: 0];
                end
            end
        end
    end
endmodule