data/full_repos/permissive/106966316/controlALU_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;   \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/controlALU_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/106966316/controlALU_tb.v:29: Cannot find file containing module: \'controlALU\'\n controlALU uut(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/controlALU\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/controlALU.v\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/controlALU.sv\n             controlALU\n             controlALU.v\n             controlALU.sv\n             obj_dir/controlALU\n             obj_dir/controlALU.v\n             obj_dir/controlALU.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module controlALU_tb();
    reg [1:0]ALUop;
    reg [5:0]instru;
    reg clk;
    wire [2:0] contALU;
    
 controlALU uut(
 		.ALUop(ALUop),
		.instru(instru),
		.clk(clk),
		.contALU(contALU)
 );
	always begin

		clk=1'b1;
		#50;
		clk=1'b0;
		#50;

		end

initial begin
	ALUop=2'b00;
	instru=6'bx1x_x1x;
	#100;
	ALUop=2'b00;
	instru=6'b001_101;
	#100;
	ALUop=2'b01;
	instru=6'b111_001;
	#100;
    ALUop=2'b10;
    instru=6'b100000;
    #100;
    ALUop=2'b10;
    instru=6'b100010;
    #100;
    ALUop=2'b10;
    instru=6'b100100;
	#100;
    ALUop=2'b10;
    instru=6'b100101;
	#100;
    ALUop=2'b10;
    instru=6'b101010;
	#100;
    ALUop=2'b11;
    instru=6'b111111;

end
endmodule
module controlALU_tb();

    reg [1:0]ALUop;
    reg [5:0]instru;
    reg clk;
    wire [2:0] contALU;
    
 controlALU uut(
 		.ALUop(ALUop),
		.instru(instru),
		.clk(clk),
		.contALU(contALU)
 );
	always begin

		clk=1'b1;
		#50;
		clk=1'b0;
		#50;

		end

initial begin
	ALUop=2'b00;
	instru=6'bx1x_x1x;
	#100;
	ALUop=2'b00;
	instru=6'b001_101;
	#100;
	ALUop=2'b01;
	instru=6'b111_001;
	#100;
    ALUop=2'b10;
    instru=6'b100000;
    #100;
    ALUop=2'b10;
    instru=6'b100010;
    #100;
    ALUop=2'b10;
    instru=6'b100100;
	#100;
    ALUop=2'b10;
    instru=6'b100101;
	#100;
    ALUop=2'b10;
    instru=6'b101010;
	#100;
    ALUop=2'b11;
    instru=6'b111111;

end
endmodule