data/full_repos/permissive/106408053/verilog/async_fifo.v
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1: b'%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:175: Cannot find include file: gray.v\n`include "gray.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.v\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.sv\n             gray.v\n             gray.v.v\n             gray.v.sv\n             obj_dir/gray.v\n             obj_dir/gray.v.v\n             obj_dir/gray.v.sv\n%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:306: Cannot find include file: gray.v\n`include "gray.v" \n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:253: Unsupported: Ignoring delay on this delayed statement.\n          #1; \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:266: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:353: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:387: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n'
module async_fifo_ram (wrclk, rdclk, wrenb, wrptr, wrdata, rdenb, rdptr, rddata);

parameter ASYNC_FIFO_MAXINDEX = 4;
parameter ASYNC_FIFO_MAXDATA = 31;

input wrclk, rdclk;
input wrenb, rdenb;
input [ASYNC_FIFO_MAXINDEX:0] wrptr, rdptr;
input [ASYNC_FIFO_MAXDATA:0] wrdata;
output [ASYNC_FIFO_MAXDATA:0] rddata;

wire #1 dly_wrenb = wrenb;
wire [ASYNC_FIFO_MAXINDEX:0] #1 dly_wrptr = wrptr;
wire [ASYNC_FIFO_MAXDATA:0] #1 dly_wrdata = wrdata;

wire #1 dly_rdenb = rdenb;
wire [ASYNC_FIFO_MAXINDEX:0] #1 dly_rdptr = rdptr;

reg [ASYNC_FIFO_MAXDATA:0] mem[0:(1<<(ASYNC_FIFO_MAXINDEX+1))-1];
reg [ASYNC_FIFO_MAXINDEX:0] rdptr_reg;
assign rddata = mem[rdptr_reg];

always @ (posedge wrclk)
begin
  if (dly_wrenb) mem[dly_wrptr] = dly_wrdata;
end
always @ (posedge rdclk)
begin
  rdptr_reg = dly_rdptr;
end
endmodule
module async_fifo_ram (wrclk, rdclk, wrenb, wrptr, wrdata, rdenb, rdptr, rddata);


parameter ASYNC_FIFO_MAXINDEX = 4;
parameter ASYNC_FIFO_MAXDATA = 31;

input wrclk, rdclk;
input wrenb, rdenb;
input [ASYNC_FIFO_MAXINDEX:0] wrptr, rdptr;
input [ASYNC_FIFO_MAXDATA:0] wrdata;
output [ASYNC_FIFO_MAXDATA:0] rddata;

wire #1 dly_wrenb = wrenb;
wire [ASYNC_FIFO_MAXINDEX:0] #1 dly_wrptr = wrptr;
wire [ASYNC_FIFO_MAXDATA:0] #1 dly_wrdata = wrdata;

wire #1 dly_rdenb = rdenb;
wire [ASYNC_FIFO_MAXINDEX:0] #1 dly_rdptr = rdptr;

reg [ASYNC_FIFO_MAXDATA:0] mem[0:(1<<(ASYNC_FIFO_MAXINDEX+1))-1];
reg [ASYNC_FIFO_MAXINDEX:0] rdptr_reg;
assign rddata = mem[rdptr_reg];

always @ (posedge wrclk)
begin
  if (dly_wrenb) mem[dly_wrptr] = dly_wrdata;
end
always @ (posedge rdclk)
begin
  rdptr_reg = dly_rdptr;
end
endmodule