data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v
1: b"%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:43: Cannot find file containing module: 'NOR2A'\n    NOR2A \\Dataout_pad_RNO_0[2]  (.A(\\DataIn_c[1] ), .B(\\DataIn_c[0] ), \n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1,data/full_repos/permissive/165160692/NOR2A\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1,data/full_repos/permissive/165160692/NOR2A.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1,data/full_repos/permissive/165160692/NOR2A.sv\n             NOR2A\n             NOR2A.v\n             NOR2A.sv\n             obj_dir/NOR2A\n             obj_dir/NOR2A.v\n             obj_dir/NOR2A.sv\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:45: Cannot find file containing module: 'OA1C'\n    OA1C \\Dataout_pad_RNO[2]  (.A(\\_l2.Dataout30_0 ), .B(\\DataIn_c[2] )\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:47: Cannot find file containing module: 'OR2'\n    OR2 \\Dataout_pad_RNO_0[0]  (.A(\\DataIn_c[0] ), .B(\\DataIn_c[1] ), \n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:49: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Dataout_pad[0]/U0/U1  (.D(\\Dataout_c[0] ), .E(VCC), \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:52: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\DataIn_pad[1]/U0/U0  (.PAD(DataIn[1]), .Y(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:54: Cannot find file containing module: 'OR2A'\n    OR2A \\Dataout_pad_RNO_0[4]  (.A(\\DataIn_c[2] ), .B(\\DataIn_c[0] ), \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:56: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\G2BN_pad/U0/U1  (.YIN(\\G2BN_pad/U0/NET1 ), .Y(G2BN_c));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:57: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Dataout_pad[7]/U0/U1  (.D(\\Dataout_c[7] ), .E(VCC), \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:60: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Dataout_pad[6]/U0/U0  (.D(\\Dataout_pad[6]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:62: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Dataout_pad[1]/U0/U1  (.D(\\Dataout_c[1] ), .E(VCC), \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:65: Cannot find file containing module: 'OR2B'\n    OR2B \\Dataout_pad_RNO_0[5]  (.A(\\DataIn_c[0] ), .B(\\DataIn_c[2] ), \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:67: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Dataout_pad[5]/U0/U1  (.D(\\Dataout_c[5] ), .E(VCC), \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:70: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\G2AN_pad/U0/U1  (.YIN(\\G2AN_pad/U0/NET1 ), .Y(G2AN_c));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:71: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Dataout_pad[2]/U0/U0  (.D(\\Dataout_pad[2]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:73: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Dataout_pad[4]/U0/U1  (.D(\\Dataout_c[4] ), .E(VCC), \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:76: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Dataout_pad[3]/U0/U0  (.D(\\Dataout_pad[3]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:78: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\DataIn_pad[1]/U0/U1  (.YIN(\\DataIn_pad[1]/U0/NET1 ), .Y(\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:80: Cannot find file containing module: 'OA1B'\n    OA1B \\Dataout_pad_RNO[5]  (.A(\\DataIn_c[1] ), .B(\\_l5.Dataout57_0 )\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:82: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\G1_pad/U0/U1  (.YIN(\\G1_pad/U0/NET1 ), .Y(G1_c));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:83: Cannot find file containing module: 'AOI1'\n    AOI1 \\Dataout_pad_RNO[7]  (.A(\\_l3.Dataout39_1 ), .B(\\DataIn_c[2] )\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:85: Cannot find file containing module: 'OA1B'\n    OA1B \\Dataout_pad_RNO[4]  (.A(\\DataIn_c[1] ), .B(\\_l4.Dataout48_0 )\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:87: Cannot find file containing module: 'OR3C'\n    OR3C G2AN_pad_RNIRL86 (.A(G2AN_c), .B(G1_c), .C(G2BN_c), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:89: Cannot find file containing module: 'OA1C'\n    OA1C \\Dataout_pad_RNO[3]  (.A(\\_l3.Dataout39_1 ), .B(\\DataIn_c[2] )\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:91: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Dataout_pad[6]/U0/U1  (.D(\\Dataout_c[6] ), .E(VCC), \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:94: Cannot find file containing module: 'NOR2B'\n    NOR2B \\Dataout_pad_RNO_0[6]  (.A(\\DataIn_c[1] ), .B(\\DataIn_c[2] ), \n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:96: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\DataIn_pad[2]/U0/U0  (.PAD(DataIn[2]), .Y(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:98: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Dataout_pad[2]/U0/U1  (.D(\\Dataout_c[2] ), .E(VCC), \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:101: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Dataout_pad[3]/U0/U1  (.D(\\Dataout_c[3] ), .E(VCC), \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:104: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\DataIn_pad[0]/U0/U0  (.PAD(DataIn[0]), .Y(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:106: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\G2BN_pad/U0/U0  (.PAD(G2BN), .Y(\\G2BN_pad/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:107: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Dataout_pad[0]/U0/U0  (.D(\\Dataout_pad[0]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:109: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Dataout_pad[7]/U0/U0  (.D(\\Dataout_pad[7]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:111: Cannot find file containing module: 'OA1B'\n    OA1B \\Dataout_pad_RNO[1]  (.A(\\DataIn_c[2] ), .B(\\_l1.Dataout21_0 )\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:113: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Dataout_pad[1]/U0/U0  (.D(\\Dataout_pad[1]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:115: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Dataout_pad[5]/U0/U0  (.D(\\Dataout_pad[5]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:117: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\G2AN_pad/U0/U0  (.PAD(G2AN), .Y(\\G2AN_pad/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:118: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\DataIn_pad[2]/U0/U1  (.YIN(\\DataIn_pad[2]/U0/NET1 ), .Y(\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:120: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\G1_pad/U0/U0  (.PAD(G1), .Y(\\G1_pad/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:121: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\DataIn_pad[0]/U0/U1  (.YIN(\\DataIn_pad[0]/U0/NET1 ), .Y(\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:123: Cannot find file containing module: 'OA1C'\n    OA1C \\Dataout_pad_RNO[6]  (.A(\\_l6.Dataout66_0 ), .B(\\DataIn_c[0] )\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:125: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Dataout_pad[4]/U0/U0  (.D(\\Dataout_pad[4]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:127: Cannot find file containing module: 'OA1B'\n    OA1B \\Dataout_pad_RNO[0]  (.A(\\DataIn_c[2] ), .B(\\_l0.Dataout12_0 )\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:129: Cannot find file containing module: 'OR2A'\n    OR2A \\Dataout_pad_RNO_0[1]  (.A(\\DataIn_c[0] ), .B(\\DataIn_c[1] ), \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:131: Cannot find file containing module: 'NOR2B'\n    NOR2B \\DataIn_pad_RNIJEJ8[0]  (.A(\\DataIn_c[1] ), .B(\\DataIn_c[0] )\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:133: Cannot find file containing module: 'GND'\n    GND GND_power_inst1 (.Y(GND_power_net1));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/designer/impl1/HC138_ba.v:134: Cannot find file containing module: 'VCC'\n    VCC VCC_power_inst1 (.Y(VCC_power_net1));\n    ^~~\n%Error: Exiting due to 46 error(s)\n"
module HC138(
       DataIn,
       Dataout,
       G1,
       G2AN,
       G2BN
    );
input  [2:0] DataIn;
output [7:0] Dataout;
input  G1;
input  G2AN;
input  G2BN;

    wire \DataIn_c[0] , \DataIn_c[1] , \DataIn_c[2] , \Dataout_c[0] , 
        \Dataout_c[1] , \Dataout_c[2] , \Dataout_c[3] , \Dataout_c[4] , 
        \Dataout_c[5] , \Dataout_c[6] , \Dataout_c[7] , G1_c, G2AN_c, 
        G2BN_c, Dataout79, \_l3.Dataout39_1 , \_l0.Dataout12_0 , 
        \_l1.Dataout21_0 , \_l2.Dataout30_0 , \_l4.Dataout48_0 , 
        \_l5.Dataout57_0 , \_l6.Dataout66_0 , \Dataout_pad[2]/U0/NET1 , 
        \Dataout_pad[2]/U0/NET2 , \G1_pad/U0/NET1 , 
        \DataIn_pad[2]/U0/NET1 , \Dataout_pad[0]/U0/NET1 , 
        \Dataout_pad[0]/U0/NET2 , \G2BN_pad/U0/NET1 , 
        \DataIn_pad[0]/U0/NET1 , \Dataout_pad[7]/U0/NET1 , 
        \Dataout_pad[7]/U0/NET2 , \Dataout_pad[1]/U0/NET1 , 
        \Dataout_pad[1]/U0/NET2 , \G2AN_pad/U0/NET1 , 
        \DataIn_pad[1]/U0/NET1 , \Dataout_pad[3]/U0/NET1 , 
        \Dataout_pad[3]/U0/NET2 , \Dataout_pad[6]/U0/NET1 , 
        \Dataout_pad[6]/U0/NET2 , \Dataout_pad[4]/U0/NET1 , 
        \Dataout_pad[4]/U0/NET2 , \Dataout_pad[5]/U0/NET1 , 
        \Dataout_pad[5]/U0/NET2 , VCC, GND, AFLSDF_VCC, AFLSDF_GND;
    wire GND_power_net1;
    wire VCC_power_net1;
    assign GND = GND_power_net1;
    assign AFLSDF_GND = GND_power_net1;
    assign VCC = VCC_power_net1;
    assign AFLSDF_VCC = VCC_power_net1;
    
    NOR2A \Dataout_pad_RNO_0[2]  (.A(\DataIn_c[1] ), .B(\DataIn_c[0] ), 
        .Y(\_l2.Dataout30_0 ));
    OA1C \Dataout_pad_RNO[2]  (.A(\_l2.Dataout30_0 ), .B(\DataIn_c[2] )
        , .C(Dataout79), .Y(\Dataout_c[2] ));
    OR2 \Dataout_pad_RNO_0[0]  (.A(\DataIn_c[0] ), .B(\DataIn_c[1] ), 
        .Y(\_l0.Dataout12_0 ));
    IOTRI_OB_EB \Dataout_pad[0]/U0/U1  (.D(\Dataout_c[0] ), .E(VCC), 
        .DOUT(\Dataout_pad[0]/U0/NET1 ), .EOUT(
        \Dataout_pad[0]/U0/NET2 ));
    IOPAD_IN \DataIn_pad[1]/U0/U0  (.PAD(DataIn[1]), .Y(
        \DataIn_pad[1]/U0/NET1 ));
    OR2A \Dataout_pad_RNO_0[4]  (.A(\DataIn_c[2] ), .B(\DataIn_c[0] ), 
        .Y(\_l4.Dataout48_0 ));
    IOIN_IB \G2BN_pad/U0/U1  (.YIN(\G2BN_pad/U0/NET1 ), .Y(G2BN_c));
    IOTRI_OB_EB \Dataout_pad[7]/U0/U1  (.D(\Dataout_c[7] ), .E(VCC), 
        .DOUT(\Dataout_pad[7]/U0/NET1 ), .EOUT(
        \Dataout_pad[7]/U0/NET2 ));
    IOPAD_TRI \Dataout_pad[6]/U0/U0  (.D(\Dataout_pad[6]/U0/NET1 ), .E(
        \Dataout_pad[6]/U0/NET2 ), .PAD(Dataout[6]));
    IOTRI_OB_EB \Dataout_pad[1]/U0/U1  (.D(\Dataout_c[1] ), .E(VCC), 
        .DOUT(\Dataout_pad[1]/U0/NET1 ), .EOUT(
        \Dataout_pad[1]/U0/NET2 ));
    OR2B \Dataout_pad_RNO_0[5]  (.A(\DataIn_c[0] ), .B(\DataIn_c[2] ), 
        .Y(\_l5.Dataout57_0 ));
    IOTRI_OB_EB \Dataout_pad[5]/U0/U1  (.D(\Dataout_c[5] ), .E(VCC), 
        .DOUT(\Dataout_pad[5]/U0/NET1 ), .EOUT(
        \Dataout_pad[5]/U0/NET2 ));
    IOIN_IB \G2AN_pad/U0/U1  (.YIN(\G2AN_pad/U0/NET1 ), .Y(G2AN_c));
    IOPAD_TRI \Dataout_pad[2]/U0/U0  (.D(\Dataout_pad[2]/U0/NET1 ), .E(
        \Dataout_pad[2]/U0/NET2 ), .PAD(Dataout[2]));
    IOTRI_OB_EB \Dataout_pad[4]/U0/U1  (.D(\Dataout_c[4] ), .E(VCC), 
        .DOUT(\Dataout_pad[4]/U0/NET1 ), .EOUT(
        \Dataout_pad[4]/U0/NET2 ));
    IOPAD_TRI \Dataout_pad[3]/U0/U0  (.D(\Dataout_pad[3]/U0/NET1 ), .E(
        \Dataout_pad[3]/U0/NET2 ), .PAD(Dataout[3]));
    IOIN_IB \DataIn_pad[1]/U0/U1  (.YIN(\DataIn_pad[1]/U0/NET1 ), .Y(
        \DataIn_c[1] ));
    OA1B \Dataout_pad_RNO[5]  (.A(\DataIn_c[1] ), .B(\_l5.Dataout57_0 )
        , .C(Dataout79), .Y(\Dataout_c[5] ));
    IOIN_IB \G1_pad/U0/U1  (.YIN(\G1_pad/U0/NET1 ), .Y(G1_c));
    AOI1 \Dataout_pad_RNO[7]  (.A(\_l3.Dataout39_1 ), .B(\DataIn_c[2] )
        , .C(Dataout79), .Y(\Dataout_c[7] ));
    OA1B \Dataout_pad_RNO[4]  (.A(\DataIn_c[1] ), .B(\_l4.Dataout48_0 )
        , .C(Dataout79), .Y(\Dataout_c[4] ));
    OR3C G2AN_pad_RNIRL86 (.A(G2AN_c), .B(G1_c), .C(G2BN_c), .Y(
        Dataout79));
    OA1C \Dataout_pad_RNO[3]  (.A(\_l3.Dataout39_1 ), .B(\DataIn_c[2] )
        , .C(Dataout79), .Y(\Dataout_c[3] ));
    IOTRI_OB_EB \Dataout_pad[6]/U0/U1  (.D(\Dataout_c[6] ), .E(VCC), 
        .DOUT(\Dataout_pad[6]/U0/NET1 ), .EOUT(
        \Dataout_pad[6]/U0/NET2 ));
    NOR2B \Dataout_pad_RNO_0[6]  (.A(\DataIn_c[1] ), .B(\DataIn_c[2] ), 
        .Y(\_l6.Dataout66_0 ));
    IOPAD_IN \DataIn_pad[2]/U0/U0  (.PAD(DataIn[2]), .Y(
        \DataIn_pad[2]/U0/NET1 ));
    IOTRI_OB_EB \Dataout_pad[2]/U0/U1  (.D(\Dataout_c[2] ), .E(VCC), 
        .DOUT(\Dataout_pad[2]/U0/NET1 ), .EOUT(
        \Dataout_pad[2]/U0/NET2 ));
    IOTRI_OB_EB \Dataout_pad[3]/U0/U1  (.D(\Dataout_c[3] ), .E(VCC), 
        .DOUT(\Dataout_pad[3]/U0/NET1 ), .EOUT(
        \Dataout_pad[3]/U0/NET2 ));
    IOPAD_IN \DataIn_pad[0]/U0/U0  (.PAD(DataIn[0]), .Y(
        \DataIn_pad[0]/U0/NET1 ));
    IOPAD_IN \G2BN_pad/U0/U0  (.PAD(G2BN), .Y(\G2BN_pad/U0/NET1 ));
    IOPAD_TRI \Dataout_pad[0]/U0/U0  (.D(\Dataout_pad[0]/U0/NET1 ), .E(
        \Dataout_pad[0]/U0/NET2 ), .PAD(Dataout[0]));
    IOPAD_TRI \Dataout_pad[7]/U0/U0  (.D(\Dataout_pad[7]/U0/NET1 ), .E(
        \Dataout_pad[7]/U0/NET2 ), .PAD(Dataout[7]));
    OA1B \Dataout_pad_RNO[1]  (.A(\DataIn_c[2] ), .B(\_l1.Dataout21_0 )
        , .C(Dataout79), .Y(\Dataout_c[1] ));
    IOPAD_TRI \Dataout_pad[1]/U0/U0  (.D(\Dataout_pad[1]/U0/NET1 ), .E(
        \Dataout_pad[1]/U0/NET2 ), .PAD(Dataout[1]));
    IOPAD_TRI \Dataout_pad[5]/U0/U0  (.D(\Dataout_pad[5]/U0/NET1 ), .E(
        \Dataout_pad[5]/U0/NET2 ), .PAD(Dataout[5]));
    IOPAD_IN \G2AN_pad/U0/U0  (.PAD(G2AN), .Y(\G2AN_pad/U0/NET1 ));
    IOIN_IB \DataIn_pad[2]/U0/U1  (.YIN(\DataIn_pad[2]/U0/NET1 ), .Y(
        \DataIn_c[2] ));
    IOPAD_IN \G1_pad/U0/U0  (.PAD(G1), .Y(\G1_pad/U0/NET1 ));
    IOIN_IB \DataIn_pad[0]/U0/U1  (.YIN(\DataIn_pad[0]/U0/NET1 ), .Y(
        \DataIn_c[0] ));
    OA1C \Dataout_pad_RNO[6]  (.A(\_l6.Dataout66_0 ), .B(\DataIn_c[0] )
        , .C(Dataout79), .Y(\Dataout_c[6] ));
    IOPAD_TRI \Dataout_pad[4]/U0/U0  (.D(\Dataout_pad[4]/U0/NET1 ), .E(
        \Dataout_pad[4]/U0/NET2 ), .PAD(Dataout[4]));
    OA1B \Dataout_pad_RNO[0]  (.A(\DataIn_c[2] ), .B(\_l0.Dataout12_0 )
        , .C(Dataout79), .Y(\Dataout_c[0] ));
    OR2A \Dataout_pad_RNO_0[1]  (.A(\DataIn_c[0] ), .B(\DataIn_c[1] ), 
        .Y(\_l1.Dataout21_0 ));
    NOR2B \DataIn_pad_RNIJEJ8[0]  (.A(\DataIn_c[1] ), .B(\DataIn_c[0] )
        , .Y(\_l3.Dataout39_1 ));
    GND GND_power_inst1 (.Y(GND_power_net1));
    VCC VCC_power_inst1 (.Y(VCC_power_net1));
    
endmodule
module HC138(
       DataIn,
       Dataout,
       G1,
       G2AN,
       G2BN
    );

input  [2:0] DataIn;
output [7:0] Dataout;
input  G1;
input  G2AN;
input  G2BN;

    wire \DataIn_c[0] , \DataIn_c[1] , \DataIn_c[2] , \Dataout_c[0] , 
        \Dataout_c[1] , \Dataout_c[2] , \Dataout_c[3] , \Dataout_c[4] , 
        \Dataout_c[5] , \Dataout_c[6] , \Dataout_c[7] , G1_c, G2AN_c, 
        G2BN_c, Dataout79, \_l3.Dataout39_1 , \_l0.Dataout12_0 , 
        \_l1.Dataout21_0 , \_l2.Dataout30_0 , \_l4.Dataout48_0 , 
        \_l5.Dataout57_0 , \_l6.Dataout66_0 , \Dataout_pad[2]/U0/NET1 , 
        \Dataout_pad[2]/U0/NET2 , \G1_pad/U0/NET1 , 
        \DataIn_pad[2]/U0/NET1 , \Dataout_pad[0]/U0/NET1 , 
        \Dataout_pad[0]/U0/NET2 , \G2BN_pad/U0/NET1 , 
        \DataIn_pad[0]/U0/NET1 , \Dataout_pad[7]/U0/NET1 , 
        \Dataout_pad[7]/U0/NET2 , \Dataout_pad[1]/U0/NET1 , 
        \Dataout_pad[1]/U0/NET2 , \G2AN_pad/U0/NET1 , 
        \DataIn_pad[1]/U0/NET1 , \Dataout_pad[3]/U0/NET1 , 
        \Dataout_pad[3]/U0/NET2 , \Dataout_pad[6]/U0/NET1 , 
        \Dataout_pad[6]/U0/NET2 , \Dataout_pad[4]/U0/NET1 , 
        \Dataout_pad[4]/U0/NET2 , \Dataout_pad[5]/U0/NET1 , 
        \Dataout_pad[5]/U0/NET2 , VCC, GND, AFLSDF_VCC, AFLSDF_GND;
    wire GND_power_net1;
    wire VCC_power_net1;
    assign GND = GND_power_net1;
    assign AFLSDF_GND = GND_power_net1;
    assign VCC = VCC_power_net1;
    assign AFLSDF_VCC = VCC_power_net1;
    
    NOR2A \Dataout_pad_RNO_0[2]  (.A(\DataIn_c[1] ), .B(\DataIn_c[0] ), 
        .Y(\_l2.Dataout30_0 ));
    OA1C \Dataout_pad_RNO[2]  (.A(\_l2.Dataout30_0 ), .B(\DataIn_c[2] )
        , .C(Dataout79), .Y(\Dataout_c[2] ));
    OR2 \Dataout_pad_RNO_0[0]  (.A(\DataIn_c[0] ), .B(\DataIn_c[1] ), 
        .Y(\_l0.Dataout12_0 ));
    IOTRI_OB_EB \Dataout_pad[0]/U0/U1  (.D(\Dataout_c[0] ), .E(VCC), 
        .DOUT(\Dataout_pad[0]/U0/NET1 ), .EOUT(
        \Dataout_pad[0]/U0/NET2 ));
    IOPAD_IN \DataIn_pad[1]/U0/U0  (.PAD(DataIn[1]), .Y(
        \DataIn_pad[1]/U0/NET1 ));
    OR2A \Dataout_pad_RNO_0[4]  (.A(\DataIn_c[2] ), .B(\DataIn_c[0] ), 
        .Y(\_l4.Dataout48_0 ));
    IOIN_IB \G2BN_pad/U0/U1  (.YIN(\G2BN_pad/U0/NET1 ), .Y(G2BN_c));
    IOTRI_OB_EB \Dataout_pad[7]/U0/U1  (.D(\Dataout_c[7] ), .E(VCC), 
        .DOUT(\Dataout_pad[7]/U0/NET1 ), .EOUT(
        \Dataout_pad[7]/U0/NET2 ));
    IOPAD_TRI \Dataout_pad[6]/U0/U0  (.D(\Dataout_pad[6]/U0/NET1 ), .E(
        \Dataout_pad[6]/U0/NET2 ), .PAD(Dataout[6]));
    IOTRI_OB_EB \Dataout_pad[1]/U0/U1  (.D(\Dataout_c[1] ), .E(VCC), 
        .DOUT(\Dataout_pad[1]/U0/NET1 ), .EOUT(
        \Dataout_pad[1]/U0/NET2 ));
    OR2B \Dataout_pad_RNO_0[5]  (.A(\DataIn_c[0] ), .B(\DataIn_c[2] ), 
        .Y(\_l5.Dataout57_0 ));
    IOTRI_OB_EB \Dataout_pad[5]/U0/U1  (.D(\Dataout_c[5] ), .E(VCC), 
        .DOUT(\Dataout_pad[5]/U0/NET1 ), .EOUT(
        \Dataout_pad[5]/U0/NET2 ));
    IOIN_IB \G2AN_pad/U0/U1  (.YIN(\G2AN_pad/U0/NET1 ), .Y(G2AN_c));
    IOPAD_TRI \Dataout_pad[2]/U0/U0  (.D(\Dataout_pad[2]/U0/NET1 ), .E(
        \Dataout_pad[2]/U0/NET2 ), .PAD(Dataout[2]));
    IOTRI_OB_EB \Dataout_pad[4]/U0/U1  (.D(\Dataout_c[4] ), .E(VCC), 
        .DOUT(\Dataout_pad[4]/U0/NET1 ), .EOUT(
        \Dataout_pad[4]/U0/NET2 ));
    IOPAD_TRI \Dataout_pad[3]/U0/U0  (.D(\Dataout_pad[3]/U0/NET1 ), .E(
        \Dataout_pad[3]/U0/NET2 ), .PAD(Dataout[3]));
    IOIN_IB \DataIn_pad[1]/U0/U1  (.YIN(\DataIn_pad[1]/U0/NET1 ), .Y(
        \DataIn_c[1] ));
    OA1B \Dataout_pad_RNO[5]  (.A(\DataIn_c[1] ), .B(\_l5.Dataout57_0 )
        , .C(Dataout79), .Y(\Dataout_c[5] ));
    IOIN_IB \G1_pad/U0/U1  (.YIN(\G1_pad/U0/NET1 ), .Y(G1_c));
    AOI1 \Dataout_pad_RNO[7]  (.A(\_l3.Dataout39_1 ), .B(\DataIn_c[2] )
        , .C(Dataout79), .Y(\Dataout_c[7] ));
    OA1B \Dataout_pad_RNO[4]  (.A(\DataIn_c[1] ), .B(\_l4.Dataout48_0 )
        , .C(Dataout79), .Y(\Dataout_c[4] ));
    OR3C G2AN_pad_RNIRL86 (.A(G2AN_c), .B(G1_c), .C(G2BN_c), .Y(
        Dataout79));
    OA1C \Dataout_pad_RNO[3]  (.A(\_l3.Dataout39_1 ), .B(\DataIn_c[2] )
        , .C(Dataout79), .Y(\Dataout_c[3] ));
    IOTRI_OB_EB \Dataout_pad[6]/U0/U1  (.D(\Dataout_c[6] ), .E(VCC), 
        .DOUT(\Dataout_pad[6]/U0/NET1 ), .EOUT(
        \Dataout_pad[6]/U0/NET2 ));
    NOR2B \Dataout_pad_RNO_0[6]  (.A(\DataIn_c[1] ), .B(\DataIn_c[2] ), 
        .Y(\_l6.Dataout66_0 ));
    IOPAD_IN \DataIn_pad[2]/U0/U0  (.PAD(DataIn[2]), .Y(
        \DataIn_pad[2]/U0/NET1 ));
    IOTRI_OB_EB \Dataout_pad[2]/U0/U1  (.D(\Dataout_c[2] ), .E(VCC), 
        .DOUT(\Dataout_pad[2]/U0/NET1 ), .EOUT(
        \Dataout_pad[2]/U0/NET2 ));
    IOTRI_OB_EB \Dataout_pad[3]/U0/U1  (.D(\Dataout_c[3] ), .E(VCC), 
        .DOUT(\Dataout_pad[3]/U0/NET1 ), .EOUT(
        \Dataout_pad[3]/U0/NET2 ));
    IOPAD_IN \DataIn_pad[0]/U0/U0  (.PAD(DataIn[0]), .Y(
        \DataIn_pad[0]/U0/NET1 ));
    IOPAD_IN \G2BN_pad/U0/U0  (.PAD(G2BN), .Y(\G2BN_pad/U0/NET1 ));
    IOPAD_TRI \Dataout_pad[0]/U0/U0  (.D(\Dataout_pad[0]/U0/NET1 ), .E(
        \Dataout_pad[0]/U0/NET2 ), .PAD(Dataout[0]));
    IOPAD_TRI \Dataout_pad[7]/U0/U0  (.D(\Dataout_pad[7]/U0/NET1 ), .E(
        \Dataout_pad[7]/U0/NET2 ), .PAD(Dataout[7]));
    OA1B \Dataout_pad_RNO[1]  (.A(\DataIn_c[2] ), .B(\_l1.Dataout21_0 )
        , .C(Dataout79), .Y(\Dataout_c[1] ));
    IOPAD_TRI \Dataout_pad[1]/U0/U0  (.D(\Dataout_pad[1]/U0/NET1 ), .E(
        \Dataout_pad[1]/U0/NET2 ), .PAD(Dataout[1]));
    IOPAD_TRI \Dataout_pad[5]/U0/U0  (.D(\Dataout_pad[5]/U0/NET1 ), .E(
        \Dataout_pad[5]/U0/NET2 ), .PAD(Dataout[5]));
    IOPAD_IN \G2AN_pad/U0/U0  (.PAD(G2AN), .Y(\G2AN_pad/U0/NET1 ));
    IOIN_IB \DataIn_pad[2]/U0/U1  (.YIN(\DataIn_pad[2]/U0/NET1 ), .Y(
        \DataIn_c[2] ));
    IOPAD_IN \G1_pad/U0/U0  (.PAD(G1), .Y(\G1_pad/U0/NET1 ));
    IOIN_IB \DataIn_pad[0]/U0/U1  (.YIN(\DataIn_pad[0]/U0/NET1 ), .Y(
        \DataIn_c[0] ));
    OA1C \Dataout_pad_RNO[6]  (.A(\_l6.Dataout66_0 ), .B(\DataIn_c[0] )
        , .C(Dataout79), .Y(\Dataout_c[6] ));
    IOPAD_TRI \Dataout_pad[4]/U0/U0  (.D(\Dataout_pad[4]/U0/NET1 ), .E(
        \Dataout_pad[4]/U0/NET2 ), .PAD(Dataout[4]));
    OA1B \Dataout_pad_RNO[0]  (.A(\DataIn_c[2] ), .B(\_l0.Dataout12_0 )
        , .C(Dataout79), .Y(\Dataout_c[0] ));
    OR2A \Dataout_pad_RNO_0[1]  (.A(\DataIn_c[0] ), .B(\DataIn_c[1] ), 
        .Y(\_l1.Dataout21_0 ));
    NOR2B \DataIn_pad_RNIJEJ8[0]  (.A(\DataIn_c[1] ), .B(\DataIn_c[0] )
        , .Y(\_l3.Dataout39_1 ));
    GND GND_power_inst1 (.Y(GND_power_net1));
    VCC VCC_power_inst1 (.Y(VCC_power_net1));
    
endmodule