data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:57: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                      : ... In instance DAC_control\n   tx_spi_din <= inidata_1[9\'d25-counter];\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:60: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                      : ... In instance DAC_control\n   tx_spi_din <= inidata_1[9\'d25-counter];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:68: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                      : ... In instance DAC_control\n   tx_spi_din <= inidata_2[9\'d50-counter];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:71: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                      : ... In instance DAC_control\n   tx_spi_din <= inidata_2[9\'d50-counter];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:79: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                      : ... In instance DAC_control\n   tx_spi_din <= inidata_3[9\'d75-counter];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:82: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                      : ... In instance DAC_control\n   tx_spi_din <= inidata_3[9\'d75-counter];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:90: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                      : ... In instance DAC_control\n   tx_spi_din <= inidata_4[9\'d100-counter];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:93: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                      : ... In instance DAC_control\n   tx_spi_din <= inidata_4[9\'d100-counter];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:102: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                       : ... In instance DAC_control\n   tx_spi_din <= sawtooth[9\'d125-counter];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:105: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                       : ... In instance DAC_control\n   tx_spi_din <= sawtooth[9\'d125-counter];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:113: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                       : ... In instance DAC_control\n   tx_spi_din <= stepwave[9\'d150-counter];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:116: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                       : ... In instance DAC_control\n   tx_spi_din <= stepwave[9\'d150-counter];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:124: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                       : ... In instance DAC_control\n   tx_spi_din <= pin3_C_yminu[9\'d175-counter];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:127: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                       : ... In instance DAC_control\n   tx_spi_din <= pin3_C_yminu[9\'d175-counter];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:135: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                       : ... In instance DAC_control\n   tx_spi_din <= pin4_D_yplus[9\'d200-counter];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:138: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n                                                                                       : ... In instance DAC_control\n   tx_spi_din <= pin4_D_yplus[9\'d200-counter];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:146: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'16\'h7cf\' generates 16 bits.\n                                                                                       : ... In instance DAC_control\n  if(verti_counter == 16\'d1999 & serial_counter == 4) loop <= 1\'d1;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:147: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                       : ... In instance DAC_control\n  if(verti_counter == 16\'d0) loop <= 1\'d0;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:155: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                       : ... In instance DAC_control\n      verti_counter <= 12\'d0;        \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:170: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                       : ... In instance DAC_control\n     verti_counter <= 12\'d0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:169: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'12\'h7cf\' generates 12 bits.\n                                                                                       : ... In instance DAC_control\n    if(verti_counter == 12\'d1999 & serial_counter == 4\'d4)begin  \n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:173: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                       : ... In instance DAC_control\n    serial_counter <= 1\'d1;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:180: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'12\'h1\' generates 12 bits.\n                                                                                       : ... In instance DAC_control\n     verti_counter <= verti_counter + 12\'d1;\n                                    ^\n%Error: Exiting due to 23 warning(s)\n'
module DAC_control(
	input wire tx_spi_sclk_wire,
	input wire rst,
	output reg tx_spi_sync,
	output reg tx_spi_din,
	output reg adc_start,
	output reg [31:0] verti_counter,
	output reg [3:0] serial_counter,
	output reg loop
	);

parameter inidata_1 = 24'b001010010000000000000001, inidata_2 = 24'b001110010000000000000001,

		inidata_3 = 24'b001000000000000000001111, inidata_4 = 24'b001100000000000000000000;

reg [8:0] counter;

reg init = 1'b1;

reg [7:0] hori_counter;

reg [23:0] sawtooth = 24'b00000000_0000000000000000;

reg [23:0] stepwave = 24'b00000001_0000000000000000;

reg [23:0] pin3_C_yminu = 24'b00000010_0000110110111001;

reg [23:0] pin4_D_yplus = 24'b00010011_1100111000111100;

parameter sawstep = 24'b0000_0000_0000_0000_0001_0000_0110;
parameter stepstep = 24'b0000_0000_0000_0010_0100_1001_0010;

	


	always @(negedge tx_spi_sclk_wire) begin
		if(~rst) begin
			counter <= 0;
		end
		else begin
			counter <= counter + 1'b1;
			if(counter == 9'd201) counter <= 9'd102;
		end
	end

	always @(posedge tx_spi_sclk_wire) begin
		case(counter)
		0:tx_spi_sync <= 1'b0;
		1: begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 1'b0;
			loop <= 1'b1;
			end

		2:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= inidata_1[9'd25-counter];
			end
		3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25:
			tx_spi_din <= inidata_1[9'd25-counter];
		26:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		27:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= inidata_2[9'd50-counter];
			end
		28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50:
			tx_spi_din <= inidata_2[9'd50-counter];
		51:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		52:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= inidata_3[9'd75-counter];
			end
		53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75:
			tx_spi_din <= inidata_3[9'd75-counter];
		76:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		77:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= inidata_4[9'd100-counter];
			end
		78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100:
			tx_spi_din <= inidata_4[9'd100-counter];
		101:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			init <= 1'b0;
			end
		
		102:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= sawtooth[9'd125-counter];
			end
		103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125:
			tx_spi_din <= sawtooth[9'd125-counter];
		126:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		127:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= stepwave[9'd150-counter];
			end
		128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150:
			tx_spi_din <= stepwave[9'd150-counter];
		151:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		152:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= pin3_C_yminu[9'd175-counter];
			end
		153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175:
			tx_spi_din <= pin3_C_yminu[9'd175-counter];
		176:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		177:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= pin4_D_yplus[9'd200-counter];
			end
		178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200:
			tx_spi_din <= pin4_D_yplus[9'd200-counter];
		201:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		default:;
		endcase
		if(verti_counter == 16'd1999 & serial_counter == 4) loop <= 1'd1;
		if(verti_counter == 16'd0) loop <= 1'd0;
	end


	always @(posedge tx_spi_sync) begin
		if (counter == 1) begin

			hori_counter <= 8'b0;
		    verti_counter <= 12'd0;
		    serial_counter <= 4'd0;
			adc_start <= 0;
			sawtooth <= 24'b00000000_0000000000000000;
			stepwave <= 24'b00000001_0000000000000000;
			pin3_C_yminu <= 24'b00000010_0000000000000000;
			pin4_D_yplus <= 24'b00010011_0000000000000000;
		end
		else if(init == 0)begin
			if(serial_counter == 4)
			adc_start <= 1;
			if(loop == 1'd1) begin
				sawtooth <= 24'b00000000_0000000000000000;
				stepwave <= 24'b00000001_0000000000000000;
				if(verti_counter == 12'd1999 & serial_counter == 4'd4)begin
					verti_counter <= 12'd0;
					hori_counter <= 8'b0;
				end
				serial_counter <= 1'd1;
			end
			else begin
				serial_counter <= serial_counter + 1'b1;

				if(serial_counter == 4'd4) begin
					serial_counter <= 4'd1;
					verti_counter <= verti_counter + 12'd1;
					
					hori_counter <= hori_counter + 1'b1;
					if(hori_counter == 8'd249) begin
						hori_counter <= 8'b0;
						sawtooth <= 24'b00000000_0000000000000000;
						stepwave <= stepwave + stepstep;
					end
					else begin
						if(hori_counter < 8'd125) sawtooth <= sawtooth + sawstep;
						if(hori_counter < 8'd249 && hori_counter >= 8'd125) sawtooth <= sawtooth - sawstep;

					end
				end
			end
		end
	end

endmodule
module DAC_control(
	input wire tx_spi_sclk_wire,
	input wire rst,
	output reg tx_spi_sync,
	output reg tx_spi_din,
	output reg adc_start,
	output reg [31:0] verti_counter,
	output reg [3:0] serial_counter,
	output reg loop
	);


parameter inidata_1 = 24'b001010010000000000000001, inidata_2 = 24'b001110010000000000000001,

		inidata_3 = 24'b001000000000000000001111, inidata_4 = 24'b001100000000000000000000;

reg [8:0] counter;

reg init = 1'b1;

reg [7:0] hori_counter;

reg [23:0] sawtooth = 24'b00000000_0000000000000000;

reg [23:0] stepwave = 24'b00000001_0000000000000000;

reg [23:0] pin3_C_yminu = 24'b00000010_0000110110111001;

reg [23:0] pin4_D_yplus = 24'b00010011_1100111000111100;

parameter sawstep = 24'b0000_0000_0000_0000_0001_0000_0110;
parameter stepstep = 24'b0000_0000_0000_0010_0100_1001_0010;

	


	always @(negedge tx_spi_sclk_wire) begin
		if(~rst) begin
			counter <= 0;
		end
		else begin
			counter <= counter + 1'b1;
			if(counter == 9'd201) counter <= 9'd102;
		end
	end

	always @(posedge tx_spi_sclk_wire) begin
		case(counter)
		0:tx_spi_sync <= 1'b0;
		1: begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 1'b0;
			loop <= 1'b1;
			end

		2:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= inidata_1[9'd25-counter];
			end
		3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25:
			tx_spi_din <= inidata_1[9'd25-counter];
		26:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		27:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= inidata_2[9'd50-counter];
			end
		28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50:
			tx_spi_din <= inidata_2[9'd50-counter];
		51:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		52:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= inidata_3[9'd75-counter];
			end
		53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75:
			tx_spi_din <= inidata_3[9'd75-counter];
		76:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		77:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= inidata_4[9'd100-counter];
			end
		78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100:
			tx_spi_din <= inidata_4[9'd100-counter];
		101:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			init <= 1'b0;
			end
		
		102:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= sawtooth[9'd125-counter];
			end
		103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125:
			tx_spi_din <= sawtooth[9'd125-counter];
		126:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		127:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= stepwave[9'd150-counter];
			end
		128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150:
			tx_spi_din <= stepwave[9'd150-counter];
		151:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		152:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= pin3_C_yminu[9'd175-counter];
			end
		153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175:
			tx_spi_din <= pin3_C_yminu[9'd175-counter];
		176:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		177:begin
			tx_spi_sync <= 1'b0;
			tx_spi_din <= pin4_D_yplus[9'd200-counter];
			end
		178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200:
			tx_spi_din <= pin4_D_yplus[9'd200-counter];
		201:begin
			tx_spi_sync <= 1'b1;
			tx_spi_din <= 0;
			end

		default:;
		endcase
		if(verti_counter == 16'd1999 & serial_counter == 4) loop <= 1'd1;
		if(verti_counter == 16'd0) loop <= 1'd0;
	end


	always @(posedge tx_spi_sync) begin
		if (counter == 1) begin

			hori_counter <= 8'b0;
		    verti_counter <= 12'd0;
		    serial_counter <= 4'd0;
			adc_start <= 0;
			sawtooth <= 24'b00000000_0000000000000000;
			stepwave <= 24'b00000001_0000000000000000;
			pin3_C_yminu <= 24'b00000010_0000000000000000;
			pin4_D_yplus <= 24'b00010011_0000000000000000;
		end
		else if(init == 0)begin
			if(serial_counter == 4)
			adc_start <= 1;
			if(loop == 1'd1) begin
				sawtooth <= 24'b00000000_0000000000000000;
				stepwave <= 24'b00000001_0000000000000000;
				if(verti_counter == 12'd1999 & serial_counter == 4'd4)begin
					verti_counter <= 12'd0;
					hori_counter <= 8'b0;
				end
				serial_counter <= 1'd1;
			end
			else begin
				serial_counter <= serial_counter + 1'b1;

				if(serial_counter == 4'd4) begin
					serial_counter <= 4'd1;
					verti_counter <= verti_counter + 12'd1;
					
					hori_counter <= hori_counter + 1'b1;
					if(hori_counter == 8'd249) begin
						hori_counter <= 8'b0;
						sawtooth <= 24'b00000000_0000000000000000;
						stepwave <= stepwave + stepstep;
					end
					else begin
						if(hori_counter < 8'd125) sawtooth <= sawtooth + sawstep;
						if(hori_counter < 8'd249 && hori_counter >= 8'd125) sawtooth <= sawtooth - sawstep;

					end
				end
			end
		end
	end

endmodule