data/full_repos/permissive/163494071/analog/analog.v
 line:349: before: "["
1: b'%Warning-MULTITOP: data/full_repos/permissive/163494071/analog/analog.v:322: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'analog\'\nmodule analog(clk,rst,start,change_map,direction1,direction2,direction3,direction4,time_sign,row,g_col,r_col,suc,step_cnt);\n       ^~~~~~\n                                                                           : ... Top module \'two_ten\'\nmodule two_ten(clk,num,ten,one);\n       ^~~~~~~\n                                                                           : ... Top module \'debounce\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n       ^~~~~~~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                ^~~\n        data/full_repos/permissive/163494071/analog/analog.v:355: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                       ^~~\n        data/full_repos/permissive/163494071/analog/analog.v:355: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                              ^~~\n        data/full_repos/permissive/163494071/analog/analog.v:355: ... Location of original declaration\n        input  [N-1:0]   key;                  \n                         ^~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key_pulse\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                  ^~~~~~~~~\n        data/full_repos/permissive/163494071/analog/analog.v:356: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key_pulse\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                               ^~~~~~~~~\n        data/full_repos/permissive/163494071/analog/analog.v:356: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/163494071/analog/analog.v:349: Duplicate declaration of port: \'key_pulse\'\nmodule debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);\n                                                                                            ^~~~~~~~~\n        data/full_repos/permissive/163494071/analog/analog.v:356: ... Location of original declaration\n output  [N-1:0]   key_pulse;                   \n                   ^~~~~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);
 
        parameter       N  =  4;
 
	input             clk;
        input             rst;
        input 	[N-1:0]   key;
	output  [N-1:0]   key_pulse;
 
        reg     [N-1:0]   key_rst_pre;
        reg     [N-1:0]   key_rst;
 
        wire    [N-1:0]   key_edge;
 

        always @(posedge clk  or  negedge rst)
          begin
             if (!rst) begin
                 key_rst <= {N{1'b1}};
                 key_rst_pre <= {N{1'b1}};
             end
             else begin
                 key_rst <= key;
                 key_rst_pre <= key_rst;
             end    
           end
 
        assign  key_edge = key_rst_pre & (~key_rst);
 
        reg	[19:0]	  cnt;
 

        always @(posedge clk or negedge rst)
           begin
             if(!rst)
                cnt <= 20'h0;
             else if(key_edge)
                cnt <= 20'h0;
             else
                cnt <= cnt + 1'h1;
             end  
 
        reg     [N-1:0]   key_sec_pre;
        reg     [N-1:0]   key_sec;                    
 
 

        always @(posedge clk  or  negedge rst)
          begin
             if (!rst) 
                 key_sec <= {N{1'b1}};                
             else if (cnt==20'hf_ffff)
                 key_sec <= key;  
          end
          
       always @(posedge clk  or  negedge rst)
          begin
             if (!rst)
                 key_sec_pre <= {N{1'b1}};
             else                   
                 key_sec_pre <= key_sec;             
                 
         end      
       assign  key_pulse = key_sec_pre & (~key_sec);     
 
endmodule
module debounce (clk,rst,key[0],key[1],key[2],key[3],key_pulse[0],key_pulse[1],key_pulse[2],key_pulse[3]);

 
        parameter       N  =  4;
 
	input             clk;
        input             rst;
        input 	[N-1:0]   key;
	output  [N-1:0]   key_pulse;
 
        reg     [N-1:0]   key_rst_pre;
        reg     [N-1:0]   key_rst;
 
        wire    [N-1:0]   key_edge;
 

        always @(posedge clk  or  negedge rst)
          begin
             if (!rst) begin
                 key_rst <= {N{1'b1}};
                 key_rst_pre <= {N{1'b1}};
             end
             else begin
                 key_rst <= key;
                 key_rst_pre <= key_rst;
             end    
           end
 
        assign  key_edge = key_rst_pre & (~key_rst);
 
        reg	[19:0]	  cnt;
 

        always @(posedge clk or negedge rst)
           begin
             if(!rst)
                cnt <= 20'h0;
             else if(key_edge)
                cnt <= 20'h0;
             else
                cnt <= cnt + 1'h1;
             end  
 
        reg     [N-1:0]   key_sec_pre;
        reg     [N-1:0]   key_sec;                    
 
 

        always @(posedge clk  or  negedge rst)
          begin
             if (!rst) 
                 key_sec <= {N{1'b1}};                
             else if (cnt==20'hf_ffff)
                 key_sec <= key;  
          end
          
       always @(posedge clk  or  negedge rst)
          begin
             if (!rst)
                 key_sec_pre <= {N{1'b1}};
             else                   
                 key_sec_pre <= key_sec;             
                 
         end      
       assign  key_pulse = key_sec_pre & (~key_sec);     
 
endmodule