data/full_repos/permissive/159902111/SCPU_experiment/MIPS_tb.v
1: b'%Error: data/full_repos/permissive/159902111/SCPU_experiment/MIPS_tb.v:11: Unsupported or unknown PLI call: $monitor\n      $monitor($time, "PC = %8x", mips.SCPU.my_PC.PC);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159902111/SCPU_experiment/MIPS_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #5 rst_n = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159902111/SCPU_experiment/MIPS_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #1 rst_n = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/159902111/SCPU_experiment/MIPS_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk <= !clk;\n    ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MIPS_tb(
  );
  `timescale 1ns/1ps
  reg clk, rst_n;
  wire [31:0] PC_Addr, Instr;
  wire [63:0] ALU_result;
  reg  [31:0] i;
  MIPS mips(clk, rst_n, PC_Addr, Instr, ALU_result);
  initial
    begin
      $monitor($time, "PC = %8x", mips.SCPU.my_PC.PC);
      clk = 0;
      rst_n = 1;
      i = 0;
      #5 rst_n = 1;
      #1 rst_n = 0;
    end
    
  always
    #10 clk <= !clk;
  always@(posedge clk or negedge rst_n)
  begin




        $display("------testcase%d------", i);
        i <= i+1;





  end    
endmodule
module MIPS_tb(
  );

  `timescale 1ns/1ps
  reg clk, rst_n;
  wire [31:0] PC_Addr, Instr;
  wire [63:0] ALU_result;
  reg  [31:0] i;
  MIPS mips(clk, rst_n, PC_Addr, Instr, ALU_result);
  initial
    begin
      $monitor($time, "PC = %8x", mips.SCPU.my_PC.PC);
      clk = 0;
      rst_n = 1;
      i = 0;
      #5 rst_n = 1;
      #1 rst_n = 0;
    end
    
  always
    #10 clk <= !clk;
  always@(posedge clk or negedge rst_n)
  begin




        $display("------testcase%d------", i);
        i <= i+1;





  end    
endmodule