data/full_repos/permissive/212897440/effect_controler.v
1: b"%Error: data/full_repos/permissive/212897440/effect_controler.v:51: Cannot find file containing module: 'sync_fifo'\nsync_fifo #( \n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/sync_fifo\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/sync_fifo.v\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/sync_fifo.sv\n             sync_fifo\n             sync_fifo.v\n             sync_fifo.sv\n             obj_dir/sync_fifo\n             obj_dir/sync_fifo.v\n             obj_dir/sync_fifo.sv\n%Error: data/full_repos/permissive/212897440/effect_controler.v:69: Cannot find file containing module: 'sync_fifo'\nsync_fifo #( \n^~~~~~~~~\n%Error: data/full_repos/permissive/212897440/effect_controler.v:89: Cannot find file containing module: 'effect_mixer'\neffect_mixer #( \n^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module effect_controler #( parameter
    d_width = 24,
    address_width = 4,
    ram_depth = 16,
    memory_d_width = 16
)(
    input                               mclk,
    input                               clk,
    input                               reset,
    input   signed      [d_width-1: 0]  i_l_data,
    input   signed      [d_width-1: 0]  i_r_data,
    output  signed      [d_width-1: 0]  o_l_data,
    output  signed      [d_width-1: 0]  o_r_data,

    output                                      o_read_done,
    output                                      o_read_ready,


    input               [1:0]           sw,

    output  signed      [memory_d_width-1: 0]   o_data_to_eff,
    output                                      o_data_valid,
    input                                       i_read_enable,
    input  signed      [memory_d_width-1: 0]    i_data_from_eff_sw0,
    input  signed      [memory_d_width-1: 0]    i_data_from_eff_sw1,

    input                                       i_dv_from_eff
     
);

wire signed [memory_d_width-1: 0]  w_o_data;



wire                            w_empty_in, w_full_in;
wire                            w_empty_out, w_full_out;

wire  [memory_d_width-1:0]       w_data_to_fifo;

wire  [address_width-1:0]       w_data_fill_input;
wire  [address_width-1:0]       w_data_fill_output;

wire                            w_data_valid_to_fifo;

assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data;
assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data;

assign o_data_valid = ~w_empty_in;


sync_fifo #( 
   .ram_depth(ram_depth),
   .address_width(address_width),
   .data_width(memory_d_width)
) fifo_input (
   .data_out(o_data_to_eff),
   .full(w_full_in),
   .empty(w_empty_in),
   .data_fill(w_data_fill_input),
   .data_in(i_l_data[ d_width-1 : d_width - memory_d_width ]),       
   .w_clk(mclk),
   .r_clk(clk),
   .reset(reset),
   .wr_en( w_full_in  ? 1'b0 : 1'b1 ),
   .rd_en( w_empty_in ? 1'b0 : i_read_enable )
);


sync_fifo #( 
   .ram_depth(ram_depth),
   .address_width(address_width),
   .data_width(memory_d_width)
) fifo_output (
   .data_out(w_o_data),
   .full(w_full_out),
   .empty(w_empty_out),
   .data_fill(w_data_fill),
   .data_in(w_data_to_fifo),       
   .w_clk(clk),
   .r_clk(mclk),
   .reset(reset),
   .wr_en( w_data_valid_to_fifo ),
   .rd_en( w_empty_out ? 1'b0 : 1'b1 )
);




effect_mixer #( 
    .data_width(memory_d_width)
) effect_mixer (
    .sw(sw),
    .clk(clk),
    .reset(reset),
    .i_fifo_full(w_full_out),
    .o_read_done(o_read_done),
    .o_read_ready(o_read_ready),
    .o_data(w_data_to_fifo),
    .o_data_valid(w_data_valid_to_fifo),
    .i_dv_from_eff(i_dv_from_eff),
    .i_data_from_eff_sw0(i_data_from_eff_sw0),
    .i_data_from_eff_sw1(i_data_from_eff_sw1) 
);




endmodule
module effect_controler #( parameter
    d_width = 24,
    address_width = 4,
    ram_depth = 16,
    memory_d_width = 16
)(
    input                               mclk,
    input                               clk,
    input                               reset,
    input   signed      [d_width-1: 0]  i_l_data,
    input   signed      [d_width-1: 0]  i_r_data,
    output  signed      [d_width-1: 0]  o_l_data,
    output  signed      [d_width-1: 0]  o_r_data,

    output                                      o_read_done,
    output                                      o_read_ready,


    input               [1:0]           sw,

    output  signed      [memory_d_width-1: 0]   o_data_to_eff,
    output                                      o_data_valid,
    input                                       i_read_enable,
    input  signed      [memory_d_width-1: 0]    i_data_from_eff_sw0,
    input  signed      [memory_d_width-1: 0]    i_data_from_eff_sw1,

    input                                       i_dv_from_eff
     
);


wire signed [memory_d_width-1: 0]  w_o_data;



wire                            w_empty_in, w_full_in;
wire                            w_empty_out, w_full_out;

wire  [memory_d_width-1:0]       w_data_to_fifo;

wire  [address_width-1:0]       w_data_fill_input;
wire  [address_width-1:0]       w_data_fill_output;

wire                            w_data_valid_to_fifo;

assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data;
assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data;

assign o_data_valid = ~w_empty_in;


sync_fifo #( 
   .ram_depth(ram_depth),
   .address_width(address_width),
   .data_width(memory_d_width)
) fifo_input (
   .data_out(o_data_to_eff),
   .full(w_full_in),
   .empty(w_empty_in),
   .data_fill(w_data_fill_input),
   .data_in(i_l_data[ d_width-1 : d_width - memory_d_width ]),       
   .w_clk(mclk),
   .r_clk(clk),
   .reset(reset),
   .wr_en( w_full_in  ? 1'b0 : 1'b1 ),
   .rd_en( w_empty_in ? 1'b0 : i_read_enable )
);


sync_fifo #( 
   .ram_depth(ram_depth),
   .address_width(address_width),
   .data_width(memory_d_width)
) fifo_output (
   .data_out(w_o_data),
   .full(w_full_out),
   .empty(w_empty_out),
   .data_fill(w_data_fill),
   .data_in(w_data_to_fifo),       
   .w_clk(clk),
   .r_clk(mclk),
   .reset(reset),
   .wr_en( w_data_valid_to_fifo ),
   .rd_en( w_empty_out ? 1'b0 : 1'b1 )
);




effect_mixer #( 
    .data_width(memory_d_width)
) effect_mixer (
    .sw(sw),
    .clk(clk),
    .reset(reset),
    .i_fifo_full(w_full_out),
    .o_read_done(o_read_done),
    .o_read_ready(o_read_ready),
    .o_data(w_data_to_fifo),
    .o_data_valid(w_data_valid_to_fifo),
    .i_dv_from_eff(i_dv_from_eff),
    .i_data_from_eff_sw0(i_data_from_eff_sw0),
    .i_data_from_eff_sw1(i_data_from_eff_sw1) 
);




endmodule