data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/fake_hilbert.v
 line:29: before: "="
data/verilator_xmls/7a58346b-c219-4de4-bb76-234283e2c536.xml
module fake_hilbert
  #( parameter WIDTH = 24,
     parameter MSB   = WIDTH-1,
     parameter TICKS = 12,
     parameter TBITS = 4,
     parameter TSB   = TBITS-1,
     parameter DELAY = 3)
   (

    input          clock_i,
    input          reset_i,


    input          enable_i,
    input          strobe_i,
    input [MSB:0]  signal_i,


    output         locked_o,
    output         strobe_o,
    output         framed_o,

    output [MSB:0] sig_re_o,
    output [MSB:0] sig_im_o
    );


   reg [MSB:0]     sig_imag = {WIDTH{1'b0}};
   reg             enable = 1'b0, starts = 1'b0;





   assign locked_o = enable;
   assign strobe_o = strobe_i;
   assign framed_o = starts;

   assign sig_re_o = signal_i;
   assign sig_im_o = sig_imag;





   always @(posedge clock_i)
     if (reset_i)
       enable <= #DELAY 1'b0;
     else if (strobe_i)
       enable <= #DELAY enable_i;
     else
       enable <= #DELAY enable;



   always @(posedge clock_i)
     if (enable_i)
       starts <= #DELAY strobe_i;



   always @(posedge clock_i)
     if (enable_i && strobe_i)
       sig_imag <= #DELAY signal_i;


endmodule
module fake_hilbert
  #( parameter WIDTH = 24,
     parameter MSB   = WIDTH-1,
     parameter TICKS = 12,
     parameter TBITS = 4,
     parameter TSB   = TBITS-1,
     parameter DELAY = 3)
   (

    input          clock_i,
    input          reset_i,


    input          enable_i,
    input          strobe_i,
    input [MSB:0]  signal_i,


    output         locked_o,
    output         strobe_o,
    output         framed_o,

    output [MSB:0] sig_re_o,
    output [MSB:0] sig_im_o
    );



   reg [MSB:0]     sig_imag = {WIDTH{1'b0}};
   reg             enable = 1'b0, starts = 1'b0;





   assign locked_o = enable;
   assign strobe_o = strobe_i;
   assign framed_o = starts;

   assign sig_re_o = signal_i;
   assign sig_im_o = sig_imag;





   always @(posedge clock_i)
     if (reset_i)
       enable <= #DELAY 1'b0;
     else if (strobe_i)
       enable <= #DELAY enable_i;
     else
       enable <= #DELAY enable;



   always @(posedge clock_i)
     if (enable_i)
       starts <= #DELAY strobe_i;



   always @(posedge clock_i)
     if (enable_i && strobe_i)
       sig_imag <= #DELAY signal_i;


endmodule