data/full_repos/permissive/104784866/CLB/Verilog/src/AsyncRAM.v
data/verilator_xmls/e52a8eed-7e58-4182-b656-6ff0e8222691.xml
module AsyncRAM#(
		parameter ADDR_WIDTH = 4,
		parameter DATA_WIDTH = 4
	) (
		clk,
		addr,
		rw,
		data_in,
		data_out
	);

	input clk;
	input [ADDR_WIDTH-1:0] addr;
	input rw;
	input [DATA_WIDTH-1:0] data_in;
	output [DATA_WIDTH-1:0] data_out;


	(* ramstyle = "MLAB, no_rw_check" *)
	reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1];

	assign data_out = mem[addr];

	always @(posedge clk) begin
		if(rw)
			mem[addr] = data_in;
	end

endmodule
module AsyncRAM#(
		parameter ADDR_WIDTH = 4,
		parameter DATA_WIDTH = 4
	) (
		clk,
		addr,
		rw,
		data_in,
		data_out
	);


	input clk;
	input [ADDR_WIDTH-1:0] addr;
	input rw;
	input [DATA_WIDTH-1:0] data_in;
	output [DATA_WIDTH-1:0] data_out;


	(* ramstyle = "MLAB, no_rw_check" *)
	reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1];

	assign data_out = mem[addr];

	always @(posedge clk) begin
		if(rw)
			mem[addr] = data_in;
	end

endmodule