data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/lfsr_sink.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/lfsr_sink.v:51: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module lfsr_sink #(
  parameter DataBits       = 8,
  parameter RepeatDefault  = 0,
  parameter PatternDefault = 0,
  parameter CountBits      = 32,
  parameter LfsrSeed       = 17'h15555)
(

  input                 cfg_rst,
  input                 cfg_clk,
  input [4:0]           cfg_paddr,
  input                 cfg_pwrite,
  input [31:0]          cfg_pwdata,
  input                 cfg_psel,
  input                 cfg_penable,
  output                cfg_pready,
  output reg [31:0]     cfg_prdata,
  output                cfg_pslverr,

  input                 din_clk,
  input                 din_rst,
  input                 din_valid,
  output                din_ready,
  input [DataBits-1:0]  din_data,
  input                 din_eof
);
`include "util.vh"




  localparam  RxCountAddr    = 0,
              ErrCountAddr   = 1,
              ClrAddr        = 2,
              RepeatAddr     = 3,
              PatternAddr    = 4;




  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;

  reg [CountBits-1:0] rx_count, rx_count_r, rx_count_rr;
  reg [CountBits-1:0] err_count, err_count_r, err_count_rr;
  reg                 cfg_clr, cfg_repeat;
  reg [1:0]           cfg_pattern;

  always @(posedge cfg_clk) begin :cfg
    integer   addr_i;
    addr_i = cfg_paddr >> 2;

    if (cfg_psel && !cfg_penable) begin


      if (cfg_pwrite) begin
        case (addr_i)
          ClrAddr:     cfg_clr    <= cfg_pwdata[0];
          RepeatAddr:  cfg_repeat <= cfg_pwdata[0];
          PatternAddr:   cfg_pattern <= cfg_pwdata;
        endcase


      end else begin
        case (addr_i)
          RxCountAddr:  cfg_prdata <= rx_count_rr;
          ErrCountAddr: cfg_prdata <= err_count_rr;
          ClrAddr:      cfg_prdata <= cfg_clr;
          RepeatAddr:   cfg_prdata <= cfg_repeat;
          PatternAddr:  cfg_prdata <= cfg_pattern;
        endcase
      end
    end



    {rx_count_rr, rx_count_r}   <= {rx_count_r, rx_count};
    {err_count_rr, err_count_r} <= {err_count_r, err_count};

    if (cfg_rst) begin
      {rx_count_rr, rx_count_r}   <= 0;
      {err_count_rr, err_count_r} <= 0;
      cfg_clr                     <= 0;
      cfg_repeat                  <= RepeatDefault;
      cfg_pattern                 <= PatternDefault;
    end
  end




  localparam SumLatency = 1 + clog2(DataBits) - 2;

  wire [DataBits-1:0]      pattern_data;
  reg                      clr_r, clr_rr;
  reg                      repeat_r, repeat_rr;
  reg [SumLatency:0]       valid_pipe;
  reg [DataBits-1:0]       errs_xor;
  wire [clog2(DataBits+1)-1:0] errs;

  assign din_ready = 1;


  sum_bits #(
    .InBits(DataBits))
  sum_errs (
    .clk  (din_clk),
    .en   (1'b1),
    .bits (errs_xor),
    .sum  (errs));

  always @(posedge din_clk) begin


    {clr_rr, clr_r}       <= {clr_r, cfg_clr};
    {repeat_rr, repeat_r} <= {repeat_r, cfg_repeat};


    if (din_valid) begin
      errs_xor <= din_data ^ pattern_data;
    end


    valid_pipe <= {valid_pipe, din_valid};

    if (valid_pipe[SumLatency]) begin
      err_count <= err_count + errs;
      rx_count  <= rx_count + 1;
    end

    if (clr_rr) begin
      rx_count   <= 0;
      err_count  <= 0;
    end

    if (din_rst) begin
      rx_count   <= 0;
      err_count  <= 0;
      {clr_rr, clr_r} <= 0;
    end

  end




  wire                lfsr_shift, lfsr_init;
  wire [DataBits-1:0] lfsr_data;

  lfsr17_shift #(
    .DataBits (DataBits),
    .LfsrSeed (LfsrSeed))
  lfsr (
    .clk       (din_clk),
    .rst       (din_rst | clr_rr),
    .seed      (LfsrSeed),
    .init      (lfsr_init),
    .shift     (lfsr_shift),
    .lfsr_data (lfsr_data)
    );


  assign lfsr_init  = din_valid & din_eof & repeat_rr;


  assign lfsr_shift = din_valid;




  reg [DataBits-1:0] count_data;
  always @(posedge din_clk) begin
    if (din_valid) begin
      count_data <= (din_eof & repeat_rr) ? 0 : count_data + 1;
    end
    if (din_rst | clr_rr) begin
      count_data <= 0;
    end
  end

  assign pattern_data = (cfg_pattern == 0) ? lfsr_data        :
                        (cfg_pattern == 1) ? count_data       :
                        (cfg_pattern == 2) ? {DataBits{1'b1}} : 0;
endmodule
module lfsr_sink #(
  parameter DataBits       = 8,
  parameter RepeatDefault  = 0,
  parameter PatternDefault = 0,
  parameter CountBits      = 32,
  parameter LfsrSeed       = 17'h15555)
(

  input                 cfg_rst,
  input                 cfg_clk,
  input [4:0]           cfg_paddr,
  input                 cfg_pwrite,
  input [31:0]          cfg_pwdata,
  input                 cfg_psel,
  input                 cfg_penable,
  output                cfg_pready,
  output reg [31:0]     cfg_prdata,
  output                cfg_pslverr,

  input                 din_clk,
  input                 din_rst,
  input                 din_valid,
  output                din_ready,
  input [DataBits-1:0]  din_data,
  input                 din_eof
);

`include "util.vh"




  localparam  RxCountAddr    = 0,
              ErrCountAddr   = 1,
              ClrAddr        = 2,
              RepeatAddr     = 3,
              PatternAddr    = 4;




  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;

  reg [CountBits-1:0] rx_count, rx_count_r, rx_count_rr;
  reg [CountBits-1:0] err_count, err_count_r, err_count_rr;
  reg                 cfg_clr, cfg_repeat;
  reg [1:0]           cfg_pattern;

  always @(posedge cfg_clk) begin :cfg
    integer   addr_i;
    addr_i = cfg_paddr >> 2;

    if (cfg_psel && !cfg_penable) begin


      if (cfg_pwrite) begin
        case (addr_i)
          ClrAddr:     cfg_clr    <= cfg_pwdata[0];
          RepeatAddr:  cfg_repeat <= cfg_pwdata[0];
          PatternAddr:   cfg_pattern <= cfg_pwdata;
        endcase


      end else begin
        case (addr_i)
          RxCountAddr:  cfg_prdata <= rx_count_rr;
          ErrCountAddr: cfg_prdata <= err_count_rr;
          ClrAddr:      cfg_prdata <= cfg_clr;
          RepeatAddr:   cfg_prdata <= cfg_repeat;
          PatternAddr:  cfg_prdata <= cfg_pattern;
        endcase
      end
    end



    {rx_count_rr, rx_count_r}   <= {rx_count_r, rx_count};
    {err_count_rr, err_count_r} <= {err_count_r, err_count};

    if (cfg_rst) begin
      {rx_count_rr, rx_count_r}   <= 0;
      {err_count_rr, err_count_r} <= 0;
      cfg_clr                     <= 0;
      cfg_repeat                  <= RepeatDefault;
      cfg_pattern                 <= PatternDefault;
    end
  end




  localparam SumLatency = 1 + clog2(DataBits) - 2;

  wire [DataBits-1:0]      pattern_data;
  reg                      clr_r, clr_rr;
  reg                      repeat_r, repeat_rr;
  reg [SumLatency:0]       valid_pipe;
  reg [DataBits-1:0]       errs_xor;
  wire [clog2(DataBits+1)-1:0] errs;

  assign din_ready = 1;


  sum_bits #(
    .InBits(DataBits))
  sum_errs (
    .clk  (din_clk),
    .en   (1'b1),
    .bits (errs_xor),
    .sum  (errs));

  always @(posedge din_clk) begin


    {clr_rr, clr_r}       <= {clr_r, cfg_clr};
    {repeat_rr, repeat_r} <= {repeat_r, cfg_repeat};


    if (din_valid) begin
      errs_xor <= din_data ^ pattern_data;
    end


    valid_pipe <= {valid_pipe, din_valid};

    if (valid_pipe[SumLatency]) begin
      err_count <= err_count + errs;
      rx_count  <= rx_count + 1;
    end

    if (clr_rr) begin
      rx_count   <= 0;
      err_count  <= 0;
    end

    if (din_rst) begin
      rx_count   <= 0;
      err_count  <= 0;
      {clr_rr, clr_r} <= 0;
    end

  end




  wire                lfsr_shift, lfsr_init;
  wire [DataBits-1:0] lfsr_data;

  lfsr17_shift #(
    .DataBits (DataBits),
    .LfsrSeed (LfsrSeed))
  lfsr (
    .clk       (din_clk),
    .rst       (din_rst | clr_rr),
    .seed      (LfsrSeed),
    .init      (lfsr_init),
    .shift     (lfsr_shift),
    .lfsr_data (lfsr_data)
    );


  assign lfsr_init  = din_valid & din_eof & repeat_rr;


  assign lfsr_shift = din_valid;




  reg [DataBits-1:0] count_data;
  always @(posedge din_clk) begin
    if (din_valid) begin
      count_data <= (din_eof & repeat_rr) ? 0 : count_data + 1;
    end
    if (din_rst | clr_rr) begin
      count_data <= 0;
    end
  end

  assign pattern_data = (cfg_pattern == 0) ? lfsr_data        :
                        (cfg_pattern == 1) ? count_data       :
                        (cfg_pattern == 2) ? {DataBits{1'b1}} : 0;
endmodule