data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v
1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                         ^~~~~~\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                               ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                      ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                 ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                            ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                       ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                                  ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                                             ^\n%Error: Exiting due to 8 warning(s)\n'
module _74LS163(
input CP,
input CR_n,
input LD_n,
input EP,
input ET,
input [3:0] D,
output reg [3:0] Q
);

always@(posedge CP)
begin
if(~CR_n) Q<=0;
else if(~LD_n) Q<=D;
else if(LD_n && EP && ET) Q<=Q+1;
end

endmodule
module _74LS163(
input CP,
input CR_n,
input LD_n,
input EP,
input ET,
input [3:0] D,
output reg [3:0] Q
);


always@(posedge CP)
begin
if(~CR_n) Q<=0;
else if(~LD_n) Q<=D;
else if(LD_n && EP && ET) Q<=Q+1;
end

endmodule