data/full_repos/permissive/212897440/i2s_receiver.v
data/verilator_xmls/e692ea6e-6b0a-4828-bf59-dc8e8b2f7229.xml
module i2s_receicer #( parameter
    sclk_ws_ratio = 64,
    mclk_sclk_ratio = 4,
    d_width = 24
)(
    input  reset_n,
    input  mclk,
    output sclk,
    output ws,
    input  sd_rx,
    output reg signed [d_width-1: 0] l_data_rx,
    output reg signed [d_width-1: 0] r_data_rx
    
    );

reg sclk_int = 0;
reg ws_int = 0;
reg signed [d_width-1: 0] l_data_rx_int = 'sb0;
reg signed [d_width-1: 0] r_data_rx_int = 'sb0;



reg [3: 0] sclk_cnt = 0;
reg [7: 0] ws_cnt   = 0;



always@(posedge mclk, posedge reset_n) begin

    if (reset_n == 1) begin
        sclk_cnt <= 'b0;
        ws_cnt <= 'b0;
        sclk_int <= 0;
        ws_int <= 0;
        l_data_rx_int <= 'sb0;
        r_data_rx_int <= 'sb0;
    end
    else begin
        if (sclk_cnt < mclk_sclk_ratio/2-1) begin
            sclk_cnt <= sclk_cnt + 1;
        end
        else begin
            sclk_cnt <= 0;
            sclk_int <= ~sclk_int;
            if (ws_cnt < sclk_ws_ratio - 1) begin
                ws_cnt <= ws_cnt + 1;
                if (sclk_int == 0 && ws_cnt > 1 && ws_cnt < d_width * 2 + 2) begin
                    if (ws_int == 1) begin
                        r_data_rx_int <= {r_data_rx_int[d_width-2 : 0] , sd_rx};
                    end else begin
                        l_data_rx_int <= {l_data_rx_int[d_width-2 : 0] , sd_rx};
                    end
                end   

                
            end else begin
                ws_cnt <= 0;
                ws_int <= ~ws_int;
                r_data_rx <= r_data_rx_int;
                l_data_rx <= l_data_rx_int;
            end
        end
    end
end

assign sclk = sclk_int;
assign ws = ws_int;

endmodule
module i2s_receicer #( parameter
    sclk_ws_ratio = 64,
    mclk_sclk_ratio = 4,
    d_width = 24
)(
    input  reset_n,
    input  mclk,
    output sclk,
    output ws,
    input  sd_rx,
    output reg signed [d_width-1: 0] l_data_rx,
    output reg signed [d_width-1: 0] r_data_rx
    
    );


reg sclk_int = 0;
reg ws_int = 0;
reg signed [d_width-1: 0] l_data_rx_int = 'sb0;
reg signed [d_width-1: 0] r_data_rx_int = 'sb0;



reg [3: 0] sclk_cnt = 0;
reg [7: 0] ws_cnt   = 0;



always@(posedge mclk, posedge reset_n) begin

    if (reset_n == 1) begin
        sclk_cnt <= 'b0;
        ws_cnt <= 'b0;
        sclk_int <= 0;
        ws_int <= 0;
        l_data_rx_int <= 'sb0;
        r_data_rx_int <= 'sb0;
    end
    else begin
        if (sclk_cnt < mclk_sclk_ratio/2-1) begin
            sclk_cnt <= sclk_cnt + 1;
        end
        else begin
            sclk_cnt <= 0;
            sclk_int <= ~sclk_int;
            if (ws_cnt < sclk_ws_ratio - 1) begin
                ws_cnt <= ws_cnt + 1;
                if (sclk_int == 0 && ws_cnt > 1 && ws_cnt < d_width * 2 + 2) begin
                    if (ws_int == 1) begin
                        r_data_rx_int <= {r_data_rx_int[d_width-2 : 0] , sd_rx};
                    end else begin
                        l_data_rx_int <= {l_data_rx_int[d_width-2 : 0] , sd_rx};
                    end
                end   

                
            end else begin
                ws_cnt <= 0;
                ws_int <= ~ws_int;
                r_data_rx <= r_data_rx_int;
                l_data_rx <= l_data_rx_int;
            end
        end
    end
end

assign sclk = sclk_int;
assign ws = ws_int;

endmodule