data/full_repos/permissive/159244411/src/jive_csr.v
data/verilator_xmls/127cfa4b-2cc0-405b-9183-129f69e7d6af.xml
module jive_csr
(
    input         rst,
    input         clk,
    
    input         msw_sel,
    input         csr_rd,
    input         csr_wr,
    input   [5:0] csr_idx,
    input  [15:0] csr_wdata,
    output [15:0] csr_rdata,
    
    input         ext_int,
    input         tmr_int,
    input         sft_int,
    output  [2:0] csr_mip,
    
    input         em_ena,
    input         mret_d,
    output        glb_int
);



    reg [63:0] r_csr_mcycle;
    reg  [2:0] r_csr_mie;
    reg  [2:0] r_csr_mip;
    reg        r_isr_on;
    
    always @ (posedge rst or posedge clk) begin : CSR_WRITE
        reg [3:1] v_inc;
    
        if (rst) begin
            r_csr_mcycle <= 64'd0;
            r_csr_mie    <= 3'b000;
            r_csr_mip    <= 3'b000;
            r_isr_on     <= 1'b0;

        end
        else begin
            if (csr_wr & ~msw_sel) begin
                if (csr_idx == 6'b01_0100) begin
                    r_csr_mie[0] <= csr_wdata[3];
                    r_csr_mie[1] <= csr_wdata[7];
                    r_csr_mie[2] <= csr_wdata[11];
                end
            end
            
            r_csr_mip[2] <= ext_int & r_csr_mie[2];
            r_csr_mip[1] <= tmr_int & r_csr_mie[1];
            r_csr_mip[0] <= sft_int & r_csr_mie[0];
            
            r_isr_on <= (r_isr_on | em_ena) & ~mret_d;
            
            r_csr_mcycle <= r_csr_mcycle + 64'd1;

        end
    end
    
    assign csr_mip = r_csr_mip;
    assign glb_int = (|r_csr_mip) & ~r_isr_on;


    
    reg  [15:0] r_csr_rdata;
    
    wire [15:0] w_csr_mie = { 4'b0, r_csr_mie[2], 3'b0, r_csr_mie[1], 3'b0, r_csr_mie[0], 3'b0 };
    wire [15:0] w_csr_mip = { 4'b0, r_csr_mip[2], 3'b0, r_csr_mip[1], 3'b0, r_csr_mip[0], 3'b0 };
    
    always @ (posedge rst or posedge clk) begin : CSR_READ
    
        if (rst) begin
            r_csr_rdata <= 16'h0000;
        end
        else begin
            if (csr_rd) begin
                case ({ csr_idx, msw_sel })

                    7'b01_0100_0 : r_csr_rdata <= w_csr_mie[15:0];

                    7'b01_1100_0 : r_csr_rdata <= w_csr_mip[15:0];

                    7'b10_0000_0 : r_csr_rdata <= r_csr_mcycle[15: 0];
                    7'b10_0000_1 : r_csr_rdata <= r_csr_mcycle[31:16];

                    7'b10_1000_0 : r_csr_rdata <= r_csr_mcycle[47:32];
                    7'b10_1000_1 : r_csr_rdata <= r_csr_mcycle[63:48];
                    default      : r_csr_rdata <= 16'h0000;
                endcase
            end
            else begin
                r_csr_rdata <= 16'h0000;
            end
        end
    end
    
    assign csr_rdata = r_csr_rdata;
    
endmodule
module jive_csr
(
    input         rst,
    input         clk,
    
    input         msw_sel,
    input         csr_rd,
    input         csr_wr,
    input   [5:0] csr_idx,
    input  [15:0] csr_wdata,
    output [15:0] csr_rdata,
    
    input         ext_int,
    input         tmr_int,
    input         sft_int,
    output  [2:0] csr_mip,
    
    input         em_ena,
    input         mret_d,
    output        glb_int
);




    reg [63:0] r_csr_mcycle;
    reg  [2:0] r_csr_mie;
    reg  [2:0] r_csr_mip;
    reg        r_isr_on;
    
    always @ (posedge rst or posedge clk) begin : CSR_WRITE
        reg [3:1] v_inc;
    
        if (rst) begin
            r_csr_mcycle <= 64'd0;
            r_csr_mie    <= 3'b000;
            r_csr_mip    <= 3'b000;
            r_isr_on     <= 1'b0;

        end
        else begin
            if (csr_wr & ~msw_sel) begin
                if (csr_idx == 6'b01_0100) begin
                    r_csr_mie[0] <= csr_wdata[3];
                    r_csr_mie[1] <= csr_wdata[7];
                    r_csr_mie[2] <= csr_wdata[11];
                end
            end
            
            r_csr_mip[2] <= ext_int & r_csr_mie[2];
            r_csr_mip[1] <= tmr_int & r_csr_mie[1];
            r_csr_mip[0] <= sft_int & r_csr_mie[0];
            
            r_isr_on <= (r_isr_on | em_ena) & ~mret_d;
            
            r_csr_mcycle <= r_csr_mcycle + 64'd1;

        end
    end
    
    assign csr_mip = r_csr_mip;
    assign glb_int = (|r_csr_mip) & ~r_isr_on;


    
    reg  [15:0] r_csr_rdata;
    
    wire [15:0] w_csr_mie = { 4'b0, r_csr_mie[2], 3'b0, r_csr_mie[1], 3'b0, r_csr_mie[0], 3'b0 };
    wire [15:0] w_csr_mip = { 4'b0, r_csr_mip[2], 3'b0, r_csr_mip[1], 3'b0, r_csr_mip[0], 3'b0 };
    
    always @ (posedge rst or posedge clk) begin : CSR_READ
    
        if (rst) begin
            r_csr_rdata <= 16'h0000;
        end
        else begin
            if (csr_rd) begin
                case ({ csr_idx, msw_sel })

                    7'b01_0100_0 : r_csr_rdata <= w_csr_mie[15:0];

                    7'b01_1100_0 : r_csr_rdata <= w_csr_mip[15:0];

                    7'b10_0000_0 : r_csr_rdata <= r_csr_mcycle[15: 0];
                    7'b10_0000_1 : r_csr_rdata <= r_csr_mcycle[31:16];

                    7'b10_1000_0 : r_csr_rdata <= r_csr_mcycle[47:32];
                    7'b10_1000_1 : r_csr_rdata <= r_csr_mcycle[63:48];
                    default      : r_csr_rdata <= 16'h0000;
                endcase
            end
            else begin
                r_csr_rdata <= 16'h0000;
            end
        end
    end
    
    assign csr_rdata = r_csr_rdata;
    
endmodule