data/full_repos/permissive/174263347/crtv10/hdl/crt_cookie.v
1: b'%Warning-WIDTH: data/full_repos/permissive/174263347/crtv10/hdl/crt_cookie.v:32: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'3\'h0\' generates 3 bits.\n                                                                               : ... In instance crt_cookie\n                case (delay[7:3])\n                ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/174263347/crtv10/hdl/crt_cookie.v:32: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'3\'h1\' generates 3 bits.\n                                                                               : ... In instance crt_cookie\n                case (delay[7:3])\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/174263347/crtv10/hdl/crt_cookie.v:32: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'3\'h2\' generates 3 bits.\n                                                                               : ... In instance crt_cookie\n                case (delay[7:3])\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/174263347/crtv10/hdl/crt_cookie.v:32: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'3\'h3\' generates 3 bits.\n                                                                               : ... In instance crt_cookie\n                case (delay[7:3])\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/174263347/crtv10/hdl/crt_cookie.v:32: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                               : ... In instance crt_cookie\n                case (delay[7:3])\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/174263347/crtv10/hdl/crt_cookie.v:32: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                               : ... In instance crt_cookie\n                case (delay[7:3])\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/174263347/crtv10/hdl/crt_cookie.v:32: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n                                                                               : ... In instance crt_cookie\n                case (delay[7:3])\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/174263347/crtv10/hdl/crt_cookie.v:32: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n                                                                               : ... In instance crt_cookie\n                case (delay[7:3])\n                ^~~~\n%Error: Exiting due to 8 warning(s)\n'
module  crt_cookie(clk, reset, ena, noice, test);

    input   clk, reset, ena, noice;
    output  test;

    reg     [11:0]   delay;
    reg             noicereg;
    
    always @ (posedge reset or posedge clk)
        if (reset)
            delay <= 0;
        else if(ena)
            delay <= delay + 1;

    always @ (posedge reset or posedge clk)
        if (reset)
            noicereg <= 0;
        else if(ena)
            if(delay[11:0] == 12'b1011_0110_1XXX)
                case (delay[7:3])
                    3'b000 : noicereg  <= 1;
                    3'b001 : noicereg  <= 0;
                    3'b010 : noicereg  <= 1;
                    3'b011 : noicereg  <= 1;
                    3'b100 : noicereg  <= 0;
                    3'b101 : noicereg  <= 0;
                    3'b110 : noicereg  <= 1;
                    3'b111 : noicereg  <= 0;
                endcase        
            else
                noicereg <= noice;

    assign test = noicereg;

endmodule
module  crt_cookie(clk, reset, ena, noice, test);


    input   clk, reset, ena, noice;
    output  test;

    reg     [11:0]   delay;
    reg             noicereg;
    
    always @ (posedge reset or posedge clk)
        if (reset)
            delay <= 0;
        else if(ena)
            delay <= delay + 1;

    always @ (posedge reset or posedge clk)
        if (reset)
            noicereg <= 0;
        else if(ena)
            if(delay[11:0] == 12'b1011_0110_1XXX)
                case (delay[7:3])
                    3'b000 : noicereg  <= 1;
                    3'b001 : noicereg  <= 0;
                    3'b010 : noicereg  <= 1;
                    3'b011 : noicereg  <= 1;
                    3'b100 : noicereg  <= 0;
                    3'b101 : noicereg  <= 0;
                    3'b110 : noicereg  <= 1;
                    3'b111 : noicereg  <= 0;
                endcase        
            else
                noicereg <= noice;

    assign test = noicereg;

endmodule