data/full_repos/permissive/135852214/Verilog/register12bit.v
data/verilator_xmls/bc6e83ca-61ea-45a3-af00-f24ecf79c3ee.xml
module register12bit(
    input [11:0] data_in,
    output reg[11:0] data_out,
    input wr_e,
    input clr,
    input clk
    );

always @(posedge clk, posedge clr)
begin
	if(clr)
		data_out <= 12'b000000000000;
	else if(wr_e)
		data_out <= data_in;
end

endmodule
module register12bit(
    input [11:0] data_in,
    output reg[11:0] data_out,
    input wr_e,
    input clr,
    input clk
    );


always @(posedge clk, posedge clr)
begin
	if(clr)
		data_out <= 12'b000000000000;
	else if(wr_e)
		data_out <= data_in;
end

endmodule