data/full_repos/permissive/174546493/dispatch2.v
data/verilator_xmls/b43a3d93-a9cf-4059-81df-4a1a0a60199c.xml
module dispatch2(opcode,funct,next_state_DT2);

input[5:0] funct;
input[5:0] opcode;
output reg[4:0] next_state_DT2;

always@(*)
begin
if(opcode == 6'b000000)
begin
	case(funct)
	6'b011010 : next_state_DT2 = 5'd20;
	6'b000101 : next_state_DT2 = 5'd21;
	6'b011000 : next_state_DT2 = 5'd20;
	6'b000110 : next_state_DT2 = 5'd22;
	endcase
end

else
begin
	case(opcode)
	6'b101011 : next_state_DT2 = 5'd24;
	6'b001000 : next_state_DT2 = 5'd25;
	6'b001101 : next_state_DT2 = 5'd25;
	6'b100011 : next_state_DT2 = 5'd23;
	endcase
end

end
endmodule
module dispatch2(opcode,funct,next_state_DT2);


input[5:0] funct;
input[5:0] opcode;
output reg[4:0] next_state_DT2;

always@(*)
begin
if(opcode == 6'b000000)
begin
	case(funct)
	6'b011010 : next_state_DT2 = 5'd20;
	6'b000101 : next_state_DT2 = 5'd21;
	6'b011000 : next_state_DT2 = 5'd20;
	6'b000110 : next_state_DT2 = 5'd22;
	endcase
end

else
begin
	case(opcode)
	6'b101011 : next_state_DT2 = 5'd24;
	6'b001000 : next_state_DT2 = 5'd25;
	6'b001101 : next_state_DT2 = 5'd25;
	6'b100011 : next_state_DT2 = 5'd23;
	endcase
end

end
endmodule