data/full_repos/permissive/133819542/test/inst_load_store_test.v
 line:392: before: "#"
1: b'%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:2: Cannot find include file: ../test/assert.v\n`include "../test/assert.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133819542/test,data/full_repos/permissive/133819542/../test/assert.v\n             data/full_repos/permissive/133819542/test,data/full_repos/permissive/133819542/../test/assert.v.v\n             data/full_repos/permissive/133819542/test,data/full_repos/permissive/133819542/../test/assert.v.sv\n             ../test/assert.v\n             ../test/assert.v.v\n             ../test/assert.v.sv\n             obj_dir/../test/assert.v\n             obj_dir/../test/assert.v.v\n             obj_dir/../test/assert.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:10: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:15: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("../test/inst_load_store_test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:16: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[1]);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:18: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[3]);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #20 rst = 0;\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:25: Define or directive not defined: \'`AR\'\n        #12 `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000EEFF);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:25: syntax error, unexpected \',\'\n        #12 `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000EEFF);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #12 `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000EEFF);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:25: Define or directive not defined: \'`AR\'\n        #12 `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000EEFF);\n                                ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:25: syntax error, unexpected \',\'\n        #12 `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000EEFF);\n                                     ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:26: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000EEFF);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:26: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000EEFF);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000EEFF);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:26: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000EEFF);\n                                ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:26: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000EEFF);\n                                     ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:27: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000EE);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:27: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000EE);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000EE);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:27: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000EE);\n                                ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:27: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000EE);\n                                     ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:28: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000EE);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:28: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000EE);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000EE);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:28: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000EE);\n                                ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:28: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000EE);\n                                     ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:29: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000CCDD);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:29: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000CCDD);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000CCDD);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:29: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000CCDD);\n                                ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:29: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000CCDD);\n                                     ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:30: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000CCDD);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:30: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000CCDD);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000CCDD);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:30: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000CCDD);\n                                ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:30: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h0000CCDD);\n                                     ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:31: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000CC);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:31: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000CC);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000CC);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:31: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000CC);\n                                ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:31: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000CC);\n                                     ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:32: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000CC);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:32: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000CC);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000CC);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:32: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000CC);\n                                ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:32: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hxxxxxxxx);`AR(3,32\'h000000CC);\n                                     ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:33: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hFFFFFFFF);`AR(3,32\'h000000CC);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:33: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hFFFFFFFF);`AR(3,32\'h000000CC);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(1,32\'hFFFFFFFF);`AR(3,32\'h000000CC);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:33: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'hFFFFFFFF);`AR(3,32\'h000000CC);\n                                ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:33: syntax error, unexpected \',\'\n        #2  `AR(1,32\'hFFFFFFFF);`AR(3,32\'h000000CC);\n                                     ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:34: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'h000000EE);`AR(3,32\'h000000CC);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:34: syntax error, unexpected \',\'\n        #2  `AR(1,32\'h000000EE);`AR(3,32\'h000000CC);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(1,32\'h000000EE);`AR(3,32\'h000000CC);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:34: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'h000000EE);`AR(3,32\'h000000CC);\n                                ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:34: syntax error, unexpected \',\'\n        #2  `AR(1,32\'h000000EE);`AR(3,32\'h000000CC);\n                                     ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:35: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'h000000EE);`AR(3,32\'h0000AABB);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:35: syntax error, unexpected \',\'\n        #2  `AR(1,32\'h000000EE);`AR(3,32\'h0000AABB);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_load_store_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(1,32\'h000000EE);`AR(3,32\'h0000AABB);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:35: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'h000000EE);`AR(3,32\'h0000AABB);\n                                ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:35: syntax error, unexpected \',\'\n        #2  `AR(1,32\'h000000EE);`AR(3,32\'h0000AABB);\n                                     ^\n%Error: data/full_repos/permissive/133819542/test/inst_load_store_test.v:36: Define or directive not defined: \'`AR\'\n        #2  `AR(1,32\'h000000EE);`AR(3,32\'h0000AABB);\n            ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module inst_load_store_test();
    reg     clk, rst;
    integer i  ;

    open_mips_min_sopc open_mips_min_sopc0 (clk,rst);

    always #1 clk = ~clk;
    wire [31:0] mem0x0000 = {open_mips_min_sopc0.data_ram0.bank3[0], open_mips_min_sopc0.data_ram0.bank2[0], open_mips_min_sopc0.data_ram0.bank1[0], open_mips_min_sopc0.data_ram0.bank0[0]};
    wire [31:0] mem0x0004 = {open_mips_min_sopc0.data_ram0.bank3[1], open_mips_min_sopc0.data_ram0.bank2[1], open_mips_min_sopc0.data_ram0.bank1[1], open_mips_min_sopc0.data_ram0.bank0[1]};
    wire [31:0] mem0x0008 = {open_mips_min_sopc0.data_ram0.bank3[2], open_mips_min_sopc0.data_ram0.bank2[2], open_mips_min_sopc0.data_ram0.bank1[2], open_mips_min_sopc0.data_ram0.bank0[2]};
    initial begin
        $dumpfile("../test/inst_load_store_test.vcd");
        $dumpvars;
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[1]);
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[3]);

        $readmemh("../data/inst_load_store_test.txt", open_mips_min_sopc0.inst_rom0.inst_mem, 0, 31);

        clk = 0;
        rst = 1;
        #20 rst = 0;
        #12 `AR(1,32'hxxxxxxxx);`AR(3,32'h0000EEFF);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h0000EEFF);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h000000EE);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h000000EE);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h0000CCDD);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h0000CCDD);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h000000CC);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h000000CC);
        #2  `AR(1,32'hFFFFFFFF);`AR(3,32'h000000CC);
        #2  `AR(1,32'h000000EE);`AR(3,32'h000000CC);
        #2  `AR(1,32'h000000EE);`AR(3,32'h0000AABB);
        #2  `AR(1,32'h000000EE);`AR(3,32'h0000AABB);
        #2  `AR(1,32'h0000AABB);`AR(3,32'h0000AABB);
        #2  `AR(1,32'hFFFFAABB);`AR(3,32'h0000AABB);
        #2  `AR(1,32'hFFFFAABB);`AR(3,32'h00008899);
        #2  `AR(1,32'hFFFFAABB);`AR(3,32'h00008899);
        #2  `AR(1,32'hFFFF8899);`AR(3,32'h00008899);
        #2  `AR(1,32'h00008899);`AR(3,32'h00008899);
        #2  `AR(1,32'h00008899);`AR(3,32'h00004455);
        #2  `AR(1,32'h00008899);`AR(3,32'h44550000);
        #2  `AR(1,32'h00008899);`AR(3,32'h44556677);
        #2  `AR(1,32'h00008899);`AR(3,32'h44556677);
        #2  `AR(1,32'h44556677);`AR(3,32'h44556677);
        #2  `AR(1,32'h44556677);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889977);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889977);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889944);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889944);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889944);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889944);`AR(3,32'h44556677);
        #2  `AR(1,32'h889944FF);`AR(3,32'h44556677);
        #2  `AR(1,32'hAABB88BB);`AR(3,32'h44556677);
        #40 `PASS(load & store instruction test);
    end

endmodule
module inst_load_store_test();

    reg     clk, rst;
    integer i  ;

    open_mips_min_sopc open_mips_min_sopc0 (clk,rst);

    always #1 clk = ~clk;
    wire [31:0] mem0x0000 = {open_mips_min_sopc0.data_ram0.bank3[0], open_mips_min_sopc0.data_ram0.bank2[0], open_mips_min_sopc0.data_ram0.bank1[0], open_mips_min_sopc0.data_ram0.bank0[0]};
    wire [31:0] mem0x0004 = {open_mips_min_sopc0.data_ram0.bank3[1], open_mips_min_sopc0.data_ram0.bank2[1], open_mips_min_sopc0.data_ram0.bank1[1], open_mips_min_sopc0.data_ram0.bank0[1]};
    wire [31:0] mem0x0008 = {open_mips_min_sopc0.data_ram0.bank3[2], open_mips_min_sopc0.data_ram0.bank2[2], open_mips_min_sopc0.data_ram0.bank1[2], open_mips_min_sopc0.data_ram0.bank0[2]};
    initial begin
        $dumpfile("../test/inst_load_store_test.vcd");
        $dumpvars;
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[1]);
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[3]);

        $readmemh("../data/inst_load_store_test.txt", open_mips_min_sopc0.inst_rom0.inst_mem, 0, 31);

        clk = 0;
        rst = 1;
        #20 rst = 0;
        #12 `AR(1,32'hxxxxxxxx);`AR(3,32'h0000EEFF);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h0000EEFF);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h000000EE);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h000000EE);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h0000CCDD);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h0000CCDD);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h000000CC);
        #2  `AR(1,32'hxxxxxxxx);`AR(3,32'h000000CC);
        #2  `AR(1,32'hFFFFFFFF);`AR(3,32'h000000CC);
        #2  `AR(1,32'h000000EE);`AR(3,32'h000000CC);
        #2  `AR(1,32'h000000EE);`AR(3,32'h0000AABB);
        #2  `AR(1,32'h000000EE);`AR(3,32'h0000AABB);
        #2  `AR(1,32'h0000AABB);`AR(3,32'h0000AABB);
        #2  `AR(1,32'hFFFFAABB);`AR(3,32'h0000AABB);
        #2  `AR(1,32'hFFFFAABB);`AR(3,32'h00008899);
        #2  `AR(1,32'hFFFFAABB);`AR(3,32'h00008899);
        #2  `AR(1,32'hFFFF8899);`AR(3,32'h00008899);
        #2  `AR(1,32'h00008899);`AR(3,32'h00008899);
        #2  `AR(1,32'h00008899);`AR(3,32'h00004455);
        #2  `AR(1,32'h00008899);`AR(3,32'h44550000);
        #2  `AR(1,32'h00008899);`AR(3,32'h44556677);
        #2  `AR(1,32'h00008899);`AR(3,32'h44556677);
        #2  `AR(1,32'h44556677);`AR(3,32'h44556677);
        #2  `AR(1,32'h44556677);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889977);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889977);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889944);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889944);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889944);`AR(3,32'h44556677);
        #2  `AR(1,32'hBB889944);`AR(3,32'h44556677);
        #2  `AR(1,32'h889944FF);`AR(3,32'h44556677);
        #2  `AR(1,32'hAABB88BB);`AR(3,32'h44556677);
        #40 `PASS(load & store instruction test);
    end

endmodule