data/full_repos/permissive/168395472/labs/06_rom/clk_div.v
data/verilator_xmls/9853de04-49b6-4726-a791-ac5508919f63.xml
module clk_div #(parameter X = 12)(
    input clk_in,

    output clk_out
);

reg [X-1:0]cnt = 0;

assign clk_out = cnt[X-1];

always @(posedge clk_in) begin
    cnt <= cnt + 1;
end

endmodule
module clk_div #(parameter X = 12)(
    input clk_in,

    output clk_out
);


reg [X-1:0]cnt = 0;

assign clk_out = cnt[X-1];

always @(posedge clk_in) begin
    cnt <= cnt + 1;
end

endmodule