data/full_repos/permissive/193669196/uartm/rtl/uartm_rx.v
1: b'%Error: data/full_repos/permissive/193669196/uartm/rtl/uartm_rx.v:32: Cannot find include file: uartm_params.v\n  `include "uartm_params.v" \n           ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193669196/uartm/rtl,data/full_repos/permissive/193669196/uartm_params.v\n             data/full_repos/permissive/193669196/uartm/rtl,data/full_repos/permissive/193669196/uartm_params.v.v\n             data/full_repos/permissive/193669196/uartm/rtl,data/full_repos/permissive/193669196/uartm_params.v.sv\n             uartm_params.v\n             uartm_params.v.v\n             uartm_params.v.sv\n             obj_dir/uartm_params.v\n             obj_dir/uartm_params.v.v\n             obj_dir/uartm_params.v.sv\n%Error: Exiting due to 1 error(s)\n'
module uartm_rx (

  input  wire        hclk,
  input  wire        hresetn,


  input  wire        hwrite,
  input  wire        hready,


  input  wire [31:0] uartm_baud,
  input  wire [31:0] uartm_ctl,


  input  wire        sample_data_bit,
  input  wire [7:0]  bit_cnt,
  input  wire [7:0]  uartm_dw,
  input  wire [7:0]  uartm_plw,


  input  wire        RX,

  output reg [31:0]  rx_reg,
  output reg [2:0]   rx_curr_st,
  output reg [2:0]   rx_nxt_st
);





  `include "uartm_params.v"


reg [2:0]   rx_prev_st;



   always @ (posedge hclk or negedge hresetn) begin
     if (hresetn == 1'b0) begin
       rx_reg = 32'b0;
     end
     else begin
       if ((sample_data_bit == 1'b1) && (bit_cnt <= uartm_dw)) begin
           rx_reg = {RX, rx_reg[31:1]};
       end
     end
   end
 












 
 always @* begin
   rx_nxt_st = rx_curr_st;
   case (rx_curr_st)
     RX_IDLE : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         if (uartm_ctl[1:0] == 2'b10) begin
           rx_nxt_st = RX_CHECK;
         end
         else begin
           rx_nxt_st = RX_WAIT1;
         end
       end
     end
     RX_CHECK : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         if (uartm_ctl[1:0] == 2'b10) begin
           if (hwrite == 1'b1) begin
             rx_nxt_st = RX_WRITE;
           end 
           else begin
             rx_nxt_st = RX_READ;
           end
         end
         else begin
           rx_nxt_st = RX_WAIT1;
         end
       end
     end
     RX_WAIT1 : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         if (uartm_ctl[1:0] == 2'b01) begin
           if (rx_prev_st == RX_IDLE) begin
             rx_nxt_st = RX_CHECK;
           end
           else if (rx_prev_st == RX_CHECK) begin
             if (hwrite == 1'b1) begin
               rx_nxt_st = RX_WRITE;
             end 
             else begin
               rx_nxt_st = RX_READ;
             end
           end
           else if (rx_prev_st == RX_WRITE) begin
             rx_nxt_st = RX_WDATA;
           end
           else begin
             rx_nxt_st = RX_IDLE;
           end
         end
         else begin
           rx_nxt_st = RX_WAIT2;
         end
       end
     end
     RX_WAIT2 : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         rx_nxt_st = RX_WAIT3;
       end
     end
     RX_WAIT3 : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         if (rx_prev_st == RX_IDLE) begin
           rx_nxt_st = RX_CHECK;
         end
         else if (rx_prev_st == RX_CHECK) begin
           if (hwrite == 1'b1) begin
             rx_nxt_st = RX_WRITE;
           end 
           else begin
             rx_nxt_st = RX_READ;
           end
         end
         else if (rx_prev_st == RX_WRITE) begin
           rx_nxt_st = RX_WDATA;
         end
       end
     end
     RX_READ : begin
         rx_nxt_st = RX_IDLE;
     end
     RX_WRITE : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         if (uartm_ctl[1:0] == 2'b10) begin
           rx_nxt_st = RX_WDATA;
         end
         else begin
           rx_nxt_st = RX_WAIT1;
         end
       end
     end
     RX_WDATA : begin
         rx_nxt_st = RX_IDLE;
     end
     default : begin
       rx_nxt_st = RX_IDLE;
     end
   endcase
 end

 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     rx_curr_st <= 3'b0;
   end
   else begin
     rx_curr_st <= rx_nxt_st;
   end
 end
 
 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     rx_prev_st <= 3'b0;
   end
   else begin
     if ((rx_curr_st == RX_IDLE) && (rx_nxt_st != RX_IDLE)) begin
       rx_prev_st <= RX_IDLE;
     end
     else if ((rx_curr_st == RX_CHECK) && (rx_nxt_st != RX_CHECK)) begin
       rx_prev_st <= RX_CHECK;
     end
     else if ((rx_curr_st == RX_READ) && (rx_nxt_st != RX_READ)) begin
       rx_prev_st <= RX_READ;
     end
     else if ((rx_curr_st == RX_WRITE) && (rx_nxt_st != RX_WRITE)) begin
       rx_prev_st <= RX_WRITE;
     end
     else if ((rx_curr_st == RX_WDATA) && (rx_nxt_st != RX_WDATA)) begin
       rx_prev_st <= RX_WDATA;
     end
   end
 end


endmodule
module uartm_rx (

  input  wire        hclk,
  input  wire        hresetn,


  input  wire        hwrite,
  input  wire        hready,


  input  wire [31:0] uartm_baud,
  input  wire [31:0] uartm_ctl,


  input  wire        sample_data_bit,
  input  wire [7:0]  bit_cnt,
  input  wire [7:0]  uartm_dw,
  input  wire [7:0]  uartm_plw,


  input  wire        RX,

  output reg [31:0]  rx_reg,
  output reg [2:0]   rx_curr_st,
  output reg [2:0]   rx_nxt_st
);






  `include "uartm_params.v"


reg [2:0]   rx_prev_st;



   always @ (posedge hclk or negedge hresetn) begin
     if (hresetn == 1'b0) begin
       rx_reg = 32'b0;
     end
     else begin
       if ((sample_data_bit == 1'b1) && (bit_cnt <= uartm_dw)) begin
           rx_reg = {RX, rx_reg[31:1]};
       end
     end
   end
 












 
 always @* begin
   rx_nxt_st = rx_curr_st;
   case (rx_curr_st)
     RX_IDLE : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         if (uartm_ctl[1:0] == 2'b10) begin
           rx_nxt_st = RX_CHECK;
         end
         else begin
           rx_nxt_st = RX_WAIT1;
         end
       end
     end
     RX_CHECK : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         if (uartm_ctl[1:0] == 2'b10) begin
           if (hwrite == 1'b1) begin
             rx_nxt_st = RX_WRITE;
           end 
           else begin
             rx_nxt_st = RX_READ;
           end
         end
         else begin
           rx_nxt_st = RX_WAIT1;
         end
       end
     end
     RX_WAIT1 : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         if (uartm_ctl[1:0] == 2'b01) begin
           if (rx_prev_st == RX_IDLE) begin
             rx_nxt_st = RX_CHECK;
           end
           else if (rx_prev_st == RX_CHECK) begin
             if (hwrite == 1'b1) begin
               rx_nxt_st = RX_WRITE;
             end 
             else begin
               rx_nxt_st = RX_READ;
             end
           end
           else if (rx_prev_st == RX_WRITE) begin
             rx_nxt_st = RX_WDATA;
           end
           else begin
             rx_nxt_st = RX_IDLE;
           end
         end
         else begin
           rx_nxt_st = RX_WAIT2;
         end
       end
     end
     RX_WAIT2 : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         rx_nxt_st = RX_WAIT3;
       end
     end
     RX_WAIT3 : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         if (rx_prev_st == RX_IDLE) begin
           rx_nxt_st = RX_CHECK;
         end
         else if (rx_prev_st == RX_CHECK) begin
           if (hwrite == 1'b1) begin
             rx_nxt_st = RX_WRITE;
           end 
           else begin
             rx_nxt_st = RX_READ;
           end
         end
         else if (rx_prev_st == RX_WRITE) begin
           rx_nxt_st = RX_WDATA;
         end
       end
     end
     RX_READ : begin
         rx_nxt_st = RX_IDLE;
     end
     RX_WRITE : begin
       if (bit_cnt == uartm_plw[7:0])  begin
         if (uartm_ctl[1:0] == 2'b10) begin
           rx_nxt_st = RX_WDATA;
         end
         else begin
           rx_nxt_st = RX_WAIT1;
         end
       end
     end
     RX_WDATA : begin
         rx_nxt_st = RX_IDLE;
     end
     default : begin
       rx_nxt_st = RX_IDLE;
     end
   endcase
 end

 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     rx_curr_st <= 3'b0;
   end
   else begin
     rx_curr_st <= rx_nxt_st;
   end
 end
 
 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     rx_prev_st <= 3'b0;
   end
   else begin
     if ((rx_curr_st == RX_IDLE) && (rx_nxt_st != RX_IDLE)) begin
       rx_prev_st <= RX_IDLE;
     end
     else if ((rx_curr_st == RX_CHECK) && (rx_nxt_st != RX_CHECK)) begin
       rx_prev_st <= RX_CHECK;
     end
     else if ((rx_curr_st == RX_READ) && (rx_nxt_st != RX_READ)) begin
       rx_prev_st <= RX_READ;
     end
     else if ((rx_curr_st == RX_WRITE) && (rx_nxt_st != RX_WRITE)) begin
       rx_prev_st <= RX_WRITE;
     end
     else if ((rx_curr_st == RX_WDATA) && (rx_nxt_st != RX_WDATA)) begin
       rx_prev_st <= RX_WDATA;
     end
   end
 end


endmodule