data/full_repos/permissive/16552133/src/verilog/random_access_memory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/16552133/src/verilog/random_access_memory.v:53: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s ARRAYSEL generates 1 bits.\n                                                                                         : ... In instance random_access_memory\n assign MDR_line = (enable && ~rw) ? MEM[address] : 16\'hZZ;\n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/16552133/src/verilog/random_access_memory.v:53: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 16 bits.\n                                                                                         : ... In instance random_access_memory\n assign MDR_line = (enable && ~rw) ? MEM[address] : 16\'hZZ;\n                 ^\n%Error: Exiting due to 2 warning(s)\n'
module random_access_memory#(parameter n=1, parameter m=1)(clk,address,MDR_line,enable,clr,rw);
	parameter L = (2**n);
	integer i;
	input clk, enable,clr,rw;
	input [n-1:0]address;
	inout [m-1:0]MDR_line;
	reg [m-1:0]MEM [L-1:0];
	
	initial begin

	end
	
	always @(posedge clk)
	begin
		if (clr == 1) begin

			for(i=0;i<L;i=i+1) begin
				MEM[i] <= 0;
			end
		end
		else if(enable && rw) begin

			MEM[address] <= MDR_line;
		end
		else if(enable && ~rw) begin

		end
		else begin

		end		
	end
	

	assign MDR_line = (enable && ~rw) ? MEM[address] : 16'hZZ;
endmodule
module random_access_memory#(parameter n=1, parameter m=1)(clk,address,MDR_line,enable,clr,rw);

	parameter L = (2**n);
	integer i;
	input clk, enable,clr,rw;
	input [n-1:0]address;
	inout [m-1:0]MDR_line;
	reg [m-1:0]MEM [L-1:0];
	
	initial begin

	end
	
	always @(posedge clk)
	begin
		if (clr == 1) begin

			for(i=0;i<L;i=i+1) begin
				MEM[i] <= 0;
			end
		end
		else if(enable && rw) begin

			MEM[address] <= MDR_line;
		end
		else if(enable && ~rw) begin

		end
		else begin

		end		
	end
	

	assign MDR_line = (enable && ~rw) ? MEM[address] : 16'hZZ;
endmodule