data/full_repos/permissive/202776140/BatAmaBehavioural.v
1: b'%Warning-WIDTH: data/full_repos/permissive/202776140/BatAmaBehavioural.v:145: Bit extraction of var[23:0] requires 5 bit index, not 3 bits.\n                                                                            : ... In instance BatAmateurController\n     REGS[INSTR[2:0]] <= REGS[INSTR[2:0]] ^ 1\'b1;\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/202776140/BatAmaBehavioural.v:145: Bit extraction of var[23:0] requires 5 bit index, not 3 bits.\n                                                                            : ... In instance BatAmateurController\n     REGS[INSTR[2:0]] <= REGS[INSTR[2:0]] ^ 1\'b1;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/202776140/BatAmaBehavioural.v:207: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                            : ... In instance BatAmateurController\n      PC <= 2\'b01;\n         ^~\n%Error: Exiting due to 3 warning(s)\n'
module BatAmateurController(
	input wire CLK, RST,
	input wire [7:0] ALU_REG,
	input wire [15:0] INSTR,

	output reg [2:0] PC,
	output reg [1:0] MAR,
	output reg [1:0] RAM,
	output reg [1:0] IR,

	output reg [23:0] REGS,
	output reg ALU_EN,
	output reg [4:0] ALU_OP
);

reg [2:0] uOP;

always @(negedge CLK)
begin


	uOP = uOP + 1;


	PC = 0;
	MAR = 0;
	RAM = 0;
	IR = 0;
	REGS = 0;
	ALU_EN = 0;
	ALU_OP = 0;
	
	if(RST == 1'b0)
	begin
		uOP = 3'b111;
	end
	else
	begin

	case(uOP)
	
		0:
			begin
			PC <= 3'b011;
			MAR <= 2'b01;
			end

		1:
			begin
			PC <= 3'b110; 
			MAR <= 2'b11;
			RAM <= 2'b11;
			IR <= 2'b01;
			end
	
		2:



			begin
				if(INSTR[15:12] == 4'b0111)
				begin


					

					if(INSTR[11:7] == 5'b11111)
					begin

						REGS[INSTR[5:3]*3] <= 1'b1;

						REGS[INSTR[2:0]*3+1] <= 1'b1;
						REGS[INSTR[2:0]*3] <= 1'b1;

						uOP <= 3'b111;
					end

					else if(INSTR[11:7] == 5'b11110)
					begin

						REGS[INSTR[5:3]*3+2] <= 1'b1;
						REGS[INSTR[5:3]*3+1] <= 1'b1;

						uOP <= 3'b111;
					end
					else
					begin



						

						REGS[0] <= 1'b1;
						REGS[INSTR[5:3]*3] <= (REGS[INSTR[5:3]*3]) ^ 1'b1;
						REGS[INSTR[5:3]*3+1] <= 1'b1;
					end
				end
				else
				begin


					if(INSTR[14]==1'b1)
					begin


						if(((INSTR[13:12] == 1) && (ALU_REG[0] == 1)) || (INSTR[13:12] == 2 && ALU_REG[0] == 0) ||(INSTR[13:12] == 2'b00))
						begin
							if(INSTR[15] == 1)
							begin

								REGS[0] <= 1'b1;
								PC <= 3'b011;
							end
							else
							begin

								IR <= 2'b11;
								MAR <= 2'b01;
							end
						end
						else
						begin
							uOP <= 3'b111;
						end
					end
					else if(INSTR[14]==1'b0)
					begin

						IR <= 2'b11;
						MAR <= 2'b01;
					end
				end
			end
		3:
		    begin
				if(INSTR[15:12] == 4'b0111)
				begin
					REGS[3] <= 1'b1;
					REGS[INSTR[2:0]] <= REGS[INSTR[2:0]] ^ 1'b1;
					REGS[INSTR[2:0]+1] <= 1'b1;
				end
				else
				begin
					if(INSTR[14]==1'b1)
					begin
						if(INSTR[15] == 1'b1)
						begin
							RAM <= 2'b11;
							MAR <= 2'b11;
							PC <= 3'b001;
							uOP <= 3'b111;
						end
						else
						begin
							REGS[3] <= 1'b1;
							IR <= 2'b11;
						end
					end
					else
					begin


						if(INSTR[13]==1'b1 && INSTR[15] == 1'b0)
						begin
							REGS[INSTR[12]*3+1] <= 1'b1;
							REGS[INSTR[12]*3] <= 1'b1;
							RAM <= 2'b01;
							MAR <= 2'b11;
							uOP <= 3'b111;
						end
						else if(INSTR[13]==1'b0 && INSTR[15]==1'b0)
						begin
							MAR <= 2'b11;
							RAM <= 2'b11;
							REGS[INSTR[6]*3] <= 1'b1;
							uOP <= 3'b111;
						end
						else
						begin
							RAM <= 2'b11;
							MAR <= 2'b01;
						end
					end
				end
			end
		4:
		    begin
				if(INSTR[15:12] == 4'b0111)
				begin
					ALU_EN <= 1'b1;
					ALU_OP <= INSTR[11:7];
					REGS[INSTR[6]*3] <= 1'b1;
					uOP <= 3'b111;
				end
				else
				begin
					if(INSTR[14]==1'b1)
					begin
						ALU_EN <= 1'b1;
						ALU_OP <= 5'b00000;
						PC <= 2'b01;
						uOP <= 3'b111;
					end
					else
					begin
						if(INSTR[13] == 1'b1)
						begin
							RAM <= 2'b01;
							REGS[INSTR[6]*3] <= 1'b1;
							REGS[INSTR[6]*3+1] <= 1'b1;
							uOP <= 3'b111;
						end
						else
						begin
							REGS[INSTR[6]*3] <= 1'b1;
							RAM <= 2'b11;
							uOP <= 3'b111;
						end
					end
				end
			end
		default:
		    begin
				uOP <= 3'b111;
			end
	endcase
	end
end

endmodule
module BatAmateurController(
	input wire CLK, RST,
	input wire [7:0] ALU_REG,
	input wire [15:0] INSTR,

	output reg [2:0] PC,
	output reg [1:0] MAR,
	output reg [1:0] RAM,
	output reg [1:0] IR,

	output reg [23:0] REGS,
	output reg ALU_EN,
	output reg [4:0] ALU_OP
);


reg [2:0] uOP;

always @(negedge CLK)
begin


	uOP = uOP + 1;


	PC = 0;
	MAR = 0;
	RAM = 0;
	IR = 0;
	REGS = 0;
	ALU_EN = 0;
	ALU_OP = 0;
	
	if(RST == 1'b0)
	begin
		uOP = 3'b111;
	end
	else
	begin

	case(uOP)
	
		0:
			begin
			PC <= 3'b011;
			MAR <= 2'b01;
			end

		1:
			begin
			PC <= 3'b110; 
			MAR <= 2'b11;
			RAM <= 2'b11;
			IR <= 2'b01;
			end
	
		2:



			begin
				if(INSTR[15:12] == 4'b0111)
				begin


					

					if(INSTR[11:7] == 5'b11111)
					begin

						REGS[INSTR[5:3]*3] <= 1'b1;

						REGS[INSTR[2:0]*3+1] <= 1'b1;
						REGS[INSTR[2:0]*3] <= 1'b1;

						uOP <= 3'b111;
					end

					else if(INSTR[11:7] == 5'b11110)
					begin

						REGS[INSTR[5:3]*3+2] <= 1'b1;
						REGS[INSTR[5:3]*3+1] <= 1'b1;

						uOP <= 3'b111;
					end
					else
					begin



						

						REGS[0] <= 1'b1;
						REGS[INSTR[5:3]*3] <= (REGS[INSTR[5:3]*3]) ^ 1'b1;
						REGS[INSTR[5:3]*3+1] <= 1'b1;
					end
				end
				else
				begin


					if(INSTR[14]==1'b1)
					begin


						if(((INSTR[13:12] == 1) && (ALU_REG[0] == 1)) || (INSTR[13:12] == 2 && ALU_REG[0] == 0) ||(INSTR[13:12] == 2'b00))
						begin
							if(INSTR[15] == 1)
							begin

								REGS[0] <= 1'b1;
								PC <= 3'b011;
							end
							else
							begin

								IR <= 2'b11;
								MAR <= 2'b01;
							end
						end
						else
						begin
							uOP <= 3'b111;
						end
					end
					else if(INSTR[14]==1'b0)
					begin

						IR <= 2'b11;
						MAR <= 2'b01;
					end
				end
			end
		3:
		    begin
				if(INSTR[15:12] == 4'b0111)
				begin
					REGS[3] <= 1'b1;
					REGS[INSTR[2:0]] <= REGS[INSTR[2:0]] ^ 1'b1;
					REGS[INSTR[2:0]+1] <= 1'b1;
				end
				else
				begin
					if(INSTR[14]==1'b1)
					begin
						if(INSTR[15] == 1'b1)
						begin
							RAM <= 2'b11;
							MAR <= 2'b11;
							PC <= 3'b001;
							uOP <= 3'b111;
						end
						else
						begin
							REGS[3] <= 1'b1;
							IR <= 2'b11;
						end
					end
					else
					begin


						if(INSTR[13]==1'b1 && INSTR[15] == 1'b0)
						begin
							REGS[INSTR[12]*3+1] <= 1'b1;
							REGS[INSTR[12]*3] <= 1'b1;
							RAM <= 2'b01;
							MAR <= 2'b11;
							uOP <= 3'b111;
						end
						else if(INSTR[13]==1'b0 && INSTR[15]==1'b0)
						begin
							MAR <= 2'b11;
							RAM <= 2'b11;
							REGS[INSTR[6]*3] <= 1'b1;
							uOP <= 3'b111;
						end
						else
						begin
							RAM <= 2'b11;
							MAR <= 2'b01;
						end
					end
				end
			end
		4:
		    begin
				if(INSTR[15:12] == 4'b0111)
				begin
					ALU_EN <= 1'b1;
					ALU_OP <= INSTR[11:7];
					REGS[INSTR[6]*3] <= 1'b1;
					uOP <= 3'b111;
				end
				else
				begin
					if(INSTR[14]==1'b1)
					begin
						ALU_EN <= 1'b1;
						ALU_OP <= 5'b00000;
						PC <= 2'b01;
						uOP <= 3'b111;
					end
					else
					begin
						if(INSTR[13] == 1'b1)
						begin
							RAM <= 2'b01;
							REGS[INSTR[6]*3] <= 1'b1;
							REGS[INSTR[6]*3+1] <= 1'b1;
							uOP <= 3'b111;
						end
						else
						begin
							REGS[INSTR[6]*3] <= 1'b1;
							RAM <= 2'b11;
							uOP <= 3'b111;
						end
					end
				end
			end
		default:
		    begin
				uOP <= 3'b111;
			end
	endcase
	end
end

endmodule