data/full_repos/permissive/127311496/src/v/Cache/DCache.v
 line:112: before: "="
1: b"%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:136: Cannot find file containing module: 'DCacheTag'\n DCacheTag cacheTag(.clka(clk), .wea(tagWe),\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/DCacheTag\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/DCacheTag.v\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/DCacheTag.sv\n             DCacheTag\n             DCacheTag.v\n             DCacheTag.sv\n             obj_dir/DCacheTag\n             obj_dir/DCacheTag.v\n             obj_dir/DCacheTag.sv\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:138: Cannot find file containing module: 'CacheLRUBit'\n CacheLRUBit cacheLRU(.clk(clk), .req(req_reg), .addr(tagAddr), .hit({hit1, hit0}), .flag(LRUBit));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:60: Cannot find file containing module: 'DCacheData'\n DCacheData way0Data(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:65: Cannot find file containing module: 'DCacheData'\n DCacheData way1Data(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:88: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceTypeCross (.clki(clkCPU), .clko(clkDDR), .i(replaceType_CPU), .o(replaceType_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:89: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceIndexCross[9:0](.clki(clkCPU), .clko(clkDDR), .i(replaceIndex_CPU), .o(replaceIndex_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:90: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) oldTagCross[16:0](.clki(clkCPU), .clko(clkDDR), .i(oldTag_CPU), .o(oldTag_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:91: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) newTagCross[16:0](.clki(clkCPU), .clko(clkDDR), .i(newTag_CPU), .o(newTag_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:93: Cannot find file containing module: 'AsyncHandshake'\n AsyncHandshake #(.STB_FREQ(1000 / CLKCPU_PERIOD), .ACK_FREQ(1000 / CLKDDR_PERIOD))\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/DCache.v:97: Cannot find file containing module: 'AsyncHandshake'\n AsyncHandshake #(.STB_FREQ(1000 / CLKDDR_PERIOD), .ACK_FREQ(1000 / CLKCPU_PERIOD))\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module DCacheFSM_DDR(
	input clk, input rst,

	output [31:0] ws_addr, output reg [511:0] ws_dout, output reg [63:0] ws_dm,
	input [511:0] ws_din, output reg ws_cyc = 0, output ws_stb, output ws_we, input ws_ack,

	output [9:0] addrb, output dataOp, output reg web,
	output reg [511:0] dinb, input [511:0] doutb, input [63:0] dirtyb,

	input replaceStb, input replaceType, output reg replaceAck, output reg completeStb = 0,
	input [9:0] replaceIndex, input [16:0] oldTag, input [16:0] newTag
);


	reg [16:0] newTag_reg;
	reg writeBack, readIn;
	reg [25:0] addr = 0;
	reg waySel = 0;
	assign ws_addr = {addr, 6'h0};
	assign addrb = {waySel, addr[8:0]};
	
	reg blockDirty;
	
	localparam STATE_IDLE = 3'h0;
	localparam STATE_MEM_READ = 3'h1;
	localparam STATE_MEM_READ_END = 3'h2;
	localparam STATE_WS_PREP = 3'h3;
	localparam STATE_WS_READ = 3'h4;

	localparam STATE_MEM_WRITE_END = 3'h6;
	localparam STATE_WS_WRITE = 3'h7;
	reg [2:0] state;
	
	assign ws_stb = (state == STATE_WS_READ) | (state == STATE_WS_WRITE);
	assign ws_we = (state == STATE_WS_WRITE);
	assign dataOp = (state != STATE_MEM_READ_END);
	
	always @ (posedge clk)
	if(rst)
	begin
		state <= STATE_IDLE;
		ws_cyc <= 1'b0;
	end
	else
	begin
	replaceAck <= 1'b0;
	completeStb <= 1'b0;
	case(state)
	STATE_IDLE: begin
		if(replaceStb)
		begin
			waySel <= replaceIndex[9];
			readIn <= replaceType;
			writeBack <= (oldTag != newTag);
			newTag_reg <= oldTag ^ newTag;
			addr <= {oldTag, replaceIndex[8:0]};
			if(replaceType & (oldTag == newTag))
			begin
				state <= STATE_WS_READ;
				ws_cyc <= 1'b1;
				replaceAck <= 1'b1;
			end
			else
				state <= STATE_MEM_READ;
		end
	end
	STATE_MEM_READ: begin
		state <= STATE_MEM_READ_END;
		web <= 1'b1;
	end
	STATE_MEM_READ_END: begin
		web <= 1'b0;
		ws_dout <= waySel? {doutb[255:0], doutb[511:256]}: doutb;
		ws_dm <= waySel? {dirtyb[31:0], dirtyb[63:32]}: dirtyb;
		blockDirty <= |dirtyb;
		state <= STATE_WS_PREP;
		replaceAck <= 1'b1;
	end
	STATE_WS_PREP: begin
		writeBack <= writeBack & blockDirty;
		if(readIn)
		begin
			ws_cyc <= 1'b1;
			state <= STATE_WS_READ;
			addr[25:9] <= addr[25:9] ^ newTag_reg;
		end
		else if(blockDirty)
		begin
			ws_cyc <= 1'b1;
			state <= STATE_WS_WRITE;
		end
		else
			state <= STATE_IDLE;
	end
	STATE_WS_READ: begin
		if(ws_ack)
		begin
			state <= STATE_MEM_WRITE_END;
			dinb <= waySel? {ws_din[255:0], ws_din[511:256]}: ws_din;
			web <= 1'b1;
			ws_cyc <= writeBack;
		end
	end
	STATE_MEM_WRITE_END: begin
		web <= 1'b0;
		completeStb <= 1'b1;
		if(writeBack)
		begin
			state <= STATE_WS_WRITE;
			addr[25:9] <= addr[25:9] ^ newTag_reg;
		end
		else
			state <= STATE_IDLE;
	end
	STATE_WS_WRITE: begin
		if(ws_ack)
		begin
			state <= STATE_IDLE;
			ws_cyc <= 1'b0;
		end
	end
	endcase
	end

endmodule
module DCacheFSM_DDR(
	input clk, input rst,

	output [31:0] ws_addr, output reg [511:0] ws_dout, output reg [63:0] ws_dm,
	input [511:0] ws_din, output reg ws_cyc = 0, output ws_stb, output ws_we, input ws_ack,

	output [9:0] addrb, output dataOp, output reg web,
	output reg [511:0] dinb, input [511:0] doutb, input [63:0] dirtyb,

	input replaceStb, input replaceType, output reg replaceAck, output reg completeStb = 0,
	input [9:0] replaceIndex, input [16:0] oldTag, input [16:0] newTag
);



	reg [16:0] newTag_reg;
	reg writeBack, readIn;
	reg [25:0] addr = 0;
	reg waySel = 0;
	assign ws_addr = {addr, 6'h0};
	assign addrb = {waySel, addr[8:0]};
	
	reg blockDirty;
	
	localparam STATE_IDLE = 3'h0;
	localparam STATE_MEM_READ = 3'h1;
	localparam STATE_MEM_READ_END = 3'h2;
	localparam STATE_WS_PREP = 3'h3;
	localparam STATE_WS_READ = 3'h4;

	localparam STATE_MEM_WRITE_END = 3'h6;
	localparam STATE_WS_WRITE = 3'h7;
	reg [2:0] state;
	
	assign ws_stb = (state == STATE_WS_READ) | (state == STATE_WS_WRITE);
	assign ws_we = (state == STATE_WS_WRITE);
	assign dataOp = (state != STATE_MEM_READ_END);
	
	always @ (posedge clk)
	if(rst)
	begin
		state <= STATE_IDLE;
		ws_cyc <= 1'b0;
	end
	else
	begin
	replaceAck <= 1'b0;
	completeStb <= 1'b0;
	case(state)
	STATE_IDLE: begin
		if(replaceStb)
		begin
			waySel <= replaceIndex[9];
			readIn <= replaceType;
			writeBack <= (oldTag != newTag);
			newTag_reg <= oldTag ^ newTag;
			addr <= {oldTag, replaceIndex[8:0]};
			if(replaceType & (oldTag == newTag))
			begin
				state <= STATE_WS_READ;
				ws_cyc <= 1'b1;
				replaceAck <= 1'b1;
			end
			else
				state <= STATE_MEM_READ;
		end
	end
	STATE_MEM_READ: begin
		state <= STATE_MEM_READ_END;
		web <= 1'b1;
	end
	STATE_MEM_READ_END: begin
		web <= 1'b0;
		ws_dout <= waySel? {doutb[255:0], doutb[511:256]}: doutb;
		ws_dm <= waySel? {dirtyb[31:0], dirtyb[63:32]}: dirtyb;
		blockDirty <= |dirtyb;
		state <= STATE_WS_PREP;
		replaceAck <= 1'b1;
	end
	STATE_WS_PREP: begin
		writeBack <= writeBack & blockDirty;
		if(readIn)
		begin
			ws_cyc <= 1'b1;
			state <= STATE_WS_READ;
			addr[25:9] <= addr[25:9] ^ newTag_reg;
		end
		else if(blockDirty)
		begin
			ws_cyc <= 1'b1;
			state <= STATE_WS_WRITE;
		end
		else
			state <= STATE_IDLE;
	end
	STATE_WS_READ: begin
		if(ws_ack)
		begin
			state <= STATE_MEM_WRITE_END;
			dinb <= waySel? {ws_din[255:0], ws_din[511:256]}: ws_din;
			web <= 1'b1;
			ws_cyc <= writeBack;
		end
	end
	STATE_MEM_WRITE_END: begin
		web <= 1'b0;
		completeStb <= 1'b1;
		if(writeBack)
		begin
			state <= STATE_WS_WRITE;
			addr[25:9] <= addr[25:9] ^ newTag_reg;
		end
		else
			state <= STATE_IDLE;
	end
	STATE_WS_WRITE: begin
		if(ws_ack)
		begin
			state <= STATE_IDLE;
			ws_cyc <= 1'b0;
		end
	end
	endcase
	end

endmodule