data/full_repos/permissive/14593708/tests/register-testbench.v
1: b'%Error: data/full_repos/permissive/14593708/tests/register-testbench.v:11: Unsupported or unknown PLI call: $monitor\n        $monitor("value=%d set=%b out=%d", value, set, out);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #0  value = \'d42;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #0  set = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1  set = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1  set = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1  value = \'d21;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/register-testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1  set = 1;\n    ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_testbench;

    reg[31:0]  value;
    wire[31:0] out;
    reg        set;

    register r1(value, set, out);

    initial
    begin
        $monitor("value=%d set=%b out=%d", value, set, out);
    #0  value = 'd42;
    #0  set = 0;
    #1  set = 1;
    #1  set = 0;
    #1  value = 'd21;
    #1  set = 1;
    end

endmodule
module register_testbench;


    reg[31:0]  value;
    wire[31:0] out;
    reg        set;

    register r1(value, set, out);

    initial
    begin
        $monitor("value=%d set=%b out=%d", value, set, out);
    #0  value = 'd42;
    #0  set = 0;
    #1  set = 1;
    #1  set = 0;
    #1  value = 'd21;
    #1  set = 1;
    end

endmodule