data/full_repos/permissive/140495330/src/hdl/debouncer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/140495330/src/hdl/debouncer.v:21: Operator GTE expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'count\' generates 8 bits.\n                                                                           : ... In instance debouncer\n                    if (count >= CLOCKS-1) begin\n                              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module debouncer #(
    parameter WIDTH = 1,
    parameter CLOCKS = 256,
    parameter CLOCKS_CLOG2 = 8
) (
    input  wire clk,
    input  wire [WIDTH-1:0] din,
    output wire [WIDTH-1:0] dout
);
    genvar i;
    generate for (i=0; i<WIDTH; i=i+1) begin : IDX
        reg [CLOCKS_CLOG2-1:0] count = 'b0;
        reg transitioning = 1'b0;
        reg data = 1'b0;
        always@(posedge clk)
            if (transitioning == 1'b1)
                if (data != din[i])
                    if (count >= CLOCKS-1) begin
                        data <= din[i];
                        transitioning <= 1'b0;
                    end else
                        count <= count + 1'b1;
                else
                    transitioning <= 1'b0;
            else if (data != din[i]) begin
                count <= 'b0;
                transitioning <= 1'b1;
            end
        assign dout[i] = data;
    end endgenerate
endmodule
module debouncer #(
    parameter WIDTH = 1,
    parameter CLOCKS = 256,
    parameter CLOCKS_CLOG2 = 8
) (
    input  wire clk,
    input  wire [WIDTH-1:0] din,
    output wire [WIDTH-1:0] dout
);

    genvar i;
    generate for (i=0; i<WIDTH; i=i+1) begin : IDX
        reg [CLOCKS_CLOG2-1:0] count = 'b0;
        reg transitioning = 1'b0;
        reg data = 1'b0;
        always@(posedge clk)
            if (transitioning == 1'b1)
                if (data != din[i])
                    if (count >= CLOCKS-1) begin
                        data <= din[i];
                        transitioning <= 1'b0;
                    end else
                        count <= count + 1'b1;
                else
                    transitioning <= 1'b0;
            else if (data != din[i]) begin
                count <= 'b0;
                transitioning <= 1'b1;
            end
        assign dout[i] = data;
    end endgenerate
endmodule