data/full_repos/permissive/187199324/stannel/Receive.v
1: b'%Error: data/full_repos/permissive/187199324/stannel/Receive.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:5: Define or directive not defined: \'`ADDRESS_BITS\'\nmodule Receive #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:5: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nmodule Receive #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                                    ^\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:5: Define or directive not defined: \'`DATA_BITS\'\nmodule Receive #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:5: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule Receive #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                                                                      ^\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:8: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                reset,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:9: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                 finished,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:11: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg  [addrBits-1:0] address,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:12: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                 readWriteMode,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:13: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire [dataBits-1:0] dataOut,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg  [dataBits-1:0] dataIn,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:16: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire [addrBits-1:0] channel,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [addrBits-1:0] rxPid,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                 shouldScheduleSender,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:20: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                 shouldDescheduleReceiver,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:21: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg  [addrBits-1:0] scheduleTxPid,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:22: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                 hasDeliveredMessage,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg  [dataBits-1:0] deliveredMessage\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:24: syntax error, unexpected \')\', expecting \',\' or \';\'\n  );\n  ^\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:55: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:90: Define or directive not defined: \'`RAM_READ\'\n    readWriteMode             = `RAM_READ;\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:126: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:133: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:148: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive.v:155: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: Exiting due to 25 error(s)\n'
module Receive #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    output reg                 finished,

    output reg  [addrBits-1:0] address,
    output reg                 readWriteMode,
    input  wire [dataBits-1:0] dataOut,
    output reg  [dataBits-1:0] dataIn,

    input  wire [addrBits-1:0] channel,
    input  wire [addrBits-1:0] rxPid,

    output reg                 shouldScheduleSender,
    output reg                 shouldDescheduleReceiver,
    output reg  [addrBits-1:0] scheduleTxPid,
    output reg                 hasDeliveredMessage,
    output reg  [dataBits-1:0] deliveredMessage
  );


  wire [addrBits-1:0] messageAddress = channel + 1;



  localparam STATE_INIT            = 3'd0;
  localparam STATE_READ_TX_PROC    = 3'd1;
  localparam STATE_HANDLE_TX_PROC  = 3'd2;
  localparam STATE_WRITE_RX_PROC_0 = 3'd3;
  localparam STATE_WRITE_RX_PROC_1 = 3'd4;
  localparam STATE_READ_MESSAGE    = 3'd5;
  localparam STATE_WRITE_0         = 3'd6;
  localparam STATE_WRITE_1         = 3'd7;

  reg [2:0]          rState;



  reg [2:0]          wNextState;
  reg                wHasMessage;
  reg [dataBits-1:0] wMessage;
  reg                wShouldScheduleSender;
  reg                wShouldDescheduleReceiver;
  reg                wFinished;
  reg                wUpdateTx;
  reg                wUpdateMessage;
  reg                wUpdateScheduling;


  always @(posedge clk)
  begin
    if (!reset)
      begin
        rState                    <= STATE_INIT;
        shouldScheduleSender     <= 0;
        shouldDescheduleReceiver <= 0;
        finished                 <= 0;
        hasDeliveredMessage      <= 0;
      end
    else
      begin
        rState <= wNextState;
        finished <= wFinished;

        if (wUpdateTx)
          scheduleTxPid <= dataOut[7:0];

        if (wUpdateScheduling)
          begin
            shouldScheduleSender     <= wShouldScheduleSender;
            shouldDescheduleReceiver <= wShouldDescheduleReceiver;
            hasDeliveredMessage      <= wHasMessage;
          end

        if (wUpdateMessage)
          deliveredMessage <= wMessage;
      end
  end


  always @(*)
  begin
    address                   = {addrBits{1'bx}};
    dataIn                    = {dataBits{1'bx}};
    readWriteMode             = `RAM_READ;
    wFinished                 = 0;
    wNextState                = rState;
    wHasMessage               = 0;
    wMessage                  = {dataBits{1'bx}};
    wShouldScheduleSender     = 0;
    wShouldDescheduleReceiver = 0;
    wFinished                 = 0;
    wUpdateTx                 = 0;
    wUpdateMessage            = 0;
    wUpdateScheduling         = 0;
    case (rState)
      STATE_INIT:
        begin
          address    = channel;
          wNextState = STATE_READ_TX_PROC;
        end
      STATE_READ_TX_PROC:
        begin
          wUpdateTx  = 1;
          address    = channel;
          wNextState = STATE_HANDLE_TX_PROC;
        end
      STATE_HANDLE_TX_PROC:
        begin
          wUpdateScheduling         = 1;
          wShouldDescheduleReceiver = scheduleTxPid == 0;
          wShouldScheduleSender     = scheduleTxPid != 0;
          wHasMessage               = scheduleTxPid != 0;
          wNextState                = scheduleTxPid == 0 ? STATE_WRITE_RX_PROC_0 : STATE_READ_MESSAGE;
          address                   = messageAddress;
        end
      STATE_WRITE_RX_PROC_0:
        begin
          address       = channel;
          dataIn        = {8'b0, rxPid};
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_RX_PROC_1;
        end
      STATE_WRITE_RX_PROC_1:
        begin
          address       = channel;
          dataIn        = {8'b0,rxPid};
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_INIT;
          wFinished     = 1;
        end
      STATE_READ_MESSAGE:
        begin
          address        = messageAddress;
          wUpdateMessage = 1;
          wMessage       = dataOut;
          wNextState     = STATE_WRITE_0;
        end
      STATE_WRITE_0:
        begin
          address       = channel;
          dataIn        = 0;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_1;
        end
      STATE_WRITE_1:
        begin
          address       = channel;
          dataIn        = 0;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_INIT;
          wFinished     = 1;
        end
    endcase
  end

endmodule
module Receive #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    output reg                 finished,

    output reg  [addrBits-1:0] address,
    output reg                 readWriteMode,
    input  wire [dataBits-1:0] dataOut,
    output reg  [dataBits-1:0] dataIn,

    input  wire [addrBits-1:0] channel,
    input  wire [addrBits-1:0] rxPid,

    output reg                 shouldScheduleSender,
    output reg                 shouldDescheduleReceiver,
    output reg  [addrBits-1:0] scheduleTxPid,
    output reg                 hasDeliveredMessage,
    output reg  [dataBits-1:0] deliveredMessage
  );



  wire [addrBits-1:0] messageAddress = channel + 1;



  localparam STATE_INIT            = 3'd0;
  localparam STATE_READ_TX_PROC    = 3'd1;
  localparam STATE_HANDLE_TX_PROC  = 3'd2;
  localparam STATE_WRITE_RX_PROC_0 = 3'd3;
  localparam STATE_WRITE_RX_PROC_1 = 3'd4;
  localparam STATE_READ_MESSAGE    = 3'd5;
  localparam STATE_WRITE_0         = 3'd6;
  localparam STATE_WRITE_1         = 3'd7;

  reg [2:0]          rState;



  reg [2:0]          wNextState;
  reg                wHasMessage;
  reg [dataBits-1:0] wMessage;
  reg                wShouldScheduleSender;
  reg                wShouldDescheduleReceiver;
  reg                wFinished;
  reg                wUpdateTx;
  reg                wUpdateMessage;
  reg                wUpdateScheduling;


  always @(posedge clk)
  begin
    if (!reset)
      begin
        rState                    <= STATE_INIT;
        shouldScheduleSender     <= 0;
        shouldDescheduleReceiver <= 0;
        finished                 <= 0;
        hasDeliveredMessage      <= 0;
      end
    else
      begin
        rState <= wNextState;
        finished <= wFinished;

        if (wUpdateTx)
          scheduleTxPid <= dataOut[7:0];

        if (wUpdateScheduling)
          begin
            shouldScheduleSender     <= wShouldScheduleSender;
            shouldDescheduleReceiver <= wShouldDescheduleReceiver;
            hasDeliveredMessage      <= wHasMessage;
          end

        if (wUpdateMessage)
          deliveredMessage <= wMessage;
      end
  end


  always @(*)
  begin
    address                   = {addrBits{1'bx}};
    dataIn                    = {dataBits{1'bx}};
    readWriteMode             = `RAM_READ;
    wFinished                 = 0;
    wNextState                = rState;
    wHasMessage               = 0;
    wMessage                  = {dataBits{1'bx}};
    wShouldScheduleSender     = 0;
    wShouldDescheduleReceiver = 0;
    wFinished                 = 0;
    wUpdateTx                 = 0;
    wUpdateMessage            = 0;
    wUpdateScheduling         = 0;
    case (rState)
      STATE_INIT:
        begin
          address    = channel;
          wNextState = STATE_READ_TX_PROC;
        end
      STATE_READ_TX_PROC:
        begin
          wUpdateTx  = 1;
          address    = channel;
          wNextState = STATE_HANDLE_TX_PROC;
        end
      STATE_HANDLE_TX_PROC:
        begin
          wUpdateScheduling         = 1;
          wShouldDescheduleReceiver = scheduleTxPid == 0;
          wShouldScheduleSender     = scheduleTxPid != 0;
          wHasMessage               = scheduleTxPid != 0;
          wNextState                = scheduleTxPid == 0 ? STATE_WRITE_RX_PROC_0 : STATE_READ_MESSAGE;
          address                   = messageAddress;
        end
      STATE_WRITE_RX_PROC_0:
        begin
          address       = channel;
          dataIn        = {8'b0, rxPid};
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_RX_PROC_1;
        end
      STATE_WRITE_RX_PROC_1:
        begin
          address       = channel;
          dataIn        = {8'b0,rxPid};
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_INIT;
          wFinished     = 1;
        end
      STATE_READ_MESSAGE:
        begin
          address        = messageAddress;
          wUpdateMessage = 1;
          wMessage       = dataOut;
          wNextState     = STATE_WRITE_0;
        end
      STATE_WRITE_0:
        begin
          address       = channel;
          dataIn        = 0;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_1;
        end
      STATE_WRITE_1:
        begin
          address       = channel;
          dataIn        = 0;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_INIT;
          wFinished     = 1;
        end
    endcase
  end

endmodule