data/full_repos/permissive/114811571/test/samples/adder/adder.v
data/verilator_xmls/3cd522fb-4bf2-4395-845d-861fdbfa98c7.xml
module cla_full_adder(
		input	a,
		input	b,
		input	c,
		output	g,
		output	p,
		output	s);

	assign g = a & b;
	assign p = a ^ b;
	assign s = a ^ (b ^ c);

endmodule
module cla_full_adder(
		input	a,
		input	b,
		input	c,
		output	g,
		output	p,
		output	s);


	assign g = a & b;
	assign p = a ^ b;
	assign s = a ^ (b ^ c);

endmodule