data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/inst_cache.v
1: b'%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/inst_cache.v:28: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/inst_cache.v:38: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] addr,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/inst_cache.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] addr,  \n                    ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/inst_cache.v:41: Define or directive not defined: \'`RAW_INST_BUS\'\n    output reg [`RAW_INST_BUS] data\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/inst_cache.v:47: syntax error, unexpected initial\n    initial begin\n    ^~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module inst_cache#(
    parameter DATA_WIDTH = 32,
    parameter DATA_PER_BYTE_WIDTH = 2
)(
    input clk,
    input rst_n,


    input [`DATA_BUS] addr,
    

    output reg [`RAW_INST_BUS] data
    );

    reg [7:0] dat[0:127];
    integer i;
    
    initial begin
        $readmemb("test_single_cycle.txt", dat);
    end
    

    always @*
    begin
        data[31:24] <= dat[addr    ];
        data[23:16] <= dat[addr + 1];
        data[15: 8] <= dat[addr + 2];
        data[ 7: 0] <= dat[addr + 3];
    end
endmodule
module inst_cache#(
    parameter DATA_WIDTH = 32,
    parameter DATA_PER_BYTE_WIDTH = 2
)(
    input clk,
    input rst_n,


    input [`DATA_BUS] addr,
    

    output reg [`RAW_INST_BUS] data
    );


    reg [7:0] dat[0:127];
    integer i;
    
    initial begin
        $readmemb("test_single_cycle.txt", dat);
    end
    

    always @*
    begin
        data[31:24] <= dat[addr    ];
        data[23:16] <= dat[addr + 1];
        data[15: 8] <= dat[addr + 2];
        data[ 7: 0] <= dat[addr + 3];
    end
endmodule