data/full_repos/permissive/171756809/synchronous_reset_timer.v
data/verilator_xmls/4ab9a450-9d1c-4cf7-9568-6494b841dbea.xml
module synchronous_reset_timer(input wire clk, output wire reset_out, input wire reset_in);
	parameter LENGTH=7;

	reg [$clog2(LENGTH+1)-1:0] timer = LENGTH;
	assign reset_out = |timer;

	always @(posedge clk, posedge reset_in) begin
		if(reset_in) begin
			timer <= LENGTH;
		end else if(reset_out) begin
			timer <= timer - 1;
		end
	end

endmodule
module synchronous_reset_timer(input wire clk, output wire reset_out, input wire reset_in);

	parameter LENGTH=7;

	reg [$clog2(LENGTH+1)-1:0] timer = LENGTH;
	assign reset_out = |timer;

	always @(posedge clk, posedge reset_in) begin
		if(reset_in) begin
			timer <= LENGTH;
		end else if(reset_out) begin
			timer <= timer - 1;
		end
	end

endmodule