data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:13: Define or directive not defined: '`VTX_CHECKER_MODULE_BEGIN'\n`VTX_CHECKER_MODULE_BEGIN(instr_aesmix_dec)\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:13: syntax error, unexpected '('\n`VTX_CHECKER_MODULE_BEGIN(instr_aesmix_dec)\n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:15: Define or directive not defined: '`CRS1'\nwire [7:0] t0 = `CRS1[ 7: 0];\n                ^~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:15: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\nwire [7:0] t0 = `CRS1[ 7: 0];\n                     ^\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:16: Define or directive not defined: '`CRS1'\nwire [7:0] t1 = `CRS1[15: 8];\n                ^~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:16: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\nwire [7:0] t1 = `CRS1[15: 8];\n                     ^\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:17: Define or directive not defined: '`CRS2'\nwire [7:0] t2 = `CRS2[23:16];\n                ^~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:17: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\nwire [7:0] t2 = `CRS2[23:16];\n                     ^\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:18: Define or directive not defined: '`CRS2'\nwire [7:0] t3 = `CRS2[31:24];\n                ^~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:18: syntax error, unexpected '[', expecting TYPE-IDENTIFIER\nwire [7:0] t3 = `CRS2[31:24];\n                     ^\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:42: syntax error, unexpected always\nalways @(*) begin\n^~~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:52: Define or directive not defined: '`VTX_CHECK_INSTR_BEGIN'\n`VTX_CHECK_INSTR_BEGIN(aesmix_dec) \n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:56: Define or directive not defined: '`VTX_ASSERT_CRD_VALUE_IS'\n    `VTX_ASSERT_CRD_VALUE_IS(mixdec_expected);\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:59: Define or directive not defined: '`VTX_ASSERT_RESULT_IS'\n    `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS)\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:62: Define or directive not defined: '`VTX_ASSERT_WEN_IS_CLEAR'\n    `VTX_ASSERT_WEN_IS_CLEAR\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:64: Define or directive not defined: '`VTX_CHECK_INSTR_END'\n`VTX_CHECK_INSTR_END(aesmix_dec)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169382915/verif/formal/fml_chk_instr_aesmix_dec.v:66: Define or directive not defined: '`VTX_CHECKER_MODULE_END'\n`VTX_CHECKER_MODULE_END(instr_aesmix_dec)\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n"
function [7:0] xt2;
    input[7:0] a;
    xt2 = a[7] ? (a << 1) ^ 8'h1b : (a<<1);
endfunction
function [7:0] xt2;

    input[7:0] a;
    xt2 = a[7] ? (a << 1) ^ 8'h1b : (a<<1);
endfunction