data/full_repos/permissive/115784205/src/rtl/ubbefpga1.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/59f9298e-acf4-428c-ae80-c5a22621e3f1.xml
module ubbefpga(
                input wire          clk,
                input wire          reset_n,

                input wire          led_inc,
                output wire [7 : 0] led
                );





  parameter DELAY = 32'h0100000;





  reg [31 : 0] delay_ctr_reg;
  reg [31 : 0] delay_ctr_new;

  reg [7 : 0]  led_reg;
  reg [7 : 0]  led_new;
  reg          led_we;





  assign led = led_reg;





  always @ (posedge clk or negedge reset_n)
    begin : reg_update
      if (!reset_n)
        begin
          delay_ctr_reg <= 32'h0;
          led_reg       <= 8'h0;
        end
      else
        begin
          delay_ctr_reg <= delay_ctr_new;

          if (led_we)
            led_reg <= led_new;
        end
    end





  always @*
    begin : delay_ctr
      if (delay_ctr_reg == DELAY)
        begin
          delay_ctr_new = 32'h0;
        end
      else
        delay_ctr_new = delay_ctr_reg + 1'b1;
    end





  always @*
    begin : led_toggle
      led_new = 8'h00;
      led_we  = 0;

      if (delay_ctr_reg == 32'h0)
        begin
          if (led_inc)
            begin
              led_new = led_reg + 1'b1;
              led_we  = 1;
            end
        end
    end

endmodule
module ubbefpga(
                input wire          clk,
                input wire          reset_n,

                input wire          led_inc,
                output wire [7 : 0] led
                );






  parameter DELAY = 32'h0100000;





  reg [31 : 0] delay_ctr_reg;
  reg [31 : 0] delay_ctr_new;

  reg [7 : 0]  led_reg;
  reg [7 : 0]  led_new;
  reg          led_we;





  assign led = led_reg;





  always @ (posedge clk or negedge reset_n)
    begin : reg_update
      if (!reset_n)
        begin
          delay_ctr_reg <= 32'h0;
          led_reg       <= 8'h0;
        end
      else
        begin
          delay_ctr_reg <= delay_ctr_new;

          if (led_we)
            led_reg <= led_new;
        end
    end





  always @*
    begin : delay_ctr
      if (delay_ctr_reg == DELAY)
        begin
          delay_ctr_new = 32'h0;
        end
      else
        delay_ctr_new = delay_ctr_reg + 1'b1;
    end





  always @*
    begin : led_toggle
      led_new = 8'h00;
      led_we  = 0;

      if (delay_ctr_reg == 32'h0)
        begin
          if (led_inc)
            begin
              led_new = led_reg + 1'b1;
              led_we  = 1;
            end
        end
    end

endmodule