data/full_repos/permissive/114091260/material/CPU设计代码/第二步/VGA显示/i_memory.v
1: b'%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:2: Cannot find include file: def.v\n`include "def.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba,data/full_repos/permissive/114091260/def.v\n             data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba,data/full_repos/permissive/114091260/def.v.v\n             data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba,data/full_repos/permissive/114091260/def.v.sv\n             def.v\n             def.v.v\n             def.v.sv\n             obj_dir/def.v\n             obj_dir/def.v.v\n             obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:20: Define or directive not defined: \'`LOAD\'\n     RAM[0] <= {`LOAD, `gr1, 1\'b0, `gr0, 4\'b0000};\n                ^~~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:20: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[0] <= {`LOAD, `gr1, 1\'b0, `gr0, 4\'b0000};\n                     ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:20: Define or directive not defined: \'`gr1\'\n     RAM[0] <= {`LOAD, `gr1, 1\'b0, `gr0, 4\'b0000};\n                       ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:20: Define or directive not defined: \'`gr0\'\n     RAM[0] <= {`LOAD, `gr1, 1\'b0, `gr0, 4\'b0000};\n                                   ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:21: Define or directive not defined: \'`LOAD\'\n     RAM[1] <= {`LOAD, `gr2, 1\'b0, `gr0, 4\'b0001};\n                ^~~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:21: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[1] <= {`LOAD, `gr2, 1\'b0, `gr0, 4\'b0001};\n                     ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:21: Define or directive not defined: \'`gr2\'\n     RAM[1] <= {`LOAD, `gr2, 1\'b0, `gr0, 4\'b0001};\n                       ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:21: Define or directive not defined: \'`gr0\'\n     RAM[1] <= {`LOAD, `gr2, 1\'b0, `gr0, 4\'b0001};\n                                   ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:22: Define or directive not defined: \'`NOP\'\n     RAM[2] <= {`NOP, 11\'b000_0000_0000};\n                ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:22: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[2] <= {`NOP, 11\'b000_0000_0000};\n                    ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:23: Define or directive not defined: \'`NOP\'\n     RAM[3] <= {`NOP, 11\'b000_0000_0000};\n                ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:23: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[3] <= {`NOP, 11\'b000_0000_0000};\n                    ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:24: Define or directive not defined: \'`NOP\'\n     RAM[4] <= {`NOP, 11\'b000_0000_0000};\n                ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:24: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[4] <= {`NOP, 11\'b000_0000_0000};\n                    ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:25: Define or directive not defined: \'`ADD\'\n     RAM[5] <= {`ADD, `gr3, 1\'b0, `gr1, 1\'b0, `gr2};\n                ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:25: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[5] <= {`ADD, `gr3, 1\'b0, `gr1, 1\'b0, `gr2};\n                    ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:25: Define or directive not defined: \'`gr3\'\n     RAM[5] <= {`ADD, `gr3, 1\'b0, `gr1, 1\'b0, `gr2};\n                      ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:25: Define or directive not defined: \'`gr1\'\n     RAM[5] <= {`ADD, `gr3, 1\'b0, `gr1, 1\'b0, `gr2};\n                                  ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:25: Define or directive not defined: \'`gr2\'\n     RAM[5] <= {`ADD, `gr3, 1\'b0, `gr1, 1\'b0, `gr2};\n                                              ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:26: Define or directive not defined: \'`NOP\'\n     RAM[6] <= {`NOP, 11\'b000_0000_0000};\n                ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:26: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[6] <= {`NOP, 11\'b000_0000_0000};\n                    ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:27: Define or directive not defined: \'`NOP\'\n     RAM[7] <= {`NOP, 11\'b000_0000_0000};\n                ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:27: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[7] <= {`NOP, 11\'b000_0000_0000};\n                    ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:28: Define or directive not defined: \'`NOP\'\n     RAM[8] <= {`NOP, 11\'b000_0000_0000};\n                ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:28: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[8] <= {`NOP, 11\'b000_0000_0000};\n                    ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:29: Define or directive not defined: \'`STORE\'\n     RAM[9] <= {`STORE, `gr3, 1\'b0, `gr0, 4\'b0010};\n                ^~~~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:29: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[9] <= {`STORE, `gr3, 1\'b0, `gr0, 4\'b0010};\n                      ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:29: Define or directive not defined: \'`gr3\'\n     RAM[9] <= {`STORE, `gr3, 1\'b0, `gr0, 4\'b0010};\n                        ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:29: Define or directive not defined: \'`gr0\'\n     RAM[9] <= {`STORE, `gr3, 1\'b0, `gr0, 4\'b0010};\n                                    ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:30: Define or directive not defined: \'`BNZ\'\n     RAM[10] <= {`BNZ, `gr1, 8\'b0001_0000};\n                 ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:30: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[10] <= {`BNZ, `gr1, 8\'b0001_0000};\n                     ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:30: Define or directive not defined: \'`gr1\'\n     RAM[10] <= {`BNZ, `gr1, 8\'b0001_0000};\n                       ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:31: Define or directive not defined: \'`NOP\'\n     RAM[11] <= {`NOP, 11\'b000_0000_0000};\n                 ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:31: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[11] <= {`NOP, 11\'b000_0000_0000};\n                     ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:32: Define or directive not defined: \'`NOP\'\n     RAM[12] <= {`NOP, 11\'b000_0000_0000};\n                 ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:32: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[12] <= {`NOP, 11\'b000_0000_0000};\n                     ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:33: Define or directive not defined: \'`NOP\'\n     RAM[13] <= {`NOP, 11\'b000_0000_0000};\n                 ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:33: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[13] <= {`NOP, 11\'b000_0000_0000};\n                     ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:34: Define or directive not defined: \'`CMP\'\n     RAM[187] <= {`CMP, 4\'b0000, `gr1, 1\'b0, `gr2};\n                  ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:34: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[187] <= {`CMP, 4\'b0000, `gr1, 1\'b0, `gr2};\n                      ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:34: Define or directive not defined: \'`gr1\'\n     RAM[187] <= {`CMP, 4\'b0000, `gr1, 1\'b0, `gr2};\n                                 ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:34: Define or directive not defined: \'`gr2\'\n     RAM[187] <= {`CMP, 4\'b0000, `gr1, 1\'b0, `gr2};\n                                             ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:35: Define or directive not defined: \'`HALT\'\n     RAM[188] <= {`HALT, 11\'b000_0000_0000};\n                  ^~~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:35: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     RAM[188] <= {`HALT, 11\'b000_0000_0000};\n                       ^\n%Error: Exiting due to 45 error(s)\n'
module i_memory(
    input clk,
    input rst,
    input [7:0] addr,
    input we,
    input [15:0] datain,
    output [15:0] dataout
    );

	reg [15:0] RAM[255:0];
	
	assign dataout = RAM[addr];
	always @(posedge clk or negedge rst)
		begin
			if (!rst)
				begin
					RAM[0] <= {`LOAD, `gr1, 1'b0, `gr0, 4'b0000};
					RAM[1] <= {`LOAD, `gr2, 1'b0, `gr0, 4'b0001};
					RAM[2] <= {`NOP, 11'b000_0000_0000};
					RAM[3] <= {`NOP, 11'b000_0000_0000};
					RAM[4] <= {`NOP, 11'b000_0000_0000};
					RAM[5] <= {`ADD, `gr3, 1'b0, `gr1, 1'b0, `gr2};
					RAM[6] <= {`NOP, 11'b000_0000_0000};
					RAM[7] <= {`NOP, 11'b000_0000_0000};
					RAM[8] <= {`NOP, 11'b000_0000_0000};
					RAM[9] <= {`STORE, `gr3, 1'b0, `gr0, 4'b0010};
					RAM[10] <= {`BNZ, `gr1, 8'b0001_0000};
					RAM[11] <= {`NOP, 11'b000_0000_0000};
					RAM[12] <= {`NOP, 11'b000_0000_0000};
					RAM[13] <= {`NOP, 11'b000_0000_0000};
					RAM[187] <= {`CMP, 4'b0000, `gr1, 1'b0, `gr2};
					RAM[188] <= {`HALT, 11'b000_0000_0000};
				end
			else if (we)
				RAM[addr] <= datain;
		end

endmodule
module i_memory(
    input clk,
    input rst,
    input [7:0] addr,
    input we,
    input [15:0] datain,
    output [15:0] dataout
    );


	reg [15:0] RAM[255:0];
	
	assign dataout = RAM[addr];
	always @(posedge clk or negedge rst)
		begin
			if (!rst)
				begin
					RAM[0] <= {`LOAD, `gr1, 1'b0, `gr0, 4'b0000};
					RAM[1] <= {`LOAD, `gr2, 1'b0, `gr0, 4'b0001};
					RAM[2] <= {`NOP, 11'b000_0000_0000};
					RAM[3] <= {`NOP, 11'b000_0000_0000};
					RAM[4] <= {`NOP, 11'b000_0000_0000};
					RAM[5] <= {`ADD, `gr3, 1'b0, `gr1, 1'b0, `gr2};
					RAM[6] <= {`NOP, 11'b000_0000_0000};
					RAM[7] <= {`NOP, 11'b000_0000_0000};
					RAM[8] <= {`NOP, 11'b000_0000_0000};
					RAM[9] <= {`STORE, `gr3, 1'b0, `gr0, 4'b0010};
					RAM[10] <= {`BNZ, `gr1, 8'b0001_0000};
					RAM[11] <= {`NOP, 11'b000_0000_0000};
					RAM[12] <= {`NOP, 11'b000_0000_0000};
					RAM[13] <= {`NOP, 11'b000_0000_0000};
					RAM[187] <= {`CMP, 4'b0000, `gr1, 1'b0, `gr2};
					RAM[188] <= {`HALT, 11'b000_0000_0000};
				end
			else if (we)
				RAM[addr] <= datain;
		end

endmodule