data/full_repos/permissive/212394344/PCIM_TB.v
 line:158: before: "forever"
1: b'%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #600;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #700;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:149: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:160: Unsupported: Ignoring delay on this delayed statement.\n   #500;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/PCIM_TB.v:157: Unsupported: Ignoring delay on this delayed statement.\n  #500\n  ^\n%Error: data/full_repos/permissive/212394344/PCIM_TB.v:40: Cannot find file containing module: \'PCIM\'\n PCIM uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/PCIM\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/PCIM.v\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/PCIM.sv\n             PCIM\n             PCIM.v\n             PCIM.sv\n             obj_dir/PCIM\n             obj_dir/PCIM.v\n             obj_dir/PCIM.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PCIM_TB;


	reg [7:0] jmp_loc;
	reg pc_mux_sel;
	reg Stall;
	reg Stall_pm;
	reg reset;
	reg clk;


	wire [23:0] ins;
	wire [7:0] Current_Address;


	PCIM uut (
		.ins(ins), 
		.Current_Address(Current_Address), 
		.jmp_loc(jmp_loc), 
		.pc_mux_sel(pc_mux_sel), 
		.Stall(Stall), 
		.Stall_pm(Stall_pm), 
		.reset(reset), 
		.clk(clk)
	);

	initial begin

		jmp_loc = 8;
		pc_mux_sel = 1;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;

		#200;
		
		jmp_loc = 8;
		pc_mux_sel = 1;
		Stall = 0;
		Stall_pm = 0;
		reset = 0;

		#600;

		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
		
		#700;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
		
		#1000;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
		
		#1000;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 1;
		Stall_pm = 0;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 1;
		Stall_pm = 0;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 1;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 1;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 1;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 1;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
			
		

		#100;
        


	end

	initial begin 
		clk=0;
		#500
		forever begin
			clk=~clk;
			#500;
		end
	end
      
endmodule
module PCIM_TB;



	reg [7:0] jmp_loc;
	reg pc_mux_sel;
	reg Stall;
	reg Stall_pm;
	reg reset;
	reg clk;


	wire [23:0] ins;
	wire [7:0] Current_Address;


	PCIM uut (
		.ins(ins), 
		.Current_Address(Current_Address), 
		.jmp_loc(jmp_loc), 
		.pc_mux_sel(pc_mux_sel), 
		.Stall(Stall), 
		.Stall_pm(Stall_pm), 
		.reset(reset), 
		.clk(clk)
	);

	initial begin

		jmp_loc = 8;
		pc_mux_sel = 1;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;

		#200;
		
		jmp_loc = 8;
		pc_mux_sel = 1;
		Stall = 0;
		Stall_pm = 0;
		reset = 0;

		#600;

		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
		
		#700;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
		
		#1000;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
		
		#1000;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 1;
		Stall_pm = 0;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 1;
		Stall_pm = 0;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 1;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 0;
		Stall = 0;
		Stall_pm = 1;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 1;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
		
		#500;
		
		jmp_loc = 8;
		pc_mux_sel = 1;
		Stall = 0;
		Stall_pm = 0;
		reset = 1;
			
		

		#100;
        


	end

	initial begin 
		clk=0;
		#500
		forever begin
			clk=~clk;
			#500;
		end
	end
      
endmodule