data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Arithmetic_Circuits/fadd.v
data/verilator_xmls/d856fd9f-ba50-4cbb-ac7f-9e9bb40f2d2f.xml
module top_module( 
    input a, b, cin,
    output cout, sum );
    assign {cout,sum} = a + b + cin;
endmodule
module top_module( 
    input a, b, cin,
    output cout, sum );

    assign {cout,sum} = a + b + cin;
endmodule