data/full_repos/permissive/193753641/test.v
data/verilator_xmls/e58558b6-c539-427d-be81-a688d8bbb239.xml
module test(out,in);
input [1:0] in;
output reg [1:0] out;

always@(*) begin
	case(in)
	 1: out=1;
	 2: out=2;
	 3: out=3;
	 0: out=0;
	endcase
	end
endmodule
module test(out,in);

input [1:0] in;
output reg [1:0] out;

always@(*) begin
	case(in)
	 1: out=1;
	 2: out=2;
	 3: out=3;
	 0: out=0;
	endcase
	end
endmodule