data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/Memory.v
None: at end of input
1: b'%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/Memory.v:2: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory,data/full_repos/permissive/180413071/constants.vh\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory,data/full_repos/permissive/180413071/constants.vh.v\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory,data/full_repos/permissive/180413071/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/Memory.v:3: Cannot find include file: files.vh\n`include "files.vh" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/Memory.v:6: Define or directive not defined: \'`RAM_FILE\'\nmodule Memory #(parameter PATH=`RAM_FILE) (\n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/Memory.v:6: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule Memory #(parameter PATH=`RAM_FILE) (\n                                        ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/Memory.v:16: Define or directive not defined: \'`WORD\'\n    input  [`WORD-1:0] address,\n            ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/Memory.v:17: Define or directive not defined: \'`WORD\'\n    input  [`WORD-1:0] write_data,\n            ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/Memory.v:22: Define or directive not defined: \'`WORD\'\n    output [`WORD-1:0] read_data\n            ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/Memory.v:25: Define or directive not defined: \'`WORD\'\n    wire [`WORD-1:0] write_data_modified;\n          ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/memory/Memory.v:27: syntax error, unexpected IDENTIFIER\n    branch_source branch_source(\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module Memory #(parameter PATH=`RAM_FILE) (
    input              read_clk,
    input              write_clk,
    input              reset,
    input              zero,
    input              negative,
    input              overflow,
    input              carry,
    input              mem_read,
    input              mem_write,
    input  [`WORD-1:0] address,
    input  [`WORD-1:0] write_data,
    input  [2:0]       branch_op,
    input  [10:0]      opcode,
    input  [4:0]       rt,
    output [1:0]       pc_src,
    output [`WORD-1:0] read_data
);

    wire [`WORD-1:0] write_data_modified;
    
    branch_source branch_source(
        .zero(zero),
        .negative(negative),
        .carry(carry),
        .overflow(overflow),
        .branch_op(branch_op),
        .conditional_branch(rt),
        .branch_src(pc_src)
    );
    
    write_data_modifier write_data_modifier(
        .opcode(opcode),
        .write_data_in(write_data),
        .write_data_out(write_data_modified)
    );
    
    data_memory #(.PATH(PATH)) data_memory(
        .read_clk(read_clk),
        .write_clk(write_clk),
        .reset(reset),
        .address(address),
        .mem_read(mem_read),
        .mem_write(mem_write),
        .read_data(read_data),
        .write_data(write_data_modified)
    );

endmodule
module Memory #(parameter PATH=`RAM_FILE) (
    input              read_clk,
    input              write_clk,
    input              reset,
    input              zero,
    input              negative,
    input              overflow,
    input              carry,
    input              mem_read,
    input              mem_write,
    input  [`WORD-1:0] address,
    input  [`WORD-1:0] write_data,
    input  [2:0]       branch_op,
    input  [10:0]      opcode,
    input  [4:0]       rt,
    output [1:0]       pc_src,
    output [`WORD-1:0] read_data
);


    wire [`WORD-1:0] write_data_modified;
    
    branch_source branch_source(
        .zero(zero),
        .negative(negative),
        .carry(carry),
        .overflow(overflow),
        .branch_op(branch_op),
        .conditional_branch(rt),
        .branch_src(pc_src)
    );
    
    write_data_modifier write_data_modifier(
        .opcode(opcode),
        .write_data_in(write_data),
        .write_data_out(write_data_modified)
    );
    
    data_memory #(.PATH(PATH)) data_memory(
        .read_clk(read_clk),
        .write_clk(write_clk),
        .reset(reset),
        .address(address),
        .mem_read(mem_read),
        .mem_write(mem_write),
        .read_data(read_data),
        .write_data(write_data_modified)
    );

endmodule