data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/clockdiv/clockdiv.v
data/verilator_xmls/0ab36863-31e0-4719-aa8b-8c1dbb261b53.xml
module clockdiv
#( parameter DIV=2 )
(
   input clk,
   output div_clk
);

localparam LOG2DIV = $clog2(DIV);

reg [ LOG2DIV - 1 : 0 ] count;
initial
  count = 0;
always @(posedge clk)
  count <= count + 'b01;

assign div_clk = count[LOG2DIV-1];

endmodule
module clockdiv
#( parameter DIV=2 )
(
   input clk,
   output div_clk
);


localparam LOG2DIV = $clog2(DIV);

reg [ LOG2DIV - 1 : 0 ] count;
initial
  count = 0;
always @(posedge clk)
  count <= count + 'b01;

assign div_clk = count[LOG2DIV-1];

endmodule