data/full_repos/permissive/172538466/hw/src/sim0/top_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/172538466/hw/src/sim0/top_tb.v:1: Cannot find include file: defs.vh\n`include "defs.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172538466/hw/src/sim0,data/full_repos/permissive/172538466/defs.vh\n             data/full_repos/permissive/172538466/hw/src/sim0,data/full_repos/permissive/172538466/defs.vh.v\n             data/full_repos/permissive/172538466/hw/src/sim0,data/full_repos/permissive/172538466/defs.vh.sv\n             defs.vh\n             defs.vh.v\n             defs.vh.sv\n             obj_dir/defs.vh\n             obj_dir/defs.vh.v\n             obj_dir/defs.vh.sv\n%Error: data/full_repos/permissive/172538466/hw/src/sim0/top_tb.v:2: Cannot find include file: sim0.vh\n`include "sim0.vh" \n         ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/172538466/hw/src/sim0/top_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n     #0 tb_clk = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/172538466/hw/src/sim0/top_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n     #0 tb_rst = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/172538466/hw/src/sim0/top_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n     #100 tb_rst = 0;\n     ^\n%Error: data/full_repos/permissive/172538466/hw/src/sim0/top_tb.v:65: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile("build/waveform0.vcd");\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/172538466/hw/src/sim0/top_tb.v:66: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars;\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/172538466/hw/src/sim0/top_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n     #2000000 $finish(0);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/172538466/hw/src/sim0/top_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n       # 100 $finish(20);\n       ^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n'
module top_tb();
   localparam FREQ = 12000000;

   reg tb_clk, tb_rst;
   wire uart_rx, uart_tx;

   wire [7:0] gpio_in;
   wire [7:0] gpio_out;
   wire [7:0] gpio_dir;


   assign gpio_in = (gpio_dir & gpio_out) | (~gpio_dir & 8'hAA);


   top dut
     (
      .CLK_I(tb_clk),
      .RESET_I(tb_rst),
      .RX_I(uart_rx),
      .TX_O(uart_tx),

      .PORT_I(gpio_in),
      .PORT_O(gpio_out),
      .DIR_O(gpio_dir)
      );



   stim_uart stim_uart0
     (
      .CLK_I(tb_clk),
      .RST_I(tb_rst),
      .RX_I(uart_tx),
      .TX_O(uart_rx)
      );


   listen_gpio listen_gpio0
     (
      .CLK_I(tb_clk),
      .RST_I(tb_rst),

      .IN_I(gpio_in),
      .OUT_I(gpio_out),
      .DIR_I(gpio_dir)
      );



   initial begin
     #0 tb_clk = 0;
     #0 tb_rst = 1;
     #100 tb_rst = 0;

     forever
       tb_clk = #(1000000000 / (FREQ * 2)) !tb_clk;
   end



   initial begin
     $dumpfile("build/waveform0.vcd");
     $dumpvars;


     #2000000 $finish(0);
   end


   always @(tb_clk)
     if(dut.cpu_lockup_o) begin
       $write("Existing due to cpu lockup\n");
       # 100 $finish(20);
     end

endmodule
module top_tb();

   localparam FREQ = 12000000;

   reg tb_clk, tb_rst;
   wire uart_rx, uart_tx;

   wire [7:0] gpio_in;
   wire [7:0] gpio_out;
   wire [7:0] gpio_dir;


   assign gpio_in = (gpio_dir & gpio_out) | (~gpio_dir & 8'hAA);


   top dut
     (
      .CLK_I(tb_clk),
      .RESET_I(tb_rst),
      .RX_I(uart_rx),
      .TX_O(uart_tx),

      .PORT_I(gpio_in),
      .PORT_O(gpio_out),
      .DIR_O(gpio_dir)
      );



   stim_uart stim_uart0
     (
      .CLK_I(tb_clk),
      .RST_I(tb_rst),
      .RX_I(uart_tx),
      .TX_O(uart_rx)
      );


   listen_gpio listen_gpio0
     (
      .CLK_I(tb_clk),
      .RST_I(tb_rst),

      .IN_I(gpio_in),
      .OUT_I(gpio_out),
      .DIR_I(gpio_dir)
      );



   initial begin
     #0 tb_clk = 0;
     #0 tb_rst = 1;
     #100 tb_rst = 0;

     forever
       tb_clk = #(1000000000 / (FREQ * 2)) !tb_clk;
   end



   initial begin
     $dumpfile("build/waveform0.vcd");
     $dumpvars;


     #2000000 $finish(0);
   end


   always @(tb_clk)
     if(dut.cpu_lockup_o) begin
       $write("Existing due to cpu lockup\n");
       # 100 $finish(20);
     end

endmodule