data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v
1: b'%Error: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:150: Cannot find file containing module: \'cfg_reg_to_axi4lite\'\ncfg_reg_to_axi4lite CFG2AXI4L (\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog,data/full_repos/permissive/208113388/cfg_reg_to_axi4lite\n             data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog,data/full_repos/permissive/208113388/cfg_reg_to_axi4lite.v\n             data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog,data/full_repos/permissive/208113388/cfg_reg_to_axi4lite.sv\n             cfg_reg_to_axi4lite\n             cfg_reg_to_axi4lite.v\n             cfg_reg_to_axi4lite.sv\n             obj_dir/cfg_reg_to_axi4lite\n             obj_dir/cfg_reg_to_axi4lite.v\n             obj_dir/cfg_reg_to_axi4lite.sv\n%Warning-WIDTH: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:229: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                                : ... In instance flash_sub_system\n             s_axi_bresp   = {2{g_axi_bresp[0]}};\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:233: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                                : ... In instance flash_sub_system\n             s_axi_rresp   = {2{g_axi_rresp[0]}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:239: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                                : ... In instance flash_sub_system\n             s_axi_bresp   = {2{g_axi_bresp[1]}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:243: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                                : ... In instance flash_sub_system\n             s_axi_rresp   = {2{g_axi_rresp[1]}};\n                           ^\n%Error: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:265: Cannot find file containing module: \'axi_hwicap_0\'\naxi_hwicap_0 ICAP (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:307: Cannot find file containing module: \'axi_quad_spi_0\'\naxi_quad_spi_0 QSPI (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:381: Cannot find file containing module: \'STARTUPE3\'\nSTARTUPE3 #(\n^~~~~~~~~\n%Error: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:492: Cannot find file containing module: \'IOBUF\'\nIOBUF IOBUF_DQ7 (\n^~~~~\n%Error: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:499: Cannot find file containing module: \'IOBUF\'\nIOBUF IOBUF_DQ6 (\n^~~~~\n%Error: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:506: Cannot find file containing module: \'IOBUF\'\nIOBUF IOBUF_DQ5 (\n^~~~~\n%Error: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:513: Cannot find file containing module: \'IOBUF\'\nIOBUF IOBUF_DQ4 (\n^~~~~\n%Error: data/full_repos/permissive/208113388/board_support_packages/ad9h3/verilog/flash_sub_system.v:520: Cannot find file containing module: \'IOBUF\'\nIOBUF IOBUF_CE2 (\n^~~~~\n%Error: Exiting due to 9 error(s), 4 warning(s)\n'
module flash_sub_system (




    input          axi_clk
  , input          spi_clk








  , input          icap_clk
  , input          reset_n




  , input    [1:0] cfg_axi_devsel
  , input   [13:0] cfg_axi_addr
  , input          cfg_axi_wren
  , input   [31:0] cfg_axi_wdata
  , input          cfg_axi_rden
  , output  [31:0] axi_cfg_rdata
  , output         axi_cfg_done
  , output   [1:0] axi_cfg_bresp
  , output   [1:0] axi_cfg_rresp
  , output   [7:0] axi_cfg_status
  , input          data_expand_enable
  , input          data_expand_dir

  , inout          FPGA_FLASH_CE2_L
  , inout          FPGA_FLASH_DQ4
  , inout          FPGA_FLASH_DQ5
  , inout          FPGA_FLASH_DQ6
  , inout          FPGA_FLASH_DQ7
);


wire  [13:0] s_axi_awaddr; 
wire         s_axi_awvalid;
reg          s_axi_awready; 
wire  [31:0] s_axi_wdata;
wire   [3:0] s_axi_wstrb; 
wire         s_axi_wvalid; 
reg          s_axi_wready;
reg    [1:0] s_axi_bresp;
reg          s_axi_bvalid; 
wire         s_axi_bready; 
wire  [13:0] s_axi_araddr; 
wire         s_axi_arvalid; 
reg          s_axi_arready;
reg   [31:0] s_axi_rdata; 
reg    [1:0] s_axi_rresp; 
reg          s_axi_rvalid;
wire         s_axi_rready;


wire [4:0] unused;
wire       icap_interrupt;
wire       qspi_interrupt;
wire       preq;
wire       eos;




`ifdef CFG_FLASH_SIM
  wire FPGA_FLASH_CE1_L;
  wire FPGA_FLASH_DQ0;
  wire FPGA_FLASH_DQ1;
  wire FPGA_FLASH_DQ2;
  wire FPGA_FLASH_DQ3;
  wire FPGA_FLASH_CCLK;
`endif


wire [7:0] spi_dq_i;   
wire [7:0] spi_dq_o;
wire [7:0] spi_dq_t;


wire       spi_sck_o;
wire       spi_sck_t;


wire [0:0] spi_ce1_o;
wire       spi_ce1_t;
wire       spi_ce2_o;
wire       spi_ce2_t;


assign axi_cfg_status[7:4]  = 4'b0;   
assign axi_cfg_status[3]    = qspi_interrupt;
assign axi_cfg_status[2]    = icap_interrupt;
assign axi_cfg_status[1]    = preq;
assign axi_cfg_status[0]    = eos;








cfg_reg_to_axi4lite CFG2AXI4L (
    .s_axi_aclk       ( axi_clk         )
  , .s_axi_aresetn    ( reset_n         )

  , .cfg_axi_addr     ( cfg_axi_addr    )
  , .cfg_axi_wren     ( cfg_axi_wren    )
  , .cfg_axi_wdata    ( cfg_axi_wdata   )
  , .cfg_axi_rden     ( cfg_axi_rden    )
  , .axi_cfg_rdata    ( axi_cfg_rdata   )
  , .axi_cfg_done     ( axi_cfg_done    )
  , .axi_cfg_bresp    ( axi_cfg_bresp   )
  , .axi_cfg_rresp    ( axi_cfg_rresp   )

  , .data_expand_enable ( data_expand_enable )
  , .data_expand_dir    ( data_expand_dir    )


  , .s_axi_awaddr     ( s_axi_awaddr    )
  , .s_axi_awvalid    ( s_axi_awvalid   )
  , .s_axi_awready    ( s_axi_awready   )
  , .s_axi_wdata      ( s_axi_wdata     )
  , .s_axi_wstrb      ( s_axi_wstrb     )
  , .s_axi_wvalid     ( s_axi_wvalid    )
  , .s_axi_wready     ( s_axi_wready    )
  , .s_axi_bresp      ( s_axi_bresp     )
  , .s_axi_bvalid     ( s_axi_bvalid    )
  , .s_axi_bready     ( s_axi_bready    )
  , .s_axi_araddr     ( s_axi_araddr    )
  , .s_axi_arvalid    ( s_axi_arvalid   )
  , .s_axi_arready    ( s_axi_arready   )
  , .s_axi_rdata      ( s_axi_rdata     )
  , .s_axi_rresp      ( s_axi_rresp     )
  , .s_axi_rvalid     ( s_axi_rvalid    )
  , .s_axi_rready     ( s_axi_rready    )
);













wire        g_axi_awvalid [1:0];
wire        g_axi_awready [1:0];


wire        g_axi_wvalid  [1:0];
wire        g_axi_wready  [1:0];
wire  [1:0] g_axi_bresp   [1:0];
wire        g_axi_bvalid  [1:0];


wire        g_axi_arvalid [1:0];
wire        g_axi_arready [1:0];
wire [31:0] g_axi_rdata   [1:0];
wire  [1:0] g_axi_rresp   [1:0];
wire        g_axi_rvalid  [1:0];



assign g_axi_awvalid[0] = (cfg_axi_devsel == 2'b00) ? s_axi_awvalid : 1'b0;
assign g_axi_wvalid[0]  = (cfg_axi_devsel == 2'b00) ? s_axi_wvalid  : 1'b0;
assign g_axi_arvalid[0] = (cfg_axi_devsel == 2'b00) ? s_axi_arvalid : 1'b0;

assign g_axi_awvalid[1] = (cfg_axi_devsel == 2'b01) ? s_axi_awvalid : 1'b0;
assign g_axi_wvalid[1]  = (cfg_axi_devsel == 2'b01) ? s_axi_wvalid  : 1'b0;
assign g_axi_arvalid[1] = (cfg_axi_devsel == 2'b01) ? s_axi_arvalid : 1'b0;

always @(*)
  case (cfg_axi_devsel)
    2'b00: begin
             s_axi_awready = g_axi_awready[0];
             s_axi_wready  = g_axi_wready[0];
             s_axi_bresp   = {2{g_axi_bresp[0]}};
             s_axi_bvalid  = g_axi_bvalid[0];
             s_axi_arready = g_axi_arready[0];
             s_axi_rdata   = g_axi_rdata[0];
             s_axi_rresp   = {2{g_axi_rresp[0]}};
             s_axi_rvalid  = g_axi_rvalid[0];
           end
    2'b01: begin
             s_axi_awready = g_axi_awready[1];
             s_axi_wready  = g_axi_wready[1];
             s_axi_bresp   = {2{g_axi_bresp[1]}};
             s_axi_bvalid  = g_axi_bvalid[1];
             s_axi_arready = g_axi_arready[1];
             s_axi_rdata   = g_axi_rdata[1];
             s_axi_rresp   = {2{g_axi_rresp[1]}};
             s_axi_rvalid  = g_axi_rvalid[1];
           end
    default: begin
             s_axi_awready = 1'b0;
             s_axi_wready  = 1'b0;
             s_axi_bresp   = 2'b11;
             s_axi_bvalid  = 1'b0;
             s_axi_arready = 1'b0;
             s_axi_rdata   = 32'h0000_0000;
             s_axi_rresp   = 2'b00;
             s_axi_rvalid  = 1'b0;
           end
  endcase








axi_hwicap_0 ICAP (
    .icap_clk       ( icap_clk           )
  , .eos_in         ( eos                )
  , .s_axi_aclk     ( axi_clk            )
  , .s_axi_aresetn  ( reset_n            )
  , .s_axi_awaddr   ( s_axi_awaddr[8:0]  )
  , .s_axi_awvalid  ( g_axi_awvalid[1]   )
  , .s_axi_awready  ( g_axi_awready[1]   )
  , .s_axi_wdata    ( s_axi_wdata        )
  , .s_axi_wstrb    ( s_axi_wstrb        )
  , .s_axi_wvalid   ( g_axi_wvalid[1]    )
  , .s_axi_wready   ( g_axi_wready[1]    )
  , .s_axi_bresp    ( g_axi_bresp[1]     )
  , .s_axi_bvalid   ( g_axi_bvalid[1]    )
  , .s_axi_bready   ( s_axi_bready       )
  , .s_axi_araddr   ( s_axi_araddr[8:0]  )
  , .s_axi_arvalid  ( g_axi_arvalid[1]   )
  , .s_axi_arready  ( g_axi_arready[1]   )
  , .s_axi_rdata    ( g_axi_rdata[1]     )
  , .s_axi_rresp    ( g_axi_rresp[1]     )
  , .s_axi_rvalid   ( g_axi_rvalid[1]    )
  , .s_axi_rready   ( s_axi_rready       )
  , .ip2intc_irpt   ( icap_interrupt     )









);
 
 







axi_quad_spi_0 QSPI (
    .ext_spi_clk    ( spi_clk            )
  , .s_axi_aclk     ( axi_clk            )
  , .s_axi_aresetn  ( reset_n            )

  , .s_axi_awaddr   ( s_axi_awaddr[6:0]  )
  , .s_axi_awvalid  ( g_axi_awvalid[0]   )
  , .s_axi_awready  ( g_axi_awready[0]   )
  , .s_axi_wdata    ( s_axi_wdata        )
  , .s_axi_wstrb    ( s_axi_wstrb        )
  , .s_axi_wvalid   ( g_axi_wvalid[0]    )
  , .s_axi_wready   ( g_axi_wready[0]    )
  , .s_axi_bresp    ( g_axi_bresp[0]     )
  , .s_axi_bvalid   ( g_axi_bvalid[0]    )
  , .s_axi_bready   ( s_axi_bready       )
  , .s_axi_araddr   ( s_axi_araddr[6:0]  )
  , .s_axi_arvalid  ( g_axi_arvalid[0]   )
  , .s_axi_arready  ( g_axi_arready[0]   )
  , .s_axi_rdata    ( g_axi_rdata[0]     )
  , .s_axi_rresp    ( g_axi_rresp[0]     )
  , .s_axi_rvalid   ( g_axi_rvalid[0]    )
  , .s_axi_rready   ( s_axi_rready       )

  , .io0_i          ( spi_dq_i[0]        )
  , .io0_o          ( spi_dq_o[0]        )
  , .io0_t          ( spi_dq_t[0]        )
  , .io1_i          ( spi_dq_i[1]        )
  , .io1_o          ( spi_dq_o[1]        )
  , .io1_t          ( spi_dq_t[1]        )
  , .io2_i          ( spi_dq_i[2]        )
  , .io2_o          ( spi_dq_o[2]        )
  , .io2_t          ( spi_dq_t[2]        )
  , .io3_i          ( spi_dq_i[3]        )
  , .io3_o          ( spi_dq_o[3]        )
  , .io3_t          ( spi_dq_t[3]        )
  , .sck_i          ( spi_sck_o          )
  , .sck_o          ( spi_sck_o          )
  , .sck_t          ( spi_sck_t          )
  , .ss_i           ( 1'b0               )
  , .ss_o           ( spi_ce1_o          )
  , .ss_t           ( spi_ce1_t          )

  , .io0_1_i        ( spi_dq_i[4]        )
  , .io0_1_o        ( spi_dq_o[4]        )
  , .io0_1_t        ( spi_dq_t[4]        )
  , .io1_1_i        ( spi_dq_i[5]        )
  , .io1_1_o        ( spi_dq_o[5]        )
  , .io1_1_t        ( spi_dq_t[5]        )
  , .io2_1_i        ( spi_dq_i[6]        )
  , .io2_1_o        ( spi_dq_o[6]        )
  , .io2_1_t        ( spi_dq_t[6]        )
  , .io3_1_i        ( spi_dq_i[7]        )
  , .io3_1_o        ( spi_dq_o[7]        )
  , .io3_1_t        ( spi_dq_t[7]        )
  , .ss_1_i         ( 1'b0               )
  , .ss_1_o         ( spi_ce2_o          )
  , .ss_1_t         ( spi_ce2_t          )

  , .ip2intc_irpt   ( qspi_interrupt     )
);












`ifndef CFG_FLASH_SIM

STARTUPE3 #(
   .PROG_USR      ( "FALSE" ),
   .SIM_CCLK_FREQ ( 10.0    )
   )
   STARTUP (
     .CFGCLK    ( unused[0]     )

   , .CFGMCLK   ( unused[1]     )
   , .DI        ( spi_dq_i[3:0] )
   , .EOS       ( eos           )
   , .PREQ      ( preq          )
   , .DO        ( spi_dq_o[3:0] )
   , .DTS       ( spi_dq_t[3:0] )
   , .FCSBO     ( spi_ce1_o     )
   , .FCSBTS    ( spi_ce1_t     )
   , .GSR       ( 1'b0          )
   , .GTS       ( 1'b0          )
   , .KEYCLEARB ( 1'b1          )
   , .PACK      ( 1'b0          )
   , .USRCCLKO  ( spi_sck_o     )
   , .USRCCLKTS ( spi_sck_t     )
   , .USRDONEO  ( 1'b1          )
   , .USRDONETS ( 1'b0          )
);
`endif







`ifdef CFG_FLASH_SIM



IOBUF IOBUF_CCLK (
    .O  ( unused[2]       )
  , .I  ( spi_sck_o       )
  , .IO ( FPGA_FLASH_CCLK )
  , .T  ( spi_sck_t       )
);

  IOBUF IOBUF_DQ3 (
      .O  ( spi_dq_i[3]    )
    , .I  ( spi_dq_o[3]    )
    , .IO ( FPGA_FLASH_DQ3 )
    , .T  ( spi_dq_t[3]    )
  );







IOBUF IOBUF_DQ2 (
    .O  ( spi_dq_i[2]    )
  , .I  ( spi_dq_o[2]    )
  , .IO ( FPGA_FLASH_DQ2 )
  , .T  ( spi_dq_t[2]    )
);

IOBUF IOBUF_DQ1 (
    .O  ( spi_dq_i[1]    )
  , .I  ( spi_dq_o[1]    )
  , .IO ( FPGA_FLASH_DQ1 )
  , .T  ( spi_dq_t[1]    )
);

IOBUF IOBUF_DQ0 (
    .O  ( spi_dq_i[0]    )
  , .I  ( spi_dq_o[0]    )
  , .IO ( FPGA_FLASH_DQ0 )
  , .T  ( spi_dq_t[0]    )
);

IOBUF IOBUF_CE1 (
    .O  ( unused[3]        )
  , .I  ( spi_ce1_o        )
  , .IO ( FPGA_FLASH_CE1_L )
  , .T  ( spi_ce1_o        )
);

`endif























IOBUF IOBUF_DQ7 (
    .O  ( spi_dq_i[7]    )
  , .I  ( spi_dq_o[7]    )
  , .IO ( FPGA_FLASH_DQ7 )
  , .T  ( spi_dq_t[7]    )
);

IOBUF IOBUF_DQ6 (
    .O  ( spi_dq_i[6]    )
  , .I  ( spi_dq_o[6]    )
  , .IO ( FPGA_FLASH_DQ6 )
  , .T  ( spi_dq_t[6]    )
);

IOBUF IOBUF_DQ5 (
    .O  ( spi_dq_i[5]    )
  , .I  ( spi_dq_o[5]    )
  , .IO ( FPGA_FLASH_DQ5 )
  , .T  ( spi_dq_t[5]    )
);

IOBUF IOBUF_DQ4 (
    .O  ( spi_dq_i[4]    )
  , .I  ( spi_dq_o[4]    )
  , .IO ( FPGA_FLASH_DQ4 )
  , .T  ( spi_dq_t[4]    )
);

IOBUF IOBUF_CE2 (
    .O  ( unused[4]        )
  , .I  ( spi_ce2_o        )
  , .IO ( FPGA_FLASH_CE2_L )
  , .T  ( spi_ce2_t        )
);




`ifdef CFG_FLASH_SIM
  pullup(FPGA_FLASH_DQ3); 
  pullup(FPGA_FLASH_DQ2); 
  pullup(FPGA_FLASH_CE1_L); 
`endif
pullup(FPGA_FLASH_DQ7); 
pullup(FPGA_FLASH_DQ6); 
pullup(FPGA_FLASH_CE2_L); 



`ifdef CFG_FLASH_SIM




  N25Qxxx FLASH_1(
      .S         ( FPGA_FLASH_CE1_L )
    , .C_        ( FPGA_FLASH_CCLK  )
    , .RESET_DQ3 ( FPGA_FLASH_DQ3   )
    , .DQ0       ( FPGA_FLASH_DQ0   )
    , .DQ1       ( FPGA_FLASH_DQ1   )
    , .Vcc       ( 32'h0000_0708    )
    , .Vpp_W_DQ2 ( FPGA_FLASH_DQ2   )
  );






  N25Qxxx FLASH_2(
      .S         ( FPGA_FLASH_CE2_L )
    , .C_        ( FPGA_FLASH_CCLK  )
    , .RESET_DQ3 ( FPGA_FLASH_DQ7   )
    , .DQ0       ( FPGA_FLASH_DQ4   )
    , .DQ1       ( FPGA_FLASH_DQ5   )
    , .Vcc       ( 32'h0000_0708    )
    , .Vpp_W_DQ2 ( FPGA_FLASH_DQ6   )
  );
`endif


endmodule
module flash_sub_system (




    input          axi_clk
  , input          spi_clk








  , input          icap_clk
  , input          reset_n




  , input    [1:0] cfg_axi_devsel
  , input   [13:0] cfg_axi_addr
  , input          cfg_axi_wren
  , input   [31:0] cfg_axi_wdata
  , input          cfg_axi_rden
  , output  [31:0] axi_cfg_rdata
  , output         axi_cfg_done
  , output   [1:0] axi_cfg_bresp
  , output   [1:0] axi_cfg_rresp
  , output   [7:0] axi_cfg_status
  , input          data_expand_enable
  , input          data_expand_dir

  , inout          FPGA_FLASH_CE2_L
  , inout          FPGA_FLASH_DQ4
  , inout          FPGA_FLASH_DQ5
  , inout          FPGA_FLASH_DQ6
  , inout          FPGA_FLASH_DQ7
);



wire  [13:0] s_axi_awaddr; 
wire         s_axi_awvalid;
reg          s_axi_awready; 
wire  [31:0] s_axi_wdata;
wire   [3:0] s_axi_wstrb; 
wire         s_axi_wvalid; 
reg          s_axi_wready;
reg    [1:0] s_axi_bresp;
reg          s_axi_bvalid; 
wire         s_axi_bready; 
wire  [13:0] s_axi_araddr; 
wire         s_axi_arvalid; 
reg          s_axi_arready;
reg   [31:0] s_axi_rdata; 
reg    [1:0] s_axi_rresp; 
reg          s_axi_rvalid;
wire         s_axi_rready;


wire [4:0] unused;
wire       icap_interrupt;
wire       qspi_interrupt;
wire       preq;
wire       eos;




`ifdef CFG_FLASH_SIM
  wire FPGA_FLASH_CE1_L;
  wire FPGA_FLASH_DQ0;
  wire FPGA_FLASH_DQ1;
  wire FPGA_FLASH_DQ2;
  wire FPGA_FLASH_DQ3;
  wire FPGA_FLASH_CCLK;
`endif


wire [7:0] spi_dq_i;   
wire [7:0] spi_dq_o;
wire [7:0] spi_dq_t;


wire       spi_sck_o;
wire       spi_sck_t;


wire [0:0] spi_ce1_o;
wire       spi_ce1_t;
wire       spi_ce2_o;
wire       spi_ce2_t;


assign axi_cfg_status[7:4]  = 4'b0;   
assign axi_cfg_status[3]    = qspi_interrupt;
assign axi_cfg_status[2]    = icap_interrupt;
assign axi_cfg_status[1]    = preq;
assign axi_cfg_status[0]    = eos;








cfg_reg_to_axi4lite CFG2AXI4L (
    .s_axi_aclk       ( axi_clk         )
  , .s_axi_aresetn    ( reset_n         )

  , .cfg_axi_addr     ( cfg_axi_addr    )
  , .cfg_axi_wren     ( cfg_axi_wren    )
  , .cfg_axi_wdata    ( cfg_axi_wdata   )
  , .cfg_axi_rden     ( cfg_axi_rden    )
  , .axi_cfg_rdata    ( axi_cfg_rdata   )
  , .axi_cfg_done     ( axi_cfg_done    )
  , .axi_cfg_bresp    ( axi_cfg_bresp   )
  , .axi_cfg_rresp    ( axi_cfg_rresp   )

  , .data_expand_enable ( data_expand_enable )
  , .data_expand_dir    ( data_expand_dir    )


  , .s_axi_awaddr     ( s_axi_awaddr    )
  , .s_axi_awvalid    ( s_axi_awvalid   )
  , .s_axi_awready    ( s_axi_awready   )
  , .s_axi_wdata      ( s_axi_wdata     )
  , .s_axi_wstrb      ( s_axi_wstrb     )
  , .s_axi_wvalid     ( s_axi_wvalid    )
  , .s_axi_wready     ( s_axi_wready    )
  , .s_axi_bresp      ( s_axi_bresp     )
  , .s_axi_bvalid     ( s_axi_bvalid    )
  , .s_axi_bready     ( s_axi_bready    )
  , .s_axi_araddr     ( s_axi_araddr    )
  , .s_axi_arvalid    ( s_axi_arvalid   )
  , .s_axi_arready    ( s_axi_arready   )
  , .s_axi_rdata      ( s_axi_rdata     )
  , .s_axi_rresp      ( s_axi_rresp     )
  , .s_axi_rvalid     ( s_axi_rvalid    )
  , .s_axi_rready     ( s_axi_rready    )
);













wire        g_axi_awvalid [1:0];
wire        g_axi_awready [1:0];


wire        g_axi_wvalid  [1:0];
wire        g_axi_wready  [1:0];
wire  [1:0] g_axi_bresp   [1:0];
wire        g_axi_bvalid  [1:0];


wire        g_axi_arvalid [1:0];
wire        g_axi_arready [1:0];
wire [31:0] g_axi_rdata   [1:0];
wire  [1:0] g_axi_rresp   [1:0];
wire        g_axi_rvalid  [1:0];



assign g_axi_awvalid[0] = (cfg_axi_devsel == 2'b00) ? s_axi_awvalid : 1'b0;
assign g_axi_wvalid[0]  = (cfg_axi_devsel == 2'b00) ? s_axi_wvalid  : 1'b0;
assign g_axi_arvalid[0] = (cfg_axi_devsel == 2'b00) ? s_axi_arvalid : 1'b0;

assign g_axi_awvalid[1] = (cfg_axi_devsel == 2'b01) ? s_axi_awvalid : 1'b0;
assign g_axi_wvalid[1]  = (cfg_axi_devsel == 2'b01) ? s_axi_wvalid  : 1'b0;
assign g_axi_arvalid[1] = (cfg_axi_devsel == 2'b01) ? s_axi_arvalid : 1'b0;

always @(*)
  case (cfg_axi_devsel)
    2'b00: begin
             s_axi_awready = g_axi_awready[0];
             s_axi_wready  = g_axi_wready[0];
             s_axi_bresp   = {2{g_axi_bresp[0]}};
             s_axi_bvalid  = g_axi_bvalid[0];
             s_axi_arready = g_axi_arready[0];
             s_axi_rdata   = g_axi_rdata[0];
             s_axi_rresp   = {2{g_axi_rresp[0]}};
             s_axi_rvalid  = g_axi_rvalid[0];
           end
    2'b01: begin
             s_axi_awready = g_axi_awready[1];
             s_axi_wready  = g_axi_wready[1];
             s_axi_bresp   = {2{g_axi_bresp[1]}};
             s_axi_bvalid  = g_axi_bvalid[1];
             s_axi_arready = g_axi_arready[1];
             s_axi_rdata   = g_axi_rdata[1];
             s_axi_rresp   = {2{g_axi_rresp[1]}};
             s_axi_rvalid  = g_axi_rvalid[1];
           end
    default: begin
             s_axi_awready = 1'b0;
             s_axi_wready  = 1'b0;
             s_axi_bresp   = 2'b11;
             s_axi_bvalid  = 1'b0;
             s_axi_arready = 1'b0;
             s_axi_rdata   = 32'h0000_0000;
             s_axi_rresp   = 2'b00;
             s_axi_rvalid  = 1'b0;
           end
  endcase








axi_hwicap_0 ICAP (
    .icap_clk       ( icap_clk           )
  , .eos_in         ( eos                )
  , .s_axi_aclk     ( axi_clk            )
  , .s_axi_aresetn  ( reset_n            )
  , .s_axi_awaddr   ( s_axi_awaddr[8:0]  )
  , .s_axi_awvalid  ( g_axi_awvalid[1]   )
  , .s_axi_awready  ( g_axi_awready[1]   )
  , .s_axi_wdata    ( s_axi_wdata        )
  , .s_axi_wstrb    ( s_axi_wstrb        )
  , .s_axi_wvalid   ( g_axi_wvalid[1]    )
  , .s_axi_wready   ( g_axi_wready[1]    )
  , .s_axi_bresp    ( g_axi_bresp[1]     )
  , .s_axi_bvalid   ( g_axi_bvalid[1]    )
  , .s_axi_bready   ( s_axi_bready       )
  , .s_axi_araddr   ( s_axi_araddr[8:0]  )
  , .s_axi_arvalid  ( g_axi_arvalid[1]   )
  , .s_axi_arready  ( g_axi_arready[1]   )
  , .s_axi_rdata    ( g_axi_rdata[1]     )
  , .s_axi_rresp    ( g_axi_rresp[1]     )
  , .s_axi_rvalid   ( g_axi_rvalid[1]    )
  , .s_axi_rready   ( s_axi_rready       )
  , .ip2intc_irpt   ( icap_interrupt     )









);
 
 







axi_quad_spi_0 QSPI (
    .ext_spi_clk    ( spi_clk            )
  , .s_axi_aclk     ( axi_clk            )
  , .s_axi_aresetn  ( reset_n            )

  , .s_axi_awaddr   ( s_axi_awaddr[6:0]  )
  , .s_axi_awvalid  ( g_axi_awvalid[0]   )
  , .s_axi_awready  ( g_axi_awready[0]   )
  , .s_axi_wdata    ( s_axi_wdata        )
  , .s_axi_wstrb    ( s_axi_wstrb        )
  , .s_axi_wvalid   ( g_axi_wvalid[0]    )
  , .s_axi_wready   ( g_axi_wready[0]    )
  , .s_axi_bresp    ( g_axi_bresp[0]     )
  , .s_axi_bvalid   ( g_axi_bvalid[0]    )
  , .s_axi_bready   ( s_axi_bready       )
  , .s_axi_araddr   ( s_axi_araddr[6:0]  )
  , .s_axi_arvalid  ( g_axi_arvalid[0]   )
  , .s_axi_arready  ( g_axi_arready[0]   )
  , .s_axi_rdata    ( g_axi_rdata[0]     )
  , .s_axi_rresp    ( g_axi_rresp[0]     )
  , .s_axi_rvalid   ( g_axi_rvalid[0]    )
  , .s_axi_rready   ( s_axi_rready       )

  , .io0_i          ( spi_dq_i[0]        )
  , .io0_o          ( spi_dq_o[0]        )
  , .io0_t          ( spi_dq_t[0]        )
  , .io1_i          ( spi_dq_i[1]        )
  , .io1_o          ( spi_dq_o[1]        )
  , .io1_t          ( spi_dq_t[1]        )
  , .io2_i          ( spi_dq_i[2]        )
  , .io2_o          ( spi_dq_o[2]        )
  , .io2_t          ( spi_dq_t[2]        )
  , .io3_i          ( spi_dq_i[3]        )
  , .io3_o          ( spi_dq_o[3]        )
  , .io3_t          ( spi_dq_t[3]        )
  , .sck_i          ( spi_sck_o          )
  , .sck_o          ( spi_sck_o          )
  , .sck_t          ( spi_sck_t          )
  , .ss_i           ( 1'b0               )
  , .ss_o           ( spi_ce1_o          )
  , .ss_t           ( spi_ce1_t          )

  , .io0_1_i        ( spi_dq_i[4]        )
  , .io0_1_o        ( spi_dq_o[4]        )
  , .io0_1_t        ( spi_dq_t[4]        )
  , .io1_1_i        ( spi_dq_i[5]        )
  , .io1_1_o        ( spi_dq_o[5]        )
  , .io1_1_t        ( spi_dq_t[5]        )
  , .io2_1_i        ( spi_dq_i[6]        )
  , .io2_1_o        ( spi_dq_o[6]        )
  , .io2_1_t        ( spi_dq_t[6]        )
  , .io3_1_i        ( spi_dq_i[7]        )
  , .io3_1_o        ( spi_dq_o[7]        )
  , .io3_1_t        ( spi_dq_t[7]        )
  , .ss_1_i         ( 1'b0               )
  , .ss_1_o         ( spi_ce2_o          )
  , .ss_1_t         ( spi_ce2_t          )

  , .ip2intc_irpt   ( qspi_interrupt     )
);












`ifndef CFG_FLASH_SIM

STARTUPE3 #(
   .PROG_USR      ( "FALSE" ),
   .SIM_CCLK_FREQ ( 10.0    )
   )
   STARTUP (
     .CFGCLK    ( unused[0]     )

   , .CFGMCLK   ( unused[1]     )
   , .DI        ( spi_dq_i[3:0] )
   , .EOS       ( eos           )
   , .PREQ      ( preq          )
   , .DO        ( spi_dq_o[3:0] )
   , .DTS       ( spi_dq_t[3:0] )
   , .FCSBO     ( spi_ce1_o     )
   , .FCSBTS    ( spi_ce1_t     )
   , .GSR       ( 1'b0          )
   , .GTS       ( 1'b0          )
   , .KEYCLEARB ( 1'b1          )
   , .PACK      ( 1'b0          )
   , .USRCCLKO  ( spi_sck_o     )
   , .USRCCLKTS ( spi_sck_t     )
   , .USRDONEO  ( 1'b1          )
   , .USRDONETS ( 1'b0          )
);
`endif







`ifdef CFG_FLASH_SIM



IOBUF IOBUF_CCLK (
    .O  ( unused[2]       )
  , .I  ( spi_sck_o       )
  , .IO ( FPGA_FLASH_CCLK )
  , .T  ( spi_sck_t       )
);

  IOBUF IOBUF_DQ3 (
      .O  ( spi_dq_i[3]    )
    , .I  ( spi_dq_o[3]    )
    , .IO ( FPGA_FLASH_DQ3 )
    , .T  ( spi_dq_t[3]    )
  );







IOBUF IOBUF_DQ2 (
    .O  ( spi_dq_i[2]    )
  , .I  ( spi_dq_o[2]    )
  , .IO ( FPGA_FLASH_DQ2 )
  , .T  ( spi_dq_t[2]    )
);

IOBUF IOBUF_DQ1 (
    .O  ( spi_dq_i[1]    )
  , .I  ( spi_dq_o[1]    )
  , .IO ( FPGA_FLASH_DQ1 )
  , .T  ( spi_dq_t[1]    )
);

IOBUF IOBUF_DQ0 (
    .O  ( spi_dq_i[0]    )
  , .I  ( spi_dq_o[0]    )
  , .IO ( FPGA_FLASH_DQ0 )
  , .T  ( spi_dq_t[0]    )
);

IOBUF IOBUF_CE1 (
    .O  ( unused[3]        )
  , .I  ( spi_ce1_o        )
  , .IO ( FPGA_FLASH_CE1_L )
  , .T  ( spi_ce1_o        )
);

`endif























IOBUF IOBUF_DQ7 (
    .O  ( spi_dq_i[7]    )
  , .I  ( spi_dq_o[7]    )
  , .IO ( FPGA_FLASH_DQ7 )
  , .T  ( spi_dq_t[7]    )
);

IOBUF IOBUF_DQ6 (
    .O  ( spi_dq_i[6]    )
  , .I  ( spi_dq_o[6]    )
  , .IO ( FPGA_FLASH_DQ6 )
  , .T  ( spi_dq_t[6]    )
);

IOBUF IOBUF_DQ5 (
    .O  ( spi_dq_i[5]    )
  , .I  ( spi_dq_o[5]    )
  , .IO ( FPGA_FLASH_DQ5 )
  , .T  ( spi_dq_t[5]    )
);

IOBUF IOBUF_DQ4 (
    .O  ( spi_dq_i[4]    )
  , .I  ( spi_dq_o[4]    )
  , .IO ( FPGA_FLASH_DQ4 )
  , .T  ( spi_dq_t[4]    )
);

IOBUF IOBUF_CE2 (
    .O  ( unused[4]        )
  , .I  ( spi_ce2_o        )
  , .IO ( FPGA_FLASH_CE2_L )
  , .T  ( spi_ce2_t        )
);




`ifdef CFG_FLASH_SIM
  pullup(FPGA_FLASH_DQ3); 
  pullup(FPGA_FLASH_DQ2); 
  pullup(FPGA_FLASH_CE1_L); 
`endif
pullup(FPGA_FLASH_DQ7); 
pullup(FPGA_FLASH_DQ6); 
pullup(FPGA_FLASH_CE2_L); 



`ifdef CFG_FLASH_SIM




  N25Qxxx FLASH_1(
      .S         ( FPGA_FLASH_CE1_L )
    , .C_        ( FPGA_FLASH_CCLK  )
    , .RESET_DQ3 ( FPGA_FLASH_DQ3   )
    , .DQ0       ( FPGA_FLASH_DQ0   )
    , .DQ1       ( FPGA_FLASH_DQ1   )
    , .Vcc       ( 32'h0000_0708    )
    , .Vpp_W_DQ2 ( FPGA_FLASH_DQ2   )
  );






  N25Qxxx FLASH_2(
      .S         ( FPGA_FLASH_CE2_L )
    , .C_        ( FPGA_FLASH_CCLK  )
    , .RESET_DQ3 ( FPGA_FLASH_DQ7   )
    , .DQ0       ( FPGA_FLASH_DQ4   )
    , .DQ1       ( FPGA_FLASH_DQ5   )
    , .Vcc       ( 32'h0000_0708    )
    , .Vpp_W_DQ2 ( FPGA_FLASH_DQ6   )
  );
`endif


endmodule