data/full_repos/permissive/206169433/pipeline/register.v
data/verilator_xmls/ad8b3fa0-767d-4905-8d18-ea44e05f9ff0.xml
module register(clk, read1, read2, out1, out2, write_address, write_Data, write);
    input clk, write;
    input [4:0] read1, read2, write_address;
    input [31:0] write_Data;
    output [31:0] out1, out2;

    reg [31:0] regs [0:31];
    integer i;


    initial begin
      for(i=0; i<32; i=i+1)
        regs[i] = 32'b0;
    end


    assign out1 = regs[read1];
    assign out2 = regs[read2];
    
    always @ (negedge clk) begin
        if (write == 1)
            regs[write_address] <= write_Data;
    end

endmodule
module register(clk, read1, read2, out1, out2, write_address, write_Data, write);

    input clk, write;
    input [4:0] read1, read2, write_address;
    input [31:0] write_Data;
    output [31:0] out1, out2;

    reg [31:0] regs [0:31];
    integer i;


    initial begin
      for(i=0; i<32; i=i+1)
        regs[i] = 32'b0;
    end


    assign out1 = regs[read1];
    assign out2 = regs[read2];
    
    always @ (negedge clk) begin
        if (write == 1)
            regs[write_address] <= write_Data;
    end

endmodule