data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/txd.v
None: at end of input
1: b'%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/txd.v:14: Cannot find include file: .\\\\src\\\\head_uart.v\n`include    ".\\\\src\\\\head_uart.v" \n            ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v.v\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v.sv\n             .\\\\src\\\\head_uart.v\n             .\\\\src\\\\head_uart.v.v\n             .\\\\src\\\\head_uart.v.sv\n             obj_dir/.\\\\src\\\\head_uart.v\n             obj_dir/.\\\\src\\\\head_uart.v.v\n             obj_dir/.\\\\src\\\\head_uart.v.sv\n%Error: Exiting due to 1 error(s)\n'
module  trans_reg( d_in, load, shift, txd, clk, rst ) ;
    input   [7:0]                   d_in ;
    input                           load ;
    input                           shift ;
    output                          txd ;
    input                           clk ;
    input                           rst ;

    reg     [10:0]                  t_reg ;
    integer                         i ;


    assign  txd = t_reg[0] ;
    

    always  @( posedge clk or posedge rst )
        if ( rst )
            t_reg <= 'h7FF ;
        else
            if ( load )
                begin 
                    t_reg[10]    <= 1'b1 ;
                    t_reg[9:2]   <= d_in ;
                    t_reg[1]     <= 1'b0 ;
                    t_reg[0]     <= 1'b1 ;
                end
            else
                if ( shift )
                    for ( i=1; i<=10; i=i+1 )
                        t_reg[i-1] <= t_reg[i] ;
    
endmodule
module  trans_reg( d_in, load, shift, txd, clk, rst ) ;

    input   [7:0]                   d_in ;
    input                           load ;
    input                           shift ;
    output                          txd ;
    input                           clk ;
    input                           rst ;

    reg     [10:0]                  t_reg ;
    integer                         i ;


    assign  txd = t_reg[0] ;
    

    always  @( posedge clk or posedge rst )
        if ( rst )
            t_reg <= 'h7FF ;
        else
            if ( load )
                begin 
                    t_reg[10]    <= 1'b1 ;
                    t_reg[9:2]   <= d_in ;
                    t_reg[1]     <= 1'b0 ;
                    t_reg[0]     <= 1'b1 ;
                end
            else
                if ( shift )
                    for ( i=1; i<=10; i=i+1 )
                        t_reg[i-1] <= t_reg[i] ;
    
endmodule