data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:50: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 bits.\n                                                                                           : ... In instance use_counter\n    wan=zong_counter_data/10000;\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:51: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                           : ... In instance use_counter\n    qian=zong_counter_data/1000-wan*10;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:52: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                           : ... In instance use_counter\n    bai=zong_counter_data/100-wan*100-qian*10;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:53: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                           : ... In instance use_counter\n    shi=zong_counter_data/10-wan*1000-qian*100-bai*10;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:54: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                           : ... In instance use_counter\n    ge=zong_counter_data-wan*10000-qian*1000-bai*100-shi*10;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:56: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 bits.\n                                                                                           : ... In instance use_counter\n    tiao_qian=tiao_jian_counter_data/1000;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:57: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                           : ... In instance use_counter\n    tiao_bai=tiao_jian_counter_data/100-tiao_qian*10;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:58: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                           : ... In instance use_counter\n    tiao_shi=tiao_jian_counter_data/10-tiao_qian*100-tiao_bai*10;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:59: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                           : ... In instance use_counter\n    tiao_ge=tiao_jian_counter_data-tiao_qian*1000-tiao_bai*100-tiao_shi*10;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:61: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 bits.\n                                                                                           : ... In instance use_counter\n    wu_tiao_qian=wu_tiao_jian_counter_data/1000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:62: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                           : ... In instance use_counter\n    wu_tiao_bai=wu_tiao_jian_counter_data/100-wu_tiao_qian*10;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:63: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                           : ... In instance use_counter\n    wu_tiao_shi=wu_tiao_jian_counter_data/10-wu_tiao_qian*100-wu_tiao_bai*10;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/use_counter.v:64: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                           : ... In instance use_counter\n    wu_tiao_ge=wu_tiao_jian_counter_data-wu_tiao_qian*1000-wu_tiao_bai*100-wu_tiao_shi*10;\n              ^\n%Error: Exiting due to 13 warning(s)\n'
module use_counter(zong_counter_data,tiao_jian_counter_data,wu_tiao_jian_counter_data,clk_n,rst,zhong_zhou_qi_incress_signal,tiao_jian_incress_signal,wu_tiao_jian_incress_signal,    wan,qian,bai,shi,ge,  tiao_qian,tiao_bai,tiao_shi,tiao_ge,  wu_tiao_qian,wu_tiao_bai,wu_tiao_shi,wu_tiao_ge);
input clk_n;
input rst;
input zhong_zhou_qi_incress_signal;
input tiao_jian_incress_signal;
input wu_tiao_jian_incress_signal;
output reg [3:0]wan;
output reg [3:0]qian;
output reg [3:0]bai;
output reg [3:0]shi;
output reg [3:0]ge;

output reg [3:0]tiao_qian;
output reg [3:0]tiao_bai;
output reg [3:0]tiao_shi;
output reg [3:0]tiao_ge;

output reg [3:0]wu_tiao_qian;
output reg [3:0]wu_tiao_bai;
output reg [3:0]wu_tiao_shi;
output reg [3:0]wu_tiao_ge;

initial begin
    wan=0;
 qian=0;
 bai=0;
 shi=0;
 ge=0;

 tiao_qian=0;
 tiao_bai=0;
 tiao_shi=0;
 tiao_ge=0;

 wu_tiao_qian=0;
 wu_tiao_bai=0;
 wu_tiao_shi=0;
 wu_tiao_ge=0;

end

input [31:0]zong_counter_data;
input [31:0]tiao_jian_counter_data;
input [31:0]wu_tiao_jian_counter_data;
always@(posedge clk_n)
begin
    wan=zong_counter_data/10000;
    qian=zong_counter_data/1000-wan*10;
    bai=zong_counter_data/100-wan*100-qian*10;
    shi=zong_counter_data/10-wan*1000-qian*100-bai*10;
    ge=zong_counter_data-wan*10000-qian*1000-bai*100-shi*10;
    
    tiao_qian=tiao_jian_counter_data/1000;
    tiao_bai=tiao_jian_counter_data/100-tiao_qian*10;
    tiao_shi=tiao_jian_counter_data/10-tiao_qian*100-tiao_bai*10;
    tiao_ge=tiao_jian_counter_data-tiao_qian*1000-tiao_bai*100-tiao_shi*10;
    
    wu_tiao_qian=wu_tiao_jian_counter_data/1000;
    wu_tiao_bai=wu_tiao_jian_counter_data/100-wu_tiao_qian*10;
    wu_tiao_shi=wu_tiao_jian_counter_data/10-wu_tiao_qian*100-wu_tiao_bai*10;
    wu_tiao_ge=wu_tiao_jian_counter_data-wu_tiao_qian*1000-wu_tiao_bai*100-wu_tiao_shi*10;
end    

endmodule
module use_counter(zong_counter_data,tiao_jian_counter_data,wu_tiao_jian_counter_data,clk_n,rst,zhong_zhou_qi_incress_signal,tiao_jian_incress_signal,wu_tiao_jian_incress_signal,    wan,qian,bai,shi,ge,  tiao_qian,tiao_bai,tiao_shi,tiao_ge,  wu_tiao_qian,wu_tiao_bai,wu_tiao_shi,wu_tiao_ge);

input clk_n;
input rst;
input zhong_zhou_qi_incress_signal;
input tiao_jian_incress_signal;
input wu_tiao_jian_incress_signal;
output reg [3:0]wan;
output reg [3:0]qian;
output reg [3:0]bai;
output reg [3:0]shi;
output reg [3:0]ge;

output reg [3:0]tiao_qian;
output reg [3:0]tiao_bai;
output reg [3:0]tiao_shi;
output reg [3:0]tiao_ge;

output reg [3:0]wu_tiao_qian;
output reg [3:0]wu_tiao_bai;
output reg [3:0]wu_tiao_shi;
output reg [3:0]wu_tiao_ge;

initial begin
    wan=0;
 qian=0;
 bai=0;
 shi=0;
 ge=0;

 tiao_qian=0;
 tiao_bai=0;
 tiao_shi=0;
 tiao_ge=0;

 wu_tiao_qian=0;
 wu_tiao_bai=0;
 wu_tiao_shi=0;
 wu_tiao_ge=0;

end

input [31:0]zong_counter_data;
input [31:0]tiao_jian_counter_data;
input [31:0]wu_tiao_jian_counter_data;
always@(posedge clk_n)
begin
    wan=zong_counter_data/10000;
    qian=zong_counter_data/1000-wan*10;
    bai=zong_counter_data/100-wan*100-qian*10;
    shi=zong_counter_data/10-wan*1000-qian*100-bai*10;
    ge=zong_counter_data-wan*10000-qian*1000-bai*100-shi*10;
    
    tiao_qian=tiao_jian_counter_data/1000;
    tiao_bai=tiao_jian_counter_data/100-tiao_qian*10;
    tiao_shi=tiao_jian_counter_data/10-tiao_qian*100-tiao_bai*10;
    tiao_ge=tiao_jian_counter_data-tiao_qian*1000-tiao_bai*100-tiao_shi*10;
    
    wu_tiao_qian=wu_tiao_jian_counter_data/1000;
    wu_tiao_bai=wu_tiao_jian_counter_data/100-wu_tiao_qian*10;
    wu_tiao_shi=wu_tiao_jian_counter_data/10-wu_tiao_qian*100-wu_tiao_bai*10;
    wu_tiao_ge=wu_tiao_jian_counter_data-wu_tiao_qian*1000-wu_tiao_bai*100-wu_tiao_shi*10;
end    

endmodule