data/full_repos/permissive/167489907/Examples/Mux8to1Nbit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/167489907/Examples/Mux8to1Nbit.v:9: Operator CASE expects 5 bits on the Case expression, but Case expression\'s VARREF \'FS\' generates 3 bits.\n                                                                             : ... In instance Mux8to1Nbit\n  case(FS)\n  ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Mux8to1Nbit(F, FS, I7, I6, I5, I4, I3, I2, I1, I0);

parameter N = 8;
output reg [N-1:0]F;
input [2:0] FS;
input [N-1:0] I7, I6, I5, I4, I3, I2, I1, I0;

	always @(*) begin
		case(FS)
			5'h00: F <= I0;
			5'h01: F <= I1;
			5'h02: F <= I2;
			5'h03: F <= I3;
			5'h04: F <= I4;
			5'h05: F <= I5;
			5'h06: F <= I6;
			5'h07: F <= I7;
		endcase
	end
endmodule
module Mux8to1Nbit(F, FS, I7, I6, I5, I4, I3, I2, I1, I0);


parameter N = 8;
output reg [N-1:0]F;
input [2:0] FS;
input [N-1:0] I7, I6, I5, I4, I3, I2, I1, I0;

	always @(*) begin
		case(FS)
			5'h00: F <= I0;
			5'h01: F <= I1;
			5'h02: F <= I2;
			5'h03: F <= I3;
			5'h04: F <= I4;
			5'h05: F <= I5;
			5'h06: F <= I6;
			5'h07: F <= I7;
		endcase
	end
endmodule