data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v
 line:272: before: "function"
1: b'%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:49: Cannot find include file: trellis.vh\n`include "trellis.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh.v\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh.sv\n             trellis.vh\n             trellis.vh.v\n             trellis.vh.sv\n             obj_dir/trellis.vh\n             obj_dir/trellis.vh.v\n             obj_dir/trellis.vh.sv\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:50: Cannot find include file: ultrascale.vh\n`include "ultrascale.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:66: Define or directive not defined: \'`SIG_CPLID_W\'\n     input [`SIG_CPLID_W-1:0]                CONFIG_COMPLETER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:74: Define or directive not defined: \'`SIG_RQ_TUSER_W\'\n     output [`SIG_RQ_TUSER_W-1:0]            S_AXIS_RQ_TUSER,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:86: Define or directive not defined: \'`SIG_FBE_W\'\n     input [`SIG_FBE_W-1:0]                  TXR_META_FDWBE, \n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:87: Define or directive not defined: \'`SIG_LBE_W\'\n     input [`SIG_LBE_W-1:0]                  TXR_META_LDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:88: Define or directive not defined: \'`SIG_ADDR_W\'\n     input [`SIG_ADDR_W-1:0]                 TXR_META_ADDR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:89: Define or directive not defined: \'`SIG_LEN_W\'\n     input [`SIG_LEN_W-1:0]                  TXR_META_LENGTH,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:90: Define or directive not defined: \'`SIG_TAG_W\'\n     input [`SIG_TAG_W-1:0]                  TXR_META_TAG,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:91: Define or directive not defined: \'`SIG_TC_W\'\n     input [`SIG_TC_W-1:0]                   TXR_META_TC,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:92: Define or directive not defined: \'`SIG_ATTR_W\'\n     input [`SIG_ATTR_W-1:0]                 TXR_META_ATTR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:93: Define or directive not defined: \'`SIG_TYPE_W\'\n     input [`SIG_TYPE_W-1:0]                 TXR_META_TYPE,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:100: Define or directive not defined: \'`UPKT_TXR_MAXHDR_W\'\n    localparam C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W;\n                                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W;\n                                                   ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:116: Define or directive not defined: \'`SIG_NONPAY_W\'\n    wire [`SIG_NONPAY_W-1:0]                 wTxHdrNonpayLen;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:117: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n    wire [`SIG_PACKETLEN_W-1:0]              wTxHdrPacketLen;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:118: Define or directive not defined: \'`SIG_LEN_W\'\n    wire [`SIG_LEN_W-1:0]                    wTxHdrPayloadLen; \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:177: Define or directive not defined: \'`SIG_LEN_W\'\n         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:178: Define or directive not defined: \'`SIG_NONPAY_W\'\n         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:179: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:188: Define or directive not defined: \'`SIG_CPLID_W\'\n         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),\n                                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:190: Define or directive not defined: \'`SIG_FBE_W\'\n         .TXR_META_FDWBE                (TXR_META_FDWBE[`SIG_FBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:191: Define or directive not defined: \'`SIG_LBE_W\'\n         .TXR_META_LDWBE                (TXR_META_LDWBE[`SIG_LBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:192: Define or directive not defined: \'`SIG_ADDR_W\'\n         .TXR_META_ADDR                 (TXR_META_ADDR[`SIG_ADDR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:193: Define or directive not defined: \'`SIG_LEN_W\'\n         .TXR_META_LENGTH               (TXR_META_LENGTH[`SIG_LEN_W-1:0]),\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:194: Define or directive not defined: \'`SIG_TAG_W\'\n         .TXR_META_TAG                  (TXR_META_TAG[`SIG_TAG_W-1:0]),\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:195: Define or directive not defined: \'`SIG_TC_W\'\n         .TXR_META_TC                   (TXR_META_TC[`SIG_TC_W-1:0]),\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:196: Define or directive not defined: \'`SIG_ATTR_W\'\n         .TXR_META_ATTR                 (TXR_META_ATTR[`SIG_ATTR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:197: Define or directive not defined: \'`SIG_TYPE_W\'\n         .TXR_META_TYPE                 (TXR_META_TYPE[`SIG_TYPE_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:225: Define or directive not defined: \'`SIG_LEN_W\'\n         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:226: Define or directive not defined: \'`SIG_NONPAY_W\'\n         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:227: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:264: Define or directive not defined: \'`SIG_RQ_TUSER_W\'\n         .S_AXIS_RQ_TUSER               (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:278: Define or directive not defined: \'`UPKT_TXR_MAXHDR_W\'\n      parameter C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W,\n                                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:278: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      parameter C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W,\n                                                    ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:280: syntax error, unexpected parameter, expecting IDENTIFIER\n      parameter C_MAX_PACKET_DWORDS = 10\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:281: syntax error, unexpected \')\', expecting \';\'\n      )\n      ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:290: Define or directive not defined: \'`SIG_CPLID_W\'\n     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:294: Define or directive not defined: \'`SIG_FBE_W\'\n     input [`SIG_FBE_W-1:0]        TXR_META_FDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:295: Define or directive not defined: \'`SIG_LBE_W\'\n     input [`SIG_LBE_W-1:0]        TXR_META_LDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:296: Define or directive not defined: \'`SIG_ADDR_W\'\n     input [`SIG_ADDR_W-1:0]       TXR_META_ADDR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:297: Define or directive not defined: \'`SIG_LEN_W\'\n     input [`SIG_LEN_W-1:0]        TXR_META_LENGTH,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:298: Define or directive not defined: \'`SIG_TAG_W\'\n     input [`SIG_TAG_W-1:0]        TXR_META_TAG,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:299: Define or directive not defined: \'`SIG_TC_W\'\n     input [`SIG_TC_W-1:0]         TXR_META_TC,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:300: Define or directive not defined: \'`SIG_ATTR_W\'\n     input [`SIG_ATTR_W-1:0]       TXR_META_ATTR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:301: Define or directive not defined: \'`SIG_TYPE_W\'\n     input [`SIG_TYPE_W-1:0]       TXR_META_TYPE,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:308: Define or directive not defined: \'`SIG_LEN_W\'\n     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:309: Define or directive not defined: \'`SIG_NONPAY_W\'\n     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:310: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n     output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:316: Define or directive not defined: \'`UPKT_TXR_MAXHDR_W\'\n    wire [`UPKT_TXR_MAXHDR_W-1:0]  wHdr;\n          ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module txr_formatter_ultrascale
    #(
      parameter C_PCI_DATA_WIDTH = 128,
      parameter C_PIPELINE_INPUT = 1,
      parameter C_PIPELINE_OUTPUT = 1,
      parameter C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W,
      parameter C_MAX_NONPAY_DWORDS = 5,
      parameter C_MAX_PACKET_DWORDS = 10
      )
    (

     input                         CLK,


     input                         RST_IN,


     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,


     input                         TXR_META_VALID,
     input [`SIG_FBE_W-1:0]        TXR_META_FDWBE,
     input [`SIG_LBE_W-1:0]        TXR_META_LDWBE,
     input [`SIG_ADDR_W-1:0]       TXR_META_ADDR,
     input [`SIG_LEN_W-1:0]        TXR_META_LENGTH,
     input [`SIG_TAG_W-1:0]        TXR_META_TAG,
     input [`SIG_TC_W-1:0]         TXR_META_TC,
     input [`SIG_ATTR_W-1:0]       TXR_META_ATTR,
     input [`SIG_TYPE_W-1:0]       TXR_META_TYPE,
     input                         TXR_META_EP,
     output                        TXR_META_READY,


     output                        TX_HDR_VALID,
     output [C_MAX_HDR_WIDTH-1:0]  TX_HDR,
     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,
     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,
     output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
     output                        TX_HDR_NOPAYLOAD,
     input                         TX_HDR_READY
     );

    wire                           wHdrNoPayload;
    wire [`UPKT_TXR_MAXHDR_W-1:0]  wHdr;
    
    wire                           wTxHdrReady;
    wire                           wTxHdrValid;
    wire [`UPKT_TXR_MAXHDR_W-1:0]  wTxHdr;
    wire [`SIG_NONPAY_W-1:0]       wTxHdrNonpayLen;
    wire [`SIG_PACKETLEN_W-1:0]    wTxHdrPacketLen;
    wire [`SIG_LEN_W-1:0]          wTxHdrPayloadLen; 
    wire                           wTxHdrNopayload;
    wire [`SIG_TYPE_W-1:0]         wTxHdrType;
    

    assign wHdr[`UPKT_TXR_ATYPE_R] = `UPKT_TXR_ATYPE_W'd0;
    assign wHdr[`UPKT_TXR_ADDR_R] = TXR_META_ADDR[63:2];
    assign wHdr[`UPKT_TXR_LENGTH_R] = {1'b0,TXR_META_LENGTH};
    assign wHdr[`UPKT_TXR_EP_R] = TXR_META_EP;
`ifdef BE_HACK
    assign wHdr[`UPKT_TXR_FBE_R] = TXR_META_FDWBE;
    assign wHdr[`UPKT_TXR_LBE_R] = TXR_META_LDWBE;
    assign wHdr[`UPKT_TXR_RSVD0_R] = 0;

`else
    assign wHdr[`UPKT_TXR_REQID_R] = CONFIG_COMPLETER_ID;
`endif

    assign wHdr[`UPKT_TXR_TAG_R] = TXR_META_TAG;
    assign wHdr[`UPKT_TXR_CPLID_R] = `UPKT_TXR_CPLID_W'd0;
    assign wHdr[`UPKT_TXR_REQIDEN_R] = 0;
    assign wHdr[`UPKT_TXR_TC_R] = TXR_META_TC;
    assign wHdr[`UPKT_TXR_ATTR_R] = TXR_META_ATTR;
    assign wHdr[`UPKT_TXR_TD_R] = `UPKT_TXR_TD_W'd0;

    assign wTxHdr[`UPKT_TXR_TYPE_R] = trellis_to_upkt_type(wTxHdrType);
    assign wTxHdrNopayload = ~wTxHdrType[`TRLS_TYPE_PAY_I];
    assign wTxHdrNonpayLen = 4;
    assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`UPKT_TXR_LENGTH_R];
    assign wTxHdrPacketLen = wTxHdrNonpayLen + wTxHdrPayloadLen;

    pipeline
        #(

          .C_DEPTH                         (C_PIPELINE_INPUT?1:0),
          .C_WIDTH                         (`UPKT_TXR_MAXHDR_W-1),
          .C_USE_MEMORY                    (0)
)
    input_inst
        (

         .WR_DATA_READY                  (TXR_META_READY),
         .RD_DATA                        ({wTxHdr[`UPKT_TXR_MAXHDR_W-1:(`UPKT_TXR_TYPE_I + `UPKT_TXR_TYPE_W)],
                                           wTxHdr[`UPKT_TXR_TYPE_I-1:0],
                                           wTxHdrType}),
         .RD_DATA_VALID                  (wTxHdrValid),

         .WR_DATA                        ({wHdr[`UPKT_TXR_MAXHDR_W-1:(`UPKT_TXR_TYPE_I + `UPKT_TXR_TYPE_W)],
                                           wHdr[`UPKT_TXR_TYPE_I-1:0],
                                           TXR_META_TYPE}),
         .WR_DATA_VALID                  (TXR_META_VALID),
         .RD_DATA_READY                  (wTxHdrReady),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    pipeline
        #(

          .C_DEPTH                         (C_PIPELINE_OUTPUT?1:0),
          .C_WIDTH                         (`UPKT_TXR_MAXHDR_W + 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
          .C_USE_MEMORY                    (0)
)
    output_inst
        (

         .WR_DATA_READY                  (wTxHdrReady),
         .RD_DATA                        ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
         .RD_DATA_VALID                  (TX_HDR_VALID),

         .WR_DATA                        ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
         .WR_DATA_VALID                  (wTxHdrValid),
         .RD_DATA_READY                  (TX_HDR_READY),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));
endmodule
module txr_formatter_ultrascale
    #(
      parameter C_PCI_DATA_WIDTH = 128,
      parameter C_PIPELINE_INPUT = 1,
      parameter C_PIPELINE_OUTPUT = 1,
      parameter C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W,
      parameter C_MAX_NONPAY_DWORDS = 5,
      parameter C_MAX_PACKET_DWORDS = 10
      )
    (

     input                         CLK,


     input                         RST_IN,


     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,


     input                         TXR_META_VALID,
     input [`SIG_FBE_W-1:0]        TXR_META_FDWBE,
     input [`SIG_LBE_W-1:0]        TXR_META_LDWBE,
     input [`SIG_ADDR_W-1:0]       TXR_META_ADDR,
     input [`SIG_LEN_W-1:0]        TXR_META_LENGTH,
     input [`SIG_TAG_W-1:0]        TXR_META_TAG,
     input [`SIG_TC_W-1:0]         TXR_META_TC,
     input [`SIG_ATTR_W-1:0]       TXR_META_ATTR,
     input [`SIG_TYPE_W-1:0]       TXR_META_TYPE,
     input                         TXR_META_EP,
     output                        TXR_META_READY,


     output                        TX_HDR_VALID,
     output [C_MAX_HDR_WIDTH-1:0]  TX_HDR,
     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,
     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,
     output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
     output                        TX_HDR_NOPAYLOAD,
     input                         TX_HDR_READY
     );


    wire                           wHdrNoPayload;
    wire [`UPKT_TXR_MAXHDR_W-1:0]  wHdr;
    
    wire                           wTxHdrReady;
    wire                           wTxHdrValid;
    wire [`UPKT_TXR_MAXHDR_W-1:0]  wTxHdr;
    wire [`SIG_NONPAY_W-1:0]       wTxHdrNonpayLen;
    wire [`SIG_PACKETLEN_W-1:0]    wTxHdrPacketLen;
    wire [`SIG_LEN_W-1:0]          wTxHdrPayloadLen; 
    wire                           wTxHdrNopayload;
    wire [`SIG_TYPE_W-1:0]         wTxHdrType;
    

    assign wHdr[`UPKT_TXR_ATYPE_R] = `UPKT_TXR_ATYPE_W'd0;
    assign wHdr[`UPKT_TXR_ADDR_R] = TXR_META_ADDR[63:2];
    assign wHdr[`UPKT_TXR_LENGTH_R] = {1'b0,TXR_META_LENGTH};
    assign wHdr[`UPKT_TXR_EP_R] = TXR_META_EP;
`ifdef BE_HACK
    assign wHdr[`UPKT_TXR_FBE_R] = TXR_META_FDWBE;
    assign wHdr[`UPKT_TXR_LBE_R] = TXR_META_LDWBE;
    assign wHdr[`UPKT_TXR_RSVD0_R] = 0;

`else
    assign wHdr[`UPKT_TXR_REQID_R] = CONFIG_COMPLETER_ID;
`endif

    assign wHdr[`UPKT_TXR_TAG_R] = TXR_META_TAG;
    assign wHdr[`UPKT_TXR_CPLID_R] = `UPKT_TXR_CPLID_W'd0;
    assign wHdr[`UPKT_TXR_REQIDEN_R] = 0;
    assign wHdr[`UPKT_TXR_TC_R] = TXR_META_TC;
    assign wHdr[`UPKT_TXR_ATTR_R] = TXR_META_ATTR;
    assign wHdr[`UPKT_TXR_TD_R] = `UPKT_TXR_TD_W'd0;

    assign wTxHdr[`UPKT_TXR_TYPE_R] = trellis_to_upkt_type(wTxHdrType);
    assign wTxHdrNopayload = ~wTxHdrType[`TRLS_TYPE_PAY_I];
    assign wTxHdrNonpayLen = 4;
    assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`UPKT_TXR_LENGTH_R];
    assign wTxHdrPacketLen = wTxHdrNonpayLen + wTxHdrPayloadLen;

    pipeline
        #(

          .C_DEPTH                         (C_PIPELINE_INPUT?1:0),
          .C_WIDTH                         (`UPKT_TXR_MAXHDR_W-1),
          .C_USE_MEMORY                    (0)
)
    input_inst
        (

         .WR_DATA_READY                  (TXR_META_READY),
         .RD_DATA                        ({wTxHdr[`UPKT_TXR_MAXHDR_W-1:(`UPKT_TXR_TYPE_I + `UPKT_TXR_TYPE_W)],
                                           wTxHdr[`UPKT_TXR_TYPE_I-1:0],
                                           wTxHdrType}),
         .RD_DATA_VALID                  (wTxHdrValid),

         .WR_DATA                        ({wHdr[`UPKT_TXR_MAXHDR_W-1:(`UPKT_TXR_TYPE_I + `UPKT_TXR_TYPE_W)],
                                           wHdr[`UPKT_TXR_TYPE_I-1:0],
                                           TXR_META_TYPE}),
         .WR_DATA_VALID                  (TXR_META_VALID),
         .RD_DATA_READY                  (wTxHdrReady),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));

    pipeline
        #(

          .C_DEPTH                         (C_PIPELINE_OUTPUT?1:0),
          .C_WIDTH                         (`UPKT_TXR_MAXHDR_W + 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
          .C_USE_MEMORY                    (0)
)
    output_inst
        (

         .WR_DATA_READY                  (wTxHdrReady),
         .RD_DATA                        ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
         .RD_DATA_VALID                  (TX_HDR_VALID),

         .WR_DATA                        ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
         .WR_DATA_VALID                  (wTxHdrValid),
         .RD_DATA_READY                  (TX_HDR_READY),


         .CLK                           (CLK),
         .RST_IN                        (RST_IN));
endmodule