data/full_repos/permissive/197264840/rtl/wrapper/sram_axi_adapter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/197264840/rtl/wrapper/sram_axi_adapter.v:55: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'mem_wstrb\' generates 4 bits.\n                                                                                      : ... In instance sram_axi_adapter\n assign mem_axi_arvalid = mem_cen && !mem_wstrb;\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sram_axi_adapter (
input        g_clk              ,
input        g_resetn           ,



output        mem_axi_awvalid   ,
input         mem_axi_awready   ,
output [31:0] mem_axi_awaddr    ,
output [ 2:0] mem_axi_awprot    ,

output        mem_axi_wvalid    ,
input         mem_axi_wready    ,
output [31:0] mem_axi_wdata     ,
output [ 3:0] mem_axi_wstrb     ,

input         mem_axi_bvalid    ,
output        mem_axi_bready    ,

output        mem_axi_arvalid   ,
input         mem_axi_arready   ,
output [31:0] mem_axi_araddr    ,
output [ 2:0] mem_axi_arprot    ,

input         mem_axi_rvalid    ,
output        mem_axi_rready    ,
input  [31:0] mem_axi_rdata     ,

input         mem_instr         ,
input         mem_cen           ,
output        mem_stall         ,
output        mem_error         ,
input  [31:0] mem_addr          ,
input  [31:0] mem_wdata         ,
input  [ 3:0] mem_wstrb         ,
output [31:0] mem_rdata
);
	reg ack_awvalid;
	reg ack_arvalid;
	reg ack_wvalid;
	reg xfer_done;

	assign mem_axi_awvalid = mem_cen && |mem_wstrb;
	assign mem_axi_awaddr = mem_addr;
	assign mem_axi_awprot = 0;

	assign mem_axi_arvalid = mem_cen && !mem_wstrb;
	assign mem_axi_araddr = mem_addr;
	assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;

	assign mem_axi_wvalid = mem_cen && |mem_wstrb && !ack_wvalid;
	assign mem_axi_wdata = mem_wdata;
	assign mem_axi_wstrb = mem_wstrb;

	wire   mem_ready = mem_axi_bvalid || mem_axi_rvalid;
    assign mem_stall = !mem_ready;
	assign mem_axi_bready = mem_cen && |mem_wstrb;

	assign mem_axi_rready = 1'b1;
	assign mem_rdata = mem_axi_rdata;
    

    assign mem_error = 1'b0;

	always @(posedge g_clk) begin
		if (!g_resetn) begin
			ack_awvalid <= 0;
		end else begin
			xfer_done <= mem_cen && mem_ready;
			if (mem_axi_awready && mem_axi_awvalid)
				ack_awvalid <= 1;
			if (mem_axi_arready && mem_axi_arvalid)
				ack_arvalid <= 1;
			if (mem_axi_wready && mem_axi_wvalid)
				ack_wvalid <= 1;
			if (xfer_done || !mem_cen) begin
				ack_awvalid <= 0;
				ack_arvalid <= 0;
				ack_wvalid <= 0;
			end
		end
	end
endmodule
module sram_axi_adapter (
input        g_clk              ,
input        g_resetn           ,



output        mem_axi_awvalid   ,
input         mem_axi_awready   ,
output [31:0] mem_axi_awaddr    ,
output [ 2:0] mem_axi_awprot    ,

output        mem_axi_wvalid    ,
input         mem_axi_wready    ,
output [31:0] mem_axi_wdata     ,
output [ 3:0] mem_axi_wstrb     ,

input         mem_axi_bvalid    ,
output        mem_axi_bready    ,

output        mem_axi_arvalid   ,
input         mem_axi_arready   ,
output [31:0] mem_axi_araddr    ,
output [ 2:0] mem_axi_arprot    ,

input         mem_axi_rvalid    ,
output        mem_axi_rready    ,
input  [31:0] mem_axi_rdata     ,

input         mem_instr         ,
input         mem_cen           ,
output        mem_stall         ,
output        mem_error         ,
input  [31:0] mem_addr          ,
input  [31:0] mem_wdata         ,
input  [ 3:0] mem_wstrb         ,
output [31:0] mem_rdata
);

	reg ack_awvalid;
	reg ack_arvalid;
	reg ack_wvalid;
	reg xfer_done;

	assign mem_axi_awvalid = mem_cen && |mem_wstrb;
	assign mem_axi_awaddr = mem_addr;
	assign mem_axi_awprot = 0;

	assign mem_axi_arvalid = mem_cen && !mem_wstrb;
	assign mem_axi_araddr = mem_addr;
	assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;

	assign mem_axi_wvalid = mem_cen && |mem_wstrb && !ack_wvalid;
	assign mem_axi_wdata = mem_wdata;
	assign mem_axi_wstrb = mem_wstrb;

	wire   mem_ready = mem_axi_bvalid || mem_axi_rvalid;
    assign mem_stall = !mem_ready;
	assign mem_axi_bready = mem_cen && |mem_wstrb;

	assign mem_axi_rready = 1'b1;
	assign mem_rdata = mem_axi_rdata;
    

    assign mem_error = 1'b0;

	always @(posedge g_clk) begin
		if (!g_resetn) begin
			ack_awvalid <= 0;
		end else begin
			xfer_done <= mem_cen && mem_ready;
			if (mem_axi_awready && mem_axi_awvalid)
				ack_awvalid <= 1;
			if (mem_axi_arready && mem_axi_arvalid)
				ack_arvalid <= 1;
			if (mem_axi_wready && mem_axi_wvalid)
				ack_wvalid <= 1;
			if (xfer_done || !mem_cen) begin
				ack_awvalid <= 0;
				ack_arvalid <= 0;
				ack_wvalid <= 0;
			end
		end
	end
endmodule