data/full_repos/permissive/133161058/cla/hdl/cla.v
 line:57: before: ":"
1: b"%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:57: Define or directive not defined: '`REG_SIZE'\ninput [`REG_SIZE:0] a, b;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:57: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\ninput [`REG_SIZE:0] a, b;\n                ^\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:58: Define or directive not defined: '`REG_SIZE'\noutput [`REG_SIZE:0] s;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:58: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\noutput [`REG_SIZE:0] s;\n                 ^\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:61: Define or directive not defined: '`REG_SIZE'\nreg [`REG_SIZE:0] carrychain;\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:61: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\nreg [`REG_SIZE:0] carrychain;\n              ^\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:64: Define or directive not defined: '`REG_SIZE'\nwire [`REG_SIZE:0] p = a ^ b;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:64: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\nwire [`REG_SIZE:0] p = a ^ b;\n               ^\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:65: Define or directive not defined: '`REG_SIZE'\nwire [`REG_SIZE:0] g = a & b;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:65: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\nwire [`REG_SIZE:0] g = a & b;\n               ^\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:66: Define or directive not defined: '`REG_SIZE'\nwire [`REG_SIZE+1:0] shiftedcarry = {carrychain, ci};\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:67: Define or directive not defined: '`REG_SIZE'\nwire [`REG_SIZE:0] s = p ^ shiftedcarry[`REG_SIZE:0];\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:67: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\nwire [`REG_SIZE:0] s = p ^ shiftedcarry[`REG_SIZE:0];\n               ^\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:67: Define or directive not defined: '`REG_SIZE'\nwire [`REG_SIZE:0] s = p ^ shiftedcarry[`REG_SIZE:0];\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:68: Define or directive not defined: '`REG_SIZE'\nwire co = shiftedcarry[`REG_SIZE+1];\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:73: Define or directive not defined: '`REG_SIZE'\n        for ( i = 1; i <= `REG_SIZE; i = i + 1)\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:73: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n        for ( i = 1; i <= `REG_SIZE; i = i + 1)\n                                   ^\n%Error: data/full_repos/permissive/133161058/cla/hdl/cla.v:73: syntax error, unexpected ')', expecting ';'\n        for ( i = 1; i <= `REG_SIZE; i = i + 1)\n                                              ^\n%Error: Exiting due to 18 error(s)\n"
module CLA ( s, co, a, b, ci );

input ci;
input [`REG_SIZE:0] a, b;
output [`REG_SIZE:0] s;
output co;

reg [`REG_SIZE:0] carrychain;
integer i;

wire [`REG_SIZE:0] p = a ^ b;
wire [`REG_SIZE:0] g = a & b;
wire [`REG_SIZE+1:0] shiftedcarry = {carrychain, ci};
wire [`REG_SIZE:0] s = p ^ shiftedcarry[`REG_SIZE:0];
wire co = shiftedcarry[`REG_SIZE+1];

always @ (a or b or ci or g or p)
begin
        carrychain[0] = g[0] | (p[0] & ci);
        for ( i = 1; i <= `REG_SIZE; i = i + 1)
                carrychain[i] = g[i] | (p[i] & carrychain[i-1]);
end

endmodule
module CLA ( s, co, a, b, ci );


input ci;
input [`REG_SIZE:0] a, b;
output [`REG_SIZE:0] s;
output co;

reg [`REG_SIZE:0] carrychain;
integer i;

wire [`REG_SIZE:0] p = a ^ b;
wire [`REG_SIZE:0] g = a & b;
wire [`REG_SIZE+1:0] shiftedcarry = {carrychain, ci};
wire [`REG_SIZE:0] s = p ^ shiftedcarry[`REG_SIZE:0];
wire co = shiftedcarry[`REG_SIZE+1];

always @ (a or b or ci or g or p)
begin
        carrychain[0] = g[0] | (p[0] & ci);
        for ( i = 1; i <= `REG_SIZE; i = i + 1)
                carrychain[i] = g[i] | (p[i] & carrychain[i-1]);
end

endmodule