data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v
'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte
1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n             const_defination.v\n             const_defination.v.v\n             const_defination.v.sv\n             obj_dir/const_defination.v\n             obj_dir/const_defination.v.v\n             obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:25: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] f_pc,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`digitsBus] f_pc,\n                         ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire need_valc,\n    ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[`digitsBus] valPC\n    ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/addPC.v:28: Define or directive not defined: \'`digitsBus\'\n    output reg[`digitsBus] valPC\n               ^~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module addPC(
    input wire[`digitsBus] f_pc,
    input wire need_regids,
    input wire need_valc,
    output reg[`digitsBus] valPC
    );
    
    always@(*)
    begin
        if(need_regids==1&&need_valc==1)
        begin
            valPC=f_pc+10;
        end
        else if(need_valc==1)
        begin
            valPC=f_pc+9;
        end
        else if(need_regids==1)
        begin
            valPC=f_pc+2;
        end
        else
        begin
            valPC=f_pc+1;
        end
    end
    
endmodule
module addPC(
    input wire[`digitsBus] f_pc,
    input wire need_regids,
    input wire need_valc,
    output reg[`digitsBus] valPC
    );

    
    always@(*)
    begin
        if(need_regids==1&&need_valc==1)
        begin
            valPC=f_pc+10;
        end
        else if(need_valc==1)
        begin
            valPC=f_pc+9;
        end
        else if(need_regids==1)
        begin
            valPC=f_pc+2;
        end
        else
        begin
            valPC=f_pc+1;
        end
    end
    
endmodule