data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v
1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:13: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.v\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.sv\n             sm_settings.vh\n             sm_settings.vh.v\n             sm_settings.vh.sv\n             obj_dir/sm_settings.vh\n             obj_dir/sm_settings.vh.v\n             obj_dir/sm_settings.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:54: Define or directive not defined: \'`SM_CONFIG_ROM_SIZE\'\n    sm_rom #(`SM_CONFIG_ROM_SIZE) reset_rom(imAddr, imData);\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:100: Define or directive not defined: \'`SM_RAM\'\n    `SM_RAM data_ram\n    ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:102: syntax error, unexpected \'(\', expecting IDENTIFIER\n        .clk    ( clk     ),\n        ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:126: Define or directive not defined: \'`SM_CPU\'\n    `SM_CPU sm_cpu\n    ^~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module sm_debouncer
#(
    parameter SIZE = 1
)
(
    input                      clk,
    input      [ SIZE - 1 : 0] d,
    output reg [ SIZE - 1 : 0] q
);
    reg        [ SIZE - 1 : 0] data;

    always @ (posedge clk) begin
        data <= d;
        q    <= data;
    end

endmodule
module sm_debouncer
#(
    parameter SIZE = 1
)
(
    input                      clk,
    input      [ SIZE - 1 : 0] d,
    output reg [ SIZE - 1 : 0] q
);

    reg        [ SIZE - 1 : 0] data;

    always @ (posedge clk) begin
        data <= d;
        q    <= data;
    end

endmodule