data/full_repos/permissive/208636171/fpga/top.v
 line:139 column:17: Illegal character "'"
1: b'%Error: data/full_repos/permissive/208636171/fpga/top.v:39: Cannot find file containing module: \'SB_PLL40_CORE\'\nSB_PLL40_CORE #(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208636171/fpga,data/full_repos/permissive/208636171/SB_PLL40_CORE\n             data/full_repos/permissive/208636171/fpga,data/full_repos/permissive/208636171/SB_PLL40_CORE.v\n             data/full_repos/permissive/208636171/fpga,data/full_repos/permissive/208636171/SB_PLL40_CORE.sv\n             SB_PLL40_CORE\n             SB_PLL40_CORE.v\n             SB_PLL40_CORE.sv\n             obj_dir/SB_PLL40_CORE\n             obj_dir/SB_PLL40_CORE.v\n             obj_dir/SB_PLL40_CORE.sv\n%Warning-WIDTH: data/full_repos/permissive/208636171/fpga/top.v:76: Operator ADD expects 6 bits on the RHS, but RHS\'s LOGNOT generates 1 bits.\n                                                                  : ... In instance top\n  always @(posedge clk_48mhz) usb_reset_cnt <= usb_reset_cnt + !usb_resetn;\n                                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/208636171/fpga/top.v:113: Cannot find file containing module: \'usb_uart\'\n  usb_uart uart (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/208636171/fpga/top.v:138: Cannot find file containing module: \'SB_IO\'\n  SB_IO #(\n  ^~~~~\n%Error: data/full_repos/permissive/208636171/fpga/top.v:150: Cannot find file containing module: \'SB_IO\'\n  SB_IO #(\n  ^~~~~\n%Error: data/full_repos/permissive/208636171/fpga/top.v:183: Cannot find file containing module: \'uart_rx\'\nuart_rx  #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) RX0\n^~~~~~~\n%Error: data/full_repos/permissive/208636171/fpga/top.v:194: Cannot find file containing module: \'dmx_rx\'\ndmx_rx DMX_RX\n^~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module top (
        input wire clk,
        input wire rx,
        output wire tx,
        output wire tx_en,
        output wire LED,
        inout  USBP,
        inout  USBN,
        output USBPU,
        output PIN_22
        `ifdef simulation
          ,input clk_48mhz
        `endif
       );





wire clk_48mhz;
`ifndef simulation
SB_PLL40_CORE #(
 .DIVR(4'b0000),
 .DIVF(7'b0101111),
 .DIVQ(3'b100),
 .FILTER_RANGE(3'b001),
 .FEEDBACK_PATH("SIMPLE"),
 .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
 .FDA_FEEDBACK(4'b0000),
 .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
 .FDA_RELATIVE(4'b0000),
 .SHIFTREG_DIV_MODE(2'b00),
 .PLLOUT_SELECT("GENCLK"),
 .ENABLE_ICEGATE(1'b0)
) usb_pll_inst (
 .REFERENCECLK(clk),
 .PLLOUTCORE(clk_48mhz),
 .RESETB(1'b1),
 .BYPASS(1'b0)
);
`endif


  wire [7:0] usb_uart_di;
  reg [7:0] r_usb_uart_di;
  wire [7:0] usb_uart_do;
  wire usb_uart_re, usb_uart_we;
  wire usb_uart_wait;
  wire usb_uart_ready;
  reg blink_counter = 1'b1;
  reg r_LED;
  reg r_UsbUartWe2 = 1'b0;


  reg [5:0] usb_reset_cnt = 0;
  wire usb_resetn = &usb_reset_cnt;
  reg state = 0;

  always @(posedge clk_48mhz) usb_reset_cnt <= usb_reset_cnt + !usb_resetn;

parameter s_IDLE = 2'b00;
parameter s_HIGHNIBBLE = 2'b01;
parameter s_PREPLOWNIBBLE = 2'b10;
parameter s_LOWNIBBLE = 2'b11;

reg r_OutputState = 0;

  always @(posedge clk_48mhz)
  begin


    if(breakdet && state==0)
    begin
      blink_counter <= blink_counter + 1;
      r_LED <= blink_counter;
    end
    else
    begin
      if(!breakdet) state <= 0;
    end
  end



    wire usb_p_tx;
    wire usb_n_tx;
    wire usb_p_rx;
    wire usb_n_rx;
    wire usb_tx_en;
    wire usb_p_in;
    wire usb_n_in;

assign usb_uart_di = r_usb_uart_di;

`ifndef simulation
  usb_uart uart (
    .clk_48mhz  (clk_48mhz),
    .resetn     (usb_resetn),

    .usb_p_tx(usb_p_tx),
    .usb_n_tx(usb_n_tx),
    .usb_p_rx(usb_p_rx),
    .usb_n_rx(usb_n_rx),
    .usb_tx_en(usb_tx_en),

    .uart_we  (usb_uart_we),
    .uart_re  (usb_uart_re),
    .uart_di  (usb_uart_di),
    .uart_do  (usb_uart_do),
    .uart_wait(usb_uart_wait),
    .uart_ready(usb_uart_ready)
  );


  assign USBPU = 1'b1;
  assign LED = usb_uart_ready;

  assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_in;
  assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_in;

  SB_IO #(
    .PIN_TYPE(6'b 1010_01),
    .PULLUP(1'b 0)
  )
  iobuf_usbp
  (
    .PACKAGE_PIN(USBP),
    .OUTPUT_ENABLE(usb_tx_en),
    .D_OUT_0(usb_p_tx),
    .D_IN_0(usb_p_in)
  );

  SB_IO #(
    .PIN_TYPE(6'b 1010_01),
    .PULLUP(1'b 0)
  )
  iobuf_usbn
  (
    .PACKAGE_PIN(USBN),
    .OUTPUT_ENABLE(usb_tx_en),
    .D_OUT_0(usb_n_tx),
    .D_IN_0(usb_n_in)
  );
`endif

assign tx = 1'b0;
assign tx_en = 1'b0;


assign USBPU = 0;


wire rcv;



reg enabl = 1;


wire breakdet;

parameter c_CLKS_PER_BIT = 64;


wire [7:0] r_DMX_rx;
uart_rx  #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) RX0
      (
       .i_Clock(clk),
       .i_Rx_Serial(rx),
       .o_Rx_DV(rcv),
       .o_Rx_Byte(r_DMX_rx),
       .o_Rx_Break(breakdet)
      );



dmx_rx DMX_RX
(
  .i_Clock(clk_48mhz),
  .i_Rx_DataReady(rcv),
  .i_RxData(r_DMX_rx),
  .i_RxBreak(breakdet),
  .i_usbReady(~usb_uart_ready),
  .o_dataReady(usb_uart_we),
  .o_data(usb_uart_di)
  );


endmodule
module top (
        input wire clk,
        input wire rx,
        output wire tx,
        output wire tx_en,
        output wire LED,
        inout  USBP,
        inout  USBN,
        output USBPU,
        output PIN_22
        `ifdef simulation
          ,input clk_48mhz
        `endif
       );






wire clk_48mhz;
`ifndef simulation
SB_PLL40_CORE #(
 .DIVR(4'b0000),
 .DIVF(7'b0101111),
 .DIVQ(3'b100),
 .FILTER_RANGE(3'b001),
 .FEEDBACK_PATH("SIMPLE"),
 .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
 .FDA_FEEDBACK(4'b0000),
 .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
 .FDA_RELATIVE(4'b0000),
 .SHIFTREG_DIV_MODE(2'b00),
 .PLLOUT_SELECT("GENCLK"),
 .ENABLE_ICEGATE(1'b0)
) usb_pll_inst (
 .REFERENCECLK(clk),
 .PLLOUTCORE(clk_48mhz),
 .RESETB(1'b1),
 .BYPASS(1'b0)
);
`endif


  wire [7:0] usb_uart_di;
  reg [7:0] r_usb_uart_di;
  wire [7:0] usb_uart_do;
  wire usb_uart_re, usb_uart_we;
  wire usb_uart_wait;
  wire usb_uart_ready;
  reg blink_counter = 1'b1;
  reg r_LED;
  reg r_UsbUartWe2 = 1'b0;


  reg [5:0] usb_reset_cnt = 0;
  wire usb_resetn = &usb_reset_cnt;
  reg state = 0;

  always @(posedge clk_48mhz) usb_reset_cnt <= usb_reset_cnt + !usb_resetn;

parameter s_IDLE = 2'b00;
parameter s_HIGHNIBBLE = 2'b01;
parameter s_PREPLOWNIBBLE = 2'b10;
parameter s_LOWNIBBLE = 2'b11;

reg r_OutputState = 0;

  always @(posedge clk_48mhz)
  begin


    if(breakdet && state==0)
    begin
      blink_counter <= blink_counter + 1;
      r_LED <= blink_counter;
    end
    else
    begin
      if(!breakdet) state <= 0;
    end
  end



    wire usb_p_tx;
    wire usb_n_tx;
    wire usb_p_rx;
    wire usb_n_rx;
    wire usb_tx_en;
    wire usb_p_in;
    wire usb_n_in;

assign usb_uart_di = r_usb_uart_di;

`ifndef simulation
  usb_uart uart (
    .clk_48mhz  (clk_48mhz),
    .resetn     (usb_resetn),

    .usb_p_tx(usb_p_tx),
    .usb_n_tx(usb_n_tx),
    .usb_p_rx(usb_p_rx),
    .usb_n_rx(usb_n_rx),
    .usb_tx_en(usb_tx_en),

    .uart_we  (usb_uart_we),
    .uart_re  (usb_uart_re),
    .uart_di  (usb_uart_di),
    .uart_do  (usb_uart_do),
    .uart_wait(usb_uart_wait),
    .uart_ready(usb_uart_ready)
  );


  assign USBPU = 1'b1;
  assign LED = usb_uart_ready;

  assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_in;
  assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_in;

  SB_IO #(
    .PIN_TYPE(6'b 1010_01),
    .PULLUP(1'b 0)
  )
  iobuf_usbp
  (
    .PACKAGE_PIN(USBP),
    .OUTPUT_ENABLE(usb_tx_en),
    .D_OUT_0(usb_p_tx),
    .D_IN_0(usb_p_in)
  );

  SB_IO #(
    .PIN_TYPE(6'b 1010_01),
    .PULLUP(1'b 0)
  )
  iobuf_usbn
  (
    .PACKAGE_PIN(USBN),
    .OUTPUT_ENABLE(usb_tx_en),
    .D_OUT_0(usb_n_tx),
    .D_IN_0(usb_n_in)
  );
`endif

assign tx = 1'b0;
assign tx_en = 1'b0;


assign USBPU = 0;


wire rcv;



reg enabl = 1;


wire breakdet;

parameter c_CLKS_PER_BIT = 64;


wire [7:0] r_DMX_rx;
uart_rx  #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) RX0
      (
       .i_Clock(clk),
       .i_Rx_Serial(rx),
       .o_Rx_DV(rcv),
       .o_Rx_Byte(r_DMX_rx),
       .o_Rx_Break(breakdet)
      );



dmx_rx DMX_RX
(
  .i_Clock(clk_48mhz),
  .i_Rx_DataReady(rcv),
  .i_RxData(r_DMX_rx),
  .i_RxBreak(breakdet),
  .i_usbReady(~usb_uart_ready),
  .o_dataReady(usb_uart_we),
  .o_data(usb_uart_di)
  );


endmodule