data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src/BranchDecisionMaking.v
'utf-8' codec can't decode byte 0xbc in position 1536: invalid start byte
1: b'%Error: data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src/BranchDecisionMaking.v:12: Cannot find include file: Parameters.v\n`include "Parameters.v"    \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v.v\n             data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src,data/full_repos/permissive/175780824/Parameters.v.sv\n             Parameters.v\n             Parameters.v.v\n             Parameters.v.sv\n             obj_dir/Parameters.v\n             obj_dir/Parameters.v.v\n             obj_dir/Parameters.v.sv\n%Error: Exiting due to 1 error(s)\n'
module BranchDecisionMaking(
    input wire [2:0] BranchTypeE,
    input wire [31:0] Operand1,Operand2,
    output reg BranchE
    );
endmodule
module BranchDecisionMaking(
    input wire [2:0] BranchTypeE,
    input wire [31:0] Operand1,Operand2,
    output reg BranchE
    );

endmodule