data/full_repos/permissive/135622446/trig_board_firmware/LED_4.v
Syntax Error
data/verilator_xmls/89eac616-ab0b-44d7-8e54-714bc61d04cb.xml
module LED_4(
	input nrst,
	input clk,
	inout reg [3:0]led,
	input coax1,
	input coax2,
	output reg coax_out_1
	);
	

	integer counter;
	reg clk2;
	always@(posedge clk) begin
		if(!nrst) begin
			counter <= 0;
			clk2 <= 0;
		end
		else if (counter == 100000000) begin
			counter <= 0;
			clk2 = ~clk2;
		end
		else counter <= counter + 32'd1;
	end
	reg [1:0] ledi;	
	always@(posedge clk2) begin
		case (ledi)
		0:	begin led <= 4'b1110;ledi<=ledi+2'b01; end
		1:	begin led <= 4'b1101;ledi<=ledi+2'b01; end
		2:	begin led <= 4'b1011;ledi<=ledi+2'b01; end
		3:	begin led <= 4'b0111;ledi<=ledi+2'b01; end
		endcase			
	end
	
	


	

	integer state=READY;
	localparam READY=0, FIRING=1, DEAD=2;
	integer firingcounter=0;
	always@(posedge clk) begin		
	case (state)
		READY: begin
			firingcounter<=0;
			coax_out_1 <= 0;
			if (coax1 || coax2) begin
				state = FIRING;
			end
		end
		FIRING: begin
			firingcounter <= firingcounter+1;
			coax_out_1 <= 1;
			if (firingcounter >= 4) begin
				state = DEAD;
			end
		end
		DEAD: begin
			firingcounter <= firingcounter+1;
			coax_out_1 <= 0;
			if (firingcounter >= 24) begin
				state = READY;
			end
		end
	endcase
	end
	
endmodule
module LED_4(
	input nrst,
	input clk,
	inout reg [3:0]led,
	input coax1,
	input coax2,
	output reg coax_out_1
	);

	

	integer counter;
	reg clk2;
	always@(posedge clk) begin
		if(!nrst) begin
			counter <= 0;
			clk2 <= 0;
		end
		else if (counter == 100000000) begin
			counter <= 0;
			clk2 = ~clk2;
		end
		else counter <= counter + 32'd1;
	end
	reg [1:0] ledi;	
	always@(posedge clk2) begin
		case (ledi)
		0:	begin led <= 4'b1110;ledi<=ledi+2'b01; end
		1:	begin led <= 4'b1101;ledi<=ledi+2'b01; end
		2:	begin led <= 4'b1011;ledi<=ledi+2'b01; end
		3:	begin led <= 4'b0111;ledi<=ledi+2'b01; end
		endcase			
	end
	
	


	

	integer state=READY;
	localparam READY=0, FIRING=1, DEAD=2;
	integer firingcounter=0;
	always@(posedge clk) begin		
	case (state)
		READY: begin
			firingcounter<=0;
			coax_out_1 <= 0;
			if (coax1 || coax2) begin
				state = FIRING;
			end
		end
		FIRING: begin
			firingcounter <= firingcounter+1;
			coax_out_1 <= 1;
			if (firingcounter >= 4) begin
				state = DEAD;
			end
		end
		DEAD: begin
			firingcounter <= firingcounter+1;
			coax_out_1 <= 0;
			if (firingcounter >= 24) begin
				state = READY;
			end
		end
	endcase
	end
	
endmodule