data/full_repos/permissive/20688874/viterbi/spdutb.v
1: b'%Error: data/full_repos/permissive/20688874/viterbi/spdutb.v:3: Cannot find include file: spdu.v\n`include "spdu.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/spdu.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/spdu.v.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/spdu.v.sv\n             spdu.v\n             spdu.v.v\n             spdu.v.sv\n             obj_dir/spdu.v\n             obj_dir/spdu.v.v\n             obj_dir/spdu.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:18: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:20: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:22: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:24: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:26: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:28: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:31: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:33: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:36: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:38: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:41: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:43: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:47: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:49: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:52: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:54: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:57: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:59: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:62: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/spdutb.v:64: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Error: data/full_repos/permissive/20688874/viterbi/spdutb.v:70: Unsupported or unknown PLI call: $shm_open\n $shm_open("spdu.shm");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/20688874/viterbi/spdutb.v:71: Unsupported or unknown PLI call: $shm_probe\n $shm_probe("AC"); \n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s), 20 warning(s)\n'
module spdutb;
    reg 	in0, in1, in2, in3, d0, d1, d2, d3;
    reg 	clk, reset;
    wire 	out0, out1, out2, out3;

    spdu spdu1(in0, in1, in2, in3, d0, d1, d2, d3,
    	       out0, out1, out2, out3, clk, reset);

    initial
        begin
            d0=1'b0; d1=1'b1; d2=1'b0; d3=1'b1; 
            in0=1'b0; in1=1'b1; in2=1'b0; in3=1'b1; 
            clk=1'b0; reset=1'b0;
            #10;
            clk=1'b1; reset=1'b0;
	    #10;
            clk=1'b0; reset=1'b1;
	    #10;
            clk=1'b1; reset=1'b1;
	    #10;
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
	    #10;
	    in0=1'b0; in1=1'b0; in2=1'b0; in3=1'b0; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    in0=1'b0; in1=1'b0; in2=1'b0; in3=1'b1; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    in0=1'b0; in1=1'b0; in2=1'b1; in3=1'b0; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
            d0=1'b1; d1=1'b0; d2=1'b1; d3=1'b0; 
	    in0=1'b0; in1=1'b0; in2=1'b0; in3=1'b1; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    in0=1'b0; in1=1'b0; in2=1'b1; in3=1'b0; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    in0=1'b1; in1=1'b0; in2=1'b1; in3=1'b1; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    in0=1'b1; in1=1'b1; in2=1'b0; in3=1'b0; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;


        end
initial
    begin
	$shm_open("spdu.shm");
	$shm_probe("AC");	
    end
endmodule
module spdutb;

    reg 	in0, in1, in2, in3, d0, d1, d2, d3;
    reg 	clk, reset;
    wire 	out0, out1, out2, out3;

    spdu spdu1(in0, in1, in2, in3, d0, d1, d2, d3,
    	       out0, out1, out2, out3, clk, reset);

    initial
        begin
            d0=1'b0; d1=1'b1; d2=1'b0; d3=1'b1; 
            in0=1'b0; in1=1'b1; in2=1'b0; in3=1'b1; 
            clk=1'b0; reset=1'b0;
            #10;
            clk=1'b1; reset=1'b0;
	    #10;
            clk=1'b0; reset=1'b1;
	    #10;
            clk=1'b1; reset=1'b1;
	    #10;
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
	    #10;
	    in0=1'b0; in1=1'b0; in2=1'b0; in3=1'b0; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    in0=1'b0; in1=1'b0; in2=1'b0; in3=1'b1; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    in0=1'b0; in1=1'b0; in2=1'b1; in3=1'b0; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
            d0=1'b1; d1=1'b0; d2=1'b1; d3=1'b0; 
	    in0=1'b0; in1=1'b0; in2=1'b0; in3=1'b1; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    in0=1'b0; in1=1'b0; in2=1'b1; in3=1'b0; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    in0=1'b1; in1=1'b0; in2=1'b1; in3=1'b1; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    in0=1'b1; in1=1'b1; in2=1'b0; in3=1'b0; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;


        end
initial
    begin
	$shm_open("spdu.shm");
	$shm_probe("AC");	
    end
endmodule