data/full_repos/permissive/150214807/lab5.v
 line:79: before: "["
1: b'%Error: data/full_repos/permissive/150214807/lab5.v:100: Unsupported or unknown PLI call: $monitor\n$monitor(,$time,"r1=%b r2=%b reset=%b, w=%b, d=%h, rd1=%h, rd2=%h rw=%b",rr1,rr2,rst,w,wd,rd1,rd2,rw);\n^~~~~~~~\n%Error: data/full_repos/permissive/150214807/lab5.v:100: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n$monitor(,$time,"r1=%b r2=%b reset=%b, w=%b, d=%h, rd1=%h, rd2=%h rw=%b",rr1,rr2,rst,w,wd,rd1,rd2,rw);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:102: Unsupported: Ignoring delay on this delayed statement.\n#30 rst = 1\'b1; wd=32\'hAFAFAFAF; w=2\'b10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:103: Unsupported: Ignoring delay on this delayed statement.\n#10 rw=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:104: Unsupported: Ignoring delay on this delayed statement.\n#15 w=2\'b01;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:105: Unsupported: Ignoring delay on this delayed statement.\n#20 wd=32\'hFAFAFAFA;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:106: Unsupported: Ignoring delay on this delayed statement.\n#10 rst=1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:107: Unsupported: Ignoring delay on this delayed statement.\n#200 $finish;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:111: Unsupported: Ignoring delay on this delayed statement.\n#7 clk = ~clk;\n^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tbm41();
reg clk,rst,rw;
reg [1:0] rr1,rr2,w;
wire [31:0] rd1,rd2;
reg[31:0] wd;
RegFile r1(clk,rst,rr1,rr2,w,wd,rw,rd1,rd2);           
initial
begin 
$monitor(,$time,"r1=%b r2=%b reset=%b, w=%b, d=%h, rd1=%h, rd2=%h rw=%b",rr1,rr2,rst,w,wd,rd1,rd2,rw);
rst = 1'b0; clk=1'b0;rw=1'b0; rr1=2'b01;rr2=2'b10;
#30 rst = 1'b1; wd=32'hAFAFAFAF; w=2'b10;
#10 rw=1'b1; 
#15 w=2'b01;
#20 wd=32'hFAFAFAFA;
#10 rst=1'b0;
#200 $finish;
end
always
begin
#7 clk = ~clk;
end
endmodule
module tbm41();

reg clk,rst,rw;
reg [1:0] rr1,rr2,w;
wire [31:0] rd1,rd2;
reg[31:0] wd;
RegFile r1(clk,rst,rr1,rr2,w,wd,rw,rd1,rd2);           
initial
begin 
$monitor(,$time,"r1=%b r2=%b reset=%b, w=%b, d=%h, rd1=%h, rd2=%h rw=%b",rr1,rr2,rst,w,wd,rd1,rd2,rw);
rst = 1'b0; clk=1'b0;rw=1'b0; rr1=2'b01;rr2=2'b10;
#30 rst = 1'b1; wd=32'hAFAFAFAF; w=2'b10;
#10 rw=1'b1; 
#15 w=2'b01;
#20 wd=32'hFAFAFAFA;
#10 rst=1'b0;
#200 $finish;
end
always
begin
#7 clk = ~clk;
end
endmodule