data/full_repos/permissive/167962127/sine_wave.v
1: b"%Error: data/full_repos/permissive/167962127/sine_wave.v:11: Cannot find file containing module: 'sine_addr'\n  sine_addr SINE_ADDR(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/sine_addr\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/sine_addr.v\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/sine_addr.sv\n             sine_addr\n             sine_addr.v\n             sine_addr.sv\n             obj_dir/sine_addr\n             obj_dir/sine_addr.v\n             obj_dir/sine_addr.sv\n%Error: data/full_repos/permissive/167962127/sine_wave.v:18: Cannot find file containing module: 'quad_sine'\n  quad_sine QUAD_SINE(\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module sine_wave(
  input i_clk,
  input [15:0] i_addr,
  output reg [15:0] o_data
);

  wire [13:0] w_saddr_to_lut;
  wire w_neg;
  wire [15:0] w_data;

  sine_addr SINE_ADDR(
    .i_clk(i_clk),
    .i_addr(i_addr),
    .o_addr(w_saddr_to_lut),
    .o_neg(w_neg)
  );

  quad_sine QUAD_SINE(
    .i_clk(i_clk),
    .i_addr(w_saddr_to_lut),
    .o_data(w_data)
  );

  always @ (posedge i_clk)
  begin
    case (w_neg)
      0 : o_data <= w_data;
      default : o_data <= -w_data;
    endcase
  end

endmodule
module sine_wave(
  input i_clk,
  input [15:0] i_addr,
  output reg [15:0] o_data
);


  wire [13:0] w_saddr_to_lut;
  wire w_neg;
  wire [15:0] w_data;

  sine_addr SINE_ADDR(
    .i_clk(i_clk),
    .i_addr(i_addr),
    .o_addr(w_saddr_to_lut),
    .o_neg(w_neg)
  );

  quad_sine QUAD_SINE(
    .i_clk(i_clk),
    .i_addr(w_saddr_to_lut),
    .o_data(w_data)
  );

  always @ (posedge i_clk)
  begin
    case (w_neg)
      0 : o_data <= w_data;
      default : o_data <= -w_data;
    endcase
  end

endmodule