data/full_repos/permissive/172054326/rtl/trng_reg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:46: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  ctl_state <= IDLE;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:50: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'RGEN\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n        IDLE : ctl_state  <= (gen)? RGEN : IDLE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:50: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n        IDLE : ctl_state  <= (gen)? RGEN : IDLE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:51: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'PROC\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n        RGEN : ctl_state  <= PROC;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:52: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  PROC : ctl_state  <= (trn_gen_done)? IDLE: PROC;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:52: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'PROC\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  PROC : ctl_state  <= (trn_gen_done)? IDLE: PROC;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:54: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n            ctl_state <= IDLE;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:49: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  case (ctl_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:49: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'RGEN\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  case (ctl_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:49: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROC\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n  case (ctl_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:59: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n     case (ctl_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:59: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'RGEN\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n     case (ctl_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/172054326/rtl/trng_reg.v:59: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'PROC\' generates 2 bits.\n                                                                      : ... In instance trng_reg\n     case (ctl_state)\n     ^~~~\n%Error: data/full_repos/permissive/172054326/rtl/trng_reg.v:87: Cannot find file containing module: \'es_trng\'\n       (* dont_touch = "true" *) es_trng trng_ins(\n                                 ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172054326/rtl,data/full_repos/permissive/172054326/es_trng\n             data/full_repos/permissive/172054326/rtl,data/full_repos/permissive/172054326/es_trng.v\n             data/full_repos/permissive/172054326/rtl,data/full_repos/permissive/172054326/es_trng.sv\n             es_trng\n             es_trng.v\n             es_trng.sv\n             obj_dir/es_trng\n             obj_dir/es_trng.v\n             obj_dir/es_trng.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n'
module parity_filter #(parameter ORD=3)(input rst, input clk, input trn_val, input trn_rnb, output val, output rnb);
localparam CW = $clog2(ORD);

reg [ORD-1:0] trn_bit_reg;
always @(posedge clk) begin
    if		(rst)       trn_bit_reg <= {ORD{1'b0}};    
    else if (trn_val)   trn_bit_reg <= {trn_bit_reg[ORD-2:0], trn_rnb};    
end

reg [CW-1:0] trn_bit_cnt;
always @(posedge clk) begin
    if		(rst)       trn_bit_cnt <= {CW{1'b0}};    
    else if (trn_val)   trn_bit_cnt <= (trn_bit_cnt==(ORD-1))?{CW{1'b0}}:trn_bit_cnt+1'd1;    
end

reg  trn_bit_reg_full;
always @(posedge clk) begin
    if		(rst)	      							trn_bit_reg_full <= 1'b0;    
    else if ((trn_val & (trn_bit_cnt==(ORD-1))))	trn_bit_reg_full <= 1'b1;
	else     										trn_bit_reg_full <= 1'b0;
end

assign val = trn_bit_reg_full;
assign rnb = ^trn_bit_reg[ORD-1:0];

endmodule
module parity_filter #(parameter ORD=3)(input rst, input clk, input trn_val, input trn_rnb, output val, output rnb);

localparam CW = $clog2(ORD);

reg [ORD-1:0] trn_bit_reg;
always @(posedge clk) begin
    if		(rst)       trn_bit_reg <= {ORD{1'b0}};    
    else if (trn_val)   trn_bit_reg <= {trn_bit_reg[ORD-2:0], trn_rnb};    
end

reg [CW-1:0] trn_bit_cnt;
always @(posedge clk) begin
    if		(rst)       trn_bit_cnt <= {CW{1'b0}};    
    else if (trn_val)   trn_bit_cnt <= (trn_bit_cnt==(ORD-1))?{CW{1'b0}}:trn_bit_cnt+1'd1;    
end

reg  trn_bit_reg_full;
always @(posedge clk) begin
    if		(rst)	      							trn_bit_reg_full <= 1'b0;    
    else if ((trn_val & (trn_bit_cnt==(ORD-1))))	trn_bit_reg_full <= 1'b1;
	else     										trn_bit_reg_full <= 1'b0;
end

assign val = trn_bit_reg_full;
assign rnb = ^trn_bit_reg[ORD-1:0];

endmodule