data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'block_ram_sp\'\nmodule  block_ram_sp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'block_ram_dp\'\nmodule  block_ram_dp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'dist_ram_dp\'\nmodule  dist_ram_dp(\n        ^~~~~~~~~~~\n                                                                                             : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n                                                                                           : ... In instance per_dp4_0_r\n  counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n                                            ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module  dist_ram_dp(
wen,                              
clk,                             
addr_r,                            
addr_w,                            
din,                            
dout                             
);                               
  parameter DATA_WIDTH = 8;                                
  parameter ADDR_WIDTH = 2;                                
  parameter RAM_SIZE = 1 << ADDR_WIDTH;                                
  input wen, clk;                   
  input [ADDR_WIDTH-1:0] addr_r;                        
  input [ADDR_WIDTH-1:0] addr_w;                        
  input [DATA_WIDTH-1:0] din;                        
  output [DATA_WIDTH-1:0] dout;        
  
  reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];        
  
  always@(posedge clk)             
  begin                            

  if(wen)                         
      ram[addr_w] <= din ;              
  end                             
 
  assign dout = ram[addr_r];         
  
endmodule
module  dist_ram_dp(
wen,                              
clk,                             
addr_r,                            
addr_w,                            
din,                            
dout                             
);
                               
  parameter DATA_WIDTH = 8;                                
  parameter ADDR_WIDTH = 2;                                
  parameter RAM_SIZE = 1 << ADDR_WIDTH;                                
  input wen, clk;                   
  input [ADDR_WIDTH-1:0] addr_r;                        
  input [ADDR_WIDTH-1:0] addr_w;                        
  input [DATA_WIDTH-1:0] din;                        
  output [DATA_WIDTH-1:0] dout;        
  
  reg [DATA_WIDTH-1:0] ram[RAM_SIZE-1:0];        
  
  always@(posedge clk)             
  begin                            

  if(wen)                         
      ram[addr_w] <= din ;              
  end                             
 
  assign dout = ram[addr_r];         
  
endmodule