data/full_repos/permissive/200104480/Processor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:440: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'singleBit\' generates 1 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.A.ze\n assign dataOut = 32\'b0 + singleBit;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:361: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'dataIn\' generates 16 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.ZE\n assign dataOut = 32\'b0 + dataIn;\n                        ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Processor(input CLK);
	wire [31:0] pcPrime;
	wire [31:0] pc;
	wire [31:0] Instr;
	wire [31:0] RD1;
	wire [31:0] RD2;
	wire [31:0] SignImm;
	wire [31:0] ZeroImm;
	wire [4:0] WriteReg;
	wire [31:0] Result;
	wire [31:0] SrcB;
	wire [31:0] ALUResult;
	wire [31:0] ReadData;
	wire [31:0] pcp4;
	wire [31:0] pcb;
	wire [31:0] shiftOut;
	wire cout;
	wire [1:0] PCSrc;
	wire zero;
	wire [31:0] mx2mx;
	wire [31:0] JLine;
	
	wire MemtoReg;
	wire MemWrite;
	wire BranchEQ;
	wire BranchNE;
	wire [2:0] ALUControl;
	wire [1:0] ALUSrc;
	wire RegDst;
	wire RegWrite;
	wire Jump;	
	
	
	PC PC1(CLK, pcPrime, pc);
	InstructionMemory IM(pc, Instr);
	RegFile RF(CLK, RegWrite, Instr[25:21], Instr[20:16], WriteReg, Result, RD1, RD2);
	ControlUnit CU(Instr[31:26], Instr[5:0], MemtoReg, MemWrite, BranchEQ, BranchNE, ALUSrc, RegDst, RegWrite, Jump, ALUControl);
	ALU A(RD1, SrcB, ALUControl, ALUResult);
	DataMem DM(CLK, MemWrite, ALUResult, RD2, ReadData);
	SignExtend SE(Instr[15:0], SignImm);
	ZeroExtend16to32 ZE(Instr[15:0], ZeroImm);
	PCPlus4 pc4(pc, pcp4);
	Shifter SH(SignImm, shiftOut);
	adder32 pcBranch(shiftOut, pcp4, 1'b0, pcb, cout);
	
	assign zero = (ALUResult==0);
	assign PCSrc[1] = BranchEQ & zero;
	assign PCSrc[0] = BranchNE & (!zero);
	assign JLine[31:26] = pcp4[31:26];
	assign JLine[25:0] = Instr[25:0];

	mux4to1 mx0(PCSrc, pcp4, pcb, pcb, 32'bx, mx2mx);
	mux2to1_5 mx1(RegDst, Instr[20:16], Instr[15:11], WriteReg);
	mux4to1 mx2(ALUSrc, RD2, SignImm, ZeroImm, 32'bx, SrcB);
	mux2to1 mx3(MemtoReg, ALUResult, ReadData, Result);
	mux2to1 mxJ(Jump, mx2mx, JLine, pcPrime);

	
endmodule
module Processor(input CLK);

	wire [31:0] pcPrime;
	wire [31:0] pc;
	wire [31:0] Instr;
	wire [31:0] RD1;
	wire [31:0] RD2;
	wire [31:0] SignImm;
	wire [31:0] ZeroImm;
	wire [4:0] WriteReg;
	wire [31:0] Result;
	wire [31:0] SrcB;
	wire [31:0] ALUResult;
	wire [31:0] ReadData;
	wire [31:0] pcp4;
	wire [31:0] pcb;
	wire [31:0] shiftOut;
	wire cout;
	wire [1:0] PCSrc;
	wire zero;
	wire [31:0] mx2mx;
	wire [31:0] JLine;
	
	wire MemtoReg;
	wire MemWrite;
	wire BranchEQ;
	wire BranchNE;
	wire [2:0] ALUControl;
	wire [1:0] ALUSrc;
	wire RegDst;
	wire RegWrite;
	wire Jump;	
	
	
	PC PC1(CLK, pcPrime, pc);
	InstructionMemory IM(pc, Instr);
	RegFile RF(CLK, RegWrite, Instr[25:21], Instr[20:16], WriteReg, Result, RD1, RD2);
	ControlUnit CU(Instr[31:26], Instr[5:0], MemtoReg, MemWrite, BranchEQ, BranchNE, ALUSrc, RegDst, RegWrite, Jump, ALUControl);
	ALU A(RD1, SrcB, ALUControl, ALUResult);
	DataMem DM(CLK, MemWrite, ALUResult, RD2, ReadData);
	SignExtend SE(Instr[15:0], SignImm);
	ZeroExtend16to32 ZE(Instr[15:0], ZeroImm);
	PCPlus4 pc4(pc, pcp4);
	Shifter SH(SignImm, shiftOut);
	adder32 pcBranch(shiftOut, pcp4, 1'b0, pcb, cout);
	
	assign zero = (ALUResult==0);
	assign PCSrc[1] = BranchEQ & zero;
	assign PCSrc[0] = BranchNE & (!zero);
	assign JLine[31:26] = pcp4[31:26];
	assign JLine[25:0] = Instr[25:0];

	mux4to1 mx0(PCSrc, pcp4, pcb, pcb, 32'bx, mx2mx);
	mux2to1_5 mx1(RegDst, Instr[20:16], Instr[15:11], WriteReg);
	mux4to1 mx2(ALUSrc, RD2, SignImm, ZeroImm, 32'bx, SrcB);
	mux2to1 mx3(MemtoReg, ALUResult, ReadData, Result);
	mux2to1 mxJ(Jump, mx2mx, JLine, pcPrime);

	
endmodule