data/full_repos/permissive/10379745/hard/muldiv.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/10379745/hard/muldiv.sv:70: Cannot find include file: hard/log2.inc\n`include "hard/log2.inc" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc\n             data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc.v\n             data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc.sv\n             hard/log2.inc\n             hard/log2.inc.v\n             hard/log2.inc.sv\n             obj_dir/hard/log2.inc\n             obj_dir/hard/log2.inc.v\n             obj_dir/hard/log2.inc.sv\n%Error: Exiting due to 1 error(s)\n'
module mc_div #( parameter W = 4 ) 
               ( input          CLK,
                 input          RESET,

                 input          GO,
                 output         BUSY,
                 output         W_RESULT,

                 input  [W-1:0] A,
                 input  [W-1:0] B,

                 output [W-1:0] QUOT,
                 output [W-1:0] REM );

`include "hard/log2.inc"

localparam C = log2(W); 

logic    [2*W-1:0] nextval, Q;
logic      [W-1:0] dvsr, hiword;
logic signed [W:0] diff;
logic      [C-1:0] cnt;
logic              busy;

assign hiword = Q[2*W-2:W-1];

assign diff = hiword - dvsr;

assign nextval =         GO ? { {W{1'b0}}, A}               :
                    diff[W] ? Q << 1                        : 
                              {diff[W-1:0], Q[W-2:0], 1'b1} ;

ffd   #(W) dvsr_reg(CLK, RESET, GO, B, dvsr);

ffd #(2*W) result_reg(CLK, RESET, GO | busy, nextval, Q);

rsd  busy_reg(CLK, RESET | W_RESULT, GO, busy );

counter #(C) counter( CLK, GO, busy, cnt );

assign BUSY     = busy;
assign W_RESULT = (cnt == W);

assign REM  = Q[2*W-1:W];
assign QUOT = Q[W-1:0];

endmodule
module mc_div #( parameter W = 4 ) 
               ( input          CLK,
                 input          RESET,

                 input          GO,
                 output         BUSY,
                 output         W_RESULT,

                 input  [W-1:0] A,
                 input  [W-1:0] B,

                 output [W-1:0] QUOT,
                 output [W-1:0] REM );


`include "hard/log2.inc"

localparam C = log2(W); 

logic    [2*W-1:0] nextval, Q;
logic      [W-1:0] dvsr, hiword;
logic signed [W:0] diff;
logic      [C-1:0] cnt;
logic              busy;

assign hiword = Q[2*W-2:W-1];

assign diff = hiword - dvsr;

assign nextval =         GO ? { {W{1'b0}}, A}               :
                    diff[W] ? Q << 1                        : 
                              {diff[W-1:0], Q[W-2:0], 1'b1} ;

ffd   #(W) dvsr_reg(CLK, RESET, GO, B, dvsr);

ffd #(2*W) result_reg(CLK, RESET, GO | busy, nextval, Q);

rsd  busy_reg(CLK, RESET | W_RESULT, GO, busy );

counter #(C) counter( CLK, GO, busy, cnt );

assign BUSY     = busy;
assign W_RESULT = (cnt == W);

assign REM  = Q[2*W-1:W];
assign QUOT = Q[W-1:0];

endmodule