data/full_repos/permissive/2084115/testbench/sim/library/tb_fifo_width_convert/tb_fifo_width_convert.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_fifo_width_convert/tb_fifo_width_convert.v:12: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_fifo_width_convert.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_fifo_width_convert/tb_fifo_width_convert.v:13: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_fifo_width_convert);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_fifo_width_convert/tb_fifo_width_convert.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #10000000\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_fifo_width_convert/tb_fifo_width_convert.v:21: Unsupported: Ignoring delay on this delayed statement.\n    always #(S_RATE/2.0)    s_clk = ~s_clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_fifo_width_convert/tb_fifo_width_convert.v:24: Unsupported: Ignoring delay on this delayed statement.\n    always #(S_RATE/2.0)    m_clk = ~m_clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_fifo_width_convert/tb_fifo_width_convert.v:27: Unsupported: Ignoring delay on this delayed statement.\n    initial #(S_RATE*100)   reset <= 1\'b0;\n            ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_fifo_width_convert();
    localparam S_RATE  = 1000.0/100.0;
    localparam M_RATE  = 1000.0/100.0;
    
    
    initial begin
        $dumpfile("tb_fifo_width_convert.vcd");
        $dumpvars(0, tb_fifo_width_convert);
    
    #10000000
        $finish;
    end
    
    
    reg     s_clk = 1'b1;
    always #(S_RATE/2.0)    s_clk = ~s_clk;
    
    reg     m_clk = 1'b1;
    always #(S_RATE/2.0)    m_clk = ~m_clk;
    
    reg     reset = 1'b1;
    initial #(S_RATE*100)   reset <= 1'b0;
    
    
    parameter ASYNC            = 1;
    parameter UNIT_WIDTH       = 8;
    parameter S_NUM            = 4;
    parameter M_NUM            = 8;
    parameter S_DATA_WIDTH     = (UNIT_WIDTH * S_NUM);
    parameter M_DATA_WIDTH     = (UNIT_WIDTH * M_NUM);
    
    parameter FIFO_PTR_WIDTH   = 8;
    parameter FIFO_RAM_TYPE    = "block";
    parameter FIFO_LOW_DEALY   = 0;
    parameter FIFO_DOUT_REGS   = 1;
    parameter FIFO_S_REGS      = 1;
    parameter FIFO_M_REGS      = 1;
    
    
    
    genvar                          i;
    
    reg     [S_DATA_WIDTH-1:0]      src_data;
    reg                             src_valid;
    wire                            src_ready;
    
    wire    [M_DATA_WIDTH-1:0]      dst_data;
    wire                            dst_valid;
    reg                             dst_ready;
    
    always @(posedge s_clk) begin
        if ( reset ) begin
            src_data  <= 0;
            src_valid <= 0;
        end
        else begin
            if ( src_valid & src_ready ) begin
                src_data <= src_data + 1;
            end
            src_valid <= {$random()};
        end
    end
    
    always @(posedge m_clk) begin
        dst_ready <= {$random()};
    end
    
    
    

    jelly_fifo_width_convert
            #(
                .ASYNC              (ASYNC),
                .UNIT_WIDTH         (UNIT_WIDTH),
                .S_NUM              (S_NUM),
                .M_NUM              (M_NUM),
                .FIFO_PTR_WIDTH     (FIFO_PTR_WIDTH),
                .FIFO_RAM_TYPE      (FIFO_RAM_TYPE),
                .FIFO_LOW_DEALY     (FIFO_LOW_DEALY),
                .FIFO_DOUT_REGS     (FIFO_DOUT_REGS),
                .FIFO_S_REGS        (FIFO_S_REGS),
                .FIFO_M_REGS        (FIFO_M_REGS)
            )
        i_fifo_width_convert
            (
                .endian             (1'b0),
                
                .s_reset            (reset),
                .s_clk              (s_clk),
                .s_data             (src_data),
                .s_valid            (src_valid),
                .s_ready            (src_ready),
                .s_fifo_free_count  (),
                .s_fifo_wr_signal   (),
                
                .m_reset            (reset),
                .m_clk              (m_clk),
                .m_data             (dst_data),
                .m_valid            (dst_valid),
                .m_ready            (dst_ready),
                .m_fifo_data_count  (),
                .m_fifo_rd_signal   ()
            );
    
    
endmodule
module tb_fifo_width_convert();

    localparam S_RATE  = 1000.0/100.0;
    localparam M_RATE  = 1000.0/100.0;
    
    
    initial begin
        $dumpfile("tb_fifo_width_convert.vcd");
        $dumpvars(0, tb_fifo_width_convert);
    
    #10000000
        $finish;
    end
    
    
    reg     s_clk = 1'b1;
    always #(S_RATE/2.0)    s_clk = ~s_clk;
    
    reg     m_clk = 1'b1;
    always #(S_RATE/2.0)    m_clk = ~m_clk;
    
    reg     reset = 1'b1;
    initial #(S_RATE*100)   reset <= 1'b0;
    
    
    parameter ASYNC            = 1;
    parameter UNIT_WIDTH       = 8;
    parameter S_NUM            = 4;
    parameter M_NUM            = 8;
    parameter S_DATA_WIDTH     = (UNIT_WIDTH * S_NUM);
    parameter M_DATA_WIDTH     = (UNIT_WIDTH * M_NUM);
    
    parameter FIFO_PTR_WIDTH   = 8;
    parameter FIFO_RAM_TYPE    = "block";
    parameter FIFO_LOW_DEALY   = 0;
    parameter FIFO_DOUT_REGS   = 1;
    parameter FIFO_S_REGS      = 1;
    parameter FIFO_M_REGS      = 1;
    
    
    
    genvar                          i;
    
    reg     [S_DATA_WIDTH-1:0]      src_data;
    reg                             src_valid;
    wire                            src_ready;
    
    wire    [M_DATA_WIDTH-1:0]      dst_data;
    wire                            dst_valid;
    reg                             dst_ready;
    
    always @(posedge s_clk) begin
        if ( reset ) begin
            src_data  <= 0;
            src_valid <= 0;
        end
        else begin
            if ( src_valid & src_ready ) begin
                src_data <= src_data + 1;
            end
            src_valid <= {$random()};
        end
    end
    
    always @(posedge m_clk) begin
        dst_ready <= {$random()};
    end
    
    
    

    jelly_fifo_width_convert
            #(
                .ASYNC              (ASYNC),
                .UNIT_WIDTH         (UNIT_WIDTH),
                .S_NUM              (S_NUM),
                .M_NUM              (M_NUM),
                .FIFO_PTR_WIDTH     (FIFO_PTR_WIDTH),
                .FIFO_RAM_TYPE      (FIFO_RAM_TYPE),
                .FIFO_LOW_DEALY     (FIFO_LOW_DEALY),
                .FIFO_DOUT_REGS     (FIFO_DOUT_REGS),
                .FIFO_S_REGS        (FIFO_S_REGS),
                .FIFO_M_REGS        (FIFO_M_REGS)
            )
        i_fifo_width_convert
            (
                .endian             (1'b0),
                
                .s_reset            (reset),
                .s_clk              (s_clk),
                .s_data             (src_data),
                .s_valid            (src_valid),
                .s_ready            (src_ready),
                .s_fifo_free_count  (),
                .s_fifo_wr_signal   (),
                
                .m_reset            (reset),
                .m_clk              (m_clk),
                .m_data             (dst_data),
                .m_valid            (dst_valid),
                .m_ready            (dst_ready),
                .m_fifo_data_count  (),
                .m_fifo_rd_signal   ()
            );
    
    
endmodule