data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #PERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test048.simple-counter-again.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #HALF_PERIOD;\n  ^\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb;
	parameter WIDTH = 8;
	parameter HALF_PERIOD = 5;
	parameter PERIOD = 2*HALF_PERIOD;
	reg clk = 0;
	reg pre_rst = 0;
	reg rst = 0;
	reg pre_load = 0;
	reg load = 0;
	wire [WIDTH-1:0] cnt;
	initial begin
		pre_rst <= 0;
		pre_load <= 0;
		#100;
		pre_rst <= 1;
		#PERIOD;
		$display("%02x", cnt);
		#PERIOD;
		$display("%02x", cnt);
		#1000;
		$display("%02x", cnt);
		#PERIOD;
		$display("%02x", cnt);
		pre_load <= 1;
		#PERIOD;
		pre_load <= 0;
		#PERIOD;
		$display("%02x", cnt);
		#PERIOD;
		$display("%02x", cnt);
		#10000;
		$display("%02x", cnt);
		#PERIOD;
		$display("%02x", cnt);
		$finish;
	end
	always begin
		#HALF_PERIOD;
		clk <= ~clk;
	end
	always @(posedge clk) begin
		rst <= pre_rst;
		load <= pre_load;
	end
	counter counter1(.clk(clk), .rst(rst), .load(load), .cnt_out(cnt));
endmodule
module counter_tb;

	parameter WIDTH = 8;
	parameter HALF_PERIOD = 5;
	parameter PERIOD = 2*HALF_PERIOD;
	reg clk = 0;
	reg pre_rst = 0;
	reg rst = 0;
	reg pre_load = 0;
	reg load = 0;
	wire [WIDTH-1:0] cnt;
	initial begin
		pre_rst <= 0;
		pre_load <= 0;
		#100;
		pre_rst <= 1;
		#PERIOD;
		$display("%02x", cnt);
		#PERIOD;
		$display("%02x", cnt);
		#1000;
		$display("%02x", cnt);
		#PERIOD;
		$display("%02x", cnt);
		pre_load <= 1;
		#PERIOD;
		pre_load <= 0;
		#PERIOD;
		$display("%02x", cnt);
		#PERIOD;
		$display("%02x", cnt);
		#10000;
		$display("%02x", cnt);
		#PERIOD;
		$display("%02x", cnt);
		$finish;
	end
	always begin
		#HALF_PERIOD;
		clk <= ~clk;
	end
	always @(posedge clk) begin
		rst <= pre_rst;
		load <= pre_load;
	end
	counter counter1(.clk(clk), .rst(rst), .load(load), .cnt_out(cnt));
endmodule