data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v
1: b'%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:9: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                   : ... In instance bcdto7seg\n          4\'h0: sevenseg <= 8\'b11111100 | dot;\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:10: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'h1: sevenseg <= 8\'b01100000 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:11: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'h2: sevenseg <= 8\'b11011010 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:12: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'h3: sevenseg <= 8\'b11110010 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:13: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'h4: sevenseg <= 8\'b01100110 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:14: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'h5: sevenseg <= 8\'b10110110 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:15: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'h6: sevenseg <= 8\'b00111110 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:16: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'h7: sevenseg <= 8\'b11100000 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:17: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'h8: sevenseg <= 8\'b11111110 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:18: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'h9: sevenseg <= 8\'b11100110 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:19: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'ha: sevenseg <= 8\'b11111010 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:20: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'hb: sevenseg <= 8\'b00111110 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:21: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'hc: sevenseg <= 8\'b00011010 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:22: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'hd: sevenseg <= 8\'b01111010 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:23: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'he: sevenseg <= 8\'b10011010 | dot;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/daughterboard_demo/7segdrv.v:24: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'dot\' generates 1 bits.\n                                                                                    : ... In instance bcdto7seg\n          4\'hf: sevenseg <= 8\'b10001010 | dot;\n                                        ^\n%Error: Exiting due to 16 warning(s)\n'
module bcdto7seg (bcd, sevenseg, dot);
   input [3:0]      bcd;
   input            dot;
   output reg [7:0] sevenseg;

   always @(bcd, dot)
     begin
        case(bcd)
          4'h0: sevenseg <= 8'b11111100 | dot;
          4'h1: sevenseg <= 8'b01100000 | dot;
          4'h2: sevenseg <= 8'b11011010 | dot;
          4'h3: sevenseg <= 8'b11110010 | dot;
          4'h4: sevenseg <= 8'b01100110 | dot;
          4'h5: sevenseg <= 8'b10110110 | dot;
          4'h6: sevenseg <= 8'b00111110 | dot;
          4'h7: sevenseg <= 8'b11100000 | dot;
          4'h8: sevenseg <= 8'b11111110 | dot;
          4'h9: sevenseg <= 8'b11100110 | dot;
          4'ha: sevenseg <= 8'b11111010 | dot;
          4'hb: sevenseg <= 8'b00111110 | dot;
          4'hc: sevenseg <= 8'b00011010 | dot;
          4'hd: sevenseg <= 8'b01111010 | dot;
          4'he: sevenseg <= 8'b10011010 | dot;
          4'hf: sevenseg <= 8'b10001010 | dot;
        endcase
     end
endmodule
module bcdto7seg (bcd, sevenseg, dot);

   input [3:0]      bcd;
   input            dot;
   output reg [7:0] sevenseg;

   always @(bcd, dot)
     begin
        case(bcd)
          4'h0: sevenseg <= 8'b11111100 | dot;
          4'h1: sevenseg <= 8'b01100000 | dot;
          4'h2: sevenseg <= 8'b11011010 | dot;
          4'h3: sevenseg <= 8'b11110010 | dot;
          4'h4: sevenseg <= 8'b01100110 | dot;
          4'h5: sevenseg <= 8'b10110110 | dot;
          4'h6: sevenseg <= 8'b00111110 | dot;
          4'h7: sevenseg <= 8'b11100000 | dot;
          4'h8: sevenseg <= 8'b11111110 | dot;
          4'h9: sevenseg <= 8'b11100110 | dot;
          4'ha: sevenseg <= 8'b11111010 | dot;
          4'hb: sevenseg <= 8'b00111110 | dot;
          4'hc: sevenseg <= 8'b00011010 | dot;
          4'hd: sevenseg <= 8'b01111010 | dot;
          4'he: sevenseg <= 8'b10011010 | dot;
          4'hf: sevenseg <= 8'b10001010 | dot;
        endcase
     end
endmodule