data/full_repos/permissive/121592400/tb_winnerPolicy.v
 line:413: before: "state"
1: b'%Error: data/full_repos/permissive/121592400/tb_winnerPolicy.v:7: Cannot find include file: memory.v\n`include "memory.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/121592400,data/full_repos/permissive/121592400/memory.v\n             data/full_repos/permissive/121592400,data/full_repos/permissive/121592400/memory.v.v\n             data/full_repos/permissive/121592400,data/full_repos/permissive/121592400/memory.v.sv\n             memory.v\n             memory.v.v\n             memory.v.sv\n             obj_dir/memory.v\n             obj_dir/memory.v.v\n             obj_dir/memory.v.sv\n%Error: data/full_repos/permissive/121592400/tb_winnerPolicy.v:8: Cannot find include file: randomGenerator.v\n`include "randomGenerator.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121592400/tb_winnerPolicy.v:9: Cannot find include file: winnerPolicy.v\n`include "winnerPolicy.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121592400/tb_winnerPolicy.v:10: Cannot find include file: rngAddress.v\n`include "rngAddress.v" \n         ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_winnerPolicy.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #5 nrst = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_winnerPolicy.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10 nrst = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_winnerPolicy.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #20 en = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_winnerPolicy.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #20 en = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_winnerPolicy.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #100 start_winnerPolicy = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_winnerPolicy.v:120: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clock = ~clock;\n                ^\n%Error: data/full_repos/permissive/121592400/tb_winnerPolicy.v:124: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_winnerPolicy.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/121592400/tb_winnerPolicy.v:125: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_winnerPolicy);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/121592400/tb_winnerPolicy.v:126: Unsupported: Ignoring delay on this delayed statement.\n        #600\n        ^\n%Error: Exiting due to 6 error(s), 7 warning(s)\n'
module tb_winnerPolicy();
    reg clock, nrst;


    wire wr_en;
    wire [`WORD_WIDTH-1:0] mem_data_in;
    wire [`WORD_WIDTH-1:0] mem_data_out;
    wire [10:0] address;
	mem mem1(clock, address, wr_en, mem_data_in, mem_data_out);


    wire en_rng, done_rng;
	wire [`WORD_WIDTH-1:0] rng_out, rng_out_4bit;
	randomGenerator rng1(clock, nrst, rng_out, rng_out_4bit, en_rng, done_rng);


	wire [`WORD_WIDTH-1:0] rng_address, betterNeighborCount, which;
	wire start_rngAddress, done_rngAddress;
	rngAddress rad1(clock, nrst, start_rngAddress, betterNeighborCount, which, rng_address, done_rngAddress);


	reg en, start_winnerPolicy;
	reg [`WORD_WIDTH-1:0] mybest, besthop, bestvalue, bestneighborID, MY_NODE_ID, epsilon, epsilon_step;
	wire [`WORD_WIDTH-1:0] nexthop;
	wire done_winnerPolicy;
	winnerPolicy wp1(clock, nrst, en, start_winnerPolicy, mybest, besthop, bestvalue, bestneighborID, MY_NODE_ID,
						address, mem_data_out, wr_en, mem_data_in, epsilon_step, nexthop, done_winnerPolicy, en_rng, rng_out, rng_out_4bit, 
						rng_address, start_rngAddress, done_rngAddress, betterNeighborCount, which
	);


    initial begin
        nrst = 1;
        #5 nrst = 0;
        #10 nrst = 1;
        #20 en = 1;
        #20 en = 0;
    end

    reg [3:0] state;

	initial begin

        epsilon = 7;
        epsilon_step = 1;
        mybest = 1;
        besthop = 50;
        bestneighborID = 4;   
        MY_NODE_ID = 5;
        bestvalue = 8;
        state = 1;
		#100 start_winnerPolicy = 1;


	end


    initial begin
        clock = 0;
        forever #10 clock = ~clock;
    end

    initial begin
        $dumpfile("tb_winnerPolicy.vcd");
        $dumpvars(0, tb_winnerPolicy);
        #600
        $finish; 
    end
endmodule
module tb_winnerPolicy();

    reg clock, nrst;


    wire wr_en;
    wire [`WORD_WIDTH-1:0] mem_data_in;
    wire [`WORD_WIDTH-1:0] mem_data_out;
    wire [10:0] address;
	mem mem1(clock, address, wr_en, mem_data_in, mem_data_out);


    wire en_rng, done_rng;
	wire [`WORD_WIDTH-1:0] rng_out, rng_out_4bit;
	randomGenerator rng1(clock, nrst, rng_out, rng_out_4bit, en_rng, done_rng);


	wire [`WORD_WIDTH-1:0] rng_address, betterNeighborCount, which;
	wire start_rngAddress, done_rngAddress;
	rngAddress rad1(clock, nrst, start_rngAddress, betterNeighborCount, which, rng_address, done_rngAddress);


	reg en, start_winnerPolicy;
	reg [`WORD_WIDTH-1:0] mybest, besthop, bestvalue, bestneighborID, MY_NODE_ID, epsilon, epsilon_step;
	wire [`WORD_WIDTH-1:0] nexthop;
	wire done_winnerPolicy;
	winnerPolicy wp1(clock, nrst, en, start_winnerPolicy, mybest, besthop, bestvalue, bestneighborID, MY_NODE_ID,
						address, mem_data_out, wr_en, mem_data_in, epsilon_step, nexthop, done_winnerPolicy, en_rng, rng_out, rng_out_4bit, 
						rng_address, start_rngAddress, done_rngAddress, betterNeighborCount, which
	);


    initial begin
        nrst = 1;
        #5 nrst = 0;
        #10 nrst = 1;
        #20 en = 1;
        #20 en = 0;
    end

    reg [3:0] state;

	initial begin

        epsilon = 7;
        epsilon_step = 1;
        mybest = 1;
        besthop = 50;
        bestneighborID = 4;   
        MY_NODE_ID = 5;
        bestvalue = 8;
        state = 1;
		#100 start_winnerPolicy = 1;


	end


    initial begin
        clock = 0;
        forever #10 clock = ~clock;
    end

    initial begin
        $dumpfile("tb_winnerPolicy.vcd");
        $dumpvars(0, tb_winnerPolicy);
        #600
        $finish; 
    end
endmodule