data/full_repos/permissive/162571337/multiplers/16x16_unsigned/pareto_pwr_mre/mul16u_3BB.v
data/verilator_xmls/6b84273c-96e7-478c-8897-11d87f4ff1a6.xml
module PDKGENHAX1( input A, input B, output YS, output YC );
    assign YS = A ^ B;
    assign YC = A & B;
endmodule
module PDKGENHAX1( input A, input B, output YS, output YC );

    assign YS = A ^ B;
    assign YC = A & B;
endmodule