data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_pci_decoder.v
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_pci_decoder.v:59: Cannot find include file: pci_constants.v\n`include "pci_constants.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v.sv\n             pci_constants.v\n             pci_constants.v.v\n             pci_constants.v.sv\n             obj_dir/pci_constants.v\n             obj_dir/pci_constants.v.v\n             obj_dir/pci_constants.v.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_pci_decoder.v:62: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module pci_pci_decoder (hit, addr_out, 
					addr_in, bc_in,
					base_addr, mask_addr, tran_addr, at_en, 
					mem_io_space, mem_en, io_en) ;



parameter		decode_len     = 12 ;









output	hit ;

output	[31:0]	addr_out ;

input	[31:0]	addr_in ;
input	[3:0]	bc_in ;


input	[31:(32-decode_len)]	base_addr ;
input	[31:(32-decode_len)]	mask_addr ;
input	[31:(32-decode_len)]	tran_addr ;


input	at_en ;


input	mem_io_space ;
input	mem_en ;
input	io_en ;




wire	img_en ;


wire	[31:(32-decode_len)]	addr_in_compare ;

wire	[31:(32-decode_len)]	base_addr_compare ;



assign	addr_in_compare = (addr_in[31:(32-decode_len)] & mask_addr) ;

assign	base_addr_compare = (base_addr & mask_addr) ;

assign	img_en = mask_addr[31] ;

wire	addr_hit = (addr_in_compare == base_addr_compare) ;

wire	space_hit = (!mem_io_space && mem_en && img_en) || (mem_io_space && io_en && img_en) ;

reg		bc_hit ;
always@(bc_in or mem_io_space)
begin
	case ( {bc_in[3:1], mem_io_space} )
	4'b001_1,
	4'b011_0,
	4'b110_0,
	4'b111_0:
		bc_hit <= 1'b1 ;
	default:
		bc_hit <= 1'b0 ;
	endcase
end

wire	bc_forbid = bc_in[3] && bc_in[2] && !bc_in[1] && bc_in[0] ;


assign	hit = (addr_hit && space_hit && bc_hit && !bc_forbid) ;



`ifdef ADDR_TRAN_IMPL


    wire	[31:(32-decode_len)] addr_in_combine ;

    reg		[31:(32-decode_len)] tran_addr_combine ;

    assign addr_in_combine = (addr_in[31:(32-decode_len)] & ~mask_addr) ;
    always@(at_en or tran_addr or mask_addr or addr_in)
	begin
	    if (at_en)
			begin
				tran_addr_combine <= (tran_addr & mask_addr) ;
    		end
    	else
			begin
				tran_addr_combine <= (addr_in[31:(32-decode_len)] & mask_addr) ;
			end
	end

    assign addr_out[31:(32-decode_len)] = (addr_in_combine | tran_addr_combine) ;
    assign addr_out[(31-decode_len):0] = addr_in [(31-decode_len):0] ;
`else
    assign addr_out = addr_in ;
`endif

endmodule
module pci_pci_decoder (hit, addr_out, 
					addr_in, bc_in,
					base_addr, mask_addr, tran_addr, at_en, 
					mem_io_space, mem_en, io_en) ;




parameter		decode_len     = 12 ;









output	hit ;

output	[31:0]	addr_out ;

input	[31:0]	addr_in ;
input	[3:0]	bc_in ;


input	[31:(32-decode_len)]	base_addr ;
input	[31:(32-decode_len)]	mask_addr ;
input	[31:(32-decode_len)]	tran_addr ;


input	at_en ;


input	mem_io_space ;
input	mem_en ;
input	io_en ;




wire	img_en ;


wire	[31:(32-decode_len)]	addr_in_compare ;

wire	[31:(32-decode_len)]	base_addr_compare ;



assign	addr_in_compare = (addr_in[31:(32-decode_len)] & mask_addr) ;

assign	base_addr_compare = (base_addr & mask_addr) ;

assign	img_en = mask_addr[31] ;

wire	addr_hit = (addr_in_compare == base_addr_compare) ;

wire	space_hit = (!mem_io_space && mem_en && img_en) || (mem_io_space && io_en && img_en) ;

reg		bc_hit ;
always@(bc_in or mem_io_space)
begin
	case ( {bc_in[3:1], mem_io_space} )
	4'b001_1,
	4'b011_0,
	4'b110_0,
	4'b111_0:
		bc_hit <= 1'b1 ;
	default:
		bc_hit <= 1'b0 ;
	endcase
end

wire	bc_forbid = bc_in[3] && bc_in[2] && !bc_in[1] && bc_in[0] ;


assign	hit = (addr_hit && space_hit && bc_hit && !bc_forbid) ;



`ifdef ADDR_TRAN_IMPL


    wire	[31:(32-decode_len)] addr_in_combine ;

    reg		[31:(32-decode_len)] tran_addr_combine ;

    assign addr_in_combine = (addr_in[31:(32-decode_len)] & ~mask_addr) ;
    always@(at_en or tran_addr or mask_addr or addr_in)
	begin
	    if (at_en)
			begin
				tran_addr_combine <= (tran_addr & mask_addr) ;
    		end
    	else
			begin
				tran_addr_combine <= (addr_in[31:(32-decode_len)] & mask_addr) ;
			end
	end

    assign addr_out[31:(32-decode_len)] = (addr_in_combine | tran_addr_combine) ;
    assign addr_out[(31-decode_len):0] = addr_in [(31-decode_len):0] ;
`else
    assign addr_out = addr_in ;
`endif

endmodule