data/full_repos/permissive/116563702/generate_hardware/genrate_parameter_NinputAnd.v
data/verilator_xmls/671f9012-e136-46b4-8486-84a8c9d9ce00.xml
module andN #(parameter N=8)
	     (input [N-1:0] a,
	      output y);

   wire [N-1:1]      x;

   genvar 	     i;

   generate
      for (i=1; i<N; i=i+1)
	begin:ForLoop
	   if (i==1)
	     assign x[1] = a[0] & a[1];
	   else
	     assign x[i] = x[i-1] & a[i];
	end
      endgenerate

   assign y = x[N-1];
endmodule
module andN #(parameter N=8)
	     (input [N-1:0] a,
	      output y);


   wire [N-1:1]      x;

   genvar 	     i;

   generate
      for (i=1; i<N; i=i+1)
	begin:ForLoop
	   if (i==1)
	     assign x[1] = a[0] & a[1];
	   else
	     assign x[i] = x[i-1] & a[i];
	end
      endgenerate

   assign y = x[N-1];
endmodule