data/full_repos/permissive/157135695/lab4iram1A.v
 line:24 column:22: Illegal character "'"
data/verilator_xmls/ec16c16b-77d1-445e-a916-6e618ce2ef8a.xml
module lab4iram1A(CLK, RESET, ADDR, Q);
  input         CLK;
  input         RESET;
  input  [7:0]  ADDR;
  output [15:0] Q;

  reg    [15:0] mem[0:127];

  wire   [6:0]  saddr;
  integer       i;


  assign saddr = ADDR[7:1];
  assign Q = mem[saddr];


  always @(posedge CLK) begin
    if(RESET) begin
      mem[0]   <= 16'b 1111000000000001;
      mem[1]   <= 16'b 0101000101111111;
      mem[2]   <= 16'b 0010101001111010;
      mem[3]   <= 16'b 0010101010111011;
      mem[4]   <= 16'b 1111000001011001;
      mem[5]   <= 16'b 0101011011111111;
      mem[6]   <= 16'b 1111000010100001;
      mem[7]   <= 16'b 0101100100111111;
      mem[8]   <= 16'b 0000000000000000;
      mem[9]   <= 16'b 1111001100101101;
      mem[10]  <= 16'b 1111011010110101;
      mem[11]  <= 16'b 1111101110111110;
      mem[12]  <= 16'b 0101000101000100;
      mem[13]  <= 16'b 0100101111111000;
      mem[14]  <= 16'b 0110111101000001;
      mem[15]  <= 16'b 1111000101110000;
      mem[16]  <= 16'b 1111111000111011;
      mem[17]  <= 16'b 0110111101000001;
      mem[18]  <= 16'b 1111110101110000;
      mem[19]  <= 16'b 1111111000111011;
      mem[20]  <= 16'b 0110111101000001;
      mem[21]  <= 16'b 1111110101110000;
      mem[22]  <= 16'b 1111111000111011;
      mem[23]  <= 16'b 0110111101000001;
      mem[24]  <= 16'b 1111110101110000;
      mem[25]  <= 16'b 1111111000111011;
      mem[26]  <= 16'b 0110111101000001;
      mem[27]  <= 16'b 1111110101110000;
      mem[28]  <= 16'b 1111111000111011;
      mem[29]  <= 16'b 0110111101000001;
      mem[30]  <= 16'b 1111110101110000;
      mem[31]  <= 16'b 1111111000111011;
      mem[32]  <= 16'b 0110111101000001;
      mem[33]  <= 16'b 1111110101110000;
      mem[34]  <= 16'b 1111111000111011;
      mem[35]  <= 16'b 0110111101000001;
      mem[36]  <= 16'b 1111110101110000;
      mem[37]  <= 16'b 0100000110111111;
      mem[38]  <= 16'b 0101000101111000;
      mem[39]  <= 16'b 0101000001001000;
      mem[40]  <= 16'b 1111001110100001;
      mem[41]  <= 16'b 0100101100000110;

      for(i = 42; i < 128; i = i + 1) begin
        mem[i] <= 16'b0000000000000000;
      end
    end
  end

endmodule
module lab4iram1A(CLK, RESET, ADDR, Q);

  input         CLK;
  input         RESET;
  input  [7:0]  ADDR;
  output [15:0] Q;

  reg    [15:0] mem[0:127];

  wire   [6:0]  saddr;
  integer       i;


  assign saddr = ADDR[7:1];
  assign Q = mem[saddr];


  always @(posedge CLK) begin
    if(RESET) begin
      mem[0]   <= 16'b 1111000000000001;
      mem[1]   <= 16'b 0101000101111111;
      mem[2]   <= 16'b 0010101001111010;
      mem[3]   <= 16'b 0010101010111011;
      mem[4]   <= 16'b 1111000001011001;
      mem[5]   <= 16'b 0101011011111111;
      mem[6]   <= 16'b 1111000010100001;
      mem[7]   <= 16'b 0101100100111111;
      mem[8]   <= 16'b 0000000000000000;
      mem[9]   <= 16'b 1111001100101101;
      mem[10]  <= 16'b 1111011010110101;
      mem[11]  <= 16'b 1111101110111110;
      mem[12]  <= 16'b 0101000101000100;
      mem[13]  <= 16'b 0100101111111000;
      mem[14]  <= 16'b 0110111101000001;
      mem[15]  <= 16'b 1111000101110000;
      mem[16]  <= 16'b 1111111000111011;
      mem[17]  <= 16'b 0110111101000001;
      mem[18]  <= 16'b 1111110101110000;
      mem[19]  <= 16'b 1111111000111011;
      mem[20]  <= 16'b 0110111101000001;
      mem[21]  <= 16'b 1111110101110000;
      mem[22]  <= 16'b 1111111000111011;
      mem[23]  <= 16'b 0110111101000001;
      mem[24]  <= 16'b 1111110101110000;
      mem[25]  <= 16'b 1111111000111011;
      mem[26]  <= 16'b 0110111101000001;
      mem[27]  <= 16'b 1111110101110000;
      mem[28]  <= 16'b 1111111000111011;
      mem[29]  <= 16'b 0110111101000001;
      mem[30]  <= 16'b 1111110101110000;
      mem[31]  <= 16'b 1111111000111011;
      mem[32]  <= 16'b 0110111101000001;
      mem[33]  <= 16'b 1111110101110000;
      mem[34]  <= 16'b 1111111000111011;
      mem[35]  <= 16'b 0110111101000001;
      mem[36]  <= 16'b 1111110101110000;
      mem[37]  <= 16'b 0100000110111111;
      mem[38]  <= 16'b 0101000101111000;
      mem[39]  <= 16'b 0101000001001000;
      mem[40]  <= 16'b 1111001110100001;
      mem[41]  <= 16'b 0100101100000110;

      for(i = 42; i < 128; i = i + 1) begin
        mem[i] <= 16'b0000000000000000;
      end
    end
  end

endmodule