data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v
1: b"%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:25: syntax error, unexpected ',', expecting IDENTIFIER or do or final\n    input wire int,\n                  ^\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:29: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire inst_wr,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [1:0] inst_size,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] inst_addr,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:32: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] inst_wdata,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [31:0] inst_rdata,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:34: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire inst_addr_ok,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire inst_data_ok,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:38: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire data_req,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:39: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire data_wr,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:40: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [1:0] data_size,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:41: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] data_addr,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:42: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] data_wdata,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:43: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [31:0] data_rdata,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:44: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire data_addr_ok,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:45: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire data_data_ok,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:62: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] debug_wb_pc,   \n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:63: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [ 3:0] debug_wb_rf_wen,  \n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:64: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [ 4:0] debug_wb_rf_wnum, \n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:65: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] debug_wb_rf_wdata  \n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:96: syntax error, unexpected ')', expecting ',' or ';'\n    );\n    ^\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:141: syntax error, unexpected assign\n    assign IF_allow_in = (IF_over & ID_allow_in) | cancel;\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:231: syntax error, unexpected always\n    always @(posedge clk) \n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/pipeline_cpu.v:323: syntax error, unexpected assign\n    assign next_fetch = IF_allow_in;\n    ^~~~~~\n%Error: Exiting due to 24 error(s)\n"
module pipeline_cpu(
    input wire clk,
    input wire resetn,
    input wire int,
    

    output wire inst_req,
    output wire inst_wr,
    output wire [1:0] inst_size,
    output wire [31:0] inst_addr,
    output wire [31:0] inst_wdata,
    input wire [31:0] inst_rdata,
    input wire inst_addr_ok,
    input wire inst_data_ok,
    

    output wire data_req,
    output wire data_wr,
    output wire [1:0] data_size,
    output wire [31:0] data_addr,
    output wire [31:0] data_wdata,
    input wire [31:0] data_rdata,
    input wire data_addr_ok,
    input wire data_data_ok,
    















    output wire [31:0] debug_wb_pc,
    output wire [ 3:0] debug_wb_rf_wen,
    output wire [ 4:0] debug_wb_rf_wnum,
    output wire [31:0] debug_wb_rf_wdata













    




    



    







    );


     wire [4:0] rf_addr;
     wire [31:0] mem_addr;
     wire [31:0] rf_data;
     wire [31:0] mem_data;
     wire [31:0] IF_pc;
     wire [31:0] IF_inst;
     wire [31:0] ID_pc;
     wire [31:0] EXE_pc;
     wire [31:0] MEM_pc;
     wire [31:0] WB_pc;
    

     wire [31:0] cpu_5_valid;
     wire [31:0] HI_data;
     wire [31:0] LO_data;





    reg IF_valid;
    reg ID_valid;
    reg EXE_valid;
    reg MEM_valid;
    reg WB_valid;

    wire IF_over;
    wire ID_over;
    wire EXE_over;
    wire MEM_over;
    wire WB_over;

    wire IF_allow_in;
    wire ID_allow_in;
    wire EXE_allow_in;
    wire MEM_allow_in;
    wire WB_allow_in;


    wire cancel;


    assign IF_allow_in = (IF_over & ID_allow_in) | cancel;
    assign ID_allow_in = ~ID_valid | (ID_over & EXE_allow_in);
    assign EXE_allow_in = ~EXE_valid | (EXE_over & MEM_allow_in);
    assign MEM_allow_in = ~MEM_valid | (MEM_over & WB_allow_in);
    assign WB_allow_in = ~WB_valid | WB_over;


    always @(posedge clk)
    begin
        if (!resetn)
        begin

            IF_valid <= 1'b0;
        end
        else
        begin
            IF_valid <= 1'b1;
        end
    end


    always @(posedge clk) begin
        if (!resetn || cancel)
        begin

            ID_valid <= 1'b0;
        end
        else if (ID_allow_in)
        begin
            ID_valid <= IF_over;
        end
    end


    always @(posedge clk) begin
        if (!resetn || cancel) 
        begin

            EXE_valid <= 1'b0;    
        end
        else if (EXE_allow_in)
        begin
            EXE_valid <= ID_over;    
        end
    end


    always @(posedge clk) begin
        if (!resetn || cancel)
        begin

            MEM_valid <= 1'b0;
        end
        else if (MEM_allow_in) 
        begin
            MEM_valid <= EXE_over;    
        end
    end
    

    always @(posedge clk) begin
        if (!resetn || cancel)
        begin

            WB_valid <= 1'b0;   
        end
        else if (WB_allow_in)
        begin
            WB_valid <= MEM_over;    
        end
    end







    wire [ 65:0] IF_ID_bus;
    wire [181:0] ID_EXE_bus;
    wire [166:0] EXE_MEM_bus;
    wire [160:0] MEM_WB_bus;


    reg [ 65:0] IF_ID_bus_r;
    reg [181:0] ID_EXE_bus_r;
    reg [166:0] EXE_MEM_bus_r;
    reg [160:0] MEM_WB_bus_r;


    always @(posedge clk) 
    begin
        if (IF_over && ID_allow_in) 
        begin
            IF_ID_bus_r <= IF_ID_bus;    
        end
    end


    always @(posedge clk)
    begin
        if (ID_over && EXE_allow_in)
        begin
            ID_EXE_bus_r <= ID_EXE_bus;            
        end
    end


    always @(posedge clk)
    begin
        if (EXE_over && MEM_allow_in)
        begin
            EXE_MEM_bus_r <= EXE_MEM_bus;
        end
    end


    always @(posedge clk)
    begin
        if (!resetn)
        begin
            MEM_WB_bus_r <= 161'd0;
        end
        else if (MEM_over && WB_allow_in)
        begin
            MEM_WB_bus_r <= MEM_WB_bus;
        end
    end





    wire [32:0] jbr_bus;


    wire inst_en;
    wire [3:0] inst_wen;
    wire [31:0] inst;



    wire [ 4:0] EXE_wdest;
    wire [ 4:0] MEM_wdest;
    wire [ 4:0] WB_wdest;
    wire [31:0] EXE_result_quick_get;
    wire [31:0] MEM_result_quick_get;
    wire EXE_quick_en;
    wire MEM_quick_en;


    wire dm_en;
    wire [ 3:0] dm_wen;
    wire [31:0] dm_addr;
    wire [31:0] dm_wdata;
    wire [31:0] dm_rdata;


    wire [ 4:0] rs;
    wire [ 4:0] rt;
    wire [31:0] rs_value;
    wire [31:0] rt_value;


    wire [ 3:0] rf_wen;
    wire [ 4:0] rf_wdest;
    wire [31:0] rf_wdata;


    wire [32:0] exc_bus;




    wire next_fetch;
    wire inst_jbr;
    wire mem_req;


    


    assign next_fetch = IF_allow_in;
    assign inst_wr = 1'b0;
    assign inst_size = 2'b10;
    assign inst_wdata = 32'd0;
    assign inst = inst_rdata;

    
    

    assign data_size = ~data_wr ? 2'b10
                     : ((dm_wen == 4'b0001)||(dm_wen == 4'b0010)||(dm_wen == 4'b0100)||(dm_wen == 4'b1000)) ? 2'b00
                     : ((dm_wen == 4'b0011)||(dm_wen == 4'b1100)) ? 2'b01
                     : (dm_wen == 4'b1111) ? 2'b10 : 2'b00;
    assign data_addr = ~data_addr_ok ? 32'hxxxxxxxx
                     : data_wr ? {3'd0,dm_addr[28:0]} : {3'd0,dm_addr[28:2],2'd0};
                     
    assign data_req = mem_req & ~cancel;
    assign data_wdata = dm_wdata;
    assign dm_rdata = data_rdata;





    fetch IF_module(
        .clk       (clk       ),
        .resetn    (resetn    ),
        .IF_valid  (IF_valid  ),
        .next_fetch(next_fetch),
        .inst_addr_ok(inst_addr_ok),
        .inst_data_ok(inst_data_ok),
        .inst      (inst      ),
        .jbr_bus   (jbr_bus   ),
        .inst_req  (inst_req  ),
        .inst_addr (inst_addr ),
        .IF_over   (IF_over   ),
        .IF_ID_bus (IF_ID_bus ),
        

        .exc_bus   (exc_bus   ),
        .is_ds     (inst_jbr  ),
        .ID_pc     (ID_pc     ),


        .IF_pc     (IF_pc     ),
        .IF_inst   (IF_inst   )
    );

    decode ID_module(
        .ID_valid   (ID_valid   ),
        .IF_ID_bus_r(IF_ID_bus_r),
        .rs_value   (rs_value   ),
        .rt_value   (rt_value   ),
        .rs         (rs         ),
        .rt         (rt         ),
        .jbr_bus    (jbr_bus    ),
        .inst_jbr   (inst_jbr   ),
        .ID_over    (ID_over    ),
        .ID_EXE_bus (ID_EXE_bus ),
        

        .IF_over     (IF_over     ),
        .EXE_over    (EXE_over    ),
        .MEM_over    (MEM_over    ),
        .EXE_wdest   (EXE_wdest   ),
        .MEM_wdest   (MEM_wdest   ),
        .WB_wdest    (WB_wdest    ),
        .EXE_result_quick_get(EXE_result_quick_get),
        .MEM_result_quick_get(MEM_result_quick_get),
        .EXE_quick_en(EXE_quick_en),
        .MEM_quick_en(MEM_quick_en),
        

        .ID_pc       (ID_pc       )
    ); 

    exe EXE_module(
        .EXE_valid   (EXE_valid   ),
        .ID_EXE_bus_r(ID_EXE_bus_r),
        .EXE_over    (EXE_over    ),
        .EXE_MEM_bus (EXE_MEM_bus ),
        

        .clk         (clk         ),
        .EXE_wdest   (EXE_wdest   ),
        .EXE_result_quick_get(EXE_result_quick_get),
        .EXE_quick_en(EXE_quick_en),
        

        .EXE_pc      (EXE_pc      )
    );

    mem MEM_module(
        .clk          (clk          ),
        .resetn       (resetn       ),
        .MEM_valid    (MEM_valid    ),
        .EXE_MEM_bus_r(EXE_MEM_bus_r),
        .dm_rdata     (dm_rdata     ),
        .cancel       (cancel       ),
        .data_addr_ok (data_addr_ok ),
        .data_data_ok (data_data_ok ),
        .data_req     (mem_req     ),
        .data_wr      (data_wr      ),
        .dm_addr      (dm_addr      ),
        .dm_en 		  (dm_en 		),
        .dm_wen       (dm_wen       ),
        .dm_wdata     (dm_wdata     ),
        .MEM_over     (MEM_over     ),
        .MEM_WB_bus   (MEM_WB_bus   ),
        

        .MEM_allow_in (MEM_allow_in ),
        .MEM_wdest    (MEM_wdest    ),
        .MEM_result_quick_get(MEM_result_quick_get),
        .MEM_quick_en (MEM_quick_en),


        .MEM_pc       (MEM_pc       )
    );          
 
    wb WB_module(
        .WB_valid    (WB_valid    ),
        .MEM_WB_bus_r(MEM_WB_bus_r),
        .rf_wen      (rf_wen      ),
        .rf_wdest    (rf_wdest    ),
        .rf_wdata    (rf_wdata    ),
        .WB_over     (WB_over     ),
        

        .clk         (clk         ),
      	.resetn      (resetn      ),
        .exc_bus     (exc_bus     ),
        .WB_wdest    (WB_wdest    ),
        .cancel      (cancel      ),
        

        .WB_pc       (WB_pc       ),
        .HI_data     (HI_data     ),
        .LO_data     (LO_data     )
    );







    regfile rf_module(
        .clk    (clk      ),
        .resetn (resetn   ),
        .wen    (rf_wen   ),
        .raddr1 (rs       ),
        .raddr2 (rt       ),
        .waddr  (rf_wdest ),
        .wdata  (rf_wdata ),
        .rdata1 (rs_value ),
        .rdata2 (rt_value ),


        .test_addr(rf_addr),
        .test_data(rf_data)
    );
    





















    




    



	assign debug_wb_pc = WB_pc;
	assign debug_wb_rf_wen = rf_wen;
	assign debug_wb_rf_wnum = rf_wdest;
	assign debug_wb_rf_wdata = rf_wdata;


endmodule
module pipeline_cpu(
    input wire clk,
    input wire resetn,
    input wire int,
    

    output wire inst_req,
    output wire inst_wr,
    output wire [1:0] inst_size,
    output wire [31:0] inst_addr,
    output wire [31:0] inst_wdata,
    input wire [31:0] inst_rdata,
    input wire inst_addr_ok,
    input wire inst_data_ok,
    

    output wire data_req,
    output wire data_wr,
    output wire [1:0] data_size,
    output wire [31:0] data_addr,
    output wire [31:0] data_wdata,
    input wire [31:0] data_rdata,
    input wire data_addr_ok,
    input wire data_data_ok,
    















    output wire [31:0] debug_wb_pc,
    output wire [ 3:0] debug_wb_rf_wen,
    output wire [ 4:0] debug_wb_rf_wnum,
    output wire [31:0] debug_wb_rf_wdata













    




    



    







    );



     wire [4:0] rf_addr;
     wire [31:0] mem_addr;
     wire [31:0] rf_data;
     wire [31:0] mem_data;
     wire [31:0] IF_pc;
     wire [31:0] IF_inst;
     wire [31:0] ID_pc;
     wire [31:0] EXE_pc;
     wire [31:0] MEM_pc;
     wire [31:0] WB_pc;
    

     wire [31:0] cpu_5_valid;
     wire [31:0] HI_data;
     wire [31:0] LO_data;





    reg IF_valid;
    reg ID_valid;
    reg EXE_valid;
    reg MEM_valid;
    reg WB_valid;

    wire IF_over;
    wire ID_over;
    wire EXE_over;
    wire MEM_over;
    wire WB_over;

    wire IF_allow_in;
    wire ID_allow_in;
    wire EXE_allow_in;
    wire MEM_allow_in;
    wire WB_allow_in;


    wire cancel;


    assign IF_allow_in = (IF_over & ID_allow_in) | cancel;
    assign ID_allow_in = ~ID_valid | (ID_over & EXE_allow_in);
    assign EXE_allow_in = ~EXE_valid | (EXE_over & MEM_allow_in);
    assign MEM_allow_in = ~MEM_valid | (MEM_over & WB_allow_in);
    assign WB_allow_in = ~WB_valid | WB_over;


    always @(posedge clk)
    begin
        if (!resetn)
        begin

            IF_valid <= 1'b0;
        end
        else
        begin
            IF_valid <= 1'b1;
        end
    end


    always @(posedge clk) begin
        if (!resetn || cancel)
        begin

            ID_valid <= 1'b0;
        end
        else if (ID_allow_in)
        begin
            ID_valid <= IF_over;
        end
    end


    always @(posedge clk) begin
        if (!resetn || cancel) 
        begin

            EXE_valid <= 1'b0;    
        end
        else if (EXE_allow_in)
        begin
            EXE_valid <= ID_over;    
        end
    end


    always @(posedge clk) begin
        if (!resetn || cancel)
        begin

            MEM_valid <= 1'b0;
        end
        else if (MEM_allow_in) 
        begin
            MEM_valid <= EXE_over;    
        end
    end
    

    always @(posedge clk) begin
        if (!resetn || cancel)
        begin

            WB_valid <= 1'b0;   
        end
        else if (WB_allow_in)
        begin
            WB_valid <= MEM_over;    
        end
    end







    wire [ 65:0] IF_ID_bus;
    wire [181:0] ID_EXE_bus;
    wire [166:0] EXE_MEM_bus;
    wire [160:0] MEM_WB_bus;


    reg [ 65:0] IF_ID_bus_r;
    reg [181:0] ID_EXE_bus_r;
    reg [166:0] EXE_MEM_bus_r;
    reg [160:0] MEM_WB_bus_r;


    always @(posedge clk) 
    begin
        if (IF_over && ID_allow_in) 
        begin
            IF_ID_bus_r <= IF_ID_bus;    
        end
    end


    always @(posedge clk)
    begin
        if (ID_over && EXE_allow_in)
        begin
            ID_EXE_bus_r <= ID_EXE_bus;            
        end
    end


    always @(posedge clk)
    begin
        if (EXE_over && MEM_allow_in)
        begin
            EXE_MEM_bus_r <= EXE_MEM_bus;
        end
    end


    always @(posedge clk)
    begin
        if (!resetn)
        begin
            MEM_WB_bus_r <= 161'd0;
        end
        else if (MEM_over && WB_allow_in)
        begin
            MEM_WB_bus_r <= MEM_WB_bus;
        end
    end





    wire [32:0] jbr_bus;


    wire inst_en;
    wire [3:0] inst_wen;
    wire [31:0] inst;



    wire [ 4:0] EXE_wdest;
    wire [ 4:0] MEM_wdest;
    wire [ 4:0] WB_wdest;
    wire [31:0] EXE_result_quick_get;
    wire [31:0] MEM_result_quick_get;
    wire EXE_quick_en;
    wire MEM_quick_en;


    wire dm_en;
    wire [ 3:0] dm_wen;
    wire [31:0] dm_addr;
    wire [31:0] dm_wdata;
    wire [31:0] dm_rdata;


    wire [ 4:0] rs;
    wire [ 4:0] rt;
    wire [31:0] rs_value;
    wire [31:0] rt_value;


    wire [ 3:0] rf_wen;
    wire [ 4:0] rf_wdest;
    wire [31:0] rf_wdata;


    wire [32:0] exc_bus;




    wire next_fetch;
    wire inst_jbr;
    wire mem_req;


    


    assign next_fetch = IF_allow_in;
    assign inst_wr = 1'b0;
    assign inst_size = 2'b10;
    assign inst_wdata = 32'd0;
    assign inst = inst_rdata;

    
    

    assign data_size = ~data_wr ? 2'b10
                     : ((dm_wen == 4'b0001)||(dm_wen == 4'b0010)||(dm_wen == 4'b0100)||(dm_wen == 4'b1000)) ? 2'b00
                     : ((dm_wen == 4'b0011)||(dm_wen == 4'b1100)) ? 2'b01
                     : (dm_wen == 4'b1111) ? 2'b10 : 2'b00;
    assign data_addr = ~data_addr_ok ? 32'hxxxxxxxx
                     : data_wr ? {3'd0,dm_addr[28:0]} : {3'd0,dm_addr[28:2],2'd0};
                     
    assign data_req = mem_req & ~cancel;
    assign data_wdata = dm_wdata;
    assign dm_rdata = data_rdata;





    fetch IF_module(
        .clk       (clk       ),
        .resetn    (resetn    ),
        .IF_valid  (IF_valid  ),
        .next_fetch(next_fetch),
        .inst_addr_ok(inst_addr_ok),
        .inst_data_ok(inst_data_ok),
        .inst      (inst      ),
        .jbr_bus   (jbr_bus   ),
        .inst_req  (inst_req  ),
        .inst_addr (inst_addr ),
        .IF_over   (IF_over   ),
        .IF_ID_bus (IF_ID_bus ),
        

        .exc_bus   (exc_bus   ),
        .is_ds     (inst_jbr  ),
        .ID_pc     (ID_pc     ),


        .IF_pc     (IF_pc     ),
        .IF_inst   (IF_inst   )
    );

    decode ID_module(
        .ID_valid   (ID_valid   ),
        .IF_ID_bus_r(IF_ID_bus_r),
        .rs_value   (rs_value   ),
        .rt_value   (rt_value   ),
        .rs         (rs         ),
        .rt         (rt         ),
        .jbr_bus    (jbr_bus    ),
        .inst_jbr   (inst_jbr   ),
        .ID_over    (ID_over    ),
        .ID_EXE_bus (ID_EXE_bus ),
        

        .IF_over     (IF_over     ),
        .EXE_over    (EXE_over    ),
        .MEM_over    (MEM_over    ),
        .EXE_wdest   (EXE_wdest   ),
        .MEM_wdest   (MEM_wdest   ),
        .WB_wdest    (WB_wdest    ),
        .EXE_result_quick_get(EXE_result_quick_get),
        .MEM_result_quick_get(MEM_result_quick_get),
        .EXE_quick_en(EXE_quick_en),
        .MEM_quick_en(MEM_quick_en),
        

        .ID_pc       (ID_pc       )
    ); 

    exe EXE_module(
        .EXE_valid   (EXE_valid   ),
        .ID_EXE_bus_r(ID_EXE_bus_r),
        .EXE_over    (EXE_over    ),
        .EXE_MEM_bus (EXE_MEM_bus ),
        

        .clk         (clk         ),
        .EXE_wdest   (EXE_wdest   ),
        .EXE_result_quick_get(EXE_result_quick_get),
        .EXE_quick_en(EXE_quick_en),
        

        .EXE_pc      (EXE_pc      )
    );

    mem MEM_module(
        .clk          (clk          ),
        .resetn       (resetn       ),
        .MEM_valid    (MEM_valid    ),
        .EXE_MEM_bus_r(EXE_MEM_bus_r),
        .dm_rdata     (dm_rdata     ),
        .cancel       (cancel       ),
        .data_addr_ok (data_addr_ok ),
        .data_data_ok (data_data_ok ),
        .data_req     (mem_req     ),
        .data_wr      (data_wr      ),
        .dm_addr      (dm_addr      ),
        .dm_en 		  (dm_en 		),
        .dm_wen       (dm_wen       ),
        .dm_wdata     (dm_wdata     ),
        .MEM_over     (MEM_over     ),
        .MEM_WB_bus   (MEM_WB_bus   ),
        

        .MEM_allow_in (MEM_allow_in ),
        .MEM_wdest    (MEM_wdest    ),
        .MEM_result_quick_get(MEM_result_quick_get),
        .MEM_quick_en (MEM_quick_en),


        .MEM_pc       (MEM_pc       )
    );          
 
    wb WB_module(
        .WB_valid    (WB_valid    ),
        .MEM_WB_bus_r(MEM_WB_bus_r),
        .rf_wen      (rf_wen      ),
        .rf_wdest    (rf_wdest    ),
        .rf_wdata    (rf_wdata    ),
        .WB_over     (WB_over     ),
        

        .clk         (clk         ),
      	.resetn      (resetn      ),
        .exc_bus     (exc_bus     ),
        .WB_wdest    (WB_wdest    ),
        .cancel      (cancel      ),
        

        .WB_pc       (WB_pc       ),
        .HI_data     (HI_data     ),
        .LO_data     (LO_data     )
    );







    regfile rf_module(
        .clk    (clk      ),
        .resetn (resetn   ),
        .wen    (rf_wen   ),
        .raddr1 (rs       ),
        .raddr2 (rt       ),
        .waddr  (rf_wdest ),
        .wdata  (rf_wdata ),
        .rdata1 (rs_value ),
        .rdata2 (rt_value ),


        .test_addr(rf_addr),
        .test_data(rf_data)
    );
    





















    




    



	assign debug_wb_pc = WB_pc;
	assign debug_wb_rf_wen = rf_wen;
	assign debug_wb_rf_wnum = rf_wdest;
	assign debug_wb_rf_wdata = rf_wdata;


endmodule