data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp
 line:18: before: "parameter"
1: b"%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:17: Define or directive not defined: '`mname'\nmodule   `mname`  #(\n         ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:17: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule   `mname`  #(\n               ^\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:19: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:40: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic                  res_p\n  ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:53: syntax error, unexpected always_ff\nalways_ff @(posedge clk or negedge rst_n) begin\n^~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:63: Unsupported or unknown PLI call: $op_a_r\n`$op_a_r->mname()` #(.DataWidth(DataWidth)) `$op_a_r->iname()`\n ^~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:63: Unsupported or unknown PLI call: $op_a_r\n`$op_a_r->mname()` #(.DataWidth(DataWidth)) `$op_a_r->iname()`\n                                             ^~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:75: Unsupported or unknown PLI call: $op_b_r\n`$op_b_r->mname()` #(.DataWidth(DataWidth)) `$op_b_r->iname()`\n ^~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:75: Unsupported or unknown PLI call: $op_b_r\n`$op_b_r->mname()` #(.DataWidth(DataWidth)) `$op_b_r->iname()`\n                                             ^~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:89: Unsupported or unknown PLI call: $op_c_r\n`$op_c_r->mname()` #(.DataWidth(DataWidth)) `$op_c_r->iname()`\n ^~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:89: Unsupported or unknown PLI call: $op_c_r\n`$op_c_r->mname()` #(.DataWidth(DataWidth)) `$op_c_r->iname()`\n                                             ^~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:103: Unsupported or unknown PLI call: $op_d_r\n`$op_d_r->mname()` #(.DataWidth(1)) `$op_d_r->iname()`\n ^~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:103: Unsupported or unknown PLI call: $op_d_r\n`$op_d_r->mname()` #(.DataWidth(1)) `$op_d_r->iname()`\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:127: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\nlocalparam NUM_ADDERS = `$use_add`;\n                        ^\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:127: Unsupported or unknown PLI call: $use_add\nlocalparam NUM_ADDERS = `$use_add`;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:137: syntax error, unexpected genvar\ngenvar ggg;\n^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:142: Unsupported or unknown PLI call: $full_add\n  `$full_add->mname()` #(.DataWidth(DataWidth)) `$full_add->iname()`\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:142: Unsupported or unknown PLI call: $full_add\n  `$full_add->mname()` #(.DataWidth(DataWidth)) `$full_add->iname()`\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:155: syntax error, unexpected assign\nassign add_res_0 = add_res[0];\n^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:169: syntax error, unexpected $undefined\n`$lut->mname()` #(.DataWidth(DataWidth)) `$lut->iname()`\n^\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:169: Unsupported or unknown PLI call: $lut\n`$lut->mname()` #(.DataWidth(DataWidth)) `$lut->iname()`\n ^~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:169: Unsupported or unknown PLI call: $lut\n`$lut->mname()` #(.DataWidth(DataWidth)) `$lut->iname()`\n                                          ^~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:180: Unsupported or unknown PLI call: $c_in_slice\n  .op_c_in  (op_c`$c_in_slice`),\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:192: syntax error, unexpected $undefined\n`$mult->mname()` #(.DataWidth(DataWidth)) `$mult->iname()`\n^\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:192: Unsupported or unknown PLI call: $mult\n`$mult->mname()` #(.DataWidth(DataWidth)) `$mult->iname()`\n ^~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_pe.svp:192: Unsupported or unknown PLI call: $mult\n`$mult->mname()` #(.DataWidth(DataWidth)) `$mult->iname()`\n                                           ^~~~~\n%Error: Exiting due to 26 error(s)\n"
module   `mname`  #(
  parameter DataWidth = 16
) (
  input                clk,
  input                rst_n,


  input         [15:0] cfg_d,
  input         [7:0]  cfg_a,
  input                cfg_en,


  input [15:0]                  op_code,


  input  [DataWidth-1:0]        op_a_in,
  input  [DataWidth-1:0]        op_b_in,

  input  [DataWidth-1:0]        op_c_in,

  input                         op_d_p_in,

  output logic [DataWidth-1:0]  res,
  output logic                  res_p
);

logic  [DataWidth-1:0]        op_a;
logic  [DataWidth-1:0]        op_b;

logic  [DataWidth-1:0]        op_c;

logic                         op_d_p;



logic [15:0] op_code;
always_ff @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    op_code <= 4'h0;
  end else if(cfg_en && (&cfg_a)) begin
    op_code <= cfg_d;
  end
end



`$op_a_r->mname()` #(.DataWidth(DataWidth)) `$op_a_r->iname()`
(
  .clk     (clk),
  .rst_n   (rst_n),
  .load    (cfg_en && (cfg_a == 8'hF0)),
  .val     (cfg_d[DataWidth-1:0]),
  .sel     (op_code[15]),
  .data_in (op_a_in),
  .res     (op_a)
);


`$op_b_r->mname()` #(.DataWidth(DataWidth)) `$op_b_r->iname()`
(
  .clk     (clk),
  .rst_n   (rst_n),
  .load    (cfg_en && (cfg_a == 8'hF1)),
  .val     (cfg_d[DataWidth-1:0]),
  .sel     (op_code[14]),
  .data_in (op_b_in),
  .res     (op_b)
);




`$op_c_r->mname()` #(.DataWidth(DataWidth)) `$op_c_r->iname()`
(
  .clk     (clk),
  .rst_n   (rst_n),
  .load    (cfg_en && (cfg_a == 8'hF2)),
  .val     (cfg_d[DataWidth-1:0]),
  .sel     (op_code[15]),
  .data_in (op_c_in),
  .res     (op_c)
);




`$op_d_r->mname()` #(.DataWidth(1)) `$op_d_r->iname()`
(
  .clk     (clk),
  .rst_n   (rst_n),
  .load    (cfg_en && (cfg_a == 8'hF3)),
  .val     (cfg_d[0]),
  .sel     (op_code[15]),
  .data_in (op_d_p_in),
  .res     (op_d_p)
);



assign op_a = op_a_in;
assign op_b = op_b_in;

assign op_c = op_c_in;

assign op_d_p = op_d_p_in;





localparam NUM_ADDERS = `$use_add`;
localparam ADD_MSB = NUM_ADDERS - 1;

logic [DataWidth-1:0]  add_a     [ADD_MSB:0];
logic [DataWidth-1:0]  add_b     [ADD_MSB:0];
logic                  add_c_in  [ADD_MSB:0];

logic [DataWidth-1:0]  add_res   [ADD_MSB:0];
logic                  add_c_out [ADD_MSB:0];

genvar ggg;

generate
  for(ggg=0;ggg<NUM_ADDERS;ggg=ggg+1) begin

  `$full_add->mname()` #(.DataWidth(DataWidth)) `$full_add->iname()`
    (
      .a     (add_a[ggg]),
      .b     (add_b[ggg]),
      .c_in  (add_c_in[ggg]),

      .res   (add_res[ggg]),
      .c_out (add_c_out[ggg])
    );
  end
endgenerate

logic [DataWidth-1:0]  add_res_0;
assign add_res_0 = add_res[0];



logic [DataWidth-1:0] res_w;
logic                 res_p_w;


logic [DataWidth-1:0] res_lut;





`$lut->mname()` #(.DataWidth(DataWidth)) `$lut->iname()`
(
  .cfg_clk  (clk),
  .cfg_rst_n(rst_n),
  .cfg_d    (cfg_d),
  .cfg_a    (cfg_a),
  .cfg_en   (cfg_en),

  .op_a_in  (op_a),
  .op_b_in  (op_b),

  .op_c_in  (op_c`$c_in_slice`),


  .res      (res_lut)
);



logic [2*DataWidth-1:0] mult_res;
logic                 mult_c_out;


`$mult->mname()` #(.DataWidth(DataWidth)) `$mult->iname()`
(
  .a  (op_a),
  .b  (op_b),

  .c  (op_c),


  .res   (mult_res),
  .c_out (mult_c_out)
);


always_comb begin : proc_alu

  add_a[0] = op_a;
  add_b[0] = op_b;
  add_c_in[0] = 1'b0;


  add_a[1] = add_res[0];
  add_b[1] = op_c;
  add_c_in[1] = 1'b0;


  res_w   = add_res[ADD_MSB];
  res_p_w = add_c_out[ADD_MSB];

  res_w = 'hX;
  res_p_w = 'hX;



  case (op_code)

    16'h0: begin
        ;

        add_c_in[1] = add_c_out[0];

      end
    16'h1: begin
        add_b[0]    = ~op_b;
        add_c_in[0] = 1'b1;

        add_c_in[1] = add_c_out[0];

      end
    16'h2: begin
        add_b[0]    = ~op_b;
        add_c_in[0] = 1'b1;
      end
    16'h4: begin
        add_b[0]    = ~op_b;
        add_c_in[0] = 1'b1;

        res_w   = add_res_0[DataWidth-1] ? op_a : op_b;
        res_p_w = ~add_res_0[DataWidth-1];
      end
    16'h5: begin
        add_b[0]    = ~op_b;
        add_c_in[0] = 1'b1;

        res_w   = ~add_res_0[DataWidth-1] ? op_a : op_b;
        res_p_w = add_res_0[DataWidth-1];
      end
    16'h6: begin
        res_p_w = ~|(op_a ^ op_b);
        res_w   = op_b;
      end
    16'h7: begin
        res_p_w = |(op_a ^ op_b);
        res_w   = op_a;
      end
    16'h8: begin
        res_w = op_d_p ? op_a : op_b;
      end


    16'h9: begin
         res_w = res_lut;
       end


    16'hA: begin
        add_a[1]    = add_res_0[DataWidth-1] ? ~add_res[0] : add_res[0];
        add_c_in[1] = add_res_0[DataWidth-1];
      end


    16'hF: begin
        res_w = op_a >> op_b[3:0];
      end
    16'h10: begin
        res_w = $signed(op_a) >>> op_b[3:0];
      end
    16'h11: begin
        res_w = op_a <<< op_b[3:0];
      end


    16'hB: begin
        res_w   = mult_res[15:0];
        res_p_w = mult_c_out;
      end
    16'hC: begin
        res_w   = mult_res[23:8];
        res_p_w = mult_c_out;
      end
    16'hD: begin
        res_w   = mult_res[31:16];
        res_p_w = mult_c_out;
      end


    16'h12: begin
        res_w = op_a | op_b;
      end
    16'h13: begin
        res_w = op_a & op_b;
      end
    16'h14: begin
        res_w = op_a ^ op_b;
      end
    16'h14: begin
        res_w = ~op_a;
      end



    default: begin
        res_w   = op_a;
        res_p_w = op_d_p;
      end
  endcase
end


always_ff @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    res   <= 16'h0;
    res_p <= 1'b0;
  end else begin
    res   <= res_w;
    res_p <= res_p_w;
  end
end

  assign res   = res_w;
  assign res_p = res_p_w;


endmodule
module   `mname`  #(
  parameter DataWidth = 16
) (
  input                clk,
  input                rst_n,


  input         [15:0] cfg_d,
  input         [7:0]  cfg_a,
  input                cfg_en,


  input [15:0]                  op_code,


  input  [DataWidth-1:0]        op_a_in,
  input  [DataWidth-1:0]        op_b_in,

  input  [DataWidth-1:0]        op_c_in,

  input                         op_d_p_in,

  output logic [DataWidth-1:0]  res,
  output logic                  res_p
);


logic  [DataWidth-1:0]        op_a;
logic  [DataWidth-1:0]        op_b;

logic  [DataWidth-1:0]        op_c;

logic                         op_d_p;



logic [15:0] op_code;
always_ff @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    op_code <= 4'h0;
  end else if(cfg_en && (&cfg_a)) begin
    op_code <= cfg_d;
  end
end



`$op_a_r->mname()` #(.DataWidth(DataWidth)) `$op_a_r->iname()`
(
  .clk     (clk),
  .rst_n   (rst_n),
  .load    (cfg_en && (cfg_a == 8'hF0)),
  .val     (cfg_d[DataWidth-1:0]),
  .sel     (op_code[15]),
  .data_in (op_a_in),
  .res     (op_a)
);


`$op_b_r->mname()` #(.DataWidth(DataWidth)) `$op_b_r->iname()`
(
  .clk     (clk),
  .rst_n   (rst_n),
  .load    (cfg_en && (cfg_a == 8'hF1)),
  .val     (cfg_d[DataWidth-1:0]),
  .sel     (op_code[14]),
  .data_in (op_b_in),
  .res     (op_b)
);




`$op_c_r->mname()` #(.DataWidth(DataWidth)) `$op_c_r->iname()`
(
  .clk     (clk),
  .rst_n   (rst_n),
  .load    (cfg_en && (cfg_a == 8'hF2)),
  .val     (cfg_d[DataWidth-1:0]),
  .sel     (op_code[15]),
  .data_in (op_c_in),
  .res     (op_c)
);




`$op_d_r->mname()` #(.DataWidth(1)) `$op_d_r->iname()`
(
  .clk     (clk),
  .rst_n   (rst_n),
  .load    (cfg_en && (cfg_a == 8'hF3)),
  .val     (cfg_d[0]),
  .sel     (op_code[15]),
  .data_in (op_d_p_in),
  .res     (op_d_p)
);



assign op_a = op_a_in;
assign op_b = op_b_in;

assign op_c = op_c_in;

assign op_d_p = op_d_p_in;





localparam NUM_ADDERS = `$use_add`;
localparam ADD_MSB = NUM_ADDERS - 1;

logic [DataWidth-1:0]  add_a     [ADD_MSB:0];
logic [DataWidth-1:0]  add_b     [ADD_MSB:0];
logic                  add_c_in  [ADD_MSB:0];

logic [DataWidth-1:0]  add_res   [ADD_MSB:0];
logic                  add_c_out [ADD_MSB:0];

genvar ggg;

generate
  for(ggg=0;ggg<NUM_ADDERS;ggg=ggg+1) begin

  `$full_add->mname()` #(.DataWidth(DataWidth)) `$full_add->iname()`
    (
      .a     (add_a[ggg]),
      .b     (add_b[ggg]),
      .c_in  (add_c_in[ggg]),

      .res   (add_res[ggg]),
      .c_out (add_c_out[ggg])
    );
  end
endgenerate

logic [DataWidth-1:0]  add_res_0;
assign add_res_0 = add_res[0];



logic [DataWidth-1:0] res_w;
logic                 res_p_w;


logic [DataWidth-1:0] res_lut;





`$lut->mname()` #(.DataWidth(DataWidth)) `$lut->iname()`
(
  .cfg_clk  (clk),
  .cfg_rst_n(rst_n),
  .cfg_d    (cfg_d),
  .cfg_a    (cfg_a),
  .cfg_en   (cfg_en),

  .op_a_in  (op_a),
  .op_b_in  (op_b),

  .op_c_in  (op_c`$c_in_slice`),


  .res      (res_lut)
);



logic [2*DataWidth-1:0] mult_res;
logic                 mult_c_out;


`$mult->mname()` #(.DataWidth(DataWidth)) `$mult->iname()`
(
  .a  (op_a),
  .b  (op_b),

  .c  (op_c),


  .res   (mult_res),
  .c_out (mult_c_out)
);


always_comb begin : proc_alu

  add_a[0] = op_a;
  add_b[0] = op_b;
  add_c_in[0] = 1'b0;


  add_a[1] = add_res[0];
  add_b[1] = op_c;
  add_c_in[1] = 1'b0;


  res_w   = add_res[ADD_MSB];
  res_p_w = add_c_out[ADD_MSB];

  res_w = 'hX;
  res_p_w = 'hX;



  case (op_code)

    16'h0: begin
        ;

        add_c_in[1] = add_c_out[0];

      end
    16'h1: begin
        add_b[0]    = ~op_b;
        add_c_in[0] = 1'b1;

        add_c_in[1] = add_c_out[0];

      end
    16'h2: begin
        add_b[0]    = ~op_b;
        add_c_in[0] = 1'b1;
      end
    16'h4: begin
        add_b[0]    = ~op_b;
        add_c_in[0] = 1'b1;

        res_w   = add_res_0[DataWidth-1] ? op_a : op_b;
        res_p_w = ~add_res_0[DataWidth-1];
      end
    16'h5: begin
        add_b[0]    = ~op_b;
        add_c_in[0] = 1'b1;

        res_w   = ~add_res_0[DataWidth-1] ? op_a : op_b;
        res_p_w = add_res_0[DataWidth-1];
      end
    16'h6: begin
        res_p_w = ~|(op_a ^ op_b);
        res_w   = op_b;
      end
    16'h7: begin
        res_p_w = |(op_a ^ op_b);
        res_w   = op_a;
      end
    16'h8: begin
        res_w = op_d_p ? op_a : op_b;
      end


    16'h9: begin
         res_w = res_lut;
       end


    16'hA: begin
        add_a[1]    = add_res_0[DataWidth-1] ? ~add_res[0] : add_res[0];
        add_c_in[1] = add_res_0[DataWidth-1];
      end


    16'hF: begin
        res_w = op_a >> op_b[3:0];
      end
    16'h10: begin
        res_w = $signed(op_a) >>> op_b[3:0];
      end
    16'h11: begin
        res_w = op_a <<< op_b[3:0];
      end


    16'hB: begin
        res_w   = mult_res[15:0];
        res_p_w = mult_c_out;
      end
    16'hC: begin
        res_w   = mult_res[23:8];
        res_p_w = mult_c_out;
      end
    16'hD: begin
        res_w   = mult_res[31:16];
        res_p_w = mult_c_out;
      end


    16'h12: begin
        res_w = op_a | op_b;
      end
    16'h13: begin
        res_w = op_a & op_b;
      end
    16'h14: begin
        res_w = op_a ^ op_b;
      end
    16'h14: begin
        res_w = ~op_a;
      end



    default: begin
        res_w   = op_a;
        res_p_w = op_d_p;
      end
  endcase
end


always_ff @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    res   <= 16'h0;
    res_p <= 1'b0;
  end else begin
    res   <= res_w;
    res_p <= res_p_w;
  end
end

  assign res   = res_w;
  assign res_p = res_p_w;


endmodule