data/full_repos/permissive/170402453/test7Seg.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/170402453/test7Seg.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/170402453/test7Seg.v:39: Cannot find file containing module: \'Segment7\'\n Segment7 uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/Segment7\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/Segment7.v\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/Segment7.sv\n             Segment7\n             Segment7.v\n             Segment7.sv\n             obj_dir/Segment7\n             obj_dir/Segment7.v\n             obj_dir/Segment7.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test7Seg;


	reg CLK;
	reg [7:0] DATA1;
	reg [7:0] DATA2;
	reg [7:0] DATA3;
	reg [7:0] DATA4;


	wire [7:0] SEGMENT;
	wire [3:0] DIG;


	Segment7 uut (
		.CLK(CLK), 
		.DATA1(DATA1), 
		.DATA2(DATA2), 
		.DATA3(DATA3), 
		.DATA4(DATA4), 
		.SEGMENT(SEGMENT), 
		.DIG(DIG)
	);

	initial begin

		CLK = 0;
		DATA1 = 0;
		DATA2 = 0;
		DATA3 = 0;
		DATA4 = 0;


		#100;
        

		DATA1 = "1";
		DATA1 = "2";
		DATA1 = "3";
		DATA1 = "4";

	end
      
endmodule
module test7Seg;



	reg CLK;
	reg [7:0] DATA1;
	reg [7:0] DATA2;
	reg [7:0] DATA3;
	reg [7:0] DATA4;


	wire [7:0] SEGMENT;
	wire [3:0] DIG;


	Segment7 uut (
		.CLK(CLK), 
		.DATA1(DATA1), 
		.DATA2(DATA2), 
		.DATA3(DATA3), 
		.DATA4(DATA4), 
		.SEGMENT(SEGMENT), 
		.DIG(DIG)
	);

	initial begin

		CLK = 0;
		DATA1 = 0;
		DATA2 = 0;
		DATA3 = 0;
		DATA4 = 0;


		#100;
        

		DATA1 = "1";
		DATA1 = "2";
		DATA1 = "3";
		DATA1 = "4";

	end
      
endmodule