data/full_repos/permissive/210844779/lab4/4.1.1/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.1.1/tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.1.1/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.1.1/tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.1.1/tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.1.1/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: data/full_repos/permissive/210844779/lab4/4.1.1/tb.v:7: Cannot find file containing module: \'mela_non\'\n  mela_non mo(ip,clk,g_rst,set,op);\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab4/4.1.1,data/full_repos/permissive/210844779/mela_non\n             data/full_repos/permissive/210844779/lab4/4.1.1,data/full_repos/permissive/210844779/mela_non.v\n             data/full_repos/permissive/210844779/lab4/4.1.1,data/full_repos/permissive/210844779/mela_non.sv\n             mela_non\n             mela_non.v\n             mela_non.sv\n             obj_dir/mela_non\n             obj_dir/mela_non.v\n             obj_dir/mela_non.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab4/4.1.1/tb.v:26: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\n    ip=$random;\n      ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
   parameter m=5;

  reg ip,clk,g_rst,set;
  wire op;
 
  mela_non mo(ip,clk,g_rst,set,op);
  always
  begin
    clk=1;
    #5
    clk=0;
    #5;
  end
  
  initial
  begin
    g_rst=1;set=0;
    #10
    g_rst=0;set=0;
    #10;
  end
  
  always
  begin  
    ip=$random;
    #10;
  end
  
endmodule
module tb();

   parameter m=5;

  reg ip,clk,g_rst,set;
  wire op;
 
  mela_non mo(ip,clk,g_rst,set,op);
  always
  begin
    clk=1;
    #5
    clk=0;
    #5;
  end
  
  initial
  begin
    g_rst=1;set=0;
    #10
    g_rst=0;set=0;
    #10;
  end
  
  always
  begin  
    ip=$random;
    #10;
  end
  
endmodule