data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v
 line:18: before: "reg"
1: b'%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #5 C = !C;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #2 CLR = CLEAR_VAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #2 CLR = ~CLEAR_VAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #57 CLR = CLEAR_VAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #2  CLR = ~CLEAR_VAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #42 CLR = CLEAR_VAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #2  CLR = ~CLEAR_VAL;\n        ^\n%Error: data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation/reg_testbench.v:25: Cannot find file containing module: \'register\'\n    register #(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation,data/full_repos/permissive/110143902/register\n             data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation,data/full_repos/permissive/110143902/register.v\n             data/full_repos/permissive/110143902/projects/reg_async_reset/src/simulation,data/full_repos/permissive/110143902/register.sv\n             register\n             register.v\n             register.sv\n             obj_dir/register\n             obj_dir/register.v\n             obj_dir/register.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_testbench (  );

    parameter                          DATA_WIDTH = 4;
    parameter reg [DATA_WIDTH - 1 : 0] INIT_VAL   = 0;
    parameter                          CLEAR_VAL  = 1;

    reg [DATA_WIDTH - 1 : 0] D;
    reg C, CLR;
    wire [DATA_WIDTH - 1 : 0] Q;

    register #(
        .DATA_WIDTH(DATA_WIDTH),
        .INIT_VAL(INIT_VAL),
        .CLEAR_VAL(CLEAR_VAL)
    ) register_i (
        .D(D),
        .C(C),
        .CLR(CLR),
        .Q(Q)
    );


    always
        #5 C = !C;


    always @(posedge C)
        D <= D + 1;


    initial begin
        D   = INIT_VAL;
        C   = 0;
        CLR = ~CLEAR_VAL;

        #2 CLR = CLEAR_VAL;
        #2 CLR = ~CLEAR_VAL;

        #57 CLR = CLEAR_VAL;
        #2  CLR = ~CLEAR_VAL;

        #42 CLR = CLEAR_VAL;
        #2  CLR = ~CLEAR_VAL;
    end

endmodule
module register_testbench (  );


    parameter                          DATA_WIDTH = 4;
    parameter reg [DATA_WIDTH - 1 : 0] INIT_VAL   = 0;
    parameter                          CLEAR_VAL  = 1;

    reg [DATA_WIDTH - 1 : 0] D;
    reg C, CLR;
    wire [DATA_WIDTH - 1 : 0] Q;

    register #(
        .DATA_WIDTH(DATA_WIDTH),
        .INIT_VAL(INIT_VAL),
        .CLEAR_VAL(CLEAR_VAL)
    ) register_i (
        .D(D),
        .C(C),
        .CLR(CLR),
        .Q(Q)
    );


    always
        #5 C = !C;


    always @(posedge C)
        D <= D + 1;


    initial begin
        D   = INIT_VAL;
        C   = 0;
        CLR = ~CLEAR_VAL;

        #2 CLR = CLEAR_VAL;
        #2 CLR = ~CLEAR_VAL;

        #57 CLR = CLEAR_VAL;
        #2  CLR = ~CLEAR_VAL;

        #42 CLR = CLEAR_VAL;
        #2  CLR = ~CLEAR_VAL;
    end

endmodule