data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #60;\n  ^\n%Error: data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v:64: syntax error, unexpected \'@\'\n        @ (negedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v:65: Unsupported: Ignoring delay on this delayed statement.\n        # 2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #220;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/157667710/benchmark/AES-T900/AES-T900/src/TjIn/tbTOP.v:80: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tbTOP;


	reg clk;
	reg rst;
	reg [127:0] state;
	reg [127:0] key;


	wire [127:0] out;
	wire [63:0] Capacitance;


	top uut (
		.clk(clk), 
		.rst(rst), 
		.state(state), 
		.key(key), 
		.out(out), 
		.Capacitance(Capacitance)
	);

	initial begin		clk = 0;
		state = 0;
		key = 0;
		rst = 0;
		
		#20;
		rst = 1;

		#20;
		rst = 0;
		
		#60;

        @ (negedge clk);
        # 2;
        state = 128'h3243f6a8_885a308d_313198a2_e0370734;
        key   = 128'h2b7e1516_28aed2a6_abf71588_09cf4f3c;
        #10;
        state = 128'h00112233_44556677_8899aabb_ccddeeff;
        #10;
        state = 128'h0;
        #10;
        state = 128'h0;
        #10;
        state = 128'h1;
        #220;
        $finish;
	end
      
    always #5 clk = ~clk;
      
endmodule
module tbTOP;



	reg clk;
	reg rst;
	reg [127:0] state;
	reg [127:0] key;


	wire [127:0] out;
	wire [63:0] Capacitance;


	top uut (
		.clk(clk), 
		.rst(rst), 
		.state(state), 
		.key(key), 
		.out(out), 
		.Capacitance(Capacitance)
	);

	initial begin		clk = 0;
		state = 0;
		key = 0;
		rst = 0;
		
		#20;
		rst = 1;

		#20;
		rst = 0;
		
		#60;

        @ (negedge clk);
        # 2;
        state = 128'h3243f6a8_885a308d_313198a2_e0370734;
        key   = 128'h2b7e1516_28aed2a6_abf71588_09cf4f3c;
        #10;
        state = 128'h00112233_44556677_8899aabb_ccddeeff;
        #10;
        state = 128'h0;
        #10;
        state = 128'h0;
        #10;
        state = 128'h1;
        #220;
        $finish;
	end
      
    always #5 clk = ~clk;
      
endmodule