data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:106: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'dsi_byte_reverse\'\nmodule dsi_byte_reverse\n       ^~~~~~~~~~~~~~~~\n                                                                                         : ... Top module \'dsi_packer\'\nmodule dsi_packer\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:100: Operator SHIFTL expects 80 bits on the LHS, but LHS\'s VARREF \'d_i\' generates 24 bits.\n                                                                                      : ... In instance dsi_packer.U_Shifter\n        assign gen_array[i] = d_i << (i * 8);\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:103: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                      : ... In instance dsi_packer.U_Shifter\n   assign shifted_o = gen_array[shift_i];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:75: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s ARRAYSEL generates 24 bits.\n                                                                                     : ... In instance dsi_packer.U_RevIn\n   assign q_o = (size_i) <= g_num_bytes ? swapped[size_i] : \'hx;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:75: Operator ASSIGNW expects 24 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                     : ... In instance dsi_packer.U_RevIn\n   assign q_o = (size_i) <= g_num_bytes ? swapped[size_i] : \'hx;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:160: Operator GTE expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n   assign shift_out = (count >= q_size_i && q_req_i);\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:161: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n   assign in_shift = (shift_out ? count - q_size_i : count);\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:164: Input port connection \'size_i\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'d_size_i\' generates 4 bits.\n                                                                                      : ... In instance dsi_packer\n   dsi_byte_swapper #(g_input_bytes) U_RevIn ( d_i, d_size_i, d_in );\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:182: Input port connection \'shift_i\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'in_shift\' generates 5 bits.\n                                                                                      : ... In instance dsi_packer\n      .shift_i(in_shift),\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:183: Output port connection \'shifted_o\' expects 80 bits on the pin connection, but pin connection\'s VARREF \'in_shifted\' generates 64 bits.\n                                                                                      : ... In instance dsi_packer\n      .shifted_o(in_shifted)\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:198: Operator GT expects 32 bits on the LHS, but LHS\'s VARREF \'count\' generates 5 bits.\n                                                                                      : ... In instance dsi_packer\n            q_valid_o[i] <= count > i;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:221: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n             count <= count - q_size_i + d_size_i;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:227: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n             count <= count - q_size_i;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:238: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n       avail_next <= avail + q_size_i - d_size_i;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:242: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n       avail_next <= avail + q_size_i;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:249: Operator SUB expects 32 or 5 bits on the RHS, but RHS\'s VARREF \'q_size_i\' generates 3 bits.\n                                                                                      : ... In instance dsi_packer\n   assign d_req_int = (avail_next >= g_input_bytes) || (shift_out && avail_next >= (g_input_bytes - q_size_i));\n                                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/rtl/dsi_core/dsi_packer.v:251: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'count\' generates 5 bits.\n                                                                                      : ... In instance dsi_packer\n   assign d_empty_o = !count;\n                      ^\n%Error: Exiting due to 17 warning(s)\n'
module dsi_byte_reverse
  (
   d_i,
   q_o);
   parameter g_num_bytes = 4;

   input [g_num_bytes * 8 - 1 : 0] d_i;
   output [g_num_bytes * 8 - 1 : 0] q_o;

   generate 
      genvar                        i, j;
      for(i=0;i<8;i=i+1)
        for(j=0;j<g_num_bytes;j=j+1)
          assign q_o[8 * (g_num_bytes-1-j) + i] = d_i[8 * j + i];
   endgenerate
   
endmodule
module dsi_byte_reverse
  (
   d_i,
   q_o);

   parameter g_num_bytes = 4;

   input [g_num_bytes * 8 - 1 : 0] d_i;
   output [g_num_bytes * 8 - 1 : 0] q_o;

   generate 
      genvar                        i, j;
      for(i=0;i<8;i=i+1)
        for(j=0;j<g_num_bytes;j=j+1)
          assign q_o[8 * (g_num_bytes-1-j) + i] = d_i[8 * j + i];
   endgenerate
   
endmodule