data/full_repos/permissive/162533945/skeleton.v
None: at end of input
1: b"%Error: data/full_repos/permissive/162533945/skeleton.v:20: Cannot find file containing module: 'imem'\n    imem my_imem(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/imem\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/imem.v\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/imem.sv\n             imem\n             imem.v\n             imem.sv\n             obj_dir/imem\n             obj_dir/imem.v\n             obj_dir/imem.sv\n%Error: data/full_repos/permissive/162533945/skeleton.v:33: Cannot find file containing module: 'dmem'\n    dmem my_dmem(\n    ^~~~\n%Error: data/full_repos/permissive/162533945/skeleton.v:47: Cannot find file containing module: 'regfile'\n    regfile my_regfile(\n    ^~~~~~~\n%Error: data/full_repos/permissive/162533945/skeleton.v:60: Cannot find file containing module: 'processor'\n    processor my_processor(\n    ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module skeleton(clock, reset);
    input clock, reset;




    wire [11:0] address_imem;
    wire [31:0] q_imem;
    imem my_imem(
        .address    (address_imem),
        .clock      (~clock),
        .q          (q_imem)
    );




    wire [11:0] address_dmem;
    wire [31:0] data;
    wire wren;
    wire [31:0] q_dmem;
    dmem my_dmem(
        .address    (address_dmem),
        .clock      (~clock),
        .data	    (data),
        .wren	    (wren),
        .q          (q_dmem)
    );



    wire ctrl_writeEnable;
    wire [4:0] ctrl_writeReg, ctrl_readRegA, ctrl_readRegB;
    wire [31:0] data_writeReg;
    wire [31:0] data_readRegA, data_readRegB;
    regfile my_regfile(
        clock,
        ctrl_writeEnable,
        ctrl_reset,
        ctrl_writeReg,
        ctrl_readRegA,
        ctrl_readRegB,
        data_writeReg,
        data_readRegA,
        data_readRegB
    );


    processor my_processor(

        clock,
        reset,


        address_imem,
        q_imem,


        address_dmem,
        data,
        wren,
        q_dmem,


        ctrl_writeEnable,
        ctrl_writeReg,
        ctrl_readRegA,
        ctrl_readRegB,
        data_writeReg,
        data_readRegA,
        data_readRegB
		  
    );

endmodule
module skeleton(clock, reset);

    input clock, reset;




    wire [11:0] address_imem;
    wire [31:0] q_imem;
    imem my_imem(
        .address    (address_imem),
        .clock      (~clock),
        .q          (q_imem)
    );




    wire [11:0] address_dmem;
    wire [31:0] data;
    wire wren;
    wire [31:0] q_dmem;
    dmem my_dmem(
        .address    (address_dmem),
        .clock      (~clock),
        .data	    (data),
        .wren	    (wren),
        .q          (q_dmem)
    );



    wire ctrl_writeEnable;
    wire [4:0] ctrl_writeReg, ctrl_readRegA, ctrl_readRegB;
    wire [31:0] data_writeReg;
    wire [31:0] data_readRegA, data_readRegB;
    regfile my_regfile(
        clock,
        ctrl_writeEnable,
        ctrl_reset,
        ctrl_writeReg,
        ctrl_readRegA,
        ctrl_readRegB,
        data_writeReg,
        data_readRegA,
        data_readRegB
    );


    processor my_processor(

        clock,
        reset,


        address_imem,
        q_imem,


        address_dmem,
        data,
        wren,
        q_dmem,


        ctrl_writeEnable,
        ctrl_writeReg,
        ctrl_readRegA,
        ctrl_readRegB,
        data_writeReg,
        data_readRegA,
        data_readRegB
		  
    );

endmodule