data/full_repos/permissive/217060808/bsg_async/bsg_async_ptr_gray/bsg_async_ptr_gray_lg_size_p_5_use_negedge_for_launch_p_0_use_async_reset_p_0/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_ptr_gray/bsg_async_ptr_gray_lg_size_p_5_use_negedge_for_launch_p_0_use_async_reset_p_0/top.v:58: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                        : ... In instance top.wrapper.ptr_sync.sync_p_z_blss\n                                  (N1)? iclk_data_i : 1\'b0;\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_ptr_gray/bsg_async_ptr_gray_lg_size_p_5_use_negedge_for_launch_p_0_use_async_reset_p_0/top.v:151: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                         : ... In instance top.wrapper\n                        (N1)? w_ptr_gray_r_o : 1\'b0;\n                            ^\n%Error: Exiting due to 2 warning(s)\n'
module top
(
  w_clk_i,
  w_reset_i,
  w_inc_i,
  r_clk_i,
  w_ptr_binary_r_o,
  w_ptr_gray_r_o,
  w_ptr_gray_r_rsync_o
);

  output [4:0] w_ptr_binary_r_o;
  output [4:0] w_ptr_gray_r_o;
  output [4:0] w_ptr_gray_r_rsync_o;
  input w_clk_i;
  input w_reset_i;
  input w_inc_i;
  input r_clk_i;

  bsg_async_ptr_gray
  wrapper
  (
    .w_ptr_binary_r_o(w_ptr_binary_r_o),
    .w_ptr_gray_r_o(w_ptr_gray_r_o),
    .w_ptr_gray_r_rsync_o(w_ptr_gray_r_rsync_o),
    .w_clk_i(w_clk_i),
    .w_reset_i(w_reset_i),
    .w_inc_i(w_inc_i),
    .r_clk_i(r_clk_i)
  );


endmodule
module top
(
  w_clk_i,
  w_reset_i,
  w_inc_i,
  r_clk_i,
  w_ptr_binary_r_o,
  w_ptr_gray_r_o,
  w_ptr_gray_r_rsync_o
);


  output [4:0] w_ptr_binary_r_o;
  output [4:0] w_ptr_gray_r_o;
  output [4:0] w_ptr_gray_r_rsync_o;
  input w_clk_i;
  input w_reset_i;
  input w_inc_i;
  input r_clk_i;

  bsg_async_ptr_gray
  wrapper
  (
    .w_ptr_binary_r_o(w_ptr_binary_r_o),
    .w_ptr_gray_r_o(w_ptr_gray_r_o),
    .w_ptr_gray_r_rsync_o(w_ptr_gray_r_rsync_o),
    .w_clk_i(w_clk_i),
    .w_reset_i(w_reset_i),
    .w_inc_i(w_inc_i),
    .r_clk_i(r_clk_i)
  );


endmodule