data/full_repos/permissive/158922207/Verilog Design/modules/ForwardingUnit.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/ForwardingUnit.v\n%Error: Exiting due to 3 error(s)\n'
module ForwardingUnit_EX(ForwardA, ForwardB,ID_EX_rs, ID_EX_rt, EX_MEM_rd, MEM_WB_rd,EX_MEM_RegWrite, MEM_WB_RegWrite);
input EX_MEM_RegWrite, MEM_WB_RegWrite;
input [4:0] ID_EX_rs, ID_EX_rt, EX_MEM_rd, MEM_WB_rd;
output [1:0] ForwardA, ForwardB;

reg[1:0] conditionA, conditionB;

always @(*) begin
conditionA = 2'b00;
conditionB = 2'b00;

if ((EX_MEM_RegWrite && EX_MEM_rd != 5'd0) && (EX_MEM_rd == ID_EX_rs))
	conditionA = 2'b10;
else if ((MEM_WB_RegWrite && MEM_WB_rd != 5'd0) && ((MEM_WB_rd == ID_EX_rs)))
	conditionA = 2'b01;
	
if ((EX_MEM_RegWrite && EX_MEM_rd != 5'd0) && (EX_MEM_rd == ID_EX_rt))
	conditionB = 2'b10;
else if ((MEM_WB_RegWrite && MEM_WB_rd != 5'd0) && (MEM_WB_rd == ID_EX_rt))
	conditionB = 2'b01;
end

assign ForwardA = conditionA;
assign ForwardB = conditionB;
endmodule
module ForwardingUnit_EX(ForwardA, ForwardB,ID_EX_rs, ID_EX_rt, EX_MEM_rd, MEM_WB_rd,EX_MEM_RegWrite, MEM_WB_RegWrite);

input EX_MEM_RegWrite, MEM_WB_RegWrite;
input [4:0] ID_EX_rs, ID_EX_rt, EX_MEM_rd, MEM_WB_rd;
output [1:0] ForwardA, ForwardB;

reg[1:0] conditionA, conditionB;

always @(*) begin
conditionA = 2'b00;
conditionB = 2'b00;

if ((EX_MEM_RegWrite && EX_MEM_rd != 5'd0) && (EX_MEM_rd == ID_EX_rs))
	conditionA = 2'b10;
else if ((MEM_WB_RegWrite && MEM_WB_rd != 5'd0) && ((MEM_WB_rd == ID_EX_rs)))
	conditionA = 2'b01;
	
if ((EX_MEM_RegWrite && EX_MEM_rd != 5'd0) && (EX_MEM_rd == ID_EX_rt))
	conditionB = 2'b10;
else if ((MEM_WB_RegWrite && MEM_WB_rd != 5'd0) && (MEM_WB_rd == ID_EX_rt))
	conditionB = 2'b01;
end

assign ForwardA = conditionA;
assign ForwardB = conditionB;
endmodule