data/full_repos/permissive/19591557/modules/aer_interface/spio_spinn2aer_mapper.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19591557/modules/aer_interface/spio_spinn2aer_mapper.v:24: Cannot find include file: ../../modules/spinnaker_link/spio_spinnaker_link.h\n`include "../../modules/spinnaker_link/spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/modules/aer_interface,data/full_repos/permissive/19591557/../../modules/spinnaker_link/spio_spinnaker_link.h\n             data/full_repos/permissive/19591557/modules/aer_interface,data/full_repos/permissive/19591557/../../modules/spinnaker_link/spio_spinnaker_link.h.v\n             data/full_repos/permissive/19591557/modules/aer_interface,data/full_repos/permissive/19591557/../../modules/spinnaker_link/spio_spinnaker_link.h.sv\n             ../../modules/spinnaker_link/spio_spinnaker_link.h\n             ../../modules/spinnaker_link/spio_spinnaker_link.h.v\n             ../../modules/spinnaker_link/spio_spinnaker_link.h.sv\n             obj_dir/../../modules/spinnaker_link/spio_spinnaker_link.h\n             obj_dir/../../modules/spinnaker_link/spio_spinnaker_link.h.v\n             obj_dir/../../modules/spinnaker_link/spio_spinnaker_link.h.sv\n%Error: data/full_repos/permissive/19591557/modules/aer_interface/spio_spinn2aer_mapper.v:34: Define or directive not defined: \'`PKT_BITS\'\n  input  wire [`PKT_BITS - 1:0] opkt_data,\n               ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module spio_spinn2aer_mapper
(
  input wire                    rst,
  input wire                    clk,


  input  wire [`PKT_BITS - 1:0] opkt_data,
  input  wire                   opkt_vld,
  output reg                    opkt_rdy,


  output reg             [15:0] oaer_data,
  output reg                    oaer_req,
  input  wire                   oaer_ack
);




  localparam OSTATE_BITS = 2;
  localparam IDLE_OST    = 0;
  localparam HS11_OST    = IDLE_OST + 1;
  localparam HS10_OST    = HS11_OST + 1;





  reg [OSTATE_BITS - 1:0] ostate;





  always @(posedge clk or posedge rst)
    if (rst)
      opkt_rdy <= 1'b1;
    else
      case (ostate)
        IDLE_OST:
          if (opkt_vld)
            opkt_rdy <= 1'b0;
          else
            opkt_rdy <= 1'b1;
	
        HS10_OST:
          if (oaer_ack)
            opkt_rdy <= 1'b1;
          else
            opkt_rdy <= 1'b0;
	
	default:  
            opkt_rdy <= opkt_rdy;
      endcase





  always @(posedge clk or posedge rst)
    if (rst)
      oaer_data <= 16'd0;
    else
      case (ostate)
        IDLE_OST:
          if (opkt_vld)
            oaer_data <= opkt_data[23:8];
          else
            oaer_data <= oaer_data;
	
	default:  
            oaer_data <= oaer_data;
      endcase


  always @(posedge clk or posedge rst)
    if (rst)
      oaer_req <= 1'b1;
    else
      case (ostate)
        IDLE_OST:
          if (opkt_vld)
            oaer_req <= 1'b0;
          else
            oaer_req <= 1'b1;
	
        HS11_OST:
          if (!oaer_ack)
            oaer_req <= 1'b1;
          else
            oaer_req <= 1'b0;
	
	default:  
            oaer_req <= oaer_req;
      endcase





  always @(posedge clk or posedge rst)
    if (rst)
      ostate <= IDLE_OST;
    else
      case (ostate)
        IDLE_OST:
          if (opkt_vld)
            ostate <= HS11_OST;
          else
            ostate <= IDLE_OST;

	HS11_OST:
          if (!oaer_ack)
            ostate <= HS10_OST;
	  else
            ostate <= HS11_OST;

	HS10_OST:
          if (oaer_ack)
            ostate <= IDLE_OST;
	  else
            ostate <= HS10_OST;

	default:  
            ostate <= ostate;
      endcase
endmodule
module spio_spinn2aer_mapper
(
  input wire                    rst,
  input wire                    clk,


  input  wire [`PKT_BITS - 1:0] opkt_data,
  input  wire                   opkt_vld,
  output reg                    opkt_rdy,


  output reg             [15:0] oaer_data,
  output reg                    oaer_req,
  input  wire                   oaer_ack
);





  localparam OSTATE_BITS = 2;
  localparam IDLE_OST    = 0;
  localparam HS11_OST    = IDLE_OST + 1;
  localparam HS10_OST    = HS11_OST + 1;





  reg [OSTATE_BITS - 1:0] ostate;





  always @(posedge clk or posedge rst)
    if (rst)
      opkt_rdy <= 1'b1;
    else
      case (ostate)
        IDLE_OST:
          if (opkt_vld)
            opkt_rdy <= 1'b0;
          else
            opkt_rdy <= 1'b1;
	
        HS10_OST:
          if (oaer_ack)
            opkt_rdy <= 1'b1;
          else
            opkt_rdy <= 1'b0;
	
	default:  
            opkt_rdy <= opkt_rdy;
      endcase





  always @(posedge clk or posedge rst)
    if (rst)
      oaer_data <= 16'd0;
    else
      case (ostate)
        IDLE_OST:
          if (opkt_vld)
            oaer_data <= opkt_data[23:8];
          else
            oaer_data <= oaer_data;
	
	default:  
            oaer_data <= oaer_data;
      endcase


  always @(posedge clk or posedge rst)
    if (rst)
      oaer_req <= 1'b1;
    else
      case (ostate)
        IDLE_OST:
          if (opkt_vld)
            oaer_req <= 1'b0;
          else
            oaer_req <= 1'b1;
	
        HS11_OST:
          if (!oaer_ack)
            oaer_req <= 1'b1;
          else
            oaer_req <= 1'b0;
	
	default:  
            oaer_req <= oaer_req;
      endcase





  always @(posedge clk or posedge rst)
    if (rst)
      ostate <= IDLE_OST;
    else
      case (ostate)
        IDLE_OST:
          if (opkt_vld)
            ostate <= HS11_OST;
          else
            ostate <= IDLE_OST;

	HS11_OST:
          if (!oaer_ack)
            ostate <= HS10_OST;
	  else
            ostate <= HS11_OST;

	HS10_OST:
          if (oaer_ack)
            ostate <= IDLE_OST;
	  else
            ostate <= HS10_OST;

	default:  
            ostate <= ostate;
      endcase
endmodule