data/full_repos/permissive/119715647/sim/Utilities/ButtonShaper_tb.v
 line:25: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Utilities/ButtonShaper_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/119715647/sim/Utilities/ButtonShaper_tb.v:20: Unsupported or unknown PLI call: $monitor\n  $monitor("time:[%0t], input:[%b], output:[%b]",\n  ^~~~~~~~\n%Error: data/full_repos/permissive/119715647/sim/Utilities/ButtonShaper_tb.v:25: syntax error, unexpected \'@\'\n  @(posedge clk) #10 _input = 3\'b111;\n  ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ButtonShaper_tb(); 
	reg [0:0] clk, rst; 
	reg [2:0] _input; 
	wire[2:0] _output;

	ButtonShaper b1(clk, _input[0], _output[0]), 
				 b2(clk, _input[1], _output[1]),
				 b3(clk, _input[2], _output[2]);

	always begin
		#10 clk = ~clk; 
	end 

	initial begin
		$monitor("time:[%0t], input:[%b], output:[%b]",
			$time, 
			_input, 
			_output); 
		clk = 1; rst = 1; 
		@(posedge clk) #10 _input = 3'b111;
		@(posedge clk) #10 _input = 3'b000; 
		@(posedge clk) #30 _input = 3'b111;  
		@(posedge clk) #10 _input = 3'b010; 
		@(posedge clk) #30 _input = 3'b111; 
	end
endmodule
module ButtonShaper_tb();
 
	reg [0:0] clk, rst; 
	reg [2:0] _input; 
	wire[2:0] _output;

	ButtonShaper b1(clk, _input[0], _output[0]), 
				 b2(clk, _input[1], _output[1]),
				 b3(clk, _input[2], _output[2]);

	always begin
		#10 clk = ~clk; 
	end 

	initial begin
		$monitor("time:[%0t], input:[%b], output:[%b]",
			$time, 
			_input, 
			_output); 
		clk = 1; rst = 1; 
		@(posedge clk) #10 _input = 3'b111;
		@(posedge clk) #10 _input = 3'b000; 
		@(posedge clk) #30 _input = 3'b111;  
		@(posedge clk) #10 _input = 3'b010; 
		@(posedge clk) #30 _input = 3'b111; 
	end
endmodule