data/full_repos/permissive/128100618/SV/FP_operations_design.v
 line:6: before: "("
1: b'%Warning-MULTITOP: data/full_repos/permissive/128100618/SV/FP_operations_design.v:280: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'DE2_Top\'\nmodule DE2_Top (\n       ^~~~~~~\n                                                                                     : ... Top module \'fpneg\'\nmodule fpneg(fout, f1) ;\n       ^~~~~\n                                                                                     : ... Top module \'int2fp\'\nmodule int2fp(fp_out, int_in, scale_in) ;\n       ^~~~~~\n                                                                                     : ... Top module \'fp2int\'\nmodule fp2int(int_out, fp_in, scale_in) ;\n       ^~~~~~\n                                                                                     : ... Top module \'fpinv\'\nmodule fpinv (fout, f1);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FP_operations_design.v:263: Input port connection \'num\' expects 4 bits on the pin connection, but pin connection\'s SEL generates 1 bits.\n                                                                                  : ... In instance DE2_Top\n HexDigit d2(HEX2, disp[8]);\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FP_operations_design.v:619: Operator SHIFTR expects 10 bits on the LHS, but LHS\'s VARREF \'m_in\' generates 9 bits.\n                                                                                  : ... In instance fp2int\n assign abs_int = (e_in>8\'h80)? (m_in >> (8\'h89 - e_in)) : 10\'d0 ;\n                                      ^~\n%Error: Exiting due to 3 warning(s)\n'
module HexDigit(segs, num);
	input [3:0] num	;
	output [6:0] segs ;
	reg [6:0] segs ;
	always @ (num)
	begin
		case (num)
				4'h0: segs = 7'b1000000;
				4'h1: segs = 7'b1111001;
				4'h2: segs = 7'b0100100;
				4'h3: segs = 7'b0110000;
				4'h4: segs = 7'b0011001;
				4'h5: segs = 7'b0010010;
				4'h6: segs = 7'b0000010;
				4'h7: segs = 7'b1111000;
				4'h8: segs = 7'b0000000;
				4'h9: segs = 7'b0010000;
				4'ha: segs = 7'b0001000;
				4'hb: segs = 7'b0000011;
				4'hc: segs = 7'b1000110;
				4'hd: segs = 7'b0100001;
				4'he: segs = 7'b0000110;
				4'hf: segs = 7'b0001110;
				default segs = 7'b1111111;
		endcase
	end
endmodule
module HexDigit(segs, num);

	input [3:0] num	;
	output [6:0] segs ;
	reg [6:0] segs ;
	always @ (num)
	begin
		case (num)
				4'h0: segs = 7'b1000000;
				4'h1: segs = 7'b1111001;
				4'h2: segs = 7'b0100100;
				4'h3: segs = 7'b0110000;
				4'h4: segs = 7'b0011001;
				4'h5: segs = 7'b0010010;
				4'h6: segs = 7'b0000010;
				4'h7: segs = 7'b1111000;
				4'h8: segs = 7'b0000000;
				4'h9: segs = 7'b0010000;
				4'ha: segs = 7'b0001000;
				4'hb: segs = 7'b0000011;
				4'hc: segs = 7'b1000110;
				4'hd: segs = 7'b0100001;
				4'he: segs = 7'b0000110;
				4'hf: segs = 7'b0001110;
				default segs = 7'b1111111;
		endcase
	end
endmodule