data/full_repos/permissive/127311496/src/v/Infrastructure/VGADevice.v
1: b'%Warning-WIDTH: data/full_repos/permissive/127311496/src/v/Infrastructure/VGADevice.v:37: Operator ADD expects 32 or 19 bits on the RHS, but RHS\'s SEL generates 10 bits.\n                                                                                        : ... In instance VGADevice\n  assign addra = addrBus_reg[18:10] * 640 + addrBus_reg[9:0];\n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/127311496/src/v/Infrastructure/VGADevice.v:38: Operator ADD expects 32 or 19 bits on the RHS, but RHS\'s VARREF \'HCoord\' generates 10 bits.\n                                                                                        : ... In instance VGADevice\n  assign addrb = VCoord * 640 + HCoord;\n                              ^\n%Error: data/full_repos/permissive/127311496/src/v/Infrastructure/VGADevice.v:39: Cannot find file containing module: \'GraphicVRAM\'\n  GraphicVRAM RAM0 (.clka(clkMem), .ena(ena_reg[1]), .wea(wea_reg[1]), .addra(addra_reg),\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/v/Infrastructure,data/full_repos/permissive/127311496/GraphicVRAM\n             data/full_repos/permissive/127311496/src/v/Infrastructure,data/full_repos/permissive/127311496/GraphicVRAM.v\n             data/full_repos/permissive/127311496/src/v/Infrastructure,data/full_repos/permissive/127311496/GraphicVRAM.sv\n             GraphicVRAM\n             GraphicVRAM.v\n             GraphicVRAM.sv\n             obj_dir/GraphicVRAM\n             obj_dir/GraphicVRAM.v\n             obj_dir/GraphicVRAM.sv\n%Error: data/full_repos/permissive/127311496/src/v/Infrastructure/VGADevice.v:68: Cannot find file containing module: \'CharVRAM\'\n CharVRAM RAM1(.clka(clkMem), .ena(en_Char), .wea(weBus), .addra(addrBus[13:2]),\n ^~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Infrastructure/VGADevice.v:71: Cannot find file containing module: \'CharROM\'\n CharROM ROM0(.clk(clkVGA), .ascii(chData[7:0]), .x(HCoord_reg), .y(VCoord[3:0]), .dot(charDot));\n ^~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Infrastructure/VGADevice.v:74: Cannot find file containing module: \'VGAScan\'\n VGAScan #(.HCALIBRATE(0), .VCALIBRATE(0)) U0(\n ^~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module VGADevice #(
	parameter GRAPHIC_VRAM = 1
)(
	input clkVGA, input clkMem,

	input [31:0] ctrl0, input [31:0] ctrl1,

	input [31:0] addrBus, input [31:0] dataInBus, input [3:0] weBus,

	input en_Graphic,

	input en_Char, output [31:0] dataOut_Char,

	output [9:0] HCoord, output [8:0] VCoord, output frameStart,

	output [11:0] videoOut, output HSync, output VSync
);
	

	wire [11:0] colorG;
	generate
	if(GRAPHIC_VRAM != 0)
	begin: GRAPHIC_VRAM_EXIST
		reg [18:0] addrBus_reg, addra_reg;
		reg [1:0] ena_reg, wea_reg;
		wire [18:0] addra, addrb;
		reg [11:0] dina_reg0, dina_reg1;
	
		assign addra = addrBus_reg[18:10] * 640 + addrBus_reg[9:0];
		assign addrb = VCoord * 640 + HCoord;
		GraphicVRAM RAM0 (.clka(clkMem), .ena(ena_reg[1]), .wea(wea_reg[1]), .addra(addra_reg),
			.dina(dina_reg1), .clkb(clkVGA), .addrb(addrb), .doutb(colorG));
	
		always @ (posedge clkMem)
		begin
			dina_reg0 <= dataInBus[11:0];
			addrBus_reg <= addrBus[20:2];
			wea_reg[0] <= &weBus;
			ena_reg[0] <= en_Graphic;
			
			dina_reg1 <= dina_reg0;
			addra_reg <= addra;
			wea_reg[1] <= wea_reg[0];
			ena_reg[1] <= ena_reg[0];
		end
	end
	else
	begin: GRAPHIC_VRAM_NOTEXIST
		assign colorG = 12'h0;
	end
	endgenerate
	

	wire [31:0] chData;
	reg [11:0] colorC_F, colorC_B;
	reg [2:0] HCoord_reg;
	wire charDot;
	wire inCursor;
	
	CharVRAM RAM1(.clka(clkMem), .ena(en_Char), .wea(weBus), .addra(addrBus[13:2]),
		.dina(dataInBus), .douta(dataOut_Char), .clkb(clkVGA),
		.addrb({VCoord[8:4], HCoord[9:3]}), .doutb(chData));
	CharROM ROM0(.clk(clkVGA), .ascii(chData[7:0]), .x(HCoord_reg), .y(VCoord[3:0]), .dot(charDot));

	reg [11:0] colorMixed;
	VGAScan #(.HCALIBRATE(0), .VCALIBRATE(0)) U0(
		.clk(clkVGA), .HAddr(HCoord), .VAddr(VCoord), .HSync(HSync), .VSync(VSync),
		.videoIn(colorMixed), .frameStart(frameStart), .videoOut(videoOut));
	
	always @ (posedge clkVGA)
	begin
		HCoord_reg <= HCoord[2:0];
		if(inCursor)
		begin
			colorC_F <= chData[31:20];
			colorC_B <= chData[19:8];
		end
		else
		begin
			colorC_F <= chData[19:8];
			colorC_B <= chData[31:20];
		end
	end
	
	always @*
	begin
		if(charDot)
			colorMixed <= colorC_F;
		else if((colorC_B == 12'h0) & ctrl1[0])
			colorMixed <= colorG;
		else
			colorMixed <= colorC_B;
		
	end
	
	vgaCursorGen cursor(.clk(clkVGA), .ctrl(ctrl0), .HCoord(HCoord), .VCoord(VCoord), .en(inCursor));

endmodule
module VGADevice #(
	parameter GRAPHIC_VRAM = 1
)(
	input clkVGA, input clkMem,

	input [31:0] ctrl0, input [31:0] ctrl1,

	input [31:0] addrBus, input [31:0] dataInBus, input [3:0] weBus,

	input en_Graphic,

	input en_Char, output [31:0] dataOut_Char,

	output [9:0] HCoord, output [8:0] VCoord, output frameStart,

	output [11:0] videoOut, output HSync, output VSync
);

	

	wire [11:0] colorG;
	generate
	if(GRAPHIC_VRAM != 0)
	begin: GRAPHIC_VRAM_EXIST
		reg [18:0] addrBus_reg, addra_reg;
		reg [1:0] ena_reg, wea_reg;
		wire [18:0] addra, addrb;
		reg [11:0] dina_reg0, dina_reg1;
	
		assign addra = addrBus_reg[18:10] * 640 + addrBus_reg[9:0];
		assign addrb = VCoord * 640 + HCoord;
		GraphicVRAM RAM0 (.clka(clkMem), .ena(ena_reg[1]), .wea(wea_reg[1]), .addra(addra_reg),
			.dina(dina_reg1), .clkb(clkVGA), .addrb(addrb), .doutb(colorG));
	
		always @ (posedge clkMem)
		begin
			dina_reg0 <= dataInBus[11:0];
			addrBus_reg <= addrBus[20:2];
			wea_reg[0] <= &weBus;
			ena_reg[0] <= en_Graphic;
			
			dina_reg1 <= dina_reg0;
			addra_reg <= addra;
			wea_reg[1] <= wea_reg[0];
			ena_reg[1] <= ena_reg[0];
		end
	end
	else
	begin: GRAPHIC_VRAM_NOTEXIST
		assign colorG = 12'h0;
	end
	endgenerate
	

	wire [31:0] chData;
	reg [11:0] colorC_F, colorC_B;
	reg [2:0] HCoord_reg;
	wire charDot;
	wire inCursor;
	
	CharVRAM RAM1(.clka(clkMem), .ena(en_Char), .wea(weBus), .addra(addrBus[13:2]),
		.dina(dataInBus), .douta(dataOut_Char), .clkb(clkVGA),
		.addrb({VCoord[8:4], HCoord[9:3]}), .doutb(chData));
	CharROM ROM0(.clk(clkVGA), .ascii(chData[7:0]), .x(HCoord_reg), .y(VCoord[3:0]), .dot(charDot));

	reg [11:0] colorMixed;
	VGAScan #(.HCALIBRATE(0), .VCALIBRATE(0)) U0(
		.clk(clkVGA), .HAddr(HCoord), .VAddr(VCoord), .HSync(HSync), .VSync(VSync),
		.videoIn(colorMixed), .frameStart(frameStart), .videoOut(videoOut));
	
	always @ (posedge clkVGA)
	begin
		HCoord_reg <= HCoord[2:0];
		if(inCursor)
		begin
			colorC_F <= chData[31:20];
			colorC_B <= chData[19:8];
		end
		else
		begin
			colorC_F <= chData[19:8];
			colorC_B <= chData[31:20];
		end
	end
	
	always @*
	begin
		if(charDot)
			colorMixed <= colorC_F;
		else if((colorC_B == 12'h0) & ctrl1[0])
			colorMixed <= colorG;
		else
			colorMixed <= colorC_B;
		
	end
	
	vgaCursorGen cursor(.clk(clkVGA), .ctrl(ctrl0), .HCoord(HCoord), .VCoord(VCoord), .en(inCursor));

endmodule