data/full_repos/permissive/169496369/mux2x1_24b.v
data/verilator_xmls/d67eb8e1-ce94-499c-a42e-147d12a0ef15.xml
module mux2x1_24b(a, b, s, o);
    input [23:0] a, b;
    input s;
    
    output logic [23:0]o;
    
    assign o = s ? b : a;
    
endmodule
module mux2x1_24b(a, b, s, o);

    input [23:0] a, b;
    input s;
    
    output logic [23:0]o;
    
    assign o = s ? b : a;
    
endmodule