data/full_repos/permissive/120518070/main/source/dataToDecrypt.sv
data/verilator_xmls/ede0ee19-adfe-4a37-a79c-d6ee48a2021e.xml
module dataToDecrypt(
	input wire clk_i,
	input wire read_ready_i,
	input wire [31:0] rc4_data_i,
	output reg [31:0] dataToDecrypt_o
);

always_ff @(posedge clk_i)
begin
	if (read_ready_i == 1)
	begin
		dataToDecrypt_o <= rc4_data_i;
	end
	else
	begin
		dataToDecrypt_o <= dataToDecrypt_o;
	end
end
endmodule
module dataToDecrypt(
	input wire clk_i,
	input wire read_ready_i,
	input wire [31:0] rc4_data_i,
	output reg [31:0] dataToDecrypt_o
);


always_ff @(posedge clk_i)
begin
	if (read_ready_i == 1)
	begin
		dataToDecrypt_o <= rc4_data_i;
	end
	else
	begin
		dataToDecrypt_o <= dataToDecrypt_o;
	end
end
endmodule