data/full_repos/permissive/187199324/stannel/SaveState.v
1: b'%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:9: Define or directive not defined: \'`ADDRESS_BITS\'\nmodule SaveState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:9: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nmodule SaveState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                     ^\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:9: Define or directive not defined: \'`DATA_BITS\'\nmodule SaveState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:9: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule SaveState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                                                      ^\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                reset,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [dataBits-1:0] dataIn,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [addrBits-1:0] address,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                rwMode,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                finished,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [addrBits-1:0] stackPointer,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [addrBits-1:0] callStackPointer,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [8:0]          programCounter,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [3:0]          aluFlags,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [dataBits-1:0] topOfStack1,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [dataBits-1:0] topOfStack2,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [dataBits-1:0] topOfStack3\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:25: syntax error, unexpected \')\', expecting \',\' or \';\'\n  );\n  ^\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:30: syntax error, unexpected assign\n  assign dataIn = wDataIn;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:32: syntax error, unexpected assign\n  assign address = wAddress;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:34: Define or directive not defined: \'`RAM_WRITE\'\n  assign rwMode = reset && !finished ? `RAM_WRITE : `RAM_READ;\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:34: Define or directive not defined: \'`RAM_READ\'\n  assign rwMode = reset && !finished ? `RAM_WRITE : `RAM_READ;\n                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/SaveState.v:46: syntax error, unexpected assign\n  assign finished = rState == SAVE_DONE;\n  ^~~~~~\n%Error: Exiting due to 23 error(s)\n'
module SaveState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    output wire [dataBits-1:0] dataIn,
    output wire [addrBits-1:0] address,
    output wire                rwMode,
    output wire                finished,

    input  wire [addrBits-1:0] stackPointer,
    input  wire [addrBits-1:0] callStackPointer,
    input  wire [8:0]          programCounter,
    input  wire [3:0]          aluFlags,
    input  wire [dataBits-1:0] topOfStack1,
    input  wire [dataBits-1:0] topOfStack2,
    input  wire [dataBits-1:0] topOfStack3
  );



  reg [dataBits-1:0] wDataIn;
  assign dataIn = wDataIn;
  reg [addrBits-1:0] wAddress;
  assign address = wAddress;

  assign rwMode = reset && !finished ? `RAM_WRITE : `RAM_READ;

  reg rRamCycle;
  reg [2:0] rState;

  localparam SAVE_STACK_1                 = 3'd0;
  localparam SAVE_STACK_2                 = 3'd1;
  localparam SAVE_STACK_3                 = 3'd2;
  localparam SAVE_STACK_POINTERS          = 3'd3;
  localparam SAVE_PROGRAM_COUNTER_AND_ALU = 3'd4;
  localparam SAVE_DONE                    = 3'd5;

  assign finished = rState == SAVE_DONE;



  always @(posedge clk)
  begin
    if (!reset)
      rRamCycle <= 0;
    else
      rRamCycle <= rRamCycle + 1;

    if (!reset)
      rState <= 0;
    else if (rRamCycle)
      rState <= rState + 1;
  end

  always @(*)
    case (rState)
      SAVE_STACK_1:
      begin
        wAddress = stackPointer + 0;
        wDataIn  = topOfStack1;
      end
      SAVE_STACK_2:
      begin
        wAddress = stackPointer + 1;
        wDataIn  = topOfStack2;
      end
      SAVE_STACK_3:
      begin
        wAddress = stackPointer + 2;
        wDataIn  = topOfStack3;
      end
      SAVE_STACK_POINTERS:
      begin
        wAddress = 0;
        wDataIn  = { stackPointer, callStackPointer - 8'd2 };
      end
      SAVE_PROGRAM_COUNTER_AND_ALU:
      begin
        wAddress = 1;
        wDataIn  = { aluFlags, 3'b0, programCounter };
      end
      default:
      begin
        wAddress = {addrBits{1'bx}};
        wDataIn  = {dataBits{1'bx}};
      end
    endcase
endmodule
module SaveState #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    output wire [dataBits-1:0] dataIn,
    output wire [addrBits-1:0] address,
    output wire                rwMode,
    output wire                finished,

    input  wire [addrBits-1:0] stackPointer,
    input  wire [addrBits-1:0] callStackPointer,
    input  wire [8:0]          programCounter,
    input  wire [3:0]          aluFlags,
    input  wire [dataBits-1:0] topOfStack1,
    input  wire [dataBits-1:0] topOfStack2,
    input  wire [dataBits-1:0] topOfStack3
  );




  reg [dataBits-1:0] wDataIn;
  assign dataIn = wDataIn;
  reg [addrBits-1:0] wAddress;
  assign address = wAddress;

  assign rwMode = reset && !finished ? `RAM_WRITE : `RAM_READ;

  reg rRamCycle;
  reg [2:0] rState;

  localparam SAVE_STACK_1                 = 3'd0;
  localparam SAVE_STACK_2                 = 3'd1;
  localparam SAVE_STACK_3                 = 3'd2;
  localparam SAVE_STACK_POINTERS          = 3'd3;
  localparam SAVE_PROGRAM_COUNTER_AND_ALU = 3'd4;
  localparam SAVE_DONE                    = 3'd5;

  assign finished = rState == SAVE_DONE;



  always @(posedge clk)
  begin
    if (!reset)
      rRamCycle <= 0;
    else
      rRamCycle <= rRamCycle + 1;

    if (!reset)
      rState <= 0;
    else if (rRamCycle)
      rState <= rState + 1;
  end

  always @(*)
    case (rState)
      SAVE_STACK_1:
      begin
        wAddress = stackPointer + 0;
        wDataIn  = topOfStack1;
      end
      SAVE_STACK_2:
      begin
        wAddress = stackPointer + 1;
        wDataIn  = topOfStack2;
      end
      SAVE_STACK_3:
      begin
        wAddress = stackPointer + 2;
        wDataIn  = topOfStack3;
      end
      SAVE_STACK_POINTERS:
      begin
        wAddress = 0;
        wDataIn  = { stackPointer, callStackPointer - 8'd2 };
      end
      SAVE_PROGRAM_COUNTER_AND_ALU:
      begin
        wAddress = 1;
        wDataIn  = { aluFlags, 3'b0, programCounter };
      end
      default:
      begin
        wAddress = {addrBits{1'bx}};
        wDataIn  = {dataBits{1'bx}};
      end
    endcase
endmodule