data/full_repos/permissive/160024456/day18/part1_test.v
 line:21: before: "for"
1: b'%Warning-STMTDLY: data/full_repos/permissive/160024456/day18/part1_test.v:4: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = !clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160024456/day18/part1_test.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/day18/part1_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Error: data/full_repos/permissive/160024456/day18/part1_test.v:10: Cannot find file containing module: \'field\'\n  field dut (.clk(clk), .en(en), .trees(trees), .lumberyards(lumberyards));\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/160024456/day18,data/full_repos/permissive/160024456/field\n             data/full_repos/permissive/160024456/day18,data/full_repos/permissive/160024456/field.v\n             data/full_repos/permissive/160024456/day18,data/full_repos/permissive/160024456/field.sv\n             field\n             field.v\n             field.sv\n             obj_dir/field\n             obj_dir/field.v\n             obj_dir/field.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module part1_test;

  reg clk = 0;
  always #1 clk = !clk;
  reg en = 0;

  wire [2499:0] trees;
  wire [2499:0] lumberyards;

  field dut (.clk(clk), .en(en), .trees(trees), .lumberyards(lumberyards));

  integer i, j;

  initial begin
    $display("start");
    #10
    en = 1;


    #20
    for (i=0; i<50; i = i+1) begin
      for (j=0; j<50; j = j+1) begin
        if ((trees[i*50+j] == 0) && (lumberyards[i*50+j]==0))
          $write(".");
        else if ((trees[i*50+j] == 1) && (lumberyards[i*50+j]==0))
          $write("|");
        else if ((trees[i*50+j] == 0) && (lumberyards[i*50+j]==1))
          $write("#");
        else
          $write("E");
      end
      $display();
    end
    $display();

    $display("tree=%b", trees);
    $display("lumberyards=%b", lumberyards);

    $finish;
  end
endmodule
module part1_test;


  reg clk = 0;
  always #1 clk = !clk;
  reg en = 0;

  wire [2499:0] trees;
  wire [2499:0] lumberyards;

  field dut (.clk(clk), .en(en), .trees(trees), .lumberyards(lumberyards));

  integer i, j;

  initial begin
    $display("start");
    #10
    en = 1;


    #20
    for (i=0; i<50; i = i+1) begin
      for (j=0; j<50; j = j+1) begin
        if ((trees[i*50+j] == 0) && (lumberyards[i*50+j]==0))
          $write(".");
        else if ((trees[i*50+j] == 1) && (lumberyards[i*50+j]==0))
          $write("|");
        else if ((trees[i*50+j] == 0) && (lumberyards[i*50+j]==1))
          $write("#");
        else
          $write("E");
      end
      $display();
    end
    $display();

    $display("tree=%b", trees);
    $display("lumberyards=%b", lumberyards);

    $finish;
  end
endmodule