data/full_repos/permissive/13201424/vlog/tmds_decode.v
 line:25: before: "for"
1: b'%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_decode.v:20: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tmds_decode\n wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_decode.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tmds_decode\n wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_decode.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tmds_decode\n wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_decode.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tmds_decode\n wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_decode.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tmds_decode\n wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_decode.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tmds_decode\n wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_decode.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tmds_decode\n wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];\n                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_decode.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tmds_decode\n wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];\n                                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_decode.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tmds_decode\n wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];\n                                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_decode.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance tmds_decode\n wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];\n                                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_decode.v:53: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 9 bits.\n                                                                         : ... In instance tmds_decode\n   q_in_disparity = {n1_q_in, 1\'b0} - 8\'d10;\n                  ^\n%Error: Exiting due to 11 warning(s)\n'
module tmds_decode (
	input clk, input rst,
	input [9:0] q_in,
	output reg [7:0] d,
	output reg c0,
	output reg c1,
	output reg de,
	output reg signed [7:0] cnt);

	reg [9:0] s1_q_in;
	wire [7:0] d_q;
	reg c0_1, c1_1, de_1;
	genvar i;
	
	wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];
	reg signed [7:0] q_in_disparity;
	

	assign d_q[0] = s1_q_in[0];
	for (i = 1; i < 8; i = i + 1) begin : decode_loop
		assign d_q[i] = (s1_q_in[8]) ? (s1_q_in[i] ^ s1_q_in[i - 1]) : ~(s1_q_in[i] ^ s1_q_in[i - 1]);
	end
	
	always @ (posedge clk) begin
		if (rst) begin
			cnt <= 0;
		end else begin
			case(q_in)
				10'b1101010100 : {de_1, c0_1, c1_1} <= 3'b000;
				10'b0010101011 : {de_1, c0_1, c1_1} <= 3'b001;
				10'b0101010100 : {de_1, c0_1, c1_1} <= 3'b010;
				10'b1010101011 : {de_1, c0_1, c1_1} <= 3'b011;
				default : {de_1, c0_1, c1_1} <= 3'b100;
			endcase
			

			s1_q_in[9:8] <= q_in[9:8];
			s1_q_in[7:0] <= (q_in[9]) ? (~q_in[7:0]) : (q_in[7:0]);
			

			d <= d_q;
			
			de <= de_1;
			c0 <= c0_1;
			c1 <= c1_1;
			

			q_in_disparity = {n1_q_in, 1'b0} - 8'd10;
			cnt <= cnt + q_in_disparity;
		end
	end
endmodule
module tmds_decode (
	input clk, input rst,
	input [9:0] q_in,
	output reg [7:0] d,
	output reg c0,
	output reg c1,
	output reg de,
	output reg signed [7:0] cnt);


	reg [9:0] s1_q_in;
	wire [7:0] d_q;
	reg c0_1, c1_1, de_1;
	genvar i;
	
	wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];
	reg signed [7:0] q_in_disparity;
	

	assign d_q[0] = s1_q_in[0];
	for (i = 1; i < 8; i = i + 1) begin : decode_loop
		assign d_q[i] = (s1_q_in[8]) ? (s1_q_in[i] ^ s1_q_in[i - 1]) : ~(s1_q_in[i] ^ s1_q_in[i - 1]);
	end
	
	always @ (posedge clk) begin
		if (rst) begin
			cnt <= 0;
		end else begin
			case(q_in)
				10'b1101010100 : {de_1, c0_1, c1_1} <= 3'b000;
				10'b0010101011 : {de_1, c0_1, c1_1} <= 3'b001;
				10'b0101010100 : {de_1, c0_1, c1_1} <= 3'b010;
				10'b1010101011 : {de_1, c0_1, c1_1} <= 3'b011;
				default : {de_1, c0_1, c1_1} <= 3'b100;
			endcase
			

			s1_q_in[9:8] <= q_in[9:8];
			s1_q_in[7:0] <= (q_in[9]) ? (~q_in[7:0]) : (q_in[7:0]);
			

			d <= d_q;
			
			de <= de_1;
			c0 <= c0_1;
			c1 <= c1_1;
			

			q_in_disparity = {n1_q_in, 1'b0} - 8'd10;
			cnt <= cnt + q_in_disparity;
		end
	end
endmodule