data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/display_top.v
1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/display_top.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n             char_def.vh\n             char_def.vh.v\n             char_def.vh.sv\n             obj_dir/char_def.vh\n             obj_dir/char_def.vh.v\n             obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/display_top.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n         ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module display_top(
    input SYSCLK_IP,
    input [7:0] SW_IP,
    input CPU_RESETN_IP,
    output [7:0] LED_OP,
    output OLED_DC_OP,
    output OLED_RES_OP,
    output OLED_SCLK_OP,
    output OLED_SDIN_OP,
    output OLED_VBAT_OP,
    output OLED_VDD_OP,
    input WE_IP,
    input [5:0] WRITE_ADDR_IP,
    input [7:0] WRITE_DATA_IP
    );

    reg [7:0] sw_r;
    wire [64*8-1:0] char_data;
    wire print_fin;

    oled_ctrl o_ctrl(
    .clk(SYSCLK_IP),
    .rst(~CPU_RESETN_IP),
    .dc(OLED_DC_OP),
    .res(OLED_RES_OP),
    .sclk(OLED_SCLK_OP),
    .sdo(OLED_SDIN_OP),
    .vbat(OLED_VBAT_OP),
    .vdd(OLED_VDD_OP),
    .char_data(char_data),
    .print_fin(print_fin)
    );

    char_test c_test(
    .clk(SYSCLK_IP),
    .rst(~CPU_RESETN_IP),
    .dout(char_data),
    .print_fin(print_fin),
    .we(WE_IP),
    .wr_addr(WRITE_ADDR_IP),
    .din(WRITE_DATA_IP)
    );

    assign LED_OP = sw_r;

    always @(posedge SYSCLK_IP)
        sw_r <= SW_IP;

endmodule
module display_top(
    input SYSCLK_IP,
    input [7:0] SW_IP,
    input CPU_RESETN_IP,
    output [7:0] LED_OP,
    output OLED_DC_OP,
    output OLED_RES_OP,
    output OLED_SCLK_OP,
    output OLED_SDIN_OP,
    output OLED_VBAT_OP,
    output OLED_VDD_OP,
    input WE_IP,
    input [5:0] WRITE_ADDR_IP,
    input [7:0] WRITE_DATA_IP
    );


    reg [7:0] sw_r;
    wire [64*8-1:0] char_data;
    wire print_fin;

    oled_ctrl o_ctrl(
    .clk(SYSCLK_IP),
    .rst(~CPU_RESETN_IP),
    .dc(OLED_DC_OP),
    .res(OLED_RES_OP),
    .sclk(OLED_SCLK_OP),
    .sdo(OLED_SDIN_OP),
    .vbat(OLED_VBAT_OP),
    .vdd(OLED_VDD_OP),
    .char_data(char_data),
    .print_fin(print_fin)
    );

    char_test c_test(
    .clk(SYSCLK_IP),
    .rst(~CPU_RESETN_IP),
    .dout(char_data),
    .print_fin(print_fin),
    .we(WE_IP),
    .wr_addr(WRITE_ADDR_IP),
    .din(WRITE_DATA_IP)
    );

    assign LED_OP = sw_r;

    always @(posedge SYSCLK_IP)
        sw_r <= SW_IP;

endmodule