data/full_repos/permissive/211471959/src/hdl/shift.v
 line:27: before: "="
data/verilator_xmls/fbb2d3ca-fdf8-4472-814a-04257d2a5650.xml
module shift(
    input sel,
    input clk,
    input reset,
    output reg [15:0] led = 0
    );
    
    reg [3:0] shift_count = 0;
    always @(posedge clk, posedge reset) begin
        if (reset) begin
            shift_count <= 0;
            led <= 0;
        end
        else begin
        if(shift_count >= 15) begin
            shift_count <= 0;
        end



        led <= sel ? 1 << shift_count : 2**15 >> shift_count;
                                                              
        shift_count <= shift_count + 1;
        end
    end
endmodule
module shift(
    input sel,
    input clk,
    input reset,
    output reg [15:0] led = 0
    );

    
    reg [3:0] shift_count = 0;
    always @(posedge clk, posedge reset) begin
        if (reset) begin
            shift_count <= 0;
            led <= 0;
        end
        else begin
        if(shift_count >= 15) begin
            shift_count <= 0;
        end



        led <= sel ? 1 << shift_count : 2**15 >> shift_count;
                                                              
        shift_count <= shift_count + 1;
        end
    end
endmodule