data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_debouncer.v
data/verilator_xmls/6c044b4d-5cdb-46e2-b852-7a4571c68acb.xml
module raggedstone_spinn_aer_if_debouncer
#(

  parameter DBNCER_CONST = 20'hfffff,
  parameter RESET_VALUE  = 1'b1
)
(
  input  wire                   rst,
  input  wire                   clk,


  input  wire                   pb_input,
  output reg                    pb_debounced
);



  reg [19:0] pb_debounce_cnt;
  reg  [2:0] pb_bounce;
  reg        pb_sel_debounced;





  initial
    begin
      pb_debounced = RESET_VALUE;
      pb_debounce_cnt = DBNCER_CONST;
    end

  always @(posedge clk or posedge rst)
    if (rst)
      pb_debounced <= RESET_VALUE;
    else
      if ((pb_bounce[2] == pb_bounce[1]) && (pb_debounce_cnt == 0))
        pb_debounced <= pb_bounce[2];

  always @(posedge clk)
    begin
      pb_bounce[0] <= pb_input;  
      pb_bounce[1] <= pb_bounce[0];
      pb_bounce[2] <= pb_bounce[1];
    end

  always @(posedge clk)
    if (pb_bounce[2] != pb_bounce[1]) 
      pb_debounce_cnt <= DBNCER_CONST;
    else
      if (pb_debounce_cnt != 0)
        pb_debounce_cnt <= pb_debounce_cnt - 1;
endmodule
module raggedstone_spinn_aer_if_debouncer
#(

  parameter DBNCER_CONST = 20'hfffff,
  parameter RESET_VALUE  = 1'b1
)
(
  input  wire                   rst,
  input  wire                   clk,


  input  wire                   pb_input,
  output reg                    pb_debounced
);




  reg [19:0] pb_debounce_cnt;
  reg  [2:0] pb_bounce;
  reg        pb_sel_debounced;





  initial
    begin
      pb_debounced = RESET_VALUE;
      pb_debounce_cnt = DBNCER_CONST;
    end

  always @(posedge clk or posedge rst)
    if (rst)
      pb_debounced <= RESET_VALUE;
    else
      if ((pb_bounce[2] == pb_bounce[1]) && (pb_debounce_cnt == 0))
        pb_debounced <= pb_bounce[2];

  always @(posedge clk)
    begin
      pb_bounce[0] <= pb_input;  
      pb_bounce[1] <= pb_bounce[0];
      pb_bounce[2] <= pb_bounce[1];
    end

  always @(posedge clk)
    if (pb_bounce[2] != pb_bounce[1]) 
      pb_debounce_cnt <= DBNCER_CONST;
    else
      if (pb_debounce_cnt != 0)
        pb_debounce_cnt <= pb_debounce_cnt - 1;
endmodule