data/full_repos/permissive/178052224/Tarea3y4/modules/demux_1to2.v
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1: b'%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/demux_1to2.v:1: Cannot find include file: not.v\n`include "not.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/178052224/Tarea3y4/modules,data/full_repos/permissive/178052224/not.v\n             data/full_repos/permissive/178052224/Tarea3y4/modules,data/full_repos/permissive/178052224/not.v.v\n             data/full_repos/permissive/178052224/Tarea3y4/modules,data/full_repos/permissive/178052224/not.v.sv\n             not.v\n             not.v.v\n             not.v.sv\n             obj_dir/not.v\n             obj_dir/not.v.v\n             obj_dir/not.v.sv\n%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/demux_1to2.v:2: Cannot find include file: nand.v\n`include "nand.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/demux_1to2.v:3: Cannot find include file: nor.v\n`include "nor.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/demux_1to2.v:4: Cannot find include file: flip-flop.v\n`include "flip-flop.v" \n         ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module demux_1to2(   input clk, reset_L, data_in,
                output wire data_out0, data_out1);
   
   

    reg s = 'b0;
    

    wire data_after_reset_L, s_n, out0_before_inv, out1_before_inv;
    
    

    nandG   nandRST(data_in, reset_L , data_after_reset_L);
    notG    sneg(s, s_n);
    nandG   nand0(data_in, s, out0);
    nandG   nand1(data_in, s_n, out1);
    notG    data_out_neg_0(out0_before_inv, data_out0);
    notG    data_out_neg_1(out1_before_inv, data_out1);
endmodule
module demux_1to2(   input clk, reset_L, data_in,
                output wire data_out0, data_out1);

   
   

    reg s = 'b0;
    

    wire data_after_reset_L, s_n, out0_before_inv, out1_before_inv;
    
    

    nandG   nandRST(data_in, reset_L , data_after_reset_L);
    notG    sneg(s, s_n);
    nandG   nand0(data_in, s, out0);
    nandG   nand1(data_in, s_n, out1);
    notG    data_out_neg_0(out0_before_inv, data_out0);
    notG    data_out_neg_1(out1_before_inv, data_out1);
endmodule