data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v
1: b'%Error: data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v:20: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("fifo_wave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v:21: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #80;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_tester.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifo_tester #(parameter DATA_WIDTH = 8, parameter ADDRESS_WIDTH = 3, parameter BUFFER_DEPTH = 8)(
  output reg CLK,
  output reg ENB,
  output reg RST,
  output reg sRead,
  output reg sWrite,


  output reg [ADDRESS_WIDTH-1:0] umbEmpty,
  output reg [ADDRESS_WIDTH-1:0] umbFull,

  output reg [DATA_WIDTH-1:0] inputData
  );

  initial begin
    CLK <= 0;
  end

  initial begin
    $dumpfile("fifo_wave.vcd");
    $dumpvars;
    ENB <= 0;
    RST <= 1;
    inputData <= 8'b00110011;
    sRead <= 0;
    sWrite <= 0;
    umbEmpty <= 3'd3;
    umbFull <= 3'd6;
    #10;
    RST <=0;
    #10;
    ENB <= 1;
    sWrite <= 1;

    #80;
    sWrite <= 0;
    sRead <= 0;

    #20;
    sRead <= 1;

    #100;

    ENB <= 0;
    RST <= 1;
    inputData <= 8'b11001100;
    sRead <= 0;
    sWrite <= 0;
    umbEmpty <= 3'd3;
    umbFull <= 3'd6;
    #10;
    RST <=0;
    #10;
    ENB <= 1;
    sWrite <= 1;

    #100;

    $finish;
  end

  always begin
    #5;
    CLK <= ~CLK;
  end
endmodule
module fifo_tester #(parameter DATA_WIDTH = 8, parameter ADDRESS_WIDTH = 3, parameter BUFFER_DEPTH = 8)(
  output reg CLK,
  output reg ENB,
  output reg RST,
  output reg sRead,
  output reg sWrite,


  output reg [ADDRESS_WIDTH-1:0] umbEmpty,
  output reg [ADDRESS_WIDTH-1:0] umbFull,

  output reg [DATA_WIDTH-1:0] inputData
  );


  initial begin
    CLK <= 0;
  end

  initial begin
    $dumpfile("fifo_wave.vcd");
    $dumpvars;
    ENB <= 0;
    RST <= 1;
    inputData <= 8'b00110011;
    sRead <= 0;
    sWrite <= 0;
    umbEmpty <= 3'd3;
    umbFull <= 3'd6;
    #10;
    RST <=0;
    #10;
    ENB <= 1;
    sWrite <= 1;

    #80;
    sWrite <= 0;
    sRead <= 0;

    #20;
    sRead <= 1;

    #100;

    ENB <= 0;
    RST <= 1;
    inputData <= 8'b11001100;
    sRead <= 0;
    sWrite <= 0;
    umbEmpty <= 3'd3;
    umbFull <= 3'd6;
    #10;
    RST <=0;
    #10;
    ENB <= 1;
    sWrite <= 1;

    #100;

    $finish;
  end

  always begin
    #5;
    CLK <= ~CLK;
  end
endmodule