data/full_repos/permissive/189570969/1180300220-崔涵/1180300220-崔涵-完整工程/project_1.srcs/sources_1/new/huo4.v
data/verilator_xmls/84f992b8-df68-4ba3-9f9d-61da6e80f4d1.xml
module huo4(
    input a1,
    input a2,
    input a3,
    input a4,
    output oup
    );
    assign oup=a1|a2|a3|a4;
endmodule
module huo4(
    input a1,
    input a2,
    input a3,
    input a4,
    output oup
    );

    assign oup=a1|a2|a3|a4;
endmodule