data/full_repos/permissive/128497744/fsm_calculator_part3/Full_Calculator/Full_Calculator.srcs/sources_1/new/mux2.v
data/verilator_xmls/3ce77dbe-f716-446a-961d-7b288ca9fba9.xml
module MUX2 #(parameter Data_width = 4)(
input [Data_width - 1:0] d0, d1,
input sel,
output reg [Data_width - 1:0] out 
);

always @ (d0, d1, sel)
begin
        if (sel)
            out <= d1;
        else
            out <= d0;
end
endmodule
module MUX2 #(parameter Data_width = 4)(
input [Data_width - 1:0] d0, d1,
input sel,
output reg [Data_width - 1:0] out 
);


always @ (d0, d1, sel)
begin
        if (sel)
            out <= d1;
        else
            out <= d0;
end
endmodule