data/full_repos/permissive/211316121/lab6_3/clkdiv.v
data/verilator_xmls/0bd64705-56ef-47f3-81ac-5e95e1357246.xml
module clkdiv(
    input mclk,


    output clk95,
    output clk48

    );
    reg [27:0] q;
    always@(posedge mclk)




         q<=q+1;


    assign clk95=q[19];
    assign clk48=q[20];

endmodule
module clkdiv(
    input mclk,


    output clk95,
    output clk48

    );

    reg [27:0] q;
    always@(posedge mclk)




         q<=q+1;


    assign clk95=q[19];
    assign clk48=q[20];

endmodule