data/full_repos/permissive/20270692/labs/lab1/fig3p37_tb.v
 line:38: before: "$"
1: b'%Error: data/full_repos/permissive/20270692/labs/lab1/fig3p37_tb.v:7: Cannot find include file: fig3p37.v\n`include "fig3p37.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab1,data/full_repos/permissive/20270692/fig3p37.v\n             data/full_repos/permissive/20270692/labs/lab1,data/full_repos/permissive/20270692/fig3p37.v.v\n             data/full_repos/permissive/20270692/labs/lab1,data/full_repos/permissive/20270692/fig3p37.v.sv\n             fig3p37.v\n             fig3p37.v.v\n             fig3p37.v.sv\n             obj_dir/fig3p37.v\n             obj_dir/fig3p37.v.v\n             obj_dir/fig3p37.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab1/fig3p37_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab1/fig3p37_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\ninitial #200 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module fig3p37_tb (A,B,C);
  output A,B,C;
  reg A,B,C;


  fig3p37 I1 (A,B,C,D,E);

  initial
    begin


      A=1'b0; B=1'b0; C=1'b0;
      #100
      A=1'b1; B=1'b1; C=1'b1;


    end

initial #200 $finish;

endmodule
module fig3p37_tb (A,B,C);

  output A,B,C;
  reg A,B,C;


  fig3p37 I1 (A,B,C,D,E);

  initial
    begin


      A=1'b0; B=1'b0; C=1'b0;
      #100
      A=1'b1; B=1'b1; C=1'b1;


    end

initial #200 $finish;

endmodule