data/full_repos/permissive/184916587/OLD/Decoder.v
 line:167: before: "module"
1: b'%Error: Unsupported: module decls within module decls\n%Error: data/full_repos/permissive/184916587/OLD/Decoder.v:178: syntax error, unexpected $end\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module R_type_decode(

	input[31:0] instr,

	output[9:0] alu_op,
	output[4:0] rs1,
	output[4:0] rs2,
	output[4:0] rd
);

	wire[2:0] funct3;
	wire[6:0] funct7;

	assign rs1=instr[19:15];
	assign rs2=instr[24:20];
	assign rd=instr[11:7];

	assign funct3=instr[14:12];
	assign funct7=instr[31:25];
	
	reg[9:0] alu_op_temp;


	always @(*)
	begin

		if(funct7===7'b0000000)
			begin
				if(funct3===3'b000)
					alu_op_temp=10'b0000000001;
			end
			begin
				if(funct3===3'b001)
					alu_op_temp=10'b0000000011;
			end
			begin
				if(funct3===3'b010)
					alu_op_temp=10'b0000000101;
			end
			begin
				if(funct3===3'b011)
					alu_op_temp=10'b0000000110;
			end
			begin
				if(funct3===3'b100)
					alu_op_temp=10'b0000000111;
			end
			begin
				if(funct3===3'b101)
					alu_op_temp=10'b0000001000;
			end
			begin
				if(funct3===3'b110)
					alu_op_temp=10'b0000001010;
			end
			begin
				if(funct3===3'b111)
					alu_op_temp=10'b0000001011;
			end
	end
	always @(*)
	begin

		if(funct7===7'b0100000)
			begin
				if(funct3===3'b000)
					alu_op_temp=10'b0000000010;
			end
			begin
				if(funct3===3'b101)
					alu_op_temp=10'b0000001001;
			end
	end

	assign alu_op=alu_op_temp;

module I_type_decode(
	input[31:0] instr,
	output[9:0] alu_op,
	output[4:0] rs1,
	output[4:0] rd
);
	always @(*) begin
		
	end

endmodule
module R_type_decode(

	input[31:0] instr,

	output[9:0] alu_op,
	output[4:0] rs1,
	output[4:0] rs2,
	output[4:0] rd
);


	wire[2:0] funct3;
	wire[6:0] funct7;

	assign rs1=instr[19:15];
	assign rs2=instr[24:20];
	assign rd=instr[11:7];

	assign funct3=instr[14:12];
	assign funct7=instr[31:25];
	
	reg[9:0] alu_op_temp;


	always @(*)
	begin

		if(funct7===7'b0000000)
			begin
				if(funct3===3'b000)
					alu_op_temp=10'b0000000001;
			end
			begin
				if(funct3===3'b001)
					alu_op_temp=10'b0000000011;
			end
			begin
				if(funct3===3'b010)
					alu_op_temp=10'b0000000101;
			end
			begin
				if(funct3===3'b011)
					alu_op_temp=10'b0000000110;
			end
			begin
				if(funct3===3'b100)
					alu_op_temp=10'b0000000111;
			end
			begin
				if(funct3===3'b101)
					alu_op_temp=10'b0000001000;
			end
			begin
				if(funct3===3'b110)
					alu_op_temp=10'b0000001010;
			end
			begin
				if(funct3===3'b111)
					alu_op_temp=10'b0000001011;
			end
	end
	always @(*)
	begin

		if(funct7===7'b0100000)
			begin
				if(funct3===3'b000)
					alu_op_temp=10'b0000000010;
			end
			begin
				if(funct3===3'b101)
					alu_op_temp=10'b0000001001;
			end
	end

	assign alu_op=alu_op_temp;

module I_type_decode(
	input[31:0] instr,
	output[9:0] alu_op,
	output[4:0] rs1,
	output[4:0] rd
);
	always @(*) begin
		
	end

endmodule