data/full_repos/permissive/210118624/MB112S146.v
1: b'%Warning-WIDTH: data/full_repos/permissive/210118624/MB112S146.v:40: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                   : ... In instance MB112S146\nassign out1 = (reverse) ? dataReg1[counter] : dataReg1[7-counter];\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/210118624/MB112S146.v:41: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                   : ... In instance MB112S146\nassign out2 = (reverse) ? dataReg2[counter] : dataReg2[7-counter];\n                                  ^\n%Error: Exiting due to 2 warning(s)\n'
module MB112S146 (clk, load, data1, data2, out1, out2, reverse, latch, in1, in2, select16bit, clear); 
input  clk, load, reverse, clear; 
input  latch, in1, in2, select16bit;

input [7:0] data1, data2;
reg [7:0] dataReg1, dataReg2;
reg [3:0] counter;
output out1, out2; 
 
always @( posedge clk or negedge clear ) 
begin 
	if (~clear)
	begin

		dataReg1 <= 8'b0;
		dataReg2 <= 8'b0;
		counter = 0;
	end
	else if (~load)
	begin
		counter = 0;
		dataReg1 <= data1;
		dataReg2 <= data2;
	end
	else if (load)
	begin
		if (counter < 7)
		begin
			counter = counter + 1;
		end
		else
		begin
			dataReg1 <= 8'b0;
			dataReg2 <= 8'b0;
		end
	end
	
end

assign out1 = (reverse) ? dataReg1[counter] : dataReg1[7-counter];
assign out2 = (reverse) ? dataReg2[counter] : dataReg2[7-counter];

endmodule
module MB112S146 (clk, load, data1, data2, out1, out2, reverse, latch, in1, in2, select16bit, clear);
 
input  clk, load, reverse, clear; 
input  latch, in1, in2, select16bit;

input [7:0] data1, data2;
reg [7:0] dataReg1, dataReg2;
reg [3:0] counter;
output out1, out2; 
 
always @( posedge clk or negedge clear ) 
begin 
	if (~clear)
	begin

		dataReg1 <= 8'b0;
		dataReg2 <= 8'b0;
		counter = 0;
	end
	else if (~load)
	begin
		counter = 0;
		dataReg1 <= data1;
		dataReg2 <= data2;
	end
	else if (load)
	begin
		if (counter < 7)
		begin
			counter = counter + 1;
		end
		else
		begin
			dataReg1 <= 8'b0;
			dataReg2 <= 8'b0;
		end
	end
	
end

assign out1 = (reverse) ? dataReg1[counter] : dataReg1[7-counter];
assign out2 = (reverse) ? dataReg2[counter] : dataReg2[7-counter];

endmodule