data/full_repos/permissive/139213403/FPGA/blastit_demo_uart.v
1: b"%Error: data/full_repos/permissive/139213403/FPGA/blastit_demo_uart.v:70: Cannot find file containing module: 'uart'\n uart #(.FIFO_R(2), .FIFO_W(2), .DVSR_BIT(8), .DBIT(8)) \n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/uart\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/uart.v\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Error: Exiting due to 1 error(s)\n"
module blastit_demo_uart
(



	input wire CLOCK_50,




	input wire DAYLIGHT,
	



	input wire UART_RX,
	



	output wire[7:0] C_SSEG,
	



	output wire[15:0] C,
	



	output wire[9:0] D,
	



	output wire[9:0] G,
	



	output wire UART_TX,
	



	output wire[3:0] LED,
	



	output wire WARN
);

	wire tx;


	reg [7:0] tx_data_reg, tx_data_next;
	reg tx_en_reg, tx_en_next;
	wire [7:0] e_data;
	wire rx_done_tick, tx_done_tick;
	wire tx_full, rx_empty;
	wire tx_empty, rx_full;





	uart #(.FIFO_R(2), .FIFO_W(2), .DVSR_BIT(8), .DBIT(8)) 
		  uart_unit(
			  .clk(CLOCK_50), .reset(0), 
			  .dbit(8), .pbit(1), .sb_tick(32), .os_tick(32), .dvsr(13),
			  .rd_uart(~rx_empty), .wr_uart(rx_done_tick), 
			  .rx(UART_RX), .w_data(e_data), .tx_full(tx_full), .rx_empty(rx_empty),
			  .tx(UART_TX), .r_data(e_data), .tx_done_tick(tx_done_tick), .rx_done_tick(rx_done_tick),
			  .tx_empty(tx_empty), .rx_full(rx_full)
		  );
		
	assign LED = { ~rx_empty, ~rx_full, ~tx_empty, ~tx_full };
	
endmodule
module blastit_demo_uart
(



	input wire CLOCK_50,




	input wire DAYLIGHT,
	



	input wire UART_RX,
	



	output wire[7:0] C_SSEG,
	



	output wire[15:0] C,
	



	output wire[9:0] D,
	



	output wire[9:0] G,
	



	output wire UART_TX,
	



	output wire[3:0] LED,
	



	output wire WARN
);


	wire tx;


	reg [7:0] tx_data_reg, tx_data_next;
	reg tx_en_reg, tx_en_next;
	wire [7:0] e_data;
	wire rx_done_tick, tx_done_tick;
	wire tx_full, rx_empty;
	wire tx_empty, rx_full;





	uart #(.FIFO_R(2), .FIFO_W(2), .DVSR_BIT(8), .DBIT(8)) 
		  uart_unit(
			  .clk(CLOCK_50), .reset(0), 
			  .dbit(8), .pbit(1), .sb_tick(32), .os_tick(32), .dvsr(13),
			  .rd_uart(~rx_empty), .wr_uart(rx_done_tick), 
			  .rx(UART_RX), .w_data(e_data), .tx_full(tx_full), .rx_empty(rx_empty),
			  .tx(UART_TX), .r_data(e_data), .tx_done_tick(tx_done_tick), .rx_done_tick(rx_done_tick),
			  .tx_empty(tx_empty), .rx_full(rx_full)
		  );
		
	assign LED = { ~rx_empty, ~rx_full, ~tx_empty, ~tx_full };
	
endmodule