data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v
 line:30: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:10: Unsupported: Ignoring delay on this delayed statement.\nalways #3 clock = ~ clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:15: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("out.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:16: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,simple_sim);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #5 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #5 reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #50 pause = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #50 pause = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #100 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simple_sim ();
reg         clock;
reg         reset;
reg         pause;
reg         reverse;
wire [6:0]  data;

Counter7SD C7SD(clock,reset,pause,reverse,data);

always #3 clock = ~ clock;


initial
begin
  $dumpfile("out.vcd");
  $dumpvars(0,simple_sim);
end

initial begin
  clock = 1;


  #5 reset = 0;
  #5 reset = 1;
  #50 pause = 0;
  #50 pause = 1;

  #100 reset = 0;

  #10 $finish;
end
endmodule
module simple_sim ();

reg         clock;
reg         reset;
reg         pause;
reg         reverse;
wire [6:0]  data;

Counter7SD C7SD(clock,reset,pause,reverse,data);

always #3 clock = ~ clock;


initial
begin
  $dumpfile("out.vcd");
  $dumpvars(0,simple_sim);
end

initial begin
  clock = 1;


  #5 reset = 0;
  #5 reset = 1;
  #50 pause = 0;
  #50 pause = 1;

  #100 reset = 0;

  #10 $finish;
end
endmodule