data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic/full_adder_8.v
1: b"%Error: data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic/full_adder_8.v:7: Cannot find file containing module: 'full_adder'\n    full_adder F_A_0 (X[0], Y[0], Cin, carry[0], Sum[0]);\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic,data/full_repos/permissive/149912776/full_adder\n             data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic,data/full_repos/permissive/149912776/full_adder.v\n             data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic,data/full_repos/permissive/149912776/full_adder.sv\n             full_adder\n             full_adder.v\n             full_adder.sv\n             obj_dir/full_adder\n             obj_dir/full_adder.v\n             obj_dir/full_adder.sv\n%Error: data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic/full_adder_8.v:8: Cannot find file containing module: 'full_adder'\n    full_adder F_A_1 (X[1], Y[1], carry[0], carry[1], Sum[1]);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic/full_adder_8.v:9: Cannot find file containing module: 'full_adder'\n    full_adder F_A_2 (X[2], Y[2], carry[1], carry[2], Sum[2]);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic/full_adder_8.v:10: Cannot find file containing module: 'full_adder'\n    full_adder F_A_3 (X[3], Y[3], carry[2], carry[3], Sum[3]);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic/full_adder_8.v:11: Cannot find file containing module: 'full_adder'\n    full_adder F_A_4 (X[4], Y[4], carry[3], carry[4], Sum[4]);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic/full_adder_8.v:12: Cannot find file containing module: 'full_adder'\n    full_adder F_A_5 (X[5], Y[5], carry[4], carry[5], Sum[5]);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic/full_adder_8.v:13: Cannot find file containing module: 'full_adder'\n    full_adder F_A_6 (X[6], Y[6], carry[5], carry[6], Sum[6]);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic/full_adder_8.v:14: Cannot find file containing module: 'full_adder'\n    full_adder F_A_7 (X[7], Y[7], carry[6], Cout, Sum[7]);\n    ^~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module full_adder_8 (Sum, Cout, X, Y, Cin);
input [7:0] X, Y;
input Cin;
output [7:0] Sum;
output Cout;
wire [7:0] carry;
    full_adder F_A_0 (X[0], Y[0], Cin, carry[0], Sum[0]);
    full_adder F_A_1 (X[1], Y[1], carry[0], carry[1], Sum[1]);
    full_adder F_A_2 (X[2], Y[2], carry[1], carry[2], Sum[2]);
    full_adder F_A_3 (X[3], Y[3], carry[2], carry[3], Sum[3]);
    full_adder F_A_4 (X[4], Y[4], carry[3], carry[4], Sum[4]);
    full_adder F_A_5 (X[5], Y[5], carry[4], carry[5], Sum[5]);
    full_adder F_A_6 (X[6], Y[6], carry[5], carry[6], Sum[6]);
    full_adder F_A_7 (X[7], Y[7], carry[6], Cout, Sum[7]);
endmodule
module full_adder_8 (Sum, Cout, X, Y, Cin);

input [7:0] X, Y;
input Cin;
output [7:0] Sum;
output Cout;
wire [7:0] carry;
    full_adder F_A_0 (X[0], Y[0], Cin, carry[0], Sum[0]);
    full_adder F_A_1 (X[1], Y[1], carry[0], carry[1], Sum[1]);
    full_adder F_A_2 (X[2], Y[2], carry[1], carry[2], Sum[2]);
    full_adder F_A_3 (X[3], Y[3], carry[2], carry[3], Sum[3]);
    full_adder F_A_4 (X[4], Y[4], carry[3], carry[4], Sum[4]);
    full_adder F_A_5 (X[5], Y[5], carry[4], carry[5], Sum[5]);
    full_adder F_A_6 (X[6], Y[6], carry[5], carry[6], Sum[6]);
    full_adder F_A_7 (X[7], Y[7], carry[6], Cout, Sum[7]);
endmodule