data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v
 line:609: before: "dat_o"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:506: Signal definition not found, creating implicitly: \'param_scs\'\n                                                                                            : ... Suggested alternative: \'param_o\'\n   assign     param_scs       = param2[3];  \n              ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:612: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                         : ... In instance spi_flash_ctrl.simple_spi\n  assign rfre = wb_acc & (adr_i == 2\'b10) & ack_o & ~we_i;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:631: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                         : ... In instance spi_flash_ctrl.simple_spi\n  wire wr_spsr = wb_wr & (adr_i == 2\'b01);\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:192: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n   wire [63:0]      buf_addr_t = (buf_addr[31:20]==12\'h1fc)? \n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:192: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n   wire [63:0]      buf_addr_t = (buf_addr[31:20]==12\'h1fc)? \n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:370: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'nxt_addr\' generates 24 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n                                                   nxt_addr - 24\'h1f    :\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:370: Operator SUB expects 64 bits on the RHS, but RHS\'s CONST \'24\'h1f\' generates 24 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n                                                   nxt_addr - 24\'h1f    :\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:371: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'nxt_addr\' generates 24 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n                                                   nxt_addr + 24\'b1) :\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:371: Operator ADD expects 64 bits on the RHS, but RHS\'s CONST \'24\'h1\' generates 24 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n                                                   nxt_addr + 24\'b1) :\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:369: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s VARREF \'nxt_addr\' generates 24 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n                     byte_ready & ~spi_pause? (buf_wrap&(&nxt_addr[4:0]) & ~(tot_bytes == 8\'b0)?\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:368: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s COND generates 64 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n         nxt_addr <= new_axireq & s_idle    ? buf_addr_t :\n                  ^~\n%Error: Exiting due to 11 warning(s)\n'
module simple_spi_top(
  input  wire       clk_i,         
  input  wire       rst_i,         
  input  wire       cyc_i,         
  input  wire       stb_i,         
  input  wire [3:0] adr_i,         
  input  wire       we_i,          
  input  wire [7:0] dat_i,         
  output reg  [7:0] dat_o,         
  output reg        ack_o,         
  output reg        inta_o,        

  output reg        sck_o,         
  output wire       mosi_o,        
  input  wire       miso_i,        

  output reg  [7:0] param,
  output reg  [7:0] param2,
  output reg  [7:0] softcs,
  output reg        busy
);

  reg  [7:0] spcr;       
  wire [7:0] spsr;       
  reg  [7:0] sper;       
  reg  [7:0] treg, rreg; 

  wire [7:0] rfdout;
  reg        wfre, rfwe;
  wire       rfre, rffull, rfempty;
  wire [7:0] wfdout;
  wire       wfwe, wffull, wfempty;

  wire      tirq;     
  wire      wfov;     
  reg [1:0] state;    
  reg [2:0] bcnt;

  wire wb_acc = cyc_i & stb_i;       
  wire wb_wr  = wb_acc & we_i;       

  always @(posedge clk_i)
    if (~rst_i)
      begin
          spcr <= 8'h12;  
          sper <= 8'h00;
          `ifdef FAST_SIMU
          param<= 8'h1;  
          param2<=8'h07;  
          `else
          param<= 8'h1;   
          param2<=8'h03;  
          `endif
          softcs<=8'hf0;  
      end
    else if (wb_wr)
      begin
        if (adr_i == 4'b00)
          spcr <= dat_i | 8'h10; 

        if (adr_i == 4'b11)
          sper <= dat_i;

        if (adr_i == 4'b0100)
          param <= dat_i;
        if (adr_i == 4'b0101)
          softcs<= dat_i;
        if (adr_i == 4'b0110)
          param2 <= dat_i;
      end

  assign wfwe = wb_acc & (adr_i == 4'b10) & ack_o &  we_i;
  assign wfov = wfwe & wffull;

  always @(*) 
    case(adr_i)
      4'b0000: dat_o = spcr;
      4'b0001: dat_o = spsr;
      4'b0010: dat_o = rfdout;
      4'b0011: dat_o = sper;
      4'b0100: dat_o = param;
      4'b0101: dat_o = softcs;
      4'b0110: dat_o = param2;
      default  dat_o = 8'h0;
    endcase

  assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i;

  always @(posedge clk_i)
    ack_o <= 1'b1;

  wire       spie = spcr[7];   
  wire       spe  = spcr[6];   
  wire       dwom = spcr[5];   
  wire       mstr = spcr[4];   
  wire       cpol = spcr[3];   
  wire       cpha = spcr[2];   
  wire [1:0] spr  = spcr[1:0]; 

  wire [1:0] icnt = sper[7:6]; 
  wire [1:0] spre = sper[1:0]; 
  wire     smh_spi= sper[2]; 

  wire [3:0] espr = {spre, spr};

  wire wr_spsr = wb_wr & (adr_i == 2'b01);

  reg spif;
  always @(posedge clk_i)
    if (~spe)
      spif <= 1'b0;
    else
      spif <= (tirq | spif) & ~(wr_spsr & dat_i[7]);

  reg wcol;
  always @(posedge clk_i)
    if (~spe)
      wcol <= 1'b0;
    else
      wcol <= (wfov | wcol) & ~(wr_spsr & dat_i[6]);

  assign spsr[7]   = spif;
  assign spsr[6]   = wcol;
  assign spsr[5:4] = 2'b00;
  assign spsr[3]   = wffull;
  assign spsr[2]   = wfempty;
  assign spsr[1]   = rffull;
  assign spsr[0]   = rfempty;
  

  always @(posedge clk_i)
    inta_o <= spif & spie;

  spi_fifo4 #(8)
  rfifo(
        .clk   ( clk_i   ),
        .rst   ( rst_i   ),
        .clr   ( ~spe    ),
        .din   ( treg    ),
        .we    ( rfwe    ),
        .dout  ( rfdout  ),
        .re    ( rfre    ),
        .full  ( rffull  ),
        .empty ( rfempty )
  ),
  wfifo(
        .clk   ( clk_i   ),
        .rst   ( rst_i   ),
        .clr   ( ~spe    ),
        .din   ( dat_i   ),
        .we    ( wfwe    ),
        .dout  ( wfdout  ),
        .re    ( wfre    ),
        .full  ( wffull  ),
        .empty ( wfempty )
  );

  reg [11:0] clkcnt;
  always @(posedge clk_i)
    if(spe & (|clkcnt & |state))
      clkcnt <= clkcnt - 11'h1;
    else
      case (espr)
        4'b0000: clkcnt <= 12'h0;   
        4'b0001: clkcnt <= 12'h1;   
        4'b0010: clkcnt <= 12'h7;   
        4'b0011: clkcnt <= 12'hf;   
        4'b0100: clkcnt <= 12'h3;   
        4'b0101: clkcnt <= 12'h1f;  
        4'b0110: clkcnt <= 12'h3f;  
        4'b0111: clkcnt <= 12'h7f;  
        4'b1000: clkcnt <= 12'hff;  
        4'b1001: clkcnt <= 12'h1ff; 
        4'b1010: clkcnt <= 12'h3ff; 
        4'b1011: clkcnt <= 12'h7ff; 
        default:;
      endcase

  wire ena = ~|clkcnt;
  reg sample;
  always @(posedge clk_i)
    if (~spe)
      begin
          state <= 2'b00; 
          bcnt  <= 3'h0;
          treg  <= 8'h00;
          wfre  <= 1'b0;
          rfwe  <= 1'b0;
          sck_o <= 1'b0;
      end
    else if (smh_spi)
      begin
         wfre <= 1'b0;
         rfwe <= 1'b0;

         case (state)
           2'b00: 
              begin
                  bcnt  <= 3'h7;   
                  treg  <= wfdout; 
                  sck_o <= cpol;   

                  if (~wfempty) begin
                    wfre  <= 1'b1;
                    state <= 2'b01;
                  end
              end

           2'b01: 
              if (ena) begin
                sck_o   <= ~sck_o; 
                state   <= 2'b10;
                if (cpha==0) sample <= miso_i;
              end

           2'b10: 
              if (ena) begin
                sck_o <= ~sck_o;
                state <= 2'b11;
                if (cpha==0) begin
                   treg   <= {treg[6:0], sample};
                end else begin
                   sample <= miso_i;
                end
              end

           2'b11: 
              if (ena) begin
                bcnt <= bcnt -3'h1;
                if (cpha==0) begin
                   sample <= miso_i;
                end else begin
                   treg   <= {treg[6:0], sample};
                end

                if (~|bcnt) begin
                  state <= 2'b00;
                  sck_o <= cpol;
                  rfwe  <= 1'b1;
                end else begin
                  state <= 2'b10;
                  sck_o <= ~sck_o;
                end

              end

         endcase
      end
    else
    begin
        wfre <= 1'b0;
        rfwe <= 1'b0;

        case (state)
        2'b00: 
        begin
            bcnt  <= 3'h7;   
            treg  <= wfdout; 
            sck_o <= cpol;   

            if (~wfempty) begin
                wfre  <= 1'b1;
                state <= 2'b01;
                if (cpha) sck_o <= ~sck_o;
            end
        end

        2'b01: 
        if (ena) begin
            sck_o <= ~sck_o;
            state <= 2'b11;
        end

        2'b11: 
        if (ena) begin
            treg <= {treg[6:0], miso_i};
            bcnt <= bcnt -3'h1;

            if (~|bcnt) begin
                state <= 2'b00;
                sck_o <= cpol;
                rfwe  <= 1'b1;
            end
            else begin
                state <= 2'b01;
                sck_o <= ~sck_o;
            end
        end

        2'b10: state <= 2'b00;
        default: state <=2'b00;
        endcase
    end

  assign mosi_o = treg[7];

  reg [1:0] tcnt; 
  always @(posedge clk_i)
    if (~spe)
      tcnt <= icnt;
    else if (rfwe) begin
      if (|tcnt)
        tcnt <= tcnt - 2'h1;
      else
        tcnt <= icnt;
    end

  assign tirq = ~|tcnt & rfwe;

  always @(posedge clk_i)
    busy <= ~wfempty | (|state);
endmodule
module simple_spi_top(
  input  wire       clk_i,         
  input  wire       rst_i,         
  input  wire       cyc_i,         
  input  wire       stb_i,         
  input  wire [3:0] adr_i,         
  input  wire       we_i,          
  input  wire [7:0] dat_i,         
  output reg  [7:0] dat_o,         
  output reg        ack_o,         
  output reg        inta_o,        

  output reg        sck_o,         
  output wire       mosi_o,        
  input  wire       miso_i,        

  output reg  [7:0] param,
  output reg  [7:0] param2,
  output reg  [7:0] softcs,
  output reg        busy
);


  reg  [7:0] spcr;       
  wire [7:0] spsr;       
  reg  [7:0] sper;       
  reg  [7:0] treg, rreg; 

  wire [7:0] rfdout;
  reg        wfre, rfwe;
  wire       rfre, rffull, rfempty;
  wire [7:0] wfdout;
  wire       wfwe, wffull, wfempty;

  wire      tirq;     
  wire      wfov;     
  reg [1:0] state;    
  reg [2:0] bcnt;

  wire wb_acc = cyc_i & stb_i;       
  wire wb_wr  = wb_acc & we_i;       

  always @(posedge clk_i)
    if (~rst_i)
      begin
          spcr <= 8'h12;  
          sper <= 8'h00;
          `ifdef FAST_SIMU
          param<= 8'h1;  
          param2<=8'h07;  
          `else
          param<= 8'h1;   
          param2<=8'h03;  
          `endif
          softcs<=8'hf0;  
      end
    else if (wb_wr)
      begin
        if (adr_i == 4'b00)
          spcr <= dat_i | 8'h10; 

        if (adr_i == 4'b11)
          sper <= dat_i;

        if (adr_i == 4'b0100)
          param <= dat_i;
        if (adr_i == 4'b0101)
          softcs<= dat_i;
        if (adr_i == 4'b0110)
          param2 <= dat_i;
      end

  assign wfwe = wb_acc & (adr_i == 4'b10) & ack_o &  we_i;
  assign wfov = wfwe & wffull;

  always @(*) 
    case(adr_i)
      4'b0000: dat_o = spcr;
      4'b0001: dat_o = spsr;
      4'b0010: dat_o = rfdout;
      4'b0011: dat_o = sper;
      4'b0100: dat_o = param;
      4'b0101: dat_o = softcs;
      4'b0110: dat_o = param2;
      default  dat_o = 8'h0;
    endcase

  assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i;

  always @(posedge clk_i)
    ack_o <= 1'b1;

  wire       spie = spcr[7];   
  wire       spe  = spcr[6];   
  wire       dwom = spcr[5];   
  wire       mstr = spcr[4];   
  wire       cpol = spcr[3];   
  wire       cpha = spcr[2];   
  wire [1:0] spr  = spcr[1:0]; 

  wire [1:0] icnt = sper[7:6]; 
  wire [1:0] spre = sper[1:0]; 
  wire     smh_spi= sper[2]; 

  wire [3:0] espr = {spre, spr};

  wire wr_spsr = wb_wr & (adr_i == 2'b01);

  reg spif;
  always @(posedge clk_i)
    if (~spe)
      spif <= 1'b0;
    else
      spif <= (tirq | spif) & ~(wr_spsr & dat_i[7]);

  reg wcol;
  always @(posedge clk_i)
    if (~spe)
      wcol <= 1'b0;
    else
      wcol <= (wfov | wcol) & ~(wr_spsr & dat_i[6]);

  assign spsr[7]   = spif;
  assign spsr[6]   = wcol;
  assign spsr[5:4] = 2'b00;
  assign spsr[3]   = wffull;
  assign spsr[2]   = wfempty;
  assign spsr[1]   = rffull;
  assign spsr[0]   = rfempty;
  

  always @(posedge clk_i)
    inta_o <= spif & spie;

  spi_fifo4 #(8)
  rfifo(
        .clk   ( clk_i   ),
        .rst   ( rst_i   ),
        .clr   ( ~spe    ),
        .din   ( treg    ),
        .we    ( rfwe    ),
        .dout  ( rfdout  ),
        .re    ( rfre    ),
        .full  ( rffull  ),
        .empty ( rfempty )
  ),
  wfifo(
        .clk   ( clk_i   ),
        .rst   ( rst_i   ),
        .clr   ( ~spe    ),
        .din   ( dat_i   ),
        .we    ( wfwe    ),
        .dout  ( wfdout  ),
        .re    ( wfre    ),
        .full  ( wffull  ),
        .empty ( wfempty )
  );

  reg [11:0] clkcnt;
  always @(posedge clk_i)
    if(spe & (|clkcnt & |state))
      clkcnt <= clkcnt - 11'h1;
    else
      case (espr)
        4'b0000: clkcnt <= 12'h0;   
        4'b0001: clkcnt <= 12'h1;   
        4'b0010: clkcnt <= 12'h7;   
        4'b0011: clkcnt <= 12'hf;   
        4'b0100: clkcnt <= 12'h3;   
        4'b0101: clkcnt <= 12'h1f;  
        4'b0110: clkcnt <= 12'h3f;  
        4'b0111: clkcnt <= 12'h7f;  
        4'b1000: clkcnt <= 12'hff;  
        4'b1001: clkcnt <= 12'h1ff; 
        4'b1010: clkcnt <= 12'h3ff; 
        4'b1011: clkcnt <= 12'h7ff; 
        default:;
      endcase

  wire ena = ~|clkcnt;
  reg sample;
  always @(posedge clk_i)
    if (~spe)
      begin
          state <= 2'b00; 
          bcnt  <= 3'h0;
          treg  <= 8'h00;
          wfre  <= 1'b0;
          rfwe  <= 1'b0;
          sck_o <= 1'b0;
      end
    else if (smh_spi)
      begin
         wfre <= 1'b0;
         rfwe <= 1'b0;

         case (state)
           2'b00: 
              begin
                  bcnt  <= 3'h7;   
                  treg  <= wfdout; 
                  sck_o <= cpol;   

                  if (~wfempty) begin
                    wfre  <= 1'b1;
                    state <= 2'b01;
                  end
              end

           2'b01: 
              if (ena) begin
                sck_o   <= ~sck_o; 
                state   <= 2'b10;
                if (cpha==0) sample <= miso_i;
              end

           2'b10: 
              if (ena) begin
                sck_o <= ~sck_o;
                state <= 2'b11;
                if (cpha==0) begin
                   treg   <= {treg[6:0], sample};
                end else begin
                   sample <= miso_i;
                end
              end

           2'b11: 
              if (ena) begin
                bcnt <= bcnt -3'h1;
                if (cpha==0) begin
                   sample <= miso_i;
                end else begin
                   treg   <= {treg[6:0], sample};
                end

                if (~|bcnt) begin
                  state <= 2'b00;
                  sck_o <= cpol;
                  rfwe  <= 1'b1;
                end else begin
                  state <= 2'b10;
                  sck_o <= ~sck_o;
                end

              end

         endcase
      end
    else
    begin
        wfre <= 1'b0;
        rfwe <= 1'b0;

        case (state)
        2'b00: 
        begin
            bcnt  <= 3'h7;   
            treg  <= wfdout; 
            sck_o <= cpol;   

            if (~wfempty) begin
                wfre  <= 1'b1;
                state <= 2'b01;
                if (cpha) sck_o <= ~sck_o;
            end
        end

        2'b01: 
        if (ena) begin
            sck_o <= ~sck_o;
            state <= 2'b11;
        end

        2'b11: 
        if (ena) begin
            treg <= {treg[6:0], miso_i};
            bcnt <= bcnt -3'h1;

            if (~|bcnt) begin
                state <= 2'b00;
                sck_o <= cpol;
                rfwe  <= 1'b1;
            end
            else begin
                state <= 2'b01;
                sck_o <= ~sck_o;
            end
        end

        2'b10: state <= 2'b00;
        default: state <=2'b00;
        endcase
    end

  assign mosi_o = treg[7];

  reg [1:0] tcnt; 
  always @(posedge clk_i)
    if (~spe)
      tcnt <= icnt;
    else if (rfwe) begin
      if (|tcnt)
        tcnt <= tcnt - 2'h1;
      else
        tcnt <= icnt;
    end

  assign tirq = ~|tcnt & rfwe;

  always @(posedge clk_i)
    busy <= ~wfempty | (|state);
endmodule