data/full_repos/permissive/125927162/PLCOUNTER/plcounter.v
data/verilator_xmls/c09e62ed-0068-46d4-93bf-42f4bce95e43.xml
module plcounter (clk, rst, updown, out, in);
   parameter WIDTH = 8;
   input clk;
   input rst;
   input updown;
   input [WIDTH-1:0] in;
   output reg [WIDTH-1:0] out;

   always@(posedge clk) begin
      if (rst)
	out <= in;
      else begin
	 if (updown)
	   out <= out + 1;
	 else
	   out <= out - 1;
      end
   end
endmodule
module plcounter (clk, rst, updown, out, in);

   parameter WIDTH = 8;
   input clk;
   input rst;
   input updown;
   input [WIDTH-1:0] in;
   output reg [WIDTH-1:0] out;

   always@(posedge clk) begin
      if (rst)
	out <= in;
      else begin
	 if (updown)
	   out <= out + 1;
	 else
	   out <= out - 1;
      end
   end
endmodule