data/full_repos/permissive/174263347/crtv10/hdl/crt_syncsinv.v
1: b"%Error: data/full_repos/permissive/174263347/crtv10/hdl/crt_syncsinv.v:37: Cannot find file containing module: 'onefextractor'\n    onefextractor hsig_obj( clk, reset, 1'b1, hsync, hris);\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/onefextractor\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/onefextractor.v\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/onefextractor.sv\n             onefextractor\n             onefextractor.v\n             onefextractor.sv\n             obj_dir/onefextractor\n             obj_dir/onefextractor.v\n             obj_dir/onefextractor.sv\n%Error: Exiting due to 1 error(s)\n"
module crt_syncsinv(clk, reset, onemks, hsync, vsync, csync);

    input           clk, reset, onemks;
    input           hsync, vsync;
    output          csync;

    reg     [3:0]   hcnt, vcnt;

    always @ (posedge reset or posedge clk)
        if (reset)
            hcnt <= 4'b1000;
        else if(onemks)
        begin
            if (hsync)
            begin
                if(hcnt != 4'b1111)
                    hcnt <= hcnt + 1;
            end
            else
            begin
                if(hcnt != 4'b0000)
                    hcnt <= hcnt - 1;
            end
        end

    wire    hris;

    onefextractor hsig_obj( clk, reset, 1'b1, hsync, hris);

    always @ (posedge reset or posedge clk)
        if (reset)
            vcnt <= 4'b1000;
        else if(hris)
        begin
            if (vsync)
            begin
                if(vcnt != 4'b1111)
                    vcnt <= vcnt + 1;
            end
            else
            begin
                if(vcnt != 4'b0000)
                    vcnt <= vcnt - 1;
            end
        end

    assign   csync = (hsync ^ hcnt[3]) ^ (vsync ^ vcnt[3]);
endmodule
module crt_syncsinv(clk, reset, onemks, hsync, vsync, csync);


    input           clk, reset, onemks;
    input           hsync, vsync;
    output          csync;

    reg     [3:0]   hcnt, vcnt;

    always @ (posedge reset or posedge clk)
        if (reset)
            hcnt <= 4'b1000;
        else if(onemks)
        begin
            if (hsync)
            begin
                if(hcnt != 4'b1111)
                    hcnt <= hcnt + 1;
            end
            else
            begin
                if(hcnt != 4'b0000)
                    hcnt <= hcnt - 1;
            end
        end

    wire    hris;

    onefextractor hsig_obj( clk, reset, 1'b1, hsync, hris);

    always @ (posedge reset or posedge clk)
        if (reset)
            vcnt <= 4'b1000;
        else if(hris)
        begin
            if (vsync)
            begin
                if(vcnt != 4'b1111)
                    vcnt <= vcnt + 1;
            end
            else
            begin
                if(vcnt != 4'b0000)
                    vcnt <= vcnt - 1;
            end
        end

    assign   csync = (hsync ^ hcnt[3]) ^ (vsync ^ vcnt[3]);
endmodule