data/full_repos/permissive/115837888/source-7400/74147-tb.v
 line:5: before: "tbassert"
1: b'%Error: data/full_repos/permissive/115837888/source-7400/74147-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74147-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74147-tb.v:24: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("74147-tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74147-tb.v:25: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74147-tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: Exiting due to 4 error(s), 36 warning(s)\n'
module test;

`TBASSERT_METHOD(tbassert)

localparam WIDTH_IN = 9;
localparam WIDTH_OUT = 4;


reg [WIDTH_IN-1:0] A_bar;


wire [WIDTH_OUT-1:0] Y_bar;


ttl_74147 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .A_bar(A_bar),
  .Y_bar(Y_bar)
);

initial
begin
  $dumpfile("74147-tb.vcd");
  $dumpvars;


  A_bar = 9'b000000000;
#6
  tbassert(Y_bar == ~4'b1001, "Test 1");
#0

  A_bar = 9'b111111111;
#6
  tbassert(Y_bar == ~4'b0000, "Test 2");
#0

  A_bar = 9'b111011111;
#6
  tbassert(Y_bar == ~4'b0110, "Test 3");
#0

  A_bar = 9'b111010101;
#6
  tbassert(Y_bar == ~4'b0110, "Test 4");
#0

  A_bar = 9'b111110101;
#6
  tbassert(Y_bar == ~4'b0100, "Test 5");
#0

  A_bar = 9'b111111110;
#6
  tbassert(Y_bar == ~4'b0001, "Test 6");
#0

  A_bar = 9'b101111110;
#6
  tbassert(Y_bar == ~4'b1000, "Test 7");
#0

  A_bar = 9'b010000001;
#6
  tbassert(Y_bar == ~4'b1001, "Test 8");
#0

  A_bar = 9'b011111111;
#6
  tbassert(Y_bar == ~4'b1001, "Test 9");
#0

  A_bar = 9'b110101100;
#6
  tbassert(Y_bar == ~4'b0111, "Test 10");
#0
  A_bar = 9'b110000111;
#6
  tbassert(Y_bar == ~4'b0111, "Test 10");
#0

  A_bar = 9'b111111111;
#6
  tbassert(Y_bar == ~4'b0000, "Test 11");
#0
  A_bar = 9'b111000110;
#6
  tbassert(Y_bar == ~4'b0110, "Test 11");
#0

  A_bar = 9'b111111111;
#6
  tbassert(Y_bar == ~4'b0000, "Test 12");
#0

  A_bar = 9'b011111111;
#6
  tbassert(Y_bar == ~4'b1001, "Test 13");
#0











  A_bar = 9'b0zz0zz000;
#6
  tbassert(Y_bar == ~4'b1001, "Test 14");
#0

  A_bar = 9'b1110z01zz;
#6
  tbassert(Y_bar == ~4'b0110, "Test 15");
#0

  A_bar = 9'b11111110z;
#6
  tbassert(Y_bar == ~4'b0010, "Test 16");
#10
  $finish;
end

endmodule
module test;


`TBASSERT_METHOD(tbassert)

localparam WIDTH_IN = 9;
localparam WIDTH_OUT = 4;


reg [WIDTH_IN-1:0] A_bar;


wire [WIDTH_OUT-1:0] Y_bar;


ttl_74147 #(.DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .A_bar(A_bar),
  .Y_bar(Y_bar)
);

initial
begin
  $dumpfile("74147-tb.vcd");
  $dumpvars;


  A_bar = 9'b000000000;
#6
  tbassert(Y_bar == ~4'b1001, "Test 1");
#0

  A_bar = 9'b111111111;
#6
  tbassert(Y_bar == ~4'b0000, "Test 2");
#0

  A_bar = 9'b111011111;
#6
  tbassert(Y_bar == ~4'b0110, "Test 3");
#0

  A_bar = 9'b111010101;
#6
  tbassert(Y_bar == ~4'b0110, "Test 4");
#0

  A_bar = 9'b111110101;
#6
  tbassert(Y_bar == ~4'b0100, "Test 5");
#0

  A_bar = 9'b111111110;
#6
  tbassert(Y_bar == ~4'b0001, "Test 6");
#0

  A_bar = 9'b101111110;
#6
  tbassert(Y_bar == ~4'b1000, "Test 7");
#0

  A_bar = 9'b010000001;
#6
  tbassert(Y_bar == ~4'b1001, "Test 8");
#0

  A_bar = 9'b011111111;
#6
  tbassert(Y_bar == ~4'b1001, "Test 9");
#0

  A_bar = 9'b110101100;
#6
  tbassert(Y_bar == ~4'b0111, "Test 10");
#0
  A_bar = 9'b110000111;
#6
  tbassert(Y_bar == ~4'b0111, "Test 10");
#0

  A_bar = 9'b111111111;
#6
  tbassert(Y_bar == ~4'b0000, "Test 11");
#0
  A_bar = 9'b111000110;
#6
  tbassert(Y_bar == ~4'b0110, "Test 11");
#0

  A_bar = 9'b111111111;
#6
  tbassert(Y_bar == ~4'b0000, "Test 12");
#0

  A_bar = 9'b011111111;
#6
  tbassert(Y_bar == ~4'b1001, "Test 13");
#0











  A_bar = 9'b0zz0zz000;
#6
  tbassert(Y_bar == ~4'b1001, "Test 14");
#0

  A_bar = 9'b1110z01zz;
#6
  tbassert(Y_bar == ~4'b0110, "Test 15");
#0

  A_bar = 9'b11111110z;
#6
  tbassert(Y_bar == ~4'b0010, "Test 16");
#10
  $finish;
end

endmodule