data/full_repos/permissive/107057345/7 Seg Display Synthesized/Design Task 2 synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v
1: b'%Error: Cannot find file containing module: Seg\n        ... Looked in:\n             data/full_repos/permissive/107057345/7/Seg\n             data/full_repos/permissive/107057345/7/Seg.v\n             data/full_repos/permissive/107057345/7/Seg.sv\n             Seg\n             Seg.v\n             Seg.sv\n             obj_dir/Seg\n             obj_dir/Seg.v\n             obj_dir/Seg.sv\n%Error: Cannot find file containing module: Display\n%Error: Cannot find file containing module: Synthesized/Design\n%Error: Cannot find file containing module: Task\n%Error: Cannot find file containing module: 2\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop,data/full_repos/permissive/107057345\n%Error: Cannot find file containing module: data/full_repos/permissive/107057345/7\n%Error: Cannot find file containing module: synthesized.srcs/sources_1/imports/imports/Desktop/dassign2.v\n%Error: Exiting due to 8 error(s)\n'
module Buttons(input [15:0] sw,
 input left, 
 input right, 
 input up, 
 input down, 
 output[15:0] x,
 output led
  );

reg sub;
reg[15:0] wdinA, wdinB;
wire[15:0] inputA, inputB;
wire subt;
assign inputA = wdinA;
assign inputB = wdinB;
assign subt = sub; 

dassign2 u2(
 .wdinA(inputA),
 .wdinB(inputB),
 .sub(subt),
  .wdout(x), 
  .ovunflow(led)
  );

always @(left or right or up or down or sw) begin
if(left == 1)
    begin
    wdinA = sw;
    end
else if (right == 1)
    begin
    wdinB = sw;
    end
else if(down == 1)
    begin 
    sub = 1;
    end
else if(up == 1)
    begin
    sub = 0;
    end
else
begin
    wdinA = wdinA;
    wdinB = wdinB;
end
end
endmodule
module Buttons(input [15:0] sw,
 input left, 
 input right, 
 input up, 
 input down, 
 output[15:0] x,
 output led
  );


reg sub;
reg[15:0] wdinA, wdinB;
wire[15:0] inputA, inputB;
wire subt;
assign inputA = wdinA;
assign inputB = wdinB;
assign subt = sub; 

dassign2 u2(
 .wdinA(inputA),
 .wdinB(inputB),
 .sub(subt),
  .wdout(x), 
  .ovunflow(led)
  );

always @(left or right or up or down or sw) begin
if(left == 1)
    begin
    wdinA = sw;
    end
else if (right == 1)
    begin
    wdinB = sw;
    end
else if(down == 1)
    begin 
    sub = 1;
    end
else if(up == 1)
    begin
    sub = 0;
    end
else
begin
    wdinA = wdinA;
    wdinB = wdinB;
end
end
endmodule