data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:15: Cannot find include file: sim_exec_report.vh\n`include "sim_exec_report.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker,data/full_repos/permissive/214858095/sim_exec_report.vh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker,data/full_repos/permissive/214858095/sim_exec_report.vh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker,data/full_repos/permissive/214858095/sim_exec_report.vh.sv\n             sim_exec_report.vh\n             sim_exec_report.vh.v\n             sim_exec_report.vh.sv\n             obj_dir/sim_exec_report.vh\n             obj_dir/sim_exec_report.vh.v\n             obj_dir/sim_exec_report.vh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:19: Define or directive not defined: \'`TEST_BENCH_INIT\'\n   `TEST_BENCH_INIT("chdr_dechunker_tb", 8, 1)\n   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:19: syntax error, unexpected \'(\'\n   `TEST_BENCH_INIT("chdr_dechunker_tb", 8, 1)\n                    ^~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:43: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:45: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("chdr_dechunker_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:46: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,chdr_dechunker_tb);\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:66: Define or directive not defined: \'`ASSERT_ERROR\'\n            `ASSERT_ERROR(0, "Result did not match expected value");\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:66: syntax error, unexpected \',\'\n            `ASSERT_ERROR(0, "Result did not match expected value");\n                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:85: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:90: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:93: syntax error, unexpected \'@\'\n               @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:97: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:108: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:110: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:116: Unsupported: Ignoring delay on this delayed statement.\n      #100 reset = 0;\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:122: syntax error, unexpected \'@\'\n      while(reset) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:124: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                       : ... Suggested alternative: \'`SV_COV_START\'\n      `TEST_CASE_START("Running test case: First packet after reset");\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:124: syntax error, unexpected \';\'\n      `TEST_CASE_START("Running test case: First packet after reset");\n                                                                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:126: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:128: Define or directive not defined: \'`TEST_CASE_DONE\'\n      `TEST_CASE_DONE(result);\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:128: syntax error, unexpected \';\'\n      `TEST_CASE_DONE(result);\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:132: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                       : ... Suggested alternative: \'`SV_COV_START\'\n      `TEST_CASE_START("Running test case: sizeof(packet) < quantum");\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:132: syntax error, unexpected \';\'\n      `TEST_CASE_START("Running test case: sizeof(packet) < quantum");\n                                                                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:134: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:136: Define or directive not defined: \'`TEST_CASE_DONE\'\n      `TEST_CASE_DONE(result);\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:136: syntax error, unexpected \';\'\n      `TEST_CASE_DONE(result);\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:138: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                       : ... Suggested alternative: \'`SV_COV_START\'\n      `TEST_CASE_START("Running test case: sizeof(packet) == quantum");\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:138: syntax error, unexpected \';\'\n      `TEST_CASE_START("Running test case: sizeof(packet) == quantum");\n                                                                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:140: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:142: Define or directive not defined: \'`TEST_CASE_DONE\'\n      `TEST_CASE_DONE(result);\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:142: syntax error, unexpected \';\'\n      `TEST_CASE_DONE(result);\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:144: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                       : ... Suggested alternative: \'`SV_COV_START\'\n      `TEST_CASE_START("Running test case: sizeof(packet) == quantum - 64bits");\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:144: syntax error, unexpected \';\'\n      `TEST_CASE_START("Running test case: sizeof(packet) == quantum - 64bits");\n                                                                               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:146: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:148: Define or directive not defined: \'`TEST_CASE_DONE\'\n      `TEST_CASE_DONE(result);\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:148: syntax error, unexpected \';\'\n      `TEST_CASE_DONE(result);\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:150: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                       : ... Suggested alternative: \'`SV_COV_START\'\n      `TEST_CASE_START("Running test case: sizeof(packet) == quantum + 64bits");\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:150: syntax error, unexpected \';\'\n      `TEST_CASE_START("Running test case: sizeof(packet) == quantum + 64bits");\n                                                                               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:152: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:154: Define or directive not defined: \'`TEST_CASE_DONE\'\n      `TEST_CASE_DONE(result);\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:154: syntax error, unexpected \';\'\n      `TEST_CASE_DONE(result);\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:158: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                       : ... Suggested alternative: \'`SV_COV_START\'\n      `TEST_CASE_START("Running test case: sizeof(packet) > quantum");\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:158: syntax error, unexpected \';\'\n      `TEST_CASE_START("Running test case: sizeof(packet) > quantum");\n                                                                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:160: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:162: Define or directive not defined: \'`TEST_CASE_DONE\'\n      `TEST_CASE_DONE(result);\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:162: syntax error, unexpected \';\'\n      `TEST_CASE_DONE(result);\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:166: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                       : ... Suggested alternative: \'`SV_COV_START\'\n      `TEST_CASE_START("Running test case: sizeof(packet) == 2");\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:166: syntax error, unexpected \';\'\n      `TEST_CASE_START("Running test case: sizeof(packet) == 2");\n                                                                ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:168: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:170: Define or directive not defined: \'`TEST_CASE_DONE\'\n      `TEST_CASE_DONE(result);\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:170: syntax error, unexpected \';\'\n      `TEST_CASE_DONE(result);\n                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv:172: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                                       : ... Suggested alternative: \'`SV_COV_START\'\n      `TEST_CASE_START("Running test case: Multiple packets");\n      ^~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module chdr_dechunker_tb();
   `TEST_BENCH_INIT("chdr_dechunker_tb", `NUM_TEST_CASES, `NS_PER_TICK)


   reg clk    = 0;
   reg reset  = 1;
   reg clear  = 0;
   reg [15:0] quantum;
   wire error;


   reg [31:0] o_xfer_count = 0, i_xfer_count = 0;
   reg [63:0] o_last_tdata = 0;

   reg [63:0]  i_tdata;
   reg         i_tlast;
   reg         i_tvalid;
   wire        i_tready;

   wire [63:0] o_tdata;
   wire        o_tlast, o_tvalid, o_tready;

   reg result;


   always #10 clk = ~clk;
   
   initial $dumpfile("chdr_dechunker_tb.vcd");
   initial $dumpvars(0,chdr_dechunker_tb);

   function check_result;
      input [31:0]   o_xfer_count_arg;
      input [31:0]   i_xfer_count_arg;
      input [63:0]   o_last_tdata_arg;
      input          error_arg;
      begin

         check_result = 1;
         check_result = check_result & ((o_xfer_count_arg == o_xfer_count) !== 0);
         check_result = check_result & ((i_xfer_count_arg == i_xfer_count) !== 0);
         check_result = check_result & ((o_last_tdata_arg == o_last_tdata) !== 0);
         check_result = check_result & ((error_arg == error) != 0);
         
         if (!check_result) begin
            $display ("o_xfer_count = %d (Expected %d)",o_xfer_count,o_xfer_count_arg);
            $display ("i_xfer_count = %d (Expected %d)",i_xfer_count,i_xfer_count_arg);
            $display ("o_last_tdata = %h (Expected %h)",o_last_tdata,o_last_tdata_arg);
            $display ("error = %d  (Expected %d)",error,error_arg);
            `ASSERT_ERROR(0, "Result did not match expected value");
         end


         o_xfer_count = 0;
         i_xfer_count = 0;
         o_last_tdata = 64'h0;
      end
   endfunction

   task send_packet;
      input [63:0] data_start;
      input [31:0] len;
      input [31:0] quant;
      
      begin
         if(quant < 2) begin
            {i_tlast, i_tdata} <= { 1'b1, data_start[63:32], len[15:0], data_start[15:0] };
            i_tvalid <= 1;
            @(posedge clk);
            i_tvalid <= 0;
         end else begin
            {i_tlast, i_tdata} <= { 1'b0, data_start[63:32], len[15:0], data_start[15:0] };
            i_tvalid <= 1;
            @(posedge clk);
            repeat(quant - 2) begin
               i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
               @(posedge clk);
            end
            i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
            i_tlast <= 1;
            @(posedge clk);
            i_tvalid <= 1'b0;
         end
      end
   endtask

   task reset_quantum_atomic;
      input [15:0] quant;
      begin
         quantum <= quant;
         clear <= 1;
         @(posedge clk);
         clear <= 0;
         @(posedge clk);
      end
   endtask


   initial begin
      #100 reset = 0;
   end
   
   initial begin
      quantum <= 8;
      i_tvalid <= 0;
      while(reset) @(posedge clk);

      `TEST_CASE_START("Running test case: First packet after reset");
      send_packet(64'h00000001_00000000, 32, 8);
      @(posedge clk);
      result = check_result(4,8,64'hxxxxxxxx_xxxxxx06, 0);
      `TEST_CASE_DONE(result);

      reset_quantum_atomic(10);

      `TEST_CASE_START("Running test case: sizeof(packet) < quantum");
      send_packet(64'h00000001_00000000, 64, 10);
      @(posedge clk);
      result = check_result(8,10,64'hxxxxxxxx_xxxxxx0e, 0);
      `TEST_CASE_DONE(result);

      `TEST_CASE_START("Running test case: sizeof(packet) == quantum");
      send_packet(64'h00000001_00000000, 80, 10);
      @(posedge clk);
      result = check_result(10,10,64'hxxxxxxxx_xxxxxx12, 0);
      `TEST_CASE_DONE(result);
      
      `TEST_CASE_START("Running test case: sizeof(packet) == quantum - 64bits");
      send_packet(64'h00000001_00000000, 72, 10);
      @(posedge clk);
      result = check_result(9,10,64'hxxxxxxxx_xxxxxx10, 0);
      `TEST_CASE_DONE(result);

      `TEST_CASE_START("Running test case: sizeof(packet) == quantum + 64bits");
      send_packet(64'h00000001_00000000, 88, 10);
      @(posedge clk);
      result = check_result(32'hxxxxxxxx,10,64'hxxxxxxxx_xxxxxxxx, 1);
      `TEST_CASE_DONE(result);

      reset_quantum_atomic(10);

      `TEST_CASE_START("Running test case: sizeof(packet) > quantum");
      send_packet(64'h00000001_00000000, 88, 10);
      @(posedge clk);
      result = check_result(32'hxxxxxxxx,10,64'hxxxxxxxx_xxxxxxxx, 1);
      `TEST_CASE_DONE(result);

      reset_quantum_atomic(8);

      `TEST_CASE_START("Running test case: sizeof(packet) == 2");
      send_packet(64'h00000001_00000000, 8, 8);
      @(posedge clk);
      result = check_result(1,8,64'hxxxxxxxx_xxxxxx00, 0);
      `TEST_CASE_DONE(result);

      `TEST_CASE_START("Running test case: Multiple packets");
      send_packet(64'h00000001_00000000, 8, 8);
      send_packet(64'h00000001_00000000, 16, 8);
      send_packet(64'h00000001_00000000, 24, 8);
      send_packet(64'h00000001_00000000, 32, 8);
      @(posedge clk);
      result = check_result(10,32,64'hxxxxxxxx_xxxxxx06, 0);
      `TEST_CASE_DONE(result);

      `TEST_BENCH_DONE;
   end


   chdr_dechunker dut (
      .clk(clk), .reset(reset), .clear(clear), .frame_size(quantum),
      .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
      .error(error));
      
   assign o_tready = 1;
  
   always @(posedge clk) begin
      if (o_tvalid & o_tready) begin
         o_xfer_count <= o_xfer_count + 1;
         o_last_tdata <= o_tdata;
      end
      if (i_tvalid & i_tready) i_xfer_count <= i_xfer_count + 1;
   end

endmodule
module chdr_dechunker_tb();

   `TEST_BENCH_INIT("chdr_dechunker_tb", `NUM_TEST_CASES, `NS_PER_TICK)


   reg clk    = 0;
   reg reset  = 1;
   reg clear  = 0;
   reg [15:0] quantum;
   wire error;


   reg [31:0] o_xfer_count = 0, i_xfer_count = 0;
   reg [63:0] o_last_tdata = 0;

   reg [63:0]  i_tdata;
   reg         i_tlast;
   reg         i_tvalid;
   wire        i_tready;

   wire [63:0] o_tdata;
   wire        o_tlast, o_tvalid, o_tready;

   reg result;


   always #10 clk = ~clk;
   
   initial $dumpfile("chdr_dechunker_tb.vcd");
   initial $dumpvars(0,chdr_dechunker_tb);

   function check_result;
      input [31:0]   o_xfer_count_arg;
      input [31:0]   i_xfer_count_arg;
      input [63:0]   o_last_tdata_arg;
      input          error_arg;
      begin

         check_result = 1;
         check_result = check_result & ((o_xfer_count_arg == o_xfer_count) !== 0);
         check_result = check_result & ((i_xfer_count_arg == i_xfer_count) !== 0);
         check_result = check_result & ((o_last_tdata_arg == o_last_tdata) !== 0);
         check_result = check_result & ((error_arg == error) != 0);
         
         if (!check_result) begin
            $display ("o_xfer_count = %d (Expected %d)",o_xfer_count,o_xfer_count_arg);
            $display ("i_xfer_count = %d (Expected %d)",i_xfer_count,i_xfer_count_arg);
            $display ("o_last_tdata = %h (Expected %h)",o_last_tdata,o_last_tdata_arg);
            $display ("error = %d  (Expected %d)",error,error_arg);
            `ASSERT_ERROR(0, "Result did not match expected value");
         end


         o_xfer_count = 0;
         i_xfer_count = 0;
         o_last_tdata = 64'h0;
      end
   endfunction

   task send_packet;
      input [63:0] data_start;
      input [31:0] len;
      input [31:0] quant;
      
      begin
         if(quant < 2) begin
            {i_tlast, i_tdata} <= { 1'b1, data_start[63:32], len[15:0], data_start[15:0] };
            i_tvalid <= 1;
            @(posedge clk);
            i_tvalid <= 0;
         end else begin
            {i_tlast, i_tdata} <= { 1'b0, data_start[63:32], len[15:0], data_start[15:0] };
            i_tvalid <= 1;
            @(posedge clk);
            repeat(quant - 2) begin
               i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
               @(posedge clk);
            end
            i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
            i_tlast <= 1;
            @(posedge clk);
            i_tvalid <= 1'b0;
         end
      end
   endtask

   task reset_quantum_atomic;
      input [15:0] quant;
      begin
         quantum <= quant;
         clear <= 1;
         @(posedge clk);
         clear <= 0;
         @(posedge clk);
      end
   endtask


   initial begin
      #100 reset = 0;
   end
   
   initial begin
      quantum <= 8;
      i_tvalid <= 0;
      while(reset) @(posedge clk);

      `TEST_CASE_START("Running test case: First packet after reset");
      send_packet(64'h00000001_00000000, 32, 8);
      @(posedge clk);
      result = check_result(4,8,64'hxxxxxxxx_xxxxxx06, 0);
      `TEST_CASE_DONE(result);

      reset_quantum_atomic(10);

      `TEST_CASE_START("Running test case: sizeof(packet) < quantum");
      send_packet(64'h00000001_00000000, 64, 10);
      @(posedge clk);
      result = check_result(8,10,64'hxxxxxxxx_xxxxxx0e, 0);
      `TEST_CASE_DONE(result);

      `TEST_CASE_START("Running test case: sizeof(packet) == quantum");
      send_packet(64'h00000001_00000000, 80, 10);
      @(posedge clk);
      result = check_result(10,10,64'hxxxxxxxx_xxxxxx12, 0);
      `TEST_CASE_DONE(result);
      
      `TEST_CASE_START("Running test case: sizeof(packet) == quantum - 64bits");
      send_packet(64'h00000001_00000000, 72, 10);
      @(posedge clk);
      result = check_result(9,10,64'hxxxxxxxx_xxxxxx10, 0);
      `TEST_CASE_DONE(result);

      `TEST_CASE_START("Running test case: sizeof(packet) == quantum + 64bits");
      send_packet(64'h00000001_00000000, 88, 10);
      @(posedge clk);
      result = check_result(32'hxxxxxxxx,10,64'hxxxxxxxx_xxxxxxxx, 1);
      `TEST_CASE_DONE(result);

      reset_quantum_atomic(10);

      `TEST_CASE_START("Running test case: sizeof(packet) > quantum");
      send_packet(64'h00000001_00000000, 88, 10);
      @(posedge clk);
      result = check_result(32'hxxxxxxxx,10,64'hxxxxxxxx_xxxxxxxx, 1);
      `TEST_CASE_DONE(result);

      reset_quantum_atomic(8);

      `TEST_CASE_START("Running test case: sizeof(packet) == 2");
      send_packet(64'h00000001_00000000, 8, 8);
      @(posedge clk);
      result = check_result(1,8,64'hxxxxxxxx_xxxxxx00, 0);
      `TEST_CASE_DONE(result);

      `TEST_CASE_START("Running test case: Multiple packets");
      send_packet(64'h00000001_00000000, 8, 8);
      send_packet(64'h00000001_00000000, 16, 8);
      send_packet(64'h00000001_00000000, 24, 8);
      send_packet(64'h00000001_00000000, 32, 8);
      @(posedge clk);
      result = check_result(10,32,64'hxxxxxxxx_xxxxxx06, 0);
      `TEST_CASE_DONE(result);

      `TEST_BENCH_DONE;
   end


   chdr_dechunker dut (
      .clk(clk), .reset(reset), .clear(clear), .frame_size(quantum),
      .i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
      .error(error));
      
   assign o_tready = 1;
  
   always @(posedge clk) begin
      if (o_tvalid & o_tready) begin
         o_xfer_count <= o_xfer_count + 1;
         o_last_tdata <= o_tdata;
      end
      if (i_tvalid & i_tready) i_xfer_count <= i_xfer_count + 1;
   end

endmodule