data/full_repos/permissive/173670949/abcd-serial/top.v
1: b'%Error: data/full_repos/permissive/173670949/abcd-serial/top.v:18: Cannot find file containing module: \'pll\'\n    pll PLL_50MHz(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/173670949/abcd-serial,data/full_repos/permissive/173670949/pll\n             data/full_repos/permissive/173670949/abcd-serial,data/full_repos/permissive/173670949/pll.v\n             data/full_repos/permissive/173670949/abcd-serial,data/full_repos/permissive/173670949/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/173670949/abcd-serial/top.v:31: Cannot find file containing module: \'uart_tx2\'\n    uart_tx2 #(\n    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/173670949/abcd-serial/top.v:60: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'posoff\' generates 7 bits.\n                                                                         : ... In instance top\n            if (posoff == "z" - "1")  \n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module top (
    input  ICE_CLK,
    input  UART_RX,
    output UART_TX,
    output RLED1,
    output RLED2,
    output RLED3,
    output RLED4,
    output GLED5,
    output OUT106
);

    wire pll_clk_50m;
    wire pll_locked;
    pll PLL_50MHz(
        .clock_in(ICE_CLK),
        .clock_out(pll_clk_50m),
        .locked(pll_locked)
    );


    wire       tx_dv;
    reg  [7:0] tx_byte;
    wire       tx_done;

    assign tx_dv = tx_done;

    uart_tx2 #(
        .F_CLK(50_000_000),
        .UART_BAUD(921600)
    )
    tx (
        .CLK(pll_clk_50m),
        .TX_DV(tx_dv),
        .TX_BYTE(tx_byte),
        .TX_DATA(UART_TX),
        .DONE(tx_done)
    );

    wire [3:0] leds = {RLED1, RLED2, RLED3, RLED4};
    assign leds = tx_byte[6:3];

    assign GLED5 = pll_locked;
    assign OUT106 = !UART_TX;


    reg [6:0] posoff = 0;
    parameter START = "0";


    always @(posedge tx_done) begin

        if (tx_byte > START + posoff) begin
            tx_byte <= "\n";


            if (posoff == "z" - "1")
                posoff <= 0;
            else
                posoff <= posoff + 1;
        end
        else if (tx_byte == "\n") begin
            tx_byte <= START;
        end
        else begin
            tx_byte <= tx_byte + 1;
        end
    end






























endmodule
module top (
    input  ICE_CLK,
    input  UART_RX,
    output UART_TX,
    output RLED1,
    output RLED2,
    output RLED3,
    output RLED4,
    output GLED5,
    output OUT106
);


    wire pll_clk_50m;
    wire pll_locked;
    pll PLL_50MHz(
        .clock_in(ICE_CLK),
        .clock_out(pll_clk_50m),
        .locked(pll_locked)
    );


    wire       tx_dv;
    reg  [7:0] tx_byte;
    wire       tx_done;

    assign tx_dv = tx_done;

    uart_tx2 #(
        .F_CLK(50_000_000),
        .UART_BAUD(921600)
    )
    tx (
        .CLK(pll_clk_50m),
        .TX_DV(tx_dv),
        .TX_BYTE(tx_byte),
        .TX_DATA(UART_TX),
        .DONE(tx_done)
    );

    wire [3:0] leds = {RLED1, RLED2, RLED3, RLED4};
    assign leds = tx_byte[6:3];

    assign GLED5 = pll_locked;
    assign OUT106 = !UART_TX;


    reg [6:0] posoff = 0;
    parameter START = "0";


    always @(posedge tx_done) begin

        if (tx_byte > START + posoff) begin
            tx_byte <= "\n";


            if (posoff == "z" - "1")
                posoff <= 0;
            else
                posoff <= posoff + 1;
        end
        else if (tx_byte == "\n") begin
            tx_byte <= START;
        end
        else begin
            tx_byte <= tx_byte + 1;
        end
    end






























endmodule