data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v
 line:131: before: "skip"
1: b'%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:10: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_stream_gate.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:11: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_stream_gate);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #1000000;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:22: Unsupported: Ignoring delay on this delayed statement.\n    always #(RATE/2.0)    clk   = ~clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:25: Unsupported: Ignoring delay on this delayed statement.\n    initial #(RATE*100)   reset = 1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:129: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:130: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:141: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:145: syntax error, unexpected \'@\'\n            @(posedge clk)\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:156: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:158: Unsupported: Ignoring delay on this delayed statement.\n            #10000;\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:161: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:170: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:172: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:175: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:184: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:186: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:189: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:198: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:200: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:203: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:212: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:214: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:217: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:226: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:228: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:232: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:241: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:243: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:245: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:254: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:256: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:260: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:269: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:271: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:273: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:282: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:284: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:286: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:295: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:297: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:299: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:308: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:310: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:313: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:322: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:324: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:327: syntax error, unexpected \'@\'\n        @(posedge clk)\n        ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:336: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_stream_gate/tb_stream_gate.v:338: Unsupported: Ignoring delay on this delayed statement.\n        #10000;\n        ^\n%Error: Exiting due to 32 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_stream_gate();
    localparam RATE = 1000.0/20.0;
    
    initial begin
        $dumpfile("tb_stream_gate.vcd");
        $dumpvars(0, tb_stream_gate);
        
        #1000000;
            $finish;
    end
    
    
    parameter   RAND_BUSY = 0;
    
    
    reg     clk = 1'b1;
    always #(RATE/2.0)    clk   = ~clk;
    
    reg     reset = 1'b1;
    initial #(RATE*100)   reset = 1'b0;
    
    reg     cke = 1'b1;
    always @(posedge clk) cke <= 1;
    
    
    parameter N               = 2;
    parameter BYPASS          = 0;
    parameter DETECTOR_ENABLE = 1;
    
    parameter DATA_WIDTH      = 32;
    parameter LEN_WIDTH       = 32;
    parameter LEN_OFFSET      = 1'b1;
    parameter USER_WIDTH      = 0;
    
    parameter S_PERMIT_REGS   = 1;
    parameter S_REGS          = 1;
    parameter M_REGS          = 1;
    
    parameter USER_BITS       = USER_WIDTH > 0 ? USER_WIDTH : 1;
    
    reg                         skip = 0;
    reg     [N-1:0]             detect_first = 1;
    reg     [N-1:0]             detect_last  = 1;
    reg                         padding_en   = 1;
    reg     [DATA_WIDTH-1:0]    padding_data = 32'haa55aa55;
    reg                         padding_skip = 0;
    
    reg     [N-1:0]             s_permit_first = 1;
    reg     [N-1:0]             s_permit_last  = 1;
    reg     [LEN_WIDTH-1:0]     s_permit_len;
    reg     [USER_BITS-1:0]     s_permit_user = 0;
    reg                         s_permit_valid;
    wire                        s_permit_ready;
    
    wire    [N-1:0]             s_first;
    wire    [N-1:0]             s_last;
    reg     [DATA_WIDTH-1:0]    s_data;
    reg                         s_valid;
    wire                        s_ready;
    
    assign s_first[0] = (s_data[2:0] == 3'b000);
    assign s_last[0]  = (s_data[2:0] == 3'b111);
    assign s_first[1] = (s_data[5:0] == 5'b00000);
    assign s_last[1]  = (s_data[5:0] == 5'b11111);
    
    
    wire    [N-1:0]             m_first;
    wire    [N-1:0]             m_last;
    wire    [DATA_WIDTH-1:0]    m_data;
    wire    [USER_BITS-1:0]     m_user;
    wire                        m_valid;
    reg                         m_ready;
    
    
    
    jelly_stream_gate
            #(
                .N                  (N),
                .BYPASS             (BYPASS),
                .DETECTOR_ENABLE    (DETECTOR_ENABLE),
                .DATA_WIDTH         (DATA_WIDTH),
                .LEN_WIDTH          (LEN_WIDTH),
                .LEN_OFFSET         (LEN_OFFSET),
                .S_PERMIT_REGS      (S_PERMIT_REGS),
                .S_REGS             (S_REGS),
                .M_REGS             (M_REGS)
            )
        i_stream_gate
            (
                .reset              (reset),
                .clk                (clk),
                .cke                (cke),
                
                .skip               (skip),
                .detect_first       (detect_first),
                .detect_last        (detect_last),
                .padding_en         (padding_en),
                .padding_data       (padding_data),
                .padding_skip       (padding_skip),
                
                .s_permit_first     (s_permit_first),
                .s_permit_last      (s_permit_last),
                .s_permit_len       (s_permit_len),
                .s_permit_user      (s_permit_user),
                .s_permit_valid     (s_permit_valid),
                .s_permit_ready     (s_permit_ready),
                
                .s_first            (s_first),
                .s_last             (s_last),
                .s_data             (s_data),
                .s_valid            (s_valid),
                .s_ready            (s_ready),
                
                .m_first            (m_first),
                .m_last             (m_last),
                .m_data             (m_data),
                .m_user             (m_user),
                .m_valid            (m_valid),
                .m_ready            (m_ready)
            );
    
    initial begin
            s_permit_valid = 0;
    #10000;
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 2'b11;
            detect_last    <= 2'b11;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_first <= 2'b11;
            s_permit_last  <= 2'b01;
            s_permit_len   <= 1 - LEN_OFFSET;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
            @(posedge clk)
                skip           <= 0;
                detect_first   <= 2'b11;
                detect_last    <= 2'b11;
                padding_en     <= 1;
                padding_data   <= 32'haa55aa55;
                s_permit_first <= 2'b01;
                s_permit_last  <= 2'b01;
                s_permit_len   <= 13 - LEN_OFFSET;
                s_permit_valid <= 1;
            while ( !(s_permit_valid && s_permit_ready) )
                @(posedge clk);
                s_permit_valid <= 0;
            #10000;

        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 1;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 6;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 1;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 7;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 1;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 8;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 1;
            padding_en     <= 1;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 8;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 1;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 8;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        

        @(posedge clk)
            skip           <= 0;
            detect_first   <= 1;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 8;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 1;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 3;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        

        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 8;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 3;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 2;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 2;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        

        @(posedge clk)
            skip           <= 1;
            detect_first   <= 1;
            detect_last    <= 1;
            padding_en     <= 1;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 11;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        

        @(posedge clk)
            skip           <= 0;
            detect_first   <= 1;
            detect_last    <= 1;
            padding_en     <= 1;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 4;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        $finish();
    end
    
    
    always @(posedge clk) begin
        if ( reset ) begin
            s_data   <= 0;
            s_valid  <= 0;
            m_ready  <= 0;
        end
        else if ( cke ) begin
            if ( s_ready ) begin
                s_valid <= (RAND_BUSY ? {$random()} : 1'b1);
            end
            
            if ( s_ready & s_valid ) begin
                s_data <= s_data + 1;
            end
            
            m_ready <= (RAND_BUSY ? {$random()} : 1'b1);
        end
    end
    
    
    
    
    
    integer fp;
    initial begin
        fp = $fopen("out.txt", "w");
    end
    
    always @(posedge clk) begin
        if ( reset ) begin
        end
        else if ( cke ) begin
            if ( m_valid && m_ready ) begin
                $fdisplay(fp, "%h %b %b", m_data, m_first, m_last);
            end
        end
    end
    
    
    
endmodule
module tb_stream_gate();

    localparam RATE = 1000.0/20.0;
    
    initial begin
        $dumpfile("tb_stream_gate.vcd");
        $dumpvars(0, tb_stream_gate);
        
        #1000000;
            $finish;
    end
    
    
    parameter   RAND_BUSY = 0;
    
    
    reg     clk = 1'b1;
    always #(RATE/2.0)    clk   = ~clk;
    
    reg     reset = 1'b1;
    initial #(RATE*100)   reset = 1'b0;
    
    reg     cke = 1'b1;
    always @(posedge clk) cke <= 1;
    
    
    parameter N               = 2;
    parameter BYPASS          = 0;
    parameter DETECTOR_ENABLE = 1;
    
    parameter DATA_WIDTH      = 32;
    parameter LEN_WIDTH       = 32;
    parameter LEN_OFFSET      = 1'b1;
    parameter USER_WIDTH      = 0;
    
    parameter S_PERMIT_REGS   = 1;
    parameter S_REGS          = 1;
    parameter M_REGS          = 1;
    
    parameter USER_BITS       = USER_WIDTH > 0 ? USER_WIDTH : 1;
    
    reg                         skip = 0;
    reg     [N-1:0]             detect_first = 1;
    reg     [N-1:0]             detect_last  = 1;
    reg                         padding_en   = 1;
    reg     [DATA_WIDTH-1:0]    padding_data = 32'haa55aa55;
    reg                         padding_skip = 0;
    
    reg     [N-1:0]             s_permit_first = 1;
    reg     [N-1:0]             s_permit_last  = 1;
    reg     [LEN_WIDTH-1:0]     s_permit_len;
    reg     [USER_BITS-1:0]     s_permit_user = 0;
    reg                         s_permit_valid;
    wire                        s_permit_ready;
    
    wire    [N-1:0]             s_first;
    wire    [N-1:0]             s_last;
    reg     [DATA_WIDTH-1:0]    s_data;
    reg                         s_valid;
    wire                        s_ready;
    
    assign s_first[0] = (s_data[2:0] == 3'b000);
    assign s_last[0]  = (s_data[2:0] == 3'b111);
    assign s_first[1] = (s_data[5:0] == 5'b00000);
    assign s_last[1]  = (s_data[5:0] == 5'b11111);
    
    
    wire    [N-1:0]             m_first;
    wire    [N-1:0]             m_last;
    wire    [DATA_WIDTH-1:0]    m_data;
    wire    [USER_BITS-1:0]     m_user;
    wire                        m_valid;
    reg                         m_ready;
    
    
    
    jelly_stream_gate
            #(
                .N                  (N),
                .BYPASS             (BYPASS),
                .DETECTOR_ENABLE    (DETECTOR_ENABLE),
                .DATA_WIDTH         (DATA_WIDTH),
                .LEN_WIDTH          (LEN_WIDTH),
                .LEN_OFFSET         (LEN_OFFSET),
                .S_PERMIT_REGS      (S_PERMIT_REGS),
                .S_REGS             (S_REGS),
                .M_REGS             (M_REGS)
            )
        i_stream_gate
            (
                .reset              (reset),
                .clk                (clk),
                .cke                (cke),
                
                .skip               (skip),
                .detect_first       (detect_first),
                .detect_last        (detect_last),
                .padding_en         (padding_en),
                .padding_data       (padding_data),
                .padding_skip       (padding_skip),
                
                .s_permit_first     (s_permit_first),
                .s_permit_last      (s_permit_last),
                .s_permit_len       (s_permit_len),
                .s_permit_user      (s_permit_user),
                .s_permit_valid     (s_permit_valid),
                .s_permit_ready     (s_permit_ready),
                
                .s_first            (s_first),
                .s_last             (s_last),
                .s_data             (s_data),
                .s_valid            (s_valid),
                .s_ready            (s_ready),
                
                .m_first            (m_first),
                .m_last             (m_last),
                .m_data             (m_data),
                .m_user             (m_user),
                .m_valid            (m_valid),
                .m_ready            (m_ready)
            );
    
    initial begin
            s_permit_valid = 0;
    #10000;
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 2'b11;
            detect_last    <= 2'b11;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_first <= 2'b11;
            s_permit_last  <= 2'b01;
            s_permit_len   <= 1 - LEN_OFFSET;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
            @(posedge clk)
                skip           <= 0;
                detect_first   <= 2'b11;
                detect_last    <= 2'b11;
                padding_en     <= 1;
                padding_data   <= 32'haa55aa55;
                s_permit_first <= 2'b01;
                s_permit_last  <= 2'b01;
                s_permit_len   <= 13 - LEN_OFFSET;
                s_permit_valid <= 1;
            while ( !(s_permit_valid && s_permit_ready) )
                @(posedge clk);
                s_permit_valid <= 0;
            #10000;

        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 1;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 6;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 1;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 7;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 1;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 8;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 1;
            padding_en     <= 1;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 8;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 1;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 8;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        

        @(posedge clk)
            skip           <= 0;
            detect_first   <= 1;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 8;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 1;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 3;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        

        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 8;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 3;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 2;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        @(posedge clk)
            skip           <= 0;
            detect_first   <= 0;
            detect_last    <= 0;
            padding_en     <= 0;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 2;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        

        @(posedge clk)
            skip           <= 1;
            detect_first   <= 1;
            detect_last    <= 1;
            padding_en     <= 1;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 11;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        

        @(posedge clk)
            skip           <= 0;
            detect_first   <= 1;
            detect_last    <= 1;
            padding_en     <= 1;
            padding_data   <= 32'haa55aa55;
            s_permit_len   <= 4;
            s_permit_valid <= 1;
        while ( !(s_permit_valid && s_permit_ready) )
            @(posedge clk);
            s_permit_valid <= 0;
        #10000;
        
        $finish();
    end
    
    
    always @(posedge clk) begin
        if ( reset ) begin
            s_data   <= 0;
            s_valid  <= 0;
            m_ready  <= 0;
        end
        else if ( cke ) begin
            if ( s_ready ) begin
                s_valid <= (RAND_BUSY ? {$random()} : 1'b1);
            end
            
            if ( s_ready & s_valid ) begin
                s_data <= s_data + 1;
            end
            
            m_ready <= (RAND_BUSY ? {$random()} : 1'b1);
        end
    end
    
    
    
    
    
    integer fp;
    initial begin
        fp = $fopen("out.txt", "w");
    end
    
    always @(posedge clk) begin
        if ( reset ) begin
        end
        else if ( cke ) begin
            if ( m_valid && m_ready ) begin
                $fdisplay(fp, "%h %b %b", m_data, m_first, m_last);
            end
        end
    end
    
    
    
endmodule