data/full_repos/permissive/111393021/filter_spad.v
data/verilator_xmls/c5573243-23fe-4c30-8eb5-b09193cd20ed.xml
module filter_spad(clk, addr, we, data_port);

	input clk;
	input [7:0] addr;
	input we;
	inout [15:0] data_port;
	reg [15:0] data_out;
	reg [15:0] mem [223:0];

	assign data_port = !we ? data_out : 16'bz;

	always @ (posedge clk)	
	begin
		if (we)
			mem[addr] <= data_port;
		else
		begin
			data_out <= mem[addr];
		end

	end
endmodule
module filter_spad(clk, addr, we, data_port);


	input clk;
	input [7:0] addr;
	input we;
	inout [15:0] data_port;
	reg [15:0] data_out;
	reg [15:0] mem [223:0];

	assign data_port = !we ? data_out : 16'bz;

	always @ (posedge clk)	
	begin
		if (we)
			mem[addr] <= data_port;
		else
		begin
			data_out <= mem[addr];
		end

	end
endmodule