data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor/f15_wf_agg.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor/f15_wf_agg.v:181: Cannot find file containing module: 'delay_bit'\n delay_bit #(2) dl_init(init_0, init_2, clk);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor,data/full_repos/permissive/214858095/delay_bit\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor,data/full_repos/permissive/214858095/delay_bit.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor,data/full_repos/permissive/214858095/delay_bit.sv\n             delay_bit\n             delay_bit.v\n             delay_bit.sv\n             obj_dir/delay_bit\n             obj_dir/delay_bit.v\n             obj_dir/delay_bit.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fosphor/f15_wf_agg.v:187: Cannot find file containing module: 'delay_bit'\n delay_bit #(2) dl_zvalid(zvalid_1, zvalid_3, clk);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module f15_wf_agg #(
	parameter integer Y_WIDTH = 12,
	parameter integer X_WIDTH = 16,
	parameter integer DECIM_WIDTH = 8
)(
	input wire [Y_WIDTH-1:0] yin_0,
	input wire [X_WIDTH-1:0] x_0,
	input wire valid_0,
	input wire last_0,
	input wire [15:0] rng_0,

	output wire [Y_WIDTH-1:0] yout_3,
	output wire [7:0] zout_3,
	output wire zvalid_3,

	input wire [1:0] cfg_div,
	input wire cfg_mode,
	input wire [DECIM_WIDTH-1:0] cfg_decim,
	input wire cfg_decim_changed,

	input wire clk,
	input wire rst
);

	localparam integer R_WIDTH = X_WIDTH + 9;



	reg [R_WIDTH-1:0] xe_1;
	reg [R_WIDTH-1:0] ye_1;

	wire over_2;
	reg [R_WIDTH-1:0] r_2;
	reg [Y_WIDTH-1:0] x_2;
	reg [Y_WIDTH-1:0] y_2;

	reg [Y_WIDTH-1:0] y_3;


	reg [DECIM_WIDTH:0] decim_cnt;
	reg init_0;
	wire init_2;
	reg init_force_0;
	reg flush_0;
	reg zvalid_1;






	always @(posedge clk)
	begin
		case (cfg_div)
			2'b00:
				xe_1 <= { 1'd0, x_0, 8'd0 };

			2'b01:
				xe_1 <= { 4'd0, x_0, 5'd0 };

			2'b10:
				xe_1 <= { 7'd0, x_0, 2'd0 };

			2'b11:
				xe_1 <= { 9'd0, x_0 };
		endcase
	end


	always @(posedge clk)
	begin
		if (cfg_mode)

			ye_1 <= { 1'b0, yin_0, rng_0[R_WIDTH-Y_WIDTH-2:0] };
		else

			ye_1 <= { 1'b0, yin_0, {(R_WIDTH-Y_WIDTH-1){1'b0}} };
	end


	always @(posedge clk)
	begin
		if (cfg_mode)

			r_2 <= ye_1 + xe_1;
		else

			r_2 <= ye_1 - xe_1;
	end

	assign over_2 = r_2[R_WIDTH-1];


	always @(posedge clk)
	begin
		x_2 <= xe_1[R_WIDTH-2:R_WIDTH-Y_WIDTH-1];
		y_2 <= ye_1[R_WIDTH-2:R_WIDTH-Y_WIDTH-1];
	end


	always @(posedge clk)
	begin







		if (init_2)
			y_3 <= x_2;
		else if (cfg_mode)
			y_3 <= over_2 ? { (Y_WIDTH){1'b1} } : r_2[R_WIDTH-2:R_WIDTH-Y_WIDTH-1];
		else
			y_3 <= over_2 ? x_2 : y_2;
	end

	assign yout_3 = y_3;
	assign zout_3 = y_3[Y_WIDTH-1:Y_WIDTH-8];






	always @(posedge clk)
	begin
		if (rst)
			decim_cnt <= 0;
		else if (cfg_decim_changed)

			decim_cnt <= { 1'b0, cfg_decim };
		else if (valid_0 & last_0)
			if (decim_cnt[DECIM_WIDTH])

				decim_cnt <= { 1'b0, cfg_decim };
			else

				decim_cnt <= decim_cnt - 1;
	end


	always @(posedge clk)
	begin
		if (rst) begin

			flush_0 <= 1'b0;
			init_0  <= 1'b1;
			init_force_0 <= 1'b0;
		end else begin
			if (valid_0 & last_0) begin

				flush_0 <= decim_cnt[DECIM_WIDTH];


				init_0 <= flush_0 | init_force_0;
			end


			if (cfg_decim_changed)
				init_force_0 <= 1'b1;
			else if (valid_0 & last_0)
				init_force_0 <= 1'b0;
		end
	end

	delay_bit #(2) dl_init(init_0, init_2, clk);


	always @(posedge clk)
		zvalid_1 <= valid_0 & flush_0;

	delay_bit #(2) dl_zvalid(zvalid_1, zvalid_3, clk);

endmodule
module f15_wf_agg #(
	parameter integer Y_WIDTH = 12,
	parameter integer X_WIDTH = 16,
	parameter integer DECIM_WIDTH = 8
)(
	input wire [Y_WIDTH-1:0] yin_0,
	input wire [X_WIDTH-1:0] x_0,
	input wire valid_0,
	input wire last_0,
	input wire [15:0] rng_0,

	output wire [Y_WIDTH-1:0] yout_3,
	output wire [7:0] zout_3,
	output wire zvalid_3,

	input wire [1:0] cfg_div,
	input wire cfg_mode,
	input wire [DECIM_WIDTH-1:0] cfg_decim,
	input wire cfg_decim_changed,

	input wire clk,
	input wire rst
);


	localparam integer R_WIDTH = X_WIDTH + 9;



	reg [R_WIDTH-1:0] xe_1;
	reg [R_WIDTH-1:0] ye_1;

	wire over_2;
	reg [R_WIDTH-1:0] r_2;
	reg [Y_WIDTH-1:0] x_2;
	reg [Y_WIDTH-1:0] y_2;

	reg [Y_WIDTH-1:0] y_3;


	reg [DECIM_WIDTH:0] decim_cnt;
	reg init_0;
	wire init_2;
	reg init_force_0;
	reg flush_0;
	reg zvalid_1;






	always @(posedge clk)
	begin
		case (cfg_div)
			2'b00:
				xe_1 <= { 1'd0, x_0, 8'd0 };

			2'b01:
				xe_1 <= { 4'd0, x_0, 5'd0 };

			2'b10:
				xe_1 <= { 7'd0, x_0, 2'd0 };

			2'b11:
				xe_1 <= { 9'd0, x_0 };
		endcase
	end


	always @(posedge clk)
	begin
		if (cfg_mode)

			ye_1 <= { 1'b0, yin_0, rng_0[R_WIDTH-Y_WIDTH-2:0] };
		else

			ye_1 <= { 1'b0, yin_0, {(R_WIDTH-Y_WIDTH-1){1'b0}} };
	end


	always @(posedge clk)
	begin
		if (cfg_mode)

			r_2 <= ye_1 + xe_1;
		else

			r_2 <= ye_1 - xe_1;
	end

	assign over_2 = r_2[R_WIDTH-1];


	always @(posedge clk)
	begin
		x_2 <= xe_1[R_WIDTH-2:R_WIDTH-Y_WIDTH-1];
		y_2 <= ye_1[R_WIDTH-2:R_WIDTH-Y_WIDTH-1];
	end


	always @(posedge clk)
	begin







		if (init_2)
			y_3 <= x_2;
		else if (cfg_mode)
			y_3 <= over_2 ? { (Y_WIDTH){1'b1} } : r_2[R_WIDTH-2:R_WIDTH-Y_WIDTH-1];
		else
			y_3 <= over_2 ? x_2 : y_2;
	end

	assign yout_3 = y_3;
	assign zout_3 = y_3[Y_WIDTH-1:Y_WIDTH-8];






	always @(posedge clk)
	begin
		if (rst)
			decim_cnt <= 0;
		else if (cfg_decim_changed)

			decim_cnt <= { 1'b0, cfg_decim };
		else if (valid_0 & last_0)
			if (decim_cnt[DECIM_WIDTH])

				decim_cnt <= { 1'b0, cfg_decim };
			else

				decim_cnt <= decim_cnt - 1;
	end


	always @(posedge clk)
	begin
		if (rst) begin

			flush_0 <= 1'b0;
			init_0  <= 1'b1;
			init_force_0 <= 1'b0;
		end else begin
			if (valid_0 & last_0) begin

				flush_0 <= decim_cnt[DECIM_WIDTH];


				init_0 <= flush_0 | init_force_0;
			end


			if (cfg_decim_changed)
				init_force_0 <= 1'b1;
			else if (valid_0 & last_0)
				init_force_0 <= 1'b0;
		end
	end

	delay_bit #(2) dl_init(init_0, init_2, clk);


	always @(posedge clk)
		zvalid_1 <= valid_0 & flush_0;

	delay_bit #(2) dl_zvalid(zvalid_1, zvalid_3, clk);

endmodule