data/full_repos/permissive/143278/ivltests/always3.1.3D.v
 line:38: before: "value1"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.3D.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #15;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/always3.1.3D.v:38: Unsupported: Verilog 1995 force\nalways force value1 = 4\'h5;\n       ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ;

reg [3:0] value1 ;

initial
  begin
    #15;
    if(value1 != 4'h5)
      $display("FAILED - 3.1.3D always force reg_lvalue = constant;\n");
    else
	begin
           $display("PASSED\n");
	   $finish;
        end
  end

always force value1 = 4'h5;

endmodule
module main ;


reg [3:0] value1 ;

initial
  begin
    #15;
    if(value1 != 4'h5)
      $display("FAILED - 3.1.3D always force reg_lvalue = constant;\n");
    else
	begin
           $display("PASSED\n");
	   $finish;
        end
  end

always force value1 = 4'h5;

endmodule