data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:116: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdptr_b_rd  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:117: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdptr_g_rd  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:118: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrptr_g_rd1 <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:119: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrptr_g_rd2 <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:120: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrptr_b_rd  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:121: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdusedw     <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:131: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  rdptr_g_rd  <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:132: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  wrptr_g_rd1 <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:133: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  wrptr_g_rd2 <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:204: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrptr_b_wr  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:205: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrptr_g_wr  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:206: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdptr_g_wr1 <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:207: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdptr_g_wr2 <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:208: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             rdptr_b_wr  <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:209: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n             wrusedw     <= {ADDR_WIDTH{1\'b0}} ;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:219: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  wrptr_g_wr  <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:220: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  rdptr_g_wr1 <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:221: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  rdptr_g_wr2 <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:222: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance lite_fifo\n                  rdptr_b_wr  <= {ADDR_WIDTH{1\'b0}} ;\n                              ^~\n%Error: data/full_repos/permissive/141582589/src/common_rtl/lite_fifo.v:377: Cannot find file containing module: \'dp_ram\'\ndp_ram\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141582589/src/common_rtl,data/full_repos/permissive/141582589/dp_ram\n             data/full_repos/permissive/141582589/src/common_rtl,data/full_repos/permissive/141582589/dp_ram.v\n             data/full_repos/permissive/141582589/src/common_rtl,data/full_repos/permissive/141582589/dp_ram.sv\n             dp_ram\n             dp_ram.v\n             dp_ram.sv\n             obj_dir/dp_ram\n             obj_dir/dp_ram.v\n             obj_dir/dp_ram.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n'
function [ADDR_WIDTH:0] gray2bin
     ( input [ADDR_WIDTH:0] gray ) ;
      reg [ADDR_WIDTH:0] temp ;
      integer i ;
      begin
         temp[ADDR_WIDTH] = gray[ADDR_WIDTH] ;
         for (i = (ADDR_WIDTH-1); i >= 0 ; i = i - 1)
           begin
              temp[i] = temp[i+1] ^ gray[i] ;
           end
         gray2bin = temp ;
      end
   endfunction
function [ADDR_WIDTH:0] gray2bin
     ( input [ADDR_WIDTH:0] gray ) ;

      reg [ADDR_WIDTH:0] temp ;
      integer i ;
      begin
         temp[ADDR_WIDTH] = gray[ADDR_WIDTH] ;
         for (i = (ADDR_WIDTH-1); i >= 0 ; i = i - 1)
           begin
              temp[i] = temp[i+1] ^ gray[i] ;
           end
         gray2bin = temp ;
      end
   endfunction