data/full_repos/permissive/195227969/work/hwtst/max_iceblink40-hx1k/max_iceblink40-hx1k.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/195227969/work/hwtst/max_iceblink40-hx1k/max_iceblink40-hx1k.v:10: Cannot find include file: ../../midgetv.v\n`include "../../midgetv.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/195227969/work/hwtst/max_iceblink40-hx1k,data/full_repos/permissive/195227969/../../midgetv.v\n             data/full_repos/permissive/195227969/work/hwtst/max_iceblink40-hx1k,data/full_repos/permissive/195227969/../../midgetv.v.v\n             data/full_repos/permissive/195227969/work/hwtst/max_iceblink40-hx1k,data/full_repos/permissive/195227969/../../midgetv.v.sv\n             ../../midgetv.v\n             ../../midgetv.v.v\n             ../../midgetv.v.sv\n             obj_dir/../../midgetv.v\n             obj_dir/../../midgetv.v.v\n             obj_dir/../../midgetv.v.sv\n%Error: data/full_repos/permissive/195227969/work/hwtst/max_iceblink40-hx1k/max_iceblink40-hx1k.v:12: Cannot find include file: ../div/m_digilent.v\n`include "../div/m_digilent.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/195227969/work/hwtst/max_iceblink40-hx1k/max_iceblink40-hx1k.v:13: Cannot find include file: ../div/m_fm_xmit.v\n`include "../div/m_fm_xmit.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/195227969/work/hwtst/max_iceblink40-hx1k/max_iceblink40-hx1k.v:135: Cannot find include file: ice40loaderprog.hv\n%Error: Exiting due to 4 error(s)\n'
module top
  # ( parameter
      SRAMADRWIDTH       = 12,
      FORCEEBRAWIDTH     = 11,
      IWIDTH             = 32,
      NO_CYCLECNT        = 0, 
      MTIMETAP           = 16, 
      HIGHLEVEL          = 0
      )
   (
    input        padCLK_I,
    output [3:0] padled,

    output       padSS_B,
    
    input        padnADDRSTB,
    input        padnDATASTB,
    input        padnWRITE,
    inout [7:0]  padDB,
    output       padnWAIT,

    output       padantennae
    );
   


   wire [31:0]          ADR_O;
   wire                 CYC_O;
   wire [31:0]          DAT_O;
   wire [3:0]           SEL_O;
   wire                 STB_O;
   wire                 WE_O;
   wire                 antennae;
   wire                 corerunning;
   wire [31:0]          dbga;
   wire                 digilent_ACK_O;
   wire [0:0]           fm_xmit_DAT_O;
   wire                 fm_xmt_ACK_O;
   wire                 midgetv_core_killwarnings;

   
   
   

   wire          led_ACK_O;
   wire          led_STB_I      = STB_O & ADR_O[2];
   wire          digilent_STB_I = STB_O & ADR_O[3];
   wire          fm_xmit_STB_I  = STB_O & ADR_O[4];
   wire          ACK_I = led_ACK_O | digilent_ACK_O | fm_xmt_ACK_O;
   
   wire          CLK_I;

   SB_IO #(.PIN_TYPE( 6'b 0110_01)) theSS_B(.PACKAGE_PIN(padSS_B), .D_OUT_0(1'b1));
   SB_GB_IO #(.PIN_TYPE( 6'b0000_01)) theCLK_I(.PACKAGE_PIN(padCLK_I),.GLOBAL_BUFFER_OUTPUT(CLK_I));
   

   reg [3:0] rled;
   always @(posedge CLK_I)  begin
      if ( led_STB_I & WE_O  ) begin
         rled[3:0]  <= DAT_O[3:0];
      end
   end

   SB_IO #(.PIN_TYPE( 6'b 0110_01)) theled [3:0] (.PACKAGE_PIN(padled), .D_OUT_0(rled));
   assign led_ACK_O = led_STB_I;
   

   wire [7:0] digilent_DAT_O;
   m_digilent 
     inst_digilent
       (
        .ACK_O(       digilent_ACK_O ),
        .DAT_O(       digilent_DAT_O ),

        .STB_I(       digilent_STB_I ),
        .DAT_I(       DAT_O[7:0]     ),
        .ADR_I(       ADR_O[2:2]     ),
        .WE_I(        WE_O           ),


        .padnWAIT                       (padnWAIT),

        .padDB                          (padDB[7:0]),

        .CLK_I                          (CLK_I),
        .padnADDRSTB                    (padnADDRSTB),
        .padnDATASTB                    (padnDATASTB),
        .padnWRITE                      (padnWRITE));
   

   m_fm_xmit i_fm_xmit
     (
      .ACK_O                            (fm_xmt_ACK_O),
      .DAT_O                            (fm_xmit_DAT_O[0:0]),
      .antennae                         (antennae),

      .DAT_I                            (DAT_O[14:0]),
      .STB_I                            (fm_xmit_STB_I),
      .WE_I                             (WE_O),


      .CLK_I                            (CLK_I));
   SB_IO #(.PIN_TYPE( 6'b 0110_01)) theantennae (.PACKAGE_PIN(padantennae), .D_OUT_0(antennae));

   

`ifndef defaulticeprog 
 `define defaulticeprog "ice40loaderprog.hv" 
`endif 
`include `defaulticeprog
   
   m_midgetv_core
     #(
       .SRAMADRWIDTH       ( SRAMADRWIDTH       ),
       .EBRAWIDTH          ( FORCEEBRAWIDTH     ),
       .IWIDTH             ( IWIDTH             ),
       .NO_CYCLECNT        ( NO_CYCLECNT        ),
       .MTIMETAP           ( MTIMETAP           ),
       .HIGHLEVEL          ( HIGHLEVEL          ),
       .prg00(prg00),       .prg01(prg01),       .prg02(prg02),       .prg03(prg03),
       .prg04(prg04),       .prg05(prg05),       .prg06(prg06),       .prg07(prg07),
       .prg08(prg08),       .prg09(prg09),       .prg0A(prg0A),       .prg0B(prg0B),
       .prg0C(prg0C),       .prg0D(prg0D),       .prg0E(prg0E),       .prg0F(prg0F)
       )
   inst_midgetv_core
     (
      .RST_I                            (1'b0),
      .meip                             (1'b0),
      .start                            (1'b1),
      .DAT_I                            ({23'h0,fm_xmit_DAT_O,digilent_DAT_O}),


      .CYC_O                            (CYC_O),
      .STB_O                            (STB_O),
      .WE_O                             (WE_O),
      .ADR_O                            (ADR_O[31:0]),
      .DAT_O                            (DAT_O[31:0]),
      .SEL_O                            (SEL_O[3:0]),
      .corerunning                      (corerunning),
      .dbga                             (dbga[31:0]),
      .midgetv_core_killwarnings        (midgetv_core_killwarnings),

      .CLK_I                            (CLK_I),
      .ACK_I                            (ACK_I));
     
endmodule
module top
  # ( parameter
      SRAMADRWIDTH       = 12,
      FORCEEBRAWIDTH     = 11,
      IWIDTH             = 32,
      NO_CYCLECNT        = 0, 
      MTIMETAP           = 16, 
      HIGHLEVEL          = 0
      )
   (
    input        padCLK_I,
    output [3:0] padled,

    output       padSS_B,
    
    input        padnADDRSTB,
    input        padnDATASTB,
    input        padnWRITE,
    inout [7:0]  padDB,
    output       padnWAIT,

    output       padantennae
    );

   


   wire [31:0]          ADR_O;
   wire                 CYC_O;
   wire [31:0]          DAT_O;
   wire [3:0]           SEL_O;
   wire                 STB_O;
   wire                 WE_O;
   wire                 antennae;
   wire                 corerunning;
   wire [31:0]          dbga;
   wire                 digilent_ACK_O;
   wire [0:0]           fm_xmit_DAT_O;
   wire                 fm_xmt_ACK_O;
   wire                 midgetv_core_killwarnings;

   
   
   

   wire          led_ACK_O;
   wire          led_STB_I      = STB_O & ADR_O[2];
   wire          digilent_STB_I = STB_O & ADR_O[3];
   wire          fm_xmit_STB_I  = STB_O & ADR_O[4];
   wire          ACK_I = led_ACK_O | digilent_ACK_O | fm_xmt_ACK_O;
   
   wire          CLK_I;

   SB_IO #(.PIN_TYPE( 6'b 0110_01)) theSS_B(.PACKAGE_PIN(padSS_B), .D_OUT_0(1'b1));
   SB_GB_IO #(.PIN_TYPE( 6'b0000_01)) theCLK_I(.PACKAGE_PIN(padCLK_I),.GLOBAL_BUFFER_OUTPUT(CLK_I));
   

   reg [3:0] rled;
   always @(posedge CLK_I)  begin
      if ( led_STB_I & WE_O  ) begin
         rled[3:0]  <= DAT_O[3:0];
      end
   end

   SB_IO #(.PIN_TYPE( 6'b 0110_01)) theled [3:0] (.PACKAGE_PIN(padled), .D_OUT_0(rled));
   assign led_ACK_O = led_STB_I;
   

   wire [7:0] digilent_DAT_O;
   m_digilent 
     inst_digilent
       (
        .ACK_O(       digilent_ACK_O ),
        .DAT_O(       digilent_DAT_O ),

        .STB_I(       digilent_STB_I ),
        .DAT_I(       DAT_O[7:0]     ),
        .ADR_I(       ADR_O[2:2]     ),
        .WE_I(        WE_O           ),


        .padnWAIT                       (padnWAIT),

        .padDB                          (padDB[7:0]),

        .CLK_I                          (CLK_I),
        .padnADDRSTB                    (padnADDRSTB),
        .padnDATASTB                    (padnDATASTB),
        .padnWRITE                      (padnWRITE));
   

   m_fm_xmit i_fm_xmit
     (
      .ACK_O                            (fm_xmt_ACK_O),
      .DAT_O                            (fm_xmit_DAT_O[0:0]),
      .antennae                         (antennae),

      .DAT_I                            (DAT_O[14:0]),
      .STB_I                            (fm_xmit_STB_I),
      .WE_I                             (WE_O),


      .CLK_I                            (CLK_I));
   SB_IO #(.PIN_TYPE( 6'b 0110_01)) theantennae (.PACKAGE_PIN(padantennae), .D_OUT_0(antennae));

   

`ifndef defaulticeprog 
 `define defaulticeprog "ice40loaderprog.hv" 
`endif 
`include `defaulticeprog
   
   m_midgetv_core
     #(
       .SRAMADRWIDTH       ( SRAMADRWIDTH       ),
       .EBRAWIDTH          ( FORCEEBRAWIDTH     ),
       .IWIDTH             ( IWIDTH             ),
       .NO_CYCLECNT        ( NO_CYCLECNT        ),
       .MTIMETAP           ( MTIMETAP           ),
       .HIGHLEVEL          ( HIGHLEVEL          ),
       .prg00(prg00),       .prg01(prg01),       .prg02(prg02),       .prg03(prg03),
       .prg04(prg04),       .prg05(prg05),       .prg06(prg06),       .prg07(prg07),
       .prg08(prg08),       .prg09(prg09),       .prg0A(prg0A),       .prg0B(prg0B),
       .prg0C(prg0C),       .prg0D(prg0D),       .prg0E(prg0E),       .prg0F(prg0F)
       )
   inst_midgetv_core
     (
      .RST_I                            (1'b0),
      .meip                             (1'b0),
      .start                            (1'b1),
      .DAT_I                            ({23'h0,fm_xmit_DAT_O,digilent_DAT_O}),


      .CYC_O                            (CYC_O),
      .STB_O                            (STB_O),
      .WE_O                             (WE_O),
      .ADR_O                            (ADR_O[31:0]),
      .DAT_O                            (DAT_O[31:0]),
      .SEL_O                            (SEL_O[3:0]),
      .corerunning                      (corerunning),
      .dbga                             (dbga[31:0]),
      .midgetv_core_killwarnings        (midgetv_core_killwarnings),

      .CLK_I                            (CLK_I),
      .ACK_I                            (ACK_I));
     
endmodule