data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/i2s_clkctrl_apb.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/i2s_clkctrl_apb.v:146: Signal definition not found, creating implicitly: \'lrclk\'\n                                                                                                      : ... Suggested alternative: \'lrclk1\'\n  .reset_n (reset_n & ~lrclk),\n                       ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module i2s_clkctrl_apb (
	input				clk,
	input				reset_n,

	input		[4:0]	paddr,
	input				penable,
	input				pwrite,
	input 		[31:0]	pwdata,
	input				psel,
	output reg	[31:0]	prdata,
	output				pready,

	input				clk_48,
	input				clk_44,

	input				ext_bclk,
	input				ext_playback_lrclk,
	input				ext_capture_lrclk,
	output				master_slave_mode,

	output				clk_sel_48_44,
	output				mclk,
	output				bclk,
	output				playback_lrclk,
	output				capture_lrclk
);


	reg [31:0]		cmd_reg1;
	wire			cmd_sel1 = psel && (paddr == 0);
	reg [31:0]		cmd_reg2;
	wire			cmd_sel2 = psel && (paddr == 4);
	assign 			master_slave_mode = cmd_reg1[0];
	assign			clk_sel_48_44 = cmd_reg1[1];
	wire			cmd_reg2_wr = cmd_sel2 & pwrite & penable;

	always @(posedge clk or negedge reset_n)
	begin
		if (~reset_n)
		begin
			cmd_reg1 <= 0;
			cmd_reg2 <= 0;
		end
		else
		begin
			if (cmd_sel1 & pwrite & penable)
				cmd_reg1 <= pwdata;
			else if (cmd_sel1 & ~pwrite & ~penable)
				prdata <= cmd_reg1;
			if (cmd_reg2_wr)
				cmd_reg2 <= pwdata;
			else if (cmd_sel2 & ~pwrite & ~penable)
				prdata <= cmd_reg2;
		end
	end

	wire mclk48;
	wire bclk48;
	wire playback_lrclk48;
	wire capture_lrclk48;
	audio_clock_generator playback_gen48 (
		.clk		(clk_48),
		.reset_n	(reset_n),
		.cmd_reg1	(cmd_reg1),
		.cmd_reg2	(cmd_reg2),
		.mclk		(mclk48),
		.bclk		(bclk48),
		.lrclk_clear(cmd_reg2_wr),
		.lrclk1		(playback_lrclk48),
		.lrclk2		(capture_lrclk48)
	);
	wire mclk44;
	wire bclk44;
	wire playback_lrclk44;
	wire capture_lrclk44;
	audio_clock_generator playback_gen44 (
		.clk		(clk_44),
		.reset_n	(reset_n & ~cmd_reg2_wr),
		.cmd_reg1	(cmd_reg1),
		.cmd_reg2	(cmd_reg2),
		.mclk		(mclk44),
		.bclk		(bclk44),
		.lrclk_clear(cmd_reg2_wr),
		.lrclk1		(playback_lrclk44),
		.lrclk2		(capture_lrclk44)
	);
	

	assign mclk = clk_sel_48_44 ? mclk44 : mclk48;
	assign bclk = master_slave_mode
		? (clk_sel_48_44 ? bclk44 : bclk48)
		: ext_bclk;
	assign playback_lrclk = master_slave_mode
		? (clk_sel_48_44 ? playback_lrclk44 : playback_lrclk48)
		: ext_playback_lrclk;
	assign capture_lrclk = master_slave_mode
		? (clk_sel_48_44 ? capture_lrclk44 : capture_lrclk48)
		: ext_capture_lrclk;


	assign pready = penable;

endmodule
module i2s_clkctrl_apb (
	input				clk,
	input				reset_n,

	input		[4:0]	paddr,
	input				penable,
	input				pwrite,
	input 		[31:0]	pwdata,
	input				psel,
	output reg	[31:0]	prdata,
	output				pready,

	input				clk_48,
	input				clk_44,

	input				ext_bclk,
	input				ext_playback_lrclk,
	input				ext_capture_lrclk,
	output				master_slave_mode,

	output				clk_sel_48_44,
	output				mclk,
	output				bclk,
	output				playback_lrclk,
	output				capture_lrclk
);



	reg [31:0]		cmd_reg1;
	wire			cmd_sel1 = psel && (paddr == 0);
	reg [31:0]		cmd_reg2;
	wire			cmd_sel2 = psel && (paddr == 4);
	assign 			master_slave_mode = cmd_reg1[0];
	assign			clk_sel_48_44 = cmd_reg1[1];
	wire			cmd_reg2_wr = cmd_sel2 & pwrite & penable;

	always @(posedge clk or negedge reset_n)
	begin
		if (~reset_n)
		begin
			cmd_reg1 <= 0;
			cmd_reg2 <= 0;
		end
		else
		begin
			if (cmd_sel1 & pwrite & penable)
				cmd_reg1 <= pwdata;
			else if (cmd_sel1 & ~pwrite & ~penable)
				prdata <= cmd_reg1;
			if (cmd_reg2_wr)
				cmd_reg2 <= pwdata;
			else if (cmd_sel2 & ~pwrite & ~penable)
				prdata <= cmd_reg2;
		end
	end

	wire mclk48;
	wire bclk48;
	wire playback_lrclk48;
	wire capture_lrclk48;
	audio_clock_generator playback_gen48 (
		.clk		(clk_48),
		.reset_n	(reset_n),
		.cmd_reg1	(cmd_reg1),
		.cmd_reg2	(cmd_reg2),
		.mclk		(mclk48),
		.bclk		(bclk48),
		.lrclk_clear(cmd_reg2_wr),
		.lrclk1		(playback_lrclk48),
		.lrclk2		(capture_lrclk48)
	);
	wire mclk44;
	wire bclk44;
	wire playback_lrclk44;
	wire capture_lrclk44;
	audio_clock_generator playback_gen44 (
		.clk		(clk_44),
		.reset_n	(reset_n & ~cmd_reg2_wr),
		.cmd_reg1	(cmd_reg1),
		.cmd_reg2	(cmd_reg2),
		.mclk		(mclk44),
		.bclk		(bclk44),
		.lrclk_clear(cmd_reg2_wr),
		.lrclk1		(playback_lrclk44),
		.lrclk2		(capture_lrclk44)
	);
	

	assign mclk = clk_sel_48_44 ? mclk44 : mclk48;
	assign bclk = master_slave_mode
		? (clk_sel_48_44 ? bclk44 : bclk48)
		: ext_bclk;
	assign playback_lrclk = master_slave_mode
		? (clk_sel_48_44 ? playback_lrclk44 : playback_lrclk48)
		: ext_playback_lrclk;
	assign capture_lrclk = master_slave_mode
		? (clk_sel_48_44 ? capture_lrclk44 : capture_lrclk48)
		: ext_capture_lrclk;


	assign pready = penable;

endmodule