data/full_repos/permissive/117880471/HW3/full_adder.v
 line:27: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:12: Unsupported: Ignoring delay on this delayed statement.\n #00 clock = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:13: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clock = ~clock;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:18: Unsupported: Ignoring delay on this delayed statement.\n #10 ain = 1\'b0; bin = 1\'b0; cin = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:19: Unsupported: Ignoring delay on this delayed statement.\n #20 ain = 1\'b1; bin = 1\'b0; cin = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:20: Unsupported: Ignoring delay on this delayed statement.\n #20 ain = 1\'b0; bin = 1\'b1; cin = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:21: Unsupported: Ignoring delay on this delayed statement.\n #20 ain = 1\'b1; bin = 1\'b0; cin = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:22: Unsupported: Ignoring delay on this delayed statement.\n #20 ain = 1\'b0; bin = 1\'b0; cin = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:23: Unsupported: Ignoring delay on this delayed statement.\n #20 ain = 1\'b1; bin = 1\'b0; cin = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:24: Unsupported: Ignoring delay on this delayed statement.\n #20 ain = 1\'b0; bin = 1\'b1; cin = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20 ain = 1\'b1; bin = 1\'b0; cin = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:26: Unsupported: Ignoring delay on this delayed statement.\n #20 ain = 1\'b0; bin = 1\'b1; cin = 1\'b0;\n ^\n%Error: data/full_repos/permissive/117880471/HW3/full_adder.v:28: syntax error, unexpected end, expecting \';\'\nend\n^~~\n%Error: data/full_repos/permissive/117880471/HW3/full_adder.v:32: Unsupported or unknown PLI call: $monitor\n $monitor("time=%3d, fa_out=%b, cout=%b, ain=%b, bin=%b, cin=%b", $time, fa_out, cout, ain, bin, cin);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/full_adder.v:27: Unsupported: Ignoring delay on this delayed statement.\n #20 $stop\n ^\n%Error: data/full_repos/permissive/117880471/HW3/full_adder.v:37: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("full_adder.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/full_adder.v:38: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_full_adder();

wire fa_out, cout;
reg ain, bin, cin;

full_adder uut(fa_out, cout, ain, bin, cin);

initial
begin
	#00 clock = 1'b0;
	forever #20 clock = ~clock;
end

initial
begin
	#10 ain = 1'b0; bin = 1'b0; cin = 1'b0;
	#20 ain = 1'b1; bin = 1'b0; cin = 1'b1;
	#20 ain = 1'b0; bin = 1'b1; cin = 1'b0;
	#20 ain = 1'b1; bin = 1'b0; cin = 1'b1;
	#20 ain = 1'b0; bin = 1'b0; cin = 1'b0;
	#20 ain = 1'b1; bin = 1'b0; cin = 1'b1;
	#20 ain = 1'b0; bin = 1'b1; cin = 1'b0;
	#20 ain = 1'b1; bin = 1'b0; cin = 1'b1;
	#20 ain = 1'b0; bin = 1'b1; cin = 1'b0;
	#20 $stop
end

initial
begin
	$monitor("time=%3d, fa_out=%b, cout=%b, ain=%b, bin=%b, cin=%b", $time, fa_out, cout, ain, bin, cin);
end

initial
begin
	$dumpfile("full_adder.vcd");
	$dumpvars;
end

endmodule
module tb_full_adder();


wire fa_out, cout;
reg ain, bin, cin;

full_adder uut(fa_out, cout, ain, bin, cin);

initial
begin
	#00 clock = 1'b0;
	forever #20 clock = ~clock;
end

initial
begin
	#10 ain = 1'b0; bin = 1'b0; cin = 1'b0;
	#20 ain = 1'b1; bin = 1'b0; cin = 1'b1;
	#20 ain = 1'b0; bin = 1'b1; cin = 1'b0;
	#20 ain = 1'b1; bin = 1'b0; cin = 1'b1;
	#20 ain = 1'b0; bin = 1'b0; cin = 1'b0;
	#20 ain = 1'b1; bin = 1'b0; cin = 1'b1;
	#20 ain = 1'b0; bin = 1'b1; cin = 1'b0;
	#20 ain = 1'b1; bin = 1'b0; cin = 1'b1;
	#20 ain = 1'b0; bin = 1'b1; cin = 1'b0;
	#20 $stop
end

initial
begin
	$monitor("time=%3d, fa_out=%b, cout=%b, ain=%b, bin=%b, cin=%b", $time, fa_out, cout, ain, bin, cin);
end

initial
begin
	$dumpfile("full_adder.vcd");
	$dumpvars;
end

endmodule