data/full_repos/permissive/122924576/sram_control.v
data/verilator_xmls/21427351-73ce-4699-82e2-6be199b4662e.xml
module sram_controller(

input clk_50,
input rst_n,
input[19:0] addr_in,
input start,
input[15:0] data_in,

output[19:0] sram_addr,
output sram_wr_n,
output sram_ce_n,
output sram_oe_n,
output sram_ub_n,
output sram_lb_n,
output led,

inout[15:0] sram_data
);

assign sram_ce_n = 1'b0;
assign sram_oe_n = 1'b0;
assign sram_ub_n = 1'b0;
assign sram_lb_n = 1'b0;

reg[25:0] delay;
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        delay <= 26'd0;
    else
        delay <= delay+1'b1;

reg[15:0] wr_data;
reg[15:0] rd_data;
reg[19:0] addr_r;
wire sram_wr_req;
wire sram_rd_req;
reg led_r;
 
assign sram_wr_req = (delay == 26'd9999);
assign sram_rd_req = (delay == 26'd19999);
 
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        wr_data <= 16'b0;
    else if(start == 1'b1)
        wr_data <= data_in;
         
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        addr_r <= 20'b0;
    else if(start == 1'b1)
        addr_r <= addr_in;
     
always@(posedge clk_50 or negedge rst_n)
        if(!rst_n)
            led_r <= 1'b0;
        else if(delay == 26'd99)
            begin
                if(wr_data == rd_data)
                    led_r <= 1'b1;
                else
                    led_r <= 1'b0;
            end
assign led = led_r;

`define DELAY_80NS  (cnt == 3'd7)
 
reg[3:0] cstate, nstate;
parameter   IDEL = 4'd0,
            WRT0 = 4'd1,
            WRT1 = 4'd2,
            REA0 = 4'd3,
            REA1 = 4'd4;
             
reg[2:0] cnt;
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        cnt <= 3'b0;
    else if(cstate == IDEL)
        cnt <= 3'b0;
    else
        cnt <= cnt+1'b1;

always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        cstate <= IDEL;
    else
        cstate <= nstate;

always@(posedge clk_50 or negedge rst_n)
    case(cstate)
        IDEL:   if(sram_wr_req)
                    nstate <= WRT0;
                else if(sram_rd_req)
                    nstate <= REA0;
                else
                    nstate <= IDEL;
        WRT0:   if(`DELAY_80NS)
                    nstate <= WRT1;
                else
                    nstate <= WRT0;
        WRT1:   nstate <= IDEL;
        REA0:   if(`DELAY_80NS)
                    nstate <= REA1;
                else
                    nstate <= REA0;
        REA1:   nstate <= IDEL;
        default:nstate <= IDEL;
    endcase
     
assign sram_addr =addr_r;

reg sdlink;
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        rd_data <= 16'b0;
    else if(cstate == REA1)
        rd_data <= sram_data;
         
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        sdlink <= 1'b0;
    else
        case(cstate)
            IDEL:   if(sram_wr_req)
                        sdlink <= 1'b1;
                    else if(sram_rd_req)
                        sdlink <= 1'b0;
                    else
                        sdlink <= 1'b0;
            WRT0:   sdlink <= 1'b1;
            default:sdlink <= 1'b0;
        endcase
     
assign sram_data = sdlink ? wr_data:16'hzzzz;
assign sram_wr_n = ~sdlink;
 
endmodule
module sram_controller(

input clk_50,
input rst_n,
input[19:0] addr_in,
input start,
input[15:0] data_in,

output[19:0] sram_addr,
output sram_wr_n,
output sram_ce_n,
output sram_oe_n,
output sram_ub_n,
output sram_lb_n,
output led,

inout[15:0] sram_data
);


assign sram_ce_n = 1'b0;
assign sram_oe_n = 1'b0;
assign sram_ub_n = 1'b0;
assign sram_lb_n = 1'b0;

reg[25:0] delay;
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        delay <= 26'd0;
    else
        delay <= delay+1'b1;

reg[15:0] wr_data;
reg[15:0] rd_data;
reg[19:0] addr_r;
wire sram_wr_req;
wire sram_rd_req;
reg led_r;
 
assign sram_wr_req = (delay == 26'd9999);
assign sram_rd_req = (delay == 26'd19999);
 
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        wr_data <= 16'b0;
    else if(start == 1'b1)
        wr_data <= data_in;
         
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        addr_r <= 20'b0;
    else if(start == 1'b1)
        addr_r <= addr_in;
     
always@(posedge clk_50 or negedge rst_n)
        if(!rst_n)
            led_r <= 1'b0;
        else if(delay == 26'd99)
            begin
                if(wr_data == rd_data)
                    led_r <= 1'b1;
                else
                    led_r <= 1'b0;
            end
assign led = led_r;

`define DELAY_80NS  (cnt == 3'd7)
 
reg[3:0] cstate, nstate;
parameter   IDEL = 4'd0,
            WRT0 = 4'd1,
            WRT1 = 4'd2,
            REA0 = 4'd3,
            REA1 = 4'd4;
             
reg[2:0] cnt;
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        cnt <= 3'b0;
    else if(cstate == IDEL)
        cnt <= 3'b0;
    else
        cnt <= cnt+1'b1;

always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        cstate <= IDEL;
    else
        cstate <= nstate;

always@(posedge clk_50 or negedge rst_n)
    case(cstate)
        IDEL:   if(sram_wr_req)
                    nstate <= WRT0;
                else if(sram_rd_req)
                    nstate <= REA0;
                else
                    nstate <= IDEL;
        WRT0:   if(`DELAY_80NS)
                    nstate <= WRT1;
                else
                    nstate <= WRT0;
        WRT1:   nstate <= IDEL;
        REA0:   if(`DELAY_80NS)
                    nstate <= REA1;
                else
                    nstate <= REA0;
        REA1:   nstate <= IDEL;
        default:nstate <= IDEL;
    endcase
     
assign sram_addr =addr_r;

reg sdlink;
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        rd_data <= 16'b0;
    else if(cstate == REA1)
        rd_data <= sram_data;
         
always@(posedge clk_50 or negedge rst_n)
    if(!rst_n)
        sdlink <= 1'b0;
    else
        case(cstate)
            IDEL:   if(sram_wr_req)
                        sdlink <= 1'b1;
                    else if(sram_rd_req)
                        sdlink <= 1'b0;
                    else
                        sdlink <= 1'b0;
            WRT0:   sdlink <= 1'b1;
            default:sdlink <= 1'b0;
        endcase
     
assign sram_data = sdlink ? wr_data:16'hzzzz;
assign sram_wr_n = ~sdlink;
 
endmodule