data/full_repos/permissive/174263347/crtv10/hdl/crt_clock.v
data/verilator_xmls/0bc81d1d-058f-4835-9bda-cc4a5ebadd6f.xml
module crt_clock (clk, reset, pxclk, med_res, onemks);

    input           clk;
    input           reset;
	input           med_res;
	output			pxclk, onemks;

    reg             div2;
    reg     [3:0]   div16;



 	always @ (posedge reset or posedge clk)
    	if (reset)
            div2 <= 1'b0;
        else
            if (med_res)
                div2 <= 1'b1;
            else
                div2 <= ~div2;

    assign pxclk    = div2;



 	always @ (posedge reset or posedge clk)
    	if (reset)
            div16 <= 4'b0000;
        else
            div16 <= div16 + 1;

    assign onemks = (div16 == 4'b1111);

endmodule
module crt_clock (clk, reset, pxclk, med_res, onemks);


    input           clk;
    input           reset;
	input           med_res;
	output			pxclk, onemks;

    reg             div2;
    reg     [3:0]   div16;



 	always @ (posedge reset or posedge clk)
    	if (reset)
            div2 <= 1'b0;
        else
            if (med_res)
                div2 <= 1'b1;
            else
                div2 <= ~div2;

    assign pxclk    = div2;



 	always @ (posedge reset or posedge clk)
    	if (reset)
            div16 <= 4'b0000;
        else
            div16 <= div16 + 1;

    assign onemks = (div16 == 4'b1111);

endmodule