data/full_repos/permissive/160408009/components/COREDDR_TIP/1.6.106/rtl/vlog/core/flag_generator.v
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data/verilator_xmls/7c69de1f-dd89-4d7d-b88a-1a76945435a9.xml
module data_transition_detector(clock,data,sample,data_transition_flag);
parameter data_width=2;
input clock;
input [data_width-1:0] data;
input sample;
output  data_transition_flag;

reg [data_width-1:0] data_0;
reg [data_width-1:0] data_1;

reg                  sample_reg;

assign data_transition_flag=data_0!=data_1;

always @ (posedge clock) begin
  sample_reg <= sample;
  if (!sample_reg && sample)
  begin
    data_0<=data;
    data_1<=data_0;
  end
end

endmodule
module data_transition_detector(clock,data,sample,data_transition_flag);

parameter data_width=2;
input clock;
input [data_width-1:0] data;
input sample;
output  data_transition_flag;

reg [data_width-1:0] data_0;
reg [data_width-1:0] data_1;

reg                  sample_reg;

assign data_transition_flag=data_0!=data_1;

always @ (posedge clock) begin
  sample_reg <= sample;
  if (!sample_reg && sample)
  begin
    data_0<=data;
    data_1<=data_0;
  end
end

endmodule