data/full_repos/permissive/20688874/viterbi/nanosim/Files/conv_encoder.v
data/verilator_xmls/3f738bbe-dfed-487a-a386-bce97a0dba1b.xml
module conv_encoder (c, b, clk, reset);


   output [1:0] c;
   

   input  	b, clk, reset;
   

   reg [1:0] 	c;
   reg		d0, d1;

   always @ (posedge clk)
	 begin
		if (reset)
		  begin
		    d0 <= 1'b0;
		    d1 <= 1'b0;
		  end
		if (b)
		  begin
		    d1 <= d0;
		    d0 <= b;
		  end
	 end

   always @ (d0 or d1 or b)
	 begin
		c[0]  <= b^d0^d1;
		c[1]  <= b^d1;
	 end

endmodule
module conv_encoder (c, b, clk, reset);



   output [1:0] c;
   

   input  	b, clk, reset;
   

   reg [1:0] 	c;
   reg		d0, d1;

   always @ (posedge clk)
	 begin
		if (reset)
		  begin
		    d0 <= 1'b0;
		    d1 <= 1'b0;
		  end
		if (b)
		  begin
		    d1 <= d0;
		    d0 <= b;
		  end
	 end

   always @ (d0 or d1 or b)
	 begin
		c[0]  <= b^d0^d1;
		c[1]  <= b^d1;
	 end

endmodule