data/full_repos/permissive/101171422/sim/level_wait.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:19: Unsupported: Ignoring delay on this delayed statement.\n  wait (data_ready == 1) #1 data = data_bus;\n                         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101171422/sim/level_wait.v:19: Unsupported: wait statements\n  wait (data_ready == 1) #1 data = data_bus;\n  ^~~~\n%Error: data/full_repos/permissive/101171422/sim/level_wait.v:23: Unsupported or unknown PLI call: $monitor\n  $monitor("TIME = %g READ = %b READY = %b DATA = %b", \n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_bus = 8\'hDE;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10 mem_read = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #20 data_ready = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1  mem_read = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #1  data_ready = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #10 data_bus = 8\'hAD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #10 mem_read = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #20 data_ready = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1  mem_read = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1  data_ready = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/level_wait.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module level_wait
(
	output reg [7:0] data
);

	reg mem_read, data_ready;
	reg [7:0] data_bus;


	always @ (mem_read or data_bus or data_ready)
	begin
		data = 0;



		wait (data_ready == 1) #1 data = data_bus;
	end

	initial begin
		$monitor("TIME = %g READ = %b READY = %b DATA = %b", 
					$time, mem_read, data_ready, data);
		data_bus = 0;
		mem_read = 0;
		data_ready = 0;
		#10 data_bus = 8'hDE;
		#10 mem_read = 1;
		#20 data_ready = 1;
		#1  mem_read = 1;
		#1  data_ready = 0;
		#10 data_bus = 8'hAD;
		#10 mem_read = 1;
		#20 data_ready = 1;
		#1  mem_read = 1;
		#1  data_ready = 0;
		#10 $finish;
	end

endmodule
module level_wait
(
	output reg [7:0] data
);


	reg mem_read, data_ready;
	reg [7:0] data_bus;


	always @ (mem_read or data_bus or data_ready)
	begin
		data = 0;



		wait (data_ready == 1) #1 data = data_bus;
	end

	initial begin
		$monitor("TIME = %g READ = %b READY = %b DATA = %b", 
					$time, mem_read, data_ready, data);
		data_bus = 0;
		mem_read = 0;
		data_ready = 0;
		#10 data_bus = 8'hDE;
		#10 mem_read = 1;
		#20 data_ready = 1;
		#1  mem_read = 1;
		#1  data_ready = 0;
		#10 data_bus = 8'hAD;
		#10 mem_read = 1;
		#20 data_ready = 1;
		#1  mem_read = 1;
		#1  data_ready = 0;
		#10 $finish;
	end

endmodule