data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv
 line:63: before: "unsigned"
1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:23: Cannot find file containing module: 'shift_out_reg_right'\nshift_out_reg_right #(8) sr(CLK, EN & ready, bit_inc, DATA, sr_q);\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right.v\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/shift_out_reg_right.sv\n             shift_out_reg_right\n             shift_out_reg_right.v\n             shift_out_reg_right.sv\n             obj_dir/shift_out_reg_right\n             obj_dir/shift_out_reg_right.v\n             obj_dir/shift_out_reg_right.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:25: Cannot find file containing module: 'counter'\ncounter #(16) bit_counter (CLK, ready | bit_done, 1'b1, bit_cnt  );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:27: Cannot find file containing module: 'counter'\ncounter #(3)  byte_counter(CLK, ready,         bit_inc, byte_cnt );\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:31: Cannot find file containing module: 'ffd'\nffd #(1) parity_fd(CLK, RESET, (EN & ready) | bit_inc, par_fd_in, par_fd_q);\n^~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_tx.sv:32: Cannot find file containing module: 'ffd'\nffd #(1) output_fd(CLK, RESET, 1'b1, tx_logic, TX );\n^~~\n%Error: Exiting due to 5 error(s)\n"
module uart_tx ( input        CLK,
                 input        RESET,
                
                 input  [7:0] DATA,
                 input        EN,
                 output       READY,

                 input [15:0] BIT_TIME,
                 input        PARITY_EN,
                 input        PARITY_ODD,
                
                 output       TX );
                
logic        ready, par_ovr, fsm_ovr, fsm_val, sr_q, tx_logic,
             bit_done, byte_done, bit_inc, par_fd_in, par_fd_q;
logic [15:0] bit_cnt;
logic  [2:0] byte_cnt;

assign bit_done  = (bit_cnt  == BIT_TIME);
assign byte_done = (byte_cnt == 3'd7);
assign bit_inc   = bit_done & ~fsm_ovr;

shift_out_reg_right #(8) sr(CLK, EN & ready, bit_inc, DATA, sr_q);

counter #(16) bit_counter (CLK, ready | bit_done, 1'b1, bit_cnt  );

counter #(3)  byte_counter(CLK, ready,         bit_inc, byte_cnt );

assign par_fd_in = (EN & ready) ? PARITY_ODD : (par_fd_q ^ sr_q);

ffd #(1) parity_fd(CLK, RESET, (EN & ready) | bit_inc, par_fd_in, par_fd_q);
ffd #(1) output_fd(CLK, RESET, 1'b1, tx_logic, TX );

uart_tx_fsm fsm( .CLK       ( CLK       ),
                 .RESET     ( RESET     ),
                 .EN        ( EN        ),
                 .BIT_DONE  ( bit_done  ),
                 .BYTE_DONE ( byte_done ),
                 .PARITY_EN ( PARITY_EN ),
                 .READY     ( ready     ),
                 .PAR_OVR   ( par_ovr   ),
                 .FSM_OVR   ( fsm_ovr   ),
                 .FSM_VAL   ( fsm_val   ) );

assign READY = ready;
assign tx_logic = par_ovr ? par_fd_q :
                  fsm_ovr ? fsm_val  : 
                                sr_q ;
                
endmodule
module uart_tx ( input        CLK,
                 input        RESET,
                
                 input  [7:0] DATA,
                 input        EN,
                 output       READY,

                 input [15:0] BIT_TIME,
                 input        PARITY_EN,
                 input        PARITY_ODD,
                
                 output       TX );

                
logic        ready, par_ovr, fsm_ovr, fsm_val, sr_q, tx_logic,
             bit_done, byte_done, bit_inc, par_fd_in, par_fd_q;
logic [15:0] bit_cnt;
logic  [2:0] byte_cnt;

assign bit_done  = (bit_cnt  == BIT_TIME);
assign byte_done = (byte_cnt == 3'd7);
assign bit_inc   = bit_done & ~fsm_ovr;

shift_out_reg_right #(8) sr(CLK, EN & ready, bit_inc, DATA, sr_q);

counter #(16) bit_counter (CLK, ready | bit_done, 1'b1, bit_cnt  );

counter #(3)  byte_counter(CLK, ready,         bit_inc, byte_cnt );

assign par_fd_in = (EN & ready) ? PARITY_ODD : (par_fd_q ^ sr_q);

ffd #(1) parity_fd(CLK, RESET, (EN & ready) | bit_inc, par_fd_in, par_fd_q);
ffd #(1) output_fd(CLK, RESET, 1'b1, tx_logic, TX );

uart_tx_fsm fsm( .CLK       ( CLK       ),
                 .RESET     ( RESET     ),
                 .EN        ( EN        ),
                 .BIT_DONE  ( bit_done  ),
                 .BYTE_DONE ( byte_done ),
                 .PARITY_EN ( PARITY_EN ),
                 .READY     ( ready     ),
                 .PAR_OVR   ( par_ovr   ),
                 .FSM_OVR   ( fsm_ovr   ),
                 .FSM_VAL   ( fsm_val   ) );

assign READY = ready;
assign tx_logic = par_ovr ? par_fd_q :
                  fsm_ovr ? fsm_val  : 
                                sr_q ;
                
endmodule