data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v
 line:148: before: "$"
1: b'%Error: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:40: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("spi_ram_slave.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:41: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, test);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #456 cs = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:138: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:140: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:141: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:143: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #32 sck = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #100 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111499712/fw/sim/spi_ram_slave.v:152: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = !clk;\n       ^\n%Error: Exiting due to 2 error(s), 67 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
parameter ClkFreq = 50000000;

reg cs = 1;
reg sck = 0;
reg mosi = 0;

initial begin
  $dumpfile("spi_ram_slave.vcd");
  $dumpvars(0, test);

  #456 cs = 0;


  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;


  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;

  cs = 1;
  #100 $finish;
end

reg clk = 0;
always #10 clk = !clk;

wire ram_wr;
wire [12:0] ram_addr;
wire [15:0] ram_data;

spi_ram_slave spi_ram_slave(clk, sck, cs, mosi, ram_addr, ram_data, ram_wr);

endmodule
module test;

parameter ClkFreq = 50000000;

reg cs = 1;
reg sck = 0;
reg mosi = 0;

initial begin
  $dumpfile("spi_ram_slave.vcd");
  $dumpvars(0, test);

  #456 cs = 0;


  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;


  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b0;
  #32 sck = 1;
  #32 sck = 0;
  mosi = 1'b1;

  cs = 1;
  #100 $finish;
end

reg clk = 0;
always #10 clk = !clk;

wire ram_wr;
wire [12:0] ram_addr;
wire [15:0] ram_data;

spi_ram_slave spi_ram_slave(clk, sck, cs, mosi, ram_addr, ram_data, ram_wr);

endmodule