data/full_repos/permissive/168395472/problems/08_cpu_v2/reg_file.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/168395472/problems/08_cpu_v2/reg_file.v:24: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'raddr0\' generates 5 bits.\n                                                                                     : ... In instance reg_file\nassign rdata0 = (raddr0 != 32\'b0) ? x[raddr0] : 32\'b0;\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/168395472/problems/08_cpu_v2/reg_file.v:25: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'raddr1\' generates 5 bits.\n                                                                                     : ... In instance reg_file\nassign rdata1 = (raddr1 != 32\'b0) ? x[raddr1] : 32\'b0;\n                        ^~\n%Error: Exiting due to 2 warning(s)\n'
module reg_file(
    input clk,
    input [4:0]raddr0,
    input [4:0]raddr1,
    input [4:0]waddr,
    input [31:0]wdata,
    input we,

    output [31:0]rdata0,
    output [31:0]rdata1
);

reg [31:0]x[31:0];

genvar i;
generate
for (i = 0; i < 32; i = i + 1)
begin : reg_init
    initial
        x[i] = 32'b0;
end
endgenerate

assign rdata0 = (raddr0 != 32'b0) ? x[raddr0] : 32'b0;
assign rdata1 = (raddr1 != 32'b0) ? x[raddr1] : 32'b0;

always @(posedge clk) begin
    if (we) begin
        x[waddr] <= wdata;
    end
end

endmodule
module reg_file(
    input clk,
    input [4:0]raddr0,
    input [4:0]raddr1,
    input [4:0]waddr,
    input [31:0]wdata,
    input we,

    output [31:0]rdata0,
    output [31:0]rdata1
);


reg [31:0]x[31:0];

genvar i;
generate
for (i = 0; i < 32; i = i + 1)
begin : reg_init
    initial
        x[i] = 32'b0;
end
endgenerate

assign rdata0 = (raddr0 != 32'b0) ? x[raddr0] : 32'b0;
assign rdata1 = (raddr1 != 32'b0) ? x[raddr1] : 32'b0;

always @(posedge clk) begin
    if (we) begin
        x[waddr] <= wdata;
    end
end

endmodule