data/full_repos/permissive/21051978/processor/regfiletb.v
 line:337: before: "$"
1: b'%Error: data/full_repos/permissive/21051978/processor/regfiletb.v:23: Cannot find include file: regfile.v\n`include "regfile.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/regfile.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/regfile.v.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/regfile.v.sv\n             regfile.v\n             regfile.v.v\n             regfile.v.sv\n             obj_dir/regfile.v\n             obj_dir/regfile.v.v\n             obj_dir/regfile.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:111: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:112: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:181: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:188: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:195: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:202: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:209: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:216: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:223: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:230: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:237: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/regfiletb.v:254: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Error: Exiting due to 1 error(s), 14 warning(s)\n'
module tb_regfile();

	parameter DEPTH = 8;

	parameter WIDTH = 8;
	
	
	
	
	
	
	


	


	wire [WIDTH-1:0] d_out;
	
	
	
	
	
	
	

	


	reg clock,wr_en;

	reg [WIDTH-1:0] d_in;

	reg [DEPTH-1:0] w_addr,r_addr ;
	
	
	
	
	
	
	
	



	
	
	
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end	
	
	
	
	
	
	
	
	
	

	

	regfile rg (


		d_out,d_in,w_addr,r_addr,wr_en,clock);
	
	
	
	

	

	initial
	begin

		$display($time, " << Starting the simulation >>");

		d_in=8'd6;
		w_addr=3'd0;
		r_addr=3'd0;
		wr_en=1;
		
		
		#10
		d_in=8'd7;
		w_addr=3'd0;
		r_addr=3'd0;
		wr_en=0;
		

		#10
		d_in=8'd6;
		w_addr=3'd2;
		r_addr=3'd0;
		wr_en=1;
		
		
		#10
		d_in=8'd5;
		w_addr=3'd3;
		r_addr=3'd1;
		wr_en=1;
		
		
		#10
		d_in=8'd100;
		w_addr=3'd4;
		r_addr=3'd7;
		wr_en=1;
		
		
		#10
		d_in=8'd200;
		w_addr=3'd5;
		r_addr=3'd6;
		wr_en=1;
		

		#10
		d_in=8'd3;
		w_addr=3'd4;
		r_addr=3'd2;
		wr_en=0;
		
		
		#10
		d_in=8'd2;
		w_addr=3'd5;
		r_addr=3'd3;
		wr_en=0;
		
		
		#10
		d_in=8'd1;
		w_addr=3'd6;
		r_addr=3'd4;
		wr_en=0;
		
		
		#10
		d_in=8'd0;
		w_addr=3'd7;
		r_addr=3'd5;
		wr_en=0;
		
		
		#10
		d_in=8'd5;
		w_addr=3'd7;
		r_addr=3'd1;
		wr_en=1;
		
		
		#10
		d_in=8'd0;
		w_addr=3'd2;
		r_addr=3'd7;
		wr_en=0;
		
		
		
		
		
		
		
		
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_regfile();


	parameter DEPTH = 8;

	parameter WIDTH = 8;
	
	
	
	
	
	
	


	


	wire [WIDTH-1:0] d_out;
	
	
	
	
	
	
	

	


	reg clock,wr_en;

	reg [WIDTH-1:0] d_in;

	reg [DEPTH-1:0] w_addr,r_addr ;
	
	
	
	
	
	
	
	



	
	
	
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end	
	
	
	
	
	
	
	
	
	

	

	regfile rg (


		d_out,d_in,w_addr,r_addr,wr_en,clock);
	
	
	
	

	

	initial
	begin

		$display($time, " << Starting the simulation >>");

		d_in=8'd6;
		w_addr=3'd0;
		r_addr=3'd0;
		wr_en=1;
		
		
		#10
		d_in=8'd7;
		w_addr=3'd0;
		r_addr=3'd0;
		wr_en=0;
		

		#10
		d_in=8'd6;
		w_addr=3'd2;
		r_addr=3'd0;
		wr_en=1;
		
		
		#10
		d_in=8'd5;
		w_addr=3'd3;
		r_addr=3'd1;
		wr_en=1;
		
		
		#10
		d_in=8'd100;
		w_addr=3'd4;
		r_addr=3'd7;
		wr_en=1;
		
		
		#10
		d_in=8'd200;
		w_addr=3'd5;
		r_addr=3'd6;
		wr_en=1;
		

		#10
		d_in=8'd3;
		w_addr=3'd4;
		r_addr=3'd2;
		wr_en=0;
		
		
		#10
		d_in=8'd2;
		w_addr=3'd5;
		r_addr=3'd3;
		wr_en=0;
		
		
		#10
		d_in=8'd1;
		w_addr=3'd6;
		r_addr=3'd4;
		wr_en=0;
		
		
		#10
		d_in=8'd0;
		w_addr=3'd7;
		r_addr=3'd5;
		wr_en=0;
		
		
		#10
		d_in=8'd5;
		w_addr=3'd7;
		r_addr=3'd1;
		wr_en=1;
		
		
		#10
		d_in=8'd0;
		w_addr=3'd2;
		r_addr=3'd7;
		wr_en=0;
		
		
		
		
		
		
		
		
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule