data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v
1: b'%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:36: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v.v\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:52: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]           cpu_data_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegBus]           cpu_data_i,\n                   ^\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:53: Define or directive not defined: \'`PhyAddrBus\'\n input wire[`PhyAddrBus]       cpu_addr_i,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:55: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegSel]           cpu_sel_i,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:55: Define or directive not defined: \'`RegSel\'\n input wire[`RegSel]           cpu_sel_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:56: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]           cpu_data_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:59: Define or directive not defined: \'`WishboneDataBus\'\n input wire[`WishboneDataBus]  wishbone_data_i,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:61: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[`PhyAddrBus]      wishbone_addr_o,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:61: Define or directive not defined: \'`PhyAddrBus\'\n output wire[`PhyAddrBus]      wishbone_addr_o,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:62: Define or directive not defined: \'`WishboneDataBus\'\n output wire[`WishboneDataBus] wishbone_data_o,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:64: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[`WishboneSelBus]  wishbone_sel_o,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:64: Define or directive not defined: \'`WishboneSelBus\'\n output wire[`WishboneSelBus]  wishbone_sel_o,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:66: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire                   wishbone_cyc_o,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:68: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire                    stallreq        \n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:76: syntax error, unexpected assign\n assign process = (cpu_ce_i == 1\'b1) && (flush_i == `NoFlush);\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:76: Define or directive not defined: \'`NoFlush\'\n assign process = (cpu_ce_i == 1\'b1) && (flush_i == `NoFlush);\n                                                    ^~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:92: syntax error, unexpected assign\n assign cpu_req_id = (process == 1\'b1) ? (cpu_ack_id ^ 1\'b1) : cpu_ack_id;\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:107: syntax error, unexpected assign\n assign request_bus = (process == 1\'b1) && (wishbone_ack_id != cpu_req_id || wishbone_ack_valid == 1\'b0); \n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:112: syntax error, unexpected always\n always @ (posedge cpu_clk or negedge rst_n)\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:113: Define or directive not defined: \'`RstEnable\'\n  if(rst_n == `RstEnable)\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:118: Define or directive not defined: \'`Stop\'\n  else if(stallreq != `Stop && (stall_this_i != `Stop || flush_i == `NoFlush))\n                      ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:118: Define or directive not defined: \'`Stop\'\n  else if(stallreq != `Stop && (stall_this_i != `Stop || flush_i == `NoFlush))\n                                                ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:118: Define or directive not defined: \'`NoFlush\'\n  else if(stallreq != `Stop && (stall_this_i != `Stop || flush_i == `NoFlush))\n                                                                    ^~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:125: Define or directive not defined: \'`RstEnable\'\n  if(rst_n == `RstEnable)\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:140: Define or directive not defined: \'`WishboneDataBus\'\n assign wishbone_data_o = cpu_data_i[`WishboneDataBus];\n                                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:143: Define or directive not defined: \'`NoFlush\'\n assign wishbone_cyc_o = ((request_bus) | ((flush_i == `NoFlush) & ~(&req_cnt) & (stallreq == `Stop || stall_this_i == `NoStop)));\n                                                       ^~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:143: Define or directive not defined: \'`Stop\'\n assign wishbone_cyc_o = ((request_bus) | ((flush_i == `NoFlush) & ~(&req_cnt) & (stallreq == `Stop || stall_this_i == `NoStop)));\n                                                                                              ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:143: Define or directive not defined: \'`NoStop\'\n assign wishbone_cyc_o = ((request_bus) | ((flush_i == `NoFlush) & ~(&req_cnt) & (stallreq == `Stop || stall_this_i == `NoStop)));\n                                                                                                                       ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:146: Define or directive not defined: \'`WishboneSelBus\'\n assign wishbone_sel_o = cpu_sel_i[`WishboneSelBus];\n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:151: syntax error, unexpected always\n always @ (posedge wishbone_clk or negedge rst_n)\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:152: Define or directive not defined: \'`RstEnable\'\n  if(rst_n == `RstEnable)\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:154: Define or directive not defined: \'`Flush\'\n  else if(flush_i == `Flush)\n                     ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/wishbone_bus_if.v:162: Define or directive not defined: \'`NoFlush\'\n assign stallreq = (|stall_delay) && (flush_i == `NoFlush);\n                                                 ^~~~~~~~\n%Error: Exiting due to 34 error(s)\n'
module wishbone_bus_if(
	input wire wishbone_clk,

	input wire cpu_clk,

	input wire rst_n,
	

	input wire[5:0]               stall_i,
	input                         stall_this_i,
	input                         flush_i,
	

	input wire                    cpu_ce_i,
	input wire[`RegBus]           cpu_data_i,
	input wire[`PhyAddrBus]       cpu_addr_i,
	input wire                    cpu_we_i,
	input wire[`RegSel]           cpu_sel_i,
	output reg[`RegBus]           cpu_data_o,
	

	input wire[`WishboneDataBus]  wishbone_data_i,
	input wire                    wishbone_ack_i,
	output wire[`PhyAddrBus]      wishbone_addr_o,
	output wire[`WishboneDataBus] wishbone_data_o,
	output wire                   wishbone_we_o,
	output wire[`WishboneSelBus]  wishbone_sel_o,
	output wire                   wishbone_stb_o,
	output wire                   wishbone_cyc_o,

	output wire                    stallreq	       
	
);

	parameter delay = 10;


	wire process;
	assign process = (cpu_ce_i == 1'b1) && (flush_i == `NoFlush);












	reg cpu_ack_id;
	wire cpu_req_id;
	reg wishbone_ack_id;
	assign cpu_req_id = (process == 1'b1) ? (cpu_ack_id ^ 1'b1) : cpu_ack_id;


	reg wishbone_ack_valid;










	wire request_bus;
	assign request_bus = (process == 1'b1) && (wishbone_ack_id != cpu_req_id || wishbone_ack_valid == 1'b0); 


	parameter cyc_len_log_2 = 8;
	reg [(cyc_len_log_2 - 1) : 0] req_cnt;
	always @ (posedge cpu_clk or negedge rst_n)
		if(rst_n == `RstEnable)
		begin
			cpu_ack_id <= 1'b0;
			req_cnt <= {cyc_len_log_2{1'b0}};
		end
		else if(stallreq != `Stop && (stall_this_i != `Stop || flush_i == `NoFlush))
		begin
			cpu_ack_id <= wishbone_ack_id;
			req_cnt <= req_cnt + 1'b1;
		end

	always @ (posedge wishbone_clk or negedge rst_n)
		if(rst_n == `RstEnable)
		begin
			wishbone_ack_valid <= 1'b0;
			wishbone_ack_id <= 1'b0;
		end
		else if((wishbone_ack_i & request_bus) == 1'b1)
		begin
			wishbone_ack_valid <= 1'b1;
			wishbone_ack_id <= cpu_req_id;

			cpu_data_o <= wishbone_data_i;
		end


	assign wishbone_addr_o = cpu_addr_i;
	assign wishbone_data_o = cpu_data_i[`WishboneDataBus];


	assign wishbone_cyc_o = ((request_bus) | ((flush_i == `NoFlush) & ~(&req_cnt) & (stallreq == `Stop || stall_this_i == `NoStop)));
	assign wishbone_stb_o = request_bus; 
	assign wishbone_we_o = cpu_we_i;
	assign wishbone_sel_o = cpu_sel_i[`WishboneSelBus];

	reg[delay:0] stall_delay;
	reg not_use;

	always @ (posedge wishbone_clk or negedge rst_n)
		if(rst_n == `RstEnable)
			stall_delay <= {1'b0};
		else if(flush_i == `Flush)
			stall_delay <= {1'b0};
		else if((wishbone_ack_i & request_bus) == 1'b1)
			{not_use, stall_delay} <= {stall_delay, 1'b0};
		else
			{not_use, stall_delay} <= {stall_delay, request_bus};


	assign stallreq = (|stall_delay) && (flush_i == `NoFlush);

endmodule
module wishbone_bus_if(
	input wire wishbone_clk,

	input wire cpu_clk,

	input wire rst_n,
	

	input wire[5:0]               stall_i,
	input                         stall_this_i,
	input                         flush_i,
	

	input wire                    cpu_ce_i,
	input wire[`RegBus]           cpu_data_i,
	input wire[`PhyAddrBus]       cpu_addr_i,
	input wire                    cpu_we_i,
	input wire[`RegSel]           cpu_sel_i,
	output reg[`RegBus]           cpu_data_o,
	

	input wire[`WishboneDataBus]  wishbone_data_i,
	input wire                    wishbone_ack_i,
	output wire[`PhyAddrBus]      wishbone_addr_o,
	output wire[`WishboneDataBus] wishbone_data_o,
	output wire                   wishbone_we_o,
	output wire[`WishboneSelBus]  wishbone_sel_o,
	output wire                   wishbone_stb_o,
	output wire                   wishbone_cyc_o,

	output wire                    stallreq	       
	
);


	parameter delay = 10;


	wire process;
	assign process = (cpu_ce_i == 1'b1) && (flush_i == `NoFlush);












	reg cpu_ack_id;
	wire cpu_req_id;
	reg wishbone_ack_id;
	assign cpu_req_id = (process == 1'b1) ? (cpu_ack_id ^ 1'b1) : cpu_ack_id;


	reg wishbone_ack_valid;










	wire request_bus;
	assign request_bus = (process == 1'b1) && (wishbone_ack_id != cpu_req_id || wishbone_ack_valid == 1'b0); 


	parameter cyc_len_log_2 = 8;
	reg [(cyc_len_log_2 - 1) : 0] req_cnt;
	always @ (posedge cpu_clk or negedge rst_n)
		if(rst_n == `RstEnable)
		begin
			cpu_ack_id <= 1'b0;
			req_cnt <= {cyc_len_log_2{1'b0}};
		end
		else if(stallreq != `Stop && (stall_this_i != `Stop || flush_i == `NoFlush))
		begin
			cpu_ack_id <= wishbone_ack_id;
			req_cnt <= req_cnt + 1'b1;
		end

	always @ (posedge wishbone_clk or negedge rst_n)
		if(rst_n == `RstEnable)
		begin
			wishbone_ack_valid <= 1'b0;
			wishbone_ack_id <= 1'b0;
		end
		else if((wishbone_ack_i & request_bus) == 1'b1)
		begin
			wishbone_ack_valid <= 1'b1;
			wishbone_ack_id <= cpu_req_id;

			cpu_data_o <= wishbone_data_i;
		end


	assign wishbone_addr_o = cpu_addr_i;
	assign wishbone_data_o = cpu_data_i[`WishboneDataBus];


	assign wishbone_cyc_o = ((request_bus) | ((flush_i == `NoFlush) & ~(&req_cnt) & (stallreq == `Stop || stall_this_i == `NoStop)));
	assign wishbone_stb_o = request_bus; 
	assign wishbone_we_o = cpu_we_i;
	assign wishbone_sel_o = cpu_sel_i[`WishboneSelBus];

	reg[delay:0] stall_delay;
	reg not_use;

	always @ (posedge wishbone_clk or negedge rst_n)
		if(rst_n == `RstEnable)
			stall_delay <= {1'b0};
		else if(flush_i == `Flush)
			stall_delay <= {1'b0};
		else if((wishbone_ack_i & request_bus) == 1'b1)
			{not_use, stall_delay} <= {stall_delay, 1'b0};
		else
			{not_use, stall_delay} <= {stall_delay, request_bus};


	assign stallreq = (|stall_delay) && (flush_i == `NoFlush);

endmodule