data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/stimulus/testbench138.v
 line:11: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/stimulus/testbench138.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #20 DataIn=$random;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/stimulus/testbench138.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #40 G1=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/stimulus/testbench138.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #20 G2AN=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/stimulus/testbench138.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #40 G2BN=1;\n  ^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/stimulus/testbench138.v:7: Cannot find file containing module: \'HC138\'\nHC138 u1(DataIn,Dataout,G1,G2AN,G2BN);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/stimulus,data/full_repos/permissive/165160692/HC138\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/stimulus,data/full_repos/permissive/165160692/HC138.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/stimulus,data/full_repos/permissive/165160692/HC138.sv\n             HC138\n             HC138.v\n             HC138.sv\n             obj_dir/HC138\n             obj_dir/HC138.v\n             obj_dir/HC138.sv\n%Warning-WIDTH: data/full_repos/permissive/165160692/04.FPGA/5932_74HC138/stimulus/testbench138.v:12: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                    : ... In instance testbench\n  #20 DataIn=$random;\n            ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
reg[2:0]DataIn;reg G1,G2AN,G2BN;
wire[7:0]Dataout;

HC138 u1(DataIn,Dataout,G1,G2AN,G2BN);
initial
begin
  DataIn=0;
  repeat(20)
  #20 DataIn=$random;
end

initial
 begin
  G1=0;
  #40 G1=1;
end

initial
 begin
  G2AN=0;
  #20 G2AN=1;
end

initial
 begin
  G2BN=0;
  #40 G2BN=1;
end
endmodule
module testbench();

reg[2:0]DataIn;reg G1,G2AN,G2BN;
wire[7:0]Dataout;

HC138 u1(DataIn,Dataout,G1,G2AN,G2BN);
initial
begin
  DataIn=0;
  repeat(20)
  #20 DataIn=$random;
end

initial
 begin
  G1=0;
  #40 G1=1;
end

initial
 begin
  G2AN=0;
  #20 G2AN=1;
end

initial
 begin
  G2BN=0;
  #40 G2BN=1;
end
endmodule