data/full_repos/permissive/154350027/rtl/tcpip/mac_pack.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/mac_pack.v:258: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'mac_fcs_cnt\' generates 2 bits.\n                                                                             : ... In instance mac_pack\n mac_fcs_cnt_dly <= mac_fcs_cnt;\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/mac_pack.v:293: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h0\' generates 2 bits.\n                                                                             : ... In instance mac_pack\n case(mac_fcs_cnt_dly2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/mac_pack.v:293: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h1\' generates 2 bits.\n                                                                             : ... In instance mac_pack\n case(mac_fcs_cnt_dly2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/mac_pack.v:293: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n                                                                             : ... In instance mac_pack\n case(mac_fcs_cnt_dly2)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/154350027/rtl/tcpip/mac_pack.v:293: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n                                                                             : ... In instance mac_pack\n case(mac_fcs_cnt_dly2)\n ^~~~\n%Error: data/full_repos/permissive/154350027/rtl/tcpip/mac_pack.v:342: Cannot find file containing module: \'crc32\'\n  crc32 u_crc32\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/154350027/rtl/tcpip,data/full_repos/permissive/154350027/crc32\n             data/full_repos/permissive/154350027/rtl/tcpip,data/full_repos/permissive/154350027/crc32.v\n             data/full_repos/permissive/154350027/rtl/tcpip,data/full_repos/permissive/154350027/crc32.sv\n             crc32\n             crc32.v\n             crc32.sv\n             obj_dir/crc32\n             obj_dir/crc32.v\n             obj_dir/crc32.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module mac_pack
  (
   input wire 	     clk,
   input wire 	     rst_n,

   input wire [47:0] des_mac_addr, 
   input wire [47:0] src_mac_addr,
   input wire [15:0] prot_type,


   input wire 	     app_fifo_empty,
   output reg 	     mac_head_end,
   input wire 	     mac_data_end,


   output reg 	     mac_wram_clk_en,
   output reg [9:0]  mac_wram_addr,
   output reg [7:0]  mac_wram_dat,

   output reg 	     mac_rram_clk_en,
   output reg [9:0]  mac_rram_addr,
   input wire [7:0]  mac_rram_dat,


   output wire 	     fcs_get,
   input wire 	     fcs_en,
   input wire [31:0] fcs,
   


   output reg 	     tx_en,
   output reg [7:0]  txd,
   output reg 	     tx_er,


   output wire 	     tx_busy
   );


  parameter IDLE      = 3'd0;
  parameter HEAD      = 3'd1;
  parameter PKT_DATA  = 3'd2;
  parameter FCS_START = 3'd3;
  parameter SEND      = 3'd4;
  parameter FCS	      = 3'd5;
  parameter DONE      = 3'd6;
  
  reg [2:0] 	     mac_cs;
  reg [2:0] 	     mac_ns;

  reg [4:0] 	     mac_head_cnt;
  reg [1:0] 	     mac_fcs_cnt;
  reg [9:0] 	     mac_send_cnt;
  
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_cs <= IDLE;
    else
      mac_cs <= mac_ns;

  always@(*)
    case(mac_cs)
      IDLE:
	if(!app_fifo_empty)mac_ns = HEAD;
	else mac_ns = IDLE;
      HEAD:
	if(mac_head_cnt == 5'd21)mac_ns = PKT_DATA;
	else mac_ns = HEAD;
      PKT_DATA:
	if(mac_data_end)mac_ns = FCS_START;
	else mac_ns = PKT_DATA;
      FCS_START:
	mac_ns = SEND;
      SEND:
	if(mac_send_cnt == 10'd1010)mac_ns = FCS;
	else mac_ns = SEND;
      FCS:
	if(mac_fcs_cnt == 2'd3)mac_ns = DONE;
	else mac_ns = FCS;
      DONE:
	mac_ns = IDLE;
      default:
	mac_ns = IDLE;
    endcase


  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_head_cnt <= 5'd0;
    else if(mac_cs == HEAD)
      mac_head_cnt <= mac_head_cnt + 1'b1;
    else
      mac_head_cnt <= 5'd0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_fcs_cnt <= 2'd0;
    else if(mac_cs == FCS)
      mac_fcs_cnt <= mac_fcs_cnt + 1'b1;
    else
      mac_fcs_cnt <= 2'd0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)  
      mac_send_cnt <= 10'd0;
    else if(mac_cs == SEND)
      mac_send_cnt <= mac_send_cnt + 1'b1;
    else
      mac_send_cnt <= 10'd0;
  

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_wram_clk_en <= 1'b0;
    else if(mac_cs == HEAD)
      mac_wram_clk_en <= 1'b1;
    else
      mac_wram_clk_en <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_wram_addr <= 10'd0;
    else if(mac_cs == HEAD)
      mac_wram_addr <= {5'b0, mac_head_cnt};



  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_wram_dat <= 8'd0;
    else if(mac_cs == HEAD)
      begin
	case(mac_head_cnt)

	  5'd0, 5'd1, 5'd2, 5'd3, 5'd4, 5'd5, 5'd6:
	    mac_wram_dat <= 8'h55;
	  5'd7:
	    mac_wram_dat <= 8'hd5;

	  5'd8:
	    mac_wram_dat <= des_mac_addr[47:40];
	  5'd9:
	    mac_wram_dat <= des_mac_addr[39:32];
	  5'd10:
	    mac_wram_dat <= des_mac_addr[31:24];
	  5'd11:
	    mac_wram_dat <= des_mac_addr[23:16];
	  5'd12:
	    mac_wram_dat <= des_mac_addr[15:8];
	  5'd13:
	    mac_wram_dat <= des_mac_addr[7:0];

	  5'd14:
	    mac_wram_dat <= src_mac_addr[47:40];
	  5'd15:
	    mac_wram_dat <= src_mac_addr[39:32];
	  5'd16:
	    mac_wram_dat <= src_mac_addr[31:24];
	  5'd17:
	    mac_wram_dat <= src_mac_addr[23:16];
	  5'd18:
	    mac_wram_dat <= src_mac_addr[15:8];
	  5'd19:
	    mac_wram_dat <= src_mac_addr[7:0];

	  5'd20:
	    mac_wram_dat <= prot_type[15:8];
	  5'd21:
	    mac_wram_dat <= prot_type[7:0];
	endcase
      end









    else
      mac_wram_dat <= 8'd0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_head_end <= 1'b0;
    else if(mac_cs == HEAD && mac_head_cnt == 5'd21)
      mac_head_end <= 1'b1;
    else
      mac_head_end <= 1'b0;
  

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_rram_clk_en <= 1'b0;
    else if(mac_cs == SEND)
      mac_rram_clk_en <= 1'b1;
    else
      mac_rram_clk_en <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_rram_addr <= 10'd0;
    else
      mac_rram_addr <= mac_send_cnt;


  reg st_send_dly;
  reg st_send_dly2;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      st_send_dly <= 1'b0;
    else if(mac_cs == FCS)
      st_send_dly <= 1'b1;
    else
      st_send_dly <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      st_send_dly2 <= 1'b0;
    else
      st_send_dly2 <= st_send_dly;
 

  wire [31:0] crc32;
  reg 	      crc32_start;
  reg [7:0]   mac_fcs_cnt_dly;
  reg [7:0]   mac_fcs_cnt_dly2;
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      crc32_start <= 1'b0;
    else if(mac_cs == FCS_START)
      crc32_start <= 1'b1;
    else
      crc32_start <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      begin
	mac_fcs_cnt_dly <= 8'b0;
	mac_fcs_cnt_dly2 <= 8'b0;
      end
    else
      begin
	mac_fcs_cnt_dly <= mac_fcs_cnt;
	mac_fcs_cnt_dly2 <= mac_fcs_cnt_dly;
      end
      










	  
  reg tx_en_tmp;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      begin
	tx_en_tmp <= 1'b0;
	tx_en <= 1'b0;
      end
    else
      begin
	tx_en_tmp <= mac_rram_clk_en;
	tx_en <= tx_en_tmp | st_send_dly2;
      end

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      txd <= 8'b0;
    else if(tx_en_tmp)
      txd <= mac_rram_dat;
    else if(st_send_dly2)
      begin
	case(mac_fcs_cnt_dly2)
	  2'b00: txd <= crc32[7:0];
	  2'b01: txd <= crc32[15:8];
	  2'b10: txd <= crc32[23:16];
	  2'b11: txd <= crc32[31:24];
	endcase
      end

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      tx_er <= 1'b0;

  reg tx_busy_dly1;
  reg tx_busy_dly2;
  reg tx_busy_dly3;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      tx_busy_dly1 <= 1'b0;
    else if(mac_cs == FCS_START || mac_cs == SEND || 
	    mac_cs == FCS)
      tx_busy_dly1 <= 1'b1;
    else
      tx_busy_dly1 <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      begin
	tx_busy_dly2 <= 1'b0;
	tx_busy_dly3 <= 1'b0;
      end
    else
      begin
	tx_busy_dly2 <= tx_busy_dly1;
	tx_busy_dly3 <= tx_busy_dly2;
      end

  assign tx_busy = tx_busy_dly1 | tx_busy_dly2 | tx_busy_dly3;


  reg crc_dat_en;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      crc_dat_en <= 1'b0;
    else if(mac_rram_clk_en && mac_rram_addr > 10'd7)
      crc_dat_en <= 1'b1;
    else
      crc_dat_en <= 1'b0;

  
  crc32 u_crc32
    (

     .crc32				(crc32[31:0]),

     .clk				(clk),
     .rst_n				(rst_n),
     .start				(crc32_start),
     .dat_en				(crc_dat_en),
     .dat				(mac_rram_dat[7:0])
     );
  

  
endmodule
module mac_pack
  (
   input wire 	     clk,
   input wire 	     rst_n,

   input wire [47:0] des_mac_addr, 
   input wire [47:0] src_mac_addr,
   input wire [15:0] prot_type,


   input wire 	     app_fifo_empty,
   output reg 	     mac_head_end,
   input wire 	     mac_data_end,


   output reg 	     mac_wram_clk_en,
   output reg [9:0]  mac_wram_addr,
   output reg [7:0]  mac_wram_dat,

   output reg 	     mac_rram_clk_en,
   output reg [9:0]  mac_rram_addr,
   input wire [7:0]  mac_rram_dat,


   output wire 	     fcs_get,
   input wire 	     fcs_en,
   input wire [31:0] fcs,
   


   output reg 	     tx_en,
   output reg [7:0]  txd,
   output reg 	     tx_er,


   output wire 	     tx_busy
   );



  parameter IDLE      = 3'd0;
  parameter HEAD      = 3'd1;
  parameter PKT_DATA  = 3'd2;
  parameter FCS_START = 3'd3;
  parameter SEND      = 3'd4;
  parameter FCS	      = 3'd5;
  parameter DONE      = 3'd6;
  
  reg [2:0] 	     mac_cs;
  reg [2:0] 	     mac_ns;

  reg [4:0] 	     mac_head_cnt;
  reg [1:0] 	     mac_fcs_cnt;
  reg [9:0] 	     mac_send_cnt;
  
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_cs <= IDLE;
    else
      mac_cs <= mac_ns;

  always@(*)
    case(mac_cs)
      IDLE:
	if(!app_fifo_empty)mac_ns = HEAD;
	else mac_ns = IDLE;
      HEAD:
	if(mac_head_cnt == 5'd21)mac_ns = PKT_DATA;
	else mac_ns = HEAD;
      PKT_DATA:
	if(mac_data_end)mac_ns = FCS_START;
	else mac_ns = PKT_DATA;
      FCS_START:
	mac_ns = SEND;
      SEND:
	if(mac_send_cnt == 10'd1010)mac_ns = FCS;
	else mac_ns = SEND;
      FCS:
	if(mac_fcs_cnt == 2'd3)mac_ns = DONE;
	else mac_ns = FCS;
      DONE:
	mac_ns = IDLE;
      default:
	mac_ns = IDLE;
    endcase


  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_head_cnt <= 5'd0;
    else if(mac_cs == HEAD)
      mac_head_cnt <= mac_head_cnt + 1'b1;
    else
      mac_head_cnt <= 5'd0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_fcs_cnt <= 2'd0;
    else if(mac_cs == FCS)
      mac_fcs_cnt <= mac_fcs_cnt + 1'b1;
    else
      mac_fcs_cnt <= 2'd0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)  
      mac_send_cnt <= 10'd0;
    else if(mac_cs == SEND)
      mac_send_cnt <= mac_send_cnt + 1'b1;
    else
      mac_send_cnt <= 10'd0;
  

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_wram_clk_en <= 1'b0;
    else if(mac_cs == HEAD)
      mac_wram_clk_en <= 1'b1;
    else
      mac_wram_clk_en <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_wram_addr <= 10'd0;
    else if(mac_cs == HEAD)
      mac_wram_addr <= {5'b0, mac_head_cnt};



  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_wram_dat <= 8'd0;
    else if(mac_cs == HEAD)
      begin
	case(mac_head_cnt)

	  5'd0, 5'd1, 5'd2, 5'd3, 5'd4, 5'd5, 5'd6:
	    mac_wram_dat <= 8'h55;
	  5'd7:
	    mac_wram_dat <= 8'hd5;

	  5'd8:
	    mac_wram_dat <= des_mac_addr[47:40];
	  5'd9:
	    mac_wram_dat <= des_mac_addr[39:32];
	  5'd10:
	    mac_wram_dat <= des_mac_addr[31:24];
	  5'd11:
	    mac_wram_dat <= des_mac_addr[23:16];
	  5'd12:
	    mac_wram_dat <= des_mac_addr[15:8];
	  5'd13:
	    mac_wram_dat <= des_mac_addr[7:0];

	  5'd14:
	    mac_wram_dat <= src_mac_addr[47:40];
	  5'd15:
	    mac_wram_dat <= src_mac_addr[39:32];
	  5'd16:
	    mac_wram_dat <= src_mac_addr[31:24];
	  5'd17:
	    mac_wram_dat <= src_mac_addr[23:16];
	  5'd18:
	    mac_wram_dat <= src_mac_addr[15:8];
	  5'd19:
	    mac_wram_dat <= src_mac_addr[7:0];

	  5'd20:
	    mac_wram_dat <= prot_type[15:8];
	  5'd21:
	    mac_wram_dat <= prot_type[7:0];
	endcase
      end









    else
      mac_wram_dat <= 8'd0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_head_end <= 1'b0;
    else if(mac_cs == HEAD && mac_head_cnt == 5'd21)
      mac_head_end <= 1'b1;
    else
      mac_head_end <= 1'b0;
  

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_rram_clk_en <= 1'b0;
    else if(mac_cs == SEND)
      mac_rram_clk_en <= 1'b1;
    else
      mac_rram_clk_en <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      mac_rram_addr <= 10'd0;
    else
      mac_rram_addr <= mac_send_cnt;


  reg st_send_dly;
  reg st_send_dly2;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      st_send_dly <= 1'b0;
    else if(mac_cs == FCS)
      st_send_dly <= 1'b1;
    else
      st_send_dly <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      st_send_dly2 <= 1'b0;
    else
      st_send_dly2 <= st_send_dly;
 

  wire [31:0] crc32;
  reg 	      crc32_start;
  reg [7:0]   mac_fcs_cnt_dly;
  reg [7:0]   mac_fcs_cnt_dly2;
  
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      crc32_start <= 1'b0;
    else if(mac_cs == FCS_START)
      crc32_start <= 1'b1;
    else
      crc32_start <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      begin
	mac_fcs_cnt_dly <= 8'b0;
	mac_fcs_cnt_dly2 <= 8'b0;
      end
    else
      begin
	mac_fcs_cnt_dly <= mac_fcs_cnt;
	mac_fcs_cnt_dly2 <= mac_fcs_cnt_dly;
      end
      










	  
  reg tx_en_tmp;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      begin
	tx_en_tmp <= 1'b0;
	tx_en <= 1'b0;
      end
    else
      begin
	tx_en_tmp <= mac_rram_clk_en;
	tx_en <= tx_en_tmp | st_send_dly2;
      end

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      txd <= 8'b0;
    else if(tx_en_tmp)
      txd <= mac_rram_dat;
    else if(st_send_dly2)
      begin
	case(mac_fcs_cnt_dly2)
	  2'b00: txd <= crc32[7:0];
	  2'b01: txd <= crc32[15:8];
	  2'b10: txd <= crc32[23:16];
	  2'b11: txd <= crc32[31:24];
	endcase
      end

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      tx_er <= 1'b0;

  reg tx_busy_dly1;
  reg tx_busy_dly2;
  reg tx_busy_dly3;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      tx_busy_dly1 <= 1'b0;
    else if(mac_cs == FCS_START || mac_cs == SEND || 
	    mac_cs == FCS)
      tx_busy_dly1 <= 1'b1;
    else
      tx_busy_dly1 <= 1'b0;

  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      begin
	tx_busy_dly2 <= 1'b0;
	tx_busy_dly3 <= 1'b0;
      end
    else
      begin
	tx_busy_dly2 <= tx_busy_dly1;
	tx_busy_dly3 <= tx_busy_dly2;
      end

  assign tx_busy = tx_busy_dly1 | tx_busy_dly2 | tx_busy_dly3;


  reg crc_dat_en;
  always@(posedge clk, negedge rst_n)
    if(!rst_n)
      crc_dat_en <= 1'b0;
    else if(mac_rram_clk_en && mac_rram_addr > 10'd7)
      crc_dat_en <= 1'b1;
    else
      crc_dat_en <= 1'b0;

  
  crc32 u_crc32
    (

     .crc32				(crc32[31:0]),

     .clk				(clk),
     .rst_n				(rst_n),
     .start				(crc32_start),
     .dat_en				(crc_dat_en),
     .dat				(mac_rram_dat[7:0])
     );
  

  
endmodule