data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sim_1/imports/new/test_bench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sim_1/imports/new/test_bench.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #5 reset <= \'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sim_1/imports/new/test_bench.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk <= ~clk;\n        ^\n%Error: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sim_1/imports/new/test_bench.v:36: Cannot find file containing module: \'CPU\'\n    CPU CPU1(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sim_1/imports/new,data/full_repos/permissive/191638444/CPU\n             data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sim_1/imports/new,data/full_repos/permissive/191638444/CPU.v\n             data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sim_1/imports/new,data/full_repos/permissive/191638444/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_bench();
    reg clk;
    reg reset;
    wire LEDcheck;

    CPU CPU1(
        .clk(clk), 
        .reset(reset), 
        .LEDcheck(LEDcheck)

    );
    
    initial
    begin
        clk <= 'b1;
        reset <= 'b0;   
        #5 reset <= 'b1;
    end
    
    always
    begin
        #10 clk <= ~clk;
    end
    

endmodule
module test_bench();

    reg clk;
    reg reset;
    wire LEDcheck;

    CPU CPU1(
        .clk(clk), 
        .reset(reset), 
        .LEDcheck(LEDcheck)

    );
    
    initial
    begin
        clk <= 'b1;
        reset <= 'b0;   
        #5 reset <= 'b1;
    end
    
    always
    begin
        #10 clk <= ~clk;
    end
    

endmodule