data/full_repos/permissive/193669196/memss/rtl/sram_wrap.v
 line:2: before: "NUM_64K_MEM"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/193669196/memss/rtl/sram_wrap.v:53: Signal definition not found, creating implicitly: \'valid_wr\'\n  assign valid_wr = hready & hsel &  hwrite & ~dec_err;\n         ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/193669196/memss/rtl/sram_wrap.v:54: Signal definition not found, creating implicitly: \'valid_rd\'\n                                                                                : ... Suggested alternative: \'valid_wr\'\n  assign valid_rd = hready & hsel & ~hwrite & ~dec_err;\n         ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/193669196/memss/rtl/sram_wrap.v:63: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                             : ... In instance sram_wrap\n      wbyte_en_lat <= 3\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/193669196/memss/rtl/sram_wrap.v:80: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'19\'h0\' generates 19 bits.\n                                                                             : ... In instance sram_wrap\n  sram_addr = 19\'b0;\n            ^\n%Error: data/full_repos/permissive/193669196/memss/rtl/sram_wrap.v:183: Cannot find file containing module: \'sram_sp_hde_64k\'\n      sram_sp_hde_64k u_sram_inst (\n      ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193669196/memss/rtl,data/full_repos/permissive/193669196/sram_sp_hde_64k\n             data/full_repos/permissive/193669196/memss/rtl,data/full_repos/permissive/193669196/sram_sp_hde_64k.v\n             data/full_repos/permissive/193669196/memss/rtl,data/full_repos/permissive/193669196/sram_sp_hde_64k.sv\n             sram_sp_hde_64k\n             sram_sp_hde_64k.v\n             sram_sp_hde_64k.sv\n             obj_dir/sram_sp_hde_64k\n             obj_dir/sram_sp_hde_64k.v\n             obj_dir/sram_sp_hde_64k.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module sram_wrap #(
  NUM_64K_MEM = 1)
  (  

  input  wire         hclk,
  input  wire         hresetn,

  input   wire        hsel,
  input   wire [31:0] haddr,
  input   wire [ 2:0] hsize,
  input   wire [31:0] hwdata,
  input   wire        hwrite,
  output  reg  [31:0] hrdata,
  output  reg         hready,
  output  reg         hresp
);




  localparam IDLE         = 0;
  localparam READ         = 1;
  localparam WRITE        = 2;
  localparam WAIT         = 3;
  localparam ERROR        = 4;

  localparam NUM_MEM      = NUM_64K_MEM;

  reg [4:0]  ahb_ps;
  reg [4:0]  ahb_ns;

  reg [13:0] sram_addr;
  reg [31:0] sram_rdata[NUM_MEM-1 :0];
  reg        sram_sel;
  reg        sram_we_n;

  reg [NUM_MEM-1 :0] sram_cs_n;
  reg [NUM_MEM-1 :0] sram_cs_n_lat;

  reg [31:0] haddr_lat;
  wire       dec_err;

  reg [3:0]  wbyte_en;
  reg [3:0]  wbyte_en_lat;

  genvar  i;
  integer j;




  assign dec_err  = hready & hsel & (haddr[31:17] != 15'h1000);
  assign valid_wr = hready & hsel &  hwrite & ~dec_err;
  assign valid_rd = hready & hsel & ~hwrite & ~dec_err;





  always @(posedge hclk or negedge hresetn) begin 
    if (hresetn == 1'b0) begin
      haddr_lat    <= 32'b0;
      wbyte_en_lat <= 3'b0;
    end
    else if (ahb_ns[WRITE] | ahb_ns[WAIT]) begin
      haddr_lat    <= haddr;
      wbyte_en_lat <= wbyte_en;
    end
  end






always@*  begin
  ahb_ns    = 5'b0_0000;
  sram_sel  = 1'b0;
  sram_we_n = 1'b1;
  sram_addr = 19'b0;
  case (1'b1)
    ahb_ps[IDLE] : begin
      if (hsel == 1'b1) begin
        if (dec_err == 1'b1) begin
          ahb_ns[ERROR] = 1'b1;
        end
        else if (hwrite == 1'b0) begin
          ahb_ns[READ] = 1'b1;
          sram_sel     = 1'b1;
          sram_addr    = haddr[15:2];
        end
        else begin
          ahb_ns[WRITE] = 1'b1;
        end
      end
      else begin
        ahb_ns[IDLE] = 1'b1;
      end
    end
    ahb_ps[READ] : begin
      if (hsel == 1'b1) begin
        if (dec_err == 1'b1) begin
          ahb_ns[ERROR] = 1'b1;
        end
        else if (hwrite == 1'b0) begin
          ahb_ns[READ] = 1'b1;
          sram_sel     = 1'b1;
          sram_addr    = haddr[15:2];
        end
        else begin
          ahb_ns[WRITE] = 1'b1;
        end
      end
      else begin
        ahb_ns[IDLE] = 1'b1;
      end
    end
    ahb_ps[WRITE] : begin
      sram_sel  = 1'b1;
      sram_we_n = 1'b0;
      sram_addr = haddr_lat[15:2];
      if (hsel == 1'b1) begin
        if (dec_err == 1'b1) begin
          ahb_ns[ERROR] = 1'b1;
        end
        else if (hwrite == 1'b0) begin
          ahb_ns[WAIT] = 1'b1;
        end
        else begin
          ahb_ns[WRITE] = 1'b1;
        end
      end
      else begin
        ahb_ns[IDLE] = 1'b1;
      end
    end
    ahb_ps[WAIT] : begin
      sram_sel  = 1'b1;
      sram_addr = haddr_lat[15:2];
      ahb_ns[IDLE] = 1'b1;
    end
    ahb_ps[ERROR] : begin
      ahb_ns[IDLE] = 1'b1;
    end
    default  : begin
      sram_sel     = 1'b0;
      sram_we_n    = 1'b1;
      sram_addr    = 14'b0;
      ahb_ns[IDLE] = 1'b1;
    end
  endcase
end

 
  always @ (posedge hclk or negedge hresetn) begin
    if (hresetn == 1'b0) begin
      ahb_ps <= 5'b0_0001;
    end
    else begin
      ahb_ps  <= ahb_ns;
    end
  end





generate
  for (i=0; i<NUM_MEM; i=i+1) begin

     assign sram_cs_n[i] = sram_sel ? 1'b0 : 1'b1;

    `ifdef FPGA_SYNTH
      sram_sp_hsd \genblk1[0].u_sram_inst  (
        .douta(sram_rdata[i]),
        .addra(sram_addr),
        .dina(hwdata),
        .clka(hclk), 
        .ena(~sram_cs_n[i]),
        .wea(~sram_we_n)
      );
    `else
      sram_sp_hde_64k u_sram_inst (
       .CLK  (hclk),
       .CEN  (sram_cs_n[i]),

       .WEN  (sram_we_n),
       .A    (sram_addr[13:0]),
       .D    (hwdata),
       .EMA  (3'b0),
       .RETN (1'b1),
       .Q    (sram_rdata[i])
      );
    `endif
  end


endgenerate




   
  always @ (posedge hclk or negedge hresetn) begin
    if (hresetn == 1'b0) begin
      sram_cs_n_lat <= {NUM_MEM{1'b1}};
    end
    else begin
      sram_cs_n_lat <= sram_cs_n | ~sram_we_n;
    end
  end

  always@* begin
      hrdata = 32'b0;
    for (j=0; j< NUM_MEM; j=j+1) begin
      hrdata = hrdata | ({32{~sram_cs_n_lat[j]}} & sram_rdata[j]);
    end
  end










   always @* begin
     if (valid_wr == 1'b1) begin
       if (haddr[1:0] == 2'b00) begin
         case (hsize)
           3'b000 : wbyte_en = 4'b0001;
           3'b001 : wbyte_en = 4'b0011;
           3'b010 : wbyte_en = 4'b1111;
           default: wbyte_en = 4'b0000;
         endcase
       end
       if((haddr[1:0] == 2'b01)) begin
         case (hsize)
           3'b000 : wbyte_en = 4'b0010;
           default: wbyte_en = 4'b0000;
         endcase
       end
       if((haddr[1:0] == 2'b10)) begin
         case (hsize)
           3'b000 : wbyte_en = 4'b0100;
           3'b001 : wbyte_en = 4'b1100;
           default: wbyte_en = 4'b0000;
         endcase
       end
       if((haddr[1:0] == 2'b11)) begin
         case (hsize)
           3'b000 : wbyte_en = 4'b1000;
           default: wbyte_en = 4'b0000;
         endcase
       end
     end
     else begin
       wbyte_en = 4'b0000;
     end
   end





   
  always @ (posedge hclk or negedge hresetn) begin
    if (hresetn == 1'b0) begin
      hready <= 1'b1;
    end
    else if (ahb_ns[ERROR] | ahb_ns[WAIT]) begin
      hready <= 1'b0;
    end
    else begin
      hready <= 1'b1;
    end
  end
  
  always @ (posedge hclk or negedge hresetn) begin
    if (hresetn == 1'b0) begin
      hresp  <= 1'b0;
    end
    else if (ahb_ns[ERROR] | ahb_ps[ERROR]) begin
      hresp  <= 1'b1;
    end
    else begin
      hresp  <= 1'b0;
    end
  end


endmodule
module sram_wrap #(
  NUM_64K_MEM = 1)
  (  

  input  wire         hclk,
  input  wire         hresetn,

  input   wire        hsel,
  input   wire [31:0] haddr,
  input   wire [ 2:0] hsize,
  input   wire [31:0] hwdata,
  input   wire        hwrite,
  output  reg  [31:0] hrdata,
  output  reg         hready,
  output  reg         hresp
);





  localparam IDLE         = 0;
  localparam READ         = 1;
  localparam WRITE        = 2;
  localparam WAIT         = 3;
  localparam ERROR        = 4;

  localparam NUM_MEM      = NUM_64K_MEM;

  reg [4:0]  ahb_ps;
  reg [4:0]  ahb_ns;

  reg [13:0] sram_addr;
  reg [31:0] sram_rdata[NUM_MEM-1 :0];
  reg        sram_sel;
  reg        sram_we_n;

  reg [NUM_MEM-1 :0] sram_cs_n;
  reg [NUM_MEM-1 :0] sram_cs_n_lat;

  reg [31:0] haddr_lat;
  wire       dec_err;

  reg [3:0]  wbyte_en;
  reg [3:0]  wbyte_en_lat;

  genvar  i;
  integer j;




  assign dec_err  = hready & hsel & (haddr[31:17] != 15'h1000);
  assign valid_wr = hready & hsel &  hwrite & ~dec_err;
  assign valid_rd = hready & hsel & ~hwrite & ~dec_err;





  always @(posedge hclk or negedge hresetn) begin 
    if (hresetn == 1'b0) begin
      haddr_lat    <= 32'b0;
      wbyte_en_lat <= 3'b0;
    end
    else if (ahb_ns[WRITE] | ahb_ns[WAIT]) begin
      haddr_lat    <= haddr;
      wbyte_en_lat <= wbyte_en;
    end
  end






always@*  begin
  ahb_ns    = 5'b0_0000;
  sram_sel  = 1'b0;
  sram_we_n = 1'b1;
  sram_addr = 19'b0;
  case (1'b1)
    ahb_ps[IDLE] : begin
      if (hsel == 1'b1) begin
        if (dec_err == 1'b1) begin
          ahb_ns[ERROR] = 1'b1;
        end
        else if (hwrite == 1'b0) begin
          ahb_ns[READ] = 1'b1;
          sram_sel     = 1'b1;
          sram_addr    = haddr[15:2];
        end
        else begin
          ahb_ns[WRITE] = 1'b1;
        end
      end
      else begin
        ahb_ns[IDLE] = 1'b1;
      end
    end
    ahb_ps[READ] : begin
      if (hsel == 1'b1) begin
        if (dec_err == 1'b1) begin
          ahb_ns[ERROR] = 1'b1;
        end
        else if (hwrite == 1'b0) begin
          ahb_ns[READ] = 1'b1;
          sram_sel     = 1'b1;
          sram_addr    = haddr[15:2];
        end
        else begin
          ahb_ns[WRITE] = 1'b1;
        end
      end
      else begin
        ahb_ns[IDLE] = 1'b1;
      end
    end
    ahb_ps[WRITE] : begin
      sram_sel  = 1'b1;
      sram_we_n = 1'b0;
      sram_addr = haddr_lat[15:2];
      if (hsel == 1'b1) begin
        if (dec_err == 1'b1) begin
          ahb_ns[ERROR] = 1'b1;
        end
        else if (hwrite == 1'b0) begin
          ahb_ns[WAIT] = 1'b1;
        end
        else begin
          ahb_ns[WRITE] = 1'b1;
        end
      end
      else begin
        ahb_ns[IDLE] = 1'b1;
      end
    end
    ahb_ps[WAIT] : begin
      sram_sel  = 1'b1;
      sram_addr = haddr_lat[15:2];
      ahb_ns[IDLE] = 1'b1;
    end
    ahb_ps[ERROR] : begin
      ahb_ns[IDLE] = 1'b1;
    end
    default  : begin
      sram_sel     = 1'b0;
      sram_we_n    = 1'b1;
      sram_addr    = 14'b0;
      ahb_ns[IDLE] = 1'b1;
    end
  endcase
end

 
  always @ (posedge hclk or negedge hresetn) begin
    if (hresetn == 1'b0) begin
      ahb_ps <= 5'b0_0001;
    end
    else begin
      ahb_ps  <= ahb_ns;
    end
  end





generate
  for (i=0; i<NUM_MEM; i=i+1) begin

     assign sram_cs_n[i] = sram_sel ? 1'b0 : 1'b1;

    `ifdef FPGA_SYNTH
      sram_sp_hsd \genblk1[0].u_sram_inst  (
        .douta(sram_rdata[i]),
        .addra(sram_addr),
        .dina(hwdata),
        .clka(hclk), 
        .ena(~sram_cs_n[i]),
        .wea(~sram_we_n)
      );
    `else
      sram_sp_hde_64k u_sram_inst (
       .CLK  (hclk),
       .CEN  (sram_cs_n[i]),

       .WEN  (sram_we_n),
       .A    (sram_addr[13:0]),
       .D    (hwdata),
       .EMA  (3'b0),
       .RETN (1'b1),
       .Q    (sram_rdata[i])
      );
    `endif
  end


endgenerate




   
  always @ (posedge hclk or negedge hresetn) begin
    if (hresetn == 1'b0) begin
      sram_cs_n_lat <= {NUM_MEM{1'b1}};
    end
    else begin
      sram_cs_n_lat <= sram_cs_n | ~sram_we_n;
    end
  end

  always@* begin
      hrdata = 32'b0;
    for (j=0; j< NUM_MEM; j=j+1) begin
      hrdata = hrdata | ({32{~sram_cs_n_lat[j]}} & sram_rdata[j]);
    end
  end










   always @* begin
     if (valid_wr == 1'b1) begin
       if (haddr[1:0] == 2'b00) begin
         case (hsize)
           3'b000 : wbyte_en = 4'b0001;
           3'b001 : wbyte_en = 4'b0011;
           3'b010 : wbyte_en = 4'b1111;
           default: wbyte_en = 4'b0000;
         endcase
       end
       if((haddr[1:0] == 2'b01)) begin
         case (hsize)
           3'b000 : wbyte_en = 4'b0010;
           default: wbyte_en = 4'b0000;
         endcase
       end
       if((haddr[1:0] == 2'b10)) begin
         case (hsize)
           3'b000 : wbyte_en = 4'b0100;
           3'b001 : wbyte_en = 4'b1100;
           default: wbyte_en = 4'b0000;
         endcase
       end
       if((haddr[1:0] == 2'b11)) begin
         case (hsize)
           3'b000 : wbyte_en = 4'b1000;
           default: wbyte_en = 4'b0000;
         endcase
       end
     end
     else begin
       wbyte_en = 4'b0000;
     end
   end





   
  always @ (posedge hclk or negedge hresetn) begin
    if (hresetn == 1'b0) begin
      hready <= 1'b1;
    end
    else if (ahb_ns[ERROR] | ahb_ns[WAIT]) begin
      hready <= 1'b0;
    end
    else begin
      hready <= 1'b1;
    end
  end
  
  always @ (posedge hclk or negedge hresetn) begin
    if (hresetn == 1'b0) begin
      hresp  <= 1'b0;
    end
    else if (ahb_ns[ERROR] | ahb_ps[ERROR]) begin
      hresp  <= 1'b1;
    end
    else begin
      hresp  <= 1'b0;
    end
  end


endmodule