data/full_repos/permissive/139831595/hw/source/decompressor_wrapper.v
1: b"%Error: data/full_repos/permissive/139831595/hw/source/decompressor_wrapper.v:79: Cannot find file containing module: 'decompressor'\ndecompressor dec0(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139831595/hw/source,data/full_repos/permissive/139831595/decompressor\n             data/full_repos/permissive/139831595/hw/source,data/full_repos/permissive/139831595/decompressor.v\n             data/full_repos/permissive/139831595/hw/source,data/full_repos/permissive/139831595/decompressor.sv\n             decompressor\n             decompressor.v\n             decompressor.sv\n             obj_dir/decompressor\n             obj_dir/decompressor.v\n             obj_dir/decompressor.sv\n%Error: Exiting due to 1 error(s)\n"
module decompressor_wrapper(
		input clk,
		input rst_n,

    output last,
    output done,
    input  start,



	
		input[511:0] in_data,
		input in_data_valid,
		output in_data_ready,
	
		input[34:0] compression_length,
		input[31:0] decompression_length,
		input in_metadata_valid,
		output in_metadata_ready,
	
		output[511:0] out_data,
		output out_data_valid,
    output[63:0] out_data_byte_valid,
		input out_data_ready
	);

wire dec_done;
wire almost_full;

reg start_reg;
always@(posedge clk)begin
	if(~rst_n)begin
		start_reg	<= 1'b0;
	end else begin
		start_reg	<= start;
	end
end

reg [34:0]com_len_reg;
reg [31:0]dec_len_reg;
reg in_metadata_ready_reg;
always@(posedge clk)begin
	if(~rst_n)begin
    com_len_reg <= 35'b0;
    dec_len_reg <= 32'b0;
	end else begin
		if(in_metadata_valid && in_metadata_ready_reg) begin
      com_len_reg <= compression_length;
      dec_len_reg <= decompression_length;
    end
	end
end

always@(posedge clk)begin
	if(~rst_n)begin
    in_metadata_ready_reg <= 1'b1;
	end else begin
		if(in_metadata_ready_reg) begin
      if(in_metadata_valid) begin
        in_metadata_ready_reg <= 1'b0;
      end
    end
    else begin
      if(dec_done)
        in_metadata_ready_reg <= 1'b1;
    end
	end
end


decompressor dec0(
  .clk(clk),
	.rst_n(rst_n),
	.data(in_data),
	.valid_in(in_data_valid),
	.start(start_reg),
	.compression_length(com_len_reg),
	.decompression_length(dec_len_reg),
	.wr_ready(out_data_ready),

	.data_fifo_almostfull(almost_full),
	
	.done(dec_done),
	.last(last),
	.data_out(out_data),
	.byte_valid_out(out_data_byte_valid),
	.valid_out(out_data_valid)
);

assign in_metadata_ready = in_metadata_ready_reg;
assign done = dec_done;
assign in_data_ready = ~almost_full;

endmodule
module decompressor_wrapper(
		input clk,
		input rst_n,

    output last,
    output done,
    input  start,



	
		input[511:0] in_data,
		input in_data_valid,
		output in_data_ready,
	
		input[34:0] compression_length,
		input[31:0] decompression_length,
		input in_metadata_valid,
		output in_metadata_ready,
	
		output[511:0] out_data,
		output out_data_valid,
    output[63:0] out_data_byte_valid,
		input out_data_ready
	);


wire dec_done;
wire almost_full;

reg start_reg;
always@(posedge clk)begin
	if(~rst_n)begin
		start_reg	<= 1'b0;
	end else begin
		start_reg	<= start;
	end
end

reg [34:0]com_len_reg;
reg [31:0]dec_len_reg;
reg in_metadata_ready_reg;
always@(posedge clk)begin
	if(~rst_n)begin
    com_len_reg <= 35'b0;
    dec_len_reg <= 32'b0;
	end else begin
		if(in_metadata_valid && in_metadata_ready_reg) begin
      com_len_reg <= compression_length;
      dec_len_reg <= decompression_length;
    end
	end
end

always@(posedge clk)begin
	if(~rst_n)begin
    in_metadata_ready_reg <= 1'b1;
	end else begin
		if(in_metadata_ready_reg) begin
      if(in_metadata_valid) begin
        in_metadata_ready_reg <= 1'b0;
      end
    end
    else begin
      if(dec_done)
        in_metadata_ready_reg <= 1'b1;
    end
	end
end


decompressor dec0(
  .clk(clk),
	.rst_n(rst_n),
	.data(in_data),
	.valid_in(in_data_valid),
	.start(start_reg),
	.compression_length(com_len_reg),
	.decompression_length(dec_len_reg),
	.wr_ready(out_data_ready),

	.data_fifo_almostfull(almost_full),
	
	.done(dec_done),
	.last(last),
	.data_out(out_data),
	.byte_valid_out(out_data_byte_valid),
	.valid_out(out_data_valid)
);

assign in_metadata_ready = in_metadata_ready_reg;
assign done = dec_done;
assign in_data_ready = ~almost_full;

endmodule