data/full_repos/permissive/198139336/2019_DD_LAB10/BOOTH/BOOTH_me/Booth/Booth.srcs/sources_1/imports/vivado_demo/code/32mpy_booth.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/198139336/2019_DD_LAB10/BOOTH/BOOTH_me/Booth/Booth.srcs/sources_1/imports/vivado_demo/code/32mpy_booth.v:23: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                                                                                                      : ... In instance lab\n  Counter <=6\'b0;\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/198139336/2019_DD_LAB10/BOOTH/BOOTH_me/Booth/Booth.srcs/sources_1/imports/vivado_demo/code/32mpy_booth.v:25: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                                                                                                      : ... In instance lab\n  Counter <=6\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/198139336/2019_DD_LAB10/BOOTH/BOOTH_me/Booth/Booth.srcs/sources_1/imports/vivado_demo/code/32mpy_booth.v:26: Operator LTE expects 7 bits on the RHS, but RHS\'s CONST \'6\'h11\' generates 6 bits.\n                                                                                                                                                      : ... In instance lab\n else if(Counter<=6\'d17)\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/198139336/2019_DD_LAB10/BOOTH/BOOTH_me/Booth/Booth.srcs/sources_1/imports/vivado_demo/code/32mpy_booth.v:68: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'in_a\' generates 32 bits.\n                                                                                                                                                      : ... In instance lab\n  Mplicand <= in_a;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/198139336/2019_DD_LAB10/BOOTH/BOOTH_me/Booth/Booth.srcs/sources_1/imports/vivado_demo/code/32mpy_booth.v:76: Operator LTE expects 7 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n                                                                                                                                                      : ... In instance lab\n else if(Counter <=6\'d16)\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/198139336/2019_DD_LAB10/BOOTH/BOOTH_me/Booth/Booth.srcs/sources_1/imports/vivado_demo/code/32mpy_booth.v:67: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                                                                                                      : ... In instance lab\n else if(Counter == 6\'d0) begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/198139336/2019_DD_LAB10/BOOTH/BOOTH_me/Booth/Booth.srcs/sources_1/imports/vivado_demo/code/32mpy_booth.v:97: Operator GTE expects 7 bits on the RHS, but RHS\'s CONST \'6\'h10\' generates 6 bits.\n                                                                                                                                                      : ... In instance lab\n else if(Counter>=6\'d16)\n                ^~\n%Error: Exiting due to 7 warning(s)\n'
module lab(CLK, RST, din,addr, ctrl,Partial_Product, Product_Valid);
input CLK, RST;
input [2:0]ctrl;
input [15:0]addr;
input signed [31:0] din;
output reg [31:0] Partial_Product;
output reg Product_Valid;

reg signed[31:0]	in_a;
reg signed[31:0]	in_b;

reg [63:0] Mplicand;
reg signed [63:0] Product;
reg [32:0] Mplier;
reg [6:0]	Counter ;
reg	sign;



always@(posedge CLK or negedge RST)
begin
	if(!RST)
		Counter <=6'b0;
	else if(ctrl[0])
		Counter <=6'b0;
	else if(Counter<=6'd17)
		Counter <= Counter +6'b1;
end

always@(posedge CLK or negedge RST)
begin
	if(!RST) begin
		in_a <=32'd0;
		in_b <=32'd0;
	end
	else if(addr[15:8]==8'h00)begin
		in_a <=din;
		in_b <=din;
	end
end

always@(posedge CLK or negedge RST)
begin
	if(!RST)begin
		Partial_Product<=32'd0;
	end
	else if(ctrl[2])begin
		Partial_Product<=Product[31:0];
	end
	else if(ctrl[1])begin
		Partial_Product<=Product[63:32];
	end
end


always @(posedge CLK or negedge RST)
begin

	if(!RST) begin
		Product  <= 64'b0;
		Mplicand <= 64'b0;

		Mplier   <= 33'b0;	
	end 
	

	else if(Counter == 6'd0) begin
		Mplicand <= in_a;
		Mplier <= {in_b,1'b0};


	end 
	


	else if(Counter <=6'd16)
	begin
		if(Mplier[2:0] == 3'b001||Mplier[2:0] == 3'b010)
		Product <= Mplicand + Product;
		else if(Mplier[2:0] == 3'b011)
		Product <= 2 * Mplicand + Product;
		else if(Mplier[2:0] == 3'b100)
		Product <= Product - 2 * Mplicand;
		else if(Mplier[2:0] == 3'b101||Mplier[2:0] == 3'b110)
		Product <= Product - Mplicand;
		Mplicand <= Mplicand << 2'b10;
		Mplier <= Mplier >> 2'b10;
	end

end


always @(posedge CLK or negedge RST)
begin
	if(!RST)
		Product_Valid <=1'b0;
	else if(Counter>=6'd16)
		Product_Valid <=1'b1;
	else
		Product_Valid <=1'b0;
end

endmodule
module lab(CLK, RST, din,addr, ctrl,Partial_Product, Product_Valid);

input CLK, RST;
input [2:0]ctrl;
input [15:0]addr;
input signed [31:0] din;
output reg [31:0] Partial_Product;
output reg Product_Valid;

reg signed[31:0]	in_a;
reg signed[31:0]	in_b;

reg [63:0] Mplicand;
reg signed [63:0] Product;
reg [32:0] Mplier;
reg [6:0]	Counter ;
reg	sign;



always@(posedge CLK or negedge RST)
begin
	if(!RST)
		Counter <=6'b0;
	else if(ctrl[0])
		Counter <=6'b0;
	else if(Counter<=6'd17)
		Counter <= Counter +6'b1;
end

always@(posedge CLK or negedge RST)
begin
	if(!RST) begin
		in_a <=32'd0;
		in_b <=32'd0;
	end
	else if(addr[15:8]==8'h00)begin
		in_a <=din;
		in_b <=din;
	end
end

always@(posedge CLK or negedge RST)
begin
	if(!RST)begin
		Partial_Product<=32'd0;
	end
	else if(ctrl[2])begin
		Partial_Product<=Product[31:0];
	end
	else if(ctrl[1])begin
		Partial_Product<=Product[63:32];
	end
end


always @(posedge CLK or negedge RST)
begin

	if(!RST) begin
		Product  <= 64'b0;
		Mplicand <= 64'b0;

		Mplier   <= 33'b0;	
	end 
	

	else if(Counter == 6'd0) begin
		Mplicand <= in_a;
		Mplier <= {in_b,1'b0};


	end 
	


	else if(Counter <=6'd16)
	begin
		if(Mplier[2:0] == 3'b001||Mplier[2:0] == 3'b010)
		Product <= Mplicand + Product;
		else if(Mplier[2:0] == 3'b011)
		Product <= 2 * Mplicand + Product;
		else if(Mplier[2:0] == 3'b100)
		Product <= Product - 2 * Mplicand;
		else if(Mplier[2:0] == 3'b101||Mplier[2:0] == 3'b110)
		Product <= Product - Mplicand;
		Mplicand <= Mplicand << 2'b10;
		Mplier <= Mplier >> 2'b10;
	end

end


always @(posedge CLK or negedge RST)
begin
	if(!RST)
		Product_Valid <=1'b0;
	else if(Counter>=6'd16)
		Product_Valid <=1'b1;
	else
		Product_Valid <=1'b0;
end

endmodule