data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v
None: at end of input
1: b'%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:25: Cannot find include file: kplic_defines.vh\n`include "kplic_defines.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159016511/src/rtl/kplic,data/full_repos/permissive/159016511/kplic_defines.vh\n             data/full_repos/permissive/159016511/src/rtl/kplic,data/full_repos/permissive/159016511/kplic_defines.vh.v\n             data/full_repos/permissive/159016511/src/rtl/kplic,data/full_repos/permissive/159016511/kplic_defines.vh.sv\n             kplic_defines.vh\n             kplic_defines.vh.v\n             kplic_defines.vh.sv\n             obj_dir/kplic_defines.vh\n             obj_dir/kplic_defines.vh.v\n             obj_dir/kplic_defines.vh.sv\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:35: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\ninput wire [`KPLIC_DATA_WIDTH - 1 : 0] write_data,   \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:36: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput wire [`KPLIC_DATA_WIDTH - 1 : 0] read_data,   \n             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:39: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput reg [`KPLIC_DATA_WIDTH - 1 : 0] int_type,   \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:40: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput reg [`KPLIC_DATA_WIDTH - 1 : 0] int_enable,   \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:41: Define or directive not defined: \'`INT_NUM\'\noutput reg [`INT_NUM - 1  : 0] int_completion,    \n            ^~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:44: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\ninput wire [`KPLIC_DATA_WIDTH - 1 : 0] int_pending_status,  \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:45: Define or directive not defined: \'`INT_WIDTH\'\ninput wire [`INT_WIDTH - 1 : 0] mppi,    \n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:46: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput reg [`KPLIC_DATA_WIDTH - 1 : 0] target_priority,   \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:47: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group0,  \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:48: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group1,  \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:49: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group2,  \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:50: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group3,  \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:51: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group4,  \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:52: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group5,  \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:53: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group6,  \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:54: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\noutput reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group7,  \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:77: Define or directive not defined: \'`KPLIC_INT_TYPE_OFFSET\'\nassign int_type_sel = (addr == `KPLIC_INT_TYPE_OFFSET);\n                               ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_type_sel = (addr == `KPLIC_INT_TYPE_OFFSET);\n                                                     ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:78: Define or directive not defined: \'`KPLIC_INT_ENABLE_OFFSET\'\nassign int_enable_sel = (addr == `KPLIC_INT_ENABLE_OFFSET);\n                                 ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:78: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_enable_sel = (addr == `KPLIC_INT_ENABLE_OFFSET);\n                                                         ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:79: Define or directive not defined: \'`KPLIC_INT_PENDING_STATUS_OFFSET\'\nassign int_pending_status_sel = (addr == `KPLIC_INT_PENDING_STATUS_OFFSET);\n                                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:79: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_pending_status_sel = (addr == `KPLIC_INT_PENDING_STATUS_OFFSET);\n                                                                         ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:80: Define or directive not defined: \'`KPLIC_TARGET_PRIORITY_OFFSET\'\nassign target_priority_sel = (addr == `KPLIC_TARGET_PRIORITY_OFFSET);\n                                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:80: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign target_priority_sel = (addr == `KPLIC_TARGET_PRIORITY_OFFSET);\n                                                                   ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:81: Define or directive not defined: \'`KPLIC_INT_COMPLETION_OFFSET\'\nassign int_completion_sel =(addr == `KPLIC_INT_COMPLETION_OFFSET); \n                                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:81: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_completion_sel =(addr == `KPLIC_INT_COMPLETION_OFFSET); \n                                                                ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:82: Define or directive not defined: \'`KPLIC_MPPI_OFFSET\'\nassign mppi_sel = (addr == `KPLIC_MPPI_OFFSET);\n                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:82: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign mppi_sel = (addr == `KPLIC_MPPI_OFFSET);\n                                             ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:83: Define or directive not defined: \'`KPLIC_INT_PRIORITY_GROUP0_OFFSET\'\nassign int_priority_group0_sel = (addr == `KPLIC_INT_PRIORITY_GROUP0_OFFSET);\n                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:83: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_priority_group0_sel = (addr == `KPLIC_INT_PRIORITY_GROUP0_OFFSET);\n                                                                           ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:84: Define or directive not defined: \'`KPLIC_INT_PRIORITY_GROUP1_OFFSET\'\nassign int_priority_group1_sel = (addr == `KPLIC_INT_PRIORITY_GROUP1_OFFSET);\n                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_priority_group1_sel = (addr == `KPLIC_INT_PRIORITY_GROUP1_OFFSET);\n                                                                           ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:85: Define or directive not defined: \'`KPLIC_INT_PRIORITY_GROUP2_OFFSET\'\nassign int_priority_group2_sel = (addr == `KPLIC_INT_PRIORITY_GROUP2_OFFSET);\n                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:85: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_priority_group2_sel = (addr == `KPLIC_INT_PRIORITY_GROUP2_OFFSET);\n                                                                           ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:86: Define or directive not defined: \'`KPLIC_INT_PRIORITY_GROUP3_OFFSET\'\nassign int_priority_group3_sel = (addr == `KPLIC_INT_PRIORITY_GROUP3_OFFSET);\n                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:86: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_priority_group3_sel = (addr == `KPLIC_INT_PRIORITY_GROUP3_OFFSET);\n                                                                           ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:87: Define or directive not defined: \'`KPLIC_INT_PRIORITY_GROUP4_OFFSET\'\nassign int_priority_group4_sel = (addr == `KPLIC_INT_PRIORITY_GROUP4_OFFSET);\n                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:87: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_priority_group4_sel = (addr == `KPLIC_INT_PRIORITY_GROUP4_OFFSET);\n                                                                           ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:88: Define or directive not defined: \'`KPLIC_INT_PRIORITY_GROUP5_OFFSET\'\nassign int_priority_group5_sel = (addr == `KPLIC_INT_PRIORITY_GROUP5_OFFSET);\n                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:88: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_priority_group5_sel = (addr == `KPLIC_INT_PRIORITY_GROUP5_OFFSET);\n                                                                           ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:89: Define or directive not defined: \'`KPLIC_INT_PRIORITY_GROUP6_OFFSET\'\nassign int_priority_group6_sel = (addr == `KPLIC_INT_PRIORITY_GROUP6_OFFSET);\n                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:89: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_priority_group6_sel = (addr == `KPLIC_INT_PRIORITY_GROUP6_OFFSET);\n                                                                           ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:90: Define or directive not defined: \'`KPLIC_INT_PRIORITY_GROUP7_OFFSET\'\nassign int_priority_group7_sel = (addr == `KPLIC_INT_PRIORITY_GROUP7_OFFSET);\n                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:90: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign int_priority_group7_sel = (addr == `KPLIC_INT_PRIORITY_GROUP7_OFFSET);\n                                                                           ^\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:105: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\n  int_type <= {`KPLIC_DATA_WIDTH{1\'b0}};\n               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:119: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\nwire [`KPLIC_DATA_WIDTH - 1 : 0] int_type_read_data;\n      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:120: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\nassign int_type_read_data = int_type_sel ? int_type : {`KPLIC_DATA_WIDTH{1\'b0}};\n                                                       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:127: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\n  int_enable <= {`KPLIC_DATA_WIDTH{1\'b1}};\n                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/kplic/kplic_regs.v:141: Define or directive not defined: \'`KPLIC_DATA_WIDTH\'\nwire [`KPLIC_DATA_WIDTH - 1 : 0] int_enable_read_data;\n      ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module kplic_regs (

input wire kplic_clk,
input wire kplic_rstn,


input wire valid_reg_access,
input wire [11:0] addr,
input wire rd_wr,
input wire [`KPLIC_DATA_WIDTH - 1 : 0] write_data,
output wire [`KPLIC_DATA_WIDTH - 1 : 0] read_data,


output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_type,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_enable,
output reg [`INT_NUM - 1  : 0] int_completion,


input wire [`KPLIC_DATA_WIDTH - 1 : 0] int_pending_status,
input wire [`INT_WIDTH - 1 : 0] mppi,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] target_priority,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group0,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group1,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group2,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group3,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group4,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group5,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group6,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group7,
output wire int_claim
);





wire int_type_sel;
wire int_enable_sel;
wire int_pending_status_sel;
wire target_priority_sel;
wire int_completion_sel;
wire mppi_sel;
wire int_priority_group0_sel;
wire int_priority_group1_sel;
wire int_priority_group2_sel;
wire int_priority_group3_sel;
wire int_priority_group4_sel;
wire int_priority_group5_sel;
wire int_priority_group6_sel;
wire int_priority_group7_sel;

assign int_type_sel = (addr == `KPLIC_INT_TYPE_OFFSET);
assign int_enable_sel = (addr == `KPLIC_INT_ENABLE_OFFSET);
assign int_pending_status_sel = (addr == `KPLIC_INT_PENDING_STATUS_OFFSET);
assign target_priority_sel = (addr == `KPLIC_TARGET_PRIORITY_OFFSET);
assign int_completion_sel =(addr == `KPLIC_INT_COMPLETION_OFFSET); 
assign mppi_sel = (addr == `KPLIC_MPPI_OFFSET);
assign int_priority_group0_sel = (addr == `KPLIC_INT_PRIORITY_GROUP0_OFFSET);
assign int_priority_group1_sel = (addr == `KPLIC_INT_PRIORITY_GROUP1_OFFSET);
assign int_priority_group2_sel = (addr == `KPLIC_INT_PRIORITY_GROUP2_OFFSET);
assign int_priority_group3_sel = (addr == `KPLIC_INT_PRIORITY_GROUP3_OFFSET);
assign int_priority_group4_sel = (addr == `KPLIC_INT_PRIORITY_GROUP4_OFFSET);
assign int_priority_group5_sel = (addr == `KPLIC_INT_PRIORITY_GROUP5_OFFSET);
assign int_priority_group6_sel = (addr == `KPLIC_INT_PRIORITY_GROUP6_OFFSET);
assign int_priority_group7_sel = (addr == `KPLIC_INT_PRIORITY_GROUP7_OFFSET);




wire valid_reg_read;
wire valid_reg_write;
assign valid_reg_read = valid_reg_access & !rd_wr;
assign valid_reg_write = valid_reg_access & rd_wr;


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_type <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_type_sel && valid_reg_write)
		begin
			int_type <= write_data;
		end
		else
		begin
			int_type <= int_type;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_type_read_data;
assign int_type_read_data = int_type_sel ? int_type : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_enable <= {`KPLIC_DATA_WIDTH{1'b1}};
	end
	else
	begin
		if (int_enable_sel && valid_reg_write)
		begin
			int_enable <= write_data;
		end
		else
		begin
			int_enable <= int_enable;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_enable_read_data;
assign int_enable_read_data = int_enable_sel ? int_enable : {`KPLIC_DATA_WIDTH{1'b0}};



wire [`KPLIC_DATA_WIDTH - 1 : 0] int_pending_status_read_data;
assign int_pending_status_read_data = int_pending_status_sel ? int_pending_status : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		target_priority <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (target_priority_sel && valid_reg_write)
		begin
			target_priority <= write_data;
		end
		else
		begin
			target_priority <= target_priority;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] target_priority_read_data;
assign target_priority_read_data = target_priority_sel ? target_priority : {`KPLIC_DATA_WIDTH{1'b0}};


wire [`KPLIC_DATA_WIDTH - 1 : 0] mppi_read_data;
assign mppi_read_data = mppi_sel ? {27'h0,mppi} : {`KPLIC_DATA_WIDTH{1'b0}};


reg valid_completion;

reg [`INT_WIDTH - 1 : 0] completion_intid;
always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		completion_intid <= {`INT_WIDTH{1'b0}};
	end
	else
	begin
		if (valid_reg_write && int_completion_sel)
		begin
			completion_intid <= write_data[`INT_WIDTH - 1 : 0];
		end
		else
		begin
			completion_intid <= completion_intid;
		end
	end
end

always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		valid_completion <= 1'b0;
	end
	else
	begin
		if(valid_reg_write && int_completion_sel && (write_data[`INT_WIDTH - 1 : 0] < `INT_NUM))
		begin
			valid_completion <= 1'b1;
		end
		else
		begin
			valid_completion <= 1'b0;
		end
	end
end

integer i;

always @ *
begin
	for (i=0; i<`INT_NUM; i=i+1)
	begin
		if(valid_completion && (i==completion_intid))
			int_completion[i] = 1'b1;
		else
			int_completion[i] = 1'b0; 
	end
end


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group0 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group0_sel && valid_reg_write)
		begin
			int_priority_group0 <= write_data;
		end
		else
		begin
			int_priority_group0 <= int_priority_group0;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group0_read_data;
assign int_priority_group0_read_data = int_priority_group0_sel ? int_priority_group0 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group1 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group1_sel && valid_reg_write)
		begin
			int_priority_group1 <= write_data;
		end
		else
		begin
			int_priority_group1 <= int_priority_group1;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group1_read_data;
assign int_priority_group1_read_data = int_priority_group1_sel ? int_priority_group1 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group2 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group2_sel && valid_reg_write)
		begin
			int_priority_group2 <= write_data;
		end
		else
		begin
			int_priority_group2 <= int_priority_group2;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group2_read_data;
assign int_priority_group2_read_data = int_priority_group2_sel ? int_priority_group2 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group3 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group3_sel && valid_reg_write)
		begin
			int_priority_group3 <= write_data;
		end
		else
		begin
			int_priority_group3 <= int_priority_group3;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group3_read_data;
assign int_priority_group3_read_data = int_priority_group3_sel ? int_priority_group3 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group4 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group4_sel && valid_reg_write)
		begin
			int_priority_group4 <= write_data;
		end
		else
		begin
			int_priority_group4 <= int_priority_group4;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group4_read_data;
assign int_priority_group4_read_data = int_priority_group4_sel ? int_priority_group4 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group5 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group5_sel && valid_reg_write)
		begin
			int_priority_group5 <= write_data;
		end
		else
		begin
			int_priority_group5 <= int_priority_group5;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group5_read_data;
assign int_priority_group5_read_data = int_priority_group5_sel ? int_priority_group5 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group6 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group6_sel && valid_reg_write)
		begin
			int_priority_group6 <= write_data;
		end
		else
		begin
			int_priority_group6 <= int_priority_group6;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group6_read_data;
assign int_priority_group6_read_data = int_priority_group6_sel ? int_priority_group6 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group7 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group7_sel && valid_reg_write)
		begin
			int_priority_group7 <= write_data;
		end
		else
		begin
			int_priority_group7 <= int_priority_group7;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group7_read_data;
assign int_priority_group7_read_data = int_priority_group7_sel ? int_priority_group7 : {`KPLIC_DATA_WIDTH{1'b0}};



assign read_data = {32{valid_reg_read}} &
		       (int_type_read_data 		|
			int_enable_read_data 		|
			int_pending_status_read_data 	|
			target_priority_read_data 	|
			mppi_read_data 			|
			int_priority_group0_read_data 	|
			int_priority_group1_read_data 	|
			int_priority_group2_read_data 	|
			int_priority_group3_read_data 	|
			int_priority_group4_read_data 	|
			int_priority_group5_read_data 	|
			int_priority_group6_read_data 	|
			int_priority_group7_read_data) ;

assign int_claim = valid_reg_read & mppi_sel;

endmodule
module kplic_regs (

input wire kplic_clk,
input wire kplic_rstn,


input wire valid_reg_access,
input wire [11:0] addr,
input wire rd_wr,
input wire [`KPLIC_DATA_WIDTH - 1 : 0] write_data,
output wire [`KPLIC_DATA_WIDTH - 1 : 0] read_data,


output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_type,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_enable,
output reg [`INT_NUM - 1  : 0] int_completion,


input wire [`KPLIC_DATA_WIDTH - 1 : 0] int_pending_status,
input wire [`INT_WIDTH - 1 : 0] mppi,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] target_priority,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group0,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group1,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group2,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group3,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group4,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group5,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group6,
output reg [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group7,
output wire int_claim
);






wire int_type_sel;
wire int_enable_sel;
wire int_pending_status_sel;
wire target_priority_sel;
wire int_completion_sel;
wire mppi_sel;
wire int_priority_group0_sel;
wire int_priority_group1_sel;
wire int_priority_group2_sel;
wire int_priority_group3_sel;
wire int_priority_group4_sel;
wire int_priority_group5_sel;
wire int_priority_group6_sel;
wire int_priority_group7_sel;

assign int_type_sel = (addr == `KPLIC_INT_TYPE_OFFSET);
assign int_enable_sel = (addr == `KPLIC_INT_ENABLE_OFFSET);
assign int_pending_status_sel = (addr == `KPLIC_INT_PENDING_STATUS_OFFSET);
assign target_priority_sel = (addr == `KPLIC_TARGET_PRIORITY_OFFSET);
assign int_completion_sel =(addr == `KPLIC_INT_COMPLETION_OFFSET); 
assign mppi_sel = (addr == `KPLIC_MPPI_OFFSET);
assign int_priority_group0_sel = (addr == `KPLIC_INT_PRIORITY_GROUP0_OFFSET);
assign int_priority_group1_sel = (addr == `KPLIC_INT_PRIORITY_GROUP1_OFFSET);
assign int_priority_group2_sel = (addr == `KPLIC_INT_PRIORITY_GROUP2_OFFSET);
assign int_priority_group3_sel = (addr == `KPLIC_INT_PRIORITY_GROUP3_OFFSET);
assign int_priority_group4_sel = (addr == `KPLIC_INT_PRIORITY_GROUP4_OFFSET);
assign int_priority_group5_sel = (addr == `KPLIC_INT_PRIORITY_GROUP5_OFFSET);
assign int_priority_group6_sel = (addr == `KPLIC_INT_PRIORITY_GROUP6_OFFSET);
assign int_priority_group7_sel = (addr == `KPLIC_INT_PRIORITY_GROUP7_OFFSET);




wire valid_reg_read;
wire valid_reg_write;
assign valid_reg_read = valid_reg_access & !rd_wr;
assign valid_reg_write = valid_reg_access & rd_wr;


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_type <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_type_sel && valid_reg_write)
		begin
			int_type <= write_data;
		end
		else
		begin
			int_type <= int_type;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_type_read_data;
assign int_type_read_data = int_type_sel ? int_type : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_enable <= {`KPLIC_DATA_WIDTH{1'b1}};
	end
	else
	begin
		if (int_enable_sel && valid_reg_write)
		begin
			int_enable <= write_data;
		end
		else
		begin
			int_enable <= int_enable;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_enable_read_data;
assign int_enable_read_data = int_enable_sel ? int_enable : {`KPLIC_DATA_WIDTH{1'b0}};



wire [`KPLIC_DATA_WIDTH - 1 : 0] int_pending_status_read_data;
assign int_pending_status_read_data = int_pending_status_sel ? int_pending_status : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		target_priority <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (target_priority_sel && valid_reg_write)
		begin
			target_priority <= write_data;
		end
		else
		begin
			target_priority <= target_priority;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] target_priority_read_data;
assign target_priority_read_data = target_priority_sel ? target_priority : {`KPLIC_DATA_WIDTH{1'b0}};


wire [`KPLIC_DATA_WIDTH - 1 : 0] mppi_read_data;
assign mppi_read_data = mppi_sel ? {27'h0,mppi} : {`KPLIC_DATA_WIDTH{1'b0}};


reg valid_completion;

reg [`INT_WIDTH - 1 : 0] completion_intid;
always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		completion_intid <= {`INT_WIDTH{1'b0}};
	end
	else
	begin
		if (valid_reg_write && int_completion_sel)
		begin
			completion_intid <= write_data[`INT_WIDTH - 1 : 0];
		end
		else
		begin
			completion_intid <= completion_intid;
		end
	end
end

always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		valid_completion <= 1'b0;
	end
	else
	begin
		if(valid_reg_write && int_completion_sel && (write_data[`INT_WIDTH - 1 : 0] < `INT_NUM))
		begin
			valid_completion <= 1'b1;
		end
		else
		begin
			valid_completion <= 1'b0;
		end
	end
end

integer i;

always @ *
begin
	for (i=0; i<`INT_NUM; i=i+1)
	begin
		if(valid_completion && (i==completion_intid))
			int_completion[i] = 1'b1;
		else
			int_completion[i] = 1'b0; 
	end
end


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group0 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group0_sel && valid_reg_write)
		begin
			int_priority_group0 <= write_data;
		end
		else
		begin
			int_priority_group0 <= int_priority_group0;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group0_read_data;
assign int_priority_group0_read_data = int_priority_group0_sel ? int_priority_group0 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group1 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group1_sel && valid_reg_write)
		begin
			int_priority_group1 <= write_data;
		end
		else
		begin
			int_priority_group1 <= int_priority_group1;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group1_read_data;
assign int_priority_group1_read_data = int_priority_group1_sel ? int_priority_group1 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group2 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group2_sel && valid_reg_write)
		begin
			int_priority_group2 <= write_data;
		end
		else
		begin
			int_priority_group2 <= int_priority_group2;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group2_read_data;
assign int_priority_group2_read_data = int_priority_group2_sel ? int_priority_group2 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group3 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group3_sel && valid_reg_write)
		begin
			int_priority_group3 <= write_data;
		end
		else
		begin
			int_priority_group3 <= int_priority_group3;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group3_read_data;
assign int_priority_group3_read_data = int_priority_group3_sel ? int_priority_group3 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group4 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group4_sel && valid_reg_write)
		begin
			int_priority_group4 <= write_data;
		end
		else
		begin
			int_priority_group4 <= int_priority_group4;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group4_read_data;
assign int_priority_group4_read_data = int_priority_group4_sel ? int_priority_group4 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group5 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group5_sel && valid_reg_write)
		begin
			int_priority_group5 <= write_data;
		end
		else
		begin
			int_priority_group5 <= int_priority_group5;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group5_read_data;
assign int_priority_group5_read_data = int_priority_group5_sel ? int_priority_group5 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group6 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group6_sel && valid_reg_write)
		begin
			int_priority_group6 <= write_data;
		end
		else
		begin
			int_priority_group6 <= int_priority_group6;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group6_read_data;
assign int_priority_group6_read_data = int_priority_group6_sel ? int_priority_group6 : {`KPLIC_DATA_WIDTH{1'b0}};


always @ (posedge kplic_clk or negedge kplic_rstn)
begin
	if (!kplic_rstn)
	begin
		int_priority_group7 <= {`KPLIC_DATA_WIDTH{1'b0}};
	end
	else
	begin
		if (int_priority_group7_sel && valid_reg_write)
		begin
			int_priority_group7 <= write_data;
		end
		else
		begin
			int_priority_group7 <= int_priority_group7;
		end
	end
end
wire [`KPLIC_DATA_WIDTH - 1 : 0] int_priority_group7_read_data;
assign int_priority_group7_read_data = int_priority_group7_sel ? int_priority_group7 : {`KPLIC_DATA_WIDTH{1'b0}};



assign read_data = {32{valid_reg_read}} &
		       (int_type_read_data 		|
			int_enable_read_data 		|
			int_pending_status_read_data 	|
			target_priority_read_data 	|
			mppi_read_data 			|
			int_priority_group0_read_data 	|
			int_priority_group1_read_data 	|
			int_priority_group2_read_data 	|
			int_priority_group3_read_data 	|
			int_priority_group4_read_data 	|
			int_priority_group5_read_data 	|
			int_priority_group6_read_data 	|
			int_priority_group7_read_data) ;

assign int_claim = valid_reg_read & mppi_sel;

endmodule