data/full_repos/permissive/117436613/mmix/bus_adapter.sv
 line:51: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/117436613/mmix/bus_adapter.sv:77: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                           : ... In instance bus_adapter\n    i_byteenable = 2\'b11 << (mem_address[2:1] * 2);\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/117436613/mmix/bus_adapter.sv:82: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                           : ... In instance bus_adapter\n    i_byteenable = 4\'b1111 << (mem_address[2] * 4);\n                           ^~\n%Error: Exiting due to 2 warning(s)\n'
module bus_adapter(
		input  wire        clk,
		input  wire        reset_n,

		input  wire [63:0] mem_address,
		input	 wire [1:0]  mem_datasize,
		input	 wire			 mem_read,
		output wire [63:0] mem_readdata,
		input  wire			 mem_write,
		input  wire [63:0] mem_writedata,
		output wire			 mem_done,
	
		output wire [27:0] d_address,
		output wire [7:0]  d_byteenable,
		output wire        d_read,
		input  wire [63:0] d_readdata,
		input  wire        d_waitrequest,
		output wire        d_write,
		output wire [63:0] d_writedata,
		input  wire        d_readdatavalid
	);

	logic			write_done;
	logic [1:0]	i_state;
	logic			i_request;
	logic [63:0]	i_readdata;
	logic [63:0]	i_writedata;
	logic [7:0]		i_byteenable;

	function [63:0] octa_swap (input [63:0] in);
		octa_swap = {	in[7:0], in[15:8],
							in[23:16], in[31:24],
							in[39:32], in[47:40],
							in[55:48], in[63:56]};
	endfunction
	
	assign mem_readdata = octa_swap(i_readdata);
	assign d_writedata = octa_swap(i_writedata);
							
	assign d_address = {mem_address[48], mem_address[26:3], 3'b000};
	assign i_request = ~i_state[1];
	assign d_read = mem_read & i_request;
	assign d_write = mem_write & i_request;
	assign d_byteenable = i_byteenable;

	assign mem_done = (i_state == 2) ? d_readdatavalid : write_done;
	
	always_comb begin
		case (mem_datasize)
		0:	begin
				i_byteenable = 1'b1 << mem_address[2:0];
				i_readdata = d_readdata << ((7 - mem_address[2:0]) << 3);
				i_writedata = mem_writedata << ((7 - mem_address[2:0]) << 3);
			end
		1:	begin
				i_byteenable = 2'b11 << (mem_address[2:1] * 2);
				i_readdata = d_readdata << ((3 - mem_address[2:1]) << 4);
				i_writedata = mem_writedata << ((3 - mem_address[2:1]) << 4);
			end
		2:	begin
				i_byteenable = 4'b1111 << (mem_address[2] * 4);
				i_readdata = d_readdata << ((1 - mem_address[2]) << 5);
				i_writedata = mem_writedata << ((1 - mem_address[2]) << 5);
			end
		3:	begin
				i_byteenable = 8'b11111111;
				i_readdata = d_readdata;
				i_writedata = mem_writedata;
			end
		endcase
	end
	
	always_ff @(posedge clk or negedge reset_n)
	begin
		if (reset_n == 0)
			begin
				i_state <= 0;
				write_done <= 0;
			end	
		else
			case (i_state)
			0:
				if (mem_read | mem_write)
					begin
						i_state <= 1;

					end
			1:
				if (d_waitrequest == 0)
					begin
						if (mem_read)
							i_state <= 2;
						else begin
							i_state <= 3;
							write_done <= 1;
						end
					end
			2:
				if (d_readdatavalid == 1)
					begin
						i_state <= 0;
					end
			3: begin
					i_state <= 0;
					write_done <= 0;
				end
			endcase
	end
	
endmodule
module bus_adapter(
		input  wire        clk,
		input  wire        reset_n,

		input  wire [63:0] mem_address,
		input	 wire [1:0]  mem_datasize,
		input	 wire			 mem_read,
		output wire [63:0] mem_readdata,
		input  wire			 mem_write,
		input  wire [63:0] mem_writedata,
		output wire			 mem_done,
	
		output wire [27:0] d_address,
		output wire [7:0]  d_byteenable,
		output wire        d_read,
		input  wire [63:0] d_readdata,
		input  wire        d_waitrequest,
		output wire        d_write,
		output wire [63:0] d_writedata,
		input  wire        d_readdatavalid
	);


	logic			write_done;
	logic [1:0]	i_state;
	logic			i_request;
	logic [63:0]	i_readdata;
	logic [63:0]	i_writedata;
	logic [7:0]		i_byteenable;

	function [63:0] octa_swap (input [63:0] in);
		octa_swap = {	in[7:0], in[15:8],
							in[23:16], in[31:24],
							in[39:32], in[47:40],
							in[55:48], in[63:56]};
	endfunction
	
	assign mem_readdata = octa_swap(i_readdata);
	assign d_writedata = octa_swap(i_writedata);
							
	assign d_address = {mem_address[48], mem_address[26:3], 3'b000};
	assign i_request = ~i_state[1];
	assign d_read = mem_read & i_request;
	assign d_write = mem_write & i_request;
	assign d_byteenable = i_byteenable;

	assign mem_done = (i_state == 2) ? d_readdatavalid : write_done;
	
	always_comb begin
		case (mem_datasize)
		0:	begin
				i_byteenable = 1'b1 << mem_address[2:0];
				i_readdata = d_readdata << ((7 - mem_address[2:0]) << 3);
				i_writedata = mem_writedata << ((7 - mem_address[2:0]) << 3);
			end
		1:	begin
				i_byteenable = 2'b11 << (mem_address[2:1] * 2);
				i_readdata = d_readdata << ((3 - mem_address[2:1]) << 4);
				i_writedata = mem_writedata << ((3 - mem_address[2:1]) << 4);
			end
		2:	begin
				i_byteenable = 4'b1111 << (mem_address[2] * 4);
				i_readdata = d_readdata << ((1 - mem_address[2]) << 5);
				i_writedata = mem_writedata << ((1 - mem_address[2]) << 5);
			end
		3:	begin
				i_byteenable = 8'b11111111;
				i_readdata = d_readdata;
				i_writedata = mem_writedata;
			end
		endcase
	end
	
	always_ff @(posedge clk or negedge reset_n)
	begin
		if (reset_n == 0)
			begin
				i_state <= 0;
				write_done <= 0;
			end	
		else
			case (i_state)
			0:
				if (mem_read | mem_write)
					begin
						i_state <= 1;

					end
			1:
				if (d_waitrequest == 0)
					begin
						if (mem_read)
							i_state <= 2;
						else begin
							i_state <= 3;
							write_done <= 1;
						end
					end
			2:
				if (d_readdatavalid == 1)
					begin
						i_state <= 0;
					end
			3: begin
					i_state <= 0;
					write_done <= 0;
				end
			endcase
	end
	
endmodule