data/full_repos/permissive/101862289/bitcounter.v
data/verilator_xmls/f8b84d85-2fa2-4c04-9d87-a36c1eda3ace.xml
module bitcounter(
    input start,
    input en,
	 input clk,
	 input rst,
    output [3:0] out
    );
wire engedelyezes;
wire nemnulla;
reg[3:0] Q;

assign nemnulla =(Q>4'b0);
assign engedelyezes = (en&(start|nemnulla));


always@(posedge clk)
begin
	if(rst|(en&Q==10)) Q<=4'b0;
	else if(engedelyezes) Q<=Q+1;
end

assign out = Q;

endmodule
module bitcounter(
    input start,
    input en,
	 input clk,
	 input rst,
    output [3:0] out
    );

wire engedelyezes;
wire nemnulla;
reg[3:0] Q;

assign nemnulla =(Q>4'b0);
assign engedelyezes = (en&(start|nemnulla));


always@(posedge clk)
begin
	if(rst|(en&Q==10)) Q<=4'b0;
	else if(engedelyezes) Q<=Q+1;
end

assign out = Q;

endmodule