data/full_repos/permissive/175808891/verilog/prv32.v
 line:209: before: "("
1: b"%Error: data/full_repos/permissive/175808891/verilog/prv32.v:280: syntax error, unexpected type\n    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));\n                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:310: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    output reg [31:0] do\n                      ^~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:315: syntax error, unexpected '='\n        3'b100  : do = {24'b0,di[7:0]};\n                     ^\n%Error: Cannot continue\n"
module prv32_HazardsUnit (
    input wire [4:0] rs1, rs2,
    input wire [4:0] rd,
    input wire rd_valid, rs1_valid, rs2_valid,
    output fwd1, fwd2
);

    assign fwd1 = rd_valid & rs1_valid & ((rd == rs1) && (rs1 != 0));
    assign fwd2 = rd_valid & rs2_valid & ((rd == rs2) && (rs2 != 0));

endmodule
module prv32_HazardsUnit (
    input wire [4:0] rs1, rs2,
    input wire [4:0] rd,
    input wire rd_valid, rs1_valid, rs2_valid,
    output fwd1, fwd2
);


    assign fwd1 = rd_valid & rs1_valid & ((rd == rs1) && (rs1 != 0));
    assign fwd2 = rd_valid & rs2_valid & ((rd == rs2) && (rs2 != 0));

endmodule