data/full_repos/permissive/174917352/RTL/Memory.v
data/verilator_xmls/10a804b6-5f4e-4dd4-b0f7-e9483df3c8e7.xml
module Memory(clk,
              rst_b,
              addr,
              data_in,
              write_read,
              data_out);

input wire clk;
input wire rst_b;
input wire [5:0]addr;
input wire [15:0]data_in;
input wire write_read;

output reg [15:0]data_out;

reg [15:0]Memory[63:0];

always @(posedge clk)
if (!write_read)
    Memory[addr] <= data_in;
else 
    Memory[addr] <= 16'b0;

always @(posedge clk)
if(write_read)
    data_out <= Memory[addr];
else 
    data_out <= 16'b0;

endmodule
module Memory(clk,
              rst_b,
              addr,
              data_in,
              write_read,
              data_out);


input wire clk;
input wire rst_b;
input wire [5:0]addr;
input wire [15:0]data_in;
input wire write_read;

output reg [15:0]data_out;

reg [15:0]Memory[63:0];

always @(posedge clk)
if (!write_read)
    Memory[addr] <= data_in;
else 
    Memory[addr] <= 16'b0;

always @(posedge clk)
if(write_read)
    data_out <= Memory[addr];
else 
    data_out <= 16'b0;

endmodule