data/full_repos/permissive/143278/ivltests/pr3549328.v
1: b"%Error: data/full_repos/permissive/143278/ivltests/pr3549328.v:14: Expecting expression to be constant, but variable isn't const: 'wid2'\n                                                                 : ... In instance bug\nwire part2 = |vector[off2 +: wid2];\n                             ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr3549328.v:14: Width of :+ or :- bit extract isn't a constant\n                                                                 : ... In instance bug\nwire part2 = |vector[off2 +: wid2];\n                             ^~~~\n%Error: Exiting due to 2 error(s)\n"
module bug();

localparam off1 = 1;
localparam wid1 = 0;

integer off2 = 1;
integer wid2 = 0;

wire [7:0] vector = 8'h55;

wire part1 = |vector[off1 +: wid1];
wire part2 = |vector[off2 +: wid2];

endmodule
module bug();


localparam off1 = 1;
localparam wid1 = 0;

integer off2 = 1;
integer wid2 = 0;

wire [7:0] vector = 8'h55;

wire part1 = |vector[off1 +: wid1];
wire part2 = |vector[off2 +: wid2];

endmodule