data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/axil_regport_master.v
 line:12: before: "dapter"
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/axil_regport_master.v:153: Cannot find file containing module: 'axi_fifo_2clk'\n   axi_fifo_2clk #( .WIDTH(DWIDTH/8 + AWIDTH + DWIDTH), .SIZE(0) ) wr_fifo_2clk_i (\n   ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/axi_fifo_2clk\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/axi_fifo_2clk.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/axi_fifo_2clk.sv\n             axi_fifo_2clk\n             axi_fifo_2clk.v\n             axi_fifo_2clk.sv\n             obj_dir/axi_fifo_2clk\n             obj_dir/axi_fifo_2clk.v\n             obj_dir/axi_fifo_2clk.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/axil_regport_master.v:230: Cannot find file containing module: 'axi_fifo_2clk'\n   axi_fifo_2clk #( .WIDTH(AWIDTH), .SIZE(0) ) readreq_fifo_2clk_i (\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/axil_regport_master.v:239: Cannot find file containing module: 'axi_fifo_2clk'\n   axi_fifo_2clk #( .WIDTH(DWIDTH), .SIZE(0) ) rdresp_fifo_2clk_i (\n   ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module axil_regport_master #(
  parameter DWIDTH  = 32,
  parameter AWIDTH  = 32,
  parameter WRBASE  = 32'h0,
  parameter RDBASE  = 32'h0,
  parameter TIMEOUT = 10
)(

  input                      s_axi_aclk,
  input                      s_axi_aresetn,
  input                      reg_clk,

  input      [AWIDTH-1:0]    s_axi_awaddr,
  input                      s_axi_awvalid,
  output reg                 s_axi_awready,

  input      [DWIDTH-1:0]    s_axi_wdata,
  input      [DWIDTH/8-1:0]  s_axi_wstrb,
  input                      s_axi_wvalid,
  output reg                 s_axi_wready,

  output reg [1:0]           s_axi_bresp,
  output reg                 s_axi_bvalid,
  input                      s_axi_bready,

  input      [AWIDTH-1:0]    s_axi_araddr,
  input                      s_axi_arvalid,
  output reg                 s_axi_arready,

  output reg [DWIDTH-1:0]    s_axi_rdata,
  output reg [1:0]           s_axi_rresp,
  output reg                 s_axi_rvalid,
  input                      s_axi_rready,

  output                     reg_wr_req,
  output     [AWIDTH-1:0]    reg_wr_addr,
  output     [DWIDTH-1:0]    reg_wr_data,
  output     [DWIDTH/8-1:0]  reg_wr_keep,

  output                     reg_rd_req,
  output     [AWIDTH-1:0]    reg_rd_addr,
  input                      reg_rd_resp,
  input      [DWIDTH-1:0]    reg_rd_data
);

  localparam ADDR_LSB = $clog2(DWIDTH/8);




  reg [AWIDTH-1:0]  wr_addr_cache;
  wire              wr_fifo_valid, wr_fifo_ready;
  wire [AWIDTH-1:0] wr_addr_rel = (s_axi_awaddr - WRBASE);


  always @(posedge s_axi_aclk) begin
     if (!s_axi_aresetn) begin
        s_axi_awready <= 1'b0;
        wr_addr_cache <= {AWIDTH{1'b0}};
     end else begin
        if (~s_axi_awready && s_axi_awvalid && s_axi_wvalid && wr_fifo_ready) begin
           s_axi_awready <= 1'b1;
           wr_addr_cache <= {wr_addr_rel[AWIDTH-1:ADDR_LSB], {ADDR_LSB{1'b0}}};
        end else begin
           s_axi_awready <= 1'b0;
        end
     end
  end


  always @(posedge s_axi_aclk) begin
     if (!s_axi_aresetn) begin
        s_axi_wready <= 1'b0;
     end else begin
        if (~s_axi_wready && s_axi_wvalid && s_axi_awvalid && wr_fifo_ready) begin
           s_axi_wready <= 1'b1;
        end else begin
           s_axi_wready <= 1'b0;
        end
     end
  end


  assign wr_fifo_valid = s_axi_awready && s_axi_awvalid && s_axi_wready && s_axi_wvalid;

  reg [4:0]  unacked_writes;
  always @(posedge s_axi_aclk) begin
     if (!s_axi_aresetn) begin
        s_axi_bvalid   <= 1'b0;
        s_axi_bresp    <= 2'b0;
        unacked_writes <= 0;
     end else begin
        s_axi_bresp <= 2'b0;
        if (wr_fifo_valid && wr_fifo_ready) begin
           unacked_writes <= unacked_writes+1;
        end
        if (unacked_writes > 0) begin

           s_axi_bvalid <= 1'b1;
        end
        if (s_axi_bready && s_axi_bvalid) begin
           if (wr_fifo_valid && wr_fifo_ready)
             unacked_writes <= unacked_writes;
           else
             unacked_writes <= unacked_writes-1;
           s_axi_bvalid <= 1'b0;
        end
     end
  end

   axi_fifo_2clk #( .WIDTH(DWIDTH/8 + AWIDTH + DWIDTH), .SIZE(0) ) wr_fifo_2clk_i (
      .reset(~s_axi_aresetn), .i_aclk(s_axi_aclk),
      .i_tdata({s_axi_wstrb, wr_addr_cache, s_axi_wdata}),
      .i_tvalid(wr_fifo_valid), .i_tready(wr_fifo_ready),
      .o_aclk(reg_clk),
      .o_tdata({reg_wr_keep, reg_wr_addr, reg_wr_data}),
      .o_tvalid(reg_wr_req), .o_tready(1'b1)
   );




   reg [TIMEOUT-1:0] read_pending_ctr = {TIMEOUT{1'b0}};
   wire              read_timed_out = (read_pending_ctr == {{(TIMEOUT-1){1'b0}}, 1'b1});
   wire [AWIDTH-1:0] rd_addr_rel = (s_axi_araddr - RDBASE);

   wire              rdreq_fifo_ready, rdresp_fifo_valid;
   wire [DWIDTH-1:0] rdresp_fifo_data;


   reg [4:0]  unacked_reads;
   always @(posedge s_axi_aclk) begin
      if (!s_axi_aresetn) begin
         s_axi_arready <= 1'b0;
         read_pending_ctr <= {TIMEOUT{1'b0}};
         unacked_reads <= 0;
      end else begin
         if (unacked_reads > 0) begin
            if (read_pending_ctr > 0) begin
               read_pending_ctr <= read_pending_ctr-1;
            end
         end else begin
            read_pending_ctr <= {TIMEOUT{1'b0}};
         end

         if (~s_axi_arready && s_axi_arvalid && rdreq_fifo_ready) begin
            s_axi_arready <= 1'b1;
            read_pending_ctr <= {TIMEOUT{1'b1}};
            unacked_reads <= unacked_reads+1;            
         end else begin
            s_axi_arready <= 1'b0;
         end
         
         if (s_axi_rvalid && s_axi_rready) begin
            if (~s_axi_arready && s_axi_arvalid && rdreq_fifo_ready) begin
               unacked_reads <= unacked_reads;
            end else begin
               unacked_reads <= unacked_reads-1;
            end
         end         
      end
   end


   always @(posedge s_axi_aclk) begin
      if (!s_axi_aresetn) begin
         s_axi_rvalid <= 1'b0;
         s_axi_rresp <= 2'b00;
         s_axi_rdata <= 0;
      end else begin
         if (unacked_reads > 0 && rdresp_fifo_valid && ~s_axi_rvalid) begin

            s_axi_rvalid <= 1'b1;
            s_axi_rresp <= 2'b00;
            s_axi_rdata <= rdresp_fifo_data;
         end else if (unacked_reads > 0 && read_timed_out && ~s_axi_rvalid) begin

            s_axi_rvalid <= 1'b1;
            s_axi_rresp <= 2'b10;
            s_axi_rdata <= {DWIDTH{1'b1}};
         end else if (s_axi_rvalid && s_axi_rready) begin

            s_axi_rvalid <= 1'b0;
         end
      end
   end

   axi_fifo_2clk #( .WIDTH(AWIDTH), .SIZE(0) ) readreq_fifo_2clk_i (
      .reset(~s_axi_aresetn), .i_aclk(s_axi_aclk),
      .i_tdata({rd_addr_rel[AWIDTH-1:ADDR_LSB], {ADDR_LSB{1'b0}}}),
      .i_tvalid(s_axi_arready && s_axi_arvalid), .i_tready(rdreq_fifo_ready),
      .o_aclk(reg_clk),
      .o_tdata(reg_rd_addr),
      .o_tvalid(reg_rd_req), .o_tready(1'b1)
   );

   axi_fifo_2clk #( .WIDTH(DWIDTH), .SIZE(0) ) rdresp_fifo_2clk_i (
      .reset(~s_axi_aresetn), .i_aclk(reg_clk),
      .i_tdata(reg_rd_data),
      .i_tvalid(reg_rd_resp), .i_tready(),
      .o_aclk(s_axi_aclk),
      .o_tdata(rdresp_fifo_data),
      .o_tvalid(rdresp_fifo_valid), .o_tready((unacked_reads==0) || (s_axi_rvalid && s_axi_rready && (s_axi_rresp == 2'b00)))
   );

endmodule
module axil_regport_master #(
  parameter DWIDTH  = 32,
  parameter AWIDTH  = 32,
  parameter WRBASE  = 32'h0,
  parameter RDBASE  = 32'h0,
  parameter TIMEOUT = 10
)(

  input                      s_axi_aclk,
  input                      s_axi_aresetn,
  input                      reg_clk,

  input      [AWIDTH-1:0]    s_axi_awaddr,
  input                      s_axi_awvalid,
  output reg                 s_axi_awready,

  input      [DWIDTH-1:0]    s_axi_wdata,
  input      [DWIDTH/8-1:0]  s_axi_wstrb,
  input                      s_axi_wvalid,
  output reg                 s_axi_wready,

  output reg [1:0]           s_axi_bresp,
  output reg                 s_axi_bvalid,
  input                      s_axi_bready,

  input      [AWIDTH-1:0]    s_axi_araddr,
  input                      s_axi_arvalid,
  output reg                 s_axi_arready,

  output reg [DWIDTH-1:0]    s_axi_rdata,
  output reg [1:0]           s_axi_rresp,
  output reg                 s_axi_rvalid,
  input                      s_axi_rready,

  output                     reg_wr_req,
  output     [AWIDTH-1:0]    reg_wr_addr,
  output     [DWIDTH-1:0]    reg_wr_data,
  output     [DWIDTH/8-1:0]  reg_wr_keep,

  output                     reg_rd_req,
  output     [AWIDTH-1:0]    reg_rd_addr,
  input                      reg_rd_resp,
  input      [DWIDTH-1:0]    reg_rd_data
);


  localparam ADDR_LSB = $clog2(DWIDTH/8);




  reg [AWIDTH-1:0]  wr_addr_cache;
  wire              wr_fifo_valid, wr_fifo_ready;
  wire [AWIDTH-1:0] wr_addr_rel = (s_axi_awaddr - WRBASE);


  always @(posedge s_axi_aclk) begin
     if (!s_axi_aresetn) begin
        s_axi_awready <= 1'b0;
        wr_addr_cache <= {AWIDTH{1'b0}};
     end else begin
        if (~s_axi_awready && s_axi_awvalid && s_axi_wvalid && wr_fifo_ready) begin
           s_axi_awready <= 1'b1;
           wr_addr_cache <= {wr_addr_rel[AWIDTH-1:ADDR_LSB], {ADDR_LSB{1'b0}}};
        end else begin
           s_axi_awready <= 1'b0;
        end
     end
  end


  always @(posedge s_axi_aclk) begin
     if (!s_axi_aresetn) begin
        s_axi_wready <= 1'b0;
     end else begin
        if (~s_axi_wready && s_axi_wvalid && s_axi_awvalid && wr_fifo_ready) begin
           s_axi_wready <= 1'b1;
        end else begin
           s_axi_wready <= 1'b0;
        end
     end
  end


  assign wr_fifo_valid = s_axi_awready && s_axi_awvalid && s_axi_wready && s_axi_wvalid;

  reg [4:0]  unacked_writes;
  always @(posedge s_axi_aclk) begin
     if (!s_axi_aresetn) begin
        s_axi_bvalid   <= 1'b0;
        s_axi_bresp    <= 2'b0;
        unacked_writes <= 0;
     end else begin
        s_axi_bresp <= 2'b0;
        if (wr_fifo_valid && wr_fifo_ready) begin
           unacked_writes <= unacked_writes+1;
        end
        if (unacked_writes > 0) begin

           s_axi_bvalid <= 1'b1;
        end
        if (s_axi_bready && s_axi_bvalid) begin
           if (wr_fifo_valid && wr_fifo_ready)
             unacked_writes <= unacked_writes;
           else
             unacked_writes <= unacked_writes-1;
           s_axi_bvalid <= 1'b0;
        end
     end
  end

   axi_fifo_2clk #( .WIDTH(DWIDTH/8 + AWIDTH + DWIDTH), .SIZE(0) ) wr_fifo_2clk_i (
      .reset(~s_axi_aresetn), .i_aclk(s_axi_aclk),
      .i_tdata({s_axi_wstrb, wr_addr_cache, s_axi_wdata}),
      .i_tvalid(wr_fifo_valid), .i_tready(wr_fifo_ready),
      .o_aclk(reg_clk),
      .o_tdata({reg_wr_keep, reg_wr_addr, reg_wr_data}),
      .o_tvalid(reg_wr_req), .o_tready(1'b1)
   );




   reg [TIMEOUT-1:0] read_pending_ctr = {TIMEOUT{1'b0}};
   wire              read_timed_out = (read_pending_ctr == {{(TIMEOUT-1){1'b0}}, 1'b1});
   wire [AWIDTH-1:0] rd_addr_rel = (s_axi_araddr - RDBASE);

   wire              rdreq_fifo_ready, rdresp_fifo_valid;
   wire [DWIDTH-1:0] rdresp_fifo_data;


   reg [4:0]  unacked_reads;
   always @(posedge s_axi_aclk) begin
      if (!s_axi_aresetn) begin
         s_axi_arready <= 1'b0;
         read_pending_ctr <= {TIMEOUT{1'b0}};
         unacked_reads <= 0;
      end else begin
         if (unacked_reads > 0) begin
            if (read_pending_ctr > 0) begin
               read_pending_ctr <= read_pending_ctr-1;
            end
         end else begin
            read_pending_ctr <= {TIMEOUT{1'b0}};
         end

         if (~s_axi_arready && s_axi_arvalid && rdreq_fifo_ready) begin
            s_axi_arready <= 1'b1;
            read_pending_ctr <= {TIMEOUT{1'b1}};
            unacked_reads <= unacked_reads+1;            
         end else begin
            s_axi_arready <= 1'b0;
         end
         
         if (s_axi_rvalid && s_axi_rready) begin
            if (~s_axi_arready && s_axi_arvalid && rdreq_fifo_ready) begin
               unacked_reads <= unacked_reads;
            end else begin
               unacked_reads <= unacked_reads-1;
            end
         end         
      end
   end


   always @(posedge s_axi_aclk) begin
      if (!s_axi_aresetn) begin
         s_axi_rvalid <= 1'b0;
         s_axi_rresp <= 2'b00;
         s_axi_rdata <= 0;
      end else begin
         if (unacked_reads > 0 && rdresp_fifo_valid && ~s_axi_rvalid) begin

            s_axi_rvalid <= 1'b1;
            s_axi_rresp <= 2'b00;
            s_axi_rdata <= rdresp_fifo_data;
         end else if (unacked_reads > 0 && read_timed_out && ~s_axi_rvalid) begin

            s_axi_rvalid <= 1'b1;
            s_axi_rresp <= 2'b10;
            s_axi_rdata <= {DWIDTH{1'b1}};
         end else if (s_axi_rvalid && s_axi_rready) begin

            s_axi_rvalid <= 1'b0;
         end
      end
   end

   axi_fifo_2clk #( .WIDTH(AWIDTH), .SIZE(0) ) readreq_fifo_2clk_i (
      .reset(~s_axi_aresetn), .i_aclk(s_axi_aclk),
      .i_tdata({rd_addr_rel[AWIDTH-1:ADDR_LSB], {ADDR_LSB{1'b0}}}),
      .i_tvalid(s_axi_arready && s_axi_arvalid), .i_tready(rdreq_fifo_ready),
      .o_aclk(reg_clk),
      .o_tdata(reg_rd_addr),
      .o_tvalid(reg_rd_req), .o_tready(1'b1)
   );

   axi_fifo_2clk #( .WIDTH(DWIDTH), .SIZE(0) ) rdresp_fifo_2clk_i (
      .reset(~s_axi_aresetn), .i_aclk(reg_clk),
      .i_tdata(reg_rd_data),
      .i_tvalid(reg_rd_resp), .i_tready(),
      .o_aclk(s_axi_aclk),
      .o_tdata(rdresp_fifo_data),
      .o_tvalid(rdresp_fifo_valid), .o_tready((unacked_reads==0) || (s_axi_rvalid && s_axi_rready && (s_axi_rresp == 2'b00)))
   );

endmodule