data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:619: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:623: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:628: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  {temp[0], temp[31:1]} = out_left & key_left;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:596: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:600: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:604: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  {temp[0], temp[31:1]} = in_left & key_left;\n                                ^\n%Error: Exiting due to 14 warning(s)\n'
module Camellia_f_func(in, out, key);
  input  [63:0] in;
  input [63:0] 	key;
  output [63:0] out;

  wire [63:0] 	key_added;
  reg [7:0] 	y1, y2, y3, y4, y5, y6, y7, y8;
  wire [7:0] 	z1, z2, z3, z4, z5, z6, z7, z8;

  assign 	key_added = in ^ key;

  always @(key_added)
  begin
    y1 <= key_added[63:56];
    y2 <= key_added[55:48];
    y3 <= key_added[47:40];
    y4 <= key_added[39:32];
    y5 <= key_added[31:24];
    y6 <= key_added[23:16];
    y7 <= key_added[15:8];
    y8 <= key_added[7:0];
  end

  Camellia_sbox1 Camellia_sbox1a( .in(y1), .out(z1) );
  Camellia_sbox2 Camellia_sbox2a( .in(y2), .out(z2) );
  Camellia_sbox3 Camellia_sbox3a( .in(y3), .out(z3) );
  Camellia_sbox4 Camellia_sbox4a( .in(y4), .out(z4) );
  Camellia_sbox2 Camellia_sbox2b( .in(y5), .out(z5) );
  Camellia_sbox3 Camellia_sbox3b( .in(y6), .out(z6) );
  Camellia_sbox4 Camellia_sbox4b( .in(y7), .out(z7) );
  Camellia_sbox1 Camellia_sbox1b( .in(y8), .out(z8) );
  Camellia_p_func Camellia_p_func(.in( {z1, z2, z3, z4, z5, z6, z7, z8} ), .out(out) );
endmodule
module Camellia_f_func(in, out, key);

  input  [63:0] in;
  input [63:0] 	key;
  output [63:0] out;

  wire [63:0] 	key_added;
  reg [7:0] 	y1, y2, y3, y4, y5, y6, y7, y8;
  wire [7:0] 	z1, z2, z3, z4, z5, z6, z7, z8;

  assign 	key_added = in ^ key;

  always @(key_added)
  begin
    y1 <= key_added[63:56];
    y2 <= key_added[55:48];
    y3 <= key_added[47:40];
    y4 <= key_added[39:32];
    y5 <= key_added[31:24];
    y6 <= key_added[23:16];
    y7 <= key_added[15:8];
    y8 <= key_added[7:0];
  end

  Camellia_sbox1 Camellia_sbox1a( .in(y1), .out(z1) );
  Camellia_sbox2 Camellia_sbox2a( .in(y2), .out(z2) );
  Camellia_sbox3 Camellia_sbox3a( .in(y3), .out(z3) );
  Camellia_sbox4 Camellia_sbox4a( .in(y4), .out(z4) );
  Camellia_sbox2 Camellia_sbox2b( .in(y5), .out(z5) );
  Camellia_sbox3 Camellia_sbox3b( .in(y6), .out(z6) );
  Camellia_sbox4 Camellia_sbox4b( .in(y7), .out(z7) );
  Camellia_sbox1 Camellia_sbox1b( .in(y8), .out(z8) );
  Camellia_p_func Camellia_p_func(.in( {z1, z2, z3, z4, z5, z6, z7, z8} ), .out(out) );
endmodule