data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB3-Verilog/First_tf.v
 line:87: before: ";"
1: b'%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB3-Verilog/First_tf.v:116: Cannot find include file: ./oksim/okHostCalls.v\n`include "./oksim/okHostCalls.v"   // Do not remove!  The tasks, functions, and data stored \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB3-Verilog,data/full_repos/permissive/120539939/./oksim/okHostCalls.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB3-Verilog,data/full_repos/permissive/120539939/./oksim/okHostCalls.v.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB3-Verilog,data/full_repos/permissive/120539939/./oksim/okHostCalls.v.sv\n             ./oksim/okHostCalls.v\n             ./oksim/okHostCalls.v.v\n             ./oksim/okHostCalls.v.sv\n             obj_dir/./oksim/okHostCalls.v\n             obj_dir/./oksim/okHostCalls.v.v\n             obj_dir/./oksim/okHostCalls.v.sv\n%Error: Exiting due to 1 error(s)\n'
module FIRST_TEST;

wire  [4:0]   okUH;
wire  [2:0]   okHU;
wire  [31:0]  okUHU;
wire  [7:0]   led;

First dut (
	.okUH(okUH),
	.okHU(okHU),
	.okUHU(okUHU),
	.led(led)
	);




parameter BlockDelayStates = 5;
parameter ReadyCheckDelay = 5;

parameter PostReadyDelay = 5;

parameter pipeInSize = 1024;

parameter pipeOutSize = 1024;


integer k;
reg  [7:0]  pipeIn [0:(pipeInSize-1)];
initial for (k=0; k<pipeInSize; k=k+1) pipeIn[k] = 8'h00;

reg  [7:0]  pipeOut [0:(pipeOutSize-1)];
initial for (k=0; k<pipeOutSize; k=k+1) pipeOut[k] = 8'h00;

wire [31:0] u32Address [0:31];
reg  [31:0] u32Data [0:31];
wire [31:0] u32Count;
wire [31:0] ReadRegisterData;























reg [31:0] r1, r2, exp, sum;
initial r1 = 0;
initial r2 = 0;
initial exp = 0;
initial sum = 0;

initial begin
	FrontPanelReset;








	for (k=0; k<5; k=k+1) begin

		r1 = $random & 32'hffff_ffff;
		r2 = $random & 32'hffff_ffff;
		exp = r1 + r2;
		SetWireInValue(8'h01, r1, 32'hffff_ffff);
		SetWireInValue(8'h02, r2, 32'hffff_ffff);
		UpdateWireIns;
		

		UpdateWireOuts;
		sum = GetWireOutValue(8'h21);
		if (exp == sum)
			$display("SUCCESS -- Expected: 0x%04h   Received: 0x%04h", exp, sum);
		else
			$display("FAILURE -- Expected: 0x%04h   Received: 0x%04h", exp, sum);
	end

end

`include "./oksim/okHostCalls.v"


endmodule
module FIRST_TEST;


wire  [4:0]   okUH;
wire  [2:0]   okHU;
wire  [31:0]  okUHU;
wire  [7:0]   led;

First dut (
	.okUH(okUH),
	.okHU(okHU),
	.okUHU(okUHU),
	.led(led)
	);




parameter BlockDelayStates = 5;
parameter ReadyCheckDelay = 5;

parameter PostReadyDelay = 5;

parameter pipeInSize = 1024;

parameter pipeOutSize = 1024;


integer k;
reg  [7:0]  pipeIn [0:(pipeInSize-1)];
initial for (k=0; k<pipeInSize; k=k+1) pipeIn[k] = 8'h00;

reg  [7:0]  pipeOut [0:(pipeOutSize-1)];
initial for (k=0; k<pipeOutSize; k=k+1) pipeOut[k] = 8'h00;

wire [31:0] u32Address [0:31];
reg  [31:0] u32Data [0:31];
wire [31:0] u32Count;
wire [31:0] ReadRegisterData;























reg [31:0] r1, r2, exp, sum;
initial r1 = 0;
initial r2 = 0;
initial exp = 0;
initial sum = 0;

initial begin
	FrontPanelReset;








	for (k=0; k<5; k=k+1) begin

		r1 = $random & 32'hffff_ffff;
		r2 = $random & 32'hffff_ffff;
		exp = r1 + r2;
		SetWireInValue(8'h01, r1, 32'hffff_ffff);
		SetWireInValue(8'h02, r2, 32'hffff_ffff);
		UpdateWireIns;
		

		UpdateWireOuts;
		sum = GetWireOutValue(8'h21);
		if (exp == sum)
			$display("SUCCESS -- Expected: 0x%04h   Received: 0x%04h", exp, sum);
		else
			$display("FAILURE -- Expected: 0x%04h   Received: 0x%04h", exp, sum);
	end

end

`include "./oksim/okHostCalls.v"


endmodule