data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v
 line:153: before: "begin"
1: b'%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:88: syntax error, unexpected \'@\'\n      while(rx !== 1\'b1) @(rx);\n                         ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:91: syntax error, unexpected \'@\'\n        while(rx != 1\'b0) @(rx);\n                          ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:92: syntax error, unexpected \'@\'\n        repeat(8) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:94: syntax error, unexpected \'@\'\n           repeat(16) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:97: syntax error, unexpected \'@\'\n        repeat(16) @(posedge clk);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:112: Unsupported: Ignoring delay on this delayed statement.\n   initial #100\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:169: Unsupported: Ignoring delay on this delayed statement.\n         #1000000;\n         ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:171: Unsupported: wait statements\n         wait(gpio);\n         ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:172: Unsupported: Ignoring delay on this delayed statement.\n         if (uart_number == 1) #200000;\n                               ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:213: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:215: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:217: syntax error, unexpected \'@\'\n      repeat (3) @(posedge clk);\n                 ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:219: syntax error, unexpected \'@\'\n        @uart_tx_state;\n        ^\n%Error: Exiting due to 10 error(s), 3 warning(s)\n'
module uart_tfifo_v (clk, 
    wb_rst_i, data_in, data_out,
    push, 
    pop,   

    overrun,
    count,
    fifo_reset,
    reset_status
);


parameter fifo_width     = `V_UART_FIFO_WIDTH;
parameter fifo_depth     = `V_UART_FIFO_DEPTH;
parameter fifo_pointer_w = `V_UART_FIFO_POINTER_W;
parameter fifo_counter_w = `V_UART_FIFO_COUNTER_W;

input	clk;
input	wb_rst_i;
input	push;
input	pop;
input	[fifo_width-1:0]	data_in;
input	fifo_reset;
input   reset_status;

output	[fifo_width-1:0]	data_out;
output	overrun;
output	[fifo_counter_w-1:0]	count;

wire	[fifo_width-1:0]	data_out;

reg	[fifo_pointer_w-1:0]	top;
reg	[fifo_pointer_w-1:0]	bottom;

reg	[fifo_counter_w-1:0]	count;
reg			     overrun;
wire    [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;

raminfr_v #(fifo_pointer_w,fifo_width,fifo_depth) tfifo (.clk(clk), 
    .we(push), 
    .a(top), 
    .dpra(bottom), 
    .di(data_in), 
    .dpo(data_out)
); 


always @(posedge clk) 
begin
	if (wb_rst_i)
	begin
		top		<= 0;
		bottom		<= 1'b0;
		count		<= 0;
	end
	else
	if (fifo_reset) begin
		top		<= 0;
		bottom		<= 1'b0;
		count		<= 0;
	end
        else
	begin
		case ({push, pop})
		2'b10 : if (count<fifo_depth)  
			begin
				top       <= top_plus_1;
				count     <= count + 1'b1;
			end
		2'b01 : if(count>0)
			begin
				bottom    <= bottom + 1'b1;
				count	  <= count - 1'b1;
			end
		2'b11 : begin
				bottom    <= bottom + 1'b1;
				top       <= top_plus_1;
		        end
                default: ;
		endcase
	end
end   

always @(posedge clk) 
begin
  if (wb_rst_i)
    overrun   <= 1'b0;
  else
  if(fifo_reset | reset_status) 
    overrun   <= 1'b0;
  else
  if(push & (count==fifo_depth))
    overrun   <= 1'b1;
end   

endmodule
module uart_tfifo_v (clk, 
    wb_rst_i, data_in, data_out,
    push, 
    pop,   

    overrun,
    count,
    fifo_reset,
    reset_status
);



parameter fifo_width     = `V_UART_FIFO_WIDTH;
parameter fifo_depth     = `V_UART_FIFO_DEPTH;
parameter fifo_pointer_w = `V_UART_FIFO_POINTER_W;
parameter fifo_counter_w = `V_UART_FIFO_COUNTER_W;

input	clk;
input	wb_rst_i;
input	push;
input	pop;
input	[fifo_width-1:0]	data_in;
input	fifo_reset;
input   reset_status;

output	[fifo_width-1:0]	data_out;
output	overrun;
output	[fifo_counter_w-1:0]	count;

wire	[fifo_width-1:0]	data_out;

reg	[fifo_pointer_w-1:0]	top;
reg	[fifo_pointer_w-1:0]	bottom;

reg	[fifo_counter_w-1:0]	count;
reg			     overrun;
wire    [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;

raminfr_v #(fifo_pointer_w,fifo_width,fifo_depth) tfifo (.clk(clk), 
    .we(push), 
    .a(top), 
    .dpra(bottom), 
    .di(data_in), 
    .dpo(data_out)
); 


always @(posedge clk) 
begin
	if (wb_rst_i)
	begin
		top		<= 0;
		bottom		<= 1'b0;
		count		<= 0;
	end
	else
	if (fifo_reset) begin
		top		<= 0;
		bottom		<= 1'b0;
		count		<= 0;
	end
        else
	begin
		case ({push, pop})
		2'b10 : if (count<fifo_depth)  
			begin
				top       <= top_plus_1;
				count     <= count + 1'b1;
			end
		2'b01 : if(count>0)
			begin
				bottom    <= bottom + 1'b1;
				count	  <= count - 1'b1;
			end
		2'b11 : begin
				bottom    <= bottom + 1'b1;
				top       <= top_plus_1;
		        end
                default: ;
		endcase
	end
end   

always @(posedge clk) 
begin
  if (wb_rst_i)
    overrun   <= 1'b0;
  else
  if(fifo_reset | reset_status) 
    overrun   <= 1'b0;
  else
  if(push & (count==fifo_depth))
    overrun   <= 1'b1;
end   

endmodule