data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v
1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n             ^\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n              ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n                ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/214823094/lab_6/project_3/project_3.srcs/sources_1/new/digital_clock.v:66: Unsized numbers/parameters not allowed in replications.\n                                                                                                                          : ... In instance digital_clock\n        T4<={0,0,swt[13],swt[12]};\n                        ^\n%Error: Exiting due to 4 warning(s)\n'
module BCD_7_segment_display(
    input [3:0] swt,
    output reg [6:0] C
    );
    

    always@(swt)
    begin
    case(swt)
    4'b0000:C=7'b0000001;
    4'b0001:C=7'b1001111;
    4'b0010:C=7'b0010010;
    4'b0011:C=7'b0000110;
    4'b0100:C=7'b1001100;
    4'b0101:C=7'b0100100;
    4'b0110:C=7'b0100000;
    4'b0111:C=7'b0001111;
    4'b1000:C=7'b0000000;
    4'b1001:C=7'b0000100;
    default:C=7'b0000001;
    endcase
    end
    
endmodule
module BCD_7_segment_display(
    input [3:0] swt,
    output reg [6:0] C
    );

    

    always@(swt)
    begin
    case(swt)
    4'b0000:C=7'b0000001;
    4'b0001:C=7'b1001111;
    4'b0010:C=7'b0010010;
    4'b0011:C=7'b0000110;
    4'b0100:C=7'b1001100;
    4'b0101:C=7'b0100100;
    4'b0110:C=7'b0100000;
    4'b0111:C=7'b0001111;
    4'b1000:C=7'b0000000;
    4'b1001:C=7'b0000100;
    default:C=7'b0000001;
    endcase
    end
    
endmodule