data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v
 line:66: before: "integer"
1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v:44: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v:26: ... Location of original declaration\nmodule top_module (\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v:50: Duplicate declaration of module: \'top_module\'\nmodule top_module( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v:26: ... Location of original declaration\nmodule top_module (\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v:61: Duplicate declaration of module: \'top_module\'\nmodule top_module( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v:26: ... Location of original declaration\nmodule top_module (\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v:71: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v:26: ... Location of original declaration\nmodule top_module (\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v:84: Duplicate declaration of module: \'top_module\'\nmodule top_module( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v:26: ... Location of original declaration\nmodule top_module (\n       ^~~~~~~~~~\n%Warning-MULTITOP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/MoreFeature.v:98: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                                : ... Top module \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                                                                                                : ... Top module \'add1\'\nmodule add1 ( input a, input b, input cin,   output sum, output cout );\n       ^~~~\n%Error: Exiting due to 6 warning(s)\n'
module top_module (
    input [7:0] in,
    output parity); 
    assign parity = ^in[7:0];
endmodule
module top_module (
    input [7:0] in,
    output parity);
 
    assign parity = ^in[7:0];
endmodule