data/full_repos/permissive/204608363/65536_8 floatpoint/all_float/rtable.v
1: b'%Error: Cannot find file containing module: floatpoint/all_float,data/full_repos/permissive/204608363\n        ... Looked in:\n             data/full_repos/permissive/204608363/65536_8/floatpoint/all_float,data/full_repos/permissive/204608363\n             data/full_repos/permissive/204608363/65536_8/floatpoint/all_float,data/full_repos/permissive/204608363.v\n             data/full_repos/permissive/204608363/65536_8/floatpoint/all_float,data/full_repos/permissive/204608363.sv\n             floatpoint/all_float,data/full_repos/permissive/204608363\n             floatpoint/all_float,data/full_repos/permissive/204608363.v\n             floatpoint/all_float,data/full_repos/permissive/204608363.sv\n             obj_dir/floatpoint/all_float,data/full_repos/permissive/204608363\n             obj_dir/floatpoint/all_float,data/full_repos/permissive/204608363.v\n             obj_dir/floatpoint/all_float,data/full_repos/permissive/204608363.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/204608363/65536_8\n%Error: Cannot find file containing module: floatpoint/all_float/rtable.v\n%Error: Exiting due to 3 error(s)\n'
module rtable #(parameter ADDR_WIDTH = 19, DATA_WIDTH = 32, DEPTH = 524288) (
    input wire i_clk,
    input wire [ADDR_WIDTH-1:0] i_addr, 
    input wire i_read,
    output reg [DATA_WIDTH-1:0] o_data);

    always @ (posedge i_clk)
    begin
        casez (i_addr)

            19'b0000_0000_????_????_000: o_data<= -32'b11000111100000000000000000000000;
            19'b0000_0000_????_????_001: o_data<= -32'b11000111100000000000000000000000;
            19'b0000_0000_????_????_111: o_data<= -32'b11000111100000000000000000000000;


            19'b????_????_0000_0000_001: o_data<= -32'b11000111100000000000000000000000;
            19'b????_????_0000_0000_010: o_data<= -32'b11000111100000000000000000000000;
            19'b????_????_0000_0000_011: o_data<= -32'b11000111100000000000000000000000;

            19'b1111_1111_????_????_011: o_data<= -32'b11000111100000000000000000000000;
            19'b1111_1111_????_????_100: o_data<= -32'b11000111100000000000000000000000;
            19'b1111_1111_????_????_101: o_data<= -32'b11000111100000000000000000000000;

            19'b????_????_1111_1111_101: o_data<= -32'b11000111100000000000000000000000;
            19'b????_????_1111_1111_110: o_data<= -32'b11000111100000000000000000000000;
            19'b????_????_1111_1111_111: o_data<= -32'b11000111100000000000000000000000;


            19'b1111_1110_1111_1111_100: o_data<= 32'b01000111100000000000000000000000;
            19'b1111_1111_1111_1110_110: o_data<= 32'b01000111100000000000000000000000;
            19'b1111_1110_1111_1110_101: o_data<= 32'b01000111100000000000000000000000;


            
            default :  o_data<= {DATA_WIDTH{1'b0}};
        endcase    

    end
endmodule
module rtable #(parameter ADDR_WIDTH = 19, DATA_WIDTH = 32, DEPTH = 524288) (
    input wire i_clk,
    input wire [ADDR_WIDTH-1:0] i_addr, 
    input wire i_read,
    output reg [DATA_WIDTH-1:0] o_data);


    always @ (posedge i_clk)
    begin
        casez (i_addr)

            19'b0000_0000_????_????_000: o_data<= -32'b11000111100000000000000000000000;
            19'b0000_0000_????_????_001: o_data<= -32'b11000111100000000000000000000000;
            19'b0000_0000_????_????_111: o_data<= -32'b11000111100000000000000000000000;


            19'b????_????_0000_0000_001: o_data<= -32'b11000111100000000000000000000000;
            19'b????_????_0000_0000_010: o_data<= -32'b11000111100000000000000000000000;
            19'b????_????_0000_0000_011: o_data<= -32'b11000111100000000000000000000000;

            19'b1111_1111_????_????_011: o_data<= -32'b11000111100000000000000000000000;
            19'b1111_1111_????_????_100: o_data<= -32'b11000111100000000000000000000000;
            19'b1111_1111_????_????_101: o_data<= -32'b11000111100000000000000000000000;

            19'b????_????_1111_1111_101: o_data<= -32'b11000111100000000000000000000000;
            19'b????_????_1111_1111_110: o_data<= -32'b11000111100000000000000000000000;
            19'b????_????_1111_1111_111: o_data<= -32'b11000111100000000000000000000000;


            19'b1111_1110_1111_1111_100: o_data<= 32'b01000111100000000000000000000000;
            19'b1111_1111_1111_1110_110: o_data<= 32'b01000111100000000000000000000000;
            19'b1111_1110_1111_1110_101: o_data<= 32'b01000111100000000000000000000000;


            
            default :  o_data<= {DATA_WIDTH{1'b0}};
        endcase    

    end
endmodule