data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/cordic/cordic_rot.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/cordic/cordic_rot.v:34: Cannot find file containing module: \'cordic_factor_Kn_rom_ip\'\n    cordic_factor_Kn_rom_ip  Kn_rom_ip_core (.address(Kn_THETAn_address),.clock(sys_clk),.q({Kn, THETAn}));\n    ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/cordic,data/full_repos/permissive/143584361/cordic_factor_Kn_rom_ip\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/cordic,data/full_repos/permissive/143584361/cordic_factor_Kn_rom_ip.v\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/cordic,data/full_repos/permissive/143584361/cordic_factor_Kn_rom_ip.sv\n             cordic_factor_Kn_rom_ip\n             cordic_factor_Kn_rom_ip.v\n             cordic_factor_Kn_rom_ip.sv\n             obj_dir/cordic_factor_Kn_rom_ip\n             obj_dir/cordic_factor_Kn_rom_ip.v\n             obj_dir/cordic_factor_Kn_rom_ip.sv\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/cordic/cordic_rot.v:199: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 33 bits.\n                                                                                                         : ... In instance cordic_rot\n  rho <= rho_reg[2*DATA_WIDTH-1:DATA_WIDTH-1];\n      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module cordic_rot
#(parameter	DATA_WIDTH = 32,
  parameter	EPSILON = 3,
  parameter ITERATION = 8,
  parameter ROM_LATENCY = 2,
  parameter	DATA_ZERO = {DATA_WIDTH{1'B0}}
)
(
	input	wire	sys_clk, sys_rst_n,
	input	wire	[DATA_WIDTH-1:0]	src_x,
	input	wire	[DATA_WIDTH-1:0]	src_y,
	
	output	reg		[DATA_WIDTH-1:0]	rho,
    output  reg	    [DATA_WIDTH-1:0]    theta
);


	wire	[DATA_WIDTH-1:0]	Kn_THETAn_address;
	wire	[DATA_WIDTH-1:0]	Kn;
	wire	[DATA_WIDTH-1:0]	THETAn;
    cordic_factor_Kn_rom_ip 	Kn_rom_ip_core	(.address(Kn_THETAn_address),.clock(sys_clk),.q({Kn, THETAn}));

	


	reg		signed 	[DATA_WIDTH-1:0]	Xn	[0:ITERATION-1];
	reg		signed 	[DATA_WIDTH-1:0]	Yn	[0:ITERATION-1];
	reg									Sn	[0:ITERATION-1];

	reg				[DATA_WIDTH-1:0]	Nn	[0:ITERATION-1];	

	reg		signed 	[DATA_WIDTH-1:0]	Tn	[0:ITERATION-1];
	reg		signed 	[DATA_WIDTH-1:0]	T0n	[0:ITERATION-1];
	reg		signed 	[DATA_WIDTH-1:0]	K0n	[0:ITERATION-1];

	reg		[4:0]	cstate;
	parameter		IDLE = 0;
	parameter		LOAD = 1;
	parameter		COMP = 2;
	reg		[DATA_WIDTH-1:0]	timer_in_state;
	reg		[DATA_WIDTH-1:0]	rom_address;

	always @(posedge sys_clk)

		if(!sys_rst_n)
			init_system_task;

		else
		begin
			case(cstate)
				IDLE:		prepare_load_task;
				LOAD:		execute_load_task;
				COMP:		execute_comp_task;	
				default:	init_system_task;
			endcase
		end


integer	n;

task init_system_task;
begin
	cstate <= IDLE;

	for(n=0; n<ITERATION; n=n+1)
	begin
		Xn[n] <= DATA_ZERO;
		Yn[n] <= DATA_ZERO;
		Nn[n] <= DATA_ZERO;
		Tn[n] <= DATA_ZERO;
	end

	timer_in_state <= DATA_ZERO;

	rom_address <= 0;
end
endtask



task prepare_load_task;
begin	

	if(timer_in_state>=(ROM_LATENCY-1))
	begin
		cstate <= LOAD;

		timer_in_state <= DATA_ZERO;
	end

	else
	begin
		timer_in_state <= timer_in_state+1;
	end

	rom_address <= rom_address+1;
end
endtask

task execute_load_task;
begin	

	if(timer_in_state>=(ITERATION))
	begin
		cstate <= COMP;

		timer_in_state <= DATA_ZERO;
	end
	else
	begin

		T0n[timer_in_state] <= THETAn;
		K0n[timer_in_state] <= Kn;
		rom_address <= rom_address+1;
		timer_in_state <= timer_in_state+1;
	end
end
endtask

task execute_comp_task;
begin

	Xn[0] <= src_x[DATA_WIDTH-1]? (~src_x+1) : src_x;
	Sn[0] <= src_x[DATA_WIDTH-1];
	Yn[0] <= src_y;
	Nn[0] <= DATA_ZERO;
	Tn[0] <= DATA_ZERO;

	for(n=ITERATION-1; n>=1; n=n-1)
	begin

		if(Yn[n-1]>EPSILON)
		begin
			Xn[n] <= Xn[n-1] + (Yn[n-1]>>>(n-1));
			Yn[n] <= Yn[n-1] - (Xn[n-1]>>>(n-1));
			Nn[n] <= Nn[n-1] + 1;
			Tn[n] <= Tn[n-1] + T0n[n-1];
		end

		else if(Yn[n-1]<-EPSILON)
		begin
			Xn[n] <= Xn[n-1] - (Yn[n-1]>>>(n-1));
			Yn[n] <= Yn[n-1] + (Xn[n-1]>>>(n-1));
			Nn[n] <= Nn[n-1] + 1;
			Tn[n] <= Tn[n-1] - T0n[n-1];
		end

		else
		begin
			Xn[n] <= Xn[n-1];
			Yn[n] <= Yn[n-1];
			Nn[n] <= Nn[n-1];
			Tn[n] <= Tn[n-1];
		end

		Sn[n] <= Sn[n-1];
	end
end
endtask


	assign	Kn_THETAn_address = rom_address;



	reg		[2*DATA_WIDTH-1:0]	rho_reg;
	reg		[DATA_WIDTH-1:0]	theta_reg;
	always @(posedge sys_clk)
	begin
		if(Nn[ITERATION-1]==0)
			rho_reg <= {Xn[ITERATION-1], DATA_ZERO} >>> 1;
		else
			rho_reg <= Xn[ITERATION-1]*K0n[Nn[ITERATION-1]-1];
		

		if(Sn[ITERATION-1]==0)
			theta_reg <= Tn[ITERATION-1];
		else
		begin
			if(Tn[ITERATION-1][DATA_WIDTH-1])
				theta_reg <= {1'B1, {(DATA_WIDTH-1){1'B0}}} - Tn[ITERATION-1];
			else
				theta_reg <= {1'B0, {(DATA_WIDTH-1){1'B1}}} - Tn[ITERATION-1];
		end

		rho <= rho_reg[2*DATA_WIDTH-1:DATA_WIDTH-1];
		theta <= theta_reg;
	end
	
endmodule
module cordic_rot
#(parameter	DATA_WIDTH = 32,
  parameter	EPSILON = 3,
  parameter ITERATION = 8,
  parameter ROM_LATENCY = 2,
  parameter	DATA_ZERO = {DATA_WIDTH{1'B0}}
)
(
	input	wire	sys_clk, sys_rst_n,
	input	wire	[DATA_WIDTH-1:0]	src_x,
	input	wire	[DATA_WIDTH-1:0]	src_y,
	
	output	reg		[DATA_WIDTH-1:0]	rho,
    output  reg	    [DATA_WIDTH-1:0]    theta
);



	wire	[DATA_WIDTH-1:0]	Kn_THETAn_address;
	wire	[DATA_WIDTH-1:0]	Kn;
	wire	[DATA_WIDTH-1:0]	THETAn;
    cordic_factor_Kn_rom_ip 	Kn_rom_ip_core	(.address(Kn_THETAn_address),.clock(sys_clk),.q({Kn, THETAn}));

	


	reg		signed 	[DATA_WIDTH-1:0]	Xn	[0:ITERATION-1];
	reg		signed 	[DATA_WIDTH-1:0]	Yn	[0:ITERATION-1];
	reg									Sn	[0:ITERATION-1];

	reg				[DATA_WIDTH-1:0]	Nn	[0:ITERATION-1];	

	reg		signed 	[DATA_WIDTH-1:0]	Tn	[0:ITERATION-1];
	reg		signed 	[DATA_WIDTH-1:0]	T0n	[0:ITERATION-1];
	reg		signed 	[DATA_WIDTH-1:0]	K0n	[0:ITERATION-1];

	reg		[4:0]	cstate;
	parameter		IDLE = 0;
	parameter		LOAD = 1;
	parameter		COMP = 2;
	reg		[DATA_WIDTH-1:0]	timer_in_state;
	reg		[DATA_WIDTH-1:0]	rom_address;

	always @(posedge sys_clk)

		if(!sys_rst_n)
			init_system_task;

		else
		begin
			case(cstate)
				IDLE:		prepare_load_task;
				LOAD:		execute_load_task;
				COMP:		execute_comp_task;	
				default:	init_system_task;
			endcase
		end


integer	n;

task init_system_task;
begin
	cstate <= IDLE;

	for(n=0; n<ITERATION; n=n+1)
	begin
		Xn[n] <= DATA_ZERO;
		Yn[n] <= DATA_ZERO;
		Nn[n] <= DATA_ZERO;
		Tn[n] <= DATA_ZERO;
	end

	timer_in_state <= DATA_ZERO;

	rom_address <= 0;
end
endtask



task prepare_load_task;
begin	

	if(timer_in_state>=(ROM_LATENCY-1))
	begin
		cstate <= LOAD;

		timer_in_state <= DATA_ZERO;
	end

	else
	begin
		timer_in_state <= timer_in_state+1;
	end

	rom_address <= rom_address+1;
end
endtask

task execute_load_task;
begin	

	if(timer_in_state>=(ITERATION))
	begin
		cstate <= COMP;

		timer_in_state <= DATA_ZERO;
	end
	else
	begin

		T0n[timer_in_state] <= THETAn;
		K0n[timer_in_state] <= Kn;
		rom_address <= rom_address+1;
		timer_in_state <= timer_in_state+1;
	end
end
endtask

task execute_comp_task;
begin

	Xn[0] <= src_x[DATA_WIDTH-1]? (~src_x+1) : src_x;
	Sn[0] <= src_x[DATA_WIDTH-1];
	Yn[0] <= src_y;
	Nn[0] <= DATA_ZERO;
	Tn[0] <= DATA_ZERO;

	for(n=ITERATION-1; n>=1; n=n-1)
	begin

		if(Yn[n-1]>EPSILON)
		begin
			Xn[n] <= Xn[n-1] + (Yn[n-1]>>>(n-1));
			Yn[n] <= Yn[n-1] - (Xn[n-1]>>>(n-1));
			Nn[n] <= Nn[n-1] + 1;
			Tn[n] <= Tn[n-1] + T0n[n-1];
		end

		else if(Yn[n-1]<-EPSILON)
		begin
			Xn[n] <= Xn[n-1] - (Yn[n-1]>>>(n-1));
			Yn[n] <= Yn[n-1] + (Xn[n-1]>>>(n-1));
			Nn[n] <= Nn[n-1] + 1;
			Tn[n] <= Tn[n-1] - T0n[n-1];
		end

		else
		begin
			Xn[n] <= Xn[n-1];
			Yn[n] <= Yn[n-1];
			Nn[n] <= Nn[n-1];
			Tn[n] <= Tn[n-1];
		end

		Sn[n] <= Sn[n-1];
	end
end
endtask


	assign	Kn_THETAn_address = rom_address;



	reg		[2*DATA_WIDTH-1:0]	rho_reg;
	reg		[DATA_WIDTH-1:0]	theta_reg;
	always @(posedge sys_clk)
	begin
		if(Nn[ITERATION-1]==0)
			rho_reg <= {Xn[ITERATION-1], DATA_ZERO} >>> 1;
		else
			rho_reg <= Xn[ITERATION-1]*K0n[Nn[ITERATION-1]-1];
		

		if(Sn[ITERATION-1]==0)
			theta_reg <= Tn[ITERATION-1];
		else
		begin
			if(Tn[ITERATION-1][DATA_WIDTH-1])
				theta_reg <= {1'B1, {(DATA_WIDTH-1){1'B0}}} - Tn[ITERATION-1];
			else
				theta_reg <= {1'B0, {(DATA_WIDTH-1){1'B1}}} - Tn[ITERATION-1];
		end

		rho <= rho_reg[2*DATA_WIDTH-1:DATA_WIDTH-1];
		theta <= theta_reg;
	end
	
endmodule