data/full_repos/permissive/159891569/noiseChannel.v
1: b"%Error: data/full_repos/permissive/159891569/noiseChannel.v:29: Cannot find file containing module: 'lenCounter'\n lenCounter lc(clk256, lenLoad, trigger, lenEnable, chanEnable);\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/lenCounter\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/lenCounter.v\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/lenCounter.sv\n             lenCounter\n             lenCounter.v\n             lenCounter.sv\n             obj_dir/lenCounter\n             obj_dir/lenCounter.v\n             obj_dir/lenCounter.sv\n%Error: data/full_repos/permissive/159891569/noiseChannel.v:32: Cannot find file containing module: 'varTimer'\n varTimer #(7) tmr(clk, period, srClk);\n ^~~~~~~~\n%Error: data/full_repos/permissive/159891569/noiseChannel.v:40: Cannot find file containing module: 'volumizer'\n volumizer vol(clk64, envAdd, trigger, envPeriod, startVol, volume);\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module noiseChannel(
	input clk, clk256, clk64,
	input [5:0] lenLoad, 
	input [3:0] startVol,
	input envAdd, 
	input [2:0] envPeriod,
	input [3:0] clkShift,
	input widthMode,
	input [2:0] divisor,
	input trigger, lenEnable,
	output [3:0] noise
);
	
	wire chanEnable, srClk;
	wire [6:0] period;
	reg [14:0] sr;
	
	lenCounter lc(clk256, lenLoad, trigger, lenEnable, chanEnable);

	assign period = divisor == 0 ? 7'd8 : (16 * divisor);
	varTimer #(7) tmr(clk, period, srClk);

	initial sr = 15'b1;
	always @(posedge srClk) begin
		sr <= widthMode ? {(sr[1]^sr[0]), sr[14:8], (sr[1]^sr[0]), sr[6:1]} : {(sr[1]^sr[0]), sr[14:1]};
	end

	wire [3:0] volume;
	volumizer vol(clk64, envAdd, trigger, envPeriod, startVol, volume);
	assign noise = (chanEnable && !sr[0]) ? volume : 0;

endmodule
module noiseChannel(
	input clk, clk256, clk64,
	input [5:0] lenLoad, 
	input [3:0] startVol,
	input envAdd, 
	input [2:0] envPeriod,
	input [3:0] clkShift,
	input widthMode,
	input [2:0] divisor,
	input trigger, lenEnable,
	output [3:0] noise
);

	
	wire chanEnable, srClk;
	wire [6:0] period;
	reg [14:0] sr;
	
	lenCounter lc(clk256, lenLoad, trigger, lenEnable, chanEnable);

	assign period = divisor == 0 ? 7'd8 : (16 * divisor);
	varTimer #(7) tmr(clk, period, srClk);

	initial sr = 15'b1;
	always @(posedge srClk) begin
		sr <= widthMode ? {(sr[1]^sr[0]), sr[14:8], (sr[1]^sr[0]), sr[6:1]} : {(sr[1]^sr[0]), sr[14:1]};
	end

	wire [3:0] volume;
	volumizer vol(clk64, envAdd, trigger, envPeriod, startVol, volume);
	assign noise = (chanEnable && !sr[0]) ? volume : 0;

endmodule