data/full_repos/permissive/178601407/common-modules/timer.sv
Syntax Error
data/verilator_xmls/e31de788-e936-43f8-b17c-c4e16adcee7a.xml
module timer(input logic clk, clk1kHz, enable, input logic [9:0] delayInMs, output logic timeout);
initial timeout = 0;
logic [9:0] counter = 0;
logic loaded = 0;

always_ff @(posedge clk)

	if (enable && loaded) begin
		if (counter == 0 && timeout == 1'b0)
			timeout <= 1'b1;
		else if (counter == 0 && timeout == 1'b0)
			timeout <= 1'b0;
		else
			counter--;
	end

	else if (enable && ~loaded) begin
		counter <= delayInMs;
		loaded <= 1'b1;
	end
endmodule
module timer(input logic clk, clk1kHz, enable, input logic [9:0] delayInMs, output logic timeout);

initial timeout = 0;
logic [9:0] counter = 0;
logic loaded = 0;

always_ff @(posedge clk)

	if (enable && loaded) begin
		if (counter == 0 && timeout == 1'b0)
			timeout <= 1'b1;
		else if (counter == 0 && timeout == 1'b0)
			timeout <= 1'b0;
		else
			counter--;
	end

	else if (enable && ~loaded) begin
		counter <= delayInMs;
		loaded <= 1'b1;
	end
endmodule