data/full_repos/permissive/190426879/pipelined_cpu/source/pipepc.v
data/verilator_xmls/aac6b9bc-9144-470f-b44e-c2928feec7de.xml
module pipepc (	npc, wpcir, clock, resetn, pc ); 
	input wire[31:0] npc;
	input wpcir;
	input clock,resetn;
	output reg[31:0] pc;
	
	always @ (posedge clock)
	begin 
		if (~resetn)
		begin
			pc <= 0;
		end
		else
		begin
			if (wpcir)
			begin
				pc <= npc;
			end
		end
	end
endmodule
module pipepc (	npc, wpcir, clock, resetn, pc );
 
	input wire[31:0] npc;
	input wpcir;
	input clock,resetn;
	output reg[31:0] pc;
	
	always @ (posedge clock)
	begin 
		if (~resetn)
		begin
			pc <= 0;
		end
		else
		begin
			if (wpcir)
			begin
				pc <= npc;
			end
		end
	end
endmodule