data/full_repos/permissive/143278/ivltests/signed_equality.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_equality.v:2: Operator EQCASE expects 6 bits on the RHS, but RHS\'s CONST \'4\'sh8\' generates 4 bits.\n                                                                              : ... In instance top\n  parameter seeq1 = 6\'sb111000 === 4\'sb1000;\n                               ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_equality.v:3: Operator EQCASE expects 6 bits on the RHS, but RHS\'s CONST \'4\'sbx000\' generates 4 bits.\n                                                                              : ... In instance top\n  parameter seeqx = 6\'sbxxx000 === 4\'sbx000;\n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_equality.v:4: Operator EQCASE expects 6 bits on the RHS, but RHS\'s CONST \'4\'sbz000\' generates 4 bits.\n                                                                              : ... In instance top\n  parameter seeqz = 6\'sbzzz000 === 4\'sbz000;\n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_equality.v:5: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'4\'sh8\' generates 4 bits.\n                                                                              : ... In instance top\n  parameter seq1 = 6\'sb111000 == 4\'sb1000;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_equality.v:6: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'4\'sbx000\' generates 4 bits.\n                                                                              : ... In instance top\n  parameter seqx = 6\'sbxxx000 == 4\'sbx000;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed_equality.v:7: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'4\'sbz000\' generates 4 bits.\n                                                                              : ... In instance top\n  parameter seqz = 6\'sbzzz000 == 4\'sbz000;\n                              ^~\n%Error: Exiting due to 6 warning(s)\n'
module top;
  parameter seeq1 = 6'sb111000 === 4'sb1000;
  parameter seeqx = 6'sbxxx000 === 4'sbx000;
  parameter seeqz = 6'sbzzz000 === 4'sbz000;
  parameter seq1 = 6'sb111000 == 4'sb1000;
  parameter seqx = 6'sbxxx000 == 4'sbx000;
  parameter seqz = 6'sbzzz000 == 4'sbz000;
  reg pass;

  initial begin
    pass = 1'b1;

    if (seeq1 !== 1'b1) begin
      $display("FAILED: signed === (1), got %b", seeq1);
      pass = 1'b0;
    end

    if (seeqx !== 1'b1) begin
      $display("FAILED: signed === (x), got %b", seeqx);
      pass = 1'b0;
    end

    if (seeqz !== 1'b1) begin
      $display("FAILED: signed === (z), got %b", seeqz);
      pass = 1'b0;
    end

    if (seq1 !== 1'b1) begin
      $display("FAILED: signed == (1), got %b", seq1);
      pass = 1'b0;
    end

    if (seqx !== 1'bx) begin
      $display("FAILED: signed == (x), got %b", seqx);
      pass = 1'b0;
    end

    if (seqz !== 1'bx) begin
      $display("FAILED: signed == (z), got %b", seqz);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  parameter seeq1 = 6'sb111000 === 4'sb1000;
  parameter seeqx = 6'sbxxx000 === 4'sbx000;
  parameter seeqz = 6'sbzzz000 === 4'sbz000;
  parameter seq1 = 6'sb111000 == 4'sb1000;
  parameter seqx = 6'sbxxx000 == 4'sbx000;
  parameter seqz = 6'sbzzz000 == 4'sbz000;
  reg pass;

  initial begin
    pass = 1'b1;

    if (seeq1 !== 1'b1) begin
      $display("FAILED: signed === (1), got %b", seeq1);
      pass = 1'b0;
    end

    if (seeqx !== 1'b1) begin
      $display("FAILED: signed === (x), got %b", seeqx);
      pass = 1'b0;
    end

    if (seeqz !== 1'b1) begin
      $display("FAILED: signed === (z), got %b", seeqz);
      pass = 1'b0;
    end

    if (seq1 !== 1'b1) begin
      $display("FAILED: signed == (1), got %b", seq1);
      pass = 1'b0;
    end

    if (seqx !== 1'bx) begin
      $display("FAILED: signed == (x), got %b", seqx);
      pass = 1'b0;
    end

    if (seqz !== 1'bx) begin
      $display("FAILED: signed == (z), got %b", seqz);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule