data/full_repos/permissive/188434311/verilog/register_slice/backward_register_slice.v
None: at end of input
data/verilator_xmls/29b94862-bb58-43c1-adda-3ce0b8c78bfb.xml
module backward_register_slice #(parameter BITWIDTH = 8)
(
input  wire                         clki,
input  wire                         rst_n,

input  wire                         RxVld,
input  wire  [ BITWIDTH - 1 : 0 ]   RxData,
output wire                         RxRdy,

output wire                         TxVld,
output wire  [ BITWIDTH - 1 : 0 ]   TxData,
input  wire                         TxRdy
);

reg [ BITWIDTH - 1 : 0 ] RxData_r  ;
wire                     RxData_en ;
reg                      Full      ;

assign TxVld = ( Full | RxVld & RxRdy ) ;
assign RxRdy = ~ Full ;

always @( posedge clki or negedge rst_n )
  if( ! rst_n )
    Full <= #0.001 (1'b0) ;
  else Full <= #0.001 ( TxVld & ~ TxRdy );


assign TxData = Full ? RxData_r : RxData ;
assign RxData_en = RxVld & RxRdy ;
always @( posedge clki )
  if( RxData_en )
    RxData_r <= #0.01 ( RxData ) ;

endmodule
module backward_register_slice #(parameter BITWIDTH = 8)
(
input  wire                         clki,
input  wire                         rst_n,

input  wire                         RxVld,
input  wire  [ BITWIDTH - 1 : 0 ]   RxData,
output wire                         RxRdy,

output wire                         TxVld,
output wire  [ BITWIDTH - 1 : 0 ]   TxData,
input  wire                         TxRdy
);


reg [ BITWIDTH - 1 : 0 ] RxData_r  ;
wire                     RxData_en ;
reg                      Full      ;

assign TxVld = ( Full | RxVld & RxRdy ) ;
assign RxRdy = ~ Full ;

always @( posedge clki or negedge rst_n )
  if( ! rst_n )
    Full <= #0.001 (1'b0) ;
  else Full <= #0.001 ( TxVld & ~ TxRdy );


assign TxData = Full ? RxData_r : RxData ;
assign RxData_en = RxVld & RxRdy ;
always @( posedge clki )
  if( RxData_en )
    RxData_r <= #0.01 ( RxData ) ;

endmodule