data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v
 line:139: before: "?"
1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:13: Cannot find include file: ahb_lite.vh\n`include "ahb_lite.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.v\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.sv\n             ahb_lite.vh\n             ahb_lite.vh.v\n             ahb_lite.vh.sv\n             obj_dir/ahb_lite.vh\n             obj_dir/ahb_lite.vh.v\n             obj_dir/ahb_lite.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:119: Define or directive not defined: \'`SM_MEM_SCRATCHPAD\'\n    assign sel = `SM_MEM_SCRATCHPAD ? SEL_SCR : SEL_AHB;\n                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:119: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n    assign sel = `SM_MEM_SCRATCHPAD ? SEL_SCR : SEL_AHB;\n                                    ^\n%Error: Exiting due to 3 error(s)\n'
module sm_matrix
#(
    parameter SIZE = 64
)
(
    input             clk,
    input             rst_n,

    input      [31:0] a,
    input             we,
    input      [31:0] wd,
    input             valid,
    output            ready,
    output     [31:0] rd,

    output            HCLK,
    output            HRESETn,
    output            HWRITE,
    output     [ 1:0] HTRANS,
    output     [31:0] HADDR,
    input      [31:0] HRDATA,
    output     [31:0] HWDATA,
    input             HREADY,
    input             HRESP       
);

    wire [ 1:0] sel;
    wire [ 1:0] sel_r;
    wire [ 1:0] sel_a;
    assign sel = valid ? sel_a : 2'b0;
    
    wire [ 1:0] readyout;
    wire [31:0] rdata;
    wire [31:0] rdata0;
    wire [31:0] rdata1;
    

    sm_ram_outbuf scratchpad_ram
    (
        .clk    ( clk            ),
        .rst_n  ( rst_n          ),
        .a      ( a              ),    
        .we     ( we             ),   
        .wd     ( wd             ),   
        .valid  ( sel        [0] ),
        .ready  ( readyout   [0] ),
        .rd     ( rdata0         )
    );


    sm_ahb_master ahb_master
    (
        .clk      ( clk         ),
        .rst_n    ( rst_n       ),
   
        .a        ( a           ),        
        .we       ( we          ),       
        .wd       ( wd          ),       
        .valid    ( sel     [1] ),    
        .ready    ( readyout[1] ),    
        .rd       ( rdata1      ),       

        .HCLK     ( HCLK        ),
        .HRESETn  ( HRESETn     ),
        .HWRITE   ( HWRITE      ),
        .HTRANS   ( HTRANS      ),
        .HADDR    ( HADDR       ),
        .HRDATA   ( HRDATA      ),
        .HWDATA   ( HWDATA      ),
        .HREADY   ( HREADY      ),
        .HRESP    ( HRESP       )          
    );



    sm_matrix_decoder decoder ( a, sel_a);


    sm_register_we #(2) r_sel ( clk, rst_n, ready, sel, sel_r );


    sm_response_mux response_mux
    (
        .sel      ( sel_r    ),
        .rdata0   ( rdata0   ),
        .rdata1   ( rdata1   ),
        .readyout ( readyout ),
        .rdata    ( rd       ),
        .ready    ( ready    )
    );

endmodule
module sm_matrix
#(
    parameter SIZE = 64
)
(
    input             clk,
    input             rst_n,

    input      [31:0] a,
    input             we,
    input      [31:0] wd,
    input             valid,
    output            ready,
    output     [31:0] rd,

    output            HCLK,
    output            HRESETn,
    output            HWRITE,
    output     [ 1:0] HTRANS,
    output     [31:0] HADDR,
    input      [31:0] HRDATA,
    output     [31:0] HWDATA,
    input             HREADY,
    input             HRESP       
);


    wire [ 1:0] sel;
    wire [ 1:0] sel_r;
    wire [ 1:0] sel_a;
    assign sel = valid ? sel_a : 2'b0;
    
    wire [ 1:0] readyout;
    wire [31:0] rdata;
    wire [31:0] rdata0;
    wire [31:0] rdata1;
    

    sm_ram_outbuf scratchpad_ram
    (
        .clk    ( clk            ),
        .rst_n  ( rst_n          ),
        .a      ( a              ),    
        .we     ( we             ),   
        .wd     ( wd             ),   
        .valid  ( sel        [0] ),
        .ready  ( readyout   [0] ),
        .rd     ( rdata0         )
    );


    sm_ahb_master ahb_master
    (
        .clk      ( clk         ),
        .rst_n    ( rst_n       ),
   
        .a        ( a           ),        
        .we       ( we          ),       
        .wd       ( wd          ),       
        .valid    ( sel     [1] ),    
        .ready    ( readyout[1] ),    
        .rd       ( rdata1      ),       

        .HCLK     ( HCLK        ),
        .HRESETn  ( HRESETn     ),
        .HWRITE   ( HWRITE      ),
        .HTRANS   ( HTRANS      ),
        .HADDR    ( HADDR       ),
        .HRDATA   ( HRDATA      ),
        .HWDATA   ( HWDATA      ),
        .HREADY   ( HREADY      ),
        .HRESP    ( HRESP       )          
    );



    sm_matrix_decoder decoder ( a, sel_a);


    sm_register_we #(2) r_sel ( clk, rst_n, ready, sel, sel_r );


    sm_response_mux response_mux
    (
        .sel      ( sel_r    ),
        .rdata0   ( rdata0   ),
        .rdata1   ( rdata1   ),
        .readyout ( readyout ),
        .rdata    ( rd       ),
        .ready    ( ready    )
    );

endmodule