data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/sum_pipe.v
1: b'%Warning-WIDTH: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/sum_pipe.v:34: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                        : ... In instance sum_pipe\n        sum10 = dataA[1:0] + dataB[1:0];\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/sum_pipe.v:34: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                        : ... In instance sum_pipe\n        sum10 = dataA[1:0] + dataB[1:0];\n                           ^\n%Error: Exiting due to 2 warning(s)\n'
module sum_pipe(
                input               clk,
                input               reset_L,
                input       [3:0]   dataA,
                input       [3:0]   dataB,
                output reg  [3:0]   sum30_dd 
                );


    reg [3:0] sum10, sum10_d, sum30_d;
    reg [3:0] data_A_d, data_B_d;
    reg acarreo, acarreo_d;


    reg data_out;

    always@(*) begin
        if (!reset_L)begin
            acarreo = 'b0;
            sum30_d = 'b0;
            sum10   = 'b0; 
        end      

        sum10 = dataA[1:0] + dataB[1:0];
        

        acarreo = sum10[2];
        sum30_d[3:2] = data_A_d[3:2] + data_B_d[3:2] + acarreo_d;
        sum30_d[1:0] = sum10_d[1:0];
    end

    
    
    always@( posedge clk )begin
        if (!reset_L)begin
            acarreo_d   <= 'b0;
            sum10_d     <= 'b0;
            data_A_d    <= 'b0;
            data_B_d    <= 'b0;
            sum30_dd    <= 'b0;
        end
        else begin
            data_out    <= 1;

            data_A_d    <= dataA;          
            data_B_d    <= dataB;
            sum10_d     <= sum10;
            acarreo_d   <= acarreo;
        

        	sum30_dd <= sum30_d;
        end
    end
endmodule
module sum_pipe(
                input               clk,
                input               reset_L,
                input       [3:0]   dataA,
                input       [3:0]   dataB,
                output reg  [3:0]   sum30_dd 
                );



    reg [3:0] sum10, sum10_d, sum30_d;
    reg [3:0] data_A_d, data_B_d;
    reg acarreo, acarreo_d;


    reg data_out;

    always@(*) begin
        if (!reset_L)begin
            acarreo = 'b0;
            sum30_d = 'b0;
            sum10   = 'b0; 
        end      

        sum10 = dataA[1:0] + dataB[1:0];
        

        acarreo = sum10[2];
        sum30_d[3:2] = data_A_d[3:2] + data_B_d[3:2] + acarreo_d;
        sum30_d[1:0] = sum10_d[1:0];
    end

    
    
    always@( posedge clk )begin
        if (!reset_L)begin
            acarreo_d   <= 'b0;
            sum10_d     <= 'b0;
            data_A_d    <= 'b0;
            data_B_d    <= 'b0;
            sum30_dd    <= 'b0;
        end
        else begin
            data_out    <= 1;

            data_A_d    <= dataA;          
            data_B_d    <= dataB;
            sum10_d     <= sum10;
            acarreo_d   <= acarreo;
        

        	sum30_dd <= sum30_d;
        end
    end
endmodule