data/full_repos/permissive/143278/ivltests/pr1676071.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1676071.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module add1(a, b, ci, sum, co);
	input a, b, ci;
	output sum, co;
	assign {co,sum} = a + b + ci;
endmodule
module add1(a, b, ci, sum, co);

	input a, b, ci;
	output sum, co;
	assign {co,sum} = a + b + ci;
endmodule