data/full_repos/permissive/159001439/src/clock_detect.v
data/verilator_xmls/95085011-2395-44cb-aa1b-9315c2e77329.xml
module clock_detect(
    input clk,
    input detect_clock,
    output reg active
);

reg [15:0] cnt;
always @(posedge detect_clock)
begin
    cnt <= cnt+1;
end

reg [7:0] tmr;
reg [15:0] prev;
always @(posedge clk)
begin
    if(tmr==0) begin
        if(prev==cnt)
            active <= 1'b0;
        else
            active <= 1'b1;
    end
    tmr <= tmr+1;
end

endmodule
module clock_detect(
    input clk,
    input detect_clock,
    output reg active
);


reg [15:0] cnt;
always @(posedge detect_clock)
begin
    cnt <= cnt+1;
end

reg [7:0] tmr;
reg [15:0] prev;
always @(posedge clk)
begin
    if(tmr==0) begin
        if(prev==cnt)
            active <= 1'b0;
        else
            active <= 1'b1;
    end
    tmr <= tmr+1;
end

endmodule