data/full_repos/permissive/147086086/Lab4/hw/dec_7seg_rtl/dec_7seg_tb.v
 line:14: before: "i"
1: b'%Warning-STMTDLY: data/full_repos/permissive/147086086/Lab4/hw/dec_7seg_rtl/dec_7seg_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #DELAY;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147086086/Lab4/hw/dec_7seg_rtl/dec_7seg_tb.v:10: Cannot find file containing module: \'dec_7seg\'\ndec_7seg    dec_7seg_inst(.i_dat (bin_code), \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147086086/Lab4/hw/dec_7seg_rtl,data/full_repos/permissive/147086086/dec_7seg\n             data/full_repos/permissive/147086086/Lab4/hw/dec_7seg_rtl,data/full_repos/permissive/147086086/dec_7seg.v\n             data/full_repos/permissive/147086086/Lab4/hw/dec_7seg_rtl,data/full_repos/permissive/147086086/dec_7seg.sv\n             dec_7seg\n             dec_7seg.v\n             dec_7seg.sv\n             obj_dir/dec_7seg\n             obj_dir/dec_7seg.v\n             obj_dir/dec_7seg.sv\n%Warning-WIDTH: data/full_repos/permissive/147086086/Lab4/hw/dec_7seg_rtl/dec_7seg_tb.v:19: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                          : ... In instance dec_7seg_tb\n        bin_code = i;\n                 ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dec_7seg_tb;

parameter DELAY = 20;

reg     [3:0]   bin_code;
wire    [6:0]   segments;

dec_7seg    dec_7seg_inst(.i_dat (bin_code), 
                          .o_seg (segments)
                          );

integer unsigned i;

initial begin

    for (i = 0; i < 16; i = i + 1) begin
        bin_code = i;
        #DELAY;
    end

    $finish;

end

endmodule
module dec_7seg_tb;


parameter DELAY = 20;

reg     [3:0]   bin_code;
wire    [6:0]   segments;

dec_7seg    dec_7seg_inst(.i_dat (bin_code), 
                          .o_seg (segments)
                          );

integer unsigned i;

initial begin

    for (i = 0; i < 16; i = i + 1) begin
        bin_code = i;
        #DELAY;
    end

    $finish;

end

endmodule