data/full_repos/permissive/147974511/uvm/aes_driver.sv
 line:1: before: "class"
1: b"%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:1: Unsupported: classes\nclass aes_driver extends uvm_driver#(aes_transaction);\n^~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:1: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass aes_driver extends uvm_driver#(aes_transaction);\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:2: Define or directive not defined: '`uvm_component_utils'\n `uvm_component_utils(aes_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:4: Unsupported: virtual data type\n virtual aes_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:6: Unsupported: new constructor\n function new(string name, uvm_component parent);\n          ^~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:6: syntax error, unexpected IDENTIFIER, expecting ')'\n function new(string name, uvm_component parent);\n                                         ^~~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:10: syntax error, unexpected IDENTIFIER, expecting ')'\n function void build_phase(uvm_phase phase);\n                                     ^~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:13: Unsupported: virtual data type\n  void'(uvm_resource_db#(virtual aes_if)::read_by_name\n                         ^~~~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:17: syntax error, unexpected IDENTIFIER, expecting ')'\n task run_phase(uvm_phase phase);\n                          ^~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:22: syntax error, unexpected IDENTIFIER\n  aes_transaction aes_tx;\n                  ^~~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:40: syntax error, unexpected '@'\n   @(posedge vif.sig_clock)\n   ^\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:51: syntax error, unexpected ':'\n     1: begin \n      ^\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:60: syntax error, unexpected end\n     end\n     ^~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:68: syntax error, unexpected end\n     end\n     ^~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:75: syntax error, unexpected end\n       end else if( vif.sig_rst == 1 | vif.sig_enable == 0) FSMstate = 5;\n       ^~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:84: syntax error, unexpected end\n       end \n       ^~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_driver.sv:90: syntax error, unexpected end\n     end\n     ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n"
function void build_phase(uvm_phase phase);
		super.build_phase(phase);

		void'(uvm_resource_db#(virtual aes_if)::read_by_name
			(.scope("ifs"), .name("aes_if"), .val(vif)));
	endfunction
function void build_phase(uvm_phase phase);

		super.build_phase(phase);

		void'(uvm_resource_db#(virtual aes_if)::read_by_name
			(.scope("ifs"), .name("aes_if"), .val(vif)));
	endfunction