data/full_repos/permissive/106029354/verilog_source/pipeline3.v
1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline3.v:21: Cannot find include file: params_proc.v\n`include "params_proc.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n             params_proc.v\n             params_proc.v.v\n             params_proc.v.sv\n             obj_dir/params_proc.v\n             obj_dir/params_proc.v.v\n             obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n'
module pipeline3(
	clk_in,
	RST,
    ctrl_in,
	pc_in,
	A_addr,
    B_addr,
	A,
	B,
	imm,
	pc_chg,
	pc_out,
    mem_we,
    data,
    addr,
    reg_addr,
    ctrl_out
);


`include "params_proc.v"


input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input [PC_WIDTH-1:0] pc_in;
input [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
input signed [DATA_WIDTH-1:0] A, B, imm;

output reg pc_chg;
output reg [PC_WIDTH-1:0] pc_out;
output reg mem_we;
output reg signed [DATA_WIDTH-1:0] data;
output reg [MEM_WIDTH-1:0] addr;
output reg [REG_ADDR_WIDTH-1:0] reg_addr;
output reg [CTRL_WIDTH-1:0] ctrl_out;


reg [RFLAGS_WIDTH-1:0] rflags_last;
wire signed [DATA_WIDTH-1:0] B_imm;




reg ula_to_data;
reg signed [DATA_WIDTH-1:0] data_default;
reg [MEM_WIDTH-1:0] addr_default;


reg signed [DATA_WIDTH-1:0] ula_data1, ula_data2;
reg [OPCODE_WIDTH-1:0] ula_opcode;
wire signed [DATA_WIDTH-1:0] ula_out;
wire [RFLAGS_WIDTH-1:0] rflags;


ula ula0(.opcode(ula_opcode),
	.data1(ula_data1), .data2(ula_data2),
	.out(ula_out), .rflags(rflags));


always @(negedge clk_in) begin
	if (!RST) begin
		rflags_last  <= 0;
	end else begin
		rflags_last <= rflags;
	end
end


always @(posedge clk_in) begin
    if (!RST) begin
        ctrl_out    <= NOP;
    end else begin
        ctrl_out    <= ctrl_in;
    end
end


always @(posedge clk_in) begin
	if (!RST) begin

		pc_out         <= PC_INITIAL + 1;
		reg_addr       <= 0;
		pc_chg 	       <= 0;

		ula_to_data    <= 0;
		data_default   <= 0;
		addr_default   <= 0;
		ula_opcode     <= NOP;
		ula_data1      <= 0;
		ula_data2      <= 0;
        mem_we         <= 0;
	end	else begin
        pc_out      <= pc_in;
        reg_addr    <= A_addr;
        pc_chg      <= 0;

        ula_to_data    <= 1;
        data_default   <= 0;
        addr_default   <= 0;
        ula_opcode     <= NOP;
        ula_data1      <= 0;
        ula_data2      <= 0;
        mem_we         <= 0;
		case(ctrl_in)
		LW: begin


    		ula_to_data    <= 0;
			ula_opcode     <= ADD;
    		ula_data1      <= B_imm;
    		ula_data2      <= 0;

    		reg_addr       <= A_addr;
		end
        LW_IMM: begin

            ula_to_data    <= 1;
            ula_opcode     <= ADD;
            ula_data1      <= imm;
            ula_data2      <= 0;

            reg_addr       <= A_addr;
        end
		SW: begin

    		ula_to_data    <= 0;
			ula_opcode     <= ADD;
    		ula_data1      <= B_imm;
    		ula_data2      <= 0;

            mem_we         <= 1;

    		data_default   <= A;
		end
		JR: begin

			pc_chg   <= 1;
			pc_out   <= A;
		end
		JPC: begin


			pc_chg   <= 1;
			pc_out   <= pc_in + B_imm;
		end
		BRFL: begin

			if (rflags_last[imm[RFLAGS_WIDTH-1:0]] == B) begin

				pc_chg   <= 1;
				pc_out   <= A;
			end
		end
		CALL: begin

    		reg_addr     <= REG_FUNC_RET;

    		ula_to_data  <= 1;
			ula_opcode   <= ADD;
	        ula_data1    <= pc_in;
	        ula_data2    <= 0;

			pc_chg   <= 1;
			pc_out   <= A;
		end
		RET: begin


			pc_chg   <= 1;
			pc_out   <= A;
		end
		NOP: begin

		end
		default: begin

    		reg_addr    <= A_addr;

    		ula_to_data <= 1;
			ula_opcode  <= ctrl_in;

			ula_data1   <= A;
	        ula_data2   <= B_imm;
		end
		endcase
	end
end


always @(*) begin
	if (ula_to_data) begin
		data <= ula_out;
		addr <= addr_default;
	end else begin
		data <= data_default;
		addr <= ula_out;
	end
end


assign B_imm = B + imm;

endmodule
module pipeline3(
	clk_in,
	RST,
    ctrl_in,
	pc_in,
	A_addr,
    B_addr,
	A,
	B,
	imm,
	pc_chg,
	pc_out,
    mem_we,
    data,
    addr,
    reg_addr,
    ctrl_out
);



`include "params_proc.v"


input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input [PC_WIDTH-1:0] pc_in;
input [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
input signed [DATA_WIDTH-1:0] A, B, imm;

output reg pc_chg;
output reg [PC_WIDTH-1:0] pc_out;
output reg mem_we;
output reg signed [DATA_WIDTH-1:0] data;
output reg [MEM_WIDTH-1:0] addr;
output reg [REG_ADDR_WIDTH-1:0] reg_addr;
output reg [CTRL_WIDTH-1:0] ctrl_out;


reg [RFLAGS_WIDTH-1:0] rflags_last;
wire signed [DATA_WIDTH-1:0] B_imm;




reg ula_to_data;
reg signed [DATA_WIDTH-1:0] data_default;
reg [MEM_WIDTH-1:0] addr_default;


reg signed [DATA_WIDTH-1:0] ula_data1, ula_data2;
reg [OPCODE_WIDTH-1:0] ula_opcode;
wire signed [DATA_WIDTH-1:0] ula_out;
wire [RFLAGS_WIDTH-1:0] rflags;


ula ula0(.opcode(ula_opcode),
	.data1(ula_data1), .data2(ula_data2),
	.out(ula_out), .rflags(rflags));


always @(negedge clk_in) begin
	if (!RST) begin
		rflags_last  <= 0;
	end else begin
		rflags_last <= rflags;
	end
end


always @(posedge clk_in) begin
    if (!RST) begin
        ctrl_out    <= NOP;
    end else begin
        ctrl_out    <= ctrl_in;
    end
end


always @(posedge clk_in) begin
	if (!RST) begin

		pc_out         <= PC_INITIAL + 1;
		reg_addr       <= 0;
		pc_chg 	       <= 0;

		ula_to_data    <= 0;
		data_default   <= 0;
		addr_default   <= 0;
		ula_opcode     <= NOP;
		ula_data1      <= 0;
		ula_data2      <= 0;
        mem_we         <= 0;
	end	else begin
        pc_out      <= pc_in;
        reg_addr    <= A_addr;
        pc_chg      <= 0;

        ula_to_data    <= 1;
        data_default   <= 0;
        addr_default   <= 0;
        ula_opcode     <= NOP;
        ula_data1      <= 0;
        ula_data2      <= 0;
        mem_we         <= 0;
		case(ctrl_in)
		LW: begin


    		ula_to_data    <= 0;
			ula_opcode     <= ADD;
    		ula_data1      <= B_imm;
    		ula_data2      <= 0;

    		reg_addr       <= A_addr;
		end
        LW_IMM: begin

            ula_to_data    <= 1;
            ula_opcode     <= ADD;
            ula_data1      <= imm;
            ula_data2      <= 0;

            reg_addr       <= A_addr;
        end
		SW: begin

    		ula_to_data    <= 0;
			ula_opcode     <= ADD;
    		ula_data1      <= B_imm;
    		ula_data2      <= 0;

            mem_we         <= 1;

    		data_default   <= A;
		end
		JR: begin

			pc_chg   <= 1;
			pc_out   <= A;
		end
		JPC: begin


			pc_chg   <= 1;
			pc_out   <= pc_in + B_imm;
		end
		BRFL: begin

			if (rflags_last[imm[RFLAGS_WIDTH-1:0]] == B) begin

				pc_chg   <= 1;
				pc_out   <= A;
			end
		end
		CALL: begin

    		reg_addr     <= REG_FUNC_RET;

    		ula_to_data  <= 1;
			ula_opcode   <= ADD;
	        ula_data1    <= pc_in;
	        ula_data2    <= 0;

			pc_chg   <= 1;
			pc_out   <= A;
		end
		RET: begin


			pc_chg   <= 1;
			pc_out   <= A;
		end
		NOP: begin

		end
		default: begin

    		reg_addr    <= A_addr;

    		ula_to_data <= 1;
			ula_opcode  <= ctrl_in;

			ula_data1   <= A;
	        ula_data2   <= B_imm;
		end
		endcase
	end
end


always @(*) begin
	if (ula_to_data) begin
		data <= ula_out;
		addr <= addr_default;
	end else begin
		data <= data_default;
		addr <= ula_out;
	end
end


assign B_imm = B + imm;

endmodule