data/full_repos/permissive/124999927/arith/multiplier_int.v
1: b'%Warning-WIDTH: data/full_repos/permissive/124999927/arith/multiplier_int.v:79: Operator AND expects 8 bits on the LHS, but LHS\'s ARRAYSEL generates 4 bits.\n                                                                              : ... In instance multiplier_int\n      p_product[i] = (opp_a_pipe[i] & {OPP_W{opp_b_pipe[i][i]}}) << i;\n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/124999927/arith/multiplier_int.v:79: Operator AND expects 8 bits on the RHS, but RHS\'s REPLICATE generates 4 bits.\n                                                                              : ... In instance multiplier_int\n      p_product[i] = (opp_a_pipe[i] & {OPP_W{opp_b_pipe[i][i]}}) << i;\n                                    ^\n%Error: Exiting due to 2 warning(s)\n'
module multiplier_int(

  clk,
  aresetn,

  opp_a,
  opp_b,

  out
);

  parameter OPP_W = 4;

  input clk;
  input aresetn;

  input [OPP_W - 1:0] opp_a;
  input [OPP_W - 1:0] opp_b;


  output [2 * OPP_W - 1:0] out;

  reg [OPP_W - 1:0] opp_a_pipe [0:OPP_W - 1];
  reg [OPP_W - 1:0] opp_b_pipe [0:OPP_W - 1];
  reg opp_a_sign [0:OPP_W];
  reg opp_b_sign [0:OPP_W];


  reg [2 * OPP_W - 1:0] acc [0:OPP_W - 1];
  reg [2 * OPP_W - 1:0] p_product [0:OPP_W - 1];

  integer i;
  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin

      for(i = 0; i < OPP_W; i = i + 1) begin
        opp_a_pipe[i] <= 0;
        opp_b_pipe[i] <= 0;
        acc[i] <= 0;
      end

      for(i = 0; i <= OPP_W; i = i + 1) begin
        opp_a_sign[i] <= 0;
        opp_b_sign[i] <= 0;
      end

    end else begin

      opp_a_pipe[0] <= opp_a[OPP_W - 1] ? -opp_a : opp_a;
      opp_b_pipe[0] <= opp_b[OPP_W - 1] ? -opp_b : opp_b;
      opp_a_sign[0] <= opp_a[OPP_W - 1];
      opp_b_sign[0] <= opp_b[OPP_W - 1];
      for(i = 1; i < OPP_W; i = i + 1) begin
        opp_a_pipe[i] <= opp_a_pipe[i - 1];
        opp_b_pipe[i] <= opp_b_pipe[i - 1];
        opp_a_sign[i] <= opp_a_sign[i - 1];
        opp_b_sign[i] <= opp_b_sign[i - 1];
      end
      opp_a_sign[OPP_W] <= opp_a_sign[OPP_W - 1];
      opp_b_sign[OPP_W] <= opp_b_sign[OPP_W - 1];


      acc[0] <= p_product[0];
      for(i = 1; i < OPP_W; i = i + 1) begin
        acc[i] <= acc[i - 1] + p_product[i];
      end
    end
  end


  assign out = (opp_a_sign[OPP_W] ^ opp_b_sign[OPP_W]) ? 
    -acc[OPP_W - 1] : acc[OPP_W - 1];


  always@(*) begin
    for(i = 0; i < OPP_W; i = i + 1) begin

      p_product[i] = (opp_a_pipe[i] & {OPP_W{opp_b_pipe[i][i]}}) << i;
    end
  end

endmodule
module multiplier_int(

  clk,
  aresetn,

  opp_a,
  opp_b,

  out
);


  parameter OPP_W = 4;

  input clk;
  input aresetn;

  input [OPP_W - 1:0] opp_a;
  input [OPP_W - 1:0] opp_b;


  output [2 * OPP_W - 1:0] out;

  reg [OPP_W - 1:0] opp_a_pipe [0:OPP_W - 1];
  reg [OPP_W - 1:0] opp_b_pipe [0:OPP_W - 1];
  reg opp_a_sign [0:OPP_W];
  reg opp_b_sign [0:OPP_W];


  reg [2 * OPP_W - 1:0] acc [0:OPP_W - 1];
  reg [2 * OPP_W - 1:0] p_product [0:OPP_W - 1];

  integer i;
  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin

      for(i = 0; i < OPP_W; i = i + 1) begin
        opp_a_pipe[i] <= 0;
        opp_b_pipe[i] <= 0;
        acc[i] <= 0;
      end

      for(i = 0; i <= OPP_W; i = i + 1) begin
        opp_a_sign[i] <= 0;
        opp_b_sign[i] <= 0;
      end

    end else begin

      opp_a_pipe[0] <= opp_a[OPP_W - 1] ? -opp_a : opp_a;
      opp_b_pipe[0] <= opp_b[OPP_W - 1] ? -opp_b : opp_b;
      opp_a_sign[0] <= opp_a[OPP_W - 1];
      opp_b_sign[0] <= opp_b[OPP_W - 1];
      for(i = 1; i < OPP_W; i = i + 1) begin
        opp_a_pipe[i] <= opp_a_pipe[i - 1];
        opp_b_pipe[i] <= opp_b_pipe[i - 1];
        opp_a_sign[i] <= opp_a_sign[i - 1];
        opp_b_sign[i] <= opp_b_sign[i - 1];
      end
      opp_a_sign[OPP_W] <= opp_a_sign[OPP_W - 1];
      opp_b_sign[OPP_W] <= opp_b_sign[OPP_W - 1];


      acc[0] <= p_product[0];
      for(i = 1; i < OPP_W; i = i + 1) begin
        acc[i] <= acc[i - 1] + p_product[i];
      end
    end
  end


  assign out = (opp_a_sign[OPP_W] ^ opp_b_sign[OPP_W]) ? 
    -acc[OPP_W - 1] : acc[OPP_W - 1];


  always@(*) begin
    for(i = 0; i < OPP_W; i = i + 1) begin

      p_product[i] = (opp_a_pipe[i] & {OPP_W{opp_b_pipe[i][i]}}) << i;
    end
  end

endmodule