data/full_repos/permissive/150133337/fpga/hardware/testbench/axi_slave/axi_slave_tb.v
 line:67: before: "wait"
1: b'%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/axi_slave/axi_slave_tb.v:62: syntax error, unexpected \'@\'\n    @(negedge ACLK);\n    ^\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/axi_slave/axi_slave_tb.v:67: Unsupported: wait statements\n    wait (ARESETN);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/150133337/fpga/hardware/testbench/axi_slave/axi_slave_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n#100000\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/axi_slave/axi_slave_tb.v:69: syntax error, unexpected \'@\'\n    @(negedge ACLK);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/150133337/fpga/hardware/testbench/axi_slave/axi_slave_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\nalways #1 ACLK = ~ACLK;\n       ^\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/axi_slave/axi_slave_tb.v:84: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("hw-imp/bin/waveform/axi_slave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/axi_slave/axi_slave_tb.v:85: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,axi_slave_tb);\n    ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module axi_slave_tb;



    parameter integer PERF_CNTR_WIDTH       = 32;
    parameter integer AXIS_DATA_WIDTH       = 32;
    parameter integer AXIS_ADDR_WIDTH       = 6;
    parameter integer VERBOSITY             = 1;






    reg                                     ACLK;
    reg                                     ARESETN;

    wire                                    tx_req;
    wire                                    tx_done;
    wire                                    rd_done;
    wire                                    wr_done;
    wire                                    processing_done;

    wire [PERF_CNTR_WIDTH-1:0]              total_cycles;
    wire [PERF_CNTR_WIDTH-1:0]              rd_cycles;
    wire [PERF_CNTR_WIDTH-1:0]              pr_cycles;
    wire [PERF_CNTR_WIDTH-1:0]              wr_cycles;

    wire[AXIS_ADDR_WIDTH-1 : 0]             S_AXI_AWADDR;
    wire[2 : 0]                             S_AXI_AWPROT;
    wire                                    S_AXI_AWVALID;
    wire                                    S_AXI_AWREADY;

    wire [AXIS_DATA_WIDTH-1 : 0]            S_AXI_WDATA;
    wire [(AXIS_DATA_WIDTH/8)-1 : 0]        S_AXI_WSTRB;
    wire                                    S_AXI_WVALID;
    wire                                    S_AXI_WREADY;

    wire[1 : 0]                             S_AXI_BRESP;
    wire                                    S_AXI_BVALID;
    wire                                    S_AXI_BREADY;

    wire [AXIS_ADDR_WIDTH-1 : 0]            S_AXI_ARADDR;
    wire [2 : 0]                            S_AXI_ARPROT;
    wire                                    S_AXI_ARVALID;
    wire                                    S_AXI_ARREADY;

    wire[AXIS_DATA_WIDTH-1 : 0]             S_AXI_RDATA;
    wire[1 : 0]                             S_AXI_RRESP;
    wire                                    S_AXI_RVALID;
    wire                                    S_AXI_RREADY;



initial begin
    $display("***************************************");
    $display ("Testing AXI Slave");
    $display("***************************************");
    ACLK = 0;
    ARESETN = 0;
    @(negedge ACLK);
    @(negedge ACLK);
    ARESETN = 1;
#100000

    wait (ARESETN);

    @(negedge ACLK);
    @(negedge ACLK);

    u_axis_driver.test_main;
    u_axis_driver.test_pass;
end

always #1 ACLK = ~ACLK;

always @(posedge ACLK)
begin
end

initial
begin
    $dumpfile("hw-imp/bin/waveform/axi_slave.vcd");
    $dumpvars(0,axi_slave_tb);
end




    axi4lite_slave #(
        .AXIS_DATA_WIDTH        ( AXIS_DATA_WIDTH       ),
        .AXIS_ADDR_WIDTH        ( AXIS_ADDR_WIDTH       ),
        .PERF_CNTR_WIDTH        ( PERF_CNTR_WIDTH       )
    ) axi_slave_i (
        .S_AXI_ACLK             ( ACLK                  ),
        .S_AXI_ARESETN          ( ARESETN               ),
    
        .S_AXI_AWADDR           ( S_AXI_AWADDR          ),
        .S_AXI_AWPROT           ( S_AXI_AWPROT          ),
        .S_AXI_AWVALID          ( S_AXI_AWVALID         ),
        .S_AXI_AWREADY          ( S_AXI_AWREADY         ),
    
        .S_AXI_WDATA            ( S_AXI_WDATA           ),
        .S_AXI_WSTRB            ( S_AXI_WSTRB           ),
        .S_AXI_WVALID           ( S_AXI_WVALID          ),
        .S_AXI_WREADY           ( S_AXI_WREADY          ),
    
        .S_AXI_BRESP            ( S_AXI_BRESP           ),
        .S_AXI_BVALID           ( S_AXI_BVALID          ),
        .S_AXI_BREADY           ( S_AXI_BREADY          ),
    
        .S_AXI_ARADDR           ( S_AXI_ARADDR          ),
        .S_AXI_ARPROT           ( S_AXI_ARPROT          ),
        .S_AXI_ARVALID          ( S_AXI_ARVALID         ),
        .S_AXI_ARREADY          ( S_AXI_ARREADY         ),
    
        .S_AXI_RDATA            ( S_AXI_RDATA           ),
        .S_AXI_RRESP            ( S_AXI_RRESP           ),
        .S_AXI_RVALID           ( S_AXI_RVALID          ),
        .S_AXI_RREADY           ( S_AXI_RREADY          ),
    
        .tx_req                 ( tx_req                ),
        .tx_done                ( tx_done               ),
        
        .rd_done                ( rd_done               ),
        .processing_done        ( processing_done       ),
        .wr_done                ( wr_done               ),
    
        .total_cycles           ( total_cycles          ),
        .rd_cycles              ( rd_cycles             ),
        .pr_cycles              ( pr_cycles             ),
        .wr_cycles              ( wr_cycles             )
    );





axi_slave_tb_driver
#(
    .PERF_CNTR_WIDTH            ( PERF_CNTR_WIDTH       ),
    .AXIS_DATA_WIDTH            ( AXIS_DATA_WIDTH       ),
    .AXIS_ADDR_WIDTH            ( AXIS_ADDR_WIDTH       ),
    .VERBOSITY                  ( VERBOSITY             )
) u_axis_driver (
    .tx_req                     ( tx_req                ),
    .tx_done                    ( tx_done               ),
    .rd_done                    ( rd_done               ),
    .wr_done                    ( wr_done               ),
    .processing_done            ( processing_done       ),
    .total_cycles               ( total_cycles          ),
    .rd_cycles                  ( rd_cycles             ),
    .pr_cycles                  ( pr_cycles             ),
    .wr_cycles                  ( wr_cycles             ),
    .S_AXI_ACLK                 ( ACLK                  ),
    .S_AXI_ARESETN              ( ARESETN               ),
    .S_AXI_AWADDR               ( S_AXI_AWADDR          ),
    .S_AXI_AWPROT               ( S_AXI_AWPROT          ),
    .S_AXI_AWVALID              ( S_AXI_AWVALID         ),
    .S_AXI_AWREADY              ( S_AXI_AWREADY         ),
    .S_AXI_WDATA                ( S_AXI_WDATA           ),
    .S_AXI_WSTRB                ( S_AXI_WSTRB           ),
    .S_AXI_WVALID               ( S_AXI_WVALID          ),
    .S_AXI_WREADY               ( S_AXI_WREADY          ),
    .S_AXI_BRESP                ( S_AXI_BRESP           ),
    .S_AXI_BVALID               ( S_AXI_BVALID          ),
    .S_AXI_BREADY               ( S_AXI_BREADY          ),
    .S_AXI_ARADDR               ( S_AXI_ARADDR          ),
    .S_AXI_ARPROT               ( S_AXI_ARPROT          ),
    .S_AXI_ARVALID              ( S_AXI_ARVALID         ),
    .S_AXI_ARREADY              ( S_AXI_ARREADY         ),
    .S_AXI_RDATA                ( S_AXI_RDATA           ),
    .S_AXI_RRESP                ( S_AXI_RRESP           ),
    .S_AXI_RVALID               ( S_AXI_RVALID          ),
    .S_AXI_RREADY               ( S_AXI_RREADY          )
);


endmodule
module axi_slave_tb;




    parameter integer PERF_CNTR_WIDTH       = 32;
    parameter integer AXIS_DATA_WIDTH       = 32;
    parameter integer AXIS_ADDR_WIDTH       = 6;
    parameter integer VERBOSITY             = 1;






    reg                                     ACLK;
    reg                                     ARESETN;

    wire                                    tx_req;
    wire                                    tx_done;
    wire                                    rd_done;
    wire                                    wr_done;
    wire                                    processing_done;

    wire [PERF_CNTR_WIDTH-1:0]              total_cycles;
    wire [PERF_CNTR_WIDTH-1:0]              rd_cycles;
    wire [PERF_CNTR_WIDTH-1:0]              pr_cycles;
    wire [PERF_CNTR_WIDTH-1:0]              wr_cycles;

    wire[AXIS_ADDR_WIDTH-1 : 0]             S_AXI_AWADDR;
    wire[2 : 0]                             S_AXI_AWPROT;
    wire                                    S_AXI_AWVALID;
    wire                                    S_AXI_AWREADY;

    wire [AXIS_DATA_WIDTH-1 : 0]            S_AXI_WDATA;
    wire [(AXIS_DATA_WIDTH/8)-1 : 0]        S_AXI_WSTRB;
    wire                                    S_AXI_WVALID;
    wire                                    S_AXI_WREADY;

    wire[1 : 0]                             S_AXI_BRESP;
    wire                                    S_AXI_BVALID;
    wire                                    S_AXI_BREADY;

    wire [AXIS_ADDR_WIDTH-1 : 0]            S_AXI_ARADDR;
    wire [2 : 0]                            S_AXI_ARPROT;
    wire                                    S_AXI_ARVALID;
    wire                                    S_AXI_ARREADY;

    wire[AXIS_DATA_WIDTH-1 : 0]             S_AXI_RDATA;
    wire[1 : 0]                             S_AXI_RRESP;
    wire                                    S_AXI_RVALID;
    wire                                    S_AXI_RREADY;



initial begin
    $display("***************************************");
    $display ("Testing AXI Slave");
    $display("***************************************");
    ACLK = 0;
    ARESETN = 0;
    @(negedge ACLK);
    @(negedge ACLK);
    ARESETN = 1;
#100000

    wait (ARESETN);

    @(negedge ACLK);
    @(negedge ACLK);

    u_axis_driver.test_main;
    u_axis_driver.test_pass;
end

always #1 ACLK = ~ACLK;

always @(posedge ACLK)
begin
end

initial
begin
    $dumpfile("hw-imp/bin/waveform/axi_slave.vcd");
    $dumpvars(0,axi_slave_tb);
end




    axi4lite_slave #(
        .AXIS_DATA_WIDTH        ( AXIS_DATA_WIDTH       ),
        .AXIS_ADDR_WIDTH        ( AXIS_ADDR_WIDTH       ),
        .PERF_CNTR_WIDTH        ( PERF_CNTR_WIDTH       )
    ) axi_slave_i (
        .S_AXI_ACLK             ( ACLK                  ),
        .S_AXI_ARESETN          ( ARESETN               ),
    
        .S_AXI_AWADDR           ( S_AXI_AWADDR          ),
        .S_AXI_AWPROT           ( S_AXI_AWPROT          ),
        .S_AXI_AWVALID          ( S_AXI_AWVALID         ),
        .S_AXI_AWREADY          ( S_AXI_AWREADY         ),
    
        .S_AXI_WDATA            ( S_AXI_WDATA           ),
        .S_AXI_WSTRB            ( S_AXI_WSTRB           ),
        .S_AXI_WVALID           ( S_AXI_WVALID          ),
        .S_AXI_WREADY           ( S_AXI_WREADY          ),
    
        .S_AXI_BRESP            ( S_AXI_BRESP           ),
        .S_AXI_BVALID           ( S_AXI_BVALID          ),
        .S_AXI_BREADY           ( S_AXI_BREADY          ),
    
        .S_AXI_ARADDR           ( S_AXI_ARADDR          ),
        .S_AXI_ARPROT           ( S_AXI_ARPROT          ),
        .S_AXI_ARVALID          ( S_AXI_ARVALID         ),
        .S_AXI_ARREADY          ( S_AXI_ARREADY         ),
    
        .S_AXI_RDATA            ( S_AXI_RDATA           ),
        .S_AXI_RRESP            ( S_AXI_RRESP           ),
        .S_AXI_RVALID           ( S_AXI_RVALID          ),
        .S_AXI_RREADY           ( S_AXI_RREADY          ),
    
        .tx_req                 ( tx_req                ),
        .tx_done                ( tx_done               ),
        
        .rd_done                ( rd_done               ),
        .processing_done        ( processing_done       ),
        .wr_done                ( wr_done               ),
    
        .total_cycles           ( total_cycles          ),
        .rd_cycles              ( rd_cycles             ),
        .pr_cycles              ( pr_cycles             ),
        .wr_cycles              ( wr_cycles             )
    );





axi_slave_tb_driver
#(
    .PERF_CNTR_WIDTH            ( PERF_CNTR_WIDTH       ),
    .AXIS_DATA_WIDTH            ( AXIS_DATA_WIDTH       ),
    .AXIS_ADDR_WIDTH            ( AXIS_ADDR_WIDTH       ),
    .VERBOSITY                  ( VERBOSITY             )
) u_axis_driver (
    .tx_req                     ( tx_req                ),
    .tx_done                    ( tx_done               ),
    .rd_done                    ( rd_done               ),
    .wr_done                    ( wr_done               ),
    .processing_done            ( processing_done       ),
    .total_cycles               ( total_cycles          ),
    .rd_cycles                  ( rd_cycles             ),
    .pr_cycles                  ( pr_cycles             ),
    .wr_cycles                  ( wr_cycles             ),
    .S_AXI_ACLK                 ( ACLK                  ),
    .S_AXI_ARESETN              ( ARESETN               ),
    .S_AXI_AWADDR               ( S_AXI_AWADDR          ),
    .S_AXI_AWPROT               ( S_AXI_AWPROT          ),
    .S_AXI_AWVALID              ( S_AXI_AWVALID         ),
    .S_AXI_AWREADY              ( S_AXI_AWREADY         ),
    .S_AXI_WDATA                ( S_AXI_WDATA           ),
    .S_AXI_WSTRB                ( S_AXI_WSTRB           ),
    .S_AXI_WVALID               ( S_AXI_WVALID          ),
    .S_AXI_WREADY               ( S_AXI_WREADY          ),
    .S_AXI_BRESP                ( S_AXI_BRESP           ),
    .S_AXI_BVALID               ( S_AXI_BVALID          ),
    .S_AXI_BREADY               ( S_AXI_BREADY          ),
    .S_AXI_ARADDR               ( S_AXI_ARADDR          ),
    .S_AXI_ARPROT               ( S_AXI_ARPROT          ),
    .S_AXI_ARVALID              ( S_AXI_ARVALID         ),
    .S_AXI_ARREADY              ( S_AXI_ARREADY         ),
    .S_AXI_RDATA                ( S_AXI_RDATA           ),
    .S_AXI_RRESP                ( S_AXI_RRESP           ),
    .S_AXI_RVALID               ( S_AXI_RVALID          ),
    .S_AXI_RREADY               ( S_AXI_RREADY          )
);


endmodule