data/full_repos/permissive/210844779/lab3/3.1/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab3/3.1/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210844779/lab3/3.1/tb.v:6: Cannot find file containing module: \'prior_enc\'\nprior_enc u0(I,Y);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab3/3.1,data/full_repos/permissive/210844779/prior_enc\n             data/full_repos/permissive/210844779/lab3/3.1,data/full_repos/permissive/210844779/prior_enc.v\n             data/full_repos/permissive/210844779/lab3/3.1,data/full_repos/permissive/210844779/prior_enc.sv\n             prior_enc\n             prior_enc.v\n             prior_enc.sv\n             obj_dir/prior_enc\n             obj_dir/prior_enc.v\n             obj_dir/prior_enc.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab3/3.1/tb.v:11: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\nI=$random;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

reg [15:0]I;
wire [3:0]Y;

prior_enc u0(I,Y);

always
begin

I=$random;

#10;
$write("for write Y=%b I=%b \n",Y,I);
end

endmodule
module tb();


reg [15:0]I;
wire [3:0]Y;

prior_enc u0(I,Y);

always
begin

I=$random;

#10;
$write("for write Y=%b I=%b \n",Y,I);
end

endmodule