data/full_repos/permissive/129934093/ALU_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/129934093/ALU_test.v:61: Unsupported: Ignoring delay on this delayed statement.\n  clk=1; #50;   \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129934093/ALU_test.v:62: Unsupported: Ignoring delay on this delayed statement.\n  clk=0; #50;   \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/129934093/ALU_test.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #20; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129934093/ALU_test.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #60; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129934093/ALU_test.v:113: Unsupported: Ignoring delay on this delayed statement.\n   #20; \n   ^\n%Warning-WIDTH: data/full_repos/permissive/129934093/ALU_test.v:89: Bit extraction of array[12:0] requires 4 bit index, not 11 bits.\n                                                                  : ... In instance ALU_test\n  {aluop,a,b,exp_result}= testvec[vec_cnt]; \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/129934093/ALU_test.v:107: Bit extraction of array[12:0] requires 4 bit index, not 11 bits.\n                                                                   : ... In instance ALU_test\n  if ((testvec[vec_cnt][99:96] === 4\'bxxxx))\n              ^\n%Error: data/full_repos/permissive/129934093/ALU_test.v:124: Cannot find file containing module: \'ALU\'\n   ALU ALU_self_impl(.a(a),\n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/129934093,data/full_repos/permissive/129934093/ALU\n             data/full_repos/permissive/129934093,data/full_repos/permissive/129934093/ALU.v\n             data/full_repos/permissive/129934093,data/full_repos/permissive/129934093/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_test;


   reg [31:0]	a;
   reg [31:0]	b;
   reg [3:0]	aluop;


   wire [31:0]	result;
   wire			zero;


   reg			clk ;


   reg [31:0]	exp_result;
   wire			exp_zero;


   reg [10:0]	vec_cnt, err_cnt;











    reg [99:0] testvec [12:0];
    


   always
	begin
		clk=1; #50;
		clk=0; #50;
	end


	initial
	begin



		$readmemh("testvectors_hex.txt", testvec);
		err_cnt=0;
		vec_cnt=0;
	end

   



   assign exp_zero = (exp_result == 32'd0)? 1:0;
   

	always @ (posedge clk)
	begin

		#20; 


		{aluop,a,b,exp_result}= testvec[vec_cnt]; 


		#60; 


		if ((result !== exp_result) | (zero !== exp_zero))
		begin                                         

			$display("Error at %5d ns: Aluop %b a=%h b=%h", $time, aluop,a,b);
			$display("       %h (%h expected)",result,exp_result);
			$display(" Zero: %b (%b expected)",zero,exp_zero);
			err_cnt = err_cnt + 1;
		end

		vec_cnt = vec_cnt + 1;
	

		if ((testvec[vec_cnt][99:96] === 4'bxxxx))
		begin

			$display ("%d tests completed with %d errors", vec_cnt, err_cnt);
			

			#20; 
			

			$finish;
		end
	end



   

   ALU ALU_self_impl(.a(a),
                     .b(b),
                     .aluop(aluop),
                     .zero(zero),
                     .result(result));

   
endmodule
module ALU_test;



   reg [31:0]	a;
   reg [31:0]	b;
   reg [3:0]	aluop;


   wire [31:0]	result;
   wire			zero;


   reg			clk ;


   reg [31:0]	exp_result;
   wire			exp_zero;


   reg [10:0]	vec_cnt, err_cnt;











    reg [99:0] testvec [12:0];
    


   always
	begin
		clk=1; #50;
		clk=0; #50;
	end


	initial
	begin



		$readmemh("testvectors_hex.txt", testvec);
		err_cnt=0;
		vec_cnt=0;
	end

   



   assign exp_zero = (exp_result == 32'd0)? 1:0;
   

	always @ (posedge clk)
	begin

		#20; 


		{aluop,a,b,exp_result}= testvec[vec_cnt]; 


		#60; 


		if ((result !== exp_result) | (zero !== exp_zero))
		begin                                         

			$display("Error at %5d ns: Aluop %b a=%h b=%h", $time, aluop,a,b);
			$display("       %h (%h expected)",result,exp_result);
			$display(" Zero: %b (%b expected)",zero,exp_zero);
			err_cnt = err_cnt + 1;
		end

		vec_cnt = vec_cnt + 1;
	

		if ((testvec[vec_cnt][99:96] === 4'bxxxx))
		begin

			$display ("%d tests completed with %d errors", vec_cnt, err_cnt);
			

			#20; 
			

			$finish;
		end
	end



   

   ALU ALU_self_impl(.a(a),
                     .b(b),
                     .aluop(aluop),
                     .zero(zero),
                     .result(result));

   
endmodule