data/full_repos/permissive/131069375/uv-risc/verilog/system.v
1: b"%Error: data/full_repos/permissive/131069375/uv-risc/verilog/system.v:12: Cannot find file containing module: 'auto_reset'\n   auto_reset reset_gen (.clock(clk), .reset(reset));\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131069375/uv-risc/verilog,data/full_repos/permissive/131069375/auto_reset\n             data/full_repos/permissive/131069375/uv-risc/verilog,data/full_repos/permissive/131069375/auto_reset.v\n             data/full_repos/permissive/131069375/uv-risc/verilog,data/full_repos/permissive/131069375/auto_reset.sv\n             auto_reset\n             auto_reset.v\n             auto_reset.sv\n             obj_dir/auto_reset\n             obj_dir/auto_reset.v\n             obj_dir/auto_reset.sv\n%Error: data/full_repos/permissive/131069375/uv-risc/verilog/system.v:25: Cannot find file containing module: 'instr_mem'\n   instr_mem imem (.clk(cpu_clk),.we(dummy_we),.data_in(mem_in),.addr(pc),.data_out(instr));\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/131069375/uv-risc/verilog/system.v:28: Cannot find file containing module: 'data_mem'\n   data_mem dmem (.clk(cpu_clk),.we(mem_we),\n   ^~~~~~~~\n%Error: data/full_repos/permissive/131069375/uv-risc/verilog/system.v:34: Cannot find file containing module: 'uvrisc'\n   uvrisc uvrisc0 (.reset(reset),.clk(cpu_clk),.pc(pc),.instr(instr),\n   ^~~~~~\n%Error: data/full_repos/permissive/131069375/uv-risc/verilog/system.v:41: Cannot find file containing module: 'word_to_7seg'\n   word_to_7seg decoder (.word(pc), .digits(digits));\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/131069375/uv-risc/verilog/system.v:43: Cannot find file containing module: 'strobe'\n   strobe strobe0 (.reset(reset), .clock(clk), .digits(digits), .seg(seg), .an(an));\n   ^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module system(
 input 	       clk,
 output [6:0]  seg,
 output [3:0]  an, 
 output        dp
);

   wire        reset, cpu_clk;
   
   auto_reset reset_gen (.clock(clk), .reset(reset));


   assign cpu_clk = clk;
      

   wire [15:0] pc, instr;

   wire mem_we, dummy_we;
   wire [15:0] mem_in, mem_out, mem_addr;
   
   assign dummy_we = (instr[15:13] == 3'b101) && ~instr[6];
   
   instr_mem imem (.clk(cpu_clk),.we(dummy_we),.data_in(mem_in),.addr(pc),.data_out(instr));


   data_mem dmem (.clk(cpu_clk),.we(mem_we),
		  .addr(mem_addr),.data_in(mem_in),.data_out(mem_out));

   wire        halt;


   uvrisc uvrisc0 (.reset(reset),.clk(cpu_clk),.pc(pc),.instr(instr),
		   .mem_we(mem_we),.mem_addr(mem_addr),
		   .mem_in(mem_in),.mem_out(mem_out),
		   .halt(halt));


   wire [27:0] digits;
   word_to_7seg decoder (.word(pc), .digits(digits));

   strobe strobe0 (.reset(reset), .clock(clk), .digits(digits), .seg(seg), .an(an));

   assign dp = halt;
   
endmodule
module system(
 input 	       clk,
 output [6:0]  seg,
 output [3:0]  an, 
 output        dp
);


   wire        reset, cpu_clk;
   
   auto_reset reset_gen (.clock(clk), .reset(reset));


   assign cpu_clk = clk;
      

   wire [15:0] pc, instr;

   wire mem_we, dummy_we;
   wire [15:0] mem_in, mem_out, mem_addr;
   
   assign dummy_we = (instr[15:13] == 3'b101) && ~instr[6];
   
   instr_mem imem (.clk(cpu_clk),.we(dummy_we),.data_in(mem_in),.addr(pc),.data_out(instr));


   data_mem dmem (.clk(cpu_clk),.we(mem_we),
		  .addr(mem_addr),.data_in(mem_in),.data_out(mem_out));

   wire        halt;


   uvrisc uvrisc0 (.reset(reset),.clk(cpu_clk),.pc(pc),.instr(instr),
		   .mem_we(mem_we),.mem_addr(mem_addr),
		   .mem_in(mem_in),.mem_out(mem_out),
		   .halt(halt));


   wire [27:0] digits;
   word_to_7seg decoder (.word(pc), .digits(digits));

   strobe strobe0 (.reset(reset), .clock(clk), .digits(digits), .seg(seg), .an(an));

   assign dp = halt;
   
endmodule