data/full_repos/permissive/124803629/src/Pipeline_CPU/UART.v
1: b'%Warning-WIDTH: data/full_repos/permissive/124803629/src/Pipeline_CPU/UART.v:55: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                               : ... In instance UART.UART_Receiver_1\n      rx_data[cnt_catch]<=uart_rx;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module UART_Receiver(uart_rx, sysclk, rx_data, rx_status, rx_LoadFinish, reset);
input uart_rx, rx_LoadFinish, sysclk, reset;
output reg [7:0] rx_data;
output reg rx_status;

reg [3:0] cnt_catch;
reg [4:0] cnt_clk;
reg status;
reg [8:0] brcnt16;

always @(posedge sysclk or negedge reset)
begin
	if(~reset) begin
		brcnt16 <= 9'd0;
		cnt_catch <= 4'd0;
		cnt_clk <= 5'd0;
		status <= 0;
		rx_status <= 0;
		rx_data <= 8'd0;
		end
	else begin
		if(~status) begin
			if(rx_LoadFinish)
				rx_status <= 0;
			if(~uart_rx) begin
				if(cnt_clk==5'd8) begin
					cnt_clk <= 5'd0;
					status <= 1;
					brcnt16 <= 9'd0;
					end
				else begin
					if (brcnt16 == 9'd325) begin
						brcnt16 <= 9'd0;
						cnt_clk <= cnt_clk + 1;
						end
					else
						brcnt16 <= brcnt16 + 1;
				end
			end
		end
		else begin
			if(cnt_catch==4'd9) begin
				cnt_catch <= 4'd0;
				status <= 0;
				brcnt16 <= 9'd0;
				cnt_clk <= 5'd0;
				rx_status <= 1;
				end
			else begin
				if(cnt_clk == 5'd16) begin
					cnt_clk <= 5'd0;
					brcnt16 <= 9'd0;
					cnt_catch <= cnt_catch+1;
					if (cnt_catch < 4'd8)
						rx_data[cnt_catch]<=uart_rx;
					end
				else begin
					if(brcnt16 == 9'd325) begin
						brcnt16 <= 9'd0;
						cnt_clk <= cnt_clk + 1;
						end
					else
						brcnt16 <= brcnt16 + 1;
				end
			end
		end
	end
end

endmodule
module UART_Receiver(uart_rx, sysclk, rx_data, rx_status, rx_LoadFinish, reset);

input uart_rx, rx_LoadFinish, sysclk, reset;
output reg [7:0] rx_data;
output reg rx_status;

reg [3:0] cnt_catch;
reg [4:0] cnt_clk;
reg status;
reg [8:0] brcnt16;

always @(posedge sysclk or negedge reset)
begin
	if(~reset) begin
		brcnt16 <= 9'd0;
		cnt_catch <= 4'd0;
		cnt_clk <= 5'd0;
		status <= 0;
		rx_status <= 0;
		rx_data <= 8'd0;
		end
	else begin
		if(~status) begin
			if(rx_LoadFinish)
				rx_status <= 0;
			if(~uart_rx) begin
				if(cnt_clk==5'd8) begin
					cnt_clk <= 5'd0;
					status <= 1;
					brcnt16 <= 9'd0;
					end
				else begin
					if (brcnt16 == 9'd325) begin
						brcnt16 <= 9'd0;
						cnt_clk <= cnt_clk + 1;
						end
					else
						brcnt16 <= brcnt16 + 1;
				end
			end
		end
		else begin
			if(cnt_catch==4'd9) begin
				cnt_catch <= 4'd0;
				status <= 0;
				brcnt16 <= 9'd0;
				cnt_clk <= 5'd0;
				rx_status <= 1;
				end
			else begin
				if(cnt_clk == 5'd16) begin
					cnt_clk <= 5'd0;
					brcnt16 <= 9'd0;
					cnt_catch <= cnt_catch+1;
					if (cnt_catch < 4'd8)
						rx_data[cnt_catch]<=uart_rx;
					end
				else begin
					if(brcnt16 == 9'd325) begin
						brcnt16 <= 9'd0;
						cnt_clk <= cnt_clk + 1;
						end
					else
						brcnt16 <= brcnt16 + 1;
				end
			end
		end
	end
end

endmodule