data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:434: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:436: Unsupported: Ignoring delay on this delayed statement.\n  #5000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:438: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:440: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:442: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:444: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:446: Unsupported: Ignoring delay on this delayed statement.\n  #30;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:450: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:452: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:456: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:458: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:462: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:464: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n                                                                            ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock50_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n                                                                            ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_p\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n                                                                            ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:398: Cell has missing pin: \'local_clock509_in_n\'\n mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea uut (\n                                                                            ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:361: Multiple top level modules\n                                                                                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                                                                                         : ... Top module \'ssynchronizer_90_270\'\nmodule ssynchronizer_90_270 #(\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                                                                                         : ... Top module \'mything_tb\'\nmodule mything_tb;\n       ^~~~~~~~~~\n                                                                                                                                                         : ... Top module \'mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top\'\nmodule mza_test029_pll_509divider_and_revo_encoder_plus_calibration_serdes_althea_top (\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_p\'\n                                                                                                                                                         : ... Suggested alternative: \'e_p\'\n  .trg_out_p(f_p), .trg_out_n(f_n),\n             ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:494: Signal definition not found, creating implicitly: \'f_n\'\n                                                                                                                                                         : ... Suggested alternative: \'d_n\'\n  .trg_out_p(f_p), .trg_out_n(f_n),\n                              ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_p\'\n                                                                                                                                              : ... Suggested alternative: \'remote_clock509_in_p\'\n  .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n   ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:399: Pin not found: \'remote_clock50_in_n\'\n                                                                                                                                              : ... Suggested alternative: \'remote_clock509_in_n\'\n  .remote_clock50_in_p(remote_clock50_in_p), .remote_clock50_in_n(remote_clock50_in_n),\n                                              ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:409: Signal definition not found, creating implicitly: \'l_p\'\n  .led_revo(l_p),\n            ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/115035459/verilog/src/mza-test029.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.revA.v:410: Signal definition not found, creating implicitly: \'l_n\'\n                                                                                                                                                         : ... Suggested alternative: \'l_p\'\n  .led_rfclock(l_n),\n               ^~~\n%Error: Exiting due to 2 error(s), 22 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ssynchronizer_90_270 #(
	parameter WIDTH=1
) (
	input clock1,
	input clock2, clock1_90, clock1_270,
	input reset,
	input [WIDTH-1:0] in1,
	output [WIDTH-1:0] out2
);
	reg [WIDTH-1:0] intermediate_f1;
	reg [WIDTH-1:0] intermediate_f2;
	reg [WIDTH-1:0] intermediate_f3;
	reg [WIDTH-1:0] intermediate_f4;
	reg [WIDTH-1:0] intermediate_s1;
	reg [WIDTH-1:0] intermediate_s2;

	always @(posedge clock1) begin
		if (reset) begin
			intermediate_f1 <= 0;
		end else begin
			intermediate_f1 <= in1;
		end
	end
	always @(posedge clock1_270) begin
		if (reset) begin
			intermediate_f2 <= 0;
		end else begin
			intermediate_f2 <= intermediate_f1;
		end
	end
	always @(negedge clock1) begin
		if (reset) begin
			intermediate_f3 <= 0;
		end else begin
			intermediate_f3 <= intermediate_f2;
		end
	end
	always @(posedge clock1_90) begin
		if (reset) begin
			intermediate_f4 <= 0;
		end else begin
			intermediate_f4 <= intermediate_f3;
		end
	end

	always @(negedge clock2) begin
		if (reset) begin
			intermediate_s1 <= 0;
		end else begin

			intermediate_s1 <= intermediate_f4;
		end
	end
	always @(posedge clock2) begin
		if (reset) begin
			intermediate_s2 <= 0;
		end else begin
			intermediate_s2 <= intermediate_s1;
		end
	end
	assign out2 = intermediate_s2;
endmodule
module ssynchronizer_90_270 #(
	parameter WIDTH=1
) (
	input clock1,
	input clock2, clock1_90, clock1_270,
	input reset,
	input [WIDTH-1:0] in1,
	output [WIDTH-1:0] out2
);

	reg [WIDTH-1:0] intermediate_f1;
	reg [WIDTH-1:0] intermediate_f2;
	reg [WIDTH-1:0] intermediate_f3;
	reg [WIDTH-1:0] intermediate_f4;
	reg [WIDTH-1:0] intermediate_s1;
	reg [WIDTH-1:0] intermediate_s2;

	always @(posedge clock1) begin
		if (reset) begin
			intermediate_f1 <= 0;
		end else begin
			intermediate_f1 <= in1;
		end
	end
	always @(posedge clock1_270) begin
		if (reset) begin
			intermediate_f2 <= 0;
		end else begin
			intermediate_f2 <= intermediate_f1;
		end
	end
	always @(negedge clock1) begin
		if (reset) begin
			intermediate_f3 <= 0;
		end else begin
			intermediate_f3 <= intermediate_f2;
		end
	end
	always @(posedge clock1_90) begin
		if (reset) begin
			intermediate_f4 <= 0;
		end else begin
			intermediate_f4 <= intermediate_f3;
		end
	end

	always @(negedge clock2) begin
		if (reset) begin
			intermediate_s1 <= 0;
		end else begin

			intermediate_s1 <= intermediate_f4;
		end
	end
	always @(posedge clock2) begin
		if (reset) begin
			intermediate_s2 <= 0;
		end else begin
			intermediate_s2 <= intermediate_s1;
		end
	end
	assign out2 = intermediate_s2;
endmodule