data/full_repos/permissive/143278/ivltests/pr3534422.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3534422.v:12: Unsupported: Ignoring delay on this delayed statement.\n      initial #1 flags[j] = 1\'b1;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3534422.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #2 $display("flags = %b", flags);\n  ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug();

reg [3:0] flags = 4'b0000;

generate
  genvar i;

  for (i = 1; i < 4; i = i + 1) begin:loop
    localparam j = i;

    if (j > 0) begin
      initial #1 flags[j] = 1'b1;
    end
  end
endgenerate

initial begin
  #2 $display("flags = %b", flags);
  if (flags === 4'b1110)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module bug();


reg [3:0] flags = 4'b0000;

generate
  genvar i;

  for (i = 1; i < 4; i = i + 1) begin:loop
    localparam j = i;

    if (j > 0) begin
      initial #1 flags[j] = 1'b1;
    end
  end
endgenerate

initial begin
  #2 $display("flags = %b", flags);
  if (flags === 4'b1110)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule