data/full_repos/permissive/180199545/DigitalSSD/digital_ssd_test_top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/180199545/DigitalSSD/digital_ssd_test_top.v:50: Cannot find file containing module: \'BUF\'\n BUF BUF1 (board_clk, ClkPort);  \n ^~~\n        ... Looked in:\n             data/full_repos/permissive/180199545/DigitalSSD,data/full_repos/permissive/180199545/BUF\n             data/full_repos/permissive/180199545/DigitalSSD,data/full_repos/permissive/180199545/BUF.v\n             data/full_repos/permissive/180199545/DigitalSSD,data/full_repos/permissive/180199545/BUF.sv\n             BUF\n             BUF.v\n             BUF.sv\n             obj_dir/BUF\n             obj_dir/BUF.v\n             obj_dir/BUF.sv\n%Error: data/full_repos/permissive/180199545/DigitalSSD/digital_ssd_test_top.v:51: Cannot find file containing module: \'BUF\'\n BUF BUF2 (reset, BtnU);\n ^~~\n%Error: data/full_repos/permissive/180199545/DigitalSSD/digital_ssd_test_top.v:52: Cannot find file containing module: \'BUF\'\n BUF BUF3 (start, ~BtnD);\n ^~~\n%Error: data/full_repos/permissive/180199545/DigitalSSD/digital_ssd_test_top.v:71: Cannot find file containing module: \'hvsync_generator\'\n hvsync_generator syncgen(.clk(clk), .reset(reset),.vga_h_sync(vga_h_sync), .vga_v_sync(vga_v_sync), .inDisplayArea(inDisplayArea), .CounterX(CounterX), .CounterY(CounterY));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/180199545/DigitalSSD/digital_ssd_test_top.v:74: Cannot find file containing module: \'digital_ssd\'\n digital_ssd LeftSSD(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/180199545/DigitalSSD/digital_ssd_test_top.v:120: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                          : ... In instance digital_ssd_test_top\n     vgaBlue <= LeftSSDBgColor[1:0];\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/180199545/DigitalSSD/digital_ssd_test_top.v:126: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                          : ... In instance digital_ssd_test_top\n     vgaBlue <= LeftSSDColor[1:0];\n             ^~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module digital_ssd_test_top(ClkPort, vga_h_sync, vga_v_sync, vgaRed, vgaGreen, vgaBlue, btnU, btnD,
	St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar,
	An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp,
	LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7,
	JA, JB,
	Sw);
	input ClkPort, btnU, btnD;
	input [7:0] JA, JB;
	input [7:0] Sw;
	output St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar;
	output vga_h_sync, vga_v_sync, vgaRed, vgaGreen, vgaBlue;
	output An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp;
	output LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7;
	reg [2:0] vgaRed, vgaGreen, vgaBlue;
	


	reg [10:0] LeftSSDX;
	reg [9:0] LeftSSDY;
	wire [3:0] LeftSSDScale;
	
	wire [3:0] LeftSSDValue;
	
	wire LeftSSDHit;
	wire LeftSSDBg;
	
	reg [10:0] RightSSDX;
	reg [9:0] RightSSDY;
	reg [9:0] RightSSDScale;
	
	reg [3:0] RightSSDValue;
	
	wire RightSSDHit;
	
	reg [7:0] LeftSSDColor;
	reg [7:0] LeftSSDBgColor;

	
	

	

	wire	reset, start, ClkPort, board_clk, clk, button_clk;
	
	BUF BUF1 (board_clk, ClkPort); 	
	BUF BUF2 (reset, BtnU);
	BUF BUF3 (start, ~BtnD);
	
	reg [27:0]	DIV_CLK;
	always @ (posedge board_clk, posedge reset)  
	begin : CLOCK_DIVIDER
      if (reset)
			DIV_CLK <= 0;
      else
			DIV_CLK <= DIV_CLK + 1'b1;
	end	

	assign	button_clk = DIV_CLK[18];
	assign	clk = DIV_CLK[1];
	assign 	{St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar} = {5'b11111};
	
	wire inDisplayArea;
	wire [9:0] CounterX;
	wire [9:0] CounterY;

	hvsync_generator syncgen(.clk(clk), .reset(reset),.vga_h_sync(vga_h_sync), .vga_v_sync(vga_v_sync), .inDisplayArea(inDisplayArea), .CounterX(CounterX), .CounterY(CounterY));
	

	digital_ssd LeftSSD(
		.clk(clk),
		.reset(reset),
		.ObjectX(LeftSSDX),
		.ObjectY(LeftSSDY),
		.ObjectScale(LeftSSDScale),
		.Value(LeftSSDValue),
		.PollX(CounterX),
		.PollY(CounterY),
		.Hit(LeftSSDHit),
		.Hit2(LeftSSDBg)
	);
	



	

	always @(posedge DIV_CLK[18])
		begin
		if(reset)
			begin

				LeftSSDX <= 11'd255;
				LeftSSDY <= 10'd220;
				LeftSSDColor <= 8'b11111111;
				LeftSSDBgColor <= 8'b11100000;
			end
		end
	



	

	always @(posedge clk)
	begin
		if(inDisplayArea)
			begin
				vgaRed <= 3'b000;
				vgaGreen <= 3'b000;
				vgaBlue <= 3'b000;
				if(LeftSSDBg)
					begin
					vgaRed <= LeftSSDBgColor[7:5];
					vgaGreen <= LeftSSDBgColor[4:2];
					vgaBlue <= LeftSSDBgColor[1:0];
					end
				if(LeftSSDHit)
					begin
					vgaRed <= LeftSSDColor[7:5];
					vgaGreen <= LeftSSDColor[4:2];
					vgaBlue <= LeftSSDColor[1:0];
					end
			end
		else
			begin
			vgaRed <= 3'b000;
			vgaGreen <= 3'b000;
			vgaBlue <= 3'b000;
			end
	end
	
	assign LeftSSDValue = {Sw[3:0]};
	assign LeftSSDScale = {Sw[7:4]};
	



	



	wire LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7;
	assign {LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7} = 8'b00000000;
	



	



	reg 	[3:0]	SSD;
	wire 	[3:0]	SSD0, SSD1, SSD2, SSD3;
	wire 	[1:0] ssdscan_clk;
	
	assign SSD3 = {2'b00, LeftSSDY[9:8]};
	assign SSD2 = LeftSSDY[7:4];
	assign SSD1 = LeftSSDY[3:0];
	assign SSD0 = LeftSSDValue[3:0];
	


	assign ssdscan_clk = DIV_CLK[19:18];	
	assign An0	= !(~(ssdscan_clk[1]) && ~(ssdscan_clk[0]));
	assign An1	= !(~(ssdscan_clk[1]) &&  (ssdscan_clk[0]));
	assign An2	= !( (ssdscan_clk[1]) && ~(ssdscan_clk[0]));
	assign An3	= !( (ssdscan_clk[1]) &&  (ssdscan_clk[0]));
	
	always @ (ssdscan_clk, SSD0, SSD1, SSD2, SSD3)
	begin : SSD_SCAN_OUT
		case (ssdscan_clk) 
			2'b00:
					SSD = SSD0;
			2'b01:
					SSD = SSD1;
			2'b10:
					SSD = SSD2;
			2'b11:
					SSD = SSD3;
		endcase 
	end	


	reg [6:0]  SSD_CATHODES;
	assign {Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp} = {SSD_CATHODES, 1'b1};

	always @ (SSD) 
	begin : HEX_TO_SSD
		case (SSD)
			4'b0000: SSD_CATHODES = 7'b0000001 ;
			4'b0001: SSD_CATHODES = 7'b1001111 ;
			4'b0010: SSD_CATHODES = 7'b0010010 ;
			4'b0011: SSD_CATHODES = 7'b0000110 ;
			4'b0100: SSD_CATHODES = 7'b1001100 ;
			4'b0101: SSD_CATHODES = 7'b0100100 ;
			4'b0110: SSD_CATHODES = 7'b0100000 ;
			4'b0111: SSD_CATHODES = 7'b0001111 ;
			4'b1000: SSD_CATHODES = 7'b0000000 ;
			4'b1001: SSD_CATHODES = 7'b0000100 ;
			4'b1010: SSD_CATHODES = 7'b0001000 ;
			4'b1011: SSD_CATHODES = 7'b0000000 ;
			4'b1100: SSD_CATHODES = 7'b0110001 ;
			4'b1101: SSD_CATHODES = 7'b0000001 ;
			4'b1110: SSD_CATHODES = 7'b0001000 ;
			4'b1111: SSD_CATHODES = 7'b0111000 ;
			default: SSD_CATHODES = 7'bXXXXXXX ;
		endcase
	end
	



endmodule
module digital_ssd_test_top(ClkPort, vga_h_sync, vga_v_sync, vgaRed, vgaGreen, vgaBlue, btnU, btnD,
	St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar,
	An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp,
	LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7,
	JA, JB,
	Sw);

	input ClkPort, btnU, btnD;
	input [7:0] JA, JB;
	input [7:0] Sw;
	output St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar;
	output vga_h_sync, vga_v_sync, vgaRed, vgaGreen, vgaBlue;
	output An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp;
	output LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7;
	reg [2:0] vgaRed, vgaGreen, vgaBlue;
	


	reg [10:0] LeftSSDX;
	reg [9:0] LeftSSDY;
	wire [3:0] LeftSSDScale;
	
	wire [3:0] LeftSSDValue;
	
	wire LeftSSDHit;
	wire LeftSSDBg;
	
	reg [10:0] RightSSDX;
	reg [9:0] RightSSDY;
	reg [9:0] RightSSDScale;
	
	reg [3:0] RightSSDValue;
	
	wire RightSSDHit;
	
	reg [7:0] LeftSSDColor;
	reg [7:0] LeftSSDBgColor;

	
	

	

	wire	reset, start, ClkPort, board_clk, clk, button_clk;
	
	BUF BUF1 (board_clk, ClkPort); 	
	BUF BUF2 (reset, BtnU);
	BUF BUF3 (start, ~BtnD);
	
	reg [27:0]	DIV_CLK;
	always @ (posedge board_clk, posedge reset)  
	begin : CLOCK_DIVIDER
      if (reset)
			DIV_CLK <= 0;
      else
			DIV_CLK <= DIV_CLK + 1'b1;
	end	

	assign	button_clk = DIV_CLK[18];
	assign	clk = DIV_CLK[1];
	assign 	{St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar} = {5'b11111};
	
	wire inDisplayArea;
	wire [9:0] CounterX;
	wire [9:0] CounterY;

	hvsync_generator syncgen(.clk(clk), .reset(reset),.vga_h_sync(vga_h_sync), .vga_v_sync(vga_v_sync), .inDisplayArea(inDisplayArea), .CounterX(CounterX), .CounterY(CounterY));
	

	digital_ssd LeftSSD(
		.clk(clk),
		.reset(reset),
		.ObjectX(LeftSSDX),
		.ObjectY(LeftSSDY),
		.ObjectScale(LeftSSDScale),
		.Value(LeftSSDValue),
		.PollX(CounterX),
		.PollY(CounterY),
		.Hit(LeftSSDHit),
		.Hit2(LeftSSDBg)
	);
	



	

	always @(posedge DIV_CLK[18])
		begin
		if(reset)
			begin

				LeftSSDX <= 11'd255;
				LeftSSDY <= 10'd220;
				LeftSSDColor <= 8'b11111111;
				LeftSSDBgColor <= 8'b11100000;
			end
		end
	



	

	always @(posedge clk)
	begin
		if(inDisplayArea)
			begin
				vgaRed <= 3'b000;
				vgaGreen <= 3'b000;
				vgaBlue <= 3'b000;
				if(LeftSSDBg)
					begin
					vgaRed <= LeftSSDBgColor[7:5];
					vgaGreen <= LeftSSDBgColor[4:2];
					vgaBlue <= LeftSSDBgColor[1:0];
					end
				if(LeftSSDHit)
					begin
					vgaRed <= LeftSSDColor[7:5];
					vgaGreen <= LeftSSDColor[4:2];
					vgaBlue <= LeftSSDColor[1:0];
					end
			end
		else
			begin
			vgaRed <= 3'b000;
			vgaGreen <= 3'b000;
			vgaBlue <= 3'b000;
			end
	end
	
	assign LeftSSDValue = {Sw[3:0]};
	assign LeftSSDScale = {Sw[7:4]};
	



	



	wire LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7;
	assign {LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7} = 8'b00000000;
	



	



	reg 	[3:0]	SSD;
	wire 	[3:0]	SSD0, SSD1, SSD2, SSD3;
	wire 	[1:0] ssdscan_clk;
	
	assign SSD3 = {2'b00, LeftSSDY[9:8]};
	assign SSD2 = LeftSSDY[7:4];
	assign SSD1 = LeftSSDY[3:0];
	assign SSD0 = LeftSSDValue[3:0];
	


	assign ssdscan_clk = DIV_CLK[19:18];	
	assign An0	= !(~(ssdscan_clk[1]) && ~(ssdscan_clk[0]));
	assign An1	= !(~(ssdscan_clk[1]) &&  (ssdscan_clk[0]));
	assign An2	= !( (ssdscan_clk[1]) && ~(ssdscan_clk[0]));
	assign An3	= !( (ssdscan_clk[1]) &&  (ssdscan_clk[0]));
	
	always @ (ssdscan_clk, SSD0, SSD1, SSD2, SSD3)
	begin : SSD_SCAN_OUT
		case (ssdscan_clk) 
			2'b00:
					SSD = SSD0;
			2'b01:
					SSD = SSD1;
			2'b10:
					SSD = SSD2;
			2'b11:
					SSD = SSD3;
		endcase 
	end	


	reg [6:0]  SSD_CATHODES;
	assign {Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp} = {SSD_CATHODES, 1'b1};

	always @ (SSD) 
	begin : HEX_TO_SSD
		case (SSD)
			4'b0000: SSD_CATHODES = 7'b0000001 ;
			4'b0001: SSD_CATHODES = 7'b1001111 ;
			4'b0010: SSD_CATHODES = 7'b0010010 ;
			4'b0011: SSD_CATHODES = 7'b0000110 ;
			4'b0100: SSD_CATHODES = 7'b1001100 ;
			4'b0101: SSD_CATHODES = 7'b0100100 ;
			4'b0110: SSD_CATHODES = 7'b0100000 ;
			4'b0111: SSD_CATHODES = 7'b0001111 ;
			4'b1000: SSD_CATHODES = 7'b0000000 ;
			4'b1001: SSD_CATHODES = 7'b0000100 ;
			4'b1010: SSD_CATHODES = 7'b0001000 ;
			4'b1011: SSD_CATHODES = 7'b0000000 ;
			4'b1100: SSD_CATHODES = 7'b0110001 ;
			4'b1101: SSD_CATHODES = 7'b0000001 ;
			4'b1110: SSD_CATHODES = 7'b0001000 ;
			4'b1111: SSD_CATHODES = 7'b0111000 ;
			default: SSD_CATHODES = 7'bXXXXXXX ;
		endcase
	end
	



endmodule