data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec_test.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec_test.v:39: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("./vvp.out.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec_test.v:40: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;


   reg [31:0] iB, iA;
   reg [2:0] iALUctrl;
   

   wire [31:0] res;
   wire zero;
   

    ALUexec uut(iA,
                iB,
                iALUctrl,
                res,
                zero);
   initial begin

    #10;
    iB = 32'hDEADBEEF;
    iA = 32'h0;
    #10;
    iALUctrl = 3'b010;
    #10;
    iALUctrl = 3'b110;
    #10;
    iALUctrl = 3'b010;
    #10;
    iALUctrl = 3'b001;
    #10;
    iALUctrl = 3'b111;
    #10;
   end


   initial begin
      $dumpfile("./vvp.out.vcd");
      $dumpvars;
   end

endmodule
module main_test;



   reg [31:0] iB, iA;
   reg [2:0] iALUctrl;
   

   wire [31:0] res;
   wire zero;
   

    ALUexec uut(iA,
                iB,
                iALUctrl,
                res,
                zero);
   initial begin

    #10;
    iB = 32'hDEADBEEF;
    iA = 32'h0;
    #10;
    iALUctrl = 3'b010;
    #10;
    iALUctrl = 3'b110;
    #10;
    iALUctrl = 3'b010;
    #10;
    iALUctrl = 3'b001;
    #10;
    iALUctrl = 3'b111;
    #10;
   end


   initial begin
      $dumpfile("./vvp.out.vcd");
      $dumpvars;
   end

endmodule