data/full_repos/permissive/115074071/src/main/run.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/115074071/src/main/run.v:7: Unsupported: Ignoring delay on this delayed statement.\n        #12 rst = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115074071/src/main/run.v:10: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/115074071/src/main/run.v:12: Cannot find file containing module: \'mips\'\n    mips mips(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/115074071/src/main,data/full_repos/permissive/115074071/mips\n             data/full_repos/permissive/115074071/src/main,data/full_repos/permissive/115074071/mips.v\n             data/full_repos/permissive/115074071/src/main,data/full_repos/permissive/115074071/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module run();
    reg     clk, rst;

    initial begin
        clk = 0;
        rst = 1;
        #12 rst = 0;
    end

    always #10 clk = ~clk;

    mips mips(
        .clk(clk),
        .rst(rst)
    );
endmodule
module run();

    reg     clk, rst;

    initial begin
        clk = 0;
        rst = 1;
        #12 rst = 0;
    end

    always #10 clk = ~clk;

    mips mips(
        .clk(clk),
        .rst(rst)
    );
endmodule