data/full_repos/permissive/210737016/wam_gen.v
1: b'%Error: data/full_repos/permissive/210737016/wam_gen.v:48: Cannot find file containing module: \'wam_par\'\n    wam_par par( .hrdn(hrdn), .age(age), .rto(rto) );\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_par\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_par.v\n             data/full_repos/permissive/210737016,data/full_repos/permissive/210737016/wam_par.sv\n             wam_par\n             wam_par.v\n             wam_par.sv\n             obj_dir/wam_par\n             obj_dir/wam_par.v\n             obj_dir/wam_par.sv\n%Warning-WIDTH: data/full_repos/permissive/210737016/wam_gen.v:84: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'j\' generates 3 bits.\n                                                                 : ... In instance wam_gen\n                            if (j==i) begin                          \n                                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module wam_gen (
    input wire clk_19,
    input wire clr,
    input wire [31:0] clk_cnt,
    input wire [7:0]  hit,
    input wire [3:0]  hrdn,
    output reg [7:0]  holes
    );

    reg  [2:0]  clk_22_cnt;
    reg  [31:0] holes_cnt;
    wire [7:0]  rnum;

    wire [3:0]  age;
    wire [7:0]  rto;

    reg  [2:0]  j;
    integer i;


    wam_par par( .hrdn(hrdn), .age(age), .rto(rto) );


    wam_rdn rdn( .clk(clk_cnt[21]), .load(clr), .seed(~clk_cnt[7:0]), .num(rnum) );


    always @ ( posedge clk_19 or posedge clr ) begin
        if (clr) begin
            holes <= 8'b0;
            holes_cnt <= 32'b0;
            j <= 0;
        end
        else begin
            if (clk_22_cnt < 3'b111) begin
                clk_22_cnt <= clk_22_cnt + 1;
                for (i=0; i<8; i=i+1) begin
                    if (hit[i]) begin
                        holes_cnt[4*i+:4] <= 4'b0000;
                        holes[i] <= 0;
                    end
                end
            end
            else begin
                clk_22_cnt <= 3'b000;
                for (i=0; i<8; i=i+1) begin
                    if (holes[i] > 0) begin
                        if ((holes_cnt[4*i+:4] > age) || hit[i]) begin
                            holes_cnt[4*i+:4] <= 4'b0000;
                            holes[i] <= 0;
                        end
                        else begin
                            holes_cnt[4*i+:4] <= holes_cnt[4*i+:4] + 1;
                        end
                    end
                    else begin
                        if (rnum < rto) begin
                            if (j==i) begin
                                holes_cnt[4*i+:4] <= 4'b0001;
                                holes[i] <= 1;
                            end
                        end
                    end
                end
                j <= j + 1;
            end
        end
    end
endmodule
module wam_gen (
    input wire clk_19,
    input wire clr,
    input wire [31:0] clk_cnt,
    input wire [7:0]  hit,
    input wire [3:0]  hrdn,
    output reg [7:0]  holes
    );


    reg  [2:0]  clk_22_cnt;
    reg  [31:0] holes_cnt;
    wire [7:0]  rnum;

    wire [3:0]  age;
    wire [7:0]  rto;

    reg  [2:0]  j;
    integer i;


    wam_par par( .hrdn(hrdn), .age(age), .rto(rto) );


    wam_rdn rdn( .clk(clk_cnt[21]), .load(clr), .seed(~clk_cnt[7:0]), .num(rnum) );


    always @ ( posedge clk_19 or posedge clr ) begin
        if (clr) begin
            holes <= 8'b0;
            holes_cnt <= 32'b0;
            j <= 0;
        end
        else begin
            if (clk_22_cnt < 3'b111) begin
                clk_22_cnt <= clk_22_cnt + 1;
                for (i=0; i<8; i=i+1) begin
                    if (hit[i]) begin
                        holes_cnt[4*i+:4] <= 4'b0000;
                        holes[i] <= 0;
                    end
                end
            end
            else begin
                clk_22_cnt <= 3'b000;
                for (i=0; i<8; i=i+1) begin
                    if (holes[i] > 0) begin
                        if ((holes_cnt[4*i+:4] > age) || hit[i]) begin
                            holes_cnt[4*i+:4] <= 4'b0000;
                            holes[i] <= 0;
                        end
                        else begin
                            holes_cnt[4*i+:4] <= holes_cnt[4*i+:4] + 1;
                        end
                    end
                    else begin
                        if (rnum < rto) begin
                            if (j==i) begin
                                holes_cnt[4*i+:4] <= 4'b0001;
                                holes[i] <= 1;
                            end
                        end
                    end
                end
                j <= j + 1;
            end
        end
    end
endmodule