data/full_repos/permissive/143278/ivltests/test_mux2to1.v
 line:8: before: "["
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_mux2to1.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #T;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_mux2to1.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #T;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_mux2to1.v:31: Unsupported: Ignoring delay on this delayed statement.\n     #1 if (y != y_check) begin\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_mux2to1.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #S;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_mux2to1.v:11: Operator LT expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'i\' generates 3 bits.\n                                                                            : ... In instance test.stim\n  for (i = 0; i < M; i=i+1) begin\n                ^\n%Error: data/full_repos/permissive/143278/ivltests/test_mux2to1.v:49: Cannot find file containing module: \'mux2to1\'\n  mux2to1          duv   (.i0(i0), .i1(i1), .s(s), .y(y) );\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/mux2to1\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/mux2to1.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/mux2to1.sv\n             mux2to1\n             mux2to1.v\n             mux2to1.sv\n             obj_dir/mux2to1\n             obj_dir/mux2to1.v\n             obj_dir/mux2to1.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stimulus #(parameter M = 8, T = 10) (
                 output reg i0, i1,
                 output reg s
                 );

bit [2:0] i;

initial begin
  for (i = 0; i < M; i=i+1) begin
    #T;
    {i0, i1, s} = i;
  end
  #T;
end


endmodule
module stimulus #(parameter M = 8, T = 10) (
                 output reg i0, i1,
                 output reg s
                 );


bit [2:0] i;

initial begin
  for (i = 0; i < M; i=i+1) begin
    #T;
    {i0, i1, s} = i;
  end
  #T;
end


endmodule