data/full_repos/permissive/129155059/counter/counter.v
data/verilator_xmls/124acbc3-0b11-4c0d-94c5-5b5159a7157e.xml
module counter(out, iclk, ireset);

    parameter WIDTH = 8;

    output [WIDTH-1 : 0] out;
    input                iclk, ireset;

    reg [WIDTH-1 : 0]    out;
    wire                 iclk, ireset;

    always @(posedge iclk)
        out <= out + 1;

    always @(ireset)
        if (ireset)
out = 0;


endmodule
module counter(out, iclk, ireset);


    parameter WIDTH = 8;

    output [WIDTH-1 : 0] out;
    input                iclk, ireset;

    reg [WIDTH-1 : 0]    out;
    wire                 iclk, ireset;

    always @(posedge iclk)
        out <= out + 1;

    always @(ireset)
        if (ireset)
out = 0;


endmodule