data/full_repos/permissive/139213403/FPGA/bin2bcd_testbench.v
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/bin2bcd_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/bin2bcd_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/bin2bcd_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #(T / 2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/bin2bcd_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n   #(T);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/bin2bcd_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #(T);\n    ^\n%Error: data/full_repos/permissive/139213403/FPGA/bin2bcd_testbench.v:52: syntax error, unexpected \'@\'\n  @(negedge reset);\n  ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bin2bcd_testbench;

	localparam BCD_N = 4,
	           BIN_N = 15;
	localparam T = 20;
	
	integer i;
	reg clk, reset, start;
	reg [BIN_N-1:0] bin;
	wire ready, done_tick;
	wire [(4*BCD_N)-1:0] bcd;
	
	bin2bcd #(.BCD_N(BCD_N), .BIN_N(BIN_N-1)) uut(.clk(clk), .reset(reset), .start(start), .sign(bin[BIN_N-1]),
                                               .bin(bin[BIN_N-2:0]), .ready(ready), .done_tick(done_tick), .bcd(bcd));
	

	always
	begin
		clk = 1'b1;
		#(T / 2);
		clk = 1'b0;
		#(T / 2);
	end
	

	initial
	begin
		reset = 1'b1;
		#(T / 2);
		reset = 1'b0;
	end
	
	task bin2bcd_test;
		input reg [BIN_N:0] data;
		begin
			bin = data;
			start = 1'b1;
			#(T);
			start = 1'b0;
			while (!ready)
				#(T);
				
			$display("data=%d bcd=%h", data, bcd);
		end
	endtask
	
	initial
	begin
		start = 1'b0;
		@(negedge reset);
		@(negedge clk);
		
		bin2bcd_test(1234);
		for (i = 0; i <= 16383; i = i + 1000)
			bin2bcd_test(i);
		
		$stop;
	end
endmodule
module bin2bcd_testbench;


	localparam BCD_N = 4,
	           BIN_N = 15;
	localparam T = 20;
	
	integer i;
	reg clk, reset, start;
	reg [BIN_N-1:0] bin;
	wire ready, done_tick;
	wire [(4*BCD_N)-1:0] bcd;
	
	bin2bcd #(.BCD_N(BCD_N), .BIN_N(BIN_N-1)) uut(.clk(clk), .reset(reset), .start(start), .sign(bin[BIN_N-1]),
                                               .bin(bin[BIN_N-2:0]), .ready(ready), .done_tick(done_tick), .bcd(bcd));
	

	always
	begin
		clk = 1'b1;
		#(T / 2);
		clk = 1'b0;
		#(T / 2);
	end
	

	initial
	begin
		reset = 1'b1;
		#(T / 2);
		reset = 1'b0;
	end
	
	task bin2bcd_test;
		input reg [BIN_N:0] data;
		begin
			bin = data;
			start = 1'b1;
			#(T);
			start = 1'b0;
			while (!ready)
				#(T);
				
			$display("data=%d bcd=%h", data, bcd);
		end
	endtask
	
	initial
	begin
		start = 1'b0;
		@(negedge reset);
		@(negedge clk);
		
		bin2bcd_test(1234);
		for (i = 0; i <= 16383; i = i + 1000)
			bin2bcd_test(i);
		
		$stop;
	end
endmodule