data/full_repos/permissive/196070799/src/DelayHandler.v
data/verilator_xmls/ac452250-2b07-4459-8424-39cc8a01550e.xml
module DelayHandler
(
  IN_CLOCK                                                                                  ,
  IN_RESET_N                                                                                ,
  IN_START                                                                                  ,
  IN_CANCEL                                                                                 ,
  IN_COUNTER_VAL                                                                            ,
  OUT_IRQ                                                                                   
);

input                               IN_CLOCK                                                ;
input                               IN_RESET_N                                              ;
input                               IN_START                                                ;
input                               IN_CANCEL                                               ;
input           [31:0]              IN_COUNTER_VAL                                          ;
output                              OUT_IRQ                                                 ;

reg             [31:0]              counter_r                                               ;
reg                                 start_r                                                 ;
reg                                 start_r_d0                                              ;
reg                                 go_r                                                    ;
reg                                 done_r                                                  ;


always @ (posedge IN_CLOCK) begin
  start_r                                           <= IN_START                             ;
  start_r_d0                                        <= start_r                              ;
end


always @ (posedge IN_CLOCK) begin
  if ((!IN_RESET_N) | (IN_CANCEL)) begin
    go_r                                            <= 1'b0                                 ;
  end
  else begin
    if ((start_r == 1'b1) & (start_r_d0 == 1'b0)) begin
      go_r                                          <= 1'b1                                 ;
    end
    else if (counter_r == IN_COUNTER_VAL) begin
      go_r                                          <= 1'b0                                 ;
    end
    else begin
      go_r                                          <= go_r                                 ;
    end
  end
end


always @ (posedge IN_CLOCK) begin
  if ((!IN_RESET_N) | (IN_CANCEL)) begin
    counter_r                                       <= 32'h00000000                         ;
    done_r                                          <= 1'b0                                 ;
  end
  else begin
    if (go_r == 1'b1) begin
      if (counter_r != IN_COUNTER_VAL) begin
        counter_r                                   <= counter_r + 1'b1                     ;
        done_r                                      <= 1'b0                                 ;
      end
      else begin
        counter_r                                   <= counter_r                            ;
        done_r                                      <= 1'b1                                 ;
      end
    end
    else begin
      counter_r                                     <= 32'h00000000                         ;
      done_r                                        <= 1'b0                                 ;
    end
  end
end

assign OUT_IRQ                                      = done_r                                ;

endmodule
module DelayHandler
(
  IN_CLOCK                                                                                  ,
  IN_RESET_N                                                                                ,
  IN_START                                                                                  ,
  IN_CANCEL                                                                                 ,
  IN_COUNTER_VAL                                                                            ,
  OUT_IRQ                                                                                   
);


input                               IN_CLOCK                                                ;
input                               IN_RESET_N                                              ;
input                               IN_START                                                ;
input                               IN_CANCEL                                               ;
input           [31:0]              IN_COUNTER_VAL                                          ;
output                              OUT_IRQ                                                 ;

reg             [31:0]              counter_r                                               ;
reg                                 start_r                                                 ;
reg                                 start_r_d0                                              ;
reg                                 go_r                                                    ;
reg                                 done_r                                                  ;


always @ (posedge IN_CLOCK) begin
  start_r                                           <= IN_START                             ;
  start_r_d0                                        <= start_r                              ;
end


always @ (posedge IN_CLOCK) begin
  if ((!IN_RESET_N) | (IN_CANCEL)) begin
    go_r                                            <= 1'b0                                 ;
  end
  else begin
    if ((start_r == 1'b1) & (start_r_d0 == 1'b0)) begin
      go_r                                          <= 1'b1                                 ;
    end
    else if (counter_r == IN_COUNTER_VAL) begin
      go_r                                          <= 1'b0                                 ;
    end
    else begin
      go_r                                          <= go_r                                 ;
    end
  end
end


always @ (posedge IN_CLOCK) begin
  if ((!IN_RESET_N) | (IN_CANCEL)) begin
    counter_r                                       <= 32'h00000000                         ;
    done_r                                          <= 1'b0                                 ;
  end
  else begin
    if (go_r == 1'b1) begin
      if (counter_r != IN_COUNTER_VAL) begin
        counter_r                                   <= counter_r + 1'b1                     ;
        done_r                                      <= 1'b0                                 ;
      end
      else begin
        counter_r                                   <= counter_r                            ;
        done_r                                      <= 1'b1                                 ;
      end
    end
    else begin
      counter_r                                     <= 32'h00000000                         ;
      done_r                                        <= 1'b0                                 ;
    end
  end
end

assign OUT_IRQ                                      = done_r                                ;

endmodule