data/full_repos/permissive/104443190/chen_div.v
 line:13: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:14: Unsupported: Ignoring delay on this delayed statement.\n initial #30 rst=1;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:15: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n       ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function [31:0] unsignedtosigned; 
	   input [31:0] x;
	   input sign;  
	   begin
	   		unsignedtosigned = sign?~x+1'b1:x;
	   end
	endfunction
function [31:0] unsignedtosigned;
 
	   input [31:0] x;
	   input sign;  
	   begin
	   		unsignedtosigned = sign?~x+1'b1:x;
	   end
	endfunction