data/full_repos/permissive/168753118/testbench/modules/PIPELINE/PIPELINE_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/168753118/testbench/modules/PIPELINE/PIPELINE_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/168753118/testbench/modules/PIPELINE/PIPELINE_tb.v:245: Unsupported: Ignoring delay on this delayed statement.\n        #period; pipeline_clock_in = !pipeline_clock_in;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/168753118/testbench/modules/PIPELINE/PIPELINE_tb.v:246: Unsupported: Ignoring delay on this delayed statement.\n        #period; pipeline_clock_in = !pipeline_clock_in;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/168753118/testbench/modules/PIPELINE/PIPELINE_tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Error: data/full_repos/permissive/168753118/testbench/modules/PIPELINE/PIPELINE_tb.v:275: syntax error, unexpected \'@\'\n   @eachvec;\n   ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PIPELINE_tb;


	parameter XLEN = 32;


	reg eachvec;


  reg pipeline_clock_in;


	reg pipeline_reset_in;
	reg pipeline_bru_correction_flag_in;
	reg pipeline_check_correction_flag_in;
	reg pipeline_ins_mem_ready_in;
  reg pipeline_data_mem_valid_in;
  reg pipeline_data_mem_ready_in;
  reg pipeline_invalid_ins_in;


	reg pipeline_ins_mem_valid_golden;
  reg pipeline_pc_if_set_golden;
  reg pipeline_if_dec_set_golden;
  reg pipeline_dec_reg_set_golden;
  reg pipeline_reg_ex_set_golden;
  reg pipeline_ex_wb_set_golden;
  reg pipeline_pc_if_clear_golden;
  reg pipeline_if_dec_clear_golden;
  reg pipeline_dec_reg_clear_golden;
  reg pipeline_reg_ex_clear_golden;
  reg pipeline_ex_wb_clear_golden;


	reg pipeline_ins_mem_valid_result;
  reg pipeline_pc_if_set_result;
  reg pipeline_if_dec_set_result;
  reg pipeline_dec_reg_set_result;
  reg pipeline_reg_ex_set_result;
  reg pipeline_ex_wb_set_result;
  reg pipeline_pc_if_clear_result;
  reg pipeline_if_dec_clear_result;
  reg pipeline_dec_reg_clear_result;
  reg pipeline_reg_ex_clear_result;
  reg pipeline_ex_wb_clear_result;


	wire pipeline_ins_mem_valid_out;
  wire pipeline_pc_if_set_out;
  wire pipeline_if_dec_set_out;
  wire pipeline_dec_reg_set_out;
  wire pipeline_reg_ex_set_out;
  wire pipeline_ex_wb_set_out;
  wire pipeline_pc_if_clear_out;
  wire pipeline_if_dec_clear_out;
  wire pipeline_dec_reg_clear_out;
  wire pipeline_reg_ex_clear_out;
  wire pipeline_ex_wb_clear_out;


	localparam period = 5;


	integer golden, inputs, results, status;


	PIPELINE_CONTROL pipeline_ctrl (
		.pipeline_clock_in(pipeline_clock_in),
    .pipeline_reset_in(pipeline_reset_in),
    .pipeline_bru_correction_flag_in(pipeline_bru_correction_flag_in),
    .pipeline_check_correction_flag_in(pipeline_check_correction_flag_in),
    .pipeline_ins_mem_ready_in(pipeline_ins_mem_ready_in),
    .pipeline_ins_mem_valid_out(pipeline_ins_mem_valid_out),
    .pipeline_data_mem_valid_in(pipeline_data_mem_valid_in),
    .pipeline_data_mem_ready_in(pipeline_data_mem_ready_in),
    .pipeline_invalid_ins_in(pipeline_invalid_ins_in),
    .pipeline_pc_if_set_out(pipeline_pc_if_set_out),
    .pipeline_if_dec_set_out(pipeline_if_dec_set_out),
    .pipeline_dec_reg_set_out(pipeline_dec_reg_set_out),
    .pipeline_reg_ex_set_out(pipeline_reg_ex_set_out),
    .pipeline_ex_wb_set_out(pipeline_ex_wb_set_out),
    .pipeline_pc_if_clear_out(pipeline_pc_if_clear_out),
    .pipeline_if_dec_clear_out(pipeline_if_dec_clear_out),
    .pipeline_dec_reg_clear_out(pipeline_dec_reg_clear_out),
    .pipeline_reg_ex_clear_out(pipeline_reg_ex_clear_out),
    .pipeline_ex_wb_clear_out(pipeline_ex_wb_clear_out)
	);

  initial begin


			$display("Opening golden file");
			golden = $fopen("./out/PIPELINE_outputs.txt", "r");


			$display("Opening inputs file");
			inputs = $fopen("./out/PIPELINE_inputs.txt", "r");


			$display("Opening results file");
			results = $fopen("./out/PIPELINE_results.txt", "w");


			if (golden == `NULL) begin
				$display("Golden file was NULL");
				$finish;
			end


			if(inputs == `NULL) begin
				$display("Inputs file was NULL");
			end


			if(results == `NULL) begin
				$display("Results file was NULL");
			end

      pipeline_clock_in = 1'b0;


			while(!$feof(golden)) begin


				status = $fscanf(
					inputs,
					"%d %d %d %d %d %d %d",
          pipeline_reset_in,
          pipeline_bru_correction_flag_in,
          pipeline_check_correction_flag_in,
          pipeline_ins_mem_ready_in,
          pipeline_data_mem_valid_in,
          pipeline_data_mem_ready_in,
          pipeline_invalid_ins_in
				);


				status = $fscanf(
					golden,
					"%d %d %d %d %d %d %d %d %d %d %d",
					pipeline_ins_mem_valid_golden,
          pipeline_pc_if_set_golden,
          pipeline_if_dec_set_golden,
          pipeline_dec_reg_set_golden,
          pipeline_reg_ex_set_golden,
          pipeline_ex_wb_set_golden,
          pipeline_pc_if_clear_golden,
          pipeline_if_dec_clear_golden,
          pipeline_dec_reg_clear_golden,
          pipeline_reg_ex_clear_golden,
          pipeline_ex_wb_clear_golden
				);





        #period;


				if (pipeline_ins_mem_valid_out == pipeline_ins_mem_valid_golden)
					pipeline_ins_mem_valid_result = 1'b1;
				else begin
					pipeline_ins_mem_valid_result = 1'b0;
          $display("State: %d", pipeline_ctrl.ins_mem_state);
          $display("%d %d", pipeline_ins_mem_valid_out, pipeline_ins_mem_valid_golden);
        end

				if (pipeline_pc_if_set_out == pipeline_pc_if_set_golden)
					pipeline_pc_if_set_result = 1'b1;
				else
					pipeline_pc_if_set_result = 1'b0;

        if (pipeline_if_dec_set_out == pipeline_if_dec_set_golden)
					pipeline_if_dec_set_result = 1'b1;
				else
					pipeline_if_dec_set_result = 1'b0;

        if (pipeline_dec_reg_set_out == pipeline_dec_reg_set_golden)
					pipeline_dec_reg_set_result = 1'b1;
				else begin
					pipeline_dec_reg_set_result = 1'b0;
        end

        if (pipeline_reg_ex_set_out == pipeline_reg_ex_set_golden)
					pipeline_reg_ex_set_result = 1'b1;
				else begin
					pipeline_reg_ex_set_result = 1'b0;
        end

        if (pipeline_ex_wb_set_out == pipeline_ex_wb_set_golden)
					pipeline_ex_wb_set_result = 1'b1;
				else
					pipeline_ex_wb_set_result = 1'b0;


        if (pipeline_pc_if_clear_out == pipeline_pc_if_clear_golden)
					pipeline_pc_if_clear_result = 1'b1;
				else begin
					pipeline_pc_if_clear_result = 1'b0;
          $display("ERROR PC/IF");
        end

        if (pipeline_if_dec_clear_out == pipeline_if_dec_clear_golden)
					pipeline_if_dec_clear_result = 1'b1;
				else begin
					pipeline_if_dec_clear_result = 1'b0;
          $display("ERROR IF/DEC");
        end

        if (pipeline_dec_reg_clear_out == pipeline_dec_reg_clear_golden)
					pipeline_dec_reg_clear_result = 1'b1;
				else begin
					pipeline_dec_reg_clear_result = 1'b0;
          $display("ERROR DEC/REG");
        end

        if (pipeline_reg_ex_clear_out == pipeline_reg_ex_clear_golden)
					pipeline_reg_ex_clear_result = 1'b1;
				else begin
					pipeline_reg_ex_clear_result = 1'b0;
          $display("ERROR REG/EX");
        end

        if (pipeline_ex_wb_clear_out == pipeline_ex_wb_clear_golden)
					pipeline_ex_wb_clear_result = 1'b1;
				else begin
					pipeline_ex_wb_clear_result = 1'b0;
          $display("ERROR EX/WB");
          $display("C: %d G: %d", pipeline_ex_wb_clear_out, pipeline_ex_wb_clear_golden);
        end


        #period; pipeline_clock_in = !pipeline_clock_in;
        #period; pipeline_clock_in = !pipeline_clock_in;

        #period;


				$fwrite(
					results,
					"%d %d %d %d %d %d %d %d %d %d %d\n",
					pipeline_ins_mem_valid_result,
					pipeline_pc_if_set_result,
          pipeline_if_dec_set_result,
          pipeline_dec_reg_set_result,
          pipeline_reg_ex_set_result,
          pipeline_ex_wb_set_result,
          pipeline_pc_if_clear_result,
          pipeline_if_dec_clear_result,
          pipeline_dec_reg_clear_result,
          pipeline_reg_ex_clear_result,
          pipeline_ex_wb_clear_result
				);

			end

			$display("Simulation has ended");

			$fclose(golden);
			$fclose(inputs);
			$fclose(results);

			@eachvec;
			$finish;

		end
endmodule
module PIPELINE_tb;



	parameter XLEN = 32;


	reg eachvec;


  reg pipeline_clock_in;


	reg pipeline_reset_in;
	reg pipeline_bru_correction_flag_in;
	reg pipeline_check_correction_flag_in;
	reg pipeline_ins_mem_ready_in;
  reg pipeline_data_mem_valid_in;
  reg pipeline_data_mem_ready_in;
  reg pipeline_invalid_ins_in;


	reg pipeline_ins_mem_valid_golden;
  reg pipeline_pc_if_set_golden;
  reg pipeline_if_dec_set_golden;
  reg pipeline_dec_reg_set_golden;
  reg pipeline_reg_ex_set_golden;
  reg pipeline_ex_wb_set_golden;
  reg pipeline_pc_if_clear_golden;
  reg pipeline_if_dec_clear_golden;
  reg pipeline_dec_reg_clear_golden;
  reg pipeline_reg_ex_clear_golden;
  reg pipeline_ex_wb_clear_golden;


	reg pipeline_ins_mem_valid_result;
  reg pipeline_pc_if_set_result;
  reg pipeline_if_dec_set_result;
  reg pipeline_dec_reg_set_result;
  reg pipeline_reg_ex_set_result;
  reg pipeline_ex_wb_set_result;
  reg pipeline_pc_if_clear_result;
  reg pipeline_if_dec_clear_result;
  reg pipeline_dec_reg_clear_result;
  reg pipeline_reg_ex_clear_result;
  reg pipeline_ex_wb_clear_result;


	wire pipeline_ins_mem_valid_out;
  wire pipeline_pc_if_set_out;
  wire pipeline_if_dec_set_out;
  wire pipeline_dec_reg_set_out;
  wire pipeline_reg_ex_set_out;
  wire pipeline_ex_wb_set_out;
  wire pipeline_pc_if_clear_out;
  wire pipeline_if_dec_clear_out;
  wire pipeline_dec_reg_clear_out;
  wire pipeline_reg_ex_clear_out;
  wire pipeline_ex_wb_clear_out;


	localparam period = 5;


	integer golden, inputs, results, status;


	PIPELINE_CONTROL pipeline_ctrl (
		.pipeline_clock_in(pipeline_clock_in),
    .pipeline_reset_in(pipeline_reset_in),
    .pipeline_bru_correction_flag_in(pipeline_bru_correction_flag_in),
    .pipeline_check_correction_flag_in(pipeline_check_correction_flag_in),
    .pipeline_ins_mem_ready_in(pipeline_ins_mem_ready_in),
    .pipeline_ins_mem_valid_out(pipeline_ins_mem_valid_out),
    .pipeline_data_mem_valid_in(pipeline_data_mem_valid_in),
    .pipeline_data_mem_ready_in(pipeline_data_mem_ready_in),
    .pipeline_invalid_ins_in(pipeline_invalid_ins_in),
    .pipeline_pc_if_set_out(pipeline_pc_if_set_out),
    .pipeline_if_dec_set_out(pipeline_if_dec_set_out),
    .pipeline_dec_reg_set_out(pipeline_dec_reg_set_out),
    .pipeline_reg_ex_set_out(pipeline_reg_ex_set_out),
    .pipeline_ex_wb_set_out(pipeline_ex_wb_set_out),
    .pipeline_pc_if_clear_out(pipeline_pc_if_clear_out),
    .pipeline_if_dec_clear_out(pipeline_if_dec_clear_out),
    .pipeline_dec_reg_clear_out(pipeline_dec_reg_clear_out),
    .pipeline_reg_ex_clear_out(pipeline_reg_ex_clear_out),
    .pipeline_ex_wb_clear_out(pipeline_ex_wb_clear_out)
	);

  initial begin


			$display("Opening golden file");
			golden = $fopen("./out/PIPELINE_outputs.txt", "r");


			$display("Opening inputs file");
			inputs = $fopen("./out/PIPELINE_inputs.txt", "r");


			$display("Opening results file");
			results = $fopen("./out/PIPELINE_results.txt", "w");


			if (golden == `NULL) begin
				$display("Golden file was NULL");
				$finish;
			end


			if(inputs == `NULL) begin
				$display("Inputs file was NULL");
			end


			if(results == `NULL) begin
				$display("Results file was NULL");
			end

      pipeline_clock_in = 1'b0;


			while(!$feof(golden)) begin


				status = $fscanf(
					inputs,
					"%d %d %d %d %d %d %d",
          pipeline_reset_in,
          pipeline_bru_correction_flag_in,
          pipeline_check_correction_flag_in,
          pipeline_ins_mem_ready_in,
          pipeline_data_mem_valid_in,
          pipeline_data_mem_ready_in,
          pipeline_invalid_ins_in
				);


				status = $fscanf(
					golden,
					"%d %d %d %d %d %d %d %d %d %d %d",
					pipeline_ins_mem_valid_golden,
          pipeline_pc_if_set_golden,
          pipeline_if_dec_set_golden,
          pipeline_dec_reg_set_golden,
          pipeline_reg_ex_set_golden,
          pipeline_ex_wb_set_golden,
          pipeline_pc_if_clear_golden,
          pipeline_if_dec_clear_golden,
          pipeline_dec_reg_clear_golden,
          pipeline_reg_ex_clear_golden,
          pipeline_ex_wb_clear_golden
				);





        #period;


				if (pipeline_ins_mem_valid_out == pipeline_ins_mem_valid_golden)
					pipeline_ins_mem_valid_result = 1'b1;
				else begin
					pipeline_ins_mem_valid_result = 1'b0;
          $display("State: %d", pipeline_ctrl.ins_mem_state);
          $display("%d %d", pipeline_ins_mem_valid_out, pipeline_ins_mem_valid_golden);
        end

				if (pipeline_pc_if_set_out == pipeline_pc_if_set_golden)
					pipeline_pc_if_set_result = 1'b1;
				else
					pipeline_pc_if_set_result = 1'b0;

        if (pipeline_if_dec_set_out == pipeline_if_dec_set_golden)
					pipeline_if_dec_set_result = 1'b1;
				else
					pipeline_if_dec_set_result = 1'b0;

        if (pipeline_dec_reg_set_out == pipeline_dec_reg_set_golden)
					pipeline_dec_reg_set_result = 1'b1;
				else begin
					pipeline_dec_reg_set_result = 1'b0;
        end

        if (pipeline_reg_ex_set_out == pipeline_reg_ex_set_golden)
					pipeline_reg_ex_set_result = 1'b1;
				else begin
					pipeline_reg_ex_set_result = 1'b0;
        end

        if (pipeline_ex_wb_set_out == pipeline_ex_wb_set_golden)
					pipeline_ex_wb_set_result = 1'b1;
				else
					pipeline_ex_wb_set_result = 1'b0;


        if (pipeline_pc_if_clear_out == pipeline_pc_if_clear_golden)
					pipeline_pc_if_clear_result = 1'b1;
				else begin
					pipeline_pc_if_clear_result = 1'b0;
          $display("ERROR PC/IF");
        end

        if (pipeline_if_dec_clear_out == pipeline_if_dec_clear_golden)
					pipeline_if_dec_clear_result = 1'b1;
				else begin
					pipeline_if_dec_clear_result = 1'b0;
          $display("ERROR IF/DEC");
        end

        if (pipeline_dec_reg_clear_out == pipeline_dec_reg_clear_golden)
					pipeline_dec_reg_clear_result = 1'b1;
				else begin
					pipeline_dec_reg_clear_result = 1'b0;
          $display("ERROR DEC/REG");
        end

        if (pipeline_reg_ex_clear_out == pipeline_reg_ex_clear_golden)
					pipeline_reg_ex_clear_result = 1'b1;
				else begin
					pipeline_reg_ex_clear_result = 1'b0;
          $display("ERROR REG/EX");
        end

        if (pipeline_ex_wb_clear_out == pipeline_ex_wb_clear_golden)
					pipeline_ex_wb_clear_result = 1'b1;
				else begin
					pipeline_ex_wb_clear_result = 1'b0;
          $display("ERROR EX/WB");
          $display("C: %d G: %d", pipeline_ex_wb_clear_out, pipeline_ex_wb_clear_golden);
        end


        #period; pipeline_clock_in = !pipeline_clock_in;
        #period; pipeline_clock_in = !pipeline_clock_in;

        #period;


				$fwrite(
					results,
					"%d %d %d %d %d %d %d %d %d %d %d\n",
					pipeline_ins_mem_valid_result,
					pipeline_pc_if_set_result,
          pipeline_if_dec_set_result,
          pipeline_dec_reg_set_result,
          pipeline_reg_ex_set_result,
          pipeline_ex_wb_set_result,
          pipeline_pc_if_clear_result,
          pipeline_if_dec_clear_result,
          pipeline_dec_reg_clear_result,
          pipeline_reg_ex_clear_result,
          pipeline_ex_wb_clear_result
				);

			end

			$display("Simulation has ended");

			$fclose(golden);
			$fclose(inputs);
			$fclose(results);

			@eachvec;
			$finish;

		end
endmodule