data/full_repos/permissive/120518070/main/source/RC4_gen_pseudo_rand_module.sv
1: b"%Error: data/full_repos/permissive/120518070/main/source/RC4_gen_pseudo_rand_module.sv:48: Cannot find file containing module: 'RC4_pseudo_rand_comb'\n RC4_pseudo_rand_comb RC4_PSEUDO_RAND_COMB (.clk(clk),.locSafe_i(locSafe),.counterI_i(counterI),.clearCounterJ_i(clearCouterJ),\n ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/RC4_pseudo_rand_comb\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/RC4_pseudo_rand_comb.v\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/RC4_pseudo_rand_comb.sv\n             RC4_pseudo_rand_comb\n             RC4_pseudo_rand_comb.v\n             RC4_pseudo_rand_comb.sv\n             obj_dir/RC4_pseudo_rand_comb\n             obj_dir/RC4_pseudo_rand_comb.v\n             obj_dir/RC4_pseudo_rand_comb.sv\n%Error: data/full_repos/permissive/120518070/main/source/RC4_gen_pseudo_rand_module.sv:53: Cannot find file containing module: 'RC4_gen_ps_state'\n RC4_gen_ps_state RC4_GEN_PS_STATE (.clk(clk),.n_rst_i(n_rst),.genStateArr_i(genStateArr_i),.genVal_i(genVal_i),.counterI_i(counterI),.sarrGenerated_o(sarrGenerated_o_),\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120518070/main/source/RC4_gen_pseudo_rand_module.sv:58: Cannot find file containing module: 'sarr'\n sarr SARR (.clk(clk),.waddr_i(waddr),.wdata_i(wData),.swap_i(swap),.wenable_i(write_enable),.renable_i(read_enable),.raddr_i(raddr),.rdata_o(rdata));\n ^~~~\n%Error: data/full_repos/permissive/120518070/main/source/RC4_gen_pseudo_rand_module.sv:63: Cannot find file containing module: 'counterI'\n counterI COUNTERI \n ^~~~~~~~\n%Error: data/full_repos/permissive/120518070/main/source/RC4_gen_pseudo_rand_module.sv:75: Cannot find file containing module: 'locSafe'\n locSafe LOCSAFE(\n ^~~~~~~\n%Error: data/full_repos/permissive/120518070/main/source/RC4_gen_pseudo_rand_module.sv:82: Cannot find file containing module: 'temp'\n temp TEMP(\n ^~~~\n%Error: data/full_repos/permissive/120518070/main/source/RC4_gen_pseudo_rand_module.sv:89: Cannot find file containing module: 'outputToXor'\n outputToXor OUTPUTTOXOR(\n ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module RC4_gen_pseudo_rand_module(
	input wire clk,
	input wire n_rst,
	input wire genStateArr_i,
	input wire genVal_i,
	input wire [31:0] rc4_key_i_,
	output reg [7:0] outputToXor_o,
	output reg sarrGenerated_o_,
	output reg valReady_o_
);


	wire [7:0] locSafe;
	wire [7:0] counterJ;
	wire [7:0] counterI;
	wire clearCouterJ;
	wire det_j_2;
	wire det_j;

	wire gen_final;
	wire end_;
	wire swap_1;
	wire store_temp;
	wire val_init;
	wire [7:0] temp;
	wire [7:0] rdata;
	wire [7:0] locEnd;
	wire store_loc;
	wire [7:0] ncouterJ;
	wire [7:0] raddr;
	wire [7:0] wData;
	wire [7:0] waddr;
	wire swap;
	wire read_enable;
	wire write_enable;
	wire clear_i;
	wire enable_counterI;


	RC4_pseudo_rand_comb RC4_PSEUDO_RAND_COMB (.clk(clk),.locSafe_i(locSafe),.counterI_i(counterI),.clearCounterJ_i(clearCouterJ),
				  .det_j_2_i(det_j_2),.det_j_i(det_j),.valReady_i(valReady_o_),.gen_final_i(gen_final),.end_i(end_),.swap_i(swap_1),.store_temp_i(store_temp),
				  .val_init_i(val_init),.rc4_key_i(rc4_key_i_),.temp_i(temp),.rdata_i(rdata),.locEnd_o(locEnd),.store_loc_o(store_loc),.raddr_o(raddr),
				  .wData_o(wData),.waddr_o(waddr),.swap_o(swap),.read_enable_o(read_enable),.write_enable_o(write_enable));

	RC4_gen_ps_state RC4_GEN_PS_STATE (.clk(clk),.n_rst_i(n_rst),.genStateArr_i(genStateArr_i),.genVal_i(genVal_i),.counterI_i(counterI),.sarrGenerated_o(sarrGenerated_o_),
				.valReady_o(valReady_o_),.clearCounterJ_o(clearCouterJ),.clear_i_o(clear_i),.enable_counterI_o(enable_counterI),
				.det_j_o(det_j),.swap_o(swap_1),.det_j_2_o(det_j_2),.store_temp_o(store_temp),.end_o(end_),
				.gen_final_o(gen_final),.val_init_o(val_init));

	sarr SARR (.clk(clk),.waddr_i(waddr),.wdata_i(wData),.swap_i(swap),.wenable_i(write_enable),.renable_i(read_enable),.raddr_i(raddr),.rdata_o(rdata));




	counterI COUNTERI 
	(
  		.clk          (clk),
  		.n_rst        (n_rst),
  		.clear        (clear_i),
  		.count_enable (enable_counterI),
  		.rollover_val (8'b11111111),
  		.count_out    (counterI),
  		.rollover_flag()
  	);


	locSafe LOCSAFE(
		.clk(clk),
		.locEnd_i(locEnd),
		.store_loc_i(store_loc),
		.locSafe_o(locSafe)
	);

	temp TEMP(
		.clk(clk),
		.rdata_i(rdata),
		.store_temp_i(store_temp),
		.temp_o(temp)
	);

	outputToXor OUTPUTTOXOR(
		.clk(clk),
		.rdata_i(rdata),
		.end_i(end_),
		.outputToXor_o(outputToXor_o)
	);

endmodule
module RC4_gen_pseudo_rand_module(
	input wire clk,
	input wire n_rst,
	input wire genStateArr_i,
	input wire genVal_i,
	input wire [31:0] rc4_key_i_,
	output reg [7:0] outputToXor_o,
	output reg sarrGenerated_o_,
	output reg valReady_o_
);



	wire [7:0] locSafe;
	wire [7:0] counterJ;
	wire [7:0] counterI;
	wire clearCouterJ;
	wire det_j_2;
	wire det_j;

	wire gen_final;
	wire end_;
	wire swap_1;
	wire store_temp;
	wire val_init;
	wire [7:0] temp;
	wire [7:0] rdata;
	wire [7:0] locEnd;
	wire store_loc;
	wire [7:0] ncouterJ;
	wire [7:0] raddr;
	wire [7:0] wData;
	wire [7:0] waddr;
	wire swap;
	wire read_enable;
	wire write_enable;
	wire clear_i;
	wire enable_counterI;


	RC4_pseudo_rand_comb RC4_PSEUDO_RAND_COMB (.clk(clk),.locSafe_i(locSafe),.counterI_i(counterI),.clearCounterJ_i(clearCouterJ),
				  .det_j_2_i(det_j_2),.det_j_i(det_j),.valReady_i(valReady_o_),.gen_final_i(gen_final),.end_i(end_),.swap_i(swap_1),.store_temp_i(store_temp),
				  .val_init_i(val_init),.rc4_key_i(rc4_key_i_),.temp_i(temp),.rdata_i(rdata),.locEnd_o(locEnd),.store_loc_o(store_loc),.raddr_o(raddr),
				  .wData_o(wData),.waddr_o(waddr),.swap_o(swap),.read_enable_o(read_enable),.write_enable_o(write_enable));

	RC4_gen_ps_state RC4_GEN_PS_STATE (.clk(clk),.n_rst_i(n_rst),.genStateArr_i(genStateArr_i),.genVal_i(genVal_i),.counterI_i(counterI),.sarrGenerated_o(sarrGenerated_o_),
				.valReady_o(valReady_o_),.clearCounterJ_o(clearCouterJ),.clear_i_o(clear_i),.enable_counterI_o(enable_counterI),
				.det_j_o(det_j),.swap_o(swap_1),.det_j_2_o(det_j_2),.store_temp_o(store_temp),.end_o(end_),
				.gen_final_o(gen_final),.val_init_o(val_init));

	sarr SARR (.clk(clk),.waddr_i(waddr),.wdata_i(wData),.swap_i(swap),.wenable_i(write_enable),.renable_i(read_enable),.raddr_i(raddr),.rdata_o(rdata));




	counterI COUNTERI 
	(
  		.clk          (clk),
  		.n_rst        (n_rst),
  		.clear        (clear_i),
  		.count_enable (enable_counterI),
  		.rollover_val (8'b11111111),
  		.count_out    (counterI),
  		.rollover_flag()
  	);


	locSafe LOCSAFE(
		.clk(clk),
		.locEnd_i(locEnd),
		.store_loc_i(store_loc),
		.locSafe_o(locSafe)
	);

	temp TEMP(
		.clk(clk),
		.rdata_i(rdata),
		.store_temp_i(store_temp),
		.temp_o(temp)
	);

	outputToXor OUTPUTTOXOR(
		.clk(clk),
		.rdata_i(rdata),
		.end_i(end_),
		.outputToXor_o(outputToXor_o)
	);

endmodule