data/full_repos/permissive/173670949/shiftreg/top.v
1: b'%Error: data/full_repos/permissive/173670949/shiftreg/top.v:15: Cannot find include file: vfd_bits.v\n    `include "vfd_bits.v" \n             ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173670949/shiftreg,data/full_repos/permissive/173670949/vfd_bits.v\n             data/full_repos/permissive/173670949/shiftreg,data/full_repos/permissive/173670949/vfd_bits.v.v\n             data/full_repos/permissive/173670949/shiftreg,data/full_repos/permissive/173670949/vfd_bits.v.sv\n             vfd_bits.v\n             vfd_bits.v.v\n             vfd_bits.v.sv\n             obj_dir/vfd_bits.v\n             obj_dir/vfd_bits.v.v\n             obj_dir/vfd_bits.v.sv\n%Error: Exiting due to 1 error(s)\n'
module top(
    input  ICE_CLK,
    output SHIFT_LATCH,
    output SHIFT_CLOCK,
    output SHIFT_DATA,
    output GLED5,
    output RLED1,
    output RLED2,
    output RLED3,
    output RLED4
);
    `include "vfd_bits.v"

    parameter DISPLAY_BITS = 32;

    reg [DISPLAY_BITS-1:0] vfd_data   = 0;
    reg                    data_valid = 1;
    wire                   shift_busy;

    always @(posedge ICE_CLK) begin
        if (!shift_busy && !data_valid) begin
            vfd_data   <= vfd_data + 1;
            data_valid <= 1;
        end
        else begin
            data_valid <= 0;
        end
    end

    shiftout #(
        .FREQUENCY(1_000_000), .DATA_WIDTH(DISPLAY_BITS)
    ) shitfout_inst (
        ICE_CLK, ~vfd_data, data_valid, SHIFT_LATCH, SHIFT_CLOCK, SHIFT_DATA, shift_busy
    );

    assign GLED5 = !shift_busy;
    assign RLED1 = SHIFT_CLOCK;
    assign RLED2 = SHIFT_LATCH;
    assign RLED3 = data_valid;
    assign RLED4 = SHIFT_DATA;

endmodule
module top(
    input  ICE_CLK,
    output SHIFT_LATCH,
    output SHIFT_CLOCK,
    output SHIFT_DATA,
    output GLED5,
    output RLED1,
    output RLED2,
    output RLED3,
    output RLED4
);

    `include "vfd_bits.v"

    parameter DISPLAY_BITS = 32;

    reg [DISPLAY_BITS-1:0] vfd_data   = 0;
    reg                    data_valid = 1;
    wire                   shift_busy;

    always @(posedge ICE_CLK) begin
        if (!shift_busy && !data_valid) begin
            vfd_data   <= vfd_data + 1;
            data_valid <= 1;
        end
        else begin
            data_valid <= 0;
        end
    end

    shiftout #(
        .FREQUENCY(1_000_000), .DATA_WIDTH(DISPLAY_BITS)
    ) shitfout_inst (
        ICE_CLK, ~vfd_data, data_valid, SHIFT_LATCH, SHIFT_CLOCK, SHIFT_DATA, shift_busy
    );

    assign GLED5 = !shift_busy;
    assign RLED1 = SHIFT_CLOCK;
    assign RLED2 = SHIFT_LATCH;
    assign RLED3 = data_valid;
    assign RLED4 = SHIFT_DATA;

endmodule