data/full_repos/permissive/220229160/sdc-plugin/tests/restore_from_json/restore_from_json.v
data/verilator_xmls/bd4ca6e9-6a99-4023-921a-865b309622a4.xml
module top (
    input  clk,
    input  i,
    output o
);

  reg [0:0] outff = 0;

  assign o = outff;

  always @(posedge clk) begin
    outff <= i;
  end

endmodule
module top (
    input  clk,
    input  i,
    output o
);


  reg [0:0] outff = 0;

  assign o = outff;

  always @(posedge clk) begin
    outff <= i;
  end

endmodule