data/full_repos/permissive/152986713/ice40/ram.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/152986713/ice40/ram.v:37: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'RAM_sync\'\nmodule RAM_sync(clk, addr, din, dout, we);\n       ^~~~~~~~\n                                                                      : ... Top module \'RAM_async\'\nmodule RAM_async(clk, addr, din, dout, we);\n       ^~~~~~~~~\n                                                                      : ... Top module \'RAM_async_tristate\'\nmodule RAM_async_tristate(clk, addr, data, we);\n       ^~~~~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/ram.v:32: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'dout\'\n                                                                       : ... In instance RAM_sync\n    dout <= mem[addr];  \n    ^~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module RAM_async(clk, addr, din, dout, we);
  
  parameter A = 10;
  parameter D = 8;
  
  input  clk;
  input  [A-1:0] addr;
  input  [D-1:0] din;
  output [D-1:0] dout;
  input  we;
  
  reg [D-1:0] mem [0:(1<<A)-1];
  
  always @(posedge clk) begin
    if (we)
      mem[addr] <= din;
  end

  assign dout = mem[addr];

endmodule
module RAM_async(clk, addr, din, dout, we);

  
  parameter A = 10;
  parameter D = 8;
  
  input  clk;
  input  [A-1:0] addr;
  input  [D-1:0] din;
  output [D-1:0] dout;
  input  we;
  
  reg [D-1:0] mem [0:(1<<A)-1];
  
  always @(posedge clk) begin
    if (we)
      mem[addr] <= din;
  end

  assign dout = mem[addr];

endmodule