data/full_repos/permissive/156721532/UART/setupSystem.v
1: b"%Error: data/full_repos/permissive/156721532/UART/setupSystem.v:12: Cannot find file containing module: 'system'\n system systemUnit(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156721532/UART,data/full_repos/permissive/156721532/system\n             data/full_repos/permissive/156721532/UART,data/full_repos/permissive/156721532/system.v\n             data/full_repos/permissive/156721532/UART,data/full_repos/permissive/156721532/system.sv\n             system\n             system.v\n             system.sv\n             obj_dir/system\n             obj_dir/system.v\n             obj_dir/system.sv\n%Error: data/full_repos/permissive/156721532/UART/setupSystem.v:20: Cannot find file containing module: 'PLL'\n PLL PLLUnit(\n ^~~\n%Error: Exiting due to 2 error(s)\n"
module setupSystem(CLOCK_50, SW, UART_TXD, UART_RXD, LEDR);
	input CLOCK_50;
	input [17:0]SW;
	output UART_TXD;
	input UART_RXD;
	output [17:0]LEDR;
	wire CLOCK_100;
	system systemUnit(
			 .clk(CLOCK_100),
			 .rst(SW[0]),
			 .TxD(UART_TXD),
			 .RxD(UART_RXD)
			);


	PLL PLLUnit(
					.areset(SW[0]),
					.inclk0(CLOCK_50),
					.c0(CLOCK_100),
					.locked(LEDR[0])
					);
endmodule
module setupSystem(CLOCK_50, SW, UART_TXD, UART_RXD, LEDR);

	input CLOCK_50;
	input [17:0]SW;
	output UART_TXD;
	input UART_RXD;
	output [17:0]LEDR;
	wire CLOCK_100;
	system systemUnit(
			 .clk(CLOCK_100),
			 .rst(SW[0]),
			 .TxD(UART_TXD),
			 .RxD(UART_RXD)
			);


	PLL PLLUnit(
					.areset(SW[0]),
					.inclk0(CLOCK_50),
					.c0(CLOCK_100),
					.locked(LEDR[0])
					);
endmodule