data/full_repos/permissive/1840016/lab4/add32.v
data/verilator_xmls/7bea3504-dff8-4253-ad7c-61de7442e319.xml
module add32(a, b, result);
  input [31:0] a, b;
  output [31:0] result;

  assign result = a + b;
endmodule
module add32(a, b, result);

  input [31:0] a, b;
  output [31:0] result;

  assign result = a + b;
endmodule