data/full_repos/permissive/205055389/test/verga/gatelevel.v
 line:24: before: "#"
1: b'%Error: data/full_repos/permissive/205055389/test/verga/gatelevel.v:10: Unsupported or unknown PLI call: $monitor\n        $monitor("%d\\t%b %b %b",$time,a,b,c);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/gatelevel.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #10 a = 0; b = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/gatelevel.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #10 a = 1; b = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/gatelevel.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #10 a = 1; b = 1;\n        ^\n%Error: data/full_repos/permissive/205055389/test/verga/gatelevel.v:24: syntax error, unexpected (-for-strength, expecting \'(\'\n  nand (highz1,strong0) #1 g1(Y1, A1, B1);\n        ^~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

    reg a,b;
    tri c,trash;

    SN7401 g1(a,a,a,a, b,b,b,b, c,trash,trash,trash);

    initial
      begin
        $monitor("%d\t%b %b %b",$time,a,b,c);
        a = 0; b = 0;
        #10 a = 0; b = 1;
        #10 a = 1; b = 0;
        #10 a = 1; b = 1;
      end

endmodule
module top;


    reg a,b;
    tri c,trash;

    SN7401 g1(a,a,a,a, b,b,b,b, c,trash,trash,trash);

    initial
      begin
        $monitor("%d\t%b %b %b",$time,a,b,c);
        a = 0; b = 0;
        #10 a = 0; b = 1;
        #10 a = 1; b = 0;
        #10 a = 1; b = 1;
      end

endmodule