data/full_repos/permissive/128659832/verilog/MEMORY.v
 line:44: before: "."
1: b"%Error: data/full_repos/permissive/128659832/verilog/MEMORY.v:34: Cannot find file containing module: 'mem_wrapper'\n    mem_wrapper #(  ) mem_wrapper0 (\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128659832/verilog,data/full_repos/permissive/128659832/mem_wrapper\n             data/full_repos/permissive/128659832/verilog,data/full_repos/permissive/128659832/mem_wrapper.v\n             data/full_repos/permissive/128659832/verilog,data/full_repos/permissive/128659832/mem_wrapper.sv\n             mem_wrapper\n             mem_wrapper.v\n             mem_wrapper.sv\n             obj_dir/mem_wrapper\n             obj_dir/mem_wrapper.v\n             obj_dir/mem_wrapper.sv\n%Error: Exiting due to 1 error(s)\n"
module MEMORY (
        input  wire [7:0] ADDR,
        input  wire       clk,
        input  wire [7:0] R,
        input  wire       srcA,
        input  wire       wM,
        input  wire       wAR,
        input  wire       mmio,
        input  wire       rst,
        output wire [7:0] M,
        output wire [7:0] o_leds
    );

    wire [7:0] AR_d;

    parameter ROMFILE = "";


    assign AR_d = ( srcA == 0 ) ? ADDR : M ;


    reg [7:0] AR_q;

    always @(posedge clk)
    begin
        if( wAR )
            AR_q <= AR_d;
        else
            AR_q <= AR_q;
    end

    mem_wrapper #(  ) mem_wrapper0 (
        .clk( clk ),
        .addr( AR_q ),
        .dout( M ),
        .write_en( wM ),
        .mmio( mmio ),
        .din( R ),
        .o_leds( o_leds ),
        .rst( rst )
    );
    defparam mem_wrapper0.ROMFILE = ROMFILE;

`ifndef SYNTHESIS
    always @(R)
       $display("%t DEBUG AR_q=%h", $time, AR_q);
    always @(M)
       $display("%t DEBUG M=%h", $time, M);
`endif

endmodule
module MEMORY (
        input  wire [7:0] ADDR,
        input  wire       clk,
        input  wire [7:0] R,
        input  wire       srcA,
        input  wire       wM,
        input  wire       wAR,
        input  wire       mmio,
        input  wire       rst,
        output wire [7:0] M,
        output wire [7:0] o_leds
    );


    wire [7:0] AR_d;

    parameter ROMFILE = "";


    assign AR_d = ( srcA == 0 ) ? ADDR : M ;


    reg [7:0] AR_q;

    always @(posedge clk)
    begin
        if( wAR )
            AR_q <= AR_d;
        else
            AR_q <= AR_q;
    end

    mem_wrapper #(  ) mem_wrapper0 (
        .clk( clk ),
        .addr( AR_q ),
        .dout( M ),
        .write_en( wM ),
        .mmio( mmio ),
        .din( R ),
        .o_leds( o_leds ),
        .rst( rst )
    );
    defparam mem_wrapper0.ROMFILE = ROMFILE;

`ifndef SYNTHESIS
    always @(R)
       $display("%t DEBUG AR_q=%h", $time, AR_q);
    always @(M)
       $display("%t DEBUG M=%h", $time, M);
`endif

endmodule