data/full_repos/permissive/161526648/ForwardUnit.v
data/verilator_xmls/079e57c1-811a-4393-ba56-32e3ada1b364.xml
module ForwardUnit(rt_ex,rs_ex,WriteReg_mem,WriteReg_wb,RegWrite_mem,RegWrite_wb,forward1,forward2);
	input [4:0] rt_ex,rs_ex,WriteReg_mem,WriteReg_wb;
	input RegWrite_mem,RegWrite_wb;
	output reg [1:0] forward1,forward2;

	always @ (rt_ex or rs_ex or WriteReg_mem or WriteReg_wb or RegWrite_mem or RegWrite_wb) begin
	if ((WriteReg_mem == rs_ex) && (RegWrite_mem==1) && (WriteReg_mem != 0))
			forward1 <= 2'b10;
	else if ((WriteReg_wb == rs_ex) && (RegWrite_wb==1) && (WriteReg_wb!=0))
	      forward1 <= 2'b01;
	else 
	      forward1 <= 2'b00;
			
	if ((WriteReg_mem == rt_ex) && (RegWrite_mem==1) && (WriteReg_mem != 0))
			forward2 <= 2'b10;
	else if ((WriteReg_wb == rt_ex) && (RegWrite_wb==1) && (WriteReg_wb!=0))
	      forward2 <= 2'b01;
	else 
	      forward2 <= 2'b00;
	end	
endmodule
module ForwardUnit(rt_ex,rs_ex,WriteReg_mem,WriteReg_wb,RegWrite_mem,RegWrite_wb,forward1,forward2);

	input [4:0] rt_ex,rs_ex,WriteReg_mem,WriteReg_wb;
	input RegWrite_mem,RegWrite_wb;
	output reg [1:0] forward1,forward2;

	always @ (rt_ex or rs_ex or WriteReg_mem or WriteReg_wb or RegWrite_mem or RegWrite_wb) begin
	if ((WriteReg_mem == rs_ex) && (RegWrite_mem==1) && (WriteReg_mem != 0))
			forward1 <= 2'b10;
	else if ((WriteReg_wb == rs_ex) && (RegWrite_wb==1) && (WriteReg_wb!=0))
	      forward1 <= 2'b01;
	else 
	      forward1 <= 2'b00;
			
	if ((WriteReg_mem == rt_ex) && (RegWrite_mem==1) && (WriteReg_mem != 0))
			forward2 <= 2'b10;
	else if ((WriteReg_wb == rt_ex) && (RegWrite_wb==1) && (WriteReg_wb!=0))
	      forward2 <= 2'b01;
	else 
	      forward2 <= 2'b00;
	end	
endmodule