data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:160: Unsupported: Ignoring delay on this delayed statement.\n  #5000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:170: Unsupported: Ignoring delay on this delayed statement.\n  #30;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:127: Cell has missing pin: \'local_clock509_in_p\'\n mza_test028_pll_509divider_and_revo_encoder_althea uut (\n                                                    ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:127: Cell has missing pin: \'local_clock509_in_n\'\n mza_test028_pll_509divider_and_revo_encoder_althea uut (\n                                                    ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:183: Multiple top level modules\n                                                                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                                                                 : ... Top module \'mything_tb\'\nmodule mything_tb;\n       ^~~~~~~~~~\n                                                                                                                                 : ... Top module \'mza_test028_pll_509divider_and_revo_encoder_althea_top\'\nmodule mza_test028_pll_509divider_and_revo_encoder_althea_top (\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:36: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS remote_input_clock_instance (.I(remote_clock509_in_p), .IB(remote_clock509_in_n), .O(remote_clock509));\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.sv\n             IBUFGDS\n             IBUFGDS.v\n             IBUFGDS.sv\n             obj_dir/IBUFGDS\n             obj_dir/IBUFGDS.v\n             obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:37: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS local_input_clock_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(local_clock509));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:42: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS trigger_input_instance (.I(remote_revo_in_p), .IB(remote_revo_in_n), .O(rawtrg));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:61: Cannot find file containing module: \'simplepll_BASE\'\n simplepll_BASE #(.OVERALL_DIVIDE(2), .MULTIPLY(4), .DIVIDE1(8), .DIVIDE2(4), .PERIOD(1.965), .COMPENSATION("INTERNAL")) mypll (.clockin(clock509), .reset(reset), .clock1out(rawclock127), .clock1out180(rawclock127b), .clock2out(rawclock254), .clock2out180(rawclock254b), .locked(locked));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:64: Cannot find file containing module: \'BUFG\'\n BUFG mybufg1 (.I(rawclock127), .O(clock127));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:65: Cannot find file containing module: \'BUFG\'\n BUFG mybufg2 (.I(rawclock127b), .O(clock127b));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:68: Cannot find file containing module: \'BUFG\'\n BUFG mybufg3 (.I(rawclock254), .O(clock254));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:69: Cannot find file containing module: \'BUFG\'\n BUFG mybufg4 (.I(rawclock254b), .O(clock254b));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:84: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut1 (.C0(clock127), .C1(clock127b), .CE(1\'b1), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr1));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:85: Cannot find file containing module: \'OBUFDS\'\n OBUFDS supercool (.I(clock127oddr1), .O(clock127_out_p), .OB(clock127_out_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:87: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut2 (.C0(clock127), .C1(clock127b), .CE(~trg),  .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr2));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:88: Cannot find file containing module: \'OBUFDS\'\n OBUFDS grouch2 (.I(clock127oddr2), .O(trg_out_p), .OB(trg_out_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:98: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut3 (.C0(clock127), .C1(clock127b), .CE(1\'b1), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr3));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:99: Cannot find file containing module: \'OBUFDS\'\n OBUFDS outa (.I(clock127oddr3), .O(outa_p), .OB(outa_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:100: Cannot find file containing module: \'OBUFDS\'\n OBUFDS out1 (.I(trg), .O(out1_p), .OB(out1_n));\n ^~~~~~\n%Error: Exiting due to 15 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mza_test028_pll_509divider_and_revo_encoder_althea (
	input local_clock509_in_p,
	input local_clock509_in_n,
	input remote_clock509_in_p,
	input remote_clock509_in_n,
	input remote_revo_in_p,
	input remote_revo_in_n,
	output clock127_out_p,
	output clock127_out_n,
	output trg_out_p,
	output trg_out_n,
	output out1_p,
	output out1_n,
	output outa_p,
	output outa_n,
	output led_0,
	output led_1,
	output led_2,
	output led_3,
	output led_4,
	output led_5,
	output led_6,
	output led_7
);
	wire remote_clock509;
	wire local_clock509;
	wire clock509;
	IBUFGDS remote_input_clock_instance (.I(remote_clock509_in_p), .IB(remote_clock509_in_n), .O(remote_clock509));
	IBUFGDS local_input_clock_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(local_clock509));
	assign clock509 = remote_clock509;
	reg reset = 1;
	reg [12:0] reset_counter = 0;
	wire rawtrg;
	IBUFGDS trigger_input_instance (.I(remote_revo_in_p), .IB(remote_revo_in_n), .O(rawtrg));
	parameter TRGSTREAM_WIDTH = 16;
	parameter TRG_MAX_DURATION = 8;
	reg [TRGSTREAM_WIDTH-1:0] trgstream = 0;
	reg [TRGSTREAM_WIDTH-TRG_MAX_DURATION-1:0] upper;
	reg [TRG_MAX_DURATION-1:0] lower;
	always @(posedge clock509) begin
		if (reset) begin
			if (reset_counter[10]) begin
				reset <= 0;
			end
			reset_counter <= reset_counter + 1'b1;
		end
	end
	wire rawclock127;
	wire rawclock127b;
	wire rawclock254;
	wire rawclock254b;
	wire locked;
	simplepll_BASE #(.OVERALL_DIVIDE(2), .MULTIPLY(4), .DIVIDE1(8), .DIVIDE2(4), .PERIOD(1.965), .COMPENSATION("INTERNAL")) mypll (.clockin(clock509), .reset(reset), .clock1out(rawclock127), .clock1out180(rawclock127b), .clock2out(rawclock254), .clock2out180(rawclock254b), .locked(locked));
	wire clock127;
	wire clock127b;
	BUFG mybufg1 (.I(rawclock127), .O(clock127));
	BUFG mybufg2 (.I(rawclock127b), .O(clock127b));
	wire clock254;
	wire clock254b;
	BUFG mybufg3 (.I(rawclock254), .O(clock254));
	BUFG mybufg4 (.I(rawclock254b), .O(clock254b));
	reg trg = 0;
	always @(posedge clock254) begin
		trgstream <= { trgstream[TRGSTREAM_WIDTH-2:0], rawtrg };


		trg <= 0;

		if (upper==0 & lower!=0) begin
			trg <= 1;
		end
		upper <= trgstream[TRGSTREAM_WIDTH-1:TRG_MAX_DURATION];
		lower <= trgstream[TRG_MAX_DURATION-1:0];
	end
	wire clock127oddr1;
	ODDR2 doughnut1 (.C0(clock127), .C1(clock127b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr1));
	OBUFDS supercool (.I(clock127oddr1), .O(clock127_out_p), .OB(clock127_out_n));
	wire clock127oddr2;
	ODDR2 doughnut2 (.C0(clock127), .C1(clock127b), .CE(~trg),  .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr2));
	OBUFDS grouch2 (.I(clock127oddr2), .O(trg_out_p), .OB(trg_out_n));
	assign led_7 = reset;
	assign led_6 = 0;
	assign led_5 = 0;
	assign led_4 = trg;
	assign led_3 = 0;
	assign led_2 = reset_counter[12];
	assign led_1 = 0;
	assign led_0 = locked;
	wire clock127oddr3;
	ODDR2 doughnut3 (.C0(clock127), .C1(clock127b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr3));
	OBUFDS outa (.I(clock127oddr3), .O(outa_p), .OB(outa_n));
	OBUFDS out1 (.I(trg), .O(out1_p), .OB(out1_n));
endmodule
module mza_test028_pll_509divider_and_revo_encoder_althea (
	input local_clock509_in_p,
	input local_clock509_in_n,
	input remote_clock509_in_p,
	input remote_clock509_in_n,
	input remote_revo_in_p,
	input remote_revo_in_n,
	output clock127_out_p,
	output clock127_out_n,
	output trg_out_p,
	output trg_out_n,
	output out1_p,
	output out1_n,
	output outa_p,
	output outa_n,
	output led_0,
	output led_1,
	output led_2,
	output led_3,
	output led_4,
	output led_5,
	output led_6,
	output led_7
);

	wire remote_clock509;
	wire local_clock509;
	wire clock509;
	IBUFGDS remote_input_clock_instance (.I(remote_clock509_in_p), .IB(remote_clock509_in_n), .O(remote_clock509));
	IBUFGDS local_input_clock_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(local_clock509));
	assign clock509 = remote_clock509;
	reg reset = 1;
	reg [12:0] reset_counter = 0;
	wire rawtrg;
	IBUFGDS trigger_input_instance (.I(remote_revo_in_p), .IB(remote_revo_in_n), .O(rawtrg));
	parameter TRGSTREAM_WIDTH = 16;
	parameter TRG_MAX_DURATION = 8;
	reg [TRGSTREAM_WIDTH-1:0] trgstream = 0;
	reg [TRGSTREAM_WIDTH-TRG_MAX_DURATION-1:0] upper;
	reg [TRG_MAX_DURATION-1:0] lower;
	always @(posedge clock509) begin
		if (reset) begin
			if (reset_counter[10]) begin
				reset <= 0;
			end
			reset_counter <= reset_counter + 1'b1;
		end
	end
	wire rawclock127;
	wire rawclock127b;
	wire rawclock254;
	wire rawclock254b;
	wire locked;
	simplepll_BASE #(.OVERALL_DIVIDE(2), .MULTIPLY(4), .DIVIDE1(8), .DIVIDE2(4), .PERIOD(1.965), .COMPENSATION("INTERNAL")) mypll (.clockin(clock509), .reset(reset), .clock1out(rawclock127), .clock1out180(rawclock127b), .clock2out(rawclock254), .clock2out180(rawclock254b), .locked(locked));
	wire clock127;
	wire clock127b;
	BUFG mybufg1 (.I(rawclock127), .O(clock127));
	BUFG mybufg2 (.I(rawclock127b), .O(clock127b));
	wire clock254;
	wire clock254b;
	BUFG mybufg3 (.I(rawclock254), .O(clock254));
	BUFG mybufg4 (.I(rawclock254b), .O(clock254b));
	reg trg = 0;
	always @(posedge clock254) begin
		trgstream <= { trgstream[TRGSTREAM_WIDTH-2:0], rawtrg };


		trg <= 0;

		if (upper==0 & lower!=0) begin
			trg <= 1;
		end
		upper <= trgstream[TRGSTREAM_WIDTH-1:TRG_MAX_DURATION];
		lower <= trgstream[TRG_MAX_DURATION-1:0];
	end
	wire clock127oddr1;
	ODDR2 doughnut1 (.C0(clock127), .C1(clock127b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr1));
	OBUFDS supercool (.I(clock127oddr1), .O(clock127_out_p), .OB(clock127_out_n));
	wire clock127oddr2;
	ODDR2 doughnut2 (.C0(clock127), .C1(clock127b), .CE(~trg),  .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr2));
	OBUFDS grouch2 (.I(clock127oddr2), .O(trg_out_p), .OB(trg_out_n));
	assign led_7 = reset;
	assign led_6 = 0;
	assign led_5 = 0;
	assign led_4 = trg;
	assign led_3 = 0;
	assign led_2 = reset_counter[12];
	assign led_1 = 0;
	assign led_0 = locked;
	wire clock127oddr3;
	ODDR2 doughnut3 (.C0(clock127), .C1(clock127b), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr3));
	OBUFDS outa (.I(clock127oddr3), .O(outa_p), .OB(outa_n));
	OBUFDS out1 (.I(trg), .O(out1_p), .OB(out1_n));
endmodule